Display device and method for controlling independently by a group of pixels

A display driver integrated circuit may include a controller configured to receive first image data from an application processor positioned outside the display driver integrated circuit and a data driver configured to receive the first image data from the controller.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0151969, filed on Nov. 15, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein its entirety.

BACKGROUND

The present disclosure relates to a technology for charging pixels included in a display.

2. Description of Related Art

An electronic device, which is equipped with a display, such as a smartphone, a wearable device, or the like has been widely supplied as mobile communication technologies develop. A user may execute various functions such as a photo or video capturing function, a music or video file playing function, a game function, an Internet function, and the like through a screen output from the display.

As the demand for clearer and cleaner screens increases, the display with high resolution (e.g., 2560×1440) has been distributed increasingly. That is, when the number of pixels included in the display increases, the display may provide a user with the clearer and cleaner screen.

However, when the number of pixels increases, a display driver integrated circuit may not have enough time to charge each of the pixels. As such, it may be difficult for the display driver integrated circuit to charge the pixels to the voltage level required by each of the pixels. The voltage level lower than the voltage level required by each of the pixels may distort the screen or may cause a flicker phenomenon.

In addition, when the number of pixels increases, the amount of data to be processed by the display driver integrated circuit may increase. The increase of the data may slow the driving speed of the display.

SUMMARY

Aspects of the present disclosure are provided to address at least the above-mentioned problems and/or disadvantages and provide at least the advantages described below. Accordingly, an aspect of the present disclosure is to provide an electronic device (e.g., a display device or a portable communication device including the same), and a method of controlling the same for addressing the above-described problem and problems brought up in this disclosure.

In accordance with an aspect of the present disclosure, a display driver integrated circuit may include a controller configured to receive first image data from an application processor disposed outside the display driver integrated circuit, and a data driver configured to receive the first image data from the controller. The data driver may include a group of shift registers configured to convert the first image data to second image data, a first group of latches configured to receive the second image data from the group of shift registers to store the second image data, a second group of latches configured to receive the second image data from the first group of latches to store the second image data, a group of converters configured to convert a first portion or a second portion of the second image data into a data voltage for causing at least part of pixels of a pixel group corresponding to a first pixel group and a second pixel group to display light, and a group of amplifiers configured to output the data voltage to the at least part of the pixels. Before transmission of the second image data from the first group of latches to the second group of latches is completed, the controller may be configured to cause the second group of latches to transmit a portion of the second image data, the transmission to the second group of latches of which is completed, among the first portion of the second image data and the second portion of the second image data to the converters. The group of shift registers may include a first shift register corresponding to a first pixel group of at least one pixel line of a display panel connected to the display driver integrated circuit, and a second shift register corresponding to a second pixel group of the at least one pixel line. The first group of latches may include a first latch configured to store a first portion of the second image data received from the first shift register, and a second latch configured to store a second portion of the second image data received from the second shift register. The second group of latches may include a third latch configured to store the first portion received from the first latch, and a fourth latch configured to store the second portion received from the second latch.

In accordance with another aspect of the present disclosure, a display may include a display panel in which a plurality of pixels and at least one pixel line electrically connected to each of the pixels are disposed and a display driver integrated circuit electrically connected to the at least one pixel line. The display driver integrated circuit may include a timing controller configured to receive first image data from an application processor; and a data driver including a group of shift registers configured to convert the first image data to second image data, a first group of latches configured to receive the second image data from the group of shift registers to store the second image data, a group of converters configured to convert the second image data to a data voltage for causing the pixels to display light, a group of amplifiers configured to output the data voltage to the display panel, and a second group of latches configured to receive the second image data from the first group of latches to transmit the second image data to the group of converters. The timing controller may be configured to cause the second group of latches to transmit the stored second image data to the group of converters during a time interval in which the first group of latches stores the second image data.

In accordance with another aspect of the present disclosure, an electronic device may include a display panel including a plurality of pixel lines, a display driver integrated circuit, and a processor. The processor may be configured to supply a plurality of signals corresponding to a first portion of the display data to the first pixel group using a first switch at a first point in time and to supply a plurality of signals corresponding to a second portion of the display data to a second pixel group using a second switch at a second point in time. At least one pixel line among the plurality of pixel lines may include a first pixel group connected to a first transmission line and a second pixel group connected to a second transmission line. The display driver integrated circuit may include a storage circuit configured to at least temporarily store display data to be displayed through the at least one pixel line, at least one first source amplifier connected to the first pixel group and at least one second source amplifier connected to the second pixel group, a first decoder connected to the first source amplifier and a second decoder connected to the second source amplifier, at least one first switch configured to control a connection between the first source amplifier and the first pixel group and at least one second switch configured to control a connection between the second source amplifier and the second pixel group.

According to various example embodiments of the present disclosure, it is possible to provide a user with a clear screen. Furthermore, according to various example embodiments of the present disclosure, it is possible to enhance a display driving speed.

A variety of effects directly or indirectly understood through this disclosure may be provided.

DETAILED DESCRIPTION

FIG. 1illustrates a block diagram illustrating a display in which a display driver integrated circuit and a display panel are simplified, according to an embodiment. A display driver integrated circuit (DDI) (e.g., including display driving circuitry)100and a display panel200that are illustrated inFIG. 1may be included in an electronic device601illustrated inFIG. 6.

Referring toFIG. 1, the DDI100may be electrically connected to lines disposed on the display panel200. For example, the DDI100may be connected to gate lines201,202,203, and204and data lines (not illustrated) (or pixel lines). The DDI100may transmit (e.g., forward) various kinds of signals through the gate lines201,202,203, and204and the data lines and may cause pixels210connected to the gate lines201,202,203, and204and the data lines to emit light or put pixels in a state to emit light (e.g., to display light).

According to an embodiment, the DDI100may include a timing controller110(or a controller), a gate driver (e.g., including gate driving circuitry)120, and a data driver (e.g., including data driving circuitry)130.

The timing controller110may receive control information and first image data from a processor (e.g., an application processor (not shown)). The control information may refer, for example, to data for controlling components included in the DDI100or for selecting the first image data. The first image data may refer to data associated with an image output through the display panel200.

The timing controller110may generate a clock based on the control information. The clock may refer to electrical vibration applied to the components for the purpose of operating the components (e.g., the gate driver120, and the data driver130) included in the DDI100at a specified (e.g., constant) speed. The components may operate based on the clock generated by the timing controller110.

The timing controller110may generate a gate control signal GCS for controlling the gate driver120. The gate control signal may include a signal for controlling a point in time when the gate driver120applies a voltage to the gate lines201,202,203, and204, a signal for controlling a period in which the voltage is applied, or the like. The gate driver120may apply a gate voltage to the gate lines201,202,203, and204based on the gate control signal. For example, the gate driver120may apply the gate voltage in order of the ‘N’ line201, the ‘N+1’ line202, the ‘N+2’ line203, and the ‘N+3’ line204. Transistors included in the pixels210may be turned on by the gate voltage. In the present disclosure, the gate driver120may be referred to, for example, as a “scan driver”.

The timing controller110may transmit the first image data to the data driver130. The data driver130may convert the first image data to second image data. The second image data may refer, for example, to data obtained by parallelizing the first image data. In the present disclosure, the data driver130may be referred to, for example, as a “source driver”.

The data driver130may convert the second image data into a data voltage. The data voltage may refer to a voltage capable of charging a capacitive element (e.g., a capacitor) included in the pixels210. When the capacitive element is charged and then a current flows into, for example, an organic light-emitting diode (OLED) by the charged voltage, the pixels210may emit light.

FIG. 2is a block diagram illustrating a data driver, according to an embodiment.

Referring toFIG. 2, the data driver130may include a group of shift registers131, a first group of latches132(or a first group of storage circuits), a second group of latches133(or a second group of storage circuits), a group of digital analog converters134(or a group of decoders), a group of gamma blocks135, a group of amplifiers136, and a group of switches137.

The group of shift registers131may receive first image data from the timing controller110. The group of shift registers131may convert the first image data to second image data.

The first group of latches132may sequentially store the second image data received from the group of shift registers131. For example, the first group of latches132may store the second image data in order from the second image data to be output to the left side of the ‘N’ line201to the second image data to be output to the right side of the ‘N’ line201, or vice versa. When the second image data corresponding to the ‘N’ line201is stored completely, the first group of latches132may store the second image data to be output through the ‘N+1’ line202. At this time, the first group of latches132may store the second image data in order from the second image data to be output to the left side of the ‘N+1’ line202to the second image data to be output to the right side of the ‘N+1’ line202, or vice versa.

While the first group of latches132stores the second image data for each line, the second group of latches133may transmit the second image data of the corresponding line to the group of digital analog converters134. For example, while the first group of latches132stores the second image data of the ‘N’ line201, the second group of latches133may transmit the second image data, which is stored in the first group of latches132, of the ‘N’ line201, to the group of digital analog converters134. For another example, while the first group of latches132stores the second image data of the ‘N+1’ line202, the second group of latches133may transmit the second image data, which is stored in the first group of latches132, of the ‘N+1’ line202, to the group of digital analog converters134.

The group of gamma blocks135may apply a gray scale voltage to the group of digital analog converters134. The gray scale voltage may refer, for example, to a voltage for correcting the sensitivity of the user's eyes. For example, even though the brightness of light emitted from a pixel changes linearly, the user may feel the change in brightness of the light nonlinearly. The gray scale voltage may refer, for example, to a voltage for correcting the above-mentioned nonlinear characteristic.

The group of digital analog converters134may convert the second image data, which is received from the second group of latches133, into a data voltage based on the gray scale voltage received from the group of gamma blocks135. The data voltage may charge a capacitive element (e.g., a capacitor) included in the pixels210, as the voltage applied to the pixels210.

The group of amplifiers136may output the data voltage received from the group of digital analog converters134, to the display panel200. For example, when the data voltage applied to an input terminal (e.g., a terminal between the group of digital analog converters134and the group of amplifiers136) of the group of amplifiers136is not less than a specific level, the group of amplifiers136may output the data voltage that is not less than the specific level.

The group of switches137may be opened or closed and thus may adjust the timing at which the data voltage is output to the display panel200. For example, when the group of switches137is opened, the data voltage may not be transmitted to the display panel200; when the group of switches137is closed, the data voltage may be transmitted to the display panel200. In the present disclosure, the group of switches137may be referred to, for example, as a “group of source output switches”137.

In accordance with the DDI based on a comparison example, a second group of latches may transmit the second image data stored in a first group of latches to a converter for each line. For example, after transmitting the second image data to be output through the ‘N’ line201to a group of digital analog converters, the second group of latches may transmit the second image data to be output through the ‘N+1’ line202to a group of digital analog converters. In accordance with the DDI based on the comparison example, since the second group of latches transmits the second image data corresponding to a line to a group of digital analog converters at a time, the amount of data to be processed by a group of digital analog converters may increase; it is understood that the load of a gamma block may increase in response to the data processing of the group of digital analog converters. The increase of the data may decrease the voltage level of the input terminal (e.g., a terminal between a group of digital analog converters and a group of amplifiers) of a group of amplifiers or may increase a time interval in which the voltage level increases to a specific level. As such, a flicker phenomenon may occur on the screen output through a display panel, or the screen output speed may be slow.

However, according to an embodiment of the present disclosure, while the first group of latches132stores the second image data for each line, the second group of latches133may transmit the second image data of the corresponding line to the group of digital analog converters134. In other words, since the second group of latches133transmits a part of the stored second image data to the group of digital analog converters134without transmitting a large amount of second image data to the group of digital analog converters134at a time, the load of the group of digital analog converters134or the group of gamma blocks135may decrease. As such, the voltage level of the input terminal of the group of amplifiers136may increase to be greater than or equal to a specific range within a specified time interval (or a time required such that the voltage level of the input terminal of the group of amplifiers136increases to be greater than or equal to a specific range may be reduced). According to an embodiment of the present disclosure, the voltage level of the input terminal of the group of amplifiers136increases to be greater than or equal to a specific level within a specified time interval, thereby preventing and/or reducing a flicker phenomenon and increasing a display driving speed.

According to an embodiment, the timing controller110may sense a voltage of the input terminal of the group of amplifiers136. When the sensed voltage is not greater than a specific level, the timing controller110may cause the second group of latches133to transmit the second image data to the group of digital analog converters134. For example, when the voltage of the input terminal of the group of amplifiers136is not greater than the specific level, the timing controller110may transmit the second image data, and thus may rapidly increase the voltage of the input terminal of the group of amplifiers136to be greater than or equal to the specific level.

In the present disclosure, a description given with reference toFIGS. 1 and 2may be applied to components that have the same reference marks as the DDI100and the display panel200illustrated inFIGS. 1 and 2.

FIG. 3is a diagram illustrating an enlarged view of a display panel and a data driver, according to an embodiment.FIG. 3illustrates the combination relationship between the lines disposed in the display panel200and the data driver130.

Referring toFIG. 3, the group of shift registers131may include a plurality of registers131a,131b, and131c; the group of digital analog converters134may include a plurality of converters134a,134b, and134c; the group of amplifiers136may include a plurality of amplifiers136a,136b, and136c; and the group of switches137may include a plurality of switches137a,137b, and137c.

The first group of latches132may include a first latch132a, a second latch132b, and a third latch132c, and the second group of latches133may include a fourth latch133a, a fifth latch133b, and a sixth latch133c. According to an embodiment, the latches132a,132b, and132cincluded in the first group of latches132and the latches133a,133b, and133cincluded in the second group of latches133may be different kinds of latches. For example, the latches132a,132b, and132cincluded in the first group of latches132may store second image data received from the group of shift registers131simply. On the other hand, after receiving and storing the second image data from the first group of latches132, the latches133a,133b, and133cincluded in the second group of latches133may transmit the second image data to the group of digital analog converters134.

According to an embodiment, the eight converters134amay be connected to one latch (e.g.,133a) included in the second group of latches133, and one amplifier may be connected to each of converters. One switch may be connected to each of amplifiers, and each of the amplifiers may be selectively connected to a specified sub pixel by using the connected switch. The above-described connection relationship is simply an example, and the scope of the embodiment of the present disclosure is not limited to the connection relationship illustrated inFIG. 3. For example, six converters may be connected to one latch (e.g.,133a).

The group of shift registers131a,131b, and131cmay convert first image data received from the timing controller110, to the second image data.

The first group of latches132a,132b, and132cmay receive the second image data from the group of shift registers131a,131b, and131cand may store the second image data for each line. For example, after storing image data corresponding to the ‘N’ line201, the first group of latches132a,132b, and132cmay store image data corresponding to the ‘N+1’ line202.

While the first group of latches132a,132b, and132cstore the image data for each line, the second group of latches133a,133b, and133cmay transmit the second image data received from the first group of latches132a,132b, and132c, to the group of digital analog converters134a,134b, and134c. For example, the first latch132amay store second image data, which is to be output through first data lines211included in a first group, from among pieces of second image data corresponding to the ‘N’ line201. The second latch132bmay store second image data, which is to be output through second data lines212included in a second group, from among the pieces of second image data corresponding to the ‘N’ line201. The fourth latch133amay transmit second image data to be output through the first data lines211to the converters134a. In other words, while the second latch132bstores second image data to be output through the second data lines212, the fourth latch133amay transmit second image data to be output through the first data lines211, to the converters134a. The converters134amay convert the second image data to be output through the first data lines211, to a data voltage based on the gray scale voltage received from the group of gamma blocks135.

The above-mentioned details may be also applied to an operation in which the third latch132cstores second image data to be output through third data lines213included in a third group. For example, while the third latch132cstores second image data to be output through the third data lines213, the fifth latch133bmay transmit second image data to be output through the second data lines212, to the converters134b. The converters134bmay convert second image data to be output through the second data lines212, to a data voltage based on the gray scale voltage received from the group of gamma blocks135.

When the voltage of an input terminal increases to be greater than or equal to a specific level, the group of amplifiers136a,136b, and136cmay output the data voltage to the group of switches137a,137b, and137c.

The group of switches137a,137b, and137cmay be opened or closed and thus may adjust the timing at which the data voltage is output to the display panel200. For example, when the switches137aare closed, the data voltage may be transmitted to sub pixels connected to the ‘N’ line201and the first data lines211. For another example, when the switches137bare closed, the data voltage may be transmitted to sub pixels connected to the ‘N’ line201and the second data lines212.

When the processing of the second image data corresponding to the ‘N’ line201is completed, the first latch132amay store second image data, which is to be output through the first data lines211, from among pieces of second image data corresponding to the ‘N+1’ line202. Next, the second latch132bmay store second image data, which is to be output through the second data lines212, from among the pieces of second image data corresponding to the ‘N+1’ line202. At this time, the fourth latch133amay transmit second image data to be output through the first data lines211to the converters134a. In other words, while the second latch132bstores second image data to be output through the second data lines212, the fourth latch133amay transmit second image data to be output through the first data lines211, to the converters134a. The converters134amay convert second image data to be output through the first data lines211, to a data voltage based on the gray scale voltage received from the group of gamma blocks135.

The above-mentioned procedure may be also applied to an operation in which the third latch132cstores second image data to be output through the third data lines213. For example, while the third latch132cstores second image data to be output through the third data lines213, the fifth latch133bmay transmit second image data to be output through the second data lines212, to the converters134b. The converters134bmay convert second image data to be output through the second data lines212, to a data voltage based on the gray scale voltage received from the group of gamma blocks135.

When the voltage of an input terminal increases to be greater than or equal to a specific level, the group of amplifiers136a,136b, and136cmay output the data voltage to the group of switches137a,137b, and137c.

The group of switches137a,137b, and137cmay be opened or closed and thus may adjust the timing at which the data voltage is output to the display panel200. For example, when the switches137aare closed, the data voltage may be transmitted to sub pixels connected to the ‘N+1’ line202and the first data lines211. For another example, when the switches137bare closed, the data voltage may be transmitted to sub pixels connected to the ‘N+1’ line202and the second data lines212.

FIG. 4Ais a diagram illustrating a timing, according to an embodiment.FIG. 4Aillustrates the operation timing of each of the components illustrated inFIG. 3.

Referring toFIG. 4A, a synchronization signal HSYNC may be a clock generated by the timing controller110. The components included in the DDI100may operate based on the synchronization signal HSYNC.

A first gate control signal GCS1and a second gate control signal GCS2may be a signal applied to the ‘N’ line201and the ‘N+1’ line202, respectively. Next, the first gate control signal GCS1and the second gate control signal GCS2may be applied to the ‘N+2’ line203and the ‘N+3’ line204, respectively. Transistors connected to the ‘N’ line201, the ‘N+1’ line202, the ‘N+2’ line203, and the ‘N+3’ line204may be turned on by the first gate control signal GCS1and the second gate control signal GCS2.

A graph410may indicate whether image data is stored in the first group of latches132. In the graph410, a high level indicates a state where the image data is stored in the first group of latches132; a low level indicates a state where the image data is not stored in the first group of latches132.

A graph420indicates the operation timing of the second group of latches133. In the graph420, a high level indicates a state where the second group of latches133transmits image data stored in the first group of latches132to the group of digital analog converters134(e.g.,134a,134b, or134c); a low level indicates a state where the second group of latches133does not transmit the image data.

A graph430indicates the voltage of the input terminal (e.g., the terminal or wiring between the group of digital analog converters134and the group of amplifiers136) of the group of amplifiers136; and a graph440indicates the data voltage of an output terminal of the group of amplifiers136.

A graph450indicates whether the group of switches137is opened or closed. In the graph450, a high level indicates that the group of switches137is closed; a low level indicates that the group of switches137is opened.

A graph460indicates the voltage input to the display panel200.

Referring to the graph410, the first group of latches132may receive second image data from the group of shift registers131to store the second image data for each line. For example, after storing the second image data corresponding to the ‘N+1’ line202, the first group of latches132may store the second image data corresponding to the ‘N+2’ line203. Next, the first group of latches132may store second image data corresponding to the ‘N+3’ line204.

Referring to the graph420, while the first group of latches132stores second image data for each line, the second group of latches133may transmit the second image data stored in the first group of latches132, to the group of digital analog converters134. For example, while the first group of latches132stores second image data corresponding to the ‘N+1’ line202, the second group of latches133may transmit second image data, which is stored in the first group of latches132and which corresponds to the ‘N+1’ line202, to the group of digital analog converters134.

According to an embodiment, while the first group of latches132stores second image data corresponding to the ‘N+1’ line202, the second group of latches133may operate at least once or a plurality of times. For example, while the first group of latches132stores the second image data corresponding to the ‘N+1’ line202, the second group of latches133may transmit a part of the second image data stored in the first group of latches132to the group of digital analog converters134in twice. The above-described number of times that the second group of latches133operates is exemplary, and the scope of the embodiment of the present disclosure is not limited to the specific number of times.

Referring to the graph430, since the second group of latches133transmits a part of the second image data stored in the first group of latches132to the group of digital analog converters134a plurality of times, the voltage of the input terminal of the group of amplifiers136may increase or decrease repeatedly. For example, whenever the second group of latches133transmits the second image data, the voltage of the input terminal of the group of amplifiers136may increase. On the other hand, when the second group of latches133does not transmit the second image data, the voltage of the input terminal of the group of amplifiers136may decrease.

Referring to the graph440, while the first group of latches132stores the second image data, the data voltage may be output through the output terminal of the group of amplifiers136. In other words, while the first group of latches132stores the second image data, the second group of latches133may transmit the second image data stored in the first group of latches132, to the group of digital analog converters134. The group of digital analog converters134may convert the second image data into a data voltage based on a gray scale voltage, and the converted data voltage may be output through the output terminal of the group of amplifiers136. As such, while the first group of latches132stores the second image data, the data voltage may be output to the output terminal of the group of amplifiers136.

Referring to the graph450and the graph460, the timing at which the data voltage is output to the display panel200may be changed depending on the event that the group of switches137is opened or closed. For example, during at least part of a time interval in which the first group of latches132stores the second image data, the group of switches137may be closed. On the other hand, while the second group of latches133transmits the second image data to the group of digital analog converters134, the group of switches137may be opened. Since the group of switches137is opened, the data voltage may not be outputted to the display panel200. For another example, the group of switches137may be closed in synchronization with the synchronization signal HSYNC. When the group of switches137is closed, the data voltage may be output to the display panel200.

FIG. 4Bis a timing diagram, according to another embodiment. In comparison withFIG. 4BandFIG. 4A, a gate control signal and the timing at which the gate control signal is applied to gate lines may be different. InFIG. 4A, details about the remaining components other than the gate control signal may be identically applied toFIG. 4B.

Referring toFIG. 4B, a first gate control signal GCS1, a second gate control signal GCS2, and a third gate control signal GCS3may be sequentially applied to gate lines. For example, the first gate control signal GCS1, the second gate control signal GCS2, and the third gate control signal GCS3may be applied to the ‘N’ line201, the ‘N+1’ line202, and the ‘N+2’ line203, respectively. Next, the first gate control signal GCS1, the second gate control signal GCS2, and the third gate control signal GCS3may be applied to the ‘N+3’ line204, an ‘N+4’ line, and an ‘N+5’ line, respectively. Transistors connected to the ‘N’ line201, the ‘N+1’ line202, the ‘N+2’ line203, the ‘N+3’ line204, the ‘N+4’ line, and the ‘N+5’ line may be sequentially turned on by the first gate control signal GCS1, the second gate control signal GCS2, and the third gate control signal GCS3.

Although not illustrated inFIG. 4B, a fourth gate control signal may be sequentially applied to gate lines. In this case, the first gate control signal GCS1, the second gate control signal GCS2, the third gate control signal GCS3, and the fourth gate control signal may be applied to the ‘N’ line201, the ‘N+1’ line202, the ‘N+2’ line203, and the ‘N+3’ line204, respectively. Transistors connected to the ‘N’ line201, the ‘N+1’ line202, the ‘N+2’ line203, and the ‘N+3’ line204may be sequentially turned on by the first gate control signal GCS1, the second gate control signal GCS2, the third gate control signal GCS3, and the fourth gate signal. The number of gate control signals illustrated inFIGS. 4A and 4Bis exemplary, and embodiments of the present disclosure are not limited toFIGS. 4A and 4B.

FIG. 5Ais a diagram illustrating a structure of a pixel, according to an embodiment.FIG. 5Billustrates a structure of a pixel, according to another embodiment.

Referring toFIG. 5A, sub pixels511,512,513, and514may be disposed on the ‘N’ line201(or on the ‘N+1’ line202) in order of the red sub pixel511, the green sub pixel512, the blue sub pixel513, the green sub pixel514, and a red sub pixel (not shown). The structure illustrated inFIG. 5Amay be referred to as a “pentile layout”, as a structure applied to the embodiment illustrated inFIG. 3. In this case, one pixel structure510or520may include four sub pixels511,512,513, and514, or521,522,523, and524. In the meantime, two sub pixels may comprise one pixel. For example, the red sub pixel511and the green sub pixel512may comprise one pixel, and the blue sub pixel513and the green sub pixel514may comprise one pixel. Since the four sub pixels511,512,513, and514, or521,522,523, and524are included in one pixel structure510or520, four data lines531,532,533, and534may be required to drive one pixel structure510or520. Furthermore, the amplifiers (e.g.,136a) and the converters (e.g.,134a) described inFIG. 3may be connected to each of four data lines531,532,533, and534.

Referring toFIG. 5B, sub pixels541,542, and543may be disposed on the ‘N’ line201(or on the ‘N+1’ line202) in order of the red sub pixel541, the green sub pixel542, the blue sub pixel543, and a red sub pixel (not shown). The structure of a pixel540or550illustrated inFIG. 5Bmay be referred to as a “RGB stripe layout”, as a pixel structure different from the embodiment illustrated inFIG. 3.

According to an embodiment of the present disclosure, the details about the data driver130illustrated inFIGS. 1 to 4Bmay be applied to the structure of the pixel540or550illustrated inFIG. 5B. That is, since the one pixel540or550includes three sub pixels541,542, and543, or551,552, and553, the structure of the pixel540or550illustrated inFIG. 5Bmay need three data lines561,562, and563to drive one pixel540or550. The amplifiers (e.g., a part of136a) and the converters (e.g., a part of134a) described inFIG. 3may be connected to each of the three data lines561,562, and563. As such, six amplifiers (e.g., a part of136a) and six converters (e.g., a part of134a) may be connected to one latch (e.g.,133a) of the second group of latches133. One latch (e.g.,133a) of the second group of latches133may be connected to one latch (e.g.,132a) of the first group of latches132; while one latch (e.g.,132a) of the first group of latches132stores image data, one latch (e.g.,133a) of the second group of latches133may transmit second image data stored in one latch (e.g.,132a) of the first group of latches132, to converters (e.g., a part of134a).

According to an embodiment of the present disclosure, a display driver integrated circuit may include a controller configured to receive first image data from an application processor disposed outside the display driver integrated circuit, and a data driver configured to receive the first image data from the controller. The data driver may include a group of shift registers configured to convert the first image data to second image data, a first group of latches configured to receive the second image data from the group of shift registers to store the second image data, a second group of latches configured to receive the second image data from the first group of latches to store the second image data, a group of converters comprising digital analog converting circuitry configured to convert the first portion and/or the second portion of the second image data into a data voltage for causing at least part of pixels of a pixel group corresponding to the first pixel group and the second pixel group to emit or display light, and a group of amplifiers configured to output the data voltage to the at least part of pixels. Before transmission of the second image data from the first group of latches to the second group of latches is completed, the controller may be configured to cause the second group of latches to transmit a portion of the second image data, the transmission to the second group of latches of which is completed, from among the first portion of the second image data and the second portion of the second image data to the converters. The group of shift registers may include a first shift register corresponding to a first pixel group of at least one pixel line of a display panel connected to the display driver integrated circuit, and a second shift register corresponding to a second pixel group of the at least one pixel line. The first group of latches may include a first latch configured to store a first portion of the second image data received from the first shift register, and a second latch configured to store a second portion of the second image data received from the second shift register. The second group of latches may include a third latch configured to store the first portion of the second image data received from the first latch, and a fourth latch configured to store the second portion of the second image data received from the second latch.

According to an embodiment of the present disclosure, a first time interval in which the first group of latches stores the second image data and a second time interval in which the second group of latches transmits the stored second image data to the group of converters may overlap at least partly with each other.

According to an embodiment of the present disclosure, the group of amplifiers may include an input terminal configured to receive the data voltage as an input, and the controller may be configured to cause the second group of latches to transmit the stored second image data to the group of converters based on a voltage of the input terminal.

According to an embodiment of the present disclosure, the controller may be configured to cause the second group of latches to transmit the stored second image data to the group of converters based at least on a specified time period.

According to an embodiment of the present disclosure, the data driver may further include a group of switches interposed between the group of amplifiers and the display panel, and the controller may be configured to adjust a timing at which the data voltage is output, by opening and closing of the group of switches.

According to an embodiment of the present disclosure, a first time interval in which at least one of the group of switches is opened may overlap at least partly with a second time interval in which the second group of latches transmits the stored second image data to the converters.

According to an embodiment of the present disclosure, a first time interval in which at least one of the group of switches is closed may overlap at least partly with a second time interval in which the first group of latches stores the second image data.

According to an embodiment of the present disclosure, the data driver may further include a gamma circuit configured to generate a gray scale voltage to apply to the group of converters, and the group of converters may be configured to convert the first portion and/or the second portion of the second image data into the data voltage based on the gray scale voltage.

According to an embodiment of the present disclosure, the controller may be configured to cause the data driver to output the data voltage through the at least one pixel line.

According to an embodiment of the present disclosure, the display driver integrated circuit may further include a gate driver electrically connected to the at least one pixel line and configured to control on/off of a transistor connected to the at least one pixel line.

According to an embodiment of the present disclosure, the controller may be configured to receive control information for generating a clock from the application processor, and the data driver may operate in synchronization with the clock.

According to an embodiment of the present disclosure, the second image data corresponds to data obtained by parallelizing the first image data.

According to an embodiment of the present disclosure, a display may include a display panel in which a plurality of pixels and at least one pixel line electrically connected to each of the pixels are disposed and a display driver integrated circuit electrically connected to the at least one pixel line. The display driver integrated circuit may include a timing controller configured to receive first image data from an application processor; and a data driver including a group of shift registers configured to convert the first image data to second image data, a first group of latches configured to receive the second image data from the group of shift registers to store the second image data, a group of converters configured to convert the second image data to a data voltage for causing the pixels to emit or display light, a group of amplifiers configured to output the data voltage to the display panel, and a second group of latches configured to receive the second image data from the first group of latches to transmit the second image data to the group of converters. The timing controller may be configured to cause the second group of latches to transmit the stored second image data to the group of converters during a time interval in which the first group of latches stores the second image data.

According to an embodiment of the present disclosure, the data driver may further include a group of switches interposed between the group of amplifiers and the display panel, and the timing controller may be configured to adjust a timing in which the data voltage is output, by opening or closing the group of switches.

According to an embodiment of the present disclosure, the data driver may further include a gamma circuit configured to generate a gray scale voltage to apply to the group of converters, and the group of converters may be configured to convert the second image data to the data voltage based on the gray scale voltage.

According to an embodiment of the present disclosure, an electronic device may include a display panel including a plurality of pixel lines, a display driver integrated circuit, and a processor. The processor may be configured to supply a plurality of signals corresponding to a first portion of the display data to the first pixel group using the first switch at a first point in time and to supply a plurality of signals corresponding to a second portion of the display data to the second pixel group using the second switch at a second point in time. At least one pixel line among the plurality of pixel lines may include a first pixel group connected to a first transmission line and a second pixel group connected to a second transmission line. The display driver integrated circuit may include a storage circuit configured to at least temporarily store display data to be displayed through the at least one pixel line, at least one first source amplifier connected to the first pixel group and at least one second source amplifier connected to the second pixel group, a first decoder connected to the first source amplifier and a second decoder connected to the second source amplifier, at least one first switch for controlling a connection between the first source amplifier and the first pixel group and at least one second switch for controlling a connection between the second source amplifier and the second pixel group.

According to an embodiment of the present disclosure, the display driver integrated circuit may further include a gamma generating circuit configured to provide a gamma voltage associated with the display data to the first decoder and the second decoder.

According to an embodiment of the present disclosure, the storage circuit may include a first storage circuit and a second storage circuit. The first storage circuit may be configured to store the first portion of the display data, and the second storage circuit may be configured to transmit at least part of the stored first portion to the first decoder, while the first storage circuit stores the first portion of the display data.

According to an embodiment of the present disclosure, the first storage circuit may be configured to store the second portion of the display data and the second storage circuit may be configured to transmit at least part of the stored second portion to the second decoder, while the first storage circuit stores the second portion of the display data.

According to an embodiment of the present disclosure, the electronic device may further include an application processor configured to generate the display data. The display driver integrated circuit may further include a timing controller configured to receive the display data from the application processor.

FIG. 6is a block diagram of an electronic device in a network environment according to various embodiments.

Referring toFIG. 6, an electronic device601may communicate with an electronic device602through a first network698(e.g., a short-range wireless communication) or may communicate with an electronic device604or a server608through a second network699(e.g., a long-distance wireless communication) in a network environment600. According to an embodiment, the electronic device601may communicate with the electronic device604through the server608. According to an embodiment, the electronic device601may include a processor620, a memory630, an input device650, a sound output device655, a display device660, an audio module670, a sensor module676, an interface677, a haptic module679, a camera module680, a power management module688, a battery689, a communication module690, a subscriber identification module696, and an antenna module697. According to some embodiments, at least one (e.g., the display device660or the camera module680) among components of the electronic device601may be omitted or other components may be added to the electronic device601. According to some embodiments, some components may be integrated and implemented as in the case of the sensor module676(e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) embedded in the display device660(e.g., a display).

The processor620may operate, for example, software (e.g., a program640) to control at least one of other components (e.g., a hardware or software component) of the electronic device601connected to the processor620and may process and compute a variety of data. The processor620may load a command set or data, which is received from other components (e.g., the sensor module676or the communication module690), into a volatile memory632, may process the loaded command or data, and may store result data into a nonvolatile memory634. According to an embodiment, the processor620may include a main processor621(e.g., a central processing unit or an application processor) and an auxiliary processor623(e.g., a graphic processing device, an image signal processor, a sensor hub processor, or a communication processor), which operates independently from the main processor621, additionally or alternatively uses less power than the main processor621, or is specified to a designated function. In this case, the auxiliary processor623may operate separately from the main processor621or embedded.

In this case, the auxiliary processor623may control, for example, at least some of functions or states associated with at least one component (e.g., the display device660, the sensor module676, or the communication module690) among the components of the electronic device601instead of the main processor621while the main processor621is in an inactive (e.g., sleep) state or together with the main processor621while the main processor621is in an active (e.g., an application execution) state. According to an embodiment, the auxiliary processor623(e.g., the image signal processor or the communication processor) may be implemented as a part of another component (e.g., the camera module680or the communication module690) that is functionally related to the auxiliary processor623. The memory630may store a variety of data used by at least one component (e.g., the processor620or the sensor module676) of the electronic device601, for example, software (e.g., the program640) and input data or output data with respect to commands associated with the software. The memory630may include the volatile memory632or the nonvolatile memory634.

The program640may be stored in the memory630as software and may include, for example, an operating system642, a middleware644, or an application646.

The input device650may be a device for receiving a command or data, which is used for a component (e.g., the processor620) of the electronic device601, from an outside (e.g., a user) of the electronic device601and may include, for example, a microphone, a mouse, or a keyboard.

The sound output device655may be a device for outputting a sound signal to the outside of the electronic device601and may include, for example, a speaker used for general purposes, such as multimedia play or recordings play, and a receiver used only for receiving calls. According to an embodiment, the receiver and the speaker may be either integrally or separately implemented.

The display device660may be a device for visually presenting information to the user of the electronic device601and may include, for example, a display, a hologram device, or a projector and a control circuit for controlling a corresponding device. According to an embodiment, the display device660may include a touch circuitry or a pressure sensor for measuring an intensity of pressure on the touch.

The audio module670may convert a sound and an electrical signal in dual directions. According to an embodiment, the audio module670may obtain the sound through the input device650or may output the sound through an external electronic device (e.g., the electronic device602(e.g., a speaker or a headphone)) wired or wirelessly connected to the sound output device655or the electronic device601.

The sensor module676may generate an electrical signal or a data value corresponding to an operating state (e.g., power or temperature) inside or an environmental state outside the electronic device601. The sensor module676may include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

The interface677may support a designated protocol wired or wirelessly connected to the external electronic device (e.g., the electronic device602). According to an embodiment, the interface677may include, for example, an HDMI (high-definition multimedia interface), a USB (universal serial bus) interface, an SD card interface, or an audio interface.

A connecting terminal678may include a connector that physically connects the electronic device601to the external electronic device (e.g., the electronic device602), for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

The haptic module679may convert an electrical signal to a mechanical stimulation (e.g., vibration or movement) or an electrical stimulation perceived by the user through tactile or kinesthetic sensations. The haptic module679may include, for example, a motor, a piezoelectric element, or an electric stimulator.

The camera module680may shoot a still image or a video image. According to an embodiment, the camera module680may include, for example, at least one lens, an image sensor, an image signal processor, or a flash.

The power management module688may be a module for managing power supplied to the electronic device601and may serve as at least a part of a power management integrated circuit (PMIC).

The battery689may be a device for supplying power to at least one component of the electronic device601and may include, for example, a non-rechargeable (primary) battery, a rechargeable (secondary) battery, or a fuel cell.

The communication module690may establish a wired or wireless communication channel between the electronic device601and the external electronic device (e.g., the electronic device602, the electronic device604, or the server608) and support communication execution through the established communication channel. The communication module690may include at least one communication processor operating independently from the processor620(e.g., the application processor) and supporting the wired communication or the wireless communication. According to an embodiment, the communication module690may include a wireless communication module692(e.g., a cellular communication module, a short-range wireless communication module, or a GNSS (global navigation satellite system) communication module) or a wired communication module694(e.g., an LAN (local area network) communication module or a power line communication module) and may communicate with the external electronic device using a corresponding communication module among them through the first network698(e.g., the short-range communication network such as a Bluetooth, a Wi-Fi direct, or an IrDA (infrared data association)) or the second network699(e.g., the long-distance wireless communication network such as a cellular network, an internet, or a computer network (e.g., LAN or WAN)). The above-mentioned various communication modules690may be implemented into one chip or into separate chips, respectively.

According to an embodiment, the wireless communication module692may identify and authenticate the electronic device601using user information stored in the subscriber identification module696in the communication network.

The antenna module697may include one or more antennas to transmit or receive the signal or power to or from an external source. According to an embodiment, the communication module690(e.g., the wireless communication module692) may transmit or receive the signal to or from the external electronic device through the antenna suitable for the communication method.

Some components among the components may be connected to each other through a communication method (e.g., a bus, a GPIO (general purpose input/output), an SPI (serial peripheral interface), or an MIPI (mobile industry processor interface)) used between peripheral devices to exchange signals (e.g., a command or data) with each other.

According to an embodiment, the command or data may be transmitted or received between the electronic device601and the external electronic device604through the server608connected to the second network699. Each of the electronic devices602and604may be the same or different types as or from the electronic device601. According to an embodiment, all or some of the operations performed by the electronic device601may be performed by another electronic device or a plurality of external electronic devices. When the electronic device601performs some functions or services automatically or by request, the electronic device601may request the external electronic device to perform at least some of the functions related to the functions or services, in addition to or instead of performing the functions or services by itself. The external electronic device receiving the request may carry out the requested function or the additional function and transmit the result to the electronic device601. The electronic device601may provide the requested functions or services based on the received result as is or after additionally processing the received result. To this end, for example, a cloud computing, distributed computing, or client-server computing technology may be used.

FIG. 7is a block diagram of a display device according to various embodiments.

Referring toFIG. 7, the display device660may include a display710and a display driver IC (DDI)730for controlling the display710. The DDI730may include an interface module731, a memory733(e.g., a buffer memory), an image processing module735, or a mapping module737. For example, the DDI730may receive image information including image data or an image control signal corresponding to a command for controlling the image data from a processor620(e.g., a main processor621or an application processor) or an auxiliary processor623, which is operated independently of the main processor621, through the interface module731. The DDI730may communicate with a touch circuit750, the sensor module676, or the like through the interface module731. In addition, the DDI730may store at least a part of the received image information in the memory733, for example, in units of frames. For example, the image processing module735may perform preprocessing or post-processing (e.g., adjustment of resolution, brightness, or size) on at least a part of the image data based at least partially on characteristics of the image data or the display710. The mapping module737may convert the image data preprocessed or post-processed through the image processing module735into a voltage value or a current value capable of driving the pixels, based at least partially on attributes of the pixels of the display710(e.g., an array of pixels (RGB stripe or pentile) or a size of each of subpixels). For example, at least some pixels of the display710may be driven based on the voltage or current value, such that visual information (e.g., a text, an image, or an icon) corresponding to the image data is displayed on the display710.

According to an embodiment, the display device660may further include the touch circuit750. The touch circuit750may include a touch sensor751and a touch sensor IC753for controlling the touch sensor751. The touch sensor IC753may controls the touch sensor751to measure, for example, a change in a signal (e.g., a voltage, a light amount, a resistance, or a charge amount) at a specific position of the display710to sense a touch input or a hovering input, and may provide information (e.g., a location, an area, a pressure or a time) about the sensed touch input or hovering input to the processor620. According to an embodiment, at least a part (e.g., the touch sensor IC753) of the touch circuit750may be included as a part of the display driver IC730or the display710, or as a part of another component (e.g., the auxiliary processor623) arranged outside the display device660.

According to an embodiment, the display device660may further include at least one sensor (e.g., a fingerprint sensor, an iris sensor, a pressure sensor or an illuminance sensor) of the sensor module676, or a control circuitry thereof. In this case, the at least one sensor or the control circuitry thereof may be embedded in a part (e.g., the display710or the DDI730) of the display device660or a part of the touch circuit750. For example, when the sensor module676embedded in the display device660includes a biometric sensor (e.g., a fingerprint sensor), the biometric sensor may obtain biometric information associated with a touch input through an area of the display710. As another example, when the sensor module676embedded in the display device660includes a pressure sensor, the pressure sensor may obtain information about a pressure corresponding to a touch input through an area or entire area of the display710. According to an embodiment, the touch sensor751or the sensor module676may be arranged between pixels of the pixel layer of the display710, or above or below the pixel layer.

The electronic device according to various embodiments disclosed in the present disclosure may be various types of devices. The electronic device may include, for example, at least one of a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a mobile medical appliance, a camera, a wearable device, or a home appliance. The electronic device according to an embodiment of the present disclosure should not be limited to the above-mentioned devices.

It should be understood that various embodiments of the present disclosure and terms used in the embodiments do not intend to limit technologies disclosed in the present disclosure to the particular forms disclosed herein; rather, the present disclosure should be construed to cover various modifications, equivalents, and/or alternatives of embodiments of the present disclosure. With regard to description of drawings, similar components may be assigned with similar reference numerals. As used herein, singular forms may include plural forms as well unless the context clearly indicates otherwise. In the present disclosure disclosed herein, the expressions “A or B”, “at least one of A or/and B”, “A, B, or C” or “one or more of A, B, or/and C”, and the like used herein may include any and all combinations of one or more of the associated listed items. The expressions “a first”, “a second”, “the first”, or “the second”, used in herein, may refer to various components regardless of the order and/or the importance, but do not limit the corresponding components. The above expressions are used merely for the purpose of distinguishing a component from the other components. It should be understood that when a component (e.g., a first component) is referred to as being (operatively or communicatively) “connected,” or “coupled,” to another component (e.g., a second component), it may be directly connected or coupled directly to the other component or any other component (e.g., a third component) may be interposed between them.

The term “module” used herein may represent, for example, a unit including one or more combinations of hardware, software and firmware. The term “module” may be interchangeably used with the terms “logic”, “logical block”, “part” and “circuit”. The “module” may be a minimum unit of an integrated part or may be a part thereof. The “module” may be a minimum unit for performing one or more functions or a part thereof. For example, the “module” may include an application-specific integrated circuit (ASIC).

Various embodiments of the present disclosure may be implemented by software (e.g., the program640) including an instruction stored in a machine-readable storage media (e.g., an internal memory636or an external memory638) readable by a machine (e.g., a computer). The machine may be a device that calls the instruction from the machine-readable storage media and operates depending on the called instruction and may include the electronic device (e.g., the electronic device601). When the instruction is executed by the processor (e.g., the processor620), the processor may perform a function corresponding to the instruction directly or using other components under the control of the processor. The instruction may include a code generated or executed by a compiler or an interpreter. The machine-readable storage media may be provided in the form of non-transitory storage media. Here, the term “non-transitory”, as used herein, is a limitation of the medium itself (i.e., tangible, not a signal) as opposed to a limitation on data storage persistency.

According to an embodiment, the method according to various embodiments disclosed in the present disclosure may be provided as a part of a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of machine-readable storage medium (e.g., a compact disc read only memory (CD-ROM)) or may be distributed only through an application store (e.g., a Play Store™). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or generated in a storage medium such as a memory of a manufacturer's server, an application store's server, or a relay server.

Each component (e.g., the module or the program) according to various embodiments may include at least one of the above components, and a portion of the above sub-components may be omitted, or additional other sub-components may be further included. Alternatively or additionally, some components (e.g., the module or the program) may be integrated in one component and may perform the same or similar functions performed by each corresponding components prior to the integration. Operations performed by a module, a programming, or other components according to various embodiments of the present disclosure may be executed sequentially, in parallel, repeatedly, or in a heuristic method. Also, at least some operations may be executed in different sequences, omitted, or other operations may be added.