Bias circuit and power amplifier for improving linearity

A bias circuit includes a current source to generate a reference current, a temperature compensation portion in an off-state in an initial start period in response to a first control signal, and in an on-state in a normal driving period, subsequent to the initial start period, and to receive a first current of the reference current, and a bias output portion to generate a warm up current based on the reference current in the initial start period and to generate a bias current based on a second current, which is lower than the reference current by an amount of the first current, in the normal driving period.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 USC 119(a) to Korean Patent Application No. 10-2018-0095546 filed on Aug. 16, 2018 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

The following description relates to a bias circuit and a power amplifier for improving linearity.

2. Description of Background

Generally, a method of time division duplexing (TDD) and a method of frequency division duplexing (FDD) are used as wireless communication methods. Both methods are used to communicate with a greater number of users within limited sources. TDD is used to communicate with a plurality of users by dividing the time for which communication is performed by equal intervals in the same frequency, while FDD is used to communicate with users by allocating a different frequency to each user.

A common time division duplexing method is a method of communicating with a plurality of users by dividing the time for which communication is performed by equal intervals in the same frequency. In the common time division duplexing method, one frequency is used, and communications are performed in different periods of time. Accordingly, transmission and reception are repeatedly converted to each other during communication.

Accordingly, a high response speed of a transmitter and a receiver becomes an important factor of performance in communication based on a time division duplex method, and an amplifier circuit included in the transmitter and the receiver may also be required to have a high response speed.

However, to improve a response speed of a transmitter, it may be necessary to improve a response speed of a power amplifier provided in the transmitter. Particularly, the power amplifier may be required to reach a normal state swiftly within a short period of time when the power amplifier starts operating.

SUMMARY

In one general aspect, a bias circuit includes a current source to generate a reference current, a temperature compensation portion in an off-state in an initial start period in response to a first control signal, and in an on-state in a normal driving period, subsequent to the initial start period, and to receive a first current of the reference current, and a bias output portion to generate a warm up current based on the reference current in the initial start period and to generate a bias current based on a second current, which is lower than the reference current by an amount of the first current, in the normal driving period.

The temperature compensation portion may include a temperature compensation circuit connected between a first node, an output stage of the current source, and a first ground, and may also include a first switch connected between the first node and the temperature compensation circuit. The first switch may be in an off-state in the initial start period in response to the first control signal and in an on-state in the normal driving period.

The temperature compensation portion may include a temperature compensation circuit connected between a first node, an output stage of the current source, and a first ground, and may also include a first switch connected between the temperature compensation circuit and the first ground. The first switch may be in an off-state in the initial start period in response to the first control signal and in an on-state in the normal driving period.

The bias output portion may include a bias output circuit connected between the first node and a power amplifier circuit, and may also include a second switch connected between the first node and the bias output circuit. The second switch may be in an on-state in the initial start period and in the normal driving period in response to a second control signal.

The bias output portion may include a bias output circuit connected between the first node and a power amplifier circuit, and may also include a second switch connected between the bias output circuit and the power amplifier circuit. The second switch may be in an on-state in the initial start period and in the normal driving period in response to a second control signal.

The bias output circuit may include a bias transistor including a base connected to the second switch, a collector connected to an operational voltage terminal, and an emitter connected to the power amplifier circuit. The bias transistor may generate the warm up current in the initial start period and generate the bias current in the normal driving period by amplifying a current input through the second switch, and may output the amplified current to an input node of the power amplifier circuit.

The first current may be input in the temperature compensation circuit in the normal driving period and the second current may be input in the bias output circuit in the normal driving period, and the first current may be higher than the second current.

In another general aspect, a power amplifier includes a bias circuit to generate a warm up current in an initial start period and to generate a bias current in a normal driving period, subsequent to the initial start period, and a power amplifier circuit to be warmed up by receiving the warm up current and to be driven by receiving the bias current. The bias circuit includes a current source to generate a reference voltage, a temperature compensation portion in an off-state in the initial start period and in an on-state in the normal driving period, a bias output portion to generate the warm up current based on the reference current in the initial start period and to generate the bias current based on a current, which is lower than the reference current, in the normal driving period.

The temperature compensation portion may include a temperature compensation circuit connected between a first node, an output stage of the current source, and a first ground, and may also include a first switch connected between the first node and the temperature compensation circuit. The first switch may be in an off-state in the initial start period in response to the first control signal and in an on-state in the normal driving period.

The temperature compensation portion may include a temperature compensation circuit connected between a first node, an output stage of the current source, and a first ground, and may also include a first switch connected between the temperature compensation circuit and the first ground. The first switch may be in an off-state in the initial start period in response to the first control signal and in an on-state in the normal driving period.

The bias output portion may include a bias output circuit connected between the first node and a power amplifier circuit, and may also include a second switch connected between the first node and the bias output circuit. The second switch may be in an on-state in the initial start period and in the normal driving period in response to a second control signal.

The bias output portion may include a bias output circuit connected between the first node and a power amplifier circuit, and may also include a second switch connected between the bias output circuit and the power amplifier circuit. The second switch may be in an on-state in the initial start period and in the normal driving period in response to a second control signal.

The bias output circuit may include a bias transistor including a base connected to the second switch, a collector connected to an operational voltage terminal, and an emitter connected to the power amplifier circuit, and the bias transistor may generate the warm up current in the initial start period and generate the bias current in the normal driving period by amplifying a current input through the second switch, and may output the amplified current to an input node of the power amplifier circuit.

The power amplifier may include a control circuit to output the first control signal based on a system enable signal, the first control signal may have a switching-on level in the initial start period, the control circuit may generate the second control signal, and the second control signal may have a switching-off level in the initial start period and a switching-on level in the normal driving period.

The control circuit may include a buffer to output a second control voltage based on the system enable signal, a constant current source to generate a constant current, a capacitor circuit to charge an electric charge based on the constant current and to output a charging voltage, and a comparator to compare the charging voltage and a reference voltage and to output the first control signal having a level depending on a result of the comparison.

The control circuit may include a first constant current source to generate a first constant current, a second constant current source to generate a second constant current, a first capacitor circuit to charge an electric charge based on the first constant current and to output a first charging voltage, a second capacitor circuit to charge an electric charge based on the second constant current and to output a second charging voltage, a discharge control circuit to compare the first charging voltage and a first reference voltage and to control an output shutdown and a discharge of the first constant current source and the second constant current source having a level depending on a result of the comparison of the first charging voltage and the first reference voltage, a discharge circuit to discharge the first capacitor circuit and the second capacitor circuit in response to a control of the discharge control circuit, a first comparison circuit to compare the first charging voltage and a second reference voltage and to output the first control signal having a level depending on a result of the comparison of the first charging voltage and the second reference voltage, and a second comparison circuit to compare the second charging voltage and the second reference voltage and to output the second control signal having a level depending on a result of the comparison of the second charging voltage and the second reference voltage.

In another general aspect, a bias circuit includes a bias transistor configured to receive a first current and a second current lower than the first current, to output a third current based on the first current in a first time period, and to output a fourth current based on the second current in a second time period subsequent to the first time period, the fourth current being lower than the third current.

A power amplifier may include the bias circuit and a power amplifier circuit to be warmed up in the first time period in response to receiving the third current and to be driven in the second time period in response to receiving the fourth current.

The bias circuit may include one or more diodes to receive a fifth current equal to the first current minus the second current.

The bias circuit may include one or more diode-connected transistors to receive a fifth current equal to the first current minus the second current.

DETAILED DESCRIPTION

FIG. 1is a diagram illustrating an example configuration of a bias circuit and a power amplifier.FIG. 2is a diagram illustrating an example configuration of a bias circuit and a power amplifier.

Referring toFIGS. 1 and 2, a power amplifier may include a bias circuit100and a power amplifier circuit200.

The bias circuit100may generate a warm up current Iwp higher than a bias current Ibias in an initial start period PT1, and generate the bias current Ibias, lower than the warm up current Iwp, in a normal driving period PT2, subsequent to the initial start period PT1.

The power amplifier circuit200may be warmed up by receiving the warm up current Iwp in the initial start period PT1, and may be driven by receiving the bias current Ibias in the normal driving period PT2.

For example, the bias circuit100may include a current source110, a temperature compensation portion120and a bias output portion130.

The current source110may generate a reference current Iref.

The temperature compensation portion120may be in an off-state in the initial start period PT1, and may be in an on-state in the normal driving period PT2and receive a first current of the reference current Iref. For example, the temperature compensation portion120may be in an off-state in the initial start period PT1in response to a first control signal SC1, and may be in an on-state in the normal driving period PT2subsequent to the initial start period PT1and receive the first current I1of the reference current Iref.

The bias output portion130may generate the warm up current Iwp in the initial start period PT1based on the reference current Iref, and generate the bias current Ibias in the normal driving period PT2based on a base current Ib lower than the reference current Iref, that is, based on a second current I2, lower than the reference current Iref by the first current I1. For example, the bias output portion130may receive the base current Ib from the current source110, and the base current Ib may be the reference current Iref or the second current I2.

Referring toFIG. 2, the power amplifier may further include a control circuit300. The control circuit300may output the first control signal SC1having a switching-on level in the initial start period PT1, determined in advance, based on a system enable signal, and may generate a second control signal SC2including a switching-off level in the initial start period PT1and including a switching-on level in the normal driving period PT2.

For example, the first current I1may be configured to be input in the temperature compensation portion120in the normal driving period PT2, and may be higher than the second current I2input in bias output portion130.

For example, in the case in which a current amplifier gain of the bias output portion130is 100, the reference current Iref is 100 μA, the first current I1is 80 μA, and the second current I2is 20 μA, the warm up current Iwp may become 10 mA, equal to one hundred times the reference current Iref (100 μA), and the bias current Ibias may become 2 mA, equal to one hundred times the second current I2(20 μA).

For example, the temperature compensation portion120may operate in response to the first control signal SC1, and the bias output portion130may operate in response to the second control signal SC2.FIGS. 1 and 2merely illustrate an example, and the power amplifier, bias circuit, power amplifier circuit, and control circuit are not limited to such configurations. Various configurations will be described in greater detail with reference toFIGS. 5 to 8later.

In respect to the drawings, unnecessary overlapped descriptions of elements having the same reference numerals and functions will be omitted, and mainly, different features of the example in each diagram will be described.

FIG. 3is a diagram illustrating an example of a bias circuit.FIG. 4is a diagram illustrating an example of a bias circuit.

In the description below, examples of a temperature compensation portion120in a bias circuit100will be described with reference toFIGS. 3 and 4.

Referring toFIGS. 3 and 4, the temperature compensation portion120may include a temperature compensation circuit121and a first switch122.

Referring toFIG. 3, the temperature compensation circuit121may be connected between a first node N1, an output stage of a current source110, and a first ground GND1.

The first switch122may be connected between the first node N1and the temperature compensation circuit121, and may be in an off-state in an initial start period PT1in response to the first control signal SC1, and shutdown current supplied to the temperature compensation circuit121. The first switch122may be in an on-state in a normal driving period PT2and allow current to be supplied to the temperature compensation circuit121.

The temperature compensation circuit121may not operate when the first switch122is in an off-state, as the temperature compensation circuit121is not supplied with current, and when the first switch122is in an on-state, the temperature compensation circuit121may be supplied with a first current I1from a reference current Iref and operate normally.

Referring toFIG. 4, the temperature compensation circuit121may be connected between the first node N1, an output stage of the current source110, and the first ground GND1.

The first switch122may be connected between the temperature compensation circuit121and the first ground GND1, and may be in an off-state in the initial start period PT1in response to the first control signal SC1and shutdown current supplied to the temperature compensation circuit121, and may be in an on-state in the normal driving period PT2and allow current to be supplied to the temperature compensation circuit121.

The temperature compensation circuit121may not operate when the first switch122is in an off-state, as the temperature compensation circuit121is not supplied with current, and when the first switch122is in an on-state, the temperature compensation circuit121may be supplied with the first current I1from a reference current Iref and operate normally.

Referring toFIGS. 3 and 4, for example, the first switch122may include at least one switching device, such as an MOS transistor that can be switched on or off in response to the first control signal SC1.

FIG. 5is a diagram illustrating an example of a bias circuit.FIG. 6is a diagram illustrating an example of a bias circuit.

In the description below, examples of a bias output portion130in a bias circuit100will be described with reference toFIGS. 5 and 6.

The bias output portion130may include a bias output circuit131and a second switch132.

Referring toFIG. 5, the bias output circuit131may be connected between a first node N1and a power amplifier circuit200.

The second switch132may be connected between the first node N1and the bias output circuit131, and may be in an on-state in an initial start period PT1and in a normal driving period PT2in response to a second control signal SC2.

Operation of the bias output portion130may be in an off-state when the second switch132is in an off-state, and when the second switch132is in an on-state, the bias output portion130may generate a warm up current Iwp or a bias current Ibias based on a reference current Iref or a second current I2.

Referring toFIG. 6, the bias output circuit131may be connected between the first node N1and a power amplifier circuit200.

The second switch132may be connected between the bias output circuit131and the power amplifier circuit200, and may be in an on-state in the initial start period PT1and in the normal driving period PT2.

Operation of the bias output portion130may be in an off-state when the second switch132is in an off-state, and when the second switch132is in an on-state, the bias output portion130may generate a warm up current Iwp or a bias current Ibias based on the reference current Iref or the second current I2.

Referring toFIGS. 5 and 6, for example, the second switch132may include at least one switching device, such as an MOS transistor that can be switched on or off in response to the second control signal SC2.

FIGS. 5 and 6merely illustrate examples, and the present disclosure is not limited configurations.

FIG. 7is a diagram illustrating an example of a temperature compensation portion120and a bias output portion130.

Referring toFIG. 7, the temperature compensation portion120may include a temperature compensation circuit121, which may include a plurality of diode-connected transistors DT1and DT2connected in series between a first switch122and a first ground GND1.

FIG. 8is a diagram illustrating an example of a temperature compensation portion120and a bias output portion130.

Referring toFIG. 8, the temperature compensation portion120may include a temperature compensation circuit121, which may include a plurality of diodes D1and D2connected in series between the first switch122and the first ground GND1.

Referring toFIGS. 7 and 8, the bias output portion130may include a bias output circuit131, which may include a bias transistor Q31. The bias transistor Q31may include a base connected to a second switch132, a collector connected to an operational voltage Vbat terminal through a resistor R31, and an emitter connected to a power amplifier circuit200through a resistor R32.

The bias transistor Q31may amplify a current input through the second switch132and output the amplified current to the power amplifier circuit200.

For example, the bias transistor Q31may amplify a reference current Iref input in an initial start period PT1through the second switch132or a second current I2input in a normal driving period PT2, generate a warm up current Iwp in the initial start period PT1or generate a bias current Ibias in the normal driving period PT2, and output the amplified current to an input node NI of the power amplifier circuit200. For example, a capacitor C31may be connected between the base of the bias transistor Q31and a ground for stable operation of the bias transistor Q31.

The power amplifier circuit200may include an amplifier transistor QA. The amplifier transistor QA may include a base connected to an input stage IN through a first blocking capacitor CB1, a collector connected to an operational voltage Vcc terminal through a coil L1and connected to an output stage OUT through a second blocking capacitor CB2, and an emitter connected to a ground.

For example, the amplifier transistor QA may receive the warm up current Iwp through the base and be warmed up in the initial start period PT1.

The amplifier transistor QA may receive the bias current Ibias through the base in the normal driving period PT2, and may receive a signal, input through the input stage IN, through the base via the first blocking capacitor CB1, amplify the bias current Ibias and the signal, and output the amplified signal through the output stage OUT via the second blocking capacitor CB2.

The number of the plurality of diode-connected transistors DT1and DT2may be determined to compensate changes of the bias transistor Q31and the amplifier transistor QA caused by temperature. The number of the plurality of diodes D1and D2may be determined to compensate changes of the bias transistor Q31and the amplifier transistor QA caused by temperature.

Properties of the bias transistor Q31and the amplifier transistor QA may change depending on temperature, and properties of the plurality of diode-connected transistors DT1and DT2and the plurality of diodes D1and D2may also change depending on temperature in the same direction as a direction of properties change of the bias transistor Q31and the amplifier transistor QA. Thus, temperature compensation of the power amplifier may be achieved by the temperature compensation circuit121.

FIG. 9is a diagram illustrating an example of a control circuit.

Referring toFIG. 9, a control circuit300may generate and output a first control signal SC1having a switching-on level in an initial start period PT1, determined in advance, based on a system enable signal Sen.

The control circuit300may generate and output a second control signal SC2including a switching-off level in the initial start period PT1and including a switching-on level in a normal driving period PT2.

FIG. 10is a diagram illustrating an example of a timing chart of a main signal of the control circuit inFIG. 9.

Referring toFIG. 10, the element “Sen” may be a system enable signal input in a control circuit300. For example, the system enable signal Sen may be transited from a low level and to a high level when a system is enabled, and the system enable signal Sen may be transited from a high level to a low level when a system is disabled.

The element “SC2” may be a second control signal output from the control circuit300. The second control signal SC2may be synchronized to an ascent edge and a descent edge of the system enable signal Sen, and may go through an ascent transition T1and a descent transition T3.

The element “SC1” may be a first control signal output from the control circuit300. The first control signal SC1may maintain a low level from the ascent edge of the system enable signal Sen, may go through a transition from a low level to a high level (T2) after an initial start period PT1, predetermined, and continuously maintain a high level until a system is disabled (T3). Once the system is disabled (T3), the first control signal SC1may be transited from a high level to a low level.

FIG. 11is a diagram illustrating an example of a control circuit, such as the control circuit300inFIG. 9.FIG. 12is a diagram illustrating an example of a timing chart of a main signal and an operation of the control circuit inFIG. 11.

Referring toFIGS. 11 and 12, the control circuit300may include a buffer311, a constant current source321, a capacitor circuit331, and a comparator341.

The buffer311may output a second control signal SC2based on a system enable signal Sen.

The constant current source321may generate a constant current Iref2. For example, the constant current Iref2may be configured to be variable depending on an external control.

The capacitor circuit331may charge an electric charge based on the constant current Iref2and output a charging voltage Vx.

The comparator341may compare the charging voltage Vx and a reference voltage VREF and output a first control signal SC1including a level depending on a result of the comparison. For example, the reference voltage VREF may be configured to be variable depending on an external change.

For example, the comparator341may output the first control signal SC1including a low level when the charging voltage Vx is lower than the reference voltage VREF, and the comparator341may output the first control signal SC1including a high level when the charging voltage Vx is higher than the reference voltage VREF.

A control circuit200illustrated inFIG. 11may control the time of warm up accurately, but a process variation of a capacitor of the capacitor circuit331and an offset process variation of the comparator341may impede provision of an exact timing. To address the issue, a control circuit inFIG. 13may be used.

FIG. 13is a diagram illustrating an example of a control circuit, such as the control circuit300inFIG. 9.FIG. 14is a diagram illustrating an example of a timing chart of a main signal and an operation of the control circuit inFIG. 13.

Referring toFIG. 13, a control circuit300may include a first constant current source321-1, a second constant current source321-2, a first capacitor circuit331-1, a second capacitor circuit331-2, a discharge control circuit350, a discharge circuit360, a first comparison circuit341-1, and a second comparison circuit341-2.

The first constant current source321-1may be in a switched-on state or a switched-off state in response to a Q signal, and may generate and output a first constant current IREF1in an on-state.

The second constant current source321-2may be in a switched-on state or a switched-off state in response to a Q signal, and may generate and output a second constant current IREF2in an on-state.

For example, the first constant current IREF1may be a current higher than the second constant current IREF2. Accordingly, a slope of a first charging voltage Vx of a first capacitor circuit331-1may be greater than a slope of second charging voltage Vy of the second capacitor circuit331-2.

The first capacitor circuit331-1may include a first capacitor C1connected in parallel and a first switch device M1, and the first capacitor C1may charge electric charge based on the first constant current IREF1and output the first charging voltage Vx. The first switch device M1may be in an off-state in a system enabled state in response to an inversion enable signal Sen_B, and be in an on-state in a system disabled state, and discharge the first charging voltage Vx charged on the first capacitor C1.

The second capacitor circuit331-2may include a second capacitor C2connected in parallel and a second switch device M2, and the second capacitor C2may charge an electric charge based on the second constant current IREF2and output a second charging voltage Vy. The second switch device M2may be in an off-state in a system enabled state in response to an inversion enable signal Sen_B, and be in an on-state in a system disabled state and discharge the second charging voltage Vy charged on the second capacitor C2.

The discharge control circuit350may compare the first charging voltage Vx and a first reference voltage VREF1, and control an output shutdown and a discharge of first and second constant current sources321-1and321-2including a level depending on a result of the comparison. For example, the discharge control circuit350may include a comparator351and a latch352. The comparator351may compare the first charging voltage Vx and the first reference voltage VREF1, and in the case in which the first charging voltage Vx is lower than the first reference voltage VREF1, the comparator351may output a signal having a low level to the latch352, and in the case in which the first charging voltage Vx is higher than the first reference voltage VREF1, the comparator351may output a signal having a high level to a clock terminal of the latch352. The latch352may output a Q1signal having a low level and a Q2signal having a high level in the case in which a signal input in the clock terminal is a low level signal, and in the case in which a signal input in the clock terminal is a high level signal, the latch352may output a Q1signal having a high level and a Q2signal having a low level.

The discharge circuit360may discharge the first capacitor circuit331-1and the second capacitor circuit331-2in response to a control of the discharge control circuit350. For example, the discharge circuit360may allow a third current IREF3to flow to a ground in response to the Q1signal to discharge the first charging voltage Vx of the first capacitor circuit331-1, and may allow a fourth current IREF4to flow to a ground in response to the Q1signal to discharge the second charging voltage Vy of the second capacitor circuit331-2.

For example, in the case in which the Q2signal is a high level signal, a charging operation may be performed in the first capacitor circuit331-1and the second capacitor circuit331-2, and in the case in which the Q1signal is a high level signal, a discharging operation may be performed in the first capacitor circuit331-1and the second capacitor circuit331-2by the discharge circuit360configured to be in an on-state.

The second comparison circuit341-2may compare the second charging voltage Vy and a second reference voltage VREF2, and output the second control signal SC2including a level depending on a result of the comparison.

For example, the second comparison circuit341-2may include a second comparator COM2and a second AND gate AND2. The second comparator COM2may compare the second charging voltage Vy and the second reference voltage VREF2, and output a signal that includes a low level in the case in which the second charging voltage Vy is higher than the second reference voltage VREF2, and that includes a high level in the case in which the second charging voltage Vy is lower than the second reference voltage VREF2, to the second AND gate AND2.

The second AND gate AND2may logically multiply the Q1signal by the output signal of the second comparator COM2, and in the case in which both the signals are high level signals, the second AND gate AND2may output the second control signal SC2having a high level.

The first comparison circuit341-1may compare the first charging voltage Vx and the second reference voltage VREF2and output the first control signal SC1including a level depending on a result of the comparison.

For example, the first comparison circuit341-1may include a first comparator COM1and a first AND gate AND1. The first comparator COM1may compare the first charging voltage Vx and the second reference voltage VREF2, and output a signal that includes a low level in the case in which the first charging voltage Vx is higher than the second reference voltage VREF2, and that includes a high level in the case in which the first charging voltage Vx is lower than the second reference voltage VREF2, to the first AND gate AND1.

The first AND gate AND1may logically multiply the Q1signal by the output signal of the first comparator COM1, and in the case in which both the signals are high level signals, the first AND gate AND1may output the first control signal SC1having a high level.

Referring toFIGS. 13 and 14, in the case in which the first capacitor C1of the first capacitor circuit331-1and the second capacitor C2of the second capacitor circuit331-2have the same level of capacitance, and the first constant current IREF1is n times higher than the second constant current IREF2(IREF1=n×IREF2), the first charging voltage Vx may increase faster than the second charging voltage Vy.

When the first charging voltage Vx or the second charging voltage Vy charged at the time TO when an enable signal is transited to a high level reaches the first reference voltage VREF1(T1), the Q2signal may become an off-level signal, and the Q1signal may become an on-level signal. Accordingly, electric charge charged in the first capacitor C1and the second capacitor C2may be discharged in a constant speed.

By discharging the electric charge as described above, the first control signal SC1and the second control signal SC2may be transited to an ascent level at the time T2and T3when the first charging voltage Vx and the second charging voltage Vy become equal to the level of the second reference voltage VREF2, respectively. At the time T2when the second charging voltage Vy becomes equal to the second reference voltage VREF2, the second control signal SC2may enter an on-level, and at the time T3when the first charging voltage Vx becomes equal to the second reference voltage VREF2, the first control signal SC1may enter an on-level. Consequently, the power amplifier may be warmed up during the time elapsed between the time T2when the second control signal SC2enters an on-level and the time T3when first control signal SC1enters an on-level.

Even in the case in which the first capacitor C1and the second capacitor C2change due to a process variation, the amount of change in ratio (C1/C2) between the first capacitor C1and the second capacitor C2may be significantly low. Thus, even though the time points T1, T2and T3may change upon a process variation of the capacitors and an offset of the comparators, the time of T3-T2(corresponding to the initial start period PT1) may not significantly change. Accordingly, the time of a more stable initial start period PT1may be obtained in relation to process voltage temperature.

InFIG. 14, the aforementioned time may be adjusted as intended by adjusting the first reference voltage VREF1and the second reference voltage VREF2. Each of the first reference voltage VREF1and the second reference voltage VREF2may be a function of an operational voltage Vcc. For example, in the case in which the operational voltage Vcc is high, the level of warm up (Vcc×Iwp×time) corresponding to the initial start period PT1may be adjusted to be constant by setting the level of the first reference voltage VREF1to be low to reduce the time described above.

Further, inFIG. 14, the time may also be adjusted as intended by adjusting first to fourth reference voltages IREF1, IREF2, IREF3and IREF4. For example, in the case in which the third reference voltage IREF3is set to ¼ of the fourth reference voltage IREF4, the first charging voltage Vx may reduce four times more slowly than the second charging voltage Vy, and thus, it may be possible to increase the initial start period PT1(T3-T2) four times.

InFIG. 14, the element “Sen” may be a system enable signal. For example, when a mode is changed from a receiving mode RX to a transmitting mode TX, the system enable signal Sen may be transited from a low level to a high level. “TO” indicates an enabling time, “T1” indicates a discharging time determined by the Q1signal of the discharge control circuit350, “T2” indicates an ascent time of the second control signal SC2determined depending on an output signal of the second comparison circuit341-2, “T3” indicates an ascent time of the second control signal SC2determined depending on an output signal of the first comparison circuit341-1, and “T4” indicates the time when a signal is input.

The control circuit of the power amplifier according to an example may be implemented in a computing environment in which a processor such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like, a memory such as a volatile memory (e.g., a RAM, and the like) and a non-volatile memory (e.g., a ROM, a flash memory, and the like), an input device such as a keyboard, a mouse, a pen, a voice input device, a touch input device, an infrared camera, a video input device, and the like, an output device such as a display, a speaker, a printer, and the like, and a communication connection device such as a modem, a network interface card (NIC), an integrated network interface, a wireless frequency transmitter/receiver, an infrared port, a USB connection device, and the like, are interconnected to one another (e.g., peripheral component interconnection (PCI), USB, firmware [IEEE 1394], an optical bus structure, a network, and the like).

The computing environment may be implemented as a distributed computing environment including a personal computer, a server computer, a handheld or laptop device, a mobile device (e.g., a mobile phone, a PDA, a media player, and the like), a multi-processor system, a consumer electronic device, a mini-computer, a mainframe computer, the aforementioned random system or device, but the computing environment is not limited thereto.

According to the examples, a normal operational state may be reached swiftly by using a relatively high warm up current without performing temperature compensation in the initial start period PT1, and in the normal driving period PT2subsequently, a normal operation may be performed by using a bias current lower than the warm up current while performing temperature compensation. Accordingly, linearity may be improved.

By using a single current source and switching branching routes of a single reference current, the normal driving period may be reached swiftly using a high warm up current in the initial start period. Accordingly, the time when the bias circuit is warmed up may be accurately controlled in a simplified manner.

According to the examples, a bias circuit and a power amplifier improves linearity, and are capable of swiftly reaching a normal driving state using a relatively high warm up current without performing temperature compensation in an initial driving period PT1, and in a subsequent normal driving period PT2, a normal operation is performed using a bias current lower than the warm up current while performing temperature compensation.