Oscillation signal generation circuit

An oscillation signal generation circuit includes an oscillator and a calibration circuit. The oscillator includes a reference signal source circuit that has a reference signal source outputting a reference signal and converts the output reference signal into a control voltage, a filter that includes a variable resistance and a capacitance and removes noise in the control voltage, a transistor that converts the control voltage which has passed through the filter into a control current and outputs the control current, a core circuit that is driven by the control current and generates an output signal, and an output terminal that outputs the generated output signal. The calibration circuit is connected to the output terminal of the oscillator, detects whether or not the generated output signal is oscillating, and adjusts the current value of the control current by controlling the resistance value of the variable resistance in accordance with the detection result.

BACKGROUND

1. Technical Field

The present disclosure relates to an oscillation signal generation circuit that operates in a high frequency band exceeding 100 GHz.

2. Description of the Related Art

In recent years, with an increase in the use of the wireless technology typified by communication and radar, a frequency has rapidly become scarce. For this reason, a frequency band exceeding 100 GHz which is a frequency higher than a millimeter waveband is expected to be utilized. Thus, it is anticipated that a wireless integrated circuit (IC) that operates in a frequency band exceeding 100 GHz will be widely used.

In general, the wireless IC is often produced by a production method such as a complementary metal-oxide semiconductor (CMOS) process by using a semiconductor as a material. However, the performance of the CMOS process at high frequencies is lower than the performance of other production methods, which makes it difficult to achieve power gain at high frequencies.

Theoretically, the use of the fine CMOS process makes it possible to produce a wireless IC that operates in a frequency band exceeding 100 GHz, but there is almost no design margin. Furthermore, accuracy variations occur between transistors for a frequency band exceeding 100 GHz, the transistors formed by the CMOS process. This makes it necessary for the wireless IC to perform calibration. There is a high possibility that, in particular, a voltage controlled oscillator (VCO) which is one of the component elements of the wireless IC does not meet an oscillation condition due to the accuracy variations between the transistors. Therefore, a calibration technique for the VCO is important in developing a wireless IC that operates in a frequency band exceeding 100 GHz.

For example, in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007, a configuration having a VCO and a calibration circuit that controls the oscillation condition of the VCO is disclosed. The calibration circuit disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007 detects a current value which is the oscillation condition by controlling a current value flowing through the VCO in accordance with an oscillation signal of the VCO.

SUMMARY

However, in the above-described existing technique of IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007, noise contained in the current flowing through the VCO becomes phase noise in the oscillation signal. For example, it is possible to reduce the noise contained in the current by inserting an RC filter formed of a resistance and a capacitance into the VCO; however, in that case, a leakage current flowing through the resistance causes a voltage drop. That is, in the configuration in which the RC filter is inserted into the VCO, the range of calibration which controls the oscillation condition of the VCO is narrowed due to the voltage drop.

One non-limiting and exemplary embodiment provides an oscillation signal generation circuit that can expand the range of calibration which controls the oscillation condition of an oscillator while reducing phase noise in the oscillator.

In one general aspect, the techniques disclosed here feature an oscillation signal generation circuit including an oscillator and a calibration circuit. The oscillator includes a reference signal source circuit that has a reference signal source outputting a reference signal and converts the output reference signal into a control voltage, a first filter that includes a variable resistance and a capacitance and removes noise in the control voltage, a first transistor that converts the control voltage output from the first filter into a control current and outputs the control current, a core circuit that is driven by the control current and generates an output signal, and an output terminal that outputs the generated output signal. The calibration circuit is connected to the output terminal of the oscillator, detects whether or not the generated output signal is oscillating, and adjusts the current value of the control current by controlling the resistance value of the variable resistance in accordance with the detection result. These general and specific aspects may be implemented using a device, a system, a method, and a computer program, and any combination of devices, systems, methods, and computer programs.

With the present disclosure, it is possible to expand the range of calibration which controls the oscillation condition of an oscillator while reducing phase noise in the oscillator.

DETAILED DESCRIPTION

First, the underlying knowledge forming the basis of the present disclosure will be described. The present disclosure relates to an oscillation signal generation circuit that operates in a high frequency band exceeding 100 GHz.

FIG. 1Ais a configuration diagram of a common voltage control oscillation circuit1100. The voltage control oscillation circuit (hereinafter abbreviated as VCO)1100includes a reference current source circuit1101, an RC low-pass filter1102, a tail transistor1103, a cross-coupled transistor1104, and an LC tank1105. The cross-coupled transistor1104and the LC tank1105are each a core circuit of the VCO1100.

The reference current source circuit1101has a current source that outputs a reference current for generating a control voltage Vcontfor a current Itailwhich flows through the core circuit of the VCO1100. Incidentally, the reference current source circuit1101may be replaced with a reference voltage source circuit having a voltage source.

The control voltage Vcontwhich is generated by the reference current source circuit1101secondarily contains noise caused in the reference current source circuit1101. The noise contained in the control voltage Vcontbecomes phase noise in an output signal which is output from the core circuit of the VCO1100.

The RC low-pass filter1102is formed of a resistance and a capacitance and removes noise in a reference signal which is input from the reference current source circuit1101in order to suppress the phase noise in the output signal which is output from the core circuit of the VCO1100. The cutoff frequency fc of the RC low-pass filter1102is determined by the resistance value R of the resistance and the capacitance value C1of the capacitance.

FIG. 1Bis a diagram depicting the frequency characteristics of the RC low-pass filter1102. The horizontal axis ofFIG. 1Brepresents a frequency and the vertical axis represents a gain. As depicted inFIG. 1B, the RC low-pass filter1102allows a frequency component of a signal which is input thereto, the frequency component which is lower than or equal to the cutoff frequency fc, to pass therethrough and attenuates a frequency component which is higher than or equal to the cutoff frequency fc at a fixed angle of inclination.

For example, in the case of a primary RC filter like the RC low-pass filter1102, the cutoff frequency fc is expressed as fc=1/(2πC1R). That is, if the resistance value R or the capacitance value C1is large, the cutoff frequency decreases, which makes it possible to eliminate also noise of a lower frequency component.

However, if the resistance value R or the capacitance value C1is made larger, the area of the resistance or the capacitance increases, resulting in an increase of the chip size of the circuit. Moreover, in general, the resistance is smaller than the capacitance, but, since the resistance is connected in series to a control line X, if the size of the resistance is increased, higher noise is caused in the RC low-pass filter1102. The noise caused in the RC low-pass filter1102also becomes phase noise in the output signal which is output from the core circuit of the VCO1100.

Therefore, in general, the resistance of the RC low-pass filter1102is increased in size to the extent that noise which is caused in the RC low-pass filter1102does not affect phase noise in the output signal and the capacitance is increased in size to the extent that the size is permissible with respect to the chip area.

The reference current source circuit1101controls the control voltage Vcontby adjusting the reference current and outputs the control voltage Vcontto the RC low-pass filter1102. The RC low-pass filter1102removes noise of a high frequency component, the noise contained in the control voltage Vcont, and outputs the voltage from which the noise is eliminated to the tail transistor1103as a voltage Vtail.

The tail transistor1103is a voltage-current converter that outputs the current Itailin accordance with the voltage Vtail. The core circuit is driven by the current Itailwhich is output from the tail transistor1103, and generates an output signal and outputs the output signal from an output terminal.

The cross-coupled transistor1104compensates for power losses which are caused in the core circuit. The compensation capability of the cross-coupled transistor1104is generally expressed as transconductance (gm) and gm is determined by the current Itailand the size/process of the cross-coupled transistor1104. Specifically, let a coefficient which is determined by the size/process of the cross-coupled transistor1104be β. Then, gm is expressed by Equation 1 below.
gm=√{square root over (β·Itail)}  [Equation 1]
The larger the value of gm is, the higher the compensation capability of the cross-coupled transistor1104is.

On the other hand, the LC tank1105determines the oscillation frequency foof the VCO1100. The LC tank1105is formed of an inductor having an inductance value L and a capacitance having a capacitance value C2. Specifically, the oscillation frequency foof the VCO1100is expressed by Equation 2 below.

fo=12⁢⁢π⁢L·C2[Equation⁢⁢2]
In general, the VCO1100changes the oscillation frequency foby making the capacitance value C2variable by using a control signal Tosc.

Moreover, the loss of the LC tank1105is quantified by the Q value. By the use of the Q value, an equivalent parallel resistance Rp is determined. The larger the Q value is, the higher the equivalent parallel resistance Rp is.

In the VCO1100depicted inFIG. 1A, an oscillation condition indicating a condition as to whether or not the output signal oscillates is provided. The oscillation condition is affected by the LC tank1105and the cross-coupled transistor1104. Specifically, the oscillation condition is defined as the product of the transconductance gm of the cross-coupled transistor1104and the equivalent parallel resistance Rp of the LC tank1105. If gm·Rp≥1, the oscillation condition is met; if gm·Rp<1, the oscillation condition is not met. Since the equivalent parallel resistance Rp is determined by the loss of the LC tank1105, it is difficult to make an adjustment after the VCO1100is produced. Thus, in general, in order to adjust the oscillation condition by calibration after the VCO1100is produced, the current Itailis adjusted to change gm.

The adjustment of the current Itailis made by adjusting the voltage Vtailwhich is output from the RC low-pass filter1102. Therefore, the wider the variable range of the voltage Vtailis, that is, the larger a difference between the maximum value and the minimum value which can be taken by the voltage Vtailis, the wider the variable range of the current Itailbecomes.

In the existing CMOS process, since an oxide film which is formed between the gate of a transistor and a substrate is thick, a leakage current Ileakdoes not flow. However, in the fine CMOS process which effects operation in a frequency band exceeding 100 GHz, the leakage current Ileakflows and therefore the leakage current Ileakcannot be ignored. As depicted inFIG. 1A, since the leakage current Ileakflows to the resistance of the RC low-pass filter1102, a voltage drop occurs. If the magnitude of the voltage drop is assumed to be Vdrop, the voltage drop is expressed as follows: Vdrop=R·Ileak.

The relationship between the control voltage Vcontand the voltage Vtailis expressed as follows: Vtail=Vcont+Vdrop. Thus, unlike the existing CMOS process, in the fine CMOS process which effects operation in a frequency band exceeding 100 GHz, the variable range of the voltage Vtailis narrowed depending on the magnitude of Vdropand it becomes difficult to make an adjustment of the oscillation condition, that is, an adjustment of the current Itail.

For example, in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007, the configuration of a VCO that can control the oscillation condition is described. The configuration described in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007 is formed of a VCO, a differential squaring circuit that converts an oscillation signal of the VCO into a DC signal commensurate with the oscillation level, a DC cut capacitance that removes a DC value which appears in the output of the differential squaring circuit, a comparator that determines whether or not there is a difference among differential components which are output from the DC cut capacitance, a determination circuit that outputs a control signal based on the output of the comparator, and a current source circuit that determines the current value of the VCO based on the output of the determination circuit. With this configuration, it is possible to detect a current value flowing through the VCO, the current value which is necessary for the VCO to oscillate.

However, in the above-described existing technique of IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007, an RC filter is not provided and therefore noise contained in the current flowing through the VCO becomes phase noise in the oscillation signal. For example, as in the configuration depicted inFIG. 1A, even when an RC filter formed of a resistance and a capacitance is inserted into the VCO, the variable range of the voltage Vtailis narrowed and it is difficult to make an adjustment of the oscillation condition, that is, an adjustment of the current Itail.

In view of these circumstances, the inventors of the present disclosure have focused on the fact that, by providing an RC low-pass filter in a voltage control oscillation circuit and controlling the resistance value of a resistance of the RC low-pass filter, it is possible to curb the influence of a voltage drop and attained the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Incidentally, each embodiment which will be described below is an example and the present disclosure is not limited by these embodiments.

First Embodiment

FIG. 2is a block diagram depicting a configuration example of an oscillation signal generation circuit100according to a first embodiment of the present disclosure. As depicted inFIG. 2, the oscillation signal generation circuit100includes a voltage controlled oscillator107and a calibration circuit115. The voltage controlled oscillator107has a reference current source circuit101, an RC low-pass filter104having a variable resistance102and a capacitance103, a tail transistor105, and a core circuit106. The calibration circuit115has an envelope detection circuit108, a clock generation circuit109, an oscillation detection circuit110, a control signal generation circuit111, a switch112, a current value control circuit113, and a resistance value control circuit114.

The reference current source circuit101has a current source whose current value is variable and outputs a control voltage Vcontto the RC low-pass filter104based on a current value which is controlled by the current value control circuit113. In this embodiment, description is given based on the premise that the control voltage Vcontis generated by the reference current source circuit101having the current source; alternatively, the control voltage Vcontmay be generated by a circuit having a voltage source whose voltage value is variable in place of the current source. Incidentally, in the configuration of the reference current source circuit101depicted inFIG. 2, the larger the current value which is output from the current source is, the lower the control voltage Vcontbecomes.

The RC low-pass filter104has the variable resistance102and the capacitance103and removes, from the control voltage Vcont, noise whose frequency is higher than a cutoff frequency which is determined by the resistance value of the variable resistance102and the capacitance value of the capacitance103. The RC low-pass filter104outputs the voltage from which the noise is eliminated to the tail transistor105as a voltage Vtail. Incidentally, in the configuration of the reference current source circuit101depicted inFIG. 2, the smaller the resistance value of the variable resistance102is, the lower the voltage Vtailbecomes.

The tail transistor105is a voltage-current converter that generates a current Itailbased on the voltage Vtailwhich is input as a gate voltage. The tail transistor105outputs the current Itailto the core circuit106. Incidentally, in the configuration of the tail transistor105depicted inFIG. 2, the lower the voltage Vtailis, the larger the current Itailbecomes.

The core circuit106has, for example, a cross-coupled transistor (not depicted in the drawing) having transconductance (gm) commensurate with the current Itailand an LC tank (not depicted in the drawing) formed of an inductor that controls an oscillation frequency and a variable capacitance. The core circuit106is driven by the current Itailand outputs, from an output terminal P, an output signal Voscof the oscillation frequency which is adjusted by a signal Tosc. Incidentally, the core circuit106may be a ring oscillator.

With the configuration described above, the voltage controlled oscillator107outputs the output signal Voscfrom the output terminal P.

In the voltage controlled oscillator107, the lower the control voltage Vcontis, the lower the voltage Vtailbecomes, and, the lower the voltage Vtailis, the larger the current Itailbecomes. Moreover, the larger the current Itailis, the higher the output signal Voscbecomes and the larger the value of gm becomes. Since the possibility that the output signal Voscoscillates (that is, the possibility that the oscillation condition is met) is increased with an increase in the value of gm, the oscillation condition is stabilized.

In other words, a determination as to whether or not the output signal Voscoscillates (that is, whether or not the voltage controlled oscillator107meets the oscillation condition) is made based on the current Itail. The calibration circuit115according to this embodiment is configured so as to adjust the current Itailsuch that the output signal Voscoscillates (that is, the voltage controlled oscillator107meets the oscillation condition).

Specifically, the calibration circuit115connects to the output terminal P and receives the output signal Voscand detects whether or not the output signal Voscis oscillating. Then, the calibration circuit115adjusts the current Itailby controlling the variable resistance102or the reference current source circuit101in accordance with the detection result. Hereinafter, each component element of the calibration circuit115will be described.

The envelope detection circuit108is connected to the output terminal P and receives the output signal Vosc. The envelope detection circuit108detects an envelope of the output signal Voscand outputs the detected envelope to the oscillation detection circuit110as an envelope voltage Venv.

The clock generation circuit109generates a clock signal CLK and outputs the generated clock signal CLK to the oscillation detection circuit110and the control signal generation circuit111.

The oscillation detection circuit110detects the value of the envelope voltage Venvon the rising edge of the clock signal CLK and outputs, to the control signal generation circuit111, a detection signal DET indicating whether or not the output signal Voscis oscillating. Specifically, the oscillation detection circuit110outputs a high (“H”)-level detection signal DET if the output signal Voscis oscillating and outputs a low (“L”)-level detection signal DET if the output signal Voscis not oscillating. The oscillation detection circuit110may detect the value of the envelope voltage Venvon the falling edge of the clock signal CLK. Incidentally, the oscillation detection circuit110may output a low (“L”)-level detection signal DET if the output signal Voscis oscillating and output a high (“H”)-level detection signal DET if the output signal Voscis not oscillating.

Incidentally, configuration examples of the envelope detection circuit108and the oscillation detection circuit110will be described later.

The control signal generation circuit111generates an oscillation control signal CNT that controls the reference current source circuit101or the variable resistance102and a switch control signal SW that controls switching of the switch112on the rising edge of the clock signal CLK based on the detection result indicated by the detection signal DET and outputs the signals to the switch112. Incidentally, a specific configuration example of the control signal generation circuit111will be described later.

The switch112switches an output destination of the oscillation control signal CNT to either the current value control circuit113or the resistance value control circuit114based on the switch control signal SW. Incidentally, in this embodiment, as initial setting, the switch112is connected in such a way as to output the oscillation control signal CNT to the current value control circuit113.

The current value control circuit113outputs a control signal Tcurthat controls the current value of the current source of the reference current source circuit101to the reference current source circuit101based on the oscillation control signal CNT. Incidentally, a configuration example of the current value control circuit113will be described later along with a configuration example of the reference current source circuit101.

The resistance value control circuit114outputs a control signal Tresthat controls the resistance value of the variable resistance102to the variable resistance102based on the oscillation control signal CNT. Incidentally, a specific configuration example of the resistance value control circuit114will be described later along with a configuration example of the variable resistance102.

The calibration circuit115according to this embodiment adjusts the current Itailsuch that the current Itailincreases stepwise by controlling the current value of the current source of the reference current source circuit101and the resistance value of the variable resistance102stepwise.

For example, a controllable range Imin to Imax of the current value of the current source of the reference current source circuit101is divided into a plurality of control levels NI(NIis an integer which is greater than or equal to 2) in such a way that a level 0 which is an initial value corresponds to the minimum value Imin and a level NI−1 corresponds to the maximum value Imax. Then, the calibration circuit115adjusts the current Itailsuch that the current Itailincreases stepwise by controlling the current value of the current source of the reference current source circuit101so as to become larger stepwise from the level 0 to the level NI−1. Incidentally, the initial value of the current value may not be the minimum value Imin.

Moreover, a controllable range Rmax to Rmin of the resistance value of the variable resistance102is divided into a plurality of control levels NR(NRis an integer which is greater than or equal to 2) in such a way that a level 0 which is an initial value corresponds to the maximum value Rmax and a level NR−1 corresponds to the minimum value Rmin. Then, the calibration circuit115adjusts the current Itailsuch that the current Itailincreases stepwise by controlling the resistance value of the variable resistance102so as to become smaller stepwise from the level 0 to the level NR−1. Incidentally, the initial value of the resistance value may not be the maximum value Rmax.

The calibration circuit115according to this embodiment first controls the current value such that the current value becomes larger from Imin to Imax until the output signal Voscoscillates. Then, if the output signal Voscdoes not oscillate even when the current value reaches Imax, the calibration circuit115controls the resistance value such that the resistance value becomes smaller from Rmax to Rmin.

Incidentally, a method of controlling the current value and the resistance value in the calibration circuit115is not limited to the above-described method. For example, the calibration circuit115may control the resistance value first; alternatively, a method in which the calibration circuit115controls the current value and the resistance value alternately may be adopted. Moreover, the calibration circuit115may set the current value at a fixed value and control the resistance value.

Next, the configuration example of the control signal generation circuit111will be described.FIG. 3is a block diagram depicting a first configuration example of the control signal generation circuit111according to the first embodiment.

The control signal generation circuit111depicted inFIG. 3has a counter circuit201, a digital comparator202, a threshold value generation circuit203, and a determination circuit204.

The counter circuit201receives the detection signal DET and the clock signal CLK and generates the oscillation control signal CNT. Specifically, the counter circuit201detects the value of the detection signal DET on the rising edge of the clock signal CLK. Then, if the detected value indicates that the output signal Voscis not oscillating (that is, the oscillation condition is not met), the counter circuit201increases the number of counts (increments a count) of the oscillation control signal CNT whose initial value is zero and outputs the oscillation control signal CNT to the digital comparator202and the determination circuit204. Moreover, if the detected value indicates that the output signal Voscis oscillating (that is, the oscillation condition is met), the counter circuit201stops counting and does not output the oscillation control signal CNT. Incidentally, the counter circuit201may be configured so as to reduce the number of counts (decrement a count) of the oscillation control signal CNT.

With this configuration, the number of counts indicated by the oscillation control signal CNT increments by 1 on the rising edge of the clock signal CLK until the output signal Voscoscillates. The number of counts indicated by the oscillation control signal CNT corresponds to the control level of the current value or the resistance value which is controlled stepwise. That is, the number of counts indicated by the oscillation control signal CNT indicates one value of a plurality of values which the current Itailcan take.

Moreover, the counter circuit201receives the switch control signal SW. The counter circuit201does not initialize the oscillation control signal CNT if the switch control signal SW indicates the output level “L” and initializes the oscillation control signal CNT to zero if the switch control signal SW indicates the output level “H”.

The digital comparator202outputs the switch control signal SW to the switch112and the counter circuit201based on the oscillation control signal CNT and a threshold value Nthwhich is output from the threshold value generation circuit203. The switch control signal SW is a signal that controls switching of the switch112and takes either one of the values: the output level “L” indicating that switching is not performed and the output level “H” indicating that switching is performed.

Specifically, the digital comparator202compares the oscillation control signal CNT with the threshold value Nthand outputs the switch control signal SW at the output level “L” if the oscillation control signal CNT is smaller than the threshold value Nth. If the oscillation control signal CNT is greater than or equal to the threshold value Nth, the digital comparator202outputs the switch control signal SW at the output level “H”. Incidentally, the digital comparator202may be configured so as to compare the oscillation control signal CNT with the threshold value Nthand output the switch control signal SW at the output level “H” if the oscillation control signal CNT is smaller than the threshold value Nthand output the switch control signal SW at the output level “L” if the oscillation control signal CNT is greater than or equal to the threshold value Nth.

The threshold value generation circuit203sets the threshold value Nthand outputs the threshold value Nthto the digital comparator202. The threshold value Nthis set based on the controllable range of the current value in the current value control circuit113and the controllable range of the resistance value in the resistance value control circuit114. For example, if the calibration circuit115controls the current value, the threshold value Nthis set at NI; if the calibration circuit115controls the resistance value, the threshold value Nthis set at NR. The threshold value generation circuit203determines whether the calibration circuit115controls the current value or the resistance value based on the switch control signal SW and sets the threshold value Nth.

The determination circuit204is a circuit that prevents the oscillation control signal CNT from being output if the oscillation control signal CNT is greater than or equal to the threshold value Nth. Specifically, the determination circuit204receives the oscillation control signal CNT, the switch control signal SW, and the clock signal CLK and outputs the oscillation control signal CNT on the rising edge of the clock signal CLK if the switch control signal SW indicates the output level “L”. Moreover, if the switch control signal SW indicates the output level “H”, the determination circuit204does not output the oscillation control signal CNT after a lapse of a time corresponding to one clock indicated by the clock signal CLK after the determination circuit204outputs the oscillation control signal CNT. With this configuration, if the oscillation control signal CNT is greater than or equal to the threshold value Nth, that is, if the control level of the current value or the resistance value indicated by the oscillation control signal CNT exceeds the controllable range, the determination circuit204does not output the oscillation control signal CNT.

With the configuration depicted inFIG. 3, the control signal generation circuit111can output the oscillation control signal CNT in such a way that the resistance value is controlled stepwise within the controllable range of the resistance value in the resistance value control circuit114after the current value is controlled stepwise within the controllable range of the current value in the current value control circuit113.

In general, in an oscillator like the voltage controlled oscillator107according to this embodiment, along with an oscillation starting condition for making the output signal start oscillating, an oscillation continuance condition for making the output signal continue oscillating after starting oscillation is provided. This oscillation continuance condition is a condition on which a relatively relaxed constraint as compared to the constraint placed on the oscillation starting condition is placed. That is, after the output signal starts oscillating under the oscillation starting condition, the condition can be relaxed. Another configuration example of the control signal generation circuit111which will be described below is a configuration in which a search for the oscillation continuance condition is made by relaxing the condition after oscillation is started.

FIG. 4is a block diagram depicting a second configuration example of the control signal generation circuit111according to the first embodiment.

The control signal generation circuit111depicted inFIG. 4has a counter circuit301, a digital comparator302, a threshold value generation circuit303, a determination circuit304, and an up-down switching circuit305.

The up-down switching circuit305receives the detection signal DET and the clock signal CLK, and generates an up-down control signal UD and outputs the generated up-down control signal UD to the counter circuit301, the digital comparator302, and the threshold value generation circuit303. The up-down control signal UD is a signal indicating an increase (increment in a count) or a reduction (decrement in a count) in the number of oscillation control signals CNT.

Specifically, the up-down switching circuit305detects the value of the detection signal DET on the rising edge of the clock signal CLK. Then, if the detected value indicates that the oscillation condition is not met (that is, the output signal Voscis not oscillating), the up-down switching circuit305generates the up-down control signal UD indicating an increase in the number of oscillation control signals CNT (increment in a count) and outputs the generated up-down control signal UD. Moreover, if the detected value indicates that the oscillation condition is met (that is, the output signal Voscis oscillating), the up-down switching circuit305generates the up-down control signal UD indicating a reduction in the number of oscillation control signals CNT (decrement in a count) and outputs the generated up-down control signal UD.

If the up-down control signal UD indicates an increase in the number of oscillation control signals CNT (increment in a count), the counter circuit301increases the number of oscillation control signals CNT on the rising edge of the clock signal CLK. If the up-down control signal UD indicates a reduction (decrement in a count) in the number of oscillation control signals CNT, the counter circuit301reduces the number of oscillation control signals CNT on the rising edge of the clock signal CLK.

The digital comparator302outputs a switch control signal SW to the switch112and the counter circuit301based on the oscillation control signal CNT, a threshold value Nthwhich is output from the threshold value generation circuit303, and the up-down control signal UD. The switch control signal SW is a signal that controls switching of the switch112and takes either one of the values: the output level “L” indicating that switching is not performed and the output level “H” indicating that switching is performed.

Specifically, the digital comparator302operates in different manners when the up-down control signal UD indicates an increase in the number of oscillation control signals CNT (increment in a count) and when the up-down control signal UD indicates a reduction in the number of oscillation control signals CNT (decrement in a count).

When the up-down control signal UD indicates an increase in the number of oscillation control signals CNT (increment in a count), the digital comparator302compares the oscillation control signal CNT with the threshold value Nthand outputs the switch control signal SW at the output level “L” if the oscillation control signal CNT is smaller than the threshold value Nth. If the oscillation control signal CNT is greater than or equal to the threshold value Nth, the digital comparator302outputs the switch control signal SW at the output level “H”.

When the up-down control signal UD indicates a reduction in the number of oscillation control signals CNT (decrement in a count), the digital comparator302compares the oscillation control signal CNT with the threshold value Nthand outputs the switch control signal SW at the output level “L” if the oscillation control signal CNT is greater than or equal to the threshold value Nth. If the oscillation control signal CNT is smaller than the threshold value Nth, the digital comparator302outputs the switch control signal SW at the output level “H”.

The threshold value generation circuit303sets the threshold value Nthand outputs the threshold value Nthto the digital comparator302. The threshold value Nthis set based on the controllable range of the current value in the current value control circuit113and the controllable range of the resistance value in the resistance value control circuit114. Moreover, the threshold value generation circuit303outputs different threshold values when the up-down control signal UD indicates an increase in the number of oscillation control signals CNT (increment in a count) and when the up-down control signal UD indicates a reduction in the number of oscillation control signals CNT (decrement in a count).

For example, if the up-down control signal UD indicates an increase in the number of oscillation control signals CNT (increment in a count) and the current value is controlled, the threshold value Nthis set at NI; if the up-down control signal UD indicates an increase in the number of oscillation control signals CNT (increment in a count) and the resistance value is controlled, the threshold value Nthis set at NR. Moreover, if the up-down control signal UD indicates a reduction in the number of oscillation control signals CNT (decrement in a count) and the current value is controlled, the threshold value Nthis set at a level (that is, zero) corresponding to the minimum value Imin; if the up-down control signal UD indicates a reduction in the number of oscillation control signals CNT (decrement in a count) and the resistance value is controlled, the threshold value Nthis set at a level (that is, zero) corresponding to the maximum value Rmax.

The determination circuit304does not output the oscillation control signal CNT if the control level indicated by the oscillation control signal CNT is out of the controllable range. Specifically, the determination circuit304receives the oscillation control signal CNT, the switch control signal SW, and the clock signal CLK and outputs the oscillation control signal CNT on the rising edge of the clock signal CLK if the switch control signal SW indicates the output level “L”. Moreover, if the switch control signal SW indicates the output level “H”, the determination circuit304does not output the oscillation control signal CNT after a lapse of a time corresponding to one clock indicated by the clock signal CLK after the determination circuit304outputs the oscillation control signal CNT.

With the configuration depicted inFIG. 4, the control signal generation circuit111can output the oscillation control signal CNT in such a way that control is performed such that the resistance value is made smaller stepwise within the controllable range of the resistance value in the resistance value control circuit114after the current value is made larger stepwise within the controllable range of the current value in the current value control circuit113when the output signal Voscis not oscillating. Moreover, the control signal generation circuit111can output the oscillation control signal CNT in such a way that control is performed such that the current value is made smaller stepwise within the controllable range of the current value in the current value control circuit113after the resistance value is made larger stepwise within the controllable range of the resistance value in the resistance value control circuit114when the output signal Voscis oscillating.

Next, the specific configuration examples of the current value control circuit113and the reference current source circuit101will be described.FIG. 5is a block diagram depicting a first configuration example of the current value control circuit113and the reference current source circuit101according to the first embodiment.

The reference current source circuit101depicted inFIG. 5has an n-type metal-oxide-semiconductor field-effect-transistor (MOSFET)403and a p-type MOSFET404. The source terminal of the n-type MOSFET403connects to a ground, the gate terminal thereof connects to a digital-analog conversion circuit402, and the drain terminal thereof connects to the drain terminal of the p-type MOSFET404. The source terminal of the p-type MOSFET404connects to a power-supply line and the gate terminal thereof connects to the drain terminal of the p-type MOSFET404. The potential Vcontat the gate terminal of the p-type MOSFET404is output to the RC low-pass filter104. Incidentally, one or both of the n-type MOSFET403and the p-type MOSFET404may have a cascode configuration or the p-type and the n-type may be placed in the positions of the n-type and the p-type, respectively. Moreover, the MOSFET may be other types of transistor.

The current value control circuit113depicted inFIG. 5has a decode circuit401and the digital-analog conversion circuit402.

The decode circuit401generates a digital signal based on the oscillation control signal CNT and outputs the digital signal to the digital-analog conversion circuit402. For example, the decode circuit401has a table indicating the correspondence between the number of counts indicated by the oscillation control signal CNT, that is, the control level of the current value and a digital signal of a current value control signal Tcurto the gate terminal of the n-type MOSFET403for outputting a current value corresponding to the control level and outputs a digital signal of a current value control signal Tcurbased on the table.

The digital-analog conversion circuit402converts the received digital signal into a current value control signal Tcurand outputs the current value control signal Tcurto the gate terminal of the n-type MOSFET403. The current value control circuit113depicted inFIG. 5outputs an analog control voltage as the current value control signal Tcur.

With this configuration, the current value which flows through the reference current source circuit101varies in accordance with the current value control signal Tcur. For example, in the configuration depicted inFIG. 5, the larger the current value control signal Tcurbecomes, the larger the flowing current value becomes. Then, when the flowing current value becomes larger, the potential Vcontdecreases. On the other hand, when the current value control signal Tcurbecomes smaller, the potential Vcontincreases.

The decode circuit401may have a storage that stores the oscillation starting condition and the oscillation continuance condition. Since the oscillation continuance condition is a condition before (a control level before) the condition under which oscillation stops, the decode circuit401may have a circuit that calculates that condition. Incidentally, if the resistance value is controlled, the present condition (the present control level), not a condition before the condition under which oscillation stops, is the oscillation continuance condition.

Next, other configuration examples of the current value control circuit113and the reference current source circuit101will be described.FIG. 6is a block diagram depicting a second configuration example of the current value control circuit113and the reference current source circuit101according to the first embodiment.

As depicted inFIG. 6, the current value control circuit113has a decode circuit501. Moreover, the reference current source circuit101has a variable current circuit505and a p-type MOSFET506. The variable current circuit505has a current control unit504A including an n-type MOSFET502A and a switch503A and current control units504B to504X, each having the same configuration as the current control unit504A.

The decode circuit501outputs the current value control signal Tcurbased on the oscillation control signal CNT. The decode circuit501depicted inFIG. 6outputs, as the current value control signal Tcur, a signal that controls ON/OFF of the switches503A to503X of the variable current circuit505. For example, the decode circuit501has a table indicating the correspondence between the number of counts indicated by the oscillation control signal CNT, that is, the control level of the current value and a signal that controls ON/OFF of the switches503A to503X for outputting a current value corresponding to the control level and outputs the current value control signal Tcurbased on the table.

The source terminal of the n-type MOSFET502A of the current control unit504A connects to a ground and the drain terminal thereof connects to the drain terminal of the p-type MOSFET506via the switch503A. Moreover, to the gate terminal of the n-type MOSFET502A, a fixed potential is applied from an unillustrated bias circuit.

The switch503A brings the drain terminal of the n-type MOSFET502A and the drain terminal of the p-type MOSFET506into or out of conduction in accordance with the current value control signal Tcur.

The current control units504B to504X also have the same configuration as the current control unit504A.

The source terminal of the p-type MOSFET506connects to a power-supply line and the gate terminal thereof connects to the drain terminal of the p-type MOSFET506. The potential Vcontat the gate terminal of the p-type MOSFET506is output to the RC low-pass filter104.

Incidentally, one or both of the n-type MOSFETs502A to502X and the p-type MOSFET506may have a cascode configuration or the p-type and the n-type may be placed in the positions of the n-type and the p-type, respectively. Moreover, the switch503A may be positioned between the source terminal of the n-type MOSFET502A and the ground or between the gate terminal and the unillustrated bias circuit. When the switch503A is provided between the gate terminal and the bias circuit, it is more preferable to provide a reset switch that resets the gate-source voltage to about 0 V. The same goes for the positions of the switches503B to503X. Moreover, the MOSFET may be other types of transistor.

The variable current circuit505changes the number of current control units504which are connected to the p-type MOSFET506in accordance with the current value control signal Tcur.

With this configuration, the current value flowing through the reference current source circuit101varies in accordance with the current value control signal Tcur. For example, in the configuration depicted inFIG. 6, the larger the number of current control units504which are connected to the p-type MOSFET506is, the larger the flowing current value becomes. Then, when the flowing current value becomes larger, the potential Vcontdecreases. On the other hand, when the number of current control units504which are connected to the p-type MOSFET506is small, the potential Vcontincreases.

The decode circuit501may have a storage that stores the oscillation start condition and the oscillation continuance condition. Since the oscillation continuance condition is a condition before (a control level before) the condition under which oscillation stops, the decode circuit501may have a circuit that calculates that condition. Incidentally, if the resistance value is controlled, the present condition (the present control level), not a condition before the condition under which oscillation stops, is the oscillation continuance condition.

Next, the specific configuration examples of the resistance value control circuit114and the variable resistance102will be described.FIG. 7is a block diagram depicting a first configuration example of the resistance value control circuit114and the variable resistance102according to the first embodiment.

The variable resistance102depicted inFIG. 7has an n-type MOSFET603. The source terminal of the n-type MOSFET603connects to the output terminal of the reference current source circuit101, the gate terminal thereof connects to the output terminal of a digital-analog conversion circuit602, and the drain terminal thereof connects to the capacitance103of the RC low-pass filter104and the gate terminal of the tail transistor105.

Incidentally, the n-type MOSFET603may be replaced with a p-type MOSFET. In that case, the drain terminal of the p-type MOSFET connects to the output terminal of the reference current source circuit101, the gate terminal thereof connects to the output terminal of the digital-analog conversion circuit602, and the source terminal thereof connects to the capacitance103of the RC low-pass filter104and the gate terminal of the tail transistor105.

The capacitance103may be, for example, a MIM capacitor, a MOM capacitor, or a MOS capacitor. Moreover, the MOSFET may be other types of transistor. Hereinafter, a case in which the variable resistance102has the n-type MOSFET603and the tail transistor105is a p-type MOSFET will be described.

The resistance value control circuit114depicted inFIG. 7has a decode circuit601and the digital-analog conversion circuit602.

The decode circuit601generates a digital signal based on the oscillation control signal CNT and outputs the digital signal to the digital-analog conversion circuit602. For example, the decode circuit601has a table indicating the correspondence between the number of counts indicated by the oscillation control signal CNT, that is, the control level of the resistance value and a digital signal of a resistance value control signal Tresto the gate terminal of the n-type MOSFET603for obtaining a resistance value corresponding to the control level and outputs a digital signal of a resistance value control signal Tresbased on the table.

The digital-analog conversion circuit602converts the received digital signal into a resistance value control signal Tresand outputs the resistance value control signal Tresto the gate terminal of the n-type MOSFET603. The resistance value control circuit114depicted inFIG. 7outputs an analog control voltage as the resistance value control signal Tres.

With this configuration, the resistance value of the variable resistance102varies in accordance with the resistance value control signal Tres. For example, in the configuration depicted inFIG. 7, the larger the resistance value control signal Tresbecomes, the smaller the resistance value of the variable resistance102becomes. As a result, the leakage current Ileakflowing from the tail transistor105becomes smaller and the voltage drop caused by the variable resistance102is suppressed, and Vtaildecreases. On the other hand, when the resistance value control signal Tresbecomes smaller, Vtailincreases. Moreover, when the tail transistor105is an n-type MOSFET, the reverse of what is observed when the tail transistor105is a p-type MOSFET is observed.

The decode circuit601may have a storage that stores the oscillation starting condition and the oscillation continuance condition. Since the oscillation continuance condition is a condition before (a control level before) the condition under which oscillation stops, the decode circuit601may have a circuit that calculates that condition.

Next, other configuration examples of the resistance value control circuit114and the variable resistance102will be described.FIG. 8is a block diagram depicting a second configuration example of the resistance value control circuit114and the variable resistance102according to the first embodiment.

As depicted inFIG. 8, the resistance value control circuit114has a decode circuit701. Moreover, the variable resistance102has resistance units704A to704X. The resistance unit704A has a fixed resistance702A and a switch703A which is connected in parallel to the fixed resistance702A. The resistance units704B to704X have the same configuration as the resistance unit704A.

The decode circuit701outputs a resistance value control signal Tresbased on the oscillation control signal CNT. The decode circuit701depicted inFIG. 7outputs, as the resistance value control signal Tres, a signal that controls ON/OFF of the switches703A to703X. For example, the decode circuit701has a table indicating the correspondence between the number of counts indicated by the oscillation control signal CNT, that is, the control level of the resistance value and a signal that controls ON/OFF of the switches703A to703X for obtaining a resistance value corresponding to the control level and outputs the resistance value control signal Tresbased on the table.

In the variable resistance102, the fixed resistances702A to702X are connected in series. Then, one of the ends of the fixed resistance702A, the end which does not connect to the fixed resistance702B, connects to the output terminal of the reference current source circuit101, and, one of the ends of the fixed resistance702X, the end which does not connect to another fixed resistance, connects to the capacitance103of the RC low-pass filter104and the gate terminal of the tail transistor105.

The switches703A to703X switch ON/OFF in accordance with the resistance value control signal Tres.

With this configuration, the resistance value of the variable resistance102varies in accordance with the resistance value control signal Tres. For example, in the configuration depicted inFIG. 8, the larger the number of switches703A to703X which are turned ON by the resistance value control signal Tresis, the smaller the resistance value of the variable resistance102becomes. As a result, the leakage current Ileakflowing from the tail transistor105becomes smaller and the voltage drop caused by the variable resistance102is suppressed, and Vtaildecreases. On the other hand, the smaller the number of switches703A to703X which are turned ON by the resistance value control signal Tresis, the higher Vtailbecomes. Moreover, when the tail transistor105is an n-type MOSFET, the reverse of what is observed when the tail transistor105is a p-type MOSFET is observed.

The decode circuit701may have a storage that stores the oscillation starting condition and the oscillation continuance condition. Since the oscillation continuance condition is a condition before (a control level before) the condition under which oscillation stops, the decode circuit701may have a circuit that calculates that condition.

Next, the specific configuration examples of the voltage controlled oscillator107, the envelope detection circuit108, and the oscillation detection circuit110will be described.FIG. 9Ais a block diagram depicting a first configuration example of the voltage controlled oscillator107, the envelope detection circuit108, and the oscillation detection circuit110according to the first embodiment. In the voltage controlled oscillator107inFIG. 9A, the reference current source circuit101and the variable resistance102which have been described above are omitted.

The tail transistor105is formed as a p-type MOSFET801. Incidentally, the tail transistor105may be formed as an n-type MOSFET.

The core circuit106has an LC tank portion804including an inductor802and a variable capacitance803and a cross-coupled transistor807including two n-type MOSFETs805and806. Incidentally, the cross-coupled transistor807may be formed of two p-type MOSFETs or may be formed of two p-type MOSFETs and two n-type MOSFETs. Moreover, the MOSFET may be other types of transistor.

The LC tank portion804has a configuration in which the inductor802and the variable capacitance803are connected in parallel. The capacitance value of the variable capacitance803is set by a control signal TOSC.

The gate terminal of the p-type MOSFET801connects to a power-supply line and the drain terminal thereof connects to a midpoint of the inductor802. The source terminal of the p-type MOSFET801connects to the output end of the RC low-pass filter104and receives the voltage Vtail.

The source terminals of the n-type MOSFET805and the n-type MOSFET806connect to a ground. The gate terminal of the n-type MOSFET805connects to the drain terminal of the n-type MOSFET806and one of the terminals of the LC tank portion807. The drain terminal of the n-type MOSFET805connects to the gate terminal of the n-type MOSFET806and the other terminal of the LC tank portion807.

With this configuration, the voltage controlled oscillator107outputs output signals Voscpand Voscnfrom the drain terminal of the n-type MOSFET805and the drain terminal of the n-type MOSFET806, respectively. The output signals Voscpand Voscnare differential signals with opposite signs.

The envelope detection circuit108has a squaring circuit808and a low-pass filter809, and connects to the output terminal of the voltage controlled oscillator107and receives the output signals Voscpand Voscn.

The squaring circuit808outputs, to the low-pass filter809, a signal obtained as the square of either the output signal Voscpor Voscnand a signal obtained by multiplying the output signals Voscpand Voscn. If the output signals Voscpand Voscnare oscillating at a predetermined frequency, the signal output from the squaring circuit808contains a component having a frequency which is twice as high as the predetermined frequency and a DC component.

The low-pass filter809removes the component having a frequency which is twice as high as the predetermined frequency, the component contained in the signal output from the squaring circuit808, and outputs DC components Venvpand Venvnto the oscillation detection circuit110. Incidentally, the DC components Venvpand Venvnrespectively correspond to a positive envelope amplitude and a negative envelope amplitude which are obtained from the output signals Voscpand Voscn.

The oscillation detection circuit110has a comparator810. The comparator810receives the DC components Venvpand Venvn, receives the clock signal CLK from the clock generation circuit109(seeFIG. 2), and outputs the detection signal DET.

The comparator810detects the values of the DC components Venvpand Venvnon the rising edge of the clock signal CLK and performs a comparison between the values. If there is no difference between the DC components Venvpand Venvn, the comparator810does not change the detection signal DET and keeps the detection signal DET at the initial value; if there is a difference between the DC components Venvpand Venvn, the comparator810changes the detection signal DET.

Incidentally, the comparator810may perform detection and comparison on the falling edge of the clock signal CLK.

Moreover, in order to avoid a malfunction caused by noise, the input and output characteristics of the comparator810may be provided with hysteresis. In that case, it is necessary to set the initial output value of the comparator810at “L” or “H”. For example, at a time point at which the comparator810does not perform detection and comparison (on the falling edge of the clock signal CLK, for example), the value may be reset to the initial value at which the output of the comparator810is set. With this configuration, it is possible to support also the second configuration example of the control signal generation circuit111according to this embodiment.

Here, examples of the signals which are input and output to and from the voltage controlled oscillator107, the envelope detection circuit108, and the oscillation detection circuit110which are depicted inFIG. 9Awill be described.FIG. 9Bis a diagram depicting examples of input-output signal waveforms of the voltage controlled oscillator107, the envelope detection circuit108, and the oscillation detection circuit110in this embodiment.

As depicted inFIG. 9B, the output signals Voscpand Voscnare differential signals with opposite signs. The DC components Venvpand Venvnrespectively correspond to a positive envelope amplitude and a negative envelope amplitude which are obtained from the output signals Voscpand Voscn. If the output signals Voscpand Voscnare not oscillating, the DC components Venvpand Venvnare zero. Moreover, if the output signals Voscpand Voscnare oscillating, the DC components Venvpand Venvnhave DC components with opposite signs.

Moreover, in the clock signal CLK ofFIG. 9B, two rising-edge time points P1and P2are depicted. Here, the operation of the comparator810at the time points P1and P2will be described.

First, the comparator810detects the values of the DC components Venvpand Venvnat the time point P1and performs a comparison between the values. In the case ofFIG. 9B, since there is no difference between the DC components Venvpand Venvnat the time point P1, the comparator810does not change the detection signal DET and keeps the detection signal DET at the initial value.

Next, the comparator810detects the values of the DC components Venvpand Venvnat the time point P2and performs a comparison between the values. In the case ofFIG. 9B, since there is a difference between the DC components Venvpand Venvnat the time point P2, the comparator810changes the detection signal DET from zero to VD.

As described above, when the output signal Voscpand Voscnare oscillating, the comparator810generates, by changing the detection signal DET from zero to VD, the detection signal DET indicating whether or not the output signal Voscis oscillating. Incidentally, in the above description, the detection signal DET is assumed to be a binary signal of zero and VD, but the present disclosure is not limited thereto.

Moreover, in the above description, the comparator810changes the value of the detection signal DET depending on whether or not there is a difference between the values of the DC components Venvpand Venvn, but the comparator810may compare the difference between the DC components Venvpand Venvnwith a predetermined threshold value and change the value of the detection signal DET in accordance with the comparison result.

Next, other configuration examples of the voltage controlled oscillator107, the envelope detection circuit108, and the oscillation detection circuit110will be described.FIG. 10Ais a block diagram depicting a second configuration example of the voltage controlled oscillator107, the envelope detection circuit108, and the oscillation detection circuit110according to the first embodiment. In the voltage controlled oscillator107inFIG. 10A, the reference current source circuit101and the variable resistance102which have been described above are omitted. Moreover, inFIG. 10A, such component elements as are found also inFIG. 9Awill be identified with the same reference characters and their detailed explanations will be omitted.

The second configuration example depicted inFIG. 10Ahas a differential to single phase conversion circuit901that converts the differential output signals Voscpand Voscnin the first configuration example depicted inFIG. 9Ainto a single-phase output signal Vosc. Moreover, the configurations of the envelope detection circuit108and the oscillation detection circuit110depicted inFIG. 10Adiffer from the configurations depicted inFIG. 9A.

The differential to single phase conversion circuit901converts the differential output signals Voscpand Voscnwhich are respectively output from the drain terminal of the n-type MOSFET805and the drain terminal of the n-type MOSFET806into a single-phase output signal Vosc. Incidentally, the differential to single phase conversion circuit901may be provided in the envelope detection circuit108.

The envelope detection circuit108depicted inFIG. 10Ahas a squaring circuit902and a low-pass filter903, and connects to the output terminal of the differential to single phase conversion circuit901of the voltage controlled oscillator107and receives the output signal Vosc.

The squaring circuit902squares the output signal Voscand outputs the output signal squared to the low-pass filter903. If the output signal Voscis oscillating at a predetermined frequency, the output signal squared contains a component having a frequency which is twice as high as the predetermined frequency and a DC component.

The low-pass filter903removes the component having a frequency which is twice as high as the predetermined frequency, the component contained in the signal squared, and outputs a DC component Venvto the oscillation detection circuit110. Incidentally, the DC component Venvcorresponds to the envelope amplitude of the output signal Vosc.

The oscillation detection circuit110has a threshold value generation circuit904and a comparator905. The threshold value generation circuit904generates a predetermined threshold value Vthand outputs the threshold value Vthto the comparator905. The comparator905receives the DC component Venvand the threshold value Vth, receives the clock signal CLK from the clock generation circuit109(seeFIG. 2), and outputs the detection signal DET.

The comparator905detects the value of the DC component Venvon the rising edge of the clock signal CLK and compares the detected value with the threshold value Vth. If the value of the DC component Venvis smaller than the threshold value Vth, the comparator905does not change the detection signal DET and keeps the detection signal DET at the initial value; if the value of the DC component Venvis greater than or equal to the threshold value Vth, the comparator905changes the detection signal DET.

Incidentally, if the value of the DC component Venvis smaller than or equal to the threshold value Vth, the comparator905may not change the detection signal DET and may keep the detection signal DET at the initial value; if the value of the DC component Venvis greater than the threshold value Vth, the comparator905may change the detection signal DET. Moreover, the comparator905may perform detection and comparison on the falling edge of the clock signal CLK.

Moreover, in order to avoid a malfunction caused by noise, the input and output characteristics of the comparator905may be provided with hysteresis. In that case, it is necessary to set the initial output value of the comparator905at “L” or “H”. For example, at a time point at which the comparator905does not perform detection and comparison (on the falling edge of the clock signal CLK, for example), the value may be reset to the initial value at which the output of the comparator905is set. With this configuration, it is possible to support also the second configuration example of the control signal generation circuit111according to this embodiment.

Here, examples of the signals which are input and output to and from the voltage controlled oscillator107, the envelope detection circuit108, and the oscillation detection circuit110which are depicted inFIG. 10Awill be described.FIG. 10Bis a diagram depicting examples of input-output signal waveforms of the voltage controlled oscillator107, the envelope detection circuit108, and the oscillation detection circuit110in this embodiment.

As depicted inFIG. 10B, the output signal Voscis a single-phase signal. The DC component Venvcorresponds to the envelope amplitude of the output signal Vosc. If the output signal Voscis not oscillating, the DC component Venvis zero. Moreover, if the output signal Voscis oscillating, the DC component Venvhas a DC component with a magnitude commensurate with the amplitude of oscillation. Furthermore, for the DC component Venv, the threshold value Vthis depicted.

Moreover, in the clock signal CLK ofFIG. 10B, three rising-edge time points P1, P2, and P3are depicted. Here, the operation of the comparator905at the time points P1, P2, and P3will be described.

First, the comparator905detects the value of the DC component Venvat the time point P1and compares the detected value with the threshold value Vth. In the case ofFIG. 10B, since the output signal Voscis not oscillating at the time point P1, the DC component Venvis zero. Thus, since the value of the DC component Venvat the time point P1is smaller than the threshold value Vth, the comparator905does not change the detection signal DET and keeps the detection signal DET at the initial value, that is, zero.

Next, the comparator905detects the value of the DC component Venvat the time point P2and compares the detected value with the threshold value Vth. In the case ofFIG. 10B, at the time point P2, although the output signal Voscis oscillating, the amplitude of oscillation is small. Thus, since the DC component Venvat the time point P2is smaller than the threshold value Vth, the comparator905does not change the detection signal DET and keeps the detection signal DET at the initial value, that is, zero.

Next, the comparator905detects the value of the DC component Venvat the time point P3and compares the detected value with the threshold value Vth. In the case ofFIG. 10B, at the time point P3, the output signal Voscis oscillating with large amplitude. Thus, since the DC component Venvat the time point P3is greater than or equal to the threshold value Vth, the comparator905changes the detection signal DET from zero to VD.

As described above, when the output signal Voscis oscillating, the comparator905generates, by changing the detection signal DET from zero to VD, the detection signal DET indicating whether or not the output signal Voscis oscillating. Incidentally, in the above description, the detection signal DET is assumed to be a binary signal of zero and VD, but the present disclosure is not limited thereto.

As described above, with the configuration of the oscillation signal generation circuit described in this embodiment, by inserting a filter having a resistance and a capacitance into a voltage controlled oscillator, it is possible to reduce phase noise in the output signal, and, by controlling the resistance value of the resistance of the filter, it is possible to expand the range of calibration that controls the oscillation condition.

Incidentally, the oscillation signal generation circuit described in this embodiment may have a storage, such as a memory or a register, which stores any one of the oscillation starting condition and the oscillation continuance condition or both.

Second Embodiment

In general, parasitic capacitance or the like which occurs in a core circuit sometimes varies in accordance with the value of a current flowing through the core circuit. As a result, there is a possibility that an output signal from a voltage control oscillation circuit does not oscillate in a desired oscillation frequency range. An oscillation signal generation circuit according to this embodiment adopts a configuration in which control is performed such that an output signal oscillates in a desired oscillation frequency range. A series of loops of confirmation and control of the range of an oscillation frequency in this embodiment is referred to as a frequency range control loop.

FIG. 11is a block diagram depicting a configuration example of the oscillation signal generation circuit according to this embodiment. Incidentally, inFIG. 11, such component elements as are found also inFIG. 2will be identified with the same reference characters and their detailed explanations will be omitted.

A voltage controlled oscillator1007depicted inFIG. 11has a configuration obtained by replacing the core circuit106in the voltage controlled oscillator107depicted inFIG. 2with a core circuit1006. Moreover, a calibration circuit1017has a configuration obtained by replacing the control signal generation circuit111in the calibration circuit115depicted inFIG. 2with a control signal generation circuit1011and adding a frequency adjustment circuit1015and a frequency determination circuit1016.

The control signal generation circuit1011has, in addition to the configuration of the control signal generation circuit111described inFIG. 2, a configuration by which the control signal generation circuit1011outputs a control signal TF to the frequency adjustment circuit1015and the frequency determination circuit1016. The control signal TF is a signal that makes the frequency adjustment circuit1015and the frequency determination circuit1016start control of the range of an oscillation frequency. The control signal generation circuit1011detects the oscillation continuance condition and then outputs the control signal TF to the frequency adjustment circuit1015and the frequency determination circuit1016.

The frequency adjustment circuit1015receives the output signal Voscwhich is output from the core circuit1006, tunes, for example, the frequency division ratio of a frequency divider provided in the frequency adjustment circuit1015or a reference frequency source in accordance with a predetermined order, and outputs the control signal Toscto the core circuit1006and the frequency determination circuit1016.

The frequency determination circuit1016receives the control signal Toscand determines whether or not the output signal Voscfalls within the oscillation frequency range based on whether or not the control signal Toscis a fixed value. If the control signal Toscis a fixed value, this indicates that the oscillation frequency is stabilized. The frequency determination circuit1016determines that the output signal Voscfalls within the oscillation frequency range if the control signal Toscis a fixed value at all the oscillation frequencies in a desired oscillation frequency range. On the other hand, if the frequency determination circuit1016determines that the output signal Voscdoes not fall within the oscillation frequency range, the frequency determination circuit1016outputs a frequency band switching control signal Tbandto the core circuit1006.

The core circuit1006has a variable capacitance whose capacitance value is variable and changes the capacitance value in accordance with the frequency band switching control signal Tband. The oscillation signal generation circuit depicted inFIG. 11can change the oscillation frequency by changing the capacitance value of the variable capacitance of the core circuit1006.

With the configuration described above, the oscillation signal generation circuit according to this embodiment can change the oscillation frequency of the output signal Vosc, after the output signal Voscoscillates, in such a way that the output signal Voscoscillates in a desired oscillation frequency range. The capacitance value controlled such that the output signal Voscoscillates in a desired oscillation frequency range is referred to as an oscillation frequency condition.

Incidentally, while control of the range of the oscillation frequency is being performed, the state sometimes enters a state in which the oscillation continuance condition is not met (that is, the oscillation of the output signal Voscsometimes stops). In this case, it is necessary to perform control to make the output signal Voscoscillate.

For example, based on the control signal Toscand the control signal TF, the frequency determination circuit1016outputs, to the control signal generation circuit1011, a control signal FDET indicating the state of control performed by the calibration circuit1017.

Specifically, first, in an initial state (that is, a state in which a control loop (an oscillation control loop) for starting oscillation is performed), the frequency determination circuit1016outputs, to the control signal generation circuit1011, the control signal FDET indicating that the oscillation control loop is executed.

If the frequency determination circuit1016receives the control signal TF, the frequency determination circuit1016determines whether or not the output signal Voscfalls within the oscillation frequency range. If the output signal Voscdoes not fall within the oscillation frequency range, the frequency determination circuit1016outputs, to the control signal generation circuit1011, the control signal FDET indicating that the frequency range control loop is being executed.

If the frequency determination circuit1016confirms that the oscillation of the output signal Voschas stopped, the frequency determination circuit1016outputs, to the control signal generation circuit1011, the control signal FDET indicating that the loop returns to the oscillation control loop from the frequency range control loop.

If the control signal generation circuit1011receives the control signal FDET indicating a return to the oscillation control loop, the control signal generation circuit1011returns to the control loop (the oscillation control loop) for starting oscillation and controls the current value or the resistance value. Then, after detecting the oscillation continuance condition again, the control signal generation circuit1011outputs the control signal TF to the frequency adjustment circuit1015and the frequency determination circuit1016, and the frequency range control loop is started again. Then, if the frequency determination circuit1016determines that the output signal Voscis oscillating in a desired oscillation frequency range, the frequency determination circuit1016outputs the control signal FDET indicating the completion of control to the control signal generation circuit1011.

As described above, with the configuration of the oscillation signal generation circuit described in this embodiment, by repeating the frequency range control loop and the oscillation control loop, it is possible to suppress phase noise while making the output signal fall within a desired frequency range (that is, meeting the oscillation frequency condition) and meeting the oscillation condition (the oscillation continuance condition).

Incidentally, the oscillation signal generation circuit described in this embodiment may have a storage, such as a memory or a register, which stores the oscillation starting condition, the oscillation continuance condition, and the oscillation frequency condition.

Incidentally, the calibration circuit in each embodiment may be configured so as to be implemented in a semiconductor integrated circuit such as LSI together with the voltage controlled oscillator. Moreover, the calibration circuit in each embodiment may be configured so as to be implemented in a semiconductor integrated circuit such as LSI which is different from the semiconductor integrated circuit in which the voltage controlled oscillator is implemented.

In the embodiments described above, the calibration circuit is integrated with the voltage controlled oscillator, but the calibration circuit may perform calibration of the voltage controlled oscillator alone. For example, the current value and the resistance value which are oscillation conditions may be determined by connecting the produced voltage controlled oscillator to the calibration circuit. With this configuration, it is possible to suppress a reduction in the yield of the produced voltage controlled oscillator.

It would be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present disclosure as shown in the specific embodiments without departing from the spirit or scope of the present disclosure as broadly described. The present embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive. It should be further noted that the individual features of the different embodiments of the present disclosure may individually or in arbitrary combination be subject matter to another present disclosure.

Further, although the various embodiments of the present disclosure have been explained to be configured using hardware, they may also be implemented by a combination of software modules and a hardware implementation. The software modules may be stored on any kind of computer readable storage media, for example RAM, EPROM, EEPROM, flash memory, registers, hard disks, CD-ROM, DVD, etc.

The blocks used for the description of the embodiments are typically realized as an LSI comprising at least one input terminal and an at least one output terminal, which is an integrated circuit. These may be individually chipped or part or all of the functional blocks may be collectively chipped. Here, the term “LSI” is used, but terms “IC”, “system LSI”, “super LSI”, and “ultra LSI” may be used depending on the degree of integration.

Furthermore, a method for realizing the integrated circuit is not limited to LSI, but the integrated circuit may be realized by a dedicated circuit or a general processor. An FPGA (Field Programmable Gate Array) that can be programmed after production of an LSI or a reconfigurable processor in which connection and settings of a circuit cell in the LSI can be reconfigured may be used.

Furthermore, if other techniques for achieving an integrated circuit that take the place of LSI appear as a result of the progress or derivation of the semiconductor technique, it is of course possible to realize integration of functional blocks by using such other techniques. One possibility is application of a biotechnology etc.

The oscillation signal generation circuit according to the present disclosure is suitably used in radar devices and communication devices that operate in a high frequency band exceeding 100 GHz.