System and method of providing atomicity to large writes to persistent memory

A system and a method are disclosed that provides atomicity for large data writes to persistent memory of an object storage system. A segment of persistent memory is allocated to an application. The persistent memory includes non-volatile memory that is accessible in a random access, byte-addressable manner. The segment of persistent memory is associated with first and second bits of a bitmap. The first bit is set indicating that the segment of persistent memory has been allocated. Data is received from the application for storage in the segment of persistent memory, and the second bit is set indicating that data in the segment of persistent memory has been finalized and is ready for storage in a storage medium that is different from persistent memory. The atomicity of the data in persistent memory may be determined based on the first bit and the second bit being set.

TECHNICAL FIELD

The subject matter disclosed herein relates to object storage systems. More specifically, the subject matter disclosed herein relates to a system and a method that provides atomicity for large data writes to persistent memory.

BACKGROUND

A single write to a persistent memory (e.g., nonvolatile dual inline memory (NVDIMM), storage class memory (SCM)) is consistent only within a specific size (e.g., a cache line) that is based on an underlying central processing unit (CPU), an operating system (OS), or both. When a large amount of data (greater than, for example, a cache line) is written to persistent memory, there is no guarantee that the entire data is consistent if a power-failure occurs during the write. Moreover, there is no standard technique for guaranteeing atomicity of large data writes to persistent memory and, therefore, there is no way to know which data are recoverable after a power failure.

SUMMARY

An example embodiment provides an object storage system that may include a storage medium, persistent memory and a controller. The persistent memory may include non-volatile memory that is accessible in a random access, byte-addressable manner. The controller may be coupled to the storage medium and the persistent memory, and the controller may be configured to: receive data from an application for storage in a segment of the persistent memory that has been allocated to the application in which the segment of the persistent memory may be associated with a first bit and a second bit of a bitmap, and the first bit may be set to indicate that the segment of the persistent memory has been allocated to the application; set the second bit of the bitmap to indicate that data in the segment of the persistent memory has been finalized and is ready for storage in a storage medium that is different from the persistent memory; and determine whether the data in the persistent memory has atomicity based on the first bit and the second bit being set. In one embodiment, the controller may be further configured to allocate the segment of the persistent memory to the application in response to a request received from the application. In still another embodiment, the controller is further configured to store the data in the segment of the persistent memory in the storage medium based on the second bit of the bitmap being set. The persistent memory may further include a plurality of segments each having a same size as another segment of the plurality of segments, and each segment may be associated with a corresponding first bit and a corresponding second bit of the bitmap. In one embodiment, the bitmap may include a first bitmap region and a second bitmap region, and the first bit associated with each of the plurality of segments may be located in the first bitmap region and the second bit associated with each of the plurality of segments may be located in the second bitmap region.

An example embodiment provides an object storage system that may include a storage medium, persistent memory and a controller. The persistent memory may include non-volatile memory that is accessible in a random access, byte-addressable manner. The controller may be coupled to the storage medium and the persistent memory, and may be configured to: allocate a segment of the persistent memory to an application in which the segment of the persistent memory may be associated with a first bit and a second bit of a bitmap; set the first bit of the bitmap to indicate that the segment of the persistent memory has been allocated; receive data from the application for storage in the segment of the persistent memory; set the second bit of the bitmap to indicate that data in the segment of the persistent memory has been finalized and is ready for storage in a storage medium that is different from the persistent memory; and determine whether the data in the persistent memory has atomicity based on the first bit and the second bit being set.

An example embodiment provides a method to provide atomicity for data writes to an object storage system that may include: allocating a segment of a persistent memory to an application in which the persistent memory may include non-volatile memory that is accessible in a random access, byte-addressable manner, and the segment of the persistent memory may be associated with a first bit and a second bit of a bitmap; setting the first bit of the bitmap to indicate that the segment of the persistent memory has been allocated; receiving data from the application for storage in the segment of the persistent memory; setting the second bit of the bitmap to indicate that data in the segment of the persistent memory has been finalized and is ready for storage in a storage medium that is different from the persistent memory; and determining whether the data in the persistent memory has atomicity based on the first bit and the second bit being set.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. It will be understood, however, by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail not to obscure the subject matter disclosed herein.

The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms “first,” “second,” etc., as used herein, are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. Such usage is, however, for simplicity of illustration and ease of discussion only; it does not imply that the construction or architectural details of such components or units are the same across all embodiments or such commonly-referenced parts/modules are the only way to implement some of the example embodiments disclosed herein.

As used herein, the term “module” refers to any combination of software, firmware and/or hardware configured to provide the functionality described herein in connection with a module. The software may be embodied as a software package, code and/or instruction set or instructions, and the term “hardware,” as used in any implementation described herein, may include, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, but not limited to, an integrated circuit (IC), system on-chip (SoC) and so forth. The various components and/or functional blocks disclosed herein may be embodied as modules that may include software, firmware and/or hardware that provide functionality described herein in connection with the various components and/or functional blocks.

The subject matter disclosed herein provides a system and a method that ensures atomicity, or complete updates (no partial updates), for large data writes to persistent memory. A segment of a persistent memory may be allocated to an application. The persistent memory may include non-volatile memory that is accessible in a random access, byte-addressable manner. The segment of the persistent memory may be associated with first and second bits of a bitmap. The first bit may be set indicating that the segment of the persistent memory has been allocated to an application. Data is then received from the application for storage in the segment of the persistent memory, and the second bit may be set indicating that data in the segment of the persistent memory has been finalized and is ready for storage in a storage medium that is different from the persistent memory. The atomicity of the data in the persistent memory may be determined based on the first bit and the second bit being set.

FIG. 1depicts a block diagram of an object storage system100that provides an atomicity for large writes to the object storage system according to the subject matter disclosed herein. The object storage system100may include a controller101, a data buffer102, a persistent memory103, and a storage media104. The controller101is communicatively coupled to each of the data buffer102, the persistent storage103, and the storage media104. The various components depicted inFIG. 1for the object storage system100may be implemented as one or more modules.

The controller101may include, for example, at least one microprocessor, at least one digital signal processor, at least one microcontroller, or the like. There may be a memory (not shown) that is coupled to the controller101that may store command code to be used by the controller101or a user data.

The buffer102may be configured to receive data and commands from an application106executing in a host system105, and send data and status information to the host system105. Although only one application106has been depicted as executing in the host system105, it will be understood that any number of applications106may be executing in the host system105. Additionally, it will also be understood that more than one host system105may be communicatively coupled to the object storage device100.

The persistent memory103may be non-volatile memory that is accessible in a random access, byte-addressable manner. In one example embodiment, the persistent memory103may be, for example, dynamic random access memory (DRAM) or static random access memory (SRAM) having a power supply provided with battery backup. In another example embodiment, the persistent memory103may be a nonvolatile (NV) dual inline memory module (DIMM). In still another embodiment, the persistent memory103may be a storage class memory (SCM). The persistent memory103provides persistent storage, for example, across a power-failure.

The storage media104may be a non-volatile mass-storage device, such as, but not limited to one or more solid-state drives (SSDs) and/or one or more hard drives (HDs). In one embodiment, the persistent memory103may be used by the controller101to store command code and/or user data that is used by the controller101. The storage media104may have a native block size. In one embodiment, the native block size of the storage media may be 512 bytes.

In one embodiment, when the application106writes object data to the object storage system100, the controller101allocates a segment, or buffer, of the persistent memory103to the application106. In one embodiment, there may be a plurality of segments in the persistent memory103in which each segment has a uniform size with each other segment. The uniform size of the segments may be any convenient size that allows metadata associated with each segment to be no larger than a single cache line for the controller101and/or operating system of the controller101. Two bits of metadata may be associated with each segment and are also stored in the persistent memory103.

FIG. 2depicts an example segment201and the metadata202that is associated with the segment201according to the subject matter disclosed herein. The metadata202is also stored in the persistent memory103and its size is guaranteed to be within a single cache line, which guarantees that the metadata are persisted once it has been written to the persistent memory103.

The metadata202may be further partitioned into two bitmap sections, or regions.FIG. 3depicts two example bitmap sections301and302in which the bits in each respective bitmap may represent one of two possible states of a persistent memory segment. The association between bits in the respective bitmaps and a segment may be defined by a relative position in the bitmap. A first state, an allocated state, indicated by a set bit in the allocated bitmap section301means that a corresponding segment is ready for use by an application, that is, the segment has been allocated to the application for use by the application. A second state, a committed state, indicated by a set bit in the committed bitmap302means that application data has been written into the segment and is guaranteed to be consistent.

That is, one bitmap (i.e., the allocated bitmap301) may be used to indicate whether a particular data segment has been allocated to an application, and the other bitmap (i.e., the committed bitmap302) may be used to indicate whether the data-segment is a committed entry.FIG. 4depicts an example association400between bits in an allocated bitmap401, a committed bitmap402and a data segment403that may be defined by the relative positions of the associated bit in the bitmaps. It should be noted that although it appears inFIG. 4that the allocated bitmap401and the committed bitmap402are the same size as the data segments403, such is not generally the case because each respective bit map only contains one bit for each data segment, whereas each segment has a uniform size with each other segment and the uniform size of the segments may be any convenient size that allows metadata associated with each segment (i.e., the allocated bitmap401and the committed bitmap402) to be no larger than a single cache line for the controller101and/or operating system of the controller101.

When a data segment is allocated, then the associated allocated bit may be set by, for example, the controller101.FIG. 5pictorially depicts a bit of an allocated bitmap being set at501when a data segment has been allocated to an application according to the subject matter disclosed herein. Subsequently at502, the applicantion writes data to the allocated data segment. When the contents of the data segment are finalized at503, then the data segment may be committed and the associated committed bit may be set by, for example, the controller101in response to an indication from the application that the data segment is finalized. The sequence from501to503may represent an example of a life-cycle of a data buffer. If a power failure occurs, the two bits associated with a segment may be checked afterwards, and if both bits are set then the data segment may be recovered after the power failure. If only one bit is set, then the data segment is marked as free by, for example, the controller101. This guarantees that finalized data segments are fully recoverable and also helps the system to avoid any resource leaks after a power failure by freeing up the data segments that were not committed and thereby allowing that data segment to be reused by other applications.

During a recovery from a power failure, the bitmap sections may be traversed in sequence. If both the allocated and committed bits are set, then the corresponding data segment is recoverable. If only one bit is set, then the corresponding data segment and header are considered to be free, and the corresponding allocated and committed bits are then reset to zero by, for example, the controller101.