Method and apparatus for placing an integrated circuit into a default mode of operation

An integrated circuit having a signal bus carrying address signals includes mode selection means. The mode selection means has a default state and a non-default state. The integrated circuit is placed into a default and generic mode of operation when the mode selection means is in the default state. An address signal applied to the integrated circuit is interpreted as a specific mode of operation when the integrated circuit is in the default and generic mode of operation. The mode selection means when in the non-default state precludes placement of the integrated circuit into the default and generic mode of operation.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits and, more particularly, to integrated circuits that are placed into different modes of operation.

BACKGROUND OF THE INVENTION

Integrated circuits (ICs) are often very complex devices from both a structural and functional standpoint. The testing of such structurally and functionally complex devices is often equally complex. In order to ensure the IC is functioning properly, manufacturers test the devices on sophisticated testing machines. Some ICs are placed into a test mode of operation in order to be properly and expediently tested. These ICs are operated in their final or end use in a normal or non-test mode of operation. Thus, the IC must be placed into a desired one of at least two different operational modes.

Typically, an IC is placed into a desired mode of operation through the application of a predetermined sequence of several mode selection signals to the input pins of the IC. In order for mode selection or other input signals to be received and decoded by the IC, the IC must be powered up and ready to accept input signals. This requires the IC to complete its power on or start-up process, which typically includes turning on voltage pumps, initializing chip logic, etc. The predetermined sequence of mode selection signals sent to the IC to invoke the desired mode of operation generally includes signals that set the operational mode register of the IC and thereby cause the IC to enter a desired “generic” operational mode. Further mode selection signals, referred to as mode entry keys, are provided to select a specific test or operational mode within the generic mode of operation.

The first mode selection signal is compared against a predetermined code. If the mode selection signal matches the predetermined code, the next signal is received as a mode entry key and decoded as such to thereby place the IC into a specific mode of operation that corresponds to the particular mode entry key. The mode selection signal, in essence, verifies that the signal to follow will be a mode entry key and will therefore correspond to a specific mode of operation. Thus, in order to place a conventional IC into a specific mode of operation, at least two separate mode selection signals, i.e., a mode selection signal and a mode entry key, must be issued and decoded.

The above-described signals are typically applied by a piece of equipment, such as, for example, a test machine or test station, which must be configured to apply the appropriate signals in the proper sequence that are required to place the particular IC into the desired operational mode. If, for example, the manufacturer desires to test a different IC on the same piece of test equipment that piece of test equipment must be reconfigured to apply the specific signals in the proper sequence to place that particular IC in the desired mode of operation. The required set up of the machine and the application of the signals to the IC consumes valuable time.

The first time, or first few times, an IC is powered up and operated is likely to be for the purpose of testing. However, each IC must nonetheless be individually placed into the desired mode of operation through the time-consuming and laborious process described above. Once the initial testing of the IC has been completed, subsequent entry into the test mode of operation is typically not necessary and may be undesirable.

Therefore, what is needed in the art is a method and apparatus that places an IC into a desired mode of operation in a reduced amount of time.

Furthermore, what is needed in the art is a method and apparatus that places an IC into a desired mode of operation without requiring the application of a plurality of input signals to the IC.

Moreover, what is needed in the art is a method and apparatus that places an IC into a default mode of operation and which can be reset to automatically enter a non-default mode of operation to thereby prevent inadvertent entry of the IC into the default mode of operation.

SUMMARY OF THE INVENTION

The present invention provides an integrated circuit having a default and generic mode of operation from which a specific mode of operation is entered in response to the application of a single address signal.

The invention comprises, in one form thereof, an integrated circuit including mode selection means having a default state and a non-default state. The integrated circuit is placed into a default and generic mode of operation when the mode selection means is in the default state. An address signal applied to the integrated circuit is interpreted as a specific mode of operation when the integrated circuit is in the default and generic mode of operation. The mode selection means when in the non-default state precludes placement of the integrated circuit into the default and generic mode of operation.

An advantage of the present invention is that the integrated circuit is placed in a default and generic mode of operation that enables entry into a specific mode of operation without requiring the application of a plurality of input/address signals.

Another advantage of the present invention is that the integrated circuit is placed into a desired specific mode of operation in a reduced amount of time.

Yet another advantage of the present invention is that the integrated circuit is automatically placed into a default mode of operation, and can be reset to automatically enter a non-default mode of operation to thereby prevent subsequent entry of the integrated circuit into the default mode of operation.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring now toFIG. 1, one embodiment of an integrated circuit of the present invention is shown. Integrated circuit (IC)10includes signal or control bus12, test mode decoder14, comparator16, test mode block18, mode decoder20, mode register22, and mode selection device24. Integrated circuit10is formed on substrate26, and is connected to at least one supply voltage28.

Generally, and as will be more particularly described hereinafter, mode selection device24is manufactured in a default state or condition which, in turn, automatically places IC10in a default and generic mode of operation, such as, for example, a generic test mode. With IC10thus placed into the default and generic mode of operation, a single address signal places IC10into a specific mode of operation, such as, for example, a specific test mode. IC10, when mode selection device24is removed from the default state and placed into a non-default state, requires at least one mode entry signal to enter a generic (non-default) mode of operation, such as, for example, a generic use mode. Further, at least one mode entry key signal must be applied to place IC10into a specific mode of operation, such as, for example, a specific use mode. However, with mode selection device24placed in the non-default state, entry of IC10into the default and generic mode of operation is disabled.

Control bus12carries various signals for distribution to the various functional blocks and circuitry of IC10. More particularly, control bus12carries mode register set (MRS) signal32, enable signal34, and address signal36. MRS signal32is received by, and an active MRS signal32enables, test mode decoder14and mode decoder20. Enable signal34is received by test mode decoder14and mode decoder20. An active enable signal34enables test mode decoder14, whereas an inactive enable signal34enables mode decoder20. Address signal36contains data, such as, for example, data that corresponds to a generic mode of operation, a specific mode of operation, or other commands and information for the various other functional blocks (not shown) of IC10.

Test mode decoder14is electrically connected to control bus12and receives MRS signal32, enable signal34and address signal36therefrom. Test mode decoder14is also electrically connected to comparator16. Test mode decoder14, when enabled by MRS signal32and enable signal34, passes address signal36to comparator16. If not enabled by MRS signal32and enable signal34, test mode decoder14blocks address signal36from being received by comparator16.

Comparator16receives address signal36from test mode decoder14when test mode decoder14is enabled by MRS signal32and enable signal34. Mode input16aof comparator16is electrically connected to mode selection device24. Comparator16passes address signal36to test mode block18dependent upon the logic level of mode input16a.Mode input16ais, in turn, dependent at least in part upon the state or condition of mode selection device24as will be more particularly described hereinafter. Thus, test mode block18receives address signal36only when test mode decoder14is enabled as described above and when mode selection device24is in the appropriate state.

Test mode block18, such as, for example, a conventional address decoder, receives address signal36from comparator16when comparator16is enabled by mode selection device24. Test mode block18, as is known in the art, decodes or interprets address signal36to select and place IC10in a specific mode of operation, such as, for example, a specific test mode, corresponding to or indicated by address signal36.

Mode decoder20, such as, for example, a conventional address decoder, is electrically connected to control bus12and receives MRS signal32, enable signal34and address signal36therefrom. Mode decoder20is also electrically connected to mode register22. Mode decoder20, when enabled by MRS signal32and enable signal34, passes address signal36to mode register22.

Mode register22, such as, for example, a conventional address decoder, receives address signal36from mode decoder20when decoder20is enabled as described above. Mode register22decodes or interprets address signal36to select and place IC10in a generic or general mode of operation, such as, for example, a general test or non-test operational mode.

Mode selection device24, such as, for example, a laser fuse or electronic fuse, is interconnected between supply voltage28and mode input16aof comparator16. Mode selection device24in a default state or condition electrically connects mode input16aof comparator16to a default voltage or logic level, such as supply voltage28. In a non-default state or condition, mode selection device24connects mode input16ato non-default voltage or logic level, such as, for example, ground potential. Dependent at least in part upon the logic level of mode input16a,comparator16passes or blocks address signal36from test mode block18. Those skilled in the art will recognize that a current-limiting resistor (not shown) may be placed between mode input16aand ground. Mode selection device24is, for example, formed integrally with substrate26. However, it is to be understood that mode selection device24can be alternately configured, such as, for example, as a discrete device commonly packaged with or as an input to IC10.

In use, IC10is configured to power-up in a default and generic mode of operation, and to be placed into a specific mode of operation in response to the application of a single input signal. More particularly, mode selection device24is manufactured or set in a predetermined state or condition to thereby place a corresponding default logic level at mode input16aof comparator16. With MRS signal32and enable signal34enabling test mode decoder14to pass address signal36to comparator16, the logic level at mode input16adetermines whether comparator16passes or blocks address signal36to/from test mode block18. With mode input16aat the default logic level, such as, for example, a high logic level, comparator16is configured to pass address signal36to test mode block18. Test mode block18, in turn, decodes or interprets address signal36as indicating a specific operational mode, and places IC10in a specific mode of operation, such as, for example, a specific test mode, that corresponds to or is indicated by the data contained within address signal36.

Conversely, with mode selection device24removed from the default state and placed into a non-default state, and with MRS signal32and enable signal34remaining enabled, test mode decoder14remains enabled to pass address signal36to comparator16. However, due to mode selection device24being in the non-default state, mode input16aof comparator16is now at a non-default logic level. Thus, comparator16is configured to block address signal36from test mode block18. Address signal36is rejected, i.e., is not passed onto or decoded by either of test mode block18or mode register22, and therefore is precluded from being interpreted as a specific operational mode.

Alternatively, with MRS signal32active and enable signal34inactive address signal36is received and interpreted by mode register22to thereby place IC10into a generic (but not default) mode of operation. Further alternatively, with MRS signal32inactive test mode decoder14and mode decoder22are disabled, and address signal36is interpreted by various other functional circuits (not shown) of IC10to perform other functions.

As will be understood by those skilled in the art, placing IC10in a generic or general mode of operation initializes various circuitry, such as, for example, logic gates and registers, in preparation for receiving and appropriately interpreting subsequent commands, such as, for example, specific mode selection or mode entry key signals. In contrast, placing IC10in a specific mode of operation, such as a specific test mode or use mode, commences the operation of that particular test mode. Mode selection device24places a default logic voltage level at mode input16aof comparator16to thereby place IC10into a generic default operational mode. With IC10in the generic default operating mode, the application of a single address signal36places IC10directly into a specific operational mode upon. The application of one or more mode selection signals is not required in order to place IC10into a generic operational mode. Nor is the application of more than one mode entry key signal required in order to place IC10into a specific operational mode. Thus, IC10is placed into a desired and specific mode of operation with the application of a single address signal36. The amount of time required to set-up or program a piece of test equipment to issue the proper sequence of signals to place IC10into a desired mode of operation is thereby reduced. Further, the amount of time required for a piece of test equipment to place IC10into a desired mode of operation is also reduced, thereby saving costly test time.

Referring now toFIG. 2, a flow chart of one embodiment of a method of placing an integrated circuit into a default mode of operation is shown. Method50includes the steps of applying voltages52, power-up sequence54, evaluate mode selection device56, enter default generic operating mode58, and enter non-default operating mode60.

Applying voltages step52includes the application of the at least one supply voltage28, such as, for example, VDD, VSS, VREF, ground voltages, etc., required for IC10to operate. Power-up sequence54includes the initialization of the internal circuitry of IC10, such as, for example, mode decoder20, mode register22, logic circuitry and voltage pumps (not shown), etc., of IC. Exactly what is performed in each of applying voltages step52and power-up sequence54will vary depending on the particular configuration of the particular IC.

Evaluate mode selection device step56determines whether the integrated circuit enters a default generic mode of operation or a non-default mode of operation. More particularly, evaluate step56includes checking the state or condition of mode selection device24. Depending upon the outcome of evaluate step56, IC10enters either the default generic mode of operation or waits for one or more address signals36to place IC10into a non-default mode of operation. If evaluate step56determines that the mode selection device24indicates that IC10is to be operated in the default generic mode of operation, method50proceeds to execute the step of entering default generic operating mode58.

The step of entering default generic operating mode58prepares IC10to enter a specific mode of operation, such as, for example, a specific test mode, upon the receipt of a single address signal36. The default specific mode of operation contained within the single address signal36is decoded by test mode block18. Thus, only one address signal36containing a single test mode entry key need be issued to IC10in order for IC10to enter a specific mode of operation from the default generic operating mode.

The step of entering non-default operating mode60places IC10into one of a plurality of other, i.e., non-default, operating modes, such as, for example, a generic use mode of operation. Further address signals36containing additional data, such as, for example, mode selection signals and/or mode entry keys, are required in order to place IC10into a specific operational mode.

As described above, mode selection device24is manufactured in a default state or condition wherein a default logic level is placed upon mode input16aof comparator16. The default logic level at mode input16aof comparator16places IC10into a default generic operational mode. With IC10in the default generic operating mode, the application to IC10of a single address signal36places IC10into a specific operating mode within the default generic operating mode. Thus, IC10is placed into one of a plurality of specific modes of operation, such as, for example, a test mode, through the application of a single address signal36to IC10. In essence, mode selection device24in the default state switches on the default generic mode of operation, and in the non-default state precludes placing IC10into the generic mode of operation.

In the embodiment shown, mode selection device24when in a default position places mode input16aat a default logic level to thereby enable comparator16to pass address signal36to test mode block18. However, it is to be understood that the present invention can be alternately configured, such as, for example, to block address signal36from being passed to test mode block18when mode selection device24and the logic level at mode input16aare at the default state and logic level, respectively.

In the embodiment shown, mode selection device24when placed in the non-default state precludes the entry of IC10into the default and generic mode of operation is disabled. However, it is to be understood that the present invention can be alternately configured to enable IC10to be placed into a generic test and/or a specific test mode of operation regardless of the condition (i.e., default or non-default) of mode selection device24. Such a configuration enables the testing of the integrated circuit subsequent to the placing of mode selection device24into the non-default state.