Bottom Air Spacer by Oxidation

VFET devices having a porous bottom air spacer formed by oxidation are provided. In one aspect, a VFET device includes: at least one fin present on a substrate, wherein the at least one fin serves as a vertical fin channel of the VFET device; a bottom source/drain region at a base of the at least one fin; a bottom air-containing spacer disposed on the bottom source/drain region; a gate stack alongside the at least one fin; a top spacer above the gate stack at a top of the at least one fin; and a top source/drain region at a top of the at least one fin. A method of forming a VFET device is also provided.

FIELD OF THE INVENTION

The present invention relates to vertical field-effect transistor (VFET) devices, and more particularly, to VFET devices having a porous bottom air spacer and techniques for fabrication thereof using an oxidation process.

BACKGROUND OF THE INVENTION

As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical field effect transistor (VFET) devices are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. VFET devices are being pursued as a viable device option for continued CMOS scaling.

There are, however, some notable challenges associated with implementing a VFET design. For instance, with the vertically-oriented configuration of a VFET, there is often a large area of overlap area between the gate stack and the bottom source/drain region. This large area of overlap can undesirably lead to a significant amount of parasitic capacitance between the gate stack and the bottom source/drain region.

Parasitic capacitance refers to the capacitance that exists between device components in close proximity to one another (in this case the gate stack and the bottom source/drain region) which results in a stored electric charge. Such parasitic capacitance can negatively impact VFET device performance.

Therefore, techniques for efficiently and effectively reducing parasitic capacitance in VFET devices would be desirable.

SUMMARY OF THE INVENTION

The present invention provides vertical field-effect transistor (VFET) devices having a porous bottom air spacer formed by oxidation. In one aspect of the invention, a VFET device is provided. The VFET device includes: at least one fin present on a substrate, wherein the at least one fin serves as a vertical fin channel of the VFET device; a bottom source/drain region at a base of the at least one fin; a bottom air-containing spacer disposed on the bottom source/drain region; a gate stack alongside the at least one fin; a top spacer above the gate stack at a top of the at least one fin; and a top source/drain region at a top of the at least one fin.

In another aspect of the invention, another VFET device is provided. The VFET device includes: at least one fin present on a substrate, wherein the at least one fin serves as a vertical fin channel of the VFET device; a bottom source/drain region at a base of the at least one fin, wherein the bottom source/drain region is in direct contact with a first portion of a sidewall of the at least one fin; a bottom air-containing spacer disposed directly on the bottom source/drain region, wherein the bottom air-containing spacer is in direct contact with a second portion of the sidewall of the at least one fin; a gate stack alongside the at least one fin; a top spacer above the gate stack at a top of the at least one fin; and a top source/drain region at a top of the at least one fin.

In yet another aspect of the invention, a method of forming a VFET device is provided. The method includes: patterning at least one fin in a substrate; forming a bottom source/drain region at a base of the at least one fin; forming a bottom air spacer on the bottom source/drain region using oxidation, wherein the bottom air spacer includes air-containing pores distributed throughout the bottom spacer; forming a gate stack alongside the at least one fin, wherein the at least one fin serves as a vertical fin channel of the VFET device; forming a top spacer above the gate stack at a top of the at least one fin; and forming a top source/drain region at a top of the at least one fin. For instance, a bottom spacer can be formed on the bottom source/drain region, wherein the bottom spacer includes silicon germanium (SiGe) having from about 50% Ge to about 100% Ge; and the bottom spacer can be annealed in an oxygen ambient to form the bottom air spacer on the bottom source/drain region.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

As provided above, with a vertical field effect transistor (VFET) device architecture there is a considerable area of overlap between the gate stack and the bottom source/drain region. This overlap can undesirably lead to high parasitic capacitance which negatively impacts the device performance.

A bottom spacer is often employed to offset the gate stack from the bottom source/drain region. Conventional designs typically employ an oxide or nitride dielectric material such as silicon nitride (SiN) for forming the bottom spacer. Even so, the effect of parasitic capacitance on the device performance remains significant.

On the other hand, air has a significantly lower dielectric constant than these conventional oxide and nitride dielectric spacer materials. For instance, by way of example only, at room temperature (i.e., 25° C. (°C)), air has a dielectric constant of 1.00059, whereas SiN has a dielectric constant of about 9.5. Thus, being able to effectively implement a bottom air spacer in a VFET device design would greatly reduce the parasitic capacitance.

Advantageously, provided herein are techniques for forming a porous bottom air spacer for a VFET device using an oxidation process. As will be described in detail below, the bottom spacers are formed from a semiconductor material such as silicon germanium (SiGe) having a high germanium (Ge) content (also referred to herein as ‘high Ge content SiGe’). The high Ge content SiGe is then oxidized to form a porous oxide (e.g., silicon oxide (SiOx)) bottom air spacer between the gate stack and the bottom source/drain region. By ‘porous’ it is meant that there are air-containing pores formed (by way of the present process) throughout the bottom spacer.

Given the above overview, an exemplary methodology for fabricating a VFET device is now described by way of reference toFIGS.1-17. As shown inFIG.1, the process begins with the patterning of a plurality of fins106in a substrate102. According to an exemplary embodiment, substrate102is a bulk semiconductor wafer, such as a bulk silicon (Si), bulk germanium (Ge), bulk silicon germanium (SiGe) and/or bulk III-V semiconductor wafer. Alternatively, substrate102can be a semiconductor-on-insulator (SOI) wafer. A SOI wafer includes a SOI layer separated from an underlying substrate by a buried insulator. When the buried insulator is an oxide it is also referred to herein as a buried oxide or BOX. The SOI layer can include any suitable semiconductor material(s), such as Si, Ge, SiGe and/or a III-V semiconductor. Further, substrate102may already have pre-built structures (not shown) such as transistors, diodes, capacitors, resistors, interconnects, wiring, etc.

Standard lithography and etching techniques can be employed to pattern the fins106in substrate102. For instance, with standard lithography and etching techniques, a lithographic stack (not shown), e.g., photoresist/organic planarizing layer (OPL)/anti-reflective coating (ARC), is used to pattern fin hardmasks104with the footprint and location of each of the fins106. Suitable hardmask materials include, but are not limited to, nitride hardmask materials such as silicon nitride (SiN), silicon oxynitride (SiON) and/or silicon carbide nitride (SiCN). A directional (i.e., anisotropic) etching process such as reactive ion etching (RIE) is then employed to transfer the pattern from the fin hardmask104to the substrate102, forming fins106in the substrate102. Alternatively, the fin hardmasks104can be formed by other suitable techniques, including but not limited to, sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and other self-aligned multiple patterning (SAMP). As shown inFIG.1, the as-patterned fins106extend partway through the substrate102.

As will be described in detail below, the bottom source/drain regions will be grown at a base of the fins106, followed by the bottom spacers (with later oxidation to form the porous bottom air spacer). To do so, a unique bilayer spacer-based process is employed whereby a first sidewall spacer is formed alongside the fins106, followed by an etch to extend the base of the fins106below the first sidewall spacer. A second sidewall spacer is then formed over the first sidewall spacer (i.e., forming the bilayer spacer), followed by another etch to further extend the base of the fins106below the second sidewall spacer.

The bilayer spacer is then used to place the bottom source/drain region at the base of the fins106. After which, the second sidewall spacer is removed and the first sidewall spacer is used to place the bottom spacer over the bottom source/drain region at the base of the fins106. The first sidewall spacer is then also removed.

Namely, as shown inFIG.1, a first sidewall spacer108is formed alongside the fins106. By way of example only, the first sidewall spacer108can be formed by depositing a layer of a spacer material onto the fins106and exposed surfaces of the substrate102. A directional (i.e., anisotropic) etching process such as RIE can then be used to remove the material deposited onto horizontal surfaces. What remains is the spacer material on the sidewalls of the fins106that serves as the first sidewall spacer108.

Suitable materials for the first sidewall spacer108include, but are not limited to, SiN, silicon carbide (SiC), silicon borocarbonitride (SiBCN) and/or silicon oxycarbonitride (SiOCN) which can be deposited using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). According to an exemplary embodiment, the first sidewall spacer108is formed having a thickness of from about 2 nanometers (nm) to about 5 nm and ranges therebetween.

With the first sidewall spacer108now protecting the sidewalls of the fins106, as highlighted above, an etch is then performed to recess the substrate102in between the fins106thereby extending the base of the fins106below the first sidewall spacer108. SeeFIG.2. A directional (i.e., anisotropic) etching process such as RIE can be employed for this recess etch.

As shown inFIG.2, the first sidewall spacer108covers a portion of the underlying substrate during this recess etch. As a result, the bottom of the fins106is now wider than the portions of the fins106adjacent to the first sidewall spacer108. Namely, the portions of the fins106adjacent to the first sidewall spacer108have a width W1 and the bottom of the fins106have a width W2, whereby W1 is less than W2, i.e., W1 < W2. However, as will be described in detail below, the bottom of the fins106is next trimmed to reduce its width. Trimming the width at the bottom of the fins has notable advantages such as, among other things, reducing a distance between the bottom source/drain regions and the vertical fin channel (see below).

Namely, a lateral etch of the exposed base of the fins106is next performed to trim/reduce the width of the bottom of the fins106from W2 to W2'. SeeFIG.3. According to an exemplary embodiment, the reduced width W2' is approximately the same as the width W1 of the fins106adjacent to the first sidewall spacer108, i.e., W2' ≈ W1. For instance, W2' differs from W1 by less than or equal to about 0.25 nm. A non-directional (i.e., isotropic) etching process such as a wet chemical etch or a gas phase etch can be employed to trim the base of the fins106below the first sidewall spacer108.

As highlighted above, a second sidewall spacer402is next formed alongside the fins106over the first sidewall spacer108. SeeFIG.4. This combination of first sidewall spacer108and second sidewall spacer402is what is being referred to herein as a bilayer spacer. Like first sidewall spacer108, the second sidewall spacer402can be formed by depositing a layer of a spacer material onto the fins106and exposed surfaces of the substrate102over the first sidewall spacer108. A directional (i.e., anisotropic) etching process such as RIE can then be used to remove the material deposited onto horizontal surfaces. What remains is the spacer material on the first sidewall spacer108along the sidewalls of the fins106that serves as the second sidewall spacer402.

The materials chosen for the first/second sidewall spacers108and402need to enable the selective removal of the second sidewall spacers402relative to the first sidewall spacers108. Namely, as will be described in detail below, this will enable the formation of the bottom spacers on the bottom source/drain regions at the base of the fins106. By way of example only, suitable materials for the second sidewall spacer402include, but are not limited to, silicon nitride (SiN) which can be deposited using a process such as CVD, ALD, or PVD. According to an exemplary embodiment, the second sidewall spacer402is formed having a thickness of from about 2 nm to about 8 nm and ranges therebetween.

Notably, as shown inFIG.4, the second sidewall spacer402covers the first sidewall spacer108as well as the sidewall of the base of the fins106below the first sidewall spacer108. Namely, the second sidewall spacer402is in direct contact with the fins106below the first sidewall spacer108. As will be described in detail below, this placement of the second sidewall spacer402along the fins106below the first sidewall spacer108, will first enable the formation of the bottom source/drain regions, followed by the bottom spacer.

Next, in the same manner as described above, the substrate is again recessed to extend the base of the fins106below the bilayer spacer (i.e., first sidewall spacer108/second sidewall spacer402) followed by a lateral trimming of the exposed base of the fins106. Namely, with the first sidewall spacer108and the second sidewall spacer402protecting the sidewalls of the fins106, an etch is performed to further recess the substrate102in between the fins106thereby extending the base of the fins106below the bilayer spacer. SeeFIG.5. A directional (i.e., anisotropic) etching process such as RIE can be employed for this recess etch.

As shown inFIG.5, the bilayer spacer (i.e., first sidewall spacer108/second sidewall spacer402) covers a portion of the underlying substrate during this recess etch. As a result, the bottom of the fins106is now wider than the portions of the fins106adjacent to the bilayer spacer. Namely, the portions of the fins106adjacent to the bilayer spacer have the same width W1 as described above, and the bottom of the fins106have a width W3, whereby W1 is less than W2, i.e., W1 < W2. Based on the combined thickness of the first sidewall spacer108and second sidewall spacer402, the width W3 at the bottom of the fins106is also greater than the width W2 resulting from the first recess etch (seeFIG.2- described above), i.e., W2 < W3. An optional trim at the bottom of the fins106can next be performed to reduce its width. It is notable that, while trimming the exposed base of the fins106below the bilayer spacer can help improve resistance at the bottom source/drain region, doing so is not required, and embodiments are contemplated herein where trimming of the fins106below the bilayer spacer is not performed.

However, in the exemplary embodiment shown illustrated inFIG.6, a lateral etch of the exposed base of the fins106below the bilayer spacer is performed to trim/reduce the width of the bottom of the fins106from W3 to W3'. According to an exemplary embodiment, the reduced width W3' is approximately the same as the width W1 of the fins106adjacent to the bilayer spacer, i.e., W3' ≈ W1. For instance, W3' differs from W1 by less than or equal to about 0.25 nm. A non-directional (i.e., isotropic) etching process such as a wet chemical etch or a gas phase etch can be employed to trim the base of the fins106below the bilayer spacer.

Bottom source/drain regions702are then formed at the base of the fins106beneath the bilayer spacer (i.e., first sidewall spacer108/second sidewall spacer402). SeeFIG.7. According to an exemplary embodiment, bottom source/drain regions702are formed from an in-situ doped (i.e., during growth) or ex-situ doped (e.g., via ion implantation) epitaxial material such as epitaxial Si, epitaxial SiGe, etc. grown at the base of the fins106and doped with an n-type or p-type dopant. Suitable n-type dopants include, but are not limited to, phosphorous (P) and/or arsenic (As). Suitable p-type dopants include, but are not limited to, boron (B). Growth of the bottom source/drain regions702is limited to the portion of the sidewall of the fins106beneath the bilayer spacer.

The second sidewall spacer402is then removed from the fins106selective to the first sidewall spacer108. SeeFIG.8. As shown inFIG.8, the first sidewall spacer108remains in place covering the upper portions of the fins106. However, removing the second sidewall spacer402exposes a portion of the sidewall at the base of the fins106above the bottom source/drain regions702. As provided above, the second sidewall spacer402can be formed from a material such as SiN. In that case, an etch using a fluorine- and hydrogen-containing plasma can be employed to selectively remove the second sidewall spacer402.

A bottom spacer902is then formed on the bottom source/drain regions702at the base of the fins106beneath the first sidewall spacer108. SeeFIG.9. According to an exemplary embodiment, the bottom spacer902is formed from a semiconductor material such as SiGe having a high Ge content (also referred to herein as ‘high Ge content SiGe’). By way of example only, the term ‘high Ge content SiGe’ as used herein refers to SiGe having from about 50% Ge to about 100% Ge (i.e., pure Ge) and ranges therebetween. For instance, in one non-limiting example, the bottom spacer902is formed from SiGe having greater than or equal to about 60% Ge, where in some cases the bottom spacer902is formed from SiGe having greater than or equal to about 75% Ge, and even further in some cases the bottom spacer902is formed from SiGe having greater than or equal to about 80% Ge. As highlighted above, the high Ge content SiGe will later be oxidized to form a porous oxide (e.g., SiOx) bottom air spacer over the bottom source/drain regions702. Advantageously, the lower dielectric constant of the bottom air spacer helps to greatly reduce the parasitic capacitance.

In one embodiment, the bottom spacer902is formed from high Ge content SiGe epitaxial grown on the bottom source/drain regions702at the base of the fins106. Epitaxial SiGe can be grown using Si and Ge precursors such as silane (SiH4) or dichlorosilane and germane (GeH4) or digermane (Ge2H6), respectively. The Ge content can be regulated by controlling the flow of the Ge precursor during growth. According to an exemplary embodiment, the bottom spacer902is formed having a thickness of from about 5 nm to about 20 nm and ranges therebetween. Growth of the bottom spacer902is limited to the portion of the sidewall of the fins106above the bottom source/drain regions702and beneath the first sidewall spacer108.

Following formation of the bottom spacer902, the first sidewall spacer108is removed. The particular etch chemistry employed to remove the first sidewall spacer108can be selected based on the material chosen for the first sidewall spacer108. For instance, by way of example only, if the first sidewall spacer108is formed from SiN (see above), then a wet chemical etch with phosphoric acid (H3PO4) can be used to selectively remove the first sidewall spacer108. Gate stacks are then formed alongside the fins106and over the bottom source/drain regions702and bottom spacer902. SeeFIG.10. As shown inFIG.10, the gate stacks include a gate dielectric1002disposed on the fins106and at least one workfunction-setting metal1004disposed on the gate dielectric1002. Although not explicitly shown in the figures, an interfacial oxide may be formed on the exposed surfaces of the fins106prior to the gate dielectric1002such that the gate dielectric1002is disposed on the fins106over the interfacial oxide. By way of example only, the interfacial oxide can be formed on the exposed surfaces of the fins106by a thermal oxidation, a chemical oxidation, or any other suitable oxide formation process. According to an exemplary embodiment, the interfacial oxide has a thickness of from about 0.5 nm to about 5 nm and ranges therebetween, e.g., about 1 nm.

Suitable materials for the gate dielectric1002include, but are not limited to, SiOx, SiN, silicon oxynitride (SiOxNy), high-κ materials, or any combination thereof. The term “high-κ” as used herein refers to a material having a relative dielectric constant κ which is much higher than that of silicon dioxide (e.g., a dielectric constant κ is about 25 for hafnium oxide (HfO2) rather than 3.9 for SiO2). Suitable high-κ materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiOxNy), tantalum oxide (TaOx), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3) and/or lead zinc niobite (Pb(Zn,Nb)O). The high-κ material can further include dopants such as lanthanum (La), aluminum (Al) and/or magnesium (Mg). The gate dielectric1002can be deposited using a process or combination of processes such as, but not limited to, thermal oxidation, chemical oxidation, thermal nitridation, plasma oxidation, plasma nitridation, CVD, ALD, etc. According to an exemplary embodiment, the gate dielectric1002has a thickness of from about 1 nm to about 5 nm and ranges therebetween.

Suitable workfunction-setting metals1004include, but are not limited to, titanium nitride (TiN), titanium aluminum nitride (TiAlN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium carbide (TiC) titanium aluminum carbide (TiAlC), tantalum carbide (TaC) and/or hafnium carbide (HfC). The workfunction-setting metal(s)1004can be deposited using a process or combination of processes such as, but not limited to, CVD, ALD, PVD, sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc. According to an exemplary embodiment, the workfunction-setting metal(s)1004has a thickness of from about 5 nm to about 10 nm and ranges therebetween.

An encapsulation liner1006is then formed on the gate stacks (i.e., gate dielectric1002and workfunction-setting metal(s)1004) over the fins106. The encapsulation liner1006will serve to protect the gate stacks during subsequent processing steps. Suitable materials for the encapsulation liner1006include, but are not limited to, nitride materials such as SiN and/or silicon carbide nitride (SiCN) and/or amorphous silicon, which can be deposited using a process such as CVD, ALD or PVD. According to an exemplary embodiment, encapsulation liner1006has a thickness of from about 1 nm to about 5 nm and ranges therebetween.

The bottom spacer902is then oxidized to form a bottom air-containing spacer1102between the bottom source/drain regions702and the gate stacks (i.e., gate dielectric1002and workfunction-setting metal(s)1004). SeeFIG.11. As provided above, the bottom spacer902is formed from high Ge content SiGe, i.e., SiGe having from about 50% Ge to about 100% Ge (i.e., pure Ge) and ranges therebetween, such as SiGe having greater than or equal to about 60% Ge, SiGe having greater than or equal to about 75% Ge, or even SiGe having greater than or equal to about 80% Ge. The presence of Ge in the bottom spacer902catalyzes the oxidation reaction, and an increase in temperature increases the reaction rate. See, for example, Mohamed A. Rabie et al., “A kinetic model for the oxidation of silicon germanium alloys,” Journal of Applied Physics, 98, 074904 (October 2005) (11 pages) (hereinafter “Rabie”). A higher Ge content also increases the reaction rate relative to, e.g., the underlying bottom source/drain regions702. Thus, if the bottom source/drain regions702contain Ge (see above), it is preferable that the Ge content of the bottom spacer902is greater than the Ge content of the bottom source/drain regions702. For instance, according to an exemplary embodiment, the bottom source/drain regions702contain from about 0% Ge to about 50% Ge and ranges therebetween. That way, the present techniques can be implemented to form the bottom air-containing spacer1102by oxidation with little if any oxidation also occurring in the bottom source/drain regions702.

It was found herein that, by employing the present oxidation techniques, the resulting bottom air-containing spacer1102formed is pure SiOx meaning that there is no Ge present in the final bottom air-containing spacer1102. Without being bound by any particular theory, it is believed that during this oxidation process, the Ge is sublimated as germanium oxide (GeO) which leaves behind pure SiOx as the bottom air-containing spacer1102, with the vacancies in the material left by the Ge sublimation creating air-containing pores in the bottom air-containing spacer1102. Namely, as shown inFIG.11, bottom air-containing spacer1102has air-containing pores1104distributed throughout, these air-containing pores1104having a bubble shape. According to an exemplary embodiment, each of the air-containing pores1104has a size of from about 1 nm to about 15 nm and ranges therebetween, which is measured as the largest diameter d of each of the air-containing pores1104(seeFIG.11). The size of the air-containing pores1104formed can depend on factors such as the Ge content and/or thickness of the bottom spacer902(see above) and/or the temperature of the thermal oxidation anneal (see below). Namely, the higher the Ge content of the bottom spacer902and/or the greater the thickness of the bottom spacer902and/or the greater the temperature of the thermal oxidation anneal (within the limits provided herein), the greater the size of the resulting the air-containing pores1104will be. As described above, the presence of the air-containing pores1104in the bottom air-containing spacer1102helps to greatly reduce the parasitic capacitance between the gate stacks (i.e., gate dielectric1002and workfunction-setting metal(s)1004) and the bottom source/drain regions702. Thus, in one exemplary embodiment, the goal is to produce the largest (sized) air-containing pores1104possible in the bottom air-containing spacer1102.

According to an exemplary embodiment, the bottom spacer902is oxidized using a thermal oxidation process whereby the VFET device structure is annealed in an oxygen (O2)-containing ambient under conditions (e.g., temperature, duration, etc.) sufficient to form bottom air-containing spacer1102(i.e., pure SiOx) having air-containing pores1104distributed throughout. In one exemplary embodiment, the annealing is performed at a temperature of greater than about 700° C. (°C), for example, at a temperature of from about 700° C. to about 900° C. and ranges therebetween, for a duration of from about 1 minute to about 10 minutes and ranges therebetween. According to an exemplary embodiment, the anneal is performed with a ramp rate of from about 25° C./second (s) to about 50° C./s and ranges therebetween. Notably, in addition to O2, the process can also have hydrogen (H2) gas. For instance, in one exemplary embodiment, from about 5 percent (%) to about 15% H2is mixed with O2to form the (i.e., pure SiOx) bottom air-containing spacer1102.

An interlayer dielectric (ILD)1202is then deposited over the gate stacks (i.e., gate dielectric1002and workfunction-setting metal(s)1004) and fins106. SeeFIG.12. Suitable materials for ILD1202include, but are not limited to, oxide materials such as SiOx and/or organosilicate glass (SiCOH) and/or ultralow-κ interlayer dielectric (ULK-ILD) materials, e.g., having a dielectric constant κ of less than 2.7. Suitable ultralow-κ dielectric materials include, but are not limited to, porous organosilicate glass (pSiCOH). A process such as CVD, ALD, or PVD can be used to deposit the ILD1202. Following deposition, the ILD1202can be polished down to the encapsulation liner1006using a process such as chemical mechanical polishing (CMP).

The encapsulation liner1006is now exposed at the tops of the fins106. Exposure of the encapsulation liner1006enables its removal, as well as the underlying fin hardmasks104and gate stacks from the top of the fins106. SeeFIG.13. As shown inFIG.13, the encapsulation liner1006, the workfunction-setting metal(s)1004, the gate dielectric1002, and the fin hardmasks104have been removed from the top of the fins106. The fins106will serve as vertical fin channels of the VFET device.

According to an exemplary embodiment, the encapsulation liner1006, the workfunction-setting metal(s)1004and the gate dielectric1002are recessed such that a top surface of the encapsulation liner1006, the workfunction-setting metal(s)1004and the gate dielectric1002is present below a top surface of the fins106(i.e., vertical fin channels). Doing so creates gaps1302between the sidewall at the tops of the fins106and the ILD1202. SeeFIG.13. As will be described in detail below, a top spacer will be formed in these gaps, and top source/drain regions will be formed on the exposed tops of the fins106. The bottom spacer902and the top spacer will serve to offset the bottom source/drain regions702and the top source/drain regions from the gate stack, respectively. A directional (i.e., anisotropic) etching process such as RIE and/or a non-directional (i.e., isotropic) etching process such as a wet chemical etch or a gas phase etch can be employed to remove the encapsulation liner1006, the workfunction-setting metal(s)1004, the gate dielectric1002, and the fin hardmasks104from the top of the fins106.

A top spacer1402is then formed above the gate stack in the gaps1302alongside the tops of the fins106(i.e., vertical fin channels). SeeFIG.14. Suitable materials for the top spacer1402include, but are not limited to, oxide spacer materials such as SiOx and/or silicon oxycarbide (SiOC) and/or nitride spacer materials such as SiN, silicon-boron-nitride (SiBN), siliconborocarbonitride (SiBCN) and/or silicon oxycarbonitride (SiOCN), which can be deposited into the gaps1302using a process such as CVD, ALD or PVD. Following deposition, an etch-back of the spacer material (e.g., using an oxide- or nitride-selective RIE as the case may be) is used to form the top spacer1402in the gaps1302. Based on this process, according to an exemplary embodiment, a top surface of the top spacer1402is coplanar with the top surface of the fins106. SeeFIG.14. Further, this leaves a top surface of the fins106exposed alongside the top spacer1402which will enable the formation of the top source/drain regions.

Namely, the above-described process of removing the encapsulation liner1006, the workfunction-setting metal(s)1004, the gate dielectric1002, and the fin hardmasks104from the top of the fins106, followed by the formation of the top spacer1402alongside the tops of the fins106creates trenches1404over the fins106. As shown inFIG.14, the tops of the fins106are exposed at the bottom of the trenches1404. Top source/drain regions1502are then formed in the trenches1404at the tops of the fins106(i.e., vertical fin channels). SeeFIG.15.

According to an exemplary embodiment, top source/drain regions1502are formed from an in-situ doped (i.e., during growth) or ex-situ doped (e.g., via ion implantation) epitaxial material such as epitaxial Si, epitaxial SiGe, etc. grown at the tops of the fins106and doped with an n-type or p-type dopant. As provided above, suitable n-type dopants include, but are not limited to, P and/or As. Suitable p-type dopants include, but are not limited to, B. Following growth, the epitaxial material can be planarized using a process such as CMP. As a result, the top surface of the top source/drain regions1502is coplanar with a top surface of the ILD1202. SeeFIG.15.

Contacts are next formed to the top source/drain regions1502. To do so, an ILD1602is first deposited onto the ILD1202over the fins106(i.e., vertical fin channels). For clarity, the terms ‘first’ and ‘second’ may also be used herein when referring to the ILD1202and the ILD1602. Suitable materials for ILD1602include, but are not limited to, oxide materials such as SiOx and/or SiCOH and/or ULK-ILD materials such as pSiCOH. A process such as CVD, ALD, or PVD can be used to deposit the ILD1602. Following deposition, the ILD1602can be polished using a process such as CMP. Standard lithography and etching techniques (see above) are then employed to pattern contact trenches1604in the ILD1602. As shown inFIG.16, one of the contact trenches1604is present in the ILD1602over each of the top source/drain regions1502.

The contact trenches1604are then filled with a metal or a combination of metals to form contacts1702to the top source/drain regions1502. SeeFIG.17. Suitable metals include, but are not limited to, copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni) and/or platinum (Pt). The metal(s) can be deposited into the contact trenches1604using a process such as evaporation, sputtering, or electrochemical plating. Following deposition, the metal overburden can be removed using a process such as CMP. Prior to depositing the metal(s), a barrier layer (not shown) can be deposited into and lining the contact trenches1604. Use of such a barrier layer helps to prevent diffusion of the metal(s) into the surrounding ILD1602. Suitable barrier layer materials include, but are not limited to, ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium (Ti) and/or titanium nitride (TiN). Additionally, a seed layer (not shown) can be deposited into and lining the contact trenches1604prior to metal deposition, i.e., in order to facilitate plating of the metal into the contact trenches1604.

As shown inFIG.17, there are some unique structural features of the present VFET device to be noted. For instance, based on the above-described bilayer spacer (i.e., first sidewall spacer108/second sidewall spacer402) design and process sequence, the bottom source/drain regions702are present at the base of the fins106alongside (and in direct contact with) a first portion1704of the sidewall of the fins106. The bottom air-containing spacer1102is present directly on the bottom source/drain regions702alongside (and in direct contact with) a second portion1706of the sidewall of the fins106which is above the first portion1704of the sidewall.

With the above-described process the high Ge content SiGe bottom spacer902is placed prior to the gate stack (i.e., the gate dielectric1002and workfunction-setting metal(s)1004). However, the (thermal) oxidation to form the bottom air-containing spacer1102occurs after formation of the gate stack. This process may result in some re-oxidation of the gate dielectric1002which can generate defects in the material and thereby degrade device performance. In order to avoid re-oxidation of the gate dielectric1002, an alternative process flow is contemplated herein where both the placement of the high Ge content SiGe bottom spacer902and the (thermal) oxidation to form the bottom air spacer occur before the gate stack is formed, thereby avoiding altogether any exposure of the gate dielectric1002to re-oxidation.

This alternative exemplary embodiment is now described by way of reference toFIGS.18-21. The process begins in exactly the same manner as the example described in conjunction with the description ofFIGS.1-9above, i.e., with the patterning of fins106in the substrate102using fin hardmasks104, the formation of the bilayer spacer (i.e., first sidewall spacer108/second sidewall spacer402) along with the associated recess and trimming at the base of the fins106in exactly the same manner as described above, formation of the bottom source/drain regions702at the base of the fins106, removal of the second sidewall spacer402, and formation of the bottom spacer902. As provided above, the bottom spacer902is formed from high Ge content SiGe, i.e., SiGe having from about 50% Ge to about 100% Ge (i.e., pure Ge) and ranges therebetween, such as SiGe having greater than or equal to about 60% Ge, SiGe having greater than or equal to about 75% Ge, or even SiGe having greater than or equal to about 80% Ge. Thus, what is depicted inFIG.18follows from the structure ofFIG.9.

In this case, however, a capping layer1802is next formed on the high Ge content SiGe bottom spacer902. SeeFIG.18. Suitable materials for the capping layer1802include, but are not limited to, nitride materials such as SiN, SiON and/or SiCN. According to an exemplary embodiment, the capping layer1802is formed using a directional deposition process whereby a greater amount of the capping layer material is deposited on horizontal surfaces (including on top of the bottom spacer902) as compared to vertical surfaces (such as along sidewalls of the fins106/first sidewall spacer108). Thus, when an etch is used on the capping layer material, the timing of the etch needed to remove the capping layer material from the vertical surfaces will leave the capping layer1802shown inFIG.18on bottom spacer902since a greater amount of the capping layer material was deposited on the bottom spacer902. By way of example only, a high-density plasma (HDP) chemical vapor deposition (CVD) or physical vapor deposition (PVD) process can be used for directional film deposition, and a nitride-selective isotropic etch can be used to remove the (thinner) capping layer material deposited onto the vertical surfaces. According to an exemplary embodiment, the capping layer1802is formed have a thickness of greater than about 1 nm.

The oxidation of the high Ge content SiGe bottom spacer902is then carried out in the same manner as described above, except with the capping layer1802rather than the gate stack being present over the bottom spacer902, to form the bottom air-containing spacer1102between the bottom source/drain regions702and the capping layer1802. Namely, according to an exemplary embodiment, the bottom spacer902is oxidized using a thermal oxidation process whereby the VFET device structure is annealed in an O2-containing ambient under conditions (e.g., temperature, duration, etc.) sufficient to form the bottom air-containing spacer1102(i.e., pure SiOx) having air-containing pores1104distributed throughout. SeeFIG.19. In one exemplary embodiment, the annealing is performed at a temperature of greater than about 700° C., for example, at a temperature of from about 700° C. to about 900° C. and ranges therebetween, for a duration of from about 1 minute to about 10 minutes and ranges therebetween. According to an exemplary embodiment, the anneal is performed with a ramp rate of from about 25° C./s to about 50° C./s and ranges therebetween. Notably, in addition to O2, the process can also have H2gas. For instance, in one exemplary embodiment, from about 5% to about 15% H2is mixed with O2to form the (i.e., pure SiOx) bottom air-containing spacer1102. As described above, the presence of the air-containing pores1104in the bottom air-containing spacer1102helps to greatly reduce the parasitic capacitance between the gate stacks and the bottom source/drain regions702. The presence of the gate stack or, in this case, the capping layer1802helps promote formation of the (i.e., pure SiOx) bottom air-containing spacer1102during this oxidation process for example by providing a surface on which the SiOx being formed can adhere to.

Following oxidation, the capping layer1802is then selectively removed. SeeFIG.20. As provided above, the capping layer1802can be formed from a nitride material (e.g., SiN, SiON and/or SiCN). In that case, a nitride-selective etch such as a nitride-selective RIE can be employed to remove the capping layer1802.

The first sidewall spacer108is also selectively removed as described above and the gate stacks are then formed alongside the fins106and over the bottom source/drain regions702and bottom air-containing spacer1102. SeeFIG.21. In the same manner as described above, the gate stacks include a gate dielectric1002disposed on the fins106and at least one workfunction-setting metal1004disposed on the gate dielectric1002. Although not explicitly shown in the figures, an interfacial oxide may be formed on the exposed surfaces of the fins106prior to the gate dielectric1002such that the gate dielectric1002is disposed on the fins106over the interfacial oxide. Suitable materials, dimensions and fabrication techniques for the gate dielectric1002, the workfunction-setting metal(s)1004and the interfacial oxide have been provided above.

The encapsulation liner1006is then formed on the gate stacks (i.e., gate dielectric1002and workfunction-setting metal(s)1004) over the fins106. As described above, the encapsulation liner1006will serve to protect the gate stacks during subsequent processing steps. Suitable materials, dimensions and fabrication techniques for the encapsulation liner1006have been provided above.

The remainder of the process is the same as that described in conjunction with the description ofFIGS.12-17above. Namely, the (first) ILD1202is deposited over the gate stacks, the encapsulation liner1006, the workfunction-setting metal(s)1004, the gate dielectric1002, and the fin hardmasks104are removed from the top of the fins106, the top spacer1402are formed alongside the tops of the fins106(i.e., vertical fin channels), the top source/drain regions1502are formed at the tops of the fins106, the (second) ILD1602is deposited onto the ILD1202over the fins106, and the contacts1702are formed in the ILD1602to the top source/drain regions1502. Thus, according to an alternative embodiment, what is depicted inFIG.12can also follow from the structure ofFIG.21.