Semiconductor packages including a multi-chip stack

Semiconductor packages are provided. The semiconductor package includes a first semiconductor chip to which a first elevated pillar bump is connected, a second semiconductor chip stacked on the first semiconductor chip to leave revealed the first elevated pillar bump and configured to include a first chip pad disposed on a center region of the second semiconductor chip, a third semiconductor chip offset and stacked on the second semiconductor chip to leave revealed the first chip pad, and a chip supporter supporting an overhang of the third semiconductor chip.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. 119(a) to Korean Application No. 10-2018-0006508, filed on Jan. 18, 2018, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates to semiconductor package technologies and, more particularly, to semiconductor packages including a multi-chip stack and methods of fabricating the same.

2. Related Art

Recently, semiconductor packages having a high density and a high performance have been required in various electronic systems. In addition, the semiconductor packages have been developed to have a relatively small form factor because mobile systems require compact semiconductor packages. A flip chip stack technique may be attractive as a package technique for realizing high performance semiconductor packages. A general flip chip stack technique has been proposed to provide a dual-die stack structure including a couple of chips or a couple of dies which are stacked on a substrate. Accordingly, it may be necessary to develop a package technique for increasing the number of semiconductor chips embedded in the package without increasing a thickness of the package.

SUMMARY

According to an embodiment, there is provided a semiconductor package. The semiconductor package includes a first semiconductor chip to which a first elevated pillar bump is connected and a second semiconductor chip stacked on the first semiconductor chip to leave revealed the first elevated pillar bump and configured to include a first chip pad disposed in a center region of the second semiconductor chip. The center region of the second semiconductor chip is spaced apart from an edge region of the second semiconductor chip. A third semiconductor chip is stacked on the second semiconductor chip to be laterally offset from the second semiconductor chip to leave revealed the first chip pad. The third semiconductor chip includes an overhang laterally protruding further than a side surface of the second semiconductor chip. A chip supporter is provided to support the overhang of the third semiconductor chip. An encapsulation layer is disposed to encapsulate a stack structure of the first, second, and third semiconductor chips. Circuit interconnection patterns are disposed on the encapsulation layer and electrically connected to the first elevated pillar bump and the first chip pad.

According to another embodiment, there is provided a semiconductor package. The semiconductor package includes a first semiconductor chip to which a first elevated pillar bump is connected, a second semiconductor chip stacked on the first semiconductor chip to leave revealed the first elevated pillar bump and configured to include a first chip pad, an encapsulation layer encapsulating a stack structure of the first and second semiconductor chips, opening holes substantially penetrating the encapsulation layer to expose the first elevated pillar bump and the first chip pad, and circuit interconnection patterns configured to include via portions and extension portions. The via portions are connected to the first elevated pillar bump and the first chip pad through the opening holes, and the extension portions extend from the via portions onto the encapsulation layer.

According to yet another embodiment, there is provided a method of fabricating a semiconductor package. The method includes providing a first semiconductor chip to which a first elevated pillar bump is connected and stacking a second semiconductor chip on the first semiconductor chip to leave revealed the first elevated pillar bump. The second semiconductor chip has a first chip pad disposed in a center region of the second semiconductor chip, which is spaced apart from an edge region of the second semiconductor chip. A third semiconductor chip is stacked on the second semiconductor chip to be laterally offset from the second semiconductor chip and to leave revealed the first chip pad. An encapsulation layer is formed to encapsulate a stack structure of the first, second, and third semiconductor chips. Circuit interconnection patterns, which are electrically connected to the first elevated pillar bump and the first chip pad, are formed on the encapsulation layer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be construed to be different according to ordinary skill in the art to which the embodiments belong. If defined in detail, the terms may be construed according to the definitions. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

It will be understood that although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, but not used to define only the element itself or to mean a particular sequence.

It will also be understood that when an element or layer is referred to as being “on,” “over,” “below,” “under,” or “outside” another element or layer, the element or layer may be in direct contact with the other element or layer, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between” versus “directly between” or “adjacent” versus “directly adjacent”).

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom” and the like, may be used to describe an element and/or feature's relationship to another element(s) and/or feature(s) as, for example, illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as below and/or beneath other elements or features would then be oriented above the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A semiconductor package may include electronic devices such as semiconductor chips or semiconductor dies. The semiconductor chips or the semiconductor dies may be obtained by separating a semiconductor substrate such as a wafer into a plurality of pieces using a die sawing process. The semiconductor chips may correspond to memory chips, logic chips (including application specific integrated circuits (ASIC) chips), or system-on-chips (SoC). The memory chips may include dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, NAND-type flash memory circuits, NOR-type flash memory circuits, magnetic random access memory (MRAM) circuits, resistive random access memory (ReRAM) circuits, ferroelectric random access memory (FeRAM) circuits or phase change random access memory (PcRAM) circuits which are integrated on the semiconductor substrate. The logic chips may include logic circuits which are integrated on the semiconductor substrate. The semiconductor package may be employed in communication systems such as mobile phones, electronic systems associated with biotechnology or health care, or wearable electronic systems.

Same reference numerals refer to same elements throughout the specification. Even though a reference numeral is not mentioned or described with reference to a drawing, the reference numeral may be mentioned or described with reference to another drawing. In addition, even though a reference numeral is not shown in a drawing, it may be mentioned or described with reference to another drawing.

FIG. 1is a cross-sectional view illustrating a first semiconductor chip301and a second semiconductor chip302stacked to be offset from the first semiconductor chip301on a cover wafer100.FIG. 2is a cross-sectional view illustrating the first semiconductor chip301. In the specification, the terms “first semiconductor chip,” “second semiconductor chip,” “third semiconductor chip,” “fourth semiconductor chip,” and the like are only used to distinguish one semiconductor chip from another semiconductor chip, but not used to mean a particular sequence.

Referring toFIG. 1, the cover wafer100may be a dummy wafer without any integrated circuits. The dummy wafer used as the cover wafer100may be a silicon wafer. The dummy wafer, used as the cover wafer100, may be a semiconductor wafer, a metal wafer, or a dielectric wafer. The cover wafer100may act as a base member supporting the first and second semiconductor chips301and302stacked on the cover wafer100. A portion of the cover wafer100may be used as a protection member that protects the first and second semiconductor chips301and302in a semiconductor package.

The first semiconductor chip301may be attached to a first surface101of the cover wafer100using a first adhesive layer210. The cover wafer100may have the first surface101and a second surface102which are located opposite the first semiconductor chip301. The first adhesive layer210may bond a third surface309of the first semiconductor chip301to the first surface101of the cover wafer100.

The first semiconductor chip301may include a chip body310providing the third surface309. The chip body310may also provide a fourth surface308which is located opposite the cover wafer100. First chip pads330may be exposed at the fourth surface308of the chip body310. Referring toFIG. 2, the chip body310may include first integrated circuit elements313. The first integrated circuit elements313may be integrated in or on a first semiconductor layer311. The first semiconductor layer311may be a silicon layer. A first interlayer insulation layer312may be disposed on the first semiconductor layer311to cover the first integrated circuit elements313, and a first internal interconnection structure314may be disposed in the first interlayer insulation layer312. The first interlayer insulation layer312may include a plurality of dielectric layers which are vertically stacked and may provide the fourth surface308of the chip body310. The first internal interconnection structure314may electrically connect the first chip pads330to the first integrated circuit elements313disposed in the chip body310.

The first chip pads330may correspond to center pads which are located on a surface of a center region301C of the chip body310. The center region301C may be a region which is spaced apart from the first edge regions301E of the chip body310. The first semiconductor chip301may include redistributed interconnection lines350extending from the first chip pads330located in the center region301C toward the first edge region301E. First elevated pillar bumps390may be disposed on and connected to one of the first edge regions301E. Each of the redistributed interconnection lines350may include a connection portion351, and the first elevated pillar bumps390may be disposed on the connection portions351of the redistributed interconnection lines350. The first elevated pillar bumps390may be electrically connected to the connection portions351of the redistributed interconnection lines350. A dielectric layer370may be formed on the fourth surface308of the chip body310to cover the redistributed interconnection lines350. The dielectric layer370may be formed to leave open and expose the connection portions351of the redistributed interconnection lines350. The first elevated pillar bumps390may be connected to the connection portions351which are exposed by the dielectric layer370.

Referring toFIGS. 1 and 2, the first elevated pillar bumps390may act as connection members having a vertical length H1. The length H1of the first elevated pillar bumps390may correspond to a height of the first elevated pillar bumps390upwardly protruding from the chip body310. The first elevated pillar bumps390may be provided to substantially heighten a location of the connection portions351of the redistributed interconnection lines350. The first elevated pillar bumps390may be formed of a metal material, for example, a copper material. The first elevated pillar bumps390may be formed to have the length H1of approximately several tens of micrometers to approximately one hundred and several tens of micrometers. The length H1of the first elevated pillar bumps390may be substantially equal to a thickness H2of the first semiconductor chip301. The length H1of the first elevated pillar bumps390may be greater than the thickness H2of the first semiconductor chip301. The thickness H2of the first semiconductor chip301may correspond to a distance between the third surface309of the first semiconductor chip301and a surface of the dielectric layer370opposite the first interlayer insulation layer312.

Referring again toFIG. 1, the second semiconductor chip302may be stacked on the first semiconductor chip301to be laterally offset by the first semiconductor chip301. The second semiconductor chip302may be attached to the first semiconductor chip301using a second adhesive layer230. The second semiconductor chip302may be a semiconductor chip having substantially the same configuration as the first semiconductor chip301. For example, the second semiconductor chip302may include second chip pads332corresponding to center pads and second elevated pillar bumps392disposed on a second edge region302E of the second semiconductor chip302.

The second semiconductor chip302may be laterally offset relative to the first semiconductor chip301to leave the first edge region301E of the first semiconductor chip301revealed. Accordingly, the first semiconductor chip301and the second semiconductor chip302may be vertically stacked on the cover wafer100to provide a step structure. The second semiconductor chip302may be disposed so that the second edge region302E is adjacent to the first edge region301E of the first semiconductor chip301. Thus, the second elevated pillar bumps392may be adjacent to the first elevated pillar bumps390.

A side surface of the second semiconductor chip302may be disposed to face the first elevated pillar bumps390in a lateral direction. The first elevated pillar bumps390may be laterally spaced apart from the second semiconductor chip302by a certain distance. The length H1of the first elevated pillar bumps390may be greater than a vertical thickness H3of the second semiconductor chip302. Thus, top surfaces390S of the first elevated pillar bumps390may be located at a level which is higher than a top surface of the second semiconductor chip302. More specifically, the top surfaces390S of the first elevated pillar bumps390may be located at a level which is higher than the second chip pads332. The second chip pads332may be disposed in a center region of the second semiconductor chip302.

The second elevated pillar bumps392may be formed to have substantially the same shape as the first elevated pillar bumps390. For example, a vertical length H4of the second elevated pillar bumps392may be substantially equal to the length H1of the first elevated pillar bumps390. The length H4of the second elevated pillar bumps392may be greater than the thickness H3of the second semiconductor chip302. The length H4of the second elevated pillar bumps392may be greater than the thickness H2of the first semiconductor chip301.

In some embodiments, the length H4of the second elevated pillar bumps392may be less than the length H1of the first elevated pillar bumps390.

FIG. 3is a cross-sectional view illustrating a third semiconductor chip401stacked on the second semiconductor chip302and laterally offset from the second semiconductor chip302.FIG. 4is a cross-sectional view illustrating the third semiconductor chip401.

Referring toFIG. 3, the third semiconductor chip401may be laterally offset relative to the second semiconductor chip302. The third semiconductor chip401may be attached to the second semiconductor chip302using a third adhesive layer240. The third semiconductor chip401may be laterally offset from the second semiconductor chip302to leave the second edge region302E of the second semiconductor chip302revealed. The second semiconductor chip302and the third semiconductor chip401may be vertically stacked on the first semiconductor chip301provide a step structure. Thus, the third semiconductor chip401may be disposed on the second semiconductor chip302such that a side surface of the second semiconductor chip302may face the second elevated pillar bumps392in a lateral direction. The length H4of the second elevated pillar bumps392may be greater than a vertical thickness H5of the third semiconductor chip401. Thus, top surfaces392S of the second elevated pillar bumps392may be located at a level which is higher than a fifth surface409of the third semiconductor chip401opposite the second semiconductor chip302. In some embodiments, the second elevated pillar bumps392may upwardly protrude from the second semiconductor chip302to have a vertical length H4substantially equal to a thickness of the third semiconductor chip401.

Referring toFIGS. 3 and 4, the third semiconductor chip401may be configured without any elevated pillar bumps unlike the first and second semiconductor chips301and302. The third semiconductor chip401may include third chip pads430which remain exposed on the fifth surface409corresponding to a top surface of the third semiconductor chip401. The third semiconductor chip401may include second integrated circuit elements413. The second integrated circuit elements413may be integrated in or on a second semiconductor layer411. The second semiconductor layer411may be a silicon layer. A second interlayer insulation layer412may be disposed on the second semiconductor layer411to cover the second integrated circuit elements413, and a second internal interconnection structure414may be disposed in the second interlayer insulation layer412. The second interlayer insulation layer412may include a plurality of dielectric layers which are vertically stacked and may provide the fifth surface409. The second internal interconnection structure414may electrically connect the third chip pads430to the second integrated circuit elements413disposed in the third semiconductor chip401.

The second integrated circuit elements413may include cell transistors constituting a memory device. The first integrated circuit elements (313ofFIG. 2) may also include cell transistors constituting a memory device. The third semiconductor chip401may be a memory chip, and the first and second semiconductor chips301and302may also be memory chips.

The third chip pads430may correspond to center pads which are located in a center region401C of the third semiconductor chip401. The third semiconductor chip401may be configured not to include any redistributed interconnection lines and any dielectric layer covering the redistributed interconnection lines, unlike the first and second semiconductor chips301and302.

Referring again toFIG. 3, a chip supporter500may be disposed on the cover wafer100to be spaced apart from the third semiconductor chip401. The chip supporter500may be attached to the first surface101of the cover wafer100using a fourth adhesive layer260. The cover wafer100may support the chip supporter500. The chip supporter500may be provided to have a vertical thickness H7which is substantially equal to a total height H6of the first, second, and third semiconductor chips301,302, and401. For example, the thickness H7of the chip supporter500may correspond to a value that remains after subtracting a thickness of the fourth adhesive layer260from the total height H6of the first, second, and third semiconductor chips301,302, and401. Thus, a top surface509of the chip supporter500may be located at substantially the same level as the fifth surface409that corresponds to a top surface of the third semiconductor chip401.

FIG. 5is a cross-sectional view illustrating a fourth semiconductor chip402stacked to be laterally offset on the third semiconductor chip401.

Referring toFIG. 5, the fourth semiconductor chip402may be stacked to be laterally offset by the third semiconductor chip401. The second, third, and fourth semiconductor chips302,401, and402may be sequentially stacked on the first semiconductor chip301to be offset relative to the first semiconductor chip301in substantially the same offset direction. An offset distance454of the fourth semiconductor chip402relative to the third semiconductor chip401may be greater than an offset distance453of the third semiconductor chip401relative to the second semiconductor chip302.

The center region401C where the third chip pads430are located may remain uncovered by the fourth semiconductor chip402. The center region401C of the third semiconductor chip401may be spaced apart from an edge region of the third semiconductor chip401. The fourth semiconductor chip402may be offset such that the third chip pads430of the third semiconductor chip401remain exposed, and the fourth semiconductor chip402may partially overlap with the third semiconductor chip401. Thus, a portion of the fourth semiconductor chip402may laterally protrude beyond a side surface of the third semiconductor chip401to provide an overhang402P. A width of the overhang402P of the fourth semiconductor chip402may be greater than a width of an overlap portion402L of the fourth semiconductor chip402, which overlaps the third semiconductor chip401.

The chip supporter500may support the overhang402P of the fourth semiconductor chip402. The chip supporter500may prevent the overhang402P of the fourth semiconductor chip402from warping downwardly. That is, the chip supporter500may prevent warpage or deformation of the overhang402P of the fourth semiconductor chip402to prevent cracks from forming in the fourth semiconductor chip402. The fourth semiconductor chip402may be attached to both the third semiconductor chip401and the chip supporter500using a fifth adhesive layer250.

The chip supporter500may be a dummy die. The chip supporter500may be provided to have the same material as the fourth semiconductor chip402. For example, the chip supporter500may be a silicon die. The chip supporter500may have a width which is half a width of the fourth semiconductor chip402. Alternatively, the width of the chip supporter500may be less than half the width of the fourth semiconductor chip402.

The fourth semiconductor chip402may be a semiconductor chip having substantially the same function and shape as the third semiconductor chip401. The fourth semiconductor chip402may be provided to have a center region402C and fourth chip pads431disposed on the center region402C.

Referring toFIG. 6, the photosensitive material layer600may be formed on the first surface101of the cover wafer100to cover the first, second, third, and fourth semiconductor chips301,302,401, and402. The photosensitive material layer600may be formed by laminating a photosensitive dielectric film on the first surface101of the cover wafer100. The photosensitive material layer600may act as an encapsulation layer that covers, encapsulates, and protects the first, second, third, and fourth semiconductor chips301,302,401, and402.

The photosensitive material layer600may include a photosensitive polymer material such as a photosensitive polyimide material or a photosensitive polybenzoxazole material. Because the photosensitive material layer600includes a photosensitizer, a solubility of the photosensitive material layer600may depend on an exposure process applied to the photosensitive material layer600. For example, a solubility of the photosensitive material layer600exposed to a light such as an ultraviolet (UV) ray may be different from a solubility of the photosensitive material layer600not exposed to a light such as an ultraviolet (UV) ray.

FIG. 7is a cross-sectional view illustrating a step of partially exposing the photosensitive material layer600.

Referring toFIG. 7, some portions of the photosensitive material layer600may be selectively exposed to a light using a photolithography apparatus. Specifically, a photomask700may be located over the photosensitive material layer600, and an exposure light790may be irradiated onto the photomask700. A portion of the exposure light790may be blocked by light blocking regions710of the photomask700, and the remaining portion791of the exposure light790may pass through light permeation regions720of the photomask700to reach predetermined portions of the photosensitive material layer600. Thus, the exposure light790may change a chemical property of the predetermined portions of the photosensitive material layer600and may change a solubility of the predetermined portions of the photosensitive material layer600.

The exposure light790may infiltrate into the photosensitive material layer600to form exposed regions609of the photosensitive material layer600. The exposed regions609may correspond to regions which are aligned to overlap with the first and second elevated pillar bumps390and392and the third and fourth chip pads430and431. An exposure critical depth D that the exposure light790is able to effectively travel into the photosensitive material layer600may be limited to a certain depth. The exposure critical depth D indicates an effective depth of the photosensitive material layer600which is normally exposed by the exposure light790. That is, the exposure light790being intense enough to normally expose the photosensitive material layer600may not reach a portion of the photosensitive material layer600, which is lower than the exposure critical depth D. Accordingly, the exposed regions609should not be formed deeper than the exposure critical depth D.

In the present disclosure, the first and second elevated pillar bumps390and392may be formed so that top surfaces of the first and second elevated pillar bumps390and392are located within a range of the exposure critical depth D. Thus, the exposed regions609may be formed to contact the top surfaces of the first and second elevated pillar bumps390and392.

FIG. 8is a cross-sectional view illustrating a step of forming opening holes605in the photosensitive material layer600.

Referring toFIG. 8, the exposed regions (609ofFIG. 7) may be selectively removed by developing the photosensitive material layer600. As a result, the opening holes605which substantially penetrate the photosensitive material layer600may be formed. The opening holes605may be formed using a single exposure step and a single development step. The opening holes605may include first to fourth opening holes601,602,603, and604. The first opening holes601may be aligned with the first elevated pillar bumps390and may be formed to expose top surfaces of the first elevated pillar bumps390. The second opening holes602may be aligned with the second elevated pillar bumps392and may be formed to expose top surfaces of the second elevated pillar bumps392. The third opening holes603may be aligned with the third chip pads430and may be formed to expose top surfaces of the third chip pads430. The fourth opening holes604may be aligned with the fourth chip pads431and may be formed to expose top surfaces of the fourth chip pads431. Even though the opening holes605are formed at different positions and are formed to have different depths, all of the opening holes605may be simultaneously formed using a single lithography step including a single exposure step and a single development step.

Referring toFIGS. 7 and 8, the first and second semiconductor chips301and302may be located out of the range of the exposure critical depth D. Thus, it may be difficult to form the exposed regions609directly extending to surfaces of the first and second semiconductor chips301and302. That is, it may be difficult to form the first and second opening holes601and602that directly expose surfaces of the first and second semiconductor chips301and302. At least top surfaces of the first and second elevated pillar bumps390and392may be directly exposed by the first and second opening holes601and602because the first and second elevated pillar bumps390and392extend upwardly so that the top surfaces of the first and second elevated pillar bumps390and392are located within range of the exposure critical depth D. Accordingly, the first and second elevated pillar bumps390and392may act as connectors that connect the first and second semiconductor chips301and302to the first and second opening holes601and602.

The fourth chip pads431may be spaced apart from the third chip pads430by the offset distance (454ofFIG. 5). Thus, the fourth opening holes604may also be spaced apart from the third opening holes603by the offset distance (454ofFIG. 5). The third chip pads430may be spaced apart from the second elevated pillar bumps392by at least half a width of the third semiconductor chip401. Thus, the third opening holes603may also be spaced apart from the second opening holes602by at least half a width of the third semiconductor chip401. As such, because the second, third, and fourth opening holes602,603, and604are spaced apart from each other by a relatively long distance, it may be possible to prevent the second, third, and fourth opening holes602,603, and604from being connected to each other.

FIG. 9is a cross-sectional view illustrating a step of forming circuit interconnection patterns800.

Referring toFIG. 9, the circuit interconnection patterns800may be formed on the photosensitive material layer600. Each of the circuit interconnection patterns800may be formed to include a via portion810filling any one of the opening holes605, and an extension portion830extending from the via portion810onto a surface606of the photosensitive material layer600. The via portions810of the circuit interconnection patterns800may directly contact the first and second elevated pillar bumps390and392and the third and fourth chip pads430and431, respectively. The via portions810of the circuit interconnection patterns800may be directly connected to the first and second elevated pillar bumps390and392and the third and fourth chip pads430and431, respectively. The via portions810of the circuit interconnection patterns800may be directly and respectively connected to the first and second elevated pillar bumps390and392and the third and fourth chip pads430and431through the opening holes605.

Because the first opening holes601may be extend deeper than a lower portion of the third semiconductor chip401, a vertical length of the via portions810filling the first opening holes601may be greater than a thickness of the third semiconductor chip401. Because the third opening holes603may be formed deeper than a lower portion of the fourth semiconductor chip402, a vertical length of the via portions810filling the third opening holes603may be greater than a thickness of the fourth semiconductor chip402. In contrast, because the fourth opening holes604are formed shallower than a thickness of the fourth semiconductor chip402, a vertical length of the via portions810filling the fourth opening holes604may be less than a thickness of the fourth semiconductor chip402.

A dielectric layer910may be formed on the surface606of the photosensitive material layer600to leave portions of the extension portions830of the circuit interconnection patterns800revealed. Outer connectors900may be formed on the portions of the extension portions830of the circuit interconnection patterns800which remain revealed. The outer connectors900may be formed of bumps or solder balls. In such a case, some of the extension portions830may be formed to extend onto an edge region of the photosensitive material layer600to not overlap with the first to fourth semiconductor chips301,302,401, and402. Accordingly, some of the outer connectors900may be formed to not overlap with the first to fourth semiconductor chips301,302,401, and402.

The cover wafer100on which the outer connectors900may be cut using a singulation process such as a die sawing process to provide a plurality of discrete semiconductor packages10, one of which is illustrated inFIG. 10. Before the singulation process is performed, a recession process may be applied to the second surface102of the cover wafer100to reduce a thickness of the cover wafer100.

Referring toFIG. 10, the discrete semiconductor package10may include the first to fourth semiconductor chips301,302,401, and402which are stacked on any one of a plurality of cover dies100D produced by cutting the cover wafer100. The cover die100D may be a silicon die. The chip supporter500may be supported by the cover die100D. The first elevated pillar bumps390may be disposed on the first edge region301E of the first semiconductor chip301, and the second elevated pillar bumps392may be disposed on the second edge region302E of the second semiconductor chip302. The overhang402P of the fourth semiconductor chip402may be supported by the chip supporter500.

A stack of the first to fourth semiconductor chips301,302,401, and402may be covered and encapsulated by the photosensitive material layer600. The opening holes605may be formed to substantially penetrate the photosensitive material layer600using a single photolithography step including a single exposure step and a single development step. The opening holes605may be filled with the via portions810, and the via portions810may extend onto the photosensitive material layer600to provide the extension portions830. The via portions810and the extension portions830may constitute the circuit interconnection patterns800. The circuit interconnection patterns800may be disposed on the photosensitive material layer600acting as an encapsulation layer and may be electrically connected to the first and second elevated pillar bumps390and392and the third and fourth chip pads430and431. The dielectric layer910may be disposed on the circuit interconnection patterns800to leave portions of the circuit interconnection patterns800revealed, and the outer connectors900may be attached and connected to the revealed portions of the circuit interconnection patterns800.

FIG. 11is a block diagram illustrating an electronic system including a memory card7800employing the semiconductor package according to an embodiment. The memory card7800includes a memory7810such as a nonvolatile memory device, and a memory controller7820. The memory7810and the memory controller7820may store data or read out the stored data. At least one of the memory7810and the memory controller7820may include the semiconductor package according to an embodiment.

The memory7810may include a nonvolatile memory device to which the technology of the embodiment of the present disclosure is applied. The memory controller7820may control the memory7810such that stored data is read out or data is stored in response to a read/write request from a host7830.

FIG. 12is a block diagram illustrating an electronic system8710including the semiconductor packages according to an embodiment. The electronic system8710may include a controller8711, an input/output device8712, and a memory8713. The controller8711, the input/output device8712, and the memory8713may be coupled with one another through a bus8715providing a path through which data move.

In an embodiment, the controller8711may include one or more microprocessor, digital signal processor, microcontroller, and/or logic device capable of performing the same functions as these components. The controller8711or the memory8713may include one or more of the semiconductor packages according to an embodiment of the present disclosure. The input/output device8712may include at least one selected among a keypad, a keyboard, a display device, a touchscreen and so forth. The memory8713is a device for storing data. The memory8713may store data and/or commands to be executed by the controller8711, and the like.

The memory8713may include a volatile memory device such as a DRAM and/or a nonvolatile memory device such as a flash memory. For example, a flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system8710may stably store a large amount of data in a flash memory system.

The electronic system8710may further include an interface8714configured to transmit and receive data to and from a communication network. The interface8714may be a wired or wireless type. For example, the interface8714may include an antenna or a wired or wireless transceiver.

The electronic system8710may be realized as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

If the electronic system8710is an equipment capable of performing wireless communication, the electronic system8710may be used in a communication system using a technique of CDMA (code division multiple access), GSM (global system for mobile communications), NADC (north American digital cellular), E-TDMA (enhanced-time division multiple access), WCDAM (wideband code division multiple access), CDMA2000, LTE (long term evolution), or Wibro (wireless broadband Internet).