Direct bandgap semiconductor bonded to silicon photonics

According to an example of the present disclosure a direct bandgap (DBG) semiconductor structure is bonded to an assembly comprising a silicon photonics (SiP) wafer and a complementary metal-oxide-semiconductor (CMOS) wafer. The SiP wafer includes photonics circuitry and the CMOS wafer includes electronic circuitry. The direct bandgap (DBG) semiconductor structure is optically coupled to the photonics circuitry.

BACKGROUND

Photonics is the field of technology relating to the generation, transmission, reception and manipulation of light. Photonic devices include for example waveguides, splitters, combiners, wavelength-division multiplexing (WDM) structures, mirrors, gratings, lasers, photodetectors, optical amplifiers, optical modulators, optical filters, optical resonators etc. Silicon photonics (SiP) relates to photonic devices which are based on silicon and has the potential to provide high quality, low cost photonic devices built using silicon chip technologies.

DETAILED DESCRIPTION

For simplicity and illustrative purposes, the present disclosure is described by referring mainly to examples thereof. As used herein, the terms “includes” means includes but not limited to, the term “including” means including but not limited to. The term “comprises” means includes but not limited to, the term “comprising” means including but not limited to. The term “based on” means based at least in part on. The term “number” means any natural number equal to or greater than one. The terms “a” and “an” are intended to denote at least one of a particular element. The term “connected to” means “connected directly or indirectly to”, the term “connects to” means “connects directly or indirectly to”. Several examples and diagrams refer to layers of an assembly and their relative positions. Positioned over means positioned above and includes directly above and above with one or more layers in between. Positioned under means positioned below and includes directly below and below with one or more layers in between. It is to be understood that each layer may itself comprise one or more sub-layers.

Complementary metal oxide semiconductor (CMOS) fabrication is a well-established technology for manufacturing silicon based electronic integrated circuits. Due to many years of research such electronic ICs can now be manufactured at a large scale, at low unit cost with high reliability and with very small transistor sizes.

Silicon photonic (SiP) devices may be manufactured by processing a silicon substrate to sub-micro meter precision. Complementary metal oxide semiconductor (CMOS) fabrication lines may be used to form the SiP devices thereby leveraging existing production lines and many years of experience with CMOS fabrication techniques. However, the manufacturing environment for CMOS fabrication is very tightly specified and controlled and many substances are forbidden on a CMOS production line.

Silicon, Germanium and other CMOS compatible semiconductors have an indirect bandgap. An indirect band gap semiconductor is a semiconductor in which the maximum energy of the valence band occurs at a different value of momentum to the minimum energy of the conduction band. As such indirect bandgap semiconductors are suitable for constructing waveguides, gratings and mirrors, but are not optimum for the construction of light emitting and light detecting devices. Certain photonic devices, especially lasers, but also photodetectors and others, are best implemented using direct bandgap semiconductors. A direct bandgap (DBG) semiconductor is a semiconductor in which the maximum energy of the valence band and the minimum energy of the conduction band occur at the same value of momentum. Direct bandgap semiconductors include, but are not limited to, Group III-V semiconductors and Group II-VI semiconductors. A Group III-V semiconductor is a semiconductor including at least one element from Group III or Group V of the Periodic Table. A Group II-VI semiconductor is a semiconductor including at least one element from Group II or Group VI of the Periodic Table. Many direct bandgap semiconductors are compound semiconductors, which are semiconductors composed of two or more elements.

In general, direct bandgap semiconductor materials, such as Group III-V materials, are not allowed on a CMOS production line. Furthermore, certain materials such as gold, which are often used as electrical contacts for direct bandgap semiconductor devices, are not allowed on a CMOS production line.

Accordingly, one example of the present application proposes a method including receiving an assembly comprising a SiP wafer which has been bonded to a CMOS wafer. The SiP wafer is a wafer which includes photonic circuitry, wherein at least some of the photonic circuitry includes silicon. The CMOS wafer is a wafer which includes electronic circuitry, at least some of the circuitry including a metal-oxide-semiconductor structure. The electronic circuitry may include silicon. The method comprises bonding a direct bandgap (DBG) semiconductor structure to the SiP wafer. Because the DBG semiconductor structure is bonded to the SiP wafer after the SiP wafer has been bonded to the CMOS wafer, the bonding of the DBG semiconductor structure to the SiP wafer may be carried out on a different production line, or at the back end of the production line, so as not to contaminate the CMOS manufacturing facilities.

The DBG semiconductor structure may be optically coupled to the photonic circuitry in the SiP wafer and electrically connected to the electronic circuitry in the CMOS wafer. In one example, the DBG semiconductor structure is controlled by the electronic circuitry and generates light that is to be directed to the photonics circuitry. In another example the DBG semiconductor structure detects an optical signal received from the photonic circuitry and sends an electrical signal based on the optical signal to the electronic circuitry for processing.

FIG. 1is a flow diagram showing a method10according to one example of the present disclosure.

At block110of method10, an assembly100including a SiP wafer300which has already been bonded to a CMOS wafer200is received. The assembly100may for example be received by a production line, or section of a production line, which is to carry out processes such as those described in any of blocks120-140described below.

The SiP wafer300and CMOS wafer200may have been bonded together to form the assembly at an earlier stage of the manufacturing process, prior to block110, as is described in more detail later. An example of the assembly100comprising the CMOS wafer200bonded to the SiP wafer300is shown inFIG. 2.

The CMOS wafer200comprises electronic circuitry201. The electronic circuitry201includes at least one logic device, such as a transistor, logic gate, processor etc. The electronic circuitry may also include electronically conductive lines to connect logic devices of the electronic circuitry together and/or to connect the electronic circuitry with devices external to the CMOS wafer, as will be described in more detail later. The electrical circuitry may further comprise resistors, capacitors, inductors, high speed analogue circuitry etc. The electronic circuitry201may have been fabricated on the CMOS wafer in a previous process on another production line, or at an earlier stage of the same production line.

The SiP wafer300comprises photonics circuitry301. The photonics circuitry301may include one or more photonic devices, such as but not limited to an waveguides, optical splitters, optical combiners, wavelength-division multiplexing (WDM) structures, mirrors, gratings, lasers, photodetectors, optical amplifiers, optical modulators, optical filters, optical resonators. In some examples the photonics circuitry includes a plurality of photonic devices at least some of which are to perform different optical functions to each other. The photonic circuitry301may have been fabricated on the SiP wafer in a previous process on another production line, or at an earlier stage of the same production line.

At block120of method10, a direct bandgap (DBG) semiconductor structure is bonded to the SiP wafer. Any suitable bonding method may be used including, but no limited to, molecule bonding, metal bonding, polymer bonding etc. Molecule bonding is a method in which a surface of the DBG semiconductor structure is bonded directly to a surface of the SiP wafer. Molecule bonding may include exposing the surfaces to some surface activation process, e.g. a plasma, to facilitate the bonding, prior to placing the surfaces in contact with each other. Molecule bonding may result in good optical properties such that coupling of light between the DBG semiconductor structure and the SiP wafer is not disrupted.

The DBG semiconductor structure includes a direct bandgap semiconductor material. In one example the DBG semiconductor material is a group III-V semiconductor material. In one example the DBG semiconductor material is a group II-VI semiconductor material. In one example the DBG semiconductor material is a compound semiconductor. The DBG semiconductor structure may include a number of layers and may include a plurality of different semiconductor materials. In one example the DBG semiconductor structure includes at least one material selected from the group comprising: indium phosphide (InP), gallium arsenide (GaAs), Indium gallium arsenide (InGaAs), indium arsenide (InAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide phosphide (lnGaAsP), indium gallium aluminum arsenide (InGaAlAs), indium gallium arsenide nitride (lnGaAsN), indium gallium phosphide (InGaP), indium aluminum arsenide (InAlAs), indium antimonide (InSb), aluminum antimonide (AlSb), aluminum arsenide antimonide (AlAsSb), indium gallium antimonide (InGaSb) and indium gallium aluminum antimonide (InGaAlS).

In one example, the DBG semiconductor structure comprises a photonics device. In another example the DBG semiconductor structure comprises an unprocessed or partially processed die which may be further processed, after bonding to the SiP wafer, to form a photonics device. The photonics device may be a light emitting or light detecting device such as a laser, photodetector, optical modulator or optical amplifier etc.

In some examples there may be additional processes between receiving the assembly100in block110and bonding the DBG semiconductor structure400to the assembly100in block120. For example, a substrate of the SiP wafer300of the assembly100may be removed before bonding the DBG semiconductor structure400to the SiP wafer. This and examples of other processes are described in more detail later.

At block130of method10, the DBG semiconductor structure is optically coupled to the photonics circuitry in the SiP wafer. In this context, “optically coupling” the DBG semiconductor structure to the photonics circuitry in the SiP wafer means forming an optical structure by which an optical signal may be coupled in at least one direction between the DBG semiconductor structure and the photonics circuitry. This may make it possible for an optical signal generated by the DBG semiconductor structure to be transferred to the photonics circuitry and/or for an optical signal in the photonics circuitry to be transferred to the DBG semiconductor structure for detection.

The optical coupling of block130may form part of the bonding process of block120or may be a contemporaneous process or a subsequent process. For instance, the bonding process of block120may include aligning pre-existing optical structures of the SiP wafer with pre-existing optical structures of the DBG semiconductor structure to create an optical coupling between them. In other examples, at least one of the DBG semiconductor structure and the SiP wafer may be further processed after the bonding of block120to form optical structures which create the optical coupling. The optical coupling of the DBG semiconductor structure to the photonics circuitry may comprise forming an optical path including at least one of an evanescent coupling structure, a grating, a mirror and an angled facet. Examples are described in more detail later.

At block140of method10, the DBG semiconductor structure is electrically connected to the electronic circuitry201in the CMOS wafer200. This may allow the electronic circuitry201to at least one of: control operation of the DBG semiconductor structure and receive electrical signals from the DBG semiconductor structure. In one example, electrically connecting the DBG semiconductor structure to the electronic circuitry of the CMOS wafer may include connecting an electrical contact of the DBG semiconductor structure with a via that extends at least partially through the SiP wafer.

FIG. 3shows an example of a hybrid photonics-electronics assembly500formed by the method10ofFIG. 1. In the context of this disclosure, the term “hybrid” means that the assembly includes both a DBG semiconductor structure and silicon photonics. The assembly500comprises a SiP wafer300including photonics circuitry301, which is bonded to a CMOS wafer200including electronic circuitry201. A DBG semiconductor structure400is bonded to surface of the SiP wafer300. The SiP wafer300is positioned between the DBG semiconductor structure400and the CMOS wafer200. More specifically the SiP wafer300underlies the DBG semiconductor structure and overlies the CMOS wafer200. This allows for convenient optical coupling between the DBG semiconductor structure400and the photonic circuit301in the SiP wafer300. Furthermore, the DBG semiconductor structure400and the electronic circuitry201of the CMOS wafer200may generate significant heat, so positioning them at the top and bottom of the assembly may facilitate dissipation of heat to the surrounding environment or to a heat sink mounted to the top or bottom of the assembly. In this respect positioning the DBG semiconductor at the top of the assembly may be especially convenient, as it allows the heat generating DB G to be in closer contact with a heat sink, therefore allowing efficient heat extraction.

The DBG semiconductor structure400is electrically connected to the electronic circuitry201of the CMOS wafer by an electrically conductive line202and optically coupled to the photonic circuitry201of the SiP wafer as indicated by arrow302. It should be noted that the optical coupling may be in one direction or both directions.

It will be appreciated that the method10ofFIG. 1comprises receiving an assembly100including a CMOS wafer and a SiP wafer which have already been bonded together.FIG. 4Ais a flow diagram showing a previous stage5of the manufacturing process prior toFIG. 1. Thus at block102ofFIG. 4Aa SiP wafer is bonded to a CMOS wafer. This is shown schematically inFIG. 4Bwhere a SiP wafer300including photonic circuitry301is bonded to a CMOS wafer200including electronic circuitry201. The bonding at block102may be molecule bonding, metal bonding or polymer bonding etc. The bonding may form a strong mechanical connection between the CMOS wafer200and SiP wafer300such that they are fixed in place relative to each other. In some examples, the bonding may form an electrical connection203between the photonics circuitry301and the electronic circuitry201as shown inFIG. 4C. For example, respective surfaces of the CMOS wafer and the SiP wafer which are to be bonded together may include electrically conductive contacts which are aligned with each other when the CMOS wafer is bonded to the SiP wafer. This may allow the electronic circuitry to control the photonic circuitry and/or to send/receive electrically transmitted data or other signals to/from the photonic circuitry. In one example the bonding of the SiP wafer to the CMOS wafer is flip chip bonding. Flip chip bonding is a technique in which one wafer is flipped over so that its tops surface faces downwards and is bonded to the top surface of another wafer, as shown inFIG. 4B.

FIG. 5Ais a schematic diagram showing another example of a hybrid photonics-electronics assembly510formed by the method10ofFIG. 1. It is the same as the example ofFIG. 3, except that it shows an electrical connection203between the CMOS electronic circuitry201and the SiP photonic circuitry301, as well as an electrical connection202between the CMOS electronic circuitry201and the DB G semiconductor structure400. ThusFIG. 3shows an arrangement in which the CMOS electronic circuitry201is not connected to the SiP photonic circuitry. This may be useful where the SiP photonic circuitry comprises passive photonic devices such as waveguides.FIG. 5Ashows an arrangement in which there is an electrical connection203between the CMOS electronic circuitry201and the SiP photonic circuitry301and may be useful where the photonic circuitry201includes an active photonic device or a plurality of active photonic devices.

FIG. 5Bis a schematic diagram showing a further example of a hybrid photonics-electronics assembly520formed by the method10ofFIG. 1. It is the same as the example ofFIG. 5A, but shows the photonic circuitry301in more detail. The photonic circuitry301comprises a plurality of photonic devices at least some of which perform different photonic functions to each other. The plurality of photonic devices includes a first photonic device301A and a second photonic device301B. In this example, the first photonic device301A is optically coupled to the DBG semiconductor structure, but is not electrically connected to the electronic circuitry201of the CMOS wafer. The second photonic device301B is electrically connected to the electronic control circuitry, but is not optically coupled to the DBG semiconductor structure. For example, the DBG semiconductor structure400may be a light generating device such as a laser, the first photonic device301A may be a passive photonic device such as a waveguide which is to receive light generated by the DBG semiconductor structure, and the second photonic device301B may be an active photonic device, such as an optical modulator, which is optically coupled to the first photonic device.

In general, a passive photonics device is a device which performs an optical function without using electrical power, while an active photonics device is a device which uses electrical power to interact with the light in the desired fashion. The photonics circuitry may comprise a plurality of active and passive photonic devices and the active photonic devices may be electrically connected to the CMOS electronic circuitry201.

It will be appreciated that some implementations of the present disclosure may include complicated photonics circuitry including many photonic devices which operate under control of sophisticated CMOS electronic circuitry. Furthermore, the photonics circuitry may make use of an active DBG photonics device which is optically coupled to the photonics circuitry and may be controlled by the CMOS electronic circuitry. Possible applications include, but are not limited to, an optical transmitter or optical receiver and dense wavelength division multiplexing (DWDM). Furthermore, the CMOS electronic circuitry may include logic circuitry to perform complicated signal encoding and decoding operations. According to some implementations of the present disclosure, such a device may be provided on a single hybrid photonics-electronic integrated chip and may be manufactured at scale by using semiconductor fabrication techniques.

FIG. 5Cis a schematic diagram showing another example of a hybrid photonics-electronics assembly530formed by the method10ofFIG. 1. It is the same as the example ofFIG. 3, except that it shows an example of the DBG semiconductor structure400in more detail.

The DBG semiconductor structure400shown inFIG. 5Cincludes an active layer420positioned between a first cladding layer410and a second cladding layer430. For example, the first cladding layer410may be bonded to an upper surface of the SiP wafer300, the active layer420may be positioned over the first cladding layer410and the second cladding layer430may be positioned over the active layer420. While depicted as single layers for clarity inFIG. 5C, it is to be understood that each of the first cladding layer410, active layer420and second cladding layer430may include one or more layers.

The active layer420may be a layer which is to generate or amplify light in response to application of an electric potential, or to generate an electrical current in response receiving photons. The active layer may, for example, be a gain region of a laser, amplifier or modulator. In one example, the active layer420is a quantum well layer and may include one or more quantum wells or quantum dots. The cladding layers410and430may at least partially optically confine photons within the active layer420. The cladding layers may be positively or negatively doped. In one example the cladding layers and active layer together form a p-i-n structure. At least the active layer420is formed of a DBG semiconductor material. The cladding layers410,430may also comprise a DBG semiconductor material of the same, or a different, type. The DBG semiconductor structure400may, for example, be a blank epitaxial die which is to be processed to form a DBG photonic device, or may be a partially or fully processed die. In some examples, the DBG semiconductor structure400may include the active layer420and the cladding layer430which is above the active layer, but not the cladding layer410which is below the active layer. In such examples the active layer420may be bonded directly to the upper surface of the SiP wafer300. In that case one of the dielectric layers in the SiP wafer, e.g. layer330or310, may act as the lower cladding layer.

FIG. 6Ais a schematic diagram showing an example structure of a CMOS-SiP wafer assembly100, such as the assembly manufactured inFIG. 4A, in more detail. The CMOS wafer200includes a substrate210and an electronic circuitry layer201positioned over the substrate. The SiP wafer300comprises a photonics layer320which includes the photonics circuitry301and an electrical interconnect layer310which is positioned under the photonics layer320. One side of the electrical interconnect layer310may be adjacent the photonics layer320and the other side may be bonded to the CMOS wafer200. The electrical interconnect layer310includes at least one electrically conductive line203which is embedded in electrically insulating material204. The electrically conductive line203may connect the photonic circuitry301with the electronic circuitry201of the CMOS wafer200. Another electrically conductive line202is shown inFIG. 6Bwhich includes a via extending from the interconnect layer310through the photonics layer320to an upper surface305of the photonics wafer300. The via may later form part of an electrical path linking the electronic circuitry201to the DB G semiconductor structure400(not shown inFIG. 6A) which is later to be bonded to the upper surface305of the SiP wafer.

In another example, the electrically conductive line202may connect the electronic circuitry201of the CMOS wafer200to an electrical contact which is to receive power from an external power supply. In another example, the electrically conductive line202may connect the electronic circuitry201to an electrical contact for receiving electrical control signals from, or sending electrical controls signals to an external device.

FIG. 6Bis another schematic diagram of a CMOS-SiP assembly100, which is similar toFIG. 6A, but shows an example structure of the electronic circuitry201of the CMOS wafer200in more detail. Specifically, the electronic circuitry201may include a logic layer220comprising at least one logic circuit222,224and a CMOS interconnect layer230. The CMOS interconnect layer230may comprise at a number of electrically conductive lines203A,202A embedded in an electrically insulating material204A to electrically connect the logic circuits222,224with a corresponding electrically conductive line203,202of the SiP interconnect layer310. The logic circuits222,224may include a number of transistors or logic gates or a processor, for example. The electrically conductive line202may include a via which extends at least partially through the SiP wafer300. In the example ofFIG. 6B, the via extends all the way through the photonics layer320and part of the way through the SiP interconnect layer.

While two separate logic circuits222,224are shown inFIG. 6B, in other examples there may be just one logic circuit or a larger number of logic circuits. Likewise, there may be a large number of electrically conductive lines and any of the logic circuits may be connected to both electrically conductive lines202A and203A.

Any CMOS compatible materials may be used for the various layers of the CMOS wafer200and the SiP wafer300described above. In one example, the photonics layer320includes silicon as an optical medium. The silicon may have been processed using semiconductor fabrication techniques to form the photonics circuitry. The photonics circuitry may include other CMOS compatible materials. For example materials having a different refractive index to silicon, such as silicon dioxide. The photonics circuitry may include germanium, germanium oxides, germanium and silicon alloys etc for forming active or passive photonic devices and may include electrically conductive materials to form contacts for active photonics devices. The electrically insulating material204of the SiP interconnect layer310may have a lower refractive index than silicon in order to help prevent light from leaking out of the photonics layer320into the CMOS wafer. The electrically insulating material204A of the CMOS interconnect layer230may be, but does not have to be, the same as the electrically insulating material204of layer310so as to keep the refractive indexes and thermal expansivity of the layers the same. In one example the electrically insulating material is a dielectric such as silicon dioxide. The electrically conductive lines203,203A,202and202A may comprise any appropriate material, including but not limited to copper, aluminum, indium tin oxide etc.

FIG. 7is a flow chart showing an example method700of manufacturing a CMOS wafer-SiP wafer assembly100. The following description of the flow chart may be read in conjunction withFIGS. 8A-8Fwhich are cross sectional views of the assembly100at various stages of the manufacturing process.

At block710a CMOS wafer is processed to form electronic circuitry. The processing may include processing a silicon substrate210to form electronic circuitry201. The processing may include material deposition, etching, patterning and doping etc in order to form and connect the various electronic components.FIG. 8Ashows an example of the CMOS wafer200including a substrate210and an electronic circuitry layer201. The electronic circuitry layer may include a plurality of electrically conductive lines203A and at least one electronic logic circuit222, both of which are embedded in an electrically insulating material205. The electrically conductive lines203A may connect the at least one electronic logic circuit222to another electronic logic circuit in the CMOS wafer and/or to electrically conductive contacts on an upper surface of the CMOS wafer.

At block720a SiP wafer is processed to form photonics circuitry. An example of the SiP wafer300is shown inFIG. 8A. The SiP wafer may start as a silicon on insulator (SOI) wafer including a silicon layer320over a dielectric layer330, such as silicon dioxide, over a silicon substrate340. The dielectric layer330is electrically insulating and may have a lower refractive index than the silicon layer320so as to help confine light in the silicon layer320. Photonics circuitry may be formed in the silicon layer320, which after the formation of photonics circuitry may be referred to as the “photonics layer”. Creating the photonics circuitry may include semiconductor fabrication techniques such as material deposition, etching, patterning and doping etc. The SiP wafer further includes an electrical interconnect layer310positioned over the photonics layer320. The electrical interconnect layer310may include an electrically insulating material204such as silicon dioxide and a plurality of electrically conductive lines203embedded in the electrically insulating material. The electrically conductive lines203may extend to contacts on an upper surface of the SiP wafer and at least some of the lines203may connect to electrical contacts of active photonic devices in the photonic circuitry in layer320.

Blocks710and720may be carried out at CMOS production site. While they may be carried out on the same production line, usually the CMOS wafer processing and SiP wafer processing will be carried out on separate production lines, as photonic devices are much larger than the transistors in modern integrated circuits and so older and cheaper equipment may be used to form the photonic circuitry.

At block730the SiP wafer is bonded to the CMOS wafer. This may involve any of the methods described above in relation toFIGS. 4A-4CandFIGS. 6A-6B.

FIG. 8Bis similar toFIG. 4Cand shows the CMOS wafer200and SiP wafer300ofFIG. 8Aafter they have been bonded together to form an assembly100.

At block740the substrate340of the SiP wafer is removed. For example the substrate340may be chemically etched away. This may leave the oxide layer330as an exposed upper layer of the SiP wafer, as shown inFIG. 8C.

At block750the dielectric layer330is thinned or removed, for example by chemical etching. In other examples, the dielectric layer330may be maintained at the same thickness or even thickened. Further, in some examples the substrate340is not removed.

If the substrate340is removed and the dielectric layer330is thinned or removed, this may later facilitate optical coupling between the photonics circuitry of the photonics layer320and DBG semiconductor structure400which is added later. Another reason for removing the substrate340and removing or thinning the dielectric layer330, may be to reduce the distance between the electronic circuitry201and the upper surface of the SiP wafer. This may lead to a shorter electrically conductive line and quicker transmission of electrical signals between the electronic circuitry201and the DBG semiconductor structure400.

At block760vias208are formed in the SiP wafer300. The vias208extend at least partially through the SiP wafer. For example the vias208may extend through the photonics layer320, through the dielectric layer330(if it has not been removed) and through the substrate340(if it has not been removed) to the upper surface of the SiP wafer. The vias208may extend all the way through the electrical interconnect layer310, or connect with electrically conductive lines in the interconnect layer310, to form an electrically conductive line linking the upper surface of the SiP wafer with the electronic circuitry201of the CMOS wafer.

FIG. 8Dshows an example of the assembly after the vias208have been formed.FIG. 8Eshows another example, which is the same asFIG. 8D, but in which the dielectric layer330has been thinned and has a reduced thickness compared to the dielectric layer330inFIGS. 8A-8D.FIG. 8Fshows yet another example, which is the same asFIG. 8D, but in which the dielectric layer330has been removed.

FIG. 9is a flow diagram showing an example method800of manufacturing a hybrid photonics-electronic assembly in detail.FIG. 9may be read together withFIGS. 10A to 10Dwhich show cross-sectional views of the hybrid assembly at various stages of the manufacturing process.

At block810an assembly100is received. The assembly includes a SiP wafer300bonded to a CMOS wafer200. This is the same as block110of method10ofFIG. 1.

At block820a DBG semiconductor structure400is bonded to the received assembly. This is the same as block120ofFIG. 1and may employ any of the methods described above in relation toFIGS. 1, 3 and 5A to 5C.

The assembly100which is received at block810may, for example, be similar to that shown in any ofFIGS. 8D to 8F. In other examples, the received assembly100may be similar to that shown inFIG. 8C, in which case the vias208may be formed after the bonding of the DBG semiconductor structure400to the SiP wafer300. In other examples, the received assembly100may be similar to that shown inFIG. 8B, in which case the substrate300may be maintained or thinned prior to the bonding of the DBG semiconductor structure400to the SiP wafer300.

FIG. 10Ashows an example of the hybrid assembly after the DBG semiconductor structure400has been bonded to the SiP wafer300. The DBG semiconductor structure400is similar to that shown inFIG. 5Cand includes an active layer420between two cladding layers410,430. These layers may be as described in relation toFIG. 5Cand may comprise similar materials as described in relation toFIG. 5C. The DBG semiconductor structure400further includes a substrate layer440over the upper cladding layer430. The substrate layer430may, for example, comprise an undoped DBG semiconductor material. The substrate layer may have been used as a handling layer to hold the DBG semiconductor structure during in bonding process of block820.

At block830the substrate layer440of the DBG semiconductor assembly may be removed. The resulting structure after removal of the substrate layer440is shown inFIG. 10B.

At block840the DBG semiconductor structure400may be etched. The etching may be to form an optical structure to confine light in an active region of the DBG semiconductor structure. An example of the structure after etching is shown inFIG. 10C. It can be seen that, in this example, the upper cladding layer430and the active layer420are narrower than the lower cladding layer410. This may help to confine light within an optical mode of the active layer420as the refractive index of the active layer420may be higher than the surrounding air, or higher than a surrounding layer which is deposited later.

At block850a passivation layer450is deposited over the DBG semiconductor structure400. The passivation layer450may for example be a dielectric or polymer material and may electrically isolate and mechanically protect the DBG semiconductor structure. Further, as mentioned above, the passivation layer may have a lower refractive index than the active layer420and the cladding layers410,430so as to confine light within the DBG semiconductor structure. An example of the assembly after depositing the passivation layer is shown inFIG. 10D.

At block860an electrically conductive material is deposited to electrically connect the DBG semiconductor assembly400to the electronic circuitry201in CMOS wafer. This may, for example, include forming electrical contacts of the DBG semiconductor structure and connecting these electrical contacts to the vias208. Block860may include a plurality of etching and deposition processes to achieve the desired electrical connections.FIG. 10Eshows an example of an assembly540in which electrical connections461,462are formed to connect upper and lower layers of the DBG semiconductor assembly to vias208. Thus, by applying an electric potential between the connections461,462the electronic circuitry201may apply a potential difference across the active layer420of the DBG semiconductor structure.

In some implementations, there may be one or more further vias, similar to the vias208shown inFIG. 10E. These further vias may be extended through the passivation layer450as well as the at least part of the SiP wafer300in order to connect the electronic circuitry201with one or more external electrical contacts (not shown) on an outside surface of the assembly540. These electrical external electrical contacts and further vias may be used to route electrical power from an external power supply to the electronic circuitry201, to route electric control signals from an external device to control the electronic circuitry201, or to send electrical signals from the electronic circuitry201to an external device.

In the example shown inFIGS. 10A to 10E, a blank epitaxial die400for forming a DBG laser was bonded to the SiP wafer inFIG. 10Band subsequently processed to form a DBG laser as shown inFIG. 10E. In other examples a partially or fully pre-processed DBG laser may be bonded to the SiP wafer. In that case, depending on the extent of pre-processing, some or all of blocks830to850need not take place. In the case of a fully pre-processed DBG laser, electrical connection of the laser to the vias208may still be performed, although the electrical contact pads of the DBG laser may already been in place.

While a single die of the CMOS and SiP wafers has been shown in the figures above, it is to be understood that the CMOS wafer may include a plurality of electronic integrated chips and the SiP wafer may include a plurality of integrated photonic chips. The process blocks ofFIG. 7may be carried out at the wafer level, where each wafer includes a plurality of integrated chips. The process blocks ofFIG. 9may be carried out at the wafer level or the chip level. In one example, at least blocks810and820are carried out at the wafer level for enhanced process efficiency. Blocks830to850may be carried out at either the wafer level or the chip level.

FIGS. 11A to 11Dshow cross sectional examples of stages in the manufacturing process when carried out at the wafer level.

Thus,FIG. 11Ashows bonding of a DBG wafer401including a plurality of DBG semiconductor structures400A,400B,400C on a common substrate440to a CMOS-SiP wafer assembly100. The assembly100comprises a SiP wafer300bonded to a CMOS wafer200. The SiP wafer includes a plurality of photonic integrated circuits300A,300B,300C, while the CMOS wafer200includes a plurality of electronic integrated circuits200A,200B,200C. The SiP wafer300is bonded to the CMOS wafer200and they may share the same substrate210. Each respective electronic integrated circuit200A,200B,200C in the CMOS wafer200may be electrically connected to a respective photonic integrated circuit300A,300B,300C in the SiP wafer300.

FIG. 11Bshows the resulting hybrid photonics-electronic wafer assembly501after the DBG wafer401has been bonded to the CMOS-SiP wafer assembly100. While the electronic integrated circuits200A,200B,200C and photonic integrated circuits300A,300B,300C were shown schematically inFIG. 11A, they are shown in a greater level of detail inFIG. 11B, similar to that ofFIGS. 10A to 10E. Each electronic integrated circuit and photonic integrated circuit may have any of the features discussed above in relation the CMOS wafer and SiP wafer, for instance but not limited to the features described with reference toFIGS. 4C to 6B, 8A to 8F and 10A to 10E.

The DBG semiconductor structures400A,400B,400C may be photonic devices or dies which may be processed to form photonic devices. They may have any of the features of the DBG semiconductor structures described above, for example with reference to but not limited to that described in relation toFIG. 5CandFIGS. 10A to 10E. As a result of the bonding inFIG. 11A, or as a result of further processing carried out after the bonding ofFIG. 11A, each respective DBG semiconductor structure400A,400B,400C of the DBG semiconductor wafer401is optically coupled to a respective photonic integrated circuit300A,300B,300C of the SiP wafer300.

FIG. 11Cshows the hybrid photonics-electronic wafer assembly501after each DBG photonic device400A,400B,400C has been electrically connected to a respective electronic integrated circuit200A,200B,200C.

In the example ofFIGS. 11A to 11Deach process is carried out at the wafer level. However, in other examples, the order of the electrical connection and the cutting into separate chips may be reversed. Thus, in other examples, the hybrid photonics-electronic wafer assembly may be cut into separate hybrid photonics integrated chips before individually connecting each DBG photonic device to a corresponding electronic integrated circuit.

12A is a schematic cross sectional view of a hybrid photonics-electronics integrated chip formed by the above methods.

The hybrid photonics-electronics integrated chip includes a complementary metal-oxide-semiconductor (CMOS) layer200, a silicon photonics (SiP) layer300bonded to the CMOS layer200and a direct bandgap (DBG) semiconductor layer405bonded to the SiP layer300. The CMOS layer200includes electronic circuitry201. The SiP layer includes photonics circuitry301.

The DBG semiconductor layer405includes a DBG semiconductor photonics device400which is optically coupled302to the photonics circuitry301of the SiP layer300.

An electrically conductive line202connects the electronic circuitry201of the CMOS layer to an electrical contact460of the DBG semiconductor photonics device400. In this way the electronic circuitry may control the DBG semiconductor photonics device and/or receive a signal from the DBG semiconductor device. For instance, in one example the electronic circuitry is electronic control circuitry to control a light emitting DBG semiconductor device. In another example the electronic circuitry is electronic circuitry to receive and process a signal from a light detecting photonic device such as a photodetector.

The electrically conductive line202, which connects the electronic control circuitry201with the electrical contact460of the DBG semiconductor photonics device400, may include an electrically conductive via which extends at least partially through the SiP layer300.

FIG. 12Bis a schematic cross sectional view of another example hybrid photonics-electronics integrated chip, which is similar to the chip ofFIG. 12Aexcept that it does not include an electrically conductive line202to connect the electronic control circuitry201with the DBG semiconductor photonics device400. Instead, there is an electrically conductive line203which connects the electronic control circuitry201of the CMOS layer to the photonics circuitry301in the SiP layer300. In this way the electronic control circuitry201may control and/or receive data or other signals from the photonics circuitry301.

FIG. 12Cis a schematic cross sectional view of another example hybrid photonics-electronics integrated chip, which is similar to the chip ofFIG. 12A, but includes both an electrically conductive line202which connects the electronic control circuitry201with the DBG semiconductor photonics device400and an electrically conductive line203which connects the electronic control circuitry201with the photonics circuitry301.

In the above examples, the SiP layer300may comprise a photonics layer and an electrically insulating oxide layer. The photonics layer includes the photonics circuitry, while the electrically insulating oxide layer is positioned under the photonics layer and above the CMOS layer. A plurality of electrically conductive lines may be embedded in the electrically insulating oxide layer and may connect the electronic control circuitry of the CMOS layer to at least one of the photonics circuitry301and the DBG semiconductor photonics device400.

In examples of the present disclosure, the optical coupling302may be by virtue of an optical structure which couples light in one direction, or both directions, between the DBG semiconductor photonics device400and the photonics circuitry301. The optical coupling structure may couple light vertically between the DBG semiconductor photonics device and the photonics circuitry in the SiP layer. In this context “couple light vertically” means couple the light into a layer above or into a layer below and includes coupling at various angles to the horizontal. Vertical coupling is in contrast to butt coupling which is coupling light horizontally from one component to another in the same plane. The optical coupling structure of the present disclosure may include, but is not limited to any of the following structures: an evanescent coupling structure, a grating, a mirror and an angled facet of the DBG semiconductor device. Various examples will now be described with reference toFIGS. 13-16.

FIGS. 13 and 14show an example of evanescent coupling. Evanescent coupling is coupling due to the evanescent field generated by a light wave. For instance, evanescent coupling may occur between two waveguides which are close together, such that the evanescent field generated by a light wave in one waveguide overlaps with the other waveguide. Thus evanescent coupling may occur between two photonic devices which are next to each other, or separated by a thin layer of material having a low refractive index.

Evanescent coupling may, for example, occur when an optical mode of the DBG semiconductor structure overlaps an optical mode of a photonic device in the photonic circuitry. An optical mode is the spatial distribution of light in a direction perpendicular to its direction of propagation in an optical medium. Light in a photonic device adopts one or more optical modes which are characteristic of the photonic device. An example of evanescent coupling will now be explained further with reference toFIGS. 13 and 14.

FIG. 13is a cross sectional example of an assembly according to the present disclosure and is similar toFIG. 10D. Like reference numerals indicate like parts as inFIG. 10D. It is to be understood that conductive lines to connect the DBG photonics device400to vias280may be present, but are not shown in order to preserve the clarity of the diagram. The dashed line600indicates an optical mode of the DBG semiconductor photonics device400. As can be seen, the optical mode600centers on the active region420of the photonics device400. However, the optical mode overlaps with the photonic circuitry in photonics layer320. This part of the optical mode, which overlaps the dielectric layer330and the photonic layer320, is referred to as the evanescent field of the light.

FIG. 14is a close up of the upper part ofFIG. 13and shows how the optical mode600overlaps with a photonic device322in the photonics layer320. The photonics circuitry in layer320includes at least the photonic device322and may include other photonic devices as well. The photonic device322may, for example, be a waveguide. The evanescent field of the optical mode600overlaps with the photonic device322and excites an optical mode610in the photonic device322. The optical mode610is shown inFIG. 14by the ellipsoid610which is shaded with dots. This phenomena is known as evanescent coupling. In order for evanescent coupling to take place the DBG photonics device400and the photonic device322should be close enough that they have optical modes which overlap. Evanescent coupling is also affected by the refractive index and relative thickness of any material, such as dielectric layer330, which lies between the DBG photonics device400and the photonic device322. Evanescent coupling is more likely where any such intermediate layer330is relatively thin and has a relatively low refractive index compared to the refractive indexes of the cores of the photonic devices400,322. For this reason, in some examples, the dielectric layer330may be thinned or even removed, as mentioned in block750ofFIG. 7, as well as shown inFIGS. 8E and 8F.

In some examples the evanescent coupling structure may be formed as a result of bonding the DBG semiconductor structure400to the SiP wafer300. For example, if the DBG semiconductor structure400and a photonic component322of the photonic circuitry are close enough when the DBG then this may form an evanescent coupling structure. In other examples, the evanescent coupling structure may not exist immediately after bonding the DBG semiconductor structure400to the SiP wafer, but may be created by subsequent processes. For instance, in some examples, etching the DBG semiconductor structure400may create an optical mode which overlaps with the photonic circuitry, while in other examples an overlapping optical mode may exist even before etching.

Evanescent coupling is one type of optical path which may link the DBG semiconductor structure400with the photonic circuitry301. Other types of optical coupling structure include optical paths comprising a grating, mirror or angled facet etc. Examples are shown inFIGS. 15 and 16.

FIG. 15is a close up of the upper part of a hybrid photonic electronic integrated assembly according to the present disclosure, similar toFIG. 14. However, whileFIG. 14showed evanescent coupling, inFIG. 15the optical coupling is by a path including an angled facet412positioned at one end of the DBG photonic device400. The angled facet412directs light620from an optical mode600of the DBG photonic device, downward into the layers below by virtue of internal reflection. The light620is received by a grating324of the photonic circuitry in layer320and may be directed by the grating324to another photonic device322, such as a waveguide, in layer320.

FIG. 16is similar toFIG. 15, except that instead of a grating324, the light620is received by an angled facet326and directed into a waveguide322of the photonic layer320. In other examples the grating or angled facets described above may be replaced by mirrors.

While the above examples have been described in relation to transferring an optical signal from the DBG semiconductor structure to the photonic circuitry in the SiP wafer, it will be understood that similar techniques could be used to transfer light from the photonic circuitry to the DBG semiconductor structure.

Examples structures of DBG semiconductor lasers will now be described.FIG. 17is similar toFIG. 10Eand shows a cross section in the X-Y plane of an example device comprising a DBG semiconductor laser which is bonded to an assembly comprising a SiP layer300and CMOS layer200, as described in the earlier examples. Like numerals denote like parts as inFIG. 10E. The laser may for example be a horizontal cavity laser or a vertical cavity surface emitting laser (VCESL).

FIG. 18shows a cross section in the Y-Z plane of the device ofFIG. 17, in the case that the laser is a horizontal cavity laser. Like reference numerals denote like parts as inFIG. 17. For clarity, the detailed structure of the electrical interconnect layer310and the electronic circuitry layer201are not shown. The arrow630shows the general direction of light confined horizontally in the laser cavity along the Z direction. The light may be mostly confined to the active layer420and reflect back and forth between the ends of the laser so that lasing occurs. A portion of the laser light is coupled to the photonic circuitry in layer320as shown by the arrow640.

FIG. 19shows a cross section in the Y-Z plane of the device ofFIG. 17, in the case that the laser is a VCESL. Like reference numerals denote like parts as inFIG. 17. For clarity, the detailed structure of the electrical interconnect layer310and the electronic circuitry layer201are not shown. The arrow630shows the general direction of light confined vertically in the laser cavity along the Y direction. The light may reflect back and forth between the ends of the laser and be amplified in the active region420so that lasing occurs. A portion of the laser light is coupled to the photonic circuitry in layer320as shown by the arrow640.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the blocks of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or blocks are mutually exclusive. Furthermore, except where explicitly stated otherwise or where the context or logic demands otherwise, the processes described herein may be carried out in any order and are not limited to the specific order shown in the particular examples. Some the processes or method blocks described herein may be carried contemporaneously with each other.