A voltage-controlled oscillator (VCO) enabling proper gain adjustment with a simple configuration. The VCO includes a first current source for generating a first control current in accordance with the first control voltage and a second current source for generating a second control current in accordance with the second control voltage. A control voltage generation circuit synthesizes the first and second control currents to generate an oscillation control voltage in accordance with the synthesized current. A ring oscillator generates an oscillation signal with a frequency corresponding to the oscillation control voltage. The first current source varies a changing amount of the first control current relative to a change in the first control voltage. The second current source varies a changing amount of the second control current relative to a change in the second control voltage.

BACKGROUND OF THE INVENTION

The present invention relates to a voltage-controlled oscillator for variably controlling the frequency of an output pulse in accordance with an input voltage.

A phase locked loop (PLL) is known to be used to generate a clock signal that is synchronized with a reference pulse signal. The PLL includes a phase comparator for comparing the clock signal generated by the PLL with the reference pulse signal, a low pass filter for generating DC voltage in accordance with the comparison result of the phase comparator, and a voltage-controlled oscillator (VCO) for generating the clock signal from a control voltage, or the DC voltage from the low pass filter. In the VCO, a signal based on the difference between the frequency of the clock signal and the frequency of the reference signal is applied as the control voltage to the VCO to perform feedback control. The VCO varies the frequency of the clock signal in accordance with the control voltage. Thus, the VCO generates clock signals synchronized with various frequency signals.

The VCO, which varies its gain (the varied amount of the frequency (control current) relative to the varied amount of a predetermined control voltage) to generate the clock signal, is optimal, for example, when generating the reference clock signal with a data recording device in accordance with the rotation of the disc medium, the rotation of which is controlled. That is, when the data recording device performs 2× speed recording, the gain of the VCO is varied in accordance with the rotation velocity to generate the reference clock signal that properly corresponds to the rotation of the disc medium regardless of changes in the rotation velocity of the disc medium.

The gain control of the VCO may be performed by adding a certain control voltage to the predetermined control voltage. However, in such a case, when providing a control gain for each control voltage to the VCO gain, complicated control must be performed. Thus, the gain control is complicated when varying the VCO gain by adding two control voltages related to the rotation speed of the disc medium, in for example, a data recording device provided with a 2×speed recording function.

SUMMARY OF THE INVENTION

An aspect of the present invention is a voltage-controlled oscillator for generating an oscillation signal with a frequency corresponding to first and second control voltages. The voltage-controlled oscillator includes a first current source for generating a first control current in accordance with the first control voltage, with the first current source varying a changing amount of the first control current relative to a change in the first control voltage. A second current source generates a second control current in accordance with the second control voltage, with the second current source varying a changing amount of the second control current relative to a change in the second control voltage. A control voltage generation circuit is connected to the first and second current sources to synthesize a synthesized current from the first and second control currents and generate an oscillation control voltage in accordance with the synthesized current. A ring oscillator is connected to the control voltage generation circuit to generate the oscillation signal with a frequency corresponding to the oscillation control voltage.

A further aspect of the present invention is a voltage-controlled oscillator for generating an oscillation signal with a frequency corresponding to a plurality of control voltages. The voltage-controlled oscillator includes a plurality of current sources, each generating a control current in accordance with an associated one of the control voltages, each current source varying a changing amount of its respective control current relative to a change in the associated control voltage. A control voltage generation circuit is connected to the plurality of current sources to synthesize a synthesized current from the control currents and generate an oscillation control voltage in accordance with the synthesized current. A ring oscillator is connected to the control voltage generation circuit to generate the oscillation signal with a frequency corresponding to the oscillation control voltage.

A further aspect of the present invention is a method for controlling a voltage-controlled oscillator that generates an oscillation signal with a frequency corresponding to first and second control voltages. The method includes generating a first control current in accordance with the first control voltage by supplying the voltage-controlled oscillator with the first control voltage, varying a changing amount of the first control current relative to a change in the first control voltage, generating a second control current in accordance with the second control voltage by supplying the voltage-controlled oscillator with the second control voltage, varying a changing amount of the second control current relative to a change in the second control voltage, synthesizing a synthesized current from the first and second control currents to generate an oscillation control voltage in accordance with the synthesized current, and generating the oscillation signal with a frequency corresponding to the oscillation control voltage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a schematic block diagram of a voltage-controlled oscillator (VCO) according to a preferred embodiment of the present invention. The VCO110is used in a clock generator100of a data recording controller200. The data recording controller200will now be discussed.

FIG. 6is a schematic block diagram of the data recording controller200. The data recording controller200is employed as a DVD-R data recording controller.

An optical disc1, which is a disc medium, is the recording subject of the data recording controller200. The optical disc1is, for example, a data writeable (recordable) DVD-R disc. A pregroove, which functions as a guide groove of the optical disc1, extends spirally in the disc1. Land prepits (LPPs) are formed near the pregrooves.

The pregroove extends in a wobbled manner along the optical disc1. A signal including a wobble component has a frequency of 140.6 kHz. The LPPs are formed at predetermined intervals along the optical disc1. The interval is set so that a signal having one pulse per about sixteen pulses of the wobble signal may be obtained. An LPP signal is generated by reproducing the LPPs.

The data recording controller200includes an optical head10, an RF amplifier20, a decoder30, and a clock generator100. The optical head10emits a laser beam onto the optical disc1and receives the reflection of the laser beam from the optical disc1. The RF amplifier20generates a binary digital signal from the reflection received by the optical head10. The decoder30decodes the digital signal and generates the wobble signal and the LPP signal.

The clock generator100generates a clock signal, which is used by the data recording controller200, in accordance with the wobble signal and the LPP signal. More specifically, the clock generator100generates the clock signal with a frequency that is 5952 times greater than the frequency of the LPP signal. In other words, the clock signal has 5952 pulses between two LPP signal pulses. The clock signal has a frequency of 52.32 MHz.

After synchronizing the frequency of the clock signal with the frequency of the wobble signal, the clock generator100synchronizes the phase of the clock signal with the phase of the LPP signal. More specifically, after the difference between the frequencies of the wobble signal and the clock signal converges to within a predetermined range, the clock generator100phase-controls the clock signal in accordance with the LPP signal. This is because the generation of the clock signal in synchronization with the LPP signal is difficult since the frequency of the LPP signal is lower than the frequency of the wobble signal and the LPPs formed in the disc medium may be lost when data is recorded. In the preferred embodiment, the clock signal is roughly adjusted in accordance with the wobble signal. Then, the roughly adjusted clock signal is finely adjusted in accordance with the LPP signal to generate the clock signal with its phase synchronized to that of the LPP signal.

The clock generator100includes two phase-locked loops (PLLs), as shown in FIG.6. One of the two loops is a first loop A and the other is a second loop B. The first loop A synchronizes the frequency of a first divisional clock signal, which is generated by a first divider105, with the frequency of the wobble signal. The second loop B synchronizes the phase of a second divisional clock signal, which is generated by a second divider176, with the phase of the LPP signal. The first loop A and the second loop B share the same voltage-controlled oscillator (VCO)110. The VCO110has a first control voltage input terminal INa and a second control voltage input terminal INb. The first control voltage input terminal INa is supplied with a first control voltage corresponding to the difference between the frequency of the first divisional clock signal and the frequency of the wobble signal. The second control voltage input terminal INb is supplied with a second control voltage corresponding to the difference between the phase of the second divisional clock signal and the phase of the LPP signal.

The VCO110, which is shared by the first loop A and the second loop B, will now be discussed.FIG. 1is a schematic circuit diagram of the VCO110.

As shown inFIG. 1, the VCO110includes a first current source112, a second current source114, a gain control circuit115, a control voltage generation circuit116, and a ring oscillator118.

The first current source112adjusts the gain to drive the ring oscillator118with a control current (first control current) corresponding to the first control voltage Va input from the first control voltage input terminal INa. More specifically, the first current source112includes a plurality of first output current channels, each of which is configured by a p-channel transistor Tip, and a plurality of switches SWi, each of which are connected in series to an associated one of the output current channels. The series-connected p-channel transistors Tip and switches SWi are connected in parallel between the power supply VDD and the output of the first current source112. In accordance with the gain control circuit115, the switches SWi connect and disconnect the power supply VDD and the output. The gain control circuit115sets the number of stages of the first output current channels to be used, which are connected in parallel to each other.

Further, the first current source112includes an input current circuit configured by an n-channel transistor Tan and a p-channel transistor Tap, which are connected in series between the power supply VDD and the ground. The amount of current that flows through the p-channel transistor Tap and the voltage at the gate of the transistor Tap are determined in accordance with the level of the first control voltage Va, which is applied to the gate of the n-channel transistor Tan. Voltage that is equal to the gate voltage of the transistor Tap is applied to the gate of each p-channel transistor Tip, which is current mirror connected to the p-channel transistor Tap. This determines the amount of current flowing between the source and drain of each p-channel transistor Tip. Accordingly, the amount of current output from the first current source112is controlled in accordance with the level of the first control voltage.

The second current source114has the same configuration as that of the first current source112, as shown in FIG.1. That is, the second current source114includes a plurality of second output current channels (p-channel transistors Tkp), a plurality of switches SWk, and a second input current source (n-channel transistor Tbn and p-channel transistor Tbp). The second current source114adjusts the gain to drive the ring oscillator118with a control current (second control current) corresponding to the second control voltage Vb input from the second control voltage input terminal INb. This controls the amount of current output from the second current source114in accordance with the level of the second control voltage Vb.

The gain control circuit115controls the first current source112and the second current source114in accordance with the mode data stored in a register115a.That is, the gain control circuit115selectively opens and closes the switches SWi of the first current source112and the switches SWk of the second current source114to adjust the fluctuation rate of the output current (first and second control currents) of the first and second current sources112and114in accordance with fluctuations in the first and second control voltages.

The control voltage generation circuit116converts the first and second control currents supplied from the current sources112and114to voltage (oscillation control voltage). The control voltage generation circuit116includes two stages of current mirror circuits, which are configured by n-channel transistors T1nand T2nand p-channel transistors T3pand T4p.The gate bias voltage of an n-channel transistor T5n,which is series-connected to the p-channel transistor T4pof the second stage current mirror circuit, is supplied to the ring oscillator118.

The ring oscillator118includes an odd number of inverters IV connected between the power supply VDD and the ground. The amount of current supplied to each of the inverters IV is controlled in accordance with the first and second control voltages. More specifically, a p-channel transistor Tjp is connected between the power supply VDD and each inverter IV. Further, an n-channel transistor Tjn is connected between each inverter IV and the ground. The voltage corresponding to the first and second control currents of the first and second current sources112and114is applied to the transistors Tjp and Tjn, which control the amount of current flowing through the inverters IV, via the control voltage generation circuit116.

The characteristics of the VCO110will now be discussed.FIG. 2is a graph illustrating the relationship between the first control voltage Va applied to the first control voltage input terminal INa and the oscillation frequency of the VCO110. InFIG. 2, curve f1is obtained when the second control voltage applied to the control voltage input terminal INb is zero. As apparent fromFIG. 2, the oscillation frequency increases as the first control voltage Va increases.

Curves f2to f4are obtained when applying the voltage of the power supply VDD to the second control voltage input terminal INb. The number of stages in the second output current channel of the second current source114is one, two, and three for the curves f2, f3, and f4, respectively. As shown inFIG. 3, when the first control voltage is constant, the oscillation frequency increases as the number of stages of the second output current channels used in the second current source114increases.

When the first control voltage is constant and the second control voltage applied to the second control voltage input terminal INb is variable, the bandwidth of the oscillation frequency increases as the number of stages of the second output current channels increases (ΔA<ΔB<ΔC).

The slanted lines inFIG. 3show the oscillation frequency bandwidth of the VCO110when the stages of the second output current channels are fixed to a predetermined number “n” and the first and second control voltages are variable.

FIG. 4shows the relationship of the first control voltage Va and the oscillation frequency when the second control voltage Vb is zero and the number of stages of the first output current channels in the first current source112is changed. The number of stages of the first output current channels in the first current source112increases in the order of curve f1′, curve f1, and curve f1″. As shown inFIG. 4, the increase rate of the oscillation frequency relative to the change in the first control voltage increases as the number of stages of the output current channels in the first current source112increases.

The characteristics schematically shown inFIGS. 2to4are also obtained when the first control voltage input terminal INa is reversed with the second control voltage input terminal INb.

In the VCO110, which has the two control voltage input terminals INa and INb, the output voltage of a low pass filter142(first control voltage Va) is applied to the first control voltage input terminal INa, and the output voltage of a low pass filter170(second control voltage Vb) is applied to the second control voltage INb. This synchronizes the frequency of the clock signal (more accurately, the first divisional clock signal), which is generated by the VCO110, and the frequency of the wobble signal with the first control voltage input terminal INa, and the phase of the clock signal (more accurately, the second divisional clock signal) and the phase of the LPP signal with the second control voltage input terminal INb. In other words, the first control voltage Va roughly adjusts the oscillation frequency of the VCO110as shown in FIG.5(a), and the second control voltage Vb finely adjusts the oscillation frequency as shown in FIG.5(b).

The rough adjustment of the oscillation frequency of the VCO110with the first loop A and the fine adjustment of the oscillation frequency with the second loop B of the VCO110will now be discussed. The first loop A compares the rising edges and trailing edges of the first divisional clock signal and the wobble signal and controls the VCO110in accordance with the comparison result. The rising and trailing edges are both used for the reasons described below.

The RF amp20generates the binary wobble signal shown in FIG.7(b) from the signal of FIG.7(a), which corresponds to the wobble of the disc medium and which is read by the laser beam. The duty ratio of the wobble signal fluctuates. Thus, when controlling the VCO110in accordance with the difference between the phases of the divisional clock signal and the wobble signal, the control of the VCO110may be affected by the fluctuations of the duty ratio.

However, the cycle Tw between the centers of pulses and the phase of the wobble signal remain constant even when the pulse width Wh changes, as shown in FIG.7(d). Accordingly, the VCO110is controlled in accordance with the phase and the cycle Tw between pulse centers of the wobble signal and in accordance with the phase and the cycle between pulse centers of the divisional clock signals. This prevents the control of the VCO110from being affected by changes in the duty ratio.

More specifically, the first loop A ofFIG. 6includes a rising edge comparator120aand a trailing edge comparator120bto compare the rising edges and trailing edges of the wobble signal and the first divisional clock signal. A signal generated in accordance with the comparison result is provided from each of the comparators120aand120bto an associated one of charge pumps130aand130band converted to a predetermined charge pump output signal. The two charge pump signals are synthesized by an adder140, smoothed by the low pass filter142, and then applied as the first control voltage Va to the first control voltage input terminal INa of the VCO110. The first divider105divides the clock signal, which is controlled by the first control voltage Va, and provides the divided signal to the rising edge comparator120aand the trailing edge comparator120b.The first divisional clock signal is controlled so that its frequency is synchronized with the frequency of the wobble signal. The dividing ratio of the first divisional clock signal is 1/372. Thus, the output signal of the VCO110is controlled at 52.32 MHz.

Referring toFIG. 8, the gain of the charge pump130ais variable. The charge pump130aincludes a plurality of charge pump units CP, which output current corresponding to the output signal of the rising edge comparator120a,and a gain switching circuit131a,which drives selectively some of the charge pump units CP. The gain switching circuit131aswitches the number of stages of the driven charge pump units CP to switch the gain of the charge pump130a,or the amount of current output from the charge pump130arelative to the phase comparison output.

FIG. 9is a schematic circuit diagram of the rising edge comparator120aand one of the charge pump units CP. As shown inFIG. 9, the charge pump unit CP includes an output section132a,which outputs a signal corresponding to a comparison output signal from the rising edge comparator120a,and a bias circuit133a,which adjusts the output of the output section132a.

When the rising edge of the wobble signal is earlier than the rising edge of the first divisional clock signal, the output section132agenerates a high potential signal (charge operation) from when the wobble signal goes high to when the divisional clock signal goes high. Further, when the rising edge of the first divisional clock signal is earlier than the rising edge of the wobble signal, the output section132agenerates a low potential signal (discharge operation) from when the first divisional signal goes high to when the wobble signal goes high.

In the charge pump130a,the charge current and discharge current are set to be equal to each other when the period of the charge operation and the period of the discharge operation are the same.

The rising edge comparator120agenerates a predetermined output signal with the charge pump130afrom when one of the wobble signal and the first divisional clock signal goes high to when the other one of these signals goes high. The wobble signal and the first divisional clock signal are provided to different flip-flops (F/F). Each flip-flop outputs a high signal in synchronism with the rising edge of the provided pulse. When the pulses provided to the two flip-flops both go high, the two flip-flops are reset to interrupt the output of the signal from the charge pump130a.

The trailing edge comparator120band the charge pump130bofFIG. 6are configured in the same manner as the rising edge comparator120aand the charge pump130a.Referring toFIG. 6, the signal input to the rising edge comparator120ais inverted by an inverter and input to the trailing edge comparator120b.

FIG. 10shows the relationship between the signal input to the rising edge comparator120aand the trailing edge comparator120band the output of the adder140. As shown in FIG.10(b), when the timing of the rising edge and trailing edge of the first divisional clock signal is the same as the timing of the rising edge and trailing edge of the wobble signal (as indicated by β in FIG.10(a)), the output of the adder140is substantially zero.

In comparison, when the pulse width of the wobble signal (as indicated by α in FIG.10(a)) is smaller than the pulse width of the first divisional clock signal, the adder140generates a low potential signal (performs the discharge operation as indicated by α in FIG.10(c)) from when the first divisional clock signal goes high to when the wobble signal goes high. During the period from when the wobble signal goes low to when the first divisional clock signal goes low, the adder140generates a high potential signal (performs the charge operation as indicated by α in FIG.10(c)). The period from when the first divisional clock signal goes high to when the wobble signal goes high is equal to the period from when the wobble signal goes low to when the first divisional clock signal goes low. Thus, the discharge current and the charge current are equal to each other.

When the pulse width of the wobble signal is greater than the pulse width of the first divisional clock signal (as indicated by γ in FIG.10(a)), the adder140generates a high potential signal (performs the charge operation as indicated by γ in FIG.10(c)) from when the wobble signal goes high to when the first divisional clock signal goes high. During the period from when the first divisional clock signal goes low to when the wobble signal goes low, the adder140generates a low potential signal (performs the discharge operation as indicated by γ in FIG.10(c)). The period from when the wobble signal goes high to when the first divisional clock signal goes high is equal to the period from when the first divisional clock signal goes low to when the wobble signal goes low. Thus, the charge current and the discharge current are equal to each other.

When the pulse center of the first divisional clock signal and the wobble signal are equal, the charge current is equal to the discharge current in the charge pumps130aand130b.Accordingly, the pulse centers of the wobble signal and the first divisional clock signal are coincided with each other regardless of differences in the pulse widths of the wobble signal and the first divisional clock signal.

The second loop B ofFIG. 6will now be discussed. The second loop B predicts the period in which the LPP signal is detected to distinguish the LPP signal, which is provided to the clock generator100from the decoder30, from noise. A command section172stores the time the LPP signal was first detected when starting the recording of data and counts, for example, clock pulses to calculate the period from when the LPP signal is detected to when the next LPP signal is detected. The command section172generates a window pulse at predetermined cycles in synchronism with the timing at which the LPP signal is likely to be detected. The pulse width of the window pulse covers the period during which there is a possibility that the LPP signal may be detected. If the LPP signal is detected when the window pulse is being provided, an LPP output section174outputs the LPP signal. This prevents noise from being erroneously detected as the LPP signal.

A phase comparator150compares the phase of the LPP signal with the phase of the second divisional clock signal, which is generated by dividing the clock signal with the second divider176. The phase comparator150generates a comparison signal in accordance with the comparison result. A charge pump160converts the comparison signal so that it has a predetermined output level and provides the converted signal to a low pass filter170. The low pass filter170smoothes the comparison signal and generates the second control voltage Vb, which is provided to the second control voltage input terminal INb of the VCO110.

The dividing ratio of the second divider176is 1/5952. The second divider176generates the second divisional clock signal, which is offset from the LPP signal by a predetermined phase. The phase comparator150generates the comparison signal only when receiving the LPP signal from the LPP output section174. This controls the frequency of the clock signal to be 52.32 MHz.

The comparison between the LPP signal and the second divisional clock signal, or the rising edge of the second divisional clock signal provided to the phase comparator150is controlled so that it coincides with the pulse center of the LPP signal. To perform such control, the LPP output section174and the phase comparator150may be configured as shown inFIG. 11. Acharge pump unit CP, which is connected to the output side of the phase comparator150, is arranged in the charge pump160. The charge pump160is configured in the same manner as the charge pump130aof FIG.8.

FIG. 12shows the relationship between the window pulse, the LPP signal, the second divisional clock signal, and the output of the charge pump160. When the window pulse is not provided to the LPP output section174, noise is not provided to the phase comparator150even when noise is mixed in with the LPP signal (refer to FIGS.12(a) and12(b)). If the LPP signal is provided to the LPP output section174when the window pulse is provided to the LPP output section174(refer to FIGS.12(a) and12(b)), the LPP signal is provided to the phase comparator150. As a result, the charge pump160generates a high potential signal from when the LPP signal is provided to the phase comparator150to when the second divisional clock signal goes high. If the second divisional clock signal goes high when the LPP signal is being provided, the charge pump160generates a low potential signal (refer to FIGS.12(c) and12(d)).

When the charge operation time and discharge operation time are the same, the charge pump160equalizes the charge current and the discharge current. Thus, when the rising edge of the second divisional clock signal is located at the pulse center of the LPP signal, the charge current and the discharge current are equalized. In such manner, the VCO110is controlled so that the rising edge of the second divisional clock signal coincides with the pulse center of the LPP signal in accordance with the output signal of the charge pump160.

The fine adjustment with the second loop B synchronizes the frequency of the clock signal with the frequency of the wobble signal and the phase of the clock signal with the phase of the LPP signal. Thus, even if the center of the LPP signal is not coincided with the center of the wobble signal as shown by the broken lines in FIG.7(d), the phase of the clock signal is synchronized with the phase of the LPP signal.

A circuit for performing the two processes of rough adjustment and fine adjustment to synchronize the frequency of the clock signal with the frequency of the wobble signal and then synchronize the phase of the clock signal with the phase of the LPP signal will now be discussed.

Referring toFIG. 6, to perform the rough and fine adjustments, the clock generator100includes a first monitor circuit180, a second monitor circuit182, a voltage generation circuit184, and a control circuit186.

The first monitor circuit180retrieves the wobble signal and the first divisional clock signal to monitor whether the frequency synchronization of the wobble signal and the first divisional clock signal in the first loop A has been completed. The second monitor circuit182retrieves the LPP signal and the second divisional clock signal and monitors the state of the LPP signal and the second divisional clock in the second loop B.

Referring toFIG. 13, the voltage generation circuit184, which includes a voltage generation section184cand a decoder184d,generates a predetermined DC voltage. The voltage generation section184cgenerates a plurality of different voltages. The decoder184ddecodes a command signal, which is provided from the control circuit186, and selectively switches the value of the voltage generated by the voltage generation section184c.Referring toFIG. 6, a switching circuit185selectively supplies a predetermined DC voltage to the low pass filter170.

In accordance with a mode signal provided from an external device, the control circuit186controls the charge pumps130a,130b,and160, the voltage generation circuit184, and the switching circuit185. The mode signal designates the speed for recording data. In the data recording controller200, for example, a microcomputer, which controls the entire device, generates the mode signal.

The rough adjustment of the clock signal with the first loop A and the fine adjustment of the clock signal with the second loop B that are controlled by the control circuit186will now be discussed.

The microcomputer first provides the control circuit186with the mode signal to write mode data to the register115ain the gain control circuit115of FIG.2. In accordance with the mode data, the VCO110sets the current sources112and114so that the gain optimally corresponds to the data recording speed (linear velocity related to rotation of the optical disc1). In other words, the VCO110sets the current sources112and114to obtain the gain (drive capacity) that is optimal for controlling the oscillation frequency in correspondence with the data recording speed. During gain adjustment, it is preferred that the gain be increased as the data recording speed increases.

The control circuit186sets the drive capacities of the charge pumps130aand130bto optimally correspond to the data recording speed. In other words, the control circuit186sets the drive capacities in optimal correspondence with the data recording speed (linear velocity related to the rotation of the optical disc1). The setting of the drive capacities of the charge pumps130aand130bwith the control circuit186is performed by providing a command signal to the gain switching circuit131aofFIG. 8or a corresponding circuit. During the adjustment of the drive capacity, it is preferred that the drive capacity be increased as the data recording speed increases.

In accordance with the mode signal, the control circuit186generates a command signal, which is provided to the decoder184dof the voltage generation circuit184. Further, the control circuit186switches the switching circuit185to apply the DC voltage of the voltage generation circuit184to the low pass filter170and inactivates the charge pump160. In other words, the control circuit186does not apply an enable signal to all of the charge pump units CP to inactivate the charge pump160. This completes the initial setting with the clock generator100.

Subsequent to the initial setting, when the clock generator100is provided with the wobble signal, the frequencies of the first divisional clock signal and the wobble signal are synchronized in the first loop A. In this state, the charge pump160in the second loop B is inactivated. The DC voltage of the voltage generation circuit184, or a constant voltage, is applied to the second control voltage input terminal INb of the VCO110. At this point, the second loop B performs open loop control.

In the first loop A, when the first monitor circuit180detects that the difference between the frequencies of the first divisional clock signal and the wobble signal are converged within a predetermined range, the control circuit186switches the second loop B to closed loop control. That is, the control circuit186inactivates a predetermined number of charge pump units CP in the charge pump160and switches the switching circuit185so that the voltage of the voltage generation circuit184is not applied to the low pass filter170. This applies a voltage, which corresponds to the difference between the phases of the second divisional clock signal and the LPP signal, to the second control voltage input terminal INb of the VCO110.

Further, the control circuit186lowers the drive capacities of the charge pumps130aand130b.This causes the load on the first loop A to be less than the load on the second loop B after the difference between the frequencies of the wobble signal and the first divisional signal becomes small. Thus, the second loop B is hardly affected by the first loop A, and the second loop B properly performs fine adjustment of the clock signal.

When the first loop A is performing the rough adjustment, the voltage generation circuit184applies a constant (DC) voltage on the second control voltage input terminal INb of the VCO110. This smoothly switches the second loop B to fine adjustment. That is, when the charge pump160is switched from an inactivated state to an activated state, the oscillation frequency is prevented from suddenly fluctuating due to sudden changes in the value of the voltage applied to the second control voltage input terminal INb of the VCO110.

It is preferred that the DC voltage supplied to the second control voltage input terminal INb from the voltage generation circuit184be about the same as the voltage applied to the second control voltage input terminal INb when the second loop B synchronizes the phases of the second divisional clock signal and the LPP signal. This prevents the value of the DC voltage from suddenly fluctuating when the charge pump160is activated. It is preferred that the value of the DC voltage be a median value between maximum and minimum values of the voltage applied to the second control voltage input terminal INb.

The VCO110of the preferred embodiment has the advantages described below.

(1) The first and second current sources112and114of the VCO each have the output current channels, which are connected in parallel to one another, and selectively activates the output current channels to vary the changing amount of the output current relative to changes in the first and second control voltages Va and Vb. Thus, optimal gain adjustment is easily performed even when adjusting the gain of the VCO110with the two control voltages Va and Vb.

(2) The VCO110includes the first and second current sources112and114to adjust the gain of the VCO110by varying the changing amount of the output current relative to changes in the first and second control voltages Va and Vb. Thus, the characteristics of the VCO110is optimally varied in accordance with the rotation velocity of the optical disc1.

The first current source112may be replaced if necessary as long as the changing amount of the first control current relative to the changing amount of the first control voltage Va is enabled.

The second current source114may be replaced if necessary as long as the changing amount of the second control current relative to the changing amount of the second control voltage Vb is enabled.

The control voltage generation circuit116may be replaced if necessary as long as the control voltage of the ring oscillator118is generated in accordance with the synthesized current of the first and second control currents.

The ring oscillator118may include a delay circuit, which delaying amount is varied in accordance with the amount of supplied current. In this case, an odd number of inverters may be arranged at the input side or output side of the delay circuit.