A temperature sensor circuit is disclosed that uses multiple bipolar devices to generate a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current. A difference in the PTAT and CTAT current is evaluated using a feedback loop of an amplifier circuit which alternatively charges and discharges a capacitor to create a time-varying analog signal. A comparator circuit compares the analog signal to threshold values to generate an output digital signal whose duty cycle varies with temperature.

TECHNICAL FIELD

This disclosure relates to sensor circuits in computer systems, and, more particularly, to temperature sensor circuit operation.

DESCRIPTION OF THE RELATED ART

Modern computer systems may perform certain tasks or operations in response to changes in the environment in which the computer systems are located. For example, changes in ambient light may result in a computer system adjusted brightness of a display. Additionally, changes in temperature may result in a computer system adjusting a level of processing being performed in order to maintain the computer system within designated thermal limits. In some cases, rapid changes in acceleration may result in the computer system taking certain actions to prevent damage to movable parts within the computer system.

To react to changes in environment, a computer system may include multiple sensor circuits designed to detect various effects or situations. For example, such sensor circuits may include temperature sensors, acceleration sensors, ambient light sensors, and the like. The outputs of such sensor circuits may be polled by a processor or controller included in the computer system to determine what actions to perform.

Sensor circuits, such as those described above, may include any suitable combination of logic circuits, analog circuits, radio frequency circuits, and the like. In some cases, the sensor circuits may employ passive sensing techniques. Other sensor circuits may employ active sensing by transmitting signals and monitoring any returning signals.

DETAILED DESCRIPTION OF EMBODIMENTS

In many computer systems, sensor circuits are used to measure operating characteristics, which may be used to adjust the operation of the computer systems. For example, in some cases, the temperature of a computer system is monitored in order to protect the computer system against overheating or other functional failures resulting from the temperature exceeding allowed limits.

Many temperature sensor circuits rely on PNP bipolar transistors in combination with power supply regulator circuits, bandgap reference circuits, buffer circuits, biasing circuits, sigma-delta analog-to-digital conversion (ADC) circuits, and extensive logic circuits. In some cases, the temperature sensor circuits also include charge-pump circuits and voltage-to-frequency converter circuits.

Some sensor circuits, such as those described above, can consume a large area on an integrated circuit, making integration difficult. Moreover, the accuracy of such sensor circuits is limited due to sensitivities to multiple sources of variation, such as power supply voltage variation, device variation, and the like. To compensate for device variation, some sensor circuits are trimmed a second time after manufacture trimming in order to achieve desired levels of accuracy.

Techniques described in the present disclosure allow for the direct processing of a current proportional to absolute temperature (PTAT) in conjunction with a current complementary to absolute temperature (CTAT) using an analog feedback loop that evaluates a difference between the two currents to generate a signal whose duty cycle encodes the temperature. By processing the two currents in such a fashion, the need for an analog-to-digital conversion circuit and a bandgap reference circuit may be eliminated, reducing circuit area and the need for additional trimming.

Turning toFIG. 1, a block diagram of a sensor circuit is depicted. As illustrated, sensor circuit100includes current sources101and102, diode103, resistor104, amplifier circuit105, and Schmitt trigger circuit107.

Current source101is coupled between power supply node111and node116, and is configured to generate Iptatcurrent109. As described below, current source101may be implemented using any suitable combination of current mirrors, bipolar devices, and the like.

Diode103is coupled between node116and ground supply node112. In various embodiments, as Iptatcurrent109flows through diode103into ground supply node112, a voltage drop is developed across diode103, setting a voltage level on node116. In various embodiments, diode103may be implemented as a bipolar transistor, and the voltage drop across diode103may correspond to a base-to-emitter voltage (VBE) of the bipolar transistor.

Current source102is coupled between power supply node111and node114. In various embodiments, current source102is configured to source Iptatcurrent109to node114. In some embodiments, current source102may be implemented using a current mirror that is configured to mirror the current generated by current source101.

Ictatcurrent110flows through resistor104, which is coupled between node114and ground supply node112. Iptatcurrent109and Ictatcurrent110are combined at node114. In various embodiments, the currents are compared to each other via subtraction, resulting in a difference current (i.e., Idiffcurrent113) flowing into or out of capacitor106.

The value of resistor104is a function of output signal108. In some embodiments, resistor104may include multiple resistors and switches that are configured to open and close based on the voltage level of output signal108. By adjusting the value of resistor104, the polarity of Idiffcurrent113can be changed from positive to negative so that capacitor106is either charged or discharged. In various embodiments, resistor104may be implemented using polysilicon, metal, or any other suitable material available as part of a semiconductor manufacturing process.

Amplifier circuit105is configured to generate a voltage level on node115using the voltage levels on nodes116and114. Capacitor106is coupled between node115and node114, and, in conjunction with amplifier circuit105, integrates Idiffcurrent113to generate a voltage on node115. In various embodiments, amplifier circuit105may be implemented using any suitable combination of metal-oxide semiconductor field-effect transistors (MOSFETs), Fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAAFETs), or other suitable transconductance devices. Capacitor106may be implemented using a metal-oxide-metal (MOM), metal-insulator-metal (MIM), or any other suitable capacitor structure available as part of a semiconductor manufacturing process.

Schmitt trigger circuit107is configured to generate output signal108using the voltage on node115. In various embodiments, Schmitt trigger circuit107is configured to compare the voltage on node115to a high-threshold value and a low-threshold value. In response to a determination that the voltage on node115is below the low-threshold value, Schmitt trigger circuit107may set output signal108to a voltage level at or near ground potential. In response to a determination that the voltage on node115is greater than the high-threshold value, Schmitt trigger circuit107may set output signal108to a voltage level at or near that of power supply node111.

Example waveforms associated with the operation of a sensor circuit are depicted inFIG. 2. In various embodiments, the waveforms illustrated inFIG. 2may be associated with the operation of sensor circuit100. The top graph depicts the respective voltage levels of output signal108and node115as a function of time. The bottom graph depicts Idiffcurrent113as a function of time.

At time t1, output signal108transitions from ground to the voltage level of power supply node111in response to a voltage level of node115dropping below a low-threshold value. As described above, the low-threshold value against which the voltage level of node115is compared may be determined by Schmitt trigger circuit107.

The change in the value of output signal108results in a change in a value of resistor104. In various embodiments, the value of resistor104may toggle between two different values depending on the value of output signal108. By changing the value of resistor104, Idiffcurrent113toggles between two different values. In various embodiments, the two different values of Idiffcurrent113may flow in different directions, represented by having the two different values having different signs. As illustrated, the Idiffcurrent113transitions from a negative value to a positive value at time t1, which charges capacitor106, thereby increasing the voltage level of node115.

At time t2, output signal108transitions from the voltage level of power supply node111to ground potential in response to the voltage of node115exceeding a high-threshold level. As noted above, the high-threshold value may be determined by Schmitt trigger circuit107.

The change in output signal108results in another change in the value of resistor104. In this case, the change in the value of resistor104causes Idiffcurrent113to transition from a positive value to a negative value, which discharges capacitor106. As capacitor106is discharged, the voltage level of node115decreases.

At time t3, the voltage level of node115again drops below the low-threshold value, which results in output signal108changing value as described above. The process then repeats as long as sensor circuit100is active. As described below, the duty cycle of output signal108can be used to determine a value of the temperature of sensor circuit100.

Sensor circuits, such as sensor circuit100, may be fabricated using various semiconductor manufacturing processes. Depending on the type of devices available in a given semiconductor manufacturing process, a sensor circuit may be implemented using various circuit topologies. One particular circuit topology for a sensor circuit is depicted inFIG. 3. As illustrated, sensor circuit300includes devices301-307, resistors308,309and313, capacitor310, devices311and312, switch314, current source315and Schmitt trigger circuit316.

Device301is coupled between power supply node111and node317, and is controlled by a voltage level on node317. In a similar fashion, device302is coupled between power supply node111and node318, and is controlled by the voltage level on node317. In various embodiments, devices301and302form a current mirror circuit in which a current flowing through device301is replicated or “mirrored” in device302.

Device305is coupled between node317and resistor308, and is controlled by a voltage level on node318. In a similar fashion, device306is coupled between node318and device312, and is controlled by the voltage level on node318. In various embodiments, devices305and306form a current mirror circuit in which a current flowing through device306is mirrored in device305.

Resistor308is coupled between device305and device311, which is, in turn coupled to ground supply node112. A control terminal of device311is also coupled to ground supply node112. In a similar fashion, device312is coupled between device306and ground supply node112, and a control terminal of device312is also coupled to ground supply node112. In various embodiments, the current densities of devices311and312may be different. In some embodiments, devices311and312may be implemented as PNP bipolar transistors with different emitter areas. In some embodiments, the PNP bipolar transistors may be implemented as parasitic vertical bipolar transistors fabricated using a complementary metal-oxide semiconductor (CMOS) process.

Device303is coupled to power supply node111and node319, and is controlled by the voltage level on node317. In various embodiments, device303forms a current mirror circuit with device301. Device307is coupled between node319and node321, and is controlled by the voltage on node318. In various embodiments, device307forms a current mirror circuit with device306.

Resistor309is coupled between node321and node320. Resistor313is coupled between node320and ground supply node112. In various embodiments, resistors309and313may correspond to resistor104as depicted in the embodiment ofFIG. 1. Switch314is coupled between node320and ground supply node112, and is configured to selectively couple node320to ground supply node112using output signal108. In various embodiments, switch314may be implemented as a pass gate or other switching circuit that includes multiple MOSFETs, FinFETs, GAAFETs, or other suitable switching devices.

Device304is coupled between power supply node111and node322, and is controlled by a voltage level on node319. Capacitor310is coupled between node321and node322. Capacitor310is part of a feedback loop for an amplifier that includes device304. The addition of capacitor310in the feedback loop can help stabilize the amplifier. In various embodiments, capacitor310may be implemented as a MOM, MIM, or any other suitable capacitor structure.

Current source315is configured to sink a bias current from node322. In various embodiments, current source315may be implemented as one or more MOSFETs, FinFETs, GAAFETs, or other suitable transconductance devices where a gate or control terminal is set to a particular voltage level to determine a value of the bias current.

Schmitt trigger circuit316is configured to generate output signal108using a voltage level of node322. To generate output signal108, Schmitt trigger circuit316may be further configured to convert an analog voltage level on node322to a digital signal. In various embodiments, Schmitt trigger circuit316may be implemented as a comparator circuit with hysteresis that applies positive feedback to a non-inverting input of the comparator circuit.

During operation, devices311and312, in conjunction with devices301,302,305and306, form a PTAT biasing loop that results in a PTAT current flowing in devices301,302,305, and306. The base-to-emitter voltage of device312is a CTAT voltage. In various embodiments, device307is a replica of device306. As used herein, a replica device is a different instance of another device, and is designed and fabricated to have similar electrical characteristics. Since device307is a replica of device306, the CTAT base-to-emitter voltage of device312is transformed into a CTAT current flowing through resistors309and313.

The PTAT current and the CTAT current are combined at node321. In various embodiments, the currents are compared to each other via subtraction, resulting in a difference current (e.g., Idiffcurrent113) flowing into or out of capacitor310. The direction of the difference current is based on the values of resistors309and313, as well as the temperature of sensor circuit300.

Depending on the direction of the difference current, capacitor310is linearly charged or discharged. As capacitor310is charged and discharged, the voltage level of node322increases or decreases in a linear fashion. Schmitt trigger circuit316converts the analog voltage level of node322to a digital value on output signal108, which, in turn, controls switch314. By opening and closing switch314in such a fashion, the effective resistance between node321and ground supply node112toggles between two values (the value of resistor309and a combined value of resistors309and313). The change in effective resistance between node321and ground supply node112changes the direction of the difference current, resulting in the duty cycle of output signal108being modulated by the PTAT and CTAT currents to encode the temperature.

In various embodiments, devices301-304may be implemented as p-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices. Devices305-307may be implemented as n-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices. Resistors308,309, and313may be implemented using polysilicon, metal, or any other material available as part of a semiconductor manufacturing process.

As described above, the duty cycle of output signal108can be used to determine the temperature value. As noted above, Idiffcurrent113is the difference between the PTAT and CTAT currents. Substituting values in for Ictatand Iptat, Idiffcan be expressed as shown in Equation 1, where Rcis the effective CTAT resistance (either resistor309, or the sum of resistors309and313), Vbe2is the base-to-emitter voltage of device312, Vtis the thermal voltage of a PN junction, Rpis the value of resistor308, and N is the ratio of emitter areas between devices311and312. In various embodiments, the emitter area of device311may be greater than the emitter area of device312.

The time for the voltage level on node115to transition up or down is given by Equation 2, where ΔU is an amount of hysteresis, and C1is the value of capacitor310.

The duty cycle, denoted DC, of output signal108can then be defined in terms of the transition time as shown in Equation 3, where Δt1is the transition time for the voltage of node115where the CTAT resistance is the value of resistor309, and where Δt2is the transition time for the voltage of node115where the CTAT resistance is the sum of the respective values of resistors309and313.

Combining Equations 1 and 3, the duty cycle can be expressed as shown in Equation 4, where Rc1is the value of resistor309and Rc2is the value of resistor313.

From Equation 4, it is evident that the duty cycle depends on the ratio of devices311and312, the thermal voltage, and the base-to-emitter voltage of device312. It is noted that Vbe2can be approximated as Vbe2=VG0+tc·T, where VG0 is the silicon bandgap, tc is the temperature coefficient of device312, and T is the temperature. Substituting the approximation for Vbe2into Equation 4, the temperature may be expressed as shown in Equation 5, where kbis Boltzmann's constant, and e is Euler's constant.

As evident from Equation 2, output signal108does not depend on upper or lower threshold values of the voltage of node115. The hysteresis ΔU, therefore, affects only the frequency of the signal on node115, and can be implemented using a Schmitt trigger circuit (e.g., Schmitt trigger circuit316). It is further noted that the impact of capacitor310similarly affects only the frequency of the signal on node115.

As noted above, some of the devices in the embodiments of bothFIGS. 3 and 4are intended to be replicas of each other. During manufacturing, however, some differences between the devices are possible. One possible technique used to compensate for such variation is to employ dynamic element matching (DEM).

Devices401-403function in a similar fashion to devices301-303as depicted in the embodiment ofFIG. 3. In various embodiments, devices401-403may be implemented as p-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices.

Devices406-408function in a similar fashion to devices305-307as depicted in the embodiment ofFIG. 3. In various embodiments, devices406-408may be implemented as n-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices.

Device405is coupled between power supply node111and node424, and a control terminal of device405is coupled to device406. Current source419is coupled between node424and ground supply node112. Device405and current source419form a bias network for devices406-408that provides symmetric DC levels for the drain voltages of devices401-403and406-408. In various embodiments, device405may be implemented as a p-channel MOSFET, FinFET, GAAFET, or any other suitable transconductance device, and current source419may be implemented as a biased device that is part of a current mirror or other suitable circuit.

Device412is coupled between resistor409and ground supply node112, while device413is coupled between switch circuit421and ground supply node112. Resistor409is further coupled to switch circuit421. Respective control terminals of devices412and413are coupled to resistor414, which is, in turn, coupled to ground supply node112. In various embodiments, resistor409may be implemented using polysilicon, metal, or any other material available as part of a semiconductor manufacturing process.

In various embodiments, the current densities of devices412and413may be different. In some embodiments, devices412and413may be implemented as PNP bipolar transistors with different emitter areas. In some cases, the PNP bipolar transistors may be implemented as parasitic vertical bipolar transistors fabricated using a CMOS process. In various embodiments, devices412and413function in a similar fashion to devices311and312, respectively, of the embodiment depicted inFIG. 3.

Switch circuit420is configured to sequentially swap the drain connections between devices401-403using clock signals423. In a similar fashion, switch circuit421is configured to sequentially swap the drain connections between device406-408using clock signals423. By switching the drain connections of devices401-403and the drain connections of devices406-408, the effect on output signal108from differences in the electrical characteristics of devices401-403and from differences in the electrical characteristics of devices406-408can be reduced by averaging the duty cycle of output signal108over multiple cycles. In various embodiments, switch circuits420and421may be implemented using multiple pass gate circuits arranged in a wired-OR fashion or any other suitable circuit topology.

Clock generator circuit422is configured to generate clock signals423using output signal108. In various embodiments, clock generator circuit422may be configured to change respective values of clock signals423on each rising (or falling) edge of output signal108. Clock generator circuit422may, in some embodiments, be implemented as a shift register or other suitable sequential logic circuit.

Schmitt trigger circuit418is configured to generate output signal108using a voltage level of node425. To generate output signal108, Schmitt trigger circuit418may be further configured to convert an analog voltage level on node425to a digital signal. In various embodiments, Schmitt trigger circuit418may be implemented as a comparator circuit with hysteresis that applies positive feedback to a non-inverting input of the comparator circuit.

Device404is coupled between power supply node111and node425, and is controlled by a voltage level on node426. Capacitor411is coupled between node427and node425. Capacitor411is part of a feedback loop for an amplifier that includes device404. The addition of capacitor411in the feedback loop can help stabilize the amplifier. In various embodiments, capacitor411may be implemented as a MOM, MIM, or any other suitable capacitor structure.

Resistor410is coupled between node427and node428. Resistor415is coupled between node428and ground supply node112. In various embodiments, resistors410and415may correspond to resistor104as depicted in the embodiment ofFIG. 1. Device416is coupled between node428and ground supply node112, and is configured to selectively couple node428to ground supply node112using output signal108. In various embodiments, device416may be implemented as an n-channel MOSFET, FinFET, GAAFET, or other suitable switching device, and resistors410and415may be implemented using polysilicon, metal, or any other material available as part of a semiconductor manufacturing process.

Current source417is configured to sink a bias current from node425. In various embodiments, current source417may be implemented as one or more MOSFETs, FinFETs, GAAFETs, or other suitable transconductance devices where a gate or control terminal is set to a particular voltage level to determine a value of the bias current.

During operation, devices412and413, in conjunction with devices401,402,406and407, form a PTAT biasing loop that results in a PTAT current flowing in devices401,402,406, and407. The base-to-emitter voltage of device413is a CTAT voltage. In various embodiments, device408is a replica of device407and, as such, the CTAT base-to-emitter voltage of device413is transformed into a CTAT current flowing through resistors410and415.

The PTAT current and the CTAT current are combined at node427. In various embodiments, the currents are compared to each other via subtraction, resulting in a difference current (e.g., Idiffcurrent113) flowing into or out of capacitor411. The direction of the difference current is based on the values of resistors410and415, as well as the temperature of sensor circuit400.

Depending on the direction of the difference current, capacitor411is linearly charged or discharged. As capacitor411is charged and discharged, the voltage level of node425increases or decreases in a linear fashion. Schmitt trigger circuit418converts the analog voltage level of node425to a digital value on output signal108, which, in turn, controls device416. By activating and deactivating device416in such a fashion, the effective resistance between node427and ground supply node112toggles between two values (the value of resistor410and a combined value of resistors410and415). The change in effective resistance between node427and ground supply node112, changes the direction of the difference current, resulting in the duty cycle of output signal108being modulated by the PTAT and CTAT currents to encode the temperature in the duty cycle of signal108.

To summarize, various embodiments of a temperature sensor circuit are disclosed. Broadly speaking, an apparatus is contemplated in which a first current source is configured to generate a first current whose value is proportional to temperature, and a second current source is configured to generate a second current whose value is complementary to temperature. An amplifier circuit is configured to generate an integrated signal using a difference between the first current and the second current, and a comparator circuit is configured to generate, using the integrated signal, an output signal whose duty cycle is based on the difference between the first current and the second current.

In some embodiments, the apparatus further includes a first bipolar device and a second bipolar device coupled to the first bipolar device, where a first emitter area of the first bipolar device is greater than a second emitter area of the second bipolar device. The first bipolar device and the second bipolar device are configured to provide bias to the first current source, and the second current source is further configured to generate the second current using a base-to-emitter voltage of the second bipolar device.

In other embodiments, the apparatus further comprises a capacitor coupled between an output of the amplifier circuit and an input of the amplifier circuit. To generate the integrated signal, the amplifier circuit is further configured to charge the capacitor during a first time period using the difference current, and discharge the capacitor during a second time period using the difference current.

In another embodiment, to generate the output signal, the comparator circuit is further configured to compare the integrated signal to an upper threshold and a lower threshold. In various embodiments, the apparatus further comprises a variable resistor coupled to the input of the amplifier circuit, and where a value of the variable resistor is based on the output signal. In some cases, the variable resistor includes a first resistor and a second resistor coupled in series, and a switch configured to couple a node between the first resistor and the second resistor using the output signal.

Turning toFIG. 5, a flow diagram depicting an embodiment of a method for operating a sensor circuit is illustrated. The method, which may be applied to various sensor circuits, such as temperature sensor circuit100, begins in block501.

The method includes generating a first current whose value is proportional to temperature (block502). In various embodiments, the method further includes generating the first current using a first bipolar device and a second bipolar device. In some embodiments, a first emitter area of the first bipolar device is greater than a second emitter area of the second bipolar device. As described above, the first bipolar device and the second bipolar device may be included as part of a bias circuit configured to provide a bias voltage and/or current to one or more current mirror circuits.

The method also includes generating a second current whose value is complementary to temperature (block503). In some embodiments, the method further includes generating the second current using a base-to-emitter voltage of the second bipolar device. In various embodiments, generating the second current includes converting the base-to-emitter voltage to a current using a current mirror circuit or other suitable circuit.

The method further includes combining the first current and the second current to generate a difference current (block504). In various embodiments, combining the first current and the second current includes subtracting the second current from the first current. In some embodiments, the first current and the second current are combined on an input node of an amplifier circuit.

The method also includes adjusting a duty cycle of an output signal using the difference current (block505). In various embodiments, adjusting the duty cycle of the output signal may include charging, during a first time period and using the difference current, a capacitor in the feedback loop of the amplifier circuit, discharging, during a second time period and using the difference current, the capacitor, and generating an integrated signal using an output voltage of the amplifier circuit. In some cases, the method may further include comparing the integrated signal to an upper threshold and a lower threshold to generate the output signal.

In some embodiments, adjusting the duty cycle of the output signal may include changing, using the output signal, a value of a variable resistor coupled to an input of the amplifier circuit. In various embodiments, the variable resistor may include a first resistor and a second resistor coupled in series, and wherein changing the value of the variable resistor includes coupling, using the output signal, a node between the first resistor and the second resistor to a ground supply node.

The method further includes determining a temperature value using a variation in the duty cycle of the output signal (block506). In various embodiments, determining the temperature value may include incrementing a counter circuit using the output signal, and comparing a value of the counter circuit accumulated over a particular period of time to a reference count value. The method concludes in block507.

A block diagram of an embodiment of a system-on-a-chip (SoC) is illustrated inFIG. 6. As illustrated, SoC600includes processor circuit601, memory circuit602, analog/mixed-signal circuits603, input/output circuits604, and sensor circuit605each of which is coupled to communication bus606. It is noted that in various embodiments, sensor circuit605may correspond to any of the sensor circuits described above. In various embodiments, SoC600may be configured for use in a desktop computer, server, or in a mobile computing application such as, a tablet, laptop computer, or wearable computing device.

Processor circuit601may, in various embodiments, be representative of a general-purpose processor that performs computational operations. For example, processor circuit601may be a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, or the like, and may be implemented as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc. In some embodiments, processor circuit601may interface to memory circuit602, analog/mixed-signal circuits603, input/output circuits604, and sensor circuit605via communication bus606. In various embodiments, processor circuit601may be configured to extract a temperature value using a duty cycle of a signal generated by sensor circuit605. In some cases, processor circuit601may employ a counter circuit that is incremented by the signal generated by sensor circuit605. In such cases, processor circuit601may be further configured to compare a count value of the counter circuit accumulated over a particular time period to a reference count value to extract the temperature value.

Memory circuit602may, in various embodiments, include any suitable type of memory such as a Dynamic Random-Access Memory (DRAM), a Static Random-Access Memory (SRAM), a Read-Only Memory (ROM), Electrically Erasable Programmable Read-only Memory (EEPROM), or a non-volatile memory, for example. It is noted that in the embodiment of a computer system inFIG. 6, a single memory circuit is depicted. In other embodiments, any suitable number of memory circuits may be employed.

Analog/mixed-signal circuits603may include a crystal oscillator circuit, an analog-to-digital converter (ADC) circuit, a digital-to-analog converter (DAC) circuit, and a phase-locked loop circuit (all not shown). In other embodiments, analog/mixed-signal circuits603may be configured to perform power management tasks with the inclusion of on-chip power supplies and voltage regulators.

Input/output circuits604may be configured to coordinate data transfer between SoC600and one or more peripheral devices. Such peripheral devices may include, without limitation, storage devices (e.g., magnetic or optical media-based storage devices including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral devices. In some embodiments, input/output circuits604may be configured to implement a version of Universal Serial Bus (USB) protocol or IEEE 1394 (Firewire®) protocol.

Input/output circuits604may also be configured to coordinate data transfer between SoC600and one or more devices (e.g., other computing systems or integrated circuits) coupled to SoC600via a network. In one embodiment, input/output circuits604may be configured to perform the data processing necessary to implement an Ethernet (IEEE 802.3) networking standard such as Gigabit Ethernet or 10-Gigabit Ethernet, for example, although it is contemplated that any suitable networking standard may be implemented. In some embodiments, input/output circuits604may be configured to implement multiple discrete network interface ports.

Sensor circuit605may, in various embodiments, correspond to any of the sensor circuits described above. For example, in some embodiments, sensor circuit605may be implemented using temperature sensor circuit100. Although only one sensor circuit is depicted in the embodiment ofFIG. 6, in other embodiments, any suitable number of sensor circuits may be employed.

Turning now toFIG. 7, various types of systems that may include any of the circuits, devices, or systems discussed above are illustrated. System or device700, which may incorporate or otherwise utilize one or more of the techniques described herein, may be utilized in a wide range of areas. For example, system or device700may be utilized as part of the hardware of systems such as a desktop computer710, laptop computer720, tablet computer730, cellular or mobile phone740, or television750(or set-top box coupled to a television).

Similarly, disclosed elements may be utilized in a wearable device760, such as a smartwatch or a health-monitoring device. Smartwatches, in many embodiments, may implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device may also be designed solely to perform health-monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to an emergency medical service, etc. Other types of devices are also contemplated, including devices worn on the neck, devices implantable in the human body, glasses or a helmet designed to provide computer-generated reality experiences such as those based on augmented and/or virtual reality, etc.

System or device700may also be used in various other contexts. For example, system or device700may be utilized in the context of a server computer system, such as a dedicated server or on shared hardware that implements a cloud-based service770. Still further, system or device700may be implemented in a wide range of specialized everyday devices, including devices780commonly found in the home such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Elements may also be implemented in various modes of transportation. For example, system or device700could be employed in the control systems, guidance systems, entertainment systems, etc. of various types of vehicles790.

The applications illustrated inFIG. 7are merely exemplary and are not intended to limit the potential future applications of disclosed systems or devices. Other example applications include, without limitation: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

FIG. 8is a block diagram illustrating an example of a non-transitory computer-readable storage medium that stores circuit design information, according to some embodiments. In the illustrated embodiment, semiconductor fabrication system820is configured to process design information815stored on non-transitory computer-readable storage medium810and fabricate integrated circuit830based on design information815.

Design information815may be specified using any of various appropriate computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information815may be usable by semiconductor fabrication system820to fabricate at least a portion of integrated circuit830. The format of design information815may be recognized by at least one semiconductor fabrication system, such as semiconductor fabrication system820, for example. In some embodiments, design information815may include a netlist that specifies elements of a cell library, as well as their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit830may also be included in design information815. Such cell libraries may include information indicative of device or transistor level netlists, mask design data, characterization data, and the like, of cells included in the cell library.

Integrated circuit830may, in various embodiments, include one or more custom macrocells, such as memories, analog or mixed-signal circuits, and the like. In such cases, design information815may include information related to included macrocells. Such information may include, without limitation, schematics capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to graphic data system (GDSII), or any other suitable format.

In various embodiments, integrated circuit830is configured to operate according to a circuit design specified by design information815, which may include performing any of the functionality described herein. For example, integrated circuit830may include any of various elements shown or described herein. Further, integrated circuit830may be configured to perform various functions described herein in conjunction with other components. Further, the functionality described herein may be performed by multiple connected integrated circuits.

The present disclosure includes references to “embodiments,” which are non-limiting implementations of the disclosed concepts. References to “an embodiment,” “one embodiment,” “a particular embodiment,” “some embodiments,” “various embodiments,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of the disclosure. Not all embodiments will necessarily manifest any or all of the potential advantages described herein.

Unless stated otherwise, the specific embodiments are not intended to limit the scope of claims that are drafted based on this disclosure to the disclosed forms, even where only a single example is described with respect to a particular feature. The disclosed embodiments are thus intended to be illustrative rather than restrictive, absent any statements to the contrary. The application is intended to cover such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure.

Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. The disclosure is thus intended to include any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.

For example, while the appended dependent claims are drafted such that each depends on a single other claim, additional dependencies are also contemplated. Where appropriate, it is also contemplated that claims drafted in one statutory type (e.g., apparatus) suggest corresponding claims of another statutory type (e.g., method).

References to the singular forms such as “a,” “an,” and “the” are intended to mean “one or more” unless the context clearly dictates otherwise. Reference to “an item” in a claim thus does not preclude additional instances of the item.

When the term “or” is used in this disclosure with respect to a list of options, it will generally be understood to be used in the inclusive sense unless the context provides otherwise. Thus, a recitation of “x or y” is equivalent to “x or y, or both,” covering x but not y, y but not x, and both x and y. On the other hand, a phrase such as “either x or y, but not both” makes clear that “or” is being used in the exclusive sense.

Various “labels” may proceed nouns in this disclosure. Unless context provides otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. The labels “first,” “second,” and “third” when applied to a particular feature do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise.

The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function. This unprogrammed FPGA may be “configurable to” perform that function, however.

Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Should Applicant wish to invoke Section 112(f) during prosecution, it will recite claim elements using the “means for” [performing a function] construct.