Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth

A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

TECHNICAL FIELD

The present invention relates generally to semiconductor technology, and more particularly to heterojunction bipolar transistors and a method of manufacturing therefor using selective epitaxial growth.

BACKGROUND ART

A popular device for controllably varying the magnitude of electrical current flowing between two terminals is a bipolar junction transistor (BJT). BJTs have three terminals. The three terminals include a base terminal, a collector terminal, and an emitter terminal. The movement of electrical charge carriers, which produce electrical current flow between the collector and the emitter terminals, varies dependent upon variations in the voltage on the base terminal thereby causing the magnitude of the current to vary. Thus, the voltage across the base and emitter terminals controls the current flow through the emitter and collector terminals.

The terminals of a BJT are connected to their respective base, collector and emitter structures formed in a semiconductor substrate. BJTs comprise two p-n junctions placed back-to-back in close proximity to each other, with one of the regions common to both junctions. There is a first junction between the base and the emitter, and a second junction between the emitter and the collector. This forms either a p-n-p or an n-p-n transistor depending upon the characteristics of the semiconductive materials used to form the BJT.

Recently, demand for BJTs has increased significantly because these transistors are capable of operating at higher speeds and driving more current. These characteristics are important for high-speed, high-frequency communication networks such as those required by cell phones and computers.

BJTs can be used to provide linear voltage and current amplification because small variations of the voltage between the base and emitter terminals, and hence the base current, result in large variations of the current and voltage output at the collector terminal. The transistor can also be used as a switch in digital logic and power switching applications. Such BJTs find application in analog and digital circuits and integrated circuits at all frequencies from audio to radio frequency.

Heterojunction bipolar transistors (HBTs) are BJTs where the emitter-base junction is formed from two different semiconductive materials having similar characteristics. Materials used in forming the base-emitter junction are preferably compound semiconductive materials such as silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), or a combination thereof. HBTs using compound semiconductive materials have risen in popularity due to their high-speed and low electrical noise capabilities, coupled with the ability to manufacture them using processing capabilities used in the manufacture of silicon BJTs. Lateral HBTs are HBTs in which the current flow is parallel to the surface of the substrate on which the HBT is manufactured. HBTs have found use in higher-frequency applications such as cell phones, optical fiber, and other high-frequency applications requiring faster switching transistors, such as satellite communication devices.

Although the use of compound semiconductive materials has proven useful in HBTs, once formed by existing methods, this material is subsequently subjected to multiple thermal cycles, implantations and/or etching processes during the formation steps of the remaining elements of the HBT. Such steps include the deposition and etching of oxide layers, nitride layers and subsequently formed polysilicon layers. Several of these processing steps inherently damage the compound semiconductive material. Etching polysilicon over a compound semiconductive layer, for example, adversely affects the compound semiconductive material because the etchants used do not selectively etch only the polysilicon. Some of the compound semiconductive material is also etched during this processing step, resulting in HBTs that are slower and exhibit poor noise performance compared to other HBTs on the same semiconductor wafer. The adverse effects of etching the emitter window persist however. During the operation of etching the stack over-etching still occurs. The lack of adequate controls and reproducibility of over-etching typically results in the intrinsic base being implanted after formation of the emitter window. Implantation on the over-etched surface does not overcome the problems associated with the over-etched surface.

Furthermore, to improve the operating speed of a HBT, it is important that the base structure be thin enough to minimize the time it takes electronic charges to move from the emitter to the collector, thereby minimizing the response time of the HBT. It is also important, however, that the base structure have a high concentration of dopant in order to minimize base resistance. Typically, ion implantation techniques are used to form a base layer. However, this technique has the problem of ion channeling, which limits the minimum thickness of the base layer. Another disadvantage of ion implantation is that the compound semiconductive layer is often damaged by the ions during implantation.

Additionally, high-temperature annealing typically is required to drive dopants into the various material layers. This annealing step, however, alters the profile of concentration levels of the dopants within the various layers of semiconductive materials forming the transistor to create undesirable dopant profiles within the various material layers.

Existing methods of manufacturing HBTs still have the problems associated with over-etching, the detrimental effects of ion implantation and annealing, and consistency of manufacturability.

Additionally, existing HBTs require both shallow trench isolations STIs) and deep trench isolations (DTIs) for both transistor isolation and to reduce collector-substrate load capacitance as well as other parasitic capacitances in the transistor.

Furthermore, the differences in manufacturing techniques used to form complimentary metal oxide semiconductor (CMOS) transistors and HBTs have made it difficult to manufacture bipolar complimentary metal oxide semiconductor (BiCMOS) integrated circuits using compound semiconductive materials that have proven to be useful in HBTs.

DISCLOSURE OF THE INVENTION

The present invention provides a method for manufacturing a heterojunction bipolar transistor with a substrate. A collector structure is formed on the substrate, and an extrinsic base structure is formed over the collector structure. An intrinsic base structure is formed laterally adjacent the collector structure. An emitter structure is formed laterally adjacent the intrinsic base structure. An interlevel dielectric layer is formed and a number of contacts are formed through the interlevel dielectric layer to the collector structure, the base structure, and the emitter structure.

The present invention overcomes the problems associated with existing HBTs. In some embodiments, shallow trench isolations and deep trench isolations are unnecessary.

Parasitic capacitances are reduced. There is a high reduction in the collector-substrate capacitance thereby reducing the load capacitance at high frequencies. There is a significant reduction in the base-collector capacitance because there is no extrinsic base directly contacting the collector.

The present invention also can be utilized with existing bipolar complimentary metal oxide semiconductor (BiCMOS) processing techniques.

Certain embodiments of the invention have other advantages in addition to, or in place of, those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known configurations and process steps are not disclosed in detail.

Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the FIGs. Generally, the device can be operated in any orientation.

The term “processing” or “processed” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.

Referring now toFIG. 1, therein is shown a heterojunction bipolar transistor (HBT)100in an intermediate stage of manufacture in accordance with the present invention. The HBT100includes a semiconductor substrate102, such as a lightly doped semiconductor of a first conductivity type, for example, a p−doped silicon substrate.

A first insulating layer104, such as an oxide layer, is formed over the semiconductor substrate102. A second insulating layer106, such as a nitride layer, is formed over the first insulating layer104. A third insulating layer108, such as an oxide layer, is formed over the second insulating layer106. The first insulating layer104, the second insulating layer106, and the third insulating layer108are processed to form a collector structure110, such as lightly doped silicon such as an n−doped epitaxially grown silicon. A first insulating structure112is formed over the top of the collector structure110.

Referring now toFIG. 2, therein is shown the structure ofFIG. 1after formation of an extrinsic base stack200. The extrinsic base stack200includes an extrinsic base structure202formed over the first insulating structure112. A first silicide layer204is formed over the extrinsic base structure202. A second insulating structure206, such as a tetraethylorthosilicate (TEOS) structure, is formed over the first silicide layer204. A third insulating structure208, such as a nitride structure, is formed over the second insulating structure206.

The extrinsic base stack200is formed by depositing the layers of the materials that make up the extrinsic base stack200, and then masking, etching, and processing the layers to form the structures in the extrinsic base stack200. Thus, the extrinsic base stack200is comprised of the extrinsic base structure202, the first silicide structure204, the second insulating structure206, and the third insulating structure208.

Referring now toFIG. 3, therein is shown the structure ofFIG. 2after formation of an insulating spacer300, such as a nitride spacer around the extrinsic base stack200. The insulating spacer300is formed by depositing an insulating material, such as a nitride layer, and processing the insulating layer using conventional semiconductor processing techniques.

Referring now toFIG. 4, therein is shown the structure ofFIG. 3after formation of an intrinsic base window400. The intrinsic base window400is formed by providing a photoresist layer402that is then masked and processed. The intrinsic base window400is formed by performing a dry etch of the third insulating layer108and then performing a wet hydrofluoric acid/buffered oxide etch (HF/BOE) dip, which is an isotropic etch to form an undercut region404under a portion of the extrinsic base stack200.

Referring now toFIG. 5, therein is shown the structure ofFIG. 4after formation of an intrinsic base structure500. The photoresist layer402shown inFIG. 4is stripped off. The intrinsic base structure500is formed by selectively growing a compound semiconductive material laterally on the collector structure110. Preferably, the compound semiconductive material comprises at least one of silicon-germanium (Si/Ge), silicon-germanium-carbon (Si/Ge/C), and a combination thereof.

The intrinsic base structure500also preferably is heavily doped in situ to provide a heavily doped compound semiconductive material of the first conductivity type. The compound semiconductive material can be doped in situ, for example, by adding boron (B) to the compound semiconductive material as it is selectively formed on the lateral side of the collector structure110in the undercut region404beneath the extrinsic base stack200.

Referring now toFIG. 6, therein is shown the structure ofFIG. 5after formation of an extrinsic collector window600. The extrinsic collector window600is formed by applying a photoresist layer602. The photoresist layer602is then masked and processed to form the extrinsic collector window600on the side of the collector structure110, opposite the side on which the intrinsic base structure500is formed.

Referring now toFIG. 7, therein is shown the structure ofFIG. 6after formation of an extrinsic collector structure700and an emitter structure702. The extrinsic collector structure700and the emitter structure702are formed by stripping the photoresist layer602shown inFIG. 6and forming a doped polysilicon layer in the extrinsic collector window600, and in the intrinsic base window400shown inFIG. 4andFIG. 5. The polysilicon layer is doped in situ to create a polysilicon layer of the second conductivity type, such as an n+-polysilicon layer. The polysilicon layer is then etched back so it is substantially level with the upper surface of the third insulating layer108thereby forming the extrinsic collector structure700and the emitter structure702. If necessary, a rapid thermal anneal (RTA) can be performed to drive the dopant into the polysilicon layer.

Alternatively, the extrinsic collector structure700and the emitter structure702can be formed by selectively growing a doped polysilicon material of the second conductivity type, such as an n+doped polysilicon, in the extrinsic collector window600and in the intrinsic base window400.

After the extrinsic collector structure700and the emitter structure702are formed, a second silicide structure704is formed over the extrinsic collector structure700. A third silicide structure706is formed over the emitter structure702. The second silicide structure704and the third silicide structure706are formed using conventional processing techniques known in the semiconductor manufacturing industry.

Referring now toFIG. 8, therein is shown the structure ofFIG. 7after formation of a collector contact802, a base contact804, and an emitter contact806through an interlevel dielectric (ILD) layer800. The ILD layer800is formed over the structure shown inFIG. 7by depositing a dielectric material, such as an oxide, and then planarizing the dielectric material, such as by using a chemical mechanical polishing (CMP) process. A number of trenches are formed in the ILD layer800. The trenches are filled with a suitable contact material such as tungsten (W) to form the collector contact802, the base contact804and the emitter contact806.

The collector contact802is formed through the ILD layer800in contact with the second silicide structure704over the extrinsic collector structure700. The base contact804is formed through the ILD layer800in contact with the first silicide structure204over the extrinsic base structure202. The emitter contact806is formed through the ILD layer800in contact with the third silicide structure706over the emitter structure702.

Referring now toFIG. 9, therein is shown an alternate embodiment for formation of a collector contact902, a base contact904, and an emitter contact906in the structure ofFIG. 8. The collector contact902is formed through the ILD layer800in contact with the outer side of the extrinsic collector structure700. The base contact904is formed through the ILD layer800, through the third insulating structure208, through the second insulating structure206, and in contact with the first silicide structure204above the extrinsic base structure202. The emitter contact906is formed through the ILD layer800in contact with the outer side of the emitter structure702.

Referring now toFIG. 10, therein is shown a plan view of a circular layout1000of the HBT100shown inFIGS. 1 through 9in accordance with the present invention. The circular layout1000includes an emitter structure1002in the center of the circular layout1000. An extrinsic base structure1004surrounds the emitter structure1002separated by a first insulating layer1003. A collector structure1006surrounds the extrinsic base structure1004separated by a second insulating layer1005. It will be readily apparent to those skilled in the art that the circular layout1000could also be oval.

Referring now toFIG. 11, therein is shown a plan view of a rectangular layout1100of the HBT100shown inFIGS. 1 through 9manufactured in accordance with the present invention. The rectangular layout1100includes an emitter structure1102located in the center of the rectangular layout1100. An extrinsic base structure1104surrounds the emitter structure1102separated by a first insulating layer1103. A collector structure1106surrounds the extrinsic base structure1104separated by a second insulating layer1105. It will be apparent to those skilled in the art that the rectangular layout1100could also be a square.

Referring now toFIG. 12, therein is shown a HBT1200in an intermediate stage of manufacture in accordance with an alternate embodiment of the present invention. The HBT1200includes a semiconductor substrate1202having an extrinsic collector structure1204, such as a buried collector region therein. An intrinsic collector structure1206, such as a sub-collector region, is located over the extrinsic collector structure1204. Together the extrinsic collector structure1204and the intrinsic collector structure1206will be referred to as a collector structure1207.

The semiconductor substrate also includes a number of shallow trench isolations (STIs)1208. The STIs1208are formed by creating trenches in the semiconductor substrate1202, and then filling the trenches with an insulating material, such as an oxide. The outermost STIs1208also have a number of deep trench isolations (DTIs)1210located beneath the number of STIs1208.

Over the semiconductor substrate1202is a field-insulating layer1212, such as a field oxide layer. A first insulating layer1214, such as an oxide layer, is formed over the field-insulating layer1212. A base polysilicon layer1216, such as a heavily doped polysilicon layer of the first conductivity type, for example, a p+doped polysilicon layer, is formed over the first insulating layer1214. A second insulating layer1218, such as an oxide layer, is formed over the base polysilicon layer1216. An emitter polysilicon layer1220, such as a heavily doped polysilicon layer of the second conductivity type, for example, an n+doped polysilicon layer, is formed over the second insulating layer1218. A third insulating layer1222, such as an oxide layer is formed over the emitter polysilicon layer1220. A photoresist layer1224is used to create a mask over the third insulating layer1222. The photoresist layer1224is located over the intrinsic collector structure1206.

Referring now toFIG. 13, therein is shown the structure ofFIG. 12after formation of an emitter-base stack1300. The emitter-base stack1300is formed by using photolithographic techniques to remove, such as by etching, the third insulating layer1222, the emitter polysilicon layer1220, the second insulating layer1218, the base polysilicon layer1216, and the first insulating layer1214shown inFIG. 12in the areas not covered by the photoresist layer1224. There is thus formed an extrinsic emitter structure1220A formed from the emitter polysilicon layer1220shown inFIG. 12, and an extrinsic base structure1216A formed from the base polysilicon layer1216shown inFIG. 12in the emitter-base stack1300.

Referring now toFIG. 14, therein is shown the structure ofFIG. 13after formation of a recess1400around the emitter-base stack1300. The recess1400is formed by removing, such as by etching, a portion of the STIs1208on either side of the emitter-base stack1300to reveal an upper portion of the intrinsic collector structure1206.

Referring now toFIG. 15, therein is shown the structure ofFIG. 14after formation of an intrinsic base layer1500. The photoresist layer1224shown inFIG. 14is removed. Then the intrinsic base layer1500is formed by depositing a thin, lightly doped compound semiconductive material of the first conductivity type, such as a p−-doped compound semiconductive material over the structure shown inFIG. 14. Preferably, the compound semiconductive material comprises silicon and at least one of silicon-germanium (Si/Ge), silicon-germanium-carbon (Si/Ge/C), and a combination thereof.

Referring now toFIG. 16, therein is shown the structure ofFIG. 15after formation of an insulating spacer1600over the intrinsic base layer1500. The insulating spacer1600is formed by depositing an insulating material, such as a nitride, over the structure shown inFIG. 15and processing the insulating material to form the insulating spacer1600. The insulating spacer1600covers a portion of the intrinsic base layer1500and surrounds a lower portion of the emitter-base stack1300formed by the recess1400. The insulating spacer1600extends up the sides of the emitter-base stack1300to cover the first insulating layer1214, the extrinsic base structure1216A, and the second insulating layer1218of the emitter-base stack1300.

Referring now toFIG. 17, therein is shown the structure ofFIG. 16after processing the intrinsic base layer1500to form a bi-layer spacer1700. The intrinsic base layer1500is removed, such as by etching, except in the area under the insulating spacer1600so an unetched portion1702of the intrinsic base layer1500remains. Thus, the bi-layer spacer1700comprising the unetched portion1702of the intrinsic base layer1500and the insulating spacer1600is formed.

Referring now toFIG. 18, therein is shown the structure ofFIG. 17after formation of an intrinsic base structure1800. The intrinsic base structure1800is formed by removing the insulating spacer1600thereby uncovering the unetched portion of the intrinsic base layer1500. The intrinsic base structure1800is formed around the emitter-base stack1300. The intrinsic base structure1800is in contact with the extrinsic base structure1216A.

Referring now toFIG. 19, therein is shown the structure ofFIG. 18after formation of an emitter layer1900. The emitter layer1900is formed by depositing a semiconductive layer, such as a heavily doped polysilicon layer of the second conductivity type, for example, an n+polysilicon layer over the structure shown inFIG. 18.

Referring now toFIG. 20, therein is shown the structure ofFIG. 19after formation of an emitter structure2000. The emitter structure2000is formed by masking, etching and processing the emitter layer1900to form the emitter structure2000over the intrinsic base structure1800. The upper portion of the emitter structure2000is in contact with the extrinsic emitter structure1220A in the emitter-base stack1300.

Referring now toFIG. 21, therein is shown the structure ofFIG. 20after formation of an emitter contact2100, a base contact2102, and a collector contact2104in an interlevel dielectric (ILD) layer2106. The ILD layer2106is formed over the structure shown inFIG. 20by depositing a dielectric material, such as an oxide, and then planarizing the dielectric material, such as by using a chemical mechanical polishing (CMP) process. A number of trenches are formed in the ILD layer2106. The trenches are filled with a suitable contact material such as tungsten (W) to form the emitter contact2100, the base contact2102, and the collector contact2104.

The emitter contact2100is formed through the ILD layer2106in contact with the extrinsic emitter structure1220A. The base contact2102is formed through the ILD layer2106in contact with the extrinsic base structure1216A. The collector contact2104is formed through the ILD layer2106in contact with the extrinsic collector structure1206.

The base contact2102is shown in phantom inFIG. 21as being offset from the emitter contact2100for clarity of presentation. It will be appreciated by those skilled in the art that the base contact2102is actually substantially in line with the emitter contact2100as described in connection withFIG. 22AandFIG. 22Bdescribed below.

Referring now toFIG. 22A, therein is shown a plan view of the emitter structure2000, the intrinsic base structure1800, and the collector structure1207ofFIG. 21. The emitter structure2000covers the intrinsic base structure1800. The collector structure1207is substantially perpendicular to the emitter structure2000and the intrinsic base structure1800.

Referring now toFIG. 22Btherein is shown a cross sectional view taken along line22B—22B ofFIG. 21. The emitter contact2100is formed by etching the third insulating layer1222to stop on the extrinsic emitter structure1220A. The base contact is formed by etching the third insulating layer1222, the extrinsic emitter structure1220A and the second insulating layer1218to stop on the extrinsic base structure1216A.

Referring now toFIG. 23, therein is shown a HBT2300in an intermediate stage of manufacture in accordance with a further embodiment of the present invention. The HBT2300includes a semiconductor substrate2302, such as a lightly doped semiconductor substrate of the first conductivity type, for example, a p−doped semiconductor substrate. A first insulating layer2304, such as an oxide layer, is formed over the semiconductor substrate2302. A second insulating layer2306, such as a nitride layer, is formed over the first insulating layer2304. The first insulating layer2304and the second insulating layer2306are then processed using a collector well mask to expose a portion of the semiconductor substrate2302. The semiconductor substrate2302is then etched to form a first trench2310and a second trench2311on either side of an intrinsic collector structure2308. The intrinsic collector structure2308is the second conductivity type, which is formed, for example, by implanting a dopant in the intrinsic collector structure2308. The dopant then is driven into the intrinsic collector structure2308. A third insulating layer2312, such as a thin TEOS layer, is formed in the first trench2310and the second trench2311. A fourth insulating layer2314, such as a nitride layer, is formed over the third insulating layer2312.

Referring now toFIG. 24, therein is shown the structure ofFIG. 23after formation of a fifth insulating layer2400, such as a TEOS layer. The fifth insulating layer2400is formed by filling the first trench2310and the second trench2311with a high-density plasma (HDP) oxide or TEOS layer. The fifth insulating layer2400then undergoes a chemical-mechanical polish (CMP) and then is recessed deep into the first trench2310and the second trench2311by etching.

Referring now toFIG. 25, therein is shown the structure ofFIG. 24after formation of a collector window2500and an emitter window2501. The collector window2500and the emitter window2501are formed by providing a photoresist layer2502over a portion of the fourth insulating layer2314. The photoresist layer2502is masked and processed to form the collector window2500and the emitter window2501. The fourth insulating layer2314is removed, such as by etching, in the area of the fourth insulating layer2314unmasked by the photoresist layer2502. Preferably, the processing includes an anisotropic etch and then an isotropic etch to define the collector window2500and the emitter window2501.

Referring now toFIG. 26, therein is shown the structure ofFIG. 25after filling of the collector window2500and the emitter window2501with an insulating material2600, such as the HDP oxide or the TEOS. The photoresist layer2502as shown inFIG. 25is stripped. The collector window2500and the emitter window2501shown inFIG. 25are filled with the insulating material2600. The insulating material2600then undergoes a CMP process and the second insulating layer2306and the third insulating layer2312are removed, such as by etching.

It will be appreciated by one who is skilled in the art that the processing steps shown and described inFIGS. 23 through 26can be performed at the very beginning of the manufacturing line. The remainder of the HBT2300then can be formed as part of a complementary metal oxide semiconductor (CMOS) process or a bipolar complimentary metal oxide semiconductor (BiCMOS) process.

Referring now toFIG. 27, therein is shown the structure ofFIG. 26after formation of a base stack2700. The base stack2700includes an extrinsic base structure2702. The extrinsic base structure2702is formed, for example, by depositing a layer of polysilicon that is implanted to form the extrinsic base structure2702that is a heavily doped polysilicon material of the first conductivity type, such as a p+doped polysilicon.

A first silicide layer2704, such as a tungsten silicide layer, is formed over the extrinsic base structure2702, for example, by depositing a layer of silicide over the layer of polysilicon forming the extrinsic base structure2702.

A first insulating structure2706, such as an oxide structure, for example, a TEOS structure, is formed over the first silicide layer2704, for example, by depositing an insulating layer over the silicide layer. A second insulating structure2708, such as a nitride structure, is formed over the first insulating structure2706, for example, by depositing an insulating material over the insulating layer forming the first insulating structure2706.

The base stack2700is formed by depositing the various layers just described and processing them, for example, by exposing a base poly mask and then etching the various layers to form the base stack2700. Thus, the base stack2700includes an extrinsic base structure2702, a first silicide layer2704on top of the extrinsic base structure2702, a first insulating structure2706on top of the first silicide layer2704, and a second insulating structure2708over the first insulating structure2706.

Referring now toFIG. 28, therein is shown the structure ofFIG. 27after formation of an insulating spacer2800, such as a nitride spacer, around the base stack. The insulating spacer2800is formed by depositing an insulating layer over the base stack2700. The insulating layer is then processed to form the insulating spacer2800using conventional semiconductor manufacturing techniques.

Referring now toFIG. 29, therein is shown the structure ofFIG. 28after formation of an intrinsic base window2900. The intrinsic base window2900is formed by providing a photoresist layer2902. The photoresist layer2902is masked and processed to define a space over the intrinsic base window2900. The insulating material2600in the intrinsic base window2900is then etched to stop on the fourth insulating layer2314and on the fifth insulating layer2400at the bottom of the intrinsic base window2900. An anisotropic etch, such as a wet etch, for example, a HF/BOE is performed to etch the sidewall of the intrinsic base window2900to form an undercut region2904adjacent the intrinsic collector structure2308. The undercut region2904extends beneath a portion of the base stack2700.

Referring now toFIG. 30, therein is shown the structure ofFIG. 29after formation of an intrinsic base structure3000. The intrinsic base structure3000is formed by selectively forming a compound semiconductive material on the sidewall of the intrinsic collector structure2308in the undercut region2904shown inFIG. 29of the intrinsic base window2900. Preferably, the intrinsic base structure3000comprises at least one of silicon-germanium (Si/Ge), silicon-germanium-carbon (Si/Ge/C), and a combination thereof. The intrinsic base structure3000also preferably is doped in situ to form a lightly doped material of the first conductivity type, such as a p−doped compound semiconductive material. Formation of the intrinsic base structure3000partially fills the intrinsic base window2900to form an emitter window3002.

Referring now toFIG. 31, therein is shown the structure ofFIG. 30after formation of an extrinsic collector window3100. The extrinsic collector window3100is formed by depositing a second photoresist layer3102. The second photoresist layer3102is then masked and processed to form the extrinsic collector window3100. The processing includes performing an anisotropic etch of the insulating material2600shown inFIG. 30followed by a short isotropic etch, such as a HF/BOE dip, to expose the lateral side of the intrinsic collector structure2308.

Referring now toFIG. 32, therein is shown the structure ofFIG. 31after formation of an extrinsic collector structure3200and an emitter structure3202. The extrinsic collector structure3200and the emitter structure3202are formed by removing the second photoresist layer3102shown inFIG. 31. The extrinsic collector structure3200, such as a heavily doped semiconductive material of the second conductivity type, is formed in the extrinsic collector window3100shown inFIG. 31. The emitter structure3202is formed in the emitter window3002shown inFIG. 30. The semiconductive material can be either selectively grown epitaxial silicon that is doped in situ, such as an n+epitaxial silicon, or deposited polysilicon that is doped in situ, such as an n+doped polysilicon. The semiconductive material is then etched back to recess it partially from the surface of the first insulating layer2304. A RTA process may be performed if necessary to drive the dopant into the extrinsic collector structure3200and the emitter structure3202to obtain the desired dopant profile.

Referring now toFIG. 33, therein is shown an enlarged cross-sectional view3300of the relative position of the extrinsic collector structure3200, the intrinsic collector structure2308, the intrinsic base structure3000, and the emitter structure3202of the structure ofFIG. 32. The extrinsic collector structure3200has a first interface3300with the intrinsic collector structure2308. Adjacent the opposite side of the intrinsic collector structure2308is the intrinsic base structure3000. The intrinsic base structure3000has a second interface3302with the emitter structure3202.

Referring now toFIG. 34, therein is shown the structure ofFIG. 32after formation of a collector contact3400, a base contact3402, and an emitter contact3406through an ILD layer3408. A second silicide layer3410is formed over the extrinsic collector structure3200. A third silicide layer3412is formed over the emitter structure3202.

The ILD layer3408is formed over the second silicide layer3410, the third silicide layer3412, and the base stack2700. The collector contact3400is formed through the ILD layer3408in contact with the second silicide layer3410over the extrinsic collector structure3200. The base contact3402is formed through the ILD layer3408, through the second insulating structure2708, and through the first insulating structure2706in contact with the first silicide layer2704over the extrinsic base structure2702. The emitter contact3410is formed through the ILD layer3408in contact with the third silicide layer3412over the emitter structure3202.

Referring now toFIG. 35, therein is shown a flow chart of a method3500of manufacturing a HBT in accordance with the present invention. The method3500includes a step3502of providing a substrate; a step3504of forming an intrinsic collector structure on the substrate; a step3506of forming an extrinsic base structure partially overlapping the intrinsic collector structure; a step3508of forming an intrinsic base structure adjacent the intrinsic collector structure and under the extrinsic base structure; a step3510of forming an emitter structure adjacent the intrinsic base structure; a step3512of forming an extrinsic collector structure adjacent the intrinsic collector structure; a step3514of forming an interlevel dielectric layer; and a step3516of forming a plurality of contacts through the interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

Thus, it has been discovered that the method and apparatus of the present invention furnish important and heretofore unavailable solutions, capabilities, and functional advantages for manufacturing heterojunction bipolar transistors. The resulting process and configurations are straightforward, economical, uncomplicated, highly versatile, and effective, use conventional technologies, and are thus readily suited for manufacturing devices fully compatible with conventional manufacturing processes and technologies.