Memory layout for preventing reference layer from breaks

A memory comprising substrates is provided. Each substrate comprises a through-hole area at center; a first contact area at a side of the through-hole area; and a second contact area at another side of the through-hole area. The substrate uses its first or second contact area to mutually electrically connects to the first or second contact area of the another substrate through the through-hole area. After the pins of the memory having at least PAR pin included are electrically connects to the first and second contact areas of the substrate, all the substrates obtain mutual connections across layers through signal lines with the guidance of the through-hole areas. Thus, on fabricating the memory, reference layer is effectively prevented from breaks with good power distribution and sufficient wiring space achieved while good signal integrity is further maintained.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a memory, more particularly, to effectively preventing reference layer from breaks on fabricating the memory, where good power distribution and sufficient wiring space are obtained with good signal integrity further maintained.

DESCRIPTION OF THE RELATED ART

In general, a conventional memory has its pins obtain separate electrical connections according to requirements. Then, contacts obtain mutual electrical connections with signal lines. Thus, the setting of the memory is completed.

Conventional wiring for the memory provides through-holes on places of an entire substrate. The pins directly electrically connect to the contacts through the through-holes with the signal lines. As a result, the circuit layout is relatively cramped in space. In addition, power distribution is sometimes so poor that a reference layer may be broken on wiring. The reference layer of the memory may lose its signal integrity.

Hence, the prior art does not fulfill all users' expectations on actual use.

SUMMARY OF THE INVENTION

The main purpose of the present invention is to, after the pins of a memory device are electrically connected to a first and a second contact area of a substrate, separately mutually connect the first or the second contact areas of the other substrates in the same stack across layers through through-hole areas with corresponding signal lines. On fabricating the memory device, a reference layer is effectively prevented from breaks; good power distribution and sufficient wiring space are obtained with good signal integrity further maintained.

To achieve the above purpose, the present invention is a memory device having a layout preventing a reference layer from breaks comprising a plurality of substrates, where each one of the substrates comprises a through-hole area, a first contact area and a second contact area. The through-hole area is set at a center of one of the substrates for connection. The first contact area is set at a side of the through-hole area on the one of the substrates for connection. The first contact area connects to pins of the memory device through signal lines. The second contact area is set at another side of the through-hole area on the one of the substrates for connection. The second contact area connects to pins of the memory device through signal lines and at least a command/address parity (PAR) pin is included in the pins of the memory device to be connected and one of the substrates uses its first or second contact area to be mutually electrically connected to the first or second contact area of another one of the substrates. Accordingly, a novel memory device having a layout preventing reference layer from breaks is obtained.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Please refer toFIG. 1toFIG. 2, which are a view showing a preferred embodiment according to the present invention and a view showing a state-of-use of the preferred embodiment respectively. As shown in the figures, the present invention is a memory device having a layout preventing a reference layer from breaks comprising a plurality of substrates1. Each one of the substrates1comprises a through-hole area2, a first contact area3, and a second contact area4.

The substrates1are circuit boards and the substrates1are arranged in a vertically corresponding or stacking way.

The through-hole area2is set at a center of the substrate1for connection.

The first contact area3is set on the substrate1and located at a side of the through-hole area2for connection. The first contact area3connects to pins of the memory device through signal lines (not shown in the figures).

The second contact area4is set on the substrate1and located at another side of the through-hole area2for connection. The second contact area4connects to pins of the memory device through signal lines (not shown in the figures). At least a command/address parity (PAR) pin is included in the pins of the memory device. The substrate1uses its first or second contact area3,4to be mutually electrically connected with the first or the second contact area3,4of another one of the substrates1through the through-hole area2.

After the pins of the memory electrically connect to the first and the second contact areas3,4of one substrate1, signal lines5corresponding to the first and the second contact areas3,4electrically connect to the required first or second contact area3,4of another one of the substrates1across a reference layer though the guidance of the through-hole area2(not shown in the figures). Thus, on fabricating the memory device, a reference layer is effectively prevented from breaks with good power distribution and sufficient wiring space achieved while good signal integrity is further maintained.

The through-hole area2comprises a first through-hole row21, a second through-hole row22at a side of the first through-hole row21in one direction, and a third through-hole row23at a side of the second through-hole row22in the direction. The first through-hole row21comprises eight instances of first through-hole211; the second through-hole row22comprises nine instances of second through-hole221; the third through-hole row23comprises eight instances of third through-hole231. A separating zone24is set between every neighboring two rows in the first through-hole row21, the second through-hole row22, and the third through-hole row23. Each one of the first, the second, and the third through-holes211,221,231has an insulating zone212,222,232surrounding an outside edge and a power-connecting zone (not shown in the figures) is set between the first, the second, and the third through-holes211,221,231.

In a state-of-use, the first contact area3comprises a first contact row31, a second contact row32at a side of the first contact row31in one direction, and a third contact row33at a side of the second contact row32in the direction and each one of the first contact row31, the second contact row32, and the third contact row33comprises nine instances of first contact311, second contact321, and third contact331, respectively.

In a state-of-use, the second contact area4comprises a fourth contact row41, a fifth contact row42at a side of the fourth contact row41in one direction, and a sixth contact row43at a side of the fifth contact row42in the direction and each one of the fourth contact row41, the fifth contact row42, and the sixth contact row43comprises nine instances of fourth contact411, fifth contact421, and sixth contact431, respectively.

While the memory device is electrically connected with the first contact area3and the second contact area4of one of the substrates1, a state-of-use is described as follows:

On connecting the memory device, a VDD pin of the memory device is connected to the first contact311of the first contact row31in the first contact area3. Address A13pin of the memory device is connected to the second contact321of the second contact row32in the first contact area3. Address A17pin of the memory device is connected to the third contact331of the third contact row33in the first contact area3. A PAR pin of the memory device is connected to the fourth contact411of the fourth contact row41in the second contact area4. Address A11pin of the memory device is connected to the fifth contact421of the fifth contact row42in the second contact area4and a VSS pin of the memory device is connected to the sixth contact431of the sixth contact row43in the second contact area4.

As is described, the through-hole area2is set between the first contact area3and the second contact area4. Hence, when the first contact area3and the second contact area4of the substrate1are electrically connected to the another substrate1(not shown in the figures), the signal lines5are separately wired and guided to pass through two surfaces of the substrate1with the first, the second, and the third through-holes211,221,231of the first, the second and the third through-hole rows21,22,23in the through-hole area2. Then, after the first, the second, and the third contacts311,321,331in the first contact area3and the fourth, the fifth, and the sixth contacts411,421,431in the second contact area4are passed through the first, the second and the third through-holes211,221,231as required, the signal lines5are electrically connected across a reference layer to the first contact area3and the second contact area4of the another substrate1. Therein, a power line or grounding line is connected with the power-connecting zone (not shown in the figures) according to requirements. In a state-of-use, the signal lines5are of the same length, so that the signal lines5are wired in a clean and neat way with the reference layer prevented from breaks and, owing to the same lengths, good power distribution and sufficient wiring space are obtained.

Furthermore, the first, the second, and the third through-hole rows21,22,23are separated by the separating zones24for avoiding interference between the signal lines5and the signal lines5use the insulating zones212,222,232to avoid shortcuts of contacting the power-connecting zone (not shown in the figures) on passing through the first, the second and the third through-holes211,221,231.

To sum up, the present invention is a memory device having a layout preventing a reference layer from breaks where, after the pins of a memory device are electrically connected to a first and a second contact areas of a substrate, the first or the second contact areas of the other substrates in the same stack can separately mutually connect across required substrate layers through through-hole areas with corresponding signal lines On fabricating the memory device, a reference layer is effectively prevented from breaks to obtain good power distribution and sufficient wiring space with good signal integrity further maintained.