Liquid crystal display and display panel thereof

An LCD and a display panel thereof are provided. A common voltage generation circuit of the display panel is electrically connected to at least one pixel in a non-active pixels region. According to the display voltage at a drain of a TFT in the pixel, an average of display voltages of positive and negative polarities is obtained in two frame times. The average value is regarded as a common voltage supplied to every pixel in an active pixel region in the display panel. Thereby, the problem of a drift of a feed-through voltage (ΔVD) of a scan voltage due to an RC delay of a parasitic-capacitance and a parasitic-resistance on the scan line can be avoided. Further, the gray-level accuracy of every pixel in the active pixel region can be improved, and the flicker-noise of the display-panel can be reduced, thus significantly promoting the display quality of the LCD.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 95142533, filed Nov. 17, 2006. All disclosure of the Taiwan application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display and a display panel thereof, and more particularly to a liquid crystal display and a display panel thereof capable of adjusting a common voltage automatically.

2. Description of Related Art

In recent years, liquid crystal displays (LCDS) have been widely adopted and have replaced the conventional cathode ray tube (CRT) displays. Currently, the LCDs have become one of the mainstream products in the market of displays. With the progress of the semiconductor technology, LCD panels have the advantages of low power consumption, slimness and compactness, high resolution, high color saturation, long life time, and so on. Therefore, the LCD panels have been extensively applied in electronic products closely related to daily life, including liquid crystal screens of computers and LCD TVs.

FIG. 1illustrates a pixel configuration100of a conventional thin film transistor liquid crystal display (TFT-LCD). Please refer toFIG. 1. The pixel configuration100includes a TFT101, a liquid crystal capacitance CLC, a storage capacitance Cs, a common electrode CE, and a parasitic capacitance Cgd. The electrical connection of the pixel configuration100disclosed inFIG. 1clearly indicates a Cs-on-common design.FIG. 2illustrates another pixel configuration200of the conventional TFT-LCD. Please refer toFIGS. 1 and 2together. The main difference between the pixel configurations100and200lies in that the pixel configuration200is of a Cs-on-gate design.

When the voltage level of a scan voltage (VG) outputted by a gate driver (not shown) rapidly declines from a high voltage level (VGH) to a low voltage level (VGL) and the TFT101is then switched off, a coupling effect is induced by the parasitic capacitance Cgdno matter which pixel configuration is adopted. Thereby, the voltage in a drain d of the TFT101is simultaneously dropped by a voltage level (ΔVD), which can be represented by the following equation 1.

In equation 1, ΔVGPis obtained by subtracting the low voltage level (VGL) from the high voltage level (VGH) i.e. ΔVGP=VGH−VGL. The varying voltage level (ΔVD) is called a feed-through voltage of the scan voltage, and the value of said feed-through voltage is not a constant.

Due to physical characteristics of liquid crystal molecules, however, the value of the liquid crystal capacitance CLCvaries according to different gray-level voltages. Hence, every pixels with different gray levels has different feed-through voltages (ΔVD) of the scan voltage. In addition, it is well known that each of the scan lines in the display panel (not shown) includes a parasitic capacitance and a parasitic resistance on a scan line. Accordingly, said ΔVGPis affected by the parasitic capacitance and the parasitic resistance on the scan line, thus resulting in a so-called RC delay. Thereby, the farther the distance between an input terminal of the scan voltage and its corresponding pixel is, the smaller the value of ΔVGPbecomes. Besides, due to various RC delays on each of the scan lines in the display panel, the feed-through voltages (ΔVD) of pixels in the same column in the display panel may be different.

As described above, both factors resulting in different feed-through voltages (ΔVD) of the scan voltages lead to an increase in flicker noises of the display panel, and thereby images displayed by the TFT-LCD flicker. To resolve said problems, relevant solutions disclosed in the related art have been correspondingly developed, including:

1. Adjusting the common voltage Vcom supplied to the pixels in the display panel based on the value of the feed-through voltage (ΔVD) of the scan voltage.

2. Adopting a technology of driving a three-level or a four-level scan voltage.

Said solution1is adapted to the pixel configuration100(Cs on common) and to the pixel configuration200(Cs on gate), which is implemented by observing and adjusting the common voltage Vcom supplied to the pixels in the display panel through optical measurements, such that the flicker noises in the middle of the display panel can be minimized. Then, after the adjusted common voltage is set, a corrected gamma voltage outside a source driver is fine tuned to eliminate the shift of the feed-through voltage (ΔVD) Of the scan voltage. Said shift is caused by variation in the value of the liquid crystal capacitance CLCdue to different gray-level voltages. It should be mentioned that the problem of the flicker noises at both sides of the display panel is not completely overcome even though said solution1minimizes the flicker noises in the middle of the display panel.

FIG. 3is a diagram of a simulation waveform depicting said solution1. Please refer toFIGS. 1˜3together. As shown inFIG. 3, the diagram of the simulation waveform includes a waveform of the scan voltage VG, of the data voltage Vs (the data voltage supplied by the source driver and received by the source s of the TFT101), of the display voltage VD(the display voltage of the drain d of the TFT101), and of the common voltage Vcom. Here, the coupling effect induced by said parasitic capacitance Cgdgenerates the feed-through voltage ΔVDof the scan voltage, which can be learned from the waveform of the display voltage VD.

In view of the foregoing, complicated manual measurement is required when the solution1is adopted to resolve the problem of the feed-through voltage (ΔVD) of the scan voltage, so as to obtain the best common voltage Vcomsupplied to the pixel in the display panel. Moreover, each display panel has different characteristics, and therefore said best common voltage Vcomand the fine-tuned corrected gamma voltage outside the source driver may not be applicable to all display panels.

Furthermore, said solution2can merely be used in the pixel configuration200(Cs on gate) disclosed hereinbefore.FIG. 4is a diagram of a simulation waveform depicting said solution2which adopts a technology of driving a three-level scan voltage. Please refer toFIGS. 2 and 4together. According to said solution2, as the scan voltage VGof the previous scan line Gm-1is set at a low voltage level VGL1(m-1), and the feed-through voltage ΔVDof the scan voltage VGof the scan line Gm occurs, the scan voltage of the previous scan line Gm-1at the low voltage level VGL1(m-1)is raised by a voltage level Vpto a low voltage level VGL2(m-1). Through said increase in the voltage level and the voltage coupling effects of the storage capacitance Csand of the parasitic capacitance Cgd, the shift of the feed-through voltage ΔVDof the scan voltage VGof the scan line Gmis compensated. Theoretically, the voltage level Vpdescribed in said solution2can be calculated through the following two equations:

However, if a technology of driving a multi-level e.g. a three- or a four-level scan voltage is intended to be developed according to said solution2, it is obvious that said development complicates the design of the gate driver. Besides, given that the voltage level Vpcannot be accurately calculated by the gate driver, the feed-through voltage ΔVDof the scan voltage VGof the scan line Gmmay be insufficiently or excessively compensated, which results in uncertainties in terms of design and measurement. Moreover, it is required for said solution2to be implemented in conjunction with the fine-tuned corrected gamma voltage outside the source driver so as to compensate the shift of the feed-through voltage of the scan voltage. The shift is caused by variation in the value of the liquid crystal capacitance CLCdue to different gray-level voltages.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides a display panel, in which a common voltage generation circuit is electrically connected to at least a pixel in a non-active pixel region, and a common voltage of the pixel corresponding to one column of pixels in the display panel is automatically adjusted in N frame time (N is a positive integer, e.g. 2). Thereby, the complicated process of conventional manual adjustment of the common voltage can be eliminated. Furthermore, the common voltage supplied is ensured to be at a best voltage level required by the column of the pixels in the display panel.

The present invention further provides a display to which the spirit of said display panel can be applied. Thereby, not only can the advantages of the display panel disclosed in the present invention be achieved, but the flicker noises of the display panel can be minimized, thus leading to an improvement of the display quality.

The display panel provided by the present invention includes a first pixel region, a second pixel region, and a common voltage generation circuit. The first pixel region includes a plurality of first pixels arranged in array. The second pixel region includes a plurality of second pixels disposed in the periphery of the first pixel region. The common voltage generation circuit is electrically connected to at least one second pixel corresponding to one column of pixels in the first pixel region. Here, the common voltage generation circuit supplies a common voltage to each of the first pixels in the first pixel region based on a display voltage of the second pixel, and the common voltage is an average of the display voltages of positive and negative polarities.

From another aspect, the present invention provides a display including a display panel and a gate driver. The display panel includes a first pixel region, a second pixel region, and a common voltage generation circuit. The first pixel region includes a plurality of first pixels arranged in array. The second pixel region includes a plurality of second pixels disposed in the periphery of the first pixel region. The common voltage generation circuit is electrically connected to at least one second pixel corresponding to one column of pixels in the first pixel region.

The gate driver electrically connected to the display panel includes a plurality of gate lines for sequentially outputting a scan voltage from each of the gate lines to a corresponding scan line of the first pixels and the second pixels based on timing. Here, the common voltage generation circuit supplies a common voltage to each of the first pixels in the first pixel region based on a display voltage of the second pixel, and the common voltage is an average of the display voltages of positive and negative polarities.

According to one embodiment of the present invention, the display further includes a source driver electrically connected to the display panel. The source driver includes a plurality of source lines for outputting the display voltage to a corresponding data line of the first pixels through the source lines based on image data. The display voltage corresponds to the first pixels.

According to one embodiment of the present invention, each of the first and the second pixels includes a transistor and a storage capacitance. A gate terminal of the transistor is electrically connected to a scan line, and a first drain/source terminal thereof is electrically connected to a data line. The storage capacitance includes a first terminal and a second terminal. The first terminal is electrically connected to a second drain/source terminal of the transistor, and the second terminal is adopted to receive the common voltage.

According to one embodiment of the present invention, each of the first and the second pixels includes a parasitic capacitance and a liquid crystal capacitance. The parasitic capacitance has a first and a second terminals. The first terminal is electrically connected to the scan line, and the second terminal is electrically connected to the second drain/source terminal of the transistor. The liquid crystal capacitance includes a first and a second terminals. The first terminal is electrically connected to the second drain/source terminal of the transistor, and the second terminal is adopted to receive the common voltage.

According to one embodiment of the present invention, the transistor includes a TFT.

According to one embodiment of the present invention, the common voltage generation circuit includes a first operational amplifier, a first switch, a second switch, a third switch, a fourth switch, a first capacitance, a second capacitance, a fifth switch, a second operational amplifier, a sixth switch, a third capacitance, and a third operational amplifier. The first operational amplifier includes a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal is electrically connected to the second drain/source terminal of the transistor, while the negative input terminal and the output terminal are electrically connected to each other. The first switch includes a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to the output terminal of the first operational amplifier.

The second switch includes a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to the first terminal of the first switch. The third switch includes a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to the first terminal of the second switch. The fourth switch includes a first terminal, a second terminal, and a control terminal. Here, the first terminal is electrically connected to the second terminal of the first switch, and the second terminal is connected to ground.

The first capacitance includes a first terminal and a second terminal. Here, the first terminal is electrically connected to the second terminal of the first switch, and the second terminal is electrically connected to the second terminal of the second switch. The second capacitance includes a first terminal and a second terminal. Here, the first terminal is electrically connected to the second terminal of the second switch, and the second terminal is electrically connected to the second terminal of the third switch. The fifth switch includes a first terminal, a second terminal, and a control terminal. Here, the first terminal is electrically connected to the second terminal of the third switch, and the second terminal is connected to ground.

The second operational amplifier includes a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal is electrically connected to the second terminal of the second switch, while the negative input terminal and the output terminal are electrically connected to each other. The sixth switch includes a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to the output terminal of the second operational amplifier. The third capacitance includes a first terminal and a second terminal. Here, the first terminal is electrically connected to the second terminal of the sixth switch, and the second terminal is connected to ground. The third operational amplifier includes a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal is electrically connected to the first terminal of the third capacitance, while the negative input terminal and the output terminal are electrically connected to each other, so as to output the common voltage to each of the first pixels in the first pixel region.

According to one embodiment of the present invention, the control terminals of the first, the second, the third, the fourth, the fifth, and the sixth switches determine an ON/OFF state of the switches based on a corresponding control signal.

According to one embodiment of the present invention, the first, the second, the third, the fourth, the fifth, and the sixth switches are switched off when the control signal is generated in a first phase. The first, the second, and the fifth switches are switched on and the third, the fourth, and the sixth switches are switched off when the control signal is generated in a second phase.

According to one embodiment of the present invention, the first, the second, the third, the fourth, the fifth, and the sixth switches are switched off when the control signal is generated in a third phase. The fourth switch is switched on and the first, the second, the third, the fifth, and the sixth switches are switched off when the control signal is generated in a fourth phase.

According to one embodiment of the present invention, the third and the fourth switches are switched on and the first, the second, the fifth, and the sixth switches are switched off when the control signal is generated in a fifth phase. The fourth and the sixth switches are switched on and the first, the second, the third, and the fifth switches are switched off when the control signal is generated in a sixth phase.

According to one embodiment of the present invention, the column of pixels is positioned in the middle of the first pixel region.

According to one embodiment of the present invention, the display panel includes an LCD panel, while the display includes an LCD.

In the display and the display panel thereof provided by the present invention, the common voltage generation circuit is electrically connected to at least one second pixel in the second pixel region i.e. the non-active pixel region in the display panel, and obtains an average of the voltages having positive and negative polarities in N frame time (N is a positive integer e.g. 2.) according to the display voltage of the drain of the TFT in the second pixel. Then, the average is utilized as the common voltage and provided to each of the first pixels in the first pixel region i.e. the active pixel region in the display panel. Thereby, the complicated process of conventional manual adjustment of the common voltage can be eliminated. Furthermore, the common voltage supplied is ensured to be at the best voltage level required by the column of the pixels in the display panel.

In addition, given that the common voltage generation circuit is electrically connected to more than two second pixels in the second pixel region i.e. the non-active pixel region, the problem of the drift of the feed-through voltage (ΔVD) caused by an RC delay of the parasitic capacitance and the parasitic resistance on the scan line can be avoided. Thereby, the gray-level accuracy of each of the first pixels in the first pixel region in the display panel can be significantly improved, and the flicker noises of the display panel can be reduced, thus promoting the display quality.

In order to make the aforementioned and other objectives, features and advantages of the present invention comprehensible, several embodiments accompanied with figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

FIG. 5is a block diagram depicting a display500according to one embodiment of the present invention. Please refer toFIG. 5. The display500e.g. an LCD includes a display panel501e.g. an LCD panel, a gate driver503, and a source driver505. In the present embodiment, the display panel501includes a first pixel region507, a second pixel region509, and a common voltage generation circuit511. The first pixel region507has a plurality of first pixels (not shown) arranged in an i*j array for displaying images. Here, i and j are positive integers. The second pixel region509has a plurality of second pixels509adisposed in the periphery of the first pixel region507.

The common voltage generation circuit511is electrically connected to one of the second pixels509ain the second pixel region509, and the second pixel509acorresponds to one column of the pixels in the first pixel region507. In addition, the common voltage generation circuit511provides a common voltage Vcomto each of the first pixels in the first pixel region507based on a display voltage (VD) of the drain of the TFT (not shown) in the second pixel509aelectrically connected to the common voltage generation circuit511. Here, the display voltage at a high voltage level VDHhas positive polarity, and the display voltage at a low voltage level VDLhas negative polarity. The common voltage Vcomis an average of the display voltages of positive and negative polarities. Namely, it can be expressed by the following equation.
Vcom=(VDH+VDL)/2  Equation (4)

In the second pixel region509, the amount of the second pixel509aelectrically connected to the common voltage generation circuit511is not limited in the present embodiment. However, it is required for said second pixel509ato be the one adjacent to the uppermost or the lowermost row in the first pixel region507. For example, if the display panel resolution of the present embodiment is i*j (e.g. 1024*768, i and j are positive integers), the second pixel509awhich is in the second pixel region509and is electrically connected to the common voltage generation circuit511is disposed in row0(in the second pixel region509adjacent to the first row of the pixels in the first pixel region507) or in row769(in the second pixel region509adjacent to the 768throw of the pixels in the first pixel region507). According to the present embodiment, the second pixel509acorresponding to the column of pixels in the first pixel region507is approximately positioned in the middle of the first pixel region507. Noted that those skilled in the art should know the first pixel region507is an active pixel region, while the second pixel region509is a dummy pixel region. Thus, it can be known that the gate driver503and the source driver505of the present embodiment respectively supply a scan voltage and a data voltage not only to each of the first pixels in the first pixel region507, but also to the row of pixels corresponding to the second pixel509a. However, since the gate driver503and the source driver505are not the technical features of the present invention, and the principle of driving the gate driver503and the source driver505is well known to those skilled in the art. Hence, for fear of raising confusion between the related art and the present invention, detailed descriptions are then omitted.

FIG. 6illustrates a pixel configuration of a second pixel509aaccording to the present embodiment.FIG. 7is a diagram of a common voltage generation circuit511according to the present embodiment. Please refer toFIGS. 5˜7together. The second pixel509adepicted inFIG. 6adopts a Cs-on-common pixel configuration. The common voltage Vcomsupplied to the first pixels and the second pixel509ais provided by the common voltage generation circuit511as is disclosed inFIG. 7.

First, please refer toFIG. 7. The common voltage generation circuit511of the present embodiment includes operational amplifiers701,703,705, switches SW1˜SW6, and capacitances C1˜C3. Through the electrical connection between the operational amplifiers701and703disclosed inFIG. 7, it can be deduced that said operational amplifiers are employed as unit gain buffers to increase a driving force of the received voltage. Thereby, capacitances C1, C2and a peck detector consisting of the operational amplifier705and the capacitance C3are driven, respectively. Besides, each of the switches SW1˜SW6has a control terminal which determines an ON/OFF state of the switches based on corresponding control signals CS1˜CS6.

FIG. 8is a timing diagram of controlling the control signals CS1˜CS6corresponding to the control switches SW1˜SW6in the common voltage generation circuit511according to the present embodiment. Please refer toFIGS. 5˜8together. It can be learned from the timing diagram inFIG. 8that the switches SW1˜SW6are switched on correspondingly when pulses of the control signals CS1˜CS6are high. Hence, the switches SW1˜SW6are switched off at timing t1, which means the common voltage generation circuit511is in initial status, and node voltages Va=Vb=Vc=0V. At timing t2during which the display voltage VDof the drain of the TFT in the second pixel509ais at the high voltage level (i.e. a high-pulsed display voltage VDH), the switches SW1, SW2, SW5are switched on while SW3, SW4, SW6are switched off. Here, the switches SW1and SW2receive a positive high-pulsed display voltage VDHthrough the operational amplifier701, and the node voltages Va=Vb=VDHwhile Vc=0V.

Then, at timing t3, the switches SW1˜SW6are switched off, and the node voltages Va, Vb, and Vcare in floating states. Thereby, the voltage differential between each group of two of the node voltages Va, Vb, and Vcremains consistent, and thus it can be deduced that the node voltages Va=Vb, and Va−Vc=VDH. Next, at timing t4, the switch SW4is switched on while the other switches SW1˜SW3, SW5, SW6are switched off. Accordingly, it can be derived from the law of conservation of electric charges that the node voltages Vband Vcare in floating states, and the node voltages Va=Vb=0V while Vc=−VDH.

Thereafter, at timing t5during which the display voltage VDof the drain of the TFT in the second pixel509ais at the low voltage level (i.e. a low-pulsed display voltage VDL), the switches SW3and SW4are switched on while SW1, SW2, SW5, SW6are switched off. Here, the node voltage Va=0V, and Vbis raised from 0V to [(VDH+VDL)/2]V in view of the principle of voltage division of the capacitances C1and C2. Besides, Vcis raised from the negative high-pulsed display voltage −VDHto the positive low-pulsed display voltage VDL. Finally, at timing t6, the switches SW4and SW6are switched on while the switches SW1˜3and SW5are switched off. Here, through the operational amplifier703, the node voltage Vbis supplied to the peak detector consisting of the operational amplifier705and the capacitance C3, so as to stabilize the voltage outputted to each of the first pixels in the first pixel region507. The outputted voltage is regarded as the common voltage Vcomrequired by each of the first pixels in the first pixel region507. Note that the values of the input capacitances of the operational amplifiers701and703ought to be as small as possible. And the values of the capacitances C1and C2must be identical and should be as large as possible. Thereby, the errors in the calculation of said common voltage Vcomcan be eliminated.

From the timing diagram ofFIG. 8, the common voltage generation circuit511of the present embodiment requires two frame times for calculating the outputted common voltage Vcom. It can also be learned from the timing of a scan signal GS. Here, in the first frame time, the common voltage generation circuit511memorizes the high-pulsed display voltage VDH, while the common voltage generation circuit511memorizes the low-pulsed display voltage VDLin the second frame time. Thereby, according to the order of controlling the switches SW1˜SW6through the control signals CS, the node voltage Vbcan be obtained and supplied to each of the first pixels in the first pixel region507as the common voltage Vcomrequired by each of the first pixels in the first pixel region507.

From the operation of the common voltage generation circuit511disclosed in the present embodiment, it can be learned that the average of two voltage signals inputted at different frame times i.e. the average of the display voltages at the high voltage level VDHand at the low voltage level VDLis obtained. Therefore, the common voltage generation circuit511of the present embodiment can be applied to other technical fields in the event of obtaining the average voltage inputted at different frame times.

In the present embodiment, the second pixel509a(the dummy pixel region) is adopted by the common voltage generation circuit511to calculate the common voltage Vcomrequired by the column of pixels in the display panel501. Accordingly, the gate driver503supplies the scan voltage to enable the row of pixels corresponding to the second pixel509a, and the data voltage supplied by the source driver505must be driven in the manner as driving the display panel501i.e. a normally white manner or a normally black manner. Thereby, the correct data voltage (white signal or black signal) is correspondingly supplied to the column of pixels, and the gray level of the supplied data voltage must be consistent.

For example, as the display panel501is driven in the normally white manner, the data voltage which is supplied to the column of the pixels corresponding to the second pixel509aby the source driver505must be a white signal. On the contrary, as the display panel501is driven in the normally black manner, the data voltage which is supplied to the column of the pixels corresponding to the second pixel509aby the source driver505must be a black signal. Thus, it should be noted that after the common voltage generation circuit511of the present invention is operated, the state of the scan voltage outputted by the gate driver503and that of the data voltage outputted by the source driver505ought to be taken into consideration even though the row of pixels corresponding to the second pixel509ais not used at the time the display panel501is driven.

More noticeably, since the second pixel509ais adopted by the common voltage generation circuit511to calculate the common voltage Vcomrequired by the column of pixels in the display panel501, the column of pixels corresponding to the second pixel509ais capable of resolving the problem of the feed-through voltage (ΔVD) of the scan voltage in the display panel, and further eliminating the flicker noises of the display panel501thoroughly. As disclosed in the related art, said problem of the feed-through voltage (ΔVD) of the scan voltage results from the RC delay induced by the parasitic capacitance and the parasitic resistance on the scan line.

Furthermore, in the present embodiment, the RC delay on the scan line poses less impact on the first pixels adjacent to the column of pixels corresponding to the second pixel509aand is disposed in the display panel501. However, the first pixels far from the middle of the display panel501are still likely to be affected by the RC delay on the scan line. Hence, the flicker noises may occur in the first pixels at two sides of the display panel501.

Despite the flicker noises occurring in the first pixels at two sides of the display panel501, the flicker noises occurring in the first pixels adjacent to the display panel501or corresponding to the second pixel509acan be reduced. Moreover, according to the present embodiment, the common voltage Vcomsupplied to each of the first pixels in the display panel501is automatically generated by the common voltage generation circuit511rather than supplied outside. Thereby, the voltage across the liquid crystal capacitance CLCand the storage capacitance CSremains consistent, and the gray level accuracy of each of the first pixels in the first pixel region507is further improved. Accordingly, the complicated process of conventional manual adjustment of the common voltage Vcomcan be eliminated, and the best common voltage Vcomrequired by the first pixels in the display panel501can be obtained.

Said embodiment has taken one second pixel509ain the second pixel region509electrically connected to the common voltage generation circuit511for an example. To further reduce the flicker noises occurring in the first pixels at two sides of the display panel501, another embodiment taking a plurality of the second pixels509ain the second pixel region509electrically connected to the common voltage generation circuit511for an example is provided hereinafter.

FIG. 9is a block diagram depicting a display900according to another embodiment of the present invention. Please refer toFIGS. 5 and 9together. The difference between the display900ofFIG. 9and the display500lies in that the common voltage generation circuit511is electrically connected to four of the second pixels509ain the second pixel region509. Here, two of the second pixels509aare disposed adjacent to the uppermost row of the pixels in the first pixel region507, and the other two of the second pixels509aare disposed adjacent to the lowermost row of the pixels in the first pixel region507. The disposition represented inFIG. 9but not limited in the present embodiment can be adjusted according to the design of the display panel501.

In the present embodiment, since the principle of operating the display panel501and the common voltage generation circuit511is similar to that of operating the display500described in the former embodiment, further descriptions are omitted. Note that the common voltage generation circuit511of the present embodiment is electrically connected to four of the second pixels509ain the second pixel region509. Hence, it can be anticipated that the flicker noises of the display panel501are significantly reduced, and the display quality of the display900is improved.

FIG. 10is a block diagram depicting a display1000according to another embodiment of the present invention. Please refer toFIG. 10. In the display1000ofFIG. 10, the common voltage generation circuit511is electrically connected to ten of the second pixels509ain the second pixel region509. Here, five of the second pixels509aare disposed adjacent to the uppermost row of the pixels in the first pixel region507, and the other five of the second pixels509aare disposed adjacent to the lowermost row of the pixels in the first pixel region507. The disposition represented inFIG. 10but not limited in the present embodiment can be adjusted according to the design of the display panel501.

In the present embodiment, since the principle of operating the display panel501and the common voltage generation circuit511is similar to that of operating the display500described in the former embodiment, further descriptions are omitted. Note that the common voltage generation circuit511of the present embodiment is electrically connected to ten of the second pixels509ain the second pixel region509. Hence, it can be anticipated that the flicker noises of the display panel501are further reduced to a great extent, and the display quality of the display1000is better than that of the displays500and900.

According to said embodiment, it can be deduced that when the common voltage generation circuit511is electrically connected to more of the second pixels509ain the second pixel region509, the problem of the drift of the feed-through voltage (ΔVD) caused by the RC delay of the parasitic-capacitance and the parasitic-resistance on the scan line can be avoided when said embodiment is applied to an actual display panel. Further, the flicker noises of the display panel501can be reduced, thus significantly promoting the display quality.

In addition to the above, three embodiments are provided hereinafter based on the spirit of said embodiments of the present invention. According to the following embodiments, a photo mask is adopted to divide a color filter of the display panel into a plurality of areas, and the common voltage generation circuit511described above is employed to supply the common voltage required by the pixels in each of the areas. Likewise, the three embodiments also have advantages similar to those of the former embodiments.

FIG. 11is a block diagram depicting a display1100according to another embodiment of the present invention. Please refer toFIG. 11. The display1100adopts a photo mask to divide a color filter (not shown) into three areas. That is, the display panel501is divided into three areas: area A, area B, and area C. Here, the areas A, B, and C have corresponding second pixel509arespectively and a common voltage Vcomprovided by the common voltage generation circuit511. In the present embodiment, since the principle of operating the display1100is similar to that of operating the display500described in the former embodiments, further descriptions are omitted. Thereby, the problem of the drift of the feed-through voltage (ΔVD) caused by the RC delay on the scan line of the areas A, B, and C can be avoided when said embodiment is applied to an actual display panel. Further, the flicker noises of the display panel501can be reduced, thus significantly promoting the display quality of the display1100.

FIGS. 12 and 13are block diagrams depicting displays1200and1300according to another embodiment of the present invention. Please refer toFIGS. 11˜13together. The displays1200and1300are similar to the display1100. The difference lies in that the display1200adopts a photo mask to divide a color filter into five areas, while the display1300divides the color filter into ten areas. Thus, the display panel of the display1200is divided into five areas A˜E, and that of the display1300is divided into ten areas A˜J. Based on the above, it can be deduced that when the color filter is divided into numerous areas, the display panel thereof is also divided into a great number of areas. And the common voltage generation circuit511described above is employed to supply the common voltage required in each of the areas. Thereby, the flicker noises of the display panel can be completely avoided, thus promoting the display quality.

In summary, the present invention provides a display and a display panel thereof. According to the spirit of the present invention, the present invention has the following advantages:

1. Through the electrical connection of the common voltage generation circuit to at least a second pixel in the second pixel region, and through the automatic adjustment of the common voltage of the pixel corresponding to one column of pixels in the display panel in N frame time (N is a positive integer, e.g. 2), the complicated process of conventional manual adjustment of the common voltage can be eliminated. Furthermore, the common voltage provided by the common voltage generation circuit is ensured to be at the best voltage level required by the column of the pixels in the display panel.

2. Through the photo mask, the color filter is divided into a plurality of areas, and so is the display panel. Thereby, the problem of the drift of the feed-through voltage (ΔVD) of the scan voltage due to the RC delay on the scan line can be avoided. Further, the flicker noises of the display panel can be reduced, thus significantly promoting the display quality.

Although the present invention has been disclosed above by the embodiments, they are not intended to limit the present invention. Anybody skilled in the art can make some modifications and alteration without departing from the spirit and scope of the present invention. Therefore, the protecting range of the present invention falls in the appended claims.