Reducing power consumption by preventing memory image destaging to a nonvolatile memory device

Power consumption can be reduced by preventing a memory image from being destaged to a nonvolatile memory device. For example, a system can determine, subsequent to a computing device being in a first power mode and having a memory image stored in a first nonvolatile memory device that performs a caching function, that the computing device is in a second power mode that is a higher power mode than the first power mode. The system can, in response to determining that the computing device is in the second power mode, generate a first command to store the memory image in a volatile memory device and prevent the memory image from being stored in a second nonvolatile memory device. The system can, in response to generating the first command, store the memory image in the volatile memory device.

TECHNICAL FIELD

The present disclosure relates generally to power consumption of user devices. More specifically, but not by way of limitation, this disclosure relates to reducing power consumption by preventing memory image destaging to a nonvolatile memory device.

BACKGROUND

User devices, such as mobile phones, laptop computers, and desktop computer, often include a dynamic random access memory (DRAM) and a solid-state drive (SSD) for storing data. Data in the DRAM can be destaged to the SSD, for example, when the user device enters a power-save mode. An SSD is organized into blocks, with each block including a number of pages made up of a row of cells. SSDs read and write data as pages, but erase data at the block level. Once a block is erased, new data can be written to the cells of the block. A block can be written and erased a predefined amount of time before the SSD fails. For example, an SSD may be limited to writing and erasing a block 1000 times.

DETAILED DESCRIPTION

User devices regularly switch between power modes. For example, a user device may operate in a higher power mode when the user device is interacted with to perform operations and may operate at a lower power mode when the user device is turned off in an idle state. Typically, when a user device enters the lower power mode, a memory image of data for the user device is stored in a solid-state drive (SSD) and power is turned off to the memory device, such as a dynamic random access memory (DRAM) device. When power resumes, the memory image is read from the SSD into the memory device and operations continue from the previous state. Each time the memory image is stored to the SSD, a part of the erase cycles for the SSD are consumed, which are typically limited to fewer than one-thousand erase cycles. An SSD may include a caching layer of a storage class memory (SCM) that is faster than the underlying SSD, nonvolatile, and capable of virtually unlimited erase cycles.

A write to the SSD can first be stored in the SCM cache for fast response time and to help mitigate write amplification. But, the write is eventually destaged to the SSD to free up space for additional writes. The cycle of storing a memory image to the SSD and restoring the memory image to the DRAM can result in unnecessary writes to the SSD. For a user device, it may be beneficial to enter the lower power mode each time the screen is turned off and to resume the higher power mode when the screen is turned on. Taking into account the frequency of a user turning on and off the screen of the user device and a size of the memory device, the number of cycles of storing and restoring the memory image increases quickly. For example, if the user turns off and on the screen sixty times in one day and the DRAM is eight GB, there are four-hundred eighty GB of store and restore data in one day. As a result, a two-hundred fifty GB SSD may be rewritten at least twice a day, which may be increased due to write amplification. The erase cycles may additionally consumed within one year by storing and restoring the memory image, which does not take into account other processes. To mitigate erase cycle usage, user devices may wait a predetermined time after the screen is turned off to enter the lower power mode to skip saving the memory image for situations in which there is a short delay between the turning off and turning on of the screen.

Some examples of the present disclosure can overcome one or more of the abovementioned problems by providing a system that can store the memory image in a first nonvolatile memory device and prevent the memory image from being destaged to a second nonvolatile memory device during a lower power mode. The first nonvolatile memory device can perform a caching function and may be an SCM device. After being in the lower power mode with the memory image stored in the first nonvolatile memory device, the system can enter the higher power mode. A command can be generated to store the memory image in a volatile memory device, such as a DRAM, and to prevent the memory image from being stored in the second nonvolatile memory device. As a result, each time the system enters the lower power mode, the memory image can be moved to the first nonvolatile memory device and then restored to the volatile memory device when the system enters the higher power mode. Thus, write amplification and erase-cycle usage of the second nonvolatile memory device can be reduced. In addition, power consumption can be reduced since the system can enter the lower power mode each time a screen of the system is turned off, and not only after the screen remains off for a predetermined length of time.

As an example, a screen of a mobile phone can be turned off, so the mobile phone can be considered to be in a power-save mode. The mobile device can include a DRAM device as a volatile memory device and a storage device that includes two nonvolatile memory devices: an SCM device that performs a caching function and an SSD. To enter the power-save mode, a command can be generated to store a memory image in the SCM device. The command can also prevent the memory image from being destaged to the SSD. The screen of the mobile phone can then be turned on, and the mobile phone can enter a full-power mode. Another command can be generated to restore the memory image to the DRAM. The other command can also prevent the memory image from being stored in the SSD. As a result of bypassing the SSD, storing and restoring cycles for the memory image can reduce write amplification and erase-cycle usage of the SSD and also power consumption for the mobile phone.

FIG.1is a block diagram of an example of a system for implementing preventing memory image destaging to a nonvolatile memory device according to some aspects of the present disclosure. The system can include a user device100that can include a storage device110and a volatile memory device130in communication with a processor140. Examples of the user device100can include a mobile phone, a laptop computer, a tablet, a server, or another user device. The volatile memory device130may be a DRAM device. The storage device110can include at least two nonvolatile memory devices120a-b. One of the nonvolatile memory devices, such as the nonvolatile memory device120a, can perform a caching function. The nonvolatile memory device120acan be an SCM device. Examples of the nonvolatile memory device120bcan include a hard drive, an SSD, a magnetoresistive random access memory (MRAM) device, etc.

In some examples, the user device100can be in a first power mode, such as a power-save mode, meaning that the user device100is operating at a lower power level than a full-power mode, which can be a second power mode. In the power-save mode, a memory image122of data for processes executed by the user device100can be stored in the nonvolatile memory device120athat performs the caching function. To store the memory image122in the nonvolatile memory device120a, the processor140can generate a command126afor the storage device110upon determining the user device100is in the power-save mode. The command126acan indicate the memory image122is to be stored in the nonvolatile memory device120aand can prevent the memory image122from being stored in the nonvolatile memory device120b. The processor140can also allocate a virtual address of the nonvolatile memory device120bin which the memory image122can be stored subsequent to being stored in the nonvolatile memory device120a. The virtual address can be included in the command126aas a virtual address indication128. But, the virtual address may not exist in the nonvolatile memory device120b. For example, the nonvolatile memory device120bmay be an SSD with 256 GB and the processor140may allocate the virtual address to be higher than an address available in the 256 GB. As a result, the memory image122can remain in the nonvolatile memory device120aand not be moved to the nonvolatile memory device120b.

Additionally, during the power-save mode, the user device100can be in a state in which no processes are executing on the user device100. As a result, no additional writes can be received that would use the nonvolatile memory device120a. So, the memory image122can be stored in the nonvolatile memory device120awithout subsequently being destaged to the nonvolatile memory device120b.

At some point in time subsequent to the user device100being in the power-save mode, the processor140can determine that the user device100is in the full-power mode. In response, the processor140can generate a command126bto store the memory image122in the volatile memory device130. The command126bcan also prevent the memory image122from being stored in the nonvolatile memory device120b. The processor140can then read the memory image122from the nonvolatile memory device120ainto the volatile memory device130. The processor140can also remove the memory image122from the nonvolatile memory device120abased on the command126bin response to the memory image122being stored in the volatile memory device130. As a result, the space that the memory image122was occupying in the nonvolatile memory device120acan become available for other data. The space in the nonvolatile memory device120abecomes available without the memory image122being destaged to the nonvolatile memory device120b.

The nonvolatile memory device120bmay be able to store data that is not the memory image122while the user device100is in the full-power mode or in the power-save mode. For example, while the user device100is in the full-power mode, the processor140can receive a write request132for a data unit124. The processor140can initially store the data unit124in the nonvolatile memory device120a. After a predetermined length of time passes from storing the data unit124in the nonvolatile memory device120a, or once the nonvolatile memory device120ais full, the processor140can move the data unit124to the nonvolatile memory device120b.

FIG.1is illustrative and non-limiting. Other examples may include more components, fewer components, different components, or a different arrangement of the components shown inFIG.1. For example, although the user device100includes one storage device in the example ofFIG.1, the user device100may include a larger number of storage devices in other examples. Additionally, whileFIG.1is described with respect to a power-save mode and a full-power mode, the prevention of destaging to the nonvolatile memory device120bmay be used for any process that produces data that does not have to be maintained long term. For example, the prevention of destaging to the nonvolatile memory device120bmay be used for a build process, image processing, data mining, etc.

FIG.2is a block diagram of another system for implementing preventing memory image destaging to a nonvolatile memory device according to some aspects of the present disclosure. The system includes a computing device200that is communicatively coupled to a processor202and a memory204. The processor202and the memory204may be part of the computing device200. The processor202may be the processor140fromFIG.1.

The processor202can include one processor or multiple processors. Non-limiting examples of the processor202include a Field-Programmable Gate Array (FPGA), an application-specific integrated circuit (ASIC), a microprocessor, etc. The processor202can execute instructions206stored in the memory204to perform operations. The instructions206may include processor-specific instructions generated by a compiler or an interpreter from code written in any suitable computer-programming language, such as C, C++, C#, etc.

The memory204can include one memory or multiple memories. The memory204can be non-volatile and may include any type of memory that retains stored information when powered off. Non-limiting examples of the memory204include electrically erasable and programmable read-only memory (EEPROM), flash memory, or any other type of non-volatile memory. At least some of the memory204can include a non-transitory computer-readable medium from which the processor202can read instructions206. A computer-readable medium can include electronic, optical, magnetic, or other storage devices capable of providing the processor202with computer-readable instructions or other program code. Non-limiting examples of a computer-readable medium include magnetic disk(s), memory chip(s), ROM, random-access memory (RAM), an ASIC, a configured processor, optical storage, or any other medium from which a computer processor can read the instructions206.

In some examples, the processor202can execute the instructions206to perform operations. For example, the processor202can determine, subsequent to the computing device200being in a first power mode212and having a memory image222stored in a first nonvolatile memory device220athat performs a caching function208, that the computing device200is in a second power mode214that is a higher power mode than the first power mode212. The first nonvolatile memory device220amay be an SCM device that is included in a storage device, such as the storage device110inFIG.1. The processor202can, in response to determining that the computing device200is in the second power mode214, generate a first command226to store the memory image222in a volatile memory device230and to prevent the memory image222from being stored in a second nonvolatile memory device220b. The volatile memory device230can be a DRAM device and the second nonvolatile memory device220bcan be an SSD. The first command226can ensure that the memory image222is not destaged to the second nonvolatile memory device220b, and thus reduce write amplification and erase-cycle usage involved with moving data to and from the second nonvolatile memory device220b.

FIG.3is a flowchart of a process for implementing preventing memory image destaging to a nonvolatile memory device according to some aspects of the present disclosure. The processor202can implement some or all of the steps shown inFIG.3. Other examples can include more steps, fewer steps, different steps, or a different order of the steps than is shown inFIG.3. The steps ofFIG.3are discussed below with reference to the components discussed above in relation toFIG.2.

In block302, the processor202determines, subsequent to the computing device200being in a first power mode212and having a memory image222stored in a first nonvolatile memory device220athat performs a caching function208, that the computing device200is in a second power mode214. The second power mode214can be a higher power mode than the first power mode212. For example, the first power mode212may be a power-save mode and the second power mode214may be a full-power mode. The first nonvolatile memory device220amay be an SCM device. The memory image222can be stored in the first nonvolatile memory device220abased on a command generated by the processor202. The command can include an indication of a virtual address for the second nonvolatile memory device220bin which the memory image222is to be stored subsequent to being stored in the first nonvolatile memory device220a. But, the second nonvolatile memory device220bcan exclude the virtual address, so the memory image222may not be stored in the second nonvolatile memory device220b. Additionally or alternatively, the command may include a time length for which the memory image222is to be in the first nonvolatile memory device220abefore being moved to the second nonvolatile memory device220b. To prevent the memory image222from being moved to the second nonvolatile memory device220b, the time length can be indicated to be infinite. The first nonvolatile memory device220aand the second nonvolatile memory device220bmay be part of a storage device in communication with the processor202and the volatile memory device230.

In block304, the processor202, in response to determining that the computing device200is in the second power mode214, generates a first command226to store the memory image222in the volatile memory device230. The first command226can also prevent the memory image222from being stored in the second nonvolatile memory device220b. The first command226may designate an address of the volatile memory device230for the memory image222to be stored in. The first command226may additionally include a virtual address of the second nonvolatile memory device220bthat the second nonvolatile memory device220bdoes not include, so the memory image222may not be stored in the second nonvolatile memory device220b. As a result, the memory image222can be moved between the volatile memory device230and the first nonvolatile memory device220awithout being stored in the second nonvolatile memory device220b. But, in the second power mode214, data may be written to and read from the second nonvolatile memory device220b.

In block306, the processor202, in response to generating the first command226, stores the memory image222in the volatile memory device230. The processor202can read the memory image222from the first nonvolatile memory device220ainto the volatile memory device230. Operations of the computing device200can then be resumed using the memory image222in the volatile memory device230. The processor202can also remove the memory image222from the first nonvolatile memory device220abased on the first command226in response to the memory image222being stored in the volatile memory device230. As a result, the space that the memory image222was occupying in the first nonvolatile memory device220acan become available for other data without the memory image222being destaged to the second nonvolatile memory device220b.