Information processing system and method

An information processing system includes: a first system that includes a group of arithmetic units, a controller, and an external device; and a second system configured to execute calculation which is the same as calculation executed in the first system and compare calculation results to each other, wherein the controller is configured to: stop a plurality of arithmetic units when it is detected that an output request to the external device is output from one or more arithmetic units among the plurality of arithmetic units that execute first calculation in the group of arithmetic units, the plurality of arithmetic units including one or more arithmetic units that does not output the output request, transmit first comparison target data including a value output in response to the output request to the second system, and instruct the stopped one or more arithmetic units to execute second calculation.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2014-153940, filed on Jul. 29, 2014, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a synchronization technology for a fault-tolerant computer.

BACKGROUND

As a method of implementing synchronization in a fault tolerant computer, there is a synchronization scheme called a lock step. In the lock step, when the same “initial state and execution command of central processing units (CPUs)” are given to calculators, states are matched with each other between two systems by executing the same command from the same initial state using determinativeness of the calculators in which calculation results are the same. An instruction lock step which is a kind of lock step is a scheme of matching states of cores and memory of CPUs in execution command units of the CPUs between two systems.

In the case of symmetric multiprocessing (SMP), information regarding an access order to a shared memory is used as calculation information as well as “an initial state and an execution command of a CPU” for the purpose that the results of calculations executed asynchronously between two systems are the same. Therefore, as the instruction lock step corresponding to the SMP, a scheme is adopted in which when synchronization is executed, two calculators are configured to have roles of a precedence system and a delay system, an access order and access content are recorded on a shared memory in the precedence system, the access order and the access content are transferred to the delay system, and the calculation is reproduced. That is, after a calculation result of the precedence system is confirmed, the calculation is then reproduced in the delay system. Therefore, until the calculation result of the precedence system is transferred, a delay time occurs in the delay system.

When the flow of the process is described in brief, calculation is started by the precedence system. Then, the precedence system transfers data of access to the shared memory generated during the calculation, data of a generated output request, and register values of cores as the calculation result to the delay system. Here, the calculation of the precedence system stops.

When the delay system receives the calculation result from the precedence system, the delay system reproduces the calculation. Then, the delay system compares the reproduction result of the calculation to the calculation result received from the precedence system and notifies the precedence system of the comparison result. The precedence system receives the comparison result from the delay system. In this case, when the comparison result indicates that the calculation results match each other, the precedence system executes output to an external device in response to an output request. Then, the calculation of the precedence system resumes.

However, in the related art, when a process is executed by the above-described flow without consideration of a case in which many cores are included in the CPU, the cores of the precedence system which have not executed the output also stop calculation until the reception of the comparison result from the delay system. For this reason, calculation resources may not be utilized effectively.

As a related technical document, there is Japanese Laid-open Patent Publication No. 2004-46599.

SUMMARY

According to an aspect of the invention, an information processing system includes: a first system that includes a first group of arithmetic units, a first controller, and a first external device; and a second system that configured to execute calculation which is the same as calculation executed in the first system and compare calculation results to each other, wherein the first controller is configured to: control to stop a plurality of first arithmetic units when it is detected that a first output request to the first external device is output from one or more second arithmetic units among the plurality of first arithmetic units that execute processing with regard to first calculation in the first group of arithmetic units, the plurality of first arithmetic units including one or more third arithmetic units that does not output the first output request, transmit first comparison target data including a value to be output in response to the first output request to the second system, and instruct the one or more third arithmetic units stopped by the control to execute processing with regard to second calculation.

DESCRIPTION OF EMBODIMENTS

According to one aspect of an embodiment to be disclosed, calculation resources may be utilized effectively even when synchronization is executed in a fault tolerant computer. Hereinafter, the embodiment will be described with reference to the drawings.

First Embodiment

FIG. 1is a diagram illustrating an overview of an information processing system according to the embodiment. In the information processing system, a precedence system calculator100and a delay system calculator200are connected via an inter-system communication path190.

The precedence system calculator100includes a calculation unit110, a synchronization control unit120, a communication unit130executing communication via the inter-system communication path190, and an external device140. The calculation unit110includes a plurality of cores111(111ato111dinFIG. 1), a memory114shared by the cores111, a memory control unit112, and an access extraction unit113. In the following description, the terms, “an arithmetic unit,” “a processing unit,” and “a processor,” are not limited to the meaning of a CPU and are assumed to also include calculation units (110and210) or cores (111and211).

The memory control unit112controls access to the memory114. The access extraction unit113extracts the access to the memory114and notifies the synchronization control unit120of the extraction of the access.

The synchronization control unit120includes an access history storage unit121, an output value storage unit123, and a control unit122. The access history storage unit121stores data from the access extraction unit113. The output value storage unit123stores values output in response to output requests issued by the cores111of the calculation unit110. The control unit122executes various processes to establish synchronization related to an instruction lock step via the communication unit130and the inter-system communication path190, while cooperating with a synchronization control unit220of the delay system calculator200.

The external device140includes devices such as a storage device141and an I/O device142. The precedence system calculator is connected to another calculator via the external device140in some cases.

The delay system calculator200includes a calculation unit210, the synchronization control unit220, a communication unit230executing communication via the inter-system communication path190, and an external device240. The calculation unit210includes a plurality of cores211(211ato211dinFIG. 1), a memory214shared by the cores211, a memory control unit212, and an access extraction unit213.

The memory control unit212controls access to the memory214. The access extraction unit213extracts the access to the memory214and notifies the synchronization control unit220of the extraction of the access.

The synchronization control unit220includes an access history storage unit221, an output value storage unit223, and a control unit222. The access history storage unit221stores data from the access extraction unit213. The output value storage unit223stores values output in response to output requests issued by the cores211of the calculation unit210. The control unit222executes various processes to establish synchronization related to an instruction lock step via the communication unit230and the inter-system communication path190, while cooperating with a synchronization control unit120of the precedence system calculator100.

The external device240includes devices such as a storage device241and an I/O device242. The delay system calculator is connected to another calculator via the external device240in some cases.

FIG. 2is a diagram illustrating a functional block configuration example of the control unit122of the precedence system calculator100. The control unit122includes a group correspondence table1221, a group management unit1222, and a core execution control unit1223. The group correspondence table1221retains data for managing whether each of the cores111is a core outputting an output request and a core capable of executing calculation. The group correspondence table1221is retained along with the number (for example, an execution sequence number) of a synchronization confirmation point at the time of update in order to make reference in sequence later.

The group correspondence table1221has, for example, a format illustrated inFIG. 3. In the example ofFIG. 3, core IDs of the cores111and affiliated groups of the cores are stored. Here, the affiliated group of each core refers to an output group to which the core issuing an output request is affiliated (that is, belongs) or a calculation group to which the core capable of executing calculation is affiliated.

The group management unit1222executes update, management, or the like of the group correspondence table1221. The core execution control unit1223controls running and stopping of each core according to the group correspondence table1221.

FIG. 4is a diagram illustrating a functional block configuration example of the control unit222of the delay system calculator200. The control unit222includes a group correspondence table2221, a core execution control unit2222, and a comparison unit2223.

The group correspondence table2221is sent from the control unit122in the precedence system calculator100. The core execution control unit2222controls running and stopping of each core according to the group correspondence table2221. The comparison unit2223executes a process of comparing a calculation result of the precedence system calculator100to a calculation result of the delay system calculator200and verifying the calculation results.

Next, the flow of a process of the system illustrated inFIG. 1will be described with reference toFIGS. 5 to 9. First, the control unit122of the synchronization control unit120in the precedence system calculator100acquires a register value, data M of a memory, and data C of a cache from the calculation unit110of the precedence system calculator100and transfers the register value, the data M, and the data C to the synchronization control unit220of the delay system calculator200(process (1)). The control unit222of the synchronization control unit220in the delay system calculator200receives the register value, the data M of the memory, and the data C of the cache.

The control unit122of the synchronization control unit120in the precedence system calculator100issues an initialization request to the synchronization control unit220of the delay system calculator200(process (2)). When receiving the initialization request, the control unit222of the synchronization control unit220in the delay system calculator200issues an initialization command to initialize the cores211using the data M of the memory and the data C of the cache to the calculation unit210in the delay system calculator200(process (3)). Accordingly, the same initialization state as that of the calculation unit110of the precedence system calculator100is realized in the calculation unit210of the delay system calculator200.

Thereafter, the control unit122(the core execution control unit1223) of the synchronization control unit120in the precedence system calculator100issues a calculation execution command to the calculation unit110(process (4)). Thus, the cores111of the calculation unit110start calculation. Initially, all of the cores111are affiliated to a calculation group.

During the calculation, when one core111of the calculation unit110gains access to the memory114, the access is detected by the access extraction unit113. Then, the access extraction unit113notifies the control unit122of the synchronization control unit120of access S1to the memory114(process (5)).

When the control unit122is notified of the access S1to the memory114, the control unit122of the synchronization control unit120transfers data of the access S1to the control unit222of the synchronization control unit220in the delay system calculator200(process (6)). When the control unit222receives the data of the access S1to the shared memory, the control unit222of the synchronization control unit220in the delay system calculator200stores the data of the access S1in the access history storage unit221. The data of the access S1to the shared memory is also stored in the access history storage unit121of the synchronization control unit120in the precedence system calculator100.

Thereafter, the cores111(at least one core) of the calculation unit110of the precedence system calculator100issue an output request (process (7)). Then, the control unit122of the synchronization control unit120in the precedence system calculator100receives the output request and stores an estimated output value O1by the output request in the output value storage unit123.

Accordingly, the control unit122(the core execution control unit1223) issues a calculation stop command to the cores111of the calculation unit110of the precedence system calculator100(process (8)). Thus, the cores111of the calculation unit110of the precedence system calculator100stop the calculation. Further, the control unit122issues a command to acquire a register value to the cores111(for example, only the cores executing the calculation) of the calculation unit110(process (9)). The cores111of the calculation unit110outputs a register value R1to the control unit122of the synchronization control unit120in response to the command to acquire the register value (process (10)).

Here, the control unit122(the group management unit1222) of the synchronization control unit120in the precedence system calculator100registers data indicating that the cores issuing the output requests are affiliated to an output group along with an execution sequence number at this time in the group correspondence table1221of the precedence system calculator100(process (11)). The control unit122(the group management unit1222) transfers the changed group correspondence table1221to the synchronization control unit220of the delay system calculator200as well as executing the registration (process (12)). The control unit222of the synchronization control unit220in the delay system calculator200executes registration in the group correspondence table2221.

Initially, the group correspondence table1221illustrated inFIG. 6is assumed to be set. When the output requests are assumed to be output by the cores1and2(the cores111aand111b), the group correspondence table1221illustrated inFIG. 3is registered.

The control unit122of the synchronization control unit120in the precedence system calculator100transfers the estimated output value O1to the synchronization control unit220of the delay system calculator200(process (13)) and also transfers the register value R1to the synchronization control unit220of the delay system calculator200(process (14)).

The process proceeds to a process ofFIG. 7. The control unit122of the synchronization control unit120in the precedence system calculator100specifies the cores affiliated to the calculation group from the latest group correspondence table1221with reference to the group correspondence table1221(process (15)).

Then, the control unit122(the core execution control unit1223) of the synchronization control unit120in the precedence system calculator100issues a calculation execution command to the specified cores (process (16)). The calculation unit110of the precedence system calculator100executes calculation X in the cores receiving the instruction by the calculation execution command. In the embodiment, the cores issuing the output requests are in a standby state, but the other cores execute the following calculation without standby along with the cores affiliated to the calculation group and issuing the output commands. In this way, effective utilization of the calculation resources is achieved.

During the execution of the calculation X, the cores111of the calculation unit110in the precedence system calculator100gain access to the memory114in some cases. This access is detected by the access extraction unit113. The access extraction unit113notifies the control unit122of the synchronization control unit120of access S2to the memory114(process (17)).

When the control unit122is notified of the access S2to the memory114, the control unit122of the synchronization control unit120transfers data of the access S2to the control unit222of the synchronization control unit220in the delay system calculator200(process (18)). When the control unit222receives the data of the access S2to the shared memory, the control unit222of the synchronization control unit220in the delay system calculator200stores the data of the access S2to the shared memory in the access history storage unit221. The data of the access S2to the shared memory is also stored in the access history storage unit121of the synchronization control unit120in the precedence system calculator100.

On the other hand, when the control unit222receives the estimated output value O1and the register value R1from the precedence system calculator100, the control unit222(the core execution control unit2222) of the synchronization control unit220in the delay system calculator200specifies the cores affiliated to the calculation group from the oldest group correspondence table among the group correspondence tables which have not yet been referred to, with reference to the group correspondence table2221(process (19)). In this example, as illustrated inFIG. 6, four cores are affiliated to the calculation group.

Then, the control unit222of the synchronization control unit220issues a calculation reproduction command to the calculation unit210so that the cores affiliated to the calculation group execute calculation reproduction using the register value R and the access S1received in the process (1) (process (20)). In response to the calculation reproduction command, the cores affiliated to the calculation group in the calculation unit210execute the calculation having executed in the precedence system calculator100. Then, as in the precedence system calculator100, the access to the shared memory is generated, but access to the data of the access S1received from the precedence system calculator100is executed. During the calculation reproduction, the cores211(at least one core) of the calculation unit210of the delay system calculator200issue an output request (process (21)). Then, the control unit222of the synchronization control unit220in the delay system calculator200receives the output request and stores an estimated output value O2by the output request in the output value storage unit223.

Then, the control unit222(the core execution control unit2222) issues a calculation reproduction stop command to the cores211of the calculation unit210of the delay system calculator200(process (22)). Thus, the cores211of the calculation unit210of the delay system calculator200stop the calculation reproduction. Further, the control unit222issues a command to acquire a register value to the cores211(for example, only the cores executing the calculation) of the calculation unit210(process (23)). The cores211of the calculation unit210outputs a register value R2to the control unit222of the synchronization control unit220in response to the command to acquire the register value (process (24)).

Then, the control unit222(the comparison unit2223) of the synchronization control unit220in the delay system calculator200reconfirms the cores affiliated to the calculation group from the group correspondence table for the executed calculation reproduction with reference to the group correspondence table2221(process (25)). The present process may be executed before the register value is acquired.

Thereafter, the control unit222of the synchronization control unit220in the delay system calculator200transfers a comparison result to the synchronization control unit120of the precedence system calculator100(process (27)). The control unit122of the synchronization control unit120in the precedence system calculator100receives the comparison result from the delay system calculator200.

When the comparison result indicates O1=O2and R1=R2, the synchronization control unit220of the delay system calculator200outputs the estimated output value O2to the external device240.

When the control unit122of the synchronization control unit120in the precedence system calculator100receives the comparison result from the delay system calculator200, the control unit122issues a calculation stop command to the calculation unit210(process (28)). When the control unit122confirms the comparison result and the comparison result indicates O1=O2and R1=R2, the control unit122outputs the estimated output value O1stored in the output value storage unit123to the external device140(process (29)).

The control unit122(the group management unit1222) of the synchronization control unit120in the precedence system calculator100specifies the cores having outputted the output request for the calculation in which the comparison result may be obtained and registers data (that is, deletion of the output group) indicating that the specified cores are affiliated along with the execution sequence number at this time to the group correspondence table1221of the precedence system calculator100(process (30)). The control unit122(the group management unit1222) executes such registration and transfers the changed group correspondence table1221to the synchronization control unit220of the delay system calculator200(process (31)). The control unit222of the synchronization control unit220in the delay system calculator200registers in the group correspondence table2221.

By executing such a process, it is possible to avoid all of the cores being in the standby state in section of the calculation X. Therefore, effective utilization of the calculation resources may be achieved, and thus calculation efficiency is improved.

FIG. 8is a diagram schematically illustrating a temporal change of a use state of the cores. An example in which four cores are present as inFIG. 1is illustrated. The cores issuing the output request are assumed to cores1and2(the cores111aand111b). Time flows from the upper side to the lower side. When calculation1is first executed by the precedence system calculator100and the cores1and2issue the output request at a point A, calculation reproduction1is executed by the cores1to4in the delay system calculator200. At the point A, the group correspondence table1221illustrated inFIG. 3is registered.

On the other hand, in the precedence system calculator100, the cores3and4other than the cores1and2issuing the output request execute calculation2immediately after the point A. Meanwhile, in the delay system calculator200, calculation reproduction1ends and the comparison result is output to the precedence system calculator100at a point B. Here, when the comparison result indicates matching of the register value and the estimated output value, the precedence system calculator100and the delay system calculator200execute output. At the point B, the group correspondence table1221illustrated inFIG. 6is registered.

When the output is executed, the cores1to4execute calculation3in the precedence system calculator100. Further, in the delay system calculator200, the cores3and4execute calculation reproduction2based on the group correspondence table2221at the point A.

Thereafter, in the precedence system calculator100, the cores1and2are assumed to issue the output request at a point C, as in calculation1. At the point C, the same correspondence table1221(seeFIG. 3) as that of the point A is registered. Then, in the precedence system calculator100, the cores3and4execute calculation4based on the group correspondence table1221illustrated inFIG. 3.

On the other hand, in the delay system calculator200, when calculation reproduction2ends, the cores1to4execute calculation reproduction3corresponding to calculation3based on the group correspondence table2221at the point B. Then, when the comparison result in calculation reproduction3is transmitted from the delay system calculator200to the precedence system calculator100and the comparison result indicates matching of the register value and the estimated output value, the precedence system calculator100and the delay system calculator200execute output.

On the other hand, when all of the cores are configured to execute calculation as in the related art, as illustrated inFIG. 9, standby times Y and Z of the cores1to4may occur. Since the cores having not issued the output request stop, it may be understood that efficiency deteriorates.

In contrast, although some of the cores execute calculation2and calculation4inFIG. 8, the calculation may be executed without standby. Thus, it may be understood that efficiency is improved.

InFIG. 8, the example in which two cores issues the output request among four cores is illustrated. However, when the number of cores increases, a ratio of the number of cores issuing the output request is considered not to be the same or increase and a ratio of the cores issuing the output request to the total number of cores is considered to decrease. Then, when a CPU including more cores is adopted, the effect of the embodiment is further achieved.

Next, a specific process by the synchronization control unit120of the precedence system calculator100will be described with reference toFIGS. 10 to 21.

First, the synchronization control unit120executes an initialization process (S1inFIG. 10). The initialization process will be described with reference toFIG. 11.

First, the control unit122of the synchronization control unit120reads the register value of the calculation unit110(S31inFIG. 11). The control unit122reads the data of the memory114of the calculation unit110(S33). Further, the control unit122reads the data of the cache of the calculation unit110(S35).

Then, the control unit122transfers the register value, the memory data, and the cache data to the synchronization control unit220of the delay system calculator200(S37). Further, the control unit122transmits an initialization request of the calculation unit210of the delay system calculator200to the synchronization control unit220of the delay system calculator200(S39). Then, the process returns to the calling original process.

In this way, the state of the calculation unit210of the delay system calculator200is matched with the state of the calculation unit110of the precedence system calculator100.

The description returns to the description of the process ofFIG. 10. The control unit122determines whether the comparison result is received from the delay system calculator200(S3). When the comparison result is received from the delay system calculator200, the process proceeds to a process ofFIG. 20via a terminal A.

Conversely, when the comparison result is not received from the delay system calculator200, the control unit122executes a calculation instruction process (S5). The calculation instruction process will be described with reference toFIG. 12.

The core execution control unit1223of the control unit122specifies the cores affiliated to the calculation group with reference to the latest group correspondence table1221(S41inFIG. 12).

Then, the core execution control unit1223of the control unit122issues a calculation execution command to execute calculation by only the specified cores to the calculation unit110(S43).

In this way, the cores issuing the output request stand by until receiving the comparison result from the delay system calculator200, but the other cores still execute the calculation.

The description returns to the description of the process ofFIG. 10. When the control unit122receives the data of the access to the memory114from the access extraction unit113of the calculation unit110, the control unit122transfers the data of the access to the memory114to the delay system calculator200(S7). The data of the access is stored in the access history storage unit121.

The control unit122determines whether synchronization confirmation point notification is received from the calculation unit110(S9). For example, whenever the calculation unit110counts the number of executions of if branch and the number of executions reaches a predetermined number of times, the synchronization confirmation point notification is assumed to be issued.

When the synchronization confirmation point notification is received, the control unit122executes a confirmation process (S19). The confirmation process will be described with reference toFIG. 13.

First, the core execution control unit1223of the control unit122issues a calculation stop command to the calculation unit110(S51inFIG. 13). Then, the cores111of the calculation unit110stop the calculation.

The control unit122issues a command to acquire the register value to the calculation unit110(S53). Then, the calculation unit110outputs the register value to the control unit122.

Thereafter, the control unit122receives the register value from the calculation unit110(S55). The process returns to the calling original process.

The description returns to the description of the process ofFIG. 10. The control unit122transfers the acquired register value to the synchronization control unit220of the delay system calculator200(S21). Thereafter, the process returns to the process of S3via a terminal B.

Conversely, when the synchronization confirmation point notification is not received, the control unit122determines whether the output request is received from the calculation unit110(S11). When the output request is not received, the process returns to S7.

Conversely, when the output request is received, the control unit122executes the confirmation process (S13). The confirmation process is a process described inFIG. 13. The control unit122executes a registration process (S15). The registration process will be described with reference toFIG. 14.

First, the group management unit1222of the control unit122acquires the IDs of all the cores of the calculation unit110(S61inFIG. 14). The group management unit1222acquires the output request to the external device140(S63). The control unit122stores the estimated output value output in response to the output request and the IDs of the cores having outputted the output request in the output value storage unit123.

The group management unit1222checks the affiliated group of each core with reference to the group correspondence table1221(S65).

The group management unit1222updates the group correspondence table1221in association with the execution sequence number at the time of the issuing of the output request using the affiliated group of the core IDs included in the output request as the output group (S67).

For example, the group correspondence table1221illustrated inFIG. 6is updated to the group correspondence table1221illustrated inFIG. 3. When the output group is already present, for example, the group correspondence table1221is updated to, for example, the group correspondence table1221illustrated inFIG. 15in some cases. That is, a first output group (output1) including the cores1and2and a second output group (output2) including the core3are registered.

The group management unit1222notifies the synchronization control unit220of the delay system calculator200of the updating of the group correspondence table1221(S69). Accordingly, the group correspondence table2221is updated.

In this way, it is possible to specify the cores which may be used for the following calculation.

The description returns to the description of the process ofFIG. 10. The control unit122transfers the estimated output value of the output request to the synchronization control unit220of the delay system calculator200(S17). For example, the synchronization control unit220of the delay system calculator200stores the received estimated output value in the output value storage unit223. The subsequent process proceeds to S21.

Since the process after the terminal A is executed after completion of the calculation reproduction in the delay system calculator200, a process of the synchronization control unit220in the delay system calculator200will be described first with reference toFIGS. 16 to 19.

First, the control unit222of the synchronization control unit220determines whether the initialization request is received from the precedence system calculator100(S71inFIG. 16). When the initialization request is received, the initialization of the calculation unit210is executed based on the memory data and the cache data among the register value, the memory data, and the cache data received from the synchronization control unit120of the precedence system calculator100(S73). The process returns to S71via a terminal C.

Conversely, when the initialization request is not received, the control unit222of the synchronization control unit220receives the data of the access to the shared memory from the synchronization control unit120of the precedence system calculator100(S75) and stores the data in the access history storage unit221.

The control unit222of the synchronization control unit220receives the register value from the synchronization control unit120of the precedence system calculator100(S77). The register value received in S77is a target compared to the register value included in a subsequent calculation result.

The control unit222executes the calculation reproduction process by the calculation group (S79). The calculation reproduction process will be described with reference toFIG. 17.

The core execution control unit2222of the control unit222specifies the cores affiliated to the calculation group with reference to the group correspondence table2221of a section to be subsequently executed (S91inFIG. 17). The oldest group correspondence table (the execution sequence number is the smallest) is used among unused group correspondence tables.

The core execution control unit2222of the control unit222confirms whether data of the access to the shared memory, a register value at the time of start, and a register value at the time of end are provided for the specific cores (S93). In the example ofFIG. 5, the core execution control unit2222determines whether register values R and R1and data S1of access to the shared memory are provided. When the data and the values are not provided, the core execution control unit2222stands by.

When the register values at the time of start and the time of end and the data of the access to the shared memory are provided, the core execution control unit2222of the control unit222issues a calculation reproduction execution command based on the data of the access to the shared memory and the register values by the cores affiliated to the calculation group to the calculation unit210(S95). When the access extraction unit213detects the access to the memory214from the cores211of the calculation unit210, the data of the access to the shared memory received from the precedence system calculator100is output to the cores211of the access source.

When the output request is generated by the calculation unit210(Yes route in S97), the control unit222receives the output request from the calculation unit210(S99). The estimated output value output in response to the output request and the ID of the output source core are retained. The process proceeds to S103.

Conversely, when the output request is not generated by the calculation unit210(No route in S97), the control unit222receives the synchronization confirmation point notification from the calculation unit210(S101). For example, the control unit222is notified that if branch is executed a predetermined number of times.

Thereafter, the core execution control unit2222of the control unit222issues the calculation reproduction stop command to the calculation unit210(S103).

In this way, the calculation reproduction is executed in the delay system calculator200.

The description returns to the description of the process ofFIG. 16. The control unit222executes an acquisition process for the process result of the calculation reproduction process (S81). The acquisition process will be described with reference toFIG. 18.

First, the control unit222issues a command to acquire the register value to the calculation unit210(S111inFIG. 18). Thus, the calculation unit210reads the register values and outputs the register values to the control unit222.

Accordingly, the control unit222acquires the register values from the calculation unit210(S113). The process returns to the process ofFIG. 16.

The description returns to the description of the process ofFIG. 16. The control unit222executes the comparison process for the calculation result (S83). The comparison process for the calculation result will be described with reference toFIG. 19.

First, the comparison unit2223of the control unit222specifies the cores of the calculation group with reference to the group correspondence table2221of a section in which the calculation reproduction is executed (S121).

The comparison unit2223of the control unit222compares the acquired register value to the register value received from the precedence system calculator100in regard to the specified cores (S123).

When the output request is received from the calculation unit210(Yes route in S125), the comparison unit2223of the control unit222compares the estimated output value obtained by the calculation reproduction to the estimated output value received from the precedence system calculator100(S127). The process proceeds to S129.

Conversely, when the output request is not received from the calculation unit210(No route in S125), the process proceeds to S129.

The comparison unit2223of the control unit222transmits the comparison result to the synchronization control unit120of the precedence system calculator100(S129). The comparison result of S123and the comparison result of S127at the time of the issuing of the output request are transmitted to the precedence system calculator100. The process returns to the calling original process.

The description returns to the description of the process ofFIG. 16. At the time of reception of the output request, the calculation unit210executes the output when the comparison result indicates the register value and the estimated output value match (S85).

When such a process is executed, the calculation reproduction may be executed properly by the delay system calculator200.

The description returns to the description of the process of the synchronization control unit120of the precedence system calculator100(FIGS. 20 and 21). The control unit122of the synchronization control unit120determines whether the comparison result indicates the matching when the comparison result is received from the synchronization control unit220of the delay system calculator200(S131). The matching of the register values and the matching of the estimated output values are each determined.

When the register values and the estimated output values are partially not matched, the control unit222executes a pre-decided exception process (S133). The exception process is the same as that of the related art and the detailed description will be omitted herein. Then, the process ends.

Conversely, when the comparison result indicates that the register values and the estimated output values are entirely matched, the control unit122determines whether there is an output request related to the comparison result (S135). When there is no output request related to the comparison result, the process proceeds to S139.

Conversely, when there is the output request related to the comparison result, the control unit122reads an output value stored in the output value storage unit123and outputs the output value to the external device140(S137).

The control unit122executes a deletion process (S139). When this process ends, the process returns to S3ofFIG. 10via the terminal B. The deletion process will be described with reference toFIG. 21.

First, the group management unit1222of the control unit122acquires the IDs of the cores having issued the output request from, for example, the output value storage unit123(S141inFIG. 21).

The group management unit1222of the control unit122checks the affiliated group of each core with reference to the group correspondence table of a section related to the output request (S143).

The group management unit1222of the control unit122updates the group correspondence table1221using the group affiliated to the cores having issued the output request as the calculation group in association with the execution sequence number at this time point (S145).

The control unit122notifies the synchronization control unit220of the delay system calculator200of the updating of the group correspondence table1221(S147). The control unit222of the synchronization control unit220in the delay system calculator200updates the group correspondence table2221when the synchronization control unit220is notified of the updating of the group correspondence table.

When the above-described processes are executed, as described above, use efficiency of the cores is improved, and thus the calculation efficiency is improved.

Second Embodiment

In an embodiment, an example in which functions executing the processes described in the first embodiment are mounted mainly by software will be described.

Specifically, in the embodiment, the technology described in the first embodiment is applied to a calculation virtual machine operated on a hypervisor.

In the embodiment, as described inFIG. 22, two physical servers are connected to each other via an inter-system communication path. Each physical server includes a virtualization support mechanism, a memory control unit, a CPU including a plurality of cores (four cores inFIG. 22), a memory, a chip set, an external device, and a communication unit. In each physical server, a hypervisor is executed to activate and control a virtual machine.

The virtual machine is generated in each of the two physical servers and synchronization is established in a virtual machine level. A plurality of virtual cores may be allocated to the virtual machine to be synchronized and an SMP is executed. In the SMP, calculation is executed by cooperation of the plurality of cores using a shared memory which is a memory region which may be accessed by the plurality of cores.

In the embodiment, for example, two physical servers having, for example, a configuration illustrated inFIG. 23are constructed. The physical server is, for example, a calculator that has an Intel x86 CPU. In each physical server, for example, a hypervisor which is virtualization software called XenServer is executed and control software is executed on a management virtual machine dom0 generated on the hypervisor. The control software is software which is executed to activate, manage, and control a virtual machine for establishing synchronization.

The control software generates a calculation virtual machine and a control virtual machine in each physical server. The calculation virtual machine includes a plurality of virtual cores, and a driver executing a process according to the embodiment and a general operating system (OS) are executed.

In each physical server, a virtual disc is prepared for a kind of external device.

The calculation virtual machine and the control virtual machine are virtually wired with an internal communication path for executing mutual communication. The two physical servers realize synchronization by mutually executing communication using the inter-system communication path that directly wires the two physical servers. The calculation virtual machine corresponds to the calculation unit according to the first embodiment and the control virtual machine corresponds to the synchronization control unit according to the first embodiment.

In such a configuration, input and output of a memory, a cache, and a register are controlled and command execution is monitored by using a virtualization support mechanism (for example, Intel Virtualization Technology) which the CPU of the physical server has.

When the command execution is monitored, a counter that counts the number of executions of if branch which is a kind of counter of a performance counter in, for example, an Intel x86 CPU is used. That is, whenever if branch is executed a given number of times, calculation execution/stop is realized by pausing/resuming a virtual clock of the virtual machine using the function of the hypervisor. Further, a timing at which a process is generated is managed as an execution sequence number by using the counter.

The calculation reproduction is realized by executing pausing using the function of the hypervisor when access to the shared memory is detected using the virtualization support mechanism of the CPU, in addition to the above-described calculation execution/stop, rewriting a value of a memory of an access destination by the virtualization support mechanism, and then resuming the calculation virtual machine.

As the OS of the calculation virtual machine, for example, Windows (registered trademark) is used. To control the input and output of the calculation virtual machine and an operation of the calculation virtual machine, a driver according to the embodiment is installed. The driver notifies the control virtual machine of the input and output generated in the calculation virtual machine through virtual wiring as an output request to the external device.

As the OS of the control virtual machine, for example, Linux (registered trademark) is installed and controls the calculation virtual machine based on information obtained from the driver of the calculation virtual machine through virtual wiring. The group correspondence table is managed by the control virtual machine. When an output request is generated, the group correspondence table is generated and updated by the control virtual machine and virtual cores used for calculation of the calculation virtual machine are controlled. In the group correspondence table, the execution sequence number at the time of the generation of the output request, the ID of the virtual core executing the output request, and the execution sequence number at the time of execution of the output are treated as one set. An output process permitted by the control virtual machine which is the synchronization control unit is executed by the management virtual machine (dom0).

Third Embodiment

FIG. 24is a diagram illustrating a configuration example of an information processing system according to an embodiment. In the embodiment, a precedence system calculator300and a delay system calculator400are connected to each other via, for example, a network such as Ethernet (registered trademark).

The precedence system calculator300includes CPUs310and320, a chip set350, memories330and340, an external device370, and a communication unit360.

The CPU310includes cores311aand311b, a ring bus312, a last level (LL) cache313, and a memory controller314. The cores311aand311b, the LL cache313, and the memory controller314are connected to the ring bus312. The memory330which is a shared memory is connected to the memory controller314.

The CPU320also includes cores321aand321b, a ring bus322, an LL cache323, and a memory controller324. The cores321aand321b, the LL cache323, and the memory controller324are connected to the ring bus322. The memory340which is a shared memory is connected to the memory controller324.

The CPU310and the CPU320are connected to each other via a Quick Path Interconnect (QPI) bus380, and the chip set350is also connected to the QPI bus380.

The chip set350includes an access extraction unit351that extracts access to the memories330and340which are the shared memories, an access history storage unit352, a control unit353that executes a main process in the embodiment, and a device control unit354that has the function of a chip set of the related art.

The access extraction unit351and the control unit353receives memory transactions by the cores311aand311band the cores321aand321bvia the QPI bus380. The device control unit354is connected to the external device370and the communication unit360via, for example, a Peripheral Component Interconnect Express (PCIe). The control unit353executes output to the external device370and the communication unit360via the device control unit354. The access extraction unit351, the access history storage unit352, and the control unit353are mounted with a field-programmable gate array (FPGA). In the embodiment, the output value storage unit123in the first embodiment is not provided.

In the embodiment, the LL caches313and323are used as buffers. Whenever each core executes an access request to the shared memory at the time of execution of an IF command, each core outputs a signal to the QPI bus380. The CPUs310and320, the QPI bus380, and the access extraction unit351in the embodiment correspond to the calculation unit in the first embodiment. The units of the chip set350excluding the access extraction unit351and the communication unit360in the embodiment correspond to the synchronization control unit in the first embodiment.

The control unit353and the access extraction unit351monitor a generated command by monitoring the ring bus312via the QPI bus380. Accordingly, access to the memories330and340is monitored to count the number of times the IF command is executed. By correcting an interrupt vector table so that the control unit353is notified of content output at the time of generation of output interrupt, the control unit353acquires generation of an output request (which is also referred to as an output command). In the embodiment, since no output value storage unit is provided in the chip set350, writing on input output (IO) spaces by the CPUs310and320is executed on the memories330and340and is executed via the control unit353again after execution of calculation reproduction or the like.

The control unit353counts the number of times the IF command is executed by the cores311aand311band the cores321aand321b. Whenever the IF command is executed a given number of times, a synchronization confirmation point is generated. Based on the counted number, the control unit353possesses an execution sequence number indicating a timing at which each core executes the IF command.

The delay system calculator400has the same configuration as the precedence system calculator300. That is, the delay system calculator400includes CPUs410and420, a chip set450, memories430and440, an external device470, and a communication unit460.

The CPU410includes cores411aand411b, a ring bus412, a last level (LL) cache413, and a memory controller414. The cores411aand411b, the LL cache413, and the memory controller414are connected to the ring bus412. The memory430which is a shared memory is connected to the memory controller414.

The CPU420also includes cores421aand421b, a ring bus422, an LL cache423, and a memory controller424. The cores421aand421b, the LL cache423, and the memory controller424are connected to the ring bus422. The memory440which is a shared memory is connected to the memory controller424.

The chip set450includes an access extraction unit451that extracts access to the memories430and440which are the shared memories, an access history storage unit452, a control unit453that executes a main process in the embodiment, and a device control unit454that has the function of a chip set of the related art.

The access extraction unit451and the control unit453receives memory transactions by the cores411aand411band the cores421aand421bvia the QPI bus480. The device control unit454is connected to the external device470and the communication unit460via, for example, a Peripheral Component Interconnect Express (PCIe). The control unit453executes output to the external device470and the communication unit460via the device control unit454. The access extraction unit451, the access history storage unit452, and the control unit453are mounted with a field-programmable gate array (FPGA). In the embodiment, the output value storage unit223in the first embodiment is not provided.

Whenever each core executes an access request to the shared memory at the time of execution of an IF command, each core outputs a signal to the QPI bus480. The CPUs410and420, the QPI bus480, and the access extraction unit451in the embodiment correspond to the calculation unit in the first embodiment. The units of the chip set450excluding the access extraction unit451and the communication unit460in the embodiment correspond to the synchronization control unit in the first embodiment. The control unit453and the access extraction unit451monitor a generated command by monitoring the ring bus412via the QPI bus480.

As described above, in the embodiment, since values output in response to the output request are stored in the memories330and340, a structure is adopted to avoid that estimated output values stored in the memories330and340are rewritten before the output process is actually executed.

For this reason, in the embodiment, an output mode is provided in which the cores of the calculation group execute provisional calculation until the output request is generated and then the output is actually completed.

A difference between the provisional calculation and calculation in a normal mode is access to the memories330and340which are the shared memories. To avoid that the estimated output values are rewritten, consistency of the memories330and340is maintained by indirectly referring to the LL cache313or323, which is a buffer without executing writing directly, on the shared memories on the memories330and340. Here, to store the estimated output values temporarily in regions other than the memories330and340, the address of the memory330or340and the value are maintained in the LL cache313or323.

In the provisional calculation, the following memory related processes are performed:

(a) when access to the memories330and340is generated, values of corresponding addresses in the LL cache313or323are referred to rather than the values of the memories330and340;

(b) when reading is generated in a state in which the values of the corresponding addresses are not present in the LL caches313and323, a value in the memory330or340is directly referred to;

(c) when writing is generated in the state in which the values of the corresponding addresses are not present in the LL caches313and323, the writing on the memory330or340is not executed, and the corresponding address is newly generated instead in the LL cache313or323and the writing is executed thereon;

(d) generations are present in the LL caches313and323, and thus a memory state different for each generation may be maintained. While the generation is not updated, the access to the memory330or340is access to the same address of the LL cache313or323; and

(e) by designating the generations and executing commitment in regard to information on the LL caches313and323, information regarding the designated generations in the LL caches313and323is reflected to the memory330or340.

In the delay system calculator400, provisional calculation reproduction is executed to correspond to the provisional calculation. Further, in the delay system calculator400, calculation reproduction is executed to correspond to the calculation in the normal mode.

For this reason, for example, the LL caches313and323in the CPUs310and320stores a generation management table, as illustrated inFIG. 25. In the example ofFIG. 25, the generation management table includes identification information of the generation and the execution sequence number at the time of generation updating. As will be described below, the generation is updated when the synchronization confirmation point and the output request are detected and the output is actually executed.

The LL cache313or323maintains data, for example, as illustrated inFIG. 26. In the example ofFIG. 26, a value, a corresponding address in the memory330or340, and a generation are stored for each buffer address.

When commitment of the provisional calculation designated by the execution sequence number is instructed from the control unit353, data of the corresponding generation is written on the memory330or340from the LL cache313or323. In the examples ofFIGS. 25 and 26, when commitment of execution sequence numbers 001500 to 003000 is instructed, the commitment is made with generation “2.” Therefore, “2” of address A and “3” of address B are written on the memory330or340.

In the embodiment, the control units353and453manage a group correspondence table illustrated inFIG. 27. In the embodiment, the execution sequence number at the time of the output request, the ID (group ID) of a group of the cores executing the output request, the ID (core ID) of the core affiliated to the group, and the execution sequence number at the time of output are registered. In the example ofFIG. 27, it is indicated that on the assumption that the output have already been executed actually in the first line, but the output request is detected in the second line, the execution sequence number at the time of the output request, the group ID, and the core ID are registered.

The control unit353in the precedence system calculator300includes a group correspondence table3531, a group management unit3532, a core execution control unit3533, and an output mode processing unit3534, as illustrated inFIG. 28. The group management unit3532and the core execution control unit3533have the same functions as the group management unit and the core execution control unit in the first embodiment. The output mode processing unit3534executes processes related to the output mode and the provisional calculation.

The control unit453in the delay system calculator400includes a group correspondence table4531, a core execution control unit4532, a comparison unit4533, and an output mode processing unit4534, as illustrated inFIG. 29. The core execution control unit4532and the comparison unit4533have the same functions as the core execution control unit and the comparison unit in the first embodiment. The output mode processing unit4534executes processes related to the output mode and the provisional calculation reproduction.

Next, process content according to the embodiment will be described with reference toFIGS. 30 to 50.

First, the CPUs310and320and the control unit353in the precedence system calculator300execute a process for initialization (S201inFIG. 30). This process is the same as the initialization process in the first embodiment. Data of the memory, data of the cache, and a register value are copied from the precedence system calculator300to the delay system calculator400, and the group correspondence table3531of the precedence system calculator300is copied to the delay system calculator400. Initially, no output group is present in the group correspondence table3531. Therefore, an empty group correspondence table is copied to the delay system calculator400.

When a current process is in the normal mode (Yes route in S203), the CPUs310and320in the precedence system calculator300execute normal calculation (S207). Since the normal calculation is the same as that of the related art, the normal calculation will not be described. Initially, the normal calculation is executed.

Conversely, when the current process is in the output mode (No route in S203), the CPUs310and320in the precedence system calculator300execute the provisional calculation (S205). The provisional calculation is calculation which is executed by only the cores affiliated to the calculation group and on which direct writing on the memory330or340is not executed. The provisional calculation will be described with reference toFIG. 31.

The cores (at least one of the cores311aand311band the cores321aand321b) of the CPUs310and320execute predetermined calculation (S231inFIG. 31).

When reading from the memory330or340is generated during the calculation (Yes route in S233), the cores of the CPUs310and320determine whether the buffer of a current generation having the corresponding address is present in the LL cache313or323(S243). When the buffer of the current generation having the corresponding address in the LL cache313or323is not present, the cores of the CPUs310and320read the value from the memory330or340(S247). Conversely, when the buffer of the current generation having the corresponding address in the LL cache313or323is present, the cores of the CPUs310and320read the value of the buffer of the current generation from the LL cache313or323(S245).

Conversely, when the reading from the memory330or340is not generated during the calculation (No route in S233) and writing on the memory330or340is generated (Yes route in S235), the cores of the CPUs310and320determine whether the buffer of the current generation having the corresponding address is present in the LL cache313or323(S237). When the writing on the memory330or340is not generated (No route in S235), the process returns to the calling original process.

When the buffer of the current generation having the corresponding address is not present in the LL cache313or323, the cores of the CPUs310and320generate a buffer region for the writing of this time in the LL cache313or323(S239). Then, the process proceeds to S241.

When the buffer of the current generation having the corresponding address is present in the LL cache313or323, the cores of the CPUs310and320execute writing on the buffer of the current generation in the LL cache313or323(S241).

These processes are repeated so as to avoid that the result of the writing on the memory330or340corresponding to the output to the IO spaces by the cores of the CPUs310and320is updated carelessly.

The description returns to the description of the process ofFIG. 30. When the access extraction unit351detects the access to the memory330or340via the QPI bus380(Yes route in S209), the access extraction unit351notifies the control unit353of the access to the memory330or340(S211). The control unit353is notified of the IDs of the cores executing the access and access content.

The control unit353receives the access notification to the memory330or340from the access extraction unit351(S213). Accordingly, the control unit353records the access to the memory and executes the transfer process (S215). This process will be described with reference toFIG. 32.

The control unit353grants an execution sequence number to the data of the access to the memory to generate a journal file and stores the journal file in the access history storage unit352(S251inFIG. 32).

The control unit353transmits the generated journal file to the delay system calculator400(S253). Then, the process returns to the calling original process.

The description returns to the description of the process ofFIG. 30. The control unit353notifies the access extraction unit351of the reception completion after receiving the notification of the access to the memory (S217). On the other hand, the access extraction unit351receives the notification of the reception completion from the control unit353(S219).

After S219or when the access to the memory330or340is not detected (No route in S209) and when no output command is generated (No route in S221), the process proceeds to the process ofFIG. 39via a terminal F.

Conversely, when the output command is generated (Yes route in S221), writing on the LL cache313or323or the memory330or340is executed. Therefore, the data (output content and the IDs of the cores generating the output command) of the output command is output to the control unit353via the QPI bus380(S223). The control unit353receives the data of the output command by the CPUs310and320via the QPI bus380(S225). Then, the process proceeds to the process ofFIG. 33via a terminal E.

The description of the process ofFIG. 33will proceed, the control unit353executes a state acquisition process after the terminal E (S261). The state acquisition process will be described with reference toFIG. 34.

First, the core execution control unit3533of the control unit353issues a stop command for the cores to the CPUs310and320(S281inFIG. 34). The cores of the CPUs310and320stop the cores in response to the stop command for the cores from the control unit353(S283) and notify the control unit353of the stop of the cores (S285).

The core execution control unit3533of the control unit353receives the notification of the stop of the cores from the CPUs310and320(S287). Then, the control unit353issues an acquisition command for the register value and the changed address and value (referred to as a memory state) of the memory to the cores of the CPUs310and320(S289). The cores of the CPUs310and320read the register value and the memory state in response to the acquisition command and output the register value and the memory state to the control unit353(S291).

The control unit353receives data of the register value and the memory state from the CPUs310and320and grants the execution sequence number at the current time point (S293). The process returns to the process ofFIG. 33.

The description returns to the description of the process ofFIG. 33. The group management unit3532of the control unit353executes an updating process for the group correspondence table (S263). The updating process for the group correspondence table will be described with reference toFIG. 35.

First, when the output command is detected (Yes route in S301), the group management unit3532of the control unit353generates a unique ID as a group ID (S303). For example, a number may be issued in serial. The group management unit3532executes updating so that data of the output group including the execution sequence number at the time of the generation of the output command, the generated group ID, and the IDs of the cores issuing the output command are registered in the group correspondence table3531(S305).

The group management unit3532transmits the data of the group correspondence table after the updating to the delay system calculator400(S309).

On the other hand, the control unit453of the delay system calculator400receives the data of the group correspondence table after the updating (S311) and updates the group correspondence table4531in the delay system calculator400based on the received data of the group correspondence table (S313).

Conversely, when the output command is not detected (No route in S301), the output process is executed by the output command. Therefore, the group management unit3532executes updating so that the execution sequence number at the time of the execution of the output process is set in the group related to the output (S307). Then, the process proceeds to S309.

In this way, the group correspondence table of the delay system calculator400is synchronized with the group correspondence table of the precedence system calculator300.

To return to the description of the process ofFIG. 33, the control unit353executes an activation process for the non-output cores (S265). The activation process for the non-output cores will be described with reference toFIG. 36.

The core execution control unit3533of the control unit353specifies the cores scheduled to execute the output command from the group correspondence table3531(S321inFIG. 36). As illustrated inFIG. 27, since only the IDs of the cores issuing the output command are registered in the group correspondence table3531according to the embodiment, the IDs of the cores affiliated to the group in which the output is not completed are specified.

The core execution control unit3533of the control unit353specifies the cores of the calculation group including the cores other than the specified cores (S323). Thereafter, the core execution control unit3533of the control unit353outputs an activation command for the calculation group (including the core IDs) to the CPUs310and320(S325).

On the other hand, the CPUs310and320receive the activation command for the calculation group (S327). Then, the CPUs310and320activate the cores stopped in the calculation group (S329). In this way, the cores executing the following provisional calculation enter an activation state. Then, the process returns to the calling original process.

The description returns to the description of the process ofFIG. 33. The control unit353determines whether the current mode is the output mode (S267). Initially, the mode is a standard mode. When the current mode is the standard mode, the control unit353executes a mode switching process of switching the mode to the output mode (S269). The mode switching process will be described with reference toFIG. 37.

The control unit353notifies the CPUs310and320of mode switching to a specific mode (for example, the output mode) (S331). On the other hand, the CPUs310and320receives the notification of the mode switching to the specific mode (S333).

The description returns to the description of the process ofFIG. 33. When the current mode is output mode, the control unit353executes the generation updating process of the buffer (S271). The generation updating process of the buffer will be described with reference toFIG. 38.

First, the control unit353issues a generation updating command including the current execution sequence number to the CPUs310and320(S341). On the other hand, the CPUs310and320receive the generation updating command including the current execution sequence number (S343).

Then, the CPUs310and320record the generation management table (seeFIG. 25) as the execution sequence number (the execution sequence number at the time of the end of the current generation) at the time of the updating the received execution sequence number and generates a new generation (S345). The CPUs310and320output generation updating notification to the control unit353(S347).

The control unit353receives the generation updating notification from the CPUs310and320(S349). Then, the process returns to the calling original process.

In this way, the data management in the LL caches313and323of the CPUs310and320is changed.

The description returns to the description of the process ofFIG. 33. The control unit353transmits the execution sequence number, the register value of each core, the memory state, and the output content to the delay system calculator400(S273).

The process at the time of the detection of the output command temporarily ends and the process returns to the process of S203ofFIG. 30via the terminal D.

Conversely, when the output command is not generated in S221ofFIG. 30, the process ofFIG. 39is executed via the terminal F. That is, the control unit353counts the number of executions of an IF command (S351).

The control unit353determines whether a condition of the synchronization confirmation in which the number of executions of the IF command reaches a predetermined number of times is satisfied (S353). When the condition of the synchronization confirmation is not satisfied, the process returns to S203ofFIG. 30via the terminal D.

Conversely, when the condition of the synchronization confirmation is satisfied, the control unit353executes a state acquisition process (S355). This process is the same as the process described inFIG. 34.

Thereafter, the control unit353executes the activation process of the non-output cores (S357). This process is the same as the process described inFIG. 36.

When the current mode is the output mode, the control unit353executes the generation updating process of the buffer (S361). This process is the process described inFIG. 38. Conversely, when the current mode is not the output mode, the process proceeds to S363.

The control unit353transmits the execution sequence number, the register value of each core, and the memory state to the delay system calculator400(S363). Then, the process returns to S203ofFIG. 30via the terminal D.

In this way, even when the output command is not issued, data regarding the synchronization confirmation point is transmitted to the delay system calculator400.

Next, a process executed after the comparison result of the calculation results for the calculation reproduction or the provisional calculation reproduction is received from the delay system calculator400will be described with reference toFIGS. 40 and 41.

The control unit353of the precedence system calculator300receives the comparison result including the execution sequence number at the time of the issuing of the output command or the synchronization confirmation point from the delay system calculator400(S401). When the comparison result indicates that non-matching of the register values or the output values is detected, the process abnormally ends. Therefore, in the embodiment, the description will be omitted. That is, in the following process, a case in which the comparison result indicates that the register values and the output values match will be described.

Then, based on the group correspondence table3531and the execution sequence number in the comparison result, the control unit353determines whether a section is a section in which the output command is generated (S403). The execution sequence number at the time point at which the output command is generated is registered in the group correspondence table3531. Therefore, to determine the section, it is determined whether the execution sequence number matching the execution sequence number in the comparison result is registered in the group correspondence table3531. When the section is a section in which the output command is not generated, the process returns to S203ofFIG. 30via the terminal D.

Conversely, when the section is the section in which the output command is generated, the control unit353executes an output process to the external device370based on the data such as the estimated output value stored in the memory330or340(S405).

The control unit353executes the updating process for the group correspondence table (S407). The updating process is the same as the process ofFIG. 35.

The control unit353executes a state acquisition process (S408). The state acquisition process is the same as the process ofFIG. 34.

The control unit353executes an activation process of the non-output cores (S409). The activation process of the non-output cores is the same as the process ofFIG. 36.

The control unit353executes commitment of the provisional calculation (S411). The commitment of the provisional calculation will be described with reference toFIG. 41.

First, the output mode processing unit3534of the control unit353specifies a commitment section from the group correspondence table3531(S421). The output mode processing unit3534specifies a section (the execution sequence numbers at the time of start and end) from the time of the issuing of the output command for the output process to the external device370executed immediately before S421to the time of the issuing of a subsequent output command. Then, the output mode processing unit3534of the control unit353notifies the CPUs310and320of the commitment section (S423).

On the other hand, the CPUs310and320receive the notification of the commitment section from the control unit353(S425). Then, the CPUs310and320specify the generation in the notified section from the generation management table (S427).

Then, the CPUs310and320specify the unexecuted generation among the generations in the notified section (S429). The CPUs310and320determine whether conflict occurs in the specified generations (S431). For example, when access including writing on the same memory address in a plurality of transactions occurs and there is a possibility of deadlock, it is determined that the conflict occurs.

When there is the conflict, the CPUs310and320abort the provisional calculation in this section (S433). Therefore, the process proceeds to S439.

Conversely, when there is no conflict, the CPUs310and320reflect the changed data stored in the buffer (LL cache313or323) for the specified generation to the memory330or340(S435).

The CPUs310and320determine whether there is an unexecuted generation among the generations in the notified section (S437). When there is the unexecuted generation, the process returns to S429.

Conversely, when there is no unexecuted generation, the CPUs310and320notify the control unit353of the process result (S439). The output mode processing unit3534of the control unit353receives the notification of the process result (S441). Then, the process returns to the calling original process.

This process is executed in the delay system calculator400. However, when abortion occurs, the process abnormally ends (ABEND). When the abortion occurs, the provisional calculation executed in the commitment section is executed again. Therefore, the process of initializing the precedence system calculator300and the delay system calculator400is resumed with the memory state and the register value at the time of start of the provisional calculation. Hereinafter, a commitment succession case will be described.

The description returns to the description of the process ofFIG. 40. The control unit353executes the generation updating process of the buffer (S413). This process is the same as the process ofFIG. 38.

The control unit353transmits the commitment result to the delay system calculator400(S415). The commitment result includes the data of the execution sequence number in S408, the execution sequence number of the commitment section, and the register value and the memory state of each core.

The control unit353determines whether there is an unexecuted output command from the group correspondence table3531(S417). When there is the unexecuted output command, the output mode is maintained. Therefore, the process returns to S203ofFIG. 30via the terminal D. Conversely, when there is no unexecuted output command, the control unit353executes the mode switching process to the normal mode (S419). This process is the same as the process ofFIG. 37. Then, the process returns to S203ofFIG. 30via the terminal D.

In this way, the memories330and340are updated with the data in the LL caches313and323used as the buffers according to the output process, and the generations are updated.

Here, data transition related to the commitment of the provisional calculation will be described with reference toFIGS. 42A and 42B. As illustrated on the right side ofFIG. 42A, when the cores1to4execute calculation in the normal mode, the cores1and2issue output command1(point A). Up to here, writing on the memories330and340is executed and the value output by the output command is also written on the memory330or340.

The cores3and4execute the provisional calculation. Thereafter, the core3issues output command2(point B). The core4executes the provisional calculation. Thereafter, the comparison result (the result of the calculation reproduction up to the point A) may be obtained from the delay system calculator400(point C). Then, the output process by output command1is executed. Thereafter, the commitment up to output command2is executed in accordance withFIG. 41. Black horizontal lines inFIG. 42Aare assumed to indicate synchronization confirmation points.

In this example, at the point A, a first output group (the cores1and2) and the execution sequence number at the point A are registered in the group correspondence table3531. At this time point, recording on the LL caches313and323used as the buffers starts. At a subsequent synchronization confirmation point, the generations are updated. At the point B, a second output group (the core3) and the execution sequence number at the point B are additionally registered in the group correspondence table3531.

At output point1(the point C) at which the output command is executed, the execution sequence number at the point C is registered as the execution sequence number at the time of the output process in the group correspondence table3531in regard to the first output group.

In the commitment up to output command2, the commitment is executed in the section of the points A to B. This situation will be described with reference toFIG. 42B. In the drawing, time is assumed to flow from the upper side to the lower side. In the buffers (the LL cache313and323) and the memories330and340, addresses0to3are assumed to be present. Each line of the buffer indicates the generation.

The buffer is not used up to the point A and the writing on the memories330and340is executed. The memories330and340are not updated from the point A and recording on the buffer is executed. “X” is written on buffer “3” as the first generation, “Y” is written on buffer “3” as the second generation, “Y” is written on buffer “2” as the third generation, and “Z” is written on buffer “3.” The first to third generations are included between the points A and B but the fourth to sixth generations are present up to the point C.

When the commitment is executed, the section from the point A to the point B is committed. Therefore, the generations up to the third generation are written on the corresponding addresses of the memories330and340. In the example ofFIG. 42B, “Y” is written on memory “2” and “Z is written on memory “3.” Memories “0” and “1” are not changed.

In this way, only the committed data are reflected from the buffers to the memories.

Next, process content in the delay system calculator400of the side receiving the data in the above-described process will be described with reference toFIGS. 43 to 50.

First, the control unit453of the delay system calculator400is in reception standby of the data from the precedence system calculator300(S501). Thereafter, the control unit453receives the data from the precedence system calculator300(S503). The data is received when (A) the execution sequence number, the register value of each core, and the memory state are received, when (B) the execution sequence number, the register value of each core, the memory state, and the output content are received, when (C) the journal file including the execution sequence number is received, and when (D) the execution sequence number, the execution sequence number indicating the commitment section, the register value of each core, and the memory state are received. The output content is included when the output command is issued. The journal file is transmitted at each time. When (A) the execution sequence number, the register value of each core, and the memory state are received, the data is transmitted at the time of the updating of the generation.

Next, the control unit453determines, from the group correspondence table4531, whether the section specified from the execution sequence number included in the received data is in the normal mode (S505). When the execution sequence number at the time of the output process is registered in a certain output group in the group correspondence table4531, the mode is determined as the normal mode.

When the mode is the normal mode, the control unit453executes the mode switching process to the normal mode (S507). This process is the same as the process ofFIG. 37.

The control unit453determines whether the condition of the calculation reproduction execution is satisfied (S509). Specifically, the condition is set in which the calculation reproduction in the section previous to the reproduced section is completed and the following data is provided:

1. the journal file in the section;

2. data of the register value of each core and the memory state at the time of start of the section;

3. data of the register value of each core and the memory state at the time of end of the section; and

4. output content when there is the output command.

The section is regulated from a specific execution sequence number to another specific execution sequence number and is regulated from the final execution sequence number of the section in which the synchronization is completed to the execution sequence number at a timing at which subsequent synchronization is executed due to non-completion of the synchronization. As described in the example according to the first embodiment, the understanding is easy when an interval at the time of the issuing of the output command, an interval at the time of the completion of the comparison, or an interval between the time of the issuing of the output command and the completion of the comparison is assumed.

When the condition of the calculation reproduction execution is satisfied, the control unit453and the like execute the calculation reproduction (S511). The calculation reproduction will be described with reference toFIG. 44. The process after S511proceeds to a process ofFIG. 49via a terminal G.

The control unit453issues an initialization command to initialize registers to values at the time of start of the section to the CPUs410and420(S531inFIG. 44). The CPUs410and420update the registers to the values at the time of the start of the section in response to the initialization command (S533). The CPUs410and420reply to the control unit453with update completion notification (S535). On the other hand, the control unit453receives the update completion notification (S537).

The core execution control unit4532of the control unit453issues an activation command for the cores (S539). Because of the normal mode, all of the cores are activated. The CPUs410and420activate the cores in response to the activation command (S541). Then, the CPUs410and420execute predetermined calculation by the cores (S543).

When reading from the memory430or440is generated in the calculation (Yes route in S545), the access extraction unit451detects access to the memory430or440and outputs access notification to the memory430to440to the control unit453(S547). On the other hand, the control unit453rewrites an estimated read value to data of the journal file specified based on the current execution sequence number and stored in the access history storage unit452according to the reception of the access notification (S549).

Then, the CPUs410and420actually execute the reading from the memory (S551). A subsequent process proceeds to a process ofFIG. 45via a terminal J. When the reading from the memory is not detected (No route in S545), the process also proceeds to the process ofFIG. 45via the terminal J.

The description will proceed to the description of the process ofFIG. 45. When the output command to the external device470is generated (Yes route in S553), the output content is output to the control unit453via the QPI bus480(S555). The control unit453receives the output content from the CPUs410and420(S557). Then, the process returns to the calling original process.

When the output command to the external device470is not generated (No route in S553) and the calculation corresponding to the section does not end (No route in S559), the process returns to S543ofFIG. 44via a terminal K. Conversely, when the calculation corresponding to the section ends (Yes route in S559), the process returns to the calling original process. In this way, the calculation reproduction is executed.

The description returns to the description of the process ofFIG. 43. When the current mode is determined to be output mode in S505(No route in S505), the control unit453executes the mode switching process to the output mode (S513). This process is the same as the process ofFIG. 37.

Thereafter, the control unit453determines whether the provisional calculation reproduction of the target section is completed (S515). When the provisional calculation reproduction of the target section is not completed, the process proceeds to S521. Conversely, when the provisional calculation reproduction of the target section is completed, the output mode processing unit4534of the control unit453determines whether the memory state at the time of the end of the section is received (S517). When the memory state at the time of the end of the section is not obtained, the process returns to S501. Conversely, when the memory state at the time of the end of the section is received, the control unit453and the like execute the commitment of the section (S519). This process will be described with reference toFIG. 48. Then, the process proceeds to the process ofFIG. 49via a terminal G.

When the provisional calculation reproduction of the target section is not completed, the control unit453determines whether the condition of the provisional calculation reproduction is satisfied (S521). Specifically, the condition is set in which the calculation reproduction or the provisional calculation reproduction in the section previous to the reproduced section and the commitment are completed and the following data is provided:

1. the journal file in the section;

2. the register value of each core affiliated to the calculation group at the time of start of the section;

3. the register value of each core affiliated to the calculation group at the time of end of the section; and

4. output content when there is the output command.

When the condition of the provisional calculation reproduction is not satisfied, the process returns to S501. Conversely, when the condition of the provisional calculation reproduction is satisfied, the control unit453and the like execute the provisional calculation reproduction (S523). The provisional calculation reproduction will be described with reference toFIGS. 46 and 47.

The output mode processing unit4534of the control unit453specifies the cores affiliated to the calculation group in the target section with reference to the group correspondence table4531(S561inFIG. 46). The cores not affiliated to the output group are the cores affiliated to the calculation group.

The output mode processing unit4534of the control unit453issues an initialization command to initialize the registers of the specified cores to the values at the time of start of the section to the CPUs410and420(S563). The CPUs410and420update the registers of the specified cores to the values at the time of start of the section in response to the initialization command (S565). The CPUs410and420reply to the control unit453with update completion notification (S567). On the other hand, the control unit453receives the update completion notification (S569).

The output mode processing unit4534of the control unit453issues an activation command for the cores affiliated to the calculation group (S571). Then, the CPUs410and420activate the cores affiliated to the calculation group in response to the activation command (S573). Then, the CPUs410and420execute predetermined calculation by the cores affiliated to the calculation group (S575).

When reading from the memory430or440is generated in the calculation (Yes route in S577), the access extraction unit451detects reading and outputs access notification to the memory430to440to the control unit453(S579). On the other hand, the control unit453rewrites an estimated read value to data of the journal file specified based on the current execution sequence number and stored in the access history storage unit452according to the reception of the access notification (S581).

Then, the CPUs410and420actually execute the reading from the memory (S583). A subsequent process proceeds to a process ofFIG. 47via a terminal L. When the reading from the memory is not detected (No route in S577), the process also proceeds to the process ofFIG. 47via the terminal L.

The description of the process ofFIG. 47will proceed. When writing on the memory430or440is generated (Yes route in S585) and the access extraction unit451detects the writing, the access extraction unit451causes the CPUs410and420to cancel the writing (S587). Then, the process proceeds to S589. When the writing on the memory430or440is not generated (No route in S585), the process proceeds to S589.

When the output command to the external device470is generated (Yes route in S589), the output content is output to the control unit453via the QPI bus480(S591). The output mode processing unit4534of the control unit453receives the output content from the CPUs410and420(S593). Then, the process returns to the calling original process.

When the output command to the external device470is not generated (No route in S589) and the calculation corresponding to the section does not end (No route in S595), the process returns to S575ofFIG. 46via a terminal M. Conversely, when the calculation corresponding to the section ends (Yes route in S595), the process returns to the calling original process.

In this way, the provisional calculation reproduction is executed. In the delay system calculator400, unlike the precedence system calculator300, another calculation reproduction or provisional calculation reproduction starts after the provisional calculation reproduction, the commitment, and the output process are continuously executed. Therefore, the writing on the memories430and440is not controlled using the LL caches413and423as the buffers.

The description returns to the description of the process ofFIG. 43. The output mode processing unit4534of the control unit453determines whether the memory state at the time of the end of the section is received (S525). When the memory state at the time of the end of the section is not obtained, the process returns to S501.

Conversely, when the memory state at the time of the end of the section is received, the control unit453and the like execute the commitment of the section (S527). The commitment of the section will be described with reference toFIG. 48. Then, the process after S527proceeds to the process ofFIG. 49via the terminal G.

First, the output mode processing unit4534of the control unit453specifies a commitment section from the group correspondence table4531(S651). The output mode processing unit4534specifies a section (the execution sequence numbers at the time of start and end) from the time of the issuing of the output command for the output process to the external device470executed immediately before S651to the time of the issuing of a subsequent output command. Then, the output mode processing unit4534of the control unit453specifies the journal file included in the specified section and notifies the CPUs410and420of the commitment section and the journal file included in the section (S653). When the generation is updated, as described above, the data notified of by the precedence system calculator300is present and the generation is also specified. Therefore, information regarding the generation is added to the notified journal file.

On the other hand, the CPUs410and420receive the commitment section and the journal file of the section from the control unit453(S655). Then, the CPUs410and420specify the generation in the notified section from the received data (S657).

The CPUs410and420specify the unexecuted generation among the generations in the notified section (S659). The CPUs410and420determine whether conflict occurs in the specified generations (S661). At this time, the CPUs410and420determines there is the conflict using the latest journal file in the specified generation rather than the data of the LL caches413and423. That is, when access including writing on the same memory address in a plurality of transactions occurs and there is a possibility of deadlock, it is determined that the conflict occurs.

When there is the conflict, the CPUs410and420aborts the provisional calculation reproduction in this section (S663). Therefore, the process proceeds to S669.

Conversely, when there is no conflict, the CPUs410and420reflect the content of the journal file to the memory430or440(S665).

The CPUs410and420determine whether there is an unexecuted generation among the generations in the notified section (S667). When there is the unexecuted generation, the process returns to S659.

Conversely, when there is no unexecuted generation, the CPUs410and420notify the control unit453of the process result (S669). The output mode processing unit4534of the control unit453receives the notification of the process result (S671). Then, the process returns to the calling original process.

The description will proceed to the description of the process ofFIG. 49. The control unit453and the like execute the updating process for the memory state (S601inFIG. 49). This process will be described with reference toFIG. 50.

First, the control unit453instructs the CPUs410and420to execute overwriting on the memories430and440in the memory state in the execution sequence number at the time of the end of the section (S621). On the other hand, the CPUs410and420execute the overwriting of the memory state in response to the instruction (S623). It is beneficial to synchronize the precedence system calculator300and the memories. Then, the process returns to the calling original process.

The control unit453executes a state acquisition process (S603). The state acquisition process is the same as the process ofFIG. 34.

The control unit453executes a comparison process on the calculation results (the register values and the output content when the output command is generated, but only the cores of the calculation group in the case of the output mode) (S605). The control unit453determines whether the register values match or the estimated output values match.

When it is indicated that the calculation results do not match each other (No route in S607), the control unit453executes a pre-decided abnormality handling process (S609). Then, the process ends.

When it is indicated that the calculation results match each other (Yes route in S607), the control unit453determines whether the output command is generated (S611). When the output command is generated, an output process to the external device470is executed (S613). Conversely, when the output command is not generated, the process proceeds to S615.

The control unit453transmits the comparison result of S605to the precedence system calculator300(S615). Then, the process returns to S501via a terminal H.

By executing such processes, it is possible to progress the calculation efficiently while verifying the comparison of the calculation results of the precedence system calculator300in the delay system calculator400.

An example of the synchronization process executed by the precedence system calculator300and the delay system calculator400is illustrated inFIG. 51. InFIG. 51, time flows from the upper side to the lower side.

In the example ofFIG. 51, in the precedence system calculator300, the data transition until “commitment up to output command2” is the same as that described with reference toFIG. 42A. After “commitment up to output command2,” the commitment section and the register values are transmitted from the precedence system calculator300to the delay system calculator400.

Even when “commitment up to output command2” is executed in the precedence system calculator300, the output process in response to output command2is not executed, and thus the mode remains to be the output mode. However, since the output of output command1is executed for the cores1and2, the provisional calculation by the cores1,2, and4is executed.

On the other hand, in the delay system calculator400, the calculation reproduction is executed, the register value and the estimated output value are compared, and the comparison result at the point A is transmitted to the precedence system calculator300. When the comparison result indicates matching, an output process in response to output command1is subsequently executed. Then, the provisional calculation reproduction is executed for the provisional calculation executed by the cores3and4of the precedence system calculator300. The provisional calculation reproduction is executed at a time point at which the data other than the memory state is provided, as described above.

In the delay system calculator400, the commitment up to output command2is executed when the provisional calculation reproduction corresponding to the provisional calculation up to the point B is completed, the commitment is executed in the precedence system calculator300, and the memory state is acquired. When the commitment is completed, the register value and the estimated output value are compared and the comparison result is transmitted from the delay system calculator400to the precedence system calculator300. When the comparison result indicates that the resister value and the estimated output value match each other, the output process in response to output command2is executed.

In the precedence system calculator300, the output process in response to output command2is executed when the comparison result is received and the comparison result indicates the matching. The group correspondence table3531is updated and the execution sequence number (point D) at the time of the output process of the second output group is registered. In the precedence system calculator300, the commitment is executed up to output point1. Then, the commitment section and the register value are transmitted from the precedence system calculator300to the delay system calculator400. Thereafter, the commitment of the provisional calculation up to output point2is also executed. At each commitment, the commitment section and the register value are transmitted from the precedence system calculator300to the delay system calculator400.

Thereafter, since the unexecuted output process is not present, the precedence system calculator300returns to the normal mode and executes the calculation by the cores1to4.

When the previous provisional calculation reproduction is committed, the provisional calculation reproduction of the provisional calculation executed by only the core4is executed in the delay system calculator400. When the provisional calculation reproduction is completed, the commitment (commitment up to output point1) of the provisional calculation reproduction is executed. Then, in the delay system calculator400, the provisional calculation reproduction is executed for the provisional calculation executed by the cores1,2, and4. When the provisional calculation reproduction is completed, the commitment (commitment up to output point2) of the provisional calculation reproduction is executed. When the commitment is completed, the mode returns to the normal mode and the calculation reproduction is executed.

In this way, various provisional calculations are executed so that a standby time is lost as less as possible in the precedence system calculator300. The corresponding provisional calculation reproduction is also executed in sequence in the delay system calculator400.

The embodiments of the disclosure have been described above, but the technology is not limited thereto. For example, the processing flows may be shifted in the order of the processes or may be executed in parallel a plurality of times as long as the processing results are not changed.

The functional block diagrams are merely examples and do not match program module configurations in some cases.

The above-described embodiments may be summarized as follows.

The information processing system according to the embodiments includes: a first system that includes a plurality of first arithmetic units, a first control unit, and a first external device; and a second system that includes a plurality of second arithmetic units, a second control unit, and a second external device and that executes calculation which is the same as calculation executed in the first system and compares calculation results to each other. The first control unit (A) stops, when the first control unit detects that a first output request to the first external device is output from one or plural first arithmetic units among the plurality of first arithmetic units, first arithmetic units including the one or plural first arithmetic units that were executing first calculation, (B) transmits first comparison target data including a value output with the first output request to the second control unit, and (C) causes the first arithmetic units other than the one or plural first arithmetic units among the first arithmetic units that were executing the first calculation to execute second calculation. The second control unit (D) causes second arithmetic units corresponding to the first arithmetic units that were executing the first calculation to execute third calculation corresponding to the first calculation when the second control unit receives the first comparison target data from the first control unit, and (E) compares the first comparison target data to second comparison target data including a value output with a second output request when the second control unit detects that the second output request to the second external device is output from one or plural second arithmetic units among the second arithmetic units corresponding to the first arithmetic units that were executing the first calculation.

In this way, the second calculation is executed rapidly and effective use of the arithmetic units in the system may be achieved.

The above described first control unit may transmit information for specifying the first arithmetic units that execute the first calculation in advance to the second control unit. In this case, the second control unit may specify the second arithmetic units corresponding to the first arithmetic units that were executing the first calculation based on the information. In this way, the same calculation as the first calculation is executed by the second arithmetic units.

More specifically, the above-described first control unit (F) may transmit information for specifying the first arithmetic units that execute the second calculation to the second control unit, (G) may stop the first arithmetic units that were executing the second calculation when the first control unit detects that a third output request to the first external device is output from a certain first arithmetic unit among the first arithmetic units that were executing the second calculation, (H) may transmit third comparison target data including a value output with the third output request to the second control unit, and (I) may cause the first arithmetic units other than the certain first arithmetic unit among the first arithmetic units that were executing the second calculation to execute the third calculation. The above-described second control unit (3) may receive the information from the first control unit, (K) may specify and cause the second arithmetic units that execute fourth calculation corresponding to the second calculation to execute the fourth calculation based on the information when the second control unit receives the third comparison target data from the first control unit, and (L) may compare the third comparison target data to fourth comparison target data including a value output with a fourth output request when the second control unit detects that the fourth output request to the second external device is output from a certain second arithmetic unit among the specified second arithmetic units.

In this way, the calculation reproduction is executed in the second system with the same configuration as the first system.

The information for specifying the first arithmetic units that execute the second calculation may include an identifier of the one first arithmetic unit or identifiers of plural first arithmetic units. In contrast, the information may include an identifier of the first arithmetic unit that output the output request.

The above-described first system may include a first virtual machine including the plurality of first arithmetic units, a second virtual machine including the first control unit, and a first management unit managing the first virtual machine and the second virtual machine. In this case, the above-described second system may include a third virtual machine including the plurality of second arithmetic units, a fourth virtual machine including the second control unit, and a second management unit managing the third virtual machine and the fourth virtual machine. The mounting manner may be modified in various ways.

The above-described first control unit may retain the value output with the first output request. In this case, the above-described second control unit may transmit a comparison result to the first control unit. Further, the first control unit may output the retained value to the first external device when the comparison result received from the second control unit indicates that the first comparison target data matches the second comparison target data. When the value to be output may be retained by the first control unit, such a process is executed.

On the other hand, the above-described first system includes a first memory shared by the plurality of first arithmetic units, a first buffer retaining data before reflected to the first memory in some cases. In this case, the one or plural first arithmetic units may write the value output with the first output request on the first memory. The first arithmetic units other than the one or plural first arithmetic units among the first arithmetic units that were executing the first calculation may write data in the second calculation on the first buffer. When the above-described second control unit transmits a comparison result to the first control unit, the first control unit may receive the comparison result from the second control unit, output the value written on the first memory to the first external device when the comparison result received from the second control unit indicates that the first comparison target data matches the second comparison target data, and cause the plurality of first arithmetic units to determine whether the writing on the first buffer conflicts and reflects a writing result on the first buffer to the first memory when it is determined that the writing on the first buffer does not conflict.

When a value to be output is not retained, this configuration is adopted in the first control unit, thereby obtaining the same operational effects.

The above-described first control unit may transmit information for specifying the first arithmetic units that execute the second calculation to the second control unit, transmit data written on the first buffer by the first arithmetic units that are executing the second calculation to the second control unit, stop the first arithmetic units that were executing the second calculation when the first control unit detects that a third output request to the first external device is output from a certain first arithmetic unit among the first arithmetic units that were executing the second calculation, and transmit third comparison target data including a value output with the third output request to the second control unit. In this case, the second control unit may receive the information and the data written on the first buffer from the first control unit, specify and cause the second arithmetic units that execute fourth calculation corresponding to the second calculation to execute the fourth calculation based on the information when the second control unit receives the third comparison target data from the first control unit, compare the third comparison target data to fourth comparison target data including a value output with a fourth output request when the second control unit detects that the fourth output request to the second external device is output from a certain second arithmetic unit among the specified second arithmetic units, cause the certain second arithmetic unit to output the value output with the fourth output request to the second external device when a result of the comparison indicates that the third comparison target data matches the fourth comparison target data, and cause the second arithmetic units to determine whether writing conflicts, using the data written on the first buffer.

A program causing a processor to execute the above-described processes may be generated. The program is stored in, for example, a computer-readable storage medium or storage device such as a flexible disk, an optical disc such as a CD-ROM, a magneto-optical disc, a semiconductor memory (for example, a ROM), or a hard disk. Data during a process is temporarily stored in a storage device such as a RAM.