CAPACITOR EMBEDDED SUBSTRATE

A capacitor embedded substrate that can implement low impedance over a wide frequency band and improve heat radiation performance and signal transmission performance at the same time by embedding a plurality of capacitors having different capacitances in a laminated core and connecting the capacitors in parallel.

DETAILED DESCRIPTION OF THE PREFERABLE EMBODIMENTS

Advantages and features of the present invention and methods of accomplishing the same will be apparent by referring to embodiments described below in detail in connection with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. The embodiments are provided only for completing the disclosure of the present invention and for fully representing the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout the specification.

Terms used herein are provided to explain embodiments, not limiting the present invention. Throughout this specification, the singular form includes the plural form unless the context clearly indicates otherwise. When terms “comprises” and/or “comprising” used herein do not preclude existence and addition of another component, step, operation and/or device, in addition to the above-mentioned component, step, operation and/or device.

The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. Objects described herein as being “adjacent to” each other may be in physical contact with each other, in close proximity to each other, or in the same general region or area as each other, as appropriate for the context in which the phrase is used. Occurrences of the phrase “in one embodiment” herein do not necessarily all refer to the same embodiment.

Hereinafter, configurations and operational effects of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1is a view schematically showing a capacitor embedded substrate100in accordance with a first embodiment of the present invention.

The capacitor embedded substrate100in accordance with the first embodiment of the present invention is a substrate in which a plurality of capacitors110,120, and130having different capacitances are embedded.

At this time, the plurality of capacitors110,120, and130may be embedded in an insulating portion140, and although not shown, a core may be provided in one region inside the insulating portion140.

Referring toFIG. 1, the capacitor embedded substrate in accordance with the first embodiment of the present invention may include the insulating portion140, the first to third capacitors110,120, and130, a first conductor pattern150, and a via160.

At this time, the first to third capacitors110,120, and130may have different capacitances.

Further, the first to third capacitors110,120, and130may be connected electrically in parallel by the vias160and the first conductor patterns150.

For example, the capacitance of the first capacitor110may be several to hundreds of pF, the capacitance of the second capacitor120may be several to hundreds of nF, and the capacitance of the third capacitor130may be several to hundreds of uF.

FIG. 4is a view for explaining an impedance reduction effect in accordance with an embodiment of the present invention. Referring toFIG. 4, it is to be understood that the smaller the capacitance of the capacitor, the lower the impedance in a high frequency band.

For example, when the first capacitor110having a capacitance of picofarads, and the second capacitor120having a capacitance of nanofarads, and the third capacitor130having a capacitance of microfarads are connected in parallel, it is possible to exhibit impedance characteristics as shown by the solid line inFIG. 4. Accordingly, it is possible to implement low impedance characteristics over a wider frequency band than the prior art.

Meanwhile, the first to third capacitors110,120, and130may be embedded in the substrate by being provided inside the insulating portion140.

At this time, the first conductor patterns150may be provided on an outer surface of the insulating portion140, and the vias160may be provided between external electrodes of the first to third capacitors110,120, and130and the first conductor patterns150to connect the first to third capacitors110,120, and130electrically in parallel.

FIG. 2is a view schematically showing a capacitor embedded substrate200in accordance with a second embodiment of the present invention.

A repeated description similar to the description of the above-described first embodiment will be omitted.

Referring toFIG. 2, the capacitor embedded substrate200in accordance with the second embodiment of the present invention may consist of a core241and a first build-up layer242and may be implemented by embedding first to third capacitors210,220, and230inside the core241.

At this time, the core241may perform a role of improving heat radiation performance of the capacitor embedded substrate200.

FIG. 3is a view schematically showing a capacitor embedded substrate300in accordance with a third embodiment of the present invention.

A repeated description similar to those of the above-described first and second embodiments will be omitted.

Referring toFIG. 3, the capacitor embedded substrate300in accordance with the third embodiment of the present invention may include a laminated core340, first to third capacitors310,320, and330, a first build-up layer342, a second build-up layer343, and a first conductor pattern351.

First, the laminated core is formed by laminating a plurality of cores341having a core via361on each layer.

In order to minimize warpage due to thermal stress, typically, a core is formed using a material with a coefficient of thermal expansion (CTE) of less than 10 ppm/degree C. However, when processing a material with a low coefficient of thermal expansion using a mechanical drill, a drill blade made of a high strength material is required and processing efficiency is deteriorated.

Considering this problem, laser may be used when processing a core via hole. However, when the core is thick, since the core via hole is processed by irradiating laser to both surfaces of the core, it is common that the core via hole is formed in the shape of a sandglass.

However, in the core via hole processed by laser in the shape of a sandglass, a cross-sectional area of a center portion in the thickness direction of the core is smaller than a cross-sectional area of upper and lower portions of the core via hole. At this time, the cross-sectional area of the upper and lower portions of the core via hold should be proportionally increased to increase the cross-sectional area of the center portion.

Accordingly, in a process of filling the entire inside of the core via hole having a sandglass shape with conductive metal such as copper, there are difficulties in completely filling the inside of the core via hole having a large cross-sectional area.

Further, in this structure, there are additional difficulties in implementing a stack structure (high speed signal transmission structure) between the core vias, thus exerting a bad influence on wiring density.

Therefore, in the core via hole having a sandglass shape, several problems are caused by the increase in the cross-sectional area of the center portion of the thickness direction.

In order to overcome this problem, the capacitor embedded substrate300in accordance with the third embodiment of the present invention can minimize the cross-sectional area of the via which electrically connects between one surface and the other surface of the laminated core340while thickening the laminated core340by laminating the cores341having a predetermined thickness in a plurality of layers in a state in which the core vias361are formed in the cores341.

At this time, the cores341, which form the laminated core340, may have the same thickness or different thicknesses according to the need.

Accordingly, it is possible to improve a signal processing speed by implementing improvement in electrical conductivity as well as improvement in heat radiation performance.

Meanwhile, the first to third capacitors310,320, and330may be embedded in the laminated core340. At this time, a cavity344may be provided to embed at least one of the first to third capacitors310,320, and330in the laminated core340.

Further, the capacitance of the capacitors may be adjusted according to the size of the capacitors. As shown, when the size of the first to third capacitors310,320, and330satisfies the relation: [the first capacitor310<the second capacitor320<the third capacitor330], the capacitance thereof also may satisfy the relation: [capacitance of the first capacitor310<capacitance of the second capacitor320<capacitance of the third capacitor330].

Further, in setting the size and capacitance of the capacitors like this, the thickness of the capacitors may be determined differentially.

Therefore, the number of layers of the cores341positioned in regions vertically above and under the first capacitor310may be greater than the number of layers of the cores341positioned in regions vertically above and under the second capacitor320, and the number of layers of the cores341positioned in the regions vertically above and under the second capacitor320may be greater than the number of layers of the cores341positioned in regions vertically above and under the third capacitor330.

Accordingly, it is possible to improve efficiency of the process of embedding the capacitors in the laminated core340, and it is possible to reduce the size and thickness of the capacitor embedded substrate300by minimizing the space required for embedding the capacitors in the laminated core340.

Meanwhile, the second build-up layer343may be provided on a surface of the laminated core340, and the first build-up layer342may be provided on a surface of the second build-up layer343.

At this time, the second build-up layer343may include a second conductor pattern352and a second build-up via363. The first build-up layer342may include a first build-up via362and the first conductor pattern351may be provided on a surface of the first build-up layer342.

Here, the second build-up layer343may include a glass fiber or a material having a value of coefficient of thermal expansion between a value of coefficient of thermal expansion of the laminated core340and a value of coefficient of thermal expansion of the first build-up layer342.

As the capacitor embedded substrate300is made of materials having different physical properties, such as the laminated core340and the build-up layers342and343, non-uniform expansion and contraction may occur due to thermal impact in the process of manufacturing and using the capacitor embedded substrate300, and cracks may occur on a boundary surface between the laminated core340and the build-up layers342and343due to this phenomenon.

This problem may emerge as a serious problem when the capacitor embedded substrate300becomes slimmer and the configuration of the capacitor embedded substrate300becomes complicated.

In order to overcome this problem, in the capacitor embedded substrate300in accordance with the third embodiment of the present invention, the second build-up layer343includes a glass fiber or a material that can reduce a difference in the coefficient of thermal expansion between the laminated core340and the first build-up layer342.

Meanwhile, the second conductor pattern352is in direct contact with the core via361, and the second build-up via363is in direct contact with the second conductor pattern352and the third conductor pattern353to implement electrical connection.

At this time, the more the signal transmission path between the first to third capacitors310,320, and330and the first conductor pattern351is secured, the higher the utilization of the capacitance of the first to third capacitors310,320, and330is.

For this, in the capacitor embedded substrate300in accordance with the third embodiment of the present invention, a plurality of second build-up vias363are in contact with the second conductor pattern352in direct contact with the core via361of which one side is in contact with the external electrodes of the first to third capacitors310,320, and330.

At this time, as shown inFIG. 3, the core vias361, whose one sides are in contact with the external electrodes of the first to third capacitors310,320, and330, may be connected in more than 2 layers.

Accordingly, the signal transmission path between the first to third capacitors310,320, and330and the first conductor pattern can be widened than the prior art. As a result, it is possible to efficiently utilize the capacitance of the first to third capacitors310,320, and330.

The present invention configured as above can implement low impedance characteristics over a wider frequency band than the prior art and improve a signal processing speed by implementing improvement in electrical conductivity as well as improvement in heat radiation performance.

Further, it is possible to miniaturize and slim the capacitor embedded substrate and efficiently utilize the capacitance of the embedded capacitor.