Structure and formation method of interconnection structure of semiconductor device

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation.

However, these advances have increased the complexity of processing and manufacturing ICs. Since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

DETAILED DESCRIPTION

FIGS. 1A-1Lare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown inFIG. 1A, a semiconductor substrate100is provided. In some embodiments, the semiconductor substrate100is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate100may include silicon or another elementary semiconductor material such as germanium. For example, the semiconductor substrate100is a silicon wafer. In some other embodiments, the semiconductor substrate100includes a compound semiconductor. The compound semiconductor may include silicon germanium, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable compound semiconductor, or a combination thereof.

In some embodiments, the semiconductor substrate100includes a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a wafer bonding process, a silicon film transfer process, a separation by implantation of oxygen (SIMOX) process, another applicable method, or a combination thereof.

In some embodiments, various device elements are formed in and/or over the semiconductor substrate100. The device elements are not shown in figures for the purpose of simplicity and clarity. Examples of the various device elements include transistors, diodes, another suitable element, or a combination thereof. For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n channel field effect transistors (PFETs/NFETs), etc. Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form the various device elements. The FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in the semiconductor substrate100. The isolation features are used to define active regions and electrically isolate various device elements formed in and/or over the semiconductor substrate100in the active regions. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.

In some embodiments, an interconnection structure (which will be described in more detail later) is formed over the semiconductor substrate100. The interconnection structure includes multiple dielectric layers containing an interlayer dielectric (ILD) layer and one or more inter-metal dielectric (IMD) layers. The interconnection structure also includes multiple conductive features formed in the ILD and IMD layers. The conductive features may include conductive lines, conductive vias, and/or conductive contacts. Various processes, such as back-end-of-line (BEOL) semiconductor fabrication processes, are performed to form the interconnection structure.

Various device elements are interconnected through the interconnection structure over the semiconductor substrate100to form integrated circuit devices. The integrated circuit devices include logic devices, memory devices (e.g., static random access memories, SRAMs), radio frequency (RF) devices, input/output (I/O) devices, system-on-chip (SoC) devices, image sensor devices, other applicable types of devices, or a combination thereof.

More specifically, as shown inFIG. 1A, a dielectric layer110is deposited over the semiconductor substrate100. The dielectric layer110may serve as an ILD or IMD layer of an interconnection structure. The dielectric layer110covers device elements formed in and/or over the semiconductor substrate100. AlthoughFIG. 1Ashows that the dielectric layer110is a single layer, embodiments of the disclosure are not limited thereto. In some other embodiments, the dielectric layer110is a multi-layer structure including dielectric sub-layers (not shown).

In some embodiments, the dielectric layer110is made of or includes a low dielectric constant (low-k) material, an extreme low-k (ELK) material, silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), one or more other suitable materials, or a combination thereof. In some embodiments, the dielectric layer110is deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a spin-on process, a spray coating process, one or more other applicable processes, or a combination thereof.

The low-k or ELK material may have a smaller dielectric constant than that of silicon dioxide. For example, the low-k material may have a dielectric constant in a range from about 1.5 to about 3.5. The ELK material may have a dielectric constant, which is less than about 2.5 or in a range from about 1.5 to about 2.5. As the density of semiconductor devices increases and the size of circuit elements becomes smaller, the resistance capacitance (RC) delay time increasingly dominates circuit performance. Therefore, using a low-k or ELK material as the dielectric layer110is helpful for reducing the RC delay.

A wide variety of low-k or ELK material may be used for forming the dielectric layer110. In some embodiments, the dielectric layer110is made of or includes a porous dielectric material, an organic polymer, an organic silica glass, SiOF series material, a hydrogen silsesquioxane (HSQ) series material, a methyl silsesquioxane (MSQ) series material, carbon doped silicon oxide, amorphous fluorinated carbon, parylene, benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE) (Teflon), silicon oxycarbide polymers (SiOC), a porous organic series material, a spin-on inorganic dielectric, a spin-on organic dielectric, one or more other suitable materials, or a combination thereof.

Multiple conductive features (not shown) are formed in the dielectric layer110. The conductive features are electrically connected to the device elements. In some embodiments, the conductive features are made of or include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), gold (Au), platinum (Pt), one or more other suitable materials, or a combination thereof. Various processes, including deposition, etching, planarization, or the like, may be used to form the conductive features in the dielectric layer110.

As shown inFIG. 1A, a dielectric layer120is deposited over the dielectric layer110. The dielectric layer120may serve as an IMD layer of an interconnection structure. AlthoughFIG. 1Ashows that the dielectric layer120is a single layer, embodiments of the disclosure are not limited thereto. In some other embodiments, the dielectric layer120is a multi-layer structure including dielectric sub-layers (not shown). The materials and/or formation methods of the dielectric layer120are the same as or similar to those of the dielectric layer110, as illustrated in the aforementioned embodiments, and therefore are not repeated.

Multiple conductive features are formed in the dielectric layer120. Conductive features130are shown inFIG. 1Aas an example. It should be noted that the dimensions of the conductive features130shown inFIG. 1Aare only an example and not a limitation to the disclosure. The conductive features130may be conductive lines or other suitable conductive features. The conductive features130may be single or dual damascene structures. The conductive features130are electrically connected to the device elements through the conductive features (not shown) in the dielectric layer110.

AlthoughFIG. 1Ashows that each of the conductive features130is a single layer, embodiments of the disclosure are not limited thereto. The conductive features130may be a multi-layer structure including conductive sub-layers. For example, the conductive sub-layers include a diffusion barrier layer, a seed layer, a metal-filling layer, one or more other suitable layers, or a combination thereof. The conductive sub-layers are not shown in figures for the purpose of simplicity and clarity.

As shown inFIG. 1A, an etching stop layer140is deposited over the dielectric layer120, in accordance with some embodiments. The etching stop layer140covers the conductive features130. The etching stop layer140is used to protect the conductive features130from being damaged during subsequent etching processes. The etching stop layer140may serve as a barrier layer, which can protect a dielectric layer (such as dielectric layer150) from diffusion of a metal material from subsequent conductive features during subsequent thermal processes or cycles.

In some embodiments, the thickness of the etching stop layer140is in a range from about 10 Å to about 100 Å. In some embodiments, the etching stop layer140is made of or includes plasma-enhanced oxide (PEOX), tetraethoxysilane (TEOS), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SiCO), silicon nitride (SiN), silicon oxynitride (SiON), one or more other suitable materials, or a combination thereof. Examples of SiC include oxygen-doped silicon carbide (SiC:O, also known as ODC) and nitrogen-doped silicon carbide (SiC:N, also known as NDC). In some embodiments, the etching stop layer140is deposited using a CVD process, a spin-on process, one or more other suitable materials, or a combination thereof. Embodiments of the disclosure have many variations. In some other embodiments, the etching stop layer140is not formed.

As shown inFIG. 1A, a dielectric layer150is deposited over the etching stop layer140, in accordance with some embodiments. The dielectric layer150serves as an IMD layer of an interconnection structure. In some embodiments, the thickness of the dielectric layer150is in a range from about 100 Å to about 300 Å. The materials and/or formation methods of the dielectric layer150are the same as or similar to those of the dielectric layer110, as illustrated in the aforementioned embodiments, and therefore are not repeated.

As shown inFIG. 1A, a first barrier liner160is deposited over the dielectric layer150, in accordance with some embodiments. The first barrier liner160is used to improve the reliability of subsequent conductive features (which will be described in more detail later). The first barrier liner160serves as a diffusion barrier layer, which can protect a dielectric layer (such as the dielectric layer150) from diffusion of a metal material from subsequent conductive features during subsequent thermal processes or cycles. High resistance, current leakage or short circuiting, which may be induced by metal diffusion or electron migration, is reduced or eliminated. Therefore, the semiconductor device structure has improved device performance (e.g., improved electro-migration (EM) characteristics) and reliability.

In some embodiments, the thickness of the first barrier liner160is in a range from about 1 Å to about 20 Å. The range is only an example and is not a limitation to the disclosure. In some embodiments, the first barrier liner160is thinner than the etching stop layer140, but embodiments of the disclosure are not limited thereto. In some embodiments, the first barrier liner160is made of or includes a diffusion barrier material. For example, the first barrier liner160is made of or includes nitride (such as silicon nitride), oxide (such as PEOX or TEOS), ODC, NDC, one or more other suitable materials, or a combination thereof. In some embodiments, the first barrier liner160is free of tantalum nitride (TaN) or a combination of TaN and Ta. The first barrier liner160may be referred to as a hard or dandified liner.

In some embodiments, the first barrier liner160is deposited using an ALD process, one or more other applicable processes, or a combination thereof. The first barrier liner160may be referred to as an ALD liner. In some embodiments, the first barrier liner160is deposited conformally and therefore the first barrier liner160may be referred to as a conformal liner. The first barrier liner160has good uniformity. In some embodiments, the deposition of the first barrier liner160does not include a physical vapor deposition (PVD) process and/or a CVD process.

As shown inFIG. 1B, a dielectric layer170is deposited over the first barrier liner160, in accordance with some embodiments. The dielectric layer170serves as an IMD layer of an interconnection structure. The materials and/or formation methods of the dielectric layer170are the same as or similar to those of the dielectric layer110or the dielectric layer150, as illustrated in the aforementioned embodiments, and therefore are not repeated.

In some embodiments, the thickness of the dielectric layer170is in a range from about 200 Å to about 400 Å. In some embodiments, the dielectric layer170is thicker than the dielectric layer150, but embodiments of the disclosure are not limited thereto. The first barrier liner160is thinner than the dielectric layer170and the dielectric layer150. In some embodiments, the first barrier liner160is longitudinally sandwiched between the dielectric layer170and the dielectric layer150.

As shown inFIG. 1B, a hard mask180is deposited over the dielectric layer170, in accordance with some embodiments. In some embodiments, the hard mask180is made of or includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or a combination thereof. In some other embodiments, the hard mask180is a multi-layer structure, such as oxide-nitride-oxide (ONO) layers. In some embodiments, the hard mask180is deposited using a PVD process, a CVD process, an ALD process, one or more other applicable processes, or a combination thereof.

As shown inFIG. 1C, a patterned mask layer190is formed over the hard mask180, in accordance with some embodiments. The mask layer190defines the pattern of trenches, which will subsequently be formed in the dielectric layer170. The mask layer190may be a photoresist (PR) or photo-sensitive layer and is patterned using a photolithography process. The mask layer190may be negative type or positive type.

In some embodiments, the mask layer190is made of or includes polyimide, metal-containing organic-inorganic hybrid compound, one or more other suitable materials, or a combination thereof. Examples of the metal-containing organic-inorganic hybrid compound may include metal-containing oxide (such as ZrOxor TiOx) or another organic-inorganic hybrid compound.

As the density of semiconductor devices increases and the size of circuit elements becomes smaller, the resolution in a photolithography process increasingly becomes important and extreme ultraviolet (EUV) radiation is widely used. Using metal-containing organic-inorganic hybrid compound as the mask layer190is helpful for enhancing the resolution in a photolithography process and is suitable for EUV radiation.

AlthoughFIG. 1Cshows that the mask layer190is a single layer, embodiments of the disclosure are not limited thereto. In some other embodiments, the mask layer190is a multi-layer structure including sub-layers (not shown). For example, the mask layer190may include a bottom layer, a middle layer, and a top PR layer.

Afterwards, one or more etching processes (such as a dry etching process and/or a wet etching process) are performed over the mask layer190. The hard mask180is partially etched such that a patterned hard mask180′ is formed, as shown inFIG. 1D. As a result, the pattern of trenches is transferred to the hard mask180′.

Subsequently, one or more etching processes are performed over the hard mask180′. The dielectric layer170is etched and patterned such that multiple trenches175are formed, as shown inFIG. 1D. The dielectric layer170is etched using a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the first barrier liner160serves as an etching stop layer during the etching process for forming the trenches175. The mask layer190may be removed or stripped before, during or after the etching process for forming the trenches175.

The trenches175penetrate through the dielectric layer170such that the first barrier liner160is partially exposed through the trenches175. In some embodiments, the depth of the trenches175in the dielectric layer170is in a range from about 200 Å to about 400 Å. The trenches175may have different dimensions from each other or substantially the same dimension.

In some embodiments, the trenches175have substantially vertical sidewalls, as shown inFIG. 1D. However, embodiments of the disclosure are not limited thereto. In some other embodiments, the trenches175have inclined sidewalls. The horizontal profile of the trenches175may be line-shaped or another shape.

As shown inFIG. 1E, a patterned mask layer200is formed over the hard mask180′ and fills some of the trenches175, in accordance with some embodiments. The mask layer200defines the pattern of via holes, which will subsequently be formed in the first barrier liner160and the dielectric layer150. The materials and/or formation methods of the mask layer200are the same as or similar to those of the mask layer190, as illustrated in the aforementioned embodiments, and therefore are not repeated.

Afterwards, one or more etching processes are performed over the mask layer200. The first barrier liner160and the dielectric layer150are etched and patterned such that multiple via holes155are formed, as shown inFIG. 1F. The first barrier liner160and the dielectric layer150are etched using a dry etching process, a wet etching process, or a combination thereof. As mentioned above, the etching stop layer140protects the conductive features130from being damaged during the etching process for forming the via holes155. The first barrier liner160and the etching stop layer140are made of or include different materials. The mask layer200is then removed or stripped.

The via holes155extend from the trenches175penetrate through the first barrier liner160and the dielectric layer150such that the etching stop layer140is partially exposed through the via holes155. In some embodiments, the depth of the via holes155in the dielectric layer150is in a range from about 100 Å to about 300 Å. The via holes155may have different dimensions from each other or substantially the same dimension.

The via holes155and the trenches175may have substantially the same depth or different depths. For example, the via holes155may have a greater depth than the trenches175. The via holes155and the trenches175may have substantially the same width or different widths. For example, the via holes155may be narrower than the trenches175. The via holes155and the trenches175may have small dimensions or any suitable dimensions. The dimensions are not a limitation to the disclosure.

In some embodiments, the via holes155have substantially vertical sidewalls, as shown inFIG. 1F. However, embodiments of the disclosure are not limited thereto. In some other embodiments, the via holes155have inclined sidewalls. The horizontal profile of the via holes155may be relatively rounded, circular, rectangular, square, or another shape.

As shown inFIG. 1G, a second barrier liner210is deposited over the hard mask180′, in accordance with some embodiments. The second barrier liner210is used to improve the reliability of subsequent conductive features (which will be described in more detail later). The second barrier liner210serves as a diffusion barrier layer, which can protect a dielectric layer (such as the dielectric layer170) from diffusion of a metal material from subsequent conductive features during subsequent thermal processes or cycles.

The second barrier liner210partially fills the via holes155and the trenches175. In some embodiments, the second barrier liner210covers and adjoins the hard mask180′, the dielectric layer170, the first barrier liner160, the dielectric layer150and the etching stop layer140. In some embodiments, the second barrier liner210and the first barrier liner160are separated from the top surface of the conductive features130.

In some embodiments, a portion of the hard mask180′ is longitudinally sandwiched between the second barrier liner210and the dielectric layer170. In some embodiments, a portion of the first barrier liner160is longitudinally sandwiched between the second barrier liner210and the dielectric layer150. In some embodiments, a portion of the etching stop layer140is longitudinally sandwiched between the second barrier liner210and the conductive features130. In some embodiments, one or more portions of the dielectric layer170and the hard mask180′ are surrounded by the second barrier liner210and the first barrier liner160.

In some embodiments, the thickness of the second barrier liner210is in a range from about 1 Å to about 20 Å. The range is only an example and is not a limitation to the disclosure. The second barrier liner210and the first barrier liner160may have substantially the same thickness or different thicknesses. In some embodiments, the second barrier liner210is thinner than the etching stop layer140, but embodiments of the disclosure are not limited thereto.

In some embodiments, the second barrier liner210is made of or includes a diffusion barrier material. For example, the second barrier liner210is made of or includes nitride (such as silicon nitride), oxide (such as PEOX or TEOS), ODC, NDC, one or more other suitable materials, or a combination thereof. In some embodiments, the second barrier liner210is free of TaN or a combination of TaN and Ta. The second barrier liner210may be referred to as a hard or dandified liner. The second barrier liner210and the first barrier liner160may be made of or include the same material or different materials.

In some embodiments, the second barrier liner210is deposited using an ALD process, one or more other applicable processes, or a combination thereof. The second barrier liner210may be referred to as an ALD liner. In some embodiments, the second barrier liner210is deposited conformally and therefore the second barrier liner210may be referred to as a conformal liner. The second barrier liner210has good uniformity.

In some embodiments, the deposition of the second barrier liner210includes an ALD process, rather than a PVD process and/or a CVD process. Since the second barrier liner210is a thin ALD liner, the dielectric layer150and the dielectric layer170are prevented from becoming damaged, such as suffering cracks or deformation. The damage in the dielectric layer150and the dielectric layer170may be induced by being pushed and pressed during a deposition process that is not an ALD process.

Afterwards, one or more etching processes are performed over the second barrier liner210. The second barrier liner210is partially etched until the hard mask180′, the first barrier liner160and the etching stop layer140become partially exposed, as shown inFIG. 1H. The second barrier liner210is etched using an anisotropic etching process, such as a dry etching process, one or more other applicable processes, or a combination thereof.

More specifically, the second barrier liner210has horizontal portions, which cover the hard mask180′, the first barrier liner160and the etching stop layer140, and longitudinal portions, which cover the sidewalls of the via holes155and the trenches175. The horizontal portions of the second barrier liner210are removed while the longitudinal portions of the second barrier liner210are left on the sidewalls of the via holes155and the trenches175, as shown inFIGS. 1G and 1H. The bottom surface of the via holes155is not covered by the first barrier liner160, and the second barrier liner210exposes the bottom surface of the via holes155, as shown inFIG. 1H.

As mentioned above, the etching stop layer140protects the conductive features130from being damaged during the etching process for the partial removal of the second barrier liner210. In some embodiments, the hard mask180′ serves as an etching stop layer and protects the dielectric layer170from being damaged during the etching process for the partial removal of the second barrier liner210.

In some embodiments, the second barrier liner210and the first barrier liner160are made of different materials, and the first barrier liner160can serve as an etching stop layer during the etching process for the partial removal of the second barrier liner210. However, embodiments of the disclosure are not limited thereto. In some other embodiments, the second barrier liner210and the first barrier liner160are made of the same material.

The first barrier liner160is deposited before the formation of the via holes155and remains over the dielectric layer150after the partial removal of the second barrier liner210. As a result, the first barrier liner160can protect the dielectric layer150from damage during etching processes and metal diffusion during subsequent thermal processes.

Subsequently, the etching stop layer140is partially removed such that the conductive features130become partially exposed through the via holes155and the trenches175, as shown inFIG. 1I. The partial removal of the etching stop layer140may include one or more etching processes, such as dry etching processes, wet etching processes, or a combination thereof.

As shown inFIG. 1I, the sidewalls of the trenches175are covered by the second barrier liner210and the bottom surface of the trenches175is covered by the first barrier liner160. The sidewalls of the via holes155are covered by the second barrier liner210and the etching stop layer140but the bottom surface of the via holes155is not covered by the first barrier liner160and the second barrier liner210.

The first barrier liner160and the second barrier liner210protect the dielectric layer150and the dielectric layer170from being damaged during the etching process for the partial removal of the etching stop layer140. Some portions of the dielectric layer150and the dielectric layer170, which are near the via holes155and the trenches175, are prevented from being modified or slightly damaged.

For example, the dielectric layer150and the dielectric layer170may include carbon and the etchant may include oxygen. Due to the first barrier liner160and the second barrier liner210, carbon in the dielectric layer150and the dielectric layer170is prevented from being oxidized during the etching process. As a result, the carbon concentration of the dielectric layer150and the dielectric layer170is substantially unchanged. The dielectric constant of the dielectric layer150and the dielectric layer170maintains substantially the same. It can be ensured that the capacitance stays sufficiently low. Accordingly, the RC delay time is reduced. The operation speed of the semiconductor device structure is increased.

A microscope or spectrometer may be used to observe and analyze the modifying status or to measure the change of carbon concentration. The microscope may include a transmission electron microscope (TEM) or another suitable microscope. The spectrometer may include an electron energy loss spectrometer (EELS) or another suitable spectrometer.

As shown inFIG. 1J, a diffusion barrier layer220is deposited over the hard mask180′ and fills the via holes155and the trenches175, in accordance with some embodiments. In some embodiments, the diffusion barrier layer220is in direct contact with the hard mask180′, the second barrier liner210, the first barrier liner160, the etching stop layer140, and the conductive features130.

In some embodiments, the diffusion barrier layer220and the dielectric layer170horizontally sandwich a portion of the second barrier liner210, as shown inFIG. 1J. In some embodiments, the diffusion barrier layer220and the dielectric layer150horizontally sandwich another portion of the second barrier liner210. In some embodiments, the diffusion barrier layer220and the first barrier liner160horizontally sandwich yet another portion of the second barrier liner210.

In some embodiments, the thickness of the diffusion barrier layer220is in a range from about 1 Å to about 10 Å. The range is only an example and is not a limitation to the disclosure. The diffusion barrier layer220and the first barrier liner160may have substantially the same thickness or different thicknesses. The diffusion barrier layer220and the second barrier liner210may have substantially the same thickness or different thicknesses.

In some embodiments, the diffusion barrier layer220is made of or includes ruthenium (Ru), cobalt (Co), Ta, one or more other suitable materials, or a combination thereof. In some embodiments, the diffusion barrier layer220is free of nitride, such as TaN or a combination of TaN and Ta. In some embodiments, the diffusion barrier layer220is deposited using an ALD process, a PVD process, a CVD process, one or more other applicable processes, or a combination thereof. In some embodiments, the diffusion barrier layer220is deposited conformally.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the deposition of the diffusion barrier layer220includes an ALD process, rather than a PVD process and/or a CVD process. The diffusion barrier layer220has good uniformity. Since the diffusion barrier layer220may be a thin ALD layer, the dielectric layer150and the dielectric layer170are prevented from being damaged, such as suffering cracks or deformation. As a result, bending and dislocation of conductive features, which are subsequently formed in the dielectric layer150and the dielectric layer170, can be avoided.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the diffusion barrier layer220is not formed.

As shown inFIG. 1K, a conductive layer230is deposited over the diffusion barrier layer220and fills the via holes155and the trenches175, in accordance with some embodiments. The conductive layer230and the diffusion barrier layer220together fill up the via holes155and the trenches175. The conductive layer230is thicker than each of the diffusion barrier layer220, the first barrier liner160and the second barrier liner210.

In some embodiments, the conductive layer230and the hard mask180′ longitudinally sandwich a portion of the diffusion barrier layer220, as shown inFIG. 1K. In some embodiments, the conductive layer230and the first barrier liner160longitudinally sandwich another portion of the diffusion barrier layer220. In some embodiments, the conductive layer230and the second barrier liner210horizontally sandwich yet another portion of the diffusion barrier layer220. In some embodiments, the conductive layer230and one of the conductive features130longitudinally sandwich yet another portion of the diffusion barrier layer220.

In some embodiments, the conductive layer230is made of or includes Cu, Al, W, Ti, Ni, Au, Pt, one or more other suitable materials, or a combination thereof. In some other embodiments, the conductive layer230is made of or includes Ru, Co, one or more other suitable materials, or a combination thereof. In some embodiments, the conductive layer230is deposited using an electroplating process, a PVD process, a CVD process, an electroless plating process, one or more other applicable processes, or a combination thereof. The conductive layer230may include a seed layer, which is not shown in figures for the purpose of simplicity and clarity.

In some embodiments, the conductive layer230and the diffusion barrier layer220are made of different materials, but embodiments of the disclosure are not limited thereto. For example, the conductive layer230may be made of Cu and the diffusion barrier layer220may be made of Ru, Co or Ta which can prevent metal diffusion or electron migration without increasing electrical resistance. The diffusion barrier layer220protects the dielectric layer150and the dielectric layer170from diffusion of a metal material from the conductive layer230during subsequent thermal processes or cycles. In some embodiments, the combination of the diffusion barrier layer220, the first barrier liner160and the second barrier liner210significantly reduces or eliminates metal diffusion or electron migration of the conductive layer230. The dielectric layer150and the dielectric layer170are prevented from being damaged.

In some embodiments, a thermal process is performed so that metal atoms in the diffusion barrier layer220are drafted into the conductive layer230. The metal atoms from the diffusion barrier layer220fix or strengthen the bonds between metal atoms (such as Cu or Al) in the conductive layer230. Therefore, the conductive layer230can be prevented from being pulled and thereby breaking or peeling when the semiconductor device operates and current flows through the conductive layer230. The diffusion barrier layer220improves the reliability of the conductive layer230.

As mentioned above, in some other embodiments, the diffusion barrier layer220is not formed so that the conductive layer230is in direct contact with the hard mask180′, the second barrier liner210, the first barrier liner160, the etching stop layer140, and the conductive features130. In these embodiments, the conductive layer230is made of or includes a material that is substantially free of metal migration during thermal processes, such as Ru, Co, one or more other suitable materials, or a combination thereof.

In some other embodiments, the conductive layer230is made of or includes a material that may induce metal migration during thermal processes when the diffusion barrier layer220is not formed. Even if the conductive layer230is made of or includes a material that may induce metal migration, the first barrier liner160and the second barrier liner210can provide with the dielectric layer150and the dielectric layer170sufficient protection from the metal migration. As a result, the capacitance still stays sufficiently low.

Afterwards, a planarization process is performed to remove portions of the diffusion barrier layer220and the conductive layer230outside of the trenches175. The remaining portions of the diffusion barrier layer220and the conductive layer230in the via holes155and the trenches175form conductive features240and250, as shown inFIG. 1L. The hard mask180′ is removed during the planarization process. As a result, the dielectric layer170and the second barrier liner210become exposed during and after the planarization process. The second barrier liner210is also polished and partially removed during the planarization process. The planarization process may include a CMP process, a dry polishing process, a grinding process, an etching process, one or more other applicable processes, or a combination thereof.

In some embodiments, the steps described inFIGS. 1A-1Lmay be referred to as dual damascene processes. AlthoughFIGS. 1A-1Fshow a trench-first process, embodiments of the disclosure are not limited thereto. Embodiments of the disclosure may be applied to a via-first process.

As shown inFIG. 1L, the conductive features240and250are confined in the first barrier liner160and the second barrier liner210. The conductive features250are electrically connected to the conductive features130through the conductive features240. The conductive features250may be referred to as conductive lines. The conductive features240may be referred to as conductive vias. The conductive features240and250may have substantially the same width or different widths. For example, the conductive features250may be wider than the conductive features240. As a result, there may be a corner between the conductive features240and the conductive features250. The corner is filled with the second barrier liner210. The second barrier liner210filling the corner separates the first barrier liner160from the conductive features240.

In some embodiments, the first barrier liner160horizontally extends between two of the conductive features240, as shown inFIG. 1L. In some embodiments, the first barrier liner160and the second barrier liner210are spaced apart from the bottom surface of the conductive features240. In some embodiments, the horizontal interface between the first barrier liner160and the second barrier liner210is substantially coplanar with the bottom surface of the conductive features250.

As shown inFIG. 1L, the first barrier liner160and the second barrier liner210enclose the side edges of the conductive features240and250, in accordance with some embodiments. The combination of the first barrier liner160and the second barrier liner210may be referred to as a barrier liner feature. The combination of the conductive features240and250may be referred to as an interconnection feature. In other words, the side edges and corners of the interconnection feature are enclosed by the barrier liner feature. Therefore, the barrier liner feature provides the dielectric layer150and the dielectric layer170with sufficient protection from metal diffusion of the interconnection feature.

More specifically, the first barrier liner160and the second barrier liner210encircle the sidewalls and the bottom surface of the conductive features250. The second barrier liner210and the etching stop layer140encircle the sidewalls of the conductive features240.

There is no barrier liner adjoining the bottom surface of the conductive features240. In some embodiments, there is no TaN material adjoining the conductive features130. As a result, the electrical resistance between the conductive features240and the conductive features130is greatly reduced. It can be ensured that the RC delay time is sufficiently low. Accordingly, the operation speed of the semiconductor device structure is increased. The semiconductor device structure has enhanced electrical performance.

The first barrier liner160and the second barrier liner210have good adhesion to the conductive features240and250. The first barrier liner160and the second barrier liner210confirm and support the conductive features240and250in the dielectric layer150and the dielectric layer170. As a result, the conductive features240and250have improved physical strength. Since the first barrier liner160and the second barrier liner210include a hard material, the first barrier liner160and the second barrier liner210can resist stress, which may be induced during the formation of the conductive features240and250. The conductive features240and250are prevented from bending, cracking or peeling due to stress. Therefore, the semiconductor device structure includes a stable and reliable interconnection structure.

Afterwards, one or more dielectric layers and multiple conductive features are formed over the dielectric layer170and the conductive features240and250to continue the formation of the interconnection structure of the semiconductor device structure. In some embodiments, the operations illustrated inFIGS. 1A-1Lare repeated one or more times to continue the formation of the interconnection structure.

For example, an upper etching stop layer, which may be the same as or similar to the etching stop layer140, may be deposited to cover the dielectric layer170and the conductive features240and250. Afterwards, the same or similar steps as those described inFIGS. 1A-1Lare performed over the upper etching stop layer.

Many variations and/or modifications can be made to embodiments of the disclosure. For example, the conductive features240and250may not include the diffusion barrier layer220.FIG. 2is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. The semiconductor device structure shown inFIG. 2is similar to that shown inFIG. 1L. In some embodiments, the materials, formation methods, and/or benefits of the semiconductor device structure shown inFIGS. 1A-1Lcan also be applied in the embodiments illustrated inFIG. 2, and are therefore not repeated.

As shown inFIG. 2, the conductive features240and250are made of the conductive layer230, in accordance with some embodiments. For example, similar to the stages shown inFIGS. 1J and 1K, the conductive layer230is deposited over the hard mask180′ and fills the via holes155and the trenches175. A planarization process is then performed to remove portions of the conductive layer230outside of the trenches175. The remaining portions of the conductive layer230in the via holes155and the trenches175form conductive features240and250, as shown inFIG. 2.

In some embodiments, the conductive layer230shown inFIG. 2is made of or includes a bulk material that is substantially free of metal migration during thermal processes, such as Ru, Co, one or more other suitable materials, or a combination thereof. However, embodiments of the disclosure are not limited. The conductive layer230shown inFIG. 2may be made of or include Cu, Al, W, Ti, Ni, Au, Pt, one or more other suitable materials, or a combination thereof.

In some embodiments, the conductive layer230is in direct contact with the second barrier liner210, the first barrier liner160, the etching stop layer140, and the conductive features130. In some embodiments, a portion of the first barrier liner160is longitudinally sandwiched between the conductive layer230and the dielectric layer150, as shown inFIG. 2. In some embodiments, a portion of the second barrier liner210is horizontally sandwiched between the conductive layer230and the dielectric layer150or the dielectric layer170. In some embodiments, another portion of the second barrier liner210is horizontally sandwiched between the conductive layer230and the first barrier liner160.

Many variations and/or modifications can be made to embodiments of the disclosure. For example,FIGS. 1A-1Lshow that the first barrier liner160is deposited before the formation of the trenches175, but embodiments of the disclosure are not limited. The first barrier liner160may be deposited after the formation of the trenches175.FIGS. 3A-3Kare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. The stages shown inFIGS. 3A-3Kare similar to those shown inFIGS. 1A-1L. In some embodiments, the materials, formation methods, and/or benefits of the semiconductor device structure shown inFIGS. 1A-1Lcan also be applied in the embodiments illustrated inFIGS. 3A-3K, and are therefore not repeated.

As shown inFIG. 3A, an etching stop layer140is deposited over the dielectric layer120and covers the conductive features130, in accordance with some embodiments. Subsequently, a dielectric layer150is deposited over the etching stop layer140and a hard mask180is deposited over the dielectric layer150, in accordance with some embodiments. In some embodiments, the thickness of the dielectric layer150is in a range from about 400 Å to about 800 Å. The dielectric layer150shown inFIG. 3Ais thicker than the dielectric layer150shown inFIG. 1A.

As shown inFIG. 3B, a patterned mask layer190is then formed over the hard mask180, in accordance with some embodiments. The mask layer190defines the pattern of trenches, which will subsequently be formed in the dielectric layer150.

Afterwards, one or more etching processes (such as a dry etching process and/or a wet etching process) are performed over the mask layer190. The hard mask180is partially etched such that a patterned hard mask180′ is formed, as shown inFIG. 3C. As a result, the pattern of trenches is transferred to the hard mask180′.

Subsequently, one or more etching processes are performed over the hard mask180′. The dielectric layer150is etched and patterned such that multiple trenches175are formed, as shown inFIG. 3C. The dielectric layer150is etched using a dry etching process, a wet etching process, or a combination thereof. The mask layer190may be removed or stripped before, during or after the etching process for forming the trenches175.

The trenches175extend in the dielectric layer150without penetrating through the dielectric layer150. In some embodiments, the depth of the trenches175in the dielectric layer150is in a range from about 200 Å to about 400 Å.

As shown inFIG. 3D, a first barrier liner160is deposited over the hard mask180′ and fills the trenches175, in accordance with some embodiments. In some embodiments, the first barrier liner160is deposited conformally in the trenches175. In some embodiments, the first barrier liner160is in direct contact with the hard mask180′ and the dielectric layer150.

As shown inFIG. 3E, a patterned mask layer200is formed over the first barrier liner160and fills some of the trenches175, in accordance with some embodiments. The mask layer200defines the pattern of via holes, which will subsequently be formed in the first barrier liner160and the dielectric layer150.

Afterwards, one or more etching processes are performed over the mask layer200. The first barrier liner160and the dielectric layer150are etched and patterned such that multiple via holes155are formed, as shown inFIG. 3F. The first barrier liner160and the dielectric layer150are etched using a dry etching process, a wet etching process, or a combination thereof. The mask layer200is then removed or stripped.

The etching stop layer140protects the conductive features130from being damaged during the etching process for forming the via holes155. The first barrier liner160also protects the dielectric layer150from being damaged during the etching process. Some portions of the dielectric layer150, which are near the trenches175, are prevented from being modified or slightly damaged. For example, due to the first barrier liner160, carbon in the dielectric layer150is prevented from being oxidized during the etching process. As a result, the dielectric constant of the dielectric layer150maintains substantially the same. The capacitance stays sufficiently low and the RC delay time is reduced.

The via holes155extend from the trenches175and penetrate through the first barrier liner160and the dielectric layer150such that the etching stop layer140is partially exposed through the via holes155. In some embodiments, the depth of the via holes155in the dielectric layer150is in a range from about 200 Å to about 400 Å. The via holes155and the trenches175may have substantially the same depth or different depths. For example, the via holes155may have a greater depth than the trenches175. The via holes155and the trenches175may have substantially the same width or different widths. For example, the via holes155may be narrower than the trenches175.

As shown inFIG. 3G, a second barrier liner210is deposited over the first barrier liner160and partially fills the via holes155and the trenches175, in accordance with some embodiments. In some embodiments, the second barrier liner210is in direct contact with the first barrier liner160, the dielectric layer150and the etching stop layer140.

In some embodiments, a portion of the first barrier liner160is longitudinally or horizontally sandwiched between the second barrier liner210and the hard mask180′. As a result, the second barrier liner210is separated from the hard mask180′ by the first barrier liner160. In some embodiments, a portion of the first barrier liner160is longitudinally or horizontally sandwiched between the second barrier liner210and the dielectric layer150. In some embodiments, a portion of the etching stop layer140is longitudinally sandwiched between the second barrier liner210and the conductive features130.

Afterwards, one or more etching processes are performed over the second barrier liner210. The second barrier liner210is partially etched until the first barrier liner160and the etching stop layer140become exposed, as shown inFIG. 3H.

More specifically, the second barrier liner210has horizontal portions, which cover the first barrier liner160and the etching stop layer140, and longitudinal portions, which extend along the sidewalls of the via holes155and the trenches175. The horizontal portions of the second barrier liner210are removed while the longitudinal portions of the second barrier liner210are left in the via holes155and the trenches175, as shown inFIGS. 3G and 3H. The bottom surface of the via holes155is not covered by the first barrier liner160, and the second barrier liner210exposes the bottom surface of the via holes155, as shown inFIG. 3H. The hard mask180′ remains covered by the first barrier liner160during and after the etching process for the partial removal of the second barrier liner210.

The etching stop layer140protects the conductive features130from being damaged during the etching process for the partial removal of the second barrier liner210. In some embodiments, the second barrier liner210and the first barrier liner160are made of different materials. The first barrier liner160can serve as an etching stop layer and protect the dielectric layer150from being damaged during the etching process for the partial removal of the second barrier liner210.

The first barrier liner160is deposited after the formation of the trenches175and before the formation of the via holes155and remains over the dielectric layer150after the partial removal of the second barrier liner210. As a result, the first barrier liner160can protect the dielectric layer150from damage during etching processes and metal diffusion during subsequent thermal processes.

Subsequently, the etching stop layer140is partially removed such that the conductive features130become partially exposed through the via holes155and the trenches175, as shown inFIG. 3I. The first barrier liner160and the second barrier liner210protect the dielectric layer150from being damaged during the etching process. As a result, the dielectric constant of the dielectric layer150maintains substantially the same. The capacitance stays sufficiently low and the RC delay time is reduced.

As shown inFIG. 3J, a diffusion barrier layer220are deposited over the second barrier liner210and fills the via holes155and the trenches175, in accordance with some embodiments. In some embodiments, the diffusion barrier layer220is in direct contact with the second barrier liner210, the first barrier liner160, the etching stop layer140, and the conductive features130.

In some embodiments, a portion of the first barrier liner160is longitudinally sandwiched between the diffusion barrier layer220and the hard mask180′, as shown inFIG. 3J. In some embodiments, a portion of the first barrier liner160is longitudinally sandwiched between the diffusion barrier layer220and the dielectric layer150.

In some embodiments, a portion of the second barrier liner210is horizontally sandwiched between the diffusion barrier layer220and the dielectric layer150, as shown inFIG. 3J. In some embodiments, another portion of the second barrier liner210is horizontally sandwiched between the diffusion barrier layer220and the first barrier liner160.

As shown inFIG. 3J, a conductive layer230is deposited over the diffusion barrier layer220and fills the via holes155and the trenches175, in accordance with some embodiments. The conductive layer230and the diffusion barrier layer220together fill the via holes155and the trenches175.

In some embodiments, a portion of the diffusion barrier layer220is longitudinally sandwiched between the conductive layer230and the first barrier liner160, as shown inFIG. 3J. In some embodiments, another portion of the diffusion barrier layer220is horizontally sandwiched between the conductive layer230and the second barrier liner210. In some embodiments, yet another portion of the diffusion barrier layer220is longitudinally sandwiched between the conductive layer230and one of the conductive features130.

A planarization process is then performed to remove portions of the diffusion barrier layer220and the conductive layer230outside of the trenches175. The remaining portions of the diffusion barrier layer220and the conductive layer230in the via holes155and the trenches175form conductive features240and250, as shown inFIG. 3K. The hard mask180′ is removed during the planarization process. As a result, the dielectric layer150, the first barrier liner160and the second barrier liner210become exposed during and after the planarization process. The first barrier liner160and the second barrier liner210are also polished and partially removed during the planarization process.

In some embodiments, the steps described inFIGS. 3A-3Kmay be referred to as dual damascene processes. AlthoughFIGS. 3A-3Fshow a trench-first process, embodiments of the disclosure are not limited thereto. Embodiments of the disclosure may be applied to a via-first process.

As shown inFIG. 3K, the first barrier liner160and the second barrier liner210enclose the side edges and corners of the conductive features240and250, in accordance with some embodiments. In some embodiments, the first barrier liner160horizontally extends between two of the conductive features240. In some embodiments, the first barrier liner160extends from the bottom surface of the conductive features250along the sidewall (or side edges) of the conductive features250, as shown inFIG. 3K.

More specifically, the first barrier liner160and the second barrier liner210encircle the sidewalls of the conductive features250. The first barrier liner160covers or overlies the bottom surface of the conductive features250. The second barrier liner210and the etching stop layer140encircle the sidewalls of the conductive features240.

There is no barrier liner adjoining the bottom surface of the conductive features240. In some embodiments, there is no TaN material adjoining the conductive features130. As a result, the electrical resistance between the conductive features240and the conductive features130is greatly reduced.

Afterwards, one or more dielectric layers and multiple conductive features are formed over the dielectric layer150and the conductive features240and250to continue the formation of the interconnection structure of the semiconductor device structure. In some embodiments, the operations illustrated inFIGS. 3A-3Kare repeated one or more times to continue the formation of the interconnection structure.

For example, an upper etching stop layer, which may be the same as or similar to the etching stop layer140, may be deposited to cover the dielectric layer150and the conductive features240and250. An upper dielectric layer, which may be the same as or similar to the dielectric layer150, may be deposited over the upper etching stop layer. Afterwards, the same or similar steps as those described inFIGS. 3A-3Kare performed over the upper dielectric layer to continue the formation of the interconnection structure.

Many variations and/or modifications can be made to embodiments of the disclosure. As mentioned above, the conductive features240and250may not include the diffusion barrier layer220.FIG. 4is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. The semiconductor device structure shown inFIG. 4is similar to those shown inFIGS. 1L, 2 and 3K. In some embodiments, the materials, formation methods, and/or benefits of the semiconductor device structure shown inFIGS. 1A-1L, 2 and 3A-3Kcan also be applied in the embodiments illustrated inFIG. 4, and are therefore not repeated.

As shown inFIG. 4, the conductive features240and250are made of the conductive layer230, in accordance with some embodiments. For example, similar to the stages shown inFIG. 3J, the conductive layer230is deposited over the first barrier liner160and the second barrier liner210and fills the via holes155and the trenches175. A planarization process is then performed to remove portions of the conductive layer230outside of the trenches175. The remaining portions of the conductive layer230in the via holes155and the trenches175form conductive features240and250, as shown inFIG. 4.

In some embodiments, the conductive layer230shown inFIG. 4is made of or includes a bulk material that is substantially free of metal migration during thermal processes, such as Ru, Co, one or more other suitable materials, or a combination thereof. However, embodiments of the disclosure are not limited. The conductive layer230shown inFIG. 4may be made of or include Cu, Al, W, Ti, Ni, Au, Pt, one or more other suitable materials, or a combination thereof.

In accordance with some embodiments, the semiconductor device structure shown inFIGS. 1L, 2, 3K and 4includes a more reliable interconnection structure with enhanced performance. The interconnection structure includes the conductive features240and250, the first barrier liner160and the second barrier liner210. The side edges and corners of the conductive features240and250are sufficiently surrounded by the first barrier liner160and the second barrier liner210. As a result, the first barrier liner160and the second barrier liner210reduce or eliminated metal diffusion or electron migration from the conductive features240and250to the dielectric layer of the interconnection structure.

The first barrier liner160and the second barrier liner210are free of TaN material and do not extend under the conductive features240and250. Since there is no TaN material between the conductive features130and the conductive features240, electrical resistance is greatly reduced. Accordingly, the device performance and reliability of the semiconductor device structure can both be improved due to the first barrier liner160and the second barrier liner210.

Furthermore, the first barrier liner160and the second barrier liner210have better physical strength themselves. The first barrier liner160and the second barrier liner210also increase the physical strength and adhesion of the conductive features240and250in the dielectric layer of the interconnection structure. The first barrier liner160and the second barrier liner210further protect the dielectric layer of the interconnection structure from damage during etching processes. Therefore, the reliability of the semiconductor device structure is enhanced even further.

In some embodiments, the formation methods described inFIGS. 1A-1L, 2, 3A-3K and 4are used to form an interconnection structure of a semiconductor device. However, embodiments of the disclosure are not limited. In some other embodiments, the formation methods described in the disclosure can be used to form any suitable conductive structures surrounded by barrier liners.

Embodiments of the disclosure can be applied to not only a semiconductor device structure with planar FETs but also a semiconductor device structure with FinFETs or other applicable devices. Embodiments of the disclosure are not limited and may be applied to fabrication processes for any suitable technology generation. Various technology generations include a 28 nm node, a 20 nm node, a 16 nm node, a 10 nm node, a 7 nm node, a 5 nm node, a 3 nm node, or another suitable node.

Embodiments of the disclosure provide structures and formation methods of a semiconductor device structure. The semiconductor device structure includes an interconnection feature in a dielectric layer and a barrier liner feature between the interconnection feature and the dielectric layer. The barrier liner feature surrounds the side edges and corners of the interconnection feature so as to provide the dielectric layer with sufficient protection from metal diffusion or electron migration of the interconnection feature. The barrier liner feature does not cover the bottom of the interconnection feature. As a result, electrical resistance between the interconnection feature and an underlying interconnection feature is greatly reduced. Therefore, the electrical performance and reliability of the semiconductor device structure are both enhanced even further.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer over a semiconductor substrate and a conductive feature in the first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via over the conductive feature. The conductive via is in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The conductive line is electrically connected to the conductive feature through the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding the sidewall of the conductive line and the sidewall of the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first conductive feature in a first dielectric layer. The semiconductor device structure also includes a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a second conductive feature in the second dielectric layer. In addition, the semiconductor device structure includes a third conductive feature over the second conductive feature. The third conductive feature and the second conductive feature are electrically connected to the first conductive feature. The semiconductor device structure also includes a first barrier liner covering a bottom surface of the third conductive feature. The semiconductor device structure further includes a second barrier liner surrounding side edges of the second conductive feature and the third conductive feature. The first barrier liner and the second barrier liner are spaced apart from a bottom surface of the second conductive feature.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes depositing an etching stop layer over a first dielectric layer. The etching stop layer covers a conductive feature in the first dielectric layer. The method also includes depositing a second dielectric layer over the etching stop layer and depositing a first barrier liner over the second dielectric layer. The method further includes forming a trench over the conductive feature and etching the first barrier liner and the second dielectric layer to form a via hole exposing the etching stop layer. In addition, the method includes depositing a second barrier liner in the trench and the via hole. The method also includes partially removing the second barrier liner to expose the first barrier liner and the etching stop layer. The method further includes partially removing the etching stop layer to expose the conductive feature and filling the trench and the via hole with a conductive layer.