Gate line edge roughness reduction by using 2P/2E process together with high temperature bake

A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.

FIELD OF INVENTION

The present invention relates generally to semiconductor devices and more particularly to a method of patterning polysilicon features with reduced pattern distortion.

BACKGROUND OF THE INVENTION

There is a constant drive within the semiconductor industry to increase overall performance and operating speed of integrated circuit devices, e.g., microprocessors, memory devices, communication chips, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices and the components that make up such devices, e.g., transistors. That is, many features of a typical field effect transistor (FET), e.g., channel length, junction depth, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase device performance and the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.

In addition, there is a constant drive to increase the density of modern integrated circuit devices, i.e., to put more and more semiconductor devices, e.g., transistors, closer together on a single chip. Increasing the density of integrated circuit devices makes more efficient use of the semiconductor die area, and may assist in increasing the overall yield from semiconductor manufacturing operations.

One problem encountered in efforts to increase the density of modern integrated circuit devices arises in forming ever smaller critical dimension features. Typically, a polysilicon feature such as a transistor gate structure is formed by depositing a polysilicon layer over a substrate, followed by forming a photoresist layer over the polysilicon. The photoresist is then selectively exposed to ultraviolet radiation, and (in the cases of a positive photoresist) the exposed portions are removed by application of a developer solution. The patterned photoresist is then subsequently employed as an etch mask in patterning the underlying polysilicon.

One challenge in reducing the critical dimension of a polysilicon feature is line edge roughness (LER) of the developed photoresist, which then gets transferred down to the polysilicon during the subsequent etching. It is desirable to reduce line edge roughness to improve feature dimension control as scaling continues.

SUMMARY OF THE INVENTION

The present invention relates to a method of patterning a plurality of polysilicon structures, and comprises forming a polysilicon layer over a semiconductor body. The polysilicon layer is then patterned to form a first polysilicon structure using a first patterning process that reduces line edge roughness (LER). The polysilicon layer is then subsequently patterned to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.

In another embodiment of the invention, a method of patterning a polysilicon layer with two distinct, separate patterning processes is disclosed. The method comprises forming a first photoresist layer over the polysilicon layer, and patterning the first photoresist layer with a first patterning process that reduces line edge roughness (LER) (e.g., using a post-pattern photoresist high temperature bake). A portion of the polysilicon layer is patterned using the first patterned photoresist layer to form a plurality of first polysilicon structures having a layout symmetry associated therewith. A second photoresist layer is formed over the plurality of first polysilicon structures and over a remaining unpatterned portion of the single polysilicon layer, and the second photoresist layer is patterned with a second patterning process that is different than the first patterning process. A portion of the remaining unpatterned portion of the polysilicon layer is subsequently patterned to form one or more second polysilicon structures having a layout that is asymmetric with respect to the plurality of first polysilicon structures.

According to another embodiment of the invention, a method of forming a plurality of transistors is disclosed and comprises defining a plurality of active areas in a semiconductor body using one or more isolation regions, and forming a gate dielectric over the active areas. The method further comprises forming a polysilicon layer over the gate dielectric in the active areas, and over the isolation regions, and forming a first patterned photoresist layer with a first patterning process, that reduces line edge roughness (LER), over the polysilicon layer. The polysilicon layer is patterned using the first patterned photoresist layer as an etch mask resulting in a first plurality of polysilicon structures, and an unpatterned portion of the polysilicon layer. The first patterned photoresist layer is then removed after forming the first plurality of polysilicon structures, and a second patterned photoresist layer is formed over the first plurality of polysilicon structures and over the unpatterned portion of the polysilicon layer with a second patterning process that is different than the first patterning process. The method still further comprises patterning a portion of the unpatterned portion of the polysilicon layer using the second patterned photoresist layer as an etch mask to form one or more second polysilicon structures, and removing the second patterned photoresist layer after forming the one or more second polysilicon structures.

The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.

DETAILED DESCRIPTION OF THE INVENTION

One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. The inventors of the present invention discovered that a conventional solution for reducing line edge roughness (LER) in polysilicon structures results in some undesired distortion. More particularly, it was discovered that a post-pattern photoresist high temperature bake, while reducing the polysilicon gate line edge roughness, caused increased polysilicon pattern distortion for selected feature layout configurations. The present invention comprises a two-step pattern (2P) and a two-step etch (2E) that addresses different feature configurations with different patterning processes to achieve decreased line edge roughness (LER) for selected features, while decreasing an amount of polysilicon pattern distortion that was associated with conventional polysilicon patterns. Details of the inventive method will be more fully appreciated in light of the detailed explanation provided below.

FIG. 1is a prior art plan view of a baseline (BL) wafer10illustrating patterned polysilicon features12that were patterned without a photoresist post-pattern high temperature bake. Prior artFIG. 1further illustrates another wafer14having polysilicon features16that were patterned with a post-pattern photoresist high temperature bake. More particularly, after exposing and developing the overlying photoresist, the photoresist pattern is subjected to a high temperature bake that is near, but below the melting point of the resist. In one example, the high temperature bake temperature is about 206 C for a duration of about 90 seconds. As can be seen inFIG. 1, the polysilicon features16experiencing the post-pattern high temperature resist bake before poly etch exhibit a 20-30% reduction in line edge roughness (LER) compared to the untreated features12.

While the post-pattern high temperature resist bake advantageously provides for a reduction in line edge roughness, the inventors of the present invention discovered that the bake process results in a distortion of the pattern poly gates, as well as other select features, as may be more fully appreciated inFIGS. 2A and 2B. InFIG. 2Aa plurality of patterned polysilicon features20are illustrated overlying active areas22and isolation regions24, respectively. In general, the polysilicon features26overlying the active areas22are poly gates, while the polysilicon features28and30over the isolation regions24are poly contact pads and connecting field poly, respectively. InFIG. 2A, the polysilicon features20are not formed with a post-pattern photoresist high temperature bake.

InFIG. 2B, a plurality of polysilicon features30is also illustrated, wherein poly gates26overlie active areas22, and poly contact pads28and connecting field poly features30overlie isolation regions24, respectively. InFIG. 2B, the polysilicon features30are patterned with the post-pattern photoresist high temperature bake, and thus exhibit reduced line edge roughness. In addition, however, the polysilicon features30ofFIG. 2Bexhibit more pattern distortion than the polysilicon features20ofFIG. 2A. Such distortion can be seen by comparing the deviation of the poly gates26that extend along dotted lines40and42. As can be seen inFIG. 2B, the gates26deviate from the vertical dotted line42substantially more than the gates26deviate from the dotted line40ofFIG. 2A.

The reason for the increased distortion can be better appreciated in the context ofFIG. 3. InFIG. 3polysilicon features50extend over active regions52and isolation regions54surrounding the active regions. The distortions experienced by the poly gate features56are related to asymmetric poly layout configurations that include the connecting field poly58and the poly gate contact pads60. With the asymmetric poly layout configurations, extra stresses in the polysilicon are induced from the post-pattern photoresist high temperature bake and subsequent poly etch, and because of the lateral asymmetry, the stresses do not balance each other. Consequently, the uneven application of stresses introduce more poly pattern distortion.

In appreciation of the cause of poly pattern distortion, the inventors disclose a segmentation of the poly patterning process into two or more separate, distinct patterning processes, wherein those features most apt to induce distortions into poly gate features are patterned with a different patterning process than that employed for the poly gates. In one embodiment of the invention, features such as poly gates that have a substantially symmetric layout configuration are patterned with a first process that reduces line edge roughness (LER), (e.g., using a post-pattern photoresist high temperature bake or other method of reducing LER) while other features such as connecting field poly and poly contact pads are patterned with a separate, distinct process that does not employ a post-pattern photoresist high temperature bake. Consequently, select patterns such as the poly gates exhibit reduced LER, while those features most apt to exert stresses on other features and cause resultant distortion do not get processed with the high temperature bake.

One example illustration of how the two-step pattern (2P) and two-step etch (2E) can work is illustrated inFIGS. 4A-4C.FIG. 4Aillustrates polysilicon features comprising poly gates56connecting field poly58and gate contact pads60. An original or conventional poly mask would concurrently form all the poly features shown inFIG. 4Ain a single pattern and etch process. However, the two-step pattern (2P) and two-step etch (2E) utilizes a two mask set, shown inFIGS. 4B-4C. The two mask set comprises a first polysilicon processing mask, associated with a first patterning process, that forms polysilicon features including poly gates56(e.g., with a post-pattern photoresist high temperature bake) (seeFIG. 4B). A second mask, configured for use with a ‘dark field’ exposure, ‘cuts’ away unwanted polysilicon features formed by the first mask and results in poly features58and the gate contact pads60(e.g., without a post-pattern photoresist high temperature bake) (seeFIG. 4C) Therefore, the combined result of the two masks, shown inFIGS. 4B and 4C, is a layout that resembles that which is shown inFIG. 4A, and that reduces poly gate distortion compared to conventional polysilicon processing.

Turning now toFIG. 5, a method500of patterning a plurality of polysilicon structures is provided. While the exemplary method500is illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention.

The method500begins at502with the defining of active areas in a semiconductor body. In one embodiment, isolation regions such as field oxide or shallow trench isolation structures are employed to define active areas therebetween. The active areas that are bounded by such isolation regions are then typically doped with n-type or p-type dopant to form n-wells or p-wells for PMOS and NMOS transistor fabrication, respectively. Examples of active areas bounded by isolation regions may be seen at22and24ofFIGS. 2A and 2B, and52and54ofFIG. 3.

A gate dielectric is then formed in the active areas at504ofFIG. 5. In one embodiment, a gate dielectric comprises a thermally grown oxide, however, high-k gate dielectrics may be deposited in alternative embodiments. A polysilicon layer is then formed, at506, over the gate dielectric in the active areas and over the isolation regions with a blanket deposition, such as, for example, a CVD process.

A first patterned photoresist is formed at508using a first patterning process that reduces LER. In one embodiment, the first patterning process comprises a post-pattern photoresist high temperature bake to reduce the line edge roughness associated therewith. The underlying polysilicon layer is then patterned via, for example, a dry etch at510using the first patterned photoresist as an etch mask. The patterning at510results in the formation of a plurality of polysilicon structures, as well as unpatterned portions of the polysilicon. The first patterned photoresist is then removed via, for example, an ashing process at512.

In one embodiment a ‘thermal flow assist layer’ may be used during the first patterning process (e.g., associated with the first polysilicon processing mask) to improve the temperature sensitivity of the high-temp bake process. The thermal flow assist layer may be deposited onto polysilicon features after they have been patterned but prior to the high temperature bake process. In one embodiment, during the high-temp bake process the thermal flow assist layer contracts, pulling at the polysilicon structures in a manner that improves their configuration and results in a reduced LER.

Still referring toFIG. 5, a second patterned photoresist is then formed over the polysilicon layer at514, wherein the second patterned photoresist is formed by a second patterning process that is different than the first patterning process. In one embodiment the second patterning process does not include a post-pattern photoresist high temperature bake. Rather, such a process may comprise depositing the photoresist, performing a low temperature resist bake, selectively exposing the resist to radiation, and developing the exposed photoresist. The underlying polysilicon layer is then again patterned, this time using the second patterned photoresist as an etch mask at516. The second patterned photoresist is then removed at518via, for example, an ashing process.

By the two-step pattern (2P), two-step etch (2E) process set forth inFIG. 5, polysilicon structures may be fabricated with polysilicon gates exhibiting decreased line edge roughness without substantial adverse pattern distortion. For example, referring back toFIGS. 4B and 4C, features56may be patterned with the first patterning process, while the features58and60ofFIG. 4Cmay be fabricated with the second patterning process.

The active areas may then be implanted to form transistor devices at520, as may be appreciated.