Coherent access to persistent memory region range

A method and system for maintaining coherency between DMA and NVMe data paths are disclosed. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands with a dedicated queue that is hidden from a host that has higher priority than the corresponding host (NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding LBA ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read-only, read coherency against host writes to the same region may be achieved.

BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

Embodiments of the present disclosure generally relate to a direct memory access, and more particularly to maintaining data coherency for data in a PMR range.

Description of the Related Art

A computer system's memory can be composed of main memory, such as volatile memory, and secondary memory or memory storage, such as non-volatile memory. Communication between memory storage and a central processing unit (CPU) of a computer is defined by the command set and protocols specifying instructions for read/write access and by the host programming interface upon which those commands are transmitted. Communication protocols have been defined to enable faster adoption and interoperability of memory storage devices connected to a host over a bus, such as a peripheral computer expansion bus.

The CPU accesses data from a memory storage device through communication via various physical layers, link layers, host interface layers, memory management layers, data-path layers, and flash translation layers between the host and the memory storage device. The time latency for each communication between the host and memory storage device adds significant amount of time to the data fetch/execute cycle time.

In direct memory access (DMA) mode, a host device such as a CPU or GPU may access a part of non-volatile memory that is mapped to a persistent memory region (PMR) via the peripheral component interface (PCI) bus to engage in read-only memory transactions. Such a host may additionally engage in memory transactions via a Non-Volatile Memory express (NVMe) protocol.

Conventionally, DMA access and NVMe access occur on separate paths. This can lead to complexities in implementation as both work in parallel, as maintaining data coherency when the same data is accessed via both paths.

Therefore, there is a need for improved systems and methods for maintaining data coherency.

SUMMARY OF THE DISCLOSURE

The present disclosure generally relates to a method and system for maintaining data coherency in a non-volatile memory (NVM) as between DMA and NVMe memory transactions on the NVM. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands within a dedicated queue that is hidden from a host that has higher priority than corresponding host (NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding logical block address (LBA) ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read only, read coherency against host writes to the same region may be achieved.

In one embodiment, a controller is disclosed that includes a memory comprising computer-readable instructions for a method for driverless access of a non-volatile memory of a non-volatile memory device by a host, and a processor configured execute the executable instructions. In certain embodiments the executable instructions cause the controller to initialize a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space through a PCIe link between the host and the non-volatile memory device, and send load/store commands to the PCIe memory space for driverless access. The executable instructions further cause the controller to place the load/store commands in a persistent memory region (PMR) queue of the non-volatile memory device, and aggregate the load/store commands of the PMR queue with one or more commands of a Non-Volatile Memory express (NVMe) queue.

In another embodiment, a data storage device is disclosed that includes a controller configured to execute a method of driver access and driverless access of a non-volatile memory of a non-volatile memory device by a host. In certain embodiments the method includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space through a PCIe link between the host and the non-volatile memory device, initializing a PCIe configuration space with a configuration information of the non-volatile memory device, and sending load/store commands to the PCIe memory space for driverless access. The method further includes sending read/write commands to an NVMe driver of the host for driver access utilizing the configuration information of the non-volatile memory device, and providing the load/store commands and read/write commands to an aggregated command queue for processing by the non-volatile memory device.

In another embodiment, a system for storing data is disclosed, including one or more non-volatile memory means, and a controller means configured to carry out a method to maintain coherency between PMR and NVMe data transactions. In certain embodiments the method includes establishing a PCIe link between a host and the non-volatile memory means and an NVMe link between the host and the non-volatile memory means, initializing a PCIe memory space mapping one or more portions of the non-volatile memory of the non-volatile memory means to a host memory space through a PCIe link between the host and the non-volatile memory means, and sending load/store commands to the PCIe memory space for driverless access. The method further includes placing the load/store commands in a persistent memory region (PMR) queue of the non-volatile memory means, and aggregating the load/store commands of the PMR que with one or more read/write commands of a Non-Volatile Memory express (NVMe) queue.

DETAILED DESCRIPTION

The present disclosure provides for methods and systems for maintaining data coherency in a non-volatile memory (NVM) as between DMA and NVMe memory transactions on the NVM. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands with a dedicated queue that is hidden from a host and that has higher priority than corresponding host (e.g., NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding LBA ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read only, read coherency against host writes to the same region may be achieved.

FIG.1Adepicts a schematic illustration of one embodiment of a system100including an initiator or host150and a NVM device102, such as a SSD, for host150. Host150may utilize a NVM106included in NVM device102to write and to read data, such as for memory storage, main memory, cache memory, backup memory, or redundant memory. NVM device102may be an internal storage drive, such as a notebook hard drive or a desktop hard drive. NVM device102may be a removable mass storage device, such as, but not limited to, a handheld, removable memory device, such as a memory card (e.g., a secure digital (SD) card, a micro secure digital (micro-SD) card, or a multimedia card (MMC)) or a universal serial bus (USB) device, provided such memory device supports a communications protocol that enables direct memory access. NVM device102may take the form of an embedded mass storage device, such as an eSD/eMMC embedded flash drive, embedded in host150. NVM device102may also be any other type of internal storage device, removable storage device, embedded storage device, external storage device, or network storage device.

Host150may include a wide range of devices, such as computer servers, network attached storage (NAS) units, desktop computers, notebook (i.e., laptop) computers, tablet computers (i.e., “smart” pad), set-top boxes, telephone handsets (i.e., “smart” phones), televisions, cameras, display devices, digital media players, video gaming consoles, video streaming devices, and automotive applications (i.e., mapping, autonomous driving). In certain embodiments, host150includes any device having a processing unit or any form of hardware capable of processing data, including a general purpose processing unit, dedicated hardware (such as an application specific integrated circuit (ASIC)), configurable hardware such as a field programmable gate array (FPGA), or any other form of processing unit configured by software instructions, microcode, or firmware.

Host150includes a central processing unit (CPU)152connected through a root complex153to a memory address space154, such as DRAM or other main memories. Root complex153may be integrated with CPU152or may be a discrete component. An application program may be stored to memory address space154for execution by components of host150. Host150includes a bus156, such as a storage device interface, which interacts with a host interface101of NVM device102. Bus156and host interface101operate under a communication protocol118,120such as a Peripheral Component Interface Express (PCIe) serial communication protocol or other suitable communication protocols. Other suitable communication protocols include ethernet or any protocol related to remote direct memory access (RDMA) such as Infiniband, iWARP, or RDMA over Converged Ethernet (RoCE) and other suitable serial communication protocols.

In the PCIe communication protocol, host150sends commands as transaction packets (TLPs). A TLP includes an address field specifying that the read or write information being sought is located in NVM106of NVM device102. The TLP may include other fields such as an Fmt field, Type field, TC field, TD field, CRC, Length field, Requester ID field, Tag field, and other fields. Controller110may use the address field to access the data at the location specified.

NVM106of NVM device102may be configured for long-term storage of information as non-volatile memory space and retains information after power on/off cycles. NVM106may consist of one of more dies of NAND flash memory. Other examples of non-volatile memory include phase change memories, ReRAM memories, MRAM memories, magnetic media (including shingle magnetic recording), optical disks, floppy disks, electrically programmable read only memories (EPROM), electrically erasable programmable read only memories (EEPROM), and other solid-state memories. Magnetic media non-volatile memory may be one or more magnetic platters in NVM device102. Each platter may contain one or more regions of one or more tracks of data. NVM106may include one or more types of non-volatile memory.

Controller110manages operations of non-volatile memory device102, such as writes to and reads from NVM106. Controller110may include one or more processors130, which may be multi-core processors. Processor130handles the components of NVM device102through firmware code. Controller110interfaces with host150through host interface101which may include mac and phy components. Host interface101interfaces with NVM106through a NVM interface114.

Controller110may operate under NVM Express (NVMe) protocol, but other protocols are applicable. NVMe is a communications interface/protocol developed for SSDs to operate over a host and storage device linked over a PCIe interface. The interface provides a command queue and completion path for SSDs, such as SSDs having NVM106of NAND flash memory. NVMe includes support for enterprise capabilities, such as end-to-end data protection, enhanced error reporting, and virtualization.

Controller110also includes volatile memory112or cache buffer(s) for short-term storage or temporary memory during operation of NVM device102. Volatile memory112does not retain stored data if powered off. Examples of volatile memories include random access memories (RAM), dynamic random access memories (DRAM), static random access memories (SRAM), and other forms of volatile memories.

Controller110executes computer-readable program code (e.g., software or firmware) executable instructions (herein referred to as “instructions”). The instructions may be executed by various components of controller110, such as processor130, logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, embedded microcontrollers, and other components of controller110.

The instructions are stored in a non-transitory computer readable storage medium. In certain embodiments, the instructions are stored in a non-transitory computer readable storage medium of NVM device102, such as in read-only memory (ROM)113or NVM106. Instructions stored in NVM device102may be executed without added input or directions from host150. In other embodiments, the instructions are transmitted from host150. The stored instructions may be stored in full or in part into volatile memory112of controller110for execution by controller. The controller110is configured with hardware and instructions to perform the various functions described herein and shown in the figures.

NVM device102may also be connected to host150through a switch or a bridge. System100may also include a peripheral device190, such as a camera, connected to bus156of host150or connected to host150through a switch or a bridge. System100may also include second host (not shown) connected to host150through a switch or a bridge.

FIG.1Bis a schematic diagram of a memory map155of memory address space154of host150and NVM106of NVM device102ofFIG.1A. Memory map155is described in reference to system100, but other systems may be applicable. The memory map155shows both driverless access mode and driver access mode of NVM106of NVM device102established by host150.

In driver access mode, host150may activate one BAR124of NVM device102implemented in a PCIe configuration space corresponding to DeviceA_bar0. The PCIe configuration space stores configuration information of NVM device102. Host150accesses the configuration information of NVM device102to implement driver access through NVMe driver layers of host150and NVM device102to access NVM portions106A through106E of NVM device102.

In driverless access mode, host150may activate another BAR124of NVM device102implemented in PCIe memory space or virtual memory space corresponding to DeviceA_bar2. Host150maps the internal registers of NVM portion106B to memory address space154B of host150. Host150may directly read and write to the addresses of memory address space154B in which the PCIe communication protocol automatically conveys the read and write commands to NVM device102. Host150may activate additional BARs124of NVM device102in driverless access mode to provide access to another portion of NVM106of NVM device102. For example, host may activate an additional BAR124of NVM implemented in a PCIe memory space corresponding to DeviceA_bar4 to map the internal registers of NVM portion106D to memory address space154C of host150.

Host150may establish driverless access and/or driver access to a second device, such as a peripheral device or a second NVM device. For example, a second PCIe device may activate a BAR implemented in a PCIe configuration space corresponding to DeviceB_bar0 to provide driver access to the second PCIe device.

FIG.2depicts a schematic diagram illustrating one embodiment of NVMe-based host access200or driver access to NVM230of NVM device202described in reference to system100ofFIG.1, but other systems may be applicable. NVMe-based host access200includes host250managing NVM device202by commands initiated by an application210of host250. Application210of host250sends a command, such as a read or a write command, to a file-system layer212of host250. File-system layer212passes the command to an NVMe device driver214of host250. NVMe device driver214may load and store queue messages from and to DRAM216of host250. NVMe driver214passes the read/write command to a PCIe layer218of host250operating under the PCIe communication protocol.

PCIe layer220of NVM device202receives the command from host250and passes the command to an NVMe layer222of NVM device202. NVMe layer222translates the command into NVMe protocol and passes the command to a front-end layer224of NVM device202. Front-end layer224of NVM device202may include cache management and coherency management of NVM230of NVM device202. Front-end layer224passes the read/write command to a data-path layer226of NVM device202. Data-path layer226accesses a flash translation layer (FTL) module228to determine physical addresses associated with the logical addresses of the command. Data-path layer226accesses a NVM230to read or write the data associated with the command. Data-path layer226receives commands from front-end layer224and address information from FTL module228to initiate read/write operations to NVM230. In sum, when application210provides a NVMe-based access command to NVM device202, the command passes from application210to file-system layer212to NVMe driver214to PCIe layer218of host to PCIe layer220of NVM device to NVMe layer222to front end to data-path layer226accessing FTL module228to NVM230.

FIG.2also illustrates one embodiment of a driverless access route240to NVM230in which NVM230is mapped to a memory space of host250. For example, application210of host250passes a driverless access command to PCIe layer218of host250. PCIe layer220of NVM device202receives the driverless access command from host250and passes the driverless access command to data-path layer226of NVM device202. Data-path layer226module initiates read/write operations to NVM230. In sum, when application210provides a driverless access command to NVM device202, the command passes from application210to PCIe layer218of host to PCIe layer220of NVM device to data-path layer226to NVM230.

In driverless access route240, controller110is instructed to bypass the NVMe file-system tables and to treat a BAR as a virtual-to-physical address mapping. For example, a BAR corresponding to a physical portion of NVM230may be dynamically mapped to logical block addresses. The PCIe protocol enables mapping LBA ranges to its own virtual memory address space and allowing driverless access to these LBAs using PCIe transactions—thus bypassing the NVMe layer. The PCIe protocol is used to bypass the NVMe layer by mapping a specific LBA range and then directly addressing those LBAs through the PCIe layer. Host250may directly access this address space via the PCIe and read to and write to this address space.

In certain embodiments in driverless access route240, controller110may aggregate or bind a plurality of driverless access request into a burst operation to NVM interface114. The plurality of driverless access commands may be aggregated in volatile memory112. NVM interface114may execute the burst operation as a single request to NVM106. For NVM106comprising NAND flash, a burst operation may increase performance since an idle time of the NAND flash dies may be reduced.

In certain aspects, the PCIe translates NVM230in NVM device202into a memory aperture exposing the memory aperture to a memory address space in host250. The PCIe protocol maps the memory aperture to a memory address space on host250. NVM230may appear as simple memory to CPU152reducing submission and completion latency and increasing effective bandwidth utilization.

In certain embodiments, the serial PCIe is used to dynamically map a allocated portion of physical memory to a virtual address space in the host device. For instance, in embodiments where systems operate under the PCIe protocol or any one of its derivatives, devices can be mapped to host memory address space via a BAR.

In driverless access mode, a portion of the NVM230is mapped into the memory space of host250for a certain period of time. The portion of the NVM230allocated may be a subset of the NVM230to reduce complexity. Driverless access route240may include cooperation with FTL module228in which data-path layer226accesses FTL module228for address translation. In other embodiments, driverless access route240may include bypassing of FTL module228. By bypassing FTL module228of NVM device202, host250directly manages NVM230, such as by performing and managing address translation.

Mapping of the physical addresses to a virtual address space of application210provides driverless access into a specific address range through load/store memory transactions of a CPU rather than through read/write regular host transactions. Load/store memory transaction instead of being routed to DRAM216are routed to NVM device102. Driverless access to NVM230reduces the latency between host250and NVM device202by bypassing NVMe driver214of host250and NVMe layer222of NVM device202.

FIG.3depicts a schematic diagram illustrating one embodiment of NVMe-based host access300or driver access of a peripheral device390, such as a camera, to NVM330of NVM device302described in reference to the system ofFIG.1, but other systems are applicable. For example, peripheral device390, such as a PCIe peripheral device, may provide data to be written to a DRAM316. DRAM316sends the data to a file-system layer312. File-system layer312passes the data to a NVMe driver314of host350. NVMe driver314passes the data to PCIe layer318of host350. PCIe layer320of NVM device302receives the data from host350and passes the data to a NVMe layer322of NVM device302. NVMe layer322passes the data to a front-end layer324of NVM device302. Front-end layer324of NVM device302passes the data to a data-path layer326of NVM device302. Data-path layer326accesses a FTL module328to determine physical block addresses associated with the logical addresses of the data. Data-path layer326accesses a NVM330to write the data to NVM330. In sum, when peripheral device390provides a NVMe-based access to NVM330, the data passes from peripheral device390to DRAM316to file-system layer312to NVMe driver314to PCIe layer318of host to PCIe layer320of NVM device to NVMe layer322to front end layer324to data-path layer326accessing FTL module328to NVM330.

FIG.3also illustrates one embodiment of a writing path of a driverless access route340to NVM330. In one embodiment of a writing path of a driverless access route340, peripheral device provides data to be written to PCIe layer318of host350. PCIe layer320of NVM device302receives the data from host350and passes the data to data-path layer326of NVM device302. Data-path layer326accesses NVM330to write the data to NVM330. In sum, when peripheral device390provides a driverless write data to NVM330, the data passes from peripheral device390to PCIe layer318to PCIe layer320of NVM device302to data-path layer326to NVM330.

A much shorter PCIe-to-PCIe route is enabled by driverless access route340. In driverless access route340, controller110is instructed to bypass the NVMe file-system tables and to treat an allocated BAR as a virtual-to-physical address mapping. The PCIe protocol enables mapping LBA ranges to its own virtual memory address space and allowing direct access to these LBAs using PCIe transactions—thus bypassing the NVMe layer. The PCIe protocol is used to bypass the NVMe layer by mapping a specific LBA range and then directly addressing those LBAs through the PCIe layer. Host350may directly access this address space via the PCIe and read to and write to this address space.

In certain embodiments in driverless access route340, controller110may aggregate or bind a plurality of driverless access request into a burst operation to NVM interface114. The plurality of driverless access commands may be aggregated in volatile memory112. NVM interface114may execute the burst operation as a single request to NVM device102. For NVM device102comprising NAND flash, a burst operation may increase performance since an idle time of the NAND flash dies may be reduced.

Driverless access route340may include cooperation with FTL module328in which data-path layer326accesses FTL module328for address translation. In other embodiments, driverless access route340may include bypassing of FTL module328. By bypassing FTL module328of NVM device302, host350directly manages NVM330, such as by performing and managing address translation.

Mapping of the physical addresses to a virtual address space allocated to peripheral device390provides driverless access into a specific address range through load/store memory transactions of CPU rather than through read/write regular host transactions. Driverless access to NVM330reduces the latency between peripheral device390and NVM device302by bypassing NVMe driver314of host350and NVMe layer322of NVM device302.

In certain embodiments, host350may configure peripheral device390to a BAR corresponding to an allocated portion of NVM106of NVM device102, such a writing configuration commands to a PCIe controller of host350and/or NVM device302. In certain embodiments, the allocated BAR memory may be accessed by peripheral device390(or a second host) without involving an operating system of host350, such as by accessing the allocated BAR memory through the firmware or other components of host350.

In certain aspects, driverless access route340avoids routing data, such as data to be written, to be buffered in DRAM316and then routed to file-system layer312, NVMe driver314, and then PCIe layer318. If a BAR allocation is made, then data may be directly routed to NVM330of NVM device302through the memory aperture.

In certain aspects, driverless access route340provides improved performance for sequential writing of data from peripheral device390, such as a camera, into NVM330of NVM device302. For example, sequential writing of data may comprise large amount of data that is written to a sequential pattern of pages of NVM330. Driverless access route340may provide a low latency, high bandwidth access to NVM330by bypassing the communication protocol, such as NVMe, and other layers in host350and in NVM device302.

Driverless access route340may also be used for in-place-code execution of code stored on peripheral device390. For example, in NVMe-based host access300, peripheral device390may provide commands to be executed to the DRAM316. DRAM316sends the commands to be executed to a file-system layer312. File-system layer312passes the commands to be executed to NVMe driver314of host350. NVMe driver314passes the commands to be executed to PCIe layer318of host350. PCIe layer320of NVM device302receives the commands to be executed from host350and passes the commands to be executed to NVMe layer322of NVM device302for execution.

In driverless access route340, peripheral device390may provide commands to be executed from code stored on peripheral device390to PCIe layer318of host350. PCIe layer318directly sends the commands to be executed to PCIe layer320of NVM device302. PCIe layer320of NVM device302executes the commands. Driverless access route340allows directly executing the commands from code stored on peripheral device390and avoids storing the code to DRAM316of host350as well as bypassing other layers of host350and NVM device302. Therefore, driverless access route340may provide low latency execution of code stored on peripheral device390.

FIG.4depicts a schematic diagram illustrating one embodiment of a method400of accessing NVM106of NVM device102by host150described in reference to system100ofFIG.1, although other system may be applicable. Method400includes accessing NVM106of NVM device102by host150in both driver access mode and driverless access mode. One or more blocks of method400may be performed by CPU152, controller110, or other controllers executing computer-readable program code (e.g., software or firmware) executable instructions stored in NVM device102or host150.

At block410, a portion of NVM106is dynamical mapped by host150through a communication protocol, such as through PCIe protocol, into memory address space154of host150. A size of the portion of the NVM may be dynamically allocated by host based upon the requirements or needs of the host. Host150may dynamically map NVM106into memory address space154of host150by activating one or more BARs corresponding to various portions of NVM106of NVM device102.

At block420, a driverless access command is received by controller110of NVM device102. For example, the driverless access command may be received through memory aperture236mapping the portion of NVM106into memory address space154.

At block430, the driverless access command is routed to bypass a host interface protocol layer, such as an NVMe layer.

At block440, the portion of NVM106mapped into memory address space154of host150is accessed in response to the driverless access command. For example, the portion of NVM106mapped into memory address space154may be accessed through memory aperture236. Host150and NVM device102may align on an alignment size to complete the driverless access command. In certain embodiments, the alignment size may be greater than one byte for NVM programmed and read by multiple bytes, such as when the NVM comprises NAND flash.

Blocks410,420,430,440may be repeated to remap another portion of the NVM106through the communication protocol into memory address space154of host150. For example, a second BAR may be activated corresponding to another portion of NVM106. NVM106may be remapped through the communication protocol into memory address space154of host150to change an allocated size of NVM106.

At block450, a driver access command by the controller of the non-volatile memory device is received. The driver access command may be through a host interface, such as NVMe interface.

At block460, the driver access command is routed to the host interface protocol layer. For example, the driver access command is routed to the host interface protocol layer of the host through communication protocol of NVM device102.

At block470, another portion of NVM106of NVM device102through the host interface protocol layer is accessed in response to the driver access command. In one embodiment, two separate portions of NVM may be simultaneously allocated for driverless access at block440and for driver access at block470. For example, one portion of NVM106may be is mapped into memory address space154of host150by activating a BAR corresponding to a portion of NVM106of NVM device102for driverless access and another portion NVM106may be allocated for driver access.

In another embodiment, overlapping portions of NVM106may be allocated for driverless access at block440and for driver access at block470. For example, one BAR corresponding to the portion of NVM106for driverless access may be active while driver access may be inactive. Similarly, one BAR corresponding to the portion of NVM106for driverless access may be inactive while driver access may be active.

Method400provides both driverless access and driver access to NVM device102using the same communication protocol, such as a PCIe communication protocol. NVM device102over the same communication protocol may complete driverless access commands and driver access commands at the same time using different LBA ranges. NVM device102over the same communication protocol may complete driverless access commands and driver access commands at the different times using overlapping LBA ranges.

In certain embodiments, driver access may be NVMe-based access over PCIe. In certain embodiments, driverless access may be accomplished by mapping of NVM106by a PCIe BAR, such as PCIe BAR4, to memory address space154of host150. Host150may queue NVMe commands while also sending load/store direct access commands to PCIe BAR mapped to NVM106.

Host150or peripheral device190may use driverless access to reduce latency. Driverless access may be used to reduce latency for sequential data writes/reads to NVM106since buffering of the accessed data may be avoided. Driverless access may be used to reduce latency for any type of data, sequential or random, since NVMe layers and other layers are bypassed in host150and in NVM device102. Method400may apply to any access commands, such as a single access command or multiple access commands, of NVM106of NVM device102.

FIG.5depicts a schematic diagram illustrating one embodiment of a method500of operating NVM device102in a driverless access mode described in reference to system100ofFIG.1, although other NVM devices may be applicable. One or more blocks of method500may be performed by controller110executing computer-readable program code (e.g., software or firmware) executable instructions stored in NVM device102or host150.

At block510, a PCIe memory space is initialized mapping a portion of NVM106of the NVM device102to host memory space154. Mapping is conducted through a PCIe link between host150and NVM device102.

At block520, available or preferred alignment modes are advertised or transmitted by NVM device102. The alignment size may be negotiated before or after activating a BAR. NVM device102may advertise a list of preferred alignment modes. Since byte access is non-optimal to NVM106for embodiments in which the NVM is programmed and read by a plurality of bytes, NVM device102may align on an alignment size. For example, NVM device102may transmit or advertise a preferred alignment size of 64 bytes or larger, such as the size of one page or more of NAND memory. NVM device102may further provide a list of other alignment parameters supported.

At block530, an alignment selection of an alignment size is received by NVM device102. The alignment selection is from host150or peripheral device190connected to host150. After negotiation of an alignment size, transaction packets are transmitted in the alignment size or multiples of the alignment size to complete the driverless access commands.

NVM device102may receive an alignment mode selection of other alignment parameters. Driverless access mode may be established as part of this negotiation. For example, NVM device102may be aligned with host150in dynamic alignment in which the alignment size varies according to the requirements or needs of host150. For example, one or more driverless access commands are conducted in one alignment size and one or more other driverless access commands are conducted in another alignment size. In other embodiments, NVM device102may be aligned with host150in static alignment in which each driverless access command is conducted in the same alignment size (i.e., transaction packets transmitted in the alignment size or multiples of the alignment size).

If an alignment selection is not received by NVM device102after a time-out period, driverless access mode may be established in a default alignment size. In other embodiments, blocks520and530may be skipped with driverless access mode established in a default alignment size.

At block540, a BAR corresponding to a portion of NVM106of NVM device102is activated. After the BAR is activated, transaction packets are transmitted by host150and NVM device102in the alignment size or multiples of the alignment size. The transaction packets addressed to the logical address of host memory space154will be sent to NVM device102bypassing the NVMe layer of the NVM device102. The BAR may be deactivated to provide driver access to the same portion of NVM106of NVM device102. Blocks510,520,530, and540may be repeated to activate other BARs124of NVM device102. Blocks510,520,530, and540may be repeated to re-established driverless access mode to a BAR with a different size of NVM106of the NVM device102and/or different alignment size.

At block550, NVM device102receives access requests in the aligned alignment size or default alignment size to the activated BARs in driverless access mode.

In certain aspects of method500, NVM device102negotiates and aligns with host150or peripheral device190on the access alignment size. NVM device102can provide driverless access in a non-byte (more than one byte) resolution to host150or peripheral device190. For example, for NVM106made of NAND flash, single byte or a few byte transaction size is difficult to support since several bytes are program and read by page of NAND flash array. Host150or peripheral device190may choose which access alignment size based upon performance or application requirements. In certain aspects, driverless memory access allows working with dynamic read/write alignment sizes. By reviewing host planned operations, the pipeline between host150and NVM device102may be configured to increase performance by selectively using of driverless access to memory aperture236.

In certain aspects, reduced latency may be achieved for host150, for NVM device102, or for both host150and NVM device102. Bypassing NVMe driver214,314of host250,350and NVMe layer222,322of NVM device202,302may provide reduced latency for host150and/or NVM device302. Along with reduced latency, increased throughput of data access writes/reads may be achieved. Along with reduced latency, reduced power consumption by host150and/or NVM device102may be achieved.

In certain aspects, quality of service (QoS) levels or input/output operations per seconds (IOPS) levels during mapping may be determined. For example, a portion or all of NVM106of NVM device102may be mapped to memory address space154of host150to provide a flexible QoS or IOPS levels. Host150may communicate to allocate resources under agreed to or certain parameters. In certain embodiments, if low latency is desired, then a large portion of NVM106may be allocated to driverless access mode. In certain embodiments, portions of NVM106may be allocated dynamically for driverless access in an as-needed basis. For example, a BAR mapping a portion of NVM106may be un-mapped and re-mapped dynamically to adjust the amount of storage space needed by host150.

In certain embodiments, host150send driverless commands to the NAND flash by sending commands through memory aperture236bypassing several hardware and firmware components to perform debug operations and isolate errors in NVM106of NVM device102. Driverless access of NVM106, such as driverless access of a NAND flash die, may reduce debug effort by focusing on the critical component of NVM106and bypassing physical links and circuitry connecting host150and NVM106.

In certain embodiments, NVM device102may be accessed on a dynamic basis (i.e., the same NVM device may provide driver access mode and driverless access mode at the same time). Both modes may operate in parallel, for example, a BAR for one portion of NVM106of NVM device102may be allocated for driverless access and another portion of NVM106of NVM device102may be allocated to driver access. In other words, driverless access and driver access may be accessing different physical addresses of NVM106of NVM device102.

In certain embodiments, driverless access to NVM106of NVM device102may be through load/storage commands received from host150and driver access may be through read/write commands received from host150.

In certain embodiments, NVM106appears as a memory to CPU152in driverless access mode. In optional embodiments, communication protocols for driverless access mode may be performed by an intermediate controller. Intermediate controller may optionally perform error checking, buffering of incoming commands, and/or wear leveling. Driverless access may be performed on any system100operating under a communication protocol to reduce submission and completion latency and increases effective bandwidth utilization.

Bypassing one or more components of the chipset of host150may reduce an amount of time to transfer the data between host150and NVM device102as compared to routing the data via the application processor and/or the main memory (i.e., DRAM) of the chipset. By bypassing one or more components of the chipset during the transfer of the data, a power consumption of the chipset may be reduced.

In some embodiments, communication between host150and NVM device102may pass through several electrical links, each connected by an interconnect switch or by a protocol bridge adaptor. In such embodiments, communication along each link may be negotiated according to a different protocol. For instance, a command placed in command queue may be routed through a PCIe root port, switch to a computer-networking communications standard link via a network adaptor, and then switch back to PCIe before arriving at NVM device102.

In certain aspects, providing driverless access to NVM106of NVM device102in the embodiments described herein, other driverless access through the PCIe protocol, other direct access through the PCIe protocol, or other direct access through other communication protocols (collectively referred to as “direct access”) may make the NVM device102vulnerable to security violations. Direct access may reduce the effectiveness of standard security protection tools which are operated at the host level. For example, in a direct access mode established between host150and NVM device102, an unauthorized or hacking device or program may bypass permissions, NVMe security protocols, and other security layers. A hacking device or program may identify that NVM device102is in direct access mode with host150and may attempt to establish its own access with NVM device102through a mapped memory aperture of NVM106into memory address space154of host150. A hacking device or program may take control of the mapped portions of NVM106. A hacking device or program with access to NVM device102through a memory aperture may have undesired read and write access to critical areas, such as system files, boot files, passwords, management tables, firmware, and erased/invalid data. Such security violations may be difficult to detect.

FIG.6depicts a schematic diagram of one embodiment of a controller610of a NVM device having an anomaly detector module620. The controller610may be implemented in NVM device102ofFIG.1, although other NVM devices may be applicable.

FIG.7depicts a schematic diagram illustrating one embodiment of a method700of operating a NVM device by controller610ofFIG.6, although other NVM devices may be applicable. Method700includes providing access to NVM106of NVM device102in direct access mode and detecting potential security violations. Method700is described in reference to system100and controller610, but other systems and controllers may be used. One or more blocks of method700may be performed by controller610executing computer-readable program code (e.g., software or firmware) executable instructions stored in NVM device102.

The one or more parameters are tracked from a PCIe layer690of controller610providing a direct access to NVM106. Tracking or monitoring of direct access transactions of host150may comprise tracking or monitoring all direct access transactions or may comprise tracking or monitoring a sample or a portion of direct access transactions. In certain embodiments, multiple transactions may be tracked or monitored to create a history of the transactions. For each transaction of the multiple transactions tracked or monitored, one or more parameters may be tracked or monitored. A rate of change of one or more parameters may be determined over the course of multiple transactions. For example, a rate at which certain logical block addresses are accessed may be tracked or monitored.

At block720, a normal-pattern-fitting module640of controller610determines a threshold for a normal behavior pattern. The threshold for a normal behavior pattern may be determined by the one or more parameters tracked at block710, by contents of accessed data tracked at block710, by data accumulated at performance testing, and/or by off-line settings. The threshold for a normal behavior pattern may be updated as new information is accumulated from block710. In one aspect, NVM device102determines a pattern of the parameters gathered at block710or the statistics or probability of a transaction or a parameter of a transaction occurring.

In one embodiment, block720may be conducted online as NVM device102is in operation. In another embodiment, a threshold behavior pattern may be set by a user mode page as NVM device102is in operation. In another embodiment, block720may be conducted offline, such as during qualification of NVM device102. For example, a lookup table or a dictionary of a normal behavior may be created offline and uploaded to NVM device102.

At block730, an anomaly determination module650of controller110determines whether a threshold for a normal behavior pattern has been exceeded for the threshold behavior pattern determined at block720. For example, anomaly determination module650determines if a transaction is an outlier to the pattern determined at block720. In certain embodiments, determining whether a threshold for a normal behavior pattern has been exceeded may by based on one or more of the following categories of techniques: an unsupervised learning operation (an operation based upon determining a pattern), an supervised learning operation (an operation based upon a data set example of both normal and abnormal transactions), or a semi-supervised learning operation.

In certain embodiments, determining whether a threshold has been exceed may be based upon one or more of the following techniques: density-based techniques (e.g. k-nearest neighbor, local outlier factor), subspace and correlation-based outlier detection for high-dimensional data, one class support vector machines, replicator neural networks, cluster analysis-based outlier detection, deviations from association rules and frequent item sets, fuzzy logic based outlier detection, and ensemble techniques (i.e., using feature bagging, score normalization, different sources of diversity, etc.). For example, an excess number of read/writes to a small portion of an address space may indicate suspicious direct access transactions. In another example, a pattern of multiple read transactions with isolated write transactions may indicate suspicious direct access transactions.

At block740, a countermeasure module660of controller610may perform a countermeasure if the threshold has been determined to be exceeded at block730. One example of a countermeasure includes providing an alert when a threshold is exceeded or an anomaly is detected. The alert may be sent to host150. The alert may also include a confidence level of whether the anomaly detected is a low security risk, a medium security risk, or a high security risk. The alert may also enable feedback on whether the host approves or disapproves of the suspicious transaction.

Another example of a countermeasure includes identifying a source of the problematic access command by examination of a source identified through root-complex153, such as review of the enumeration information. Another example of a countermeasure includes selectively blocking an identified source of the problematic direct access transactions. Another example of a countermeasure includes selectively throttling or delaying access to an identified source of the problematic direct access transactions. Throttling or delayed access may be increased if suspicious direct access commands continue.

Another example of a countermeasure includes creating a log of the alerts or the instances a threshold is exceeded or an anomaly is detected. The log may include one or more parameters tracked at block710. The log may include a history of the alerts or the instances a threshold is exceeded or an anomaly is detected. The log may include a confidence level of whether the anomaly detected is a low security risk, a medium security risk, or a high security risk. The log may be stored in NVM106. In one embodiment, host150may review the log. In another embodiment, controller610may use the log in combination with other countermeasures. For example, following a certain number, rate (i.e., soon one after the other), and/or severity of alerts or instances of a threshold is exceeded or an anomaly is detected, NVM device102may increase the severity of the countermeasures. Anomaly detector module620may start with any countermeasure and increase to any other countermeasure. For example, anomaly detector module620may start with throttling as a countermeasure and then increase the countermeasure to blocking if the anomalies continue or increase.

In certain embodiments, anomaly detection of direct access of NVM106of NVM device102is provided. Anomaly detection by NVM device102may identify potential security violations which cannot or are not identified by host150. A countermeasure from anomaly detection may be a static action, such as a notification to host150, or an active action, such as throttling access or blocking access. In certain embodiments, the countermeasure may switch from a static action to an active action if suspicious direct access commands continue.

In certain embodiments, security protections in regards to direct access transactions are provided by NVM device102. Security protections may include identifying suspicious transactions and may include identifying the source of suspicious direct access commands. Security protections may include implementing countermeasures when suspicious direct access transactions are identified. In certain aspects, these security protections may not be bypassed in direct access mode.

FIG.8depicts a schematic diagram of one embodiment of memory mapped regions800. The memory mapped regions800includes a device mapped memory810and a host mapped memory820. The device mapped memory810includes a configuration (config) space812, NVMe registers814, a MSI-X table816, and a persistent memory region (PMR)818. The device mapped memory810is accessible to the host and to peers, such as the GPU. The host mapped memory820includes submission queue (SQ) and completion queue (CQ) pairs822, host data areas824, and a peer mapping space826. The host mapped memory820is accessible to the data storage device using a physical address located in the host DRAM.

The host, such as the host150ofFIG.1A, is able to utilize the config space812to configure the registers using PCIe protocol. Likewise, host150is able to configure the NVMe Registers814. The MSI-X table816is for interrupts, such as the interrupt generated during the execution of a command. The PMR818is an area of the non-volatile memory dedicated to the host150for read-only DMA operations, that is power-fail protected.

The SQ and CQ pairs822store commands not yet executed in the submission queue and completion messages for commands executed in the completion queue. The host data areas824store host data, and the peer mapping space826is a region of memory that the processors of the system, such as the processor130ofFIG.1A, are able to access.

FIGS.9A and9Bdepict a schematic diagram of one embodiment of an NVMe queue structure. The SQ and the CQs are maintained in the host memory, such as the SQ and CQ pairs822ofFIG.8. Each block represents a location for a SQ entry or a CQ entry. Each queue has equal weight and a burst size of 1 in the current embodiment. Commands are pulled sequentially from each queue. Other combinations are possible, such as a higher queue depth, a variable weight in each queue, and a different burst size, which will be reflected in the number of commands retrieved from each queue. In certain embodiments, some commands will have higher priority than others and will be placed closer to the head of a given queue. For example, admin commands have a higher priority than input/output (I/O) commands, but typically, these commands are not aggregated into the I/O queue but have a separate internal queue.

Referring toFIG.9B, the aggregate I/O queue includes each of the SQ commands, for example, according to priority, wherein the SQ commands are aggregated left to right into the aggregate I/O queue. For example, a first command is taken from SQ1, a second command is taken from SQ2, a third command is taken from SQ3, a fourth command is taken from SQ4, and a fifth command is taken from SQ1. The process continues until no more commands are in the SQs.

FIGS.10A and10Bdepict a schematic diagram of one embodiment of the PMR queue structure.FIGS.10A and10Bare similar toFIGS.9A and9B. However, as illustrated inFIG.10A, a PMR range is mapped from the NVM device, such as the NVM device102ofFIG.1A. The entries in the PMR range ofFIG.10Aare mapped into a PMR queue, as illustrated inFIG.10B. As direct memory access (DMA) requests are received in the PMR region, the controller, such as the controller110ofFIG.1A, will automatically translate them into dummy NVMe commands (i.e., indirect commands) and store them within the PMR queue. Such commands stored in the PMR queue, in certain embodiments, have a higher priority than corresponding host commands stored in the SQs. The payload returned from the internally executed dummy NVMe command is stored in a buffer, which is used to complete the DMA request.

As memory reads are submitted, controller110will mark the corresponding LBA ranges for overlap, such that coherency is ensured between these reads and writes from other queues. Since the PMR queue has a higher priority than host-facing queues (i.e., the SQs), the read coherency against host writes to the same region of the NVM, such as the NVM106ofFIG.1A, may be maintained, according to certain embodiments. As shown inFIG.10B, the PMR range entries are placed into the PMR queue and are pulled first into the aggregate I/O queue. In some examples, if a command has already begun processing in the aggregate queue, the controller110may pre-empt a PMR queued command. Furthermore, the PMR queue may include both a submission queue and a command queue for PMR queued commands.

FIG.11depicts a schematic diagram illustrating one embodiment of a method1100of accessing a PMR. At block1110, a PMR access request is received by the controller, such as the controller110ofFIG.1A. In certain embodiments, the PMR access request may be received via a PCIe link between a host, such as host150ofFIG.1A, and an NVM device, such as the NVM device102ofFIG.1A. The PCIe link may be initialized during the NVM device boot, where the PCIe memory space maps a portion of an NVM, such as the NVM106, to a host memory space. The PMR access request may be for driverless access. The PMR access request or command may be a direct access command (i.e., a DMA request). Furthermore, a processor may be configured to complete the same tasks as the controller110. At block1120, controller110translates the command to a namespace (NS)/LBA offset and length. At block1130, internal memory in the NVM is allocated for the command payload.

At block1140, a load/store command is generated for the PMR access request. The load/store command is a dummy NVMe indirect command. The load/store command is placed in a PMR queue, such as the PMR queue described inFIG.10B. At block1150, the commands of the PMR queue and the commands of the SQs are arbitrated, where the PMR queue has the highest priority. The arbitrated queue may resemble the aggregated I/O queue illustrated inFIG.10B. Furthermore, the SQs may be NVMe queues. At block1160, the load/store commands in the arbitrated queue are processed using the normal read path. However, the load/store commands are processed with an internal memory target. At block1170, the PMR access from internal memory is completed.

FIG.12depicts a schematic diagram illustrating one embodiment of a method1200of driverless access of the NVM. Aspects ofFIG.1Amay be referenced in the following description as non-limiting examples. At block1210, a controller110initializes a PCIe memory space, mapping a portion of an NVM106of the NVM device102to a host memory space through a PCIe link between a host150and the NVM device102. The PCIe memory space is initialized by activating a BAR124corresponding to a physical region of NVM106of the NVM device102. At block1220, controller110sends load/store commands to the PCIe memory space for driverless access (i.e., the direct memory access request). The load/store commands are generated dummy NVMe commands for indirect access associated with the direct memory access requests.

At block1230, the load/store commands are placed in a PMR queue in the NVM device102. The PMR may be mapped to a volatile memory112, such as the DRAM, of the NVM device102. At block1240, the load/store commands located in the PMR queue are aggregated with one or more commands of an NVMe queue, such as the plurality of SQs. The aggregated commands may resemble the aggregate I/O queue ofFIG.10B.

By including a PMR for arbitrary ranges of storage-backed memory, coherency between direct access and NVMe access may be improved, leading to improved data storage device operation.

In one embodiment, a controller is disclosed that includes a memory comprising computer-readable instructions for a method for driverless access of a non-volatile memory device by a host and a processor configured to execute the executable instructions. In certain embodiments, the executable instructions cause the controller to initialize a PCIe memory space mapping a portion of the non-volatile memory device to a host memory space through a PCIe link between the host and the non-volatile memory device and send load/store commands to the PCIe memory space for driverless access. The executable instructions further cause the controller to place the load/store commands in a persistent memory region (PMR) queue of the non-volatile memory device and aggregate the load/store commands of the PMR queue with one or more commands of a Non-Volatile Memory express (NVMe) queue.

The processor is further configured to cause the system to process the load/store commands using an NVMe read path. The processor is further configured to cause the system to process the load/store commands at a persistent memory region (PMR) of the non-volatile memory device. At least one of the load/store commands receives a higher priority than at least one of the one or more commands of the NVMe queue. Each of the load/store commands has additional memory allocated to conform to NVMe command payload size. The PMR queue comprises a submission queue and a command queue. The load/store commands are placed in the PMR queue by a controller of the non-volatile memory device.

In another embodiment, a data storage device is disclosed that includes a controller configured to execute a method of driver access and driverless access of a non-volatile memory device by a host. In certain embodiments, the method includes initializing a PCIe memory space mapping a portion of the non-volatile memory device to a host memory space through a PCIe link between the host and the non-volatile memory device, initializing a PCIe configuration space with configuration information of the non-volatile memory device, and sending load/store commands to the PCIe memory space for driverless access. The method further includes sending read/write commands to an NVMe driver of the host for driver access utilizing the configuration information of the non-volatile memory device, and providing the load/store commands and read/write commands to an aggregated command queue for processing by the non-volatile memory device.

The PCIe memory space is initialized by activating a BAR corresponding to a physical region of the non-volatile memory device. The NVMe driver sends read/write commands to an NVMe layer of the non-volatile memory device. At least one of the load/store commands receives a higher priority than at least one of the read/write commands. Each of the load/store commands has additional memory allocated to conform to a command payload size of the read/write commands. The load/store commands are provided to a persistent memory region (PMR) queue. The PMR queue comprises a submission queue and a completion queue. The load/store commands are placed in the PMR queue by a controller of the non-volatile memory device.

In another embodiment, a system for storing data is disclosed, including one or more non-volatile memory means, and a controller means configured to carry out a method to maintain coherency between PMR and NVMe data transactions. In certain embodiments, the method includes establishing a PCIe link between a host and the non-volatile memory means and an NVMe link between the host and the non-volatile memory means, initializing a PCIe memory space mapping one or more portions of the non-volatile memory means to a host memory space through a PCIe link between the host and the non-volatile memory means, and sending load/store commands to the PCIe memory space for driverless access. The method further includes placing the load/store commands in a persistent memory region (PMR) queue of the non-volatile memory means, and aggregating the load/store commands of the PMR queue with one or more read/write commands of a Non-Volatile Memory express (NVMe) queue.

The method includes at least one of the load/store commands that receives a higher priority than at least one of the one or more read/write commands of the NVMe queue. The method further includes processing the load/store commands at a PMR of the non-volatile memory means. The method further includes processing the load/store commands using an NVMe read path. Each of the load/store commands has additional memory allocated to conform with NVMe read/write command payload size.