Semiconductor device and method of manufacturing the same

A semiconductor device having favorable electric characteristics is provided. The semiconductor device includes a first transistor and second transistor. The first transistor includes a first conductor over a substrate; a first insulator thereover; a first oxide thereover; a second insulator over thereover; a second conductor including a side surface substantially aligned with a side surface of the second insulator and being over the second insulator; a third insulator including a side surface substantially aligned with a side surface of the second conductor and being over the second conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with the first oxide and the fourth insulator. The second transistor includes a third conductor; a fourth conductor at least part of which overlaps with the third conductor; and a second oxide between the third conductor and the fourth conductor. The third conductor and the fourth conductor are electrically connected to the first conductor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

One embodiment of the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. One embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

In this specification and the like, a semiconductor device refers to every device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. A display device (e.g., a liquid crystal display device and a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, and the like may include a semiconductor device.

2. Description of the Related Art

In recent years, semiconductor devices have been developed to be used mainly for an LSI, a CPU, or a memory. A CPU is an aggregation of semiconductor elements each provided with an electrode which is a connection terminal, which includes a semiconductor integrated circuit (including at least a transistor and a memory) separated from a semiconductor wafer.

A semiconductor circuit (IC chip) of an LSI, a CPU, a memory, or the like is mounted on a circuit board, for example, a printed wiring board, to be used as one of components of a variety of electronic devices.

A technique by which a transistor is formed using a semiconductor thin film formed over a substrate having an insulating surface has been attracting attention. The transistor is used in a wide range of electronic devices such as an integrated circuit (IC) or an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film that can be used for a transistor. As another material, an oxide semiconductor has been attracting attention.

It is known that a transistor including an oxide semiconductor has an extremely small leakage current in an off state. For example, a low-power-consumption CPU utilizing a characteristic of small leakage current of the transistor including an oxide semiconductor has been disclosed (see Patent Document 1).

In addition, a technique in which oxide semiconductor layers with different electron affinities (or conduction band minimum states) are stacked to increase the carrier mobility of a transistor is disclosed (see Patent Documents 2 and 3).

In recent years, demand for an integrated circuit in which transistors and the like are integrated with high density has risen with reductions in the size and weight of an electronic device. In addition, the productivity of the semiconductor device including an integrated circuit is required to be improved.

REFERENCE

Patent Document

SUMMARY OF THE INVENTION

An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a semiconductor device that can be manufactured with high productivity.

An object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long time. An object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed data writing. An object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility. An object of one embodiment of the present invention is to provide a low-power semiconductor device. An object of one embodiment of the present invention is to provide a novel semiconductor device.

A first transistor and a second transistor having different electrical characteristics from those of the first transistor are provided over the same layer. For example, a first transistor having a first threshold voltage and a second transistor having a second threshold voltage are provided over the same layer. A semiconductor layer where a channel of the first transistor is formed and a semiconductor layer where a channel of the second transistor is formed are formed using semiconductor materials having different electron affinities.

Providing transistors having different electrical characteristics in one semiconductor device can increase circuit design flexibility. On the other hand, the transistors need to be separately manufactured; thus, the number of manufacturing steps of the semiconductor device is drastically increased. The drastic increase in manufacturing steps easily leads a decrease in yield, and the productivity of the semiconductor device is significantly decreased in some cases. According to one embodiment of the present invention, transistors having different electrical characteristics can be provided in one semiconductor device, without drastic increase in the manufacturing steps.

In the first transistor and the second transistor, an insulator is provided in contact with a side surface of a gate electrode and a side surface of a gate insulator. Note that the insulator is preferably deposited by an atomic layer deposition (ALD) method, in which case an insulator formed of a film with favorable coverage or a dense film can be obtained. The insulator in contact with the side surface of the gate insulator can prevent outward diffusion of oxygen contained in the gate insulator and entry of impurities such as water or hydrogen into the gate insulator.

One embodiment of the present invention is a semiconductor device including a first transistor and second transistor. The first transistor includes a first conductor over a substrate; a first insulator over the first conductor; a first oxide over the first insulator; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator over the second conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with the first oxide and the fourth insulator. The second transistor includes a third conductor; a fourth conductor at least part of which overlaps with the third conductor; and a second oxide between the third conductor and the fourth conductor. The third conductor and the fourth conductor are electrically connected to the first conductor.

One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first transistor includes a first conductor over a substrate; a first insulator over the first conductor; a first oxide over the first insulator; a second oxide in contact with at least part of a top surface of the first oxide; a third oxide in contact with at least part of a top surface of the second oxide; a second insulator over the third oxide; a second conductor over the second insulator; a third insulator over the second conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with the third oxide and the fourth insulator. The second transistor includes a third conductor; a fourth conductor at least part of which overlaps with the third conductor; and a fourth oxide between the third conductor and the fourth conductor. The third conductor and the fourth conductor are electrically connected to the first conductor.

In the above embodiment, each of the first to the fourth oxides preferably includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. In the above embodiment, it is preferable that the first oxide include a first region and a second region that overlaps with the second insulator, at least part of the first region be in contact with the fifth insulator, and the first region have a higher hydrogen concentration and/or a higher nitrogen concentration than the second region. The first region preferably includes a portion overlapping with the fourth insulator and the second insulator. The fifth insulator preferably includes one or both of hydrogen and nitrogen.

One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first transistor includes a first conductor over a substrate; a first insulator over the first conductor; a first oxide over the first insulator; a second oxide in contact with at least part of a top surface of the first oxide; a third oxide in contact with a side surface of the first oxide and a top surface and a side surface of the second oxide, a second insulator over the third oxide; a second conductor over the second insulator; a third conductor over the second conductor; a third insulator over the third conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, a side surface of the third conductor, and a side surface of the third insulator; and a fifth insulator in contact with a top surface of the third oxide and a side surface of the fourth insulator. A top surface of the third insulator and a top surface of the fourth insulator are substantially aligned with each other. The second transistor includes a fourth conductor over the substrate; a first insulator over the fourth conductor; a fourth oxide and a fifth oxide which are apart from each other over the first insulator; a sixth oxide in contact with at least part of a top surface of the fourth oxide; a seventh oxide in contact with at least part of a top surface of the fifth oxide; an eighth oxide in contact with a side surface of the fourth oxide, a side surface of the fifth oxide, a top surface and a side surface of the sixth oxide, and a top surface and a side surface of the seventh oxide and in contact with the first insulator in a region between the fourth oxide and the fifth oxide; a sixth insulator over the eighth oxide; a fifth conductor which is over the sixth insulator and at least part of which overlaps with a region between the fourth oxide and the fifth oxide; a sixth conductor which is over the fifth conductor and at least part of which overlaps with a region between the fourth oxide and the fifth oxide; a seventh insulator over the sixth conductor; an eighth insulator in contact with a side surface of the sixth insulator, a side surface of the fifth conductor, a side surface of the sixth conductor, and a side surface of the seventh insulator; and a fifth insulator in contact with a top surface of the eighth oxide and a side surface of the eighth insulator. A top surface of the seventh insulator and a top surface of the eighth insulator are substantially aligned with each other.

One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first transistor includes a first conductor over a substrate; a first insulator over the first conductor; a first oxide over the first insulator; a second oxide in contact with at least part of a top surface of the first oxide; a third oxide in contact with at least part of a top surface of the second oxide; a second insulator over the third oxide; a second conductor over the second insulator; a third conductor over the second conductor; a third insulator over the third conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, a side surface of the third conductor, and a side surface of the third insulator; and a fifth insulator in contact with a top surface of the third oxide and a side surface of the fourth insulator. A top surface of the third insulator and a top surface of the fourth insulator are substantially aligned with each other. The second transistor includes a fourth conductor over the substrate; a first insulator over the fourth conductor; a fourth oxide and a fifth oxide which are apart from each other over the first insulator; a sixth oxide in contact with at least part of a top surface of the fourth oxide; a seventh oxide in contact with at least part of a top surface of the fifth oxide; an eighth oxide in contact with at least part of a top surface of the sixth oxide and at least part of a top surface of the seventh oxide; a sixth insulator over the eighth oxide; a fifth conductor which is over the sixth insulator and at least part of which overlaps with a region between the fourth oxide and the fifth oxide; a sixth conductor which is over the fifth conductor and at least part of which overlaps with a region between the fourth oxide and the fifth oxide; a seventh insulator over the sixth conductor; an eighth insulator in contact with a side surface of the sixth insulator, a side surface of the fifth conductor, a side surface of the sixth conductor, and a side surface of the seventh insulator; and a fifth insulator in contact with a top surface of the sixth oxide and a side surface of the eighth insulator. A top surface of the seventh insulator and a top surface of the eighth insulator are substantially aligned with each other.

In the above embodiment, each of the first oxide to the eighth oxide preferably contains In, an element M (M is Al, Ga, Y, or Sn), and Zn. It is preferable that the second oxide include a first region and a second region overlapping with the second insulator, at least part of the first region be in contact with the fifth insulator, and the first region have a higher hydrogen concentration and/or a higher nitrogen concentration than the second region. Furthermore, the first region preferably includes a portion overlapping with the fourth insulator and the second insulator.

In the above embodiment, the fourth insulator and the eighth insulator preferably contain aluminum oxide or hafnium oxide. The third insulator and the seventh insulator preferably contain aluminum oxide or hafnium oxide. The thickness of each of the third insulator and the seventh insulator is preferably larger than the thickness of each of the fourth insulator and the eighth insulator. The second conductor and the fifth conductor preferably contain conductive oxide. The fifth insulator preferably contains one or both of hydrogen and nitrogen. The third oxide and the eighth oxide preferably have the same composition.

One embodiment of the present invention is a method of manufacturing a semiconductor device. The method includes the steps of: forming a first conductor and a second conductor over a substrate; forming a first insulator over the first conductor and the second conductor; forming a first oxide film and a second oxide film in this order over the first insulator; processing the first oxide film and the second oxide film into an island shape, thereby forming a first oxide, a second oxide over the first oxide, a third oxide, a fourth oxide over the third oxide, a fifth oxide, and a sixth oxide over the fifth oxide; forming a third oxide film over the first insulator and the first oxide to the sixth oxide; processing the third oxide film into an island shape, thereby forming a seventh oxide that covers the first oxide and the second oxide and an eighth oxide that covers the third oxide to the sixth oxide; forming a first insulating film, a first conductive film, a second conductive film, and a second insulating film in this order over the first insulator and the first oxide to the eighth oxide; etching the first insulating film, the first conductive film, the second conductive film, and the second insulating film, thereby forming a second insulator, a third conductor, a fourth conductor, and a third insulator over the seventh oxide and forming a fourth insulator, a fifth conductor, a sixth conductor, and a fifth insulator over the eighth oxide; forming a third insulating film by an ALD method to cover the seventh oxide, the eighth oxide, the second insulator to the fifth insulator, and the third conductor to the sixth conductor; performing dry etching treatment on the third insulating film, thereby forming a sixth insulator in contact with a side surface of the second insulator, a side surface of the third conductor, a side surface of the fourth conductor, and a side surface of the third insulator and forming a seventh insulator in contact with a side surface of the fourth insulator, a side surface of the fifth conductor, a side surface of the sixth conductor, and a side surface of the fifth insulator; and forming an eighth insulator by a PECVD method to cover the seventh oxide, the eighth oxide, the third insulator, the fifth insulator, the sixth insulator, and the seventh insulator.

One embodiment of the present invention is a method of manufacturing a semiconductor device. The method includes the steps of: forming a first conductor and a second conductor over a substrate; forming a first insulator over the first conductor and the second conductor; forming a first oxide film and a second oxide film in this order over the first insulator; forming an opening in the first oxide film and the second oxide film to expose part of the first insulator; forming a third oxide film over the first oxide film and the second oxide film in which the opening is formed and the exposed first insulator; processing the first oxide film and the second oxide film in which the opening is formed and the third oxide film into an island shape, thereby forming a first oxide, a second oxide over the first oxide, a seventh oxide over the second oxide, a third oxide, a fourth oxide over the third oxide, a fifth oxide, a sixth oxide over the fifth oxide, the eighth oxide over the fourth oxide and the sixth oxide; forming a first insulating film, a first conductive film, a second conductive film, and a second insulating film in this order over the first insulator and the first oxide to the eighth oxide; etching the first insulating film, the first conductive film, the second conductive film, and the second insulating film, thereby forming a second insulator, a third conductor, a fourth conductor, and a third insulator over the seventh oxide and forming a fourth insulator, a fifth conductor, a sixth conductor, and a fifth insulator over the eighth oxide; forming a third insulating film by an ALD method to cover the seventh oxide, the eighth oxide, the second insulator to the fifth insulator, and the third conductor to the sixth conductor; performing dry etching treatment on the third insulating film, thereby forming a sixth insulator in contact with a side surface of the second insulator, a side surface of the third conductor, a side surface of the fourth conductor, and a side surface of the third insulator and forming a seventh insulator in contact with a side surface of the fourth insulator, a side surface of the fifth conductor, a side surface of the sixth conductor, and a side surface of the fifth insulator; and forming an eighth insulator by a PECVD method to cover the seventh oxide, the eighth oxide, the third insulator, the fifth insulator, the sixth insulator, and the seventh insulator.

One embodiment of the present invention can provide a semiconductor device having favorable electric characteristics. One embodiment of the present invention can provide a semiconductor device that can be miniaturized or highly integrated. One embodiment of the present invention can provide a semiconductor device with high productivity.

A semiconductor device capable of retaining data for a long time can be provided. A semiconductor device capable of high-speed data writing can be provided. A semiconductor device with high design flexibility can be provided. A low-power semiconductor device can be provided. A novel semiconductor device can be provided.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not have to have all the effects listed above. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

DETAILED DESCRIPTION OF THE INVENTION

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, the size, the layer thickness, or the region is not limited to the illustrated scale. Note that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to shapes or values shown in the drawings. For example, in the actual manufacturing process, a layer, a resist mask, or the like might be unintentionally reduced in size by treatment such as etching, which is not illustrated in some cases for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and explanation thereof will not be repeated in some cases. Furthermore, the same hatching pattern is applied to portions having similar functions, and the portions are not especially denoted by reference numerals in some cases.

Especially in a top view (also referred to as a “plan view”), a perspective view, or the like, some components might not be illustrated for easy understanding of the invention. In addition, some hidden lines and the like might not be shown.

Note that the ordinal numbers such as “first”, “second”, and the like in this specification and the like are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, description can be made even when “first” is replaced with “second” or “third”, as appropriate. In addition, the ordinal numbers in this specification and the like are not necessarily the same as those which specify one embodiment of the present invention.

In this specification, terms for describing arrangement, such as “over”, “above”, “under”, and “below”, are used for convenience in describing a positional relation between components with reference to drawings. Furthermore, the positional relationship between components is changed as appropriate in accordance with a direction in which each component is described. Thus, there is no limitation on terms used in this specification, and description can be made appropriately depending on the situation.

For example, in this specification and the like, an explicit description “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or texts, another connection relationship is included in the drawings or the texts.

Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

Examples of the case where X and Y are directly connected include the case where an element that allows an electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) is not connected between X and Y, and the case where X and Y are connected without the element that allows the electrical connection between X and Y provided therebetween.

In this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. The transistor has a channel region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel region. Note that in this specification and the like, a channel region refers to a region through which current mainly flows.

Furthermore, functions of a source and a drain might be switched when a transistor of opposite polarity is employed or a direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be switched in some cases in this specification and the like.

Note that the channel length refers to, for example, the distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in a plan view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not fixed to one value in some cases. Thus, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed. In one transistor, channel widths in all regions are not necessarily the same. In other words, the channel width of one transistor is not fixed to one value in some cases. Thus, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter referred to as an “effective channel width”) is different from a channel width shown in a top view of a transistor (hereinafter referred to as an “apparent channel width”) in some cases. For example, in a transistor having a gate electrode covering a side surface of a semiconductor, an effective channel width is greater than an apparent channel width, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a gate electrode covering a side surface of a semiconductor, the proportion of a channel formation region formed in a side surface of a semiconductor is increased. In that case, an effective channel width is greater than an apparent channel width.

In such a case, an effective channel width is difficult to measure in some cases. For example, to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known as an assumption condition. Accordingly, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure an effective channel width accurately.

Thus, in this specification, an apparent channel width is referred to as a surrounded channel width (SCW) in some cases. Furthermore, in this specification, in the case where the term “channel width” is simply used, it may represent a surrounded channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may represent an effective channel width. Note that a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by analyzing a cross-sectional TEM image and the like.

Note that an impurity in a semiconductor refers to, for example, elements other than the main components of a semiconductor. For example, an element with a concentration lower than 0.1 atomic % can be regarded as an impurity. When an impurity is contained, the density of states (DOS) in a semiconductor may be increased, or the crystallinity may be decreased. In the case where the semiconductor is an oxide semiconductor, examples of an impurity which changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor; there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example. For an oxide semiconductor, water also serves as an impurity in some cases. For an oxide semiconductor, entry of impurities may lead to formation of oxygen vacancies, for example. Furthermore, when the semiconductor is silicon, examples of an impurity which changes the characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

In this specification and the like, a silicon oxynitride film contains more oxygen than nitrogen. A silicon oxynitride film preferably contains, for example, oxygen, nitrogen, silicon, and hydrogen in the ranges of 55 atomic % to 65 atomic % inclusive, 1 atomic % to 20 atomic % inclusive, 25 atomic % to 35 atomic % inclusive, and 0.1 atomic % to 10 atomic % inclusive, respectively. A silicon nitride oxide film contains more nitrogen than oxygen. A silicon nitride oxide film preferably contains nitrogen, oxygen, silicon, and hydrogen in the ranges of 55 atomic % to 65 atomic % inclusive, 1 atomic % to 20 atomic % inclusive, 25 atomic % to 35 atomic % inclusive, and 0.1 atomic % to 10 atomic % inclusive, respectively.

In addition, in this specification and the like, the term “insulator” can be replaced with the term “insulating film” or “insulating layer.” Moreover, the term “conductor” can be replaced with the term “conductive film” or “conductive layer.” Furthermore, the term “semiconductor” can be replaced with the term “semiconductor film” or “semiconductor layer.”

Furthermore, unless otherwise specified, transistors described in this specification and the like are field effect transistors. Unless otherwise specified, transistors described in this specification and the like are n-channel transistors. Thus, unless otherwise specified, the threshold voltage (also referred to as “Vth”) is higher than 0 V.

Note that in this specification, a barrier film refers to a film having a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen. The barrier film that has conductivity may be referred to as a conductive barrier film.

In this specification and the like, a metal oxide means an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, a metal oxide used in an active layer of a transistor is called an oxide semiconductor in some cases. In other words, an OS FET is a transistor including an oxide or an oxide semiconductor.

An example of a semiconductor device of one embodiment of the present invention including a transistor1000and a transistor2000is described below.

FIGS. 1A and 1Bare cross-sectional views of the semiconductor device including the transistor1000and the transistor2000, andFIG. 2is a top view of the semiconductor device.FIG. 1Ais a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2inFIG. 2, which illustrates a cross section of the transistor1000in the channel length direction.FIG. 1Bis a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4inFIG. 2, which illustrates a cross section of the transistor1000in the channel width direction. For simplification of the drawing, some components are not illustrated in the top view inFIG. 2.

The transistors1000and2000formed over a substrate (not illustrated) have different structures. For example, the transistor2000may have a smaller drain current Icutthan the transistor1000when a back gate voltage and a top gate voltage are each 0 V. In this specification and the like, Icutis a drain current when a gate voltage that controls switching operation of a transistor is 0 V. The transistor2000is a switching element capable of controlling the potential of a back gate of the transistor1000. Therefore, a charge at a node connected to the back gate of the transistor1000can be prevented from being lost by making the node have a desired potential and then turning off the transistor2000.

The structures of the transistors1000and2000will be described below with reference toFIGS. 1A and 1BtoFIGS. 4A and 4B.

As illustrated inFIGS. 1A and 1B, the transistor1000includes an insulator401and an insulator301over a substrate (not illustrated); a conductor410embedded in the insulator401and the insulator301; an insulator302over the insulator301and the conductor410; an insulator303over the insulator302; an insulator402over the insulator303; an oxide406aover the insulator402; an oxide406bin contact with at least part of a top surface of the oxide406a; an oxide406cover the oxide406b; an insulator412over the oxide406c; a conductor404aover the insulator412; a conductor404bover the conductor404a; an insulator419over the conductor404b; an insulator418in contact with side surfaces of the insulator412, the conductor404a, the conductor404b, and the insulator419; and an insulator409in contact with a top surface of the oxide406cand a side surface of the insulator418. Here, as illustrated inFIG. 1A, a top surface of the insulator418is preferably substantially aligned with a top surface of the insulator419. Hereinafter the oxide406a, the oxide406b, and the oxide406care collectively referred to as the oxide406in some cases. Furthermore, the insulator409is preferably provided to cover the insulator419, the conductor404, the insulator418, and the oxide406.

Although the oxides406a,406b, and406care stacked in the transistor1000, the structure of the present invention is not limited to this structure. For example, only the oxides406band406cmay be provided. Furthermore, the conductors404aand404bare collectively referred to as the conductor404in some cases. Although the conductors404aand404bare stacked in the transistor1000, the structure of the present invention is not limited to this structure. For example, only the conductor404bmay be provided.

In the transistor1000, an insulator400may be provided over the substrate. An insulator432may be provided over the insulator400. The transistor1000may further include an insulator430provided over the insulator432and a conductor440embedded in the insulator430. The insulator401may be provided over the insulator430, and the insulator301may be provided over the insulator401.

The conductor440includes a conductor440athat is in contact with an inner wall of an opening of the insulator430and a conductor440bpositioned inside the conductor440a. Here, top surfaces of the conductors440aand440bcan have substantially the same level as a top surface of the insulator430. Although the conductor440aand the conductor440bare stacked in the transistor1000, the structure of the present invention is not limited to this structure. For example, only the conductor440bmay be provided.

It is preferable that the conductor410be provided over and in contact with the conductor440so as to overlap with the oxide406and the conductor404. In the conductor410, the conductor410ais formed in contact with an inner wall of the opening in the insulators401and301, and the conductor410bis formed inside the conductor410a. Thus, a structure in which the conductor410ais in contact with the conductor440bis preferable. Here, top surfaces of the conductors410aand410bcan have substantially the same level as a top surface of the insulator301. Although the conductor410aand the conductor410bare stacked in the transistor1000, the structure of the present invention is not limited to this structure. For example, only the conductor410bmay be provided.

The conductor404can function as a top gate (also referred to as a first gate in some cases), and the conductor410can function as a back gate (also referred to as a second gate in some cases). By changing the potential of the back gate independently of the potential of the top gate, the threshold voltage of the transistor1000can be changed. In particular, by applying a negative potential to the back gate, the threshold voltage of the transistor1000can be higher than 0 V, off-state current can be reduced, and Icutcan be noticeably reduced.

The conductor440extends in the channel width direction in a manner similar to that of the conductor404, and functions as a wiring through which a potential is applied to the conductor410, i.e., the back gate. When the conductor410is stacked over the conductor440functioning as the wiring for the back gate so as to be embedded in the insulators401and301, the insulators401and301and the like are positioned between the conductor440and the conductor404, reducing the parasitic capacitance between the conductor440and the conductor404and thereby increasing the withstand voltage. The reduction in the parasitic capacitance between the conductor440and the conductor404can improve the switching speed of the transistor, so that the transistor can have high frequency characteristics. The increase in the withstand voltage between the conductor440and the conductor404can improve the reliability of the transistor1000. Therefore, the thicknesses of the insulators401and301are preferably large. Note that the extending direction of the conductor440is not limited to this example; for example, the conductor440may extend in the channel length direction of the transistor1000.

Here, it is preferable to use conductive materials that have a function of inhibiting the penetration of impurities such as water or hydrogen or hardly transmit such impurities for the conductor410aand the conductor440a. For example, a single layer or a stacked layer of tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. Owing to this, diffusion of impurities such as water or hydrogen from a layer below the insulator432into an upper layer through the conductors440and410can be inhibited. Note that it is preferable that the conductors410aand440ahave a function of inhibiting the penetration of at least one of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, and NO2), and a copper atom and oxygen (e.g., an oxygen atom or an oxygen molecule). Furthermore, in the following description, the same applies to a conductive material having a function of inhibiting the penetration of impurities. When the conductors410aand440ahave a function of inhibiting the penetration of oxygen, the conductivity of the conductors410band440bcan be prevented from being lowered because of oxidation.

Moreover, the conductor410bis preferably formed using a conductive material including tungsten, copper, or aluminum as its main component. Although not illustrated, the conductor410bmay have a stacked structure and be, for example, stacked layers of titanium, titanium nitride, and the above-described conductive material.

The conductor440b, which serves as a wiring, is preferably formed using a conductor having a higher conductivity than the conductor410b; a conductive material including copper or aluminum as its main component can be used, for example. Although not illustrated, the conductor440bmay have a stacked structure and be, for example, stacked layers of titanium, titanium nitride, and the above-described conductive material.

Moreover, a conductor441may be provided in a manner similar to that of the conductor440. The conductor441is provided in an opening formed in the insulator400, the insulator432, and the insulator430. Part of the conductor441formed in the same layer as the insulator430functions as a wiring and part of the conductor441formed in the same layer as the insulator400and the insulator432functions as a plug. The conductor441includes a conductor441athat is in contact with an inner wall of the opening and a conductor441bthat is inside the conductor441a. As the conductor441a, a conductor that is used as the conductor440acan be used. As the conductor441b, a conductor that is used as the conductor440bcan be used. Moreover, top surfaces of the conductors441aand441bcan have substantially the same level as the top surface of the insulator430.

The conductor441can be connected to a wiring, a circuit element, a semiconductor element, or the like positioned under the insulator400. Moreover, when a similar wiring and a similar plug are provided over the conductor441, the conductor441can be connected to a wiring, a circuit element, a semiconductor element, or the like positioned over the conductor441.

The insulator432and the insulator401can function as barrier insulating films that prevent impurities such as water or hydrogen from entering the transistor from a lower layer. The insulator432and the insulator401are preferably formed with an insulating material having a function of inhibiting the penetration of impurities such as water or hydrogen. For example, it is preferable that aluminum oxide be used for the insulator432and silicon nitride be used for the insulator401. Accordingly, diffusion of impurities such as water or hydrogen into a layer over the insulator432and the insulator401can be inhibited. Note that it is preferable that the insulator432and the insulator401have a function of inhibiting the penetration of at least one of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, and NO2), and a copper atom. Furthermore, in the following description, the same applies to an insulating material having a function of inhibiting the penetration of impurities.

Furthermore, the insulator432and the insulator401are preferably formed using an insulating material that has a function of inhibiting the penetration of oxygen (e.g., an oxygen atom or an oxygen molecule). Thus, oxygen contained in the insulator402or the like can be prevented from being diffused to lower layers.

Furthermore, with the structure in which the conductor410is stacked over the conductor440, the insulator401can be provided between the conductor440and the conductor410. Here, even when a metal that is easily diffused, such as copper, is used as the conductor440b, silicon nitride or the like provided as the insulator401can prevent diffusion of the metal to a layer positioned above the insulator401.

The insulator303is preferably formed using an insulating material that has a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen, and is preferably formed using aluminum oxide or hafnium oxide, for example. Accordingly, diffusion of impurities such as water or hydrogen from a layer under the insulator303into a layer over the insulator303can be inhibited. Furthermore, oxygen contained in the insulator402or the like can be prevented from being diffused to lower layers.

Furthermore, the concentration of impurities such as water, hydrogen, or nitrogen oxide in the insulator402is preferably lowered. The amount of hydrogen released from the insulator402, which is converted into hydrogen molecules per unit area of the insulator402, is less than or equal to 2×1015molecules/cm2, preferably less than or equal to 1×1015molecules/cm2, further preferably less than or equal to 5×1014molecules/cm2in thermal desorption spectroscopy (TDS) in the range of 50° C. to 500° C., for example. The insulator402is preferably formed using an insulator from which oxygen is released by heating.

The insulator412can function as a first gate insulating film, and the insulator302, the insulator303, and the insulator402can function as a second gate insulating film. Although the insulator302, the insulator303, and the insulator402are stacked in the transistor1000, the present invention is not limited to this structure. For example, any two of the insulators302,303, and402may be stacked, or any one of the insulators may be used.

In the oxide406, the oxide406a, the oxide406b, and the oxide406care stacked in this order. Side surfaces of the oxide406aand the oxide406bare preferably substantially aligned with each other and form one surface. The oxide406cis preferably formed to cover the oxide406aand the oxide406b. For example, the oxide406cis formed in contact with the side surface of the oxide406a, the top and side surfaces of the oxide406b, and part of a top surface of the insulator402. Here, when the oxide406cis seen from above, the side surface of the oxide406cis positioned outside the side surfaces of the oxide406aand the oxide406b.

The oxide406is preferably formed using a metal oxide serving as an oxide semiconductor (hereinafter, such a metal oxide may also be referred to simply as an oxide semiconductor). The metal oxide to be used preferably has an energy gap greater than or equal to 2 eV, further preferably greater than or equal to 2.5 eV. With the use of a metal oxide having such a wide energy gap, the off-state current of the transistor can be reduced.

A transistor formed using an oxide semiconductor has an extremely low leakage current in an off state; thus, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used in a transistor included in a highly integrated semiconductor device.

Note that in this specification and the like, a metal oxide containing nitrogen is also called a metal oxide in some cases. Moreover, a metal oxide containing nitrogen may be called a metal oxynitride.

Here, the atomic ratio of the element M to the constituent elements in the metal oxide used as the oxide406ais preferably greater than that in the metal oxide used as the oxide406b. Moreover, the atomic ratio of the element M to In in the metal oxide used as the oxide406ais preferably greater than that in the metal oxide used as the oxide406b. The atomic ratio of In to the element M in the metal oxide used as the oxide406bis preferably greater than that in the metal oxide used as the oxide406a. Note that as the oxide406c, the metal oxide that can be used as the oxide406aor the oxide406bcan be used. The case in which the metal oxide that can be used as the oxide406ais employed as the oxide406cis described below.

When using the above metal oxide as the oxide406aand the oxide406c, it is preferable that the conduction band minimum of the oxide406aand the oxide406cbe higher than the conduction band minimum of the region of the oxide406bwhere the conduction band minimum is low. In other words, the electron affinity of the oxide406aand the oxide406cis preferably smaller than the electron affinity of the region of the oxide406bwhere the conduction band minimum is low.

Here, the energy level of the conduction band minimum is gradually varied in the oxides406a,406b, and406c. In other words, the energy level of the conduction band minimum is continuously varied or continuously connected. To vary the energy level gradually, the density of defect states in a mixed layer formed at the interface between the oxides406aand406band at the interface between the oxides406band406cis decreased.

Specifically, when the oxides406aand406bcontain and the oxides406band406ccontain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide406bis an In—Ga—Zn oxide, it is preferable to use an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like as the oxides406aand406c.

At this time, a narrow-gap portion formed in the oxide406bserves as a main carrier path. Since the density of defect states at the interface between the oxides406aand406band the interface between the oxides406band406ccan be decreased, the influence of interface scattering on carrier conduction is small, and high on-state current can be obtained.

FIGS. 3A and 3Bare enlarged views of the oxide406and its vicinity illustrated inFIG. 1A. As illustrated inFIGS. 3A and 3B, the oxide406includes a region426a, a region426b, and a region426c. As illustrated inFIGS. 3A and 3B, the region426ais sandwiched between the region426band the region426c. The regions426band426care reduced in resistance through formation of the insulator409, and are high in conductivity than the region426a. Impurity elements such as hydrogen or nitrogen, which are contained in an atmosphere where the insulator409is formed, are added to the regions426band426c. Accordingly, oxygen vacancies are formed because of the added impurity elements, and the impurity elements enter the oxygen vacancies, thereby increasing the carrier density and reducing resistance mainly in a region of the oxide406which is in contact with the insulator409.

Thus, it is preferable that the concentration of at least one of hydrogen and nitrogen be higher in the regions426band426cthan in the region426a. The concentration of hydrogen or nitrogen is measured by secondary ion mass spectrometry (SIMS) or the like. As the concentration of hydrogen or nitrogen in the region426a, the concentration of hydrogen or nitrogen near the center of a region of the oxide406bthat overlaps with the insulator412(e.g., a portion of the oxide406b, which is substantially equally away from the left and right side surfaces of the insulator412in the channel length direction) is measured.

The regions426band426care reduced in resistance when an element forming an oxygen vacancy or an element trapped by an oxygen vacancy is added thereto. Typical examples of such an element are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas element. Typical examples of the rare gas element are helium, neon, argon, krypton, and xenon. Accordingly, the regions426band426care made to contain one or more of the above elements.

It is preferable in the oxide406aand the oxide406cthat the atomic ratio of In to the element M in the regions426band426cbe substantially the same as that in the oxide406b. In other words, in the oxide406aand the oxide406c, the atomic ratio of In to the element M in the regions426band426cis preferably greater than that in the region426a. Thus, when the indium content in the oxide406is increased, the carrier mobility is increased and the resistance can be decreased. Even when the thickness of the oxide406cis small and electric resistance of the oxide406is high in the manufacturing process of the transistor1000, the regions426band426ccan serve as source and drain regions owing to the sufficiently reduced resistance of the oxide406in the regions426band426c. For example, even when the oxide406cis removed and the thickness of the oxide406bis small, the regions426band426cin the oxide406can serve as source and drain regions owing to the sufficiently reduced resistance of the oxide406ain the regions426band426c.

As illustrated inFIGS. 3A and 3B, the region426band the region426care formed in at least the regions of the oxide406in contact with the insulator409. The regions426bof the oxide406bcan serve as one of a source region and a drain region, and the region426cof the oxide406bcan serve as the other of the source region and the drain region. The region426aof the oxide406bcan serve as a channel formation region.

Although the regions426a,426b, and426care formed in the oxides406a,406b, and406cinFIG. 1AandFIGS. 3A and 3B, one embodiment of the present invention is not limited thereto. For example, it is acceptable as long as these regions are formed at least in the oxide406b. Although the boundary between the regions426aand426band the boundary between the regions426aand426care substantially perpendicular to the top surface of the oxide406inFIG. 1AandFIGS. 3A and 3Band the like, one embodiment of the present invention is not limited thereto. For example, the regions426band426cproject to the conductor404side in the vicinity of the surface of the oxide406band are recessed to the conductor451aside or the conductor451bside in the vicinity of a lower surface of the oxide406a.

In the transistor1000, the regions426band426care preferably formed in regions of the oxide406that overlap with the insulator409and the insulator418and overlap with the vicinity of edges of the insulators418and412, as illustrated inFIG. 3A. In that case, portions of the regions426band426cthat overlap with the conductor404serve as what we call overlap regions (also referred to as Lov regions). With the Lov regions, no high-resistance region is formed between the channel formation region and the source or drain region of the oxide406; accordingly, the on-state current and the mobility of the transistor can be increased.

However, the semiconductor device described in this embodiment is not limited to the above-described structure. For example, as illustrated inFIG. 3B, the regions426band426cmay be formed in regions of the oxide406that overlap with the insulator409and the insulator418. The structure illustrated inFIG. 3Bcan be rephrased as the structure in which the width of the conductor404in the channel length direction is substantially the same as the width of the region426a. Because a high-resistance region is not formed between the source region and the drain region in the structure illustrated inFIG. 3B, the on-state current of the transistor can be increased. Since the gate does not overlap with the source and drain regions in the channel length direction in the structure illustrated inFIG. 3B, formation of unnecessary capacitance can be suppressed.

By appropriately selecting the areas of the regions426band426cin the above manners, a transistor having desired electrical characteristics can be easily provided in accordance with the circuit design.

The insulator412is preferably provided in contact with the top surface of the oxide406c. The insulator412is preferably formed using an insulator from which oxygen is released by heating. When the insulator412formed using such a material is provided in contact with the top surface of the oxide406c, oxygen can be supplied to the region426aof the oxide406beffectively. Furthermore, the concentration of impurities such as water or hydrogen in the insulator412is preferably lowered as in the insulator402. The thickness of the insulator412is preferably 1 nm to 20 nm inclusive (e.g., approximately 1 nm).

The insulator412preferably contains oxygen. The amount of oxygen released from the insulator412, which is converted into oxygen molecules per unit area of the insulator412, is greater than or equal to 1×1014molecules/cm2, preferably greater than or equal to 2×1014molecules/cm2, further preferably greater than or equal to 4×1014molecules/cm2in thermal desorption spectroscopy (TDS) in the range of the surface temperatures from 100° C. to 700° C. inclusive or from 100° C. to 500° C. inclusive, for example.

The insulator412, the conductor404, and the insulator419each include a region that overlaps with the oxide406b. In addition, it is preferable that side surfaces of the insulator412, the conductor404a, the conductor404b, and the insulator419be substantially aligned with each other.

The conductor404ais preferably formed using a conductive oxide. For example, the metal oxide that can be used as the oxide406aor the oxide406bcan be used for the conductor404a. In particular, an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=4:2:3 to 4:2:4.1 or in the neighborhood thereof, which has high conductivity, is preferably used. When the conductor404ais formed using such a material, oxygen can be prevented from entering the conductor404b, and an increase in electric resistance value of the conductor404bdue to oxidation can be prevented.

In addition, by depositing such a conductive oxide by sputtering, oxygen can be added to the insulator412, which makes it possible to supply oxygen to the oxide406b. Thus, oxygen vacancies in the region426aof the oxide406can be reduced.

The conductor404bcan be formed using a metal such as tungsten, for example. It is also possible to use, as the conductor404b, a conductor that can add impurities such as nitrogen to the conductor404ato improve the conductivity of the conductor404a. For example, titanium nitride or the like is preferably used for the conductor404b. Alternatively, the conductor404bmay be a stack including a metal nitride such as titanium nitride and a metal such as tungsten thereover.

Here, the conductor404functioning as a gate electrode is provided to cover the top surface of the region426aand its periphery and the side surface, which is in the channel width direction, of the oxide406bwith the insulator412interposed therebetween. Thus, the electric field of the conductor404functioning as a gate electrode can electrically surround the top surface of the region426aand its periphery and the side surface, which is in the channel width direction, of the oxide406b. The structure of the transistor in which the channel formation region is electrically surrounded by the electric field of the conductor404is referred to as a surrounded channel (s-channel) structure. Thus, a channel can be formed in the top surface of the region426aand its periphery and the side surface, which is in the channel width direction, of the oxide406b; therefore, a large amount of current can flow between the source and the drain, and a current in an on state (on-state current) can be large. Moreover, since the top surface of the region426aand its periphery and the side surface, which is in the channel width direction, of the oxide406bare surrounded by the electric field of the conductor404, a leakage current in an off state (off-state current) can be small.

The insulator419is preferably provided over the conductor404b. In addition, it is preferable that the position of a side surface of the insulator412be substantially the same as the positions of side surfaces of the insulator419, the conductor404a, and the conductor404bwhen the substrate is perpendicularly seen from above. The insulator419is preferably formed by an atomic layer deposition (ALD) method. In that case, the insulator419can be formed with a thickness of approximately 1 nm to 20 nm inclusive, preferably approximately 5 nm to 10 nm inclusive. The insulator419is preferably formed using an insulating material having a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen, and is preferably formed using aluminum oxide or hafnium oxide, for example.

The insulator418is provided in contact with the side surfaces of the insulator412, the conductor404, and the insulator419. Furthermore, it is preferable that the top surface of the insulator418be substantially aligned with the top surface of the insulator419. The insulator418is preferably deposited by an ALD method, in which case the thickness of the insulator418can be approximately 1 nm to 20 nm inclusive, preferably approximately 1 nm to 3 nm inclusive (e.g., 1 nm).

Like the insulator419, the insulator418is preferably formed using an insulating material that has a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen, and is preferably formed using aluminum oxide or hafnium oxide, for example. In this manner, oxygen in the insulator412can be prevented from diffusing outward. In addition, impurities such as water or hydrogen can be prevented from entering the oxide406through the side of the insulator412or the like.

When the insulators418and419are provided as described above, the insulators with a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen can cover the top and side surfaces of the conductor404and the side surface of the insulator412. This can prevent entry of impurities such as water or hydrogen into the oxide406through the conductor404and the insulator412. Thus, the insulator418functions as a side barrier for protecting side surfaces of a gate electrode and a gate insulating film, and the insulator419functions a top barrier for protecting a top surface of the gate electrode.

As mentioned above, the regions426band426cof the oxide406are formed because of the impurity elements added in the formation of the insulator409. In the case where a transistor is miniaturized to have a channel length of approximately greater than or equal to 10 nm and less than or equal to 30 nm, impurity elements contained in a source region or a drain region may diffuse and the source region and the drain region may be electrically connected to each other. By contrast, when the insulators418and419are formed as described in this embodiment, entry of impurities such as water or hydrogen into the insulator412and the conductor404and outward diffusion of oxygen included in the insulator412can be inhibited; thus, the source region and the drain region can be prevented from being electrically connected to each other when the gate voltage is 0 V.

When the insulator418is formed as described in this embodiment, the distance between two regions of the oxide406that are in contact with the insulator409can be longer; thus, the source region and the drain region can be prevented from being electrically connected to each other. Moreover, the insulator418formed by an ALD method can have a thickness substantially equal to or less than a miniaturized channel length, which can prevent the distance between the source and drain regions from being longer than necessary and the resistance from increasing.

The insulator418is preferably formed in the following manner: an insulating film is deposited by an ALD method and then subjected to anisotropic etching so that a portion of the insulating film in contact with the side surfaces of the insulator412, the conductor404, and the insulator419remains. Thus, the insulator418having a small thickness as described above can be easily formed. At this time, even when the insulator419provided over the conductor404is partly removed by the anisotropic etching, the portion of the insulator418in contact with the insulator412and the conductor404can be left sufficiently.

Note that a precursor used in the ALD method sometimes contains impurities such as carbon. Thus, the insulator418and/or the insulator419may contain impurities such as carbon. In the case where the insulator432is formed by sputtering and the insulator418and/or the insulator419are/is formed by an ALD method, for example, the insulator418and/or the insulator419may contain more impurities such as carbon than the insulator432even when the insulator418and/or the insulator419and the insulator432are formed using aluminum oxide. Note that impurities can be quantified by X-ray photoelectron spectroscopy (XPS).

The insulator409is provided to cover the insulator419, the insulator418, the oxide406, and the insulator402. Here, the insulator409is provided in contact with the top surface of the insulator419and the top and side surfaces of the insulator418. As mentioned above, the insulator409adds impurities such as hydrogen or nitrogen to the oxide406to form the regions426band426c. Thus, the insulator409preferably contains at least one of hydrogen and nitrogen.

Furthermore, the insulator409is preferably provided in contact with side surfaces of the oxides406band406aas well as the top surface of the oxide406b. This enables a resistance reduction to the side surfaces of the oxides406ato406cin the regions426b426c.

The insulator409is preferably formed using an insulating material that has a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen. For example, the insulator409is preferably formed using silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, or aluminum nitride oxide. When the insulator409is formed using any of the above materials, entry of oxygen through the insulator409to be supplied to oxygen vacancies in the regions426band426c, which decreases the carrier density, can be prevented. In addition, entry of impurities such as water or hydrogen through the insulator409, which causes the regions426band426cto excessively extend to the region426aside, can be prevented.

An insulator415is preferably provided over the insulator409. The concentration of impurities such as water or hydrogen in the insulator415is preferably lowered as in the insulator402and the like. An insulator that is similar to the insulator432may be provided over the insulator415.

In openings formed in the insulators415and409, conductors451aand451bare provided. The conductors451aand451bare preferably provided to face each other with the conductor404positioned therebetween. Note that the heights of the upper surfaces of the conductor451aand the conductor451bcan be substantially the same.

Here, the conductor451ais formed in contact with an inner wall of one opening in the insulators415and409. The region426bof the oxide406is positioned in at least part of a bottom portion of the opening, and the conductor451ais in contact with the region426b. Similarly, the conductor451bis formed in contact with an inner wall of the other opening in the insulators415and409. The region426cof the oxide406is positioned in at least part of a bottom portion of the opening, and the conductor451bis in contact with the region426c.

The conductors451aand451bare preferably formed using a conductive material including tungsten, copper, or aluminum as its main component. Although not illustrated, the conductors451aand451bmay have a stacked structure and be, for example, stacked layers of titanium, titanium nitride, and the above-described conductive material.

The conductor451ais in contact with the region426bserving as one of a source region and a drain region of the transistor1000, and the conductor451bis in contact with the region426cserving as the other of the source region and the drain region of the transistor1000. Thus, the conductor451acan serve as one of a source electrode and a drain electrode, and the conductor451bcan serve as the other of the source electrode and the drain electrode. Because the region426band the region426care reduced in resistance, the contact resistance between the conductor451aand the region426band the contact resistance between the conductor451band the region426care reduced, leading to a large on-state current of the transistor1000.

Here,FIG. 4Ais a cross-sectional view of a portion along the dashed-dotted line A5-A6inFIG. 2. Although the cross-sectional view inFIG. 4Aillustrates the conductor451a, the conductor451bhas a similar structure.

As illustrated inFIG. 1AandFIG. 4A, the conductor451a(the conductor451b) is in contact with at least the top surface of the oxide406and is preferably in contact with the side surface of the oxide406. Specifically, as illustrated inFIG. 4A, the conductor451a(the conductor451b) is preferably in contact with one or both of side surfaces (the side surfaces on the A5side and the A6side) of the oxide406in the channel width direction. As illustrated inFIG. 1A, the conductor451a(the conductor451b) may be in contact with the side surface on the A1side (the A2side) of the oxide406in the channel length direction. Thus, when the structure in which the conductor451a(the conductor451b) is in contact with the side surface of the oxide406in addition to the top surface of the oxide406is employed, the contact area between the conductor451a(the conductor451b) and the oxide406can be increased without an increase in the area of the top surface of the contact portion, so that the contact resistance between the conductor451a(the conductor451b) and the oxide406can be reduced. Accordingly, miniaturization of the source electrode and the drain electrode of the transistor can be achieved and, in addition, the on-state current can be increased.

Here, in the oxide406, the oxide406aand the oxide406bare covered with the oxide406c, and the conductor451a(the conductor451b) is in contact with the oxide406c.

Although the conductor in which the opening is formed is only the conductor451a(the conductor451b) inFIG. 4A, this embodiment is not limited to this structure. A structure in which a conductor450in contact with inner walls of the insulator415and the insulator409is formed and the conductor451a(the conductor451b) is formed inside the conductor450as illustrated inFIG. 4Bmay be employed. Thus, the conductor451a(the conductor451b) is electrically connected to the region426b(the region426c) through the conductor450.

Here, the conductor450is preferably formed using a conductive material having a function of inhibiting the penetration of impurities such as water or hydrogen, like the conductor410aor the like. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used, and a single layer or stacked layers may be used. This can prevent entry of impurities such as water or hydrogen from a layer positioned over the insulator415to the oxide406through the conductor451aand the conductor451b.

It is preferable that a conductor452abe provided in contact with a top surface of the conductor451aand a conductor452bbe provided in contact with a top surface of the conductor451b. The conductor452aand the conductor452bare each preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Although not shown, the conductor452aand the conductor452bmay have a stacked layer structure, and for example, stacked layers of titanium, titanium nitride, and the above-described conductive material may be formed. Note that like the conductor440or the like, the conductor452aand the conductor452bmay be embedded in openings in an insulator.

Next, the transistor2000whose electrical characteristics are different from those of the transistor1000is described. The transistor2000can be formed in parallel with the transistor1000, and is preferably formed in the same layer as the transistor1000. By the formation of the transistors1000and2000in parallel, the transistor2000can be formed without increasing a manufacturing step.

As illustrated inFIG. 1A, the transistor2000includes an insulator401and an insulator301over a substrate (not illustrated); a conductor510embedded in the insulator401and the insulator301; an insulator302over the insulator301and the conductor510; an insulator303over the insulator302; an insulator402over the insulator303; an oxide506a1and an oxide506a2apart from each other over the insulator402; an oxide506b1in contact with a top surface of the oxide506a1; an oxide506b2in contact with a top surface of the oxide506a2; an oxide506cin contact with a top surface of the insulator402, side surfaces of the oxides506a1and the oxide506a2, top and side surfaces of the oxide506b1and the oxide506b2; an insulator512over the oxide506c; a conductor504aover the insulator512; a conductor504bover the conductor504a; an insulator519over the conductor504b; an insulator518in contact with side surfaces of the insulator512, the conductor504a, the conductor504b, and the insulator519; and the insulator409in contact with a top surface of the oxide506cand a side surface of the insulator518. Here, as illustrated inFIG. 1A, the top surface of the insulator518is preferably substantially aligned with a top surface of the insulator519. Furthermore, the insulator409is preferably provided to cover the insulator519, the conductor504, the insulator518, and the oxide506. It is preferable that when the substrate is perpendicularly seen from above, the position of the side surface of the insulator512is substantially the same as the positions of the side surfaces of the insulator519, the conductor504a, and the conductor504b.

In the following description, the oxide506a1, the oxide506a2, the oxide506b1, the oxide506b2, and the oxide506care collectively referred to as the oxide506in some cases. Although the conductor504aand the conductor504bare stacked in the transistor2000, the structure of the present invention is not limited to this structure. For example, only the conductor504bmay be provided.

Here, the conductors, the insulators, and the oxides included in the transistor2000can be formed in the same step as the conductors, the insulators, and the oxides included in the transistor1000that is in the same layer as the transistor2000. That is, the conductor540(the conductor540aand the conductor540b) corresponds to the conductor440(the conductor440aand the conductor440b); the oxide506(the oxide506a1, the oxide506a2, the oxide506b1, the oxide506b2, and the oxide506c) corresponds to the oxide406(the oxide406a, the oxide406b, and the oxide406c); the insulator512corresponds to the insulator412; the conductor504(the conductor504aand the conductor504b) corresponds to the conductor404(the conductor404aand the conductor404b); the insulator519corresponds to the insulator419; and the insulator518corresponds to the insulator418. Therefore, the conductors, the insulators, and the oxides included in the transistor2000can be formed with the materials the same as those for the transistor1000, and description of the transistor1000can be referred to for the transistor2000.

Furthermore, the transistor2000may include the insulator430over the insulator432and the conductor540embedded in the insulator430. Here, the conductor540includes a conductor540athat is in contact with an inner wall of an opening of the insulator430and a conductor540bpositioned inside the conductor540a. The conductor540(the conductor540aand the conductor540b) corresponds to the conductor440(the conductor440aand the conductor440b). The conductor540can be formed with a material the same as that for the conductor440, and description of the conductor440can be referred to for the conductor540.

A conductor551aand a conductor551bare placed in openings formed in the insulator415and the insulator409. The conductor551aand the conductor551bare preferably oppositely disposed with the conductor504sandwiched therebetween. The conductor551aand the conductor551bcorrespond to the conductor451aand the conductor451b. The conductor551aand the conductor551bcan be formed with a material the same as that for the conductor451aand the conductor451b, and description of the conductor451aand the conductor451bcan be referred to for the conductor551aand the conductor551b.

It is preferable that the conductor552abe disposed in contact with a top surface of the conductor551aand the conductor552bbe disposed in contact with a top surface of the conductor551b. The conductor552aand the conductor552bcan be formed with a material the same as that for the conductor452aand the conductor452b, and description of the conductor452aand the conductor452bcan be referred to for the conductor552aand the conductor552b.

The oxide506cis preferably formed to cover the oxide506a1, the oxide506b1, the oxide506a2, and the oxide506b2. A side surface of the oxide506a1and a side surface of the oxide506b1are preferably substantially aligned with each other, and a side surface of the oxide506a2and a side surface of the oxide506b2are preferably substantially aligned with each other. For example, the oxide506cis formed in contact with the side surfaces of the oxide506a1and the oxide506a2, the top and side surfaces of the oxide506b1and the oxide506b2, and part of the top surface of the insulator402. Here, when the oxide506cis seen from above, the side surface of the oxide506cis positioned outside the side surfaces of the oxide506a1and the oxide506b1and the side surfaces of the oxide506a2and the oxide506b2.

The oxides506a1and506b1and the oxides506a2and506b2are oppositely disposed with the conductor510, the oxide506c, the insulator512, and the conductor504sandwiched therebetween.

The oxide506includes a region in contact with the insulator409. The resistance of the region and its vicinity is lowered in a manner similar to that of the region426band the region426cin the transistor1000. Accordingly, the oxide506a1, the oxide506b1, and part of the oxide506ccan function as one of a source region and a drain region of the transistor2000, and the oxide506a2, the oxide506b2, and other part of the oxide506ccan function as the other of the source region and the drain region of the transistor2000.

A region of the oxide506csandwiched between the oxides506a1and506a2and the oxides506b1and506b2functions as a channel formation region. Here, the distance between the oxides506a1and506a2and the oxides506b1and506b2is preferably long. For example, the distance is preferably longer than the length in the channel length direction of the conductor404of the transistor1000. Thus, the off-state current of the transistor2000can be reduced.

The oxide506cof the transistor2000can be formed with a material the same as that of the oxide406cof the transistor1000. That is, as the oxide506c, the metal oxide that can be used as the oxide406aor the oxide406bcan be used. For example, in the case where an In—Ga—Zn oxide is used as the oxide506c, the atomic ratio of In to Ga and Zn can be 1:3:2, 4:2:3, 1:1:1, or 1:3:4.

A transistor including the oxide506cand a transistor including the oxide406bpreferably have different electrical characteristics. For this reason, for example, the oxide506cand the oxide406bare preferably different in any of a material of the oxide, the content ratio of elements in the oxide, the thickness of the oxide, and the width and the length of a channel formation region formed in the oxide.

The case in which the metal oxide that can be used as the oxide406ais employed as the oxide506cis described below. For example, metal oxide with an atomic ratio of the region C inFIG. 12C, which has a relatively high insulating property, is preferably used as the oxide506c. In the oxide506cformed of the metal oxide, the atomic ratio of the element M to constituent elements can be greater than that in the oxide406b. In addition, in the oxide506c, the atomic ratio of the element M to In can be greater than that in the oxide406b. Thus, the threshold voltage of the transistor2000can be higher than 0 V, the off-state current can be reduced, and Icutcan be noticeably reduced.

In the oxide506cserving as a channel formation region of the transistor2000, oxygen vacancies and impurities such as water or hydrogen are preferably reduced as in the oxide406cof the transistor1000or the like. Thus, the threshold voltage of the transistor2000can be higher than 0 V, the off-state current can be reduced, and Icutcan be noticeably reduced.

The threshold voltage of the transistor2000including the oxide506cis preferably larger than that of the transistor1000in which a negative potential is not applied to the back gate. In order to make the threshold voltage of the transistor2000higher than that of the transistor1000, for example, it is preferable that metal oxide with an atomic ratio of the region A inFIG. 12Abe used as the oxide406bin the transistor1000and metal oxide with the atomic ratio of the region C inFIG. 12Cbe used as the oxide506cin the transistor2000.

Furthermore, the length of the conductor504in the A1-A2direction of the transistor2000is preferably longer than the length of the conductor404in the A1-A2direction of the transistor1000. Since the channel length of the transistor2000can be longer than that of the transistor1000in this way, the threshold voltage of the transistor2000can be higher than that of the transistor1000in which a negative potential is not applied to the back gate.

The channel formation region in the transistor2000is formed in the oxide506c, whereas the channel formation region in the transistor1000is formed in the oxide406a, the oxide406b, and the oxide406c. Accordingly, the thickness of the oxide506in the channel formation region in the transistor2000can be smaller than that of the oxide406in the channel formation region in the transistor1000. Therefore, the threshold voltage of the transistor2000can be higher than that of the transistor1000in which a negative potential is not applied to the back gate.

A capacitor1500may be provided over the transistor1000and the transistor2000. In this embodiment, an example in which the capacitor1500is formed using the conductor452belectrically connected to the transistor1000is described.

An insulator411is preferably provided over the conductor452a, the conductor452b, the conductor552a, and the conductor552b. The insulator411may be, for example, a single layer of aluminum oxide or silicon oxynitride or a stacked layer of aluminum oxide and silicon oxynitride.

Moreover, a conductor454is preferably provided over the insulator411to overlap with at least part of the conductor452b. Like the conductor452b, the conductor454is preferably formed with a conductive material containing tungsten, copper, or aluminum as its main component. Although not illustrated, the conductor454may have a stacked structure, and for example, may be a stacked layer of titanium, titanium nitride, and the above-described conductive material. Note that, like the conductor440, the conductor454may be embedded in an opening formed in an insulator.

The conductor452bfunctions as one electrode of the capacitor1500, and the conductor454functions as the other electrode of the capacitor1500. The insulator411functions as a dielectric of the capacitor1500.

An insulator420is preferably provided over the insulator411and the conductor454. An insulator that can be used as the insulator415may be used as the insulator420.

FIG. 13Ais a circuit diagram showing an example of connection relation of the transistor1000, the transistor2000, and the capacitor1500in the semiconductor device described in this embodiment.FIG. 13Bis a cross-sectional view, which corresponds toFIG. 1A, of wirings1601to1604and the like inFIG. 13A.

As illustrated inFIGS. 13A and 13B, in the transistor1000, the gate is electrically connected to the wiring1601, one of the source and the drain is electrically connected to the wiring1602, and the other of the source and the drain is electrically connected to one electrode of the capacitor1500. The other electrode of the capacitor1500is electrically connected to the wiring1603. The drain of the transistor2000is electrically connected to the wiring1604. As illustrated inFIG. 13B, the back gate of the transistor1000and the source, a top gate, and the back gate of the transistor2000are electrically connected through a wiring1605, a wiring1606, a wiring1607, and a wiring1608.

The on/off states of the transistor1000can be controlled by application of a potential to the wiring1601. When the transistor1000is on to apply a potential to the wiring1602, charges can be supplied to the capacitor1500through the transistor1000. At this time, by making the transistor1000off, the charges supplied to the capacitor1500can be held. By application of a given potential to the wiring1603, the potential of a connection portion between the transistor1000and the capacitor1500can be controlled by capacitive coupling. For example, when a ground potential is applied to the wiring1603, the charges are held easily. Furthermore, by application of a negative potential to the wiring1604, the negative potential is applied to the back gate of the transistor1000through the transistor2000, whereby the threshold voltage of the transistor1000can be higher than 0 V, the off-state current can be reduced, and Icutcan be noticeably reduced.

With a structure in which the top gate and the back gate of the transistor2000are diode-connected to the source, and the source of the transistor2000and the back gate of the transistor1000are connected, the back-gate voltage of the transistor1000can be controlled by the wiring1604. When the negative potential of the back gate of the transistor1000is held, the voltage between the top gate and the source of the transistor2000and the voltage between the back gate and the source of the transistor2000are each 0 V. Since the Icutof the transistor2000is extremely small and the threshold voltage of the transistor2000is significantly higher than that of the transistor1000, the structure allows the negative potential of the back gate of the transistor1000to be held for a long time without supply of power to the transistor2000.

Moreover, the negative potential of the back gate of the transistor1000is held, in which case Icutof the transistor1000can be noticeably reduced even without supply of power to the transistor1000. In other words, the charges can be held in the capacitor1500for a long time even without supply of power to the transistor1000and the transistor2000. For example, with use of the semiconductor device as a memory element, data can be held for a long time without power supply. Therefore, a memory device with a low refresh frequency or a memory device that does not need refresh operation can be provided.

Note that the connection relation of the transistor1000, the transistor2000, and the capacitor1500is not limited to that illustrated inFIGS. 13A and 13B. The connection relation can be modified as appropriate in accordance with a necessary circuit configuration.

Next, components of the transistor1000and the transistor2000will be described.

As a substrate over which the transistor1000and the transistor2000are formed, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), or a resin substrate is used, for example. As the semiconductor substrate, a semiconductor substrate of silicon, germanium, or the like, or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be used, for example. A semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, e.g., a silicon on insulator (SOI) substrate or the like is used. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like is used. A substrate including a metal nitride, a substrate including a metal oxide, or the like is used. An insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like is used. Alternatively, any of these substrates over which an element is provided may be used. As the element provided over the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a memory element, or the like is used.

Alternatively, a flexible substrate may be used as the substrate. As a method of providing the transistor over a flexible substrate, there is a method in which the transistor is formed over a non-flexible substrate and then the transistor is separated and transferred to the substrate which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. As the substrate, a sheet, a film, or a foil containing a fiber may be used. The substrate may have elasticity. The substrate may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate may have a property of not returning to its original shape. The substrate has a region with a thickness of, for example, greater than or equal to 5 μm and less than or equal to 700 μm, preferably greater than or equal to 10 μm and less than or equal to 500 μm, further preferably greater than or equal to 15 μm and less than or equal to 300 μm. When the substrate has a small thickness, the weight of the semiconductor device including the transistor can be reduced. When the substrate has a small thickness, even in the case of using glass or the like, the substrate may have elasticity or a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate, which is caused by dropping or the like, can be reduced. That is, a robust semiconductor device can be provided.

For the substrate that is a flexible substrate, metal, an alloy, resin, glass, or fiber thereof can be used, for example. The flexible substrate preferably has a lower coefficient of linear expansion because deformation due to an environment is suppressed. The flexible substrate is formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10−3/K, lower than or equal to 5×10−5/K, or lower than or equal to 1×10−5/K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used for the flexible substrate because of its low coefficient of linear expansion.

The insulator can be an oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like having an insulating property.

Note that when the transistor is surrounded by an insulator that has a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen, the electrical characteristics of the transistor can be stabilized. For example, an insulator that has a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen is used for each of the insulators303,401, and432.

The insulator that has a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen can have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.

It is preferable that the insulator302, the insulator303, the insulator402, the insulator412, the insulator512, and/or the insulator411be formed using an insulator with a high dielectric constant. For example, it is preferable that the insulator302, the insulator303, the insulator402, the insulator412, the insulator512, and/or the insulator411contain gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium. Alternatively, it is preferable that the insulator302, the insulator303, the insulator402, and/or the insulator412have a stacked-layer structure of silicon oxide or silicon oxynitride and an insulator with a high dielectric constant. Because silicon oxide and silicon oxynitride have thermal stability, a combination of silicon oxide or silicon oxynitride with an insulator with a high dielectric constant allows the stacked-layer structure to be thermally stable and have a high dielectric constant. For example, when aluminum oxide, gallium oxide, or hafnium oxide is positioned in contact with the oxide406in each of the insulators402and412, silicon contained in silicon oxide or silicon oxynitride can be prevented from entering the oxide406. Furthermore, for example, when silicon oxide or silicon oxynitride is in contact with the oxide406in each of the insulators402and412, trap centers might be formed at the interface between aluminum oxide, gallium oxide, or hafnium oxide and silicon oxide or silicon oxynitride. The trap centers can shift the threshold voltage of the transistor in the positive direction by trapping electrons, in some cases.

Each of the insulators400,430,301,415, and420preferably includes an insulator with a low dielectric constant. For example, each of the insulators400,430,301,415, and420preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like. Alternatively, each of the insulators400,430,301,415, and420preferably has a stacked-layer structure of a resin and one of the following materials: silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having pores. Because silicon oxide and silicon oxynitride have thermal stability, a combination of silicon oxide or silicon oxynitride with a resin allows the stacked-layer structure to be thermally stable and have a low dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic.

For the insulators418,518,419, and519, an insulator having a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen is used. For the insulators418,518,419, and519, for example, a metal oxide such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide; silicon nitride oxide; or silicon nitride can be used.

The conductors404aand404b, the conductors504aand504b, the conductors410aand410b, a conductor510a, a conductor510b, the conductors440aand440b, the conductors540aand540b, the conductors441aand441b, the conductor450, the conductors451aand451b, the conductors551aand551b, the conductors452aand452b, the conductors552aand552b, and the conductor454can be formed using a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like. Alternatively, a semiconductor having a high electric conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

For the above-described conductors, especially for the conductors404a,504a,410a,510a,440a,540a, and450, a conductive material containing oxygen and a metal element included in a metal oxide that can be used for the oxide406may be used. A conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. An indium tin oxide, an indium oxide containing tungsten oxide, an indium zinc oxide containing tungsten oxide, an indium oxide containing titanium oxide, an indium tin oxide containing titanium oxide, an indium zinc oxide, or an indium tin oxide to which silicon is added may be used. An indium gallium zinc oxide containing nitrogen may be used. With the use of such a material, hydrogen contained in the oxide406can be captured in some cases. Alternatively, hydrogen entering from an external insulator or the like can be captured in some cases.

A stack including a plurality of conductive layers formed using the above materials may be used. For example, a stacked-layer structure formed using a combination of a material containing the above-described metal element and a conductive material containing oxygen may be used. Alternatively, a stacked-layer structure formed using a combination of a material containing the above-described metal element and a conductive material containing nitrogen may be used. Alternatively, a stacked-layer structure formed using a combination of a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

When the oxide is used for the channel formation region of the transistor, a stacked-layer structure formed using a material containing the above-described metal element and a conductive material containing oxygen is preferably used for the gate electrode. In that case, the conductive material containing oxygen is preferably formed on the channel formation region side. When the conductive material containing oxygen is formed on the channel formation region side, oxygen released from the conductive material is likely to be supplied to the channel formation region.

<Metal Oxide Applicable to Oxides406and506>

The oxides406and506of one embodiment of the present invention will be described below. For the oxides406and506, a metal oxide functioning as an oxide semiconductor (hereinafter, the metal oxide is also referred to as an oxide semiconductor) is preferably used.

Note that in this specification and the like, a metal oxide containing nitrogen is also called a metal oxide in some cases. Moreover, a metal oxide containing nitrogen may be called a metal oxynitride.

Here, the case where the metal oxide contains indium, the element M, and zinc is considered. The terms of the atomic ratio of indium to the element M and zinc contained in the metal oxide are denoted by [In], [M], and [Zn], respectively.

Preferred ranges of the atomic ratio of indium to the element M and zinc contained in the metal oxide that can be used for the oxides406aand406bare described with reference toFIGS. 12A to 12C. Note that the proportion of oxygen atoms is not shown inFIGS. 12A to 12C. The terms of the atomic ratio of indium to the element M and zinc contained in the metal oxide are denoted by [In], [M], and [Zn], respectively.

InFIGS. 12A to 12C, broken lines indicate a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):1 (−1≤α≤1), a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):2, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):3, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):4, and a line where the atomic ratio [In]:[M]:[Zn] is (1+α): (1−α):5.

Furthermore, dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is 5:1:β (β≥0), a line where the atomic ratio [In]:[M]:[Zn] is 2:1:β a line where the atomic ratio [In]:[M]:[Zn] is 1:1:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:2:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:3:β, and a line where the atomic ratio [In]:[M]:[Zn] is 1:4:β.

Furthermore, a metal oxide with the atomic ratio of [In]:[M]:[Zn]=0:2:1 or a neighborhood thereof inFIGS. 12A to 12Ctends to have a spinel crystal structure.

A plurality of phases (e.g., two phases or three phases) exist in the metal oxide in some cases. For example, with an atomic ratio [In]:[M]:[Zn] that is close to 0:2:1, two phases of a spinel crystal structure and a layered crystal structure are likely to exist. In addition, with an atomic ratio [In]:[M]:[Zn] that is close to 1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure are likely to exist. In the case where a plurality of phases exist in the metal oxide, a grain boundary might be formed between different crystal structures.

A region A inFIG. 12Arepresents an example of the preferred range of the atomic ratio of indium, the element M, and zinc contained in the metal oxide.

In addition, the metal oxide having a higher content of indium can have higher carrier mobility (electron mobility). Thus, a metal oxide having a high content of indium has higher carrier mobility than a metal oxide having a low content of indium.

By contrast, when the indium content and the zinc content in a metal oxide become lower, carrier mobility becomes lower. Thus, with an atomic ratio of [In]:[M]:[Zn]=0:1:0 and the neighborhood thereof (e.g., the region C inFIG. 12C), insulation performance becomes better.

For example, the metal oxide used as the oxide406b, the oxide506b1, and the oxide506b2preferably have an atomic ratio represented by the region A inFIG. 12A. The metal oxide with the atomic ratio has high carrier mobility. The atomic ratio of In to Ga and Zn of the metal oxide used as the oxide406b, the oxide506b1, and the oxide506b2may be 4:2:3 to 4:2:4.1 or in the neighborhood thereof, for example. By contrast, the metal oxide used as the oxide406a, the oxide506a1, and the oxide506a2preferably have an atomic ratio represented by the region C inFIG. 12C. The metal oxide with the atomic ratio has relatively high insulating properties. The atomic ratio of In to Ga and Zn of the metal oxide used as the oxide406a, the oxide506a1, and the oxide506a2may be approximately 1:3:4, for example. Note that the metal oxide that is used as the oxide406cand the oxide506cmay be the metal oxide that can be used as the oxide406a, the oxide506a1, and the oxide506a2or the metal oxide that can be used as the oxide406b, the oxide506b1, and the oxide506b2.

A metal oxide having an atomic ratio in the region A, particularly in a region B inFIG. 12B, has high carrier mobility and high reliability and is excellent.

Note that the region B includes an atomic ratio of [In]:[M]:[Zn]=4:2:3 to 4:2:4.1 and the neighborhood thereof. The neighborhood includes an atomic ratio of [In]:[M]:[Zn]=5:3:4. Note that the region B includes an atomic ratio of [In]:[M]:[Zn]=5:1:6 and the neighborhood thereof and an atomic ratio of [In]:[M]:[Zn]=5:1:7 and the neighborhood thereof.

In the case where the metal oxide is formed of an In-M-Zn oxide, it is preferable to use a target containing a polycrystalline In-M-Zn oxide as the sputtering target. Note that the atomic ratio of the formed metal oxide varies from the above atomic ratios of metal elements of the sputtering targets in a range of ±40%. For example, when a sputtering target with an atomic ratio of In:Ga:Zn=4:2:4.1 is used for forming the metal oxide, the atomic ratio of In to Ga and Zn in the formed metal oxide may be 4:2:3 or in the neighborhood of 4:2:3. When a sputtering target with an atomic ratio of In:Ga:Zn=5:1:7 is used for forming the metal oxide, the atomic ratio of In to Ga and Zn in the formed metal oxide may be 5:1:6 or in the neighborhood of 5:1:6.

Note that the property of a metal oxide is not uniquely determined by an atomic ratio. Even with the same atomic ratio, the property of a metal oxide might be different depending on a formation condition. For example, in the case where the metal oxide is deposited with a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of the target is formed. In particular, [Zn] in the film might be smaller than [Zn] in the target depending on the substrate temperature in deposition. Thus, the illustrated regions each represent an atomic ratio with which a metal oxide tends to have specific characteristics, and boundaries of the regions A to C are not clear.

<Composition of Metal Oxide>

Described below is the composition of a cloud-aligned composite oxide semiconductor (CAC-OS) applicable to a transistor disclosed in one embodiment of the present invention.

In this specification and the like, “c-axis aligned crystal (CAAC)” or “cloud-aligned composite (CAC)” might be stated. Note that CAAC refers to an example of a crystal structure, and CAC refers to an example of a function or a material composition.

A CAC-OS or a CAC metal oxide has a conducting function in a part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS or the CAC metal oxide has a function of a semiconductor. In the case where the CAC-OS or the CAC metal oxide is used in an active layer of a transistor, the conducting function is to allow electrons (or holes) serving as carriers to flow, and the insulating function is to not allow electrons serving as carriers to flow. By the complementary action of the conducting function and the insulating function, the CAC-OS or the CAC metal oxide can have a switching function (on/off function). In the CAC-OS or the CAC metal oxide, separation of the functions can maximize each function.

Furthermore, in the CAC-OS or the CAC metal oxide, the conductive regions and the insulating regions each have a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3 nm and are dispersed in the material, in some cases.

The CAC-OS or the CAC metal oxide includes components having different bandgaps. For example, the CAC-OS or the CAC metal oxide contains a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region. In the case of such a composition, carriers mainly flow in the component having a narrow gap. The component having a narrow gap complements the component having a wide gap, and carriers also flow in the component having a wide gap in conjunction with the component having a narrow gap. Therefore, in the case where the above-described CAC-OS or the CAC metal oxide is used in a channel region of a transistor, high current drive capability in the on state of the transistor, that is, high on-state current and high field-effect mobility, can be obtained.

In other words, the CAC-OS or the CAC metal oxide can be called a matrix composite or a metal matrix composite.

<Structure of Metal Oxide>

The CAAC-OS has c-axis alignment, its nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion. Note that distortion refers to a portion where the direction of a lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where the nanocrystals are connected.

The shape of the nanocrystal is basically a hexagon but is not always a regular hexagon and is a non-regular hexagon in some cases. A pentagonal lattice arrangement, a heptagonal lattice arrangement, and the like are included in the distortion in some cases. Note that a clear grain boundary cannot be observed even in the vicinity of distortion in the CAAC-OS. That is, a lattice arrangement is distorted and thus formation of a grain boundary is inhibited. This is probably because the CAAC-OS can tolerate distortion owing to a low density of oxygen atom arrangement in an a-b plane direction, a change in interatomic bond distance by substitution of a metal element, and the like.

The CAAC-OS is an oxide semiconductor with high crystallinity. By contrast, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur because a clear grain boundary cannot be observed. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies). Thus, an oxide semiconductor including a CAAC-OS is physically stable. Therefore, the oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.

In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method.

The a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low-density region. That is, the a-like OS has low crystallinity as compared with the nc-OS and the CAAC-OS.

An oxide semiconductor can have any of various structures which show various different properties. Two or more of the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the nc-OS, and the CAAC-OS may be included in an oxide semiconductor of one embodiment of the present invention.

Next, the case where the oxide semiconductor is used for a transistor will be described.

When the oxide semiconductor is used in a transistor, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability.

Moreover, the carrier density in the region426aof the oxide406bin the transistor is preferably low. In order to reduce the carrier density of the oxide semiconductor film, the concentration of impurities in the oxide semiconductor film is reduced so that the density of defect states can be reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. The region426aof the oxide406bhas, for example, a carrier density lower than 8×1011/cm3, preferably lower than 1×1011/cm3, and further preferably lower than 1×1010/cm3, and higher than or equal to 1×10−9/cm3.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases.

Charge trapped by the trap states in the oxide semiconductor takes a long time to be released and may behave like fixed charge. Thus, a transistor whose channel region is formed in the oxide semiconductor having a high density of trap states has unstable electrical characteristics in some cases.

In order to obtain stable electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the region426aof the oxide406b. In addition, in order to reduce the concentration of impurities in the region426aof the oxide406b, the concentration of impurities in a film that is adjacent to the region426ais preferably reduced. As examples of the impurities, hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like are given.

Here, the influence of impurities in the oxide semiconductor is described.

When silicon or carbon that is one of Group 14 elements is contained in the oxide, defect states are formed. Thus, the concentration of silicon or carbon (the concentration is measured by SIMS) in the region426aof the oxide406bis set to be lower than or equal to 2×1018atoms/cm3, preferably lower than or equal to 2×1017atoms/cm3.

When the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor including an oxide semiconductor that contains an alkali metal or an alkaline earth metal is likely to be normally-on. Therefore, it is preferable to reduce the concentration of an alkali metal or an alkaline earth metal in the region426aof the oxide406b. Specifically, the concentration of alkali metal or alkaline earth metal in the region426aof the oxide406b, which is measured by SIMS, is lower than or equal to 1×1018atoms/cm3, preferably lower than or equal to 2×1016atoms/cm3.

When the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor containing nitrogen in the region426aof the oxide406btends to have normally-on characteristics. For this reason, nitrogen in the region426aof the oxide406bis preferably reduced as much as possible; for example, the concentration of nitrogen in the region426aof the oxide406bmeasured by SIMS is set to lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, and still further preferably lower than or equal to 5×1017atoms/cm3.

Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy, in some cases. Entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, the transistor containing much hydrogen in the region426aof the oxide406btends to have normally-on characteristics. For this reason, hydrogen in the region426aof the oxide406bis preferably reduced as much as possible. Specifically, the hydrogen concentration of the oxide semiconductor measured by SIMS is lower than 1×1020atoms/cm3, preferably lower than 1×1019atoms/cm3, further preferably lower than 5×1018atoms/cm3, and still further preferably lower than 1×1018atoms/cm3.

By reducing impurities in the region426aof the oxide406bto an enough level, the transistor can have stable electrical characteristics.

Next, a method of manufacturing the transistor1000and the transistor2000in parallel which are included in the semiconductor device of one embodiment of the present invention is described with reference toFIGS. 5A to 5DtoFIGS. 11A to 11D.FIGS. 5A and 5C,FIGS. 6A and 6C,FIGS. 7A and 7C,FIGS. 8A and 8C,FIGS. 9A and 9C,FIGS. 10A and 10C, andFIGS. 11A and 11Care cross-sectional views taken along the dashed-dotted line A1-A2inFIG. 2.FIGS. 5B and 5D,FIGS. 6B and 6D,FIGS. 7B and 7D,FIGS. 8B and 8D,FIGS. 9B and 9D,FIGS. 10B and 10D, andFIGS. 11B and 11Dare cross-sectional views taken along the dashed-dotted line A3-A4inFIG. 2.

First, a substrate (not illustrated) is prepared, and the insulator400is formed over the substrate. The insulator400and the insulator432can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

Note that CVD methods can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Moreover, the CVD methods can be classified into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on a source gas.

The use of a PECVD method can provide a high-quality film at a relatively low temperature. A thermal CVD method does not use plasma and thus causes less plasma damage to an object. A wiring, an electrode, an element (e.g., a transistor or a capacitor), or the like included in a semiconductor device might be charged up by receiving charges from plasma, for example. In that case, accumulated charges might break the wiring, electrode, element, or the like included in the semiconductor device. By contrast, when a thermal CVD method not using plasma is employed, such plasma damage is not caused and the yield of semiconductor devices can be increased. A thermal CVD method does not cause plasma damage during deposition, so that a film with few defects can be obtained.

An ALD method also causes less plasma damage to an object. Since an ALD method does not cause plasma damage during deposition, a film with few defects can be obtained.

Unlike in a deposition method in which particles ejected from a target or the like are deposited, in a CVD method and an ALD method, a film is formed by reaction at a surface of an object. Thus, a CVD method and an ALD method can provide favorable step coverage almost regardless of the shape of an object. In particular, an ALD method can provide excellent step coverage and excellent thickness uniformity and thus can be favorably used for covering a surface of an opening with a high aspect ratio, for example. On the other hand, an ALD method has a relatively low deposition rate; thus, it is sometimes preferable to combine an ALD method with another deposition method with a high deposition rate such as a CVD method.

When a CVD method or an ALD method is used, the composition of a film to be formed can be controlled with the flow rate ratio of a source gas. For example, by a CVD method or an ALD method, a film with a certain composition can be formed depending on the flow rate ratio of a source gas. Moreover, by changing the flow rate ratio of a source gas during deposition by a CVD method or an ALD method, a film whose composition is continuously changed can be formed. In the case where a film is formed while changing the flow rate ratio of a source gas, as compared to the case where a film is formed using a plurality of deposition chambers, time taken for the deposition can be reduced because time taken for transfer and pressure adjustment is omitted. Thus, semiconductor devices can be manufactured with improved productivity in some cases.

In this embodiment, silicon oxynitride is deposited as the insulator400by a CVD method.

Then, the insulator432is formed over the insulator400. In this embodiment, aluminum oxide is deposited as the insulator432by a sputtering method. The insulator432may have a multilayer structure. For example, aluminum oxide may be formed by a sputtering method and another aluminum oxide may be formed by an ALD method over the aluminum oxide. Alternatively, aluminum oxide may be formed by an ALD method and another aluminum oxide may be formed by a sputtering method over the aluminum oxide.

Then, the insulator430is formed over the insulator432. The insulator430can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide was deposited as the insulator430by a CVD method.

Next, a groove that reaches the insulator432is formed in the insulator430. Examples of the groove include a hole and an opening. In forming the groove, wet etching may be employed; however, dry etching is preferably employed in terms of microfabrication. The insulator432is preferably an insulator that functions as an etching stopper film used in forming the groove by etching the insulator430. In the case where a silicon oxide film is used for the insulator430in which the groove is to be formed, the insulator432is preferably formed using a silicon nitride film, an aluminum oxide film, or a hafnium oxide film, for example.

After the formation of the groove, the conductive film to be the conductor440a, the conductor540a, and the conductor441ais formed. The conductive film desirably contains a conductor that has a function of inhibiting the penetration of oxygen. For example, tantalum nitride, tungsten nitride, or titanium nitride can be used. Alternatively, a stacked-layer film formed using the conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductor to be the conductor440can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, as a conductive film to be the conductor440a, the conductor540a, and the conductor441a, tantalum nitride or a stacked film obtained by stacking titanium nitride over tantalum nitride is formed by a sputtering method. With use of such metal nitride for the conductor440a, the conductor540a, and the conductor441a, even when metal that easily diffuses, such as copper, is used for the conductor440b, the conductor540b, and the conductor441bto be described later, the metal can be prevented from diffusing from the conductor440a, the conductor540a, and the conductor441ato the outside.

Next, a conductive film to be the conductor440b, the conductor540b, and the conductor441bis formed over the conductive film to be the conductor440a, the conductor540a, and the conductor441a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, as the conductive film to be the conductor440b, the conductor540b, and the conductor441b, a film of a low resistance conductive material, such as copper, is formed.

Next, CMP treatment is performed to remove a portion above the insulator430of the conductive film to be the conductor440a, the conductor540a, and the conductor441aand a portion above the insulator430of the conductive film to be the conductor440b, the conductor540b, and the conductor441b. As a result, the conductive film to be the conductor440a, the conductor540a, and the conductor441aand the conductive film to be the conductor440b, the conductor540b, and the conductor441bremain only in the grooves. Thus, the conductor440including the conductor440aand the conductor440bwhose top surfaces are flat, the conductor540including the conductor540aand the conductor540bwhose top surfaces are flat, and the conductor441including the conductor441aand the conductor441bwhose top surfaces are flat can be formed (seeFIGS. 5A and 5B).

For example, the conductor441, the conductor440, and the conductor540can be formed in parallel by a dual damascene method. In this case, when the groove in which the conductor440is embedded and the groove in which the conductor540is embedded are formed in the insulator430, the groove in which the conductor441is embedded can be formed in the insulator400, the insulator432, and the insulator430in parallel to the groove in which the conductor440is embedded and the groove in which the conductor540is embedded.

Next, the insulator401is formed over the conductor440, the conductor540, the conductor441, and the insulator430. The insulator401can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon nitride is deposited as the insulator401by a CVD method. With use of the insulator that is less likely to transmit copper, such as silicon nitride, as the insulator401, even when metal that easily diffuses, such as copper, is used for the conductor440b, the conductor441b, and the like, the metal can be prevented from diffusing into layers above the insulator401.

Next, the insulator301is formed over the insulator401. The insulator301can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is deposited as the insulator301by a CVD method.

Next, grooves that reach the conductor440and the conductor540are formed in the insulator401and the insulator301. Examples of the groove include a hole and an opening. In forming the groove, wet etching may be employed; however, dry etching is preferably employed in terms of microfabrication.

After the formation of the grooves, a conductive film to be the conductor410aand the conductor510ais formed. The conductive film to be the conductor410aand the conductor510adesirably contains a conductive material that has a function of inhibiting the penetration of oxygen. For example, tantalum nitride, tungsten nitride, or titanium nitride can be used. Alternatively, a stacked-layer film formed using the conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film to be the conductor410acan be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, tantalum nitride is deposited by a sputtering method for the conductive film to be the conductor410aand the conductor510a.

Next, a conductive film to be the conductor410band the conductor510bis formed over the conductive film to be the conductor410aand the conductor510a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, for the conductive film to be the conductor410band the conductor510b, titanium nitride is deposited by a CVD method and tungsten is deposited by a CVD method over the titanium nitride.

Next, CMP treatment is performed to remove a portion above the insulator301of the conductive film to be the conductor410aand the conductor510aand a portion above the insulator301of the conductive film to be the conductor410band the conductor510b. As a result, the conductive film to be the conductor410aand the conductor510aand the conductive film to be the conductor410band the conductor510bremain only in the grooves. Thus, the conductor410including the conductor410aand the conductor410bwhose top surfaces are flat and the conductor510including the conductor510aand the conductor510bwhose top surfaces are flat can be formed (seeFIGS. 5A and 5B).

Then, the insulator302is formed over the insulator301, the conductor410, and the conductor510. The insulator302can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, the insulator303is formed over the insulator302. The insulator303can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

After that, the insulator402is formed over the insulator303. The insulator402can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (seeFIGS. 5A and 5B).

Next, first heat treatment is preferably performed. The first heat treatment can be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., and further preferably higher than or equal to 320° C. and lower than or equal to 450° C. The first heat treatment is performed in a nitrogen atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under a reduced pressure. Alternatively, the first heat treatment may be performed in such a manner that heat treatment is performed in a nitrogen atmosphere or an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen. By the first heat treatment, impurities such as water or hydrogen contained in the insulator402can be removed, for example. In the first heat treatment, plasma treatment using oxygen may be performed under a reduced pressure. The plasma treatment using oxygen is preferably performed using an apparatus including a power source for generating high-density plasma using microwaves, for example. Alternatively, a power source for applying a radio frequency (RF) to a substrate side may be provided. The use of high-density plasma enables high-density oxygen radicals to be produced, and application of the RF to the substrate side allows oxygen radicals generated by the high-density plasma to be efficiently introduced into the insulator402. Alternatively, after plasma treatment using an inert gas is performed with the apparatus, plasma treatment using oxygen may be performed in order to compensate for released oxygen. Note that the first heat treatment is not necessary in some cases.

Alternatively, the heat treatment can be performed after the formation of the insulator302, after the formation of the insulator303, and after the formation of the insulator402. Although each heat treatment can be performed under the conditions for the first heat treatment, the heat treatment after the formation of the insulator302is preferably performed in an atmosphere containing nitrogen.

In this embodiment, the first heat treatment is performed at 400° C. in a nitrogen atmosphere for one hour after the insulator402is formed.

Next, an oxide film to be the oxide406a, the oxide506a1, and the oxide506a2and an oxide film to be the oxide406b, the oxide506b1, and the oxide506b2are formed in this order over the insulator402. Note that it is preferable that the oxide films be successively formed without being exposed to the atmosphere. In that case, impurities or moisture in the atmosphere can be prevented from being attached onto the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2, and the interface between the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2and the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2and the vicinity of the interface can be kept clean.

The oxide film to be the oxide406a, the oxide506a1, and the oxide506a2and the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In the case where the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2and the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2are formed by a sputtering method, for example, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. When the proportion of oxygen in the sputtering gas is increased, the amount of excess oxygen in the oxide films to be formed can be increased. In the case where the oxide films are formed by a sputtering method, the above-described In-M-Zn oxide target can be used.

In particular, part of oxygen contained in the sputtering gas is supplied to the insulator402in some cases, at the formation of the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2.

Note that the proportion of oxygen contained in the sputtering gas for the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2is 70% or higher, preferably 80% or higher, and further preferably 100%.

In the case where the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2is formed by a sputtering method, when the proportion of oxygen in the sputtering gas is higher than or equal to 1% and lower than or equal to 30%, preferably higher than or equal to 5% and lower than or equal to 20%, an oxygen-deficient oxide semiconductor is formed. A transistor including an oxygen-deficient oxide semiconductor can have relatively high field-effect mobility.

In the case where an oxygen-deficient oxide semiconductor is used for the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2, an oxide film containing excess oxygen is preferably used as the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2. Oxygen doping treatment may be performed after the formation of the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2.

In this embodiment, the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2is formed by a sputtering method using a target containing In, Ga, and Zn at an atomic ratio of 1:3:4, and the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2is formed by a sputtering method using a target containing In, Ga, and Zn at an atomic ratio of 4:2:4.1.

After that, second heat treatment may be performed. For the second heat treatment, the conditions for the first heat treatment can be used. By the second heat treatment, impurities such as water or hydrogen contained in the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2and the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2can be removed. In this embodiment, the second heat treatment is performed in such a manner that treatment at 400° C. in a nitrogen atmosphere is performed for one hour and then treatment at 400° C. in an oxygen atmosphere is successively performed for one hour.

Next, the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2and the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2are processed into island shapes to form the oxide406a, the oxide506a1, the oxide506a2, the oxide406b, the oxide506b1, and the oxide506b2(seeFIGS. 5C and 5D). Here, the oxides406aand406bare formed so that at least parts thereof overlap with the conductor410. At least part of the conductor510overlaps with a region between the oxides506a1and506b1and the oxides506a2and506b2. When the oxide films are collectively processed, the side surface of the oxide406band the side surface of the oxide406apreferably form one surface. The side surface of the oxide506b1and the side surface of the oxide506a1preferably form one surface. The side surface of the oxide506b2and the side surface of the oxide506a2preferably form one surface. A lithography method may be employed for the processing of the oxide films. Alternatively, a dry etching method or a wet etching method may be used for the processing. A dry etching method is suitable for minute processing.

In the lithography method, first, a resist is exposed to light through a mask. Next, a region exposed to light is removed or left using a developing solution, so that a resist mask is formed. Then, etching is conducted with the resist mask. As a result, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. The resist mask is formed by, for example, exposure of the resist to light such as KrF excimer laser light, ArF excimer laser light, or extreme ultraviolet (EUV) light. A liquid immersion technique may be employed in which a portion between a substrate and a projection lens is filled with a liquid (e.g., water) to perform light exposure. An electron beam or an ion beam may be used instead of the above-mentioned light. Note that a mask is not necessary in the case of using an electron beam or an ion beam. To remove the resist mask, dry etching treatment such as ashing or wet etching treatment can be used. Alternatively, wet etching treatment can be performed after dry etching treatment. Further alternatively, dry etching treatment can be performed after wet etching treatment.

Instead of the resist mask, a hard mask formed of an insulator or a conductor may be used. In the case where a hard mask is used, a hard mask with a desired shape can be formed in the following manner: an insulating film or a conductive film that is the material of the hard mask is formed over the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2, a resist mask is formed thereover, and then the material of the hard mask is etched. The etching of the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2and the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2may be performed after or without removal of the resist mask. In the latter case, the resist mask may be eliminated during the etching. The hard mask may be removed by etching after the etching of the oxide films. The hard mask does not need to be removed in the case where the material of the hard mask does not affect the following process or can be utilized in the following process.

As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus including parallel plate electrodes may have a structure in which high-frequency power is applied to one of the parallel plate electrodes. Alternatively, different high-frequency powers are applied to one of the parallel plate electrodes. Further alternatively, high-frequency powers with the same frequency are applied to the parallel plate electrodes. Still further alternatively, high-frequency powers with different frequencies are applied to the parallel plate electrodes. Alternatively, a dry etching apparatus including a high-density plasma source can be used. As the dry etching apparatus including a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used, for example.

Note that after the processing of the oxide films, the oxides406aand406b, the oxides506a1and506b1, and the oxides506a2and506b2may have tapered cross sections. The taper angle to a plane parallel to the bottom surface of the substrate is, for example, greater than or equal to 30° and less than 75°. Owing to such a taper angle, the coverage with films formed later in the manufacturing process can be improved. A dry etching method is suitable the processing into a tapered shape.

In some cases, treatment such as dry etching performed in the above process causes the attachment or diffusion of impurities due to an etching gas or the like to a surface or an inside of the oxide406a, the oxide506a1, the oxide506a2, the oxide406b, the oxide506b1, the oxide506b2, or the like. Examples of the impurities include fluorine and chlorine.

To remove the impurities or the like, cleaning is performed. As the cleaning, any of wet cleaning using a cleaning solution or the like, plasma treatment using plasma, cleaning by heat treatment, and the like can be performed by itself or in appropriate combination.

The wet cleaning may be performed using an aqueous solution in which oxalic acid, phosphoric acid, hydrofluoric acid, or the like is diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

Next, third heat treatment may be performed. For the third heat treatment, the conditions for the first heat treatment can be used. Note that the third heat treatment is not necessary in some cases. In this embodiment, the third heat treatment is not performed.

Next, the oxide film406C is formed over the insulator402, the oxide406a, the oxide506a1, the oxide506a2, the oxide406b, the oxide506b1, and the oxide506b2(seeFIGS. 6A and 6B). The oxide film406C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The oxide film406C is an oxide film to be the oxide406cand the oxide506c. Therefore, in accordance with characteristics required for the oxide406cand the oxide506c, the oxide film406C is formed by a method similar to the method of forming the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2or the method of forming the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2. In this embodiment, the oxide film406C is formed by a sputtering method using a target with an atomic ratio of In:Ga:Zn=4:2:4.1.

Next, the oxide film406C is processed into an island shape to form the oxide406cand the oxide506c(seeFIGS. 6C and 6D). Here, the oxide406cpreferably covers the oxide406aand the oxide406b. In addition, the oxide506cpreferably covers the oxide506a1, the oxide506b1, the oxide506a2, and the oxide506b2. A lithography method may be employed for the processing of the oxide film406C. Alternatively, a dry etching method or a wet etching method may be used for the processing. A dry etching method is suitable for minute processing. In the lithography method, a hard mask may be used instead of a resist mask.

Next, an insulating film to be the insulator412and the insulator512, a conductive film to be the conductor404aand the conductor504a, a conductive film to be the conductor404band the conductor504b, and an insulating film to be the insulator419and the insulator519are formed in this order over the insulator402, the oxide406c, and the oxide506c.

The insulating film to be the insulator412and the insulator512can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Note that oxygen is excited by a microwave to generate high-density oxygen plasma, and the insulating film to be the insulator412and the insulator512is exposed to the oxygen plasma, whereby oxygen can be supplied to the insulator412, the insulator512, the oxide406, and the oxide506. Furthermore, in a later step, by heat treatment performed after the formation of the insulator418and the insulator518, oxygen contained in the insulator412and the insulator512can be selectively diffused into the oxide406and the oxide506, leading to a reduction in oxygen vacancies in the oxide406and the oxide506.

Here, fourth heat treatment can be performed. For this heat treatment, the conditions for the first heat treatment can be used. The fourth heat treatment can reduce the moisture concentration and the hydrogen concentration in the insulating film to be the insulator412and the insulator512. Note that the fourth heat treatment is not necessary in some cases.

The conductive film to be the conductor404aand the conductor504acan be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the conductive film, conductive oxide that can be used as the conductor404aor the like is deposited by a sputtering method in an atmosphere containing oxygen, whereby oxygen can be added to the insulator412and the insulator512and oxygen can be supplied to the oxide406b, the oxide406c, and the oxide506c.

The conductive film to be the conductor404band the conductor504bcan be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. By forming the conductive film by a sputtering method, the conductive film to be the conductor404aand the conductor504acan have reduced electric resistance and become a conductor. Such a conductor can be called an oxide conductor (OC) electrode. Another conductor may be formed by a sputtering method or the like over the conductor over the OC electrode.

Here, fifth heat treatment can be performed. For the fifth heat treatment, the conditions for the first heat treatment can be used. The fifth heat treatment is necessarily be performed in some cases. In this embodiment, the fifth heat treatment is performed in a nitrogen atmosphere at 400° C. for one hour.

The insulating film to be the insulator419and the insulator519can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In particular, an ALD method is preferred. The insulating film to be the insulator419and the insulator519formed by an ALD method can have a thickness of greater than or equal to 1 nm and less than or equal to 20 nm, preferably greater than or equal to 5 nm and less than or equal to 10 nm. Here, this thickness is preferably larger than that of the insulating film to be the insulator418and the insulator518. With this structure, the insulator419is likely to be left over the conductor404and the insulator519is likely to be left over the conductor504in a later step of forming the insulator418and the insulator518.

Next, the insulating film to be the insulator412and the insulator512, the conductive film to be the conductor404aand the conductor504a, the conductive film to be the conductor404band the conductor504b, and the insulating film to be the insulator419and the insulator519are etched to form the insulator412, the insulator512, the conductor404a, the conductor504a, the conductor404b, the conductor504b, the insulator419, and the insulator519(seeFIGS. 7A and 7B). At least part of the insulator412, part of the conductor404a, part of the conductor404b, and part of the insulator419overlap with the conductor410and the oxide406. Furthermore, at least part of the insulator512, part of the conductor504a, part of the conductor504b, and part of the insulator519overlap with the conductor510and the oxide506. A lithography method may be employed for the processing of the insulating films.

Here, it is preferable that the position of a side surface of the insulator412be substantially the same as positions of side surfaces of the insulator419, the conductor404a, and the conductor404bwhen the substrate is perpendicularly seen from above. In addition, it is preferable that the position of a side surface of the insulator512be substantially the same as positions of side surfaces of the insulator519, the conductor504a, and the conductor504bwhen the substrate is perpendicularly seen from above.

Here, a cross section of the insulator412, the conductor404a, the conductor404b, and the insulator419and a cross section of the insulator512, the conductor504a, the conductor504b, and the insulator519are preferably tapered as little as possible. In that case, the insulator418and the insulator518are likely to be left in a later formation step of the insulator418and the insulator518.

Note that an upper portion of the oxide406cin a region not overlapping with the insulator412may be etched by the above etching. In that case, the oxide406cis thicker in the region overlapping with the insulator412than in the region not overlapping with the insulator412. The same applies to a region of the oxide506cwhich does not overlap with the insulator512.

Next, the insulating film to be the insulator418and the insulator518is formed by an ALD method to cover the insulator402, the oxide406, the insulator412, the conductor404, the insulator419, the oxide506, the insulator512, the conductor504, and the insulator519. The insulating film formed by an ALD method can have a thickness of greater than or equal to 1 nm and less than or equal to 20 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, and approximately 1 nm, for example. Furthermore, by an ALD method, even when the aspect ratio of a structure body formed of the insulator412, the conductor404, and the insulator419is extremely high, the insulating film can be formed on a top surface and a side surface of the structure body to have few pinholes and uniform thickness. In this embodiment, aluminum oxide is formed as the insulating film by an ALD method.

Next, the insulating film to be the insulator418and the insulator518is subjected to anisotropic etching to form the insulator418in contact with side surfaces of the insulator412, the conductor404, and the insulator419and the insulator518in contact with side surfaces of the insulator512, the conductor504, and the insulator519(seeFIGS. 7C and 7D). Dry etching is preferably performed as the anisotropic etching. In this manner, the insulating film in a region on a plane substantially parallel to the substrate can be removed, so that the insulator418and the insulator518can be formed in a self-aligned manner.

Here, the thicknesses of the insulator419and the insulator519are set larger than the thickness of the insulating film to be the insulator418and the insulator518, in which case the insulator419, the insulator418, the insulator519, and the insulator518can be left even after upper portions of the insulator419and the insulator418and upper portions of the insulator519and the insulator518are removed. Furthermore, when the oxide406and the oxide506have tapered edges, time for removing the insulating film to be the insulator418and the insulator518formed in contact with the side surfaces of the oxide406and the oxide506can be shortened, which facilitates formation of the insulator418and the insulator518.

An insulator may be left on the side surface of the oxide406and/or the side surface of the oxide506. The insulator on the side surface of the oxide406and/or the side surface of the oxide506can reduce impurities such as water or hydrogen that enter the oxide406and/or the oxide506and can prevent outward diffusion of oxygen from the oxide406and/or the oxide506, in some cases.

Next, the oxide406and the oxide506are subjected to plasma treatment using plasma422, with use of the insulator412, the conductor404, the insulator418, the insulator419, the insulator512, the conductor504, the insulator518, and the insulator519as masks (seeFIGS. 8A and 8B). The plasma treatment is performed in an atmosphere containing the above-described element forming an oxygen vacancy or an element trapped by an oxygen vacancy. For example, the plasma treatment is performed using an argon gas and a nitrogen gas.

Instead of the plasma treatment, a dopant may be added. For the addition of the dopant, an ion implantation method by which an ionized source gas is subjected to mass separation and then added, an ion doping method by which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used. In the case where mass separation is performed, an ion species to be added and its concentration can be strictly controlled. By contrast, in the case where mass separation is not performed, ions at a high concentration can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be employed. Instead of the term “dopant,” the term “ion,” “donor,” “acceptor,” “impurity,” “element,” or the like may be used.

As the dopant, the element forming an oxygen vacancy, the element trapped by an oxygen vacancy, or the like may be used. Typical examples of such an element are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas element. Typical examples of the rare gas element are helium, neon, argon, krypton, and xenon.

As described above, when the indium content in the oxide406and the oxide506is increased, the carrier density can be increased and the resistance can be decreased. For example, a metal element such as indium which increases the carrier density of the oxide406can be used as the dopant. Here, the dopant is preferably added such that the concentration of indium has a peak in the oxide406a, the oxide506a1, and the oxide506a2.

In this way, it is preferable that the atomic ratio of indium to the element M in the regions426band426cin the oxide406abe substantially the same as the atomic ratio of indium to the element M in the oxide406b. In other words, in the oxide406a, the atomic ratio of indium to the element M in the regions426band426cis preferably larger than the atomic ratio of indium to the element M in the region426a.

With indium added in the above manner, even when the oxide406cis removed, the thickness of the oxide406bis small, and electric resistance of the oxide406bis high in the manufacturing process of the transistor1000, the region426band the region426cin the oxide406can serve as source and drain regions owing to the sufficiently reduced resistance of the oxide406ain the region426band the region426c.

Next, the insulator409is formed to cover the insulator402, the oxide406, the insulator418, the insulator419, the insulator502, the oxide506, the insulator518, and the insulator519(seeFIGS. 8C and 8D). The insulator409can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The insulating film409is preferably formed in an atmosphere containing at least one of nitrogen and hydrogen. In that case, oxygen vacancies are formed mainly in the regions of the oxide406band the oxide406cnot overlapping with the insulator412and the oxygen vacancies and impurity elements such as nitrogen or hydrogen are bonded to each other, leading to an increase in carrier density. In this manner, the regions426band426cwith reduced resistance can be formed. In addition, regions of the oxide506band the oxide506cwhich do not overlap with the insulator512and the vicinity of the regions can have high carrier density and low resistance. For the insulator409, for example, silicon nitride, silicon nitride oxide, or silicon oxynitride can be formed by a CVD method. In this embodiment, silicon nitride oxide is used for the insulator409.

As described above, in the method for manufacturing a semiconductor device described in this embodiment, a source region and a drain region can be formed in a self-aligned manner owing to the formation of the insulator409, even in a minute transistor whose channel length is approximately 10 nm to 30 nm. Thus, minute or highly integrated semiconductor devices can be manufactured with high yield.

Here, the top and side surfaces of the conductor404and the insulator412are covered with the insulator419and the insulator418, whereby impurity elements such as nitrogen or hydrogen can be prevented from entering the conductor404and the insulator412. Thus, the impurity elements such as nitrogen or hydrogen can be prevented from passing through the conductor404and the insulator412and entering the region426athat functions as the channel formation region of the transistor1000. Similarly, the top and side surfaces of the conductor504and the insulator512are covered with the insulator519and the insulator518, whereby the impurity elements can be prevented from entering the channel formation region of the transistor2000. Therefore, the transistor1000and the transistor2000with favorable electrical characteristics can be provided.

An insulating material having a function of inhibiting the penetration of oxygen and impurities such as water or hydrogen, is preferably used for the insulator409. When such an insulator is provided over the regions426band426c, oxygen or impurities such as water or hydrogen can be prevented from entering the regions426band426c, leading to the prevention of a change in carrier density.

Note that the case where the region426band the region426care formed through the plasma treatment using the plasma422and the formation of the insulator419is described above, but this embodiment is not limited to this case. For example, the region426band the region426cmay be formed through one of the plasma treatment using the plasma422and the formation of the insulator419.

Next, an insulating film415A is deposited over the insulator409(seeFIGS. 9A and 9B). The insulating film415A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, the insulating film415A can be formed by a spin coating method, a dipping method, a droplet discharging method (such as an ink-jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, a curtain coater method, or the like. In this embodiment, silicon oxynitride is used for the insulating film415A.

Next, the insulating film415A is partly removed to form the insulator415(seeFIGS. 9C and 9D). The insulator415is preferably formed to have a flat top surface. For example, the top surface of the insulating film415A may be flat immediately after the film formation. Alternatively, the insulator415may have flatness in the following manner, for example: an insulator and the like are removed from the top surface after the film formation so that the top surface of the insulator415becomes parallel to a reference surface such as the rear surface of the substrate. Such treatment is referred to as planarization treatment. Examples of the planarization treatment include CMP treatment and dry etching treatment. In this embodiment, CMP treatment is performed as the planarization treatment. Note that the top surface of the insulator415is not necessarily flat.

Next, an opening reaching the region426bof the oxide406, an opening reaching the region426cof the oxide406, an opening reaching a portion of the oxide506b1that overlaps with the oxide506c, and an opening reaching a portion of the oxide506b2that overlaps with the oxide506care formed in the insulator415and the insulator409. A lithography method may be employed for the formation of the openings. Here, the openings reaching the oxide406are formed so that the side surfaces of the oxide406are exposed and the conductor451aand the conductor451bare in contact with the side surfaces of the oxide406. Similarly, the openings reaching the oxide506are formed so that the side surfaces of the oxide506are exposed and the conductor551aand the conductor551bare in contact with the side surfaces of the oxide506.

Next, a conductive film to be the conductor451a, the conductor451b, the conductor551a, and the conductor551bis formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, CMP treatment is performed to remove a portion above the insulator415of the conductive film to be the conductor451a, the conductor451b, the conductor551a, and the conductor551b. As a result, the conductive film is left only in the openings, whereby the conductor451a, the conductor451b, the conductor551a, and the conductor551bwith flat top surfaces can be formed.

Next, a conductive film is formed and processed by a photolithography method to form the conductor452a, the conductor452b, the conductor552a, and the conductor552b(seeFIGS. 10C and 10D). The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Like the conductor440, the conductors452a,452b,552a, and552bmay be embedded in an insulator.

Next, the insulator411is formed over the insulator415, the conductor452a, the conductor452b, the conductor552a, and the conductor552b(seeFIGS. 11A and 11B). The insulator411can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a stacked-layer film of aluminum oxide formed by an ALD method and silicon oxynitride formed by a CVD method is used as the insulator411.

Next, a conductive film is formed over the insulator411and processed by a photolithography method to form the conductor454. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Like the conductor440, the conductor454may be embedded in an insulator.

Next, the insulator420is formed over the insulator411and the conductor454(seeFIGS. 11C and 11D). The insulator420can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, the insulator420can be formed by a spin coating method, a dipping method, a droplet discharging method (such as an ink-jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, a curtain coater method, or the like. Note that a top surface of the insulator420is preferably planarized by CMP treatment or the like.

Through the above process, the semiconductor device including the transistor1000, the transistor2000, and the capacitor1500can be manufactured (seeFIGS. 1A and 1B). As illustrated inFIGS. 5A to 5DtoFIGS. 11A to 11D, by the method of manufacturing a semiconductor device described in this embodiment, the transistor1000and the transistor2000can be formed in parallel, whereby the productivity of the semiconductor device can be improved.

As described above, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated, a semiconductor device having good electrical characteristics, a semiconductor device with low off-state current, a transistor with high on-state current, a highly reliable semiconductor device, a semiconductor device with low power consumption, or a semiconductor device that can be manufactured with high productivity can be provided.

An example of a semiconductor device of one embodiment of the present invention including a transistor1000and a transistor2000is described below.

FIGS. 14A and 14Bare cross-sectional views of the semiconductor device including the transistor1000and the transistor2000, andFIG. 15is a top view of the semiconductor device.FIG. 14Ais a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2inFIG. 15, which illustrates a cross section of the transistor1000in the channel length direction.FIG. 14Bis a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4inFIG. 15, which illustrates a cross section of the transistor1000in the channel width direction. For simplification of the drawing, some components are not illustrated in the top view inFIG. 15.

Note that in the semiconductor device illustrated inFIGS. 14A and 14BandFIG. 15, components having the same functions as the components in the semiconductor device described in <Structural example 1 of semiconductor device> are denoted by the same reference numerals.

The structures of the transistors1000and2000will be described below with reference toFIGS. 14A and 14B,FIG. 15, andFIGS. 16A and 16B. Note that as materials of the transistor1000and the transistor2000in this section, the materials described in <Structural example 1 of semiconductor device> can be used.

As illustrated inFIGS. 14A and 14B, the transistor1000differs from that in the semiconductor device described in <Structural example 1 of semiconductor device> in at least the shape of the oxide406c.

In the oxide406, the oxide406a, the oxide406b, and the oxide406care stacked in this order. Side surfaces of the oxides406a,406b, and406care preferably substantially aligned with one another. The side surface of the oxide406band the side surface of the oxide406apreferably form one surface. The side surface of the oxide406cand the side surface of the oxide406bpreferably form one surface. The side surface of the oxide406cand the side surface of the oxide406apreferably form one surface. That is, it is preferable that when the substrate is perpendicularly seen from above, the position of the side surface of the oxide406cbe substantially the same as the positions of the side surfaces of the oxide406aand the oxide406b.

Therefore, the oxide406a, the oxide406b, and the oxide406ccan be formed in the same step, which improves the productivity. Furthermore, the formation of the oxides406a,406b, and406cin the same step facilitates miniaturization and high integration of the transistor1000.

As illustrated inFIG. 16A, the conductor451a(the conductor451b) is in contact with the side surfaces of the oxide406a, the side surface of the oxide406b, and the top and side surfaces of the oxide406cwhich are included in the oxide406.

Although the conductor in which the opening is formed is only the conductor451a(the conductor451b) inFIG. 16A, this embodiment is not limited to this structure. A structure in which a conductor450in contact with inner walls of the insulator415and the insulator409is formed and the conductor451a(the conductor451b) is formed inside the conductor450as illustrated inFIG. 16Bmay be employed. Thus, the conductor451a(the conductor451b) is electrically connected to the region426b(the region426c) through the conductor450.

Part of the insulator402may be removed when an opening is formed in the insulator415and the insulator409. In that case, the insulator302is preferably an insulator that serves as an etching stopper film used in forming the groove by etching the insulators415,409, and402. The insulator303serving as an etching stopper film can inhibit conduction with a wiring between the substrate and the insulator302.

As illustrated inFIGS. 14A and 14B, the transistor2000differs from that in the semiconductor device described in <Structural example 1 of semiconductor device> in at least the shape of the oxide506c.

As illustrated inFIGS. 14A and 14B, the transistor2000includes an insulator401and an insulator301over a substrate (not illustrated); a conductor510embedded in the insulator401and the insulator301; an insulator302over the insulator301and the conductor410; an insulator303over the insulator302; an insulator402over the insulator303; an oxide506a1and an oxide506a2apart from each other over the insulator402; an oxide506b1in contact with a top surface of the oxide506a1; an oxide506b2in contact with a top surface of the oxide506a2; an oxide506cin contact with top surfaces of the oxide506b1and the oxide506b2; an insulator512over the oxide506c; a conductor504aover the insulator512; a conductor504bover the conductor504a; an insulator519over the conductor504b; an insulator518in contact with side surfaces of the insulator512, the conductor504a, the conductor504b, and the insulator519; and the insulator409in contact with side surfaces of the oxides506aand506b, top and side surfaces of the oxide506c, and a side surface of the insulator518. Here, as illustrated inFIG. 14A, the top surface of the insulator518is preferably substantially aligned with a top surface of the insulator519. Furthermore, the insulator409is preferably provided to cover the insulator519, the conductor504, the insulator518, and the oxide506. It is preferable that when the substrate is perpendicularly seen from above, the position of the side surface of the insulator512is substantially the same as the positions of the side surfaces of the insulator519, the conductor504a, and the conductor504b.

The oxide506a1, the oxide506b1, the oxide506a2, and the oxide506b2preferably overlap with part of the oxide506c. The side surface of the oxide506a1and the side surface of the oxide506b1are preferably substantially aligned with each other, and the side surface of the oxide506a2and the side surface of the oxide506b2are preferably substantially aligned with each other. For example, the oxide506cis formed in contact with the side surfaces of the oxide506a1and the oxide506a2, the top and side surfaces of the oxide506b1and the oxide506b2, and part of the top surface of the insulator402. That is, as illustrated inFIG. 15, the stacked structure of the oxide506a1and the oxide506b1and the stacked structure of the oxide506a2and the oxide506b2are preferably disposed in a region that is the projected area of the oxide506c.

The oxides506a1and506b1and the oxides506a2and506b2are oppositely disposed with the conductor510, the oxide506c, the insulator512, and the conductor504sandwiched therebetween.

The oxide506includes a region in contact with the insulator409. The resistance of the region and its vicinity is lowered in a manner similar to that of the region426band the region426cin the transistor1000. Accordingly, the oxide506a1, the oxide506b1, and part of the oxide506ccan function as one of a source region and a drain region of the transistor2000, and the oxide506a2, the oxide506b2, and other part of the oxide506ccan function as the other of the source region and the drain region of the transistor2000.

Next, a method of manufacturing the transistor1000and the transistor2000in parallel which are included in the semiconductor device of one embodiment of the present invention is described with reference toFIGS. 17A to 17DtoFIG. 23.FIGS. 17A and 17CandFIGS. 18A and 18Care cross-sectional views taken along the dashed-dotted line A1-A2inFIG. 15.FIGS. 17B and 17DandFIGS. 18B and 18Dare cross-sectional views taken along the dashed-dotted line A3-A4inFIG. 15.

First, the structure illustrated inFIGS. 17A and 17Bis formed by a manufacturing method similar to the manufacturing method described in <Method 1 of manufacturing semiconductor device>.

Next, the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2and the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2are formed. Note that the oxide films can be formed in a manner similar to that in the manufacturing method described in <Method 1 of manufacturing semiconductor device>.

Then, an opening505is formed by removing part of the oxide film to expose part of the insulator402, whereby an oxide406A and an oxide406B are formed (seeFIGS. 17C and 17D). Note that a lithography method may be employed for the processing of the oxide films. Alternatively, a dry etching method or a wet etching method may be used for the processing. A dry etching method is suitable for minute processing.

Note that after the processing of the oxide films, the opening505may have a tapered cross section. The taper angle to a plane parallel to the bottom surface of the substrate is, for example, greater than or equal to 30° and less than 75°, preferably greater than or equal to 30° and less than 70°. Owing to such a taper angle, the coverage with films formed later in the manufacturing process can be improved. A dry etching method is suitable the processing into a tapered shape.

In some cases, treatment such as dry etching performed in the above process causes the attachment or diffusion of impurities due to an etching gas or the like to a surface or an inside of the oxide406A, the oxide406B, or the like. Examples of the impurities include fluorine and chlorine. To remove the impurities or the like, cleaning may be performed.

The oxide406A and the oxide406B may be subjected to heat treatment. For the heat treatment, the conditions for the first heat treatment can be used.

Next, the oxide film406C is formed over the insulator402exposed in the opening505, the oxide406A, and the oxide406B (seeFIGS. 18A and 18B). The oxide film406C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The oxide film406C is an oxide film to be the oxide406cand the oxide506c. Therefore, in accordance with characteristics required for the oxide406cand the oxide506c, the oxide film406C is formed by a method similar to the method of forming the oxide film to be the oxide406a, the oxide506a1, and the oxide506a2or the method of forming the oxide film to be the oxide406b, the oxide506b1, and the oxide506b2. In this embodiment, the oxide film406C is formed by a sputtering method using a target with an atomic ratio of In:Ga:Zn=4:2:4.1.

Next, the oxide406A, the oxide406B, and the oxide film406C are processed into island shapes to form the oxide406a, the oxide506a1, the oxide506a2, the oxide406b, the oxide506b1, the oxide506b2, the oxide406c, and the oxide506c(seeFIGS. 18C and 18D). Here, at least part of the oxide406a, part of the oxide406b, and part of the oxide406coverlap with the conductor410. At least part of the conductor510overlaps with a region between the oxides506a1and506b1and the oxides506a2and506b2. Note that a lithography method may be employed for the processing of the oxide406A, the oxide406B, and the oxide film406C. Alternatively, a dry etching method or a wet etching method may be used for the processing. A dry etching method is suitable for minute processing. In the lithography method, a hard mask may be used instead of a resist mask.

Note that the side surface of the oxide406band the side surface of the oxide406apreferably form one surface. The side surface of the oxide406band the side surface of the oxide406cpreferably form one surface. The side surface of the oxide406cand the side surface of the oxide406apreferably form one surface. The side surface of the oxide506b1and the side surface of the oxide506a1preferably form one surface. One side surface of the oxide506cand the side surface of the oxide506a1preferably form one surface. The one side surface of the oxide506cand the side surface of the oxide506b1preferably form one surface. The side surface of the oxide506b2and the side surface of the oxide506a2preferably form one surface. The other side surface of the oxide506cand the side surface of the oxide506a2preferably form one surface. The other side surface of the oxide506cand the side surface of the oxide506b2preferably form one surface.

The oxide406A, the oxide406B, and the oxide film406C are collectively processed, so that the side surfaces of the oxide406a, the oxide406b, and the oxide406care substantially aligned with one another. The side surfaces of the oxide506a1and the oxide506b1are substantially aligned with each other, and the side surfaces of the oxide506a2and the oxide506b2are substantially aligned with each other. In addition, the oxide506a1, the oxide506b1, the oxide506a2, and the oxide506b2overlap with part of the oxide506c. That is, as illustrated inFIG. 15, the stacked structure of the oxide506a1and the oxide506b1and the stacked structure of the oxide506a2and the oxide506b2are formed in a region that is the projected area of the oxide506c.

The following steps can be formed in a manner similar to that in the manufacturing method described in <Method 1 of manufacturing semiconductor device>.

The structures, the methods, and the like described in this embodiment can be used in appropriate combination with any of the structures, the methods, and the like described in the other embodiments.

In this embodiment, one embodiment of a semiconductor device will be described with reference toFIG. 19toFIG. 22.

Semiconductor devices illustrated inFIG. 19andFIG. 20each include a transistor300, a transistor200, a transistor345, and a capacitor100.

The transistor200is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor, and can be the transistor described in Embodiment 1. Since the transistor described in Embodiment 1 can be formed with high yield even when it is miniaturized, the transistor200can be miniaturized. The use of such a transistor in a memory device allows miniaturization or high integration of the memory device. Since the off-state current of the transistor described in Embodiment 1 is low, a memory device including the transistor can retain stored data for a long time. In other words, such a memory device does not require refresh operation or has an extremely low frequency of the refresh operation, which leads to a sufficient reduction in power consumption of the memory device.

In each ofFIG. 19andFIG. 20, a wiring3001is electrically connected to a source of the transistor300. A wiring3002is electrically connected to a drain of the transistor300. A wiring3003is electrically connected to one of a source and a drain of the transistor200. A wiring3004is electrically connected to a first gate of the transistor200. A wiring3006is electrically connected to a second gate of the transistor200. A gate of the transistor300and the other of the source and the drain of the transistor200are electrically connected to one electrode of the capacitor100. A wiring3005is electrically connected to the other electrode of the capacitor100.

In each ofFIG. 19andFIG. 20, the wiring3001is electrically connected to the source of the transistor300. The wiring3002is electrically connected to the drain of the transistor300. The wiring3003is electrically connected to one of the source and the drain of the transistor200. The wiring3004is electrically connected to a gate of the transistor200. The wiring3006is electrically connected to a back gate of the transistor200. The gate of the transistor300and the other of the source and the drain of the transistor200are electrically connected to one electrode of the capacitor100. The wiring3005is electrically connected to the other electrode of the capacitor100. A wiring3007is electrically connected to a source of the transistor345, a wiring3008is electrically connected to a gate of the transistor345, a wiring3009is electrically connected to a back gate of the transistor345, and a wiring3010is electrically connected to a drain of the transistor345. The wiring3006, the wiring3007, the wiring3008, and the wiring3009are electrically connected to one another.

The transistor1000, the transistor2000, and the capacitor1500inFIGS. 13A and 13Bdescribed in the above embodiment correspond to the transistor200, the transistor345, and the capacitor100, respectively. The wiring1605, the wiring1606, the wiring1607, and the wiring1608inFIGS. 13A and 13Bcorrespond to the wiring3006, the wiring3007, the wiring3008, and the wiring3009, respectively.

The semiconductor devices illustrated inFIG. 19andFIG. 20each have a feature that the potential of the gate of the transistor300can be retained and thus enable writing, retaining, and reading of data as follows.

By arranging the memory devices illustrated inFIG. 19andFIG. 20in a matrix, a memory cell array can be formed. Note that one transistor345can control back-gate voltages of the plurality of transistors200. For this reason, the number of transistors345can be smaller than the number of transistors200.

Writing and retaining of data are described. First, the potential of the wiring3004is set to a potential at which the transistor200is turned on, so that the transistor200is turned on. Accordingly, the potential of the wiring3003is supplied to a node FG where the gate of the transistor300and the one electrode of the capacitor100are electrically connected to each other. That is, a predetermined charge is supplied to the gate of the transistor300(writing). Here, one of two kinds of charges providing different potential levels (hereinafter referred to as a low-level charge and a high-level charge) is supplied. After that, the potential of the wiring3004is set to a potential at which the transistor200is turned off, so that the transistor200is turned off. Thus, the charge is retained in the node FG (retaining).

In the case where the off-state current of the transistor200is low, the charge of the node FG is retained for a long time.

Next, reading of data is described. An appropriate potential (reading potential) is supplied to the wiring3005while a predetermined potential (constant potential) is supplied to the wiring3001, whereby the potential of the wiring3002varies depending on the amount of charge retained in the node FG. This is because in the case of using an n-channel transistor as the transistor300, an apparent threshold voltage Vth_Hat the time when a high-level charge is given to the gate of the transistor300is lower than an apparent threshold voltage Vth_Lat the time when a low-level charge is given to the gate of the transistor300. Here, an apparent threshold voltage refers to the potential of the wiring3005which is needed to turn on the transistor300. Thus, the potential of the wiring3005is set to a potential V0which is between Vth_Hand Vth_L, whereby the charge supplied to the node FG can be determined. For example, in the case where a high-level charge is supplied to the node FG in writing and the potential of the wiring3005is V0(>Vth_H), the transistor300is turned on. Meanwhile, in the case where a low-level charge is supplied to the node FG in writing, even when the potential of the wiring3005is V0(<Vth_L), the transistor300remains off. Thus, the data retained in the node FG can be read by determining the potential of the wiring3002.

<Structure of Semiconductor Device 1>

The semiconductor device of one embodiment of the present invention includes the transistor300, the transistor200, a transistor345, and the capacitor100as illustrated inFIG. 19andFIG. 20. The transistor200and the transistor345are provided above the transistor300, and the capacitor100is provided above the transistor300, the transistor200, and the transistor345.

The transistor300is provided over a substrate311and includes a conductor316, an insulator315, a semiconductor region313that is a part of the substrate311, and low-resistance regions314aand314bfunctioning as a source region and a drain region.

The transistor300may be a p-channel transistor or an n-channel transistor.

It is preferable that a region of the semiconductor region313where a channel is formed, a region in the vicinity thereof, the low-resistance regions314aand314bfunctioning as a source region and a drain region, and the like contain a semiconductor such as a silicon-based semiconductor, further preferably single crystal silicon. Alternatively, a material including germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium aluminum arsenide (GaAlAs), or the like may be contained. Silicon whose effective mass is controlled by applying stress to the crystal lattice and thereby changing the lattice spacing may be contained. Alternatively, the transistor300may be a high-electron-mobility transistor (HEMT) with GaAs and GaAlAs, or the like.

The low-resistance regions314aand314bcontain an element which imparts n-type conductivity, such as arsenic or phosphorus, or an element which imparts p-type conductivity, such as boron, in addition to a semiconductor material used for the semiconductor region313.

The conductor316functioning as a gate electrode can be formed using a semiconductor material such as silicon containing the element which imparts n-type conductivity, such as arsenic or phosphorus, or the element which imparts p-type conductivity, such as boron, or a conductive material such as a metal material, an alloy material, or a metal oxide material.

Note that a work function of a conductor is determined by a material of the conductor, whereby the threshold voltage can be adjusted. Specifically, it is preferable to use titanium nitride, tantalum nitride, or the like as the conductor. Furthermore, in order to ensure the conductivity and embeddability of the conductor, it is preferable to use a stacked layer of metal materials such as tungsten and aluminum as the conductor. In particular, tungsten is preferable in terms of heat resistance.

Note that the transistor300illustrated inFIG. 19andFIG. 20is only an example and is not limited to the structure illustrated therein; an appropriate transistor may be used in accordance with a circuit configuration or a driving method.

An insulator320, an insulator322, an insulator324, and an insulator326are stacked sequentially so as to cover the transistor300.

The insulator320, the insulator322, the insulator324, and the insulator326can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

The insulator322may function as a planarization film for eliminating a level difference caused by the transistor300or the like underlying the insulator322. For example, the top surface of the insulator322may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to increase the level of planarity.

The insulator324is preferably formed using a film having a barrier property that prevents impurities and hydrogen from diffusing from the substrate311, the transistor300, or the like into a region where the transistor200is formed.

As an example of the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be given. The diffusion of hydrogen to a semiconductor element including an oxide semiconductor, such as the transistor200, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that prevents hydrogen diffusion is preferably provided between the transistor300and the transistor200and between the transistor300and the transistor345. Specifically, the film that prevents hydrogen diffusion is a film from which hydrogen is less likely to be released.

The amount of released hydrogen can be measured by thermal desorption spectroscopy (TDS), for example. The amount of hydrogen released from the insulator324that is converted into hydrogen atoms per unit area of the insulator324is less than or equal to 10×1015atoms/cm2, preferably less than or equal to 5×1015atoms/cm2in the TDS analysis in the range of 50° C. to 500° C., for example.

Note that the permittivity of the insulator326is preferably lower than that of the insulator324. For example, the relative permittivity of the insulator326is preferably lower than 4, further preferably lower than 3. For example, the relative permittivity of the insulator326is preferably 0.7 times or less that of the insulator324, further preferably 0.6 times or less that of the insulator324. In the case where a material with a low permittivity is used as an interlayer film, the parasitic capacitance between wirings can be reduced.

A conductor328, a conductor330, and the like that are electrically connected to the capacitor100or the transistor200are provided in the insulator320, the insulator322, the insulator324, and the insulator326. Note that the conductor328and the conductor330each function as a plug or a wiring. A plurality of structures of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where part of a conductor functions as a wiring and part of a conductor functions as a plug.

As a material of each of plugs and wirings (e.g., the conductor328and the conductor330), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single-layer structure or a stacked-layer structure. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

A wiring layer may be provided over the insulator326and the conductor330. For example, inFIG. 19andFIG. 20, an insulator350, an insulator352, and an insulator354are stacked sequentially. Furthermore, a conductor356is formed in the insulator350, the insulator352, and the insulator354. The conductor356functions as a plug or a wiring. Note that the conductor356can be formed using a material similar to those used for forming the conductor328and the conductor330.

Note that for example, the insulator350is preferably formed using an insulator having a barrier property against hydrogen, like the insulator324. Furthermore, the conductor356preferably includes a conductor having a barrier property against hydrogen. The conductor having a barrier property against hydrogen is formed particularly in an opening of the insulator350having a barrier property against hydrogen. In such a structure, the transistor300, the transistor200, and the transistor345can be separated by a barrier layer, so that the diffusion of hydrogen from the transistor300to the transistor200and the transistor345can be prevented.

Note that as the conductor having a barrier property against hydrogen, tantalum nitride may be used, for example. By stacking tantalum nitride and tungsten, which has high conductivity, the diffusion of hydrogen from the transistor300can be prevented while the conductivity of a wiring is ensured. In this case, a tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator350having a barrier property against hydrogen.

A wiring layer may be provided over the insulator354and the conductor356. For example, inFIG. 19andFIG. 20, an insulator210, an insulator212, an insulator214, and an insulator216are stacked in this order over the insulator354. A material having a barrier property against oxygen and hydrogen is preferably used for any of the insulator210, the insulator212, the insulator214, and the insulator216.

The insulators210and214are preferably formed using, for example, a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate311, a region where the transistor300is formed, or the like to a region where the transistor200or the transistor345is formed. Therefore, the insulators210and214can be formed using a material similar to that used for forming the insulator324.

As an example of the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be given. The diffusion of hydrogen to a semiconductor element including an oxide semiconductor, such as the transistor200, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that prevents hydrogen diffusion is preferably provided between the transistor300and the transistor200and between the transistor300and the transistor345. Specifically, the film that prevents hydrogen diffusion is a film from which hydrogen is less likely to be released.

As the film having a barrier property against hydrogen, for example, as each of the insulators210and214, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used.

In particular, aluminum oxide has an excellent blocking effect that prevents permeation of oxygen and impurities such as water or hydrogen and moisture which cause a change in electrical characteristics of the transistor. Accordingly, the use of aluminum oxide can prevent entry of impurities such as water or hydrogen and moisture into the transistor200and the transistor345in and after a manufacturing process of the transistor. In addition, release of oxygen from the oxide in the transistor200and the transistor345can be prevented. Therefore, aluminum oxide is suitably used as a protective film for the transistor200and the transistor345.

For example, the insulators212and216can be formed using a material similar to that used for forming the insulator320. In the case where interlayer films formed of a material with a relatively low permittivity are used for the insulators, the parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used for the insulators212and216.

A conductor218, a conductor included in the transistor200, a conductor included in the transistor345, and the like are provided in the insulators210,212,214, and216. Note that the conductor218functions as a plug or a wiring that is electrically connected to the capacitor100or the transistor300. The conductor218can be formed using a material similar to those used for forming the conductors328and330.

In particular, part of the conductor218which is in contact with the insulators210and214is preferably a conductor with a barrier property against oxygen, hydrogen, and water. In such a structure, the transistor300and the transistors200and345can be completely separated by the layer with a barrier property against oxygen, hydrogen, and water. As a result, the diffusion of hydrogen from the transistor300to the transistor200and the transistor345can be prevented.

The transistor200and the transistor345are provided over the insulator216. Note that the transistor included in the semiconductor device described in the above embodiment may be used as the transistor200and the transistor345. For example, the transistor1000can be used as the transistor200, and the transistor2000can be used as the transistor345.FIG. 19andFIG. 20illustrate an example in which the transistor1000is used as the transistor200and the transistor2000is used as the transistor345. Note that the transistor200and the transistor345inFIG. 19andFIG. 20are only examples and are not limited to the structures illustrated therein, and an appropriate transistor may be used in accordance with a circuit configuration or a driving method.

An insulator230and an insulator232are stacked in this order over the insulator216and the conductor218. A material having a barrier property against oxygen or hydrogen is preferably used for at least one of the insulator230and the insulator232.

The insulators230and232are preferably formed using, for example, a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate311, a region where the transistor300is formed, or the like to a region where the transistor200or the transistor345is formed. Therefore, the insulators230and232can be formed using a material similar to that used for forming the insulator324.

As an example of the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be given. The diffusion of hydrogen to a semiconductor element including an oxide semiconductor, such as the transistor200, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that prevents hydrogen diffusion is preferably provided between the transistor300and the transistor200and between the transistor300and the transistor345. Specifically, the film that prevents hydrogen diffusion is a film from which hydrogen is less likely to be released.

A conductor219is embedded in the insulator230and the insulator232. Note that the conductor219serves as a plug that is electrically connected to a back gate electrode of the transistor200and a back gate electrode of the transistor345, a plug that is electrically connected to the capacitor100or the transistor300, or a wiring. The conductor219can be formed with a material similar to that of the conductor328and the conductor330.

The insulator230and the insulator232are provided between the back gate electrodes of the transistor200and the transistor345and the top gate electrodes of the transistor200and the transistor345, whereby parasitic capacitance between the back gate electrode and the top gate electrode of the transistor200and parasitic capacitance between the back gate electrode and the top gate electrode of the transistor345can be reduced.

The insulator280is provided over the transistor200and the transistor345. In the insulator280, an excess-oxygen region is preferably formed. In particular, in the case of using an oxide semiconductor in the transistor200and the transistor345, when an insulator including an excess-oxygen region is provided in an interlayer film or the like in the vicinity of the transistor200and the transistor345, oxygen vacancies in the oxide included in the transistor200and the transistor345are reduced, whereby the reliability can be improved. The insulator280that covers the transistor200and the transistor345may function as a planarization film that covers a roughness thereunder.

As the insulator including the excess-oxygen region, specifically, an oxide that releases part of oxygen by heating is preferably used. The oxide that releases part of oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018atoms/cm3, preferably greater than or equal to 3.0×1020atoms/cm3in TDS analysis. Note that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 500° C.

For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, “silicon oxynitride” refers to a material that contains oxygen at a higher proportion than nitrogen, and “silicon nitride oxide” refers to a material that contains nitrogen at a higher proportion than oxygen.

The insulator282is provided over the insulator280. A material having a barrier property against oxygen or hydrogen is preferably used for the insulator282. Thus, the insulator282can be formed using a material similar to that used for forming the insulator214. As the insulator282, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used, for example.

In particular, aluminum oxide has an excellent blocking effect that prevents permeation of oxygen and impurities such as water and hydrogen which cause a change in electrical characteristics of the transistor. Accordingly, the use of aluminum oxide can prevent entry of impurities such as water and hydrogen into the transistor200and the transistor345in and after a manufacturing process of the transistor. In addition, release of oxygen from the oxide in the transistor200and the transistor345can be prevented. Therefore, aluminum oxide is suitably used as a protective film for the transistor200and the transistor345.

Note that in the case where the transistor1000is provided as the transistor200and the transistor2000is provided as the transistor345, the insulator214corresponds to the insulator432, the conductor218corresponds to the conductor440, the insulator216corresponds to the insulator430, the insulator230corresponds to the insulator401, the insulator232corresponds to the insulator301, an insulator220corresponds to the insulator302, an insulator222corresponds to the insulator303, an insulator224corresponds to the insulator402, an insulator225corresponds to the insulator409, and the insulator280corresponds to the insulator415. Therefore, description of the corresponding structures described in the above embodiment can be referred to.

The insulator286is provided over the insulator282. The insulator286can be formed using a material similar to that of the insulator320. In the case where a material with a relatively low permittivity is used for an interlayer film, the parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used for the insulator286.

The conductors246, the conductors248, and the like are provided in the insulators220,222,224,280,282, and286.

The conductors246and248function as plugs or wirings that are electrically connected to the capacitor100, the transistor200, the transistor345, or the transistor300. The conductors246and248can be formed using a material similar to those used for forming the conductors328and330.

The capacitor100is provided above the transistor200and the transistor345. The capacitor100includes a conductor110, a conductor120, and an insulator130.

A conductor112may be provided over the conductors246and248. Note that the conductor112functions as a plug or a wiring that is electrically connected to the capacitor100, the transistor200, the transistor345, or the transistor300. The conductor110functions as the one electrode of the capacitor100. The conductor112and the conductor110can be formed at the same time.

The conductor112and the conductor110can be formed using a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium; a metal nitride film containing any of the above elements as its component (e.g., a tantalum nitride film, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film); or the like. Alternatively, it is possible to use a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.

The conductor112and the conductor110each have a single-layer structure inFIG. 19andFIG. 20; however, one embodiment of the present invention is not limited thereto, and a stacked-layer structure of two or more layers may be used. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor which is highly adhesive to the conductor having a barrier property and the conductor having high conductivity may be formed.

As a dielectric of the capacitor100, the insulator130is provided over the conductors112and110. The insulator130can be formed to have a single-layer structure or a stacked-layer structure using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like.

For example, a material with high dielectric strength, such as silicon oxynitride, is preferably used for the insulator130. In the capacitor100having the structure, the dielectric strength can be increased and the electrostatic breakdown of the capacitor100can be prevented because of the insulator130.

Over the insulator130, the conductor120is provided so as to overlap with the conductor110. Note that the conductor120can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material which has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. In the case where the conductor120is formed concurrently with another component such as a conductor, Cu (copper), A1(aluminum), or the like which is a low-resistance metal material may be used.

An insulator150is provided over the conductor120and the insulator130. The insulator150can be formed using a material similar to that used for forming the insulator320. The insulator150may function as a planarization film that covers a roughness thereunder.

Description is made on a dicing line (also referred to as a scribe line, a dividing line, or a cutting line) that is provided when a large-sized substrate is divided into semiconductor elements so that a plurality of semiconductor devices are each formed in a chip form. In an example of a dividing method, for example, a groove (dicing line) for separating the semiconductor elements is formed on the substrate, and then the substrate is cut along the dicing line so that a plurality of semiconductor devices that are separated are obtained. For example,FIG. 19andFIG. 20are cross-sectional views of a structure500around the dicing line.

As in the structure500, for example, openings are provided in the insulators280,225,224,222,220,232,230, and216around a region overlapping with the dicing line formed in an end portion of the memory cell including the transistor200or the transistor345. Furthermore, the insulator282is provided to cover the side surfaces of the insulator280, the insulator225, the insulator224, the insulator222, the insulator220, the insulator232, the insulator230, and the insulator216.

Thus, in the openings, the insulator214is in contact with the insulator282. At that time, the insulator214is formed using the same material and method as those used for forming the insulator282, whereby the adhesion therebetween can be improved. Aluminum oxide can be used, for example.

With such a structure, the insulator280, the transistor200, and the transistor345can be enclosed with the insulator214and the insulator282. Since the insulators210,222, and282have functions of preventing the diffusion of oxygen, hydrogen, and water, even when the substrate is divided into circuit regions each of which is provided with the semiconductor elements in this embodiment to form a plurality of chips, the entry and diffusion of impurities such as water or hydrogen from the direction of a side surface of the divided substrate to the transistor200or the transistor345can be prevented.

Furthermore, in the structure, excess oxygen in the insulator280can be prevented from diffusing to the outside of the insulators282and222. Accordingly, excess oxygen in the insulator280is efficiently supplied to the oxide where the channel is formed in the transistor200or the transistor345. The oxygen can reduce oxygen vacancies in the oxide where the channel is formed in the transistor200or the transistor345. Thus, the oxide where the channel is formed in the transistor200or the transistor345can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, a change in electrical characteristics of the transistor200or the transistor345can be prevented and the reliability can be improved.

The above is the description of the structural example. With the use of the structure, a change in electrical characteristics can be prevented and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. The power consumption of a semiconductor device including a transistor including an oxide semiconductor can be reduced. Miniaturization or high integration of a semiconductor device including a transistor including an oxide semiconductor can be achieved. A miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of Memory Cell Array>

Next,FIG. 21andFIG. 22illustrate an example of a memory cell array of this embodiment. When the memory devices each of which is illustrated inFIG. 19orFIG. 20are arranged as memory cells in a matrix, a memory cell array can be formed. Note that inFIG. 21andFIG. 22, the transistor345illustrated inFIG. 19andFIG. 20is omitted.FIG. 21andFIG. 22are cross-sectional views that illustrate part of a row in which the memory devices each of which is illustrated inFIG. 19andFIG. 20are arranged in a matrix.

The structure of the transistor300inFIG. 21andFIG. 22is different from that of the transistor300inFIG. 19andFIG. 20. In the transistor300illustrated inFIG. 21andFIG. 22, the semiconductor region313(part of the substrate311) in which a channel is formed has a protruding portion. Furthermore, the conductor316is provided to cover the top and side surfaces of the semiconductor region313with the insulator315positioned therebetween. Note that the conductor316may be formed using a material for adjusting the work function. The transistor300having such a structure is also referred to as a FIN transistor because the protruding portion of the semiconductor substrate is utilized. An insulator functioning as a mask for forming the protruding portion may be provided in contact with the top surface of the protruding portion. Although the case where the protruding portion is formed by processing part of the semiconductor substrate is described here, a semiconductor film having a protruding shape may be formed by processing an SOI substrate.

In the memory device illustrated inFIG. 21andFIG. 22, a memory cell600aand a memory cell600bare arranged adjacent to each other. The transistors300and200and the capacitor100are included and electrically connected to the wirings3001,3002,3003,3004,3005, and3006in each of the memory cells600aand600b. Also in the memory cells600aand600b, a node where a gate of the transistor300and one electrode of the capacitor100are electrically connected to each other is referred to as the node FG. Note that the wiring3002is shared by the memory cells600aand600badjacent to each other.

Note that in the case where memory cells are arrayed, it is necessary that data of a desired memory cell be read in read operation. For example, in the case of a NOR-type memory cell array, only data of a desired memory cell can be read by turning off the transistors300of memory cells from which data is not read. In this case, a potential at which the transistor300is turned off regardless of the charge supplied to the node FG, that is, a potential lower than Vth_H, is supplied to the wiring3005connected to the memory cells from which data is not read. Alternatively, in the case of a NAND-type memory cell array, for example, only data of a desired memory cell can be read by turning on the transistors300of memory cells from which data is not read. In this case, a potential at which the transistor300is turned on regardless of the charge supplied to the node FG, that is, a potential higher than Vth_L, is supplied to the wiring3005connected to the memory cells from which data is not read.

With the use of the structure, a change in electrical characteristics can be prevented and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. The power consumption of a semiconductor device including a transistor including an oxide semiconductor can be reduced. Miniaturization or high integration of a semiconductor device including a transistor including an oxide semiconductor can be achieved. A miniaturized or highly integrated semiconductor device can be provided with high productivity.

In this embodiment, a frame memory including a semiconductor device of one embodiment of the present invention, which can be used in a display controller IC, a source driver IC, or the like, is described.

A dynamic random access memory (DRAM) including memory cells of 1T1C (one transistor, one capacitor) type can be used as the frame memory, for example. A memory device in which OS transistors are used in memory cells (hereinafter referred to as an OS memory) can also be used. Here, a RAM including memory cells of 1T1C type is described as an example of the OS memory. Such a RAM is herein referred to as a dynamic oxide semiconductor RAM (DOSRAM).FIG. 23illustrates a configuration example of a DOSRAM.

The DOSRAM1400includes a controller1405, a row circuit1410, a column circuit1415, and a memory cell and sense amplifier array1420(hereinafter referred to as MC-SA array1420).

The row circuit1410includes a decoder1411, a word line driver circuit1412, a column selector1413, and a sense amplifier driver circuit1414. The column circuit1415includes a global sense amplifier array1416and an input/output circuit1417. The global sense amplifier array1416includes a plurality of global sense amplifiers1447. The MC-SA array1420includes a memory cell array1422, a sense amplifier array1423, and global bit lines GBLL and GBLR.

The MC-SA array1420has a stacked-layer structure where the memory cell array1422is stacked over the sense amplifier array1423. The global bit lines GBLL and GBLR are stacked over the memory cell array1422. The DOSRAM1400adopts a hierarchical bit line structure, where the bit lines are layered into local and global bit lines.

The memory cell array1422includes N local memory cell arrays1425<0> to1425<N−1>, where N is an integer greater than or equal to 2.FIG. 24Aillustrates a configuration example of the local memory cell array1425. The local memory cell array1425includes a plurality of memory cells1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR. In the example inFIG. 24A, the local memory cell array1425has an open bit-line architecture but may have a folded bit-line architecture.

FIG. 24Billustrates a circuit configuration example of the memory cell1445. The memory cell1445includes a transistor MW1, a capacitor CS1, and terminals B1and B2. The transistor MW1has a function of controlling the charging and discharging of the capacitor CS1. A gate of the transistor MW1is electrically connected to the word line, a first terminal of the transistor MW1is electrically connected to the bit line, and a second terminal of the transistor MW1is electrically connected to a first terminal of the capacitor CS1. A second terminal of the capacitor CS1is electrically connected to the terminal B2. A constant voltage (e.g., low power supply voltage) is input to the terminal B2.

The transistor MW1includes a back gate, and the back gate is electrically connected to the terminal B1. This makes it possible to change the threshold voltage of the transistor MW1with a voltage applied to the terminal B1. For example, a fixed voltage (e.g., negative constant voltage) may be applied to the terminal B1; alternatively, the voltage applied to the terminal B1may be changed in response to the operation of the DOSRAM1400.

The back gate of the transistor MW1may be electrically connected to the gate, the source, or the drain of the transistor MW1. Alternatively, the transistor MW1does not necessarily include the back gate.

The sense amplifier array1423includes N local sense amplifier arrays1426<0> to1426<N−1>. The local sense amplifier array1426includes one switch array1444and a plurality of sense amplifiers1446. A bit line pair is electrically connected to the sense amplifier1446. The sense amplifier1446has a function of precharging the bit line pair, a function of amplifying a voltage difference between the bit line pair, and a function of retaining the voltage difference. The switch array1444has a function of selecting a bit line pair and electrically connecting the selected bit line pair and a global bit line pair to each other.

Here, two bit lines that are compared simultaneously by the sense amplifier are collectively referred to as the bit line pair. Two global bit lines that are compared simultaneously by the global sense amplifier are collectively referred to as the global bit line pair. The bit line pair can be referred to as a pair of bit lines, and the global bit line pair can be referred to as a pair of global bit lines. Here, a bit line BLL and a bit line BLR form one bit line pair. A global bit line GBLL and a global bit line GBLR form one global bit line pair. In the description hereinafter, the expressions “bit line pair (BLL, BLR)” and “global bit line pair (GBLL, GBLR)” are also used.

The controller1405has a function of controlling the overall operation of the DOSRAM1400. The controller1405has a function of performing logic operation on a command signal that is input from the outside and determining an operation mode, a function of generating control signals for the row circuit1410and the column circuit1415so that the determined operation mode is executed, a function of retaining an address signal that is input from the outside, and a function of generating an internal address signal.

The row circuit1410has a function of driving the MC-SA array1420. The decoder1411has a function of decoding an address signal. The word line driver circuit1412generates a selection signal for selecting the word line WL of a row that is to be accessed.

The column selector1413and the sense amplifier driver circuit1414are circuits for driving the sense amplifier array1423. The column selector1413has a function of generating a selection signal for selecting the bit line of a column that is to be accessed. The selection signal from the column selector1413controls the switch array1444of each local sense amplifier array1426. The control signal from the sense amplifier driver circuit1414drives each of the plurality of local sense amplifier arrays1426independently.

The column circuit1415has a function of controlling the input of data signals WDA[31:0], and a function of controlling the output of data signals RDA[31:0]. The data signals WDA[31:0] are write data signals, and the data signals RDA[31:0] are read data signals.

The global sense amplifier1447is electrically connected to the global bit line pair (GBLL, GBLR). The global sense amplifier1447has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR), and a function of retaining the voltage difference. Data are written to and read from the global bit line pair (GBLL, GBLR) by the input/output circuit1417.

A write operation of the DOSRAM1400is briefly described. Data are written to the global bit line pair by the input/output circuit1417. The data of the global bit line pair are retained by the global sense amplifier array1416. By the switch array1444of the local sense amplifier array1426specified by the address signal, the data of the global bit line pair are written to the bit line pair of the column where data are to be written. The local sense amplifier array1426amplifies the written data, and then retains the amplified data. In the specified local memory cell array1425, the word line WL of the row where data are to be written is selected by the row circuit1410, and the data retained at the local sense amplifier array1426are written to the memory cell1445of the selected row.

A read operation of the DOSRAM1400is briefly described. One row of the local memory cell array1425is specified with the address signal. In the specified local memory cell array1425, the word line WL of the row where data are to be read is selected, and data of the memory cell1445are written to the bit line. The local sense amplifier array1426detects a voltage difference between the bit line pair of each column as data, and retains the data. The switch array1444writes the data of a column specified by the address signal to the global bit line pair; the data are chosen from the data retained at the local sense amplifier array1426. The global sense amplifier array1416detects and retains the data of the global bit line pair. The data retained at the global sense amplifier array1416are output to the input/output circuit1417. Thus, the read operation is completed.

The DOSRAM1400has no limitations on the number of rewrites in principle and data can be read and written with low energy consumption, because data are rewritten by charging and discharging the capacitor CS1. Simple circuit configuration of the memory cell1445allows a high memory capacity.

The transistor MW1is an OS transistor. The extremely low off-state current of the OS transistor can inhibit leakage of charge from the capacitor CS1. Therefore, the retention time of the DOSRAM1400is considerably longer than that of DRAM. This allows less frequent refresh, which can reduce power needed for refresh operations. For this reason, the DOSRAM1400used as the frame memory can reduce the power consumption of the display controller IC and the source driver IC.

Since the MC-SA array1420has a stacked-layer structure, the bit line can be shortened to a length that is close to the length of the local sense amplifier array1426. A shorter bit line results in smaller bit line capacitance, which allows the storage capacitance of the memory cell1445to be reduced. In addition, providing the switch array1444in the local sense amplifier array1426allows the number of long bit lines to be reduced. For the reasons described above, a load to be driven during access to the DOSRAM1400is reduced, enabling a reduction in the energy consumption of the display controller IC and the source driver IC.

In this embodiment, a field-programmable gate array (FPGA) is described as an example of a semiconductor device in which a transistor of one embodiment of the present invention whose semiconductor includes an oxide (OS transistor) is used. In an FPGA of this embodiment, an OS memory is used for a configuration memory and a register. Here, such an FPGA is referred to as an “OS-FPGA”.

The OS memory is a memory including at least a capacitor and an OS transistor that controls charge and discharge of the capacitor. The OS memory has excellent retention characteristics because the OS transistor has an extremely low off-state current and thus can function as a nonvolatile memory.

FIG. 25Aillustrates a configuration example of an OS-FPGA. An OS-FPGA3110illustrated inFIG. 25Ais capable of normally-off computing for context switching by a multi-context configuration and fine-grained power gating in each PLE. The OS-FPGA3110includes a controller3111, a word driver3112, a data driver3113, and a programmable area3115.

The programmable area3115includes two input/output blocks (IOBs)3117and a core3119. The IOB3117includes a plurality of programmable input/output circuits. The core3119includes a plurality of logic array blocks (LABs)3120and a plurality of switch array blocks (SABs)3130. The LAB3120includes a plurality of PLEs3121.FIG. 25Billustrates an example in which the LAB3120includes five PLEs3121. As illustrated inFIG. 25C, the SAB3130includes a plurality of switch blocks (SBs)3131arranged in array. The LAB3120is connected to the LABs3120in four directions (on the left, right, top, and bottom sides) through its input terminals and the SABs3130.

The SB3131is described with reference toFIGS. 26A to 26C. To the SB3131inFIG. 26A, data, datab, signals context[1:0], and signals word[1:0] are input. The data and the datab are configuration data, and the logics of the data and the datab are complementary to each other. The number of contexts in the OS-FPGA3110is two, and the signals context[1:0] are context selection signals. The signals word[1:0] are word line selection signals, and wirings to which the signals word[1:0] are input are each a word line.

The SB3131includes a programmable routing switch (PRS)3133[0] and a PRS3133[1]. The PRS3133[0] and the PRS3133[1] each include a configuration memory (CM) that can store complementary data. Note that in the case where the PRS3133[0] and the PRS3133[1] are not distinguished from each other, they are each referred to as a PRS3133. The same applies to other elements.

FIG. 26Billustrates a circuit configuration example of the PRS3133[0]. The PRS3133[0] and the PRS3133[1] have the same circuit configuration. The PRS3133[0] and the PRS3133[1] are different from each other in a context selection signal and a word line selection signal which are input. The signal context[0] and the signal word[0] are input to the PRS3133[0], and the signal context[1] and the signal word[1] are input to the PRS3133[1]. For example, in the SB3131, when the signal context[0] is set to “H”, the PRS3133[0] is activated.

The PRS3133[0] includes a CM3135and a Si transistor M31. The Si transistor M31is a pass transistor that is controlled by the CM3135. The CM3135includes a memory circuit3137and a memory circuit3137B. The memory circuit3137and the memory circuit3137B have the same circuit configuration. The memory circuit3137includes a capacitor C31, an OS transistor MO31, and an OS transistor MO32. The memory circuit3137B includes a capacitor CB31, an OS transistor MOB31, and an OS transistor MOB32.

The OS transistors MO31, MO32, MOB31, and MOB32each include a back gate, and these back gates are electrically connected to power supply lines that each supply a fixed voltage.

A gate of the Si transistor M31, a gate of the OS transistor MO32, and a gate of the OS transistor MOB32correspond to a node N31, a node N32, and a node NB32, respectively. The node32and the node NB32are each a charge retention node of the CM3135. The OS transistor MO32controls the conduction state between the node N31and a signal line for the signal context[0]. The OS transistor MOB32controls the conduction state between the node N31and a low-potential power supply line VSS.

A logic of data that the memory circuit3137retains and a logic of data that the memory circuit3137B retains are complementary to each other. Thus, either the OS transistor MO32or the OS transistor MOB32is turned on.

The operation example of the PRS3133[0] is described with reference toFIG. 26C. In the PRS3133[0], in which configuration data has already been written, the node N32of the PRS3133[0] is at “H”, whereas the node NB32is at “L”.

The PRS3133[0] is inactivated while the signal context[0] is at “L”. During this period, even when an input terminal of the PRS3133[0] is transferred to “H”, the gate of the Si transistor M31is kept at “L” and an output terminal of the PRS3133[0] is also kept at “L”.

The PRS3133[0] is activated while the signal context[0] is at “H”. When the signal context[0] is transferred to “H”, the gate of the Si transistor M31is transferred to “H” by the configuration data stored in the CM3135.

While the PRS3133[0] is active, when the potential of the input terminal is changed to “H”, the gate voltage of the Si transistor M31is increased by boosting because the OS transistor MO32of the memory circuit3137is a source follower. As a result, the OS transistor MO32of the memory circuit3137loses the driving capability, and the gate of the Si transistor M31is brought into a floating state.

In the PRS3133with a multi-context function, the CM3135also functions as a multiplexer.

FIG. 27illustrates a configuration example of the PLE3121. The PLE3121includes a lookup table (LUT) block3123, a register block3124, a selector3125, and a CM3126. The LUT block3123is configured to select and output data in the LUT block in accordance with inputs inA to inD. The selector3125selects an output of the LUT block3123or an output of the register block3124in accordance with the configuration data stored in the CM3126.

The PLE3121is electrically connected to a power supply line for a voltage VDD through a power switch3127. Whether the power switch3127is turned on or off is determined in accordance with configuration data stored in a CM3128. Fine-grained power gating can be performed by providing the power switch3127for each PLE3121. The PLE3121which is not used after context switching can be power gated owing to the fine-grained power gating function; thus, standby power can be effectively reduced.

The register block3124is formed by nonvolatile registers to achieve normally-off computing. The nonvolatile registers in the PLE3121are each a flip-flop provided with an OS memory (hereinafter referred to as OS-FF).

The register block3124includes an OS-FF3140[1] and an OS-FF3140[2]. A signal user_res, a signal load, and a signal store are input to the OS-FF3140[1] and the OS-FF3140[2]. A clock signal CLK1is input to the OS-FF3140[1] and a clock signal CLK2is input to the OS-FF3140[2].FIG. 28Aillustrates a configuration example of the OS-FF3140.

The OS-FF3140includes a FF3141and a shadow register3142. The FF3141includes a node CK, a node R, a node D, a node Q, and a node QB. A clock signal is input to the node CK. The signal user_res is input to the node R. The signal user_res is a reset signal. The node D is a data input node, and the node Q is a data output node. The logics of the node Q and the node QB are complementary to each other.

The shadow register3142can function as a backup circuit of the FF3141. The shadow register3142backs up data of the node Q and data of the node QB in response to the signal store and writes back the backed up data to the node Q and the node QB in response to the signal load.

The shadow register3142includes an inverter circuit3188, an inverter circuit3189, a Si transistor M37, a Si transistor MB37, a memory circuit3143, and a memory circuit3143B. The memory circuit3143and the memory circuit3143B each have the same circuit configuration as the memory circuit3137of the PRS3133. The memory circuit3143includes a capacitor C36, an OS transistor MO35, and an OS transistor MO36. The memory circuit3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36. A node N36and a node NB36correspond to a gate of the OS transistor MO36and a gate of the OS transistor MOB36, respectively, and are each a charge retention node. A node N37and a node NB37correspond to a gate of the Si transistor M37and a gate of the Si transistor MB37, respectively.

The OS transistors MO35, MO36, MOB35, and MOB36each include a back gate, and these back gates are electrically connected to power supply lines that each supply a fixed voltage.

An example of an operation method of the OS-FF3140will be described with reference toFIG. 28B.

When the signal store at “H” is input to the OS-FF3140, the shadow register3142backs up data of the FF3141. The node N36becomes “L” when the data of the node Q is written thereto, and the node NB36becomes “H” when the data of the node QB is written thereto. After that, power gating is performed and the power switch3127is turned off. Although the data of the node Q and the data of the node QB of the FF3141are lost, the shadow register3142retains the backed up data even when power supply is stopped.

The power switch3127is turned on to supply power to the PLE3121. After that, when the signal load at “H” is input to the OS-FF3140, the shadow register3142writes back the backed up data to the FF3141. The node N37is kept at “L” because the node N36is at “L”, and the node NB37becomes “H” because the node NB36is at “H”. Thus, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF3140is restored to a state at the backup operation.

A combination of the fine-grained power gating and backup/recovery operation of the OS-FF3140allows power consumption of the OS-FPGA3110to be effectively reduced.

A possible error in a memory circuit is a soft error due to the entry of radiation. The soft error is a phenomenon in which a malfunction such as inversion of data stored in a memory is caused by electron-hole pair generation when a transistor is irradiated with a rays emitted from a material of a memory or a package or the like, secondary cosmic ray neutrons generated by nuclear reaction of primary cosmic rays entering the Earth's atmosphere from outer space with nuclei of atoms existing in the atmosphere, or the like. An OS memory including an OS transistor has a high soft-error tolerance. Therefore, the OS-FPGA3110including an OS memory can have high reliability.

In this embodiment, an example of a CPU including the semiconductor device of one embodiment of the present invention, such as the above-described memory device, is described.

A semiconductor device5400shown inFIG. 29includes a CPU core5401, a power management unit5421, and a peripheral circuit5422. The power management unit5421includes a power controller5402and a power switch5403. The peripheral circuit5422includes a cache5404including cache memory, a bus interface (BUS I/F)5405, and a debug interface (Debug I/F)5406. The CPU core5401includes a data bus5423, a control unit5407, a PC (program counter)5408, a pipeline register5409, a pipeline register5410, an ALU (arithmetic logic unit)5411, and a register file5412. Data is transmitted between the CPU core5401and the peripheral circuit5422such as the cache5404via the data bus5423.

The semiconductor device (cell) can be used for many logic circuits typified by the power controller5402and the control unit5407, particularly for all logic circuits that can be constituted using standard cells. Accordingly, the semiconductor device5400can be small. The semiconductor device5400can have reduced power consumption. The semiconductor device5400can have a higher operating speed. The semiconductor device5400can have a smaller power supply voltage variation.

When p-channel Si transistors and the transistor described in the above embodiment which includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region are used in the semiconductor device (cell) and the semiconductor device (cell) is used in the semiconductor device5400, the semiconductor device5400can be small. The semiconductor device5400can have reduced power consumption. The semiconductor device5400can have a higher operating speed. Particularly when the Si transistors are only p-channel ones, the manufacturing cost can be reduced.

The control unit5407has functions of decoding and executing instructions contained in a program such as inputted applications by controlling the overall operations of the PC5408, the pipeline registers5409and5410, the ALU5411, the register file5412, the cache5404, the bus interface5405, the debug interface5406, and the power controller5402.

The ALU5411has a function of performing a variety of arithmetic operations such as four arithmetic operations and logic operations.

The cache5404has a function of temporarily storing frequently used data. The PC5408is a register having a function of storing an address of an instruction to be executed next. Note that although not shown inFIG. 29, the cache5404is provided with a cache controller for controlling the operation of the cache memory.

The pipeline register5409has a function of temporarily storing instruction data.

The register file5412includes a plurality of registers including a general purpose register and can store data that is read from the main memory, data obtained as a result of arithmetic operations in the ALU5411, or the like.

The pipeline register5410has a function of temporarily storing data used for arithmetic operations of the ALU5411, data obtained as a result of arithmetic operations of the ALU5411, or the like.

The bus interface5405has a function of a path for data between the semiconductor device5400and various devices outside the semiconductor device5400. The debug interface5406has a function of a path of a signal for inputting an instruction to control debugging to the semiconductor device5400.

The power switch5403has a function of controlling supply of a power supply voltage to various circuits included in the semiconductor device5400other than the power controller5402. The above various circuits belong to several different power domains. The power switch5403controls whether the power supply voltage is supplied to the various circuits in the same power domain. In addition, the power controller5402has a function of controlling the operation of the power switch5403.

The semiconductor device5400having the above structure is capable of performing power gating. A description will be given of an example of the power gating operation sequence.

First, by the CPU core5401, timing for stopping the supply of the power supply voltage is set in a register of the power controller5402. Then, an instruction of starting power gating is sent from the CPU core5401to the power controller5402. Then, various registers and the cache5404included in the semiconductor device5400start data saving. Then, the power switch5403stops the supply of a power supply voltage to the various circuits other than the power controller5402included in the semiconductor device5400. Then, an interrupt signal is input to the power controller5402, whereby the supply of the power supply voltage to the various circuits included in the semiconductor device5400is started. Note that a counter may be provided in the power controller5402to be used to determine the timing of starting the supply of the power supply voltage regardless of input of an interrupt signal. Next, the various registers and the cache5404start data restoration. Then, execution of an instruction is resumed in the control unit5407.

Such power gating can be performed in the whole processor or one or a plurality of logic circuits included in the processor. Furthermore, power supply can be stopped even for a short time. Consequently, power consumption can be reduced at a fine spatial or temporal granularity.

In performing power gating, data held by the CPU core5401or the peripheral circuit5422is preferably saved in a short time. In that case, the power can be turned on or off in a short time, and an effect of saving power becomes significant.

In order that the data held by the CPU core5401or the peripheral circuit5422be saved in a short time, the data is preferably saved in a flip-flop circuit itself (referred to as a flip-flop circuit capable of backup operation). Furthermore, the data is preferably saved in an SRAM cell itself (referred to as an SRAM cell capable of backup operation). The flip-flop circuit and SRAM cell which are capable of backup operation preferably include transistors including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region. Consequently, the transistor has a low off-state current; thus, the flip-flop circuit and SRAM cell which are capable of backup operation can retain data for a long time without power supply. When the transistor has a high switching speed, the flip-flop circuit and SRAM cell which are capable of backup operation can save and restore data in a short time in some cases.

An example of the flip-flop circuit capable of backup operation is described with reference toFIG. 30.

A semiconductor device5500shown inFIG. 30is an example of the flip-flop circuit capable of backup operation. The semiconductor device5500includes a first memory circuit5501, a second memory circuit5502, a third memory circuit5503, and a read circuit5504. As a power supply voltage, a potential difference between a potential V1and a potential V2is supplied to the semiconductor device5500. One of the potential V1and the potential V2is at a high level, and the other is at a low level. An example of the structure of the semiconductor device5500when the potential V1is at a low level and the potential V2is at a high level will be described below.

The first memory circuit5501has a function of retaining data when a signal D including the data is input in a period during which the power supply voltage is supplied to the semiconductor device5500. Furthermore, the first memory circuit5501outputs a signal Q including the retained data in the period during which the power supply voltage is supplied to the semiconductor device5500. On the other hand, the first memory circuit5501cannot retain data in a period during which the power supply voltage is not supplied to the semiconductor device5500. That is, the first memory circuit5501can be referred to as a volatile memory circuit.

The second memory circuit5502has a function of reading the data held in the first memory circuit5501to store (or save) it. The third memory circuit5503has a function of reading the data held in the second memory circuit5502to store (or save) it. The read circuit5504has a function of reading the data held in the second memory circuit5502or the third memory circuit5503to store (or restore) it in the first memory circuit5501.

In particular, the third memory circuit5503has a function of reading the data held in the second memory circuit5502to store (or save) it even in the period during which the power supply voltage is not supplied to the semiconductor device5500.

As shown inFIG. 30, the second memory circuit5502includes a transistor5512and a capacitor5519. The third memory circuit5503includes a transistor5513, a transistor5515, and a capacitor5520. The read circuit5504includes a transistor5510, a transistor5518, a transistor5509, and a transistor5517.

The transistor5512has a function of charging and discharging the capacitor5519in accordance with data held in the first memory circuit5501. The transistor5512is desirably capable of charging and discharging the capacitor5519at a high speed in accordance with data held in the first memory circuit5501. Specifically, the transistor5512desirably contains crystalline silicon (preferably polycrystalline silicon, further preferably single crystal silicon) in a channel formation region.

The conduction state or the non-conduction state of the transistor5513is determined in accordance with the charge held in the capacitor5519. The transistor5515has a function of charging and discharging the capacitor5520in accordance with the potential of a wiring5544when the transistor5513is in a conduction state. It is desirable that the off-state current of the transistor5515be extremely low. Specifically, the transistor5515desirably contains an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region.

Specific connection relations between the elements will be described. One of a source and a drain of the transistor5512is connected to the first memory circuit5501. The other of the source and the drain of the transistor5512is connected to one electrode of the capacitor5519, a gate of the transistor5513, and a gate of the transistor5518. The other electrode of the capacitor5519is connected to a wiring5542. One of a source and a drain of the transistor5513is connected to the wiring5544. The other of the source and the drain of the transistor5513is connected to one of a source and a drain of the transistor5515. The other of the source and the drain of the transistor5515is connected to one electrode of the capacitor5520and a gate of the transistor5510. The other electrode of the capacitor5520is connected to a wiring5543. One of a source and a drain of the transistor5510is connected to a wiring5541. The other of the source and the drain of the transistor5510is connected to one of a source and a drain of the transistor5518. The other of the source and the drain of the transistor5518is connected to one of a source and a drain of the transistor5509. The other of the source and the drain of the transistor5509is connected to one of a source and a drain of the transistor5517and the first memory circuit5501. The other of the source and the drain of the transistor5517is connected to a wiring5540. Although a gate of the transistor5509is connected to a gate of the transistor5517inFIG. 30, it is not necessarily connected to the gate of the transistor5517.

The transistor described in the above embodiment as an example can be applied to the transistor5515. Because of the low off-state current of the transistor5515, the semiconductor device5500can retain data for a long time without power supply. The favorable switching characteristics of the transistor5515allow the semiconductor device5500to perform high-speed backup and recovery.

In this embodiment, one mode of a semiconductor device of one embodiment of the present invention will be described with reference toFIGS. 31A and 31BandFIGS. 32A and 32B.

FIG. 31Ais a top view of a substrate711before dicing treatment. As the substrate711, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used, for example. A plurality of circuit regions712are provided over the substrate711. A semiconductor device of one embodiment of the present invention or the like can be provided in the circuit region712.

Each of the circuit regions712is surrounded by a separation region713. Separation lines (also referred to as “dicing lines”)714are set at a position overlapping with the separation regions713. The substrate711can be cut along the separation lines714into chips715including the circuit regions712.FIG. 31Bis an enlarged view of the chip715.

A conductive layer, a semiconductor layer, or the like may be provided in the separation regions713. Providing a conductive layer, a semiconductor layer, or the like in the separation regions713relieves ESD that might be caused in a dicing step, preventing a decrease in the yield of the dicing step. A dicing step is generally performed while pure water whose specific resistance is decreased by dissolution of a carbonic acid gas or the like is supplied to a cut portion, in order to cool down the substrate, remove swarf, and prevent electrification, for example. Providing a conductive layer, a semiconductor layer, or the like in the separation regions713allows a reduction in the usage of the pure water. Thus, the cost of manufacturing semiconductor devices can be reduced. In addition, semiconductor devices can be manufactured with improved productivity.

An example of an electronic component using the chip715will be described with reference toFIGS. 32A and 32B. Note that an electronic component is also referred to as a semiconductor package or an IC package. For electronic components, there are various standards, names, and the like in accordance with the direction in which terminals are extracted, the shapes of terminals, and the like.

The electronic component is completed when the semiconductor device described in any of the above embodiments is combined with components other than the semiconductor device in an assembly process (post-process).

The post-process is described with reference to a flow chart inFIG. 32A. After the semiconductor device of one embodiment of the present invention and the like are formed over the substrate711in a pre-process, a back surface grinding step in which the back surface (the surface where a semiconductor device and the like are not formed) of the substrate711is ground is performed (Step S721). When the substrate711is thinned by grinding, the size of the electronic component can be reduced.

Next, the substrate711is divided into a plurality of chips715in a dicing step (Step S722). Then, the divided chips715are individually bonded to a lead frame in a die bonding step (Step S723). To bond the chip715and a lead frame in the die bonding step, a method such as resin bonding or tape-automated bonding is selected as appropriate depending on products. Note that the chip715may be bonded to an interposer substrate instead of the lead frame.

Next, a wire bonding step for electrically connecting a lead of the lead frame and an electrode on the chip715through a metal wire is performed (Step S724). As the metal wire, a silver wire, a gold wire, or the like can be used. Ball bonding or wedge bonding can be used as the wire bonding.

The wire-bonded chip715is subjected to a molding step of sealing the chip with an epoxy resin or the like (Step S725). Through the molding step, the inside of the electronic component is filled with a resin, so that a wire for connecting the chip715to the lead can be protected from external mechanical force, and deterioration of characteristics (decrease in reliability) due to moisture or dust can be reduced.

Subsequently, the lead of the lead frame is plated in a lead plating step (Step S726). Through the plating process, corrosion of the lead can be prevented, and soldering for mounting the electronic component on a printed circuit board in a later step can be performed with higher reliability. Then, the lead is cut and processed in a formation step (Step S727).

Next, a printing (marking) step is performed on a surface of the package (Step S728). After a testing step (Step S729) for checking whether an external shape is good and whether there is malfunction, for example, the electronic component is completed.

FIG. 32Bis a perspective schematic diagram of a completed electronic component.FIG. 32Bshows a perspective schematic diagram of a quad flat package (QFP) as an example of an electronic component. An electronic component750inFIG. 32Bincludes a lead755and the chip715. The electronic component750may include multiple chips715.

The electronic component750inFIG. 32Bis mounted on a printed circuit board752, for example. A plurality of electronic components750are combined and electrically connected to each other over the printed circuit board752; thus, a circuit board on which the electronic components are mounted (a circuit board754) is completed. The completed circuit board754is provided in an electronic device or the like.

A semiconductor device of one embodiment of the present invention can be used for a variety of electronic devices.FIGS. 33A to 33Feach illustrate a specific example of an electronic device including the semiconductor device of one embodiment of the present invention.

FIG. 33Ais an external view illustrating an example of a car. A car2980includes a car body2981, wheels2982, a dashboard2983, lights2984, and the like. The car2980also includes an antenna, a battery, and the like.

An information terminal2910illustrated inFIG. 33Bincludes a housing2911, a display portion2912, a microphone2917, a speaker portion2914, a camera2913, an external connection portion2916, an operation switch2915, and the like. A display panel and a touch screen that use a flexible substrate are provided in the display portion2912. The information terminal2910also includes an antenna, a battery, and the like inside the housing2911. The information terminal2910can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, or an e-book reader.

A notebook personal computer2920illustrated inFIG. 33Cincludes a housing2921, a display portion2922, a keyboard2923, a pointing device2924, and the like. The notebook personal computer2920also includes an antenna, a battery, and the like inside the housing2921.

A video camera2940illustrated inFIG. 33Dincludes a housing2941, a housing2942, a display portion2943, operation switches2944, a lens2945, a joint2946, and the like. The operation switches2944and the lens2945are provided on the housing2941, and the display portion2943is provided on the housing2942. The video camera2940also includes an antenna, a battery, and the like inside the housing2941. The housing2941and the housing2942are connected to each other with the joint2946, and the angle between the housing2941and the housing2942can be changed with the joint2946. By changing the angle between the housings2941and2942, the orientation of an image displayed on the display portion2943may be changed or display and non-display of an image may be switched.

FIG. 33Eillustrates an example of a bangle-type information terminal. An information terminal2950includes a housing2951, a display portion2952, and the like. The information terminal2950also includes an antenna, a battery, and the like inside the housing2951. The display portion2952is supported by the housing2951having a curved surface. A display panel with a flexible substrate is provided in the display portion2952, so that the information terminal2950can be a user-friendly information terminal that is flexible and lightweight.

FIG. 33Fillustrates an example of a watch-type information terminal. An information terminal2960includes a housing2961, a display portion2962, a band2963, a buckle2964, an operation switch2965, an input/output terminal2966, and the like. The information terminal2960also includes an antenna, a battery, and the like inside the housing2961. The information terminal2960is capable of executing a variety of applications such as mobile phone calls, e-mailing, text viewing and editing, music reproduction, Internet communication, and computer games.

The display surface of the display portion2962is bent, and images can be displayed on the bent display surface. Furthermore, the display portion2962includes a touch sensor, and operation can be performed by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon2967displayed on the display portion2962. With the operation switch2965, a variety of functions such as time setting, ON/OFF of the power, ON/OFF of wireless communication, setting and cancellation of a silent mode, and setting and cancellation of a power saving mode can be performed. The functions of the operation switch2965can be set by setting the operating system incorporated in the information terminal2960, for example.

The information terminal2960can employ near field communication that is a communication method based on an existing communication standard. In that case, for example, mutual communication between the information terminal2960and a headset capable of wireless communication can be performed, and thus hands-free calling is possible. Moreover, the information terminal2960includes the input/output terminal2966, and data can be directly transmitted to and received from another information terminal via a connector. Power charging through the input/output terminal2966is also possible. The charging operation may be performed by wireless power feeding without using the input/output terminal2966.

A memory device including the semiconductor device of one embodiment of the present invention, for example, can hold control data, a control program, or the like of the above electronic device for a long time. With the use of the semiconductor device of one embodiment of the present invention, a highly reliable electronic device can be provided.

This application is based on Japanese Patent Application Serial No. 2016-224546 filed with Japan Patent Office on Nov. 17, 2016 and Japanese Patent Application Serial No. 2016-224503 filed with Japan Patent Office on Nov. 17, 2016, the entire contents of which are hereby incorporated by reference.