SMPS power-on with energy saver

In an embodiment, a method for soft-starting an SMPS includes: asserting an enable signal; disabling an output stage of the SMPS; after asserting the enable signal, measuring a feedback voltage of the SMPS; receiving a first reference voltage at an input reference node; comparing the measured feedback voltage with the first reference voltage; and, when the measured feedback voltage is lower than the first reference voltage, storing the feedback voltage in a soft-start capacitor, connecting an output reference node to the soft-start capacitor, enabling the output stage of the SMPS, and switching a transistor of the output stage to regulate the output voltage based on the feedback voltage and a second reference voltage at the output reference node, and injecting a current into the soft-start capacitor.

TECHNICAL FIELD

The present invention relates generally to an electronic system and method, and, in particular embodiments, to a switched-mode power supply (SMPS) power-on with energy saver.

BACKGROUND

Electronic systems are pervasive in modern society. Power supply systems or converters are typically used to supply power to many electronic systems. For example,FIG. 1shows a schematic diagram of exemplary electronic system100having converter102receiving power from battery104and supplying a controlled voltage (Vout) to a load. The load may be, for example, an integrated circuit inside an electronic device, such as a smartphone or wearable device.

Efficiency is an important parameter for electronic systems in general, and for power supply systems in particular. Increasing efficiency may result in many advantages, such as increase battery life, less heat, etc.

An SMPS is a type of converter that uses a switching regulator to transfer power from an AC or DC source into a load. An SMPS is typically more efficient than other types of power supply systems because it is based on controlled charging and discharging of an inductive element, which reduces energy lost due to power dissipation caused by a resistive voltage drop.

An SMPS may be implemented as a step-down (buck) converter, a step-up (boost) converter, a buck-boost converter, among others. A buck converter, for example, typically maintains a constant voltage at its output over a wide range of input voltages and loads.

An SMPS may be operated in various modes, such as a pulse-width modulation (PWM) mode, pulse frequency modulation (PFM) mode, among others. Techniques, such as pulse skipping, are typically used to further improve efficiency.

SUMMARY

In accordance with an embodiment, a method for soft-starting an SMPS includes: asserting an enable signal; disabling an output stage of the SMPS; after asserting the enable signal, measuring a feedback voltage of the SMPS; receiving a first reference voltage at an input reference node; comparing the measured feedback voltage with the first reference voltage; and, when the measured feedback voltage is lower than the first reference voltage, storing the feedback voltage in a soft-start capacitor, connecting an output reference node to the soft-start capacitor, enabling the output stage of the SMPS, and switching a transistor of the output stage to regulate the output voltage based on the feedback voltage and a second reference voltage at the output reference node, and injecting a current into the soft-start capacitor.

In accordance with an embodiment, a circuit includes: an input terminal configured to receive an input voltage; an output terminal configured to be coupled to an inductor and an output capacitor; a feedback terminal configured to be coupled to the output capacitor; an output stage coupled to the output terminal; a controller configured to regulate an output voltage at the output capacitor based on a first reference voltage and a feedback voltage of the feedback terminal; and a soft-start circuit. The soft-start circuit includes an output reference terminal configured to provide the first reference voltage, an input reference terminal configured to receive a second reference voltage, a soft-start capacitor, a first switch coupled between the input reference terminal and the output reference terminal, and a second switch coupled between the soft-start capacitor and the feedback terminal, and a third switch coupled between the soft-start capacitor and the output reference terminal, where, when an enable signal transitions from a first state to a second state, the soft-start circuit is configured to: disable the output stage, determine a feedback voltage, compare the determined feedback voltage with the second reference voltage, and when the determined feedback voltage is lower than the second reference voltage: close the second switch to store the feedback voltage in the soft-start capacitor, close the third switch, enable the output stage, and inject a current into the soft-start capacitor.

In accordance with an embodiment, a buck converter includes: a first supply terminal and a second supply terminal configured to be coupled to a power source; an output terminal; an inductor coupled to the output terminal; an output capacitor coupled between the inductor and the second supply terminal; a feedback terminal coupled to the output capacitor; an output stage coupled to the output terminal, the output stage including a half-bridge coupled to the output terminal, and a gate driver circuit coupled to the half-bridge; a ramp generator; an error amplifier having a first input configured to receive a first reference voltage and a second input coupled to the feedback terminal; a PWM controller having an output coupled to the output stage and configured to regulate an output voltage at the output capacitor based on an output of the error amplifier and an output of the ramp generator; and a soft-start circuit. The soft-start circuit includes an output reference terminal configured to provide the first reference voltage, an input reference terminal configured to receive a second reference voltage, a soft-start capacitor, a first switch coupled between the input reference terminal and the output reference terminal, a second switch coupled between the soft-start capacitor and the feedback terminal, and a third switch coupled between the soft-start capacitor and the output reference terminal, where, when an enable signal transitions from a first state to a second state, the soft-start circuit is configured to: disable the output stage, determine a feedback voltage at the feedback terminal, compare the determined feedback voltage with the second reference voltage, and when the determined feedback voltage is lower than the second reference voltage: close the second switch to store the feedback voltage in the soft-start capacitor, close the third switch, enable the output stage, and inject a current into the soft-start capacitor.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The description below illustrates the various specific details to provide an in-depth understanding of several example embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials and the like. In other cases, known structures, materials or operations are not shown or described in detail so as not to obscure the different aspects of the embodiments. References to “an embodiment” in this description indicate that a particular configuration, structure or feature described in relation to the embodiment is included in at least one embodiment. Consequently, phrases such as “in one embodiment” that may appear at different points of the present description do not necessarily refer exactly to the same embodiment. Furthermore, specific formations, structures or features may be combined in any appropriate manner in one or more embodiments.

The present invention will be described with respect to embodiments in a specific context, a buck converter having a soft-start circuit. Embodiments of the present invention may be used in other SMPS topologies, such as boost and buck-boost topologies, as well as in other circuits implementing a soft-start circuit.

In an embodiment of the present invention, a buck converter saves energy by periodically disabling the buck converter (e.g., when not in use) without discharging the output capacitor. A spike of current flowing through the inductor of the buck converter is avoided by sampling a feedback signal when the buck converter is enabled, and comparing the sampled signal with a threshold. If the sampled signal is higher than the threshold, the buck converter waits until the load draws enough current to decrease the output voltage below the threshold, at which point the buck converter begins operating normally. If the sampled signal is lower than the threshold, the buck converter is enabled and a reference signal is ramped starting from the sampled voltage.

During normal operation, PWM controller206adjusts the duty cycle of signal VPWMsuch that control logic212and gate driver circuit214drives half-bridge216to produce output voltage Voutsubstantially equal to an expected voltage. PWM controller206determines the duty cycle of signal VPWMbased on error signal Verrand ramp Vramp. Error signal Vrefis based on feedback voltage Vfb(which is based on output voltage Vout) and reference voltage Vref.

FIG. 2Bshows waveforms of buck converter202, according to an embodiment of the present invention. As shown inFIG. 2B, signal VPWMis low when ramp Vrampis higher than error signal Verrand is high when ramp Vrampis lower than error signal Verr. When output voltage Voutdecreases, feedback voltage Vfbdecreases, causing error signal Verrto increase, thereby causing the duty cycle of signal VPWMto increase, which increases output voltage Vout. An opposite behavior is observed when output voltage Voutincreases, thereby maintaining output voltage Voutsubstantially equal to the expected value. The expected value may be modified by adjusting, for example, the value of resistors224or226, reference voltage Vref, the gain of error amplifier208, or in any other way known in the art.

When activating buck converter202, a current spike flowing through inductor218may occur based on a voltage developed across inductor218. For example, if output capacitor is charged to a first voltage V1, and reference voltage Vrefis initially at 0 V, error signal Verrbecomes negative, thereby causing transistor230to discharge capacitor220to ground via inductor218. Similarly, if output capacitor is initially discharged (o V), and reference voltage Vrefis initially high, error signal Verrbecomes high, thereby casing transistor228to rapidly charge output capacitor220via inductor218.

To avoid a current spike flowing through inductor218during start-up of buck converter202, output capacitor220is conventionally discharged before enabling buck converter202. Upon enabling buck converter202(e.g., by asserting signal SMPS_ON), reference voltage Vrefis conventionally ramped up from 0 V. In this way, output voltage Voutis initially at 0 V and reference voltage Vrefis initially at 0 V, which causes error signal Verrto be initially at 0 V. As reference voltage Vrefincreases, so does output voltage Vout, thereby avoiding a current spike from flowing through inductor218.

In low power systems, buck converter202may be activated and deactivated on a regular basis (e.g., using enable signal EN) in order to decrease power consumption. For example, buck converter202may be deactivated when not needed to reduce power consumption. In some low power systems, buck converter202may be deactivated every 300 ms, 100 ms, or faster. The discharging of output capacitor220each activation/deactivation draws current from battery104, which may be significant. For example, an output capacitor220having a capacitance of 2.2 μF charged and discharged to 3 V every 100 ms consumes an average current of about 66 μA from battery104.

In some embodiments, buck converter202saves energy (i.e., increases efficiency) by avoiding discharging output capacitor220each activation/deactivation cycle of buck converter202. Buck converter202avoids a current spike flowing through inductor218by sampling feedback voltage V when enable signal EN is asserted, and comparing the sampled signal with a threshold. If the sampled signal is higher than the threshold, buck converter202waits until load106draws enough current to decrease output voltage Voutbelow the threshold, at which point buck converter202begins operating normally. If the sampled signal is lower than the threshold, buck converter202is enabled and reference voltage Vrefis ramped starting from the sampled voltage.

Battery104may be, for example, a lithium-ion battery. Other types of power sources may be used. For example, in some embodiments, battery104may be a 12 V battery from a car. Other embodiments may implement a power source different than a battery. For example, some embodiments may use the output of a power converter to supply voltage Vbatinstead of a battery.

Load106may be, for example, an integrated circuit, such as processor or micro-controller. The load may also be a circuit inside a power management integrated circuit (PMIC), a light-emitting diode (LED), or any other load that is conventionally supplied by an SMPS.

Voltage divider222is implemented using resistors224and226as shown inFIG. 2A. In some embodiments, feedback voltage V may be obtained in other ways, such as by using optocouplers, an analog-to-digital converter (ADC) or in other ways known in the art.

PWM controller206, control logic212, gate driver circuits214, error amplifier208, and ramp generator210may be implemented in any way known in the art. For example, in some embodiments, PWM controller206, control logic212, gate driver circuits214, error amplifier208, and ramp generator210may be implemented using custom analog and digital circuits. In other embodiments, PWM controller206, control logic212, gate driver circuits214, error amplifier208, and ramp generator210may be implemented with a general purpose micro-controller and discrete amplifiers.

Some embodiments implement switching techniques different than PWM. For example, some embodiments implement PFM mode instead or in addition to the PWM controller. Other switching techniques may also be used.

In some embodiments, PWM controller206, control logic212, gate driver circuits214, error amplifier208, ramp generator210, soft-start circuit204, half-bridge216, inductor218, output capacitor220, and voltage divider222are implemented with discrete components. In other embodiments, PWM controller206, control logic212, gate driver circuits214, error amplifier208, ramp generator210, soft-start circuit204, half-bridge216and voltage divider222are integrated within the same die of an integrated circuit (IC). In some embodiments, PWM controller206, control logic212, gate driver circuits214, error amplifier208, ramp generator210, soft-start circuit204, half-bridge216and voltage divider222are integrated in multiple dies within the same package. In some embodiments, half-bridge216is implemented externally to the IC or package. Other implementations are also possible.

FIG. 3shows a flowchart of embodiment method300for SMPS power-on, according to an embodiment of the present invention.FIG. 3may be understood in view ofFIG. 2A. Method300may be implemented, for example, by soft-start circuit204. In some embodiments, method300is implemented by a general purpose controller. In other embodiments, method300is implemented by custom logic and using analog circuits. Other implementations are also possible.

During step302, the SMPS, such as buck converter202is disabled (e.g., by deasserting enable signal EN). Disabling the SMPS causes the SMPS to stop switching (e.g., half-bridge216stops switching). During step304, the SMPS is enabled (e.g., by asserting enable signal EN). Enabling the SMPS, however, does not cause the SMPS to start switching. In other words, an output stage of the SMPS (e.g., half-bridge216) is kept off (e.g., drivers232and234keep off transistors228and230).

After enabling the SMPS, feedback voltage Vfbis sampled during step306. Sampling feedback voltage Vfbmay be performed by using an ADC, a peak detector, a capacitor, a flip-flop, or in any other way known in the art.

During step308, feedback voltage Vfbis compared with a threshold voltage Vth. In some embodiments, the threshold voltage Vthcorresponds to a reference voltage provided by a reference circuit, such as voltage REF_SMPS (not shown inFIG. 2A). In some embodiments, the reference circuit is a bandgap circuit having a voltage of 1.2 V.

If feedback voltage Vfbis not lower than the threshold voltage Vth, the SMPS enters into pre-charged mode, in which a reference voltage provided to the SMPS, such as reference voltage Vref(as shown inFIG. 2A) is connected to the reference voltage (e.g., REF_SMPS) during step314.

In some embodiments, feedback voltage Vfbis higher than threshold voltage Vth when the SMPS is off (e.g., in high impedance mode) due to leakage (e.g., from a path coupled to a supply voltage). In some embodiments, feedback voltage Vfbis intentionally pulled higher than threshold voltage Vth(e.g., to supply voltage Vbat) by pulling up, e.g., output voltage Vout, using, e.g., a pull-up transistor, when the SMPS is off. By raising output voltage Vout, thereby charging output capacitor220, a faster startup time may be achieved.

During step316, the SMPS waits until feedback voltage Vfbdecreases below the threshold voltage Vth. The decrease in voltage may happen due to a load (e.g., load106) sinking current, due to leakage currents (e.g., in output capacitor220) for example. After feedback voltage Vfbbecomes lower than the threshold voltage Vth, the SMPS is turned on in step318, which causes the SMPS to start switching and regulating (e.g., half-bridge216begins switching). The SMPS may be disabled again for saving energy during step302.

If feedback voltage Vfbis lower than the threshold voltage Vth, the SMPS enters into soft-start mode, in which the reference voltage provided to the SMPS (e.g., Vref) is set equal to voltage feedback voltage Vfbduring step310. During step311, the SMPS is turned on, which causes the SMPS to start switching and regulating. During step312, the reference voltage provided to the SMPS (e.g., Vref) is ramped, starting from the initial voltage (e.g., Vfb) up to voltage REF_SMPS, thereby causing output voltage Vout, and feedback voltage Vfbto ramp up (since the SMPS has already been turned on in step311). The SMPS may be disabled again for saving energy during step302. In some embodiments steps310and306may occur concurrently. In some embodiments, steps311and312may occur concurrently.

Advantages of some embodiments include the preservation of the charge in the output capacitor of the SMPS upon activating the SMPS in both the pre-charged mode and the soft-start mode. By preserving the charged of the output capacitor, such charge may be delivered to the load instead of being discharged to ground, thereby increasing the efficiency of the SMPS.

In an embodiment, a soft-start circuit samples a feedback voltage of a buck converter by using a comparator and a D-flip-flop. Based on the output of the D-flip-flop, the buck converter enters into pre-charged mode or in soft-start mode. In pre-charged mode, the buck converter connects a reference voltage (e.g., Vref) to a second reference voltage (e.g., REF_SMPS) and begins regulating after the feedback decreases below the second reference voltage. In soft-start mode, the buck converter connects the reference voltage to a soft-start capacitor, and injects current into the soft-start capacitor to ramp up the reference voltage.

FIG. 4shows a schematic diagram of soft-start circuit400, according to an embodiment of the present invention.FIGS. 5 and 6show waveforms of soft-start circuit400during pre-charged mode and soft-start mode, respectively, according to an embodiment of the present invention.FIG. 4may be understood in view ofFIGS. 5 and 6.

During normal operation, since output capacitor220is not actively discharged after buck converter202is disabled, output voltage Voutmay be different than 0 V before enabling buck converter202. When enable signal EN is asserted (e.g., transitions from low to high), controller402starts clock CLK (as illustrated by signal CLK_OK inFIGS. 4 and 5) and closes switch404by asserting signal S404(as illustrated inFIGS. 4 and 5).

Upon starting clock CLK, controller402starts a counter (not shown) that counts for a pre-determined time (e.g., 20 us). The pre-determined time may be, for example, an initialization time to properly bias analog blocks of buck converter202. Once the counter reaches the predetermine time, controller402deasserts signal S404and asserts signal BIAS_OK (as illustrated inFIGS. 4 and 5).

Before signal BIAS_OK is asserted, D-flip-flops413,416, and419are in a reset state (their associated outputs are low). When signal BIAS_OK is asserted, D-flip-flop416latches in the output of comparator414. Comparator414outputs a high when voltage REF_SMPS is higher than feedback voltage Vfband a low when voltage REF_SMPS is lower than feedback voltage Vfb.

If D-flip-flop416latches in a 1, signal SFST becomes high, signal PRECH becomes low, and buck converter202enters the soft-start mode (as shown inFIG. 6). If D-flip-flop416latches in a 0, signal SFST becomes low, signal PRECH becomes high, and buck converter202enters the pre-charged mode (as shown inFIG. 5).

When in pre-charged mode, switch426is closed by signal PRECH, which causes reference voltage Vrefto be connected to voltage REF_SMPS (as shown by curve502, which illustrates reference voltage Vref, inFIG. 5). Signal SMPS_ON, however, remains low until feedback voltage Vfbbecomes lower than voltage REF_SMPS (as shown by curve504, which illustrates feedback voltage Vfb, inFIG. 5). When feedback voltage Vfbbecomes lower than voltage REF_SMPS, OR gate420outputs a 1, which causes signal SMPS_ON to assert, thereby causing buck converter202to begin regulating output voltage Vout.

When in soft-start mode, switch424is closed by signal SFST, which causes reference voltage Vrefto be connected to soft-start capacitor406(which has initially a voltage equal to feedback voltage Vf6as a result of pulsing signal S404, as shown inFIG. 6). Signal SFST also causes OR gate420to output a 1, which causes signal SMPS_ON to assert, thereby causing buck converter202to begin regulating output voltage Vout, as shown inFIG. 6.

As shown inFIG. 4, comparator412causes switch408to close when voltage REF_SMPS is higher than voltage V406. Current source410, therefore, injects a current into soft-start capacitor406than ramps up voltage V406, and reference voltage Vrefuntil reference voltage Vrefreaches voltage REF_SMPS, as shown by curve502inFIG. 6. Since buck converter202is regulating output voltage Vout, feedback voltage Vfbalso ramps up, as shown by curve504inFIG. 6.

When voltage V406reaches REF_SMPS, signal S412goes low. D-flip-flop413and AND gate411latch the output of D-flip-flop413to 0, thereby causing switch408to open and stop the charging of soft-start capacitor406. Leakage currents may cause soft-start capacitor406to slowly discharge, which causes voltage V406to decreases, thereby causing signal S412to become high. However, signal S412transitioning from low to high does not cause the output of D-flip-flop413to change to 1. By avoiding periodically switching switch408on and off, ripple in voltage V406is avoided. Such ripple may be undesirable in some embodiments. This is advantageous, for example, for embodiments that exhibit low leakage currents of soft-start capacitor406. An improvement is shown inFIG. 7, in which AND gate702and OR gate704allow to connect reference voltage Vrefto voltage REF_SMPS after voltage V406reaches voltage REF_SMPS.

In embodiments in which ripple in voltage V406is tolerated, a loop comprising comparator412, AND gate409and switch408causes soft-start capacitor406to maintain voltage V406at a level substantially equal to voltage REF_SMPS despite any leakage associated with soft-start capacitor406. For example, in an embodiment that does not implement D-flip-flop413and AND gate411(e.g., output of comparator412directly connected to the input of AND gate409), voltage V406may be kept substantially equal to REF_SMPS while exhibiting a ripple with a saw-tooth shape.

Switches404,424and426may be implemented in any way known in the art, such as using metal-oxide-semiconductor (MOS) transistors, or solid-state relays, or mechanical relays, for example.

Flip-flop416is implemented as a D-flip-flop. In some embodiments, a different type of flip-flop, such as an SR-flip-flop, T-flip-flop, or other, may be used with appropriate modifications.

In some embodiments, voltage REF_SMPS may be produced by a bandgap circuit, such as bandgap430o. In some embodiments, voltage REF_SMPS may be produced by a voltage regulator or voltage source. In some embodiments, voltage REF_SMPS is produced inside soft-start circuit400. In other embodiments, voltage REF_SMPS is received from a voltage source that is external to soft-start circuit400.

Controller402may be implemented as a stand-alone controller, or as part of another controller. For example, in some embodiments, controllers206and406are implemented as a single controller.

FIG. 7shows a schematic diagram of soft-start circuit700, according to an embodiment of the present invention. Soft-start circuit700operates in a similar manner as soft-start circuit400. Soft-start circuit700, however, connects reference voltage Vrefto voltage REF_SMPS after voltage V4o6reaches voltage REF_SMPS during soft-start mode.

Soft-start circuit700advantageous uses the same voltage REF_SMPS for operating buck converter202regardless of which mode was used to power-on buck converter202. In some embodiments, voltage REF_SMPS may be more stable than a voltage across the soft-start capacitor.

Some embodiments may be applied to SMPS other than buck. For example, a boost converter may save energy by avoiding the discharge of the output capacitor when the boost converter is off.

A method for soft-starting a switched-mode power supply (SMPS), the method including: asserting an enable signal, where the SMPS is activated or deactivated based on the enable signal; disabling an output stage of the SMPS; after asserting the enable signal, measuring a feedback voltage of the SMPS, the feedback voltage being based on an output voltage of the SMPS; receiving a first reference voltage at an input reference node; comparing the measured feedback voltage with the first reference voltage; and when the measured feedback voltage is lower than the first reference voltage: storing the feedback voltage in a soft-start capacitor, connecting an output reference node to the soft-start capacitor, enabling the output stage of the SMPS and switching a transistor of the output stage to regulate the output voltage based on the feedback voltage and a second reference voltage at the output reference node, and injecting a current into the soft-start capacitor.

The method of example 1, further including, when the measured feedback voltage is higher than the first reference voltage, connecting the input reference node to the output reference node, waiting until the feedback voltage decreases to a voltage lower than the first reference voltage, and when the feedback voltage becomes lower than the first reference voltage, enabling the output stage of the SMPS and switching the transistor of the output stage to regulate the output voltage based on the feedback voltage and the second reference voltage.

The method of one of examples 1 or 2, further including, when the measured feedback voltage is lower than the first reference voltage, connecting the input reference node to t output reference node after a voltage of the soft-start capacitor reaches the first reference voltage.

The method of one of examples 1 to 3, further including receiving the first reference voltage from a bandgap circuit.

The method of one of examples 1 to 4, where the feedback voltage is lower than the output voltage.

The method of one of examples 1 to 5, where the transistor is a transistor of a half-bridge of the SMPS.

The method of one of examples 1 to 6, where disabling the SMPS includes turning off the transistor and a second transistor of the half-bridge.

The method of one of examples 1 to 7, further including asserting and deasserting the enable signal every 300 ms or faster.

The method of one of examples 1 to 8, further including pulling up the output voltage when the SMPS is deactivated.

A circuit including: an input terminal configured to receive an input voltage; an output terminal configured to be coupled to an inductor and an output capacitor; a feedback terminal configured to be coupled to the output capacitor; an output stage coupled to the output terminal; a controller configured to regulate an output voltage at the output capacitor based on a first reference voltage and a feedback voltage of the feedback terminal; and a soft-start circuit including an output reference terminal configured to provide the first reference voltage, an input reference terminal configured to receive a second reference voltage, a soft-start capacitor, a first switch coupled between the input reference terminal and the output reference terminal, and a second switch coupled between the soft-start capacitor and the feedback terminal, and a third switch coupled between the soft-start capacitor and the output reference terminal, where, when an enable signal transitions from a first state to a second state, the soft-start circuit is configured to: disable the output stage, determine a feedback voltage, compare the determined feedback voltage with the second reference voltage, and when the determined feedback voltage is lower than the second reference voltage: close the second switch to store the feedback voltage in the soft-start capacitor, close the third switch, enable the output stage, and inject a current into the soft-start capacitor.

The circuit of example 10, where the soft-start circuit is further configured to, when the determined feedback voltage is higher than the second reference voltage, close the first switch to provide the second reference voltage to the output reference terminal, wait until the feedback voltage decreases to a voltage lower than the second reference voltage, and enable the output stage when the feedback voltage becomes lower than the second reference voltage.

The circuit of one of examples 10 or 11, where the soft-start circuit is further configured to, when the determined feedback voltage is lower than the second reference voltage, provide the second reference voltage at the output reference terminal after a voltage of the soft-start capacitor reaches the second reference voltage.

The circuit of one of examples 10 to 12, where the soft-start circuit further includes a current source and a fourth switch coupled between the current source and the soft-start capacitor, where the soft-start circuit is configured to inject the current into the soft-start capacitor by closing the fourth switch.

The circuit of one of examples 10 to 13, where the soft-start circuit further includes: a comparator having a first input coupled to the input reference terminal, and a second input coupled to the feedback terminal; and a flip-flop having an input coupled to an output of the comparator and a second input configured to receive a first signal, where the soft-start circuit is configured to compare the feedback voltage with the second reference voltage by asserting the first signal.

The circuit of one of examples 10 to 14, where the flip-flop is a D-flip-flop and the second input of the flip-flop is a clock input.

The circuit of one of examples 10 to 15, further including the inductor and the output capacitor, where the output terminal is coupled to the inductor and the output capacitor.

The circuit of one of examples 10 to 16, further including a first resistor coupled between the output capacitor and the feedback terminal, and a second resistor coupled between the feedback terminal and a reference terminal.

The circuit of one of examples 10 to 17, where the output stage includes a half-bridge.

A buck converter including: a first supply terminal and a second supply terminal configured to be coupled to a power source; an output terminal; an inductor coupled to the output terminal; an output capacitor coupled between the inductor and the second supply terminal; a feedback terminal coupled to the output capacitor; an output stage coupled to the output terminal, the output stage including a half-bridge coupled to the output terminal, and a gate driver circuit coupled to the half-bridge; a ramp generator; an error amplifier having a first input configured to receive a first reference voltage and a second input coupled to the feedback terminal; a pulse-width modulation (PWM) controller having an output coupled to the output stage and configured to regulate an output voltage at the output capacitor based on an output of the error amplifier and an output of the ramp generator; and a soft-start circuit including an output reference terminal configured to provide the first reference voltage, an input reference terminal configured to receive a second reference voltage, a soft-start capacitor, a first switch coupled between the input reference terminal and the output reference terminal, a second switch coupled between the soft-start capacitor and the feedback terminal, and a third switch coupled between the soft-start capacitor and the output reference terminal, where, when an enable signal transitions from a first state to a second state, the soft-start circuit is configured to: disable the output stage, determine a feedback voltage at the feedback terminal, compare the determined feedback voltage with the second reference voltage, and when the determined feedback voltage is lower than the second reference voltage: close the second switch to store the feedback voltage in the soft-start capacitor, close the third switch, enable the output stage, and inject a current into the soft-start capacitor.

The buck converter of example 19, where the soft-start circuit is furthered configured to, when the determined feedback voltage is higher than the second reference voltage, close the first switch to provide the second reference voltage to the output reference terminal, wait until the feedback voltage decreases to a voltage lower than the second reference voltage, and when the feedback voltage becomes lower than the second reference voltage, enable the output stage.

The buck converter of one of examples 19 or 20, further including the power source, where the power source is a battery.