Semiconductor fin-shaped structure and manufacturing process thereof

The present invention provides a method for forming a fin structure comprising the following steps: first, a substrate is provided and a plurality of fin structures, a plurality of first dummy fin structures and a plurality of second dummy fin structures are formed on the substrate; a first patterned photoresist is used as a hard mask to perform a first etching process to remove each first dummy fin structure; then a second patterned photoresist is used as a hard mask to perform a second etching process to remove each second dummy fin structure, wherein the pattern density of the first patterned photoresist is higher than the pattern density of the second patterned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor manufacturing process, and more particularly to a method for improving the precision when removing the fin structures.

2. Description of the Prior Art

With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), the three-dimensional or non-planar transistor technology, such as the fin field effect transistor technology (Fin FET), has been developed to replace planar MOS transistors.

However, as the size of the FETs shrink, the electrical and physical requirements in each part of the multi-gate FET become critical, like the sizes and shapes of the fin-shaped structures and the spacing between each fin-shaped structure for example. Thus, how to reach standard requirements and overcome the physical limitations has become an important issue in the industry of the FETs.

In conventional processes, if a plurality of fin structures is disposed on a substrate, and the interval between each fin structure is small, when a photo-etching process is performed only once to remove some fin structures, since the density of fin structures between different regions (including the isolated region and the dense region) on the substrate is different, a precise positioning process is needed to etch some fin structures, so as to keep the required fin structures, which requires additional effort and time.

SUMMARY OF THE INVENTION

The present invention provides a method for forming a fin structure comprising the following steps: first, a substrate is provided, and a plurality of fin structures, a plurality of first dummy fin structures and a plurality of second dummy fin structures are formed on the substrate; a first patterned photoresist is used as a hard mask to perform a first etching process and to remove each first dummy fin structure; afterwards, a second patterned photoresist is used as a hard mask to perform a second etching process and to remove each second dummy fin structure, wherein the pattern density of the first patterned photoresist is higher than the pattern density of the second patterned.

The present invention further provides a fin structure comprising: a long thin fin structure, a short wide fin structure disposed between the long thin fin structure and a substrate, a first isolating layer disposed on the side of the short wide fin structure and a second isolating layer disposed between the long thin fin structure and the first isolating layer, which is disposed on the short wide fin structure.

The method of the present invention uses two different etching processes to remove parts of the fin structures. After the first etching process is performed, the density of fin structures on the substrate has lowered, therefore, the required fin structures can be kept precisely after the second etching process is performed, thereby reducing the complexity of the process, and avoiding the method the need for a lot of effort on the positioning process.

DETAILED DESCRIPTION

To provide a better understanding of the present invention to users skilled in the technology of the present invention, preferred embodiments are detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the contents and the effects to be achieved.

Please note that the figures are only for illustration and the figures may not be to scale. The scale may be further modified according to different design considerations. When referring to the words “up” or “down” that describe the relationship between components in the text, it is well known in the art and should be clearly understood that these words refer to relative positions that can be inverted to obtain a similar structure, and these structures should therefore not be precluded from the scope of the claims in the present invention.

Please refer toFIGS. 1˜11.FIGS. 1-11are schematic, cross-sectional diagrams showing a method for forming a fin structure according to the first preferred embodiment of the present invention.

As shown inFIG. 1, a substrate10is provided, such as a bulk silicon substrate; then, a multiple layer structure11is formed on the substrate10as a hard mask, wherein the multiple layer structure11includes at least two materials. In this embodiment, the multiple layer structure11includes a top layer12and a bottom layer13, which are formed through a regular deposition process. Besides, a buffer layer14may be selectively formed between the multiple layer structure11and the substrate10, wherein the buffer layer14not only serves as a hard mask in the following pattern transfer process but is also used as a protective layer to protect the substrate10from unwanted damages. It is worth noting that each material comprised in the multiple layer structure11has a different etching selectivity to each other. For example, in this embodiment, the top layer12is silicon oxide, and the bottom layer13is silicon nitride; the etching rates of those two materials are different during etching processes. Besides, a buffer layer14is selectively formed and disposed between the multiple layer structure11and the substrate10, which has a different etching selectivity from the adjacent bottom layer13.

As shown inFIG. 1, at least one sacrificial gate16is formed on the multiple layer structure11, which comprises a material having a different etching selectivity from the multiple layer structure11. In this embodiment, the material of the sacrificial gate16is preferably chosen to be amorphous silicon or poly silicon, which are easier to be removed during following etching processes, but not limited thereto; other suitable materials can also be selected as the material of the sacrificial gate16. Then, at least a material layer (not shown) is formed to cover each sacrificial gate16. The material layer may be selected to be a material having a different etching rate from that of the sacrificial gate16, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide or the likes. In the present embodiment silicon nitride is selected as the material, but it is not limited thereto. An etching process is then performed on the material layer, such as a plasma process, to form a plurality of “sail-shaped” spacers20on the sidewall of each sacrificial gate16. In this embodiment, the spacers comprise silicon nitride, but not limited thereto. Besides, the size of each component can be adjusted according to actual requirement.

As shown inFIGS. 2˜3. The sacrificial gate16is entirely removed, the rest of the spacers20is used as a mask, and a pattern transfer process is performed on the multiple layer structure11to transfer the pattern of the spacers20to the multiple layer structure11and to form a plurality of corresponding patterned multiple layer structures21. It should be noted that the pattern transfer process may include a plurality of etching processes and a corresponding preferred embodiment is described as follows. First, the sacrificial gate16is completely removed through a regular etching process, such as dry etching or wet etching process, so that only the spacers20remain on the multiple layer structure11. During this etching process, since the etching rate of the sacrificial gate16is higher than that of the spacers20, only parts or even nothing of the spacers20are etched away. Then, by using the spacers20as a mask, one or more than one anisotropic etching processes are carried out to sequentially etch down the multiple layer structure11and the buffer layer14. At this time, the patterns defined by the spacers20can be transferred to the multiple layer structure11and the buffer layer14. Besides, since many etching processes are performed, by the time the bottom layer13or the buffer layer14is to be etched, the sail-shape spacers20may have been etched away or completely removed. It is worth noting that, the “the pattern transfer process” also includes the concepts of the “sidewall image transfer (SIT) process”; in other words, the “pattern transfer process” can be deemed as a superordinate concept of the “sidewall image transfer process”.

Afterwards, the patterned multiple layer structures21is used as a hard mask, to perform another SIT process that transfers the pattern of the patterned multiple layer structure21to the substrate10, so as to form a plurality of trenches by removing parts of the substrate10, and to form at least one fin structure26in the substrate10between the trenches. The fin structure further comprises a plurality of first dummy fin structures26A and a plurality of second dummy fin structures26B, but not limited thereto. The SIT process here is similar to the SIT process mentioned above. Besides, since many etching processes are performed, at this time, or by the time the bottom layer13or the buffer layer14mentioned above is to be etched, the sail-shaped spacers20may have been etched away or completely removed, but not limited thereto; parts of the spacers20may still remain on the patterned multiple layer structures21.

Please refer toFIG. 4; an isolating layer28is filled between the fin structures26; then, a planarizing process (such as a chemical mechanical process, CMP) and an etching back process are performed in sequence to etch parts of the isolating layer28to allow the fin structures26to jut out the top surface of the isolating layer28. A liner29can be selectively formed on the surface of the fin structures26and a cap layer30is then formed on the isolating layer28to cover each fin structure26. The material of the isolating layer28mainly includes silicon oxide, the material of the liner29mainly includes silicon oxide and the material of the cap layer30mainly includes a silicon nitride, but not limited thereto.

As shown inFIG. 5, a first dielectric layer33is formed on the cap layer30, wherein the first dielectric layer33can be a single layer structure or multiple layer structure. In this embodiment, the first dielectric layer33includes a bottom layer31and a top layer32, wherein the bottom layer31and the top layer32are made of different materials, such as silicon nitride and silicon oxide respectively, but not limited thereto. The materials can be adjusted according to the actual requirements. Then, a plurality of first patterned photoresists34is formed on the first dielectric layer33, wherein each first patterned photoresist34is substantially disposed correspondingly to the first dummy fin structures26A disposed below. More precisely, in this embodiment, the first dummy fin structures26A are arranged in intervals, therefore the first patterned photoresists34are arranged in intervals too and one other fin structures26is disposed between each two first dummy fin structures26A. In other words, if each the fin structures26on the substrate10is noted with a number, only the fin structures26having an odd number (or an even number) are the first dummy fin structures26A, and the corresponding first patterned photoresist34is disposed above. The first patterned photoresists34will not be disposed correspondingly to other fin structures26adjacent to the first dummy fin structures26A. In this embodiment, the width of each first patterned photoresist34is about 48 nanometer (nm), but not limited thereto. It is worth noting that, in this embodiment, the first patterned photoresists34are arranged in intervals (odd number intervals or even number intervals), but the present invention is not limited thereto; it can be adjusted according to actual requirements.

A first etching process E1is then performed to etch the region that is not covered by the first patterned photoresist34, including etching the first dielectric layer33, the cap layer30, the first dummy fin structures26A, the isolating layer28and parts of the substrate10in sequence. More precisely, during the first etching process E1, since the first dummy fin structures26A are arranged in odd intervals or even intervals, the amount of removed first dummy fin structures26A is the same as the amount of the remaining fin structures26, but the present invention is not limited thereto; the amount of remaining fin structures26is related to the arrangement of the first patterned photoresist34. Since the size and the amount of the first patterned photoresist34can be adjusted according to actual requirements, the amount of remaining fin structures26can be different after the first etching process E1has been performed in other embodiments.

In this embodiment, after the first etching process E1is performed, as shown inFIG. 6, since the first dummy fin structures26A have been removed, the interval between the remaining fin structures26and the adjacent fin structures26become larger, thereby reducing the difficulty of the positioning process in the following steps. In addition, the first etching process E1further partially removes the substrate10disposed below the first dummy fin structures26A to form a plurality of trenches35and a short wide fin structure36is formed between the trenches35and the remaining fin structures26are disposed on each short wide fin structure36. Besides, parts of the isolating layer28are disposed on the sidewall of the fin structures26and disposed on the short wide fin structure36. It is worth noting that the sidewall of the isolating layer28is trimmed with the sidewall of the short wide fin structure36.

As shown inFIG. 7, a second dielectric layer43is formed to fill the trench35and cover the cap layer30, wherein the second dielectric layer43can be a single layer structure or multiple layer structure. In this embodiment, the second dielectric layer43includes a bottom layer41and a top layer42, wherein the bottom layer41and the top layer42are made of different materials, such as silicon nitride and silicon oxide respectively, but not limited thereto; the materials can be adjusted according to the actual requirements. Then, a plurality of second patterned photoresists44is formed on the second dielectric layer43, wherein the second patterned photoresists44are disposed correspondingly to the fin structures26below that are predicted to remain in the following steps. The other fin structures26not corresponding to the second patterned photoresist44are defined as the second dummy fin structures26B, which will be removed in the following steps. It is worth nothing that, the width of each second patterned photoresist44is preferably larger than the width of the first patterned photoresist34to entirely protect the fin structures26disposed below from unwanted damages. In this embodiment, the width of the second patterned photoresist44is about 86 nm, but not limited thereto; the size and the amount of the second patterned photoresist44can be adjusted according to the actual requirements. In addition, since the second patterned photoresists44are only disposed correspondingly to the fin structures26that are predicted to remain, the amount of second patterned photoresists44is less than the amount of first patterned photoresists34and the pattern density of the first patterned photoresists34is higher than a pattern density of the second patterned photoresists44.

A second etching process E2is then performed to etch the region that is not covered by the second patterned photoresist44, including etching the second dielectric layer43, the cap layer30, the second dummy fin structures26B, the isolating layer28and parts of the short wide fin structures36. As shown inFIG. 8, after the second etching process E2is performed, only the fin structures26disposed correspondingly to the second patterned photoresists44remain and the second dummy fin structures26B are removed. It is worth noting that, in the present invention, the amount of fin structures26on the substrate10has been reduced after the first etching process E1is performed, therefore even though the second patterned photoresists44are wider, it will not affect other adjacent fin structures26and the second patterned photoresist44can entirely protect the fin structures26disposed below. In addition, after the second etching process E2is performed, some of the short wide fin structures36may not be removed completely and some portions of the short wide fin structures36still remain on the substrate10, thereby forming a plurality of bumps37arranged in intervals on the substrate10, but not limited thereto.

As shown inFIGS. 9˜10, an isolating layer48is disposed on the substrate10and entirely covers the short wide fin structures36, the isolating layer28, the fin structures26and the cap layer30. A planarizing process is then performed to expose the cap layer30, and to level the top surface of the cap layer30with the top surface of the isolating layer48. An etching back process is then performed to remove the cap layer30in the isolating layer and to expose the surface of the fin structures26.

Finally, as shown inFIG. 11, a thermal oxidation process can be performed to form a barrier layer (not shown) on the surface of the fin structures26. Then, a high-k layer51, a work function metal layer52and a conductive layer53are formed on the fin structures26in sequence; a planarizing process is performed to level the top surface of the conductive layer53with the top surface of the isolating layer48. The high-k layer51, the work function metal layer52and the conductive layer53form a gate structure disposed on the fin structures26. In this embodiment, the high-k layer51can be selected from the group of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3) tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) and barium strontium titanate (BaxSr1-xTiO3, BST). The work function metal layer52can be selected from the group of titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminum (TiAl) and aluminum titanium nitride (TiAlN). The conductive layer53manly comprises polysilicon or metals with high conductivity, such as gold, silver, copper, tungsten or the alloys thereof, but not limited thereto.

According to the method of the present invention, the final fin structures shown inFIGS. 10˜11comprise: a substrate10, at least one fin structure26(it may be deemed as a long thin fin structure), at least one short wide fin structure36disposed between the substrate10and the fin structures26, an isolating layer48disposed on the sidewall of the short wide fin structure36and an isolating layer28disposed between the fin structures26and the isolating layer48and disposed on the short wide fin structure36, wherein the sidewall of the isolating layer48is trimmed with the sidewall of the short wide fin structure36.

In addition, in this embodiment, the present invention further comprises a gate structure disposed on the fin structures26, wherein the gate structure includes a high-k layer51, a work function metal layer52and a conductive layer53.

Besides, in this embodiment, the isolating layer28or the isolating layer48comprises silicon oxide or silicon nitride, but not limited thereto.

Besides, the surface of the substrate10is a non-planar surface; a plurality of bumps37are disposed on the substrate10and arranged in intervals. The other material properties and components are similar to those of the first preferred embodiment detailed above and will not be redundantly described.

In summary, compared with conventional processes that remove parts of the fin structures through only one photo-etching process, the method of the present invention uses two different etching processes to remove parts of the fin structures. After the first etching process is performed, the density of the fin structure on the substrate is reduced, therefore, the required fin structure can remain precisely after the second etching process is performed, thereby reducing the difficulty of the process, and avoiding spending a lot of effort on the positioning process.