Electrical package including bimetal lid

Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, (ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to an electrical package, and more specifically, to an electrical package that includes a bimetal lid for reducing delamination of a thermal interface material (hereinafter, “TIM”) occurring from thermal stress.

BACKGROUND OF THE INVENTION

FIG. 1shows an example of a conventional electrical package for high-end servers. Electrical package10includes organic substrate1, semiconductor chip2electrically connected to the organic substrate using a plurality of solder balls (bumps)3, lid4for encapsulating semiconductor chip2on organic substrate1.

InFIG. 1, the inner surface of the central part of lid4is connected to the surface of semiconductor chip2via TIM5. The inner surface of the outer part of lid4is hermetically connected to the surface of organic substrate1using sealing materials6. Further, underfill7is formed between semiconductor chip2and the surface of organic substrate1.

Since the coefficient of thermal expansion (CTE) of each component in package10is different, thermo-mechanical stress occurs within package10, and also warpage of organic substrate1occurs during the thermal cycle/stress. As a result, delamination of TIM5tends to occur, especially in corner part8. When the TIM delamination occurs, the temperature of semiconductor chip2increases because of insufficient cooling performance, and semiconductor chip2may not operate properly.

Therefore it is necessary to reduce the TIM delamination occurred under the thermal cycle/stress in order to maintain the semiconductor chip performance/reliability.

SUMMARY OF THE INVENTION

The present invention provides an electrical package which includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate. In the electrical package, an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and the lid has a bimetal structure including at least two different metals.

The present invention also provides a circuit module. The circuit modules includes: at least one electrical package mounted on a circuit board using ball grid array (BGA).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Through the more detailed description of some embodiments of the present invention in the accompanying drawings, the above and other objects, features and advantages of the present invention will become more apparent, wherein the same reference generally refers to the same components in the embodiments of the present invention.

Referring toFIG. 2, a cross-sectional diagram of an electrical package of one embodiment of the present invention is shown. Electrical package100includes organic substrate10, semiconductor chip20electrically connected to the organic substrate10using a plurality of solder balls (bumps)30, lid40for encapsulating semiconductor chip20on organic substrate10. Each bump30contains metal (e.g., Cu) pillar301and solder ball302. Lid40is also called a thermal spreader. Lid40has a bimetal structure including at least two different metals. InFIG. 1, lid40consists of two metal layers401,402.

Inner surface401of the central part of lid40is connected to the surface of semiconductor chip20via TIM50. TIM50can include: silicone grease, heat conduction sheet, or perpendicular orientation carbon nanotube (CNT). Inner surface401of the outer part of lid40is hermetically connected to the surface of organic substrate10using sealing materials60. Sealing materials60can include thermosetting resin. Further, underfill70is formed between semiconductor chip20and the surface of organic substrate10. Underfill70can include epoxy resin with fillers.

FIG. 3shows an example of a cross section of organic substrate10. Organic substrate10includes core layer101which is sandwiched by two buildup layers102,103. Core layer101includes organic materials and a plurality of conductive vias to electrically connect between buildup layers102,103. Core layer101further includes metal layers and composite layers with dielectric materials enclosing glass fiber cloth. Buildup layers102,103include a plurality of wiring layers and dielectric layers. The wiring layers include patterned metal layer in a dielectric material. The dielectric layers are in between the wiring layers.

The semiconductor chip20may include a silicon chip or other semiconductor chip such as IC, LSI, VLSI, or MPU. The material of the semiconductor chip is not limited to specific types. Lid40of electronic package100has bimetal structure401,402(shown inFIG. 2) so that lid40is transformed to follow warpage of organic substrate10under the thermal stress/cycle. In other words, the lid's warpage is dependent on the temperature in the thermal cycle/stress. For example, lid40bends into the upper part when organic substrate10bends into the upper part. On the contrary, lid40bends into the bottom when organic substrate10bends into the bottom. As a result, stress to TIM50decreases and the TIM delamination can be reduced, especially delamination at the edge of TIM50.

Metal layers401,402of lid40may be made of a combination of Copper (Cu)401and Cu alloy402. Cu alloy402may include Chromium Copper (CuCr) or Zirconium Copper (ZrCu) because CuCr and ZrCu have high thermal conductivity as shown in Table1ofFIG. 8. Also, Tungsten (W) and Nickel (Ni) are usable for metal layer402. Further, other candidate metals may be selected from Table 1 ofFIG. 8.

FIG. 4shows a cross-sectional diagram of other electrical package of one embodiment of the present invention. InFIG. 4, electrical package100further includes cooling module80formed on lid40(402) via TIM55. TIM55may include silicone grease, heat conduction sheet, or perpendicular orientation CNT. Other constitution inFIG. 4is the same as constitution ofFIG. 2. Cooling module80is used to let heat generation of semiconductor chip20go to the outside of the electrical package100. For example, cooling module80may include a heat sink. The warpage of the top surface of lid40(402) may be larger than conventional lid4consisted of Cu inFIG. 1. However, if TIM55is thicker than TIM50, it is considered that the large warpage of the top surface of lid40(402) can be managed by the thick TIM55.

FIG. 5shows a cross-sectional diagram of a circuit module of one embodiment of the present invention. Circuit module200is an example of a circuit module using electrical package100. InFIG. 5, electrical package100is mounted on circuit board110. Circuit board100is also called a mother board. For example, circuit board100may include a printed circuit board (PCB). Electrical pads12on the surface of organic substrate10of electrical package100are connected with electrical pads112on the surface of circuit board110using ball grid array (BGA)114.

FIG. 6shows a cross-sectional diagram of the other lid of one embodiment of the present invention. Lid40has three metal layers401,402,403. Metal layer402is sandwiched by metal layers401,403. For example, metal layer402includes Cu alloy such as CuCr or ZrCu and metal layers401,403include Cu. The bimetal structure of lid40shown inFIGS. 2-6may be formed by the conventional metal rolling process. The metal rolling process is a metal forming process in which metal stock is passed through one or more pairs of rolls to reduce the thickness and to make the thickness uniform of the metal stock.

FIG. 7is a cross-sectional diagram of the other lid of one embodiment of the present invention. Lid40has two metal layers404,405. Metal layer405is only formed in the central part of lid40parallel to the surface of semiconductor chip20. Metal layer405is formed to cover at least the area over the surface of semiconductor chip20. Metal layer405includes CuCr, ZrCu, W, or Ni and metal layer404includes Cu.

The embodiment of the present invention has been described with reference to the accompanying drawings. However, the present invention is not limited to the embodiment. The present invention can be carried out in forms to which various improvements, corrections, and modifications are added based on the knowledge of those skilled in the art without departing from the purpose of the present invention.