Method of fabricating semiconductor chips with silicide and implanted junctions

A method of fabricating a semiconductor device includes the steps of providing a semiconductor chip (10) with a memory area (22) and a logic area (26). The memory area (22) and the logic area (26) each have gate structures (50) formed therein. The step of sequentially forming silicided junctions (44) in the logic area (26) and implanted junctions in the memory area (26) is also included.

BACKGROUND 
1. Technical Field 
This disclosure relates to semiconductor chips and more particularly, to a 
method for creating silicided junctions and implanted junctions on the 
same semiconductor chip. 
2. Description of the Related Art 
Embedded memory chips have increasingly become more vital to high 
technology components. Embedded memory chips such as embedded dynamic 
random access memory (DRAM), refer to semiconductor chips that include 
logic circuits with memory arrays "embedded" therein. Embedded DRAM chips 
improve data transfer rates as well as increase bandwidth for the chip. 
Embedded DRAM chips have many applications in multimedia and 
communications. 
Although embedded DRAM chips are desirable they are relatively more 
difficult to manufacture. Logic circuits generally require silicided 
junctions while memory arrays utilize implanted junctions. These two types 
of junctions are created using two different processes that are somewhat 
difficult to incorporate into a single process sequence. For example, the 
higher reaction temperatures needed to form the silicided junctions can 
present problems with respect to the integrity of the implanted junctions. 
Further, the silicide process and the implant process must be integrated 
without unduly complicating the process sequence or unduly increasing the 
number of thermal cycles required for the overall process. Ion implanted 
junctions are formed by bombarding the silicon surface with dopant ions. 
Ion implanted junctions do not have low sheet resistance as do silicided 
junctions. However, ion implanted junctions have controlled subsurface 
depth dopant concentrations. 
Silicided junctions are formed in order to reduce sheet resistance over the 
semiconductor junction. A refractory metal is deposited on the surface of 
the semiconductor chip over a layer containing silicon. The refractory 
metal, for example, titanium or cobalt is reacted with the underlying 
layer containing silicon to form a silicide. The silicide formation at the 
silicon surface is determined by the metal silicon interface. The 
deposition of a highly pure metal and a clean surface are required for the 
silicide reaction. Any residues or contaminants lead to non-uniform 
silicide layers. 
Therefore, a need exists for a semiconductor device in which silicided 
junctions and implanted junctions can be formed on the same semiconductor 
chip in a single process sequence. 
SUMMARY 
A method of fabricating a semiconductor device comprising the steps of 
providing a semiconductor chip with a memory area and a logic area, each 
having gate structures formed therein, and sequentially forming silicided 
junctions in the logic area and implanted junctions in the memory area. 
In particular, one method of fabricating a semiconductor device includes 
the steps of providing a semiconductor chip with a memory area and a logic 
area, etching a first dielectric layer to remove the first dielectric 
layer from the logic area and to pattern the first dielectric layer in the 
memory area, etching a second dielectric layer disposed beneath the first 
dielectric layer in both the memory area and the logic area to form gate 
structures and expose a gate oxide layer containing silicon below the 
second dielectric layer, depositing a spacer layer on the memory area and 
the logic area removing the spacer layer from the logic area, depositing a 
layer of refractory metal on the memory area and the logic area, the 
refractory metal being in contact with the exposed area of the gate oxide 
layer, annealing the layer of refractory metal to form a metal silicide 
with the exposed area of the gate oxide layer and removing the refractory 
metal layer and the spacer layer. 
Embodiments of the invention include the first dielectric layer being 
silicon nitride and the second dielectric layer being polycrystalline 
silicon. The refractory metal layer may be titanium or cobalt and the 
metal silicide is a compound based on the metal used. A transition region 
may be introduced that separates the logic area and the memory area and 
the step of reserving a transition area between the logic area and the 
memory area set aside a separation for the logic area from the memory area 
by between 0.3 .mu.m and 0.5 .mu.m. Further, a portion of the spacer layer 
may remain disposed laterally on the gate structures for protection of the 
gate structures during implantation.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
The present invention relates to an integrated circuit (IC) and the 
formation thereof. In particular, the invention relates to an IC that 
comprises both silicided and ion implanted junctions. Such IC, for 
example, includes a merged memory-logic circuit such as a embedded 
DRAM-logic, a RAM, a DRAM (DRAM), a synchronous DRAM (SDRAM), or a static 
RAM (SRAM). The IC can also be a logic device such as a programmable logic 
array (PLA) or an application specific ICs (ASIC), or any circuit device. 
Typically, numerous ICs are fabricated on a semiconductor substrate, such 
as a silicon wafer, in parallel. After processing, the wafer is diced in 
order to separate the ICs into a plurality of individual chips. The chips 
are then packaged into final products for use in, for example, consumer 
products such as computer systems, cellular phones, personal digital 
assistants (PDAs), and other electronic products. 
In accordance with one embodiment of the invention, the IC comprises an 
embedded DRAM-logic device. The silicided junctions for employed for logic 
circuit components and implanted junctions are employed for memory array 
components. The invention provides for the formation of silicided and 
implanted junctions in a single process sequence, which can be used to 
form both types of junctions on a single chip. 
Referring now in specific detail to the drawings in which like reference 
numerals identify similar or identical elements throughout the several 
views, and initially to FIG. 1, a semiconductor chip 10 is formed from a 
silicon substrate 12. The substrate, for example, comprises a silicon 
wafer. Other semiconductor substrates such as gallium arsenide, germanium, 
silicon on insulator (SOI), or other semiconductor materials are also 
useful. The substrate, for example, may be lightly or heavily doped with 
dopants of a pre-determined conductivity to achieve the desired electrical 
characteristics. The substrate may comprises device features (not shown) 
formed in a portion thereof, such as trench capacitors used in memory 
cells. 
As shown, a gate oxide layer 14 is formed on silicon substrate 12. A layer 
of polycrystalline silicon 16 is formed on gate oxide layer 14 and a layer 
of dielectric material 18, such as, for example, silicon nitride is formed 
on layer of polycrystalline silicon 16. A resist mask 20 is placed at 
desired locations in a predetermined pattern in a memory array area 22 to 
protect masked regions from etching in later processing steps. A 
transition area 24 is needed to isolate memory array area 22 from a logic 
area 26. Layer of silicon nitride 18 is not needed in a logic area 26 and 
therefore no resist is applied. Since transition region 24 is used for 
isolation between memory array 22 and logic area 26, the silicon nitride 
layer 18 is desirably maintained for processing in later steps. Hence, 
resist mask 20 is applied to transition region 24. Transition region 24 
separates logic area 26 from memory array 22 by a distance of, for 
example, between 0.3 .mu.m and 0.5 .mu.m. 
Resist mask 20 is patterned in memory array 22 to form transistor gates. 
The layer of silicon nitride 18 is removed in areas of the surface absent 
of resist mask 20 using any suitable technique known to those skilled in 
the art such as, for example, dry etching. The exact conditions used in 
the dry etch process will depend on a number of factors. In one 
embodiment, the dry etching step includes exposing the surface of 
semiconductor chip 10 to CF.sub.4, CHF.sub.3 or Ar gas. This process 
exposes layer of polycrystalline silicon 16 in the areas absent resist 
mask 20. Silicon nitride layer 18 is also removed from logic area 26 by 
this etching process. Resist mask 20 is removed after etching. 
Referring to FIG. 2, transition area 24 now includes a silicon nitride cap 
30 which separates memory array 22 from logic area 26. The exposed areas 
of polycrystalline silicon layer 16 are to be etched. A resist mask 28 is 
applied to logic area 26 to protect polycrystalline silicon layer 18. 
Silicon nitride layer 18 acts as a mask to protect polycrystalline silicon 
layer 16 in memory array 22. Any suitable technique known to those skilled 
in the art can be used to remove polycrystalline silicon layer 16 in 
memory array 22 in those areas absent silicon nitride layer 18. In one 
embodiment, a dry etching is employed. As with the previous etching step, 
the exact parameters employed during the etch will depend on a number of 
factors such as, for example, the thickness of layer 16 and the nature of 
the masking materials. Typically, however, the dry etching process 
utilizes HCl gas. Resist mask 28 is removed after etching. After etching 
of the poly layer, ion implantation is performed to create doped regions 
within substrate 12 to form implanted junctions in memory array 22. The 
implant is self aligned because the nitride cap layer 18 and resist 28 
serve as an implant mask. Dopants include, for example, arsenic, boron, or 
phosphorus. 
Referring to FIG. 3, a resist mask 32 is applied in a desired pattern to 
logic area 26. Memory array 22 is protected by resist mask 34 to prevent 
further etching of the polycrystalline silicon layer 16 during the removal 
of the unmasked portion of layer 16 in the logic area 26. Again, any 
suitable technique known to those skilled in the art can be utilized to 
remove the unmasked portion of polycrystalline silicon layer 16 where dry 
etching is used. Typical etching techniques include using HCl gas. 
Polycrystalline silicon layer 16 is removed to expose gate oxide layer 14 
in logic area 26. Resist mask 32 and resist mask 34 are removed subsequent 
to etching. 
Referring to FIG. 4, a spacer layer 36 is deposited over semiconductor chip 
10. Memory array 22, transition region 24 and logic area 26 are covered by 
spacer layer 36. Spacer layer 36 can be made from any dielectric material 
such as, for example, silicon nitride. Spacer layer 36 is typically 
applied using chemical vapor deposition (CVD) or low pressure chemical 
vapor deposition (LPCVD). A resist mask 38 is developed on memory array 22 
which prepares spacer layer 36 to be removed from logic area 26. 
Referring to FIG. 5, spacer layer 36 is etched away from logic area 26 
using any suitable technique, such as the previously used process for 
silicon nitride etching using a resist to mask the array region. A 
byproduct of the etching process leaves spacers 42 formed laterally on 
dielectric layers. Logic area 26 has spacers formed laterally on the 
remaining portions of polycrystalline silicon layer 16, and transition 
region 24 adjacent to logic area 26 has spacer 42 formed laterally on both 
polycrystalline silicon layer 16 and silicon nitride layer 18. A 
refractory metal layer 40 is deposited over the entire surface of 
semiconductor chip 10. Refractory metal layer 40 may be made for example 
from titanium or cobalt. Other refractory metals are also useful. 
Deposition of refractory metal layer 40 is within the purview of one 
skilled in the art. Thus, for example, refractory metal layer 40 may be 
sputtered or epitaxially grown on the surface of semiconductor chip 10. 
Since spacer layer 36 is etched away in logic area 26, gate oxide layer 14 
is exposed in regions 44. When refractory metal layer 40 is deposited, it 
is in contact with gate oxide layer 14. Gate oxide layer 14 is comprised 
of a silicon-containing compound, such as silicon dioxide which will react 
with refractory metal layer 40. 
Semiconductor chip 10 is subjected to rapid thermal annealing (RTA). This 
process consists of heating semiconductor chip 10 to between 750 and 900 
degrees C. Inert gas such as helium or argon is introduced to aid in the 
prevention of surface reactions on the surface of semiconductor chip 10. 
RTA causes refractory metal layer 40 to react with gate oxide layer 14 to 
form silicided junctions in region 44. Silicided junctions 44 may have 
titanium silicide, for example, therein. After RTA, refractory metal layer 
40 is removed using known techniques. Where the refractory metal layer 40 
is cobalt or titanium, a wet etching process using nitric acid can be used 
to dissolve and remove refractory metal layer 40. 
Referring to FIG. 6, spacer layer 36 is removed from memory array 22. Prior 
to etching spacer layer 36, a resist mask 46 is developed in logic area 26 
to protect that region from the etching process to follow. A dry etching 
process can be used similar to the dry etching process used in the 
description of FIG. 5 to remove spacer layer 36 from memory array 22. 
Silicided junctions 44 are shown through gate oxide layer 14. 
Referring now to FIG. 7, spacer layer 36 as described in FIG. 6 is etched 
away, but leaves spacers 48 laterally disposed on silicon nitride layer 18 
and polycrystalline silicon layer 16. Gate structures 50 include the 
raised dielectric portions remaining on semiconductor chip 10. Spacers 48 
aide in protecting these gate structures 50 during later implantation 
processes. 
The process described herein provides a semiconductor chip 10 with both a 
memory array 22 and logic area 26, including both silicided and implanted 
junctions manufactured into the same semiconductor chip 10. 
It is also contemplated that further processing of the chip can be 
performed. Such further processing includes, for example, ion implantation 
to dope the regions adjacent to gate structures 50 to form diffusion 
areas. Ion implantation processes are carried out to increase the doping 
in junction areas between gate structures 50. Ion implantation includes 
p-doping and n-doping. Areas to be p-doped are masked during n-doping, and 
n-doped areas are masked during p-doping. Barrier deposition is completed 
on diffusion areas to serve as a diffusion barrier for contact metals 
which are subsequently deposited. Barrier deposition also provides a 
conductive path through diffusion area to contacts. Later, a passivation 
layer (not shown) can be deposited over the surface of semiconductor chip 
10. The passivation layer is preferably formed from borophosphosilicate 
glass (BPSG). Contact openings (not shown) can subsequently be formed in 
this passivation layer. 
Having described embodiments of a novel for a semiconductor chip having 
implanted and silicided junctions in a single process sequence (which are 
intended to be illustrative and not limiting), it is noted that 
modifications and variations can be made by persons skilled in the art in 
light of the above teachings. It is therefore to be understood that 
changes may be made in the particular embodiments of the invention 
disclosed which are within the scope and spirit of the invention as 
delined by the appended claims. Having thus described the invention with 
the details and particularity required by the patent laws, what is claimed 
and desired protected by letters patent is set forth in the appended 
claims.