Semiconductor memory device, storage system, and computer

A semiconductor memory device includes, in addition to a first switching circuit with which a data system signal line between a plurality of semiconductor memory portions and a memory controller is branched, a second switching circuit with which a non-data system signal line between the plurality of semiconductor memory portions and the memory controller is branched, and the first and second switching circuits share a switching signal line.

TECHNICAL FIELD

This invention generally relates to connection between a plurality of semiconductor memory portions and a memory controller.

BACKGROUND ART

A nonvolatile memory device (hereinafter, referred to as an NVM device) including a plurality of nonvolatile memory chips (hereinafter, referred to as an NVM chip) has been known as a semiconductor memory device including a plurality of semiconductor memory portion.

Recently, a demand for large capacity storage systems, using NVM devices (for example, flash memory devices) featuring a low cost and high-density packaging, has been increasing. A larger number of NVM chips are required for implementing a larger capacity storage system.

A larger number of NVM chips coupled to a memory controller directly relates to a larger number of signal lines for the NVM chips. Examples of the signal line for the NVM chip include a data system signal line, a chip enable (CE) signal line, and a ready/busy (R/B) signal line. A data system signal is transmitted on the data system signal line. The data system signal includes a command, an address, a write enable (WE), read enable (RE), command latch enable (CLE), address latch enable (ALE), and I/O data (write (program) or read target data). A chip enable (CE) signal for selecting a NVM chip is transmitted on the CE signal line. A ready busy (R/B) signal indicating an operation state of an NVM chip is transmitted on the R/B signal line.

The increase in the number of signal lines for the NVM chip involves at least one of the following problems.(1) The number of pins of the memory controller increases. This results in an increased size of the memory controller, which might result in an increased cost of the memory controller.(2) The signal lines occupy a large package occupying area. This results in an increased size of the NVM device (for example, a substrate).(3) The packaging density of the signal lines increases to render the packaging more difficult. This results in an increased packaging steps and an increased packaging cost.

Thus, the number of signal lines between the plurality of NVM chips and the memory controller is preferably reduced. PTL 1 discloses a technique for achieving a smaller number of signal lines. PTL 1 discloses the following configuration: “a memory system includes a NAND memory incorporating a plurality of chips and a NAND controller112that controls the NAND memory. A bus switch is provided that switches the connection of the signal lines between a plurality of chips incorporated in the NAND controller112and the NAND memory. Thus, the load capacity of the signal line at the time of accessing the NAND memory10can be reduced, whereby a signal delay can be prevented”.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

PTL 1 uses the bus switch for the data system signal line so that the number of data system signal lines can be reduced. However, the total number of signal lines needs to be reduced even further. More specifically, in PTL 1, the number of non-data system signal lines (signal lines other than the data system signal lines), at least including the R/B signal lines and the CE signal lines for example, is not reduced.

For example, a plurality of R/B signals, each coupled to a corresponding one of the plurality of NVM chips, may be integrated to reduce the number of R/B signal lines. Unfortunately, this compromises operation multiplicity (the number of NVM chips that can operate in parallel) of the NVM chips, and thus leads to lower performance. Furthermore, a failed R/B signal would be undetectable in this configuration.

The bus switch may be provided also for the non-data system signal lines to reduce the number of non-data signal lines. Unfortunately, simply providing the bus switch for the non-data system signal lines leads to another problem related to signal lines. More specifically, a signal line (switching signal line) for a switching signal, for switching the NVM chip as the coupling destination, is required for each of the bus switch for the data system signal line and the bus switch for the non-data system signal line. Thus, the number of switching signal lines increases.

Semiconductor memory devices other than the NVM device may also be plagued by these problems.

Solution to Problem

To solve the problems described above, configurations described in the appended claims can be employed, for example. An example of means for solving the problems described is as follows.

Specifically, a semiconductor memory device includes, in addition to a first switching circuit with which a data system signal line between a plurality of semiconductor memory portions and a memory controller is branched, a second switching circuit with which a non-data system signal line between the plurality of semiconductor memory portions and the memory controller is branched, and the first and second switching circuits share a switching signal line.

Advantageous Effects of Invention

Not only the number of data system signal lines but also the number of non-data system signal lines can be reduced without increasing the number of switching signal lines. Thus, the number of pins of the memory controller can be reduced, and the package occupying area or the packaging density of the signal lines can be reduced.

DESCRIPTION OF EMBODIMENTS

Some embodiments are described below with reference to the drawings. A semiconductor memory device in the embodiments described below is an NVM device. Alternatively, the present invention may be applied to a semiconductor memory device other than the NVM device (semiconductor memory other than the NVM).

In the following description, individual reference numerals of the same types of components may be referred to in order to describe them in a distinguished manner, whereas only apart of the reference numerals common to them may be referred to in order to describe them without distinguishing one from another. For example, “chip61” is referred to in order to describe chips (dies) without distinguishing one from another, whereas “chip61A” and “chip61B” are referred to in order to distinguish one from another.

FIG. 1illustrates an overview of an NVM device according to an Embodiment 1.

An NVM device (for example, a substrate)100includes an NVM controller (hereinafter, referred to as a controller)200and an NVM300.

The controller200is an example of a memory controller, and controls writing (programing) of data to the NVM300and reading of data from the NVM300. For example, the controller200transmits a data write (program) command or a data read command to the NVM300. Data write/read (write or read) may be performed in response to an I/O request from an upper level device (not illustrated) or without the I/O request from the upper level device. For example, write/read performed without the I/O request from the upper level device is write/read performed in internal processing such as reclamation processing or refresh processing. The controller200includes a plurality of pins181. Each signal line is coupled to two or more pins181in the plurality of pins181. The controller200may be any one of an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), a CPU (Central Processing Unit), and a GPU (Graphics Processing Unit). The “upper level device” of the NVM device100may be any type of device that transmits an I/O request to the NVM device100. For example, when the NVM device100is used as an external storage device for a computer, the upper level device may be the computer. When the NVM device100is used as a storage device embedded in a computer, the upper level device may be a processor (for example, a CPU) in the computer. When the NVM device100is used as a storage device in a storage system, the upper level device maybe a storage controller in the storage system.

The NVM300is an example of a semiconductor memory, and includes two or more (for example, four) NVM chips (dies)61. The NVM chip (hereinafter, simply referred to as “chip” in some cases)61is an example of an NVM portion. The NVM300uses a data system signal and also uses a non-data system signal such as an R/B signal, and may be, for example, any one of a flash memory, a PRAM (Phase Change Random Access Memory), an ReRAM (Resistance Random Access Memory), and an FeRAM (Ferroelectric Random Access Memory). In the present embodiment, the NVM300is a flash memory (for example, a NAND flash memory).

In the present embodiment, the controller200and the NVM300are coupled to each other in 1 to 1 relationship. However, the present invention is not limited to this configuration, and a configuration may be employed in which the controller200and the NVM300are coupled to each other in 1 to n (n being any integer of 1 or more) relationship.

A signal line that couples the controller200to the NVM300includes a data system signal line and a non-data system signal line. An R/B (ready/busy) signal line is illustrated as the non-data system signal line. The R/B signal line indicates a signal representing an operation state of the chip61. The R/B signal according to the present embodiment is a 4-bit signal. In the present embodiment, other types of non-data system signal lines are not integrated by a switching circuit or the like. For example, four chip enable (CE) signal lines may each be coupled to a corresponding one of four chips61A to61D and to the controller200.

A first switching circuit40A and a second switching circuit40B are provided between the controller200and the NVM300. A data system signal line600M from the controller200is branched by the first switching circuit40A into four data system signal lines600A to600D that are respectively coupled to the four chips61A to61D. Similarly, an R/B signal line700M from the controller200is branched by the second switching circuit40B into four R/B signal lines700A to700D that are respectively coupled to the four chips61A to61D. In the present embodiment, the switching circuits40A and40B are each a (1:m) branching switching circuit (m being an integer of 2 or more), with m not being limited to 4.

The controller200also has a switching signal line80. A signal for controlling a coupling destination of the switching circuit40, as a switching signal input to the switching circuit40, is transmitted on the switching signal line80. The first and second switching circuits40A and40B share the switching signal line80(switching signal). Thus, the same switching signal is input to both the first and second switching circuits40A and40B. This means that the switching of the coupling destination of one of the first and second switching circuits40A and40B leads to (for example, at the same time causes) the switching of the coupling destination of the other one of the first and second switching circuits40A and40B to the same chip. In other words, a single switching of the coupling destination of the controller200involves switching of both the switching circuits40A and40B corresponding to the same switching signal line. A single switching signal with two types (ON/OFF) of a signal level can cover a 1:2 branching switching circuit. In the present embodiment, the switching circuit40is a 1:4 branching switching circuit. Thus, two switching signals are input to a single switching circuit40(two switching signal lines80A and80B are coupled to a single switching circuit40).

An overview of an example of signal transmission (transmission of the data system signal and the R/B signal) according to Embodiment 1 is described.

First of all, the controller200sequentially switches the coupling destination of the second switching circuit40B, and receives the R/B signal from each of the chips61A to61D. Thus, the controller200checks whether the operation state of each of the chips61A to61D is a ready state (a state of waiting for a command from the controller200).

A case where the transmission destination chip61for the data system signal is the chip61A is described. The controller200uses a CE signal line of the transmission destination chip61A to select the transmission destination chip61A. The controller200uses the switching signal to switch the coupling destination of the first switching circuit40A to the transmission destination chip (selected chip)61. Then, the controller transmits the data system signal.

When the coupling destination of the first switching circuit40A switches to the transmission destination chip61A, the coupling destination of the second switching circuit40B is also switched to the transmission destination chip61A, because the first and second switching circuits40A and40B share the switching signal. Thus, in a period in which the coupling destination of the first switching circuit40A is the transmission destination chip61A, only the R/B signal of the transmission destination chip61A, from among the R/B signals of the chips61A to61D, is input to the controller200. Thus, the R/B signals of the chips61B to61D, different from that of the transmission destination chip61A, are not input to the controller200.

Thus, after the data transmission to the transmission destination chip61A, the controller200checks whether the operation state of the transmission destination chip61A has transitioned from the ready state to a busy state (a state where the NVM300is processing data). In other words, after the data transmission to the transmission destination chip61A, the controller200waits until the operation state of the transmission destination chip61A transitions from the ready state to the busy state. After confirming that the busy state has been achieved, the controller200can perform a similar transmission to any one of the other chips61B to61D. For example, in a flash memory, a time period required for checking the R/B signal of a single chip61is sufficiently shorter (several tens of nanoseconds (ns)) than an operation time period of the chip61(for example, a read operation (for example, several tens to hundreds of microseconds (μs)), a program operation (several milliseconds (ms)), and an erase operation (for example, several ms)). Thus, a bus occupation time period (more specifically, a time period in which an operation state checking target chip is selected as the coupling destination, and thus the other chips cannot be selected) is short. Thus, the common switching signal can be used without largely compromising the performance.

As illustrated inFIG. 1, in the present embodiment, R/B signal lines700between the NVM300and the second switching circuit40B are independently provided to respective chips61. More specifically, the R/B signal lines700A to700D independent from each other and extending from the chips61A to61D are coupled to the second switching circuit40B respectively. Thus, the operation state of each chip61can be checked with an oscilloscope or the like, whereby maintainability and reliability of the NVM device100can be ensured. The NVM300, which is a flash memory for example, has a risk that a voltage value of the R/B signal not operating properly might be fixed. Thus, it may be important that the state of each R/B signal can be checked in terms of maintainability and reliability. In view of this, the controller200may include a timer circuit for measuring an elapsed time period after the transition of the signal level of the R/B signal. When the elapsed time period exceeds a predetermined time period with no transition of the signal level of the R/B signal detected, the controller200may determine that the failure has occurred and report the failure.

FIG. 2is an example of a timing chart related to write processing (program processing).

FIG. 2is based on the following condition. The two chips61A and61B are each a write processing target (transmission destination chip (write target chip)). InFIG. 2, a first switching signal transmitted through the first switching signal line80A is denoted with “S0”, and a second switching signal transmitted through the second switching signal line80B is denoted with “S1”. InFIG. 2, a CE signal for the chip61A is denoted with “CE#_1”, and a CE signal for the chip61B is denoted with “CE#_2”. InFIG. 2, a data system signal for the chip61A is denoted with “D#_1”, and a data system signal for the chip61B is denoted with “D#_2”. InFIG. 2, an R/B signal from the chip61A is denoted with “R/B#_1”, and an R/B signal from the chip61B is denoted with “R/B#_2”.

For example, the operation state of each chip61is not recognized by the controller200in the initial state after being started for the first time or being restarted. Thus, the controller200may execute initial check processing for checking the operation state of each chip61. In the initial check processing, the controller200sequentially switches the coupling destination of the switching circuits40A and40B, and selects the coupling destination chip61with the CE signal, and thus receives the R/B signal from the chip61. Thus, the controller200recognizes the operation state of each chip61. Through this initial check processing, the controller200can detect that the operation state of each of the chips61A to61D is the ready state. Instead of executing the initial check processing involving all the chips with the common switching signal, the initial check processing may be executed on a chip-by-chip basis. The initial check processing on the chip-by-chip basis may be executed on a chip the operation state of which has not been detected. The initial check processing for a chip may be executed when the chip becomes a write/read target for the first time, before the write/read is performed.

An example is described where the transition of the operation state of the chip61A, which has been detected as being in the busy state, to the ready state has not been detected. In such a case, the controller200performs ready return check processing on the chip61A. Specifically, for example, the controller200selects the chip61A by using the CE signal (CE#_1) for the chip61A. When the chip61A is not the coupling destination of the switching circuits40A and40B, before (or after) the chip61A is selected, the switching signal for the chip61A is used (for example, by setting the signal level of each of the first and second switching signals (S0and S1) to Low level), and the coupling destination of the switching circuits40A and40B is switched to the chip61A. When the chip61A is the coupling destination of the switching circuits40A and40B and is in the selected state, the controller200can receive the R/B signal from the chip61A. When the R/B signal (R/B#_1) from the chip61A indicates the ready state, the controller200can detect that the chip61A is in the ready state.

When the chip61A has been detected to be in the ready state, the controller200can write data to the chip61A. Specifically, the controller200uses the CE signal (CE#_1) for the chip61A (sets the signal level of CE#_1to Low level) to select the chip61A (time point t1). Then, the controller200transmits a required data system signal (for example, command, address, and, write target data) to the chip61A. Then, the controller200waits until the operation state of the chip61A transitions to the busy state (time point t2to time point t3). In other words, the controller200maintains the state in which the chip61A is selected until the operation state of the chip61A transitions to the busy state (does not cancel the selected state). Thus, the controller200does not switch the coupling destination of the switching circuits40A and40B (the chip61A remains to be the coupling destination).

When the busy state of the chip61A is detected from. the R/B signal from the chip61A (time point t3), the controller200uses the CE signal (CE#_1) for the chip61A to cancel the selection of the chip61A (time point t4).

After the selection of the chip61A is cancelled (after the time point t4), the ready state may have been detected as the operation state of the chip61B in, for example, detection may have been already made in the initial check processing or in the ready return check processing for the chip31B. In such a case, the controller200can write data to the chip61B. Specifically, the controller200first uses the switching signal (for example, sets only the signal level of the second switching signal (S1) as one of the first and second switching signals (S0and S1) to High level) to switch the coupling destination of the switching circuits40A and40B to the chip61B (time point t5). Then, the controller200uses the CE signal (CE#_2) for the chip61B, (sets the signal level of the CE#_2to Low level) to select the chip61B (time point t6). Then, the controller200transmits a required data system signal (for example, command, address, and write target data) to the chip61B. Then, the controller200waits until the operation state of the chip61B transitions to the busy state (time point t7to time point t8). In other words, the controller200maintains the state where the chip61B is selected (does not cancel the selected state) until the operation state of the chip61B transitions to the busy state. Thus, the controller200does not switch the coupling destination of the switching circuits40A and40B (the chip61B remains to be the coupling destination). When the busy state of the chip61B is detected from the R/B signal from the chip61B (time point t8), the controller200uses the CE signal (CE#_2) for the chip61B to cancel the selection of the chip61B (time point t9).

The controller200needs to receive the R/B signal from the transmission destination chip61again, for recognizing that the operation of the transmission destination chip61has ended (the operation state has returned to the ready state from the busy state). For receiving the R/B signal from the transmission destination chip61again, the coupling destination of the switching circuits40A and40B needs to be switched to the transmission destination chip61and the transmission destination chip needs to be selected by using the CE signal for the transmission destination chip61. Thus, the ready return check processing described above needs to be executed on the transmission destination chip61.

An example is described in which the returning of the operation state of the chip61A, which has been detected to be the busy state at the time point t3, to the ready state has not been detected by the controller200. In such a case, the controller200executes the ready return check processing, described above, on the chip61A.

Specifically, for example, the chip61A is not in the selected state with the coupling destination of the switching circuits40A and40B being the other chip61B. Thus, the controller200first uses the switching signal to switch the coupling destination of the switching circuits40A and40B to the chip61A (time point t10). Then, the controller200uses the CE signal (CE#_1) for the chip61A to select the chip61A (time point t11). Thus, the controller200can receive the R/B signal from the chip61A. When the R/B signal indicating the ready state is received (time point t12), the controller200checks whether the R/B signal indicates the ready state. When the ready state is detected with the R/B signal, the controller200uses the CE signal (CE#_1) for the chip61A to cancel the selection of the chip61A (time point t13), because the returning to the ready state of the chip61A is detected.

The timing chart inFIG. 2is as described above.

The controller200may cancel the selection of the chip61A, when the R/B signal indicating the ready state is not received for a predetermined time period after the chip61A has been selected (from the time point t11) in the ready return check processing executed on the chip61A.

For example, the controller200may execute the ready return check processing on the chip61A when at least one of the following conditions is satisfied:(A) the CE signals for all of the other chips61B to61D, corresponding to the same switching signals as the chip61A, are in a selection cancel state (not in the selected state) (for example, not waiting for the busy state);(B) none of the other chips61B to61D, corresponding to the same switching signals as the chip61A, is a write/read target corresponding to an unprocessed I/O request accumulated in the controller200(for example a queue); and(C) the chip61A is the write/read target corresponding to the unprocessed I/O request accumulated in the controller200.

For example, in a case where the chip61A may not be the write/read target corresponding to the unprocessed I/O request accumulated in the controller200and moreover any one of the other chips61B to61D, corresponding to the same switching signals as the chip61A, may be the write/read target corresponding to the unprocessed I/O request accumulated in the controller200, then the controller200may prioritize the write, read, or ready return check processing on the chip as the write/read target, over the ready return check processing on the chip61A.

For example, the controller200may include a volatile or a nonvolatile storage area storing configuration information that may indicate association between a switching signal and the switching circuits and the chips the switching signal for which is the same. Thus, the controller200may identify two or more chips61and two or more switching circuits40corresponding to the same the switching signal, based on the configuration information.

FIG. 3illustrates an example of a timing chart related to read processing.

This figure is based on conditions similar to those forFIG. 2. For example, the two chips61A and61B are each a target (transmission destination chip (read target chip)) of the read processing. InFIG. 3, “W/R#” representing a W/R signal (write enable signal/read enable signal) not illustrated inFIG. 2, is additionally provided.

Specifically, selection/selection canceling for the chip61needs to be performed only once in the write processing on the chip61, but needs to be performed for a plurality of times in the read processing on the chip61.

More specifically, for example, a first selected period351of the chip61A starts when the chip61A is selected. A data system signal transmitted in the first selected period351does not include data on a read target. In the first selected period351, the controller200transmits a data system signal, including a command and an address and including no read target data, and waits for the busy state. When the busy state of the chip61A is detected, the selection of the chip61A is cancelled. Thus, the first selected period351ends.

Then, a second selected period352starts when the chip61A is selected again. When the ready state of the chip61A is detected in the second selected period352, the controller200uses the W/R signal (W/R#) to receive the read target data from the chip61A. After the read target data has been successfully received, the selection of the chip61A may be cancelled by the controller200. When the ready state is not detected for a predetermined time period after the second selected period352has started, the controller200may cancel the selection of the chip61A to end the second selected period352. Thereafter, the selected period related to the read processing on the chip61A may be repeated until the ready state is detected.

The timing chart inFIG. 3is as described above.

The following description can be made based onFIG. 2andFIG. 3, with the chip61A as an example. The ready return check processing on the chip61A is executed regardless of whether the processing executed immediately before is the write processing, or the first part of the read processing (a processing section involving the transmission of the data system signal including no read target data).

The following processing is executed when the write processing is the previous processing executed immediately before the ready return check processing on the chip61A. Specifically, when the ready state is detected in the ready return check processing, the controller200cancels the selection of the chip61A.

The following processing is executed when the first part of the read processing is the processing executed immediately before the ready return check processing on the chip61A. Specifically, when the ready state is detected in the ready return check processing, the controller200uses the W/R signal to receive the read target data from the chip61A, and then cancels the selection of the chip61A.

As described above, the ready return check processing on the chip61A is different between the case where the processing executed immediately before ready return check processing is the write processing and the case where the processing executed immediately before ready return check processing is the first part of the read processing.

Embodiment 1 is as described above. In Embodiment 1, the switching circuit for the CE signal line may be provided instead of the switching circuit for the R/B signal line. Thus, the switching circuit for the data system signal and the switching circuit for the CE signal line may share the switching signal.

In Embodiment 1, not only the switching circuit40A for the data system signal, but also the switching circuit40B for the R/B signal is provided, and the switching circuits40A and40B share the switching signal. Thus, not only the number of data system signal lines600, but also the number of R/B signal lines700can be reduced, without increasing the number of switching signal lines80. Thus, the number of pins181of the controller200can be reduced, and the package occupation area or a packaging density of the signal line can be reduced.

In Embodiment 1, the switching circuit using the same switching signal as the switching circuit40A for the data system signal does not correspond to a transmission system signal (a signal transmitted from the controller200) such as a data system signal, and corresponds to a reception system signal such as an R/B signal (an example of a signal for notifying the operation state of a chip). Thus, the common switching signal is used for the transmission system and the reception system. This means that transmission of a switching signal, for establishing connection with the transmission destination chip for the data system signal might lead to connection to a chip other than a chip from which the R/B signal is to be received. In other words, a common line is used for the R/B signal line and for a bus.

Thus, in Embodiment 1, the controller200waits for the busy state after the data system signal is transmitted to the chip (for example,61A) in the ready state. Then, the coupling destination can be switched from the chip61A to another chip (for example,61B) after the busy state of the chip61A is detected. The coupling destination may be switched to the other chip61B before the busy state of the chip61A is detected. However, in such a case, when the coupling destination is switched again to the chip61A and the ready state is detected, it cannot be determined whether the ready state is achieved by returning from the busy state, or has been unchanged with no transitioning to the busy state. All things considered, with the waiting for the busy state, the degradation of the reliability can be prevented in Embodiment 1.

In Embodiment 1, the initial check processing or the ready return check processing described above is executed. The time period required for checking the ready state is sufficiently shorter than, for instance, the time period required for read and the time period required for write (program) as described above. Thus, the performance is not largely compromised even when the common switching signal is used for the switching circuit40A for the data system signal and the switching circuit40B for the R/B signal.

Embodiment 2 is described. The difference from Embodiment 1 is mainly described, and the points that are the same as Embodiment 1 are not described or briefly described.

FIG. 4illustrates an overview of an NVM device according to Embodiment 2.

In an NVM device101according to Embodiment 2, a common (single) switching circuit40S serves as the switching circuit40A for the data system signal and the switching circuit40B for the R/B signal. In other words, the switching circuits40A and40B are each a part of the single switching circuit40S. The switching circuit40S also corresponds to (1:m) branching with m not being limited to 4.

In Embodiment 2, a package occupying area of the switching circuit can be reduced, and the number of components mounted on the NVM device101can be reduced. Thus, improvement of the maintainability of the NVM device101can be expected.

The size of the switching circuit40S may be the same as that of each of the switching circuits40A and40B. For example, the switching circuits40A,40B and40S may be the same parts. Specifically, for example, each of the switching circuits40A and40B may include an unused port (pin). More specifically, for example, the switching circuit40A may include enough unused ports for coupling the R/B signal lines700M and700A to700D. Thus, the switching circuit40A may have the unused port coupled to the R/B signal lines700M and700A to700D to implement the switching circuit40S according to Embodiment 2. Thus, when the single switching circuit40S is coupled to a signal line for a transmission system signal such as the data system signal and a signal line for a reception system signal such as the R/B system signal, the common switching signal is used for the transmission system signal line and the reception system signal line. When the common switching signal is used in the transmission system signal line and in the reception system signal line, the problem described in Embodiment 1 occurs. Still, such a problem is solved in Embodiment 1, and thus, the problem caused by coupling the transmission system signal line and the reception system signal line to the single switching circuit40S, as in Embodiment 2, has been solved.

Embodiment 3 is described. The difference from Embodiment 1 is mainly described, and the points that are the same as Embodiment 1 are not described or briefly described.

FIG. 5illustrates an overview of an NVM device according to Embodiment 3.

In an NVM device102according to Embodiment 3, at least a second switching circuit40C is an analog switching circuit, and a pullup resistor900for an R/B signal is incorporated in a controller201.

With the analog switching circuit, input/output of an analog signal can be performed, and input/output of a digital signal (1 or 0) cannot be performed. The R/B signal is an open drain output, and thus requires the pullup resistor outside the NVM300. However, when the second switching circuit40C is the analog switching circuit, the pullup resistor needs not to be provided to each of the R/B signal lines700A to700D. When the second switching circuit40C is a digital switching circuit, the pullup resistor may be required for each signal line coupled to the digital switching circuit so that which one of 1 or 0 (input value) is indicated by the input signal can be clearly recognized. If the second switching circuit40C is the analog switching circuit, the pullup resistor900may be provided to a single R/B signal line700M (the R/B signal line700M coupled to the controller201) that may be coupled to each of the R/B signal lines700A to700D. Thus, the number of the pullup resistors can be reduced compared with a case where the pullup resistor is provided to each of the R/B signal lines700A to700D. As a result, the package occupying area and the packaged number of pullup resistors can be reduced.

In the switching circuit including the switching circuit40A for the data system signal and the switching circuit40C for the R/B signal independently provided, the switching circuit40A may be a digital switching circuit, whereas the switching circuit40C may be an analog switching circuit.

Embodiment 4 is described. The difference from Embodiment 1 is mainly described, and the points that are the same as Embodiment 1 are not described or briefly described.

FIG. 6illustrates an overview of an NVM device according to Embodiment 4.

An NVM device103according to Embodiment 4 includes the switching circuit40A for the data system signal and the switching circuit40B for the R/B signal, and further includes a switching circuit (an example of a second switching circuit for selection)40D for the CE signal. A common switching signal is used for the switching circuits40A,40B and40D. The switching circuit40D also corresponds to (1:m) branching with m not being limited to 4. A CE signal line1200M from a controller202is branched by the switching circuit40D for the CE signal into four CE signal lines1200A to1200D that are respectively coupled to the chips61A to61D. The CE signal may be referred to as a CS signal.

In Embodiment 4, the number of CE signal lines is reduced by the switching circuit40D, and thus the total number of signal lines can be further reduced, without increasing the number of switching signal lines because the common switching signal, used for the switching circuits40A and40B, is also used for the switching circuit40D.

Embodiment 5 is described. The difference from Embodiment 4 is mainly described, and the points that are the same as Embodiment 4 are not described or briefly described.

FIG. 7illustrates an overview of an NVM device according to Embodiment 5.

An NVM device104according to Embodiment 5 includes a common (single) switching circuit40R serving as the switching circuits40A,40B and40D. In other words, the switching circuits40A,40B and40D are each a part of the single switching circuit40R. The switching circuit40R also corresponds to (1:m) branching with m not being limited to 4.

In Embodiment 5, the packaging area of the switching circuit can be reduced, and the number of components mounted on the NVM device104can be reduced.

The switching circuit40R may have the same size as each of the switching circuits40A and40B. For example, the switching circuits40A,40B,40D and40R may be the same parts.

Embodiment 6 is described. The difference from Embodiments 1 to 5 is mainly described, and the points that are the same as Embodiments 1 to 5 are not described or briefly described.

FIG. 8illustrates an overview of an NVM device according to Embodiment 6.

An NVM device105according to Embodiment 6 includes an NVM module (for example, DIMM (dual inline memory module) substrate)1100and a module connector1000.

The NVM module1100is a package including the switching circuit40S and the NVM300, and may be detachably attached to the module connector1000. The switching circuit40S is a switching circuit in which the switching circuits40A and40B are integrated as in Embodiment 2.

In Embodiment 6, the number of pins allocated to signals, in pins of the connector1000with which the NVM module1100is coupled, can be reduced. Thus, the number of pins for power supply and ground can be increased. As a result, an improved power supply quality and signal quality can be expected.

Embodiment 7 is described. The difference from Embodiment 1 is mainly described, and the points that are the same as Embodiment 1 are not described or briefly described.

FIG. 9illustrates an overview of an NVM device according to Embodiment 7.

An NVM device106according to Embodiment 7 includes a second switching circuit40E corresponding to (1:m) branching with the value m being smaller than the number of chips corresponding to the same switching signal. In other words, the number of chips the switching signal corresponding to the same switching signal is larger than the value m. Thus, at least one coupling destination of the second switching circuit40E includes two or more chips. For example, in the present embodiment, the number of chips using the common switching signal is four, and the value m is two. Thus, the number of coupling destination chips of the second switching circuit40E is two. In Embodiment 1, the two R/B signal lines700A and700B, independent from each other before reaching the second switching circuit40B, are integrated into a single R/B signal line700X to be coupled to the second switching circuit40E. Similarly, in Embodiment 1, the two R/B signal lines700C and700D, independent from each other before reaching the second switching circuit40B, are integrated into a single R/B signal line700Y to be coupled to the second switching circuit40E.

Thus, in Embodiment 7, pullup resistors9A to9D are respectively provided to the chips61A to61D. The pullup resistors9A to9D respectively have resistance values R1to R4. Thus, a multi-level R/B signal, indicating more than simple ON/OFF, is input to the controller203through the R/B signal line700M. The resistance values R1to R4are different values. Thus, the controller203receives an R/B signal with four signal levels. More specifically, for example, when the coupling destination of the switching circuit40E is the chips61A and61B, the R/B signal received by the controller203has one of the following four signal levels (X1) to (X4):(X1) both the chip61A and the chip61B are in the ready state;(X2) only the chip61A is in the busy state;(X3) only the chip61B is in the busy state; and(X4) both the chip61A and the chip61B are in the busy state.

Some of the resistance value R1to R4may be of the same resistance value. Still, the number of the pullup resistors with the same resistance value cannot exceed m. The pullup resistors with the same resistance value are coupled to different ports (pins) of the second switching circuit40E. This is because when the pullup resistors with the same resistance value are coupled to the same port (pin), the chip cannot be uniquely identified by the controller203by comparing the received R/B signal with reference voltage (described in detail below).

The controller203includes different signal reference voltages Vref1to Vref4respectively corresponding to the different resistance values R1to R4. When the resistance values R1to R4include the same resistance value, the number of included reference voltages may be reduced accordingly.

The controller203executes the operation state check processing (for example, the initial check processing or the ready return check processing) on the coupling destination of the switching circuit40E (and40A). For example, the operation state check processing executed by the controller203includes the following (a) to (c):(a) for example, a selected reference voltage is compared with a signal level (voltage level) of the received R/B signal;(b) when the chip as the coupling destination of the switching circuit40E and the operation state of the chip can be identified from the result of the comparison (a) (for example, when one of (X1) to (X4) described above can be identified), the operation check processing is terminated; and(c) when the chip as the coupling destination of the switching circuit40E and the operation state of the chip cannot be identified from the result of the comparison (a), the selected reference voltage is switched, and the processing returns to (a). For example, when the condition in (b) is satisfied, the controller203switches the coupling destination of the switching circuit40E (and40A), and may start the operation state check processing including (a) to (c) described above on the coupling destination chip, as a result of the switching.

In Embodiment 7, the signal lines can be reduced even when the number of chips, the switching signal for which is common, is larger than the number of branches (a value m) provided by the second switching circuit40E.

Embodiment 8 is an example where the NVM device according to any one of Embodiments 1 to 7 is applied to at least one of a computer and a storage system.

FIG. 10illustrates a configuration of a computer system according to Embodiment 8.

The computer system includes: a plurality of (or a single) computers10; and a storage system1coupled to the computers10. The computer10and the storage system1are coupled to each other via a communication network (for example a SAN (storage area network))12.

The computer10transmits an I/O request to the storage system1. For example, at least one computer10may include: a communication interface device (I/F) (not illustrated) coupled to the SAN12; an SSD (solid state drive)72; and a processor71coupled to these components. The SSD72may be used as a main storage memory or an auxiliary storage device. The SSD72may be an example of a semiconductor memory device, and may be, for example, the NVM device in at least one of Embodiments 1 to 7. The processor71is an upper level device of the SSD72.

The storage system1includes a storage controller2and a storage device group14coupled to the storage controller2.

The storage device group14may include a RAID (redundant array of independent (or inexpensive) disks) group. The RAID group stores data in accordance with a predetermined RAID level. The storage device group14may include storage devices of different types, or may include storage devices of the same type. In the present embodiment, the storage device group14includes a plurality of flash packages15. The flash package15may be an example of the semiconductor memory device, and may be, for example, the NVM device in at least one of Embodiments 1 to 7. The storage controller2is an upper level device of the flash package15.

The storage controller2includes; a SAN I/F (interface device)6coupled to the SAN12; a disk I/F7coupled to the storage device group14; a memory4; a cache memory5; and a processor (for example, the CPU)3coupled to these components. The memory and the cache memory5may be integrally formed. At least one of the memory4and cache memory5may be an example of the semiconductor memory device and may be, for example, the NVM device in any one of Embodiments 1 to 7. The processor3is an upper level device of the memory4and the cache memory5.

The storage controller2(processor3) provides a logical volume to the computer10, receives an I/O request (a write request or a read request) with the logical volume designated, from the computer10, and, according to the received I/O request, performs data I/O for the logical volume. The storage controller2transmits a data write or read request to one or more flash packages15for performing data I/O for the I/O target data. The flash package15that has received the write or the read request executes the write processing or the read processing described above with reference toFIG. 2andFIG. 3for example.

FIG. 11illustrates a configuration of the flash package15.

The flash package15includes a plurality of (or a single) DIMMs30and an FM controller20coupled to these. Each of the DIMMs30includes one or more SWs (switches)31and a plurality of FM (flash memory) chips32. The SW31may be provided outside the DIMM30. A single FM chip32is a single chip61in at least one of Embodiments 1 to 7. A single DIMM30or a group of two or more DIMMs30is a single NVM300in at least one of Embodiments 1 to 7. The FM controller20is a controller (memory controller) in according to at least one of Embodiments 1 to 7. For example, the FM chip32includes a plurality physical blocks. Each physical block includes a plurality of physical pages. Erasing is performed on a block-by-block basis, and I/O is performed on a page-by-page basis. Thus, the FM chip32is a NAND FM chip. Each cell in the FM chip32may be an SLC (single level cell) or an MLC (multi level cell).

The FM controller20includes: an upper level I/F23coupled to the storage controller2; a plurality of FM I/Fs24coupled to the plurality of DIMMs30; a DRAM11; and a processor (for example, a CPU)21coupled to these components. The DRAM11stores therein various programs and information for managing the flash package15. The processor21can implement various functions by executing a program based on the information stored in the DRAM11.

The FM I/F24is coupled to the SW31, and the SW31is coupled to the plurality of FM chips32mounted on the DIMM30. The FM I/F24uses the CE signal to independently control each of the plurality of FM chips32. The FM I/F24operates in accordance with a read/write request from the processor21.

In Embodiment 8, at least one of Embodiments 1 to 7 may be applied to a signal line between the FM I/F24and the FM chip32. For example, when Embodiment 1 is applied, the switching circuits40A and40B are disposed between the FM I/F24and the FM chip32. For example, the SW31may be the switching circuits40A and40B. The FM chips32controlled by the common switching signal are coupled to the SW31the coupling destination of which is switched by the common switching signal. Two or more SWs31may share the switching signal.

The present invention is not limited to some embodiments described above, and may include various modifications. For example, the embodiments described above are described in detail for the sake of description of the present invention, and the present invention is not necessarily limited to a mode including all the above-described configurations. A configuration of one embodiment may be partially replaced with a configuration of another embodiment. Furthermore, a configuration of one embodiment may be added to a configuration of another embodiment. For apart of a configuration of each embodiment, adding, deleting, and replacing of another configuration may be performed. Two or more of Embodiments 1 to 8 may be combined.

For example, components, such as a signal line, described herein are components regarded as being necessary for the description. In other words, these components do not necessarily represent all the components required to form a product.

For example, in Embodiment 2, Embodiment 5, and Embodiment 6, a single circuit to which two or more types of signal lines are coupled is employed instead of two or more switching circuits corresponding to two or more types of signal lines respectively. Alternatively, a single switching circuit may logically (virtually) include two or more switching circuits corresponding to two or more types of signal lines respectively.

REFERENCE SIGNS LIST