MOS power component with a reduced surface area

A MOS power component in which the active regions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. A MOS power transistor according to the present invention alternately includes a source region of a first conductivity type, an intermediary region, and a drain region of the first conductivity type, each of these regions extending across the entire thickness of the substrate, the source and drain regions being contacted by conductive fingers or plates substantially crossing the substrate, insulated and spaced apart conductive fingers crossing from top to bottom the intermediary region, the horizontal distance between the insulated fingers being such that the intermediary region can be inverted when an appropriate voltage is applied to these insulated fingers.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a novel type of MOS-type semiconductor power component, this component being generally called a discrete component although several such components may be provided on the same chip, and/or they can be associated with logic circuits provided on the same chip.

2. Discussion of the Related Art

FIGS. 1A and 1Bare a partial cross-section view and a top view of an example of the structure of a conventional multicellular vertical MOS power component.

This transistor is formed from a lightly-doped N-type layer or substrate1including, on its rear surface side, a heavily-doped N-type layer2(N+). Conversely to what is shown, the N+layer may be much thicker than the N substrate. On the upper surface side of substrate1are formed P wells including a more heavily doped central portion3and a more lightly doped peripheral portion4. Substantially at the center of the P wells is formed a heavily-doped N-type ring5. Portion6of the P well external to N well5is topped with a conductive gate7insulated by a thin insulating layer8. The upper surface and the lateral surface of gate7are insulated by an insulating layer9and the assembly is coated with a source metallization MS. The lower surface of the component is coated with a drain metallization MD. All the gates7are connected to a common gate terminal, not shown.

FIG. 1Bis a top view of the structure without the gate and source metallization MS. The same elements are designated therein with the same references as inFIG. 1A.

For the simplicity of the drawing, each cell has been shown according to a square pattern. Other shapes are possible and currently used. When the source is negative with respect to the drain and the gate is properly biased, the current flows from the drain to the source, through the channel region in the direction of arrows1illustrated inFIGS. 1A and 1Bin a portion of the structure. Similar currents flow from each of the cells. These currents essentially flow vertically, whereby the MOS transistor is said to be vertical.

A disadvantage of vertical MOS power transistors is their on-state resistance. Indeed, practical considerations make it difficult to optimize the thicknesses of the various layers and regions according to the desired transistor characteristics. In particular, the thickness of N-type layer1must be sufficiently high for the component to have a desired breakdown voltage but must also be as small as possible to limit the on-state resistance of the component. N+ layer2is used to take an ohmic drain contact on the rear surface. Its thickness could be reduced to a few micrometers, but this would lead to too thin silicon wafer thicknesses (<100 μm), incompatible with current production tools. Very thick N+layers2(of a few hundreds of micrometers) are thus used. This layer then introduces an additional series resistance that reduces the on-state performances of the transistor.

Another disadvantage of vertical components is that the channel width (perimeter of P wells4) depends in particular on the surface of the semiconductor chip taken up by the transistor and cannot be increased beyond certain limits.

A MOS transistor has been described, only as an example of a vertical MOS-type component. The problems indicated hereabove generally relate to MOS power or vertical high-power components, for example, insulated-gate bipolar transistors (IGBT) and other voltage-control enrichment or depletion components, of MOS or Schottky-MOS type.

SUMMARY OF THE INVENTION

The present invention aims at providing novel types of semiconductor MOS power or high-voltage components enabling avoiding at least some of the above-mentioned disadvantages of vertical components, in particular increasing the active junction surface with respect to the surface area of the chip in which the component is formed, and reducing the on-state voltage drop.

To achieve these and other objects, the present invention provides a MOS power component in which the active regions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof.

According to an embodiment of the present invention, the contacts with the regions to be connected are taken by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

According to an embodiment of the present invention, the conductive fingers are metal fingers.

According to an embodiment of the present invention, the junctions or limits between regions are arranged in planes perpendicular to the main chip surfaces.

According to an embodiment of the present invention, the junctions or limits between regions are formed of several cylinders perpendicular to the main chip surfaces.

A MOS power transistor according to the present invention alternately comprises a source region of a first conductivity type, an intermediary region, and a drain region of the first conductivity type, each of these regions extending across the entire thickness of the substrate, the source and drain regions being contacted by conductive fingers or plates substantially crossing the substrate, insulated and spaced apart conductive fingers crossing from top to bottom the intermediary region, the horizontal distance between the insulated fingers being such that the intermediary region can be inverted when an appropriate voltage is applied to these insulated fingers.

According to an embodiment of the present invention, the conductive fingers penetrating into lightly-doped N-type regions are surrounded with heavily-doped N-type regions.

An IGBT transistor according to the present invention alternately comprises a source region of a first conductivity type, an intermediary region, a drain region of the first conductivity type, and an additional region of the second conductivity type, each of these regions extending across the entire substrate thickness, the source region and the additional region being contacted by conductive fingers or plates substantially crossing the substrate, insulated and spaced apart conductive fingers crossing from top to bottom the intermediary region, the horizontal region between the insulated fingers being such that the intermediary region can be inverted when an appropriate voltage is applied to these insulated fingers.

According to an embodiment of the present invention, each of the conductive fingers is respectively connected to a source metallization, to a gate metallization, and to a drain metallization.

According to an embodiment of the present invention, localized metallizations extend vertically between the source region and the intermediary region to form localized short-circuits.

According to an embodiment of the present invention, the insulated and spaced apart conductive fingers are formed from conductive fingers crossing the entire thickness of the chip, the walls of which are oxidized and which are filled with doped polysilicon.

DETAILED DESCRIPTION

As conventional in the field of semiconductor representation, the various drawings are not to scale. Especially, in these various drawings, the lateral dimensions have been greatly exaggerated with respect to the vertical directions. Indeed, a silicon wafer currently has a thickness of from 300 to 500 μm—and greater thicknesses may be chosen for an implementation of the present invention—while patterns and vias may be defined according to dimensions on the order of from 5 to 50 μm.

FIG. 2Ais a simplified cross-section view of a portion of a semiconductor wafer in which is formed an assembly of MOS transistor cells according to the present invention. The main surfaces of the component correspond to the upper and lower surfaces of a semiconductor wafer, and the vertical dimension, the height of which is designated as e, corresponds to the thickness of the semiconductor wafer.

FIGS. 2B and 2Care two simplified examples of top views of the structure formed in the semiconductor substrate, both corresponding to the cross-section view ofFIG. 2A.

An elementary cell according to the present invention comprises a conductive finger11extending across the entire wafer thickness or across a major part of this thickness. Conductive finger11is bordered with a heavily-doped N-type region12(N+), itself bordered with a P-type intermediary region13, then with a lightly-doped N-type region14, and a heavily-doped N-type region15serving as an ohmic contact recovery with a conductive finger16. Since conductive finger11, regions12,13,14, and15and conductive finger16extend substantially across the entire substrate thickness, and the junctions or limits between these elements are substantially vertical. Conductive finger11corresponds to a source metallization, region12corresponds to a source area, intermediary region13corresponds to the area in which a channel can be formed, region14corresponds to a drain area, region15corresponds to a drain contact recovery layer, and finger16corresponds to a drain metallization.

FIG. 2Bis a top view of the present invention in an embodiment in which the conductive fingers are made in the form of vertical conductive plates extending in trenches made in a semiconductor substrate.

The embodiment of the MOS transistor gate according to the present invention can be better seen inFIG. 2B. This gate is formed by means of spaced apart conductive fingers21surrounded with an insulating layer22extending vertically in intermediary region13. When a positive voltage is applied between gate fingers21and source finger11, a channel forms in the vertical area of intermediary region13comprised between two gate fingers, so that the MOS transistor becomes conductive between its source and its drain, and a current indicated by arrows1is likely to flow horizontally from the drain to the source. An enrichment MOS transistor has been described hereabove; in the case of a depletion MOS transistor, intermediary region13, at least in the vicinity of the gate insulator, would be lightly doped of type N and the application of a voltage between gate fingers21and source finger11would make the MOS transistor non-conductive between its source and its drain.

Conductive fingers23penetrating into all or part of the substrate thickness and enabling establishing a short-circuit between intermediary well13and source region12have also been shown inFIG. 2B, which forms the equivalent of the short-circuit established by source metallization MS ofFIG. 1Abetween N+ring5and the central portion of P well3.

FIG. 2Cillustrates in top view another embodiment of a component according to the present invention in which each MOS transistor cell exhibits a closed contour. Central source finger11is surrounded with an N+-type ring-shaped region12, itself surrounded with a P-type intermediary ring-shaped region13, an N-type ring-shaped region14, and an N-type heavily-doped ring-shaped region15(N+). InFIG. 2C, the structure has been shown as completely surrounded with a conductive ring16. In practice, this ring may be formed of a succession of conductive fingers close to one another. To simplify the representation, conductive fingers23have not been shown inFIG. 2C.

The drain, gate, and source metallizations have not been shown inFIGS. 2A,2B, and2C. It should be understood that all gate fingers21are connected to a same metallization, all source fingers11are connected to a same metallization, and all drain fingers16are connected to a same metallization. Preferably, as in a conventional component, the drain and source metallizations are formed on two opposite surfaces of the semiconductor chip. According to an advantage of the present invention, the gate metallization may, as chosen and as simply, be formed on the drain side or on the source side, which simplifies monolithic assemblies of components according to the present invention.

The forming of a component according to the present invention will readily occur to those skilled in the art who may use conventional techniques for forming openings in the form of vias or trenches, for doping from the openings thus formed, then for filling these openings with a conductor, for example, a metal, for example, copper, this filling being preceded or not by the forming of an insulating layer. It should be understood that, although terms via or finger are used in the present invention, these terms also encompass trench-shaped structures such as those inFIG. 2Bor ring-shaped structures such as metallization16ofFIG. 2C.

The above description essentially aims at the MOS transistor structure and the order of the manufacturing steps may be modified.

As indicated previously, the present invention applies not only to a MOS transistor, but also generally to any MOS power or high-voltage component, for example insulated-gate bipolar transistors (IGBT) and other enrichment or depletion voltage-controlled components, of MOS or Schottky-MOS type. In particular, it can be simply changed from the MOS transistor structure ofFIG. 2to an IGBT structure by replacing heavily-doped N-type layer15with a heavily-doped P-type layer.

According to an advantage of the present invention, the channel width per surface area unit is much greater than that obtained in a vertical diffused MOS transistor (VDMOS) such as that ofFIG. 1, as well as the total surface area of the drain of the cell assembly may be greater than the surface area of the chip containing these cells.

Another advantage of the present invention is that it is possible to form several components according to the present invention in the same semiconductor layer, with each of these components being easy to surround with insulating walls formed in any chosen fashion. Examples of such assemblies will be given inFIGS. 3 and 4.

FIG. 3Ashows the diagram of an antiparallel assembly of two IGBT transistors according to the present invention comprising two main terminals T1and T2and two control terminals G1and G2. In the following description, the main terminals of the IGBT transistor will be called the source and the drain to simplify the analogy with the previously-described MOS transistor.

FIG. 3Bshows a simplified example of the forming of such an assembly in which the same elements as inFIG. 2Aare designated with the same reference numerals. The left-hand portion of the drawing shows an IGBT transistor comprising a source finger11-1, surrounded with an N+region12-1, an intermediary region13-1crossed by gate fingers that are not visible in the drawing. An N-type region14-1extends between region13-1and a P+-type region32-1that surrounds a drain finger16-1. This assembly is separated by an insulating wall31from a structure arranged symmetrically with respect to this wall and comprising a drain finger16-2surrounded with a P+region32-2and separated by a lightly-doped N-type region14-2from an intermediary region13-2in which a channel is likely to form and into which gate fingers, not shown, penetrate. Intermediary region13-2is in contact with a heavily-doped N-type region12-2in contact with a source finger11-2. Although a single cell has been shown, it should be understood that each of the structures is formed of a cell assembly, as described previously. The source fingers of the cells located to the left of the insulating wall are solid with an upper metallization T1, as well as drain fingers16-2of the cells arranged to the right of the insulating wall. Drain fingers15-1of the cells located to the left of the insulating wall are connected to a lower metallization T2, as well as source fingers11-2of the cells located to the right of the insulating wall. Connections G1and G2, of which it should be noted that they may easily be formed on the same surface of the component, have only been shown symbolically.

This structure has, as compared to monolithic structures assembling conventional vertical IGBT transistors, the advantage that the two IGBT transistors are perfectly symmetrical and that the transistors characteristics are also perfectly symmetrical.

The structures according to the present invention further enable associating MOS components such as described hereabove also formed with vertical junctions (perpendicular to the main substrate surfaces).

FIG. 4Ashows an example of such an association, comprising a MOS transistor, TMOS, and a diode, D, the anode of the diode being connected to the drain of the MOS transistor. This circuit forms an element currently used in practice and difficult to integrate with conventional technologies.

FIG. 4Bshows an embodiment of such a structure. InFIG. 4B, the left-hand portion is strictly identical to the left-hand portion ofFIG. 3Bexcept that the P-type region surrounding the drain region is replaced with an N+-type region to form a MOS transistor. The MOS transistor comprises a source finger11, a source region12, an intermediary region13, a drain region14, and a drain finger16surrounded with a heavily-doped N-type region15. This assembly is separated by an insulating wall32from a diode structure comprising a cathode finger40surrounded with a heavily-doped N-type region41and separated, by a lightly-doped N-type region42, from an anode finger43surrounded with a P-type region44. The source finger of the MOS transistor is connected to a first main metallization M1. The gate fingers (not shown) are connected to a control metallization G1. Cathode finger40of the diode is connected to a metallization M2. The drain fingers of the MOS transistor cells as well as anode fingers43of the diode cells are connected to a metallization M3. In the shown example, metallization M3is on the rear surface side and metallizations M1, M2, and G1are on the front surface side.

The various illustrated structures are likely to have various alterations and modifications, and those skilled in the art should note the alterations described for certain embodiment apply to other embodiments.

On the other hand, many embodiments will readily occur to those skilled in the art, and will be possible according to the technical development, the forming of conductive fingers or of plates formed in trenches only being examples of possible approaches of the forming of structures with vertical limits or junctions.

It should be noted that, since more current per surface area unit of the chip may flow through a MOS transistor according to the present invention than through a conventional MOS transistor, more heat will be generated per surface area unit when the transistor is on (although the on-state voltage drop is smaller due to the possible optimization of the thickness of the reverse voltage hold layer). However, this heat may advantageously be extracted by means of the through conductive fingers. Indeed, metal fingers have a heat conductivity from 2 to 3.5 times greater than the equivalent silicon volume. These fingers may take up a large surface area and, in particular, the peripheral “fingers” may take up the entire free surface area between elementary cells of a component.