METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

A method of manufacturing a semiconductor device in which a conductive layer is formed over a semiconductor substrate, and a hard mask layer is formed. Some portions of the hard mask layer are selectively removed to form first patterns of the hard mask layer and a second pattern of the hard mask layer. A first shielding pattern that shields a first region of the semiconductor substrate is formed, and the portions of the conductive layer, exposed by the first shielding pattern and the second pattern of the hard mask layer are selectively removed to form a first conductive line pattern. A second shielding pattern that shields a second region of the semiconductor substrate is formed, and other portions of the conductive layer, exposed by the second shielding pattern and the first patterns of the hard mask layer are selectively removed to form second conductive line patterns.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. 119(a) to Korean Application No. 10-2023-0039903, filed on Mar. 27, 2023, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure generally relates to integrated circuit devices and, more particularly, to methods of manufacturing semiconductor devices including conductive patterns.

2. Related Art

Integrated circuit elements may be integrated on a semiconductor substrate to form semiconductor devices. As design rules required for the semiconductor devices change over time, spaces between conductive patterns constituting the integrated circuit elements are decreasing. Conductive patterns having different critical dimensions (CDs) are being formed on semiconductor substrates with different line widths, spacings, and densities.

SUMMARY

One embodiment of the present disclosure may provide a method of manufacturing a semiconductor device including forming a first conductive layer over a semiconductor substrate including a first region and a second region, forming a hard mask layer on the first conductive layer, forming first patterns of the hard mask layer over the first region and a second pattern of the hard mask layer over the second region by selectively etching portions of the hard mask layer, forming a first shielding pattern that shields the first region and opens the second region, forming a first conductive line pattern by selectively removing first portions of the first conductive layer, exposed by the first shielding pattern and the second pattern of the hard mask layer, forming a second shielding pattern that shields the second region and opens the first region, and forming second conductive line patterns by selectively removing second portions of the first conductive layer, exposed by the second shielding pattern and the first patterns of the hard mask layer.

Another embodiment of the present disclosure may provide a method of manufacturing a semiconductor device including forming a first conductive layer over a semiconductor substrate, forming a hard mask layer on the first conductive layer, selectively etching portions of the hard mask layer to form first patterns of the hard mask layer and a second pattern of the hard mask layer, forming a first shielding pattern that shields first portions of the first conductive layer exposed by the first patterns of the hard mask layer and opens second portions of the first conductive layer exposed by the second pattern of the hard mask layer, selectively removing the second portions of the first conductive layer to form a first conductive line pattern, forming a second shielding pattern that shields the first conductive line pattern and opens the first portions of the first conductive layer, and selectively removing the second portions of the first conductive layer to form second conductive line patterns.

DETAILED DESCRIPTION

The terms used herein may correspond to words selected in consideration of their functions in the presented embodiments. If defined in detail, the terms may be construed according to the definitions. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the plain and ordinary meaning as understood by one of ordinary skill in the art to which the embodiments belong.

In the descriptions in the present disclosure, descriptions such as “first” and “second,” “bottom,” “top,” and “lower” are for distinguishing elements, and are not used to limit the elements themselves or to imply a specific order. These descriptors mean a relative positional relationship, and do not limit a specific case in which another member is further introduced into direct or indirect contact with the element or at an interface between them. The same interpretation may be applied to other expressions describing the relationship between components.

Embodiments of the present disclosure may be applied to technical fields for implementing integrated circuit devices such as for example dynamic random access memory (DRAM) circuits, phase change random access memory (PcRAM) devices, or resistive random access memory (ReRAM) devices. In addition, the embodiments of the present disclosure may be applied to technical fields for implementing memory devices such as for example static random access memory (SRAM) devices, FLASH memory devices, magnetic random access memory (MRAM) devices, or ferroelectric random access memory (FeRAM) devices, or logic devices in which logic circuits are integrated. The embodiments of the present application may be applied (in general) to any technical fields implementing various products requiring fine-sized conductive patterns.

The same reference numerals in this disclosure refer to same devices throughout the specification. Even though a reference numeral might not be mentioned or described with reference to a drawing, the reference numeral may be mentioned or described with reference to another drawing. In addition, even though a reference numeral might not be shown in a drawing, it may be shown in another drawing.

FIG.1is a schematic view illustrating formation of a first conductive layer300in a method of manufacturing a semiconductor device according to one embodiment.

Referring toFIG.1, the first conductive layer300may be formed over a semiconductor substrate100. The first conductive layer300may be a layer for a first conductive line pattern and/or a second conductive line pattern. The second conductive line pattern may include a bit line pattern, and the first conductive line pattern may include a gate pattern. The first conductive layer300may include a metal layer such as a tungsten (W) layer. The first conductive layer300may further include a barrier layer under the metal layer to prevent diffusion or movement of metal ions. The barrier layer may include a layer such as, for example, a titanium (Ti) layer, a tungsten nitride (TiN) layer, or a tungsten silicon nitride (WSiN) layer, or a composite layer thereof.

The first conductive layer300may be formed to extend to cover structures formed over a first region100C and a second region100P of the semiconductor substrate100. The first region100C and the second region100P of the semiconductor substrate100may be regions distinguished from each other. Patterns of different shapes, different densities, or different line widths may be formed over the first region100C and the second region100P of the semiconductor substrate100. The first conductive layer300may be separated or patterned into patterns having different shapes, patterns disposed at different densities, patterns having different line widths, or patterns disposed at different spacings in the first region100C and the second region100P of the semiconductor substrate100. In order to provide bit line patterns over the first region100C of the semiconductor substrate100, the first conductive layer300may extend over the first region100C of the semiconductor substrate100. In order to provide a gate pattern over the second region100P of the semiconductor substrate100, the first conductive layer300may extend over the second region100P of the semiconductor substrate100.

The first region100C of the semiconductor substrate100may be a cell region, and the second region100P of the semiconductor substrate100may be a peripheral region. The cell region may be a region in which main circuits constituting a semiconductor device are disposed, and the peripheral region may be a region in which peripheral circuits for operating the main circuits are disposed. In a semiconductor device including a memory device such as a DRAM device, memory elements may be disposed in the cell region, and the peripheral circuits such as, for example, sensing and amplifying circuits may be disposed in the peripheral region. The memory element may include cell transistor elements. Peripheral transistors constituting the peripheral circuits may be disposed in the second region100P of the semiconductor substrate100.

The semiconductor substrate100may include a semiconductor material such as silicon (Si). The semiconductor substrate100may include a semiconductor material such as germanium (Ge). The semiconductor substrate100may include a compound semiconductor material such as, for example, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphorus (InP). The semiconductor substrate100may have a wafer shape.

Connection elements for connecting the first conductive layer300and the semiconductor substrate100to each other may be disposed under the first conductive layer300. Bit line plugs210C may be disposed as conductive elements electrically connecting the first conductive layer300and some portions of the semiconductor substrate100to each other. The first conductive layer300may be formed over the semiconductor substrate100to be connected to the bit line plugs210C.

The bit line plugs210C may be positioned over the first region100C of the semiconductor substrate100. The bit line plugs210C may have shapes in which some portions of the bit line plugs210C penetrate into some portions of the semiconductor substrate100in the first region100C. The bit line plugs210C may have shapes in which some portions of the bit line plugs210C are infiltrated into some portions of the semiconductor substrate100in the first region100C. The shapes of the bit line plugs210C, in which some portions of the bit line plugs210C infiltrate into some portions of the semiconductor substrate100, may further secure contact surfaces between the bit line plugs210C and the semiconductor substrate100, and may be advantageous in improving contact resistance.

The bit line plugs210C may be connected to some portions of active regions101of the semiconductor substrate100of the first region100C. The active regions101of the semiconductor substrate100may be regions partitioned by device isolation layers110formed in the semiconductor substrate100. The active regions101positioned in the first region100C of the semiconductor substrate100may each have a narrower width than other active regions101formed in the second region100P. The device isolation layers110positioned in the first region100C of the semiconductor substrate100may each have a narrower width than other device isolation layers110formed in the second region100P. Each of the device isolation layers110may include silicon oxide (SiO2) or silicon nitride (Si3N4) layer. The device isolation layer110positioned in the second region100P of the semiconductor substrate100may be formed as a composite layer including a silicon oxide (SiO2) layer and a silicon nitride (Si3N4) layer.

A second conductive layer210may be further formed between the first conductive layer300and the second region100P of the semiconductor substrate100. The second conductive layer210may be formed as a layer constituting peripheral gate patterns for the peripheral transistors constituting the peripheral circuits in the second region100P of the semiconductor substrate100, together with the first conductive layer300. The second conductive layer210may also be formed over the first region100C of the semiconductor substrate100to form the bit line plugs210C. The bit line plugs210C may be patterns formed by being separated from some portions of the second conductive layer210, extending over the first region100C of the semiconductor substrate100.

A gate dielectric layer111may be disposed between the second conductive layer210and the second region100P of the semiconductor substrate100. The gate dielectric layer111may be a dielectric layer covering a surface101S of the semiconductor substrate100positioned in the second region100P of the semiconductor substrate100. The gate dielectric layer111may include a silicon oxide (SiO2) layer. A first dielectric layer120and a second dielectric layer130may be disposed between the first conductive layer300and the first region100C of the semiconductor substrate100. The first dielectric layer120and the second dielectric layer130may electrically isolate the active regions101of the semiconductor substrate100from the first conductive layer300in the first region100C. The first dielectric layer120and the second dielectric layer130may be formed of different dielectric materials. The first dielectric layer120may be formed of silicon oxide, and the second dielectric layer130may be formed of silicon nitride. The bit line plugs210C may be formed to penetrate the first dielectric layer120and the second dielectric layer130.

FIGS.2to6are views schematically illustrating for forming the first conductive layer300ofFIG.1over the semiconductor substrate100. The processings shown inFIGS.2to6present a procedure for forming a lower structure on which the first conductive layer300ofFIG.1is formed. Forming the lower structure on which the first conductive layer300is formed is not limited to these processings.

Referring toFIG.2, the device isolation layers110may be formed on the first region100C and the second region100P of the semiconductor substrate100to partition the active regions101. The first dielectric layer120and the second dielectric layer130may be formed over the first region100C of the semiconductor substrate100.

Referring toFIG.3, buried gate patterns150may be formed in the semiconductor substrate100.FIG.3shows a cross-sectional shape obtained by cutting the first region100C of the semiconductor substrate100in a direction different from that ofFIG.2.FIG.3shows a cross section crossing a plurality of neighboring buried gate patterns150. The buried gate patterns150may be formed to extend while crossing bit line patterns to be separated from the first conductive layer (layer300inFIG.1).

The buried gate patterns150may constitute cell transistors, together with the bit line patterns. Some portions of the first region100C of the semiconductor substrate100may be recessed to form recess portions150T in which the buried gate patterns150are to be formed. When the portions of the first region100C of the semiconductor substrate100are recessed, the first dielectric layer120may open some portions of the semiconductor substrate100where the recess portions150T are to be formed, and cover and protect other portions of the semiconductor substrate100which are not to be recessed. Each of the recess portions150T may be formed in a trench shape. The buried gate patterns150containing a conductive material may be formed in the recess portions150T, and the second dielectric layer130may be formed to fill the recess portions150T while covering the buried gate patterns150.

Buried gate dielectric layers may be formed at interfaces between the buried gate patterns150and the active regions101of the semiconductor substrate100. As the buried gate patterns150are buried in the semiconductor substrate100, the buried gate patterns150may be positioned lower than the surface101S of the semiconductor substrate100, and a longer channel length or a longer length between source and drain regions of the cell transistor may be secured. The source region and the drain region may be formed by doping the active regions101of the semiconductor substrate100in the first region100C with impurities.

Referring toFIG.4, some portions of the semiconductor substrate100positioned in the first region100C of the semiconductor substrate100may be recessed to form plug holes210H extending into some active regions101of the semiconductor substrate100. The plug holes210H may be provided to form the bit line plugs210C ofFIG.1. The plug holes210H may be formed to substantially penetrate the first and second dielectric layers120and130and further extend below the surface101S of the semiconductor substrate100. Bottoms of the plug holes210H may be positioned lower than the surface101S of the semiconductor substrate100.

Referring toFIG.5, the second conductive layer210may be formed over the semiconductor substrate100. The second conductive layer210may be formed over the second region100P and the first region100C of the semiconductor substrate100. The second conductive layer210may be formed of a different conductive material from the first conductive layer300ofFIG.1. The second conductive layer210may include doped polycrystalline silicon. The second conductive layer210may extend to fill the plug holes210H in the first region100C of the semiconductor substrate100. The second conductive layer210may extend to cover the gate dielectric layer111while directly contacting the gate dielectric layer111in the second region100P of the semiconductor substrate100. Some portions210-1of the second conductive layer210may extend to cover the second dielectric layer130while directly contacting the second dielectric layer130in the first region100C of the semiconductor substrate100.

Referring toFIGS.5and6, the portions210-1of the second conductive layer210may be removed to form the bit line plugs210C separated from each other. The bit line plugs210C may be separated from the second conductive layer210to fill the plug holes210H. The first conductive layer300ofFIG.1may be formed on a resultant structure in which the bit line plugs210C are formed.

After the portions210-1of the second conductive layer210(shown inFIG.5) are removed, a third shielding pattern350(shown inFIG.6) may be formed to open the first region100C of the semiconductor substrate100while shielding the second region100P of the semiconductor substrate100. The third shielding pattern350may cover a portion of the second conductive layer210positioned in the second region100P of the semiconductor substrate100to protect the portion from an etch process for removing the portions210-1of the second conductive layer210. The third shielding pattern350may include a resist material. The third shielding pattern350may include a resist material for argon fluoride (ArF), that may be exposed by ArF light.

FIG.7is a schematic view illustrating formation of a hard mask layer400in the method of manufacturing a semiconductor device according to one embodiment.

Referring toFIG.7, the hard mask layer400may be formed on the first conductive layer300. The hard mask layer400may be formed as a layer that covers and protects the first conductive layer300. The hard mask layer400may be formed as a layer that blocks diffusion of metal ions from a metal layer such as tungsten (W) layer, constituting the first conductive layer300. The hard mask layer400may include a dielectric material such as silicon nitride (Si3N4).

FIG.8is a schematic view illustrating formation of first patterns400C and a second pattern400P of the hard mask layer400in the method of manufacturing a semiconductor device according to one embodiment.

Referring toFIGS.7and8, some portions of the hard mask layer400may be selectively removed to form the first patterns400C of the hard mask layer and the second pattern400P of the hard mask layer. The hard mask layer400may be patterned so that the first patterns400C of the hard mask layer are positioned over the first region100C of the semiconductor substrate100, and the second pattern400P of the hard mask layer is positioned over the second region100P of the semiconductor substrate100. A line width W1of each of the first patterns400C of the hard mask layer may be smaller than a line width W2of the second pattern400P of the hard mask layer. The first patterns400C of the hard mask layer may have higher density than the second pattern400P of the hard mask layer.

FIGS.9to12are views schematically illustrating for forming the first patterns400C and the second pattern400P of the hard mask layer ofFIG.8. The processings shown inFIGS.9to12present one method of implementing the first patterns400C and the second pattern400P of the hard mask layer ofFIG.8. Forming the first patterns400C and the second pattern400P of the hard mask layer is not limited to these processings.

Referring toFIG.9, a resist layer520may be formed over the hard mask layer400. A resist underlayer510may be further formed between the hard mask layer400and the resist layer520. The resist layer520may include a resist material for extreme ultraviolet (EUV) lithography process.

The resist underlayer510may include a dielectric material. The resist underlayer510may include a double layer of a first underlayer511and a second underlayer512. The first underlayer511may include a carbon layer. The carbon layer may be formed through a spin on carbon (SOC) process. The carbon layer may include an amorphous carbon layer. The second underlayer512may be formed as a dielectric layer that isolates the carbon layer and the resist layer520from each other. The second underlayer512may prevent the resist layer520from being undesirably contaminated by mixing carbon of the carbon layer with a resist material constituting the resist layer520. The second underlayer512may include a dielectric layer containing silicon (Si). The second underlayer512may include an oxide containing silicon (Si) or a nitride containing silicon (Si). The dielectric layer containing silicon (Si) may be a layer including silicon oxynitride (SiON).

Referring toFIGS.9and10, the resist layer520may be exposed and developed to form resist patterns520C and520P. Some portions of the resist layer520may be exposed using extreme ultraviolet (EUV) light, and the exposed portions may be developed and removed from the resist layer520. By exposing the resist layer520through a lithography process using for example extreme ultraviolet (EUV), the resist patterns520C and520P may be formed as patterns having minute line widths.

The resist patterns520C and520P may be formed to provide the shapes of the first patterns400C of the hard mask layer and the second pattern400P of the hard mask layer ofFIG.8. The resist patterns520C and520P may include the first resist patterns520C and the second resist pattern520P. The first resist patterns520C may be positioned over the first region100C of the semiconductor substrate100and formed in patterns having a minute line width. The first resist patterns520C may provide the shapes of the first patterns400C of the hard mask layer, and the second resist pattern520P may provide the shape of the second pattern400P of the hard mask layer. The second resist pattern520P may be positioned over the second region100P of the semiconductor substrate100.

Referring toFIGS.10and11, resist underlayer patterns510C and510P may be formed through a selective etching process using the resist patterns520C and520P as etch masks. The selective etching process may be performed to selectively remove some portions of the resist underlayer510, exposed by the resist patterns520C and520P. The portions of the resist underlayer510may be selectively etched and removed, and the shapes of the resist patterns520C and520P may be transferred to the resist underlayer patterns510C and510P. The resist underlayer patterns510C and510P may include resist underlayer first patterns510C and a resist underlayer second pattern510P. The resist underlayer first patterns510C may be configured in a stack structure of a first underlayer first pattern511C and a second underlayer first pattern512C, and the resist underlayer second pattern510P may be configured in a stack structure of a first underlayer second pattern511P and a second underlayer second pattern512P.

Referring toFIGS.11and12, through another selective etching process using the resist patterns520C and520P and the resist underlayer patterns510C and510P as etch masks, the hard mask layer400may be patterned. The shapes of the resist patterns520C and520P may be pattern-transferred to the first patterns400C of the hard mask layer and the second pattern400P of the hard mask layer. Some portions of the hard mask layer400exposed through the resist underlayer patterns510C and510P may be selectively etched and removed, so that the first patterns400C of the hard mask layer and the second pattern400P of the hard mask layer, in which the shapes of the resist underlayer patterns510C and510P are pattern-transferred, may be formed.

After forming the first patterns400C of the hard mask layer and the second pattern400P of the hard mask layer, the resist underlayer patterns510C and510P may be removed while removing the resist patterns520C and520P. The resist patterns520C and520P may be removed using an ashing process. An O2plasma may be provided to the resist patterns520C and520P, so that the resist material may be removed by the O2plasma. While the resist patterns520C and520P are ashed, the first underlayer first patterns511C and the first underlayer second pattern511P may be ashed and removed together. Because the first underlayer first patterns511C and the first underlayer second pattern511P are formed of carbon, the first underlayer first patterns511C and the first underlayer second pattern511P may be removed by the O2plasma. As the first underlayer first patterns511C and the first underlayer second pattern511P are removed, the second underlayer first patterns512C and the second underlayer second pattern512P may also be removed. As the first underlayer first patterns511C and the first underlayer second pattern511P are removed, the second underlayer first patterns512C and the second underlayer second pattern512P may be lifted-off.

FIG.13is a schematic view illustrating formation of bit line patterns300C and a gate pattern300P+210P in the method of manufacturing a semiconductor device according to one embodiment.FIGS.14to17are views schematically illustrating processings which form the bit line patterns300C and the gate pattern300P+210P ofFIG.13. The processings shown inFIGS.14to17present one method of forming the bit line patterns300C and the gate pattern300P+210P. Forming the bit line patterns300C and the gate pattern300P+210P is not limited to these processings. Each of the bit line patterns300C may include a second conductive line pattern, and the gate pattern300P+210P may include first and second conductive line patterns. The gate pattern300P+210P may include the first gate pattern300P and the second gate pattern210P. The first gate pattern300P may include the first conductive line pattern, and the second gate pattern210P may include the third conductive line pattern. In the following descriptions, the first gate pattern300P may indicate the first conductive line pattern, the second gate pattern210P may indicate the third conductive line pattern, and the bit line pattern300C may indicate the second conductive line pattern.

Referring toFIGS.13and14, a first shielding pattern310may be formed over the semiconductor substrate100. In order to form the gate pattern300P+210P in the second region100P of the semiconductor substrate100, the first shielding pattern310may be formed over the semiconductor substrate100to shield the first region100C of the semiconductor substrate100and to open the second region100P of the semiconductor substrate100. The first shielding pattern310may be formed to open some portions300A of the first conductive layer positioned around the second pattern400P of the hard mask layer. The first shielding pattern310may be formed as a pattern that opens and exposes the second pattern400P of the hard mask layer. The first shielding pattern310may be formed to shield other portions300B of the first conductive layer310exposed between the first patterns400C of the hard mask layer. The first shielding pattern310may extend to cover the first patterns400C of the hard mask layer.

The first shielding pattern310may include a resist material different from that of the resist layer520ofFIG.9. The first shielding pattern310may include a resist material that may be exposed by argon fluoride (ArF) light. A first shielding layer may be formed over the semiconductor substrate100to cover the first patterns400C of the hard mask layer and the second pattern400P of the hard mask layer, and a portion of the first shielding layer may be selectively exposed and developed, thereby forming the first shielding pattern310.

Referring toFIGS.14and15, the gate pattern300P+210P may be formed over the second region100P of the semiconductor substrate100through a selective etching process using the first shielding pattern310and the second pattern400P of the hard mask as etch masks. The portions300A of the first conductive layer300exposed by the first shielding pattern310and the second pattern400P of the hard mask layer may be selectively etched and removed to form the first gate pattern300P from the first conductive layer300. The portions of the second conductive layer210, exposed while selectively removing the portions300A of the first conductive layer300may be further removed. Accordingly, the second gate pattern210P overlapping with the first gate pattern300P may be formed. The gate pattern300P+210P may be formed in a stack structure in which the first gate pattern300P overlaps with the second gate pattern210P. The gate pattern300P+210P may constitute a peripheral transistor for the peripheral circuit. After forming the gate pattern300P+210P, the first shielding pattern310may be removed.

Referring toFIGS.13and16, a second shielding pattern330may be formed over the semiconductor substrate100. In order to form the bit line patterns300C in the first region100C of the semiconductor substrate100, the second shielding pattern330may be formed over the semiconductor substrate100to shield the second region100P of the semiconductor substrate100and to open and expose the first region100C of the semiconductor substrate100. The second shielding pattern330may be formed to open and expose the portions300B of the first conductive layer300, positioned between the first patterns400C of the hard mask layer. The second shielding pattern330may extend to cover the second pattern400P of the hard mask layer and the first gate pattern300P and second gate pattern210P.

The second shielding pattern330may include different material from the resist layer520ofFIG.9. The second shielding pattern330may include a resist material that may be exposed by argon fluoride (ArF) light. The second shielding pattern330may be formed by forming a second shielding layer over the semiconductor substrate100to cover the second pattern400P of the hard mask layer, the first gate pattern300P, and the second gate pattern210P, and selectively exposing and developing some portions of the second shielding layer.

Referring toFIGS.16and17, through a selective etching process using the second shielding pattern330and the first patterns400C of the hard mask layer as etching masks, the bit line patterns300C may be formed over the first region100C of the semiconductor substrate100. The portions300B of the first conductive layer300, exposed by the second shielding pattern330and the first patterns400C of the hard mask layer may be selectively etched and removed to separate the bit line patterns300C from the first conductive layer300.

Some portions of the bit line plugs210C, exposed while the portions300B of the first conductive layer300are selectively removed may be further removed. Accordingly, bit line plugs210CA having a width reduced from the width of the bit line plugs210C may be formed. As the portions of the bit line plugs210C are removed, gap portions210CH may be formed between the bit line plugs210CA and the first dielectric layer120and between the bit line plugs210CA and the second dielectric layer130. The first dielectric layer120may be formed of silicon nitride substantially the same as that of each of the first patterns400C of the hard mask layer, and may be substantially maintained without being removed by etching. As the portions of the bit line plugs210C are removed, the width of the bit line plug210CA may be reduced to be substantially equal to or similar to the width of the bit line pattern300C. An insulating layer may fill the gap portions210CH generated next to the bit line plugs210CA. After forming the bit line patterns300C, the second shielding pattern330may be removed.

Referring back toFIG.12, one processing may simultaneously etch and remove some portions of the first conductive layer300, exposed by the first patterns400C of the hard mask layer and the second pattern400P of the hard mask layer using the first patterns400C of the hard mask layer and the second pattern400P of the hard mask layer as etch masks. Because the first patterns400C of the hard mask layer and the second pattern400P of the hard mask layer have different line widths and are disposed at different densities, different etching loading effects may be applied to the first region100C and the second region100P of the semiconductor substrate100. Due to the difference in the etching loading effects applied in the first region100C and the second region100P of the semiconductor substrate100, etching defects may be caused in the stacks of the bit line patterns300C and the first patterns400C of the hard mask layer to be formed in the shapes shown inFIG.13. A defect in which the stacks of the bit line patterns300C and the first patterns400C of the hard mask layer fall over or tilt during the etching process or the subsequent cleaning process may be caused.

In the present disclosure, the etch forming of the gate pattern300P+210P using the first shielding pattern310as shown inFIG.15and the etch forming of the bit line patterns300C using the second shielding pattern330as shown inFIG.17may be performed separately from each other. Accordingly, it is possible to effectively suppress or reduce a problem in which etching defects are caused due to different etching loading effects according to the regions100C and100P. After the etch forming of the bit line patterns300C using the second shielding pattern330and the first patterns400C of the hard mask layer as shown inFIG.17, an etch forming of the gate patterns300P+210P may be performed using the first shielding pattern310as shown inFIG.15.

FIG.18is a schematic view illustrating formation of spacers620and630in the method of manufacturing a semiconductor device according to another embodiment.

Referring toFIGS.17and18, a first spacer610may be formed on a side of the stack structure including the first and second gate patterns300P and210P and the second pattern400P of the hard mask layer. The second spacers620may be formed on sides of the stack structures including the bit line patterns300C and the first patterns400C of the hard mask layer. While forming the second spacers620on the sides of the stack structures including the bit line patterns300C and the first patterns400C of the hard mask layer, the second spacer620may also be formed on the side of the first spacer610. An overlapping spacer630in which the first spacer610and the second spacer620overlap may be formed on the side of the first and second gate patterns300P and210P and the second pattern400P of the hard mask layer. The second spacers620may extend to fill the gap portions210CH formed on the sides of the bit line plugs210CA. Because the sides of the bit line plugs210CA are blocked by the second spacers620, unwanted connection defects between the bit line plugs210CA and other conductive elements may be suppressed.

Thereafter, an insulating layer700(as shown inFIG.18) covering the first and second gate patterns300P and210P, the second pattern400P of the hard mask layer, and the overlapping spacer630may be formed. The insulating layer700may extend to fill between the second spacers620.

The inventive concept has been disclosed in conjunction with the embodiments described above. Those skilled in the art will recognize that various modifications, additions and substitutions are possible, without departing from the scope of the present disclosure. Accordingly, the embodiments disclosed in the present specification should be considered from not a restrictive standpoint but rather an illustrative standpoint. The scope of the inventive concept is not limited to the above descriptions, and all of distinctive features of an equivalent scope should be construed as being included in the inventive concept.