Semiconductor memory device and manufacturing method thereof

A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a semiconductor memory device including air spacers and a manufacturing method thereof.

2. Description of the Prior Art

Dynamic random access memory (DRAM) is a kind of volatile storage device which is an indispensable key part of many electronic products. DRAM includes a great number of memory cells arranged for forming an array configured to store data. Each of the memory cells may be composed of a metal oxide semiconductor (MOS) transistor and a capacitor connected in series.

According to demands of products, the need to continuously increase the density of the memory cells in the array leads to more difficult and complex processes and design. For example, when the density of the memory cells increases, the distance between components in the memory cell becomes smaller and the influence of parasite capacitance becomes more obvious. Therefore, the related industries keep making efforts to design new structures and/or processes in order to reduce the parasite capacitance for improving the performance of the memory device.

SUMMARY OF THE INVENTION

It is one of the objectives of the present invention to provide a semiconductor memory device and a manufacturing method thereof. The formation condition of air spacers may be ensured by forming the air spacers before a step of forming storage node contact pads. The purposes of enhancing manufacturing yield and improving operation performance of the device may be achieved accordingly.

A manufacturing method of a semiconductor memory device is provided in an embodiment of the present invention. The manufacturing method includes the following steps. A semiconductor substrate is provided first. A plurality of bit line structures is formed on the semiconductor substrate. Each of the bit line structures is elongated in a first direction. A first sidewall spacer is formed on sidewalls of each of the bit line structures. A plurality of storage node contacts is formed on the semiconductor substrate. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming a plurality of stripe contact structures. Each of the stripe contact structures is elongated in the first direction and formed corresponding to a plurality of the storage node contacts. The first sidewall spacer formed at a first side of each of the bit line structures in a second direction is exposed by the first patterning process, and the first sidewall spacer formed at a second side of each of the bit line structures which is opposite to the first side in the second direction is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming a plurality of first air spacers.

A semiconductor memory device is provided by an embodiment of the present invention. The semiconductor memory device includes a semiconductor substrate, a plurality of bit line structures, a plurality of storage node contacts, a plurality of first air spacers, a plurality of first sidewall spacers, a plurality of second sidewall spacers, and a plurality of third sidewall spacers. The bit line structures are disposed on the semiconductor substrate. Each of the bit line structures is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction. The storage node contacts are disposed on the semiconductor substrate. Each of the storage node contacts is disposed between the bit line structures adjacent to one another in the second direction. Each of the first air spacers is disposed at a first side of each of the bit line structures in the second direction, and each of the first air spacers is disposed between one of the bit line structures and the storage node contact adjacent to the bit line structure. Each of the first sidewall spacers is disposed at a second side of each of the bit line structures, and the second side is opposite to the first side in the second direction. Each of the first sidewall spacers is disposed between one of the bit line structures and the storage node contact adjacent to the bit line structure. Each of the second sidewall spacers and each of the third sidewall spacers are disposed at the first side and the second side of each of the bit line structures. Each of the first sidewall spacers is disposed between one of the second sidewall spacers disposed at the second side and one of the third sidewall spacers disposed at the second side. Each of the first air spacers is disposed between one of the second sidewall spacers disposed at the first side and one of the third sidewall spacers disposed at the first side.

DETAILED DESCRIPTION

Please refer toFIGS. 1-13.FIGS. 1-13are schematic drawings illustrating a manufacturing method of a semiconductor memory device according to a first embodiment of the present invention.FIGS. 1, 3-6, 10, and 11are schematic drawings illustrating conditions in a memory cell region and a peripheral region.FIGS. 2, 7, 8, and 12are cross-sectional diagrams illustrating bit line structures and taken along a direction perpendicular to an elongation direction of the bit line structures.FIG. 9andFIG. 13are top view diagrams. Additionally,FIG. 8may be regarded as a cross-sectional diagram taken along a line A-A′ inFIG. 9, andFIG. 12may be regarded as a cross-sectional diagram taken along a line B-B′ inFIG. 13, but not limited thereto. The manufacturing method of the semiconductor memory device in this embodiment includes the following steps. As shown inFIG. 1andFIG. 2, a semiconductor substrate10is provided first. A memory cell region R1and a peripheral region R2may be defined on the semiconductor substrate10. A plurality of memory cells may be formed in the memory cell region R1, and other units other than the memory cells may be formed in the peripheral region R2, such as transistors configured to control signals transmitted by word lines and/orbit lines, but not limited thereto. The semiconductor substrate10may include silicon substrate, epitaxial silicon substrate, silicon germanium substrate, silicon carbide substrate or silicon-on-insulator (SOI) substrate, but not limited thereto. In this embodiment, a shallow trench isolation11may be formed in the memory cell region R1of the semiconductor substrate10for defining a plurality of active areas12in the memory cell region R1of the semiconductor substrate10. Additionally, a plurality of word lines22may be formed in the memory cell region R1of the semiconductor substrate10, and the word lines22in this embodiment may be buried word lines, but not limited thereto. The word lines22may be formed in the semiconductor substrate10by a buried configuration, a word line dielectric layer21may be formed between each of the word lines22and the semiconductor substrate10, and a word line cap layer23may be formed above and cover the word lines22. The word line dielectric layer21, the word lines22, and the word line cap layer23as mentioned above may be formed by forming a plurality of trenches in the semiconductor substrate10and forming the word line dielectric layer21, the word lines22, and the word line cap layer23in the trenches, but not limited thereto. In some embodiments, other kinds of the word line structures may also be applied according to other considerations. In addition, the word line dielectric layer21may include silicon oxide or other suitable dielectric materials, the word lines22may include aluminum, tungsten, copper, titanium aluminide (TiAl), or other suitable conductive materials, and the word line cap layer23may include silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulation materials.

A plurality of bit line structures BL and at least one gate structure GS are then formed on the semiconductor substrate10. Each of the bit line structures BL is elongated in a first direction D1, and the bit line structures BL may be repeatedly disposed and arranged in a second direction D2. In some embodiments, the bit line structures BL and the gate structure GS may be formed in the memory cell region R1and the peripheral region R2respectively by patterning a stack structure including multiple layers, but the present invention is not limited to this. The bit line structures BL and the gate structure GS may be also be formed by different processes and/or different materials according to other considerations. For instance, a stack structure including a non-metal conductive layer41, a barrier layer42, a metal layer43, and a cap layer44stacked sequentially may be formed on the semiconductor substrate10, and the stack structure may be patterned for forming the bit line structures BL and the gate structure GS. The non-metal conductive layer41may include polysilicon, amorphous silicon, or other non-metal conductive layer including silicon or not. The barrier layer42may include titanium, tungsten silicide (WSi), tungsten nitride (WN), or other appropriate barrier materials. The metal layer43may include aluminum, tungsten, copper, titanium aluminide, or other suitable metal conductive materials with low electrical resistivity. The cap layer44may include silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulation materials. Accordingly, each of the bit line structures BL may include a first non-metal conductive layer41A, a first barrier layer42A, a first metal layer43A, and a bit line cap layer44A stacked sequentially, and the gate structure GS may include a second non-metal conductive layer41B, a second barrier layer42B, a second metal layer43B, and a gate cap layer44B, but not limited thereto. Additionally, before the step of forming the stack structure mentioned above, an insulation layer31may be formed on the memory cell region R1of the semiconductor substrate10and cover the word line cap layer23and the active areas12, and a gate dielectric layer32may be formed on the peripheral region R2of the semiconductor substrate10for being used as a gate insulation layer in a transistor corresponding to the gate structure GS, but not limited thereto.

Dielectric layers, such as a first dielectric layer45and a second dielectric layer46shown inFIG. 1, may be formed on the gate structure GS in the peripheral region R2, and spacers may be formed on sidewalls of the gate structure GS by etching the dielectric layers, but not limited thereto. Additionally, one or more spacers may be formed on sidewalls of each of the bit line structures BL. The spacers formed on the sidewalls of each of the bit line structures BL and the spacers formed on the sidewalls of the gate structure GS may be formed together by the same process or be formed respectively by different processes according to different considerations. In this embodiment a first sidewall spacer S1may be formed on the sidewalls of each of the bit line structures BL. In some embodiments, a second sidewall spacer S2and a third sidewall spacer S3may be formed on the sidewalls of each of the bit line structures BL, but not limited thereto. The second sidewall spacer S2is disposed between the first sidewall spacer S1and each of the bit line structures BL, and the first sidewall spacer S1is disposed between the second sidewall spacer S2and the third sidewall spacer S3. In addition, a source/drain region SD may be formed in the semiconductor substrate10, and a third dielectric layer48may be formed and cover the source/drain region SD, but not limited thereto.

As shown inFIG. 1andFIG. 2, the manufacturing method in this embodiment may further include forming a plurality of storage node contacts51in the memory cell region R1, and each of the storage node contacts51is formed corresponding to and electrically connected to at least one of the active areas12. The storage node contacts51may be formed by forming an isolation structure47including a plurality of openings on the semiconductor substrate10, filling the openings of the isolation structure47with a conductive material, and performing an etching back process to the conductive material. Accordingly, a top surface of each of the storage node contacts51may be lower than a top surface of the isolation structure47in a vertical direction D3, and the top surface of each of the storage node contacts51may be higher than a top surface of the semiconductor substrate10, but not limited thereto. The storage node contacts51may include silicon, such as polysilicon, amorphous silicon, or other conductive materials containing silicon. In some embodiments, the storage node contacts51may also be formed by other manufacturing methods and/or other materials according to other considerations. In addition, a metal silicide layer52may be formed on each of the storage node contacts51for lowering a contact resistance between each of the storage node contacts51and a conductive structure subsequently formed on the storage node contact51, but not limited thereto.

A conductive layer62is then formed and covers the bit line structures BL, the first sidewall spacer S1, and the storage node contacts51. Specifically, a plurality of first recesses V1may be formed in the isolation structure47by the above mentioned etching back process of forming the storage node contacts51, and each of the first recesses V1may be formed corresponding to at least one of the storage node contacts51in the vertical direction D3. In some embodiments, the third dielectric layer48may be partly formed in the memory cell region R1, and a second recess V2penetrating the third dielectric layer48and the insulation layer31may be formed and expose the corresponding word line22before the step of forming the conductive layer62. In some embodiments, the conductive layer62may further cover the gate structure GS and the source/drain region SD, and a third recess V3and a fourth recess V4may be formed before the step of forming the conductive layer62. The third recess V3may penetrate the gate cap layer44B and expose the second metal layer43B in the gate structure GS, and the fourth recess V4may penetrate the third dielectric layer48in the peripheral region R2and expose a part of the source/drain region SD, but not limited thereto. In some embodiments, each of the first recesses V1, the second recess V2, the third recess V3, and the fourth recess V4may be filled with the conductive layer62, and a patterning process subsequently performed to the conductive layer62may be used to form storage contact pads, a word line contact structure, a gate contact structure, and a source/drain contact structure, but not limited thereto. Additionally, the conductive layer62may include aluminum, tungsten, copper, titanium aluminide, or other suitable metal conductive materials with low electrical resistivity, and a third barrier layer61may be formed before the step of forming the conductive layer62for keeping the material of the storage node contacts51from diffusing into the conductive layer62, but not limited thereto. In some embodiments, a hard mask layer63may be formed on the conductive layer62for the subsequent patterning process, but not limited thereto.

As shown inFIG. 3, a first patterning process is preformed to the conductive layer62for forming a plurality of stripe contact structures62A. Each of the stripe contact structures62A is elongated in the first direction D1and formed corresponding to a plurality of the storage node contacts51. In some embodiments, the first patterning process performed to the conductive layer62may also be used to form a word line contact structure62C and forma gate contact structure62G and a source/drain contact structure62S in the peripheral region R2, but not limited thereto. In other words, the conductive layer62disposed on the gate structure GS may be patterned by the first patterning process for forming the gate contact structure62G, and the conductive layer62disposed on the source/drain region SD may be patterned by the first patterning process for forming the source/drain contact structure62S.

As shown inFIGS. 3-7, in some embodiments, the first patterning process may include but is not limited to the following steps. As shown inFIG. 3, the conductive layer62is etched for forming the stripe contact structures62A. As shown inFIG. 4, a dielectric layer (such as a fourth dielectric layer71shown inFIG. 4) is then formed covering the stripe contact structures62A after the step of forming the stripe contact structures62A. In some embodiments, the fourth dielectric layer71may be formed in the memory cell region R1and the peripheral region R2completely, and the fourth dielectric layer71may cover the gate contact structure62G and the source/drain contact structure62S, but not limited thereto. As shown inFIGS. 5-7, an etching back process is then performed to the fourth dielectric layer71for exposing the first sidewall spacer S1formed at a first side E1of each of the bit line structures BL. In some embodiments, a patterned mask layer80may be formed and cover the peripheral region R2before the etching back process, and a part of the patterned mask layer may further cover an edge part of the stripe contact structure62A, but not limited thereto. The patterned mask layer80may be used to protect the components in the peripheral region R2from the influence of the etching back process of the fourth dielectric layer, and the patterned mask layer80may be removed after the etching back process.

Additionally, in some embodiments, a top portion of each of the stripe contact structures62A may be slightly dislocated to the corresponding storage node contact51in the vertical direction D3. Therefore, the first sidewall spacer S1formed at the first side E1of each of the bit line structures BL in the second direction D2is exposed by the first patterning process, and the first sidewall spacer S1formed at a second side E2of each of the bit line structures BL which is opposite to the first side E1in the second direction D2is covered by the stripe contact structures62A. In some embodiments, the top portions of the stripe contact structures62A may cover the first sidewall spacer S1, the second sidewall spacer S2, and the third sidewall spacer S3which are formed at the second side E2of each of the bit line structures BL in the vertical direction D3. The first sidewall spacer S1, the second sidewall spacer S2, and the third sidewall spacer S3formed at the first side E1of each of the bit line structures BL are not covered by the stripe contact structures62A in the vertical direction D3. Therefore, after the etching back process performed to the fourth dielectric layer71, the first sidewall spacer S1, the second sidewall spacer S2, and the third sidewall spacer S3formed at the first side E1of each of the bit line structures BL will be exposed, but not limited thereto. In addition, a fourth sidewall spacer71S may be formed on sidewalls of each of the stripe contact structures62A by the etching back process performed to the fourth dielectric layer71, but not limited thereto.

As shown inFIGS. 7-9, the first sidewall spacer S1exposed by the first patterning process is then removed for forming a plurality of first air spacers A1. The first sidewall spacer S1may be removed by an etching process with higher etching selectivity, such as a wet etching process, but not limited thereto. In some embodiments, other suitable etching processes may also be used to remove the first sidewall spacer S1according to other considerations. Additionally, the second sidewall spacer S2and the third sidewall spacer S3adjacent to the first sidewall spacer S1may be formed by materials with high etching selectivity to the material of the first sidewall spacer S1preferably. In other words, the material of the first sidewall spacer S1may be different from the material of the second sidewall spacer S2and the material of the third sidewall spacer S3. For example, the first sidewall spacer S1may include an oxide spacer, and the second sidewall spacer S2and the third sidewall spacer S3may include a nitride spacer respectively, but not limited thereto. Because the first sidewall spacer S1formed at the first side E1of each of the bit line structures BL is not covered by the stripe contact structures62A, the etching process mentioned above may be used to remove the first sidewall spacer S1formed at the first side E1of each of the bit line structures BL effectively and form the first air spacer A1even if the density of the memory cells increases and the thickness of the first sidewall spacer S1in the second direction D2has to be reduced. When the first sidewall spacer S1is partially covered by other components in a wet etching process and the first sidewall spacer S1has to be etched by side etching effect of the wet etching process for forming the air spacer, there will be some problems such as under etching and/or longer etching time, and these problems may be avoided by the manufacturing method of the present invention. Each of the first air spacers A1is elongated in the first direction D1and disposed between the corresponding bit line structure BL and a plurality of storage node contacts51arranged in the first direction D1for effectively reducing the parasite capacitance of the bit line structure BL. Accordingly, the purposes of enhancing manufacturing yield and improving device operation performance may be achieved by the design of the present invention.

As shown inFIGS. 8-10, after the step of forming the first air spacers A1, a second patterning process may be performed to the stripe contact structures62A for forming a plurality of storage node contact pads62B. In some embodiments, each of the storage node contact pads62B is formed corresponding to one of the storage node contacts51, and each of the storage node contact pads62B is electrically connected with the corresponding storage node contact51, but not limited thereto. As shown inFIGS. 10-13, a fifth dielectric layer72may be formed and cover the storage node contact pads62B, the space between the storage node contact pads62B may be filled with the fifth dielectric layer72, and the fifth dielectric layer72and the hard mask layer63on the storage node contact pads62B in the vertical direction D3may be removed by an etching back process for exposing the storage node contact pads62B. The fifth dielectric layer72may be formed by a material and/or a process with worse gap-fill ability for ensuring that the fifth dielectric layer72is not formed in the first air spacers A1.

A semiconductor memory device101shown inFIGS. 11-13may be formed by the manufacturing process described above. The semiconductor memory device101includes the semiconductor substrate10, a plurality of the bit line structures BL, a plurality of the storage node contacts51, a plurality of first air spacers A1, a plurality of first sidewall spacers S1, a plurality of second sidewall spacers S2, and a plurality of third sidewall spacers S3. The bit line structures BL and the storage node contacts51are disposed on the semiconductor substrate10. Each of the bit line structures BL is elongated in the first direction D1, and the bit line structures BL are repeatedly disposed in the second direction D2. In some embodiments, the first direction D1may be perpendicular to the second direction D2, but not limited thereto. Each of the storage node contacts51is disposed between the bit line structures BL adjacent to one another in the second direction D2. Each of the first air spacers A1is disposed at the first side E1of each of the bit line structures BL in the second direction D2, and each of the first air spacers A1is disposed between one of the bit line structures BL and the storage node contact51adjacent to the bit line structure BL. Each of the first sidewall spacers S1is disposed at the second side E2of each of the bit line structures BL, and the second side E2is opposite to the first side E1in the second direction D2. Each of the first sidewall spacers S1is disposed between one of the bit line structures BL and the storage node contact51adjacent to the bit line structure BL. Each of the second sidewall spacers S2and each of the third sidewall spacers S3are disposed at the first side E1and the second side E2of each of the bit line structures BL. Each of the first sidewall spacers S1is disposed between one of the second sidewall spacers S2disposed at the second side E2and one of the third sidewall spacers S3disposed at the second side E2. Each of the first air spacers A1is disposed between one of the second sidewall spacers S2disposed at the first side E1and one of the third sidewall spacers S3disposed at the first side E1. In other words, in some embodiments, the first air spacers A1may be disposed at only one side of each of the bit line structures BL in the second direction D2, but not limited thereto. Additionally, the semiconductor memory device101may further include a plurality of the storage node contact pads62B. Each of the storage node contact pads62B is disposed on one of the storage node contacts51, and each of the storage node contact pads62B is electrically connected to the corresponding storage node contact51. The storage node contact pads62B cover at least a part of the first sidewall spacers S1in the vertical direction D3. Specifically, the first sidewall spacer S1disposed at the second side E2of each of the bit line structures BL is partially covered by the storage node contact pads62B. The first air spacer A1, the second sidewall spacer S2, and the third sidewall spacer S3disposed at the first side E1of each of the bit line structures BL are not covered by the storage node contact pads62B. Each of the first air spacers A1is elongated in the first direction D1, and a length of each of the first air spacers A1in the first direction D1is longer than a length of each of the storage node contact pads62B in the first direction D1. In some embodiments, the length of each of the first air spacers A1in the first direction D1may be larger than double or triple the length of each of the storage node contact pads62B in the first direction D1.

The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.

Please refer toFIG. 14andFIG. 11.FIG. 14is a schematic drawing illustrating a manufacturing method of a semiconductor memory device according to a second embodiment of the present invention, andFIG. 11may be regarded as a schematic drawing in a step subsequent toFIG. 14. As shown inFIG. 14andFIG. 11, the difference between the manufacturing method in this embodiment and the manufacturing method in the first embodiment mentioned above is that, in this embodiment, the conductive layer62disposed on the gate structure GS and the source/drain region SD are patterned for forming the gate contact structure62G and the source/drain contact structure62S after the first patterning process described above.

Please refer toFIG. 15andFIG. 13.FIG. 15is a schematic drawing illustrating a manufacturing method of a semiconductor memory device102according to a third embodiment of the present invention.FIG. 15may be regarded as a schematic drawing in a step subsequent toFIG. 13. As shown inFIG. 13andFIG. 15, the difference between the manufacturing method in this embodiment and the manufacturing method in the first embodiment mentioned above is that, after the step of forming the storage node contact pads62B, the first sidewall spacer S1which is formed at the second side E2of each of the bit line structures BL and is not covered by the storage node contact pads62B may be removed for forming a plurality of second air spacers A2. At least a part of the second air spacers A2are repeatedly disposed in the first direction D1, and a part of the first sidewall spacer S1is disposed between the second air spacers A1adjacent to one another in the first direction D1. A length of each of the second air spacers A2in the first direction D1is shorter than the length of each of the first air spacers A1in the first direction D1because the first sidewall spacer51disposed at the second side E2of each of the bit line structures BL is partially covered by the storage node contact pads62B. Additionally, the first sidewall spacer51is divided into a plurality of fifth sidewall spacers S11arranged in the first direction by the second air spacers A2. A length of each of the fifth sidewall spacers S11in the first direction D1may be equal to or shorter than the length of each of the storage node contact pads62B in the first direction D1. Compared with the first embodiment, the semiconductor memory device102in this embodiment may further include a plurality of the second air spacers A2. Each of the second air spacers A2is disposed at the second side E2of each of the bit line structures BL, and each of the second air spacers A2is disposed between one of the second sidewall spacers S2disposed at the second side E2and one of the third sidewall spacers S3disposed at the second side E2. Additionally, in the top view diagram of the semiconductor memory device102, each of the storage node contact pads62is at least partially disposed between the second air spacers A2adjacent to one another in the first direction D1. The second air spacers A2may be used to further reduce the parasite capacitance of the bit line structures BL, and the operation performance of the semiconductor memory device102may be further improved accordingly.

To summarize the above descriptions, according to the semiconductor memory device and the manufacturing method thereof in the present invention, the first sidewall spacer disposed at one side of each of the bit line structures may be removed for forming the air spacers before the step of forming the storage node contact pads. The etching process may be used to remove the first sidewall spacer formed at the first side of each of the bit line structures effectively and form the required air spacers because the first sidewall spacer formed at the first side of each of the bit line structures is not covered by the stripe contact structures or the storage node contact pads. When the sidewall spacer is partially covered by other components in a wet etching process and the sidewall spacer has to be etched by side etching effect of the wet etching process for forming the air spacer, there will be some problems such as under etching and/or longer etching time, and these problems may be avoided by the manufacturing method of the present invention. The purposes of enhancing manufacturing yield and improving device operation performance may be achieved accordingly.