Vertically oriented metal silicide containing e-fuse device and methods of making same

One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to various embodiments of a novel vertically oriented metal silicide containing e-fuse device and methods of making such a device.

2. Description of the Related Art

The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that substantially determines performance of such integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors, are formed on a substrate including a crystalline semiconductor layer. A field affect transistor, whether an NMOS or a PMOS device, is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate structure positioned above the channel region. The gate structure is typically comprised of a very thin gate insulation layer and one or more conductive layers that act as a conductive gate electrode. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by applying an appropriate voltage to the gate electrode.

Field effect transistors come in a variety of different configurations, e.g., planar devices, FinFET devices, vertical transistor devices, etc. As technology advances, there is a constant demand to reduce the overall size of the IC products to reduce the size of the consumer products incorporating such IC products. Vertical transistor devices, with their vertically oriented channel structure, present one promising choice for advanced IC products given the potential space savings achieved by using such devices. Modern integrated circuit (IC) products typically include a very large number of active individual circuit elements, such as field effect transistors, as well as numerous passive circuit elements, such as capacitors, resistors and the like. These circuit elements are combined in various arrangements to make integrated circuits that perform a variety of functions so as to enable the IC product to perform its intended function.

For a variety of reasons, the various circuit portions may have significantly different performance capabilities, for instance with respect to useful lifetime, reliability and the like. For example, the operating speed of a digital circuit portion, such as a CPU core and the like, may depend on the configuration of the individual transistor elements and also on the characteristics and performance of the metallization system coupled to the CPU core. Consequently, the combination of the various circuit portions in a single semiconductor device may result in a significantly different behavior with respect to performance and reliability. Variations in the overall manufacturing process flow may also contribute to further variations in the performance capabilities between various circuit portions. For these reasons, in complex integrated circuits, frequently, additional mechanisms are used so as to allow the circuit itself to adapt or change the performance of certain circuit portions to comply with the performance characteristics of other circuit portions. Such mechanisms are typically used after completing the manufacturing process and/or during use of the semiconductor device. For example, when certain critical circuit portions no longer comply with corresponding device performance criteria, adjustments may be made, such as re-adjusting an internal voltage supply, re-adjusting the overall circuit speed and the like, to correct such underperformance.

In computing, e-fuses are used as a means to allow for the dynamic, real-time reprogramming of computer chips. Speaking abstractly, computer logic may generally be “etched” or “hard-coded” onto a silicon chip and cannot be changed after the chip has been manufactured. By utilizing an e-fuse, or a number of individual e-fuses, a chip manufacturer can change some aspects of the circuits on a chip. If a certain sub-system fails, or is taking too long to respond, or is consuming too much power, the chip can instantly change its behavior by blowing an e-fuse. Programming of an e-fuse is typically accomplished by forcing a large electrical current through the e-fuse. This high current is intended to break or rupture a portion of the e-fuse structure, which results in an “open” electrical path. In some applications, lasers are used to blow e-fuses. Fuses are frequently used in integrated circuits to program redundant elements or to replace identical defective elements. Further, e-fuses can be used to store die identification or other such information, or to adjust the speed of a circuit by adjusting the resistance of the current path. Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower power consumption relative to previous device generations. This drive applies to the manufacture and use of e-fuses as well.

The present disclosure is directed to various embodiments of a novel vertically oriented metal silicide containing e-fuse device for use on integrated circuit (IC) products, methods of making such e-fuse devices and IC products and the resulting IC products.

SUMMARY OF THE INVENTION

Generally, the present disclosure is directed to various embodiments of a novel vertically oriented metal silicide containing e-fuse device for use on integrated circuit products, methods of making such e-fuse devices and products and the resulting integrated circuit products. One illustrative method disclosed herein includes forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, wherein at least a portion of the vertical height of the VOS structure is a conductive silicide vertically oriented e-fuse, wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.

Another illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, wherein at least a portion of the vertical height of the VOS structure is a conductive silicide vertically oriented e-fuse, wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and first and second doped regions in the semiconductor substrate, wherein the first and second doped regions are oppositely doped and constitute a diode and wherein one of the first and second doped regions is positioned vertically below the VOS structure.

DETAILED DESCRIPTION

The present disclosure generally relates to various embodiments of a novel vertically oriented metal silicide e-fuse device for use on IC products, methods of making such e-fuse devices and IC products and the resulting IC products. As will be appreciated by those skilled in the art after a complete reading of the present application, the methods disclosed herein may be employed to form a gate structure-to-source/drain conductive contact structure in a variety of different applications. For example, the methods disclosed herein may be employed to form a gate structure-to-source/drain conductive contact structure on an SRAM device. Other applications where such cross-coupled contact structures may be employed include, but are not limited to, various devices that are typically found in the logic portion of an IC product, etc. Thus, the inventions disclosed and claimed herein should not be considered to be limited to any particular application where such cross-coupled contacts may be formed. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.

FIGS. 1-13are various views that depict one illustrative embodiment of a novel vertically oriented metal silicide containing e-fuse device for use on an IC product100, methods of making such e-fuse devices and IC products and the resulting IC product100. The product100will be formed in and above a semiconductor substrate102. The substrate102may have a variety of configurations, such as the bulk substrate configuration depicted herein or a semiconductor-on-insulator (SOI) configuration. Such an SOI substrate includes a bulk semiconductor layer, a buried insulation layer positioned on the bulk semiconductor layer and an active semiconductor layer positioned on the buried insulation layer, wherein the e-fuse devices disclosed herein are formed in and above the active layer. The active layer and/or the bulk semiconductor layer may be made of silicon or they may be made of semiconductor materials other than silicon, and they both do not have to be made of the same semiconductor material. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials.

FIG. 1depicts the IC product100after several process operations were performed. First, a vertically oriented semiconductor (VOS) structure106was formed in the substrate102. The VOS structure106was formed by performing one or more etching processes through a patterned etch mask104so as to define a plurality of trenches105in the substrate102. In the illustrated examples, the VOS structures106have a rectangular cross-section when viewed from above. In other embodiments, the VOS structures106may have a different cross-sectional shape, such as circle, oval, square, etc., as shown in the upper left-hand portion ofFIG. 1. The patterned etch mask104is intended to be representative in nature as it may be comprised of multiple layers of material, such as, for example, the depicted silicon dioxide layer104A and the silicon nitride layer104B. Thus, the particular form and composition of the patterned etch mask104should not be considered a limitation of the presently disclosed inventions. As initially formed, the VOS structure106has a dimension106W (e.g., a lateral width), the magnitude of which may vary depending upon the particular application. In one illustrative embodiment, the VOS structure106may be formed at the same time as various vertically oriented channel semiconductor structures (not shown) are formed for various vertical transistor devices (not shown) that will be formed on the substrate102.

FIG. 2depicts the product100after several process operations were performed. First, a layer of insulating material108, such as silicon dioxide, was deposited so as to over-fill the trenches105such that insulating material108was positioned above the upper surface of the patterned etch mask104. Thereafter, a CMP process was performed to planarize the upper surface of the deposited layer of insulating material108with the upper surface of the patterned etch mask104. Then, a patterned mask layer110, e.g., a patterned layer of photoresist, with an opening110A formed therein, was formed above the layer of insulating material108. The opening110A is positioned above the VOS structure106. Of course, in a real-world setting, the opening110A may be made much larger so as to expose the patterned etch mask104above each of several VOS structures106that are formed across the substrate.

FIG. 3depicts the product after a first doped region112and a second doped region114were formed in the VOS structure106. As will be described more fully below, the first and second doped regions112,114are oppositely-doped regions that define a P/N junction and a diode structure116. In one illustrative embodiment, the first doped region112may be a P-doped region, while the second doped region114may be an N-doped region, wherein the diode116would allow electron current flow in the direction113and block electron current flow in the direction115. The concentration of dopant atoms in the first and second doped regions112,114may vary depending upon the particular application, and the dopant concentration in each of the first and second doped regions112,114need not be the same, although that may be the case in some situations. In one illustrative embodiment, the doped regions112,114may be formed by performing separate ion implantation processes through the patterned mask layer110. The dopant dose and implant energy used during such ion implantation processes to form the first and second doped regions112,114may vary depending upon the particular application. Additionally, the vertical position of the first and second doped regions112,114along the vertical height of the VOS structure106may vary depending upon the particular application.

FIG. 4depicts the product100after several process operations were performed. First, the patterned mask layer110was removed. Then, a recess etching process was performed to recess the layer of insulating material108such that it has a recessed upper surface108R that exposes a portion of the vertical height of the VOS structure106. The amount of recessing of the layer of insulating material108may vary depending upon the particular application. In general, the layer of insulating material108should be recessed to a degree such that a significant portion (if not all) of the first doped region112is positioned above the recessed surface108R. Next, a simplistically-depicted sidewall spacer118was formed adjacent the exposed portion of the VOS structure106and above the recessed layer of insulating material108. The sidewall spacer118was formed by performing a conformal deposition process to form a conformal layer of spacer material above the VOS structure106and above the recessed layer of insulating material108. Thereafter, an anisotropic etching process was performed to remove the horizontally positioned portions of the layer of spacer material, thereby leaving the sidewall spacer118positioned on opposite sidewalls of the VOS structure106. The sidewall spacer118may be made of any desired material that may be selectively etched relative to the material of the recessed layer of insulating material108, e.g., silicon nitride, silicon oxynitride, etc., when the recessed layer of insulating material108is made of silicon dioxide. The thickness of the sidewall spacer118(at its base) may vary depending upon the particular application.

FIG. 5depicts the product100after an etching process was performed to remove the recessed layer of insulating material108. This process operation exposes a portion of the vertical height of the VOS structure106below the diode116for further processing.

FIG. 6depicts the product100after a VOS structure trimming etch process, e.g., an isotropic etching process, was performed to reduce the lateral width of the exposed portion of the VOS structure106. However, it should be noted that the VOS structure trimming etch process may not be performed in at least some applications. More specifically, the process operation results in the formation of a trimmed portion of the VOS structure106having a lateral width106X that is less than a lateral width106W of the initial VOS structure106. The amount of trimming or thinning of the trimmed portion of the VOS structure106relative to the un-trimmed initial VOS structure106may vary depending upon the particular application. For example, in some applications, the lateral width106X of the trimmed portion of the VOS structure106may be about 50% less than the lateral width106W of the initial VOS structure106. In some applications, the lateral width106X of the trimmed portion of the VOS structure106may be on the order of a few nanometers. As noted above, the axial length (or vertical height) of the initial VOS structure106that is exposed to this trimming process may vary depending upon the particular application.

FIG. 7depicts the product after various well-known metal silicide formation process operations were performed to form metal silicide material120on the product100. More specifically, a conformal layer of metal (not shown) was deposited on the product by performing a conformal deposition process. Thereafter, a heating or anneal process was performed to cause the layer of metal to react with the exposed portions of the substrate102and the exposed portion of the VOS structure106(which in the depicted example has been trimmed) and thereby form the metal silicide material120. Then, unreacted portions of the layer of metal were stripped from the product100. In some cases, a second anneal process may be performed after the unreacted metal has been removed. These process operations result in the formation of a conductive metal silicide region120A in the substrate102and the formation of a conductive silicide vertically oriented e-fuse106F. In the depicted example, the metal silicide material120extends throughout the entire dimension106X (i.e., lateral width) of the trimmed portion of the VOS structure106for at least some portion of the axial length (i.e., vertical height) of the trimmed portion of the VOS structure106. In some cases, the metal silicide material120extends throughout the entire dimension106X (i.e., lateral width) of the trimmed portion of the VOS structure106for substantially the entire axial length (i.e., vertical height) of the VOS structure106. The metal silicide material120may be formed to any desired thickness, and it may be comprised of any desired material, e.g., cobalt silicide, titanium silicide, nickel silicide, etc. The conductive metal silicide region120A in the semiconductor substrate102is conductively coupled to the conductive silicide vertically oriented e-fuse106F. As described more fully below, during operations, an electrical current will flow through the conductive silicide vertically oriented e-fuse106F and the conductive metal silicide region120A. The conductive silicide vertically oriented e-fuse106F has a cross-sectional current flow area A1that is equal to the dimension107X times the dimension107Y. The conductive metal silicide region120A has a cross-sectional current flow area A2that is equal to the dimension120X times120Y. Importantly, the flow area A1of the conductive silicide vertically oriented e-fuse106F is less than the flow area A2of the conductive metal silicide region120A. \The difference between the size of the cross-sectional areas A1and A2may vary depending upon the particular application. In one illustrative embodiment, the area A1may be at least 25% smaller than the area A2.

FIG. 8is a cross-sectional view that depicts the product100after various process operations were performed to form various conductive structures that are conductively coupled to the vertically oriented e-fuse106F.FIG. 9is a plan view of a unit cell comprising the conductive silicide vertically oriented e-fuse106F after the formation of the various conductive structures shown inFIG. 8. In terms of process operations, a layer of insulating material122was initially formed above the product100. In one embodiment, the layer of insulating material122was formed by performing a deposition process so as to over-fill the trenches105with insulating material. Thereafter, several process operations, such as etching, cleaning and CMP, were performed to planarize the upper surface of the layer of insulating material122and remove the patterned etch mask104and expose the second doped region114. The layer of insulating material122is intended to be representative in nature as it may be comprised of one or more layers of insulating material, e.g., silicon dioxide, silicon nitride, a low-k material, etc. Then, a conductive contact structure124that is conductively coupled to the metal silicide region120A was formed in the layer of insulating material122. The conductive contact structure124may be formed by performing one or more etching processes through a patterned etch mask (not shown) to remove exposed portions of the layer of insulating material122and define an opening125that exposes the metal silicide region120A. Thereafter, one or more conductive materials are formed in the opening125and a CMP process was performed to remove excess amounts of the conductive materials positioned above the upper surface of the layer of insulating material122. At that point, conductive contact structures128,130may be formed in another layer of insulating126, wherein the contact structure128conductively contacts to the conductive contact structure124and the contact structure130conductively contacts the diode116. After forming contact openings in the layer of insulating material126, if desired, a metal silicide material (not shown) may be formed on the doped region114to reduce contact resistance. The conductive contact structures128,130are intended to be representative in nature as they may be of any desired size, shape or configuration, and they may be comprised of any desired conductive material. In one illustrative example, the conductive contact structures128,130may be formed at the same time as various source/drain (CA) contact structures (not shown) and various gate (CB) contact structures (not shown) are formed for various transistor devices (not shown) that are formed above the substrate102. Additionally, the layer of insulating material126is intended to be representative in nature as it may be comprised of one or more layers of insulating material, e.g., silicon dioxide, silicon nitride, a low-k material, etc.

Also depicted inFIGS. 8 and 9is a simplistically depicted illustrative metallization layer, e.g., the M1 metallization layer, for the IC product100that was formed above the layer of insulating material126. In practice, the M1 metallization layer may comprise conductive vias134and136(also referred to as “V0” structures) and conductive lines135and137(also referred to as “M1” lines) that are formed in a layer of insulating material132. In general, the M1 level is the first major wiring level of the product100that establishes the means by which the various circuits formed on the product are conductively coupled together to form a functioning integrated circuit product. Typically, a modern integrated circuit product will have several metallization layers formed above the M1 metallization layer. As will be appreciated by those skilled in the art after a complete reading of the present application, the conductive line135of the M1 metallization layer will function as a word line for a single unit cell (that comprises a single conductive silicide vertically oriented e-fuse106F) when a plurality of such unit cells are arranged in a one-time programmable memory array, as disclosed more fully below.

FIG. 10is a cross-sectional view that depicts the product100after various process operations were performed to form a second metallization layer (“M2/V1”) above the M1 metallization layer.FIG. 11is a plan view of a unit cell (that comprises a single conductive silicide vertically oriented e-fuse106F) after the formation of the M2 metallization layer. The M2 metallization layer comprises a via142(also referred to as “V1” structure) and a conductive line140(also referred to as an “M2” line) that are formed in a layer of insulating material138. The layer of insulating material138is intended to be representative in nature as it may be comprised of one or more layers of insulating material, e.g., silicon dioxide, silicon nitride, a low-k material, etc. As will be appreciated by those skilled in the art after a complete reading of the present application, the conductive line140of the M2 metallization layer will function as a bit line for a single unit cell (that comprises a single conductive silicide vertically oriented e-fuse106F) when a plurality of such unit cells are arranged in a one-time programmable memory array, as disclosed more fully below.

With reference toFIG. 10, as initially formed, the silicide vertically oriented e-fuse106F is adapted to be part of a conductive flow path for an electron current150that is generated by application of appropriate voltages to the conductive structures128,130. In the depicted example, the electron current150is depicted as flowing downward through the silicide vertically oriented e-fuse106F, through the metal silicide region120A and upward through the conductive structure124. Given the relatively smaller size (cross-sectional area) of the silicide vertically oriented e-fuse106F as compared to the size of the metal silicide region120A formed in the substrate102, there will be a higher electron current density in the silicide vertically oriented e-fuse106F. Thus, by having the electron current150pass downward into the metal silicide region120A, the relatively higher density electron current flowing through the silicide vertically oriented e-fuse106F may be more readily dissipated into the larger area provided by the metal silicide region120A. The direction of flow of the electron current150may be controlled by a variety of techniques. For example, the direction of flow of the electron current150may be controlled by changing the polarity of the voltages applied to the conductive contacts128,130and by doping of the first and second doped regions112,114to form a P-N configuration. As will be appreciated by those skilled in the art after a complete reading of the present application, the silicide vertically oriented e-fuse106F is designed such that, when sufficient electron electrical current is passed through the silicide vertically oriented e-fuse106F, the e-fuse106F will rupture and thereby prevent the flow of electron current through the e-fuse106F, i.e., the conductive flow path through the e-fuse106F will be broken. Rupturing the e-fuse106F may also be referred to as programming the e-fuse106. The magnitude of the current needed to rupture the e-fuse106F may vary depending upon the particular application.

FIG. 12is a simplistic plan view of one illustrative embodiment of a one-time programmable memory array200disclosed herein that is comprised of a plurality of unit cells, each of which comprises a single silicide vertically oriented e-fuse106F disclosed herein. As indicated above, in one embodiment, a conductive line135of the M1 metallization layer functions as a word line for each of the unit cells arranged along a given row in the array200, while a conductive line140of the M2 metallization layer functions as a bit line for each of the unit cells arranged in a particular column of the array200. A single unit cell within the array200may be accessed by applying an appropriate voltage to one of the word lines and one of the bit lines. At that point, the current may be increased to rupture the e-fuse106F for the particular unit cell that was accessed. The programed unit cell (with the ruptured e-fuse106F) may represent a logically high value (e.g., a “1”), while a non-programmed unit cell (with a non-ruptured e-fuse106F) may represent a logically low value (e.g., a “0”). Of course, if desired, the logical representation of the programmed and non-programmed unit cells may be reversed if desired.

FIG. 13is a simplistic schematic of the array200showing the schematically depicted diode116and the schematically depicted silicide vertically oriented e-fuse106F arranged in the array200. Of course, as noted above, the diode116may be configured such that current flow through the diode116will be in the direction opposite to that shown inFIG. 13.

FIGS. 14 and 15depict another illustrative embodiment of a novel vertically oriented metal silicide containing e-fuse device106F for use on an IC product100A.FIG. 14is a cross-sectional view of the e-fuse106F whileFIG. 15is a plan view of another illustrative embodiment of a one-time programmable memory array200A that comprises a plurality of silicide vertically oriented e-fuses106F. Relative to the previous embodiment, rather than individual unit cells each comprised of a separate metal silicide region120A and a separate conductive structure124, a single metal silicide region120B is formed in the substrate102, and a single contact structure131(seeFIG. 15—not shown inFIG. 14) is conductively coupled to the single metal silicide region120B. Also note that, in this embodiment, the single metal silicide region120B functions as the word line that permits individually accessing each of the e-fuses106F in the array200A. In this example, the conductive lines140in the M2 metallization layer may still function as the bit lines in the array200A. The conductive metal silicide region120B in the semiconductor substrate102is conductively coupled to the conductive silicide vertically oriented e-fuses106F. Similar to the embodiment discussed above, the conductive silicide vertically oriented e-fuse106F has a cross-sectional current flow area A1that is less than the flow area A2of the conductive metal silicide region120B.

FIGS. 16-21are various views of another illustrative embodiment of a novel vertically oriented metal silicide e-fuse device106F for use on an IC product100B. FIG.16depicts the product100B after the formation of the VOS structure106and the formation of the layer of insulating material108.

FIG. 17depicts the product100B after several process operations were performed. First, the layer of insulating material108was removed. Then, the above-described sidewall spacer118was formed adjacent the VOS structure106above the substrate102. In this example, the spacer118is formed such that it has a reduced height and does not cover the entire axial length (i.e., vertical height) of the VOS structure106, i.e., in one embodiment, the spacer118may only cover about ⅔ of the axial length of the VOS structure106. The reduced height spacer118may be formed using a variety of techniques. For example, the spacer118may be initially formed such that it covers the entire axial length of the VOS structure106. At that point, a recessed layer of insulating material (not shown), e.g., silicon dioxide, may be formed in the trenches adjacent the initial full-height sidewall spacer, wherein the recessed upper surface of the recessed layer of insulating material exposes the desired amount of the initial full-height spacer to be removed. The exposed portion of the initial full-height spacer is then removed by performing an etching process, and the recessed layer of insulating material is then removed. Then, a layer of insulating material141was blanket-deposited on the product. Next, a first CMP process was performed on the layer of insulating material141that stopped on the upper surface of the patterned etch mask104. The patterned etch mask104was then removed by performing an etching process. At that point, a second CMP process was performed that stopped on the upper surface106S of the VOS structure106such that the layer of insulating material141has a recessed upper surface141R.

FIG. 18depicts the product100B after several process operations were performed. First, an epitaxial growth process was performed to form a region of epitaxial semiconductor material127on the upper surface106S (seeFIG. 17) of the VOS structure106. Then, a layer of insulating material143(e.g., silicon dioxide) was blanket-deposited on the product. Next, a CMP process was performed on the layer of insulating material143that stopped at or near the uppermost surface of the epi material127.

FIG. 19depicts the product100B after several process operations were performed. First, the above-described patterned implant mask110was formed above the layer of insulating material143. Thereafter, the above-described first and second doped regions112,114were formed in the VOS structure106. However, in this embodiment, the first doped region112is formed such that it extends at least partially into the substrate102beneath the VOS structure106. As before, the size, depth and position of the doped regions112,114, as well as the dopants in the doped regions, may vary depending upon the particular application.

FIG. 20depicts the product100B after several process operations were performed. First, the patterned mask layer110and the layers of insulating materials143and141were removed. At that point, well-known metal silicide operations (described above) were performed to form the above-described metal silicide material120A in the substrate102and metal silicide material120C in the epi material127and the upper portion of the VOS structure106. The metal silicide material120C constitutes the above-described conductive silicide vertically oriented e-fuse106F. In this embodiment, the metal silicide process was performed in such a manner so that the metal silicide material extends under the sidewall spacer118but, in one example, does not consume the entire first doped region112.

FIG. 21depicts the product100B after several process operations were performed. First, a layer of insulating material147(e.g., silicon dioxide) was blanket-deposited on the product. Next, a CMP process was performed on the layer of insulating material147to planarize its upper surface. Then, various process operations were performed to form the above-described conductive structure130and the M1 metallization layer on the product100B. Note that, in this example, when the first doped region112is an N-doped region and the second doped region114is a P-doped region, the electron current150may flow vertically upward through the vertically oriented e-fuse106F.

FIGS. 22-28are various views of another illustrative embodiment of a novel vertically oriented metal silicide e-fuse device106F for use on an IC product100C.FIG. 22depicts the product100C at a point in processing after the formation of the VOS structure106, after the above-described layer of insulating material108was formed on the product and recessed, and after a CMP process was performed that exposes the upper surface106S of the VOS structure106.

FIG. 23depicts the product100C after the above-described epitaxial growth process was performed to form a region of the above-described epitaxial semiconductor material127on the upper surface106S of the VOS structure106.

FIG. 24depicts the product100C after several process operations were performed. First, a layer of insulating material153(e.g., silicon dioxide) was blanket-deposited on the product. Next, a CMP process was performed on the layer of insulating material153that stopped at or near the uppermost surface of the epi material127. Then, the above-described first and second doped regions112,114were formed in the substrate102so as to define the diode116. In the depicted example, the first doped region112is positioned vertically under the VOS structure106, while the second doped region114is positioned laterally adjacent the first doped region112. In one illustrative process flow, the doped regions112,114may be formed by performing separate ion implantation processes through separate patterned implant masking layers (not shown) that are formed above the substrate102.

FIG. 25depicts the product100C after one or more etching processes were performed to remove the layer of insulating material153and to recess the layer of insulating material108such that it has a recessed upper surface108R that exposes a portion of the VOS structure106. The amount of recessing of the layer of insulating material108may vary depending upon the particular application. In one illustrative embodiment, the recessing of the layer of insulating material108may expose substantially all of the VOS structure106.

FIG. 26depicts the product100C after several process operations were performed. At that point, well-known metal silicide operations (described above) were performed to form the above-described metal silicide material120in the VOS structure106. In the depicted example, the metal silicide material120extends throughout the entire lateral dimension (i.e., lateral width) of the exposed portion of the VOS structure106. These process operations result in the formation of the above-described conductive silicide vertically oriented e-fuse106F. The diode116(the combination of the first and second doped regions112,114) is conductively coupled to the conductive silicide vertically oriented e-fuse106F.

FIG. 27depicts the product100C after several process operations were performed. First, a layer of insulating material152, such as silicon dioxide, was deposited so as to over-fill the trenches105such that insulating material152was positioned above the upper surface of the epi material127. Thereafter, a CMP process was performed to planarize the upper surface of the deposited layer of insulating material152with the upper surface of the epi material127. At that point, the above-described conductive contact structure124was formed in the layer of insulating material152.

FIG. 28depicts the product100C after various process operations were performed to form the above-described conductive structures128,130and the M1 metallization layer on the product100C. Note that, in this example, when the first doped region112is a P-doped region and the second doped region114is an N-doped region, the electron current150may flow vertically upward through the vertically oriented e-fuse106F.