Semiconductor die singulation method

In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.

BACKGROUND

The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductors.

In the past, the semiconductor industry utilized various methods and equipment to singulate individual semiconductor die from a semiconductor wafer on which the die was manufactured. Typically, a technique called scribing or dicing was used to either partially or fully cut through the wafer with a diamond cutting wheel along scribe grids that were formed on the wafer between the individual die. To allow for the alignment and the width of the dicing wheel each scribe grid usually had a large width, generally about one hundred fifty (150) microns, which consumed a large portion of the semiconductor wafer. Additionally, the time required to scribe all of the scribe grids on the entire semiconductor wafer could take over one hour. This time reduced the throughput and manufacturing capacity of a manufacturing area.

Another method of singulating individual semiconductor die used lasers to cut through the wafers along the scribe grids. However, laser scribing was difficult to control and also resulted in non-uniform separation. Laser scribing also required expensive laser equipment as well as protective equipment for the operators.

Accordingly, it is desirable to have a method of singulating die from a semiconductor wafer that increases the number of semiconductor die on the wafer, that provides more uniform singulation, that reduces the time to perform the singulation, and that has a narrower scribe line.

For simplicity and clarity of the illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions generally may not be straight lines and the corners may not be precise angles. The terms first, second, third and the like in the claims or/and in the Detailed Description of the Drawings, as used in a portion of a name of an element are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein. The use of the word approximately or substantially means that a value of an element has a parameter that is expected to be close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to at least ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are reasonable variances from the ideal goal of exactly as described.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1is a reduced plan view graphically illustrating, in a general manner, an example of an embodiment of a semiconductor wafer10that has a plurality of semiconductor die, such as die12,14, and16, formed on semiconductor wafer10. Die12,14, and16are spaced apart from each other on wafer10by spaces in which singulation lines are to be formed, such as singulation lines13and15. As is well known in the art, all of the plurality of semiconductor die generally are separated from each other on all sides by areas where singulation lines such as lines13and15are to be formed.

FIG. 2illustrates an enlarged cross-sectional portion of wafer10ofFIG. 1taken along section line2-2. For clarity of the drawings and of the description, this section line2-2is illustrated to cross-section only die12and portions of dice14and16. Die12,14, and16may be any type of semiconductor die including a vertical transistor, a lateral transistor, or an integrated circuit that includes a variety of types of semiconductor devices. Semiconductor dice12,14, and16generally include a semiconductor substrate18that may have doped regions formed within substrate18in order to form active and passive portions of the semiconductor die. The cross-sectional portion illustrated inFIG. 2is taken along a contact pad24of each of dice12,14, and16. Contact pad24generally is a metal that is formed on the semiconductor die in order to provide electrical contact between the semiconductor die and elements external to the semiconductor die. For example, contact pad24may be formed to receive a bonding wire that may subsequently be attached to pad24or may be formed to receive a solder ball or other type of interconnect structure that may subsequently be attached to pad24. Substrate18includes a bulk substrate19that has an epitaxial layer20formed on a surface of bulk substrate19. A portion of epitaxial layer20may be doped to form a doped region21that is used for forming active and passive portions of semiconductor die12,14, or16. Layer20and/or region21may be omitted in some embodiments or may be in other regions of dice12,14, or16. Typically, a dielectric23is formed on a top surface of substrate18in order to isolate pad24from other portions of the individual semiconductor die and to isolate each pad24from the adjacent semiconductor die. Dielectric23usually is a thin layer of silicon dioxide that is formed on the surface of substrate18. Contact pad24generally is a metal with a portion of contact pad24electrically contacting substrate18and another portion formed on a portion of dielectric23. After dice12,14, and16are formed including the metal contacts and any associated inter-layer dielectrics (not shown), a dielectric26is formed over all of the plurality of semiconductor die to function as a passivation layer for wafer10and for each individual semiconductor die12,14, and16. Dielectric26usually is formed on the entire surface of wafer10such as by a blanket dielectric deposition. The thickness of dielectric26generally is greater than the thickness of dielectric23.

FIG. 3illustrates the cross-sectional portion of wafer10inFIG. 2at a subsequent stage in an example of an embodiment of the process of singulating dice12,14, and16from wafer10. After the passivation layer of dielectric26is formed, a mask32, illustrated by dashed lines, may be applied to the surface of substrate18and patterned to form openings that expose portions of dielectric26overlying each pad24and also overlying portions of wafer10where the singulation lines, such as singulation lines13and15, are to be formed. Thereafter, dielectric26is etched through the openings in mask32to expose the underlying surface of pads24and of substrate18. The openings that are formed through dielectric26in the region where the singulation lines, such as lines13and15, are to be formed function as singulation openings28and29. The openings that are formed through dielectric26overlying pads24function as contact openings. The etching process preferably is performed with a process that selectively etches dielectrics faster than it etches metals. The etching process generally etches dielectrics at least ten (10) times faster that it etches metals. The material used for substrate18preferably is silicon and the material used for dielectric26preferably is silicon dioxide or silicon nitride. The material of dielectric26may also be other dielectric materials that can be etched without etching the material of pads24, such as polyimide. The metal of pads24functions as an etch stop that prevents the etching from removing the exposed portions of pads24. In the preferred embodiment, a fluorine based anisotropic reactive ion etch process is used.

After forming the openings through dielectric26, mask32is removed and substrate18is thinned to remove material from the bottom surface of substrate18and reduce the thickness of substrate18. Generally, substrate18is thinned to a thickness that is no greater than about one hundred to two hundred (100 to 200) microns. Such thinning procedures are well known to those skilled in the art. After wafer10is thinned, the backside of wafer10may be metalized with a metal layer27. This metalization step may be omitted in some embodiments. After metalization, wafer10usually is attached to a transport tape or carrier tape30that facilitates supporting the plurality of die after the plurality of die are singulated. Such carrier tapes are well known to those skilled in the art.

FIG. 4illustrates wafer10at a subsequent stage in the example process of singulating semiconductor die12,14, and16from wafer10. Substrate18is etched through singulation openings28and29that were formed in dielectric26. The etching process extends singulation opening28and29from the top surface of substrate18completely through substrate18. The etching process usually is performed using a chemistry that selectively etches silicon at a much higher rate than dielectrics or metals. The etching process generally etches silicon at least fifty (50) and preferably one hundred (100) times faster than it etches dielectrics or metals. Typically, a deep reactive ion etcher system which uses a combination of isotropic and anisotropic etching conditions is used to etch openings28and29from the top surface of substrate18completely through the bottom surface of substrate18. In the preferred embodiment, a process commonly referred to as the Bosch process is used to anisotropically etch singulation openings28and29through substrate18. In one example, wafer10is etched with the Bosch process in an Alcatel deep reactive ion etch system.

The width of singulation openings28and29is generally five to ten (5-10) microns. Such a width is sufficient to ensure that openings28and29can be formed completely through substrate18and are narrow enough to form the openings in a short time interval. Typically, openings28and29can be formed through substrate18within a time interval of approximately fifteen to thirty (15 to 30) minutes. Since all of the singulation lines of wafer10are formed simultaneously, all of the singulation lines can be formed across wafer10within the same time interval of approximately fifteen to thirty (15 to 30) minutes. Thereafter, wafer10is supported by carrier tape30as wafer10is taken to a pick-and-place equipment35that is utilized to remove each individual die from wafer10. Typically, equipment35has a pedestal or other tool that pushes each singulated die, such as die12, upward to release it from carrier tape30and up to a vacuum pickup (not shown) that removes the singulated die. During the pick-and-place process, the portion of thin back metal layer27that underlies openings28and29breaks away and is left behind on tape30.

FIG. 5illustrates an enlarged cross-sectional portion of semiconductor dice42,44, and46that are formed on wafer10and that are alternate embodiments of dice12,14, and16that are explained in the description ofFIGS. 1-4. Dice42,44, and46are illustrated at a manufacturing state after forming dielectric23on the top surface of substrate18and prior to forming pads24(FIG. 1). Dice42,44, and46are similar to dice12,14, and16except that dice42,44, and46each have a respective isolation trench50,54, and58that surround the die and isolate them from an adjacent die. Trenches50,54, and58generally are formed near an outside edge of each die. Trenches50,54, and58are formed to extend from the top surface of substrate18a first distance into bulk substrate19. Each trench50,54, and58generally is formed as an opening into substrate19that has a dielectric formed on the sidewall of the opening and generally is filled with a dielectric or other material such as silicon or polysilicon. For example, trench50may include a silicon dioxide dielectric51on the sidewalls of the trench opening and may be filled with polysilicon52. Similarly, trenches54and58include respective silicon dioxide dielectrics55and59on the sidewalls of the trench opening and may be filled with polysilicon56and60. Singulation line43is to be formed between trenches50and54, and singulation line45is to be formed between trenches50and58. Trenches50and54are formed adjacent to singulation line43, and trenches50and58are formed adjacent to singulation line45. Methods of forming trenches50,54, and58are well known to those skilled in the art. It should be noted that trenches50and54are used as illustration only and could be any number of shapes, sizes, or combinations of isolation tubs or trenches.

FIG. 6illustrates wafer10at a subsequent stage in the alternate process of singulating semiconductor dice42,44, and46from wafer10. After trenches50,54, and58are formed, other portions of dice42,44, and46are formed including forming contact pads24and forming dielectric26covering dice42,44, and46. Dielectric26generally also covers other portions of wafer10including the portion of substrate18where singulation lines43and45are to be formed. Thereafter, mask32is applied and patterned to expose underlying dielectric26where singulation lines and contact openings are to be formed. Dielectric26is etched through the openings in mask32to expose the underlying surface of pads24and of substrate18. The openings that are formed through dielectric26in the region where the singulation lines, such as lines43and45, are to be formed function as singulation openings47and48. The etching process used to form openings47and48through dielectrics23and26is substantially the same as the process used to form openings28and29(FIG. 3) in dielectric23and26. Openings47and48preferably are formed so that dielectrics51,55, and59on the sidewalls of respective trenches50,54, and58are not underlying openings47and48so that the dielectrics will not be affected in subsequent operations to form singulation lines43and45.

After forming openings47and48through dielectric26, mask32is removed and substrate18is thinned and metalized with metal layer27as explained hereinbefore in the description ofFIG. 3. This metalization step may be omitted in some embodiments. After metalization, wafer10is usually attached to carrier tape30.

FIG. 7illustrates wafer10at a subsequent stage in the alternate process of singulating semiconductor die42,44, and46from wafer10. Substrate18is etched through singulation openings47and48that were formed in dielectric26. The etching process extends singulation opening47and48from the top surface of substrate18completely through substrate18. Openings47and48usually are at least 0.5 microns from dielectrics51,55, and59. The etching process usually is an isotropic etch that selectively etches silicon at a much higher rate than dielectrics or metals, generally at least fifty (50) and preferably at least one hundred (100) times faster. Since the dielectric on the sidewalls of the trenches protects the silicon of substrate18, an isotropic etch can be used. The isotropic etch has a much higher etching throughput than can be obtained with the use of the BOSCH process or with limited use of the Bosch process. However, the isotropic etching typically undercuts portions of substrate19that are underlying trenches50,54, and58. Typically, a down-stream etcher with a fluorine chemistry is used to etch openings28and29from the top surface of substrate18completely through the bottom surface of substrate18and expose a portion of layer27underlying openings28and29. In one example, wafer10is etched in the Alcatel deep reactive ion etch system using full isotropic etching. In other embodiments, isotropic etching may be used for most of the etching and anisotropic etching may be used for another portion of the etching (the Bosch process). For example, isotropic etching may be used until openings28and29extend to a depth that is substantially the same depth as trenches50,54, and58, and anisotropic etching may be used thereafter to prevent the undercutting of trenches50,54, and58.

The width of singulation openings47and48is generally about the same as the width of openings28and29. Dice42,44, and46may be removed from tape30similarly to the manner of removing dice12,14, and16.

FIG. 8illustrates an enlarged cross-sectional portion of an example of an embodiment of wafer10taken along a cross-section line8-8that is illustrated inFIG. 1. A thickness70of substrate18and wafer10is illustrated by an arrow.FIG. 8illustrates additional singulation lines11that are similar to singulation lines13and15. A second surface17of substrate18and wafer10is illustrated opposite to the surface on which layer20is formed.

FIG. 9illustrates wafer10at a stage of an embodiment of one example method of singulating die from wafer10. In some embodiments, thickness70of wafer10may be reduced. Typically, wafer10is inverted in order to facilitate reducing thickness70. In some embodiments, a support structure34may be attached to wafer10along the top surface in order to facilitate thinning wafer10. In other embodiments, support structure34may be omitted. Thickness70may be reduced by methods such as back-grinding, chemical etching, chemical-mechanical polishing (CMP), or other means.

A conductor37is applied to surface17. Typically, conductor37is a metal such as metal27. However, conductor37may be a thicker metal than metal27, or may be other materials such as conductive epoxy, or thermal heat sink material, or other materials that do not include the material of substrate19.

FIG. 10illustrates wafer10at another subsequent stage of the example method. Portions of conductor37that underlie regions of wafer10where singulation lines are to be formed may have the thickness reduced thereby forming reduced thickness regions72of conductor37. Regions72usually are formed to underlie portions of wafer10where singulation lines are to be formed such as lines11,13, and15. Regions72may also be disposed at other portions of the plurality of semiconductor dies. Support structure34may or may not be utilized during this operation.

FIG. 11illustrates wafer10at another subsequent stage of the example method. Wafer10is mounted on tape30. Tape30usually is applied to wafer10in order to support wafer10during subsequent die singulation operations. Conductor37overlies tape30. Conductor37typically is disposed on tape30, however, in some embodiments there may be an intervening material between tape30and conductor37. A support frame31may be attached to tape30to facilitate handling tape30and wafer10.

Singulation openings, such as singulation openings28,29or43,48, are formed in wafer10along the singulation lines, such as singulation lines11,13,15, by methods such as those explained hereinbefore in the description ofFIGS. 1-7. The singulation openings may also be formed by methods such as those explained in related U.S. patent application Ser. No. 12/689,098 of inventor Gordon Grivna having a common assignee herewith and a title of SEMICONDUCTOR DIE SINGULATION METHOD which was filed on Jan. 18, 2010 and is incorporated herein by reference. Typically, the width of the singulation openings is greater than the width of the widest portion of region72.

Subsequently, an individual die, such as die12, may be singulated from the remainder of wafer10. For example, a pick-and-place operation may be utilized to remove die12such as illustrated and explained in the description ofFIG. 4.

During the singulation operation, regions72facilitate separating the portion of conductor37that underlie a semiconductor die, such as portion75underlying die12, from the remainder of conductor37. Because the thickness of conductor37has been reduced in regions72, conductor37easily separates along regions72thereby leaving portion75attached to die12. In embodiments where regions72do not align with the singulation openings, such as regions72being formed to both sides of the singulation openings, regions72still facilitate separating the portion of conductor37that underlie a semiconductor die, such as portion75underlying die12, from the remainder of conductor37. Because conductor37has regions72, in some embodiments conductor37may have a thickness that is greater than metal27.

In the preferred embodiment, regions72extend to approximately ninety percent (90%) of the way through conductor37in order to facilitate separation along regions72. In other embodiments, regions72may extend completely through conductor37. In some embodiments, surface17of wafer10may be exposed by regions72. In still other embodiments, forming conductor37may cause the formation of a metal-silicon alloy along the interface between conductor37and substrate18or between conductor37and substrate18. For such an embodiment, regions72typically would not extend through the metal-silicon alloy.

FIG. 12illustrates an enlarged plan view of the backside of wafer10after forming conductor37and regions72. Typically, regions72are formed to underlie all the singulation lines. Thus, regions72may traverse wafer10and one direction and other regions73that are similar regions72may traverse wafer10in other directions in order to underlie all the singulation lines of wafer10.

FIG. 13illustrates an enlarged plan view of a portion of wafer10near die12,14, and16. Preferably, regions72underlie the singulation openings such as openings28and29. In some embodiments, all or a portion of regions72may be offset from an edge of the singulation openings by an offset distance77, identified in general by an arrow. For example, the backside alignment may result is such offset or it may be desirable to reduce the area of portion75. It is believed that in some embodiments distance77may be five percent (5%) of the width of the die and still provide the desired uniform singulation of the semiconductor die including portion75.

FIG. 14illustrates an enlarged plan view of a portion of an example of an embodiment of a wafer130having hexagonal shaped die. Wafer130is similar to wafer10except that the die have a hexagonal shape. The view ofFIG. 14shows the shape of the die such as die132and133, and also illustrates a bottom view to explain where a conductor, such as conductor37, would have to be thinned to form reduced thickness regions such as regions72inFIG. 13. Conductor37is not illustrated for clarity of the explanation. For such a die configuration, several sets of reduced thickness regions72typically would be used to assist in singulating the die of wafer130. Examples of reduced thickness regions similar to regions72are illustrated in a general manner as reduced thickness regions135-137,139-141, and142. The reduced thickness regions, such as regions72,135-137,139-141, and142, may not all be formed to only underlie the regions where the singulation lines or singulation openings are to be formed because it would be difficult to form regions72in the pattern of the non-parallelogram shaped die. In such die patterns, reduced thickness regions, such as regions72,135-137,139-141, and142, may also be formed to cross the wafer in regions near where the singulation lines and singulation openings are not to be formed. For example, regions135-137may be formed near one side of a series of die such as region137formed near one side of die132to be near a singulation opening for die132. Region137may also traverse wafer130near one side of other die that are aligned with die132. Region137may also cross under the interior of other die, such as die133, that are not aligned with die132. Region136may be offset to traverse near one side of die133to be near a singulation opening for die133and this may cause region136to also traverse under the interior of die132, for example under active regions of die132. Another group of reduced thickness regions, such as regions139-141, may traverse wafer130along another side of the die, for example regions140and141may traverse near two opposite sides of die132to be near other singulation openings for die132. This may cause region141to also traverse under the interior of die133because of the off-set relationship of the die. Regions142may be formed to traverse across wafer130in another direction along another side of the die in order to be near other singulation opening for the die. Thus in general, reduced thickness regions may be formed to traverse in groups in one direction and in other groups in another direction wherein portion of regions of one group may be near an edge of a die such as underlying near singulation openings, while other regions of the group traverse to underlie interior portions of other die. One skilled in the art will appreciate that such groups may also be formed for a wafer that has die of different sizes, for example different sized parallelogram shaped die. The reduced thickness regions may be formed in one group that are positioned near an edge of die of one size to be near singulation openings for that die and may underlie interior portions of other die which have a different size.

One skilled in the art will appreciate that such a method allows putting the hexagonal shaped die closer together and still being able to uniformly singulate the die thereby increasing the number of die that can be formed in a given area of a wafer. Such a method also allows putting die of different sizes closer together and increasing the number of die that can be formed in a given area of a wafer.

FIG. 15illustrates a side view of a portion of an example of an embodiment of a tool80, such as a cutting tool or scribing tool, that may be used to form regions72.

FIG. 16illustrates a cross-sectional view of tool80taken all along a cross-sectional line14-14.

FIG. 17illustrates an isometric view of tool80. This description has references toFIGS. 13-15. Tool80includes a cutting tip89and a cutting surface88that is adjacent to tip89and extends from tip89toward a central support section82of tool80. Tip89and cutting surfaces88are configured to engage with a material which is to be scribed or cut, such as conductor37on wafer10, and reduce the thickness of the material, such as forming regions72in conductor37. Tool80also includes a depth stop83that is configured to limit the penetration of tip89and surfaces88into the material. Tip89is formed to extend a cutting distance96from stop83. Distance96is the distance that tip89and surface88may extend into or penetrate the material to be cut.

Typically, tip89and surface88are configured as a cutting wheel that rolls along the material so that tip89and surfaces88penetrate into the material as tool80rotates along the material. For such an embodiment, surface88is rotatingly attached to section82. Although tip89is illustrated as a sharp or pointed tip, tip89may have various configurations including a blunt tip as illustrated by a dashed line102. The portion of cutting surface88that extends distance from depth stop83, illustrated by a dashed line103, to tip89forms a cutting volume for tool80.

Tool80typically includes a central opening92that extends along a major axis93. In most embodiments, a shaft is typically inserted through central opening92so that tool80may rotate around the shaft.

In the preferred embodiment, central support section82is a solid piece that has a width which is greater than a width98of surface88. In other embodiments, section82may be formed from multiple elements that are abutted together to form section82. For example, section82may separate into pieces as illustrated by dashed lines120and121. These pieces may be abutted together to form tool80. For example, the shaft through opening92may hold the pieces together. Although tool80is illustrated with opening82, in other embodiments opening92may be omitted. In other embodiments, tool80may have an attachment device, such as a peg or screw, extending from section82along axis93and the attachment device may be used to section82and other portions of tool80.

During the process of using tool80for scribing or cutting the material, the cutting volume of tool80usually causes portions of the material to be displaced or forced out from within the material up toward the surface of the material. In order to control the portions of the material that are displaced and to assist in more accurate control of the cutting depth, tool80includes an accumulation region86(indicated in general by an arrow). Accumulation region86provides a space for displaced material to accumulate as tool80is cutting or scribing the material. Accumulation region86minimizes the forced out material from coming between depth stop83and the surface of the material being cut or scribed. Consequently, as the displaced material is forced out it is accumulated by region86so that tip89may extend distance96into the material. As will be explained further hereinafter, the displaced material accumulated within region86usually is extruded toward the surface of the material as tool80moves across the material.

Typically, accumulation region86is formed as a recess in section82and adjacent to surface88. Region86has sides90and91that extend into section82away from surface88and away from stop83. Preferably, recess86is formed to have a volume that is approximately the same as the cutting volume so that the forced out material may substantially fit within accumulation region86. In some embodiments, the volume of the accumulation region may be less than the cutting volume, but such a configuration may cause excess material in regions72. In other embodiments the volume of region86may be greater than the cutting volume. In one embodiment, the volume of the accumulation region is no less than the cutting volume. In the preferred embodiment, surface88extends at an angle84of approximately one hundred ten degrees (110) from a line parallel to the surface to be cut. For example, angle84may be from surface88to the surface of stop83. Angle84typically can vary from about ninety five to about one hundred thirty five (95-135) degrees and still provide the desired accurate depth control and can also provide uniform separation of the material. For example, to provide uniform separation during the singulation of semiconductor die. Those skilled in the art will appreciate that the relationship between the cutting and accumulation volumes should be maintained as angle84changes.

Although accumulation region86is illustrated as a triangle, sides90and91may have various shapes that facilitate accumulating the extruded material. For example, tip89can have a width from 0.2 to 0.55 microns for respective distance96of one to three (1-3) microns.

FIG. 18illustrates an enlarged isometric view of a portion of a semiconductor wafer110that is similar to wafer10. Wafer110includes a substrate111that is similar to substrate18. A conductor113is formed on a surface of wafer110similar to conductor37. In an operation, tool80was engaged with conductor113and moved across the surface of conductor113to reduce the thickness of conductor113. Tip89and surfaces88penetrated into conductor113and stop83abutted the surface of conductor113. As tool80moved across conductor113, a reduced thickness region115was formed. In one embodiment, region115could be considered as a trough formed in conductor113. The penetration of tool80displaced portions of conductor113out of conductor113. These displaced or forced out portions were controlled within region86of tool80and formed onto the surface of conductor113as ridges116on the surface of conductor113adjacent to the region115.

Without accumulation region86, the displaced material may have been left behind within region115thereby causing an irregular depth within region115, or may have stuck to the surface of the tool used to form region115thereby also forming an irregular depth. The irregular depth could result in non-uniform separation of the material during die singulation. The irregular depth also could result in irregular debris or contamination thereby resulting in unusable semiconductor die.

Those skilled in the art will appreciate that although the method of singulating die from wafer10is explained to form the reduced thickness regions prior to forming the singulation openings, the sequence could be changed. For example, wafer10could be applied to tape30and the singulation openings formed, then the reduced thickness regions could be formed in conductor37. For example, the reduced thickness regions may be formed from either side of the singulation openings. Additionally, regions72may be formed by means other than with tool80. For example, regions72may be formed by photoresist masking and etching, a wafer scribe tool, a saw blade, or laser ablation. In some embodiments, tool80may be used to make multiple passes across a material, material113for example, in order to form regions72to the desired depth. For example tool80may make one pass to form regions72to a first depth and another pass to form regions72to a greater depth.

In some embodiments, a cutting tool may be formed to have multiple cutting tips88to enable simultaneous cutting of multiple regions72as illustrated by a multiple cutting tool145inFIG. 20. Two tools80may be configured to simultaneously thin two regions72during one pass. The two tools80may be arranged substantially parallel along axis93. In other embodiments, the tools may be parallel but not aligned along axis93. In other embodiments, the tool80may be formed to have different distances96and/or angles102.

FIG. 19illustrates an enlarged isometric view of die12after singulation from wafer10and after attachment to a mounting platform155. Platform155may be a portion of a semiconductor package, such as a flag region, or may be a portion of another type of platform suitable for mounting die12. Connections usually are made to electrically connect portions of die12to elements external to die12. For example, a connection164may be formed between a connection pad163of die12and electrical traces on platform155.

In some cases, it may be desirable to electrically connect conductor37or a portion of conductor37to electrical connection points on platform155or to electrical connection points on die12(illustrated in general by dashed lines). During the steps of forming singulation openings for singulating die12, the methods used for forming the singulation openings may be used to form an opening in an interior of die12such as an opening158. Opening158may be formed to expose a portion of conductor37. Subsequently, a connection160may be attached to the portion of conductor37that is exposed in opening158.

In some cases, it may also be desirable to isolate the portion of conductor37that is connected to connection160from other portions of conductor37. Regions72may be used to separate conductor37into portions or sections. Regions72may be formed underlying interior portions of die12to separate one portion of conductor37, such as a portion167to which connection160is electrically attached, from other portions of conductor37.

Connection160is illustrated as a bonding wire connection; however, those skilled in the art will understand that other types of connection mechanisms may be used to form the connections and provide an electrical connection between the elements.

FIG. 21schematically illustrates in a very general manner an isometric view of a ganged tool150that may be used to reduce the thickness of a region of a material, for example a material on a surface of a semiconductor wafer. Tool150is similar to tool80but includes a support section that is suitable for accommodating a plurality of tools80. Tool150may be used to make multiple passes along a region, such as a region72, to reduce the thickness of the region. In some embodiments, one of the tool80elements may be set to have a first depth into the material to be reduced and another of the tool80elements may have a second depth that is greater than the first depth. Those skilled in the art will appreciate that one of those two depths may or may not be limited by surface83. In other embodiments, two or more of tool80elements may have the same depth, or another one or more of the tool80elements may have a different depth. In some embodiments, tools80of tool150may have different angles102from each other and/or may have different shapes of surface88and/or tip89to facilitate cut profile and depth control. Tool150facilitates making multiple cuts into the material in one pass across the material thereby reducing cycle time and associated manufacturing costs. Tool150can also reduce the pressure requirements needed by a single tool80thereby further improving the uniformity of the cut.

Tool150includes vertical supports151that are formed to engage with and support a tool80. A projection from support151could mate to opening92of tool80(seeFIGS. 15-17) to support tool80. Supports151extend from another support153that is attached to a means for moving and controlling tool150.

Those skilled in the art will appreciate that in one embodiment, A method of singulating semiconductor die from a semiconductor wafer comprises: providing a semiconductor wafer, a wafer10for example, formed from a silicon semiconductor material and having a plurality of semiconductor dies formed on a first surface of the semiconductor wafer, the plurality of semiconductor dies separated from each other by singulation regions where singulation openings, such as openings28and29, are to be formed wherein the plurality of semiconductor dies include a dielectric layer overlying portions of the plurality of semiconductor dies, the semiconductor wafer including a second surface that is opposite to the first surface; forming a conductor, conductor37for example, on the second surface of the semiconductor wafer, the conductor having a thickness; reducing the thickness of portions of the conductor to form a reduced thickness region, such as a region72, of the conductor; attaching the semiconductor wafer to a carrier tape, a carrier tape30for example, wherein the conductor overlies the carrier tape; and etching a first opening, opening28for example, to extend into the semiconductor wafer thereby creating a space between the plurality of semiconductor dies wherein the carrier tape remains attached during the etching.

In another embodiment, the method may also include separating one semiconductor die of the plurality of semiconductor dies from the carrier tape and from other die of the plurality of semiconductor dies wherein a first portion of the conductor remains attached to the one semiconductor die and is separated from other portions of the conductor along the reduced thickness region.

In other embodiments, the method may further include etching the first opening from the first surface of the semiconductor wafer through the semiconductor wafer to the second surface.

Another embodiment may include that the step of reducing the thickness of the portions of the conductor to form the reduced thickness regions includes forming the reduced thickness regions in the portions of the conductor that underlie the singulation regions.

Still other embodiments may include, wherein etching the first opening includes using etching the first opening to expose a surface of the semiconductor wafer; and etching through the first opening to extend a depth of the first opening into the semiconductor wafer thereby creating the space between the plurality of semiconductor dies wherein the carrier tape remains attached during the etching.

Those skilled in the art will appreciate that in one embodiment, a cutting tool, for example tool80, comprises: a central support section, section82for example, having a major axis, such as an axis93; a cutting tip, for example tip89; a cutting surface, surface88for example, adjacent to the cutting tip and extending from the cutting tip toward the central support section terminating in a distal end, distal end103for example, of the cutting surface wherein the cutting surface is attached to the central support section; a depth stop, stop83for example, spaced a first distance from the cutting tip toward the central support section wherein a first volume, such as a cutting volume, is formed by a portion of the cutting surface extending from the cutting tip to the depth stop; and an accumulation region, region86for example, adjacent to the central support section and extending away from the cutting surface, the accumulation region having a second volume, such as a volume86, that approximates the first volume.

Another embodiment may include that the accumulation region extends from the distal end of the cutting surface away from the cutting tip.

Other embodiments mat include that the depth stop has a first portion that is configured to engage with a surface of a conductor on a semiconductor wafer to limit a depth of penetration of the cutting tip into the conductor.

In another embodiment, the accumulation region is a formed as a recess, such formed by sides90and91, disposed within the central support section, the accumulation region positioned adjacent to the distal end of the cutting surface and extending from the distal end of the cutting surface into the central support section.

In still another embodiment, the central support section may be rotatingly coupled to the cutting surface, for example the central support section may be formed to rotate about an axis to cause the cutting surface to also rotate.

Those skilled in the art will also appreciate that a method of forming a tool, tool80for example, for a semiconductor wafer comprises: forming the tool to reduce a thickness of a material, material represented by conductor37for example, formed on a semiconductor wafer, such as wafer10; forming the tool with a cutting tip, such as tip89, and cutting surfaces, such as surface88, that are configured to penetrate into the material to form reduced thickness regions, region72for example, in the material; and forming an accumulation region, region86for example, of the tool with a recess having a first volume for accepting portions of the material displaced from within the material by the penetration.

Those skilled in the art will also understand that in one embodiment, a method of singulating semiconductor die from a semiconductor wafer comprise: providing the semiconductor wafer, such as wafer10, formed from a silicon semiconductor material and having a plurality of semiconductor dies, such as die12and14, formed on a first surface of the semiconductor wafer and separated from each other by singulation regions of the semiconductor wafer where singulation openings, openings28and29for example, are to be formed, the semiconductor wafer including a second surface that is opposite to the first surface; providing a conductor on the second surface of the semiconductor wafer, the conductor having a thickness; engaging a cutting tool with the conductor to reduce the thickness of portions of the conductor, the cutting tool having a cutting tip and cutting surfaces that penetrate into the conductor to form reduced thickness regions in the conductor; and moving the cutting tool across the conductor to form the reduced thickness regions.

In view of all of the above, it is evident that a novel device and method is disclosed. Included, among other features, is etching singulation openings completely through a semiconductor wafer. Etching the openings from one side assists in ensuring that the singulation openings are substantially aligned to the semiconductor edge and preferably are precisely aligned. Etching from one side also ensures that the singulation openings have very straight side-walls thereby providing a uniform singulation line along each side of each semiconductor die. Etching the singulation openings completely through the semiconductor wafer facilitate forming narrow singulation lines thereby allowing room to use for forming semiconductor die on a given wafer size. The etching process is faster than a sawing process, thereby increasing the throughput of a manufacturing area.

While the subject matter of the invention is described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, layers20and/or21may be omitted from substrate18. The singulation openings alternately may be formed prior to or subsequent to forming the contact openings overlying pads24. Also, the singulation openings may be formed before thinning wafer10, for example, the singulation openings may be formed partially through substrate18and the thinning process may be used to expose the bottom of the singulation openings.

As the claims hereinafter reflect, inventive aspects may lie in less than all features of a single foregoing disclosed embodiment. Thus, the hereinafter expressed claims are hereby expressly incorporated into this Detailed Description of the Drawings, with each claim standing on its own as a separate embodiment of an invention. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those skilled in the art.