Memory system

A memory system includes a memory apparatus including a write driver and a memory controller configured to control the memory apparatuses. The memory controller includes a command comparison circuit configured to compare word line addresses, bit line addresses, and pieces of write data of a first write command and a second write command and output a simultaneous write control signal having a first level when the bit line addresses and the pieces of write data are the same as each other and most significant bits (MSBs) of the word line addresses are different from each other and a processor configured to transfer a simultaneous write command for simultaneously operating the first write command and the second write command to the memory apparatus when the simultaneous write control signal having the first level is output from the command comparison circuit.

CROSS-REFERENCES TO RELATED APPLICATION

This application claims priority under 35 U.S.C. 119(a) to Korean application No. 10-2016-0070334, filed on Jun. 7, 2016, in the Korean intellectual property Office, which is incorporated by reference herein its entirety as set forth in full.

BACKGROUND

1. Technical Field

Various embodiments may generally relate to a semiconductor apparatus, and more particularly, to a memory system and controlling a write current.

2. Related Art

With regards to the demands on high capacity and low-power consumption of memory apparatuses, research on next-generation memory apparatuses having non-volatility and not having a refresh have been conducted. The next-generation memory apparatuses need to have a high integration of dynamic random access memory (DRAM), non-volatility of a flash memory, high speed of static RAM (SRAM), and the like. There are next-generation memory apparatuses which meet the requirements of being non-volatile and not having the refresh. These next-generation memory apparatuses which fulfill the requirements consist of a phase-change RAM (PRAM), a nano floating gate memory (FTGM), a polymer RAM (PoRAM), a magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), and a resistive RAM (ReRAM).

SUMMARY

According to an embodiment, a memory system may be provided. The memory system may include a memory apparatus including a write driver configured to output a write current for writing data in a plurality of memory cells; and a memory controller configured to control the memory apparatus. The memory controller may include a command comparison circuit configured to compare word line addresses, bit line addresses, and pieces of write data of a first write command and a second write command received by the memory controller and output a simultaneous write control signal having a first level when the bit line addresses and the pieces of write data are the same as each other and most significant bits (MSBs) of the word line addresses are different from each other; and a processor configured to transfer a simultaneous write command for simultaneously operating the first write command and the second write command to the memory apparatus when the simultaneous write control signal having the first level is output from the command comparison circuit. The write driver may increase the write current by receiving the simultaneous write control signal having the first level and output an increased write current.

According to an embodiment, a memory system may be provided. The memory system may include a memory cell region include a plurality of bit lines, a plurality of word lines, and a column decoder coupled to central portions of the plurality of bit lines; a write driver configured to output a write current to the column decoder of the memory cell region; a control logic configured to control the write driver to write data in the memory cell region; a command comparison circuit configured to compare word line addresses, bit line addresses, and pieces of write data of a first write command and a second write command received from a host apparatus and output a simultaneous write control signal having a first level when the bit line addresses and the pieces of write data are the same as each other and most significant bits (MSBs) of the word line addresses are different from each other; and a processor configured to transfer a simultaneous write command for simultaneously operating the first write command and the second write command to the control logic when the simultaneous write control signal having the first level is output from the command comparison circuit. The write driver may increase the write current based on the simultaneous write control signal having the first level output from the command comparison circuit and output an increased write current to the column decoder.

According to an embodiment, a MAT may be provided. The MAT may include a memory cell region including a column decoder, the column decoder located between a first word line group arranged in an upper side of the column decoder and a second word line group arranged in a lower side of the column decoder, and bit lines coupled to central portions of the column decoder as well as word lines included in the first and second word line groups; and a write driver configured to output a write current to the column decoder of the memory cell region. The write driver increases the write current to the column decoder when an intersection region of a first word line, from the first word line group, and a first bit line is substantially the same distance from the column decoder as an intersection region of a second word line, from the second word line group, and the first bit line.

A resistance to the first word line from the column decoder is substantially the same as a resistance to the second word line from the column decoder. The first word line is symmetrical to the second word line on the basis of the column decoder.

The write drive comprises a voltage supply terminal; a first current source and a second current source coupled in parallel to the voltage supply terminal; and a switching element configured to electrically couple the voltage supply terminal to provide the increased write current by supplying the second current source to the first current source.

The increased write current is substantially double the first current source. A partial write current of the increased write current flows toward the first word line along the bit line and a remaining write current toward the second word line along the bit line to substantially simultaneously write data in a memory cell arranged in the intersection region of the first word line and the first bit line and a memory cell arranged in the intersection region of the second word line and the first bit line.

The switching element is configured to electrically couple the voltage supply terminal to provide the increased write current based on a simultaneous write control signal having a first level. The simultaneous write control signal has the first level when bit line addresses and pieces of the write data for the memory cell arranged in the intersection region of the first word line and the first bit line and the memory cell arranged in the intersection region of the second word line and the first bit line are the same as each other and most significant bits (MSBs) of word line address of the memory cell arranged in the intersection region of the first word line and the first bit line and the memory cell arranged in the intersection region of the second word line and the first bit line are different from each other.

DETAILED DESCRIPTION

Examples of embodiments will be described with reference to the accompanying drawings. Examples of embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of examples of embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes illustrated herein but may include deviations in shapes that result, for example, from manufacturing. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements. It is also to be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other or substrate, or intervening layers may also be present. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form, and vice versa as long as it is not specifically mentioned.

The concepts are described herein with reference to cross-section and/or plan illustrations of embodiments. However, embodiments of the concepts should not be construed as limiting the concepts. Although a few embodiments of the concepts will be illustrated and described, it will be appreciated by those of ordinary skill in the art that changes may be made in these examples of embodiments without departing from the principles and spirit of the concepts.

One or more embodiments may be provided to a memory system capable of reducing write latency.

According to the embodiments, a write operation may be simultaneously performed on a plurality of memory cells coupled to one bit line, and thus the speed of the write operation may be improved and the write latency may be reduced.

FIG. 1is a block diagram illustrating a memory system according to an embodiment,FIG. 2is a diagram illustrating a memory apparatus ofFIG. 1, andFIG. 3is a diagram illustrating one cell region included in a memory cell array ofFIG. 2.

Referring toFIG. 1, a memory system10according to an embodiment may include a memory apparatus100and a memory controller200.

The memory system10may store data accessed by a host apparatus such as, for example but not limited to, a portable phone, a MP3 player, a laptop computer, a desktop computer, a game machine, a television (TV), or an in-vehicle infotainment system.

The memory system10may be fabricated with any one among various types of storage apparatuses according to a protocol of an interface coupled to the host apparatus. For example, the memory system10may be configured of any one among various types of storage apparatuses such as, for example but not limited to, a solid state drive (SSD), a multimedia card in the form of an MMC, an eMMC, an RS-MMC, and a micro-MMC, a secure digital card in the form of an SD, a mini-SD, and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI-express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick, and the like.

The memory system10may be fabricated with any one of various types of packages. For example, the memory system10may be fabricated with any one among various types of packages such as, for example but not limited to, a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level fabricated package (WFP), and a wafer-level stack package (WSP).

The memory apparatus100may include a memory cell array110and a control logic120.

The memory cell array100may include a plurality of memory cells (not illustrated) arranged at intersection regions of a plurality of word lines and a plurality of bit lines. In an embodiment, each memory cell may be a single level cell (SLC) which stores 1-bit data or a multi-level cell (MLC) which stores 2-bit data. In another example, each memory cell may be a triple level cell (TLC) which stores 3-bit data or a quad level cell (QLC) which stores 4-bit data. The memory cell array110may include at least one or more among the SLC, the MLC, the TLC, and the QLC.

In an embodiment, the memory cell array110may include the memory cells having a two-dimensional (2D) horizontal structure or a 3D vertical structure. An example that the memory cell array110includes the memory cells having the 2D structure will be described in the embodiments, but the embodiments are not limited thereto.

In an embodiment, the memory cell array110may include resistive memory cells including a variable resistor element (not illustrated) having a variable resistance. For example, when a resistance of the variable resistor element formed of a phase-change material (for example, Ge—Sb—Te (GST)) is changed according to temperature, the memory apparatus100may be a PRAM. When the variable resistor element includes an upper electrode, a lower electrode, and a transition metal oxide formed between the upper electrode and the lower electrode, the memory apparatus100may be a RRAM. When the variable resistor element includes an upper electrode formed of a magnetic material, a lower electrode formed of a magnetic material, and a dielectric formed between the upper electrode and the lower electrode, the memory apparatus100may be MRAM.

The memory cell array110may include a plurality of cell regions as illustrated inFIG. 2. Hereinafter, the cell region unit may refer to a MAT. Each MAT of the memory cell array110may include a plurality of tiles as illustrated inFIG. 3. Each of the plurality of tiles may include a plurality of memory cells (not illustrated).

The MAT may include a row decoder X-Dec and a column decoder Y-Dec arranged between the plurality of tiles. In an embodiment, each of the plurality of MATs may include the row decoder X-Dec arranged to extend to a first direction and the column decoder Y-Dec arranged to extend to a second direction perpendicular to the first direction. The first direction may be a direction parallel to the bit lines and the second direction may be a direction parallel to the word lines, but this is not limited thereto. The row decoder X-Dec and the column decoder Y-Dec may perpendicularly cross to each other on a plane.

The MAT may include a first tile to a fourth tile Tile1, Tile2, Tile3, and Tile4symmetrically arranged with respect to the row decoder X-Dec and the column decoder Y-Dec. For example, the first tile Tile1and the third tile3may be symmetrically arranged with the second tile Tile2and the fourth tile Tile4with respect to the row decoder X-Dec and the first tile Tile1and the second tile Tile2may be symmetrically arranged with the third tile Tile3and the fourth tile Tile4with respect to the column decoder Y-Dec. The first tile Tile1may be diagonally arranged to the fourth tile Tile4and the second tile Tile2may be diagonally arranged to the third tile Tile3.

It has been illustrated inFIG. 3that one MAT includes one row decoder X-Dec and one column decoder Y-Dec, but the embodiments are not limited thereto. For example, the MAT may include two or more row decoders X-Dec arranged to the first direction and two or more column decoders Y-Dec arranged to the second direction perpendicular to the first direction. That is, the MAT may include a plurality of row decoders X-Dec arranged between the first tile Tile1and the second tile Tile2and between the third tile Tile3and the fourth tile Tile4and a plurality of column decoders Y-Dec arranged between the first tile Tile1and the third tile Tile3and between the second tile Tile2and the fourth tile Tile4.

Hereinafter, the first tile Tile1and the second tile Tile2arranged in an upper side of the column decoder Y-Dec on a plane may refer to an upper tile group UTG and the third tile Tile3and the fourth tile Tile4arranged in a lower side of the column decoder Y-Dec on a plane may refer to a lower tile group LTG. The upper tile group UTG may include a plurality of memory cells arranged in an upper side on the basis of central portions of a plurality of bit lines BL0to BL2m−1 and the lower tile group LTG may include a plurality of memory cells arranged in a lower side on the basis of the central portions of the plurality of bit lines BL0to BL2m−1.

Referring toFIG. 4, the MAT may include the plurality of bit lines BL0to BL2m−1 and a plurality of word lines WL0to WL2n−1 which perpendicularly cross or substantially perpendicularly cross the plurality of bit lines BL0to BL2m−1. Here, n and m may refer to an integer of 2 or more.

The plurality of bit lines BL0to BL2m−1 may extend from the upper tile group UTG to the lower tile group LTG. The plurality of bit lines BL0to BLm2−1 may include a plurality of first bit lines BL0to BLm−1 which extend from the first tile Tile1to the third tile Tile3and a plurality of second bit lines BLm to BL2m−1 which extend from the second tile Tile2to the fourth tile Tile4.

The plurality of word lines WL0to WL2n−1 may be arranged on the upper tile group UTG and the lower tile group LTG to perpendicularly cross or substantially perpendicularly cross the plurality of bit lines BL0to BL2m−1. The plurality of word lines WL0to WLn2−1 may include a first word line group including a plurality of word lines WL0to WLn−1 which extend from the first tile Tile1to the second tile Tile2and a second word line group including a plurality of word lines WLn to WL2n−1 which extend from the third tile Tile3to the fourth tile Tile4. The first word line group WL0to WLn−1 may be arranged in the upper tile group UTG and the second word line group WLn to WL2n−1 may be arranged in the lower tile group LTG.

In an embodiment, the number of first bit lines BL0to BLm−1 is equal to the number of second bit lines BLm to BL2m−1 and the number of word lines WL0to WLn−1 included in the first word line group is equal to the number of word lines WLn to WL2n−1 included in the second word line group, but this is not limited thereto.

The row decoder X-Dec may be arranged between the first bit lines BL0to BLm−1 and the second bit lines BLm to BL2m−1. The column decoder Y-Dec may be arranged between the first word line group WL0to WLn−1 and the second word line group WLn to WL2n−1. That is, the column decoder Y-Dec may be arranged between the upper tile group UTG and the lower tile group LTG. For example, the row decoder X-Dec may be coupled to central portions of the plurality of word lines WL0to WL2n−1 and the column decoder Y-Dec may be coupled to the central portions of the bit lines BL0to BL2m−1. Accordingly, a write current (or a write voltage) may be applied to the central portions of the word lines WL0to WL2n−1 and the central portions of the bit lines BL0to BL2m−1, and the applied write current (or the applied write voltage) may flow toward both ends of the word lines WL0to WL2n−1 from the central portions of the word lines WL0to WL2n−1 and toward both ends of the bit lines BL0to BL2m−1 from the central portions of the bit lines BL0to BL2m−1.

For clarity, it has illustrated inFIG. 4that the word lines WL0to WLn−1 included in the first word line group are far away from the word lines WLn to WL2n−1 included in the second word line group and the first bit lines BL0to BLm−1 are far away from the second bit lines BLm to BL2m−1. However, intervals between the word lines WL0to WL2n−1 may be substantially the same and intervals between the bit lines BL0to BL2m−1 may be substantially the same. The row decoder X-Dec and the word lines WL0to WL2n−1 may be arranged on different layers and the column decoder Y-Dec and the bit lines BL0to BL2m−1 may be arranged on different layers.

In an embodiment, addresses (hereinafter, referred to as first word line addresses) of the word lines WL0to WLn−1 included in the first word line group may be arranged in reverse order to an arrangement order of addresses (hereinafter, referred to as second word line addresses) of the word lines WLn to WL2n−1 included in the second word line group, but this is not limited thereto.

For example, the first word line addresses may be arranged in ascending order and the second word line addresses may be arranged in descending order. That is, the closer to the column decoders Y-Dec, the more increased the first word line addresses and the second word line addresses may be and the farther away from the column Y-Dec, the more reduced the first word line addresses and the second word line addresses may be. Other bits of one first word line address and one second word line address which are spaced by the same distance from the column decoder Y-Dec other than the most significant bits (MSBs) may be the same as each other.

For example, when the memory cell region of one MAT includes 4K word lines, the memory cell region of one MAT may include 4096 word lines. Addresses of the 4096 word lines may be represented with ‘0(zero)’ to ‘4095’. For example, when 2048 word lines arranged in the upper side of the column decoder Y-Dec refer to the first word line group and 2048 word lines arranged in the lower side of the column decoder Y-Dec refer to the second word line group, the first word line addresses may be represented with ‘0(zero)’ to ‘2048’ and the second word line addresses may be represented with ‘2049’ to ‘4095’.

Since the first word addresses are arranged in ascending order as described above, an address of a first word line among the word lines in the first word line group may be ‘0’ and an address of a last word line among the word lines in the first word line group may be ‘2047’. Since the second word line addresses are arranged in descending order, an address of a first word line among the word lines in the second word line group may be ‘4095’ and an address of a last word line among the word lines in the second word line group may be ‘2048’.

For example, an address of a third word line among the word lines in the first word line group may be ‘2’, and an address of a word line in the second word line group which is symmetrical with the third word line in the first word line group on the basis of the column decoder Y-Dec, that is, an address of a third word line from the last word line among the word lines in the second word line group may be ‘2050’. The address ‘2’ of the third word line among the word lines in the first word line group and the address ‘2050’ of the third word line among the word lines in the second word line group may be converted to binary number ‘000000000010’ and ‘100000000010’. In an address of a word line of the first word line group and an address of a word line of the second word line group which are spaced by the same distance from the column decoder Y-Dec, the MSBs may be different from each other and other bits other than the MSBs may be the same as each other.

The MAT may include a write and read (write/read) circuit115. The write/read circuit115may be coupled to the plurality of memory cells (not illustrated) through the plurality of bit lines. For example, the write/read circuit115may be coupled to the column decoder Y-Dec coupled to the central portions of the plurality of bit lines. The write/read circuit115may include a write driver WD configured to write data in the plurality of memory cells and a sense amplifier SA configured to amplify data read from the plurality of memory cells.

The write driver WD may include a current increasing circuit CIC configured to increase a write current applied to the plurality of memory cells. For example, referring toFIGS. 5A and 5B, the current increasing circuit CIC may include a first current source I1and a second current source I2coupled to a voltage supply terminal Vpp. The first current source I1and the second current source I2may be coupled in parallel to each other. The current increasing circuit CIC may include a switching element S which electrically couples the voltage supply terminal Vpp and the second current source I2. The switching element S may include a transistor, but this is not limited thereto. The switching element S may be turned on/off according to a simultaneous write control signal CTRL_RW input from the memory controller200.

For example, when the simultaneous write control signal CTRL_RW having a first level is input from the memory controller200, the switching element S is turned on and a write current IWRTmay flow in the I1and a second current source I2. Accordingly, the write drive WD may output the doubled write current 2IWRTwhich is increased twice more than the original write current IWRT.

When the simultaneous write control signal CTRL_RW having a second level is input from the memory controller200, the switching element S is turned off and the write current IWRTmay flow only through the first current I1. Accordingly, the write driver WD may output the original write current IWRTwhich is not increased. The first level may be a high level, that is, ‘1’ and the second level may be a low level, that is, ‘0’, but is the embodiments are not limited thereto.

That is, the write driver WD may output the doubled write current by increasing the write current when a write operation is simultaneously performed on two or more memory cells sharing one bit line and output the original write current when the write operation is performed on one memory cell. When the plurality of memory cells are a resistive memory cell, the write current may include a reset current and a set current. The current increasing current CIC as illustrated inFIGS. 5A and 5Bis merely an example and may be implemented with various configurations.

The control logic120may control an overall operation of the memory apparatus100. For example, the control logic120may control the write/read circuit115to perform the memory operation such as write, read, and the like. Referring toFIGS. 2 and 3, for the write operation, the read operation, and the like of the memory apparatus100, the control logic120may provide various pulse signals Pulse such as a write pulse, a read pulse, and the like to the write/read circuit115. The write/read circuit115may receive the various pulse signals Pulse and provide the write current (or the write voltage) or a read current (or a read voltage) to the memory cell array110using the various pulse signals. A pulse generator (not illustrated) configured to generate the various pulse signals may be provided in the inside or the outside of the control logic120.

The control logic120may output various internal control signals CTRL_RW for writing data in the memory cell array110or reading data from the memory cell array110to the write/read circuit115based on a command CMD, an address ADDR, and a control signal CTRL received from the memory controller200.

The control logic120may output a row address X_ADDR for selecting a word line and a column address Y-ADDR for selecting a bit line to the row decoder X-Dec and the column decoder Y-Dec based on the address ADDR received from the memory controller200.

Referring back toFIG. 1, the memory controller200may control the memory apparatus100to read data stored in the memory apparatus100or write data in the memory apparatus100in response to a write/read request from a host apparatus. For example, the memory controller200may provide the address ADDR, the command CMD, and the control signal CTRL to the memory apparatus100and may control the write operation (or a program operation), a read operation, and an erase operation of the memory apparatus100. Data DATA to be written in the memory apparatus100and data DATA read from the memory apparatus100may be exchanged between the memory controller200and the memory apparatus100.

The memory controller200may include a processor210, a command queue220, and a command comparison circuit230. Although not illustrated inFIG. 1, the memory controller200may further include a RAM, a host interface configured to perform data exchange between a host apparatus and the memory controller200, and a memory interface configured to perform data exchange between the memory controller200and the memory apparatus100.

The processor210may control an overall operation of the memory controller200.

The command queue220may include a space for storing a plurality of commands and a plurality of addresses. The command queue220may perform queuing on the command and address received from the host apparatus in receiving order.

The command comparison circuit230may output a result value of determining whether or not write commands for simultaneously performing the write operation are presented by comparing a plurality of write commands queued in the command queue220. In an embodiment, the command comparison circuit230may compare the write commands by selecting at least two write commands among the plurality of write commands queued in the command queue220in queued order, but is the embodiments are not limited thereto. The command comparison circuit230may compare the write commands by randomly selecting two write commands.

For example, the command comparison circuit230may compare word line addresses, bit line addresses, and pieces of write data for the plurality of write commands queued in the command queue220and output the result value of determining whether or not the write commands which can be simultaneously performed or substantially simultaneously performed are presented.

Referring toFIG. 6A, the command comparison circuit230may include a first comparison operation block CB1and a second comparison operation block CB2. The first comparison operation block CB1may include a first comparison circuit CC1, a second comparison circuit CC2, and a third comparison circuit CC3.

The first comparison circuit CC1may include a logic gate configured to perform a logic operation on a MSB WLMSBof a word line address for a first write command CMD1and a MSB WLMSBof a word line address for a second write command CMD2. That is, the first comparison circuit CC1may output a result value of determining whether the MSB of the word line address for the first write command CMD1is the same as or is different from the MSB of the word line address for the second write command CMD2only by comparing the MSB of the word line address for the first write command CMD1and the MSB of the word line address for the second write command CMD2. In an embodiment, for example, WLMSBmay be a most significant bit of the word line address and WLLSBmay be a least significant bit of the word line address etc.

Referring toFIG. 6B, the first comparison circuit CC1may further include logic gates configured to perform logic operations on other bits WLMSB-1to WLLSBother than the MSB WLMSBof the word line address for the first write command CMD1and other bits WLMSB-1to WLLSBother than the MSB WLMSBof the word line address for the second write command CMD2. That is, the first comparison circuit CC1illustrated inFIG. 6Bmay output the result value of determining whether all bits of the word line address for the first write command CMD1are the same as or are different from all bits of the word line address for the second write command CMD2by comparing all the bits of the word line address for the first write command CMD1and all the bits of the word line address for the second write command CMD2.

Referring back toFIG. 6A, the second comparison circuit CC2may include a first stage S1including a plurality of logic gates configured to perform logic operations on a MSB BLMSBto a least significant bit (LSB) BLMSBof a bit line address for the first write command CMD1and a MSB BLMSBto a LSB BLMSBof a bit line address for the second write command CMD2and a second stage S2including a logic gate configured to perform a logic operation on operation results of the logic gates in the first stage S1. That is, the second comparison circuit CC2may output the result value of determining whether all bits of the bit line address for the first write command CMD1are the same as or are different from all bits of the bit line address for the second write command CMD2by comparing all the bits of the bit line address for the first write command CMD1and all the bits of the bit line address for the second write command CMD2.

The third comparison circuit CC3may include a logic gate configured to perform a logic operation on the write data for the first write command CMD1and the write data for the second write command CMD2. That is, the third comparison circuit CC3may output a result value of determining whether the write data for the first write command CMD1is the same as or is different from the write data for the second write command CMD2by comparing the write data for the first write command CMD1and the write data for the second write command CMD2.

The second comparison operation block CB2may include a logic gate configured to perform a logic operation on the result values output from the first comparison circuit CC1, the second comparison circuit CC2, and the third comparison circuit CC3.

In an embodiment, the first comparison circuit CC1may include an exclusive OR (XOR) gate, the first stage S1of the second comparison circuit CC2and the third comparison circuit CC3may include an exclusive NOR (XNOR) gate, and the second stage S2of the second comparison circuit CC2and the second comparison operation block CB2may include an AND gate, but this is not limited thereto.

In an example, the first comparison circuit CC1may include an XOR gate configured to perform a logic operation on the MSB WLMSBof the word line address for the first write command CMD1and the MSB WLMSBof the word line address for the second write command CMD2and XNOR gates configured to perform logic operations on other bits WLMSB-1to WLLSBother than the MSB WLMSBof the word line address for the first write command CMD1and other bits WLMSB-1to WLLSBother than the MSB WLMSBof the word line address for the second write command CMD2.

For example, the command comparison circuit230including the first comparison circuit CC1illustrated inFIG. 6Amay output the simultaneous write control signal CRTL_RW having a value (that is, the first level) indicating that the write operation can be simultaneously performed when the bit line address of the first write command CMD1is the same as the bit line address of the second write command CMD2, the write data of the first write command CMD1is the same as the write data of the second write command CMD2, and the MSB of the word line address of the first write command CMD1is different from the MSB of the word line address of the second write command CMD2. In this example, the write operations corresponding to the first write command CMD1and the second write command CMD2may be simultaneously performed even when the other bits other than the MSB of the word line address of the first write command CMD1are not the same as the other bits other than the MSB of the word line address of the second write command CMD2.

For example, the command comparison circuit230including the first comparison circuit CC1illustrated inFIG. 6Bmay output the simultaneous write control signal CRTL_RW having a value (that is, the first level) indicating that the write operation can be simultaneously performed when the bit line address of the first write command CMD1is the same as the bit line address of the second write command CMD2, the write data of the first write command CMD1is the same as the write data of the second write command CMD2, the MSB of the word line address of the first write command CMD1is different from the MSB of the word line address of the second write command CMD2, and the other bits other than the MSB of the word line address of the first write command CMD1are the same as the other bits other than the MSB of the word line address of the second write command CMD2. In this example, the write operations corresponding to the first write command CMD1and the second write command CMD2may be simultaneously performed only when the MSB of the word line address of the first write command CMD1is different from the MSB of the word line address of the second write command CMD2, and the other bits other than the MSB of the word line address of the first write command CMD1are the same as the other bits other than the MSB of the word line address of the second write command CMD2.

The command comparison circuit230may compare the word line addresses, the bit line addresses, and the pieces of write data for two write commands (that is, the first write command and the second write command) among the plurality of write commands queued in the command queue220and output the simultaneous write control signal CTRL_RW of the first level (that is, a high level) when the first write command and the second write command are commands which can be simultaneously performed and output the simultaneous write control signal CTRL_RW of the second level (that is, a low level) when the first write command and the second write command are commands which cannot be simultaneously performed.

The first write command CMD1and the second write command CMD2that the MSBs of the word line addresses are different from each other and the bit line addresses and the pieces of write data are the same as each other are illustrated inFIG. 7. It may be assumed that other bits other than the MSB of the word line address of the first write command CMD1are the same as other bits other than the MSB of the word line address of the second write command CMD2. An operation of the command comparison circuit230which compares the first write command CMD1and the second write command CMD2and output a result value for the comparison will be described with reference toFIG. 7. Hereinafter, the command comparison circuit230including the first comparison circuit CC1ofFIG. 6Awill be described for example, but the command comparison circuit230including the first comparison circuit CC1ofFIG. 6Bmay be operated in the same manner as the operation illustrated inFIG. 7.

Since the MSB WLMSBof the word line address for the first write command CMD1is different from the MSB WLMSBof the word line address for the second write command CMD2, the first comparison circuit CC1including the XOR gate may output a logic value (‘1’) of the first level.

Since all the bits of the bit line address for the first write command CMD1are the same as all the bits of the bit line address for the second write command CMD2, the first stage S1of the second comparison circuit CC2including the XNOR gates may output a plurality of logic values (‘1’) of the first level. The second stage S2of the second comparison circuit CC2including the AND gate may output a logic value (‘1’) of the first level.

Since the write data for the first write command CMD1is the same as the write data for the second write command CMD2, the third comparison circuit CC3including the XNOR gate may output a logic value (‘1’) of the first level.

Since the output values of the first comparison circuit CC1, the second comparison circuit CC2, and the third comparison circuit CC3have all the logic value (‘1’) of the first level, the second comparison operation block CB2including the AND gate may output the simultaneous write control signal CTRL_RW of the first level.

As described above, the simultaneous write control signal CTRL_RW output from the command comparison circuit230may be input to the write driver WD. For example, the simultaneous write control signal CTRL_RW output from the command comparison circuit230may be input to the switching element S coupled to one current source (for example, the second current source I2) among the current sources coupled in parallel in the current increasing circuit CIC of the write driver WD and thus the switching element S may be turned on or turned off. When the simultaneous write control signal CTRL_RW of the first level is input, the switching element S may be turned on and the write driver WD may output the doubled write current 2IWRT, which is increased twice more than the original current IWRT, to the column decoder Y-Dec.

The processor210may transmit a simultaneous write command for simultaneously performing the write operation on two memory cells to the memory apparatus100based on the simultaneous write control signal CTRL_RW output from the command comparison circuit230. The simultaneous write command may include addresses and pieces of write data for the two memory cells on which the write operation is to be simultaneously performed or substantially simultaneously performed.

For example, when the simultaneous write control signal CTRL_RW of the second level is output from the command comparison circuit230, the processor210may determine that the first write command CMD1and the second write command CDM2may not be simultaneously performed and the commands queued in the command queue220may be sequentially transmitted to the memory apparatus100.

When the simultaneous write control signal CTRL_RW of the first level is output from the command comparison circuit230, the processor210may determine that the first write command CMD1and the second write command CMD2may be simultaneously performed and may transmit the simultaneous write command including all the word line addresses, the bit line addresses, and the pieces of write data for the first write command CMD1and the second write command CMD2to the memory command100.

For example, the processor210may transmit the common bit line address and the command write data for the first write command CMD1and the second write command CMD2and two word line addresses for the first write command CMD1and the second write command CMD2to the memory apparatus100.

In this example, when the MSB and the other bits of the word line address of the first write command CMD1are different from the MSB and the other bits of the word line address of the second write command CDM2, the processor201may transmit both the word line address of the first write command CMD1and the word line address of the second write command CMD2to the memory apparatus100.

When the other bits other than the MSB of the word line address of the first write command CMD1are the same as the other bits other than the MSB of the word line address of the second write command CDM2, the processor210may transmit the word line address, the bit line address, and the write data of the first write command CMD1(or the second write command CMD2) and a value of the MSB of the word line address of the second write command CMD2(or the first write command CMD1) to the memory apparatus100, but the embodiments are not limited thereto.

Referring toFIGS. 3 and 8, the control logic120of the memory apparatus100may output the column address Y_ADDR for selecting a common bit line and a row address X_ADDR for selecting two word lines to the row decoder X-Dec and the column decoder Y-Dec based on a common bit line address (for example, ‘BL3’), common write data (for example, ‘1’), and two word line addresses (for example, ‘WL3’ and ‘WL2051’) for the simultaneous write command received from the memory controller200. When the bit line BL3is selected through the column decoder Y-Dec and the word lines WL3and WL2051are selected through the row decoder X-Dec, one bit line BL3and two word lines WL3and WL2051sharing the one bit line BL3may be enabled. The enabled two word lines WL3and WL2051may be arranged in the upper tile group UTG and the lower tile group LTG, respectively.

As the simultaneous write control signal CTRL_RW of the first level is input to the switching element S of the write driver WD and thus the switching element S is turned on, the write driver WD may output the doubled write current 2IWRTto the column decoder Y-Dec.

As described above, since one word line WL3in the upper tile group UTG is enabled and one word line WL2051in the lower tile group LTG is enabled, the doubled write current 2IWRToutput from the write driver WD may be distributed to the upper tile group UTG and the lower tile group LTG in the column decoder Y-Dec.

That is, since two word lines WL3and WL2051are enabled and a resistance to the word line WL3from the column decoder Y-Dec is substantially the same as a resistance to the word line WL2051from the column decoder Y-Dec, a partial write current IWRTof the doubled write current 2IWRTmay flow toward the upper word line WL3in the upper tile group UTG along the bit line BL3and the remaining write current IWRTmay flow toward the lower word line WL2051in the lower tile group LTG along the bit line BL3. Accordingly, data may be simultaneously written or substantially simultaneously written in a memory cell arranged in an intersection region of the bit line BL3and the word line WL3and a memory cell arranged in an intersection region of the bit line BL3and the word line WL2051.

Since a distance from the column decoder Y-Dec to the intersection region of the word line WL3and the bit line BL3is substantially the same as a distance from the column decoder Y-Dec to the intersection region of the word line WL2051and the bit line BL3as described above, the resistances values may be the same as each other or substantially the same as each other. Accordingly, the write current IWRTflowing toward the word line WL3may be substantially the same as the write current IWRTflowing toward the word line WL2051.

After the processor210transmits the simultaneous write command for the first write command CMD1and the second write command CMD2to the memory apparatus100, the processor210may delete write commands in which the simultaneous write operation is performed from the command queue220and rearrange the order of the remaining write commands in the command queue220.

FIG. 9is a block diagram illustrating an example of a representation of an electronic system employing a memory system according to an embodiment of the present technical spirit.

Referring toFIG. 9, an electronic system50may include a processor501, a memory controller503, a resistive memory apparatus505, an input/output (I/O) apparatus507, and a function module500.

The memory controller503may control a data processing operation of the resistive memory apparatus505, for example, a write operation, a read operation, and the like according to control of the processor501. In an embodiment, the memory controller503may be the memory controller200illustrated inFIG. 1and may determine whether or not write commands which can be simultaneously performed are presented among write commands received from a host apparatus (not illustrated) and control the resistive memory apparatus505to perform the write operation on one memory cell or to simultaneously perform the write operation on a plurality of memory cells according to the determination result.

Data programmed in the resistive memory apparatus505may be output through the I/O apparatus507according to control of the processor501and the memory controller503. For example, the I/O apparatus507may include a display apparatus, a speaker apparatus, and the like.

The I/O apparatus507may also include an input apparatus, and the I/O apparatus507may input a control signal for controlling an operation of the processor501or data to be processed in the processor501through the input apparatus.

In an embodiment, the memory controller503may be implemented with a portion of the processor501or a separate chipset from the processor501.

The resistive memory apparatus505may include, for example, a memory region configured of a resistive memory device, an address decoder, a controller, a voltage generator, and the like. In an embodiment, the resistive memory apparatus505may be the resistive memory apparatus100illustrated inFIG. 1. The resistive memory apparatus505may be configured to simultaneously perform the write operation on a plurality of memory cells coupled to one bit line according to control of the memory controller503.

The function module500may be a module which may perform a function selected according to an application example of the electronic system50illustrated inFIG. 9, and a communication module509and an image sensor511as an example of the function module500are illustrated inFIG. 9.

The communication module509may provide a communication environment that the electronic system50is coupled to a wired or wireless communication network to exchange data and a control signal.

The image sensor511may convert an optical image to digital image signals and transfer the digital image signals to the processor501and the memory controller503.

When the function module500includes the communication module509, the electronic system50ofFIG. 9may be a portable communication apparatus such as a wireless communication terminal. When the function module500may include the image sensor511, the electronic system50may be a digital camera, a digital camcorder, or an electronic system (for example, a personal computer (PC), a laptop computer, a mobile communication terminal, and the like) to which any one of the digital camera and the digital camcorder is attached.

FIG. 10is a block diagram illustrating an example of a representation of a memory card system employing a memory system according to an embodiment of the present technical spirit.

Referring toFIG. 10, a memory card system60may include a card interface601, a memory controller603, and a resistive memory apparatus605.

FIG. 10is an illustrative diagram illustrating the memory card system60used as a memory card or a smart card, and the memory card system60illustrated inFIG. 10may be any one among a PC card, a multimedia card, an embedded multimedia card, a secure digital card, and a universal serial bus (USB) drive.

The card interface601may perform interacting on data exchange between a host and the memory controller603according to a protocol of the host. In an embodiment, the card interface601may refer to hardware which may support a protocol used in the host, software installed in the hardware which may support the protocol used in the host, or a signal transmission method.

The memory controller603may control data exchange between the resistive memory apparatus605and the card interface601. The memory controller603may be the memory controller200illustrated inFIG. 1and may determine whether or not write commands which can be simultaneously performed are presented among write commands received from the host and control the resistive memory apparatus605to simultaneously perform the write operation on a plurality of memory cells coupled to one bit line according to the determination result.

The memory apparatus100illustrated inFIG. 1may be used for the resistive memory apparatus605. The resistive memory apparatus605may be configured to simultaneously perform the write operation on a plurality of memory cells coupled to one bit line according to control of the memory controller603.

The above embodiments are illustrative and not limitative. Various alternatives and equivalents are possible. The embodiments are not limited by the embodiments described herein. Nor are the embodiments limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.