FIFO circuit for DDR memory system

A FIFO circuit for a DDR memory system includes a pointer generator and a FIFO circuit. The FIFO circuit includes a pointer generator and a FIFO buffer. The pointer generator receives a first reset signal and a delay select signal from the memory controller. After the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock. An input data is stored into the FIFO buffer according to the first reference clock and the write pointer. An output data is outputted from the FIFO buffer according to the second reference clock and the read pointer.

This application claims the benefit of Taiwan Patent Application No. 107115107, filed May 3, 2018, the subject matter of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a circuit of a memory system, and more particularly to a first-in-first-out (FIFO) circuit for a double data rate (DDR) memory system.

BACKGROUND OF THE INVENTION

FIG. 1is a schematic functional block diagram illustrating the architecture of a conventional DDR memory system. As shown inFIG. 1, the DDR memory system100comprises an application-specific integrated circuit (ASIC)110and a DDR memory120.

The ASIC110comprises a memory controller112and a physical layer (PHY) circuit114. The PHY circuit114of the ASIC110and the DDR memory120exchange various signals through a memory bus122. A DDR PHY Interface116, which is also referred as a DFI interface, is connected between the memory controller112and the PHY circuit114. That is, plural signals are transmitted between the memory controller112and the PHY circuit114through the DFI interface116.

The ASIC110further comprises a phase-locked loop (PLL)118. The PLL118generates a DFI clock (DFIclk) to the memory controller112and the PHY circuit114. Consequently, the memory controller112and the PHY circuit114are operated in the same DFI clock domain.

The PHY circuit114further comprises a data physical layer circuit (Data0 PHY)131, a data physical layer circuit (Data1 PHY)132and a command physical layer circuit (CMD PHY) circuit133. Of course, the PHY circuit114of the ASIC110may comprise more than two data physical layer circuits. As the data amount increases, the number of the data physical layer circuit increases.

When the memory controller112intends to store a write data into the DDR memory120, the memory controller112generates a write command and the write data. The write command is transmitted from the memory controller112to the CMD PHY circuit133through the DFI interface116. In addition, the write command is transmitted from the CMD PHY circuit133to the DDR memory120through the memory bus122. The write data is transmitted from the memory controller112to the two data physical layers131and132through the DFI interface116. In addition, the write data is transmitted from the two data physical layers131and132to the DDR memory120through the memory bus122. Consequently, the write data is stored into the DDR memory120according to the write command.

When the memory controller112intends to acquire a read data from the DDR memory120, the memory controller112generates a read command. The read command is transmitted from the memory controller112to the CMD PHY circuit133through the DFI interface116. In addition, the read command is transmitted from the CMD PHY circuit133to the DDR memory120through the memory bus122. Moreover, the DDR memory120generates the read data according to the read command. The read data is transmitted from the DDR memory120to the two data physical layers131and132through the memory bus122. In addition, the read data is transmitted from the two data physical layers131and132to the memory controller112through the DFI interface116.

As mentioned above, the CMD PHY circuit133transfers the command in one direction, and the two data physical layers131and132transfer data in two directions.

According to the specifications of the DDR memory120, the write command and the write data are transferred according to a specified timing sequence relationship. After the memory controller112transfers the write command and the write data to the PHY circuit114according to a specified timing sequence relationship, the PHY circuit114transfers the write command and the write data to the DDR memory120according to the specified timing sequence relationship. Similarly, the read command and the read data are transferred according to the specified timing sequence relationship.

The memory controller112, the PHY circuit114and the DFI interface116in the ASIC110are operated to transfer various signals according to the DFI clock (DFIclk). Consequently, the DDR memory controller112and PHY circuit114have to perform the clock tree balance from a DFI clock tree root.

In practice, the CMD PHY circuit133and the data physical layers131and132are allocated at different positions of the ASIC110. In other words, it is almost impossible to design the suitable DFI clock tree root.

Consequently, after the memory controller112transfers the write command and the write data according to the specified timing sequence relationship, the write command and the write data received by the PHY circuit114are not maintained according to the specified timing sequence relationship. Consequently, the write data or the read data is possibly lost or the DDR memory120is erroneously operated.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a FIFO circuit. The FIFO circuit includes a pointer generator and a FIFO buffer. The pointer generator receives a first reset signal and a delay select signal from the memory controller. After the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock and the delay select signal. An input data is stored into the FIFO buffer according to the first reference clock and the write pointer. An output data is outputted from the FIFO buffer according to the second reference clock and the read pointer.

Another embodiment of the present invention provides a double data rate memory system. The double data rate memory system includes a double data rate memory and an application-specific integrated circuit. The application-specific integrated circuit is connected with the double data rate memory. The application-specific integrated circuit includes a FIFO circuit. The FIFO circuit is connected between a memory controller and a physical layer circuit. The FIFO circuit includes a pointer generator and a FIFO buffer. The pointer generator receives a first reset signal and a delay select signal from the memory controller. After the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock and the delay select signal. An input data is stored into the FIFO buffer according to the first reference clock and the write pointer. An output data is outputted from the FIFO buffer according to the second reference clock and the read pointer.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 2is a schematic functional block diagram illustrating the architecture of a DDR memory system according to an embodiment of the present invention. As shown inFIG. 2, the DDR memory system200comprises an ASIC205and a DDR memory120.

The ASIC205comprises a memory controller112, a first-in-first-out (FIFO) circuit208and a physical layer (PHY) circuit114. The PHY circuit114of the ASIC205and the DDR memory120exchange various signals through a memory bus122.

The PHY circuit114further comprises a data physical layer circuit (Data0 PHY)131, a data physical layer circuit (Data1 PHY)132and a command physical layer circuit (CMD PHY) circuit133. Of course, the PHY circuit114of the ASIC110may comprise more than two data physical layer circuits. As the data amount increases, the number of the data physical layer circuit increases.

The ASIC205further comprises a phase-locked loop (PLL)290. The PLL290generates a DFI clock (DFIclk) to the memory controller112. After the DFI clock (DFIclk) is processed by plural clock buffers295and296, a main clock (Mclk) is generated. In other words, the main clock (Mclk) and the DFI clock (DFIclk) have the same frequency but have different phases.

The memory controller112controls the FIFO circuit208according to a reset signal RST. When the reset signal RST is asserted, the FIFO circuit208is in a reset state. In the reset state, the FIFO circuit208is disabled.

When the reset signal RST is de-asserted, the FIFO circuit208is enabled. Meanwhile, the pointer generator260of the FIFO circuit208generates a write pointer Wptr1and generates a read pointer Rptr1according to a delay select signal SELd1. Consequently, the operations of the write data FIFO buffer (Wdata0 FIFO)210, the write data FIFO buffer (Wdata1 FIFO)230and the command FIFO buffer (CMD FIFO)250are controlled. Moreover, the pointer generator270of the FIFO circuit208generates a write pointer Wptr2and generates a read pointer Rptr2according to a delay select signal SELd2. Consequently, the operations of the read data FIFO butter (Rdata0 FIFO)220and the read data FIFO butter (Rdata1 FIFO)240are controlled.

In an embodiment, the PHY circuit114is operated according to the DFI clock (DFIclk). That is, the PHY circuit114is operated in the DFI clock domain. The memory controller112is operated according to the main clock (Mclk). That is, the memory controller112is operated in the main clock domain.

A portion of the FIFO circuit208is operated according to the main clock (Mclk). Another portion of the FIFO circuit208is operated according to the DFI clock (DFIclk). In other words, the FIFO circuit208exchanges data between the main clock domain and the DFI clock domain.

When the memory controller112intends to store a write data into the DDR memory120, the memory controller112generates a write command and the write data according to the main clock (Mclk). Moreover, according to the main clock (Mclk), the write command is inputted into the command FIFO buffer (CMD FIFO)250, and the write data is inputted into the write data FIFO buffer (Wdata0 FIFO)210and the write data FIFO buffer (Wdata1 FIFO)230.

Then, according to the DFI clock (DFIclk), the write command is outputted from the command FIFO buffer (CMD FIFO)250and the write data is outputted from the write data FIFO buffer (Wdata0 FIFO)210and the write data FIFO buffer (Wdata1 FIFO)230. Then, the write command is transmitted to the command physical layer circuit (CMD PHY) circuit133of the PHY circuit114, and the write data is transmitted to the data physical layer circuit (Data0 PHY)131and the data physical layer circuit (Data1 PHY)132of the PHY circuit114. Then, the write command is transmitted from the CMD PHY circuit133to the DDR memory120through the memory bus122. In addition, the write data is transmitted from the two data physical layers131and132to the DDR memory120through the memory bus122. Consequently, the write data is stored into the DDR memory120according to the write command.

When the memory controller112intends to acquire a read data from the DDR memory120, the memory controller112generates a read command according to the main clock (Mclk). The read command is inputted into the command FIFO buffer (CMD FIFO)250. Then, according to the DFI clock (DFIclk), the read command is outputted from the command FIFO buffer (CMD FIFO)250to the CMD PHY circuit133to the DDR memory120. Then, the read command is transmitted from the CMD PHY circuit133to the DDR memory120through the memory bus122.

Moreover, the DDR memory120generates the read data according to the read command. The read data is transmitted from the DDR memory120to the two data physical layers131and132through the memory bus122. Then, according to the DFI clock (DFIclk), the read data is transmitted from the two data physical layers131and132to the read data FIFO butter (Rdata0 FIFO)220and the read data FIFO butter (Rdata1 FIFO)240. Then, according to the main clock (Mclk), the read data is transmitted from the read data FIFO butter (Rdata0 FIFO)220and the read data FIFO butter (Rdata1 FIFO)240to the memory controller112.

The pointer generator260is used for controlling the write data FIFO buffer (Wdata0 FIFO)210, the write data FIFO buffer (Wdata1 FIFO)230and the command FIFO buffer (CMD FIFO)250. The pointer generator270is used for controlling the read data FIFO butter (Rdata0 FIFO)220and the read data FIFO butter (Rdata1 FIFO)240. The circuits and operations of the pointer generator260, the write data FIFO buffer (Wdata0 FIFO)210, the write data FIFO buffer (Wdata1 FIFO)230and the command FIFO buffer (CMD FIFO)250will be described as follows.

FIG. 3Ais a schematic functional block diagram illustrating the pointer generator260of the DDR memory system according to the embodiment of the present invention.FIG. 3Bis a schematic timing waveform diagram illustrating associated signals processed by the pointer generator ofFIG. 3A. The pointer generator260comprises a control circuit310, a first ring counter312and a second ring counter314. The control circuit310receives the reset signal RST and the delay select signal SELd1. Moreover, the control circuit310issues reset signals RSTa and RSTb to the first ring counter312and the second ring counter314, respectively. The first ring counter312generates the write pointer Wptr1according to a first reference clock CLK1. The second ring counter314generates the read pointer Rptr1according to a second reference clock CLK2.

When the memory controller112generates a write command, a read command or a write data to the DDR memory120, the first reference clock CLK1is the main clock (Mclk) and the second reference clock CLK2is the DFI clock (DFIclk).

In case that the reset signal RST is asserted, the reset signals RSTa and RSTb are also asserted by the control circuit310. Consequently, the first ring counter312and the second ring counter314do not start counting. In case that the reset signal RST is de-asserted, the reset signal RSTa is firstly de-asserted by the control circuit310and then the reset signal RSTb is de-asserted by the control circuit310according to the delay select signal SELd1. Consequently, the first ring counter312and the second ring counter314start counting. In addition, the first ring counter312generates the write pointer Wptr1, and the second ring counter314generates the read pointer Rptr1.

Please refer toFIG. 3B. Before the time point ta, the reset signal RST is asserted (i.e., in a low level state). Since the reset signals RSTa and RSTb are also asserted (i.e., in the low level state), the first ring counter312and the second ring counter314do not start counting.

At the time point ta, the reset signal RST is de-asserted (i.e., in a high level state). Consequently, the reset signal RSTa is de-asserted by the control circuit310at the time point tb, and the reset signal RSTb is de-asserted by the control circuit310at the time point tc. The time point tc of de-asserting the reset signal RSTb is after the time point tb of de-asserting the reset signal RSTa. Moreover, the time point of de-asserting the reset signal RSTb may be adjusted according to the delay select signal SELd1.

Please refer toFIG. 3B. In case that the delay select signal SELd1is “1” (i.e., SELd1=“1”), the delay select signal SELd1is de-asserted at the time point tc. In case that the delay select signal SELd1is “0” (i.e., SELd1=“0”), the delay select signal SELd1is de-asserted at the time point tc′. The time difference between the time point tc′ and the time point tc is equal to one cycle of the second clock CLK2. In case that the delay select signal SELd1is “2” (i.e., SELd1=“2”), the delay select signal SELd1is de-asserted at the time point tc“. The time difference between the time point tc and the time point tc” is equal to one cycle of the second clock CLK2. In the following example, the reset signal RSTb is de-asserted by the control circuit310at the time point tc.

After the reset signal RSTa is de-asserted at the time point tb, the first ring counter312cyclically counts from 0 to 2 and generates the write pointer Wptr1according to the main clock (Mclk). After the reset signal RSTb is de-asserted at the time point tc, the second ring counter314cyclically counts from 0 to 2 and generates the read pointer Rptr1according to the DFI clock (DFIclk).

As mentioned above, the pointer generator260receives the reset signal RST and the delay select signal SELd1from the memory controller112. When the reset signal RST is de-asserted, the pointer generator260generates the write pointer Wptr1according to the first reference clock CLK1and the pointer generator260generates the read pointer Rptr1according to the second reference clock CLK2and the delay select signal SELd1.

FIG. 3Cis a schematic functional block diagram illustrating the write data FIFO buffer of the FIFO circuit of the DDR memory system according to the embodiment of the present invention.FIG. 3Dis a schematic timing waveform diagram illustrating associated signals processed by the FIFO buffer ofFIG. 3C. The FIFO buffer is the write data FIFO buffer (Wdata0 FIFO)210, the write data FIFO buffer (Wdata1 FIFO)230or the command FIFO buffer (CMD FIFO)250.

The FIFO buffer comprises a first select circuit320, a second select circuit322, a first storage circuit323, a second storage circuit325, a third storage circuit327and a fourth storage circuit329. The first storage circuit323, the second storage circuit325and the third storage circuit327are operated according to the first reference clock CLK1. The fourth storage circuit329is operated according to the second reference clock CLK2.

The first select circuit320receives a data signal D1iand the write pointer Wptr1. Moreover, the first select circuit320is connected with the input terminals of the first storage circuit323, the second storage circuit325and the third storage circuit327. According to the value of the write pointer Wptr1, the first select circuit320outputs the data signal D1ito a corresponding storage circuit of the first storage circuit323, the second storage circuit325and the third storage circuit327. The data signal D1iis a command signal or the write data.

The second select circuit322is connected with the output terminals S0, S1and S2of the first storage circuit323, the second storage circuit325and the third storage circuit327, respectively. Moreover, the second select circuit322is connected with the input terminal of the fourth storage circuit329. According to the value of the read pointer Rptr1, the data from one of the output terminals S0, S1and S2of the first storage circuit323, the second storage circuit325and the third storage circuit327is outputted from the second select circuit322to the fourth storage circuit329. Consequently, the fourth storage circuit329generates a data signal D1o.

Please refer toFIG. 3D. The operations of the reset signals RST, RSTa, RSTb, the write pointer Wptr1and the read pointer Rptr1ofFIG. 3Dare similar to those ofFIG. 3B, and are not redundantly described herein.

At the time point t1corresponding to a rising edge of the main clock (Mclk), the value of the write pointer Wptr1is “0” and the content of the data signal D1iis “A”. Consequently, the content “A” of the data signal D1iis transmitted to the first storage circuit323. That is, the output signal S0of the first storage circuit323is “A”. As shown inFIG. 3D, the write pointer Wptr1is restored to “0” again after three cycles of the main clock (Mclk). Meanwhile, the content “A” of the data signal D1iin the first storage circuit323is replaced by the content “D”. The rest may be deduced by analogy.

At the time point t2corresponding to a rising edge of the main clock (Mclk), the value of the write pointer Wptr1is “1” and the content of the data signal D1iis “B”. Consequently, the content “B” of the data signal D1iis transmitted to the second storage circuit325. That is, the output signal S1of the second storage circuit325is “B”. As shown inFIG. 3D, the write pointer Wptr1is restored to “1” again after three cycles of the main clock (Mclk). Meanwhile, the content “B” of the data signal D1iin the second storage circuit325is replaced by the content “E”. The rest may be deduced by analogy.

At the time point t3corresponding to a rising edge of the main clock (Mclk), the value of the write pointer Wptr1is “2” and the content of the data signal D1iis “C”. Consequently, the content “C” of the data signal D1iis transmitted to the third storage circuit327. That is, the output signal S2of the third storage circuit327is “C”. As shown inFIG. 3D, the write pointer Wptr1is restored to “2” again after three cycles of the main clock (Mclk). Meanwhile, the content “F” of the data signal D1iin the third storage circuit327is replaced by the content “E”. The rest may be deduced by analogy.

As mentioned above, the data valid time of the output signals S0, S1and S2from the storage circuits323,324and325is equal to three cycles of the main clock (Mclk).

At the time point t4corresponding to a rising edge of the DFI clock (DFIclk), the value of the read pointer Rptr1is “0” and the output signal S0of the first storage circuit323is “A”. Consequently, the content “A” of the output signal S0of the first storage circuit323is transmitted to the fourth storage circuit329. That is, the data signal D10of the fourth storage circuit329is “A”.

At the time point t5corresponding to a rising edge of the DFI clock (DFIclk), the value of the read pointer Rptr1is “1” and the output signal S1of the second storage circuit325is “B”. Consequently, the content “B” of the output signal S1of the second storage circuit325is transmitted to the fourth storage circuit329. That is, the data signal D10of the fourth storage circuit329is “B”.

At the time point t6corresponding to a rising edge of the DFI clock (DFIclk), the value of the read pointer Rptr1is “2” and the output signal S2of the third storage circuit327is “C”. Consequently, the content “C” of the output signal S2of the third storage circuit327is transmitted to the fourth storage circuit329. That is, the data signal D10of the fourth storage circuit329is “C”. The rest may be deduced by analogy. In other words, the data signals D10of the fourth storage circuit329are sequentially D″, “E”, “F”, and so on.

From the above descriptions, the data signal D10and the DFI clock (DFIclk) are synchronized because the fourth storage circuit329is operated according to the DFI clock (DFIclk). In other words, the FIFO circuit208exchanges data between the main clock domain and the DFI clock domain. Consequently, a specified timing sequence relationship between the write command and the write data can be maintained.

The structure of the pointer generator270is identical to the structure of the pointer generator260. However, the signals received by the pointer generator270are different from the signals received by the pointer generator260. The FIFO buffers210,220,230,240and250have the same structure. Hereinafter, the connecting relationships between the pointer generator270, the read data FIFO butter (Rdata0 FIFO)220and the read data FIFO butter (Rdata1 FIFO)240will be described as follows. For succinctness, the operations of these components are omitted.

FIG. 4Ais a schematic functional block diagram illustrating the pointer generator270of the DDR memory system according to the embodiment of the present invention. The pointer generator270is used for controlling the read data FIFO butter (Rdata0 FIFO)220and the read data FIFO butter (Rdata1 FIFO)240.

In comparison with the pointer generator260, the first reference clock CLK1and the second reference clock CLK2of the pointer generator270are the DFI clock (DFIclk) and the main clock (Mclk), respectively.

The pointer generator270comprises a control circuit360, a first ring counter362and a second ring counter364. The control circuit310receives the reset signal RST and the delay select signal SELd2. Moreover, the control circuit360issues the reset signals RSTa and RSTb to the first ring counter362and the second ring counter364, respectively. The first ring counter362generates the write pointer Wptr2according to the first reference clock CLK1. The second ring counter364generates the read pointer Rptr2according to the second reference clock CLK2.

FIG. 4Bis a schematic functional block diagram illustrating the read data FIFO buffer of the FIFO circuit of the DDR memory system according to the embodiment of the present invention. The read data FIFO buffer is the read data FIFO butter (Rdata0 FIFO)220or the read data FIFO butter (Rdata1 FIFO)240.

FIFO buffer comprises a first select circuit370, a second select circuit372, a first storage circuit373, a second storage circuit375, a third storage circuit377and a fourth storage circuit379. The first storage circuit373, the second storage circuit375and the third storage circuit377are operated according to the first reference clock CLK1. The fourth storage circuit379is operated according to the second reference clock CLK2.

The first select circuit370receives a data signal D2iand the write pointer Wptr2. Moreover, the first select circuit370is connected with the input terminals of the first storage circuit373, the second storage circuit375and the third storage circuit377. According to the value of the write pointer Wptr2, the first select circuit370outputs the data signal D2ito a corresponding storage circuit of the first storage circuit373, the second storage circuit375and the third storage circuit377. The data signal D2iis a read data.

The second select circuit372is connected with the output terminals S0, S1and S2of the first storage circuit373, the second storage circuit375and the third storage circuit377, respectively. Moreover, the second select circuit372is connected with the input terminal of the fourth storage circuit379. According to the value of the read pointer Rptr2, the data from one of the output terminals S0, S1and S2of the first storage circuit373, the second storage circuit375and the third storage circuit377is outputted from the second select circuit372to the fourth storage circuit379. Consequently, the fourth storage circuit379generates a data signal D2o.

FIG. 5Ais a schematic circuit diagram illustrating the pointer generator of the DDR memory system according to the embodiment of the present invention.FIG. 5Bis a schematic circuit diagram illustrating the FIFO buffer of the FIFO circuit of the DDR memory system according to the embodiment of the present invention.FIG. 5Cis a schematic timing waveform diagram illustrating associated signals processed by the pointer generator ofFIG. 5A. For illustration, the pointer generator is the pointer generator260, and the FIFO buffer is the write data FIFO buffer (Wdata0 FIFO)210, the write data FIFO buffer (Wdata1 FIFO)230or the command FIFO buffer (CMD FIFO)250. The structure and function of the pointer generator270are similar to those of the pointer generator260. The structure and function of the read data FIFO butter (Rdata0 FIFO)220and the read data FIFO butter (Rdata1 FIFO)240are similar to those of the write data FIFO buffer (Wdata0 FIFO)210, the write data FIFO buffer (Wdata1 FIFO)230and the command FIFO buffer (CMD FIFO)250. For succinctness, the operations of these components are omitted.

The above circuits are presented herein for purpose of illustration and description only. It is noted that numerous modifications and alterations of the pointer generator and the FIFO buffer may be made while retaining the teachings of the invention.

As shown inFIG. 5A, the control circuit310of the pointer generator260comprises plural D type flip-flops401˜417and a multiplexer420. The clock input terminals of the D type flip-flops401˜405receive the first clock CLK1. The clock input terminals of the D type flip-flops411˜417receive the second clock CLK2. The first reference clock CLK1is the main clock (Mclk). The second reference clock CLK2is the DFI clock (DFIclk).

The reset terminals of the D type flip-flops401and402receive the reset signal RST. The input terminal of the D type flip-flop401receives a high voltage level “Hi”. The output terminal of the D type flip-flop401issues a reset signal ra_1. The input terminal of the D type flip-flop402receives the reset signal ra_1. The output terminal of the D type flip-flop402issues a reset signal ra_2.

The reset terminals of the D type flip-flops403,404and405receive the reset signal ra_2. The input terminal of the D type flip-flop403receives the high voltage level “Hi”. The output terminal of the D type flip-flop403issues a reset signal ra_3. The input terminal of the D type flip-flop404receives the reset signal ra_3. The output terminal of the D type flip-flop404issues a reset signal ra_4. The input terminal of the D type flip-flop405receives the reset signal ra_4. The output terminal of the D type flip-flop405issues the reset signal RSTa.

The reset terminals of the D type flip-flops411and412receive the reset signal ra_2. The input terminal of the D type flip-flop411receives the high voltage level “Hi”. The output terminal of the D type flip-flop411issues a reset signal rb_1. The input terminal of the D type flip-flop412receives the reset signal rb_1. The output terminal of the D type flip-flop412issues a reset signal rb_2.

The reset terminals of the D type flip-flops413,414,415,416and417receive the reset signal rb_2. The input terminal of the D type flip-flop413receives the high voltage level “Hi”. The output terminal of the D type flip-flop413issues a reset signal rb_3. The input terminal of the D type flip-flop414receives the reset signal rb_3. The output terminal of the D type flip-flop414issues a reset signal rb_4. The input terminal of the D type flip-flop415receives the reset signal rb_4. The output terminal of the D type flip-flop415issues a reset signal rb_5. The input terminal of the D type flip-flop416receives the reset signal rb_5. The output terminal of the D type flip-flop416issues a reset signal rb_6.

The select terminal of the multiplexer420receives the delay select signal SELd1. The first input terminal of the multiplexer420receives the reset signal rb_3. The second input terminal of the multiplexer420receives the reset signal rb_4. The third input terminal of the multiplexer420receives the reset signal rb_5. The fourth input terminal of the multiplexer420receives the reset signal rb_6. According to the delay select signal SELd1, one of the reset signal rb_3, the reset signal rb_4, the reset signal rb_5and the reset signal rb_6is outputted from the output terminal of the multiplexer420. Moreover, the input terminal of the D type flip-flop417is connected with the output terminal of the multiplexer420, and the output terminal of the D type flip-flop417issues the reset signal RSTb.

The first ring counter312generates the write pointer Wptr1according to the first reference clock CLK1. The second ring counter314generates the read pointer Rptr1according to the second reference clock CLK2. The circuits of the first ring counter312and the second ring counter314are not restricted. That is, various ring counters known to those skilled in the art may be used as the first ring counter312and the second ring counter314.

Please refer toFIG. 5B. The first select circuit320comprises a first AND gate451, a second AND gate452and a third AND gate453. The first input terminal of the first AND gate451receives the data signal D1i. The second input terminal of the first AND gate451receives the value “0” of the write pointer Wptr1(i.e., Wptr1=“0”). The first input terminal of the second AND gate452receives the data signal D1i. The second input terminal of the second AND gate452receives the value “1” of the write pointer Wptr1(i.e., Wptr1=“1”). The first input terminal of the third AND gate453receives the data signal D1i. The second input terminal of the third AND gate453receives the value “2” of the write pointer Wptr1(i.e., Wptr1=“2”).

The D type flip-flops423,425,427and429are used as the first storage circuit, the second storage circuit, the third storage circuit and the fourth storage circuit, respectively. The clock terminals of the D type flip-flops423,425and427receive the first reference clock CLK1. The reset terminals of the D type flip-flops423,425and427receive the reset signal ra_2. The clock terminal of the D type flip-flop429receives the second reference clock CLK2. The reset terminal of the D type flip-flop429receives the reset signal rb_2. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in another embodiment, the D type flip-flops423,425and427are directly connected with the high voltage level. Under this circumstance, the D type flip-flops423,425and427are continuously in the working state and not reset.

Please refer toFIG. 5Bagain. The input terminal of the D type flip-flop423is connected with the output terminal of the first AND gate451. The output terminal of the D type flip-flop423issues the output signal S0. The input terminal of the D type flip-flop425is connected with the output terminal of the second AND gate452. The output terminal of the D type flip-flop425issues the output signal S1. The input terminal of the D type flip-flop427is connected with the output terminal of the third AND gate453. The output terminal of the D type flip-flop427issues the output signal S2.

A multiplexer422is used as the second select circuit. The first input terminal of the multiplexer422receives the output signal S0. The second input terminal of the multiplexer422receives the output signal S1. The third input terminal of the multiplexer422receives the output signal S2. The select terminal of the multiplexer422receives the read pointer Rptr1. The input terminal of the D type flip-flop429is connected with the output terminal of the multiplexer422. The output terminal of the D type flip-flop429generates the data signal D1o.

Please refer toFIG. 5C. After the reset signal RST is de-asserted (i.e., in the high level state), the reset signals ra_1, ra_2, ra_3, ra_4and RSTa are sequentially de-asserted at the time interval of one cycle of the first reference clock CLK1. After the reset signal ra_2is de-asserted (i.e., in the high level state), the reset signals rb_1, rb_2, rb_3, rb_4, rb_5and rb_6are sequentially de-asserted at the time interval of one cycle of the second reference clock CLK2.

According to the first reference clock CLK1and according to the write pointer Wptr1, the first select circuit320inputs the data signal D1iinto the corresponding storage circuits423,425and427. Consequently, the content of the output signal S0from the D type flip-flop423is “A”, the content of the output signal S1from the D type flip-flop425is “B”, and the content of the output signal S2from the D type flip-flop427is “C”. As the write pointer Wptr1is changed, the contents of the output signals are correspondingly changed.

Moreover, according to the value of the read pointer Rptr1and the delay select signal SELd1, the data from one of the output terminals S0, S1and S2of the first storage circuit323, the second storage circuit325and the third storage circuit327is outputted from the second select circuit322to the fourth storage circuit329. Consequently, the fourth storage circuit329generates a data signal D1o.

In case that the value of the delay select signal SELd1is “0” (i.e., SELd1=“0”), the reset signal RSTb and the reset signal rb_4are in phase. Consequently, at the time points ta, tb and tc corresponding to the rising edges of the second reference clock CLK2, the contents A”, “B” and “C” of the output signals S0, S1and S2are sequentially received by the D type flip-flop429. The rest may be deduced by analogy.

In case that the value of the delay select signal SELd1is “1” (i.e., SELd1=“1”), the reset signal RSTb and the reset signal rb_5are in phase. Consequently, at the time points tb, tc and td corresponding to the rising edges of the second reference clock CLK2, the contents A″, “B” and “C” of the output signals S0, S1and S2are sequentially received by the D type flip-flop429. The rest may be deduced by analogy.

In case that the value of the delay select signal SELd1is “2” (i.e., SELd1=“2”), the reset signal RSTb and the reset signal rb_6are in phase. Consequently, at the time points tc, td and to corresponding to the rising edges of the second reference clock CLK2, the contents A”, “B” and “C” of the output signals S0, S1and S2are sequentially received by the D type flip-flop429. The rest may be deduced by analogy.

As mentioned above, the time point of generating the read pointer Rptr1may be properly adjusted according to the delay select signal SELd1. Consequently, the delaying time period between the data signal D1iand the data signal D10is adjustable. In other words, the FIFO circuit208exchanges data between the domain of the first reference clock CLK1and the domain of the second reference clock CLK2according to the proper adjustment of the delay select signal SELd1. Consequently, the accuracy of the data signal D1iand the data signal D10will be enhanced, and the specified timing sequence relationship between the write command and the write data can be maintained.

From the above descriptions, the present invention provides the first-in-first-out (FIFO) circuit for the double data rate (DDR) memory system. Consequently, the memory controller112and the PHY circuit114can be operated in different clock domains. Consequently, the drawbacks of operating the memory controller112and the PHY circuit114in the same clock domain will be overcome.

In the above embodiments, the ring counters312and314count from 0 to 2. It is noted that the counting values of the ring counters may be varied according to the practical requirements. For example, in another embodiment, the ring counters and count from 0 to 3. Under this circumstance, the FIFO buffer comprises a one-to-four select circuit, five storage circuits and a four-to-one select circuit.