Method for fabricating a semiconductor device

A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for fabricating a semiconductor device, and in more particularly relates to a method for fabricating an alignment mark or an overlay mark of a semiconductor device.

2. Description of the Related Art

In recent years, semiconductor device fabricating technology has continually sought new ways to achieve high device performance, lower costs, and high device densities. For example, in the case of a dynamic random access memory (DRAM), high device densities are used for forming high aspect ratio trench capacitor structures during DRAM fabrication.FIG. 1ashows a schematic top view of a substrate of a conventional semiconductor device100. The substrate of the conventional semiconductor device100comprises a device region102and a testkey region104. The device region102is a region for forming patterns comprising trench capacitors, periphery circuits or dummys. The testkey region104is a region for forming patterns comprising alignment marks, overlay marks or critical dimension (CD) testkeys. As shown inFIGS. 1bto1d, the conventional alignment mark or overlay mark testkeys may have various shapes.

During the fabricating processes of the conventional DRAM, a single side buried strap (SSBS) can be used to electrically connect a trench capacitor plate and a source of a subsequent transistor.FIG. 1eis a cross section taken along line A-A′ ofFIG. 1ashowing topography of the device region102and testkey region104after forming the conventional single side buried strap (SSBS)124. After performing the conventional trench capacitor fabricating process, a first trench capacitor120a and SSBS124are formed in a first trench110on the device region102while a second trench capacitor120band another SSBS124are formed in a second trench112on the testkey region104. The conventional DRAM fabricating process comprising SSBS124on device region102, however, causes an asymmetric profile to a central axis170on testkey region104as shown inFIG. 1e. The patterns on the testkey region104, for example, alignment marks or overlay marks, are usually used to control relative positioning of the testkey region104between laminated layers. However, alignment marks with asymmetric profiles causes optical signal judgment problems for inspection machines used in the photolithography processes. The optical signal judgment problems result from a misalignment or overlay error problem during the photolithography processes. As a result, the problems reduce yield and device reliability of the conventional DRAM fabricating processes.

Thus, a novel and reliable method for fabricating alignment marks or overlay marks of a semiconductor device without an asymmetric profile is needed.

BRIEF SUMMARY OF INVENTION

To solve the above-described problems, a method for fabricating a semiconductor device is provided. An exemplary embodiment of a method for fabricating a semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. Next, a first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer is next conformably formed in the first trench and in the second trench and the conductive layer being provided with a first etching selectivity. Next, a first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. The first trench is next covered with a patterned masking layer so that the conductive layer in the second trench is exposed. And next, a second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity, which is higher than the first etching selectivity.

Another exemplary embodiment of a method for fabricating a semiconductor device comprises providing a semiconductor substrate comprising a device region and a testkey region. Next, a first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer which has a first etching selectivity is next conformably formed in the first trench and in the second trench. Next, a patterned masking layer is formed to cover the second trench to retain the first etching selectivity of the conductive layer in the second trench. And next, a doped region and an undoped region are formed in the conductive layer in the first trench, wherein the doped region of the conductive layer in the first trench has a second etching selectivity higher than the first etching selectivity.

DETAILED DESCRIPTION OF INVENTION

The following description is of a mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 2shows a schematic top view of an exemplary embodiment of a substrate of a semiconductor device of the invention.FIGS. 3a,3b,3c,3d,3f,3gand3iare cross sections taken along line A-A′ ofFIG. 2showing an exemplary embodiment of a process of fabricating a semiconductor device of the invention.FIG. 3eshows a schematic top view ofFIG. 3d.FIG. 3hshows a schematic top view ofFIG. 3g.FIGS. 4aand4care cross sections taken along line A-A′ ofFIG. 2showing another exemplary embodiment of a process for fabricating a semiconductor device of the invention.FIG. 4bshows a schematic top view ofFIG. 4a. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer to the same or like parts.

FIG. 2shows a schematic top view of an exemplary embodiment of a semiconductor device of the invention. An exemplary embodiment of a semiconductor device comprises a semiconductor substrate200having a device region202and a testkey region204. Device region202is a region for forming patterns comprising trench capacitors, periphery circuits or dummys. Testkey region204is a region for forming patterns comprising alignment mark, overlay mark or critical dimension (CD) testkeys. Substrate200is preferably a silicon substrate. Also, substrate200may comprise SiGe silicon on insulator (SOI), and other commonly used semiconductor substrates can be used. Alignment marks or the overlay marks in testkey region204may be strap-shaped or dot-shaped from a top view.

FIG. 3ais a cross sections taken along line A-A′ ofFIG. 2showing an exemplary embodiment of a semiconductor device of the invention. An underlying first liner layer206and an overlying second liner layer208are formed on semiconductor substrate200in sequence. First liner layer206may comprise silicon dioxide (SiO2), and second liner layer208may comprise silicon nitride (Si3N4). First liner layer206may be formed on semiconductor substrate200by thermal oxidation process. Next, second liner layer208may be formed on first liner layer206by chemical vapor deposition (CVD) process. Next, a patterned photoresist layer (not shown) is formed on the second liner layer208for defining formation positions of a first trench210and a second trench212. An anisotropic etching process, for example, reactive ion etching (RIE) process, is then performed to remove a portion of first liner layer206and second liner layer208and semiconductor substrate200not covered by the patterned photoresist layer. The first trench210and second trench212are then formed in the device region202and testkey region204, respectively. The patterned photoresist layer is then removed. The first trench210and second trench212both penetrate the first liner layer206and second liner layer208, extending into the semiconductor substrate200. The first trench210and second trench212have high aspect ratio, wherein a critical dimension D2of the second trench212is preferably larger than a critical dimension D1of the first trench210.

Next, buried plates218aand218bare respectively formed in the semiconductor substrate200of the device region202and testkey region204by a fabricating process, such as ion implantation process. Buried plates218aand218bmay be doped regions surrounding inner walls of the first trench210and the second trench212, respectively. Buried plates218aand218bmay be adjacent to a lower portion of the first trench210and second trench212, respectively. In this embodiment, the buried plates218aand218bmay serve as bottom electrodes of one exemplary embodiment of trench capacitors.

Next, capacitor dielectric layers214aand214bare conformably and respectively formed on the inner walls of the first trench210and second trench212by methods such as chemical vapor deposition (CVD) or atomic layer CVD (ALD). Capacitor dielectric layers214aand214bmay comprise commonly used dielectrics, for example, oxide, nitride, oxynitride, oxycarbide or combinations thereof. Also, capacitor dielectric layers214aand214bmay comprise dielectric materials with dielectric constant (k) larger than 3.9, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiOXNY) or combinations thereof.

Next, an electrode layer216is blanketly formed on the second liner layer208, filling the first trench210and second trench212. The electrode layer216, for example, polysilicon electrode layer216, may be formed by a chemical vapor deposition (CVD) process. The electrode layer216covers the capacitor dielectric layer214aon the device region202and the capacitor dielectric layer214bon the testkey region204. In addition, the electrode layer216not only comprises polycrystalline silicon (poly-Si), but also comprises amorphous silicon (α-Si).

Next, as shown inFIG. 3b, a recess240ais formed in a first trench capacitor220aof the first trench210in device region202while a recess240bis formed in a second trench220bcapacitor of the second trench212in testkey region204. A planarization process such as chemical mechanical polish (CMP) and/or an etching back process, may be used to remove a portion of the electrode layer216on the second liner layer208, a portion of the electrode layer216and capacitor dielectric layer214ain the first trench210on the device region202, a portion of the electrode layer216and capacitor dielectric layer214bin the second trench212on the testkey region204. The electrode layer216aand capacitor dielectric layer214cthat remain, form a recess in the first trench210while the electrode layer216band capacitor dielectric layer214dthat remain, form a recess in the second trench212. The electrode layers216aand216bthat remain serve as top electrodes of one exemplary embodiment of trench capacitors. Thus, a first trench capacitor220ais formed recessed in the first trench210while a second capacitor220bis formed recessed in the second trench212.

Referring toFIG. 3c, an underlying insulating layer222and an overlying conductive layer224are conformably formed on the first trench210and second trench212, respectively. Insulating layer222may be conformably formed by methods such as chemical vapor deposition (CVD) or atomic layer CVD (ALD). Insulating layer222may comprise common used dielectrics, for example, oxide, nitride, oxynitride, oxycarbide or combinations thereof. Conductive layer224may comprise polycrystalline silicon (poly-Si) or amorphous silicon (α-Si) formed by chemical vapor deposition (CVD) process. In this embodiment, conductive layer224may have a first etching selectivity.

Next, as shown inFIG. 3dandFIG. 3e, a first implantation process226is performed along a first direction242to dope impurities into a first portion260aof the conductive layer224in the first trench210and second trench212, respectively. First direction242and a surface of the semiconductor substrate200may have an angle between 30° to 60°. A conductive layer224awith doped impurities and a conductive layer224bwithout doped impurities are formed in the device region202and testkey region204by a first implantation process226, wherein the doped impurities may comprise boron (B), boron fluoride (BF2), phosphorus (P) or arsenic (As).

Referring toFIG. 3f, a patterned masking layer230covers device region202, exposing the second trench212in the testkey region204. Patterned masking layer230may comprise a photoresist layer or a hard masking layer according to fabrication processes requirements. Next, as shown inFIG. 3gandFIG. 3h, a second implantation process232is performed to dope impurities into a second portion260bof the conductive layer224in the second trench212. In this embodiment, a second implantation process232may comprise three implantation steps. First, a first step is performed along a second direction244to dope impurities into a third portion260cof the conductive layer224in the second trench212, wherein second direction244is substantially perpendicular to the first direction242. Next, a second step is performed along a third direction246to dope impurities into a fourth portion260dof the conductive layer224in the second trench212, wherein the third direction246is substantially perpendicular to the second direction244. Finally, a third step is performed along a fourth direction248to dope impurities into a fifth portion260eof the conductive layer224in the second trench212, wherein the fourth direction248is substantially perpendicular to the third direction246. The second implantation process232is performed to form a conductive layer224cwith doped impurities into the testkey region204, wherein the doped impurities may comprise boron (B), boron fluoride (BF2), phosphorus (P) or arsenic (As). In this embodiment, the first implantation process226and second implantation process232make doped impurities disperse uniformly in the conductive layer224in the second trench212. Conductive layer224with doped impurities in the second trench212has a second etching selectivity higher than the first etching selectivity. The patterned masking layer230is then removed.

Referring toFIG. 3i, a wet etching process is performed in the first trench210to remove a portion of the conductive layer224bwithout doped impurities, a portion of the insulating layer222underlying the removed conductive layer224band a portion of the first trench capacitor220aunderlying the removed insulating layer222. A recess234is thus formed in the first trench capacitor220a. In this embodiment, an etchant used for the wet etching process may comprise ammonium hydroxide (NH4OH) dissolving in hydrogen oxide (H2O). The etchant comprising NH4OH and H2O preferably has a volume ratio between 1:100 to 1:200. Ammonium hydroxide (NH4OH) of the etchant preferably comprises industrial NH4OH with a weight concentration between 35 wt % to 45 wt %, preferably 40 wt %. In this embodiment, the conductive layer224ain the first trench210with doped impurities has a second etching selectivity, and the conductive layer224bin the first trench210without doped impurities has the first etching selectivity lower than the second etching selectivity as shown inFIG. 3g. Therefore, the etching selectivity of the conductive layer224ain first trench210is higher than that of the conductive layer224bin first trench210. Meanwhile, as shown onFIG. 3i, both conductive layers224aand224con the testkey area204with doped impurities have the second etching selectivity. Therefore, the conductive layer224in the second trench212has etching selectivity higher than that of the conductive layer224bin the first trench210. After performing the wet etching process, a recess234is formed in the first trench capacitor220aon the device region202. Meanwhile, the conductive layer224in the second trench212on the testkey area204is not removed by the wet etching process, having a symmetric profile to a central axis270. Thus, the formation of an exemplary embodiment of the semiconductor device250ais complete.

An exemplary embodiment of the semiconductor device250auses an additional implantation process (second implantation process232) to make the conductive layer224in the second trench212on the testkey region204to have doped impurities. Therefore, the conductive layer224in the second trench212may have an etching selectivity higher than that of the conductive layer224bin the first trench210. After performing the wet etching process, the conductive layer224on the testkey region204, which is a region for forming alignment marks or overlay marks, is not removed by the wet etching process, thus has a symmetric profile to a central axis270. Therefore, misalignment or overlay error problems due to asymmetric profiles of alignment marks or overlay marks on the testkey region can be avoided using the photolithography processes of the invention. Thus, fabricating yield and device reliability of a semiconductor device can be improved.

FIGS. 4aand4care cross sections showing another exemplary embodiment of a process of fabricating a semiconductor device of the invention. The same elements as shown inFIGS. 3ato3care not repeated again for brevity.

Referring toFIG. 4aandFIG. 4b, a patterned masking layer236is formed for covering the testkey region204. Patterned masking layer236may comprise a photoresist layer or a hard masking layer according to fabrication processes requirements. Next, a first implantation process226is performed along a first direction242to dope impurities into a first portion260aof the conductive layer224in the first trench210. First direction242and a surface of the semiconductor substrate200may have an angle between 30° to 60°. A conductive layer224awith doped impurities and a conductive layer224bwithout doped impurities are formed on the device region202by a first implantation process226, wherein the doped impurities may comprise boron (B), boron fluoride (BF2), phosphorus (P) or arsenic (As). Patterned masking layer236covering the second trench212is used to block impurities from the first implantation process226doping of the conductive layer224in the second trench212. Therefore, the conductive layer224in the second trench212may retain a first etching selectivity. Next, the patterned masking layer236is then removed.

Referring toFIG. 4c, a wet etching process is performed to remove a portion of the conductive layer224bwithout doped impurities, underlying the insulating layer222and underlying the first trench capacitor220a, which are in the first trench210. The aforementioned wet etching process is also removed the entire conductive layer224, the entire underlying insulating layer222and a portion of the underlying second trench capacitor220b, which are in the second trench210. A recess238aand a recess238bare thus formed in the first trench capacitor220aand second trench capacitor220b, respectively. In this embodiment, an etchant used for the wet etching process may comprise ammonium hydroxide (NH4OH) dissolving in hydrogen oxide (H2O). The etchant comprising NH4OH and H2O preferably has a volume ratio between 1:100 to 1:200. Ammonium hydroxide (NH4OH) of the etchant preferably comprises industrial NH4OH with a weight concentration between 35 wt % to 45 wt %, preferably 40 wt %. In this embodiment, the conductive layer224ain the first trench210with doped impurities has the second etching selectivity, and the conductive layer224bin the first trench210without doped impurities has the first etching selectivity lower than the second etching selectivity as shown inFIG. 4a. Therefore, the etching selectivity of the conductive layer224ain the first trench210is higher than that of the conductive layer224bin the first trench210. Meanwhile, as shown onFIG. 4a, the conductive layer224in the second trench212without doped impurities maintains a first etching selectivity. As shown inFIG. 4b, after performing the wet etching process, recess238ais formed in the first trench capacitor220aon the device region202, while recess238bis formed in the second trench capacitor220b. Meanwhile, the second trench capacitor220bon the testkey region204may have a symmetric profile to a central axis270. Thus, the formation of another exemplary embodiment of the semiconductor device250bis complete.

Another exemplary embodiment of semiconductor device250buses a patterned masking layer236covering a second trench212on the testkey region204to block doped impurities of the first implantation process226doping into the conductive layer224in the second trench212. Therefore, the conductive layer224in the second trench212may retain a first etching selectivity. After performing the wet etching process, the entire conductive layer224, entire underlying insulating layer222and a portion of the underlying second trench capacitor220b, which are in the second trench210, are removed. A recess238bformed in the second trench capacitor220bon the testkey region204, which is a region for forming alignment marks or overlay marks, has a symmetric profile to a central axis270. Misalignment or overlay error problems due to asymmetric profiles of alignment marks or overlay marks on the testkey region can be avoided using the photolithography processes of the invention. Therefore, fabricating yield and device reliability of a semiconductor device can be improved.