MULTI-CHANNEL FIELD EFFECT TRANSISTORS WITH ENHANCED MULTI-LAYERED SOURCE/DRAIN REGIONS

A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.

REFERENCE TO PRIORITY APPLICATION

This application claims priority to Korean Patent Application No. 10-2021-0152050, filed Nov. 8, 2021, the disclosure of which is hereby incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to integrated circuit devices and, more particularly, to field effect transistors.

BACKGROUND

As demand for high performance, high speed, and/or multifunctionality in a semiconductor devices has increased, the integration density of these semiconductor devices has also increased. When manufacturing a semiconductor device having a fine pattern corresponding to the trend for higher integration density, it may be necessary to implement patterns having a fine width or a fine spacing. Moreover, to overcome the relative limitations in the operational properties of such devices, which are caused by a reduction of a size of a planar metal oxide semiconductor FET (MOSFET), for example, attempts have been made to develop semiconductor devices including a FinFET having a three-dimensional (3D) channel structure.

SUMMARY

Example embodiments of the present invention provide a semiconductor device having improved electrical properties.

According to an example embodiment of the present invention, a semiconductor device is provided, which includes an active region extending in a first direction on a substrate, and a plurality of channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, on the active region. A gate structure is provided on the substrate. This gate structure intersects the active region and the plurality of channel layers, surrounds the plurality of channel layers, and extends in a second direction. A source/drain region is provided, which extends on the active region on at least one side of the gate structure and is in contact with the plurality of channel layers. The source/drain region includes a first epitaxial layer, which extends on the active region and contacts the plurality of channel layers, and has a first upper surface that is configured to be recessed. The source/drain region also includes a second epitaxial layer, which is in contact with a first portion of the first upper surface of the first epitaxial layer, and has a second upper surface configured to be recessed. The source/drain region also includes a third epitaxial layer, which is in contact with a second portion of the first upper surface of the first epitaxial layer and the second upper surface of the second epitaxial layer.

According to another embodiment of the present invention, a semiconductor device includes: (i) an active region extending in a first direction on a substrate, (ii) a plurality of channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, on the active region, (iii) a gate structure intersecting the active region and the plurality of channel layers, surrounding the plurality of channel layers, and extending in a second direction, on the substrate, and (iv) a source/drain region extending on the active region on at least one side of the gate structure and in contact with the plurality of channel layers. According to some of these embodiments, the source/drain region includes: a first epitaxial layer extending on the active region and in contact with the plurality of channel layers, a second epitaxial layer extending on the first epitaxial layer, a third epitaxial layer extending on the second epitaxial layer, and a fourth epitaxial layer extending on the third epitaxial layer. The third epitaxial layer may include a first surface in contact with the fourth epitaxial layer, a second surface in contact with the first epitaxial layer, and a third surface in contact with the second epitaxial layer.

According to another embodiment of the present disclosure, a semiconductor device is provided, which includes an active region extending in a first direction on a substrate, a gate structure intersecting the active region and extending in a second direction, on the substrate, and a source/drain region. The source/drain region extends on the active region and on at least one side of the gate structure. The source/drain region includes a lower epitaxial layer having an upper surface configured to be recessed, and an upper epitaxial layer extending on the lower epitaxial layer and having a lower surface with a curved shape (curved toward the upper surface of the lower epitaxial layer). The source/drain region also includes an intermediate epitaxial layer extending between the lower epitaxial layer and the upper epitaxial layer. Advantageously, an uppermost end of the intermediate epitaxial layer extends on a level lower than a level of an uppermost end of the upper epitaxial layer and an uppermost end of the lower epitaxial layer.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

FIG.1is a plan diagram illustrating a semiconductor device according to an example embodiment.FIG.2is a cross-sectional diagram illustrating a semiconductor device taken along lines I-I′, II-II′ and III-III′ according to an example embodiment.FIG.3is an enlarged diagram illustrating a portion of a semiconductor device, illustrating region A inFIG.2, according to an example embodiment.FIGS.1to3illustrate only main components of the semiconductor device.

Referring toFIGS.1to3, a semiconductor device100may include a substrate101(e.g., semiconductor substrate), an active region105on the substrate101, and a channel structure140including a plurality of channel layers141,142, and143vertically spaced apart from each other on the active region105, a source/drain region150in contact with the plurality of channel layers141,142, and143, a gate structure160intersecting the active region105, and a contact plug180connected to the source/drain region150. The semiconductor device100may further include device isolation layers110and an interlayer insulating layer190. The gate structure160may include a spacer layer161, a gate dielectric layer162, a gate electrode layer163, and a gate capping layer164.

In the semiconductor device100, the active region105may have a fin structure, and the gate electrode layer163may extend: (i) between the active region105and the channel structure140, (ii) between the plurality of channel layers141,142, and143of the channel structures140, and (iii) on the channel structure140, as shown. Accordingly, the semiconductor device100may be configured as a gate-all-around type field effect transistor, such as a multi-bridge channel FET (MBCFET™), which is formed by the channel structure140, the source/drain regions150, and the gate structure160. The transistor may operate as a PMOS transistor in some embodiments.

The substrate101may have an upper surface extending in the X-direction and in the Y-direction, which is orthogonal to the X-direction. The substrate101may include a semiconductor material, such as, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. In some embodiments, a group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate101may also be provided as a bulk wafer (formed from a boule), an epitaxial layer, a silicon-on-insulator (SOI) layer, and a semiconductor-on-insulator (SeOI) layer.

The device isolation layer110may define an active region105on the substrate101. The device isolation layer110may be formed by, for example, a shallow trench isolation (STI) process. In example embodiments, the device isolation layer110may further include a region having a step difference toward a lower portion of the substrate101and extending more deeply. The device isolation layer110may partially expose an upper portion of the active region105. In example embodiments, the device isolation layer110may have a wavy upper surface having a higher level toward the active region105. The device isolation layer110may be formed of an insulating material. The device isolation layer110may be, for example, oxide, nitride, or a combination thereof.

The active region105may be defined by the device isolation layer110in the substrate101and may be disposed to extend in the first direction X. The active region105may have a structure protruding from the substrate101. An upper end of the active region105may be disposed to protrude by a predetermined height from the upper surface of the device isolation layer110. The active region105may be formed as a portion of the substrate101, or may include an epitaxial layer grown from the substrate101. However, the active region105on the substrate101may be partially recessed on both sides of the gate structure160, and the source/drain regions150may be disposed on the recessed active region105. The active region105may include impurities or doped regions including impurities.

The channel structure140may include first to third channel layers141,142, and143, two or more channel layers spaced apart from each other in a direction perpendicular to the upper surface of the active region105(e.g., a Z-direction), on the active region105. The first to third channel layers141,142, and143may be connected to the source/drain region150and may be spaced apart from the upper surface of the active region105. The first to third channel layers141,142, and143may have the same or similar width as that of the active region105in the Y-direction, and may have the same or similar width as that of the gate structure160in the X-direction. However, in example embodiments, the first to third channel layers141,142, and143may have a reduced width such that side surfaces may be disposed below the gate structure160in the X-direction.

The first to third channel layers141,142, and143may be formed of a semiconductor material, and may include, for example, silicon (Si). The first to third channel layers141,142, and143may be formed of, for example, the same material as a material of the substrate101. The number of the channel layers141,142, and143included in the channel structure140and the shape thereof may be varied in example embodiments. For example, in example embodiments, the channel structure140may further include a channel layer disposed on the upper surface of the active region105.

The source/drain region150may be disposed on at least one side of the gate structure160on the active region105. The source/drain regions150may be disposed in a recess region recessed from the upper surface of the active region105. A degree of curvature of the shape of the recess region of the active region105may be varied in example embodiments. Accordingly, the shape of the source/drain region150formed in the recess region of the active region105may also be varied.

In addition, the source/drain region150may include a plurality of epitaxial layers, such as first to fourth epitaxial layers151,152,153, and154. The first epitaxial layer151may be disposed on the active region105and may extend to be in contact with the plurality of channel layers141,142, and143. The first epitaxial layer151may be in contact with a lower portion1606of the gate structure160disposed below each of the channel layers141,142, and143.

The first epitaxial layer151may include a protrusion protruding toward the gate structure160on the same level as a level of the lower portion1606of the gate structure160. In example embodiments, a side surface of the lower portion160B of the gate structure160in the first direction X may be recessed by a predetermined depth and may have an inwardly curved shape. The protrusion of the first epitaxial layer151may be disposed in a recess region of the lower portion160B of the gate structure160. The width of the first epitaxial layer151in the first direction X on the level of the gate structure160may be greater than a width of the first epitaxial layer151in the first direction X on the level of the first to third channel layers141,142, and143.

A surface of the first epitaxial layer151is in contact with the plurality of channel layers141,142, and143, and the lower portion160B of the gate structure160may have a wavy (i.e., uneven) shape, however, other embodiments and shapes are also possible. The shape of the first epitaxial layer151may be varied according to the shape of the channel structure140, and the shape of the gate structure160. For example, when the semiconductor device further includes an outer spacer (not shown) on an external side of the gate electrode layer163of the lower portion160B, an external side surface of the first epitaxial layer151may have a slightly curved shape.

The first epitaxial layer151may have an upper surface151T configured to be recessed. The first epitaxial layer151may have an almost U-shape. The upper surface151T of the first epitaxial layer151may include a first portion T1in contact with the second epitaxial layer152, a second portion T2in contact with the third epitaxial layer153, and a third portion T3in contact with the fourth epitaxial layer154.

The first epitaxial layer151may include silicon germanium (SiGe) doped with a group3element, and may have P-type conductivity. For example, the first epitaxial layer151may include one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl) as a doping element. A concentration of germanium (Ge) in the first epitaxial layer151may be lower than that of the sacrificial layer120(inFIGS.9A to9J) before the gate structure160is substituted. The first epitaxial layer151may have a lower etch selectivity than that of the sacrificial layer120under specific etching conditions during a manufacturing process. Due to a difference in etch selectivity as above, the sacrificial layer120may be selectively removed in the process inFIG.9K, and the source/drain region150surrounded by the first epitaxial layer151may remain. The concentration of Ge of the first epitaxial layer151may be, for example, about 5 at % to about 8 at %, where “at %” corresponds to atomic percent.

The second epitaxial layer152may be disposed on the first epitaxial layer151. A lower surface152B of the second epitaxial layer152may be disposed to be in contact with the first portion T1of the upper surface151T of the first epitaxial layer151. The second epitaxial layer152may have an upper surface152T configured to be recessed. The upper surface152T of the second epitaxial layer152may have an almost rounded U-shaped shape, but an example embodiment thereof is not limited to this specific shape. In example embodiments, the upper surface152T of the second epitaxial layer152may have an angular shape.

An uppermost end of the second epitaxial layer152may be disposed on a level lower than a level of an uppermost end of the first epitaxial layer151. In an example embodiment, the uppermost end of the second epitaxial layer152may be disposed on a level between a lower surface of the third channel layer143, which may be an uppermost channel layer, and an upper surface of the second channel layer142, which may be a second uppermost channel layer adjacent to the uppermost channel layer. The level of the uppermost end of the second epitaxial layer152is not limited thereto, and may be varied depending on a reflow condition in a manufacturing process and the concentration of germanium (Ge) of the second epitaxial layer152.

The first width W1of the second epitaxial layer152in the horizontal direction X may be less than the second width W2of the second epitaxial layer152in the vertical direction Z, in some embodiments. Advantageously, because the first width W1of the second epitaxial layer152has a shape smaller than that of the second width W2, an aspect ratio of the third epitaxial layer153may be reduced.

The third epitaxial layer153may be disposed on the second epitaxial layer152and may fill the source/drain region150. The lower surface1536of the third epitaxial layer153may be disposed to be in contact with the upper surface152T of the second epitaxial layer152. The lower surface1536of the third epitaxial layer153may be disposed on a level higher than a level of the lower surface of the lowermost channel layer141. The lower surface1536of the third epitaxial layer153may be disposed on a level lower than a level of the lower surface of the uppermost channel layer143.

The upper surface153T of the third epitaxial layer153may be disposed on a level lower than a level of the upper surface of the uppermost channel layer143. At least a portion of the upper surface153T of the third epitaxial layer153may be disposed on a level between the upper surface and the lower surface of the uppermost channel layer143.

The side surface153S of the third epitaxial layer153may be disposed to be in contact with the second portion T2of the upper surface151T of the first epitaxial layer151. The side surface1536of the third epitaxial layer153may be disposed on a level lower than a level of the lower surface of the uppermost channel layer143.

A point P in which the first to third epitaxial layers151,152, and153meet may be disposed between a lower surface of the uppermost channel layer143and an upper surface of the second uppermost channel layer142adjacent to the uppermost channel layer143in the vertical direction Z. The uppermost end of the second epitaxial layer152may be disposed on a level lower than a level of the uppermost end of the first epitaxial layer151and the uppermost end of the third epitaxial layer153.

As the third epitaxial layer153has the shape as described above, the third epitaxial layer153may have an aspect ratio smaller than an aspect ratio of the entire source/drain region150. An aspect ratio of the third epitaxial layer153may be about 1.0 to about 1.5.

The lower surface1536of the third epitaxial layer153may have a shape the same as or similar to that of the upper surface152T of the second epitaxial layer152in contact to the lower surface1536. The lower surface1536of the third epitaxial layer153may have an almost U-shaped rounded shape, but an example embodiment thereof is not limited thereto. In example embodiments, the lower surface153B of the third epitaxial layer153may have a chamfered shape.

The third epitaxial layer153may have a width in the first direction X, which may increase in a direction of being away from upper surface of the active region105. In example embodiments, the width of the third epitaxial layer153in the first direction X may gradually increase in the direction of being away from the upper surface of the active region105.

The fourth epitaxial layer154may be disposed on the third epitaxial layer153. The fourth epitaxial layer154is disposed to be in contact with the third portion T3of the upper surface151T of the first epitaxial layer151and the upper surface153T of the third epitaxial layer153. At least a portion of the fourth epitaxial layer154may be substantially coplanar with an upper surface of the uppermost channel layer143.

The first to third epitaxial layers151,152, and153may include silicon germanium (SiGe) or silicon (Si) doped with a group3element. In example embodiments, the first to third epitaxial layers151,152, and153may have P-type conductivity. For example, the first to third epitaxial layers151,152, and153may include silicon germanium (SiGe), and may include one of boron (B), aluminum (Al), gallium (Ga), indium (In) and thallium (Tl) as doping elements.

The first to third epitaxial layers151,152, and153may have germanium (Ge) in different concentrations. A concentration of Ge may increase in the order of the first epitaxial layer151, the second epitaxial layer152, and the third epitaxial layer153. For example, a concentration of Ge of the first epitaxial layer151may be about 5 at % to about 8 at %, a concentration of Ge of the second epitaxial layer152may be about 40 at % to about 45 at %, and a concentration of Ge of the third epitaxial layer152may be about 50 at % and about 55 at %.

The fourth epitaxial layer154may include silicon (Si) doped with a group3element. The fourth epitaxial layer154may include relatively smaller amounts of Ge, if any. The fourth epitaxial layer154may be a protective layer capping the first to third epitaxial layers151,152, and153.

The semiconductor device100in an example embodiment may include the source/drain region150having the above-described structure such that dislocation in the source/drain region150may be prevented.

To improve integration density of a semiconductor device, a contacted poly pitch (CPP) between gate structures adjacent to each other may decrease, and an aspect ratio of the source/drain region150may increase. However, as the aspect ratio of the source/drain region150increases, dislocation in the source/drain region150may increase.

One of the causes of dislocations in the source/drain region150may be due to crystalline growth properties of silicon-germanium (SiGe). Silicon-germanium (SiGe) included in the first to third epitaxial layers151,152, and153may have different crystalline growth rates in crystalline directions. For example, silicon-germanium (SiGe) may have a slow growth rate in the [111] direction perpendicular to the (111) plane, which has a relatively low surface energy. That is, the first to third epitaxial layers151,152, and153may have a slow growth rate in the [111] direction as compared to the horizontal direction (e.g., [110] direction) and the vertical direction (e.g., [100] direction). Accordingly, a dislocation in which an interatomic bond is broken may occur in a boundary between the (110) plane grown along the [110] direction and the (111) plane grown in the [111] direction. As the cavity of the source/drain region150in the horizontal direction X decreases due to a decrease in CPP of the semiconductor device, the possibility of the above-described dislocation may increase. In particular, a dislocation may be generated in the third epitaxial layer153occupying the largest volume in the source/drain region150.

A dislocation in the source/drain region150may degrade electrical performance of the semiconductor device. In particular, when the semiconductor device100is a PMOS, the third epitaxial layer153including a high concentration of Ge may work as a stressor applying a compressive force to the channel layers141,142, and143, and charge mobility in the channel layers141,142, and143may increase. However, when a dislocation is generated in the third epitaxial layer153, strain relaxation may occur in a region in which an interatomic bond is broken. Accordingly, since the third epitaxial layer153may not apply sufficient compressive stress to the channel layers141,142, and143, performance of the semiconductor device may be deteriorated due to the increase in resistance of the channel layers141,142, and143.

Since the source/drain region150in an example embodiment has the above-described structural properties, the third epitaxial layer153may have a low aspect ratio and dislocation may be prevented. Also, the second epitaxial layer152having a second width W2greater than the first width W1may be disposed below the third epitaxial layer153, such that the third epitaxial layer153may have a relatively low aspect ratio. Accordingly, defects in the source/drain region150may be prevented without limitation in the device CPP, thereby improving performance of the semiconductor device.

The gate structure160may intersect the active region105and the channel structures140on the active region105and the channel structures140and may extend in one direction, that is, for example, the Y-direction. Channel regions of transistors may be formed in the active region105and the channel structures140intersecting the gate structure160. The gate structure160may include a gate electrode layer163, a gate dielectric layer162between the gate electrode layer163and the plurality of channel layers141,142, and143, and spacer layers161on side surfaces of the gate electrode layer163, and a gate capping layer164on the upper surface of the gate electrode layer163.

The gate dielectric layer162may be disposed between the active region105and the gate electrode layer163and between the channel structure140and the gate electrode layer163, and may be disposed to cover at least a portion of surfaces of the gate electrode layer163. For example, the gate dielectric layer162may be disposed to surround all surfaces other than an uppermost surface of the gate electrode layer163. The gate dielectric layer162may extend to a region between the gate electrode layer163and the spacer layers161, but an example embodiment thereof is not limited thereto. The gate dielectric layer162may include oxide, nitride, or a high-k material. The high-k material may refer to a dielectric material having a dielectric constant higher than that of a silicon oxide layer (SiO2). The high dielectric constant material may be, for example, one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (Pr2O3).

The gate electrode layer163may be disposed to fill a region between the plurality of channel layers141,142, and143on the active region105and may extend to an upper portion of the channel structure140. The gate electrode layer163may be spaced apart from the plurality of channel layers141,142, and143by the gate dielectric layer162. The gate electrode layer163may include a conductive material. For example, at least one of a metal nitride (e.g., at least one of a titanium nitride film (TiN), a tantalum nitride film (TaN), and a tungsten nitride film (WN)), a metal material (e.g., aluminum (Al), tungsten (W), and molybdenum (Mo)), and silicon (e.g., doped polysilicon).

The gate electrode layer163may include two or more layers. The spacer layers161may be disposed on both sides of the gate electrode layer163. The gate spacer layers161may insulate the source/drain region150from the gate electrode layer163. The spacer layers161may have a multilayer structure in example embodiments. The spacer layers161may include at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

The gate capping layer164may be disposed on the gate electrode layer163, and a lower surface thereof may be surrounded by the gate electrode layer163and the spacer layers161. The interlayer insulating layer190may be disposed to cover the source/drain region150, the gate structure160, and the device isolation layer110. The interlayer insulating layer190may include, for example, at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

The contact plug180may be connected to the source/drain region150through the interlayer insulating layer190, and may apply an electrical signal to the source/drain region150. The contact plug180may be disposed on the source/drain region150, and may be disposed to have an elongated length in the Y-direction than the source/drain region150in example embodiments. The contact plug180may have an inclined side surface in which a lower width may be narrower than an upper width according to an aspect ratio, but an example embodiment thereof is not limited thereto. The contact plug180may be disposed to be recessed into the source/drain region150by a predetermined depth. In an example embodiment, the contact plug180may penetrate the fourth epitaxial layer154and may penetrate at least a portion of the third epitaxial layer153. The contact plug180may include, for example, at least one of metal nitride (e.g., at least one of a titanium nitride film (TiN), a tantalum nitride film (TaN), and a tungsten nitride film (WN)) and a metal material (e.g., at least one of aluminum (Al), tungsten (W) and molybdenum (Mo)).

FIG.4Ais an enlarged diagram illustrating a portion of a semiconductor device according to an example embodiment.FIG.4Aillustrates the enlarged diagram inFIG.3without the contact plug180.FIGS.4B to4Eare graphs illustrating distribution of concentration of germanium (Ge) in a source/drain region in a semiconductor device according to an example embodiment.FIGS.4B to4Eillustrate concentration profiles of germanium (Ge) in the source/drain region150taken along lines A-A′, B-B′, C-C′ and D-D′ inFIG.4A, respectively.

FIG.4Billustrates a concentration profile of germanium (Ge) in the source/drain region150along line A-A′ inFIG.4A. InFIG.4B, a first section La1may be a region corresponding to the first epitaxial layer151, and a second section La2may be a region corresponding to the second epitaxial layer152. The first epitaxial layer151may include Ge in a first concentration C1, and the second epitaxial layer152may include Ge in a second concentration C2higher than the first concentration C1. As illustrated inFIG.4B, the source/drain region150may not include layers other than the first epitaxial layer151and the second epitaxial layer152on the level A-A′ inFIG.4A. The third epitaxial layer153may be disposed on a level higher than a level of the lower surface of the first channel layer141, which is a lowermost channel layer.

FIG.4Cillustrates a concentration profile of germanium (Ge) in the source/drain region150taken along line B-B′ inFIG.4A. InFIG.4C, a first section Lb1may be a region corresponding to the first epitaxial layer151, a second section Lb2may be a region corresponding to the second epitaxial layer152, and a third section Lb3may be a region corresponding to the third epitaxial layer153. The first epitaxial layer151may include Ge in a first concentration C1, the second epitaxial layer152may include Ge in a second concentration C2, and the third epitaxial layer153may include Ge in a third concentration C3. The concentration of Ge may increase in the order of the first concentration C1, the second concentration C2, and the third concentration C3.

FIG.4Dillustrates a concentration profile of germanium (Ge) in the source/drain region150along line C-C′ inFIG.4A. InFIG.4D, a first section Lc1may be a region corresponding to the first epitaxial layer151, and a third section Lc3may be a section corresponding to the third epitaxial layer153. The first epitaxial layer151may include Ge in a first concentration C1, and the third epitaxial layer153may include Ge in a third concentration C3higher than the first concentration C1. As illustrated inFIG.4D, on the level C-C′ inFIG.4A, the source/drain region150may not include layers other than the first epitaxial layer151and the third epitaxial layer153. The second epitaxial layer152may be disposed on a level lower than a level of a lower surface of the uppermost channel layer143.

The length of the third section Lc3inFIG.4Dmay be greater than the length of the third section Lb3inFIG.4C. That is, the third epitaxial layer153may have a shape having a width increasing in a direction of being away from the upper surface of the active region105.

Meanwhile, an example embodiment in which the source/drain region150may be symmetrical with respect to the center line D-D′ in the first direction X is illustrated inFIGS.4A to4D, but an example embodiment thereof is not limited thereto. In example embodiments, the level of the uppermost end of the second epitaxial layer152and the width W1(inFIG.3) of the second epitaxial layer152in the first direction X may be different from each other on both sides of the source/drain region150with reference to center line D-D′.

FIG.4Eillustrates a concentration profile of germanium (Ge) in the source/drain region150taken along line D-D′ inFIG.4A. Line D-D′ inFIG.4Amay be a central line of the source/drain region150in the first direction X. InFIG.4E, a first section Ld1may be a region corresponding to the first epitaxial layer151, a second section Ld2may be a region corresponding to the second epitaxial layer152, a third section Ld3may be a region corresponding to the third epitaxial layer153, and a fourth section Ld4may be a region corresponding to the fourth epitaxial layer154. The first epitaxial layer151may include Ge in a first concentration C1, the second epitaxial layer152may include Ge in a second concentration C2higher than the first concentration C1, and the third epitaxial layer153may include Ge in a third concentration C3higher than the second concentration C2, and the fourth epitaxial layer154may not substantially include Ge. The region before the first section Ld1may correspond to the substrate101, and the substrate101may not substantially include Ge.

The length of the second section Ld2inFIG.4Emay be greater than the length of the second section Lb2inFIG.4C. That is, the width W1(inFIG.3) of the second epitaxial layer152in the first direction X may be smaller than the width W2(inFIG.3) of the second epitaxial layer152in the vertical direction Z.

As illustrated inFIGS.4B to4E, the first to fourth epitaxial layers151,152,153, and154may have different material compositions (e.g., the concentration of Ge), such that the first to fourth epitaxial layers151,152,153, and154may be distinct from each other through the Transmission Electron Microscopy Energy-Dispersive X-ray spectroscopy. In example embodiments, changes in the concentration of Ge in the boundaries between the first to fourth sections may be more abrupt or more gentle.

FIGS.5to7are cross-sectional diagrams illustrating semiconductor devices according to example embodiments. In the example embodiment inFIGS.5to7, in the case of having the same reference numerals as those inFIGS.1to3but having a different denotation, which may be for an example embodiment different from those ofFIGS.1to3, and the configurations of the same components may be the same or similar. Differently from the semiconductor device100inFIGS.1to3, the shape of the second epitaxial layer152amay be different from that of the semiconductor device100ainFIG.5.

Referring toFIG.5, an uppermost end of the second epitaxial layer152amay be disposed between the upper surface of the first channel layer141, which may be a lowermost channel layer, and a lower surface of the second channel layers142, which may be a second lowermost channel layer adjacent to the first channel layer141. The second epitaxial layer152amay be disposed on a level lower than a level of the lower surface of the second channel layer142, which is a second lowermost channel layer. A vertical height between the uppermost and lowermost ends of the second epitaxial layer152ainFIG.5may be smaller than a vertical height between the uppermost and lowermost ends of the second epitaxial layer152inFIG.2.

The shape and the position of the second epitaxial layer152amay be determined depending on a reflow condition in a process of manufacturing the source/drain region150. For example, when the temperature of the reflow process after the second epitaxial layer152ais formed is relatively high, the degree of reflow of the second epitaxial layer152amay increase, and the uppermost end of the second epitaxial layer152amay be disposed on a lower level. In the semiconductor device100binFIG.6, the shape of the second epitaxial layer152bmay be different from that of the semiconductor device100inFIGS.1to3.

Referring toFIG.6, the lowermost end of the second epitaxial layer152bmay be disposed on a level lower than a level of the uppermost surface of the active region105b. A maximum width of the second epitaxial layer152billustrated inFIG.6in the vertical direction Z may be greater than a maximum width of the second epitaxial layer152illustrated inFIG.2in the vertical direction Z.

The source/drain region150billustrated inFIG.6may have a relatively large aspect ratio as compared to that of the source/drain region150illustrated inFIG.2. Even in this case, the aspect ratio of the third epitaxial layer153bmay be controlled to be decrease by increasing the width of the second epitaxial layer152bin the vertical direction Z. Accordingly, dislocations in the third epitaxial layer153bmay be prevented, and performance of the semiconductor device100bmay improve.

In the semiconductor device100cinFIG.7, the structure of the first epitaxial layer may be different from that of the semiconductor device100inFIGS.1to3. Referring toFIG.7, the first epitaxial layer may include a first layer151c_1and a second layer151c_2. The first layer151c_1and the second layer151c_2may include germanium (Ge) of different concentrations. The first layer151c_1may include Ge in a lower concentration than that of the second layer151c_2. In an example embodiment, the first layer151c_1may include about 1 at % about 5 at % of Ge, and the second layer151c_2may include about 6 at % to about 10 at % of Ge. By controlling the concentration of the first layer151c_1disposed on an external side of the source/drain region150cto be low, a difference in etch selectivity with the sacrificial layer120in the process inFIG.9Kmay increase. Accordingly, the sacrificial layer120may be replaced with the gate structure160cwithout damaging the source/drain region150.

FIG.8is a cross-sectional diagram illustrating a semiconductor device, taken along lines I-I′, II-II′ and III-III′ inFIG.1, according to an example embodiment.FIG.8illustrates only main components of the semiconductor device. Referring toFIG.8, the semiconductor device100dmay include an active region105, an isolation layer110, a source/drain region150d, a gate structure160, a contact plug180, and an interlayer insulating layer190. The semiconductor device100dmay include a finFET device which may be a transistor having a fin structure of the active region105. The finFET device may include a transistor disposed around the active region105and the gate structure160intersecting each other. For example, the finFET device may be a PMOS transistor. Hereinafter, the same reference numerals as those inFIGS.1to3may indicate corresponding components, and overlapping descriptions will not be provided.

The source/drain regions150dmay be disposed on at least one side of the gate structure160in a recess region recessed from the upper surface of the active region105. The source/drain regions150dmay include a plurality of epitaxial layers, that is, for example, first to fourth epitaxial layers151d,152d,153d, and154d. The first to fourth epitaxial layers151d,152d,153d, and154dmay be disposed in order in the recess region. The second epitaxial layer152dmay be disposed between the first epitaxial layer151dand the third epitaxial layer153dand may lower an aspect ratio of the third epitaxial layer153d. Accordingly, dislocation in the source/drain region150dmay be prevented, such that performance of the semiconductor device100dmay improve.

FIGS.9A to9Kare cross-sectional diagrams illustrating processes of a method of manufacturing a semiconductor device in order according to an example embodiment.FIGS.9A to9Killustrate an example embodiment of a method of manufacturing the semiconductor device inFIGS.1to3, and illustrate cross-sectional surfaces corresponding toFIG.2. Referring toFIG.9A, sacrificial layers120and channel layers141,142, and143may be alternately stacked on a substrate101.

The sacrificial layers120may be replaced with the gate dielectric layer162and the gate electrode layer163as illustrated inFIG.2through a subsequent process. The sacrificial layers120may be formed of a material having etch selectivity with respect to the channel layers141,142, and143. The channel layers141,142, and143may include a material different from that of the sacrificial layers120. In an example embodiment, the channel layers141,142, and142may include silicon (Si), and the sacrificial layers120may include silicon germanium (SiGe).

The sacrificial layers120and the channel layers141,142, and143may be formed by performing an epitaxial growth process using the substrate101as a seed. Each of the sacrificial layers120and the channel layers141,142, and143may have a thickness in a range of about 1 Å to 100 nm. The number of layers of the channel layers141,142, and143alternately stacked with the sacrificial layer120may be varied in example embodiments.

Referring toFIG.9B, active structures may be formed by removing the stack structure of the sacrificial layers120and the channel layers141,142, and143and a portion of the substrate101. The active structure may include sacrificial layers120and channel layers141,142, and143alternately stacked with each other, and may further include an active region105protruding to an upper surface of the substrate101by removing a portion of the substrate101. The active structures may be formed in a linear shape extending in one direction, that is, for example, the X-direction, and may be spaced apart from each other in the Y-direction.

In the region from which a portion of the substrate101is removed, an insulating material may be filled and may be recessed to allow the active region105to protrude, thereby forming the device isolation layers110. An upper surface of the device isolation layers110may be formed to be lower than an upper surface of the active region105.

Referring toFIG.9C, sacrificial gate structures170and spacer layers161may be formed on the active structures. The sacrificial gate structures170may be sacrificial structures formed in a region in which the gate dielectric layer162and the gate electrode layer163are disposed on the channel structure140as illustrated inFIG.2through a subsequent process. The sacrificial gate structure170may include first and second sacrificial gate layers172and175and a mask pattern layer176stacked in order. The first and second sacrificial gate layers172and175may be patterned using a mask pattern layer176. The first and second sacrificial gate layers172and175may be an insulating layer and a conductive layer, respectively. For example, the first sacrificial gate layer172may include silicon oxide, and the second sacrificial gate layer175may include polysilicon. The mask pattern layer176may include silicon nitride. The sacrificial gate structures170may have a linear shape intersecting the active structures and extending in one direction. The sacrificial gate structures170may extend, for example, in a Y-direction and may be spaced apart from each other in the X-direction.

Spacer layers161may be formed on both sidewalls of the sacrificial gate structures170. The spacer layers161may be formed by forming a film having a uniform thickness along upper and side surfaces of the sacrificial gate structures170and the active structures and performing anisotropic etching. The spacer layers161may be formed of a low-k material, and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

Referring toFIG.9D, channel structures140may be formed by forming a recess region RC by removing the exposed sacrificial layers120and the channel layers141,142, and143between the sacrificial gate structures170. The exposed sacrificial layers120and the channel layers141,142, and143may be removed using the sacrificial gate structures170and the gate spacer layers161as masks. The remaining sacrificial layers120may be removed by a predetermined depth from the side surface in the X-direction, and may have inwardly curved side surfaces. The side surfaces of the remaining channel layers141,142, and143in the X-direction may be etched to have outwardly curved side surfaces. However, the shapes of the side surfaces of the sacrificial layers120and the channel layers141,142, and143are not limited to the illustrated example. The side surfaces of the sacrificial layers120and the channel layers141,142, and143may be formed to be coplanar with each other in a direction perpendicular to the upper surface of the substrate101.

Referring toFIG.9E, the first epitaxial layer151may be formed in the recess region RC. The first epitaxial layer151may extend to be in contact with the channel layers141,142, and143and the sacrificial layers120in the recess region RC. Accordingly, the upper surface of the first epitaxial layer151may be formed in a recessed shape, and may be formed to have an almost U-shape. A surface of the first epitaxial layer151in contact with the channel layers141,142, and143and the sacrificial layers120may have a wavy shape. The lowermost end of the upper surface151T of the first epitaxial layer151may be disposed on a level higher than a level of the lower surface of the lowermost sacrificial layer120.

The first epitaxial layer151may include silicon germanium (SiGe) doped with a group3element. According to an example embodiment, the first epitaxial layer151may include one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). The first epitaxial layer151may be formed by supplying silicon (Si) and germanium (Ge) source gases while supplying a carrier gas. In an example embodiment, the carrier gas may be hydrogen (H2) gas, the silicon (Si) source gas may be, for example, silane (SiH4), dichlorosilane (SiH2Cl2; DCS) or chlorosilane (SiH3Cl; MCS), the germanium (Ge) source gas may be, for example, germanium tetrahydride (GeH4). Second and third epitaxial layers may be formed in a similar manner.

The first epitaxial layer151may include germanium (Ge) having a lower concentration than that of the sacrificial layers120. In an example embodiment, the first epitaxial layer151may include Ge in a concentration of about 5 at % to about 8 at %. The first epitaxial layer151may include Ge in a lower concentration than that of the sacrificial layers120and may have a smaller etch selectivity than that of the sacrificial layers. Accordingly, in the subsequent process inFIG.9K, the sacrificial layers120may be selectively removed, and the source/drain regions150protected by the first epitaxial layer151may remain.

Referring toFIG.9F, a second preliminary epitaxial layer152P may be formed on the first epitaxial layer151. The second preliminary epitaxial layer152P may be conformally formed on the upper surface of the first epitaxial layer151to have a substantially uniform thickness. Accordingly, the upper surface of the second preliminary epitaxial layer152P may have a recessed shape similar to the upper surface of the first epitaxial layer151. The second preliminary epitaxial layer152P may be formed to cover the entire upper surface of the first epitaxial layer151, but an example embodiment thereof is not limited thereto. In example embodiments, the second preliminary epitaxial layer152P may be formed to cover only a portion of the upper surface of the first epitaxial layer151.

The second preliminary epitaxial layer152P may include silicon germanium (SiGe) doped with a group3element. According to an example embodiment, the first epitaxial layer151may include one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). The second preliminary epitaxial layer152P may include Ge in a concentration higher than that of the first epitaxial layer151. In an example embodiment, the second preliminary epitaxial layer152P may include Ge in a concentration of about 40 at % to about 45 at %.

Referring toFIG.9G, a third lower epitaxial layer153P1may be formed on the second preliminary epitaxial layer152P. The third lower epitaxial layer153P1may include silicon germanium (SiGe) doped with a group3element. According to an example embodiment, the first epitaxial layer151may include one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). The third lower epitaxial layer153P1may include Ge in a concentration higher than that of the second preliminary epitaxial layer152P. In an example embodiment, the third lower epitaxial layer153P1may include Ge in a concentration of about 50 at % to about 55 at %. The third lower epitaxial layer153P1may be formed to have a volume of about 35% to about 45% of the third epitaxial layer153in the final structure illustrated inFIG.2.

As illustrated inFIG.9G, a defect illustrated in a V-shape may be formed on the upper surface of the third lower epitaxial layer153P1. However, the defect of the third lower epitaxial layer153P1may be removed by the process inFIG.9H.

Referring toFIG.9H, the second preliminary epitaxial layer152P and the third lower epitaxial layer153P1may be reflowed. For example, heat may be supplied to the first epitaxial layer151, the second preliminary epitaxial layer152P, and the third lower epitaxial layer153P1grown in the recess region together with a carrier gas. The carrier gas may be, for example, hydrogen (H2) gas. When heat is supplied to the epitaxial layers grown in the recess region along with a carrier gas, atoms of each epitaxial layer may move in a direction in which the total surface energy is lowered, that is, for example, in a vertical downward direction (−Z).

Mobility of atoms may be different depending on the concentrations of Ge of the epitaxial layers. For example, the third lower epitaxial layer153P1and the second preliminary epitaxial layer152P including Ge in a relatively high concentration may have atomic mobility greater than that of the first epitaxial layer151including Ge in a relatively low concentration. In the example, in the third lower epitaxial layer153P1and the second preliminary epitaxial layer152P, surface atoms may be diffused and may reflow, whereas in the first epitaxial layer151, atoms may hardly move. Since the third epitaxial layer153P1includes Ge in a higher concentration than that of the second epitaxial layer152P, the atomic mobility of the third epitaxial layer153P1may be greater than the atomic mobility of the second epitaxial layer152P.

The third lower epitaxial layer153P1may have a gently curved shape as illustrated inFIG.9Hby diffusion of surface atoms. Accordingly, dislocations formed on the surface of the third lower epitaxial layer153P1formed in the process inFIG.9Gmay be removed.

In the second preliminary epitaxial layer152P, surface atoms may be diffused in the vertical downward direction (−Z), such that the level of the uppermost portion may be lowered. Accordingly, a portion of the internal surface of the first epitaxial layer151may be exposed. As surface atoms of the second preliminary epitaxial layer152P move to the central region, a thickness in the vertical direction Z in the central region of the second preliminary epitaxial layer152P may increase. The thickness in the horizontal direction X in the edge region extending from the central region of the second preliminary epitaxial layer152P may decrease. As the second preliminary epitaxial layer152P is deformed into the shape as above, an aspect ratio of the space in which the third preliminary epitaxial layer153P2formed in the process inFIG.9Iis formed may be relatively reduced.

Referring toFIG.9I, silicon-germanium (SiGe) may be epitaxially grown on the third lower epitaxial layer153P1, thereby forming a third preliminary epitaxial layer153P2. The third preliminary epitaxial layer153P2may be formed to be in contact with the second preliminary epitaxial layer152P and the first epitaxial layer151. The third preliminary epitaxial layer153P2may be formed to a level below the upper surface of the third channel layer143.

The third preliminary epitaxial layer153P2may be formed of a material having the same composition as that of the third lower epitaxial layer153P1. For example, the third lower epitaxial layer153P1may include silicon germanium (SiGe) doped with a group3element, and may include Ge in a concentration of about 50 at % to about 55 at %. Since the third preliminary epitaxial layer153P2and the third lower epitaxial layer153P1have the same composition, an interfacial surface between the third preliminary epitaxial layer153P2may not be distinct.

Similarly the third lower epitaxial layer153P1, a V-shaped defect may be formed on the upper surface of the third preliminary epitaxial layer153P2. However, the defect of the third preliminary epitaxial layer153P2may be removed by the process inFIG.9J.

Referring toFIG.9J, the second preliminary epitaxial layer152P and the third preliminary epitaxial layer153P2may be reflowed. The surface atoms of the third preliminary epitaxial layer153P2may be diffused and the third preliminary epitaxial layer153P2may have a gently curved shape as illustrated inFIG.9J. Accordingly, dislocations formed on the surface of the third preliminary epitaxial layer153P2formed in the process inFIG.9Imay be removed. The third preliminary epitaxial layer153P2from which dislocations are removed may be included in the third epitaxial layer153.

In the second preliminary epitaxial layer152P, surface atoms may be further diffused in the vertical downward direction (−Z) and the second epitaxial layer152may be formed. In the example embodiment, the second preliminary epitaxial layer152P may reflow to the extent that the level of the uppermost end may be disposed on a level between the lower surface of the third channel layer143and the upper surface of the second channel layer142, but an example embodiment thereof is not limited thereto. The second preliminary epitaxial layer152P may be reflowed to the extent that the level of the uppermost end may be disposed on a level between the lower surface of the second channel layer142and the upper surface of the first channel layer141, for example. In this case, the second epitaxial layer152aas illustrated inFIG.5may be formed. The degree to which the second preliminary epitaxial layer152P is reflowed may be controlled according to a concentration of Ge of the second preliminary epitaxial layer152P, a reflow condition, and the like.

Referring toFIG.9K, a fourth epitaxial layer154may be formed on the third epitaxial layer153. The fourth epitaxial layer154may include silicon (Si) doped with a group3element. For example, the fourth epitaxial layer154may include one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). In an example embodiment, the fourth epitaxial layer154may include silicon (Si) doped with boron (B), and germanium (Ge) may not be substantially included in the fourth epitaxial layer154.

An interlayer insulating layer190may be formed between sacrificial gate structures170adjacent to each other on the fourth epitaxial layer154, and the sacrificial layers120and the sacrificial gate structure170may be removed. The interlayer insulating layer190may be formed by forming an insulating layer covering the sacrificial gate structures170and the source/drain regions150and performing a planarization process.

The sacrificial layers120and the sacrificial gate structures170may be selectively removed with respect to the spacer layers161, the interlayer insulating layer190, and the channel layers141,142, and143. First, the upper gap regions UR may be formed by removing the sacrificial gate structures170, and the lower gap regions LR may be formed by removing the sacrificial layers120exposed through the upper gap regions UR. For example, when the sacrificial layers120include silicon germanium (SiGe) and the channel layers141,142, and143include silicon (Si), the sacrificial layers120may be selectively removed by performing a wet etching process using peracetic acid as an etchant. During the removal process, the source/drain regions150may be protected by the first epitaxial layer151formed in an outermost region and having a low selective etch ratio.

Thereafter, referring back toFIG.2, the gate structure160may be formed in the upper gap regions UR and the lower gap regions LR. The gate dielectric layer162may be formed to conformally cover internal surfaces of the upper gap regions UR and the lower gap regions LR. The gate electrode layer163may be formed to completely fill the upper gap regions UR and the lower gap regions LR. The gate electrode layer163and the spacer layers161may be removed by a predetermined depth from an upper portion in the upper gap regions UR. A gate capping layer164may be formed in a region of the upper gap regions UR from which the gate electrode layer163and the spacer layers161are removed. Accordingly, the gate structure160including the gate dielectric layer162, the gate electrode layer163, the spacer layers161, and the gate capping layer164may be formed.

Thereafter, a contact hole may be formed by patterning the interlayer insulating layer190, and the contact plug180may be formed by filling a conductive material in the contact hole. A lower surface of the contact hole may be recessed into the source/drain regions150. In an example embodiment, the contact plug180may be formed to penetrate the fourth epitaxial layer154and to partially penetrate the third epitaxial layer153. However, the shape and arrangement of the contact plug180are not limited thereto, and may be varied.

InFIGS.9A to9K, the process of manufacturing the third epitaxial layer153by a first process of forming and reflowing the third lower epitaxial layer153P1and a second process of forming and reflowing the third preliminary epitaxial layer153P2, but the method of forming the third epitaxial layer153is not limited thereto. In example embodiments, the third epitaxial layer153may be formed by performing three or more processes.

The example embodiments described above may be applied regardless of the length of the channel, the type of device, and the like. For example, the example embodiments may be applicable to both a semiconductor device having a short channel and a long channel. Also, the example embodiments may be applicable to both a single gate (SG) device and an extra gate (EG) device.

According to the aforementioned example embodiments, by controlling the structure of the source/drain region, a semiconductor device having improved electrical properties may be provided.