Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes preparing a first wafer including a first trench; forming a first semiconductor layer inside the first trench so that a first space remains in the first trench; obtaining a first level corresponding to a bottom of the first space and a second level estimated by a size or a shape of the first space; preparing a second wafer including a second trench having a shape and a size substantially same as a shape and a size of the first trench; forming a second semiconductor layer inside the second trench in the second so that a second space remains in the second trench; forming a third semiconductor layer to fill the second space in the second trench; and removing a surface portion of the second wafer to a depth corresponding to a level between the first level and the second level.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-033709, filed on Feb. 27, 2019; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments relate to a method of manufacturing a semiconductor device.

BACKGROUND

Power control semiconductor devices include a device having a so-called super junction structure in which an n-type semiconductor layer and a p-type semiconductor layer are arranged alternately in a direction crossing the current. For example, the super junction structure is formed by filling p-type semiconductor layers into trenches provided in an n-type semiconductor. However, when a trench has a large ratio of the depth to the opening width, it becomes difficult to fill a p-type semiconductor layer into the trench without a defect such as void generated therein.

DETAILED DESCRIPTION

According to one embodiment, a method of manufacturing a semiconductor device includes preparing a first wafer of a first conductivity type, the first wafer including a first trench having a first opening portion, the first opening portion being enlarged comparing to other portion of the first trench; forming a first semiconductor layer of a second conductivity type inside the first trench of the first wafer under a first growth condition so that a first space remains in the first opening portion of the first trench; obtaining first and second levels along a depth direction of the first trench, the first level corresponding to a bottom of the first space, the second level being estimated by a size or a shape of the first space in the first trench; preparing a second wafer of the first conductivity type, the second wafer including a second trench having a second opening portion, the second opening portion being enlarged comparing to other portion of the second trench, the second trench having a shape and a size substantially same as a shape and a size of the first trench; forming a second semiconductor layer of the second conductivity type inside the second trench in the second wafer under the first growth condition so that a second space remains in the second opening portion of the second trench; forming a third semiconductor layer under a second growth condition to fill the second space in the second trench; and removing a surface portion of the second wafer to a depth corresponding to an intermediate level between the first level and the second level, the surface layer including a portion of the third semiconductor layer.

Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.

There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward.

FIG. 1is a schematic cross-sectional view showing a semiconductor device1according to an embodiment. For example, the semiconductor device1is a power MOSFET which has a super junction structure.

As shown inFIG. 1, the semiconductor device1includes a semiconductor body10, a drain electrode20, a source electrode30, and a gate electrode40. The drain electrode20is provided on the back surface of the semiconductor body10. The source electrode30is provided on the front surface of the semiconductor body10. For example, the gate electrode40is provided between the semiconductor body10and the source electrode30. For example, the gate electrode40opposes the semiconductor body10with a gate insulating film43interposed. The gate electrode40is electrically insulated from the source electrode30by an inter-layer insulating film45.

The semiconductor body10includes, for example, a drift layer11, a p-type diffusion layer13, an n-type source layer15, and an n-type drain layer17. The semiconductor body10is, for example, silicon.

The drift layer11includes, for example, an n-type pillar11N, a p-type pillar11p, and an n-type semiconductor region11B. For example, the n-type pillar11N and the p-type pillar lip extend in a direction (the Z-direction) from the drain electrode20toward the source electrode30and are arranged alternately in a direction (the X-direction) along the front surface of the semiconductor body10. The n-type pillar11N is positioned between adjacent p-type pillars11P. The n-type pillar11N and the p-type pillar11P are provided to have a charge balance. In other words, the total amount of the p-type impurities included in the n-type pillar11N and the p-type pillar11P is substantially the same as the total amount of the n-type impurities included in the n-type pillar11N and the p-type pillar11P.

The n-type semiconductor region11B is positioned between the p-type pillar11P and the n-type drain layer17and between the n-type pillar11N and the n-type drain layer17. The n-type semiconductor region11B includes the n-type impurities with substantially the same concentration as the n-type impurities in the n-type pillar11N. For example, the boundary between the n-type semiconductor region11B and the n-type pillar11N is positioned at the same level as the boundary between the p-type pillar11P and the n-type semiconductor region11B, in the Z-direction.

For example, the p-type diffusion layer13is selectively provided between the p-type pillar11P and the source electrode30. The p-type diffusion layer13includes the p-type impurities with a higher concentration than the concentration of the p-type impurities in the p-type pillar11P. The source electrode30is electrically connected to the p-type diffusion layer13.

The n-type source layer15is selectively provided between the p-type diffusion layer13and the source electrode30. The n-type source layer15includes the n-type impurities with a higher concentration than the concentration of the n-type impurities in the n-type pillar11N. The source electrode30contacts the n-type source layer15and is electrically connected to the n-type source layer15.

For example, the gate electrode40is provided between the n-type pillar11N and the source electrode30. The gate electrode40is provided to oppose the n-type pillar11N and a portion of the p-type diffusion layer13between the n-type pillar11N and the n-type source layer15with the gate insulating film43interposed.

The n-type drain layer17is provided between the drift layer11and the drain electrode20. The n-type drain layer17includes the n-type impurities with a higher concentration than the concentration of the n-type impurities in the n-type pillar11N and the concentration of the n-type impurities in the n-type semiconductor region11B. For example, the drain electrode20contacts the n-type drain layer17and is electrically connected to the n-type drain layer17.

A method of manufacturing the semiconductor device1will be described here with reference toFIGS. 2A to 6B.

FIGS. 2A to 6Bare schematic cross-sectional views showing manufacturing processes of the semiconductor device1according to the embodiment.FIGS. 2A to 6Bare schematic views illustrating a cross section of a semiconductor wafer100. The semiconductor wafer100is, for example, an n-type silicon wafer.

As shown inFIG. 2A, a mask103is formed selectively on the front surface of the semiconductor wafer100. The mask103is, for example, a silicon oxide film. For example, the mask103is provided in a line-and-space configuration extending in the Y-direction.

As shown inFIG. 2B, opening portions105are formed in the front surface side of the semiconductor wafer100by selectively etching the semiconductor wafer100using the mask103. At this time, for example, the semiconductor wafer100is isotropically etched using CDE (Chemical Dry Etching) or wet etching. For example, an opening portion105is provided to have an opening width WOPin the X-direction that is wider than an opening width WMof the mask103in the X-direction.

As shown inFIG. 3A, trenches107are formed in the front surface side of the semiconductor wafer100by selectively etching the semiconductor wafer100using the mask103. For example, the trenches107are formed using anisotropic RIE (Reactive Ion Etching).

A trench107includes the opening portion105enlarged in the X-direction. The opening portion105is provided to make it easy to grow a p-type semiconductor layer inside the trench107. For example, it is possible to suppress the generation of defects, for example, cavities (voids) inside the p-type semiconductor layer by providing the opening portion105.

As shown inFIG. 3B, p-type semiconductor layers113are formed to cover the inner surfaces of the trenches107. Because the mask103remains on the front surface of the semiconductor wafer100, for example, a p-type semiconductor layer113is epitaxially grown selectively on the silicon surface that is exposed at the inner surface of the trench107. The p-type semiconductor layer113is, for example, a p-type silicon layer including boron (B) which is a p-type impurity.

As shown inFIG. 4A, p-type semiconductor layers115are further formed inside the trenches107. A p-type semiconductor layer115is epitaxially grown on the surface of the p-type semiconductor layer113. The p-type semiconductor layer115is formed under a condition such that the growth rate thereof is slower than the growth rate of the p-type semiconductor layer113. The p-type semiconductor layer115is, for example, a p-type silicon layer including boron (B) which is a p-type impurity.

For example, the growth of the p-type semiconductor layer115ends, leaving a space105sinside the opening portion105. For example, a first surface115fand a second surface115gof the p-type semiconductor layer115are exposed inside the space105s. The first surface115fis positioned in the Z-direction at a higher level than a level of the second surface115gin the Z-direction. The first surface115fis formed to be linked to the second surface115g. The tilt angle of the first surface115fwith respect to the Z-direction is larger than the tilt angle of the second surface115gwith respect to the Z-direction.

For example, when the semiconductor wafer100is a silicon wafer having the (100) plane as a major surface, the first surface115fis equivalent to the (111) plane. Such a shape of the space105sis formed by epitaxial growth of silicon on the inner surface of the opening portion105while the mask103remains. There may be a case where a small void DF1is formed directly under the space105sin the Z-direction.

As shown inFIG. 4B, a p-type semiconductor layer117is formed to fill the space105s. The p-type semiconductor layer117is epitaxially grown on the first surface115fand the second surface115gof the p-type semiconductor layer115. The p-type semiconductor layer117is, for example, a p-type silicon layer including boron (B) which is a p-type impurity. The p-type semiconductor layer117is formed under a condition such that the growth rate thereof is faster than the growth rate of the p-type semiconductor layer115. The p-type semiconductor layer117includes a void DF2positioned in the Z-direction at the level of the connected portion of the first surface115fand the second surface115g.

As shown inFIG. 5A, the surface portion of the semiconductor wafer100is removed on the front surface side thereof where the p-type semiconductor layer117is formed. For example, the surface layer of the semiconductor wafer100is removed using CMP (Chemical Mechanical Polishing). For example, the CMP is stopped at an intermediate level in the Z-direction between the void DF1and the void DF2(referring toFIG. 4B). The surface layer that includes the void DF2is removed thereby. Also, it is possible to avoid the exposure of the void DF1at the front surface of the semiconductor wafer100.

As shown inFIG. 5B, p-type diffusion layers13are formed selectively on the p-type pillars11P, respectively. The p-type pillars11P each include the p-type semiconductor layer113and the p-type semiconductor layer115. For example, the p-type diffusion layers13are formed by selectively ion-implanting boron (B) which is a p-type impurity and is diffused by heat treatment. Then, a p-type diffusion layer13is formed so that the void DF1is positioned therein. Thereby, it is possible to prevent the void DF1from being positioned inside the depletion layer when operating the semiconductor device1, and thus, it is possible to avoid the negative effects of the void DF1on the device characteristics.

As shown inFIG. 6A, the n-type source layers15are formed selectively inside the p-type diffusion layer13. For example, the n-type source layers15are formed by selectively ion-implanting phosphorus (P) which is an n-type impurity and is activated by heat treatment.

The gate electrodes40and the source electrode30also are formed on the front surface of the semiconductor wafer100. Thereby, a MOS (Metal Oxide Semiconductor) structure is formed on the front surface side of the semiconductor wafer100. Then, the semiconductor wafer100is thinned to a prescribed thickness by grinding or polishing on the backside thereof.

A p-type diffusion layer13is positioned between the p-type pillar11P and the source electrode30. An n-type source layer15is selectively provided between the p-type diffusion layer13and the source electrode30. A gate electrode40is positioned between the source electrode30and a portion of the semiconductor wafer100(the n-type pillar11N) that is positioned between the adjacent p-type pillars11P. The source electrode30is provided to cover the p-type diffusion layer13, the n-type source layer15, and the gate electrode40. The source electrode30is electrically connected to the n-type source layer15and the p-type diffusion layer13between the adjacent gate electrodes40. The gate electrode40is electrically insulated from the n-type pillar11N, the p-type diffusion layer13, and the n-type source layer15by the gate insulating film43. Also, the gate electrode40is electrically insulated from the source electrode30by the inter-layer insulating film45.

As shown inFIG. 6B, the semiconductor body10is completed by forming the n-type drain layer17at the backside of the semiconductor wafer100. The drain electrode20also is formed on the back surface of the semiconductor body10. A portion of the semiconductor wafer100remains as the n-type pillar11N and the n-type semiconductor region11B.

In the example recited above, although the processes of forming the p-type semiconductor layer113, the p-type semiconductor layer115, and the p-type semiconductor layer117inside the trench107are described in order, the p-type semiconductor layers may be formed to be continuous while changing the growth conditions.

FIG. 7is a schematic view showing a partial cross section of the semiconductor wafer100in a manufacturing process of the semiconductor device1according to the embodiment.FIG. 7is a schematic cross-sectional view in which a portion of the cross section shown inFIG. 4Ais enlarged.

For example, the structure shown inFIG. 7is obtained by ending the epitaxial growth at the time when the p-type semiconductor layer113and the p-type semiconductor layer115are formed inside the trench107.

As shown inFIG. 7, the space105sis formed on the front surface side of the semiconductor wafer100. For example, two first surfaces115fand two second surfaces115gare exposed at the inner surface of the space105s.

For example, the void DF1is formed directly under the bottom of the space105s. In other words, the void DF1is positioned lower than a level L1in the Z-direction where the bottom of the space105sis positioned. The void DF2is formed at the level in the Z-direction where the first surface115fis connected to the second surface115g. For example, a level L2where the extension planes of the two first surfaces115fcross is positioned below the void DF2.

For example, the void DF2can be removed by removing the surface layer of the semiconductor wafer100to an intermediate level between the level L1and the level L2. Also, it is possible to prevent the void DF1from being exposed at the front surface of the semiconductor wafer100after removing the surface layer thereof. Thus, the manufacturing yield of the semiconductor device1can be improved thereby.

For example, a monitor wafer is formed by stopping the growth of the p-type semiconductor layer that fills the trench107after the p-type semiconductor layer115is grown and before the growth of the p-type semiconductor layer117starts. The levels L1and L2can be estimated by the shape and size of the space105sin the monitor wafer. For example, the level L1of the bottom of the space105scan be known by measuring the size of the space105sin the monitor wafer. Also, the level L2can be derived based on an opening width WSof the space105s. In other words, when the first surface115fis equivalent to the (111) plane of silicon, the level L2is a depth calculated by WS×(½)×Tan 54.7°. Here, “54.7°” is the interior angle between the (100) and (111) planes of silicon.

Thus, in the manufacturing processes of the semiconductor device1shown inFIG. 2AtoFIG. 6B, the level L1and the level L2can be known by making the monitor wafer by stopping the growth of the p-type semiconductor layer after the p-type semiconductor layer115is grown and before the growth of the p-type semiconductor layer117starts. The removal amount of the surface layer of the semiconductor wafer100can be controlled thereby. A trench is formed in the monitor wafer and has substantially the same shape and size (e.g., the width in the X-direction and the depth in the Z-direction) as that of the wafer in which the p-type semiconductor layer117is formed.

FIG. 8is a graph showing a characteristic of the manufacturing processes of the semiconductor device1according to the embodiment. The horizontal axis X is the level in the Z-direction of the boundary between the first surface115fand the second surface115g. The vertical axis Y is the level in the Z-direction of the bottom of the space105s. For example, X and Y are depths from the front surface of the semiconductor wafer100.

Plotted inFIG. 8is data which is obtained using the monitor wafer of which the growth process is stopped after the p-type semiconductor layer115is grown and before the growth of the p-type semiconductor layer117starts. The removal amount of the surface layer of the semiconductor wafer100may be controlled based on the correlation of these data. For example, the correlation equation Y=10.6−2.24X is obtained from the data ofFIG. 8. In other words, when one of X or Y can be known from the size and the shape of the space105s, the intermediate level between the void DF1and the void DF2, e.g., (X+Y)/2 can be known. The removal amount of the surface layer of the semiconductor wafer100may be controlled thereby.

Thus, in the embodiment, the opening portion105of the trench107is enlarged; and the growth rate of the p-type semiconductor layer115is set to be slower than the growth rate of the p-type semiconductor layer113and the growth rate of the p-type semiconductor layer117. Thereby, it is possible to avoid the generation of large voids inside the p-type pillar11P while suppressing the growth time of the super junction structure. Even using such a growth method, it is difficult to avoid the generation of the small void DF2, but possible to remove the void DF2with the surface layer of the semiconductor wafer100. Moreover, the exposure of the void DF1can be avoided at the front surface of the semiconductor wafer100. The manufacturing yield of the semiconductor device1can be increased thereby.