Low power input gating

Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.

BACKGROUND

Integrated circuits typically include circuitry to perform data access functions to assist with memory operations. However, even when disabled or in standby, some of these data access functions may parasitically consume power. For instance, a significant portion of total dynamic power may be consumed due to toggling of control input pins of memory when disabled or in standby. As such, there exists a need to reduce control input pin power consumed when disabled or in standby.

DETAILED DESCRIPTION

Various implementations as described herein refer to and are directed to low power input gating circuitry for providing improved power, performance, and area (PPA) by reducing pin power to the control inputs of memory. Further, various implementations described herein refer to and are directed to introducing a low power feature configured to gate-off latches to reduce control input pin power of memory so as to improve PPA.

Various implementations of low power input gating will now be described in more detail with reference toFIGS. 1-5.

FIG. 1illustrates a block diagram of low power input gating circuitry100in accordance with various implementations described herein. As shown inFIG. 1, low power input gating circuitry100may be implemented as an integrated circuit with multiple stages. In some implementations, the multiple stages may be referred to as sub-divided circuit portions, components, or devices with interdependent relationships. For instance, low power input gating circuitry100may include a chip enable device110, a latch enable device120, a latch device130, a decoder device140, and a memory device150. As will be described in greater detail herein, these devices110,120,130,140,150may be used separately or as integrated circuit portions with interdependent relationships.

The chip enable device110may be configured to receive and use a clock input signal CLK to toggle a control input152of the memory device150based on a chip enable signal CEN, which may also be referred to as a Common Enable signal. After passing through logical processing in the chip enable device110, the clock input signal CLK may be passed from the chip enable device110to the latch enable device120and also passed to the decoder device140. The latch enable device120may be configured to receive the CLK signal from the chip enable device110and then pass one or more other CLK signals, such as, e.g., NCLK, BLCK, to the latch device130based on a latch enable signal LATEN. Further, the decoder device140may be configured to receive the CLK signal from the chip enable device110and then pass an output signal OUT based on the CLK signal to the control input152of the memory device150.

The latch device130may be configured to latch the control input152of the memory device150. As described herein, the clock input signal CLK may be passed from the chip enable device110to the latch enable device120. Further, the latch enable device120may receive the CLK signal and pass the NCLK signal and the BCLK signal to the latch device130. Further, the latch device130may be configured to receive the NCLK and BCLK signals along with an address bus signal ADDR and then provide a latch signal LAT to the decoder device140. The latch device130may be coupled to an address bus (not shown), and the latch device130may be configured to receive the address bus signal ADDR via the address bus. In various implementations, the address bus may be coupled to an external device or circuit, such as, e.g., external memory. Further, the latch device130may include a low phase latch device. Further, in various implementations, the address bus may refer to any bus or control bus configured to provide a control signal, and input gating may be used for any other signal in addition to the address bus. As such, the latch device may be coupled to any bus, and the latch device may thus be configured to receive any control signal via any bus.

As shown, the latch enable device120may be coupled between the chip enable device110and the latch device130. Further, the latch enable device120may be configured to receive the clock input signal CLK from the chip enable device110. The latch enable device120may be configured to use the clock input signal CLK to gate the latch device130based on the latch enable signal LATEN so as to selectively cutoff toggling of the clock input signal CLK (as the output signal OUT) to the control input152of the memory device150. In some implementations, the latch enable device120may be configured to provide low power input gating to the latch device130by using the latch enable signal LATEN to selectively cutoff toggling of the clock input signal CLK (as output signal OUT) to the control input152of the memory device150.

As shown, the decoder device140may be coupled to the chip enable device110, the latch device130, and the memory device150. The decoder device140may be configured to receive the clock input signal CLK from the chip enable device110, receive the latch signal LAT from the latch device130, and provide the output signal OUT to the control input152of the memory device150based on the chip enable signal CEN provided to the chip enable device110and based on the latch enable signal LATEN provided to the latch enable device120. These and other functional operations of the decoder device1440will be described in greater detail herein below.

The memory device150may comprise any relevant memory device having the control input152. In some implementations, the memory device150may include random access memory (RAM), such as, e.g., static RAM (SRAM).

FIG. 2illustrates a schematic diagram of a low power input gating circuit200in accordance with various implementations described herein. As shown inFIG. 2, the low power input gating circuit200may be implemented with multiple stages that may be referred to as sub-divided circuit portions, components, or devices with interdependent relationships. For instance, low power input gating circuit200may include a chip enable device210, a latch enable device222, a latch device230, a decoder device240, and a memory device250. These devices210,222,230,240,250may be similar to respective devices110,120,130,140,150ofFIG. 2. Further, as described in greater detail herein, these devices210,222,230,240,250may be used separately or as integrated circuit portions with interdependent relationships.

The chip enable device or circuit210may include a first logic device N1coupled to a clock input path, and the logic device N1may be configured to receive the clock input signal CLK via the clock input path. In some implementations, the logic device N1may include, e.g., an N-type Metal-Oxide-Semiconductor (NMOS) transistor N1. As shown inFIG. 2, NMOS transistor N1may be disposed between first and second inverters212,214. The first inverter212may be configured to receive and invert the clock input signal CLK and then provide the inverted clock input signal (CLK) to the NMOS transistor N1. As shown, the NMOS transistor N1may be configured to pass the inverted clock input signal (CLK) to second inverter214based on chip enable signal CEN. The second inverter214may be configured to receive and invert the inverted clock input signal (CLK) and provide the clock input signal CLK to node GTP, which may refer to a node for implementing a Global Tracking Pulse (GTP). Generally, Global Tracking Pulse (GTP) may refer to an internal memory clock signal. Further, the clock input signal CLK may then be passed to the latch enable device220and the decoder device240.

The latch enable device or circuit220may include a first logic device222and a second logic device224. As shown inFIG. 2, the first logic device222may include a NOR gate configured to receive the clock input signal CLK from the chip enable device210via the node GTP. The first logic device222(i.e., NOR gate) may also be configured to receive the latch enable signal LATEN from an external device or circuit. Further, based on latch enable signal LATEN, first logic device222(i.e., NOR gate) may be configured to provide the CLK signal as a first output clock signal NCLK to second logic device224and also to latch device230. Further, the second logic device224may include an inverter configured to receive the first output clock signal NCLK from the first logic device222(i.e., NOR gate) and provide a second output clock signal BCLK to the latch device230. The second output clock signal BCLK may be an inverse or a compliment (orNCLK) of the first clock input signal NCLK.

In some implementations, the LATEN signal may be an active low signal that may be used to clock gate the address pins of the latch device230. For instance, when the LATEN signal is 0 (LATEN=0), the latch device230may be configured in a normal active mode. Further, when the LATEN signal is 1 (LATEN=1), the BCLK signal may be forced to 1, and the latch device230may be configured in a standby mode (or chip-disable mode). This mode may be used for input latch blocking to avoid or at least inhibit any toggling of the control input252of the memory device252after the latch. Further, the latch device230may be referred to as a PH2 Latch, and when BLCK is 0 (BLCK=0), the PH2 Latch may be or become transparent.

In some implementations, the first and second logic devices222,224may be configured to provide low power input gating to latch device230by using the latch enable signal LATEN to selectively cutoff toggling of clock input signal CLK to the control input252of memory device250. For instance, the first and second logic devices222,224of the latch enable device220may be arranged and configured to use the clock input signal CLK received from the chip enable device210to gate the latch device230based on the latch enable signal LATEN so as to selectively cutoff the clock input signal CLK to the control input252of the memory250. In some cases, the first logic device222is coupled to the chip enable device210, and as such, the first logic device222is configured to receive the clock input signal CLK via the chip enable device210based on the chip enable signal LATEN. Further, in some cases, the second logic device224is coupled to the chip enable device210via the first logic device222, and as such, the second logic device224may be configured to receive the clock input signal CLK from the chip enable device210via the first logic device222based on the chip enable signal LATEN.

The latch device230may be configured to latch the control input252of the memory device250based on the first clock output signal NCLK, the second clock output signal BCLK, and/or the latch enable signal LATEN. As described herein above, the latch enable signal LATEN may be used to control output of the first output clock signal NCLK to the latch device230. In some implementations, the latch device230may receive the NCLK and BCLK signals along with an address bus signal ADDR and then provide a latch signal LAT to the decoder device240based on one or more of these signals NCLK, BCLK, and/or ADDR. Further, latch device230may be coupled to an address bus (not shown), and the latch device230may be configured to receive the address bus signal ADDR via the address bus. In some implementations, as described herein above, the latch device230may implemented with a low phase latch device.

The decoder device240may be coupled to chip enable device210, latch device230, and memory device250. The decoder device240may be configured to receive the clock input signal CLK from the chip enable device210and receive the latch signal LAT from the latch device230. Further, the decoder device240may be configured to provide the output signal OUT to the control input252of the memory device250based on the chip enable signal CEN provided to the chip enable device210and/or based on the latch enable signal LATEN provided to the latch enable device220.

In some implementations, as shown inFIG. 2, the decoder device240may include a first decoder242(e.g., a ROWCLK decoder) and a second decoder244(e.g., an address decoder). Further, the decoder device240may include one or more logic devices including, e.g., a first logic device246that may be implemented as a NAND gate and a second logic device248that may be implemented as an inverter. The first decoder242may be configured to receive the clock input signal CLK from the chip enable device210, receive the LAT signal from the latch device230, and provide a first signal (e.g., ROWCLK, such as Row Decoder signal, i.e., decoder output clock) to the first logic gate246(i.e., NAND gate). The second decoder244may be configured to receive the LAT signal from latch device230and provide an XDEC signal (i.e., X Decoder signal) to the first logic device246(i.e., NAND gate). The first logic device246(i.e., NAND gate) may be configured to receive the ROWCLK signal from the first decoder242, receive the XDEC signal from the second decoder244, and provide a first output signal to the second logic device248(i.e., inverter). The LAT signal may refer to a latched_addr signal, which may refer to a bus split into different bits, and a few bits may be used to decode ROWCLK. Other bits may be used to decode XDEC. In some cases, the LATEN signal is the same as ECEN. Further, the second logic device248(i.e., inverter) may be configured to receive the first output signal from the first logic device246(i.e., NAND gate), invert the received first output signal, and provide a second output signal (i.e., the output signal OUT) to the control input252of the memory device250.

In various implementations, a significant portion of total dynamic power may be consumed due to toggling of control inputs of memory in chip-disable mode. For instance, control input pin power in chip-disable mode may account for up to approximately 8% of total power in memory. As such, the techniques described herein may be used to reduce pin power in standby mode (i.e., chip-disable mode). For instance, techniques described herein may be used to reduce pin power in standby mode to less than approximately one-tenth of a same pin power in active mode.

With the low power input gating feature described herein, an ECEN (Early CEN) signal may be added to gate the latches of control inputs to reduce power consumption inside the memory due to the toggling of control inputs. In some cases, as described herein, the LATEN signal may be the same as the ECEN signal. Further, in some cases, this ECEN signal may be used to gate the latches for the following inputs: Address (ADDR), Global Write Enable (GWEN), Left Right Enable (LREN), and Extra Margin Adjustment (EMA). Further, the ECEN signal may not be used to gate D or WEN latches, due to implementation constraints. However, this idea may be applies to all control pins.

As described in reference toFIG. 2, the CEN signal may be used to control GTP (Global Tracking Pulse) and WL (Wordline) headers. In some cases, the CEN signal may be used to gate the power supply (not shown) to the second logic device248(i.e., inverter) of the decoder device240. With the addition of the ECEN signal, the following design changes may be introduced: the CEN signal may be used to control GTP, and the ECEN signal may be used to control WL headers and latch enables. Further explanation of these signals along with other related signals is provided herein below in reference toFIG. 3and Tables 1 and 2.

FIG. 3illustrates a diagram of latch enable circuitry300in accordance with various implementations described herein. In particular, the latch enable circuitry300ofFIG. 3is an alternate implementation of the latch enable circuitry220ofFIG. 2. As shown inFIG. 3, the latch enable circuitry300may be implemented with multiple logic devices that may be referred to as sub-divided circuit portions, components, or devices coupled together and arranged to have interdependent relationships.

The latch enable circuitry300may include a first logic device310(e.g., a NAND gate) coupled to a second logic device312(e.g., an inverter). The first logic device310(e.g., NAND gate) may be configured to receive a first input signal NDFTRAMBYP (i.e., Not Designed For Testing RAM BYPass signal) and a second input signal ECEN (i.e., Early Chip-ENable signal, or LATEN signal) and then provide an output signal to the second logic device312(i.e., inverter). The second logic device312(i.e., inverter) may be configured to receive the output signal from the first logic device310(i.e., NAND gate) and then provide an output signal ECENDFT (i.e., ECEN Designed For Testing).

The latch enable circuitry300may include a third logic device314(e.g., a NOR gate) coupled to a fourth logic device316(e.g., a NAND gate). The third logic device314(e.g., NOR gate) may be configured to receive the second input signal ECEN and a third input signal CEN (i.e., Chip-ENable signal) and then provide an output signal to the fourth logic device316(i.e., NAND gate). The fourth logic device316(i.e., NAND gate) may be configured to receive the first input signal NDFTRAMBYP and the output signal from the third logic device314(i.e., NOR gate) and then provide an output signal CENDFT.

The latch enable circuitry300may include a fifth logic device320(e.g., a NOR gate) coupled to a sixth logic device322(e.g., a NAND gate). The fifth logic device320(e.g., NOR gate) may be configured to receive output signal ECENDFT from the second logic device (i.e., inverter) and a fourth input signal GTP (i.e., Global Tracking Pulse) and then provide an output signal to the sixth logic device322(i.e., NAND gate). Further, the sixth logic device322(i.e., NAND gate) may be configured to receive the output signal from the fifth logic device320(i.e., NOR gate) and a fifth input signal NGTP (i.e., Not Global Tracking Pulse) and then provide an output signal BCLK (i.e., the second output clock signal BCLK, as described in reference toFIG. 2).

The latch enable circuitry300may include a seventh logic device324(e.g., a NAND gate) coupled to an eighth logic device326(e.g., an inverter). The seventh logic device324(e.g., NAND gate) may be configured to receive the fifth input signal NGTP and the output signal from the fifth logic device320(i.e., NOR gate) and then provide an output signal to the eighth logic device326(i.e., inverter). Further, the eighth logic device326(i.e., inverter) may be configured to receive the output signal from the seventh logic device324(i.e., NAND gate) and then provide an output signal NCLK (i.e., the first output clock signal NCLK, as described in reference toFIG. 2).

Implementation of latch enable circuitry300ofFIG. 3and ECEN functionality is provided in the subsequent Tables 1 and 2. As shown, ECEN may only be effective during Standby mode, and during Scan mode, ECEN may have no impact. In Tables 1 and 2 provided below, DFTRAMBYP refers to Designed For Testing RAM BYPass, and NDFTRAMBYP refers to the opposite polarity of DFTRAMBYP.

FIG. 4illustrates a process flow diagram of a method400for low power input gating in accordance with implementations described herein. It should be understood that even though method400indicates a particular order of execution of operations, in some instances, certain portions of the operations may be executed in a different order, and on different systems. In some other instances, additional operations or steps may be added to and/or omitted from method400. In some implementations, computing device500ofFIG. 5may be configured to perform method400. Further, in some implementations, method400may be implemented as a program or software instruction process configured for low power input gating to improve performance.

At block410, method400may receive multiple signals including a clock input signal, a chip enable signal, and a latch enable signal. At block420, method400may toggle a control input of memory with the clock input signal based on the chip enable signal. At block430, method400may latch the control input of the memory with a latch device based on the clock input signal. At block440, method400may gate the latch device based on a latch enable signal to selectively cutoff toggling of the clock input signal to the control input of the memory. In some instances, gating the latch device may include providing low power input gating to the latch device by using the latch enable signal to selectively cutoff toggling of the clock input signal to the control input of the memory.

FIG. 5illustrates a block diagram of a system500for low power input gating in accordance with various implementations described herein.

In reference toFIG. 5, the system500may include a computer based system configured for low power input gating. The system500may be associated with at least one computing device504that is implemented as a special purpose machine configured for low power input gating, as described herein. In some implementations, the computing device504may include any standard element(s) and/or component(s), including at least one processor(s)510, memory512(e.g., non-transitory computer-readable storage medium, such as e.g., random access memory (RAM)), one or more database(s)540, power, peripherals, and various other computing elements and/or components that may not be specifically shown inFIG. 5. Further, the computing device504may include instructions stored on the non-transitory computer-readable medium512that are executable by the processor510. The computing device504may be associated with a display device550(e.g., monitor or other display) that may be used to provide a user interface (UI)552, such as, e.g., a graphical user interface (GUI). The UI552may be used to receive various parameters and/or preferences from a user for managing, operating, and/or utilizing the computing device504. As such, the computing device504may include display device550for providing output to a user, and display device550may include the UI552for receiving input from the user.

In various implementations, the computing device504may be configured to implement various methodologies for low power input gating. For instance, the computing device504may include a low power input gating module520configured to cause the at least one processor510to implement one or more or all techniques described in reference toFIGS. 1-4. The low power input gating module520may be implemented in hardware and/or software. If implemented in software, the low power input gating module520may be stored in memory512and/or database540. If implemented in hardware, the low power input gating module520may be a separate processing component configured to interface with the at least one processor510.

In various implementations, the low power input gating module520may be configured to cause the at least one processor510to perform various techniques, as described herein in reference toFIGS. 1-4. For instance, low power input gating module520may be configured to cause the at least one processor510to receive multiple signals including a clock input signal, a chip enable signal, and a latch enable signal. The low power input gating module520may be configured to cause the at least one processor510to toggle a control input of memory with the clock input signal based on the chip enable signal, latch the control input of the memory with a latch device based on the clock input signal, and gate the latch device (e.g., a low phase latch device) based on a latch enable signal to selectively cutoff toggling of the clock input signal to the control input of the memory. Further, as described herein, gating the latch device may provide low power input gating to the latch device by using the latch enable signal to selectively cutoff toggling of the clock input signal to the control input of the memory.

Further, in reference toFIG. 5, the computing device504may include a simulator module522configured to cause the at least one processor510to generate one or more simulations of the integrated circuit. The simulator module522may be referred to as a simulating component and may be implemented in hardware and/or software. If implemented in software, the simulator module522may be stored in memory512or database540. If implemented in hardware, the simulator module520may be a separate processing component configured to interface with the processor510. In some instances, the simulator module522may include a SPICE simulator configured to generate SPICE simulations of the integrated circuit. Generally, SPICE refers to an acronym for Simulation Program with Integrated Circuit Emphasis, which is an open source analog electronic circuit simulator. Further, SPICE is a general-purpose software program used by the semiconductor industry to check the integrity of integrated circuit designs and to predict the behavior of integrated circuit designs. Thus, in some instances, the low power input gating module520may be configured to interface with the simulator module522to generate timing data related to operating conditions based on one or more simulations (including, e.g., SPICE simulations) of an integrated circuit that may be used for analyzing the integrated circuit. Further, the low power input gating module520may be configured to use the one or more simulations (including, e.g., SPICE simulations) of the integrated circuit for recommending changes for instances of the cells (e.g., various circuit devices, components, etc.) along circuit paths including critical paths.

In some implementations, the computing device504may include one or more databases540configured to store and/or record various information related to low power input gating. In various instances, the database(s)540may be configured to store and/or record information related to the integrated circuit, various operating conditions, and/or relevant timing data. Further, database(s)540may be configured to store and/or record information related to the integrated circuit and timing data in reference to simulation data (including, e.g., SPICE simulation data).

Implementations of various technologies described herein may be operational with numerous general purpose or special purpose computing system environments or configurations. Examples of computing systems, environments, and/or configurations that may be suitable for use with the various technologies described herein include, but are not limited to, personal computers, server computers, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, smart phones, tablets, wearable computers, cloud computing systems, virtual computers, marine electronics devices, and the like.

The various technologies described herein may be implemented in the general context of computer-executable instructions, such as program modules, being executed by a computer. Program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Further, each program module may be implemented in its own way, and all need not be implemented the same way. While program modules may execute on a single computing system, it should be appreciated that, in some implementations, program modules may be implemented on separate computing systems or devices adapted to communicate with one another. A program module may also be some combination of hardware and software where particular tasks performed by the program module may be done either through hardware, software, or some combination of both.

The various technologies described herein may be implemented in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network, e.g., by hardwired links, wireless links, or various combinations thereof. In a distributed computing environment, program modules may be located in both local and remote computer storage media including, for example, memory storage devices and similar.

Further, the discussion provided herein may be considered directed to certain specific implementations. It should be understood that the discussion provided herein is provided for the purpose of enabling a person with ordinary skill in the art to make and use any subject matter defined herein by the subject matter of the claims.

It should be intended that the subject matter of the claims not be limited to the implementations and illustrations provided herein, but include modified forms of those implementations including portions of implementations and combinations of elements of different implementations in accordance with the claims. It should be appreciated that in the development of any such implementation, as in any engineering or design project, numerous implementation-specific decisions should be made to achieve developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort may be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having benefit of this disclosure.

Described herein are various implementations of an integrated circuit. The integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.

Described herein are various implementations of an integrated circuit. The integrated circuit may include a first logic device configured to receive a clock input signal, receive a latch enable signal, and provide a first output clock signal. The integrated circuit may include a second logic device configured to receive the first output clock signal and provide a second output clock signal that is a compliment of the first clock input signal. The integrated circuit may include a latch device configured to latch a control input of memory based on the first clock output signal, the second clock output signal, and the latch enable signal. Further, the first and second logic devices may be configured to use the clock input signal to gate the latch device based on the latch enable signal so as to selectively cutoff the clock input signal to the control input of the memory.

Described herein are various implementations of a method. The method may include receiving multiple signals including a clock input signal, a chip enable signal, and a latch enable signal. The method may include toggling a control input of memory with the clock input signal based on the chip enable signal. The method may include latching the control input of the memory with a latch device based on the clock input signal. The method may include gating the latch device based on a latch enable signal to selectively cutoff toggling of the clock input signal to the control input of the memory.

Reference has been made in detail to various implementations, examples of which are illustrated in the accompanying drawings and figures. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other instances, well-known methods, procedures, components, circuits and networks have not been described in detail so as not to unnecessarily obscure details of the embodiments.

While the foregoing is directed to implementations of various techniques described herein, other and further implementations may be devised in accordance with the disclosure herein, which may be determined by the claims that follow.