DRIVE SUBSTRATES AND DISPLAY PANELS

Drive substrates and display panels are provided. In a thin film transistor of the drive substrate, a structure with double-gate and double-active layer is formed by a first active layer, a first gate, a first sub-gate of a second gate, and a part of a second active layer in an area adjacent to an output electrode; and a structure with single active layer and top gate is formed by a second sub-gate of the second gate and a part of the second active layer in an area adjacent to an input electrode. The first gate and the second gate together control a first channel of the first active layer and a first portion of a second channel of the second active layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Chinese Patent Application No. 202310801687.8, filed on Jun. 30, 2023, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, and in particular, to drive substrates and display panels.

BACKGROUND

During the research and practice of the related art, it is found that when a thin-film transistor of a Mini-LED or Micro-LED panel is a top-gate type, on a condition that the gate of the thin-film transistor operates at a high voltage, such as at a voltage of about 30 volts, a temperature at an area where the thin-film transistor is located may be as high as 150 degrees Celsius. Under such a high-voltage operation, hot carriers in an oxide semiconductor of an active layer will deteriorate, resulting in a shift in a threshold voltage (Vth).

SUMMARY

In view of above, drive substrates are provided according to embodiments of the present disclosure. The drive substrate includes a base, a first gate, a first insulation layer, a first active layer, a second active layer, a second gate, a second insulation layer, an input electrode, and an output electrode. The first gate is disposed on the base. The first insulation layer is disposed on the base and covers the first gate. The first active layer is disposed on the first insulation layer and includes a first channel overlapping the first gate. The second active layer includes a second channel, a first contact portion, and a second contact portion. The second channel includes a first portion and a second portion connected with each other. The first contact portion is connected to a side of the first portion away from the second portion, and the second contact portion is connected to a side of the second portion away from the first portion. The first portion is directly connected to the first channel. The second portion and the first channel are both attached to the first insulation layer. The second portion is disposed on peripheral sides of the first channel and the first gate. The second insulation layer is disposed on the second active layer. The second gate is disposed on the second insulation layer and includes a first sub-gate and a second sub-gate connected with each other. The first sub-gate overlaps the first portion, and the second sub-gate overlaps the second portion. The input electrode is connected to the second contact portion, and the output electrode is connected to the first contact portion.

Display panels are further provided according to embodiments of the present disclosure. The display panel includes the above-mentioned drive substrate and a light emitting element disposed on the drive substrate, and the light emitting element is connected to the output electrode.

DETAILED DESCRIPTION

Technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application. In addition, it should be understood that the specific implementations described here are only used to illustrate and explain the present disclosure, and are not intended to limit the present disclosure. In the present disclosure, unless stated to the contrary, the orientation terms such as “up” and “down” generally refer to up and down in an actual use or working state of the devices, and the terms “inside” and “outside” refer to an outline of an installation.

Embodiments of the present disclosure provide a drive substrate and a display panel, which will be described in detail below. It should be noted that a description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.

Referring toFIG.1, a drive substrate100is provided according to an embodiment of the present disclosure. The drive substrate100includes a base11, a first gate121, a second gate122, a first insulation layer131, a first active layer141, a second active layer142, a second insulation layer132, an input electrode151, and an output electrode152.

The first gate121is disposed on the base11. The first insulation layer131is disposed on the base11and covers the first gate121. The first active layer141is disposed on the first insulation layer131. The first active layer141includes a first channel41aoverlapping the first gate121.

The second active layer142includes a second channel42a, a first contact portion42b, and a second contact portion42c. The second channel42aincludes a first portion42a1and a second portion42a2connected with each other. The first contact portion42bis connected to a side of the first portion42a1away from the second portion42a2. The second contact portion42cis connected to a side of the second portion42a2away from the first portion42a1. The first portion42a1is directly connected to the first channel41a. The second portion42a2and the first channel41aare both attached to the first insulation layer131, and the second portion42a2is disposed on peripheral sides of the first channel41aand the first gate121.

The second insulation layer132is disposed on the second active layer142.

The second gate122is disposed on the second insulation layer132. The second gate122includes a first sub-gate22aand a second sub-gate22bconnected with each other. The first sub-gate22aoverlaps the first portion42a1. The second sub-gate22boverlaps the second portion42a2.

The output electrode152is connected to the first contact portion42b. The input electrode151is connected to the second contact portion42c.

In the thin film transistor TFT of the drive substrate100in the embodiments of the present disclosure, a structure with double-gate and double-active layer is formed by the first active layer141, the first gate121, the first sub-gate22a, and a part of the second active layer142in an area adjacent to the output electrode152, and a structure with single active layer and top gate is formed by the second sub-gate22band a part of the second active layer142in an area adjacent to the input electrode151. Since the first gate121and the second gate122together control the first channel41aof the first active layer141and the first portion42a1of the second channel42aof the second active layer142, a resistance and a voltage drop of the area are reduced, so that an electric field intensity of the area is weakened during operation, thereby suppressing the movement of the hot carriers and improving the stability of the threshold voltage (Vth) of the thin film transistor TFT.

In some embodiments, materials of the first active layer141and the second active layer142may be formed of single crystal silicon, polycrystalline silicon, or oxide semiconductor. The oxide semiconductor may include one of the oxides based on titanium, hafnium, zirconium, aluminum, tantalum, germanium, zinc, gallium, tin or indium, and their composite oxides (such as indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, indium gallium oxide, indium tin oxide, indium zirconium oxide, indium zirconium zinc oxide, indium zirconium tin oxide, indium zirconium gallium oxide, indium aluminum oxide, indium zinc aluminum oxide, indium tin aluminum oxide, indium aluminum gallium oxide, indium tantalum One of germanium tin oxide, indium germanium gallium oxide, titanium indium zinc oxide, and hafnium indium zinc oxide).

In some embodiments, the materials of the first active layer141and the second active layer142are both oxide semiconductors.

In some embodiments, one of the input electrode151and the output electrode152is a source, and the other is a drain.

Optionally, in the embodiment, the first contact portion42band the first channel41aare both attached to the first insulation layer131, and the first contact portion42bis connected to a lateral surface of the first channel41a.

That is to say, the first active layer141only includes the first channel41a. The first active layer141and the second active layer142share the first contact portion42b, which may save materials and subsequent doping or ion implantation time.

In some embodiments, based on an upper surface of the first insulation layer131, the first contact portion42bis overlapped with the lateral surface of the first channel41a, and a height of the first contact portion42bis greater than a height of the first channel41a.

That is, the first contact portion42bis in oblique contact with the first channel41a, which increases a contact area and also increases an area of the first contact portion42b.

In some embodiments, a resistance value of the first contact portion42band a resistance value of the second contact portion42care both less than a resistance value of the first channel41aand less than a resistance value of the second channel42a.

Since the resistance value of the first contact portion42bis less than the resistance value of the first channel41aand less than the resistance value of the second channel42a, a resistance value of the first contact portion42bis less than a resistance value of an overlapping area of the first channel41aand the second channel42a, which may improve the conductivity of the thin film transistor TFT.

In some embodiments, a doping concentration of the first contact portion42bis greater than a doping concentration of the second contact portion42c. Such arrangement may have a stronger suppression effect on the carriers. A lower resistance may be achieved by doping more doping ions to the first contact portion42b.

In some embodiments, in an orthographic projection of the drive substrate100, both of a projection of the first sub-gate22aand a projection of the first gate121completely cover a projection of the first channel41aand a projection of the first portion42a1. Such arrangement may improve a mobility of the thin film transistor TFT under a joint action of the first gate121and the second gate122.

In some embodiments, a length of the first channel41ais 15% to 30% of a length of the second channel42a. Such arrangement makes a resistance value of an entire channel (the first channel41acombined with the second channel42a) presents a decreasing trend from the second portion42a2to an overlapping portion (the first portion42a1overlapping the first channel41a) to the first contact portion42b, which is conducive to weakening the electric field intensity of the area where the output electrode152is located without affecting the electric field of the area where the input electrode151is located, thereby ensuring the conduction effect of the thin film transistor TFT.

In some embodiments, the length of the first channel41amay be 15%, 20%, 25%, or 30% of the length of the second channel42a.

In some embodiments, a carrier concentration of the first active layer141is less than or equal to a carrier concentration of the second active layer142. Since the second active layer142occupies a higher proportion as the channel, it covers an entire area of the channel and is located on a side of the first channel41aadjacent to the second gate122, so the carrier concentration of the second active layer142is higher, which may improve the mobility of the thin film transistor TFT.

On a condition that the thin film transistor TFT is N-type, the carriers are electrons. On a condition that the thin film transistor TFT is P-type, the carriers are holes.

In some embodiments, the drive substrate100may further include a passivation layer134and a conductive layer153. The passivation layer134covers the input electrode151and the output electrode152. The conductive layer153is disposed on the passivation layer134and connected to the output electrode152.

In some embodiments, the conductive layer153may be served as a bonding pad for bonding a light emitting element.

In addition, a preparation process of the drive substrate100in the above embodiments is as follows.

Step B11, referring toFIG.2, a first gate121, a first insulation layer131, and a first active layer141are sequentially formed on a base11.

The first insulation layer131covers the first gate121and the base11.

The first insulation layer131is a buffer layer, which may be a single-layer or a multi-layer stacked structure, such as SiOx, Al2O3/SiNx/SiOx, SiOx/SiNx/SiOx, or the like.

The first active layer141includes an oxide semiconductor, such as IGTO, IGZO, IGO, IZO, AIZO, ATZO, or metal oxides doped with rare earth lanthanides.

Then a step B12is subjected.

Step B12, referring toFIG.3, a second active layer142is formed on the first active layer141.

The second active layer142includes a second channel42a, a first contact portion42b, and a second contact portion42c. The second channel42aincludes a first portion42a1and a second portion42a2connected with each other. The first contact portion42bis connected to a side of the first portion42a1away from the second portion42a2. The second contact portion42cis connected to a side of the second portion42a2away from the first portion42a1. The first portion42a1is directly connected to the first channel41a. The second portion42a2and the first channel41aare both attached to the first insulation layer131, and the second portion42a2is disposed on peripheral sides of the first channel41aand the first gate121.

In some embodiments, the second active layer142includes an oxide semiconductor, such as IGTO, IGZO, IGO, IZO, AIZO, ATZO, or metal oxides doped with rare earth lanthanides.

Then a step B13is subjected.

Step B13, referring toFIG.4, a second insulation layer132and a second gate122are sequentially formed on the second active layer142, and the first contact portion42band the second contact portion42care conducted by using the second gate122as a mask.

The second gate122blocks the first channel41aand the second channel42a, and exposes the first contact portion42band the second contact portion42c. Subsequently, the first contact portion42band the second contact portion42care conducted by ion doping or ion implantation. The doped or implanted ions may be P-type or N-type.

In some embodiments, a material of the second insulation layer132may be SiOx, Al2O3/SiNx/SiOx, SiOx/SiNx/SiOx, or the like.

Then a step B14is subjected.

Step B14, referring toFIG.5, an interlayer dielectric layer133and a source-drain metal layer are sequentially formed on the second gate122. The source-drain metal layer includes an input electrode151and an output electrode152.

The interlayer dielectric layer133covers the second gate122, the second active layer142, and the first insulation layer131. The input electrode151is connected to the second contact portion42c, and the output electrode152is connected to the first contact portion42b.

In some embodiments, the interlayer dielectric layer133may be a single-layer or a multi-layer stacked structure, and its material may be SiOx, SiNx, SiNx/SiOx, SiNOx, or the like.

Then a step B15is subjected.

Step B15, referring toFIG.6, a passivation layer134and a conductive layer153are sequentially formed on the source-drain metal layer.

The passivation layer134covers the source-drain metal layer and interlayer dielectric layer133. The conductive layer153is connected to the output electrode152.

In some embodiments, the passivation layer134may be a single-layer or a multi-layer stacked structure, and its material may be SiOx, SiNx, SiNx/SiOx, SiNOx, or the like.

In this way, the preparation process of the drive substrate100of the embodiment is completed.

Referring toFIG.7, compared with the above embodiment, another embodiment of the present disclosure is different from the above embodiment in that: the first active layer141further includes a third contact portion41bconnected to a side of the first channel41a, and the first contact portion42bis stacked on and connected to the third contact portion41b.

In the embodiment, the first contact portion42band the third contact portion41bare superimposed to improve the overall conductivity and reduce the resistance value of the device, which is beneficial to weaken the electric field of the area where the output electrode152is located, thereby suppressing the movement of the hot carriers.

In addition, the superposition of the first contact portion42band the third contact portion41breduces a depth of a hole, so that the output electrode152is more stably connected to the first contact portion42b.

In some embodiments, a resistance value of the first contact portion42bstacked with the third contact portion41bas a whole is less than a resistance value of the second contact portion42c. Such arrangement may further suppress the movement of the hot carriers.

In some embodiments, the drive substrate100further includes a photo-generated carrier injection portion disposed near a junction area of the first channel41aand the first contact portion42band extending beyond the second gate122.

The carriers provided by photo-generated carrier injection portion have a type different from that of the carriers in the first channel41a, and the carriers in the first channel41aand the carriers in the second channel42ahave the same type.

It should be noted that, the photo-generated carrier injection portion is introduced in the embodiment, so that carriers may be provided in time with a change of a gate voltage of the second gate122, so as to suppress a formation of a non-equilibrium state in the area where the output electrode152is located, reduce an emission number of defect states in a pn junction depletion area at the first contact portion42band the first channel41a, thereby suppressing the dynamic hot carrier effect.

Correspondingly, referring toFIG.8, a display panel1000is further provided according to embodiments of the present disclosure. The display panel1000includes the drive substrate100as in any of the above embodiments and a light emitting element200disposed on the drive substrate100. The light emitting element200is connected to the output electrode152.

The drive substrate100further includes a conductive layer153connected to the output electrode152. The light emitting element200is bonded and connected to the conductive layer153.

In some embodiments, the light emitting element200may be a submillimeter level light emitting diode, a micro light emitting diode, an organic light emitting diode, or the like.

It should be explained that the structure of the drive substrate100of the display panel1000in the embodiments is similar or identical to the structure of the drive substrate100in the above-mentioned embodiments, and will not be repeated here.

For the display panel1000of the embodiments of the present disclosure, in the thin film transistor TFT of the drive substrate100, a structure with double-gate and double-active layer is formed by the first active layer141, the first gate121, the first sub-gate22a, and a part of the second active layer142in an area adjacent to the output electrode152, and a structure with single active layer and top gate is formed by the second sub-gate22band a part of the second active layer142in an area adjacent to the input electrode151. Since the first gate121and the second gate122together control the first channel41aof the first active layer141and the first portion42a1of the second channel42aof the second active layer142, a resistance and a voltage drop of the area are reduced, so that an electric field intensity of the area is weakened during operation, thereby suppressing the movement of the hot carriers and improving the stability of the threshold voltage (Vth) of the thin film transistor TFT.

The drive substrates and display panels according to embodiments of the present disclosure have been described above in detail. In this paper, specific examples are used to illustrate the principle and implementation of the invention. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. Those skilled in the art can make various changes and modifications without departing from the spirit of the present disclosure. Therefore, the described embodiments are not intended to limit the present disclosure.