Semiconductor device and preparation method thereof, and memory apparatus

A semiconductor device, a preparation method thereof and a memory apparatus are provided. The semiconductor device includes a semiconductor substrate on which multiple strip-shaped stacked structures and a sidewall structure covering a periphery of each stacked structure are disposed, and a conductive structure is disposed on a side of the stacked structure far away from the semiconductor substrate. The stacked structure includes a conductor layer disposed on the semiconductor substrate and configured to transmit a data signal, an isolation layer disposed on a side of the conductor layer far away from the semiconductor substrate, a separation layer disposed on a side of the isolation layer far away from the semiconductor substrate and made of a low dielectric constant material, and a dielectric layer disposed on a side of the separation layer far away from the semiconductor substrate and configured to isolate the separation layer from the conductive structure.

BACKGROUND

A Dynamic Random Access Memory (DRAM) is a common semiconductor memory device in a computer, and consists of multiple memory cells. Each of the memory cells usually includes a capacitor and a transistor. A grid of the transistor is connected with a word line, a drain electrode of the transistor is connected with a bit line, a source electrode of the transistor is connected with the capacitor. A voltage signal on the word line may control the transistor to be turned on or turned off, so that the data information stored in the capacitor may be read through the bit line, or the data information may be written into the capacitor through the bit line for storage.

These structures described above result in various parasitic capacitances in the DRAM, and these parasitic capacitances severely influence the use quality and lifetime of a chip.

It should be noted that the information disclosed in the background section is only used to enhance an understanding of the background of the disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art.

SUMMARY

The disclosure relates to the field of semiconductor technologies, and provides a semiconductor device, a preparation method of the semiconductor device, and a memory apparatus.

According to a first aspect of the disclosure, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate. Multiple strip-shaped stacked structures and a sidewall structure covering a periphery of each stacked structure may be disposed on the semiconductor substrate, and a conductive structure may be disposed on a side of the stacked structure far away from the semiconductor substrate.

The stacked structure may include a conductor layer, an isolation layer, a separation layer and a dielectric layer.

The conductor layer may be disposed on the semiconductor substrate and may be configured to transmit a data signal.

The isolation layer may be disposed on a side of the conductor layer far away from the semiconductor substrate.

The separation layer may be disposed on a side of the isolation layer far away from the semiconductor substrate and may be made of a low dielectric constant material.

The dielectric layer may be disposed on a side of the separation layer far away from the semiconductor substrate and may be configured to isolate the separation layer from the conductive structure.

According to a second aspect of the disclosure, a preparation method of a semiconductor device is provided. The preparation method may include the following operations.

A semiconductor substrate may be provided.

A conductor material layer, an isolation material layer, a separation material layer and a dielectric material layer may be sequentially formed on the semiconductor substrate.

The dielectric material layer, the separation material layer, the isolation material layer and the conductor material layer may be etched to form multiple strip-shaped stacked structures.

A sidewall structure may be formed on a periphery of each stacked structure.

A conductive structure may be formed on a side of the stacked structure far away from the semiconductor substrate.

According to a third aspect of the disclosure, a memory apparatus is provided. The memory apparatus may include a semiconductor device. The semiconductor device may include a semiconductor substrate. Multiple strip-shaped stacked structures and a sidewall structure covering a periphery of each stacked structure may be disposed on the semiconductor substrate, and a conductive structure may be disposed on a side of the stacked structure far away from the semiconductor substrate.

The stacked structure may include a conductor layer, an isolation layer, a separation layer and a dielectric layer.

The conductor layer may be disposed on the semiconductor substrate and may be configured to transmit a data signal.

The isolation layer may be disposed on a side of the conductor layer far away from the semiconductor substrate.

The separation layer may be disposed on a side of the isolation layer far away from the semiconductor substrate and may be made of a low dielectric constant material.

The dielectric layer may be disposed on a side of the separation layer far away from the semiconductor substrate and may be configured to isolate the separation layer from the conductive structure.

It should be understood that the above general descriptions and detailed descriptions below are only exemplary and explanatory and not intended to limit the disclosure.

IN THE DRAWINGS

DETAILED DESCRIPTION

Example implementations will now be described more fully with reference to the accompanying drawings. However, the example implementations can be implemented in various forms, and should not be construed as being limited to the embodiments set forth herein. On the contrary, these implementations are provided so that the disclosure will be comprehensive and complete, and will fully convey the concept of the example implementations to those skilled in the art. The same reference numerals in the drawings indicate the same or similar structures, and thus the detailed descriptions thereof are omitted.

In the related art, a parasitic capacitance between Bit Lines (BLs) is widely concerned, but a parasitic capacitance may also be generated between the BL and a conductive structure on the BL. The parasitic capacitance will affect the performance of a semiconductor device, affect an operation speed and a refresh frequency.

An example implementation firstly provides a semiconductor device. Referring toFIG.1, the semiconductor device includes a semiconductor substrate1. Multiple strip-shaped stacked structures6and a sidewall structure71covering a periphery of each stacked structure6are disposed on the semiconductor substrate1, and a conductive structure (not illustrated) is disposed on a side of the stacked structure6far away from the semiconductor substrate1. The stacked structure6includes a conductor layer62, an isolation layer63, a separation layer64and a dielectric layer65. The conductor layer62is disposed on the semiconductor substrate1and configured to transmit a data signal. The isolation layer63is disposed on a side of the conductor layer62far away from the semiconductor substrate1. The separation layer64is disposed on a side of the isolation layer63far away from the semiconductor substrate1and is made of a low dielectric constant material. The dielectric layer65is disposed on a side of the separation layer64far away from the semiconductor substrate1and configured to isolate the separation layer64from the conductive structure.

In the example implementation, word lines3and shallow-trench isolating structures4are disposed in the semiconductor substrate1. The semiconductor substrate1is divided into multiple active regions2by the shallow-trench isolating structures4.

Word line trenches31are provided in the semiconductor substrate1, an intergate dielectric layer32is disposed in each word line trench31, and the inter-gate dielectric layer32covers side walls and a bottom of the word line trench31. A material of the inter-gate dielectric layer32may include, but is not limited to, at least one of silicon oxide or silicon nitride. The inter-gate dielectric layer32may be formed by adopting an atomic layer deposition process, a Plasma chemical vapor deposition process or a rapid thermal oxidation process.

A first conductive layer33and a second conductive layer34are disposed in the word line trench31. The first conductive layer33covers side walls of the inter-gate dielectric layer32and a bottom of the inter-gate dielectric layer32. A gap between inner side walls of the first conductive layer33is fully filled with the second conductive layer34. An upper surface of the first conductive layer33and an upper surface of the second conductive layer34are both lower than an upper surface of the semiconductor substrate1, and the upper surface of the second conductive layer34is higher than the upper surface of the first conductive layer33. A material of the first conductive layer33may include any one of As or B-doped silicon, P or As-doped germanium, W, Ti, TiN or Ru. A material of the second conductive layer34may include any one of W, Ti, Ni, Al or Pt. Additionally, the material of the first conductive layer33is different from the material of the second conductive layer34. The first conductive layer33and the second conductive layer34may be formed by an atomic layer deposition process or a plasma chemical vapor deposition process.

A filling insulation layer35is disposed in the word line trench31. The filling insulation layer35covers the upper surface of the first conductive layer33and the upper surface of the second conductive layer34, and fully fills the word line trench31. A material of the filling insulation layer35may be any proper insulation materials including oxides (such as silicon oxide, aluminum oxide or hafnium oxide), silicon nitride, silicon oxynitride, and/or the like.

Bit line contact trenches8may also be provided on the semiconductor substrate1, and a bit line9is disposed in each bit line contact trench8and protrudes from the bit line contact trench8.

In the example implementation, multiple strip-shaped stacked structures6are disposed on the semiconductor substrate1. A sidewall structure71covers a periphery of each stacked structure6, and the stacked structure6and the sidewall structure71form the bit line9of the semiconductor device.

Specifically, the stacked structure6may include a conductor adhesion layer61, a conductor layer62, an isolation layer63, a separation layer64and a dielectric layer65. The conductor adhesion layer61may be disposed on the semiconductor substrate1. A material of the conductor adhesion layer61may be polysilicon, and a thickness of the conductor adhesion layer is greater than or equal to 60 nm and less than or equal to 70 nm. The conductor layer62is disposed on a side of the conductor adhesion layer61far away from the semiconductor substrate1. A material of the conductor layer62may be titanium, tungsten and/or the like, and a thickness of the conductor layer is greater than or equal to 25 nm and less than or equal to 30 nm. The isolation layer63is disposed on a side of the conductor layer62far away from the semiconductor substrate1. A material of the isolation layer63may be silicon nitride, and a thickness of the isolation layer is greater than or equal to 8 nm and less than or equal to 12 nm, and is preferably 10 nm. The separation layer64is disposed on a side of the isolation layer63far away from the semiconductor substrate1, a material of the separation layer64may be SiLK, and a thickness of the separation layer is greater than or equal to 8 nm and less than or equal to 12 nm, and is preferably 10 nm. The dielectric layer65is disposed on a side of the separation layer64far away from the semiconductor substrate1, a material of the dielectric layer65may be silicon nitride, and a thickness of the dielectric layer is greater than or equal to 120 nm and less than or equal to 160 nm, and is preferably 140 nm.

A dielectric constant of the SiLK is low, and is about 2.6. It is easier to control a pore diameter of the SiLK. By introducing micro voids with a diameter of 2 to 5 nm, and enabling the micro voids to be mutually sealed, a higher mechanical modulus and mechanical strength are achieved. A certain external force may be applied in subsequent processes of Chemico-Mechanical Polishing (CMP), encapsulation operations and the like, the separation layer with high mechanical strength can protect the bit line structure to further protect the whole semiconductor structure. Additionally, the chemical performance of this material is stable, and the stable performance can still be maintained at a high temperature. Therefore, the performance of the semiconductor device cannot be affected even if there is a high-temperature requirement in the subsequent process. Of course, in other example implementations of the disclosure, the material of the separation layer64may also be silicon dioxide, and a dielectric constant of the silicon dioxide is about 3.9. Other low dielectric constant materials can also be used, for example, may be methylsilsesquioxane (MSQ) or porous hydrogen silsesquioxane (HSQ).

In the example implementation, the sidewall structure71is not only disposed on the periphery of the stacked structure6, but also covers a part of the semiconductor substrate1where the stacked structure6is not disposed. The sidewall structure71may cover the entire stacked structure6. In other example implementations of the disclosure, a height of the sidewall structure71is at least higher than a height of the separation layer64, that is, a distance between a side of the sidewall structure71far away from the semiconductor substrate1and the semiconductor substrate1is greater than a distance between the side of the separation layer64far away from the semiconductor substrate1and the semiconductor substrate1, so that the sidewall structure71completely covers the separation layer64, to prevent the separation layer64from being exposed to the subsequent processes. The stacked structure6and the sidewall structure71form the bit line9.

In the example implementation, a conductive structure is disposed on a side of the bit line9far away from the semiconductor substrate1. The conductive structure may include a capacitance structure and a conductive layer. The conductive layer is located on the side of the bit line9far away from the semiconductor substrate1, and the conductive layer is connected to a capacitance contact. The capacitance structure is located on a side of the conductive layer far away from the semiconductor substrate1, and the conductive layer is connected to the capacitance structure to connect the capacitance structure to the capacitance contact.

According to the semiconductor device of the disclosure, the isolation layer63is disposed on the side of the conductor layer62far away from the semiconductor substrate1, the separation layer64is disposed on the side of the isolation layer63far away from the semiconductor substrate1, the dielectric layer65is disposed on the side of the separation layer64far away from the semiconductor substrate1, and the conductive structure is disposed on the side of the dielectric layer65far away from the semiconductor substrate1. Through the isolation layer63, the conductor layer62can be isolated from the separation layer64. Through the dielectric layer65, the separation layer64can be isolated from the conductive structure. The separation layer64is a low dielectric constant material. Through the separation layer64, a parasitic capacitance generated by the conductor layer62and the conductive structure can be effectively reduced, so that the RC delay, crosstalk and power consumption of the semiconductor device can be reduced, and an operation speed, a refresh frequency and the like are prevented from being affected, thereby effectively reducing the impact of the parasitic capacitance on the use quality and lifetime of the semiconductor device.

Further, an example implementation further provides a preparation method of a semiconductor device. Referring toFIG.2, the preparation method of the semiconductor device may include the following operations.

At S10, a semiconductor substrate1is provided.

At S20, a conductor material layer52, an isolation material layer53, a separation material layer54and a dielectric material layer55are sequentially formed on the semiconductor substrate1.

At S30, the dielectric material layer55, the separation material layer54, the isolation material layer53and the conductor material layer52are etched to form multiple strip-shaped stacked structures6.

At S40, a sidewall structure71is formed on a periphery of each stacked structure6.

At S50, a conductive structure is formed on a side of the stacked structure6far away from the semiconductor substrate1.

Each operation of the preparation method of a semiconductor device will be described in detail hereafter.

At S10, a semiconductor substrate1is provided.

In the example implementation, as illustrated inFIG.3, the semiconductor substrate1may include, but is not limited to, a monocrystalline silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate. Additionally, if the semiconductor substrate11is the monocrystalline silicon substrate or the polycrystalline silicon substrate, the semiconductor substrate may also be an intrinsic silicon substrate or a slightly doped silicon substrate, and may further be an N type polycrystalline silicon substrate or a P type polycrystalline silicon substrate.

At S20, a conductor material layer52, an isolation material layer53, a separation material layer54and a dielectric material layer55are sequentially formed on the semiconductor substrate1.

In the example implementation, reference is made toFIG.4.

A conductor adhesion material layer51is formed on the semiconductor substrate1through a Chemical Vapor Deposition (CVD) process. In the CVD process, deposition gas may be one or more of Si2H6, SiH4, PH3or LTO520 (precursor: SiH3N(C3H7)2).

The conductor material layer52is formed on a side of the conductor adhesion material layer51far away from the semiconductor substrate1through a Physical Vapor Deposition (PVD) process, and a target material in the PVD process may use tungsten, titanium, and/or the like.

The isolation material layer53is formed on a side of the conductor material layer52far away from the semiconductor substrate1through a Low Pressure Chemical Vapor Deposition (LPCVD) process or an Atomic layer deposition (ALD) process, and a deposition material is silicon nitride. Main deposition gas is SiCl2H2and NH3.

The separation material layer54is formed on a side of the isolation material layer53far away from the semiconductor substrate1. Specifically, SiLK and n-tetradecane are mixed according to a set proportion to form a mixed solution, the mixed solution is spin-coated, by a spin centrifugation method, onto the side of the isolation material layer53far away from the semiconductor substrate1to form a thin film with a thickness about 10 nm, and the thin film is dried in a protective atmosphere. The protective atmosphere may be nitrogen gas. Of course, helium gas can be used as the protective atmosphere. The set proportion may be that the n-tetradecane accounts for 30% to 50% of the SiLk.

The dielectric material layer55is formed on a side of the separation material layer54far away from the semiconductor substrate1through an LPCVD or Atomic Layer Deposition (ALD) process, and a deposition material is silicon nitride. Main deposition gas is SiCl2H2and NH3.

At S30, the dielectric material layer55, the separation material layer54, the isolation material layer53and the conductor material layer52are etched to form multiple strip-shaped stacked structures6.

In the example implementation, referring toFIG.5, a photoresist layer may be formed on a side of the dielectric material layer55far away from the semiconductor substrate1, a mask plate is disposed on the photoresist layer to expose the photoresist layer, and then a part of the photoresist layer not covered by the mask plate is removed and the remaining part of the photoresist layer is taken as a mask to dry-etch the dielectric material layer55, the separation material layer54, the isolation material layer53, the conductor material layer52and the conductor adhesion material layer51so as to correspondingly form multiple strip-shaped dielectric layers65, separation layers64, isolation layers63, conductor layers62and conductor adhesion layers61, i.e., the multiple strip-shaped stacked structures6are formed.

At S40, a sidewall structure71is formed on a periphery of each stacked structure6.

In the example implementation, referring toFIG.6, a sidewall material layer7may be formed on the semiconductor substrate1and on a side of each stacked structure6far away from the semiconductor substrate1through LPCVD, and additionally, a height of the sidewall material layer7is higher than a height of the dielectric layer65. Then, the sidewall material layer7is etched to remain a part of the sidewall material layer7on side walls of each stacked structure6and a part of the sidewall material layer7on the semiconductor substrate1to form the sidewall structure71, a thickness of the part of the sidewall material layer7on the side walls of each stacked structure6and a thickness of the part of the sidewall material layer7on the semiconductor substrate1are substantially the same, and are greater than or equal to 7 nm and less than or equal to 9 nm. That is, the structural diagram of the semiconductor device as illustrated inFIG.1is formed.

The stacked structure6and the sidewall structure71form the bit line9of the semiconductor device.

At S50, a conductive structure is formed on a side of the stacked structure6far away from the semiconductor substrate1.

In the example implementation, the conductive structure may include a capacitance structure and a conductive layer. The specific structure of the conductive structure has been described in detail above, and is not repeated herein.

Compared with the prior art, the preparation method of the semiconductor device provided by the example implementation of the disclosure achieves the same beneficial effects as the semiconductor device provided by the above example implementations, and the descriptions are not repeated herein.

Further, the present example implementation further provides a memory apparatus. The memory apparatus may include the semiconductor device in any one of the example implementations above. The specific structure of the semiconductor device has been illustrated in detail above, so that the descriptions are not repeated herein.

Compared with the prior art, the memory apparatus provided by the example implementation of the disclosure achieves the same beneficial effects as the semiconductor device provided by the above example implementations, and the descriptions are not repeated herein.

The features, structures, or characteristics described above may be combined in any suitable manner in one or more implementations, with the features discussed in each implementation being interchangeable, if possible. In the above descriptions, various specific details are provided in order to provide a thorough understanding of the implementations of the disclosure. However, it will be recognized by those skilled in the art that the technical solutions of the disclosure may be practiced without one or more of the specific details, or with other methods, components, materials, etc. Under other conditions, well-known structures, materials, or operations are not illustrated or described in detail to avoid obscuring aspects of the disclosure.

As used herein, the term “about” or “approximately” generally means within a 20%, preferably within 10%, and more preferably within 5% of a given value or range. The quantity given herein is an approximate quantity, meaning that the meaning of “about”, “approximately”, “substantially”, and “roughly” may still be implied without particular description.

Although relative terms, such as “upper” and “lower”, are used in the present specification to describe the relative relationship between one component and another component indicated in the drawings, these terms are used in the present specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if a device indicated in the drawings is turned over and inverted, an “upper” component will become a “lower” component. Other relative terms such as “high”, “low”, “top”, “bottom” and the like have similar meanings. When a structure is located “on” other structures, it may mean that the structure is integrally formed on other structures, or the structure is “directly” disposed on other structures, or the structure is “indirectly” disposed on other structures through another structure.

In this specification, the terms “a”, “an”, “the” and “said” are used to indicate the presence of one or more elements/components/etc. The terms “comprise”, “include” and “have” are used in an open-ended inclusive sense and mean that there may be additional elements/components/etc. In addition to the listed elements/components/etc. The terms “first”, “second”, “third” and the like are used merely as labels and are not intended to limit the quantity of objects.

It should be understood that the disclosure shall not limit its application to the detailed structure and the arrangement manner set forth in this specification. The disclosure may have other implementations, and can be practiced and performed in various manners. The above variations and modifications fall within the scope of the disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident in the text and/or drawings. All of these different combinations constitute a number of alternative aspects of the disclosure. The implementations described in this specification illustrate the preferred ways known for practicing the disclosure and will enable those skilled in the art to utilize the disclosure.