GATE STRUCTURES IN SEMICONDUCTOR DEVICES

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming nanostructured channel regions on a fin or sheet base, forming gate openings surrounding the nanostructured channel regions, forming oxide layers on exposed surfaces of the nanostructured channel regions and the fin or sheet base in the gate openings, performing a first doping process on the oxide layers to form doped oxide layers, depositing a first dielectric layer on the doped oxide layers, performing a second doping process on the first dielectric layer to form a doped dielectric layer, and depositing a conductive layer on the doped dielectric layer.

BACKGROUND

With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (finFETs), and gate-all-around (GAA) FETs. Such scaling down has increased the complexity of semiconductor manufacturing processes.

DETAILED DESCRIPTION

GAA FETs can include fin or sheet bases disposed on a substrate, stacks of nanostructured channel regions disposed on the fin or sheet bases, and gate structures surrounding each of the nanostructured channel regions. The gate voltage—the threshold voltage (Vt)—to turn on a GAA FET can depend on the semiconductor material of the nanostructured channel regions and/or the effective work function (EWF) value of the gate structures of the GAA FET. For example, for an n-type GAA FET (“NFET”), reducing the difference between the EWF value of the NFET gate structure and the conduction band energy of the material (e.g., 4.1 eV for silicon (Si) or 3.8 eV for silicon germanium (SiGe)) of the NFET nanostructured channel regions can reduce the NFET threshold voltage. For a p-type GAA FET (“PFET”), reducing the difference between the EWF value of the PFET gate structure and the valence band energy of the material (e.g., 5.2 eV for Si or 4.8 eV for SiGe) of the PFET nanostructured channel regions can reduce the PFET threshold voltage. The EWF values of the gate structures can depend on the thickness and/or material composition of each of the layers of the gate structure. As such, GAA FETs can be manufactured with different threshold voltages by adjusting the thickness and/or material composition of the gate structures.

Due to the increasing demand for multi-functional low power portable devices, there is an increasing demand for GAA FETs with low threshold voltages, such as threshold voltages between about 200 mV and about 400 mV (referred to as “low threshold voltage”), threshold voltages between about 100 mV and about 200 mV (referred to as “ultra-low threshold voltage”), and threshold voltages below about 100 mV (referred to as “extreme-low threshold voltage”). One way to achieve multi-Vt devices with low, ultra-low, and/or extreme-low threshold voltages in GAA FETs can be with different work function metal (WFM) layer thicknesses greater than about 4 nm (e.g., about 5 nm to about 10 nm) in the gate structures. However, the different WFM layer thicknesses can be constrained by the GAA FET gate structure geometries. For example, the thicknesses of the WFM layers can be constrained by the spacing between the nanostructured channel regions of the GAA FETs. And, depositing different WFM layer thicknesses can become increasingly challenging with the continuous scaling down of GAA FETs.

To address the abovementioned challenges, the present disclosure provides example GAA FETs with different gate structures configured to provide different threshold voltages, and example methods of forming such multi-Vt GAA FETs on the same substrate. The example methods form NFETs and PFETs with WFM layers of the same material and of substantially equal thicknesses, and with extreme-low, ultra-low, and/or low threshold voltages, on the same substrate. These example methods can be more cost-effective (e.g., reduce cost by about 20% to about 30%) and time-efficient (e.g., reduce time by about 15% to about 20%) in manufacturing reliable GAA FET gate structures with different threshold voltages than other methods of forming GAA FETs with similar dimensions and threshold voltages on the same substrate. In addition, these example methods can form GAA FET gate structures with much smaller dimensions (e.g., thinner gate stacks) than other methods of forming GAA FETs with similar threshold voltages.

In some embodiments, NFETs and PFETs with different gate structure configurations, but with WFM layers of the same material and of substantially equal thicknesses can be formed on the same substrate to achieve different threshold voltages. The different gate structures can have high-K (HK) gate dielectric layers doped with metal dopants of different types and/or concentrations. The different types and/or concentrations of metal dopants can induce dipoles of different polarities and/or concentrations at interfaces between the HK gate dielectric layers and interfacial oxide (IL) layers (“HK-IL interfaces”). The dipoles of different polarities and/or concentrations result in gate structures with different EWF values. Since EWF values of gate structures correspond to threshold voltage of NFETs and PFETs, gate structures with different EWF values result in NFETs and PFETs with different threshold voltages on the same substrate. Thus, controlling the types and/or concentrations of metal dopants in the HK gate dielectric layers can tune the EWF values of the NFET and PFET gate structures, and as a result can adjust the threshold voltages of the NFETs and PFETs without varying the WFM layer thicknesses. And, forming the NFET and PFET gate structures with WFM layers of the same material can reduce the number of fabrication steps and as a result, reduce device manufacturing cost compared to NFET and PFET gate structures formed with WFM layers of different materials.

In some embodiments, both the NFET and PFET gate structures can be formed with n-type WFM (“nWFM”) layers or p-type WFM (“pWFM”) layers. The nWFM layers can include a metal or a metal-containing material with a work function value closer to a conduction band energy than a valence band energy of a material of the nanostructured channel regions of the NFETs and PFETs. In some embodiments, the nWFM layers can have a work function value less than about 4.5 eV. The pWFM layers can include a metal or a metal-containing material with a work function value closer to a valence band energy than a conduction band energy of a material of the nanostructured channel regions of the NFETs and PFETs. In some embodiments, the pWFM layers can have a work function value equal to or greater than about 4.5 eV.

In some embodiments, when both the NFET and PFET gate structures are formed with pWFM layers in addition to the dipoles at the HK-IL interfaces, the PFETs can be formed to have extreme-low, ultra-low, and/or low threshold voltages. However, additional dipoles of adequate polarity and concentration are formed at interfaces between the IL layers and the nanostructured channel regions (“IL-channel interfaces”) of the NFETs to form the NFETs with extreme-low, ultra-low, and/or low threshold voltages. These additional dipoles can be formed by doping the NFET IL layers with metal dopants of adequate concentrations. In some embodiments, the metal dopants can include lutetium (Lu), scandium (Sc), yttrium (Y), thulium (Tm), or gadolinium (Gd). This additional doping of the NFET IL layers are performed because the work function value of the pWFM layers does not adequately reduce the difference between the EWF value of the NFET gate structures and the conduction band energy of the material of the NFET nanostructured channel regions in order to form the NFETs with extreme-low, ultra-low, and/or low threshold voltages.

On the other hand, in some embodiments, when both the NFET and PFET gate structures are formed with nWFM layers in addition to the dipoles at the HK-IL interfaces, the NFET can be formed to have extreme-low, ultra-low, and/or low threshold voltages. However, additional dipoles of adequate polarity and concentration can be formed at IL-channel interfaces of the PFETs to form the PFETs with extreme-low, ultra-low, and/or low threshold voltages. These additional dipoles can be formed by doping the PFET IL layers with metal dopants of adequate concentrations. This additional doping of the PFET IL layers are performed because the work function value of the nWFM layers does not adequately reduce the difference between the EWF value of the PFET gate structures and the valence band energy of the material of the PFET nanostructured channel regions in order to form the PFET gate structures with extreme-low, ultra-low, and/or low threshold voltages. In some embodiments, the metal dopants can include germanium (Ge), zinc (Zn), antimony (Sb), or tungsten (W).

FIG.1Aillustrates an isometric view of a semiconductor device100with an n-type GAA FET102N (“NFET102N”) and a p-type GAA FET102P (“PFET102P”), according to some embodiments.FIG.1Billustrates a cross-sectional view of NFET102N along line A-A ofFIG.1, according to some embodiments.FIG.1Cillustrates a cross-sectional views of PFET102P along line B-B ofFIG.1, according to some embodiments.FIGS.1B and1Cillustrate cross-sectional views of semiconductor device100with additional structures that are not shown inFIG.1Afor simplicity.FIGS.1D and1Fare enlarged views of regions112A1,112A2, and112A3ofFIG.1Band illustrate different cross-sectional views of regions112A1,112A2, and112A3.FIGS.1E and1Gare enlarged views of regions112B1,112B2, and112B3ofFIG.1Cand illustrate different cross-sectional views of regions112B1,112B2, and112B3.FIGS.1D,1E,1F, and1Gillustrate additional structures that are not shown inFIGS.1B and1Cfor simplicity. The discussion of elements with the same annotations applies to each other, unless mentioned otherwise.

Referring toFIGS.1A-1C, in some embodiments, semiconductor device100can be formed on a substrate104with NFET102N and PFET102P formed on different regions of substrate104. There may be other FETs and/or structures (e.g., isolation structures) formed between NFET102N and PFET102P on substrate104. Substrate104can be a semiconductor material, such as Si, germanium (Ge), SiGe, a silicon-on-insulator (SOI) structure, and a combination thereof. Further, substrate104can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). Semiconductor device100can further include gate spacers114, shallow trench isolation (STI) regions116, etch stop layers (ESLs)117, and interlayer dielectric (ILD) layers118. In some embodiments, gate spacers114, STI regions116, ESLs117, and ILD layers118can include an insulating material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide.

Referring toFIGS.1A and1B, in some embodiments, NFET102N can include (i) a fin or sheet base106N, (ii) source/drain (S/D) regions110N disposed on fin or sheet base106N, (iii) gate structures112N1-112N3disposed on portions of fin or sheet base106N that are not covered by S/D regions110N, and (iv) nanostructured channel regions121N surrounded by gate structures112N1-112N3. Referring toFIGS.1A and1C, in some embodiments, PFET102P can include (i) a fin or sheet base106P, (ii) source/drain (S/D) regions110P disposed on fin or sheet base106P, (iii) gate structures112P1-112P3disposed on portions of fin or sheet base106P that are not covered by S/D regions110P, and (iv) nanostructured channel regions121P surrounded by gate structures112P1-112P3. As used herein, the term “nanostructured” defines a structure, layer, and/or region as having a horizontal dimension (e.g., along an X-and/or Y-axis) and/or a vertical dimension (e.g., along a Z-axis) less than about 100 nm, for example about 90 nm, about 50 nm, about 10 nm, or other values less than about 100 nm. In some embodiments, nanostructured channel regions121can be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructured shapes. In some embodiments, fin or sheet bases106N and106P can include a material similar to substrate104and extend along an X-axis.

In some embodiments, S/D regions110N can include an epitaxially-grown semiconductor material, such as Si, and n-type dopants, such as phosphorus and other suitable n-type dopants. In some embodiments, S/D regions110P can include an epitaxially-grown semiconductor material, such as Si and SiGe, and p-type dopants, such as boron and other suitable p-type dopants.

In some embodiments, nanostructured channel regions121N and121P can include semiconductor materials similar to or different from substrate104. In some embodiments, nanostructured channel regions121N and121P can include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium stannum boron (SiGeSnB), a III-V semiconductor compound, or other suitable semiconductor materials. Though rectangular cross-sections of nanostructured channel regions121N and121P are shown, nanostructured channel regions121N and121P can have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal). In some embodiments, nanostructured channel regions121N and121P can be separated from each other along a Z-axis by a distance of about 8 nm to about 12 nm. In some embodiments, each of nanostructured channel regions121N and121P can have a thickness of about 5 nm to about 8 nm along a Z-axis. In some embodiments, each of nanostructured channel regions121N and121P can have a width of about 15 nm to about 50 nm along an X-axis.

In some embodiments, the portions of gate structures112N1-112N3surrounding nanostructured channel regions121N can be electrically isolated from adjacent S/D regions110N by inner spacers113. Similarly, the portions of gate structures112P1-112P3surrounding nanostructured channel regions121P can be electrically isolated from adjacent S/D regions110P by inner spacers113. Inner spacers113can include a material similar to gate spacers114. In some embodiments, NFET102N and PFET102P can be finFETs and have fin regions (not shown) instead of nanostructured channel regions121N and121P.

In some embodiments, gate metal fill layers128can include a suitable conductive material, such as W, titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), nickel (Ni), metal alloys, and a combination thereof. Insulating capping layers132can protect the underlying conductive capping layers130from structural and/or compositional degradation during subsequent processing of the semiconductor device100. In some embodiments, insulating capping layers132can include a nitride material, such as SiN, and can have a thickness of about 5 nm to about 10 nm for adequate protection of the underlying conductive capping layers130. Conductive capping layers130can provide conductive interfaces between gate metal fill layers128and gate contact structures (not shown) to electrically connect gate metal fill layers128to gate contact structures without forming gate contact structures directly on or within gate metal fill layers128. In some embodiments, conductive capping layers130can include a metallic material, such as W, Ru, Ir, Mo, and a combination thereof, or other suitable metallic materials.

As discussed above, based on the material of WFM layers, NFET or PFET gate structures can have metal dopants in IL layers and dipoles at IL-channel interfaces, which are further described with reference toFIGS.1D,1E,1F, and1G.FIGS.1D and1Eillustrate metal dopant configurations in IL layers122N1-122N3and122P1-122P3, and dipole configurations at IL-channel interfaces N1-N3and P1-P3for gate structures112N1-112N3and112P1-112P3having pWFM layers126.FIGS.2F and1Gillustrate metal dopant configurations in IL layers122N1-122N3and122P1-122P3, and dipole configurations at IL-channel interfaces N1-N3and P1-P3for gate structures112N1-112N3and112P1-112P3having nWFM layers126. In some embodiments, IL layers122N1-122N3and122P1-122P3can include SiO2, silicon germanium oxide (SiGeOx), or germanium oxide (GeO2).

Referring toFIG.1D, IL layers122N1-122N3can further include metal dopants that induce the formation of dipole layers140N with n-type dipoles (N-dipoles) at IL-channel interfaces N1-N3. In some embodiments, dipole layers140N can be disposed in IL layers122N1-122N3and closer to IL-channel interfaces N1-N3, instead of at IL-channel interfaces N1-N3. Each dipole layer140N can provide a flat band voltage shift of about 300 mV to counteract the increase in threshold voltages of gate structures112N1-112N3due to pWFM layers126, which can have a work function value equal to or greater than 4.5 eV. Such work function value of pWFM layers126can increase the difference between the EWF of gate structures112N1-112N3and the conduction band energy (e.g., 4.1 eV for Si or 3.8 eV for SiGe) of nanostructured channel regions121N, thus increasing the threshold voltages of gate structures112N1-112N3.

On the other hand, referring toFIG.1E, the work function value of pWFM layers126can reduce the difference between the EWF of gate structures112P1-112P3and the valence band energy (e.g., 5.2 eV for Si or 4.8 eV for SiGe) of nanostructured channel regions121P, thus reducing the threshold voltages of gate structures112P1-112P3. Thus, gate structures112P1-112P3do not include metal dopants in IL layers122P1-122P3and dipoles at IL-channel interfaces P1-P3.

Referring toFIG.1D, in some embodiments, the concentration of N-dipoles of dipoles layers140N in IL layers122N1-122N3can be substantially equal to each other. In some embodiments, N-dipoles of dipoles layers140N can include metal ions from the metal dopants in IL layers122N1-122N3and oxygen ions from the oxide material of IL layer122N1-122N3. The metal dopants in IL layers122N1-122N3can include a metal with a lower electronegativity than that of a metal (e.g., hafnium (Hf), zirconium (Zr)) in HK gate dielectric layers124N1-124N3. In some embodiments, the metal dopants in IL layers122N1-122N3can include La, Lu, Sc, Y, Tm, or Gd. In some embodiments, the metal dopants in IL layers122N1-122N3can be of the same metal with concentrations substantially equal to each other to induce N-dipoles in dipole layers140N of the same type and with concentrations substantially equal to each other. In some embodiments, the metal dopants can have a dopant concentration profile across IL layers122N1-122N3along a Z-axis, as shown inFIG.1H. The peak concentration of the metal dopants in IL layers122N1-122N3can be closer to top surfaces of IL layers122N1-122N3, as shown inFIG.1H.

Referring toFIG.1G, IL layers122P1-122P3can further include metal dopants that induce the formation of dipole layers140P with p-type dipoles (P-dipoles) at IL-channel interfaces P1-P3. In some embodiments, dipole layers140P can be disposed in IL layers122P1-122P3and closer to IL-channel interfaces P1-P3, instead of at IL-channel interfaces P1-P3. Each dipole layer140P can provide a flat band voltage shift of about 300 mV to counteract the increase in threshold voltages of gate structures112P1-112P3due to nWFM layers126, which can have a work function value less than 4.5 eV. Such work function value of nWFM layers126can increase the difference between the EWF of gate structures112P1-112P3and the valence band energy (e.g., 5.2 eV for Si or 4.8 eV for SiGe) of nanostructured channel regions121P, thus increasing the threshold voltages of gate structures112P1-112P3.

On the other hand, referring toFIG.1F, the work function value of nWFM layers126can reduce the difference between the EWF of gate structures112N1-112N3and the conduction band energy (e.g., 4.1 eV for Si or 3.8 eV for SiGe) of nanostructured channel regions121N, thus reducing the threshold voltages of gate structures112N1-112N3. Thus, gate structures112N1-112N3do not include metal dopants in IL layers122N1-122N3and dipoles at IL-channel interfaces N1-N3.

Referring toFIG.1G, in some embodiments, the concentration of P-dipoles of dipoles layers140P in IL layers122P1-122P3can be substantially equal to each other. In some embodiments, P-dipoles of dipoles layers140P can include metal ions from the metal dopants in IL layers122P1-122P3and oxygen ions from the oxide material of IL layer122P1-122P3. The metal dopants in IL layers122P1-122P3can include a metal with a higher electronegativity than that of a metal (e.g., Hf, Zr) in HK gate dielectric layers124P1-124P3. In some embodiments, the metal dopants in IL layers122P1-122P3can include Ge, Zn, Sb, or W. In some embodiments, the metal dopants in IL layers122P1-122P3can be of the same metal and with concentrations substantially equal to each other to induce P-dipoles in dipole layers140P of the same type with concentrations substantially equal to each other. In some embodiments, the metal dopants can have a dopant concentration profile across IL layers122P1-122P3along a Z-axis, as shown inFIG.1H. The peak concentration of the metal dopants in IL layers122P1-122P3can be closer to top surfaces of IL layers122P1-122P3, as shown inFIG.1H.

Referring toFIGS.1B-1G, in some embodiments, HK gate dielectric layers124N1-124N3and124P1-124P3can include (i) doped HK gate dielectric layer125N1-125N3and125P1-125P3, and (ii) undoped HK gate dielectric layers127disposed on doped HK gate dielectric layer125N1-125N3and125P1-125P3. In some embodiments, doped HK gate dielectric layer125N1-125N3and125P1-125P3and undoped HK gate dielectric layers127can include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2).

Referring toFIGS.1D and1F, doped HK gate dielectric layers125N1-125N3can further include metal dopants that induce the formation of dipole layers142N1-142N3with N-dipoles at HK-IL interfaces N4-N6. In some embodiments, dipole layers142N1-142N3can be disposed in doped HK gate dielectric layer125N1-125N3and closer to HK-IL interfaces N4-N6, instead of at HK-IL interfaces N4-N6. In some embodiments, the metal dopants in doped HK gate dielectric layer125N1-125N3can include rare-earth metals (REMs), such as lanthanum (La), yttrium (Y), cerium (Ce), ytterbium (Yb), and erbium (Er). In some embodiments, N-dipoles of dipole layers142N1-142N3can include metal ions from metal dopants in doped HK gate dielectric layers125N1-125N3and oxygen ions from the high-K material of doped HK gate dielectric layers125N1-125N3.

In some embodiments, doped HK gate dielectric layer125N1-125N3can include metal dopants of the same metal, but with concentrations different from each other to induce N-dipoles in dipole layers142N1-142N3of the same type and with concentrations different from each other. As metal dopant concentration is directly proportional to N-dipole concentration, which is inversely proportional to threshold voltage of an NFET gate structure, (i) doped HK gate dielectric layer125N1has a higher concentration of metal dopants than that in doped HK gate dielectric layers125N2and125N3to form gate structure112N1with a threshold voltage smaller than that of gate structures112N2and112N3, and (ii) doped HK gate dielectric layer125N2has a higher concentration of metal dopants than that in doped HK gate dielectric layer125N3to form gate structure112N2with a threshold voltage smaller than that of gate structure112N3. Thus, threshold voltages across different NFET gate structures (e.g., gate structures112N1-112N3) on the same substrate can be varied with different concentrations of the same polarity dipoles (e.g., N-dipoles). In some embodiments, the metal dopants in doped HK gate dielectric layer125N1-125N3can have a dopant concentration profile across doped HK gate dielectric layer125N1-125N3along a Z-axis, as shown inFIG.11. The peak concentration of the metal dopants in doped HK gate dielectric layer125N1-125N3can be closer to HK-IL interfaces N4-N6, as shown inFIG.1I.

Referring toFIGS.1E and1G, doped HK gate dielectric layers125P1-125P3can further include metal dopants that induce the formation of dipole layers142P1-142P3with P-dipoles at HK-IL interfaces P4-P6. In some embodiments, dipole layers142P1-142P3can be disposed in doped HK gate dielectric layer125P1-125P3and closer to HK-IL interfaces P4-P6, instead of at HK-IL interfaces P4-P6. In some embodiments, the metal dopants in doped HK gate dielectric layer125P1-125P3can include Zn, Ge, Al, Ti, or vanadium (V). In some embodiments, P-dipoles of dipole layers142P1-142P3can include metal ions from metal dopants in doped HK gate dielectric layers125P1-125P3and oxygen ions from the high-K material of doped HK gate dielectric layers125P1-125P3.

In some embodiments, doped HK gate dielectric layer125P1-125P3can include metal dopants of the same metal, but with concentrations different from each other to induce P-dipoles in dipole layers142P1-142P3of the same type and with concentrations different from each other. As metal dopant concentration is directly proportional to P-dipole concentration, which is inversely proportional to threshold voltage of an PFET gate structure, (i) doped HK gate dielectric layer125P3has a higher concentration of metal dopants than that in doped HK gate dielectric layers125P1and125P2to form gate structure112P3with a threshold voltage smaller than that of gate structures112P1and112P2, and (ii) doped HK gate dielectric layer125P2has a higher concentration of metal dopants than that in doped HK gate dielectric layer125P1to form gate structure112P2with a threshold voltage smaller than that of gate structure112P1. Thus, threshold voltages across different PFET gate structures (e.g., gate structures112P1-112P3) on the same substrate can be varied with different concentrations of the same polarity dipoles (e.g., P-dipoles). In some embodiments, the metal dopants in doped HK gate dielectric layer125P1-125P3can have a dopant concentration profile doped HK gate dielectric layer125P1-125P3, as shown inFIG.11. The peak concentration of the metal dopants in doped HK gate dielectric layer125P1-125P3can be closer to HK-IL interfaces P4-P6, as shown inFIG.1I.

In some embodiments, IL layers122N1-122N3and122P1-122P3can have a thickness of about 0.5 nm to about 1 nm and HK gate dielectric layers124N1-124N3and124P1-124P3can have a thickness of about 1.5 nm to about 4 nm. Within these thickness ranges of IL layers122N1-122N3and122P1-122P3and HK gate dielectric layers124N1-124N3and124P1-124P3, adequate electrical isolation between nanostructures channel regions121N and gate structures112N1-112N3and between nanostructures channel regions121P and gate structures112P1-112P3can be provided without compromising device size and manufacturing cost.

FIG.2is a flow diagram of an example method200for fabricating NFET102N and PFET102P with cross-sectional views shown inFIGS.1B-1E, according to some embodiments. For illustrative purposes, the operations illustrated inFIG.2will be described with reference to the example fabrication process for fabricating NFET102N and PFET102P as illustrated inFIGS.3A-22B.FIGS.3A-22Aare cross-sectional views of NFET102N along line A-A ofFIG.1A, andFIGS.3B-22Bare cross-sectional views of PFET102P along line B-B ofFIG.1Aat various stages of fabrication, according to some embodiments. Operations can be performed in a different order or not performed depending on specific applications. It should be noted that method200may not produce a complete NFET102N and PFET102P. Accordingly, it is understood that additional processes can be provided before, during, and after method200, and that some other processes may only be briefly described herein. Elements inFIGS.3A-22Bwith the same annotations as clements inFIGS.1A-1Eare described above.

Referring toFIG.2, in operation205, superlattice structures are formed on fin or sheet bases, and polysilicon structures are formed on the superlattice structures for an NFET and a PFET. For example, as described with reference toFIGS.3A and3B, superlattice structures323N and323P are formed on fin or sheet bases106N and106P, respectively, and polysilicon structures312N and312P are formed on superlattice structures323N and323P, respectively. Superlattice structures323N can include nanostructured layers121N and321arranged in an alternating configuration. Similarly, superlattice structures323P can include nanostructured layers121P and321arranged in an alternating configuration. In some embodiments, nanostructured layers321include materials different from nanostructured layers121N and121P. Nanostructured layers321are also referred to as “sacrificial layers321.” During subsequent processing, polysilicon structures312N and312P and sacrificial layers321can be replaced in a gate replacement process to form gate structures112N1-112N3and112P1-112P3.

Referring toFIG.2, in operation210, S/D regions are formed on the fin or sheet bases. For example as described with reference toFIGS.3A and3B, S/D regions110N and110P are formed on fin structures106N and106P, respectively. In some embodiments, S/D regions110N and110P can be epitaxially grown on fin structures106N and106P. Prior to the formation of S/D regions110N and110P, inner spacers113can be formed in superlattice structures323N and323P, as shown inFIGS.3A and3B. After the formation of S/D regions110N and110P, ESL117and ILD layer118can be formed, as shown inFIGS.3A and3B.

Referring toFIG.2, in operation215, gate openings are formed and IL layers are formed in the gate openings. For example, as described with reference toFIGS.4A and4B, gate openings412N1-412N3and412P1-412P3and IL layers422N1-422N3and122P1-122P3are formed. Gate openings412N1-412N3and412P1-412P3can be formed by removing polysilicon structures312N and312P and sacrificial layers321. IL layers422N1-422N3are formed in gate openings412N1-412N3and IL layers122P1-122P3are formed in gate openings412P1-412P3. In some embodiments, IL layers422N1-422N3and122P1-122P3can be formed by performing a wet oxidation process on the exposed surfaces of nanostructured channel regions121N and121P and fin or sheet bases106N and106P in gate openings412N1-412N3and412P1-412P3. The wet oxidation process can oxidize top portions of nanostructured channel regions121N and fin or sheet base106N to form IL layers422N1-422N3and can oxidize top portions of nanostructured channel regions121P and fin or sheet base106P to form IL layers122P1-122P3.

In some embodiments, the wet oxidation process can include (i) using a mixture (referred to as “Piranha solution”) of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) at a temperature of about 60° C. to about 100° C., (ii) using an ozone (O3) solution of O3in DI water, (iii) using a mixture of ammonium hydroxide (NH4OH) and H2O2, and/or (iv) using a mixture of hydrochloric acid (HCl) and H2O2. In some embodiments, the wet oxidation process can be followed by a densification process, which can include performing an anneal process on the structures ofFIGS.4A and4Bat a temperature of about 300° C. to about 550° C.

The subsequent processing on the structures ofFIGS.4A and4Bin operations220-240are described with reference toFIGS.5A-22B.FIGS.5A-22Aare enlarged views of regions112A1-112A3ofFIG.4A, andFIGS.5B-22Bare enlarged views of regions112B1-112B3ofFIG.4B.

Referring toFIG.2, in operation220, a doping process is performed on the IL layers of the NFET. For example, as described with reference toFIGS.5A-6B, a doping process is performed to dope IL layers422N1-422N3with metal dopants that induce N-dipoles of dipole layers140N. The doping process can include sequential operations of (i) depositing a dopant source layer544on IL layers422N1-422N3and122P1-122P3, as shown inFIGS.5A and5B, (ii) selectively removing portions of dopant source layer544on IL layers122P1-122P3using lithographic patterning and etching processes, as shown inFIG.6B, (iii) performing a drive-in anncal process on the structures ofFIGS.6A and6Bto implant metal dopants into IL layers422N1-422N3to form doped IL layers122N1-122N3, as shown inFIG.6A, and (iv) removing dopant source layer544from the structures ofFIG.6Ato form the structures ofFIG.7A.

The deposition of dopant source layer544can include depositing a metal oxide, which includes a metal with a lower electronegativity than that of a metal (e.g., Hf, Zr) in HK gate dielectric layers124N1-124N3. In some embodiments, depositing the metal oxide can include depositing lutetium oxide (LuO), scandium oxide (ScO), yttrium oxide (Y203), thulium oxide (Tm203), or gadolinium oxide (Gd203) on IL layers422N1-422N3and122P1-122P3in a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In some embodiments, depositing the metal oxide can include depositing the metal oxide with a thickness of about0.5nm to about1nm on IL layers422N1-422N3and122P1-122P3to adequately perform the doping process without compromising device manufacturing cost.

The drive-in anneal process can implant metal dopants into IL layers422N1-422N3through diffusion of metal atoms from dopant source layer544into IL layers422N1-422N3. The drive-in anneal process can include annealing the structures ofFIGS.6A and6Bat a temperature of about 500° C. to about 700° C. for a time period of about 10 seconds to about 30 seconds in an ambient of nitrogen.FIG.23shows a metal concentration profile across dopant source layer544and IL layers422N1-422N3along a Z-axis prior to the drive-in anneal process. After the drive-in anneal process and the diffusion of metal atoms from dopant source layer544to IL layers422N1-422N3, metal dopants in doped IL122N1-122N3can have the dopant concentration profile ofFIG.1H.

In some embodiments, portions of IL layers122P1-122P3can be etched during the etching of dopant source layer544from the structures ofFIG.6B. As a result, IL layers122P1-122P3can be reduced from thicknesses T1-T3(shown inFIG.5B) to thicknesses T1*-T3* (shown inFIG.6B). An oxidation process can be performed on the structures ofFIGS.6A and6Bafter the removal of dopant source layer544from the structures ofFIG.6Ato regrow IL layers122P1-122P3to thicknesses T1-T3, as shown inFIG.7B. In some embodiments, the oxidation process can include the wet oxidation process described in operation215. In some embodiments, thicknesses of IL layers122N1-122N3and122P1-122P3can be substantially equal to each other after the oxidation process.

Referring toFIG.2, in operation225, a first HK gate dielectric layer is deposited in the gate openings of the NFET and the PFET. For example, as described with reference toFIGS.8A and8B, a first HK gate dielectric layer with HK gate dielectric layer portions (“HK portions”)825N1-825N3and825P1-825P3are deposited on IL layers122N1-122N3and122P1-122P3in gate openings412N1-412N3and412P1-412P3. These HK portions825N1-825N3and825P1-825P3also extend along sidewalls of gate openings412N1-412N3and412P1-412P3, which are not shown for simplicity. In subsequent processing, HK portions825N1-825N3and825P1-825P3form doped HK gate dielectric layers125N1-125N3and125P1-125P3. The deposition of the first HK dielectric layer can include depositing a layer of high-k dielectric material, such as HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, and ZrSiO2with a thickness of about 1 nm to about 2 nm.

Referring toFIG.2, in operation230, a doping process is performed on the first HK gate dielectric layer. For example, as described with reference toFIGS.9A-21B, a doping process is performed to dope HK portions825N1-825N3in gate openings412N1-412N3and to dope HK portions825P1-825P3in gate openings412P1-412P3at a same time. HK portions825N1-825N3are doped with a first type metal dopants that induce N-dipoles of dipole layers142N1-142N3and HK portions825P1-825P3are doped with a second type metal dopants that induce P-dipoles of dipole layers142P1-142P3at a same time. The first and second type metal dopants are different from each other.

The doping process can include sequential operations of (i) depositing a dopant source layer946on HK portions825N1-825N3and825P1-825P3, as shown inFIGS.9A and9B, (ii) selectively removing portions of dopant source layer946on HK portions825N2-825N3and825P1-825P3using lithographic patterning and etching processes to form the structures ofFIGS.10A and10B, (iii) depositing a dopant source layer1146on dopant source layer946and HK portions825N2-825N3and825P1-825P3, as shown inFIGS.11A and11B, (iv) selectively removing portions of dopant source layer1146on HK portions825N3and825P1-825P3using lithographic patterning and etching processes to form the structures ofFIGS.12A and12B, (v) depositing a dopant source layer1346on dopant source layer1146and HK portions825N3and825P1-825P3, as shown inFIGS.13A and13B, (vi) selectively removing portions of dopant source layer1346on HK portions825P1-825P3using lithographic patterning and etching processes to form the structures ofFIGS.14A and14B, (vii) depositing a dopant source layer1548on dopant source layer1346and HK portions825P1-825P3, as shown inFIGS.15Aand15B, (viii) selectively removing portions of dopant source layer1548on HK portions825P1-825P2and dopant source layer1346using lithographic patterning and etching processes to form the structures ofFIGS.16A and16B, (ix) depositing a dopant source layer1748on dopant source layers1346and1548and HK portions825P1-825P2, as shown inFIGS.17A and17B, (x) selectively removing portions of dopant source layer1748on HK portions825P1and dopant source layer1346using lithographic patterning and etching processes to form the structures ofFIGS.18A and18B, (xi) depositing a dopant source layer1948on dopant source layers1346and1748and HK portion825P1, as shown inFIGS.19A and19B, (xii) selectively removing portions of dopant source layer1948on dopant source layer1346using lithographic patterning and etching processes to form the structures ofFIGS.20A and20B, (xiii) performing a drive-in anncal process on the structures ofFIGS.20A and20Bto form doped HK portions2025N1-2025N3and2025P1-2025P3, (xiv) removing dopant source layers946,1146,1346,1548,1748, and1948from the structures ofFIGS.20A and20Bto form the structures ofFIGS.21A and21B, and (xv) performing an anneal process on the structures ofFIGS.21A and21B.

ThoughFIGS.9A-20Bshow forming the dopant source layers of NFET102N prior to forming the dopant source layers of PFET102P, the formation of dopant source layers of NFET102N and PFET102P can be performed in any order. In some embodiments, dopant source layers1548,1748, and1948can be formed on HK portions825P1-825P3prior to forming dopant source layers946,1146, and1346on HK portions825N1-825N3.

The deposition of each dopant source layers946,1146, and1346can include depositing an REM oxide, such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), cerium oxide (CeO2), ytterbium oxide (Yb2O3), and erbium oxide (Er2O3) in a CVD process or an ALD process. In some embodiments, depositing the REM oxide for each dopant source layers946,1146, and1346can include depositing the REM oxide with a thickness of about 1 nm to about 3 nm to adequately dope HK portions825N1-825N3without compromising device manufacturing cost. In some embodiments, dopant source layers946,1146, and1346can have the same REM oxide.

The deposition of each dopant source layers1548,1748, and1948can include depositing a metal oxide, such as zinc oxide (ZnO), GeO2, aluminum oxide (Al2O3), titanium oxide (TiO2), and vanadium oxide (V2O3) in a CVD process or an ALD process. In some embodiments, depositing the metal oxide for each dopant source layers1548,1748, and1948can include depositing the metal oxide with a thickness of about 1 nm to about 3 nm to adequately dope HK portions825P1-825P3without compromising device manufacturing cost. In some embodiments, dopant source layers1548,1748, and1948can have the same metal oxide.

Different number of dopant source layers are deposited on HK portions825N1-825N3for doping HK portions825N1-825N3with different concentrations of the first type metal dopants to induce different concentrations of N-dipoles in dipole layers142N1-142N3. For example, the stack of three dopant source layers946,1146, and1346can implant a higher concentration of the first type metal dopants into HK portion825N1than that implanted from the stack of two dopant source layers946and1146into HK portion825N2and from one dopant source layer946into HK portion825N3. Similarly, different number of dopant source layers are deposited on HK portions825P1-825P3for doping HK portions825P1-825P3with different concentrations of the second type metal dopants to induce different concentrations of P-dipoles in dipole layers142P1-142P3. For example, the stack of three dopant source layers1548,1748, and1948can implant a higher concentration of the second type metal dopants into HK portion825P3than that implanted from the stack of two dopant source layers1748and1948into HK portion825P2and from one dopant source layer1948into HK portion825P1.

The drive-in anneal process can implant the first type metal dopants into (i) HK portion825N1through diffusion of metal atoms from dopant source layers946,1146, and1346into HK portion825N1to form doped HK portion2025N1, (ii) HK portion825N2through diffusion of metal atoms from dopant source layers1146and1346into HK portion825N2to form doped HK portion2025N2, and (iii) HK portion825N3through diffusion of metal atoms from dopant source layers1346into HK portion825N3to form doped HK portion2025N3. At the same time, the drive-in anneal process can implant the second type metal dopants into (i) HK portion825P3through diffusion of metal atoms from dopant source layers1548,1748, and1948into HK portion825P3to form doped HK portion2025P3, (ii) HK portion825P2through diffusion of metal atoms from dopant source layers1748and1948into HK portion825P2to form doped HK portion2025P2, and (iii) HK portion825P1through diffusion of metal atoms from dopant source layers1948into HK portion825P1to form doped HK portion2025P1.

The drive-in anneal process can include annealing the structures ofFIGS.20Aand20B at a temperature of about 500° C. to about 700° C. for a time period of about 10 seconds to about 30 seconds in an ambient of nitrogen. Prior to the drive-in anneal process, the metals of dopant source layers946,1146,1346,1548,1748, and1948can have a concentration profile, as shown inFIG.24, across dopant source layers946,1146,1346,1548,1748, and1948, HK portions825N1-825N3and825P1-825P3, and IL layers122N1-122N3and122P1-122P3along a Z-axis. After the drive-in anneal process and the diffusion of first and second type metal atoms into HK portions825N1-825N3and825P1-825P3, metal dopants in doped HK portions2025N1-2025N3and2025P1-2025P3can have the dopant concentration profile ofFIG.11. In some embodiments, the anneal process performed after the removal of dopant source layers946,1146,1346,1548,1748, and1948can be similar to the drive-in anneal process.

Referring toFIG.2, in operation235, a second HK gate dielectric layer is deposited in the gate openings of the NFET and the PFET. For example, as described with reference toFIGS.22A and22B, a second HK gate dielectric layer2227is deposited on HK portions825N1-825N3and825P1-825P3in gate openings412N1-412N3and412P1-412P3. The deposition of second HK gate dielectric layer2227can include depositing a layer of high-k dielectric material, such as HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, and ZrSiO2with a thickness of about 0.5 nm to about 1 nm. In subsequent processing, second HK gate dielectric layer2227form undoped HK gate dielectric layers127N1-127N3and127P1-127P3.

Referring toFIG.2, in operation240, a pWFM layer is deposited on the second HK gate dielectric layer and a gate metal fill layer is deposited on the pWFM layer. For example, as described with reference toFIGS.22A and22B, a pWFM layer2226is deposited on second HK gate dielectric layer2227and a gate metal fill layer2228is deposited on pWFM layer2226. The deposition of pWFM2226can include depositing a metal layer, a metal nitride layer, or a metal-alloy layer with a work function value equal to or greater than 4.5 eV, such as TIN, TiSiN, Ti-Au alloy, Ti-Cu alloy, TaN, TaSiN, Ta-Au alloy, Ta-Cu, MON, and W. The deposition of gate metal fill layer2228can be followed by a chemical mechanical polishing (CMP) process and an etching process on gate structures112N1-112N3and112P1-112P3to form HK gate dielectric layers124N1-124N2and124P1-124P2, pWFM layers126, and gate metal fill layers128, as shown inFIGS.1B-1E. The etching process can be followed by the formation of conductive capping layers130and insulating capping layers132.

FIG.25is a flow diagram of an example method2500for fabricating NFET102N and PFET102P with cross-sectional views shown inFIGS.1B-1C and1F-1G, according to some embodiments. For illustrative purposes, the operations illustrated inFIG.25will be described with reference to the example fabrication process for fabricating NFET102N and PFET102P as illustrated inFIGS.3A,8A-22B, and26A-29B.FIGS.3A,8A-22A, and26A-29Aare cross-sectional views of NFET102N along line A-A ofFIG.1A, andFIGS.3B,8B-22B, and26B-29Bare cross-sectional views of PFET102P along line B-B ofFIG.1Aat various stages of fabrication, according to some embodiments. Operations can be performed in a different order or not performed depending on specific applications. It should be noted that method2500may not produce a complete NFET102N and PFET102P. Accordingly, it is understood that additional processes can be provided before, during, and after method2500, and that some other processes may only be briefly described herein. Elements inFIGS.26A-29Bwith the same annotations as elements inFIGS.1A-1E and3A-22Bare described above.

Referring toFIG.25, operations2505-2510are similar to operations205-210ofFIG.2. After operation2510, structures similar to the structures ofFIGS.3A and3Bare formed. The subsequent processing on the structures ofFIGS.3A and3Bin operation2515is described with reference toFIGS.26A-26B.

Referring toFIG.25, in operation2515, gate openings are formed and IL layers are formed in the gate openings. For example, as described with reference toFIGS.26A and26B, gate openings412N1-412N3and412P1-412P3and IL layers122N1-122N3and2622P1-2622P3are formed. IL layers122N1-122N3are formed in gate openings412N1-412N3and IL layers2622P1-2622P3are formed in gate openings412P1-412P3. In some embodiments, IL layers122N1-122N3and2622P1-2622P3can be formed by performing the wet oxidation process, as described in operation215, on the exposed surfaces of nanostructured channel region121N and121P and fin or sheet bases106N and106P in gate openings412N1-412N3and412P1-412P3. The wet oxidation process can oxidize top portions of nanostructured channel region121N and fin or sheet base106N to form IL layers122N1-122N3and can oxidize top portions of nanostructured channel region121P and fin or sheet base106P to form IL layers2622P1-2622P3.

The subsequent processing on the structures ofFIGS.26A and26Bin operation220is described with reference toFIGS.27A-29B.FIGS.27A-29Aare enlarged views of regions112A1-112A3ofFIG.26A, andFIGS.27B-29Bare enlarged views of regions112B1-112B3ofFIG.26B.

Referring toFIG.25, in operation2520, a doping process is performed on the IL layers of the PFET. For example, as described with reference toFIGS.27A-29B, a doping process is performed to dope IL layers2622P1-2622P3with metal dopants that induce P-dipoles of dipole layers140P. The doping process can include sequential operations of (i) depositing a dopant source layer2744on IL layers122N1-122N3and2622P1-2622P3, as shown inFIGS.27A and27B, (ii) selectively removing portions of dopant source layer2744on IL layers122N1-122N3using lithographic patterning and etching processes, as shown inFIG.28A, (iii) performing a drive-in anneal process on the structures ofFIGS.28A and28Bto implant metal dopants into IL layers2622P1-2622P3to form doped IL layers122P1-122P3, as shown inFIG.28B, and (iv) removing dopant source layer2744from the structures ofFIG.28Bto form the structures ofFIG.29B.

The deposition of dopant source layer2744can include depositing a metal oxide, which includes a metal with a higher electronegativity than that of a metal (e.g., Hf, Zr) in HK gate dielectric layers124P1-124P3. In some embodiments, depositing the metal oxide can include depositing GeO2, germanium nitride (GeN), ZnO, zinc nitride (ZnN), antimony oxide (SbO), antimony nitride (SbN), tungsten oxide (WO), or tungsten nitride (WN) on IL layers122N1-122N3and2622P1-2622P3in a CVD process or an ALD process. In some embodiments, depositing the metal oxide can include depositing the metal oxide with a thickness of about 0.5 nm to about 1 nm on IL layers122N1-122N3and2622P1-2622P3to adequately perform the doping process without compromising device manufacturing cost.

The drive-in anneal process can implant metal dopants into IL layers2622P1-2622P3through diffusion of metal atoms from dopant source layer2744into IL layers2622P1-2622P3. The drive-in anneal process can include annealing the structures ofFIGS.28A and28Bat a temperature of about 500° C. to about 700° C. for a time period of about 10 seconds to about 30 seconds in an ambient of nitrogen.

In some embodiments, portions of IL layers122N1-122N3can be etched during the etching of dopant source layer2744from the structures ofFIG.27A. As a result, IL layers122N1-122N3can be reduced from thicknesses T1-T3(shown inFIG.27A) to thicknesses T1*-T3* (shown inFIG.28A). An oxidation process can be performed on the structures ofFIGS.28A and28Bafter the removal of dopant source layer2744from the structures ofFIG.28Bto regrow IL layers122N1-122N3to thicknesses T1-T3, as shown inFIG.29A. In some embodiments, the oxidation process can include the wet oxidation process described in operation215. In some embodiments, thicknesses of IL layers122N1-122N3and122P1-122P3can be substantially equal to each other after the oxidation process.

Referring toFIG.25, operations2525-2540are similar to operations225-240, respectively, ofFIG.2, except in operation2540an nWFM layer is deposited on second HK gate dielectric layer2227instead of pWFM layer2226. Operations2525-2540are performed on the structures ofFIGS.29A and29Bto form the structures ofFIGS.1B-1C and1F-1G.

The present disclosure provides example GAA FETs (e.g., GAA FET102N and102P) with different gate structures (e.g., gate structures112N1-112N3and112P1-112P3) configured to provide different threshold voltages, and example methods (e.g., methods200and2500) of forming such multi-Vt GAA FETs on the same substrate (e.g., substrate104). The example methods form NFETs (e.g., NFET102N) and PFETs (e.g., PFET102P) with WFM layers (e.g., WFM layers126) of the same material and of substantially equal thicknesses, and with extreme-low, ultra-low, and/or low threshold voltages, on the same substrate. These example methods can be more cost-effective (e.g., reduce cost by about 20% to about 30%) and time-efficient (e.g., reduce time by about 15% to about 20%) in manufacturing reliable GAA FET gate structures with different threshold voltages than other methods of forming GAA FETs with similar dimensions and threshold voltages on the same substrate. In addition, these example methods can form GAA FET gate structures with much smaller dimensions (e.g., thinner gate stacks) than other methods of forming GAA FETs with similar threshold voltages.

In some embodiments, NFETs and PFETs with different gate structure configurations (e.g., gate structures112N1-112N3and112P1-112P3), but with WFM layers (e.g., WFM layers126) of the same material and of substantially equal thicknesses can be formed on the same substrate to achieve different threshold voltages. The different gate structures can have HK gate dielectric layers (e.g., doped HK gate dielectric layers125N1-125N3and125P1-125P3) doped with metal dopants of different types and/or concentrations that induce N-dipoles and P-dipoles of different concentrations at HK-IL interfaces (e.g., HK-IL interfaces N4-N5and P4-P5). The N-dipoles and P-dipoles of different concentrations at HK-IL interfaces result in gate structures with different threshold voltages on the same substrate. Thus, controlling the types and/or concentrations of metal dopants in the HK gate dielectric layers can tune the threshold voltages of the NFETs and PFETs without varying the WFM layer thicknesses. And, forming the NFET and PFET gate structures with WFM layers of the same material can reduce the number of fabrication steps and as a result, reduce device manufacturing cost compared to NFET and PFET gate structures formed with WFM layers of different materials.

In some embodiments, both the NFET and PFET gate structures can be formed with nWFM layers or pWFM layers. In some embodiments, when both the NFET and PFET gate structures are formed with pWFM layers (e.g., pWFM layers126ofFIGS.1D-1E) in addition to the dipoles at the HK-IL interfaces, the PFETs can be formed to have extreme-low, ultra-low, and/or low threshold voltages. However, additional N-dipoles are formed at IL-channel interfaces (e.g., IL-channel interfaces N1-N3) of the NFETs to form the NFETs with extreme-low, ultra-low, and/or low threshold voltages. These additional dipoles can be formed by doping the NFET IL layers (e.g., IL layers122N1-122N3) with metal dopants that include a lower electronegativity than that of a metal (e.g., Hf, Zr) in the NFET HK gate dielectric layers (e.g., HK gate dielectric layers124N1-124N3). In some embodiments, the metal dopants in the NFET IL layers can include La, Lu, Sc, Y, Tm, or Gd.

On the other hand, in some embodiments, when both the NFET and PFET gate structures are formed with nWFM layers (e.g., nWFM layers126ofFIGS.1F-1G) in addition to the dipoles at the HK-IL interfaces, the NFET can be formed to have extreme-low, ultra-low, and/or low threshold voltages. However, additional P-dipoles are formed at IL-channel interfaces (e.g., IL-channel interfaces P1-P3) of the PFETs to form the PFETs with extreme-low, ultra-low, and/or low threshold voltages. These additional dipoles can be formed by doping the PFET IL layers with metal dopants that include a higher electronegativity than that of a metal (e.g., Hf, Zr) in the PFET HK gate dielectric layers (e.g., HK gate dielectric layers124P1-124P3). In some embodiments, the metal dopants can include Ge, Zn, Sb, or W.

In some embodiments, a method includes forming nanostructured channel regions on a fin or sheet base, forming gate openings surrounding the nanostructured channel regions, forming oxide layers on exposed surfaces of the nanostructured channel regions and the fin or sheet base in the gate openings, performing a first doping process on the oxide layers to form doped oxide layers, depositing a first dielectric layer on the doped oxide layers, performing a second doping process on the first dielectric layer to form a doped dielectric layer, and depositing a conductive layer on the doped dielectric layer.

In some embodiments, a method includes forming first and second nanostructured channel regions on first and second fin or sheet bases, respectively, forming first and second gate openings surrounding the first and second nanostructured channel regions, respectively, forming a first undoped oxide layer on exposed surfaces of the first nanostructured channel region in the first gate opening, forming a doped oxide layer on exposed surfaces of the second nanostructured channel region in the second gate opening, depositing a first dielectric layer with a first dielectric portion on the undoped oxide layer and a second dielectric portion the doped oxide layer, performing a doping process on the first and second dielectric portions to form first and second doped dielectric portions, respectively, and depositing a conductive layer on the first and second doped dielectric portions.

In some embodiments, a semiconductor device includes a substrate, a nanostructured channel region disposed on the substrate, and a gate structure. The gate structure includes a doped oxide layer surrounding the nanostructured channel region, a doped dielectric layer disposed on the doped oxide layer, a first dipole layer disposed between the doped oxide layer and the nanostructured channel region, and a second dipole layer disposed between the doped oxide layer and the doped dielectric layer.