Ceramic electronic device

A ceramic electronic device includes a multilayer chip having a plurality of dielectric layers and a plurality of internal electrode layers that are stacked, and having a first main face and a second main face, and a plurality of external electrodes, the plurality of external electrodes being spaced from each other, each of the plurality of external electrodes being connected to a part of the plurality of internal electrode layers, the plurality of external electrodes having a predetermined area in the planar view. On at least one of the first main face and the second main face, at least one of the plurality of external electrodes has an extension portion extending along a side of the rectangular shape toward at least one of external electrodes adjacent to the at least one of the plurality of external electrodes.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2019-232828, filed on Dec. 24, 2019, the entire contents of which are incorporated herein by reference.

FIELD

A certain aspect of the present invention relates to a ceramic electronic device.

BACKGROUND

Recently, electronic devices such as mobile phones are downsized and thinned. Therefore, substrates mounted on the electronic devices are downsized and thinned. And, ceramic electronic devices such as multilayer ceramic capacitors mounted on a substrate is downsized and thinned (for example, see Japanese Patent Application Publication No. 2019-24077).

SUMMARY OF THE INVENTION

However, transverse intensity of the ceramic electronic device having a low height may be degraded because of occurrence of crack.

According to an aspect of the present invention, there is provided a ceramic electronic device including: a multilayer chip having a plurality of dielectric layers and a plurality of internal electrode layers that are stacked, and having a first main face and a second main face that face each other in a stacking direction and have a rectangular shape in a planar view; and a plurality of external electrodes each of which extends from the first main face to the second main face at each of corners of the rectangular shape, the plurality of external electrodes being spaced from each other, each of the plurality of external electrodes being connected to a part of the plurality of internal electrode layers, the plurality of external electrodes having a predetermined area in the planar view, wherein, on at least one of the first main face and the second main face, at least one of the plurality of external electrodes has an extension portion extending along a side of the rectangular shape of the at least one of the first main face and the second main face toward at least one of external electrodes adjacent to the at least one of the plurality of external electrodes.

DETAILED DESCRIPTION

A description will be given of an embodiment with reference to the accompanying drawings.

(First embodiment) A description will be given of a basic structure of a multilayer ceramic capacitor100.FIG.1illustrates an oblique view of the multilayer ceramic capacitor100in accordance with a first embodiment.FIG.2illustrates a cross sectional view taken along a line A-A ofFIG.1.FIG.3illustrates a cross sectional view taken along a line B-B ofFIG.1. As illustrated inFIG.1toFIG.3, the multilayer ceramic capacitor100has a multilayer chip10having a board shape, and four external electrodes20ato20d.

As illustrated inFIG.2andFIG.3, the multiyear chip10has a structure in which each of dielectric layers11having a ceramic material acting as a dielectric substance and each of internal electrode layers12are alternately stacked. InFIG.3, edges of the internal electrode layers12are alternately exposed to the external electrode20aand the external electrode20d. Thus, each of the internal electrode layers12is alternately electrically connected to each of the external electrode20aand the external electrode20d. The internal electrode layer12connected to the external electrode20ais also connected to the external electrode20c. The internal electrode layer12connected to the external electrode20dis also connected to the external electrode20b. Therefore, the external electrode20aand the external electrode20chave the same pole. The external electrode20band the external electrode20dhave the same pole. In a multilayer structure of the dielectric layers11and the internal electrode layers12, outermost layers in the stacking direction are two of the internal electrode layers12. Cover layers13covers an upper face and a lower face of the multilayer structure. A main component of the cover layers13is a ceramic material. For example, the main component of the cover layer13is the same as that of the ceramic material of the dielectric layers11.

The multilayer chip10has an upper face40aand a lower face40bin the stacking direction which are two main faces. The upper face40afaces the lower face40b. The multilayer chip10has side faces50ato50dwhich are four faces other than the upper face40aand the lower face40b. The side face50afaces the side face50c. The side face50bfaces the side face50d.

A length of the multilayer ceramic capacitor100in a direction which is vertical to the stacking direction of the dielectric layers11and the internal electrode layers12and is in parallel with the side faces50aand50cis a length L. A width of the multilayer ceramic capacitor100in a direction which is vertical to the stacking direction and is in parallel with the side faces50band50dis a width W. A thickness of the multilayer ceramic capacitor100is a thickness T. In a planar view of the multilayer ceramic capacitor100viewed along the stacking direction, the multilayer chip10has a rectangular shape. The length L and the width W correspond to lengths of two sides of the rectangular shape adjacent to each other.

In a planar view which is viewed along the stacking direction, the upper face40aand the lower face40bhave a rectangular shape. The thickness T of the multilayer ceramic capacitor100in the stacking direction is, for example, 150 μm or less, 120 μm or less, 90 μm or less, or 75 μm or less. The thickness of the multilayer chip10in the stacking direction is, for example, 90 μm or less, 70 μm or less, or 50 μm or less. The minimum thickness of the multilayer chip10in the stacking direction is 30 When the thickness of the multilayer chip10is 30 μm or more and 50 μm or less, the multilayer chip10has a small size in the thickness direction and has sufficiently large transverse intensity. The length L of the multilayer ceramic capacitor100in the stacking direction is, for example, 1.7 mm, 1.2 mm, and 0.6 mm. The width W is, for example, 1.7 mm, 1.2 mm, and 0.6 mm. A ratio of one of the length L and the width W with respect to the thickness T is about 54:46 to 95:5. A ratio L/W is, for example, 0.80 or more and 1.20 or less.

The external electrode20aextends to the upper face40a, the lower face40band the side faces50aand50b, on a corner portion formed by the upper face40a, the lower face40band the side faces50aand50b. The external electrode20bextends to the upper face40a, the lower face40band the side faces50band50c, on a corner portion formed by the upper face40a, the lower face40band the side faces50band50c. The external electrode20cextends to the upper face40a, the lower face40band the side faces50cand50d, on a corner portion formed by the upper face40a, the lower face40band the side faces50cand50d. The external electrode20dextends to the upper face40a, the lower face40band the side faces50dand50a, on a corner portion formed by the upper face40a, the lower face40band the side faces50dand50a. The external electrodes20ato20dare spaced from each other. In the embodiment, the external electrodes20ato20dhave a predetermined area (for example, a rectangular shape or a square shape) in the planar view viewed along the stacking direction.

FIG.4illustrates a multilayer structure of the internal electrode layers12. The leftmost figure ofFIG.4is a plan view of the upper face40aand includes the external electrodes20ato20d. The rightmost figure ofFIG.4is a perspective view of the lower face40band includes the external electrodes20ato20d. Between the leftmost figure and the rightmost figure, each figure from the internal electrode layer12on the side of the upper face40ato the internal electrode layer12on the side of the lower face40bis illustrated, from left to right.

As illustrated inFIG.4, in the multilayer chip10, each of first internal electrode layers12and each of second internal electrode layers12are alternately stacked through each of the dielectric layers11. The first internal electrode layer12has an extraction portion12aexposed to a corner formed by the side face50aand the side face50band an extraction portion12cexposed to a corner formed by the side face50cand the side face50d. The second internal electrode layer12has an extraction portion12bexposed to a corner formed by the side face50band the side face50cand an extraction portion12dexposed to a corner formed by the side face50dand the side face50a. In the first internal electrode layer12, only the extraction portion12aand the extraction portion12care exposed to the side faces of the multilayer chip10. In the second internal electrode layer12, only the extraction portions12band12dare exposed to the side faces of the multilayer chip10.

With the structure, the external electrode20aand the external electrode20cact as electrodes of a first polarity. The external electrode20band the external electrode20dact as electrodes of a second polarity.

A main component of the internal electrode layers12is a base metal such as nickel (Ni), copper (Cu), tin (Sn) or the like. The internal electrode layers12may be made of a noble metal such as platinum (Pt), palladium (Pd), silver (Ag), gold (Au) or alloy thereof. The dielectric layers11are mainly composed of a ceramic material that is expressed by a general formula ABO3and has a perovskite structure. The perovskite structure includes ABO3-αhaving an off-stoichiometric composition. For example, the ceramic material is such as BaTiO3(barium titanate), CaZrO3(calcium zirconate), CaTiO3(calcium titanate), SrTiO3(strontium titanate), Ba1-x-yCaxSryTi1-zZrzO3(0≤x≤1, 0≤y≤1, 0≤z≤1) having a perovskite structure.

FIG.5illustrates a cross sectional view of the external electrode20a.FIG.5illustrates a partial cross sectional view taken along a line B-B ofFIG.1. InFIG.5, hatching indicating a cross section is omitted. As illustrated inFIG.5, the external electrode20ahas a structure in which a plated layer is formed on a base layer. For example, the external electrode20ahas a structure in which a Cu-plated layer22, a Ni-plated layer23and a Sn-plated layer24are formed on a base layer21. Each plated layer is not limited. Another plated layer such as an Au-plated layer may be further provided. The base layer21is, for example, a sputtered film of a conductive metal such as Cu, Ti or the like. InFIG.5, the external electrode20ais illustrated. The external electrodes20bto20dhave the same structure as that of the external electrode20a.

In the multilayer ceramic capacitor having the low-height structure, crack may occur. For example, crack may occur from a position between a first external electrode and a second external electrode adjacent to the first external electrode to a position between the first external electrode and a third external electrode adjacent to the first external electrode. InFIG.6, in the planar view of the multilayer ceramic capacitor100viewed along the stacking direction, crack occurs from the vicinity of the external electrode20aon a side between the external electrode20aand the external electrode20bto the vicinity of the external electrode20con a side between the external electrode20band the external electrode20c. When crack occurs, the transverse intensity of the multilayer ceramic capacitor may be degraded. And so, the multilayer ceramic capacitor100has a structure for suppressing the occurrence of the crack.

FIG.7AandFIG.7Billustrate details of the external electrodes20ato20d. An upper figure ofFIG.7Aillustrates a plan view of the multilayer ceramic capacitor100viewed along the stacking direction. A lower figure ofFIG.7Aillustrates a side view of the multilayer ceramic capacitor100.FIG.7Billustrates another example of the side view of the multilayer ceramic capacitor100.

For example, as illustrated inFIG.7A, the external electrode20ahas a rectangular shape, in a planar view viewed along the stacking direction. In the rectangular shape, a length in a direction of the length L is referred to as E1, and a length in a direction of the width W is referred to as E2.

Moreover, the external electrode20ahas an extension portion20a1which extends along a side corresponding to the side face50atoward the external electrode20d. The extension portion20a1contacts the side corresponding to the side face50a. Moreover, the external electrode20ahas an extension portion20a2which extends along a side corresponding to the side face50btoward the external electrode20b. The extension portion20a2contacts the side corresponding to the side face50b. That is, the external electrode20ahas extension portions extending along sides of a rectangular shape of the multilayer chip10toward the external electrodes20band20dadjacent to the external electrode20a. A length of the extension portion extending along the side is referred to as a length Rx. A length of the extension portion extending toward the side (vertical to the side) is referred to as a length Ry. A distance between the extension portions of the two external electrodes adjacent to each other in the side is referred to as a distance G.

As illustrated inFIG.7B, in the side face50a, the extension portion20a1extends to the lower face40b. Similarly, in the side face50b, the extension portion20a2extends to the lower face40b. That is, the external electrode20ahas extension portions extending toward the external electrodes20band20dadjacent to the external electrode20a, in the side faces of the multilayer chip10.

As illustrated inFIG.7B, the extension portion20a1may be broken on the way between the upper face40aand the lower face40b. Alternatively, the extension portion20a1may have a narrower width on the way between the upper face40aand the lower face40b. In this case, it is preferable that the extension portion20a1extends toward the external electrode20dnear the upper face40aand the lower face40b, and is broken on the way between the upper face40aand the lower face40b. Alternatively, it is preferable that the extension portion20a1extends toward the external electrode20dnear the upper face40aand the lower face40b, and has a narrower width on the way between the upper face40aand the lower face40b.

The external electrodes20bto20dhave the same structure as that of the external electrode20a. That is, each of the external electrodes20bto20dhas extension portions extending along sides of a rectangular shape of the multilayer chip10toward two external electrodes adjacent to each of the external electrodes20bto20d. The extension portions of the external electrodes20bto20dmay extend from the upper face40ato the lower face40b, on the side face of the multilayer chip10. The extension portions of the case may be broken on the way or may have a narrower width on the way, in the planar view against the side face.

In the planar view of the multilayer ceramic capacitor100viewed along the stacking direction, the shape of the extension portion of the external electrode is not limited. As illustrated inFIG.7A, the extension portion may be recessed toward the side. As illustrated inFIG.8A, the extension portion may project from the side to an inner side of the planar view of the multilayer ceramic capacitor100. InFIG.8A, the extension portion has a fan-shape. Alternatively, as illustrated inFIG.8B, the extension portion may have a triangle shape without a curvature, in the planar view. Alternatively, as illustrated inFIG.8C, the extension portion may have a rectangular shape in the planar view of the multilayer ceramic capacitor100.

In the embodiment, the strength of the multilayer ceramic capacitor100is improved because the extension portion extends along the side in the planar view of the multilayer chip from the external electrode, compared to a case where the extension portion is not formed. Therefore, the occurrence of the crack may be suppressed. For example, the extension portion is formed on the pathway of the crack ofFIG.6and is vertical to the pathway (in the direction of Rx). Therefore, the occurrence of the crack may be suppressed. It is therefore possible to improve the transverse strength of the multilayer ceramic capacitor100. When the extension portion extends to the side face of the multilayer chip10, the strength may be further improved.

When the length Rx and the length Ry are small, the extension portion may not necessarily have a sufficiently large length. In this case, it may not necessarily possible to sufficiently suppress the occurrence of the crack. And so, it is preferable that the length Rx and the length Ry have a lower limit. For example, it is preferable that the length Rx is 5 μm or more. It is more preferable that the length Rx is 20 μm or more. It is still more preferable that the length Rx is 70 μm or more. It is preferable that the length Ry is 5 μm or more. It is more preferable that the length Ry is 20 μm or more. It is still more preferable that the length Ry is 70 μm or more. It is possible to measure the length Rx and the length Ry by treating an inflection point of a circumference line of the external electrode toward an adjacent external electrode, as a starting point of the extension portion.

When the length Rx is large, short may occur between the external electrodes because of a solder bridge during mounting the multilayer ceramic capacitor on a substrate. And so, it is preferable that the distance G has a lower limit. For example, it is preferable that the distance G is 50 μm or more. It is more preferable that the distance G is 100 μm or more. It is still more preferable that the distance G is 180 μm or more.

When the extension portions extending from the external electrodes are thin, sufficient strength may not be necessarily achieved. And so, it is preferable that the thickness of the extension portions has a lower limit. For example, it is preferable that the thickness of the extension portion is 2 μm or more. It is more preferable that the thickness is 5 μm or more. It is still more preferable that the thickness is 10 μm or more.

In the embodiment, each of the four external electrodes20ato20dhas each of the extension portions. However, the structure is not limited. At least one of the four external electrodes20ato20dhas the extension portion. In the embodiment, the two extension portions of the external electrode extend to the two adjacent external electrodes. However, the structure is not limited. At least one of extension portions may extend to one of the two adjacent external electrodes.

Alternatively, the external electrodes20ato20dmay not necessarily extends to two sides of the multilayer chip10forming one corner. For example, the external electrode may extend to only one of the two sides forming one corner. InFIG.9, although the external electrode20aextends to the side corresponding to the side face50a, the external electrode20adoes not extend to the side corresponding to the side face50b. That is, in the rectangular shape of the planar view of the multilayer chip10viewed along the stacking direction, each of the external electrodes20ato20dis arranged on each of four corners divided by perpendicular bisectors (dotted lines ofFIG.9) of the sides. And, each of the external electrodes20ato20dextends to only one of two sides. And, the internal electrode layer12does not extend to the side where the external electrode is not formed. In this case, when the external electrode has the extension portion, the strength of the multilayer ceramic capacitor100is improved. It is therefore possible to suppress the occurrence of the crack. In the planar view of the multilayer ceramic capacitor100, each of the external electrodes20ato20dmay have other shapes as illustrated inFIG.10AtoFIG.10C. In the examples ofFIG.10AtoFIG.10C, the external electrodes20ato20dhave the extraction portion described above.

Next, a description will be given of a manufacturing method of the multilayer ceramic capacitor100.FIG.11illustrates the flow of the manufacturing methods of the multilayer ceramic capacitor100.

(Making process of raw material powder) A dielectric material for forming the dielectric layers11is prepared. The dielectric material includes a main component ceramic of the dielectric layers11. Generally, the A site element and the B site element are included in the dielectric layers11in a sintered phase of grains of ABO3. For example, BaTiO3is tetragonal compound having a perovskite structure and has a high dielectric constant. Generally, BaTiO3is obtained by reacting a titanium material such as titanium dioxide with a barium material such as barium carbonate and synthesizing barium titanate. Various methods can be used as a synthesizing method of the ceramic structuring the dielectric layers11. For example, a solid-phase method, a sol-gel method, a hydrothermal method or the like can be used. The embodiment may use any of these methods.

Additive compound may be added to the obtained ceramic powder, in accordance with purposes. The additive compound may be an oxide of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium) or a rare earth element (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium), or an oxide of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium) and Si (silicon), or glass.

In the embodiment, it is preferable that ceramic particles structuring the dielectric layer11are mixed with compound including additives and are calcined in a temperature range from 820 degrees C. to 1150 degrees C. Next, the resulting ceramic particles are wet-blended with additives, are dried and crushed. Thus, ceramic powder is obtained. It is preferable that an average particle diameter of the ceramic powder is 50 nm to 300 nm from a viewpoint of reduction of the thickness of the dielectric layers11. The grain diameter may be adjusted by crushing the resulting ceramic powder as needed. Alternatively, the grain diameter of the resulting ceramic power may be adjusted by combining the crushing and classifying.

(Stacking process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the resulting dielectric material and wet-blended. With use of the resulting slurry, a dielectric green sheet is printed on a base material by, for example, a die coater method or a doctor blade method, and then dried.

Next, metal conductive paste for forming an internal electrode is applied to the surface of the dielectric green sheet by screen printing or gravure printing. The metal conductive paste includes an organic binder. Thus, a pattern for forming an internal electrode layer is provided. As co-materials, ceramic particles are added to the metal conductive paste. A main component of the ceramic particles is not limited. However, it is preferable that the main component of the ceramic particles is the same as that of the dielectric layer11.

Then, the dielectric green sheets are alternately stacked while the base material is peeled. For example, a total number of the staked dielectric green sheets is 100 to 500.

After that, a cover sheet to be the cover layer13is cramped on the multilayer structure of the dielectric green sheets. And another cover sheet to be the cover layer13is cramped under the multilayer structure. Thus, a ceramic multilayer structure is obtained. After that, the binder is removed from the ceramic multilayer structure in N2atmosphere of 250 degrees C. to 500 degrees C.

(Firing process) The resulting ceramic multilayer structure is fired for 10 minutes to 2 hours in a reductive atmosphere having an oxygen partial pressure of 10−7to 10−10atm in a temperature range of 1100 degrees C. to 1300 degrees C. In this manner, each compound is sintered. Thus, the multilayer ceramic capacitor100is obtained.

(Re-oxidation process) After that, the re-oxidation process is performed in N2gas atmosphere in a temperature range of 600 degrees C. to 1000 degrees C.

(Forming process of external electrode) Next, a mask is provided on a region other than the external electrodes20ato20d. After that, the base layer21is formed by a sputtering method. Another method such as vapor deposition method, a spraying method or the like for forming a thin film may be used. After that, the Cu-plated layer22, the Ni-plated layer23and the Sn-plated layer24may be formed on the base layer21by plating in this order.

In the embodiments, the multilayer ceramic capacitor is described as an example of ceramic electronic devices. However, the embodiments are not limited to the multilayer ceramic capacitor. For example, the embodiments may be applied to another electronic device such as varistor or thermistor.

Examples

The multilayer ceramic capacitors in accordance with the embodiment were made and the property was measured.

(Examples 1 to 15) The multilayer ceramic capacitors100were made. The multilayer ceramic capacitors100had a 0606 shape (L=0.6 mm, W=0.6 mm). The thickness of the multilayer chip10was 70 μm. The thickness T after the plating was 90 μm. E1=E2=200 μm. The shapes of the external electrodes were the shapes ofFIG.7A. In the example 1, the length Rx was 5 to 10 μm, and the length Ry was 5 to 10 μm. In the example 2, the length Rx was 5 to 10 μm, and the length Ry was 20 to 25 μm. In the example 3, the length Rx was 5 to 10 μm, and the length Ry was 70 to 75 μm. In the example 4, the length Rx was 15 to 20 μm, and the length Ry was 5 to 10 μm. In the example 5, the length Rx was 15 to 20 μm, and the length Ry was 20 to 25 μm. In the example 6, the length Rx was 15 to 20 μm, and the length Ry was 70 to 75 μm. In the example 7, the length Rx was 30 to 35 μm, and the length Ry was 5 to 10 μm. In the example 8, the length Rx was 30 to 35 μm, and the length Ry was 20 to 25 μm. In the example 9, the length Rx was 30 to 35 μm, and the length Ry was 70 to 75 μm. In the example 10, the length Rx was 55 to 60 μm, and the length Ry was 5 to 10 μm. In the example 11, the length Rx was 55 to 60 μm, and the length Ry was 20 to 25 μm. In the example 12, the length Rx was 55 to 60 μm, and the length Ry was 70 to 75 μm. In the example 13, the length Rx was 70 to 75 μm, and the length Ry was 5 to 10 μm. In the example 14, the length Rx was 70 to 75 μm, and the length Ry was 20 to 25 μm. In the example 15, the length Rx was 70 to 75 μm, and the length Ry was 70 to 75 μm. The conditions other than the length Rx and the length Ry were common among the examples 1 to 15.

(Comparative example) In the comparative example, Rx=Ry=0. That is, in the comparative example, the external electrodes did not have any extension portions. Other conditions were the same as those of the example 1.

With respect to each of the examples 1 to 15 and the comparative example, 1000 samples were made. Each of the samples was subjected to the transverse intensity test. With respect to each of the samples, it was confirmed whether crack occurred or not after the transverse intensity test. With respect to the examples 1 to 15 and the comparative example, a ratio of the samples determined that the crack occurred with respect to the 1000 samples was measured as a crack occurrence rate.

The transverse intensity was measured with respect to each of the examples 1 to 15 and the comparative example.FIG.12illustrates the crack occurrence rate and the transverse intensity ratio. InFIG.12, the horizontal axis indicates the length Rx. The left vertical axis indicates the transverse intensity ratio (a ratio on a presumption that the transverse intensity of the comparative example was 1). The right vertical axis indicates the crack occurrence rate. The transverse intensity ratio of the length Rx was calculated from the average value of three different Ry values.

As illustrated inFIG.12, the crack occurrence rates of the examples 1 to 15 were smaller than that of the comparative example. It is thought that this was because the extension portion was formed from the external electrode, and the strength was improved. When the length Rx and the length Ry got larger, the crack occurrence rates got smaller. It is thought that this was because when the length Rx and the length Ry were large, the extension portion was also large and the strength was improved. And, when the crack occurrence rate got smaller, the transverse intensity got larger.