An ultrasound method and apparatus can include: transducer elements arranged in a sub-array for generating analog signals based on a return signal detected by the transducer elements during a receive interval; analog delay lines including individual delays unique to each of the transducer elements and calculated based on a linear delay slope for delaying the analog signals; an analog to digital converter for converting the analog signals to a digital signal; a digital beamformer with a digital delay based on one portion of the linear delay slope for delaying the digital signal; and a profile control register containing depth bits corresponding to multiple points for updating the linear delay slope during the receive interval to adjust for the multiple points within an image line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This claims priority benefit to all common subject matter of U.S. Provisional Patent Application Ser. No. 62/150,802 filed Apr. 21, 2015. The content of this application is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This disclosure relates to ultrasound sub-arrays, more particularly to dynamic focus and apodization of ultrasound receiver sub-arrays.

BACKGROUND

The rapidly advancing technology for medical imaging devices is a hallmark of modern health services that is improving the lives of many. The rapidly growing market for ultrasound devices represents one of the largest potential market opportunities for next generation medical imaging.

These devices have unique attributes that have significant impacts on manufacturing integration, in that they must be generally small, power efficient, and operate at high speed and they must be produced in high volumes at relatively low cost.

As an extension of the medical imaging industry, the ultrasound industry segment has witnessed ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace. Future medical imaging systems will be more capable, have higher resolution, use less power, and operate at higher speed, while being manufactured at lower cost than today.

There have been many approaches to addressing the advanced manufacturing requirements of medical imaging devices and many industry road maps have identified significant gaps between the current medical imaging technologies and customer demands. One approach taken in ultrasound imaging technologies is to transmit acoustic energy into a patient's body and receive the reflected acoustic signals with independent transducer elements.

The transducer elements are typically arranged as an array of piezoelectric transducers that typically range from sixty-four transducer elements to over one hundred-twenty-eight transducer elements. The transducer elements convert the received acoustic energy into electrical signals. In a traditional ultrasound system, the signals from each of the transducer elements are amplified and converted from an analog signal to a digital signal.

Once the signals from the transducer are converted into a digital signal, a digital beamformer is used to interpolate, dynamically delay and sum the digital signals. Interpolating, delaying, and summing are used to dynamically focus and steer the receive beam over a receive interval in order to create an image line.

In addition to focusing and steering the receive beam, the beamformer also apodizes, or weighs, the signals from each transducer element as a function of time during the receive interval. Apodization can provide a constant F#, which is focal length divided by aperture. The aperture being the distance spanned by active transducer elements.

Apodization can further provide the ability to window the signals using a windowing function, such as a raised cosine function, a Hamming function, or a Hanning function. Windowing the signal is used to reduce sidelobes of the signal.

This approach is large and excessively power hungry at least because the signal from each transducer element was converted from an analog signal to a digital signal with an analog to digital converter (ADC) for each signal. This required one ADC for each signal, or upwards of sixty-four ADCs.

An alternative approach implemented sub-arrays of the transducer elements and combined some of the processing of the signals. The sub-array architecture differed from the independent transducer element architecture, described above, in that some of the signals could be grouped and partially delayed and summed while in an analog domain before the signal is converted to digital.

The transducer elements used in the sub-array architecture are commonly adjacent to each other. Because of this, the maximum delay required to focus the signals across the transducer elements in the sub-array is limited to a delay that can be achieved using an analog technique.

The analog signals are delayed and summed to produce a beamformed sub-array output. In many approaches the analog delays are fixed producing a fixed focus which compromises image quality.

In other approaches, the analog delays can be changed during the receive interval to maintain dynamic focus. The beamformed sub-array output is then converted to digital in an ADC. The outputs, of multiple ADCs for multiple sub-arrays, are then digitally delayed, and digitally summed to complete the focusing.

The advantages to this approach are that the analog delay can be accomplished using significantly less power and in a smaller space than by using ADCs for each signal and doing all the beamforming digitally. The number of power hungry ADCs is reduced by the number of channels in the sub-array.

This approach, however, only provided a partial solution in that communication of delay information proved a major limitation. The limitation arose due to a need to supply significant delay information to a receive beamformer integrated circuit (IC) during the receive interval or during the time in between imaging lines (when the signals are not being received).

It has been shown that IC to IC communication activity in the receiver needs to be avoided as switching logic has proven to produce both radiated and conducted RF signals that are picked up by the receiver and produce image artifacts. Alternately, writing significant delay information to the IC in between imaging lines is problematic as it increases the time in between image lines and decreases the image frame rate to unacceptable levels.

Another problem with this approach arose when attempting to “step” or “walk” the aperture across the available transducer elements. The imaging aperture is typically a contiguous number of transducer elements that is less than the total number of available transducer elements.

As an illustrative example, the total number of transducer elements may be one hundred-twenty-eight, while the imaging aperture could consist of only thirty-two transducer elements. With a thirty-two transducer element aperture, for each image line in an image frame, the system transmits and receives on thirty-two of the total one hundred-twenty-eight transducer elements.

In order to image multiple lines to create an image, the aperture is stepped across the available transducer elements by dropping one transducer element from one side of the aperture and adding another transducer element to the other side. In this way, the aperture is walked across the available transducer elements for each successive image line.

With a receiver having the transducer elements arranged in a sub-array architecture, stepping the aperture across the available elements in this fashion is problematic. As the imaging aperture is walked across the available transducer elements the alignment of the sub-arrays within the aperture will shift from line to line as the aperture includes partial sub-arrays.

This creates many problems. One of which is the inability of the system to dynamically apodize during the receive interval in the digital domain. That is, this approach cannot maintain the same F# during the receive interval by dynamically increasing the receive aperture digitally. A further problem is that it is shown to cause slight shifts in focus from line to line in the near field that will repeat every four lines and will most likely be visible as an artifact in the image.

Thus, a need remains for smaller, more efficient, and more effective dynamic focusing and apodizing ultrasound receivers. Solutions to these problems have been long sought but prior developments have not taught or suggested any adequate solutions and, thus, solutions to these problems have long eluded those skilled in the art.

SUMMARY

A sub-array receiver beamformer system and methods, enabling effective and efficient dynamic focusing and apodization for phased array and linear transducers, are disclosed that require significantly less power, memory, size, and complexity. The sub-array receiver beamformer system and methods can include: transducer elements arranged in a sub-array for generating analog signals based on a return signal detected by the transducer elements during a receive interval; analog delay lines including individual delays unique to each of the transducer elements and calculated based on a linear delay slope for delaying the analog signals; an analog to digital converter for converting the analog signals to a digital signal; a digital beamformer with a digital delay based on one portion of the linear delay slope for delaying the digital signal; and a profile control register containing depth bits corresponding to multiple points for updating the linear delay slope during the receive interval to adjust for the multiple points within an image line.

It has been discovered that embodiments of the sub-array receiver beamformer system can maintain receive focus by using a limited number of linear delay profiles across the channels of each sub-array that are updated as a function of time. The required focusing delay profiles can be applied during receive intervals and stored in the device using minimal memory for each of the image lines for a full imaging frame eliminating the need to write to the device during the receive interval or transferring a significant amount of data in between imaging lines.

It has been further discovered that embodiments of the sub-array receiver beamformer system can enable down stream digital dynamic apodization by implementing input channel switching to maintain the same relative position of sub-arrays within the active imaging aperture as the elements are walked across the transducer. This allows digital dynamic apodization in the digital domain on the outputs of each sub-array. It also allows identical focusing from line to line eliminating artifacts and also allows the same focusing data to be used on4consecutive lines.

Other contemplated embodiments can include objects, features, aspects, and advantages in addition to or in place of those mentioned above. These objects, features, aspects, and advantages of the embodiments will become more apparent from the following detailed description, along with the accompanying drawings.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration, embodiments in which the sub-array receiver beamformer may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the sub-array receiver beamformer.

The sub-array receiver beamformer is described in sufficient detail to enable those skilled in the art to make and use the sub-array receiver beamformer and provide numerous specific details to give a thorough understanding of the sub-array receiver beamformer; however, it will be apparent that the sub-array receiver beamformer may be practiced without these specific details. The sub-array receiver beamformer is described with regard to a four channel sub-array with a four-to-one multiplexer for descriptive clarity only and is not intended to be so limited unless expressly claimed.

In order to avoid obscuring the sub-array receiver beamformer, some well-known system configurations are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs.

Referring now toFIG. 1, therein is shown a block diagram of ultrasound receiver components100. The ultrasound receiver components100are shown including transducer elements102and sub-array receiver beamformer ICs104coupled to post sub-array receiver electronics106with a cable108.

It is contemplated that the transducer elements102and the sub-array receiver beamformer ICs104can be located within a transducer probe while the post sub-array receiver electronics106can be located remotely. Alternatively, it is contemplated that the transducer elements102, the sub-array receiver beamformer ICs104, and the post sub-array receiver electronics106can be arranged within a transducer probe.

The transducer elements102are shown arranged in a64channel array. The transducer elements102are coupled to the sub-array receiver beamformer ICs104and can be grouped in sub-arrays110of four transducer elements102. The sub-array receiver beamformer ICs104can be two32channel beamformer ICs coupled together.

The sub-array receiver beamformer ICs104can include sub-array beamformer outputs112that pass through the cable108. The sub-array beamformer outputs112are depicted as sixteen sub-array beamformer outputs112, one for each of the sub-arrays110that has been sampled, delayed, and summed by the sub-array receiver beamformer ICs104.

The sub-array beamformer outputs112can be connected from the sub-array receiver beamformer ICs104to the post sub-array receiver electronics106. The post sub-array receiver electronics106can include a post sub-array receiver114coupled to a digital beamformer116.

It is contemplated that the post sub-array receiver114can be a16channel receiver and is contemplated to include low noise amplifiers, variable gain amplifiers, and ADCs. The digital beamformer116is contemplated to provide digital delays to the signals from the sub-array beamformer outputs112in the digital domain.

Further it is contemplated that the digital beamformer116can have a resolution of 1/16 of a wavelength (λ). λ can be the inverse of the transducer elements102center frequency (F0), that is 1/F0.

Referring now toFIG. 2, therein is shown a block diagram of a sub-array receiver beamformer200. The sub-array receiver beamformer200can be a component or functional block within the sub-array receiver beamformer ICs104ofFIG. 1.

It is contemplated that each of the sub-array receiver beamformer ICs104can include8of the sub-array receiver beamformers200, one sub-array receiver beamformer200for each of the sub-arrays110ofFIG. 1. The sub-array receiver beamformer200is shown having four inputs202corresponding to the four transducer elements102ofFIG. 1of the sub-arrays110.

The sub-array receiver beamformer200is further depicted having one summed beamformed output204. The inputs202are shown coupled to variable gain low noise amplifiers (VGLNAs206).

The VGLNAs206can buffer the input signals from the transducer elements102and amplify them sufficiently to match the available dynamic range of an analog delay line208. It is contemplated that the analog delay line208can include four channels210corresponding to a single four transducer element sub-array.

It is contemplated that the analog delay line208can be implemented using analog random access memory (RAM). The analog delay line208using the analog RAM can result in a high dynamic range programmable sampled analog delay line with a maximum delay of 1.5λ and a focus resolution of λ/16. It has been discovered that implementing the analog delay line208with the analog RAM enables dynamic focusing of the signals from the transducer elements102, across the sub-arrays110, which can be achieved using simplified programmable delay profiles that are changed at programmable times during the receive interval.

The analog RAM of the analog delay line208can be used to provide the delays to each of the channels210and can be implemented as sampled capacitors, which can be sampled at a rate sufficient to provide the λ/16 resolution. The maximum delay provided by the analog RAM of the analog delay line208can be dependent on the depth of the analog RAM and can determine the maximum F# and steering angle for the acoustic beam that can be supported.

As an illustrative example, a maximum delay of 1.5λ could be sufficient for a wide variety of transducers and could result in a focus resolution of λ/16. To achieve the maximum delay of 1.5λ, the analog RAM depth should be24samples, that is24samples of the analog RAM at a λ/16 sample rate would result in a 1.5λ delay.

Five profile bits can therefore be used to set the analog RAM depth for each of the channels210in the analog delay line208to control the delay profile for each of the sub-arrays110. The delay profile can be used to determine the individual delays for each of the channels210, which can be communicated from the sub-array delay controller212to the analog delay line208.

The VGLNAs206are depicted as dedicated to one of the inputs202. The VGLNAs206are coupled to a sub-array aperture shift multiplexer214. The sub-array aperture shift multiplexer214can be coupled between the VGLNAs206and the analog delay line208.

As will be discussed below with regard toFIG. 11, in one contemplated embodiment, the sub-array aperture shift multiplexer214can be coupled to the outputs of the VGLNAs206for seven of the transducer elements102with VGLNA outputs216. The sub-array aperture shift multiplexer214further includes a shift0218and a shift1220input for shifting an aperture and the sub-arrays110across the transducer elements102.

In one contemplated embodiment the sub-array receiver beamformer200including the VGLNAs206, the sub-array aperture shift multiplexer214, the analog delay line208, and the sub-array delay controller212are dedicated to one of the sub-arrays110. The sub-array receiver beamformer ICs104can include common elements that can be common for all the sub-array receiver beamformers200on the sub-array receiver beamformer ICs104.

The common elements can include an output gain controller222, a time gain controller224, and a depth counter226. The time gain controller224can be coupled to and control the VGLNAs206. The depth counter226can be coupled to the time gain controller222and can increment a count at a multiple of the F0 of the transducer elements102.

The depth counter226can further be coupled to the sub-array delay controller212. The shift0218and the shift1220inputs to the sub-array aperture shift multiplexer214can be common for the sub-array receiver beamformer ICs104along with inputs for a serial peripheral interface (SPI228), a 4xF0 clock230, a line number232, a line type234, and a 16xF0 clock236.

The 4xF0 clock230can be an input to the depth counter226and the sub-array delay controller212. The depth counter226can further have a line start238and a reset240as inputs.

Referring now toFIG. 3, therein is shown a block diagram of the sub-array delay controller212ofFIG. 2. The sub-array delay controller212is shown coupled to the depth counter226common to all the sub-arrays110ofFIG. 1.

The depth counter226is depicted having the line start238, the reset240, and the 4xF0 clock230as inputs. The sub-array delay controller212is shown having a digital comparator302coupled to the depth counter226.

The sub-array delay controller212is further shown having an initial slope control304. The initial slope control304can be an address generator for pointing to a specific delay profile control register306within a delay profile control memory308using the line number232as an input.

The delay profile control register306can be used to control dynamic delay profile adjustments. Each of the delay profile control registers306can contain 17 bits, 12 depth bits that determine the depth for a specific delay profile, and 5 profile bits that determine which of up to 32 delay profiles will be applied at that depth.

It is contemplated that the 32 channel sub-array receiver beamformer ICs104ofFIG. 1can include a total of 32,768 of the delay profile control registers306, assuming 32 delay profile control registers306per line and sufficient memory for up to 256 unique lines. That is, each of the sub-array delay controllers212assigned to a sub-array110can contain a total of 8192 delay profile control registers306.

It is further contemplated that each of the sub-arrays110can have 32 of the delay profile control registers306assigned to a single image line. The line number232is contemplated to point to these 32 delay profile control registers306for the image line and the sub-array110.

The 12 depth bits of the delay profile control registers306can be used to identify when, during the receive interval, the delay profile should be updated. It is contemplated that the 12 depth bits of the delay profile control registers306can be output from the delay profile control memory308and can be compared against the output of the depth counter226within the digital comparator302.

It has been discovered that programming the delay profile control memory308using the SPI228can be sped up by providing the delay profile control registers306, for each image line, with a separate address on the SPI228, and writing directly into the delay profile control registers306eliminating the need to address each of the delay profile control registers306separately. As a result, the number of addresses necessary to address the delay profile control registers306could be reduced to 1024 for every delay profile control register306within the sub-array receiver beamformer ICs104. Each of the addresses can represent 32 resisters, 17 bits in length, leaving the data word for each of the addresses 544 bits long.

In one contemplated embodiment, the output of the digital comparator302can be fed into a digital adder310. The digital adder310can be coupled between the initial slope control304and the delay profile control memory308.

The digital adder310can increment through the delay profile control registers306that are pointed to during the receive interval. The delay profile control register306that is being pointed to will have the 12 depth bits corresponding to the 5 profile bits.

As was previously described, the delay profile control register306that is pointed to will be used to output the 12 depth bits to the digital comparator302. The 5 profile bits of the delay profile control register306that are being pointed to will be output to a delay latch312.

The delay latch312can include a look up table314that can match a slope of the delay profile, indicated by the 5 profile bits output from the delay profile control memory308, with 5 delay bits. The 5 delay bits can be generated for each of the channels210ofFIG. 2. The 5 delay bits can set the analog RAM depth for the number of samples required to produce the individual delay for each of the channels210in the analog delay line208ofFIG. 2.

Referring now toFIG. 4, therein is shown a graphical illustration of a focal point402along an image line404in relation to one of the sub-arrays110ofFIG. 1. A return signal406is depicted as a waveform radiating out spherically away from the focal point402.

It can be seen that the return signal406impacts the center two transducer elements102of the sub-array110before the outer two transducer elements102of the sub-array110.

It has been discovered that making the simplifying assumption that the delay profile is linear across the four transducer elements102of the sub-array110, reduces the complexity and memory requirements for a sub-array delay controller and the sub-array delay controller212ofFIG. 2can be developed therefrom.

The simplifying assumption of a linear delay profile can be validated by determining how close the focal point402can be to the sub-array110before an error408, proportional to the minimum focus resolution of λ/16, is incurred at the two outer transducer elements102of the sub-array110. The minimum distance from the focal point402to the sub-arrays110before a maximum delay error is incurred at the two outer transducer elements102of the sub-arrays110can be described by Equation 1 as:

Equation 1 can be an equation for calculating the radius (R) of a circle knowing the width (W) and height (H) of a segment of the circle. The radius R that will result in a height H=λ/16 with a width W=3λ/2, is approximately 4.5λ.

As an illustrative example, a transducer operating at 2.5 MHz can have a distance from the focal point402to the sub-array110of greater than 0.278 cm before the error408of λ/16 is reached. This can result in focal point402distances greater than 0.278 cm, the focus error assuming a linear delay slope will be less than λ/16.

As a further illustrative example, a transducer operating at 5 MHz can have a distance from the focal point402to the sub-array110of greater than 0.139 cm before the error408of λ/16 is reached. This can result in focal point402distances greater than 0.139 cm, the focus error assuming a linear delay slope will be less than λ/16.

Referring now toFIG. 5, therein is shown a graphical illustration of linear delay slopes502ofFIG. 5for three of the sub-arrays110ofFIG. 1. The transducer elements102are shown staggered in the vertical dimension according to the length of delay needed to maintain focus with the focal point402ofFIG. 4.

The transducer elements102are shown arranged laterally according to their position within a transducer array. The linear delay slopes502can be used to delay the channels210ofFIG. 2in the analog delay line208ofFIG. 2while in the analog domain.

As can be seen, each of the sub-arrays110can be assigned an individual one of the linear delay slopes502and each of the transducer elements102within the sub-arrays110can be delayed according to the linear delay slopes502rather than being delayed according to an optimal delay curve504.

It is contemplated that the delay profile control registers306ofFIG. 3for the sub-array delay controller212ofFIG. 2can include the linear delay slopes502identified by the 5 profile bits. After the sub-array receiver beamformer200ofFIG. 2implements the linear delay slopes502to the sub-arrays110in the analog domain, the digital beamformer116ofFIG. 1can calculate a digital delay506and compensate with the digital delay506from the centers of the sub-arrays110since the linear delay slopes502pivot around this point.

It has been discovered that compensating the sub-arrays110with the linear delay slopes502in the analog domain greatly reduces the power consumption, size requirements, memory requirements, and digital processing requirements because conceptually the linear delay slopes502reduce a transducer with 64 elements facing perpendicular to the transducer face to a virtual transducer with only 16 elements that are 4× the size and tilted such that the face of the elements point in the direction of the receive focal point.

Referring now toFIG. 6, therein is shown a graphical illustration of the linear delay slopes502ofFIG. 5. Continuing with the example above having a λ/16 delay minimum resolution and a maximum delay of 1.5λ, a total of 25 possible linear delay slopes502would be required and can be seen labeled1-25.

The linear delay slopes502are shown graphically depicted with the length of the delay in the vertical axis and the position of the transducer elements102ofFIG. 1along the horizontal axis. It is contemplated that one of the linear delay slopes502can be assigned to all four of the transducer elements102and provide the individual delays602for a transducer element T1, a transducer element T2, a transducer element T3, and a transducer element T4.

It can be seen that the digital delay506ofFIG. 5, that can be added with the digital beamformer116ofFIG. 1, can be calculated from the pivot point604of the linear delay slopes502, which is positioned between the transducer element T2and the transducer element T3. As an illustrative example, when the focal point402ofFIG. 4is relatively near, the linear delay slope502can be more extreme and could result in the 22nd linear delay slope502being assigned to the sub-arrays110ofFIG. 1containing the transducer element T1, the transducer element T2, the transducer element T3, and the transducer element T4.

When the 22nd linear delay slope502is assigned to the transducer elements102it can be seen that the transducer element T1will have a relatively short individual delay602, the transducer element T2will have a longer individual delay602than the transducer element T1. The transducer element T3will have a longer individual delay602than both the transducer element T1and the transducer element T2, while the transducer element T4will have the longest individual delay602in the sub-array110.

The individual delays602for each of the transducer elements102will be summed in the sub-array receiver beamformer200ofFIG. 2and will be output as the sub-array beamformer outputs112ofFIG. 1. The sub-array beamformer outputs112will be converted to the digital domain in the post sub-array receiver114ofFIG. 1and further processed to include the digital delay506in the digital beamformer116calculated from the pivot point604.

Referring now toFIG. 7, therein is shown a graphical illustration of the linear delay slopes502ofFIG. 5for two of the sub-arrays110ofFIG. 1for multiple focal points402ofFIG. 4along the image line404ofFIG. 4. The image line404is shown having a close focal point702, an intermediate focal point704, and a far focal point706.

As the return signal406ofFIG. 4is detected by the sub-arrays110, the close focal point702can be the first focal point402detected on the image line404. The intermediate focal point704can be the next focal point402detected on the image line404and the far focal point706can be the last focal point402detected on the image line404.

As the focal points402get further from the sub-arrays110over time, the linear delay slopes502can be updated for each sub-array110. It is contemplated that the linear delay slopes502can be updated for each of the sub-arrays110to remain orthogonal or perpendicular to a signal path708of the return signal406.

The signal path708can be the path of the return signal406from the focal point402to the pivot point604ofFIG. 6at the center of the sub-arrays110.

It is depicted that the left of the sub-arrays110includes the linear delay slopes502that rotate counter-clockwise as the focal points402move further away along the image line404. The linear delay slopes502can start with a large negative slope that rotates counter-clockwise with time as the focal point402shifts from the close focal point702to the far focal point706.

It is further depicted that the right of the sub-arrays110includes the linear delay slopes502that rotate clockwise as the focal points402move further away along the image line404. The linear delay slopes502can start with a large positive slope that rotates clockwise with time as the focal point402shifts from the close focal point702to the far focal point706.

It is contemplated that the linear delay slopes502for each of the sub-arrays110over the receive interval for one image line404never repeat. It has been discovered that since the linear delay slopes502for each of the sub-arrays110can be a limited number of values that monotonically increase or decrease and do not repeat during a receive interval of an image line404, then an initial value of the linear delay slope502, incremented or decremented at the proper time for each focal point402, can be used to dynamically focus an individual sub-array110. This can greatly reduce the power, memory, and processing requirements.

Referring now toFIG. 8, therein is shown a graphical illustration of two focal points402ofFIG. 4in relation to one of the sub-arrays110ofFIG. 1. The return signal406is shown for each of the focal points402.

The return signal406from the far focal point706can result in the acceptable error408of less than λ/16, while the return signal406from the close focal point702can result in the unacceptable error802of greater than λ/16.

It can be appreciated that the far focal point706can be further than 4.53λ from the sub-arrays110, which will result in the error408of λ/16 or less at the two outer transducer elements102. On the other hand, the close focal point702is depicted closer than 4.53λ from the sub-arrays110, which will result in the error802of greater than λ/16 at the two outer transducer elements102.

Illustratively, when the maximum acceptable error is λ/16, the unacceptable error802can result when the close focal point702is less than 4.53λ away from the sub-arrays110, which can be 0.28 cm at F0=2.5 MHz. It is contemplated that when the distance of the close focal point702to the sub-arrays110results in the unacceptable error802at the outer transducer elements102, a “bow correction” can be added to the linear delay slopes502ofFIG. 5.

It is shown that the error 802 can be 3λ/16 for the outer transducer elements102while the error for the inner transducer elements102is still relatively small. It is contemplated that the “bow correction” can be used to bow the linear delay slopes502and correct the individual delay602ofFIG. 6for the outer transducer elements102to avoid the unacceptable error802.

For example, a 2-bit bow correction could be stored within the sub-array delay controller212ofFIG. 2and result in the individual delay602for the outer transducer elements102being corrected by 1λ to 3λ. It has been discovered that storing and applying the bow correction adds only marginal complexity while appreciably improving image quality in the very near field.

Referring now toFIG. 9, therein is shown a block diagram of a sub-array delay controller900similar to the sub-array delay controller212ofFIG. 2in an alternative embodiment. The sub-array delay controller900can include a depth counter902and the 16xF0 clock236clock input.

The depth counter902can be started at the beginning of the receive interval and can be used to determine when to increment or decrement the linear delay slopes502ofFIG. 5. The output of the depth counter902can be coupled to a digital comparator906. The digital comparator906can also be coupled to the output of a delay profile control memory908.

The delay profile control memory908can be a memory containing the depth count values required to increment or decrement the linear delay slopes502. When the digital comparator906determines that the output of the delay profile control memory908matches the output of the depth counter902, the digital comparator906can provide an output to trigger an update of the linear delay slopes502.

The update to the linear delay slopes502caused by the output of the digital comparator906can be an input to a slope counter910. The slope counter910can monotonically increment or decrement through the linear delay slopes502. The output of the digital comparator906can also increment a digital adder912that can be used to increment a memory read address counter and update the delay profile control memory's908output value to the digital comparator906.

As an illustrative example, a maximum depth of 30 cm can be assumed for a 2.5 MHz transducer, which would require the depth counter902to have a maximum count of 15.6K or 14 bits because the depth counter906operates at 16xF0. Since F0 is contemplated to be 2.5 MHz, 16xF0 would be 40 MHz.

The propagation delay of sound in the human body is approximately 1540 m/sec or a 13μ sec round trip for 1 cm depth. Hence, a maximum of 25 words, 14 bits in length, could be used to program the linear delay slope502updates for a single sub-array110ofFIG. 1having four transducer elements102ofFIG. 1for a single image line404ofFIG. 4. Words of 14 bits would be required to provide the required depth resolution for a 30 cm depth with a 2.5 MHz transducer assuming the 16xF0 clock rate of 40 MHz and a 1540 m/s speed of sound.

It should be noted that the digital beamformer116ofFIG. 1with the sub-array delay controller900of this embodiment should still have a resolution of at least λ/16. The digital adder912can include a memory read address input from an initial delay profile control memory address generator914that can generate a memory read address with the line number232input.

The line number232input can further be used in an initial slope module916to generate an initial 5 slope bits pointing to the linear delay slopes502. The line number232input can also be used in a slope increment decrement module918, which can output a single increment or decrement bit.

The output of the slope increment decrement module918and the initial slope module916can be used in the slope counter910. The slope counter910can provide 5 slope bits to a delay latch920. The delay latch920can include a look up table922that can match the slope of the linear delay slopes502indicated by the 5 slope bits with 5 delay bits. The 5 delay bits can indicate the individual delay602ofFIG. 6for each of the channels210ofFIG. 2in the analog delay line208ofFIG. 2.

The delay latch920can be clocked by the 4xF0 clock230clock input. The slope counter910and the depth counter902can include a reset924input that can act as a load signal for the slope counter910. The depth counter902can further include a line start926input. The sub-array delay controller900can include an SPI connection928for programming the sub-array delay controller900.

Referring now toFIG. 10, therein is shown a block diagram of the sub-array aperture shift multiplexer214ofFIG. 2. The sub-array aperture shift multiplexer214is shown having inputs1002from each of the32transducer elements102ofFIG. 1buffered by the VGLNAs206ofFIG. 2for a single sub-array receiver beamformer IC104ofFIG. 1.

The sub-array aperture shift multiplexer214, for each of the sub-arrays110ofFIG. 1, can include seven inputs1002from seven of the transducer elements102. As can be seen, the inputs1002for a first sub-array1004can include the transducer elements l-7, while a second sub-array1006can include the inputs1002from the transducer elements5-11.

The sub-array aperture shift multiplexer214for each of the sub-arrays110is contemplated to include 4 switches1008. The sub-array aperture shift multiplexer214includes switch outputs1010that can be summed and delayed to provide the summed beamformed output204.

The sub-array aperture shift multiplexer214can include the inputs shift0218ofFIG. 2and shift1220ofFIG. 2. The shift0218and the shift1220inputs can be used by the sub-array aperture shift multiplexer214to generate four states or position sequences within each group of four switches1008.

The switches1008can logically shift the inputs1002to the sub-arrays110by 0, 1, 2, and 3 transducer elements102. As can be seen, it is contemplated that every group of four switches1008within the sub-array aperture shift multiplexer214can have the same position sequence.

It is contemplated that the switches1008for each sub-array110can be configured as a 4:1 multiplexer, that is one of the four switches1008can be closed while the other three switches1008can be open for each state.

Referring now toFIG. 11, therein is shown a graphical illustration of the switch1008states for the sub-array aperture shift multiplexer214ofFIG. 2. The switches are shown in four states each having one of the switches1008closed and three switches1008open.

Referring now toFIG. 12, therein is shown a graphical illustration of an aperture1202stepping across the transducer elements102ofFIG. 1during five successive image lines404ofFIG. 4. In each successive image line404, the aperture1202can increment by one of the transducer elements102.

It is contemplated that the sub-array aperture shift multiplexer214ofFIG. 2can align the sub-arrays110to the aperture1202in the same relative position as the aperture1202steps across the transducer elements102. The aperture1202can be seen having a 16 transducer element102window aligned with 4 sub-arrays110.

The aperture1202can be seen maintaining the same relative location with each of the sub-arrays110while stepping across the transducer elements102until four transducer elements102has been stepped through. Once4transducer elements102have been stepped through, the aperture1202can step or increment to the next sub-array110.

It has been discovered that with the ability to align the sub-arrays110with the aperture1202as shown, dynamic receive apodization of the summed beamformed output204ofFIG. 2can be achieved with a resolution of 4 transducer elements102or 1 sub-array110. It has been further discovered that the ability to shift the aperture1202through the transducer elements 102 while keeping the same relative position with the sub-arrays110allows the same linear delay slopes502ofFIG. 5to be used with four successive image lines404on linear arrays and curved linear arrays when the image lines404are all perpendicular to the transducer face, and eliminates small focus variability from image line404to image line404which can cause image artifacts.

Thus, it has been discovered that the sub-array receiver beamformer furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects. The resulting configurations are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.