Linear device value estimating method, capacitance detecting method, integrated circuit, touch sensor system, and electronic device

A touch sensor panel includes vertical & horizontal electrodes each respectively including a repeat of first & second basic shapes connected to one another in a vertical & horizontal directions, the first & second basic shapes each including a fine wire, respectively provided on vertical & horizontal electrode surfaces, and arranged at intervals; and a plurality of linear devices at respective intersections of the electrodes. A method includes driving the vertical electrodes in parallel on a basis of code sequences di for each of the linear devices so as to output, along the horizontal electrodes, linear sums of respective outputs corresponding to the linear devices; and estimating respective values of the linear devices along the horizontal electrodes on a basis of an inner product operation of (i) the linear sums outputted along the horizontal electrodes and (ii) the code sequences di.

TECHNICAL FIELD

The present invention relates to a method for estimating or detecting a coefficient, a device value, or a capacitance in a linear system configured in a matrix. The present invention further relates to an integrated circuit, a touch sensor system, and an electronic device each operating in accordance with the method.

BACKGROUND ART

There has been known a device for detecting linear device values distributed in a matrix. Patent Literature 1, for example, discloses a touch sensor device (contact detecting device) for detecting distribution of capacitance values of a capacitance matrix Cij (i=1, . . . , M and j=1, . . . , L) formed between M drive lines and L sense lines. The touch sensor device operates in accordance with a scanning detection method; specifically, the touch sensor device sequentially selects one of the drive lines and thus detects respective values of linear devices connected to the drive line selected.

Patent Literature 2 discloses a capacitance detecting circuit which (i) in driving a plurality of drive lines, switches between a first drive line group and a second drive line group on the basis of a time series code sequence, (ii) outputs a measured voltage obtained by converting, into an electric signal, a sum total of respective currents across capacitances, connected to sense lines, at a plurality of intersections of driven drive lines with the sense lines, and (iii) performs a product-sum operation of such a measured voltage and the code sequence for each sense line so as to find a voltage value corresponding to a capacitance at each intersection.

The description below deals with an arrangement of vertical electrodes and horizontal electrodes in a conventional capacitive touch sensor panel.FIG. 41is a diagram illustrating an arrangement of vertical electrodes91and horizontal electrodes92in a conventional capacitive touch sensor panel.FIG. 41corresponds to FIG. 3 of Patent Literature 1.

This conventional capacitive touch sensor panel disclosed in Patent Literature 1 includes (i) a plurality of vertical electrodes91provided on a vertical electrode surface and arranged at predetermined intervals in a horizontal direction and (ii) a plurality of horizontal electrodes92provided on a horizontal electrode surface, which is parallel to the vertical electrode surface, and arranged at predetermined intervals in a vertical direction.

Each vertical electrode91includes a sequence of a repeat of diamond-shaped quadrangular sections93and94connected to each other in the vertical direction. Each horizontal electrode92includes a sequence of a repeat of diamond-shaped quadrangular sections95and96connected to each other in the horizontal direction.

The vertical electrodes91and the horizontal electrodes92, each including diamond-shaped sections, are so provided that the vertical electrodes91cross the horizontal electrodes92to constitute a capacitive touch sensor panel. In the case where such a capacitive touch sensor panel is to be placed on a display device for use, the vertical electrodes91and the horizontal electrodes92are normally each formed of a transparent conductive film made of, for example, ITO (indium tin oxide). Recent years have also witnessed research on the use of graphene as a substitute for ITO.

In the case where the diamond-shaped sections as illustrated inFIG. 41are made of, for example, ITO and arranged on a plane, each diamond-shaped section, having both center-line symmetry and center-point symmetry, exhibits a similarly symmetric capacitance change when touched by an object, such as a pen, that has a small touch area. Utilizing this symmetry in a capacitance change allows a symmetric position correction to be carried out during a touch-position detection, and thus increases the position detection precision.

FIG. 42is a diagram illustrating an arrangement of vertical electrodes81and horizontal electrodes82in another conventional capacitive touch sensor panel, which is disclosed in Patent Literature 2. Both the vertical electrodes and the horizontal electrodes82are arranged at predetermined intervals. The vertical electrodes81extend in a direction orthogonal to the direction in which the horizontal electrodes82extend. The vertical electrodes81and the horizontal electrodes82are arranged in the shape of a grid. The vertical electrodes81and horizontal electrodes82themselves individually include fine wires, which form a mesh.

(a) ofFIG. 43is a diagram illustrating an arrangement of vertical electrodes71in yet another conventional capacitive touch sensor panel, which is disclosed in Patent Literature 3. (b) ofFIG. 43is a diagram illustrating an arrangement of horizontal electrodes72in that capacitive touch sensor panel.

(a) ofFIG. 43illustrates an array of vertical electrodes71each including sections that each have a shape similar to a diamond shape and that are connected to one another in a vertical direction. (b) ofFIG. 43similarly illustrates an array of horizontal electrodes72each including sections that each have a shape similar to a diamond shape and that are connected to one another in a horizontal direction.

(a) ofFIG. 45is a diagram illustrating an arrangement of vertical electrodes in still another conventional capacitive touch sensor panel, which is disclosed in Patent Literature 4. (b) ofFIG. 45is a diagram illustrating an arrangement of horizontal electrodes in that capacitive touch sensor panel.

The capacitive touch sensor panel disclosed in Patent Literature 4 is a capacitance-type touch panel switch including (i) an electrically conductive X pattern group61including a plurality of conductive X sequences62arranged at slight intervals in the X direction and (ii) an electrically conductive Y pattern group66including a plurality of conductive Y sequences67arranged at slight intervals in the Y direction.

Each conductive X sequence62includes (i) a plurality of conductive X pads63that each have a substantially rhombic outline and that are arranged in the Y-axis direction and (ii) conductive X pads63athat each have a substantially isosceles-triangular outline and that are arranged in the Y-axis direction to sandwich the conductive X pads63. Adjacent conductive X pads63and63are connected to each other by a conductive X line64, while adjacent conductive X pads63and63aare also connected to each other by a conductive X line64.

The conductive X pads63and63aeach include a mesh of (i) fine wires extending in the X direction and (ii) fine wires extending in the Y direction. Each conductive X line64is thin and includes three straight lines65extending in the Y direction and arranged at predetermined intervals in the X direction.

Each conductive Y sequence67includes (i) a plurality of conductive Y pads68that each have a substantially rhombic outline and that are arranged in the X-axis direction and (ii) conductive Y pads68athat each have a substantially isosceles-triangular outline and that are arranged in the X-axis direction to sandwich the conductive Y pads68. Adjacent conductive Y pads68and68are connected to each other by a conductive Y line69, while adjacent conductive Y pads68and68aare also connected to each other by a conductive Y line69.

The conductive Y pads68and68aeach include a mesh of (i) fine wires extending in the X direction and (ii) fine wires extending in the Y direction. Each conductive Y line69is thin and includes three straight lines60extending in the X direction and arranged at predetermined intervals in the Y direction.

The X pattern group61and Y pattern group66arranged as above are so placed on top of each other as to extend orthogonally to each other in a planer view. The conductive X lines64of the conductive X sequences62and the conductive Y lines69of the conductive Y sequences67are stacked on top of each other to form a light-transmitting region having a light-transmitting property substantially identical to that of the conductive X pads63and the conductive Y pads68.

CITATION LIST

Patent Literature 1

Patent Literature 2

Patent Literature 3

Patent Literature 4

Patent Literature 5

Patent Literature 6

Patent Literature 7

Patent Literature 8

Patent Literature 9

SUMMARY OF INVENTION

Technical Problem

The touch sensor device of Patent Literature 1 operating in accordance with the scanning detection method is, however, disadvantageous in that the touch sensor device is required to complete within a period of time (T/m) a process of simultaneously selecting and scanning a plurality of lines so as to detect capacitances of the capacitance matrix Cij. For the above symbol T/m, T represents a period of time given to obtain two-dimensionally distributed capacitance values, and m represents a number of scans.

Accuracy of a detecting process can generally be better improved by a process such as averaging, as a process time is longer. On the other hand, (i) the period of time T given to obtain capacitance values needs to be shorter in order for the touch sensor device to follow a high-speed operation, and (ii) the number M of scans needs to be larger for improvement of resolution. Either of (i) and (ii) problematically reduces the process time (T/m) and thus decreases detection accuracy.

The capacitance detecting circuit of Patent Literature 2, to cancel an offset error in a measured voltage, (i) switches between driving the first drive line group and driving the second drive line group on the basis of a code sequence and (ii) subtracts a measured voltage based on the driving of the second drive line group from a measured voltage based on the driving of the first drive line group (see the specification, paragraphs [0058] through [0061]). The capacitance detecting circuit, however, carries out a two-stage operation and is problematically less effective in simultaneously achieving a high-speed operation and power consumption reduction.

The arrangement illustrated inFIG. 41, however, is problematic in that ITO and graphene each have too high a resistance value to produce a large capacitive touch sensor panel having a size of 30 inches or larger. The above arrangement thus involves a method for making diamond-shaped sections from fine lines of a metal (for example, Ag or Cu) that has a low resistance value (Patent Literature 2 [FIG. 42] and Patent Literature 3 [FIG. 43]).

The arrangement illustrated inFIG. 42problematically includes cross-shaped openings97that are present at certain intervals and that are not covered by the grid. The openings97are thus visually recognized, with the result of moire occurring. The above arrangement further has a problem of a decrease in position detection precision which decrease is due to the fact that the capacitance for the openings97is changed by a touch differently from that for the other region.

FIG. 44is a diagram illustrating a uniform grid73constituted by the vertical electrodes71and the horizontal electrodes72. The arrangement illustrated inFIG. 44, although free from openings such as those illustrated inFIG. 42, includes vertical electrodes71and horizontal electrodes72none of which has center-line symmetry or center-point symmetry. Further, placing the vertical electrodes71and the horizontal electrodes72on top of each other results in zigzag shapes78and79being formed respectively along the left side and bottom side of the grid73as illustrated inFIG. 44. This problematically makes it difficult to easily join, directly to the grid73, (i) an address line for driving the horizontal electrodes72(or the vertical electrodes71) and (ii) an address line for reading a signal from the vertical electrodes71(or the horizontal electrodes72).

The arrangement illustrated inFIG. 45includes (i) conductive X lines64that are parallel to the Y axis and (ii) conductive Y lines69that are parallel to the X axis. A conductive X line64is stacked on a conductive Y line69to form a light-transmitting region, which thus includes (i) straight lines parallel to the Y axis and (ii) straight lines parallel to the X axis. Thus, placing this capacitive touch sensor panel on, for example, a liquid crystal display problematically allows moire to occur.

It is an object of the present invention to provide a linear system coefficient estimating method, a linear device column value estimating method, a capacitance detecting method, an integrated circuit, a touch sensor system, and an electronic device each of which (i) achieves both a high detection accuracy and a high resolution and (ii) allows a high-speed operation.

It is an object of the present invention to provide (i) a capacitive touch sensor panel that includes a uniform grid with no visible gap and that can prevent moire or the like when placed on a display device, (ii) a capacitive touch sensor system including the above capacitive touch sensor panel, and (iii) an information input-output device.

Solution to Problem

A linear device value estimating method of the present invention is a linear device value estimating method for use in a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of linear devices provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the linear device value estimating method comprising: an outputting step for driving the plurality of vertical electrodes in parallel on a basis of code sequences di for each of the plurality of linear devices so as to output, along the plurality of horizontal electrodes, linear sums of respective outputs corresponding to the plurality of linear devices; and an estimating step for estimating respective values of the plurality of linear devices along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums outputted along the plurality of horizontal electrodes and (ii) the code sequences di.

The above feature drives the plurality of vertical electrodes in parallel on the basis of code sequences di, and outputs, along the plurality of horizontal electrodes, the linear sums of outputs corresponding respectively to the linear devices. This makes it possible to estimate values of the linear devices, the values being inputted all simultaneously to the plurality of vertical electrodes along the individual horizontal electrodes. The above feature consequently (i) eliminates the need to sequentially select one of M drive lines and scan it for an input as in conventional arrangements, and (ii) extends a process time for obtaining values of linear devices. The linear device value estimating method thus maintains a good detection accuracy and achieves a good resolution and a high-speed operation.

A capacitance detecting method of the present invention is a capacitance detecting method for use in a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the capacitance detecting method comprising: an outputting step for (i) driving the plurality of vertical electrodes in parallel for each of the plurality of capacitances, on a basis of code sequences di which include elements each being either +1 or −1, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (ii) outputting, along the plurality of horizontal electrodes, linear sums of respective outputs corresponding to the plurality of capacitances; and an estimating step for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of the linear sums of the outputs and the code sequences di.

An integrated circuit of the present invention is a integrated circuit for controlling a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the integrated circuit comprising: a drive section for (i) driving the plurality of vertical electrodes in parallel for each of the plurality of capacitances, on a basis of code sequences di which include elements each being either +1 or −1, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (ii) outputting, along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating section for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted along the plurality of horizontal electrodes, and (ii) the code sequences di.

A touch sensor system of the present invention is a touch sensor system comprising: a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline; and an integrated circuit for controlling the touch sensor panel, the integrated circuit including: a drive section for (i) driving the plurality of vertical electrodes in parallel for each of the plurality of capacitances, on a basis of code sequences di which include elements each being either +1 or −1, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (ii) outputting, along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating section for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted along the plurality of horizontal electrodes, and (ii) the code sequences di.

An electronic device of the present invention is a electronic device, comprising: the touch sensor system of the present invention; and a display panel which either is placed on the touch sensor panel included in the touch sensor system or contains the touch sensor panel.

A capacitance detecting method of the present invention is a capacitance detecting method for detecting a capacitance of a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the capacitance detecting method comprising: an outputting step for (i) driving the plurality of vertical electrodes in parallel for each of the plurality of capacitances, on a basis of code sequences di which include elements each being either +1 or −1, and (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating step for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted to the analog integrator along the plurality of horizontal electrodes, and (ii) the code sequences di, the outputting step driving, when the analog integrator is reset, the plurality of vertical electrodes at a first voltage represented by a voltage Vref, and driving, when the linear sums of the electric charges, the linear sums being outputted along the plurality of horizontal electrodes is sampled, the plurality of vertical electrodes at (i) a second voltage for an element of +1 in the code sequences, the second voltage being represented by a voltage (Vref+V), and (ii) a third voltage for an element of −1 in the code sequences, the third voltage being represented by a voltage (Vref−V).

Another capacitance detecting method of the present invention is a capacitance detecting method for detecting a capacitance of a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the capacitance detecting method comprising: an outputting step for (i) driving the plurality of vertical electrodes in parallel, on a basis of code sequences di which include elements each being either +1 or −1, and (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating step for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted to the analog integrator along the plurality of horizontal electrodes, and (ii) the code sequences di, the outputting step driving, for an element of +1 in the code sequences, the plurality of vertical electrodes at (i) a first voltage when the analog integrator is reset and at (ii) a second voltage when the linear sums of the electric charges, the linear sums being outputted along the plurality of horizontal electrodes, is sampled, and, for an element of −1 in the code sequences, the plurality of vertical electrodes at (i) the second voltage when the analog integrator is reset, and (ii) the first voltage when the linear sums are sampled.

Still another capacitance detecting method of the present invention is a capacitance detecting method for detecting a capacitance of a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the capacitance detecting method comprising: an outputting step for (i) driving the plurality of vertical electrodes in parallel, on a basis of code sequences di which include elements each being either +1 or −1, and (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating step for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted to the analog integrator along the plurality of horizontal electrodes, and (ii) the code sequences di, the capacitance detecting method further including, before the outputting step, a step of (i) driving, when the analog integrator is reset and when the linear sums of the electric charges, the linear sums being outputted to the analog integrator along the plurality of horizontal electrodes is sampled, the plurality of vertical electrodes at a first voltage so that the outputs of the linear sums of the electric charges are outputted to the analog integrator, (ii) reading out, from the analog integrator, the outputs of the linear sums of the electric charges as offset outputs, and (iii) storing the offset outputs in a memory.

Another integrated circuit of the present invention is an integrated circuit for controlling a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the integrated circuit comprising: a drive section for (i) driving the plurality of vertical electrodes in parallel for the plurality of capacitances, on a basis of code sequences di which include elements each being either +1 or −1 and thus (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating section for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted to the analog integrator along the plurality of horizontal electrodes, and (ii) the code sequences di, the drive section driving, for an element of +1 in the code sequences, the plurality of vertical electrodes at (i) a first voltage when the analog integrator is reset and at (ii) a second voltage when outputs from the plurality of capacitances are sampled, and, for an element of −1 in the code sequences, the plurality of vertical electrodes at (i) the second voltage when the analog integrator is reset, and (ii) the first voltage when the outputs from the plurality of capacitances are sampled.

Still another integrated circuit of the present invention is an integrated circuit for controlling a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the integrated circuit comprising: a drive section for (i) driving the plurality of vertical electrodes in parallel for the plurality of capacitances, on a basis of code sequences di which include elements each being either +1 or −1 and thus (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating section for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted to the analog integrator along the plurality of horizontal electrodes, and (ii) the code sequences di, the drive section, before the linear sums of the electric charges stored in the plurality of capacitances are outputted to the analog integrator along the plurality of horizontal electrodes, (i) driving the plurality of vertical electrodes at a first voltage when the analog integrator is reset and when the linear sums of the electric charges are sampled, (ii) outputting the linear sums of the electric charges to the analog integrator along the plurality of horizontal electrodes, (iii) reading out, from the analog integrator, the linear sums of the electric charges as offset outputs, and (iv) storing the offset outputs in a memory.

Another touch sensor system of the present invention is a touch sensor system comprising: a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline; and an integrated circuit for controlling the touch sensor panel, the integrated circuit including: a drive section for (i) driving the plurality of vertical electrodes in parallel for each of the plurality of capacitances, on a basis of code sequences di which include elements each being either +1 or −1 and thus (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating section for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted along the plurality of horizontal electrodes, and (ii) the code sequences di, the drive section driving, for an element of +1 in the code sequences, the plurality of vertical electrodes at (i) a first voltage when the analog integrator is reset and at (ii) a second voltage when the linear sums of the electric charges are sampled, and, for an element of −1 in the code sequences, the plurality of vertical electrodes at (i) the second voltage when the analog integrator is reset, and (ii) the first voltage when the linear sums of the electric charges are sampled.

Still another touch sensor system of the present invention is a touch sensor system comprising: a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline; and an integrated circuit for controlling the touch sensor panel, the integrated circuit including: a drive section for (i) driving the plurality of vertical electrodes in parallel for each of the plurality of capacitances, on a basis of code sequences di which include elements each being either +1 or −1 and thus (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating section for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted along the plurality of horizontal electrodes, and (ii) the code sequences di, the drive section, before the linear sums of the electric charges are outputted to the analog integrator, (i) driving the plurality of vertical electrodes at a first voltage when the analog integrator is reset and when the linear sums of the electric charges are sampled, (ii) outputting the linear sums of the electric charges to the analog integrator, (iii) reading out, from the analog integrator, the linear sums of the electric charges as offset outputs, and (iv) storing the offset outputs in a memory.

Another electronic device of the present invention is an electronic device, comprising: the touch sensor system of the present invention; and a display panel which either is placed on the sensor panel included in the touch sensor system or contains the sensor panel.

Still another capacitance detecting method of the present invention is a capacitance detecting method for detecting a capacitance of a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the capacitance detecting method comprising: an outputting step for (i) driving the plurality of vertical electrodes in parallel, on a basis of code sequences di which include elements each being either +1 or −1, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating step for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted to the analog integrator along the plurality of horizontal electrodes, and (ii) the code sequences di, the outputting step, to prevent saturation of the analog integrator, switching a gain of the analog integrator in accordance with an absolute value of a sum total of corresponding elements present in the code sequences along a column direction.

Still another capacitance detecting method of the present invention is a capacitance detecting method for detecting a capacitance of a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the capacitance detecting method comprising: an outputting step for (i) driving the plurality of vertical electrodes in parallel, on a basis of code sequences di which include elements each being either +1 or −1, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of 1− in the code sequences, and (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating step for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted to the analog integrator along the plurality of horizontal electrodes, and (ii) the code sequences di, the outputting step, to prevent saturation of the analog integrator, dividing, in accordance with an absolute value of a sum total of corresponding elements present in the code sequences along a column direction, a column of the code sequences into a plurality of columns so as to divide the driving of the plurality of vertical electrodes into a plurality of drivings.

Still anther capacitance detecting method of the present invention is a capacitance detecting method for detecting a capacitance of a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the capacitance detecting method comprising: an outputting step for (i) driving the plurality of vertical electrodes in parallel, on a basis of code sequences di which include elements each being either +1 or −1, the code sequences corresponding to respective rows of a Hadamard matrix created by Sylvester method for each of the plurality of capacitances, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating step for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted to the analog integrator along the plurality of horizontal electrodes, and (ii) the code sequences di, the outputting step, to prevent saturation of the analog integrator, dividing a first column of the code sequences into a plurality of columns so as to divide a driving for the first column of the code sequences into a plurality of drivings.

Still another capacitance detecting method of the present invention is a capacitance detecting method for detecting a capacitance of a touch sensor panel, the touch sensor panel including: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other; and a plurality of capacitances provided at respective intersections of the plurality of vertical electrodes with the plurality of horizontal electrodes, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extending in an oblique direction, the grid having a rectangular outline, the capacitance detecting method comprising: an outputting step for (i) driving the plurality of vertical electrodes in parallel, on a basis of code sequences di which include elements each being either +1 or −1, the code sequences corresponding to respective rows of a Hadamard matrix created by Sylvester method for each of the plurality of capacitances, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and (ii) outputting, to an analog integrator along the plurality of horizontal electrodes, linear sums of respective electric charges stored in the plurality of capacitances; and an estimating step for estimating respective capacitance values of the plurality of capacitances along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums of the electric charges, the linear sums being outputted to the analog integrator along the plurality of horizontal electrodes, and (ii) the code sequences di, the outputting step dividing a particular column of the code sequences into a plurality of columns, the particular column having an absolute value of a sum total of corresponding elements present in the code sequences along a column direction which absolute value exceeds a threshold Num for saturation of the analog integrator, so as to divide a driving for the particular column into a plurality of drivings.

Advantageous Effects of Invention

A linear device value estimating method of the present invention includes: an outputting step for driving the plurality of vertical electrodes in parallel on a basis of code sequences di for each of the plurality of linear devices so as to output, along the plurality of horizontal electrodes, linear sums of respective outputs corresponding to the plurality of linear devices; and an estimating step for estimating respective values of the plurality of linear devices along the plurality of horizontal electrodes on a basis of an inner product operation of (i) the linear sums outputted along the plurality of horizontal electrodes and (ii) the code sequences di.

The above feature drives the plurality of vertical electrodes in parallel on the basis of code sequences di, and outputs, along the plurality of horizontal electrodes, the linear sums of outputs corresponding respectively to the linear devices. This makes it possible to estimate values of the linear devices, the values being inputted all simultaneously to the plurality of vertical electrodes along the individual horizontal electrodes. The above feature consequently (i) eliminates the need to sequentially select one of M drive lines and scan it for an input as in conventional arrangements, and (ii) extends a process time for obtaining values of linear devices. The linear device value estimating method thus maintains a good detection accuracy and achieves a good resolution and a high-speed operation.

DESCRIPTION OF EMBODIMENTS

Embodiments of a touch sensor system of the present invention are described below with reference toFIGS. 1through40.

Configuration of Touch Sensor System of Embodiment 1

FIG. 1is a circuit diagram illustrating a configuration of a touch sensor system1of the present embodiment. The touch sensor system1includes: a touch sensor panel2; and an integrated circuit3for controlling the touch sensor panel2. The touch sensor panel2includes: M drive lines DL1 through DLM provided in a horizontal direction in parallel to one another so as to be separated from one another at a predetermined interval; L sense lines SL1 through SLL provided in such a direction as to cross the drive lines and in parallel to one another so as to be separated from one another at a predetermined interval; and capacitances Cij (where i=1 to M, and j=1 to L) provided in a matrix of M rows×L columns at respective intersections of the M drive lines DL1 through DLM with the L sense lines SL1 through SLL.

The integrated circuit3includes: a drive section4connected to the M drive lines DL1 through DLM; and an estimation section5.FIG. 2is a block diagram illustrating a configuration of the estimation section5included in the integrated circuit3.

The estimation section5includes: L analog integrators connected to the L sense lines SL1 through SLL, respectively; a switch7connected to the L analog integrators6; an AD converter8connected to the switch7; an inner product computing section9connected to the AD converter8; and a RAM10connected to the inner product computing section9. The analog integrators6each include: an operational amplifier with a first input grounded; an integral capacitance Cint provided between an output of the operational amplifier and a second input thereof; a first transistor connected to the second input of the operational amplifier; and a second transistor connected to the second input in parallel to the first transistor.

The integrated circuit3further includes an application processing section11which is connected to the inner product computing section9and which carries out a gesture recognition process (for example, ARM) at 240 Hz. The integrated circuit3thus includes both analog circuits and digital circuits.

(Operation of Conventional Touch Sensor System)

The description below deals first with an operation of the conventional touch sensor device disclosed in Patent Literature 1 mentioned above, and then with an operation of the touch sensor system1of the present embodiment in detail. The following looks at detection of capacitances Cij (where i=1, . . . , M, and j=1, . . . , L) formed in a matrix at respective intersections of M drive lines and L sense lines, and specifically at scanning detection in which the individual drive lines are sequentially selected.

Capacitances Cij (j=1, . . . , L) connected to a selected drive line are each supplied with a voltage V so as to store an electric charge (signal) Cij×V. Supposing that this signal is read out via a sense line so that a gain G is obtained, a signal to be detected is expressed as follows:
G×Cij×V(Formula 1)

(Operation of Touch Sensor System of Present Embodiment)

FIG. 3is a diagram illustrating a method for driving the touch sensor panel2included in the touch sensor system1. Constituents illustrated inFIG. 3which are identical to their respective equivalents illustrated and referred to inFIGS. 1 and 2are each assigned the same reference sign accordingly. Such constituents inFIG. 3are not described in detail here.

First, the present embodiment of the present invention prepares code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M). The code sequences di are orthogonal to one another and include +1 and −1. Further, the code sequences di each have a code length N. The orthogonality of the code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) each with a code length N means that the code sequences di satisfy the following condition:

where

The drive section4drives the M drive lines DL1 through DLM in parallel on the basis of the code sequences di so that a voltage +V is applied to each capacitance corresponding to +1 and a voltage −V is applied to each capacitance corresponding to −1. The capacitances Cij (where i=1 to M, and j=1 to L) consequently each store an electric charge (signal) ±Cij V in accordance with a corresponding element (+1 or −1) in the code sequences.

The analog integrators6then each (i) add, via its connection to a corresponding sense line, electric charges stored in capacitances connected to the sense line and thus (ii) read out a signal for its corresponding sense line. The analog integrators6consequently obtain output sequence vectors sj (=sj1, sj2, . . . , sjN, where j=1, . . . , L).

FIG. 4is a timing chart illustrating the method for driving the touch sensor panel2. First, a reset signal resets (i) the integral capacitances Cint of the respective analog integrators6and (ii) the capacitances provided in the touch sensor panel2in a matrix. The term “reset” as used herein means to discharge a capacitance. Next, the drive lines DL1 through DLM are driven in parallel each at Vref+V or Vref−V in accordance with each value (+1 or −1) of d11, d21, d31, . . . , dM1 in a code sequence. This causes each corresponding capacitance to store an electric charge ±CV in accordance with a corresponding element ±1 of the code sequence. Then, a corresponding one of the analog integrators6(i) adds, via its connection to a corresponding sense line, electric charges stored in the capacitances connected to the sense line and thus (ii) reads out a signal for its corresponding sense line. The analog integrator6then outputs a result represented by

G×∑k=1M⁢(Cki×V×dki)
(in this circuit, G=−1/Cint), which is next subjected to an AD conversion in the AD converter8in accordance with a sampling signal.

The above operation produces output sequence vectors sji expressed as

sj=∑k=1M⁢(Ckj×V×dk).
To find an inner product di·sj of a code sequence di and an output sequence vector sj,

where

Comparison between Formula 1 and Formula 2 shows that the method of the present embodiment makes it possible to detect a signal which is N times as large as a signal detected by the conventional scanning readout method.

The gain G is 1/Cint in a case where signals are read out via the sense lines with use of the analog integrators6illustrated inFIGS. 1 and 2, that is, electric charge integrators each including an operational amplifier provided with an integral capacitance Cint.

The drive section4of the integrated circuit3thus drives the M drive lines in parallel so that for each of a first capacitance column Cip (where p is not smaller than 1 and not larger than (L−1), and i=1, . . . , M) and a second capacitance column Ciq (where p<q, q is not smaller than 2 and not greater than L, and i=1, . . . , M), voltages +V and −V are applied to capacitances so as to correspond to +1 and −1 of a code sequence, respectively, in accordance with the code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements of +1 and −1 and each of which has a length N. The drive section4then causes (i) the first capacitance column to output sFirst (=sp1, sp2, . . . , spN) and (ii) the second capacitance column to outputs sSecond (=sq1, sq2, . . . , sqN).

The outputs sFirst (=sp1, sp2, . . . , spN) from the first capacitance column are each integrated by a corresponding analog integrator6, whereas the outputs sSecond (=sq1, sq2, . . . , sqN) from the second capacitance column are also each integrated by a corresponding analog integrator6. The switch7sequentially selects one of the analog integrators6, respectively corresponding to the sense lines SL1 through SLL, so as to supply to the AD converter8outputs from each capacitance column which have each been integrated by a corresponding analog integrator6.

Specifically, the output sp1 is first read out from the first capacitance column to a first analog integrator6and integrated by the first analog integrator6, while simultaneously, the output sq1 is read out from the second capacitance column to a second analog integrator6and integrated by the second analog integrator6. Then, the switch7connects to the first analog integrator6so as to supply to the ADC8the output sp1 read out and integrated as above. The switch7then disconnects from the first analog integrator6and connects to the second analog integrator6so as to supply to the ADC8the output sq1 read out and integrated as above. Next, the output sp2 is read out from the first capacitance column to the first analog integrator6and integrated by the first analog integrator6, while simultaneously, the output sq2 is read out from the second capacitance column to the second analog integrator6and integrated by the second analog integrator6. Then, the switch7connects to the first analog integrator6so as to supply to the ADC8the output sp2 read out and integrated as above. The switch7then disconnects from the first analog integrator6and connects to the second analog integrator6so as to supply to the ADC8the output sq2 read out and integrated as above. This operation allows the outputs sp1 through spN and the outputs sq1 through sqN to be sequentially supplied to the ADC8via the first and second analog integrators6and the switch7. The analog integrators6for all the sense lines operate in parallel in accordance with the driving of the drive lines.

The AD converter8carries out an AD conversion with respect to the outputs from each capacitance column, the outputs each having been integrated by a corresponding one of the analog integrators6, and supplies the resulting outputs to the inner product computing section9.

The inner product computing section9estimates, with reference to data stored in the RAM10, (i) a capacitance value in the first capacitance column, the capacitance value corresponding to a k1-th drive line (where 1≦k1<M), by computing an inner product of a corresponding output sFirst and a corresponding code sequence di and (ii) a capacitance value in the second capacitance column, the capacitance value corresponding to a k2-th drive line (where k1<k2, and 1<k1≦M), by computing an inner product of a corresponding output sSecond and a corresponding code sequence di.

The application processing section11carries out a gesture recognition process on the basis of capacitance values of the capacitances which capacitance values have been estimated by the inner product computing section9, and thus generates a gesture command.

(Specific Examples of Code Sequences)

FIG. 5is a diagram illustrating a first specific example of orthogonal code sequences as an input to the touch sensor panel2. The orthogonal code sequences di each with a length N can be created specifically as described below, for example.

An Hadamard matrix, which is a typical example of orthogonal code sequences, is created by Sylvester method illustrated inFIG. 5. The method first creates a building block of 2 rows×2 columns as a basic structure. The building block includes four bits, among which an upper right one, an upper left one, and a lower left one are identical to one another, whereas a lower right one is an inverse of the above bits.

The method then combines four blocks of the above 2×2 basic structure at upper right, upper left, lower right, and lower left locations so as to create codes in a bit arrangement of 4 rows×4 columns. The method also inverts bits in the lower right block as in the above creation of a 2×2 building block. Next, the method similarly creates codes in a bit arrangement of 8 rows×8 columns, and then creates codes in a bit arrangement of 16 rows×16 columns. These matrices each satisfy the above-mentioned definition of being “orthogonal” in the present invention.

In a case where, for example, the touch sensor panel2of the present embodiment includes 16 drive lines, the present embodiment can use, as the orthogonal code sequences, codes in a bit arrangement of 16 rows×16 columns illustrated inFIG. 5. An Hadamard matrix is a square matrix which includes elements each being 1 or −1 and which includes rows orthogonal to one another. In other words, any two rows in an Hadamard matrix represent vectors perpendicular to each other.

The orthogonal code sequences of the present embodiment can be any M-row matrix taken from an N-dimensional Hadamard matrix (where M≦N). As described below, an Hadamard matrix created by a method other than Sylvester method can alternatively be used in the present invention.

FIG. 6is a diagram illustrating a second specific example of the orthogonal code sequences.FIG. 7is a diagram illustrating a third specific example of the orthogonal code sequences. While any N-dimensional Hadamard matrix created by Sylvester method can be expressed by a power of N=2, it is assumed that an Hadamard matrix can be created if N is a multiple of 4. For example,FIG. 6illustrates an Hadamard matrix in which N=12, whereasFIG. 7illustrates an Hadamard matrix in which N=20. These Hadamard matrices created by a method other than Sylvester method can alternatively be used as the orthogonal code sequences of the present embodiment.

(How Inner Product is Computed)

An inner product matrix C′ij=di·sj is computed through steps described below.

(1) The integrated circuit3resets an inner product matrix stored in the RAM10(seeFIG. 2) of the estimation section5to C′ij=0.

(2) The drive section4drives an i-th drive line DLi (where i=1, . . . , M) at a voltage V×dik in parallel at a time tk (where k is one of 1, . . . , N) so as to supply each connected capacitance with an electric charge Cij×V×dik.

(3) The integrated circuit3connects the analog integrators6to their corresponding sense lines j (where j=1, . . . , L) so that the analog integrators6each read out an output voltage sjk from a corresponding one of the capacitances which have been charged at the time tk. The switch7then sequentially supplies the L output voltages sjk for the time tk to the AD converter8for AD conversion. The L output voltages sjk have been read out by the L respective analog integrators6provided so as to correspond to the L sense lines. The AD converter8carries out an AD conversion with respect to the output voltages sjk for the time tk, and then supplies them to the inner product computing section9. The output voltages sjk for the time tk thus supplied to the inner product computing section9are expressed as follows:

(4) The inner product computing section9carries out addition or subtraction with respect to C′ij in accordance with (i) the L respective output voltages sjk outputted from the AD converter8and (ii) code sequences dik stored in the RAM10. Specifically, the inner product computing section9carries out addition if a code sequence dik in question is 1, whereas it carries out subtraction if a code sequence dik in question is −1. The inner product computing section9then updates values of C′ij on the basis of results of the addition or subtraction:
C′ij←C′ij+dik×sjk

(5) The above procedure is repeated N times so as to correspond to the length of each code sequence while a value of the time is increased in increments (that is, tk+1). The process then returns to the step (1).

Completing the above steps causes C′ij to have values equal to results of the inner product computation.

The touch sensor panel2of the present embodiment, as described above, includes M drive lines and L sense lines, and has a length N for each code sequence. In a case where, for example, the touch sensor panel2is used in a 4-inch class mobile data terminal or the like, the touch sensor panel2will have a pitch of approximately 3 mm if M=16 and L=32. In a case where, for example, the touch sensor panel2is used in an electronic device including a 20-inch class screen, the touch sensor panel2will have a pitch of approximately 6 mm if M=48 and L=80. The length N of the code sequences has a very large degree of freedom, for example, N=64 to 512.

(Difference in Concept of Driving Between Present Invention and Conventional Art)

The capacitance detecting circuit disclosed in Patent Literature 2 mentioned above also (i) drives drive lines on the basis of a code sequence, (ii) outputs measured voltages each obtained by converting into an electric signal a sum total of currents across capacitances, connected to sense lines, at a plurality of respective intersections of each sense line with the driven drive lines, and (iii) carries out, for each sense line, a product-sum operation on the basis of the measured voltages and the code sequence. The capacitance detecting circuit thus finds a voltage value corresponding to each of the capacitances at the respective intersections. This capacitance detecting circuit, however, differs as below from the present embodiment in concept of driving the drive lines.

To simplify an explanation, the following description deals with an example case in which four capacitances (C1, C2, C3, and C4) are formed between a single sense line and four drive lines. Assuming that driving signals (code sequences) for the four drive lines are 1, 1, −1, and −1 (1, 1, 0, and 0 in Patent Literature 2), the present embodiment drives all the drive lines for each driving operation and thus produces an integral output corresponding to
C1+C2−C3−C4  (Formula 3),
whereas the capacitance detecting circuit disclosed in Patent Literature 2 drives only drive lines corresponding to “1” and thus produces an integral output corresponding to
C1+C2  (Formula 4).
Comparison between Formula 3 of the present embodiment and Formula 4 of Patent Literature 2 shows that the integral output produced in the present embodiment has a larger amount of information than that of Patent Literature 2.

Assuming that
Ci=C+ΔCi
where ΔCi represents a change in capacitance (ΔCi is normally approximately 10% of C),

Since ΔCi is approximately 10% of C in a touch sensor panel or the like, Formula 6 yields a value which is approximately 10 times as large as a value of Formula 5. This indicates that an integrating circuit that satisfies Formula 6 of Patent Literature 2 is unfortunately (i) required to set a gain which is approximately 1/10 of that of an integrating circuit of the present embodiment which integrating circuit satisfies Formula 5, and is thus (ii) lower in S/N ratio than the integrating circuit of the present embodiment. This difference in S/N ratio further increases with an increase in the number M of the drive lines.

The present embodiment, which drives all the drive lines in parallel for each driving operation, differs from the capacitance detecting circuit disclosed in Patent Literature 2, which switches between driving a first drive line group (C1 and C2) and driving a second drive line group (C3 and C4) on the basis of a code sequence so as to cancel an offset error in a measured voltage. In the present embodiment, an offset due to feedthrough in a reset switch can be measured on the basis of an output obtained from the AD converter8in a state where no signal is being inputted to a drive line (that is, the drive line is driven at a voltage Vref). Subtracting a measured offset value in a digital circuit cancels an offset error.

(Difference in Positive and Negative Operation Between Present Invention and Conventional Art)

The present embodiment calculates a value of Formula 3 at once by driving the M drive lines in parallel in accordance with values in a code sequence, that is, by driving the M drive lines so that voltages +V and −V are applied to the capacitances so as to correspond to +1 and −1, respectively. The capacitance detecting circuit disclosed in Patent Literature 2, in contrast, first calculates C1+C2 of Formula 4 and then calculates C3+C4 thereof. The capacitance detecting circuit of Patent Literature 2 thus carries out a two-stage operation and is less effective in simultaneously achieving a high speed operation and power consumption reduction.

The present embodiment further differs from the capacitance detecting circuit of Patent Literature 2 in that the present embodiment drives the drive lines so that a voltage −V is applied so as to correspond to a value of −1 in a code sequence, whereas the capacitance detecting circuit of Patent Literature 2 merely drives the drive lines at a voltage +V and thus lacks a concept of driving the drive lines at a voltage −V.

(Another Configuration of Estimation Section5) The present embodiment describes an example arrangement including (i) analog integrators6which are provided so as to correspond to L respective sense lines, (ii) a switch7which sequentially selects one of the analog integrators6, (iii) a single AD converter8, and (iv) a single inner product computing section9. The present invention is, however, not limited to this arrangement. The present invention can alternatively include a single analog integrator6so that the single analog integrator6sequentially selects an input to read out a signal for each sense line.

The present invention can further alternatively include (i) AD converters8provided so as to correspond to the respective sense lines and the respective analog integrators6and (ii) a switch7provided between the AD converters8and the inner product computing section9.

(Variation of Present Embodiment)

The present embodiment describes an example case of detecting capacitance values of respective capacitances formed between drive lines and sense lines. The present invention is, however, not limited to this. The present invention is also applicable in, for example, an arrangement for estimating values of respective linear devices formed between drive lines and sense lines. The present invention is further applicable in an arrangement for estimating a coefficient Ck corresponding to a k-th input xk (k=1, . . . , M) of a system which includes M inputs xk and has a linear input/output.

Furthermore, (i) the touch sensor system1of the present embodiment and (ii) a display panel placed over the touch sensor panel2of the touch sensor system1can be combined with each other so as to constitute an electronic device. Alternatively, (i) the touch sensor system1and (ii) a display panel including the touch sensor panel2and having a function of the touch sensor panel2included in the touch sensor system1can be combined with each other so as to constitute an electronic device.

Method for Driving Touch Sensor Panel at Two Voltages

FIG. 8is a first timing chart illustrating a method for driving a touch sensor panel2included in a touch sensor system1of Embodiment 2.

The method described in Embodiment 1 above with reference toFIG. 4for driving the touch sensor panel2drives the touch sensor panel2at three voltages, namely Vref, Vref+V, and Vref−V. The driving method of Embodiment 2, in contrast, drives the touch sensor panel2at two voltages V1 and V2.

Specifically, for a value of +1 in a code sequence, the method drives a corresponding drive line at (i) a voltage V1 when a corresponding one of the analog integrators6(seeFIG. 1) is reset and at (ii) a voltage V2 when an output is sampled from a capacitance connected to a corresponding sense line. Further, for a value of −1 in a code sequence, the method drives a corresponding drive line at (i) the voltage V2 when a corresponding one of the analog integrators6is reset and at (ii) the voltage V1 when an output is sampled from a capacitance connected to a corresponding sense line.

More specifically, in an example illustrated inFIG. 8, the drive line DL1, which corresponds to a code sequence having elements d11=+1 and d12=+1, is driven at (i) the voltage V1 when the analog integrators6are reset, (ii) the voltage V2 when outputs are sampled, (iii) the voltage V1 when the analog integrators6are reset next, and (iv) the voltage V2 when outputs are sampled next. The drive line DL2, which corresponds to a code sequence having elements d21=+1 and d22=−1, is driven at (i) the voltage V1 when the analog integrators6are reset, (ii) the voltage V2 when outputs are sampled, (iii) the voltage V2 when the analog integrators6are reset next, and (iv) the voltage V1 when outputs are sampled next.

The drive line DL3, which corresponds to a code sequence having elements d31=−1 and d32=−1, is driven at (i) the voltage V2 when the analog integrators6are reset, (ii) the voltage V1 when outputs are sampled, (iii) the voltage V2 when the analog integrators6are reset, and (iv) the voltage V1 when outputs are sampled next. The drive line DL4, which corresponds to a code sequence having elements d41=−1 and d42=+1, is driven at (i) the voltage V2 when the analog integrators6are reset, (ii) the voltage V1 when outputs are sampled, (iii) the voltage V1 when the analog integrators6are reset next, and (iv) the voltage V2 when outputs are sampled next. The drive line DLM, which corresponds to a code sequence having elements dM1=−1 and dM2=+1, is driven at (i) the voltage V2 when the analog integrators6are reset, (ii) the voltage V1 when outputs are sampled, (iii) the voltage V1 when the analog integrators6are reset next, and (iv) the voltage V2 when outputs are sampled next.

Assuming that V1=Vdd and V2=Vss, an output is expressed as
(Cf/Cint)×(V1−V2)=(Cf/Cint)×(Vdd−Vss).
In the method described in Embodiment 1 above with reference toFIG. 4for driving the touch sensor panel2, if Vref=(Vdd−Vss)/2,
V=(Vdd−Vss)/2
since Vdd=Vref+V and Vss=Vref−V. This V is half an output in the example illustrated inFIG. 8. The driving method of Embodiment 2 illustrated inFIG. 8thus (i) achieves a signal intensity which is twice as large as a signal intensity achieved by the driving method of Embodiment 1 illustrated inFIG. 4, and consequently (ii) allows the capacitances to each store an electric charge which is twice as large accordingly.

FIG. 9is a second timing chart illustrating a method for driving the touch sensor panel2included in the touch sensor system1of Embodiment 2.

The method drives the drive lines DL1 through DLM as illustrated inFIG. 9before it drives the drive lines DL1 through DLM in parallel illustrated inFIG. 4or8. Specifically, the method drives the drive lines DL1 through DLM at a constant voltage Vref both when the analog integrators6are reset and when outputs are sampled, and thus supplies no signals to the drive lines. The method in this state reads out offset output values from the respective analog integrators6(seeFIGS. 1 and 2). The ADC8then carries out an AD conversion with respect to the offset output values read out from the analog integrators6as above. The inner product computing section9next measures the offset output values which have been subjected to an AD conversion in the ADC8. The offset output values thus measured are each stored in the RAM10in association with a corresponding one of the sense lines SL1 through SLL.

The method next drives the drive lines DL1 through DLM in parallel as illustrated inFIG. 4or8, and causes each capacitance column to supply outputs to a corresponding analog integrator6. The ADC8then carries out an AD conversion with respect to the outputs from the capacitance columns which outputs have been received by the analog integrators6, and thus supplies the resulting outputs to the inner product computing section9. The inner product computing section9next subtracts, for the respective sense lines SL1 through SLL, the offset output values stored in the RAM10from the outputs from the capacitance columns which outputs have been supplied from the ADC8. This cancels an offset due to feedthrough in a reset switch in each analog integrator6.

The method can alternatively (i) repeat, a plurality of times, a procedure of: driving the drive lines DL1 through DLM at a constant voltage Vref both when the analog integrators6are reset and when outputs are sampled; reading out offset output values from the respective analog integrators6; causing the ADC8to carry out an AD conversion with respect to the offset output values read out as above; and causing the inner product computing section9to measure the resulting offset output values, so as to measure a plurality of sets of offset output values, and (ii) finding averages of the offset output values so as to store in the RAM10the average offset output values from which noise components included in the offset have been removed. The above plurality of times can, for example, be set to 16 times for 60 Hz or 100 times for 240 Hz.

Switching Gains of Analog Integrators

FIG. 10is a diagram illustrating a method for driving a touch sensor panel2of Embodiment 3. Constituents of the present embodiment which are identical to their respective equivalents in Embodiment 1 are each assigned the same reference sign accordingly. Such constituents of the present embodiment are not described in detail here.

The present embodiment deals with an example which involves (i) a touch sensor panel2including four drive lines DL1 through DL4 and four sense lines SL1 through SL4 and (ii) a code sequence based on a four-dimensional Hadamard matrix created by Sylvester method.

The present embodiment includes analog integrators6A. The analog integrators6A each include: an operational amplifier with a first input connected to a reference voltage Vref; an integral capacitance Cint provided between an output of the operational amplifier and a second input thereof; three other integral capacitances connected to the integral capacitance in parallel; and three switches each provided between one of the three other integral capacitances and the output of the operational amplifier.

A code sequence based on a four-dimensional Hadamard matrix created by Sylvester method includes elements such that a sum total of elements along a column direction is “4” for the first column and “0” for each of the second to fourth columns. Thus, a value obtained by adding outputs from a capacitance column is significantly greater when the drive lines are driven on the basis of the elements in the first column of the code sequence than when the drive lines are driven on the basis of the elements in one of the second to fourth columns of the code sequence. The value may exceed a capacity of a corresponding analog integrator6A and thus saturate the analog integrator6A.

In view of this, when the drive lines are driven on the basis of a column having a sum total of elements present in the code sequence along the column direction which sum total is so large as to saturate a corresponding analog integrator6A, the switches included in the corresponding analog integrator6A are appropriately turned on so as to prevent saturation of the analog integrator6A.

An Hadamard matrix created by Sylvester method invariably includes a first column having elements each being +1. An Hadamard matrix thus has a sum total of elements in the first column which sum total is significantly greater than that in any other column, and may thus saturate a corresponding analog integrator6A. It is, however, possible to prevent such saturation of an analog integrator6A by turning on the switches in the analog integrator6A as above so as to switch a gain of the analog integrator6A.

As described above, Embodiment 3 switches a gain of each analog integrator6A in accordance with an absolute value of a sum total of corresponding elements present in the code sequence along the column direction. As such, it is possible to prevent saturation of the analog integrators6A.

(Compensation of Gain Switching for Analog Integrator by Gain Switching of Inner Product Computing Section)

Division for Driving Drive Lines a Plurality of Times and Computing Inner Products

(a) and (b) ofFIG. 11are each a diagram illustrating a code sequence for use in driving a touch sensor panel2of Embodiment 4.

(a) ofFIG. 11illustrates a code sequence based on a four-dimensional Hadamard matrix created by Sylvester method. The code sequence is similar to the code sequence ofFIG. 10in that a sum total of elements along the column direction is “4” for the first column and “0” for each of the second to fourth columns. Thus, a value of a sum total of outputs obtained from a capacitance column is significantly greater when the drive lines are driven on the basis of the elements in the first column of the code sequence than when the drive lines are driven on the basis of the elements in one of the second to fourth columns of the code sequence. The value may exceed a capacity of a corresponding analog integrator6A and thus saturate the analog integrator6A.

In view of this, the present embodiment divides, as illustrated in (b) ofFIG. 11, the first column (1, 1, 1, 1) of the code sequence into two columns: one column represented by (1, 1, 0, 0) and the other column represented by (0, 0, 1, 1). This arrangement (i) increases the number of driving operations for the four drive lines from 4 times to 5 times and (ii) divides the sum total “4” of elements in the column direction into “2” and “2.” The above arrangement thus reduces a maximum sum total of elements in the column direction from “4” to “2,” and thus prevents saturation of the analog integrators.

Embodiment 4 illustrates an example code sequence based on a four-dimensional Hadamard matrix created by Sylvester method. The present invention is, however, not limited to this. The present invention is alternatively applicable in a code sequence based on a 2n-dimensional Hadamard matrix other than a four-dimensional Hadamard matrix. The present invention is also applicable in a code sequence based on an Hadamard matrix of any dimension which Hadamard matrix is created by a method other than Sylvester method.

Triangular Mountain Shaped Driving Method

FIG. 12is a diagram illustrating a code sequence for use in driving a touch sensor panel2of Embodiment 5.

In the touch sensor panel2of Embodiment 5, M drive lines are driven in parallel for each capacitance column formed between the M drive lines and L sense lines. The M drive lines are driven as such on the basis of code sequences which are orthogonal to one another and include elements each being +1 or −1 and each of which has a code length N>M. The code sequences correspond to respective rows of a 2n-dimensional Hadamard matrix (where M<2n) created by Sylvester method.FIG. 12illustrates an example of a code sequence of 13 rows×16 columns which is based on a 16-dimensional Hadamard matrix and which corresponds to M drive lines (where M=13).

FIG. 13is a graph illustrating a method for driving the touch sensor panel2. The graph has (i) a horizontal axis representing a location, along the column direction, in the Hadamard matrix (where N=16) illustrated inFIG. 12and (ii) a vertical axis representing an absolute value of a sum total of elements present in the Hadamard matrix (where N=16) along the column direction.

In the Hadamard matrix where N=16, elements in the first column are each “1.” Thus, a relation between (i) a location along the column direction (horizontal axis) and (ii) an absolute value of a sum total of elements along the column direction (vertical axis) is represented by a line L1, which shows a linear, monotone increase.

In the Hadamard matrix where N=16, the 9th column (that is, the (2(4-1)+1)th column) includes “1” from the 1st row through to the 8th row and “−1” from the 9th row through to the 16th row. Thus, the above relation for the 9th column is represented by a line L2, which shows a linear, monotone increase and then a linear, monotone decrease, thus forming a triangular mountain shape with a base length of 16 and a height of 8.

In the Hadamard matrix where N=16, the 5th column (that is, the (24-1−24-2+1)-th column) includes (i) “1” from the 1st row through to the 4th row, (ii) “−1” from the 5th row through to the 8th row, (iii) “1” from the 9th row through to the 12th row, and (iv) “−1” from the 13th row through to the 16th row. Thus, the above relation for the 5th column is represented by a line L3, which forms two triangular mountain shapes each with a base length of 8 and a height of 4. Further, the 13th column (that is, the (24-1+24-2+1)-th column) includes (i) “1” from the 1st row through to the 4th row, (ii) “−1” from the 5th row through to the 8th row, (iii) “−1” from the 9th row through to the 12th row, and (iv) “1” from the 13th row through to the 16th row. Thus, the above relation for the 13th column is also represented by the line L3, which forms two triangular mountain shapes.

The 3rd column, the 7 column, the 11th column, and the 15th column are each represented by a line L4, which forms four triangular mountain shapes each with a base length of 4 and a height of 2. The 2nd column, the 4th column, the 6th column, the 8th column, the 10th column, the 12th column, the 14th column, and the 16th column are each represented by a line L5, which forms eight triangular mountain shapes each with a base length of 2 and a height of 1.

The description below supposes that the above absolute value of a sum total of elements present in the code sequence along the column direction has a threshold Num, above which a corresponding analog integrator6(seeFIG. 1) is saturated. In the examples illustrated inFIGS. 12 and 13, Num=3, and the number of drive lines is 13 (M=13).

As illustrated inFIG. 13, the absolute value does not exceed the threshold Num=3 in any column corresponding to the line L5 (that is, the 2nd column, the 4th column, the 6th column, the 8th column, the 10th column, the 12th column, the 14th column, and the 16th column) or any column corresponding to the line L4 (that is, the 3rd column, the 7 column, the 11 column, and the 15 column). Simultaneously driving the M (=13) drive lines thus does not saturate analog integrators6corresponding to the above columns.

The 1st column corresponding to the line L1 exceeds the threshold Num=3. The 1st column is thus divided in driving on the basis of the threshold Num=3 such that four sets each including three drive lines are driven sequentially from the 1st drive line, and the drive line DL13 is then driven. This prevents saturation of the analog integrators6.

In general terms, the above driving is carried out such that [M/Num] sets each including NuM drive lines are driven sequentially from the 1st drive line through to the Num×[M/Num]-th drive line, and drive lines corresponding to a remainder of the (M/Num) are then driven in parallel. In the above description, [x] represents the integer part of x, which also applies in the description below.

The 9th column corresponding to the line L2 exceeds the threshold Num=3. For the 9th column corresponding to the line L2, the 2nd drive line through the 13th drive line are first driven in parallel in accordance with their respective corresponding elements in the code sequence, and the 1st drive line is then driven.

In general terms, the above driving is carried out such that a drive line on a row based on the (2n-1−(M−2n-1))-th row (=(2n−M)-th row) through a drive line on the M-th row are first driven in parallel. Next, [row based on the (2n-1−(M−2n-1)−1)-th row/Num] sets each including NuM drive lines are driven sequentially from the 1st drive line through to the drive line on the (2n-1−(M−2n-1))-th row (=(2n−M)-th row). Then, drive lines other than the (row based on the (2n-1−(M−2n-1)−1)-th row/Num) sets are driven in parallel.

In the example of Embodiment 5, where n=4 and M=13, the (2n-1−(M−2n-1))-th row=the 3rd row. Even in a case where the 3rd drive line through the 13th drive line are driven in parallel, a sum total of corresponding elements present in the code sequence along the column direction is +1, which is 2 less than the threshold Num=3. Thus, even in a case where the 2nd drive line through the 13th drive line are driven in parallel, a sum total of corresponding elements present in the code sequence along the column direction is +2, which is still less than the threshold Num=3. As such, although the (2n-1−(M−2n-1))-th row is the 3rd row, the 2nd row is selected as a row based on the (2n-1−(M−2n-1)-th row (=the 3rd row) in view of the threshold Num, and the 2nd drive line through the 13th drive line are thus driven in parallel.

The 5th column and the 13th column corresponding to the line L3 each exceed the threshold Num=3. For the 5th column and the 13th column corresponding to the line L3, the 1st drive line through the 8th drive line are first simultaneously driven in parallel. The 10th drive line through the 13th drive line are then driven. The 9th drive line is driven next.

In general terms, the 1st drive line through the (2n-1)-th drive line are first simultaneously driven in parallel. Next, a drive line on a row based on the ((2n-1+2n-2)−(M−(2n-1+2n-2)))-th row through a drive line on the M-th row are driven in parallel. Then, [((row based on ((2n-1+2n-2)−(M−(2n-1+2n-2)))))−(2n-1+1)/Num] sets each including NuM drive lines are driven sequentially from the drive line on the (2n-1+1)-th row through to the drive line on the ((row based on the ((2n-1+2n-2)−(M−(2n-1+2n-2))-th row))−1)-th row. Next, drive lines other than the (((row based on ((2n-1+2n-2)−(M−(2n-1+2n-2)))))−(2n-1+1)/Num) sets are driven in parallel.

In the example of Embodiment 5, where n=4 and M=13, the ((2n-1+2n-2)−(M−(2n-1+2n-2)))-th row=the 11th row. Even in a case where the 11th drive line through the 13th drive line are driven in parallel, a sum total of corresponding elements present in the code sequence along the column direction is +1, which is 2 less than the threshold Num=3. Thus, even in a case where the 10th drive line through the 13th drive line are driven in parallel, a sum total of corresponding elements present in the code sequence along the column direction is +2, which is still less than the threshold Num=3. As such, although the ((2n-1+2n-2)−(M−(2n-1+2n-2)))-th row is the 11th row, the 10th row is selected as a row based on the ((2n-1+2n-2)−(M−(2n-1+2n-2)))-th row (=the 11th row) in view of the threshold Num, and the 10th drive line through the 13th drive line are thus driven in parallel.

The following description deals with how the touch sensor panel2is driven in a case where the number of drive lines is 12 or smaller (M≦12). The description below first deals with a case in which 8<M≦12: For each of the line L1 and the line L2, a driving method is identical to a corresponding one described above for the line L1 or the line L2. For the line L3, the drive line on the 1st row through a drive line on the (2n-1)-th row are first driven simultaneously in parallel. Next, [(M−(2n-1))/Num] sets each including NuM drive lines are driven sequentially from a drive line on the ((2n-1)+1)-th row through to a drive line on the (2n-1)+Num×[(M−(2n-1))/Num]-th row. Then, drive lines other than the ((M−(2n-1))/Num) sets are driven in parallel.

The description below now deals with a case in which 4<M≦8: For the line L1, a driving method is identical to that described above for the line L1. For the line L2, a driving method is also identical to that described above for the line L1. For the line L3, a driving method is identical to that described above for the line L2 of the case of M (number of drive lines)=13.

The description below deals with a case in which M≦4: For the line L1, a driving method is identical to that described above for the line L1. For each of the line L2 and the line L3 also, a driving method is identical to that described above for the line L1.

The following description deals with how the touch sensor panel2is driven in a case where the threshold Num=1 and M (number of drive lines)=13: For each of the line L1, the line L2, and the line L3, a driving method is identical to a corresponding one described above for the case in which the threshold Num=3. For the line L4, a drive line on the 1st row through a drive line on the (2n-1+2n-2)-th row are first driven simultaneously in parallel. Next, [(M−(2n-1+2n-2))/Num] sets each including NuM drive lines are driven sequentially from a drive line on the ((2n-1+2n-2)+1)-th row through to a drive line on the (2n-1+2n-2)+Num×[(M−(2n-1+2n-2)) Num]-th row. Then, drive lines other than the ((M−(2n-1+2n-2))/Num) sets are driven in parallel.

A driving method similar to the driving method described above can simply be employed even in a case where the order of the 2n-dimensional Hadamard matrix (where M<2n) is increased to n>4.

Even in a case where the relation between (i) a location in the code sequence along the column direction and (ii) the absolute value of a sum total of corresponding elements along the column direction is not as illustrated inFIG. 13, it is possible to switch rows of the code sequence to carry out the above driving method if such switching allows a 2n-dimensional Hadamard matrix (where M<2n) to be created by Sylvester method so as to satisfy the above relation illustrated inFIG. 13.

Embodiments 1 through 5 above each describe an example of driving drive lines in parallel in accordance with orthogonal code sequences. The present invention is, however, not limited to this. The present invention can alternatively drive drive lines in accordance with code sequences based on an M-sequence.

(a) ofFIG. 14is a diagram for explaining code sequences of the above Embodiments which code sequences are based on an M-sequence. The code sequences d1=(d11, d12, . . . d1N), d2=(d21, d22, . . . d2N), . . . dM=(dM1, dM2, . . . dMN) based on an M-sequence (i) serve to drive in parallel a first drive line through an M-th drive line and (ii) each include elements each being 1 or −1. The code sequences d1, d2, . . . dM based on an M-sequence, assuming that they are sequences resulting from circularly shifting an M-sequence each having a length N (=2n−1), satisfy a condition defined by Formula 8 in (a) ofFIG. 14.

(b) ofFIG. 14is a diagram illustrating a specific example of code sequences based on an M-sequence. (b) ofFIG. 14illustrates code sequences MCS based on an M-sequence which are code sequences of 13 rows×15 columns. The code sequences MCS include a first row which is an M-sequence having a length=15, that is, “1, −1, −1, −1, 1, 1, 1, 1, −1, 1, −1, 1, 1, −1, −1.” The code sequences MCS include a second row which results from circularly shifting the M-sequence on the first row to the left by one element. The code sequences MCS include a third row which results from circularly shifting the M-sequence on the second row to the left by one element. The circular shift continues in the following code sequences. The code sequences MCS thus include a k-th row which results from circularly shifting the M-sequence on the (k−1)-th row to the left by one element (where 2≦k≦13).

Electronic Device Including Touch Sensor System

FIG. 15is a functional block diagram illustrating a configuration of a mobile telephone12including the touch sensor system1. The mobile telephone (electronic device)12includes: a CPU15; a RAM17; a ROM16; a camera21; a microphone18; a loud speaker19; operation keys20; a display panel13; a display control circuit14; and the touch sensor system1. The above constituents are interconnected via a data bus.

The CPU15controls operation of the mobile telephone12. The CPU15, for example, executes a program stored in the ROM16. The operation keys20receive an input of an instruction by a user of the mobile telephone12. The RAM17stores, in a volatile manner, data generated by execution of a program by the CPU15or data inputted with use of the operation keys20. The ROM16stores data in a nonvolatile manner.

The ROM16is a writable, erasable ROM such as EPROM (Erasable Programmable Read-Only Memory) and a flash memory. The mobile telephone12can further include an interface (IF; not shown inFIG. 15) for connecting to another electronic device by wire.

The camera21photographs an object in response to an operation of the operation keys20by the user. Image data of the object thus photographed is stored in the RAM17or an external memory (for example, a memory card). The microphone18receives a speech input from the user. The mobile telephone12digitizes the speech input (analog data), and can transmit the digitized speech input to a communication target (for example, another mobile telephone). The loud speaker19outputs, for example, sound based on data such as music data stored in the RAM17.

The touch sensor system1includes a touch sensor panel2and an integrated circuit3. The CPU15controls operation of the touch sensor system1. The CPU15, for example, executes a program stored in the ROM16. The RAM17stores, in a volatile manner, data generated by execution of a program by the CPU15. The ROM16stores data in a nonvolatile manner.

The display panel13displays, as controlled by the display control circuit14, an image stored in the ROM16or the RAM17. The display panel13either is placed on the touch sensor panel2or contains the touch sensor panel2.

The description below deals first with an overall arrangement of a touch sensor system101including the capacitive touch sensor panel102, and then with an arrangement of the touch sensor panel102itself.

FIG. 16is a block diagram illustrating a configuration of the touch sensor system101of Embodiment 7. The touch sensor system101includes a touch sensor panel102and a capacitance value distribution detecting circuit122. The touch sensor panel102includes: a plurality of horizontal electrodes107(seeFIGS. 17 and 19) extending parallel to one another in the horizontal direction; a plurality of vertical electrodes106(seeFIGS. 17 and 18) extending parallel to one another in the vertical direction; and capacitances formed at respective intersections of the horizontal electrodes107with the vertical electrodes106.

The horizontal electrodes107are connected to respective address lines HL1 to HLM, whereas the vertical electrodes106are connected to respective address lines VL1 to VLM.

The capacitance value distribution detecting circuit122includes a drive section116. The drive section116applies voltages to the respective horizontal electrodes107through the respective address lines HL1 to HLM on the basis of a code sequence to drive the individual capacitances. The capacitance value distribution detecting circuit122further includes a sense amplifier117. The sense amplifier117reads out, through the respective vertical electrodes106and the respective address lines VL1 to VLM, linear sums of electric charge corresponding to the individual capacitances driven by the drive section116, and supplies the linear sums to an AD converter119. The AD converter119carries out an AD conversion of the linear sums, having been read out through the respective address lines VL1 to VLM, of electric charge corresponding to the individual capacitances, and supplies a resulting signal to a capacitance distribution calculating section120.

The present embodiment of the present invention describes an example of (i) applying voltages to the respective horizontal electrodes to drive them and (ii) reading out voltage signals from the respective vertical electrodes. The present invention is, however, not limited to such an arrangement. The present embodiment may alternatively be arranged to (i) apply voltages to the respective vertical electrodes to drive them and (ii) read out voltage signals from the respective horizontal electrodes.

The capacitance distribution calculating section120, as in Embodiments 1 to 5, calculates a capacitance distribution over the touch sensor panel102on the basis of (i) the linear sums, having been supplied from the AD converter119, of electric charge corresponding to the individual capacitances and (ii) the code sequence, and thus supplies a result of the calculation to a touch recognizing section121. The touch recognizing section121, on the basis of the capacitance distribution supplied from the capacitance distribution calculating section120, recognizes the position on a surface of the touch sensor panel102at which position the touch sensor panel102has been touched.

The capacitance value distribution detecting circuit122further includes a timing generator118. The timing generator118generates (i) a signal that regulates the operation of the drive section116, (ii) a signal that regulates the operation of the sense amplifier117, and (iii) a signal that regulates the operation of the AD converter119. The timing generator118thus supplies such respective signals to the drive section116, the sense amplifier117, and the AD converter119.

(Configuration of Touch Sensor Panel102)

FIG. 2is a cross-sectional view illustrating a structure of the touch sensor panel102, which is included in the touch sensor system101. The touch sensor panel102includes: a substrate103(insulator); a plurality of vertical electrodes106provided on a first surface104(vertical electrode surface) of the substrate103; and a plurality of horizontal electrodes107provided on a second surface105(horizontal electrode surface) of the substrate103.

The substrate103is an insulating dielectric substrate. The substrate103is disposed between the vertical electrodes106and the horizontal electrodes107to insulate the vertical electrodes106from the horizontal electrodes107. The substrate103is provided with, on the side of the vertical electrodes106, a transparent adhesive113that covers the vertical electrodes106. The transparent adhesive113is provided with a cover film115adhered to a surface thereof. The substrate103is provided with, on the side of the horizontal electrodes107, a transparent adhesive114that covers the horizontal electrodes107. To the transparent adhesive114is attached a display112.

(a) ofFIG. 18is a diagram illustrating a first basic shape108of a vertical electrode106included in the touch sensor panel102. (b) ofFIG. 18is a diagram illustrating an arrangement of vertical electrodes106.

The vertical electrodes106are, as mentioned above with reference toFIG. 17, provided on the first surface104of the substrate103. Each vertical electrode106includes a sequence of a repeat of first basic shapes108each formed of fine wires illustrated in (a) ofFIG. 18, the first basic shapes108being connected to one another in a vertical direction as illustrated in (b) ofFIG. 18. Each first basic shape108has line symmetry with respect to a vertical center line C1, and consists only of (i) a fine wire inclined at an oblique angle of degrees and (ii) a fine wire inclined at an angle of negative 45 degrees. The vertical electrodes106are provided on the first surface104(seeFIG. 17) of the substrate103and arranged at predetermined intervals (for example, with a pitch of approximately 7 mm) in the horizontal direction.

Such inclined fine wires forming each first basic shape108do not block pixels included in a liquid crystal display112on which the touch sensor panel102is placed This arrangement thus prevents moire from occurring.

(a) ofFIG. 19is a diagram illustrating a second basic shape109of a horizontal electrode107included in the touch sensor panel102. (b) ofFIG. 19is a diagram illustrating an arrangement of horizontal electrodes107.

The horizontal electrodes107are, as mentioned above with reference toFIG. 17, provided on the second surface105of the substrate103. Each horizontal electrode107includes a sequence of a repeat of second basic shapes109each formed of fine wires illustrated in (a) ofFIG. 19, the second basic shapes109being connected to one another in a horizontal direction as illustrated in (b) ofFIG. 19. Each second basic shape109has line symmetry with respect to the vertical center line C1, and similarly to the first basic shapes108, consists only of (i) a fine wire inclined at an oblique angle of 45 degrees and (ii) a fine wire inclined at an angle of negative 45 degrees. The horizontal electrodes107are provided on the second surface105(seeFIG. 17) of the substrate103and arranged at predetermined intervals (for example, with a pitch of approximately 7 mm) in the vertical direction.

The vertical electrodes106and the horizontal electrodes107are each formed by, for example, etching a metal thin film or printing a pattern with an ink including electrically conductive nanoparticles. Such electrically conductive nanoparticles include silver, gold, platinum, palladium, copper, carbon, or a mixture of any of the above.

FIG. 20is a diagram illustrating a uniform grid110including the plurality of vertical electrodes106and the plurality of horizontal electrodes107. The vertical electrodes106and the horizontal electrodes107are so disposed that as viewed in the direction perpendicular to the substrate103(seeFIG. 17), the vertical electrodes106include no segment coincident with the horizontal electrodes107. The vertical electrodes106and the horizontal electrodes107are disposed uniformly to form a grid110with no gap. The grid110has an outline in a rectangular shape.

The basic shapes108constituting the vertical electrodes106and the basic shapes109constituting the horizontal electrodes107each have line symmetry. The vertical electrodes106and the horizontal electrodes107form a grid110, which has no gap. This arrangement solves the problem caused in, for example, the conventional arrangement illustrated inFIG. 42, that is, the problem of cross-shaped openings97that are not covered by a grid, the openings97being visibly recognized, with the result of decreased visibility. The conventional arrangement illustrated inFIG. 42poses another problem that the capacitance in a portion surrounding an opening97is changed differently from that in a portion away from the opening97. The arrangement of Embodiment 7 illustrated inFIG. 20, which causes no opening, advantageously allows a capacitance to change in a uniform manner over the entire substrate103.

The arrangement illustrated inFIG. 43includes: vertical electrodes71each formed by (i) forming a repeat of basic shapes74in the vertical direction and then (ii) joining, to the repeat of basic shapes74, a basic shape75different from the basic shapes74; and horizontal electrodes1072each formed by (i) forming a repeat of basic shape76in the horizontal direction and then (ii) joining, to the repeat of basic shapes76, a basic shape77different from the basic shapes76. The vertical electrodes71and the horizontal electrodes1072are placed on top of each other to form a grid73(seeFIG. 44), which has (i) along its bottom side, a zigzag shape78due to the basic shapes75and (ii) along its left side, a zigzag shape79due to the basic shapes77. These zigzag shapes78and79problematically make it difficult to (i) easily join, directly to the horizontal electrodes1072forming the zigzag shape79, respective address lines for driving the horizontal electrodes1072, and (ii) easily join, directly to the vertical electrodes71forming the zigzag shape78, respective address lines for driving the vertical electrodes71.

In contrast, the arrangement of Embodiment 7 illustrated inFIG. 20includes a grid110having a rectangular outline and no zigzag shape. This arrangement thus makes it possible to (i) easily join, directly to the horizontal electrodes107, respective address lines for driving the horizontal electrodes107, and (ii) easily join, directly to the vertical electrodes106, respective address lines for reading out signals from the vertical electrodes106.

The arrangement illustrated in (a) ofFIG. 45includes conductive X sequences62each formed by (i) forming, in the vertical direction, a repeat of basic shapes each combining a conductive X pad63with a conductive X line64and then (ii) joining, to the repeat of basic shapes, conductive X pads63a, each of which is a basic shape different from the basic shape combining a conductive X pad63with a conductive X line64. Thus, the conductive X sequences62illustrated in (a) ofFIG. 45are not formed of a repeat of basic shapes connected to one another in the vertical direction, and are thus different in configuration from the vertical electrodes106of Embodiment 7 illustrated inFIG. 18.

The arrangement illustrated in (b) ofFIG. 45includes conductive Y sequences67each formed by (i) forming, in the horizontal direction, a repeat of basic shapes each combining a conductive Y pad68with a conductive Y line69and then (ii) joining, to the repeat of basic shapes, conductive Y pads68a, each of which is a basic shape different from the basic shape combining a conductive Y pad68with a conductive Y line69. Thus, the conductive Y sequences67illustrated in (b) ofFIG. 45are not formed of a repeat of basic shapes connected to one another in the horizontal direction, and are thus different in configuration from the horizontal electrodes107of Embodiment 7 illustrated inFIG. 19.

As described above, an embodiment of the present invention includes a repeat of basic shapes connected to one another in the vertical or horizontal direction. This arrangement facilitates design of a vertical electrode and a horizontal electrode, and makes it possible to carry out, for example, an automatic creation and an automatic correction of an electrode. The above arrangement further allows a photolithographic mask for use in production of a touch panel and touch panel products to be inspected by a repeated image processing. The above arrangement thus also facilitates the production of a touch panel.

The arrangement illustrated inFIG. 45also poses the following problem: In the case where the conductive X pads63and the conductive Y pads68are each formed of fine wires extending in oblique directions that are not parallel to the Y axis or the X axis, it is impossible to form a uniform grid since (i) the conductive X lines64need to be parallel to the Y axis, and (ii) the conductive Y lines69need to be parallel to the X axis.

The touch sensor panel102of Embodiment 7 can be produced by either forming vertical electrodes106and horizontal electrodes107on respective surfaces of a single sheet (substrate103) as illustrated inFIG. 17, or combining (i) a sheet on which vertical electrodes106are formed with (ii) a sheet on which horizontal electrodes107are formed. Either case involves the possibility that due to positioning accuracy or combining accuracy, the resulting positional relationship between the vertical electrodes106and the horizontal electrodes107is subtly shifted from the positional relationship disclosed in Embodiment 7. This necessitates determining positioning accuracy or combining accuracy for the touch panel production in correspondence with a required accuracy of detecting a touch position.

(a) ofFIG. 21is a diagram illustrating a first basic shape108aof a vertical electrode106aincluded as a variation in the touch sensor panel102. (b) ofFIG. 21is a diagram illustrating an arrangement of vertical electrodes106aaccording to the variation. Each first basic shape108ais so arranged that the wiring path for fine wires in the upper half is connected to the wiring path for fine wires in the lower half at a junction Q1 narrowed to the width of a single fine wire. Each first basic shape108ahas line symmetry with respect to a vertical center line C1.

(a) ofFIG. 22is a diagram illustrating a second basic shape109aof a horizontal electrode107aincluded as a variation in the touch sensor panel102. (b) ofFIG. 22is a diagram illustrating an arrangement of horizontal electrodes107aaccording to the variation. Each second basic shape109ais so arranged that (i) the wiring path for fine wires in a left portion is connected to the wiring path for fine wires in a central portion at a junction Q2 narrowed to the width of a single fine wire and that (ii) the wiring path for fine wires in the central portion is connected to the wiring path for fine wires in a right portion at a junction Q3 narrowed to the width of a single fine wire. Each second basic shape109ahas line symmetry with respect to the vertical center line C1.

FIG. 23is a diagram illustrating a uniform grid110aincluding the vertical electrodes106aas a variation and the horizontal electrodes107aas a variation. As in the grid110illustrated inFIG. 20, the vertical electrodes106aand the horizontal electrodes107aare so disposed that as viewed in the direction perpendicular to the substrate103(seeFIG. 17), the vertical electrodes106ainclude no segment coincident with the horizontal electrodes107a. The vertical electrodes106aand the horizontal electrodes107aare disposed uniformly to form a grid110awith no gap. The grid110ahas an outline in a rectangular shape.

The respective arrangements of the vertical electrodes106a, the horizontal electrodes107a, and the grid110aillustrated inFIGS. 21 through 23achieve advantages similar to those achieved by the respective arrangements of the vertical electrodes106, the horizontal electrodes107, and the grid110illustrated inFIGS. 18 through 20.

(a) ofFIG. 24is a diagram illustrating a configuration of a first basic shape108aof a vertical electrode106aas a variation, the first basic shape108abeing filled with a transparent electrode material123. (b) ofFIG. 24is a diagram illustrating the vertical electrodes106aas a variation, the vertical electrodes106abeing filled with the transparent electrode material123. (a) ofFIG. 25is a diagram illustrating a configuration of a second basic shape109aof a horizontal electrode107aas a variation, the second basic shape109abeing filled with the transparent electrode material123. (b) ofFIG. 25is a diagram illustrating the horizontal electrodes107aas a variation, the horizontal electrodes107abeing filled with the transparent electrode material123.

In the case where the vertical electrodes106a, each including the first basic shapes108a, are filled with the transparent electrode material123to its contour as illustrated inFIG. 24, the vertical electrodes106aeach have an even lower resistance value. In the case where the horizontal electrodes107a, each including the second basic shapes109a, are filled with the transparent electrode material123substantially to its contour as illustrated inFIG. 25, the horizontal electrodes107aeach have an even lower resistance value. The transparent electrode material123can be made of, for example, an ITO film or graphene.

The above arrangement can further reduce the width of the fine wires, and thus reduce visibility of the fine wires. In the case where the fine wires each have a width of, for example, 0.5 mm or larger, a viewer, when close to a screen of a display device including the touch panel, visibly recognizes the fine wires.

(a) ofFIG. 26is a diagram illustrating an arrangement of the vertical electrodes106a, as a variation, connected to the respective address lines VL1 to VLM. (b) ofFIG. 26is a diagram illustrating an arrangement of the horizontal electrodes107a, as a variation, connected to the respective address lines HL1 to HLM. (c) ofFIG. 26is a diagram illustrating a grid110aincluding (i) the vertical electrodes106aconnected to the respective address lines VL1 to VLM and (ii) the horizontal electrodes107aconnected to the respective address lines HL1 to HLM.

The grid110a, which includes the vertical electrodes106aand the horizontal electrodes107a, has a rectangular outline and no zigzag shape as in the grid110. This arrangement thus makes it possible to (i) easily join, directly to the horizontal electrodes107a, the respective address lines HL1 to HLM for driving the horizontal electrodes107a, and (ii) easily join, directly to the vertical electrodes106a, the respective address lines VL1 to VLM for reading out signals from the vertical electrodes106a.

Configuration of Vertical Electrodes106b

(a) ofFIG. 27is a diagram illustrating a first basic shape108bof a vertical electrode106bincluded in a touch panel of Embodiment 8. (b) ofFIG. 27is a diagram illustrating a configuration of a vertical electrode106b. The vertical electrodes106bare, as mentioned above with reference toFIG. 17, provided on the first surface104of the substrate103. Each vertical electrode106bincludes a sequence of a repeat of first basic shapes108beach formed of fine wires, the first basic shapes108bbeing connected to one another in the vertical direction. Each first basic shape108bhas point symmetry with respect to a center point P, and consists only of (i) a fine wire inclined at an oblique angle of 45 degrees and (ii) a fine wire inclined at an angle of negative 45 degrees. The vertical electrodes106bare provided on the first surface104(seeFIG. 17) of the substrate103and arranged at predetermined intervals (for example, with a pitch of approximately 7 mm) in the horizontal direction.

(a) ofFIG. 28is a diagram illustrating a second basic shape109bof a horizontal electrode107bincluded in the touch panel of Embodiment 8. (b) ofFIG. 28is a diagram illustrating a configuration of a horizontal electrode107b. The horizontal electrodes107bare, as mentioned above with reference toFIG. 17, provided on the second surface105of the substrate103. Each horizontal electrode107bincludes a sequence of a repeat of second basic shapes109beach formed of fine wires illustrated in (a) ofFIG. 28, the second basic shapes109bbeing connected to one another in the horizontal direction. Each second basic shape109bhas point symmetry with respect to the center point P, and similarly to the first basic shapes108b, consists only of (i) a fine wire inclined at an oblique angle of 45 degrees and (ii) a fine wire inclined at an angle of negative 45 degrees. The horizontal electrodes107bare provided on the second surface105of the substrate103and arranged at predetermined intervals (for example, with a pitch of approximately 7 mm) in the vertical direction.

Configuration of Vertical Electrodes106c

(a) ofFIG. 29is a diagram illustrating a first basic shape108cof a vertical electrode106cincluded in a touch panel of Embodiment 9. (b) ofFIG. 29is a diagram illustrating a configuration of a vertical electrode106c. The vertical electrodes106care provided on the first surface104of the substrate103illustrated inFIG. 17. Each vertical electrode106cincludes a sequence of a repeat of first basic shapes108ceach formed of fine wires, the first basic shapes108bbeing connected to one another in the vertical direction. Each first basic shape108chas line symmetry with respect to (i) a vertical center line C1and (ii) a horizontal center line C2, and consists only of (i) a fine wire inclined at an oblique angle of 45 degrees and (ii) a fine wire inclined at an angle of negative 45 degrees. The vertical electrodes106care provided on the first surface104(seeFIG. 17) of the substrate103and arranged at predetermined intervals (for example, with a pitch of approximately 7 mm) in the horizontal direction.

(a) ofFIG. 30is a diagram illustrating a second basic shape109cof a horizontal electrode107cincluded in the touch panel of Embodiment 9. (b) ofFIG. 30is a diagram illustrating a configuration of a horizontal electrode107c. The horizontal electrodes107care provided on the second surface105of the substrate103illustrated inFIG. 17. Each horizontal electrode107cincludes a sequence of a repeat of second basic shapes109ceach formed of fine wires, the second basic shapes109bbeing connected to one another in the horizontal direction. Each second basic shape109chas line symmetry with respect to (i) the vertical center line C1and (ii) the horizontal center line C2, and consists only of (i) a fine wire inclined at an oblique angle of 45 degrees and (ii) a fine wire inclined at an angle of negative 45 degrees. The horizontal electrodes107care provided on the second surface105of the substrate103and arranged at predetermined intervals (for example, with a pitch of approximately 7 mm) in the vertical direction.

(Advantage Achieved by Symmetry of Vertical Electrodes and Horizontal Electrodes)

The conventional arrangement illustrated inFIG. 43includes vertical electrodes71and horizontal electrodes1072none of which has center-line symmetry or center-point symmetry. Thus, a capacitive touch sensor having an electrode distribution illustrated inFIG. 43lacks positional symmetry in a capacitance change caused by an object having a small touch area. This problematically makes it impossible to carry out a symmetric position correction during a touch-position detection, and thus requires a complicated algorithm for increasing the position detection precision. This problem leads to an increase in the amount of necessary computation, circuit complexity, and a memory usage amount, and results in an increase in, for example, power consumption and cost.

In contrast, vertical electrodes or horizontal electrodes having line symmetry or point symmetry allow a similar symmetry to occur in a capacitance change caused by an object, such as a pen, that has a small touch area. Utilizing this symmetry in a capacitance change allows a symmetric position correction to be carried out during a touch-position detection, and thus increases the position detection precision.

As described above, to solve the problem with the position detection precision, an embodiment of the present invention includes an arrangement of diamond shapes each formed by fine lines and having symmetry. This arrangement allows a large capacitive touch sensor having a size of 30 inches or larger to highly precisely carry out a position detection involving use of an object, such as a pen, that has a small touch area.

Arrangement of Vertical Electrodes106d

(a) ofFIG. 31is a diagram illustrating a first basic shape108dof a vertical electrode106dincluded in a touch panel of Embodiment 10. (b) ofFIG. 31is a diagram illustrating a configuration of a vertical electrode106d. The vertical electrodes106deach correspond to a vertical electrode106a(seeFIG. 21) except for a grid pitch that is 7/5 times larger. Each first basic shape108dis so arranged that the wiring path for fine wires in the upper half is connected to the wiring path for fine wires in the lower half at a junction Q4 narrowed to the width of a single fine wire. Each first basic shape108dhas line symmetry with respect to a vertical center line C1.

(a) ofFIG. 32is a diagram illustrating a second basic shape109dof a horizontal electrode107dincluded in the touch panel of Embodiment 10. (b) ofFIG. 32is a diagram illustrating a configuration of a horizontal electrode107d. The horizontal electrodes107deach correspond to a horizontal electrode107a(seeFIG. 22) except for a grid pitch that is 7/5 times larger. Each second basic shape109dis so arranged that (i) the wiring path for fine wires in a left portion is connected to the wiring path for fine wires in a central portion at a junction Q5 narrowed to the width of a single fine wire and that (ii) the wiring path for fine wires in the central portion is connected to the wiring path for fine wires in a right portion at a junction Q6 narrowed to the width of a single fine wire. Each second basic shape109dhas line symmetry with respect to the vertical center line C1.

Arrangement of Vertical Electrodes106e

(a) ofFIG. 33is a diagram illustrating a first basic shape108eof a vertical electrode106eincluded in a touch panel of Embodiment 11. (b) ofFIG. 33is a diagram illustrating a configuration of a vertical electrode106e. The vertical electrodes106eeach include a sequence of a repeat of first basic shapes108eeach formed of fine wires, the first basic shapes108ebeing connected to one another in the vertical direction. Each first basic shape108ehas line symmetry with respect to a vertical center line C1.

Each first basic shape108eis so arranged that (i) the wiring path for fine wires in the upper half is connected to the wiring path for fine wires in the lower half not at a point narrowed to the width of a single fine wire and that (ii) the fine wires in the upper half are instead connected in the vertical direction to the fine wires in the lower half at two or more points along any horizontal line.

(a) ofFIG. 34is a diagram illustrating a second basic shape109eof a horizontal electrode107eincluded in the touch panel of Embodiment 11. (b) ofFIG. 34is a diagram illustrating a configuration of a horizontal electrode107e. The horizontal electrodes107eeach include a sequence of a repeat of second basic shapes109eeach formed of fine wires, the second basic shapes109ebeing connected to one another in the horizontal direction. Each second basic shape109ehas line symmetry with respect to the vertical center line C1.

Each second basic shape109eis so arranged that (i) the wiring path for fine wires in a left portion is connected to the wiring path for fine wires in a right portion not at a point narrowed to the width of a single fine wire and that (ii) the fine wires in the left portion are instead connected in the horizontal direction to the fine wires in the right portion at two or more points along any vertical line.

FIG. 35is a diagram illustrating a uniform grid110eincluding the vertical electrodes106eand the horizontal electrodes107e. The vertical electrodes106eand the horizontal electrodes107eare so disposed that as viewed in the direction perpendicular to the substrate103(seeFIG. 17), the vertical electrodes106einclude no segment coincident with the horizontal electrodes107e. The vertical electrodes106eand the horizontal electrodes107eare disposed uniformly to form a grid110ewith no gap. The grid110ehas an outline in a rectangular shape.

(a) ofFIG. 36is a diagram illustrating a first basic shape108fof another vertical electrode106fincluded in the touch panel of Embodiment 11. (b) ofFIG. 36is a diagram illustrating a configuration of such another vertical electrode106f. The vertical electrodes106feach include a sequence of a repeat of first basic shapes108feach formed of fine wires, the first basic shapes108fbeing connected to one another in the vertical direction. Each first basic shape108fhas line symmetry with respect to a vertical center line C1.

As in the basic shapes108e, each first basic shape108fis so arranged that (i) the wiring path for fine wires in the upper half is connected to the wiring path for fine wires in the lower half not at a point narrowed to the width of a single fine wire and that (ii) the fine wires in the upper half are instead connected in the vertical direction to the fine wires in the lower half at two or more points along any horizontal line.

(a) ofFIG. 37is a diagram illustrating a second basic shape109fof another horizontal electrode107fincluded in the touch panel of Embodiment 11. (b) ofFIG. 37is a diagram illustrating a configuration of such another horizontal electrode107f. The horizontal electrodes107feach include a sequence of a repeat of second basic shapes109feach formed of fine wires, the second basic shapes109fbeing connected to one another in the horizontal direction. Each second basic shape109fhas line symmetry with respect to the vertical center line C1.

Each second basic shape109eis so arranged that (i) the wiring path for fine wires in a left portion is connected to the wiring path for fine wires in a right portion not at a point narrowed to the width of a single fine wire and that (ii) the fine wires in the left portion are instead connected in the horizontal direction to the fine wires in the right portion at two or more points along any vertical line.

The arrangement illustrated inFIG. 43poses another inherent problem: The vertical electrodes71of (a) ofFIG. 43and the horizontal electrodes1072of (b) ofFIG. 43each have a point at which a wiring path is connected to another, the point being narrowed to the width of a single fine wire. If a fine wire is broken at such a point, narrowed to the width of a single fine wire, during production of a touch sensor panel, electric current is prevented from flowing through any of the connected electrodes. Thus, production involving the possibility of a broken fine wire problematically decreases the yield of the touch sensor panel.

In contrast, an embodiment of the present invention is so arranged that (i) none of the first basic shapes108eand108fand the second basic shapes109eand109fincludes a point at which a wiring path is connected to another, the point being narrowed to the width of a single fine wire and that (ii) fine wires are instead connected to each other at two or more points along any vertical or horizontal line. Thus, even if one fine wire is broken during production, the remaining fine wire maintains connection. This arrangement can advantageously prevent disconnection in the vertical electrodes106eand106fand the horizontal electrodes107eand107f.

(Configurations of First Basic Shape108gand Second Basic Shape109gas Variation)

(a) ofFIG. 38is a diagram illustrating a first basic shape108gas a variation. (b) ofFIG. 38is a diagram illustrating a second basic shape109gas a variation.

Each first basic shape108gis so arranged that (i) the wiring path for fine wires in the upper half is connected to the wiring path for fine wires in the lower half not at a point narrowed to the width of a single fine wire and that (ii) the fine wires in the upper half are instead connected in the vertical direction to the fine wires in the lower half at two or more points along any horizontal line. Each first basic shape108ghas point symmetry with respect to a center point P.

Each second basic shape109gis so arranged that (i) the wiring path for fine wires in a left portion is connected to the wiring path for fine wires in a right portion not at a point narrowed to the width of a single fine wire and that (ii) the fine wires in the left portion are instead connected in the horizontal direction to the fine wires in the right portion at two or more points along any vertical line. Each second basic shape109ghas point symmetry with respect to the center point P.

(Configurations of First Basic Shape108hand Second Basic Shape109has Another Variation)

(a) ofFIG. 39is a diagram illustrating a first basic shape108has another variation. (b) ofFIG. 39is a diagram illustrating a second basic shape109has another variation.

Each first basic shape108his so arranged that (i) the wiring path for fine wires in the upper half is connected to the wiring path for fine wires in the lower half not at a point narrowed to the width of a single fine wire and that (ii) the fine wires in the upper half are instead connected in the vertical direction to the fine wires in the lower half at two or more points along any horizontal line. Each first basic shape108hhas line symmetry with respect to a vertical center line C1and a horizontal center line C2.

Each second basic shape109his so arranged that (i) the wiring path for fine wires in a left portion is connected to the wiring path for fine wires in a right portion not at a point narrowed to the width of a single fine wire and that (ii) the fine wires in the left portion are instead connected in the horizontal direction to the fine wires in the right portion at two or more points along any vertical line. Each second basic shape109hhas line symmetry with respect to the vertical center line C1and the horizontal center line C2.

Configuration of Electronic Blackboard150

FIG. 40is a diagram illustrating an appearance of an electronic blackboard50(information input-output device) of Embodiment 12. The electronic blackboard150includes a touch sensor system101of an embodiment of the present invention, the touch sensor system101in turn including a touch sensor panel102of an embodiment of the present invention. The touch sensor panel102is, for example, approximately 80 inches in size.

(Other Expressions of the Present Invention)

In order to solve the above problem, a linear system coefficient estimating method of the present invention includes the steps of: (A) (a) inputting, on a basis of M code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and each of which has a length N, M inputs Xk (k=1, . . . , M) to a system which has a linear input and output and to which the M inputs Xk (k=1, . . . , M) are to be inputted, the system being represented by

With the above feature, the linear system coefficient estimating method inputs M inputs Xk (k=1, . . . , M) on the basis of M code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and each of which has a length N and outputs N outputs s=(s1, s2, . . . , sN)=(F (d11, d21, . . . , dM1), F (d12, d22, . . . , dM2), . . . , F (d1N, d2N, . . . , dMN)). The linear system coefficient estimating method thus estimates a coefficient Ck of the linear system by simultaneously inputting all the M inputs. The linear system coefficient estimating method consequently (i) eliminates the need to sequentially select one of M inputs and scan it for an input as in conventional arrangements and (ii) even with an increase in the number M of inputs, does not shorten a process time for obtaining a coefficient value of the linear system. The linear system coefficient estimating method thus maintains a good detection accuracy and achieves a good resolution and a high-speed operation.

Another linear system coefficient estimating method of the present invention includes the steps of: (A) (a) inputting, on a basis of M code sequences di (=di1, di2, . . . , diN, where i=M) which are orthogonal to one another and each of which has a length N, M inputs Xk (k=1, . . . , M) to each of a first system and a second system each of which has a linear input and output and to each of which the M inputs Xk (k=1, . . . , M) are to be inputted, the first and second systems being represented by

With the above feature, the linear system coefficient estimating method inputs M inputs xk (k=1, . . . , M) on the basis of M code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and each of which has a length N, and outputs N outputs sFirst=(s11, s12, . . . , s1N)=(F1 (d11, d21, . . . , dM1), F1 (d12, d22, . . . , dM2), . . . , F1 (d1N, d2N, . . . , dMN)) from the first system and N outputs sSecond=(s21, s22, . . . , s2N)=(F2 (d11, d21, . . . , dM1), F2 (d12, d22, . . . , dM2), . . . , F2 (d1N, d2N, . . . , dMN)) from the second system. The linear system coefficient estimating method thus estimates a coefficient C1k of the first system and a coefficient C2k of the second system by simultaneously inputting all the M inputs. The linear system coefficient estimating method consequently (i) eliminates the need to sequentially select one of M inputs and scan it for an input as in conventional arrangements and (ii) even with an increase in the number M of inputs, does not shorten a process time for obtaining coefficient values of the first and second linear systems. The linear system coefficient estimating method thus maintains a good detection accuracy and achieves a good resolution and a high-speed operation.

A linear device column value estimating method of the present invention includes the steps of: (A) (a) driving, on a basis of M code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and each of which has a length N, M drive lines in parallel for each of (I) a first linear device column C (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second linear device column C2i (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting N outputs sFirst=(s11, s12, . . . , s1N) from the first linear device column and N outputs sSecond=(s21, s22, . . . , s2N) from the second linear device column; and (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first linear device value in the first linear device column which first linear device value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second linear device value in the second linear device column which second linear device value corresponds to a k2-th drive line.

With the above feature, the linear device column value estimating method (a) drives M drive lines in parallel on the basis of M code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and each of which has a length N, and (b) outputs N outputs sFirst=(s11, s12, . . . , s1N) from the first linear device column and N outputs sSecond=(s21, s22, . . . , s2N) from the second linear device column. The linear device column value estimating method thus estimates (a) a first linear device value in the first linear device column and (b) a second linear device value in the second linear device column by simultaneously driving all the M drive lines. The linear device column value estimating method consequently (i) eliminates the need to sequentially select one of M drive lines and scan it for an input as in conventional arrangements, and (ii) extends a process time for obtaining a first linear device value in the first linear device column and a second linear device value in the second linear device column. The linear device column value estimating method thus maintains a good detection accuracy and achieves a good resolution and a high-speed operation.

A capacitance detecting method of the present invention includes the steps of: (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column C1i (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column C2i (i=1, . . . , M) formed between the M drive lines and a second sense line, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line.

With the above feature, the capacitance detecting method (a) drives, on the basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and (b) outputs outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column. The capacitance detecting method thus estimates, by simultaneously driving all the M drive lines, (a) a first capacitance value in the first capacitance column which first capacitance value corresponds to the k1-th drive line and (b) a second capacitance value in the second capacitance column which second capacitance value corresponds to the k2-th drive line. The capacitance detecting method consequently (i) eliminates the need to sequentially select one of M drive lines and scan it for an input as in conventional arrangements, and (ii) extends a process time for obtaining (a) a first capacitance value in the first capacitance column which first capacitance value corresponds to the k1-th drive line and (b) a second capacitance value in the second capacitance column which corresponds to the k2-th drive line. The capacitance detecting method thus maintains a good detection accuracy and achieves a good resolution and a high-speed operation.

Further, the capacitance detecting method drives all the M drive lines in parallel each at either a voltage +V or a voltage −V in accordance with the code sequences. The capacitance detecting method thus (i) increases an amount of information contained in output signals from a capacitance column and (ii) improves a S/N ratio, as compared to the arrangement of Patent Literature 2, which groups the drive lines for driving in accordance with code sequences. The capacitance detecting method simply carries out a single-stage operation as compared to the arrangement of Patent Literature 2, which carries out a two-stage operation, and is consequently advantageous in achieving a high-speed operation.

An integrated circuit of the present invention includes: a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length. N, M drive lines in parallel for each of (I) a first capacitance column C1i (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column C2i (i=1, . . . , M) formed between the M drive lines and a second sense line, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line.

With the above feature, the drive section (a) drives, on the basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputs outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column. The integrated circuit thus estimates, by driving all the M drive lines, (a) a first capacitance value in the first capacitance column which first capacitance value corresponds to the k1-th drive line and (b) a second capacitance value in the second capacitance column which second capacitance value corresponds to the k2-th drive line. The integrated circuit for use in a capacitance detecting method consequently (i) eliminates the need to sequentially select one of M drive lines and scan it for an input as in conventional arrangements, and (ii) extends a process time for estimating (a) a first capacitance value in the first capacitance column which first capacitance value corresponds to the k1-th drive line and (b) a second capacitance value in the second capacitance column which corresponds to the k2-th drive line. The capacitance detecting method thus maintains a good detection accuracy and achieves a good resolution and a high-speed operation.

Further, the capacitance detecting method drives all the M drive lines in parallel each at either a voltage +V or a voltage −V in accordance with the code sequences. The capacitance detecting method thus (i) increases an amount of information contained in output signals from a capacitance column and (ii) improves a S/N ratio, as compared to the arrangement of Patent Literature 2, which groups the drive lines for driving in accordance with code sequences. The capacitance detecting method simply carries out a single-stage operation as compared to the arrangement of Patent Literature 2, which carries out a two-stage operation, and is consequently advantageous in achieving a high-speed operation.

A touch sensor system of the present invention includes: a sensor panel including (I) a first capacitance column C1i (i=1, . . . , M) formed between M drive lines and a first sense line and (II) a second capacitance column C2i (i=1, . . . , M) formed between the M drive lines and a second sense line; and an integrated circuit for controlling the sensor panel, the integrated circuit including: a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, the M drive lines in parallel for each of (I) the first capacitance column C1i (i=1, . . . , M) and (II) the second capacitance column C2i (i=1, . . . , M) so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line.

With the above feature, the drive section (a) drives, on the basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputs outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column. The touch sensor system thus estimates, by driving all the M drive lines, (a) a first capacitance value in the first capacitance column which first capacitance value corresponds to the k1-th drive line and (b) a second capacitance value in the second capacitance column which second capacitance value corresponds to the k2-th drive line. The touch sensor system consequently (i) eliminates the need to sequentially select one of M drive lines and scan it for an input as in conventional arrangements, and (ii) extends a process time for estimating (a) a first capacitance value in the first capacitance column which first capacitance value corresponds to the k1-th drive line and (b) a second capacitance value in the second capacitance column which corresponds to the k2-th drive line. The capacitance detecting method thus maintains a good detection accuracy and achieves a good resolution and a high-speed operation.

Further, the capacitance detecting method drives all the M drive lines in parallel each at either a voltage +V or a voltage −V in accordance with the code sequences. The capacitance detecting method thus (i) increases an amount of information contained in output signals from a capacitance column and (ii) improves a S/N ratio, as compared to the arrangement of Patent Literature 2, which groups the drive lines for driving in accordance with code sequences. The capacitance detecting method simply carries out a single-stage operation as compared to the arrangement of Patent Literature 2, which carries out a two-stage operation, and is consequently advantageous in achieving a high-speed operation.

An electronic device of the present invention includes: the touch sensor system of the present invention; and a display panel which either is placed on the sensor panel included in the touch sensor system or contains the sensor panel.

With the above feature, the drive section (a) drives, on the basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputs outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column. The touch sensor system thus estimates, by driving all the M drive lines, (a) a first capacitance value in the first capacitance column which first capacitance value corresponds to the k1-th drive line and (b) a second capacitance value in the second capacitance column which second capacitance value corresponds to the k2-th drive line. The electronic device including the touch sensor system consequently (i) eliminates the need to sequentially select one of M drive lines and scan it for an input as in conventional arrangements, and (ii) extends a process time for estimating (a) a first capacitance value in the first capacitance column which first capacitance value corresponds to the k1-th drive line and (b) a second capacitance value in the second capacitance column which corresponds to the k2-th drive line. The capacitance detecting method thus maintains a good detection accuracy and achieves a good resolution and a high-speed operation.

Further, the capacitance detecting method drives all the M drive lines in parallel each at either a voltage +V or a voltage −V in accordance with the code sequences. The capacitance detecting method thus (i) increases an amount of information contained in output signals from a capacitance column and (ii) improves a S/N ratio, as compared to the arrangement of Patent Literature 2, which groups the drive lines for driving in accordance with code sequences. The capacitance detecting method simply carries out a single-stage operation as compared to the arrangement of Patent Literature 2, which carries out a two-stage operation, and is consequently advantageous in achieving a high-speed operation.

A capacitance detecting method of the present invention includes the steps of: (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and Include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the step (A) driving, when the analog integrator is reset, the M drive lines at a first voltage represented by a voltage Vref and driving, when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the M drive lines at (i) a second voltage for an element of +1 in the code sequences, the second voltage being represented by a voltage (Vref+V), and (ii) a third voltage for an element of −1 in the code sequences, the third voltage being represented by a voltage (Vref−V).

The above feature makes it possible to drive the drive lines in parallel with use of a simple configuration on the basis of code sequences.

A capacitance detecting method of the present invention includes the steps of: (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the step (A), for an element of +1 in the code sequences, driving the drive lines at (i) a first voltage when the analog integrator is reset and (ii) a second voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled and, for an element of −1 in the code sequences, driving the drive lines at (i) the second voltage when the analog integrator is reset and (ii) the first voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled.

The above feature makes it possible to achieve a higher signal intensity and thus increase an electric charge stored in a capacitance.

A capacitance detecting method of the present invention includes the steps of: (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the capacitance detecting method further including, before the step (A), the step of: (C) (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at a first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator, (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as first offset outputs and second offset outputs, respectively, and (c) storing the first and second offset outputs in a memory.

The above feature makes it possible to cancel an offset caused by an analog integrator.

An integrated circuit of the present invention includes: a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (H) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the drive section, for an element of +1 in the code sequences, driving the drive lines at (i) a first voltage when the analog integrator is reset and (ii) a second voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled and, for an element of −1 in the code sequences, driving the drive lines at (i) the second voltage when the analog integrator is reset and (ii) the first voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled.

The above feature makes it possible to achieve a higher signal intensity and thus increase an electric charge stored in a capacitance.

An integrated circuit of the present invention includes: a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the drive section, before outputting the outputs sFirst and sSecond from the first and second capacitance columns to the analog integrator, (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at a first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator, (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as first offset outputs and second offset outputs, respective, and (c) storing the first and second offset outputs in a memory.

The above feature makes it possible to cancel an offset caused by an analog integrator.

A touch sensor system of the present invention includes: a sensor panel including (I) a first capacitance column Ci1 (i=1, . . . , M) formed between M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line; and an integrated circuit for controlling the sensor panel, the integrated circuit including: a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, the M drive lines in parallel for each of (I) the first capacitance column Ci1 (i=1, . . . , M) and (II) the second capacitance column Ci2 (i=1, . . . , M), and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the drive section, for an element of +1 in the code sequences, driving the drive lines at (i) a first voltage when the analog integrator is reset and (ii) a second voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled and, for an element of −1 in the code sequences, driving the drive lines at (i) the second voltage when the analog integrator is reset and (ii) the first voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled.

The above feature makes it possible to achieve a higher signal intensity and thus increase an electric charge stored in a capacitance.

A touch sensor system of the present invention includes: a sensor panel including (I) a first capacitance column Ci1 (i=1, . . . , M) formed between M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line; and an integrated circuit for controlling the sensor panel, the integrated circuit including: a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, the M drive lines in parallel for each of (I) the first capacitance column Ci1 (i=1, . . . , M) and (II) the second capacitance column Ci2 (i=1, . . . , M), and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the drive section, before outputting the outputs sFirst and sSecond from the first and second capacitance columns to the analog integrator, (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at a first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator, (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as first offset outputs and second offset outputs, respective, and (c) storing the first and second offset outputs in a memory.

The above feature makes it possible to cancel an offset caused by an analog integrator.

An electronic device of the present invention includes: a touch sensor system of the present invention; and a display panel which either is placed on the sensor panel included in the touch sensor system or contains the sensor panel.

A capacitance detecting method of the present invention includes the steps of: (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the step (A), to prevent saturation of the analog integrator, switching a gain of the analog integrator in accordance with an absolute value of a sum total of corresponding elements present in the code sequences along a column direction.

The above feature makes it possible to prevent saturation of an analog integrator.

A capacitance detecting method of the present invention includes the steps of: (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the step (A), to prevent saturation of the analog integrator, dividing, in accordance with an absolute value of a sum total of corresponding elements present in the code sequences along a column direction, a column of the code sequences into a plurality of columns so as to divide the driving of the M drive lines into a plurality of drivings.

The above feature makes it possible to prevent saturation of an analog integrator.

A capacitance detecting method of the present invention includes the steps of: (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being +1 or −1 and each of which has a code length N=M, the code sequences di corresponding to respective rows of a 2n-dimensional Hadamard matrix created by Sylvester method, (M=2n) drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the (M=2n) drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the (M=2n) drive lines and a second sense line, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the step (A), to prevent saturation of the analog integrator, dividing a first column of the code sequences into a plurality of columns so as to divide a driving for the first column of the code sequences into a plurality of drivings.

The above feature makes it possible to prevent saturation of an analog integrator.

A capacitance detecting method of the present invention includes the steps of: (A) (a) driving, on a basis of first code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being +1 or −1 and each of which has a code length N>M, the first code sequences di corresponding to respective rows of a 2n-dimensional (where M<2n) Hadamard matrix created by Sylvester method, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2=M) formed between the M drive lines and a second sense line, so that a voltage +V is applied for an element of +1 in the first code sequences and that a voltage −V is applied for an element of −1 in the first code sequences, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the first code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the first code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the step (A) dividing a particular column of the first code sequences into a plurality of columns, the particular column having an absolute value of a sum total of corresponding elements present in the first code sequences along a column direction which absolute value exceeds a threshold Num for saturation of the analog integrator, so as to divide a driving for the particular column into a plurality of drivings.

The above feature makes it possible to prevent saturation of an analog integrator in a driving based on a 2n-dimensional (where M<2n-1) Hadamard matrix.

The linear system coefficient estimating method of the present invention inputs M inputs Xk (k=1, . . . , M) on the basis of M code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and each of which has a length N and outputs N outputs s=(s1, s2, . . . , sN)=(F (d11, d21, . . . , dM1), F (d12, d22, . . . , dM2), . . . , F (d1N, d2N, . . . , dMN)). The linear system coefficient estimating method thus estimates a coefficient Ck of the linear system by simultaneously inputting all the M inputs. The linear system coefficient estimating method consequently (i) eliminates the need to sequentially select one of M inputs and scan it for an input as in conventional arrangements and (ii) even with an increase in the number M of inputs, does not shorten a process time for obtaining a coefficient value of the linear system. The linear system coefficient estimating method thus maintains a good detection accuracy and achieves a good resolution and a high-speed operation.

The linear device column value estimating method of the present embodiment may preferably be arranged such that the code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) include elements each of which is either +V or −V.

The above arrangement makes it possible to drive each drive line by applying to it either a voltage +V or a voltage −V.

The capacitance detecting method of the present embodiment may preferably be arranged such that the step (B) includes carrying out, for each parallel driving based on the code sequences di, of addition or subtraction in accordance with a code which addition or subtraction is necessary for the first and second inner product operations.

The above arrangement carries out an inner product operation for each parallel driving. The capacitance detecting method thus not only (i) allows pipeline processing and consequently carries out an operation within a short period of time, but also (ii) reduces an amount of memory necessary to carry out an operation, as compared to an arrangement which carries out an inner product operation for each of N parallel drivings corresponding to the length of the code sequences.

The capacitance detecting method may preferably be arranged such that the step (A) outputs the outputs sFirst from the first capacitance column to a first analog integrator and the outputs sSecond from the second capacitance column to a second analog integrator; and the step (B) carries out (I) the first inner product operation by subjecting the outputs sFirst, which have been outputted to the first analog integrator, to an AD conversion in an AD converter and (II) the second inner product operation by subjecting the outputs sSecond, which have been outputted to the second analog integrator, to an AD conversion in the AD converter.

The above arrangement provides analog integrators in parallel for the respective sense lines, and thus increases a speed of detecting all the capacitances provided in a matrix.

The capacitance detecting method may preferably be arranged such that the step (A) first outputs the outputs sFirst from the first capacitance column to an analog integrator and second outputs the outputs sSecond from the second capacitance column to the analog integrator; and the step (B) carries out (I) the first inner product operation by subjecting the outputs sFirst, which have been outputted to the analog integrator, to an AD conversion in an AD converter and (II) the second inner product operation by subjecting the outputs sSecond, which have been outputted to the analog integrator, to an AD conversion in the AD converter.

The above arrangement allows a single analog integrator to carry out the estimating, and thus makes it possible to detect the capacitances with use of a simpler configuration.

The capacitance detecting method may preferably be arranged such that the step (A) outputs the outputs sFirst from the first capacitance column to a first analog integrator and the outputs sSecond from the second capacitance column to a second analog integrator; and the step (B) carries out (I) the first inner product operation by subjecting the outputs sFirst, which have been outputted to the first analog integrator, to an AD conversion in a first AD converter and (II) the second inner product operation by subjecting the outputs sSecond, which have been outputted to the second analog integrator, to an AD conversion in a second AD converter.

The above arrangement provides both analog integrators and AD converters in parallel for the respective sense lines, and thus further increases the speed of detecting all the capacitances provided in a matrix.

The capacitance detecting method of the present embodiment may preferably be arranged such that the step (B) estimates (a) the first capacitance value on a basis of a third inner product operation of (I) a result obtained by subtracting, from the outputs sFirst, the first offset outputs stored in the memory and (II) the code sequences di and (b) the second capacitance value on a basis of a fourth inner product operation of (I) a result obtained by subtracting, from the outputs sSecond, the second offset outputs stored in the memory and (II) the code sequences di.

The above arrangement makes it possible to cancel an offset caused by an analog integrator.

The capacitance detecting method of the present embodiment may preferably be arranged such that the step (C) (I) repeats a plurality of times an operation of (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at the first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator and (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as the first offset outputs and the second offset outputs, respectively, and (II) averages a plurality of sets of the first and second offset outputs read out and then stores in the memory a result of the averaging.

The above arrangement makes it possible to store offset outputs in a memory after reducing a noise component contained in an offset caused by an analog integrator.

The capacitance detecting method of the present embodiment may preferably be arranged such that the step (B) estimates (a) the first capacitance value on a basis of a third inner product operation of (I) a first digital value obtained by an AD conversion of the outputs sFirst and (II) the code sequences di and (b) the second capacitance value on a basis of a fourth inner product operation of (I) a second digital value obtained by an AD conversion of the outputs sSecond and (II) the code sequences di; and the step (B) switches weighting for each of the first and second digital values in accordance with the absolute value of a sum total of corresponding elements present in the code sequences along the column direction.

The above arrangement makes it possible to cause a gain obtained on a path from an analog integrator through to the inner product computing section to be constant for each driving based on the code sequences.

The capacitance detecting method of the present embodiment may preferably be arranged such that a column having an absolute value of a sum total of corresponding elements present in the first code sequences along a column direction which absolute value exceeds a threshold Num for saturation of the analog integrator corresponds to at least one of a first column, a (2n-1+1) column, a (2n-1+2n-2+1) column, and a (2n-1−2n-2+1) column of the 2n-dimensional Hadamard matrix.

The above arrangement makes it possible to prevent, with use of a simple algorithm, saturation of an analog integrator in a driving based on a 2n-dimensional (where M<2n) Hadamard matrix.

The capacitance detecting method of the present embodiment may preferably be arranged such that where [x] represents an integer part of x, the step (A), in a case where the first column of the 2n-dimensional Hadamard matrix exceeds the threshold Num, first (a) sequentially drives [M/Num] sets each including NuM drive lines from a first drive line through to a Num×[M/Num]-th drive line and then (b) drives in parallel drive lines corresponding to a remainder of the (M/Num); the step (A), in a case where the (2n-1+1) column of the Hadamard matrix exceeds the threshold Num, first (a) drives in parallel a drive line on a row based on a (2n-1−(M−2n-1))-th row through a drive line on an M-th row, second (b) sequentially drives [row based on a (2n-1−(M−2n-1)−1)-th row/Num] sets each including NuM drive lines from the drive line on a first row through to a drive line on the row based on a (2n-1−(M−2n-1)−1)-th row, and third (c) drives in parallel drive lines corresponding to a remainder of the (row based on a (2n-1−(M−2n-1)−1)-th row/Num); and the step (A), in a case where the (2n-1+2n-2+1) column of the Hadamard matrix exceeds the threshold Num, first (a) simultaneously drives in parallel the drive line on the first row through a drive line on a (2n-1)-th row, second (b) drives in parallel a drive line on a row based on a ((2n-1+2n-2)−(M−(2n-1+2n-2)))-th row through a drive line on the M-th row, third (c) sequentially drives [(row based on (((2n-1+2n-2)−(M−(2n-1+2n-2)))))−(2n-1+1)/Num] sets each including NuM drive lines from a drive line on a (2n-1+1)-th row through to the drive line on the row based on the ((2n-1+2n-2)−(M−(2n-1+2n-2)))-th row, and fourth (d) drives in parallel drive lines corresponding to a remainder of the ((row based on (((2n-1+2n-2)−(M−(2n-1+2n-2)))))−(2n-1+1)/Num).

The above arrangement makes it possible to prevent, with use of a simple algorithm, saturation of an analog integrator in a driving based on a 2n-dimensional (where M<2n) Hadamard matrix.

The capacitance detecting method of the present embodiment may preferably further include: the step of: creating, by switching rows, second code sequences based on the Hadamard matrix, wherein: the step (A) drives the M drive lines in parallel on a basis of the second code sequences.

A capacitive touch sensor panel of the present invention includes: a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction; a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction; and an insulator provided between the vertical electrode surface and the horizontal electrode surface so as to insulate the plurality of vertical electrodes and the plurality of horizontal electrodes from each other, the plurality of vertical electrodes and the plurality of horizontal electrodes (i) being disposed so that, as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and (ii) forming a uniform grid having no gap.

The above arrangement disposes (I) a plurality of vertical electrodes (i) each including a repeat of first basic shapes connected to one another in a vertical direction, the first basic shapes each including a fine wire, (ii) provided on a vertical electrode surface, and (iii) arranged at a predetermined interval in a horizontal direction and (II) a plurality of horizontal electrodes (i) each including a repeat of second basic shapes connected to one another in the horizontal direction, the second basic shapes each including a fine wire, (ii) provided on a horizontal electrode surface parallel to the vertical electrode surface, and (iii) arranged at a predetermined interval in the vertical direction so that (i) as viewed in a direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and that (ii) the plurality of vertical electrodes and the plurality of horizontal electrodes form a uniform grid having no gap. Thus, preparing an electrode distribution with (i) the vertical electrodes, (ii) the horizontal electrodes, and (iii) an insulating film sandwiched therebetween forms a uniform grid having no visible gap. Such an electrode distribution, as placed on a display device, can prevent moire and the like from occurring.

A capacitive touch sensor system of the present invention includes: a touch sensor panel of the present invention.

An information input-output device of the present invention includes: the touch sensor system of the present invention.

A capacitive touch sensor panel of the present invention is arranged such that a plurality of vertical electrodes and a plurality of horizontal electrodes are so disposed that (i) as viewed in the direction perpendicular to the vertical electrode surface, the plurality of vertical electrodes include no segment coincident with the plurality of horizontal electrodes and that (ii) the plurality of vertical electrodes and the plurality of horizontal electrodes form a uniform grid having no gap. Thus, the capacitive touch sensor panel, as placed on a display device, can prevent moire and the like from occurring.

The capacitive touch sensor panel of the present embodiment may preferably be arranged such that the fine wire included in the first basic shapes and the fine wire included in the second basic shapes each extend in an oblique direction.

According to the above arrangement, the fine wire included in the first basic shapes and the fine wire included in the second basic shapes are each inclined with respect to a black matrix of the display. The above arrangement thus reduces the possibility of moire occurring.

The capacitive touch sensor panel of the present embodiment may preferably be arranged such that the grid has a rectangular outline.

According to the above arrangement, the vertical electrodes and the horizontal electrodes form a grid having a rectangular outline as viewed in the direction perpendicular to the vertical electrode surface. The above arrangement thus makes it possible to easily join, directly to respective portions corresponding to sides of the rectangular outline of the uniform grid having no gap, (i) address lines for driving the horizontal electrodes or the vertical electrodes and (ii) address lines for reading out signals from the vertical electrodes or the horizontal electrodes.

The capacitive touch sensor panel of the present embodiment may preferably be arranged such that the first basic shapes and the second basic shapes each have line symmetry with respect to a vertical center line extending in the vertical direction.

With the above arrangement, the first basic shapes and the second basic shapes each have a symmetric shape. The above arrangement can thus improve accuracy of reading coordinates on the basis of a change to a capacitance distribution which change is caused by a touch input involving use of a pen.

The capacitive touch sensor panel of the present embodiment may preferably be arranged such that the first basic shapes and the second basic shapes each have point symmetry.

With the above arrangement, the first basic shapes and the second basic shapes each have a symmetric shape. The above arrangement can thus improve accuracy of reading coordinates on the basis of a change to a capacitance distribution which change is caused by a touch input involving use of a pen.

The capacitive touch sensor panel of the present embodiment may preferably be arranged such that the first basic shapes and the second basic shapes each have line symmetry with respect to (i) a vertical center line extending in the vertical direction and (ii) a horizontal center line extending in the horizontal direction.

With the above arrangement, the first basic shapes and the second basic shapes each have a symmetric shape. The above arrangement can thus improve accuracy of reading coordinates on the basis of a change to a capacitance distribution which change is caused by a touch input involving use of a pen.

The capacitive touch sensor panel of the present embodiment may preferably be arranged such that the first basic shapes are each internally connected in the vertical direction at two or more fine-wire points; and the second basic shapes are each internally connected in the horizontal direction at two or more fine-wire points.

With the above arrangement, adjacent ones of the first basic shapes are connected to each other at two or more fine-wire points, while adjacent ones of the second basic shapes are also connected to each other at two or more fine-wire points. Thus, even if one fine wire is broken during production, the remaining fine wire can prevent total disconnection.

The present invention is not limited to the description of the embodiments above, but may be altered in various ways by a skilled person within the scope of the claims. Any embodiment based on a proper combination of technical means disclosed in different embodiments is also encompassed in the technical scope of the present invention.

INDUSTRIAL APPLICABILITY

The present invention is applicable to a method for estimating or detecting a coefficient, a device value, or a capacitance in a linear system configured in a matrix. The present invention is further applicable to an integrated circuit, a touch sensor system, and an electronic device each operating in accordance with the method. The present invention is also applicable to a fingerprint detection system.

The present invention is applicable to a capacitive touch sensor panel including (i) a plurality of vertical electrodes provided on a vertical electrode surface and arranged at predetermined intervals in a horizontal direction, (ii) a plurality of horizontal electrodes provided on a horizontal electrode surface, which is parallel to the vertical electrode surface, and arranged at predetermined intervals in a vertical direction, and (iii) an insulator provided between the vertical electrode surface and the horizontal electrode surface to insulate the vertical electrodes from the horizontal electrodes. The present invention is further applicable to a capacitive touch sensor system including the above capacitive touch sensor panel and to an information input-output device.

REFERENCE SIGNS LIST