Self-adaptive voltage regulator for a phase-locked loop

A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

FIELD OF THE INVENTION

The present invention relates to phase-locked loops, and more particularly to a self-adaptive voltage regulator for a phase-locked loop.

BACKGROUND OF THE INVENTION

Referring toFIG. 1, a block diagram illustrating a conventional phase-locked loop is shown. A conventional phase-locked loop (PLL)10is a feedback loop that includes a phase detector14, which receives a reference clock12as one input, a charge pump (CP)16, and a low pass filter18that provides a control voltage (VC)20to a voltage controlled oscillator (VCO)22for generation of an output clock24. The clock24output by the VCO is feedback into the phase detector14through an optional divider26, which frequency multiplies the output clock up.

The function of the PLL10is to lock the output of the VCO20to the phase of the reference clock12. In operation, the phase detector14compares the phase of the incoming reference clock12with the divided frequency of the VCO output clock24, and produces an output that is a function of the phase difference. This output from the phase detector14is used to control which direction the charge pump16charges/discharges the low pass filter18to produce a control voltage20frequency that has a reduced phase difference. The control voltage20, in turn, controls the frequency of the VCO22. This loop forms a negative feedback system. For the loop to achieve phase lock, the phase of the input reference clock12and the divided VCO output24must have a fixed phase relationship (ideally 0 degrees difference).

Temperature/process variations can cause problems for timing critical circuits, such as the PLL10. To insure the PLL loop can null the effects of process/temperature changes, the control voltage20changes to control the VCO22frequency, and thus the output clock phase position, in such a way that this fixed phase relationship with the reference clock12is maintained. More particularly, as process/temperature drifts occur, the VC20changes in the direction that will yield zero phase difference between the input reference clock12and the divided VCO output24. For example, a temperature change or slow process may slow down the VCO22. In this case, the VC20voltage will need to move lower to speed up the VCO22and keep the loop locked (i.e., zero phase difference). However, although moving the VC20away from its center position helps insure the PLL loop will maintain lock, higher output clock jitter (i.e., unwanted phase movement) can result. Ideally, the control voltage20should operate within a particular voltage range for best output jitter performance.

Thus, it is desirable to both maintain PLL phase lock AND maintain the control voltage20at some predefined optimal voltage position for lowest jitter. Moreover, it would be desirable to have an error control signal that dynamically adjusts the voltage of the VCO22or other delay sensitive circuits/paths as the process/temperature changes.

Digital sampling or logic control may be implemented to account for process/temperature drift. For example, one approach utilizes a dual loop system where the PLL feedback acts as a fast loop and a slow loop is added to the PLL loop to slowly change the gain of the VCO22to keep the PLL loop running at the proper frequency. This slow loop only operates at power-up to determine the proper operating frequency.

Although digital sampling may account for process/temperature drift, it suffers several disadvantages. The main disadvantage of digital sampling is that it only works at power up to set the proper state of the regulator output, and there is only a limited number of output states that can be chosen to center the control voltage. This is done because it is undesirable to change the control voltage20with finite granularity as that will both cause abrupt changes in the output phase of the VCO22, which is a source of jitter that needs to be avoided.

Accordingly, what is needed is a method and system for minimizing operational frequency limitations of a phase-locked loop by maintaining the control voltage at an optimal position as temperature/process changes occur during normal operation of the PLL. The present invention addresses such a need.

SUMMARY OF THE INVENTION

The present invention provides a method and system for providing a phase-locked loop with self-adaptive voltage regulator. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to the voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, a self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator, in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

According to the method and system disclosed herein, the voltage regulator of the present invention minimizes operational frequency limitations of a phase-locked loop by maintaining the control voltage at an optimal position as temperature/process changes occur during normal operation of the phase-locked loop.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a real-time sampling system for a phase-locked loop that dynamically controls a supply voltage input to the phase-locked loop in order to maintain an optimal control voltage position. This is accomplished by continually sensing the control voltage of the phase-locked loop during normal operation, comparing the control voltage to an optimal value, and dynamically adjusting the supply voltage using an analog technique in order to keep the control voltage within a predefined range of the optimal value.

In accordance with a preferred embodiment of the present invention, the real-time sampling system is implemented as an analog self-adaptive voltage regulator. When sampling the control voltage, the voltage regulator does not suffer the disadvantages of digital implementations that have limited sampling points or discrete operating conditions. In addition, the voltage regulator is capable of operating during normal steady-state conditions of the phase-locked loop. The present invention does not require digital sampling or logic control, and allows for granular control over a predetermined supply and PLL control voltage range. Accordingly, the real-time voltage regulator may be useful for extending the usable operating frequency of the phase-locked loop or extending the margin of delay critical circuits by nulling the limiting effects of process and temperature drift that occur during normal operation.

Referring now toFIG. 2, a block diagram illustrating a phase-locked loop having a self-adaptive voltage regulator in accordance with the preferred embodiment of the present invention. As described with reference toFIG. 1, a phase-locked loop (PLL)200is a feedback loop comprising a phase detector202, a charge pump204, a low pass filter206, a voltage control oscillator (VCO)208and an optional divide by circuit210. According to the present invention, the PLL200is further provided with a self-adaptive voltage regulator220, which forms a second negative feedback loop nested within the PLL200.

In operation, the phase detector202receives a reference clock222as input and produces an output that is a function of the phase difference the reference clock222and the divided frequency of the VCO output clock224. This output from the phase detector202is used to control which direction the charge pump204charges/discharges the low pass filter206to produce a control voltage226frequency that has a reduced phase difference and which controls the phase and frequency of the VCO208. Adding charge for completing charge from the low pass filter206either increases or reduces the value of the control voltage226appropriately to speed up for slowdown the VCO208.

The function of the voltage regulator220is to keep the control voltage226centered during normal operation of the PLL200, not just a power-up, by continually adjusting its regulated output supply voltage228that is input to the VCO208. More particularly, the self-adjusting voltage regulator220dynamically controls the regulated output supply voltage228connection to the VCO208by using the control voltage226from the PLL200as an error signal that is proportionate to process/temperature drift occurring in the PLL200.

In a preferred embodiment, the voltage regulator220is a negative feedback loop comprising a summing node230, a forward gain A232, and a feedback gain B234. The control voltage226output from the low pass filter206of the PLL200is input to the summing node230. The summing node230continually samples the control voltage226and compares a weighted combination of the control voltage226and a feedback supply voltage238to a reference voltage236that represents an optimal value of the control voltage226to determine an amount of drift occurring in the PLL200. In response, the regulated output supply voltage228from the regulator220is set such that the VCO208will cause the PLL200to shift the control voltage226towards the optimal value (reference voltage236). Thus, voltage regulator220ensures that the control voltage226remains centered during operation of the PLL200.

The forward gain A232multiplies the difference between summing node voltage230and the reference voltage236by a gain amount “A” to output the supply voltage228. The supply voltage228is also input to feedback gain B234, which multiplies the supply voltage228by a continuation value “B”, normally some fraction of the output. Loop gain B outputs a feedback supply voltage238to the summing node230that represents a value proportional to the current output supply voltage228. The summing node230looks for an error in the output against some ideal by outputting the difference between the reference voltage236and the weighted sum of the control voltage226and feedback supply voltage238.

During operation of the PLL200, the VCO208process may drift slower due to temperature variation, or example. To compensate, the output of the low pass filter206will tend to decrease in order to decrease the control voltage226and speed up the VCO208to maintain lock. This decrease will be sensed by the self-adaptive regulator220as it compares the control voltage226to the reference voltage236and the feedback supply voltage238. When it is determined that the control voltage226is less than the reference voltage236, the self-adaptive regulator220attempts to increase the control voltage226back into its optimal position by increasing the regulated supply voltage228input to the VCO208, thus speeding up the output frequency. In response, the control voltage226returns towards its original (optimal) position, while the regulator output supply voltage228remains higher, thus nulling out the effects of the slower process.

Similarly, if the VCO208process drifts faster, the output of the low pass filter206will increase in order to increase the control voltage226and slowdown the VCO208. The self-adaptive regulator220will sense this increase. When it is determined that the control voltage226is greater than the reference voltage236, the self-adaptive regulator220attempts to decrease the control voltage226back into its optimal position by decreasing the regulator output supply voltage228that is input to the VCO208, thus slowing down the output frequency. In response, the control voltage226returns towards its optimal position.

Thus, the PLL200of the present invention uses two feedback loops to maintain PLL phase lock—the normal PLL feedback loop, and the regulator control feedback loop. Ideally, the regulator control feedback controls the “DC” response (for slow changes), while the normal PLL feedback controls the “AC” response (time domain movement in the input reference clock222).

FIG. 3is block diagram illustrating one embodiment of the self-adaptive voltage regulator220shown inFIG. 2. In a preferred embodiment, the regulator220′ includes four resistors, OPpc0, OPpc2, OPpc3, and OPpc4. The control voltage226, which is used as an error control signal from the PLL200, is input through resistor OPpc0to the summing node230. Resistors OPpc2, OPpc3, and OPpc4form feedback gain B234, the output of which is also input to the summing node230. The output of the summing node230is input to forward gain A232along with the reference voltage236, which is an on-chip static voltage reference that is temperature and supply compensated. Vsupply300is input to the forward gain A232and is a power supply voltage that powers the voltage regulator220′. The forward gain A232multiples the difference between the reference voltage236and the output of the summing mode230to produce the regulated output supply voltage228.

The gain of the self-adaptive voltage regulator212′ can be changed by varying the values of the resistors OPpc0, OPpc2, OPpc3, and especially OPpc4, as illustrated inFIG. 4.

FIG. 4is a graph depicting the output of the regulator circuit shown inFIG. 3for different values of resistor OPpc4. The control voltage error signal is plotted on the x-axis, while the supply voltage228output by the voltage regulator220′ is plotted on the y-axis. Three curves are shown, each with a different value of OPpc4. Curve400represents the DC sweep response when OPpc4has a value of 1.75K. Curve402represents the DC sweep response when OPpc4has a value of 1.25K. And curve404represents the DC sweep response when OPpc4has a value of 750K.

The slope of each curve is determined by the ratio of OPpc4and OPpc0. The steeper the curve, the more compressed the VCO control range becomes. The intersection of the three curves, 1.2V and 1.8V, represents the nominal environment for the PLL200. This means that the PLL200should be designed such that at a nominal temperature and with a nominal process, the control voltage226for a nominal frequency would be 1.2V. This intersection is determined by the reference voltage236and the ratio of the sum OPpc2and OPpc3to OPpc0. Therefore, by altering the resistor values inFIG. 3, varying slopes and intersection points can be had. The selection of OPpc0, OPpc2, OPpc3, and OPpc4are to be considered during the design process and selection of particular values does not limit the invention to those values.

A PLL having an analog self-adaptive regulator has been disclosed that adjusts a supply voltage input to the PLL in real-time in order to keep a PLL control voltage centered during operation of the PLL.

The present invention has been described in accordance with the embodiments shown, and one of ordinary skill in the art will readily recognize that there could be variations to the embodiments, and any variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.