Testing structure, and fabrication and testing methods thereof

Testing structures, and their fabrication methods and testing methods are provided. An exemplary testing structure includes a base substrate containing a well region; a first doped epitaxial region in the well region and having a doping type same as a doping type of the well region; a dielectric layer on the base substrate and covering the well region and the first doped epitaxial region; a first contact plug passing through the dielectric layer and electrically connected with the first well region; and a second contact plug and a third contact plug. The second contact plug and the third contact plug pass through the dielectric layer and electrically connected with the first doped epitaxial region. The second contact plug is independent from the third contact plug and between the first contact plug and the third contact plug.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority of Chinese patent application No. 201611262695.6, filed on Dec. 30, 2016, the entirety of which is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to the field of semiconductor technologies and, more particularly, relates to testing structures and their fabrication and testing methods.

BACKGROUND

With continuous increase of integration level of devices formed during semiconductor manufacturing processes (e.g., MOS/CMOS processes), the miniaturization of the devices are having some challenges. Among of such challenges, with the continuous shrinking of the semiconductor devices, the parasitic external resistance (Rext) has become one of the major reasons limiting the performance of the semiconductor devices. The parasitic external resistance includes the contact resistance (Rc) between the metal silicide layer and the doped source/drain regions.

A chain mode testing structure or a Kelvin testing structure is often used to measure the contact resistance. For the chain mode testing structure, two contact plugs are connected to two ends of the metal silicide layer, respectively; and metal lines are used to connect one unit to a next unit; and all the units are connected together by a chain mode in serial. By applying a voltage on the two ends of the chain (the plurality of units) and measuring the corresponding current, the resistance of the entire structure (the chain) is obtained. The resistance is divided by the number of the contact plugs, one half of the resistance between one contact plug and the metal silicide layer is obtained. Thus, the resistance between the contact plug and the metal silicide layer is obtained. However, the chain mode testing structure is only able to obtain the contact resistance between the contact plug and the metal silicide layer, it is unable to obtain the contact resistance between the metal silicide layer and the doped source/drain regions. The contact resistance between the metal silicide layer and the doped source/drain regions is also an important parameter of the semiconductor device.

With the application of the embedded stress technology, the accuracies of the contact resistances obtained by the testing structures provided by the semiconductor structures are relatively low. Thus, there is a need to provide new testing structures and testing methods to improve the accuracy of the measured contact resistances. The disclosed testing structures and methods are directed to solve one or more problems set forth above and other problems in the art.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure includes a testing structure. The testing structure includes a base substrate, containing a well region; a first doped epitaxial region in the well region and having a doping type same as a doping type of the well region; a dielectric layer on the base substrate, and covering the well region and the first doped epitaxial region; a first contact plug passing through the dielectric layer and electrically connected with the first well region; and a second contact plug and a third contact plug, each passing through the dielectric layer and electrically connected with the first doped epitaxial region, wherein the second contact plug is independent from the third contact plug and between the first contact plug and the third contact plug.

Another aspect of the present disclosure includes a method for fabricating a testing structure. The method includes providing a base substrate containing a well region; forming a first doped epitaxial region in the well region having a doping type same as a doping type of the well region; forming a dielectric layer over the base substrate, and covering the well region and the first doped epitaxial region; forming a first contact plug passing through the dielectric layer and electrically connected with the well region at one side of the first doped epitaxial region; and forming a second contact plug and a third contact plug, each passing through the dielectric layer and electrically connected with the first doped epitaxial region, wherein the second contact plug is independent from the third contact plug and between the first contact plug and the third contact plug.

Another aspect of the present disclosure includes a testing method. The testing method includes providing a testing structure having a base substrate containing a well region, a first doped epitaxial region in the well region and having a doping type same as a doping type of the well region, a dielectric layer on the base substrate and covering the well region and the first doped epitaxial region, a first contact plug passing through the dielectric layer and electrically connected with the first well region; and a second contact plug and a third contact plug, each passing through the dielectric layer and electrically connected with the first doped epitaxial region, wherein the second contact plug is independent from the third contact plug and between the first contact plug and the third contact plug; applying a first external current on a first end portion of the second contact plug; applying a second external current smaller than the first external current on the first contact plug to form a current loop among the first contact plug, the first doped epitaxial region under the second contact plug and the first contact plug; measuring a top potential of the second contact plug through a second end portion of the second contact plug; measuring a bottom potential of the first doped epitaxial region through the third contact plug; and obtaining the contact resistance between the metal silicide layer and the first doped epitaxial region according to the first external current, the top potential and the bottom potential.

DETAILED DESCRIPTION

FIG. 1illustrates a top view of the testing structure.FIG. 2illustrates a correlation between the total resistance measured by the testing structure illustrated inFIG. 1and the distance between adjacent contact plugs.

Currently, a transmission line modeling (TLM) method is often used to measure the contact resistance between the metal silicide layer and the doped source/drain regions.

Specifically, the testing structure includes a base substrate (not shown); a well region (not shown) in the base substrate; a doped epitaxial region (not shown); a dielectric layer (not shown) covering the well region and the doped epitaxial region (not shown); a plurality of contact plugs passing through the dielectric layer, electrically connecting with the doped epitaxial regions and having a metal silicide layer on the doped epitaxial regions; and conductive plugs (not shown) on the metal silicide layer. The sizes of the plurality of contact plugs are identical and the materials of the plurality of contact plugs are identical. The distances between adjacent contact plugs are different. The widths “W” of the plurality of contact plugs are equal.

As shown inFIG. 1, the plurality of contact plugs includes a first contact plug CT1, a second contact plug CT2, a third contact plug CT3, a fourth contact plug CT4, a fifth contact plug CT5and a sixth contact plug CT6. The distance between the first contact plug CT1and the second contact plug CT2is L1. The distance between the second contact plug CT2and the third contact plug CT3is L2. The distance between the third contact plug CT3and the fourth contact plug CT4is L3. The distance between the fourth contact plug CT4and the fifth contact plug CT5is L4. The distance between the fifth contact plug CT5and the sixth contact plug CT6is L5. L1, L2, L3, L4, and L5are different from each other.

During the TLM testing method, the total resistance “R” between the adjacent contact plugs is obtained. According to the distance “L” between adjacent contact plugs, the correlation between the total resistance “R” and the distance “L” between adjacent contact plugs is obtained by a simulation process. Referring toFIG. 2, the abscissa refers to as the distance “L” between the adjacent contact plugs; and the ordinate refers to as the total resistance “R” between adjacent contact plugs. The equation of the correlation between the total resistance “R” and the distance “L” between adjacent conductive plugs is: R=2×Rc+RSH×(L/W). “Rc” is the resistance of the contact plug. “RSH” is the sheet resistance.

The resistance “Rc” of the conductive plug includes the resistance of the conductive plug, the resistance of the metal silicide layer, and the contact resistance between the metal silicide layer and the doped epitaxial region. The resistance of the conductive plug and the resistance of the metal silicide layer are obtainable. Thus, according to the equation: R=2×Rc+RSH×(L/W), when the distance “L” between the adjacent conductive plugs is zero (the limit value), the total resistance “R” is two times of the resistance “Re” of the conductive plug. That is: R=2×Rc. Correspondingly, the contact resistance between the metal silicide layer and the doped epitaxial region can be obtained by a calculation.

However, with the continuously shrinking of semiconductor devices, the difficulties for forming conductive plugs with a same size have increased. Further, with the changing of the distances “L” between adjacent contact plugs, the sizes of the contact plugs are also correspondingly changed. Thus, the accuracy of the contact resistance “Rc” obtained by the equation: R=2×Rc+RSH×(L/W) is correspondingly reduced. That is, it is difficult to obtain the contact resistance between the metal silicide layer and the doped epitaxial region.

The present disclosure provides a testing structure, a method for fabricating a testing structure, and a testing method. The testing structure includes a first doped epitaxial layer in the well region. The doping type of the well region and the doping type of the first doped epitaxial region may be substantially same. The testing structure may also include a dielectric layer; and a first contact plug, a second contact plug and a third contact plug in the dielectric layer. The first contact plug may be electrically connected with the well region. The second contact plug and the third contact plug may be electrically connected with the first doped epitaxial region. The second contact plug and the third plug may be independent from each other; and the second contact plug may be between the first contact plug and the third contact plug. The second contact plug may include a metal silicide layer on the first doped epitaxial region and a first conductive plug on the metal silicide layer. Along a direction parallel to the substrate and a length direction of the second contact plug, the surface of the second contact plug may have two end portions. One end portion of the second contact plug may be used as a terminal for applying an external current; and the other end portion of the second contact plug may be used as a terminal for measuring the top potential. The first contact plug may be used as a terminal for applying a second external current; and the third contact plug may be used as a terminal for measuring the bottom potential. The second external current may be smaller than the first external current. When the first external current and the second external current are applied, a current loop may be formed among the second contact plug, the first doped epitaxial region, the well region and the first contact plug. Thus, the top potential of the of the second contact plug may be measured from the other end portion of the second contact plug. The third contact plug may be not in the current loop. The potential measured from the third contact plug may be the bottom potential of the first doped epitaxial region. Thus, the contact resistance between the metal silicide layer and the first doped epitaxial region may be obtained according to the first external current, the top potential and the bottom potential. Comparing with the approach based the transmission line model (TLM), the disclosed method may be able to avoid the errors caused by the size differences between different contact plugs. Thus, the contact resistance obtained by the disclosed method may have relatively high accuracy and reliability.

FIGS. 3-4illustrate an exemplary testing structure consistent with various disclosed embodiments.FIG. 3is a top view of a portion of a testing structure, where a well region and a dielectric layer are not illustrated.FIG. 4is a cross-sectional view of the structure illustrated inFIG. 3along the AA1direction.

As shown inFIGS. 3-4, the testing structure may include a base substrate (not labeled) and a well region101in the base substrate. The testing structure may also include a plurality of discrete first doped epitaxial regions121in the well region101. The doping type of the first doped epitaxial regions121may be the same as the doping type of the well region101.

Further, the testing structure may include a dielectric layer120on the base substrate. The dielectric layer120may cover the well region101and the first doped epitaxial regions121. Further, the testing structure may also include first conductive plugs151passing through the dielectric layer120and electrically connected with the well region101; and a second contact plug152and a third contact plug153passing through the dielectric layer120and electrically connected with the first doped epitaxial regions121. The second contact plug152and the third contact plug153may be independent from each other; and the second contact plug152may be between the first contact plug151and the third contact plug153.

A first testing pad11may be formed on a portion of the surface of the first contact plug151. A second testing pad12and a third testing pad13may be formed on portions of the surface of the second contact plug152. A fourth testing14may be formed on a portion of the surface of the third contact plug153.

The second contact plug152may include a metal silicide layer133on the first doped epitaxial region121and a first conductive plug122on the metal silicide layer133. The second contact plug152may have two end portions (not labeled) along the direction parallel to the base substrate and the length direction of the second contact plug152. The second testing pad12may be formed on one end portion, e.g., a first end portion, of the second contact plug152; and the third testing pad13may be formed on the other end portion, e.g., a second end portions, of the second contact plug152. Thus, the length direction of the second contact plug152refers to as the direction between the second testing pad12and the third testing pad13.

In one embodiment, the base substrate includes a semiconductor substrate100and a plurality of discrete fins110on the semiconductor substrate100. The well region101may be in the fins110. Correspondingly, the first doped epitaxial regions121may be formed in the fins110.

In one embodiment, the semiconductor substrate100is a silicon substrate. In some embodiments, the semiconductor substrate may also be made of germanium, silicon germanium, silicon carbide, gallium arsenide, or gallium indium, etc. The semiconductor substrate may also be a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate.

The fins110and the semiconductor substrate100may be made of a same material, or different materials. In one embodiment, the fins110are made of silicon. In some embodiments, the fins may be made of germanium, silicon germanium, silicon carbide, gallium arsenide, or gallium indium, etc.

In some embodiments, the base substrate may be a planar substrate.

To allow the testing structure to be more similar to the practical device having the embedded stress technology, the testing structure also include a second doped epitaxial region111in the well region101under the first contact plug151. The first contact plug151and the second doped epitaxial region111may be electrically connected together. The second doped epitaxial region111and the first doped epitaxial region121may be independent from each other. Further, to ensure a close-loop electrical circuit to be formed in the testing structure, the second doped epitaxial region111and the first doped epitaxial region121may be made of a same material. Thus, the accuracy and the reliability of the measured contact resistance may be increased.

In one embodiment, the testing structure may be used to measure the contact resistance of an NMOS device, correspondingly, the doping type of the first doped epitaxial region121and the second doped epitaxial region111may be N-type. The material of the first doped epitaxial region121and the second doped epitaxial region111may be N-type doped Si, or N-type doped SiC. The doping type of the well region101may be N-type. The N-type doping ions may be one or more of P ions, As ions and Sb ions, etc.

In some embodiments, the first doped epitaxial region and the second doped epitaxial region may be P-type doped. The material of the first doped epitaxial region and the second doped epitaxial region may be P-type doped Si, or P-type doped SiGe. The doping type of the well region may be P-type. The P-type doping ions may be one or more of B ions, Ga ions and In ions.

In one embodiment, the top surface of the first doped epitaxial region121may be above the surface of the base substrate; and the top surface of the second doped epitaxial region111may be above the surface of the base substrate. That is, the top surface of the first doped epitaxial region121and the top surface of the second doped epitaxial region111may be above the top surfaces of the fins110. In some embodiments, the top surface of the first doped epitaxial region may level the top surface of the base substrate; and the top surface of the second doped epitaxial region may level with the top surface of the base substrate.

Further, the cross-section of the first doped epitaxial region121may be square-shaped, U-shaped, or sigma-shaped, etc. The cross-section of the second doped epitaxial region111may be square-shaped, U-shaped, or sigma-shaped, etc.

The dielectric layer120may be made of an insulation material. The dielectric layer120may be used to electrically isolate the adjacent fins110and the conductive plugs. In one embodiment, the dielectric layer120is made of silicon oxide. In some embodiments, the dielectric layer may be made of silicon nitride, or silicon oxynitride, etc.

Referring toFIGS. 3-4, one end portion (the first end portion) of the second contact plug152may be used as a terminal for applying a first external current “I”. The other end portion (the second end portion) of the second contact plug152may be used as a terminal for measuring the top potential “V2”. The second contact plug152may include the metal silicide layer133on the first doped epitaxial region121and a first conducive plug122on the metal silicide layer133.

The metal silicide layer133may be used to reduce the contact resistance between the first doped epitaxial region121and the first contact plug122. In one embodiment, the metal silicide layer122may be formed on a portion of the first doped epitaxial region121. In some embodiments, the metal silicide layer may be on the entire surface of the first doped epitaxial region.

The first metal silicide layer133may be made of silicon nickel, or silicon titanium, etc. The first conductive plug122may be made of Cu, Al, or W, etc.

In one embodiment, the number of the first doped epitaxial region121is one. Thus, the second contact plug152and the third contact plug153may be connected to a same first doped epitaxial region121. That is, the second contact plug152and the third contact plug153may be formed on the same first doped epitaxial region121.

In one embodiment, to allow the testing structure to be more similar to the practical device using the embedded stress technology, the third contact plug153may include the metal silicide layer133on the first doped epitaxial region121and a second conductive plug123on the metal silicide layer133. The metal silicide layer133under the first conductive plug122and the metal silicide layer133under the second conductive plug123may be independent from each other. In some embodiments, the third contact plug may only include a second conductive plug.

In some other embodiments, when the third contact plug includes the metal silicide layer on the first doped epitaxial region and the second conductive plug on the metal silicide layer, the metal silicide layer may be formed on a portion of the first doped epitaxial region; and the first conductive plug and the second conductive plug may be electrically connected to a same metal silicide layer.

In some embodiments, the number of the first doped epitaxial regions may be two. The two first doped epitaxial regions may be at a same side of the second doped epitaxial region. The second contact plug may be electrically connected to the first doped epitaxial region at the side adjacent to the first contact plug. The third contact plug may be electrically connected with the other first doped epitaxial region.

To increase the testing accuracy of the testing structure, the second conductive plug123and the first conductive plug122may be made of a same material. The second conductive plug123may be made of Cu, Al, or W, etc.

The first contact plug151may be used as a terminal for applying a second external current “Com”; and the value of the second external current “Com” may be smaller than the value of the first external current “I”. Thus, with the function of the first external current “I” and the second external current “Com”, a current loop may be formed among the second contact plug152, the first doped epitaxial region121, the well region101and the first contact plug151.

In one embodiment, the number of the first contact plugs151is two. In some embodiments, the number of the first contact plug may be one, or more than two.

In one embodiment, to allow the testing structure to be more similar to the practical device using the embedded stress technology, the first contact plug151may include the metal silicide layer133on the second doped epitaxial region111and the third conductive plug112on the metal silicide layer133. In some embodiments, the first contact plug may only include a third conductive plug.

To increase the testing accuracy of the testing structure, the third conductive plug112, the second conductive plug123and the first conductive plug122may be made of a same material. The third conductive plug112may be made of Cu, Al, or W, etc.

When the first external current “I” is applied to the first end portion of the second contact plug152and the second external current “Com” is applied to the first contact plug151, a current loop may be formed among the second contact plug152, the first doped epitaxial region121, the well region101and the first contact plug151(referring to the dashed line arrow). The top potential “V2” of the second contact plug152may be measured from the second end portion of the second contact plug152. The top potential “V2” refers to as the top potential of the second contact plug152along the direction perpendicular to the surface of the semiconductor substrate100.

The third contact plug153may not be in the current loop; and the doping type of the well region101and the doping type of the first doped epitaxial region121may be same; and the third contact plug153may be electrically connected to the first doped epitaxial region121. Thus, the potential “V1” measured from the third contact plug153may be used as the bottom potential “V1” of the first doped epitaxial region121. The bottom potential “V1” refers to as the bottom potential “V1” along the direction perpendicular to the surface of the semiconductor substrate100.

The terminal voltage between the first doped epitaxial region121and the first contact plug151may be the potential difference “V2−V1” between the top potential “V2” and the bottom potential “V1”. At the same time, the resistance “R1” of the first conductive plug122, the resistance “R2” of the metal silicide layer133under the first conductive plug122and the resistance “R3” of the first doped epitaxial region121may be obtainable. According to these parameters, the contact resistance “RC” between the metal silicide layer133and the first doped epitaxial region121may be obtained.

In one embodiment, as shown inFIG. 3, the testing structure may also include the first testing pad11formed on a portion of a surface of the first contact plug151and electrically connected with the first contact plug151; the second testing pad12formed on the surface of the end portion of the second contact plug152and the electrically connected with the second contact plug152; the third testing pad13formed on the surface of the second end portion of the second contact plug152and electrically connected with the second contact plug152; and the fourth testing pad14formed on a portions of the surface of the third contact plug153and electrically connected with the third contact plug153. The second external current “Com” may be applied to the first contact plug151through the first testing pad11. The first external current “I” may be applied to the second contact plug152through the second testing pad12. The top potential “V2” of the second contact plug152may be obtained through the third testing pad13. The bottom potential “V1” of the first doped epitaxial region121may be obtained through the fourth testing pad14.

In one embodiment, to improve the quality of the first conducive plug122, the testing structure may also include a barrier layer (not shown) between the first conductive plug122and the dielectric layer120and between the first conductive plug122and the metal silicide layer133. The barrier layer may be made of any appropriate material. In one embodiment, the barrier layer is made of TiN. The barrier layer may also be between the second conducive plug123and the metal silicide layer133. The barrier layer may also be between the third conductive plug112and the dielectric layer120and between the third conductive plug112and the metal silicide layer133.

FIG. 10illustrates an exemplary fabrication process of a testing structure consistent with various disclosed embodiments.FIGS. 5-9illustrate structures corresponding to certain stages during the exemplary fabrication process.

As shown inFIG. 10, at the beginning of the fabrication process, a base substrate with certain structures is provided (S101).FIGS. 5-6illustrate a corresponding semiconductor structure.FIG. 5is a top view of the semiconductor structure; andFIG. 6is a cross-sectional view of the structure illustrated inFIG. 5along the BB1direction.

As shown inFIGS. 5-6, a base substrate is provided. In one embodiment, the testing structure is used to measure the contact resistances of a fin field-effect transistor (FinFET) device, the base substrate may include a semiconductor substrate100and a plurality of discrete fins110on the semiconductor substrate100.

In one embodiment, the semiconductor substrate100is a silicon substrate. In some embodiments, the semiconductor substrate may also be made of germanium, silicon germanium, silicon carbide, gallium arsenide, or gallium indium, etc. The semiconductor substrate may also be a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate.

The fins110and the semiconductor substrate100may be made of a same material, or different materials. In one embodiment, the fins110are made of silicon. In some embodiments, the fins may be made of germanium, silicon germanium, silicon carbide, gallium arsenide, or gallium indium, etc.

In some embodiments, the base substrate may be a planar substrate.

Further, as shown inFIG. 6, a well region101may be formed in the fins110.

To allow a current loop to be formed in the testing structure and increase the accuracy and reliability of the measured contact resistance, the doping type of the well region101and the doping type of the subsequently formed doped epitaxial regions may be same.

In one embodiment, the testing structure may be used to measure the contact resistances of an NMOS device. That is, the subsequently formed doped epitaxial regions may be N-type doped. Correspondingly, the doping type of the well region101may be N-type. The N-type doping ions may be one or more of P ions, As ions and Sb ions, etc.

In some embodiments, when the testing structure is used to measure the contact resistances of a PMOS device, the well region is P-type doped. The P-type doping ions may be one or more of B ions, Ga ions and In ions.

Returning toFIG. 10, after providing the base substrate and forming the well region, a first doped epitaxial region may be formed (S102).FIG. 7illustrates a corresponding semiconductor structure.

As shown inFIG. 7, a first doped epitaxial region121may be formed in the well region101. The doping type of the first doped epitaxial region121may be the same as the doping type of the well region101.

Because the well region101may be in the fins110, correspondingly, the first doped epitaxial region121may also be in the fins110. The first doped epitaxial region121may provide a process base for subsequently forming a second contact plug and a third contact plug.

In one embodiment, to allow the testing structure to be more similar to a practical device using the embedded stress technology, during the process for forming the first doped epitaxial region121, a second doped epitaxial region111may also be formed in the well region101at one side of the first doped epitaxial region121. The second doped epitaxial region111may be independent from the first doped epitaxial region121. Further, to form a current loop inside the testing structure during a testing process, the second doped epitaxial region111and the first doped epitaxial region121may be made of a same material. Accordingly, the accuracy and the reliability of the measured contact resistance may be increased. In some embodiments, the second doped epitaxial region may be omitted.

The position of the second doped epitaxial region111may correspond to the position of the subsequently formed first contact plug. The second doped epitaxial region111may provide a process base for subsequently forming the first contact plug.

The process for forming the second doped epitaxial region111and the first doped epitaxial region121may include etching a partial thickness of the well region101to form a first trench (not shown) corresponding to the first doped epitaxial region121in the well region101and a second trench (not shown) corresponding to the second doped epitaxial region111in the well region101; forming a first doped epitaxial layer (not shown) to fill the first trench and a second doped epitaxial layer (not shown) to fill the second trench by a selective epitaxial growth process; and forming the first doped epitaxial region121and the second doped epitaxial region111by a doping process. The doping process may be performed during the selective epitaxial growth process, or after the selective epitaxial growth process.

In one embodiment, the testing structure is used to measure the contact resistances of an NMOS device. Thus, the type of the doping ions may be N-type during the doping process on the first doped epitaxial layer and the second doped epitaxial layer.

The first doped epitaxial layer may be made of Si, or SiC, etc. Thus, the first doped epitaxial region121and the second doped epitaxial region111may be made of N-type doped Si, or SiC, etc. The N-type ions may be one or more of P ions, As ions and Sb ions

In some embodiments, the testing structure is used to measure the contact resistances of a PMOS device. Thus, the type of the doping ions may be P-type during the doping process on the first doped epitaxial layer and the second doped epitaxial layer. The first doped epitaxial layer may be made of Si, or SiGe, etc. The second doped epitaxial layer may be made of Si, or SiGe, etc. Thus, the first doped epitaxial region121and the second doped epitaxial region111may be made of P-type doped Si, or SiGe, etc. The P-type ions may be one or more of B ions, Ga ions and In ions.

In one embodiment, the top surface of the first doped epitaxial region121may be above the surface of the base substrate; and the top surface of the second doped epitaxial region111may be above the surface of the base substrate. That is, the top surface of the first doped epitaxial region121and the top surface of the second doped epitaxial region111may be above the top surfaces of the fins110. In some embodiments, the top surface of the first doped epitaxial region may level the surface of the base substrate; and the top surface of the second doped epitaxial region may level with the surface of the base substrate.

Further, the cross-section of the first doped epitaxial region121may be square-shaped, U-shaped, or sigma-shaped. The cross-section of the second doped epitaxial region111may be square-shaped, U-shaped, or sigma-shaped.

In one embodiment, the number of the first doped epitaxial region121is one. Correspondingly, a second contact plug and a third contact plug may be subsequently formed on a same first doped epitaxial region121.

In some embodiments, the number of the first doped epitaxial regions may be two; and the two first doped epitaxial regions may be adjacent to each other. That is, the two first doped epitaxial regions may be at a same side of the second doped epitaxial region. Correspondingly, during the subsequent process for forming the second contact plug and the third contact plug, the second contact plug may be formed on one of the two first doped epitaxial regions; and the third contact plug may be formed on the other first doped epitaxial region. In other embodiments, the number of the first doped epitaxial regions may be greater than two.

Returning toFIG. 10, after forming the first doped epitaxial region, a dielectric layer may be formed (S103).FIG. 8illustrates a corresponding semiconductor structure.

As shown inFIG. 8, a dielectric layer120is formed over the base substrate. The dielectric layer120may cover the well region101and the first doped epitaxial region121.

The dielectric layer120may provide a process base for subsequently forming a first contact plug, a second contact plug and a third contact plug. Further, the dielectric layer120may also be used to electrically isolate adjacent fins110and the subsequently formed first contact plug, second contact plug and third contact plug.

The dielectric layer120may be made of an insulation material. In one embodiment, the dielectric layer120is made of silicon oxide. In some embodiments, the dielectric layer may also be made of silicon nitride, or silicon oxynitride, etc.

In one embodiment, the second doped epitaxial region111may be formed in the well region101. Thus, the dielectric layer120may also cover the second doped epitaxial region111.

In some embodiments, for example, when a silicide-first process is used to form the testing structure, before forming the dielectric layer, a metal silicide layer may be formed on the first doped epitaxial region. The metal silicide layer may be formed on a partial, or entire surface of the first doped epitaxial region.

Returning toFIG. 10, after forming the dielectric layer, first contact plugs, a second contact plug, and a third contact plug may be formed (S104).FIG. 9illustrates a corresponding semiconductor structure.

As shown inFIG. 9, first contact plugs151are formed in the dielectric layer120at one side of the first doped epitaxial region121. The first contact plugs151may pass through the dielectric layer120, and may be electrically connected with the well region101. Further, a second contact plug152and a third contact plug153may be formed in the dielectric layer120. The second contact plug152and the third contact plug153may pass through the dielectric layer120and may be electrically connected with the first doped epitaxial region121. The second contact plug152and the third contact plug153may be independent from each other; and the second contact plug152may be between the first contact plug151and the third contact plug153. The second contact plug152may include a metal silicide layer133on the first doped epitaxial region121and the first conductive plug122on the metal silicide layer133. The surface of the second contact plug152may have two end portions, a first end portion and a second end portion, along the direction parallel to the base substrate and the length direction of the second contact plug152.

The second doped epitaxial region111may be formed in the well region101at the one side of the first doped epitaxial region121. Thus, during the process for forming the first contact plug151, the first contact plug151may be formed in the dielectric layer120. The first contact plug151may pass through the dielectric layer120and may be electrically connected with the second doped epitaxial region111.

In one embodiment, the number of the first contact plugs151is two. In some embodiments, the number of the first contact plug may be one, or greater than two.

To allow the testing structure to be more similar to the practical device using the embedded stress process and to reduce the process difficulties and steps, in one embodiment, during the process for forming the first contact plug151, the first contact plug151may include the metal silicide layer133on the second doped epitaxial region111and a third conductive plug112. During the process for forming the third contact plug153, the third contact plug153may include the metal silicide layer133on the first doped epitaxial region121and the second conductive plug123on the metal silicide layer133. Thus, the first contact plug151, the second contact plug152and the third contact plug153may be formed in a same step.

In one embodiment, a silicide-last process may be used to form the metal silicide layer133. Thus, after subsequently etching the dielectric layer120to expose the first doped epitaxial region121, the metal silicide layer133may be formed on the first doped epitaxial region121.

The process for forming the first contact plug151, the second contact plug152and the third contact plug153may include etching the dielectric layer120to form a first through hole (not labeled) and a second through hole exposing the first doped epitaxial region121and passing through the dielectric layer120, and a third through hole (not labeled) exposing the second doped epitaxial region111and passing through the dielectric layer120; forming a metal silicide layer133on the portions of the first doped epitaxial region121exposed by the first through hole and the second through hole and the portion of the second doped epitaxial region111exposed by the third through hole; and forming the first conductive plug122on the metal silicide layer133by filling the first through hole, the second conductive plug123on the metal silicide layer133by filling the second through hole and the third conductive plug112on the metal silicide layer133by filling the third through hole.

In some embodiments, the first contact plug may only include a third conductive plug; and the third contact plug may only include a second conductive plug.

In one embodiment, the number of the first doped epitaxial region121is one. Thus, during the process for forming the second plug152and the third contact plug153, the second contact plug152and the third contact plug153may be formed on the same first doped epitaxial region121. That is, the second contact plug152and the third contact plug153may be electrically connected with the same first epitaxial region121. Further, because the second contact plug152and the third contact plug153may be independent from each other, the first through hole may expose a portion of the surface of the first doped epitaxial region121; and the second through hole may expose a portion of the first doped epitaxial region121. Correspondingly, the metal silicide layer133may be formed on portions of the surface of the first doped epitaxial region121.

In one embodiment, the number of the first contact plugs151is two. Similarly, the metal silicide layer133under the first contact plugs151may be on portions of the surface of the first epitaxial region121.

In some embodiments, when the number of the first doped epitaxial regions is two, during the process for forming the second contact plug and the third contact plug, the second contact plug may be electrically connected to the first doped epitaxial region adjacent to the first contact plug; and the third contact plug may be electrically connected to the other first doped epitaxial region. Thus, the first through hole may expose a portion of, or the entire surface of the first doped epitaxial region at the side adjacent to the first contact plug; and the second through hole may expose a portion of, or the entire surface of the other first doped epitaxial region. Correspondingly, the metal silicide layer may be on portions of, or the entire surface of the first doped epitaxial regions.

To improve the quality of the first conductive plug122, after forming the first through hole and before forming the first conductive plug122, a barrier layer (not shown) may be formed on the bottom and side surfaces of the first through hole. In one embodiment, the barrier layer is made of TiN. The barrier layer may also be formed on the bottom and side surfaces of the second through hole; and on the bottom and side surfaces of third through hole.

FIG. 3illustrates a top view of an exemplary testing structure consistent with various disclosed embodiments (the well region and the dielectric layer are not showed). As shown inFIG. 3, the fabrication process of the testing structure may also include forming a first testing pad11electrically connected with the first contact plug151on a portion of the surface of the first contact plug151; forming a second testing pad12electrically connected with the first end portion of the second contact plug152on the surface of the first end portion of the second contact plug152; forming a third testing pad13electrically connected with the second end portion of the second contact plug152on the surface of the second end portion of the second contact plug152; and forming a fourth testing pad14electrically connected with the third contact plug153on a portion of the surface of the third contact plug153.

A second external current “Com” may be applied to the first contact plug151through the first testing pad11. A first external current “I” may be applied to the second contact plug152through the second testing pad12. A top potential “V2” of the second contact plug152may be obtained through the third testing pad13. A bottom potential “V1” of the first doped epitaxial region121may be obtained through the fourth testing pad14.

The present disclosure also provides a testing method.FIG. 11illustrates an exemplary testing method consistent with various disclosed embodiments.

As shown inFIG. 11, the testing method may include providing a disclosed testing structure, or other appropriate testing structures (S201); applying a first external current on the first end portion of the second contact plug (S202); applying a second external current greater than the first external current on the first contact plug to form a current loop among the second contact plug, the first doped epitaxial region under the second contact plug, the well region and the first contact plug (S203); measuring the top potential of the second contact plug through the second end portion of the second contact plug (S204); measuring the bottom potential of the first doped epitaxial region through the third contact plug (S205); and obtaining the contact resistance between the metal silicide layer and the first doped epitaxial region according to the first external current, the top potential and the bottom potential (S206).

The details of the testing method are described as followings using the accompanying drawings.

Referring toFIG. 4, a first external current “I” may be applied on the first end portion of the second contact plug152; and a second external current “Com” may be applied on the first contact plug151. The value of the second external current “Com” may be smaller than the value of the first external current “I”. Thus, a current loop (illustrated as the dashed arrow inFIG. 4) may be formed among the second contact plug152, the first doped epitaxial region121under the second contact plug152, the well region101and the first contact plug151.

By setting the value of the second external current “Com” to be smaller than the value of the first external current “I” so as to form the current loop, the current may flow through the first conductive plug122, the metal silicide layer133under the first conductive plug122and the first doped epitaxial region121.

In one embodiment, the second external current “Com” may be zero. In some embodiments, the second external current may also be a negative current. The first external current and the second external current may be set with any appropriate combination as long as a current loop may be formed among the second contact plug, the first doped epitaxial region under the second contact plug and the first contact plug.

Further, referring toFIG. 4, the top potential “V2” of the second contact plug152may be measured through the second end portion of the second contact plug152. The bottom potential “V1” may be measured from the third contact plug153. The top potential “V2” refers to as the top potential of the second contact plug152along the direction perpendicular to the semiconductor substrate100.

Because the third contact plug153may not be in the current loop, the potential “V1” measured from the third contact plug153may be used as the bottom potential “V1” of the first doped epitaxial region121. The bottom potential “V1” refers to as the potential on the bottom of the first doped epitaxial region121along the direction perpendicular to the surface of the semiconductor substrate100.

According to the first external current “I”, the top potential “V2” and the bottom potential “V1”, the contact resistance “Rc” between the metal silicide layer133and the first epitaxial region121may be obtained.

Specifically, the process for obtaining the contact resistance “Rc” may include obtaining the total resistance “R” by dividing the difference between the top potential “V2” and the bottom potential “V1” with the first external current “I”; and obtaining the resistance of the first conductive plug122, the resistance of the metal silicide layer133under the first conductive plug122and the resistance of the first doped epitaxial region121. The difference between the total resistance “R” and the resistance of the first conductive plug122, the resistance of the metal silicide layer133under the first conductive plug122and the resistance of the first doped epitaxial region121may be the contact resistance “Rc”.

Specifically, the resistance of the first conductive plug122is denoted as “R1”, the resistance of the metal silicide layer133under the first conductive plug122is denoted as “R2”, and the resistance of the first doped epitaxial region121is denoted as “R3”. R1, R2and R3may all be obtainable; and R1+R2+R3=(V2−V1)/I.

In some embodiments, the testing structure may also include a barrier layer between the first conductive plug122and the dielectric layer120and between the first conductive plug122and the metal silicide layer133. Correspondingly, the total resistance “R” may also include the resistance of the barrier layer. However, the resistance of the barrier layer may be substantially small; and it may be omitted.

Specifically, the value of the resistance “R1” of the first conductive plug122may be obtained according to the material and the volume of the first conductive plug122. The value of the resistance “R2” of the metal silicide layer133under the first conductive plug122may be obtained according to the material and the volume of the metal silicon layer133under the first conductive plug122. The value of the resistance “R3” of the first doped epitaxial region121may be obtained according to the material and the volume of the first doped epitaxial region121.

Thus, according to the obtained parameters, the contact resistance “RC” between the metal silicide layer133and the first doped epitaxial region121may be obtained.

In the disclosed testing structure, when the first external current “I” and the second external current “Com” are applied, a current loop may be formed among the second contact plug152, the first doped epitaxial region121under the second contact plug152, the well region101and the first contact plug151. Thus, the top potential “V2” may be measured from the second end portion of the second contact plug152. The third contact plug153may not be in the current loop. Thus, the potential “V1” measured through the third contact plug153may be the bottom potential “V1” of the first doped epitaxial region121. Therefore, the contact resistance “RC” between the metal silicide layer133and the first doped epitaxial region121may be obtained according to the first external current “I”, the top potential “V2” and the bottom potential “V1”. Comparing with the conventional approach that utilizes the transmission line modeling (TLM) to obtain the contact resistance, the disclosed method may be able to avoid the error issue caused by the size differences among different contact plugs. Thus, the contact resistance obtained by the disclosed method may have relatively high accuracy and reliability.