Array substrate, manufacturing method thereof, and display device

An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes a first conductive pattern, an insulation layer covering the first conductive pattern, and a second conductive pattern arranged on the insulation layer. The insulation layer includes a via-hole through which the first conductive pattern is connected to the second conductive pattern. A conductive post connected to the first conductive pattern and the second conductive pattern is formed in the via-hole.

CROSS-REFERENCE TO RELATED APPLICATION APPLICATIONS

This application is the U.S. national phase of PCT Application No. PCT/CN2016/083644 filed on May 27, 2016, which claims priority to Chinese Patent Application No. 201610143214.3 filed on Mar. 14, 2016, the disclosures of which are incorporated in their entirety by reference herein.

TECHNICAL FIELD

The present disclosure relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.

BACKGROUND

For an array substrate, it is necessary to provide via-holes through which patterns at different film layers may be connected to each other. The via-holes include a via-hole through which a pixel electrode is connected to a drain electrode of a thin film transistor (TFT), and a via-hole through which a common electrode is connected to a common electrode line. Usually, these via-holes are relatively narrow and deep, so depressions may easily occur at positions where the via-holes are formed. In this way, in the case that an alignment film is coated onto the array substrate, diffusion unevenness may easily occur at the positions where the via-holes are formed, and thereby such a defect as Mura may occur for a resultant display panel.

SUMMARY

An object of the present disclosure is to provide an array substrate, a manufacturing method thereof, and a display device, so as to prevent the occurrence of such a defect as Mura due to the diffusion unevenness at the positions where the via-holes are formed, thereby to improve a display effect of the display device.

In one aspect, the present disclosure provides in some embodiments an array substrate, including a first conductive pattern, an insulation layer covering the first conductive pattern, and a second conductive pattern arranged on the insulation layer. The insulation layer includes a via-hole through which the first conductive pattern is connected to the second conductive pattern. A conductive post connected to the first conductive pattern and the second conductive pattern is formed in the via-hole.

In a possible embodiment of the present disclosure, an upper surface of the conductive post has a horizontal level that is not lower than that of an upper surface of the insulation layer.

In a possible embodiment of the present disclosure, the upper surface of the conductive post has a horizontal level that is identical to that of the upper surface of the insulation layer.

In a possible embodiment of the present disclosure, the conductive post is made of an organic conductive polymer or a metal.

In a possible embodiment of the present disclosure, the conductive post includes a resin column object and a conductive material enclosing the resin column object.

In a possible embodiment of the present disclosure, an outer surface of the conductive post is in contact with an entire inner surface of the via-hole.

In a possible embodiment of the present disclosure, the first conductive pattern is a drain electrode of a TFT, and the second conductive pattern is a pixel electrode.

In a possible embodiment of the present disclosure, the pixel electrode covers the upper surface of the conductive post.

In a possible embodiment of the present disclosure, the insulation layer includes a passivation layer.

In a possible embodiment of the present disclosure, the first conductive pattern is a common electrode line, and the second conductive pattern is a common electrode.

In a possible embodiment of the present disclosure, the common electrode covers the upper surface of the conductive post.

In a possible embodiment of the present disclosure, the insulation layer includes a gate insulation layer and a passivation layer.

In another aspect, the present disclosure provides in some embodiments a display device including the above-mentioned array substrate.

In yet another aspect, the present disclosure provides in some embodiments a method for manufacturing an array substrate. The array substrate includes a first conductive pattern, an insulation layer covering the first conductive pattern, and a second conductive pattern arranged on the insulation layer. The insulation layer includes a via-hole through which the first conductive pattern is connected to the second conductive pattern. The method includes steps of: forming a conductive post connected to the first conductive pattern in the via-hole; and forming the second conductive pattern connected to the conductive post.

In a possible embodiment of the present disclosure, the first conductive pattern is a drain electrode of a TFT, the second conductive pattern is a pixel electrode, and the insulation layer includes a passivation layer. The method includes steps of: providing a base substrate; forming a gate electrode of the TFT on the base substrate; forming a gate insulation layer; forming a pattern of an active layer; forming a source electrode and the drain electrode of the TFT and the conductive post through a single patterning process, the conductive post being connected to the drain electrode; forming the passivation layer, and etching the passivation layer so as to expose the conductive post; and forming the pixel electrode connected to the conductive post.

In a possible embodiment of the present disclosure, the first conductive pattern is a drain electrode of a TFT, the second conductive pattern is a pixel electrode, and the insulation layer includes a passivation layer. The method includes steps of: providing a base substrate; forming a gate electrode of the TFT and the conductive post on the base substrate through a single patterning process; forming a gate insulation layer; forming a pattern of an active layer, and etching the gate insulation layer and the active layer so as to expose the conductive post; forming a source electrode and the drain electrode of the TFT, the drain electrode being connected to the conductive post; forming the passivation layer, and etching the passivation layer so as to expose the conductive post; and forming the pixel electrode connected to the conductive post.

In a possible embodiment of the present disclosure, the first conductive pattern is a common electrode line, the second conductive pattern is a common electrode, and the insulation layer includes a gate insulation layer and a passivation layer. The method includes steps of: providing a base substrate; forming a gate electrode of a TFT, the common electrode line and the conductive post on the base substrate through a single patterning process, the conductive post being connected to the common electrode line; forming the gate insulation layer; forming a pattern of an active layer; forming a source electrode and a drain electrode of the TFT; forming the passivation layer, and etching the gate insulation layer and the passivation layer so as to expose the conductive post; and forming the common electrode connected to the conductive post.

According to the embodiments of the present disclosure, the conductive post is formed in the via-hole in the insulation layer, and connected to the first conductive pattern and the second conductive pattern at different layers, so the first conductive pattern may be electrically connected to the second conductive pattern through the conductive post. In addition, the conductive post is filled within the via-hole, so it is able to provide the insulation layer with a flat surface and prevent the occurrence of depressions at the position where the via-hole is located. As a result, it is able to prevent the occurrence of such a defect as Mura due to diffusion unevenness of an alignment film at the position where the via-hole is located, thereby to improve a display effect of the display device.

REFERENCE SIGN LIST

DETAILED DESCRIPTION

In order to make the objects, the technical solutions and the advantages of the present disclosure more apparent, the present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments.

In the related art, depressions may easily occur at a position where a via-hole is located, and in the case that an alignment film is coated onto an array substrate, diffusion unevenness of the alignment film may easily occur at the position where the via-hole is located. An object of the present disclosure is to provide an array substrate, a manufacturing method thereof, and a display device, so as to prevent the occurrence of such a defect as Mura due to the diffusion unevenness of the alignment film at the position where the via-hole is located, thereby to improve a display effect of the display device.

As shown inFIGS. 1 and 2, for a array substrate in the related art, it is necessary to provide via-holes through which patterns at different film layers may be connected to each other. The via-holes include a pixel electrode via-hole7through which a pixel electrode6is connected to a drain electrode of a TFT, and a common electrode via-hole9through which a common electrode8is connected to a common electrode line. Usually, each via-hole has a size of 7 μm*7 μm, i.e., it is relatively narrow and deep, so depressions may easily occur at positions where the via-holes are located. When an alignment film is coated onto the array substrate, diffusion unevenness of the alignment film may easily occur at the positions where the via-holes are located, and thereby such a defect as Mura may occur for a resultant display panel.

The present disclosure provides in some embodiments an array substrate, including a first conductive pattern, an insulation layer covering the first conductive pattern, and a second conductive pattern arranged on the insulation layer. The insulation layer includes a via-hole through which the first conductive pattern is connected to the second conductive pattern. A conductive post connected to the first conductive pattern and the second conductive pattern is formed in the via-hole.

According to the embodiments of the present disclosure, the conductive post is formed in the via-hole in the insulation layer, and connected to the first conductive pattern and the second conductive pattern at different film layers, so the first conductive pattern may be electrically connected to the second conductive pattern through the conductive post. In addition, the conductive post is filled within the via-hole, so it is able to provide the insulation layer with a flat surface and prevent the occurrence of depressions at the position where the via-hole is located. As a result, it is able to prevent the occurrence of such a defect as Mura due to diffusion unevenness of an alignment film at the position where the via-hole is located, thereby to improve a display effect of the display device.

In a possible embodiment of the present disclosure, an upper surface of the conductive post has a horizontal level that is not lower than that of an upper surface of the insulation layer, so as to prevent the occurrence of depressions at the position where the via-hole is located.

In a possible embodiment of the present disclosure, the upper surface of the conductive post has a horizontal level that is same with that of the upper surface of the insulation layer, so as to provide the insulation layer with a flat surface at the position where the via-hole is located.

In a possible embodiment of the present disclosure, conductive post may be made of an organic conductive polymer or a metal.

In another possible embodiment of the present disclosure, a main body of the conductive post may be a resin column object, and a conductive material covers the resin column object.

The present disclosure further provides in some embodiments a method for manufacturing an array substrate. The array substrate includes a first conductive pattern, an insulation layer covering the first conductive pattern, and a second conductive pattern arranged on the insulation layer. The insulation layer includes a via-hole through which the first conductive pattern is connected to the second conductive pattern. The method includes steps of: forming a conductive post connected to the first conductive pattern in the via-hole prior to forming the second conductive pattern; and forming the second conductive pattern connected to the conductive post.

According to the embodiments of the present disclosure, prior to forming the second conductive pattern on the insulation layer, the conductive post is formed in the via-hole in the insulation layer and connected to the first conductive pattern under the insulation layer, so the first conductive pattern may be electrically connected to the second conductive pattern through the conductive post. In addition, the conductive post is filled within the via-hole, so it is able to provide the insulation layer with a flat surface and prevent the occurrence of depressions at the position where the via-hole is located. As a result, it is able to prevent the occurrence of such a defect as Mura due to diffusion unevenness of an alignment film at the position where the via-hole is located, thereby to improve a display effect of the display device.

In a possible embodiment of the present disclosure, the first conductive pattern is a drain electrode of a TFT, the second conductive pattern is a pixel electrode. The method includes steps of: providing a base substrate; forming a gate electrode of the TFT on the base substrate; forming a gate insulation layer; forming a pattern of an active layer; forming a source electrode and the drain electrode of the TFT and the conductive post through a single patterning process, the conductive post being connected to the drain electrode; forming the passivation layer, and etching the passivation layer so as to expose the conductive post; and forming the pixel electrode connected to the conductive post.

In the above-mentioned steps, the conductive post and the source electrode and the drain electrode of the TFT may be formed through a single patterning process, so it is able to form the conductive post without any additional patterning process, thereby to simplify the manufacture of the array substrate.

In a possible embodiment of the present disclosure, the first conductive pattern is a drain electrode of a TFT, the second conductive pattern is a pixel electrode. The method includes steps of: providing a base substrate; forming a gate electrode of the TFT and the conductive post on the base substrate through a single patterning process; forming a gate insulation layer; forming a pattern of an active layer, and etching the gate insulation layer and the active layer so as to expose the conductive post; forming a source electrode and the drain electrode of the TFT, the drain electrode being connected to the conductive post; forming the passivation layer, and etching the passivation layer so as to expose the conductive post; and forming the pixel electrode connected to the conductive post.

In the above-mentioned steps, the conductive post and the gate electrode of the TFT may be formed through a single patterning process, so it is able to form the conductive post without any additional patterning process, thereby to simplify the manufacture of the array substrate.

In a possible embodiment of the present disclosure, the first conductive pattern is a common electrode line, the second conductive pattern is a common electrode. The method includes steps of: providing a base substrate; forming a gate electrode of a TFT, the common electrode line and the conductive post on the base substrate through a single patterning process, the conductive post being connected to the common electrode line; forming the gate insulation layer; forming a pattern of an active layer; forming a source electrode and a drain electrode of the TFT; forming the passivation layer, and etching the gate insulation layer and the passivation layer so as to expose the conductive post; and forming the common electrode connected to the conductive post.

In the above-mentioned steps, the conductive post, the gate electrode of the TFT and the common electrode line may be formed through a single patterning process, so it is able to form the conductive post without any additional patterning process, thereby to simplify the manufacture of the array substrate.

The present disclosure provides in some embodiments a method for manufacturing an array substrate which, as shown inFIGS. 3-4, includes Steps31to35.

Step31: providing a base substrate1, and forming a conductive post10, and a gate line, a common electrode line and a gate electrode on the base substrate1. The gate line, the common electrode line and the gate electrode are formed by a gate metal layer2, and the conductive post10is connected to the common electrode line.

The base substrate1may be a glass or quartz substrate. The conductive post10may be made of a material identical to the gate metal layer, so it is able to form the conductive post10, the gate line, the common electrode line and the gate electrode through a single patterning process. The conductive post10may also be made of an organic conductive polymer.

In addition, a main body of the conductive post10may be a resin column object, and a conductive material may cover the resin column object. At this time, the conductive post10may be formed by a patterning process different from the gate line, the common electrode line and the gate electrode of the TFT. In the case that the main body of the conductive post10is the resin column object, the resin column object may be formed in advance at a predetermined position, and after the subsequent formation of the gate metal layer or a source-drain metal layer, the gate metal layer or source-drain metal layer on the resin column object may be reserved as the conductive layer covering the resin column object.

Step32: forming a gate insulation layer3and a pattern of an active layer on the base substrate1obtained after Step31, and etching the gate insulation layer3so as to expose the conductive post10.

Step33: forming a drain electrode and a source electrode of the TFT and a data line on the base substrate1obtained after Step32, the source electrode, the drain electrode and the data line are formed by the source-drain metal layer.

Step34: forming a passivation layer5on the base substrate1obtained after Step33, and etching the passivation layer5so as to expose the conductive post10.

Further, in Step32, the gate insulation layer3may not be etched, and instead, after the formation of the passivation layer5, the gate insulation layer3and the passivation layer5may be etched at the same time, so as to expose the conductive post10.

Step35: forming a common electrode8on the base substrate1obtained after Step34. The common electrode8is connected to the conductive post10, so as to acquire the structure as shown inFIG. 3.

In these embodiments of the present disclosure, the conductive post10may be filled within the via-hole through which the common electrode is connected to the common electrode line, so it is able to provide the insulation layer with a flat surface and prevent the occurrence of depressions at the position where the via-hole is located, thereby to prevent the occurrence of such a defect as Mura due to the diffusion unevenness of the alignment film at the position where the via-hole is located and improve a display effect of the display device.

The present disclosure further provides in some embodiments a method for manufacturing an array substrate which, as shown inFIGS. 5-6, includes Steps41to45.

Step41: providing the base substrate1, and forming the conductive post10, the gate line and the gate electrode of the TFT on the base substrate1. The gate line and the gate electrode of the TFT are formed by the gate metal layer.

The base substrate1may be a glass or quartz substrate. The conductive post10may be made of a material identical to the gate metal layer, so it is able to form the conductive post10, the gate line and the gate electrode through a single patterning process. The conductive post10may also be made of an organic conductive polymer.

In addition, a main body of the conductive post10may be a resin column object, and a conductive material may enclose the resin column object. At this time, the conductive post10may be formed by a patterning process different from the gate line and the gate electrode of the TFT. In the case that the main body of the conductive post10is the resin column object, the resin column object may be formed in advance at a predetermined position, and after the subsequent formation of the gate metal layer or a source-drain metal layer, the gate metal layer or source-drain metal layer on the resin column object may be reserved as the conductive layer enclosing the resin column object.

Step42: forming the gate insulation layer3and a pattern of the active layer on the base substrate1obtained after Step41, and etching the gate insulation layer3, so as to expose the conductive post10.

Step43: forming the drain electrode and the source electrode of the TFT and the data line on the base substrate1obtained after Step42. The drain electrode, the source electrode and the data line are formed by the source-drain metal layer4, and the drain electrode of the TFT is connected to the conductive post10.

Step44: forming the passivation layer5on the base substrate1obtained after Step43, and etching the passivation layer5so as to expose the conductive post10.

Step45: forming the pixel electrode6on the base substrate1obtained after Step44. The pixel electrode6is connected to the conductive post10so as to acquire the structure as shown inFIG. 5. The pixel electrode6may be electrically connected to the drain electrode of the TFT through the conductive post10.

In the embodiments of the present disclosure, the conductive post10may be filled within the via-hole through which the pixel electrode is connected to the drain electrode of the TFT, so it is able to provide the insulation layer with a flat surface and prevent the occurrence of depressions at the position where the via-hole is located, thereby to prevent the occurrence of such a defect as Mura due to the diffusion unevenness of the alignment film at the position where the via-hole is located and improve a display effect of the display device.

The present disclosure further provides in some embodiments a method for manufacturing an array substrate which, as shown inFIGS. 7-8, includes Steps51to55.

Step51: providing a base substrate1, and forming the gate line and the gate electrode on the base substrate1. The gate line and the gate electrode are formed by the gate metal layer2. The base substrate1may be a glass or quartz substrate.

Step52: forming the gate insulation layer3and a pattern of the active layer on the base substrate1obtained after Step51.

Step53: forming the conductive post, the source electrode and the drain electrode of the TFT, and the data line on the base substrate1obtained after Step52. The drain electrode, the source electrode and the data line are formed by the source-drain metal layer4, and the drain electrode is connected to the conductive post10. The conductive post10may be made of a material identical to the source-drain metal layer4, so it is able to form the conductive post10, the drain electrode, the source electrode and the data line through a single patterning process. The conductive post10may also be made of an organic conductive polymer.

In addition, a main body of the conductive post10may be a resin column object, and a conductive material may enclose the resin column object. At this time, the conductive post10may be formed by a patterning process different from the drain electrode, the source electrode and the data line. In the case that the main body of the conductive post10is the resin column object, the resin column object may be formed in advance at a predetermined position, and after the subsequent formation of the gate metal layer or a source-drain metal layer, the gate metal layer or source-drain metal layer on the resin column object may be reserved as the conductive layer enclosing the resin column object.

Step54: forming the passivation layer5on the base substrate1obtained after Step53, and etching the passivation layer5so as to expose the conductive post10.

Step55: forming the pixel electrode6on the base substrate1obtained after Step54, as shown inFIG. 7. The pixel electrode6is connected to the conductive post10, so it may be electrically connected to the drain electrode of the TFT through the conductive post10.

In the embodiments of the present disclosure, the conductive post10may be filled within the via-hole through which the pixel electrode is connected to the drain electrode of the TFT, so it is able to provide the insulation layer with a flat surface and prevent the occurrence of depressions at the position where the via-hole is located, thereby to prevent the occurrence of such a defect as Mura due to the diffusion unevenness of the alignment film at the position where the via-hole is located and improve a display effect of the display device.

The present disclosure further provides in some embodiments a display device including the above-mentioned array substrate. The display device may be any product or member having a display function, such as liquid crystal television, liquid crystal display, digital photo frame, mobile phone or flat-panel computer. The display device may further include a flexible circuit board, a printed circuit board and a back plate.