Package substrate with metal on conductive portions and manufacturing method thereof

A packaging substrate includes a first dielectric layer, a first wiring layer, a first conductive pillar layer, a second dielectric layer, a second wiring layer, an electrical pad layer, and a third dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface, plural openings, and a wall surface that faces at least one of the openings. The first wiring layer is located on the first surface and the wall surface. A portion of the first wiring layer on an edge of the wall surface adjacent to the second surface extends in a direction away from the wall surface. The first conductive pillar layer is located on a portion of the first wiring layer. The second dielectric layer is located on the first surface, the first wiring layer, and in the openings.

RELATED APPLICATIONS

This application claims priority to Chinese Application Serial Number 201510453954.2, filed Jul. 29, 2015, which is herein incorporated by reference.

BACKGROUND

Field of Invention

The present invention relates to a package substrate and a manufacturing method of the package substrate.

Description of Related Art

A package substrate is used to support an integrated circuit (IC) die and is referred to as a carrier. The package substrate has inner lines and electrical contacts, such that the electrical contacts on two opposite sides of the package substrate can respectively electrically connect to the semiconductor die and a printed circuit board (PCB). As a result, the semiconductor die and the PCB may transmit signals through the inner lines of the package substrate. With the development of semiconductor manufacturing technology, designers demand increasingly higher standards with respect to wire layout density, transmission speed, and signal disturbance, and thus package substrates have been extensively utilized in electronic products. For example, package substrates may be used in smartphones, tablet computers, network and communication solutions, laptop computers, etc.

In manufacturing a typical package substrate, a patterned conductive layer is formed on a carrier, such that the conductive layer has openings that expose the carrier. Thereafter, a copper pillar layer is formed on the conductive layer, and a dielectric layer is utilized to cover the conductive layer and the openings. As a result, after the carrier is removed, the entire conductive layer is exposed. However, only a portion of the conductive layer is utilized to electrically connect to a semiconductor die. If the conductive layer is directly connected to the electrical contacts of the semiconductor die, they will be easily separated due to the poor bonding force therebetween, thereby reducing reliability. In order to improve the bonding force between the package substrate and the semiconductor die, a nickel layer and a gold layer are often electroplated on the conductive layer. However, due to process limitations, the nickel layer and the gold layer are formed on the entire exposed conductive layer, and cannot be formed only on portions of the conductive layer corresponding to the electrical contacts of the semiconductor die. Therefore, the cost of the package substrate may be significantly increased.

SUMMARY

An aspect of the present invention is to provide a package substrate.

According to an embodiment of the present invention, a package substrate includes a first dielectric layer, a first wiring layer, a first conductive pillar layer, a second dielectric layer, a second wiring layer, an electrical pad layer, and a third dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface, a plurality of openings through the first and second surfaces, and a wall surface facing at least one of the openings. The first wiring layer is located on the first surface and the wall surface. A portion of the first wiring layer on an edge of the wall surface adjacent to the second surface extends in a direction away from the wall surface. The first conductive pillar layer is located on a portion of the first wiring layer that is on the first surface. The second dielectric layer is located on the first surface, the first wiring layer, and in the openings. The first conductive pillar layer is exposed from the second dielectric layer. The second wiring layer is located on the exposed first conductive pillar layer and the second dielectric layer. The electrical pad layer is located on the second wiring layer. The third dielectric layer is located on the second dielectric layer and the second wiring layer. The electrical pad layer is exposed from the third dielectric layer.

Another aspect of the present invention is to provide a manufacturing method of a package substrate.

According to an embodiment of the present invention, a manufacturing method of a package substrate includes the following steps. (a) A patterned first dielectric layer is formed on a carrier, such that the first dielectric layer has a plurality of openings. (b) A first wiring layer is formed on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing at least one of the openings, and the carrier in at least one of the openings. (c) A first conductive pillar layer is formed on a portion of the first wiring layer that is on the first surface. (d) A second dielectric layer is formed on the first surface, the first wiring layer, and the openings, and the first conductive pillar layer is exposed from the second dielectric layer. (e) A second wiring layer is formed on the exposed first conductive pillar layer and the second dielectric layer. (f) An electrical pad layer is formed on the second wiring layer. (g) A third dielectric layer is formed on the second dielectric layer and the second wiring layer, and the electrical pad layer is exposed from the third dielectric layer.

In the aforementioned embodiments of the present invention, the first dielectric layer having the openings is formed on the carrier. Thereafter, the first wiring layer is formed on the first surface of the first dielectric layer, the wall surface that faces at least one of the openings, and the carrier that is in at least one of the openings. As a result, after the carrier is removed, only certain portions of the first wiring layer are exposed from the second surface of the first dielectric layer, and the positions of such portions of the exposed first wiring layer correspond to the positions of the electrical contacts of a semiconductor die. In the subsequent manufacturing process, since only the above portions of the first wiring layer corresponding to the positions of the electrical contacts of the semiconductor die are exposed from the second surface of the first dielectric layer, it is possible to electroplate a nickel layer and a gold layer only on these portions of the first wiring layer. Accordingly, the costs associated with the nickel layer and the gold layer can be significantly reduced in the package substrate of the present invention.

An aspect of the present invention is to provide a package substrate.

According to an embodiment of the present invention, a package substrate includes a first dielectric layer, a first wiring layer, a first conductive pillar layer, a second dielectric layer, a second wiring layer, a second conductive pillar layer, and a third dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface, a plurality of openings through the first and second surfaces, and a wall surface facing at least one of the openings. The first wiring layer is located on the first surface and the wall surface. A portion of the first wiring layer on an edge of the wall surface adjacent to the second surface extends in a direction away from the wall surface. The first conductive pillar layer is located on a portion of the first wiring layer that is on the first surface. The second dielectric layer is located on the first surface, the first wiring layer, and in the openings. The first conductive pillar layer is exposed from the second dielectric layer. The second wiring layer is located on the exposed first conductive pillar layer and the second dielectric layer. The second conductive pillar layer is located on the second wiring layer. The third dielectric layer is located on the second dielectric layer and the second wiring layer. The second conductive pillar layer is exposed from the third dielectric layer.

Another aspect of the present invention is to provide a manufacturing method of a package substrate.

According to an embodiment of the present invention, a manufacturing method of a package substrate includes the following steps. (a) A patterned first dielectric layer is formed on a carrier, such that the first dielectric layer has a plurality of openings. (b) A first wiring layer is formed on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing at least one of the openings, and the carrier in at least one of the openings. (c) A first conductive pillar layer is formed on a portion of the first wiring layer that is on the first surface. (d) A second dielectric layer is formed on the first surface, the first wiring layer, and the openings, and the first conductive pillar layer is exposed from the second dielectric layer. (e) A second wiring layer is formed on the exposed first conductive pillar layer and the second dielectric layer. (f) A second conductive pillar layer is formed on the second wiring layer. (g) A third dielectric layer is formed on the second dielectric layer and the second wiring layer, and the second conductive pillar layer is exposed from the third dielectric layer.

DETAILED DESCRIPTION

FIG. 1is a cross-sectional view of a package substrate100according to one embodiment of the present invention. As shown inFIG. 1, the package substrate100is a coreless substrate and includes a first dielectric layer110, a first wiring layer120, a first conductive pillar layer130, a second dielectric layer140, a second wiring layer150, an electrical pad layer160, and a third dielectric layer170. In the following description, the shape and the material of the electrical pad layer160may be respectively the same as the shape and the material of first conductive pillar layer130, so that the electrical pad layer160may be referred to as a second conductive pillar layer. In other words, element160may be referred to as an “electrical pad layer” or a “second conductive pillar layer” in the following description. The first dielectric layer110has a first surface112, a second surface114opposite to the first surface112, plural openings116, and a wall surface118. The openings116pass through the first and second surfaces112,114. The wall surface118faces at least one of the openings116. The first wiring layer120is located on the first surface112of the first dielectric layer110and the wall surface118of at least one of the openings116. Moreover, the first wiring layer120on the edge of the wall surface118adjacent to the second surface114extends in a direction D away from the wall surface118, such that the first wiring layer120is step-shaped.

The first conductive pillar layer130is located on the first wiring layer120, that is, on a portion of the first wiring layer120that is on the first surface112of the first dielectric layer110. The second dielectric layer140is located on the first surface112of the first dielectric layer110, the first wiring layer120, and in the openings116of the first dielectric layer110. The top of the first conductive pillar layer130is exposed from the second dielectric layer140, and the second wiring layer150is located on an exposed portion of the first conductive pillar layer130and the second dielectric layer140. The electrical pad layer160is located on the second wiring layer150. The third dielectric layer170is located on the second dielectric layer140and the second wiring layer150, and the top of the electrical pad layer160is exposed from the third dielectric layer170.

As a result of such a design, in the package substrate100of the present invention, only a portion of the first wiring layer120is exposed from the second surface114of the first dielectric layer110, and the portion of the first wiring layer120exposed from the second surface114may be utilized to electrically connect to a semiconductor die. That is to say, in the package substrate100, only a portion of the first wiring layer120desired to connect the semiconductor die is exposed, thereby reducing the costs associated with a nickel layer and a gold layer that are electroplated on the first wiring layer120. In addition, the step-shaped first wiring layer120is a three-dimensional connection trace, and it is helpful to the circuit layout of the package substrate100.

In this embodiment, the first dielectric layer110, the second dielectric layer140, and the third dielectric layer170may be made of a material including epoxy, silicon oxide, or nitrogen oxide. The first dielectric layer110, the second dielectric layer140, and the third dielectric layer170may be made of the same material, but the present invention is not limited in this regard. The first and second wiring layers120,150, the first conductive pillar layer130, and the electrical pad layer160may be made of a material including copper or other conductive metals, such that the first wiring layer120, the first conductive pillar layer130, the second wiring layer150, and the electrical pad layer160may be electrically connected with each other by contact.

Furthermore, the openings116and the orthogonal projection of the first conductive pillar layer130on the first dielectric layer110are spaced apart. In other words, the first conductive pillar layer130is not aligned with the openings116, such that the position of the first conductive pillar layer130is not limited to the positions of the openings116. Hence, flexibility is provided with respect to the circuit layout of the package substrate100.

In this embodiment, the first wiring layer120includes a first sub-portion122, a second sub-portion124, and a third sub-portion126. The first sub-portion122is located on the first surface112of the first dielectric layer110. The second sub-portion124has opposite first and second ends, and the first end is connected to an end of the first sub-portion122. The second sub-portion124is located on the wall surface118. The third sub-portion126is connected to the second end of the second sub-portion124. The third sub-portion126extends in the direction D away from the wall surface118. The extending direction of the first sub-portion122on the first surface112is opposite to the extending direction D of the third sub-portion126, and thus the first, second, and third sub-portions122,124,126are formed in a Z-shaped arrangement. Moreover, the first sub-portion122can be utilized to electrically connect to the first conductive pillar layer130, and the third sub-portion126can be utilized to electrically connect to a semiconductor die.

FIG. 2is a cross-sectional view of an electronic device200, in which the package substrate100shown inFIG. 1is used therein. The electronic device200includes the package substrate100, a semiconductor die210, and a printed circuit board230. The semiconductor die210is disposed on the package substrate100, and the package substrate100is disposed on the printed circuit board230. The semiconductor die210has plural electrical contacts212. The positions of the first wiring layer120exposed from the first dielectric layer110correspond to the positions of the electrical contacts212of the semiconductor die210, such that the first wiring layer120is electrically connected to the electrical contacts212of the semiconductor die210. In this embodiment, a nickel layer214and a gold layer216may be electroplated on the first wiring layer120to increase the bonding force between the first wiring layer120and the electrical contact212. In addition, plural conductive structures162may be formed on portions of the electrical pad layer160that are exposed from the third dielectric layer170to electrically connect to the printed circuit board230. The conductive structures162may be a ball grid array (BGA), but are not limited in this regard. As a result, the package substrate100may be regarded as a medium to transmit signals between the semiconductor die210and the printed circuit board230.

In the package substrate100, only portions of the first wiring layer120are exposed from the second surface114of the first dielectric layer110. Since only portions of the first wiring layer120corresponding to the positions of the electrical contacts212of the semiconductor die210are exposed from the first dielectric layer110, the nickel layer214and the gold layer216can be formed only on these portions of the first wiring layer120. Accordingly, the costs associated with the nickel layer214and the gold layer216can be significantly reduced in the package substrate100of the present invention.

In this embodiment, the second surface114of the first dielectric layer110and the portion of the first wiring layer120that extends in a direction away from the wall surface118are coplanar, such that the semiconductor die210can be securely disposed on the second surface114of the first dielectric layer110.

It is to be noted that the connection relationships and materials of the elements described above will not be repeated in the following description, and only aspects related to the manufacturing method of the package substrate100will be described.

FIG. 3is a flow chart of a manufacturing method of a package substrate according to one embodiment of the present invention. The manufacturing method of the package substrate includes a number of steps as outlined below. First, in step S1, a patterned first dielectric layer is formed on a carrier, such that the first dielectric layer has a plurality of openings. Thereafter, in step S2, a first wiring layer is formed on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing at least one of the openings, and the carrier in at least one of the openings. Subsequently, in step S3, a first conductive pillar layer is formed on a portion of the first wiring layer that is on the first surface. Next, in step S4, a second dielectric layer is formed on the first surface, the first wiring layer, and the openings, and the first conductive pillar layer is exposed from the second dielectric layer. Thereafter, in step S5, a second wiring layer is formed on the exposed portion of the first conductive pillar layer and the second dielectric layer. Afterwards, in step S6, an electrical pad layer is formed on the second wiring layer. Finally, in step S7, a third dielectric layer is formed on the second dielectric layer and the second wiring layer, and the electrical pad layer is exposed from the third dielectric layer.

In the following description, the aforesaid steps in the manufacturing method of the package substrate will be described in detail.

FIG. 4is a cross-sectional view of a carrier180and the first dielectric layer110according to one embodiment of the present invention. The first dielectric layer110may be formed on the surface of the carrier180, and a patterning process is performed on the first dielectric layer110, such that the first dielectric layer110is patterned to have the openings116. The patterning process may include exposure, development, and etching processes in photolithography.

FIG. 5is a cross-sectional view of the first wiring layer120after being formed on the first dielectric layer110shown inFIG. 4. As shown inFIG. 4andFIG. 5, the first dielectric layer110has the first surface112facing away from the carrier180. After the patterned first dielectric layer110is formed on the carrier180, the first wiring layer120may be formed on the first surface112of the first dielectric layer110, the wall surface118facing at least one of the openings116, and a portion of the carrier180that is in at least one of the openings116. In this embodiment, the first wiring layer120may be formed by electroless plating, dry film photoresist laminating, patterning, and electroplating in sequence, but the present invention is not limited in this regard. For example, a sputtering process or evaporation process may also be utilized to form the first wiring layer120.

FIG. 6is a cross-sectional view of the first conductive pillar layer130after being formed on the first wiring layer120shown inFIG. 5. As shown inFIG. 5andFIG. 6, after the first wiring layer120is formed, the first conductive pillar layer130may be formed on a portion of the first wiring layer120that is on the first surface112of the first dielectric layer110. In this embodiment, the first conductive pillar layer130may be formed by dry film photoresist laminating, patterning, and electroplating in sequence, but the present invention is not limited in this regard.

FIG. 7is a cross-sectional view of the second dielectric layer140after being formed on the first dielectric layer110and the first wiring layer120shown inFIG. 6. After the first conductive pillar layer130is formed on the first wiring layer120, the second dielectric layer140may be formed on the first surface112of the first dielectric layer110, the first wiring layer120, and in the openings116of the first dielectric layer110. The first conductive pillar layer130is exposed from the second dielectric layer140. In manufacturing the second dielectric layer140, the second dielectric layer140may be utilized to cover the first surface112of the first dielectric layer110, the first wiring layer120, the openings116of the first dielectric layer110, and the first conductive pillar layer130. Thereafter, the surface of the second dielectric layer140is ground to expose the first conductive pillar layer130. In this embodiment, the second dielectric layer140may be formed by molding, but the present invention is not limited in this regard.

FIG. 8is a cross-sectional view of the second wiring layer150after being formed on the first conductive pillar layer130shown inFIG. 7.FIG. 9is a cross-sectional view of the electrical pad layer160after being formed on the second wiring layer150shown inFIG. 8. As shown inFIG. 8andFIG. 9, after the first conductive pillar layer130is exposed from the second dielectric layer140, the second wiring layer150may be formed on the exposed first conductive pillar layer130and the second dielectric layer140. Afterwards, the electrical pad layer160may be formed on the second wiring layer150. In this embodiment, the forming method of the second wiring layer150and the electrical pad layer160may be the same as the forming method of the first conductive pillar layer130, but the present invention is not limited in this regard.

FIG. 10is a cross-sectional view of the third dielectric layer170after being formed on the second dielectric layer140shown inFIG. 9.FIG. 11is a cross-sectional view of the carrier180shown inFIG. 10after being etched. As shown inFIG. 10andFIG. 11, after the electrical pad layer160is formed on the second wiring layer150, the third dielectric layer170may be formed on the second dielectric layer140and the second wiring layer150, and the electrical pad layer160is exposed from the surface of the third dielectric layer170. The first dielectric layer110has the second surface114opposite to the first surface112. After the third dielectric layer170is formed, the carrier180may be etched, such that the second surface114of the first dielectric layer110and the portion of the first wiring layer120that is on an end of the wall surface118adjacent to the second surface114are exposed. The etched carrier180has a hollow region182, and a semiconductor die may be bonded to the first wiring layer120that is in the hollow region182.

After the carrier180is etched to form the hollow region182, the residual carrier180(i.e., the portion of the carrier180remaining after being etched) and edges of the first, second, and third dielectric layers110,140,170may be cut off along line L-L. As a result, the package substrate100shown inFIG. 1may be obtained.

In the manufacturing method of the package substrate, the first dielectric layer110having the openings116is formed on the carrier180. Thereafter, the first wiring layer120is formed on the first surface112of the first dielectric layer110, the wall surface118that faces at least one of the openings116, and the carrier180that is in at least one of the openings116. As a result, after the carrier180is removed, only a portion of the first wiring layer120is exposed from the second surface114of the first dielectric layer110. In the subsequent manufacturing process, since only portions of the first wiring layer120corresponding to the positions of the electrical contacts of a semiconductor die are exposed from the second surface114of the first dielectric layer110, a nickel layer and a gold layer can be electroplated only on these portions of the first wiring layer120. Hence, the costs associated with the nickel layer and the gold layer can be effectively reduced in the package substrate of the present invention.