Clock and data recovery using dual manchester encoded data streams

Two Manchester encoded bit streams each bit stream with accompanying embedded clock data are disclosed. The two encoded bit streams are encoded at the source using opposite polarities of the source clock to position transitions within the bit streams at the rising and falling edges of the source clock. The receiver may extract the clock data from both bit streams. Because both rising and falling edge clock data is available between the two bit streams, the receiver does not need a phase locked loop (PLL) or incur the accompanying expense of such PLL. Further, by avoiding use of a PLL, a nearly all digital circuit may be created, which may provide further cost and space savings. Still further, a higher data throughput is provided without increasing pin count or signal bandwidth.

FIELD OF THE DISCLOSURE

The present disclosure relates to serial data streams.

BACKGROUND

Computing devices are common in modern society. The ease with which such computing devices perform myriad functions is enabled through complex integrated circuits instantiated on separate chips. In many instances different circuits on separate chips may need to communicate with one another inside the computing device. Such interchip communication may be effectuated by a serial data bus.

As the level of complexity increases, the amount of data that needs to be transferred between chips increases. There are generally two ways to increase the rate of data transfer. The first way is to increase the number of data channels between the chips by increasing the pin count on the chips and routing appropriate conductors between the pins. Each data channel may be a separate serial data channel, but collectively they may be considered a parallel bus. Increases in the number of data channels through additional pins and conductors is relatively expensive and may lead to design complications as the extra conductors must be routed in such a manner that limits electromagnetic interference and area consumption. The second way is to increase the clock frequency associated with the data channel. Increases in clock frequency may generate additional electromagnetic interference concerns.

Accordingly, there is a desire to increase options available to circuit designers for improved serial data transmission across a single data channel.

SUMMARY

Aspects of the present disclosure provide two or more Manchester encoded bit streams, where each bit stream has accompanying embedded clock data. The two encoded bit streams are encoded at the source using phase shifts of the source clock. In an exemplary aspect, there are two Manchester encoded bit streams and the phase shift is a 180 degree phase shift, which makes the two streams of opposite polarities for a fifty percent duty cycle clock. The receiver may extract the clock data from both bit streams. Because both rising and falling edge clock data is available between the two bit streams, the receiver does not need a phase locked loop (PLL) or incur the accompanying expense of such PLL. Further, by avoiding use of a PLL, a nearly all digital circuit may be created, which may provide further cost and space savings. Still further, a higher data throughput is provided without increasing pin count or signal bandwidth.

DETAILED DESCRIPTION

Aspects of the present disclosure provide two or more Manchester encoded bit streams, where each bit stream has accompanying embedded clock data. The two encoded bit streams are encoded at the source using phase shifts of the source clock. In an exemplary aspect, there are two Manchester encoded bit streams and the phase shift is a 180 degree phase shift, which makes the two streams of opposite polarities for a fifty percent duty cycle clock. The receiver may extract the clock data from both bit streams. Because both rising and falling edge clock data is available between the two bit streams, the receiver does not need a phase locked loop (PLL) or incur the accompanying expense of such PLL. Further, by avoiding use of a PLL, a nearly all digital circuit may be created, which may provide further cost and space savings. Still further, a higher data throughput is provided without increasing pin count or signal bandwidth.

Before addressing exemplary aspects of the present disclosure, a brief overview of a conventional Manchester encoding scheme is provided with reference toFIG. 1. In particular,FIG. 1illustrates a signal versus time chart10. The source clock signal12is denoted SRC_CLK and the data signal14is denoted SRC_DATA. As illustrated, the data signal has four bits16[1]-16[4]. The encoded bit stream18is denoted MANCHESTER STREAM. As is understood in the Manchester encoding scheme, an edge (rising or falling) is always guaranteed at the mid-bit boundary such as is illustrated at points20[1] and20[2]. If there are consecutive 0 s or 1 s in the data signal14, such as the repeated 0 s of bits16[3]-16[1], transitions will also appear in the boundary as is illustrated at points20[3],20[4]. Because the transition is non-periodic, clock recovery is complicated and typically requires a PLL to be used as part of the clock recovery circuit. PLLs typically consume relatively large amounts of power, which may be undesirable in battery operated devices, such as a mobile terminal. Further, PLLs typically consume relatively large areas within an integrated circuit. Such space consumption may be undesirable in small portable devices, such as a mobile terminal. Still further, a PLL must go through a training sequence to provide a good reference to the PLL lock circuit. Once lock is achieved, data recovery can start. Waiting for the lock increases latency. An additional concern is that with arbitrarily large data sequences, PLLs can lose lock (i.e., “drift”). While a delay circuit may be used that is targeted for a specific frequency range, such specific circuitry restricts the versatility of the circuit. Accordingly, new signaling systems may be provided to increase design flexibility for serial data streams.

In this regard,FIG. 2illustrates a signal versus time chart30having two data streams encoded according to a Manchester encoding scheme. The first data signal has a bit stream32labeled SRC_DATA_A with bits34[1]-34[3]. The second data signal has a bit stream36labeled SRC_DATA_B with bits38[1]-38[4]. The source clock signal40is denoted SRC_CLK. As is readily apparent, bit stream32has a 180 degree phase shift (i.e., one-half clock cycle) relative to bit stream36. Each bit stream32,36has its respective Manchester stream42,44with respective transitions46,48. Thus, each stream has user information and some percentage of timing information. It should be appreciated that if a logical OR of transitions46,48is taken at the receiver (or decoder) (see signal50), all the clock edges of the source clock signal40may be reproduced. Such recovered clock may then be used to sample the two bit streams to recover the original data signals for bit streams32,36. With any multi-Manchester stream, there will be at least two edges per clock period. These edges are sufficient to recover the clock without the use of a PLL and, this recovery is not dependent on data length or data content.

While building an encoder and decoder that encodes the two bit streams for transmission on respective data channels is readily accomplished, such system may introduce errors in the bit stream because of skew between the two bit streams. That is, propagation delays for the two bit streams32,36may not be, and likely are not, identical. In this regard,FIG. 3illustrates a signal versus time chart30′, substantially similar to signal versus time chart30ofFIG. 2, but with skew52arising in Manchester stream42′, which in turn causes a change in the transition46′ relative to transition46. The skew52causes the logical OR of transitions46′,48(see signal50′) to include double pulses54,56. Such double pulses54,56may cause unwanted sampling of the data in a predominantly digital system.

Thus, it may advantageous to filter out double pulses54,56that occur within a predefined threshold. Such predefined threshold may be set based on an expected timing skew on the bus. An exemplary solution to this issue is provided in a communication system60ofFIG. 4A. In particular, a one-shot circuit (e.g., a monstable multivibrator) may be used to cull the double pulses. In this regard, the communication system60includes an encoder62and a decoder64. The encoder62receives a first data signal (e.g., bit stream32) from a first data source, a second data signal (e.g., bit stream36) from a second data source, and a clock signal (e.g., clock signal40) from a clock. Note that in an exemplary aspect, the data sources and clock may be part of the same integrated circuit as the encoder62, or the data sources and/or the clock may be positioned off chip. The clock signal40is passed to an inverter66, flip flops68,70and exclusive OR (XOR) gates72,74. Flip flop68also receives bit stream32and outputs to the XOR gate72. Similarly, flip flop70receives bit stream36and outputs to the XOR gate74. The propagation delay through the flip flops68,70to the XOR gates72,74will always be greater than the delay of the clock signal40to the XOR gates72,74. Collectively, the inverter66, the flip flop68, and the XOR gate72are a first stream encoder73. Likewise, collectively, the flip flop70and XOR gate74are second stream encoder75. The outputs of the XOR gates72,74couple the Manchester encoded bit streams into to respective data channels76,78, which are both received by decoder64.

With continued reference toFIG. 4A, the decoder64receives the signals from the data channels76,78and processes them with first stream decoder77and second stream decoder79respectively. The incoming signal from the data channel76is split into a delay element80, an inverted input of an AND gate82and an XOR gate84. The output of the delay element80is provided to an inverted input of an AND gate86, an input of AND gate82and the XOR gate84. The AND gate86effectively detects the rising edge of the received signal. Similarly, the AND gate82effectively detects the falling edge of the received signal. The XOR gate84detects the transitions on the data channel. The output of the XOR gate84is provided to an OR gate88. The output of the AND gates82,86is provided to a latch98.

With continued reference toFIG. 4A, the decoder64processes the signal from the data channel78in similar fashion. In particular, the incoming signal from the data channel78is split into a delay element90, an inverted input of an AND gate92and an XOR gate94. The output of the delay element90is provided to an inverted input of an AND gate96, an input of AND gate92and the XOR gate94. The AND gate96effectively detects the rising edge of the received signal. Similarly, the AND gate92effectively detects the falling edge of the received signal. The XOR gate94detects the transitions on the data channel. The output of the XOR gate94is provided to the OR gate88. The output of the AND gates92,96is provided to a latch100.

With continued reference toFIG. 4A, the output of the OR gate88is provided to a one-shot circuit102. The one shot circuit102provides an output to a toggle flop104. Collectively the OR gate, the one shot circuit102and the toggle flop104may be considered a clock recovery circuit105. The output of the toggle flop104is the recovered clock signal106, which is provided to a flip flop108and an inverter110. The output of the inverter110is provided to a flip flop112. The output of the flip flop108is the recovered bit stream32(i.e., a recovered version of SRC_DATA_A). Likewise, the output of the flip flop112is the bit stream36(i.e., a recovered version of SRC_DATA_B).

In Manchester encoding, a logical one or logical zero are represented by rising or falling edges in the serial data stream. For this reason, the latches98,100can be used to detect the logic level of the serial data from the respective AND gates (82and86for latch98or92and96for latch100). Note that the latches98and100have different phases (e.g., opposite polarity) on the set and reset inputs due to the fact that the data has different phases on the source encoding. The XOR gates84,94are used to fire the one-shot circuit102to recover the clock signal. The correct polarity of the recovered clock is used to sample the two latches98,100to recover the data. The lower limit on the one-shot circuit102is the maximum expected bus skew. The upper limit on the one-shot circuit102is derived from one half the clock frequency and other internal circuit delays. This arrangement effectively limits the bus frequency, but allows circuit designers sufficient leeway in designing circuits.

Fewer errors arise if the communication system does not have slivers. Accordingly,FIG. 4Billustrates an exemplary communication system60″ similar to communication system60, but with fewer (or no slivers). Many of the elements are substantially similar to those previously described. In the encoder62″, a clock doubler400is used to provide a clock signal to second rank flip flops402,404. Likewise, the decoder64″, some elements are eliminated and inverters406,408provide signals to flip flops108,112. This arrangement removes slivers as desired. Note that the clock doubler400may be eliminated if the flip flops402,404were sensitive to both riding and falling edges.

In the event that there is not enough leeway because of the limits on the bus frequency, an additional aspect of the present disclosure allows for use of a delay locked loop (DLL) to equalize bus propagation delays. In this regard,FIG. 5Aillustrates a communication system60′ substantially similar to communication system60but decoder64′ has a delay equalization circuit114(e.g., a DLL). The delay equalization circuit114may use a SYNC bit to measure propagation delays. In practice, the SYNC bit is inserted at the encoder62and may force a transition both data streams simultaneously. The difference in the arrival of the two transitions on the data channels76,78may be measured and used to adjust delay elements in the delay equalization circuit114to reduce skew between the signals on the different data channels76,78.

FIG. 5Billustrates a communication system60″′ that is similar to communication system60″ ofFIG. 4B, but includes the delay equalization circuit114″″, which is substantially similar to the delay equalization circuit114described above with reference toFIG. 5A.

Simulation shows that aspects of the present disclosure provide substantial benefit. In this regard,FIG. 6illustrates one exemplary simulation120with inputs and results. In particular, simulation120includes original encoded signals122,124corresponding to Manchester bit streams32,36. Further, signal126corresponds to the output of AND gate86, signal128corresponds to the output of AND gate82, and signal130corresponds to the output of the latch98. Similarly, signal132corresponds to the output of AND gate96, signal134corresponds to the output of AND gate92, and signal136corresponds to the output of the latch100.

With continued reference toFIG. 6, signal138is the output of the OR gate88, signal140is the output of the one-shot circuit102, and signal142corresponds to the recovered clock signal106. The double pulses144of the skew can be seen on signal138. However, the one-shot circuit102effectively filters these double pulses144. The signal146corresponds to the original source clock signal40. The signal148corresponds to the original Manchester bit stream32and signal150corresponds to original Manchester bit stream36. The signal152is identical to signal142and is the recovered clock signal106. The signal154is the output of the flip flop108and the signal156is the output of the flip flop112and corresponds to the recovered data signals respectively. As is readily apparent, the recovered clock is distorted relative to the original clock signal40. However, the data is properly recovered. Specifically, since the clock is embedded into the data, proper data sampling is provided. In this example, the signal148is three bits and signal150is two bits. The efficiency is five bits per three clock pulses (i.e., 1.67 bits/clock). In comparison, a typical serial interface has an efficiency of one bit per clock pulse. Thus, with eight clocks, fifteen bits can be transmitted, which results in an efficiency of 1.875 bits/clock. The size of signal transmitted can increase arbitrarily without risks associated with systems that require a PLL.

While a two stream system is suitable for some implementations, the present disclosure is not so limited. In particular, N-streams may be used. By way of further example, a three stream case is explored herein. Instead of shifting the streams by 180 degrees as in the two stream case ofFIG. 2described above, the streams are shifted by 120 degrees. Whereas, in the two stream case, the mid-bit transition of a first stream can coincide with the inter-bit transition of the second stream, the three stream case has no coincident mid-bit and inter-bit transitions. Avoiding such coincident transitions eliminates the need for the one-shot circuit102ofFIG. 4. Elimination of the one-shot circuit102allows generation of an all digital receiver that can be developed in a hardware description language (HDL), such as VERILOG (e.g. standard 1800-2012 Feb. 21, 2013 or other IEEE standard, such as IEEE 1364-2005, 1364-2001). Such generic description may then be provided to different foundries for production. Three streams also allows phased detection. During phased detection, only one stream is detected at a given time. While detecting the one stream, the other two streams are ignored, which allows inter-bit transitions on the other two streams to be ignored. Inter-bit transitions do not contain useful information, so ignoring the inter-bit transitions does not negatively impact data transfer.

In this regard,FIG. 7illustrates a three stream timing diagram180. Signal182corresponds to the clock signal shifted by a first phase amount (e.g., 0 degrees). Signal184corresponds to the clock signal shifted by a second phase amount (e.g., 120 degrees). Signal186corresponds to the clock signal shifted by a third phase amount (e.g., 240 degrees). Respective Manchester encoded streams188,190, and192are created according to a Manchester encoding algorithm.

The three Manchester encoded streams188,190, and192are provided to a receiver such as receiver200illustrated inFIG. 8. The Manchester encoded streams188,190,192are split and provided to respective delay elements202,204, and206, as well as, respective latches208,210,212. The output of the delay elements202,204,206are provided with the original Manchester encoded streams188,190,192to respective XOR gates214,216, and218. The outputs of the XOR gates214,216, and218are provided to a multiplexer (MUX)220. The MUX220is controlled by a mod-3 counter222to select between the signals received from the XOR gates214,216, and218and output one of the signals to AND gates224,226, and228. The output of the mod-3 counter222is also provided to the AND gates224,226, and228through filters230,232,234. The outputs of the AND gates224,226, and228are provided to the clock inputs of the latches208,210, and212. This arrangement allows the receiver200to mask out unselected streams. That is, the MUX220masks out two of the three streams (as dictated by the output of the mod-3 counter222). As an unmasked edge is detected, the mod-3counter222increments and stores the associated data bit. The filters230,232,234select which AND gate224,226,228is active based on the output of the mod-3 counter so as to clock the desired latch208,210,212, which generate received data236,238,240.

With continued reference toFIG. 8, all the elements of the receiver200may be implemented in hardware designed in an HDL that is fully synthesized into an all-digital circuit.

Returning toFIG. 7, the receiver200may implement a phased detection algorithm. The algorithm uses the XOR gate214to perform edge detection on Manchester encoded stream188. During this time, Manchester encoded streams190,192are masked off. Once an edge is detected, an associated Boolean data bit is stored for a Manchester encoded stream188. The MUX220then selects the output of the XOR gate216, and Manchester encoded streams188,192are masked off. Once an edge is detected on Manchester encoded stream190, an associated Boolean data bit is stored. The MUX220then selects the output of the XOR gate218, and Manchester encoded streams188,190are masked off. Once an edge is detected on Manchester encoded stream192, an associated Boolean data bit is stored. At this time, one complete period of the source clock has expired and the receiver has stored three data bits. The MUX220selects the output of the XOR gate214and the process repeats.

With reference toFIG. 7, by the time the mid-bit transition242has occurred on Manchester encoded stream192, the inter-bit transition244on Manchester encoded stream188was ignored by the MUX220because the Manchester encoded stream188was masked off. This arrangement guarantees the next transition on Manchester encoded stream188is a mid-bit transition. In general, this method effectively masks out all inter-bit transitions and only samples mid-bit transitions.

With phased detection, the falling edges of all three phased source clocks are recovered. Two of the edge detected streams can be ORed together to drive a toggle flip flop to recover a clock. The clock will not have a fifty percent duty cycle, but it will have the correct frequency.

The multi-Manchester stream may work with arbitrarily low frequencies because they do not need the same sorts of delays used in other non-PLL designs. It should also be appreciated that the multi-Manchester stream can be used in place of any synchronous serial interface. Manchester encoding inherently has a zero average rather than a forced zero average such as 8b/10b. As a further advantage, in interfaces that have a large number of parallel data bits (e.g., memory), the need to have a large peak current when all data bits transition at the same time is reduced in the multi-Manchester system because of the staggered phase differences. Thus, peak current may be reduced.

It should be appreciated that in systems with very large buses and high periods, it can become difficult to create a unique source clock phase for each data bit. In these instances, the bus can be broken up into M groups that contain N bits each. In each group, there can be N phases of the source clock. Each group can individually detect the corresponding N bits. After each clock period, the M groups are combined into one M*N sized word. In this regard, Figure illustrates an example of a three stream case expanded into M=2 groups.