Memory device including multiple gate-induced drain leakage current generator circuits

Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.

BACKGROUND

Memory devices are widely used in computers and many electronic items to store information. A memory device usually has numerous memory cells. The memory device performs a write operation to store information in the memory cells, a read operation to retrieve the stored information, and an erase operation to clear information (e.g., obsolete information) from some or all of the memory cells. The reliability of these operations highly depends on the structure of the memory device and the techniques used to operate it. Some conventional memory devices have structures and operations that are reliable for some applications but unsuitable for other applications.

DETAILED DESCRIPTION

FIG. 1shows a block diagram of an apparatus in the form of a memory device100, according to some embodiments described herein. Memory device100can include a memory array (or multiple memory arrays)101containing memory cells102arranged in blocks (memory cell blocks), such as blocks1030and1031. In the physical structure of memory device100, memory cells102can be arranged vertically (e.g., stacked over each other) over a substrate (e.g., a semiconductor substrate) of memory device100.FIG. 1shows memory device100having two blocks1030and1031as an example. Memory device100can have more than two blocks (e.g., up to thousands or more blocks).

As shown inFIG. 1, memory device100can include access lines (which can include word lines)150and data lines (which can include bit lines)170. Access lines150can carry signals (e.g., word line signals) WL0through WLm. Data lines170can carry signals (e.g., bit line signals) BL0through BLn. Memory device100can use access lines150to selectively access memory cells102of blocks1030and1031and data lines170to selectively exchange information (e.g., data) with memory cells102of blocks1030and1031.

Memory device100can include an address register107to receive address information (e.g., address signals) ADDR on lines (e.g., address lines)103. Memory device100can include row access circuitry108and column access circuitry109that can decode address information from address register107. Based on decoded address information, memory device100can determine which memory cells102of which of blocks1030and1031are to be accessed during a memory operation. Memory device100can perform a read operation to read (e.g., sense) information (e.g., previously stored information) in memory cells102of blocks1030and1031, or a write (e.g., programming) operation to store (e.g., program) information in memory cells102of blocks1030and1031. Memory device100can use data lines170associated with signals BL0through BLn to provide information to be stored in memory cells102or obtain information read (e.g., sensed) from memory cells102. Memory device100can also perform an erase operation to erase information from some or all of memory cells102of blocks1030and1031.

Memory device100can include a control unit118that can be configured to control memory operations of memory device100based on control signals on lines104. Examples of the control signals on lines104include one or more clock signals and other signals (e.g., a chip enable signal CE#, a write enable signal WE#) to indicate which operation (e.g., read, write, or erase operation) memory device100can perform.

Memory device100can include sense and buffer circuitry120that can include components such as sense amplifiers and page buffer circuits (e.g., data latches). Sense and buffer circuitry120can respond to signals BL_SEL0through BL_SELn from column access circuitry109. Sense and buffer circuitry120can be configured to determine (e.g., by sensing) the value of information read from memory cells102(e.g., during a read operation) of blocks1030and1031and provide the value of the information to lines (e.g., global data lines)175. Sense and buffer circuitry120can also can be configured to use signals on lines175to determine the value of information to be stored (e.g., programmed) in memory cells102of blocks1030and1031(e.g., during a write operation) based on the values (e.g., voltage values) of signals on lines175(e.g., during a write operation).

Memory device100can include input/output (I/O) circuitry117to exchange information between memory cells102of blocks1030and1031and lines (e.g., I/O lines)105. Signals DQ0through DQN on lines105can represent information read from or stored in memory cells102of blocks1030and1031. Lines105can include nodes within memory device100or pins (or solder balls) on a package where memory device100can reside. Other devices external to memory device100(e.g., a memory controller or a processor) can communicate with memory device100through lines103,104, and105.

Memory device100can receive a supply voltage, including supply voltages Vcc and Vss. Supply voltage Vss can operate at a ground potential (e.g., having a value of approximately zero volts). Supply voltage Vcc can include an external voltage supplied to memory device100from an external power source such as a battery or alternating current to direct current (AC-DC) converter circuitry.

Each of memory cells102can be programmed to store information representing a value of at most one bit (e.g., a single bit) or a value of multiple bits such as two, three, four, or another number of bits. For example, each of memory cells102can be programmed to store information representing a binary value “0” or “1” of a single bit. The single bit per cell is sometimes called a single-level cell. In another example, each of memory cells102can be programmed to store information representing a value for multiple bits, such as one of four possible values “00”, “01”, “10”, and “11” of two bits, one of eight possible values “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111” of three bits, or one of other values of another number of multiple bits. A cell that has the ability to store multiple bits is sometimes called a multi-level cell (or multi-state cell).

Memory device100can include a non-volatile memory device, and memory cells102can include non-volatile memory cells, such that memory cells102can retain information stored thereon when power (e.g., voltage Vcc, Vss, or both) is disconnected from memory device100. For example, memory device100can be a flash memory device, such as a NAND flash (e.g., 3-dimensional (3-D) NAND) or a NOR flash memory device, or another kind of memory device, such as a variable resistance memory device (e.g., a phase change memory device or a resistive RAM (Random Access Memory) device).

One of ordinary skill in the art may recognize that memory device100may include other components, several of which are not shown inFIG. 1so as not to obscure the example embodiments described herein. At least a portion of memory device100can include structures and perform operations similar to or identical to the structures and operations of any of the memory devices described below with reference toFIG. 2throughFIG. 12.

FIG. 2Ashows a block diagram of a portion of a memory device200including a memory array201having circuits285_1,285_2,285_3,285_4,287_1,287_2,287_3,287_4, memory cell strings231through240,291, and292, select circuits241through252and241′ through252′, according to some embodiments described herein. Memory device200can correspond to memory device100ofFIG. 1. For example, memory array201can form part of memory array101ofFIG. 1.

As described in more detailed with reference toFIG. 2B,FIG. 2C, andFIG. 2D, circuits285_1,285_2,285_3, and285_4and circuits287_1,287_2,287_3,287_4can be used to generate GIDL current to help improve an erase operation of memory device200. Thus, circuits285_1,285_2,285_3, and285_4can be called current generator circuits (e.g., top GILD current generator circuits) and circuits287_1,287_2,287_3,287_4can also be called current generator circuits (e.g., bottom GIDL current generator circuits). InFIG. 2A, “C.G. Circuit” stands for “current generator circuit”.

As shown inFIG. 2A, memory device200can include blocks (blocks of memory cells)2030and2031. Two blocks are shown as an example. Memory device200can include many blocks (e.g., up to thousands or more blocks). Each of blocks2030and2031has its own memory cell strings and associated select circuits and GIDL current generator circuits. For example, block2030has memory cell strings231through236, select circuits241through246and241′ through246′, circuits285_1and285_2, and circuits287_1and287_2. Block2031has memory cell strings237through240,291, and292, select circuits247through252and247′ through252′, circuits285_3and285_4, and circuits287_3and287_4.

Each of memory cell strings231through240,291, and292has memory cells (shown inFIG. 2B) arranged in a string (e.g., coupled in series among each other) to store information. During an operation (e.g., write or read) of memory device200, memory cell strings231through240,291, and292can be individually selected to access the memory cells in the selected memory cell string in order to store information in or retrieve information from the selected memory cell strings. Thus, in a write operation, the selected memory cell strings are memory cell strings (among memory cell strings231through240,291, and292) selected to store information in selected memory cells of the selected memory cell strings. In a read operation, the selected memory cell strings are memory cell strings (among memory cell strings231through240,291, and292) selected to read information from selected memory cells of the selected memory cell strings. During an erase operation, some or all of the memory cell strings in a particular block can be selected (e.g., concurrently selected) to erase information from them.

Each of the memory cell strings231through240,291, and292, can be associated with (e.g., coupled to) two select circuits and two current generator circuits. For example, memory cell string231is associated with select circuit (e.g., top select circuit)241, select circuit (e.g., bottom select circuit)241′, circuit285_1(directly above select circuit241), and circuit287_1(directly below select circuit241′).FIG. 2Ashows an example of six memory cell strings and their associated circuits (e.g., top and bottom select circuits and top and bottom GIDL current generator circuits) in each of blocks2030and2031. The number of memory cell strings and their associated select circuits and current generator circuits in each of blocks2030and2031can vary.

Memory device200can include lines270,271, and272that carry signals BL0, BL1, and BL2, respectively. Lines270,271, and272can correspond to data lines170ofFIG. 1. InFIG. 2A, each of lines270,271, and272can be structured as a conductive line and can form part of a respective data line (e.g., bit line) of memory device200. The memory cell strings of blocks2030and2031can share lines270,271, and272. For example, memory cell strings231,232,237, and238can share line270. Memory cell strings233,234,239, and240can share line271. Memory cell strings235,236,291, and292can share line272.FIG. 2Ashows three lines (e.g., data lines)270,271, and272as an example. The number of data lines can vary.

Memory device200can include a line299that can carry a signal SRC (e.g., source line signal). Line299can be structured as a conductive line and can form part of a source (e.g., a source line) of memory device200. Blocks2030and2031can share line299.

Memory device200can include separate control lines in blocks2030and2031. As shown inFIG. 2A, memory device200can include control lines2200,2210,2220, and2230that can carry corresponding signals (e.g., word line signals) WL00, WL10, WL20, and WL30. Memory device200can include control lines2201,2211,2221, and2231that can carry corresponding signals (e.g., word line signals) WL01, WL11, WL21, and WL31.FIG. 2Ashows four control lines (2200through2230or2201through2231) in each of blocks2030and2031as an example. The number of control lines can vary.

Control lines2200through2230and2201through2231can form part of respective access lines (e.g., similar to access lines150ofFIG. 1) of memory device200to access memory cells in a respective block. For example, during a read or write operation to store information in or retrieve information from a memory cell (or memory cells) in block2030, control lines2200,2210,2220, and2230can be activated (e.g., provided with positive voltages) to access a selected memory cell (or memory cells) in block2030. In memory device200, blocks2030and2031(which share lines270,271, and272) can be accessed (e.g., accessed during a read or write operation) one block at a time. Thus, in the example here, control lines2201,2211,2221, and2231of block2031can be deactivated (e.g., provided with zero volts (e.g., ground)) when control lines2200,2210,2220, and2230of block2030are activated.

As shown inFIG. 2A, memory device200can include double (e.g., upper and lower) drain select lines, including select lines281A,282A,283A, and284A(e.g., upper drain select lines) and select lines281B,282B,283B, and284B, (e.g., lower drain select lines). Each of select lines281A,282A,283A, and284Acan carry a separate (e.g., different) signal (e.g., an upper select line signal) SGDA. Each of select lines281B,282B,283B, and284Bcan carry a separate signal (e.g., a lower select line signal) SGDB.

As shown inFIG. 2A, select circuits241,243, and245can share select lines281Aand281B. Select circuits242,244, and246can share select line282Aand282B. Select circuits247,249, and251can share select line283Aand283B. Select circuits248,250, and252can share select line284Aand284B. Each of select circuits241through252can include multiple select gates (e.g., multiple transistors, shown inFIG. 2B) that can be controlled (e.g., turned on or turned off) by two respective select lines (e.g.,281Aand281B,282Aand282B,283Aand283B, or284Aand284B).

Memory device200can include double (e.g., lower and upper) source select lines, including select lines281′Aand283′A(e.g., lower source select lines) and select lines281′Band283′B(e.g., upper source select lines). Each of select lines281′Aand283′Acan carry a separate (e.g., different) signal SGSA. Each of select lines281′Band283′Bcan carry a separate (e.g., different) signal SGSB. In an alternative arrangement of memory device200, lines281′Aand283′Acan carry the same signal, and lines281′Band283′Bcan carry the same signal.

Select circuits241′ through246′ can share select lines281′Aand281′B. Select circuits247′ through252′ can share select lines283′Aand283′B. Each of select circuits241′ through252′ can include multiple select gates (e.g., multiple transistors, shown inFIG. 2B) that can be controlled (e.g., turned on or turned off) by two respective select lines (e.g.,281′Aand281′B, or283′Aand283′B).

Each of circuits (e.g., top GIDL current generator circuits)285_1,285_2,285_3, and285_4can be coupled in series with a respective select circuit (among select circuits241through252) between a respective data line (one of lines270,271, and272) and a respective memory string (among memory cell strings231through240,291, and292). Each of circuits285_1,285_2,285_3, and285_4can include multiple transistors (shown inFIG. 2B).

As shown inFIG. 2A, memory device200can include lines280_1A,280_2A,280_3A, and280_4A, each of which can carry a separate (e.g., different) signal GGA. Memory device200also includes lines280_1B,280_2B,280_3B, and280_4B, each of which can carry a separate signal GGB. Lines280_1A,280_2A,280_3A,280_4A,280_1B,280_2B,280_3B, and280_4Bcan be coupled to the gates of respective transistors (shown inFIG. 2B) of circuits285_1,285_2,285_3, and285_4. Thus, lines280_1A,280_2A,280_3A,280_4A,280_1B,280_2B,280_3B, and280_4Bcan be called transistor gate lines.

As shown inFIG. 2A, circuits285_1can share lines280_1Aand280_1B. Circuits285_2can share lines280_2Aand280_2B. Circuits285_3can share lines280_3Aand280_3B. Circuits285_4can share lines2804A and280_4B. Each of circuits285_1,285_2,285_3, and285_4can be controlled (e.g., turned on or turned off) by two respective transistor gate lines (e.g.,280_1Aand280_1B,280_2Aand280_2B,280_3Aand280_3e, or280_4Aand280_4B).

Each of circuits (e.g., bottom GIDL current generator circuits)287_1,287_2,287_3, and287_4can be coupled in series with a respective select circuit (among select circuits241′ through252′) between line299and a respective memory string (among memory cell strings231through240,291, and292). Each of circuits287_1,287_2,287_3, and287_4can include a transistor (shown inFIG. 2B).

As shown inFIG. 2A, memory device200can include lines289_1Band289_3B, each of which can carry a separate (e.g., different) signal GG′B. Lines289_1Band289_3Bcan be coupled to the gates of respective transistors (shown inFIG. 2B) of circuits287_1,287_2,287_3, and287_4. Thus, lines289_1Band289_3Bcan be called transistor gate lines.

As shown inFIG. 2A, circuits287_1and287_2can share lines289_1l. Circuits287_3and287_4can share lines289_3B. Each of circuits287_1,287_2,287_3, and287_4can be controlled (e.g., turned on or turned off) by a respective transistor gate line (e.g.,289_1Band289_3B).

During an operation (e.g., read or write operation) of memory device200, signals GGAand GGBcan be used to activate (e.g., turn on) respective circuits285_1,285_2,285_3, and285_4, and signal GG′Bcan be used to activate (e.g., turn on) respective circuits287_1,287_2,287_3, and287_4. Activating circuits285_1,285_2,285_3, and285_4can include providing (e.g., applying) voltages to signals GGAand GGB. Activating circuits287_1,287_2,287_3, and287_4can include providing (e.g., applying) voltages to signal GG′B.

The voltages provided to each of signal GGA, GGB, and GG′Bcan have different values for different operations of memory device200. For example, the values of the voltages provided to signals GGA, GGB, and GG′Bduring an erase operation can be much higher (e.g., two times or higher) than the values of the voltages provided to signals GGA, GGB, and GG′Bduring a read or write operation.

During an operation of memory device200, one or both select circuits associated with a selected memory cell string can be activated (e.g., by turning on the transistors in the select circuits), depending on which operation memory device200performs on the selected memory cell string. During an operation of memory device200, memory device200can select a memory cell of a particular memory cell string as a selected memory cell in order to store information in (e.g., during a write operation) or to retrieve information from (e.g., during a read operation) the selected memory cell. During an erase operation, memory device200can select a block as a selected block to erase information from memory cells in a portion (e.g., a sub-block) of the selected block or memory cells from the entire selected block.

Activating a particular select circuit among select circuits247through252during an operation of memory device200can include providing (e.g., applying) voltages having certain values to signals SGDAand SGDBassociated with that particular select circuit. Activating a particular select circuit among select circuits247′ through252′ can include providing (e.g., applying) voltages having certain values to signals SGSAand SGSBassociated with that particular select circuit. When a particular select circuit among select circuits241through252is activated during a particular operation, it can couple (e.g., form a current path from) a selected memory cell string associated with that particular select circuit to a respective data line (e.g., one of lines270,271, or272) through a respective circuit among circuits285_1,285_2,285_3, and285_4(which is also activated during that particular operation). When a particular select circuit among select circuits241′ through252′ is activated, it can couple (e.g., form a current path from) a selected memory cell string associated with that particular select circuit to a source (e.g., line299) through a respective circuit among circuits287_1,287_2,287_3, and287_4(which is also activated during that particular operation).

FIG. 2Bshows a schematic diagram of memory device200ofFIG. 2A, according to some embodiments described herein. For simplicity,FIG. 2Bshows labels for only four memory cell strings231,232,237and238, eight select circuits241,242,247,248,241′,242′,247′, and248′, and labels for some of the top GIDL current generator circuits (e.g.,285_1,285_2,285_3, and285_4) and some of the bottom GIDL current generator circuits (e.g.,287_1,287_2,287_3, and287_4).

As shown inFIG. 2B, memory device200can include memory cells210,211,212, and213, select gates (e.g., drain select gates)261and262and select gates (e.g., source select gates)263and264that can be physically arranged in three dimensions (3-D), such as x, y, and z dimensions with respect to the structure (shown inFIG. 3) of memory device200.

InFIG. 2B, each of the memory cell strings (e.g., strings231,232,237and238) of memory device200can include one of memory cells210, one of memory cells211, one of memory cells212, and one of memory cells213coupled in series among each other.FIG. 2Bshows an example where memory device200has four levels (e.g., four tiers) of respective memory cells210,211,212, and213and four memory cells in each of the memory cell strings. The number of levels (e.g., tiers) of memory cells of memory device200can vary. Thus, the number of memory cells in each memory cell string can also vary. Further, one skilled in the art would recognize that some of the memory cells among memory cells210,211,212, and213of memory cell strings231,232,237and238, may be dummy memory cells. Dummy memory cells are memory cells that are not configured to store information. Dummy memory cells may be configured for purposes known to those skilled in the art. In some examples of memory device200, one or two (or more) of memory cells at the two ends of each memory cell strings231,232,237and238(e.g., memory cells immediately next to select gates262, select gates264, or both select gates262and264) may be dummy memory cells.

As shown inFIG. 2B, memory device200can include transistors286and288. Each of circuits285_1,285_2,285_3, and285_4can include two of transistors286. Each of circuits287_1,287_2,287_3, and287_4can include one of transistors288. Each of transistors286and288can operate as a switch during a read or write operation of memory device200. During a read or write operation, signals GGA, GGB, and GG′Bat particular current generator circuits (among circuits285_1,285_2,285_3,285_4,287_1,287_2,287_3, and287_4) associated with selected memory cell strings of a selected block (e.g., block2030or2031) can be provided with voltages, such that transistors286and288associated with those particular current generator circuits can be turned on. During an erase operation, signal GGA, GGB, and GG′Bof a selected block can be provided with voltages to cause transistors286and288of the selected block to be in a condition such that GIDL current can be generated to help improve the erase operation of memory device200.

As shown inFIG. 2B, each of select circuits241,242,247, and248can include two select gates (e.g., two drain select gates): one of select gates261and one of select gates262. Each of select circuits241′,242′,247′, and248′ can include two select gates (e.g., two source select gates): one of select gates263and one of select gates264. Each of select gates261,262,263, and264can operate as a transistor.FIG. 2Bshows each of select gates261,262,263, and264and transistors286and288as having the same structure as memory cells210,211,212, and213as an example. In some examples of memory device200, some or all of select gates261,262,263, and264and transistors286and288can have a structure (e.g., a structure of a field effect transistor (FET)) different from the structure of memory cells210,211,212, and213).

In memory device200, a select line (e.g., a drain select line281A,282A,283A,284A,281a,282B,283B, or284B, or a source select line281′A,281′B,283′A, or283′B) can carry a signal (e.g., signal SGDA, SGDB, SGSA, or SGSB) but a select line does not operate like a switch (e.g., a transistor). A select gate (e.g., a drain select gate261or262or a source select gate263and264) can receive a signal from a respective select line and can operate like a switch (e.g., a transistor).

In this description, a line (e.g., any of drain select lines281A,282A,283A,284A,281B,282B,283B, and284B, any of source select lines281′A,281′B,283′A, and283′B, any of transistor gate lines280_1A,280_2A,280_3A,280_4A,280_1B,280_2B,280_3B,280_4B,289_1A,289_3A(FIG. 5A),289_1B, and289_3B, and any of control lines2200through2230and2201through2231) includes a piece of conductive material, a region of conductive material, a layer of conductive material, or any shape of a structure that can carry an electrical signal. Thus, in this description, a line includes a “line” shape structure and any other structural shapes (e.g., a region of any shape, a layer shape, and other shapes).

In order to focus on the embodiments discussed herein, the description below with reference toFIG. 2CandFIG. 2Dfocuses on four memory cell strings231,232,237, and238, select circuits241,242,247,248,241′,242′,247′, and248′, some of the current generators circuits (e.g., circuits285_1,285_2,285_3,285_4,287_1,287_2,287_3, and287_4). Other memory cell strings, select circuits, and current generator circuits of memory device200have similar structures and connections.

FIG. 2Cshows a schematic diagram of a portion of memory device200ofFIG. 2Bincluding line270, circuits285_1,285_2,285_3,285_4, select circuits241,242,247, and248, memory cell strings231,232,237, and238, select circuits241′,242′,247′, and248′, circuits287_1,287_2,287_3, and287_4, and line299, according to some embodiments described herein. As shown inFIG. 2C, select gates261and262of each of select circuits241,242,247, and248can be coupled in series with two of transistors286between line270and a respective memory cell string among memory cell strings231,232,237, and238. Select gates263and264of each of select circuits241′,242′,247′, and248′ can be coupled in series with a transistor among transistors288between line299and a respective memory cell string among memory cell strings231,232,237, and238.

Select gate261of select circuit241has a terminal (e.g., a transistor gate) that can be part of (e.g., formed by a portion of) select line281A. Select gate262of select circuit241has a terminal (e.g., a transistor gate) that can be part of (e.g., formed by a portion of) select line281B. Select gates261and262of select circuit241can be controlled (e.g., turned on or turned off) by signals SGDAand SGDBprovided to select lines281Aand281B, respectively.

Select gate263of select circuit241′ has a terminal (e.g., a transistor gate) that can be part of (e.g., formed by a portion of) select line281′A. Select gate264of select circuit241′ has a terminal (e.g., a transistor gate) that can be part of (e.g., formed by a portion of) select line281′B. Select gates263and264of select circuit241′ can be controlled (e.g., turned on or turned off) by signals SGSAand SGSBprovided to select lines281′Aand281′B, respectively.

Similarly, as shown inFIG. 2C, select gates261and262of each of select circuits242,247, and248also have terminals (transistor gates) that can be parts of (e.g., formed by portions of) respective select lines among select lines282A,283A,284A,282B,283B, and284B. Select gates263and264of each of select circuits242′,247′, and248′ also have terminals (transistor gates) that can be part of (e.g., formed by a portions of) respective select lines among select lines281′A,283′A,281′B, and283′B.

Each of transistors286and288has a terminal (e.g., a transistor gate) that can be part of (e.g., formed by a portion of) a respective transistor gate line. For example, transistor286of circuit285_1associated with signal GGAhas a transistor gate that can be part of line (e.g., transistor gate line)280_1A. In another example, transistor286of circuit285_1associated with signal GGBhas a transistor gate that can be part of line (e.g., transistor gate line)280_1B. In a further example, transistor288of circuit287_1has a transistor gate that can be part of line (e.g., transistor gate line)289_1B.

During an operation (e.g., a read or write operation) of memory device200, select gates261,262,263, and264and transistors286and288of particular select circuits associated with a selected memory cell string can be selectively activated (e.g., turned on) to couple the selected memory cell string to a respective data line (e.g., line270,271, or272) and the source (e.g., line299). For example, inFIG. 2C, during a write operation of memory device200, if memory cell string231is a selected memory cell string, then select gates261and262of select circuit241, transistors286of circuits285_1, and transistor288of circuit287_1can be activated to couple memory cell string231to line270; select gates263and264of select circuit241′ may not be activated in this example.

In another example, inFIG. 2C, during a read operation of memory device200, if memory cell string231is a selected memory cell string, then select gates261and262of select circuit241and transistors286of circuits285_1, and transistor288of circuit287_1can be activated to couple memory cell string231to line270; select gates263and264of select circuit241′ can also be activated in this example to couple memory cell string231to line299. In these two examples here, while memory cell string231is selected, memory cell strings232,237, and238can be deselected. Thus, select gates261,262,263, and264in select circuits242,247,248,242′,247′, and248′ (associated with memory cell strings232,237, and238that are deselected) and transistors286of circuits285_2,285_3, and285_4can be deactivated (e.g., turned off) to decouple memory cell strings232,237, and238from line270and line299.

In an erase operation of memory device200, signals SGDA, SGDB, SGSA, and SGSBon respective drain and source select gates of a selected block (a block selected to erase information from it) can be provided with voltages having values much higher than the values of voltages provided to these signals during a read or write operation (example values shown inFIG. 2D). As described above with reference toFIG. 2A, signals GGA, GGB, and GG′Bon respective transistor gate lines of a selected block can be provided with voltages having values much higher than the values of voltages provided to the these signals during a read or write operation (example values shown inFIG. 2D). In a deselected block of memory device200during read, write, and erase operations, the signals in the deselected block can be deactivated.

FIG. 2Dshows example waveforms of signals BL0, BL1, BL2, GGA, GGB, SGDA, SGDB, SGSA, SGSB, GG′B, and SRC of memory device200(FIG. 2AthroughFIG. 2C) during example erase, write, and read operations, according to some embodiments described herein. Signals SGDA, SGDB, SGSA, and SGSBshown inFIG. 2Dare associated with a block (e.g., either block2030or block2031) of memory device200that is selected during the example erase, write, and read operations.FIG. 2Domits other signals (e.g., some of signals shown inFIG. 2C) of memory device200to help focus on the embodiments of the memory device described herein. During erase, write, and read operations of memory device200, the omitted signals can be provided with voltages having values known to those skilled in the art.

The specific values of the voltages associated with erase, write, and read operations shown inFIG. 2Dand in this description here are example values. Other voltage values may be used.

The following description refers toFIG. 2B,FIG. 2C, andFIG. 2D. InFIG. 2D, each of voltages VERASEcan have a value greater than the value of each of voltages V1through V12, VPreCh, VBL, and V0. Voltage V0can be 0V (e.g., ground potential, such as Vss). Each of voltages V1through V12can have a positive value (e.g., a value greater than the value of voltage V0). Voltage VERASEcan have a value of approximately 20V. Voltage V1can be either voltage Vcc (e.g., a supply voltage of memory device200) or voltage Vpass. Voltage Vcc can have a value of approximately between 1V and 3V (or other values). Voltage Vpass can have a value that can cause unselected memory cells of a selected memory cell string to operate as an active conductive path (e.g., to conduct current) during a read or write operation. Voltage Vpass can have a value of approximately 3V to 5V (or other values). Voltage VPreChcan have a value between 0.5V up to the value of voltage Vcc. Each of voltages V2through V7can have a value equal to the value of voltage Vcc or other values to turn on respective drain select gates (e.g.,261and262inFIG. 2C) and source select gates (e.g.,263and264inFIG. 2C) during write and read operations. Voltages V8, V9, and V10can have the same value. Voltages V11and V12can have the same value. As an example, when voltage VERASEhas a value of approximately 20V, each of voltages V8, V9, and V10can have a value of approximately 10V, and each of voltages V11and V12can have a value of approximately 15V.

During the write operation, voltage VBLcan have a value that depends on the value (e.g., value of a bit) of information to be stored in a selected memory cell. During the read operation, voltage VBLcan have a value that depends on the value (e.g., value of a bit) of information sensed from a selected memory cell.

As shown inFIG. 2D, during the erase operation, signals BL0, BL1, and BL2and SRC can be provided with a voltage VERASEto erase information stored in memory cells210,211,212, and213of the memory strings of a selected block (e.g., block2030or block2031inFIG. 2C). Transistors286and288(FIG. 2C) can operate to generate GIDL current (e.g., operate as GIDL current generators) to help the erase operation. For example, the GIDL current generated by transistors286and288during the erase operation may speed up the charging of the body of the memory cell strings in the selected block.

As shown inFIG. 2D, the write operation of memory device200can have different stages, such as a write precharge stage (shown as “PreCh” during the write operation inFIG. 2D) and a program stage (shown as “Prgm” inFIG. 2D) after the write precharge stage. During the write precharge stage, signals BL0, BL1, and BL2can be provided with precharge voltage VPreCh. During the program stage, signals BL0, BL1, and BL2can have voltage VBL, V0, or a voltage having a value between the values of voltages V0and VBL, depending on the value of information to be stored in a selected memory cell of a memory cell string coupled to a respective line among lines270,271, and272(associated with signals BL0, BL1, and BL2). During the write operation, signals GGA, GGB, and GG′Bcan be provided with voltage V1, such that transistors286and288(FIG. 2C) can be activated (e.g., turned on); and signal SRC can be provided with voltage V1(e.g., Vcc). During the write operation, signals SGDAand SGDBcan be provided with voltages V2and V3, respectively, and signals SGSAand SGSBcan be provided with voltage V0.

The read operation of memory device200, as shown inFIG. 2D, can have different stages, such as a read precharge stage (shown as “PreCh” during a read operation inFIG. 2D) and a sense stage (shown as “Sense” inFIG. 2D) after the read precharge stage. During the read precharge stage, signals BL0, BL1, and BL2can be provided with precharge voltage VPreCh. During the sense stage, signals BL0, BL1, and BL2can have voltage VBLor V0, depending on the value of information sensed from a selected memory cell of a memory cell string coupled to a respective line among lines270,271, and272(associated with signals BL0, BL1, and BL2). During the read operation, signals GGA, GGB, and GG′Bcan be provided with voltage V1, such that transistors286and288(FIG. 2C) can be activated (e.g., turned on); and signal SRC can be provided with voltage V0. During the read operation, signals SGDAand SGDBcan be provided with voltages V4and V5, respectively; and signals SGSAand SGSBcan be provided with voltages V6and V7, respectively.

FIG. 3shows a side view of a structure of a portion of memory device200, according to some embodiments described herein. The structure of memory device200inFIG. 3corresponds to part of the schematic diagram of memory device200shown inFIG. 2C. For simplicity,FIG. 3shows the structure of memory device200that includes line270(and associated signal BL0), circuit (e.g., current generator circuit)285_1, select circuit241, memory cell string231, control lines2200,2210,2220, and2230, select circuit241′, and circuit (e.g., current generator circuit)287_1. Other similar elements of memory device200inFIG. 2A,FIG. 2B, andFIG. 2Ccan have structures such as the ones shown inFIG. 3.

As shown inFIG. 3, memory device200can include a substrate390over which memory cells210,211,212, and213of memory cell string231can be formed (e.g., formed vertically with respect to substrate390). Memory device200includes different levels307through317with respect to a z-dimension. Levels307through317are internal device levels between substrate390and line270of memory device200.

Select lines281Aand281Bcan be located in different levels (e.g., levels315and314, respectively), such that memory cell string231is between select lines281Aand281Band substrate390. Select lines281′Aand281′Bcan be located in different levels (e.g., levels308and309, respectively) between substrate390and memory cell string231.

Lines (e.g., transistor gate lines)280_1Aand280_1Bcan be located in different levels (e.g., levels317and316, respectively), such that select lines281Aand281Bare between lines280_1Aand280_1Band memory cell string231. Line (e.g., transistor gate line)289_1Bcan be located in level307, such that line289_1Bis between select lines281′Aand281′Band substrate390.

Substrate390of memory device200can include monocrystalline (also referred to as single-crystal) semiconductor material. For example, substrate390can include monocrystalline silicon (also referred to as single-crystal silicon). The monocrystalline semiconductor material of substrate390can include impurities, such that substrate390can have a specific conductivity type (e.g., n-type or p-type). Although not shown inFIG. 3, substrate390can include circuitry that can be located under memory array201(FIG. 2A), such as located directly under line299inFIG. 3. Such circuitry can include sense amplifiers, buffers (e.g., page buffers), decoders, and other circuit components of memory device200.

As shown inFIG. 3, line270can have a length extending in the direction of an x-dimension, which is perpendicular to the z-dimension and perpendicular to the y-dimension. Line270can include a conductive material (e.g., conductively doped polycrystalline silicon (doped polysilicon), metals, or other conductive materials). Line299can include a conductive material.FIG. 3shows an example where line299(e.g., source) can be formed over a portion of substrate390(e.g., by depositing a conductive material over substrate390). Alternatively, line299can be formed in or formed on a portion of substrate390(e.g., by doping a portion of substrate390).

As shown inFIG. 3, memory device200can include a pillar331having a length extending outwardly (e.g., vertically in the direction of the z-dimension of memory device200) from a conductive material region of line299. Pillar331can include portions343,344,345, and346.

Portion343(conductive portion) of pillar331has length extending in the direction (in the z-dimension) of the length of pillar331and can be coupled (e.g., directly coupled) to line270. For example, the material of portion343can directly contact a conductive material region (a portion of) line270. Portion343can be called a plug (e.g., a conductive plug) of pillar331. As described in more detail below, including portion343and circuit285_1(which includes transistors286) may improve operations (e.g., erase operation) of memory device200over some conventional memory devices.

Portion346(conductive portion) of pillar331(FIG. 3) can be coupled (e.g., directly coupled) to line299. For example, the material of portion346can directly contact a conductive material region (a portion of) of line299.

Portion344of pillar331has length extending in the direction (in the z-dimension) of the length of pillar331and can be between (e.g., vertically between) portions343and346. Portion344and at least part of each of portions343and346can form a conductive channel (e.g., part of the body of memory cell string231) in pillar331. The conductive channel (formed at least by portion344) has length extending in the direction (in the z-dimension) of the length of pillar331and can carry current (e.g., current between line270and line299(e.g., source)) during an operation (e.g., read, write, or erase) of memory device200.

Portion345(dielectric portion) of pillar331can be surrounded (e.g., horizontally surrounded) by portions344and346. During a process of forming pillar331of memory device200, pillar331can have a hollow core (e.g., an empty core) before portion345is formed. Portion345inFIG. 3can include a dielectric material (e.g., silicon dioxide) that occupies (e.g., fills) the hollow core (as shown inFIG. 3), such that portion344can surround at least part of portion345.

Each of portions343,344, and346can include conductive material (e.g., doped polycrystalline silicon). Portions343,346, and344can include materials of the same conductivity type but different doping concentrations. For example, portions343,346, and344can include a semiconductor material of n-type (e.g., n-type polycrystalline silicon), but each of portions343and346can have a doping concentration (n-type impurities (e.g., arsenic or phosphorous)) higher than the doping concentration (n-type impurities (e.g., arsenic or phosphorous)) of portion344.

Alternatively, portions343and346can include materials of the same conductivity type, and portion344can include a material having a different conductivity type from that of portions343and346. For example, portions343and346can include a semiconductor material of n-type (e.g., n-type polycrystalline silicon), and portion344can include a semiconductor material of p-type (e.g., p-type polycrystalline silicon). Each of portions343and346can have a doping concentration (n-type impurities (e.g., arsenic or phosphorous)) higher than the doping concentration (e.g., p-type impurities (e.g., boron)) of portion344.

As shown inFIG. 3, memory device200includes an interface348in pillar331. Interface348is the location where portion343(e.g., the bottom of the material of portion343) contacts portion345(e.g., contact the top of the material of portion345).FIG. 3shows an example where interface348(e.g., the bottom of portion343) is located (e.g., positioned) at approximately level316. However, interface348can be located (e.g., positioned) at another location in pillar331(e.g., at a location between level315and317). As described below with reference toFIG. 4, the structure of memory device200can allow its operations (e.g., erase operation) to be less susceptible to process variations (process of forming memory device200), thereby suppressing the effect of process variations on operations of memory device200. This allows memory device200to maintain its operations even if the location of interface348may deviate from its intended location (e.g., due to process variations). The structure of memory device200can also allow it to generate a relatively higher amount of erase GIDL current that further helps erase operations of memory device200.

As shown inFIG. 3, memory cells210,211,212, and213of memory cell string231can be located along a segment of pillar331(e.g., the segment of pillar331extending from level310to level313). Control lines2200,2210,2220,2230(associated with respective memory cells210,211,212, and213) can also be located along a segment (e.g., the segment extending from level310to level313) of pillar331. The materials of control lines2200,2210,2220,2230can include a conductive material (e.g., conductively doped polycrystalline silicon of n-type, metals, or other conductive materials).

Transistor286associated with line (e.g., transistor gate line)280_1Acan be located in level317along a segment (segment at level317) of pillar331. Line280_1Acan also be located in level317along a segment (segment at level317) of pillar331.

Transistor286associated with line (e.g., transistor gate line)280_1Bcan be located in level316along a segment (segment at level316) of pillar331. Line280_1Bcan also be located in level316along a segment (segment at level316) of pillar331.

Select line281Acan be located in level315along a segment (segment at level315) of pillar331. Select line281ecan be located in level314along a segment (segment at level314) of pillar331.

Select line281′Bcan be located in level309along a segment (segment at level309) of pillar331. Select line281′Acan be located in level308along a segment (segment at level308) of pillar331.

Transistor288associated with line (e.g., transistor gate line)289_1Bcan be located in level307along a segment (segment at level307) of pillar331. Line289_1Bcan also be located in level307along a segment (segment at level307) of pillar331.

The materials of lines280_1A,280_1B, and289_1Band select lines281A,281B,281′A, and281′Bcan include conductively doped polycrystalline silicon, metals, or other conductive materials. The materials of lines280_1A,280_1B, and289_1Band select lines281A,281B,281′A, and281′Bcan be the same as the conductive material of control lines2200,2210,2220,2230.

As shown inFIG. 3, memory device200can include a structure330, which includes portions301,302, and303between pillar331and control lines2200,2210,2220,2230. Each of memory cells210,211,212, and213of memory cell string231can include part of structure330(part of portions301,302, and303at respective levels310,311,312, and313). For example, part of portion302at a particular memory cell among memory cells210,211,212, and213can be a charge storage structure (e.g., a memory portion) of that particular memory cell and can be configured to store information in that particular memory cell.

Structure330can be part of a TANOS (TaN, Al2O3, Si3N4, SiO2, Si) structure. For example, portion301(e.g., interpoly dielectrics) can include a charge blocking material or materials (e.g., a dielectric material such as TaN and Al2O3) that are capable of blocking a tunneling of a charge. Portion302can include a charge storage element (e.g., charge storage material or materials, such as Si3N4or other dielectric materials) that can provide a charge storage function (e.g., trap charge) to represent a value of information stored in memory cells210,211,212, or213. Thus, in this example, the charge storage structure (part of portion302) in each of memory cells210,211,212, and213that is configured to store information is a dielectric structure, which can include a dielectric material (e.g., Si3N4). Portion303can include a tunnel dielectric material or materials (e.g., SiO2) that are capable of allowing tunneling of a charge (e.g., electrons). As an example, portion303can allow tunneling of electrons from portion344to portion302during a write operation and tunneling of electrons from portion302to portion344during an erase operation of memory device200.

In an alternative arrangement of memory device200, structure330can be part of a SONOS (Si, SiO2, Si3N4, SiO2, Si) structure. In this alternative arrangement, in each of memory cells210,211,212, and213, the memory portion (part of portion302) can be a dielectric material (e.g., Si3N4) portion.

In another alternative arrangement of memory device200, structure330can be part of a floating gate structure. In this alternative arrangement, the charge storage structure (part of portion302) in each of memory cells210,211,212, and213that is configured to store information can be a polycrystalline silicon structure.

As shown inFIG. 3, a select line (e.g.,281A,281B,281′A, or281′B) is a piece (e.g., a single layer) of conductive material (e.g., polycrystalline silicon, metal, or other conductive materials). As described above, a select line can carry a signal (e.g., signal SGDA, SGDB, SGSA, or SGSBinFIG. 2C) but it does not operate like a switch (e.g., a transistor). A select gate (e.g., each of select gates261,262,263, and264) can include a portion of a respective select line (e.g., a portion of the piece of the conductive material that forms the respective select line) and additional structures to perform a function (e.g., function of a transistor). For example, inFIG. 3, select gate261can include a portion of select line281Aand a portion of structure330, select gate262can include a portion of select line281Band a portion of structure330, select gate263can include a portion of select line281′Aand a portion of structure330, and select gate264can include a portion of select line281′Band portion of structure330.

Similarly, as shown inFIG. 3, a transistor gate line (e.g.,280_1A,280_1, or289_1B) is a piece (e.g., a single layer) of conductive material (e.g., polycrystalline silicon, metal, or other conductive materials). A transistor gate line can carry a signal (e.g., signal GGA, GGB, or GG′BinFIG. 2C) but a transistor gate line does not operate like a switch (e.g., a transistor). A transistor (e.g., each of transistors286and288) associated with a transistor gate line (e.g.,280_1A,280_1B, or289_1B) can include a portion of a respective transistor gate line (e.g., a portion of the piece of the conductive material that forms the respective transistor gate line) and additional structures to perform a function of a transistor. For example, inFIG. 3, transistors286can include respective portions of lines280_1Aand280_1Band respective portions of structure330, and transistor288can include a portion of line289_1Band a portion of structure330.

FIG. 3shows an example where transistors286and288and select gates261,262,263, and264have the same structure (e.g., TANOS structure) as memory cells210,211,212, and213. Alternatively, some or all of transistors286and288and select gates261,262,263, and264can have a different structure, such as an FET structure. An example of an FET includes a metal-oxide semiconductor (MOS) transistor structure. As is known to those skilled in the art, an FET usually includes a transistor gate, a transistor body channel, and a gate oxide between the transistor gate and the transistor body channel that can be in direct contact with the transistor gate and the transistor body channel.

As shown inFIG. 3, two adjacent control lines (two control lines located immediately vertically next to each other in the direction of the z-dimension) among control lines2200,2210,2220, and2230are vertically separated from each other by a distance (e.g., spacing) D1. Select lines281Aand281Bare vertically separated from each other by a distance (e.g., spacing) D2. Select lines281′Aand281′Bare vertically separated from each other by a distance (e.g., spacing) D2′. Distances D2and D2′ can be the same (e.g., substantially equal). Each of distances D2and D2′ can be the same as distance D1.

Lines280_1Aand280_1Bare vertically separated from each other by a distance (e.g., spacing) D3. Line280_1Bcan be vertically separated from select line281Aby a distance (e.g., spacing) D4. Line289_1Bcan be vertically separated from select line281′Aby a distance (e.g., spacing) D4′. Each of distances D3, D4, and D4′ can be the same as distance D1. Thus, as described above, distances (e.g., vertical distances) D1, D2, D2′, D3, D4, and D4′ can be the same.

As shown inFIG. 3, distance D1is a vertical distance (e.g., vertical spacing) measured from the nearest top or bottom edge (surfaces directly facing each other with respect to the z-dimension) of any of two vertically adjacent control lines. As described above, each of control lines2200,2210,2220, and2230can be formed from a conductive material (e.g., metal or another conductive material). Thus, distance D1can be measured between two nearest edges of the materials that form two adjacent control lines. For example, distance D1can be measured from the nearest edges of the materials that form control lines2200and2210, the nearest edges of the materials that form control lines2210and2220, or the nearest edges of the materials that form control lines2220and2230.

Distance D2is a vertical distance (e.g., vertical spacing) measured from the nearest top or bottom edge (surfaces directly facing each other with respect to the z-dimension) of select lines281Aand281B. As described above, select lines281Aand281Bcan be formed from a conductive material (e.g., metal or another conductive material). Thus, distance D2can be measured between two nearest edges of the materials that form select lines281Aand281B.

Distance D2′ is a vertical distance (e.g., vertical spacing) measured from the nearest top or bottom edge (edges with respected to the z-dimension sides directly facing each other with respect to the z-dimension) of select lines281′Aand281′B. As described above, select lines281′Aand281′Bcan be formed from a conductive material (e.g., metal or another conductive material). Thus, distance D2′ can be measured between two nearest edges of the materials that form select lines281′Aand281′B.

FIG. 3also shows distance D1′ and D1″ between elements in memory device200. Distance D1′ is a vertical distance (e.g., vertical spacing) between the select line (e.g., select line281Bin this example) that is nearest to control lines2200,2210,2220, and2230, and the control line (e.g.,2230) that is nearest to select lines281Aand281B(nearest to select line281Bin this example). Thus, distance D1′ can be measured between two nearest edges of the materials that form select line281Band control line2230. Distance D1″ is a vertical distance (e.g., vertical spacing) between the select line (e.g., select line281′Bin this example) that is nearest to control lines2200,2210,2220, and2230and the control line (e.g.,2200) that is nearest to select lines281′A, and281′B(nearest to select line281′Bin this example). Thus, distance D1″ can be measured between two nearest edges of the materials that form select line281′Band control line2200.

Distance D3is a vertical distance (e.g., vertical spacing) measured from the nearest top or bottom edge (surfaces directly facing each other with respect to the z-dimension) of lines280_1Aand280_1B. As described above, select lines280_1Aand280_1Bcan be formed from a conductive material (e.g., metal or another conductive material). Thus, distance D3can be measured between two nearest edges of the materials that form lines280_1Aand280_1B.

Distance D4is a vertical distance (e.g., vertical spacing) measured from the nearest top or bottom edge (surfaces directly facing each other with respect to the z-dimension) of lines281Aand280_1B. Thus, distance D4can be measured between two nearest edges of the materials that form lines281Aand280_1B.

Distance D4′ is a vertical distance (e.g., vertical spacing) measured from the nearest top or bottom edge (surfaces directly facing each other with respect to the z-dimension) of lines281′Aand289_1B. Thus, distance D4′ can be measured between two nearest edges of the materials that form lines281′Aand289_1B.

As shown inFIG. 3, control lines2200,2210,2220, and2230, select lines281A,281B,281′A, and281′B, and lines280_1A,280_1B, and289_1are separated from portion344(e.g., a conductive channel) of pillar331by the same distance Dx (e.g., a horizontal distance with respect to the x-dimension). Distance Dx can be the thickness of structure330with respect to the x-dimension.

As shown inFIG. 3, each of control lines2200,2210,2220, and2230has a thickness T1in the z-dimension. Thickness T1is a vertical thickness of the material of a respective control line among control lines2200,2210,2220, and2230. Each of select lines281Aand281Bhas a thickness T2in the z-dimension. Thickness T2is a vertical thickness of the material of each of select lines281Aand281B. Each of select lines281′Aand281′Bhas a thickness T2′ in the z-dimension. Thickness T2′ is a vertical thickness of the material of each of select lines281′Aand281′B.

Each of lines280_1Aand280_1Bhas a thickness T3in the z-dimension. Thickness T3is a vertical thickness of the material of each of lines280_1Aand280_1B. Line289_1Bhas a thickness T3′ in the z-dimension. Thickness T3′ is a vertical thickness of the material of each of line289_1B.

Thicknesses T1, T2, T2′, T3, and T3′ can be the same (e.g., substantially equal). Alternatively, thicknesses T2and T2′ can be the same (e.g., substantially equal), thicknesses T3and T3′ can be the same (e.g., substantially equal), and each of thicknesses T2, T2′, T3, and T3′ can be different from thickness T1.

As shown inFIG. 3, memory device200can include a dielectric (e.g., an oxide of silicon)355located between elements of memory device200. For example, dielectric355can be located (e.g., occupy the space) between two adjacent control lines among control lines2200,2210,2220, and2230. Thus, distance D1can be the thickness of the material (e.g., an oxide of silicon) of a respective dielectric (e.g., dielectric355) between two adjacent control lines among control lines2200,2210,2220, and2230. Similarly, each of distances D1′, D1″, D2, D2′, D3, D4, and D4′ can be the thickness of the material of a respective dielectric (e.g., dielectric355) between two adjacent elements as shown inFIG. 3.

Providing the structure of memory device200(e.g., transistor gate lines280_1A,280_1B, and289_1Band associated transistors286and288) as shown inFIG. 3and operating it in ways as described above (e.g.,FIG. 2D) allows memory device200to improve its operations. For example, GIDL current generated during an erase operation of memory device200may be improved (e.g., increased) with the inclusion of line280_1Aand transistors286in memory device200in comparison with memory device200without the inclusion of line280_1Aand transistors286.

Further, by making thicknesses T1, T2, T2′, T3, and T3′ of the components (shown inFIG. 3) of memory device200the same, a simplified process of making memory device200can be achieved. For example, memory device200can be formed (e.g., fabricated) to provide improved GIDL current for its erase operations without modifying the thickness (e.g., T3or T3′) of one or more of lines280_1A,280_1B, and289_1B(e.g., transistor gate lines inFIG. 3) to be different from (e.g., greater than) the thickness (e.g., T1) of control lines2200,2210,2220, and2230. In an alternative structure of memory device200, the thickness of one or more of lines280_1A,280_1B, and289_1Bcan be made greater than the thickness of control lines2200,2210,2220, and2230. However, such an alternative structure may cause forming memory device200to be more complicated than forming the structure of memory device200ofFIG. 3(where thicknesses T1, T2, T2′, T3, and T3′ are the same).

Moreover, as is known to those skilled in the art, process variations can affect (e.g., degrade) the operations of a memory device. However, the structure of memory device200(FIG. 3) can allow its operations (e.g., erase operation) to be less susceptible to process variations (process of forming memory device200). This means that memory device200can have a relatively higher tolerance for process variations in comparison with memory device200without some of its components (e.g., without the inclusion of line280_1Aand transistors286associated with line280_1A). Additionally, the inclusion of line280_1Aand transistors286associated with line280_1Aallows operations (e.g., erase operations) of memory device200to be less susceptible to variations in doping concentration of dopants (e.g., n-type impurities) used to form portion343, portion346, or both.

FIG. 4is a graph showing an example relationship between the location (e.g., position) of interface348and erase GIDL current generated during an erase operation and of memory device200ofFIG. 3, according to some embodiments described herein. The following description refers toFIG. 3andFIG. 4. InFIG. 4, a reference location LREFcan represent an intended (e.g., desired) location for interface348in memory device200at which erase GIDL current is expected (e.g., based on design simulation) to be at an intended amount (e.g., a desired amount) for an erase operation of memory device200. As an example, reference location LREFof interface348can be the location in pillar331at level316as shown inFIG. 3.

InFIG. 4, the arrow showing a direction “away from line270” indicates that the location of interface348in memory device200may deviate (e.g., due to process variations) from reference location LREF(e.g., an intended location) in a direction away from line270. This means that the length of portion343in the z-dimension (after memory device200is formed) would be greater than the intended length of portion343if interface348moves (e.g., shifts) from reference location LREFin a direction way from line270. The length of portion343can be the length of a conductive plug (e.g., an n-type material) that forms portion343. The intended length of portion343can be measured from line270to the location of interface348at reference location LREF(e.g., an intended location).

InFIG. 4, the arrow showing a direction “toward line270” indicates that the location of interface348in memory device200may deviate (e.g., due to process variations) from reference location LREF(e.g., an intended location) in a direction toward line270. This means that the length of portion343in the z-dimension (after memory device200is formed) would be less than the intended length of portion343if interface348moves (e.g., shifts) from reference location LREFin a direction toward line270.

InFIG. 4, curves401and402represent two example situations showing the effect of deviation (e.g., due to process variations) in the location of interface348on the amount of erase GIDL current in memory device200. Curve401shows a situation where line280_1Aand transistor286(FIG. 3) are removed from memory device200(e.g., memory device200without line280_1Aand transistor286). Curve402shows a situation where line280_1Aand transistor286are included in memory device200as shown inFIG. 2AthroughFIG. 3.

As shown by curve401(without line280_1Aand transistor286in memory device200), the amount of erase GIDL current is lower if the location of interface348varies and moves from reference location LREFtoward line270(moves closer to line270). A lower amount of erase GIDL may degrade the erase operations of memory device200.

In contrast, as shown by curve402(with line280_1Aand transistor286in memory device200), the amount of erase GIDL current can remain relatively unchanged (e.g., remain stable) if the location of interface348varies and moves from reference location LREFin a direction either away from (farther from) line270or toward (closer to) line270. Further, curve402also shows a higher amount of erase GIDL current than curve401, meaning that that memory device200having line280_1Aand transistor286can generate more erase GIDL current than memory device200without line280_1Aand transistor286.

In sum, with the inclusion of line280_1Aand transistors286in memory device200, a relatively higher amount of erase current can be generated in memory device200in comparison with a situation where line280_1Aand transistors286are not included in memory device200. Thus, the inclusion of line280_1Aand transistors286in memory device200can improve the erase operations of memory device200. Moreover, since the inclusion of line280_1Aand transistors286in memory device200allows the amount of erase GIDL current to remain relatively unchanged in memory device200, the operations (e.g., erase operations) of memory device200can be less susceptible to variations in the location of interface348. This can improve the reliability of memory device200.

FIG. 5Ashows a block diagram of a portion of a memory device500, which can be a variation of memory device200ofFIG. 2A, according to some embodiments described herein. Memory device500includes elements similar to or identical to those of memory device200. For simplicity, the description of similar or identical elements between memory device500(FIG. 5AthroughFIG. 6) and memory device200(FIG. 2AthroughFIG. 3) is not repeated.

Differences between memory devices200and500include differences between transistor gate lines coupled to circuits (e.g., top GIDL current generator circuits)285_1,285_2,285_3, and285_4and circuits (e.g., to bottom GIDL current generator circuits)287_1,287_2,287_3, and287_4of devices200and500. As shown inFIG. 5A, memory device500lacks lines (e.g., transistor gate lines)280_1A,280_2A,280_3A, and280_4Aand associated transistors286. However, memory device500includes the addition of lines (e.g., transistor gate lines)289_1Aand289_3Aassociated transistors288.

FIG. 5Bshows schematic diagram of memory device500ofFIG. 5A, according to some embodiments described herein. Memory device500includes elements similar to or identical to those of memory device200ofFIG. 2B. As shown inFIG. 5B, each of circuits (top GILD current generator circuits)285_1,285_2,285_3, and285_4can include one of transistors286. For simplicity, fewer than all of circuits285_1,285_2,285_3,285_4are labeled inFIG. 5B. Each of circuits (bottom GILD current generator circuits)287_1,287_2,287_3, and287_4can include two of transistors288. For simplicity, fewer than all of circuits287_1,287_2,287_3, and287_4are labeled inFIG. 5B. Lines289_1Aand289_3Acan be coupled to the gates of respective transistors among transistors288.

FIG. 5Cshows a schematic diagram of a portion of memory device500ofFIG. 5Bincluding line270, circuits285_1,285_2,285_3,285_4, select circuits241,242,247, and248, memory cell strings231,232,237, and238, select circuits241′,242′,247′, and248′, circuits287_1,287_2,287_3, and287_4, and line299, according to some embodiments described herein. As shown inFIG. 5C, select gates263and264of each of select circuits241′,242′,247′, and248′ can be coupled in series with two transistors among transistors288between line299and a respective memory cell string among memory cell strings231,232,237, and238.

FIG. 5Dshows example waveforms of signals BL0, BL1, BL2, GGB, SGDA, SGDB, SGSA, SGSB, GG′A, and GG′B, and SRC of memory device500(FIG. 5AthroughFIG. 5C) during example erase, write, and read operations, according to some embodiments described herein.FIG. 5Domits other signals of memory device500(e.g., signals shown inFIG. 5C) to help focus on the embodiments of the memory device described herein. During erase, write, and read operations, the omitted signals can be provided with voltages having values known to those skilled in the art.

The waveforms ofFIG. 5Dare similar to the waveforms ofFIG. 2Dexcept for the omission of signal GGAand for addition of signal GG′A. As shown inFIG. 5D, the waveforms of signal GG′Acan be the same as the waveforms of signal GGA(FIG. 2D). During the erase operation of memory device500, transistors286and288in respective circuits285_1,285_2,285_3,285_4,287_1,287_2,287_3, and287_4can operate to generate GIDL current to help the erase operation. For example, the GIDL current generated by transistors286and288during the erase operation may speed up the charging of the body of the memory cell strings in the selected block in preparation for information in memory cells of the memory cell strings of the selected block to be erased.

FIG. 6shows a side view of a structure of a portion of memory device500, according to some embodiments described herein. The structure of memory device500inFIG. 6corresponds to part of the schematic diagram of memory device500shown inFIG. 5C. The portion of memory device500shown inFIG. 6includes elements similar to or identical to those of memory device200ofFIG. 3. Differences between memory device200(FIG. 3) and memory device500(FIG. 6) include the omission of line280_1Aand an associated transistor286in circuit285_1Aand the addition of line289_1Aand an associated transistor288in circuit287_1. As shown inFIG. 6, transistor288associated with line (e.g., transistor gate line)289_1Acan be located in level606along a segment (segment at level606) of pillar331. Line289_1Acan also be located in level606along a segment (segment at level606) of pillar331.

As shown inFIG. 6, memory device500includes an interface648in pillar331. Interface648is the location where portion346(e.g., the material of portion346(e.g., an n-type doped region that forms portion346)) contacts portion344(e.g., contacts the material of portion344).FIG. 6shows an example where interface648is located (e.g., positioned) at approximately level606. However, interface648can be located (e.g., positioned) at another location in pillar331(e.g., at a location between levels307and606). As described below with reference toFIG. 7, the structure of memory device500can allow its operations (e.g., erase operation) it to be less susceptible to process variations (process of forming memory device500). This allows memory device500to maintain its operations even if the location of interface648may deviate from its intended location (e.g., due to process variations).

FIG. 7is a graph showing an example relationship between the location (e.g., position) of interface648and erase GIDL current generated during an erase operation of memory device500ofFIG. 6, according to some embodiments described herein. The following description refers toFIG. 6andFIG. 7. InFIG. 7, a reference location LREFcan represent an intended (e.g., desired) location for interface648at which erase GIDL current is expected (e.g., based on design simulation) to be at an intended amount (e.g., a desired amount) for an erase operation of memory device500. As an example, reference location LREFof interface648can be the location in pillar331at level606as shown inFIG. 6.

InFIG. 7, the arrow showing a direction “away from line299” indicates that the location of interface648in memory device500may deviate (e.g., due to process variations) from reference location LREF(e.g., an intended location) in a direction away from line299. This means that the length of portion346in the z-dimension (after memory device500is formed) would be greater than the intended length of portion346if interface648moves (e.g., shifts) from reference location LREFin a direction way from line299. The length of portion346can be the length of a diffusion region (e.g., an n-type doped region) that forms portion346. The intended length of portion346can be measured from line299to the location of interface648at reference location LREF(e.g., an intended location).

InFIG. 7, the arrow showing a direction “toward line299” indicates that the location of interface648in memory device500may deviate (e.g., due to process variations) from reference location LREF(e.g., an intended location) in a direction toward line299. This means that the length of portion346in the z-dimension (after memory device200is formed) would be less than the intended length of portion346if interface648moves (e.g., shifts) from reference location LREFin a direction toward line299.

InFIG. 7, curves701and702represent two example situations showing the effect of deviation (e.g., due to process variations) in the location of interface648on the amount of erase GIDL current in memory device500. Curve701shows a situation where line289_1Aand transistor288(FIG. 6) are removed from memory device500(e.g., memory device500without line289_1Aand transistor288). Curve702shows a situation where line289_1Aand transistor288are included in memory device500as shown inFIG. 5AthroughFIG. 6.

As shown by curve701(without line289_1Aand transistor288in memory device500), the amount of erase GIDL current is lower if the location of interface648varies and moves from reference location LREFtoward line299(moves closer to line299). A lower amount of erase GIDL may degrade the erase operations of memory device500.

In contrast, as shown by curve702(with line289_1Aand transistor288in memory device500), the amount of erase GIDL current can remain relatively unchanged (e.g., remain stable) if the location of interface648varies and moves from reference location LREFin a direction either away from (farther from) line299or toward (closer to) line299.

In sum, the inclusion of line289_1Aand transistor288in memory device500allows the amount of erase GIDL current to remain relatively unchanged in memory device500. Thus, the operations (e.g., erase operations) of memory device500can be less susceptible to variations in the location of interface648. This can improve the reliability of memory device500.

FIG. 8Ashows a block diagram of a portion of a memory device800, which can be a variation of memory device200ofFIG. 2Aand memory device500ofFIG. 5A, according to some embodiments described herein. Memory device800includes elements similar to or identical to those of memory devices200and500. For simplicity, the description of similar or identical elements between memory devices800and memory devices200and500is not repeated.

Memory device800can include a combination of memory devices200and500. For example, circuits (e.g., top GIDL current generator circuits)285_1,285_2,285_3, and285_4of memory device800can be the same as those of memory device200(FIG. 2A), and circuits (e.g., bottom GIDL current generator circuits)287_1,287_2,287_3, and287_4of memory device800can be the same as those of memory device500(FIG. 5A).

FIG. 8Bshows a schematic diagram of memory device800ofFIG. 8A, according to some embodiments described herein. Memory device800includes elements similar to or identical to those of memory device200ofFIG. 2Band memory device500ofFIG. 5B. As shown inFIG. 8B, each of circuits285_1,285_2,285_3, and285_4can include two of transistors286(which are the same as those of memory device200ofFIG. 2B), and each of circuits287_1,287_2,287_3, and287_4can include two of transistors288(which are the same as those of memory device500ofFIG. 5B).

FIG. 8Cshows a schematic diagram of a portion of memory device800ofFIG. 8Bincluding line270, circuits285_1,285_2,285_3,285_4, select circuits241,242,247, and248, memory cell strings231,232,237, and238, select circuits241′,242′,247′, and248′, circuits287_1,287_2,287_3, and287_4, and line299, according to some embodiments described herein.

FIG. 8Dshows example waveforms of signals BL0, BL1, BL2, GGA, GGB, SGDA, SGDB, SGSA, SGSB, GG′A, GG′B, and SRC of memory device800(FIG. 8AthroughFIG. 8C) during example erase, write, and read operations, according to some embodiments described herein.FIG. 8Domits other signals of memory device800(e.g., signals shown inFIG. 8C) to help focus on the embodiments of the memory device described herein. During erase, write, and read operations, the omitted signals can be provided with voltages having values known to those skilled in the art. The waveforms ofFIG. 8Dare the same as the waveforms of portions ofFIG. 2DandFIG. 5D. For example, the waveforms of signals GGAand GGBinFIG. 8Dare the same as the waveforms of signals GGAand GGBofFIG. 2D. The waveforms of signals GG′Aand GG′BinFIG. 8Dare the same as the waveforms of signals GG′Aand GG′BofFIG. 5D.

FIG. 9shows a side view of a structure of a portion of memory device800, according to some embodiments described herein. The structure of memory device800inFIG. 9corresponds to part of the schematic diagram of memory device800shown inFIG. 8C. The portion of memory device800shown inFIG. 9includes elements similar to or identical to those of memory device200ofFIG. 3and memory device500ofFIG. 6. For example, as shown inFIG. 9, lines280_1Aand280_1Band transistors286are the same as lines2801A and280_1Band transistors286ofFIG. 3, and lines289_1Aand289_1Band transistors288inFIG. 9are the same as lines289_1Aand289_1Band transistors288ofFIG. 6. Memory device800(FIG. 8AthroughFIG. 9) can have improvements similar to those of memory devices200and500described above with reference toFIG. 2AthoughFIG. 7.

FIG. 10,FIG. 11, andFIG. 12show sequential stages in example processes of forming a memory device1000, according to some embodiments described herein. The processes described with reference toFIG. 10throughFIG. 12can be used to form memory device200(FIG. 3), memory device500(FIG. 6), and memory device800(FIG. 9) described above with reference toFIG. 1throughFIG. 9. Some of the processes of forming memory device1000and some of the elements of memory device1000may be readily known to those skilled in the art. Thus, to help focus on the embodiments described herein, some of the processes of forming memory device1000shownFIG. 10throughFIG. 12and additional processes to complete memory device1000are omitted. Further, for simplicity, similar or identical elements among the memory devices inFIG. 2AthroughFIG. 12are given the same labels.

FIG. 10shows memory device1000after materials355′ and1002are formed over line (e.g., source)299and substrate390. Forming materials355′ and1002can include depositing alternating dielectric materials (e.g., alternating layers of materials355′ and layers of materials1002) over line299and substrate390. Materials355′ can include an oxide of silicon (e.g., silicon dioxide SiO2). Materials1002can include a combination of silicon and nitrogen (e.g., silicon nitrite SiNO4). Materials1002can be formed in each of levels606and307through317of memory device1000(e.g., each layer of materials1002can be formed in a respective level among levels606and307through317).

Materials1002can be formed to have respective thicknesses T1, T2, T2′, T3, and T3′, which can be same (e.g., substantially equal). Thicknesses T1, T2, T2′, T3, and T3′ are the same as those shown inFIG. 3,FIG. 6, andFIG. 9. InFIG. 10, a location1031(between two dashed lines) indicates a location at which portions of materials335′ and1002will be removed to form a hole in materials335′ and1002(described below).

FIG. 11shows memory device1000after some elements of memory device1000are formed. Such memory elements include a portion of pillar331, memory cell string231, control lines2200,2210,2220, and2230, lines (e.g., transistor gate lines)280_1Aand280_1B, select lines281Aand281B,281′A, and281′B, and lines (e.g., transistor gate lines)289_1Aand289_1B, structure330, and other elements (as shown inFIG. 11) that can be similar to those of memory device200(FIG. 3), memory device500(FIG. 6), and memory device800(FIG. 9).

Forming the elements of memory device1000inFIG. 11can include using a process such as a damascene process or other processes. For example, after the materials355′ and1002(FIG. 10) are formed, a hole (a vertical opening, not shown inFIG. 11) can be formed in materials355′ and1002at location1031(FIG. 10). The hole can be formed by removing (e.g., by etching) parts of materials355′ and1002at the location1031(FIG. 10) and leaving a remaining part of materials355′ (which are the materials of dielectrics355inFIG. 11where the hole was not formed) and leaving a remaining part of materials1002(not shown inFIG. 11) at respective levels606and307through317. The bottom of the hole can be at line299(e.g., at a top surface of line299). After the hole is formed, as shown inFIG. 11, memory cell string231(including structure330) can be formed at the location of the hole. Other structures (e.g., portions344,345,346, and parts of portions343of pillar331) of memory device1000can also be formed at the location of the hole.

After the portions of pillar331and structure330are formed, the remaining part of materials1002(where the hole was not formed) can be removed (e.g., by etching). Removing materials1002can include forming slits (e.g., not shown inFIG. 11) in the remaining part of materials355′ and in the remaining part of materials1002. Such slits (e.g., vertical openings) can be part of a damascene process used to form memory device1000. After the slits are formed, material1002can be subsequently etched away through the slits, thereby leaving vacancies (e.g., spaces) at the locations on each of levels606and307through317where materials1002were (before their removal). Since the thicknesses of materials1002(FIG. 10) can be the same (as discussed above), the spaces where materials1002were removed can also have the same thickness (e.g., same vertical distance).

After the removal of materials1002, conductive material (e.g., metal such as tungsten or other conductive materials) may be formed (e.g., filled) in the vacancies (e.g., the spaces on each of levels606and307through317) where materials1002were removed. As shown inFIG. 11, the conductive materials on levels606and307through317form the respective lines (e.g., transistor gate lines)280_1Aand280_1B, select lines281Aand281B, control lines2200,2210,2220, and2230, select lines281′Aand281′B, and lines (e.g., transistor gate lines)289_1Aand289_1Bof memory device1000.

Thus, as described above, lines280_1Aand280_1B, select lines281Aand281B, control lines2200,2210,2220, and2230, select lines281′Aand281′B, and lines289_1Aand289_1Bof memory device1000can be formed concurrently (formed by the same process step (e.g., the same deposition step)). Further, lines280_1Aand280_1B, select lines281Aand281B, control lines2200,2210,2220, and2230, select lines281′Aand281′B, and lines289_1Aand289_1Bcan also be formed from the same conductive material (e.g., metal or other conductive materials).

FIG. 12shows memory device1000after other elements of memory device1000are formed. Such elements include additional conductive materials at portions343to complete pillar331, and other portions (e.g., line270) of memory device1000.

As shown inFIG. 12, memory device1000can include elements that are similar to or identical to the elements of memory device800ofFIG. 9. Thus, the processes of forming a memory device1000can be used to form memory device800ofFIG. 9. One skilled in the art would readily recognize that processes similar to the processes of forming a memory device1000described above with reference toFIG. 10throughFIG. 12can also be used to form memory device200(FIG. 6) and memory device800(FIG. 9).

The illustrations of apparatuses (e.g., memory devices100,200,500,800, and1000) and methods (e.g., operating methods associated with memory devices100,200,500, and800, and methods (e.g., processes) of forming these memory devices) are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all the elements and features of apparatuses that might make use of the structures described herein. An apparatus herein refers to, for example, either a device (e.g., any of memory devices100,200,500,800, and1000) or a system (e.g., a computer, a cellular phone, or other electronic system) that includes a device such as any of memory devices100,200,500,800, and1000.

Any of the components described above with reference toFIG. 1throughFIG. 12can be implemented in a number of ways, including simulation via software. Thus, apparatuses (e.g., memory devices100,200,500,800, and1000or part of each of these memory devices, including a control unit in these memory devices, such as control unit116(FIG. 1)) described above, may all be characterized as “modules” (or “module”) herein. Such modules may include hardware circuitry, single and/or multi-processor circuits, memory circuits, software program modules and objects and/or firmware, and combinations thereof, as desired and/or as appropriate for particular implementations of various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and ranges simulation package, a capacitance-inductance simulation package, a power/heat dissipation simulation package, a signal transmission-reception simulation package, and/or a combination of software and hardware used to operate or simulate the operation of various potential embodiments.

Memory devices100,200,500,800, and1000may be included in apparatuses (e.g., electronic circuitry) such as high-speed computers, communication and signal processing circuitry, single or multi-processor modules, single or multiple embedded processors, multicore processors, message information switches, and application-specific modules including multilayer, multichip modules. Such apparatuses may further be included as subcomponents within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.

The embodiments described above with reference toFIG. 1throughFIG. 12include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor. Other embodiments including additional apparatuses and methods are described.

The above description and the drawings illustrate some embodiments of the invention to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description.