Boost charge recycle for low-power memory

A negative bit line boost circuit for a memory is configured to control a write multiplexer and a write assist transistor so that charge from a boost capacitor positively charges a bit line following a write assist period.

TECHNICAL FIELD

This application relates to memories, and more particularly to a memory having a negative bit line write assist with boost charge recycling.

BACKGROUND

A static random access memory (SRAM) bitcell includes a pair of cross-coupled inverters. Depending upon the binary state of a stored data bit, a p-type metal oxide semiconductor (PMOS) transistor in one of the inverters may charge a true (Q) data node. Similarly, a PMOS transistor in a remaining one of the cross-coupled inverters may charge a complement (QB) data node depending the binary state of the stored data bit. The Q data node couples through a first n-type metal oxide semiconductor (NMOS) access transistor to a bit line whereas the QB data node couples through a second NMOS access transistor to a complement bit line. During a write operation in which the binary content of the bitcell is changed, one of the PMOS transistors will initially be on and charging its data node while the corresponding access transistor is attempting to discharge the same data node through the corresponding grounded bit or complement bit line. The NMOS access transistor must thus be relatively strong with regard to the PMOS transistor so that the data node can be discharged relatively quickly. To provide this strength, the NMOS access transistors may be relatively large as compared to the inverter PMOS transistors. But increasing the size of the NMOS access transistors reduces density for the resulting SRAM.

To strengthen the NMOS access transistor without such a loss in density, it is thus conventional to provide a negative boost voltage on the otherwise-grounded bit line during the write operation. This negative boost voltage applied during a write assist period increases the strength of the NMOS access transistor in comparison to the inverter PMOS transistor so that the NMOS access transistor can quickly discharge the corresponding data node yet each NMOS access transistor may remain relatively small to enhance density. The negative boost voltage is applied during the write assist period by coupling the appropriate bit line to a charged boost capacitor. But the charge on the boost capacitor is partially discharged to ground at the termination of the write assist period.

This discharge of the boost capacitor charge may be better appreciated with regard to a conventional memory100shown inFIG. 1. For illustration clarity, only a single bit line105and a memory cell (bit cell)110are illustrated in memory100. Memory cell110includes a pair of cross-coupled inverters115each having a PMOS transistor (not illustrated) as discussed previously. When a voltage for a word line120is asserted high, a Q data node for memory cell110couples to bit line105through an NMOS access transistor M1. The binary state of bit line105depends upon a data signal (DATA) from a write driver (not illustrated) that drive a gate of an NMOS data transistor M5. The drain of data transistor M5couples to the bit line through a bit line multiplexer125. Using bit line multiplexer125, the write driver may write to a plurality of other bit lines (not illustrated) in addition to bit line105depending upon the binary state of a write multiplexer control signal that drives a gate of a plurality of NMOS write multiplexer transistors within write multiplexer125. For example, a write multiplexer transistor M2couples between the drain of data transistor M5and bit line105. Similarly, a write multiplexer transistor M3, a write multiplexer transistor M4, and a write multiplexer transistor M7all couple between the drain of data transistor M5and their respective bit lines (not illustrated).

The source of data transistor M5couples to ground through an NMOS write assist transistor M6. A write assist (negative bit line boost) signal that drives the gate of write assist transistor M6has a default high state that is pulsed low during the write assist period. Prior to the write assist period, write assist transistor M6will thus be on such that if the data signal is high, bit line105is discharged to ground. The default high state of the write assist signal also passes through a buffer130to charge a boost capacitor135formed by the gate capacitance of a PMOS transistor P1. The gate of transistor P1couples to the source of data transistor M5whereas its drain and source are both coupled to the output of buffer130. The drain and source of transistor P1(the anode of boost capacitor135) will thus be charged high by the buffer output signal as the gate for PMOS transistor P1is discharged to ground. This discharge of the gate for PMOS transistor P1occurs through the drain of write assist transistor M6prior to the write assist period during a write operation in which the data signal is in a binary one state. When the write assist signal goes low, the cathode of boost capacitor135(the gate of transistor P1) will thus be pulled below ground due to the gate capacitance for transistor P1. This negative boost for bit line105strengthens access transistor M1compared to the PMOS transistor charging data node Q so that the write operation speed is increased.

The falling edge of the write assist signal is delayed by buffer130so that write assist transistor M6may first be turned off to cause bit line105to float so that it may be subsequently pulled to a negative voltage by boost capacitor135during the write assist period. Prior to the end of the write assist period, write multiplexer transistor M2is switched off to isolate bit line105. Following the rising edge of the write assist signal (i.e., the termination of the write assist period), some of the charge for boost capacitor135is then discharged to ground through the switching on of write assist transistor M6. During each write operation, boost capacitor135thus discharges an appreciable amount of charge to ground.

Accordingly, there is a need in the art for memories having a negative bit line boost with reduced power consumption.

SUMMARY

A memory is provided in which a boost capacitor charges a bit line to a negative voltage during a write assist period. The assertion of a write assist signal defines the write assist period. Prior to the beginning of the write assist period, a write multiplexer transistor is switched on to couple the bit line to a data transistor having its gate driven by a data signal. The data transistor couples to ground through a write assist transistor. Prior to the write assist period, the write multiplexer transistor, the data transistor, and the write assist transistor are initially all on so that the bit line discharges to ground. The write assist transistor is then switched off responsive to the assertion of write assist signal to float the bit line so that the write assist period can begin, whereupon the bit line is given the negative voltage from the boost capacitor.

To couple the bit line to the data transistor prior to the write assist period, a memory controller asserts a write multiplexer signal. Note that as used herein, a signal is said to be “asserted” regardless of whether that assertion is active-high or active-low. The default (non-asserted) state of the write assist signal maintains the write assist transistor on outside of the write assist period. To apply the negative boost, a cathode of a boost capacitor couples to a source terminal of the data transistor. The boost capacitor cathode will thus be grounded when the bit line is grounded prior to the write assist period. An anode of the boost capacitor is positively charged responsive to the default state of the write assist signal while the boost capacitor cathode is grounded. At the assertion of the write assist signal, the write assist transistor switches off to isolate the grounded bit line. The asserted write signal is delayed through a delay circuit to produce a delayed asserted write signal that grounds the boost capacitor anode. Since the boost capacitor cathode was negatively charged with regard to the boost capacitor anode, this grounding of the boost capacitor anode negative charges the boost capacitor cathode that in turn provides a negative voltage boost to the bit line through the switched-on data transistor.

The memory controller is configured to maintain the assertion of the write multiplexer signal such that the write multiplexer signal is still asserted when the write assist signal is de-asserted at the end of the write assist period. This de-assertion of the write assist signal is delayed through the delay circuit but will cause the anode of the boost capacitor to again be positively charged. This increase of the boost capacitor anode voltage causes the boost capacitor cathode voltage to also be elevated slightly above ground. The bit line can thus be positively charged at the end of the write assist period such that the boost charge from the boost capacitor is effectively “recycled” so as to be used to positively charge the bit line. The memory thus saves charge with respect to a subsequent pre-charging of the bit line during to a subsequent write operation. To keep the write assist transistor off during this boost charge recycling, a logic circuit functions to process the write assist signal with a delayed version of the write assist signal to delay the switching on of the write assist transistor responsive to the de-assertion of the write assist signal at the conclusion of the write assist period. The write assist transistor is thus switched off at the assertion of the write assist signal but is not switched back on until a boost charge recycling period of delay has expired following the de-assertion of the write assist signal. In this fashion, the boost charge is advantageously recycled to positively charge the bit line prior to a subsequent pre-charging of the bit line.

These and other advantageous features may be better appreciated through the following detailed description.

DETAILED DESCRIPTION

A memory write assist circuit for a memory is provided that effectively recycles some of the charge from the boost capacitor that would otherwise be discharged to ground through the write assist transistor to positively charge the bit line following the write assist period. Since the charge is no longer discharged to ground, the resulting memory is advantageously low power yet also enjoys the density that negative bit line boost techniques provide with regard to maintaining the memory cell access transistors to be relatively small. Without a negative bit line boost, the access transistors would struggle to flip the memory cell contents such that memory operation speed suffers unless the access transistors were sized relatively large as compared to the PMOS transistors in the memory cells' cross-coupled inverters. But the memory write assist circuit disclosed herein enables use of relatively small access transistors yet provides low power consumption due to the prevention of the boost capacitor charge being discharged to ground through the write assist transistor following the termination of the write assist period. These advantageous properties may be better appreciated with reference to the following example embodiments.

An example memory200including a negative bit line boost circuit201is shown inFIG. 2A. As discussed with regard to memory100, memory200includes memory cell110formed through a pair of cross-coupled inverters115each having a PMOS transistor (not illustrated). Memory200is thus a static random access memory (SRAM) although it will be appreciated that other types of memories may also benefit from the negative bit line boost techniques and circuits disclosed herein. For illustration clarity, only a single bit line105and memory cell (bit cell)110are illustrated in memory200. As also discussed previously, when a voltage for word line120is asserted high during a write operation, a Q data node of memory cell110couples to bit line105through a switched-on NMOS access transistor M1. The binary state of bit line105depends upon a data signal (DATA) from a write driver (not illustrated) that drives a gate of an NMOS data transistor M5. The drain of data transistor M5couples to bit line105through bit line multiplexer125as also discussed with regard to memory100. In this fashion, the write driver may write to a plurality of other bit lines (not illustrated) in addition to bit line105depending upon the binary state of a write multiplexer signal that drives a gate of a plurality of NMOS write multiplexer transistors within write multiplexer125. For example, a write multiplexer transistor M2couples between the drain of data transistor M5and bit line105. Similarly, write multiplexer125includes a write multiplexer transistor M3, a write multiplexer transistor M4, and write multiplexer transistor M7that all couple between the drain of data transistor M5and their respective bit lines (not illustrated). Write multiplexer125is thus a 4:1 multiplexer but it will be appreciated that other ratios of column multiplexing may be in alternative embodiments.

A memory controller205within negative bit line boost circuit201controls the write multiplexer transistors such as write multiplexer transistor M2as discussed further herein. In particular, memory controller205controls the gate of write multiplexer transistor M2with the write multiplexer signal. Each write multiplexer transistor thus has its own corresponding write multiplexer signal that may be asserted by memory controller205.

As also discussed with regard to memory100, a source of data transistor M5couples to ground through a drain of NMOS write assist transistor M6. However, a logic circuit210drives the gate of write assist transistor M6responsive to the write assist signal as discussed further herein. In memory200, the write assist signal is active low such that it is asserted by being grounded. Logic circuit210responds to the falling edge of the write assist signal at the beginning of the write assist period to switch off write assist transistor M6. Since the write assist signal is active low, it will be charged high (e.g., to a power supply voltage VDD) while the write assist signal is de-asserted. Prior to the write assist period, write assist transistor M6will thus be on such that if the data signal is in a binary high state, bit line105is discharged to ground. As also discussed with regard to memory100, the default high state of the write assist signal passes through buffer130to charge a boost capacitor135formed by the gate capacitance of PMOS transistor P1. The gate of transistor P1couples to the source of data transistor M5whereas its drain and source are both coupled to the output of buffer130. The drain and source of transistor P1(the anode of boost capacitor135) will thus be charged high by the buffer output signal as the gate of transistor P1(the cathode of boost capacitor135) is discharged to ground through the drain of write assist transistor M6prior to the write assist period during a write operation in which the data signal is in a binary one state. When the write assist signal is asserted by being grounded to begin the write assist period, the cathode of boost capacitor135will thus be pulled below ground due to the gate capacitance for transistor P1. In particular, note that the anode boost capacitor135is positively charged with regard to the cathode of the boost capacitor prior to the write assist period. The gate capacitance of transistor P1thus causes the source for data transistor M5to be negatively charged. In turn, this negative charge passes through write multiplexer transistor M2to negatively charge bit line105since memory controller205is configured to maintain the assertion of the write multiplexer signal during the write assist period. This negative boost for bit line105strengthens access transistor M1compared to the PMOS transistor charging data node Q within inverter115so that the write operation speed is increased.

The falling edge of the write assist signal is delayed by buffer130so that write assist transistor M6may first be turned off to cause bit line105to float so that bit line105may be subsequently pulled negative by boost capacitor135during the write assist period. In that regard, note that logic circuit210does not delay the falling edge of the write assist signal with regard to its application to the gate of write assist transistor M6. But logic circuit210does delay the rising edge of the write assist signal with regard to switching on write assist transistor M6following the conclusion of the write assist period (the period of time during which the write assist signal is asserted). This delay by logic circuit210is quite advantageous because it maintains the isolation of bit line105from ground despite the write assist signal being de-asserted high (e.g., by being charged to the power supply voltage VDD) at the end of the write assist period. This de-assertion of the write assist signal causes the anode of boost capacitor135to be charged to the power supply voltage VDD, which in turn boosts the cathode voltage for boost capacitor135slightly above ground.

Controller205is configured to release (de-assert) the write multiplexer signal driving the gate of write multiplexer transistor M2only at the conclusion of a boost charge recycling period following the conclusion of the write assist period. The positive charge at the source of data transistor M5from the boost capacitor cathode may thus flow through data transistor M5and through write multiplexer transistor M2to charge bit line105slightly above ground during the boost charge recycling period.

There is thus no discharge to ground of charge from boost capacitor135at the conclusion of the write assist period. Instead, charge from boost capacitor135is effectively “recycled” to positively charge bit line105during the boost charge recycling period. The resulting positive charge of bit line105saves power because a pre-charge circuit (not illustrated) will pre-charge bit line105even higher in voltage during a pre-charge operation for a subsequent write operation. But the pre-charge circuit need not supply as much charge during such a pre-charge operation (as compared to charging bit line105from a grounded state) because bit line105is already slightly pre-charged due to the recycling of the boost capacitor charge.

At the conclusion of the boost charge recycling period, memory controller205releases the assertion of the write multiplexer signal so that write multiplexer transistor M2switches off to isolate bit line105from data transistor M5. Logic circuit210is configured to pass the delayed rising edge of the write assist signal to the gate of write assist transistor M6following the conclusion of the boost charge recycling period for negative bit line boost circuit201to again switch on write assist transistor M6in anticipation of another write operation.

It will be appreciated that logic circuit210has a number of alternative embodiments depending upon whether the write assist signal is active-high or active-low. For example, a NOR gate may form logic circuit210for negative bit line boost circuit201shown inFIG. 2Bin which negative bit line boost circuit201is configured to process an active-high write assist signal. NOR gate210receives the write assist signal and a delayed version of the write assist signal as produced by a delay circuit215. Since the write assist signal is active-high, it is delayed through an odd number of inverters220to form a delayed inverted version of the write assist signal for driving the anode of boost capacitor135. In this fashion, the delayed inverted version of the write assist signal will be grounded in response to the assertion of the write assist signal. Prior to the write assist period, both the delayed write assist signal and the write assist signal driving NOR gate210will be grounded to force the output of NOR gate210high to switch on write assist transistor M6. In response to the rising edge of the write assist signal, the output of NOR gate210will go low to switch off write assist transistor M6during the write assist period. Note, however, that the delayed version of the write assist signal has no effect with regard to delaying the rising edge of the write assist signal to be processed through NOR gate210and switch off write assist transistor M6. In contrast, the de-assertion of the write assist signal at the end of the write assist period does not force NOR gate210to switch on write assist transistor M6until the delayed version of the write assist signal is also de-asserted.

Referring again toFIG. 2A, it may thus be seen that logic circuit210functions to switch off write assist transistor M6in response to the assertion of the write assist signal but to switch on the write assist transistor only in response to the expiration of a delay after the de-assertion of the write assist signal. The application of the delay is selective in that it triggered only at the de-assertion of the write assist signal and not triggered by the assertion of the write assist signal. To assure that memory controller205delays the de-assertion of the write multiplexer signal until the end of the boost charge recycling period, memory controller205may respond to the grounding of the anode of boost capacitor135as shown inFIG. 2Bbefore beginning the boost charge recycling period. In particular, memory controller205may be configured to respond to a delayed version of the grounding of the boost capacitor anode to trigger the release of the write multiplexer signal. Referring again to delay circuit215, it is configured such that the delay it imparts to the write assist signal is greater than the boost charge recycling period.

In one embodiment, logic circuit210and memory controller205may be deemed to form a means for controlling write multiplexer transistor M2and write assist transistor M6so that charge from boost capacitor135following a write assist period charges bit line105to a positive voltage.

An example timing diagram for the signals in negative bit line boost circuit201is shown inFIG. 3. The write multiplexer signal Wm< > is asserted prior to the assertion of the write assist signal as is conventional for negative bit line boost operation. At the conclusion of the write assist period, the write assist signal is de-asserted at a time t0. The output of NOR gate210is denoted as a write assist (local) signal, which does not go high at time t0since a write assist (delayed) signal from delay circuit215is still high. At the expiration of the boost charge recycling period at time t1, the write multiplexer signal is released to isolate the slightly-positively-charged bit line105. The write assist (delayed) signal is then released at a time t2such that the write assist (local) signal may be driven high to again switch on write assist transistor M6.

An example method of operation for a negative bit line boost circuit as disclosed herein will now be discussed with reference to the flowchart ofFIG. 4. The method includes an act400of, responsive to an assertion of a write assist signal during a write assist period, negatively boosting a bit line using charge from a cathode of a boost capacitor while a write assist switch transistor coupled between the bit line and ground is switched off. The negative boost of bit line105during the write assist period for memory200is an example of act400. The method further includes an act405of, responsive to a de-assertion of the write assist signal at an end of the write assist period, positively charging an anode of the boost capacitor to cause the cathode of the boost capacitor to positively charge the bit line while the write assist transistor is maintained off during a boost charge recycling period. The recycling of the boost charge during the boost charge recycling period between times t0and t1as noted inFIG. 3for negative bit line boost circuit201is an example of act405. Finally, the method includes an act410of isolating the positively charged bit line at an end of the boost charge recycling period by switching off a write multiplexer transistor coupled between bit line and the write assist transistor. The switching of write multiplexer transistor M2at the termination of the boost charge recycling period is an example of act410.