Compact integration of LC resonators

A technique to provide a compact integration of inductor-capacitor resonator a capacitor having a top plate and a bottom plate embedding a dielectric layer. The top and bottom plates are substantially parallel to each other. An inductor having a first end is coupled to the capacitor at the bottom plate. The inductor has N turns surrounding the bottom plate in a spiral geometry. The inductor is co-planar to one of the top and bottom plates and ends at a second end.

BACKGROUND

1. Field of the Invention

Embodiments of the invention relate to the field of passive devices, and more specifically, to resonators.

2. Description of Related Art

In many radio frequency (RF) circuits for filtering and power supply (e.g., tank circuit) for voltage-controlled oscillator (VCO), resonators using inductors (L) and capacitors (C), referred to as LC resonators, occupy a large real estate due to relative arrangement of the capacitors and inductors.

Currently, LC resonators are designed using a side-by-side arrangement in which the capacitor is placed next to the inductor. For advanced packaging technologies having embedded passive (EP) components capability, the minimum via pad size needed to connect the underpass or the escape of the inductor is comparable to the typical plate size of a parallel-plate capacitor. When this underpass is connected to the top plate of the capacitor, an additional connecting via is needed. This additional via and the side-by-side arrangement of the capacitor and the inductor lead to an increase in size of the resonator. In addition, this design makes it difficult to control the overall inductance of the circuit.

DESCRIPTION

An embodiment of the present invention is a technique to provide a compact integration of inductor-capacitor resonator. A capacitor having a top plate and a bottom plate embedding a dielectric layer. The top and bottom plates are substantially parallel to each other. An inductor having a first end is coupled to the capacitor at the bottom plate. The inductor has N turns surrounding the bottom plate in a spiral geometry. The inductor is co-planar to one of the capacitor plates and ends at a second end.

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown to avoid obscuring the understanding of this description.

One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a program, a procedure, a method of manufacturing or fabrication, etc.

FIG. 1is a diagram illustrating a system100in which one embodiment of the invention can be practiced. The system100represents a mobile communication module. It includes a system on package (SOP)110, an intermediate frequency (IF) processing unit160, and a base-band processing unit165.

The SOP110represents the front end processing unit for the mobile communication module. It is a transceiver incorporating on-package integrated lumped passive components as well as RF components. It includes an antenna115, a duplexer120, a filter125, a system-on-chip (SOC)150, a power amplifier (PA)180, and a filter185.

The antenna115receives and transmits RF signals. It is designed in compact micro-strip and strip-line for L and C-band wireless applications. The duplexer120acts as a switch to couple to the antenna115to the receiver and the transmitter to the antenna115. The filters125and185are C-band LTCC-strip-line filter or multilayer organic lumped-element filter at 5.2 GHz and narrowband performance of 200 MHz suitable for the Institute of Electrical and Electronic Engineers (IEEE) 802.11 wireless local area network (WLAN). The SOC150includes a low noise amplifier (LNA)130, a down converter135, a local voltage controlled oscillator (VCO)140, an up converter170, and a driver amplifier175. The LNA130amplifies the received signal. The down converter135is a mixer to convert the RF signal to the IF band to be processed by the IF processing unit160. The up converter170is a mixer to convert the IF signal to the proper RF signal for transmission. The VCO140generates modulation signal at appropriate frequencies for down conversion and up conversion. The driver amplifier175drives the PA180. The PA180amplifies the transmit signal for transmission.

The IF processing unit160includes analog components to process IF signals for receiving and transmission. It may include a band-pass filter and a low pass filter at suitable frequency bands. The base-band processing unit165may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to convert analog signal to digital data and vice versa. It may include a digital processor with memory and peripheral components to process digital data.

The SOP110may be a multi-layer three-dimensional (3D) architecture for a monolithic microwave integrated circuit (MMIC) with EP technology. It may be implemented using Low Temperature Co-fired Ceramics (LTCC) and organic-based technologies. The 3D architecture may include multiple layers include a layer10to implement the antenna115, layers20,22, and24for the filters125and185, and layer30for the SOC150and the passive components using EP technology. In particular, layers20,22, and24may contain a LC resonator21that may be used as part of the filters125and185, or the VCO140, or any other RF circuits. The monolithic microwave integrated circuit (MMIC) and embedded passive components may include layer30.

The LC resonator21may be used in any applications that require a compact integration of inductors and capacitors. It may be used in RF filter circuits, VCO, etc. Typically, the packaging technology involves embedded passives with multiple layers. It may also be used with any other packaging technologies such as Flip-Chip Ball Grid Array (FCBGA). The LC resonator21may be designed as a series resonator or a parallel resonator. It may operate in RF frequency up to several GHz. For example, the resonance frequency may be at 3.8 GHz.

FIG. 2Ais a diagram illustrating a series resonator circuit21according to one embodiment of the invention. The circuit21may include a capacitor (C)210and an inductor (L)220.

The capacitor210and the inductor220are electrically connected in series. One plate of the capacitor210is connected to a first feed line230. One end of the inductor is connected to a second feed line240or is available as a contact point. The first and second feed lines230and240are used for connections to other components or parts in the package.

FIG. 2Bis a diagram illustrating a series resonator21according to one embodiment of the invention. The series resonator21is shown in three-dimensional (3-D) view. It includes a capacitor210and an inductor220.

The capacitor210includes a top plate250and a bottom plate260. These two plates are typical metal and serve as two electrodes for the capacitor. The top and bottom plates250and260embed a dielectric layer270. The dielectric layer may be made of materials having a high dielectric constant (high-k). The dielectric constant, the thickness of the dielectric material, and the dimensions of the top and bottom plates250and260may be selected to provide appropriate capacitance values according to the application. The capacitance may be a function of the area of the top and bottom plates250and260. For example, the capacitance values may be in the range of between 0.5 pF/mm2to 80 pF/mm2for RF circuits and even higher for non-RF applications such as power delivery.

The inductor220may include a metal trace having two ends: a first end and a second end. The first end may be connected to the capacitor210at the bottom plate260. Typically, the inductor220is substantially planar or co-planar to one of the top and bottom plates260. In other words, it may be in the same plane or approximately in the same plane with the bottom plate260. The inductor220may have a spiral geometry and may have N turns where N may be any real number. In one embodiment, N may range from ½ to 10. The spiral geometry of the inductor220may start from the first end, then surround the bottom plate260and then end at the second end. In essence, the capacitor210is placed inside the inductor220. The inductance of the inductor220may be any appropriate values. It may be in the range of 200 pH to 20 nH for RF applications. The inductor220may be embedded into a multi-layer build-up structure as single or multi-layer traces. The spiral geometry may be rectangle, square, or circular. Similarly, the capacitor plates may have a rectangular, circular, or any other polygonal shape. When multiple LC resonators are used, the inductors may form in an L-shape spiral geometry. The spiral inductor resonator segments may be separate, partially overlap, or fully overlap.

To provide connections or contact points to other components or devices, two feed lines or feeds may be used. The first feed230may be connected to the top plate250. The second feed240may be connected to the second end of the inductor220.

By placing the capacitor210within the inductor220, substantial area saving may be achieved. Compared to the side-by-side arrangement, this layout may achieve about 50% area reduction. In addition, it does not require vias as in the side-by-side arrangement, unless there is a requirement for a routing layer. This layout also reduces parasitic resistance or inductance due to the flexibility to connect the feed lines from any side (or location) of the capacitor plates interconnects.

FIG. 2Cis a diagram illustrating a top view of the series resonator21shown inFIG. 2Baccording to one embodiment of the invention. The top view shows the capacitor210, the inductor220, the first feed line230, and the second feed line240. Typically, the top plate250and the bottom plate260are of different sizes. In one embodiment, the bottom plate260is larger than the top plate250.

FIG. 2Dis a diagram illustrating a side view of the series resonator21shown inFIG. 2Baccording to one embodiment of the invention. The side view shows the dielectric layer270being embedded between the top and bottom plates250and260. The top plate250and the bottom plate260are substantially parallel to each other. The first and second feed lines230and240may be at any suitable orientation or angle with respect to the top plate250and the inductor220.

FIG. 3Ais a diagram illustrating a series resonator21with via according to one embodiment of the invention. The series resonator21in this embodiment is substantially similar to the one shown inFIGS. 2A through 2Dexcept that it incorporates a via310on the top plate250. The inductor220is shown to be connected to the second feed line240at the second end. The via310connects the first feed230and the top plate250. The via310may have any convenient shape and size comparable with the top plate250(e.g., square 140□m x 140□m). Note that a typical via may be circular with diameter of 64□m or more. In some design technology, the via pad on the other hand, may have a minimum diameter of 124□m. The via size may be selected to control the parasitic inductance. In addition, an array of vias may be used in place of single via to control the inductance and resistance.

FIG. 3Bis a diagram illustrating a side view of the series resonator21with via shown inFIG. 3Aaccording to one embodiment of the invention. The side view shows the inductor220, the second feed line240, the bottom plate260, and the dielectric layer270. The via310connects the top plate250and the first feed line230. It may provide a contact point or connections to a routing layer, or other components or devices in the package.

FIG. 4Ais a diagram illustrating a parallel resonator circuit21according to one embodiment of the invention. The circuit21includes a capacitor (C)410and an inductor (L)420. The capacitor410and the inductor420are electrically connected in parallel at two terminals corresponding to first feed line430and second feed line440.

FIG. 4Bis a diagram illustrating a parallel resonator21according to one embodiment of the invention. The parallel resonator21includes the capacitor410and the inductor420.

The capacitor410and the inductor420are similar to the respective capacitor and inductor in the series resonator. The main difference is the connections to form a electrically parallel circuit. As in the series resonator shown inFIGS. 2A-2D, and3A-3B, the capacitor410includes a top plate450and a bottom plate460. The two plates are substantially parallel and embed a dielectric layer470. The inductor420is connected to the capacitor410at the bottom plate460and surrounds the capacitor410in a spiral geometry. As in the series resonator, the spiral geometry may be square, rectangular, or circular. The number of turns may range from ½ to 10.

The first feed line430is connected to the bottom plate460using a bottom via435. The second feed line440is connected to the top plate450and the second end of the inductor420at a first top via445. This connection is such that the capacitor410and the inductor420are electrically in parallel between the first and the second feed lines430and440as shown inFIG. 4A.

FIG. 4Cis a diagram illustrating a top view of the parallel resonator21shown inFIG. 4Baccording to one embodiment of the invention. The top view shows the inductor420and the first top via445. The bottom plate460is typically larger than the top plate450such that there is an exposed area to provide space for the first feed430and bottom via435.

FIG. 4Dis a diagram illustrating a side view of the parallel resonator21shown inFIG. 4Baccording to one embodiment of the invention. The side view shows the dielectric layer470. The first feed430and the second feed440may be at any suitable orientation or angle with respect to the top and bottom plates450and460. In addition, the height of the first top via445may be such that it is approximately equal to the distance between the plane of the inductor and the plane of the top plate450to reduce any mechanical stress between the second feed440and the inductor420.

FIG. 5Ais a diagram illustrating a parallel resonator21with a second top via according to one embodiment of the invention. The parallel resonator21includes the inductor420, the first feed line430, the bottom via435, the first top via445, the bottom plate460, and the dielectric layer470. The parallel resonator21inFIG. 5Ais similar to that shown inFIG. 4Bexcept that there is a second top via455that connects the second feed440to the top plate450.

The second top via455provides connections to other components or devices in the package. It may be referred to as an escape via and is typically used when there are restrictions with the routing layer which may be part of the package. The height of the first top via445may be such that the second feed440is substantially parallel to the inductor plane to avoid mechanical stress or strain on the second feed440.

FIG. 5Bis a diagram illustrating a top view of the parallel resonator21with a second via shown inFIG. 5Aaccording to one embodiment of the invention. The top view shows the inductor420, the first feed line430, the second feed line440, the bottom via435, the first top via445, the bottom plate460, and the dielectric layer470. The second top via455is preferably located at approximately the center of the top plate450and is aligned with the first top via445to provide mechanical stability.

FIG. 6is a flowchart illustrating a process600to form a compact integrated LC resonator according to one embodiment of the invention. It is noted that the flowchart does not necessarily show the exact sequence of the fabrication phases or operations. For example, the embedded passive components are fabricated as part of the package process. In addition, capacitors and inductors may be fabricated simultaneously.

Upon START, the process600forms a capacitor having top and bottom plates that embed a dielectric layer (Block610). The top and bottom plates are substantially parallel and are typically made of metal. Then, the process600surrounds the bottom plate by an inductor having a first end connected to the capacitor at the bottom plate and having N turns ending in a second end (Block615). The values of N may range from ½ to 10. Next, the process600determines if the LC resonator is series or parallel (Block620).

If the LC resonator is a series resonator, the process600connects a first feed to the top plate (Block625). Then, the process600connects the second feed to the second end such that the capacitor and the inductor are electrically in series (Block630). Next, the process600determines if a routing layer for additional connections is needed (Block635). If so, the process600connects a via between the first feed and the top plate (Block640) and is then terminated. Otherwise, the process600is terminated at the END block.

If the LC resonator is a parallel resonator, the process600connects a first feed to the bottom plate at a bottom via (Block645). Then, the process600connects the second feed to the top plate and the second end at a first top via such that the capacitor and the inductor are electrically in parallel (Block650). Next, the process600determines if a routing layer for additional connections is needed (Block655). If so, the process600connects a second top via between the second feed and the top plate (Block660) and is then terminated. Otherwise, the process600is terminated at the END block.