RRAM cell structure with conductive etch-stop layer

The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

BACKGROUND

Non-volatile memories are used in a wide variety of commercial and military electronic devices and equipment. Resistive random access memory (RRAM) is one promising candidate for next generation non-volatile memory technology due to its simple structure and CMOS logic compatible process technology that is involved. Each RRAM cell includes a metal oxide material sandwiched between top and bottom electrodes. This metal oxide material has a variable resistance whose resistance level corresponds to a data state stored in the RRAM cell.

DETAILED DESCRIPTION

An RRAM cell includes two electrodes with a resistive switching element placed between the two electrodes. Resistive switching elements or a variable resistive dielectric layer use a “forming process” to prepare a memory device for use. The forming process is typically applied at the factory, at assembly, or at initial system configuration. A resistive switching material is normally insulating, but a sufficient voltage (known as a forming voltage) applied to the resistive switching material will form one or more conductive pathways in the resistive switching material. Through the appropriate application of various voltages (e.g. a set voltage and reset voltage), the conductive pathways may be modified to form a high resistance state or a low resistance state. For example, a resistive switching material may change from a first resistivity to a second resistivity upon the application of a set voltage, and from the second resistivity back to the first resistivity upon the application of a reset voltage.

An RRAM cell may be regarded as storing a logical bit, where the resistive switching element has increased resistance, the RRAM cell may be regarded as storing a “0” bit; where the resistive switching element has reduced resistance, the RRAM cell may be regarded as storing a “1” bit, and vice-versa. Circuitry may be used to read the resistive state of the resistive switching element by applying a read voltage to the two electrodes and measuring the corresponding current through the resistive switching element. If the current through the resistive switching element is greater than some predetermined baseline current, the resistive switching element is deemed to be in a reduced resistance state, and therefore the RRAM cell is storing a logical “1.” On the other hand, if the current through the resistive switching element is less than some predetermined baseline current, then the resistive switching element is deemed to be in an increased resistance state, and therefore the RRAM cell is storing a logical “0.”

RRAM cells have conductive interconnects that connect the top and bottom electrodes to the rest of the device. In traditional RRAM cells, mask patterning and etching steps are involved while forming a bottom electrode via (BEVA) and a top electrode. Since the BEVA formed over a dielectric capping layer (with an opening) creates an uneven topography, a chemical mechanical polishing (CMP) process is carried out on the bottom electrode, so as to reduce topographic issues. Moreover, an etching process, which is carried out on the dielectric capping layer to form a bottom electrode via, would land on the lower metal interconnect (which is normally copper) and could lead to non-volatile copper etching by-products which in turn makes a cell chamber contaminated and difficult to maintain.

Accordingly, the present disclosure relates to a new architecture for RRAM cells that includes a conductive etch-stop layer between a lower metal connect and a bottom electrode of an RRAM stack. This architecture has a substantially planar topography and hence no CMP process is required during or after the formation of the bottom electrode. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the extremely low-k dielectric layer under the RRAM stack during the formation of the RRAM cell. The conductive etch stop layer can be etched using a dry or wet to land on copper which does not produce as much non-volatile copper etching by-products as in traditional methods. Moreover, this structure does not involve mask patterning steps for the formation of the bottom electrode or conductive etch-stop layer.

FIG. 1illustrates a cross sectional view of an RRAM stack100according to some embodiments of the present disclosure. The RRAM stack100resides over a semiconductor work-piece103comprising a conductive metal region101which has extremely low-k dielectric region102on either side. A conductive etch-stop layer104is disposed directly above the conductive metal region101. Above the conductive etch-stop layer104resides a bottom electrode108. In some embodiments the bottom electrode108comprises a transitional nitride layer106and a conductive electrode layer107above the transitional nitride layer106. A variable resistive dielectric layer or resistive switching element110abuts the entire top surface of the bottom electrode108. The variable resistive dielectric layer110and the bottom electrode108have vertical side walls that are aligned to one another. A top electrode114resides above the variable resistive dielectric layer110at a defined region. In one embodiment the top electrode114comprises a conductive electrode layer112and a transitional nitride layer113that resides on top of conductive electrode layer112. Two spacers118aand118bare disposed on either side of the top electrode114. The spacers118aand118balso reside on the two end locations of the variable resistive dielectric layer110. An antireflective layer116is disposed above the top electrode114. The antireflective layer116and the top electrode114have vertical sidewalls that are aligned to one another. A dielectric protection layer120envelopes the whole RRAM stack and resides above the semiconductor work-piece103.

As will be appreciated in greater detail below, the conductive etch stop layer104has an etch-selectivity that is different from that of the transitional nitride layer106. During manufacturing, this different etch-selectivity allows the conductive etch stop layer104to remain in place while the transitional nitride layer106is etched away. Thus, the transitional nitride layer106can be removed with a first etch which stops on the conductive etch stop layer104, such that the conductive etch stop layer104protects the underlying metal region101and low-k dielectric region102from the first etch process. A second etch can then be used to remove the conductive etch stop layer104, whereby the etched conductive electrode107and etched transitional nitride layer106act as a mask of sorts for the second etch, such that the final conductive etch stop layer104has sidewalls that are self-aligned with sidewalls of the transitional nitride layer106. Because the second etch can end on low-k dielectric102, the second etch can be tailored to limit damage to an upper surface of low-k dielectric102, which can have a relatively low structural integrity to due to its porous nature in some embodiments. Further, because this second etch can end on metal region101, which can be copper, the second etch can be tailored to limit non-volatile copper etching by-products in some instances. Thus, the use of materials with different etch selectivities for conductive etch stop layer104and transitional nitride layer106is advantageous from a variety of perspectives. Moreover, these etching techniques for RRAM stack100can limit the required mask patterning steps compared to conventional approaches.

At202, a semiconductor base surface comprising a metal interconnect structure disposed within an extremely low-k dielectric layer is provided. In some embodiments, the metal interconnect structure comprises copper.

At204, conductive etch-stop layer (CESL) is formed, abutting an upper surface of the metal interconnect structure. In some embodiments, the conductive etch stop layer comprises titanium (Ti); titanium nitride (TiN); titanium tungsten metal (TiW); tungsten (W); tungsten nitride (WN); a combination of titanium, cobalt or tantalum (Ti/Co/Ta); or tantalum nitride (TaN).

At206, a bottom RRAM electrode layer is formed above the CESL. In some embodiments, the bottom RRAM electrode comprises a conductive electrode layer over a transitional nitride layer. In some embodiments, the bottom RRAM electrode layer comprises only a conductive electrode layer. The transitional nitride layer provides bipolar switching and comprises of TiN or TaN in some embodiments. In some other embodiments, the conductive electrode layer of the bottom RRAM electrode comprises TiN.

At208, a variable resistive dielectric layer is formed above the bottom RRAM electrode layer. In some embodiments, the variable resistive dielectric layer comprises hafnium oxide (HfO2).

At210, a top RRAM electrode layer is formed above the variable resistive dielectric layer. In some embodiments, the top RRAM electrode comprises a conductive electrode layer with a transitional nitride layer above the conductive electrode layer. In some embodiments, the conductive electrode layer of the top RRAM electrode comprises Ti and the transitional nitride layer comprises TaN.

At302, a horizontal stack of base materials for the RRAM stack are formed over a semiconductor work-piece, the base materials comprising a conductive etch-stop layer (CESL), a bottom electrode, a variable resistive dielectric layer, and a top electrode.

At304, a mask is formed over the top electrode layer. The mask covers some portions of the top electrode layer while leaving other regions of the top electrode layer exposed. In some embodiments, the top electrode comprises a conductive electrode layer and a transitional metal nitride over the conductive electrode layer.

At306, a first etch is performed to remove exposed of the top electrode layer and form a top electrode structure. In some embodiments, the first etch comprises a dry etch comprising chlorine based (Cl2/BCl2) or fluorine based (CF4/CHF3/CH2/SF6) etchants.

At308, sidewall spacers are formed about the outer sidewalls of the top electrode. The sidewall spacers and top electrode structure cover some portions of the variable resistive dielectric layer and leave other portions of the variable resistive dielectric layer exposed. In some embodiments, the top electrode comprises TaN over Ti, and the sidewall spacer material comprises SiN (silicon nitride).

At310, a second etch is performed to remove exposed portions of the variable resistive dielectric layer. With the sidewall spacers and top electrode structure in place, performing a second etch removes the exposed portions of the variable resistive dielectric layer as well as underlying portions of the bottom electrode to form a bottom electrode structure. The second etch stops at the CESL such that the bottom electrode structure covers some portions of the CESL while leaving other portions of the CESL exposed. In some embodiments, the bottom electrode comprises a conductive electrode layer (e.g. TiN) over a transitional nitride layer (e.g. TaN) or a single layer of any conductive electrode layer. In some embodiments, the second etch comprises a dry etch comprising chlorine based (Cl2/BCl2) or fluorine based (CF4/CHF3/CH2/SF6) etchants.

At312, a third etch is performed to remove exposed portions of the CESL. In some embodiments, the third etch comprises wet etching comprising an alkali base (hydrogen peroxide (H2O2) or ammonia-peroxide mixture (APM)) or acid base (hydrogen fluoride (HF) or hydrochloric acid (HCl)) etchants or dry etching comprising chlorine based (Cl2/BCl2) or fluorine based (CF4/CHF3/CH2/SF6) etchants.

FIGS. 4-9illustrate embodiments of cross sectional images of a method of formation of an RRAM stack with a conductive etch stop layer according to the present disclosure.

FIG. 4illustrates a cross sectional image400of a semiconductor body having a horizontal stack of base materials over a semiconductor work-piece, for forming the RRAM stack. The semiconductor work-piece403comprises a metal interconnect structure401disposed within extremely low-k dielectric regions402. In some embodiments, the metal interconnect structure401comprises copper (Cu) and the extremely low-k dielectric regions402comprises porous silicon dioxide, fluorinated silica glass, polyimides, polynorbornenes, benzocyclobutene, or PTFE. Over the semiconductor work-piece403, a conductive etch-stop layer404is disposed. The conductive etch-stop layer404has an etch-selectivity that is different from that of the underlying semiconductor work-piece403as well as the layer above the conductive etch-stop layer404. The conductive etch-stop layer404can comprise Ti, TiN, TiW, W, WN, Ti/Co/Ta or TaN and its thickness ranges from 10 Angstroms to 150 Angstroms. Above the conductive etch-stop layer404, a bottom electrode408is deposited. The bottom electrode408comprises a transitional nitride layer406and a conductive bottom electrode layer407. In some embodiments, the transitional nitride layer406comprises TaN with a thickness of approximately 200 Angstroms and the conductive bottom electrode layer407comprises TiN with a thickness of approximately 100 Angstroms. Above the bottom electrode408, a variable resistive dielectric layer410is deposited. In some embodiments, the variable resistive dielectric layer410comprises HfO2 with a thickness of approximately 50 Angstroms. Over the variable resistive dielectric layer410resides a top electrode414. In some embodiments, the top electrode414comprises a conductive top electrode layer412and a transitional nitride layer413. In some embodiments, the conductive top electrode layer412comprises Ti, platinum (Pt) or ruthenium (Ru) with a thickness of approximately 50 Angstroms and the transitional nitride layer413comprises TaN with a thickness of approximately 250 Angstroms. Abutting the top surface of the top electrode414, an insulating anti-reflective layer416is deposited. This layer protects the underlying layers from the future etching steps and operated to improve patterning by reducing light reflection that causes standing waves. In some embodiment, the anti-reflective layer comprises SiON with a thickness of approximately 400 Angstroms.

FIG. 5illustrates a cross sectional image500, after performing a first etch on the horizontal stack in image400. After the first etch, a top electrode structure comprising the top electrode408and the antireflective layer416is formed at the center of the variable resistive dielectric layer410leaving exposed portions of the variable resistive dielectric layer410on either side.

FIG. 6illustrates a cross sectional image600, after forming spacers602on either side of the top electrode structure. In some embodiments, the spacer material comprises silicon nitride (SiN).

FIG. 7illustrates a cross sectional image700, after performing a second etch on the semiconductor body inFIG. 6. With the sidewall spacers602and top electrode structure in place, performing a second etch would remove the exposed portions of the variable resistive dielectric layer410as well as underlying portions of the bottom electrode408to form a bottom electrode structure. The second etch stops at the CESL404such that the bottom electrode structure covers some portions of the CESL404while leaving other portions of the CESL404exposed.

FIG. 8illustrates a cross sectional image800, after performing a third etch to remove exposed portions of the CESL404, stopping at the metal interconnect structure401. Outer sidewalls of the CESL404are substantially aligned to outer sidewalls of the bottom electrode. In some embodiments, the outer sidewalls of the CESL are separated by a first distance (L1), and the outer sidewalls of the first metal interconnect structure are separated by a second distance (L2), where the first distance is less than 1.2 times the second distance and greater than 0.8 times the second distance. i.e., 0.8*L2<L1<1.2*L2.

Depending on the CESL material, the etchants used in the third etch vary. If the CESL comprises TiN, W, TiW or WN, a dry etch or wet etch using H2O2 is performed. If the CESL is Co/Ta, only a dry etch is performed and if the CESL is TaN, a wet etch with APM (ammonia peroxide mixture) is performed.

FIG. 9illustrates a cross sectional image900, where a dielectric protection layer902is formed enveloping the whole RRAM stack and the exposed portions of the semiconductor workpiece403. In some embodiments, the dielectric protection layer comprises silicon carbide (SiC).

FIG. 10illustrates a cross sectional image1000of an embodiment of a semiconductor body, wherein the bottom electrode comprises a single conductive bottom electrode layer407. In this embodiment, the CESL is the transitional nitride layer406which has an etch-selectivity different from that of the bottom electrode407and the metal interconnect structure401underneath.

FIG. 11illustrates a cross sectional view of some embodiments of an RRAM device1100with a CESL according to the present disclosure. A plurality of such RRAM devices form a memory array configured to store data.FIG. 11comprises a conventional planar MOSFET selection transistor1101to suppress sneak-path leakage (i.e., prevent current intended for a particular memory cell from passing through an adjacent memory cell) while providing enough driving current for memory cell operation. The selection transistor1101comprises a source1104and a drain1106comprised within a semiconductor body1102, separated horizontally by a channel region1105. A gate electrode1108is located on the semiconductor body1102at a position that is above the channel region1105. In some embodiments, the gate electrode comprises poly silicon. The gate electrode1108is separated from the source1104and drain1106by a gate oxide layer or gate dielectric layer1107extending laterally over the surface of the semiconductor body1102. The drain1106is connected to a data storage element or RRAM stack1120by way of a first metal interconnect1112a. The source1104is connected by way of a first metal contact1112b. The gate electrode is connected to a word line1114a, the source is connected to a select line1114bthrough the first metal contact1112band the RRAM stack1120is further connected to a bit line1114ccomprised within an upper metallization layer by way of a second metal contact1112g. A desired RRAM device may be selectively accessed using word lines and bit lines for reading, writing and erasing operations. One or more metal contacts comprising1112c,1112d,1112e,1112fand metal contact vias comprising1110a,1110b,1110c,1110d,1110e,1110fetc. that helps in connecting the RRAM memory device with the external circuitry may be present between the drain1106and the second metal contact1112g, and between the source1104and the first metal contact1112b. In some embodiments, the metal contacts comprise copper (Cu).

The RRAM cell1120comprises a resistive switching element/variable resistive dielectric layer1121sandwiched between a top electrode1122and a bottom electrode1123. In some embodiments, the top electrode comprises titanium (Ti) and tantalum nitride (TaN), the bottom electrode comprises titanium nitride (TiN) alone or two layers comprising TiN and TaN, and the resistive switching element comprises hafnium dioxide (HfO2). A top electrode via (TEVA)1124connects the top electrode1122of the memory cell1120to the second metal contact1112gand a CESL1125connects the bottom electrode1123of the RRAM cell1120to the first metal interconnect1112a.

It will be appreciated that while reference is made throughout this document to exemplary structures in discussing aspects of methodologies described herein that those methodologies are not to be limited by the corresponding structures presented. Rather, the methodologies (and structures) are to be considered independent of one another and able to stand alone and be practiced without regard to any of the particular aspects depicted in the Figs. Additionally, layers described herein, can be formed in any suitable manner, such as with spin on, sputtering, growth and/or deposition techniques, etc.

Also, equivalent alterations and/or modifications may occur to those skilled in the art based upon a reading and/or understanding of the specification and annexed drawings. The disclosure herein includes all such modifications and alterations and is generally not intended to be limited thereby. For example, although the figures provided herein, are illustrated and described to have a particular doping type, it will be appreciated that alternative doping types may be utilized as will be appreciated by one of ordinary skill in the art.

In addition, while a particular feature or aspect may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features and/or aspects of other implementations as may be desired. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, and/or variants thereof are used herein, such terms are intended to be inclusive in meaning—like “comprising.” Also, “exemplary” is merely meant to mean an example, rather than the best. It is also to be appreciated that features, layers and/or elements depicted herein are illustrated with particular dimensions and/or orientations relative to one another for purposes of simplicity and ease of understanding, and that the actual dimensions and/or orientations may differ substantially from that illustrated herein.

The present disclosure relates to a resistive random access memory (RRAM) device comprising a resistive random-access memory (RRAM) stack having a conductive etch-stop layer (CESL) that couples a bottom electrode to a first metal interconnect structure arranged under the bottom electrode. The CESL has an etch-selectivity different from that of the bottom electrode and the first metal interconnect structure which allows a dry or dry+wet etch to be performed on the CESL, landing on the metal interconnect structure. The disclosure presents a simple structure and process that saves one mask step and that requires no CMP process during the formation of the bottom electrode, compared to traditional processing methods.

In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) device, comprising, a variable resistive dielectric layer having a top surface and a bottom surface, a top electrode disposed over the variable resistive dielectric layer abutting the top surface, a bottom electrode disposed below the variable resistive dielectric layer abutting the bottom surface, and a conductive etch-stop layer (CESL) that couples the bottom electrode to a first metal interconnect structure arranged under the bottom electrode.

In another embodiment, the present disclosure relates to a resistive random access memory (RRAM) device, comprising, a semiconductor body having a source region and a drain region horizontally separated by a channel region, a gate structure coupled to the channel region, a first contact and a second contact disposed above the source and drain regions, respectively, a first metal interconnect structure disposed above the drain region, residing below the second contact and electrically coupled to the second contact, a resistive random-access memory (RRAM) stack formed above the first metal interconnect, and a conductive etch-stop layer coupling a top surface of a first metal interconnect to the RRAM stack.

In yet another embodiment, the present disclosure relates to a method of forming a resistive random-access memory (RRAM) device comprising, providing a semiconductor base surface comprising a metal interconnect structure disposed within an extremely low-k dielectric layer, forming a conductive etch-stop layer (CESL) abutting an upper surface of the metal interconnect structure, and forming a bottom RRAM electrode layer above the CESL, forming a variable resistive dielectric layer above the bottom RRAM electrode layer; and forming a top RRAM electrode layer above the variable resistive dielectric layer.