Processor instructions for iterative decoding operations

A storage circuit is configured to store multiple vectors associated with variable and check nodes of an iterative decoding operation. As part of the iterative decoding operation, a processor circuit is configured to retrieve, from the storage circuit, an intermediate value vector, a first estimation vector, a second estimation vector, and a sign vector, and determine an absolute value of the intermediate value vector. The processor circuit is also configured, using the retrieved vectors, to generate updated values for the first and second estimation vectors as part of determining a bit estimate for a check node included in the iterative decoding operation.

BACKGROUND

Technical Field

This disclosure relates to instruction processing in a computer system, and, in particular, to handling errors in instructions retrieved from memory.

Description of the Related Art

Computer systems can employ multiple processors or processor cores to perform various tasks by executing software or program instructions. Such software or program instructions may be written in a high-level computer language (e.g., C++) and then compiled into a set of instructions that can be performed by a processor or processor core. This set of instructions is referred to as a processor's “Instruction Set Architecture” (or “ISA”). During compilation of a software program or application for a particular processor, complex instructions written in the high-level computer language may be converted into a series of instructions included in the ISA of the particular processor.

To execute software or program instructions, processors or processor cores retrieve or “fetch” the compiled instructions from memory circuits, or other storage device (e.g., a solid-state disc drive), or over a network. In some cases, frequently used instructions may be stored in a cache memory to reduce the time needed to fetch such frequently used instructions.

Once an instruction has been fetched, a processor may begin a series of operations in order to execute the instruction. For example, upon receiving an instruction, a processor may perform a decode operation on the received instruction to determine if the instruction is a valid instruction in the ISA. Many processors employ multiple stages arranged in a pipelined fashion to sequentially perform the operations needed to execute a particular instruction. As the particular instruction moves through the different stages, each stage performs a different operation. Once the instruction has passed through all of the stages included in the pipeline, the instruction is completed by the processor.

SUMMARY

The present disclosure describes a technique for performing operations associated with an iterative decoding process. A storage circuit is disclosed that stores a plurality of vectors associated with an iterative decoding operation. A processor core retrieves a subset of the plurality of vectors from the storage circuit. The subset includes an intermediate value vector, a first estimation vector, a second estimation vector, and a sign vector. Upon receiving the subset of the plurality of vectors, the processor core determines an absolute value of the intermediate value vector, and generates an updated value for the first estimation vector using the absolute value of the intermediate value vector. The processor core additionally generates an updated value for the second estimation vector using the absolute value of the intermediate value vector, the updated value for the first estimation vector, and a current value of the second estimation vector. The processor core further generates an updated value for the sign vector using a current value of the sign vector and a sign of the intermediate value vector.

DETAILED DESCRIPTION

Some memory circuits store information as charge in a storage cell. When a storage cells is accessed or “read,” the charge stored in the storage cell is translated to a voltage level, which is interpreted as a particular logic value. Differences in the electrical properties between different storage cells can result in different voltage levels for the same logic value. As a result, a voltage level generated by a storage cell is used in conjunction with reliability information on the stored data to determine a logic value corresponding to the voltage level.

One technique for determining a logic value for a voltage level generated by a storage cell involves the use of a soft-decoding algorithm. Such an algorithm includes an iterative message-passing decoding process where a metric is passed between nodes where corresponding values of the metric are updated. One metric often used in soft-decoding of storage cell values is a log-likelihood ratio (“LLR”) associated with the voltage level read from a storage cell. As depicted in Equation 1, the LLR for a given bit b as a function of read voltage V is given by the logarithm of the ratio of the probability that the bit value is a logical-0 to the probability that the bit value is a logical-1.

A LLR value can be a value between negative infinity and positive infinity, where the sign of the value corresponds to an estimate of the bit value, while the magnitude of the LLR corresponds to a reliability of the bit estimate. It is noted that a LLR is one possible metric that can be used in a soft-decoding algorithm and soft-decoding algorithms may employ different metrics.

During execution of the soft-decoding algorithm, variable nodes in a decoder are initialized with LLR bit estimates based on voltages read from storage cells in a memory circuit. In an iterative process, each check node of the decoder is serially traversed where the bit estimates are updated. The process continues until parity checks have been satisfied, at which point bit values have been determined based on the voltages read from the storage cells.

A variable node within the decoder performs simple addition operations. Check nodes, however, need to perform more complex operations to determine bit estimates. An example of the computation of a bit estimate Rcvat a check node is depicted in Equation 2, where Qvcis a bit estimate from a variable node. As shown in Equation 2, to determine a bit estimate includes the calculation of hyperbolic tangent, making the computation of the bit estimate challenging.

The calculation of a bit estimate can be simplified by taking the value of Qvcwith the lowest magnitude and a sign that is the product of the Qvcsigns. An example of the simplification is depicted in Equation 3. This simplification is referred to as the min-sum algorithm. In some cases, the number of Qvcmessages may be in the order of a few dozens, allowing for a further simplification by accumulating Qvcmessages one at a time in what is referred to as a soft_xor operation.

In some computer systems, soft-decoding algorithms are implemented as dedicated circuits that may include both sequential logic circuits and combinatorial logic circuits to implement the variable and check nodes needed to perform a soft-decoding algorithm. Such dedicated circuits receive a voltage level from a storage cell along with additional information and perform an iterative decoding operation to refine a LLR value for the voltage level. Upon completion of the decoding operation, a logic value is determined based on the LLR value.

In some cases, even with the min-sum simplification, the iterative decoding operation may be too complex for a dedicated circuit, resulting in an incorrect LLR value or an error. Alternatively, or additionally, the dedicated circuit may be too costly in terms of power and area consumption for some applications. In such cases, the iterative decoding process may be performed by a general-purpose processor or processor core configured to execute a software or application program. In such cases, the variable and check nodes exist as virtual entities, with the value that they generate being determined by the general-purpose processor or processor core executing the software or application program.

When the iterative decoding operation is implemented using a general-purpose processor or processor core, many software instructions may be repeatedly fetched and executed to implement repeated tasks included in the iterative decoding operation. Such repeated fetching and execution can increase power consumption as well as limit the performance of the general-purpose processor or processor core. The embodiments illustrated in the drawings and described below may provide techniques for implementing an iterative decoding operation on a general-purpose processor or processor core with a modified instruction set architecture that includes instructions which can replace multiple software instructions associated with repeated tasks in the iterative decoding operation. By employing such a modified instruction set architecture, software can be simplified, thereby reducing power consumption and improving performance.

Turning now toFIG.1, a block diagram of a computer system is depicted. As illustrated, computer system100includes storage circuit101, and processor circuit102, which includes processor cores103A and103B. It is noted that although processor circuit102is depicted as including two processor cores, in other embodiments, any suitable number of processor cores may be employed.

Storage circuit101is configured to store vectors111. In various embodiments, vectors111may be associated with an iterative decoding process such as described above. The number of vectors included in vectors111may be based on a number of nodes included in the iterative decoding process, such as bit estimates from parity check nodes and bit estimates from variable nodes. Any of vectors111may include N bits arranged in corresponding ordered bit positions, where N is a positive integer.

Processor core103A is configured to retrieve, from storage circuit101, a subset of vectors111that includes intermediate vector104, estimation vector105, estimation vector106, and sign vector107. Processor core103A is further configured to determine an absolute value of intermediate vector104, and generate updated estimation vector109using the absolute value of intermediate vector104. Processor core103A is also configured to generate updated estimation vector110using the absolute value of intermediate vector104, updated estimation vector109, and estimation vector106. Additionally, processor core103A is further configured to generate updated sign vector108using sign vector107and a sign of intermediate vector104.

In some embodiments, processor core103A may be configured to perform a combination of the operations described above in response to receiving a soft_xor command. Pseudo code for the soft_xor command is depicted in Example 1, where Qvc corresponds to intermediate vector104, Min1 corresponds to estimation vector105, Min2 corresponds to estimation vector106, and S corresponds to sign vector107. As shown in Example 1, the soft_xor command combines the above-described operations as a multi-cycle set of operations that can be activated by the execution of a single instruction instead of multiple instructions, thereby improving performance and reducing power consumption by saving instruction fetch operations. It is noted that in various embodiments, the two logical expressions (e.g., if |Qvc|<Min 1) may be executed in parallel, or may be combined into a single logical expression.

While the soft_xor command can reduce the complexity of a software program or application designed to perform an iterative decoding process, additional commands are also possible and contemplated. Such commands may include correction commands that apply a correction to the results of the soft_xor command, thereby improving performance of the soft_xor command. The correction commands may include two types of correction that can be used to modify the results of the soft_xor command.

One type of correction command is an additive correction command. Pseudo code for an additive correction command is depicted in Example 2, where Min corresponds to estimation either of estimation vector105or estimation vector106, S corresponds to sign vector107, and alpha is a coefficient based on node relationships that stem from the code matrix.

In response to receiving an additive correction command, which may be included in instructions114, processor core103A is further configured to determine a difference between estimation vector105and the updated estimation vector109, and to determine a product of the difference and coefficient112. Processor core103A is also configured to generate a corrected value for estimation vector105using the updated value of estimation vector105and the product. It is noted that while the above description is described in terms of estimation vector105, in various embodiments, the additive correction command may be applied to estimation vector106as well.

The correction commands may also include a multiplicative correction command. Pseudo code for a multiplication correction command is depicted in Example 3, where Min corresponds to estimation either of estimation vector105or estimation vector106, S corresponds to sign vector107, and alpha corresponds to coefficient112and is based on node relationships that stem from the code matrix.

In response to receiving an additive correction command, which may be included in instructions114, processor core103A is further configured to generate a corrected value for estimation vector105using coefficient112and updated estimation vector109. It is noted that coefficient112may be stored in storage circuit101or any other suitable storage location. In various embodiments, processor core103A is further configured to multiply coefficient112and updated estimation vector109to generate the corrected value for estimation vector105. It is noted that while the above description is described in terms of estimation vector105in various embodiments, the additive correction command may be applied to estimation vector106as well.

In various embodiments, the operations associated with the soft_xor and the additive and multiplicative correction command, are performed on fixed point, e.g., estimation vector105is a fixed-point number. As such, it is important that no overflows are encountered during the iterative decoding process. To limit the possibility of overflow, processor core103A is further configured to perform a saturation check operation. To perform the saturation check operation, processor core103A is further configured to perform a comparison of updated estimation vector109to threshold113, and adjust updated estimation vector109using the result of the comparison. In various embodiments, threshold113may be stored in storage circuit101or any other suitable storage location.

In some embodiments, to adjust updated estimation vector109, processor core103A is further configured to set a value of updated estimation vector109to threshold113. It is noted that the saturation operation may be applied to any of updated sign vector108, updated estimation vector109, and updated estimation vector110. In some cases, the saturation check operation may be concatenated with the soft_xor command to prevent additional instruction fetches.

Turning toFIG.2, a block diagram of a processor core is depicted. As illustrated, processor core200includes instruction fetch unit210, memory management unit220, execution unit230, load store unit250, cache interface270, and L2 cache290. In various embodiments, processor core200may correspond to either of processor cores103A or103B.

Instruction fetch unit210is coupled to memory management unit220and cache interface270. In various embodiments, instruction fetch unit210is configured to perform various operations relating to the fetching of instructions from a cache or memory circuit, the selection of instructions from various threads of execution, and the decoding of such instructions prior to issuing the instructions to various functional units for execution. As illustrated, instruction fetch unit210includes instruction cache214and program counter215.

In some embodiments, program counter215is configured to generate multiple values corresponding to addresses of instructions to be fetched for respective threads being executed by processor core200. Program counters215may be implemented using one or more sequential logic circuits configured to generate such address values.

Memory management unit220is configured to relay requests and responses from instruction fetch unit210and cache interface270to and from system memory. In various embodiments, memory management unit220may be further configured to perform address translation from a virtual address space used by processor core200to a physical address space used by system memory. Memory management unit220may, in other embodiments, be configured to translated requests from an internal format used within processor core200to a format compatible with system memory. In a similar fashion, memory management unit220may be further configured to translate replies from system memory into a format compatible with processor core200. In various embodiments, memory management unit220may be implemented using a state machine or other sequential logic circuit, a microcontroller, or any other suitable logic circuit.

Execution unit230is configured to execute and provide results for certain types of instructions issued from instruction fetch unit210. In some embodiments, execution unit(s)230may be configured to execute certain integer-type instructions defined in the implemented instruction set architecture including the soft_xor command described above. It is noted that although only a single execution unit is depicted in the embodiment ofFIG.2, in other embodiments, multiple execution units may be employed.

As illustrated, execution unit230includes storage circuit101. In various embodiments, information indicative of vectors104-107may be stored in storage circuit101prior to execution unit230executing a soft_xor or vector shift command. It is noted that although storage circuit101is depicted as being included in execution unit230, in other embodiments, storage circuit101may be external to execution unit230or external to processor core200, and may be located at any suitable location in the hierarchy of a storage controller or computer system.

Load store unit250is configured to process data memory references, such as integer and floating-point load and store instructions. In some embodiments, load store unit250may be further configured to assist in the processing of instruction cache214misses originating from instruction fetch unit210. As illustrated, load store unit250includes data cache252in addition to a logic circuit configured to detect cache misses and, in response to such misses, request data from L2 cache290or a higher-level cache memory via cache interface270.

In various embodiments, data cache252may be implemented as a write-through cache, in which all writes (or “stores”) to data cache252are written to a higher-level cache memory regardless of whether the stores hit in data cache252. In some cases, writes that miss in data cache252can result in an allocation within data cache252that can be used for storing the data. Data cache252may, in various embodiments, be implemented as a static random-access memory (SRAM) circuit or other suitable memory circuit.

L2 cache290is configured to store (or “cache”) frequently used instructions and data for use by execution unit230. In various embodiments, L2 cache290may be implemented using multiple banks that can be independently accessed using corresponding addresses. Such banks may be implemented using set-associative or direct-mapped techniques. In some embodiments, L2 cache290, including any banks, may be implemented as SRAM circuits or any other suitable memory circuits.

Cache interface270is configured to relay data requests from data cache252and L2 cache290to higher-level cache memory circuits. In response to a determination that requested data is unavailable from the higher-level cache memory circuits, cache interface270may relay the data request to memory management unit220for transmission to system memory or other storage. Cache interface270may, in various embodiments, be implemented using a state machine or other sequential logic circuit, a microcontroller, or any other suitable logic circuit.

Turning toFIG.3, an embodiment of storage circuit101is depicted. As illustrated, storage circuit101includes registers301-304. It is noted that although only four registers are depicted in the embodiment ofFIG.3, in other embodiments, any suitable number of registers may be employed.

Register301is configured to store intermediate vectors305A-305C. In various embodiments, intermediate vectors305A-305C may include information indicative of intermediate results of corresponding nodes of an iterative decoding process being performed on a given bit. The information may, in some embodiments, include a log-likelihood ratio value associated with the given bit. Although register301is depicted as storing only three intermediate vectors, in other embodiments, register301may be configured to store any suitable number of intermediate vectors.

Registers302and303are configured to store estimation vectors306A-306C and307A-307C, respectively. In various embodiments, estimation vectors306A-306C and307A-307C may include data indicative of estimates of the value of the given bit. In some cases, the data may encode a log-likelihood ratio associated with the given bit. Although registers302and303are depicted as each storing only three estimation vectors, in other embodiments, registers302and303may be configured to store any suitable number of estimation vectors.

Register304is configured to store sign vectors308A-308C. In various embodiments, sign vectors308A-308C may include information indicative of a sign of a corresponding one of intermediate vectors305A-305C. Although register304is depicted as storing only three sign vectors, in other embodiments, register304may be configured to store any suitable number of sign vectors.

Each of registers301-304can include multiple storage circuits configured to store corresponding bits. Such storage circuits may be implemented using latch circuit, flip-flop circuits, or any other circuit configured to store information indicative of a bit. In various embodiments, portions of any of registers301-304may be accessed independently. For example, intermediate vector305A and305C may be accessed in register301without accessing intermediate vector305B.

It is noted that although storage circuit101is depicted as including multiple registers, in other embodiments, storage circuit101may be implemented as a memory circuit that does not include registers. In such cases, the locations of individual vectors may be mapped to specific addresses with an address space of the memory circuit.

Turning toFIG.4, a block diagram of an embodiment of a system that includes processor core coupled to a storage circuit and a tag storage circuit is depicted. As illustrated, system400includes storage circuit101, processor core103A, and tag storage circuit401.

Storage circuit101is configured to store vectors405-407at locations402-404, respectively. Each of locations402-404may be specified by corresponding one of tags408stored in tag storage circuit401. In various embodiments, vectors405-407may correspond to any of the vectors associated with an iterative decoding process as depicted inFIG.3. It is noted that although only three vectors are depicted in the embodiment ofFIG.4, in other embodiments, any suitable number of vectors may be stored in corresponding locations within storage circuit101.

As described above, processor core103A may be configured to shift vectors, such as vectors405-407, prior to performing operations to update the values of the vectors. For example, processor core103A is configured, in response to receiving vector shift command409, to change the storage locations of vectors405-407within storage circuit101. As illustrated, processor core103A is configured to move vector405from location402to location403, move vector406from location403to404, and move vector407from location404to location402, essentially performing a shift operation. It is noted that while a shift of a single position is depicted in the embodiment ofFIG.4, in other embodiments, a shift of more than a single position is possible, and the number of shift positions may be specified in vector shift command409.

To move individual vectors within storage circuit101, processor core103A may be further configured to retrieve a particular vector from storage circuit101, and re-write the particular vector to a different location within storage circuit101. Alternatively, processor core103A may be configured to modify tags408, which encode the storage locations for vectors405-407. By modifying tags408, the information specifying the storage locations for vectors405-407within storage circuit101may be changed, which has the effect of moving vectors405-407within the address space of storage circuit101, without actually having to move the data for vectors405-407.

Both storage circuit101and tag storage circuit401may be implemented as SRAMs, register files, or any other suitable storage circuits. It is noted that although only a single processor core is depicted in the embodiment ofFIG.4, in other embodiments, additional processor cores may be coupled to storage circuit101and tag storage circuit401.

Turning toFIG.5, a block diagram of a storage system is depicted. As illustrated, storage system500includes storage controller circuit501and memory circuits504A and504B. Storage controller circuit501includes error correction circuit502and processor circuit503. It is noted that, in various embodiments, processor circuit503may correspond to processor circuit102as depicted inFIG.1.

Memory circuits504A and504B are coupled to communication bus505. In various embodiments, memory circuit504A is configured to send data506to storage controller circuit501via communication bus505. It is noted that communication bus505may be a serial or parallel interface and may employ a particular one of various communication protocols, such as the common flash memory interface or any other suitable interface standard.

In various embodiments, memory circuits504A and504B may be implemented using either volatile or non-volatile storage cells. For example, in some embodiments, memory circuits504A and504B may be implemented as flash memory circuits, magnetic random-access memory (MRAM) circuits, spin transfer torque random-access memory (STT-RAM) circuits, ferroelectric random-access memory (FeRAM) circuits, or resistive random-access memory (RRAM) circuits, while in other embodiments, memory circuits504A and504B may be implemented as dynamic random-access memory (DRAM) circuits. Although only two memory circuits are depicted in the embodiment ofFIG.5, in other embodiments, any suitable number of memory circuits may be employed.

Error correction circuit502is configured to receive data506from memory circuit504A via communication bus505. In various embodiments, data506may be indicative of value of a given bit of multiple bits stored in memory circuit504A. In some cases, data506may include information indicative of a log-likelihood ratio associated with the given bit.

Error correction circuit502is configured to analyze data506. To analyze data506, error correction circuit502may be further configured to perform an initial number of iterations of an iterative decoding operation. Error correction circuit502may be further configured, based on intermediate results of the initial number of iterations, to determine if it is capable of completing the iterative decoding process. In some embodiments, error correction circuit502is further configured to perform an analysis of data506, and to transfer data506to processor circuit503based on results of the analysis.

In various embodiments, to perform the analysis of data506, error correction circuit502may be further configured to perform an initial number of decoding iterations of an iterative decoding operation. Error correction circuit502may also be configured to transfer data506to processor circuit503based on intermediate results generated by the initial number of decoding iterations. In other embodiments, error correction circuit502may be further configured to transfer the intermediate results to processor circuit503in addition to the data506.

In various embodiments, error correction circuit502may include storage circuits (not shown) and may be implemented as a sequential logic circuit, microcontroller, or any other suitable circuit.

Processor circuit503is configured to perform an iterative decoding operation using data506to determine a final value for the given bit. In some embodiments, processor circuit503may also be configured to determine the final value for the given bit using data506along with intermediate decoding results generated by error correction circuit502. In various embodiments, processor circuit503may correspond to either processor core103A or processor core103B as depicted in the embodiment ofFIG.1.

Turning toFIG.6, a flow diagram depicting an embodiment of a method for performing an operation associated with an iterative decoding process is illustrated. The method, which may be applied to various processor circuits (e.g., processor circuit102), begins in block601.

The method includes receiving, by a given processor core of a plurality of processor cores, a first intermediate value vector, a first estimation vector, a second estimation vector, and a sign vector (block602). In various embodiments, each of the first intermediate value vector, the first estimation vector, the second estimation vector, and the sign vector may include respective sets of N bits, arranged in N ordered bit positions, where N is a natural number. The method also includes determining, by the given processor core, an absolute value of the first intermediate value vector (block603).

The method further includes generating, by the given processor core, an updated value for the first estimation vector using a minimum of a current value of the first estimation vector and the minimum of the first intermediate value vector (block604). In some embodiments, generating the updated value for the first estimation vector includes determining a difference between the absolute value of the first intermediate value vector and the updated value for the first estimation vector, determining a product of the difference and a coefficient, and generating a corrected value for the first estimation vector using the updated value of the first estimation vector and the product. In various embodiments, the method may further include generating, by the given processor core, the corrected valued for the first estimation vector using a coefficient and the updated value of the first estimation vector.

The method may, in some embodiments, also include performing, by the given processor core, a comparison of the updated value for the first estimation vector to a threshold value, and adjusting, by the given processor core, the updated value for the first estimation vector using results of the comparison. In some embodiments, adjusting the updated value for the first estimation vector may include selecting a minimum value of the updated value for the first estimation vector and the threshold value.

The method also includes generating, by the given processor core, an updated value for the second estimation vector using a minimum of the updated value of the first estimation vector, the absolute value of the first intermediate value vector, and a current value of the second estimation vector (block605).

The method further includes generating, by the given processor core, an updated value for the sign vector using a current value of the sign vector and a sign of the first intermediate value vector (block606).

In some embodiments, the first intermediate value vector is included in a plurality of intermediate value vectors stored in corresponding ones of a plurality of registers. In such cases, the method may further include changing respective registers in which the plurality of intermediate value vectors are stored, and retrieving, by the given processor cores, the first intermediate value vector from its new storage location prior to a determination of the absolute value of the first intermediate value vector.

In other embodiments, the method may further include receiving a second intermediate value vector, a third estimation vector, a fourth estimation vector, and a second sign vector. In such cases, the method may also include determining an absolute value for the second intermediate value vector, and generating, in parallel to generating the updated value for the first estimation vector, an updated value for the third estimation vector using a minimum of a current value of the third estimation vector and the absolute value of the second intermediate value vector. The method concludes in block607.

In some iterative decoding applications, adjusting a determined intermediate value at one of the decoding nodes may improve the performance of the decoding process by reducing a number of iterations. A flow diagram depicting an embodiment of a method for performing one such adjustment is depicted inFIG.7. The method, which may be applied to various processor circuits, such as processor circuit102, begins in block701. It is noted that the method depicted in the flow diagram ofFIG.7may be used in conjunction with the method depicted in the flow diagram ofFIG.6.

The method includes determining, by a given processor core, a difference between an absolute value of an intermediate value vector and an updated value of a first estimation vector (block702). In various embodiments, the intermediate value vector and the first estimation vector may be associated with a particular decoding node included in an iterative decoding process. In various embodiments, the method may further include storing, by the given processor core, the difference in a temporary register.

The method further includes determining, by the given processor core, a product of the difference and a coefficient (block703). In various embodiments, the method may further include retrieving the difference from the temporary register and retrieving the coefficient from a storage location. In some embodiments, the storage location may be a particular register in a register file, a main memory circuit, or any other suitable storage location. It is noted that a value of the coefficient may be based on a type of the iterative decoding process.

The method further includes generating, by the given processor core, a corrected value for the first estimation vector using the updated value of the first estimation vector (block704). In various embodiments, the method may also include storing the corrected value for the first estimation vector in a register that originally stored the updated value of the first estimation vector. The method concludes in block705.

Another adjustment that may be employed when performing an iterative decoding operation is a multiplicative correction. A flow diagram depicting an embodiment of a method for performing a multiplicative correction is illustrated inFIG.8. The method, which may be applied to various processor circuits (e.g., processor circuit102), begins in block801.

The method includes receiving, by a given processor core of a plurality of processor cores, a coefficient (block802). In various embodiments, the method may include retrieving the coefficient from a storage location, such as a particular register of a register file, a memory circuit, and the like. It is noted that the coefficient may, in various embodiments, be based on characteristics of the given processor core or characteristics of an algorithm used by the given processor core to perform the iterative decoding operation.

The method further includes multiplying, by the given processor core, an updated version of a first estimation vector by the coefficient to generate a corrected value for the first estimation vector (block803). In various embodiments, the method may further include storing the corrected value by overwriting the updated version of the first estimation vector in the same storage location. The method concludes in block804.

In some cases, information to be processed by a particular node in an iterative decoding operation may need to be routed to a different node. Such re-routing can involve retrieving the information and temporarily storing the retrieved information prior to re-storing the information in new locations from which the different node retrieves its information. The process of retrieving and re-storing data may include the execution of additional software or program commands, thereby reducing the performance of the iterative decoding operation.

As described above, the inclusion of an additional shift command in the instruction set of a processor or processor core, and the overhead associated with re-routing of information within an iterative decoding operation may be reduced. A flow diagram depicting an embodiment of a method for moving data within a storage circuit (e.g., storage circuit101) is illustrated inFIG.9. The method, which may be applied to various processor circuits such as processor circuit102, begins in block901.

The method includes storing, by a given processor core of a plurality of processor cores, a plurality of vectors in corresponding ones of a plurality of registers (block902). In various embodiments, the plurality of vectors may correspond to intermediate values of an iterative decoding operation. In some cases, the intermediate values may be LLR values corresponding to a probability that information read from a memory circuit has a particular bit value.

In various embodiments, the plurality of registers may be included in a register file or other storage circuit (e.g., storage circuit101). It is noted that, in some embodiments, the plurality of registers may include support circuitry that can be employed in moving data from one register to another.

The method also includes moving, by the given processor core in response to executing a software command, the plurality of vectors to different ones of the plurality of registers (block903). In various embodiments, moving the plurality of vectors may include performing a shift operation on the plurality of vectors. Such a shift operation may be implemented by the given processor core retrieving data from a given register of the plurality of registers, and re-writing the information to a different register of the plurality of registers. In other cases, the given processor core may activate a signal that causes the plurality of registers to perform a shift operation.

In some cases, a processor or processor core accesses data in a register file using identifying information referred to as “register tags” (or simply “tags”). Tags encode information of where a particular vector is stored within the plurality of registers. In some embodiments, moving the plurality of vectors may include modifying a plurality of tags corresponding to the plurality of vectors. By modifying the tags corresponding to the plurality of vectors, the storage locations of a given vector will appear to have changed even though the actual location of the given vector remains the same. Using such a method can reduce power consumption by avoiding the movement of the data stored in the plurality of registers.

The method further includes performing, by the given processor core, an operation that includes retrieving the plurality of vectors from the different ones of the plurality of registers (block904). In various embodiments, retrieving the plurality of vectors may include retrieving a plurality of tags corresponding to the plurality of vectors, and retrieving the plurality of vectors from the storage circuit using the plurality of tags. The method concludes in block905.

When operations such as those described above are performed by a processor or processor core on fixed-point data, caution must be exercised to prevent overflows. A flow diagram of an embodiment of a method for performing a saturation check is illustrated inFIG.10. The method, which may be applied to processor circuit102, begins in block1001.

The method includes performing, by a given processor core of a plurality of processor cores, a comparison of an initial result of an operation with a threshold value (block1002). In various embodiments, the threshold value may be based on a maximum value that the given processor core can use. In some cases, the maximum value is determined by a number of bits (e.g., 64-bits) used to store data within the given processor core.

The method also includes generating, by the given processor core, a final result using a result of the comparison (block1003). In various embodiments, generating the final result may include setting the final result to a minimum of the initial result and the threshold value. By limiting the value for the final result in this fashion, an overflow condition may be avoided. It is noted that the saturation check described above may be performed by a processor or processor core after each operation (or sub-operation with a given operation) included in an iterative decoding operation. The method concludes in block1004.

As described above, a storage controller may include both a dedicated decoder circuit as well as one or more processor circuits. In some cases, the dedicated decoder circuit may be unable to complete a particular iterative decoding operation. Such failures may be the result of limitations with the decoder circuit, or a complexity with the data to be decoded, or a combination thereof. In such cases, one of the processor circuits may be used to perform the iterative decoding operation. Turning toFIG.11, a flow diagram depicting an embodiment of a method for operating a storage controller is illustrated. The method, which may be applied to storage controller circuit501, begins in block1101.

The method includes receiving, by a storage controller from a storage device, information indicative of a value of a bit (block1102). In various embodiments, the storage controller includes both a decoder circuit and one or more processor circuits, such as processor circuit102. The storage device may, in various embodiments, include one or more memory circuits. In some cases, the information may include multiple bits that encode a logarithm of a likelihood that the bit has a particular value (e.g., a logical-1 value).

The method also includes performing, by a decoder or error correction circuit, an analysis of the information (block1103). In various embodiments, the analysis may include performing an initial number of iterations of an iterative decoding operation. Based on intermediate results of the initial number of iterations, the decoder circuit can determine if it is capable of completing the iterative decoding process. In some cases, the analysis may include performing the iterative decoding operation until an error is detected.

The method further includes transferring, by the decoder circuit, the information to a processor circuit based on results of the analysis (block1104). In various embodiments, the decoder circuit may transfer an original version of the information to the processor circuit in response to a determination that the iterative decoding process cannot be completed. Alternatively, a current state of the iterative decoding operation may be transferred to the processor circuit instead of, or in addition to, the original version of the information. In various embodiments, the current state may include intermediate values for corresponding nodes within the decoding operation.

The method also includes performing, by the processor circuit, an iterative decoding operation using the information to determine a final value of the bit (block1105). In various embodiments, to perform the iterative decoding operation, the processor circuit may perform one or more of the operations (e.g., a shift operation) described above. The method concludes in block1106.

Processor circuit102described above with reference toFIG.1may be included within a variety of system configurations, one example of which is shown inFIG.12. In various embodiments, system1200may correspond to a general-purpose computer system, such as a desktop or portable computer, a mobile phone, or the like. System1200may also correspond to any type of embedded system that may employ one or more instances of processor circuit102as a dedicated controller. For example, system1200may correspond to any type of computer peripheral device such as a mass storage device or storage array, printer, or the like, as well as control systems for automobiles, aviation, manufacturing, and other suitable applications.

As shown, system1200includes processor circuit1202, memory1210, storage1220, and an input/output (I/O) device interface1230coupled via an interconnect1240. One or more I/O devices1250are coupled via I/O device interface1230. System1200also includes a network interface1260that may be configured to couple system1200to a network1270for communications with, e.g., other systems. (In various embodiments, network interface1260may be coupled to interconnect1240directly, via I/O device interface1230, or according to a different configuration.) It is noted that some or all of the components of system1200may be fabricated as a system-on-a-chip, although discrete combinations of components may also be employed.

Processor circuit102may include an instruction storage circuit as disclosed above. Memory1210may include random-access memory (RAM) of any suitable configuration, such as working memory configured to store data and instructions usable by processor circuit102. Storage1220may include mass storage devices such as magnetic, optical, or nonvolatile/flash memory storage, or a combination of these. In some embodiments, either of memory1210or storage1220may be omitted or integrated into the other as a single memory subsystem from the perspective of processor circuit102.

I/O device interface1230may be configured to interface between interconnect1240and one or more other types of buses or interfaces. For example, interconnect1240may correspond to the AHB interface discussed above (or another suitable type of high-bandwidth interconnect), and I/O device interface1230may be configured as a bridge device that enables coupling of different types of I/O devices to interconnect1240. I/O device interface1230may implement one or more interface protocols such as Universal Serial Bus, Firewire, or other suitable standards. I/O device(s)1250may include any suitable type of storage, network interface, user interface, graphics processing, or other type of device. Network1270, if present, may be any suitable type of wired or wireless communications network, such as an Internet Protocol (IP) addressed local or wide-area network, a telecommunications network, or the like. Network interface1260, if present, may be configured to implement any suitable network interface protocol needed for communication with network1270.

Turning now toFIG.13, various types of systems that may include any of the circuits, devices, or systems discussed above are illustrated. System or device1300, which may incorporate or otherwise utilize one or more of the techniques described herein, may be utilized in a wide range of areas. For example, system or device1300may be utilized as part of the hardware of systems such as a desktop computer1310, laptop computer1320, tablet computer1330, cellular or mobile phone1340, or television1350(or set-top box coupled to a television).

Similarly, disclosed elements may be utilized in a wearable device1360, such as a smartwatch or a health-monitoring device. Smartwatches, in many embodiments, may implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device may also be designed solely to perform health-monitoring functions such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to an emergency medical service, etc. Other types of devices are also contemplated, including devices worn on the neck, devices implantable in the human body, glasses or a helmet designed to provide computer-generated reality experiences such as those based on augmented and/or virtual reality, etc.

System or device1300may also be used in various other contexts. For example, system or device1300may be utilized in the context of a server computer system, such as a dedicated server or on shared hardware that implements a cloud-based service1370. Still further, system or device1300may be implemented in a wide range of specialized everyday devices, including devices1380commonly found in the home such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Elements may also be implemented in various modes of transportation. For example, system or device1300could be employed in the control systems, guidance systems, entertainment systems, etc. of various types of vehicles1390.

The applications illustrated inFIG.13are merely exemplary and are not intended to limit the potential future applications of disclosed systems or devices. Other example applications include, without limitation: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.