SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

The present disclosure provides a semiconductor memory device and a fabricating method thereof, which includes a substrate, a plurality of buried word lines, and a plurality of storage node contacts. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are embedded in the substrate, across the shallow trench isolation and the active areas. The storage node contacts directly contact the active areas and include a plurality of first plugs, with each first plug including an insulating material and a conductive material stacked sequentially from bottom to top. Within the semiconductor memory device, at least one active area simultaneously contacts two of the first plugs, or a storage node pad physically contacts at least two of the first plugs. Thus, the present disclosure is beneficial on forming the semiconductor memory device with better component reliability.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to a semiconductor device and a method of fabricating the same, in particular to a semiconductor memory device and a method of fabricating the same.

2. Description of the Prior Art

With the trend of miniaturization of various electronic products, the design of dynamic random access memory (DRAM) having recessed gate structures must meet the requirements of high integration and high density. For a DRAM cell having recessed gate structures, because the carrier channel of which is relatively long in the same semiconductor substrate compared with that of the DRAM without recessed gate structures, the leakage current from the capacitor structure in the DRAM can be reduced. Therefore, the DRAM having recessed gate structures has gradually replaced DRAM having planar gate structures under the current mainstream development trend. Generally, the DRAM cell having recessed gate structure may include a transistor element and a capacitor element connected in series, which is configured to receive voltage information from word lines (WL) and bit lines (BL). However, due to the limitation of fabricating technology, the existing DRAM cell having recessed gate structure still have many defects, and the present technology needs further improvement to effectively improve the efficiency and reliability of related memory devices.

SUMMARY OF THE INVENTION

One of the objectives of the present disclosure provides a semiconductor memory device and a method of fabricating the same, in which a plurality of storage node contacts and a plurality of dummy storage node contacts are respectively formed within a dense region and an iso region of the semiconductor memory device, so that the same luminous flux is maintained in two different regions while performing a photolithography process, which is beneficing on improving the fabricating yield of the semiconductor memory device. Accordingly, the dummy storage node contacts are formed without performing additional fabricating processes, and the aforementioned structure defects possibly caused by the limited fabricating technology are improved, so as to form the semiconductor memory device with more reliable components under a simplified process flow.

To achieve the purpose described above, one embodiment of the present disclosure provides a semiconductor memory device including a substrate, a plurality of buried word lines, a plurality of storage node contacts, and a plurality of storage node pads. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are embedded in the substrate, across the shallow trench isolation and the active areas. The storage node contacts are disposed on the substrate and directly contacted the active areas, and the storage node contacts includes a plurality of first plugs, wherein the first plugs includes an insulating material and a conductive material stacked sequentially from bottom to top. The storage node pads are disposed on the storage node contacts, wherein one of the storage node pads physically contacts at least two of the first plugs.

To achieve the purpose described above, one embodiment of the present disclosure provides a semiconductor memory device, including a substrate, a plurality of buried word lines, and a plurality of storage node contacts. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are embedded in the substrate, across the shallow trench isolation and the active areas. The storage node contacts are disposed on the substrate to directly contacted the active area, the storage node contacts includes a plurality of first plugs, wherein each of the first plugs includes an insulating material and a conductive material stacked from bottom to top, and at least one of the active areas directly contacts two of the first plugs at the same time.

To achieve the purpose described above, one embodiment of the present disclosure provides a fabricating method of a semiconductor memory device, including the following steps. Firstly, a substrate is provided, and the substrate includes a plurality of active areas and a shallow trench isolation. Next, a plurality of buried word lines is formed in the substrate, with the buried word lines being embedded in the substrate and disposed on the shallow trench isolation or on the active areas. Then, a plurality of storage node contacts is formed on the substrate, to directly contact the active areas, and the storage node contacts includes a plurality of first plugs, wherein each of the first plugs includes an insulating material and a conductive material stacked from bottom to top. After that, a plurality of storage node pads is formed on the storage node contacts, wherein one of the storage node pads physically contacts at least two of the first plugs at the same time.

DETAILED DESCRIPTION

To provide a better understanding of the presented disclosure, preferred embodiments will be described in detail. The preferred embodiments of the present disclosure are illustrated in the accompanying drawings with numbered elements. In addition, the technical features in different embodiments described in the following may be replaced, recombined, or mixed with one another to constitute another embodiment without departing from the spirit of the present disclosure.

Please refer toFIG.1toFIG.8, which are schematic diagrams illustrating a fabricating method of a semiconductor memory device100according to the first embodiment of the present disclosure. Firstly, as shown inFIG.1, the semiconductor memory device100for example includes a substrate110, such as a silicon substrate, a silicon-containing substrate (for example including a material like SiC, SiGe), or a silicon-on-insulator (SOI) substrate, and the substrate110further includes a memory cell region110A being relative higher integrity and a periphery region110B being relative lower integrity, disposed thereon. Preferably, the periphery region110B is for example disposed on at least one side of the memory cell region110A. For example, if being viewed from a top view (not shown in the drawings), the outer periphery of the memory cell region100A may be entirely surrounded by the periphery region110B, but not limited thereto.

Further in view ofFIG.1, at least one shallow trench isolation (STI)120is formed in the substrate110, to define a plurality of active areas130in the substrate110, so that, the active areas130may be surrounded by the shallow trench isolation120. The active areas130further include active areas131formed within the memory cell region110A and active areas133formed within the periphery region110B. Preferably, the active areas131and the active areas133include different extending lengths, and the active areas133include a relative greater extending length, but not limited thereto. In one embodiment, the formation of the shallow trench isolation120may be accomplished by firstly performing an etching process to form a plurality of trenches (not shown in the drawings) in the substrate110, within the memory cell region110A and the periphery region110B, followed by filling an insulating material such as silicon oxide or silicon oxynitride in the trenches, and the shallow trench isolation120is formed after performing a planarization process, but not limited thereto.

Furthermore, a plurality of buried gate structures140is formed in the substrate110, with each of the buried gate structures140includes a dielectric layer142, a gate dielectric layer143, a gate electrode144, and a capping layer145stacked from bottom to top, wherein the surface of the capping layer145of each buried gate structure140may be coplanar with the top surface of the substrate110, with the buried gate structures140being serve as buried word lines (WLs) of the semiconductor device100for receiving or transmitting the voltage signals from each memory cell (not shown in the drawings). In one embodiment, the formation of the gate structures140includes but not limited to the following steps. Firstly, a plurality of trenches141is formed in the substrate110, then, the dielectric layer142covering the entire surfaces of each trench141, the gate dielectric layer143covering the bottom surfaces of each trench141, and the gate electrode144filling in the bottom of each trench141are sequentially formed, and the capping layer145filling in the top of each trench141is formed after etching back a portion of the gate electrode144and the gate dielectric layer143. It is noted that, the gate structures140formed within the memory cell region110A are sequentially arranged by the same pitch P1, to simultaneously intersect with the active areas131and the shallow trench isolation120, and the gate structures140formed within the periphery region110B are sequentially arranged by a relative greater pitch P2(the pitch P2being greater than the pitch P1), to simultaneously intersect with the active areas133and the shallow trench isolation120.

Although the entire extending directions of the active areas130(including the active areas131and the active areas133), and the gate structures140are not precisely illustrated in the drawings of the present embodiment, people well-skilled in the art should fully realizes that if being viewed from a top view (not shown in the drawings), each of the active areas131,133is extended along a first direction (not shown in the drawings), to together arrange in an array arrangement in the memory cell region110A and the periphery region110B, and each gate structure140is parallelly extended with each other along a second direction (not shown in the drawings), across the active areas131,133and the shallow trench isolation120, with the second direction being crossed but not perpendicular with the first direction. In one embodiment, the active areas133may further include a first portion (not shown in the drawings) extending along the second direction and a second portion (not shown in the drawings) extending along a third direction (not shown in the drawings) being perpendicular with the second direction, to present in a rectangular shape or other suitable shapes surrounding outside the periphery of the active areas131. With these arrangements, the first portion and the second portion of the active areas133may perform like a protecting structure, and the structural collapse or damage of the active areas131within the memory cell region110A may be successfully avoided.

Next, a plurality of bit line contacts (BLC, not shown in the drawings) is formed in the substrate110, and a plurality of bit lines (BL, not shown in the drawings), a dielectric layer147, and an insulating layer150filled in the gaps between the bit lines are formed on the substrate110. The bit lines are parallelly and separately extended along the third direction, to intersect with the buried word lines (namely, the gate structures140) and the active areas131within the memory cell region110A, and the bit line contacts and the bit lines may be monolithic, with the bit line contacts directly contacting the active areas131respectively for receiving and transmitting the voltage signals from the memory cell. In one embodiment, each of the bit lines for example includes a semiconductor layer (for example including polysilicon, not shown in the drawings), a barrier layer (for example including titanium and/or titanium nitride, not shown in the drawings), a conductive layer (for example including a low-resistant metal like tungsten, aluminum, or copper, not shown in the drawings), and a capping layer (for example including silicon oxide, silicon nitride, or silicon oxynitride, not shown in the drawings), the dielectric layer147preferably includes a multilayer structure for example including an oxide-nitride-oxide (ONO, not shown in the drawings) structure, and the insulating layer150for example includes an insulating material like silicon oxide, or silicon oxynitride, but is not limited thereto.

As shown inFIG.2, a mask layer (not shown in the drawings) is formed on the insulating layer150, and an etching process such as a dry etching process is performed through the mask layer, to form a plurality of openings151,153,155which are penetrated through the insulating layer150and the dielectric layer147. The openings151,153,155are sequentially arranged for example by the same pitch P3, and preferably the pitch P3is the same as the pitch P1and is smaller than the pitch P2, but is not limited thereto. Precisely speaking, since the openings151formed within the memory cell region110A have substantially the same pitch as that of the gate structures140(the pitch P3is the same as the pitch P1), the openings151within the memory cell region110A are right in alignment with the gate structures140disposed in the substrate110, with the capping layer145of the gate structures140being exposed from the openings151respectively.

On the other hand, since the gate structures140formed within the periphery region110B have a relative greater pitch (namely, the pitch P2), the openings153,155formed within the periphery region110B are not in alignment with the gate structures140within the periphery region110B, with only a portion of the openings153exposing the entire covering layer145, and the rest of the openings153,155only partially exposing the surfaces of the active areas133, partially surface of the gate structures140, or the shallow trench isolation120. Also, since there is a relatively smaller or the same etching selectivity between the materials of the insulating layer150and the shallow trench isolation120, and there is a relatively greater etching selectivity between the materials of the insulating layer150and the capping layer145, each of the openings155is capable of penetrating the surface of the shallow trench isolation120and extending downwardly into a portion of the shallow trench isolation120, in particular to the shallow trench isolation120within the periphery region110B, and each of the openings151,153is only capable of extending to the surfaces of the capping layer145or the active areas133, as shown inFIG.2. In other words, the formation of the openings155is mainly caused by an excessively etching performance during the etching process, and the etching profiles in the openings155are all diverse, so that the openings155may obtain the bottom surfaces with different heights.

As shown inFIG.3, a deposition process and an etching back process are sequentially performed to form a plurality of insulating spacers161,163,165filled up the openings151,153,155respectively, with each of the insulating spacers161,163,165extending along the third direction, between each of the bit lines. The insulating spacers161formed within the memory cell region110A respectively contact the covering layer145of the gate structures140, and the insulating spacers163,165formed within the periphery region110B respectively contact the surfaces of the active areas133or the shallow trench isolation120. It is noted that, as controlling the parameters like the opening size, the opening spacing, the etching time, and the position of the openings in the peripheral region110B in the present embodiment, the insulating spacers165formed within the peripheral region110B are further extended into the portion of the shallow trench isolation120, thereby dramatically increasing the aspect ratio of the openings, as well as the difficulty of etching the openings and backfilling the insulating material. Accordingly, the insulating spacers165may therefore obtain the bottom surfaces with different heights, as shown inFIG.3.

As shown inFIG.4, a mask layer170is formed on the insulating layer150and the insulating spacers161,163,165, covering on the insulating layer150and the insulating spacers163,165within the periphery region110B, so that, the insulating layer150and the insulating spacers161within the memory cell region110A are completely exposed from the mask layer170, and the insulating spacers163closed to the memory cell region110A and the insulating layer150at two sides thereof are partially exposed from the mask layer170. Then, an etching process such as a wet etching process is performed through the mask layer170, to completely remove the insulating layer150and the dielectric layer147within the memory cell region110A, and a plurality of openings152is formed accordingly, to expose the surfaces of the active areas131, and also, a plurality of openings154is formed at the same time due to partially removing the insulating layer150at two sides of the insulating spacers163which is closed to the memory cell region110A. After that, a selective epitaxial growth (SEG) process is performed also through the mask layer170, to form a plurality of epitaxial layers181on the exposed surface of the active areas131, and the mask layer170is removed then. In one embodiment, the epitaxial layers181for example include a conductive material such as silicon (Si), silicon phosphide (SiP), silicon germanium (SiGe), or germanium (Ge), but not limited thereto.

It is noted that due to the various integration degrees between the memory cell region110A and the peripheral region110B, the micro loading effect is easily occurred on the openings154within the periphery region110B and closed to the memory cell region110A, through controlling the parameters like the size of the openings154, the spacing and the size of the insulating spacers163,165, and the etching time, so as to result in the incompletely etching profiles during the etching process. Accordingly, the insulating spacers163closed to the memory cell region110A, as well as the insulating layer150at two sides thereof, are only partially removed, without exposing the surfaces of the active areas133underneath, and without forming any epitaxial layer during the SEG process. In addition, since the various etching degrees during the etching process, the remained insulating layer150at two sides of the insulating spacers163may obtain the top surface with different heights, and also an uneven etching surface150aaccordingly, as shown inFIG.4.

As shown inFIG.5, a deposition process is performed on the substrate110, to form a conductive material layer190filling in the openings152,154and further covering on the top surfaces of the insulating spacers161,163,165and the insulating layer150. In one embodiment, the conductive material layer190for example includes a conductive material like tungsten, titanium, or copper, but is not limited thereto. In one embodiment, a barrier layer (not shown in the drawings) may be firstly formed before forming the conductive material layer190, with the barrier layer for example including a material like titanium/titanium nitride (TiN), tantalum (Ta)/tantalum nitride (TaN), but not limited thereto. Then, a mask layer200is formed on the conductive material layer190, and the mask layer200includes a plurality of mask patterns201,203. Precisely speaking, the mask patterns201formed within the memory cell region110A include a relative smaller width and pitch, which are respectively in alignment with the conductive material layer190filled in each opening152, and the mask patterns203formed within the periphery region110B include a relative greater width and pitch, so as to reduce the difference of pattern integration between the memory cell region110A and the periphery region110B. Accordingly, each of the mask patterns203is capable of simultaneously covering the conductive material layer190filled in all of the openings154, or simultaneously covering more than one of the insulating spacers165and the insulating layer150at two sides thereof, as shown inFIG.5.

Following these, an etching process such as a dry etching process is performed through the mask layer200, to pattern the conductive material layer190covered on the top surfaces of the insulating spacers161,163,165and the insulating layer150, and to expose the top surfaces of the insulating spacers161,163,165and the insulating layer150underneath, and the exposed insulating spacers161,163,165and the insulating layer150are removed. Then, the mask layer200is removed. Accordingly, as shown inFIG.6, a plurality of conductive layers191,192is formed in the openings152,154respectively, and also, a plurality of conductive pads193,195is formed over the conductive layers191,192. It is noted that, the conductive layers191, and the conductive pads195formed within the memory cell region110A are sequentially stacked on the epitaxial layers181, and the epitaxial layers181and the conductive layers191both include the conductive materials may together form a plurality of plugs211. The plugs211is disposed between the adjacent ones of the insulating spacers161and the buried word lines (namely, the gate structures140) and include the top surface which is higher than that of the insulating spacers161, so that, the plugs211may physically contact the conductive pads193hereabove, and the active areas131underneath. Through these arrangements, the plugs211may be electrically connected to the transistors disposed within the active areas131via the epitaxial layers181disposed at the bottom, and electrically connected to a capacitor formed in the subsequent process via the conductive pads193disposed at the top.

On the other hand, the conductive layers192disposed within the periphery region110B are stacked on the etching surface150aof the insulating layer150, and the insulating material (namely, the insulating layer150) and the conductive material (namely, the conductive layer192) stacked sequentially between the adjacent ones of the insulating spacers163together form a plurality of plugs213, to physically contact the active areas133underneath. The plugs213have the top surface which is the same or higher than the top surface of the insulating spacers163, wherein a portion of the plugs213is not completely located between the adjacent ones of the buried word lines, and even partially overlapped with the buried word lines in the direction perpendicular to the substrate110. Accordingly, the plugs213may not be electrically connected with the transistor within the active areas133, and at least two of the plugs213are physically contacted with the same one of the conductive pads195at the same time, to serve as dummy plugs. In the present embodiment, all of the plugs213are physically connected to the same one of the conductive pads195, as shown inFIG.6, but not limited thereto. Also, the rest of the conductive pads195disposed within the periphery region110B are physically contacted to the insulating spacers165and/or the insulating layer150over the shallow trench isolation120at the same time, so that, the insulating layer150disposed between the adjacent ones of the insulating spacers165, over the shallow trench isolation120also form a plurality of dummy plugs215, as shown inFIG.6.

As shown inFIG.7, a deposition process is performed on the substrate110to form an insulating material layer220, conformally covering on the top surfaces of the conductive pads193,195to fill up the spaces between the conductive pads193and to partially fill in the spaces between the conductive pads195. In one embodiment, the insulating material layer220for example includes an insulating material like silicon nitride or silicon carbonitride, and preferably includes an insulating material which is the same as that of the insulating spacers161,163,165, but not limited thereto.

Following these, as shown inFIG.8, an etching back process is performed to remove the insulating material layer220covered on the top surface of each of the conductive pads193,195, to form an insulating layer221filled in the space between the conductive pads193, and an insulating layer223filled in the space between the conductive pads195. The insulating layer221formed within the memory cell region110A have the top surface being coplanar with the top surfaces of the conductive pads193,195, and which may directly contact the insulating spacers161underneath. The insulating layer223formed within the periphery region110B have a relative lower, sunken top surface which is not coplanar with the top surface of the conductive pads195, and which may also directly contact the insulating spacers163,165underneath. Based on above-mentioned processes, the semiconductor memory device100of the first embodiment in the present disclosure is accomplished.

According to the first embodiment of the present disclosure, the semiconductor memory device100includes the buried word lines (namely, the gate structures140) embedded in the substrate110, the plugs211,213,215and the insulating spacers161,163,165disposed on the substrate110, wherein the insulating spacers161,163,165and the plugs211,213,215are alternately arranged with each other on the substrate110. It is noted that, each of the plugs211,213,215are configured as storage node contacts (SNCs) of the semiconductor memory device100, and the conductive pads193,195are configured as storage node pads (SN pads) of the semiconductor memory device100, to be disposed on the storage node contacts for electrically connecting thereto. Precisely speaking, each of the plugs211includes the epitaxial layer181(including the conductive material) and the conductive layer191(including the conductive material) stacked sequentially, for electrically connecting to the transistor within the substrate110, and the plugs211maybe further electrically connected to the capacitor via the conductive pads193hereabove, thereby forming the smallest memory cell of the semiconductor memory device100for receiving or transmitting required signals.

On the other hands, each of the plugs213included the insulating layer150(including the insulating material) and the conductive layer192(including the conductive material) stacked sequentially, and the plugs215are completely formed by the insulating layer150(including the insulating material), with two or more than two of the plugs213simultaneously contacting the active areas133, and/or the storage node pads (namely, the conductive pads195), and with the plugs215directly contacting the shallow trench isolation120. Accordingly, both of the plugs213,215may not be electrically connected to any transistor, so as to serve as the dummy plugs thereby. In other words, the fabricating method of the present disclosure easily leads to micro loading effect or incompletely etching issues in the etching process due to the various component densities between the memory cell region110A and the peripheral region110B of the semiconductor memory device100, so as to form the dummy storage node contacts within the periphery region110B under a simplified process flow. With these performances, the dummy storage node contacts may be formed without performing additional fabricating processes, and also, the low yield issue caused by low component density in the peripheral region110B may be improved, accordingly.

Furthermore, it is also noted that each of the insulating spacers161are formed above the gate structures140to in alignment with thereto, and however, the insulating spacers163are not in alignment with the gate structure140within the periphery region110B (having the relative greater pitch P2) underneath. Then, the insulating spacers163are disposed over the active areas133, or only partially overlapped with the gate structures140underneath. With these arrangements, the process tolerance or process window of components within the periphery region110B is dramatically improved, to prevent the micro loading effect or the etching defects caused by the various component densities from negatively affecting the overall structure of the semiconductor memory device100, which is beneficial on achieving more optimized structural integrity and efficiency.

However, people well known in the arts should easily realize the semiconductor memory device and the fabricating method thereof in the present disclosure is not limited to the aforementioned embodiment, and may further include other examples or variety. The following description will detail the different embodiments of the semiconductor memory device and fabricating method thereof in the present disclosure. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.

Please refer toFIG.9, which is a schematic diagram illustrating a fabricating method of a semiconductor memory device300according to the second embodiment of the present disclosure. The fabricating method of the semiconductor memory device300in the present embodiment are substantially the same as those of the semiconductor memory device100in the aforementioned first embodiment, and all the similarities will not be redundantly described herein after. The difference between the present embodiment and the aforementioned first embodiment is in that after forming the epitaxial layers181(for example being shown inFIG.4of the first embodiment), another etching process such as a wet etching process is performed, to further remove the insulating layer150closed to the memory cell region110A, to expose the dielectric layer147underneath. Then, the subsequent processes are continuously performed as shown inFIG.5toFIG.8of the aforementioned first embodiment, and the semiconductor memory device300of the second embodiment in the present disclosure is therefore accomplished based on above-mentioned processes.

It is noted that, due to the various integration degrees between the memory cell region110A and the peripheral region110B, the incompletely filling issue is easily occurred in the periphery region110B closed to the memory cell region110A while performing the deposition process of the conductive material layer190(as being shown inFIG.5of the aforementioned first embodiment), thereby forming a plurality of air gaps310. The air gaps310have the top surfaces with different heights, or even have uneven surfaces310a, as shown inFIG.9. Then, the conductive layer192is formed sequentially on the air gaps310within the periphery region110B, and the air gaps310(including an insulating material) and the conductive layer192(including the conductive material) will together form a plurality of plugs313.

In another embodiment, plugs (not shown in the drawings) may also by formed by sequentially stacking the insulating layer150, the air gaps, and the conductive layer192. In addition, in another embodiment, the air gap of plugs (not shown in the drawings) may further extend into a portion of the substrate110because a portion of the substrate110may be further removed during performing the another etching process to remove the insulating layer150closed to the memory cell region110A. Then, the air gap formed under the conductive layer192may therefore obtain a bottom surface with a step-height not shown in the drawings).

In the present embodiment, two or more than two of the plugs313simultaneously contact the active areas133and/or the storage node pads (namely, the conductive pads195), without electrically connecting to any transistor, to serve as the dummy plugs thereby. Thus, the fabricating method of the present embodiment also forms the dummy storage node contacts without performing additional fabricating processes, and the low yield issue of the semiconductor memory device300caused by low component density in the peripheral region110B may be improved.

Please refer toFIG.10, which is a schematic diagram illustrating a fabricating method of a semiconductor memory device400according to the third embodiment of the present disclosure. The fabricating method of the semiconductor memory device400in the present embodiment are substantially the same as those of the semiconductor memory device100in the aforementioned first embodiment, and all the similarities will not be redundantly described herein after. The difference between the present embodiment and the aforementioned first embodiment is in that the etching process of the insulating layer150(for example as shown inFIG.4of the aforementioned first embodiment) is performed through another mask layer (not shown in the drawings), to completely remove the insulating layer150within the memory cell region110A, to partially remove the insulating layer150at two sides of the insulating spacers163, and to partially remove the insulating layer150at two sides of the insulating spacers165. Then, the subsequent processes are continuously performed as shown inFIG.5toFIG.8of the aforementioned first embodiment, to form the epitaxial layers181and other required elements, and the semiconductor memory device400of the third embodiment in the present disclosure is accomplished based on the aforementioned processes.

It is noted that, due to the various integration degrees between the memory cell region110A and the peripheral region110B, the insulating layer150is incomplete etched by controlling the etching parameters like the opening size, the opening spacer, or etching time, to obtain the top surfaces with different heights or uneven etching surfaces350a, as shown inFIG.10. Accordingly, each conductive layer492formed subsequently in the periphery region110B is stacked on the etching surface350aof the insulating layer150, and the insulating layer150(for example including the insulating material), and the conductive layer492(for example including the conductive material) stacked sequentially will together form a plurality of plugs415to directly contact the shallow trench isolation120underneath. Also, two or more than two of the plugs415may contact to the storage node pads at the same time, and which cannot be electrically connected to any transistor, so as to serve as the dummy plugs, as shown inFIG.10. In this way, the fabricating method of the present embodiment also forms the dummy storage node contacts without performing additional fabricating processes, and also, the low yield issue of the semiconductor memory device400caused by low component density in the peripheral region110B may be improved, accordingly.

Overall speaking, the semiconductor memory device of the present disclosure includes a plurality of storage node contacts and a plurality of dummy storage node contacts respectively disposed in a dense region and an iso region with various component densities, so that the same luminous flux is maintained in two different regions during performing photolithography process, which is beneficing on improving the fabricating yield of the semiconductor memory device. Also, the dummy storage node contacts are formed mainly based on the micro loading effect or the incompletely etching issues caused by the aforementioned various integration degrees, without leading to additional fabricating processes. Thus, the fabricating method of the present disclosure is allowable to form the semiconductor memory device with more reliable components, to gain better performance.