Mechanism for proxy management of multiprocessor virtual memory

A method and apparatus within a computer processing environment is provided for proxy management of a plurality of memory management units connected to a plurality of processing elements or cores within a unified memory environment. The proxy management system includes a proxy processor, such as a RISC core, and proxy memory management units that translate virtual memory requests generated by each of the processing elements into physical address. If the virtual memory requests can be translated directly into a physical address, then the translation is performed and the memory request proceeds. However, if the virtual address cannot be translated into a physical address by the proxy memory management unit, then the unit alerts the proxy processor to perform a page table lookup to locate the physical address. The lookup updates the table in the proxy memory management unit and the memory access proceeds. Such lookup is transparent to the processing element that generated the memory access.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 10/186,330 entitled “MECHANISM FOR PROXY MANAGEMENT OF MULTIPROCESSOR STORAGE HIERARCHIES”, by Kevin D. Kissell, and filed on the same date as the present application.

FIELD OF THE INVENTION

This invention relates in general to the field of computer architecture, and more specifically to a method and apparatus for proxy management of virtual memory within a system-on-chip (SoC) environment.

BACKGROUND OF THE INVENTION

Embedded microprocessor based systems typically include a number of components including: a microprocessor for executing instructions; read-only memory (ROM) for storing instructions; random-access memory (RAM) for storing instructions and data; as well as an interface to various input/output (I/O) devices such as a display, keyboard, serial connector, Ethernet, etc. An example of such an embedded system is shown inFIG. 1to which attention is now directed.

FIG. 1contains a block diagram100illustrating a processing element102coupled to a memory management unit (MMU)104. The memory management unit104is coupled to a cache106which is coupled to a memory108. In operation, the processing element102presents an address for instructions (or data) that is to be read from the memory108to the cache106. If the cache106contains the instructions/data at the presented address, the instructions/data are provided to the processing element102without interfacing to the memory108. However, if the cache106does not contain the instructions/data at the presented address, the address is provided to the memory108for retrieval of the instructions/data. One skilled in the art will appreciate that the MMU104translates a virtual address provided by the processing element102into a physical address for the cache106(for a physically tagged cache) and for the memory108.

More complex systems often contain multiple microprocessors (e.g., digital signal processors, graphics processors, etc.), each with their own memory systems, and often of different architecture (i.e., executing different instruction sets). Referring toFIG. 2a block diagram200is shown having N number of processing elements202,204and206, each with their own memory system208,210, and212, respectively. Early multiprocessor systems, such as is shown inFIG. 2, were implemented using different chips, mounted on a printed circuit board, and interconnected with signal lines on the printed circuit board. However, modern implementations are moving towards providing an entire system on a chip (SoC), as designated by dashed line201. That is, a design engineer utilizes existing processing cores (elements), and existing memory structures to design multiprocessor SoC's for particular applications. Such SoC's allow for miniaturization of multiprocessing systems, and thus provide a lower cost alternative to the multi-chip, printed circuit board designs.

As shown inFIG. 2, when a SoC design requires multiple processing elements, of the same or different architecture, existing designs have chosen to support such processing elements by providing separate memory systems, and I/O device maps for each processing element. But, as the number of processing elements increases, so has the number of independent memory systems. However, the proliferation of independent memory systems is probably not the most economical solution. Multiple, large memory systems being accessed in parallel consume undesirable amounts of current. In addition, when providing independent memory systems for each processing element, the amount of memory that must be provided is the sum of the maximum runtime needs of each processing element. Memory in SoC's takes up considerable space on the chips, and thus adds to the cost of manufacture, as well as runtime cost of the chips.

Therefore, what is needed is a memory management system for SoC's that allows a unified memory system to be utilized by multiple processing elements using a virtual memory system.

SUMMARY

The present invention provides a method and apparatus for proxy management of intermediate caches between processing elements and a unified memory where the processing elements may be homogeneous or heterogeneous.

In one aspect, the present invention provides a proxy management system for virtual memory, within a computing system having a number of processing elements. The proxy management system includes a proxy processor, and a number of proxy memory management units. The proxy processor executes proxy management procedures. The proxy memory management units are coupled to the proxy processor, and are associated with at least one of the processing elements. The proxy memory management units convert virtual addresses received from their associated processing elements into physical addresses. If one of the proxy memory management units is unable to convert a virtual address into a physical address, it notifies the proxy processor causing the proxy processor to execute proxy management procedures to establish a correct physical address mapping for the virtual address.

In another aspect, the present invention provides a computing system including processing elements, a unified memory, proxy memory management units and a proxy processor. The processing elements execute processing instructions associated with their architecture. The unified memory is coupled to the processing elements and stores processing instructions for the processing elements. The proxy memory management units are coupled to associated processing elements, to receive virtual addresses generated by the processing elements, and to convert the received virtual addresses into physical addresses. The proxy processor is coupled to the proxy memory management units, to receive TLB miss signals from the proxy memory management units when the proxy memory management units cannot convert a virtual address into a physical address. If one of the memory management units cannot convert a virtual address into a physical address, the proxy processor executes proxy management procedures to establish a correct physical address mapping for the virtual address.

In yet another aspect, the present invention provides a method for proxy management of virtual memory within a computing environment, the environment having processing elements each having a proxy memory management unit, all of the proxy memory management units coupled to a unified memory. The method includes: generating a memory request from one of the processing elements to its associated proxy memory management unit using a virtual address; translating the virtual address to a physical address using the associated proxy memory management unit; and if the step of translating is successful, completing the memory request; but if the step of translating is not successful, alerting a proxy processor that a miss has occurred within the associated proxy memory management unit; updating the proxy memory management unit; and replaying the steps of generating, translating and completing.

In a further aspect, the present invention provides a computer program product for use with a computing device. The computer program product includes a computer usable medium, having computer readable program code embodied in the medium, for causing a proxy memory management system for virtual memory to be provided, the system having processing elements. The computer readable program code includes: first program code for providing a proxy processor for executing proxy memory management procedures; and second program code for providing a proxy memory management units, coupled to the proxy processor, each associated with a processing element, the proxy memory management units for converting virtual addresses received from their associated processing elements into physical addresses. If a proxy memory, management unit is unable to convert one of the virtual addresses into a physical address, the proxy memory management unit notifies the proxy processor causing the proxy processor to execute proxy management procedures to retrieve a correct physical address for the virtual address.

In another aspect, the present invention provides a computer data signal embodied in a transmission medium including computer-readable program code for providing a system on a chip. The program code includes: first program code for providing processing elements, each for executing processing instructions associated with its architecture; second program code for providing a plurality of proxy memory management units, each coupled to a processing element; third program code for providing a unified memory, coupled to a proxy memory management unit; for storing processing instructions for the processing elements; and fourth program code for providing a proxy processor, coupled to proxy memory management units, to translate virtual addresses generated by the processing elements into physical addresses; If a proxy memory management unit cannot convert a virtual address into a physical address, the memory management unit notifies the proxy processor causing the proxy processor to retrieve a physical address.

Other features and advantages of the present invention will become apparent upon study of the remaining portions of the specification and drawings.

DETAILED DESCRIPTION

The inventor of the present application has recognized the need for utilizing a unified memory structure for processing elements within a SoC design where the processing elements may be homogeneous or X heterogeneous. He has therefore developed a proxy memory management system as will be further described below with respect toFIGS. 3–8.

The phrase “proxy storage management” refers to the use of hardware and software, executing on a proxy processor to implement a SoC-wide hierarchical memory system transparently on behalf of other processing elements. In one embodiment, the inventor has utilized a MIPS RISC core, from MIPS Technologies, Inc., Mountain View, Calif., although other cores are envisioned. Proxy storage management includes both cache management and virtual memory management.

Cache Management

Sharing common RAM and ROM resources across multiple processing elements reduces the bandwidth available to each processing element and generally increases the memory latency between a processing element and memory. The increased latency is adverse to performance and is often intolerable. Therefore, existing multiprocessor systems typically utilize cache memories (or other intermediate memories) that are dedicated to each processing element to cache portions of the main memory and therefore improve the memory bandwidth and latency as seen by each processing element. However, in such multiprocessor systems, caches also create problems since it becomes possible for two different processing elements to believe that the same memory location contains two different values. In multi-chip, multiprocessing environments, sophisticated cache coherency mechanisms have been designed to insure data coherency across multiple caches. However, the processing elements in such systems are homogeneous (i.e., they execute the same instruction set), and must be designed to implement a particular coherency system. Because of this complexity, most existing SoC processing elements do not implement cache control at all, much less a mechanism to insure that the contents of the caches are coherent within a multiprocessor system.

Referring now toFIG. 3, a block diagram300is shown of a proxy management system302according to the present invention. The proxy management system302includes a proxy processor304coupled to a cache305, which is configured to store instructions/data for the proxy processor304. The cache305is coupled to a unified memory310. Additional processing elements (PE)306are also provided, which are coupled to one or more associated proxy caches308, which in turn are coupled to both the proxy processor304via command lines311, and the unified memory310. One skilled in the art will appreciate that a number of processing elements306(such as vector processors, graphics processors, digital signal processors, etc.,) running the same or different instruction sets are indicated by the processing elements306.

The proxy processor304is used to execute general system management instructions (operating system instructions) for the system-on-a-chip (SoC) that includes the processing elements306and the proxy caches308. In addition, it implements proxy management software procedures to control the proxy caches308. Such procedures include: flush; lock; migrate; initialize; prefetch; invalidate; set value; etc, for the proxy caches308coupled to the processing elements306. Thus, the proxy processor304executes proxy instructions that specify: 1) which proxy cache308is targeted; 2) what operation is to be performed; and 3) what physical/virtual addresses are to be affected.

In one embodiment, coherency between the proxy caches308is maintained by software algorithms that execute on the proxy processor304as part of the operating system. For example, if a first processing element306wished to transfer a block of data to a second processing element306, the operating system executing on the proxy processor would mediate the transfer. That is, the proxy processor304would know which data in the proxy cache308(associated with the first proxy element308) would be “dirty” and need to be written back to the unified memory310before transfer to the second proxy element308. In addition, the proxy processor304would know whether any “stale” data in the proxy cache308(associated with the second processing element306) would need to be invalidated before the ownership of the data block could be transferred. The proxy processor304therefore sends commands to the proxy caches308, such as flush, invalidate, etc. on command lines311to the proxy cache308requiring proxy management. The proxy cache308receiving the commands performs the desired function and notifies the proxy processor304upon completion. Thus, from the viewpoint of any one of the processing elements306, memory requests to the unified memory310, and thus to their associated proxy caches308, are transparently managed by the proxy processor304, without requiring either the processing elements306, or their associated proxy caches308to insure coherency between the proxy caches308. Such proxy management, as described above, provides a significant design advantage, because it allows a designer of an SoC to utilize existing heterogeneous processing elements306whether or not they have been designed to operate together, or to share a unified memory310. Of course, this proxy management could also be used with a plurality of homogeneous processing elements.

In an alternative embodiment, the proxy processor304monitors memory requests from each of the processing elements306to their associated proxy caches308, and maintains a lookup table307for each such request. The proxy processor304insures that requests made to the same area of memory by different processing elements306are not incoherent. Thus, when a processing element306performs a memory access request, the address of the request is provided to the associated proxy cache308, and to the proxy processor304for storage in the lookup table307. The lookup table307stores information regarding what addresses are stored in each of the proxy caches308, as well as information regarding the status of such addresses (e.g. shared, modified, invalid, etc). This allows the proxy processor304to insure data coherency across multiple proxy caches308. In the absence of such a “shadow” cache305describing the state of all the proxy caches308managed by the proxy processor304, the need for proxy cache intervention is determined by software algorithms running on the proxy processor304as part of the operating system (such as described above in the first embodiment).

By monitoring the allocation and use of memory in the system by the different processing elements306, and/or by interrogating a set of cache tags in the lookup table307, and executing proxy instruction such as those mentioned above, the proxy processor304effects transparency between the processing elements306and the unified memory310. That is, the proxy processor304causes the proxy caches308, ultimately, to appear as if they were the unified memory310, even though other processing elements306are also accessing the unified memory310. One skilled in the art will appreciate that such instructions insure coherency of data between multiple proxy caches308, effecting invalidate/write-back procedures, etc., as necessary. Further information related to such proxy cache instructions is provided below with reference toFIG. 6.

Referring now toFIG. 4, an alternative to the present invention can be implemented by utilizing a processing element specific cache408which is coupled to a proxy interface unit409between the proxy cache408and a proxy processor404. The proxy interface unit409includes the necessary interface (i.e., address/control information) to allow proxy commands to be transferred between the proxy processor404of the present invention, and a generic proxy cache408coupled to an associated generic processing element406. That is, a proxy cache408is provided that has characteristics specific to the needs of the processing element406. Thus, the present invention allows an SoC designer to utilize proprietary generic proxy caches coupled to processing elements306such as is described with reference toFIG. 3, or alternatively to utilize PE-specific proxy caches coupled to processing elements406, while interfacing to the proxy processor404via a well-defined proxy interface409.

Referring now toFIG. 6, a block diagram600is provided of an instruction format for execution on the proxy processor304described above. The instruction is designated XCACHE and is used within the MIPS instruction architecture, although a similar instruction is envisioned for other architectures. The address for a proxy cache operation is generated by adding the contents of general purpose registers rs and rt. The cache_id field identifies which proxy cache is targeted. In one embodiment, an all ones value in the cache_id field would indicate that the instruction is directed at all proxy cache controllers. The cacheop field indicates which cache operation is to be performed: prefetch, lock, write-back/invalidate, discard, etc. Execution of the instruction causes the address and requested cache operation to be communicated to the proxy cache identified by the instruction.

The XCACHE instruction600described above allows for 32 different proxy caches to be targeted, and allows for 32 distinct cache commands. One skilled in the art will appreciate that within the XCACHE instruction, one could increase the range of one of those parameters at the expense of the other. However, in alternative architectures, less or more commands/targets may be provided for.

Proxy Virtual Memory Management

A system wide virtual memory scheme is considered beneficial in a unified memory SoC system for several reasons. First, having all processing elements working on the same unified memory implies that, without some form of memory management, one processing element can corrupt the storage being used by another processing element. Second, some form of memory allocation scheme is desirable that can dynamically allocate the shared memory between the processing elements. A paged virtual memory system is considered appropriate because it can reduce or eliminate problems of memory fragmentation, and allow forms of demand paging. Third, by placing a virtual memory structure between a processing element and memory, the effective addressing range can be expanded for a processing element with a constrained logical/physical address space. The amount of memory addressable at any one time remains the same, but by changing the virtual memory mapping underneath the native logical/physical address space, that constrained address space can be made into a changeable “window” into a larger memory.

Most processing elements are specialized computational devices that do not have any means of managing a “page fault” or TLB miss. As with the proxy caches, the present invention uses a combination of a proxy processor, and software executing on the proxy processor to provide and manage an MMU on behalf of heterogeneous processing elements, in a manner that are transparent to the software executing on the heterogeneous processing elements.

Referring toFIG. 5, a block diagram500is shown that illustrates a proxy virtual memory management system502according to the present invention. The system502includes a proxy processor504coupled to its cache506, which is coupled to RAM516and ROM518via memory bus520. The proxy processor504is also coupled to a proxy cache/MMU510and a proxy cache/MMU514, associated with processing elements508and512, respectively. In one embodiment, the processing elements508,512do not execute the same instructions, but utilize the RAM516and ROM518as if they were attached to each directly.

To accomplish this, the processing elements508,512are connected, not directly to the RAM516and ROM518, but rather, to the proxy cache/MMU units510,514. In one embodiment, the units510,514are TLB based; translating the logical addresses provided by the processing elements508,512into physical addresses for interfacing to the unified memory system RAM516and ROM518.

Referring now toFIG. 7, a flow chart700is shown illustrating the methodology of the proxy virtual memory system illustrating inFIG. 5. Flow begins a block702when a memory access request is made by one of the processing elements508,512. Flow then proceeds to block704.

At block704, the proxy cache/MMU unit510,514that is associated with the processing element508,512making the request, translates the logical address presented by the processing element508,512into a physical address. In one embodiment, the address translation step is performed utilizing the logical address to index into a TLB within the proxy cache/MMU unit510,514. If the TLB contains a corresponding physical address, a TLB “hit” occurs, and flow proceeds to block706.

At block706, the proxy cache/MMU510,514performs a memory cycle with either the RAM516or ROM518depending on the physical address of the access. Flow then proceeds to block708.

At block708, the memory access is completed.

At block710, another memory access is made by one of the processing elements508,512. Flow then proceeds to block712.

At block712, the proxy cache/MMU510,514associated with the processing element making the request utilizes the virtual address to index into its TLB. However, for this access, the associated physical address is not in the TLB, i.e., a TLB “miss” occurs. Flow then proceeds to block714.

At block714, the proxy cache/MMU510,514generates a proxy TLB miss exception to the proxy processor504. Flow then proceeds to block716.

At block716, the proxy processor executes instructions to perform a page table lookup for the processing element virtual address that caused the TLB miss. The new TLB entry is loaded by the proxy processor504from the page table in memory corresponding to the current virtual address mapping of the PE508or512. Flow then proceeds to block718.

At block718, the TLB in the proxy cache/MMU510,514that generated the exception is updated by a write operation of the proxy processor504. Flow then proceeds to block720.

At block720, the memory access request from block710is replayed in the proxy cache/MMU510,514. Flow then proceeds to block722.

At block722, translation of the virtual address occurs, this time successfully because the proxy processor504has updated the table in the TLB. Flow then proceeds to block724.

At block724, the memory cycle is performed by the proxy cache/MMU510,514. Flow then proceeds to block726.

At block726, the memory access is completed.

In one embodiment, the present invention utilizes a combination of hardware and software to perform the proxy virtual memory management. Tasks performed by hardware are shown as rectangles inFIG. 7. Tasks performed by software are shown as ellipses inFIG. 7.

Referring now toFIG. 8, a block diagram800is shown illustrating the sequence of operations that are performed within the present invention when an illegal memory access, such as an attempt to write to a read-only memory page, is made by a processing element. Flow begins at block802when a processing element performs a memory access request. Flow then proceeds to block804.

At block804, the proxy cache/MMU, associated with the processing element making the request, looks up the virtual address in its TLB. Since the address is illegal, a TLB error occurs, causing flow to proceed to block806.

At block806, the proxy cache/MMU generates an exception to the proxy processor504. Flow then proceeds to block808.

At block808, the proxy processor504causes a page table lookup to occur for the virtual address. Flow then proceeds to block810.

At block810, the proxy processor confirms that the virtual address of the request is illegal for the processing element making the request. Flow then proceeds to blocks814and812.

At block812, the illegal memory cycle requested by the PE must be aborted. Depending on the design of the a PE, it may be necessary to provide the PE's memory interface logic with a “dummy” cycle handshake, or it may be possible to present it with a bus error or other memory access exception that will abort the suspended access. Flow then proceeds to block816.

At block814, the proxy processor executes an error handler routine which triggers whatever global operating system level “housekeeping” needs to be done in response to the error. This may include signaling an exception to the processing element making the request, resetting the PE, and communicating the fact of a failure to other PE's in the system. In more sophisticated PE's, an interrupt may be generated to cause the PE to execute error management procedures and resume operation.

At block816, the processing element receives the error indication. Flow then proceeds to block818.

At block818, the processing element executes an error handler that has been written to deal with illegal memory requests.

The above description with reference toFIGS. 3–8have illustrated alternative embodiments and a method for providing a proxy cache system, and a proxy memory management system for use in a multiprocessor environment. Although the present invention and its objects, features, and advantages have been described in detail, other embodiments are encompassed by the invention. In addition to implementations of the invention using hardware, the invention can be embodied in computer readable program code (e.g., software) disposed, for example, in a computer usable (e.g., readable) medium configured to store the code. The code causes the enablement of the functions, fabrication, modeling, simulation and/or testing, of the invention disclosed herein. For example, this can be accomplished through the use of computer readable program code in the form of general programming languages (e.g., C, C++, etc.), GDSII, hardware description languages (HDL) including Verilog HDL, VHDL, AHDL (Altera Hardware Description Language) and so on, or other databases, programming and/or circuit (i.e., schematic) capture tools available in the art. The code can be disposed in any known computer usable medium including semiconductor memory, magnetic disk, optical disc (e.g., CD-ROM, DVD-ROM, etc.) and as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., carrier wave or any other medium including digital, optical or analog-based medium). As such, the code can be transmitted over communication networks including the Internet and intranets. It is understood that the functions accomplished and/or structure provided by the invention as described above can be represented in a processor that is embodied in code (e.g., HDL, GDSII, etc.) and may be transformed to hardware as part of the production of integrated circuits. Also, the invention may be embodied as a combination of hardware and code.

Moreover, although the present invention has been described with reference to particular apparatus and method, other alternative embodiments may used without departing from the scope of the invention. For example, many variants are possible on the encoding and operational description above. For example, two registers are described to compute the address to be affected in the proxy cache, but none are used to return any information from the proxy cache/MMU. If some form of synchronization were needed, or if some kind of remote cache/MMU interrogation were desired, one of the GPR specifier fields could be used to indicate a destination register for data or status to be returned by the operation. Also, a number of programming interfaces to the proxy TLB are possible. It could be treated as an I/O device responding to a set of proxy processor memory addresses, as a separate coprocessor, or as an extension of the existing MIPS system coprocessor (i.e., COP0).

Finally, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.