Semiconductor device and method for fabricating the same

A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2017-0030355, filed on Mar. 10, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety.

TECHNICAL FIELD

Exemplary embodiments of the present inventive concept relate to a semiconductor device and a method for fabricating the same.

DISCUSSION OF RELATED ART

As one of the endeavors for increasing the density of the semiconductor device, a multi-gate transistor with a silicon body having a fin or nanowire shape may be formed on a substrate, and a gate may be formed on the surface of the silicon body.

The multi-gate transistor may utilize three-dimensional channels. The multi-gate transistor may have an increased current control capability. The multi-gate transistor may suppress a short channel effect (SCE) by controlling the dimension of the three-dimensional channel.

SUMMARY

According to an exemplary embodiment of the present inventive concept, a method for manufacturing a semiconductor device includes forming a stacked structure including one or more sacrificial layers and one or more semiconductor layers. Each sacrificial layer of the one or more sacrificial layers and each semiconductor layer of the one or more semiconductor layers are alternately stacked on a substrate. The method further include forming a dummy gate structure including a dummy gate and a dummy spacer on the stacked structure, and etching the stacked structure using the dummy gate structure as a first mask to form a first recess and exposing the one or more sacrificial layers. The method still further includes etching a part of the one or more sacrificial layers expose by the first recess, removing the dummy spacer, and forming a spacer film on the dummy gate, the one or more semiconductor layers and the one or more sacrificial layers. The method further includes etching a part of a semiconductor layer of the one or more semiconductor layers and a part of the spacer film to form a second recess using the dummy gate and the spacer film formed on a side wall of the dummy gate as a second mask. The method still further includes forming an external spacer on the side wall of the dummy gate and an internal spacer on a side wall of the one or more sacrificial layers. The method further includes forming a source/drain region in the second recess.

According to an exemplary embodiment of the present inventive concept, a method for manufacturing a semiconductor device includes providing a substrate including a first and second regions. The method further includes forming a first stacked structure including a first sacrificial layer and a first semiconductor layer alternately stacked on the first region, and a second stacked structure including a second sacrificial layer and a second semiconductor layer alternately stacked on the second region. The method still further includes forming a first dummy gate on the first stacked structure, and forming a second dummy gate on the second stacked structure. The method still includes forming a second protective layer on the second stacked structure and the second dummy gate of the second region, and forming a first dummy spacer film on the upper surface of the first stacked structure and the first dummy gate. The method further includes etching the first dummy spacer film to form a first dummy spacer on a side wall of the first dummy gate, etching the first stacked structure using the first dummy gate and the first dummy spacer as a first mask to form a first recess, and etching a part of the first sacrificial layer exposed by the first recess. The method still further includes removing the first dummy spacer. The method further includes forming a first spacer film on the first dummy gate, the first semiconductor layer and the first sacrificial layer. The method still further includes etching a part of the first semiconductor layer and a part of the first spacer film to form a second recess, using the first dummy gate and the first spacer film formed on the side wall of the first dummy gate as a second mask, thereby forming a first external spacer formed on the side wall of the first dummy gate and a first internal spacer formed on a side wall of the first sacrificial layer. The method further includes forming a first source/drain region in the second recess, removing the second protective layer, and forming a first protective layer on the first source/drain region, the first dummy gate and the first external spacer of the first region.

According to an exemplary embodiment of the present inventive concept, a semiconductor device includes a first internal spacer including a plurality of first gate electrodes spaced apart from each other on a substrate, a first nanowire formed on the first internal spacer, and a second internal spacer including a plurality of second gate electrodes spaced apart from each other on the first nanowire. The semiconductor device further includes a second nanowire formed on the second internal spacer, a plurality of third gate electrodes formed on the second nanowires, and a source/drain region extending between the plurality of second gate electrodes in a direction perpendicular to a surface of the substrate. The plurality of first gate electrodes, the plurality of second gate electrodes, and the plurality of third gate electrodes are aligned with one another when viewed from a direction perpendicular to the surface of the substrate. A gate insulating film is formed on an outer surface of the each of the pluralities of first, second, and third gate electrodes.

According to an exemplary embodiment of the present inventive concept, a method for fabricating a semiconductor device includes forming a stacked structure including one or more sacrificial layers and one or more semiconductor layers alternately stacked on a substrate, forming a dummy gate structure including a dummy gate and a dummy spacer on the stacked structure. The method further includes etching the stacked structure in a downward direction using the dummy gate structure as a first mask to form a first recess, etching a portion of the one or more sacrificial layers in a horizontal direction to form a second recess, and etching the dummy spacer. The method further includes forming a spacer film on the dummy gate and the one or more semiconductor layer, and in the first and second recesses. The method further includes etching a portion of the one or more semiconductor layers and a portion of the spacer film in the downward direction to form a third recess, using the dummy gate and the spacer film formed on the dummy gate as a second mask, to form an internal spacer formed on the side wall of the sacrificial layer. The method still further includes forming a source/drain region in the third recess, forming a plurality of gate electrodes in the internal spacer, and manufacturing the integrated circuit having the plurality of gate electrodes.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the present inventive concept will be described more fully hereafter with reference to the accompanying drawing. The present inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. It will be also understood that when an element such as a layer, film, region, or substrate is referred to as being “under” another element, it can be directly under the other element or intervening elements may also be present.

Hereinafter, a semiconductor device according to an exemplary embodiment of the present inventive concept will be described with reference toFIG. 1toFIG. 4.

FIG. 1is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept. In an embodiment, the semiconductor device may include an integrated circuit.FIG. 2is a cross-sectional view taken along the line A-A′ ofFIG. 1.FIG. 3is a cross-sectional view taken along the line B-B′ ofFIG. 1.FIG. 4is a cross-sectional view taken along the line C-C′ ofFIG. 1.

Referring toFIG. 1toFIG. 4, a semiconductor device according to an exemplary embodiment of the present inventive concept includes a substrate110, a field insulating film111, a gate electrode120, a gate insulating film121, an insulating film122, a plurality of nanowires130, an external spacer141, a first internal spacer142, a second internal spacer143, a source/drain region150, an interlayer insulating film160, a contact170, and a silicide171.

The substrate110may be, for example, bulk silicon or silicon-on-insulator (SOI). In another example, the substrate110may be a silicon substrate or may contain other materials, for example, silicon germanium (SiGe), indium antimonide (InSb), lead tellurium compounds, indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs) or gallium antimonide (GaSb). Or, the substrate110may be provided by an epitaxial layer formed on the substrate110.

Further, the substrate110may include a pin-like pattern112. The pin-like pattern112may protrude from the substrate110. The field insulating film111may surround at least a part of the side wall of the pin-like pattern112as shown inFIG. 3. The pin-like pattern112may be defined by the field insulating film111. The field insulating film111may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

InFIG. 3, although the side wall of the pin-like pattern112is illustrated as being entirely surrounded by the field insulating film111, but the present inventive concept is not limited thereto.

In one embodiment, the pin-like pattern112may extend long in a first direction X. For example, the pin-like pattern112may include a first side extending in the first direction X, and a second side extending in a second direction Y, where the first side is longer than the second side.

The pin-like pattern112may be formed by etching a part of the substrate110, and may include an epitaxial layer grown from the substrate110. In one embodiment, the pin-like pattern112may include, for example, silicon or germanium which is an elemental semiconductor material. In another embodiment, the pin-like pattern112may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

For example, in the case of group IV-IV compound semiconductor, the pin-like pattern112may be a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), tin (Sn), or a compound in which the elements are doped with group IV element.

In the case of group111-V compound semiconductor, the pin-like pattern112may be a binary compound, a ternary compound, or a quaternary compound formed by combination of at least one of aluminum (Al), gallium (Ga), or indium (In) as the group Ill element with one of phosphorus (P), arsenic (As) or antimony (Sb) as the group V element.

In the semiconductor device according to exemplary embodiments of the present inventive concept, the pin-like pattern112may include silicon.

The plurality of nanowires130may include a first nanowire131and a second nanowire132extending, for example, in the first direction X as shown inFIG. 2. The semiconductor devices exemplarily described herein may be illustrated as including two nanowires130. but the present inventive concept is not limited thereto. For example, in other exemplary embodiments, the semiconductor device may include one nanowire, or more than two nanowires130.

The first nanowire131may be formed on the substrate110so as to be spaced apart from the substrate110. The first nanowire131may be formed to extend in the first direction X.

In one embodiment, the first nanowire131may be formed on the pin-like pattern112so as to be spaced apart from the pin-like pattern112. The first nanowire131may overlap the pin-like pattern112when viewed in the third direction Z. The first nanowire131may not be formed on the field insulating film111. For example, the first nanowire131may be formed on the pin-like pattern112.

In one embodiment, the first nanowire131may have an inclination profile in which the width in the first direction X may increase as the first nanowire131is closer to the pin-like pattern. But, the present inventive concept is not limited thereto.

For example, inFIG. 3, the width of the first nanowire131in the second direction Y may be the same as the width of the pin-like pattern112in the second direction Y. But, the present inventive concept is not limited thereto. In one embodiment, the cross-section of the first nanowire131may be rectangular as shown inFIG. 3. But, the present inventive concept is not limited thereto. For example, the corners of the first nanowire131may be rounded by, for example, trimming process.

The first nanowire131may be used as a channel region of the transistor. The first nanowire131may differ depending on whether the semiconductor device is a PMOS (p-channel MOSFET) or an NMOS (n-channel MOSFET). But, the present inventive concept is not limited thereto.

Further, the first nanowire131may include the same material as the pin-like pattern112, or may include materials different from the pin-like pattern112. However, in the semiconductor device according to exemplary embodiments of the present inventive concept, the first nanowire131will be described as containing silicon.

The second nanowire132may be formed on the substrate110so as to be spaced apart from the substrate110. The second nanowire132may be formed to extend, for example, in the first direction X.

The second nanowire132may be formed farther away from the substrate110than the first nanowire131. For example, the distance from the upper surface of the pin-like pattern112to the second nanowire132may be greater than the distance from the upper surface of the pin-like pattern112to the first nanowire131.

The second nanowire132may overlap the pin-like pattern112when viewed in the third direction Z. In another embodiment, the second nanowire132may not be formed on the field insulating film111but may be formed on the pin-like pattern112when viewed in the third direction Z.

The second nanowire132may be used as the channel region of the transistor. Therefore, in one embodiment, the second nanowire132may include the same material as the first nanowire131.

The gate electrode120may be formed on the field insulating film11and the pin-like pattern112. In one embodiment, the gate electrode120may extend in the second direction Y.

The gate electrode120may be formed to surround the first nanowire131and the second nanowire132that are formed to be spaced apart from the upper surface of the pin-like pattern112. The gate electrode120may also be formed in a space between the pin-like pattern112and the first nanowire131. Further, the gate electrode120may also be formed in a space between the first nanowire131and the second nanowire132.

In one embodiment, the gate electrode120may include a conductive material. Although the gate electrode120may be illustrated as a single layer, the present inventive concept is not limited thereto. For example, in another embodiment, the gate electrode120may include a work function conductive layer which may adjust the work function, and a filling conductive layer which may fill the space formed by the work function conductive layer.

In one embodiment, the gate electrode120may include at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, or Al. Further, the gate electrode120may be made of Si, SiGe or the like rather than metal. The gate electrode120may be formed using, for example, a replacement process. But, the present inventive concept is not limited thereto.

The gate insulating film121may be formed between the first nanowire131and the gate electrode120, and between the second nanowire132and the gate electrode120. Further, the gate insulating film121may be formed between the field insulating film111and the gate electrode120, between the pin-like pattern112and the gate electrode120, between the insulating film122and the gate electrode120, between the first internal spacer142and the gate electrode120, or between the second internal spacer143and the gate electrode120.

For example, the gate insulating film121may include an interfacial film and a high dielectric constant (k) insulating film. But, the present inventive concept is not limited thereto. For example, the gate insulating film121may not include the interfacial film, depending on, for example, the material composition of the first and second nanowires131and132and the like.

The gate insulating film121may be formed along the circumference of the first and second nanowires131and132. The gate insulating film121may be formed along the upper surface of the field insulation film111and the upper surface of the pin-like pattern112. In addition, the gate insulating film121may be formed along the side walls of the external spacer141, the first internal spacer142, and the second internal spacer143.

For the first and second nanowires131and132including silicon, the interfacial film may include a silicon oxide film.

The high dielectric constant insulating film may include a dielectric material having a dielectric constant higher than the dielectric constant of silicon oxide film. For example, the dielectric material may contain one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. But, the present inventive concept is not limited thereto.

For the gate insulating film121which does not include the interfacial film, the high dielectric constant insulating film may include the silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like as well as the aforementioned dielectric materials.

The insulating film122may be formed between the gate insulating film121and the external spacer141, and between the external spacer141and the second nanowire132. The insulating film122may include, for example, silicon oxycarbonitride (SiOCN). But, the present inventive concept is not limited thereto.

The external spacer141may be formed on the insulating film122formed on both side walls of the gate electrode120extending, for example, in the second direction Y.

The external spacer141may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), or a combination thereof.

In one embodiment, the external spacer141may include the same material as the insulating layer122. For example, the insulating film122may include silicon oxycarbonitride (SiOCN), and the external spacer141may include silicon oxycarbonitride (SiOCN). However, the present inventive concept is not limited thereto. For example, in another embodiment, the insulating film122and the external spacer141may include different materials from each other

The first internal spacer142may be formed on both sides of the gate electrode120between the first nanowire131and the second nanowire132. In one embodiment, the first internal spacer142may come into contact with a portion of the side surfaces of the first and second nanowires131and132.

The first internal spacer142may be made of, for example, at least one of a low dielectric constant dielectric material, which may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), or a combination thereof. The low dielectric constant dielectric material may be a material having the dielectric constant lower than or equal to the silicon oxide.

In one embodiment, the first internal spacer142and the external spacer141may include the same material. For example, the external spacer141may include silicon oxycarbonitride (SiOCN), and the first internal spacer142may also include the silicon oxycarbonitride (SiOCN). In this case, the first internal spacer142may have the dielectric constant less than 5.

Thus, in the semiconductor device according to an exemplary embodiment of the present inventive concept, the dielectric constant of the first internal spacer142may be reduced to reduce a fringing capacitance between the gate electrode120and the source/drain region150.

But, the present inventive concept is not limited thereto. For example, in another embodiment, the first internal spacer142and the external spacer141may include different materials from each other.

The side wall of the first internal spacer142and the side wall of the second nanowire132may be aligned to each other. In one embodiment, the side wall of the first internal spacer142adjacent to the source/drain region150may be aligned with the side wall of the second nanowire132adjacent to the source/drain region150as shown inFIG. 2. For example, the first internal spacer142may not be formed in a concave shape relative to the gate electrode120.

As a result, according to an exemplary embodiment of the present inventive concept, the side wall of the first internal spacer142and the side wall of the second nanowire132may be aligned to each other, and the first internal spacer142may be formed to be relatively thick compared to, for example, the first internal spacer142with the concave shape.

The second internal spacer143may be formed on both sides of the gate electrode120between the first nanowire131and the substrate110. In one embodiment, the second internal spacer143may come into contact with a portion of the side surface of the first nanowire131.

Further, the second internal spacer143may be formed between the substrate110and the source/drain region150, and a part of the second internal spacer143may be formed in a recess formed on the substrate110. However, the second internal spacer143may not be formed between the substrate110and the gate electrode120.

Accordingly, in the semiconductor device according to an exemplary embodiment of the present inventive concept, the second internal spacer143which is an insulating layer between the substrate110and the source/drain region150, provides the semiconductor device with added insulation and increased reliability.

The second internal spacer143may include, for example, at least one of a low dielectric constant dielectric material, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), and a combination thereof. The low dielectric constant dielectric material may be a material having the dielectric constant lower than or equal to the silicon oxide.

In one embodiment, the second internal spacer143may include the same material as the external spacer141and the first internal spacer142. For example, the external spacer141and the first internal spacer142may include the silicon oxycarbonitride (SiOCN), and the third internal spacer may include the silicon oxycarbonitride (SiOCN). In this case, the second internal spacer143may have a dielectric constant (k) less than 5.

But, the present inventive concept is not limited thereto. For example, in another embodiment, the second internal spacer143and the external spacer141may include different materials from each other.

In one embodiment, the source/drain region150may be formed on at least one side of the gate electrode120. The source/drain region150may be formed on the second internal spacer143. The source/drain region150may include an epitaxial layer formed on the upper surface of the second internal spacer143.

The outer peripheral surface of the source/drain region150may have various shapes. For example, the outer peripheral surface of the source/drain region150may be at least one of a diamond shape, a circular shape, a rectangular shape, or an octagonal shape.

The source/drain region150may be directly connected to the first and second nanowires131and132that may be used as the channel region.

On the other hand, the source/drain region150may not come into direct contact with the gate insulating film121. A spacer may be located between the source/drain region150and the gate insulating film121. In one embodiment, one side wall of the first internal spacer142may come into contact with the gate insulating film121, and the other side wall of the first internal spacer142may come into contact with the source/drain region150as shown, for example inFIG. 2. Therefore, the source/drain region150and the gate insulating film121may not come into contact with each other when positioned between the first nanowire131and the second nanowire132. Further, the external spacer141may be formed on an uppermost part of the second nanowire132, and the source/drain region150and the gate insulating film121may not come into contact with each other on the second nanowire132.

The interlayer insulating film160may be formed to cover a part of the external spacer141and the source/drain region150, and the contact170may be connected to the source/drain region150through the interlayer insulating film160. In this case, a silicide layer171may be formed between the contact170and the source/drain region150.

Hereinafter, a method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept will be described with reference toFIG. 5toFIG. 15.

FIG. 5toFIG. 15are cross-sectional views for describing a method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept.

Referring toFIG. 5, a stacked structure101in which a sacrificial layer102and a semiconductor layer103are alternately stacked may be formed on the substrate110.

Each sacrificial layer102in the stacked structure101may include the same material, and the sacrificial layer102and the semiconductor layer103may include different materials from each other. In the method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept, each sacrificial layer102will be described as including the same material. Further, the semiconductor layer103may include a material having a selectivity in etch ratio to the sacrificial layer102.

For example, the substrate110and the semiconductor layer103may include materials that may be used for the channel region of the transistor. For example, in the case of PMOS, the semiconductor layer103may include a material with increased hole mobility, and in the case of NMOS, the semiconductor layer103may include a material with increased electron mobility.

The sacrificial layer102may include a material having a lattice constant and a lattice structure similar to those of the semiconductor layer103. For example, the sacrificial layer102may be a semiconductor material. In another example, the sacrificial layer102may be a crystallized metal material.

In the method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept, it is described that the semiconductor layer103may include the silicon (Si), and the sacrificial layer102may include the silicon germanium (SiGe), respectively.

Although the two semiconductor layers103are illustrated inFIG. 5, the present inventive concept is not limited thereto. For example, the sacrificial layer102and the semiconductor layer103may alternately form a plurality of pairs, and the semiconductor layer103may be formed on the uppermost sacrificial layer102.

Further, the sacrificial layer102may be illustrated as being located at the uppermost part of the stacked structure101. But, the present inventive concept is not limited thereto. For example, the semiconductor layer103may be located at the uppermost part of the stacked structure101in another embodiment.

Referring toFIG. 6, a dummy gate106may be formed by performing an etching process using the mask pattern107as a mask. The dummy gate106may extend in the second direction Y, and may intersect with the stacked structure101formed on the substrate110.

In this case, the dummy gate insulating film105may be formed between the stacked structure101and the dummy gate106. The dummy gate insulating film105may include, for example, the silicon oxide film, and the dummy gate106may include, for example, polysilicon or amorphous silicon.

Referring toFIG. 7, the insulating film122may be conformally formed to cover the upper surface of the stacked structure101, the side surfaces of the dummy gate insulating film105, the side surfaces of the dummy gate106, and the top and side surface of the mask pattern107. The insulating film122may include, for example, the silicon oxycarbonitride (SiOCN). But, the present inventive concept is not limited thereto.

A dummy spacer film108may be conformally formed on the insulating film122. The insulating film122may include, for example, the silicon oxide (SiO2). But, the present inventive concept is not limited thereto.

In this case, the dummy spacer film108may be formed to be thicker than a spacer film (140ofFIG. 11) that may be formed in a later process step.

Referring toFIG. 8, the dummy spacer film108may be etched back to expose the upper surface of the stacked structure101and the mask pattern107, thereby forming a dummy spacer109on both side walls of the dummy gate106.

The stacked structure101and the substrate110may be partially etched, using the dummy gate structure including the dummy gate106and the dummy spacer109as the mask, thereby forming a first recess R1.

Referring toFIG. 9, the sacrificial layer102exposed by the first recess R1may be partially etched. In one embodiment, the sacrificial layer102may be formed by the first recess R1, and the sacrificial layer102may be partially etched. For example, the sacrificial layer102may be etched in a first direction X from the cross-sections of the first and second nanowires131and132exposed by the first recessed portion R1.

Such a process may be performed, for example, using a selective etching process. In one embodiment, such a process may be performed through the etching process, using an etchant in which the etching rate of the sacrificial layer102may be greater than the etching rate for the first and second nanowires131and132.

In one embodiment,FIG. 9illustrates a configuration in which the side surfaces of the sacrificial layer102are etched into a planar shape. On the other hand, the side surfaces of the sacrificial layer102may have a concave shape in another embodiment.

Next, referring toFIG. 10andFIG. 11, after removing the dummy spacer109, the spacer film140may be formed on the mask pattern107, the insulating film122, the sacrificial layer102exposed by the first recess R1, the semiconductor layer103exposed by the first recess R1, and the substrate110exposed by the first recess R1.

In this case, the thickness t2of the spacer film140may be formed to be thinner than the thickness t1of the dummy spacer109illustrated inFIG. 8. For example, the thickness t1of the dummy spacer109illustrated inFIG. 8may be formed to be greater than the thickness t2of the external spacer141formed in the later processes steps.

The spacer film140may include a low dielectric constant dielectric material, e.g., the silicon oxycarbonitride (SiOCN).

Referring toFIG. 12, a second recess R2may be formed by etching a part of the semiconductor layer103, a part of the insulating film122and a part of the spacer film140, using the external spacer141formed on the side walls of the mask pattern107and the dummy gate106as a mask. In one embodiment, the second internal spacer143may not be etched, and the second recess R2may be formed on the second internal spacer143. For example, the second internal spacer143may not include the second recess R2.

In one embodiment, the width d2of the second recess R2may be formed to be greater than the width d1of the first recess R1illustrated inFIG. 8.

Accordingly, in a method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept, the side wall of the external spacer141formed on the side wall of the dummy gate106may be aligned with the side wall of the second nanowire132, and the side wall of the first internal spacer142formed on the side wall of the sacrificial layer102between the first nanowire131and the second nanowire132.

In one embodiment, the side wall of the first internal spacer142may be aligned with the side wall of the second nanowire132exposed by the second recess R2.

In another embodiment, in the method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept, the external spacer141, the first internal spacer142and the second internal spacer143may include the same material (for example, the silicon oxycarbonitride (SiOCN)).

Referring toFIG. 13, the source/drain region150may be formed in the second recess R2using, for example, an epitaxial process.

Referring toFIG. 14, an interlayer insulating film160may be formed on the field insulating film111. In one embodiment, the interlayer insulating film160may cover the source/drain region150, the external spacer141, the insulating film122and the mask pattern107.

The interlayer insulating film160may be planarized to remove the mask pattern107until the upper surface of the dummy gate106is exposed.

The dummy gate insulating film105and the dummy gate106may be removed. As a result, the first and second nanowires131,132that are overlapped with the dummy gate106in the third direction Z may be exposed.

Referring toFIG. 15, the gate insulating film121and the gate electrode120may be formed in a region where the dummy gate insulating film105and the dummy gate106are removed. A contact170and a silicide171may be formed in the interlayer insulating film160. For example, the contact170and the silicide171may penetrate the interlayer insulating film160to contact the source/drain region150as shown inFIG. 16, and the semiconductor device illustrated inFIG. 2may be manufactured.

In the method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept, the external spacer141, the first internal spacer142, and the second internal spacer143may be formed using the same material (for example, the silicon oxycarbonitride (SiOCN)) to have the dielectric constant of the first and second internal spacers142and143to be low, and the fringing capacitance between the gate electrode120and the source/drain region150may be reduced.

Further, in the method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept, the side wall of the first internal spacer142and the side wall of the second nanowire132may be aligned to each other by two recess forming processes, and the thickness of the first internal spacer142may be formed to be relatively thick compared to, for example, the first internal spacer142with, for example, the concave shape.

In the method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept, a second internal spacer143may be formed as an insulating layer between the substrate110and the source/drain region150for increased reliability of the semiconductor device.

Hereinafter, a semiconductor device and a method for fabricating a semiconductor device according to another exemplary embodiment of the present inventive concept may be described with reference toFIG. 16throughFIG. 18.

FIG. 16is a cross-sectional view describing a method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept.FIG. 17andFIG. 18are intermediate step diagrams for describing a method for fabricating a semiconductor device according to another exemplary embodiment of the present inventive concept. Description of the semiconductor device and the method for fabricating the semiconductor device already illustrated inFIG. 1,FIG. 2, andFIG. 5toFIG. 15will not be described in detail herein except as necessary for a complete understanding of the present inventive concept.

Referring toFIG. 16, for example, a difference in the semiconductor device illustrated inFIG. 16from the semiconductor device illustrated inFIG. 2may be that the source/drain region250is formed adjacent to the substrate110.

In one embodiment, the source/drain region250may be formed adjacent to the side wall of the second internal spacer243, and the side wall of the second internal spacer243adjacent to the source/drain region250may have a inclination profile in which the width of the second internal spacer243may increase toward the substrate110.

Further, the side wall of the first nanowire231adjacent to the source/drain region250, the side wall of the first internal spacer142adjacent to the source/drain region250, and the side wall of the second nanowire232adjacent to the source/drain region250may be aligned with one another.

Referring toFIG. 17, in one embodiment, the lower end of the first recess R1may be formed on the substrate110. Accordingly, the second internal spacer143may not be formed between the substrate110and the lower end of the first recess R1.

Referring toFIG. 18, in an embodiment, the lower part of the second recess R2may be formed on the substrate110. For example, the lower part of the second recess R2may not be formed in the substrate110.

Hereinafter, a semiconductor device and a method for fabricating a semiconductor device according to still another exemplary embodiment of the present inventive concept will be described with reference toFIG. 19throughFIG. 24.

FIG. 19is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept.FIG. 20is a cross-sectional view taken along the line D-D′ ofFIG. 19.FIG. 21toFIG. 24are cross-sectional views describing a method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept. Description of the semiconductor device and the method for fabricating the semiconductor device already illustrated inFIG. 1,FIG. 2, andFIG. 5toFIG. 15will not be described in detail herein except as necessary for a complete understanding of the present inventive concept.

Referring toFIG. 19andFIG. 20, in one embodiment, the semiconductor device illustrated inFIG. 19andFIG. 20includes two regions which are spaced apart from each other in the first direction X. In this case, a first region I may be the NMOS region and a second region II may be the PMOS region. In one embodiment, the semiconductor device formed in the first region I may be the same as the semiconductor device illustrated inFIG. 2.

The semiconductor device formed in the second region II may include a second substrate310, a second gate electrode320, a second gate insulating film321, a second insulating film322, a plurality of nanowires330, a second external spacer341, a second source/drain region350, a second interlayer insulating film360, a second contact370and a second silicide371.

In one embodiment, the semiconductor device formed in the second region II ofFIG. 20may indicate that no internal spacer is formed on the side walls of the third nanowire331and the fourth nanowire332. For example, the second source/drain region350and the second gate insulating film321may be in direct contact with each other, which may be different from the semiconductor device illustrated inFIG. 2.

Further, the side wall of the second gate insulating film321adjacent to the second source/drain region350may include an inclination profile. For example, the width of the side wall of the second gate insulating film321may increase toward the second substrate310, and the second source/drain region350may be formed adjacent to the second substrate310. For example, the second source/drain region350may be in direct contact with the second substrate310.

Referring toFIG. 21, a first stacked structure101in which a first sacrificial layer102and a first semiconductor layer103are alternately stacked may be formed on a first substrate110of the first region I, and a second stacked structure301in which a second sacrificial layer302and a second semiconductor layer303are alternately stacked may be formed on the second substrate310of the second region II.

In an embodiment, the first dummy gate insulating film105and the first dummy gate106may be formed by performing the etching process using the first mask pattern107, and the first dummy gate insulation film105and the first dummy gate106may be formed on the first stacked structure101, and extend in the second direction Y to intersect with the first stacked structure101. In an embodiment, the second dummy gate insulating film305and the second dummy gate306may be formed by performing the etching process using the second mask pattern307, and the second dummy gate insulating film305and the second dummy gate306may be formed on the second stacked structure301, and extend in the second direction Y to intersect with the second stacked structure301.

Referring toFIG. 22, a second protective layer390may be formed to cover the second stacked structure301, the second dummy gate insulating film305, the second dummy gate306, and the second mask pattern307in the second region II.

In an embodiment, the processes described above with reference toFIG. 7throughFIG. 13may be performed in the first region I.

Referring toFIG. 23, the second protective layer390may be removed in the second region II, and a first protective layer190may be formed on the first source/drain region150, the first external spacer141, the first insulating film122and the first mask pattern107in the first region I.

In the second region II, a second insulating film322may be formed on a part of the upper surface of the second stacked structure301, and on the second dummy gate insulating film305, the second dummy gate306and the second mask pattern307. For example, the second insulating film322may be formed on the side surface of the second dummy gate insulating film305, the second dummy gate306, and the second mask pattern307. The second external spacer341may be formed on the side wall of the second dummy gate306by forming the second external spacer341on the second insulating film322.

The second stacked structure301may be etched using the second mask pattern307, the second insulating film322and the second external spacer341as the mask, and a recess may be formed. For example, a lower end of the recess may expose the upper surface of the second substrate310. The second source/drain region350may be formed in the formed recess.

The first protective layer190may be removed in the first region I, and the processes described above with respect toFIG. 14andFIG. 15may be performed in the first region I and the second region II to fabricate the semiconductor device illustrated inFIG. 20.

Hereinafter, a semiconductor device and a method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept will be described with reference toFIG. 25.

FIG. 25is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept. Description of the semiconductor device and the method for fabricating the semiconductor device illustrated inFIG. 2,FIG. 5toFIG. 15will not be described in detail herein except as necessary for a complete understanding of the present inventive concept.

Referring toFIG. 25, in an embodiment, the semiconductor device illustrated inFIG. 25may include two regions spaced apart from each other in the first direction. For example, the first region I may be the NMOS region and the second region II may be the PMOS region. For example, the semiconductor device formed in the first region I may be the same as the semiconductor device illustrated inFIG. 2.

The semiconductor device formed in the second region II may include a substrate410, a gate electrode420, a gate insulating film421, an insulating film422, a plurality of nanowires430, an external spacer441, a first internal spacer442, a second internal spacer443, a source/drain region450, an interlayer insulating film460, a contact470, and silicide471.

The semiconductor device illustrated inFIG. 25may be formed by forming the stacked structure101, the mask pattern107, the dummy gate insulating film105, the dummy gate106, the insulating film122, and the dummy spacer109on the substrate110in the first region I by the processes illustrated inFIG. 5toFIG. 8. In the second region II, the stacked structure301, the mask pattern307, the dummy gate insulating film305, the dummy gate306, the insulating film422, and the dummy spacer109may be formed on the substrate410.

A protective layer may be formed in the second region II, and the processes described above with reference toFIG. 7throughFIG. 13may be performed in the first region I.

The protective layer may be removed in the second region II, and the protective layer may be formed in the first region I. In one example, the processes described above with reference toFIG. 7throughFIG. 13may be performed in the second region II.

The protective layer may be removed in the first region I, and the processes described above with reference toFIG. 14andFIG. 15may be performed on each of the first region I and the second region II to fabricate the semiconductor device illustrated inFIG. 25.

While the exemplary embodiments of the present inventive concept have been described with reference to the accompanying drawings, the present inventive concept can be manufactured in various different forms rather than being limited to the aforementioned embodiments. A person having ordinary skill in the technical field to which the present inventive concept pertains may understand that the present inventive concept can be provided in other concrete forms, without changing the technical idea and features of the present inventive concept. Therefore, the aforementioned embodiments should be considered in a descriptive sense only and not for purposes of limitation.