Semiconductor memory device having reduced leakage current

A static semiconductor memory device includes a memory cell formed in a memory cell region; and a dummy memory cell formed in a dummy memory cell region. The memory cell includes a power supply wiring and a ground wiring which are provided to extend in a direction of a word line; and inverters provided between the power supply wiring and the ground wiring and cross-connected to each other. The dummy memory cell includes first and second wirings respectively corresponding to the power supply wiring and the ground wiring and extending in the direction of the word line; and two sets of a dummy load circuit and a dummy drive transistor, wherein the two sets are connected with the first and second wirings, which are biased to prevent leakage current from flowing.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a static semiconductor memory device and, more particularly, to a static semiconductor memory device, in which degradation of device quality or reduction of operational margin can be prevented.

2. Description of the Related Art

In an SRAM, dummy memory cells that cannot function as memory cells are arranged around the memory cells in order to reduce a defect rate of the memory cells due to a non-coincidence of the dimension of a pattern or an incorrect shape of the pattern after a lithography process through an abrupt change in device density. Naturally, the dummy memory cell induces the incorrect pattern shapes of polysilicon gates or contact holes due to a proximity effect, compared with the memory cell. As a consequence, the dummy memory cells are designed to be separated from the memory cells from the viewpoint of circuit logic, so as to avoid any adverse influence on a normal functional operation of the memory cells.

The dummy memory cell has a layout structure similar to that of the memory cell to keep the continuity of a layout. In particular, it is desired that the dummy memory cell has the arrangement or shapes of a well, a diffusion layer, a polysilicon gate, a contact hole, a metal wiring and a via-contact identical to or similar to those of the memory cell. As a consequence, the circuit configuration of the dummy memory cell is equivalent to that of the memory cell.

Japanese Laid Open Patent Application (JP-A-Showa 61-214559) discloses the arrangement of dummy memory cells around memory cells. In this first conventional example, the dummy memory cells without any operation are arranged in a boundary between a region where the memory cells are continuously arranged, and another region where the memory cells are not continuously arranged. Also, Japanese Laid Open Patent Application (JP-A-Heisei 7-176631) as a second conventional example discloses a technique for using a dummy transistor in a dummy memory cell as a pull-up transistor to keep a bit line at a predetermined voltage. Moreover, Japanese Laid Open Patent Application (JP-P2004-071118A) as a third conventional example discloses an SRAM, in which a voltage decrease rate of a dummy bit line is higher than that of a bit line. In this third conventional example, a P-channel MOS transistor for a load in a memory cell is replaced with an N-channel MOS transistor. Also, a power supply voltage is applied to a memory node, and a ground voltage GND is applied to a source of the N-channel MOS transistor. A current flows out on a line of the ground voltage from a dummy bit line when a word line is raised up to an “H” level, thereby improving the operational margin of the SRAM.

However, in the conventional SRAMs, since power is supplied to a dummy memory cell from a power supply voltage VDD, a leakage current flows in a normal dummy memory cell although it is slight. In addition, although the dummy memory cell is permitted to have an abnormal shape, an unexpected current possibly flows. Specifically, various defects could be considered such as a short-circuit between a source and a drain in a transistor due to defect of a polysilicon gate, a short-circuit between the source and the drain due to the excessive formation of a diffusion layer, a short-circuit between the power supply voltage and a substrate voltage due to the defect of a metal wiring. In the conventional examples, a memory cell, a dummy memory cell and a Tap cell share a power supply wiring and a ground wiring, and further, the same kind of well layers arranged adjacently in an X direction. In this case, an unexpected current path is generated, and a large amount of leakage current flows through the unexpected current path. As a result, the voltages of the power supply wiring and the ground wiring are temporarily fluctuated. Thus, the operational margin of the memory cell connected to the power supply wiring and the ground wiring is greatly influenced by the above-described fluctuation of the voltage. Additionally, in the conventional SRAM, the leakage current slightly flows even through a transistor of the dummy memory cell having the correct shape.

In recent years, a power supply voltage is reduced as the pattern of an LSI has become finer, so that an operation current, i.e., a dynamic current is reduced to achieve low power consumption. However, a leakage current on standby, i.e., a static current is not decreased more than that of the operation current. Thus, a ratio of the leakage current in the current consumption increases. When the voltage is more decreased and the gate length is more shortened, the decrease in leakage current has come to an end at a certain stage, and thereafter, the leakage current is increased in turn. This becomes prominent in a 90-nm generation and the subsequent generations, and various countermeasures are proposed to reduce the leakage current. For example, a system is configured such that a power supply voltage becomes zero on the standby. Similarly, the ratio of the leakage current in the current consumption is increased due to the miniaturization in the dummy memory cell with correct shapes or with few incorrect shapes. Furthermore, as the number of dummy memory cells increases, the total leakage current becomes more. As a consequence, the leakage current flowing in the dummy memory cells increases a total leakage current in the SRAM, to increase the power consumption.

The dummy memory cell does not have a mechanism for writing or reading data. Therefore, a test of the dummy memory cell is not carried out or cannot be carried out. However, it was found by the inventor of the present invention that such an influence of the leakage current in the dummy memory cells to a memory cell array could not be ignored in the SRAM in a 0.15-μm generation. The leakage current in the dummy memory cell causes an erroneous operation of the SRAM and the defective quality due to increase in current consumption or power consumption. In future, as the pattern of the LSI becomes finer, there would be a possibility of degradation of quality due to the leakage current generated in the dummy memory cell, that is, an unexpected leakage current due to an incorrect shape or a leakage current associated with the fineness of a circuit configuration, if the conventional configuration is kept.

SUMMARY OF THE INVENTION

In aspect of the present invention, a static semiconductor memory device includes a memory cell formed in a memory cell region; and a dummy memory cell formed in a dummy memory cell region. The memory cell includes a power supply wiring and a ground wiring which are provided to extend in a direction of a word line; and inverters provided between the power supply wiring and the ground wiring and cross-connected to each other. The dummy memory cell includes first and second wirings respectively corresponding to the power supply wiring and the ground wiring and extending in the direction of the word line; and two sets of a dummy load circuit and a dummy drive transistor, wherein the two sets are connected with the first and second wirings, which are biased to prevent leakage current from flowing.

Here, each of the dummy cell and the memory cell includes a device section; and a wiring section provided above the device section. The wiring section of the memory cell includes the power supply wiring and the ground wiring, and the wiring section of the dummy memory cell comprises the first and second wirings, and the device section of the memory cell and the device section of the dummy memory cell have a same layout.

Also, the first and second wiring may be biased to a same voltage, or may be biased to different voltages.

Also, the dummy drive transistor may have a drain connected with one end of the dummy load circuit. The other end of the dummy load circuit may be connected with the first wiring and a source of the dummy drive transistor is connected with the second wiring. In this case, the dummy load circuit may include a dummy load resistor.

Also, the dummy load circuit may include a dummy load transistor. In this case, the dummy load transistor and the dummy drive transistor may be of a same conductive type, or may be of different conductive types.

Also, one end of the dummy load circuit is connected with a drain of the dummy driver transistor, and the other end of the dummy load circuit and the source of the dummy drive transistor are connected with the first wiring and the second wiring, respectively.

Also, the second wiring may be connected to the ground wiring of the memory cell, and the first wiring may be separated from the power supply wiring of the memory cell. In this case, the dummy memory cell may include a third wiring extending in a direction perpendicular to the direction of the word line, and the first and second wirings of the dummy memory cell are connected with the third wiring.

Also, a column of the dummy memory cells may be arranged in adjacent to a column of the memory cells through a column of Tap regions. Each of the Tap regions stabilizes a power supply voltage and a ground voltage supplied to the memory cells through the power supply wiring and the ground wiring, respectively.

Also, a column of the dummy memory cells, a column of Tap regions and a column of the memory cells may be arranged in this order. Each of the Tap regions stabilizes a power supply voltage and a ground voltage supplied to the memory cells through the power supply wiring and the ground wiring, respectively. In this case, a transistor connected with the power supply wiring is formed in an N well in the memory cell, and the Tap region adjacent to the memory cell has a P well, and is biased to the ground voltage.

In another aspect of the present invention, a static semiconductor memory device includes a memory cell formed in a memory cell region; and a dummy memory cell formed in a dummy memory cell region. The memory cell includes a power supply wiring and a ground wiring to supply a power supply voltage and a ground voltage, respectively; and inverters connected between the power supply wiring and the ground wiring and cross-connected to each other. The dummy memory cell includes first and second wirings provided in correspondence to the power supply wiring and the ground wiring, respectively; and two sets of a dummy load circuit and a dummy drive transistor, wherein the two sets are connected with the first and second wirings, and inputs and outputs of the two sets are cross-connected to each other.

Here, the dummy load circuit may be a p-type dummy load transistor, and the dummy drive transistor is an n-type MOS transistor. Sources of the dummy load transistor and the dummy drive transistor are respectively connected to the first and second wirings, which are connected with the ground voltage.

Also, the dummy load circuit may be an n-type dummy load transistor, and the dummy drive transistor is an n-type MOS transistor. Sources of the dummy load transistor and the dummy drive transistor are respectively connected to the first and second wirings, which are connected with the ground voltage.

Also, the dummy load circuit may be a p-type dummy load transistor, and the dummy drive transistor is an n-type MOS transistor. Sources of the dummy load transistor and the dummy drive transistor are respectively connected to the first and second wirings, which are respectively connected with the power supply voltage and the ground voltage. A set of the input of one set and the output of the other set is connected to the ground voltage, and a set of the input of the other set and the output of the one set is connected to the power supply voltage.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a static semiconductor memory device such as a static random access memory device (SRAM) according to the present invention will be described in detail with reference to the attached drawings.

Referring toFIGS. 1,2A and2B, a memory cell in the SRAM according to the present invention will be described.FIG. 1is a circuit diagram showing a memory cell100used in the SRAM according to the present invention. The memory cell100is provided with inverters10A and10B whose input and output terminals are cross-connected to each other, to form a flip-flop or latch circuit. The flip-flop is connected to a bit line BL and a bit B line BBL via access transistors13A or13B whose gates are connected with a word line WL, respectively. A WORD signal is supplied onto the word line WL, and a BIT signal and a BITB signal are transferred on the bit line BL and the bit B line BBL, respectively. In one example, a load transistor11A of the inverter10A is a P-type MOS transistor, and a drive transistor12A thereof is an N-type MOS transistor. In the same manner, a load transistor11B of the inverter10B is a P-type MOS transistor, and a drive transistor12B thereof is an N-type MOS transistor. Also, a source of each of the load transistors11A and11B is connected to the power supply voltage VDD, and further, a source of each of the drive transistors12A and12B is grounded.

FIGS. 2A and 2Bare diagrams showing an example of layout of the memory cell100having the circuit shown inFIG. 1.FIG. 2Ais a diagram showing a layout of a lower layer as a device section of the memory cell having a well region WELL, a diffusion layer Diffusion, a polysilicon layer Poly and a contact layer Contact.FIG. 2Bis a diagram showing a layout of an upper wiring layer as a wiring section of the memory cell having a contact layer Contact, a first metal wiring layer ME1, a via-contact VIA and a second metal wiring layer ME2.

Referring toFIG. 2A, the device section in the memory cell100is provided with a well region WELL having an N-type well NW and a P-type well PW formed adjacently to the N-type well NW, and the diffusion region Diffusion having a P-type diffusion layer PD in the N-type well NW and an N-type diffusion region ND in the P-type well PW. Moreover, two polysilicon gates PG1and PG2are provided to extend in a Y direction across the P-type diffusion layer PD and the N-type diffusion layer ND. In addition, a polysilicon gate PG3serving as the word line WL extends in the X direction across the P-type well PW. The P-type diffusion layer PD and the polysilicon gates PG (PG1, PG2) form P-type MOS transistors. Specifically, the P-type diffusion layer PD and a polysilicon gate PG1form the load transistor11A, and the P-type diffusion layer PD and a polysilicon gate PG2form the load transistor11B. The N-type diffusion layer ND and the polysilicon gates PG (PG1, PG2, PG3) form the N-type MOS transistors. Specifically, the N-type diffusion layer ND and the polysilicon gate PG3form the access transistors13A and13B. Also, the N-type diffusion layer ND and the polysilicon gates PG1and PG2form the drive transistor12A and the drive transistor12B. A node of each of the gate, source and drain is connected to the metal wiring layer ML in the wiring section via a via-contact CH.

Referring toFIG. 2B, the wiring section includes the first metal wiring layer ME1provided with the metal wirings ML (ML1, ML2, ML3, ML4) connected to the device section through the via-contacts CH, the via-contact layer VIA provided with via-contacts VH for connecting the first metal wiring. layer ME1and the second metal wiring layer ME2, and the second metal wiring layer ME2provided with upper metal wirings UML (UML1, UML2) to be used as the bit line BL or the bit line BBL. A metal wiring ML1extends in the X direction in such a manner as to reach both ends of the memory cell, and functions as the power supply wiring VL to be connected to the power supply voltage VDD. In addition, the metal wiring ML1is connected to the sources of the load transistors11A and11B through the via-contact CH. In contrast, a metal wiring ML2extends in the X direction in such a manner as to reach both ends of the memory cell, and is grounded, thereby forming the ground wiring GL as a substrate voltage GND. In addition, the metal wiring ML2is connected to the sources of the drive transistors12A and12B through the via-contact CH. A metal wiring ML3is connected to a drain of the load transistor11A, a drain of the drive transistor12A and a drain of the access transistor13A and a gate of each of the load transistor11B and the drive transistor12B via the via-contacts CH. Moreover, a metal wiring ML4is connected to a drain of each of the load transistor11B, the drive transistor12B and the access transistor13B and a gate of each of the load transistor11A and the drive transistor12A through the via-contacts CH. Sources of the access transistors13A and13B are connected to the bit line BL, i.e., the upper metal wiring UML1, and the bit B line BBL, i.e., the upper metal wiring UML2, through the via-contacts CH, metal wirings and the via-contacts VH, respectively.

Next, the dummy memory cell will be described below. In this description, the same reference symbols and numerals are allocated to the same components corresponding to those of the memory cell100. For example, a metal wiring ML1-1in a dummy memory cell200corresponds to the metal wiring ML1in the memory cell100.

First Embodiment

The SRAM according to the first embodiment of the present invention will be described with reference toFIGS. 3 to 11. In the SRAM in the first embodiment, dummy memory cells201,211and221are used, in which the same P-type MOS transistor as the load transistor11in the memory cell100is used as a dummy load transistor.

FIG. 3is a circuit diagram showing one of dummy memory cells201arranged in a direction of the bit lines in the SRAM according to the first embodiment of the present invention. The dummy memory cell201in the first embodiment is provided with dummy inverters20-1(20A-1and20B-1) corresponding to inverters10(10A and10B) in the memory cell and dummy access transistors23(23A-1and23B-1) corresponding to the access transistors13(13A and13B). Input and output terminals of the dummy inverters20A-1and20B-1are cross-connected to each other, and connected with the dummy access transistors23A-1and23B-1. A source of the dummy access transistor23A-1(or23B-1) is separated from a dummy bit line DBL (or the dummy bit B line DBBL), and a gate thereof is connected with a word line WL. A WORD signal is supplied onto the word line WL. The dummy inverter20A-1or20B-1includes a P-type MOS transistor21A-1or21B-1as a dummy load transistor and an N-type MOS transistor22A-1or22B-1as a dummy drive transistor. A source of each of the dummy load transistor21A-1or21B-1and the dummy drive transistor22A-1or22B-1is grounded.

FIG. 4is a circuit diagram showing one of dummy memory cells211arranged in a direction of the word line WL in the SRAM in the first embodiment. The dummy memory cell211is provided with a dummy word line DWL, the bit line BL and the bit B line BBL in place of the word line, the dummy bit line DBL and the dummy bit B line DBBL in the configuration of the dummy memory cell201, respectively. A bit signal BIT and a bit B signal BITB are transferred onto the bit line BL and the bit B line BBL, respectively. The dummy inverters20A-1and20B-1are cross-connected to each other, in the same way as the dummy memory cell201. Also, the dummy inverters20A-1and20B-1are connected with the dummy bit line DBL and the dummy bit B line DBBL through the dummy access transistors23A-1and23B-1, respectively. A gate of each of the dummy access transistors23A-1and23B-1is connected with the dummy word line DWL. A signal of a Low level is supplied to the dummy word line DWL, so that the access transistors23A-1and23B-1are always turned off. In addition, a source of the dummy access transistor23A-1(or23B-1) is connected to the bit line BL (or the bit B line BBL).

FIGS. 5A and 5Bare diagrams showing layouts of the dummy memory cell201.FIG. 5Ashows a layout of a device section andFIG. 5Bshows a layout of a wiring section arranged above the device section shown inFIG. 5A. The layout of the device section in the dummy memory cell201is same as that of the device section in the memory cell100. Referring toFIG. 5A, the dummy memory cell201is provided with the well region WELL having the N-type well NW and the P-type well PW arranged adjacently to the N-type well NW, and the diffusion layer Diffusion having the P-type diffusion layer PD in the N-type well NW and the N-type diffusion layer ND in the P-type well PW. Also, two polysilicon gates PG1and PG2are arranged to extend in the Y direction across the P-type diffusion layer PD and the N-type diffusion layer ND. In addition, the polysilicon gate PG3serving as the dummy word line DWL extends in the X direction across the P-type well PW and the N-type diffusion layer ND in such a manner as to reach both ends of one side in the dummy memory cell201.

The P-type diffusion layer PD and the polysilicon gate PG1form a dummy load transistor21A-1and the P-type diffusion layer PD and the polysilicon gate PG2form a dummy load transistor21B-1. The N-type diffusion layer ND and the polysilicon gate PG1form a dummy drive transistor22A-1, and the N-type diffusion layer ND and the polysilicon gate PG2form a dummy drive transistor22B-1. The N-type diffusion layer ND and the polysilicon gate PG3form dummy access transistors23A-1and23B-1. Nodes of the gate, source and drain of these transistors are connected to the metal wirings ML (ML1-1, ML2-1, ML3and ML4) in the wiring section through via-contacts CH.

Referring toFIG. 5B, the metal wiring ML1-1is designed in such a manner as not to reach both ends of a dummy memory cell201in the X direction. Thus, a metal wiring ML1-1is prevented from being connected to the power supply wiring VL in a Tap cell or the memory cell100adjacent in the direction of the word line, i.e., in the X direction. A metal wiring ML2-1extends in the X direction in such a manner as to reach both ends of the dummy memory cell, and is grounded, thereby forming a ground wiring GL2of the substrate voltage GND. Furthermore, the metal wiring ML2-1is connected to the sources of the dummy drive transistors22A-1and22B-1through the via-contact CH. The metal wiring ML3is connected to the drain of each of the dummy load transistor21A-1, the dummy drive transistor22A-1and the dummy access transistor23A-1and the gate of each of the dummy load transistor21B-1and the dummy drive transistor22B-1through the via-contacts CH. Additionally, the metal wiring ML4is connected to a drain of each of the dummy load transistor21B-1, the dummy drive transistor22B-1and the dummy access transistor23B-1and the gate of each of the dummy load transistor21A-1and the dummy drive transistor22A-1through the via-contacts CH. A via-contact VH2is adapted to connect the ground wiring GL1(ML2-1) of the first wiring layer ME1and the ground wiring GL2(UML2-1) of the second wiring layer ME2, i.e., an upper metal wiring UML2-1. The second wiring layer ME2includes the dummy bit line DBL, i.e., the upper metal wiring UML1-1extending in the Y direction and the ground wiring GL2serving as the substrate ground GND. The ground wiring GL2, i.e., an upper metal wiring UML2-1is connected to the metal wiring ML1-1through the via-contact VH1. As a consequence, the metal wiring ML1-1serving as a ground wiring GL3is adapted to allow sources of the dummy load transistors21A-1and21B-1to be grounded, i.e., to be connected to the substrate ground GND through the via-contact CH. Moreover, the ground wiring GL1allows sources of the dummy drive transistors22A-1and22B-1to be grounded, i.e., to be connected to the substrate ground GND through the via-contact CH.

FIGS. 6A and 6Bare diagrams showing layouts of the dummy memory cell211.FIG. 6Ashows the layout of the device section andFIG. 6Bshows the layout of the wiring section arranged above the device section. Referring toFIG. 6A, the layout of the device section in the dummy memory cell211is same as or similar to that of the device section in the dummy memory cell201except that a signal in the Low level is supplied to the polysilicon PG3serving as the dummy word line DWL. Referring toFIG. 6B, the metal wiring ML1-2(GL3) extends in the X direction in such a manner as to reach both ends of the dummy memory cell211, and is grounded, thereby forming the ground wiring GL3of the substrate voltage GND. Furthermore, the metal wiring ML1-2is connected to the sources of the dummy load transistors21A-1and21B-1through the via-contact CH. The metal wiring ML2-2(GL1) extends in the X direction in such a manner as to reach both ends of the memory cell, and is grounded, thereby forming the ground wiring GL1of the substrate voltage GND. Furthermore, the metal wiring ML2-2is connected to the sources of the dummy drive transistors22A-1and22B-1through the via-contact CH. The metal wiring ML3is connected to the drain of each of the dummy load transistor21A-1, the dummy drive transistor22A-1and the dummy access transistor23A-1and the gate of each of the dummy load transistor21B-1and the dummy drive transistor22B-1through the via-contacts CH. Additionally, the metal wiring ML4is connected to the drain of each of the dummy load transistor21B-1, the dummy drive transistor22B-1and the dummy access transistor23B-1and the gate of each of the dummy load transistor21A-1and the dummy drive transistor22A-1through the via-contacts CH. Sources of the dummy access transistors23A-1and23B-1are connected to the bit line BL, i.e., an upper metal wiring UML1-2, and the bit B line BBL, i.e., an upper metal wiring UML2-2, through the via-contacts CH, the metal wiring ML and the via-contacts VH, respectively.

In order to stabilize the power supply voltage VDD or the substrate voltage GND in the memory cell100in a memory cell array, Tap regions are typically arranged in the direction of bit line or in the Y direction, for every several memory cell columns.FIGS. 7A and 7Bare diagrams showing layouts of a Tap cell300.FIG. 7Ais a diagram showing the layout of the device section of a well layer WELL, a diffusion layer Diffusion, a polysilicon layer Poly and a contact layer Contact.FIG. 7Bis a diagram showing the layout of the wiring section of the contact layer Contact and the first metal wiring layer ME1in the device section.

Referring toFIG. 7A, the device section in the Tap cell300is provided with the well layer WELL having the N-type well NW and the P-type well PW arranged adjacently to the N-type well NW, and the diffusion layer Diffusion having the N-type diffusion layer ND in the N-type well NW and the P-type diffusion layer PD in the P-type well PW. Furthermore, a polysilicon gate PG extends in the X direction across the P-type well PW serving as the word line WL or dummy word line DWL above the P-type well PW in such a manner as to reach both ends of the Tap cell300. In addition, the N-type diffusion layer ND, the P-type diffusion layer PD and the polysilicon gate PG are connected to the metal wirings ML (ML5, ML6and ML7) of the first metal wiring layer ME1through the via-contacts CH.

Referring toFIG. 7B, the metal wiring ML5(WL or DWL) of the first metal wiring layer ME1extends in the X direction in such a manner as to reach both ends of the Tap cell300, and is connected to the power supply wiring VL or the ground wiring GL. Furthermore, the metal wiring ML5is connected to the N-type diffusion layer ND through the via-contacts CH. The metal wiring ML6extends in the X direction in such a manner as to reach both ends of the Tap cell300, and is connected to the ground wiring GL. Furthermore, the metal wiring ML6is connected to the P-type diffusion layer PD through the via-contacts CH. The metal wiring ML7is arranged in separation from both ends of the Tap cell300, and is connected to the polysilicon gate PG serving as the word line WL or the dummy word line DWL through the via-contacts CH.

FIGS. 8A and 8Bare diagrams showing layouts of a Tap cell301arranged between the dummy memory cells211.FIG. 8Ais a diagram showing the layout of the device section of a well layer WELL, a diffusion layer Diffusion, the polysilicon layer Poly and the contact layer Contact.FIG. 8Bis a diagram showing the layout of the wiring section of the contact layer Contact and the first metal wiring layer ME1in the device section.

Referring toFIG. 8A, the Tap cell301is provided with the well layer WELL having the N-type well NW and the P-type well PW arranged adjacently to the N-type well NW, and the diffusion layer Diffusion having the N-type diffusion layer ND in the N-type well NW and the P-type diffusion layer PD in the P-type well PW. Furthermore, the polysilicon gate PG extends in the X direction across the P-type well PW serving as the dummy word line DWL above the P-type well PW in such a manner as to reach both ends of the Tap cell301. In addition, the N-type diffusion layer ND, the P-type diffusion layer PD and the polysilicon gate PG are connected to the metal wiring ML (ML8, ML9, ML10) of the first metal wiring layer ME1through the via-contacts CH.

Referring toFIG. 8B, the metal wiring ML8of the first metal wiring layer ME1extends in the X direction in such a manner as to reach both ends of the Tap cell301, and is connected to the ground wiring GL3. Furthermore, the metal wiring ML8is connected to the N-type diffusion layer ND through the via-contacts CH. The metal wiring ML9extends in the X direction in such a manner as to reach both ends of the Tap cell301, and is connected to the ground wiring GL1. Furthermore, the metal wiring ML9is connected to the P-type diffusion layer PD through the via-contacts CH. Here, the metal wiring ML8and the metal wiring ML9are connected to each other. The metal wiring ML10is arranged in separation from both ends of the Tap cell301, and is connected to the polysilicon gate PG serving as the word line WL through the via-contacts CH.

FIGS. 9A and 9Bare diagrams showing layouts of a Tap cell302arranged in the Y direction or in the direction of the bit line between the memory cell100and the dummy memory cell201.FIG. 9Ais a diagram showing the layout of the device section, andFIG. 9Bis a diagram showing the layout of the wiring section arranged above the device section ofFIG. 9A.

Referring toFIG. 9A, the Tap cell302is provided with a well layer WELL having the N-type well NW and the P-type well PW arranged adjacently to the N-type well NW, and a diffusion layer Diffusion having the N-type diffusion layer ND in the N-type well NW and the P-type diffusion layer PD in the P-type well PW. The well layer adjacent to the dummy memory cell in the X direction is constituted of the P-type well PW. Furthermore, the polysilicon gate PG extends in the X direction across the P-type well PW serving as the word line WL above the P-type well PW in such a manner as to reach both ends of the Tap cell302. In addition, the N-type diffusion layer ND, the P-type diffusion layer PD and the polysilicon gate PG are connected to the metal wirings ML (ML11, ML12and ML13) of the first metal wiring layer ME1through the via-contacts CH.

Referring toFIG. 9B, the metal wiring ML11of the first metal wiring layer ME1extends in the X direction in such a manner as to reach both ends of the Tap cell302, and is connected to the power supply wiring VL. Furthermore, the metal wiring ML11is connected to the N-type diffusion layer ND through the via-contacts CH. The metal wiring ML12extends in the X direction in such a manner as to reach both ends of the Tap cell301, and is connected to the ground wiring GL1. Also, the metal wiring ML12is connected to the P-type diffusion layer PD through the via-contacts CH. The metal wiring ML13is arranged in separation from both ends of the Tap cell301, and is connected to the polysilicon gate PG serving as the word line WL through the via-contacts CH.

With the above-described configurations, the Tap regions can stabilize the voltages to be supplied to the wells in the memory cell100.

FIG. 10is a diagram showing a configuration of a corner portion of the SRAM including the memory cells100, the dummy memory cells201,211and221, and the Tap cells300,301and302in the first embodiment. The cells having a diagonal line at a left lower portion are forward cells, and the cells having a diagonal line at a left upper portion are reverse cells. The reverse cell is formed by reversing the forward cell with respect to the X direction. The reverse cell is indicated with a symbol [′].

In the SRAM, the forward cells and the reverse cells are alternately arranged adjacently to each other in the direction of the bit line, i.e., in the Y direction, and the same type of cells are arranged adjacently to each other in the direction of the word line, i.e., in the X direction. A dummy memory cell region is arranged around a region of a memory cell array. The dummy memory cells201are arranged in the Y direction in the dummy memory cell region, and in contrast, the dummy memory cells211are arranged in the X direction in the dummy memory cell region. The dummy memory cell221, which is a modification of the dummy memory cell201, is arranged at a corner of the dummy memory cell region. The dummy memory cells201and211are arranged in 1-dimensional line in the dummy memory cell region in this embodiment. However, the dummy memory cells201and211are preferably arranged in a plurality of lines. In this case, the proximity effect of the layout can be effectively attained.

Referring toFIG. 3, the circuit of the dummy memory cell221will be described. In the dummy memory cell221, the dummy word line DWL is used in place of the word line WL in the configuration of the dummy memory cell201. In addition, in the layout of the device section of the dummy memory cell221, the polysilicon gate PG3in the dummy memory cell201shown inFIG. 5Aserves as the dummy word line DWL and the signal in the low level is supplied thereto. Moreover, in the wiring section of the dummy memory cell221, the metal wiring ML1-1in the dummy memory cell201extends to the metal wiring ML8in the Tap cell301arranged adjacently in the direction of the word line, i.e., in the X direction.

A column of the Tap cells302is arranged between the column of the dummy memory cells201and the column of the memory cells100, which are arranged in the Y direction. Also, a column of the Tap cells300is arranged in the memory cell array for every several columns of the memory cells100. Additionally, the Tap cell301is arranged to be adjacent to the end of the column of the Tap cells302between the dummy memory cells221and211or the column of the Tap cells300between the dummy memory cells221. In this embodiment, the dummy memory cells221and211and the Tap cells301are arranged in the X direction in the outermost region as the forward cells.

FIGS. 11A and 11Bshow layouts of a group of the cells surrounded by a dot line A inFIG. 10.FIG. 11Ais a diagram showing the layout of the device section andFIG. 11Bis a diagram showing the layout of the wiring section arranged above the device section.

Referring toFIG. 11B, the wiring sections in the column of the dummy memory cell221, the dummy memory cells201′ and the dummy memory cells201arranged in the Y direction will be described. The upper metal wiring UML2-1of the dummy memory cell221, the upper metal wiring UML2-1of the dummy memory cell201′ and the upper metal wiring UML2-1of the dummy memory cell201are connected to the ground wiring GL2of the substrate voltage GND.

Subsequently, the wiring sections in the row of the dummy memory cell221, the Tap cell301, the dummy memory cells211, . . . and the Tap cell301arranged in the X direction will be described. The metal wiring ML1-1of the dummy memory cell221, the metal wiring ML8of the Tap cell301, the metal wiring ML1-2of the dummy memory cell211and the metal wiring ML8of the Tap cell301are connected to be grounded, thereby forming the ground wiring GL3as the substrate voltage GND. Furthermore, the metal wiring ML2of the dummy memory cell221, the metal wiring ML9of the Tap cell301, the metal wiring ML2-2of the dummy memory cell211are connected mutually to be grounded, thereby forming the ground wiring GL1of the substrate voltage GND. In this manner, the sources of the dummy load transistors21-1(21A-1and21B-1) and the dummy drive transistors22-1(22A-1and22B-1) of the dummy memory cells221and211are grounded.

Next, the wiring sections in the row of the dummy memory cell201′, the Tap cell302′, the memory cell100′, . . . and the Tap cell300′ arranged in the X direction will be described. The metal wiring ML2-1of the dummy memory cell201′, the metal wiring ML12of the Tap cell302′, the metal wiring ML2of the memory cell100′ and the metal wiring ML6of the Tap cell300are connected one after another and are grounded, thereby forming the ground wiring GL1of the substrate voltage GND. Moreover, the metal wiring ML1-1of the dummy memory cell201′ and the metal wiring ML8of the Tap cell302′ are separated while the metal wiring ML1-1of the dummy memory cell201′ is grounded through the ground wiring GL2, thereby forming the ground wiring GL3of the substrate voltage GND. In the meantime, the metal wiring ML11of the Tap cell302′, the metal wiring ML1of the memory cell100′ and the metal wiring ML5of the Tap cell300are connected one after another and finally to the power supply VDD, thereby forming a power supply wiring VL of the power supply voltage VDD. In this way, the sources of the dummy load transistors21-1(21A-1and21B-1) of the dummy memory cell201and the dummy memory cell201′ are grounded in separation from the power supply voltage.

Next, referring toFIG. 11A, the device sections in the row of the dummy memory cell201′, the Tap cell302′, the memory cell100′, . . . and the Tap cell300′ arranged in the X direction will be described. The well layer WELL of the Tap cell302′ adjacent to the N-type well NW of the dummy memory cell201′ is the P-type well PW. Since the P-type well PW is interposed between the N-type well NW of the Tap cell302′ connected to the power supply wiring VL of the power supply voltage VDDand the N-type well NW connected to the ground wiring GL3of the substrate voltage GND of the dummy memory cell201′ adjacent to the Tap cell302′, an NPN junction region is formed between the Tap cell302′ and the dummy memory cell201′, that is, between the power supply voltage VDDand the ground voltage GND. As a consequence, it is possible to prevent any unnecessary current from flowing to a device in the dummy memory cell201′ from the power supply wiring VL.

As described above, the sources of the dummy load transistors21-1of the dummy memory cells201,211and221are separated from the power supply wiring VL, and are connected to the ground wiring GL. Therefore, no leakage current due to the power supply voltage VDDcan be generated in the dummy memory cells201,211and221. Consequently, even when the dummy memory cells201,211and221use the same P-type MOS transistors as those in the memory cell100, namely, have the device sections of the same layout as or the similar layout to that of the memory cell100, the SRAM can be produced with no leakage current. The use of the dummy memory cell having the same layout as or the similar layout to that of the memory cell100allows a more excellent proximity effect. Thus, the operation of the memory cell can be stabilized, so that the defect ratio of the SRAM can be reduced.

Second Embodiment

Next, the SRAM according to the second embodiment of the present invention will be described with reference toFIGS. 12A and 12Bto15A and15B. When the P-type well PW region of the Tap cell302adjacent to the N-type well NW of the dummy memory cell201in the first embodiment can not be prepared due to miniaturization of the cell, the Tap cell303is used in the SRAM in the second embodiment in place of the Tap cell302in the SRAM in the first embodiment. In the Tap cell303, the whole well layer WELL of the Tap cell is a P-type well PW. In addition, a dummy memory cell202is used in place of the dummy memory cell201in the first embodiment. The circuit configuration of the dummy memory cell202in the second embodiment is same as or similar to that of the dummy memory cell201shown inFIG. 3.

FIGS. 12A and 12Bare diagrams showing layouts of the dummy memory cell202.FIG. 12Ashows the layout of the device section, andFIG. 12Bshows the layout of the wiring section arranged above the device section. Referring toFIG. 12A, the layout of the device section in the dummy memory cell202is same as or similar to the layout of the device section in the dummy memory cell201. Referring toFIG. 12B, the metal wiring ML1-2of the dummy memory cell202extends in the X direction in such a manner as to reach both ends of the dummy memory cell211, and is grounded, thereby forming the ground wiring GL3of a substrate voltage GND. Furthermore, the metal wiring ML1-2is connected to the sources of the dummy load transistors21A-1and21B-1through the via-contact CH. The metal wiring ML2-2extends in the X direction in such a manner as to reach both ends of the memory cell, and is grounded, thereby forming the ground wiring GL1of the substrate voltage GND. Furthermore, the metal wiring ML2-2is connected to the sources of the dummy drive transistors22A-2and22B-2through the via-contact CH. The metal wiring ML3is connected to the drain of each of the dummy load transistor21A-1, the dummy drive transistor22A-1and the dummy access transistor23A-1and the gate of each of the dummy load transistor21B-1and the dummy drive transistor22B-1through the via-contacts CH. Additionally, the metal wiring ML4is connected to the drain of each of the dummy load transistor21B-1, the dummy drive transistor22B-1and the dummy access transistor23B-1and the gate of the dummy load transistor21A-1and the dummy drive transistor22A-1through via-contacts CH. The second wiring layer ME2has the dummy bit line DBL, i.e., an upper metal wiring UML1-3, and the dummy bit B line DBBL, i.e., an upper metal wiring UML2-3, which extend in the Y direction.

FIGS. 13A and 13Bare diagrams showing the layouts of the Tap cell303.FIG. 13Ais a diagram showing the layout of the device section, andFIG. 13Bis a diagram showing the layout of the wiring section arranged above the device section.

Referring toFIG. 13A, the device section in the Tap cell303is provided with the well layer WELL including a P-type well PW and a diffusion layer Diffusion having a P-type diffusion layers PD1and PD2. Furthermore, a polysilicon gate PG extends in the X direction across the P-type well PW to function as the word line WL above the P-type well PW in such a manner as to reach both ends of the Tap cell303. In addition, the P-type diffusion layers PD1and PD2and the polysilicon gate PG are connected to the metal wirings ML (ML14, ML15and ML16) of the first metal wiring layer ME1through the via-contacts CH.

Referring toFIG. 13B, the metal wiring ML14of the first metal wiring layer ME1extends in the X direction in such a manner as to be connected to the metal wiring ML1-2, i.e., the ground wiring GL3of the dummy memory cell202adjacent to the Tap cell303while being separated from the power supply wiring VL of the adjacent memory cell100, i.e., the metal wiring ML1. Furthermore, the metal wiring ML14is connected to the P-type diffusion layer PD through the via-contacts CH. The metal wiring ML15extends in the X direction in such a manner as to reach both ends of the Tap cell303, and is connected to the ground wiring GL1. Furthermore, the metal wiring ML15is connected to the P-type diffusion layer PD through the via-contacts CH. Here, the metal wiring ML14and the metal wiring ML15are connected to each other. The metal wiring ML16is arranged in separation from both ends of the Tap cell303, and is connected to the polysilicon gate PG serving as the word line WL through the via-contacts CH.

FIG. 14is a diagram showing a configuration of a corner portion of the SRAM including the memory cells100, the dummy memory cells202,211and221, and the Tap cells300,301and303in the second embodiment. The cells having a diagonal line at a left lower portion are forward cells and the cells having a diagonal line at a left upper portion are reverse cells. The reverse cell is formed by reversing the forward cell with respect to the X direction. The reverse cell is indicated with a symbol [′].

In the SRAM, a row of the forward cells and a row of the reverse cells are alternately arranged to each other in the direction of the bit line, i.e., in the Y direction. The dummy memory cell region is arranged around a region of the memory cell array. A column of the dummy memory cells202is arranged in the Y direction in the outermost portion of the dummy memory cell region. In contrast, a row of the dummy memory cells211is arranged in the X direction in the outermost region of the dummy memory cell region. The dummy memory cell221, which is a modification of the dummy memory cell201, is arranged at a corner of the dummy memory cell region. A column of the Tap cells303is arranged between the column of the dummy memory cells202and the column of the memory cells100, which are arranged in the Y direction. Additionally, the Tap cell301is arranged between the dummy memory cell221and the dummy memory cell211at the end of the column of the Tap cells303. Moreover, a column of the Tap cells300is arranged every several columns of the memory cells100. The Tap cell301is arranged between the dummy memory cells221at the end of the column of the Tap cells301. The outermost dummy memory cells211and221and the outermost Tap cell301arranged in the X direction are the forward cells.

FIGS. 15A and 15Bshow layouts of a group of the cells surrounded by a dot line B inFIG. 14.FIG. 15Ais a diagram showing the layout of the device section, andFIG. 15Bis a diagram showing the layout of the wiring section arranged above the device section. Referring toFIG. 15B, the wiring section in the row of the dummy memory cell221, the Tap cell301, the dummy memory cell211, . . . and the Tap cell301arranged in the X direction will be described. The metal wiring ML1of the dummy memory cell221, the metal wiring ML8of the Tap cell301, the metal wiring ML1-2of the dummy memory cell211and the metal wiring ML8of the Tap cell301are connected to be grounded, thereby forming the ground wiring GL3of the substrate voltage GND. Furthermore, the metal wiring ML2of the dummy memory cell221, the metal wiring ML9of the Tap cell301, the metal wiring ML2-2of the dummy memory cell211and the metal wiring ML9of the Tap cell301are connected to be grounded, thereby forming the ground wiring GL1of the substrate voltage GND. In this way, the sources of the dummy load transistors21-1and the dummy load transistors22-1of the dummy memory cell211and the dummy memory cell221are grounded.

Subsequently, the wiring section of a row of the dummy memory cell202′, the Tap cell303′, the memory cell100′, . . . and the Tap cell300′ arranged in the X direction will be described. The metal wiring ML2-2of the dummy memory cell202′, the metal wiring ML15of the Tap cell303′, the metal wiring ML2of the memory cell100′ and the metal wiring ML6of the Tap cell300′ are connected to be grounded, thereby forming the ground wiring GL1of the substrate voltage GND. Moreover, the metal wiring ML1-2of the dummy memory cell202′ and the metal wiring ML14of the Tap cell303′ are connected to each other, and is grounded, thereby forming the ground wiring GL3of the substrate voltage GND. The metal wiring ML14of the Tap cell303′ and the metal wiring ML1of the memory cell100′ are separated, while the metal wirings ML1of the memory cells100′ and the metal wiring ML5of the Tap cell300′ are connected to the power supply VDD, thereby forming the power supply wiring VL of the power supply voltage VDD. In this way, the sources of the dummy load transistors21-1of the dummy memory cell202′ are grounded in separation from the power supply.

Next, referring toFIG. 15A, the device sections in the row of the dummy memory cell202′, the Tap cell303′, the memory cell100′, . . . and the Tap cell300′ arranged in the X direction will be described. The well layer WELL of the Tap cell303′ adjacent to the N-type well NW of the memory cell100′ is the P-type well PW. As a consequence, an NP junction region is formed between the power supply wiring VL of the power supply voltage VDDand the ground wiring GL3of the substrate voltage GND, thereby preventing any unnecessary current from flowing into the dummy memory cells202′ from the power supply wiring VL through the Tap cell303′.

As described above, the sources of the dummy load transistors21-1of the dummy memory cells202,211and221are separated from the power supply wiring VL, and are connected to the ground wiring GL. Therefore, any leakage current due to the power supply voltage VDDcannot be generated in the dummy memory cells202,211and221. Unlike the first embodiment, there is a case that a P-type well PW region of the Tap cell302adjacent to the N-type well NW region of the dummy memory cell201cannot be formed due to the miniaturization of the device section. Even in such a case, in the second embodiment, the SRAM can be produced by the use of the same P-type MOS transistor as the memory cell100, without any leakage current due to the power supply voltage VDD. That is, the SRAM has the device section of the same layout as or the similar layout to that of the memory cell100. Furthermore, the use of the dummy memory cell having the same layout as or the similar layout to that of the memory cell100can produce a more excellent proximity effect.

Third Embodiment

Next, the SRAM according to the third embodiment of the present invention will be described below with reference toFIGS. 16toFIGS. 21A and 21B. The SRAM in the third embodiment includes the memory cells100, each of which uses the load transistors11of a P-type MOS transistor, and the dummy memory cells, each of which dummy load transistors21of the N-type MOS transistor.FIG. 16is a circuit diagram showing the dummy memory cell203used in the SRAM in the third embodiment. The dummy memory cell203in the third embodiment is provided with dummy inverters20-2(20A-2and20B-2) corresponding to the inverters10(10A and10B) in the memory cell and dummy access transistors23-2(23A-2and23B-2) corresponding to the access transistors13(13A and13B). The dummy inverters20A-2and20A-2are cross-connected to each other, and the gates of the dummy access transistors23A-2and23B-2are connected to the word line WL.

Referring toFIG. 16, the dummy inverters20-2includes dummy load transistor21-2(21A-2and21B-2), which are the N-type MOS transistor, and dummy drive transistors22-2(22A-2and22B-2), which are the N-type MOS transistor. Sources of the dummy load transistors21-2and the dummy drive transistors22-2are grounded. A source of the dummy access transistor23A-2(or23B-2) is separated from the dummy bit line DBL (or the dummy bit B line DBBL). A WORD signal is supplied to the word line WL.

FIG. 17is a circuit diagram showing a dummy memory cell212in the third embodiment. In the dummy memory cell212, a dummy word line DWL is provided in place of the word line in the configuration of the dummy memory cell203, and further, the bit line BL and the bit B line BBL are provided in place of the dummy bit line DBL and the dummy bit B line DBBL, respectively. The bit signal BIT and the bit B signal BITB are supplied to the bit line BL and the bit B line BBL, respectively. The dummy inverters20A-2and20B-2are cross-connected to each other, and the dummy access transistors23A-2and23B-2are connected to the dummy word line DWL. The WORD signal of the Low level is supplied to the dummy word line DWL, so that the dummy access transistors23A-2and23B-2are always turned off. Moreover, a source of the dummy access transistor23A-2(or23B-2) is connected to the bit line BL (or the bit B line BBL).

FIGS. 18A and 18Bare diagrams showing layouts of the dummy memory cell203.FIG. 18Ais a diagram showing a layout of a device section which is provided with a well layer WELL, a diffusion layer Diffusion, a polysilicon layer Poly and a contact layer Contact.FIG. 18Bis a diagram showing a layout of a wiring section which is provided with a first metal wiring layer ME1, a via-contact layer VIA and a second metal wiring layer ME2, which are laminated from the contact layer Contact of the device section.

Referring toFIG. 18A, the dummy memory cell203is provided with a well layer WELL including a P-type well PW and a diffusion layer Diffusion including N-type diffusion layers ND1and ND2. Two polysilicon gates PG1and PG2are arranged in the Y direction across the N-type diffusion layers ND1and ND2. In addition, the polysilicon gate PG3serving as the word line WL extends in the X direction across the N-type diffusion layer ND in such a manner as to reach both ends of the dummy memory cell203.

The N-type diffusion layer ND (ND1and ND2) and the polysilicon gate PG (PG1to PG3) form the N-type MOS transistors. That is to say, the N-type diffusion layer ND1and the polysilicon gate PG1form a dummy load transistor21A-2, and the N-type diffusion layer ND1and the polysilicon gate PG2form a dummy load transistor21B-2. Furthermore, the N-type diffusion layer ND2and the polysilicon gates PG1and PG2form the N-type MOS transistors22A-2and22B-2. In other words, the N-type diffusion layer ND2and the polysilicon gate PG1form the dummy drive transistor22A-2and the dummy access transistor22B-2. Moreover, the N-type diffusion layer ND2and the polysilicon gate PG2form the dummy drive transistor12B. Also, the N-type diffusion layer ND2and the polysilicon gate PG3form the dummy access transistors23A-2and23B-2. A node of each of the gates, sources and drains of the transistors is connected to the metal wiring ML in the wiring section through the via-contact CH.

Referring toFIG. 18B, the metal wiring ML1-1is designed in such a manner as not to reach both ends of the dummy memory cell203, so that it is prevented from being connected to an adjacent Tap cell in the direction of the word line, i.e., in the X direction or the power supply wiring VL of the memory cell100. The metal wiring ML2-1extends in the X direction in such a manner as to reach both ends of the dummy memory cell, and is grounded, thereby forming the ground wiring GL1of the substrate voltage GND. Furthermore, the metal wiring ML2-1is connected to the sources of the dummy drive transistors22A-2and22B-2through the via-contact CH. The metal wiring ML3is connected to a drain of each of the dummy load transistor21A-2, the dummy drive transistor22A-2and the dummy access transistor23A-2and a gate of each of the dummy load transistor21B-2and the dummy drive transistor22B-2through the via-contacts CH. Additionally, the metal wiring ML4is connected to a drain of each of the dummy load transistor21B-2, the dummy drive transistor22B-2and the dummy access transistor23B-2and a gate of each of the dummy load transistor21A-2and the dummy drive transistor22A-2through the via-contacts CH. A via-contact VH2is adopted to connect the ground wiring GL1of the first wiring layer ME1and the ground wiring GL2of the second wiring layer ME2to each other. The second wiring layer ME2includes the dummy bit line DBL, i.e., an upper metal wiring UML1-1and the ground wiring GL2, i.e., an upper metal wiring UML2-1of the substrate ground GND, which extend in the Y direction. The ground wiring GL2is connected to the metal wiring ML1-1through the via-contact VH1. As a consequence, the sources of the dummy load transistors21A-2and21B-2are connected to the metal wiring ML1-1serving as the ground wiring GL3through the via-contact CH, and is grounded. Moreover, the sources of the dummy drive transistors22A-2and22B-2are connected to the ground wiring GL1through the via-contact VH2and the via-contact CH, and are grounded.

FIGS. 19A and 19Bare diagrams showing layouts of the dummy memory cell212in the third embodiment.FIG. 19Ashows the layout of a device section, andFIG. 19Bshows the layout of a wiring section arranged above the device shown inFIG. 19A.

Referring toFIG. 19A, the layout of the device section in the dummy memory cell212is identical to the layout of the device section in the dummy memory cell203except that the signal of the Low level is supplied to the polysilicon PG3serving as the dummy word line DWL. Referring toFIG. 19B, the metal wiring ML1-2extends in the X direction in such a manner as to reach both ends of the dummy memory cell212, and is grounded, thereby forming the ground wiring GL3of the substrate voltage GND. Furthermore, the metal wiring ML1-2is connected to the sources of the dummy load transistors21A-2and21B-2through the via-contact CH. The metal wiring ML2-2extends in the X direction in such a manner as to reach both ends of the memory cell, and is grounded, thereby forming the ground wiring GL1of the substrate voltage GND. Furthermore, the metal wiring ML2-2is connected to the sources of the dummy drive transistors22A-2and22B-2through the via-contact CH. The metal wiring ML3is connected to the drain of each of the dummy load transistor21A-2, the dummy drive transistor22A-2and the dummy access transistor23A-2and the gate of each of the dummy load transistor21B-2and the dummy drive transistor22B-2through the via-contacts CH. Additionally, the metal wiring ML4is connected to the drain of each of the dummy load transistor21B-2, the dummy drive transistor22B-2and the dummy access transistor23B-2and the gate of each of the dummy load transistor21A-2and the dummy drive transistor22A-2through the via-contacts CH. The sources of the dummy access transistors23A-2and23B-2are connected to the bit line BL, i.e., the upper metal wiring UML1-2and the bit B line BBL, i.e., the upper metal wiring UML2-2through the via-contacts CH, the metal wirings ML and the via-contacts VH, respectively.

FIG. 20is a diagram showing a configuration of a corner portion of the SRAM including the memory cell100, the dummy memory cells203,212and222, and the Tap cell300in the third embodiment. The cell that has a diagonal line at lower left corner of the cell area is a forward cell. In contrast, the cell that has a diagonal line at the upper left corner of the cell is a reverse cell. The reference numeral of the reverse cell has an apostrophe attached to reference numeral of the forward cell.

In the SRAM, a row of the forward cells and a row of the reverse cells are arranged alternately in the direction of the bit line, i.e., in the Y direction. A dummy memory cell region is arranged around a region of the memory cell array. A column of the dummy memory cells203is arranged in the Y direction of the dummy memory cell region. In contrast, the dummy memory cell212is arranged in the X direction of the dummy memory cell region. The dummy memory cell222, which is a modification of the dummy memory cell203, is arranged at a corner of the dummy memory cell region. The dummy memory cells203,212and222are arranged in one line in the dummy memory cell region in the present embodiment. However, the dummy memory cells203,212and222may be preferably arranged in a plurality of lines. The dummy memory cells are arranged in a plurality of arrays, thereby effectively exhibiting the proximity effect of the layout.

Referring toFIG. 16, the circuit of the dummy memory cell222is configured by replacing the word line WL in the configuration of the dummy memory cell203with the dummy word line DWL. In addition, the layout of the device section is arranged such that the signal of the Low level is supplied to the polysilicon gate PG3serving as the dummy word line DWL in the configuration of the dummy memory cell203referring toFIG. 18A. Moreover, the wiring section of the dummy memory cell222is configured such that the metal wiring ML1-1in the dummy memory cell203extends toward the metal wiring ML1-2in the dummy memory cell212arranged adjacently in the direction of the word line, i.e., in the X direction referring toFIG. 18B.

A column of the Tap cells300is arranged at the outermost portion of a dummy memory cell region, and extends in the Y direction. Moreover, the column of the Tap cells300is arranged every several columns of the memory cells100. An interval between the columns of the Tap cells300, i.e., the number of memory cells100between the columns of the Tap cells300in the X direction is determined such that the performance of all of the memory cells such as frequency characteristics and voltage characteristics can be sufficiently exhibited. Additionally, a row of the outermost dummy memory cells212and222and the outermost Tap cell300arranged in the X direction is the forward cells.

FIGS. 21A and 21Bshow the layouts of a group of the cells surrounded by a dot line C inFIG. 20.FIG. 21Ais a diagram showing the layout of the device section which is provided with a well layer WELL, a diffusion layer Diffusion, a polysilicon layer Poly and a contact layer Contact.FIG. 21Bis a diagram showing the layout of the wiring section which is provided with a contact layer Contact of the device, a first metal wiring layer ME1, a via-contact layer VIA and a second metal wiring layer ME2.

Referring toFIG. 21B, the wiring section in the column of the dummy memory cell222, the dummy memory cell203′ and the dummy memory cell203. . . arranged in the Y direction will be described. The upper metal wiring UML2of the dummy memory cell222, the upper metal wiring UML2-1of the dummy memory cell203′ and the upper metal wiring UML2-1of the dummy memory cell203are connected to be grounded, thereby forming the ground wiring GL2of the substrate voltage GND.

Subsequently, the wiring section in the row of the Tap cell300, the dummy memory cell222and the dummy memory cell212. . . arranged in the X direction will be described. The metal wiring ML5of the Tap cell300is connected to the power supply VDD, thereby forming the power supply wiring VL. The metal wiring ML1of the dummy memory cell222and the metal wiring ML1-2of the dummy memory cell212are connected to be grounded, thereby forming the ground wiring GL3of the substrate voltage GND. At this time, the metal wiring ML5of the Tap cell300and the metal wiring ML1-1of the dummy memory cell222are separated from each other. Furthermore, the metal wiring ML6of the Tap cell300, the metal wiring ML2-1of the dummy memory cell222and the metal wiring ML2-2of the dummy memory cell212are connected to be grounded, thereby forming the ground wiring GL1of the substrate voltage GND. In this way, the sources of the dummy load transistors21-2of the dummy memory cell212and the dummy memory cell222is grounded.

Next, the wiring sections in the row of the Tap cell300′, the dummy memory cell203′ and the memory cell100′ . . . arranged in the X direction will be described. The metal wiring ML6of the Tap cell300′, the metal wiring ML2-1of the dummy memory cell203′ and the metal wiring ML2of the memory cell100′ are connected one after another to be grounded, thereby forming the ground wiring GL1of the substrate voltage GND. The metal wiring ML5of the Tap cell300′ and the metal wiring ML1of the memory cell100′ are connected to the power supply VDDI thereby forming the power supply wiring VL of the power supply voltage VDD. Moreover, the metal wiring ML1-1of the dummy memory cell203′ is separated from the metal wiring ML5of the Tap cell300′ and the metal wiring ML1of the memory cell100′, while the metal wiring ML1-1of the dummy memory cell203′ is grounded through the ground wiring GL3, thereby forming the ground wiring GL3of the substrate voltage GND. In this way, the sources of the dummy load transistors21-2of the dummy memory cell203and the dummy memory cell203′ are grounded in separation from the power supply VDD.

Referring toFIG. 21A, the device section in the row of the Tap cell300′, the dummy memory cell203′ and the memory cells100′ . . . arranged in the X direction will be described. The well layer WELL of the dummy memory cell203′ adjacent to the N-type well NW of the memory cell100′ is the P-type well PW. In addition, the well layer WELL of the dummy memory cell203′ adjacent to the N-type well NW of the Tap cell300′ is the P-type well PW. As a consequence, the NPN junction region is formed between the power supply wiring VL of the power supply voltage VDDand the ground wiring GL3of the substrate voltage GND, thereby preventing any unnecessary current from flowing into the device section in the dummy memory cell203′ from the power supply wiring VL through the memory cell100′ or the Tap cell300′.

As described above, the sources of the dummy load transistors21-2in the dummy memory cells203,212and222are separated from the power supply wiring VL, but are connected to the ground wiring GL3. Furthermore, the sources of the dummy drive transistors22-2are connected to the ground wiring GL1. Therefore, no leakage current due to the power supply voltage VDDcan be generated in the dummy memory cells203,212and222. Thus, the operations of the memory cells can be stabilized, so that the defect rate of the SRAM can be reduced.

Fourth Embodiment

Next, the SRAM according to the fourth embodiment of the present invention will be described with reference toFIG. 22toFIGS. 25A and 25B. In the SRAM in the fourth embodiment, a dummy memory cell210having the dummy load transistors21A and21B whose sources are connected to the power supply voltage VDDis arranged in the direction of the word line WL, and further the dummy memory cell203in the third embodiment is arranged in the direction of the bit line.

FIG. 22is a circuit diagram showing the dummy memory cell210arranged in the direction of the word line WL. The dummy memory cell210is provided with the dummy inverters20(20A and20B) corresponding to the inverters10in the memory cell100and the dummy access transistors23(23A and23B) corresponding to the access transistors13. The dummy inverters20A and20B are cross-connected to each other, and the gates of the dummy access transistors23A and23B are connected to the dummy word line DWL. In addition, the output terminal of the dummy inverter20A is grounded. Moreover, the input terminal of the dummy inverter20A connected to the drain of the dummy access transistor23B and the output terminal of the dummy inverter20B is connected to the source of the dummy load transistor21A.

A source of the dummy access transistor23A (or23B) is separated from the bit line BL (or the bit B line BBL). Furthermore, the signal of the Low level is supplied to the dummy word line DWL, so that the dummy access transistors23A and23B are always turned off.

The dummy inverter20includes a dummy load transistor21, which is the P-type MOS transistor, and a dummy drive transistor22, which is the N-type MOS transistor. Sources of the dummy load transistors21A and21B and a drain of the dummy drive transistors22B are connected to the power supply VDD. Additionally, sources of dummy drive transistors22A and22B and a drain of the dummy drive transistor22A are grounded.

FIGS. 23A and 23Bare diagrams showing layouts of the dummy memory cell210having the circuit shown inFIG. 22.FIG. 23Ais a diagram showing a layout of a device section which is provided with a well layer WELL, a diffusion layer Diffusion, a polysilicon layer Poly and a contact layer Contact.FIG. 23Bis a diagram showing a layout of a wiring section which is provided with a first metal wiring layer ME1, a via-contact layer VIA and a second metal wiring layer ME2.

Referring toFIG. 23A, the layout of the device section in the dummy memory cell210is identical to the layout of the device in the memory cell100other than that the signal of the Low level is supplied to a polysilicon gate PG3serving as the dummy word line DWL.

Referring toFIG. 23B, the wiring section is identical to the wiring section of the memory cell100. In the first metal wiring layer ME1, a metal wiring ML1-0extends in the X direction in such a manner as to reach both ends of the dummy memory cell, thereby forming the power supply wiring VL connected to the power supply VDD. Moreover, the metal wiring ML1-0is connected to the sources of the dummy load transistors21A and21B through the via-contact CH. The metal wiring ML2-0is grounded in such a manner as to reach both ends of the dummy memory cell, thereby forming the ground wiring GL of the substrate voltage GND. Furthermore, the metal wiring ML2-0is connected to the sources of the dummy drive transistors22A and22B through the via-contact CH. The metal wiring ML3-0is connected to a drain of each of the dummy load transistor21A, the dummy drive transistor22A and the dummy access transistor23A and a gate of each of the dummy load transistor21B and the dummy drive transistor22B through via-contacts CH. Additionally, the metal wiring ML4-0is connected to a drain of each of the dummy load transistor21B, the dummy drive transistor22B and the dummy access transistor23B and a gate of each of the dummy load transistor21A and the dummy drive transistor22A through via-contacts CH. In the second metal wiring layer, the bit line BL and the bit B line BBL extend in the Y direction in such a manner as to reach both ends of the cell. Additionally, the metal wiring ML4-0of the dummy memory cell210is connected to the metal wiring ML1-0serving as the power supply wiring VL, and is connected to the power supply VDD. In addition, the metal wiring ML3-0is connected to the metal wiring ML2-0serving as the ground wiring GL, and is grounded.

FIG. 24is a diagram showing a configuration of a corner portion of the SRAM including the memory cells100, the dummy memory cells203and210, and the Tap cells300in the fourth embodiment. The cell having a diagonal line at the lower left corner is a forward cell. In contrast, the cell having a diagonal line at the upper left corner is a reverse cell. The reverse cell is obtained by reversing the forward cell with respect to the X direction. The reference numeral of the reverse cell has an apostrophe attached to reference numeral of the forward cell.

In the SRAM, a row the forward cells and a row of the reverse cells are alternately arranged adjacently to each other in the direction of the X direction. The dummy memory cell region is arranged outside of the memory cell array region. A column of the dummy memory cells203is arranged in the Y direction of the dummy memory cell region. In contrast, a row of the dummy memory cells210is arranged in the X direction of the dummy memory cell region. The column of the Tap cells300is arranged in the outer portion of the column of the dummy memory cells203, which is arranged in the Y direction. Moreover, another column of the Tap cells300is arranged every several columns of the memory cells100. An interval between the columns of the Tap cells300, i.e., the number of the memory cells100between the number of Tap cells300in the X direction is determined such that the performance of all of the memory cells such as frequency characteristics and voltage characteristics can be sufficiently exhibited. Additionally, the outermost dummy memory cells203and210and the outermost Tap cell300arranged in the X direction are the reverse cells.

FIGS. 25A and 25Bshow layouts of a group of the cells surrounded by a dot line D inFIG. 24.FIG. 25Ais a diagram showing the layout of the device section, andFIG. 25Bis a diagram showing the layout of the wiring section arranged above the device section. Referring toFIG. 25B, the wiring section in the column of the dummy memory cells203′ . . . arranged in the Y direction will be described. The upper metal wirings UML2-1of the dummy memory cells203′ and203are connected one after another to be grounded, thereby forming the ground wiring GL2of the substrate voltage GND.

Subsequently, the wiring section in the row of the Tap cell300′, the dummy memory cell203′ and the dummy memory cell210′ . . . arranged in the X direction will be described. The metal wiring ML6of the Tap cell300′, the metal wiring ML2-1of the dummy memory cell203′ and the metal wiring ML2-0of the dummy memory cells210′ are connected to be grounded, thereby forming the ground wiring GL1of the substrate voltage GND. The metal wirings ML1-0of the dummy memory cell210′ are connected to the power supply VDD, thereby forming the power supply wiring VL. The metal wiring ML1-1of the dummy memory cell203′ is grounded, thereby forming the ground wiring GL3of the substrate voltage GND. At this time, the metal wiring ML1-1of the dummy memory cell203′ is separated from the metal wiring ML5of the Tap cell300and the metal wiring ML1-0of the dummy memory cell210′. In this manner, the sources of the dummy load transistors21-2of the dummy memory cell203′ is grounded, and the sources of the dummy load transistors21of the dummy memory cell210′ is connected to the power supply wiring VL.

Next, the wiring section in the row of the Tap cell300, the dummy memory cell203and the memory cell100. . . arranged in the X direction will be described. The metal wirings ML1of the memory cell100are connected to the power supply VDD, thereby forming the power supply wiring VL of the power supply voltage VDD. Moreover, the metal wiring ML1-1of the dummy memory cell203is separated from the metal wiring ML5of the Tap cell300and the metal wiring ML1of the memory cell100, and is grounded through the ground wiring GL2, thereby forming the ground wiring GL3of the substrate voltage GND. Additionally, the metal wiring ML6of the Tap cell300, the metal wiring ML2-1of the dummy memory cell203and the metal wiring ML2of the memory cell100are connected to be grounded, thereby forming the ground wiring GL1of the substrate voltage GND. In this way, the sources of the dummy load transistors21-2of the dummy memory cell203and the dummy memory cell203′ is grounded in separation from the power supply VDDand the sources of the dummy load transistors21of the dummy memory cell210′ is connected to the power supply wiring VL.

Referring toFIG. 25A, the device sections in the row of the Tap cell300, the dummy memory cell203and the memory cell100. . . arranged in the X direction will be described. The well layer WELL of the dummy memory cell203′ adjacent to the N-type well NW of the memory cell100is the P-type well PW. In addition, the well layer WELL of the dummy memory cell203′ adjacent to the N-type well NW of the Tap cell300′ is the P-type well PW. As a consequence, the NPN junction region is formed between the power supply wiring VL of the power supply voltage VDDand the ground wiring GL3of the substrate voltage GND, thereby preventing any unnecessary current from flowing into the dummy memory cell203from the power supply wiring VL through the memory cell100or the Tap cell300.

As described above, in the SRAM of the fourth embodiment, the sources of the dummy load transistors21in the dummy memory cells210arranged in the direction of the word line WL are connected to the power supply wiring VL. However, the sources of the dummy load transistors21-1in the dummy memory cells203arranged in the direction of the bit line BL are separated from the power supply wiring VL, but are connected to the ground wiring GL3. Therefore, no leakage current due to the power supply voltage VDDcan be generated in the dummy memory cell203, although there remains a possibility of generation of a leakage current due to the power supply voltage VDDin the dummy memory cell210. Thus, it is possible to eliminate the leakage current at a part of the dummy memory region, so that the operation of the memory cell can be more stabilized and the defect rate of the memory cells in the SRAM can be more reduced in comparison with the conventional SRAM.

Although the embodiments according to the present invention have been described above in detail, specific configurations are not limited to the above-described embodiments. The present invention encompasses modifications and alterations without departing from the scope of the present invention. In the above-described embodiments, the leakage current is prevented from being generated in the dummy memory cell by connecting the source of the dummy load transistor and the source of the dummy drive transistor to the substrate voltage GND. Alternatively, a leakage current may be prevented from being generated in a dummy memory cell by setting the source of the dummy load transistor and the source of the dummy drive transistor to the same voltage of the power supply voltage VDD. Otherwise, the dummy load transistor may be replaced with the dummy load resistor. Or, the gate of the dummy load transistor in the above-described embodiments may be grounded.