Display device and E-book reader provided therewith

An object is to provide a display device in which deterioration in display quality due to a change in voltage applied is reduced and a lower visible efficiency in changing display is prevented. The display device has a display controller configured to make the display portion perform display by switching a first still image display period including a writing period in which a first image signal is written and a holding period in which the first image signal is held, and a second still image display period including a writing period in which a second image signal is written and a holding period in which the second image signal is held. The display controller is configured to make a length of the writing period of the first still image display period and a length of the writing period of the second still image display period different from each other.

TECHNICAL FIELD

The present invention relates to a driving method of a display device. Further, the present invention relates to a display device. Furthermore, the present invention relates to an e-book reader provided with a display device.

BACKGROUND ART

In recent years, as a digitization technology has been developed, image data and text data of a newspaper, a magazine, and the like can be provided as electronic data. The contents of such a kind of electronic data are generally read by being displayed on a display device included in a television, a personal computer, a portable electronic terminal, or the like.

Display media such as a liquid crystal display device are very different form paper media such as a newspaper and a magazine. One of features of display media is that pages are switched on a screen of a display device, which is very different from the way paper media usually are handled. Such a difference in the way they are handled causes the display media a problem such as a lower visible efficiency in text reading, sentence comprehension, or image recognition than the paper media.

It is important for display media such as a liquid crystal display device to increase in visible efficiency and to reduce in power consumption in order to be conveniently used. As a countermeasure, a technique is disclosed in which power consumption is decreased by reduction in refresh rate, that is, the number of times of rewriting an image data (see Patent Document 1).

DISCLOSURE OF INVENTION

According to Patent Document 1, power consumption can be reduced by lowering the refresh rate in displaying a still image. However, in a structure in Patent Document 1, because a transistor used for a pixel is formed using amorphous silicon, it is possible that voltage applied to a liquid crystal element which is a display element is decreased due to the off-state current of the transistor. In addition, in Patent Document 1, because time needed for rewriting an image is short, an image is momentarily updated to a newly written image when different images are switched by supplying different image signals between a period and the next period to perform display; which is different from a paper medium.

An object of an embodiment of the present invention is to provide a display device in which deterioration in display quality due to a change in voltage applied to a display element is reduced and a lower visible efficiency in changing display is prevented

An embodiment of the present invention is a display device which has a display controller configured to make the display portion perform display by switching a first still image display period comprising a writing period in which a first image signal is written and a holding period in which the first image signal is held and a second still image display period comprising a writing period in which a second image signal is written and a holding period in which the second image signal is held. Further, the display controller is configured to make a length of the writing period of the first still image display period and a length of the writing period of the second still image display period different from each other.

An embodiment of the present invention is a display device which has a display controller configured to make the display device perform display by switching a first still image display period comprising a writing period in which a first image signal is written and a holding period in which the first image signal is held and a second still image display period comprising a writing period in which a second image signal is written and a holding period in which the second image signal is held. Further, the display controller is configured to make a length of the writing period of the first still image display period and a length of the writing period of the second still image display period different from each other. The display controller includes a switching circuit which is configured to switch a first clock signal and a second clock signal and output the first clock signal or the second clock signal, and a display mode control circuit. The display mode control circuit is configured to make the length of the writing period of the first still image display period and the length of the writing period of the second still image display period different from each other by controlling the switching circuit.

An embodiment of the present invention is a display device which has a display controller for making the display device perform display by switching a first still image display period comprising a writing period in which a first image signal is written and a holding period in which the first image signal is held and a second still image display period comprising a writing period in which a second image signal is written and a holding period in which the second image signal is held. Further, the display controller makes a length of the writing period of the first still image display period and a length of the writing period of the second still image display period different from each other. The display controller includes a reference clock generation circuit which is configured to output a first clock signal, a dividing circuit which is configured to divide the first clock signal and output a second clock signal, a switching circuit which is configured to switch the first clock signal and the second clock signal and output the first clock signal or the second clock signal, and a display mode control circuit. The display mode control circuit is configured to make the length of the writing period of the first still image display period and the length of the writing period of the second still image display period different from each other by controlling the switching circuit.

An embodiment of the present invention may be a display device in which the first image signal of the first still image display period is the same as the first image signal written in the last first still image display period, and in which the second image signal of the second still image display period is different from the first image signal written in the last first still image display period or the second image signal written in the second still image display period.

An embodiment of the present invention may be a display device in which the writing period of the first still image display period is 16.6 milliseconds or less and the writing period of the second still image display period is 1 second or more.

An embodiment of the present invention can provide a display device in which deterioration in display quality due to a change in voltage applied to a display element is reduced and a lower visible efficiency in changing display is prevented.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention can be carried out in many different modes, and it is easily understood by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the purpose and the scope of the present invention. Therefore, this invention is not interpreted as being limited to the description of the embodiments below. Note that in structures of the present invention described below, identical portions are denoted by the same reference numerals in different drawings.

Note that the size, the thickness of a layer, the waveform of a signal, and a region of each structure illustrated in the drawings and the like in the embodiments are exaggerated for simplicity in some cases. Therefore, embodiments of the present invention are not limited to such scales.

Note that in this specification, terms such as “first”, “second”, “third”, and “N-th” (N is a natural number) are used in order to avoid confusion among components and do not limit the number of the components.

In this embodiment, operation of a display device will be described with reference to a schematic view, a timing chart, a block diagram, a flowchart, or the like.

First,FIGS. 1A to 1Cillustrate schematic views of a driving method of the display device. In this embodiment, a liquid crystal display device is described as an example of the display device.

Operation of the liquid crystal display device in this embodiment is roughly divided into an operation in a first still image display period101(also referred to as a first period) and an operation in a second still image display period102(also referred to as a second period) as illustrated inFIG. 1A.

The first still image display period101is a period during which one still image is displayed for sequential frame periods in which one image is displayed. An image signal (hereinafter, a first image signal) is written at a uniform refresh rate in the first still image display period101. Accordingly, in one frame period in any one of the first still image display periods101, periods103in which the first image signal that is the same image signal as the image signal in the last frame period is written are provided sequentially. Here, one frame period means a period during which an image displayed by sequential writing of image signals to a plurality of pixels in a display panel is renewed.

The second still image display period102is a period during which one frame period or sequential one frame periods in which an image is different from an image displayed by an image signal of the last frame period is/are provided, and one still image is displayed. In the second still image display period102, when an image signal written in the last frame period is the first image signal, a different signal (a second image signal) is written. Accordingly, in a period104in which the second image signal is written and which is one frame period in the second still image display period102, a second image signal is written which is a signal different from the signal of the last frame period of a period105. Note that a period106inFIG. 1Ais the same as the period103in that the same image signal as that in the last frame period (in this case, the period104) is written. Note that in the case where frame periods for displaying different images are provided sequentially, the periods104in the second still image display period are sequentially provided, so that the second image signal is written which is different from the second image signal written in the last frame period.

Next, the period103in the first still image display period101is described with reference toFIG. 1B. The period103corresponding to one frame period of the first still image display period101includes a writing period and a holding period. Note that inFIG. 1B, the period103includes a writing period W1(denoted by W1inFIG. 1B) in which the first image signal is written to a pixel and a holding period H1(denoted by H1inFIG. 1B) in which the first image signal written to the pixel is held. In the writing period W1, the first image signal is sequentially written to the first to n-th rows of pixels in a display panel. In the writing period W1, in order that the same image as the most previously written image is displayed, it is preferable that the first image signal be written within a short time so that a viewer does not feel a lower visible efficiency in changing display. Specifically, in the writing period W1in which the first image signal is written in the first still image display period101, writing is preferably performed at a speed of 16.6 milliseconds or less at which flickers do not occur. Further, it is preferable that as for the first image signal applied to a liquid crystal element be held by turning off a transistor in the holding period H1. That is to say, in the holding period H1, it is preferable that the first image signal be held by taking advantage of extremely small voltage drop due to the leakage current of the transistor. The holding period H1in which the first image signal is held in the first still image display period101is preferably 1 second or more, because such a length of time does not cause reduction in image quality due to a decrease in voltage applied to the liquid crystal element caused by cumulative elapsed time, and such a length of time can make eyestrain less severe.

Next, the period104in the second still image display period102is described with reference toFIG. 1C. The period104corresponding to one frame period of the second still image display period102includes a writing period and a holding period. Note that inFIG. 1C, the period104includes a writing period W2(denoted by W2inFIG. 1C) in which the second image signal is written to a pixel and a holding period H2(denoted by H2inFIG. 1C) in which the second image signal written to the pixel is held. In the writing period W2, the second image signal is sequentially written to the second to n-th rows of pixels in a display panel. In the writing period W2, in order that a different image from the most previously written image is displayed, unlike in the writing period W1, a viewer is allowed to perceive changing of display so that a viewer does not feel a lower visible efficiency in changing display like in the case where a viewer looks at a paper medium. Thus, the writing period W2in which the second image signal is written to a pixel is preferably longer than the writing period W1so that a viewer can perceive changing of display. Specifically, the writing period W2in which the second image signal is written in the second still image display period102is preferably 1 second or more that is the writing speed at which a viewer can perceive the switching. Further, it is preferable that as for the written second image signal, voltage applied to a liquid crystal element be held by turning off the transistor in the holding period H2. That is to say, in the holding period H2, it is preferable that the second image signal be held by taking advantage of extremely small voltage drop due to the leakage current of the transistor. The holding period H2in which the second image signal is held in the second still image display period102is preferably 1 second or more, because such a length of time does not cause reduction in image quality due to a decrease in voltage applied to the liquid crystal element caused by cumulative elapsed time, and such a length of time can make eyestrain less severe.

Next, a signal supplied to a driver circuit in the first still image display period101and the second still image display period102will be described with reference to

FIGS. 2A and 2Billustrating timing charts of a start pulse signal and a clock signal in each period. Note that a waveform of each signal in timing charts illustrated inFIGS. 2A and 2Bis exaggerated for description.

As illustrated inFIG. 2A, in the writing period W1in which the first image signal is written of the period103of the first still image display period101, a start pulse signal and a clock signal for driving a driver circuit such as a shift register circuit, which supplies the first image signal to each pixel in the display panel are supplied. The frequency or the like of the start pulse signal and the clock signal may be set as appropriate in accordance with the length of the writing period and the number of scanned pixels in the display panel. Note that with a structure in which voltage applied to a liquid crystal element is held by turning off the transistor, the start pulse signal and the clock signal can be stopped in the holding period H1in which the first image signal is held of the period103of the first still image display period101. Therefore, power consumption during the holding period H1can be reduced. Note that supply of the first image signal D1may be stopped as well as the start pulse signal and the clock signal so that in the holding period H1, an image is displayed only by holding voltage written in the writing period W1.

As illustrated inFIG. 2B, in the writing period W2in which the second image signal is written of the period104of the second still image display period102, a start pulse signal and a clock signal for driving a driver circuit such as a shift register circuit, which supplies the second image signal to each pixel in the display panel are supplied. The frequency or the like of the start pulse and the clock signal may be set as appropriate in accordance with the length of the writing period and the number of scanned pixels in the display panel. Note that with a structure in which voltage applied to a liquid crystal element is held by turning off the transistor, the start pulse signal and the clock signal can be stopped in the holding period H2in which the second image signal is held of the period104of the second still image display period102. Therefore, power consumption during the holding period H2can be reduced. Note that supply of the second image signal D2may be stopped as well as the start pulse signal and the clock signal so that in the holding period H2, an image is displayed only by holding voltage written in the writing period W2.

Note that as a clock signal supplied to the driver circuit in the second still image display period102, a signal generated by dividing the clock signal supplied to the driver circuit in the first still image display period101may be used. With the structure, clock signals with a plurality of frequencies can be generated without a plurality of clock generation circuits for generating a clock signal, or the like. Note that in this structure, the frequency of the clock signal supplied to the driver circuit in the first still image display period101which is higher than that in the second still image display period102may be applied.

As described above, the structure is applied in which in the writing period W2of the period104of the second still image display period102, the pixels are scanned from the first row to the n-th row for 1 second or more and the second image signal is supplied, so that a viewer can perceive switching of images. The function corresponding to perception of switching pages in a paper medium is applied, so that a lower visible efficiency in changing display is prevented.

Switching between the first still image display period101and the second still image display period102, which is illustrated inFIGS. 1A to 1CandFIGS. 2A and 2B, may be performed by a switching signal input from the outside by operation or the like or may be performed by judging in accordance with an image signal whether the first still image display period101or the second still image display period102is needed. Note that a moving image display period may be included in addition to the first still image display period101and the second still image display period102.

The moving image display period is described. A period301illustrated inFIG. 3Ais regarded as one frame period of the moving image display period. The period301corresponding to one frame period of the moving image display period includes a writing period W (denoted by “W” inFIG. 3A) in which an image signal is written to a pixel. Note that the moving image display period may include a holding period in addition to the writing period W and the holding period is preferably short so that flickers do not occur. In the writing period W, image signals are sequentially written to pixels in a display panel from the first row to the n-th row. In the writing period W, different image signals are input to pixels in sequential frame periods and a viewer perceives a moving image. Specifically, in the writing period W in which the image signal is written in the moving image display period, writing is preferably performed at a speed of 16.6 milliseconds or less at which flickers do not occur.FIG. 3Bshows a timing chart of a start pulse signal and a clock signal in each period so that a signal supplied to a driver circuit in the moving image display period301is described similarly toFIGS. 2A and 2B. As illustrated inFIG. 3B, in the writing period W corresponding to the period301of the moving image display period, a clock signal and a start pulse for driving a driver circuit such as a shift register circuit for supplying image signals (Dn, and Dn+1 to Dn+3) to pixels of the display panel are supplied. The frequency or the like of the start pulse and the clock signal may be set as appropriate in accordance with the length of the writing period and the number of scanned pixels in the display panel.

Next, the first still image display period101and the second still image display period102illustrated inFIGS. 1A to 1CandFIGS. 2A and 2Bare described with reference to a block diagram of a liquid crystal display device for switching operation inFIG. 4. A liquid crystal display device400illustrated inFIG. 4includes a display panel401, a display controller402, a memory circuit403, a CPU404(also referred to as an arithmetic circuit), and an external input device405.

The display panel401includes a display portion406and a driver circuit portion407. The display portion406includes a plurality of gate lines408(also referred to as scan lines), a plurality of source lines409(also referred to as signal lines), and a plurality of pixels410. Each of the plurality of pixels410includes a transistor411, a liquid crystal element412, and a capacitor413. The driver circuit portion407includes a gate line driver circuit414(also referred to as a scan line driver circuit), and a source line driver circuit415(also referred to as a signal line driver circuit).

Note that in the transistor411, an oxide semiconductor is preferably included in a semiconductor layer. When the number of carriers in an oxide semiconductor is made to be extremely small, the off-state current can be reduced. Accordingly, an electric signal such as an image signal can be held for a longer period in the pixel, and a writing interval can be set longer. The structure of the transistor may be an inverted-staggered structure or a staggered structure. Alternatively, a double-gate structure may be used in which a channel region is divided into a plurality of regions and the divided channel regions are connected in series. Alternatively, a dual-gate structure may be used in which gate electrodes are provided over and under the channel region. Further, the transistor element may be used in which a semiconductor layer is divided into a plurality of island-shaped semiconductor layers and which realizes switching operation.

Note that the liquid crystal element412is formed so that a liquid crystal is sandwiched between a first electrode and a second electrode. The first electrode of the liquid crystal element412corresponds to a pixel electrode. The second electrode of the liquid crystal element412corresponds to a counter electrode. The first electrodes and the second electrodes of the liquid crystal elements may each have a shape including a variety of opening patterns. As a liquid crystal material provided between the first electrodes and the second electrodes in the liquid crystal elements, thermotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, anti-ferroelectric liquid crystal, or the like may be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions. Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The first electrode of the liquid crystal element412is formed using a material with a light-transmitting property or a metal with high reflectivity. As examples of the light-transmitting material, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-doped zinc oxide

(GZO), and the like can be given. Aluminum, silver, or the like is used for a metal electrode with high reflectivity. Note that the first electrode, the second electrode, and the liquid crystal material are collectively referred to as a liquid crystal element in some cases.

Note that, for example, the capacitor413includes a pixel electrode and a capacitor line which is additionally provided through an insulating layer. In the case where the off-state current of the transistor411is sufficiently reduced, the capacitor which is intentionally provided can be omitted because a holding period of an electric signal such as an image signal can be longer.

Note that, a liquid crystal display device in which the pixel410includes a liquid crystal element as a display element is assumed and each element is described; however, the element is not limited to a liquid crystal element and various display elements can be used such as an EL element or an electrophoresis element.

To the gate line408, a signal for controlling on/off of the transistor411is supplied from the gate line driver circuit414. To the source line409, an image signal supplied to the liquid crystal element412is supplied from the source line driver circuit415. Note that inFIG. 4, it is preferable that the display portion406be provided over the same substrate as the gate line driver circuit414and the source line driver circuit415, but it is not necessary. When the gate line driver circuit414and the source line driver circuit415are provided over the same substrate as the display portion406, the size of the liquid crystal display device can be reduced because the number of the connection terminals for connection to the outside can be decreased.

The display controller402includes a reference clock generation circuit416, a dividing circuit417, a switching circuit418, a display mode control circuit419, a control signal generation circuit420, and an image signal output circuit421.

The reference clock generation circuit416is a circuit configured to oscillate a clock signal with a constant frequency. The reference clock generation circuit416may have a ring oscillator or a crystal oscillator, for example. The dividing circuit417is a circuit configured to change the frequency of an inputted clock signal. The dividing circuit417may include a counter circuit, for example. The switching circuit418is a circuit configured to switch a clock signal from the reference clock generation circuit416(hereinafter, a first clock signal) and a clock signal from the dividing circuit417(hereinafter, a second clock signal) and output the first clock signal or the second clock signal. The switching circuit418may control conduction or non-conduction with a transistor.

The display mode control circuit419is controlled by the CPU404and is a circuit configured to control a switching of a clock signal, which is output from the switching circuit418. By the control of the switching circuit418, the first clock signal and the second clock signal can be switched, and a mode of a first still image display period and a mode of a second still image display period illustrated inFIGS. 2A and 2Bcan be switched.

The control signal generation circuit420is a circuit which is configured to generate control signals (a start pulse GSP, a start pulse SSP, a clock signal GCK, and a clock signal SCK) for driving the gate line driver circuit414and the source line driver circuit415, on the basis of the first clock signal or the second clock signal which is selected. The image signal output circuit421is a circuit which is configured to read an image signal (Data) from the memory circuit403and output the image signal (Data) to the source line driver circuit415on the basis of the first clock signal or the second clock signal which is selected. Note that the image signal may be appropriately inverted in accordance with dot inversion driving, source line inversion driving, gate line inversion driving, frame inversion driving, or the like so as to be output to the display panel401. Note that power supply potentials (a high power supply potential Vdd, a power supply potential Vss, and a common potential Vcom) are supplied to the display panel401although not illustrated.

The memory circuit403is a circuit which is configured to store an image signal for display with the display panel401. The memory circuit403may include a static memory (SRAM), a dynamic memory (DRAM), a ferroelectric memory (FeRAM), an EEPROM, a flash memory, or the like.

The CPU404controls the display mode control circuit419or the like in accordance with a signal from the external input device405or the like. The external input device405may be an input button, an input keyboard, or a touch panel.

Next, specific operation between blocks in a block diagram inFIG. 4will be described with reference to a flowchart ofFIG. 5. Note that the flowchart ofFIG. 5illustrates a structure in which operation is performed by switching the first still image display period and the second still image display period which are described with reference toFIGS. 1A to 1CandFIGS. 2A and 2B. In the flowchart ofFIG. 5, an operation example of switching from the first still image display period to the second still image display period is explained.

First, a step501inFIG. 5is described. In the step501, a first still image written operation in the first still image display period is performed. The step501corresponds to operation in the writing period W1in which the first image signal is written inFIG. 2A. At this time, inFIG. 4, the display mode control circuit419selects the first clock signal output from the reference clock generation circuit416as a clock signal output from the switching circuit418. With the use of the first clock signal, the first image signal is read from the memory circuit403by the image signal output circuit421and a control signal is generated in the control signal generation circuit420. In the display panel401, an image signal is written at speed at which a viewer does not perceive the writing.

Then, a step502inFIG. 5is described. In the step502, a first still image holding operation in the first still image display period is performed. The step502corresponds to operation in the holding period H1in which the first image signal is held inFIG. 2A. At this time, inFIG. 4, the control signal from the control signal generation circuit420and the image signal from the image signal output circuit421are not output to the display panel401. At this time, the first image signal applied to the liquid crystal element can be held by turning off a transistor, in which an oxide semiconductor is used for a semiconductor layer. Therefore, power consumption can be reduced by deactivating the control signal generation circuit420and the image signal output circuit421. Note that when a holding period is made to be one second or more in the range in which image quality does not deteriorates due to dropping voltage applied to the liquid crystal element by cumulative elapsed time, such a length of time can make eyestrain less severe.

Then, a step503inFIG. 5is described. In the step503, whether the display mode control circuit419changes operation of the switching circuit418or not is judged. Specifically, depending on whether operation of changing pages of an e-book reader is performed by an operation button or the like in the external input device405, whether the CPU404changes operation of the switching circuit418through the display mode control circuit419or not is determined In an example in the step503, because without operation of the external input device405, the CPU404does not control the display mode control circuit419; thus, the first clock signal output from the switching circuit418is not changed. That is to say, a state of the step501is kept. On the other hand, in the case where operation of the external input device405is performed, that is, in the case where operation is performed by an operation button or the like in the external input device405, the CPU404changes operation of the switching circuit418through the display mode control circuit419. Specifically, a clock signal output from the switching circuit418is switched to the second clock signal output from the dividing circuit417.

Next, a step504inFIG. 5is described. In the step504, a second still image written operation in the second still image display period is performed. The step504corresponds to operation in the writing period W2of the second image signal inFIG. 2B. At this time, inFIG. 4, the display mode control circuit419selects the second clock signal output from the dividing circuit417as a clock signal to be output from the switching circuit418. With the use of the second clock signal, the second image signal is read from the memory circuit403by the image signal output circuit421and a control signal or the like is generated in the control signal generation circuit420. In the display panel401, writing speed can be a speed at which a viewer can perceive switching of images. The function corresponds to perception of switching pages in a paper medium, and a lower visible efficiency in changing display is prevented.

Then, a step505inFIG. 5is described. In the step505, a second still image holding operation in the second still image display period is performed. The step505corresponds to operation in the holding period H2in which the second image signal is held inFIG. 2B. At this time, inFIG. 4, the control signal from the control signal generation circuit420and the image signal from the image signal output circuit421are not output to the display panel401. At this time, the second image signal applied to the liquid crystal element can be held by turning off a transistor, in which an oxide semiconductor is used for a semiconductor layer. Therefore, power consumption can be reduced by deactivating the control signal generation circuit420and the image signal output circuit421. Note that when a holding period is made to be one second or more in the range in which image quality does not deteriorates due to dropping voltage applied to the liquid crystal element by cumulative elapsed time, such a length of time can make eyestrain less severe.

Note that in the case where the first image signal is written for display as in the step501, the similar process to the step501and the step502may be performed. Further, in the case where the display mode control circuit419changes operation of the switching circuit418again as in the step503, the similar process to the step504and the step505may be performed.

Next, an advantage obtained by the structure of this embodiment will be described with reference to schematic views ofFIGS. 6A to 6C.

FIG. 6Aillustrates a perspective view of a paper book and expresses the situation in which turning over a page over time is shown. It is apparent withoutFIG. 6A, but a viewer can see letters602in the next page of a paper book601through time needed for turning over a page.

On the other hand, an e-book including a liquid crystal display device has an operation button611and a display panel612as illustrated inFIG. 6B, for example. It is possible that with a structure inFIG. 6Bin which display is momentarily changed by pressing the operation button611, unlike that inFIG. 6A, a viewer feels a lower visible efficiency in changing display. Further, when pages are unintentionally switched, it is possible that a viewer does not recognize the change.

Contrary to the structure illustrated in the schematic view ofFIG. 6B, in a structure of this embodiment, display is changed through display including both a region621in which display is changed and a region622in which display is not changed as illustrated inFIG. 6C, because a writing period of an image signal can be long enough to rewrite an image displayed on a display panel. With a structure in this embodiment, display is performed in the writing operation with the use of a first clock signal from a reference clock generation circuit, and display is changed with the use of the second clock signal from the dividing circuit in a writing operation for renewing an image such as switching pages. As a result, data is gradually written when pages are turned over, so that a viewer can see a state where pages are turned over.

As described above, an embodiment of the present invention can provide a display device in which deterioration in display quality due to a change in voltage applied to a display element is reduced and a lower visible efficiency in changing display is prevented.

In this embodiment, an example of a transistor which can be applied to a display device disclosed in this specification will be described.

FIGS. 7A to 7Deach illustrate an example of a cross-sectional structure of a transistor.

A transistor1210illustrated inFIG. 7Ais a kind of bottom-gate structure transistor and is also called an inverted staggered transistor.

The transistor1210includes, over a substrate1200having an insulating surface, a gate electrode layer1201, a gate insulating layer1202, a semiconductor layer1203, a source electrode layer1205a, and a drain electrode layer1205b. An insulating layer1207is provided to cover the transistor1210and be stacked over the semiconductor layer1203. A protective insulating layer1209is provided over the insulating layer1207.

A transistor1220illustrated inFIG. 7Bhas a kind of bottom-gate structure called a channel-protective type (channel-stop type) and is also referred to as an inverted staggered transistor.

The transistor1220includes, over the substrate1200having an insulating surface, the gate electrode layer1201, the gate insulating layer1202, the semiconductor layer1203, an insulating layer1227that is provided over a channel formation region in the semiconductor layer1203and functions as a channel protective layer, the source electrode layer1205a, and the drain electrode layer1205b. A protective insulating layer1209is provided to cover the transistor1220.

A transistor1230illustrated inFIG. 7Cis a bottom-gate type transistor and includes, over a substrate1200which is a substrate having an insulating surface, a gate electrode layer1201, a gate insulating layer1202, a source electrode layer1205a, a drain electrode layer1205b, and a semiconductor layer1203. An insulating layer1207is provided to cover the transistor1230and be in contact with the semiconductor layer1203. A protective insulating layer1209is provided over the insulating layer1207.

In the transistor1230, the gate insulating layer1202is provided in contact with the substrate1200and the gate electrode layer1201. The source electrode layer1205aand the drain electrode layer1205bare provided in contact with the gate insulating layer1202. The semiconductor layer1203is provided over the gate insulating layer1202, the source electrode layer1205a, and the drain electrode layer1205b.

A transistor1240illustrated inFIG. 7Dis a kind of top-gate structure transistor. The transistor1240includes, over a substrate1200having an insulating surface, an insulating layer1247, a semiconductor layer1203, a source electrode layer1205aand a drain electrode layer1205b, a gate insulating layer1202, and a gate electrode layer1201. A wiring layer1246aand a wiring layer1246bare provided in contact with the source electrode layer1205aand the drain electrode layer1205b, respectively, to be electrically connected to the source electrode layer1205aand the drain electrode layer1205b, respectively.

In this embodiment, an oxide semiconductor is used for the semiconductor layer1203.

As an oxide semiconductor, an In—Sn—Ga—Zn—O-based metal oxide which is a four-component metal oxide; an In—Ga—Zn—O-based metal oxide, an In—Sn—Zn—O-based metal oxide, an In—Al—Zn—O-based metal oxide, a Sn—Ga—Zn—O-based metal oxide, an Al—Ga—Zn—O-based metal oxide, or a Sn—Al—Zn—O-based metal oxide which is a three-component metal oxide; an In—Zn—O-based metal oxide, a Sn—Zn—O-based metal oxide, an Al—Zn—O-based metal oxide, a Zn—Mg—O-based metal oxide, a Sn—Mg—O-based metal oxide, or an In—Mg—O-based metal oxide which is a two-component metal oxide; an In—O-based metal oxide, a Sn—O-based metal oxide, a Zn—O-based metal oxide, or the like can be used. Further, SiO2may be included in a semiconductor of the above metal oxide. Here, for example, an In—Ga—Zn—O-based metal oxide is an oxide including at least In, Ga, and Zn, and there is no particular limitation on the composition ratio thereof. Further, the In—Ga—Zn—O-based metal oxide may include an element other than In, Ga, and Zn.

As the oxide semiconductor, a thin film represented by the chemical formula, InMO3(ZnO)m(m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, M can be Ga, Ga and Al, Ga and Mn, Ga and Co, or the like.

Note that in the structure in this embodiment, the oxide semiconductor is an intrinsic (i-type) or substantially intrinsic semiconductor obtained by removal of hydrogen, which is an n-type impurity, from the oxide semiconductor for high purification so that the oxide semiconductor contains an impurity other than the main component as little as possible. In other words, the oxide semiconductor in this embodiment is a highly purified intrinsic (i-type) semiconductor or close to an intrinsic semiconductor obtained by removing impurities such as hydrogen and water as much as possible, not by adding an impurity element. In addition, the band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, still preferably 3.0 eV or more. Thus, in the oxide semiconductor, the generation of carriers due to thermal excitation can be suppressed. Therefore, the amount of increase in off-state current of the transistor having the channel formation region formed using the oxide semiconductor with an increase in the operation temperature can be reduced.

The number of carriers in the highly purified oxide semiconductor is very small (close to zero), and the carrier concentration is less than 1×1014/cm3, preferably less than 1×1012/cm3, further preferably less than 1×1011/cm3.

The number of carriers in the oxide semiconductor is so small that the off-state current of the transistor can be reduced. Specifically, the off-state current of the transistor in which an oxide semiconductor is used for the semiconductor layer (per channel width of 1 μm) can be reduced to 10 aA/μm (1×10−17A/μm) or lower, further reduced to 1 aA/μm (1×10−18A/μm) or lower, and still further reduced to 10 zA/μm (1×10−20A/μm). In other words, in circuit design, the oxide semiconductor can be regarded as an insulator when the transistor is off. Moreover, when the transistor is on, the current supply capability of the oxide semiconductor is expected to be higher than that of a semiconductor layer formed of amorphous silicon.

In each of the transistors1210,1220,1230, and1240which an oxide semiconductor is used for a semiconductor layer1203, the current in an off state (the off-state current) can be low. Thus, the retention time for an electric signal such as image data can be extended, and an interval between writings can be extended. As a result, the refresh rate can be reduced, so that power consumption can be further reduced.

Furthermore, the transistors1210,1220,1230, and1240in each of which an oxide semiconductor is used for a semiconductor layer1203can have relatively high field-effect mobility as the ones formed using an amorphous semiconductor; thus, the transistors can operate at high speed. As a result, high functionality and high-speed response of a display device can be realized.

Although there is no particular limitation on a substrate that can be used as the substrate1200having an insulating surface, the substrate needs to have heat resistance at least high enough to withstand heat treatment to be performed later. A glass substrate made of barium borosilicate glass, aluminoborosilicate glass, or the like can be used.

In the case where the temperature of heat treatment to be performed later is high, a glass substrate whose strain point is greater than or equal to 730° C. is preferably used. For a glass substrate, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example. Note that a glass substrate containing a larger amount of barium oxide (BaO) than boron oxide (B2O3) may be used.

Note that a substrate formed of an insulator, such as a ceramic substrate, a quartz substrate, or a sapphire substrate, may be used instead of the glass substrate. Alternatively, crystallized glass or the like may be used. A plastic substrate or the like can be used as appropriate.

In the bottom-gate structure transistors1210,1220, and1230, an insulating film serving as a base film may be provided between the substrate and the gate electrode layer. The base film has a function of preventing diffusion of an impurity element from the substrate, and can be formed with a single-layer structure or a layered structure including a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and/or a silicon oxynitride film.

The gate electrode layer1201can be formed with a single-layer structure or a layered structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or an alloy material containing any of these materials as its main component.

As a two-layer structure of the gate electrode layer1201, any of the following layered structures is preferably employed, for example: a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked. As a three-layer structure of the gate electrode layer1201, it is preferable to employ a stack of a tungsten layer or a tungsten nitride layer, a layer of an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer. Note that the gate electrode layer can be formed using a light-transmitting conductive film. An example of a material for the light-transmitting conductive film is a light-transmitting conductive oxide.

The gate insulating layer1202can be formed with a single-layer structure or a layered structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, and a hafnium oxide layer by a plasma CVD method, sputtering, or the like.

The gate insulating layer1202can have a structure in which a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer side. For example, a 100-nm-thick gate insulating layer is formed in such a manner that a silicon nitride layer (SiNy(y>0)) having a thickness of 50 nm to 200 nm is formed as a first gate insulating layer by sputtering and then a silicon oxide layer (SiOx(x>0)) having a thickness of 5 nm to 300 nm is stacked as a second gate insulating layer over the first gate insulating layer. The thickness of the gate insulating layer1202may be set as appropriate depending on characteristics needed for a transistor, and may be approximately 350 nm to 400 nm

For a conductive film used for the source electrode layer1205aand the drain electrode layer1205b, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing any of these elements, or an alloy film containing a combination of any of these elements can be used, for example. A structure may be employed in which a high-melting-point metal layer of Cr, Ta, Ti, Mo, W, or the like is stacked on one or both of a top surface and a bottom surface of a metal layer of Al, Cu, or the like. By using an aluminum material to which an element preventing generation of hillocks and whiskers in an aluminum film, such as Si, Ti, Ta, W, Mo, Cr, Nd, Sc, or Y, is added, heat resistance can be increased.

The source electrode layer1205aand the drain electrode layer1205bmay have a single-layer structure or a layered structure of two or more layers. For example, the source electrode layer1205aand the drain electrode layer1205bcan have a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order.

A conductive film serving as the wiring layers1246aand1246bconnected to the source electrode layer1205aand the drain electrode layer1205bcan be formed using a material similar to that of the source and drain electrode layers1205aand1205b.

The conductive film to be the source electrode layer1205aand the drain electrode layer1205b(including a wiring layer formed using the same layer as the source and drain electrode layers) may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (Sn02), zinc oxide (ZnO), an alloy of indium tin oxide, an alloy of indium oxide and zinc oxide (In2O3-Zn0), or any of the metal oxide materials containing silicon or silicon oxide can be used.

As the insulating layers1207,1227, and1247and the protective insulating layer1209, an inorganic insulating film such as an oxide insulating layer or a nitride insulating layer is preferably used.

As the insulating layers1207,1227, and1247, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film can be typically used.

As the protective insulating layer1209, an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, or an aluminum nitride oxide film can be used.

A planarization insulating film may be formed over the protective insulating layer1209in order to reduce surface roughness due to the transistor. The planarization insulating film can be formed using a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. Other than such organic materials, it is possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the planarization insulating film may be formed by stacking a plurality of insulating films formed from these materials.

It is possible to provide display device in which the transistor is used in which an oxide semiconductor is used for a semiconductor layer in this embodiment.

In this embodiment, an appearance and a cross section of a liquid crystal display device is illustrated and a structure thereof will be described. Specifically, when transistors are manufactured and used for a pixel portion and a driver circuit, a liquid crystal display device having a display function can be manufactured. Further, part of or the entire driver circuit can be formed over a substrate where a pixel portion is formed, using a transistor; thus, a system-on-panel can be obtained.

Note that the liquid crystal display device includes any of the following modules in its category: a module provided with a connector, for example, a flexible printed circuit (FPC), a tape automated bonding (TAB) tape, or a tape carrier package (TCP); a module provided with a printed wiring board at the end of a TAB tape or a TCP; and a module where an integrated circuit (IC) is directly mounted on a display element by a chip-on-glass (COG) method.

The appearance and a cross section of a liquid crystal display device will be described with reference to FIGS.8A1,8A2, and8B. FIGS.8A1and8A2are plan views of panels in which transistors4010and4011and a liquid crystal element4013are sealed between a first substrate4001and a second substrate4006with a sealant4005.FIG. 8Bis a cross-sectional view along M-N in FIGS.8A1and8A2.

The sealant4005is provided so as to surround a pixel portion4002and a scan line driver circuit4004that are provided over the first substrate4001. The second substrate4006is provided over the pixel portion4002and the scan line driver circuit4004. Therefore, the pixel portion4002and the scan line driver circuit4004are sealed together with a liquid crystal layer4008, by the first substrate4001, the sealant4005, and the second substrate4006. A signal line driver circuit4003that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared is mounted in a region that is different from the region surrounded by the sealant4005over the first substrate4001.

Note that there is no particular limitation on the connection method of a driver circuit that is separately formed, and a COG method, a wire bonding method, a TAB method, or the like can be used. FIG.8A1illustrates an example where the signal line driver circuit4003is mounted by a COG method. FIG.8A2illustrates an example where the signal line driver circuit4003is mounted by a TAB method.

The pixel portion4002and the scan line driver circuit4004provided over the first substrate4001include a plurality of transistors.FIG. 8Billustrates the transistor4010included in the pixel portion4002and the transistor4011included in the scan line driver circuit4004. Insulating layers4041a,4041b,4042a,4042b,4020, and4021are provided over the transistors4010and4011.

A transistor in which an oxide semiconductor is used for a semiconductor layer can be used as the transistors4010and4011. In this embodiment, the transistors4010and4011are n-channel transistors.

A conductive layer4040is provided over part of the insulating layer4021, which overlaps with a channel formation region including an oxide semiconductor in the transistor4011for the driver circuit. The conductive layer4040is provided at the position overlapping with the channel formation region including the oxide semiconductor, so that the amount of change in threshold voltage of the transistor4011before and after the BT (bias-temperature) test can be reduced. The potential of the conductive layer4040may be the same or different from that of a gate electrode layer of the transistor4011. The conductive layer4040can also function as a second gate electrode layer. The potential of the conductive layer4040may be GND or 0 V, or the conductive layer4040may be in a floating state.

A pixel electrode layer4030included in the liquid crystal element4013is electrically connected to the transistor4010. A counter electrode layer4031of the liquid crystal element4013is provided for the second substrate4006. A portion where the pixel electrode layer4030, the counter electrode layer4031, and the liquid crystal layer4008overlap with one another corresponds to the liquid crystal element4013. Note that the pixel electrode layer4030and the counter electrode layer4031are provided with an insulating layer4032and an insulating layer4033functioning as alignment films, respectively, and the liquid crystal layer4008is sandwiched between the pixel electrode layer4030and the counter electrode layer4031with the insulating layers4032and4033provided therebetween.

Note that a light-transmitting substrate can be used as the first substrate4001and the second substrate4006; glass, ceramics, or plastics can be used. As plastics, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used.

A spacer4035is a columnar spacer obtained by selective etching of an insulating film and is provided in order to control the distance (a cell gap) between the pixel electrode layer4030and the counter electrode layer4031. Note that a spherical spacer may be used. The counter electrode layer4031is electrically connected to a common potential line formed over the substrate where the transistor4010is formed. With use of the common connection portion, the counter electrode layer4031and the common potential line can be electrically connected to each other by conductive particles arranged between a pair of substrates. Note that the conductive particles can be included in the sealant4005.

Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase is only generated within a narrow range of temperature, a liquid crystal composition containing a chiral agent at 5 wt % or more so as to improve the temperature range is used for the liquid crystal layer4008. The liquid crystal composition that includes a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, has optical isotropy, which makes the alignment process unneeded, and has a small viewing angle dependence.

Note that this embodiment can also be applied to a semi-transmissive liquid crystal display device in addition to a transmissive liquid crystal display device.

This embodiment shows the example of the liquid crystal display device in which a polarizing plate is provided on the outer side of the substrate (on the viewer side) and a coloring layer and an electrode layer used for a display element are provided in this order on the inner side of the substrate; alternatively, a polarizing plate may be provided on the inner side of the substrate. The layered structure of the polarizing plate and the coloring layer is not limited to that in this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of the manufacturing process. Further, a light-blocking film serving as a black matrix may be provided in a portion other than a display portion.

The insulating layer4041athat serves as a channel protective layer and the insulating layer4041bthat covers an outer edge portion (including a side surface) of the stack of the semiconductor layers including an oxide semiconductor are formed in the transistor4011. In a similar manner, the insulating layer4042athat serves as a channel protective layer and the insulating layer4042bthat covers an outer edge portion (including a side surface) of the stack of the semiconductor layers including an oxide semiconductor are formed in the transistor4010.

The insulating layers4041band4042bthat are oxide insulating layers covering the outer edge portion (including the side surface) of the stack of the oxide semiconductor layers can increase the distance between the gate electrode layer and a wiring layer (e.g., a source wiring layer or a capacitor wiring layer) formed over or around the gate electrode layer, so that the parasitic capacitance can be reduced. In order to reduce the surface roughness of the transistors, the transistors are covered with the insulating layer4021serving as a planarizing insulating film. Here, as the insulating layers4041a,4041b,4042a, and4042b, a silicon oxide film is formed by sputtering, for example.

Moreover, the insulating layer4020is formed over the insulating layers4041a,4041b,4042a, and4042b. As the insulating layer4020, a silicon nitride film is formed by RF sputtering, for example.

The insulating layer4021is formed as the planarizing insulating film. As the insulating layer4021, an organic material having heat resistance, such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the insulating layer4021may be formed by stacking a plurality of insulating films formed of these materials.

Note that a siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may include an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may include a fluoro group.

In this embodiment, a plurality of transistors in the pixel portion may be surrounded together by a nitride insulating film. It is possible to use a nitride insulating film as the insulating layer4020and the gate insulating layer and to provide a region where the insulating layer4020is in contact with the gate insulating layer as illustrated inFIG. 8Bso as to surround at least the periphery of the pixel portion in the active matrix substrate. In this manufacturing process, entry of moisture from the outside can be prevented. Further, even after the device is completed as a liquid crystal display device, entry of moisture from the outside can be prevented in the long term, and the long-term reliability of the device can be improved.

There is no particular limitation on the formation method of the insulating layer4021, and any of the following methods and tools can be employed, for example, depending on the material: methods such as sputtering, an SOG method, a spin coating method, a dipping method, a spray coating method, a droplet discharge method (e.g., an ink-jet method, screen printing, and offset printing); and tools (equipment) such as a doctor knife, a roll coater, a curtain coater, and a knife coater. The baking step of the insulating layer4021also serves as annealing of the semiconductor layer, so that a liquid crystal display device can be efficiently manufactured.

Alternatively, the pixel electrode layer4030and the counter electrode layer4031can be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of less than or equal to 10000 ohms per square and a transmittance of greater than or equal to 70% at a wavelength of 550 nm. Further, the resistivity of the conductive high molecule included in the conductive composition is preferably less than or equal to 0.1Ω·cm.

As the conductive high molecule, a so-called π-electron conjugated conductive high molecule can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, and a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

A variety of signals and potentials are supplied from an FPC4018to the signal line driver circuit4003which is formed separately, the scan line driver circuit4004, or the pixel portion4002.

A connection terminal electrode4015is formed from the same conductive film as the pixel electrode layer4030included in the liquid crystal element4013, and a terminal electrode4016is formed from the same conductive film as source and drain electrode layers of the transistors4010and4011.

The connection terminal electrode4015is electrically connected to a terminal included in the FPC4018via an anisotropic conductive film4019.

Note that FIGS.8A1and8A2illustrate the example in which the signal line driver circuit4003is formed separately and mounted on the first substrate4001; however, the this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

FIG. 9illustrates an example of a structure of a liquid crystal display device.

FIG. 9illustrates an example of a liquid crystal display device. A TFT substrate2600and a counter substrate2601are fixed to each other with a sealant2602. A pixel portion2603including a TFT and the like, a display element2604including a liquid crystal layer, and a coloring layer2605are provided between the substrates so that a display region is formed. The coloring layer2605is necessary to perform color display. In the RGB system, coloring layers corresponding to colors of red, green, and blue are provided for pixels. A polarizing plate2606is provided on the outer side of the counter substrate2601. A polarizing plate2607and a diffusion plate2613are provided on the outer side of the TFT substrate2600. A light source includes a cold cathode tube2610and a reflective plate2611. A circuit board2612is connected to a wiring circuit portion2608of the TFT substrate2600by a flexible wiring board2609and includes an external circuit such as a control circuit or a power source circuit. The polarizing plate and the liquid crystal layer may be stacked with a retardation plate therebetween.

For a method for driving the liquid crystal display device, a TN (twisted nematic) mode, an IPS (in-plane-switching) mode, an FFS (fringe field switching) mode, an MVA (multi-domain vertical alignment) mode, a PVA (patterned vertical alignment) mode, an ASM (axially symmetric aligned micro-cell) mode, an OCB (optically compensated birefringence) mode, an FLC (ferroelectric liquid crystal) mode, an AFLC (antiferroelectric liquid crystal) mode, or the like can be used.

Through the above-described process, it is possible to manufacture a liquid crystal display device.

In this embodiment, a structure of the liquid crystal display device described in the above embodiments which has a touch-panel function will be described with reference toFIGS. 10A and 10B.

FIG. 10Ais a schematic view of a liquid crystal display device of this embodiment.FIG. 10Aillustrates a structure in which a touch panel unit1502is stacked on a liquid crystal display panel1501which is the liquid crystal display device of the above embodiment and they are attached with a housing (case)1503. As the touch panel unit1502, a resistive touch sensor, a surface capacitive touch sensor, a projected capacitive touch sensor, or the like can be used as appropriate.

The liquid crystal display panel1501and the touch panel unit1502are manufactured separately and stacked as illustrated inFIG. 10A, whereby the cost of manufacturing a liquid crystal display device having a touch-panel function can be reduced.

FIG. 10Billustrates a structure of a liquid crystal display device having a touch-panel function, which is different from that illustrated inFIG. 10A. A liquid crystal display device1504illustrated inFIG. 10Bincludes a plurality of pixels1505each having a light sensor1506and a liquid crystal element1507. Therefore, the touch panel unit1502is not necessarily stacked, which is different from that illustrated inFIG. 10A. Thus, a liquid crystal display device can be thinned. Further, a gate line driver circuit1508, a signal line driver circuit1509, and a light sensor driver circuit1510are manufactured over the same substrate as the pixels1505. Thus, a liquid crystal display device can be reduced in size. Note that the light sensor1506may be formed using amorphous silicon or the like and stacked on a transistor including an oxide semiconductor.

Note that this embodiment can be combined with other embodiments as appropriate.

In this embodiment, an example of an electronic device including the liquid crystal display device described in any of the above-described embodiments will be described.

FIG. 11Aillustrates an e-book reader (also referred to as an e-Book) that can include a housing9630, a display portion9631, operation keys9632, a solar cell9633, a charge and discharge control circuit9634, and the like. The e-book reader inFIG. 11Acan have a function of displaying a variety of information (e.g., a still image, a moving image, and a text image) on the display portion; a function of displaying a calendar, a date, the time, and the like on the display portion; a function of operating or editing the information displayed on the display portion; a function of controlling processing by various kinds of software (programs); and the like. Note thatFIG. 11Aillustrates a structure in which a battery9635and a DC-DC convertor (hereinafter, abbreviated as a convertor9636) are provided as an example of the charge and discharge control circuit9634.

With the structure illustrated inFIG. 11A, when a semi-transmissive liquid crystal display device is used as the display portion9631, the e-book reader is expected to be used in a comparatively bright environment, in which case the structure inFIG. 11Ais preferable because the solar cell9633can efficiently generate power and the battery9635can efficiently charge power. Note that a structure in which the solar cell9633is provided on each of a front surface and a rear surface of the housing9630is preferable in order to charge the battery9635. Note that when a lithium ion battery is used as the battery9635, an advantage such as reduction in size can be obtained.

In addition, a structure and operation of the charge and discharge control circuit9634illustrated inFIG. 11Ais described with reference to a block diagram ofFIG. 11B.

FIG. 11Bshows the solar cell9633, the battery9635, the converter9636, a converter9637, switches SW1to SW3, and the display portion9631. The charge and discharge control circuit9634includes the battery9635, the converter9636, the converter9637, and the switches SW1to SW3.

First, an example of operation of when the solar cell9633generates power by using external light is described. The power generated by the solar cell is raised or lowered by the converter9636to be the voltage which is stored in the battery9635. When the power from the solar cell9633is used for operation of the display portion9631, the switch SW1is turned on and the power is raised or lowered by the converter9637to be the voltage needed for the display portion9631. When display is not performed on the display portion9631, the switch SW1may be turned off and the switch SW2may be turned on, whereby the battery9635is charged.

Next, an example of operation of when the solar cell9633does not generate power by using external light is described. The power stored in the battery9635is raised or lowered by the converter9637when the switch SW3is turned on. Then, the power from the battery9635is used for operation of the display portion9631.

Note that the solar cell9633is described as an example of a charging unit here; however, charging the battery9635may be performed by another unit. Alternatively, a combination of another charging unit may be used.

This application is based on Japanese Patent Application serial no. 2010-041987 filed with Japan Patent Office on Feb. 26, 2010, the entire contents of which are hereby incorporated by reference.

Explanation of Reference