Power amplifier

In a power amplifier a Doherty amplifier is provided with an output higher harmonic reflection circuit that is connected to the output terminal of a first FET chip and sets an even-numbered higher harmonic load of an output signal at the output terminal to be a short-circuit, or at a low impedance approximating a short-circuit, and sets an odd-numbered higher harmonic load of an output signal at the output terminal to be an open-circuit, or a high impedance approximating an open-circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a high-frequency power amplifier and, more particularly to improvement of a Doherty high-frequency power amplifier used with microwave-band and millimeterwave-band communications equipment for mobile communication, satellite communication or the like.

2. Description of the Related Art

In recent years, there has been an increasing demand for smaller, higher-output communications equipment used in a microwave band and a millimeter wave band. In addition, there has been also an increasing demand for higher quality of propagated signals. With this trend, needs for high-frequency power amplifiers with less distortion have been increasing.

Especially a microwave communications system using multi-carrier signals or recent modulated-wave signals based on the CDMA method or the like actuates an amplifier at an output level that is far lower than its maximum power rating in order to avoid influences of distortion caused by nonlinearity of the amplifier that amplifies signals.

Regardless of high frequencies, typical amplifiers usually have high input signal levels and provide higher efficiency toward maximum output levels of the amplifiers. If, however, an input signal level is sufficiently lower than a maximum output level, that is, if offset backoff (hereinafter referred to as “OBO”) is sufficiently large, then the efficiency is low accordingly. This has been making it difficult to achieve high efficiency.

The Doherty amplifier was first proposed by Doherty (“A New High Efficiency Power Amplifier For Modulated Waves”, Proceedings of the Institute of Radio Engineers, Vol. 24, No. 9, September, 1936).

The Doherty amplifier is intended to be used with an AM broadcasting transmitter for low to medium frequencies, and has a carrier amplifier and a peak amplifier that are connected by an impedance conversion line having an electrical length equivalent to a quarter wavelength of a signal frequency. This configuration permits dramatically improved efficiency at a low output level.

A report by Raab on theoretical values of efficiency obtained by the Doherty amplifier indicates that high efficiency is maintained at output levels from an output point, which is a quarter of a maximum output, to a maximum output point, and that the output level at which a highly efficient operation is performed can be lowered to a quarter or less of the maximum output by setting outputs of a peak amplifier greater than those of the carrier amplifier (“Efficiency of Doherty RF power-amplifier systems”, “IEEE Trans. Broadcast, vol. BC-33, pp. 77–83, September 1987).

There is a publicly known example wherein such Doherty amplifier is used in a microwave band. This has disclosed a Doherty amplifier equipped with a carrier amplifier that carries out higher harmonic load control and a peak amplifier that has a class B or class AB configuration as in the carrier amplifier and carries out higher harmonic load control (refer to, for example, paragraphs [0022] through [0024] and [0033] of Japanese Patent No. 2945833, and FIG. 4).

Another Doherty amplifier intended for achieving improved efficiency at a lower output level has been disclosed. This Doherty amplifier allows higher efficiency to be achieved from a low output level of one tenth or less of a maximum output, it can be achieved to triple an output of the carrier amplifier by making the size of a transistor used with its peak amplifier three times as large as the size of a transistor used with its carrier amplifier (refer to, for example, “An Extended Doherty Amplifier With High Efficiency Over a Wide Power Range” by M. Iwamoto et al., IEEE Trans. Microwave Theory Tech., Vol. 49, No. 12, pp. 2472–2479, December 2001).

Still another example of a Doherty amplifier intended for achieving improved efficiency at a lower output level has been disclosed. In this example, a plurality of peak amplifiers is used to provide an equivalent effect obtained by increasing the size of a transistor used with a peak amplifier (refer to, for example, “A Fully Matched N-Way Doherty Amplifier With Optimized Linearity” by Y. Yang et al., IEEE Trans. Microwave Theory Tech., Vol. 51, No. 3, pp. 986–993, March 2003).

A Doherty amplifier that adopts a parallel coupling configuration to improve linearity is disclosed in Published Japanese Translations of PCT International Publication for Patent Application No. H 10-513631.

Further, Japanese Patent Laid-open No. H 8-330873 has disclosed a configuration for linearly amplifying a noise-like RF signal having a multicarrier. The configuration includes a ¼ wavelength impedance transforming circuit that uses a load at an output end of a carrier amplifier as the normalized impedance of an optimal load impedance and a ½ wavelength phase shifter. In addition, an input end of a peak amplifier is disposed with a ¼ wavelength phase shifter, a ¼ wavelength impedance transforming circuit that uses a load at an output end of a peak amplifier as the normalized impedance of an optimal load impedance, and a ¼ wavelength phase shifter.

The Doherty amplifier disclosed in Japanese Patent No. 2945833 has a basic construction of a Doherty high-frequency power amplifier used with microwave-band or millimeterwave-band communications equipment. In response to a demand for an amplifier that restrains low distortion caused by an extended OBO and improves efficiency, the Doherty amplifier disclosed in M. Iwamoto et al. achieves higher efficiency by increasing the size of the transistor used with the peak amplifier. In this Doherty amplifier, however, a problem arises in that the carrier amplifier and the peak amplifier use transistors of significantly different sizes, so that its divider circuit and combiner circuit inevitably have complicated configurations.

Furthermore, a Doherty amplifier requires a Doherty network having an electrical length equivalent to a quarter wavelength of a signal frequency at an output end, and a phase compensating circuit at an input end, the phase compensating circuit having an electrical length equivalent to a quarter wavelength of a signal frequency for offsetting a phase difference between a carrier amplifier and a peak amplifier that occurs in the Doherty network. If operating frequencies are low, then these circuits inevitably become extremely large, resulting in an increased size of the whole amplifier. As a solution, therefore, the Doherty amplifier disclosed in Young et al. described above uses a plurality of phase compensating circuits and peak amplifiers to improve the efficiency at a lower output level. This, however, involves a complicated configuration. Furthermore, since a plurality of the phase compensating circuits and the peak amplifiers are provided, so that the phase compensating circuits take up even more area accordingly, making it difficult to accomplish a compact amplifier.

SUMMARY OF THE INVENTION

The present invention has been made with a view toward solving the aforementioned problems, and it is a first object to constitute a high-frequency power amplifier that allows high efficiency to be obtained at a low output level with a larger offset backoff from a maximum output. A second object of the present invention is to provide a smaller package type Doherty high-frequency power amplifier.

According to one aspect of the invention, there is provided a high-frequency power amplifier comprising: a divider circuit having an input end and a first branch and a second branch for dividing input signals received through the input end into first input signals and second input signals; a first amplifier circuit including a first transistor that has a first control terminal connected to the first branch of the divider circuit to receive the first input signal, a first constant-potential terminal, and a first output terminal through which a first output signal is issued, and a first output higher harmonic load control circuit connected to the first output terminal of the first transistor, setting an even higher harmonic load of a first output signal at the first output terminal to be short-circuited or at a low impedance approximate to a short circuit, while setting an odd higher harmonic load of the first output signal at the first output terminal to be open-circuited or at a high impedance approximate to an open circuit; a first impedance conversion circuit having one end thereof connected to an output end of the first output higher harmonic load control circuit of the first amplifier circuit, and having an electrical length equivalent to one quarter of the wavelength of a first output signal propagated through the intermediary of the output higher harmonic load control circuit; a second impedance conversion circuit having one end thereof connected to the second branch, and imparting a phase difference, which offsets a phase difference to be imparted by the first impedance conversion circuit, to a second input signal from the second branch; a second amplifier circuit including a second transistor that has a second control terminal connected to an output end of the second impedance conversion circuit to receive a second input signal, a second constant-potential terminal, and a second output terminal through which a second output signal is issued, and a second output higher harmonic load control circuit connected to the second output terminal of the second transistor, setting an even higher harmonic load of a second output signal at the second output terminal to be open-circuited or at a high impedance approximate to an open circuit, while setting an odd higher harmonic load of the second output signal at the second output terminal to be short-circuited or at a low impedance approximate to a short circuit; and a combiner circuit having a third branch, a fourth branch, and an output end through which a third output signal is issued, the third branch connected to an output end of the first impedance conversion circuit, the fourth branch connected to an output end of the second output higher harmonic load control circuit.

Accordingly, in the high-frequency power amplifier according to the present invention, the first amplifier circuit performs a class F operation, while the second amplifier circuit performs a class inverse-F operation, allowing the outputs of the second amplifier circuit to exceed the outputs of the first amplifier circuit.

This makes it possible to achieve improved efficiency of the amplifier in a low output level range provided with a back-off from a maximum output.

In other words, a high-frequency power amplifier according to the present invention enables the peak amplifier to provide outputs that are greater than those of the carrier amplifier, permitting higher output efficiency of the amplifier to be achieved in a low output level range with a sufficient offset backoff from a maximum output of the amplifier.

As a result, it is possible to provide a Doherty amplifier having a simple configuration that outputs signals of good quality with minimized distortion, the Doherty amplifier being used with microwave-band and millimeterwave-band communications equipment for mobile communication, satellite communication or the like.

According to another aspect of the invention, there is provided a high-frequency power amplifier comprising: a dielectric circuit board; a divider circuit disposed on the circuit board, having an input end and a first branch and a second branch for dividing input signals received through the input end into first input signals and second input signals; a package disposed on the circuit board, having a metal substrate and a wall which is disposed on the metal substrate, and which surrounds a predetermined region of the metal substrate, a plurality of connecting terminals which connects between an internal region surrounded by the wall and an external region, and a covering member which seals an area inside the wall; a first amplifier circuit disposed on the region of the metal substrate surrounded by the wall of the package, including a first transistor that has a first control terminal connected to the first branch of the divider circuit through the intermediary of a first one of the plural connecting terminals to receive the first input signal, a first constant-potential terminal, and a first output terminal through which a first output signal is issued, and a first output higher harmonic load control circuit that is connected to the first output terminal of the first transistor, setting an even higher harmonic load of a first output signal at the first output terminal to be short-circuited or at a low impedance approximate to a short circuit, while setting an odd higher harmonic load of the first output signal at the first output terminal to be open-circuited or at a high impedance approximate to an open circuit; a first impedance conversion circuit disposed on the circuit board, having one end thereof connected to an output end of the first output higher harmonic load control circuit through the intermediary of a second one of the plural connecting terminals, and having an electrical length equivalent to one quarter of the wavelength of a first output signal propagated through the intermediary of the output higher harmonic load control circuit; a second impedance conversion circuit disposed on the circuit board, having one end thereof connected to the second branch, and imparting a phase difference, which offsets a phase difference to be imparted by the first impedance conversion circuit, to a second input signal from the second branch; a second amplifier circuit disposed on the region of the metal substrate surrounded by the wall of the package, including a second transistor that has a second control terminal connected to an output end of the second impedance conversion circuit through the intermediary of a third one of the plural connecting terminals to receive a second input signal, a second constant-potential terminal, and a second output terminal through which a second output signal is issued, and a second output higher harmonic load control circuit connected to the second output terminal of the second transistor, setting an even higher harmonic load of a second output signal at the second output terminal to be open-circuited or at a high impedance approximate to an open circuit, while setting an odd higher harmonic load of the second output signal at the second output terminal to be short-circuited or a low impedance approximate to a short circuit; and a combiner circuit disposed on the circuit board, having a third branch, a fourth branch, and an output end through which a third output signal is issued, the third branch connected to an output end of the first impedance conversion circuit, the fourth branch connected to an output end of the second output higher harmonic load control circuit through a fourth one of the plural connecting terminals, and a third output signal is issued through the output end.

Accordingly, a high-frequency power amplifier according to the present invention enables to provide a smaller package type Doherty amplifier having a simple configuration that outputs signals of good quality with minimized distortion.

According to still another aspect of the invention, there is provided a high-frequency power amplifier comprising: a dielectric circuit board; a divider circuit disposed on the circuit board, having an input end and a first branch and a second branch for dividing input signals received through the input end into first input signals and second input signals; a package disposed on the circuit board, having a metal substrate and a wall which is disposed on the metal substrate, and which surrounds a predetermined region of the metal substrate, a plurality of connecting terminals which connects between an internal region surrounded by the wall and an external region, and a covering member for which seals the region inside the wall; a first amplifier circuit disposed on the region of the metal substrate surrounded by the wall of the package, including a first transistor that has a first control terminal connected to the first branch of the divider circuit through the intermediary of a first one of the plural connecting terminals to receive the first input signal, a first constant-potential terminal, and a first output terminal through which a first output signal is issued, and a first output higher harmonic load control circuit that is connected to the first output terminal of the first transistor, setting a higher harmonic load of a first output signal at the first output terminal to a predetermined value; a first impedance conversion circuit including a dielectric board having a specific inductive capacity that is larger than that of the circuit board, and a line disposed on the dielectric board, having an electrical length equivalent to a quarter of the wavelength of a first output signal propagated through the intermediary of the output higher harmonic load control circuit, the first impedance conversion circuit disposed on the region of the metal substrate surrounded by the wall of the package through the intermediary of the dielectric board, and one end of the first impedance conversion circuit connected to an output end of the first output higher harmonic load control circuit; a second impedance conversion circuit disposed on the circuit board, having one end thereof connected to the second branch, and imparting a phase difference, which offsets a phase difference to be imparted by the first impedance conversion circuit, to a second input signal from the second branch; a second amplifier circuit disposed on the region of the metal substrate surrounded by the wall of the package, including a second transistor that has a second control terminal connected to an output end of the second impedance conversion circuit through the intermediary of a second one of the plural connecting terminals to receive a second input signal, a second constant-potential terminal, and a second output terminal through which a second output signal is issued, and a second output higher harmonic load control circuit connected to the second output terminal of the second transistor, setting a higher harmonic load of a second output signal at the second output terminal to a predetermined value; and a combiner circuit disposed on the circuit board having a third branch, a fourth branch, and an output end through which a third output signal is issued, the third branch connected to an output end of the first impedance conversion circuit through the intermediary of a third one of the plural connecting terminals, the fourth branch connected to an output end of the second output higher harmonic load control circuit through the intermediary of a fourth one of the plural connecting terminals.

Accordingly, a high-frequency power amplifier according to the present invention enables to provide a compact Doherty amplifier by disposing a Doherty network in a package, the Doherty network being formed using a microstrip line of a quarter wavelength of a signal frequency and disposed on the board formed of a dielectric exhibiting a higher specific inductive capacity than that used for a circuit board. Moreover, it is possible to provide a compact Doherty high-frequency power amplifier having a simple configuration that outputs signals of good quality with minimized distortion.

Other objects and advantages of the invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific embodiments are given by way of illustration only since various changes and modifications within the scope of the invention will become apparent to those skilled in the art from this detailed description.

In all figures, the substantially same elements are given the same reference numbers.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 1is a plan view of a high-frequency power amplifier according to one embodiment of the present invention.

Referring toFIG. 1, a Doherty amplifier10, which is an example of the first embodiment, uses a board12formed of, for example, a polytetrafluoroethylene member (hereinafter referred to as “PTFE”) serving as a circuit board.

As a material for the circuit board, a dielectric having a specific inductive capacity of about 2 to about 5 is used. In addition to PTFE having a specific inductive capacity of about 2.6, glass epoxy or the like having a specific inductive capacity of about 4.4 may be used.

A metal package14formed of a copper-molybdenum laminated material or CuW is disposed on the PTFE board12.

The package14includes a metal substrate14a, a wall14bthat is formed on the metal substrate14ato surround a central portion of the metal substrate, and four connecting terminals14c(14c1,14c2,14c3, and14c4) for connecting internal circuits surrounded by the wall14band external circuits. In addition, a covering member (not shown) for sealing the circuit parts and circuit patterns disposed in the area surrounded by the wall14bis disposed on the top of the wall14b.

A carrier amplifier16serving as a first amplifier circuit and a peak amplifier18serving as a second amplifier circuit that constitute the Doherty amplifier circuit are disposed on the area surrounded by the wall14bof the package14.

The carrier amplifier16is constructed of a first input matching circuit16a, a first FET chip16bserving as a first transistor, and a first output matching circuit16c. The peak amplifier18is constructed of a second input matching circuit18a, a second FET chip18bserving as a second transistor, and a second output matching circuit18c. The terminals of the components making up the carrier amplifier16and the peak amplifier18are connected by wires20, as necessary. The wires20connect an input end of the first input matching circuit16awith the connecting terminal14c1, an output end of the first output matching circuit16cwith the connecting terminal14c2, an input end of the second input matching circuit18awith the connecting terminal14c3, and an output end of the second output matching circuit18cwith the connecting terminal14c4, respectively.

The components making up these carrier amplifier16and the peak amplifier18are disposed on the area of the metal substrate14asurrounded by the wall14bof the package14and they are sealed by the covering member.

On the PTFE board12, a divider circuit22and a phase compensating circuit24serving as a second impedance conversion circuit, which constitute the Doherty amplifier circuit, are disposed at the input end adjacently to the package14. Further, a Doherty network26serving as a first impedance conversion circuit and a combiner circuit28are disposed at the output end.

The divider circuit22has an input end22aconnected to a signal input terminal30and a first branch22bconnected to a connection land34through the intermediary of a chip capacitor32. The connection land34is connected to the connecting terminal14clby a connecting wire36. A second branch22cof the divider circuit22is connected to the phase compensating circuit24, and the phase compensating circuit24is connected to a connection land40through the intermediary of a chip capacitor38. The connection land40is joined to the connecting terminal14c3by a connecting wire42.

The phase compensating circuit24offsets a phase difference between the carrier amplifier16and the peak amplifier18caused by the Doherty network26, and it is composed of, for example, a microstrip line having an electrical length equivalent to a quarter wavelength of a signal frequency.

Hence, an input signal received through the signal input terminal30is passed through a microstrip line31and divided into two signals by the divider circuit22. One signal is transmitted from the first branch22bof the divider circuit22to the first input matching circuit16athrough the connecting terminal14cl, while the other signal is transmitted from the second branch22cof the divider circuit22to the second matching circuit18athrough the connecting terminal14c3.

A first gate bias circuit44is formed of a line44chaving one end thereof connected to an earth end44bthrough the intermediary of a chip capacitor44aand the other end thereof connected to a connection land34. A gate bias voltage Vgg1is applied to a signal input terminal44dconnected to the line44c. The gate bias voltage Vgg1is applied to the gate of the first FET chip16bof the carrier amplifier16through the intermediary of the connecting terminal14c1and the first input matching circuit16a.

A second gate bias circuit46is formed of a line46chaving one end thereof connected to an earth end46bthrough the intermediary of a chip capacitor46aand the other end thereof connected to a connection land40. A gate bias voltage Vgg2is applied to a signal input terminal46dconnected to the line46c. The gate bias voltage Vgg2is applied to the gate of the second FET chip18bof the peak amplifier18through the intermediary of the connecting terminal14c3and the second input matching circuit18a.

In the Doherty amplifier10according to the first embodiment, the gate bias voltage Vgg1of the first FET chip16bof the carrier amplifier16and the gate bias voltage Vgg2of the second FET chip18bof the peak amplifier18use different voltages. For this reason, the chip capacitor32and the chip capacitor38are both DC-cut capacitors.

The Doherty network26is composed of, for example, a microstrip line having an electrical length equivalent to a quarter wavelength of a signal frequency. One end of the Doherty network26is attached to the connection land48and connected to the connected terminal14c3of the package14through the intermediary of a connecting wire50. The other end of the Doherty network26is connected to the first branch28aof the combiner circuit28serving as a third branch of the combiner circuit.

A second branch28bof the combiner circuit28serving as a fourth branch of the combiner circuit is attached to a connection land52and connected to the connecting terminal14c4of the package14through the intermediary of a connecting wire54.

A drain bias circuit56has one end thereof connected to an earth end56bthrough the intermediary of a chip capacitor56aand the other end thereof composed of a line56cconnected to the combiner circuit28. A drain bias voltage Vdd is applied to a signal input terminal56dconnected to the line56c. The drain bias voltage Vdd is applied to the drain of the first FET chip16bthrough the intermediary of the Doherty network26, the connecting terminal14c2and the first output matching circuit16c, and to the drain of the second FET chip18bthrough the intermediary of the connecting terminal14c4and the second output matching circuit18c. In this example, the single drain bias circuit56supplies the drain bias voltage Vdd for the first FET chip16band the second FET chip18b. Alternatively, however, a separate drain bias circuit may be provided for each of the FET chips.

Thus, the first output signal amplified by the carrier amplifier16is transmitted to the combiner circuit28through the intermediary of the connecting terminal14c3and the Doherty network26, while the second output signal amplified by the peak amplifier18is transmitted to the combiner circuit28through the intermediary of the connecting terminal14c4. The first and second output signals are combined by the combiner circuit28and applied to an output load RL from an output terminal60via an output end28cof the combiner circuit28and a transmission line58.

FIG. 2is a circuit diagram of the high-frequency power amplifier according to the embodiment of the present invention. In all figures, the same reference numerals denote the same or equivalent components.

Referring toFIG. 2, the first input matching circuit16aof the carrier amplifier16is constructed of an input fundamental wave matching circuit70primarily disposed at the input end of signals and a first input higher harmonic reflection circuit72serving as a first input higher harmonic load control circuit secondary disposed adjacently to the first FET chip16b. The first output matching circuit16cof the carrier amplifier16is constructed of a first output higher harmonic reflection circuit74serving as a first output higher harmonic load control circuit primarily disposed adjacently to the first FET chip16band a fundamental wave load adjusting circuit76secondary disposed adjacently to the output end of signals.

Further, a second input matching circuit18aof the peak amplifier18is constructed of an input fundamental wave matching circuit80primarily disposed at the input end of signals and a second input higher harmonic reflection circuit82serving as a second input higher harmonic load control circuit secondary disposed adjacently to the second FET chip18b. The second output matching circuit18cof the peak amplifier18is constructed of a second output higher harmonic reflection circuit84serving as a second output higher harmonic load control circuit primarily disposed adjacently to the second FET chip18band a fundamental wave load adjusting circuit86secondary disposed adjacently to the output end of signals.

A first input signal from the first branch22bof the divider circuit22is supplied to the gate terminal serving as the first control terminal of the first FET chip16bthrough the intermediary of the first input matching circuit16acomposed of the input fundamental wave matching circuit70and the first input higher harmonic reflection circuit72disposed adjacently to the input end in this order. A source terminal of the first FET chip16bis grounded, the source terminal serving as a first constant-voltage terminal. A first output signal is issued from the drain terminal, serving as the first output terminal, of the first FET chip16b, and transmitted to the Doherty network26.

Further, a second input signal from the second branch22cof the divider circuit22is supplied via the phase compensating circuit24to the gate terminal, serving as the second control terminal, of the second FET chip18bthrough the intermediary of the second input matching circuit18acomposed of the input fundamental wave matching circuit80and the second input higher harmonic reflection circuit82. A source terminal, serving as a second constant-voltage terminal, of the second FET chip18bis grounded. A second output signal is issued from the drain terminal, serving as the second output terminal, of the second FET chip18b, and transmitted to the combiner circuit28. In the combiner circuit, the first output signal and the second output signal are combined and the resulting signal is applied as a third output signal to the output load RL.

In the Doherty amplifier10shown inFIG. 1andFIG. 2, the load of an input signal at the gate terminal of the first FET chip16bof the carrier amplifier16, i.e., the load at a higher harmonic frequency of an input signal at the input end of the first FET chip16bis denoted by ZCS, the load of an input signal at the drain terminal of the first FET chip16bof the carrier amplifier16, i.e., the load at a higher harmonic frequency of an output signal at the output end of the first FET chip16bis denoted by ZCL, the load of an input signal at the gate terminal of the second FET chip18bof the peak amplifier18, i.e., the load at a higher harmonic frequency of an input signal at the input end of the second FET chip18bis denoted by ZPS, and the load of an input signal at the drain terminal of the second FET chip18bof the peak amplifier18, i.e., the load at a higher harmonic frequency of an output signal at the output end of the second FET chip18bis denoted by ZPL. The loads are set as shown below when “—f0” is added to the load on a fundamental wave, “—2f0” is added to the load on a second harmonic, and “—3f0” is added to the load on a third harmonic.
ZCS—f0=Zcin(1)
ZCS—2f0≈0  (2)
ZCS—3f0≈∞  (3)
ZCL—f0=Zcout(4)
ZCL—2f0≈0  (5)
ZCL—3f0≈∞  (6)
ZPS—f0=Zpin(7)
ZPS—2f0≈∞  (8)
ZPS—3f0≈0  (9)
ZPL—f0=Zpout(10)
ZPL—2f0≈∞  (11)
ZPL—3f0≈0  (12)

where Zcinand Zcoutdenote optimal matching loads in the fundamental waves of signals in the first FET chip16b, and Zpinand Zpoutdenote optimal matching loads in the fundamental waves of signals in the second FET chip18b.

When the loads are set as indicated in (1) through (12) above, the carrier amplifier16will perform the class F operation and the peak amplifier18will perform the class inverse-F operation. Therefore, if the gate widths of the first FET chip16band the second FET chip18bare the same, then the outputs of the second FET chip18bwill be larger than the outputs of the first FET chip16b.

Thus, the outputs of the peak amplifier18will be larger than the outputs of the carrier amplifier16simply by setting the higher harmonic loads of the peak amplifier18to be different from the higher harmonic loads of the carrier amplifier16. The efficiency of the amplifier can be enhanced in a low level output range with an increased offset backoff.

To generalize the settings of (1) through (12) shown above, for a load at the input end of the first FET chip16bin the carrier amplifier16, a load of the fundamental wave of an input signal is set as an optimal load, while an even higher harmonic load of an input signal is set to be short-circuited or a low impedance approximate to a short-circuit. For a load at the output end of the first FET chip16bin the carrier amplifier16, a load of the fundamental wave of an output is set as an optimal load, an even higher harmonic load is set to be short-circuited or a low impedance approximate to a short-circuit, and an odd higher harmonic load of an output signal is set to be open-circuit or at a high impedance approximate to open-circuit.

Similarly, for a load at the input end of the second FET chip18bin the peak amplifier18, a load of the fundamental wave of an input signal is set as an optimal load, while an even higher harmonic load of an input signal is set to be open-circuited or at a high impedance approximate to an open circuit. For a load at the output end of the second FET chip18bin the peak amplifier18, an even higher harmonic load of an output signal is set to be open-circuit or at a high impedance approximate to open-circuit, and an odd higher harmonic load of an output signal is set to be short-circuited or at a low impedance approximate to a short-circuit.

The load settings indicated in (1) through (12) above cover up to the third harmonics; however, theoretical values obtained by generalizing the load settings as shown above to consider higher harmonics of infinite orders indicate that the peak amplifier provides outputs that are (π/2) times as large as those of the carrier amplifier.

FIG. 3is a circuit diagram showing an example of an input higher harmonic reflection circuit of the carrier amplifier according to the first embodiment.FIG. 4is a circuit diagram showing an example of an output higher harmonic reflection circuit of the carrier amplifier according to the first embodiment.FIG. 5is a circuit diagram showing an example of an input higher harmonic reflection circuit of the peak amplifier according to the first embodiment.FIG. 6is a circuit diagram showing an example of an output higher harmonic reflection circuit of the peak amplifier according to the first embodiment.

In other words, the circuits shown inFIG. 3throughFIG. 6are examples for implementing the load settings of (1) through (12).

A first input higher harmonic reflection circuit72shown inFIG. 3is an LC series resonance circuit having one end thereof connected to an earth end, constituting a second higher harmonic reflection circuit. A terminal a of the circuit is connected to an input fundamental wave matching circuit70, while a terminal b is connected to the gate of a first FET chip16b, providing a short-circuited load relative to a second harmonic of an input signal.

A first output higher harmonic reflection circuit74shown inFIG. 4is composed of an LC series resonance circuit74ahaving one end thereof connected to an earth end and an LC parallel resonance circuit74b. A terminal a providing a connection point of the LC series resonance circuit74aand the LC parallel resonance circuit74bis connected to the drain of a first FET chip16b. In the first output higher harmonic reflection circuit74, the LC series resonance circuit74aconstitutes a second higher harmonic reflection circuit and provides a short-circuited load relative to the second higher harmonic of an output signal, while the LC parallel resonance circuit74bconstitutes a third higher harmonic reflection circuit and provides an open-circuited load relative to a third harmonic.

A second input higher harmonic reflection circuit82shown inFIG. 5is an LC parallel resonance circuit constituting a second harmonic reflection circuit and its terminal b is connected to the gate of a second FET chip18b, providing an open-circuited load relative to a second harmonic of an input signal.

A second output higher harmonic reflection circuit84shown inFIG. 6is composed of an LC series resonance circuit84ahaving one end thereof connected to an earth end and an LC parallel resonance circuit84b. A terminal a is connected to the drain of a second FET chip18b, and a terminal b providing a connection point of the LC series resonance circuit84aand the LC parallel resonance circuit84bis connected to the drain of a fundamental wave load adjusting circuit86. In the second output higher harmonic reflection circuit84, the LC series resonance circuit84aconstitutes a third harmonic reflection circuit and provides a short-circuited load relative to the third harmonic of an output signal, while the LC parallel resonance circuit84bconstitutes a second harmonic reflection circuit and provides an open-circuited load relative to a second harmonic.

FIG. 7throughFIG. 10show circuits disposed as more examples for implementing the load settings of (1) through (12).

FIG. 7is a circuit diagram showing an example of an input higher harmonic reflection circuit of the carrier amplifier according to the first embodiment.FIG. 8is a circuit diagram showing an example of an output higher harmonic reflection circuit of the carrier amplifier according to the first embodiment.FIG. 9is a circuit diagram showing an example of an input higher harmonic reflection circuit of the peak amplifier according to the first embodiment.FIG. 10is a circuit diagram showing an example of an output higher harmonic reflection circuit of the peak amplifier according to the first embodiment.

A first input higher harmonic reflection circuit72shown inFIG. 7is composed of a microstrip line72athat is connected to an input fundamental wave matching circuit70through its terminal a and also connected to the gate of a first FET chip16bthrough its terminal b, and has a predetermined length, and a microstrip line72bthat is shunt-connected with the microstrip line72aat the terminal a and has an electrical length of one eighth wavelength of a signal frequency. In the first input higher harmonic reflection circuit72, the microstrip line72bis used as a second higher harmonic reflection stub, and the shape and length of the microstrip line72aare properly set to make phase adjustment.

A first output higher harmonic reflection circuit74shown inFIG. 8is composed of a microstrip line74cand a microstrip line74dconnected in order in series between a terminal a and a terminal b, a microstrip line stub74ethat is shunt-connected between the microstrip line74cand the microstrip line74dand has an electrical length of one eighth wavelength of a signal frequency, and a microstrip line stub74fshunt-connected between the microstrip line74dand the terminal b and has an electrical length of one twelfth wavelength of a signal frequency. The terminal a is connected to the drain terminal of a first FET chip16b, while the terminal b is connected to a fundamental wave load adjusting circuit76. The stub74eis a second harmonic reflection stub, and the stub74fis a third harmonic reflection stub. The shapes and lengths of the microstrip line74cand the microstrip line74dare appropriately set to perform phase adjustment.

A second input higher harmonic reflection circuit82shown inFIG. 9is composed of a microstrip line82athat is connected to an input fundamental wave matching circuit80through its terminal a and also connected to the gate of a second FET chip18bthrough its terminal b, and has a predetermined length, and a microstrip line82bthat is shunt-connected with the microstrip line82aat the terminal a and has an electrical length of one eighth wavelength of a signal frequency. In the second input higher harmonic reflection circuit82, the microstrip line82bis used as a second harmonic reflection stub, and the shape and length of the microstrip line82aare appropriately set to make phase adjustment.

A second output higher harmonic reflection circuit84shown inFIG. 10is composed of a microstrip line84cand a microstrip line84dconnected in order in series between a terminal a and a terminal b, a microstrip line stub84ethat is shunt-connected between the microstrip line84cand the microstrip line84dand has an electrical length of one eighth wavelength of a signal frequency, and a microstrip line stub84fshunt-connected between the microstrip line84dand the terminal b and has an electrical length of one twelfth wavelength of a signal frequency. The terminal a is connected to the drain terminal of a second FET chip18b, while the terminal b is connected to a fundamental wave load adjusting circuit86. The stub84eis a second harmonic reflection stub, and the stub84fis a third harmonic reflection stub. The shapes and lengths of the microstrip line84cand the microstrip line84dare appropriately set to perform phase adjustment.

FIG. 11is a graph showing calculated values of output efficiency in relation to offset backoff of a high-frequency power amplifier according to the first embodiment.

Referring toFIG. 11, a curve a indicates the efficiency of a Doherty amplifier according to the present invention. A curve b indicates actually measured values of the efficiency of a conventional Doherty amplifier shown for the purpose of comparison. In the curve b, the conditions of the load at an input end and the load at an output end are set to be the same for both a carrier amplifier and a peak amplifier.

As shown inFIG. 11, the Doherty amplifier10according to the first embodiment exhibits improved output efficiency in a low output level range with a large offset backoff from a maximum output.

In the Doherty amplifier10, the carrier amplifier16performs the class F operation, while the peak amplifier18performs the class inverse-F operation. Setting the characteristic impedance of the Doherty network26at an optimal value contributes to improved efficiency at a low output level.

A characteristic impedance Zdof the Doherty network26is represented by the following expression:
Zd=(T×R0)/α  (13)

where T indicates the ratio of a fundamental wave input voltage V1at the input end of the Doherty network26to a fundamental wave output voltage V2at the output end of the Doherty network26, which is represented by T=V1/V2;

α indicates a fundamental wave output current at the output end of the Doherty network26when the fundamental wave output power of the entire amplifier10at a maximum output is set to 1, so that the fundamental wave output current at the output end of the peak amplifier18will be1-α; and

R0indicates an output load of the Doherty amplifier10.

Since the carrier amplifier16performs the class F operation, and the peak amplifier18performs the class inverse-F operation, the following equations apply:
T=8/(π2)  (14)
α=2/(2+π)  (15)

Therefore, an optimal characteristic impedance Zdoptof the Doherty network26is:
Zdopt=4(2+π)×R0/(π2)  (16)
First Modification

FIG. 12is a circuit diagram showing a modification of the high-frequency power amplifier according to an embodiment of the present invention.

In a Doherty amplifier88shown inFIG. 12, the second branch of the divider circuit22is further split into two branches and the first branch of the combiner circuit is further split into two branches so as to connect another phase compensating circuit24and another peak amplifier18between the second branch of the divider circuit22and the first branch of the combiner circuit in parallel to a phase compensating circuit24and a peak amplifier18disposed between the second branch of the divider circuit22and the second branch of the combiner circuit in the Doherty amplifier10shown inFIGS. 1 and 2.

Thus, using a plurality of peak amplifiers18provides the same effect as that obtained by increasing the size of the second FET chip18bof the peak amplifier18, making it possible to improve the efficiency of the amplifier at a low output level.

Regarding the Doherty amplifier10explained in the first embodiment, the description has been given of the case where the carrier amplifier16includes the first input higher harmonic reflection circuit72and the first output higher harmonic reflection circuit74, and the peak amplifier18includes the second input higher harmonic reflection circuit82and the second output higher harmonic reflection circuit74. However, even if the first input higher harmonic reflection circuit72and the second input higher harmonic reflection circuit82are removed, the output efficiency of the amplifier can be improved in a low output level range with a sufficient offset backoff from a maximum output of the amplifier.

As described above, in the high-frequency power amplifier according to the first embodiment, the carrier amplifier of the Doherty amplifier is provided with an output higher harmonic reflection circuit that is connected to the output terminal of the first FET chip and sets an even higher harmonic load of an output signal at the output terminal to be short-circuited or at a low impedance approximate to a short circuit, and sets an odd higher harmonic load of an output signal at the output terminal to be open-circuited or at a high impedance approximate to open-circuit. Further, the peak amplifier is provided with an output higher harmonic reflection circuit that is connected to the output terminal of the second FET chip, and sets an even higher harmonic load of an output signal at the output terminal to be open-circuit or at a high impedance approximate to open-circuit, while setting an odd higher harmonic load of an output signal of the output terminal to be short-circuited or at a low impedance approximate to a short-circuit. This arrangement enables the peak amplifier to provide outputs that are greater than those of the carrier amplifier, permitting higher output efficiency of the amplifier to be achieved in a low output level range with a sufficient offset backoff from a maximum output of the amplifier. As a result, it is possible to provide a Doherty amplifier having a simple configuration that outputs signals of good quality with minimized distortion, the Doherty amplifier being used with microwave-band and millimeterwave-band communications equipment for mobile communication, satellite communication or the like.

Second Embodiment

FIG. 13is a plan view of a high-frequency power amplifier according to another embodiment of the present invention.FIG. 14is a circuit diagram of a high-frequency power amplifier according to the embodiment of the present invention.

FIGS. 13 and 14show a Doherty amplifier90, which is an example of the second embodiment.

The Doherty amplifier90shares the same basic construction as the Doherty amplifier10according to the first embodiment. The Doherty amplifier90differs from the Doherty amplifier10in that the Doherty network26, which is disposed on the PTFE board12in the Doherty amplifier10, has been replaced by a smaller Doherty network92, which includes a dielectric board92aformed of a dielectric having a higher specific inductive capacity than that of the PTFE board12. The dielectric board92auses, for example, barium titanate (BaTiO3) having a specific inductive capacity of approximately 38. A microstrip line92bhaving an electrical length equivalent to a quarter wavelength of a signal frequency is formed on the dielectric board92ato make the Doherty network92, which has been reduced in size, while retaining the electrical length equivalent to a quarter wavelength of a signal frequency. The Doherty network92is disposed on a metal substrate14ain the area surrounded by a wall14bof a package14.

The specific inductive capacity of the substrate material used for the Doherty network92ranges from about 8 to about 300. If the specific inductive capacity is excessively high, then the size of the Doherty network92may be too small, depending on signal frequencies. Preferably, therefore, materials having specific inductive capacities ranging from about 8 to about 50 are used. For example, TiO or alumina having a specific inductive capacity of about 9.8 may be used.

Since the Doherty network92is placed in the area enclosed by the wall14bof the package14, a microstrip line94is provided as a connection line adjacent to a peak amplifier18.

The Doherty amplifier90has the same construction as the Doherty amplifier10according to the first embodiment except that the shape of a combiner circuit28is slightly different because the Doherty network92is sealed in the area enclosed by the wall14bof the package14.

In general, a Doherty network requires an electrical length equivalent to a quarter of the wavelength of a signal frequency, and as the wavelength increases as the frequency of a signal passing through the amplifier lowers. This results in an increased size of the entire amplifier.

An effective wavelength λL of a signal propagated through a microstrip line formed on a substrate having a specific inductive capacity ∈r is represented by the expression given below when the wavelength of a microwave in vacuum is denoted as λ0.
λL=λ0/(∈r)1/2(17)

Thus, in the Doherty amplifier90, the microstrip line of a quarter wavelength of a signal frequency is formed on the dielectric board having a higher specific inductive capacity than that of the PTFE board12instead of forming a Doherty network that is formed using a microstrip line of a quarter wavelength of a signal frequency and mounted on the PTFE board12as a circuit board. This arrangement makes it possible to make the smaller Doherty network sealed in the area surrounded by the wall14bof the package14thereby to provide the smaller Doherty amplifier.

As described above, the high-frequency power amplifier according to the second embodiment not only provides the advantages of the first embodiment, but also makes it possible to provide a compact Doherty amplifier by disposing a Doherty network in a package, the Doherty network being formed using a microstrip line of a quarter wavelength of a signal frequency and disposed on the board formed of a dielectric exhibiting a higher specific inductive capacity than that used for a circuit board.

Moreover, it is possible to provide a compact Doherty high-frequency power amplifier having a simple configuration that outputs signals of good quality with minimized distortion, the Doherty amplifier being used with microwave-band and millimeterwave-band communications equipment for mobile communication, satellite communication or the like.

Third Embodiment

FIG. 15is a plan view of a high-frequency power amplifier according to still another embodiment of the present invention.FIG. 16is a circuit diagram of a high-frequency power amplifier according to the embodiment of the present invention.

FIGS. 15 and 16show a Doherty amplifier100, which is an example of the third embodiment.

The Doherty amplifier100shares the same basic construction as the Doherty amplifier10according to the first embodiment and the Doherty amplifier90according to the second embodiment. The Doherty amplifier100differs from the Doherty amplifier90in an aspect described below. In the Doherty amplifier90, a microstrip line92bhaving an electrical length equivalent to a quarter wavelength of a signal frequency is formed on the dielectric board92ato make the Doherty network92, which has been reduced in size, while retaining the electrical length equivalent to a quarter wavelength of a signal frequency, and which is disposed on the metal substrate14ain the area surrounded by the wall14bof a package14. In the Doherty amplifier100, a microstrip line92bhaving an electrical length equivalent to a quarter wavelength of a signal frequency is formed on a dielectric board92aserving as a first dielectric board to make a Doherty network92, which has been reduced in size, while retaining the electrical length equivalent to a quarter wavelength of a signal frequency, and a microstrip line102bhaving an electrical length equivalent to a quarter wavelength of a signal frequency is formed on a dielectric board102aserving as a second dielectric board made of a dielectric material having a specific inductive capacity ranging from about 8 to about 300 similar to that of the dielectric board92a, preferably ranging from about 8 to about 50, in place of the phase compensating circuit24disposed on the PTFE board12. Thus, a phase compensating circuit102, which has been reduced in size while retaining an electrical length equivalent to a quarter wavelength of a signal frequency is formed and disposed on an internal metal substrate14aenclosed by a wall14bof a package14.

More specifically, the Doherty network92, which has been reduced in size and formed on the dielectric board having a higher specific inductive capacity than that of the PTFE board12, and the phase compensating circuit102are sealedly disposed on an area of the metal substrate14aenclosed by a wall14bof a package14. This permits a still smaller Doherty amplifier.

Since the phase compensating circuit102is placed in the area enclosed by the wall14bof the package14, a microstrip line104is disposed as a connection line adjacent to a peak amplifier18.

The Doherty amplifier100has the same construction as the Doherty amplifier90according to the second embodiment except that the shape of a divider circuit24is slightly different because the phase compensating circuit102is sealed in the area enclosed by the wall14bof the package14.

Second Modification

FIG. 17is a plan view of a modification of a high-frequency power amplifier according to an embodiment of the present invention.FIG. 18is a circuit diagram of the modification of the high-frequency power amplifier according to the embodiment of the present invention.

A Doherty amplifier108shown inFIGS. 17 and 18shares the same basic construction as that of the Doherty amplifier100. In the Doherty amplifier100, a drain bias circuit56supplies a drain bias voltage Vdd to the drain of a first FET chip16band the drain of a second FET chip18b, respectively. Meanwhile, in the Doherty amplifier108, a first branch of a combiner circuit28is connected to a connection land48through the intermediary of a chip capacitor110having a DC-cut function. A drain bias circuit112is connected to the connection land48, a drain bias voltage Vdd2being applied to the drain of the first FET chip16bthrough the intermediary of a first output matching circuit16c.

The drain bias circuit112is constructed of a line112c, one end of the line112cis connected to an earth end112bthrough the intermediary of a chip capacitor112a, and the other end of the line112cis connected to the connection land48. The drain bias voltage Vdd2is applied to a signal input terminal112dconnected to the line112c.

The Doherty amplifier108having the construction described above allows the drain bias voltage Vdd2to be applied to the drain of the first FET chip16bof the carrier amplifier16by the drain bias circuit112, and also allows a drain bias voltage Vdd1to be applied to the drain of the second FET chip18bof a peak amplifier18by a drain bias circuit56. Thus, outputs of the peak amplifier18can be made larger than outputs of the carrier amplifier16by setting the drain voltage applied to the second FET chip18bof the peak amplifier18to be higher than the drain voltage of the first FET chip16bof the carrier amplifier16. This allows the efficiency of the amplifier at a low output level to be enhanced.

The second modification has been explained by comparing it with the Doherty amplifier100. However, separately applying the drain bias voltages to the drain of the first FET chip16bof the carrier amplifier16and the drain of the second FET chip18bof the peak amplifier18, respectively can be applied also to the first embodiment and the second embodiment. This makes it possible to set the outputs of the peak amplifier18to be larger than the outputs of the carrier amplifier16, so that the efficiency of the amplifier at a low output level can be further enhanced in addition to the advantages of each of the first embodiment and the second embodiment.

Third Modification

FIG. 19is a plan view of a third modification of a high-frequency power amplifier according to an embodiment of the present invention.FIG. 20is a circuit diagram of the modification of the high-frequency power amplifier according to the embodiment of the present invention.

A Doherty amplifier114shown inFIGS. 19 and 20share the same basic construction as the Doherty amplifier108. In the Doherty amplifier108, the drain bias circuit56is connected to the second branch of the combiner circuit28to apply the drain bias voltage only to the drain of the second FET chip18bof the peak amplifier18. In the Doherty amplifier114, a second branch of a combiner circuit28is connected to a connection land52through the intermediary of a chip capacitor116, and a drain bias circuit56is also connected to the connection land52. This configuration provides an advantage similar to that of the second modification. According to the configuration, a carrier amplifier16, a peak amplifier18, a Doherty network92, and a phase compensating circuit102are disposed in an area enclosed by a wall14bof a package14. Alternatively, the drain bias circuit56, a drain bias circuit112, and chip capacitors110and116may be disposed in the area enclosed by the wall14bof the package14so as to reduce the size of the entire amplifier.

Fourth Modification

FIG. 21is a circuit diagram of a fourth modification of a high-frequency power amplifier according to an embodiment of the present invention.

In a Doherty amplifier118shown inFIG. 21, a divider circuit22, a phase compensating circuit102, a first gate bias circuit44of a carrier amplifier16, and a second gate bias circuit46of a peak amplifier18are also disposed on an internal metal substrate14aenclosed by a wall14bof a package14in addition to the components enclosed by the wall14bof the package14of the Doherty amplifier90shown inFIGS. 13 and 14. This arrangement makes it possible to further reduce the size of the Doherty amplifier.

Fifth Modification

FIG. 22is a circuit diagram of a fifth modification of a high-frequency power amplifier according to an embodiment of the present invention.

In a Doherty amplifier120shown inFIG. 22, the first modification of the first embodiment is all disposed in an area on a metal substrate14athat is surrounded by a wall14bof a package14.

More specifically, a carrier amplifier16, a first gate bias circuit44, and two pairs of a combination of a phase compensating circuit102, a peak amplifier18, and a second gate bias circuit46are disposed on an area of the metal substrate14asurrounded by the wall14bof the package14. This arrangement allows the Doherty amplifier to be made smaller.

As described above, the high-frequency power amplifier according to the third embodiment provides the advantage of the first embodiment discussed above and also makes it possible to provide a smaller Doherty amplifier by including, in the package, the Doherty network formed using the microstrip line having an electrical length equivalent to a quarter wavelength of a signal frequency on the dielectric board having a higher inductive capacity than that of the circuit board, and the phase compensating circuit formed using the microstrip line having an electrical length equivalent to a quarter wavelength of a signal frequency on the dielectric board having a higher inductive capacity than that of the circuit board. This makes it possible to provide a compact Doherty high-frequency power amplifier having a simple configuration that outputs signals of good quality with minimized distortion, the Doherty amplifier being used with microwave-band and millimeterwave-band communications equipment for mobile communication, satellite communication or the like.

In the second and the third embodiments, the descriptions have been given of the case where the class F carrier amplifiers and the class inverse-F peak amplifiers are used. The present invention, however, is not limited to such cases.

In each embodiment, FETs used as the transistors for the amplifier circuits include standard field-effect transistors, such as MESFETs and HEMTs. The same advantages can be accomplished by using standard bipolar transistors or HBTs. If a bipolar transistor is used, its base terminal serves as a control terminal, its emitter terminal serves as a constant-potential terminal, and its collector terminal serves as an output terminal.

In each of the Doherty amplifiers according to the aforesaid embodiments discussed above, the carrier amplifier includes the input higher harmonic reflection circuit and the output higher harmonic reflection circuit, and the peak amplifier includes the input higher harmonic reflection circuit and the output higher harmonic reflection circuit. However, a construction without the input higher harmonic reflection circuit and the output higher harmonic reflection circuit will advantageously improve the output efficiency of an amplifier in a low output level range in which a large offset backoff from a maximum output of the amplifier is provided.

Thus, the high-frequency power amplifiers according to the present invention can be ideally used with microwave-band and millimeterwave-band communications equipment for mobile communication, satellite communication or the like.