Power adapter interface circuitry for protecting a battery operated system

An integrated circuit (IC) has logic and timing circuits that are coupled to discrete circuitry to provide protection and indications whenever an AC adapter that is faulty or has improper voltage levels or polarity are plugged into a system. In particular, the IC device provides over-voltage, under-voltage, and reversed-polarity protections to an electronic system to keep the electronic system from being damaged by an alternating current (AC) adapter having an improper voltage range or voltage polarity. It also provides a protection that prevents an adapter from powering a host system that has a short-circuit fault.

TECHNICAL FIELD

The present invention generally relates to a protection device for a battery-powered electronic system. In particular, it relates to an integrated circuit (IC) device providing over-voltage, under-voltage, and reversed-polarity protections to an electronic system to keep the electronic system from being damaged by an alternating current (AC) adapter having an improper voltage range or voltage polarity. It also provides a protection that prevents an adapter from powering a host system that has a short-circuit fault.

BACKGROUND INFORMATION

There are many types of electronic systems powered by AC to direct current (DC) adapters including, printers, scanners, liquid crystal display (LCD) monitors, personal computer (PC) speakers, digital subscriber line (DSL) modems, etc. There are also many types of portable electronic systems that may be powered by either internal batteries or AC adapters, such as cellular phones, digital cameras, compact disc (CD) players, portable computers, and pocket computers.

There is a substantial likelihood that an adapter designed for one system having a particular voltage level may be accidentally plugged into another system with a different voltage level. An adapter with a high voltage level or a reversed polarity connector could cause severe damage if it is used to power a non-compatible host system. In certain cases, it may also result in safety hazards to a user.

Many prior art protection circuits that were designed to prevent powering a system with an incompatible adapter used a myriad of discrete components including diodes, fuses, zener diodes, and solid-state relays to provide a system protection from receiving power from incompatible voltage levels or voltage polarities. In addition, most prior art protection schemes lacked reliable anti-bounce circuitry. Intermittent contact or bouncing contacts during the initial plug-in period often leads to false triggering of the protection circuitry. Furthermore, the prior art protection schemes generally do not provide a proper interface that prevents a host system from being coupled to an adapter with incompatible voltage levels or polarities. The prior protection devices or circuits simply disable or electrically disconnect the adapter from the host system. A system user is not informed that they are using an incompatible type of adapter. There is, therefore, a need for an active protection device that can inform the host system in the event a user plugs an incompatible AC adapter into the system.

SUMMARY OF THE INVENTION

Adapter interface circuitry has series connected first and second electronic switches for coupling an adapter output voltage to a system power input. A sense voltage is generated that is proportional to the adapter output voltage. Likewise, a capacitor is charged to a capacitor voltage if the adapter output voltage has a preferred polarity. A battery, with internal short circuit protection, is coupled to the system power input with a third electronic switch. In one embodiment of the present invention, an integrated circuit (IC) contains the circuitry for generating controls for the switches as well as generating signal outputs. When the capacitor voltage exceeds a predetermined value, two timers are enabled and started, and a shutdown latch is enabled. The sense voltage is used in a window comparator to determine if the adapter voltage is within a predetermined range. When the adapter voltage output is within the predetermined range, a power correct signal is generated indicating an in-range adapter output voltage condition. If the adapter output voltage is not in-range, then the shutdown latch is set at the end of the first timer interval and a light emitting diode (LED) is turned ON indicating an out-of-range voltage condition. If the adapter output voltage is in-range and the second timer interval has not expired, then a first switch voltage within the series connected switches is coupled to the system input to determine if there is a short circuit condition within the system. If the first switch voltage is below a predetermined level after the second timer interval, then the shutdown latch is again set indicating a fault condition. If the adapter output voltage is within a desired range and there is no short circuit condition after the second timer interval, then the first and second electronic switches are turned ON thereby coupling the adapter output voltage to the system power input. Likewise, the third electronic switch is turned OFF decoupling the battery from the system power input.

In another embodiment of the present invention, an emitter current is generated in a grounded base bipolar NPN transistor when the adapter output voltage is a reverse polarity. This current flows through a resistor in the collector of the NPN transistor and generates a collector voltage. The NPN transistor saturates and clamps the collector voltage thus keeping it from going too far below ground. The collector of the NPN transistor is coupled to a logic inverter which generates a reversed voltage alert signal indicating that a reversed polarity adapter has been coupled to the adapter interface circuitry.

DETAILED DESCRIPTION

Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. In the following descriptions, the terms alternating current (AC) adapter may be used interchangeable with the term adapter. While an AC adapter may be the most used with battery powered systems, adapters from other voltage sources may be used and still be within the scope of the present invention.

Different types of electronic systems use different standard adapter voltages. Most cellular phones, hand-held computers and pocket computers use 5-volt AC adapters (hereafter adapters) while laptop computers use 16-volt to 20-volt adapters. Printers and LCD monitors often use 12-volt to 15-volt adapters. Most standard adapter plugs have a round shape with two coaxial metal contacts. Some standard adapter plugs have the positive voltage potential connected to the outside coaxial contact with the return or negative voltage potential connected to the inside coaxial contact. Other standard adapters have the polarity of the voltage potentials connected to the coaxial contacts in the opposite manner.

FIG. 1Aillustrates a typical AC adapter11and a system16. AC adapter11provides power to system16via adapter plug12when inserted into receptacle15.FIG. 1Bshows an enlarged view of adapter plug12and receptacle15. Adapter plug12has coaxial contacts, outside contact13and an inside contact14.

FIG. 2Billustrates a 5-volt adapter24with a reversed polarity being plugged into a 5-volt system26. System26would experience a negative 5-volt input voltage level if coupled to 5-volt adapter26. Again, this unexpected negative input voltage may cause damages to capacitor25and system26.

FIG. 3is a circuit diagram of an embodiment of the present invention. Circuit30comprises a protection IC50and additional discrete circuitry. IC50comprises reversed-polarity detection circuitry, out-of-range protection circuitry, and short-circuit protection circuitry. IC50also comprises a shutdown latch circuit65and two timers57and77. While IC50is shown to have all of the above circuitry, portions or all of this circuitry could also be implemented in discrete form and still be within the scope of the present invention.

The system voltage (VSYS)39is normally provided by internal battery44through a P-type MOSFET (PFET)45. Internal battery44is equipped with its own short circuit protection switch47that is normally closed but opens in case of a high current condition indicative of a short circuit. If an AC adapter is unplugged, battery44via body diode109quickly powers VSYS39until the circuitry turns ON PFET45. When a correct alternating current (AC) adapter (not shown) having a proper voltage and polarity is plugged in (via connector31) to power a system (not shown) coupled to VSYS39, IC50would normally turn OFF FET45and turn ON PFET36and PFET37. When a correct voltage AC adapter is plugged in, its normal voltage DCIN131back biases body diode109. At this point, VSYS39is powered by the voltage at DCIN131. The details of the operation of the circuitry ofFIG. 3under all conditions are detailed in the following description.

With the correct adapter plugged in, reference and under-voltage lockout (UVLO) circuit70starts (via signal108) the power up of IC50. UVLO70generates two reference voltages, V106(0.8 volt) and V107(1.1 volt). The sense voltage VSEN71is coupled to the positive input of comparator72as well as to the negative input of comparator73. The negative input of comparator72is coupled to V106and the positive input of comparator73is coupled to V107. A voltage divider (shown as 5 to 1 inFIG. 3) comprising a resistor (R)34(40 kΩ) and a resistor R35(10 kΩ) scales down DCIN131to a lower voltage. AND gate74, which receives the outputs of “window comparators”72and73, goes to logic one only when DCIN131is between 4.0 volt and 5.5 volt (5 times 0.8 volts and 1.1 volts).

1.0-second timer77and a 2.0-second timer57are started by signal108when UVLO70is activated by the voltage on capacitor C33exceeding a turn on threshold. Shut down (SD) latch65is also started by signal108. The 1.0-second blanking period of timer77delays the out-of-range protection circuit from acting on the initial plug-in condition of an adapter coupled to connector31during which the electrical contacts (not shown) may be intermittent and bouncing. After the 1.0-second blanking period, AND gates76and74are enabled (the output of timer77goes to logic one). If an out-of-voltage range condition from an plugged adapter is detected (the outputs of comparators72or73go to logic zero) after the 1.0-second blanking period, the output of AND gate74goes to logic zero causing the output of OR gate64to go to logic one setting SD latch65to logic one and turning ON light emitting diode (LED)66signaling an out-of-voltage range fault. The output of AND gate62is gated to logic zero by setting the output of SD latch65to logic one, thus turning OFF NFET54and thus PFETs36and37. In this case, VSYS39remains connected to battery44via PFET45.

When a correct input voltage from an adapter plugged into connector31is detected (DCOK transitions to a logic one) and after the 1.0-second blanking period, the output of AND gate74transitions to logic one. The output of timer57has a 2.0-second delay time from the start of UVLO70during which time it is a logic zero. Therefore, the output of AND gate75is at logic one during this period turning ON the pre-charge circuit comprising resistor52, NFET59, and PFET58. DCIN131acts to charge VSYS39via resistor R52, PFET58and the body diode110across PFET36. The output of comparator61is enabled by a logic one at the output of timer57after its 2.0 second time out. If VSYS39has charged to more than 2 volts when output of timer57goes to logic one, then both inputs of OR gate64are low and the input of SD latch65is disabled and its output is logic zero enabling gate62. When the output of timer57goes to logic one, NFET54turns ON and PFET45turns OFF. When NFET54turns ON, both PFETs36and37turn ON and DCIN131powers VSYS39(correct adapter).

After a 2.0-second delay of timer57from power up (signal108), the output of timer57goes to logic one and enables the output of comparator61via AND gate63, enabling the short circuit protection circuit comprising SD latch65and AND gate62. It also turns OFF the pre-charging NFET59by disabling AND gate75. If there is a short-circuit fault in the system, then VSYS39will not rise at all and the output of comparator61will be high after timer57enables AND gate63. When the output of comparator61goes to logic one, it causes the output of AND gate63to go to logic one. OR gate64then goes to logic one and triggers SD latch65turning ON LED66signaling a short-circuit condition. However, if there is no short-circuit condition, VSYS39will be charged via R52and PFET58to above 2.0 volts by the time the 1.0-second pre-charge time has expired. The output of comparator61then goes to logic zero and SD latch65is not triggered. The output of AND gate62goes to logic one after the 2.0-second time turning OFF PFET45and turning ON NFET54and thus PFETs36and37. The power source to VSYS39is switched from battery44to voltage DCIN131.

If a reversed-polarity adapter is plugged into connector31, a negative voltage will appear across R42and LED43. The negative voltage causes LED43to turn ON. An ON LED43sends a visible signal to the user notifying the user of a fault condition. Additionally, diode32prevents capacitor33from being charged by a negative input voltage and clamping diode51prevents VSEN71from going below a negative 0.7 volt.

If DCIN131is a negative voltage, VCC80is not charged and IC50keeps power-up NFET54from turning ON since UVLO70will not be activated and signal108will not enable timers57,77and SD latch65. PFET45is kept ON by the action of the voltage of battery44and pull-down resistor R56.

FIG. 4is a flow diagram of method steps performed by circuitry in embodiments of the present invention. In step441an adapter is plugged into the system. In step442a test is done to determine if the under voltage low voltage (UVLO) circuit is turned ON. If the result of the test in step442is NO, then in step454a determination is made whether there is no input voltage or the input voltage is reversed. In step455, a user gets a correct functioning adapter and returns to step441. If the result of the test in step442is YES, then in step443, 1.0-second timer77and 2.0-second timer457are started. In step444, a test is the done to determine if timer77has timed out. If the result of the test is NO, then a wait is executed. If the result of the test in step444is YES, then in step445the outputs of window comparators72and73are enabled. A test is done in step449to determine if the input voltage DCIN131is in the proper voltage range. If the result of the test in step449is NO, then in step446a shutdown is executed and SD latch65is set and an LED66is turned on indicating an out-of-range fault. Operation is then ended awaiting fault correction. If the result of the test in step449is YES, then in step448a test is done to determine if timers457are timed out. If the result of the test in step448is NO, then in step450NFET59and PFET58are turned ON enabling short circuit detection and a return is executed back to step448. If the result of the test in step448is YES, then in step451a test is done to determine if input voltage VSYS39is greater than 2.0 volts. If the result of the test in step451is YES, then in step453PFETs36and37are turned ON coupling the adapter voltage to the system input and PFET58and NFET59are turned OFF disabling the short circuit detection. A branch is then taken back to step449. A loop through steps449,448,453, back to449will continue as long as the adapter remains plugged and conditions are correct. If the result of the test in step451is NO, then in step452a shutdown is executed and shutdown (SD) latch65is set to signal a short circuit fault. A branch is then taken to447where an END is executed awaiting a fix for the short circuit condition.

FIG. 5is a circuit diagram of an embodiment of the present invention. Circuit130comprises a protection IC150and additional discrete circuitry. IC150comprises reversed-polarity detection circuitry, out-of-range protection circuitry, and short-circuit protection circuitry. IC150also comprises a shutdown latch circuit165and two timers157and177. In addition to detecting out-of-range input voltage condition, a short-circuit condition, reversed-polarity faults and disconnecting a wrong adapter for the system, circuit130further comprises an out-of-range alert circuit and a reversed-polarity alert circuit. These alert circuits may notify an intelligent host system such as a laptop computer or a hand-held computer of the exact cause of the fault using signal states. After receiving an alert signal, the host system may in-turn signal a user that an improper adapter is plugged in to the system. While IC150is shown to have all of the above circuitry, portions or all of this circuitry could also be implemented in discrete form and still be within the scope of the present invention.

The system voltage (VSYS)139is normally provided by internal battery144through PFET145. Internal battery144is equipped with its own short circuit protection switch147that is normally closed but opens in case of a high current condition indicative of a short circuit. If an AC adapter is unplugged, battery144via body diode209quickly powers VSYS139until the circuitry turns ON PFET145. When a correct alternating current (AC) adapter (not shown) having a proper voltage and polarity is plugged in (via connector131) to power a system (not shown) coupled to VSYS139, IC150would normally turn OFF FET145and turn ON PFET136and PFET137. When a correct voltage AC adapter is plugged in, its normal voltage DCIN231back biases body diode209. At this point, VSYS139is powered by the voltage at DCIN231. The details of the operation of the circuitry ofFIG. 5under all conditions are detailed in the following description.

With the correct adapter plugged in, reference and under-voltage lockout (UVLO) circuit170starts (via signal208) the power up of IC150. UVLO170generates two reference voltages, V206(0.8 volt) and V207(1.1 volt). The sense voltage VSEN171is coupled to the positive input of comparator172as well as to the negative input of comparator173. The negative input of comparator172is coupled to V206and the positive input of comparator173is coupled to V207. A voltage divider (shown as 5 to 1 inFIG. 5) comprising a resistor R134(40 kΩ) and a resistor R135(10 kΩ) scales down DCIN231to a lower voltage. AND gate174, which is receiving the outputs of “window comparators”172and173, goes to logic one only when DCIN231is between 4.0 volt and 5.5 volt (5 times 0.8 volts and 1.1 volts).

1.0-second timer177and a 2.0-second timer157are started by signal208when UVLO170is activated. The voltage on capacitor C133exceeding a turn on threshold activates UVLO170. Shut down (SD) latch165is also started by signal208. The 1.0-second blanking period of timer177delays the out-of-range protection circuit from acting on the initial plug-in condition of an adapter coupled to connector131during which the electrical contacts (not shown) may be intermittent and bouncing. After the 1.0-second blanking period, AND gates176and174are enabled (the output of timer177goes to logic one). If an out-of-voltage range condition from a plugged-in adapter is detected (the outputs of comparators172or173go to logic zero) after the 1.0-second blanking period, the output of AND gate174goes to logic zero causing the output of OR gate164to go to logic one setting SD latch165to logic one and turning ON LED166signaling an out-of-voltage range fault. The output of AND gate162is gated to logic zero by setting the output of SD latch165to logic one, thus turning OFF NFET154and thus PFETs136and137. In this case, VSYS139remains connected to battery144via PFET145.

In the case where a correct input voltage from an adapter plugged into connector131) is detected (DCOK is a logic one) and after the 1.0-second blanking period, the output of AND gate174goes to logic one. The output of timer157has a 2.0-second delay time from the start of UVLO170during which time it is a logic zero. Therefore, the output of AND gate175is at logic one during this period turning ON the pre-charge circuit comprising resistor152, NFET159, and PFET158. DCIN231acts to charge VSYS139via resistor R152, PFET158and the body diode210across PFET136. The output of comparator161is enabled by logic one at the output of timer157after its 2.0-second time out. If VSYS139has charged to more than 2 volts when output of timer157goes to logic one, then both inputs of OR gate164are low and the input of SD latch165is disabled and its output is logic zero enabling gate162. When the output of timer157goes to logic one, NFET154turns ON and PFET145turns OFF. When NFET154turns ON, both PFETs136and137turn ON and DCIN231powers VSYS139.

After a 2.0-second delay of timer157from power up (signal208), the output of timer157goes to logic one and enables the output of comparator161via AND gate163, enabling the short circuit protection circuit comprising SD latch165and AND gate162. It also turns OFF the pre-charging NFET159by disabling AND gate175. If there is a short-circuit fault in the system, then VSYS139will not rise at all and the output of comparator161will be high after timer157enables AND gate163. When the output of comparator161goes to logic one, it causes the output of AND gate163to go to logic one. OR gate164then goes to logic one and triggers SD latch165turning ON LED166signaling a short-circuit condition. However, if there is no short-circuit condition, VSYS139will be charged up via R152and PFET158to above 2.0 volt after the 1.0-second of pre-charge time. The output of comparator161then goes to logic zero and SD latch165is not triggered. The output of AND gate162goes to logic one after the 2.0-second time turning OFF PFET145and turning ON NFET154and thus PFETs136and137. The power source to VSYS139is switched from battery144to voltage DCIN231.

If a reversed-polarity adapter is plugged into connector131, a negative voltage will appear across R142and LED143. The negative voltage causes LED143to turn ON. An ON LED143sends a visible signal to the user notifying the user of a fault condition. Additionally, diode132prevents capacitor133from being charged by a negative input voltage and clamping diode151prevents VSEN171from going below a negative 0.7 volt.

If DCIN231is a negative voltage, VCC180is not charged and IC150keeps power-up NFET154from turning ON as UVLO170will not be activated and signal208will not enable timers157,177and SD latch165. Since neither time157or177are activated, their outputs never transition to logic one and NFET154can never turn ON. PFET145is kept ON by the action of the voltage of battery144and pull-down resistor R156.

A reversed-polarity alert circuit comprises a NPN transistor (T)94, a blocking diode143, a current-limiting resistor92and an inverter gate93. The collector of T94is connected to the input of inverter gate93as well as to a system voltage91via resistor92. Inverter gate93is also powered by voltage91provided by the host system, normally at 3.3 volts. The base of transistor94is connected to ground201. The emitter of T94is connected to DCIN231via LED143and resistor142.

In the event a reversed-polarity adapter (not shown) is plugged into connector131, a negative voltage at DCIN231will force a base current IB97from ground through the base-emitter junction of transistor94, diode143, and resistor142. IB97turns ON T94to saturation causing its collector to emitter voltage (VCE) to drop to less than 0.2 volts. Since the base to emitter (VBE) voltage drop of T92is at approximately 0.7 volts, the voltage at the emitter (VRV98) of T94will be at negative 0.7 volts relative to ground201, and the collector voltage (99) of T94is at approximately negative 0.5 volts relative to ground201. Inverter gate93goes to logic one signaling reverse voltage alert (RVA)95to the host system (not shown). An electrostatic discharge (ESD) clamping diode151prevents the application of a negative voltage DCIN231from pulling VSEN171below approximately negative 0.7 volts relative to ground201. IC150is not powered up if DCIN231is a negative voltage. However, in the event no adapter or an adapter with right polarity is plugged in, DCIN231will at a voltage greater than or equal to zero, in which case T94will not be turned ON and RVA95remains at logic zero.

On the other hand, if an adapter with a proper voltage range and polarity is plugged in, a pre-charge circuit comprising resistor152and PFET158are turned ON. If there is no short-circuit fault, NFET switches154and PFETs136and137are be turned ON and PFET145is turned OFF after two seconds from the initial power-up. The power source to the system is switched from battery144to the voltage DCIN231.