SEMICONDUCTOR DEVICE

A novel semiconductor device is provided. The semiconductor device includes a first layer; a second layer over the first layer; and a third layer over the second layer. The first layer includes a functional circuit including a first transistor, the second layer includes a plurality of pixel circuits each including a second transistor, the third layer includes a plurality of light-emitting elements, one of the plurality of pixel circuits is electrically connected to one of the plurality of light-emitting elements, the functional circuit has a function of controlling an operation of the pixel circuit, and the pixel circuit has a function of controlling emission luminance of the light-emitting element.

TECHNICAL FIELD

One embodiment of the present invention relates to a semiconductor device.

BACKGROUND ART

In recent years, higher resolution of display apparatuses have been desired. For example, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR) are given as devices requiring high-resolution display apparatuses and have been actively developed in recent years. Display apparatuses used for these devices are required to be downsized as well as to have higher resolutions.

VR, AR, SR, and MR are collectively referred to as xR. Examples of a display apparatus for xR include a liquid crystal display apparatus and a light-emitting device including a light-emitting element such as an organic EL (Electro Luminescence) element or a light-emitting diode (LED).

For example, the basic structure of an organic EL element is a structure in which a layer containing a light-emitting organic compound is provided between a pair of electrodes. By applying a voltage to this element, light emission can be obtained from the light-emitting organic compound. A display apparatus using such an organic EL element does not need a backlight that is necessary for a liquid crystal display apparatus and the like; thus, a thin, lightweight, high-contrast, and low-power display apparatus can be achieved. Patent Document 1, for example, discloses an example of a display apparatus using an organic EL element.

REFERENCE

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

For display apparatuses for xR, reduction in size, low power consumption, and multifunction are required.

An object of one embodiment of the present invention is to provide a downsized display apparatus. An object of one embodiment of the present invention is to provide a display apparatus which can achieve high color reproducibility. An object of one embodiment of the present invention is to provide a high-resolution display apparatus. An object of one embodiment of the present invention is to provide a display apparatus with high emission luminance. An object of one embodiment of the present invention is to provide a highly reliable display apparatus. An object of one embodiment of the present invention is to provide a novel display apparatus.

Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not have to achieve all these objects. Objects other than these can be derived from the description of the specification, the drawings, the claims, and the like.

Means for Solving the Problems

(1) One embodiment of the present invention is a semiconductor device including a first layer; a second layer over the first layer; and a third layer over the second layer, in which the first layer includes a functional circuit including a first transistor, the second layer includes a plurality of pixel circuits each including a second transistor, the third layer includes a plurality of light-emitting elements, one of the plurality of pixel circuits is electrically connected to one of the plurality of light-emitting elements, the functional circuit has a function of controlling an operation of the pixel circuit, and the pixel circuit has a function of controlling emission luminance of the light-emitting element.

In (1), Si transistors may be used as the first transistor and the second transistor. The first layer and the second layer may include regions that are connected to each other by Cu—Cu bonding.

In (1), an OS transistor may be used as the second transistor.

(2) Another embodiment of the present invention is a semiconductor device including a first layer; a second layer over the first layer; and a first member over the second layer. The first layer includes a functional circuit, the second layer includes a display portion including a plurality of pixels and a plurality of storage units, each of the plurality of pixels includes a pixel circuit and a light-emitting element over the pixel circuit, the plurality of storage units are arranged along at least part of the outer periphery of the display portion, and the display portion and the plurality of storage units are covered with the first member. In (2), the storage unit is preferably arranged in a sealing region. In (2), the third layer may have a light-transmitting property.

(3) One embodiment of the present invention is a semiconductor device including a first layer; a second layer over the first layer; and a third layer over the second layer. The first layer includes a storage unit including a plurality of memory cells, the second layer includes a functional circuit, the third layer includes a display portion including a plurality of pixels, the functional circuit includes a storage unit driver circuit and a display portion driver circuit, and each of the plurality of pixels includes a pixel circuit and a light-emitting element over the pixel circuit.

In (3), the memory cell includes a first transistor, the functional circuit includes a second transistor, the pixel circuit includes a third transistor. For example, a composition of a first semiconductor layer included in the first transistor and a composition of a second semiconductor layer included in the second transistor may be different from a composition of a third semiconductor layer included in the third transistor.

The above storage unit may include a DRAM. The light-emitting element may be an organic EL element. The light-emitting element may include a tandem structure. The diagonal size of the region the plurality of pixel circuits and the plurality of light-emitting elements is preferably greater than or equal to 0.5 inches and less than or equal to 2.0 inches. In other words, the diagonal size of the display portion is preferably greater than or equal to 0.5 inches and less than or equal to 2.0 inches.

The above functional circuit may include at least one of a CPU, a GPU, a super-resolution circuit, a sensor circuit, a communication circuit, and an input/output circuit. The first member may have a light-transmitting property.

Effect of the Invention

According to one embodiment of the present invention, a downsized display apparatus can be provided. Alternatively, a display apparatus which can achieve high color reproducibility can be provided. Alternatively, a high-resolution display apparatus can be provided. Alternatively, a display apparatus with high emission intensity can be provided. Alternatively, a highly reliable display apparatus can be provided. Alternatively, a novel display apparatus can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all the effects. Effects other than these can be derived from the description of the specification, the drawings, the claims, and the like.

MODE FOR CARRYING OUT THE INVENTION

In this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, and means a circuit including a semiconductor element (e.g., a transistor, a diode, or a photodiode), a device including the circuit, and the like. The semiconductor device also means all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component including a chip in a package are examples of the semiconductor device. Moreover, a memory device, a display apparatus, a light-emitting apparatus, a lighting device, an electronic device, and the like themselves may be semiconductor devices or may each include a semiconductor device.

In the case where there is description “X and Y are connected” in this specification and the like, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are regarded as being disclosed in this specification and the like. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or texts, a connection relationship other than one shown in drawings or texts is regarded as being disclosed in the drawings or the texts. Each of X and Y denotes an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

For example, in the case where X and Y are electrically connected, one or more elements that allow electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display device, a light-emitting device, and a load) can be connected between X and Y. Note that a switch is controlled to be in an on state or an off state. That is, a switch has a function of controlling whether or not current flows by being in a conduction state (on state) or a non-conduction state (off state).

For example, in the case where X and Y are functionally connected, one or more circuits that allow functional connection between X and Y (e.g., a logic circuit (an inverter, a NAND circuit, a NOR circuit, or the like); a signal converter circuit (a digital-analog converter circuit, an analog-digital converter circuit, a gamma correction circuit, or the like); a potential level converter circuit (a power supply circuit (a step-up circuit, a step-down circuit, or the like), a level shifter circuit for changing the potential level of a signal, or the like); a voltage source; a current source; a switching circuit; an amplifier circuit (a circuit that can increase signal amplitude, the amount of current, or the like, an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, or the like); a signal generation circuit; a memory circuit; a control circuit; or the like) can be connected between X and Y. For instance, even if another circuit is interposed between X and Y, X and Y are regarded as being functionally connected when a signal output from X is transmitted to Y.

Note that an explicit description that X and Y are electrically connected includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit interposed therebetween) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit interposed therebetween).

Even when independent components are electrically connected to each other in a circuit diagram, one component has functions of a plurality of components in some cases. For example, when part of a wiring also functions as an electrode, one conductive film has functions of both components: a function of the wiring and a function of the electrode. Thus, electrical connection in this specification includes, in its category, such a case where one conductive film has functions of a plurality of components.

In this specification and the like, a “capacitor” can be, for example, a circuit element having an electrostatic capacitance value higher than 0 F, a region of a wiring having an electrostatic capacitance value higher than 0 F, parasitic capacitance, or gate capacitance of a transistor. Therefore, in this specification and the like, a “capacitor” includes not only a circuit element that has a pair of electrodes and a dielectric between the electrodes, but also parasitic capacitance generated between wirings, gate capacitance generated between a gate and one of a source and a drain of a transistor, and the like. The terms “capacitor”, “parasitic capacitance”, “gate capacitance”, and the like can be replaced with the term “capacitance” and the like; conversely, the term “capacitance” can be replaced with the terms “capacitor”, “parasitic capacitance”, “gate capacitance”, and the like. The term “a pair of electrodes” of a “capacitor” can be replaced with “a pair of conductors”, “a pair of conductive regions”, “a pair of regions”, and the like. Note that the electrostatic capacitance value can be higher than or equal to 0.05 fF and lower than or equal to 10 pF, for example. As another example, the electrostatic capacitance value may be higher than or equal to 1 pF and lower than or equal to 10 μF.

In this specification and the like, a transistor includes three terminals called a gate, a source, and a drain. The gate is a control terminal for controlling the conduction state of the transistor. Two terminals functioning as the source and the drain are input/output terminals of the transistor. One of the two input/output terminals serves as the source and the other serves as the drain depending on the conductivity type (n-channel type or p-channel type) of the transistor and the levels of potentials applied to the three terminals of the transistor. Thus, the terms “source” and “drain” can be replaced with each other in this specification and the like. Furthermore, in this specification and the like, expressions “one of a source and a drain” (or a first electrode or a first terminal) and “the other of the source and the drain” (or a second electrode or a second terminal) are used in the description of the connection relation of a transistor. Depending on the transistor structure, a transistor may include a back gate in addition to the above three terminals. In that case, in this specification and the like, one of the gate and the back gate of the transistor may be referred to as a first gate and the other of the gate and the back gate of the transistor may be referred to as a second gate. Moreover, the terms “gate” and “back gate” can be replaced with each other in one transistor in some cases. In the case where a transistor includes three or more gates, the gates may be referred to as a first gate, a second gate, and a third gate, for example, in this specification and the like.

In this specification and the like, a “node” can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on the circuit configuration, the device structure, or the like. Furthermore, a terminal, a wiring, or the like can be referred to as a “node.”

Ordinal numbers such as “first”, “second”, and “third” in this specification and the like are used to avoid confusion among components. Thus, the ordinal numbers do not limit the number of components. In addition, the ordinal numbers do not limit the order of components. For example, a “first” component in one embodiment in this specification and the like can be referred to as a “second” component in other embodiments, the scope of claims, or the like. Furthermore, for example, a “first” component in one embodiment in this specification and the like can be omitted in other embodiments, the scope of claims, or the like.

In this specification and the like, terms for describing arrangement, such as “over”, “under”, “above”, and “below” are sometimes used for convenience to describe the positional relation between components with reference to drawings. The positional relation between components is changed as appropriate in accordance with a direction in which each component is described. Thus, the positional relation is not limited to the terms described in the specification and the like, and can be described with another term as appropriate depending on the situation. For example, the expression “an insulator positioned over (on) a top surface of a conductor” can be replaced with the expression “an insulator positioned under (on) a bottom surface of a conductor” when the direction of a drawing illustrating these components is rotated by 180°.

The term “over” or “under” does not necessarily mean that a component is placed directly over or directly under and directly in contact with another component. For example, the expression “electrode B over insulating layer A” does not necessarily mean that the electrode B is formed over and in direct contact with the insulating layer A, and does not exclude the case where another component is provided between the insulating layer A and the electrode B.

In this specification and the like, the terms “film”, “layer”, and the like can be interchanged with each other depending on the situation. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. As another example, the term “insulating film” can be changed into the term “insulating layer” in some cases. Alternatively, the term “film,” “layer,” or the like is not used and can be interchanged with another term depending on the case or the situation. For example, the term “conductive layer” or “conductive film” can be changed into the term “conductor” in some cases. Furthermore, for example, the term “insulating layer” or “insulating film” can be changed into the term “insulator” in some cases.

In addition, in this specification and the like, the term such as “electrode,” “wiring,” or “terminal” does not limit the function of a component. For example, an “electrode” is used as part of a wiring in some cases, and vice versa. Furthermore, the term “electrode” or “wiring” also includes the case where a plurality of “electrodes” or “wirings” are formed in an integrated manner, for example. For example, a “terminal” is used as part of a “wiring” or an “electrode” in some cases, and vice versa. Furthermore, the term “terminal” also includes the case where a plurality of “electrodes”, “wirings”, “terminals”, or the like are formed in an integrated manner, for example. Therefore, for example, an “electrode” can be part of a “wiring” or a “terminal”, and a “terminal” can be part of a “wiring” or an “electrode”. Moreover, the term “electrode”, “wiring”, “terminal”, or the like is sometimes replaced with the term “region”, for example.

In addition, in this specification and the like, the term such as “wiring,” “signal line,” or “power supply line” can be interchanged with each other depending on the case or the situation. For example, the term “wiring” can be changed into the term “signal line” in some cases. As another example, the term “wiring” can be changed into the term “power supply line” or the like in some cases. Conversely, the term such as “signal line” or “power supply line” can be changed into the term “wiring” in some cases. The term “power supply line” or the like can be changed into the term “signal line” or the like in some cases. Conversely, the term “signal line” or the like can be changed into the term “power supply line” or the like in some cases. Moreover, the term “potential” that is applied to a wiring can be sometimes changed into the term such as “signal” depending on the case or the situation. Conversely, the term “signal” or the like can be changed into the term “potential” in some cases.

In this specification, “parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −10° and less than or equal to 10°. Thus, the case where the angle is greater than or equal to −5° and less than or equal to 5° is also included. In addition, “approximately parallel” or “substantially parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −30° and less than or equal to 30°. Moreover, “perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 80° and less than or equal to 100°. Thus, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. Furthermore, “approximately perpendicular” or “substantially perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 60° and less than or equal to 120°.

Embodiments described in this specification are described with reference to the drawings. Note that the embodiments can be implemented in many different modes, and it will be readily understood by those skilled in the art that the modes and details can be changed in various ways without departing from the spirit and scope thereof. Therefore, the present invention should not be interpreted as being limited to the description in the embodiments. Note that in the structures of the invention in the embodiments, the same reference numerals are used in common for the same portions or portions having similar functions in different drawings, and repeated description thereof is omitted in some cases. Moreover, some components are omitted in a perspective view, a top view, and the like for easy understanding of the diagrams in some cases.

In addition, in the drawings in this specification, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, embodiments of the present invention are not limited to the size, aspect ratio, and the like illustrated in the drawings. Note that the drawings schematically illustrate ideal examples, and embodiments of the present invention are not limited to shapes, values, and the like illustrated in the drawings. For example, variation in signal, voltage, or current due to noise or variation in signal, voltage, or current due to difference in timing can be included.

In this specification and the like, when a plurality of components are denoted by the same reference numerals, and in particular need to be distinguished from each other, an identification sign such as “A”, “b”, “_1”, “[n]”, or “[m,n]” are sometimes added to the reference numerals.

A semiconductor device of one embodiment of the present invention will be described. Note that the semiconductor device of one embodiment of the present invention can function as a display apparatus.

<Structure Example of Semiconductor Device100A>

FIG.1AandFIG.2are perspective views of a semiconductor device100A of one embodiment of the present invention.FIG.1Bis a block diagram illustrating a structure of the semiconductor device100A. The semiconductor device100A includes a layer20over a layer10, a layer30over the layer20, and a sealing substrate40over the layer30. The layer30includes a plurality of pixel circuits51, and a layer60is provided between the sealing substrate40and the plurality of pixel circuits51. InFIG.2, the layer10, the layer20, the layer30, the layer60, the sealing substrate40, and the like are separated and illustrated for easy understanding of the structure of the semiconductor device100A.

The layer10includes a storage unit11. The storage unit11includes a plurality of memory cells12. The memory cell12functions as a memory element. Various storage systems of storage devices can be used for the storage unit11. For example, a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), a phase-change memory (PCM), a resistive random access memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), an antiferroelectric memory or the like may be used.

In addition, a flash memory may be used as the storage unit11. In addition, a NOSRAM (Nonvolaite Oxide Semiconductor Random Access Memory) or a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) may be used as the storage unit11, for example. NOSRAM and DOSRAM are each one kind of storage devices using a transistor including an oxide semiconductor in a channel formation region (hereinafter also referred to as an “OS transistor”).

The storage unit11may include a plurality of kinds of storage devices. For example, a nonvolatile storage device and a volatile storage device may be provided. The storage unit11has a function of holding various programs used in the semiconductor device100A and data and the like necessary for operation of the semiconductor device100A.

The layer20includes a functional circuit90and a terminal portion29. The functional circuit90includes a CPU (Central Processing Unit)21, a GPU (Graphics Processing Unit)22, a display portion driver circuit23, a storage unit driver circuit24, a super-resolution circuit25, a sensor circuit26, a communication circuit27, and an input/output circuit28.

Note that the functional circuit90does not necessarily include all of the circuits, and may include another structure. For example, a potential generating circuit that generate a plurality of different potentials, and/or a power management circuit for controlling supply and stop of electrical power for each circuit included in the semiconductor device100A may be provided. The supply and stop of electrical power may be performed per circuit included in the CPU21. For example, power consumption can be reduced by stopping supply of electrical power to a circuit, which is determined to be not used for a while, of the circuits included in the CPU21, and restarting the supply of electrical power to the circuit as needed. Data necessary for restarting supply of electrical power may be stored in a storage circuit in the CPU21, the storage unit11, or the like before stopping the circuit. By storing data necessary for recovery of the circuit, high-speed recovery of the circuit stopped can be performed. Note that supply of a clock signal may be stopped to stop the circuit operation.

The CPU21has a function of controlling operations of the GPU22and the circuit provided in the layer20, following the program stored in the storage unit11. The GPU22has a function of performing arithmetic processing for generating image data. Furthermore, the GPU22can perform a large number of matrix operations (product-sum operations) in parallel and thus, can perform arithmetic operation using a neural network at high speed, for example. The GPU22has a function of correcting image data using correction data stored in the storage unit11, for example. For example, the GPU22has a function of generating image data in which brightness, hue, and/or contrast, or the like is corrected.

The display portion driver circuit23is electrically connected to the plurality of pixel circuits51included in the layer30, and has a function of supplying image data to the plurality of pixel circuits51. Any of various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, and a logic circuit can be used as the display portion driver circuit23.

The layer60is provided to overlap with the layer30. The layer60includes a plurality of light-emitting elements61. One light-emitting element61and one pixel circuit51are electrically connected to each other and function as one pixel. The pixel circuit51controls the emission luminance of the light-emitting element61. In addition, the display portion31is formed using a plurality of pixels. In other words, the display portion31includes a plurality of pixels. The layer60may be included in the layer30. In this case, it can be said that the display portion31is included in the layer30. The pixel circuit51and the light-emitting element61are described later.

The super-resolution circuit25has a function of determining a potential of any pixel included in the display portion31by a product-sum operation of weights and potentials of pixels in the periphery of the pixel. The super-resolution circuit25has a function of upconverting image data with a lower definition than that of the display portion31. The super-resolution circuit25has a function of downconverting image data with a higher definition than that of the display portion31.

Note that upconversion and downconversion of image data can be performed by the GPU22; however, providing the super-resolution circuit25can reduce the load on the GPU22. For example, the GPU22executes processing up to 2K definition (or 4K definition) and the super-resolution circuit25performs upconversion to 4K definition (or 8K definition), whereby the load on the GPU22can be reduced. Consequently, the operating speed of the semiconductor device100A can be increased.

The storage portion driver circuit24is electrically connected to the storage unit11included in the layer10, and has a function of writing and reading data in and out of the storage unit11.

The sensor circuit26has a function of obtaining information on one or more of the senses of sight, hearing, touch, taste, and smell of a human. Specifically, the sensor circuit26has at least one of functions of sensing or measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, magnetism, temperature, sound, time, electric field, current, voltage, electric power, radiation, humidity, gradient, oscillation, a smell, and infrared rays. The sensor circuit26may have a function other than the functions.

The communication circuit27has a wireless or wired communication function. In particular, the communication circuit27preferably has a wireless communication function, in which case the number of parts such as a connection cable can be decreased.

In the case where the communication circuit27has a wireless communication function, the communication circuit27can perform communication via an antenna. As a communication protocol or a communication technology, a communications standard such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), or W-CDMA (registered trademark), or an IEEE communications standard such as Wi-Fi (registered trademark), Bluetooth (registered trademark), or ZigBee (registered trademark) can be used.

The communication circuit27can perform input/output of information by connecting the semiconductor device100A to another device via a computer network such as the Internet, which is an infrastructure of the World Wide Web (WWW), an intranet, an extranet, a PAN (Personal Area Network), a LAN (Local Area Network), a CAN (Campus Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), or a GAN (Global Area Network).

The input/output circuit28has a function of distributing signals supplied to the semiconductor device100A through the terminal portion29to circuits such as the CPU21and/or the GPU22. In addition, the input/output circuit28has a function of distributing signals supplied to the semiconductor device100A through the communication circuit27to the circuits such as the CPU21and/or the GPU22.

The input/output circuit28has a function of outputting signals to the outside through the terminal portion29. The input/output circuit28has function of outputting signals to the outside through the communication circuit27.

Since the FPC (Flexible printed circuits) or the like is electrically connected to the terminal portion29, the layer30and the sealing substrate40are not formed in the region overlapping with the terminal portion29.

FIG.3is a block diagram illustrating a structure example of the display portion driver circuit23. The display portion driver circuit23includes a control circuit71, a timing controller72, a serial-parallel conversion circuit73, a latch circuit74, a DAC75, an amplifier circuit76, a first driver circuit232, and a second driver circuit233. Note that the display portion driver circuit23does not necessarily include all of the structures, or may include a structure other than the structures.

The control circuit71is electrically connected to the timing controller72, the serial-parallel conversion circuit73, the latch circuit74, the DAC75, the amplifier circuit76, the first driver circuit232, and the second driver circuit233and has a function of controlling the operation of the display portion driver circuit23. For example, the control circuit71controls the output characteristics of the DAC75, the stop of the amplifier circuit76while a displayed image is not updated, and the like. In the case where the display portion31is divided into a plurality of subpanels and is driven, the control circuit71has a function of controlling the operation of each subpanel. The control circuit71may further have a function of controlling the setting conditions of weights used in the GPU22, the super-resolution circuit25, and the like, for each subpanel.

The timing controller72has a function of controlling the timing of updating a display image in accordance with the frame frequency. In the case where the display portion31is divided into a plurality of subpanels and driven, the timing controller72has a function of controlling the timing of updating image displayed, for each subpanel.

The serial-parallel conversion circuit73has a function of distributing digital image signals input by a serial-communication method to each signal line (e.g., a wiring237described later). The distributed digital image signal is temporarily stored in the latch circuit74and then is converted into an analog image signal by the DAC75. The analog image signal is amplified by the amplifier circuit76and supplied to the signal line.

FIG.4Ais a block diagram illustrating a connection relation between the display portion driver circuit23and the display portion31.

The display portion driver circuit23includes the first driver circuit232and the second driver circuit233. A circuit included in the first driver circuit232functions as, for example, a scan line driver circuit. A circuit included in the second driver circuit233functions as, for example, a signal line driver circuit. Some sort of circuit may be provided to face the first driver circuit232with the display portion31placed therebetween. Some sort of circuit may be provided to face the second driver circuit233with the display portion31placed therebetween.

The display portion driver circuit23is referred to as a “peripheral driver circuit” in some cases. Any of various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, and a logic circuit can be used as the peripheral driver circuit. In the peripheral driver circuit, a transistor, a capacitor, and the like can be used.

The display portion31includes m wirings236(m is an integer of 1 or more) which are arranged substantially parallel to each other and whose potentials are controlled by the circuit included in the first driver circuit232, and n wirings237(n is an integer of 1 or more) which are arranged substantially parallel to each other and whose potentials are controlled by the circuit included in the second driver circuit233. The wiring236is electrically connected to the first driver circuit232. The wiring237is electrically connected to the second driver circuit233.

The display portion31includes a plurality of pixels230arranged in a matrix. For example, the pixel230that controls red light, the pixel230that controls green light, and the pixel230that controls blue light are allowed to collectively function as one pixel240and the amount of light (emission luminance) emitted from each pixel230is controlled, whereby full-color display can be performed. Thus, each of the three pixels230functions as a subpixel. That is, three subpixels control the emission amount or the like of red light, green light, and blue light (see FIG.4B1). The light colors controlled by the three subpixels are not limited to a combination of red (R), green (G), and blue (B) and may be cyan (C), magenta (M), and yellow (Y) (see FIG.4B2). The areas of the three subpixels are not necessarily equal. In the case where the emission efficiency, the reliability, and the like are different depending on emission colors, the areas of subpixels may be different depending on emission colors (see FIG.4B3). Note that the arrangement of the subpixels in FIG.4B3may be called “S stripe arrangement”.

Four subpixels may collectively function as one pixel. For example, a subpixel that controls white light (W) may be added to the three subpixels that control red light, green light, and blue light (see FIG.4B4). The addition of the subpixel that controls white light can increase the luminance of a display region. Alternatively, a subpixel that controls yellow light may be added to the three subpixels that control red light, green light, and blue light (see FIG.4B5). Alternatively, a subpixel that controls white light may be added to the three subpixels that control cyan light, magenta light, and yellow light (see FIG.4B6).

When the number of subpixels functioning as one pixel is increased and subpixels that control light of red, green, blue, cyan, magenta, yellow, and the like are used in an appropriate combination, the reproducibility of halftones can be increased. Therefore, the color reproducibility can be improved.

The display apparatus of one embodiment of the present invention can reproduce the color gamut of various standards. For example, the display apparatus of one embodiment of the present invention can reproduce the color gamut of the PAL (Phase Alternating Line) standard and the NTSC (National Television System Committee) standard used for TV broadcasting; the sRGB (standard RGB) standard and the Adobe RGB standard widely used for display apparatuses used in electronic devices such as personal computers, digital cameras, and printers; the ITU-R BT.709 (International Telecommunication Union Radiocommunication Sector Broadcasting Service (Television) 709) standard used for HDTV (High Definition Television, also referred to Hi-Vision); the DCI-P3 (Digital Cinema Initiatives P3) standard used for digital cinema projection; the ITU-R BT.2020 (REC.2020 (Recommendation 2020)) standard used for UHDTV (Ultra High Definition Television, also referred to as Super Hi-Vision); and the like.

Using the pixels240arranged in a matrix of 1920×1080, the display portion31can achieve full color display with a definition of a so-called full hi-vision (also referred to as 2K definition, 2KIK, 2K, or the like). For example, using the pixels240arranged in a matrix of 3840×2160, the display portion31can achieve full color display with a definition of ultra hi-vision (also referred to as 4K definition, 4K2K, 4K, or the like). For example, using the pixels240arranged in a matrix of 7680×4320, the display portion31can achieve full color display with a definition of super hi-vision (also referred to as 8K definition, 8K4K, 8K, or the like). By increasing the number of pixels240, the display portion31that can perform full-color display with 16K or 32K definition can also be obtained.

The pixel density (resolution) of the display portion31is preferably higher than or equal to 1000 ppi and lower than or equal to 10000 ppi. For example, the resolution may be higher than or equal to 2000 ppi and lower than or equal to 6000 ppi, or higher than or equal to 3000 ppi and lower than or equal to 5000 ppi.

Note that there is no particular limitation on the screen ratio (aspect ratio) of the display portion31. For example, the display portion31of the semiconductor device100A is compatible with a variety of screen ratios such as 1:1 (a square), 4:3, 16:9, and 16:10.

In the case where the semiconductor device100A is used as a display apparatus for xR, the display portion31can have a screen diagonal greater than or equal to 0.1 inches and less than or equal to 5.0 inches, preferably greater than or equal to 0.5 inches and less than or equal to 2.0 inches, further preferably greater than or equal to 1 inch and less than or equal to 1.7 inches. For example, the display portion31may have a screen diagonal of 1.5 inches or approximately 1.5 inches. When the display portion31has a screen diagonal less than or equal to 2.0 inches, preferably, approximately 1.5 inches, the number of times of light exposure treatment using a light exposure apparatus (typified by a scanner apparatus) can be one; thus, the productivity of a manufacturing process can be improved.

InFIG.5, an example of a circuit configuration of the pixel230is illustrated. The pixels230each include the pixel circuit51and the light-emitting element61.FIG.5Aillustrates the connection of the elements included in the pixel230.FIG.5Bschematically illustrates the vertical positional relation between the layer20including the display portion driver circuit23, the layer30including the pixel circuit51, and the layer60including the light-emitting element61.

The pixel circuit51illustrated as an example inFIGS.5A and5Bincludes a transistor52A, a transistor52B, a transistor52C, and a capacitor53. The transistor52A, the transistor52B, and the transistor52C can be OS transistors. Each of the OS transistors of the transistor52A, the transistor52B, and the transistor52C preferably includes a back gate electrode, in which case the back gate electrode can be supplied with the same signal as the gate electrode or the back gate electrode can be supplied with a signal different from that of the gate electrode.

The transistor52B includes a gate electrode electrically connected to the transistor52A, a first terminal electrically connected to the light-emitting element61, and a second terminal electrically connected to a wiring ANO. The wiring ANO is a wiring for supplying a potential for supplying current to the light-emitting element61.

The transistor52A includes a first terminal electrically connected to the gate electrode of the transistor52B and a second terminal electrically connected to a wiring SL which functions as a source line, and has a function of controlling its conduction state or non-conduction state on the basis of the potential of a wiring GL1which functions as a gate line.

The transistor52C includes a first terminal electrically connected to a wiring VO and a second terminal electrically connected to the light-emitting element61, and has a function of controlling its conduction state or non-conduction state on the basis of the potential of a wiring GL2which functions as a gate line. The wiring VO is a wiring for supplying a reference potential and a wiring for outputting current flowing through the pixel circuit51to the display portion driver circuit23.

The capacitor53includes a conductive film electrically connected to the gate electrode of the transistor52B and a conductive film electrically connected to the second electrode of the transistor52C.

The light-emitting element61includes a first electrode electrically connected to the first terminal of the transistor52B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for supplying a potential for supplying current to the light-emitting element61.

Accordingly, the intensity of light emitted from the light-emitting element61can be controlled in accordance with an image signal supplied to the gate electrode of the transistor52B. Furthermore, variations in the gate-source potential of the transistor52B can be inhibited by the reference potential of the wiring VO supplied through the transistor52C.

A current value that can be used for setting of pixel parameters can be output from the wiring VO. Specifically, the wiring VO can function as a monitor line for outputting a current flowing through the transistor52B or a current flowing through the light-emitting element61to the outside. A current output to the wiring VO may be converted into a voltage by a source follower circuit or the like.

As the light-emitting element61, a self-luminous display element such an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode. Also referred to as “organic EL element” or “OEL”) can be used. In addition, as the light-emitting element61, a self-luminous type light-emitting element such as a micro LED, a QLED (Quantum-dot Light Emitting Diode) or a semiconductor laser may be used.

Note that in the structure example illustrated as an example inFIG.5B, the wirings electrically connecting the pixel circuit51and the display portion driver circuit23can be shortened, so that wiring resistances of the wirings can be reduced. In addition, the parasitic capacitances of the wirings can be lowered. Thus, data can be written at high speed, which enables high-speed driving of the display portion31. Therefore, even when the number of the pixel circuits51is increased, a sufficient frame period can be ensured, and thus, the pixel density of the display portion31can be increased. In addition, the increased pixel density of the display portion31can increase the resolution of an image displayed on the display portion31. For example, the pixel density of the display portion31can be higher than or equal to 1000 ppi, higher than or equal to 5000 ppi, or higher than or equal to 7000 ppi. Thus, the semiconductor device100A can be used in display apparatuses for xR such as AR or VR, for example. The semiconductor device100A of one embodiment of the present invention can be favorably used for an electronic device whose display portion is close to a user, such as an HMD.

FIG.6Aillustrates a variation example of the circuit configuration of the pixel230illustrated inFIG.5A. The circuit configuration inFIG.6Ais a configuration excluding the transistor52C, the wiring GL2, and the wiring VO from the circuit configuration illustrated inFIG.5A.

For example, as illustrated inFIG.6B, a transistor including a backgate may be used as the transistor52A and the backgate and the gate may be electrically connected to each other. In addition, as in the transistor52B illustrated inFIG.6B, the back gate and one of the source and the drain of the transistor may be electrically connected to each other.

As described above, the semiconductor device100A of one embodiment of the present invention has a structure in which the display portion31, the functional circuit90, and the storage unit11are stacked. The display portion31, the functional circuit90, and the storage unit11are stacked, whereby the semiconductor device100A can be downsized. Furthermore, when the display portion driver circuit23is provided so as to overlap with the display portion31, the width of the bezel around the display portion31can be extremely small; thus, the area of the display portion31can be increased. Thus, the definition of the display portion31can be increased. Consequently, the display quality of the semiconductor device100A can be improved.

Under a fixed definition of the display portion31, the occupation area per pixel can be increased. Thus, the emission luminance of the display portion31can be increased. Furthermore, the pixel aperture ratio can be increased. For example, the pixel aperture ratio can be greater than or equal to 40% and less than 100%, preferably greater than or equal to 50% and less than or equal to 95%, further preferably greater than or equal to 60% and less than or equal to 95%. By enlarging the occupation area per pixel, the density of current supplied to the pixels can be lowered. Accordingly, the load applied to the pixel is reduced, so that the reliability of the semiconductor device100A can be increased.

In addition, the display portion31, the functional circuit90, and the storage unit11are stacked, whereby the wiring for electrical connection between them can be shortened. Thus, the wiring resistance and the parasitic capacitance can be lowered, and the operation speed of the semiconductor device100A can be increased. In addition, power consumption of the semiconductor device100A is reduced.

For example, when a matrix arithmetic operation is performed in the GPU22, a large amount of data used for the arithmetic operation and data of the arithmetic operation are temporarily in the storage unit11. As the GPU22is closer to the storage unit11, a delay time is reduced, and high-speed arithmetic processing is possible.

In particular, a preferred structure is the structure in which the layer20including the functional circuit90is placed between the layer30including the display portion31and the layer10including the storage unit11, because the structure can shorten both wirings connecting the display portion31to the display portion driver circuit23and wirings connecting the storage unit11and the storage unit driver circuit24.

Although not illustrated, the layer10in the semiconductor device100A is preferably in contact with a material having a high thermal conductivity (e.g., a metal material such as a copper or aluminum).

Variation Example

Next, a variation example of the semiconductor device100A is described. In order to reduce repeated description, different points from the semiconductor device100A are mainly described. The description of the semiconductor device100A can be referred to for parts that are not described below.

Variation Example 1

FIG.7illustrates a semiconductor device100B, which is a variation example of the semiconductor device100A.FIG.7is a perspective view of the semiconductor device100B of one embodiment of the present invention. InFIG.7, the layer10, the layer20, the layer30, the layer60, the sealing substrate40, and the like are separated and illustrated for easy understanding of the structure of the semiconductor device100B.

The semiconductor device100B is different from the semiconductor device100A in the stacking order of the layer10and the layer20. Specifically, the semiconductor device100B includes the layer10over the layer20, the layer30over the layer10, and the sealing substrate40over the layer30. In addition, the semiconductor device100B includes a terminal portion19over the layer10instead of the terminal portion29over the layer20. Although not illustrated, the layer20in the semiconductor device100B is preferably in contact with a heat-radiation body. Note that the heat-radiation body refers to one having a function of releasing heat generated in the semiconductor device100B to the outside of the semiconductor device100B.

The semiconductor device of one embodiment of the present invention can change the stacking order of layers depending on the purpose or the usage.

Variation Example 2

FIG.8illustrates a semiconductor device100C, which is a variation example of the semiconductor device100A.FIG.8AandFIG.8Bare perspective views of the semiconductor device100C of one embodiment of the present invention. InFIG.8B, the layer10, the layer20, and the layer30are separated and illustrated for easy understanding of the structure of the semiconductor device100C.

The semiconductor device100C includes a terminal portion39in the layer30instead of the terminal portion29, without including the terminal portion29in the layer20.

Variation Example 3

FIG.9illustrates a semiconductor device100D, which is a variation example of the semiconductor device100A.FIG.9AandFIG.9Bare perspective views of the semiconductor device100D of one embodiment of the present invention. InFIG.9B, the layer20, the layer30, and the sealing substrate40are separated and illustrated for easy understanding of the structure of the semiconductor device100D.

The semiconductor device100D does not include the layer10, and includes a plurality of memory chips32serving as the storage unit11in the periphery of the display portion31over the layer30, instead of the layer10. The plurality of memory chips32are arranged along the outer periphery of the display portion31. The semiconductor device100D includes the memory chips32arranged in three sides of the display portion31, and the layer30and the layer20are electrically connected to each other with a plurality of wires38in the other one side. Note that the wires38may be formed by a wire bonding method.

As the memory chip32, a variety of memory devices such as a DRAM, an SRAM, or a flash memory can be used. The memory chips32can be mounted on the layer30by any of a variety of materials and methods, such as anisotropic conductive adhesive, ball bonding, and wire bonding. Alternatively, the memory chips32may be mounted on the layer30by Cu—Cu bonding (in which Cu pads on both sides are exposed and are in contact with each other at the bonding interface to establish electrical conduction) or a bond using a bump and TSV (Through Silicon Via).

The memory chip32is preferably arranged at a position overlapping with a sealing material712(also referred to as a “sealant”. The sealing material712is described below) with which the layer30and the sealing substrate40are attached to each other. A region where the layer30, the sealing material712, and the sealing substrate40overlap with each other is also referred to as a “sealing region”. The memory chips32are provided in the sealing region, whereby the memory chips32can be arranged efficiently.

In the case where the memory chips32overlap with the sealing material, the display portion31and the memory chips32are covered with the sealing substrate40. Covering the memory chips32with the sealing substrate40can prevent outside impurities and the like from diffusing into the memory chips32.

Variation Example 4

FIG.10illustrates a semiconductor device100E, which is a variation example of the semiconductor device100D.FIG.10AandFIG.10Bare perspective views of the semiconductor device100E of one embodiment of the present invention. InFIG.10B, the layer20, the layer30, and the sealing substrate40are separated and illustrated for easy understanding of the structure of the semiconductor device100E. Note that the layer60is not illustrated.

In the semiconductor device100E, the memory chips32are arranged at two opposite sides of four sides adjacent to the display portion31and the wires38for electrically connecting the layer30and the layer20are arranged at the other two sides.

By increasing the number of the wires38for electrically connecting the layer30and the layer20, the signal transmission speed between the layer30and the layer20can be increased.

Variation Example 5

FIG.11illustrates a semiconductor device100F, which is a variation example of the semiconductor device100D.FIG.11AandFIG.11Bare perspective views of the semiconductor device100F of one embodiment of the present invention. InFIG.11B, the layer20, the layer30, the sealing substrate40, and the like are separated and illustrated for easy understanding of the structure of the semiconductor device100F. Note that the layer60is not illustrated. The sealing substrate40included in the semiconductor device100F includes a plurality of cutout portions42. The cutout portions42are provided at positions overlapping with the memory chips32.

In the semiconductor device100F, the sealing substrate40and the layer30are attached to each other so that the memory chips32fit in the cutout portions42. The semiconductor device100E can be thinner than the semiconductor device100D.

Variation Example 6

FIG.12illustrates a semiconductor device100G, which is a variation example of the semiconductor device100D.FIG.12AandFIG.12Bare perspective views of the semiconductor device100G of one embodiment of the present invention. InFIG.12B, the layer20, the layer30, the sealing substrate40, and the like are separated and illustrated for easy understanding of the structure of the semiconductor device100G. Note that the layer60is not illustrated.

The semiconductor device100G is different from the semiconductor device100D in that the sealing substrate40overlaps with the display portion31without overlapping with the memory chip32.

Since the sealing substrate40overlaps with the display portion31without overlapping with the memory chip32, the thickness of the semiconductor device100G can be reduced. Furthermore, the weight of the semiconductor device100G can be reduced because the sealing substrate40becomes small.

Variation Example 7

FIG.13illustrates a semiconductor device100H, which is a variation example of the semiconductor device100C.FIG.13AandFIG.13Bare perspective views of the semiconductor device100H. The semiconductor device100H is different from the semiconductor device100C in not including the layer10. InFIG.13B, the layer20, the layer30, the sealing substrate40, and the like are separated and illustrated for easy understanding of the structure of the semiconductor device100H.

The semiconductor device100H is different from the semiconductor device100C in that the layer20includes the storage unit11. Since the layer10is not provided, the thickness of the semiconductor device100H can be reduced. In addition, the layer10is not provided, so that the weight of the semiconductor device100H can be reduced.

Variation Example 8

FIG.14illustrates a semiconductor device100I, which is a variation example of the semiconductor device100H.FIG.14AandFIG.14Bare perspective views of the semiconductor device100I. The semiconductor device100I is different from the semiconductor device100H in not including the layer20. InFIG.14B, the layer30, the sealing substrate40, and the like are separated and illustrated for easy understanding of the structure of the semiconductor device100I.

The semiconductor device100I includes the display portion driver circuit23and the pixel circuit51in the layer30. A functional circuit necessary for the layer30may be formed depending on the purpose and/or the usage. An unnecessary functional circuit is not provided depending on the purpose and/or the usage, whereby power consumption and manufacturing cost of the semiconductor device can be reduced. Furthermore, the thickness of the semiconductor device can be reduced, and thus the weight of the semiconductor device can be reduced.

The structures described in this embodiment can be used in an appropriate combination with any of the structures described in the other embodiments and the like.

In this embodiment, a structure example in which the display portion31included in the layer30is divided into a plurality of subpanels35is described.

FIG.15Aillustrates a structure example where the display portion31is divided into 32 subpanels35.FIG.15Aillustrates the subpanels35arranged in a matrix of four rows and eight columns. By dividing the display portion31into the plurality of subpanels35, operation of the subpanels35in a region in which a display image is not needed to be updated can be stopped. In other words, only the subpanels35in a region in which a display image is needed to be updated can be operated. Thus, the power consumption of the semiconductor device can be reduced.

The pixel circuit51is formed using an OS transistor having extremely low off-state current, so that data written to a pixel can be retained for a long time. Therefore, frame frequency of display can be set to an arbitrary value (can be variable). Furthermore, the display portion31can be driven per subpanel35. Therefore, the frame frequency can be set per subpanel35.

In the case where the display portion31is divided into the plurality of subpanels35, the first driver circuit232and the second driver circuit233that correspond to each subpanel35are provided in the layer20.FIG.15Billustrates an example in which the first driver circuit232and the second driver circuit233are provided in a region overlapping with the subpanel35. Note that inFIG.15B, a position corresponding to the outer edge portion of the subpanel35is illustrated by a dashed line. Although the first driver circuit232and the second driver circuit233provided per subpanel35are arranged so as to be intersect with each other at or near the center of the subpanel35in the example ofFIG.15B, one embodiment of the present invention is not limited thereto.

In the case where the layer10including the storage unit11is provided between the layer20and the layer30, the memory cells12are not placed in a region of the layer10overlapping with the first driver circuit232and the second driver circuit233. In this manner, the first driver circuit232and the second driver circuit233can be electrically connected to the subpanel35through the layer10in a short distance.

FIG.16Aillustrate a structure example of the layer10. InFIG.16A, a position corresponding to an outer edge portion of the subpanel35is illustrated by a dashed line.FIG.16Aillustrates an example in which a plurality of memory cells12are divided into four memory cell groups15in a region overlapping with the subpanel35. Furthermore, a region between adjacent memory cell groups15is a region overlapping with the first driver circuit232and the second driver circuit233included in the layer20and is not provided with the memory cells12.

FIG.16Bis a perspective view illustrating a region overlapping with one subpanel35in the layer10, the layer20, and the layer30. By not providing the memory cells12in a region overlapping with the first driver circuit232and the second driver circuit233included in the layer20, a conductor55that electrically connect the first driver circuit232and the second driver circuit233to the subpanel35can be extended in the stacking direction of the layer10, the layer20, and the layer30. Therefore, since the first driver circuit232and the second driver circuit233can be connected to the subpanel35in an extremely short distance, the wiring resistance and the parasitic capacitance can be reduced and high-speed operation can be performed. In addition, since the degradation of an image signal is small, the display quality of the semiconductor device is improved. Moreover, the power consumption of the semiconductor device can be reduced. Note that the conductor55is formed with a conductor, TSV, or the like provided in the layers.

In the semiconductor device of one embodiment of the present invention, data communication between the GPU22and the storage unit11can be performed in parallel by using a large number of wirings. Accordingly, the semiconductor device of one embodiment of the present invention can operate at high speed. In the semiconductor device of one embodiment of the present invention, it is unnecessary to compress image data that is processed arithmetically by the GPU22and stored in the storage unit11in accordance with a communication standard such as HDMI (registered trademark), MIPI (registered trademark), or Display port. Accordingly, the semiconductor device of one embodiment of the present invention can operate at high speed and reduce its power consumption.

The structures described in this embodiment can be used in an appropriate combination with any of the structures described in the other embodiments and the like.

The semiconductor device of one embodiment of the present invention may include a display correction system. The display correction system can reduce display defects based on defective pixels, such as bright spots and dark spots, by correcting current IELflowing to the light-emitting element61.

A circuit diagram illustrated inFIG.17Aillustrates an extracted part of the pixel circuit51illustrated inFIG.5A. The current IELflowing to the light-emitting element61is extremely large in a defective pixel causing a bright spot, as compared with pixels displaying normally. The current IELin a defective pixel causing a dark spot is extremely small as compared with pixels displaying normally.

The CPU21periodically obtains data of monitor current IMONIthat flows through the transistor52C. The amount of monitor current IMONIis converted into digital data that can be processed in the CPU21and arithmetic processing is performed with the digital data in the CPU21or the GPU22. A defective pixel is estimated by the arithmetic processing in the CPU21or the GPU22, and correction is performed so that a display defect due to the defective pixel is less likely to be seen. For example, in the case where a pixel230D illustrated inFIG.17Bis a defective pixel, the current IELthat flows to an adjacent pixel230N is corrected.

For example, the correction can estimated by executing an arithmetic operation based on an artificial neural network such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), or a deep belief network (DBN).

By the above correction, the current IELflowing to an adjacent pixel230N is corrected to a current IEL_C, whereby a defective pixel230D and the pixel230N are combined to a pixel230C for displaying (seeFIG.17C). By performing display as the pixel230C, defective display such as a bright spot or a dark spot due to a defective pixel is made difficult to recognize, and can be close to a normal image.

Note that in the semiconductor device of one embodiment of the present invention, data that is being processed arithmetically can be held in the storage unit11in the above arithmetic processing. The semiconductor device of one embodiment of the present invention is particularly effective, because the display portion31, the functional circuit90, and the storage unit11are provided proximately to each other and high-speed operation can be achieved in arithmetic processing of numerous amount of arithmetic operations based on artificial neural network.

The structures described in this embodiment can be used in an appropriate combination with any of the structures described in the other embodiments and the like.

In this embodiment, cross-sectional structure examples of a semiconductor device of one embodiment of the present invention will be described.

FIG.18is a cross-sectional view illustrating a structural example of the semiconductor device100A and illustrates part of the semiconductor device100A. As described above, the semiconductor device100A includes the layer10, the layer20, the layer30, the layer60, and the sealing substrate40.

The layer10includes a substrate701, and a transistor431is provided over the substrate701. The transistor431is a transistor included in the memory cell12, for example.

As the substrate701, a single crystal semiconductor substrate such as a single crystal silicon substrate can be used, for example. Note that a semiconductor substrate other than a single crystal semiconductor substrate may be used as the substrate701.

The transistor431includes a conductor443having a function as a gate electrode, an insulator445having a function as a gate insulator, and part of the substrate701. The part of the substrate701functions as a region (a semiconductor region447) including a channel formation region, a source region (one of a low-resistance region449aand a low-resistance region449b), and a drain region (the other of the low-resistance region449aand the low-resistance region449b) of the transistor431. Note that the transistor431may be a p-channel transistor or an n-channel transistor.

In the case where a single crystal silicon substrate is used as the substrate701, the transistor431is a transistor including silicon in a channel formation region (also referred to as a “Si transistor”).

The transistor431is electrically isolated from other transistors by an element isolation layer403.FIG.18illustrates the case where the transistor431is electrically isolated from other transistors by the element isolation layer403. The element isolation layer403can be formed by a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

Here, in the transistor431, the semiconductor region447has a projecting shape. Moreover, the conductor443is provided to cover the side surface and the top surface of the semiconductor region447with the insulator445placed therebetween. Note thatFIG.18does not illustrate the state where the conductor443covers the side surface of the semiconductor region447. A material adjusting the work function can be used for the conductor443.

A transistor having a projecting semiconductor region, like the transistor431, can be referred to as a fin-type transistor because the projecting portion of a semiconductor substrate is utilized. An insulator having a function of a mask for forming the projecting portion may be provided in contact with an upper portion of the projecting portion. AlthoughFIG.18illustrates the structure in which the projecting portion is formed by processing part of the substrate701, a semiconductor having a projecting shape may be formed by processing an SOI substrate.

Note that the structure of the transistor431illustrated inFIG.18is an example; the structure of the transistor431is not limited thereto and can be changed as appropriate in accordance with the circuit configuration, an operation method for the circuit, or the like. For example, the transistor431may be a planar transistor.

An insulator405, an insulator407, an insulator409, and an insulator411are provided over the substrate701, in addition to the element isolation layer403and the transistor431. A conductor451is embedded in the insulator405, the insulator407, the insulator409, and the insulator411. Here, the top surface of the conductor451and the top surface of the insulator411can be substantially level with each other.

An insulator421and an insulator422are provided over the conductor451and the insulator411. A conductor453is embedded in the insulator421and the insulator422. Here, the top surface of the conductor453and the top surface of the insulator422can be substantially level with each other.

An insulator423is provided over the conductor453and the insulator422. A conductor455is embedded in the insulator423. Here, the top surface of the conductor455and the top surface of the insulator423can be substantially level with each other.

Note that the layer10may be a multilayer wiring layer in which an insulator, a conductor, and the like are stacked, as necessary, for example.

The layer20includes a substrate702, and a transistor441and a transistor442are provided over the substrate702. The transistor441is, for example, a transistor included in the display portion driver circuit23. The transistor442is, for example, a transistor included in the storage unit driver circuit24.

A single crystal semiconductor substrate such as a single crystal silicon substrate can be used as the substrate702, like the substrate701. Note that a semiconductor substrate other than a single crystal semiconductor substrate may be used as the substrate702. The layer20can have a structure similar to that of the layer10. Thus, detailed description of the layer20is omitted here.

InFIG.18, the transistor442in the layer20is electrically connected to the transistor431in the layer10through the conductor456. The conductor456functions as a TSV. Note that the layer10and the layer20may be electrically connected to each other through a bump or the like.

The layer20includes a conductor760. The conductor760is a conductor included in the terminal portion29.FIG.18illustrates an example in which the conductor760is electrically connected to an FPC716(Flexible Printed Circuit) with an anisotropic conductor780placed therebetween. A variety of signals or the like are supplied to the semiconductor device100A through the FPC716.

The conductor760is electrically connected to a conductor347included in the layer20through a conductor353, a conductor355, and a conductor357. AlthoughFIG.18illustrates three conductors, which are the conductor353, the conductor355, and the conductor357, as conductors electrically connecting the conductor760and the conductor347, one embodiment of the present invention is not limited thereto. The number of the conductors electrically connecting the conductor760to the conductor347may be one, two, four or more. Providing a plurality of conductors electrically connecting the conductor760and the conductor347can reduce the contact resistance.

The layer30is provided over the layer20. The layer30includes the insulator214and a transistor750is provided over the insulator214. The transistor750is, for example, a transistor in the pixel circuit51. An OS transistor can be suitably used as the transistor750. The OS transistor has a feature of extremely low off-state current. Consequently, the retention time for image data or the like can be increased, so that the frequency of the refresh operation can be reduced. Thus, the power consumption of the semiconductor device100A can be reduced.

A conductor301(a conductor301aand a conductor301b) is embedded in the insulator254, the insulator280, the insulator274, and the insulator281. The conductor301ais electrically connected to one of a source and a drain of the transistor750, and the conductor301bis electrically connected to the other of the source and the drain of the transistor750. Here, the top surfaces of the conductor301aand the conductor301band the top surface of the insulator281can be substantially level with each other.

A conductor311, a conductor313, a conductor331, a capacitor790, a conductor333, and a conductor335are embedded in the insulator361. The conductor311and the conductor313are electrically connected to the transistor750and have a function of a wiring. The conductor333and the conductor335are electrically connected to the capacitor790. Here, the top surfaces of the conductor331, the conductor333, and the conductor335and the top surface of the insulator361can be substantially level with each other.

A conductor341, a conductor343, and a conductor351are embedded in the insulator363. Here, the top surface of the conductor351and the top surface of the insulator363can be substantially level with each other.

The insulator405, the insulator407, the insulator409, the insulator411, the insulator421, the insulator422, the insulator423, the insulator214, the insulator280, the insulator274, the insulator281, the insulator361, and the insulator363each have a function of an interlayer film and may also have a function of a planarization film that covers unevenness thereunder. For example, the top surface of the insulator363may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to have the increased planarity.

As illustrated inFIG.18, the capacitor790includes a lower electrode321and an upper electrode325. An insulator323is provided between the lower electrode321and the upper electrode325. In other words, the capacitor790has a stacked-layer structure in which the insulator323functioning as a dielectric is provided between the pair of electrodes. AlthoughFIG.18illustrates the example in which the capacitor790is provided over the insulator281, the capacitor790may be provided over an insulator different from the insulator281.

In the example illustrated inFIG.18, the conductor301aand the conductor301bare formed in the same layer. In the illustrated example, the conductor311, the conductor313, and the lower electrode321are formed in the same layer. In the illustrated example, the conductor331, the conductor333, and the conductor335are formed in the same layer. In the illustrated example, the conductor341and the conductor343are formed in the same layer. In the illustrated example, the conductor353, the conductor355, and the conductor357are formed in the same layer. Forming a plurality of conductors in the same layer simplifies the manufacturing process of the semiconductor device100A and can reduce the manufacturing cost of the semiconductor device100A. Note that these conductors may be formed in different layers or may contain different types of materials.

The layer60is provided over the layer30. The layer60includes the light-emitting element61. The light-emitting element61includes the conductor772, the EL layer786, and the conductor788. The EL layer786contains an organic compound or an inorganic compound such as quantum dots.

Examples of materials that can be used as an organic compound include a fluorescent material and a phosphorescent material. Examples of materials that can be used as quantum dots include a colloidal quantum dot material, an alloyed quantum dot material, a core-shell quantum dot material, and a core quantum dot material.

The conductor772is electrically connected to the other of the source and the drain of the transistor750through the conductor351, the conductor341, the conductor331, the conductor313, and the conductor301b. The conductor772is formed over the insulator363and has a function of a pixel electrode.

A material that transmits visible light or a material that reflects visible light can be used for the conductor772. As a light-transmitting material, for example, an oxide material containing indium and zinc; an oxide material containing indium, gallium, and zinc (also referred to as “IGZO”); an oxide material containing indium and tin (also referred to as “ITO”); an oxide material containing indium, tin, and silicon (also referred to as “ITSO”), or the like may be used. As a reflective material, for example, a material containing aluminum, silver, or the like may be used.

For example, in the case where light emitted from the light-emitting element61is emitted from the conductor788side, the conductor772preferably includes a reflective material. For example, the conductor772may have a single-layer structure or a stacked-layer structure of a plurality of layers. For example, in the case where the conductor772is used as an anode, a three-layer structure in which silver is sandwiched between two layers of ITO may be provided.

In the case where silicon nitride is included in a formation surface to be in contact with the conductor772, the conductor772may have a three-layer structure in which aluminum, titanium oxide, and ITO (or ITSO) are stacked in this order over the formation surface. Alternatively, in the case where silicon nitride is included in a formation surface to be in contact with the conductor772, the conductor772may have a two-layer structure in which aluminum and IGZO are stacked in this order over the formation surface.

Note that the conductor301, the conductor331, the conductor351, the conductor353, the conductor355, the conductor357, the conductor453, the conductor456, the conductor760, and the like may have the same structure as a conductor245described in another embodiment. For example, the conductor351electrically connected to the light-emitting element61may be a conductor containing tungsten and titanium nitride. Specifically, a structure in which a side surface of the insulator363is adjacent to tungsten with titanium nitride placed therebetween may be employed.

Although not illustrated inFIG.18, an optical member (optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member can be provided in the semiconductor device100A, for example.

In the semiconductor device100A illustrated inFIG.18, the light-emitting element61can be a light-emitting element having a top-emission structure in which a reflective material is used for the conductor772, a light-transmitting material is used for the conductor788, and thereby light is emitted to the conductor788side. Note that the light-emitting element61may have a bottom-emission structure in which light is emitted to the conductor772side or a dual-emission structure in which light is emitted towards both the conductor772and the conductor788. In addition, a structure body778is provided.

The sealing substrate40is provided above the layer30to cover the display portion31and the layer60. The sealing substrate40is bonded to the layer30with the sealing material712(also referred to as a “sealant”). In the case where the light-emitting element61has a top-emission structure or a dual emission structure, a light-transmitting material is used for the sealing substrate40.

Providing the sealing substrate40can prevent entry of impurities into the layer60, and thus, the reliability of the semiconductor device100A can be increased.

The light-blocking layer738is provided on the layer60side. The light-blocking layer738has a function of blocking light emitted from adjacent regions. In addition, the light-blocking layer738has a function of preventing external light from reaching the transistor750or the like.

The light-blocking layer738is covered with the insulator734. The insulator734is provided as needed. Although a solid sealing structure in which a filler layer732is provided between the light-emitting element61and the insulator734in this embodiment, a hollow sealing structure in which the filler layer732is not provided may be employed. In the case where the semiconductor device100A has a hollow sealing structure, a portion corresponding to the filler layer732may be filled with an impurity gas containing a Group 18 element (a rare gas (noble gas)) and/or nitrogen. In the case where light emitted from the light-emitting element61is emitted toward the sealing substrate40side, a material having a light-transmitting property is preferably used for the filler layer732.

Note that a transistor including any of various semiconductors can be used as the transistor included in the semiconductor device of one embodiment of the present invention. For example, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used. Furthermore, a compound semiconductor (e.g., SiGe or GaAs) or an oxide semiconductor can be used, as well as a single-element semiconductor including mainly a single element.

Note that as the transistor included in the semiconductor device of one embodiment of the present invention, a transistor with any of a variety of structures can be used. For example, a transistor having any of a variety of structures such as a planar type, a FIN-type, a TRI-GATE type, a top-gate type, a bottom-gate type, and a double-gate type (with gates placed above and below a channel) can be used. A MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor of one embodiment of the present invention.

Variation Example 1

FIG.19illustrates a variation example of the semiconductor device100A illustrated inFIG.18. The semiconductor device100A illustrated inFIG.19is different from the semiconductor device100A illustrated inFIG.18in that a coloring layer736is provided. Note that the coloring layer736is provided to have a region overlapping with the light-emitting element61. Providing the coloring layer736can improve the color purity of light extracted from the light-emitting element61. Thus, the semiconductor device100A can display high-quality images. Furthermore, all the light-emitting elements61, for example, in the semiconductor device100A can be light-emitting elements that emit white light; hence, the EL layers786are not necessarily formed so as to correspond to each color, leading to higher definition of the semiconductor device100A.

The light-emitting element61can have a micro optical resonator (microcavity) structure. Thus, light of predetermined colors (e.g., RGB) can be extracted without a coloring layer, and the semiconductor device100A can perform color display. The structure without a coloring layer can prevent light absorption by the coloring layer. As a result, the semiconductor device100A can display high-luminance images, and power consumption of the semiconductor device100A can be reduced. A structure in which a coloring layer is not provided can be employed even when the EL layer786is formed into an island shape for each pixel or into a stripe shape for each pixel column, i.e., the EL layers786are formed separately so as to correspond to each color. Note that the luminance of the semiconductor device100A can be, for example, higher than or equal to 500 cd/m2and lower than or equal to 20000 cd/m2, preferably higher than or equal to 1000 cd/m2and lower than or equal to 20000 cd/m2, further preferably higher than or equal to 5000 cd/m2and lower than or equal to 20000 cd/m2.

FIG.20illustrates a cross-sectional structure example of the semiconductor device100C, which is a variation example of the semiconductor device100A. In the cross-sectional structure example of the semiconductor device100C illustrated inFIG.20, a conductor348is provided over the insulator361included in the layer30instead of the conductor347.

The conductor348is electrically connected to the conductor760through the conductor353, the conductor355, and the conductor357. The conductor348functions like the conductor347.

Variation Example 1

FIG.21illustrates a cross-sectional structure example in which the layer30overlaps with the layer10with the layer20placed therebetween.FIG.21illustrates a variation example of the semiconductor device100C. InFIG.21, the layer20is provided over and overlap with the layer10so that the transistor included in the layer20and the transistor included in the layer10can face each other. The layer30is provided on the substrate702side in the layer20.

The conductor included in the layer10and the conductor included in the layer20can be electrically connected to each other by Cu—Cu bonding, for example. InFIG.21, for example, the conductor455included in the layer10and the conductor465included in the layer20are electrically connected to each other by Cu—Cu bonding. In that case, the conductor455and the conductor465are formed using conductors containing Cu (copper). Preferably, the insulator423in which the conductor455is embedded and the insulator424in which the conductor465is embedded are both insulators containing the same element. For example, the insulator423and the insulator424may be silicon oxide or silicon oxynitride. When the insulator423and the insulator424are insulators containing the same element, the bonding strength of the layer10and the layer20increases. Before the layer10and the layer20are bonded to each other, the planarity of surfaces of the layers is preferably improved by performing CMP treatment on the surfaces to be bonded of the layers.

Note that the bonding position between the conductor455and the conductor465completely matches with each other or not, depending on the positional alignment in bonding. The case where the conductor455and the conductor465does not completely match with each other is illustrated inFIG.21.

InFIG.21, the conductor included in the layer20and the conductor included in the layer30may be electrically connected to each other through a TSV. For example, the conductor461and the conductor462included in the layer20are both TSVs that penetrate through the substrate702.

Variation Example 2

FIG.22illustrates a variation example of the semiconductor device100C. In the cross-sectional structure example inFIG.22, the transistors included in the layer30are Si transistors. InFIG.22, the layer30includes a substrate703, and the transistor750is provided over the substrate703. The substrate703is, for example, a single crystal silicon substrate. Accordingly, the transistor750illustrated inFIG.22includes single crystal silicon in a semiconductor layer where a channel is formed. Note that a substrate similar to the substrate701and the substrate702can be used as the substrate703. The layer30in the semiconductor device100C illustrated inFIG.22includes, in addition to components similar to those of the layer20, the insulator361, the insulator363, the conductor348, the capacitor790, and the like.

Also in the semiconductor device100A, the semiconductor device100B, the semiconductor device100D to the semiconductor device100G, transistors (e.g., a Si transistor) other than OS transistors may be used for the transistors included in the layer30. As the transistors included in the layer10, the layer20, and the layer30, any of various transistors can be used depending on the purpose or usage.

Variation Example 3

As illustrated inFIG.23, a bump454and an adhesive layer457may be provided between the layer10and the layer20. The layer10and the layer20are fixed by the adhesive layer457and electrically connected to each other by the bump454. InFIG.23, the conductor456and the conductor455are electrically connected to each other through the bump454. Similarly, a bump458and an adhesive layer459may be provided between the layer20and the layer30. The layer20and the layer30are fixed to each other with the adhesive layer459and electrically connected to each other by the bump458. Note that the number of the bumps454electrically connecting the layer10and the layer20to each other is not limited to one, and may be more than one. The number of the bumps458electrically connecting the layer20and the layer30to each other is not limited to one, and may be more than one.

FIG.24illustrates a cross-sectional structure example of the semiconductor device100H, which is a variation example of the semiconductor device100C.FIG.24corresponds to a cross-sectional structure in which the layer10is removed from the cross-sectional structure example of the semiconductor device100C illustrated inFIG.20. Since the semiconductor device100H does not include the layer10, a component such as the conductor456for electrically connecting the layer10and the layer20, does not need to be provided.

Variation Example 1

FIG.25illustrates a variation example of the semiconductor device100H. In the cross-sectional structure example inFIG.25, the transistors included in the layer30are Si transistors. The layer30inFIG.25can have a structure similar to that of the layer30illustrated inFIG.22.

Variation Example 2

In the case of the structure illustrated inFIG.25, the bump458and the adhesive layer459may be provided between the layer20and the layer30as illustrated inFIG.26. The layer20and the layer30are fixed to each other with the adhesive layer459, and electrically connected to each other by the bump458. The number of the bumps458electrically connecting the layer20and the layer30to each other is not limited to one, and may be more than one as in the structure example illustrated inFIG.23.

Variation Example 3

In the case where the transistor included in the layer30is a Si transistor, the layer30may be provided over and overlap with the layer20so that the transistor included in the layer30the transistor included in the layer20can face each other (seeFIG.27). In the layer30illustrated inFIG.27, the insulator361and the insulator363are provided over the substrate703. The conductor348is provided over the insulator361. In addition, the conductor341and the conductor351are embedded in the insulator363.

The conductor included in the layer20and the conductor included in the layer30can be electrically connected to each other by Cu—Cu bonding, for example. InFIG.27, for example, the conductor465included in the layer20and the conductor475included in the layer30are electrically connected to each other by Cu—Cu bonding. In that case, the conductor465and the conductor475are formed using conductors containing Cu (copper). Preferably, the insulator424in which the conductor465is embedded and the insulator425in which the conductor475is embedded are both insulators containing the same element. For example, the insulator424and the insulator425may be silicon oxide or silicon oxynitride. When the insulator424and the insulator425are insulators containing the same element, the bonding strength of the layer20and the layer30is increased. Before the layer20and the layer30are bonded to each other, the planarity of surfaces of the layers is preferably improved by performing CMP treatment on the surfaces to be bonded of the layers.

Note that the bonding position between the conductor465and the conductor475completely matches with each other or not, depending on the positional alignment in bonding. The case where the conductor465and the conductor475does not completely match with each other is illustrated inFIG.27.

InFIG.27, a TSV may be provided for the layer30. The conductor471and the conductor472inFIG.27are both TSVs that penetrate through the substrate703. InFIG.27, the conductor471is electrically connected to the conductor341. The conductor472is electrically connected to the conductor348.

FIG.28illustrates a cross-sectional structure example of the semiconductor device100I. The semiconductor device100I illustrated inFIG.28is a variation example of the semiconductor device100H illustrated inFIG.25. Accordingly,FIG.28illustrates a cross-sectional structure example of the case where Si transistors are used for the transistors included in the layer30.

As described in the above embodiment, the semiconductor device100I includes the display portion driver circuit23and the pixel circuit51in the layer30. The transistor750inFIG.28is a transistor included in the pixel circuit51, for example. The transistor751inFIG.28is, for example, a transistor included in the display portion driver circuit23.

A functional circuit necessary for the layer30may be formed depending on the purpose and/or the usage. An unnecessary functional circuit is not provided depending on the purpose and/or the usage, whereby power consumption and manufacturing cost of the semiconductor device can be reduced. Furthermore, the thickness of the semiconductor device can be reduced, and thus the weight of the semiconductor device can be reduced.

The structures described in this embodiment can be used in an appropriate combination with any of the structures described in the other embodiments and the like.

In this embodiment, the light-emitting element61(also referred to as “light-emitting device”) is described.

As illustrated inFIG.29A, the light-emitting element61includes the EL layer786between a pair of electrodes (the conductor772and the conductor788). The EL layer786can be formed of a plurality of layers such as a layer4420, a light-emitting layer4411, and a layer4430. The layer4420can include, for example, a layer containing a substance with a high electron-injection property (an electron-injection layer) and a layer containing a substance with a high electron-transport property (an electron-transport layer). The light-emitting layer4411contains a light-emitting compound, for example. The layer4430can include, for example, a layer containing a substance with a high hole-injection property (a hole-injection layer) and a layer containing a substance with a high hole-transport property (a hole-transport layer).

The structure including the layer4420, the light-emitting layer4411, and the layer4430, which is provided between the pair of electrodes, can serve as a single light-emitting unit, and the structure inFIG.29Ais referred to as a single structure in this specification and the like.

FIG.29Billustrates a variation example of the EL layer786included in the light-emitting element61illustrated inFIG.29A. Specifically, the light-emitting element61illustrated inFIG.29Bincludes a layer4430-1over the conductor772, a layer4430-2over the layer4430-1, the light-emitting layer4411over the layer4430-2, a layer4420-1over the light-emitting layer4411, a layer4420-2over the layer4420-1, and the conductor788over the layer4420-2. For example, when the conductor772functions as an anode and the conductor788functions as a cathode, the layer4430-1functions as a hole-injection layer, the layer4430-2functions as a hole-transport layer, the layer4420-1functions as an electron-transport layer, and the layer4420-2functions as an electron-injection layer. Alternatively, when the conductor772functions as a cathode and the conductor788functions as an anode, the layer4430-1functions as an electron-injection layer, the layer4430-2functions as an electron-transport layer, the layer4420-1functions as a hole-transport layer, and the layer4420-2functions as a hole-injection layer. With such a layer structure, carriers can be efficiently injected to the light-emitting layer4411, and the efficiency of the recombination of carriers in the light-emitting layer4411can be enhanced.

Note that the structure in which a plurality of light-emitting layers (the light-emitting layer4411, a light-emitting layer4412, and a light-emitting layer4413) are provided between the layer4420and the layer4430as illustrated inFIG.29Cis also an example of the single structure.

The structure in which a plurality of light-emitting units (an EL layer786aand an EL layer786b) are connected in series with an intermediate layer (charge-generation layer)4440placed therebetween as illustrated inFIG.29Dis referred to as a tandem structure or a stack structure in this specification and the like. The tandem structure enables a light-emitting element capable of high luminance light emission.

In the case where the light-emitting element61has the tandem structure illustrated inFIG.29D, the EL layer786aand the EL layer786bmay emit light of the same color. For example, emission colors of both the EL layer786aand the EL layer786bmay be green. Note that when the display portion31includes three subpixels of R, G, and B and the subpixels each include a light-emitting element, the light-emitting element of each subpixel may have a tandem structure. Specifically, the EL layer786aand the EL layer786bin the subpixel of R each contain a material capable of emitting red light, the EL layer786aand the EL layer786bin the subpixel of G each contain a material capable of emitting green light, and the EL layer786aand the EL layer786bin the subpixel of B each contain a material capable of emitting blue light. In other words, the light-emitting layer4411and the light-emitting layer4412may contain the same material. When the emission colors of the EL layer786aand the EL layer786bare the same color, the current density per unit emission luminance can be reduced. Thus, the reliability of the light-emitting element61can be increased.

The emission color of the light-emitting element can be red, green, blue, cyan, magenta, yellow, white, or the like depending on the material that constitutes the EL layer786. Furthermore, the color purity can be further increased when the light-emitting element has a microcavity structure.

The light-emitting layer may contain two or more light-emitting substances that emit light of red (R), green (G), blue (B), yellow (Y), orange (O), or the like. The light-emitting element that emits white light (also referred to as “white light-emitting device”) preferably contains two or more kinds of light-emitting substances in the light-emitting layer. To obtain white light emission, two or more kinds of light-emitting substances are selected such that their emission colors are complementary. For example, when the emission color of a first light-emitting layer and the emission color of a second light-emitting layer have a relationship of complementary colors, it is possible to obtain the light-emitting element which emits white light as a whole. This can apply to a light-emitting element including three or more light-emitting layers.

The light-emitting layer preferably contains two or more light-emitting substances that emit light of red (R), green (G), blue (B), yellow (Y), orange (O), or the like. Alternatively, the light-emitting layer preferably contains two or more light-emitting substances that each emit light containing two or more of spectral components of R, G, and B.

A method for forming the light-emitting element61is described below.

FIG.30Aillustrates a schematic top view of the light-emitting element61. The light-emitting element61includes a plurality of light-emitting elements61R exhibiting red, a plurality of light-emitting elements61G exhibiting green, and a plurality of light-emitting elements61B exhibiting blue. InFIG.30A, light-emitting regions of the light-emitting elements are denoted by R, G, and B to easily differentiate the light-emitting elements. Note that the structure of the light-emitting element61illustrated inFIG.30Amay be referred to as an SBS (Side By Side) structure. Although the structure illustrated inFIG.30Ahas three colors of red (R), green (G), and blue (B), one embodiment of the present invention is not limited thereto. For example, the structure may have four or more colors.

The light-emitting elements61R, the light-emitting elements61G, and the light-emitting elements61B are arranged in a matrix.FIG.30Aillustrates what is called a stripe arrangement, in which the light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited thereto; another arrangement method such as a delta arrangement, a zigzag arrangement, or a PenTile arrangement may also be used.

As the light-emitting element61R, the light-emitting element61G, and the light-emitting element61B, an organic EL device such as an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode) is preferably used. As a light-emitting substance contained in the EL element, a substance that emits fluorescence (a fluorescent material), a substance that emits phosphorescence (a phosphorescent material), an inorganic compound (e.g., a quantum dot material), a substance that exhibits thermally activated delayed fluorescence (a thermally activated delayed fluorescent (TADF) material), and the like can be given.

FIG.30Bis a schematic cross-sectional view taken along dashed-dotted line A1-A2inFIG.30A.FIG.30Billustrates a cross section of the light-emitting element61R, the light-emitting element61G, and the light-emitting element61B. The light-emitting element61R, the light-emitting element61G, and the light-emitting element61B are each provided over an insulating layer251and include a conductor772functioning as a pixel electrode and a conductor788functioning as a common electrode. For the insulating layer251, one or both of an inorganic insulating film and an organic insulating film can be used. An inorganic insulating film is preferably used as the insulating layer251. As the inorganic insulating film, for example, an oxide insulating film and a nitride insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, or a hafnium oxide film can be given.

The light-emitting element61R includes an EL layer786R between the conductor772functioning as a pixel electrode and the conductor788functioning as a common electrode. The EL layer786R contains at least a light-emitting organic compound that emits light with an intensity in a red wavelength range. An EL layer786G included in the light-emitting element61G contains at least a light-emitting organic compound that emits light with an intensity in a green wavelength range. An EL layer786B included in the light-emitting element61B contains at least a light-emitting organic compound that emits light with an intensity in a blue wavelength range.

The EL layer786R, the EL layer786G, and the EL layer786B may each include one or more of an electron-injection layer, an electron-transport layer, a hole-injection layer, and a hole-transport layer in addition to the layer containing a light-emitting organic compound (the light-emitting layer).

The conductor772functioning as a pixel electrode is provided in each of the light-emitting elements. The conductor788functioning as a common electrode is provided as a continuous layer shared by the light-emitting elements. A conductive film that transmits visible light is used for either the conductor772functioning as a pixel electrode or the conductor788functioning as a common electrode, and a reflective conductive film is used for the other. When the conductor772functioning as a pixel electrode has a light-transmitting property and the conductor788functioning as a common electrode has a reflective property, a bottom-emission display apparatus can be obtained, whereas when the conductor772functioning as a pixel electrode has a reflective property and the conductor788functioning as a common electrode has a light-transmitting property, a top-emission display apparatus can be obtained. Note that when both the conductor772functioning as a pixel electrode and the conductor788functioning as a common electrode have a light-transmitting property, a dual-emission display apparatus can be obtained.

An insulating layer272is provided to cover end portions of the conductor772functioning as a pixel electrode. End portions of the insulating layer272are preferably tapered. For the insulating layer272, a material similar to the material that can be used for the insulating layer251can be used.

The EL layer786R, the EL layer786G, and the EL layer786B each include a region in contact with a top surface of the conductor772functioning as a pixel electrode and a region in contact with a surface of the insulating layer272. End portions of the EL layer786R, the EL layer786G, and the EL layer786B are positioned over the insulating layer272.

As illustrated inFIG.30B, there is a gap between the EL layers of two light-emitting elements for different colors. In this manner, the EL layer786R, the EL layer786G, and the EL layer786B are preferably provided so as not to be in contact with each other. This suitably prevents unintentional light emission (also referred to as crosstalk) from being caused by a current flowing through two adjacent EL layers. As a result, the contrast can be increased to achieve a display apparatus with high display quality.

The EL layer786R, the EL layer786G, and the EL layer786B can be formed separately by a vacuum evaporation method or the like using a shadow mask such as a metal mask. Alternatively, these layers may be formed separately by a photolithography method. The use of the photolithography method achieves a display apparatus with high resolution, which is difficult to obtain in the case of using a metal mask.

In this specification and the like, a device formed using a metal mask or an FMM (fine metal mask, high-resolution metal mask) is sometimes referred to as a device having an MM (metal mask) structure. In this specification and the like, a device formed without using a metal mask or an FMM is sometimes referred to as a device having an MML (metal maskless) structure.

A protective layer271is provided over the conductor788functioning as a common electrode so as to cover the light-emitting element61R, the light-emitting element61G, and the light-emitting element61B. The protective layer271has a function of preventing diffusion of impurities such as water into the light-emitting elements from above.

The protective layer271can have, for example, a single-layer structure or a stacked-layer structure at least including an inorganic insulating film. As the inorganic insulating film, for example, an oxide film or a nitride film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, or a hafnium oxide film can be given. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide (IGZO) may be used for the protective layer271. Note that the protective layer271may be formed by an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or a sputtering method. Although the protective layer271includes an inorganic insulating film in this example, one embodiment of the present invention is not limited thereto. For example, the protective layer271may have a stacked-layer structure of an inorganic insulating film and an organic insulating film.

Note that in this specification, a nitride oxide refers to a compound that contains more nitrogen than oxygen. An oxynitride refers to a compound that contains more oxygen than nitrogen. The content of each element can be measured by Rutherford backscattering spectrometry (RBS), for example.

In the case where an indium gallium zinc oxide is used for the protective layer271, the indium gallium zinc oxide can be processed by a wet etching method or a dry etching method. For example, in the case where IGZO is used as the protective layer271, a chemical solution of oxalic acid, phosphoric acid, a mixed chemical solution (e.g., a mixed chemical solution of phosphoric acid, acetic acid, nitric acid, and water, which is also referred to as a mixed acid aluminum etchant), or the like can be used. Note that the volume ratio of phosphoric acid, acetic acid, nitric acid, and water mixed in the mixed acid aluminum etchant can be 53.3:6.7:3.3:36.7 or in the neighborhood thereof.

FIG.30Cillustrates an example different from the above. Specifically, inFIG.30C, light-emitting elements61W that emit white light are provided. The light-emitting elements61W each include an EL layer786W that emits white light between the conductor772functioning as a pixel electrode and the conductor788functioning as a common electrode.

The EL layer786W can have, for example, a structure in which two or more light-emitting layers that are selected so as to emit light of complementary colors are stacked. It is also possible to use a stacked EL layer in which a charge-generation layer is provided between light-emitting layers.

FIG.30Cillustrates three light-emitting elements61W arranged side by side. A coloring layer264R is provided above the left light-emitting element61W. The coloring layer264R functions as a band path filter that transmits red light. Similarly, a coloring layer264G that transmits green light is provided above the middle light-emitting element61W, and a coloring layer264B that transmits blue light is provided above the right light-emitting element61W. Thus, the display apparatus can display an image with colors.

Here, the EL layer786W and the conductor788functioning as a common electrode are each separated between adjacent two light-emitting elements61W. This can prevent unintentional light emission from being caused by a current flowing through the EL layers786W of adjacent two light-emitting elements61W. Particularly when stacked EL layers in which a charge-generation layer is provided between two light-emitting layers are used as the EL layer786W, crosstalk is more significant as the resolution increases, i.e., as the distance between adjacent pixels decreases, leading to lower contrast. Thus, the above structure can achieve a display apparatus having both high resolution and high contrast.

The EL layer786W and the conductor788functioning as a common electrode are preferably isolated by a photolithography method. This can decrease the distance between light-emitting elements, achieving a display apparatus with a higher aperture ratio than that formed using, for example, a shadow mask such as a metal mask.

Note that in the case of a bottom-emission light-emitting element, a coloring layer may be provided between the conductor772functioning as a pixel electrode and the insulating layer251.

FIG.30Dillustrates an example different from the above. Specifically, inFIG.30D, the insulating layers272are not provided between the light-emitting element61R, the light-emitting element61G, and the light-emitting element61B. With such a structure, the display apparatus can have a high aperture ratio. The protective layer271covers side surfaces of the EL layer786R, the EL layer786G, and the EL layer786B. With this structure, impurities (typically, water) can be inhibited from entering the EL layer786R, the EL layer786G, and the EL layer786B through their side surfaces. In the structure illustrated inFIG.30D, the top shapes of the conductor772, the EL layer786R, and the conductor788are substantially the same. This structure can be formed in such a manner that the conductor772, the EL layer786R, and the conductor788are formed and collectively processed using a resist mask or the like. In this process, the EL layer786R and the conductor788are processed using the conductor788as a mask, and thus this process can be called self-alignment patterning. Although the EL layer786R is described here, the EL layer786G and the EL layer786B can each have a similar structure.

InFIG.30D, a protective layer273is further provided over the protective layer271. For example, the protective layer271can be formed with an apparatus that can deposit a film with excellent coverage (typically, an ALD apparatus), and the protective layer273can be formed with an apparatus that can deposit a film with coverage inferior to that of the protective layer271(typically, a sputtering apparatus), whereby a region275can be provided between the protective layer271and the protective layer273. In other words, the regions275are positioned between the EL layer786R and the EL layer786G and between the EL layer786G and the EL layer786B.

Note that the region275includes, for example, any one or more selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, and krypton). Furthermore, for example, a gas used during the deposition of the protective layer273is sometimes included in the region275. For example, in the case where the protective layer273is deposited using a sputtering method, any one or more of the above-described Group 18 elements is sometimes included in the region275. In the case where a gas is included in the region275, a gas can be identified with a gas chromatography method or the like. Alternatively, in the case where the protective layer273is deposited using a sputtering method, a gas used in the sputtering is sometimes contained in the protective layer273. In this case, an element such as argon is sometimes detected when the protective layer273is analyzed by an energy dispersive X-ray analysis (EDX analysis) or the like.

In the case where the refractive index of the region275is lower than that of the protective layer271, light emitted from the EL layer786R, the EL layer786G, or the EL layer786B is reflected at the interface between the protective layer271and the region275. Thus, light emitted from the EL layer786R, the EL layer786G, or the EL layer786B can be inhibited from entering an adjacent pixel in some cases. This can inhibit color mixture of light emitted from adjacent pixels and thus can improve the display quality of the display apparatus.

In the case of the structure illustrated inFIG.30D, a region between the light-emitting element61R and the light-emitting element61G or a region between the light-emitting element61G and the light-emitting element61B (hereinafter simply referred to as a distance between the light-emitting elements) can be small. Specifically, the distance between the light-emitting elements can be less than or equal to 1 μm, preferably less than or equal to 500 nm, further preferably less than or equal to 200 nm, less than or equal to 100 nm, less than or equal to 90 nm, less than or equal to 70 nm, less than or equal to 50 nm, less than or equal to 30 nm, less than or equal to 20 nm, less than or equal to 15 nm, or less than or equal to 10 nm. In other words, the display apparatus includes a region in which an interval between the side surface of the EL layer786R and the side surface of the EL layer786G or an interval between the side surface of the EL layer786G and the side surface of the EL layer786B is less than or equal to 1 μm, preferably less than or equal to 0.5 μm (500 nm), further preferably less than or equal to 100 nm.

In the case where the region275includes a gas, the light-emitting elements can be isolated from each other and color mixing of light or crosstalk between the light-emitting elements can be inhibited.

Alternatively, the region275may be filled with a filler. Examples of the filler include an epoxy resin, an acrylic resin, a silicone resin, a phenol resin, a polyimide resin, an imide resin, a PVC (polyvinyl chloride) resin, a PVB (polyvinyl butyral) resin, and an EVA (ethylene vinyl acetate) resin. Alternatively, a photoresist may be used as the filler. The photoresist used as the filler may be a positive photoresist or a negative photoresist.

When the white-light-emitting device (having a single structure or a tandem structure) and a light-emitting device having an SBS structure are compared to each other, the light-emitting device having an SBS structure can have lower power consumption than the white-light-emitting device. To reduce power consumption, a light-emitting device having an SBS structure is preferably used. Meanwhile, the white-light-emitting device is preferable in terms of lower manufacturing cost or higher manufacturing yield because the manufacturing process of the white-light-emitting device is simpler than that of a light-emitting device having an SBS structure.

FIG.31Aillustrates an example different from the above. Specifically, the structure illustrated inFIG.31Ais different from the structure illustrated inFIG.30Din the structure of the insulating layer251. The insulating layer251has a recessed portion in its top surface that is formed by being partially etched when the light-emitting element61R, the light-emitting element61G, and the light-emitting element61B are processed. In addition, the protective layer271is formed in the recessed portion. In other words, in the cross-sectional view, a region is provided, in which the bottom surface of the protective layer271is positioned below the bottom surface of the conductor772. With the region, impurities (typically, water or the like) can be suitably inhibited from entering the light-emitting element61R, the light-emitting element61G, and the light-emitting element61B from the bottom. It is likely that the recessed portion can be formed when impurities (also referred to as residue) that could be attached to the side surfaces of the light-emitting element61R, the light-emitting element61G, and the light-emitting element61B in processing of the light-emitting elements are removed by e.g., wet etching. After the residue is removed, the side surfaces of the light-emitting elements are covered with the protective layer271, whereby a highly reliable display apparatus can be provided.

FIG.31Billustrates an example different from the above. Specifically, the structure illustrated inFIG.31Bincludes an insulating layer276and a microlens array277in addition to the structure illustrated inFIG.31A. The insulating layer276functions as an adhesive layer. Note that when the refractive index of the insulating layer276is lower than that of the microlens array277, the microlens array277can condense light emitted from the light-emitting element61R, the light-emitting element61G, and the light-emitting element61B. This can increase the light extraction efficiency of the display apparatus. In particular, this is suitable, because a user can see bright images when the user sees the display surface from the front of the display apparatus. As the insulating layer276, a variety of curable adhesives, e.g., a photocurable adhesive such as an ultraviolet curable adhesive, a reactive curable adhesive, a thermosetting adhesive, and an anaerobic adhesive can be used. Examples of these adhesives include an epoxy resin, an acrylic resin, a silicone resin, a phenol resin, a polyimide resin, an imide resin, a PVC (polyvinyl chloride) resin, a PVB (polyvinyl butyral) resin, and an EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as an epoxy resin, is preferred. Alternatively, a two-component resin may be used. An adhesive sheet or the like may be used.

FIG.31Cillustrates an example different from the above. Specifically, the structure illustrated inFIG.31Cincludes three light-emitting elements61W instead of the light-emitting element61R, the light-emitting element61G, and the light-emitting element61B in the structure illustrated inFIG.31A. In addition, the insulating layer276is provided over the three light-emitting elements61W, and the coloring layer264R, the coloring layer264G, and the coloring layer264B are provided over the insulating layer276. Specifically, the coloring layer264R that transmits red light is provided at a position overlapping with the left light-emitting element61W, the coloring layer264G that transmits green light is provided at a position overlapping with the middle light-emitting element61W, and the coloring layer264B that transmits blue light is provided at a position overlapping with the right light-emitting element61W. Thus, the semiconductor device can display an image with colors. The structure illustrated inFIG.31Cis also a variation example of the structure illustrated inFIG.30C.

FIG.31Dillustrates an example different from the above. Specifically, in the structure illustrated inFIG.31D, the protective layer271is provided adjacent to the side surfaces of the conductor772and the EL layer786. The conductor788is provided as a continuous layer shared by the light-emitting elements. In the structure illustrated inFIG.31D, the region275is preferably filled with a filler.

Furthermore, the color purity of emitted light can be further increased when the light-emitting element61has a microcavity structure. In order that the light-emitting element61has a microcavity structure, a product (optical path length) of a distance d between the conductor772and the conductor788and a refractive index n of the EL layer786is set to m times half of a wavelength λ (m is an integer of 1 or more). The distance d can be obtained by Formula 1.

According to Formula 1, in the light-emitting element61having the microcavity structure, the distance d is determined in accordance with the wavelength (emission color) of emitted light. The distance d corresponds to the thickness of the EL layer786. Thus, the EL layer786G is provided to have a larger thickness than the EL layer786B, and the EL layer786R is provided to have a larger thickness than the EL layer786G in some cases.

To be exact, the distance d is a distance from a reflection region in the conductor772functioning as a reflective electrode to a reflection region in the conductor788functioning as a transflective electrode. For example, in the case where the conductor772is a stack of silver and ITO that is a transparent conductive film and the ITO is positioned on the EL layer786side, the distance d suitable for the emission color can be set by adjusting the thickness of the ITO. That is, even when the EL layer786R, the EL layer786G, and the EL layer786B have the same thickness, the distance d suitable for the emission color can be obtained by adjusting the thickness of the ITO.

However, it is sometimes difficult to determine the exact position of the reflection region in each of the conductor772and the conductor788. In this case, it is assumed that the effect of the microcavity structure can be fully obtained with a certain position in each of the conductor772and the conductor788being supposed as the reflection region.

The light-emitting element61includes a hole-transport layer, a hole-transport layer, a light-emitting layer, an electron-transport layer, an electron-injection layer, and the like. Note that a specific structure example of the light-emitting element61will be described in another embodiment. In order to increase the outcoupling efficiency in the microcavity structure, the optical path length from the conductor772functioning as a reflective electrode to the light-emitting layer is preferably set to an odd multiple of λ/4. In order to achieve this optical path length, the thicknesses of the layers in the light-emitting element61are preferably adjusted as appropriate.

In the case where light is emitted from the conductor788side, the reflectance of the conductor788is preferably higher than the transmittance thereof. The light transmittance of the conductor788is preferably higher than or equal to 2% and lower than or equal to 50%, further preferably higher than or equal to 2% and lower than or equal to 30%, still further preferably higher than or equal to 2% and lower than or equal to 10%. When the transmittance of the conductor788is set low (the reflectance is set high), the effect of the microcavity structure can be enhanced.

The structures described in this embodiment can be used in an appropriate combination with any of the structures described in the other embodiments and the like.

In this embodiment, transistors that can be used in the semiconductor device of one embodiment of the present invention will be described.

<Structure Example of Transistor>

FIG.32A,FIG.32B, andFIG.32Care a top view and cross-sectional views of a transistor200that can be used in the semiconductor device of one embodiment of the present invention and the periphery of the transistor200. The transistor200can be used in the semiconductor device of one embodiment of the present invention. For example, the transistor200can be used as the transistor included in the layer30.

FIG.32Ais a top view of the transistor200.FIG.32BandFIG.32Care cross-sectional views of the transistor200. Here,FIG.32Bis a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2inFIG.32Aand is a cross-sectional view of the transistor200in the channel length direction.FIG.32Cis a cross-sectional view of a portion indicated by the dashed-dotted line A3-A4inFIG.32Aand is a cross-sectional view of the transistor200in the channel width direction. Note that some components are omitted in the top view ofFIG.32Afor clarity of the drawing.

As illustrated inFIG.32, the transistor200includes a metal oxide231aplaced over a substrate (not illustrated); a metal oxide231bplaced over the metal oxide231a; a conductor242aand a conductor242bthat are placed apart from each other over the metal oxide231b; the insulator280that is placed over the conductor242aand the conductor242band has an opening between the conductor242aand the conductor242b; a conductor260placed in the opening; an insulator250placed between the conductor260and the metal oxide231b, the conductor242a, the conductor242b, and the insulator280; and a metal oxide231cplaced between the insulator250and the metal oxide231b, the conductor242a, the conductor242b, and the insulator280. Here, as illustrated inFIG.32BandFIG.32C, preferably, the top surface of the conductor260is substantially aligned with the top surfaces of the insulator250, the insulator254, the metal oxide231c, and the insulator280. Hereinafter, the metal oxide231a, the metal oxide231b, and the metal oxide231cmay be collectively referred to as a metal oxide231. The conductor242aand the conductor242bmay be collectively referred to as a conductor242.

In the transistor200illustrated inFIG.32, side surfaces of the conductor242aand the conductor242bon the conductor260side are substantially perpendicular. Note that the transistor200illustrated inFIG.32is not limited thereto, and the angle formed between the side surfaces and the bottom surfaces of the conductor242aand the conductor242bmay be greater than or equal to 10° and less than or equal to 80°, preferably greater than or equal to 30° and less than or equal to 60°. The side surfaces of the conductor242aand the conductor242bthat face each other may have a plurality of surfaces.

As illustrated inFIG.32, the insulator254is preferably placed between the insulator280and the insulator224, the metal oxide231a, the metal oxide231b, the conductor242a, the conductor242b, and the metal oxide231c. Here, as illustrated inFIG.32BandFIG.32C, the insulator254is preferably in contact with the side surface of the metal oxide231c, the top surface and the side surface of the conductor242a, the top surface and the side surface of the conductor242b, the side surfaces of the metal oxide231aand the metal oxide231b, and the top surface of the insulator224.

In the transistor200, three layers of the metal oxide231a, the metal oxide231b, and the metal oxide231care stacked in and around the region where the channel is formed (hereinafter also referred to as channel formation region); however, the present invention is not limited thereto. For example, a two-layer structure of the metal oxide231band the metal oxide231cor a stacked-layer structure of four or more layers may be employed. Although the conductor260is illustrated to have a stacked-layer structure of two layers in the transistor200, the present invention is not limited thereto. For example, the conductor260may have a single-layer structure or a stacked-layer structure of three or more layers. Furthermore, each of the metal oxide231a, the metal oxide231b, and the metal oxide231cmay have a stacked-layer structure of two or more layers.

For example, in the case where the metal oxide231chas a stacked-layer structure including a first metal oxide and a second metal oxide over the first metal oxide, the first metal oxide preferably has a composition similar to that of the metal oxide231band the second metal oxide preferably has a composition similar to that of the metal oxide231a.

Here, the conductor260functions as a gate electrode of the transistor, and the conductor242aand the conductor242beach function as a source electrode or a drain electrode. As described above, the conductor260is formed to be embedded in the opening of the insulator280and the region interposed between the conductor242aand the conductor242b. Here, the positions of the conductor260, the conductor242a, and the conductor242bare selected in a self-aligned manner with respect to the opening of the insulator280. In other words, in the transistor200, the gate electrode can be placed between the source electrode and the drain electrode in a self-aligned manner. Thus, the conductor260can be formed without an alignment margin, resulting in a reduction in the area occupied by the transistor200. Accordingly, the display apparatus can have higher resolution. In addition, the display apparatus can have a narrow bezel.

As illustrated inFIG.32, the conductor260preferably includes a conductor260aprovided on the inner side of the insulator250and a conductor260bprovided to be embedded on the inner side of the conductor260a.

The transistor200preferably includes the insulator214placed over the substrate (not illustrated); the insulator216placed over the insulator214; a conductor205placed to be embedded in the insulator216; the insulator222placed over the insulator216and the conductor205; and the insulator224placed over the insulator222. The metal oxide231ais preferably placed over the insulator224.

The insulator274and the insulator281functioning as interlayer films are preferably placed over the transistor200. Here, the insulator274is preferably placed in contact with the top surfaces of the conductor260, the insulator250, the insulator254, the metal oxide231c, and the insulator280.

The insulator222, the insulator254, and the insulator274preferably have a function of inhibiting diffusion of at least one of hydrogen (e.g., a hydrogen atom and a hydrogen molecule). For example, the insulator222, the insulator254, and the insulator274preferably have a lower hydrogen permeability than the insulator224, the insulator250, and the insulator280. Moreover, the insulator222and the insulator254preferably have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule). For example, the insulator222and the insulator254preferably have a lower oxygen permeability than the insulator224, the insulator250, and the insulator280.

Here, the insulator224, the metal oxide231, and the insulator250are separated from the insulator280and the insulator281by the insulator254and the insulator274. This can inhibit entry of impurities such as hydrogen contained in the insulator280and the insulator281and excess oxygen into the insulator224, the metal oxide231, and the insulator250.

A conductor245(a conductor245aand a conductor245b) that is electrically connected to the transistor200and functions as a plug is preferably provided. Note that an insulator241(an insulator241aand an insulator241b) is provided in contact with the side surface of the conductor245functioning as a plug. In other words, the insulator241is provided in contact with the inner wall of an opening in the insulator254, the insulator280, the insulator274, and the insulator281. In addition, a structure may be employed in which a first conductor of the conductor245is provided in contact with the side surface of the insulator241and a second conductor of the conductor245is provided on the inner side of the first conductor. Here, the top surface of the conductor245and the top surface of the insulator281can be substantially level with each other. Although the transistor200has a structure in which the first conductor of the conductor245and the second conductor of the conductor245are stacked, the present invention is not limited thereto. For example, the conductor245may have a single-layer structure or a stacked-layer structure of three or more layers. In the case where a component has a stacked-layer structure, layers may be distinguished by ordinal numbers corresponding to the formation order.

In the transistor200, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used as the metal oxide231including the channel formation region (the metal oxide231a, the metal oxide231b, and the metal oxide231c). For example, it is preferable to use a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more as the metal oxide to be the channel formation region of the metal oxide231.

The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, indium (In) and zinc (Zn) are preferably contained. In addition to them, an element M is preferably contained. As the element M, one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), and cobalt (Co) can be used. In particular, the element M is preferably one or more of aluminum (Al), gallium (Ga), yttrium (Y), and tin (Sn). Furthermore, the element M preferably contains one or both of gallium (Ga) and tin (Sn).

As illustrated inFIG.32B, the metal oxide231bin a region that does not overlap with the conductor242sometimes has a smaller thickness than the metal oxide231bin a region that overlaps with the conductor242. The thin region is formed when part of the top surface of the metal oxide231bis removed at the time of forming the conductor242aand the conductor242b. When a conductive film to be the conductor242is formed, a low-resistance region is sometimes formed on the top surface of the metal oxide231bin the vicinity of the interface with the conductive film. Removing the low-resistance region positioned between the conductor242aand the conductor242bon the top surface of the metal oxide231bin the above manner can prevent formation of the channel in the region.

According to one embodiment of the present invention, a display apparatus that includes small-size transistors and has high resolution can be provided. A display apparatus that includes a transistor with a high on-state current and has high luminance can be provided. A display apparatus that includes a transistor operating at high speed and thus operates at high speed can be provided. A display apparatus that includes a transistor having stable electrical characteristics and is highly reliable can be provided. A display apparatus that includes a transistor with a low off-state current and has low power consumption can be provided.

The structure of the transistor200that can be used in the display apparatus of one embodiment of the present invention is described in detail.

The conductor205is placed to include a region overlapping with the metal oxide231and the conductor260. Furthermore, the conductor205is preferably provided to be embedded in the insulator216.

The conductor205includes a conductor205a, a conductor205b, and a conductor205c. The conductor205ais provided in contact with the bottom surface and a side wall of the opening provided in the insulator216. The conductor205bis provided to be embedded in a recessed portion formed by the conductor205a. Here, the top surface of the conductor205bis lower in level than the top surface of the conductor205aand the top surface of the insulator216. The conductor205cis provided in contact with the top surface of the conductor205band the side surface of the conductor205a. Here, the top surface of the conductor205cis substantially level with the top surface of the conductor205aand the top surface of the insulator216. That is, the conductor205bis surrounded by the conductor205aand the conductor205c.

Here, for the conductor205aand the conductor205c, it is preferable to use a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, or the like), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule).

When the conductor205aand the conductor205care formed using a conductive material having a function of inhibiting diffusion of hydrogen, impurities such as hydrogen contained in the conductor205bcan be inhibited from diffusing into the metal oxide231through the insulator224and the like. When the conductor205aand the conductor205care formed using a conductive material having a function of inhibiting diffusion of oxygen, the conductivity of the conductor205bcan be inhibited from being lowered because of oxidation. As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. Thus, the conductor205ais a single layer or stacked layers of the above conductive materials. For example, titanium nitride is used for the conductor205a.

For the conductor205b, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used. For example, tungsten is used for the conductor205b.

The conductor260sometimes functions as a first gate (also referred to as top gate) electrode. The conductor205sometimes functions as a second gate (also referred to as bottom gate) electrode. In that case, by changing a potential applied to the conductor205not in synchronization with and independently of a potential applied to the conductor260, Vthof the transistor200can be controlled. In particular, by applying a negative potential to the conductor205, Vthof the transistor200can be higher than 0 V and the off-state current can be made low. Thus, a drain current at the time when a potential applied to the conductor260is 0 V can be lower in the case where a negative potential is applied to the conductor205than in the case where the negative potential is not applied to the conductor205.

The conductor205is preferably provided to be larger than the channel formation region in the metal oxide231. In particular, it is preferable that the conductor205extend to the outside beyond an end portion of the metal oxide231that intersects with the channel width direction, as illustrated inFIG.32C. In other words, the conductor205and the conductor260preferably overlap with each other with the insulator placed therebetween, in a region outside the side surface of the metal oxide231in the channel width direction.

With the above structure, the channel formation region of the metal oxide231can be electrically surrounded by electric fields of the conductor260having a function of the first gate electrode and electric fields of the conductor205having a function of the second gate electrode.

Furthermore, as illustrated inFIG.32C, the conductor205extends so as to function as a wiring as well. However, without limitation to this structure, a structure in which a conductor functioning as a wiring is provided below the conductor205may be employed.

The insulator214preferably functions as a barrier insulating film that inhibits the entry of impurities such as water or hydrogen to the transistor200from the substrate side. Accordingly, it is preferable to use, for the insulator214, an insulating material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, and NO2), and a copper atom (an insulating material through which the impurities are less likely to pass). Alternatively, it is preferable to use an insulating material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule) (an insulating material through which the oxygen is less likely to pass).

For example, aluminum oxide, silicon nitride, or the like is preferably used for the insulator214. Accordingly, it is possible to inhibit diffusion of impurities such as water or hydrogen to the transistor200side from the substrate side through the insulator214. Alternatively, it is possible to inhibit diffusion of oxygen contained in the insulator224and the like to the substrate side through the insulator214.

The permittivity of each of the insulator216, the insulator280, and the insulator281functioning as an interlayer film is preferably lower than that of the insulator214. When a material with a low permittivity is used for an interlayer film, the parasitic capacitance generated between wirings can be reduced. For the insulator216, the insulator280, and the insulator281, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like can be used as appropriate.

The insulator222and the insulator224have a function of a gate insulator.

Here, the insulator224in contact with the metal oxide231preferably releases oxygen by heating. In this specification, oxygen that is released by heating is referred to as excess oxygen in some cases. For example, silicon oxide, silicon oxynitride, or the like can be used as appropriate for the insulator224. When an insulator containing oxygen is provided in contact with the metal oxide231, oxygen vacancies in the metal oxide231can be reduced, leading to improved reliability of the transistor200.

Specifically, an oxide material that releases part of oxygen by heating is preferably used for the insulator224. An oxide that releases oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018atoms/cm3, preferably greater than or equal to 1.0×1019atoms/cm3, further preferably greater than or equal to 2.0×1019atoms/cm3or greater than or equal to 3.0×1020atoms/cm3in TDS (Thermal Desorption Spectroscopy) analysis. Note that the temperature of the film surface in the TDS analysis is preferably in the range of 100° C. to 700° C., both inclusive or 100° C. to 400° C., both inclusive.

As illustrated inFIG.32C, the insulator224is sometimes thinner in a region that overlaps with neither the insulator254nor the metal oxide231bthan in the other regions. In the insulator224, the region that overlaps with neither the insulator254nor the metal oxide231bpreferably has a thickness with which the above oxygen can be adequately diffused.

Like the insulator214and the like, the insulator222preferably functions as a barrier insulating film that inhibits the entry of impurities such as water or hydrogen into the transistor200from the substrate side. For example, the insulator222preferably has a lower hydrogen permeability than the insulator224. When the insulator224, the metal oxide231, the insulator250, and the like are surrounded by the insulator222, the insulator254, and the insulator274, the entry of impurities such as water or hydrogen into the transistor200from outside can be inhibited.

Furthermore, it is preferable that the insulator222have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule) (it is preferable that the oxygen be less likely to pass through the insulator222). For example, the insulator222preferably has a lower oxygen permeability than the insulator224. The insulator222preferably has a function of inhibiting diffusion of oxygen and impurities, in which case oxygen contained in the metal oxide231is less likely to diffuse to the substrate side. Moreover, the conductor205can be inhibited from reacting with oxygen contained in the insulator224and the metal oxide231.

As the insulator222, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material, is preferably used. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In the case where the insulator222is formed using such a material, the insulator222functions as a layer inhibiting release of oxygen from the metal oxide231and entry of impurities such as hydrogen into the metal oxide231from the periphery of the transistor200.

The insulator222may be a single layer or a stacked layer using an insulator containing a high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3(BST). With further miniaturization and higher integration of a transistor, a problem such as generation of leakage current may arise because of a thinned gate insulator. When a high-k material is used for the insulator functioning as a gate insulator, a gate potential at the time of operation of the transistor can be reduced while the physical thickness is maintained.

Note that the insulator222and the insulator224may each have a stacked-layer structure of two or more layers. In that case, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed. For example, an insulator similar to the insulator224may be provided below the insulator222.

The metal oxide231includes the metal oxide231a, the metal oxide231bover the metal oxide231a, and the metal oxide231cover the metal oxide231b. When the metal oxide231includes the metal oxide231aunder the metal oxide231b, it is possible to inhibit diffusion of impurities into the metal oxide231bfrom the components formed below the metal oxide231a. Moreover, when the metal oxide231includes the metal oxide231cover the metal oxide231b, it is possible to inhibit diffusion of impurities into the metal oxide231bfrom the components formed above the metal oxide231c.

Note that the metal oxide231preferably has a stacked-layer structure of a plurality of oxide layers that differ in the atomic ratio of metal atoms. For example, in the case where the metal oxide231contains at least indium (In) and the element M, the proportion of the number of atoms of the element M contained in the metal oxide231ato the number of atoms of all elements that constitute the metal oxide231ais preferably higher than the proportion of the number of atoms of the element M contained in the metal oxide231bto the number of atoms of all elements that constitute the metal oxide231b. In addition, the atomic ratio of the element M to In in the metal oxide231ais preferably greater than the atomic ratio of the element M to In in the metal oxide231b. Here, a metal oxide that can be used as the metal oxide231aor the metal oxide231bcan be used as the metal oxide231c.

The energy of the conduction band minimum of each of the metal oxide231aand the metal oxide231cis preferably higher than the energy of the conduction band minimum of the metal oxide231b. In other words, the electron affinity of each of the metal oxide231aand the metal oxide231cis preferably smaller than the electron affinity of the metal oxide231b. In this case, a metal oxide that can be used as the metal oxide231ais preferably used as the metal oxide231c. Specifically, the proportion of the number of atoms of the element M contained in the metal oxide231cto the number of atoms of all elements that constitute the metal oxide231cis preferably higher than the proportion of the number of atoms of the element M contained in the metal oxide231bto the number of atoms of all elements that constitute the metal oxide231b. In addition, the atomic ratio of the element M to In in the metal oxide231cis preferably greater than the atomic ratio of the element M to In in the metal oxide231b.

Here, the energy level of the conduction band minimum gently changes at junction portions between the metal oxide231a, the metal oxide231b, and the metal oxide231c. In other words, at junction portions between the metal oxide231a, the metal oxide231b, and the metal oxide231c, the energy level of the conduction band minimum continuously changes or the energy levels are continuously connected. This can be achieved by decreasing the density of defect states in a mixed layer formed at the interface between the metal oxide231aand the metal oxide231band the interface between the metal oxide231band the metal oxide231c.

Specifically, when the metal oxide231aand the metal oxide231bor the metal oxide231band the metal oxide231ccontain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like may be used as the metal oxide231aand the metal oxide231c, in the case where the metal oxide231bis an In—Ga—Zn oxide. The metal oxide231cmay have a stacked-layer structure. For example, a stacked-layer structure of an In—Ga—Zn oxide and a Ga—Zn oxide over the In—Ga—Zn oxide or a stacked-layer structure of an In—Ga—Zn oxide and gallium oxide over the In—Ga—Zn oxide can be employed. In other words, the metal oxide231cmay have a stacked-layer structure of an In—Ga—Zn oxide and an oxide that does not contain In.

Specifically, as the metal oxide231a, a metal oxide with In: Ga:Zn=1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] can be used. As the metal oxide231b, a metal oxide with In: Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] can be used. As the metal oxide231c, a metal oxide with In: Ga:Zn=1:3:4 [atomic ratio], In: Ga:Zn=4:2:3 [atomic ratio], Ga:Zn=2:1 [atomic ratio], or Ga:Zn=2:5 [atomic ratio] can be used. Specific examples of a stacked-layer structure of the metal oxide231cinclude a stacked-layer structure of a layer with In: Ga:Zn=4:2:3 [atomic ratio] and a layer with Ga:Zn=2:1 [atomic ratio], a stacked-layer structure of a layer with In: Ga: Zn=4:2:3 [atomic ratio] and a layer with Ga:Zn=2:5 [atomic ratio], and a stacked-layer structure of a layer with In: Ga:Zn=4:2:3 [atomic ratio] and a layer of gallium oxide.

At this time, the metal oxide231bserves as a main carrier path. When the metal oxide231aand the metal oxide231chave the above structure, the density of defect states at the interface between the metal oxide231aand the metal oxide231band the interface between the metal oxide231band the metal oxide231ccan be made low. This reduces the influence of interface scattering on carrier conduction, and the transistor200can have a high on-state current and high frequency characteristics. Note that in the case where the metal oxide231chas a stacked-layer structure, not only the effect of reducing the density of defect states at the interface between the metal oxide231band the metal oxide231c, but also the effect of inhibiting diffusion of the constituent element contained in the metal oxide231cto the insulator250side can be expected. Specifically, the metal oxide231chas a stacked-layer structure in which an oxide not containing In is positioned in the upper layer of the stacked-layer structure, whereby the diffusion of In to the insulator250side can be inhibited. Since the insulator250functions as a gate insulator, the transistor has defects in characteristics when In diffuses. Thus, the metal oxide231chaving a stacked-layer structure allows a highly reliable display apparatus to be provided.

When the conductor242is provided in contact with the metal oxide231, the oxygen concentration of the metal oxide231in the vicinity of the conductor242sometimes decreases. In addition, a metal compound layer that contains the metal contained in the conductor242and the component of the metal oxide231is sometimes formed in the metal oxide231in the vicinity of the conductor242. In such cases, the carrier concentration of the region in the metal oxide231in the vicinity of the conductor242increases, and the region becomes a low-resistance region.

Here, the region between the conductor242aand the conductor242bis formed to overlap with the opening of the insulator280. Accordingly, the conductor260can be placed in a self-aligned manner between the conductor242aand the conductor242b.

The insulator250functions as a gate insulator. The insulator250is preferably placed in contact with the top surface of the metal oxide231c. For the insulator250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide can be used. In particular, silicon oxide and silicon oxynitride, which are thermally stable, are preferable.

As in the insulator224, the concentration of impurities such as water or hydrogen in the insulator250is preferably reduced. The thickness of the insulator250is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

A metal oxide may be provided between the insulator250and the conductor260. The metal oxide preferably inhibits oxygen diffusion from the insulator250into the conductor260. Accordingly, oxidation of the conductor260due to oxygen in the insulator250can be inhibited.

The metal oxide functions as part of the gate insulator in some cases. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator250, a metal oxide that is a high-k material with a high dielectric constant is preferably used as the metal oxide. When the gate insulator has a stacked-layer structure of the insulator250and the metal oxide, the stacked-layer structure can be thermally stable and have a high dielectric constant. Accordingly, a gate potential applied during operation of the transistor can be reduced while the physical thickness of the gate insulator is maintained. In addition, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced.

Specifically, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. It is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

Although the conductor260is illustrated to have a two-layer structure inFIG.32, the conductor260may have a single-layer structure or a stacked-layer structure of three or more layers.

The conductor260ais preferably formed using the aforementioned conductor having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, and NO2), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule).

When the conductor260ahas a function of inhibiting diffusion of oxygen, the conductivity of the conductor260bcan be inhibited from being lowered by oxidation due to oxygen contained in the insulator250. As a conductive material having a function of inhibiting oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

Moreover, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor260b. The conductor260also functions as a wiring and thus is preferably formed using a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used. The conductor260bmay have a stacked-layer structure, for example, a stacked-layer structure of titanium or titanium nitride and the above conductive material.

As illustrated inFIG.32AandFIG.32C, the side surface of the metal oxide231is covered with the conductor260in a region where the metal oxide231bdoes not overlap with the conductor242, that is, the channel formation region of the metal oxide231. Accordingly, electric fields of the conductor260functioning as the first gate electrode are likely to act on the side surface of the metal oxide231. Thus, the on-state current of the transistor200can be increased and the frequency characteristics can be improved.

The insulator254, like the insulator214and the like, preferably functions as a barrier insulating film that inhibits the entry of impurities such as water or hydrogen into the transistor200from the insulator280side. The insulator254preferably has a lower hydrogen permeability than the insulator224, for example. Furthermore, as illustrated inFIG.32BandFIG.32C, the insulator254is preferably in contact with the side surface of the metal oxide231c, the top and side surfaces of the conductor242a, the top and side surfaces of the conductor242b, side surfaces of the metal oxide231aand the metal oxide231b, and the top surface of the insulator224. Such a structure can inhibit the entry of hydrogen contained in the insulator280into the metal oxide231through the top surfaces or side surfaces of the conductor242a, the conductor242b, the metal oxide231a, the metal oxide231b, and the insulator224.

Furthermore, it is preferable that the insulator254have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom and an oxygen molecule) (it is preferable that the oxygen be less likely to pass through the insulator254). For example, the insulator254preferably has a lower oxygen permeability than the insulator280or the insulator224.

The insulator254is preferably formed by a sputtering method. When the insulator254is formed by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of a region of the insulator224that is in contact with the insulator254. Thus, oxygen can be supplied from the region to the metal oxide231through the insulator224. Here, with the insulator254having a function of inhibiting upward diffusion of oxygen, oxygen can be prevented from diffusing from the metal oxide231into the insulator280. Moreover, with the insulator222having a function of inhibiting downward diffusion of oxygen, oxygen diffusion from the metal oxide231to the substrate side can be prevented. In the above manner, oxygen is supplied to the channel formation region of the metal oxide231. Accordingly, oxygen vacancies in the metal oxide231can be reduced, so that the transistor can be inhibited from having normally-on characteristics.

As the insulator254, an insulator containing an oxide of one or both of aluminum and hafnium is preferably formed, for example. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.

The insulator224, the insulator250, and the metal oxide231are covered with the insulator254having a barrier property against hydrogen, whereby the insulator280is isolated from the insulator224, the metal oxide231, and the insulator250by the insulator254. This can inhibit the entry of impurities such as hydrogen from outside of the transistor200, resulting in favorable electrical characteristics and high reliability of the transistor200.

The insulator280is provided over the insulator224, the metal oxide231, and the conductor242with the insulator254placed therebetween. The insulator280preferably includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride, which are thermally stable, are preferable. In particular, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferably used, in which case a region containing oxygen to be released by heating can be easily formed.

The concentration of impurities such as water or hydrogen in the insulator280is preferably reduced. In addition, the top surface of the insulator280may be planarized.

Like the insulator214and the like, the insulator274preferably functions as a barrier insulating film that inhibits the entry of impurities such as water or hydrogen into the insulator280from the above. As the insulator274, for example, the insulator that can be used as the insulator214, the insulator254, and the like can be used.

The insulator281functioning as an interlayer film is preferably provided over the insulator274. As in the insulator224or the like, the concentration of impurities such as water or hydrogen in the insulator281is preferably reduced.

The conductor245aand the conductor245bare placed in openings formed in the insulator281, the insulator274, the insulator280, and the insulator254. The conductor245aand the conductor245bare placed to face each other with the conductor260placed therebetween. Note that the top surfaces of the conductor245aand the conductor245bmay be on the same plane as the top surface of the insulator281.

The insulator241ais provided in contact with the inner wall of the opening in the insulator281, the insulator274, the insulator280, and the insulator254, and the first conductor of the conductor245ais formed in contact with the side surface of the insulator241a. The conductor242ais positioned on at least part of the bottom portion of the opening, and the conductor245ais in contact with the conductor242a. Similarly, the insulator241bis provided in contact with the inner wall of the opening in the insulator281, the insulator274, the insulator280, and the insulator254, and the first conductor of the conductor245bis formed in contact with the side surface of the insulator241b. The conductor242bis positioned on at least part of the bottom portion of the opening, and the conductor245bis in contact with the conductor242b.

The conductor245aand the conductor245bare preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. The conductor245aand the conductor245bmay have a stacked-layer structure.

In the case where the conductor245has a stacked-layer structure, the aforementioned conductor having a function of inhibiting diffusion of impurities such as water or hydrogen is preferably used as the conductor in contact with the metal oxide231a, the metal oxide231b, the conductor242, the insulator254, the insulator280, the insulator274, and the insulator281. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. The conductive material having a function of inhibiting diffusion of impurities such as water or hydrogen can be used as a single layer or stacked layers. The use of the conductive material can inhibit oxygen added to the insulator280from being absorbed by the conductor245aand the conductor245b. Moreover, impurities such as water or hydrogen can be inhibited from entering the metal oxide231through the conductor245aand the conductor245bfrom a layer above the insulator281.

As the insulator241aand the insulator241b, for example, the insulator that can be used as the insulator254or the like can be used. Since the insulator241aand the insulator241bare provided in contact with the insulator254, impurities such as water or hydrogen in the insulator280or the like can be inhibited from entering the metal oxide231through the conductor245aand the conductor245b. Furthermore, oxygen contained in the insulator280can be inhibited from being absorbed by the conductor245aand the conductor245b.

Although not illustrated, a conductor functioning as a wiring may be placed in contact with the top surface of the conductor245aand the top surface of the conductor245b. For the conductor functioning as a wiring, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used. Furthermore, the conductor may have a stacked-layer structure and may be a stack of titanium or a titanium nitride and the above conductive material, for example. Note that the conductor may be formed to be embedded in an opening provided in an insulator.

Materials that can be used for the transistor will be described.

As a substrate where the transistor200is formed, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate of silicon, germanium, or the like and a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Another example is a semiconductor substrate in which an insulator region is included in the semiconductor substrate, e.g., an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Other examples include a substrate including a metal nitride and a substrate including a metal oxide. Other examples include an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator. Alternatively, these substrates provided with elements may be used. Examples of the elements provided for the substrates include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

Examples of an insulator include an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide, each of which has an insulating property.

With further miniaturization and higher integration of a transistor, for example, a problem such as generation of leakage current may arise because of a thinned gate insulator. When a high-k material is used for the insulator functioning as a gate insulator, the voltage at the time of operation of the transistor can be reduced while the physical thickness is maintained. By contrast, when a material with a low dielectric constant is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator.

Examples of the insulator having a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

Examples of the insulator having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin.

When a transistor including an oxide semiconductor is surrounded by insulators having a function of inhibiting the passage of oxygen and impurities such as hydrogen (e.g., the insulator214, the insulator222, the insulator254, and the insulator274), the electrical characteristics of the transistor can be stable. An insulator having a function of inhibiting the passage of oxygen and impurities such as hydrogen can be formed to have a single layer or a stacked layer including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, as the insulator having a function of inhibiting the passage of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide or a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.

An insulator functioning as a gate insulator is preferably an insulator including a region containing oxygen to be released by heating. For example, when a structure is employed in which silicon oxide or silicon oxynitride that includes a region containing oxygen to be released by heating is provided in contact with the metal oxide231, oxygen vacancies included in the metal oxide231can be compensated.

A plurality of conductors formed using any of the above materials may be stacked. For example, a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen may be employed. In addition, a stacked-layer structure combining a material containing the above metal element and a conductive material containing nitrogen may be employed. Furthermore, a stacked-layer structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

In the case where a metal oxide is used for the channel formation region of the transistor, the conductor functioning as the gate electrode preferably employs a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen. In that case, the conductive material containing oxygen is preferably provided on the channel formation region side. When the conductive material containing oxygen is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

It is particularly preferable to use, for the conductor functioning as the gate electrode, a conductive material containing oxygen and a metal element contained in the metal oxide where the channel is formed. A conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. With the use of such a material, hydrogen contained in the metal oxide where the channel is formed can be captured in some cases. Alternatively, hydrogen entering from an external insulator or the like can be captured in some cases.

The structures described in this embodiment can be used in an appropriate combination with any of the structures described in the other embodiments and the like.

Described in this embodiment is a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used in an OS transistor described in the above embodiment.

<Classification of Crystal Structure>

First, the classification of crystal structures of an oxide semiconductor is described with reference toFIG.33A.FIG.33Ais a diagram showing classification of crystal structures of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

As shown inFIG.33A, an oxide semiconductor is roughly classified into “Amorphous”, “Crystalline”, and “Crystal”. “Amorphous” includes completely amorphous. The term “Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) (excluding single crystal and poly crystal). Note that in the classification of “Crystalline,” single crystal, poly crystal, and completely amorphous are excluded. The term “Crystal” includes single crystal and poly crystal.

Note that the structures in the thick frame inFIG.33Aare in an intermediate state between “Amorphous” and “Crystal”, and belong to a new crystalline phase. That is, these structures are completely different from “Crystal” and “Amorphous”, which is energetically unstable.

A crystal structure of a film or a substrate can be evaluated with an X-Ray Diffraction (XRD) spectrum.FIG.33Bshows an XRD spectrum, which is obtained using GIXD (Grazing-Incidence XRD) measurement, of a CAAC-IGZO film classified into “Crystalline”. Note that a GIXD method is also referred to as a thin film method or a Seemann-Bohlin method. The XRD spectrum that is shown inFIG.33Band obtained by GIXD measurement is hereinafter simply referred to as an XRD spectrum. The CAAC-IGZO film inFIG.33Bhas a composition in the vicinity of In: Ga:Zn=4:2:3 [atomic ratio]. The CAAC-IGZO film inFIG.33Bhas a thickness of 500 nm.

As shown inFIG.33B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis alignment is detected at20of around 31° in the XRD spectrum of the CAAC-IGZO film. As shown inFIG.33B, the peak at20of around 31° is asymmetric with respect to the axis of the angle at which the peak intensity is detected.

A crystal structure of a film or a substrate can also be evaluated with a diffraction pattern obtained by a nanobeam electron diffraction (NBED) method (such a pattern is also referred to as a nanobeam electron diffraction pattern).FIG.33Cshows a diffraction pattern of a CAAC-IGZO film.FIG.33Cshows a diffraction pattern obtained with the NBED method in which an electron beam is incident in the direction parallel to the substrate. The CAAC-IGZO film inFIG.33Chas a composition in the vicinity of In: Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

As shown inFIG.33C, a plurality of spots indicating c-axis alignment are observed in the diffraction pattern of the CAAC-IGZO film.

Here, the CAAC-OS, the nc-OS, and the a-like OS will be described in detail.

Note that each of the plurality of crystal regions is formed of one or more minute crystals (crystals each of which has a maximum diameter of less than 10 nm). In the case where the crystal region is formed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. In the case where the crystal region is formed of a large number of minute crystals, the size of the crystal region may be approximately several tens of nanometers.

In the case of an In-M-Zn oxide (the element M is one or more kinds selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, an (M,Zn) layer) are stacked. Indium and the element M can be replaced with each other. Therefore, indium may be contained in the (M,Zn) layer. In addition, the element M may be contained in the In layer. Note that Zn may be contained in the In layer. Such a layered structure is observed as a lattice image in a high-resolution TEM image, for example.

The CAAC-OS is an oxide semiconductor with high crystallinity in which no clear crystal grain boundary is observed. Thus, in the CAAC-OS, reduction in electron mobility due to the crystal grain boundary is less likely to occur. Moreover, since the crystallinity of an oxide semiconductor might be decreased by entry of impurities, formation of defects, and/or the like, the CAAC-OS can be regarded as an oxide semiconductor that has small amounts of impurities and defects (e.g., oxygen vacancies). Thus, an oxide semiconductor including the CAAC-OS is physically stable. Therefore, the oxide semiconductor including the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable with respect to high temperatures in the manufacturing process (what is called thermal budget). Accordingly, the use of the CAAC-OS for the OS transistor can extend the degree of freedom of the manufacturing process.

Next, the above-described CAC-OS is described in detail. Note that the CAC-OS relates to the material composition.

Here, the atomic ratios of In, Ga, and Zn to the metal elements contained in the CAC-OS in an In—Ga—Zn oxide are denoted by [In], [Ga], and [Zn], respectively. For example, the first region in the CAC-OS in the In—Ga—Zn oxide has [In] higher than [In] in the composition of the CAC-OS film. Moreover, the second region has [Ga] higher than [Ga] in the composition of the CAC-OS film. For example, the first region has higher [In] than the second region and has lower [Ga] than the second region. Moreover, the second region has higher [Ga] than the first region and has lower [In] than the first region.

Specifically, the first region includes indium oxide, indium zinc oxide, or the like as its main component. The second region includes gallium oxide, gallium zinc oxide, or the like as its main component. That is, the first region can be referred to as a region containing In as its main component. The second region can be referred to as a region containing Ga as its main component.

For example, energy dispersive X-ray spectroscopy (EDX) is used to obtain EDX mapping, and according to the EDX mapping, the CAC-OS in the In—Ga—Zn oxide has a structure in which the region containing In as its main component (the first region) and the region containing Ga as its main component (the second region) are unevenly distributed and mixed.

In the case where the CAC-OS is used for a transistor, a switching function (on/off switching function) can be given to the CAC-OS owing to the complementary action of the conductivity derived from the first region and the insulating property derived from the second region. That is, the CAC-OS has a conducting function in part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS has a function of a semiconductor. Separation of the conducting function and the insulating function can maximize each function. Accordingly, when the CAC-OS is used for a transistor, high on-state current (Ion), high field-effect mobility (μ), and excellent switching operation can be achieved.

An oxide semiconductor has various structures with different properties. Two or more kinds of the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the CAC-OS, the nc-OS, and the CAAC-OS may be included in the oxide semiconductor of one embodiment of the present invention.

Next, the case where the above oxide semiconductor is used for a transistor is described.

When the above oxide semiconductor is used for a transistor, a transistor with high field-effect mobility can be achieved. In addition, a transistor having high reliability can be achieved.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases.

Accordingly, in order to obtain stable electrical characteristics of a transistor, reducing the impurity concentration in an oxide semiconductor is effective. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable that the impurity concentration in a proximate film be also reduced. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

Here, the influence of each impurity in the oxide semiconductor is described.

When silicon and/or carbon, which are each one of Group 14 elements, is contained in the oxide semiconductor, defect states are formed in the oxide semiconductor. Thus, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon in the vicinity of an interface with the oxide semiconductor (the concentrations obtained by SIMS) are each set lower than or equal to 2×1018atoms/cm3, preferably lower than or equal to 2×1017atoms/cm3.

Furthermore, when the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase in carrier concentration. As a result, a transistor including an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. When nitrogen is contained in the oxide semiconductor, a trap state is sometimes formed. This might make the electrical characteristics of the transistor unstable. Therefore, the concentration of nitrogen in the oxide semiconductor, which is obtained using SIMS, is set lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, still further preferably lower than or equal to 5×1017atoms/cm3.

The structures described in this embodiment can be used in an appropriate combination with any of the structures described in the other embodiments and the like.

In this embodiment, electronic devices to which the semiconductor device of one embodiment of the present invention can be applied will be described.

The semiconductor device of one embodiment of the present invention can be used in a display portion of an electronic device. Thus, an electronic device with high display quality can be obtained. An electronic device with an extremely high resolution can be obtained. A highly reliable electronic device can be obtained.

Examples of electronic devices including the semiconductor device or the like of one embodiment of the present invention include display apparatuses of televisions, monitors, and the like, lighting devices, desktop or laptop personal computers, word processors, image reproduction devices which reproduce still images or moving images stored in recording media such as DVDs (Digital Versatile Discs), portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless phone handsets, transceivers, car phones, cellular phones, portable information terminals, tablet terminals, portable game machines, stationary game machines such as pachinko machines, calculators, electronic notebooks, e-book readers, electronic translators, audio input devices, video cameras, digital still cameras, electric shavers, high-frequency heating appliances such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air-conditioning systems such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for preserving DNA, flashlights, tools such as chain saws, smoke detectors, and medical equipment such as dialyzers. Other examples include industrial equipment such as guide lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and power storage devices for leveling the amount of power supply and smart grid. In addition, moving objects and the like driven by fuel engines or electric motors using power from power storage units may also be included in the category of electronic devices. Examples of the moving objects include electric vehicles (EVs), hybrid electric vehicles (HEVs) that include both an internal-combustion engine and a motor, plug-in hybrid electric vehicles (PHEVs), tracked vehicles in which caterpillar tracks are substituted for wheels of these vehicles, motorized bicycles including motor-assisted bicycles, motorcycles, electric wheelchairs, golf carts, boats, ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spacecraft.

The electronic device of one embodiment of the present invention may include a secondary battery (battery), and it is preferable that the secondary battery be capable of being charged by contactless power transmission.

Examples of the secondary battery include a lithium ion secondary battery, a nickel-hydride battery, a nickel-cadmium battery, an organic radical battery, a lead-acid battery, an air secondary battery, a nickel-zinc battery, and a silver-zinc battery.

The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, an image, information, and the like can be displayed on a display portion. When the electronic device includes the antenna and a secondary battery, the antenna may be used for contactless power transmission.

Furthermore, an electronic device including a plurality of display portions can have a function of displaying image information mainly on one display portion while displaying text information mainly on another display portion, a function of displaying a three-dimensional image by displaying images on a plurality of display portions with a parallax taken into account, or the like. Furthermore, an electronic device including an image receiving portion can have a function of taking a still image or a moving image, a function of automatically or manually correcting a taken image, a function of storing a taken image in a recording medium (an external recording medium or a recording medium incorporated in the electronic device), a function of displaying a taken image on a display portion, or the like. Note that functions of the electronic device of one embodiment of the present invention are not limited thereto, and the electronic devices can have a variety of functions.

The semiconductor device of one embodiment of the present invention can display high-resolution images. Thus, the light-emitting apparatus of one embodiment of the present invention can be suitably used especially for a portable electronic device, a wearable electronic device (wearable device), an e-book reader, and the like. In addition, the semiconductor device can be suitably used for xR devices such as a VR (Virtual Reality) device and an AR (Augmented Reality) device.

FIG.34Aillustrates an appearance of a head-mounted display810. The head-mounted display810includes a mounting portion811, a lens812, a main body813, a display portion814, a cable815, and the like. A battery816is incorporated in the mounting portion811. The semiconductor device of one embodiment of the present invention can be used in the display portion814.

The cable815supplies electric power from the battery816to the main body813. The main body813includes a wireless receiver or the like and can display received image information, such as image data, on the display portion814. The movement of the eyeball and/or the eyelid of a user is captured by a camera provided in the main body813and then the sight line of the user are calculated using the information to utilize the sight line of the user as an input means.

A plurality of electrodes may be provided in the mounting portion811at positions in contact with the user. The main body813may have a function of recognizing the user's sight line by sensing current flowing through the electrodes in accordance with the movement of the user's eyeball. The main body813may have a function of sensing current flowing through the electrodes to monitor the user's pulse. The mounting portion811may include various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor and may have a function of displaying the user's biological information on the display portion814. The main body813may sense the movement of the user's head or the like to change an image displayed on the display portion814in synchronization with the movement.

FIG.34Billustrates an appearance of a head-mounted display820. The head-mounted display820is a goggles-type information processing device.

The head-mounted display820includes a housing821, an operation button823, a fixing band824, and two display portions822. Since the head-mounted display820includes the two display portions822, the user's eyes can see their respective display portions. This allows a high-definition image to be displayed even when three-dimensional display using parallax or the like is performed. A battery825is provided for the fixing band824. The battery825may be provided in the housing821. However, the battery is preferably provided for the fixing band824, whereby the center of gravity of the head-mounted display820is placed in the rear part and thus the user's feeling of wearing is enhanced. Note that besides the battery825a driver circuit or the like for driving the display portion822may be provided for the fixing band824so that the center of gravity of the head-mounted display820can be adjusted.

The operation button823has a function of a power button or the like. A button other than the operation button823may be included.

The semiconductor device of one embodiment of the present invention can be used in the display portion822. The semiconductor device of one embodiment of the present invention has an extremely high resolution; thus, the pixels are less likely to be perceived by a user and a more realistic image can be displayed.

FIG.34Cillustrates an appearance of a camera830equipped with a finder840.

The camera830includes a housing831, a display portion832, operation buttons833, a shutter button834, and the like. Furthermore, a detachable lens836is attached to the camera830.

Although the lens836of the camera830here is detachable from the housing831for replacement, the lens836may be integrated with the housing.

The camera830can take images at the press of the shutter button834. In addition, the display portion832has a function of a touch panel, and images can also be taken by the touch on the display portion832.

The housing831of the camera830includes a mount including an electrode, so that the finder840, a stroboscope, or the like can be connected to the housing.

The finder840includes a housing841, a display portion842, a button843, and the like.

The housing841includes a mount for engagement with the mount of the camera830so that the finder840can be attached to the camera830. The mount includes an electrode, and an image or the like received from the camera830through the electrode can be displayed on the display portion842.

The button843functions as a power button. The on/off state of the display portion842can be switched with the button843.

The semiconductor device of one embodiment of the present invention can be used in the display portion832of the camera830and the display portion842of the finder840.

Although the camera830and the finder840are separate and detachable electronic devices inFIG.34C, a finder including the semiconductor device of one embodiment of the present invention may be built into the housing831of the camera830.

An information terminal850illustrated inFIG.34Dincludes a housing851, a display portion852, a microphone857, a speaker portion854, a camera853, an operation switch855, and the like. The semiconductor device of one embodiment of the present invention can be used in the display portion852. The display portion852functions as a touch panel. The information terminal850also includes an antenna, a battery, and the like inside the housing851. The information terminal850can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an e-book reader, or the like.

FIG.34Eillustrates an example of a watch-type information terminal. An information terminal860includes a housing861, a display portion862, a band863, a buckle864, an operation switch865, an input/output terminal866, and the like. In addition, the information terminal860includes an antenna, a battery, and the like inside the housing861. The information terminal860is capable of executing a variety of applications such as mobile phone calls, e-mailing, viewing and editing texts, music reproduction, Internet communication, and a computer game.

In addition, the display portion862includes a touch sensor, and operation can be performed by touching the screen with a finger, a stylus, or the like. For example, with a touch on an icon867displayed on the display portion862, an application can be started. The operation switches865can have a variety of functions such as time setting, power on/off operation, on/off operation of wireless communication, setting and cancellation of a silent mode, and setting and cancellation of a power saving mode. For example, the functions of the operation switches865can be set by the operation system incorporated in the information terminal860.

The information terminal860can execute near field communication conformable to a communication standard. For example, mutual communication between the information terminal860and a headset capable of wireless communication enables hands-free calling. The information terminal860includes an input/output terminal866, and can perform data transmission and reception with another information terminal through the input/output terminal866. In addition, charging can be performed via the input/output terminal866. Note that the charging operation may be performed by wireless power feeding without using the input/output terminal866.

The structures described in this embodiment can be used in an appropriate combination with any of the structures described in the other embodiments and the like.

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