Semiconductor integrated circuit, storage device, and error correction method

A semiconductor integrated circuit reads data from a memory, which stores the data including a data portion and a parity bit, and makes an error correction to the data. The semiconductor integrated circuit includes a memory controller for reading the data from the memory; and an error correction controller having an error correction circuit having the ability to correct a predetermined number of bits of errors. The error correction controller applies an error correction to the read data by the error correction circuit, and determines whether all errors contained in the data are corrected, based on the data portion and the parity bit of the data after the error correction. When not all the errors contained in the data are determined to be corrected, the error correction controller applies an error correction by the error correction circuit, while sequentially inverting the data value of each bit of the data.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2018-82840 filed on Apr. 24, 2018, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor integrated circuit that applies an error correction to data, and an error correction method.

BACKGROUND

Error correction circuits are widely used in various systems that treat data. For example, when data stored in a device is transferred to another device through a communication path, errors such as garbled bits sometimes occur. To correct the garbled bits occurring in the transfer, an error correction circuit is often installed in the device. The garbled bits occur not only in transferring data but also in storing or reading data in or from a recording medium such as a memory. Accordingly, there are proposed error correction circuits that applies corrections to data to be stored in memories such as flash memories using coding means such as a BCH code (for example, Japanese Patent Application Laid-Open Nos. 2014-22848 and 2009-152781).

The correction ability (in other words, how many garbled bits can be corrected) of the error correction circuit depends on the size of a circuit that is able to be installed in the device. Thus, there is a problem that a device that can install only a circuit of a small size has no other choice but to adopt an error correction circuit having a low correction ability. Even if an error correction circuit of a large size can be installed, there is still a problem that, to improve its correction ability, the error correction circuit is required to be redesigned from the beginning.

Considering the problems described above, it is aimed at providing a semiconductor integrated circuit including an error correction circuit, and more specifically a semiconductor integrated circuit that can correct errors the number of bits of which exceeds the correction ability of the error correction circuit.

DETAILED DESCRIPTION

A semiconductor integrated circuit according to embodiments is connected to a memory that stores data including a data portion and a parity bit corresponding to the data portion. The semiconductor integrated circuit reads the data from the memory and applies an error correction to the data. The semiconductor integrated circuit includes a memory controller configured to read the data from the memory; and an error correction controller configured to include an error correction circuit having the ability to correct a predetermined number of bits of errors, and to apply an error correction to the data read from the memory. The error correction controller applies an error correction to the data read from the memory, by the error correction circuit, and determines whether or not all errors contained in the data are corrected, on the basis of the data portion and the parity bit of the data after the error correction. When not all the errors contained in the data are determined to be corrected, the error correction controller applies an error correction to said data by the error correction circuit, while sequentially inverting the data value of each bit of the data.

A storage device according to the embodiments includes a memory configured to store data including a data portion and a parity bit corresponding to the data portion; a memory controller configured to read the data from the memory; and an error correction controller configured to include an error correction circuit having the ability to correct a predetermined number of bits of errors, and to applies an error correction to the data read from the memory. The error correction controller applies an error correction to the data read from the memory, by the error correction circuit, and determines whether or not all errors contained in the data are corrected, on the basis of the data portion and the parity bit of the data after the error correction. When not all the errors contained in the data are determined to be corrected, the error correction controller applies an error correction by the error correction circuit, while sequentially inverting the data value of each bit of the data.

An error correction method according to the embodiments is performed by a semiconductor integrated circuit that includes an error correction circuit having the ability to correct a predetermined number of bits of errors. The semiconductor integrated circuit reads data from a memory configured to store the data including a data portion and a parity bit corresponding to the data portion, and applies an error correction thereto. The error correction method includes the steps of reading the data from the memory; making an error correction to the data read from the memory, by the error correction circuit; generating a new parity bit on the data portion of the data after the error correction; comparing the new parity bit with the party bit on the data after the error correction, to determine whether or not all errors contained in the data are corrected; and when not all the errors contained in the data are determined to be corrected, making an error correction by the error correction circuit, while sequentially inverting the data value of each bit of the data.

An error correction method according to the embodiments is performed by a semiconductor integrated circuit that includes an error correction circuit having the ability to correct a predetermined number of bits of errors. The semiconductor integrated circuit reads data and CRC data from a memory configured to store the data including a data portion and a parity bit corresponding to the data portion and the CRC data including a CRC code corresponding to the data portion and a parity bit corresponding to the CRC code, and applies an error correction thereto. The error correction method includes the steps of reading the data and the CRC data from the memory; applying an error correction to the data read from the memory, by using the error correction circuit; applying an error correction to the CRC data read from the memory; generating a new CRC code on the data portion of the data after the error correction; and comparing the new CRC code with the CRC code of the CRC data after the error correction, to determine whether or not the error correction is precisely made on the data.

According to the semiconductor integrated circuit of the embodiments, it is possible to correct errors the number of bits of which exceeds the correction ability of the error correction circuit.

Preferred embodiments will be described below in detail. Note that, in the following description and attached drawings of the embodiments, the same reference numerals indicate substantially the same or equivalent components.

First Embodiment

FIG. 1is a block diagram that illustrates a configuration of a storage device100according to the present embodiment. The storage device100includes a memory controller11, an error correction controller12, and a memory20. The memory controller11and the error correction controller12constitute a semiconductor integrated circuit10of one chip.

The memory controller11writes data to the memory20and reads data from the memory20. The memory controller11supplies the data read from the memory20to the error correction controller12.

The error correction controller12is a circuit that applies an error correction to data read from the memory20by the memory controller11. To be more specific, the error correction controller12corrects bit errors (so-called garbled bits) that occur in writing or reading of the data. The error correction controller12includes a correction control unit13, an error correction circuit14, and an internal memory15.

The correction control unit13is a control circuit that controls the error correction circuit14to make an error correction. The correction control unit13performs data processing including generation of a parity bit on data read from the memory20, comparison of data and the like.

The error correction circuit14is a circuit to apply an error correction (in other words, a garbled bit correction) to data read from the memory20. The error correction circuit14makes the error correction using, for example, a BCH coding method. The error correction circuit14has the ability to correct a predetermined number of bits of errors, which is determined by the error correction method and the size (byte number) of a parity bit accompanying the data.

The internal memory15is a volatile memory installed in the error correction controller12. The internal memory15is used as a working area that temporarily stores data in error processing that the correction control unit13and the error correction circuit14perform.

The memory20is a non-volatile memory device composed of, for example, a NAND flash memory. The memory20stores a predetermined number of bits (for example, 16 bytes) of data and a parity bit generated on the basis of a BCH coding method, in correspondence with each other.

FIG. 2Ais a drawing illustrating an example of the structure of data stored in the memory20. The memory20stores 16-byte data accompanied with a 2-byte parity bit, as one piece of data. In the following description, the 16-byte data is referred to as a “data portion”, and the entirety (18 bytes) of the data portion accompanied with the 2-byte parity bit is simply referred to as “data”.

As described above, in the present embodiment, data is constituted of a 16-byte data portion and a 2-byte parity bit accompanying therewith. The error correction circuit14can correct up to 2 bits of errors of the 18-byte data. In other words, the error correction circuit14of the present embodiment has the ability to correct 2 bits of errors.

Next, the operation of error correction processing performed by the semiconductor integrated circuit10according to the present embodiment will be described with reference to a flowchart ofFIGS. 3 and 4andFIGS. 2A to 2F.

The memory controller11reads 18-byte data (a 16-byte data portion and a 2-byte parity bit) having the structure as illustrated inFIG. 2Afrom the memory20(STEP101). The memory controller11supplies the read data to the error correction controller12. The correction control unit13of the error correction controller12stores the read data in the internal memory15.

The correction control unit13controls the error correction circuit14to perform error correction processing on each of the data portion and the parity bit of the read data (STEP102). InFIG. 2B, the read data after the error correction is indicated with shading.

Next, the correction control unit13controls the error correction circuit14to newly generate a 2-byte parity bit on the data portion (16 bytes) of the read data (hereinafter referred to as corrected data) after the error correction (STEP103).

The correction control unit13compares the parity bit that is newly generated in STEP103with the parity bit the error of which is corrected in STEP102(STEP104). InFIG. 2C, the newly generated parity bit is indicated with dots, and the parity bit the error of which is corrected in STEP102is indicated with shading.

The correction control unit13determines whether or not the two parity bits coincide (STEP105). When the parity bits are determined to coincide (YES in STEP105), all errors contained in the read data are determined to be corrected, and the operation ends. When the parity bits are not determined to coincide (NO in STEP105), it is determined that errors exceeding the correction ability of the error correction circuit14(i.e. more than 2 bits of errors in the present embodiment) are present, and the operation of the semiconductor integrated circuit10shifts to processing steps illustrated in the flowchart ofFIG. 4.

The correction control unit13inverts the value of a first one bit of the corrected data (STEP201).FIG. 2Dillustrates corrected data after the reversal of the value of the first one bit.

The correction control unit13controls the error correction circuit14to perform error correction processing on the corrected data after the reversal of the value of the first one bit (STEP202).FIG. 2Eillustrates data after the error correction in STEP202.

The correction control unit13controls the error correction circuit14to newly generate a 2-byte parity bit on the data portion (16 bytes) of the data after the error correction in STEP202(in other words, data after the reversal of the bit and the correction) (STEP203).

The correction control unit13makes a comparison between the parity bit newly generated in STEP203and the parity bit after the error correction in STEP202(STEP204). InFIG. 2F, the newly generated parity bit is indicated with dots, and the parity bit after the error correction in STEP202is indicated with shading.

The correction control unit13determines whether or not the two parity bits coincide (STEP205). When the parity bits are determined to coincide (YES in STEP205), all errors are determined to be corrected in STEP202, and the operation ends.

On the other hand, when the parity bits are not determined to coincide (NO in STEP205), the correction control unit13repeatedly performs STEP202to STEP205, while shifting a bit the value of which is inverted until parity bits coincide or the reversal reaches the last bit. In other words, the correction control unit13determines whether or not the reversal of bits of the corrected data has proceeded to the last bit (STEP206). When the reversal of bits has not proceeded to the last bit (NO in STEP206), the value of the next bit is inverted and STEP202to STEP205are performed again. When the reversal of bits has proceeded to the last bit (YES in STEP206), the correction control unit13determines that not all errors can be corrected because the number of bits of the errors exceeds the sum of the correction ability of the error correction circuit14and one bit corrected by the reversal (in other words, 3 bits in the present embodiment) (STEP208), and the operation ends.

As described above, the semiconductor integrated circuit10according to the present embodiment makes a comparison between the parity bit on which the error correction is performed and the parity bit newly generated on the data after the error correction, and determines whether or not the parity bits coincide with each other, in order to determine whether or not all errors contained in the read data be corrected. When not all errors are determined to be corrected, the error correction is repeatedly performed while the bit value of the data is inverted on a one-by-one basis. According to the processing, even if data has errors (garbled bits) the number of which exceeds the correction ability of the error correction circuit14by one bit, the errors can be corrected precisely.

Accordingly, the semiconductor integrated circuit10according to the present embodiment can correct the bit errors exceeding the correction ability of the error correction circuit, without changing the design of the error correction circuit. As compared with the case of changing the design of the error correction circuit, it is possible to prevent an increase in the size of the circuit.

Second Embodiment

Next, a storage device according to a second embodiment will be described. The storage device according to the present embodiment has the same configuration as the storage device100according to the first embodiment illustrated inFIG. 1, but is different from the storage device100according to the first embodiment in a data structure stored in the memory20and in the operation of error correction processing performed by the error correction controller12.

FIG. 5is a drawing illustrating an example of the structure of data stored in the memory20according to the present embodiment. The memory20stores a 16-byte data portion and a 4-byte CRC (cyclic redundancy check) code corresponding to the data portion, in correspondence with each other. Each of the 16-byte data portion and the 4-byte CRC code is accompanied with a 2-byte parity bit. In the following description, the 4-byte CRC code accompanied with the 2-byte parity bit is referred to as “CRC data”.

As described above, in the present embodiment, the 16-byte data portion is accompanied with the 2-byte parity bit, and the 4-byte CRC code is accompanied with the 2-byte parity bit. The error correction circuit14according to the present embodiment has the ability to correct 2 bits of errors, as in the case of the first embodiment. Thus, the error correction circuit14can correct 2 bits of errors of the 18-byte data. The error correction circuit14can also correct 2 bits of errors of the 6-byte CRC data.

Next, the operation of error correction processing performed by the semiconductor integrated circuit10according to the present embodiment will be described with reference to a flowchart ofFIGS. 6 to 8,FIGS. 9A to 9FandFIG. 10.

The memory controller11reads 18-byte data including a 16-byte data portion and a 2-byte parity bit, and 6-byte CRC data including a 4-byte CRC code and a 2-byte parity bit from the memory20(STEP301). The memory controller11supplies the read data and the read CRC data to the error correction controller12. The correction control unit13of the error correction controller12stores the read data and the read CRC data in the internal memory15.

The semiconductor integrated circuit10performs the same processing as the sequential processing of STEPS101to105and STEPS201to208of the first embodiment on the read data. At this time, if coincidence (YES) is determined in STEP105or STEP205, the operation of the semiconductor integrated circuit10shifts to a processing step of STEP303(STEP302).

The correction control unit13controls the error correction circuit14to perform error correction processing on each of the CRC code and the parity bit of the read CRC data (STEP303).FIG. 9Aillustrates the read CRC code before the error correction. InFIG. 9B, the read CRC data after the error correction is illustrated by shading.

Next, the correction control unit13controls the error correction circuit14to newly generate, with respect to a CRC code (4 bytes) of the read CRC data after the error correction (hereinafter referred to as corrected CRC data), a 2-byte parity bit corresponding to the CRC code (STEP304).

The correction control unit13makes a comparison between the parity bit newly generated in STEP304and the parity bit the error of which is corrected in STEP303(STEP305). InFIG. 9C, the newly generated parity bit is indicated with dots, and the parity bit the error of which is corrected in STEP303is indicated with shading.

The correction control unit13determines whether or not the two parity bits coincide (STEP306). When the parity bits are determined to coincide (YES in STEP306), all errors contained in the read CRC data are determined to be corrected, and the operation of the semiconductor integrated circuit10shifts to processing steps illustrated in the flowchart ofFIG. 8. On the other hand, when the parity bits are not determined to coincide (NO in STEP306), it is determined that errors exceeding the correction ability of the error correction circuit14(i.e. more than 2 bits of errors in the present embodiment) are present, and the operation of the semiconductor integrated circuit10shifts to processing steps illustrated in the flowchart ofFIG. 7.

The correction control unit13inverts the value of a first one bit of the corrected CRC data (STEP401).FIG. 9Dillustrates the corrected CRC data after the reversal of the value of the first one bit.

The correction control unit13controls the error correction circuit14to perform error correction processing on the corrected CRC data after the reversal of the value of the first one bit (STEP402).FIG. 9Eillustrates the CRC data after the error correction in STEP402.

The correction control unit13controls the error correction circuit14to newly generate, with respect to a CRC code (4 bytes) of the CRC data after the error correction in STEP402(in other words, CRC data after the reversal of the bit and the correction), a 2-byte parity bit (STEP403).

The correction control unit13makes a comparison between the parity bit newly generated in STEP403and the parity bit after the error correction in STEP402(STEP404). InFIG. 9F, the newly generated parity bit is indicated with dots, and the parity bit after the error correction in STEP402is indicated with shading.

The correction control unit13determines whether or not the two parity bits coincide (STEP405). When the parity bits are determined to coincide (YES in STEP405), an error is determined to be corrected in STEP402, and the operation of the semiconductor integrated circuit10shifts to processing steps illustrated in the flowchart ofFIG. 8.

On the other hand, when the parity bits are not determined to coincide (NO in STEP405), the correction control unit13repeatedly performs STEP402to STEP405, while shifting a bit the value of which is inverted until the parity bits coincide or the reversal reaches the last bit. In other words, the correction control unit13determines whether or not the reversal of bits of the corrected CRC data has proceeded to the last bit (STEP406). When the reversal of bits has not proceeded to the last bit (NO in STEP406), the value of the next bit is inverted and STEP402to STEP405are performed again. When the reversal of bits has proceeded to the last bit (YES in STEP406), the correction control unit13determines that errors cannot be corrected because the number of bits of the errors exceeds the sum of the correction ability of the error correction circuit14and one bit corrected by the reversal (in other words, 3 bits in the present embodiment) (STEP408), and the operation ends.

When the correction control unit13determines that the parity bits coincide with each other in each of STEP306and STEP405, a 4-byte CRC code for the 16-byte data portion of the corrected data is newly generated (STEP501).

The correction control unit13makes a comparison between the CRC code newly generated in STEP501and the CRC code the error of which is corrected in STEP303or STEP402(STEP502). InFIG. 10, the newly generated CRC code is indicated with dots, and the CRC code the error of which is corrected in STEP303or STEP402is indicated with shading.

The correction control unit13determines whether or not the two CRC codes coincide (STEP503). When the CRC codes are determined to coincide (YES in STEP503), all errors contained in all the data and the CRC data are determined to be corrected precisely, and the operation ends (STEP504).

On the other hand, when the CRC codes are not determined to coincide (NO in STEP503), the correction control unit13determines that a wrong correction has occurred in the error correction processing, and the operation ends (STEP505).

As described above, the semiconductor integrated circuit10according to the present embodiment makes a comparison between the parity bit on which the error correction is performed and the parity bit newly generated on the data after the error correction, and determines whether or not the parity bits coincide with each other, in order to determine whether or not all errors contained in the read data are corrected. When not all errors are determined to be corrected, the error correction is repeatedly performed while the bit value of the data is inverted on a one-by-one basis. According to the processing, even if the data has errors (garbled bits) the number of which exceeds the correction ability of the error correction circuit14by one bit, the errors can be corrected precisely. Accordingly, it is possible to correct the bit errors exceeding the correction ability of the error correction circuit, without changing the design of the error correction circuit. As compared with the case of changing the design of the error correction circuit, it is possible to prevent an increase in the size of the circuit.

In the semiconductor integrated circuit10according to the present embodiment, the data is accompanied with the CRC code, and the same error correction processing as that performed on the data is also performed on the CRC code. The CRC code after the error correction is compared with a CRC code that is newly generated on the data after the error correction. Whether or not the CRC codes coincide with each other is determined, in order to determine whether or not the error correction is precisely performed. This processing serves to prevent wrong error correction.

It is not limited to the above-described embodiments. For example, the correction control unit13may not be a dedicated circuit for performing specific processing, but may be constituted of a CPU (central processing unit) and firmware that control the operation of each component of the error correction controller12.

The above-described first and second embodiments describe cases in which the error correction circuit14performs the error correction using the BCH coding method, but the error correction may be performed in an arbitrary correction method.

In the above-described first and second embodiments, by way of example, the memory controller11stores the data read out of the memory20in the internal memory15, but may store the data in an optional memory, such as a RAM (random access memory) or a non-volatile storage medium.

In the above-described first and second embodiments, the original data is stored in the memory20, but may be stored in an arbitrary storage medium such as a ROM. Otherwise, data received through a device supporting data communication, instead of data stored in the storage medium, may be processed.

In the above-described first and second embodiments, by way of example, the error correction is performed using the 16-byte data and the 2-byte parity bit for error correction, but the data and the parity bit are not limited to these sizes and may have arbitrary sizes. For example, an N-byte (N is an arbitrary natural number) of data and an M-byte (M is a natural number that satisfies M<N) of parity bit may be used.

The above-described first and second embodiments describe cases in which the error correction circuit has the ability to correct 2 bits of errors, but may have the ability to correct an arbitrary different number of errors.

In the above-described embodiment, the value of data is inverted from its front bit on a one-by-one basis, but where to start the reversal is not limited thereto. The reversal may be started from an arbitrary bit position, as long as the value of data is finally inverted at every bit. Instead of on a one-by-one basis, arbitrary n bits (n is a natural number) may be set at one unit. The value of each of the n bits may be inverted in error correction processing, and the error correction processing may be repeatedly performed while the position of reversal is shifted by n bits. For example, in a case where 2 bits constitute 1 unit, if original data is “00”, the bits are inverted to “01”, “10” and “11”, and the error correction processing is performed on each inverted data. Repeatedly performing the same processing, while shifting the position by 2 bits, allows correcting errors that exceeds the correction ability of the error correction circuit by 1 bit, and errors that exceeds the correction ability of the error correction circuit by 2 bits. After the error correction processing is performed with reversal of bits on a one-by-one basis, the error correction processing may be performed with reversal of bits by two-by-two basis. This case also allows correcting errors that exceeds the correction ability of the error correction circuit by 1 bit, and errors that exceeds the correction ability of the error correction circuit by 2 bits. When shifting an inverted bit position, the bit position may be shifted every other bit or every several bits, instead of every sequential bit.

In the above-described second embodiment, the data is accompanied with the 4-byte CRC code, but the CRC code is not limited to this size and may have an arbitrary size.

In the above-described second embodiment, after the error correction processing is performed on the data, the error correction processing is performed on the CRC code. However, the error correction processing may be performed in opposite order or in a concurrent manner.

It is understood that the foregoing description and accompanying drawings set forth the preferred embodiments of the present invention at the present time. Various modifications, additions and alternative designs will, of course, become apparent to those skilled in the art in light of the foregoing teachings without departing from the spirit and scope of the disclosed invention. Thus, it should be appreciated that the present invention is not limited to the disclosed Examples but may be practiced within the full scope of the appended claims.