Fin Isolation Regions With Improved Depth Distribution and Methods Forming the Same

A method includes forming a gate stack on a semiconductor region, wherein the semiconductor region is over a bulk semiconductor substrate. The gate stack is etched to form a first trench, wherein a plurality of protruding semiconductor fins are revealed to the first trench. The plurality of protruding semiconductor fins are etched to form a plurality of second trenches extending into the bulk semiconductor substrate. The plurality of second trenches are underlying and joined to the first trench. The plurality of second trenches include a first outmost trench having a first depth, a second outmost trench, and an inner trench between the first outmost trench and the second outmost trench. The inner trench has a second depth equal to or smaller than the first depth. A fin isolation region is formed to fill the first trench and the plurality of second trenches.

BACKGROUND

Technological advances in Integrated Circuit (IC) materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generations. In the course of IC evolution, functional density (for example, the number of interconnected devices per chip area) has generally increased while geometry sizes have decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

Such scaling down has also increased the complexity of processing and manufacturing ICs, and for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, Fin Field-Effect Transistors (FinFETs) have been introduced to replace planar transistors. The structures of FinFETs and methods of fabricating FinFETs are being developed.

The formation of FinFETs typically includes forming long semiconductor fins and long gate stacks, and then forming isolation regions to cut the long semiconductor fins and long gate stacks into shorter portions, which act as the fins and the gate stacks of FinFETs.

DETAILED DESCRIPTION

A method of forming isolation regions for isolating transistors is provided. The profiles of the isolation structures are also provided. In accordance with some embodiment, a gate stack is etched to reveal the underlying protruding semiconductor fins. The semiconductor fins and the underlying bulk semiconductor substrate are etched so that the resulting recesses extend into the underlying bulk semiconductor substrate. In the etching process, the gas conductance is increased to adjust the profile of the resulting depths of the recesses. Sputtering effect may also be increased in the etching process to adjust the profile. It is appreciated that although the formation isolations for FinFETs is used as an example, the method may also be applied to the isolation of other transistors such as planar transistors, Gate-All-Around (GAA) transistors, and the like. Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

FIGS.1-8,9A,9B,10,11A,11B,11C,12A,12B,13A,13B,14A,14B,15A,15B.16A,16B, and16C illustrate the perspective views, cross-sectional views, and a top view of intermediate stages in the formation of isolation regions and FinFETs in accordance with some embodiments. The corresponding processes are also reflected schematically in the process flow shown inFIG.21.

FIG.1illustrates a perspective view of an initial structure. The initial structure includes wafer10, which further includes substrate20. Substrate20may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. Substrate20may be doped with a p-type or an n-type impurity. Isolation regions22such as Shallow Trench Isolation (STI) regions may be formed to extend from a top surface of substrate20into substrate20. The respective process is illustrated as process202in the process flow200as shown inFIG.21. The portions of substrate20between neighboring STI regions22are referred to as semiconductor strips24.

In accordance with some embodiments, semiconductor strips24are parts of the original substrate20, and the material of semiconductor strips24is the same as that of the underlying bulk portion of substrate20. In accordance with alternative embodiments, semiconductor strips24are replacement strips formed by etching the portions of substrate20between STI regions22to form recesses, and performing an epitaxy process to regrow another semiconductor material in the recesses. Accordingly, semiconductor strips24are formed of a semiconductor material different from that of substrate20. In accordance with some embodiments, semiconductor strips24are formed of Si, SiP, carbon-doped silicon, SiPC, SiGe, SiGeB, Ge, a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or the like.

STI regions22may include a liner oxide (not shown), which may be a thermal oxide formed through the thermal oxidation of a surface layer of substrate20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), Chemical Vapor Deposition (CVD), or the like. STI regions22may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on coating, or the like.

FIG.1further illustrates the formation of dielectric dummy strips25. In accordance with some embodiments, dielectric dummy strips25are formed by etching one of the semiconductor strips24to form recesses, and then filling the recesses with a dielectric material. Accordingly, the bottoms of dielectric dummy strips25are in contact with the top surfaces of the underlying bulk portion of semiconductor substrate20. In accordance with other embodiments, dielectric dummy strips25and their surrounding portions of STI regions22are formed in a combined process. The resulting dielectric dummy strips25may land on the underlying dielectric material, and dashed lines are shown to represent the bottom surfaces of dielectric dummy strips25. Dielectric dummy strips25may be formed of or comprise a high-k dielectric material such as silicon nitride.

The semiconductor strips24between two dielectric dummy strips25collectively form a semiconductor strip group. The semiconductor strips24in the same semiconductor strip group may have a uniform pitch or a substantially uniform pitch (for example, with a variation smaller than about 20 percent). In accordance with some embodiments, as shown inFIG.1, a semiconductor strip group may include two semiconductor strips24(and the corresponding semiconductor fins24′ as shown inFIG.2). In accordance with alternative embodiments, the semiconductor strip group may be a single-strip group including a single semiconductor strip24. In accordance with yet alternative embodiments, the semiconductor strip group may include a plurality (more than two) semiconductor strips24. For example,FIG.16Cillustrates an example semiconductor strip group including a plurality of closely located semiconductor strips24.

Referring toFIG.2, STI regions22are recessed. The top portions of semiconductor strips24and dielectric dummy strips25protrude higher than the top surfaces22T of the remaining portions of STI regions22to form protruding fins24′ and dummy fin25′, respectively. The respective process is illustrated as process204in the process flow200as shown inFIG.21. The etching may be performed using a dry etching process, wherein etching gases such as the mixture of HF and NH3may be used. In accordance with alternative embodiments, the recessing of STI regions22is performed using a wet etching process. The etching chemical may include HF solution, for example.

Referring toFIG.3, dummy gate stacks30and gate spacers38are formed on the top surfaces and the sidewalls of (protruding) fins24′ and dummy fin25′. The respective process is illustrated as process206in the process flow200as shown inFIG.21. Dummy gate stacks30may include dummy gate dielectrics32and dummy gate electrodes34over dummy gate dielectrics32. Dummy gate electrodes34may be formed, for example, using polysilicon or amorphous silicon, and other materials may also be used. Each of dummy gate stacks30may also include one (or a plurality of) hard mask layer36over dummy gate electrode34. Hard mask layers36may be formed of silicon nitride, silicon oxide, silicon carbo-nitride, or multi-layers thereof. Dummy gate stacks30may cross over a single one or a plurality of protruding fins24′ and dummy fins25′ and STI regions22. Dummy gate stacks30also have lengthwise directions perpendicular to the lengthwise directions of protruding fins24′ and dummy fin25′

Next, gate spacers38are formed on the sidewalls of dummy gate stacks30. In accordance with some embodiments, gate spacers38are formed of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbo-nitride (SiCN), silicon oxynitride (SiON), silicon oxy-carbo-nitride (SiOCN), or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

FIG.4illustrates the formation of epitaxy regions42, which act as the source/drain regions of the resulting FinFETs, and hence are alternatively referred to as source/drain regions42. The respective process is illustrated as process208in the process flow200as shown inFIG.21. Source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context. In accordance with some embodiments an etching process (referred to as source/drain recessing hereinafter) is performed to etch the portions of protruding fins24′ that are not covered by dummy gate stack30and gate spacers38to form recesses. The recessing may be anisotropic, and hence the portions of protruding fins24′ directly underlying dummy gate stacks30and gate spacers38are protected, and are not etched. In the etching process, dielectric dummy fins25′ are not etched. For example, protruding fins24′ may be etched using the mixture of NF3and NH3, the mixture of HF and NH3, or the like.

Next, epitaxy regions42are formed by selectively growing a semiconductor material from the recesses. In accordance with some embodiments, epitaxy regions42include silicon germanium, silicon, silicon carbon, or the like. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p-type or an n-type impurity may be in-situ doped with the proceeding of the epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), SiB, GeB, or the like may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorous (SiP), silicon carbon phosphorous (SiCP), or the like, may be grown. After epitaxy regions42fully fill the recesses, epitaxy regions42start expanding horizontally, and facets may be formed.

FIG.5illustrates a perspective view of the structure after the formation of Contact Etch Stop Layer (CESL)46and Inter-Layer Dielectric (ILD)48. The respective process is illustrated as process210in the process flow200as shown inFIG.21. CESL46may be formed of silicon nitride, silicon carbo-nitride, or the like. CESL46may be formed using a conformal deposition method such as ALD or CVD, for example. ILD48may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or another deposition method. ILD48may also be formed of an oxygen-containing dielectric material, which may be a silicon-oxide based material such as silicon oxide, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), or the like. A planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process is performed to level the top surfaces of ILD48, dummy gate stacks30, and gate spacers38with each other.

FIG.5also illustrates the formation of hard masks50, which are used for protecting ILD48in subsequent processes. In accordance with some embodiments, the formation of hard mask50includes recessing ILD48(and possibly CESL46) to form recesses between neighboring gate spacers38, filling a dielectric layer to fill the recesses, and performing a planarization process (such as CMP process or a mechanical grinding process) to remove excess portions of the dielectric material. The remaining portions of the dielectric material are hard masks50. In accordance with some embodiments, hard masks50are formed of or comprise silicon nitride, silicon oxynitride, or the like.

FIG.6illustrates the formation of replacement gate stacks56. The respective process is illustrated as process212in the process flow200as shown inFIG.21. The formation process includes removing the dummy gate stacks30to form trenches, and forming replacement gate stacks56in the resulting trenches. Gate stacks56include gate dielectrics52and gate electrodes54. Gate dielectrics52may include interfacial layers and high-k dielectric layers over the interfacial layers. The interfacial layers may include silicon oxide. The high-k dielectric layers may include hafnium oxide, zirconium oxide, lanthanum oxide, and/or the like. Gate electrodes54may include work function layers comprising TiN, TiSiN, TaN, TiAlN, TiAl, and/or the like, and may or may not include filling metals formed of cobalt, tungsten, and/or the like. Accordingly, gate electrodes54are also referred to as metal gates54.

Next, the formation process proceeds to the cutting of gate stacks56and the cutting of protruding fins24′ in order to isolate transistors. The cutting of gate stacks56is referred to as a Cut Metal Gate (CMG) process. The cutting of protruding semiconductor fins24′ is referred to as a Continuous Metal On-Diffusion Edge (CMODE) process, or sometimes referred to as a Cut Metal on-Diffusion Edge (also CMODE) process. It is appreciated that in the illustrated example embodiments, a CMODE process is performed, in which the cutting of protruding semiconductor fins24′ is performed after the formation of replacement gate stacks56. In accordance with alternative embodiments. the cutting of protruding semiconductor fins24′ may be performed before the formation of replacement gate stacks56, and dummy gate stacks30(FIG.5) are cut. The corresponding process are thus referred to as a Continuous Poly On Diffusion Edge (CPODE) process or a Cut Poly On Diffusion Edge (CPODE) process.

Referring toFIG.7, replacement gate stacks56are recessed through etching processes to form recesses60, so that the height of replacement gate stacks56is reduced. The respective process is illustrated as process214in the process flow200as shown inFIG.21. In the etching process, hard masks50protect the underlying ILD48. In accordance with some embodiments, gate spacers38are also recessed as shown inFIG.7. In accordance with alternative embodiments, gate spacers38are not recessed.

Referring toFIG.8, hard mask64is formed. The respective process is illustrated as process216in the process flow200as shown inFIG.21. The formation process may include depositing a hard mask layer(s), and performing a planarization process such as a CMP process or a mechanical grinding process to level the top surface of hard mask64. Hard mask64extends into recesses60(FIG.7). In accordance with some embodiments, hard mask64is formed of a homogeneous material such as amorphous silicon. In accordance with alternative embodiments, hard mask64may be a composite layer including a plurality of layers. For example, hard mask layer64may include a first layer (which may be a conformal layer) and a second layer over the first layer. For example, the dashed lines represent the interface between the first layer and the second layer as an example. The first layer may be formed of or comprise silicon nitride, while the second layer may include amorphous silicon in accordance with some embodiments. Hard mask64may or may not include a third layer such as a silicon nitride layer deposited on the planarized second layer.

FIGS.9A,9B, and10illustrate a CMG process in accordance with some embodiments. As shown inFIG.9A, an etching process is performed. The etching process may include forming an etching mask (such as a photoresist or a tri-layer etching mask, not shown), patterning the etching mask, and etching hard masks64and50, ILD48. CESL46, and replacement gate stack56to form trenches66.

FIG.9Billustrates the cross-section9B-9B as shown inFIG.9A. Replacement gate stack56is cut apart into separate portions. The top surfaces of dielectric dummy fins25′ may be exposed to trenches66. The respective process is illustrated as process218in the process flow200as shown inFIG.21.

Referring toFIG.10, dielectric material68is deposited. The respective process is illustrated as process220in the process flow200as shown inFIG.21. In accordance with some embodiments, dielectric material68is formed of a homogeneous dielectric material such as silicon nitride, silicon oxide, or the like. In accordance with alternative embodiments, dielectric material68comprises a plurality of dielectric layers. For example, dielectric material68may comprise a dielectric liner formed of a first dielectric material, and a second dielectric material over the dielectric liner. The second dielectric material is different from the first dielectric material. For example, the first dielectric material may comprise silicon oxide, and the second dielectric material may comprise silicon nitride. Alternatively, the first dielectric material may comprise silicon nitride, and the second dielectric material may comprise silicon oxide.

The formation of dielectric material68includes depositing the dielectric material(s), and performing a planarization process to level the top surface of the dielectric material(s). In accordance with some embodiments, after the planarization process, a portion of the dielectric material68may be left overlapping hard mask64to act as a hard mask layer. In accordance with alternative embodiments, the planarization process is performed until the top surface of hard mask64is exposed, and another hard mask may be deposited on the remaining hard mask64. The portions of dielectric material68in trenches66(FIGS.9A and9B) are referred to as gate isolation regions70hereinafter, which are also referred to as CMG regions70. Some example gate isolation regions70are shown inFIG.16C, which illustrates a top view.

FIGS.11A,11B,11C,12A,12B,13A,13B,14A,14B,15A, and15Billustrate the intermediate stages in a CMODE process, in which fin isolation regions are formed to cut semiconductor strips and the underlying bulk portion of semiconductor substrate.

FIG.11Cillustrates a perspective view in the formation of etching mask72in accordance with some embodiments. The respective process is illustrated as process222in the process flow200as shown inFIG.21. Etching mask72may be a tri-layer, which may include bottom layer72B, middle layer72M over bottom layer72B, and top layer72T over middle layer72M. In accordance with some embodiments, bottom layer72B may comprise a carbon-containing dielectric material, a cross-linked photoresist, or the like. Middle layer72M may include an inorganic material such as silicon oxynitride. Top layer72T may comprise photoresist, which is patterned to form opening74. Middle layer72M and bottom layer72B are subsequently patterned using the patterned top layer72T as an etching mask.

FIGS.11A and11Billustrate the cross-sectional views of vertical cross-sections11A-11A and11B-11B, respectively ofFIG.11C. As shown inFIG.11A, opening74overlaps a part of each of the two dummy fins25′, and also overlaps the protruding semiconductor fins24′ in between. As shown inFIG.11B, opening74overlaps one of replacement gate stack56. In accordance with some embodiments, as shown inFIG.11B, a single opening74is formed, and on one or both sides of the opening74, there are a plurality of replacement gate stacks56with no openings74overlapping them. In accordance with alternative embodiments, a plurality of openings74(shown as being dashed) may be formed, each overlapping one of a plurality of neighboring replacement gate stacks56.

In subsequent processes, figures may be referred to using a number followed by letter “A” or “B.” The figures whose figure numbers including letter “A” are obtained from the same cross-section as the cross-section ofFIG.11A, and the figures whose figure numbers including letter “B” are obtained from the same cross-section as the cross-section ofFIG.11B.

Etching mask72is then used to etch the underlying dielectric material68, hard masks64, gate isolation regions70, and replacement gate stacks56, so that trenches76are formed extending into replacement gate stacks56. The respective process is illustrated as process224in the process flow200as shown inFIG.21. The resulting structure is shown inFIGS.12A and12B. In the etching process, top layer72T and middle layer72M (FIGS.11A and11B) may be consumed. Protruding semiconductor fins24′ are exposed. The etching may include a plurality of etching processes. For example, the etching of dielectric material68and hard mask layers64may be performed using CF4, CH2F2, CH3F, HF, O2, Ar, or combinations thereof, depending on the respective material. The etching of replacement gate stacks56may be performed using HCl, H2O2, and H2O, or the like, or combinations thereof. After the etching process, protruding semiconductor fins24′ are exposed.

Next, protruding fins24′ are etched. After the protruding fins24′ are removed, the underlying semiconductor strips24, which are between STI regions22, are also etched, resulting in trenches78. The respective process is illustrated as process226in the process flow200as shown inFIG.21. The resulting structure is shown inFIGS.13A and13B. The etching process is performed until the resulting trenches78have bottoms lower than the bottom surfaces22B of STI regions22. Accordingly, trenches78further extend into the bulk portion of substrate20below STI regions22. The details of the etching process will be discussed referring toFIGS.17and18. In accordance with some embodiments, as discussed in detail referring toFIGS.17and18, the etching process and/or the etching tool are selected, so that outmost trenches78L and78R have same depths or a same depth as inner trenches78.

FIG.13Billustrates a cross-sectional view of the structure shown inFIG.13A. In accordance with some embodiments, there is a single opening74, and hence there may be a single trench78. In accordance with alternative embodiments, a plurality of openings74are formed overlapping neighboring replacement gate stacks56, and hence a plurality of trenches78(shown as being dashed) are formed to be parallel to each other in the illustrated cross-section.

Next, trenches78and76are filled with dielectric material84, as shown inFIGS.14A and14B. The respective process is illustrated as process228in the process flow200as shown inFIG.21. In accordance with some embodiments, dielectric material84is formed of a homogeneous dielectric material such as silicon nitride, silicon oxide, or the like. In accordance with alternative embodiments, dielectric material84comprises a plurality of dielectric layers, which may be selected from the same group of candidate materials used for forming dielectric material68, the details are thus not discussed herein.

FIGS.15A and15Billustrate a planarization process to remove excess portions of dielectric material84. The respective process is illustrated as process230in the process flow200as shown inFIG.21. As a result, the remaining portions of dielectric material84are referred to as fin isolation regions86, which are also referred to as CMODE regions86. Fin isolation regions86include lower isolation regions (portions)86A, which extend into STI regions22and the bulk portion of semiconductor substrate20, and upper regions (portions)86B, which extends into gate stack56.

In accordance with some embodiments, as shown inFIGS.15A and15B, the planarization process is performed using hard mask64as a CMP stop layer, and hence the top surface of hard mask64are exposed. In accordance with alternative embodiments, the planarization process may be stopped at one of possible levels88as shown inFIG.15B. As shown by dashed lines86, there may also be a plurality of fin isolation regions86formed neighboring to each other as a group.

In subsequent processes, hard mask64is replaced with a dielectric material to form dielectric regions90, as shown inFIGS.16A and16B. Next, some upper features are formed, which include etch stop layer92, ILD94, and gate contact plugs96Source/drain silicide regions (not shown) and source/drain contact plugs (not shown) are also formed on top of source/drain regions42. The respective process is illustrated as process232in the process flow200as shown inFIG.21. FinFETs100are thus formed.

FIG.16Cillustrates a top view of the structure shown inFIGS.16A and16B.FIG.16Aillustrates the cross-section16A-16A inFIG.16C, except thatFIG.16Aillustrates two isolation regions86A, whileFIG.16Cillustrates six isolation regions86A.FIG.16Billustrates the cross-section16B-16B inFIG.16C. It is appreciated thatFIG.16Cillustrates a simplified layout showing how fin isolation regions86and gate isolations70may cut fins and gate stacks, respectively. The actual layout of fin isolation regions86and gate isolations70may be different from, and may be more complicated than, what is illustrated.

FIGS.17and18illustrate the magnified views of portion80inFIG.13Ain the etching of protruding semiconductor fins24′, semiconductor strips24, and the underlying bulk portion of semiconductor substrate20to form trenches76and78. In accordance with some embodiments, the etching process may be performed using HBr. O2, and Ar as process gases. In accordance with alternative embodiments, other process gases such as Bromine (Br2), C2F6, CF4, SO2, CH2F2, etc. may be used, or may be added into HBr, O2, and Ar as process gases. HBr and O2(and possibly other gases when used) are used for etching chemically. Ar may be used as a carrier gas, and may also remove the semiconductor material mechanically through sputtering.

In the etching process, by-products81are generated. By-products81have the function of passivating and protecting the sidewalls of the bulk portion of semiconductor substrate20, so that trenches78are more vertical. By-products81, however, have some side-effects. By-products81cause the slow-down of the etching process. Furthermore, by-products81cause the pattern-loading in the etching process. For example, it has been found that in the regions where trenches78have a higher density, by-products81are thinner (due to the more spreading of by-products81to greater surface areas), and hence higher etching rates are resulted, wherein the etching rate is the increase in depth of trenches78per unit time. Conversely, in the regions where trenches78have a lower density, by-products81are thicker (due to the less spreading of by-products81to smaller surface areas), and hence lower etching rates are resulted. Furthermore, when trenches78are longer (in the top view), the etching rate is also higher.

It is appreciated that the sidewall portions of by-products81on the sidewalls of substrate20cannot be too thin. Otherwise, the protection from the by-products81is too low, and lateral etching may be severe. This may cause the epitaxy regions42(FIG.13B) to be damaged. Accordingly, in accordance with embodiments of the present disclosure, by-products81are kept as having more uniform thicknesses throughout different trenches78to reduce the lateral etching.

Referring toFIG.17, trenches78form a trench group have a uniform pitch, or a substantially uniform pitch, with the pitch variation smaller than, for example,20percent. The trench group includes a leftmost trench78L and a rightmost trench78R. Throughout the description, the trenches between the outmost trenches78L and78R are referred to as inner trenches78I. The trench(es) in the middle of outmost trenches78L and78R are referred to as center trenches78C, which are also inner trenches78I. There is a single center trench78C when the total count of trenches78is an odd number, and there are two center trenches78C when the total count of trenches78is an even number.

The leftmost trench78L and the rightmost trench78R are in semi-dense regions because no trench is formed on one side of each of trenches78L and78R, while the other side has trenches. The inner trenches78I are in higher trench-density regions than the outmost trenches78L and78R. As a result, in conventional applications, trenches were found to have deepest center trench(es), and shallowest outmost trenches. From the center trench(es) to the outmost trenches, the depths of the trenches reduced gradually in conventional applications. This caused the outmost trenches and the resulting isolation regions formed therein to have smallest depths. Since the isolation regions are used for blocking leakage currents, their ability of blocking leakage currents is adversely affected.

In accordance with the embodiments of the present application, the etching tools and the etching process conditions are selected and adjusted to achieve deeper outmost trenches78L and78R (relative to the center trenches78C).FIG.20illustrates a schematic view of etching tool110in accordance with some embodiments. Etching tool110has wafer10therein, and is configured to etch wafer10in order to form trenches78.

Etching tool110includes top electrode112and bottom electrode116, with wafer10located in between. Plasma114is generated from the process gases therein in order to etch protruding semiconductor fins24′ (FIGS.13A and13B), semiconductor strips24, and substrate20.

Etching tool110includes chamber120, and inlet118, through which the process gases are conducted into chamber120. The process gases are pumped out of chamber120through outlet124, which is connected to pump126. Experiments have revealed that increasing the gas conductance of chamber120may result in the increase in the depths of the outer trenches relative to the depth of inner trenches. The effect of gas conductance may be related to the improved efficiency in the removal of by-products81(FIGS.17and18), and hence by-products81are thinner and have more uniform thickness in different trenches that have different depths, lengths, and densities.

A plurality of experiments have been performed to form trenches78on different wafers that have the same layout, with different conductance values used in the etching processes performed on different wafers. It has been found that with the increase in the gas conductance, the depth ratio Dom/Dce increases also, wherein Dom (FIG.18) is the depth of the outmost trenches78L and78R, while Dce is the depth of the center trenches78C. It has also been found that for the wafers etched using low gas conductance values, the corresponding depth ratios Dom/Dce of the trenches in the corresponding wafers are smaller than 1.0. When the gas conductance in etching a wafer equals to a threshold value, depth ratio Dom/Dce is increased to equal to 1.0. Further increasing the gas conductance, the depth ratios Dom/Dce of the corresponding wafers are further increased to be greater than 1.0. For example, depth ratio Dom/Dce of some wafers may be increased to a value greater than about 1.1, and may be in the range between about 1.0 and about 1.2.

In accordance with some embodiments, the threshold gas conductance (which is evaluated using flow rate/pressure ratio) corresponding to depth ratio Dom/Dce being equal to 1.0 is greater than about 20 sccm/mT, and may be in the range between about 15 sccm/mT and about 25 sccm/mT. Through the experiments, the desirable gas conductance that corresponds to the desirable profile of trenches (having the desirable Dom/Dce that is equal to or greater than 1.0) may be determined, and is used for the mass production of wafer10.

It is appreciated that increasing the gas conductance also results in the reduction in the pressure in chamber120. In accordance with some embodiments, the threshold chamber pressure in the etching process is about 30 mTorr when the threshold gas conductance is used. Accordingly, the chamber pressure in the etching process is lower than about 30 mTorr, and may be in the range between about 5 mTorr and about 30 mTorr.

To achieve the desirable gas conduction, the pumps of existing etching tools may be replaced with more powerful pumps. For example, pump126as shown inFIG.20may adopt a turbo pump. In accordance with some embodiments, with the increase in the gas conduction and the reduction in the chamber pressure, it is more difficult to generate plasma from etching gases. Accordingly, etching tool110may also adopt a mechanism that is more powerful in generating plasma. For example, Electron cyclotron Resonance (ECR) may be used to generate plasma, rather than Inductively Coupled Plasma (ICP).

In addition to gas conductance, other process conditions may also be adjusted to achieve higher depth ratios Dom/Dce. For example, the sputtering effect may also be increased to achieve more uniform depths of trenches78. In accordance with some embodiments, in the etching process, bias power is provided to increase the sputtering effect. The bias power may be turned on and off in cycles, and there may be a plurality of off-on cycles in the formation of trenches. For example, in an off-period of an off-on cycle, no bias power is provided for a first period of time T1. The sputtering effect is low during this period of time. In an on period of the off-on cycle, bias power is provided for a second period of time T2, so that the sputtering effect is high. During the off-on cycle, etching gases HBr, O2, and Ar etc. may be conducted continuously. To increase the sputtering effect, off/on ratio T2/T1is increased, so that depth ratios Dom/Dce are closer to 1.0.

It is realized that off/on ratio T2/T1cannot be too high and cannot be too Low. When off/on ratio T2/T1is too low, the effect of improving depth uniformity through sputtering effect is low. When off/on ratio T2/T1is too high, the bowing effect, which means that the middle portion of trenches78immediately underlying STI regions22are wider than the overlying portions and underlying portions, is adversely increased. In accordance with some embodiments, off/on ratio T2/T1may be in the range between about 0.25 and about 4.

The sputtering effect may also be increased by increasing the bias power. Again, the bias power cannot be too low or too high. Otherwise, either the sputtering effect is too low or the bowing is too severe. In accordance with some embodiments, the bias power may be in the range between about 20 watts and about 700 watts.

As shown inFIGS.17and18, with the proceeding of the etching of semiconductor substrate20, the depths of trenches78further increase, until desirable depths are reached, andFIG.18illustrates the trenches78when the etching process is finished. For example, the depths of trenches78may be in the range between about130nm and about170nm when the etching process is finished.

It is also realized that the etching of semiconductor of different portions may be adjusted to have adjusted process conditions. For example, in the initial stage of the etching such as the etching of protruding semiconductor fins24′ and semiconductor strips24, the trenches are wider, the non-uniformity in the thicknesses of by-products81is also not significant. Accordingly, the etching of protruding semiconductor fins24′ and semiconductor strips24may be performed using a first process condition. The subsequent etching of the bulk portion of semiconductor substrate20, however, suffers more from the thickness non-uniformity of by-products81. Accordingly, etching process conditions need to be carefully controlled to improve the thickness uniformity of by-products81. and a second process condition different from the first process condition may be used to etch the bulk portion of semiconductor substrate20.

In accordance with some embodiments, the first process condition includes a first off/on ratio T2/T1, a first bias power, a first gas conductance value, and a first chamber pressure. The second process condition includes a second off/on ratio T2/T1, a second bias power, a second gas conductance value, and a second chamber pressure. In accordance with some embodiments, the second off/on ratio T2/T1is greater than the first T2/T1ratio, and/or the second bias power is greater than the first bias power. The first gas conductance value may be smaller than the second gas conductance value. The first chamber pressure may be higher than the second chamber pressure.

FIG.18illustrates the profiles of the bottoms of trenches78in accordance with some embodiments. The outmost trenches78L and78R have the depths Dom equal to or greater than the depth of at least one inner trench. The bottoms of trenches78may be aligned to a horizontal straight line130in accordance with some embodiments. In accordance with alternative embodiments, the bottoms of trenches78may also be aligned to the straight line130substantially, for example, with the greatest average depth difference among trenches78being smaller than about 5 nm. In accordance with yet alternative embodiments, as represented by dashed line132, from the outmost trench78R to the center trench78C, the bottoms of some trenches78are aligned to a straight and slant straight line. There may also be some variations, with one of the outmost trenches78L and78R being deeper than a first inner trench7878I, but shallower than a second inner trench78I. Dashed line134illustrates another profile, wherein the outmost trenches78L and78R are the deepest, and the center trench (es)78C are the shallowest. From the outmost trenches78L and78R to the center trenches78C, the depths of trenches78may reduce gradually.

FIG.19illustrates a magnified view of a portion80′ inFIG.16A, wherein the isolation regions86have a total count greater than two. Similarly, dashed lines130,132, and134are drawn to show different possible profiles of bottoms of isolation regions86. Isolation region86include upper portion86B and lower portions86A. Lower portions86A include outmost parts86AL and86AR, inner parts86AI, and center part(s)86AC, which fill outmost parts78L and78R, inner parts78I, and center part(s)78C, respectively.

The embodiments of the present disclosure have some advantageous features. By selecting the etching tool and process conditions for etching semiconductor fins and the underlying bulk portions of semiconductor substrate, fin isolation regions (for cutting semiconductor fins) may have deeper outmost isolation regions, thus improving their ability of blocking leakage current.

In accordance with some embodiments, a method comprises forming a gate stack on a semiconductor region, wherein the semiconductor region is over a bulk semiconductor substrate; etching the gate stack to form a first trench, wherein a plurality of protruding semiconductor fins are revealed to the first trench; etching the plurality of protruding semiconductor fins to form a plurality of second trenches extending into the bulk semiconductor substrate, wherein the plurality of second trenches are underlying and joined to the first trench, and wherein the plurality of second trenches comprise a first outmost trench having a first depth; a second outmost trench; and an inner trench between the first outmost trench and the second outmost trench, wherein the inner trench has a second depth equal to or smaller than the first depth; and forming a fin isolation region filling the first trench and the plurality of second trenches.

In an embodiment, the structure further comprises, before the etching the gate stack to form the plurality of second trenches, etching the gate stack to form a third trench, wherein a dummy fin is underlying and exposed to the third trench; and forming a gate isolation region filling the third trench. In an embodiment, in the etching the plurality of protruding semiconductor fins, a pressure of a respective etching chamber is lower than about 30 mTorr. In an embodiment, in the etching the plurality of protruding semiconductor fins, a plasma is generated from a respective etching gas using ECR. In an embodiment, the second depth is equal to the first depth. In an embodiment, the second depth is smaller than the first depth.

In an embodiment, the etching the gate stack to form the first trench comprises forming a hard mask layer, wherein both of the first trench and the plurality of second trenches are formed using the hard mask layer as parts of an etching mask. In an embodiment, the hard mask layer comprises amorphous silicon. In an embodiment, the plurality of second trenches comprise a plurality of inner trenches between the first outmost trench and the second outmost trench, and wherein the first outmost trench and the second outmost trench are deeper than all inner trenches in the plurality of inner trenches. In an embodiment, the plurality of inner trenches comprise a center trench in middle between the first outmost trench and the second outmost trench, and wherein trenches from the center trench to the first outmost trench have increasingly greater depths.

In accordance with some embodiments, a structure comprises a semiconductor region; a gate stack on the semiconductor region, wherein the gate stack comprises a first gate stack portion and a second gate stack portion; and a fin isolation region separating the first gate stack portion from the second gate stack portion, wherein the fin isolation region comprises a first part higher than a bottom surface of the gate stack; and a plurality of second parts underlying and joined to the first part, wherein a first outmost part in the plurality of second parts has a first depth equal to or greater than a second depth of an inner part in the plurality of second parts. In an embodiment, the first depth is equal to the second depth.

In an embodiment, the first depth is greater than the second depth. In an embodiment, the plurality of second parts further comprise a second outmost part; and a center part in middle between the first outmost part and the second outmost part, wherein from the center part to the first outmost part, heights of the plurality of second parts increase gradually. In an embodiment, the structure further comprises a gate isolation region penetrating through the gate stack, wherein the fin isolation region contacts the gate isolation region. In an embodiment, the fin isolation region extends into the gate isolation region.

In accordance with some embodiments, a structure comprises a semiconductor substrate; dielectric isolation regions extending into the semiconductor substrate; a plurality of semiconductor fins protruding higher than the dielectric isolation regions and parallel to each other; a gate stack over the plurality of semiconductor fins; a plurality of source/drain regions extending into the plurality of semiconductor fins; and a dielectric isolation region contacting sidewalls of the plurality of semiconductor fins, wherein the gate stack and the plurality of source/drain regions are on opposite sides of the plurality of source/drain regions, wherein the dielectric isolation region comprises an upper part; and a plurality of lower parts underlying and joined to the upper part, wherein outer parts in the plurality of lower parts are deeper than inner parts in the plurality of lower parts. In an embodiment, an outmost part in the plurality of lower parts is deepest among the plurality of lower parts. In an embodiment, a center part in the plurality of lower parts is shallowest among the plurality of lower parts.