Data processing apparatus providing cyclic addressing of a data store in selectively opposite directions

A data processing apparatus in which a memory (10) is accessed at addresses stored in an address regiser (20). An incrementation circuit (38) successively increments or decrements the address stored in the principal register, under the control of an address cycling circuit (22). A pair of auxiliary registers (30, 35) respectively store the minimum and maximum address values to be reached in the principal register, and a comparison circuit (37) determines when the address therein matches the minimum or maximum value. The address cycling circuit, together with the comparison circuit, loads the principal register with the minimum address value when the address therein reaches the maximum value, the address therein thereafter being decremented, and loads it with the maximum address value when the address therein reaches the minimum value, the address therein thereafter being incremented. Such operation is particularly useful for preforming the functions of a fixed or adaptive transversal filter for data transmission, the data stored in the memory being the filter coefficients.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The invention relates to a data processing apparatus, comprising an 
addressing arrangement for supplying a memory with address codes 
originating from a variable-content principal register to which are 
connected an incrementation circuit for modifying the content of the 
principal register and a loading circuit. The addressing arrangement 
comprises two auxiliary registers, one of which serves to store the 
minimum value to be reached by the content of the principal register while 
the other auxiliary register serves to store the maximum value to be 
reached by the principal register. A comparison circuit determines when 
the content of the principal register reaches the minimum and maximum 
values. 
2. Description of the Related Art 
Such a apparatus is widely used, notably for performing the functions of a 
fixed or adaptive transversal data transmission filter. At successive 
addresses the memory contains different samples in digital form of the 
signal to be filtered. For processing of the signal it is necessary to 
address the memory locations containing these samples cyclically, so as to 
simulate a shift register in RAM-type memory. 
Apparatus of the kind set forth is described in the article "An LSI Signal 
Processor" by M. Yano, K. Inoue and T. Senba in volume 2 of IEEE 
International Conference of Acoustics, Speech and Signal Processing, held 
in Paris, France on May 3, 4, 5, 1982. 
In the known apparatus the comparison circuit compares the content of the 
principal register with that of the auxiliary register containing the 
maximum value. Consequently, the content of the principal register must 
always be modified in the same direction in practice. 
SUMMARY OF THE INVENTION 
The present invention has for its object to provide a data processing 
apparatus of the kind set forth which enables modification of the content 
of the principal register in both direction. 
To this end, the data processing apparatus in accordance with the invention 
is characterised in that the loading circuit which cooperates with the 
comparison circuit serves to load the principal register with the minimum 
value when it contains the maximum value and with the maximum value when 
it contains the minimum value. 
An important advantage of the invention consists in that the addressing 
arrangement is very well suitable for operation with processors operating 
in the pipeline mode. In this mode of operation the results arrive with a 
delay because of the pipe-line effect. The use of the pipeline mode in 
filtering algorithms necessitates the execution of two operations on the 
same data at two different instants, which implies that the principal 
register must be incremented and decremented at will; therefore, the 
present invention can be used even in the vicinity of the maximum and 
minimum address code values, thereby providing increased flexibility for 
the choice of a memory section to be used. 
An important feature of the invention is that the addressing arrangement 
can cooperate with a microprocessor system comprising an instruction bus 
and a data bus and is provided with connection means between the output of 
the principal register and the data bus in order to save the content of 
the principal register in the memory of the microprocessor system, thus 
enabling the realization of the functions of several independent 
transversal filters by means of the same system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The data processing apparatus shown in FIG. 1 is intended to cooperate with 
a microprocessor system 2. This system operates on the basis of 
instructions transported via a bus BUSI and originating from a register 
RI; data (results of calculations performed by the system 2) appear on a 
bus BUSD. The apparatus 1 supplies an address code for a memory 10 on its 
output 5. This code originates from a register 20 which is referred to as 
the principal register and whose content can be modified under the control 
of a loading circuit 22. To this end, a loading signal LAD for the 
register 20 is supplied from the circuit 22. 
The apparatus 1 comprises two auxiliary registers, one of which is denoted 
by the reference numeral 30 and serves to store the mimimum value 
wherefrom the content of the principal register can be modified, while the 
auxiliary register (35) serves to store the maximum value to be reached by 
the principal register. There is also provided a comparison circuit 37 
which cooperates with the loading circuit 22. An input of this circuit 37 
is connected to the parallel outputs of the register 20. An incrementation 
circuit which is formed essentially by an adder 38 is used to vary the 
value stored in the memory 10 by .+-..DELTA.. A latch-type register 39 
serves as an interface between the outputs of the register 20 and the 
output 5 which is connected to the address code input of the memory 10. 
This register 39 is set to the conductive state by the value "0" of a 
signal .phi.1. 
In accordance with the invention, the loading circuit 22 cooperating with 
the comparison circuit 37 serves to load the principal register 20 with 
the minimum value (stored in the auxiliary register 30) when its content 
has reached the maximum value, and with the maximum value (stored in the 
auxiliary register 35) when its content has reached the minimum value. 
The loading and incrementation operations are performed by means of a first 
multiplexer 40 which comprises four inputs E1, E2, E3 and E4. The input E1 
is connected to the output S of a dual-input multiplexer 44, the input E2 
to the instruction bus BUSI, the input E3 to the data bus BUSD, and the 
input E4 to the output of the adder circuit 38. The connection of one of 
these inputs E1 to E4 to the output S of the multiplexer 44 is controlled 
by two commands MUX 41, MUX 42. The inputs E1 and E2 of the multiplexer 44 
are combined with the inputs E1 and E2 of a further multiplexer 46. The 
inputs E1 of the multiplexers 44 and 46 are connected to the parallel 
outputs of the register 35, and the inputs E2 of the multiplexers 44 and 
46 are connected to the outputs of the register 30. The parallel inputs of 
the registers 20, 30 and 35 are all connected to the output S of the 
multiplexer 40. The multiplexers 44 and 46 are controlled by a signal C3 
for the multiplexer 46 and by the signal C3 obtained via the logic signal 
inverter 49. Thus, for one value C3 there is connection between the input 
E1 and the output S of the multiplexer 46, while a connection is 
established between the input E2 and the output S of the multiplexer 44 
for the other value of C3. 
The parallel outputs of the register 20 are connected, as has already been 
stated, to a first input of the comparator 37 whose second input is 
connected to the output S of the multiplexer 46. 
The invention thus provides the means for cyclically addressing the 
addresses in memory 10, which means that using simple instructions for 
incrementing the memory counter by .DELTA., one progresses from the 
maximum address value ADM to the minimum address value Adm, i.e. 
sequentially: ADm, ADm+.DELTA., . . . ADM -.DELTA., ADM, ADm, ADm+.DELTA. 
. . . or from the minimum address value ADm to the maximum address value 
ADM, ADM-.DELTA., . . . ADm+.DELTA., ADm, ADM, ADM-.DELTA.. .DELTA. may 
have the typical values: 0, 1 . . . . 
The adder circuit 38, whose operands are defined, for example by 7 bits, 
comprises a carry input "R". A value .DELTA..sub.2 is applied to "R" and 
to the six most significant inputs for an operand, and the seventh input 
receives the value .DELTA..sub.1. The seven inputs for the other operand 
are connected to the parallel outputs of the register 20. 
The parallel outputs of the register 20 are also connected to the bus BUSD 
via a group of tri-state amplifiers 52 which are controlled by a signal 
SVG. The content of the register 20 can thus be saved in a location of a 
memory MEM forming part of the microprocessor 2. This enables the 
execution of several independent treatments. In the intended application, 
the functions of several transversal filters can be performed. 
A clock 70 supplies the signals which control the processing speed of the 
microprocessor 2. From this clock 70 there are derived two periodic 
signals: the signal .phi.1 which determines the rate of appearance of the 
instructions on the bus BUSI and a signal F0 whose frequency is twice that 
of the former signal. These signals are used by the loading circuit 22. 
The loading circuit 22 is formed by a programmed logic array 80 which 
supplies the signals S1 to S6, C3, SVG, .DELTA.1 and .DELTA.2 on the basis 
of the data transported by the bus BUSI and the signal FO. Three AND-gates 
81, 82 and 83 supply the loading signals LMAX, LMIN, and LAD for the 
registers 35, 30 and 20. Two of the three inputs of these gates receive 
the signal .phi.1 and FO while the third input of these gates 81, 82 and 
83 receives the signals S1, S2, and S3, respectively. A fourth AND-gate 84 
receives the signal S4 on one of its inputs and its other input receives 
the signal CMP from the output of the comparator 37. Two OR-gates 85 and 
86 supply the codes MUX 41 and MUX 42; one input of these gates is 
connected to the output of the gate 84, the other input of these gates 85 
and 86 receiving the signals S5 and S6, respectively. 
The array 80 is programmed so that the following logic equations are 
realized: 
EQU S.sub.1 =I.sub.0.I.sub.1.I.sub.2.I.sub.3.I.sub.4 
EQU S.sub.2 =I.sub.0.I.sub.1.I.sub.2.I.sub.3.I.sub.4 
EQU S.sub.3 =I.sub.0.I.sub.1.I.sub.2.I.sub.28.I.sub.29.I.sub.31 
+I.sub.0.I.sub.1.I.sub.3 
EQU S.sub.4 =I.sub.0.I.sub.1.I.sub.3.I.sub.25 
EQU S.sub.5 =I.sub.0.I.sub.1.I.sub.2.+I.sub.0.I.sub.1 
EQU S.sub.6 =I.sub.0.I.sub.1 +I.sub.0.I.sub.1 
EQU C.sub.3 =I.sub.0.I.sub.1.I.sub.24 
EQU SVG=(I.sub.0.I.sub.1.I.sub.2.I.sub.3.I.sub.4.I.sub.5.I.sub.6.I.sub.8.I.sub. 
9)..phi. 
EQU .DELTA..sub.1 =I.sub.0.I.sub.1.I.sub.25.I.sub.24 
+I.sub.0.I.sub.1.I.sub.25.I.sub.24 
EQU .DELTA..sub.2 =I.sub.0.I.sub.1.I.sub.24 
The symbol "." indicates a logic AND-operation in these equations, and the 
symbol "+" indicates a logic OR-operation. The variables I.sub.i represent 
the values of the bits transported by the bus BUSI. 
For a proper understanding of the invention, the following Table I states 
the connections established by the multiplexers 44 and 46 as a function of 
signal the value of a signal C3, while Table II states the connections 
established by the multiplexer 40 as a function of the codes MUX 41 and 
MUX 42. 
TABLE I 
______________________________________ 
Connections Connections 
C.sub.3 multiplexer 46 
multiplexer 44 
______________________________________ 
0 E.sub.1 -S E.sub.2 -S 
1 E.sub.2 -S E.sub.1 -S 
______________________________________ 
TABLE II 
______________________________________ 
MUX 41 MUX 42 Connection 
______________________________________ 
0 0 E.sub.1 -S 
0 1 E.sub.2 -S 
1 0 E.sub.3 -S 
1 1 E.sub.4 -S 
______________________________________ 
For an explanation of the operation of the apparatus in accordance with the 
invention, use is made of the various instructions J0, J1, J2, J3 and J4 
shown in FIG. 2. All instructions in question are formed by thirty-two 
bits denoted as I.sub.o to I.sub.31. 
In order to initialize the apparatus 1, it is necessary to use the 
instructions J0 and J1 which are characterised by I.sub.0 =I.sub.1 
=I.sub.2 =1, I.sub.3 =I.sub.4 =0 for J0 and by I.sub.0 =I.sub.1 =I.sub.2 
=1, I.sub.3 =0, I.sub.4 =1 for J1, respectively. The instructions J0 and 
J1 enable the loading of the registers 30 and 35 with the values "MIN" and 
"MAX", respectively, determined by means of the bits I.sub.13 to I.sub.19. 
For the loading of the register 20 use is made of the instruction J2 which 
is characterised by I.sub.0 =1, I.sub.1 =I.sub.2 =0, I.sub.28 =1, I.sub.29 
=0, and I.sub.31 =1. 
The value loaded into the register 20 arrives via the bus BUSD and may be 
any value between ADMIN and ADMAX at the start of processing. 
When the same system is used for the realization of the functions of 
several transversal filters in timesharing, the value to be stored in 
register 20 is fetched for each filter from the memory MEM of the 
microprocessor and at the end of processing the content of the register 20 
is returned to the memory for the next period. 
The instruction J3 provides incrementation values .DELTA. which are 
determined by the bit I.sub.25 and whose positive or negative sign is 
given by the value of the bit I.sub.24. The instruction J4 is used to save 
the content of the register 20 in the memory MEM. The instructions J3 and 
J4 are characterised by I.sub.0 and I.sub.1 equal to "0" to J3, and 
I.sub.0 =1, I.sub.1 =0, I.sub.2 =1, I.sub.3 =I.sub.4 =0, I.sub.5 =1, 
I.sub.6 =0 for J4. The operation of the addressing element will now be 
described with reference to the time diagram shown in FIG. 3. 
The instructions J0, J1, J2 . . . J3 . . . J4 arrive in the register R1 
shortly after the negative-going edge of the signal .phi.1. 
At the instant t.sub.o, the instruction J0 is decoded and the signals MUX 
41 and MUX 42 assume a value such that the transmission of E.sub.2 to S is 
established inside the multiplexer 40; at the instant t.sub.1 the register 
30 is loaded with the output data of the multiplexer 40. 
During the next cycle, the instruction J1 is decoded and the position of 
the multiplexer 40 remains in the position for transmitting E.sub.2 to its 
output S. Subsequently, at the instant t.sub.2 the register 35 is loaded 
with the maximum value which can be reached by the register 20. During the 
next cycle the transmission of E.sub.3 to S is established by the 
multiplexer 40 under the influence of decoding of the instruction J2. At 
the instant t.sub.3 the register 20 is loaded with the output data of the 
multiplexer 40. 
The addressing element is initialized for the supply of addresses as from 
the instant t.sub.3. 
The decoding of the instruction J3 results in a code MUX 41 and MUX 42 such 
that the transmission of E.sub.4 to S is established. In the described 
example the register 20 is allowed to be incremented by positive values. 
After a given number of incrementation steps, at the instant t.sub.4 the 
register 20 will contain a maximum value which is equal to the value 
stored in the register 35 and the signal CMP will assume the value 1. For 
the next instruction it is assumed that the desired incrementation is 
always positive. This condition, taking into account the value "1" of the 
signal CMP, results in the minimum loading of the register 20 with the 
value, which is stored in the register 30, at the instant t.sub.5. To this 
end, the multiplexer 40 establishes the transmission of E.sub.1 to S and 
the multiplexer 44 establishes the connection E.sub.2 -S, while the 
transmission of E.sub.1 to S is established inside the multiplexer 46. 
When the functions of another filter are to be realized, it will be 
necessary, as stated before, to save the content of the register 20 in the 
memory of the microprocessor 2. To this end use is made of the instruction 
J4 which, when decoded, makes the signal SVG assume the value 1 at the 
instant t.sub.6 ; the outputs of the register 20 are connected to the bus 
BUSD via the register 39 and the group 52.