Method of fabricating a semiconductor device having self-aligned floating gate and related device

A semiconductor device such as a flash memory device having a self-aligned floating gate and a method of fabricating the same is provided. An embodiment of the device includes an isolation layer defining a fin body is formed in a semiconductor substrate. The fin body has a portion protruding above the isolation layer. A sacrificial pattern is formed on the isolation layer. The sacrificial pattern has an opening self-aligned with the protruding portion of the fin body. The protruding fin body is exposed in the opening. An insulated floating gate pattern is formed to fill the opening. The sacrificial pattern is then removed. An inter-gate dielectric layer covering the floating gate pattern is formed. A control gate conductive layer is formed over the inter-gate dielectric layer. The control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern are patterned to form a control gate electrode crossing the fin body as well as the insulated floating gate interposed between the control gate electrode and the fin body.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 2005-0101509, filed Oct. 26, 2005, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to a semiconductor device such as a nonvolatile memory device and a method of fabricating the same, and more particularly, to a flash memory device having a self-aligned floating gate and a method of fabricating the same.

2. Description of the Related Art

In general, semiconductor memory devices storing data can be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices lose data stored in them when power is cut off, while nonvolatile memory devices retain stored data even when the power is cut off. Accordingly, nonvolatile memory devices, such as flash memory devices, are widely used in mobile storage devices, mobile telecommunication systems, and other devices that may experience power loss.

Meanwhile, as the size and power consumption of electronic systems are gradually reduced, the required integration density of flash memory devices increases. Consequently, gates constituting a unit cell of a flash memory device should also be scaled down. One technique proposed in recent years to scale down the gates includes forming floating and control gates on an active region of a fin structure to fabricate the flash memory cell.

A typical technique in forming a floating gate employs a conventional patterning process. The patterning process requires a process margin to prepare for potential alignment errors in a photolithography process. In other words, there are many limitations in fabricating the scaled-down floating gate. In order to cope with alignment error, a technique of foaming the floating gate using self-align technology has been researched.

A nonvolatile memory device having the fin structure and a method of fabricating the same are disclosed in U.S. Pat. No. 6,657,252 B2 entitled “FinFET CMOS with NVRAM capability” to Fried et al. According to Fried et al., an insulated floating gate is disposed on the sidewalls of a fin body, and an insulated control gate is disposed to cover the floating gate. Further, Fried et al. provides an example where the floating gate can be formed self-aligned with the fin body. The floating gate is formed by forming a polysilicon layer covering the fin body and then anisotropically etching the polysilicon layer. In this case, the thickness of the floating gate can depend on the height of the fin body and the deposition thickness of the polysilicon layer. However, there is a limitation in adjusting the thickness of the floating gate.

Another method of fabricating a nonvolatile memory device is disclosed in US Patent Publication No. 2004-0099900 entitled “Semiconductor Device and Method of Manufacturing the same” to Iguchi et al.

Nevertheless, techniques of forming a flash memory device having a self-aligned floating gate require continuous improvement.

SUMMARY

Embodiments of the invention provide a memory device having a self-aligned floating gate and a method of fabricating the same.

In one embodiment, the invention is directed to a method of fabricating a flash memory device having a self-aligned floating gate. The method includes forming an isolation layer to define a fin body in a semiconductor substrate. The fin body is formed to have a first sidewall, a second sidewall facing the first sidewall, and a top surface. The fin body also has a portion protruding above the isolation layer. The isolation layer has a sacrificial pattern formed thereon. The sacrificial pattern has an opening self-aligned with the protruding portion of the fin body. The protruding fin body is exposed in the opening. An insulated floating gate pattern is formed to fill the opening. The sacrificial pattern is then removed. An inter-gate dielectric layer covering the floating gate pattern is formed. A control gate conductive layer is formed over the inter-gate dielectric layer. The control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern are patterned to form a control gate electrode crossing the fin body as well as a floating gate interposed between the control gate electrode and the fin body.

DETAILED DESCRIPTION

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. In addition, when a layer is described as being formed “on” another layer or substrate that layer may be formed directly on the other layer or substrate, or a third layer may be interposed between the layer and the other layer or substrate. Like numbers refer to like elements throughout the specification.

FIG. 1is a perspective view showing a part of a nonvolatile memory device such as a flash memory device according to a first embodiment of the present invention.FIGS. 2 to 11are cross-sectional views taken along line I-I′ ofFIG. 1, illustrating a method of fabricating a memory device according to the first embodiment of the present invention. Further,FIG. 12is a; perspective view showing a part of a memory device according to a second embodiment of the present invention, andFIGS. 13 to 19are cross-sectional views taken along line II-II′ ofFIG. 12, illustrating a method of fabricating a memory device according to the second embodiment of the present invention.

A method of fabricating a memory device according to a first embodiment of the present invention will now be described with reference toFIGS. 1 to 11.

Referring toFIGS. 1 and 2, a trench52defining a fin body53is formed in a predetermined region of a semiconductor substrate51.

Specifically, a mask layer may be formed on the semiconductor substrate51. The mask layer may be patterned to expose the predetermined region of the semiconductor substrate51; thus forming a hard mask pattern55. The semiconductor substrate51may be a silicon wafer. The hard mask pattern55may comprise a nitride layer, such as a silicon nitride layer, by a chemical vapor deposition (CVD) method.

Before the mask layer is formed, a pad oxide layer54may be formed on the semiconductor substrate51. The pad oxide layer54may comprise a thermal oxide layer. The pad oxide layer54may release physical stress due to a difference in thermal expansion coefficient between the semiconductor substrate51and the mask layer. The pad oxide layer54may be patterned together with the hard mask pattern55and thus remain under the hard mask pattern55. Alternatively, the pad oxide layer54may be omitted.

The semiconductor substrate51is then anisotropically etched using the hard mask pattern55as an etch mask thus forming the trench52defining the fin body53. The fin body53may have a first sidewall11, a second sidewall22opposite the first sidewall11, and a top surface33.

Referring toFIGS. 1 and 3, an insulating layer such as a silicon oxide layer is formed on the semiconductor substrate51having the trench52, and then planarized until the hard mask pattern55is exposed. As a result, a preliminary isolation layer57may be formed in the trench52. The planarization may be performed by a chemical mechanical polishing (CMP) process or an etch-back process, for example.

Referring toFIGS. 1 and 4, the preliminary isolation layer57is partially removed to form an isolation layer57′.

The process of partially removing the preliminary isolation layer57may be performed by an oxide layer etching process. The preliminary isolation layer57may have an etch selectivity with respect to the hard mask pattern55and the semiconductor substrate51. In other words, the preliminary isolation layer57may be selectively removed by the oxide layer etching process. As a result, the preliminary isolation layer57is recessed with respect to the top surface33of the fin body53to form the isolation layer57′. The isolation layer57′ may be formed to fill a lower region of the trench52. In other words, a portion of the fin body53may protrude above the isolation layer57′. The protruding portion of the fin body53may expose a portion of the first and second sidewalls11and22.

Referring toFIGS. 1 and 5, sacrificial insulating layers such as sacrificial oxide layers61may be formed on the exposed first and second sidewalls11and22of the fin body53.

The sacrificial oxide layers61may comprise a silicon oxide layer by thermal oxidation or CVD. When the sacrificial oxide layers61are formed by thermal oxidation, the sacrificial oxide layers61may be formed to cover the exposed first and second sidewalls11and22. When the sacrificial oxide layers61are formed by CVD, the sacrificial oxide layers61may be formed to cover substantially the entire surface of the semiconductor substrate51.

A sacrificial spacer layer63may be formed on the semiconductor substrate51having the sacrificial oxide layers61. The sacrificial spacer layer63is preferably formed of the same material layer as the hard mask pattern55. For example, the sacrificial spacer layer63and the hard mask pattern55may comprise a nitride layer such as a silicon nitride layer, by CVD. Further, the sacrificial spacer layer63may be formed to uniformly cover the protruding first and second sidewalls11and22of the fin body53.

Referring toFIGS. 1 and 6, a sacrificial layer is formed on the semiconductor substrate51having the sacrificial spacer layer63. The sacrificial layer may be formed to fill the trench52and cover the semiconductor substrate51. The sacrificial layer may comprise a material layer having an etch selectivity with respect to the sacrificial spacer layer63and the hard mask pattern55. For example, the sacrificial layer may comprise a silicon oxide layer.

The sacrificial layer may be planarized until a top surface of the sacrificial spacer layer63is exposed, thereby forming a sacrificial pattern65. The planarization is carried out by a CMP process using the sacrificial spacer layer63as a CMP stop layer. Alternatively, the planarization may be carried out by an etch-back process. As a result, top surfaces of the sacrificial pattern65and the sacrificial spacer layer63may be exposed on substantially the same plane. Further, the top surface of the sacrificial pattern65may be formed higher than the hard mask pattern55.

Referring toFIGS. 1 and 7, the sacrificial spacer layer63and the hard mask pattern55are selectively removed to form a preliminary opening73.

The process of selectively removing the sacrificial spacer layer63and the hard mask pattern55may be performed by a nitride layer etching process. The nitride layer etching process has a high etch selectivity between a nitride layer and an oxide layer. That is, the nitride layer etching process shows a high etch rate with respect to the sacrificial spacer layer63and the hard mask pattern55. The process of removing the sacrificial spacer layer63and the hard mask pattern55may be performed until the isolation layer57′ is exposed from the bottom of the preliminary opening73. In this case, the sacrificial oxide layers61, the pad oxide layer54, and the isolation layer57′ may be exposed in the preliminary opening73. Further, the sacrificial spacer layer63may be partially left between the sacrificial pattern65and the isolation layer57′.

As describe above, the preliminary opening73is formed by removing the sacrificial spacer layer63and the hard mask pattern55without a photolithography process. Thus, the preliminary opening73may be formed self-aligned with the protruding fin body53.

Referring toFIGS. 1 and 8, the preliminary opening73may be expanded to form an opening73′. The expanded opening73′ may be formed to separate the first sidewall11from the sacrificial pattern65by a first distance D1, and separate the second sidewall22from the sacrificial pattern65by a second distance D2.

The process of expanding the preliminary opening73may be performed by an oxide layer etching process until the protruding fin body53is exposed. In this case, the top surface33, the first sidewall11, and the second sidewall22of the protruding fin body53may be exposed in the opening73′. The sacrificial pattern65and the isolation layer57′ may also be partially etched. The top surface of the sacrificial pattern65may be formed higher than the protruding fin body53. Here, the opening73′ may also be formed self-aligned with the protruding fin body53.

The oxide layer etching process shows substantially the same etch rate with respect to the same material layer. Specifically, the portion of the sacrificial pattern65facing the first sidewall11and the portion of the sacrificial pattern65facing the second sidewall22may be etched at substantially the same etch rate. Thus, the first and second distances D1and D2may be substantially equal to each other. In addition, when the oxide layer etching process is performed throughout the semiconductor substrate51at the same time, the first and second distances D1and D2may be substantially equal throughout the semiconductor substrate51. Consequently, it is possible to control the openings73′ formed on the semiconductor substrate51to have substantially the same size.

Referring toFIGS. 1 and 9, a tunnel dielectric layer75may be formed on the exposed fin body53. The tunnel dielectric layer75may comprise a silicon oxide layer or a high-k dielectric layer such as an HfO2or ZrO2layer.

Subsequently, a floating gate layer may be formed to fill the opening73′ and cover the semiconductor substrate51. The floating gate layer may be planarized to form a floating gate pattern77in the opening73′. The floating gate layer may comprise a polysilicon layer. The process of planarizing the floating gate layer may be performed by a CMP process using the sacrificial pattern65as a stop layer. Alternatively, the process of planarizing the floating gate layer may be performed by an etch-back process. The floating gate pattern77may be formed to have a generally flat top surface.

The shape of the floating gate pattern77may depend on the size and shape of the opening73′. The floating gate pattern77may be formed to a first thickness D1′ on the first sidewall11, and a second thickness D2′ on the second sidewall22. The first and second thicknesses D1′ and D2′ may be determined by the first and second distances D1and D2, respectively. In other words, the first and second thicknesses D1′ and D2′ may be substantially equal to each other. Further, the first and second thicknesses D1′ and D2′ may be substantially equal to each other throughout the semiconductor substrate51.

Referring toFIGS. 1 and 10, the sacrificial pattern65and the sacrificial spacer layer63are removed to expose sidewalls and a top surface of the floating gate pattern77. The process of removing the sacrificial pattern65may be performed by an oxide layer etching process having an etch selectivity with respect to the floating gate pattern77. The process of removing the sacrificial spacer layer63may be performed by a nitride layer etching process. As a result, the sidewalls and top surface of the floating gate pattern77may be exposed.

As a result, grooves79may be formed between the floating gate patterns77. The isolation layer57′ may be exposed at the bottom of each groove79. The isolation layer57′ may also be etched such that the bottom of the groove79is located lower than the floating gate pattern77.

Referring toFIGS. 1 and 11, an inter-gate dielectric layer81covering the floating gate pattern77is formed on the resulting structure.

The inter-gate dielectric layer81may be formed to surround the floating gate pattern77at a substantially uniform thickness and to cover the semiconductor substrate51. The inter-gate dielectric layer81may comprise a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a high-k dielectric layer, or a combination layer thereof. For example, the inter-gate dielectric layer81may comprise an ONO (Oxide-Nitride-Oxide) layer.

A control gate conductive layer may be formed on substantially the entire surface of the semiconductor substrate51having the inter-gate dielectric layer81. The control gate conductive layer may comprise a polysilicon layer. The control gate conductive layer, the inter-gate dielectric layer81, and the floating gate pattern77are continuously patterned to form a control gate electrode87crossing the fin body53. Further, a floating gate77F is formed between the control gate electrode87and the fin body53.

While the control gate conductive layer is formed, a control gate extension87E may be formed in the groove79. The control gate extension87E may be formed to contact the control gate electrode87. Here, the size of the control gate extension87E may depend on the depth of the groove79. When the bottom of the groove79is formed lower than the floating gate patterns77, a lower end of the control gate extension87E may also be formed lower than the floating gate77F. In other words, the lower end of the control gate extension87E may be formed to penetrate into the isolation layer57═. In this case, the control gate extension87E may prevent parasite capacitance from being generated between the floating gates77F.

Now, a method of fabricating a flash memory device according to a second embodiment of the present invention will be described with reference toFIGS. 12 to 19.

Referring toFIGS. 12 and 13, a fin body53, a pad oxide layer54, a hard mask pattern55, an isolation layer57′, a sacrificial oxide layer61, and a sacrificial spacer layer63are formed on a semiconductor substrate51, as in the method of fabricating the flash memory device according to the first embodiment of the present invention.

The sacrificial spacer layer63may be anisotropically etched to form a sacrificial spacer63′ that covers sidewalls of the hard mask pattern55and first and second sidewalls11and22of the fin body53. The process of anisotropically etching the sacrificial spacer layer63may be performed until the isolation layer57′ is exposed in the trench52. In this case, a top surface of the hard mask pattern55may also be exposed.

Referring toFIGS. 12 and 14, a sacrificial layer may be formed on the semiconductor substrate51having the sacrificial spacer63′ in the same or similar manner as described with reference toFIG. 6. The sacrificial layer may be formed to fill the trench52and cover the semiconductor substrate51. The sacrificial layer may comprise a material layer having an etch selectivity with respect to the sacrificial spacer63′ and the hard mask pattern55. For example, the sacrificial layer may comprise a silicon oxide layer.

The sacrificial layer may be planarized until the hard mask pattern55is exposed, thereby forming a sacrificial pattern65. At this time, the sacrificial spacer63′ may also be exposed between the sacrificial pattern65and the hard mask pattern55. The planarization may be carried out by a CMP process using the hard mask pattern55as a stop layer. Alternatively, the planarization may be carried out by an etch-back process. As a result, top surfaces of the sacrificial pattern65and the hard mask pattern55may be exposed on substantially the same plane. Further, the top surface of the sacrificial pattern65may be formed higher than the fin body53.

Referring toFIGS. 12 and 15, the sacrificial spacer63′ and the hard mask pattern55are selectively removed to form a preliminary opening74.

The process of selectively removing the sacrificial spacer63′ and the hard mask pattern55may be performed by a nitride layer etching process. Here, while the nitride layer etching process is performed, the sacrificial oxide layer61, the pad oxide layer54, and the isolation layer57′ are not removed in part because of their low etch selectivity. That is, the nitride layer etching process has a sufficient process margin to remove the sacrificial spacer63′ and the hard mask pattern55. As a result, the sacrificial oxide layer61, the pad oxide layer54, and the isolation layer57′ may be exposed in the preliminary opening74. Further, the preliminary opening74may be formed in the same shape as both the sacrificial spacer63′ and the hard mask pattern55.

As mentioned above, the preliminary opening74may be formed by removing the sacrificial spacer63′ and the hard mask pattern55without a photolithography process. Thus, the preliminary opening74may be formed self-aligned with the protruding fin body53. Referring toFIGS. 12 and 16, the preliminary opening74may be expanded to form an opening74′.

The process of expanding the preliminary opening74may be performed by an oxide layer etching process until the protruding fin body53is exposed. In this case, the top surface33, the first sidewall11, and the second sidewall22of the protruding fin body53may be exposed in the opening74′. The sacrificial pattern65and the isolation layer57′ may also be partially etched. The top surface of the sacrificial pattern65may be formed to be higher than the protruding fin body53. Here, the opening74′ may also be formed self-aligned with the protruding fin body53.

The oxide layer etching process shows substantially the same etch rate with respect to the same material layer. Specifically, the sacrificial pattern65facing the first sidewall11and the sacrificial pattern65facing the second sidewall22may be etched at substantially the same etch rate. At the lower region of the opening74′, the opening74′ may be formed to separate the first sidewall11from the sacrificial pattern65by a first distance D5, and the second sidewall22from the sacrificial pattern65by a second distance D6. Thus, the first and second distances D5and D6may be substantially equal to each other. Furthermore, when the oxide layer etching process is performed throughout the semiconductor substrate51at the same time, the first and second distances D5and D6may be substantially equal throughout the semiconductor substrate51.

Here, the shape of the opening74′ may be determined by the sacrificial spacer63′ and the hard mask pattern55. The sacrificial spacer63′ may be formed in such a manner that its upper portion has a thickness smaller than that of its lower portion. Thus, a third distance D3between an upper edge of the first sidewall11and the sacrificial pattern65facing the upper edge may be shorter than the first distance D5. Similarly, a fourth distance D4between an upper edge of the second sidewall22and the sacrificial pattern65facing the upper edge may also be shorter than the second distance D6. Because of the uniform etching rate the third and fourth distances D3and D4may be substantially equal to each other. Consequently, it is possible to control the openings74′ formed on the semiconductor substrate51to have substantially the same size.

Referring toFIGS. 12 and 17, a tunnel dielectric layer75may be formed on the exposed fin body53. The tunnel dielectric layer75may comprise a silicon oxide layer or a high-kdielectric layer.

Subsequently, a floating gate layer may be formed to fill the opening74′ and cover the semiconductor substrate51. The floating gate layer may be planarized to form a floating gate pattern77′ in the opening74′. The floating gate layer may comprise a polysilicon layer. The process of planarizing the floating gate layer may be performed by a CMP process using the sacrificial pattern65as a stop layer. Alternatively, the process of planarizing the floating gate layer may be performed by an etch-back process. The floating gate pattern77′ may have a flat top surface.

The lower end of the floating gate pattern77′ may be formed to a first thickness D5′ on the first sidewall11, and to a second thickness D6′ on the second sidewall22. The first and second thicknesses D5′ and D6′ may be determined by the first and second distances D5and D6, respectively. In other words, the first and second thicknesses D5′ and D6′ may be substantially equal to each other. Further, the first and second thicknesses D5′ and D6′ may be substantially equal throughout the semiconductor substrate51.

In addition, the floating gate pattern77′ may be formed to a third thickness D3′ at an upper edge of the first sidewall11, and a fourth thickness D4′ at an upper edge of the second sidewall22. The third thickness D3′ may be smaller than the first thickness D5′ and the fourth thickness D4′ may be smaller than the second thickness D6′. The third and fourth thicknesses D3′ and D4′ may also be substantially equal to each other.

Referring toFIGS. 12 and 18, the sacrificial pattern65is removed to expose the sidewalls and top surface of the floating gate pattern77′. The process of removing the sacrificial pattern65may be performed by an oxide layer etching process having an etch selectivity with respect to the floating gate pattern77′. In this case, grooves79may be formed between the floating gate patterns77′. The isolation layer57′ may be exposed at the bottom of each groove79. The isolation layer57′ may also be etched such that the bottom of each groove79is located lower than the floating gate pattern77′.

Subsequently, an inter-gate dielectric layer81covering the floating gate pattern77′ is formed.

The inter-gate dielectric layer81may be formed to surround the floating gate pattern77′ at a substantially uniform thickness and to cover the semiconductor substrate51. The inter-gate dielectric layer81may comprise a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a high-k dielectric layer, or a combination layer thereof. For example, the inter-gate dielectric layer81may comprise an ONO (Oxide-Nitride-Oxide) layer.

Referring toFIGS. 12 and 19, a control gate conductive layer may be formed on substantially the entire surface of the semiconductor substrate51having the inter-gate dielectric layer81. The control gate conductive layer may comprise a polysilicon layer. The control gate conductive layer, the inter-gate dielectric layer81, and the floating gate pattern77′ are continuously patterned to form a control gate electrode87crossing the fin body53. Further, a floating gate77F is formed between the control gate electrode87and the fin body53.

While the control gate conductive layer is formed, a control gate extension87E may be formed in the groove79. The control gate extension87E may be formed to contact the control gate electrode87. Here, the size of the control gate extension87E may be determined by the depth of the groove79. When the bottom of the groove79is formed lower than the floating gate patterns77′, a lower end of the control gate extension87E may also be formed lower than the floating gates77′F. In other words, the lower end of the control gate extension87E may be formed to penetrate into the isolation layer57′. In this case, the control gate extension87E may prevent parasite capacitance from being generated between the floating gates77′F.

Hereinafter, a flash memory device according to a first embodiment of the present invention will be described with reference toFIGS. 1 and 11.

Referring toFIGS. 1 and 11again, an isolation layer57′ defining a fin body53is provided in a predetermined region of a semiconductor substrate51.

The semiconductor substrate51may be a silicon wafer. The fin body53has a first sidewall11, a second sidewall22facing the first sidewall11, and a top surface33. A portion of the fin body53protrudes above the isolation layer57′. A plurality of fin bodies53may be disposed parallel to each other within the semiconductor substrate51. The isolation layer57′ may be an insulating layer such as a silicon oxide layer.

A control gate electrode87crossing over the fin body53is provided. A floating gate77F, which is self-aligned with the protruding portion of the fin body53, is disposed between the control gate electrode87and the fin body53. A tunnel dielectric layer75may be interposed between the fin body53and the floating gate77F. An inter-gate dielectric layer81may be interposed between the floating gate77F and the control gate electrode87.

The floating gate77F may cover portions of the first and second sidewalls11and22, and the top surface33of the protruding fin body53. The floating gate77F may have a flat top surface. The floating gate77F has a first thickness D1′ on the first sidewall11, and a second thickness D2′ on the second sidewall22. The first thickness D1′ may be substantially equal to the second thickness D2′. Further, the first and second thicknesses D1′ and D2′ may be substantially equal throughout the semiconductor substrate51. The floating gate77F may be a polysilicon layer.

The control gate electrode87may be disposed across all the fin bodies53. In this case, the floating gates77F may be disposed between the control gate electrode87and each of the fin bodies53. A control gate extension87E contacting the control gate electrode87may be provided between the floating gates77F. A lower end of the control gate extension87E may be located lower than the floating gates77F. In other words, the lower end of the control gate extension87E may be disposed to penetrate into the isolation layer57′. The control gate extension87E may prevent parasite capacitance from being generated between the floating gates77F. Both the control gate electrode87and the control gate extension87E may be polysilicon layers.

The tunnel dielectric layer75may be a silicon oxide layer or a high-k dielectric layer. The inter-gate dielectric layer81may comprise a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a high-k dielectric layer, or a combination layer thereof. For example, the inter-gate dielectric layer81may be an ONO (Oxide-Nitride-Oxide) layer.

Hereinafter, a flash memory device according to a second embodiment of the present invention will be described with reference toFIGS. 12 and 19.

Referring toFIGS. 12 and 19again, an isolation layer57′ defining a fin body53is provided in a predetermined region of a semiconductor substrate51. The fin body53has a first sidewall11, a second sidewall22facing the first sidewall11, and a top surface33. A portion of the fin body53protrudes above the isolation layer57′. A plurality of fin bodies53may be disposed parallel to each other within the semiconductor substrate51.

A control gate electrode87crossing over the fin body53is provided. A floating gate77′F, which is self-aligned with the protruding portion of the fin body53, is disposed between the control gate electrode87and the fin body53. A tunnel dielectric layer75may be interposed between the fin body53and the floating gate77′F. An inter-gate dielectric layer81may be interposed between the floating gate77′F and the control gate electrode87.

The floating gate77′F may cover the first and second sidewalls11and22and the top surface33of the protruding fin body53. The floating gate77′F may have a flat top surface. A lower end of the floating gate77′F may be formed to a first thickness D5′ on the first sidewall11, and a second thickness D6′ on the second sidewall22. The first thickness D5′ may be substantially equal to the second thickness D6′. Further, the first and second thicknesses D5′ and D6′ may be substantially equal throughout the semiconductor substrate51.

In addition, the floating gate77′F may be formed to a third thickness D3′ at an upper edge of the first sidewall11, and to a fourth thickness D4′ at an upper edge of the second sidewall22. The third thickness D3′ may be smaller than the first thickness D5′ and the fourth thickness D4′ may be smaller than the second thickness D6′. The third thickness D3′ may also be substantially equal to the fourth thickness D4′. The floating gate77′F may be a polysilicon layer.

The control gate electrode87may be disposed across all the fin bodies53. In this case, the floating gates77′F may be disposed between the control gate electrode87and each of the fin bodies53. A control gate extension87E contacting the control gate electrode87may be provided between the floating gates77′F. A lower end of the control gate extension87E may be located lower than the floating gates77′F. That is, the lower end of the control gate extension87E may be disposed to penetrate into the isolation layer57′. The control gate extension87E may prevent parasite capacitance from being generated between the floating gates77′F. Both the control gate electrode87and the control gate extension87E may be polysilicon layers.

The tunnel dielectric layer75may be a silicon oxide layer or a high-k dielectric layer. The inter-gate dielectric layer81may comprise a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a high-k dielectric layer, or a combination layer thereof. For example, the inter-gate dielectric layer81may be an ONO (Oxide-Nitride-Oxide) layer.

As described above, according to the present invention, a sacrificial spacer is formed on sidewalls of a fin body. The sacrificial spacer is selectively removed to expose the fin body, and thus a sacrificial pattern having an opening is formed. The opening is formed to a desired size. A floating gate pattern is formed to fill the opening. Thus, the floating gate pattern is self-aligned with the fin body. The opening can be adjusted in size, and thus the floating gate pattern can be adjusted in thickness. The sacrificial pattern is removed to form a groove between the floating gate patterns. An inter-gate dielectric layer covering the floating gate pattern is formed. A control gate conductive layer is formed on substantially the entire surface of the semiconductor substrate having the inter-gate dielectric layer. The control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern are continuously patterned to form a control gate electrode crossing the fin body as well as a floating gate interposed between the control gate electrode and the fin body. Consequently, it is possible to realize a flash memory device having the self-aligned floating gate on an upper region of the fin body.