Control circuits of collector current of substrate bipolar junction transistors and circuits of compensating for base current for generating a proportional to absolute temperature (PTAT) voltage using the control circuits

A circuit for controlling a collector current of a substrate bipolar junction transistor (BJT) is provided. The circuit includes a first current mirror configured to generate a first mirroring base current corresponding to a replicate current of a base current of the substrate BJT, a current transmitter configured to transmit the first mirroring base current, a second current mirror configured to generate a second mirroring base current corresponding to a replicate current of the first mirroring base current received from the current transmitter and configured to supply the second mirroring base current to an emitter of the substrate BJT, and a current source configured to supply a drive current corresponding to a collector current of the substrate BJT to the emitter of the substrate BJT.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. 119(a) to Korean Application No. 10-2016-0083617, filed on Jul. 1, 2016, which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments of the present disclosure relate to circuits having substrate bipolar junction transistors, and more particularly, to control circuits of collector currents of substrate bipolar junction transistors and circuits for compensating base currents for generating a proportional to absolute temperature (PTAT) voltage using the control circuits.

2. Related Art

In general, bipolar junction transistors (BJTs) are well known as circuit elements having an excellent junction characteristic as compared with metal-oxide-semiconductor (MOS) transistors. The BJTs may be required in some semiconductor circuits to execute a specific function. Thus, it may be necessary to realize a semiconductor including the MOS transistors and the BJTs using a single process technology. A bipolar-complementary MOS (BiCMOS) process technology has been widely used to integrate CMOS elements and BJTs into a single device. However, the BiCMOS process technology may involve high fabrication costs and a long development time. Moreover, if the BJTs are realized using a CMOS process technology, characteristics of the BJTs may be degraded. Particularly, if substrate BJTs are realized using a CMOS process technology, it may be difficult to directly control a collector current of the substrate BJTs because collectors of the substrate BJTs are disposed in a substrate. Accordingly, circuits for controlling the collector current of the substrate BJTs may be required in various circuits such as temperature sensors or reference voltage generators.

SUMMARY

Various embodiments are directed to control circuits of collector currents of substrate BJTs and circuits of compensating for base currents for generating a PTAT voltage using the control circuits.

According to an embodiment, there is provided a circuit for controlling a collector current of a substrate BJT. The circuit includes a first current mirror configured to generate a first mirroring base current corresponding to a replicate current of a base current of the substrate BJT, a current transmitter configured to transmit the first mirroring base current, a second current mirror configured to generate a second mirroring base current corresponding to a replicate current of the first mirroring base current received from the current transmitter and configured to supply the second mirroring base current to an emitter of the substrate BJT, and a current source configured to supply a drive current corresponding to a collector current of the substrate BJT to the emitter of the substrate BJT.

According to another embodiment, there is provided a circuit for compensating a base current for generating a PTAT voltage. The circuit includes a first current mirror configured to supply a first collector current corresponding to a collector current of a first substrate bipolar junction transistor (BJT) to an emitter of the first substrate BJT, a second current mirror configured to generate a first mirroring base current corresponding to a replicate current of a base current of the first substrate BJT, a current transmitter configured to transmit the first mirroring base current, a third current mirror configured to generate a second mirroring base current corresponding to a replicate current of the first mirroring base current received from the current transmitter to supply the second mirroring base current to the emitter of the first substrate BJT and configured to generate a third mirroring base current having an amount which is equal to “N” (wherein, “N” denotes a natural number which is greater than one) times an amount of the first mirroring base current to supply the third mirroring base current to an emitter of a second substrate BJT, and a second collector current transmitter configured to supply a second collector current to the emitter of the second substrate BJT where the second collector current amount is equal to “N” times an amount of the first collector current.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present disclosure will be described below with reference to the accompanying drawings through various embodiments.

The present disclosure, however, may be embodied in various different forms, and should not be construed as being limited to the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey various aspects and features of the present disclosure to those skilled in the art.

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments.

In addition, when an element is referred to as being located “on”, “over”, “above”, “under”, or “beneath” another element, it is intended to mean relative positional relationship, but not be used to limit certain cases that the element directly contacts the other element, or at least one intervening element is present therebetween. Accordingly, the terms such as “on”, “over”, “above”, “under”, “beneath”, “below” and the like that are used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the present disclosure. Further, when an element is referred to as being “connected” or “coupled” to another element, the element may be electrically or mechanically connected or coupled to the other element directly, or may form a connection relationship or coupling relationship by replacing the other element therebetween.

FIG. 1is circuit diagram illustrating a circuit100for controlling a collector current of a substrate BJT according to an embodiment. Referring toFIG. 1, the circuit100may be configured to include a substrate BJT Q, a first current mirror110, an operational amplifier120, a current transmitter130, a second current mirror140, and a current source150. A base of the substrate BJT Q may be coupled to the first current mirror110. An emitter of the substrate BJT Q may be coupled to the second current mirror140and the current source150. A collector of the substrate BJT Q may be coupled to a ground terminal. In some embodiments, the substrate BJT Q may be a PNP BJT. Alternatively, the substrate BJT Q may be an NPN BJT. In the event that the substrate BJT Q is an NPN BJT, each of MOS transistors described in this embodiment may be construed to have an opposite channel type.

The first current mirror110may include a first NMOS transistor NM1and a second NMOS transistor NM2. The first and second NMOS transistors NM1and NM2may have the same current drivability. For example, the first and second NMOS transistors NM1and NM2may have the same transconductance (Gm). A gate of the first NMOS transistor NM1may be coupled to a gate of the second NMOS transistor NM2, and a gate bias voltage VG may be applied to the gates of the first and second NMOS transistors NM1and NM2. Sources of the first and second NMOS transistors NM1and NM2may be coupled to the ground terminal. A drain of the first NMOS transistor NM1may be coupled to the base of the substrate BJT Q and a non-inverting input terminal of the operational amplifier120. A drain of the second NMOS transistor NM2may be coupled to an inverting input terminal of the operational amplifier120and the current transmitter130. The first current mirror110may be realized so that a drain voltage of the first NMOS transistor NM1is equal to a drain voltage of the second NMOS transistor NM2. Thus, a base current Ibof the substrate BJT Q may flow through the first NMOS transistor NM1, and a first mirroring base current Ib1corresponding to a duplicate current of the base current Ibmay flow through the second NMOS transistor NM2.

The operational amplifier120may be used in equalization of the drain voltages of the first and second NMOS transistors NM1and NM2constituting the first current mirror110. Specifically, the operational amplifier120may be disposed to provide a negative feedback loop so that an output signal of the operational amplifier120is applied to the current transmitter130. The operational amplifier120and the current transmitter130may operate to equalize a voltage of the inverting input terminal of the operational amplifier120with a voltage of the non-inverting input terminal of the operational amplifier120. Thus, the inverting input terminal and the non-inverting input terminal of the operational amplifier120may have the same voltage level. As a result, the drains of the first and second NMOS transistors NM1and NM2may have the same voltage level.

The current transmitter130may include a first PMOS transistor PM1. A gate of the first PMOS transistor PM1of the current transmitter130may be coupled to an output terminal of the operational amplifier120. A source of the first PMOS transistor PM1may be coupled to the second current mirror140. A drain of the first PMOS transistor PM1may be coupled to the drain of the second NMOS transistor NM2and the inverting input terminal of the operational amplifier120. The first PMOS transistor PM1may be disposed so that the operational amplifier120constitutes a negative feedback loop. In addition, the first PMOS transistor PM1of the current transmitter130may be disposed to transmit the first mirroring base current Ib1to the second current mirror140, where the first mirroring base current Ib1may be generated by the first current mirror110.

The second current mirror140may include a second PMOS transistor PM2and a third PMOS transistor PM3. A gate of the second PMOS transistor PM2may be coupled to a gate of the third PMOS transistor PM3. Sources of the second and third PMOS transistors PM2and PM3may be coupled to a supply voltage VDD terminal. A drain of the second PMOS transistor PM2may be coupled to the source of the first PMOS transistor PM1constituting the current transmitter130. The second PMOS transistor PM2may have a diode-connected structure in which the gate and the drain of the second PMOS transistor PM2are connected to each other. A drain of the third PMOS transistor PM3may be coupled to the emitter of the substrate BJT Q. In some embodiments, the second and third PMOS transistors PM2and PM3may have the same current drivability. For example, the second and third PMOS transistors PM2and PM3may have the same transconductance (Gm). The third PMOS transistor PM3may generate a second mirroring base current Ib2corresponding to a duplicate current of the first mirroring base current Ib1flowing through the second PMOS transistor PM2.

The current source150may be coupled to the emitter of the substrate BJT Q. The current source150may supply a drive current Idriveto the emitter of the substrate BJT Q. Accordingly, the second mirroring base current Ib2generated by the second current mirror140and the drive current Idriveoutputted from the current source150may be supplied to the emitter of the substrate BJT Q.

An operation of the circuit100for controlling a collector current of the substrate BJT Q will be described hereinafter. First, if the supply voltage VDD and the drive current Idriveare applied to the circuit100, the base current Ibof the substrate BJT Q may flow through the first NMOS transistor NM1of the first current mirror110. Because the operational amplifier120constitutes a negative feedback loop, the drains of the first and second NMOS transistors NM1and NM2may have the same voltage level. As a result, the first mirroring base current In, corresponding to a duplicate current (i.e., a replicate current) of the base current Ibof the substrate BJT Q, may flow through the second NMOS transistor NM2. If the first mirroring base current Ib1flows through the second NMOS transistor NM2, the first mirroring base current Ib1may also flow through the second PMOS transistor PM2due to the presence of the first PMOS transistor PM1of the current transmitter130.

The first mirroring base current Ib1may be replicated in the second current mirror140to generate the second mirroring base current Ib2flowing through the third PMOS transistor PM3. The second mirroring base current Ib2generated by the third PMOS transistor PM3and the drive current Idriveoutputted from the current source150may flow into the emitter of the substrate BJT Q. The second mirroring base current Ib2may correspond to a replicate current of the base current Ibof the substrate BJT Q. Thus, an amount of the second mirroring base current Ib2may be substantially equal to an amount of the base current Ibof the substrate BJT Q. As a result, the collector current Icof the substrate BJT may correspond to the drive current Idrive. For example, a collector current Icof the substrate BJT Q may be the same as the drive current Idriveoutputted from the current source150. That is, even though the base current Ibof the substrate BJT Q varies according to a temperature or the like, the collector current Icof the substrate BJT Q may be controlled by adjusting the drive current Idriveoutputted from the current source150regardless of the variation of the base current Ibof the substrate BJT Q.

FIG. 2is a circuit diagram illustrating a circuit200for compensating base currents for generating a PTAT voltage according to an embodiment. Referring toFIG. 2, the compensation circuit200according to an embodiment may be configured to include a first substrate BJT Q1, a second substrate BJT Q2, a current source210, a first current mirror220, a second current mirror230, an operational amplifier240, a current transmitter250, a third current mirror260, and a second collector current transmitter270. In some embodiments, the first and second substrate BJTs Q1and Q2may be integrated on the same substrate and may be formed to have the same area. It may be necessary to realize the first and second substrate BJTs Q1and Q2so that a current density of the second substrate BJT Q2is different from a current density of the first substrate BJT Q1to generate the PTAT voltage. The circuit200according to the present embodiment may be realized so that a base current (i.e., a second base current Ib2) of the second substrate BJT Q2is equal to “N” (wherein, “N” denotes a natural number which is greater than one throughout the specification) times a base current (i.e., a first base current Ib1) of the first substrate BJT Q1, and a collector current (i.e., a second collector current Ic2) of the second substrate BJT Q2is equal to “N” times a collector current (i.e., a first collector current Ic1) of the first substrate BJT Q1using the circuit100described with reference toFIG. 1.

The first substrate BJT Q1may have a first emitter, a first base, and a first collector. The first emitter of the first substrate BJT Q1may be coupled to the first current mirror220and the third current mirror260, and a first base of the first substrate BJT Q1may be coupled to the second current mirror230. In addition, the first collector of the first substrate BJT Q1may be coupled to a ground terminal. The second substrate BJT Q2may have a second emitter, a second base, and a second collector. The second emitter of the second substrate BJT Q2may be coupled to the third current mirror260and the second collector current transmitter270, and second collector of the second substrate BJT Q2may be coupled to the ground terminal. In some embodiments, the first and second substrate BJTs Q1and Q2may be PNP BJTs. Alternatively, the first and second substrate BJTs Q1and Q2may be NPN BJTs. If the first and second substrate BJTs Q1and Q2are NPN BJTs, each of MOS transistors described in this embodiment may be construed to have an opposite channel type.

The first current mirror220may include a first PMOS transistor PM21and a second PMOS transistor PM22. A gate of the first PMOS transistor PM21may be coupled to a gate of the second PMOS transistor PM22. A source and a drain of the first PMOS transistor PM21may be coupled to a supply voltage VDD terminal and one end of the current source210, respectively. The other end of the current source210may be coupled to the ground terminal. The current source210may be disposed so that a bias current Ibiasgenerated by the current source210flows into the ground terminal. The first PMOS transistor PM21may have a diode-connected structure in which the gate and the drain of the first PMOS transistor PM21are connected to each other. A source and a drain of the second PMOS transistor PM22may be coupled to the supply voltage VDD terminal and the first emitter of the first substrate BJT Q1, respectively. The first current mirror220may generate a first collector current Ic1, and the first collector current Ic1may be supplied to the first emitter of the first substrate BJT Q1.

The second current mirror230may include a first NMOS transistor NM21and a second NMOS transistor NM22. The first and second NMOS transistors NM21and NM22may have the same current drivability. For example, the first and second NMOS transistors NM21and NM22may have the same transconductance (Gm). A gate of the first NMOS transistor NM21may be coupled to a gate of the second NMOS transistor NM22, and a gate bias voltage VG may be applied to the gates of the first and second NMOS transistors NM21and NM22. Sources of the first and second NMOS transistors NM21and NM22may be coupled to the ground terminal. A drain of the first NMOS transistor NM21may be coupled to the first base of the first substrate BJT Q1and a non-inverting input terminal of the operational amplifier240. A drain of the second NMOS transistor NM22may be coupled to an inverting input terminal of the operational amplifier240and the current transmitter250. The second current mirror230may be realized so that a drain voltage of the first NMOS transistor NM21is equal to a drain voltage of the second NMOS transistor NM22. Thus, a first base current Ib1of the first substrate BJT Q1may flow through the first NMOS transistor NM21, and a first mirroring base current Ib1′corresponding to a duplicate current (i.e., a replicate current) of the first base current Ib1may flow through the second NMOS transistor NM22.

The operational amplifier240may be used in equalization of the drain voltages of the first and second NMOS transistors NM21and NM22of the second current mirror230. Specifically, the operational amplifier240may be disposed to provide a negative feedback loop so that an output signal of the operational amplifier240is applied to the current transmitter250. The operational amplifier240and the current transmitter250may operate to equalize a voltage of the inverting input terminal of the operational amplifier240with a voltage of the non-inverting input terminal of the operational amplifier240. Thus, the inverting input terminal and the non-inverting input terminal of the operational amplifier240may have the same voltage level. As a result, the drains of the first and second NMOS transistors NM21and NM22may have the same voltage level.

The current transmitter250may be realized using a third PMOS transistor PM23. A gate of the third PMOS transistor PM23of the current transmitter250may be coupled to an output terminal of the operational amplifier240. A source of the third PMOS transistor PM23may be coupled to the third current mirror260. A drain of the third PMOS transistor PM23may be coupled to the drain of the second NMOS transistor NM22and the inverting input terminal of the operational amplifier240. The third PMOS transistor PM23may be disposed so that the operational amplifier240constitutes a negative feedback loop. In addition, the third PMOS transistor PM23may be disposed to transmit the first mirroring base current Ib1′to the third current mirror260, where the first mirroring base current Ib1′is generated by the second current mirror230.

The third current mirror260may include a fourth PMOS transistor PM24, a fifth PMOS transistor PM25, and a sixth PMOS transistor PM26. In some embodiments, the fourth PMOS transistor PM24may have the same current drivability as the fifth PMOS transistor PM25. In contrast, the sixth PMOS transistor PM26may have a current drivability which is equal to “N” times a current drivability of the fifth PMOS transistor PM25. For example, a transconductance (Gm) of the sixth PMOS transistor PM26may be equal to “N” times a transconductance (Gm) of the fifth PMOS transistor PM25. Gates of the fourth, fifth, and sixth PMOS transistors PM24, PM25, and PM26may be coupled to each other. A source and a drain of the fourth PMOS transistor PM24may be coupled to the supply voltage VDD terminal and the first emitter of the first substrate BJT Q1, respectively. A source and a drain of the fifth PMOS transistor PM25may be coupled to the supply voltage VDD terminal and the source of the third PMOS transistor PM23, respectively. The fifth PMOS transistor PM25may have a diode-connected structure in which the gate and the drain of the fifth PMOS transistor PM25are connected to each other. A source and a drain of the sixth PMOS transistor PM26may be coupled to the supply voltage VDD terminal and the second emitter of the second substrate BJT Q2, respectively. The first mirroring base current Ib1′transmitted to the fifth PMOS transistor PM25may cause a second mirroring base current Ib1″replicated by the fourth PMOS transistor PM24and a third mirroring base current Ib1′″replicated by the sixth PMOS transistor PM26. In such a case, the second mirroring base current Ib1″may be replicated to have the same amount as the first mirroring base current Ib1′but the third mirroring base current I1′″may be replicated to have an amount which is equal to “N” times the first mirroring base current Ib1′.

The second collector current transmitter270may be configured to include a seventh PMOS transistor PM27. In some embodiments, the seventh PMOS transistor PM27may have a current drivability which is equal to “N” times a current drivability of the second PMOS transistor PM22. For example, a transconductance (Gm) of the seventh PMOS transistor PM27may be equal to “N” times a transconductance (Gm) of the second PMOS transistor PM22. A gate of the seventh PMOS transistor PM27may be coupled to the gates of the first and second PMOS transistors PM21and PM22. A source and a drain of the seventh PMOS transistor PM27may be coupled to the supply voltage VDD terminal and the second emitter of the second substrate BJT Q2, respectively. The second collector current transmitter270may supply a second collector current Ic2(N×Ic1), which is equal to “N” times the first collector current Ic1of the first substrate BJT Q1, to the second emitter of the second substrate BJT Q2.

The second base of the second substrate BJT Q2may be coupled to the ground terminal through a third NMOS transistor NM23. The third NMOS transistor NM23may have a current drivability which is equal to “N” times the current drivability of the second NMOS transistor NM22. For example, a transconductance (Gm) of the third NMOS transistor NM23may be equal to “N” times a transconductance (Gm) of the second NMOS transistor NM22. A gate of the third NMOS transistor NM23may be coupled to the gates of the first and second NMOS transistors NM21and NM22, and the gate bias voltage VG may also be applied to the gate of the third NMOS transistor NM23. A drain and a source of the third NMOS transistor NM23may be coupled to the second base of the second substrate BJT Q2and the ground terminal, respectively. The third NMOS transistor NM23may provide a current path through which the second base current Ib2(N×Ib1) flows into the ground terminal.

An operation of the circuit200according to an embodiment will be described hereinafter. First, if the supply voltage VDD and the bias current Ibiasare applied to the circuit200, a collector current Icmay flow through the first NMOS transistor PM21and the first collector current Incorresponding to a replicate current of the collector current Icmay flow through the second NMOS transistor PM22. The first collector current Ic1may be substantially the same amount as the collector current Ic. However, in some embodiments, an amount of the first collector current Ic1may be different than an amount of the collector current Ic. The first collector current Ic1may be supplied to the first emitter of the first substrate BJT Q1. In the present embodiment, the current source210and the first current mirror220may have a similar function to the current source150of the circuit100described with reference toFIG. 1. That is, the first collector current Ic1may be controlled by adjusting the bias current Ibiasgenerated by the current source210.

The first base current Ib1of the first substrate BJT Q1may flow into the first NMOS transistor NM21of the second current mirror230. Because the operational amplifier240provides a negative feedback loop, the drains of the first and second NMOS transistors NM21and NM22may have the same voltage level. Thus, the first mirroring base current Ib1′corresponding to a duplicate current (i.e., a replicate current) of the first base current Ib1may flow through the second NMOS transistor NM22. If the first mirroring base current Ib1′flows through the second NMOS transistor NM22, the first mirroring base current Ib1′may also flow through the fifth PMOS transistor PM25due to the presence of the third PMOS transistor PM23of the current transmitter250, and the current transmitter250may be configured to transmit the first mirroring base current Ib1′.

The first mirroring base current Ib1′may be replicated by the fourth PMOS transistor PM24of the third current mirror260to generate the second mirroring base current Ib1′flowing through the fourth PMOS transistor PM24. The second mirroring base current Ib1″generated by the fourth PMOS transistor PM24and the first collector current Ic1generated by the second PMOS transistor PM22may flow into the first emitter of the first substrate BJT Q1. The second mirroring base current Ib1″may correspond to a replicate current of the first base current Ib1of the first substrate BJT Q1. Thus, an amount of the second mirroring base current Ib1″may be substantially equal to an amount of the first base current Ib1of the first substrate BJT Q1. As a result, the first collector current Ic1of the first substrate BJT Q1may be substantially the same amount as the first collector current Ic1flowing through the second PMOS transistor PM22. That is, even though the first base current Ib1of the first substrate BJT Q1varies according to a temperature or the like, the first collector current Ic1of the first substrate BJT Q1may be controlled by adjusting the bias current Ibiasoutputted from the current source210regardless of the variation of the first base current Ib1of the first substrate BJT Q1.

In addition, the first mirroring base current Ib1′may be replicated by the sixth PMOS transistor PM26of the third current mirror260to generate the third mirroring base current Ib1′″flowing through the sixth PMOS transistor PM26. The third mirroring base current Ib1′″may have an amount which is equal to “N” times an amount of the first mirroring base current Ib1′. The third mirroring base current Ib1′″may flow from the sixth PMOS transistor PM26into the second emitter of the second substrate BJT Q2. The third mirroring base current Ib1′″(N×Ib1′) replicated by the sixth PMOS transistor PM26and the second collector current Ic2(N×Ic1) generated by the second collector current transmitter270may be supplied to the second emitter of the second substrate BJT Q2.

As described above, a total amount of current flowing through the second emitter of the second substrate BJT Q2may be substantially the same amount as the third mirroring base current Ib1′″(N×Ib1′) flowing through the sixth PMOS transistor PM26and the second collector current Ic2(N×Ic1) flowing through the second collector current transmitter270. The third mirroring base current Ib1′″(N×Ib1) flowing through the sixth PMOS transistor PM26and into the second emitter of the second substrate BJT Q2may correspond to the second base current Ib2flowing through the second base of the second substrate BJT Q2. Thus, the second collector current Ic2(N×Ic1) supplied to the second emitter of the second substrate BJT Q2may flow into the ground terminal through the second collector of the second substrate BJT Q2. The second base current Ib2of the second substrate BJT Q2may have an amount which is equal to “N” times the first base current Ib1of the first substrate BJT Q1. In addition, the second collector current Ic2of the second substrate BJT Q2may have an amount which is equal to “N” times the first collector current Ic1of the first substrate BJT Q1.