INTEGRATED MEMS RESONATOR AND METHOD

An electronic device and associated methods are disclosed. In one example, the electronic device includes a MEMS die located within a substrate, and below a processor die. In selected examples, the MEMS die includes a resonator. Example methods of forming MEMS resonator devices are also shown.

TECHNICAL FIELD

Embodiments described herein generally relate resonators for timing in electronic devices such as computing systems.

BACKGROUND

Commonly, resonators are used in timing circuits that work in conjunction with processors and other semiconductor dies in electronic devices. However, resonators are typically coupled to a circuit board adjacent to an associated semiconductor die. It is desired to have smaller and less expensive resonators.

DESCRIPTION OF EMBODIMENTS

FIG.1shows an electronic device100according to one example. The electronic device100includes a first semiconductive die110and a second semiconductive die112. The dies110,112are shown coupled to a substrate120. In one example, one or more of the dies110,112includes a processor die or processor core. Other example dies include controller dies, memory dies, etc. Although two dies are shown inFIG.1, the invention is not so limited. A single die may be used, or more than two dies may be used in configurations of the present disclosure.FIG.1further shows one or more redistribution layers126on a bottom surface of the substrate120, and a circuit board102coupled to the redistribution layers126.

In one example, the substrate120is a glass substrate, although the invention is not so limited. Examples of a glass substrate120include silicon dioxide glass. The glass may be a silicate-based glass (e.g., lithium-silicate, borosilicate, aluminum silicate, etc.). The substrate may also include crystalline or partially crystalline silicon oxide, such as quartz. In the example shown, the substrate120is formed from more than one layer122. In one example, layers122may be bonded together to form the substrate120, for example, using an adhesive layer124. Other methods of bonding layers to form a substrate120are also within the scope of the invention. Selected examples may include multiple different materials in the layers, for example, glass and quartz. One advantage of glass substrates120over other materials such as resin-based substrates includes increased stiffness and reduced variability in dimensions. Additionally, glass or quartz substrates provide lower electrical loss compared to organic substrates. A layered substrate120provides ease of manufacturing for more complex geometries, such as inclusion of cavities, etc. in the substrate120. In the example ofFIG.1, a high-Q passive device is shown incorporated on a left side of the substrate120. One example of a high-Q passive includes an inductor. Other examples include, but are not limited to, resistors and capacitors.

A microelectromechanical systems (MEMS) die130is shown located within the substrate, and below one or more of the dies110,112. One or more vias114are shown coupled between one or more dies110,112and the MEMS die130. The one or more first vias114are shown passing through a portion of the substrate120. In one example one or more second vias116are shown passing through all of the substrate120and contacting the redistribution layers126to bypass the MEMS die130. In one example, the one or more second vias116include power connections to one or more of the dies110,112.

In one example, the MEMS die is a resonator die. In one example, the MEMS die includes at least one resonator device. In one example, the resonator device includes one or more thin film piezoelectric on substrate (TPoS) resonators as described in more detail below, although other resonator devices are within the scope of the invention. In one example, the MEMS die includes multiple resonator devices. A MEMS die with multiple resonators has an advantage of being able to supply multiple resonator frequencies that may be used in different device configurations with a single MEMS die. In one example, the MEMS die130provides a clock signal for both dies110and112, and can provide a clock signal for more than two dies. In one example the MEMS die130further includes a temperature sensor to measure and compensate for temperature related effects in providing a clock signal. In one example, a temperature sensor is placed on the MEMS die in close proximity (for example within a few hundred micrometers) of a resonator device, enabling highly accurate temperature measurement of the resonator device.

A quartz crystal device is commonly used in computing devices to provide a reference clock frequency. However, quartz crystals are typically separate components that are quite large, and are coupled to a motherboard adjacent to a die package. This configuration takes up a lot of valuable real estate in a time when miniaturized devices such as telephones, watches, etc. are increasingly driven to smaller form factors. By incorporating a MEMS resonator device within a substrate120an overall size of a final electronic device is reduced, and manufacturing may be simplified. Additionally, by incorporating resonator device and MEMS dies as described in the present disclosure, a routing distance is greatly reduced between a processor and a resonator, which greatly reduces any parasitics and enables the creation of a GHz range reference clock.

In one example, a cavity132is included within the substrate120adjacent to the MEMS die130. The cavity may include a vacuum to provide operating conditions for one or more MEMS devices formed in the MEMS die130. In one example, the MEMS die103is sealed within the substrate120to enclose the cavity132. In one example, a sealant134is used. One example of a sealant134includes a solder. A solder sealant134is useful in that it is compatible with other materials in the electronic device100, and is easily processed using existing manufacturing techniques to provide the unique configuration ofFIG.1and other configurations in the present disclosure. Using examples of the present disclosure, there is no need for a separate wafer level packaging for a MEMS die. The substrate120serves as a package for the die130.

FIG.2shows another electronic device200according to one example. The electronic device200includes a first semiconductive die210and a second semiconductive die212. Similar to the example ofFIG.2, the dies210,212are shown coupled to a substrate220. In one example, one or more of the dies210,212includes a processor die or processor core. Other example dies include controller dies, memory dies, etc. Although two dies are shown inFIG.2, the invention is not so limited. More than two dies may be used in configurations of the present disclosure.FIG.2further shows a circuit board202coupled to the substrate220.

In one example, the substrate220is a glass substrate, although the invention is not so limited. Examples of a glass substrate120include silicon dioxide glass. The glass may be a silicate-based glass (e.g., lithium-silicate, borosilicate, aluminum silicate, etc.). The substrate may also include crystalline or partially crystalline silicon oxide, such as quartz. The substrate220may include multiple layers as described inFIG.1. The substrate220may include one or more redistribution layers as described inFIG.1. In selected examples, the substrate220includes organic materials. In selected examples, the substrate220is not glass.

A die230is shown located within the substrate220, and below one or more of the dies210,212. The die230includes a top side232and a bottom side234. In one example, each side232,234includes functional devices as described in more detail below. One or more first vias213are shown coupled between one or more dies210,212and the top side232. One or more second vias214are shown passing through the die230and coupled between one or more dies210,212and the bottom side234. In one example one or more third vias216are shown passing through all of the substrate220. In one example, the one or more second vias216include power connections to one or more of the dies210,212.

In one example, the top side232includes an interconnect bridge die, and the bottom side234includes a MEMS die. In one example, the MEMS die includes one or more resonators similar to the MEMS die described above with respect toFIG.1. In one example, the MEMS side of die230provides a clock signal for both dies210and212, and can provide a clock signal for more than two dies. In one example the MEMS side of die230further includes a temperature sensor to measure and compensate for temperature related effects in providing a clock signal.

Although the interconnect bridge die is shown on the top232and the MEMS die is shown on the bottom234, the invention is not so limited. The interconnect bridge die can also be on the bottom234and the MEMS die can be on the top232.

In one example, an interconnect bridge includes all or primarily passive traces to interconnect between adjacent dies such as dies210,212. Traces236are shown inFIG.2, connected to vias213to interconnect dies210and212. By including all or primarily all passive traces, the interconnect bridge has a high manufacturing yield and can be manufactured using lithographic techniques to provide high trace density. In one example, the MEMS die components are manufactured on a common, monolithic semiconductor. In one example, the MEMS die components are manufactured on a common, monolithic glass or quartz substrate. In one example, the interconnect bridge and the MEMS die are manufactured separately, and joined back to back to form a two sided die230. In one example, a thin film cap238is included on the MEMS die side (bottom side234inFIG.2) to provide a vacuum cavity for operation of MEMS devices.

FIG.3shows a flow diagram of one example method of forming a MEMS resonator device in a semiconductor substrate. The resulting MEMS resonator device may be used in any MEMS die or die surface as described in examples above. In operation302, a first electrode layer is formed over a semiconductor substrate, the semiconductor substrate including a buried insulator layer. In operation304, a piezoelectric layer is formed over the first electrode layer. In operation306, a second electrode layer is formed over the piezoelectric layer. In operation308, a trench is formed through the first electrode layer, the piezoelectric layer, the second electrode layer, and the semiconductor substrate above the buried insulator layer to laterally separate a resonator. Lastly, in operation310, a portion of the buried insulator layer is removed to vertically separate the resonator.

FIGS.4A-4C,5A-5B, and6A-6Cillustrate selected process flow stages of the method ofFIG.3and others.FIG.4Ashows a substrate400including a bottom semiconductor portion402, a top semiconductor portion404, and a buried insulation layer406. In one example, the substrate400is a cavity silicon-on-insulator (SOI) substrate, that includes one or more cavities408. A cavity SOI substrate can be pre-manufactured, and start in the form illustrated inFIG.4A. InFIG.4B, a first electrode layer410is formed over portion404, a piezoelectric layer412is formed over the first electrode layer410, and a second electrode layer414is formed over the piezoelectric layer412. trenches416are formed through the first electrode layer410, the piezoelectric layer412, and the second electrode layer414, and into the top portion404of the semiconductor substrate400above the buried insulator layer406to laterally separate a resonator450. InFIG.4C, a portion of the buried insulator layer406is removed to vertically separate the resonator450.

InFIGS.5A-5Ba different process is shown that does not include a cavity SOI substrate. InFIG.5A, a substrate including a bottom semiconductor portion502, a top semiconductor portion504, and a buried insulation layer506is formed. In one example, the buried insulation layer506is a box oxide layer. InFIG.5A, a first electrode layer510is formed over portion504, a piezoelectric layer512is formed over the first electrode layer510, and a second electrode layer514is formed over the piezoelectric layer512. trenches516are formed through the first electrode layer510, the piezoelectric layer512, and the second electrode layer514, and into the top portion504of the semiconductor substrate above the buried insulator layer506to laterally separate a resonator550. InFIG.5B, a portion of the buried insulator layer506is removed to vertically separate the resonator550. As a result of etching the buried insulator layer506, undercuts518are formed under portion504of the substrate.

InFIGS.6A-6Ca different process is shown that includes additional holes through the resonator. The additional holes provide a number of advantages as described below. InFIG.6A, a substrate including a bottom semiconductor portion602, a top semiconductor portion604, and a buried insulation layer606is formed. In one example, the buried insulation layer606is a box oxide layer. InFIG.6A, a first electrode layer610is formed over portion604, a piezoelectric layer612is formed over the first electrode layer610, and a second electrode layer614is formed over the piezoelectric layer612. trenches616are formed through the first electrode layer610, the piezoelectric layer612, and the second electrode layer614, and into the top portion604of the semiconductor substrate above the buried insulator layer606to laterally separate a resonator650. One or more holes618are also formed vertically through the resonator650from a top surface620to a bottom622of the resonator650before any removal of the buried insulator layer606. InFIG.6B, a portion of the buried insulator layer606is removed to vertically separate the resonator650. Due to the presence of the one or more holes618, a middle section of the buried insulator layer606is also exposed to etchant, which facilitates faster, more even etching of the buried insulator layer606in the desired region beneath the resonator650. As a result, the undercuts630that are formed under portion604of the substrate are smaller than in the example ofFIG.5B.

FIG.6Cshows a top view of the resonator650with the top electrode614and the one or more holes618indicated. In addition to reducing the size of undercuts630, the addition of one or more holes618as shown inFIG.6Aprovides a resonance tuning advantage. The resonance frequency would be defined by the following equation with the resonator planar dimension Leff, effective stiffness Eeff(which would be defined by the stack of different materials in the resonator body), and the effective density for the stack of materials in the resonator body.

For example, assume the case of under etch for any fabrication process inaccuracies. This would cause the size of the resonator to be larger than what is designed and the resonance frequency to be lower than the designed resonance frequency. By adding one or more holes618in the resonator650, in the case of under etch, the holes618in the resonator would be smaller which means the effective stiffness would be higher, which would shift the resonance frequency up. In this way, the inclusion of one or more holes618compensates for any fabrication process inaccuracy and eliminates the need for subsequent coarse frequency trimming.

FIG.7illustrates a system level diagram, depicting an example of an electronic device (e.g., system) that may include an electronic device including one or more MEMS devices and dies and/or methods described above. In one embodiment, system700includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system700includes a system on a chip (SOC) system.

In one embodiment, processor710has one or more processor cores712and712N, where712N represents the Nth processor core inside processor710where N is a positive integer. In one embodiment, system700includes multiple processors including710and705, where processor705has logic similar or identical to the logic of processor710. In some embodiments, processing core712includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor710has a cache memory716to cache instructions and/or data for system700. Cache memory716may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor710includes a memory controller714, which is operable to perform functions that enable the processor710to access and communicate with memory730that includes a volatile memory732and/or a non-volatile memory734. In some embodiments, processor710is coupled with memory730and chipset720. Processor710may also be coupled to a wireless antenna778to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna778operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

Memory730stores information and instructions to be executed by processor710. In one embodiment, memory730may also store temporary variables or other intermediate information while processor710is executing instructions. In the illustrated embodiment, chipset720connects with processor710via Point-to-Point (PtP or P-P) interfaces717and722. Chipset720enables processor710to connect to other elements in system700. In some embodiments of the example system, interfaces717and722operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset720is operable to communicate with processor710,705N, display device740, and other devices, including a bus bridge772, a smart TV776, I/O devices774, nonvolatile memory760, a storage medium (such as one or more mass storage devices)762, a keyboard/mouse764, a network interface766, and various forms of consumer electronics777(such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset720couples with these devices through an interface724. Chipset720may also be coupled to a wireless antenna778to communicate with any device configured to transmit and/or receive wireless signals. In one example, any combination of components in a chipset may be separated by a continuous flexible shield as described in the present disclosure.

Chipset720connects to display device740via interface726. Display740may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor710and chipset720are merged into a single SOC. In addition, chipset720connects to one or more buses750and755that interconnect various system elements, such as I/O devices774, nonvolatile memory760, storage medium762, a keyboard/mouse764, and network interface766. Buses650and755may be interconnected together via a bus bridge772.

While the modules shown inFIG.7are depicted as separate blocks within the system700, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory716is depicted as a separate block within processor710, cache memory716(or selected aspects of716) can be incorporated into processor core712.

To better illustrate the method and apparatuses disclosed herein, a non-limiting list of embodiments is provided here:

Example 1 includes an electronic device. The device includes a processor die coupled to a substrate, a microelectromechanical systems (MEMS) resonator die located within the substrate, and below the processor die, and one or more vias coupled between the processor die and the MEMS resonator die, the one or more vias passing through a portion of the substrate.

Example 2 includes the electronic device of example 1, further including a temperature sensor.

Example 3 includes the electronic device of any one of examples 1-2, wherein the substrate includes a glass substrate.

Example 4 includes the electronic device of any one of examples 1-3, further including a cavity below the MEMS resonator die.

Example 5 includes the electronic device of any one of examples 1-4, wherein the substrate includes multiple layers of glass bonded together.

Example 6 includes the electronic device of any one of examples 1-5, wherein the MEMS resonator die is sealed over a cavity using solder.

Example 7 includes the electronic device of any one of examples 1-6, further including a redistribution layer on a bottom of substrate opposite the processor die.

Example 8 includes the electronic device of any one of examples 1-7, wherein the MEMS resonator die is formed in a silicon-on-insulator (SOI) surface.

Example 9 includes the electronic device of any one of examples 1-8, wherein the MEMS resonator die includes a thin film piezoelectric on substrate (TPoS) resonator.

Example 10 includes the electronic device of any one of examples 1-9, wherein the TPoS resonator includes a buried oxide layer with an undercut on sides of resonator.

Example 11 includes the electronic device of any one of examples 1-10, wherein the TPoS resonator includes one or more holes vertically passing through the resonator.

Example 12 includes an electronic device. The device includes a first semiconductive die and a second semiconductive die coupled to a substrate, and an interconnect bridge at least partially within the substrate, the interconnect bridge having a first side, and a second side opposite the first side, wherein the first side of the interconnect bridge is coupled between the first semiconductive die and the second semiconductive die. The device includes a microelectromechanical systems (MEMS) resonator device located on the second side of the interconnect bridge, and one or more vias coupled between at least one of the first semiconductive die and the second semiconductive die and the MEMS resonator device, the one or more vias passing through the interconnect bridge.

Example 13 includes the electronic device of example 12, further including a cavity over the MEMS resonator device.

Example 14 includes the electronic device of any one of examples 12-13, wherein the interconnect bridge includes a silicon substrate.

Example 15 includes the electronic device of any one of examples 12-14, wherein the interconnect bridge includes a glass substrate.

Example 16 includes the electronic device of any one of examples 12-15, wherein the interconnect bridge includes a quartz substrate.

Example 17 includes the electronic device of any one of examples 12-16, wherein the MEMS resonator device includes one or more thin film piezoelectric on substrate (TPoS) resonators.

Example 18 includes the electronic device of any one of examples 12-17, wherein the TPoS resonator includes a buried oxide layer with an undercut on sides of resonator.

Example 19 includes the electronic device of any one of examples 12-18, wherein the TPoS resonator includes one or more holes vertically passing through the resonator.

Example 20 includes the electronic device of any one of examples 12-19, wherein the MEMS resonator device includes multiple thin film piezoelectric on substrate (TPoS) resonators configured to provide more than one frequency.

Example 21 includes the electronic device of any one of examples 12-20, wherein the MEMS resonator device is formed in a silicon-on-insulator (SOI) surface.

Example 22 includes a method of forming a microelectromechanical systems (MEMS) resonator. The method includes forming a first electrode layer over a semiconductor substrate, the semiconductor substrate including a buried insulator layer, forming a piezoelectric layer over the first electrode layer, forming a second electrode layer over the piezoelectric layer, forming a trench through the first electrode layer, the piezoelectric layer, the second electrode layer, and the semiconductor substrate above the buried insulator layer to laterally separate a resonator, and removing a portion of the buried insulator layer to vertically separate the resonator.

Example 23 includes the method of example 22, wherein forming the first electrode layer over the semiconductor substrate includes forming the first electrode layer over a cavity in a cavity-SOI substrate.

Example 24 includes the method of any one of examples 22-23, wherein forming the first electrode layer over the semiconductor substrate includes forming the first electrode layer over a layer of semiconductor separated from a bulk semiconductor by the box oxide layer, and wherein removing a portion of the buried insulator layer includes etching a portion of the box oxide layer, and forming undercuts on sides of the resonator.

Example 25 includes the method of any one of examples 22-24, further including forming one or more holes vertically through the resonator before removing the portion of the buried insulator layer, and at least partially removing the portion of the buried insulator layer by introducing an etchant through the one or more holes.