SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device includes, above a substrate, a first layer with, on both sides in a direction, first regions; a second layer above the first layer with, on both sides in the direction, second regions above the first regions; a third layer, third regions, a fourth layer, and fourth regions, corresponding to the first layer, first regions, second layer, and second regions, respectively, the third layer being side by side with the first layer in another direction, the fourth layer being side by side with the second layer in the other direction; first and second gate electrodes above the first and second layers and the third and fourth layers, and having gate insulating films between these gate electrodes and these layers; and an insulating wall extending in the direction with both side surfaces contacted by the first and second layers and the third and fourth layers, respectively.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a semiconductor device manufacturing method.

2. Description of the Related Art

A device called a complementary field effect transistor (CFET) is known. In a CFET, an n-channel FET and a p-channel FET are stacked on a substrate. A CFET is suitable for miniaturization of a semiconductor device.

Also a device called a forksheet transistor is known. In a forksheet transistor, channels of nanowires or nanosheets are arranged in such a manner that a wall-like insulating film is placed between the channels. Also a forksheet transistor is suitable for miniaturization of a semiconductor device.

RELATED ART DOCUMENTS

Patent Documents

SUMMARY

Means for Solving the Problems

A semiconductor device according to a disclosed technology includes: a substrate; a first semiconductor layer disposed above the substrate; a first semiconductor region and a second semiconductor region that are disposed above the substrate, the first semiconductor layer being disposed between the first semiconductor region and the second semiconductor region with respect to a first direction in plan view; a second semiconductor layer disposed above the first semiconductor layer; a third semiconductor region and a fourth semiconductor region that are disposed above the first semiconductor region and the second semiconductor region, respectively, the second semiconductor layer being disposed between the third semiconductor region and the fourth semiconductor region with respect to the first direction; a third semiconductor layer disposed above the substrate and disposed side by side with respect to the first semiconductor layer with respect to a second direction different from the first direction in plan view; a fifth semiconductor region and a sixth semiconductor region disposed above the substrate, the third semiconductor layer being disposed between the fifth semiconductor region and the sixth semiconductor region with respect to the first direction in plan view; a fourth semiconductor layer disposed above the third semiconductor layer and disposed side by side with respect to the second semiconductor layer with respect to the second direction in plan view; a seventh semiconductor region and an eighth semiconductor region disposed above the fifth semiconductor region and the sixth semiconductor region, respectively, the fourth semiconductor layer being disposed between the seventh semiconductor region and the eighth semiconductor region with respect to the first direction; an insulating wall having an insulating property, disposed above the substrate, extending in the first direction, and having a first side surface and a second side surface opposite the first side surface; a first gate electrode disposed above the first semiconductor layer and the second semiconductor layer, first gate insulating films being disposed between the first gate electrode and the first semiconductor layer and between the first gate electrode and the second semiconductor layer; and a second gate electrode disposed above the third semiconductor layer and the fourth semiconductor layer, second gate insulating films being disposed between the second gate electrode and the third semiconductor layer and between the second gate electrode and the fourth semiconductor layer. The first side surface is in contact with the first semiconductor layer and the second semiconductor layer, and the second side surface is in contact with the third semiconductor layer and the fourth semiconductor layer.

The object and advantages of the invention will be implemented and attained by the elements and combinations particularly pointed out in the appended claims.

DESCRIPTION OF EMBODIMENTS

In the related arts, study for a specific structure enabling further miniaturization has not been made in detail.

An object of the present invention is to provide a semiconductor device enabling further miniaturization and a method of5manufacturing the same.

According to the disclosed technology, it is possible to provide a semiconductor device enabling further miniaturization and a method of manufacturing the same.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the specification and the drawings, components having substantially the same functions and configurations are denoted by the same reference numerals, and redundant description thereof may be omitted. In the following description, two directions parallel to a surface of a substrate and orthogonal to each other are referred to as an X direction and a Y direction, and a direction perpendicular to the surface of the substrate is referred to as a Z direction. An n-channel field-effect transistor may be referred to as an nFET, and a p-channel field-effect transistor may be referred to as a pFET. In addition, being the same in the arrangement in the present disclosure does not strictly exclude not being the same due to manufacturing variation, and even in a case where deviation occurs in the arrangement due to manufacturing variation, the arrangement can be regarded as being the same.

(Circuit included in Semiconductor Device)

A circuit included in a semiconductor device according to an embodiment will be described.FIG.1is a diagram illustrating the configuration of the circuit included in the semiconductor device according to the embodiment.

As depicted inFIG.1, the semiconductor device100according to the embodiment includes a buffer BU, a VDD wiring to which a power supply potential VDD is applied, and a VSS wiring to which a power supply potential VSS is applied. The VDD wiring is also called a power supply wiring in some cases. The power supply potential of VSS is, for example, a ground potential, and the VSS wiring is sometimes referred to as a ground wiring. The buffer BU includes an inverter1and an inverter2. An input signal IN is input to the inverter1, an output of the inverter1is input to the inverter2, and an output signal OUT is output from the inverter2. The inverter1includes a p-channel field-effect transistor (pFET)1P and an n-channel field-effect transistor (nFET)1N, and the inverter2includes a pFET2P and an nFET2N.

Next, the configuration of the buffer BU will be described.FIG.2andFIG.3depict schematic plan-view configurations of the buffer BU.FIG.2mainly depicts a layout of the nFET IN and the pFET2P.FIG.3mainly depicts a layout of the pFET1P and the nFET2N. Except for the structure depicted in bothFIGS.2and3, the structure depicted inFIG.3is located above the structure depicted inFIG.2.FIGS.4,5,6,7, and8are cross-sectional views depicting the buffer BU.FIG.4corresponds to a cross-sectional view taken along the line IV-IV inFIGS.2and3.FIG.5corresponds to a cross-sectional view taken along the line V-V inFIGS.2and3.FIG.6corresponds to a cross-sectional view taken along the line VI-VI inFIGS.2and3.FIG.7corresponds to a cross-sectional view taken along the line VII-VII inFIGS.2and3.FIG.8corresponds to a cross-sectional view taken along the line VIII-VIII inFIGS.2and3.

As depicted inFIGS.2to8, isolation films102are formed on a surface of a substrate101. The isolation films102are formed by, for example, a shallow trench isolation (STI) method. A plurality of trenches extending in the X direction are formed on the substrate101and the isolation films102, and power supply lines910and920are formed in these trenches via insulating films104. For example, the surfaces of the power supply lines910and920are covered by insulating films103. For example, the surfaces of the isolation films102and the surfaces of the insulating films103may be flush with and need not be flush with the surface of the substrate101. Power supply lines910and920are embedded in the substrate101. The power supply lines910and920having such structures may be referred to as buried power rails (BPR). For example, the power supply line910corresponds to the VDD wiring, and the power supply line920corresponds to the VSS wiring.

For example, two regions10and20arranged along the Y direction are defined by the isolation film102. Generally, the inverter1is formed in the region10, and the inverter2is formed in the region20.

In the region10, a stacked transistor structure11is formed on the substrate101. The stacked transistor structure11includes a gate electrode110, nanosheets121and122, gate insulating films130, and spacers140. The gate electrode110extends in the Y direction and extends upward in the Z direction. The nanosheets121and122penetrate the gate electrode110in the X direction, and are arranged in the Y direction and the direction. The gate insulating film130is formed between the gate electrode110and the nanosheets121and122. In the X direction, the gate electrode110and the gate insulating films130are formed in such a manner as to recede from both ends of the nanosheets121and122, and the spacers140are formed in these receded spaces. In other words, with respect to the X direction, the spacers140are formed between the gate electrode110and semiconductor layers that include n-type semiconductor layers161and p-type semiconductor layers163, which will be described later.

For example, each of the number of the nanosheets121arranged in the Z direction and the number of the nanosheets122arranged in the Z direction is two, and the two nanosheets122are arranged above the two nanosheets121. The thickness of each of the nanosheets121and each of the nanosheets122is, for example, about 5 nm. Each of the number of the nanosheets121and the number of the nanosheets122may be one, or three or more. In addition, the number of nanosheets121and the number of nanosheets122may be the same as each other or different from each other.

In the region10, the two n-type semiconductor layers161in contact with the ends of the nanosheets121are formed so that the gate electrode110is disposed between the n-type semiconductor layers161in the X direction. Two local wirings162in contact with the n-type semiconductor layers161are formed in such a manner that the gate electrode110is disposed between the local wirings162in the X direction. The two p-type semiconductor layers163in contact with ends of the nanosheets122are formed in such a manner that the gate electrode110is disposed between the p-type semiconductor layers163in the X direction. Two local wirings164in contact with the p-type semiconductor layers163are formed in such a manner that the gate electrode110is disposed between the local wirings164in the X direction. Insulating films31are formed between the local wirings162and the local wirings164. For example, the n-type semiconductor layers161are n-type Si layers, and the p-type semiconductor layers163are p-type SiGe layers. For example, silicon oxide or silicon nitride can be used for the insulating films31. Contact holes312are formed in the insulating films31between the local wirings162and the local wirings164. The local wirings164is electrically connected to the local wirings162through conductors in the contact holes312.

A portion of the gate electrode110, the nanosheets121, portions of the gate insulating films130, and the n-type semiconductor layers161are included in the nFET1N. In the nFET1N, one of the n-type semiconductor layers161functions as a source region, the other n-type semiconductor layer161functions as a drain region, and the nanosheets121function as channels. A portion of the gate electrode110, the nanosheets122, portions of the gate insulating films130, and the p-type semiconductor layers163are included in the pFET1P. In the pFET1P, the one p-type semiconductor layer163functions as a source region, the other p-type semiconductor layer163functions as a drain region, and the nanosheets122function as channels. The n-type semiconductor layers161and the substrate101may be electrically connected to each other, or may be electrically separated from each other by insulating films formed therebetween.

In the region20, a stacked transistor structure21is formed on the substrate101. The stacked transistor structure21includes a gate electrode210, nanosheets221and222, gate insulating films230, and spacers240. The gate electrode210extends in the Y direction and extends upward in the Z direction. The nanosheets221and222penetrate the gate electrode210in the X direction, and are arranged in the Y direction and the direction. The gate insulating films230are formed between the gate electrode210and the nanosheets221and222. In the X direction, the gate electrode210and the gate insulating films230are formed in such a manner as to recede from both ends of the nanosheets221and222, and the spacers240are formed in these receded spaces. In other words, in the X direction, the spacers240are formed between the gate electrode210and semiconductor layers that include the p-type semiconductor layers261and the n-type semiconductor layers263, which will be described later.

For example, each of the number of nanosheets221arranged in the Z direction and the number of nanosheets222arranged in the Z direction is two, and the two nanosheets222are arranged above the two nanosheets221. The thickness of each of the nanosheets221and222is, for example, less than or equal to 10 nm, preferably less than or equal to 5 nm. Each of the number of nanosheets221and the number of nanosheets222may be one, or three or more. In addition, each of the number of nanosheets221and the number of nanosheets222may be the same as or different from each other.

In the region20, the two p-type semiconductor layers261in contact with the ends of the nanosheets221are formed in such a manner as to sandwich the gate electrode210in the X direction. Two local wirings262in contact with the p-type semiconductor layers261are formed in such a manner that the gate electrode210is disposed between the local wirings262in the X direction. The two n-type semiconductor layers263in contact with the ends of the nanosheets222are formed in such a manner that the gate electrode210is disposed between the n-type semiconductor layers263in the X direction. Two local wirings264in contact with the n-type semiconductor layers263are formed in such a manner that the gate electrode210is disposed between the local wirings264in the X direction. Insulating films32is formed between the local wirings262and the local wirings264. For example, the p-type semiconductor layers261are p-type SiGe layers, and the n-type semiconductor layers263are n-type Si layers. For example, silicon oxide or silicon nitride can be used for the insulating films32. Contact holes322are formed in the insulating films32between the local wirings262and the local wirings264. The local wirings264are electrically connected to the local wirings262through conductors in the contact holes322. The p-type semiconductor layers261and the substrate101may be electrically connected to each other, or may be electrically separated from each other by insulating films formed therebetween.

A portion of the gate electrode210, the nanosheets221, portions of the gate insulating films230, and the p-type semiconductor layers261are included in the pFET2P. In the pFET2P, one of the p-type semiconductor layers261functions as a source region, the other p-type semiconductor layer261functions as a drain region, and the nanosheets221function as channels. A portion of the gate electrode210, the nanosheets222, portions of the gate insulating films230, and the n-type semiconductor layers263are included in the nFET2N. In the nFET2N, one of the n-type semiconductor layers263functions as a source region, the other n-type semiconductor layer263functions as a drain region, and the nanosheets222function as channels.

Although not depicted in the drawings, insulating films are formed between the substrate101and the gate electrodes110and210to electrically isolate the gate electrodes110and210from the substrate101.

The local wiring162extends in the Y direction. The local wiring162thus extends to a position above the power supply line910. A contact hole311is formed in the insulating film103between the local wiring162and the power supply line910. The local wiring162is connected to the power supply line910through a conductor in the contact hole311.

The local wiring262extends in the Y direction. The local wiring262thus extends to a position above the power supply line920. A contact hole321is formed in the insulating film103between the local wiring262and the power supply line920. The local wiring262is connected to the power supply line920through a conductor in the contact hole321.

An insulating wall50is provided on the substrate101between the regions10and20. The wall50extends in the X direction and extends upward in the Z direction. The wall50includes a side surface51and a side surface52opposite to the side surface51, the side surface51being in contact with the nanosheets121and122and the side surface52being in contact with the nanosheets221and222. The width of the wall50, i.e., the distance between the side surfaces51and52, is, for example, less than or equal to 15 nm, preferably less than or equal to 8 nm.

As depicted inFIG.4, side walls55are formed in such a manner as that the gate electrodes110and210together with the wall50are disposed between the side walls55with respect to the Y direction. Insulating films61are formed on the sides of the side walls55. As depicted inFIG.5, insulating films63are formed between the insulating films61and the local wirings164and264; and, as depicted inFIG.6, an insulating film62is formed between the insulating film61and the local wiring262.

An insulating film64is formed on the wall50, the gate electrodes110and210, the spacers140and240, the local wirings164and264, the side walls55, and the insulating films61and63; and an insulating film65is formed on the insulating film64.

A contact hole313reaching the local wiring162is formed in the insulating films64,63, and31; and a contact hole323reaching the local wiring262is formed in the insulating films64,63, and32. For example, the contact hole313is formed above the contact hole311, and the contact hole323is formed above the contact hole321.

Signal lines411and421are formed in the insulating film64. The signal line411is connected to the local wiring162through a conductor in the contact hole313. The signal line421is connected to the local wiring262through a conductor in the contact hole323.

A contact hole314reaching the gate electrode110, a contact hole315reaching one of the local wirings164, and a contact hole316reaching the other local wiring164are formed in the insulating film64. A contact hole324reaching the gate electrode210, a contact hole325reaching one of the local wirings264, and a contact hole326reaching the other local wiring264are formed in the insulating film64.

Signal lines412,413,414,422,423, and424are formed in the insulating film64. The signal line412is connected to the gate electrode110through a conductor in the contact hole314. The signal line413is connected to the one local wiring164through a conductor in the contact hole315. The signal line414is connected to the other local wiring164through a conductor in the contact hole316. The signal line423is connected to the gate electrode210through a conductor in the contact hole324. The signal line424is connected to the one local wiring264through a conductor in a contact hole325. The signal line422is connected to the other local wiring264through a conductor in the contact hole326.

A contact hole317reaching the signal line414, a contact hole318reaching the signal line413, and a contact hole319reaching the signal line411are formed in the insulating film65. A contact hole327reaching the signal line423, a contact hole328reaching the signal line421, and a contact hole329reaching the signal line424are formed in the insulating film65.

Signal lines431,432, and433are formed in the insulating film65. The signal line431is connected to the signal line413through a conductor in the contact hole318, and connected to the signal line421through a conductor in the contact hole328. The signal line432is connected to the signal line414through a conductor in the contact hole317, and connected to the signal line423through a conductor in the contact hole327. The signal line433is connected to the signal line411through a conductor in the contact hole319, and connected to the signal line424through a conductor in the contact hole329.

In the buffer BU, the input signal IN is input to the signal line412, and the output signal OUT is output from the signal line422.

For example, ruthenium (Ru), molybdenum (Mo), cobalt (Co), tungsten (W), or the like is used as the materials of the power supply lines910and920. For example, copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), or the like is used as the materials of the signal lines411to414,421to424, and431to433. When copper, cobalt, or tungsten is used, it is preferable to form conductive underlying films (barrier metal films), for example, tantalum (Ta) films or tantalum nitride (TaN) films, but, when ruthenium is used, such underlying films need not be formed.

For example, copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), tungsten (W), or the like is used as the materials of the local wirings162,164,262, and264. When copper, cobalt, or tungsten is used, it is preferable to form conductive underlying films (barrier metal films) such as titanium (Ti) films or titanium nitride (TiN) films, but, when molybdenum or ruthenium is used, such underlying films need not be formed. For example, materials same as or similar to the materials of the local wirings can be used as the conductors (vias) in the contact holes.

For example, a semiconductor such as silicon (Si) can be used for the substrate101. For example, a semiconductor such as silicon (Si) can be used for the nanosheets121,122,221, and222. For the p-type semiconductor layers163and261, a semiconductor such as silicon, silicon carbide (SiC), or silicon germanium (SiGe), containing boron (B) as a p-type impurity, can be used. A semiconductor such as silicon, silicon carbide, or silicon germanium, containing phosphorus (P) as an n-type impurity, can be used for the n-type semiconductor layers161and263.

For example, a conductive material such as titanium (Ti), titanium nitride (TiN), or polycrystalline silicon (poly-Si) can be used for the gate electrodes110and210. For example, for the gate insulating films130and230, a high-dielectric-constant material such as hafnium oxide, aluminum oxide, or an oxide of hafnium and aluminum can be used. The gate insulating films130formed on the nanosheets121and the gate insulating films130formed on the nanosheets122may contain different materials between the gate insulating films130formed on the nanosheets121and the gate insulating films130formed on the nanosheets122. Further, the gate insulating films230formed on the nanosheets221and the gate insulating films230formed on the nanosheets222may contain different materials between gate insulating films230formed on the nanosheets221and the gate insulating films230formed on the nanosheets

For example, the local wirings and the signal lines are formed by a dual damascene method together with the contact holes provided below the same. Further, the local wirings and the signal lines may be formed by a single damascene method, separately from the contact holes provided below the same.

For example, silicon oxide, silicon nitride, or the like can be used as the materials of the side walls55, the spacers140and240, and the insulating wall50.

Next, a method of manufacturing the semiconductor device100according to the embodiment will be described.FIGS.9to24are plan views illustrating the semiconductor device manufacturing method according to the embodiment.FIGS.25to37are cross-sectional views illustrating the semiconductor device manufacturing method according to the embodiment.FIGS.25to37depict changes in the cross sections taken along the line Iv-Iv inFIGS.2and3.FIGS.38to44are cross-sectional views illustrating the semiconductor device manufacturing method according to the embodiment.FIGS.38to44depict changes in the cross sections taken along the line v-v inFIGS.2and3.FIGS.45to48are cross-sectional views illustrating the semiconductor device manufacturing method according to the embodiment.FIGS.45to48depict changes in the cross sections taken along the line VI-VI inFIGS.2and3.FIGS.49to63are cross-sectional views illustrating the semiconductor device manufacturing method according to the embodiment.FIGS.49to63depict changes in the cross sections taken along the line VII-VII inFIGS.2and3. InFIGS.12to24, the insulating films other than the gate insulating films are omitted.

First, as depicted inFIGS.9,25, and49, a SiGe film71, a Si film81, a SiGe film72, a Si film82, a SiGe film73, a Si film83, a SiGe film74, a Si film84, and a SiGe film75are formed on a substrate101. The Si films81and82are used to form the nanosheets121and221, and the Si films83and84are used to form the nanosheets122and222. Each of the thicknesses of the Si films81to84is, for example, about 5 nm. Each of the thicknesses of the SiGe films71to75is, for example, about in the range of 5 nm to 8 nm. The SiGe film73may be thicker than each of the SiGe films71,72,74, and75. The SiGe films71to75and the Si films81to84are formed by, for example, an epitaxial growth method.

Next, as depicted inFIGS.10and26, a lamination of the SiGe films71to75and the Si films81to84is etched and patterned into plate shapes protruding from the substrate101. By this patterning process, fins91and92extending in the Y direction are formed for the regions10and20, respectively. The fins91and92are provided side by side with respect to the X-direction. Further, trenches105for the isolation films102are formed on the surface of the substrate101on the sides of the fins91and92in plan view.

Then, as depicted inFIG.27, the isolation films102are formed in the trenches105. For example, the two regions10and20arranged side by side with respect to the X direction are delimited by the isolation films102.

Subsequently, as depicted inFIG.28, an insulating film106is formed to cover the top and side surfaces of the fins91and92and the top surface of the isolation films102. The insulating film106is formed to fill the gap between the fins91and92.

Next, as depicted inFIGS.11and29, the insulating film106is etched in such a manner as to remain in the gap between the fins91and92, thereby forming the insulating wall50. The wall50has the side surface51in contact with the fin91and the side surface52in contact with the fin92. Note that the insulating film106may be formed before the isolation film102is formed; the insulating film106may be etched in such a manner as to remain in the gap between the fins91and92; and then, the isolation film102may be formed. In this case, instead of the isolation film102, the wall50is formed in the trench105between the fins91and92. In addition, the isolation film102and the insulating film106may be formed at a time, and then, the insulating film106may be etched in such a manner as to remain in the gap between the fins91and92.

Thereafter, as depicted inFIGS.12and30, a plurality of trenches for the power supply lines910and920extending in the X direction are formed in the isolation films102and the substrate101, and insulating films104are formed along the bottom and side surfaces of these trenches. Then, the power supply lines910and920are formed on the insulating films104, and insulating films103are formed on the power supply lines910and920. The formation of the trenches, the formation of the insulating films104, the formation of the power supply lines910and920, and the formation of the insulating films103may be performed before the formation of the wall50.

Subsequently, as depicted inFIGS.13,31, and50, sacrificial gates107and side walls55are formed. The sacrificial gates107are, for example, polycrystalline silicon films. The side walls55can be formed by, for example, forming insulating films and performing etching back thereon.

Next, as depicted inFIGS.14,32,38, and51, an insulating film61is formed. In the formation of the insulating film61, for example, a silicon oxide film is formed, and an upper surface of the silicon oxide film is polished by chemical mechanical polishing (CMP) until the sacrificial gates107and the side walls55are exposed.

Thereafter, as depicted inFIGS.15,39, and52, the insulating film61is selectively removed in regions where the gate electrodes and the local wirings are to be formed, and portions of the fins91and92exposed without being covered by the sacrificial gates107and the side walls55are removed.

Subsequently, as depicted inFIG.53, both ends of the SiGe films71to75are caused to recede in the X direction by isotropic etching. Portions of the Si films81and82in the fin91are used as the nanosheets121, portions of the Si films81and82in the fin92are used as the nanosheets221, portions of the Si films83and84in the fin91are used as the nanosheets122, and portions of the Si films83and84in the fin92are used as the nanosheets222.

Next, as depicted inFIG.54, the spacers140are formed at portions where the SiGe films71to75have thus receded.

Thereafter, as depicted inFIGS.16and55, cover films108are formed in such a manner as to cover both end surfaces of the nanosheets122and222with respect to the X direction.

Subsequently, as depicted inFIGS.17,40, and56, the n-type semiconductor layers161are caused to epitaxially grow on the side surfaces of the nanosheets121, and the p-type semiconductor layers261are caused to epitaxially grow on the side surfaces of the nanosheets221. For example, phosphorus (P) is introduced as an n-type impurity into the n-type semiconductor layers161using phosphine (PH3), and boron (B) is introduced as a p-type impurity into the p-type semiconductor layers261using diborane (B2H6). Either the n-type semiconductor layers161or the p-type semiconductor layers261may be formed first. It is preferable that the cover films108are formed also on the side surfaces of either the nanosheets121or the nanosheets221on which either the n-type semiconductor layers161or the p-type semiconductor layers261formed later are caused to grow, and are removed from portions on which the semiconductor layers formed later are caused to grow after the growth of the semiconductor layers that are formed earlier.

Next, as depicted inFIGS.18,41,45, and57, the insulating film62is formed, and the two local wirings162in contact with the n-type semiconductor layers161and the two local wirings262in contact with the p-type semiconductor layers261are formed. The local wirings162and262can be formed simultaneously. The local wirings162and262can be formed by, for example, forming conductive films and performing etching back thereon. Further, the insulating films31are formed on the local wirings162, and the insulating films32are formed on the local wirings262. The insulating films31and32can be formed simultaneously. Before forming the local wirings162and262, the contact holes311and321may be formed in the insulating films103; one of the local wirings162may be formed in such a manner as to be in contact with the power supply line910; and one of the local wirings262may be formed in such a manner as to be in contact with the power supply line920.

Thereafter, as depicted inFIGS.19,42,46, and58, the cover films108are removed, the p-type semiconductor layers163are caused to epitaxially grow on the side surfaces of the nanosheets122, and the n-type semiconductor layers263are caused to epitaxially grow on the side surfaces of the nanosheets222. For example, boron (B) is introduced as a p-type impurity into the p-type semiconductor layers163using diborane (B2H6), and phosphorus (P) is introduced as an n-type impurity into the n-type semiconductor layers263using phosphine (PH3). Either the p-type semiconductor layers163or the n-type semiconductor layers263may be formed first. It is preferable that either the p-type semiconductor layers163or the n-type semiconductor layers263formed earlier are caused to grow while the cover films108are left unremoved on the side surfaces of either the nanosheets122or the nanosheets222on which either the p-type semiconductor layers163or the n-type semiconductor layers263formed later are caused to grow; and thereafter, the entirety of the cover films108are removed.

Subsequently, the insulating films63are formed, and the local wirings164in contact with the p-type semiconductor layers163and the local wirings264in contact with the n-type semiconductor layers263are formed. The local wirings164and264can be formed simultaneously. The local wirings164and264can be formed by, for example, forming conductive films and performing etching back thereon. Before forming the local wirings164and264, the contact holes312and322may be formed in the insulating films31and32, respectively, and one of the local wirings164may be formed in such a manner as to be in contact with the local wiring162, and one of the local wirings264may be formed in such a manner as to be in contact with the local wiring262.

Thereafter, as depicted inFIGS.21,34, and60, the SiGe films71to75are removed. As a result, spaces are created around the nanosheets121,122,221, and222.

Subsequently, as depicted inFIGS.22,35, and61, the gate insulating films130and230are formed around the nanosheets121,122,221, and222. The gate insulating films130and230can be formed by a deposition method such as a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The gate insulating films130and230are formed also on the surface of the substrate101or the like, but forming of the gate insulating films130and230there is not depicted in the drawings.

Next, as depicted inFIGS.23,36,43,47, and62, the gate electrodes110and210are formed; and, for example, the insulating films61and the like are polished until the upper surfaces of the walls50are exposed, and the upper surfaces of the gate electrodes110and210are planarized. Thus, the stacked transistor structure11is formed in the region10, and the stacked transistor structure21is formed in the region20.

Thereafter, as depicted inFIGS.24,37,44,48, and63, the insulating film64is formed, the contact holes313to316and323to326are formed, and the signal lines411to414and421to424are formed. Subsequently, the insulating film65is formed, the contact holes317to319and327to329are formed, and the signal lines431to433are formed.

Thereafter, upper-layer wirings and the like are formed if necessary to complete the semiconductor device100.

A circuit included in a semiconductor device according to an embodiment of the present disclosure is not limited to a buffer such as that described above in which two inverters are connected in series. Connecting relations with respect to local wirings and signal lines may be different from those in the embodiment described above, and, for example, a circuit in which two inverters are connected in parallel may be included in a semiconductor device according to an embodiment of the present disclosure, or a circuit in which two inverters independent from each other may be included in a semiconductor device according to an embodiment of the present disclosure.

First to fourth semiconductor regions may have the same conductivity types, and fifth to eighth semiconductor regions may have the same conductivity types. For example, the conductivity types of the semiconductor regions connected to the semiconductor layers (nanosheets) in contact with the side surface51may be all n-types, and the conductivity types of the semiconductor regions connected to the semiconductor layers (nanosheets) in contact with the side surface52may be all p-types. Further, the first to eighth semiconductor regions may have the same conductivity types.

The power supply lines910and920need not be embedded in the substrate101, and may be provided above the insulating film61, for example.

Although the present invention has been described based on the embodiments, the present invention is not limited to the requirements depicted in the above embodiments. These points can be changed without departing from the gist of the present invention, and can be appropriately determined according to the application form.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a depicting of the superiority and inferiority of the invention. Although the semiconductor devices and the semiconductor device manufacturing methods have been described with reference to the embodiments, it should be understood that the present invention is not limited to these embodiments, and various changes, substitutions, and alterations could be made thereto without departing from the spirit and scope of the present invention.