Memory and operation method of memory

A method for operating a memory includes: activating a first row, and sensing and amplifying, by a first bit line sense amplifier array, data of memory cells of the first row; transferring data of first columns of the first row from the first bit line sense amplifier array to global input/output lines through first input/output sense amplifiers; storing data of the global input/output lines in the first columns of a dummy bit line sense amplifier array through dummy write drivers; transferring data of second columns of the first row from the first bit line sense amplifier array to the global input/output lines through the first input/output sense amplifiers; and storing the data of the global input/output lines in the second columns of the dummy bit line sense amplifier array through the dummy write drivers.

BACKGROUND

Various embodiments of the present invention relate to a memory.

2. Description of the Related Art

Typically, a memory, such as a Dynamic Random Access Memory (DRAM), goes through a test process to detect a defect of the memory, after it is designed and fabricated.

If there is at least one defect in a great deal of memory cells of a memory, the memory cannot perform the desired function properly but is treated as a defective product. However, when there are only a few defective memory cells, it is inefficient in terms of yield to treat the memory as a defective memory. To address this problem, a method of providing redundant memory cells in the memory in a fabrication stage of the memory and replacing the defective memory cells of the memory with the redundant memory cells after the fabrication stage.

Post-package repair means repairing a memory after a package process. The post-package repair may be performed not only in the fabrication process of the memory, but also in the process when the memory is used by a user. In order to perform a post-package repair operation on the memory in use, it is preferable to copy the data of the defective memory cell into a redundant memory cell within the memory in use.

SUMMARY

Embodiments of the present invention are directed to a technique of internally copying data in a memory.

In accordance with an embodiment of the present invention, a method for operating a memory includes: activating a first row, and sensing and amplifying, by a first bit line sense amplifier array, data of memory cells of the first row; transferring data of first columns of the first row from the first bit line sense amplifier array to global input/output lines through first input/output sense amplifiers; storing data of the global input/output lines in the first columns of a dummy bit line sense amplifier array through dummy write drivers; transferring data of second columns of the first row from the first bit line sense amplifier array to the global input/output lines through the first input/output sense amplifiers; and storing the data of the global input/output lines in the second columns of the dummy bit line sense amplifier array through the dummy write drivers.

In accordance with another embodiment of the present invention, a memory includes: a first cell array; a second cell array; a first bit line sense amplifier array suitable for sensing and amplifying data of the first cell array; a second bit line sense amplifier array suitable for sensing and amplifying data of the second cell array; a dummy bit line sense amplifier array; global input/output lines; a first bus exchange circuit suitable for exchanging transferring data between the global input/output lines and local lines of the first bit line sense amplifier array; a second bus exchange circuit suitable for exchanging transferring data between the global input/output lines and local lines of the second bit line sense amplifier array; and a dummy bus exchange circuit suitable for exchanging transferring data between the global input/output lines and local lines of the dummy bit line sense amplifier array.

In accordance with yet another embodiment of the present invention, a semiconductor memory apparatus includes: a storage circuit including: first and second rows of memory cells, first and second bit line sense amplifier arrays coupled to the memory cells of the respective first and second rows in a column direction, and a buffer array coupled to the first and second bit line sense amplifier arrays; and a control circuit suitable for controlling the storage circuit to: copy data from the first row to the buffer array through the first bit line sense amplifier array, copy data from the buffer array to the second row through the second bit line sense amplifier array, and perform a repair operation of replacing the first row with the second row, wherein the first and second bit line sense amplifier arrays and the buffer array have the same data storage structure as one another.

In accordance with still another embodiment of the present invention, a semiconductor memory apparatus includes: a storage circuit including: first and second rows of memory cells, a bit line sense amplifier array coupled to the memory cells of the first and second rows in column direction, and a buffer array coupled to the bit line sense amplifier array; and a control circuit suitable for controlling the storage circuit to: copy data from the first row to the buffer array through the bit line sense amplifier array, copy data from the buffer array to the second row through the bit line sense amplifier array, and perform a repair operation of replacing the first row with the second row, wherein the bit line sense amplifier array and the buffer array have the same data storage structure as each other.

DETAILED DESCRIPTION

FIG. 1is a block diagram illustrating a memory100in accordance with an embodiment of the present invention.

Referring toFIG. 1, the memory100may include cell arrays111and113, bit line sense amplifier arrays121and123, a dummy bit line sense amplifier array125, bus exchange circuits131and133, and a dummy bus exchange circuit135.

Each of the cell arrays111and113may include memory cells that are arranged in a plurality of rows and a plurality of columns. Although two cell arrays111and113are shown in the figure as an example, a large number of cell arrays may exist in the memory100.

The bit line sense amplifier arrays121and123may sense and amplify the data of the cell arrays111and113. The bit line sense amplifier array121may sense and amplify the data of the cell array111, and the bit line sense amplifier array123may sense and amplify the data of the cell array113.

The dummy bit line sense amplifier array125may be formed the same as the bit line sense amplifier arrays121and123. During a data copy operation, the dummy bit line sense amplifier array125may serve as a buffer rather than sensing and amplifying data of a cell array. The dummy bit line sense amplifier array125may be positioned at an edge of a region where the cell arrays111and113are disposed.

The bus exchange circuit131may be provided for data exchange between the global input/output lines GIO and the local lines LOCAL_0on the side of the bit line sense amplifier array121. The global input/output lines GIO may include N lines, where N is an integer equal to or greater than 2, and the local lines LOCAL_0may include 2N lines. The global input/output lines GIO may transfer data in a single-ended method, and the local lines LOCAL_0may transfer data in a differential method. For this reason, the number of the local lines LOCAL_0may be twice as many as the number of the global input/output lines GIO. The global input/output lines GIO may be lines for transferring data between an area where data are transferred/received between the memory100and the outside and areas where data are stored in the memory100.

The bus exchange circuit133may be provided for data exchange between the global input/output lines GIO and the local lines LOCAL_1on the side of the bit line sense amplifier array123. Also, the dummy bus exchange circuit135may be provided for data exchange between the global input/output lines GIO and the local lines LOCAL_D on the side of the dummy bit line sense amplifier array125. The dummy bus exchange circuit135may be formed the same as the bus exchange circuits131and133.

FIG. 2is a block diagram illustrating the bus exchange circuit131shown inFIG. 1in accordance with an embodiment of the present invention.

Referring toFIG. 2, the bus exchange circuit131may include a plurality of input/output sense amplifiers (IOSA)211and212and a plurality of write drivers (WDRV)221and222.

The write drivers221and222may transfer the data of the global input/output lines GIO to the local lines LOCAL_0. The write drivers221and222may be used during a write operation of the memory100and a data copy operation, which will be described later. The write driver221may amplify the data of the global input/output line GIO_0and transfer the amplified data to the local lines LOCAL_0_0and LOCAL_0_1B. Also, the write driver222may amplify the data of the global input/output line GIO_1and transfer the amplified data to the local lines LOCAL_0_1and LOCAL_0_1B. The number of the write drivers221and222may be the same as the number of the global input/output lines GIO.

The bus exchange circuit133and the dummy bus exchange circuit135may be formed the same as the bus exchange circuit131shown inFIG. 2.

FIG. 3is a block diagram illustrating the bit line sense amplifier array121shown inFIG. 1in accordance with an embodiment of the present invention.

Referring toFIG. 3, the bit line sense amplifier array121may include a plurality of sense amplifiers301to312and a plurality of switch arrays320,330and340. Herein, it is illustrated that the number of the local lines LOCAL_0_0and LOCAL_0_0B to LOCAL_0_3and LOCAL_0_3B is eight however any number of local lines may be used.

The switch arrays320,330, and340may control the coupling between the local lines LOCAL_0_0and LOCAL_0_0B to LOCAL_0_3and LOCAL_0_3B and the bit line sense amplifiers301to312. Each of the switch arrays320,330, and340may include eight switches. Among the switch arrays320,330, and340, a switch array selected based on a column address may be turned on. When the switch array320is turned on, the local lines LOCAL_0_0and LOCAL_0_0B to LOCAL_0_3and LOCAL_0_3B and the bit line sense amplifiers301to304may be electrically connected to transfer data. When the switch array330is turned on, the local lines LOCAL_0_0and LOCAL_0_0B to LOCAL_0_3and LOCAL_0_3B and the bit line sense amplifiers305to308may be electrically connected to transfer data. Likewise, when the switch array340is turned on, the local lines LOCAL_0_0and LOCAL_0_0B to LOCAL_0_3and LOCAL_0_3B and the bit line sense amplifiers309to312may be electrically connected to transfer data.

Each of the bit line sense amplifiers301to312may sense and amplify a potential difference between both ends of a bit line pair. In the figure, the lines extending to the top of the bit line sense amplifiers301to312may represent bit lines.

The bit line sense amplifier array123may be formed the same as the bit line sense amplifier array121shown inFIG. 3. The dummy bit line sense amplifier array125may be formed the same as the bit line sense amplifier array121, except that the bit lines are not coupled.

Referring toFIGS. 1 to 3, the memory100is illustrated to have a folded bit line structure, but the memory100may also have an open bit line structure, instead of a folded bit line structure.

FIG. 4is a flowchart describing a process of copying data of one row of the cell array111into another row of the cell array113in accordance with an embodiment of the present invention. A data copy operation may be used to copy the data of a defective row into a redundant row and may be used in other cases. Hereinafter, a process of performing a repair operation in which the data of a defective row are copied into a redundant row and the defective row is replaced with the redundant row will be described. The process illustrated inFIG. 4may be performed by the memory100under the control of a memory controller (not illustrated).

Referring toFIG. 4, the memory100may receive a command commanding to copy data in operation401. Along with the command commanding data copying, an address designating a defective row and an address designating a redundant row into which the data of the defective row are to be moved may be received.

A target row may be activated in operation403. The target row may mean a defective row whose data are required to be copied. A row in which a defect is detected during the operation of the memory100may become a target row. Herein, the target row is a fifth row of the cell array111. The fifth row may be activated in the cell array111, and the data stored in the memory cells of the fifth row may be sensed and amplified by the bit line sense amplifiers of the bit line sense amplifier array121. When the target row is activated, the bit line sense amplifiers of the dummy bit line sense amplifier array125may also be activated.

The data of the bit line sense amplifier array121may be moved to and stored in the dummy bit line sense amplifier array125in operation405. The data of the bit line sense amplifier array121may be transferred to the global input/output lines GIO through the input/output sense amplifiers211and212of the bus exchange circuit131, and the data of the global input/output lines GIO may be transferred to and stored in the dummy bit line sense amplifier array125through the write drivers of the dummy bus exchange circuit135.

The entire data of the bit line sense amplifier array121may not be moved to and stored in the dummy bit line sense amplifier array125at once. This is because there is a limit to the number of the input/output sense amplifiers in the bus exchange circuit, the global input/output lines, and the write drivers of the dummy bus exchange circuit. Data of the bit line sense amplifiers corresponding to one switch array (e.g., the array320ofFIG. 3) among the switch arrays (e.g., the arrays320to340ofFIG. 3) may be moved from the bit line sense amplifier array121at a time.

An operation of moving and storing the data of the bit line sense amplifier array121to and in the dummy bit line sense amplifier array125may be performed several times while changing a column address through operation407.

When all data of the bit line sense amplifier array121are moved to the dummy bit line sense amplifier array125, that is, when the operation of moving the data of all columns is completed (Y in operation S409), the target row may be precharged in operation411. When the target row (e.g., the fifth row) is precharged, the target row may be deactivated and the bit line sense amplifier array121may be deactivated. In other words, the bit line sense amplifiers301to312of the bit line sense amplifier array121may be deactivated.

Now, the redundant row of the cell array113may be activated in operation413. A redundant row may mean an extra row to replace a defective row. When the redundant row is activated in the cell array113, the data stored in the memory cells of the redundant row may be sensed and amplified by the bit line sense amplifiers of the bit line sense amplifier array123.

Now, the data of the dummy bit line sense amplifier array125, that is, the data copied from the target row, may be moved to and stored in the bit line sense amplifier array123in operation415. The data of the dummy bit line sense amplifier array125may be transferred to the global input/output lines GIO through the input/output sense amplifiers of the dummy bus exchange circuit135, and the data of the global input/output lines GIO may be transferred to and stored in the bit line sense amplifier array123through the write drivers221and222of the bus exchange circuit133. Since the redundant row is activated in the cell array113, the data of the bit line sense amplifier array123may be directly written into the redundant row of the cell array113.

Since the entire data of the dummy bit line sense amplifier array125cannot be moved to and stored in the bit line sense amplifier array123at one time, the operation of moving the data of the dummy bit line sense amplifier array125into the bit line sense amplifier array may be performed several times while changing the column address through operation417.

When all data of the dummy bit line sense amplifier array125are moved to the bit line sense amplifier array123, that is, when the operation of moving the data of all columns is completed (Y in operation S419), the redundant row of the cell array113may be precharged in operation421. When the redundant row is precharged in the cell array113, the redundant row may be deactivated, and the bit line sense amplifiers of the bit line sense amplifier array123may be deactivated. Also, the dummy bit line sense amplifier array125may be deactivated. In short, the bit line sense amplifiers in the dummy bit line sense amplifier array125may be deactivated.

A repair operation of replacing the target row of the cell array111with the redundant row of the cell array113may be performed in operation423since all the data of the defective target row in the cell array111are copied into the redundant row of the cell array113. This repair operation may be a post package repair (PPR) operation.

InFIG. 4, an operation of copying the data of the target row of the cell array111into the redundant row of the cell array113is described. That is, the operation of copying data between different cell arrays111and113is described. This operation can also be performed within the same cell arrays.

The operation of copying the data of the target row of the cell array111into the redundant row of the cell array111may include (1) activating the target row of the cell array111and sensing and amplifying data of the target row by using the bit line sense amplifier array121, (2) moving the data of the bit line sense amplifier array121to the dummy bit line sense amplifier array125, (3) precharging the target row of the cell array111, (4) activating the redundant row of the cell array111and sensing and amplifying data of the redundant row by using the bit line sense amplifier array121, (5) moving the data of the dummy bit line sense amplifier array125to the bit line sense amplifier array121, and (6) precharging the redundant row of the cell array111.

Also, the operation of copying the data of the target row of the cell array113to the redundant row of the cell array113may include (1) activating the target row of the cell array113and sensing and amplifying data of the target row by using the bit line sense amplifier array123, (2) moving the data of the bit line sense amplifier array123to the dummy bit line sense amplifier array125, (3) precharging the target row of the cell array113, (4) activating the redundant row of the cell array113and sensing and amplifying data of the redundant row by using the bit line sense amplifier array123, (5) moving the data of the dummy bit line sense amplifier array125to the bit line sense amplifier array123, and (6) precharging the redundant row of the cell array113.

According to the embodiments of the present invention, it is possible to easily copy the data of a particular row to another row in a memory. Therefore, even though a defective row is detected in the memory, the memory may be repaired without losing data by performing a repair operation of copying the data of the defective row into the redundant row, and replacing the defective row with a redundant row.

According to the embodiment of the present invention, data may be efficiently copied internally in a memory.

While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. Furthermore, the embodiments may be combined to form additional embodiments.