Methods and apparatus for bridged data transmission and protocol translation in a high serialized data system

An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PHY.

FIELD OF THE INVENTION

The present invention relates broadly to devices connected to a high-speed serial bus. Specifically, the present invention relates to bridging data transmission between IEEE 1394-compliant devices and Ethernet-compliant devices.

BACKGROUND

A “bus” is a collection of signals interconnecting two or more electrical devices that permits one device to transmit information to one or more other devices. There are many different types of buses used in computers and computer-related products. Examples include the Peripheral Component Interconnect (“PCI”) bus, the Industry Standard Architecture (“ISA”) bus and the Universal Serial Bus (“USB”), to name a few. Bus operation is usually defined by a standard that specifies various concerns such as the electrical characteristics of the bus, how data is to be transmitted over the bus, how requests for data are acknowledged, and the like. Using a bus to perform an activity, such as transmitting data, requesting data, etc., is generally called running a “cycle.”Standardizing a bus protocol helps to ensure effective communication between devices connected to the bus, even if such devices are made by different manufacturers. Any company wishing to make and sell a device to be used on a particular bus, provides that device with an interface unique to the bus to which the device will connect. Designing a device to particular bus standard ensures that device will be able to communicate properly with all other devices connected to the same bus, even if such other devices are made by different manufacturers.

Thus, for example, an internal fax/modem (i.e., internal to a personal computer) designed for operation on a PCI bus will be able to transmit and receive data to and from other devices on the PCI bus, even if each device on the PCI bus is made by a different manufacturer.

Problems occur when devices located on buses or networks using different low-level protocols are made to communicate with each other. One example involves two very popular standards, the IEEE 1394 family of serial bus protocols, and the IEEE 802.3 family of Ethernet network protocols. Despite the fact that there are versions of both protocols that use the same cables and connectors, and both support the higher level “Internet Protocol” (IP), devices implementing the Ethernet-compliant network interface are unable to communicate with devices implementing the 1394-compliant bus interface because of the differences existing between the respective protocols. Because of the large number of existing devices that use one protocol or the other, this communication gap is likely to widen as standards are developed in the two protocols. Thus, there is a heartfelt need for a solution that bridges the communication gap between protocols and effectively allows devices to communicate with each other across different bus or networking architectures.

SUMMARY

In one aspect of the present invention, and apparatus is disclosed. In one embodiment, the apparatus includes: a first interface operating according to a first protocol; at least one second interface, the at least one second interface adapted to operate according to a second protocol, the first interface configured to operate within a first clock domain, and the at least one second interface configured to operate within a second clock domain; a translation apparatus in signal communication with both the first and at least one second interfaces, the translation apparatus adapted to translate between the first and second protocols; wherein the translating apparatus is further adapted to compensate for differences between the first and second clock domains; a bridging apparatus adapted to provide logical network addressing for devices connected to the first interface and the at least one second interface; and apparatus enabling, responsive to a negotiation, the translation apparatus or the bridging apparatus.

In another embodiment, the apparatus includes: a first interface adapted to operate according to a first data protocol; a second interface, the second interface adapted to operate according to a second data protocol that is different than the first data protocol; a translation apparatus in data communication with both the first and second interfaces, the translation apparatus adapted to translate between the first and second data protocols; a bridging apparatus adapted to provide logical network addressing for a first apparatus in data communication with the first interface and a second apparatus in data communication with the second interface; and routing apparatus configured to, responsive to a negotiation sequence, route data via the translation apparatus or the bridging apparatus. The second interface is adapted to detect at least one null symbol, the null symbol being used to at least in part determine symbol synchronization.

In yet another embodiment, the apparatus includes a first interface adapted to operate according to a first data protocol and within a first clock domain; a second interface, the second interface adapted to operate according to a second data protocol that is different than the first data protocol and within a second clock domain; arbitration apparatus in data communication with both the first and second interfaces, the arbitration apparatus adapted to arbitrate transmit and receive operations so as to provide unidirectional data flow between the first interface and the second interface; a bridge apparatus adapted to provide network addressing for a first apparatus in data communication with the first interface and a second apparatus in data communication with the second interface; routing apparatus configured to, responsive to a negotiation sequence, route data via at least one of arbitration apparatus and/or the bridge apparatus; and a translating apparatus in data communication with the first and second interfaces and adapted to compensate for differences between the first and second clock domains.

In another aspect of the present invention, a method for providing data communication between electronic devices is disclosed. In one embodiment, the method includes: providing first and second interfaces, the first interface being associated with a first protocol, the second of the interface being associated with a second protocol, and the second interface being adapted to operate with multiple different protocols including the second protocol; performing a negotiation process; responsive to the negotiation process, either: translating data sent from the first interface to the second interface from the first protocol to the second protocol, or translating data sent from the second interface to the first interface from the second protocol to the first protocol; and arbitrating serial accesses from the first interface to the second interface; or establishing data communication between the first and second interface via a bridge apparatus, the bridge apparatus providing network addressing capabilities for the first and second devices.

In another aspect, a method of communicating data is disclosed. In one embodiment, the communicating is between a first data interface adapted to operate according to a first data protocol and a second data interface adapted to operate according to a second data protocol that is different than the first data protocol, and the method includes: negotiating whether data should be routed over a first path or a second path, and responsive to the negotiating, routing the data via the first path or the second path. In one variant, the first path includes apparatus for arbitration of transmit and receive operations so as to provide unidirectional data flow selectively between the first interface and the second interface, and the second path includes a bridge apparatus adapted to provide networking for a first apparatus in data communication with the first interface, and a second apparatus in data communication with the second interface. In another variant, the routing the data over the bridging apparatus includes: receiving data encoded according to the first data protocol; assembling the data into a plurality of packets via at least one first protocol layer; transmitting the packets to at least one second protocol layer; assembling a plurality of symbols from the received packets; and transmitting the received packets to the second first interface.

Other features and advantages of the present invention will become apparent from reading the following detailed description, when considered in conjunction with the accompanying drawings.

SUMMARY OF THE INVENTION

Various embodiments of the present invention utilize a 1000 BASE-T PHY that transmits and receives at no less than 0.9999 gbit/sec, and a 1394b PHY having a cable interface that utilizes a bit stream rate of no more than 0.98304+100 ppm=0.9831383 gbit/sec. Thus, the fastest S800 1394b transmission rate can be accommodated by the slowest 1000 BASE-T stream.

In an embodiment, the present invention upshifts an S800 1394b stream by inserting an illegal symbol within the transmit stream approximately once for every 59 regular symbols. In an embodiment, the illegal symbol is either all ones or all zeros since those are the furthest Hamming distance from 1394b control symbols or data symbols. In various embodiments, insertion of this illegal symbol can be performed at a fixed rate, or by utilizing a one-symbol FIFO that is fed by the 1394b transmitting port and drained by the 1000 base TX PHY. In this embodiment, when the FIFO underflows, the extra symbol is generated. On receive, the same approach can be followed. In an embodiment, a FIFO is centered at the start of a packet.

In another embodiment of the present invention, the 1000 base-T transmit stream requires a number of Ethernet IDLE symbols to appear periodically. A small transmit FIFO is provided and, when it underflows, transmission of the 1394b symbols is halted and the 1000 base TX PHY is instructed to transmit Ethernet IDLE symbols for 11 Ethernet symbol times. During this time, the transmit FIFO is filling. After the 11 Ethernet symbol times has passed, transmission of 1394b symbols is resumed. Insertion of these idle symbols satisfies a requirement for 1000 base T transmission.

Directing attention toFIG. 1, a functional representation of an embodiment of the present invention is provided. The functional elements illustrated inFIG. 1can be incorporated into a node device that communicates over a serial bus as described above to allow a user to implement a variety of Internet-based functions over a 1394-compliant bus architecture. Integrated PHY chip100includes 802.3 clause 40 PHY102having external connection103and GMII interface104, and integrated 1394 PHY106, having at least one external connector107, controllably connected to 802.3 Clause 40 PHY102. 1394 PHY106includes at least one 1394 port108, each having a FIFO110for delivering bits, characters, or symbols to 1394 arbitration and data repeat module112. Also included in 1394 PHY106is port114, which also communicates bits, characters or symbols to 1394 arbitration and data repeat module112via FIFO116. In an embodiment, FIFO116is sized larger than FIFO110to accommodate additional latencies experienced on port114. Port114also connects to 802.3 Clause 40 PHY102via a switch118. In an embodiment, switch118is controllably set between port114and GMII interface104according to an autonegotiation process described herein. 1394 arbitration and data repeat module112performs bus arbitration as well as routing data received between link layer interface122and/or ports108,114. Arbitration is handled by module112to determine whether PHY106is to transmit over a connected serial bus or receive data over the serial bus. Link layer124assembles a stream of symbols received over link layer interface122into packets that are transmitted forward over protocol layer126. Conversely, link layer124translates packets received from protocol layer126into a stream of symbols that can be passed to the link layer interface122. In an embodiment, link layer124and protocol layer126are implemented on a shared chip128. IP 1394 firmware module130includes logic for implementing application-specific protocols that transport Internet protocol (IP)-format packets over 1394 hardware and logic. IP bridge firmware module132bridges packets transmitted between IP bridge firmware module132and implements a separate IP subnet or an 802.3 subnet and bridges communication between these two types of subnets according to IP standards. Alternatively, IP bridge firmware module132manages a common subnet between 802.3 Clause 40 PHY102and 1394 PHY106and ensures that IP addressing of transmitted packets is distinct. The GMII side of the present invention includes 802.3 IP firmware module134, that performs similar functions for 802.3 Claude 40 PHY102as IP 1394 firmware module130provides for 1394 PHY106, and chip138, containing GMII side 802.3 protocol layer module140and 802.3 media access card (MAC)142, which perform similar functions for the GMII side as 1392 protocol layer126and 1394 link layer module124perform for the 1394 side, respectively.

Directing attention toFIG. 2, port114can be conceptualized has having a 1394 arbitration side of functionality and a GMII side of functionality. In an embodiment, FIFO200is included on port114, and in combination with register202and register204, and modulo 5 counter206is used to extract 10-bit symbols from the 1394 side of port114and process portions of the extracted symbols into 8-bit characters to be transmitted to GMII interface104, thus bridging communication between a 1394-compliant system and a gigabit Ethernet systems. In an embodiment, registers208and210are provided for assembly of 10-bit symbols from 8-bit characters arriving from GMII interface104over connection120. However, in another embodiment, these 10-bit symbols can be assembled using registers202and204.

Directing attention toFIG. 3, autonegotiation selects whether an Ethernet or a protocol from the 1394 family of protocols is to be used on the connection thus determining the selection made by switch118. In this embodiment, the 1394 side runs off the same 125 MHz clock as is provided by GMII interface104. The 1394 side of port114generates 10-bit symbols using a 98.304 MHz clock and pushes them into FIFO200using this clock. At the other end of FIFO200, TX Adaptation module220extracts the 10-bit symbols from FIFO200using the GMII 125 MHz clock and modulo 5 counter206. Modulo 5 counter206supplies values ranging from 0 to 4. If the modulo 5 counter reads 0, then a 10-bit symbol is extracted, but only eight bits of it are used. In an embodiment, the assembled 8-bit character can be retained in register204until transmitted to GMII interface104. The remaining two bits are retained in register202for use on the next GMII clock signal. If modulo 5 counter206reads 1, then a 10-bit symbol is extracted, but only six bits of it are used and what is transmitted combines the two bits stored in register202plus these six extracted bits. This results in four bits being left over, which are stored in register202. If modulo 5 counter206reads 2, then the four left-over bits from register202are combined with four bits from the next 10-bit symbol that is extracted from FIFO200, resulting in six bits being left over from the extracted 10-bit symbol. These remaining six bits are retained in register202. If modulo 5 counter206reads 3, then the six bits in register202are combined with two bits from the next extracted symbol, and the remaining eight bits are stored in register202. If modulo 5 counter206reads 4, then no new symbol is extracted, and the eight left over bits are sent over GMII interface104. If modulo 5 counter206has a zero value, then the 1394 side of port114does not push a 10-bit number into FIFO200. PHY102ensures that the GMII RX clock is locked to the GMII TX clock. If no symbol is available in FIFO200, TX Adaptation module220inserts an illegal or null 10-bit symbol into FIFO200.

For translation of data in the opposite direction, where 10-bit symbols are formed from 8-bit characters, synchronization characters (i.e. illegal characters) force the value of modulo 5 counter206to zero and hold it there. The first valid 8-bit character that is received via connection120is copied into register208with the counter value still at zero, so the 1394 side of port114takes no action. The next 8-bit character received over connection120is placed in register210. The 1394 side of port114assembles a 10-bit symbol by taking the eight bits from register208, appending two bits from register210, and treating the resulting 10-bit symbol as if it had been received on 1394b port108. Most such symbols are pushed into the bport RX FIFO, while others, such as repeated request or control symbols, and illegal symbols are ignored. RX Adaptation module222deletes the null or illegal 10-bit symbols, and uses the deletion frequency to control the RX symbol clock phase locked loop. Thus, the RX symbol clock is phase locked to the TX symbol clock. Elasticity FIFO224compensates for ppm differences between the two PHY clocks. The resulting 10-bit symbol is pushed into FIFO116, where conventional 1394b deletable symbols functionality prevents bport FIFO underflow and overflow. In an embodiment FIFO116is sized slightly larger than FIFO110to compensate for the “4inarushthenawait” symbol arrival characteristics. The remaining bits from register210are then stored in register208, and the next 8-bit byte received is stored in register210. Assembly of 10-bit symbols continues by using all of the bits from register208, and appending any bits needed from register210to form the 10-bit symbol. This 10-bit symbol process continues until register210is emptied upon appending bits, at which point the process repeats itself by storing an 8-bit byte in both registers208,210again.

The relationship between 10-bit symbols and 8-bit characters can be conceptualized as illustrated inFIG. 4. In an embodiment, port114can include four 10-bit registers on the 1394 side of port114(reference numeral250), and five 8-bit registers on the GMII side of port114(reference numeral252), as illustrated inFIG. 5. In an embodiment, symbol transmission begins with transmission of an illegal symbol to synchronize four 10-bit registers on the 1394b side of port114with the five 8-bit registers on the GMII side of port114. In this manner, a 10-bit symbol transmitted immediately after an illegal symbol is received as a valid 10-bit symbol. A clock domain crossing transmit FIFO bridges the 1394b PHY clock (running at 98 MHz, in an embodiment) and the 1000 base clock domains. When the clock domain crossing FIFO drains below a predetermined threshold such that it will underflow after the next five symbols are transmitted, an illegal symbol is fed into the clock domain crossing FIFO.

In an embodiment of the present invention, training and operation symbols are transmitted to support scrambler synchronization and a port synchronization handshake and can utilize K28.5 substitution. Rather than GHz logic, or phase locked loops, the present invention utilizes single clock synchronous logic in the receiver on PHY106. Bytes are presented to port114from GMII interface104synchronously to GMII interface104's RX clock (running at 125 MHz, in an embodiment), and, unlike conventional 1394b ports, there is no requirement for any high-speed bit receive logic or clock recovery in port114. The K28.5 symbol in the IBM 8B10B code is a symbol used in normal operation that contains a special “comma” pattern sequence, denoted as 0011111 or 110000, depending on disparity. When a receiver initializes upon start up, it is unaware of where the 10-bit boundaries occur in an incoming bit stream. But when it recognizes a received K28.5 symbol (the comma sequence), it can use this symbol to determine the 10-bit boundary, and thus acquire symbol synchronization. 1394b-compliant devices perform symbol synchronization by performing K28.5 substitution, replacing D28.0 symbols with K28.5 symbols. The receiver uses the K28.5 symbol to acquire symbol synchronization, and also substitutes back the D28.0 symbol for any K28.5 symbols it finds in the stream. 1394b-compliant devices send a training symbol request as the first symbol on a port. This training symbol is scrambled, and the resulting 8B10B data symbol is transmitted. Scrambling the training symbol ensures that periodically the received data symbol is a D28.0 symbol, and the K28.5 substitution can be performed.

When port114has acquired symbol and scrambler synchronization, it changes the symbol it is transmitting to an operation symbol. This operation symbol conveys another request, and is scrambled onto 8B10B data symbols in just the same way. As a result of scrambling, a D28.0 symbol is still due to be transmitted occasionally, and K28.5 substitution is performed.

When port114is both transmitting and receiving operation request symbols, it is synchronized to its peer node, and also made aware that the peer node is synchronized to port114. Port training is now considered complete, and port114is ready to transmit requests, control symbols, and data in its support of the 1394 protocols. The 5-to-4 relationship between states on the 1394b side and states on the GMII side of port114can be illustrated inFIG. 5. In an embodiment, port114utilizes five 8-bit registers (as seen on the GMII side of port114) a, b, c, d and e, which correspond to four 10-bit registers on the 1394b side of port114. On the GMII side of port114, each successive 8-bit character is pushed into register a, b, c, d or e using a value read from modulo 5 counter206at intervals denoted by the RX clock on GMII interface104. On the 1394b side of port114, 10-bit data is pulled from the GMII side of port114using a clock that runs at ⅘ of the GMII RX clock frequency (100 MHz in an embodiment). This clock increments modulo 5 counter206for each symbol read. The successive values read are a[7:0]∥b[7:6], b[5:0]∥c[7:4], c[3:0]∥d[7:2] and finally d[1:0] ∥e[7:0].

Clocking appears as shown in Table 1.

In an embodiment, illegal symbols are transmitted after the 0 modulo 5 symbols have been transmitted since the last illegal symbol was transmitted, and are also used to synchronize the four 10-bit registers on the 1394b side with the five 8-bit registers on the GMII side. Read and write clock pulses are aligned with the necessary phase offset for the first symbol received after a synchronizing symbol, and the read and write selectors reset to point to register “a” for write and register “ab” for read. The first 10-bit symbol is read one read clock pulse later, after values have been written to both registers a and b. While the four 10-bit registers and five 8-bit registers are synchronizing with each other, no symbols are read out, nor are any 10-bit symbols pushed into the bport RX FIFO using the 100 MHz clock.

The present invention implements the 8-bit GMII interface104as a serial interface, by shifting a byte into the 10-bit register on the 1394b side using serial interface FIFO200. Whenever an illegal symbol is shifted into 10-bit register, it is deleted from FIFO200. The illegal symbol can be inserted into any stream, and deleted at the other end, even without byte/symbol synchronization.

Directing attention toFIG. 6, in another embodiment, the present invention can be implemented without RX symbol clock recovery. In this embodiment, the RX clock on PHY102is locked to the TX clock on PHY102. 10-bit symbols are placed in FIFO200using flagged encoding. TX adaptation module220extracts the 10-bit symbols from FIFO200and places them in registers202,204. In this embodiment, 802.3-compliant idle bytes are used rather than inserting 10-bit null or illegal symbols. If there is no-symbol available in FIFO200, then TX Adaptation module220de-asserts a transmit enabled state (TX_EN) on GMII interface104for 11 clock periods, which causes PHY102to insert 802.3-compliant idle bytes. This embodiment thus meets a requirement in the 802.3 standard to periodically insert idle bytes. If there is no symbol in FIFO200then TX-EN is de-asserted on PHY102for 11 clock periods, which causes PHY102to insert the idle bytes. In this embodiment, FIFO200is appropriately sized to buffer nine 10-bit symbols that accumulate during the 11 clock periods. On the receive side, RX Adaptation module222only takes data from GMII interface104when receive data valid (RX_DV) is asserted, which is not asserted when 802.3-compliant idle bytes are being received. Using flagged decoding, 10-bit decoded symbols are pushed into the receive FIFO when available when available. Usually, this occurs on four out of every five clock cycles, but with bursts of 11 clocks with no push when RX_DV is de-asserted. In an embodiment, elasticity FIFO224handles both the ppm differences between PHY106and PHY102, as well as the frequency difference between the 802.3 bit rate and the 1394 S800 bit rate. Elasticity FIFO224thus must be at least nine symbols deeper than used in 1394b implementations to compensate for the bursty nature of reception. However, in this embodiment, there is no need for PHY102to recover the TX symbol clock.

Directing attention toFIG. 7, in yet another embodiment, robust encoding is realized, which implements TX adaptation phase knowledge. PHY102ensures that the GMII RX clock is locked to the GMII TX clock. Robust encoding module230takes a 10-bit symbol from FIFO200on four out of every five GMII TX clocks, and uses TX Adaptation module220to determine the encoding to be used, thus generating a 10-bit encoded symbol. TX Adaptation module220places the extracted symbol into registers202,204to generate on every GMII TX clock an 8-bit byte as described above. If there is no symbol available in FIFO200, then robust encoding module230instructs TX Adaptation module220accordingly. TX Adaptation module220de-asserts TX_EN on GMII interface104for 11 clock periods, which causes PHY102to insert 802.3-compliant idle bytes. FIFO200is appropriately dimensioned to buffer nine symbols.

The receive side in this embodiment is similar to the receive side illustrated inFIG. 6and explained above, with the addition of robust decoding module232. Robust decoding module232decodes the 10-bit symbols that result from RX Adaptation module222's conversion to 10-bit, encoded symbols from 8-bit, encoded bytes received from PHY102.

While numerous methods and apparatus for transmitting 1394-compliant symbols using a gigabit Ethernet PHY have been illustrated and described in detail, it is to be understood that many modifications may be made to embodiments of the present invention without departing from the spirit thereof.