Method and system for supporting multiple cache configurations

A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

BACKGROUND OF THE INVENTION

Referring toFIG. 1, an electrical coupling network between a static random access memory20a(hereinafter “SRAM20a”) and a static random access memory20b(hereinafter “SRAM20b”) is shown. SRAM20aand SRAM20bare identical memory devices. Specifically, both SRAM20aand SRAM20bhave an identical pin arrangement including seven (7) rows and seventeen (17) columns of pins. The first column of pins are shown inFIG. 1. In the first column of pins, SRAM20aincludes two (2) output power supply pins21aand27a, and SRAM20bincludes two (2) output power supply pins21band27b. Also in the first column of pins, SRAM20aincludes four (4) synchronous address input pins22a,23a,25a, and26a, and SRAM20bincludes four (4) synchronous address input pins22b,23b,25b, and26b. Pin24aof SRAM20aand pin24bof SRAM20bare not utilized.

In support of four (4) cache configurations, SRAM20ais mounted to a front side of a processor card10, and SRAM20bis mounted to a rear side of processor card10. SRAM20aand SRAM20bare positioned with an alignment of pin21aand pin27b, an alignment of pin22aand pin26b, an alignment of pin23aand pin25b, an alignment of pin24aand pin24b, an alignment of pin25aand pin23b, an alignment of pin26aand pin22b, and an alignment of pin27aand pin21b.

Pin22aand pin22bare functionally equivalent and electrically coupled via a conductor28awithin processor card10to concurrently receive a first address bit signal from a microprocessor. Pin23aand pin23bare functionally equivalent and electrically coupled via a conductor28bwithin processor card10to concurrently receive a second address bit signal from the microprocessor. Pin25aand pin25bare functionally equivalent and electrically coupled via a conductor28cwithin processor card10to concurrently receive a third address bit signal from the microprocessor. Pin26aand pin26bare functionally equivalent and electrically coupled via a conductor28dwithin processor card10to concurrently receive a fourth address bit signal from the microprocessor. The four (4) address bits signal are selectively provided by the microprocessor as a function of a selected cache configuration.

A drawback associated with the aforementioned electrical couplings as shown is the length of conductors28a–28dtends to establish a maximum frequency at which the microprocessor can effectively and efficiently control SRAM20aand SRAM20b, and the established maximum frequency can be significantly lower than a desired operating frequency of the microprocessor. The computer industry is therefore continually striving to improve upon the electrical coupling between the synchronous address input pins of SRAM20aand SRAM20bwhereby a maximum frequency at which a microprocessor can effectively and efficiently control SRAM20aand SRAM20bmatches a desired operating frequency of the microprocessor. The computer industry is also continually striving to improve upon the electrical communication of a selected cache configuration from a microprocessor to the synchronous address input pins of SRAM20aand SRAM20b.

FIELD OF THE INVENTION

The present invention generally relates to computer hardware mounted upon a processor card, and in particular to an electrical coupling between memory components for supporting multiple cache configurations and an electrical communication from a microprocessor to the memory components for selecting one of the supported multiple cache configurations.

SUMMARY OF THE INVENTION

One form of the present invention is a processor card having a first memory device and a second memory device mounted thereon. The first memory device includes a first address pin and a second address pin. The second memory device includes a third address pin and a fourth address pin. The first address pin of the first memory device and the third address pin of the second memory device are functionally equivalent address pins. The second address pin of the first memory device and the fourth address pin are functionally equivalent address pins. The first address pin of the first memory device and the fourth address pin of the second memory device are electrically coupled to thereby concurrently receive a first address bit signal. The second address pin of the first memory device and the third address pin of the second memory device are electrically coupled to thereby concurrently receive a second address bit signal.

Another form of the present invention is a system including a first memory device, a second memory device, and a microprocessor. The first memory device includes a first address pin and a second address pin. The second memory device includes one address pin and a fourth address pin. The first address pin of the first memory device and the third address pin of the second memory device are functionally equivalent address pins. The second address pin of the first memory device and the fourth address pin are functionally equivalent address pins. The microprocessor is operable to concurrently provide a first address bit signal to first address pin of the first memory device and the fourth address pin of the second memory device. The microprocessor is further operable to concurrently provide a first address bit signal to second address pin of the first memory device and the third address pin of the second memory device.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

Referring toFIG. 2, SRAM20aand SRAM20bare mounted upon processor card10as previously described in connection withFIG. 1. In accordance with the present invention, pin22aand pin26bare electrically coupled via a conductor29awithin processor card10to concurrently receive a first address bit signal. Pin23aand pin25bare electrically coupled via a conductor29bwithin processor card10to concurrently receive a second address bit signal. Pin25aand pin23bare electrically coupled via a conductor29cwithin processor card10to concurrently receive a third address bit signal. Pin26aand pin22bare electrically coupled via a conductor29dwithin processor card10to concurrently receive a fourth address bit signal. The length of the conductors29a–29dfacilitate an effective and efficient operation of SRAM20aand SRAM20bover a wide range of operating frequencies of a microprocessor.

Referring toFIG. 3A, a microprocessor30in accordance with the present invention for selecting between two (2) of the four (4) cache configurations supported by SRAM20aand SRAM20bis shown. Microprocessor30includes main logic units31for interpreting and executing operating and application programs as would occur to one skilled in the art. Microprocessor30further includes a controller32and a multiplexer33. Address bus32aand address bus32bprovide electrical communication between controller32and multiplexer33. Address bus32aand address bus32beach have two (2) address lines. Multiplexer33has an address bus33awith a first address line electrically coupled to pin22a(FIG. 2) and pin26b(FIG. 2), and a second address line electrically coupled to pin26a(FIG. 2) and pin22b(FIG. 2). The following Table 1 exemplary illustrates an address bit logic utilized by main logic units31for electrically communicating a selected cache configuration between an 8 Mbyte cache and a 16 Mbyte cache to SRAM20aand SRAM20b.

Still referring toFIG. 3A, microprocessor30further comprises a configuration register34. Configuration register34provides a control signal to multiplexor33via a control bus34ain response to a selection signal from main logic units31via a data bus31a. The selection signal is indicative of a selected cache configuration by main logic units31during an initial boot of microprocessor30. The control signal is indicative of the address bus that corresponds to the selected cache configuration. Consequently, multiplexor33provides the appropriate address signals via address bus33ato SRAM20aand SRAM20bin response to the selection signal. For example, when the selection signal indicates the 16 Mbyte cache has been selected during an initial boot of microprocessor30, pin22aand pin26bconcurrently receive address signal net1, and pin26aand pin22bconcurrently receive address signal net2 as indicated by Table 1.

Referring toFIG. 3B, a microprocessor40in accordance with the present invention for selecting between three (3) of the four (4) cache configurations supported by SRAM20aand SRAM20bis shown. Microprocessor40includes main logic units41for interpreting and executing operating and application programs as would occur to one skilled in the art. Microprocessor40further includes a controller42and a multiplexer43. Address bus42a, address bus42b, and address bus42cprovide electrical communication between controller42and multiplexer43. Address bus42aaddress bus42b, and address bus42ceach have three (3) address lines. Multiplexer43has an address bus43awith a first address line electrically coupled to pin22a(FIG. 2) and pin26b(FIG. 2), a second address line electrically coupled to pin26a(FIG. 2) and pin22b(FIG. 2), and a third address line electrically coupled to pin23a(FIG. 2) and pin25b(FIG. 2). The following Table 2 exemplary illustrates the address bit logic utilized by main logic units41for electrically communicating a selected cache configuration between a 4 Mbyte cache, an 8 Mbyte cache and a 16 Mbyte cache to SRAM20aand SRAM20b.

Still referring toFIG. 3B, microprocessor40further comprises a configuration register44. Configuration register44provides a control signal to multiplexor43via a control bus44ain response to a selection signal from main logic units41via a data bus41a. The selection signal is indicative of a selected cache configuration by main logic units41during an initial boot of microprocessor40. The control signal is indicative of the address bus that corresponds to the selected cache configuration. Consequently, multiplexor43provides the appropriate address signals via address bus43ato SRAM20aand SRAM20bin response to the selection signal. For example, when the selection signal indicates the 8 Mbyte cache has been selected, pin22aand pin26bconcurrently receive address signal net2, pin26aand pin22bconcurrently receive address signal net2, and pin23aand pin25bconcurrently receive address signal net3 as indicated by Table 2.

Referring toFIG. 3C, a microprocessor50in accordance with the present invention for selecting between all four (4) cache configurations supported by SRAM20aand SRAM20bis shown. Microprocessor50includes main logic units51for interpreting and executing operating and application programs as would occur to one skilled in the art. Microprocessor50further includes a controller52and a multiplexer53. Address bus52a, address bus52b, address bus52c, and address bus52dprovide electrical communication between controller52and multiplexer53. Address bus52aaddress bus52b, address bus52c, and address bus52deach have four (4) address lines. Multiplexer53has an address bus53awith a first address line electrically coupled to pin22a(FIG. 2) and pin26b(FIG. 2), a second address line electrically coupled to pin26a(FIG. 2) and pin22b(FIG. 2), a third address line electrically coupled to pin23a(FIG. 2) and pin25b(FIG. 2), and a fourth address line electrically coupled to pin23b(FIG. 2) and pin25a(FIG. 2). The following Table 3 exemplary illustrates the address bit logic utilized by main logic units51for electrically communicating a selected cache configuration between a 2 Mbyte cache, a 4 Mbyte cache, an 8 Mbyte cache and a 16 Mbyte cache to SRAM20aand SRAM20b.

Still referring toFIG. 3C, microprocessor50further comprises a configuration register54. Configuration register54provides a control signal to multiplexor53via a control bus54ain response to a selection signal from main logic units51via a data bus51a. The selection signal is indicative of a selected cache configuration by main logic units51during an initial boot of microprocessor50. The control signal is indicative of the address bus that corresponds to the selected cache configuration. Consequently, multiplexor53provides the appropriate address signals via address bus53ato SRAM20aand SRAM20bin response to the selection signal. For example, when the selection signal indicates the 8 Mbyte cache has been selected, pin22aand pin26bconcurrently receive address signal net2, pin26aand pin22bconcurrently receive address signal net2, pin23aand pin25bconcurrently receive address signal net3, and pin23band pin25aconcurrently receive address signal net4 as indicated by Table 3.

From the previous description of SRAM20aand SRAM20bherein in connection withFIG. 2, one skilled in the art will know how to make and use electrical couplings between additional synchronous address pins of SRAM20aand SRAM20bin accordance with the present invention. From the previous description of microprocessors30,40, and50in connection withFIGS. 3A–3C, respectively, one skilled in the art will know how to make and use microprocessors in accordance with the present invention for selecting a cache configuration between five or more supported cache configurations.

While the embodiments of the present invention disclosed herein are presently considered to be preferred, various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is indicated in the appended claims, and all changes that come within the meaning and range of equivalents are intended to be embraced therein. For examples, the pin configuration and size of SRAM20aand SRAM20bcan vary, and/or SRAM20aand SRAM20bmay include asynchronous address pins. Additionally, SRAM20aand SRAM20bmay be misaligned along the respective sides of processor card10, and/or mounted on the same side of processor card10. Also, other memory devices may be utilized in lieu of SRAM20aand SRAM20b, e.g. dynamic static random access memories.