Method and apparatus for endianness control in a data processing system

A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect the endianness order of the information transferred during the access. In one embodiment, the first endianness control overrides a default endianness corresponding to the access. The default endianness may be provided by a master endianness control corresponding to a master requesting the current access. A data processing system includes a first bus master, first and second peripherals, first endianness control corresponding to the first peripheral and second endianness control corresponding to the second peripheral, and control circuitry which uses the first endianness control to control endianness for an access between the first bus master and the first peripheral. In one embodiment, the data processing system may include multiple masters.

FIELD OF THE INVENTION

The present invention relates to a data processing system, and more particularly, to endianness control in a data processing system.

RELATED ART

Processors may read and write binary values to and from memory. The data may be stored in memory according to various endian formats, such as, for example, big-endian or little-endian formats. As used in the description ofFIGS. 9 and 10, endianness refers to the byte ordering of bytes within a word or halfword. In this case, endianness may also be referred to as byte ordering. One commonly-used data storage format is illustrated inFIG. 9and is referred to as big-endian format, and a second commonly-used format is illustrated inFIG. 10and is referred to as little-endian format.

InFIG. 9, four byte memory locations are illustrated. The four memory locations may be used to store four bytes of information referred to as byte0, byte1, byte2, and byte3. In another form, the four storage locations inFIG. 9may be used to store a halfword0and a halfword1. As illustrated inFIG. 9, each halfword is a 16-bit value that includes two bytes, and each word is a 32-bit value that includes four bytes. Note that alternatively, words and halfwords can be defined differently. For example, a word can be a 16-bit value and a halfword an 8-bit value. Therefore, the storage locations inFIG. 9allow byte, halfword, and word storage of data.

Big-endian and little-endian differ in how halfwords and words are stored. Referring toFIG. 9, halfword0is stored in two byte locations referred to as byte0and byte1. Byte0is a most significant portion of the halfword and byte1is a least significant portion of the halfword. Byte0stores the value12in hexadecimal and byte1stores the value34in hexadecimal. Therefore, halfword0will be read fromFIG. 9as being a hexadecimal value 1234. In a similar manner, halfword1will be read from memory, having a most significant byte of value56in hexadecimal and a least significant byte of value78in hexadecimal so that halfword1stores the hexadecimal value5678.

InFIG. 9, byte0will have an address value less than byte1, byte1will have an address value less than byte2, and byte2will have an address value less than byte3. For example, if byte0was located in memory such that byte0has an address of 50 hexadecimal, byte1will have an address of 51 hexadecimal, byte2will have an address of 52 hexadecimal, and byte3will have an address of 53 hexadecimal. Therefore, for example, byte3is referred to as residing in a higher address space than byte0,1, or2. Therefore, when reading halfwords or words from memory, most significant bytes in the big-endian formats are stored in low address space whereas least significant byte portions are stored in a higher address space than the most significant bit portions.

When a 32-bit word is stored inFIG. 9, the value read will be 12345678 hexadecimal due to the fact that byte0is a most significant byte and byte3is a least significant byte.

FIG. 10illustrates the little-endian format. Halfword0ofFIG. 10will be read from memory as having a value of 5678. This is because, when using little-endian storage format, most significant bytes are stored in a higher address space than least significant bytes. This little-endian format is the reverse of the big-endian format. Therefore, halfword0will be read as a value5678hexadecimal, and halfword1will be read as a value1234hexadecimal. If a 32-bit word value referred to as word0is read from memory inFIG. 10, this word will have a hexadecimal value of 12345678.

In summary, if a 32-bit word is read fromFIG. 9using a big-endian format, that 32-bit value would be hexadecimal 12345678. Also if a 32-bit word is read fromFIG. 10using the little-endian format, the hexadecimal value 12345678 is read. However, as one can see fromFIGS. 9 and 10, even though both reads result in the same value, the individual bytes ofFIGS. 9 and 10are reversed when compared to each other.

This inherent difference in bit or byte ordering between different endian formats results in problems within data processing systems such as multiple master and multiple peripheral data processing systems which seek to operate using different endian formats. Therefore, a need exists for a data processing system that allows for flexible and dynamic control of endianness for data processing systems having one or more masters and one or more peripherals.

DETAILED DESCRIPTION OF THE DRAWINGS

As described above, data may be stored in memory according to various endian formats, such as, for example, big-endian or little-endian formats. As will be used in the description ofFIGS. 1-8, endianness refers to the byte ordering of bytes within a word or halfword. Therefore, in this case, endianness may also be referred to as byte ordering. However, alternatively, endianness may also refer to bit ordering of bits within a byte, word, or halfword. Endianness may also refer to word orderings or halfword orderings, etc. That is, endianness may refer to the ordering of any “n” number of bits (or bytes) within a grouping of bits (or bytes), such as, for example, within a byte, halfword, word, longword, doubleword, etc. Therefore, endianness, in general, refers to this broad concept of the ordering of any “n” number of bits or bytes, and is not limited to byte ordering. Also, note that in one embodiment, a word corresponds to 32 bits and a halfword to 16 bits. However, in alternate embodiments, a word may include a different number of bits, such as, for example, 16 bits or 64 bits.

One embodiment of the present invention provides for a flexible endianness control mechanism within a data processing system through the use of peripheral endianness controls which allows for endianness control on a per-peripheral basis and on a per access basis. For example, in one embodiment, the data processing system may include shared peripherals which must respond to masters running in different endian modes. Also, for software compatibility with previous systems, the peripherals may need to respond with a memory image which is different from the accessing master's current endianness, due to the way the software was originally written. Furthermore, peripherals may need to respond to different endiannesses without receiving indication of the current master's endian mode. In one embodiment, master endianness control fields may be used to provide default endian modes for each master in the system. Furthermore, the peripheral endianness controls may selectively override the endian mode of each master to allow, for example, for backwards compatibility with previous system configurations or software conventions. Note that the peripheral endianness controls and master endianness controls may apply to single master or multiple master data processing systems having dedicated peripherals, shared peripherals, or any combination thereof.

Another embodiment of the present invention provides a flexible peripheral access protection mechanism within a data processing system in order to obtain a more secure operating environment. For example, the data processing system may include a combination of trusted and untrusted bus masters needing to access shared peripherals. One embodiment allows for the dynamic update by a trusted bus master of privileges and trust attributes for each bus master and of access controls for each peripheral. A trusted bus master is therefore able to establish which bus masters have permission to access which peripheral in order to protect the data processing system from corruption due to errant or hostile software running on untrusted bus masters.

Through the use of a bus master identifier, trust attributes, and privilege levels, access to the requested peripheral can either be allowed or denied based on the permissions established by the trusted bus master. For example, in one embodiment, each master within the data processing system includes a corresponding privilege level modifier and corresponding trust attributes for particular bus access types (such as read and write accesses). Also, in one embodiment, each peripheral within the data processing system includes a corresponding trust attribute, write protect indicator, and a privilege protect indicator. Therefore, in one embodiment, a bus access by a bus master to a peripheral is allowed when the bus master has the appropriate privilege level and appropriate level of trust required by the peripheral (and the peripheral is not write protected, if the bus access is a write access). Also, through the use of privilege level modifiers, a bus master can be forced to a particular privilege level for a particular bus access.

FIG. 1illustrates one embodiment of a data processing system10. Data processing system10includes a bus slave26, a bus master14, a bus master15, bus arbitration logic28, a system bus16, a bus interface18, a peripheral bus20, and peripherals22and24. Bus slave26, bus master14, bus master15, bus arbitration logic28, and bus interface18are all bidirectionally coupled to system bus16. Bus interface18, peripheral22, and peripheral24are all bidirectionally coupled to peripheral bus20. Peripheral22includes peripheral circuitry19and peripheral registers21, and peripheral24includes peripheral circuitry23and peripheral registers25. Although only two peripherals22and24are illustrated inFIG. 1, data processing system10may include any number of peripherals coupled to peripheral bus20. (Also note that each of peripherals22and24may be shared peripherals by all or some of the masters in data processing system10, or may be dedicated peripherals accessible by only one master.) Likewise, any number of bus masters and slaves may be coupled to system bus16and are not limited to those shown inFIG. 1. Also, whileFIG. 1illustrates bus arbitration logic28as a separate unit coupled to system bus16, portions of bus arbitration logic28may be located in each of the bus masters (or in a portion of the bus masters) coupled to system bus16. (Bus arbitration logic28may operate as any known bus arbiter in the art today).

In one embodiment, all of data processing system10is included on a single integrated circuit. Alternatively, data processing system10may be included on any number of integrated circuits.

In one embodiment, bus master14and bus master15may be processors, such as microprocessors, digital signal processors, etc., or may be any other type of master device, such as a direct memory access (DMA) unit. One or more of these bus masters may be trusted bus masters which are less susceptible to corruption than untrusted bus masters. For example, a trusted bus master may execute instructions that are completely controlled by the manufacturer of the bus master or the SoC (i.e. the software running on a trusted master can be considered trusted software.) That is, in one embodiment, third party software is unable to execute on a trusted master and no third parties are allowed access to the trusted master. Alternatively, the level of trust (i.e. the level of security) for a trusted bus master may vary from completely trusted to less trusted and depends on the design of data processing system10, but is generally more trusted than untrusted bus masters.

Similarly, any one or more of bus masters14and15may be untrusted bus masters, which are generally more accessible or susceptible to corruption. In one embodiment, untrusted bus masters may be general applications processors that may receive and execute third-party software (e.g. user developed software) or any other untrusted software (where the contents and the function of the software are generally unknown). Since the software is untrusted, it may be errant or hostile software which may attempt to corrupt other portions of data processing system10(such as other trusted bus masters or peripherals22and24), introduce a virus into data processing system10, or access secured information within bus master14or15, peripherals22or24, bus slave26, or elsewhere within data processing system10.

Also, note that a particular bus master may be considered trusted for some types of accesses and untrusted for others. For example, a same bus master may be considered trusted for reads and untrusted for writes. Therefore, each master can have different levels of trust for different types of accesses. Also, each bus master can have different privilege levels. For example, in one embodiment, one bus master may operate with a higher privilege level (such as in supervisor mode) while others may operate with a lower privilege level (such as in user mode). A particular privilege level is used to determine which resources a master is able to access.

Therefore, in one embodiment, as will be described below, each master within data processing system10has a corresponding set of trust attribute fields which determine the level of trust for the corresponding master for a particular type of bus access. Also, each bus master has a corresponding privilege modifier field which allows the privilege level for the corresponding master to be selectively adjusted for a particular bus access. Similarly, each peripheral such as peripherals22and24has a corresponding set of access control fields which determine the level of access supported by the given peripheral. For example, a particular peripheral may give more access to those masters that are identified as trusted or those that operate in a supervisor mode (i.e. have a supervisor privilege level). These privilege and trust attribute fields for the bus masters and the access control fields for the peripherals will be discussed in more detail below in reference toFIGS. 2-5.

Also, note that each bus master within data processing system10may operate according to a particular endian mode, where the endian modes of different bus masters may differ. Therefore, in one embodiment, as will be described below, a set of peripheral endianness control registers is used to determine in which endian mode to perform a current access from a particular bus master, where, in one example, one or more peripherals has a corresponding peripheral endianness control register which provides endianness control information for each master capable of accessing that peripheral. In this manner, for each access, the accessed peripheral can respond to the requesting master using the appropriate endianness. Also, in one embodiment, a set of master endianness control fields provides endianness control information corresponding to each master, where this endianness control information may be selectively overridden by the endianness control information provided by the peripheral endianness control registers. For example, these master endianness control fields may provide default endianness information for each master. These master endianness control fields and peripheral endianness control registers will be discussed in more detail below in reference toFIGS. 2-8.

Referring back toFIG. 1, bus slave26may be any slave device, such as, for example, a memory accessible by bus masters14and15, as well as any type of peripheral which resides on the system bus, including the same types of peripherals as peripheral22and24. Peripherals22and24may be any type of peripheral, such as a universal asynchronous receiver transmitter (UART), a real time clock (RTC), a keyboard controller, etc. Peripheral circuitry19permits communication between peripheral bus20and peripheral registers21. Similarly, peripheral circuitry23permits communication between peripheral bus20and peripheral registers25. In an alternate embodiment, peripheral22may be a memory unit where peripheral registers21would be memory address locations instead.

In operation, bus masters14and15request access of system bus16to request access to other slave devices coupled to system bus16, such as bus slave26, or to request access to peripherals22and24via bus interface18. Bus interface18, as will be described below, determines whether a request or particular type of request to a particular peripheral is allowed. If not allowed, bus interface18may provide a bus error response via system bus16. However, if the request is allowed, bus interface18will provide any necessary bus protocol and endianness control information to complete the requested bus access. As mentioned above, each bus master14and15may have limited access to peripherals22and24as determined by its privilege level and level of trust and the access control fields of the peripheral being accessed. Furthermore, each bus master14and15may operate according to different endian modes, and each accessed peripheral22and24may respond accordingly, based on the settings within the peripheral endianness control registers.

FIG. 2illustrates a portion of bus interface18ofFIG. 1in accordance with one embodiment of the present invention. Bus interface18includes control circuitry44, master privilege registers30, peripheral access control registers54, and peripheral endianness control registers154. Control circuitry44provides and receives bus master identifier36, address42, data40, control38, and privilege indicator37via system bus16. Optionally, control circuitry44receives endian indicator137(also referred to as an endian signal137) via system bus16, as indicated by the dotted line. (In alternate embodiments, endian indicator137, if present, may be provided directly from one or more of masters14and15as, for example, side-band signals rather than via system bus16.) System bus16, in alternate embodiments, may also provide additional information such as a type indicator indicating whether the current access is for data or instructions or a size indicator indicating the size of a current access.

Control circuitry44includes circuitry46for trusted bus master read/write (R/W) access to registers30,54, and154that are bidirectionally coupled to each of master privilege registers30, peripheral access control registers54, and peripheral endianness control registers154. Control circuitry44also includes circuitry48for accessing peripherals22,24. Circuitry48includes bus master attribute determination circuitry50which receives information from master privilege registers30and also includes peripheral protection determination circuitry51which receives information from peripheral access control registers54. Control circuitry48also includes signal bridging circuitry52which receives information from peripheral endianness control registers154and is bidirectionally coupled to peripheral bus20in order to provide and receive appropriate signals to and from peripherals22and24. Bus master attribute determination circuitry50also provides adjusted endian indicator157, adjusted privilege indicator57, R/W indicator58, and trusted indicator59to peripheral protection determination circuitry51and receives access error signal60from peripheral protection determination circuitry51. Note that access error signal60may also be communicated back to bus masters14and15via system bus16. In an alternate embodiment, access error signal60is communicated via system bus16and is not provided to bus master attribute determination circuitry50.

Master privilege registers30includes master privilege register32and master endianness control132, master privilege register34, and master endianness control134. In one embodiment, each of master privilege registers30corresponds to a master on system bus16. Also, in one embodiment, master privilege registers30may include only a single register, or alternatively, may include any number of registers, as will be described further below in reference toFIG. 3. Also, note that master endianness controls132and134may be additional fields located within master privilege registers32and34, respectively, or master endianness controls132and134may be included in one or more separate registers within master privilege registers30or elsewhere within bus interface18.

Peripheral access control registers54include peripheral access control register55and peripheral access control register56. In one embodiment, each of the peripheral access control registers corresponds to a peripheral on peripheral bus20. Also, in one embodiment, peripheral access control registers54may include only a single register, or alternatively, may include any number of registers, as will be described further below in reference toFIG. 3. Peripheral endianness control registers154include peripheral endianness control register155and peripheral endianness control register156. In one embodiment, each of the peripheral endianness control registers corresponds to a peripheral on peripheral bus20. Also, in one embodiment, peripheral endian control registers154may include only a single register, or alternatively, may include any number of registers, as will be described further below in reference toFIG. 7. Also, in one embodiment, note that peripheral access control registers54and peripheral endianness control registers154may be combined into one ore more registers including both access and endianness control information for each peripheral.

Also, note that master privilege registers30, peripheral access control registers54, and peripheral endianness control registers154may be located anywhere within data processing system10and do not have to be located within bus interface18. In some alternate embodiments of the present invention, peripheral access control registers and peripheral endianness control registers may be distributed within each peripheral22and24, or bus slave26, and master privilege registers may be distributed, or may reside in one or more bus slaves26.

In operation, bus interface18provides access to master privilege registers30, peripheral access control registers54, and peripheral endianness control registers154based on bus master identifier36. Bus master identifier36identifies to control circuitry44which bus master is providing the current request. For example, in one embodiment, each bus master in data processing system10may have a corresponding identification (ID) number. For example, bus master14may have a corresponding ID number of 0 and bus master15may have a corresponding ID number of 1. Any bus masters in data processing system10can therefore be assigned unique ID numbers. When a particular bus master requests access to a peripheral, its corresponding ID number can be provided to control circuitry44as bus master identifier36. In this example, if bus master identifier36is 0, bus master14is indicated. In alternate embodiments, any type of identification system may be used to differentiate among different bus masters.

Bus interface18, via circuitry46, ensures that only a trusted bus master is able to obtain R/W access to master privilege registers30, peripheral access control registers54, and peripheral endianness control registers154. (Alternatively, circuitry46may allow untrusted masters to access some or all of these registers. For example, in one embodiment, circuitry46may allow only trusted masters to access registers30and54and may allow trusted or untrusted masters to access registers154.) In the illustrated embodiment, circuitry46compares the incoming bus master identifier36to determine if a trusted bus master is requesting R/W access to registers30, registers54, or registers154. In one embodiment, circuitry46includes a list which identifies which bus masters are allowed to modify registers30,54, and154. For example, in one embodiment, only one of masters14and15may be considered a trusted master and only that trusted master has the ability to modify registers30,54, and154. Alternatively, circuitry46may include other circuitry that ensures that only trusted masters modify registers30,54, and154. Also, circuitry46may make this determination based on other attributes in addition to or in place of bus master identifier36. For example, in an alternate embodiment, circuitry46may use privilege indicator37(which indicates a privilege level of the requesting bus master for the current bus access) to make the determination. In this manner, a trusted bus master is able to set the fields of registers30,54, and154to control access of peripherals22and24. In one embodiment, a trusted bus master may program the values into registers30,54, and154upon power up, upon reset, in response to initiation of a software application, or at any other appropriate time. This allows for dynamic access to registers30,54, and154such that they may be updated as necessary. Alternatively, though, the values within registers30,54, and154may be programmed a single time (such as by using a write once only memory), programmed only a limited amount of times, or may be hardwired. Prior to discussing bus master attribute determination circuitry50within circuitry48for accessing peripherals22,24, the contents of registers30will be described in reference toFIGS. 3 and 6.

FIG. 3illustrates one embodiment of master privilege registers30where, in the illustrated embodiment, master privilege registers30includes a master privilege register32and master endianness control132, both corresponding to bus master14and a master privilege register34and master endianness control134, both corresponding to bus master15. In one embodiment, master endianness control132may be included as an additional field within master privilege register32(similar to fields70-72). Alternatively, master endianness control132may be stored in a separate registers. (Note that master endianness control132and134may also be referred to as master endianness control fields132and134, respectively.) Therefore, in the current embodiment, master privilege registers30include one master privilege register and a master endianness control field for each bus master. However, in alternate embodiments, a single register may be used to store the necessary information for all masters, or, alternatively, any number and combination of registers may be used. Master privilege register32and master endianness control132will be discussed herein as examples; however, note that the descriptions for master privilege register32and master endianness control132also apply to all master privilege registers and master endianness control fields in master privilege registers30such as master privilege register34and master endianness control134. Master privilege register32includes a privilege level modifier for bus master14field70, a trust attribute for writes by bus master14field71, and a trust attribute for reads by bus master14field72.

Privilege level modifier field70allows for the current privilege level of bus master14for a particular access to be selectively modified or adjusted, as indicated by the value stored in field70. The current privilege of bus master14, in one embodiment, is provided by bus master14to control circuitry44by privilege indicator37via system bus16. In one embodiment, privilege indicator37is used to identify whether, during the current bus access, the current bus master (as identified by bus master identifier36) requesting the bus access has a supervisor or user privilege level. That is, in this embodiment, privilege indicator37indicates a privilege level corresponding to one of supervisor or user mode. Therefore, if bus master14is performing a bus access, privilege level modifier field70may be used to indicate to bus master attribute determination circuitry50whether the privilege level of bus master14for the current bus access should be adjusted. For example, if operating in supervisor mode, privilege level modifier field70may be used to force the privilege level of bus master14to user mode. Alternatively, privilege level modifier field70can indicate any type of privilege level, and is not limited only to supervisor or user modes. Furthermore, privilege level modifier field70may include one or more bits used to provide the privilege level of bus master14. For example, in one embodiment, one bit within privilege level modifier field70may be used to indicate whether or not the privilege level of a requesting bus master during a current bus access should be modified, and another one or more bits may be used to indicate what the adjusted privilege level should be. (Note that in some embodiments, the current privilege level may be the same as the privilege level indicated by field70, indicated that no adjustment is necessary.)

Trust attribute for writes by bus master14field71is used to indicate whether bus master14is a trusted master for write accesses by bus master14. Similarly, trust attribute for reads by bus master14field72is used to indicate whether bus master14is a trusted master for read accesses by bus master14. Therefore, each bus master, such as bus master14, may have different trust attributes for read or write access. For example, for performing a read access to a peripheral or bus slave, bus master14may be considered as a trusted master while for performing a write access from a peripheral or bus slave, bus master14may be considered as an untrusted master. Therefore, each of fields71and72may include one or more bits used to indicate the level of trust of bus master14for write and read accesses. In an alternate embodiment, a bus master may have more levels of trust for particular types of bus accesses rather than just being categorized as trusted or untrusted. For example, fields71and72may indicate one level from a selection of N levels of trust (N>2) for bus master14.

Note that more or fewer or different fields than those illustrated may be included in master privilege register32. For example, a single trust attribute field may be used for both writes and reads by bus master14where bus master14is either considered trusted or untrusted for both reads and writes. Alternatively, trust attributes may be provided for other types of bus accesses.

Note that the descriptions provided above for fields70-72also apply for fields74-76of master privilege register34. That is, privilege level modifier for bus master15field74allows for the privilege level of bus master15to be selectively adjusted for a current bus access. Trust attribute for writes by bus master15field75indicates the level of trust of bus master15for a write access, and trust attribute for reads by bus master15field76indicates the level of trust of bus master15for a read access.

Master endianness control132provides endianness control information for bus master14. Therefore, if bus master14requests the current access (as identified, for example, by bus master identifier36), master endianness control132may be used to provide endianness information. For example,FIG. 6provides example settings for master endianness control132and134which determine how the endianness of bus master14or bus master15is determined. In one embodiment, the endianness determined by master endianness control132and134is referred to as the default endianness of the requesting master. Referring toFIG. 6, if master endianness control132is set to “10,” then accesses from bus master14are forced to little-endian mode, regardless of the actual endian mode of bus master14. In this case, adjusted endian indicator157would indicate little-endian mode, regardless of the endian mode the requesting bus master is operating in or regardless of the endian mode indicated by endian indicator137(if present). If master endianness control132is set to “11,” then accesses from bus master14are forced to big-endian mode, regardless of the actual endian mode of bus master14. In this case, adjusted endian indicator157would indicate big-endian mode, regardless of the endian mode the requesting bus master is operating in or regardless of the endian mode indicated by endian indicator137(if present).

Still referring toFIG. 6, if master endianness control132is set to “00,” then accesses from bus master14are not forced to a particular endian mode, regardless of the actual endianness mode. Therefore, if set to “00” then the endian mode indicated by endian indicator137(corresponding to the endian mode of the requesting bus master) is used. In this case, adjusted endian indicator157indicates the same mode as endian indicator137. However, if master endianness control132is set to “01,” then access from bus master14are reversed from the mode indicated by endian indicator137. For example, if endian indicator137indicates that bus master14is operating in big-endian mode, then, if master endianness control132is set to “01,” adjusted endian indicator157will be set to indicate little-endian mode. In alternate embodiments, a setting of “01” may indicate that a different endianness is used, rather than just the reverse endianness. (Therefore, note that in cases where master endianness control132is set to “00” or “01,” endian indicator137or some other indicator of the endian mode of the requesting processor is provided.)

Note that the descriptions provided above with respect toFIG. 6and master endianness control132also apply to master endianness control134. Also, note that in alternate embodiments, more or less may bits may be used to provide the endianness information, or other settings may be used. For example, in an alternate embodiment, alternate sets of values may be used for when the bus access is an instruction access or a data access. In this alternate embodiment, based on whether a type indicator indicates data information or instruction information is being accessed during the current access, different sets of values for master endianness control may be applied. Also, in another alternate embodiment, different sets of values may be used based upon the size of the data or information access. For example, one set of values may be used if the current access corresponds to a 16-bit size and a different set of values may be used if the current access corresponds to a 32-bit size. Therefore, each of master endianness control132and134may include multiple fields rather than the single two-bit field illustrated inFIG. 6which may be used to control endianness based on requesting master, access type, access size, or any combination thereof.

Returning toFIG. 2, circuitry48for accessing peripherals22,24includes bus master attribute determination circuitry50which receives address42, control38, privilege indicator37, bus master identifier36, and optionally, endian indicator137, and provides adjusted endian indicator157, adjusted privilege indicator57, R/W indicator58, and trusted indicator59to peripheral protection determination circuitry51. Therefore circuitry50receives all the information necessary that identifies the type of bus access (read or write), the peripheral requested, the identification of which bus master is making the request, the privilege level of the bus master making the request, and, in some embodiments, the endian mode of the bus master making the request. Using information stored in master privilege registers30, as was described above, circuitry50determines adjusted endian indicator157, adjusted privilege indicator57, R/W indicator58, and trusted indicator59. For example, a bus access may be initiated which requires access to a peripheral by a bus master (this bus access can be either a read or write bus access). During at least a portion of the bus access, bus master identifier36is provided. Bus master identifier36is used to select master privilege information and master endianness information (corresponding to the requesting bus master) from master privilege registers30for the bus access. The values for adjusted endianness indicator157, adjusted privilege indicator57, R/W indicator58, and trusted indicator59can then be determined.

For example, in one embodiment where bus master14is performing the current bus access, adjusted privilege indicator57is determined based on the current privilege level as indicated by privilege indicator37and privilege level modifier field70. If privilege level modifier field70indicates that a particular privilege level should be forced upon bus master14, then the value of adjusted privilege indicator57is set to indicate this forced privilege level. If privilege level modifier field70indicates that no privilege should be forced upon bus master14, then the value of adjusted privilege indicator57can be set to indicate the same privilege level as privilege indicator37. R/W indicator58can be determined from control38which indicates whether the current bus access is a read or a write access. Trusted indicator59is determined based on whether the current bus access is a read or a write access (as can be determined from control38) and on trust attribute fields71and72. For example, if the current bus access is a write access by bus master14, then trusted indicator59is set to indicate the level of trust indicated by trust attribute field71. Similarly, if the current bus access is a read access by bus master14, then trusted indicator is set to indicate the level of trust indicated by trust attribute field72. Adjusted endianness indicator157is determined based on endian indicator137(if present) and master endianness control132. For example, if master endianness control132indicates that a particular endian mode is to be forced for bus master14, then adjusted endianness indicator157is set accordingly. If master endianness control132indicates that the endian mode indicated by endian indicator137is to be reversed, then adjusted endianness indicator157is set accordingly.

Adjusted privilege indicator57, R/W indicator58, and trusted indicator59, in combination with peripheral access control registers54, are then used by peripheral protection determination circuitry51to determine whether an access to a peripheral is allowed or, in some cases, whether an access error is generated and communicated via access error signal60back to bus master attribute determination circuitry50and/or the bus master whose access request caused the error. If access is allowed, adjusted endian indicator157and peripheral endianness control registers154are used by signal bridging circuitry52to perform the allowed access to the peripheral using the appropriate endianness. Prior to discussing peripheral protection determination circuitry51and signal bridging circuitry52within circuitry48for accessing peripherals22,24, the contents of registers54and154will be described in reference toFIGS. 4,7and8.

FIG. 4illustrates one embodiment of peripheral access control registers54where, in the illustrated embodiment, peripheral access control registers54includes peripheral access control register55corresponding to peripheral22and peripheral access control register56corresponding to peripheral24. Therefore, in the illustrated embodiment, peripheral access control registers54include one peripheral access control register for each peripheral. However, in alternate embodiments, a single register may be used to store the necessary information for all peripherals, or, alternatively, any number and combination of registers may be used. Peripheral access control register55will be discussed herein as an example; however, note that the descriptions for peripheral access control register55also apply to all peripheral access control registers in peripheral access control registers54such as peripheral access control register56. Peripheral access control register55includes a peripheral trust attribute for peripheral22field80, a write protect for peripheral22field81, and a privilege protect for peripheral22field82.

Peripheral trust attribute for peripheral22field80indicates whether peripheral22allows accesses (either reads or writes) from an untrusted master. For example, if the bus master performing the current bus access is untrusted, as indicated by the trust attribute fields corresponding to the current bus master (e.g. fields71and72), then the bus access will only be allowed if field80indicates that accesses from an untrusted master are allowed. Write protect for peripheral22field81indicates whether peripheral22allows write accesses to itself by a master. For example, if the current bus access being performed by the current bus master (regardless of the level of trust of the bus master) is a write access to peripheral22, then the write access cannot be performed if field81indicates that peripheral22is write protected. Privilege protect for peripheral22field82indicates whether peripheral22requires a certain privilege level for the current bus access. Therefore, privilege protect field82may include any number of bits that may indicate a minimum privilege level required for access to peripheral22. In one embodiment, a single bit may be used to indicate whether or not a supervisor privilege is required. Alternatively, more bits may be used to indicate that a minimum one of N-levels of privilege (N>2) is required.

Note that more or fewer or different fields than those illustrated may be included in peripheral access control register55. For example, separate peripheral trust attribute fields such as peripheral trust attribute field80may be used to indicate whether read accesses are allowed from an untrusted master and whether write accesses are allowed from an untrusted master. Also, additional bits or fields may be used to indicate a minimum level of trust of N possible levels of trust (N>2) needed for peripheral22to allow a read or a write access.

Note that the descriptions provided above for fields80-82also apply for fields84-86of peripheral access control register56. That is, peripheral trust attribute for peripheral24field84indicates whether peripheral24allows accesses (either reads or writes) from an untrusted master. Write protect for peripheral24field85indicates whether peripheral24allows write accesses to itself by a master. Privilege protect for peripheral24field86indicates whether peripheral24requires a certain privilege level for the current bus access.

FIG. 7illustrates one embodiment of peripheral endianness control registers154where, in the illustrated embodiment, peripheral endianness control registers154includes peripheral endianness control register155corresponding to peripheral22and peripheral endianness control register156corresponding to peripheral24. Therefore, in the illustrated embodiment ofFIG. 2, peripheral endianness control registers154include one peripheral endianness control register for each peripheral. However, in alternate embodiments, a single register may be used to store the necessary endianness control information for all peripherals, or, alternatively, any number and combination of registers may be used. In alternate embodiments, only a subset of peripherals may be provided with peripheral endianness control registers. Peripheral endianness control register155will be discussed herein as an example; however, note that the descriptions for peripheral endianness control register155also apply to all peripheral endianness control registers in peripheral endianness control registers154such as peripheral endianness control register156.

Peripheral endianness control register155includes a bus master14peripheral endianness control field300, and a bus master15peripheral endianness control field302. Therefore, in the illustrated embodiment, peripheral endianness control register155includes a peripheral endianness control field for each bus master which accesses the corresponding peripheral (where, in this embodiment, peripheral endianness control register155corresponds to peripheral22). In one embodiment, peripheral endianness control registers154selectively override the endianness information provided by master endianness control132and134, depending on the values of fields300and302(as will be described below in reference toFIG. 8). That is, in one embodiment, the endianness information provided by the peripheral endianness control register corresponding to the current peripheral being accessed can override the endianness information provided by adjusted endian indicator157(which may have been provided directly by the accessing master, via, for example, endian indicator137or which may have been determined by bus master attribute determination circuitry50using the master endianness control of registers30corresponding to the requesting master). In this embodiment, master endianness control132and134may be considered the default endianness information which can be selectively overridden.

Referring back toFIG. 7, each field300and302within register155provides endianness information for the corresponding master. For example,FIG. 8illustrates example settings which may be used within each of fields300and302to provide the endianness information.FIG. 8will be discussed using bus master14peripheral endianness control field300as an example; however, note that the descriptions also correspond to the other fields within registers155and156, such as field302. Therefore, the example settings ofFIG. 8may be used to determine the endianness of bus master14. Referring toFIG. 8, if field300is set to “00”, then access from bus master14are not forced, regardless of the actual processor mode. That is, in this case, bus master14peripheral endianness control field300does not override adjusted endian indicator157. However, if field300is set to some value other than “00”, then the endianness information provided by field300overrides the endianness information provided by master endianness control132(which is used, as described above in reference toFIG. 6, to determine adjusted endian indicator157).

For example, if field300is set to “10,” then accesses from bus master14are forced to little-endian mode, regardless of the actual endian mode of bus master14. In this case, little-endian mode would be used by signal bridging circuitry52, regardless of the endian mode indicated by adjusted endian indicator157, thus possibly overriding the endianness control provided by master endianness control132. If field300is set to “11,” then accesses from bus master14are forced to big-endian mode, regardless of the actual endian mode of bus master14. In this case, big-endian mode would be used by signal bridging circuitry52, regardless of the endian mode indicated by adjusted endian indicator157. If field300is set to “01,” then access from bus master14are reversed from the mode indicated by adjusted endian indicator157. For example, if adjusted endian indicator157indicates that bus master14is operating in big-endian mode, then, if field300is set to “01,” little-endian mode is used by bridging circuitry52. In alternate embodiments, a setting of “01” may indicate that a different endianness is used, rather than just the reverse endianness.

Note that the descriptions provided above with respect toFIG. 8and field300also apply to field302. Also, note that in alternate embodiments, more or less may bits may be used to provide the endianness information, or other settings may be used. For example, in an alternate embodiment, a different set of values may be used for when the bus access is an instruction access or a data access. In this alternate embodiment, based on whether a type indicator indicates data information or instruction information is being accessed during the current access, different sets of values for master endianness control may be applied. Also, in another alternate embodiment, different sets of values may be used based upon the size of the data or information access. For example, one set of values may be used if the current access corresponds to a 16-bit size and a different set of values may be used if the current access corresponds to a 32-bit size. Therefore, each of fields300and302may include multiple fields rather than the single two-bit field illustrated inFIG. 8which may be used to control endianness based on the peripheral being accessed, the requesting master, access type, access size, or any combination thereof.

Note that with the use of master endianness controls132and134, an endian indicator from the requesting master, such as endian indicator137, is not needed. That is, adjusted endian indicator157may be set in a variety of different ways with or without the use of endian indicator137. Also note that in an alternate embodiment, master endianness controls132and134may not be present. In this alternate embodiment, the endianness for a particular access is controlled by peripheral endianness control registers154. Alternatively, adjusted endian indicator157may also not be present. That is, each of master endianness controls132and134, endian indicator137, and adjusted endian indicator157may or may not be present in data processing system10. Therefore, peripheral endianness control registers may not have any knowledge of the current master's endianness. In these embodiments, the endianness of an access to a peripheral may be determined based on the endianness information within the peripheral endianness control registers. In an alternate embodiment, only a subset of peripherals may be provided with peripheral endianness control registers. In this case, peripherals which are not provided with peripheral endianness control registers154may instead rely on master endianness controls132and134, and signal bridging circuitry52uses the value of adjusted endian indicator157directly for accesses to those peripherals.

Returning back toFIG. 2, circuitry48for accessing peripherals22,24includes peripheral protection determination circuitry51which receives adjusted privilege indicator57, RW indicator58, and trusted indicator59and provides access error signal60to bus master attribute determination circuitry50. (Alternatively or additionally, access error signal60may be provided back to the bus master whose request caused the error via system bus16.) Therefore circuitry51uses indicators57-59and information stored in peripheral access control registers54, as was described above, to determine whether the bus access to the requested peripheral is allowed. For example, if bus master14initiates a bus access for performing a write to peripheral22, circuitry51determines if the bus access is allowed. For example, circuitry51uses adjusted privilege indicator57and privilege protect field82to determine whether peripheral22requires a particular privilege level for accesses (as indicated by field82) and whether bus master14has the required privilege level (as indicated by adjusted privilege indicator57). Circuitry51also uses R/W indicator58and write protect field81to determine whether the current bus access is a write access, and if so, whether write accesses are allowed to peripheral22. Circuitry51also uses trusted indicator59and peripheral trust attribute field80to determine whether bus master14has the appropriate level of trust (indicated by trusted indicator59) as required by peripheral22(indicated by field80). Therefore, circuitry51, using all the above information, can determine whether the bus access requested by bus master14to peripheral22is allowed. That is, bus master14needs to have the appropriate privilege level and the appropriate level of trust, and, if the bus access is a write, peripheral22must not be write protected, for the bus access to be allowed.

If access is allowed (meaning the requesting bus master does have the appropriate access permission for the particular peripheral being requested), then operation continues (i.e. the bus access continues) and the necessary bus protocol is provided to complete the operation. For example, signal bridging circuitry52provides any appropriate data, address, and control signals to the accessed peripheral derived from control38, data40, and address42. Similarly, signal bridging circuitry52returns any necessary control, data, and address information to system bus16via control38, data40, and address42. Also, status information may be returned by way of control38. Signal bridging circuitry52, based on adjusted endian indicator157and peripheral endianness control registers154, determines the appropriate endian mode to use in completing the access operation. Therefore, as described above, the peripheral endianness control register corresponding to the peripheral being accessed and the field within that register corresponding to the requesting master is used by signal bridging circuitry52to determine the endian mode, i.e. to determine the endianness of the information to be transferred during the current access. For example, if the field indicates a “00”, then the endian mode indicated by adjusted endian indicator157is used by signal bridging circuitry52to complete the access. If the field indicates a value other than “00”, then signal bridging circuitry52operates according to the endian mode indicated by that field. In this manner, the endianness control information within peripheral endianness control registers154may be used to affect the endianness order of information transferred during the current access.

However, if access is not allowed by peripheral protection determination circuitry51(meaning the requesting bus master does not have the appropriate access permission for the particular peripheral being requested), the bus access is terminated prior to accessing the peripheral. Also, access error signal60may be used to indicate that the requesting bus master is denied access to the peripheral. Also, a bus error may be provided via system bus16to the requesting bus master. The bus error can be provided by bus master permission determination circuitry50as one of control signals38. In response, the requesting bus master may perform appropriate exception handling to recover from the bus error. Alternatively, if access is not allowed, a reset of all or a portion of data processing system10may be performed.

As discussed above, a trusted bus master may dynamically change permissions in registers30and54as necessary. In one embodiment, the trusted bus master may change permissions in response to the initiation of a software application. For example, an untrusted bus master may alert a trusted bus master that it is preparing to begin a software application. In response, the trusted bus master may update registers30and54in order to provide the untrusted bus master access to the necessary peripheral in order to complete its application. Upon completing the application, the trusted bus master may revoke the permissions previously granted such that permissions are only granted on an application by application basis.

Also, as discussed above, peripheral endianness control registers and master endian control fields may be used to allow for dynamic and flexible control of the endian mode of a particular access on an access by access basis. The use of peripheral endianness control registers (associated with each peripheral) may be used to override the default endian mode indicated by the requesting master, as needed. This may provide for the ability to handle software using a different endian mode than the one in which the master normally operates, and may provide for the ability to emulate a previous bridging configuration from a different system, thus allowing for software written for the previous configuration to be reused.

In an alternate embodiment, peripheral22or24may be a memory unit where peripheral registers21or25may be memory locations. Registers30and54, in this embodiment, can define access permissions corresponding to each bus master to specific memory locations or portions of the memory unit. Similarly, registers154, in this embodiment, can provide endianness information corresponding to each bus master to specific memory locations or portions of the memory unit.

Also note that in alternate embodiments, the information stored in registers30can be located within each corresponding master and the information stored in registers54and154can be located within each peripheral rather than in bus interface18. Furthermore, the bus master permission determination circuitry may also be located in or next to the masters and the peripheral protection determination circuitry and signal bridging circuitry can be located in or next to the peripherals such that permission and the endian mode (if so indicated by the corresponding field within the peripheral endianness control registers) is determined by the peripheral. Therefore, alternate embodiments may store the information of registers30,54, and154that is accessible by a trusted bus master or other bus master in any place within data processing system10. Also, data processing system10may include any number of trusted bus masters or other bus masters that are capable of updating the permission and endian information, and is not limited to a single secure bus master.

FIG. 5illustrates data processing system100in accordance with an alternate embodiment of the present invention. Data processing system100includes bus master101, bus master102, bus master attribute determination circuitry, master privilege register, and master endianness control104, bus master attribute determination circuitry, master privilege register, and master endianness control110, peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control register106, peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control register112, and peripherals108and114.

Bus master101provides privilege indicator116and, optionally, endian indicator216to bus master attribute determination circuitry, master privilege register, and master endianness control104, which provides adjusted privilege indicator118via a system bus103to peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control registers106and112and to peripherals108and114, provides trusted indicator120via system bus103to peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control registers106and112, and provides adjusted endian indicator220via system bus103to peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control registers106and112. Bus master101also provides other information122via system bus103to peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control registers106and112and to peripherals108and114.

Bus master102provides privilege indicator130and, optionally, endian indicator230to bus master attribute determination circuitry, master privilege register, and master endianness control110, which provides adjusted privilege indicator126via a system bus103to peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control registers106and112and to peripherals108and114, provides trusted indicator128via system bus103to peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control registers106and112, and provides adjusted endian indicator226via system bus103to peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control registers106and112. Bus master102also provides other information124via system bus103to peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control registers106and112and to peripherals108and114.

In operation, data processing system100operates similarly to data processing system10. For example, masters101and102may be similar to masters14and15, and peripherals108and114may be similar to peripherals22and24. Also, data processing system100may include any number of masters and any number of peripherals. However, in data processing system100, portions of bus interface18are distributed to different locations. Also, in data processing system100, trusted indicators120and128are provided via system bus103to peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control registers106and112. Also, privilege indicators116and130are selectively modified by bus master attribute determination circuitry, master privilege register, and master endianness control104and110, respectively, and provided as adjusted privilege indicators118and126via system bus103to peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control registers106and112and peripherals108and114. Adjusted endian indicators220and226are generated by bus master attribute determination circuitry, master privilege register, and master endianness control104and110based on endian indicators216and230(if present) and master endianness control Note that each of bus master attribute determination circuitry, master privilege registers, and master endianness control104and110operate similarly to bus master attribute determination circuitry50and master privilege registers30described above in reference toFIGS. 2-4. For example, the information stored in the master privilege registers (including the master endianness control fields) and peripheral access control registers are used in the same manner to determine whether a bus access is allowed and to determine an endian mode. Other information122and124may include information like control38, data40, address42, and bus master identifier36. Therefore, the same signals may be used as described inFIGS. 1-4above; however, the circuitry which generates the signals or some of the signals themselves may be located in different places or structured differently.

Note that in the illustrated embodiment ofFIG. 5, each bus master101and102has a corresponding bus master attribute determination circuitry, master privilege register, and master endianness control. Therefore, the determination circuitry, master privilege register, and master endianness control are distributed with each master. For example, each determination circuitry, master privilege register, and master endianness control can include the privilege level and trust attribute fields (such as fields70-72and74-76) and master endianness control field (such as fields132and134) corresponding to its corresponding bus master. The circuitry and the information stored in the master privilege register (including the master endianness control fields) can be located within each master or in communication between the master and the system bus. Also, the peripheral protection determination circuitry51, the peripheral access registers54, and the peripheral endianness control registers154may be distributed with each peripheral. For example, as illustrated inFIG. 5, each peripheral108and114has a corresponding peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control register where each peripheral protection determination circuitry, peripheral access control register, and peripheral endianness control register can include access control fields (such as fields80-82and84-86) and peripheral endianness control fields (such as fields300and302) corresponding to its corresponding peripheral. Also note that peripherals108and116may be any type of peripheral, memory device, or bus slave, as described earlier with reference to data processing system10, thus are not limited in scope to a particular function. Also, note that portions of signal bridging circuitry52which utilize the selected endianness mode may also be distributed with each peripheral. Therefore, the distributed signal bridging circuitry can perform the requested access using the appropriate endian mode based on the adjusted endian indicator and the peripheral endianness control register of the corresponding peripheral. Alternatively, portions of signal bridging circuitry52may be distributed with each peripheral and other portions with each bus master. Note that endian indicators216and230, adjusted endian indicators220and226, master endianness control, and peripheral endianness control register operate as was described above in reference toFIGS. 1-8.

Note that althoughFIGS. 1 and 2illustrate the use of bidirectional conductors, it should be understood that a combination of unidirectional conductors may be used instead. Alternatively, a combination of bidirectional and unidirectional conductors may used. Signals may also be transferred serially via a single conductor or in parallel via a plurality of conductors. Alternatively, signals may be time multiplexed on a single or a plurality of conductors. Also, note that signals illustrated as bidirectional conductors may be replaced with unidirectional conductors, and unidirectional conductors may be replaced with bidirectional conductors.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, it should be understood that data processing system10and100could be any type of data processing system which can be located on a single chip or integrated circuit (IC) or a combination of chips or ICs. Data processing system10and100can also apply to a variety of masters and slaves located on a network (coupled via a network system bus) having shared peripherals. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.