Methods of forming isolation structures and fins on a FinFET semiconductor device

One method includes forming a plurality of trenches in a semiconducting substrate to define a plurality of fins, forming a layer of overfill material that overfills the trenches, wherein an upper surface of the overfill material is positioned above an upper surface of the fins, forming a masking layer above the layer of overfill material, wherein the masking layer has an opening that is positioned above a subset of the plurality of fins that is desired to be removed and wherein the subset of fins is comprised of at least one but less than all of the fins, performing an etching process through the masking layer to remove at least a portion of the layer of overfill material and expose the upper surface of the subset of fins, and performing a second etching process on the exposed surface of the subset of fins to remove the subset of fins.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming isolation structures and fins on a FinFET semiconductor device.

2. Description of the Related Art

The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.

To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.

In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the depletion width under the channel and thereby reduce so-called short channel effects. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.

Both FET and FinFET semiconductor devices have an isolation structure, e.g., a shallow trench isolation structure, that is formed in the semiconducting substrate around the device so as to electrically isolate the semiconductor device.FIGS. 1A-1Ddepict various illustrative problems that may be encountered in forming isolation structures on FinFET semiconductor devices. In general, as shown inFIG. 1A, formation of the fins16for a FinFET device10involves etching a plurality of trenches14in a semiconducting substrate12that essentially define the fins16. The etching process is generally performed through a patterned hard mask layer18that may be comprised of a layer of silicon nitride18A and a layer of silicon dioxide18B.

As FinFET devices10have been scaled to meet ever increasing performance and size requirements, the width16W of the fins16has become very small, e.g., 6-12 nm, and the fin pitch16P has also been significantly decreased, e.g., the fin pitch16P may be on the order of about 30-60 nm. Traditionally, isolation structures were always the first structure that was formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the semiconductor device. In the case of a FinFET device, this involved masking the previously formed isolation structure and etching the trenches in the substrate that defined the fins.

However, as the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form a so-called “sea-of-fins” across the substrate, and thereafter remove some of the fins where larger isolation structures will be formed.FIG. 1Adepicts an illustrative FinFET device10that is at the point of fabrication where the “sea-of-fins” has been initially formed in the substrate12. Using this “sea-of-fins” type manufacturing approach, better accuracy and repeatability may be achieved in forming the fins16to very small dimensions due to the more uniform environment in which the etching process that forms the trenches14is performed. In the example depicted inFIGS. 1A-1B, the fins16all have a single uniform spacing. However, in a real-world device, the fins16may be formed so as to have various regions with different spacing or fin pitches16P.

After the “sea-of-fins” has been formed, some of the fins16must be removed to create room for or define the spaces where isolation regions will ultimately be formed.FIG. 1Bdepicts the device10after several process operations have been formed. Initially, an optical planarization layer (OPL)23is formed so as to overfill the trenches14. Thereafter, an anti-reflective coating layer (ARC)24is formed above the OPL layer23and a patterned mask layer26, e.g., a patterned photoresist mask, is formed above the ARC layer24. The mask layer26has a plurality of openings26A-26C positioned above various fins16to be removed. In the depicted example, only a single fin will be removed to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin16may be removed. The ARC layer24may be comprised of a variety of materials, such as, for example, silicon nitride, silicon oxynitride, silicon or carbon containing organic polymers, etc.

In some cases, with very tight fin pitches, the lithography and etching processes that are performed to define the trenches14in the substrate12may introduce variables that can lead to damaged fins16. For example, inFIG. 1B, the openings26B-26C have a dimension28that is precisely as intended by the design process, whereas the opening26A has a dimension30that is greater than that of dimension28. The variations in the dimensions28,30may be due to acceptable process variations in the lithography operations that are performed to make the patterned mask layer26. Overlay errors in attempts to properly locate the openings26A-26C may also lead to problems that may cause fin damage when the trenches14are formed.

The trench etching process that is performed to form the trenches14should be non-selective in nature, i.e., the etchants used may consume the litho film material (such as the OPL layer23) and the fins16. The trench etching process may also introduce undesirable process variations in the size of the openings that are formed through the ARC layer24and the OPL layer23to remove the fins16under the openings26A-26C. InFIG. 1B, the dashed line32depicts the idealized pattern of the opening that will be formed in removing the selected fins16. The dashed line34depicts the situation where, due to variations in the etching process, the openings are wider than desired. In the case where the openings that will be formed to remove a selected number of fins16is too large, the fins16that will become part of the final FinFET device10may become damaged. For example, in the dashed line region36, an undesirably wide opening in the OPL layer23and the ARC layer24, as reflected by the dashed line34, may actually consume some of the fin16.

FIGS. 1C-1Ddepict an illustrative example wherein a FinFET device10will be formed above an SOI (silicon-on-insulator) structure40. In general, the SOI structure40is comprised of a bulk semiconducting substrate40A, a buried insulation layer40B (“BOX” layer) and an active layer40C comprised of a semiconducting material. In general, the fins16will be formed in the active region40C above the buried insulation layer40B.FIG. 1Cdepicts the device10at the point where the “sea-of-fins”16have been formed, and the OPL layer23, the ARC layer24and the patterned mask layer26have been formed above the fins16. Also depicted inFIG. 1Care dashed lines32that depict the idealized location of the openings that will be formed in removing the selected fins16. One problem encountered when removing some of the fins16positioned above the buried insulation layer40B, is that the non-selective, fin-removal etching process that is performed to remove the ARC layer24, the OPL layer23and the fin16may consume some of the buried insulation layer40B in the regions enclosed by dashed lines35.FIG. 1Ddepicts the device10after the non-selective, fin-removal process has been performed to define the openings36and thereby remove the selected fins16. Eventually, isolation regions (not shown) will be formed in the openings36. As can be seen inFIG. 1D, the non-selective, fin-removal etching process undesirably consumed some of the buried insulation layer40B. This gouging of the buried insulation layer40B can lead to undesirable gate-to-gate shorts when the gates are filled with a metal material.

In the examples shown inFIGS. 1A-1D, the methods involved formation of the OPL layer23and the ARC layer24. However, there are other materials that may be more desirable to use during the fin removal process due to differences in etch selectivity. For example, the OPL layer23may be replaced with a layer of amorphous or spin-on carbon, which typically does not require the use of an ARC layer. However, when an amorphous carbon or spin-on glass material is used, a protection layer of, for example, silicon oxynitride is typically formed above the amorphous carbon or spin-on carbon material to provide a means to re-work the wafer in situations where there was an error in forming the patterned mask layer26. In another material combination, the OPL layer23and the ARC layer24may be replaced with a DUO material that has anti-reflective coating type properties due to the manner in which it manufactured. Yet another material combination that has been employed involves replacing the OPL layer23with a spin-on-glass (SOG) material. The ARC layer24would also be employed with the SOG material.

The present disclosure is directed to various methods of forming isolation structures and fins on a FinFET semiconductor device that may solve or reduce one or more of the problems identified above.

SUMMARY OF THE INVENTION

Generally, the present disclosure is directed to various methods of forming isolation structures and fins on a FinFET semiconductor device. One illustrative method disclosed herein includes forming a plurality of trenches in a semiconducting substrate to thereby define a plurality of fins, forming a layer of overfill material that overfills the trenches, wherein an upper surface of the overfill material is positioned above an upper surface of the fins, forming a masking layer above the layer of overfill material, wherein the masking layer has an opening that is positioned above a subset of the plurality of fins that is desired to be removed, wherein the subset of fins is comprised of at least one but less than all of the plurality of fins, performing at least one first etching process through the masking layer to remove at least a portion of the layer of overfill material and thereby expose the upper surface of the subset of fins, and performing at least one second etching process on the exposed surface of the subset of fins to remove the subset of fins.

Another illustrative method includes forming a plurality of trenches in a semiconducting substrate to thereby define a plurality of fins, forming a layer of overfill material comprised of a DUO™ 248 or DUO™ 193 material that overfills the trenches, wherein an upper surface of the overfill material is positioned above the upper surface of the fins, forming a masking layer on the layer of overfill material, wherein the masking layer has an opening that is positioned above a subset of the plurality of fins that is desired to be removed, wherein the subset of fins is comprised of at least one but less than all of the plurality of fins, performing at least one first etching process through the masking layer to remove at least a portion of the layer of overfill material and thereby expose the upper surface of the subset of fins, and performing at least one second etching process on the exposed surface of the subset of fins to remove the subset of fins.

DETAILED DESCRIPTION

The present disclosure is directed to various methods of forming a FinFET semiconductor device. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods disclosed herein may be employed in manufacturing a variety of different devices, including, but not limited to, logic devices, memory devices, etc. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.

FIGS. 2A-2Fdepict one illustrative embodiment of a method disclosed herein of forming isolation structures and fins on a FinFET semiconductor device100that is formed on a bulk semiconducting substrate112.FIG. 2Ais a simplified view of an illustrative FinFET semiconductor device100at an early stage of manufacturing. As will be recognized by those skilled in the art after a complete reading of the present application, the illustrative FinFET device100described herein may be either an N-type FinFET device or a P-type FinFET device. In this illustrative embodiment, the substrate112has a bulk semiconducting material configuration. The substrate112may be made of silicon or it may be made of materials other than silicon. Thus, the terms “substrate” or “semiconducting substrate” should be understood to cover all forms of all semiconductor materials.

FIG. 2Adepicts the device100after one or more trench-formation etching processes have been performed through a patterned hard mask layer118to define a plurality of trenches114in the substrate112. The trenches114define a plurality of fins116, i.e., a “sea-of-fins.” The patterned mask layer118is intended to be representative in nature as it may be comprised of a variety of materials, such as, for example, a photoresist material, silicon nitride, silicon oxynitride, etc. Moreover, the patterned mask layer118may be comprised of multiple layers of material, such as, for example, a silicon nitride layer118A and a layer of silicon dioxide118B. The patterned mask layer118may be formed by depositing the layer(s) of material that comprise the mask layer118and thereafter directly patterning the mask layer118using known photolithography and etching techniques. Alternatively, the patterned mask layer118may be formed by using known sidewall image transfer techniques. Thus, the particular form and composition of the patterned mask layer118and the manner in which it is made should not be considered a limitation of the present invention. In the case where the patterned mask layer118is comprised of one or more hard mask layers, such layers may be formed by performing a variety of known processing techniques, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an epitaxial deposition process (EPI), or plasma enhanced versions of such processes, and the thickness of such a layer(s) may vary depending upon the particular application.

As indicated above, one or more trench-formation etching processes, such as a plurality of dry or wet etching processes, are performed through the patterned mask layer118to form the trenches114. These etching processes result in the definition of a plurality of overall fin structures116. The overall size, shape and configuration of the trenches114and the fin structures116may vary depending on the particular application. The depth114D of the trenches114may vary depending upon the particular application. In one illustrative embodiment, based on current-day technology, the depth114D of the trenches114may range from approximately 100-300 nm. In some embodiments, the fins116may have a width116W within the range of about 6-12 nm. In the illustrative example depicted in the attached figures, the trenches114and the fins116are all of a uniform size and shape. However, such uniformity in the size and shape of the trenches114and the fins116is not required to practice at least some aspects of the inventions disclosed herein. In the example depicted herein, the trenches114are depicted as having been formed by performing a plurality of anisotropic etching processes. In some cases, the trenches114may have a reentrant profile near the bottom of the trenches114. To the extent the trenches114are formed by performing a wet etching process, the trenches114may tend to have a more rounded configuration or non-linear configuration as compared to the generally linear configurations of the trenches114that are formed by performing an anisotropic etching process. Thus, the size and configuration of the trenches114, and the manner in which they are made, should not be considered a limitation of the present invention.

FIG. 2Bdepicts the device100after several process operations have been per formed. Initially, in this illustrative embodiment, an overfill material layer122is formed so as to overfill the trenches114. As will be recognized by those skilled in the art after a complete reading of the present application, the inventions disclosed herein may be employed where a variety of materials may be used to overfill the trenches114at this stage of the process flow. In one illustrative embodiment, the overfill material layer122may be comprised of one of the DUO brand materials sold by Honeywell under the names DUO™ 248, DUO™ 193 or a spin-on-glass (SOG) material.

In some cases, an additional OPL and ARC layer or a protection layer may be formed above such an overfill material, however, in the case where the illustrative overfill material layer122is made of DUO, a separate ARC layer may not be required. Thus, the present invention should not be considered to be limited to any particular type of material used to overfill the trenches114unless such a material is expressly recited in the claims. In the case where the overfill material layer122is made of a DUO material, it may be formed by performing a spin-coating process and it may have a thickness of about 50-200 nm.

With continuing reference toFIG. 2B, a patterned mask layer124, e.g., a patterned photoresist mask, is formed on the overfill material layer122. The mask layer124has a plurality of openings124A-124C positioned above a subset of the fins116that are to be removed. In the depicted example, the subset of the fins to be removed contains only a single fin that will be removed to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin116may be in the subset of the fins116to be removed.

Next, as shown inFIG. 2C, one or more dry fin-exposure etching processes are performed through the masking layer124to define a plurality of cavities126that expose the upper surface116S of the underlying fins116in the subset of fins to be removed. In the depicted example, the fin-exposure etching processes remove underlying portions of the overfill material layer122and the hard mask layer118.

FIG. 2Ddepicts the device100after several process operations have been per formed. First, the patterned mask layer126was removed. Thereafter, a dry or wet etching process132was performed to remove the exposed fins116(that constitute the subset of the fins to be removed) selectively relative to the overfill material layer122and thereby define openings134in the overfill material layer122. Depending upon the nature and duration of the etching process132, portions of the underlying substrate112may be removed. InFIG. 2D, reference number134A depicts the idealized situation where there is no etching of the underlying substrate112, wherein reference numbers134B,134C refer to illustrative over-etch profiles that may be found in the substrate112when the etching process132is a dry or wet etching process, respectively. To the extent that there is any over-etching of the substrate112during the etching process132, such over-etched regions will eventually be filled with the material that will be used to form the isolation regions on the device100.

FIG. 2Edepicts the device100after several process operations have been per formed. Initially, the overfill material layer122is removed by performing an etching or solvent-based stripping process depending upon the material used for the overfill material layer122. Thereafter, a layer of insulating material140, e.g., silicon dioxide (which may be in various deposition forms), etc., is blanket-deposited on the device100such that it overfills the trenches114.FIG. 2Edepicts the device100after one or more chemical mechanical polishing (CMP) processes have been performed to remove the patterned hard mask118and to planarize the upper surface140S with the now-exposed upper surface116S of the remaining fins116. These process operations initially define the illustrative isolation regions140A-140C in the areas that includes at least the area that was formerly occupied by the fins116that were removed from the initial “sea-of-fins.”

FIG. 2Fdepicts the device100after an etching process was performed to recess the upper surface of the layer of insulating material140so as to effectively expose the fins116to their desired final fin height116H, e.g., about 20-40 nm. At the point of fabrication depicted inFIG. 2F, traditional manufacturing operations may be performed to complete the fabrication of the FinFET device100, e.g., gate formation, source/drain implants, fin epi, contact formation, etc.

FIGS. 3A-3Edepict one illustrative embodiment of a method disclosed herein of forming isolation structures and fins on a FinFET semiconductor device101that is formed on an SOI substrate150. The SOI substrate150is generally comprised of a bulk substrate150A, a buried insulation layer150B and an active layer150C. The illustrative FinFET device101is formed in and above the active region150C.

FIG. 3Adepicts the device101at a point of fabrication after the trench-formation etching processes were performed through the patterned mask layer118to form the trenches114that define the “sea-of-fins”116. In this example, there are regions of the substrate150wherein the fins116are formed with different fin pitches. InFIG. 3A, the layer of overfill material122and the patterned mask layer124have also been formed. The mask layer124has a plurality of openings124A-124C positioned above various fins116that are the subset of fins that are to be removed. In the depicted example, only a single fin will be removed to make room for the isolation region. However, as noted before, depending upon the desired final size of the isolation regions, more than one fin116may be included in the subset of fins to be removed.

Next, as shown inFIG. 3B, one or more dry fin-exposure etching processes are performed through the masking layer124to define the cavities126that expose the upper surfaces116S of the underlying fins116. In the depicted example, the fin-exposure etching processes remove underlying portions of the overfill material layer122and the hard mask layer118.FIG. 3Cdepicts the device100after several process operations have been performed. First, the patterned mask layer126was removed. Thereafter, the etching process132was performed to remove the exposed fins116selectively relative to the overfill material layer122and thereby define the openings134in the overfill material layer122. In this embodiment, the etching process132stops on the underlying buried insulation layer150B.

FIG. 3Ddepicts the device100after several process operations have been performed. Initially, the overfill material layer122was removed by performing an etching or solvent-based stripping process depending upon the material used for the overfill material layer122. At the point of fabrication depicted inFIG. 3D, traditional manufacturing operations may be performed to complete the fabrication of the FinFET device101, e.g., gate formation, source/drain implants, fin epi, contact formation, etc.