Buffer circuit and switching controller

A buffer circuit includes a first inverter circuit that inverts an input signal, a second inverter circuit that inverts the output signal of the first inverter circuit, an impedance element connected between the first inverter circuit and the second inverter circuit, a first conductivity type switching element that increases a potential of the output node of the second inverter circuit when the input signal exceeds a first threshold voltage, and a second conductivity type switching element that decreases a potential of the output node of the second inverter circuit when the input signal is lower than a second threshold voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-026944, filed Feb. 14, 2013, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a buffer circuit and a switching controller having the buffer circuit.

BACKGROUND

The high frequency circuit section of a cell phone, smart phone, or other portable terminals includes a transmitting circuit, a receiving circuit, and a high frequency switching circuit. Generally, the transmitting circuit and the receiving circuit are connected to a shared antenna via the high frequency switching circuit. Currently, most portable terminals are made to be multi-mode and multi-band compatible. As a result, the number of ports needed for the high frequency switching circuit has increased to accommodate multi-mode/multi-band operations. As the port number increases, the number of bits of the control signal needed for controlling the connecting state of the high frequency switching circuit also increases.

For an integrated circuit (IC) containing the high frequency switching circuit, in order to decrease the number of terminals needed for the control signals, serial control signals may be input. In this case, to convert the serial control signal to a parallel control signal, a series-parallel converter is arranged inside the IC.

The series-parallel converter carries out the series/parallel conversion for the control signal in synchronization with a clock signal. The frequency of the clock signal can be about 26 MHz, for example. In this case, the rise time and fall time of the clock signal each are about 1 ns and a harmonic of about 1 GHz is generated. Because this harmonic has a frequency close to the frequency of the high frequency signal switched by the high frequency switching circuit, the harmonic will be superposed as noise on the high frequency signal.

DETAILED DESCRIPTION

Embodiments provide a buffer circuit that can suppress a harmonic in the high frequency band generated by a high frequency switching circuit and a switching controller that includes a buffer circuit of this type.

In general, embodiments will be described with reference to the figures.

An embodiment provides a buffer circuit including a first inverter circuit that receives an input signal and outputs an inverted input signal. A second inverter circuit of the buffer circuit receives the inverted input signal and outputs an output signal. An impedance element is connected between an output node of the first inverter circuit and an input node of the second inverter circuit. A switching element of a first conductivity type increases the potential of an output node of the second inverter circuit when the input signal exceeds a first threshold voltage. A switching element of a second conductivity type decreases potential of the output node of the second inverter circuit when the input signal is lower than a second threshold voltage.

First Embodiment

FIG. 1is a block diagram illustrating the schematic configuration of semiconductor device2including a switching controller1according to the first embodiment. The semiconductor device2shown inFIG. 1can be formed as a one-chip configuration. However, semiconductor device2may also comprise plural chips and some component parts may be discrete parts on the same chip or located on another chip.

According to the present embodiment, the entirety of the semiconductor device2shown inFIG. 1is formed on a single silicon-on-insulator (SOI) substrate. Because the SOI substrate has a high resistance, it is possible to suppress the loss of signal due to leakage of the high frequency signal to the substrate side.

The semiconductor device2shown inFIG. 1can be conceptually divided into a switching controller1and a high frequency switching circuit3. The high frequency switching circuit3selects one of the plural RF signal terminals RF1to RFn and is connected to the antenna terminal RF_COM. The plural RF signal terminals RF1to RFn are connected to a transceiver (not shown inFIG. 1). The transceiver can generate individual RF signals for each wireless system so that the semiconductor device2can cope with plural wireless systems. In conventional wireless equipment, at least one of the semiconductor devices2shown inFIG. 1would be included.

The switching controller1includes a buffer circuit4, a series-parallel converter5, and a driver circuit6.

The buffer circuit4carries out a waveform shaping treatment for a clock signal CLK input from the semiconductor device2. The clock signal is input to the series-parallel converter5after having its waveform shaped by the buffer circuit4.

The series-parallel converter5converts a serial switching control signal that instructs the switching of the high frequency switching circuit3to a parallel switching control signal in synchronization with the clock signal.

On the basis of the parallel switching control signal converted by the series-parallel converter5, the high frequency switching circuit3selects and outputs to one of the plural RF signal terminals RF1to RFn.

FIG. 2is a block diagram illustrating an example internal configuration of the buffer circuit4and the series-parallel converter5. As shown inFIG. 2, the buffer circuit4includes a clock input buffer7and a data input buffer8. The clock input buffer7carries out waveform shaping for the clock signal CLK received at the CLK input terminal. The data input buffer8buffers and outputs the serial switching control signal data received at the DATA input terminal.

The series-parallel converter5shown inFIG. 2includes plural D type flip-flops (hereinafter to be referred to as DFF)9connected in series. The clock signal CK_int output from the buffer circuit4is input to each of the clock terminals CK of the DFF9. The input terminal D of the initial-step DFF9receives the serial switching control signal data output from the data input buffer8. As a result, the serial switching control signal data are sequentially propagated and output in the DFF9in synchronization with the clock signal CLK. From the output terminals Q of the DFF9, the parallel switching control signals D1, D2, D3obtained by the series-parallel conversion of the serial switching control signal data are output.

FIG. 3is a circuit diagram illustrating an example of the configuration of the clock input buffer7. The clock input buffer7shown inFIG. 3includes a first inverter circuit INV1, a second inverter circuit INV2, an impedance element25, a first conductivity type switching element26, and a second conductivity type switching element27.

The first inverter circuit INV1is a Schmitt trigger type inverter circuit having hysteresis characteristics, and first inverter circuit INV1inverts and outputs the input signal IN. The input signal IN is the clock signal CLK.

More specifically, the first inverter circuit INV1includes PMOS transistors P1to P3and NMOS transistors N1to N3. The PMOS transistors P1, P2and the NMOS transistors N2, N1are connected in series between the power supply voltage Vdd and the ground voltage (the second reference voltage) Vss. Gates o of transistors P1, P2, N1, N2are connected to the input signal IN. The drains of the PMOS transistor P2and the NMOS transistor N2are connected to the gates of the PMOS transistor P3and the NMOS transistor N3, respectively. The source of the PMOS transistor P3is connected to the drain of the PMOS transistor P1and the source of the PMOS transistor P2. The drain of the PMOS transistor P3is set at the ground voltage Vss. The drain of the NMOS transistor N3is set at the power supply voltage Vdd, and the source of the NMOS transistor N3is connected to the source of the NMOS transistor N2and the drain of the NMOS transistor N1.

The second inverter circuit INV2inverts and outputs the output signal of the first inverter circuit INV1. The second inverter circuit INV2includes a PMOS transistor (second PMOS transistor) P4and an NMOS transistor (second NMOS transistor) N4connected in series between the power supply voltage Vdd and the ground voltage Vss.

The impedance element25is made of, for example, a resistor element R1connected between the output node of the first inverter circuit INV1and the input node of the second inverter circuit INV2.

For a first conductivity type switching element26, when the input signal is over a first threshold voltage, the element26increases the potential at the output node of the second inverter circuit INV2. As an example of the first conductivity type switching element26, it is an NMOS transistor (first NMOS transistor) N5of which drain the power supply voltage Vdd (the first reference voltage) is applied to, with the output node of the second inverter circuit INV2being connected to its source, and it includes its gate connected to the input node IN.

When the input signal becomes lower than the second threshold voltage, the second conductivity type element27decreases the potential of the output node of the second inverter circuit INV2. An example of the second conductivity type element27is a PMOS transistor (first PMOS transistor) P5that has the output node OUT of the second inverter circuit INV2connected to its source, the drain set at the ground voltage Vss, and the gate connected to the input node IN.

By arranging the impedance element25between the output node of the first inverter circuit INV1and the input node of the second inverter circuit INV2, the waveform of the clock signal CLK output from the first inverter circuit INV1becomes gentler, and the harmonic component of the clock signal CLK is decreased.

However, as the impedance element25also causes the delay time of the clock signal CLK to become longer. Here, according to the present embodiment, the PMOS transistor P5and the NMOS transistor N5are arranged on the later section side of the second inverter circuit INV2. Thus, when the potential of the clock signal CLK output from the first inverter circuit INV1makes a transition from the low level to the high level, the PMOS transistor P5makes a transition from ON to OFF, while the NMOS transistor N5makes a transition from OFF to ON. However, during the transition process, the drains of the PMOS transistor P5and the NMOS transistor N5reach a high impedance state. The reason is that for both transistors, the gate-source voltage becomes lower than the threshold voltage in this case. Consequently, at the output node of the clock input buffer7, the potential starts changing before the change in the potential at the input node of the second inverter circuit INV2. However, such a change in the potential takes place until halfway point is reached and the potential then varies in synchronization with the inverted output timing. As a result, for the clock input buffer7, although there is no significant change in the hysteresis characteristics of the first inverter circuit INV1, a Schmitt trigger type inverter circuit, it is still possible to shorten the delay time generated by the impedance element25.

FIG. 4is a circuit diagram illustrating the detailed configuration of the clock input buffer7according to a comparative example. The comparative example clock input buffer7shown inFIG. 4is lacking impedance element25, the first PMOSFET, and the PMOS transistor P5from the circuit configuration shown inFIG. 3.

FIG. 5is a graph showing the input/output characteristics of the clock input buffers7shown inFIG. 3andFIG. 4.FIG. 5shows the waveform w1of the clock signal CLK (input clock signal CLK) input to each clock input buffer7, the waveform w2of the clock signal CLK (output clock signal CLK) output from the clock input buffer7shown inFIG. 3, and the waveform w3of the clock signal CLK (output clock signal CLK) output from the clock input buffer7shown inFIG. 4.

As can be seen fromFIG. 5, the delay times of the waveform w2and waveform w3with respect to the waveform w1are almost identical to each other. However, the slope of waveform w2at the rising edge and the falling edge is gentler (less steep) than that of waveform w3.

FIG. 6includes frequency spectrum diagrams corresponding to the graph shown inFIG. 5.FIG. 6Ais a frequency spectrum diagram of the output clock signal CLK of the clock input buffer7shown inFIG. 3.FIG. 6Bis a frequency spectrum diagram of the output clock signal CLK of the clock input buffer7shown inFIG. 4.

As can be seen by comparingFIG. 6AwithFIG. 6B, in the case shown inFIG. 6A, it is possible to suppress the harmonic component near 1 GHz as the frequency band of the high frequency signal switched and controlled by the high frequency switching circuit3, on the other hand, in the case shown inFIG. 6B, the harmonic component near 1 GHz is significant. This result indicates that when the clock input buffer7shown inFIG. 3is used, there is significantly less adverse influence on the high frequency switching circuit3that switches and controls the high frequency signal of the 1 GHz band.

FIG. 5,FIG. 6A, andFIG. 6Billustrate the results of a simulation where it is assumed that MOS transistors formed on an SOI substrate are used to form the clock input buffer7. Here, for these simulated MOS transistors, the gate length is 0.25 μm and the gate oxide film thickness is 9 nm, while the values of the gate width Wg of the NMOS transistor N4and PMOS transistor P4that form the second inverter circuit INV2in the clock input buffer7, as well as the NMOS transistor N5and PMOS transistor P5, are set as follows:

Wg of the NMOS transistor=16 μm, Wg of the PMOS transistor=32 μm

Wg of the NMOS transistor N5=32 μm, Wg of the PMOS transistor=32 μm

Also, the simulated impedance element25has a resistance of 10 kΩ, and the output capacitance of the output node of the clock input buffer7is 1 pF.

In the following, the circuit constant of the clock input buffer7will be explained in detail. As explained above, by arranging the impedance element25, the input waveform for the second inverter circuit INV2including of the NMOS transistor N4and the PMOS transistor P4becomes gentler, and it is possible to decrease the harmonic noise of a component with the same frequency as that of the high frequency signal that is being switched and controlled by the high frequency switching circuit3.

However, as the impedance of the impedance element25is increased, the delay time in the output signal with respect to the input signal to the clock input buffer7is increased.

FIG. 7is a circuit diagram illustrating the clock input buffer7according to another comparative example.FIG. 8is a graph showing the results of a simulation of the delay time of the output signal with respect to the input signal of the clock input buffer7shown inFIG. 7.FIG. 8shows the waveform of the input signal IN and the waveform of the output node OUT when the impedance element25has different resistance values.

As shown inFIG. 8, when the resistance of the impedance element25is increased, the delay time of the output node OUT increases.

On the other hand,FIG. 9Ais a circuit diagram in which only the NMOS transistor N5and the PMOS transistor P5connected to the last section of the clock input buffer7shown inFIG. 3are shown.FIG. 9Bis a diagram illustrating simulation results for the circuit shown inFIG. 9A.FIG. 9Bshows the waveform of the input signal IN and the waveform of the output node OUT when the NMOS transistor N5and the PMOS transistor P5have different gate widths Wg5.

As can be seen fromFIG. 9B, the larger the gate widths Wg5of the NMOS transistor N5and the PMOS transistor P5, the steeper the rising edge of the output node OUT.

As the input signal is input to the gates of the NMOS transistor N5and the PMOS transistor P5, respectively, as the potential of the input signal changes, the potential at the output node OUT changes quickly for the NMOS transistor N5and the PMOS transistor P5. In this case, it can be seen from the results of the simulation shown inFIG. 9Bthat when the gate width is larger for the NMOS transistor N5and the PMOS transistor P5, the potential at the output node OUT can change more quickly.

Consequently, the gate widths Wg5of the NMOS transistor N5and the PMOS transistor P5are preferably close to or larger than the gate widths of the NMOS transistor N4and the PMOS transistor P5.

One may also adopt a scheme in which the gate length is adjusted instead of the gate width. Consequently, it is preferred that to adjust the gate width and/or the gate length to meet the following relationship for the MOS transistors N4, P4, N5, P5in the clock input buffer7.
MIN[Wg(N4)/Lg(N4),Wg(P4)/Lg(P4)]≦MIN[Wg(N5)/Lg(N5),Wg(P5)/Lg(P5)]  (1)

Here, Wg(N4) represents the gate width of the NMOS transistor N4, Lg (N4) represents the gate length of the NMOS transistor N4, Wg (N5) represents the gate width of the NMOS transistor N5, and Lg (N5) represents the gate length of the NMOS transistor N5. Similarly, Wg(P4) represents the gate width of the PMOS transistor P4, Lg (P4) represents the gate length of the PMOS transistor P4, Wg (P5) represents the gate width of the PMOS transistor P5, and Lg (P5) represents the gate length of the PMOS transistor P5.

The above-listed formula (I) indicates that the value obtained by dividing the channel width of the PMOS transistor P5by its channel length or the value obtained by dividing the channel width of the NMOS transistor N5by its channel length, whichever is smaller, is equal to or larger than the value obtained by dividing the channel width of the PMOS transistor P4by its channel length or the value obtained by dividing the channel width of the NMOS transistor N4by its channel length, whichever is smaller.

In this way, when the clock signal CLK is generated by the clock input buffer7, the clock signal CLK is not significantly delayed, and the waveforms of the rising edge and the falling edge of the clock signal CLK are gentler. Consequently, the harmonic at a frequency close to the high frequency signal switched and controlled by the high frequency switching circuit3generated from the clock signal CLK is suppressed, and the high frequency switching circuit3is barely influenced by the harmonic noise.

In the above, an example of the configuration of the circuit of the clock input buffer7shown inFIG. 3is explained. However, it may be preferable that the data input buffer8shown inFIG. 2also be formed using the circuit shown inFIG. 3to limit harmonic noise generated from the data input to the series-parallel converter5as well.

Second Embodiment

In the second embodiment to be explained below, the harmonic noise can be further suppressed as compared with the first embodiment.

The semiconductor device2according to a second embodiment has the same schematic configuration as that shown inFIG. 1.FIG. 10is a diagram illustrating a layout of series-parallel converter5in the semiconductor device2according to the second embodiment. For example, the semiconductor device2may be formed in plural layers on an SOI substrate.

In a bottom layer (the second pattern layer), plural power supply voltage (Vdd) pattern portions11are formed in a comb shape, and plural ground (GND) pattern portions12are formed in a comb shape in the gaps formed by pattern portions11.

For example, the series-parallel converter5can be formed using standard cells13. Here, the standard cells13are usually formed in the bottom layer.FIG. 10shows the cell arrangement regions of the DFF1to DFF13that form the series-parallel converter5. The regions of the DFF1to DFF13are depicted as respective rectangular blocks.

The clock signal CK fed to each DFF is routed in a prescribed layer (the first pattern layer) of the second layer or higher layer. According to the present embodiment, the ground pattern portions12are arranged in the first layer (e.g., below the prescribed layer in the second pattern layer) along the pattern14of the clock signal CK. As a result, the harmonic noise generated from the clock signal CK does not significantly propagate to the substrate side, and no harmonic noise is superposed on the high frequency switching circuit3formed on the same substrate. That is, according to the present embodiment, because no other circuit block is arranged below the pattern14, it is possible to avoid the capacitive coupling of the pattern14carrying the clock signal CK with the other circuit blocks, and the harmonic noise generated from the clock signal CK is not superposed on the other signals.

FIG. 11is a diagram illustrating a comparative example of the layout pattern generated by the automatic arranging wiring tool without pattern14arranged along the ground pattern portions12. In the case ofFIG. 11, the position of the pattern14of the clock signal CK and the position of the ground pattern portions12are offset from each other.

A simulation of the harmonic noise for the layout diagram shown inFIG. 10and the harmonic noise for the layout diagram shown inFIG. 11was made.

FIG. 12is the circuit diagram used in generating the simulation results. The circuit shown inFIG. 12is a clock input buffer7in the configuration of the Schmitt trigger circuit, and the load capacitance15is connected to its output. Because the RF_COM line of the high frequency switching circuit3shown inFIG. 1is of a 50Ω system, the circuit shown inFIG. 12is modeled by the wiring having the two ends terminated by 50Ω. The coupling capacitance16is connected between the clock signal CK and the RF_COM line. The frequency of the clock signal CK output from the clock input buffer7is set at 25 MHz.

In order to determine the value of the coupling capacitance16, an analysis of the electromagnetic field for both the layout diagram of the present embodiment shown inFIG. 10and the layout diagram of the comparative example shown inFIG. 11was carried out. As a result, for the layout diagram shown inFIG. 11, the coupling capacitance=2.4 fF, and, for the layout diagram shown inFIG. 10, the coupling capacitance=0.1 fF.

FIG. 13is a graph showing the simulation results for the layout diagram in the present embodiment shown inFIG. 10.FIG. 14is a graph showing the simulation results in a comparative example shown inFIG. 11.

As far as the noise level at frequency of 825 MHz is concerned, it is −103.6 dBm for the comparative example shown inFIG. 14and it is −131.1 dBm in the present embodiment shown inFIG. 13. Consequently, the noise level is improved by 27.5 dB.

For cell phones, it is generally required that the noise level in the high frequency switching circuit3be −130 dBm or lower. As can be seen fromFIG. 13, this requirement can be met by this embodiment.

FIG. 15is a graph showing the dependence of the noise power on the coupling capacitance. Here, the abscissa represents the coupling capacitance (fF) and the ordinate represents the spurious signal (MHz). According toFIG. 15, to suppress the noise level to −130 dBm or lower, a coupling capacitance of 0.12 fF or smaller is required.

In this way, as the ground pattern portions12are formed along the pattern14in a layer below the pattern14such that it is possible to suppress the capacitive coupling of the harmonic noise generated in series-parallel converter5with another circuit block via the semiconductor substrate. In particular, according to the present embodiment, it is possible to prevent the capacitive coupling of the harmonic noise of the clock signal CK of the series-parallel converter5to the high frequency switching circuit3, so that it is possible to decrease the harmonic noise in the high frequency switching circuit3.

FIG. 16shows a modified example of the layout diagram of the series-parallel converter5shown inFIG. 10. For the layout diagram shown inFIG. 16, the first to third layers are the same as those shown inFIG. 10, and a fourth layer made of a solid ground layer17is added.FIG. 16shows the fourth layer made of the solid ground layer17as a diagonal hatching. The solid ground layer17is arranged so that it covers the entirety of the layout block of the series-parallel converter5, and it is connected to the ground pattern portions12on the first layer through via holes18.

As shown inFIG. 16, by arranging the solid ground layer17, it is possible to further decrease the capacitive coupling on the upper surface side of the layout substrate, so that it is possible to further decrease noise.

FIG. 17is a layout diagram illustrating an example of the layout configuration of the semiconductor device2with the same configuration as that shown inFIG. 1having the series-parallel converter5according to the present embodiment. According to the layout diagram shown inFIG. 17, the ground layer19formed in the first layer is arranged between the series-parallel converter5and the high frequency switching circuit3. In the example shown inFIG. 17, the configuration of the layout of the series-parallel converter5is the same as that shown inFIG. 10. However, one may also adopt a scheme in which it is the same as that shown inFIG. 16.

As shown inFIG. 17, the clock input buffer7that feeds the clock signal CK to the series-parallel converter5and the CLK pad20that receives the clock signal CLK from the outer side are arranged on the side opposite to the ground layer19, with the series-parallel converter5sandwiched between them.

As a result, it is possible to significantly decrease the harmonic noise in the high frequency switching circuit3caused by the capacitive coupling of the harmonics generated in the clock signal CK input from the CLK pad20, the clock signal CK output from the clock input buffer7, and the clock signal CK propagating in the series-parallel converter5.

According to the second embodiment, the circuit configuration of the clock input buffer7is taken to be the same as that in the first embodiment in the explanation. However, one may also adopt a scheme in which the circuit configuration of the clock input buffer7is that shown inFIG. 4orFIG. 7, although the danger of the generation of harmonic noise may be increased in such a case.

Third Embodiment

According to a third embodiment, the clock signal CK input to the series-parallel converter5is assumed to be a differential signal.

The semiconductor device2according to the third embodiment has the same block configuration as that shown inFIG. 1.FIG. 18is a circuit diagram of the buffer circuit4and the series-parallel converter5according to the third embodiment. The plural register circuits9connected in series in the series-parallel converter5shown inFIG. 18respectively include differential clock input terminals CK, CK/. The clock input buffer7includes plural inverter circuits21that output the clock signal CK input from the outer side in differential form.

As shown inFIG. 18, the differential clock signals CK_int, CK_int/output from the clock input buffer7are output via plural inverter circuits21, so that a delay takes place. Here, in order to adjust the delay time, the data input buffer8also includes plural inverter circuits21connected in series.

It is preferred that the differential clock signals CK_int, CK_int/ output from the clock input buffer7have the phases accurately offset by 180°. Here, by making appropriate adjustment of the circuit constants of the MOS transistors (not shown) in the inverter circuits21, it is possible to accurately set the phases of the differential clock signals CK_int, CK_int/ offset by 180°.

Also, it is preferred that the signal pattern of the differential clock signals CK_int, CK_int/ be formed by using metal portions on the same layer which are as close as possible on the substrate and with the same width so that the harmonic noises superposed on the differential clock signals CK_int, CK_int/ output from the clock input buffer7cancel each other, so that harmonic noise is not superposed on the high frequency switching circuit3.

The third embodiment may be executed in combination with the second embodiment. That is, the ground layer may be arranged along the signal pattern of the differential clock signals CK_int, CK_int/ in another layer different from the layer in which the signal pattern of the differential clock signals is arranged. In addition, one may also adopt a scheme in which a solid ground layer is arranged in yet another layer so that it covers the entirety of the layout block of the series-parallel converter5. In addition, one may also adopt a scheme in which, as shown inFIG. 17, a ground layer is arranged between the series-parallel converter5and the high frequency switching circuit3.

The third embodiment may also be executed in combination with the first embodiment. That is, the inverter circuits21connected in series in the clock input buffer7may have the configuration shown inFIG. 3.

Fourth Embodiment

A fourth embodiment has the same block configuration as that shown inFIG. 1.FIG. 19is a circuit diagram illustrating buffer circuit4and series-parallel converter5according to the fourth embodiment. A dummy inverter circuit (a third inverter circuit)22is connected to the output node of the clock input buffer7shown inFIG. 19. A capacitor C1is arranged between the output node of the dummy inverter circuit22and the ground node (reference voltage node). By adjusting the capacitance value of the capacitor C1and the location of capacitor C1, it is possible to suppress the harmonic noise generated from clock signal CK fed to the series-parallel converter5.

The harmonic noise is suppressed as follows: The clock signal CK output from the clock input buffer7and the clock signal CK output from the dummy inverter circuit22have a phase difference of 180° from each other, so that they may, ideally, each cancel the harmonic noises of the other.

In this way, according to the fourth embodiment, the dummy inverter circuit22and the capacitor C1are connected in series with the output node of the clock input buffer7, and the capacitance value of the ground capacitor and the site for arranging the capacitor C1can be adjusted. As a result, it is possible to suppress the harmonic noise generated from the clock signal CK fed to the series-parallel converter5, and it is possible to decrease the harmonic noise superposed on the high frequency switching circuit3.

Fifth Embodiment

For the semiconductor device shown inFIG. 1, the ground terminal for the series-parallel converter5and the ground terminal for the other circuits are usually separated from each other. The reason is as follows: For example, suppose a high frequency signal is applied on the high frequency switching circuit3, or suppose the series-parallel converter5works in synchronization with the clock signal CK, the ground potential may undergo significant variation and, under its influence, the ground potential level of the other circuit blocks also varies, so that mis-operation may take place.

However, when the ground for the series-parallel converter5and the ground for the other circuits are separated from each other, the potential level of one ground terminal may still vary for one or the other, for example, when the series-parallel converter5carries out the series-parallel conversion operation in synchronization with the clock signal CK, the ground potential level for the series-parallel converter5varies. However, in this case, suppose the ground potential level for the other circuit blocks is constant, in the later-section circuit that receives the parallel switching control signal output from the series-parallel converter5, this case may be recognized as a variation in the potential level of the parallel switching control signal, and mis-operation may take place.

In a fifth embodiment a measure is taken to ensure that such a type of mis-operation does not take place.

FIG. 20is a block diagram illustrating the schematic configuration of the semiconductor device2in the fifth embodiment. InFIG. 20, the same keys as those inFIG. 1are adopted to represent the common elements. In the following, only the different features will be explained in detail. The semiconductor device2shown inFIG. 20includes a noise removing circuit31and a decoder circuit32between the series-parallel converter5and the driver circuit6. However, the decoder circuit32is not a necessity. The ground for the series-parallel converter5and the ground for the other circuit blocks are arranged as indicated with GND1connected to the series-parallel converter5and GND2connected to the other circuit blocks.

The noise removing circuit31includes plural Schmitt trigger buffer sections33connected to the parallel switching control signals output from the series-parallel converter5, respectively.

FIG. 21is a circuit diagram illustrating an example of the internal configuration of the Schmitt trigger buffer section33. The Schmitt trigger buffer section33shown inFIG. 21includes PMOS transistors P6to P9and NMOS transistors N5to N9.

The PMOS transistors P6, P7, the NMOS transistors N5, N7, and the PMOS transistors are connected in series between the power supply voltage Vdd and the ground voltage Vss, and the gates of the transistors are connected to the input node IN.

The gate of the PMOS transistor P8is connected to the two drains of the PMOS transistor P7and the NMOS transistor N5. The source of the PMOS transistor P8is connected to the drain of the PMOS transistor P6and the source of the PMOS transistor P7, and the drain of the PMOS transistor P8is connected to the ground.

The gate of the NMOS transistor N8is connected to the two drains of the PMOS transistor P7and the NMOS transistor N5. The drain of the NMOS transistor is set at the power supply voltage Vdd, and the source of the NMOS transistor is connected to the source of the NMOS transistor N5and the drain of the NMOS transistor N7.

The PMOS transistor P9and the NMOS transistor N9are connected in series between the power supply voltage Vdd and the ground voltage Vss. The drains of these transistors are connected to the output node OUT, and the gates are connected to the two drains of the PMOS transistor P7and the NMOS transistor N5.

The Schmitt trigger buffer section33has hysteresis characteristics. Consequently, when the input signal to the Schmitt trigger buffer section33exceeds the threshold voltage, the logic state of the output signal is inverted; then, even when the potential level of the input signal varies slightly, there is still no change in the logic state of the output signal. As a result, it is possible to suppress variation in the output potential of the Schmitt trigger buffer section33.

For the decoder circuit32, as the output signal of the noise removing circuit31made of the Schmitt trigger buffer section33is sent to it, the potential level of the input signal to the decoder circuit32is barely influenced by the noise. As shown inFIG. 20, even when the ground for the series-parallel converter5and the ground for the other circuit blocks are separated from each other, the decoder circuit32is still barely be influenced by the potential variation of the ground of the series-parallel converter5.