NAND PILLAR MEMORY DEVICE AND METHOD

Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include memory strings with a conductor channel shell and a low dielectric constant central region. In one example, memory devices, systems and methods include memory strings with a conductor channel shell and a hollow central region.

BACKGROUND

Memory devices are semiconductor circuits that provide electronic storage of data for a host system (e.g., a computer or other electronic device). Memory devices may be volatile or non-volatile. Volatile memory requires power to maintain data, and includes devices such as random-access memory (RAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), or synchronous dynamic random-access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory, such as phase change random access memory (PCRAM), resistive random-access memory (RRAM), or magnetoresistive random access memory (MRAM), among others.

Host systems typically include a host processor, a first amount of main memory (e.g., often volatile memory, such as DRAM) to support the host processor, and one or more storage systems (e.g., often non-volatile memory, such as flash memory) that provide additional storage to retain data in addition to or separate from the main memory.

A storage system, such as a solid-state drive (SSD), can include a memory controller and one or more memory devices, including a number of dies or logical units (LUNs). In certain examples, each die can include a number of memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller can include interface circuitry configured to communicate with a host device (e.g., the host processor or interface circuitry) through a communication interface (e.g., a bidirectional parallel or serial communication interface). The memory controller can receive commands or operations from the host system in association with memory operations or instructions, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data or address data, etc.) between the memory devices and the host device, erase operations to erase data from the memory devices, perform drive management operations (e.g., data migration, garbage collection, block retirement), etc.

The present description relates generally to example structures and associated methods for vertical stacked memory cells, strings, and arrays.

DETAILED DESCRIPTION

FIG.1shows a block diagram of an apparatus in the form of a memory device100, according to an embodiment of the invention. Memory device100can include a memory array102having memory cells103that can be arranged in rows and columns along with lines (e.g., access lines)104and lines (e.g., data lines)105. In one example, memory cells103are arranged in memory strings that are further arranged in rows and columns. Memory device100can use lines104to access memory cells103and lines105to exchange information with memory cells103.

Row access108and column access109circuitry can respond to an address register112to access memory cells103based on row address and column address signals on lines110,111, or both. A data input/output circuit114can be configured to exchange information between memory cells103and lines110. Lines110and111can include nodes within memory device100or pins (or solder balls) on a package where memory device100can reside.

A control circuit116can control operations of memory device100based on signals present on lines110and111. A device (e.g., a processor or a memory controller) external to memory device100can send different commands (e.g., read, write, or erase commands) to memory device100using different combinations of signals on lines110,111, or both.

Memory device100can respond to commands to perform memory operations on memory cells103, such as performing a read operation to read information from memory cells103or performing a write (e.g., programming) operation to store (e.g., program) information into memory cells103. Memory device100can also perform an erase operation to clear information from some or all of memory cells103.

Memory device100can receive a supply voltage, including supply voltages Vcc and Vss. Supply voltage Vss can operate at a ground potential (e.g., having a value of approximately zero volts). Supply voltage Vcc can include an external voltage supplied to memory device100from an external power source such as a battery or an alternating-current to direct-current (AC-DC) converter circuitry.

Each of memory cells103can be programmed to store information representing a value of a fraction of a bit, a value of a single bit, or a value of multiple bits such as two, three, four, or another number of bits. For example, each of memory cells103can be programmed to store information representing a binary value “0” or “1” of a single bit. The single bit per cell is sometimes called a single level cell. In another example, each of memory cells103can be programmed to store information representing a value for multiple bits, such as one of four possible values “00,” “01,” “10,” and “11” of two bits, one of eight possible values “000,” “001,” “010,” “011,” “100,” “101,” “110,” and “111” of three bits, or one of other values of another number of multiple bits. A cell that has the ability to store multiple bits is sometimes called a multi-level cell (or multi-state cell).

Memory device100can include a non-volatile memory device, and memory cells103can include non-volatile memory cells, such that memory cells103can retain information stored thereon when power (e.g., Vcc, Vss, or both) is disconnected from memory device100. For example, memory device100can be a flash memory device, such as a NAND flash or a NOR flash memory device, or another kind of memory device, such as a variable resistance memory device (e.g., a phase change or resistive RAM device).

Memory device100can include a memory device where memory cells103can be physically located in multiple levels on the same device, such that some of memory cells103can be stacked over some other memory cells103in multiple levels over a substrate (e.g., a semiconductor substrate) of memory device100.

One of ordinary skill in the art may recognize that memory device100may include other elements, several of which are not shown inFIG.1, so as not to obscure the example embodiments described herein.

FIG.2Ashows a schematic diagram of a portion of a memory device200A having a memory array202A with a gate280(e.g., a shared bottom source select gate), according to an embodiment of the invention. Gate280can form part of a select line (e.g., source select line) of memory device200A. Memory device200A can include control gates250,251,252, and253that can carry corresponding signals WL0, WL1, WL2, and WL3. Each of control gates250,251,252, and253can form part of a respective access line of memory device200A. Memory device200A can include lines270,271, and272that carry signals BL0, BL1, and BL2, respectively. Each of lines270,271, and272can form part of a respective data line of memory device200A.FIG.2Ashows four control gates250,251,252, and253and three lines270,271, and272as an example. The number of such control gates and lines can vary.

Memory device200A can include memory cells210,211,212, and213, and transistors (e.g., select transistors)261through268. Memory cells210,211,212, and213can be arranged in memory cell strings, such as memory cell strings231,232, and233. For simplicity, inFIG.2A, only three of the memory cell strings are labeled (231,232, and233).

Each memory cell string in memory device200A can be coupled to two associated transistors among transistors261through268. For example, memory cell string231can be coupled to transistor262(directly under string231) and transistor266(directly over string231).

FIG.2Ashows an example of twelve memory cell strings and four memory cells210,211,212, and213in each memory cell string. The number of such memory cell strings and number of such memory cells in each memory cell string can vary.

As shown inFIG.2A, transistors261,262,263, and264can share the same gate280. Thus, transistors261,262,263, and264can be controlled (e.g., turned on or turned off) by the same signal, such as an SGS signal (e.g., source select gate signal) associated with gate280. Transistors261,262,263, and264can include body regions241,242,243, and244, respectively. During a memory operation, such as a read or write operation, transistors261,262,263, and264and can be turned on (e.g., by activating an SGS signal) to couple the memory cell strings of memory device200A to a line299through body regions241,242,243, and244. Transistors261,262,263, and264can be turned off (e.g., by deactivating the SGS signal) to decouple the memory cell strings of memory device200A from line299. Line299can form part of a source (e.g., a source line) of memory device200A and can carry a signal, such as signal SL (e.g., source line signal).

Transistors265,266,267, and268can include separate gates (e.g., drain select gates)285,286,287, and288. However, transistors265can share the same gate285. Transistors266can share the same gate286. Transistors267can share the same gate287. Transistors268can share the same gate288. Each of gates285,286,287, and288can form part of a respective select line (e.g., drain select line) of memory device200A.

Transistors265,266,267, and268and can be controlled (e.g., turned on or turned off) by corresponding SGD0, SGD1, SGD2, and SGD3signals (e.g., drain select gate signals) in order to selectively couple the memory cell strings of memory device200A to their respective lines270,271, and272, during a memory operation, such as a read or write operation. For example, during a memory operation, the SGD1signal can be activated to couple memory cell string231to line270. The SGD0, SGD2, and SGD3signals can be deactivated to decouple the other memory cell strings from line270. During a memory operation (e.g., a read or write operation), only one of the SGD0, SGD1, SGD2, and SGD3signals can be activated at a time.

Memory cells210,211,212, and213can be physically located in multiple levels of memory device200A, such that memory cells210,211,212, and213in the same memory cell string can be stacked over each other in multiple levels of memory device200A.

FIG.2Bshows a schematic diagram of a portion of a memory device200B having a memory array202B with a gate289(shared top drain select gate), according to an embodiment of the invention. Gate289can form part of a select line (e.g., drain select line) of memory device200A. Memory device200B includes elements that can be similar to or identical to those of memory device200A ofFIG.2A. For simplicity, detailed description of similar or the identical elements betweenFIG.2AandFIG.2Bis not repeated in the description ofFIG.2B.

As shown inFIG.2B, transistors265,266,267, and268can share the same gate289. Thus, transistors265,266,267, and268can be controlled (e.g., turned on or turned off) by the same signal, such as an SGD signal (e.g., source select gate signal) associated with gate289. During a memory operation, such as a read or write operation, transistors265,266,267, and268and can be turned on (e.g., by activating the SGD signal) to couple the memory cell strings of memory device200B to their respective lines270,271, and272. Transistors265,266,267, and268and can be turned off (e.g., by deactivating the SGD signal) to decouple the memory cell strings of memory device200B from lines270,271, and272.

Transistors261,262,263, and264can include separate gates (e.g., source select gates)281,282,283, and284. However, transistors261can share the same gate281. Transistors262can share the same gate282. Transistors263can share the same gate283. Transistors264can share the same gate284. Each of gates281,282,283, and284can form part of a respective select line (e.g., source select line) of memory device200A.

Transistors261,262,263, and264and can be controlled (e.g., turned on or turned off) by corresponding SGS0, SGS1, SGS2, and SGS3signals (e.g., source select gate signals) in order to selectively couple the memory cell strings of memory device200B to line299, during a memory operation, such as a read or write operation. For example, during a memory operation, the SGS1signal can be activated to couple memory cell string231to line299. The SGS0, SGS2, and SGS3signals can be deactivated to decouple the other memory cell strings from line299. During a memory operation (e.g., a read or write operation), only one of the SGS0, SGS1, SGS2, and SGS3signals can be activated at a time.

FIG.3shows an individual memory string300similar to memory strings231or232shown inFIGS.2A and2B. Memory string300includes a central pillar310including a conductor channel shell312. In the example ofFIG.3, the conductor channel shell312of the central pillar310defines a hollow central region314. The memory string300also includes a plurality of gates316along a length of the central pillar310. In one example, the plurality of gates316are similar to the gates of memory cells210,211,212, and213fromFIGS.2A and2B. In one example, the memory string300, including the plurality of gates316, is formed from a plurality of layers, including conductor layers306alternating with dielectric layers308. By patterning and building up conductor layers306and dielectric layers308, a memory device structure is formed that includes conducting elements that are isolated from one another by dielectric.

FIG.3further shows a source line304and a data line302coupled to ends of the conductor channel shell312. Source line304and data line302are similar to source line299and bit lines (BL0, BL1, BL2) fromFIGS.2A and2B. In operation, a charge can be stored adjacent to each of the gates316in the memory string300. The presence or absence, or charge level stored adjacent to each of the gates indicates a bit of data that is used to store information in the memory string300and more broadly in a memory device such as device100fromFIG.1.

As components of memory cells are reduced in size to increase memory density, device performance can be reduced. For example, decreased pitch between layers in a memory string stack can increase interference between adjacent cells in the string. As illustrated inFIG.3, as gates in the plurality of gates316become closer together, they can be more prone to interference with each other.

As noted above, in one example, a the conductor channel shell312of the central pillar310defines a hollow central region314. The hollow central region314helps to focus conduction within the more narrow cylindrical shell of the conductor channel shell312. This improves performance of the central pillar310as a conductor, and also provides a more confined charge profile for stored charge adjacent to each of the gates316in the memory string300. This can improve performance of memory strings and allow acceptable performance in memory strings with reduced pitch between layers in a memory string stack.

In one example, the conductor channel shell312includes polysilicon, although the invention is not so limited. Other conductors such as metals, metallic compounds, or other conductively doped semiconductors are also within the scope of the invention. In one example, the hollow central region314is filled with a gas. In one example, an inert gas is used, such as nitrogen or argon. In one example, the hollow central region314is filled with a mixture of gasses such as air. In one example, the hollow central region314is at least partially pressurized above ambient pressure. In one example, the hollow central region314is at least partially evacuated, although one of ordinary skill in the art will recognize that a vacuum is usually a matter of degree, and that a perfect vacuum is impossible to obtain. Pressurizing or evacuating the hollow central region further allows tuning of the dielectric constant (K) in the hollow central region. For example, for any given gas, pressurization or adding gas will raise the dielectric constant, and reducing pressure will lower the dielectric constant, when compared to the same gas at ambient pressure.

In one example the hollow central region314is filled with a low dielectric constant (K) material similar to a gas or a vacuum. In one example, the hollow central region314is filled with an oxide having a K less than 10. In one example, the hollow central region314is filled with an oxide having a K less than 5. In one example, the hollow central region314is filled with an oxide having a K less than 3.

In one example some, or all of a length of the central pillar310includes a hollow central region. A benefit as described above will be recognized for any fraction of a length of the central pillar310that includes a hollow central region314. In one example, substantially all of a length of the central pillar310includes a hollow central region314.

FIG.4shows a close up cross section view of a portion of a memory string400, similar to memory string300fromFIG.3. A plurality of gates416are shown adjacent to a conductor channel shell412of a central pillar, similar to central pillar310ofFIG.3. A hollow central region414is also shown inFIG.4. A charge storage layer404is shown located between the plurality of gates416and the conductor channel shell412. In one example, the charge storage layer404includes a nitride layer, although the invention is not so limited. In the example ofFIG.4, the charge storage layer404is separated from the plurality of gates416by a first dielectric layer402. In the example ofFIG.4, the charge storage layer404is separated from the conductor channel shell412by a second dielectric layer406. In one example, the first and/or second dielectric layers402,406include an oxide, however the invention is not so limited.

FIG.4further shows simulated data of a stored charge420that is localized adjacent to an adjacent gate416. The focused area of charge420storage is facilitated by the conductor channel shell412and the hollow central region414shown.

FIG.5shows another example of a memory string500. The memory string500includes a central pillar510including a conductor channel shell512. In the example ofFIG.5, the conductor channel shell512of the central pillar510defines a hollow central region514. The memory string500also includes a plurality of gates516along a length of the central pillar510. The example ofFIG.5shows a plurality of floating gates518that are separated from the plurality of gates516by a first gate oxide520. The plurality of floating gates518are further separated from the conductor channel shell512by a second gate oxide522.

Similar to the examples ofFIGS.3and4, in one example, the conductor channel shell512includes polysilicon, although the invention is not so limited. Other conductors such as metals, metallic compounds, or other conductively doped semiconductors are also within the scope of the invention. In one example, the hollow central region514is filled with a gas. In one example, an inert gas is used, such as nitrogen or argon. In one example, the hollow central region514is filled with air. In one example, the hollow central region514is at least partially evacuated.

In one example the hollow central region514is filled with a low dielectric constant (K) material similar to a gas or a vacuum. In one example, the hollow central region514is filled with an oxide having a K less than 10. In one example, the hollow central region514is filled with an oxide having a K less than 5. In one example, the hollow central region514is filled with an oxide having a K less than 3.

While the gate structure ofFIG.5is different than the structure of the memory string300fromFIG.3, the conductor channel shell512of memory string500being adjacent to a hollow central region514improves performance in a manner similar to the example ofFIGS.3and4discussed above.

FIG.6shows a flow diagram of an example method of forming a memory string. In operation602, a plurality of layers are formed on a semiconductor substrate, the layers including conducting layers and dielectric layers. In operation604a vertical hole is formed through at least a portion of the plurality of layers. In operation606, a central pillar is formed within the vertical hole. In operation608a first dielectric layer is formed within the vertical hole, followed by a storage layer over the first dielectric layer. In operation610, a second dielectric layer is formed over the storage layer, followed by a conducting layer wherein the conducting layer forms a conductor channel shell, the conductor channel shell having a hollow central region.

In one example, the vertical hole of operation604is formed by etching, although the invention is not so limited. Other examples include plasma removal, ablation, etc.

In one example, the hollow central region is filled with a gas. Examples of gas, include, but are not limited to, air, nitrogen, argon, or other inert gases. In one example, the hollow central region is at least partially evacuated. Although air or other gasses have a low dielectric constant near 1, a vacuum, by definition, has a dielectric constant of 1, that is lower than a gas.

FIG.7illustrates a block diagram of an example machine (e.g., a host system)700which may include one or more memory devices and/or memory systems as described above. Specifically, one or more memory devices shown inFIG.7include a memory string having a conductor channel shell and a hollow central region. As discussed above, machine700may benefit from enhanced memory performance from use of one or more of the described memory devices and/or memory systems, facilitating improved performance of machine700(as for many such machines or systems, efficient reading and writing of memory can facilitate improved performance of a processor or other components that machine, as described further below.

Examples, as described herein, may include, or may operate by, logic, components, devices, packages, or mechanisms. Circuitry is a collection (e.g., set) of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuitry membership may be flexible over time and underlying hardware variability. Circuitries include members that may, alone or in combination, perform specific tasks when operating. In an example, hardware of the circuitry may be immutably designed to carry out a specific operation (e.g., hardwired). In an example, the hardware of the circuitry may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a computer-readable medium physically modified (e.g., magnetically, electrically, moveable placement of invariant massed particles, etc.) to encode instructions of the specific operation. In connecting the physical components, the underlying electrical properties of a hardware constituent are changed, for example, from an insulator to a conductor or vice versa. The instructions enable participating hardware (e.g., the execution units or a loading mechanism) to create members of the circuitry in hardware via the variable connections to carry out portions of the specific tasks when in operation. Accordingly, the computer-readable medium is communicatively coupled to the other components of the circuitry when the device is operating. In an example, any of the physical components may be used in more than one member of more than one circuitry. For example, under operation, execution units may be used in a first circuit of a first circuitry at one point in time and reused by a second circuit in the first circuitry, or by a third circuit in a second circuitry at a different time.

The machine (e.g., computer system, a host system, etc.)700may include a processing device702(e.g., a hardware processor, a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, etc.), a main memory704(e.g., read-only memory (ROM), dynamic random-access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory706(e.g., static random-access memory (SRAM), etc.), and a storage system718, some or all of which may communicate with each other via a communication interface (e.g., a bus)730. In one example, the main memory704includes one or more memory devices as described in examples above.

The storage system718can include a machine-readable storage medium (also known as a computer-readable medium) on which is stored one or more sets of instructions726or software embodying any one or more of the methodologies or functions described herein. The instructions726can also reside, completely or at least partially, within the main memory704or within the processing device702during execution thereof by the computer system700, the main memory704and the processing device702also constituting machine-readable storage media.

The term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions, or any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media. In an example, a massed machine-readable medium comprises a machine-readable medium with multiple particles having invariant (e.g., rest) mass. Accordingly, massed machine-readable media are not transitory propagating signals. Specific examples of massed machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

The machine700may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, one or more of the display unit, the input device, or the UI navigation device may be a touch screen display. The machine a signal generation device (e.g., a speaker), or one or more sensors, such as a global positioning system (GPS) sensor, compass, accelerometer, or one or more other sensor. The machine700may include an output controller, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

The instructions726(e.g., software, programs, an operating system (OS), etc.) or other data are stored on the storage system718can be accessed by the main memory704for use by the processing device702. The main memory704(e.g., DRAM) is typically fast, but volatile, and thus a different type of storage than the storage system718(e.g., an SSD), which is suitable for long-term storage, including while in an “off” condition. The instructions726or data in use by a user or the machine700are typically loaded in the main memory704for use by the processing device702. When the main memory704is full, virtual space from the storage system718can be allocated to supplement the main memory704; however, because the storage system718device is typically slower than the main memory704, and write speeds are typically at least twice as slow as read speeds, use of virtual memory can greatly reduce user experience due to storage system latency (in contrast to the main memory704, e.g., DRAM). Further, use of the storage system718for virtual memory can greatly reduce the usable lifespan of the storage system718.

In various examples, the components, controllers, processors, units, engines, or tables described herein can include, among other things, physical circuitry or firmware stored on a physical device. As used herein, “processor” means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including a group of processors or multi-core devices.

The term “horizontal” as used in this document is defined as a plane parallel to the conventional plane or surface of a substrate, such as that underlying a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on,” “over,” and “under” are defined with respect to the conventional plane or surface being on the top or exposed surface of the substrate, regardless of the orientation of the substrate; and while “on” is intended to suggest a direct contact of one structure relative to another structure which it lies “on” (in the absence of an express indication to the contrary); the terms “over” and “under” are expressly intended to identify a relative placement of structures (or layers, features, etc.), which expressly includes—but is not limited to—direct contact between the identified structures unless specifically identified as such. Similarly, the terms “over” and “under” are not limited to horizontal orientations, as a structure may be “over” a referenced structure if it is, at some point in time, an outermost portion of the construction under discussion, even if such structure extends vertically relative to the referenced structure, rather than in a horizontal orientation.

The terms “wafer” is used herein to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. The term “substrate” is used to refer to either a wafer, or other structures which support or connect to other components, such as memory die or portions thereof. Thus, the term “substrate” embraces, for example, circuit or “PC” boards, interposers, and other organic or non-organic supporting structures (which in some cases may also contain active or passive components). The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the various embodiments is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

It will be understood that when an element is referred to as being “on,” “connected to” or “coupled with” another element, it can be directly on, connected, or coupled with the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled with” another element, there are no intervening elements or layers present. If two elements are shown in the drawings with a line connecting them, the two elements can be either be coupled, or directly coupled, unless otherwise indicated.

To better illustrate the method and apparatuses disclosed herein, a non-limiting list of embodiments is provided here:

Example 1 is a memory string. The memory string includes a central pillar, including a conductor channel shell, the conductor channel shell having a hollow central region. The memory string also includes a plurality of gates along a length of the central pillar, a source line coupled to a first end of the conductor channel shell, and a data line coupled to a second end of the conductor channel shell.

In Example 2, the memory string of Example 1 optionally includes wherein the conductor channel shell includes polysilicon.

In Example 3, the memory string of any one of Examples 1-2 optionally further includes a nitride storage layer between the plurality of gates and the conductor channel shell.

In Example 4, the memory string of any one of Examples 1-3 optionally includes wherein the hollow central region includes a gas.

In Example 5, the memory string of any one of Examples 1-4 optionally includes wherein the hollow central region includes gas at ambient pressure or higher.

In Example 6, the memory string of any one of Examples 1-5 optionally includes wherein the hollow central region includes a gas at a pressure lower than ambient pressure.

In Example 7, the memory string of any one of Examples 1-6 optionally includes wherein the plurality of gates includes metal gates.

In Example 8, the memory string of any one of Examples 1-7 optionally includes wherein the plurality of gates includes polysilicon gates.

In Example 9, the memory string of any one of Examples 1-8 optionally includes wherein the plurality of gates includes floating gates.

Example 10 is an electronic device. The electronic device includes an array of vertical memory cell strings. At least one memory cell string includes a central pillar, including a conductor channel shell, the conductor channel shell having a hollow central region. The at least one memory cell string also includes a plurality of gates along a length of the central pillar, a number of source lines coupled to first ends of conductor channel shells in the array. The at least one memory cell string also includes a number of bit lines coupled to second ends of conductor channel shells in the array, and a number of wordlines coupled to the plurality of gates in the array.

In Example 11, the electronic device of Example 10 optionally includes a processing device coupled to the array of vertical memory cell strings.

In Example 12, the electronic device of any one of Examples 10-11 optionally further includes a network interface device coupled to the array of vertical memory cell strings.

In Example 13, the electronic device of any one of Examples 10-12 optionally includes wherein the conductor channel shell includes polysilicon.

In Example 14, the electronic device of any one of Examples 10-13 optionally further includes a nitride storage layer between the plurality of gates and the conductor channel shell.

In Example 15, the electronic device of any one of Examples 10-14 optionally includes wherein the hollow central region includes a gas.

In Example 16, the electronic device of any one of Examples 10-15 optionally includes wherein the hollow central region includes gas at ambient pressure or higher.

In Example 17, the electronic device of any one of Examples 10-16 optionally includes wherein the hollow central region includes a gas at a pressure lower than ambient pressure.

Example 18 is a method of forming a memory device. The method includes forming a plurality of layers on a semiconductor substrate, the layers including conducting layers and dielectric layers, forming a vertical hole through at least a portion of the plurality of layers, forming a central pillar within the vertical hole, including forming a first dielectric layer within the vertical hole, followed by a storage layer over the first dielectric layer, and forming a second dielectric layer over the storage layer, followed by a conducting layer wherein the conducting layer forms a conductor channel shell, the conductor channel shell having a hollow central region.

Example 19 includes the method of Example 18, optionally including wherein forming the vertical hole includes etching a vertical hole.

Example 20 includes the method of any one of Examples 18-19, optionally including filling the hollow central region with a gas.

Example 21 includes the method of any one of Examples 18-20, optionally including wherein filling the hollow central region with the gas includes filling the hollow central region with nitrogen.

Example 22 includes the method of any one of Examples 18-21, optionally further including at least partially evacuating the hollow central region.