Integrated circuit packages and methods of forming the same

An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.

BACKGROUND

In recent years, the semiconductor industry has experienced rapid growth due to continuous improvement in integration density of various electronic components, e.g., transistors, diodes, resistors, capacitors, etc. For the most part, this improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area. However, the heat dissipation is a challenge in a variety of packages including more components.

DETAILED DESCRIPTION

The thermal control may protect the device in the integrated circuit packages from a thermal damage. In the disclosure, the heat dissipation efficiency is improved by adding at least one thermal via around the bonding interface between two adjacent semiconductor dies.

Herein, a “thermal” or “thermally conductive” element indicates the element is configured to conduct heat from inside a structure to outside the structure. In some embodiments, a thermal element is both thermally and electrically conductive, but merely conductive to the adjacent element rather than a device or a transistor of the structure. In other embodiments, a thermal element is merely thermally conductive.

Herein, when an element is described as being “thermally connected to” another element, it means that the element is in direct contact with or in physical contact with the another element, or that a thermally conductive element or a very thin insulator is positioned between the element and the another element.

FIG.1toFIG.6are cross-sectional views schematically illustrating a method of forming an integrated circuit package in accordance with some embodiments of the present disclosure. It is understood that the disclosure is not limited by the method described below. Additional operations can be provided before, during, and/or after the method and some of the operations described below can be replaced or eliminated, for additional embodiments of the methods. AlthoughFIG.1toFIG.6are described in relation to a method, it is appreciated that the structures disclosed inFIG.1toFIG.6are not limited to such a method, but instead may stand alone as structures independent of the method.

Referring toFIG.1toFIG.4, a semiconductor dies100(e.g., logic die, memory die, or the like) is provided. In some embodiments, the semiconductor die100includes an active side (e.g., front surface) and a non-active side (e.g., back surface) opposite to the active side. Throughout the description, the side of the semiconductor die100with die pads is referred to as an active side.

In some embodiments, as shown inFIG.1, the semiconductor die100includes a semiconductor substrate102, at least one device T1, an interconnect structure106, die pads118aand118b, and a passivation layer120.

The semiconductor substrate102may include an elementary semiconductor such as silicon, germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide. In some embodiments, the semiconductor substrate102may take the form of a planar substrate, a substrate with multiple fins, nanowires, or other forms. In some embodiments, the semiconductor die100may further include at least one through substrate via (TSV) formed in the semiconductor substrate102and electrically connected to interconnect wirings or lines of the interconnect structure106. The TSV may include Cu, Ti, Ta, W, Ru, Co, Ni, the like, an alloy thereof, or a combination thereof. In some embodiments, an insulating liner may be provided between the semiconductor substrate102and the TSV.

The device T1is disposed on/in the semiconductor substrate102and includes one or more functional devices. The functional devices may include active components, passive components, or a combination thereof. In some embodiments, the functional devices may include integrated circuits devices. The functional devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices and/or other similar devices. In some embodiments, the semiconductor die100may be referred to as a “first device die,” “first-tier semiconductor die,” or “lower integrated circuit structure.”

The interconnect structure106is formed on the semiconductor substrate102and electrically connected to the device T1. The interconnect structure106may include one or more dielectric layers, collectively referred to as a dielectric layer110, and metal features108embedded in the dielectric layer110. The metal features108are disposed in the dielectric layer110and electrically connected with each other. Portions of the metal features108, such as top metal lines, are exposed by the dielectric layer110. In some embodiments, the dielectric layer110includes an inter-layer dielectric (ILD) layer on the semiconductor substrate102, and at least one inter-metal dielectric (IMD) layer over the inter-layer dielectric layer. In some embodiments, the dielectric layer110includes silicon oxide, silicon oxynitride, silicon nitride, a low-k material having a dielectric constant less than 3.5 or 3, or a combination thereof. The dielectric layer110may be a single layer or a multiple-layer structure. In some embodiments, the metal features108include metal plugs and metal lines. The plugs may include contacts formed in the inter-layer dielectric layer, and vias formed in the inter-metal dielectric layer. The contacts are formed between and in contact with a bottom metal line and the underlying device T1. The vias are formed between and in contact with two metal lines. The metal features108may include Cu, Ti, Ta, W, Ru, Co, Ni, the like, an alloy thereof, or a combination thereof. In some embodiments, a seed layer and/or a barrier layer may be disposed between each metal feature108and the dielectric layer110to serve as a seed and/or prevent the material of the metal feature108from migrating to the underlying device T1. The seed layer includes Ti/Cu. The barrier layer includes Ta, TaN, Ti, TiN, CoW, the like, or a combination thereof, for example. In some embodiments, the interconnect structure106is formed by a dual damascene process. In other embodiments, the interconnect structure106is formed by multiple single damascene processes. In other embodiments, the interconnect structure106is formed by an electroplating process.

The die pads118aand118bare formed over the interconnect structure106. In some embodiments, the die pads118aand118bare electrically connected to the interconnect structure106and therefore the device T1. The die pads118aand118bare referred to as “active die pads” in some examples. In some embodiments, the die pads118aand118bare aluminum pads. However, the disclosure is not limited thereto. In other embodiments, the dies pads118aand118bare copper pads, nickel pads or pads made by other suitable materials. In some embodiments, some of the die pads118aand118bhave probe marks on the top surfaces thereof. The semiconductor die100may be referred to as a “known good die” after passing testing. In some embodiments, the die pads118aand118bare free of probe marks. In some embodiments, the die pads118aand118bare formed by a sputtering process, a deposition process, an electroplating process, the like, or a combination thereof.

The passivation layer120is formed over the interconnect structure106and covers the sidewalls and top surfaces of the die pads118aand118b. In some embodiments, the passivation layer120includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), the like, or a combination thereof, and is formed by a suitable process such as spin coating, CVD or the like.

Referring toFIG.2, an insulator I1is formed on the die pad118a. Specifically, the insulator I1is in physical contact with the die pad118a. In some embodiments, the insulator I1includes an insulating material or a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, a low-k material having a dielectric constant less than 3.5 or 3, or a combination thereof. In some embodiments, the method of forming the insulator I1includes forming an insulating layer over the interconnect structure106, and patterning the insulating layer with photolithography and etching steps.

Referring toFIG.3, a seed layer SL1is formed on the die pads118aand118b. In some embodiments, the seed layer SL1covers the top surfaces of the passivation layer120the die pads118aand118b, and covers the top and sidewall of the insulator I1. In some embodiments, the seed layer SL1may include Ti/Cu, and is formed by a sputtering process.

Thereafter, a photoresist layer PR1is formed on the seed layer SL1. In some embodiments, the photoresist layer PR1has openings OP11and OP12, the opening OP11corresponds to a portion of the die pad118a, and the opening OP12corresponds to the insulator IL In some embodiments, the width W11of the opening OP11is different from (e.g., greater than) the width W12of the opening OP12. However, the disclosure is not limited thereto. In other embodiments, the width W11of the opening OP11is substantially the same as or less than the width W12of the opening OP12.

Referring toFIG.4, a conductive via V11and a thermal via V12are formed in the openings OP11and OP12of the photoresist layer PR1with an electroplating process is performed by using the seed layer SL1as a seed. In some embodiments, the conductive via V11and the thermal via V12include Cu, Ti, Ta, W, Ru, Co, Ni, the like, an alloy thereof, or a combination thereof. In some embodiments, a portion of the seed layer SL1is in contact with the conductive via V11and the die pad118a, and another portion of the seed layer SL1is in contact with the thermal via V12and the insulator IL The conductive via V11and the thermal via V12are made by the same material (e.g., Cu), wherein the conductive via V11is electrically connected to the die pad118awhile the thermal via V12is electrically insulated from the die pad118a. The photoresist layer PR1and the underlying seed layer SL1are then removed.

Thereafter, a dielectric layer124is formed around the conductive via V11and the thermal via V12and the underlying insulator IL Specifically, the top surface of the dielectric layer124is level with the top surfaces of the conductive via V11and the thermal via V12. In some embodiments, the dielectric layer124includes silicon oxide, silicon nitride, silicon oxynitirde, the like, or a combination thereof. The method of forming the dielectric layer124includes forming a dielectric material over the conductive via V11and the thermal via V12, and performing a planarization process until the top surfaces of the conductive via V11and the thermal via V12are exposed.

In some embodiments, as shown in the local enlarged view A1ofFIG.4, the sidewall of the thermal via V12is slightly recessed from the sidewall of the insulator I1by a non-zero distance d. The non-zero distance d ranges from about 0.01-0.5 um, for example. However, the disclosure is not limited thereto. In some embodiments, as shown in the local enlarged view B1ofFIG.4, the sidewall of the thermal via V12is substantially aligned with the sidewall of the underlying insulator I1.

Afterwards, bonding pads BP11and BP12are formed over the conductive via V11and thermal via V12, respectively. In some embodiments, the bonding pads BP11and BP12are embedded in the bonding dielectric layer125and in contact with the conductive via V11and thermal via V12, respectively. In some embodiments, bonding pads BP13and BP14are embedded in the bonding dielectric layer125and formed aside the bonding pads BP11and BP12. The bonding pads BP11to BP14may include Cu, Ti, Ta, W, Ru, Co, Ni, the like, an alloy thereof, or a combination thereof. In some embodiments, a seed layer and/or a barrier layer may be disposed between each bonding pad and the dielectric layer125to serve as a seed and/or prevent the material of the bonding pad from migrating to the underlying device T1. The seed layer includes Ti/Cu. The barrier layer includes Ta, TaN, Ti, TiN, CoW, the like, or a combination thereof, for example. In some embodiments, the bonding pads BP11to BP14are formed by damascene processes. In other embodiments, the bonding pads BP11to BP14are formed by an electroplating process. In some embodiments, the bonding dielectric layer125includes silicon (Si), silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0) or other suitable bonding materials. The semiconductor die100is thus completed.

The bonding pad BP11is called an “active bonding pad” in some examples, because it provides electrical path between dies. The bonding pads BP12, BP13and BP14are called “dummy bonding pads” or “floating bonding pads” in some examples, because they enhance the bonding strength between dies without providing electrical paths. The bonding pad BP12is called a “thermal bonding pad” in some examples, because the bonding pad BP12enhances the heat dissipation efficiency between dies. In some embodiments, the bonding pads BP11to BP14have substantially the same size (e.g., width). However, the disclosure is not limited thereto. In other embodiments, the bonding pads BP11to BP14may have different sizes.

Referring toFIG.5, a semiconductor die200(e.g., logic die, memory die, or the like) is provided and bonded to the semiconductor die100. In some embodiments, the semiconductor die200includes an active side (e.g., front surface) and a non-active side (e.g., back surface) opposite to the active side. Throughout the description, the side of the semiconductor die200with die pads is referred to as an active side. In some embodiments, the second semiconductor die200has a structure similar to that of the first semiconductor die100, so the difference between them is illustrated below, and the similarity is not iterated herein.

In some embodiments, the semiconductor die200includes a semiconductor substrate202, at least one device T2, an interconnect structure206, die pads218aand218b, and a passivation layer220.

The semiconductor substrate202may include an elementary semiconductor such as silicon, germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide. In some embodiments, the semiconductor substrate202may take the form of a planar substrate, a substrate with multiple fins, nanowires, or other forms. In some embodiments, the semiconductor die200may further include at least one through substrate via (TSV)203formed in the semiconductor substrate202and electrically connected to interconnect wirings or lines of the interconnect structure206. As illustrated inFIG.6, the at least one TSV203is embedded in the semiconductor substrate202, and the TSV203is not revealed from the back surface of the semiconductor substrate202at this stage. The TSV may include Cu, Ti, Ta, W, Ru, Co, Ni, the like, an alloy thereof, or a combination thereof. In some embodiments, an insulating liner may be provided between the semiconductor substrate202and the TSV203.

The device T2is disposed on/in the semiconductor substrate202and includes one or more functional devices. The functional devices may include active components, passive components, or a combination thereof. In some embodiments, the functional devices may include integrated circuits devices. The functional devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices and/or other similar devices. In some embodiments, the semiconductor die200may be referred to as a “second device die,” “second-tier semiconductor die,” or “upper integrated circuit structure.”

The interconnect structure206is formed on the semiconductor substrate202and electrically connected to the device T2. The interconnect structure206may include one or more dielectric layers, collectively referred to as a dielectric layer210, and metal features208embedded in the dielectric layer210. The metal features208are disposed in the dielectric layer210and electrically connected with each other. Portions of the metal features208, such as top metal lines, are exposed by the dielectric layer210. In some embodiments, the dielectric layer210includes an inter-layer dielectric (ILD) layer on the semiconductor substrate202, and at least one inter-metal dielectric (IMD) layer over the inter-layer dielectric layer. In some embodiments, the dielectric layer210includes silicon oxide, silicon oxynitride, silicon nitride, a low-k material having a dielectric constant less than 3.5 or 3, or a combination thereof. The dielectric layer210may be a single layer or a multiple-layer structure. In some embodiments, the metal features208include metal plugs and metal lines. The plugs may include contacts formed in the inter-layer dielectric layer, and vias formed in the inter-metal dielectric layer. The contacts are formed between and in contact with a bottom metal line and the underlying device T2. The vias are formed between and in contact with two metal lines. The metal features208may include Cu, Ti, Ta, W, Ru, Co, Ni, the like, an alloy thereof, or a combination thereof. In some embodiments, a barrier layer may be disposed between each metal feature208and the dielectric layer210to prevent the material of the metal feature108from migrating to the underlying device T2. The barrier layer includes Ta, TaN, Ti, TiN, Co W, the like, or a combination thereof, for example. In some embodiments, the interconnect structure206is formed by a dual damascene process. In other embodiments, the interconnect structure206is formed by multiple single damascene processes. In other embodiments, the interconnect structure206is formed by an electroplating process.

The die pads218aand218bare formed over the interconnect structure106. In some embodiments, the die pads218aand218bare electrically connected to the interconnect structure206and therefore the device T2. In some embodiments, the die pads218aand218bare aluminum pads. However, the disclosure is not limited thereto. In other embodiments, the dies pads218aand218bare copper pads, nickel pads or pads made by other suitable materials. In some embodiments, some of the die pads218aand218bhave probe marks on the top surfaces thereof. The semiconductor die200may be referred to as a “known good die” after passing testing. In some embodiments, the die pads218aand218bare free of probe marks. In some embodiments, the die pads218aand218bare formed by a sputtering process, a deposition process, an electroplating process, the like, or a combination thereof.

The passivation layer220is formed over the interconnect structure206and covers the sidewalls and top surfaces of the die pads218aand218b. In some embodiments, the passivation layer220includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO), the like, or a combination thereof, and is formed by a suitable process such as spin coating, CVD or the like.

Thereafter, an insulator12is formed on the die pad218a. Specifically, the insulator12is in physical contact with the die pad218a. In some embodiments, the insulator12includes an insulating material or a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, a low-k material having a dielectric constant less than 3.5 or 3, or a combination thereof. In some embodiments, the method of forming the insulator12includes forming an insulating material over the passivation layer220and the die pads218aand218b, and patterning the insulating material with photolithography and etching steps.

Afterwards, a seed layer SL2, a conductive via V21and a thermal via V22are formed over the die pad218a. A portion of the seed layer SL2is formed between the conductive via V21and the die pad218a, and a portion of the seed layer SL2is formed between the thermal via V22and the insulator12. The materials and forming methods of the seed layer SL2, the conductive via V21and the thermal via V22are similar to those of the seed layer SL1, the conductive via V21and the thermal via V22described above, so the details are not iterated herein.

Thereafter, a dielectric layer224is formed around the conductive via V21and the thermal via V22and the underlying insulator12. In some embodiments, the dielectric layer224includes silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof. The method of forming the dielectric layer224includes forming a dielectric material over the conductive via V21and the thermal via V22, and performing a planarization process until the top surfaces of the conductive via V21and the thermal via V22are exposed.

In some embodiments, as shown in the local enlarged view A2ofFIG.5, the sidewall of the thermal via V22is slightly recessed from the sidewall of the underlying insulator12by a non-zero distance d. The non-zero distance d ranges from about 0.01-0.5 um, for example. However, the disclosure is not limited thereto. In some embodiments, as shown in the local enlarged view B2ofFIG.5, the sidewall of the overlying thermal via V22is substantially level with the sidewall of the underlying insulator12.

Afterwards, bonding pads BP21and BP22are formed over the conductive via V21and thermal via V22, respectively. In some embodiments, the bonding pads BP21and BP22are embedded in the bonding dielectric layer225and in contact with the conductive via V21and thermal via V22, respectively. In some embodiments, bonding pads BP23and BP24are embedded in the bonding dielectric layer225and formed aside the bonding pads BP21and BP22.

The bonding pads BP21to BP24may include Cu, Ti, Ta, W, Ru, Co, Ni, the like, an alloy thereof, or a combination thereof. In some embodiments, a seed layer and/or a barrier layer may be disposed between each bonding pad and the dielectric layer225to serve as a seed and/or prevent the material of the bonding pad from migrating to the underlying device T2. The seed layer includes Ti/Cu. The barrier layer includes Ta, TaN, Ti, TiN, CoW, the like, or a combination thereof, for example. In some embodiments, the bonding pads BP21to BP24are formed by damascene processes. In other embodiments, the bonding pads BP21to BP24are formed by an electroplating process. In some embodiments, the bonding dielectric layer225includes silicon (Si), silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0) or other suitable bonding materials. The semiconductor die200is thus completed.

The bonding pad BP21is called an “active bonding pad” in some examples, because it provides electrical path between dies. The bonding pads BP22, BP23and BP24are called “dummy bonding pads” or “floating bonding pads” in some examples, because they enhance the bonding strength between dies without providing electrical paths. The bonding pad BP22is called a “thermal bonding pad” in some examples, because the bonding pad BP22enhances the heat dissipation efficiency between dies. In some embodiments, the bonding pads BP21to BP24have substantially the same size (e.g., width). However, the disclosure is not limited thereto. In other embodiments, the bonding pads BP11to BP14may have different sizes.

Still referring toFIG.5, the semiconductor die200is turned over and then bonded to the semiconductor die100. In some embodiments, the semiconductor die200and the semiconductor die100are bonded in a face-to-face alignment, wherein the front side or active side of the semiconductor die200faces the front side or active side of the semiconductor die100. Specifically, the bonding pads BP21to BP24of the semiconductor die200are aligned and in physical contact with the corresponding bonding pads BP11to BP14of the semiconductor die100, and the bonding dielectric layer225of the semiconductor die200is aligned and in physical contact with the corresponding bonding dielectric layer125of the semiconductor die100. In some embodiments, the dimension of the bonding pads BP21to BP24is the same as that of the bonding pads BP11to BP14. In other embodiments, the dimension of one or more of the bonding pads BP21to BP24is different from that of the bonding pads BP11to BP14. The semiconductor die200and the semiconductor die100are heated and/or pressed to enable a metal-to-metal bonding (e.g., copper-to-copper bonding) and a dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding). Such bonding is called a “hybrid bonding”.

Referring toFIG.6, the semiconductor die200is thinned to expose an upper portion of the TSV203of the semiconductor die200. In some embodiments, the semiconductor substrate202is thinned from the backside and a portion of the semiconductor substrate202is removed through a suitable grinding process and/or a polishing process such as chemical mechanical polishing (CMP) or the like to reveal the upper portion of the TSV203.

Thereafter, an isolation layer222is formed over the semiconductor die200, covers the backside of the semiconductor die200and aside the exposed portion of the TSV203. The isolation layer222includes silicon oxide, silicon nitride, silicon oxynitride or a combination thereof and is formed by a suitable process such as CVD.

Afterwards, a backside metal feature223is formed over and electrically connected to the TSV203. The backside metal feature223includes redistribution layer (RDL) lines and/or pads embedded in a passivation layer226. An under bump metallization (UBM) layer228is formed over the backside metal feature223, and a bump is formed or mounted over the UBM layer228. In some embodiments, the bump is electrically connected to the TSV203through the backside metal feature223. In some embodiments, the UBM layer228is made of Ti, TiN, Ta, TaN, or the like and formed by a suitable process such as CVD. In some embodiments, the bump is made of a conductive material with low resistivity, such as Sn, Pb, Ag, Cu, Ni, Bi or an alloy thereof, and formed by a suitable process such as evaporation, plating, ball drop, or screen printing. In some embodiments, the bump includes a lower portion230(e.g., Cu pillar) and an upper portion232(e.g., solder ball) made by different materials. An integrated circuit package1a-1is thus completed.

In the integrated circuit package1a-1, the thermal control performance is improved by adding thermal vias V12and V22around the bonding interface between two adjacent semiconductor dies100and200, respectively. Specifically, each of the thermal vias V12and V22is thermally conductive to the bonding pads BP12and BP22, but electrically insulated from the device T1and the device T2by inserting the insulators I1and12to block the electrical paths. In this embodiment, the bonding pads BP12and BP22are called “thermal bonding pads”. The thermal resistance of SoIC bond is significantly reduced by adding the thermal vias and/or thermal bonding pads of the disclosure.

Thermal vias with various configurations are contemplated as falling within the spirit and scope of the present disclosure, as long as such thermal vias provide thermal paths but block conductive paths.

FIG.7toFIG.10are cross-sectional views schematically illustrating a method of forming an integrated circuit package in accordance with some embodiments of the present disclosure. It is understood that the disclosure is not limited by the method described below. Additional operations can be provided before, during, and/or after the method and some of the operations described below can be replaced or eliminated, for additional embodiments of the methods. AlthoughFIG.7toFIG.10are described in relation to a method, it is appreciated that the structures disclosed inFIG.7toFIG.10are not limited to such a method, but instead may stand alone as structures independent of the method.

The integrated circuit package1a-2ofFIG.10is similar to the integrated circuit package1a-1ofFIG.6, wherein like reference numerals refer to like elements. The materials, configurations and forming methods of elements ofFIG.7toFIG.10may refer to those of similar elements described in the previous embodiments. The integrated circuit package1a-2ofFIG.10may be beneficial for process flexibility.

Referring toFIG.7toFIG.9, a semiconductor dies100(e.g., logic die, memory die, or the like) is provided. In some embodiments, as shown inFIG.7, the semiconductor die100includes a semiconductor substrate102, at least one device T1, an interconnect structure106, die pads118aand118b, and a passivation layer120.

Thereafter, as shown inFIG.8, a photoresist layer PR1is formed on the passivation layer120. In some embodiments, the photoresist layer PR1has openings OP11and OP12, the opening OP11corresponds to a portion of the die pad118a, and the opening OP12corresponds to another portion of the die pad118a. In some embodiments, the width W11of the opening OP11is different from (e.g., less than) the width W12of the opening OP12. However, the disclosure is not limited thereto. In other embodiments, the width W11of the opening OP11is substantially the same as the width W12of the opening OP12.

Referring toFIG.9, a conductive via V11and a thermal via V12are formed in the openings OP11and OP12of the photoresist layer PR1with an electroplating process by using the die pad118aas a seed. In some embodiments, the conductive via V11and the thermal via V12include Cu, Ti, Ta, W, Ru, Co, Ni, the like, an alloy thereof, or a combination thereof. The conductive via V11and the thermal via V12are made by the same material (e.g., Cu), wherein the conductive via V11and the thermal via V12are electrically connected to the die pad118a. In some embodiments, since the width W11of the opening OP11is less than the width W12of the opening OP12, the conductive via V11is formed higher than the thermal via V12during the same electroplating process. The photoresist layer PR1is then removed.

Thereafter, a dielectric layer124is formed around the conductive via V11and the thermal via V12. Specifically, the top surface of the dielectric layer124is level with the top surface of the conductive via V11but higher than the top surface of the thermal via V12. Specifically, the dielectric layer124covers the top surface and the sidewall of the thermal via V12. From another point of view, the portion of the dielectric layer124above the thermal via V22is regarded as an insulator I1′ in some examples.

In some embodiments, the dielectric layer124includes silicon oxide, silicon nitride, silicon oxynitirde, the like, or a combination thereof. The method of forming the dielectric layer124includes forming a dielectric material over the conductive via V11and the thermal via V12, and performing a planarization process until the top surface of the conductive via V11is exposed.

In some embodiments, as shown in the local enlarged view A1ofFIG.9, the insulator I1′ marked by dotted line is part of the dielectric layer124, so an interface is not present between the insulator I1′ and the dielectric layer124. The insulator I1′ and the dielectric layer124of the local enlarged view A1are made by the same material. However, the disclosure is not limited thereto. In some embodiments, as shown in the local enlarged view B1ofFIG.9, a patterning process (including, for example, a deposition step followed by photolithography and etching steps) may be performed to provide an insulator I1′ over the thermal via V12, so a visible interface is present between the insulator I1′ and the dielectric layer124. The insulator I1′ and the dielectric layer124of the local enlarged view B1are made by the same material or different materials.

Afterwards, bonding pads BP11and BP12are formed over the conductive via V11and thermal via V12, respectively. In some embodiments, the bonding pads BP11and BP12are embedded in the bonding dielectric layer125and in contact with the conductive via V11and the insulator I′, respectively. Specifically, the insulator I1′ is disposed between and in contact with the bonding pad BP11and the conductive via V11. In some embodiments, bonding pads BP13and BP14are embedded in the bonding dielectric layer125and formed aside the bonding pads BP11and BP12. The bonding pads BP11to BP14may include Cu, Ti, Ta, W, Ru, Co, Ni, the like, an alloy thereof, or a combination thereof. In some embodiments, a seed layer and/or a barrier layer may be disposed between each bonding pad and the dielectric layer125to serve as a seed and/or prevent the material of the bonding pad from migrating to the underlying device T1. The seed layer includes Ti/Cu. The barrier layer includes Ta, TaN, Ti, TiN, CoW, the like, or a combination thereof, for example. In some embodiments, the seed layer and/or the barrier layer is disposed between and in physical contact with the insulator I′ and the bonding pad BP11. In some embodiments, the bonding dielectric layer125includes silicon (Si), silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0) or other suitable bonding materials. The semiconductor die100is thus completed.

The bonding pads BP12, BP13and BP14are referred to “dummy bonding pads” or “floating bonding pads” in some examples because they enhance the bonding strength between dies. The bonding pad BP12is called a “thermal bonding pad” in some examples, because the bonding pad BP12enhances the heat dissipation efficiency between dies. In some embodiments, the bonding pads BP11to BP14have substantially the same size (e.g., width), as shown inFIG.4. However, the disclosure is not limited thereto. In other embodiments, the bonding pads BP11to BP14may have different sizes.

Referring toFIG.10, a semiconductor die200(e.g., logic die, memory die, or the like) is provided and bonded to the semiconductor die100. In some embodiments, the semiconductor die200has a structure similar to that of the semiconductor die100, so the details are not iterated herein. An integrated circuit package1a-2is thus completed.

In the integrated circuit package1a-2, the thermal control performance is improved by adding thermal vias V12and V22around the bonding interface between two adjacent semiconductor dies100and200, respectively. Specifically, each of the thermal vias V12and V22is thermally conductive to the die pads118aand218a, but electrically insulated from the device T1and the device T2by inserting the insulators I1′ and12′ to block the electrical paths. In this embodiment, the bonding pads BP12and BP22are called “thermal bonding pads” although the thermal vias V12and V22are not in physical contact with the bonding pads BP12and BP22. Specifically, the insulator I1′/I2′ is so thin such that the heat dissipation is not affected much by the thin insulator I1′/I2′ between the thermal via V12/V22and thermal pad BP12/BP22. For example, the thickness of the insulator I1′/I2′ is about 1/10- 1/50 of the thickness of the thermal via V12/V22. The thermal resistance of SoIC bond is significantly reduced by adding the thermal vias and/or thermal bonding pads of the disclosure.

The above embodiments in which the thermal vias and/or thermal bonding pads are provided in both of the facing semiconductor dies are provided for illustration purposes, and are not to be construed as limiting the present disclosure. In some embodiments, the thermal vias and/or thermal bonding pads are provided in one of the facing semiconductor dies. Besides, the thermal vias may have other configurations as long as they provide thermal paths around the bonding interface of the dies.

FIG.11toFIG.20are cross-sectional views schematically illustrating integrated circuit packages in accordance with some embodiments of the present disclosure. The integrated circuit packages1a-3to1a-12ofFIG.11toFIG.20are similar to the integrated circuit packages1a-1to1a-2ofFIG.6andFIG.10, wherein like reference numerals refer to like elements. The materials, configurations and forming methods of elements ofFIG.11toFIG.20may refer to those of similar elements described in the previous embodiments. The integrated circuit packages ofFIG.11toFIG.20may be beneficial for product flexibility.

The integrated circuit package1a-3ofFIG.11is similar to the integrated circuit packages1a-1ofFIG.6, and the difference between them lies in that, in the integrated circuit package1a-3ofFIG.11, the thermal via V22and the insulator12are omitted from the semiconductor die200facing the ball array.

The integrated circuit package1a-4ofFIG.12is similar to the integrated circuit package1a-2ofFIG.10, and the difference between them lies in that, in the integrated circuit package1a-4ofFIG.12, the thermal via V22and the insulator12′ are omitted from the semiconductor die200facing the ball array.

The integrated circuit packages1a-5ofFIG.13is similar to the integrated circuit package1a-1ofFIG.6, and the difference between them lies in that, in the integrated circuit package1a-5ofFIG.13, the thermal via V22and the insulator12are omitted from the semiconductor die200facing the ball array, and the insulator I1is omitted from the semiconductor die100facing away from the ball array. In this embodiment, the thermal via V12is in physical contact with the bonding pad BP12and the die pad118abut electrically insulated from the device T2.

The integrated circuit package1a-6ofFIG.14is similar to the integrated circuit package1a-1ofFIG.6, and the difference between them lies in that, in the integrated circuit package1a-6ofFIG.14, the thermal via V12and the insulator I1are omitted from the semiconductor die100facing away from the ball array.

The integrated circuit package1a-7ofFIG.15is similar to the integrated circuit package1a-2ofFIG.10, and the difference between them lies in that, in the integrated circuit package1a-7ofFIG.15, the thermal via V12and the insulator I1′ are omitted from the semiconductor die100facing away from the ball array.

The integrated circuit packages1a-8ofFIG.16is similar to the integrated circuit package1a-1ofFIG.6, and the difference between them lies in that, in the integrated circuit package1a-8ofFIG.16, the thermal via V12and the insulator I1are omitted from the semiconductor die100facing away from the ball array, and the insulator12is omitted from the semiconductor die200facing the ball array. In this embodiment, the thermal via V22is in physical contact with the bonding pad BP22and the die pad218abut electrically insulated from the device T1.

The integrated circuit package1a-9ofFIG.17is similar to the integrated circuit packages1a-1ofFIG.6, and the difference between them lies in that, in the integrated circuit package1a-9ofFIG.17, the insulator12is omitted from the semiconductor die200facing the ball array. In this embodiment, the thermal via V22is in physical contact with the bonding pad BP22and the die pad218abut electrically insulated from the device T1.

The integrated circuit package1a-10ofFIG.18is similar to the integrated circuit packages1a-2ofFIG.10, and the difference between them lies in that, in the integrated circuit package1a-10ofFIG.18, the insulator12′ is omitted from the semiconductor die200facing the ball array. In this embodiment, the thermal via V22is in physical contact with the bonding pad BP22and the die pad218abut electrically insulated from the device T1.

The integrated circuit package1a-11ofFIG.19is similar to the integrated circuit packages1a-1ofFIG.6, and the difference between them lies in that, in the integrated circuit package1a-9ofFIG.17, the insulator I1is omitted from the semiconductor die100facing away from the ball array. In this embodiment, the thermal via V12is in physical contact with the bonding pad BP12and the die pad118abut electrically insulated from the device T2.

The integrated circuit package1a-12ofFIG.20is similar to the integrated circuit packages1a-2ofFIG.10, and the difference between them lies in that, in the integrated circuit package1a-12ofFIG.20, the insulator I1′ is omitted from the semiconductor die100facing away from the ball array. In this embodiment, the thermal via V12is in physical contact with the bonding pad BP2and the die pad118abut electrically insulated from the device T2.

FIG.21toFIG.32are cross-sectional views schematically illustrating integrated circuit packages in accordance with some embodiments of the present disclosure. The integrated circuit packages1b-1to1b-12ofFIG.21toFIG.32are similar to the integrated circuit packages1a-1to1a-12ofFIG.6andFIG.10toFIG.20, wherein like reference numerals refer to like elements. The materials, configurations and forming methods of elements ofFIG.21toFIG.32may refer to those of similar elements described in the previous embodiments. The integrated circuit packages ofFIG.21toFIG.32may be beneficial for product flexibility.

The integrated circuit packages1b-1to1b-12ofFIG.21toFIG.32are similar to the integrated circuit packages1a-1to1a-12ofFIG.6andFIG.10toFIG.20, and the difference lies in that, inFIG.21toFIG.32, the thermal via V12and the conductive V11are landed on different die pads118band118a, and the thermal via V22and the conductive V21are landed on different die pads218band218a. The die pads118band118aare active die pads electrically connected to the device T1, and the die pads218band218aare active die pads electrically connected to the device T2. Due to the location shift, the thermal via V12is located between the die pad118band the bonding pad BP13, and the thermal via V22is located between the die pad218band the bonding pad BP23. In these embodiments, the bonding pads BP13and BP23are called “thermal pads”, and the bonding pads BP12, BP22, BP14and BP24are called “dummy bonding pads”.

FIG.33toFIG.44are cross-sectional views schematically illustrating integrated circuit packages in accordance with some embodiments of the present disclosure. The integrated circuit packages1c-1to1c-12ofFIG.33toFIG.44are similar to the integrated circuit packages1a-1to1a-12ofFIG.6andFIG.10toFIG.20, wherein like reference numerals refer to like elements. The materials, configurations and forming methods of elements ofFIG.33toFIG.44may refer to those of similar elements described in the previous embodiments. The integrated circuit packages ofFIG.33toFIG.44may be beneficial for product flexibility.

The integrated circuit packages1c-1to1c-12ofFIG.33toFIG.44are similar to the integrated circuit packages1a-1to1a-12ofFIG.6andFIG.10toFIG.20, and the difference lies in that, inFIG.33toFIG.44, the thermal via V12and the conductive V11are landed on different die pads118cand118a, and the thermal via V22and the conductive V21are landed on different die pads218cand218a. The die pad118ais an active die pad electrically connected to the device T1, but the die pad118cis a dummy die pad electrically insulated from the device T1. The die pad218ais an active die pad electrically connected to the device T2, but the die pad218cis a dummy die pad electrically insulated from the device T2. Due to the location shift, the thermal via V12is located between the die pad118cand the bonding pad BP14, and the thermal via V22is located between the die pad218cand the bonding pad BP24. In these embodiments, the bonding pads BP14and BP24are called “thermal pads”, and the bonding pads BP12, BP22, BP13and BP23are called “dummy bonding pads”.

FIG.45illustrates an integrated circuit package1d-1including combinations of the previous embodiments. Specifically, the dummy via V12/V22between the bonding pad BP12/BP22and the die pad118a/218acan refer to one of configurations as shown inFIG.6,FIG.10toFIG.20, the dummy via V12/V22between the bonding pad BP13/BP23and the die pad118b/218bcan refer to one of configurations as shown in

FIG.21toFIG.32, and the dummy via V12/V22between the bonding pad BP14/BP24and the die pad118c/218ccan refer to one of configurations as shown inFIG.33toFIG.44. Several configurations are provided below for illustration purposes, but the disclosure is not limited to.

For example, in the integrated circuit package1d-2ofFIG.46, three bonding vias V12and three bonding vias V22are disposed around the bonding interface between two adjacent semiconductor dies100and200, and the bonding vias V12correspond to the bonding vias V22, respectively. Specifically, each of the thermal vias V12and V22is thermally conductive to the bonding pads BP12/BP13/BP14and BP22/BP23/BP24, but electrically insulated from the device T1and the device T2by inserting the insulators I1and12to block the electrical paths. In this embodiment, the bonding pads BP12/BP13/BP14and BP22/BP23/BP24are called “thermal bonding pads”. The thermal resistance of SoIC bond is significantly reduced by adding the thermal vias and/or thermal bonding pads of the disclosure.

For example, in the integrated circuit package1d-3ofFIG.47, two bonding vias V12and one bonding via V22are disposed around the bonding interface between two adjacent semiconductor dies100and200, and the bonding vias V12are misaligned with the thermal via V22. Specifically, the bonding via V22is disposed between the bonding vias V12. In other embodiments, when multiple bonding vias V22and multiple bonding vias V12are provided around the bonding interface, the bonding vias V22and the bonding vias V21may be arranged alternately. In this embodiments, each thermal via V12is thermally conductive to the die pads118a/118c, but electrically insulated from the device T1and the device T2by inserting the insulators I1′ to block the electrical paths. Besides, the thermal via V22is thermally conductive to the die pads218b, but electrically insulated from the device T1and the device T2by inserting the insulators12′ to block the conductive paths. In this embodiment, the bonding pads BP12/BP13/BP14and BP22/BP23/BP24are called “thermal bonding pads”. The thermal resistance of SoIC bond is significantly reduced by adding the thermal vias and/or thermal bonding pads of the disclosure.

For example, in the integrated circuit package1d-4ofFIG.48, two bonding vias V12and two bonding vias V22are disposed around the bonding interface between two adjacent semiconductor dies100and200. In this embodiments, each thermal via V12is thermally conductive to the die pads118a/118c, but electrically insulated from the device T1and the device T2by inserting the insulators I1′ to block the electrical paths. Besides, one of the thermal via V22is thermally conductive to the active die pad218bbut electrically insulated from the device T1, and another of the thermal vias V22is thermally conductive to the dummy die pad218cbut electrically insulated from the device T1and the device T2. In this embodiment, the bonding pads BP12/BP13/BP14and BP22/BP23/BP24are called “thermal bonding pads”. The thermal resistance of SoIC bond is significantly reduced by adding the thermal vias and/or thermal bonding pads of the disclosure.

The above embodiments ofFIG.46toFIG.48in which thermal vias are provided within both of the facing semiconductor dies are provided for illustration purposes, and are not construed as limiting the present disclosure. In other embodiments, upon the design requirements (e.g., shorter cycle time or cost reduction), the thermal vias may be provided in only one of the facing semiconductor dies.

In the above embodiments, the semiconductor die200and the semiconductor die100are bonded in a face-to-face alignment with a hybrid bonding. However, the disclosure is not limited thereto. In other embodiments, the semiconductor die200and the semiconductor die100are bonded in a face-to-back alignment or a back-to-back alignment with a hybrid bonding, a fusion bonding, a eutectic bonding or an adhesive bonding upon the actual requirements. Several configurations are provided below for illustration purposes, but the disclosure is not limited to.

FIG.49is a cross-sectional view schematically illustrating an integrated circuit packages in accordance with other embodiments of the present disclosure. The integrated circuit packages2a-1ofFIG.49is similar to the integrated circuit packages1d-1ofFIG.45, wherein like reference numerals refer to like elements.

The integrated circuit packages2a-1ofFIG.49is similar to the integrated circuit packages1d-1ofFIG.45, and the difference lies in that, in the integrated circuit packages2a-1ofFIG.49, the semiconductor die200and the semiconductor die100are bonded in a face-to-back alignment, rather than the face-to-face alignment of the integrated circuit package2d-1. The materials, configurations and forming methods of elements ofFIG.49may refer to those of similar elements described in the previous embodiments. The integrated circuit package ofFIG.49may be beneficial for product flexibility.

Referring toFIG.49, a semiconductor die100is provided. In some embodiments, the semiconductor device100may be formed with operations similar to those described inFIG.1toFIG.4orFIG.7toFIG.9. In some embodiments, the semiconductor device100includes a first interconnect structure106, first die pads118a/118b/118c, first thermal vias V12, and first bonding pads BP11/BP12/BP13/BP14sequentially formed on a front side of a first semiconductor substrate102.

Thereafter, a semiconductor device200is provided. In some embodiments, the semiconductor device200includes a second interconnect structure206, second die pads218a/218b/218c, and a passivation layer226sequentially formed on a front side of a second semiconductor substrate202. The second semiconductor substrate200has at least one through substrate via (TSV)203formed therein.

The semiconductor substrate200may be thinned to expose the upper portion of the TSV203, and the isolation layer222is formed aside the upper portion of the TSV203.

Afterwards, second thermal vias V22and second bonding pads BP21/BP22/BP23/BP24are sequentially formed on a backside of the second semiconductor substrate202.

The bump including a lower portion230(e.g., Cu pillar) and an upper portion232(e.g., solder ball) is then formed through the passivation layer226and electrically connected to the die pad218a.

The integrated circuit package2a-1ofFIG.49includes combinations of the previous embodiments. Specifically, the dummy via V12/V22between the bonding pad BP12/BP22and the die pad118a/218acan refer to one of configurations as shown inFIG.6,FIG.10toFIG.20, the dummy via V12/V22between the bonding pad BP13/BP23and the die pad118b/218bcan refer to one of configurations as shown inFIG.21toFIG.32, and the dummy via V12/V22between the bonding pad BP14/BP24and the die pad118c/218ccan refer to one of configurations as shown inFIG.33toFIG.44. Several configurations are provided below for illustration purposes, but the disclosure is not limited to.

For example, in the integrated circuit package2a-2ofFIG.50, three bonding vias V12and three bonding vias V22are disposed around the bonding interface between two adjacent semiconductor dies100and200, and the bonding vias V12correspond to the bonding vias V22, respectively. Specifically, each of the thermal vias V12and V22is thermally conductive to the bonding pads BP12/BP13/BP14and BP22/BP23/BP24, but electrically insulated from the device T1and the device T2by inserting the insulators I1and12to block the electrical paths. In some embodiments, upon the process requirements, dummy TSVs may be provided within the semiconductor substrate202and correspond to the thermal vias V22, so as to improve the heat dissipation efficiency. In this embodiment, the bonding pads BP12/BP13/BP14and BP22/BP23/BP24are called “thermal bonding pads”. The thermal resistance of SoIC bond is significantly reduced by adding the thermal vias and/or thermal bonding pads of the disclosure.

For example, in the integrated circuit package2a-3ofFIG.51, two bonding vias V12and one bonding via V22are disposed around the bonding interface between two adjacent semiconductor dies100and200, and the bonding vias V12are misaligned with the thermal via V22. Specifically, the bonding via V22is disposed between the bonding vias V12. In other embodiments, when multiple bonding vias V22and multiple bonding vias V12are provided around the bonding interface, the bonding vias V22and the bonding vias V21may be arranged alternately. In some embodiments, upon the process requirements, dummy TSVs may be provided within the semiconductor substrate202and correspond to the thermal vias V22, so as to improve the heat dissipation efficiency. In this embodiments, each thermal via V12is thermally conductive to the die pads118a/118c, but electrically insulated from the device T1and the device T2by inserting the insulators I1′ to block the electrical paths. Besides, the thermal via V12is thermally conductive to the die pads118b, but electrically insulated from the device T1and the device T2by inserting the insulators12′ to block the conductive path. In this embodiment, the bonding pads BP12/BP13/BP14and BP22/BP23/BP24are called “thermal bonding pads”. The thermal resistance of SoIC bond is significantly reduced by adding the thermal vias and/or thermal bonding pads of the disclosure.

For example, in the integrated circuit package2a-4ofFIG.52, two bonding vias V12and two bonding vias V22are disposed around the bonding interface between two adjacent semiconductor dies100and200. In this embodiments, each thermal via V12is thermally conductive to the die pads118a/118c, but electrically insulated from the device T1and the device T2by inserting the insulators I1′ to block the electrical paths. Besides, one of the thermal via V22is thermally conductive to the active die pad218bbut electrically insulated from the device T1, and another of the thermal vias V22is thermally conductive to the dummy die pad218cbut electrically insulated from the device T1and the device T2. In some embodiments, upon the process requirements, dummy TSVs may be provided within the semiconductor substrate202and correspond to the thermal vias V22, so as to improve the heat dissipation efficiency. In this embodiment, the bonding pads BP12/BP13/BP14and BP22/BP23/BP24are called “thermal bonding pads”. The thermal resistance of SoIC bond is significantly reduced by adding the thermal vias and/or thermal bonding pads of the disclosure.

The above embodiments ofFIG.50toFIG.52in which thermal vias are provided within both of the facing semiconductor dies are provided for illustration purposes, and are not construed as limiting the present disclosure. In other embodiments, upon the design requirements (e.g., shorter cycle time or cost reduction), the thermal vias may be provided in only one of the facing semiconductor dies.

The structures of the integrated circuit packages of the disclosure are illustrated below with reference to the previous figures.

In some embodiments, an integrated circuit package (e.g.,1a-1to1a-12,1b-1to1b-12,1c-1to1c-12,1d-1to1d-4,2a-1to2a-4) includes a first semiconductor die (e.g.,100) and a second semiconductor die (e.g.,200) bonded to each other. The first semiconductor die includes a plurality of first die pads (e.g.,118ato118c) over a first device (e.g., T1) and a plurality of first bonding pads (e.g., BP11to BP14) over the first die pads.

In some embodiments, in the integrated circuit package (e.g.,1a-1,1a-3,1a-9), a first conductive via (e.g., V11) is disposed between and electrically connected to a first one (e.g., right side of118a) of the first die pads and a first one (e.g., BP11) of the first bonding pads, and a first thermal via (e.g., V12) is disposed between a second one (e.g., left side of118a) of the first die pads and a second one (e.g., BP12) of the first bonding pads and electrically insulated from the second one of the first die pads. In some embodiments, the second one (e.g., left side of118a) of the first die pads is an active die pad electrically connected to the first device (e.g., T1). In some embodiments, the first one (e.g., right side of118a) of the first die pads is connected to the second one (e.g., left side of118a) of the first die pads. In some embodiments, the first semiconductor die further includes a first insulator (e.g., I1) between the first thermal via (e.g., V11) and the second one (e.g., left side of118a) of the first die pads. Besides, the second semiconductor die (e.g.,200) includes a plurality of second bonding pads (e.g., BP21to BP24), wherein the first one (e.g., BP11) of the first bonding pads is connected to a first one (e.g., BP21) of the second bonding pads, and the second one (e.g., BP12) of the first bonding pads is connected to a second one (e.g., BP22) of the second bonding pads.

In some embodiments, in the integrated circuit package (e.g.,1b-1,1b-3,1b-9), a first conductive via (e.g., V11) is disposed between and electrically connected to a first one (e.g.,118a) of the first die pads and a first one (e.g., BP11) of the first bonding pads, and a first thermal via (e.g., V12) is disposed between a second one (e.g.,118b) of the first die pads and a second one (e.g., BP13) of the first bonding pads and electrically insulated from the second one of the first die pads. In some embodiments, the second one (e.g.,118b) of the first die pads is an active die pad electrically connected to the first device (e.g., T1). In some embodiments, the second one (e.g.,118b) of the first die pads is an active die pad electrically connected to the first device (e.g., T1). In some embodiments, the first one (e.g.,118a) of the first die pads is separated from the second one (e.g.,118b) of the first die pads. In some embodiments, the first semiconductor die further includes a first insulator (e.g., I1) between the first thermal via (e.g., V11) and the second one (e.g., left side of118a) of the first die pads. Besides, the second semiconductor die (e.g.,200) includes a plurality of second bonding pads (e.g., BP21to BP24), wherein the first one (e.g., BP11) of the first bonding pads is connected to a first one (e.g., BP21) of the second bonding pads, and the second one (e.g., BP13) of the first bonding pads is connected to a second one (e.g., BP23) of the second bonding pads.

In some embodiments, in the integrated circuit package (e.g.,1c-1,1c-3,1c-9), a first conductive via (e.g., V11) is disposed between and electrically connected to a first one (e.g.,118a) of the first die pads and a first one (e.g., BP11) of the first bonding pads, and a first thermal via (e.g., V12) is disposed between a second one (e.g.,118c) of the first die pads and a second one (e.g., BP14) of the first bonding pads and electrically insulated from the second one of the first die pads. In some embodiments, the second one (e.g.,118c) of the first die pads is an active die pad electrically connected to the first device (e.g., T1). In some embodiments, the second one (e.g.,118c) of the first die pads is a floating die pad electrically insulated from the first device (e.g., T1). In some embodiments, the first one (e.g.,118a) of the first die pads is separated from the second one (e.g.,118c) of the first die pads. In some embodiments, the first semiconductor die further includes a first insulator (e.g., I1) between the first thermal via (e.g., V11) and the second one (e.g.,118c) of the first die pads. Besides, the second semiconductor die (e.g.,200) includes a plurality of second bonding pads (e.g., BP21to BP24), wherein the first one (e.g., BP11) of the first bonding pads is connected to a first one (e.g., BP21) of the second bonding pads, and the second one (e.g., BP14) of the first bonding pads is connected to a second one (e.g., BP24) of the second bonding pads.

In some embodiments, in the integrated circuit package (e.g.,1a-2,1a-4,1a-10), a first conductive via (e.g., V11) is disposed between and electrically connected to a first one (e.g., right side of118a) of the first die pads and a first one (e.g., BP11) of the first bonding pads, and a first thermal via (e.g., V12) is disposed between a second one (e.g., left side of118a) of the first die pads and a second one (e.g., BP12) of the first bonding pads and electrically insulated from the second one of the first bonding pads. In some embodiments, the second one (e.g., left side of118a) of the first die pads is an active die pad electrically connected to the first device (e.g., T1). In some embodiments, the first one (e.g., right side of118a) of the first die pads is connected to the second one (e.g., left side of118a) of the first die pads. In some embodiments, the first semiconductor die further includes a first insulator (e.g., I1′) between the first thermal via (e.g., V11) and the second one (e.g., left side of118a) of the first bonding pads. Besides, the second semiconductor die (e.g.,200) includes a plurality of second bonding pads (e.g., BP21to BP24), wherein the first one (e.g., BP11) of the first bonding pads is connected to a first one (e.g., BP21) of the second bonding pads, and the second one (e.g., BP12) of the first bonding pads is connected to a second one (e.g., BP22) of the second bonding pads.

In some embodiments, in the integrated circuit package (e.g.,1b-2,1b-4,1b-10), a first conductive via (e.g., V11) is disposed between and electrically connected to a first one (e.g.,118a) of the first die pads and a first one (e.g., BP11) of the first bonding pads, and a first thermal via (e.g., V12) is disposed between a second one (e.g.,118b) of the first die pads and a second one (e.g., BP13) of the first bonding pads and electrically insulated from the second one of the first bonding pads. In some embodiments, the second one (e.g.,118b) of the first die pads is an active die pad electrically connected to the first device (e.g., T1). In some embodiments, the first one (e.g.,118a) of the first die pads is separated from the second one (e.g.,118b) of the first die pads. In some embodiments, the first semiconductor die further includes a first insulator (e.g., I1′) between the first thermal via (e.g., V11) and the second one (e.g.,118b) of the first bonding pads. Besides, the second semiconductor die (e.g.,200) includes a plurality of second bonding pads (e.g., BP21to BP24), wherein the first one (e.g., BP11) of the first bonding pads is connected to a first one (e.g., BP21) of the second bonding pads, and the second one (e.g., BP13) of the first bonding pads is connected to a second one (e.g., BP23) of the second bonding pads.

In some embodiments, in the integrated circuit package (e.g.,1c-2,1c-4,1c-10), a first conductive via (e.g., V11) is disposed between and electrically connected to a first one (e.g.,118a) of the first die pads and a first one (e.g., BP11) of the first bonding pads, and a first thermal via (e.g., V12) is disposed between a second one (e.g.,118c) of the first die pads and a second one (e.g., BP14) of the first bonding pads and electrically insulated from the second one of the first bonding pads. In some embodiments, the second one (e.g.,118c) of the first die pads is a floating die pad electrically insulated from the first device (e.g., T1). In some embodiments, the first one (e.g.,118a) of the first die pads is separated from the second one (e.g.,118c) of the first die pads. In some embodiments, the first semiconductor die further includes a first insulator (e.g., I1′) between the first thermal via (e.g., V11) and the second one (e.g.,118c) of the first bonding pads. Besides, the second semiconductor die (e.g.,200) includes a plurality of second bonding pads (e.g., BP21to BP24), wherein the first one (e.g., BP11) of the first bonding pads is connected to a first one (e.g., BP21) of the second bonding pads, and the second one (e.g., BP14) of the first bonding pads is connected to a second one (e.g., BP24) of the second bonding pads.

In some embodiments, in the integrated circuit package (e.g.,1a-5,1a-11,1a-12), a first conductive via (e.g., V11) is disposed between and electrically connected to a first one (e.g., right side of118a) of the first die pads and a first one (e.g., BP11) of the first bonding pads, and a first thermal via (e.g., V12) is disposed between a second one (e.g., left side of118a) of the first die pads and a second one (e.g., BP12) of the first bonding pads and electrically insulated from a second device (e.g., T2) of the semiconductor device. In some embodiments, the first one (e.g., right side of118a) of the first die pads is connected to the second one (e.g., left side of118a) of the first die pads. Besides, the second semiconductor die (e.g.,200) includes a plurality of second bonding pads (e.g., BP21to BP24), wherein the first one (e.g., BP11) of the first die pads is connected to a first one (e.g., BP21) of the second bonding pads, and the second one (e.g., BP12) of the first die pads is connected to a second one (e.g., BP22) of the second bonding pads.

In some embodiments, in the integrated circuit package (e.g.,1b-5,1b-11,1b-12), a first conductive via (e.g., V11) is disposed between and electrically connected to a first one (e.g.,118a) of the first die pads and a first one (e.g., BP11) of the first bonding pads, and a first thermal via (e.g., V12) is disposed between a second one (e.g.,118c) of the first die pads and a second one (e.g., BP13) of the first bonding pads and electrically insulated from a second device (e.g., T2) of the semiconductor device. In some embodiments, the first one (e.g.,118a) of the first die pads is separated from the second one (e.g.,118c) of the first die pads. Besides, the second semiconductor die (e.g.,200) includes a plurality of second bonding pads (e.g., BP21to BP24), wherein the first one (e.g., BP11) of the first die pads is connected to a first one (e.g., BP21) of the second bonding pads, and the second one (e.g., BP13) of the first die pads is connected to a second one (e.g., BP23) of the second bonding pads.

In some embodiments, in the integrated circuit package (e.g.,1c-5,1c-11,1c-12), a first conductive via (e.g., V11) is disposed between and electrically connected to a first one (e.g.,118a) of the first die pads and a first one (e.g., BP11) of the first bonding pads, and a first thermal via (e.g., V12) is disposed between a second one (e.g.,118c) of the first die pads and a second one (e.g., BP14) of the first bonding pads and electrically insulated from the second one of the first die pads. In some embodiments, the second one (e.g.,118c) of the first die pads is a floating die pad electrically insulated from the first device (e.g., T1). In some embodiments, the first one (e.g.,118a) of the first die pads is separated from the second one (e.g.,118c) of the first die pads. Besides, the second semiconductor die (e.g.,200) includes a plurality of second bonding pads (e.g., BP21to BP24), wherein the first one (e.g., BP11) of the first die pads is connected to a first one (e.g., BP21) of the second bonding pads, and the second one (e.g., BP14) of the first die pads is connected to a second one (e.g., BP24) of the second bonding pads.

The relationships of components described above may be applied to different locations of thermal vias V22in the second semiconductor dies200, as shown in some of integrated circuit packages (e.g., e.g.,1a-6,1a-7,1a-8,1b-6,1b-7,1b-8,1c-6,1c-7,1c-8), so the details are not iterated herein.

In some embodiments, a dimension of the first conductive via (e.g., V11) is different from a dimension of the first thermal via (e.g., V12). In some embodiments, the dimension includes a height, a width, a top-view area or a combination thereof.

In some embodiments, in the integrated circuit package (e.g.,1a-1to1a-12,1b-1to1b-12,1c-1to1c-12,1d-1to1d-4), the first semiconductor die is bonded to the second semiconductor die through a face-to-face bonding.

In some embodiments, in the integrated circuit package (e.g.,2a-1to2a-4), the first semiconductor die is bonded to the second semiconductor die through a face-to-back bonding.

In some embodiments, an integrated circuit package (e.g.,1a-1to1a-12,1b-1to1b-12,1c-1to1c-12,1d-1to1d-4,2a-1to2a-4) includes a first semiconductor die (e.g.,100) bonded to a second semiconductor die (e.g.,200). The first semiconductor die includes a plurality of first die pads (e.g.,118ato118c) over a first device (e.g., T1), a plurality of first bonding pads (e.g., BP11to BP14) over the first die pads, a first conductive via (e.g., V11) disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via (e.g., V12) disposed between a second one of the first die pads and a second one of the first bonding pads. The second semiconductor die (e.g.,200) includes a plurality of second bonding pads (e.g., BP21to BP24), wherein the first one of the first die pads is connected to a first one of the second bonding pads, and the second one of the first die pads is connected to a second one of the second bonding pads. Besides, the first thermal via (e.g., V12) is electrically insulated from a second device (e.g., T2) of the second semiconductor die (e.g.,200).

In some embodiments, in the integrated circuit package (e.g.,1a-1,1a-3,1a-9,1b-1,1b-3,1b-9,1c-1,1c-3,1c-9), the first thermal via (e.g., V12) is electrically insulated from the second one of the first die pads.

In some embodiments, in the integrated circuit package (e.g.,1a-2,1a-4,1a-10,1b-2,1b-4,1b-10,1c-2,1c-4,1c-10), the first thermal via (e.g., V12) is electrically insulated from the second one of the first bonding pads.

In some embodiments, in the integrated circuit package (e.g.,1a-5,1a-11,1a-12,1b-5,1b-11,1b-12,1c-5,1c-11,1c-12), the first thermal via (e.g., V12) is electrically connected to the second one of the first die pads and the second one of the first bonding pads, and the second one of the first die pads is a dummy die pad.

The relationships of components described above may be applied to different locations of thermal vias V22in the second semiconductor dies200, as shown in some of integrated circuit packages (e.g., e.g.,1a-6,1a-7,1a-8,1b-6,1b-7,1b-8,1c-6,1c-7,1c-8), so the details are not iterated herein.

In some embodiments, in the integrated circuit package (e.g.,1d-1to1d-4,2a-1to2a-4), the first semiconductor die further includes a second thermal via (e.g., V12away from V11) disposed aside the first thermal via (e.g., V12adjacent to V11).

In view of the above, in the disclosure, the thermal control performance is improved by adding one or more thermal vias around the bonding interface between two adjacent semiconductor dies.

In accordance with some embodiments of the disclosure, an integrated circuit package includes a first semiconductor die and a second semiconductor die bonded to each other. The first semiconductor die includes a plurality of first die pads over a first device, a plurality of first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second semiconductor die includes a plurality of second bonding pads, wherein the first one of the first die pads is connected to a first one of the second bonding pads, and the second one of the first die pads is connected to a second one of the second bonding pads.

In some embodiments, the first semiconductor die further includes a first insulator between the first thermal via and the second one of the first die pads. In some embodiments, the first semiconductor die further includes a first insulator between the first thermal via and the second one of the first bonding pads. In some embodiments, the first one of the first die pads is connected to the second one of the first die pads. In some embodiments, the first one of the first die pads is separated from the second one of the first die pads. In some embodiments, a dimension of the first conductive via is different from a dimension of the first thermal via. In some embodiments, the dimension includes a height, a width, a top-view area or a combination thereof. In some embodiments, the second one of the first die pads is an active die pad electrically connected to the first device. In some embodiments, the second one of the first die pads is a floating die pad electrically insulated from the first device. In some embodiments, the first semiconductor die is bonded to the second semiconductor die through a face-to-face bonding. In some embodiments, the first semiconductor die is bonded to the second semiconductor die through a face-to-back bonding.

In accordance with some embodiments of the disclosure, an integrated circuit package includes a first semiconductor die bonded to a second semiconductor die. The first semiconductor die includes a plurality of first die pads over a first device, a plurality of first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads. The second semiconductor die includes a plurality of second bonding pads, wherein the first one of the first bonding pads is connected to a first one of the second bonding pads, and the second one of the first bonding pads is connected to a second one of the second bonding pads. Besides, the first thermal via is electrically insulated from a second device of the second semiconductor die.

In some embodiments, the first thermal via is electrically insulated from the second one of the first die pads. In some embodiments, the first thermal via is electrically insulated from the second one of the first bonding pads. In some embodiments, the first thermal via is electrically connected to the second one of the first die pads and the second one of the first bonding pads, and the second one of the first die pads is a dummy die pad. In some embodiments, the first semiconductor die further includes a second thermal via disposed aside the first thermal via.

In accordance with some embodiments of the disclosure, a method of forming an integrated circuit package includes forming first die pads on a first semiconductor substrate; forming a first insulator on a first one of the first die pads; forming a first conductive via and a first thermal via on the first one of the first die pads, wherein the first insulator is between the first thermal via and the first one of the first die pads; and forming first bonding pads on the first conductive via and the first thermal via, so as to obtain a first semiconductor die.

In some embodiments, a method of forming the first conductive via and the first thermal via includes forming a seed layer over the first insulator and the first one of the first die pads, forming a photoresist layer on the seed layer, wherein the photoresist layer has a first opening corresponding to the first insulator and a second opening corresponding to the first one of the die pad, forming the first conductive via and the first thermal via by using the seed layer as a seed, and removing the photoresist layer. In some embodiments, the method further includes forming a second thermal via on a second one of the first die pads. In some embodiments, the method further includes bonding a second semiconductor die to the first semiconductor die through a metal-to-metal bonding and a dielectric-to-dielectric bonding.