TUNNELING FIELD EFFECT TRANSISTORS (TFETS) WITH UNDOPED DRAIN UNDERLAP WRAP-AROUND REGIONS

Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region formed above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around regions.

TECHNICAL FIELD

Embodiments of the invention are in the field of semiconductor devices and, in particular, tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions.

BACKGROUND

In the manufacture of integrated circuit devices, a metal oxide semiconductor field effect transistor's (MOSFET) sub-threshold slope has a theoretical lower limit of kT/q (60 mV/dec at room temperature) with k being Boltzmann's constant, T being absolute temperature, and q being the magnitude of electron charge on an electron. For low active-power, it is very favorable to operate at lower supply voltages because of active power's strong dependence on supply voltage (e.g., a dependency of approximately Capacitance (C)*Voltage (V)2). However, due to limited (kT/q) rate of increase of current from off-current to on-current, when MOSFET is operated at low supply-voltages, the on-current would be significantly lower because it may be operating close to its threshold-voltage. A different type of transistor—tunneling FET (TFET) has been shown to achieve sharper turn-on behavior (steeper subthreshold-slope) than MOSFET. This enables higher on-currents than MOSFET at low supply-voltages, as shown inFIG. 1.FIG. 1illustrates drain current (Id) versus gate voltage (Vg) for a low power MOSFET and an InAs TFET for a gate length of 20 nanometers (nm). A heterojunction TFET, which uses a combination of two semiconductor materials to enable higher tunneling current, enables better TFET characteristics as illustrated inFIG. 2.FIG. 2also illustrates a low power MOSFET and a homojunction InAs TFET for a gate length of 15 nm, a gate oxide thickness of 0.8 nm, a drain to source voltage of 0.3 volts, and an off current of 1 nA/um.

However, TFET devices require a long drain underlap—an undoped region between gate edge and doped drain region, to keep its steep sub-threshold slope and low off-current leakage at short gate lengths.FIG. 3shows an InAs TFET curve302with drain underlap and InAs TFET curve306having symmetric source/drain spacers without a drain underlap. Without drain underlap, the leakage current is high and the subthreshold slope is not steep for curve306. When drain underlap is introduced, leakage reduces and a sub-threshold slope steeper than 60 mV/dec can be achieved. The curve304shows the device characteristics for a low power MOSFET.

FIG. 4shows cross-sectional sketches for a TFET device400with drain underlap and a TFET device450without drain underlap. Although the TFET device400with a drain underlap achieves better device characteristics including lower leakage and steeper subthreshold-slope, it requires a longer device, costing extra area for the transistor layout. Also, a longer drain underlap region410will likely require a different spacer processing, adding to process complexity and cost.

DESCRIPTION OF THE EMBODIMENTS

Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

In one embodiment, TFETs are used to achieve steeper sub-threshold slope (SS) and lower leakage versus a corresponding metal oxide semiconductor field effect transistor (MOSFET) with a thermal limit of approximately 60 mV/decade. Generally, embodiments described herein may be suitable for high performance or scaled transistors for logic devices having low power applications.

To provide a background context, a conventional TFET design requires an undoped region between the gate edge and the n+ doped drain region, called the drain underlap region as illustrated inFIG. 4. This prevents degradation of a TFET device's steep sub-threshold slope and keeps leakage current low. The leakage and sub-threshold degradation is due to ambipolar leakage and a short-channel effect. Ambipolar leakage is caused by band-to-band-tunneling between the channel and drain region. A short channel effect includes tunneling from source to either channel or drain due to drain effect on channel potential and short source-to-drain distance.

FIG. 5illustrates a tunneling path of an electron at a source side of a heterojunction TFET device with a drain underlap region. The TFET device500includes a gate520, a source region522(e.g., p+ doped), a channel524(e.g., undoped channel), a drain underlap region526(e.g., undoped), and a drain region528(e.g., n+ doped). An energy band structure544for the TFET device is shown below the TFET device. The energy band structure544includes a conduction band540and a valence band542. Electrons within the conduction band are mobile charge carriers in solid state devices. The energy band structure shows electron energy in units of eV on a vertical axis and a position within the TFET device in units of nanometers on a horizontal axis.

Leakage is dominated by a tunneling distance from the source to a point in the drain of the TFET device. If this distance is longer, then leakage will be lower. The shortest path illustrated by arrow550to the other side of the bandgap together with the height of barrier semi-classically explains how large the tunneling current will be. Thus, it is desirable to keep this tunneling distance longer during an off condition and shorter during an on condition of the TFET device.

Generally,FIG. 6aillustrates a top down view600of a multi-gate device architecture, in accordance with an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, FinFET) includes gate electrodes602,604,606, an active region or fin620, and isolation region630. Generally,FIG. 6billustrates a cross-sectional view650through a cross-section610of the active region620of the multi-gate device architecture ofFIG. 6a, in accordance with an embodiment of the present invention. The device architecture includes the gates602,604,606, the dielectric layers660-662, gate spacers640-645, the active region620, and a substrate690. This design architecture includes a wrapped-around drain underlap design as illustrated inFIGS. 6A-13and15in order to achieve TFET devices without thick gate spacers or a longer device layout such as a horizontal drain underlap design, which is illustrated inFIG. 14.

Generally,FIG. 7aillustrates a top down view700of a multi-gate device architecture during a lithography operation, in accordance with an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, FinFET) includes a blocking layer712with an opening that exposes gate electrodes702,704, and an active region720. The opening has a length708approximately equal to a polysilicon pitch and a width709. Generally,FIG. 7billustrates a cross-sectional view750through a cross-section710of the active region720of the multi-gate device architecture ofFIG. 7a, in accordance with an embodiment of the present invention. The device architecture includes the gate electrodes702,704,706and respective gate spacers740-745and gate dielectric layers760-762. The device architecture also includes the blocking layer712, the active region720, and the substrate790. The blocking layer712provides an opening to the active region in a source region. The exposed active region is then either implanted with p+ doping or etched and a p+ in-situ doped source region is grown as illustrated inFIGS. 8aand8b.

Generally,FIG. 8aillustrates a top down view800of a multi-gate device architecture, in accordance with an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, finFET) includes a blocking layer812with an opening that exposes gate electrodes802and804and a source region808(p+ source region). Generally,FIG. 8billustrates a cross-sectional view850through a cross-section810of an active region of the multi-gate device architecture ofFIG. 8a, in accordance with an embodiment of the present invention. The device architecture includes the gate electrodes802,804,806and respective gate spacers840-845and gate oxide layers860-862. The device architecture also includes the blocking layer812, the active region820, and the substrate890. The p+ source region is formed in the active region820with implantation or partially in the active region with an etch and in-situ doped source growth. After a photoresist and block layer812(or hard mask) are removed, then a new lithography operation is performed to open drain regions as illustrated inFIGS. 9aand9b.

Generally,FIG. 9aillustrates a top down view900of a multi-gate device architecture, in accordance with an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, finFET) includes a blocking layer912with an opening that exposes gate electrodes902and904and an active region920for forming a drain region. Generally,FIG. 9billustrates a cross-sectional view950through a cross-section910of the active region920of the multi-gate device architecture ofFIG. 9a, in accordance with an embodiment of the present invention. The device architecture includes the gate electrodes902,904,906and respective gate spacers940-945and gate dielectric layers960-962. The device architecture also includes the blocking layer912, the active region920, and the substrate990. A drain region is formed on the undoped active region920by growing a thin layer of additional undoped material and then growing in-situ n-doped material or implanting the region with a low dose and low energy n-type doping as illustrated inFIGS. 10aand10b.

Generally,FIG. 10aillustrates a top down view1000of a multi-gate device architecture, in accordance with an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, finFET) includes a blocking layer1012with an opening that exposes gates1004and1008and an active region1020for forming a drain region with n+ doping. Generally,FIG. 10billustrates a cross-sectional view1050through a cross-section1010of an active region of the multi-gate device architecture ofFIG. 10a, in accordance with an embodiment of the present invention. The device architecture includes the gate electrodes1002,1004,1006and respective gate spacers1040-1045and gate oxide layers1060-1062. The device architecture also includes the blocking layer1012, the active region1020, and the substrate1090. A drain region1072is formed on the undoped active region1020by growing a thin layer1071of additional undoped material and then growing in-situ n-doped material1070or implanting the region with a low dose and low energy n-type doping. After the photoresist and block layer1012(or hard mask) are removed, then a TFET with wrapped-around drain underlap having symmetric spacers is formed as illustrated inFIGS. 11aand11b.

Generally,FIG. 11aillustrates a top down view1100of a multi-gate device architecture with wrapped-around drain underlap and symmetric spacers, in accordance with an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, FinFET) includes gates1102,1104, and1106and an active region1120(e.g., fin or body) for forming a source region1108(e.g., p+ source region) and a drain region1160(e.g., n+ drain region). Generally,FIG. 11billustrates a cross-sectional view1150through a cross-section1110of the active region1120of the multi-gate device architecture ofFIG. 11a, in accordance with an embodiment of the present invention. The device architecture includes the gate electrodes1102,1104,1106and respective gate spacers1140-1145and gate dielectric layers1160-1162(e.g., gate oxide layers). The device architecture also includes the active region1120and the substrate1190. A drain region is formed on the undoped active region1120by growing a thin layer1171of additional undoped material and then growing in-situ n-doped material1170or implanting the region including layer1171with a low dose and low energy n-type doping. A source region1108(e.g., p+ source region) is also formed on the undoped active region1120. A similar process approach illustrated inFIGS. 6a-11bcan be applied for a heterojunction TFET device design to provide enhanced TFET performance.

Generally,FIG. 12aillustrates a top down view1200of a multi-gate device architecture with wrapped-around drain underlap having symmetric spacers, in accordance with an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, finFET) includes gate electrodes1202,1204, and1206and an active region1220for forming a source region (e.g., p+ source region) and a drain region (e.g., n+ drain region) for a small size TFET transistor1270. Generally,FIG. 12billustrates a cross-sectional view1250through a cross-section1210of the active region1220of the multi-gate device architecture ofFIG. 12a, in accordance with an embodiment of the present invention. The device architecture includes the gate electrodes1202,1204,1206and respective symmetric gate spacers1240-1245and gate dielectric layers1260-1262. The device architecture also includes the active region1220(e.g., undoped InAs), the substrate1290, a source region1208with p+ doping (e.g., GaSb) and a drain region1273. The drain region1273is formed on the undoped active region1220by growing a thin layer1271of additional undoped material (e.g., InAs) and then growing in-situ n-doped material1272(e.g., n-type InAs) or implanting the region including layer1271with a low dose and low energy n-type doping.FIGS. 12aand12billustrate different views of an n-type TFET using GaSb in the source region and InAs in the active region including channel regions under the gate regions and also the drain region1273. In one embodiment, a p-type TFET can be designed with Si, Ge, Sn or any alloy of these materials in the source region and Si, Ge, Sn or any alloy of these materials in the active region including channel regions under the gate regions and also drain regions. In an embodiment, a TFET can be designed with In, Ga, Al, As, Sb, P, N or any alloy of these materials in the source region and In, Ga, Al, As, Sb, P, N or any alloy of these materials in the active region including channel regions under the gate regions and also drain regions. Including contacts (e.g., a source contact1280and a drain contact1281), the TFET device can be designed as small as a counterpart MOSFET device.

Generally,FIG. 13illustrates a cross-sectional view1300through a cross-section1212of the active region1220of the multi-gate device architecture ofFIG. 12b, in accordance with an embodiment of the present invention. The device architecture includes the gate electrode1304and respective symmetric gate spacers1340-1343and gate oxide layers1360-1361. The device architecture also includes the active region1320(e.g., undoped InAs), a source region1308with p+ doping (e.g., GaSb) and a drain region1325. The drain region1325is formed on the undoped active region1320by growing a thin layer1321,1324of additional undoped material (e.g., InAs) and then growing in-situ n-doped material1322,1323(e.g., n-type InAs) or implanting the region including layer1321,1324with a low dose and low energy n-type doping. Arrows1380and1381indicate paths of electrons from the source region to the drain region.

Generally,FIG. 14illustrates a cross-sectional view1400through a cross-section of an active region of a conventional multi-gate device architecture. The device architecture includes the gate electrode1404and respective asymmetric gate spacers1420,1421,1440,1441and gate dielectric layers. The device architecture also includes the active region1430(e.g., undoped InAs), a source region1408with p+ doping (e.g., GaSb), drain underlap region1431, and a drain region1410(e.g., n-type InAs).FIG. 14illustrates the conventional long horizontal drain underlap TFET whileFIG. 13illustrates a wrapped-around drain underlap TFET. Arrow1422indicates a path of an electron from the source region to the drain region.

Although the wrapped-around TFET ofFIG. 13has a shorter device length in comparison to the TFET ofFIG. 14, the wrapped-around TFET still has good electrostatics to keep leakage current low.

FIGS. 15 and 16illustrate device cross-sections for the wrapped-around TFET1500and the conventional long horizontal TFET, respectively. Generally,FIG. 15illustrates a device cross-section for the wrapped-around TFET, in accordance with an embodiment of the present invention. The wrapped-around TFET1500includes gate electrodes1520a,1520b, a gate spacer1560and gate dielectric layers1522and1523. An additional symmetric gate spacer and additional drain portion are not shown inFIG. 15with the additional symmetric gate spacer being symmetric with respect to the spacer1560and the additional drain portion being symmetric with respect to a drain electrode1540and a drain region1542. The TFET device includes an active region1525or body (e.g., undoped InAs), a source electrode1510, a source region1511with p+ doping (e.g., GaSb), the drain electrode1540with the drain region1542, and a drain underlap region1530. In one embodiment, the active region1525or body has a width of 5 nm as illustrated with double arrows1531and1532. The source has a length1512of 30 nm, a channel of the active region has a length1524of 20 nm, a drain underlap has a first length1532of 5 nm and a second length1533of 10 nm, and a drain region has a length1541of 15 nm. The gate dielectric layers may have a thickness1526of approximately 1 nm. A spacer1560has a thickness1561of approximately 3 nm. The first and second lengths1532and1533of the drain underlap1530are approximately perpendicular to a device length in order to only contribute a width1531of the drain underlap1530in a direction of device length but yet provide a length1532and1533for improved leakage characteristics.

Generally,FIG. 16illustrates a device cross-section for the conventional long horizontal TFET. The conventional long horizontal TFET1600corresponds to the TFET1400ofFIG. 14. The TFET1600includes gate electrodes1620a,1620b, gate spacers1626and1627, and gate oxide layers1660aand1660b. The TFET device also includes an active region1622or body (e.g., undoped InAs), a source electrode1610, a source region1612with p+ doping (e.g., GaSb), a drain electrode1640with a drain region1642with n+ doping, and a drain underlap region1625. The active region1622or body has a width of 5 nm as illustrated with double arrows1641. The drain has a length1665of 20 nm, a channel has a length1623of 20 nm, a drain underlap has a length1624of 10 nm, and a source region has a length1611of 30 nm.

FIGS. 17 and 18illustrate potential profiles for the conventional long horizontal TFET and the wrapped-around TFET, in accordance with an embodiment of the present invention.FIG. 17illustrates potential profiles for the conventional long horizontal TFET and the wrapped-around TFET for when the gates of the TFET devices are ON, in accordance with an embodiment of the present invention. The graph1700shows energy (eV) versus position within the respective TFET device. The conduction band (upper band) and valence band (lower band) of the conventional long horizontal TFET1730are nearly identical to the conduction band (upper band) and valence band (lower band) of the wrapped-around TFET1740with the gate voltage bias being sufficient to turn ON the devices.

FIG. 18illustrates potential profiles for the conventional long horizontal TFET and the wrapped-around TFET for when the TFET devices are OFF, in accordance with an embodiment of the present invention. The graph1800shows energy (eV) versus position within the respective TFET device. The conduction band (upper band) and valence band (lower band) of the conventional long horizontal TFET1830are nearly identical to the conduction band (upper band) and valence band (lower band) of the wrapped-around TFET1840for a position (nm) of zero to 40. The conduction and valence bands of these devices diverge from a position of approximately 40 to 80 with the devices being biased for OFF condition. A tunneling path1850of the wrapped-around TFET of an electron from the valence to the conduction band is significantly longer than a tunneling path1852of the conventional long horizontal TFET. The tunneling path is correlated to the leakage current, thus the wrapped-around TFET yields lower leakage currents.

Thus, the wrapped-around TFET has a shorter device length for smaller area and cost and no complex spacer process in comparison to the conventional long horizontal TFET. The wrapped-around TFET also has a better controlled potential profile yielding a lower OFF condition tunneling currents and thus a TFET with lower leakage in comparison to the conventional long horizontal TFET.

In the above described embodiments, whether formed on virtual substrate layers or on bulk substrates, an underlying substrate used for TFET device manufacture may be composed of a semiconductor material that can withstand a manufacturing process. In an embodiment, the substrate is a bulk substrate, such as a P-type silicon substrate as is commonly used in the semiconductor industry. In an embodiment, substrate is composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof. In another embodiment, the substrate is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate.

The substrate may instead include an insulating layer formed in between a bulk crystal substrate and an epitaxial layer to form, for example, a silicon-on-insulator substrate. In an embodiment, the insulating layer is composed of a material such as, but not limited to, silicon dioxide, silicon nitride, silicon oxy-nitride or a high-k dielectric layer. The substrate may alternatively be composed of a group III-V material. In an embodiment, the substrate is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In another embodiment, the substrate is composed of a III-V material and charge-carrier dopant impurity atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

In the above embodiments, TFET devices include source drain regions that may be doped with charge carrier impurity atoms. In an embodiment, the group IV material source and/or drain regions include N-type dopants such as, but not limited to phosphorous or arsenic. In another embodiment, the group IV material source and/or drain regions include P-type dopants such as, but not limited to boron.

In the above embodiments, although not always shown, it is to be understood that the TFETs include gate stacks with a gate dielectric layer and a gate electrode layer. In an embodiment, the gate electrode of gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-K material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, aluminium oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the corresponding channel region. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride.

In an embodiment, the gate electrode is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer. In an embodiment, the gate electrode is composed of a P-type or N-type material. The gate electrode stack may also include dielectric spacers.

The TFET semiconductor devices described above cover both planar and non-planar devices, including gate-all-around devices. Thus, more generally, the semiconductor devices may be a semiconductor device incorporating a gate, a channel region and a pair of source/drain regions. In an embodiment, semiconductor device is one such as, but not limited to, a MOS-FET. In one embodiment, semiconductor device is a planar or three-dimensional MOS-FET and is an isolated device or is one device in a plurality of nested devices. As will be appreciated for a typical integrated circuit, both N- and P-channel transistors may be fabricated on a single substrate to form a CMOS integrated circuit. Furthermore, additional interconnect wiring may be fabricated in order to integrate such devices into an integrated circuit.

Generally, one or more embodiments described herein are targeted at tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions. Group IV or III-V active layers for such devices may be formed by techniques such as, but not limited to, chemical vapor deposition (CVD) or molecular beam epitaxy (MBE), or other like processes.

FIG. 19illustrates a computing device1900in accordance with one implementation of the invention. The computing device1900houses a board1902. The board1902may include a number of components, including but not limited to a processor1904and at least one communication chip1906. The processor1904is physically and electrically coupled to the board1902. In some implementations the at least one communication chip1906is also physically and electrically coupled to the board1902. In further implementations, the communication chip1906is part of the processor1904.

The processor1904of the computing device1900includes an integrated circuit die1910packaged within the processor1904. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices1912, such as tunneling field effect transistors (TFETs) built in accordance with implementations of the invention. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip1906also includes an integrated circuit die1920packaged within the communication chip1906. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices1921, such as tunneling field effect transistors (TFETs) built in accordance with implementations of the invention.

In further implementations, another component housed within the computing device1900may contain an integrated circuit die that includes one or more devices, such as tunneling field effect transistors (TFETs) built in accordance with implementations of the invention.

Thus, embodiments of the present invention include tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions.

In an embodiment, a tunneling field effect transistor (TFET) includes a homojunction active region formed (e.g., placed, arranged, positioned, disposed) above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate stack is formed on the undoped channel region, between the source and wrapped-around regions. The gate stack includes a gate dielectric portion and gate electrode portion. The TFET has a length in a first direction and a width in a second direction while the wrapped-around region has a width in the second direction that is greater than a length in the first direction. The length and width of the TFET may be designed to have similar dimensions as a length and width of a metal oxide semiconductor field effect transistor (MOSFET).

In one embodiment, the TFET is a finfet or trigate based device.

In an embodiment, the TFET device further includes symmetric gate spacers each adjacent to the gate electrode. The wrapped-around region may be grown on an exposed portion of the active region and is adjacent to one of the gate spacers of the gate electrode.

In one embodiment, a doped drain region is formed by growing in-situ doped material on an exposed portion of the wrapped-around region.

In one embodiment, the TFET device is a n-type TFET that includes the source region having a p+ dopant and the drain region having a n-type dopant.

In one embodiment, a tunneling field effect transistor (TFET) includes a hetero-junction active region formed above a substrate. The hetero-junction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around region. A gate stack includes a gate dielectric portion and gate electrode portion.

In one embodiment, the TFET has a length in a first direction and a width in a second direction and the wrapped-around region has a width in the second direction that is greater than a length in the first direction.

In an embodiment, the length and width of the TFET is similar to a length and width of a metal oxide semiconductor field effect transistor (MOSFET). The TFET may be a finfet or trigate based device.

In one embodiment, the TFET device further includes symmetric gate spacers having approximately the same thickness and each adjacent to the gate electrode.

In an embodiment, the wrapped-around region is grown on an exposed portion of the active region and is adjacent to one of the gate spacers of the gate electrode.

A doped drain region is formed by growing in-situ doped material on an exposed portion of the wrapped-around region.

In one embodiment, the TFET device is a n-type TFET that includes the source region having Gallium Antimony (GaSb), the channel region having Indium Arsenide (InAs), and the drain region having InAs.

In one embodiment, a computing device includes memory to store electronic data and a processor coupled to the memory. The processor processes electronic data. The processor includes an integrated circuit die having tunneling field effect transistors (TFETs). At least one TFET includes a hetero-junction active region that is formed above a substrate. The hetero-junction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around region. A gate stack includes a gate dielectric portion and gate electrode portion.

In one embodiment, the TFET has a length in a first direction and a width in a second direction and the wrapped-around region has a width in the second direction that is greater than a length in the first direction.

In an embodiment, the length and width of the TFET is similar to a length and width of a metal oxide semiconductor field effect transistor (MOSFET). The TFET may be a finfet or trigate based device.

In one embodiment, the TFET device further includes symmetric gate spacers having approximately the same thickness and each adjacent to the gate electrode.

In an embodiment, the wrapped-around region is grown on an exposed portion of the active region and is adjacent to one of the gate spacers of the gate electrode.

A doped drain region is formed by growing in-situ doped material on an exposed portion of the wrapped-around region.

In one embodiment, the TFET device is a n-type TFET that includes the source region having Gallium Antimony (GaSb), the channel region having Indium Arsenide (InAs), and the drain region having InAs.