Device and method for digital data distribution, device and method for digital data reproduction, synchronized reproduction system, program, and recording medium

In order to eliminate timing offset between reproduction devices when a content transmitted from a distribution device is received and reproduced by a plurality of reproduction devices, data (SCR) indicating the elapsed time from the start of the content, generated by counting clock pulses, and data (FCR) indicating a frame number generated by counting the number of frames reproduced by a decoder (54) are transmitted by the distribution device, and a clock generation unit (103) in each reproduction device is controlled so that data (STC) indicating the elapsed time and data (FTC) indicating the frame number, which are generated in the same manner by each reproduction device, match the transmitted data (SCR, FCR). Synchronization between reproduction devices can thereby be established even when, in a state in which a content is being reproduced by one reproduction device, another reproduction device subsequently connects to the distribution device.

TECHNICAL FIELD

The present invention relates to a digital data distribution device and method and a digital data reproduction device and method, more particularly to technology for obtaining frame synchronization when an identical content is reproduced on a plurality of display devices. The invention further relates to a synchronized reproduction system equipped with the above digital data distribution device and digital data reproduction device. The invention relates further to a program for causing a computer to execute the digital data distribution method, a program for causing a computer to execute the digital data reproduction method, and a computer-readable recording medium on which either of these programs is recorded.

BACKGROUND ART

Conventional reproduction systems have synchronized the picture reproduction of a selected content by using a frame synchronization signal on a digital bus (for example, patent reference 1).

PRIOR ART REFERENCES

Patent Reference

Patent reference 1: Japanese Patent Application Publication No. 2003-173614

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

The conventional systems start decoding operations in synchronization with the frame synchronization signal. Consequently, synchronization can be established when distribution from the transmitting-side device starts after all reproduction devices are in the receiving mode. A problem is that when the transmitting-side device is distributing a content continuously, a reproduction device that connects later and then starts to reproduce the content cannot establish frame synchronization. Another problem is the skipping of frames when synchronization is lost and then recovered. Gradually increasing loss of frame synchronization during lengthy reproduction continues is yet another problem.

Means for Solving the Problem

A digital data distribution device according to the invention comprises:

a clock generation unit for generating clock pulses with a given frequency;

a data reading unit for reading a content including audio and video from a storage medium that stores the content;

a decoder for decoding the content read by the data reading unit;

a reference clock counter that is reset when decoding of each content begins and thereafter counts the clock pulses generated by the clock counter to generate data indicating elapsed time from the start of the content for at least some frames constituting the video of the content;

a frame synchronization counter that is reset when decoding of each content begins and thereafter counts the number of frames constituting the video decoded by the decoder to generate data indicating a frame number in the content for at least some of the frames constituting the video of the content; and

a communication unit for transmitting data of the content that have been read from the storage medium, transmitting the data indicating the elapsed time generated by the reference clock counter, and transmitting the data indicating the frame number generated by the frame synchronization counter.

A digital data reproduction device according to the invention comprises:

a clock generation unit for generating clock pulses with a given frequency;

a communication unit for receiving data of a content including audio and video and, for at least some frames constituting the video, data indicating elapsed time from the start of the content and data indicating a frame number in the content;

a decoder operating on the clock pulses to decode the audio and the video of the content received by the communication unit;

a separation unit for separating the data indicating the elapsed time and the data indicating the frame number from the data received by the communication unit;

a reference clock counter in which the data indicating the elapsed time received by the communication unit is set as an initial value when, on a basis of the data of the content received by the communication unit, reproduction of the content begins, the reference clock counter counting the clock pulses generated by the clock generation unit to generate internal data indicating elapsed time from the start of the content for at least some of the frames constituting the video of the content;

a frame synchronization counter in which the data indicating the frame number received by the communication unit is set as an initial value, when the reproduction of the content begins, the frame synchronization counter counting the number of frames constituting the video decoded by the decoder to generate internal data indicating a frame number in the content for at least some of the frames constituting the video of the content;

a frame synchronization comparator for comparing the data indicating the frame number received by the communication unit with the internal data generated by the frame synchronization counter, during the reproduction of the content;

a clock comparator for comparing the data indicating the elapsed time received by the communication unit with the internal data generated by the reference counter, during the reproduction of the content; and

a frequency control unit for combining a comparison result obtained by the frame synchronization comparator with a comparison result obtained by the clock comparator and controlling the frequency of the clock pulses generated by the clock generation unit on a basis of a result of combination.

A synchronized reproduction system according to the invention comprises the above digital data distribution device and one or more of the above digital data reproduction devices which are connected to the digital data distribution device by a digital bus.

Effect of the Invention

The invention can synchronize reproduction by a plurality of reproduction devices. In addition, if, while one reproduction device is already reproducing a given content, another reproduction device is connected to the distribution device, these reproduction devices can also be synchronized.

MODE FOR CARRYING OUT THE INVENTION

First Embodiment

FIG. 1shows a content reproduction system according to the first embodiment of the invention.

The illustrated content reproduction system has a distribution device10as a transmitting-side device, and a plurality of reproduction devices11to14as receiving-side devices. The distribution device10and reproduction devices11to14are interconnected by a digital bus20. The content reproduction system shown inFIG. 1is used in, for example, a rear seat entertainment system for listening to audio and viewing video in the cabin of a car.

The digital bus20may be in the form of wired connections such as MOST (Media-Oriented System Transport), IEEE 1394, or Ethernet connections. Alternatively, the digital bus20may be in the form of wireless connections such as those referred to as WiFi or Bluetooth (registered trademark).

The reproduction system may be used in a mode in which a content distributed from the single distribution device10is received by the plurality of reproduction devices11to14, video and audio are reproduced by the plurality of the reproduction devices11to14for display on respective display units and for audio output by an audio output device in one or more of the reproduction devices. A loudspeaker or headphones, for example, may be used as the audio output device in this case. Audio may be output simultaneously from all the reproduction devices, or may be output from only some one of the reproduction devices.

If there is any timing offset in picture among the plurality of the reproduction devices11to14, synchronization with the sound is imperfect, which is disconcerting. To solve this problem, it would be desirable to achieve reproduction with timing offset of not even one frame.

It would also be desirable for reproduction timing offset not to occur even when, while one reproduction device (for example, reproduction device11) is already reproducing a given content, other reproduction devices (reproduction devices12to14) are connected to the distribution device10at different timings and start to reproduce the same content.

It would also be desirable for timing offset of picture of even one frame not to occur among the reproduction devices11to14even during lengthy reproduction.

In addition, when synchronization is lost, it would be desirable to recover synchronization without skipping frames.

The reproduction system of the present invention meets these requirements.

FIG. 2shows an example of the configuration of the distribution device10inFIG. 1. The illustrated transmitting device reads a content from a storage medium51such as an HDD, a DVD, a USB memory, an SD memory card, a CD-ROM, or a Blu-ray disc in which the content is stored, and transmits the content toward the reproduction devices11to14shown inFIG. 1via the digital bus20, and has a data reading unit52, a clock generation unit53, a decoder54, an STC counter55, a frame synchronization counter56, a multiplexing unit57, a transmission processing unit58, a communication unit59, and a control unit60.

The control unit60is formed of, for example, the CPU of a microcomputer, and controls the entire distribution device. In particular, the control unit60controls the data reading unit52, decoder54, STC counter55, frame synchronization counter56, multiplexing unit57, and communication unit59. The signal lines for control signals supplied from the control unit60to each of these are omitted from the drawing.

The data reading unit52reads a content from the storage medium51. The reading of data (e.g., the timing of the reading) is controlled by the control unit60. The data reading unit52reads data, taking a certain cluster as a unit, on the basis of instructions from the control unit60.

When the storage medium51is an HDD, a DVD, a CD-ROM, a Blu-ray disc, or the like, the storage medium51and the data reading unit52are interconnected by, for example, a SATA (Serial Advanced Technology Attachment) interface, and reading is performed by memory transfer by a DMA facility included in the CPU constituting the control unit60.

When the storage medium51is a USB memory, the storage medium51and the data reading unit52are interconnected by a USB interface, and when the storage medium51is an SD memory card, the storage medium51and the data reading unit52are interconnected by an SD interface; in these cases data are read by a DMA facility included in the CPU constituting the control unit60or by software.

The storage medium51, the data reading unit52, and the decoder54are interconnected by a data bus61.

The clock generation unit53generates clock pulses C53which are used as a reference for the operation of the entire reproduction system. The generated clock pulses C53are in the form of, for example, a 27-MHz square wave.

The decoder54decodes the content read by the data reading unit52. When the content is compressively encoded according to MPEG-2, the content is decoded according to MPEG-2, and the picture data for each frame before compression are reproduced. The decoder54performs the decoding on the basis of the clock pulses generated by the clock generation unit53(with the decoding timing being controlled by the clock pulses).

The STC (System Time Clock) counter55, also referred to as a reference clock counter, counts the clock pulses C53output by the clock generation unit53, and outputs a count value C55. The count value C55is reset to an initial value of ‘0’ each time reading of each content begins (including cases in which reading is switched from one content to another), and then the clocks C53are counted. The count value C55therefore indicates elapsed time or reproduction time from the start of the content, and is transmitted to the reproduction devices11to14as reference time information SCR (System Clock Reference) for the entire reproduction system.

The STC counter55is, for example, a 42-bit counter, and if 27-MHz clock pulses C53are counted, the count repeats in cycles of approximately 162 seconds.

The frame synchronization counter56counts the number of video frames reproduced by the decoding of the content by the decoder54, and outputs a count value C56. The count value C56is reset to an initial value of ‘0’ when reading of each content begins (including cases in which reading is switched from one content to another), and is incremented on input of frame timing signals included in the video signal reproduced by the decoder54. The count value C56therefore represents a frame number in the content (e.g., data indicating how many frames the current frame is from the start of the content), and is transmitted to the reproduction devices11to14as frame number data FCR (Frame Clock Reference).

The frame synchronization counter56is, for example, a 32-bit counter. For a content based on NTSC standards, 30-Hz frame timing signals are counted, so that a single cycle lasts approximately 4.5 years. Because 4.5 years is an unrealistically long time for the reproduction of a single content, the FCR could be said to represent each frame in the content uniquely.

The multiplexing unit57multiplexes the SCR from the STC counter55and the FCR from the frame synchronization counter56to generate synchronization packets. In the multiplexing of the SCR and FCR, the FCR value captured when the FCR value is updated (incremented) is multiplexed with the SCR value at the time of the update.

The STC counter55counts at a higher speed than the frame synchronization counter56. Transmission of every SCR value counted by the STC counter55to the reproduction devices would require an impracticably large amount of data transmission. Accordingly, the FCR value and the SCR value are read by the multiplexing unit57at the timings at which the frame synchronization counter56increments the count value C56to generate synchronization packets in which the FCR and SCR values are multiplexed.

The transmission processing unit58converts the data of the content read by the data reading unit52to packets in a format suitable for transmission, for example, TS packets (transport stream packets).

The communication unit59transmits digital data. If the digital bus20is, for example, the communication unit59transmits synchronization packets as TCP packets, and transmits TS packets of audio and video data (audio and video packets) as UDP packets.

TCP packets are suitable for transmission of synchronization packets because they reliably reach their destinations without data errors. In contrast, TS packets of audio and video are transmitted as UDP packets because they enable large amounts of data to be transmitted and received in real time. Because the data field of a synchronization packet contains at most about 14 bytes, and the transmission interval is 1/30 of a second, even with TCP packets there is no problem of delay. Because it is the decoder104in the receiving side that operates on the basis of the FCR and SCR included in synchronization packets, transmission of the TS packets of audio and video does not have to be precisely synchronized with transmission of the synchronization packets.

FIG. 4(a)shows a synchronization packet200that is transmitted as a TCP packet.

Included in the data field202that follows the TCP header201of the synchronization packet200, is content identification information203of 16 bits, for example, which is followed successively by frame synchronization identification information204, a 32-bit FCR value205, frame synchronization identification information206, and a 42-bit SCR value.

The synchronization identification information204that identifies the FCR value205is, for example, 0x01 (0x indicates that the following numeric value is a hexadecimal number), and the synchronization identification information206that identifies the SCR value207is, for example, 0x02.

FIG. 4(b)shows a, UDP packet (audio and video packet)210that transmits audio and video. In the data field212that follows the UDP header211of the audio and video packet, content identification information213, of 16 bits, for example, is followed by content data214. Audio data and video data are stored in the content data214, divided into 188-byte TS packets.

The purpose of the content identification information203in the synchronization packet200inFIG. 4(a)and the content identification information213in the audio-video packet210inFIG. 4(b)is to confirm that the synchronization packet200and the audio-video packet210including them mutually correspond.

FIG. 5shows an example of the configuration of the communication unit59inFIG. 2. The synchronization packets200are transmitted through an Ethernet communication unit93by a TCP procedure executed by a TCP transmission unit91, and the audio-video packets210are transmitted through the Ethernet communication unit93by a UDP procedure executed by a UDP transmission unit92.

FIG. 3shows an example of the configuration of one of the reproduction devices11to14inFIG. 1, for example, reproduction device11. The other reproduction devices12to14are configured identically.

The illustrated reproduction device has a communication unit101, a separation unit102, a clock generation unit103, the decoder104, an STC counter105, an STC comparator106, a frame synchronization counter107, a frame synchronization comparator108, a frequency control unit109, and a control unit110.

The clock generation unit103generates clock pulses C103with a given frequency, 27 MHz for example, to determine the timing of reproduction operations in the reproduction device11, in particular, the timing of decoding operations in the decoder104.

The illustrated clock generation unit103has a VCO121and a rectangular wave generation unit122.

The VCO (Voltage Controlled Oscillator)121can adjust its oscillation frequency in either the positive direction (higher frequency) or negative direction (lower frequency) according to an input voltage. The rectangular wave generation unit122generates square wave pulses with the oscillation frequency of the VCO.

The control unit110is formed of, for example, the CPU of a microcomputer, and controls the entire reproduction device. In particular, the control unit110controls the communication unit101, separation unit102, decoder104, STC comparator106, and frame synchronization comparator108. The signal lines for control signals supplied from the control unit110to each of these are omitted from the drawing.

The communication unit101receives digital data, more specifically, UDP packets including content data, and TCP packets including the SCR and FCR, transmitted from the distribution device10through the digital bus20, by, for example, the Ethernet protocol. TCP packets are received every 1/30 of a second.

The communication unit101extracts TS packets including audio and video data from the UDP packets, generates TS stream data, and supplies the generated TS stream data to the decoder104.

The communication unit101also supplies the TCP packets to the separation unit102.

The decoder104receives the TS stream data from the communication unit101and performs decoding on the basis of the clock pulses C103output from the clock generation unit103(with the timing being controlled by the clock pulses). When the content transmitted from the distribution device10is compressively encoded according to MPEG-2, the decoder104decodes the content according to MPEG-2.

The decoder104has a video decoder111and an audio decoder112. The video decoder111decodes TS stream data and reproduces a video picture, and the audio decoder112decodes TS stream data and reproduces sound. The output from the video decoder111is supplied to a screen display unit113, and the output from the audio decoder112is supplied to a speaker114.

The decoder104also supplies the frame synchronization counter107with frame timing signals included in the video signal reproduced by decoding.

The separation unit102separates the SCR data and FCR data from the synchronization packets200, which it receives as TCP packets from the communication unit101.

The separated SCR is supplied to the STC counter105and the STC comparator106. The separated FCR is supplied to the frame synchronization counter107and the frame synchronization comparator108.

The STC counter105, also referred to as a reference clock counter, counts the clock pulses generated by the clock generation unit103of the reproduction device11, and outputs a count value C105. Each time reproduction of each content transmitted from the distribution device10begins in the reproduction device11, the SCR separated by the separation unit102from the received synchronization packet200is set in the STC counter105as an initial value, and the STC counter105then counts the clock pulses C103output from the above clock generation unit103. The count value C105of the STC counter105therefore indicates elapsed time or reproduction time from the start of the content reproduced by the reproduction device11, and is supplied to the STC comparator106as elapsed time information STC (System Time Clock) generated in the reproduction device11.

The SCR data also indicate elapsed time from the start of the content. The SCR and the STC differ from each other in that the SCR is generated in the distribution device10and transmitted to the reproduction device11from the distribution device10whereas the STC is generated by counting the clock pulses output from the clock generation unit103in the reproduction device11. To distinguish the SCR and STC, the SCR will be referred to as reference data and the STC will be referred to as internal data (data generated in the reproduction device11).

The STC counter105is, for example, a 42-bit counter like the STC counter55in the distribution device10.

The frame synchronization counter107counts the number of video frames of the content reproduced by the reproduction device11, and outputs a count value C107. Each time reproduction of each content transmitted from the distribution device10begins in the reproduction device11, the FCR separated by the separation unit102from the received synchronization packet200is set in the frame synchronization counter107, as an initial value, and the frame synchronization counter107then increments the count value C107each time one frame is reproduced by the decoder104. More specifically, the count value C107is incremented on input of frame timing signals included in the video signal reproduced by the decoder54. The count value C107of the frame synchronization counter107therefore represents a frame number in the content reproduced by the reproduction device11(e.g., data indicating how many frames the current frame is from the start of the content), and is supplied to the frame synchronization comparator108as frame number data FTC (Frame Time Clock).

The FCR data also indicate frame numbers. The FCR and the FTC differ from each other in that the FCR is generated in the distribution device10and transmitted to the reproduction device11from the distribution device10whereas the FTC is generated by counting the number of frames reproduced by the decoder104in the reproduction device11. To distinguish the FCR and FTC, the FCR will be referred to as reference data and the FTC will be referred to as internal data (data generated in the reproduction device11).

The frame synchronization counter107is, for example, a 32-bit counter like the frame synchronization counter56in the distribution device10.

The frame synchronization comparator108calculates the difference ΔFTC between the FTC obtained from the frame synchronization counter107and the FCR separated by the separation unit102from the synchronization packet200. The difference ΔFTC is expressed by the following equation (1).
ΔFTC=FCR−FTC(1)

The calculation according to equation (1) is made, when, for example, the FTC value is updated (incremented), by using the FTC value at that time and the FCR value output from the separation unit102at that time. Alternatively, the calculation may be performed, when new FCR data are separated by the separation unit102, by using the FCR value at that time and the FTC value output from the frame synchronization counter107at that time.

Since the frame synchronization counters56, and107are, for example, 32-bit counters and their count values do not reach their maximum value while the content is being reproduced, the wrapping around of one of the count values from the maximum value to zero need not be considered.

When the difference AΔFTC obtained by equation (1) is negative, the output frequency of the clock generation unit103is adjusted downward. When the difference ΔFTC is positive, the output frequency of the clock generation unit103is adjusted upward.

The reproduction device11is thereby frame-synchronized to the distribution device10, and, as a result, frame synchronization can be obtained by a plurality of reproduction devices.

The STC comparator106calculates the difference ΔSTC between the STC from the STC counter105and the SCR separated by the separation unit102from the synchronization packet200. The calculation is performed, when, for example, new SCR data are separated by the separation unit102, by using the SCR value at that time and the STC value output from the STC counter105at that time.

The difference ΔSTC is normally obtained by the following equation.
ΔSTC=SCR−STC(2)

Because a single cycle lasts approximately 162 seconds in the STC counters55,105, calculations in the neighborhood of the timing at which the STC and SCR values wrap around from the maximum value MAX (=242−1=4,398,046,511,103) to zero have to be adjusted in consideration of the wrap-around. This point will be described below with reference toFIGS. 6 and 7.

FIGS. 6 and 7show cases in which the STC value and the SCR value are located on opposite sides of the boundary at which the count values wrap around from the maximum value MAX to zero.

When frames are synchronized, the difference between SCR and STC should be less than the count value (27×106÷30=9×105=Cf) corresponding to the 1/30-second duration of a single frame period. Therefore, ΔSTC is first calculated by equation (2), and if the absolute value of the calculated ΔSTC is equal to or less than Cf, the ΔSTC value obtained from equation (2) is output as the correct value. If the absolute value of the calculated ΔSTC is greater than Cf, the STC comparator106concludes that the STC and SCR values are located on opposite sides of the wraparound boundary from the maximum value MAX to zero, and carries out the following process.

First, if ΔSTC is greater than Cf, the STC comparator106concludes that the SCR value occurs just before the timing of the change from the maximum value MAX to zero as inFIG. 6, and is therefore close to the maximum value MAX, and that the STC value occurs just after the timing of the change from the maximum value MAX to zero, and is therefore close to zero, and recalculates the difference ΔSTC by the following equation (3).
ΔSTC=(SCR−MAX)−STC(3)

If the ΔSTC value calculated from equation (2) is less than −Cf, the STC comparator106concludes that the SCR value occurs just after the timing of the change from the maximum value MAX to zero as inFIG. 7, and is therefore close to zero, and that the STC value occurs just before the timing of the change from the maximum value MAX to zero, and is therefore close to the maximum value MAX, and recalculates the difference ΔSTC by the following equation (4).
ΔSTC=SCR−(STC−MAX)   (4)

When the difference ΔSTC obtained by equation (2), (3), or (4) is negative (this includes the case inFIG. 6), STC is found to lead SCR, and the output frequency of the clock generation unit103is adjusted downward.

When the difference ΔSTC obtained by equation (2), (3), or (4) is positive, (this includes the case inFIG. 7), STC is found to lag SCR, and the output frequency of the clock generation unit103is adjusted upward.

The frequency control unit109has DA conversion units131,132, a gain adjustment and combining unit133, and a low pass filter134.

DA conversion unit131converts the digital signal representing the difference ΔFTC output from the frame synchronization comparator108to an analog signal.

DA conversion unit132converts the digital signal representing the difference ΔSTC output from the STC comparator106to an analog signal.

The gain adjustment and combining unit133uses internal amplifiers or the like to adjust the gain of the output from DA conversion unit131(the analog signal converted from the difference ΔFTC output from the frame synchronization comparator108) and the gain of the output from DA conversion unit132(the analog signal converted from the difference ΔSTC output from the STC comparator106), combines the adjusted outputs, and generates an analog control signal (voltage waveform). The combining operation is performed by, for example, analog summing. The analog control signal generated by the gain adjustment and combining unit133is input to the low pass filter134.

The low pass filter134receives the output from the gain adjustment and combining unit133, removes its high-frequency component, and supplies the resultant signal to the VCO121. The high-frequency component of the output from the gain adjustment and combining unit133is removed in order to prevent the high-frequency component from causing rapid changes in the VCO121thereby to stabilize frequency control.

By the processing described above, the frequency control unit109controls the output frequency of the clock generation unit103on the basis of the differences ΔFTC and ΔSTC. As a result, the timing of decoding by the decoder104is controlled, and the display of a video picture by the screen display unit113and output of sound by the speaker114can be synchronized with the operation of the decoder54in the distribution device10.

The frame synchronization operation will be described with reference toFIGS. 8 and 9.

FIG. 8shows a case in which reproduction by the decoder104in reproduction device11is too fast. When the distribution device10transmits FCR values of Nt+2 and Nt+3, reproduction device11generates FTC values of Nt+3 and Nt+4, and the difference ΔFTC obtained by equation (1) is −1. In this case, as described above, reproduction by the decoder104is slowed by lowering the output frequency of the clock generation unit103, thereby restoring the frame offset to zero.

FIG. 9shows a case in which reproduction by the decoder104in reproduction device11is too slow. During the interval while reproduction device11generates an FTC value of Nt+2, at first an FCR value of Nt+2 is received from the distribution device10, in which case the frame number offset is zero, but next an FCR value of Nt+3 is received, and the difference ΔFTC obtained by equation (1) is +1. In this case, as described above, reproduction by the decoder104is sped up by raising the output frequency of the clock generation unit103, thereby restoring the frame offset to zero.

As described above, by control of the output frequency of the clock generation unit103according to the output from the frame synchronization comparator108, the displayed video offset can be held to within ±1 frame interval. The displayed video picture can also be more precisely synchronized by control of the output frequency of the clock generation unit103based on the output from the STC comparator106.

As a result of performing the above-described control in each reproduction device, reproduction by a plurality of reproduction devices can be synchronized. Synchronization is not lost even during lengthy reproduction.

Even when, in a state in which a first reproduction device is already reproducing a content, a second reproduction device is connected to the distribution device, synchronization between these reproduction devices can be secured. Even when a plurality of other reproduction devices are connected at different timings after the first, all the reproduction devices can be similarly synchronized.

In addition, when synchronization is lost, it can be recovered without skipping frames.

Second Embodiment

FIG. 10shows a reproduction device in the second embodiment of the invention.

The reproduction device inFIG. 10is generally the same as the reproduction device inFIG. 3, but with the following differences.

First, the reproduction device inFIG. 10lacks the DA conversion units131,132inFIG. 3.

The clock generation unit103, STC comparator106, frame synchronization counter107, frame synchronization comparator108, gain adjustment and combining unit133, and low pass filter134inFIG. 3are replaced by a clock generation unit103b, an STC comparator106b, a frame synchronization counter107b, a frame synchronization comparator108b, a gain adjustment and combining unit133b,and a low pass filter134bthat are configured in software, that is, in a programmed computer system.

The gain adjustment and combining unit133band low pass filter134bin the second embodiment constitute a frequency control unit109b.

Each of these elements in the second embodiment performs the same process as the corresponding element in the first embodiment (indicated by the same reference characters without the additional letter ‘b’).

The output from the gain adjustment and combining unit133b, however, is digital data indicating a result of combination. The low pass filter134bperforms low pass filtering (filtering in the time axis direction) on a time series of the digital data.

The clock generation unit103bis formed of a digitally controlled oscillator. The digitally controlled oscillator is configured in hardware, and can change its output frequency according to the output data (digital data) of the low pass filter134b.

The control unit110b, like the control unit110inFIG. 3, is formed of the CPU of a microcomputer. The functions of the elements configured in software as described above can all be implemented by the CPU of the control unit110b, but they are indicated as separate elements for convenience.

The operation of the STC comparator106band gain adjustment and combining unit133bis similar to the operation of the STC comparator106and gain adjustment and combining unit133, respectively, but the operation of the STC comparator106band gain adjustment and combining unit133bwill be described below with reference to flowcharts.

First, the operation of the STC comparator106bwill be described with reference toFIG. 11.

First, the STC comparator106breads the SCR output from the separation unit102(step ST101).

Next, it reads the STC from the STC counter104b(step ST102).

Next, STC is subtracted from SCR to obtain the difference ΔSTC (step ST103).

If the result of the comparison in step ST104is that ΔSTC is greater than Cf, the STC comparator106bproceeds to step ST105, recalculates the difference ΔSTC by equation (3) above, that is, by the equation below, and proceeds to step ST107.
ΔSTC=(SCR−MAX)−STC

If the result of the comparison in step ST104is that ΔSTC is less than −Cf, the STC comparator106bproceeds to step ST105, recalculates the difference ΔSTC by equation (4) above, that is, by the equation below, and proceeds to step ST107.
ΔSTC=SCR−(STC−MAX)

If ΔSTC is equal to or greater than −Cf and equal to or less than Cf in step ST104, that is, if |ΔSTC|≤Cf, the STC comparator106bproceeds immediately to step ST107.

In step ST107, the STC comparator106boutputs the difference ΔSTC.

The difference ΔSTC is supplied to the gain adjustment and combining unit133bas in the first embodiment.

In the first embodiment, the difference ΔSTC undergoes DA conversion by the DA conversion unit132and is then supplied to the gain adjustment and combining unit133. In the second embodiment, the difference ΔSTC is supplied directly to the gain adjustment and combining unit133bwithout undergoing DA conversion.

Next, the operation of the gain adjustment and combining unit133bwill be described with reference toFIG. 12.

First, the gain adjustment and combining unit133breads ΔFTC from the frame synchronization comparator108b(ST201).

Next, it determines whether or not ΔFTC is zero (ST202).

If ΔFTC is not zero, the gain adjustment and combining unit133bproceeds to step ST203and obtains the combination result D133by multiplying ΔFTC by a given coefficient k1.

If ΔFTC is zero, in step ST202, the gain adjustment and combining unit133bproceeds to step ST204and reads ΔSTC from the STC comparator106b. Then in step ST205, the combination result D133is obtained by multiplying ΔSTC by a given coefficient k2.

The combination result D133is output after step ST203or ST205. The combination result D133is supplied to the clock generation unit103bthrough the low pass filter134bas a frequency control signal.

The output frequency of the clock generation unit103bis controlled according to the frequency control signal supplied through the low pass filter134b.

Other than the differences described above, the operation of the second embodiment is the same as the operation of the first embodiment.

Advantages of the configuration of the second embodiment are that gain adjustment can be performed easily by modifying software, and high-precision control is possible.

Third Embodiment

FIGS. 13 and 14show a digital data distribution device and a digital data reproduction device in the third embodiment of the invention. These can be used respectively as the distribution device10and the reproduction devices11to14in the system shown inFIG. 1.

The distribution device inFIG. 13is generally the same as the distribution device inFIG. 2, and the same or similar elements are indicated by the same reference characters.

The distribution device inFIG. 13differs in that the decoder54inFIG. 2has been replaced with a different decoder64, and the multiplexing unit57and transmission processing unit58inFIG. 2have been replaced with an encoder67.

The decoder64inFIG. 13is generally the same as the decoder54inFIG. 2, but a plurality of frames of content data are organized into a GOP (group of pictures) and the content data are compressively encoded, taking each GOP as a unit, and when the content is decoded, the count value C56of the frame synchronization counter56and the count value C55of the STC counter55are output as the FCR value and the SCR value, respectively, only for a representative frame in each GOP, for example, the first frame in the GOP.

The encoder67compressively encodes the data decoded by the decoder64to generate stream data (encoded data) in units of GOPs, and inserts the SCR output from the STC counter55and the FCR output from the frame synchronization counter56into the GOP header at the start of the GOP. The stream data in units of GOPs are then packetized, i.e., converted to UDP packets.

The reproduction device inFIG. 14is generally the same as the reproduction device inFIG. 3, and the same or similar elements are indicated by the same reference characters.

The reproduction device inFIG. 14differs in that the separation unit102inFIG. 3has been replaced with a GOP separation unit142.

Since the stream data in units of GOPs including the FCR and SCR are transmitted from the distribution device to the reproduction device after having been packetized, the reproduction device receives data representing audio and video together with the FCR and SCR used for synchronization.

The GOP separation unit142separates the FCR and SCR embedded by the distribution device from the GOP header in the transmitted packet data.

For each GOP, the frame synchronization comparator108compares the FCR with the FTC and the STC comparator106compares the SCR with the STC. Since each GOP consists of, for example, 15 frames, these comparisons are performed, for example, once every 15 frames.

Other than the differences described above, the configuration and operation of the third embodiment are the same as the configuration and operation of the first embodiment. As will be understood from the third embodiment, the invention is not limited to configurations in which data indicating a frame number and elapsed time are transmitted from a distribution device to a reproduction device for each of the frames constituting a video content, and the reproduction device also generates data indicating a frame number and elapsed time for each of the frames constituting the video content, compares the generated data with the corresponding data transmitted from the transmitting device, and controls the output frequency of its clock generation unit on the basis of the comparison result; configurations in which the distribution device transmits data indicating a frame number and elapsed time to the reproduction device for at least some frames constituting the video content (for example, once every given number of frames), and the reproduction device generates data indicating a frame number and elapsed time for at least some of the frames constituting the video content (the same frames for which the distribution device generates data indicating the above frame number and elapsed time), compares the generated data with the corresponding data transmitted from the transmitting device, and controls the output frequency of the clock generation unit on the basis of the comparison result.

A distribution device according to the invention, a reproduction device according to the invention, and a reproduction system including these devices have been described above, but the invention also includes the distribution method and the reproduction method implemented by these devices and the system. In addition, the invention also includes programs for causing a computer to execute the functions and processes carried out in these devices, the system, or these methods, and a computer readable recording medium on which such a program is recorded.

REFERENCE CHARACTERS