SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING

A semiconductor arrangement and method of forming the semiconductor arrangement are provided. The semiconductor arrangement includes a first conductive layer and a first dielectric layer over the first conductive layer. A second conductive layer is over a portion of the first dielectric layer and has a sidewall surface. A spacer is over a portion of the sidewall surface of the second conductive layer and covers an interface between the second conductive layer and the first dielectric layer.

BACKGROUND

Capacitors are useful to, among other things, store electrical charge within circuits.

DETAILED DESCRIPTION

One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. According to some embodiments, a capacitor comprises conductive layers and dielectric layers arranged in a stack. In some embodiments, the capacitor is a trench capacitor. Portions of a first conductive layer and a first dielectric layer are removed to expose a second conductive layer under the first conductive layer and the first dielectric layer so that a contact can be formed to contact the second conductive layer. According to some embodiments, during an etch process to remove the first conductive layer and the first dielectric layer, a precursor gas is added to the etch mixture to cause a spacer to form on sidewalls of the first conductive layer. In some embodiments, the precursor gas comprises a halogen gas, and the spacer formed during the etch process comprises a metal halide material. The spacer covers and protects the sidewall of the first conductive layer at an interface where the first conductive layer contacts the first dielectric layer to reduce erosion of the first dielectric layer during the etch process or a subsequent process, such as an ashing process and/or a cleaning process. In some embodiments, the spacer covers and protects the sidewall of the first conductive layer at a first interface where the first conductive layer contacts the first dielectric layer under the first conductive layer and at a second interface where the first conductive layer contacts a second dielectric layer over the first conductive layer. Reducing erosion of the dielectric material (e.g., the first dielectric layer and/or the second dielectric layer) reduces leakage current, increases capacitance of the capacitor, and reduces defects in the capacitor, such as a short between the first conductive layer and the second conductive layer.

FIG. 1is a top view illustrating a portion of a semiconductor arrangement100according to some embodiments. In some embodiments, the semiconductor arrangement100comprises capacitors105, such as trench capacitors, arranged in groups110A,110B. In some embodiments, the groups110A,110B are arranged in a grid format, where adjacent groups110A,110B are rotated 90 degrees with respect to one another. Material formed in a trench can exert stress on structures adjacent the trench. Providing the groups110A,110B with different orientations results in the stress being directed in different directions, thereby reducing the likelihood of warping occurring on a substrate layer on which the capacitors105are formed.

Referring toFIG. 2, a cross section view of the semiconductor arrangement100is provided. In some embodiments, the capacitor105is formed in trenches200A,200B formed in a substrate layer205. In some embodiments, the substrate layer205comprises at least one of an epitaxial layer, a single crystalline semiconductor material, such as, but not limited to, at least one of Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, or InP, a silicon-on-insulator (all) structure, a wafer, or a die formed from a wafer. In some embodiments, the substrate layer205comprises at least one of crystalline silicon or other suitable materials. Other structures and/or configurations of the substrate layer205are within the scope of the present disclosure.

In an embodiment, the trenches200A,200B are formed in the substrate layer205. In some embodiments, the trenches200A,200B are formed by forming at least one mask layer over the substrate layer205. In some embodiments, the mask layer comprises a layer of oxide material over the substrate layer205, a layer of nitride material over the layer of oxide material, and/or one or more other suitable layers. At least some of the material of the mask layer is removed to define an etch mask for use as an etch template to etch the substrate layer205to form the trenches200A,200B. The number of trenches200A,200B formed in the substrate layer205may vary. In the illustration ofFIG. 2, the capacitor105is formed in two trenches in the substrate layer205. Other structures and configurations of the capacitor105are within the scope of the present disclosure. For example, any number of trenches200A,200B may be employed to form a single capacitor105or a group110A,110B of capacitors105.

Referring toFIG. 2, the capacitor105is formed by forming a dielectric layer210in the trenches200A,200B. In some embodiments, the dielectric layer210comprises silicon dioxide, silicon nitride, or other suitable dielectric materials. In some embodiments, the dielectric layer210is formed by at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), or other suitable techniques. In some embodiments, the dielectric layer210electrically isolates the capacitor105from the substrate layer205.

According to some embodiments, a conductive layer215A is formed over the dielectric layer210. In some embodiments, the conductive layer215A comprises a conductive material, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tungsten (W), iridium (Jr), rubidium (Ru), platinum (Pt), aluminum (Al), copper (Cu), and/or other suitable materials or combinations of suitable materials. In some embodiments, the conductive layer215A is formed by at least one of ALD, PVD, CVD, thermal evaporation, and/or other suitable techniques.

In some embodiments, a dielectric layer220A is formed over the conductive layer215A. In some embodiments, the dielectric layer220A comprises a high-k dielectric material. As used herein, the term “high-k dielectric” refers to the material having a dielectric constant, k, greater than or equal to about 3.9, which is the k value of SiO2. The high-k dielectric material may be any suitable material. Examples of the high-k dielectric material include but are not limited to Al2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, Al2OxNy, HfOxNy, ZrOxNy, La2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNX, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2. According to some embodiments, the dielectric layer220A is formed by thermal growth, chemical growth, ALD, CVD, plasma-enhanced chemical vapor deposition (PECVD), and/or other suitable techniques.

According to some embodiments, a conductive layer215B is formed over the dielectric layer220A, a dielectric layer220B is formed over the conductive layer215B, a conductive layer215C is formed over the dielectric layer220B, a dielectric layer220C is formed over the conductive layer215C, a conductive layer215D is formed over the dielectric layer220C, and a dielectric layer220D is formed over the conductive layer215D. In some embodiments, a dielectric layer225is formed over the dielectric layer220D to fill the trenches and extend above the upper surface of the dielectric layer220D.

In some embodiments, the conductive layers215A,215B,215C,215D have the same material composition. In some embodiments, a thickness of the conductive layers215A,215B,215C,215D is approximately the same. In some embodiments, the material composition of at least one of the conductive layers215A,215B,215C,215D may be different than the material composition of another at least one of the conductive layers215A,215B,215C,215D and/or the thickness of at least one of the conductive layers215A,215B,215C,215D may be different than may be different than the thickness of another at least one of the conductive layers215A,215B,215C,215D. The material composition and/or thickness of the conductive layers215A,215B,215C,215D may be selected based upon, among other things, specified parameters, such as capacitance of the capacitor105. In some embodiments, the thickness of one of the conductive layers215A,215B,215C,215D is between about 100 and 300 angstroms. In some embodiments, the thickness of one of the conductive layers215A,215B,215C,215D is about 200 angstroms. In some embodiments, the dielectric layers220A,220B,220C,220D have the same material composition. In some embodiments, a thickness of the dielectric layers220A,220B,220C,220D is approximately the same. In some embodiments, the thickness of one of the dielectric layers220A,220B,220C,220D is about between about 40 and 100 angstroms. In some embodiments, the thickness of one of the dielectric layers220A,220B,220C,220D is about 70 angstroms. In some embodiments, the material composition of at least one of the dielectric layers220A,220B,220C,220D may be different than the material composition of another at least one of the dielectric layers220A,220B,220C,220D and/or the thickness of at least one of the dielectric layers220A,220B,220C,220D may be different than may be different than the thickness of another at least one of the dielectric layers220A,220B,220C,220D. The material composition and/or thickness of the dielectric layers220A,220B,220C,220D may be selected based upon, among other things, specified parameters, such as capacitance of the capacitor105.

In some embodiments, the capacitor105includes five trenches200A,200B and occupies a space of about 100 micrometers. In some embodiments, an aspect ratio of the trenches200A,200B is about 1:5 or higher. In some embodiments, the number of conductive layers215A,215B,215C,215D and dielectric layers220A,220B,220C,220D in the capacitor105varies. In some embodiments, the capacitor105comprises at least two conductive layers215A,215B,215C,215D and at least two dielectric layers220A,220B,220C,220D.

FIGS. 3A-3Pare cross-section views of the semiconductor arrangement100at various stages of fabrication, in accordance with some embodiments. Referring toFIG. 3, a portion of the capacitor105over a horizontal portion of the dielectric layer210and adjacent the trenches200A,200B is illustrated.

Referring toFIG. 3A, a mask300is formed over the dielectric layer225, according to some embodiments. In some embodiments, the mask300comprises a photoresist layer. In some embodiments, the photoresist layer is formed by at least one of spinning, spray coating, or other suitable techniques. The photoresist is a negative photoresist or a positive photoresist. With respect to a negative photoresist, regions of the negative photoresist become insoluble when illuminated by a light source, such that application of a solvent to the negative photoresist during a subsequent development stage removes non-illuminated regions of the negative photoresist. A pattern formed in the negative photoresist is thus a negative image of a pattern defined by opaque regions of a template, such as a mask, between the light source and the negative photoresist. In a positive photoresist, illuminated regions of the positive photoresist become soluble and are removed via application of a solvent during development. Thus, a pattern formed in the positive photoresist is a positive image of opaque regions of the template, such as a mask, between the light source and the positive photoresist. One or more etchants have a selectivity such that the one or more etchants remove or etch away one or more layers exposed or not covered by the photoresist at a greater rate than the one or more etchants remove or etch away the photoresist. Accordingly, an opening in the photoresist allows the one or more etchants to form a corresponding opening in the one or more layers under the photoresist, and thereby transfer a pattern in the photoresist to the one or more layers under the photoresist. The photoresist is ashed, stripped, or washed away after the pattern transfer.

Referring toFIG. 3B, the mask300is used as an etch template to remove exposed portions of the dielectric layer225and the dielectric layer220D, according to some embodiments. In some embodiments, one or more etch processes are performed using etch chemistries that remove the material of the dielectric layer225and the dielectric layer220D to expose the conductive layer215D. In some embodiments, the conductive layer215D is an etch stop layer for the etch process that removes the dielectric layer220D.

Referring toFIGS. 3C, 3D, and 3E, the mask300is used as an etch template to remove exposed portions of the conductive layer215D, according to some embodiments. In some embodiments, an etch process302is performed using an etch chemistry that removes the material of the conductive layer215D. In some embodiments, the etch process comprises a reactive ion etch using a carbon tetrafluoride (CF4) etch gas or other suitable etch gas. In some embodiments, a precursor gas comprising a halogen is added to the etch gas during at least one phase of the etch process302. In some embodiments, the halogen comprises at least one of fluorine, chlorine, bromine, or another suitable material.FIGS. 3C, 3D, and 3Eshow the etch process302as the etch front progresses through the conductive layer215B. According to some embodiments, the halogen reacts with material of the conductive layer215D during the etch process to form a metal halide material that deposits on a portion of the sidewall surface305of the conductive layer215D to form a spacer310. As used herein the language regarding covering “a portion” of a sidewall surface includes covering the entire sidewall surface. In an embodiment where the material of the conductive layer215D is TiN and the halogen precursor gas is fluorine, the spacer310comprises the metal halide, titanium tetrafluoride (TiF4). The spacer310can comprise other metal halide materials if different conductive materials and/or halogen precursor gases are used. In some embodiments, the metal halide formed during the etch process302has a sublimation point or boiling point of at least around 130° C. to 230° C. In some embodiments, a portion of the metal halide generated during the etch process is volatile and is exhausted from the etch chamber. However, the etch process302also includes a redepositing component304, where a portion of the metal halide is sputtered during the etch process302and deposits on the sidewall surface305of the conductive layer215D to form the spacer310. In some embodiments, the dielectric layer220C is an etch stop layer for the etching of the conductive layer215D.

In some embodiments, the spacer310covers a sidewall interface312defined by the sidewall surface305of the conductive layer215D and a sidewall surface320of the dielectric layer220D. In some embodiments, the height H1and/or thickness T1of the spacer310are controlled by the ratio of halogen gas to etching gas. Increasing the amount of halogen gas increases the amount of metal halide material that forms and deposits during the redepositing component304to form the spacer310. In some embodiments, the spacer310covers a portion of a sidewall surface of the dielectric layer220C. Referring toFIG. 3E, after the completion of the etch process302, the spacer310covers a corner interface315defined where the conductive layer215D contacts an upper surface of the dielectric layer220C. In some embodiments, the thickness, T1, of the spacer310is between about 0.3 and 0.7 micrometers. In some embodiments, the thickness, T1, of the spacer310is 0.5 micrometers or less.

Referring toFIG. 3F, the mask300is removed according to some embodiments. In some embodiments, the mask300is removed by performing a removal process325. In some embodiments, the removal process325comprises an oxygen plasma strip process. In some embodiments, the removal process325also includes a cleaning process, such as a diluted hydrofluoric acid (DHF) wet cleaning process, to remove residue from the oxygen plasma strip process. The spacer310protects the dielectric layers220C,220D from erosion during the removal process325at the corner interface315and the sidewall interface312, respectively. In some embodiments, a portion of the spacer310is removed during the removal process325, and the height H1and/or the thickness T1may be reduced.

Referring toFIG. 3G, a mask330is formed over the dielectric layer225, the dielectric layer220D, the conductive layer215D, the spacer310, and a portion of the dielectric layer220C, according to some embodiments. In some embodiments, the mask330comprises a photoresist layer. In some embodiments, the photoresist layer is formed by at least one of spinning, spray coating, or other suitable techniques. The photoresist is patterned using a positive or negative technique to form the mask330.

Referring toFIG. 3H, the mask330is used as an etch template to remove exposed portions of the dielectric layer220C, according to some embodiments. In some embodiments, an etch process is performed using an etch chemistry that removes the material of the exposed portions of the dielectric layer220C to expose the conductive layer215C. In some embodiments, the conductive layer215C is an etch stop layer for the etch process that removes the dielectric layer220C.

Referring toFIG. 3I, the mask330is used as an etch template to remove exposed portions of the conductive layer215C, according to some embodiments. In some embodiments, an etch process332is performed using an etch chemistry that removes the material of the conductive layer215C. In some embodiments, the etch process332comprises a reactive ion etch using a carbon tetrafluoride (CF4) etch gas or other suitable etch gas. In some embodiments, a precursor gas comprising a halogen is added to the etch gas during at least one phase of the etch process332. In some embodiments, the halogen comprises at least one of fluorine, chlorine, bromine, or another suitable material. In some embodiments, the halogen in the precursor gas for the etch process332is the same halogen used for the etch process302. In some embodiments, a different halogen is used in the etch process332. According to some embodiments, the halogen reacts with material of the conductive layer215C during the etch process332to form a metal halide material that deposits on a sidewall surface335of the conductive layer215C to form a spacer340. In some embodiments, the etch process332includes a redepositing component334, where a portion of the metal halide is sputtered during the etch process332and deposits on the sidewall surface335of the conductive layer215C to form the spacer340. In some embodiments, the dielectric layer220B is an etch stop layer for the etching of the conductive layer215C. The etch process332progresses as illustrated inFIGS. 3C-3Eto form the spacer340.

In some embodiments, the spacer340covers at least a portion of the sidewall surface335of the conductive layer215C at a corner interface345where the conductive layer215C contacts an upper surface of the dielectric layer220B. In some embodiments, the spacer340covers a sidewall interface342defined by the sidewall surface335of the conductive layer215C and a sidewall surface350of the dielectric layer220C. In some embodiments, the spacer340covers a portion of a sidewall surface of the mask330. In some embodiments, the height H2and/or thickness T2of the spacer340are controlled by the ratio of halogen gas to etching gas. Increasing the amount of halogen gas increases the amount of metal halide material that forms and deposits to form the spacer340. In some embodiments, the thickness, T2, of the spacer310is between about 0.3 and 0.7 micrometers. In some embodiments, the thickness, T2, of the spacer310is 0.5 micrometers or less.

Referring toFIG. 3J, the mask330is removed according to some embodiments. In some embodiments, the mask330is removed by performing a removal process355. In some embodiments, the removal process355comprises an oxygen plasma strip process. In some embodiments, the removal process355also includes a cleaning process, such as a DHF wet cleaning process, to remove residue from the oxygen plasma strip process. The spacer340protects the dielectric layers220B,220C from erosion during the removal process355. In some embodiments, after removal of the mask330, a portion of a sidewall surface340S of the spacer340is exposed. In some embodiments, a portion of the spacer340is removed during the removal process355, and the height H2and/or the thickness T2may be reduced.

Referring toFIG. 3K, a mask360is formed over the dielectric layer225, the dielectric layers220C,220D, the conductive layers215C,215D, the spacers310,340and a portion of the dielectric layer220B, according to some embodiments. In some embodiments, the mask360comprises a photoresist layer. In some embodiments, the photoresist layer is formed by at least one of spinning, spray coating, or other suitable techniques. The photoresist is patterned using a positive or negative technique to form the mask360.

Referring toFIG. 3L, the mask360is used as an etch template to remove exposed portions of the dielectric layer220B, according to some embodiments. In some embodiments, an etch process is performed using an etch chemistry that removes the material of the exposed portions of the dielectric layer220B to expose the conductive layer215B. In some embodiments, the conductive layer215B is an etch stop layer for the etch process that removes the dielectric layer220B.

Referring toFIG. 3M, the mask360is used as an etch template to remove exposed portions of the conductive layer215B, according to some embodiments. In some embodiments, an etch process362is performed using an etch chemistry that removes the material of the conductive layer215B. In some embodiments, the etch process362comprises a reactive ion etch using a carbon tetrafluoride (CF4) etch gas or other suitable etch gas. In some embodiments, a precursor gas comprising a halogen is added to the etch gas during at least one phase of the etch process362. In some embodiments, the halogen comprises at least one of fluorine, chlorine, bromine, or another suitable material. In some embodiments, the halogen in the precursor gas for the etch process362is the same halogen used for the etch process302or the etch process332. In some embodiments, a different halogen is used in the etch process362compared to the halogen(s) used in the etch processes302,332. According to some embodiments, the halogen reacts with material of the conductive layer215B during the etch process362to form a metal halide material that deposits on a sidewall surface365of the conductive layer215B to form a spacer370. In some embodiments, the etch process332includes a redepositing component364, where a portion of the metal halide is sputtered during the etch process362and deposits on the sidewall surface365of the conductive layer215B to form the spacer370. In some embodiments, the dielectric layer220A is an etch stop layer for the etching of the conductive layer215B.

In some embodiments, the spacer370covers at least a portion of the sidewall surface365of the conductive layer215B at a corner interface375where the conductive layer215B contacts an upper surface of the dielectric layer220A. In some embodiments, the spacer370covers a sidewall interface372defined by the sidewall surface365of the conductive layer215B and a sidewall surface380of the dielectric layer220B. In some embodiments, the spacer370covers a portion of a sidewall surface of the mask360. In some embodiments, the height H3and/or thickness T3of the spacer370is controlled by the ratio of halogen gas to etching gas. Increasing the amount of halogen gas increases the amount of metal halide material that forms and deposits to form the spacer340. In some embodiments, the thickness, T3, of the spacer310is between about 0.3 and 0.7 micrometers. In some embodiments, the thickness, T3, of the spacer310is 0.5 micrometers or less.

Referring toFIG. 3N, the mask360is removed according to some embodiments. In some embodiments, the mask360is removed by performing a removal process385. In some embodiments, the removal process385comprises an oxygen plasma strip process. In some embodiments, the removal process385also includes a cleaning process, such as a DHF wet cleaning process, to remove residue from the oxygen plasma strip process. The spacer370protects the dielectric layers220A,220B from erosion during the removal process385. In some embodiments, after removal of the mask360, the portion of the sidewall surface370S of the spacer370and a portion of a sidewall surface370S of the spacer370are exposed. In some embodiments, a portion of the sidewall spacer380is removed during the removal process385, and the height H3and/or the thickness T3may be reduced.

Referring toFIG. 3O, a dielectric layer390is formed over the capacitor105and an interconnect structure395is formed in the dielectric layer390, according to some embodiments. In some embodiments, the interconnect structure395comprises a line portion395L and a via portion395V. In some embodiments, the interconnect structure395is formed in any number of ways, such as by a single damascene process, a dual damascene process, a trench silicide process, and/or other suitable techniques. In some embodiments, additional contacts (not shown) are formed to contact the capacitor105at different positions, such as into or out of the page or to the left of the portion of the capacitor105illustrated inFIG. 3O. In some embodiments, the interconnect structure395comprises a barrier layer, a seed layer, a metal fill layer, and/or other suitable layers. In some embodiments, the metal fill layer comprises tungsten, aluminum, copper, cobalt, and/or other suitable materials. Other structures and/or configurations of the interconnect structure395are within the scope of the present disclosure. In some embodiments, the via portions395V of the interconnect structure395contact the conductive layers215A,215C.

FIG. 3Pillustrates the semiconductor arrangement100after the processing ofFIGS. 3A-3O, according to some embodiments. In some embodiments, an interconnect structure397is formed on the side of the capacitor105opposite the interconnect structure395. In some embodiments, the interconnect structure contacts the conductive layers215B,215D. The configuration of the interconnect structures395,397depends on the interconnections between the conductive layers215A,215B,215C,215D to form the capacitor. For example, to form a set of parallel capacitors in the capacitor105, a power supply voltage, VDD, is applied to the conductive layers215A,215C using the interconnect structure395and a reference supply voltage, VSS, is applied to the conductive layers215B,215D using the interconnect structure397.

To form a set of series capacitors in the capacitor105, the power supply voltage, VDD, is applied to the conductive layer215A and the reference supply voltage, VSS, is applied to the conductive layer215D. For example, the via of the interconnect structure395contacting the conductive layer215C may be omitted, the via of the interconnect structure397contacting the conductive layer215B may be omitted, VDDmay be applied to the interconnect structure397, and VSSmay be applied to the interconnect structure395. Thus, embodiments where a set of series capacitors are to be formed, interconnect structures may be provided that connect to the conductive layers215A,215D to provide the VDDand VSSvoltages, respectively (instead of connecting a single interconnect structure to the conductive layers215A,215C as shown inFIG. 3O).

FIG. 4is a flow diagram illustrating a method400for forming a semiconductor arrangement100, in accordance with some embodiments. At402, a first conductive layer215A is formed over a substrate layer205. At404, a first dielectric layer220A is formed over the first conductive layer215A. At406, a second conductive layer215B is formed over the first dielectric layer220A. At408, a first mask360is formed over a first portion of the second conductive layer215B. At410, a first etch process is performed using the first mask360as an etch template to remove a second portion of the second conductive layer215B and define a sidewall surface265of the second conductive layer215B. At412, a phase of the first etch process is performed in the presence of a halogen precursor gas to form a first spacer370over a portion of the sidewall surface265and cover a corner interface375between the second conductive layer215B and the first dielectric layer220A.

Still another embodiment involves a computer-readable medium comprising processor-executable instructions configured to implement one or more of the techniques presented herein. An exemplary computer-readable medium is illustrated inFIG. 5, wherein the embodiment 500 comprises a computer-readable medium502(e.g., a CD-R, DVD-R, flash drive, a platter of a hard disk drive, etc.), on which is encoded computer-readable data504. This computer-readable data504in turn comprises a set of processor-executable computer instructions506configured to operate according to one or more of the principles set forth herein. In some embodiments 500, the processor-executable computer instructions506are configured to perform a method508, such as at least some of the aforementioned methods. In some embodiments, the processor-executable computer instructions506are configured to implement a system, such as at least some of the aforementioned systems. Many such computer-readable media may be devised by those of ordinary skill in the art that are configured to operate in accordance with the techniques presented herein.

FIG. 6depicts an example of a system600comprising a computing device602to implement some embodiments provided herein. In some configurations, the computing device602includes at least one processing unit604and memory606. Depending on the exact configuration and type of computing device, the memory606may be volatile (such as random access memory (RAM), for example), non-volatile (such as read-only memory (ROM), flash memory, etc., for example) or some combination of the two. This configuration is illustrated inFIG. 7by dashed line608.

In some embodiments, the computing device602may include additional features and/or functionality. For the example, the computing device602may also include additional storage (e.g., removable and/or non-removable) including, but not limited to, magnetic storage, optical storage, and the like. Such additional storage is illustrated inFIG. 6by storage610. In some embodiments, computer readable instructions to implement one or more embodiments provided herein may be in the storage610. The storage610may also store other computer readable instructions to implement an operating system, an application program, and the like. Computer readable instructions may be loaded in the memory606for execution by the at least one processing unit604, for example.

In some embodiments, the computing device602comprises a communication interface612, or multiple communication interfaces, that allow the computing device602to communicate with other devices. The communication interface612may include, but is not limited to, a modem, a Network Interface Card (NIC), an integrated network interface, a radio frequency transmitter/receiver, an infrared port, a Universal Serial Bus (USB) connection, or other interface for connecting the computing device602to other computing devices. The communication interface612may implement a wired connection or a wireless connection. The communication interface612may transmit and/or receive communication media.

The computing device602may include input device(s)614such as keyboard, mouse, pen, voice input device, touch input device, infrared cameras, video input devices, and/or any other suitable input device. An output device(s)616such as one or more displays, speakers, printers, and/or any other suitable output device may also be included in the computing device602. The input device(s)614and the output device(s)616may be connected to the computing device602via a wired connection, wireless connection, or any combination thereof. In some embodiments, an input device or an output device from another computing device may be used as the input device(s)614or the output device(s)616for the computing device602.

Components of the computing device602may be connected by various interconnects, such as a bus. Such interconnects may include a Peripheral Component Interconnect (PCI), such as PCI Express, a USB, firewire (IEEE 1394), an optical bus structure, and the like. In some embodiments, components of the computing device602may be interconnected by a network. For example, the memory606may be comprised of multiple physical memory units located in different physical locations interconnected by a network.

Those skilled in the art will realize that storage devices utilized to store computer readable instructions may be distributed across a network. For example, a computing device618accessible via a network620may store computer readable instructions to implement one or more embodiments provided herein. The computing device602may access the computing device618and download a part or all of the computer readable instructions for execution. Alternatively, the computing device602may download pieces of the computer readable instructions, as needed, or some instructions may be executed at the computing device602and some instructions may be executed at the computing device618.

Providing the spacer310,340,370over interfaces between conductive layers215A,215B,215C,215D and dielectric layers220A,220B,220C,220D when performing mask removal and cleaning processes protects the dielectric layers220A,220B,220C,220D from erosion. Reducing erosion of the dielectric material of the dielectric layers220A,220B,220C,220D reduces leakage current, increases capacitance of the capacitor, and reduces defects in the capacitor, such as a short between conductive layers.

According to some embodiments, a method of forming a semiconductor arrangement includes forming a first conductive layer over a substrate layer. A first dielectric layer is formed over the first conductive layer. A second conductive layer is formed over the first dielectric layer. A first mask is formed over a first portion of the second conductive layer. A first etch process is performed using the first mask as a template to remove a second portion of the second conductive layer and define a sidewall surface of the second conductive layer. Performing the first etch process includes comprises performing a phase of the first etch process in the presence of a halogen precursor gas to form a first spacer over a portion of the sidewall surface and cover an interface between the second conductive layer and the first dielectric layer.

According to some embodiments, a semiconductor arrangement includes a first conductive layer and a first dielectric layer over the first conductive layer. A second conductive layer is over a portion of the first dielectric layer and has a sidewall surface. A spacer is over a portion of the sidewall surface of the second conductive layer and covers an interface between the second conductive layer and the first dielectric layer. The first conductive layer, the first dielectric layer, and the second conductive layer define a capacitor.

According to some embodiments, a capacitor includes a first metal layer comprising a first metal, a second metal layer, a first dielectric layer between the first metal layer and the second metal layer, and a spacer comprising a metal halide. The metal halide comprises the first metal. The spacer covers an interface between the first dielectric layer and the first metal layer or the second metal layer.

The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand various aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of various embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

It will be appreciated that layers, features, elements, etc., depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers, regions, features, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques, growth techniques, or deposition techniques such as chemical vapor deposition (CVD), for example.

Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others of ordinary skill in the art based upon a reading and understanding of this specification and the annexed drawings. The disclosure comprises all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.