Metal-insulator-semiconductor transistors with gate-dielectric/semiconductor interfacial protection layer

Structures, devices and methods are provided for forming an interface protection layer (204) adjacent to a fully or partially recessed gate structure (202) of a group III nitride, a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) device or a metal-insulator-semiconductor field-effect transistor (MIS-FET) device, and forming agate dielectric (114) disposed the interface protection layer (204).

TECHNICAL FIELD

The subject disclosure is directed to metal-insulator-semiconductor transistors and, more specifically, to structures, devices, and methods for creating an interfacial protection layer in metal-insulator-semiconductor transistors.

BACKGROUND

Group III-nitride (III-N) compound semiconductor materials, (e.g., GaN, etc.) comprise wide energy bandgap, high breakdown electrical field, and high thermal conductivity. In addition, typical wide-bandgap heterostructure systems, such as those incorporating AlGaN/GaN heterostructures, enhanced by the spontaneous and piezoelectric polarization effects, yield two-dimensional electron gas (2DEG) channels with a high sheet charge concentration and high electron mobility. Accordingly, group III-N-based devices, such as GaN-based devices, for example, can provide enhancement-mode metal-insulator-semiconductor (MIS-) field-effect transistors (FETs) for high-performance power conversion systems.

GaN metal-insulator-semiconductor (MIS-) field-effect transistor (FET) with fully recessed gate (e.g., with the barrier layer completely removed) shows promise for high-frequency power switching applications for its enhancement-mode (E-mode) operation, and its capability in providing large forward gate voltage swing, which enables strong immunity to large positive voltage overshoot spikes. By partially recessing the barrier layer at the gate foot area of a recessed gate structure a conventional GaN MIS-HEMTs (high-electron-mobility transistors) can be transformed from depletion-mode to enhancement-mode (E-mode), which is preferred for fail-safe operation and simpler gate control and driver configuration. To suppress gate leakage current, a gate dielectric can be formed between the gate electrode and the semiconductor or channel layer under gate electrode, and a large conduction band offset between gate dielectric and the semiconductor or channel layer can suppress gate leakage.

However, despite desirable enhanced gate swing and lower gate leakage, commercialization of recessed-gate E-mode III-N MIS-FET has been hindered due to concerns over complications regarding voltage stability and gate dielectric reliability. It is difficult for conventional gate dielectric deposition processes such as plasma-enhanced atomic layer deposition (PEALD) or plasma-enhanced chemical vapor deposition (PECVD) to pass reliability tests and qualifications.

Conventional commercialized enhancement-mode GaN devices features p-type GaN layer on top of AlGaN/GaN heterojunction. The p-GaN layer can effectively raise the energy band of the heterojunction and deplete the 2DEG channel at zero gate bias, leading to E-mode operation. In high-frequency power switching circuits, the gate voltage could easily exceed the critical safe operating bias (determined by specific gate technology) in the form of gate ringing due to parasitic inductance and capacitance in the gate control loop. For p-GaN E-mode power transistors, gate stress over 10 V can result in easy gate breakdown and the safe operating gate bias range of commercial E-mode GaN power devices has been specified at 7 V, or less. Such low gate voltage headroom has imposed significant burden upon gate drive design when the switching speed is often compromised.

Typically, to provide adequate gate over-drive to overcome the positive threshold voltage shift and resultant on-resistance degradation, a relatively high forward gate bias (e.g., 5-6 V) is required. Thus, the p-GaN gate E-mode devices exhibit a small safe operating gate bias range.

The above-described deficiencies of conventional group III-N-based devices are merely intended to provide an overview of some of the problems of conventional systems and methods, and are not intended to be exhaustive. Other problems with conventional systems and corresponding benefits of the various non-limiting embodiments described herein may become further apparent upon review of the various non-limiting embodiments of the following description.

SUMMARY

Various non-limiting embodiments described herein employing an exemplary gate interface protection layer and high-temperature gate dielectric can provide exemplary metal-insulator-semiconductor (MIS-) field-effect transistors (FETs) or MIS-HEMTs (high electron mobility transistors) with low on-resistance, small hysteresis, high threshold voltage stability, and/or high gate dielectric reliability.

For example, in various embodiments, enhancement-mode group-III-nitride (III-N) (e.g., GaN, etc.) metal-insulator-semiconductor devices, such as, for example, MIS-FETs or MIS-HEMTs, incorporating a recessed gate structure (e.g., fully recessed or partially recessed) and a gate dielectric deposited at high temperature and gate interface protection methods are disclosed herein. In non-limiting aspects, by recessing the barrier layer at the gate region, exemplary MIS-FETs and/or MIS-HEMTs can be transformed from depletion-mode to enhancement-mode, which is preferred for the fail-safe operation and simpler gate control and driver configuration. In further non-limiting aspects, a high temperature gate dielectric can be formed between the gate electrode and the semiconductor under gate electrode to suppress the gate leakage current. In addition, a gate dielectric and semiconductor or channel layer having a large conduction band offset can be employed to suppress gate leakage, whereas exemplary gate interface protection methods can ensure high threshold voltage stability and high gate dielectric reliability.

Accordingly, various embodiments described herein can provide enhancement-mode III-N MIS-FET or MIS-HEMT devices with high performance, high stability, and high reliability.

In one non-limiting embodiment, the subject disclosure provides methods comprising forming an interface protection layer adjacent to a recessed gate structure (e.g., fully recessed) of a group III nitride, metal-insulator-semiconductor field-effect transistor (MIS-FET) device, and forming a gate dielectric layer disposed on the interface protection layer. In another non-limiting embodiment, the subject disclosure provides methods comprising forming an interface protection layer adjacent to a recessed gate structure (e.g., partially recessed) of a group III nitride, metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) device, and forming a gate dielectric layer disposed on the interface protection layer.

In other embodiments, the subject disclosure provides metal-insulator-semiconductor devices comprising a recessed gate structure (e.g., fully recessed or partially recessed), an interface protection layer (e.g., gate interface connection layer) adjacent to the recessed gate structure, and a gate dielectric layer (e.g., gate dielectric) disposed on the interface protection layer.

Further, one or more embodiments of the subject disclosure provides a semiconductor device comprising a substrate (e.g., a semiconductor substrate, a heterostructure, etc.), a buffer layer comprising a channel layer, a recessed gate (e.g., fully recessed or partially recessed) recessed into a portion of a barrier layer and the channel layer of the semiconductor device, a gate interface protection layer adjacent to the channel layer, and a gate dielectric layer disposed between gate interface protection layer and a gate electrode formed in the recessed gate.

These and other additional features of the disclosed subject matter are described in more detail below.

DETAILED DESCRIPTION

Overview

As used herein, acronyms are used to denote the following: Source (S), Drain (D), Gate (G), Current (I or C), Volts or Voltage (V), Resistance (R), Breakdown Voltage (BV), Transconductance (Gm), Length, Width, Distance, or Spacing (L or W), Relative Position or Number (X), Ohmic Contact (O), Anode or Amperes (A), Cathode, Capacitance, Celsius, etc. (C), Seconds (s), Energy or Electric Field Strength (E), Temperature (T), Time (t), as is apparent from the context. In addition, as used herein, various chemical symbols are used refer to their elements or components of a compound, including, but not limited to, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), silicon carbide (SiC), silicon nitrides (SiNx), silicon dioxide (SiO2), silicon oxynitrides (SiNxOy), etc.

As described above, group III-nitride (III-N) compound semiconductor materials, (e.g., GaN, etc.) comprise wide energy bandgap, high breakdown electrical field, and high thermal conductivity. In addition, typical wide-bandgap heterostructure systems, such as those incorporating AlGaN/GaN heterostructures, enhanced by the spontaneous and piezoelectric polarization effects, yields two-dimensional electron gas (2DEG) channels with a high sheet charge concentration and high electron mobility. Accordingly, group III-N-based devices, such as GaN-based devices, for example, can provide enhancement-mode metal-insulator-semiconductor (MIS-) field-effect transistors (FETs) and/or metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) for high-performance power conversion systems.

For example,FIG.1depicts a conventional III-nitride E-mode LPCVD-SiNxMIS-FET100having an exemplary recessed barrier under the gate, without an interfacial protection layer, in which various aspects described herein can be implemented. Exemplary devices100can comprise a substrate102, a nucleation layer104, a buffer layer106, a semiconductor or channel layer108, a barrier layer110, a passivation layer112, and a gate dielectric114, according to various non-limiting aspects. In addition, exemplary devices100can comprise a gate electrode118formed on the gate dielectric114, an exemplary source electrode116and a drain electrode120.

As further described herein, by recessing barrier layer110at the gate foot area of a recessed gate structure (e.g., fully recessed) of semiconductor or channel layer108, as shown inFIG.1, conventional GaN MIS-FETs (field-effect transistors) can facilitate enhancement-mode operation, which is preferred for fail-safe operation and simpler gate control and driver configuration. To suppress gate leakage current, a gate dielectric114can be formed between the gate electrode118and the semiconductor or channel layer108under gate electrode, in a non-limiting aspect. In a further non-limiting aspect, a large conduction band offset between gate dielectric114and the semiconductor or channel layer108can suppress gate leakage.

In depletion mode (D-mode) MIS-HEMT devices, it has been shown that the GaN surface can still maintain excellent morphology after the deposition of low-pressure chemical vapor deposition (LPCVD)-SiNx. However, combining highly reliable LPCVD-SiNxwith recessed-gate structure (e.g., partially recessed) for E-mode GaN MIS-FET has been much more challenging. The etched GaN surface (with weakened chemical bonds at the surface) experiences stronger Ga and N out-diffusion in high-temperature ambient at the start of the LPCVD process, and suffers from significant degradation. Thus, the high-performance LPCVD-SiNxgate dielectric has not been successfully deployed in recessed-gate GaN MIS-FET devices with satisfactory performance and reliability. However, these MIS-FETs exhibit higher gate breakdown voltage (e.g., greater than 20 V) compared to ˜10 V in p-GaN power devices. In addition, a high gate bias of +11 V was revealed from time-dependent dielectric breakdown (TDDB) tests for a 10-year lifetime, which is much higher than the reported value of p-GaN power transistors (e.g., less than 6.5 V).

However, despite desirable enhanced gate swing and lower gate leakage, commercialization of recessed-gate E-mode III-N MIS-FET has been hindered due to concerns over complications regarding voltage stability and gate dielectric reliability. Despite the gate leakage issue, gate swing, threshold voltage stability and gate dielectric reliability are also critical concerns for the commercialization of MIS-FETs. It is difficult for conventional gate dielectric114deposition processes (e.g., Al2O3, SiNx, SiO2, etc. prepared by atomic layer deposition (ALD) or plasma-enhanced atomic layer deposition (PEALD) and plasma-enhanced chemical vapor deposition (PECVD) to pass reliability test and qualifications due to relatively low film quality as a result of low deposition temperature (e.g., 300° C.)). As described herein, conventional gate dielectric deposition processes provide relatively low film quality as a result of low deposition temperature (e.g., 300 degrees Celsius (° C.)). As further described herein, high deposition temperature can provide a gate dielectric114with reduced trap density and high film quality. Despite a smaller band gap (5.2 electron volts (eV)) than Al2O3(7 eV), SiNxhas a type-II alignment with GaN that yields a conduction band offset of 2.3 eV (larger than 2.1 eV for Al2O3) and is a promising dielectric for n-channel GaN MIS-FET. SiNxdeposited by LPCVD has shown superior performance in terms of low leakage, high breakdown electric field and long TDDB lifetime, mainly because of its high film quality as a result of its high deposition temperature (e.g., 780° C.).

Accordingly, various embodiments as described herein can employ high deposition temperature to facilitate provided gate dielectric114with reduced trap density and enhanced film quality. In various embodiments, exemplary gate dielectric114can comprise a silicon nitride film deposited using LPCVD at high temperature such as, for example, 780° C., as further described herein. However, in high-temperature ambient environments, an etched semiconductor surface (e.g., an etched GaN surface, etc.) could experience out-diffusion of atoms and suffer from significant surface degradation, leading to a rough semiconductor/gate dielectric114interface with high trap density. That is, in a high-temperature ambient environment, surface of the gate foot area of a recessed gate structure of semiconductor or channel layer108(e.g., having weakened chemical bonds at the surface) can experience stronger atomic out-diffusion and significant surface degradation.

To overcome this issue, various non-limiting embodiments of interface protection methods can provide exemplary gate interface protection layers, which can facilitate providing enhancement-mode III-N MIS-FET or MIS-HEMT devices with high performance, high stability and high reliability. Accordingly, various non-limiting embodiments of the disclosed subject matter can employ a gate interface protection layer between an exemplary gate dielectric114, which, when deposited at high-temperature can prevent semiconductor or channel layer108surface roughness, as further described herein. As a result, charge carriers at this interface that would otherwise exhibit low mobility with threshold voltage instability due to the high interface trap density can be prevented. For example, without employing an exemplary gate interface protection layer as described herein, a conventional LPCVD-SiNxfilm employed as a gate dielectric114for an enhancement-mode GaN MIS-HEMT device with a partially recessed gate structure can result in large hysteresis in the threshold voltage.

Accordingly, various non-limiting embodiments described herein employing an exemplary gate interface protection layer and high-temperature gate dielectric114can provide exemplary MIS-FET or MIS-HEMT devices with low on-resistance, small hysteresis, high threshold voltage stability, and/or high gate dielectric reliability, while high-temperature gate dielectric114can facilitate providing devices with low gate leakage, high breakdown electric field, low defect density, and long time to breakdown lifetime, and while enabling seamless process integration of the high-temperature gate dielectric114in GaN devices having an exemplary recessed gate structure (e.g., fully recessed or partially recessed) for manufacturing enhancement-mode GaN power MIS-FETs or MIS-HEMTs. Thus, various embodiments described herein facilitate fabrication of enhancement-mode GaN power MIS-FET or MIS-HEMT devices that offer unique advantages over the current p-GaN gate devices, including improved immunity of gate ringing and simplified gate driver circuits. As a non-limiting example, exemplary GaN MIS-FET devices as described herein can facilitate providing devices having relatively lower gate leakage, larger gate swing, and higher gate dielectric reliability, compared to conventional devices.

Thus, various disclosed embodiments can employ a gate interface protection layer as further described herein, which can protect the semiconductor or channel layer108from degradation at high temperature during the fabrication process. While various embodiments describe or depict recessed gate structures (e.g., fully recessed) of exemplary MIS-FET devices for the purposes of illustration, and not limitation, it is understood that disclosed techniques can be incorporated into other devices, such as for example recessed gate structures (e.g., partially recessed) of exemplary MIS-HEMT devices, as further described herein. As a non-limiting example, an exemplary starting epitaxial substrate can be employed in exemplary HEMT structures (e.g., with GaN(cap)/AlGaN/GaN heterojunction) as for MIS-FET structure, where an exemplary MIS-HEMT device can refer to a device structure with a partially recessed gate structure (e.g., a non-recessed or a partially recessed gate structure, for example, with a thin barrier layer remaining, etc.) and with a MIS-gate, while an exemplary MIS-FET device can refer to a device structure with a fully recessed gate structure (e.g., with the GaN(cap)/AlGaN removed, for example, by etching) and with a MIS-gate. Thus, various embodiments as described herein can employ an exemplary gate interface protection layer in both exemplary MIS-FET and MIS-HEMT devices. Thus, as used herein, exemplary metal-insulator-semiconductor devices can refer to exemplary MIS-FET and/or MIS-HEMT devices. For example,FIG.2depicts a first exemplary embodiment of a gate interface protection layer, wherein a dielectric stack under the gate electrode118includes forming a gate interface protection layer comprising a dielectric layer and forming a second gate dielectric114at high temperature. An exemplary gate interface protection layer can comprise a dielectric layer prepared in low temperature such as, for example, 300° C., to form a high quality interface (e.g., silicon nitride, etc.) prepared using plasma-enhanced chemical vapor deposition. During subsequent high-temperature processing, a gate interface protection layer comprising a dielectric layer can protect the etched surface of semiconductor or channel layer108from degradation. As a result, a sharp interface between a gate interface protection layer comprising a dielectric layer and semiconductor or channel layer108is well maintained, as depicted inFIG.4. Note that an exemplary gate interface protection layer comprising a dielectric layer can also be further densified during the high-temperature process, according to a further non-limiting aspect.

As a further example,FIG.3depicts a second exemplary embodiment of a gate interface protection layer, wherein an exemplary dielectric stack under the gate electrode118can comprise a surface treatment of semiconductor or channel layer108, annealing at high temperature, and forming gate dielectric114. In a non-limiting aspect, a surface of the semiconductor or channel layer108can be oxidized by exposure to an oxygen containing gas plasma or an oxygen containing gas. During an exemplary annealing process, re-configuration near the surface of semiconductor or channel layer108can be facilitated by high temperature. As further described herein, an exemplary annealing process can be performed in situ (e.g., during a deposition process for gate dielectric114at high temperature). As a result, a stable gate interface protection layer can be formed before deposition of gate dielectric114, which can protect semiconductor or channel layer108surface from decomposition.FIG.4demonstrates improved interface morphology with the gate interface protection layer.

Additionally, variations of the disclosed embodiments as suggested by the disclosed structures and methodologies are intended to be encompassed within the scope of the subject matter disclosed herein. Furthermore, the various embodiments of the structures, devices, and methodologies of the disclosed subject matter can include variations in the device type, location, configuration, process, and/or process variables associated with the recessed gate structure or region (e.g., fully recessed or partially recessed), and/or location, configuration, process, and/or process variables associated with the gate interface protection layer, etc.

Exemplary Devices

FIG.2depicts exemplary schematic cross section of a non-limiting LPCVD-SiNxMIS-FET200comprising an exemplary first embodiment of a gate interface protection layer, having an exemplary 2 nanometer (nm), plasma-enhanced chemical vapor deposition (PECVD)-SiNxgate interface protection layer, according to various non-limiting aspects described herein. Exemplary devices200as described herein can comprise a substrate102, a nucleation layer104, a buffer layer106, a semiconductor or channel layer108, a barrier layer110, a passivation layer112, a gate interface protection layer204and a gate dielectric114, according to various non-limiting aspects.

Exemplary substrate102can comprise silicon, sapphire, diamond, SiC, AlN, GaN, etc., in further non-limiting aspects. In addition, an exemplary nucleation layer104can comprise AlN, GaN, InN, and/or their alloys, etc. In further non-limiting aspects, an exemplary buffer layer106can comprise AlN, GaN, InN, and/or their alloys, etc. In still other non-limiting aspects, an exemplary semiconductor or channel layer108can comprise GaN, AlN, InN, and/or their alloys, etc. In non-limiting embodiments, exemplary barrier layer110can comprise one or more layers. For example, the barrier layer110can comprise AlN, GaN, InN, and/or their alloys, etc., and exemplary barrier layer110can comprise a stack of these layers. In yet another non-limiting aspect, one or more layer in the barrier layer110has a bandgap larger than the semiconductor or channel layer108. In various non-limiting embodiments, an exemplary channel122can be formed at an interface between the barrier layer110and semiconductor or channel layer108. Furthermore, a gate recess can be formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), in various embodiments as described herein.

At the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), the barrier layer110can be removed, in a non-limiting aspect. In a further non-limiting aspect, a portion of the semiconductor or channel layer108can also be removed. Accordingly, exemplary channel122at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed) can comprise a metal-insulator-semiconductor channel located at the MIS interface, e.g., the interface between the gate dielectric114and the underlying semiconductor or channel layer108. Gate interface protection layer204is formed before the formation of gate dielectric114.

In particular, an exemplary gate interface protection layer204as described herein comprising a dielectric layer can be formed at a relatively low temperature, at which the surface of semiconductor or channel layer108has no degradation such that an interface with low trap density can be formed, in various non-limiting aspect. In addition, an exemplary gate dielectric114can be formed at high temperature, such as, for example, 780° C., in further non-limiting aspects. In further embodiments, an exemplary gate dielectric114can comprise silicon nitride deposited using low-pressure chemical vapor deposition.

In addition, an exemplary gate electrode118can be formed on the gate dielectric114, such that gate electrode118is placed with the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed) covered by the gate electrode118. In further non-limiting aspects, an exemplary source electrode116and a drain electrode120can be formed (e.g., at opposite sides of gate electrode118, etc.). The various embodiments of the disclosed subject matter can comprise a dielectric stack at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed) according to further non-limiting aspects. Thus, in various embodiments described herein, the interface between the gate interface protection layer204comprising a dielectric layer and semiconductor or channel layer108is protected from degradation during high temperature processing. Therefore, the electron mobility in the gate region is high and concentration of traps at the interface is low in various non-limiting embodiments described herein. As a result, the various embodiments of the disclosed subject matter can include normally off operation, low on-resistance, stable threshold voltage and a reliable gate dielectric114.

In a further non-limiting embodiment, an exemplary device comprising an exemplary first embodiment of a gate interface protection layer204can comprise a 0.5 millimeter (mm) Si (111) substrate102, a 4 micrometer (μm) GaN buffer layer108, an AlGaN barrier layer110, a passivation layer112, a LPCVD-SiNxgate dielectric114, and a 2 nm PECVD-SiNxgate interface protection layer204.

FIG.3depicts exemplary schematic cross section of a non-limiting LPCVD-SiNxMIS-FET300comprising an exemplary second embodiment of a gate interface protection layer, having an exemplary oxide-based gate interface protection layer, according to various non-limiting aspects described herein. Exemplary devices300as described herein can comprise a substrate102, a nucleation layer104, a buffer layer106, a semiconductor or channel layer108, a barrier layer110, a passivation layer112, a gate interface protection layer302and a gate dielectric114, according to various non-limiting aspects.

Exemplary substrate102can comprise silicon, sapphire, diamond, SiC, AlN, GaN, etc., in further non-limiting aspects. In addition, an exemplary nucleation layer104can comprise AlN, GaN, InN, and/or their alloys, etc. In further non-limiting aspects, an exemplary buffer layer106can comprise AlN, GaN, InN, and/or their alloys, etc. In still other non-limiting aspects, an exemplary semiconductor or channel layer108can comprise GaN, AlN, InN, and/or their alloys, etc. In non-limiting embodiments, exemplary barrier layer110can comprise one or more layers. For example, the barrier layer110can comprise AlN, GaN, InN, and/or their alloys, etc., and exemplary barrier layer110can comprise a stack of these layers. In yet another non-limiting aspect, one or more layer in the barrier layer110has a bandgap larger than the semiconductor or channel layer108. In various non-limiting embodiments, an exemplary channel122can be formed at an interface between the barrier layer110and semiconductor or channel layer108. Furthermore, a gate recess can be formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), in various embodiments as described herein.

At the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), the barrier layer110can be removed, in a non-limiting aspect. In a further non-limiting aspect, a portion of the semiconductor or channel layer108can also be removed. Accordingly, exemplary channel122at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed) can comprise a metal-insulator-semiconductor channel located at the MIS interface, e.g., the interface between the gate dielectric114and the underlying semiconductor or channel layer108.

In further non-limiting aspects, an exemplary gate interface protection layer302can be formed by surface treatment of semiconductor or channel layer108and/or annealing at high temperature. In non-limiting embodiments, a surface of the semiconductor or channel layer108in the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed) can be oxidized by exposure to an oxygen containing gas plasma, an oxygen containing gas, etc. to form an oxide-based gate interface protection layer302. In further non-limiting embodiments, after annealing, re-configuration near the surface of semiconductor or channel layer108can be facilitated by high temperature. As a result, a stable gate interface protection layer302can be formed before deposition of gate dielectric114, which can protect the semiconductor or channel layer108surface from decomposition prior to gate dielectric114deposition. In a non-limiting aspect, an exemplary annealing process can be performed in situ, such as, for example, during a process of gate dielectric114formation or deposition at high temperature, e.g., 780° C. In further embodiments, an exemplary gate dielectric114can comprise silicon nitride deposited using low-pressure chemical vapor deposition.

In addition, an exemplary gate electrode118can be formed on the gate dielectric114, such that gate electrode118is placed with the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed) covered by the gate electrode118. In further non-limiting aspects, an exemplary source electrode116and a drain electrode120can be formed (e.g., at opposite sides of gate electrode118, etc.). Thus, in various embodiments described herein, the interface between the gate interface protection layer302and semiconductor or channel layer108is protected from degradation during high temperature processing. Therefore, the electron mobility in the gate region is high and concentration of traps at the interface is low in various non-limiting embodiments described herein. As a result, the various embodiments of the disclosed subject matter can include normally off operation, low on-resistance, stable threshold voltage and a reliable gate dielectric114.

In a further non-limiting embodiment, an exemplary device comprising an exemplary second embodiment of a gate interface protection layer302can comprise a 0.5 millimeter (mm) Si (111) substrate102, a 4 micrometer (μm) GaN buffer layer108, an AlGaN barrier layer110, a passivation layer112, a LPCVD-SiNxgate dielectric114, and an oxide or oxide-based interface protection layer302.

FIG.4depicts exemplary cross-sectional high-resolution transmission electron microscope (TEM) micrographs400of gate dielectric114and semiconductor structure of an exemplary LPCVD-SiNx/GaN MIS-structure, without an exemplary gate interface protection layer (e.g., without exemplary gate interface protection layer204,302, etc.), with an exemplary 2-nm PECVD-SiNxgate interface protection layer (e.g., with exemplary gate interface protection layer204, etc.), and with an exemplary oxide-based gate interface protection layer (e.g., with exemplary gate interface protection layer302, etc.), wherein an enlarged micrograph of the interface at the SiNx/GaN boundary is depicted, according to further non-limiting aspects. Note that the seemingly different atomic arrangement in GaN layer in panel (a) compared to (b) and (c) is due to different sidewall orientations in sample preparations.FIG.5depicts an exemplary energy-dispersive X-ray spectroscopy plot500at position A, B, C and D shown inFIG.4.

FIG.6demonstrates exemplary measured frequency (fm)-dependent current−voltage (C−V) characteristics of LPCVD-SiNxMIS-diodes with and without an exemplary gate interface protection layer, according to various non-limiting embodiments described herein.FIG.7demonstrates exemplary measured Gp/ω-f characteristics of LPCVD-SiNxMIS-diodes without an exemplary gate interface protection layer, according to various non-limiting embodiments described herein, at measurement temperature (Tm)=25 degrees Celsius (° C.) and 200° C.FIG.8depicts exemplary measured Gp/ω-f characteristics of LPCVD-SiNxMIS-diodes with an exemplary gate interface protection layer, according to further non-limiting embodiments described herein, at measurement temperature (Tm)=25° C. and 200° C.FIG.9depicts Dit-ETmapping of MIS diode using alternating current (AC)-conductance method, wherein a cross-section u of 10−14per square centimeters (cm2) is used to correlate re to the corresponding ET of the interface traps.

FIG.10depicts an exemplary block diagram1000of non-limiting aspects of exemplary fabrication methods, as described herein. For instance, an exemplary heterostructure can comprise a heterostructure prepared by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HYPE), etc. An exemplary heterostructure can comprise a substrate102, a nucleation layer104, a buffer layer106, a semiconductor or channel layer108, and a barrier layer110, as further described above regardingFIGS.2-3, etc. For example, exemplary substrate102can comprise silicon, sapphire, diamond, SiC, GaN, etc., in further non-limiting aspects. In addition, an exemplary nucleation layer104can comprise AlN, GaN, InN, and/or their alloys, etc. In further non-limiting aspects, an exemplary buffer layer106can comprise AlN, GaN, InN, and/or their alloys, etc. In still other non-limiting aspects, an exemplary semiconductor or channel layer108can comprise GaN, AlN, InN, and/or their alloys, etc. In non-limiting embodiments, exemplary barrier layer110can comprise one or more layers. For example, the barrier layer110can comprise AlN, GaN, InN, and/or their alloys, etc, and exemplary barrier layer110can comprise a stack of these layers. In yet another non-limiting aspect, one or more layer in the barrier layer110has a bandgap larger than the semiconductor or channel layer108. In various non-limiting embodiments, an exemplary channel122can be formed at an interface between the barrier layer110and semiconductor or channel layer108.

FIG.11depicts an exemplary block diagram1100of further non-limiting aspects of exemplary fabrication methods, as further described herein. For instance, one or more exemplary passivation layers112can be deposited on the exemplary heterostructure, which can facilitate relieving current collapse III-V HEMTs, as further described herein. An exemplary layer112can comprise one or a combination of insulating, or semi-conducting layers, such as SiNx, SiO2, Al2O3, AlN, GaN, Si, diamond, etc.

FIG.12depicts an exemplary block diagram1200of still further non-limiting aspects of exemplary fabrication methods, as described herein. For instance, an exemplary gate recess can be formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), in various embodiments as described herein. For example, the one or more exemplary passivation layers112at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed) can be removed. As a further example, exemplary barrier layer110and a portion of semiconductor or channel layer108can be removed. In another non-limiting example, a thin layer of exemplary barrier layer110can remain to facilitate providing exemplary MIS-HEMT devices. In a non-limiting aspect, etching of the one or more exemplary passivation layers112can comprise a wet etch or dry etch depending on which material has been adopted for passivation. In a further non-limiting aspect, etching of exemplary barrier layer110and a portion of semiconductor or channel layer108can include, but is not limited to, plasma dry etching, digital etching, and/or a combination.

FIG.13depicts an exemplary block diagram1300of non-limiting aspects of exemplary fabrication methods directed to an exemplary first embodiment, as described herein. For instance, an exemplary gate interface protection layer dielectric204can be formed comprising a dielectric layer, deposited at a relatively low temperature, such as, for example, 300° C., as further described herein. In a non-limiting aspect, exemplary gate interface protection layer dielectric204comprising a dielectric can comprise silicon nitride, silicon oxide or silicon oxynitride, etc., and can be deposited via PECVD, in a further non-limiting aspect.

FIG.14depicts an exemplary block diagram1400of other non-limiting aspects of exemplary fabrication methods directed to an exemplary first embodiment, as further described herein. For instance, an exemplary gate dielectric114can be deposited over exemplary gate interface protection layer dielectric204, as further described herein. In a non-limiting aspect, exemplary gate dielectric114can comprise one layer or a stack of layers comprising SiNx, SiNxOy, SiO2, etc., and/or combinations. In a further non-limiting aspect, exemplary gate dielectric114can be deposited via LPCVD.

FIG.15depicts an exemplary block diagram1500of still other non-limiting aspects of exemplary fabrication methods directed to an exemplary first embodiment, as described herein. For instance, exemplary ohmic contacts can be formed on the heterostructure for source electrode116and drain electrode120, as further described herein. In a non-limiting aspect, exemplary ohmic contacts can comprise a metal comprising one or more Ti, Al, Ni, Au, W, V, Ta, etc. In yet another non-limiting aspect, exemplary ohmic contacts can be subjected to an annealing process to generate the exemplary ohmic contacts.

FIG.16depicts an exemplary block diagram1600of further non-limiting aspects of exemplary fabrication methods directed to an exemplary first embodiment, as further described herein. For instance, exemplary gate electrode118can be formed on the heterostructure, as further described herein. In a non-limiting aspect, exemplary gate electrode118can cover at least the recessed gate region (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed)), so that the recessed region is modulated by the gate voltage.

FIG.17depicts an exemplary block diagram1700of non-limiting aspects of exemplary fabrication methods directed to an exemplary second embodiment, as described herein. For instance, exemplary fabrication methods directed to an exemplary second embodiment can proceed from heterostructure depicted in exemplary block diagram1200ofFIG.12. In further non-limiting aspects, an exemplary gate interface protection layer302can be formed by surface treatment of semiconductor or channel layer108and/or annealing at high temperature. In non-limiting embodiments, a surface of the semiconductor or channel layer108in the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed) can be oxidized by exposure to an oxygen containing gas plasma, an oxygen containing gas, etc. to form an oxide-based gate interface protection layer302. In further non-limiting embodiments, after annealing, re-configuration near the surface of semiconductor or channel layer108can be facilitated by high temperature. As a result, a stable gate interface protection layer302can be formed before deposition of gate dielectric114, which can protect the semiconductor or channel layer108surface from decomposition prior to gate dielectric114deposition. In a non-limiting aspect, an exemplary annealing process can be performed in situ, such as, for example, during a process of gate dielectric114formation or deposition at high temperature, e.g., 780° C. For example,FIG.18depicts an exemplary block diagram1800of other non-limiting aspects of exemplary fabrication methods directed to an exemplary second embodiment, as further described herein. For instance, For instance, an exemplary gate dielectric114can be deposited over exemplary gate interface protection layer dielectric204, as further described herein. In a non-limiting aspect, exemplary gate dielectric114can comprise one layer or a stack of layers comprising SiNx, SiNxOy, SiO2, etc., and/or combinations. In a further non-limiting aspect, exemplary gate dielectric114can be deposited via LPCVD or other high temperature deposition techniques.

FIG.19depicts an exemplary block diagram1900of still other non-limiting aspects of exemplary fabrication methods directed to an exemplary second embodiment, as described herein. For instance, exemplary ohmic contacts can be formed on the heterostructure for source electrode116and drain electrode120, as further described herein. In a non-limiting aspect, exemplary ohmic contacts can comprise a metal comprising one or more Ti, Al, Ni, Au, W, V, Ta, etc. In yet another non-limiting aspect, exemplary ohmic contacts can be subjected to an annealing process to generate the exemplary ohmic contacts.

FIG.20depicts an exemplary block diagram2000of further non-limiting aspects of exemplary fabrication methods directed to an exemplary second embodiment, as further described herein. For instance, exemplary gate electrode118can be formed on the heterostructure, as further described herein. In a non-limiting aspect, exemplary gate electrode118can cover at least the recessed gate region (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed)), so that the recessed region is modulated by the gate voltage.

FIG.21depicts non-limiting, experimental transfer ID−VGScharacteristic and output ID−VGScharacteristic of a conventional LPCVD-SiNx/GaN MIS-FET, without exemplary gate interface protection layer, for an exemplary device having dimensions, LGS/LG/LGD=2/1.5/15 micrometers (μm).FIG.22depicts non-limiting, experimental transfer ID−VGScharacteristic and output ID−VGScharacteristic of an exemplary first embodiment comprising an exemplary 2-nm PECVD-SiNxgate interface protection layer204, according to non-limiting aspects, for an exemplary device having dimensions, LGS/LG/LGD=2/1.5/15 μm.FIG.23depicts non-limiting, experimental transfer ID−VGScharacteristic and output ID−VGScharacteristic of an exemplary second embodiment comprising an exemplary oxide-based gate interface protection layer302, according to further non-limiting aspects, for an exemplary device having dimensions, LGS/LG/LGD=2/1.5/15 μm. Compared with the conventional LPCVD-SiNx/GaN MIS-FET ofFIG.21, both embodiments ofFIGS.22-23deliver smaller subthreshold swing, smaller hysteresis, and lower on-resistance for a device with gate-to-drain distance of 15 μm. In particular, the maximum field-effect mobility of the conventional LPCVD-SiNx/GaN MIS-FET ofFIG.21, the first embodiment and the second embodiment is 40 cm2/V·s, 160 cm2/V·s and 145 cm2/V·s, respectively.

FIG.24depicts exemplary extracted field-effect mobility using a long channel, MIS-FET with LG/WG=44/100 μm, and threshold voltage uniformity of the normally-off LPCVD-SiNxMIS-FETs according to an exemplary first embodiment comprising a non-limiting gate interface protection layer204, as described herein. The threshold voltage (defined at ID=100 μA/mm) shows a tight distribution of 2.37±0.22 V.

FIG.25demonstrates exemplary temperature dependence of threshold voltage in non-limiting conventional LPCVD-SiNx/GaN MIS-FET devices, an exemplary first embodiment, and an exemplary second embodiment, as further described herein. Both exemplary devices according to the first and the second embodiment show more thermally stable threshold voltage (negative VTH shifts smaller than 0.22 V up to 200° C.) than the conventional LPCVD-SiNx/GaN MIS-FET device.FIG.26depicts exemplary T-dependent transfer characteristics of an LPCVD-SiNxgate interface protection layer in an exemplary GaN MIS-FET with measurement temperature (Tm) increasing from 25° C. to 200° C., for an exemplary device having dimensions, LGS/LG/LGD=2/1.5/15 μm.

FIG.27depicts exemplary experimental off-state breakdown characteristics or leakage current of a non-limiting LPCVD-SiNxMIS-FET device according to an exemplary first embodiment comprising a gate interface protection layer204, with the substrate grounded, for an exemplary device having dimensions, LGS/LG/LGD=2/1.5/15 μm. The breakdown voltage is 650 V for a device with gate-to-drain distance of 15 μm, which is limited by the drain-to-substrate vertical leakage current. The device according to the second embodiment shows the similar off-state breakdown characteristics (not shown).

FIG.28demonstrates exemplary normalized dynamic on-resistance or ID−VDScharacteristics in linear region of an exemplary LPCVD-SiNxMIS-FET device, with gate-to-drain distance of 15 μm and with an exemplary gate interface protection layer204, and normalized dynamic RON extracted from the pulsed ID−VDSwith VGS_ON=15 volts (V), wherein waveforms of VGSand VDSduring the pulsed ID−VDStest are depicted, for an exemplary device having dimensions, LGS/LG/LGD=2/1.5/15 μm. The dynamic on-resistance is extracted from the pulsed ID−VDSwith VGS_ON=15 V. The ratio dynamic-RON/static-RONonly increases to 1.40 with a switching time of 5 μs and off-state quiescent drain bias (VDS_OFF) up to 600 V.

FIG.29demonstrates exemplary temperature-dependent gate leakage IG−VGcharacteristics of an exemplary LPCVD-SiNxMIS-FET device, with an exemplary gate interface protection layer204and with gate dielectric114deposited at high temperature, and with Tmincreasing from 25° C. to 200° C., and T-dependence of electric-field strength (EBD), wherein energy band diagram along the vertical direction in the gate region with VG=VTHis depicted, with the electric field in gate dielectric estimated as ESiNx=(VG−VTH)/tSiNxE0. The gate dielectric114enables a high forward gate breakdown voltage of 21.5 V (electric field ˜12 megaVolts (MV)/cm) at 25° C. and effectively suppressed gate leakage even at 200° C.

FIG.30depicts exemplary time to breakdown (tBD) of a non-limiting LPCVD-SiNxMIS-FETs with gate interface protection layer204according to an exemplary first embodiment at forward gate stress of 18, 17, 16 and 15 V at 25° C.FIG.31depicts exemplary Weibull plot of the electric field-dependent tBDdistribution for a non-limiting LPCVD-SiNxMIS-FETs with gate interface protection layer204according to an exemplary first embodiment.FIG.32depicts exemplary lifetime prediction with failure rate of 63.2% and 0.01%, respectively, for a non-limiting LPCVD-SiNxMIS-FETs with gate interface protection layer204according to an exemplary first embodiment. The lifetime of gate dielectric is predicted to be 11 V at a failure rate of 63.2% and 9.1 V at failure rate of 0.01%, as compared to a reported value for p-GaN devices at lower than 6.5 V for a 10 years lifetime with a failure rate of 63.2%.

FIG.33depicts exemplary time to breakdown (tBD) of the LPCVD-SiNxMIS-FETs with gate interface protection layer at 25° C., 100° C., 150° C., and 200° C. with forward gate stress of 16 V.FIG.34depicts an exemplary Weibull plot of the temperature-dependent tBDdistribution.FIG.35depicts an exemplary Arrhenius plot of tBDextracted at the failure rate of 63.2%.

FIG.36depicts exemplary monitored VTHand RONof LPCVD-SiNxMIS-FET with gate interface protection layer during the gate bias stress with VGS=−30 V (negative-bias temperature instability (NBTI), (a) and (b)) and VGS=10 V (positive bias temperature instability (PBTI), (c) and (d)) at both 25° C. and 150° C., for an exemplary device having dimensions, LGS/LG/LGD=1.5/2/2 μm.

FIG.37depicts exemplary monitored threshold voltage of a non-limiting device according to an exemplary first embodiment during the gate bias stress with VGS=+10 V.FIG.38depicts exemplary monitored threshold voltage of a non-limiting device according to an exemplary second embodiment during the gate bias stress with VGS=+10 V.

In view of the structures and devices described supra, methodologies that can be implemented in accordance with the disclosed subject matter will be better appreciated with reference to the flowcharts ofFIGS.39-40. While for purposes of simplicity of explanation, the methodologies are shown and described as a series of blocks, it is to be understood and appreciated that such illustrations or corresponding descriptions are not limited by the order of the blocks, as some blocks may occur in different orders and/or concurrently with other blocks from what is depicted and described herein. Any non-sequential, or branched, flow illustrated via a flowchart should be understood to indicate that various other branches, flow paths, and orders of the blocks, can be implemented which achieve the same or a similar result. Moreover, not all illustrated blocks may be required to implement the methodologies described hereinafter.

Exemplary Methodologies

FIG.39depicts exemplary non-limiting methods3900in accordance with aspects of the disclosed subject matter. As a non-limiting example, exemplary methods3900can comprise, at3902, forming an interface protection layer (e.g., gate interface protection layer204,302, etc.) adjacent to a recessed gate structure (e.g., adjacent to a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), etc.) of a metal-insulator-semiconductor device (e.g., a group III nitride, metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) device, a MIS-FET device, etc.). For instance, in a non-limiting aspect, exemplary methods3900can comprise forming the interface protection layer (e.g., gate interface protection layer302, etc.) comprising exposing a surface of the channel layer to an oxygen-containing plasma or an oxygen-containing gas, as further described herein. In a further non-limiting aspect, exemplary methods3900can comprise forming the interface protection layer (e.g., gate interface protection layer204, etc.) comprises forming one or more layer of one or more of an oxide, silicon oxide, silicon nitride, or silicon oxynitride adjacent to the recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), etc.). In addition, exemplary methods3900can further comprise forming the interface protection layer (e.g., gate interface protection layer204, etc.) comprising depositing a dielectric material at or below about 300° C. or depositing the dielectric material via PECVD, as further described herein. Exemplary methods3900can further forming the interface protection layer (e.g., gate interface protection layer204, gate interface protection layer302, etc.) adjacent to a recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), etc.) of the group III nitride, metal-insulator-semiconductor device comprising forming the interface protection layer (e.g., gate interface protection layer204, gate interface protection layer302, etc.) adjacent to a fully recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202, etc.) of a metal-insulator-semiconductor field-effect-transistor device, to a partially recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202, etc.) of a high electron mobility transistor device, etc. as further described herein.

In a further non-limiting example, exemplary methods3900can comprise, at3904, forming a gate dielectric layer (e.g., gate dielectric114, etc.) disposed on the interface protection layer (e.g., gate interface protection layer204,302, etc.). As a non-limiting example, exemplary methods3900can comprise forming the gate dielectric layer comprises at least one of depositing the gate dielectric layer (e.g., gate dielectric114, etc.) at or above about 780° C., depositing one or more layer of one or more of silicon nitride, silicon oxide, or silicon oxynitride, or depositing the gate dielectric layer (e.g., gate dielectric114, etc.) via LPCVD, as further described herein. As a further non-limiting example, depositing the gate dielectric layer (e.g., gate dielectric114, etc.) can comprise depositing one or more of silicon oxide, silicon nitride, or silicon oxynitride.

Exemplary methods3900can further comprise forming the recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), etc.). As a non-limiting example, forming the recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed)) can comprise etching a portion of a barrier layer (e.g., barrier layer110, etc.) and a portion of a channel layer (e.g., semiconductor or channel layer108, etc.) of the metal-insulator-semiconductor device, as further described herein. In addition, exemplary methods3900can comprise forming a gate electrode118operatively coupled to the gate recessed structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), etc.).

FIG.40depicts other exemplary non-limiting methods4000in accordance with further aspects of the disclosed subject matter. As a non-limiting example, exemplary methods4000can comprise, at4002, forming the recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), etc.). As a non-limiting example, forming the recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed)) can comprise etching a portion of a barrier layer (e.g., barrier layer110, etc.) and a portion of a channel layer (e.g., semiconductor or channel layer108, etc.) of the metal-insulator-semiconductor device, as further described herein.

In a further non-limiting example, exemplary methods4000can comprise, at4004, forming an interface protection layer (e.g., gate interface protection layer204,302, etc.) adjacent to a recessed gate structure (e.g., adjacent to a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), etc.) of a metal-insulator-semiconductor device (e.g., a group III nitride, metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) device, a MIS-FET device, etc.). For instance, in a non-limiting aspect, exemplary methods4000can comprise forming the interface protection layer (e.g., gate interface protection layer302, etc.) comprising exposing a surface of the channel layer to an oxygen-containing plasma or an oxygen-containing gas, as further described herein. In a further non-limiting aspect, exemplary methods4000can comprise forming the interface protection layer (e.g., gate interface protection layer204, etc.) comprises forming one or more layer of one or more of an oxide, silicon oxide, silicon nitride, or silicon oxynitride adjacent to the recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), etc.). In addition, exemplary methods4000can further comprise forming the interface protection layer (e.g., gate interface protection layer204, etc.) comprising depositing a dielectric material at or below about 300° C. or depositing the dielectric material via PECVD, as further described herein. Exemplary methods4000can further forming the interface protection layer (e.g., gate interface protection layer204, gate interface protection layer302, etc.) adjacent to a recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), etc.) of the group III nitride, metal-insulator-semiconductor device comprising forming the interface protection layer (e.g., gate interface protection layer204, gate interface protection layer302, etc.) adjacent to a fully recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202, etc.) of a metal-insulator-semiconductor field-effect-transistor device, to a partially recessed gate structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202, etc.) of a high electron mobility transistor device, etc. as further described herein.

In a further non-limiting example, methods4000can comprise, at4006, forming a gate dielectric layer (e.g., gate dielectric114, etc.) disposed on the interface protection layer (e.g., gate interface protection layer204,302, etc.). As a non-limiting example, exemplary methods4000can comprise forming the gate dielectric layer comprises at least one of depositing the gate dielectric layer (e.g., gate dielectric114, etc.) at or above about 780° C., depositing one or more layer of one or more of silicon nitride, silicon oxide, or silicon oxynitride, or depositing the gate dielectric layer (e.g., gate dielectric114, etc.) via LPCVD, as further described herein. As a further non-limiting example, depositing the gate dielectric layer (e.g., gate dielectric114, etc.) can comprise depositing one or more of silicon oxide, silicon nitride, or silicon oxynitride. In addition, exemplary methods4000can comprise forming a gate electrode118operatively coupled to the gate recessed structure (e.g., a gate recess formed at the gate foot area of a recessed gate structure202(e.g., fully recessed or partially recessed), etc.), at4008.

While the disclosed subject matter has been described in connection with the preferred embodiments of the various figures, it is to be understood that other similar embodiments may be used or modifications and additions may be made to the described embodiments for performing the same function of the disclosed subject matter without deviating therefrom. For example, one skilled in the art will recognize that aspects of the disclosed subject matter as described in the various embodiments of the present application may apply to other Group III-Nitride heterostructures, other insulating or semiconducting materials or substrates, etc.

As a further example, for simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and description, details, and techniques may be omitted to avoid unnecessarily obscuring the disclosed concepts. Additionally, elements in the drawing figures are not necessarily drawn to scale, and some areas or elements may be expanded to help improve understanding of embodiments of the disclosed embodiments.

In other instances, variations of process parameters (e.g., dimensions, configuration, process step timing and order, addition and/or deletion of process steps, addition of preprocessing and/or post-processing steps, etc.) may be made to further optimize the provided structures, devices and methodologies, as shown and described herein. In any event, the structures and devices, as well as the associated methodologies described herein have many applications in metal-insulator-semiconductor transistor heterostructures. For instance, it is contemplated and intended that various aspects of the disclosed subject can be applied to other heterostructures, for example, other than single simple AlGaN/GaN heterostructures. However, an ordinary person in the art would know the variations to modify the design to make other combinations and forms of designs.

Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, apparatus, or composition that comprises a list of elements is not necessarily limited to those elements, but may include other elements or combinations not expressly listed or combinations, whether inherent to such process, method, article, apparatus, or composition, or otherwise.

Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims.