Methods and apparatus for providing a low-power memory block using a pair of nvm cells

A semiconductor device provides logic operations utilizing low-power memory blocks (“LMBs”) for power conservation. An LMB, in one embodiment, includes a first nonvolatile memory (“NVM”), a second NVM cell, and an LMB output terminal. The first NVM cell contains an NVM transistor able to store one (1) bit of first value persistently. The second NVM cell is configured to persistently store one (1) bit of second value which is opposite logic value of the first value. The LMB output terminal, coupled to a drain terminal of first NVM cell and a source terminal of second NVM cell, is operable to provide an output value in accordance with the first value.

FIELD

The exemplary embodiment(s) of the present application relates to the field of programmable semiconductor devices for logic operations involving in the computer hardware and software. More specifically, the exemplary embodiment(s) of the present invention relates to low-power memory cells for power conservation.

BACKGROUND

With increasing popularity of digital computations, network communications, artificial intelligence (AI), IoT (Internet of Things), and/or robotic controls, there is an increasing demand for fast, flexible, and efficient hardware and/or semiconductor devices with processing capabilities. Thus, high-speed and flexible semiconductor chips are generally more desirable. One conventional approach to satisfy this demand is the use of dedicated custom integrated circuits and/or application-specific integrated circuits (“ASICs”). However, a notable shortcoming of the ASIC approach is that it lacks flexibility and consumes a large number of resources.

An increasingly popular alternative approach is the utilization of programmable semiconductor devices (“PSDs”) such as programmable logic devices (“PLDs”) or field-programmable gate arrays (“FPGAs”). A feature of PSD is that it allows an end-user to program and/or reprogram one or more desirable functions to suit a variety of diverse applications after the PSDs are fabricated.

A drawback, associated with a conventional PSD as well as ASIC chips is their relatively large power consumption. For example, leakage current or a small amount of current in a conventional memory cell constantly flows through its transistors even when the memory cell is not active.

SUMMARY

A semiconductor device, in one embodiment, is able to provide logic and/or memory operations utilizing low-power memory blocks (“LMBs”) for power conservation. Each LMB, in one aspect, is configured to use two nonvolatile memory (“NVM”) cells for one logic value. For example, an LMB includes a first NVM, a second NVM cell, and an LMB output terminal. The first NVM cell contains an NVM transistor able to store one (1) bit of first value persistently. The second NVM cell is configured to persistently store one (1) bit of second value which is opposite logic value of the first value. The LMB output terminal, coupled to a drain terminal of first NVM cell and a source terminal of second NVM cell, is operable to provide an output value in accordance with the first value with minimal power consumption.

DETAILED DESCRIPTION

Embodiments of the present invention disclose a method(s) and/or apparatus for providing a low-power memory block (“LMB”) using dual nonvolatile memory (“NVM”) cells for power conservation.

The purpose of the following detailed description is to provide an understanding of one or more embodiments of the present invention. Those of ordinary skills in the art will realize that the following detailed description is illustrative only and is not intended to be in any way limiting. Other embodiments will readily suggest themselves to such skilled persons having the benefit of this disclosure and/or description.

In the interest of clarity, not all of the routine features of the implementations included herein are shown and described. It will, of course, be understood that in the development of any such actual implementation, numerous implementation-specific decisions may be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be understood that although such a development effort might be complex and time-consuming, it would nevertheless be a routine undertaking of engineering for those of ordinary skills in the art having the benefit of embodiment(s) of this disclosure.

Various embodiments of the present invention illustrated in the drawings may not be drawn to scale. Rather, the dimensions of the various features may be expanded or reduced for clarity. In addition, some of the drawings may be simplified for clarity. Thus, the drawings may not depict all components of a given apparatus (e.g., device) or method. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.

In accordance with the embodiment(s) of the present invention, the components, process steps, and/or data structures described herein may be implemented using various types of operating systems, computing platforms, computer programs, and/or general-purpose machines. In addition, those of ordinary skills in the art will recognize that devices of a less general-purpose nature, such as hardware devices, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or the like, may also be used without departing from the scope and spirit of the inventive concepts disclosed herein. Where a method comprising a series of process steps is implemented by a computer or a machine and those process steps can be stored as a series of instructions readable by the machine, it may be stored on a tangible medium such as a computer memory device, such as but not limited to, magnetoresistive random access memory (“MRAM”), phase-change memory, or ferroelectric RAM (“FeRAM”), flash memory, resistive random-access memory (“ReRAM” or “RRAM”), conductive-bridging RAM (“CBRAM”), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), Jump Drive, magnetic storage medium (e.g., tape, magnetic disk drive, and the like), optical storage medium (e.g., CD-ROM, DVD-ROM, paper card and paper tape, and the like) and other known types of program memory.

The term “system” or “device” is used generically herein to describe any number of components, elements, sub-systems, devices, packet switch elements, packet switches, access switches, routers, networks, computer and/or communication devices or mechanisms, or combinations of components thereof. The term “computer” includes a processor, memory, and buses capable of executing instructions wherein the computer refers to one or a cluster of computers, personal computers, workstations, mainframes, or combinations of computers thereof.

A semiconductor device, in one embodiment, can provide logic and/or memory operations utilizing low-power memory blocks (“LMBs”) for power conservation. Each LMB, in one aspect, is configured to use two nonvolatile memory (“NVM”) cells for one logic value. For example, an LMB includes a first NVM, a second NVM cell, and an LMB output terminal. The first NVM cell contains an NVM transistor able to store one (1) bit of first value persistently. The second NVM cell is configured to persistently store one (1) bit of second value which is opposite logic value of the first value. The LMB output terminal, coupled to a drain terminal of first NVM cell and a source terminal of second NVM cell, is operable to provide an output value in accordance with the first value with minimal power consumption.

Alternatively, LMBs can be used in a programmable semiconductor devices (“PSDs”) such as FPGA or PLD for reducing power consumption. For example, PSD includes an array of LMBs for storing configuration data. Alternatively, LMBs can also be programmed or configured to be used for storing user data during logic operations. In one aspect, LMB includes a first NVM cell and a second NVM cell configured to storage one logic value. The first NVM cell, for example, is a flash-based transistor able to store one (1) bit of data persistently. The second NVM cell containing a second flash-based transistor is able to persistently store one (1) bit of data which stores a digital value having opposite logic value of digital value in the first NVM cell.

FIG.1is a block diagram100illustrating a circuit containing LMB for storing one bit information using two NVM cells in accordance with one embodiment of the present invention. Diagram100includes input line116, LMB120, and two input transistors110-112. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram100.

LMB120, in one embodiment, includes an NVM cell102, NVM cell106, and output terminal108. NVM cell102includes a source (“S”) terminal122connecting to a power supply such as Vcc (voltage common collector), gate (“G”) terminal128, and drain (“D”) terminal126coupling to a node118. NVM cell106includes an S terminal132connecting to node118, G terminal136, and D terminal132coupling to a power supply such as GND (ground). Output terminal108is coupled to node118for providing an output of LMB120.

G terminal128is coupled to D terminal of transistor110while G terminal of transistor110is connected to input line116for receiving input signals. G terminal136is coupled to D terminal of transistor112and G terminal of transistor112is connected to input line116for receiving input signals. It should be noted that even though G terminals128and136are driven by similar or same input signals, the input values to NVM cell102and NVM cell106are opposite logic values due to an inversion function as indicated by numeral138.

NVM cells102-106are digital storage components capable of storing or retaining stored data even when the power supply is removed or disconnected. NVM cells102-106can be constructed via flash memory, ferroelectric RAM (“F-RAM”), magnetoresistive RAM (“MRAM”), Phase-change Memory (“PCM”), or a combination of flash, F-Ram, MRAM, and/or PCM. It should be noted that flash memory is a solid-state chip that maintains stored data without any external power source. Flash memory devices use two different technologies—NOR and NAND—to map data. NOR flash provides high-speed random access, reading and writing data in specific memory locations. NAND flash reads and writes sequentially at high speed, handling data in blocks, however it is slower on read when compared to NOR.

Ferroelectric RAM (“FeRAM, F-RAM or FRAM”) is a form of random-access memory using a capacitor and transistor. An F-RAM cell contains a thin ferroelectric film of lead zirconate titanate for changing [Pb(Zr,Ti)O3] or PZT polarity in an electric field. Due to the PZT (lead zirconate titanate) crystal maintaining polarity, F-RAM retains its data memory when power is shut off or interrupted. Due to the crystal structure and how it is influenced, F-RAM offers distinct properties from other nonvolatile memory options, including extremely high, although not infinite, endurance (exceeding 1016read/write cycles for 3.3 V devices), ultra low-power consumption (since F-RAM does not require a charge pump like other non-volatile memories), single-cycle write speeds, and gamma radiation tolerance.

MRAM stores data in magnetic storage elements called magnetic tunnel junctions (MTJs). For example, Thermal-assisted switching (TAS) type of MRAM is used for storing data. PCM stores data in chalcogenide glass, which can reversibly change the phase between the amorphous and the crystalline state, accomplished by heating and cooling of the glass. The crystalline state has low resistance and the amorphous phase has high resistance, which allow currents to be switched ON and OFF to represent digital “1” and “0” states. ReRAM or RRAM provides persistence memory storage by changing the resistance across a dielectric solid-state material, also known as a memristor.

It should be noted that Conductive bridging random access memory (“CBRAM”) is another type of NVM capable of storing digital information persistently through a process of dissolving ions in electrolyte material.

LMB120, in one example, includes a pair of NVM cells102-106wherein both NVM cells are used to store one (1) bit value, logic value, or digital information. LMB such as LMB120, for example, contains NVM cells using dual or pair NVM devices. During an operation, if NVM cell102stores a logic “1” value, NVM cell102is logic “on” as a transistor function whereby NVM cell102pulls node118to logic “1” value via Vcc. If NVM cell102is logic “on”, NVM cell106is set to logic “off” due to its stored logic “0” value. Since NVM cell106is in logic “off” or “open” status maintained by NVM cell106, the leakage current or current loss between NVM cells102to NVM cells106is minimized.

A semiconductor device, chip, or die using LMB120for power conservation includes a first NVM cell or NVM cell102, second NVM cell or NVM cell106, and an LMB output terminal or output terminal108. The first NVM cell is configured to contain an NVM transistor able to store one (1) bit of first value persistently. In one example, the first NVM cell can be a flash-based transistor, MRAM based transistor, PCM based transistor, FeRAM based transistor. RRAM based transistor, or CBRAM based transistor able for storing data persistently. The second NVM cell is configured to persistently store one (1) bit of second value which is opposite logic value of the first value. The second NVM cell can be a flash-based transistor, MRAM based transistor, PCM based transistor, FeRAM based transistor, RRAM based transistor, or CBRAM based transistor for storing data persistently. The LMB output terminal, coupling to a drain terminal of first NVM cell and a source terminal of second NVM cell, is configured to provide an output value in accordance with the first value.

In one embodiment, the semiconductor device also includes an FPGA containing configurable logic blocks (“LBs”) wherein the configurable LBs can be selectively programmed to perform user defined one or more logic functions. It should be noted that configurable LBs using its LMBs to store configuration data for programming at least a portion of the configurable LBs. In one example, a system or computing system uses LMBs to provide various digital processing functions and/or network communications.

An advantage of using an LMB to store one bit information is to achieve power conservation especially in FPGA and/or PLD devices. For example, since each FPGA device requires large number of memory cells, substituting LMB for each traditional six-transistor memory cell can reduce overall leakage current. The LMB such as LMB120can also be used to replace 1-transistor 1-resistor (1T1R) memory cell for facilitating low-power operations.

FIG.2is a block diagram200illustrating an embodiment of LMB used in an array of memory storage with low-power operations in accordance with one embodiment of the present invention. Diagram200illustrates LMB202and LMB204wherein LMB202shows an array of memory using various NVM cells such as LMB1-LMB4used in FPGA for storing digital information such as configuration data for low-power operations. LMB204illustrates a simplified version of a logic illustration having a similar output as LMB202. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram200.

LMB202, which represents a memory array, includes four (4) cell blocks250-258, select lines (S1, S2. . . )210-212, word lines (WL0, WL1, . . . )222-226, and bit lines (B1, B2. . . )216-218, and an output block230. Cell blocks250-258include LMBs and transistors Q1-Q4wherein transistors Q1-Q4are used to handle word lines such as WLs222-226as well as select lines210-212. Each of LMB1-LMB4, in one embodiment, includes dual or a pair of NVM cells wherein each pair of NBM cells are used for storing one logic value. Bit lines216-218, in one example, are configured to couple to terminals of LMBs such as LMB1-LMB4.

Output block230includes a transistor Q5and invertor236, wherein transistor Q5is configured to receive input232. In one embodiment, input232is logic active or “on” indicating FPGA functional mode. The input terminal of invertor236is coupled to word line222and the output terminal of invertor236provides an output O1. Depending on the applications, multiple output blocks such as output block230are required for handling multiple word lines as well as bit lines.

LMB204is a logic illustration used in one or more cell blocks such as cell blocks250and256having an output terminal O1. LMB204includes NVM cells270-272capable of providing a low-power operation for an FPGA chip or die using two NVM cells to maintain one logic value. In one example, transistor Q5of LMB204is used to control or manage the FPGA modes such as configuration mode or user data mode.

In operation, transistor Q5of LMB202is used to facilitate the management of FPGA functions. During a mode of configuration, output O1provide an output value based on designated or configured LMB(s) such as LMB250. In one aspect, word lines222-226, select lines210-212, and bit lines216-218are used for configuring or programming LMBs such as LMB1-LMB4. After programming LMBs such as LMB1-LMB2, the word lines such as WL0222and WL1226are set to be inactive or logic zero so that transistors Q1-Q4will be off. Accordingly, the stored values in LMBs such as LMB1-LMB4control the output of LMBs. When LMB1-LMB2, for instance, containing transistors Q2and Q4are turned off, LMB2and LMB4decide the output value of LMBs.

An advantage of using LMBs is to minimize leakage current which conserves the power consumption of FPGA.

FIG.3illustrates embodiments of logic operations of LMB using a pair of NVM cells in accordance with one embodiment of the present invention. LMB302or306includes NVM cell1, NVM cell2, and an output terminal310. LMB302or306, in one example, is coupled to a control circuit312for managing LMB302or306. A function of LMB302is to provide and maintaining an output value with minimal power loss. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram300.

A process of facilitating a cell block containing LMB302for outputting and/or maintaining a logic value includes storing a logic one (1) value to a first NVM device or NVM cell1wherein one terminal of the first NVM device such as the source terminal of NVM cell1is coupled to Vcc and another terminal of the first NVM device such as the drain terminal of NVM cell1is coupled to an output terminal of the NVM block such as output terminal310. A logic zero (0) value is stored to a second NVM device such as NVM cell2. One terminal of the second NVM device such as the drain terminal of NVM cell2is coupled to a ground voltage (“GND”) and another terminal of the second NVM device such as the source terminal of NVM cell2is coupled to the output terminal such as output terminal310. The process provides a logic one (1) output value at the output terminal of the NVM block such as output terminal310with approximately zero current flowing through from the first NVM device to the second NVM device. In one embodiment, the process is implemented for storing configuration data to various NVM blocks for configuring FPGA.

In an alternative embodiment, a process of facilitating a cell block containing LMB306for outputting or maintaining a logic value includes storing a logic zero (0) value to a first NVM device such as NVM cell1wherein one terminal of the first NVM device such as the source terminal of NVM cell1is coupled to Vcc and another terminal of the first NVM device such as the drain terminal of NVM cell1is coupled to an output terminal of the dual NVM block such as output terminal310. A logic one (1) value is concurrently stored to a second NVM device such as NVM cell2wherein one terminal of the second NVM device such as the drain terminal of NVM cell2is coupled to a ground voltage (“GND”) and another terminal of the second NVM device such as the source terminal of NVM cell2is coupled to the output terminal such as output terminal310. The process is capable of providing a logic zero (0) output value at the output terminal of the NVM block such as output terminal310with approximately zero current flowing through from the first NVM device to the second NVM device.

An advantage of using LMB is to allow cell blocks or LMBs using dual or a pair of NVM cells for each logic value for power conservation in FPGA operation.

FIG.4is a block diagram400illustrating a programmable logic block (“LAB”)402containing LMBs based logic lookup table (“LUT”) in accordance with one embodiment of the present invention. LAB402includes multiple LUTs410-412, routing multiplexers430-432, and registers420-422. Each LUT receives a set of inputs and generates an output based on the inputs as well as functional configuration. For example, LUT410receives input data from terminals A1, B1, . . . . X1, and generates an output O1based on the input data as well as configuration value associated with LUT410. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram400.

IC component diagram406is an exploded-view of LUT412showing multiple memory bits, cells or units416and multiplexers418to form a configurable LUT. It should be noted that LUT412can have, for example, 2, 3, 4, 6, 8, 15, or 32 inputs LUT. LMB120, in one embodiment, is used for memory bits416for power conservation.

Depending on the applications, a large portion of LABs in PSD or FPGA can be idling (or not used) after configuration. Since each LAB contains an array of LMB based memory bits, the LAB(s) can be reconfigured to be a user memory. A random accessible LMB based memory can be configured as a user memory for power conservation.

An advantage of using LMB based LUTs is that the LUTs can remember the configured information persistently with minimal power loss until they are reprogrammed.

Programmable Semiconductor Device (PSD)

FIG.5is a block diagram500illustrating a programmable semiconductor device (“PSD”) or FPGA able to facilitate execution of user defined logic operations in accordance with one embodiment of the present invention. PSD, also known as FPGA, PIC, and/or a type of Programmable Logic Device (“PLD”), employs LMB based memory571and operations for achieving low-power operations. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram500.

PSD includes an array of configurable LBs580surrounded by input/output blocks (“IOs”)582, and programmable interconnect resources588(“PIR”) that include vertical interconnections and horizontal interconnections extending between the rows and columns of LBs580and IO582. PRI588may further include interconnecting array decoders (“IAD”) or programmable interconnection array (“PIA”). It should be noted that the terms PRI, IAD, and PIA may be used interchangeably hereinafter.

Each LB, in one example, includes programmable combinational circuitry and selectable output registers programmed to implement at least a portion of a user's logic function. The programmable interconnections, connections, or channels of interconnect resources are configured using various switches to generate signal paths between the LBs580for performing logic functions. Each IO582is programmable to selectively use an IO pin (not shown) of PSD.

PIC, in one embodiment, can be divided into multiple programmable partitioned regions (“PPRs”)572wherein each PPR572includes a portion of LBs580, some PPRs588, and IOs582. A benefit of organizing PIC into multiple PPRs572is to optimize management of storage capacity, power supply, and/or network transmission.

Bitstream of configuration data is a binary sequence (or a file) containing programming information or data for a PIC, FPGA, or PLD. The bitstream is created to reflect the user's logic functions together with certain controlling information. For an FPGA or PLD to function properly, at least a portion of the registers or flipflops in FPGA needs to be programmed or configured before it can function. It should be noted that bitstream is used as input configuration data to FPGA.

FIG.6is a block diagram illustrating a PSD operable to carry out various user-defined logic operations using LMB based memory cells620in accordance with one embodiment of the present invention. To simplify the foregoing discussion, the terms “PSD”, “PIC”, FPGA, and PLD are referring the same or similar devices and they can be used interchangeably hereinafter. Diagram600includes multiple PPRs602-608, PIA650, and regional IO ports666. PPRs602-608further includes control units610, memory612, and LBs616. Note that control units610can be configured into one single control unit, and similarly, memory612can also be configured into one single memory for storing configurations. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram600.

LBs616, also known as configurable function unit (“CFU”) include multiple logic array blocks (“LABs”)618which is also known as a configurable logic unit (“CLU”). Each LAB616, for example, can be further organized to include, among other circuits, a set of programmable logical elements (“LEs”), configurable logic slices (“CLS”), or macrocells, not shown inFIG.6. Each LAB, in one example, may include anywhere from32to612programmable LEs. IO pins (not shown inFIG.6), LABs, and LEs are linked by PIA650and/or other buses, such as buses662or614, for facilitating communication between PIA650and PPRs602-608.

Each LE includes programmable circuits such as the product-term matrix, lookup tables, and/or registers. LE is also known as a cell, configurable logic block (“CLB”), slice, CFU, macrocell, and the like. Each LE can be independently configured to perform sequential and/or combinatorial logic operation(s). It should be noted that the underlying concept of PSD would not change if one or more blocks and/or circuits were added or removed from PSD.

Control units610, also known as configuration logics, can be a single control unit. Control unit610, for instance, manages and/or configures individual LE in LAB618based on the configuring information stored in memory612. It should be noted that some IO ports or IO pins are configurable so that they can be configured as input pins and/or output pins. Some IO pins are programmed as bi-directional IO pins while other IO pins are programmed as unidirectional IO pins. The control units such as unit610are used to handle and/or manage PSD operations in accordance with system clock signals.

LBs616include multiple LABs that can be programmed by the end-user(s). Each LAB contains multiple LEs wherein each LE further includes one or more lookup tables (“LUTs”) as well as one or more registers (or D flip-flops or latches). Depending on the applications, LEs can be configured to perform user-specific functions based on a predefined functional library facilitated by the configuration software. PSD, in some applications, also includes a set fixed circuit for performing specific functions. For example, the fixed circuits include, but not limited to, a processor(s), a DSP (digital signal processing) unit(s), a wireless transceiver(s), and so forth.

PIA650is coupled to LBs616via various internal buses such as buses614or662. In some embodiments, buses614or662are part of PIA650. Each bus includes channels or wires for transmitting signals. It should be noted that the terms channel, routing channel, wire, bus, connection, and interconnection are referred to as the same or similar connections and will be used interchangeably herein. PIA650can also be used to receive and/or transmits data directly or indirectly from/to other devices via IO pins and LABs.

Memory612may include multiple storage units situated across a PPR. Alternatively, memories612can be combined into one single memory unit in PSD. In one embodiment, memory612is an NVM storage unit used for both configuration and user memory. The NVM storage unit can be, but not limited to, MRAM, flash, Ferroelectric RAM, and/or phase changing memory (or chalcogenide RAM). Depending on the applications, a portion of the memory612can be designated, allocated, or configured to be a block RAM (“BRAM”) used for storing large amounts of data in PSD.

A PSD includes many programmable or configurable LBs616that are interconnected by PIA650, wherein each programmable LB is further divided into multiple LABs618. Each LAB618further includes many LUTs, multiplexers and/or registers. During configuration, a user programs a truth table for each LUT to implement a desired logical function. For example, a four-input (16 bit) LUT receives LUT inputs from a routing structure (not shown inFIG.6). Based upon the truth table programmed into LUT during configuration of PSD, a combinatorial output is generated via a programmed truth table of LUT in accordance with the logic values of LUT inputs. The combinatorial output is subsequently latched or buffered in a register or flip-flop before the clock cycle ends.

In one embodiment, control unit610includes a configuration logic or memory using LMB620.

FIG.7is a block diagram700illustrating a routing logic or routing fabric containing programmable interconnection arrays capable of routing data and/or clock signals for facilitating low-power operations in accordance with one embodiment of the present invention. Diagram700includes control logic706, PIA702, IO pins730, and clock unit732. Control logic706provides various control functions including channel assignment, differential IO standards, and clock management. Control logic706may contain volatile memory, non-volatile memory, and/or a combination of the volatile and nonvolatile memory device for storing information such as configuration data. In one embodiment, control logic706is incorporated into PIA702. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram700.

IO pins730, connected to PIA702via a bus731, contain many programmable IO pins configured to receive and/or transmit signals to external devices. Each programmable IO pin, for instance, can be configured to input, output, and/or bi-directional pin. Depending on the applications, IO pins730may be incorporated into control logic706.

Clock unit732, in one example, connected to PIA702via a bus733, receives various clock signals from other components, such as a clock tree circuit or a global clock oscillator. Clock unit732, in one instance, generates clock signals in response to system clocks as well as reference clocks for implementing IO communications. Depending on the applications, clock unit732, for example, provides clock signals to PIA702including reference clock(s).

PIA702, in one aspect, is organized into an array scheme including channel groups710and720, bus704, and IO buses714,724,734,744. Channel groups710,720are used to facilitate routing information between LBs based on PIA configurations. Channel groups can also communicate with each other via internal buses or connections such as bus704. Channel group710further includes interconnecting array decoders (“IADs”)712-718. Channel group720includes four IADs722-728. A function of IAD is to provide configurable routing resources for data transmission.

IAD such as IAD712includes routing multiplexers or selectors for routing signals between IO pins, feedback outputs, and/or LAB inputs to reach their destinations. For example, an IAD can include up to 36 multiplexers which can be laid out in four banks wherein each bank contains nine rows of multiplexers. It should be noted that the number of IADs within each channel group is a function of the number of LEs within the LAB.

PIA702, in one embodiment, designates a special IAD such as IAD718for facilitating data transmission as well as clock signals for LMB based memory blocks.

Systems and Network Systems

FIG.8is a diagram800illustrating a system or computer using PSD with low-power operation via application of LMBs in accordance with one embodiment of the present invention. Computer system800includes a processing unit801, an interface bus812, and an input/output (“IO”) unit820. Processing unit801includes a processor802, main memory804, system bus811, static memory device806, bus control unit805, IO element830, and FPGA885. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed fromFIG.8.

Bus811is used to transmit information between various components and processor802for data processing. Processor802may be any of a wide variety of general-purpose processors, embedded processors, or microprocessors such as ARM® embedded processors, Intel® Core™ Duo, Core™ Quad, Xeon®, Pentium™ microprocessor, Motorola™ 68040, AMD® family processors, or Power PC™ microprocessor.

Main memory804, which may include multiple levels of cache memories, stores frequently used data and instructions. Main memory804may be RAM (random access memory), MRAM (magnetic RAM), or flash memory. Static memory806may be a ROM (read-only memory), which is coupled to bus811, for storing static information and/or instructions. Bus control unit805is coupled to buses811-812and controls which component, such as main memory804or processor802, can use the bus. Bus control unit805manages the communications between bus811and bus812. Mass storage memory or SSD which may be a magnetic disk, an optical disk, hard disk drive, floppy disk, CD-ROM, and/or flash memories are used for storing large amounts of data.

IO unit820, in one embodiment, includes a display821, keyboard822, cursor control device823, and low-power PLD825. Display device821may be a liquid crystal device, cathode ray tube (“CRT”), touch-screen display, or other suitable display devices. Display821projects or displays images of a graphical planning board. Keyboard822may be a conventional alphanumeric input device for communicating information between computer system800and computer operator(s). Another type of user input device is cursor control device823, such as a conventional mouse, touch mouse, trackball, or other types of the cursor for communicating information between system800and user(s).

PLD825is coupled to bus812for providing configurable logic functions to local as well as remote computers or servers through a wide-area network. PLD825and/or FPGA885are configured to facilitate low-power operation using dual NVM cells of LMBs to improve overall efficiency of FPGA and/or PLD. In one example, PLD825may be used in a modem or a network interface device for facilitating communication between computer800and the network. Computer system800may be coupled to servers via a network infrastructure as illustrated in the following discussion.

FIG.9is a block diagram900illustrating various applications of PSD (e.g., FPGA, PLD, etc.) capable of providing low-power operation using LMBs in accordance with one embodiment of the present invention. Diagram900illustrates AI server908, communication network902, switching network904, Internet950, and portable electric devices913-919. In one aspect, PSD capable of facilitating UII and/or SDB operation is used in an AI server, portable electric devices, and/or switching network. Network or cloud network902can be a wide area network, metropolitan area network (“MAN”), local area network (“LAN”), satellite/terrestrial network, or a combination of a wide-area network, MAN, and LAN. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (or networks) were added to or removed from diagram900.

Network902includes multiple network nodes, not shown inFIG.9, wherein each node may include mobility management entity (“MME”), radio network controller (“RNC”), serving gateway (“S-GW”), packet data network gateway (“P-GW”), or Home Agent to provide various network functions. Network902is coupled to Internet950, AI server908, base station912, and switching network904. Server908, in one embodiment, includes machine learning computers (“MLC”)906.

Switching network904, which can be referred to as packet core network, includes cell sites922-926capable of providing radio access communication, such as 3G (3rdgeneration), 4G, or 5G cellular networks. Switching network904, in one example, includes IP and/or Multiprotocol Label Switching (“MPLS”) based network capable of operating at a layer of Open Systems Interconnection Basic Reference Model (“OSI model”) for information transfer between clients and network servers. In one embodiment, switching network904logically couples multiple users and/or mobiles916-920across a geographic area via cellular and/or wireless networks. It should be noted that the geographic area may refer to campus, city, metropolitan area, country, continent, or the like.

Base station912, also known as cell-site, node B, or eNodeB, includes a radio tower capable of coupling to various user equipments (“UEs”) and/or electrical user equipments (“EUEs”). The term UEs and EUEs are referring to similar portable devices, and can be used interchangeably. For example, UEs or PEDs can be cellular phone915, laptop computer917, iPhone®916, tablets, and/or iPad® 919 via wireless communications. A handheld device can also be a smartphone, such as iPhone®, BlackBerry®, Android®, and so on. Base station912, in one example, facilitates network communication between mobile devices such as portable handheld device913-919via wired and wireless communications networks. It should be noted that base station912may include additional radio towers as well as other land switching circuitry.

Internet950is a computing network using Transmission Control Protocol/Internet Protocol (“TCP/IP”) to provide linkage between geographically separated devices for communication. Internet950, in one example, couples to supplier server938and satellite network930via satellite receiver932. Satellite network930, in one example, can provide many functions as wireless communication as well as a global positioning system (“GPS”). It should be noted that the UII and/or SDB operation enhancing efficiency of FPGA can benefit many applications, such as but not limited to, smartphones913-919, satellite network930, automobiles913, AI servers908, business907, and homes920.

The exemplary embodiment of the present invention includes various processing steps, which will be described below. The steps of the embodiment may be embodied in machine or computer-executable instructions. The instructions can be used to cause a general-purpose or special-purpose system, which is programmed with the instructions, to perform the steps of the exemplary embodiment of the present invention. Alternatively, the steps of the exemplary embodiment of the present invention may be performed by specific hardware components that contain hard-wired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

FIG.10is a flowchart1000illustrating a process of storing or maintaining one (1) bit information using two NVM cells in accordance with one embodiment of the present invention. At block1002, the process for storing digital information in a configurable device such as FPGA via LMB using NVM cells can program a first NVM cell of an NVM memory block or LMB to persistently contain a first logic value in accordance with an input signal. In one example, a second logic value which represents opposite logic value of the first logic value is identified or obtained.

At block1004, a second NVM cell of the NVM memory block or LMB is configured storing the second logic value persistently in accordance with the input signal.

At block1006, the process is capable of identifying an output terminal of the NVM memory block or LMB which is coupling to the first and second NVM cells.

At block1008, an output value is provided and/or maintained at the output terminal with minimal power consumption. In one embodiment, the process can generate an output value in response to the first logic value and/or the second logic value. The process is capable of storing configuration data to NVM blocks or LMBs for configuring FPGA.