Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof

An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the field of integrated circuits, and, in particular, to integrated circuits including capacitors having different capacitor dielectrics.

2. Description of the Related Art

Integrated circuits typically include a large number of circuit elements, which form an electric circuit. In addition to active devices such as, for example, field effect transistors and/or bipolar transistors, integrated circuits may include passive devices such as resistors, inductances and/or capacitors.

Types of capacitors that may be provided in integrated circuits include metal-insulator-metal capacitors. Metal-insulator-metal capacitors may be provided in additional interconnect levels, which are provided in addition to interconnect levels wherein electrically conductive lines connecting circuit elements of integrated circuits are provided.

Metal-insulator-metal capacitors may be used as decoupling capacitors in CMOS logic integrated circuits to minimize voltage drops at the power grids. In such decoupling capacitors, thin films of a high-k dielectric material may be employed as a capacitor dielectric to obtain a high capacitance density of the decoupling capacitors and a low leakage current. Other applications of metal-insulator-metal capacitors include filter and analog capacitors, for example, in analog-to-digital converters or digital-to-analog converters, radio frequency coupling capacitors and radio frequency bypass capacitors in radio frequency oscillators, resonator circuits and matching networks.

In many applications of integrated circuits, such as integrated circuits for computers, consumer electronics, communication electronics and automotive electronics, nonvolatile embedded memory is desired. Types of nonvolatile memory include floating gate-based flash memory. However, integrating floating gate-based flash memory cells into integrated circuits that also include circuitry of another type, such as, for example, logic circuitry, may have issues associated therewith, in particular due to the relatively high process complexity of the formation of floating gate-based flash memory cells. Typically, more than eight additional photo masks may be required when floating gate-based flash memory cells are provided in an integrated circuit, in addition to photo masks that are used for forming other devices of the integrated circuit. Furthermore, in the operation of floating gate-based flash memory cells, relatively high voltages may be required, which may lead to further issues due to the need for high voltage transistors in the integrated circuit.

As an alternative to floating gate-based flash memory, other types of nonvolatile memory have been proposed, which include spin-transfer torque magnetoresistive random access memory (STT-MRAM), phase-change memory (PCM) and resistive random access memory (RRAM). However, using these techniques in embedded applications may be associated with issues related to technology maturity, cost and compatibility with processes for the manufacturing of logic circuits.

Embodiments of the present disclosure provide semiconductor structures and methods for the formation thereof which may provide an improved integration of nonvolatile memory into integrated circuits.

SUMMARY OF THE INVENTION

An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

An illustrative semiconductor structure disclosed herein includes an interlayer dielectric provided over a semiconductor substrate, a first capacitor and a second capacitor. Each of the first capacitor and the second capacitor includes a first electrode and a second electrode and is arranged over the interlayer dielectric. The semiconductor structure further includes a layer of substantially non-ferroelectric dielectric material and a layer of ferroelectric dielectric material. The layer of substantially non-ferroelectric dielectric material includes a first portion and a second portion. The first portion is arranged between the first electrode and the second electrode of the first capacitor and provides a capacitor dielectric of the first capacitor. The second portion is arranged between the interlayer dielectric and the first electrode of the second capacitor. The layer of ferroelectric dielectric material includes a first portion arranged between the first electrode and the second electrode of the second capacitor and provides a capacitor dielectric of the second capacitor.

Another illustrative method disclosed herein includes providing a semiconductor structure comprising a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a capacitor is formed over the interlayer dielectric. A layer of a ferroelectric dielectric material is formed over the first electrode. A second electrode of the capacitor is formed over the ferroelectric dielectric material.

DETAILED DESCRIPTION

The present disclosure provides a process integration scheme that allows a fabrication of both decoupling metal-insulator-metal capacitors and ferroelectric metal-insulator-metal capacitors in a standard CMOS logic process. Each of the ferroelectric metal-insulator-metal capacitors may be employed for forming a nonvolatile memory cell, wherein each of the nonvolatile memory cells includes one transistor and one ferroelectric metal-insulator-metal capacitor.

In some embodiments, the ferroelectric metal-insulator-metal capacitor may be a three-dimensional capacitor, which may help to reduce the size of the nonvolatile memory cells. This may be helpful for high density embedded ferroelectric random access memory (FRAM) applications. For forming a three-dimensional ferroelectric metal-insulator-metal capacitor, an extra masking and etching may be performed to define a narrow capacitor trench prior to the formation of a metal-insulator-metal stack.

FIG. 1shows a schematic cross-sectional view of a semiconductor structure100in a stage of a manufacturing process. The semiconductor structure100includes a substrate101. The substrate101may include a bulk semiconductor substrate, for example, a wafer or die of a semiconductor material, such as silicon. In other embodiments, the substrate101may include a semiconductor-on-insulator substrate that includes a layer of a semiconductor material, such as silicon, provided on a layer of an electrically insulating material, such as silicon dioxide. The layer of electrically insulating material may be provided on a support substrate, which may be a silicon wafer or a silicon die.

The substrate101may further include circuit elements of an integrated circuit. In particular, the substrate101may include a plurality of field effect transistors and/or other circuit elements, such as resistors and/or diodes.

The semiconductor structure100further includes an interlayer dielectric102that is provided over the substrate101. The interlayer dielectric102may include an electrically insulating material, such as silicon dioxide or a low-k dielectric material. In the interlayer dielectric102, trenches103,104,105,106may be provided. The trenches103,104,105,106may be filled with an electrically conductive material108, for example, copper or a copper alloy. A diffusion barrier layer107may be provided in each of the trenches103,104,105,106between the electrically conductive material108and the interlayer dielectric102for substantially avoiding or at least reducing a diffusion of the electrically conductive material108into the interlayer dielectric102and/or other components of the semiconductor structure100.

The trenches103,104,105,106filled with the electrically conductive material108provide electrically conductive lines which may be used for electrically connecting circuit elements, such as transistors formed at the substrate101, with other circuit elements of the semiconductor structure100, in particular with capacitors formed above the interlayer dielectric102, as will be described in more detail below. For connecting the electrically conductive lines provided by the trenches103,104,105,106filled with the electrically conductive material108with circuit elements formed at the substrate101, contact vias filled with an electrically conductive material (not shown) may be provided.

In some embodiments, the semiconductor structure100may include further interlayer dielectric layers including trenches and contact vias filled with an electrically conductive material, which are provided between the interlayer dielectric102and circuit elements formed at the substrate101.

The above-described features may be formed using known techniques for the formation of semiconductor structures. In particular, circuit elements at the substrate101may be formed by means of known semiconductor processing techniques. The interlayer dielectric102may be formed using a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and/or spin coating. The trenches103,104,105,106may be formed by means of techniques of photolithography and etching. After the formation of the trenches103,104,105,106, the diffusion barrier layer107may be deposited using deposition processes, such as CVD, PECVD and/or atomic layer deposition (ALD). Then, the electrically conductive material108may be deposited using techniques of electroplating, and portions of the diffusion barrier layer107and the electrically conductive material108outside the trenches103,104,105,106may be removed by means of chemical mechanical polishing (CMP).

After these processing steps, a capping layer109may be deposited over the electrically conductive material108in the trenches103,104,105,106and the interlayer dielectric102. The capping layer109may include silicon nitride, and it may be formed by means of a process for the deposition of silicon nitride that may be performed at a relatively low temperature, such as, for example, PECVD. In some embodiments, the deposition process for forming the capping layer109may be performed at a temperature of about 450° C. or less.

Thereafter, an interlayer dielectric110may be deposited on the capping layer109. In some embodiments, the interlayer dielectric110may include silicon dioxide, and it may be formed by means of a CVD process or PECVD process wherein tetraethyl orthosilicate (TEOS) is employed as a reactant.

After the formation of the interlayer dielectric102, a bottom electrode111of a first capacitor112may be formed over the interlayer dielectric110. The bottom electrode111may include an electrically conductive material, such as titanium nitride, tantalum nitride, tantalum and/or ruthenium. In other embodiments, the bottom electrode111may include another electrically conductive material, for example an electrically conductive material having a relatively high work function, such as iridium, iridium dioxide or ruthenium dioxide. The bottom electrode111of the first capacitor112may be provided above the trench103and above an area between the trenches103,104, but not above the trench104. Thus, above the trench104, there is a portion of the interlayer dielectric110that is not covered by the bottom electrode111of the first capacitor112. Furthermore, there are portions of the interlayer dielectric110above the trenches105,106and above an area between the trenches105,106that are not covered by the bottom electrode111of the first transistor112.

The bottom electrode111of the first capacitor112may be formed by depositing a layer of the electrically conductive material from which the bottom electrode111is formed over the interlayer dielectric110and patterning the layer of the electrically conductive material by means of processes of photolithography and etching.

FIG. 2shows a schematic cross-sectional view of the semiconductor structure100in a later stage of the manufacturing process. After the formation of the bottom electrode111, a layer of a dielectric material201may be deposited over the bottom electrode111of the first capacitor112and the portion of the interlayer dielectric110that is not covered by the bottom electrode111.

In some embodiments, the layer201of first dielectric material may be a substantially homogeneous layer of a high-k dielectric material. The high-k dielectric material may have a dielectric constant that is greater than a dielectric constant of silicon dioxide. In particular, the high-k dielectric material may have a dielectric constant greater than four.

In other embodiments, the layer201of first dielectric material may include a plurality of sub-layers, wherein at least two of the plurality of sub-layers are formed of different materials. In such embodiments, the layer201of first dielectric material may include a first sub-layer that is provided directly on the bottom electrode111of the first capacitor112and the portions of the interlayer dielectric110that are not covered by the bottom electrode111, a second sub-layer provided on the first sub-layer and a third sub-layer provided on the second sub-layer.

An enlarged schematic cross-sectional view of a portion of the semiconductor structure100after the formation of the layer201of first dielectric material in an embodiment wherein the layer201of first dielectric material includes three sub-layers is shown inFIG. 11. Therein, the first sub-layer of the layer201of first dielectric material is denoted by reference numeral1101, the second sub-layer is denoted by reference numeral1102and the third sub-layer is denoted by reference numeral1103.

The first sub-layer1101and the third sub-layer1103may be formed of substantially the same material, for example, hafnium dioxide and/or zirconium dioxide. The second sub-layer1102may be formed of a material that is different from the material of the first sub-layer1101and the third sub-layer1103, for example, aluminum oxide.

In embodiments wherein the layer201of first dielectric material is a substantially homogeneous layer of a high-k material, the layer201of first dielectric material may include tantalum pentoxide (Ta2O5).

For forming the layer201of first dielectric material, or, in embodiments wherein the layer201includes a plurality of sub-layers, processes of deposition, such as CVD, PECVD and/or ALD, may be employed.

The one or more materials that are used for forming the layer201of first dielectric material and the techniques employed for forming the layer201of first dielectric material may be adapted such that the layer201of first dielectric material is substantially non-ferroelectric.

Further features of the layer201of first dielectric material may correspond to those of known capacitor dielectrics employed in metal-insulator-metal capacitors that are provided as decoupling capacitors in integrated circuits.

After the formation of the layer201of first dielectric material, a layer202of electrically conductive material may be deposited over the layer201of first dielectric material. In some embodiments, the layer202of electrically conductive material may include titanium nitride, tantalum nitride, tantalum and/or ruthenium. In some embodiments, the layer202of electrically conductive material and the bottom electrode111of the first capacitor112may be formed of substantially the same material. For forming the layer202of electrically conductive material, deposition techniques such as CVD, PECVD and physical vapor deposition (PVD) may be employed.

FIG. 3shows a schematic cross-sectional view of the semiconductor structure100in a later stage of the manufacturing process. After the formation of the layer202of electrically conductive material, a top electrode301of the first capacitor112and a bottom electrode302of a second capacitor303may be formed from the layer202of electrically conductive material. This may be done by patterning the layer202of electrically conductive material by means of processes of photolithography and etching. Since the top electrode301of the first capacitor112and the bottom electrode302of the second capacitor303are both formed from the layer202of electrically conductive material, the top electrode301of the first capacitor112and the bottom electrode302of the second capacitor303are formed of substantially the same material.

The top electrode301of the first capacitor112may be provided over the area between the trenches103,104and over the trench104, but not over the trench103. Thus, above the area between the trenches103,104, there is a portion of the layer201of the first dielectric material that is arranged between the bottom electrode111and the top electrode301of the first capacitor112and forms a capacitor dielectric of the first capacitor112. The portions of the bottom electrode111and the top electrode301of the first capacitor112over the area between the trenches103,104may have a configuration similar to that of a plate capacitor.

The portion of the bottom electrode111above the trench103may be used for providing an electrical connection between the bottom electrode111and the electrically conductive line provided by the trench103filled with the electrically conductive material108, and the portion of the top electrode301above the trench104may be employed for providing an electrical connection between the top electrode301and the electrically conductive line provided by the trench104filled with the electrically conductive material108, as will be detailed below.

The bottom electrode302of the second capacitor303may be provided above an area between the trenches105,106and above the trench106but not above the trench105.

FIG. 4shows a schematic cross-sectional view of the semiconductor structure100in a later stage of the manufacturing process. After the formation of the top electrode301of the first capacitor112and the bottom electrode302of the second capacitor303, a layer401of a second dielectric material may be deposited. The second dielectric material may be a ferroelectric dielectric material. In some embodiments, the second dielectric material may be a material that obtains ferroelectric properties when further processing steps are performed after the deposition of the layer401of second dielectric material. Such further processing steps may include, for example, an annealing, as will be detailed below. For simplicity, the term “ferroelectric dielectric material” is sometimes used herein generally for denoting the material of the second dielectric layer401, even if the layer401is formed of a material that obtains ferroelectric properties only after further processing steps and is initially non-ferroelectric directly after its deposition.

In some embodiments, the layer401of second dielectric material may include hafnium dioxide, zirconium dioxide and/or hafnium zirconium dioxide.

The second dielectric material of the layer401may be doped. For example, in some embodiments, the layer401may include silicon-doped hafnium dioxide. Aluminum-doped hafnium dioxide, strontium-doped hafnium dioxide, yttrium-doped hafnium dioxide, gadolinium-doped hafnium dioxide and/or other rare earth-doped hafnium oxide systems may also be employed. In further embodiments, the layer401may include substantially undoped hafnium dioxide. In some embodiments, the deposition process used for depositing the second dielectric of the layer401may be adapted such that the as-deposited material is substantially amorphous and does not have ferroelectric properties.

In embodiments wherein the layer401of second dielectric includes silicon-doped hafnium dioxide, an ALD process may be performed for depositing the layer401of second dielectric material. In the ALD process, tetrakis-(ethylmethylamino)-hafnium, tetrakis-dimethylamino-silane and ozone may be employed. In some embodiments, metal organic precursors and/or halide precursors may additionally be used. The ALD process may be performed at a temperature of less than 500° C., for example, at a temperature in a range from about 200-400° C., in particular at a temperature of about 350° C. A silicon content of the layer401of second dielectric material may be in a range from about 2-5 mol %, in particular in a range from about 2.5-4.5 mol %. The silicon dioxide content of the layer401of second dielectric material may be controlled by varying the composition of gases employed in the ALD process. Depositing the layer401of second dielectric material at a relatively low temperature as described above may help to obtain an amorphous structure of the as-deposited layer401of second dielectric material.

In embodiments wherein the layer401of second dielectric material includes aluminum-doped hafnium dioxide, yttrium-doped hafnium dioxide or gadolinium-doped hafnium dioxide, an ALD process wherein tetrakis-(ethylmethylamino)-hafnium, hafnium tetrachloride as well as ozone and/or water are used may be employed. Furthermore, depending on whether the layer401of second dielectric material includes aluminum, yttrium or gadolinium, trimethylaluminum, tris(methylcyclopentadienyl)yttrium or tris(isopropylcyclopentane)gadolinium may be used. Further parameters of the ALD process may correspond to those described above in the context of embodiments wherein the layer401of second dielectric material includes silicon-doped hafnium dioxide.

In embodiments wherein the layer401of second dielectric material includes substantially undoped hafnium dioxide, a CVD process may be used for forming the layer401of second dielectric material, wherein materials and/or parameters corresponding to the embodiments described above are used but the substances provided for doping the layer401of second dielectric material are omitted.

In embodiments wherein the layer401of second dielectric material includes hafnium zirconium dioxide, an ALD process wherein tetrakis(ethylmethylamino)zirconium, tetrakis(ethylmethylamino)hafnium and ozone are used may be performed for depositing the layer401of second dielectric material. In some embodiments, the hafnium zirconium dioxide may have a composition in accordance with the formula HfxZr1-xO2, for example, a composition in accordance with the formula Hf0.5Zr0.5O2. Further parameters of the ALD process may correspond to those described above in the context of embodiments wherein the layer401of second dielectric material includes silicon-doped hafnium dioxide.

In embodiments wherein the layer401of second dielectric material includes zirconium dioxide, deposition processes similar to those described above in the context of embodiments wherein the layer401of second dielectric material includes hafnium dioxide may be used, wherein reactants including zirconium are employed instead of reactants including hafnium. In particular, tetrakis(ethylmethylamino)zirconium may be used instead of tetrakis(ethylmethylamino)hafnium, and zirconium tetrachloride may be used instead of hafnium tetrachloride.

After the deposition of the layer401of second dielectric material, a top electrode402of the second capacitor303may be formed. For forming the top electrode402of the second capacitor403, a layer of an electrically conductive material, for example a layer including titanium nitride, tantalum nitride, tantalum and/or ruthenium, may be deposited. For this purpose, deposition techniques such as CVD, PECVD and/or PVD may be employed. Thereafter, techniques of photolithography and etching may be employed for patterning the layer of electrically conductive material, wherein the top electrode402of the second capacitor303is formed. In some embodiments, the electrically conductive material from which the top electrode402is formed may be substantially the same material as the materials of the bottom electrode111and the top electrode301of the first capacitor112and the bottom electrode302of the second capacitor303.

The top electrode402of the second capacitor303may be provided over the area between the trenches105,106and over the trench105but not over the trench106.

The portions of the bottom electrode302and the top electrode402above the area between the trenches105,106may have a configuration corresponding to that of a plate capacitor, wherein a portion of the layer401of second dielectric material between the bottom electrode302and the top electrode402of the second capacitor303provides a capacitor dielectric.

In some embodiments, after the deposition of the layer of electrically conductive material from which the top electrode402of the second capacitor303is formed, or after the patterning of this layer of electrically conductive material by means of photolithography and etching, an annealing process may be performed for crystallizing the layer401of second dielectric material. Due to the crystallization of the layer401of second dielectric material in the presence of the material of the top electrode402of the second capacitor303thereon, a crystal structure of at least the portion of the layer401of second dielectric material between the bottom electrode302and the top electrode402of the second capacitor303having ferroelectric properties may be obtained. The annealing process may be a rapid thermal annealing process wherein the semiconductor structure100is exposed to a temperature in a range from about 300-500° C.

After the formation of the top electrode402of the second capacitor303, an interlayer dielectric403may be deposited. In some embodiments, the interlayer dielectric403may include silicon dioxide, and it may be formed by means of a CVD process or PECVD process wherein tetraethyl orthosilicate (TEOS) is used as a reactant. As schematically illustrated inFIG. 4, after the deposition of the interlayer dielectric403, the interlayer dielectric403may have a relatively uneven surface, since the shape of the surface of the interlayer dielectric403may be influenced by the topology of the first capacitor112and the second capacitor303below the interlayer dielectric403.

FIG. 5shows a schematic cross-sectional view of the semiconductor structure100in a later stage of the manufacturing process. After the deposition of the interlayer dielectric403, a planarization process may be performed for obtaining a substantially planar surface of the interlayer dielectric403. The planarization process may be a CMP process.

Thereafter, contact vias501,502,503,504may be formed. The contact via501is provided over the trench103, the contact via502is provided over the trench104, the contact via503is provided over the trench105, and the contact via504is provided over the trench106. Each of the contact vias501,502,503,504extends through the capping layer109, the interlayer dielectric110, the layer201of first dielectric material, the layer401of second dielectric material and the interlayer dielectric403. Furthermore, each of the contact vias501,502,503,504extends through one of the electrodes111,301,302,402of the capacitors112,303. In particular, the contact via501extends through the bottom electrode111of the first capacitor112and the contact via502extends through the top electrode301of the first capacitor112. The contact via503extends through the top electrode402of the second capacitor303and the contact via504extends through the bottom electrode302of the second capacitor303.

After the formation of the contact vias501,502,503,504, a diffusion barrier layer505may be deposited. Then, the contact vias501,502,503,504may be filled with an electrically conductive material506. The electrically conductive material506may include a metal, for example, copper or a copper alloy.

Thereafter, a CMP process may be performed for removing portions of the diffusion barrier layer505and the electrically conductive material506outside the contact vias501,502,503,504.

The contact via501filled with the electrically conductive material506provides an electrical connection between the bottom electrode111of the first capacitor112and the trench103filled with the electrically conductive material108. The contact via502filled with the electrically conductive material506provides an electrical connection between the top electrode301of the first capacitor112and the trench104filled with the electrically conductive material108. The contact via503filled with the electrically conductive material506provides an electrical connection between the top electrode402of the second capacitor303and the trench105filled with the electrically conductive material108. The contact via504filled with the electrically conductive material506provides an electrical connection between the bottom electrode302of the second capacitor303and the trench106filled with the electrically conductive material108. Thus, the electrically conductive lines provided by the trenches103,104,105,106filled with the electrically conductive material108may be employed for electrically connecting the first capacitor112and the second capacitor303to other portions of the semiconductor structure100.

In particular, the first capacitor112may be used as a decoupling capacitor connected between electrically conductive lines in a power grid of an integrated circuit formed in the semiconductor structure100, similar to decoupling capacitors in known integrated circuits. The second capacitor303that includes a ferroelectric capacitor dielectric provided by the portion of the layer401of second dielectric material may be used for storing a bit of data in a nonvolatile memory cell, as will be described in more detail below.

The present disclosure is not limited to embodiments wherein the bottom electrode302and the top electrode402of the second capacitor303are substantially planar, as described above with reference toFIGS. 1-5. In other embodiments, the second capacitor303may be a three-dimensional metal-insulator-metal capacitor. In the following, such embodiments will be described with reference toFIGS. 6-9.

For convenience, inFIGS. 1-5, on the one hand, andFIGS. 6-9, on the other hand, like reference numerals are used to denote like components. Unless explicitly stated otherwise, features of components of the embodiments described with reference toFIGS. 6-9may correspond to features of components of the embodiments described with reference toFIGS. 1-5denoted by like reference numerals, and corresponding methods may be used for the formation thereof.

FIG. 6shows a schematic cross-sectional view of a semiconductor structure600according to an embodiment in a stage of a manufacturing process according to an embodiment. Similar to the semiconductor structure100described above with reference toFIGS. 1-5, the semiconductor structure600includes a substrate101and an interlayer dielectric102. In the interlayer dielectric102, trenches103,104,105,106filled with an electrically conductive material108are formed. A diffusion barrier layer107may be provided for substantially avoiding or at least reducing a diffusion of the electrically conductive material108into other portions of the semiconductor structure600. On the interlayer dielectric102and the trenches103,104,105,106filled with the electrically conductive material108, a cap layer109may be provided. On the cap layer109, an interlayer dielectric110may be provided.

In the interlayer dielectric110, a trench601may be formed. This may be done by means of techniques of photolithography and etching. The trench601may be arranged above an area between the trenches105,106but not above the trenches105,106themselves. In some embodiments, the trench601may extend through the interlayer dielectric110to the cap layer109. In such embodiments, the cap layer109may be used as an etch stop layer in the formation of the trench601. In other embodiments, the trench601may extend through the cap layer109into the interlayer dielectric102.

The semiconductor structure600may further include a bottom electrode111of a first capacitor112, a layer201of first dielectric material and a layer202of electrically conductive material. The layer201of first dielectric material may be provided over the bottom electrode111of the first capacitor112, and over portions of the interlayer dielectric110that are not covered by the bottom electrode111. In particular, the layer201of first dielectric material may be provided on a top surface of the interlayer dielectric110, on sidewalls of the trench601, and at a bottom of the trench601.

The semiconductor structure600further includes a layer202of electrically conductive material. The layer202of electrically conductive material may be provided over the layer201of first dielectric material. In particular, the layer202of electrically conductive material may be provided above the bottom electrode111of the first capacitor112as well as at the sidewalls and at the bottom of the trench601, and above portions of the interlayer dielectric110over the trenches105,106.

The present disclosure is not limited to embodiments wherein the layer201of first dielectric material is provided at the sidewalls and at the bottom of the trench601. In other embodiments, the layer202of electrically conductive material may be provided directly on the interlayer dielectric110at the sidewalls of the trench601and directly on the capping layer109at the bottom of the trench601. In such embodiments, the trench601may be formed after the formation of the layer201of first dielectric material. In embodiments wherein the layer201of first dielectric material is provided at the sidewalls and at the bottom of the trench601, the trench601may be formed before the deposition of the layer201of first dielectric material, for example, before the formation of the bottom electrode111of the first capacitor112or after the formation of the bottom electrode111.

FIG. 7shows a schematic cross-sectional view of the semiconductor structure600in a later stage of the manufacturing process. After the deposition of the layer202of electrically conductive material, the layer202of electrically conductive material may be patterned by means of processes of photolithography and etching to form a top electrode301of the first capacitor112and a bottom electrode302of a second capacitor303.

The top electrode301of the first capacitor112may have a configuration corresponding to that of the top electrode301of the first capacitor112in the embodiments described above with reference toFIGS. 1-5. The bottom electrode302of the second capacitor303may be provided at the bottom and at the sidewalls of the trench601. Additionally, the bottom electrode302of the second capacitor303may have a portion above the trench106, whereas no portion of the bottom electrode302is provided above the trench105.

After the formation of the electrodes301,302, a layer401of second dielectric material may be deposited. The layer401may cover the entire bottom electrode302of the second capacitor303, including portions at the sidewall and at the bottom of the trench601. Additionally, the layer401of second dielectric material may cover substantially horizontal portions of the layer201of first dielectric material and the bottom electrode302of the second capacitor303outside the trench601.

After the formation of the layer401of second dielectric material, an electrically conductive material701may be deposited over the semiconductor structure600. The electrically conductive material701may include titanium nitride, tantalum nitride, tantalum and/or ruthenium. The electrically conductive material701may be deposited by means of deposition techniques such as CVD, PECVD and/or PVD. An amount of the electrically conductive material701that is deposited may be adapted such that the entire trench601is filled with the electrically conductive material701. Therefore, a relatively large thickness of the electrically conductive material701may be obtained outside the trench601. Furthermore, a surface of the as-deposited electrically conductive material701may be relatively uneven, having a recess over the trench601, as shown inFIG. 7.

FIG. 8shows a schematic cross-sectional view of the semiconductor structure600in a later stage of the manufacturing process. After the deposition of the electrically conductive material701, a planarization process, for example, a CMP process, may be performed for obtaining a substantially planar surface of the electrically conductive material701and for reducing a thickness of portions of the electrically conductive material701outside the trench601. In some embodiments, the CMP process may be stopped as soon as a portion of the layer401of second dielectric material over the top electrode301of the first capacitor112is exposed.

FIG. 9shows a schematic cross-sectional view of the semiconductor structure600in a later stage of the manufacturing process. After the CMP process, the electrically conductive material701may be patterned by means of techniques of photolithography and etching for forming a top electrode402of the second capacitor303from the electrically conductive material701.

After the formation of the top electrode402of the second capacitor303, a further interlayer dielectric may be deposited over the semiconductor structure600, and contact vias filled with an electrically conductive material may be formed for providing an electrical connection between the bottom electrode111of the first capacitor112and the trench103filled with the electrically conductive material108, an electrical connection between the top electrode301of the first capacitor112and the trench104filled with the electrically conductive material108, an electrical connection between the top electrode402of the second capacitor303and the trench105filled with the electrically conductive material108, and an electrical connection between the bottom electrode302of the second capacitor303and the trench106filled with the electrically conductive material108. The formation of the further interlayer dielectric and the contact vias may be performed as described above with reference toFIGS. 4 and 5.

Similar to the embodiments described above with reference toFIGS. 1-5, the first capacitor112may be used as a decoupling capacitor in a power supply grid for an integrated circuit provided in the semiconductor structure600, and the second capacitor303may be used as a ferroelectric capacitor in a nonvolatile memory cell of the integrated circuit provided in the semiconductor structure600. Since portions of the bottom electrode302and the top electrode402of the second capacitor303are provided in the trench601, compared to the embodiments described above with reference toFIGS. 1-5, in the embodiments ofFIGS. 6-9, a capacitance of the second capacitor303per area of the semiconductor structure600may be improved.

FIG. 10shows a schematic circuit diagram of a nonvolatile memory cell1000that may be provided in the semiconductor structure100described above with reference toFIGS. 1-5or in the semiconductor structure600described above with reference toFIGS. 6-9.

The nonvolatile memory cell1000includes a capacitor1004having a ferroelectric capacitor dielectric. The capacitor1004may be provided by the second capacitor303of the semiconductor structure100described above with reference toFIGS. 1-5or the second capacitor303of the semiconductor structure600described above with reference toFIGS. 6-9.

The nonvolatile memory cell1000further includes a field effect transistor1010. The field effect transistor1010may be a field effect transistor of a known type, and it may be formed at a semiconductor material of the substrate101. The transistor1010includes a first source/drain region1005, a second source/drain region1006, and a gate electrode1007. The first source/drain region1005is electrically connected to a bitline1001, and the gate electrode1007is electrically connected to a wordline1002. The second source/drain region1006is electrically connected to one of the electrodes of the capacitor1004by an electrical connection1008. The other electrode of the capacitor1004is electrically connected to a plate line1003by a second electrical connection1009.

In some embodiments, the electrical connection1008may be provided by a contact via and a trench filled with an electrically conductive material connected to the top electrode402, and the electrical connection1009may be provided by a contact via and a trench filled with an electrically conductive material connected to the bottom electrode302. In other embodiments, the electrical connection1008may be provided by a contact via and a trench filled with an electrically conductive material connected to the bottom electrode302, and the electrical connection1009may be provided by a contact via and a trench filled with an electrically conductive material connected to the top electrode402.

The semiconductor structure100or600, respectively, may include an array of nonvolatile memory cells having a configuration corresponding to that of the nonvolatile memory cell1000, wherein the first source/drain regions of the transistors of the nonvolatile memory cells in one column of the array of nonvolatile memory cells are electrically connected to the same bitline, and the gate electrodes of the transistors of the nonvolatile memory cells in one row of the array of nonvolatile memory cells are electrically connected to the same wordline.

For accessing the nonvolatile memory cell1000, a voltage adapted for switching the transistor1010into an electrically conductive state may be applied to the wordline1002, and voltages for reading data or writing data may be applied to the bitline1001and the plate line1003. The reading of data from the nonvolatile memory cell1000and the writing of data to the nonvolatile memory cell1000may be performed in accordance with known techniques for reading data from a ferroelectric memory cell and for writing data to a ferroelectric memory cell.

Compared to semiconductor structures wherein only a decoupling capacitor having features corresponding to those of the first capacitor112in the embodiments described above with reference toFIGS. 1-9is formed, in the embodiments described above with reference toFIGS. 1-5, one additional photo mask is used for patterning a layer of electrically conductive material from which the top electrode402of the second capacitor303is formed. The patterning of the layer202of electrically conductive material for forming the bottom electrode302of the second capacitor303may be performed using the same photo mask as for forming the top electrode301of the first capacitor112, since the top electrode301of the first capacitor112, and the bottom electrode302of the second capacitor303may be formed in a common patterning process. Moreover, the contact vias503,504which are provided for providing electrical connections to the electrodes302,402of the second capacitor303may be formed in a same patterning process as the contact vias501,502which are employed for providing electrical connections to the electrodes111,301of the first capacitor112.

In the embodiments described above with reference toFIGS. 6-9, a further photo mask is used for forming the trench601, so that two masks are used for forming the second capacitor303in addition to the masks used in the formation of the first capacitor112.

For integrating floating gate-based flash memory into an integrated circuit, typically more than eight additional photo masks are required, in addition to the masks employed for forming other elements of the integrated circuit than the floating gate-based flash memory cells. Therefore, embodiments as described herein may be carried out using a reduced number of additional photo masks, which may help to reduce the costs of the manufacturing process.

Experiments performed by the inventors have shown that a polarization hysteresis may be obtained when a voltage is applied between the electrodes302,402of the second capacitor303in a semiconductor structure having features corresponding to those of the semiconductor structure100described above with reference toFIGS. 1-5, wherein the second dielectric material401included hafnium dioxide. A remnant polarization of at least about 10 μC/cm2and a low amount of leakage current could be obtained. Endurance measurements wherein a rectangular signal of +/−2.5 V was applied at a frequency of 20 kHz have shown that a ferroelectric switching between two polarization states of the capacitor dielectric of the second capacitor303may be obtained for at least five million switching cycles, and no drift in coercive voltages was obtained during the endurance testing.

The present disclosure is not limited to embodiments wherein three layers of electrically conductive material are used for forming the electrodes of a decoupling capacitor and a ferroelectric capacitor as in the embodiments described above. In other embodiments, the capacitor dielectric of the decoupling capacitor and the capacitor dielectric of the ferroelectric capacitor may be formed of the same material. In such embodiments, wherein the capacitor dielectric of the decoupling capacitor may also have ferroelectric properties, the electrodes of the decoupling capacitor and the ferroelectric capacitor may be formed in accordance with known techniques for forming metal-insulator-metal capacitors in semiconductor structures.