Erasable programmable single-poly non-volatile memory cell and associated array structure

An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.

FIELD OF THE INVENTION

The present invention relates to a non-volatile memory, and more particularly to an erasable programmable single-poly non-volatile memory cell and an associated array structure.

BACKGROUND OF THE INVENTION

As is well known, a memory cell of a non-volatile memory comprises a storage unit. For example, the storage unit is a floating gate transistor. The storage state of the memory cell is determined according to the number of charges stored in the floating gate of the floating gate transistor.

In order to be compatible with the standard CMOS manufacturing process, the memory cell of the conventional non-volatile memory is equipped with a single-poly floating gate transistor. The floating gate transistor and associated electronic devices are collaboratively formed as a single-poly non-volatile memory cell.

For example, an erasable programmable single-poly non-volatile memory is disclosed in U.S. Pat. No. 8,941,167.FIG.1Ais a schematic top view illustrating a conventional single-poly non-volatile memory cell.FIG.1Bis a schematic equivalent circuit diagram of the single-poly non-volatile memory cell as shown inFIG.1A. For succinctness, the single-poly non-volatile memory cell is referred hereinafter as a memory cell.

As shown inFIG.1A, three p-type doped regions31,32and33are formed in an N-well region NW1. In addition, a select gate34and a floating gate36formed of a polysilicon layer are spanned over the areas between the p-type doped regions31,32and33. The floating gate36is externally extended to a region beside a p-type doped region48and an n-type doped region49. The p-type doped region48and the n-type doped region49are formed in an N-well region NW2. In addition, the floating gate36is also located beside an n-type doped region53.

The conventional single-poly non-volatile memory cell comprises a select transistor Ms, a floating gate transistor MF, a p-type transistor and an n-type transistor. The select transistor Ms and the floating gate transistor MF are constructed in the N-well region NW1. The p-type transistor is constructed in the N-well region NW2. The n-type transistor is constructed in a P-well region PW (not shown), which is located under the n-type doped region53.

The p-type doped region31, the p-type doped region32, the select gate34and the N-well region NW1are collaboratively formed as the select transistor Ms. The p-type doped region32, the p-type doped region33, the floating gate36and the N-well region NW1are collaboratively formed as the floating gate transistor MF. The floating gate36and an erase gate region45are collaboratively formed as the p-type transistor. The floating gate36and an assist gate region55are collaboratively formed as the n-type transistor. In addition, the erase gate region45comprises the N-well region NW2, the p-type doped region48and the n-type doped region49. The assist gate region55comprises the P-well region PW and the n-type doped region53.

Please refer toFIG.1B. The select gate34of the select transistor Ms receives a select gate voltage VSG. The first drain/source terminal of the select transistor Ms receives a source line voltage VSL. The body terminal of the select transistor Ms receives an N-well voltage VNW1. The first drain/source terminal of the floating gate transistor MF is connected to the second drain/source terminal of the select transistor Ms. The second drain/source terminal of the floating gate transistor MF receives a bit line voltage VBL. The body terminal of the floating gate transistor MF receives the N-well voltage VNW1.

Moreover, it is regarded that the two drain/source terminals of the p-type transistor are connected to the p-type doped region48. The body terminal of the p-type transistor receives an N-well voltage VNW2. That is, the p-type transistor is formed as a metal-oxide-semiconductor capacitor CMOS1. Hereinafter, the metal-oxide-semiconductor capacitor is also referred as a MOS capacitor. The first terminal of the MOS capacitor CMOS1is connected to the floating gate36. The second terminal of the MOS capacitor CMOS1receives an erase line voltage VEL.

Similarly, it is regarded that the two drain/source terminals of the n-type transistor are connected to the n-type doped region53. The body terminal of the n-type transistor receives a P-well voltage VPW. That is, the p-type transistor is formed as a MOS capacitor CMOS2. The first terminal of the MOS capacitor CMOS2is connected to the floating gate36. The second terminal of the MOS capacitor CMOS2receives an assist gate voltage VAG.

By providing proper bias voltages as the select gate voltage VSG, the source line voltage VSL, the bit line voltage VSL, the erase line voltage VEL, the assist gate voltage VAG, the N-well voltage VNW1, the N-well voltage VNW2and the P-well voltage VPW, a program action, an erase action or a read action can be selectively performed on the non-volatile memory cell.

In the assist gate region55, the second terminal of the MOS capacitor CMOS2receives the assist gate voltage VAG. While the program action, the erase action or the read action is performed, the assist gate voltage VAGis coupled to the floating gate36in order to enhance the programming efficiency, the erasing efficiency or the reading speed of non-volatile memory cell.

In the conventional non-volatile memory cell, the assist gate region55is a MOS capacitor composed of the n-type transistor. In other words, the process of fabricating the assist gate region55is complicated. It is necessary to form the P-well region PW in a substrate and then perform the procedure of forming the n-type doped region53. In addition, the arrangement of the conventional assist gate region55also increases the size of the non-volatile memory cell.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides an array structure of erasable programmable non-volatile memory cells. The array structure is constructed in a substrate. The array structure includes an isolation structure, a first well region, a second well region, a first gate structure, a second gate structure, a third gate structure, a first doped region, a second doped region, a third doped region, a fourth doped region and a metal layer. The isolation structure is formed on the substrate. A surface of the substrate is divided into a first region and a second region by the isolation structure. The first well region is formed in the surface of the substrate corresponding to the first region. The second well region is formed in the surface of the substrate corresponding to the second region. The first gate structure and the second gate structure are formed on the surface of the first region. The first region is divided into a first doped region, a second doped region and a third doped region by the first gate structure and the second gate structure. The first gate structure is connected to a first select gate line. The second gate structure is extended externally to the second region through a surface of the isolation structure. A portion of the second region is covered by the second gate structure. The third gate structure is formed on the isolation structure and located beside a first side of the second gate structure. The first doped region is connected to a source line. The third doped region is connected to a first bit line. The fourth doped region is formed in the surface of the substrate corresponding to the second region. The fourth doped region is connected to an erase line. The metal layer is formed over the second gate structure, and electrically connected to the third gate structure. The metal layer is connected to an assist gate line. The first gate structure includes a first gate oxide layer and a first polysilicon gate layer. The second gate structure includes a second gate oxide layer and a second polysilicon gate layer. The third gate structure includes a third gate oxide layer and a third polysilicon gate layer. The first doped region, the first gate structure and the second doped region are collaboratively formed as a first select transistor. The second doped region, the second gate structure and the third doped region are collaboratively formed as a first floating gate transistor. The second gate structure and the fourth doped region are collaboratively formed as a first MOS capacitor. The second polysilicon gate layer and the third polysilicon gate layer are collaboratively formed as a first poly/poly plate capacitor. The second polysilicon gate layer and the metal layer are collaboratively formed as a first metal/poly plate capacitor. Moreover, a first memory cell of the array structure includes the first select transistor, the first floating gate transistor, the first MOS capacitor, the first poly/poly plate capacitor and the first metal/poly plate capacitor.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIGS.2A to2Gschematically illustrate the steps of a method of manufacturing a single-poly non-volatile memory cell according to a first embodiment of the present invention.FIG.2His a schematic equivalent circuit diagram of the single-poly non-volatile memory cell according to the first embodiment of the present invention. Hereinafter, the single-poly non-volatile memory cell is referred as a memory cell.

As shown inFIG.2A, an isolation structure forming step is performed. Firstly, an isolation structure such as a shallow trench isolation (STI) structure102is formed on a substrate which can be a semiconductor substrate (such as a p-type substrate (p-sub) or a n-type substrate (n-sub)), or a glass substrate, or other types of substrate. Due to the STI structure102, a region A and a region B is defined. The substrate is covered by the STI structure102. The surface of the substrate corresponding to the region A and the region B is exposed. In the subsequent steps, two serially-connected n-type transistors are formed in the region A, and an erase gate region is formed in the region B.

Then, a well region forming step is performed. As shown inFIG.2B, the region A is exposed, and a first well region, such as a P-well region PW, is formed in the surface of the substrate corresponding to the region A.

Also, another well region forming step is performed in the surface of the substrate corresponding to the region B. As shown inFIG.2C, it is a schematic cross-sectional view taken along the line a-b ofFIG.2Bafter the another well region forming step. A second well region, such as a lightly-doped P-well region LPW, is formed in the surface of the substrate corresponding to the region B, and the second well region is contact with the first well region under the STI structure102. In other embodiments, the second well region may be a P-well region PW or a N-well region NW.

Then, a gate structure forming step is performed. As shown inFIG.2D, four polysilicon gate layers113,115,117and119are formed over the substrate. In some embodiments, four gate oxide layers103,105,107and109are further formed between the surface of the substrate and the four polysilicon gate layers113,115,117and119, respectively, before the four polysilicon gate layers. Consequently, four gate structures123,125,127and129are formed.

Please refer toFIG.2Dagain. The two gate structures123and125are formed on the surface of the region A. In addition, the region A is divided into three sub-regions by the two gate structures123and125. The gate structure125is extended externally to the region B through the surface of the STI structure102. In addition, a portion of the region B is covered by the gate structure125. The polysilicon gate layer115of the gate structure125is served as a floating gate. The polysilicon gate layer113of the gate structure123is served as a select gate.

In this embodiment, the two gate structures127and129cover the STI structure102only. The two gate structures127and129are located beside two opposite sides of the gate structure125. In addition, the two gate structures127and129are not contacted with the gate structure125.

Please refer toFIG.2E. Then, a doped region forming step is performed. In an embodiment, a doping process is performed to form four n-type doped regions141,142,143and145by using the two gate structures123and125as the mask. That is, these n-type doped regions141,142and143are formed in the three sub-regions of the region A that is not covered by the two gate structures123and125. In addition, the n-type doped region145is formed in the portion of the region B that is not covered by the gate structure125.

In the region A, the gate structure123and the two n-doped regions141and142on its two sides are collaboratively formed as a select transistor. In addition, the gate structure125and the two n-doped regions142and143on its two sides are collaboratively formed as a floating gate transistor. In this embodiment, the floating gate transistor and the select transistor are n-type transistors and constructed in the P-well region PW. That is, the body terminal of the floating gate transistor and the body terminal of the select transistor are connected to the P-well region PW.

In the region B, the n-type doped region145is an erase gate region. The gate structure125is externally extended and located beside the erase gate region. Consequently, the erase gate region and the gate structure125are collaboratively formed as an n-type transistor. In addition, the n-type transistor is connected as a MOS capacitor.

Please refer toFIG.2F. Then, a metal layer150is formed over the polysilicon gate layer115but not contacted with the polysilicon gate layer115. The metal layer150is electrically connected to the two polysilicon gate layers117and119. After a step of forming metal conductor lines is completed, the memory cell of the first embodiment is fabricated. That is, the n-type doped region141is connected to a source line SL, the n-type doped region143is connected to a bit line BL, the n-type doped region145is connected to an erase line EL, the polysilicon gate layer113is connected to a select gate line SG, and the metal layer150is connected to an assist gate line AG. According to the embodiment of the invention, at least 50% area of the polysilicon gate layer115overlaps with the metal layer150. In other words, at least 50% of the area of the polysilicon gate layer115is overlapped by the projection of the metal layer150.

FIG.2Gis a schematic cross-sectional view illustrating the resulting structure ofFIG.2Fand taken along the line c-d. In this embodiment, the gate structures127and129are disposed on the surface of the STI structure102. In addition, the metal layer150is located over the polysilicon gate layer115and electrically connected to the two polysilicon gate layers117and119. Consequently, the polysilicon gate layer115and the polysilicon gate layer117are collaboratively formed as a first poly/poly plate capacitor, and the polysilicon gate layer115and the polysilicon gate layer119are collaboratively formed as a second poly/poly plate capacitor. In addition, the polysilicon gate layer115and the metal layer150are collaboratively formed as a metal/poly plate capacitor.

As shown inFIG.2H, the memory cell of the first embodiment comprises a select transistor Ms, a floating gate transistor MF, a MOS capacitor CMOS, a first poly/poly plate capacitor CP1, a metal/poly plate capacitor CP2and a second poly/poly plate capacitor CP3. The first poly/poly plate capacitor CP1, the metal/poly plate capacitor CP2and the second poly/poly plate capacitor CP3are connected with each other in parallel.

The gate terminal of the select transistor MS is connected to the select gate line SG. The first drain/source terminal of the select transistor Ms is connected to the source line SL. The first drain/source terminal of the floating gate transistor MF is connected to the second drain/source terminal of the select transistor MS. The second drain/source terminal of the floating gate transistor MF is connected to the bit line BL.

The first terminal of the MOS capacitor CMOSis connected to the floating gate115. The second terminal of the MOS capacitor CMOSis connected to the erase line EL. The first terminal of the first poly/poly plate capacitor CP1is connected to the floating gate115. The second terminal of the first poly/poly plate capacitor CP1is connected to the assist gate line AG. The first terminal of the metal/poly plate capacitor CP2is connected to the floating gate115. The second terminal of the metal/poly plate capacitor CP2is connected to the assist gate line AG. The first terminal of the second poly/poly plate capacitor CP3is connected to the floating gate115. The second terminal of the second poly/poly plate capacitor CP3is connected to the assist gate line AG.

As mentioned above, an assist gate region of the memory cell of the first embodiment is composed of the three plate capacitors CP1, CP2and CP3. The structures and the fabricating processes of the plate capacitors CP1, CP2and CP3are simple. In addition, the uses of the plate capacitors CP1, CP2and CP3can effectively reduce the size of the memory cell.

FIG.3Ais a bias voltage table illustrating the bias voltages for performing a program action, an erase action and a read action on the memory cell according to the first embodiment of the present invention.FIG.3Bis a schematic circuit diagram the operations of performing the program action on the memory cell according to the first embodiment of the present invention.FIG.3Cis a schematic circuit diagram the operations of performing the erase action on the memory cell according to the first embodiment of the present invention.FIG.3Dis a schematic circuit diagram the operations of performing the read action on the memory cell according to the first embodiment of the present invention.

While the program action (PGM), the erase action (ERS) and the read action (Read) are performed, the P-well region and the source line SL receive a ground voltage (0V). Moreover, the assist gate line voltage VAGis higher than the erase voltage VEE, the erase voltage VEEis higher than the program voltage VPP, the program voltage VPPis higher than the read voltage VR, and the read voltage VRis higher than the ground voltage (0V). For example, the assist gate line voltage VAGis 15V, the erase voltage VEEis 12V, the program voltage VPPis 9V, and the read voltage VRis 5V.

Please refer toFIG.3B. While the program action is performed, the bit line BL receives a program voltage VPP, the select gate line SG receives the program voltage VPP, the erase line EL receives a voltage between the ground voltage (0V) and the erase voltage VEE, and the assist gate line AG receives a voltage between the ground voltage (0V) and the assist gate line voltage VAG.

While the program action is performed, the select transistor Ms is turned on, and a program current IP is generated between the bit line BL and the source line SL. When the hot carriers (e.g., electrons) of the program current IP flow through a channel region corresponding to the floating gate115, a channel hot effect (CHE) effect is generated. Due to the CHE effect, the hot carriers are injected into the floating gate115. The voltage received by the assist gate line AG is helpful to increase the number of the hot carriers injected into the floating gate115. Consequently, the programming efficiency is enhanced.

According to the present invention, since the polysilicon gate layer119and117are formed over the STI structure102, a higher assist gate line voltage VAGcan be supplied to the metal layer150and polysilicon gate layers119,117to effectively improve the coupling ratio during the program action (PGM). In comparison with the present memory cell and the conventional memory cell, when the two assist gate regions have the same size, the memory cell of the present invention has a better coupling ratio. In other words, the size of the present memory cell can be reduced when the two assist gate regions have the same coupling ratio.

Please refer toFIG.3C. While the erase action is performed, the bit line BL receives the ground voltage (0V), the select gate line SG receives the ground voltage (0V), the erase line EL receives the erase voltage VEE, and the assist gate line AG receives a voltage between the negative value of the assist gate line voltage −VAGand the ground voltage (0V).

While the erase action is performed, the select transistor MS is turned off. Under this circumstance, a Fowler-Nordheim Tunneling (FN) effect is generated between the two terminals of the MOS capacitor CMOS. Consequently, hot carriers are ejected from the floating gate115to the erase line EL. The voltage received by the assist gate line AG is helpful to increase the speed of ejecting the hot carriers from the floating gate115. Consequently, the erasing efficiency is enhanced.

Please refer toFIG.3D. While the read action is performed, the bit line BL receives the read voltage VR, the source line SL receives the ground voltage (0V), the select gate line SG receives the read voltage VR, the erase line EL receives the ground voltage (0V), and the assist gate line AG receives a voltage between the negative and the positive value of the assist gate line voltage VAG(i.e. — VAG˜VAG). According to the voltage received by the assist gate line AG, the magnitude of a read current IRis correspondingly adjusted.

While the read action is performed, the select transistor MS is turned off, and the read current IRis generated between the bit line BL and the source line SL. The storage state of the memory cell can be determined according to the magnitude of the read current IR. For example, in case that the electrons are stored in the floating gate115, the magnitude of the read current IRis very low (e.g., nearly zero). Consequently, it is determined that the memory cell is in a first storage state. Whereas, in case that no electrons are stored in the floating gate115, the magnitude of the read current IRis very high. Under this circumstance, it is determined that the memory cell is in a second storage state.

Moreover, plural memory cells of the first embodiment can be collaboratively formed as an array structure.

FIG.4Ais a schematic top view illustrating an array structure of with plural memory cells of the first embodiment.FIG.4Bis a schematic circuit diagram illustrating the equivalent circuit of the array structure as shown inFIG.4A. The array structure comprises four memory cells in a 2×2 array. The array structure is connected to the source line SL, the select gate lines SG1, SG2, the bit lines BL1, BL2, the erase line EL and the assist gate line AG. The array structure comprises plural n-type doped regions411,412,413,414,415,416,431,432,433,434,435, plural polysilicon gate layers423,425,427,429,443,445,447,449,452,454,456,458, and a metal layer560. The metal layer560is indicated by oblique lines.

The structure of each memory cell is similar to that ofFIG.2F. For succinctness, only the structure of the memory cell c11will be described as follows, and the structures of the other memory cells are not redundantly described herein. In the memory cell c11, the polysilicon gate layer423and the two n-doped regions411and412are collaboratively formed as a select transistor, and the polysilicon gate layer425and the two n-doped regions412and413are collaboratively formed as a floating gate transistor. In addition, the polysilicon gate layer425and the n-doped region416are collaboratively formed as an n-type transistor, and the n-type transistor is connected as a MOS capacitor. The polysilicon gate layer425and the polysilicon gate layer454are collaboratively formed as a first poly/poly plate capacitor. The polysilicon gate layer425and the polysilicon gate layer452are collaboratively formed as a second poly/poly plate capacitor. The polysilicon gate layer425and the metal layer560are collaboratively formed as a metal/poly plate capacitor.

The n-type doped region411is connected to the source line SL. The n-type doped region413is connected to the bit line BL. The polysilicon gate layer423is connected to the select gate line SG. The n-type doped region416is connected to the erase line EL. The metal layer560is connected to the polysilicon gate layers452and454. The metal layer560is connected to the assist gate line AG.

The equivalent circuit of the array structure is shown inFIG.4B. The array structure comprises four memory cells c11˜c22in a 2×2 array. The structures of these memory cells c11˜c22are identical. For succinctness, only the structure of the memory cell c11will be described as follows, and the structures of the other memory cells are not redundantly described herein. The first poly/poly plate capacitor, the second poly/poly plate capacitor and the metal/poly plate capacitor of the memory cell c11are connected with each other in parallel. Consequently, an equivalent plate capacitor CPthof these plate capacitors is shown in the drawing.

The connecting relationships between associated components of the memory cells c11will be described as follows. The first drain/source terminal of the select transistor Ms is connected to the source line SL. The gate terminal of the select transistor Ms is connected to the select gate line SG1. The second drain/source terminal of the floating gate transistor MF is connected to the bit line BL. The first terminal of the MOS capacitor CMOSis connected to the floating gate of the floating gate transistor MF. The second terminal of the MOS capacitor CMOSis connected to the erase line EL. The first terminal of the equivalent plate capacitor CPthis connected to the floating gate of the floating gate transistor MF. The second terminal of the equivalent plate capacitor CPthis connected to the assist gate line AG.

Similarly, by providing proper bias voltages to the source line SL, the select gate lines SG1, SG2, the bit lines BL1, BL2, the erase line EL and the assist gate line AG, a program action, an erase action or a read action can be selectively performed on the memory cells c11˜c22of the array structure.

In the first embodiment, the select transistor and the floating transistor of the memory cell are n-type transistors. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in another embodiment, the n-type select transistor and floating gate transistor are replaced by p-type transistors. In addition, the memory cell and the array structure with the p-type transistors can be implemented according to the teachings of the first embodiment.

FIG.5Aschematically illustrates the structure of a variant example of the single-poly non-volatile memory cell according to the first embodiment of the present invention. In comparison with the memory cell ofFIG.2E, the select transistor and the floating gate transistor of the memory cell of this embodiment are p-type transistors. The memory cell of this embodiment is constructed in a first well region, such as an N-well region NW. Also, three p-doped regions501,502and503are formed in the N-well region NW. Furthermore, a second well region (not shown), such as a N-well region NW, a lightly-doped P-well region LPW or a P-well region PW, is formed in the surface of the substrate corresponding to the region B. The lightly-doped P-well region LPW or the P-well region PW as the second well region is not contact with the N-well region NW as the first well region under the STI structure102. Also, a n-doped region504is formed in the second well region.

FIG.5Bis a bias voltage table illustrating the bias voltages for performing a program action, an erase action and a read action on the memory cell as shown inFIG.5A. In an embodiment, the assist gate line voltage VAGis higher than the erase voltage VEE, the erase voltage VEEis higher than the program voltage VPP, the program voltage VPPis higher than the read voltage VR, and the read voltage VRis higher than the ground voltage (0V). The program action (PGM), the erase action (ERS) and the read action (Read) are similar to those of the first embodiment, and not redundantly described herein.

Moreover, the memory cell of the first embodiment may be further modified to reduce the size of the memory cell or achieve the better layout configuration.FIG.6Aschematically illustrates the structure of a single-poly non-volatile memory cell according to a second embodiment of the present invention.

As mentioned above, the memory cell ofFIG.2Ecomprises the gate structures123and129. In this embodiment, the gate structure129is omitted, and the gate structure123is extended. That is, a gate oxide layer603and a polysilicon gate layer613of the gate structure623are extended from the region A to the adjacent memory cell. The other components of the memory cell of this embodiment are similar to those of the memory cell of the first embodiment, and not redundantly described herein.

In this embodiment, the polysilicon gate layer115and the polysilicon gate layer117are collaboratively formed as a poly/poly plate capacitor, and the polysilicon gate layer115and the metal layer150are collaboratively formed as a metal/poly plate capacitor.

FIG.6Bis a schematic equivalent circuit diagram of the single-poly non-volatile memory cell as shown inFIG.6A. In comparison with the equivalent circuit ofFIG.2G, only two plate capacitors CP1and CP2in the memory cell of this embodiment are connected with each other in parallel. For brevity, only the connecting relationship between these two plate capacitors will be described as follows.

The first terminal of the poly/poly plate capacitor CP1is connected to the floating gate115. The second terminal of the poly/poly plate capacitor CP1is connected to the assist gate line AG. The first terminal of the metal/poly plate capacitor CP2is connected to the floating gate115. The second terminal of the metal/poly plate capacitor CP2is connected to the assist gate line AG.

In this embodiment, the assist gate region is composed of the two plate capacitors CP1and CP2. The structures and the fabricating processes of the plate capacitors CP1and CP2are simple. In addition, the uses of the plate capacitors CP1and CP2can effectively reduce the size of the memory cell.

Similarly, the program action, the erase action and the read action can be performed on the memory cell of the second embodiment according to the bias voltage table ofFIG.3A. Of course, the n-type transistors of the memory cell of the second embodiment may be replaced by p-type transistors. Under this circumstance, the program action, the erase action and the read action can be performed on the memory cell of the second embodiment according to the bias voltage table ofFIG.5B. Similarly, plural memory cells of the second embodiment can be collaboratively formed as an array structure. The associated operations can be performed on the array structures.

FIG.6Cis a schematic top view illustrating an array structure of with plural memory cells of the second embodiment. The array structure comprises four memory cells in a 2×2 array. In this array structure, a polysilicon gate layer613of the gate structure623is shared by the select transistor in this memory cell c11and the selector transistor in an adjacent memory cell c21. The other array structure is similar to that ofFIG.4A, and is not redundantly described herein.

FIGS.7A to7Cschematically illustrate the steps of a method of manufacturing a single-poly non-volatile memory cell according to a third embodiment of the present invention. In comparison with the memory cell of the first embodiment, the memory cell of this embodiment has an L-shaped floating gate. Similar to the previous embodiments, the memory cell of the third embodiment may improve the coupling ratio during the program action (PGM).

As shown inFIG.7A, a shallow trench isolation (STI) structure702is formed on a substrate to define a region A and a region B. The substrate is covered by the STI structure702. The surface of the substrate is exposed through the region A and the region B. Then, a well region forming step is performed. Consequently, a first well region, such as a P-well region PW, is formed in the surface of the substrate corresponding to the region A. Moreover, another well region forming step is performed to form a second well region (not shown), such as a lightly-doped P-well region LPW, a P-well region PW or a N-well region NW, in the surface of the substrate corresponding to the region B.

Then, as shown inFIG.7B, three gate oxide layers703,705and707are formed on the surface of the substrate. Then, three polysilicon gate layers713,715and717are formed on the three gate oxide layers703,705and707, respectively. Consequently, three gate structures723,725and727are formed.

Please refer toFIG.7Bagain. The two gate structures723and725are formed on the surface of the region A. In addition, the region A is divided into three sub-regions by the two gate structures723and725. Moreover, the gate structure725is an L-shaped structure. The L-shaped gate structure725is bent and extended to the left side (first side) so the gate structure725does not connect with the gate structure727on the right side (second side). That is to say, the gate structure725is extended externally to the region B through the surface of the STI structure702. In addition, a portion of the region B is covered by the gate structure725. The gate structure727covers the surface of the STI structure702only. In addition, the gate structure727is located beside the second side of the gate structure725.

Then, a doping process is performed on the surface of the substrate by using the two gate structures723and725as the mask. Consequently, three n-type doped regions741,742and743are formed in the three sub-regions of the region A that is not covered by the two gate structures723and725. In addition, an n-type doped region745is formed in the portion of the region B that is not covered by the gate structure725.

In the region A, the gate structure723and the two n-doped regions741and742on its two sides are collaboratively formed as a select transistor. In addition, the gate structure725and the two n-doped regions742and743on its two sides are collaboratively formed as a floating gate transistor. The floating gate transistor and the select transistor are n-type transistors and constructed in the P-well region PW. That is, the body terminal of the floating gate transistor and the body terminal of the select transistor are connected to the P-well region PW.

In the region B, the n-type doped region745is an erase gate region. The gate structure725is externally extended and located beside the erase gate region. Consequently, the erase gate region and the gate structure725are collaboratively formed as an n-type transistor. The n-type transistor is connected as a MOS capacitor.

Please refer toFIG.7C. Then, a metal layer750is formed over the polysilicon gate layer715, and at least 50% area of the polysilicon gate layer715overlaps with the metal layer750. The metal layer750is electrically connected to the polysilicon gate layer717. After a step of forming metal conductor lines is performed, the memory cell of the third embodiment is fabricated. That is, the n-type doped region741is connected to a source line SL, the n-type doped region743is connected to a bit line BL, the n-type doped region745is connected to an erase line EL, the polysilicon gate layer713is connected to a select gate line SG, and the metal layer750is connected to an assist gate line AG.

In this embodiment, the gate structures727is disposed on the surface of the STI structure702. In addition, the metal layer750is located over the gate structure725. Consequently, the polysilicon gate layer715and the polysilicon gate layer717are collaboratively formed as a first poly/poly plate capacitor. In addition, the polysilicon gate layer715and the metal layer750are collaboratively formed as a metal/poly plate capacitor.

As mentioned above, the assist gate region of the memory cell of this embodiment is composed of two plate capacitors. The equivalent circuit of the memory cell of this embodiment is similar to that ofFIG.6B. Similarly, the program action, the erase action and the read action can be performed on the memory cell of the third embodiment according to the bias voltage table ofFIG.3A. Of course, the n-type transistors of the memory cell of the third embodiment may be replaced by p-type transistors. Under this circumstance, the program action, the erase action and the read action can be performed on the memory cell of the third embodiment according to the bias voltage table ofFIG.5B. Similarly, plural memory cells of the third embodiment can be collaboratively formed as an array structure. The associated operations can be performed on the array structures.

FIGS.8A to8Cschematically illustrate the steps of a method of manufacturing a single-poly non-volatile memory cell according to a fourth embodiment of the present invention. Like the memory cell of the third embodiment, the memory cell of this embodiment has an L-shaped floating gate.

As shown inFIG.8A, a shallow trench isolation (STI) structure802is formed in a substrate to define a region A and a region B. The substrate is covered by the STI structure802. The surface of the substrate is exposed through the region A and the region B. Then, a well region forming step is performed. Consequently, a first well region, such as P-well region PW, is formed in the surface of the substrate corresponding to the region A, and a second well region, such as lightly-doped P-well region LPW, a P-well region PW or a N-well region NW is formed in the surface of the substrate corresponding to the region B.

Then, as shown inFIG.8B, four gate oxide layers803,805,807and809are formed on the surface of the substrate. Then, four polysilicon gate layers813,815,817and819are formed on the four gate oxide layers803,805,807and809, respectively. Consequently, four gate structures823,825,827and829are formed.

Please refer toFIG.8Bagain. The two gate structures823and825are formed on the surface of the region A. In addition, the region A is divided into three sub-regions by the two gate structures823and825. Moreover, the gate structure825is an L-shaped structure. The gate structure825is extended externally to the region B through the surface of the STI structure802. In addition, a portion of the region B is covered by the gate structure825. The gate structures827and829cover the surface of the STI structure802only. In addition, the two gate structures827and829are located beside two opposite sides of the gate structure825. The two gate structures827and829are not contacted with the gate structure825.

Then, a doping process is performed on the surface of the substrate by using the two gate structures823and825as the mask. Consequently, three n-type doped regions841,842and843are formed in the three sub-regions of the region A that is not covered by the two gate structures823and825. In addition, an n-type doped region845is formed in the portion of the region B that is not covered by the gate structure825.

In the region A, the gate structure823and the two n-doped regions841and842on its two sides are collaboratively formed as a select transistor. In addition, the gate structure825and the two n-doped regions842and843on its two sides are collaboratively formed as a floating gate transistor. The floating gate transistor and the select transistor are n-type transistors and constructed in the P-well region PW. That is, the body terminal of the floating gate transistor and the body terminal of the select transistor are connected to the P-well region PW.

In the region B, the n-type doped region845is an erase gate region. The gate structure825is externally extended and located beside the erase gate region. Consequently, the erase gate region and the gate structure825are collaboratively formed as an n-type transistor. The n-type transistor is connected as a MOS capacitor.

Please refer toFIG.8C. Then, a metal layer850is formed over the polysilicon gate layer815, and at least 50% area of the polysilicon gate layer815overlaps with the metal layer850. The metal layer850is electrically connected to the two polysilicon gate layers817and819. After a step of forming metal conductor lines is performed, the memory cell of the fourth embodiment is fabricated. That is, the n-type doped region841is connected to a source line SL, the n-type doped region843is connected to a bit line BL, the n-type doped region845is connected to an erase line EL, the polysilicon gate layer813is connected to a select gate line SG, and the metal layer850is connected to an assist gate line AG.

In this embodiment, the gate structures827and829are disposed on the surface of the STI structure802. In addition, the metal layer850is located over the gate structure825. Consequently, the polysilicon gate layer815and the polysilicon gate layer817are collaboratively formed as a first poly/poly plate capacitor, and the polysilicon gate layer815and the polysilicon gate layer819are collaboratively formed as a second poly/poly plate capacitor. In addition, the polysilicon gate layer815and the metal layer850are collaboratively formed as a metal/poly plate capacitor.

As mentioned above, the assist gate region of the memory cell of this embodiment is composed of three plate capacitors. The equivalent circuit of the memory cell of this embodiment is similar to that ofFIG.6B. Similarly, the program action, the erase action and the read action can be performed on the memory cell of the fourth embodiment according to the bias voltage table ofFIG.3A. Of course, the n-type transistors of the memory cell of the fourth embodiment may be replaced by p-type transistors. Under this circumstance, the program action, the erase action and the read action can be performed on the memory cell of the fourth embodiment according to the bias voltage table ofFIG.5B. Similarly, plural memory cells of the fourth embodiment can be collaboratively formed as an array structure. The associated operations can be performed on the array structures.

From the above descriptions, the present invention provides an erasable programmable single-poly non-volatile memory cell and an associated array structure. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.