CONTROL APPARATUS AND ROBOT SYSTEM

A control apparatus includes a first board having a first memory unit containing a first work area and a first coupling area and a first processing unit executing a first program stored in the first work area, a second board having a second memory unit containing a second work area and a second processing unit executing a second program stored in the second work area, a communication interface linking the first coupling area and the second work area, and a memory medium storing a compressed file, wherein the compressed file is read out from the memory medium into the first work area, the first program is loaded in the first work area, the second program is loaded in the first coupling area, and the second program is transferred from the first coupling area to the second work area via the communication interface.

The present application is based on, and claims priority from JP Application Serial Number 2022-195806, filed Dec. 7, 2022, the disclosure of which is hereby incorporated by reference herein in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates to a control apparatus and a robot system.

2. Related Art

JP-A-2007-086920 discloses an electronic apparatus configured to activate the electronic apparatus by reading in and executing a program stored in external memory means. According to the electronic apparatus, even when a boot program stored in a read-only memory (ROM) or the ROM itself is defective, the electronic apparatus can be activated. Thereby, time and effort for repairing including replacement of the ROM may be saved.

An electronic apparatus may include a main board at least for activation and a sub-board for functionality expansion. When the electronic apparatus including the plurality of boards is activated, in related art, a program necessary for activation is once read out from external memory means into a memory of the main board, and then, a processor of the main board executes processing of loading programs for the respective boards. The loading processing is performed after the programs for the respective boards are read in a work area of the memory of the main board. Accordingly, the work area of the main board is temporarily reduced and the speed of the loading processing and the speed of the activation processing of the main board become lower. As a result, a problem that time is taken for activation of the electronic apparatus arises.

SUMMARY

A control apparatus according to an application example of the present disclosure includes a first board having a first memory unit containing a first work area and a first coupling area and a first processing unit executing a first program stored in the first work area, a second board having a second memory unit containing a second work area and a second processing unit executing a second program stored in the second work area, a communication interface linking the first coupling area and the second work area, and a memory medium storing a compressed file containing the first program and the second program, wherein the compressed file is read out from the memory medium into the first work area, the first program contained in the compressed file is loaded in the first work area, the second program contained in the compressed file is loaded in the first coupling area, and the second program is transferred from the first coupling area to the second work area via the communication interface.

A robot system according to an application example of the present disclosure includes a robot including a robot arm, and the control apparatus according to the application example of the present disclosure controlling a motion of the robot.

DESCRIPTION OF EMBODIMENTS

As below, a control apparatus and a robot system of the present disclosure will be explained in detail based on preferred embodiments shown in the accompanying drawings.

1. Robot System

First, a robot system according to an embodiment will be explained.

FIG.1is a conceptual diagram showing a robot system1according to the embodiment.

The robot system1shown inFIG.1includes a robot100, a control apparatus200(a control apparatus according to the embodiment), a teach pendant300, a personal computer350, and a display unit360.

The robot100shown inFIG.1includes a base120and a robot arm130. The robot arm130includes six arms coupled sequentially from the base120side and six joints J1 to J6 coupling between the base120and the arm and between the arms. Of the six joints J1 to J6 shown inFIG.1, the three joints J2, J3, J5 are bending joints and the other three joints J1, J4, J6 are twisting joints. Each of the joints J1 to J6 includes a motor as a drive source and an encoder for detecting a rotation amount of the motor, i.e., position information of the motor (not shown). In the specification, the motor and the encoder are combined as a servo motor. A control point showing a position of the robot arm130as an object to be controlled is set at a distal end of the robot arm130.

Note that, in the embodiment, a six-axis vertical articulated robot is exemplified as the robot100, however, the number of axes is not particularly limited, but may be more or less than six. Or, the robot100may be a horizontal articulated robot, a dual-arm robot, or a robot having another form.

An arm end132is provided at the distal end of the robot arm130, i.e., an end of the robot arm130opposite to the base120. An end effector160is attached to the arm end132. The end effector160is detachably attached. The end effector160includes e.g., a hand gripping a workpiece and a suction tool suctioning a work piece.

1.2. Control Apparatus

FIG.2is a block diagram showing a hardware configuration of the control apparatus200shown inFIG.1.

The control apparatus200shown inFIG.2includes a main board220(first board), a first sub-board240(second board), and a second sub-board260(third board). These respective boards can communicate with one another via a communication interface280.

1.2.1. Main Board

The main board220shown inFIG.2includes a printed wiring board221, a processor222(first processing unit), a system bus226, a RAM228(first memory unit), a ROM230, an input/output port232, a memory card interface234, and a memory card290(memory medium). The RAM is abbreviated for Random Access Memory and the ROM is abbreviated for Read-Only Memory.

The printed wiring board221includes an insulated substrate and wires and electrically couples attached electronic components.

The processor222realizes various functions by executing a first program loaded in the RAM228. The processor222includes e.g., a microprocessor, a core, and a processor circuit having a cache memory etc. (not shown). The microprocessor and the core include e.g., CPUs (Central Processing Units) and DSPs (Digital Signal Processors). The processor circuit includes e.g., a SoC (System on a Chip) and a SiP (System in a Package). Or, a part or all of the processor222may be formed by a device such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array).

The system bus226is a transmission route coupling between the processor222and the RAM228and ROM230for enabling mutual communication.

The RAM228temporarily stores the first program to be executed by the processor222, read-out data, etc. The RAM228includes e.g., a DRAM (Dynamic Random Access Memory).

The ROM230stores a boot program to be executed by the processor222etc. The ROM230includes e.g., an EEPROM (registered trademark) (Electrically Erasable Programmable Read-Only Memory) and a Flash ROM (Flash Read-Only Memory). Note that the ROM230may be an external memory.

The input/output port232is an interface for communication between the respective units of the main board220and another apparatus. The input/output port232includes e.g., a digital input/output port such as a USB (Universal Serial Bus), an Ethernet (registered trademark) port, and a picture output port.

The memory card interface234is an interface for the memory card290(memory medium) to be detachable. The memory card interface234reads out a file stored in the attached memory card290and writes a file in the attached memory card290. A compressed file400, which will be described later, is stored in the memory card290.

The memory card290includes e.g., various memory media such as an SD card and a USB memory. Preferably, the memory media are data-writable and non-volatile. Thereby, for example, the memory medium may be easily replaced by a memory card290storing a new compressed file400, and the new compressed file400may be introduced into the main board220easily in a short time.

Note that the memory card290is detachable and external data may be easily read in the main board220. On the other hand, the memory card290may be undetachable and, in this case, may be fixed to the control apparatus200as a mere memory medium. Further, data may be downloaded in the memory medium via a network or the like.

The first sub-board240shown inFIG.2includes a printed wiring board241, a processor242(second processing unit), a system bus246, and a RAM248(second memory unit).

The printed wiring board241includes an insulated substrate and wires and electrically couples attached electronic components.

The processor242realizes various functions by executing a second program loaded in the RAM248. The processor242includes e.g., a microprocessor, a core, and a processor circuit having a cache memory etc. (not shown). Or, a part or all of the processor242may be formed by a device such as an ASIC or an FPGA.

The system bus246enables communication between the processor242and the RAM248. The RAM248temporarily stores the second program to be executed by the processor242, read-out data, etc.

The second sub-board260shown inFIG.2includes a printed wiring board261, a processor262(third processing unit), a system bus266, and a RAM268(third memory unit).

The printed wiring board261includes an insulated substrate and wires and electrically couples attached electronic components.

The processor262realizes various functions by executing a third program loaded in the RAM268. The processor262includes e.g., a microprocessor, a core, and a processor circuit having a cache memory etc. (not shown). Or, a part or all of the processor262may be formed by a device such as an ASIC or an FPGA.

The system bus266enables communication between the processor262and the RAM268. The RAM268temporarily stores the third program to be executed by the processor262, read-out data, etc.

1.2.4. Communication Interface

The communication interface280is a transmission route for transmission of programs, data, etc., e.g., a serial communication interface such as a PCI or PCI-Express (registered trademark) or the like. In the following description, the PCI-Express is also referred to as “PCle”.

As above, the hardware configuration example of the control apparatus200is explained, however, the hardware configuration is not limited to that. For example, the second sub-board260may be omitted or another sub-board may be added.

1.2.5. Functional Units

FIG.3is a functional block diagram showing functions of the control apparatus200shown inFIG.2.

1.2.5.1. Functional Units of Main Board

The main board220shown inFIG.3has an interface control unit312, a language analysis unit314, an input/output control unit316, an interrupt control unit318, and an activation processing unit320as functional units. The functions of these respective functional units are realized by e.g., the processor222executing the first program stored in the RAM228of the main board220and the boot program stored in the ROM230depending on the hardware configuration of the main board220.

For example, the interface control unit312controls communication among the main board220, the first sub-board240, and the second sub-board260.

The language analysis unit314reads and analyzes a robot language describing a motion of the robot100. The unit receives a motion program of the robot100from the personal computer350via the input/output control unit316, which will be described later, analyzes the motion program, and acquires target position information of the robot arm130. The target position information is information on a target position as a target location to which the control point of the robot arm130is moved, e.g., data representing coordinates of the target position.

The input/output control unit316controls coupling to the teach pendant300, the personal computer350, and another peripheral device coupled to the main board220.

The interrupt control unit318controls processing of branching from a program being executed to another program (interrupt processing).

The activation processing unit320has a function of activating the main board220. The activation processing unit320has a hardware initialization section322, a program readout section324, a program certification section326, a program loading section328, and a program execution section330.

The hardware initialization section322initializes at least the main board220and the communication interface280.

The program readout section324reads out a file stored in the memory card290. Then, the program readout section324copies the read-out file in the RAM228.

FIG.4shows a file structure of overall firmware440stored in the memory card290inFIG.2. As shown inFIG.4, the overall firmware440has a main board firmware410(first program), a first sub-board firmware420(second program), and a second sub-board firmware430(third program). Each firmware is a program containing e.g., an OS (operating system), an application, data, etc. The overall firmware440is generally in a binary format, but may be in a text format.

FIG.5shows a memory map of the memory card290shown inFIG.2and a memory map of the main board220shown inFIG.2. Note that the memory map shown inFIG.5is an example and the memory map is not limited to that.

As shown inFIG.5, the RAM228of the main board220contains memory spaces including a PCle link area512(first coupling area), a peripheral area514, a work area516(first work area), and a boot area518. Of the areas, the boot area518stores a public key542and a bootloader544.

Further, as shown inFIG.5, the memory space of the memory card290is divided in a first partition291and a second partition292. The first partition291stores the compressed file400and an electronic signature405. The second partition292stores a root file system403.

The compressed file400, the electronic signature405, and the root file system403shown inFIG.5are copied in the work area516in the activation processing of the control apparatus200, which will be described later.

The program certification section326certifies the compressed file400read out in the RAM228. The certification refers to verification of integrity and authenticity of the compressed file400. In the specification, as a result of the verification, a status that the integrity and the authenticity are confirmed is referred to as “certified”.

The program loading section328loads the main board firmware410of the certified compressed file400in the work area516of the RAM228of the main board220. Further, the program loading section328loads the first sub-board firmware420and the second sub-board firmware430of the certified compressed file400in the PCle link area512of the RAM228.

The program execution section330executes the certified main board firmware410. Thereby, the main board220is activated.

Note that these functional units of the main board220are examples and may be partially omitted or partially provided on another board, and another functional unit may be added.

1.2.5.2. Functional Units of First Sub-Board

The first sub-board240shown inFIG.3has a trajectory generation unit332and an activation processing unit336as functional units. The functions of these respective functional units are realized by e.g., the processor242executing the second program stored in the RAM248of the first sub-board240depending on the hardware configuration of the first sub-board240.

The trajectory generation unit332generates a trajectory when the robot arm130is driven based on the target position information received from the main board220.

The activation processing unit336executes the certified first sub-board firmware420. Thereby, the first sub-board240is activated.

Note that these functional units of the first sub-board240are examples and may be partially omitted or partially provided in another board, and another functional unit may be added.

1.2.5.3. Functional Units of Second Sub-Board

The second sub-board260shown inFIG.3has a servo processing unit342and an activation processing unit346as functional units. The functions of these respective functional units are realized by e.g., the processor262executing the second program stored in the RAM248of the second sub-board260depending on the hardware configuration of the second sub-board260.

The servo processing unit342controls an operation of the servo motor of the robot100.

The activation processing unit346executes the certified second sub-board firmware430. Thereby, the second sub-board260is activated.

Note that these functional units of the second sub-board260are examples and may be partially omitted or partially provided in another board, and another functional unit may be added.

1.3. Activation Method for Control Apparatus

Next, an activation method for the control apparatus200shown inFIG.3is explained.

FIG.6is a flowchart for explanation of the activation method for the control apparatus200.FIGS.7to10are conceptual diagrams for explanation of the activation method shown inFIG.6.

The activation method for the control apparatus200shown inFIG.6has step S102to step S114.

After the control apparatus200is turned on, the process goes to step S102. At step S102, the program readout section324of the activation processing unit320performs processing of reading out the public key542and the bootloader544stored in the boot area518shown inFIG.5. Then, the program certification section326performs processing of certifying the public key542and the bootloader544. The certification processing is processing of verifying integrity and authenticity of the public key542and the bootloader544.

At step S104, the hardware initialization section322initializes the main board220and the communication interface280.

At step S106, the program execution section330executes the bootloader544. Thereby, preparation for execution of the firmwares is made.

At step S108, the program readout section324reads out the compressed file400, the electronic signature405, and the root file system403stored in the memory card290in the work area516.

The electronic signature405is a digital signature associated with the compressed file400. The compressed file400is a file formed by data compression of the overall firmware440. The root file system403is a root file system of each firm ware.

InFIG.7, generation processing of the electronic signature405is explained.

First, the overall firmware440is data-compressed and the compressed file400is obtained. The compressed file400is stored in the memory card290without change. The overall firmware440is compressed and stored, and thereby, data capacity of the memory card290may be reduced and time taken for reading out and loading of the stored compressed file may be reduced.

On the other hand, a hash function is executed on the compressed file400. Thereby, a hash value401is obtained. The hash function is a function of returning output data (hash value) having a fixed length from data having an arbitrary length and has a property of returning the same hash value from the same data. The hash function includes e.g., SHA-258, SHA-384, and SHA-512.

The obtained hash value401is encrypted using a secret key402. The encryption of the hash value401may be performed by e.g., a certificate authority as a certification institution using the secret key402. Thereby, the electronic signature405is obtained. The electronic signature405is stored in the memory card290.

At step S110, the program certification section326certifies the compressed file400based on the electronic signature405read out in the work area516.

InFIG.8, the certification processing of the compressed file400is explained.

First, the read-out electronic signature405is decrypted using the public key542. The public key542forms a pair with the above-described secret key402and is issued from the certificate authority in advance. By decryption, a hash value407(first hash value) is generated. On the other hand, the hash function is executed on the compressed file400. Thereby, a hash value408(second hash value) is generated. Then, the hash value407and the hash value408are compared. When the values are the same, integrity and authenticity of the compressed file400are confirmable, and thereby, the compressed file is certified. When the values are different, integrity and authenticity of the compressed file400are impaired, and thereby, the compressed file is not certified.

According to the certification processing, the certification of the compressed file400may be achieved only by comparison between the values having fixed lengths as hash values. Accordingly, the certification may be achieved in a shorter time and that contributes to shortening of the activation time of the control apparatus200. Further, it is preferable that the public key542is stored in the control apparatus200. Thereby, the certification processing may be performed in a local environment and that contributes to further shortening of the activation time.

At step S111, whether the compressed file400is certified is determined. When the compressed file is certified, the process goes to step S112. When the compressed file is not certified, the flow is ended. Thereby, the control apparatus200may be activated only when the file is certified and secure boot is realized.

At step S112, the program loading section328loads the respective firmwares from the compressed file400.

FIGS.9and10are respectively for explanation of the processing of loading the respective firmwares from the compressed file400.

As shown inFIGS.9and10, the main board220contains the PCle link area512(first coupling area), the peripheral area514, and the work area516(first work area) as the memory spaces. Of the areas, the PCle link area512contains a first sub-board link area512aand a second sub-board link area512b. The peripheral area514is a memory space provided to a peripheral device coupled to the main board220. The work area516is a memory space accessed by the processor222. Note that these memory spaces are set in e.g., the RAM228, however, may be set in another memory device. Further, the setting of the memory spaces is performed by e.g., a controller (not shown) contained in the chipset of the communication interface280.

As shown inFIG.10, the first sub-board240contains a PCle link area522(second coupling area) and a work area526(second work area) as memory spaces. Of the areas, the PCle link area522contains a second sub-board link area522b. The work area526is a memory space accessed by the processor242. Note that these memory spaces are set in e.g., the RAM248, however, may be set in another memory device.

As shown inFIG.10, the second sub-board260contains a work area536(third work area) as a memory space. The work area536is a memory space accessed by the processor262.

The first sub-board link area512ais linked to the work area526via the communication interface280.

The second sub-board link area512bis mutually linked to the second sub-board link area522band the work area536via the communication interface280.

At step S112, as shown inFIG.9, the program loading section328extracts the main board firmware410(first program) from the compressed file400and loads the firmware in the work area516of the main board220. Further, as shown inFIG.9, the program loading section328extracts the first sub-board firmware420(second program) from the compressed file400and loads the firmware in the first sub-board link area512acontained in the PCle link area512(first coupling area) of the main board220. Furthermore, as shown inFIG.9, the program loading section328extracts the second sub-board firmware430(third program) from the compressed file400and loads the firmware in the second sub-board link area512bcontained in the PCle link area512of the main board220. The loading processing is performed by e.g., the processor222or the controller (not shown) contained in the chipset of the communication interface280.

Note that, when the program loading section328performs the above-described loading, the section may load the respective firmwares remaining in the compressed conditions or in decompressed conditions.

When loaded in the compressed conditions, the firmwares may be decompressed in the respective boards.

At step S114, as shown inFIG.10, the first sub-board firmware420is transferred from the first sub-board link area512acontained in the PCle link area512(first coupling area) to the work area526(second work area) of the first sub-board240via the communication interface280.

Further, at step S114, as shown inFIG.10, the second sub-board firmware430is transferred from the second sub-board link area512bcontained in the PCle link area512(first coupling area) through the PCle link area522(second coupling area) of the first sub-board240to the work area536(third work area) of the second sub-board260via the communication interface280. The loading processing is performed by e.g., the controller (not shown) contained in the chipset of the communication interface280. Thereby, the transfer processing may be performed with the minimized load on the processor222.

In the above-described manner, the respective firmwares may be loaded in the respective work areas. Then, the respective firmwares are executed in the respective work areas, and thereby, the respective boards may be activated and the activation of the control apparatus200is completed.

As described above, not all of the compressed file400read out into the work area516of the main board220is loaded in the work area516, but only the main board firmware410is loaded in the work area516. On the other hand, the first sub-board firmware420and the second sub-board firmware430are loaded in the PCle link area512.

Then, the first sub-board firmware420is transferred from the PCle link area512to the work area526of the first sub-board240and the second sub-board firmware430is transferred from the PCle link area512through the PCle link area522to the work area536of the second sub-board260.

Thereby, the work area516of the main board220may be avoided from being occupied by the loading and the transfer of the respective firmwares. As a result, the temporal reduction of the work area516may be suppressed and the reduction of the processing speed of the processor222of the main board220may be suppressed. Further, in parallel to the operation of the processor222, the respective firmwares can be transferred. Accordingly, the reduction of the operation speed of the processor222with the transfer of the respective firmwares may be suppressed. Therefore, the activation time of the control apparatus200may be shortened using the above-described activation method.

In the control apparatus200, the system of reading out the compressed file400is employed, and therefore, compared to a case where an uncompressed firmware is read out, data capacity of the memory card290may be reduced. Thereby, the time taken to read out the firmware may be reduced.

2. Effects Exerted by Embodiment

As described above, the control apparatus200(the control apparatus according to the above-described embodiment) includes the main board220(first board), the first sub-board240(second board), the communication interface280, and the memory card290(memory medium) as shown inFIGS.1and2.

As shown inFIGS.2and10, the main board220has the RAM228(first memory area) containing the work area516(first work area) and the PCle link area512(first coupling area) and the processor222(first processing unit) executing the main board firmware410(first program) stored in the work area516.

The first sub-board240has the RAM248(second memory unit) containing the work area526(second work area) and the processor242(second processing unit) executing the first sub-board firmware420(second program) stored in the work area526.

The communication interface280links the PCle link area512and the work area526.

The memory card290(memory medium) stores the compressed file400containing the main board firmware410and the first sub-board firmware420.

Then, the control apparatus200reads out the compressed file400from the memory card290into the work area516, loads the main board firmware410contained in the compressed file400in the work area516, loads the first sub-board firmware420contained in the compressed file400in the PCle link area512, and transfers the first sub-board firmware420from the PCle link area512to the work area526via the communication interface280.

According to the configuration, the work area516of the main board220may be avoided from being occupied by the loading and the transfer of the respective firmwares. As a result, the temporal reduction of the work area516may be suppressed and the reduction of the processing speed of the processor222of the main board220may be suppressed. Further, in parallel to the operation of the processor222, the respective firmwares can be transferred. Accordingly, the reduction of the operation speed of the processor222with the transfer of the respective firmwares may be suppressed. Therefore, according to the above-described configuration, the activation time of the control apparatus200may be shortened.

Further, in the above-described embodiment, the memory card290(memory medium) stores the electronic signature405associated with the compressed file400.

It is preferable that the control apparatus200according to the above-described embodiment performs the certification processing of certifying the compressed file400based on the electronic signature405, when the compressed file is certified in the certification processing, loads the main board firmware410(first program) and the first sub-board firmware420(second program) and, when the compressed file is not certified, does not load the main board firmware410and the first sub-board firmware420.

Thereby, the secure boot of the control apparatus200may be realized. That is, the activation of the control apparatus200based on the uncertified compressed file400may be prevented.

Further, in the above-described embodiment, the certification processing has the processing of generating the hash value407(first hash value) from the electronic signature405using the public key542, the processing of generating the hash value408(second hash value) by executing the hash function on the compressed file400, and the processing of comparing the hash value407and the hash value408.

Thereby, the certification of the compressed file400may be achieved only by reading out of the two files (the electronic signature405and the compressed file400) from the memory card290and comparison between the values having fixed lengths generated from the files. Thereby, the activation time of the control apparatus200may be further shortened. Further, the public key542is stored in the control apparatus200, and thereby, the activation time may be further shortened.

In the above-described embodiment, the communication interface280is the PCI-Express interface. The PCI-Express interface includes a mechanism for performing transfer processing with suppressed loads on the processors222,242,262, e.g., bus master transfer. Thereby, in the processors222,242,262, other processing than the transfer processing may be performed in parallel. As a result, the activation time of the control apparatus200may be further shortened.

In the above-described embodiment, the control apparatus200further includes the second sub-board260(third board). The second sub-board260has the RAM268(third memory unit) containing the work area536(third work area) and the processor262(third processing unit) executing the second sub-board firmware430(third program) stored in the work area536.

The RAM248(second memory unit) further contains the PCle link area522(second coupling area) and the communication interface280mutually links the PCle link area512(first coupling area), the PCle link area522(second coupling area), and the work area536(third work area).

The control apparatus200transfers the second sub-board firmware430from the PCle link area512through the PCle link area522to the work area536via the communication interface280.

According to the configuration, even the control apparatus200having two or more expansion boards (sub-boards) may shorten the activation time. Thereby, a balance between improvements in performance and stability with function distribution and shortening of the activation time may be achieved.

The robot system1according to the above-described embodiment includes the robot100having the robot arm130and the control apparatus200(the control apparatus according to the embodiment) controlling the motion of the robot100.

According to the configuration, the robot system1that may enjoy the effects exerted by the control apparatus200and can be activated in a shorter time may be realized.

As above, the control apparatus and the robot system of the present disclosure are explained based on the illustrated embodiments, however, the present disclosure is not limited to those.

For example, in the control apparatus and the robot system of the present disclosure, the configurations of the respective parts of the above-described embodiments may be replaced by any configurations having the same functions, or any other configuration may be added. Further, the control apparatus of the present disclosure may be used for another purpose than the control of the robot.