Semiconductor device having a die and through substrate-via

Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

BACKGROUND

Consumer electronic devices, in particular, mobile electronic devices such as smart phones, tablet computers, and so forth, increasingly employ smaller, more compact components to furnish their users with desired features. Such devices often employ three dimensional integrated circuit devices (3D IC). Three-dimensional integrated circuit devices are semiconductor devices that employ two or more layers of active electronic components. Through-substrate vias (TSV) interconnect electronic components on the different layers (e.g., different substrates) of the device allowing the devices to be integrated vertically as well as horizontally. Consequently, three-dimensional integrated circuit devices can provide increased functionality within a smaller, more compact footprint than do conventional two-dimensional integrated circuit devices.

SUMMARY

Semiconductor devices are described that include a semiconductor wafer and an integrated circuit die bonded together. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the semiconductor wafer and the integrated circuit die. In implementations, the semiconductor devices are fabricated by bonding a semiconductor wafer and an integrated circuit die together using an adhesive material, such as a dielectric. The adhesive material allows for lateral expansion when the integrated circuit die is attached to the semiconductor wafer and during the bonding process. For example, an integrated circuit die may be bonded to a semiconductor wafer by applying adhesive material to a second (e.g., backside or bottom) surface of the semiconductor wafer. The adhesive material may then be used to bond the integrated circuit die to the second (e.g., backside or bottom) surface of the semiconductor wafer. Vias may then be formed through the semiconductor wafer and the patterned adhesive material to furnish electrical interconnection between the semiconductor wafer and the integrated circuit die. The semiconductor wafer may then be segmented into individual semiconductor devices.

DETAILED DESCRIPTION

Overview

Three-dimensional integrated circuit devices are commonly manufactured using die-on-wafer techniques wherein electronic components (e.g., circuits) are first fabricated on two or more semiconductor wafers. The individual die are aligned on and attached to semiconductor wafers and segmented to provide individual devices. Through-substrate vias (TSV) are either built into wafers before they are attached, or else created in the wafer stack after attachment. However, the fabrication of three-dimensional integrated circuit devices requires additional manufacturing steps to join the die and wafers together. This increases the cost of the devices. Moreover, each extra manufacturing step adds a risk for inducing defects, possibly reducing device yield.

Accordingly, techniques are described to fabricate semiconductor devices having multiple, stacked die on a substrate (e.g., a semiconductor wafer) in a reliable, production-worthy way. In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include a die bonded to the backside of a semiconductor wafer with an adhesive material. The die and semiconductor wafer include one or more integrated circuits formed therein. Through-substrate vias (TSV) are formed through the semiconductor wafer and the adhesive material is disposed between the die and the semiconductor wafer. The through-substrate vias in the semiconductor wafer include a conductive material, such as copper, that furnishes electrical interconnection between the integrated circuits in the semiconductor wafer and the die. It is contemplated that more than one die may be provided for attaching to the semiconductor wafer.

In implementations, a wafer-level package device that employs example techniques in accordance with the present disclosure includes bonding a carrier wafer to a processed semiconductor wafer, using an adhesive material to attach an integrated circuit die to a second side of the processed semiconductor wafer, removing the carrier wafer, and forming a through-silicon via in the processed semiconductor wafer, where the through-silicon via furnishes an electrical connection between the processed semiconductor wafer and the integrated circuit die. Additionally, the integrated circuit die may be placed in a cavity on the second side (e.g., the backside) of the semiconductor wafer or may be covered by a cap wafer placed over the integrated circuit die and on the second side of the processed semiconductor wafer. The processed semiconductor wafer may then be segmented into individual semiconductor devices.

Example Implementations

FIG. 1illustrates a semiconductor semiconductor device100in accordance with example implementations of the present disclosure. As shown, the semiconductor semiconductor device100is illustrated at wafer level prior to singulation of the semiconductor semiconductor device100. The semiconductor semiconductor device100includes a semiconductor wafer102. The semiconductor wafer102includes one or more integrated circuits (not shown), which are formed within the semiconductor wafer102. As illustrated inFIG. 1, the semiconductor wafer102further includes one or more alignment marks106. The alignment marks106may be utilized to align the semiconductor wafer102with a carrier wafer (described herein below). Additionally, the alignment marks106may be utilized to indicate a location for forming a through-silicon via130, further described below. The semiconductor wafer102includes a first (e.g., top or front) surface and a second (e.g., bottom or backside) surface. The integrated circuits are formed (e.g., fabricated) proximate to the first surface of the semiconductor wafer102. It is contemplated that the first and/or the second surface of the semiconductor wafer102may be planarized or unplanarized.

The semiconductor wafer102include a base material utilized to form one or more integrated circuit devices through various fabrication techniques such as photolithography, ion implantation, deposition, etching, and so forth. The semiconductor wafer102may be configured in a variety of ways. For example, the semiconductor wafer102may comprise an n-type silicon wafer or a p-type silicon wafer. In an implementation, the semiconductor wafer102may comprise group V elements (e.g., phosphorus, arsenic, antimony, etc.) configured to furnish n-type charge carrier elements. In another implementation, the semiconductor wafer102may comprise group IIIA elements (e.g., boron, etc.) configured to furnish p-type charge carrier elements. Further, the integrated circuits may be configured in a variety of ways. For example, the integrated circuits may include digital integrated circuits, analog integrated circuits, mixed-signal circuits, and so forth. In one or more implementations, the integrated circuits may include digital logic devices, analog devices (e.g., amplifiers, etc.), combinations thereof, and so forth. As described above, the integrated circuits may be fabricated utilizing various fabrication techniques. For example, the integrated circuits may be fabricated via complimentary metal-oxide-semiconductor (CMOS) techniques, bi-polar semiconductor techniques, and so on.

As shown inFIG. 1, the semiconductor semiconductor device100also includes one or more area arrays of conductive layers116of the semiconductor wafer102. In an implementation, the conductive layers116may comprise one or more conductive (e.g., contact) pads, redistribution structures, or the like. In a further implementation, the conductive layers116may include seed metal and/or barrier metal layers to allow for plated-line formation. The number and configuration of conductive layers116may vary depending on the complexity and configuration of the integrated circuits, and so forth. The conductive layers116provide electrical contacts through which the integrated circuits are interconnected to other components, such as printed circuit boards (not shown), when the semiconductor devices100are configured as wafer-level packaging (WLP) devices or other integrated circuits disposed within the semiconductor semiconductor device100. In one or more implementations, the conductive layers116may comprise an electrically conductive material, such as a metal material (e.g., aluminum, copper, etc.), or the like.

The conductive layers116may furnish electrical interconnection between various electrical components associated with the semiconductor semiconductor device100. For instance, a first conductive layer116deployed over the semiconductor wafer102may furnish an electrical interconnection to a second conductive layer116deployed over another device (e.g., an integrated circuit die140). In another instance, a conductive layer116deployed over the semiconductor wafer102may provide electrical interconnection with one or more solder bumps118. Solder bumps118are provided to furnish mechanical and/or electrical interconnection between the conductive layers116and corresponding pads (not shown) formed on the surface of a printed circuit board (not shown) or another semiconductor device. In one or more implementations, the solder bumps118may be fabricated of a lead-free solder such as a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder (i.e., SAC), a Tin-Silver (Sn—Ag) alloy solder, a Tin-Copper (Sn—Cu) alloy solder, and so on. However, it is contemplated that Tin-Lead (PbSn) solders may be used.

Bump interfaces120may be applied to the conductive layers116to provide a reliable interconnect boundary between the conductive layers116and the solder bumps118. For instance, in the semiconductor semiconductor device100shown inFIG. 1, the bump interface120comprises under-bump metallization (UBM)122applied to the conductive layers116of the integrated circuit chip102. The UBM122may have a variety of compositions. For example, the UBM122include multiple layers of different metals (e.g., Aluminum (Al), Nickel (Ni), Copper (Cu), etc.) that function as an adhesion layer, a diffusion barrier layer, a solderable layer, an oxidation barrier layer, and so forth. However, other UBM structures are possible.

In one or more implementations, the semiconductor semiconductor device100may employ a Redistribution Layer (“RDL”) configuration. The RDL configuration employs a redistribution structure124comprised of a thin-film metal (e.g., aluminum, copper, etc.) rerouting and interconnection system that redistributes the conductive layers116to an area array of bump interfaces120(e.g., UBM pads) that may be more evenly deployed over the surface of the semiconductor semiconductor device100. The solder bumps118are subsequently placed over these bump interfaces120to form bump assemblies126.

As illustrated inFIG. 1, the redistribution layer124may include wings124A,124B to provide further structural support to the solder bumps118. The structural support may reduce the stress to the semiconductor semiconductor device100, which may prevent the cracking of the semiconductor semiconductor device100during various testing phases (e.g., temperature cycling, drop testing, etc.). In one or more implementations, the wings124A,124B provide a redistribution layer124extension that may extend to approximately the width (W) of the solder bump118. However, it is contemplated that the wings124A,124B may extend beyond (e.g., greater than) the width (W) of the solder bumps118in some implementations and may not extend (e.g., less than) the width (W) of the solder bumps118in other implementations. It is contemplated that the extension of the wings124A,124B may vary depending on the various characteristics of the semiconductor semiconductor device100, such as the structural requirements of the semiconductor semiconductor device100, the power requirements of the semiconductor semiconductor device100, and so forth.

WhileFIG. 1illustrates a semiconductor semiconductor device100that employs a Redistribution Layer (“RDL”) configuration, it is contemplated that the semiconductor semiconductor device100illustrated and described herein may also employ a Bump-On-Pad (“BOP”) configuration. The BOP configuration may employ a conductive layer116disposed under the bump interface120(e.g., UBM pads).

Viewed together, the solder bumps118and associated bump interfaces120(e.g., UBM122) comprise bump assemblies126that are configured to provide mechanical and/or electrical interconnection of the integrated circuits formed in the semiconductor wafer102to the printed circuit board (not shown).

The semiconductor semiconductor device100further includes an adhesive material128disposed on a second side (e.g., the backside or side opposite the formed integrated circuits) of the semiconductor wafer102. The adhesive material128is configured to bond the semiconductor wafer102and the integrated circuit die140once the integrated circuit die140is placed on the semiconductor wafer102. The adhesive material128may be configured in a variety of ways. For example, the adhesive material128may be an adhesive dielectric material such as benzocyclobutene (BCB), or the like. In one implementation, the adhesive material128is configured to be patterned (e.g., not continuous) to allow for lateral expansion when the adhesive material128is pressed vertically (e.g., the integrated circuit die140is brought into contact with the adhesive material128) for bonding purposes. In this implementation, the patterned adhesive material128is coated at least partially over the second surface of the semiconductor wafer102and then patterned to allow the adhesive material128to reflow laterally during the bonding procedure. Moreover, the adhesive material128may function to planarize the second surface of the semiconductor wafer102(e.g., when the semiconductor wafer102is non-planarized) during reflow of the adhesive material128.

The semiconductor device100includes an integrated circuit die140that is attached to the second side (e.g., backside) of the semiconductor wafer102. In embodiments, the integrated circuit die140includes a conductive pad116(e.g., a bond pad) that functions as an electrical connection between the integrated circuit die140and the electrical interconnections of the semiconductor wafer102. The conductive pad116may be exposed or may be covered by a passivation layer. In implementations, the integrated circuit die140is attached to the adhesive material128on the second side of the semiconductor wafer102. In one implementation, the integrated circuit die140is attached to the backside of the semiconductor wafer102using benzocyclobutene (BCB) as the adhesive material128. Additionally, the integrated circuit die140may be attached and properly aligned using alignment marks106formed in the semiconductor wafer102.

In one embodiment and as shown inFIG. 1A, an integrated circuit die140is attached to the second side (e.g., backside) of the semiconductor wafer102and the adhesive material128. In this embodiment, the integrated circuit die140includes a conductive pad116that functions as an electrical interconnection between the integrated circuit die140and the semiconductor wafer102. Additionally, a cap wafer104may be attached to the semiconductor wafer102and the adhesive material128, where the cap wafer104includes a pre-formed cavity138configured to house the integrated circuit die140. The cap wafer104may include a wafer (e.g., an unprocessed passive silicon wafer) that is configured to provide protection to the integrated circuit die140. The cap wafer104functions to structurally and environmentally protect the integrated circuit die102. The cap wafer104may be thinned as necessary to reduce weight and/or bulk of the semiconductor device100. In some implementations, the cap wafer104may be background so that the integrated circuit die140is at least partially exposed. In these implementations, the cavity138may be at least partially filled with a mold compound or an encapsulation material to further protect the integrated circuit die140.

In another embodiment and as shown inFIG. 1B, a second side (e.g., backside) of the semiconductor wafer102is patterned and wet-etched to form a cavity138configured to house the integrated circuit die140. The cavity138is configured to house a substantially planar integrated circuit die140. The second surface of the semiconductor wafer102to which the integrated circuit die140is attached and the adhesive material128must also be substantially planar to form a solid attachment. In some implementations, the cavity138may subsequently be filled with a mold or encapsulation material to further protect the integrated circuit die102.

The semiconductor device100also includes a via130(e.g., a through-substrate via (TSV)) that extends through the semiconductor wafer102and the adhesive material128to at least one conductive layer116of the integrated circuit die140. As illustrated inFIGS. 1A and 1B, the via130includes a conductive material132that furnishes an electrical interconnection between a first conductive layer116of semiconductor wafer102and a second conductive layer116of the integrated circuit die140. In one or more implementations, the conductive material132may include a metal material (e.g., copper, aluminum, etc.). For instance, the via130may provide an electrical interconnection between a first integrated circuit formed in the semiconductor wafer102and a second integrated circuit formed in the integrated circuit die140.

The via130also includes an insulating liner134to electrically isolate the conductive material132disposed in the via130from the semiconductor wafer102. As illustrated inFIGS. 1A and 1B, the insulating liner134is deposited in the via130such that the insulating liner134extends through the via130at least substantially the thickness of the semiconductor wafer104(e.g., the first surface to the second surface), as well as at least substantially the thickness of the adhesive material128to the conductive pad116of the integrated circuit die140. The insulating liner134may be configured in a variety of ways. For example, the insulating liner134may be an insulating material (e.g., an oxide material, a nitride material, etc.). The insulating liner134is formed by depositing the insulating material in the via130and then etching the insulating material to form the insulating liner134along the sides of the via130. In one or more implementations, the insulating material may be deposited via plasma-enhanced chemical vapor deposition (PECVD) techniques and then anisotropically etching the insulating material down to the contact pad116of the integrated circuit die140to form the insulating liner134. In one or more implementations, the insulating material may include a silicon dioxide (SiO2) material or the like.

While a wafer and an attached integrated circuit die (e.g., semiconductor wafer102, integrated circuit die140) are shown inFIGS. 1A and 1B, it is contemplated that the semiconductor device100may employ additional wafers and/or die stacked and bonded together. For example, a third die may be positioned over the first or second surface of the semiconductor wafer102and one or more vias formed therein. It is contemplated that many through-silicon via configurations may be utilized depending on the characteristics of semiconductor device100(e.g., design requirements, structural requirements, etc.).

In accordance with the present disclosure, a semiconductor device100includes a semiconductor wafer102with an integrated circuit die140bonded together via an adhesive material128. In some embodiments, the adhesive material128may be selectively patterned before the integrated circuit die140is positioned over and attached to the second surface (e.g., the backside) of the semiconductor wafer102and in contact with the adhesive material128. If the adhesive material128is patterned, the selective patterning may allow the adhesive material128to reflow laterally during the bonding procedure. Once the bonding procedure is complete (e.g., after curing of the adhesive material128, etc.), a via130is formed that extends through the semiconductor wafer102and the adhesive material128to a conductive layer116in the integrated circuit die140. The conductive layer116of the integrated circuit die140is configured to provide an electrical interconnection with one or more integrated circuits formed in the semiconductor wafer102. The via130includes a conductive material132that further provides an interconnection between the conductive layer116of the semiconductor wafer102to a conductive layer116of the integrated circuit die140so that the integrated circuit of the semiconductor wafer102is electrically connected to an integrated circuit formed in the integrated circuit die140. Once the fabrication is complete, suitable wafer-level packaging processes may be employed to segment and package the individual semiconductor semiconductor device100. In one or more implementations, the segmented semiconductor devices may comprise wafer chip-scale package devices, which may further be attached to another device (e.g., a printed circuit board) to create an electronic device.

Example Fabrication Processes

FIG. 2illustrates an example process200that employs wafer-level packaging techniques to fabricate three-dimensional semiconductor devices, such as the semiconductor device100shown inFIGS. 1A and 1B.FIGS. 3A through 3Gillustrate sections of example wafers that may be utilized to fabricate semiconductor devices300(such as semiconductor device100) shown inFIGS. 1A and 1B. A semiconductor wafer302, as shown inFIG. 3A, includes a first surface (e.g., the top or frontside) and a second surface (e.g., the bottom or backside). The semiconductor wafer302includes one or more integrated circuits (not shown) formed proximate to the first surface. The integrated circuits are connected to one or more contact pads316(e.g., a metal pad, etc.) that are configured to provide electrical contacts through which the integrated circuits are interconnected to other components (e.g., other integrated circuits, printed circuit boards, etc.) associated with semiconductor device300. The semiconductor wafer302may further include one or more interconnect layer(s)332,316formed of various conducting and insulating materials, such as silicon dioxide (SiO2), aluminum, copper, tungsten, and so forth between the contact pads316and the first surface of the semiconductor wafer102. The passivation layer336covers the interconnect layer(s)332,316and other components of the semiconductor wafer302to provide protection and insulation to the integrated circuits. The passivation layer336can be either planarized or non-planar and may include patterned holes to provide access to the contact pads316.

As illustrated inFIG. 2, a semiconductor wafer is bonded to a carrier wafer (Block202). For example, as shown inFIG. 3B, the semiconductor wafer302is bonded to a carrier wafer342via a temporary adhesive material344. In one or more implementations, the temporary adhesive material344may be a soluble bonding agent or wax. The carrier wafer342is configured to provide structural support to the semiconductor wafer302during one or more backgrinding processes. Once the carrier wafer342is bonded to the semiconductor wafer302, a backgrinding process is applied to the second surface (e.g., backside) of the semiconductor wafer302to allow for stacking and high density packaging of the semiconductor device (Block204).

As illustrated inFIG. 3, the semiconductor device300includes a semiconductor wafer302having a first surface and a second surface. The first surface includes one or more integrated circuits formed therein. The integrated circuits are connected to one or more contact pads316to provide electrical interconnection between the integrated circuits and other components associated with the semiconductor device300(e.g., other integrated circuits, printed circuit boards, etc.) A passivation layer (e.g., SiO2) at least partially covers the first surface to provide protection to the integrated circuits from later fabrication steps.

In some embodiments, the second side (e.g., backside) of the semiconductor wafer is patterned and etched (Block206). In these embodiments and as shown inFIG. 3G, the second side of the semiconductor wafer302is patterned (e.g., using photolithography) and wet-etched to form a cavity338that is suitable to house the integrated circuit die340. Wet-etching may include exposing the semiconductor wafer302in an etchant (e.g., potassium hydroxide (KOH), buffered hydrofluoric acid, etc.) to remove an exposed portion of the backside of the semiconductor wafer302. In some embodiments, the first side of the semiconductor wafer302may be cushioned and protected with a gas while the second side of the semiconductor wafer302is etched to form the cavity338.

As illustrated inFIG. 2, a second surface of a semiconductor wafer is coated with an adhesive material (Block208). In implementations where the semiconductor wafer302is patterned and etched to form a cavity338, the second side of the semiconductor wafer302as well as the cavity338is coated with the adhesive material328. The adhesive material328may be configured as an adhesive dielectric (e.g., benzocyclobutene (BCB), etc.). Once the adhesive material328is applied to the semiconductor wafer302, the adhesive material328may be patterned to allow for lateral expansion of the patterned adhesive material328when the integrated circuit die340is pressed into contact with the patterned adhesive material328.

Next, the integrated circuit die is placed on the adhesive material and the semiconductor wafer (Block210). As illustrated inFIG. 3C, placing the integrated circuit die340includes placing the integrated circuit die340on the adhesive material328on the second side of the semiconductor wafer302. If the semiconductor wafer302has been etched, the integrated circuit die340is placed in the cavity338formed by the etching process. It is contemplated that once the integrated circuit die340is attached to the second side of the semiconductor wafer302, a curing process may be utilized to further harden the adhesive material328.

In embodiments where the semiconductor wafer is not etched to form a cavity, a cap wafer is placed on the backside of the semiconductor wafer and over the integrated circuit die (Block212). As shown inFIG. 3D, placing a cap wafer304includes placing the cap wafer304having a pre-formed cavity338on the second side (the second side of the semiconductor wafer302is illustrated at the top ofFIG. 3D) of the semiconductor wafer302, where the previously attached integrated circuit die340is housed in the pre-formed cavity338. In implementations, the cap wafer304is attached to the adhesive material328, which may subsequently be cured. In some embodiments, placing the cap wafer304may include grinding the cap wafer304such that a portion of the integrated circuit chip340is exposed. In these specific embodiments, the cavity338between the cap wafer304and the integrated circuit die340may be filled with a mold material or an encapsulation material for further support and/or environmental protection.

It is contemplated that various aligning procedures may be employed to align the integrated circuit die340, the semiconductor wafer302, the carrier wafer342, and/or the cap wafer304. In an implementation, alignment marking techniques may be utilized to align each component. For instance, the semiconductor wafer302may include one or more alignment marks306to properly align the semiconductor wafer302with the integrated circuit die340, the carrier wafer342, and/or the cap wafer304during placement and/or bonding. In implementations, visible light/infrared light alignment techniques may be utilized to align each component. In an implementation, a top visible light source (not shown) positioned above the semiconductor wafer302provides visible light to properly align the semiconductor wafer302. Then, a top infrared light detector (not shown) positioned above the semiconductor wafer302, in combination with a bottom infrared source positioned below the semiconductor wafer302, allow for positioning of the integrated circuit die340, the carrier wafer342, and/or the cap wafer304. The infrared optics may be configured to provide an infrared light such that an operator, with proper magnification and visualization equipment, can see through the wafers and/or components to allow for proper alignment with the already properly aligned semiconductor wafer302.

The carrier wafer is then removed from the semiconductor wafer (Block214) by heating the temporary adhesive material (e.g., temporary adhesive material344) sufficiently to allow for removal of the carrier wafer (e.g., carrier wafer342) (seeFIG. 3E). A via is then formed through the semiconductor wafer and the adhesive material (Block216) down (the second side of the semiconductor wafer is illustrated at the bottom inFIG. 3E) to a conductive layer disposed as a portion of the integrated circuit die. The via330is formed by etching an aperture through the semiconductor wafer302and the adhesive material328. As illustrated inFIGS. 3F and 3G, a via330is formed through the semiconductor wafer302and the adhesive material328utilizing one or more photolithography and etching techniques. For instance, once the semiconductor wafer302is patterned, an etch to remove the various insulation layers (e.g., passivation layers), silicon layers, adhesive material, and so forth, is performed. The etching step is configured to form the via330and to stop on the conductive pad (e.g., conductive pad316of the integrated circuit die340). It is contemplated that various etching techniques (e.g., dry etch, wet etch, etc.) may be utilized depending on the requirements of the semiconductor device300, the via330, and so forth.

An insulating liner is formed in the via (Block218) to electrically isolate the semiconductor wafer from the via. In an implementation, an insulating material is first deposited via plasma enhanced chemical vapor deposition (PECVD) techniques and then anisotropically etched down to the conductive layer316to form the insulating liner334as shown inFIGS. 3F and 3G. Moreover, a diffusion barrier metal (e.g., Ti, etc.) and a seed metal may be deposited over the first surface of the semiconductor wafer302as a part of the electrical interconnection layers (e.g., redistribution layer124, conductive material332, conductive pad316, etc.). The barrier metal and the seed metal may be patterned (e.g., via photolithography) to further provide electrical interconnections between the semiconductor wafer302and the integrated circuit die340at later fabrication stages.

A conductive material is then deposited in the via (Block220) to provide an electrical interconnection between the semiconductor wafer and the integrated circuit die. For instance, as illustrated inFIGS. 3F and 3G, a conductive material332(e.g., copper, or the like) is deposited in the via330to form an electrical interconnection between the conductive layer316of the semiconductor wafer302and the conductive layer316of the integrated circuit die340. In one or more implementations, the conductive material332is selectively plated-up via electroplating to form the electrical interconnections. Moreover, in one or more implementations, the conductive material332deposited in the via330may also serve as the conductive material utilized for a redistribution structure, such as the redistribution structure324shown inFIGS. 3F and 3G. Thus, the deposition of the conductive material332in the via330may also result in the formation of a redistribution structure. It is contemplated that further semiconductor fabrication techniques may be utilized to finalize the semiconductor device300fabrication process. For instance, further stripping of photoresist, etching of the seed and barrier metals to electrically isolate plated-up lines, and depositing of passivation layers may be incorporated. For example, seed and barrier metal in unplated areas may be removed to form the electrical interconnections.

Once the wafer fabrication process is complete, suitable wafer-level packaging processes may be employed to segment and package the individual semiconductor devices (Block222). In one or more implementations, the segmented semiconductor devices may comprise wafer chip-scale package devices.

CONCLUSION