Smart lock-in circuit for phase-locked loops

The smart lock-in circuits basically include a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all smart lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule.

FIELD OF THE INVENTION

The present invention relates to the field of fast-locking phase-locked loops and more particularly to smart lock-in circuit for phase-locked loops.

BACKGROUND ART

Phase-looked loop is a vitally important device. Phase-looked loop is analog and mixed signal building block used extensively in communication, networks, digital systems, consumer electronics, computers, and any other fields that require frequency synthesizing, clock recovery, and synchronization.

Prior ArtFIG. 1illustrates a block diagram of a basic architecture of two types of conventional phase-locked loops, which are a conventional phase-locked loop110and a conventional fast-locking phase-locked loop120. The conventional phase-locked loop110typically consists of a phase-frequency detector (or phase detector), a charge-pump, a low-pass filter, and a voltage-controlled oscillator in a loop. Phase-locked loops without any frequency divider in a loop are considered here for simplicity. The phase-frequency detector (or phase detector) is a block that has an output voltage with an average value proportional to the phase difference between the input signal and the output signal of the voltage-controlled oscillator. The charge-pump either injects the charge into the low-pass filter or subtracts the charge from the low-pass filter, depending on the outputs of the phase-frequency detector (or phase detector). Therefore, change in the low-pass filter's output voltage drives the voltage-controlled oscillator. The negative feedback of the loop results in the output of the voltage-controlled oscillator being synchronized with the input signal. As a result, the phase-locked loop is in lock.

In the conventional phase-locked loop110of Prior ArtFIG. 1, lock-in time is defined as the time that is required to attain lock from an initial loop condition. Assuming that the phase-locked loop bandwidth is fixed, the lock-in time is proportional to the difference between the input signal frequency and the initial voltage-controlled oscillator's frequency as follows:

(ωin-ωosc)2ω03
where ωinis the input signal frequency, ωascis the initial voltage-controlled oscillator's frequency, and ω0is the loop bandwidth. The loop bandwidth must be wide enough to obtain a fast lock-in time. But most systems require a fast lock-in time without regard to the input signal frequency, bandwidth, and output phase jitter due to external noise. However, the conventional phase-locked loop110shown in Prior ArtFIG. 1has suffered from slow locking and harmonic locking. Thus, time and power are unnecessarily consumed until the phase-locked loops become locked. In addition, it has taken a vast amount of time to simulate and verify the conventional phase-locked loop110before fabrication since the simulation time of phase-locked loop circuits is absolutely proportional to time that is required the phase-locked loops to be locked. This long simulation adds additional cost and serious bottleneck to better design time to market. For these reasons, the conventional phase-locked locked loop110of Prior ArtFIG. 1is very inefficient to implement in an integrated circuit (IC) or system-on-chip (SOC).

To overcome the drawbacks of the conventional phase-locked loop110of Prior ArtFIG. 1, a conventional fast-locking phase-locked loop120of Prior ArtFIG. 1is illustrated. The conventional fast-locking phase-locked loop120consists of a digital phase-frequency detector, a proportional-integral controller122, a 10-bit digital-to-analog converter124, and a voltage-controlled oscillator. Unfortunately, the conventional fast-locking phase-locked loop is costly, complicated, and inefficient to implement in system-on-chip (SOC) or integrated circuit (IC) because additional proportional-integral controller122and the 10-bit digital-to-analog converter124take much more chip area, consume much more power, and make the stability analysis very difficult. The complexity increases the number of blocks that need to be designed and verified. The conventional fast-locking phase-locked loop120might improve the lock-in time, but definitely results in bad time-to-market, higher cost, larger chip area, much more power consumption, and longer design time.

Thus, what is desperately needed is a highly cost-effective fast-locking phase-locked loop that can be highly efficiently implemented with a drastic improvement in a very fast lock-in time, lock-in time controllability, performance, cost, chip area, power consumption, stand-by time, and fast design time for much better time-to-market. At the same time, serious harmonic locking problem has to be resolved. The present invention satisfies these needs by providing smart lock-in circuits.

SUMMARY OF THE INVENTION

The present invention provides five types of the smart lock-in circuits for phase-locked loops. The smart lock-in circuits simultaneously enable any phase-locked loop to be locked according to schedule. The basic architecture of the smart lock-in circuits consists of a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor senses a voltage at its input. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the output voltage reaches the midpoint voltage. The time to reach the midpoint voltage at the filter is simply equal to the charge stored at the filter divided by the current, which can be scaled.

Consequently, all smart lock-in circuits provide a significant reduction in the difference between the initial loop condition and the locked condition in order to overcome serious drawbacks simultaneously. The lock-in time controllability enables all of the phase-locked loops on the chip to be locked according to schedule. In addition, the present invention has five different embodiments which achieve a drastic improvement in a very fast lock-in time, lock-in time controllability, performance, cost, chip area, power consumption, stand-by time, and design time.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the present invention, five types of the smart lock-in circuits, numerous specific details are set forth in order to provide a through understanding of the present invention. However, it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, CMOS digital gates, components, and metal-oxide-semiconductor field-effect transistor (MOSFET) device physics have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

FIG. 2illustrates a block diagram of two types of the smart lock-in circuits for phase-locked loops in accordance with the present invention. One type of the smart lock-in circuit is applied for phase-locked loops including a filter216connected between VCand ground, as seen in the phase-locked loop210shown inFIG. 2. The other type of the smart lock-in circuit called “p-type smart lock-in circuit” is applied for phase-locked loops including a filter226connected between VDDand VC, as seen in the phase-locked loop220shown inFIG. 2. To reduce the difference between the initial loop condition and the locked condition, the outputs of the smart lock-in circuit214and the p-type smart lock-in circuit224are coupled to the outputs of the filter216and the filter226, respectively, as shown inFIG. 2. The phase-locked loop210excluding the smart lock-in circuit214represents all types of phase-locked loops including a filter216connected between VCand ground without regard to the types of phase-locked loops because the applications of the smart lock-in circuit214is independent of architectures and types of phase-locked loops. The phase-locked loop220excluding the p-type smart lock-in circuit224represents all types of phase-locked loops including a filter226connected between VDDand VCwithout regard to the types of phase-locked loops because the applications of the p-type smart lock-in circuit224is independent of architectures and types of phase-locked loops. The filters216and226are low-pass filters. If these filters are multiple-order low-pass filters, then they will be approximated to the first-order filter with neglecting resistor in the filter for simplicity.

FIG. 3illustrates a basic smart lock-in circuit according to the present invention. This basic smart lock-in circuit300does not have power-down mode in order to show the fundamental concept of the invention clearly. The basic smart lock-in circuit300is a feedback circuit that consists of lower-voltage sensing inverters302and312(i.e., an even number of inverters), higher-voltage sensing inverters304and324(i.e., an even number of inverters), two stacked PMOS transistors306and308, two stacked NMOS transistors326and328, and a feedback line310. The gate terminal of a PMOS transistor308is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor326is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., VDD, “1”, high, etc.).

It is assumed that the output of the basic smart lock-in circuit300is at ground. Since the first lower-voltage sensing inverter302initially senses a voltage less than the lower midpoint voltage of the first lower-voltage sensing inverter302, the output voltage of the second lower-voltage sensing inverter312is low enough to turn on the PMOS transistor306. At the same time, the output voltage of the second higher-voltage sensing inverter324is low enough to turn off the NMOS transistor328. Thus, the PMOS transistor306provides a current (i.e., IP) to the output until the output voltage (i.e., VC) goes up to the lower midpoint voltage of the first lower-voltage sensing inverter302. The time to reach the lower midpoint voltage at the filter connected between VCand ground is as follows:

Δ⁢⁢t=VM⁢CPIP
where VMis the lower midpoint voltage determined by the device aspect ratios of the first lower-voltage sensing inverter302and CPis the value of the capacitor in the filter. Thus, the lock-in time of the phase-locked loops including the filter connected between VCand ground is approximately given by

(ωin-ωM)2ω03+VM⁢CPIP
where ωinis the input signal frequency, ωMis the voltage-controlled oscillator's frequency for VC=VM, and ω0is the loop bandwidth. This lock-in time is varied by the current IPdepending on the size of the PMOS transistor306.

It is assumed that the output of the basic smart lock-in circuit300is at power supply. Since the first higher-voltage sensing inverter304initially senses a voltage greater than the higher midpoint voltage of the first higher-voltage sensing inverter304, the output voltage of the second higher-voltage sensing inverter324is high enough to turn on the NMOS transistor328. At the same time, the output voltage of the second lower-voltage sensing inverter312is high enough to turn off the PMOS transistor306. Thus, the NMOS transistor328provides a current (i.e., IN) to the output until the output voltage (i.e., VC) goes down to the higher midpoint voltage of the first higher-voltage sensing inverter304. The time to reach the higher midpoint voltage at the filter connected between VCand power supply is as follows:

Δ⁢⁢t=(VDD-VM⁡(H))⁢⁢CPIN
where VM(H)is the higher midpoint voltage determined by the device aspect ratios of the first higher-voltage sensing inverter304and CPis the value of the capacitor in the filter. Thus, the lock-in time of the phase-locked loops including the filter connected between VCand power supply is approximately given by

(ωin-ωM⁡(H))2ω03+(VDD-VM⁡(H))⁢CPIN
where ωinis the input signal frequency, ωM(H)is the voltage-controlled oscillator's frequency for VC=VM(H), and ω0is the loop bandwidth. This lock-in time is varied by the current INdepending on the size of the NMOS transistor328.

The midpoint voltage is a voltage where the input voltage and the output voltage of the inverter are equal in the voltage transfer characteristic. At the midpoint voltage, the transistors of the inverter operate in the saturation mode. This midpoint voltage of inverter is expressed as

In design of the basic smart lock-in circuit ofFIG. 3, it is also desirable to use a value for the lower midpoint voltage, VM, less than VC′ and a value for the higher midpoint voltage, VM(H), greater than VC′. VC′ is the voltage that makes the frequency of the voltage-controlled oscillator equal to the input signal's frequency.

FIG. 4illustrates a smart lock-in circuit400according to the present invention. A power-down input voltage, VPD, is defined as the input voltage for power-down mode. The power-down enable system is in power-down mode when VPDis VDDand it is in normal mode when VPDis zero. The smart lock-in circuit400is a feedback circuit that consists of lower-voltage sensing inverters402and412(i.e., an even number of inverters), two stacked PMOS transistors406and408, two stacked NMOS transistors426and428, a feedback line410, and a power-down NMOS transistor442. In addition, the gate terminal of a PMOS transistor408is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor426is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., VDD, “1”, high, etc.). Furthermore, the gate terminal of a NMOS transistor428is shorted and thus no current flows into the drains of the NMOS transistors426and428.

The circuit mode changes from power-down mode to normal mode inFIG. 4. Since the first lower-voltage sensing inverter402initially senses a voltage less than the lower midpoint voltage of the first lower-voltage sensing inverter402, the output voltage of the second lower-voltage sensing inverter412is low enough to turn on the PMOS transistor406. The PMOS transistor406generates a current (i.e., IP) to the output until the output voltage (i.e., VC) goes up to the lower midpoint voltage of the first lower-voltage sensing inverter402. Furthermore, the lock-in time of the phase-locked loops including the filter connected between VCand ground is approximately given by

(ωin-ωM)2ω03+VM⁢CPIP
where ωinis the input signal frequency, ωMis the voltage-controlled oscillator's frequency for VC=VM, and ω0is the loop bandwidth. Also, VMis the lower midpoint voltage determined by the device aspect ratios of the first lower-voltage sensing inverter402and CPis the value of the capacitor in the filter. The lock-in time is varied by the current IPdepending on the size of the PMOS transistor406.

In design of the smart lock-in circuit ofFIG. 4, it is also desirable to use a value for the lower midpoint voltage, VM, less than VC′. VC′ is the voltage that makes the frequency of the voltage-controlled oscillator equal to the input signal's frequency. The smart lock-in circuit400is used for all types of phase-locked loops including the filter connected between VCand ground.

Since the power-down NMOS transistor442is on during power-down mode, it provides an output pull-down path to ground. Thus, VCof the smart lock-in circuit400is zero so that no current flows into the circuits during power-down mode.

FIG. 5illustrates a dual smart lock-in circuit500in accordance with the present invention. The dual smart lock-in circuit500is a modification of the circuit described inFIG. 4. The gate terminal of a PMOS transistor508is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor526is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., VDD, “1”, high, etc.). Furthermore, compared toFIG. 4, the first difference to note is that the higher-voltage sensing inverters504and524(i.e., an even number of inverters) are added intoFIG. 5in order to provide the higher-voltage sensing function. The second difference to note is that the output of the second higher-voltage sensing inverter524is connected to the gate terminal of a NMOS transistor528. Therefore, the dual smart lock-in circuit500is able to sense the lower-voltage as well as the higher-voltage while the smart lock-in circuit400is able to sense only the lower-voltage.

No current flows into the drains of the NMOS transistors526and528assuming VC<VM(H)where VM(H)is the higher midpoint voltage decided by the device aspect ratios of the first higher-voltage sensing inverter504. If VCis greater than VM(H), the gate voltage of the NMOS transistor528is VDD. As a result, a current flows into the drains of the NMOS transistors526and528until VCgoes down to VM(H).

In design of the dual smart lock-in circuit ofFIG. 5, it is also desirable to use a value for the midpoint voltage, VM, less than VCand a value for the higher midpoint voltage, VM(H), greater than V′C. V′Cis the voltage that makes the frequency of the voltage-controlled oscillator equal to the input signal's frequency. VMis the midpoint voltage decided by the device aspect ratios of the first lower-voltage sensing inverter502. The dual smart lock-in circuit500is used for all types of phase-locked loops including the filter connected between VCand ground. Zero dc volt at VCensures that no current flows into the circuits during power-down mode.

FIG. 6illustrates a p-type smart lock-in circuit600according to the present invention. The power-down input voltage, VPD, is defined as the input voltage for the p-type power-down mode as well as for the power-down mode. The p-type power-down enable system is in power-down mode when VPDis VDDand it is in normal mode when VPDis zero. The p-type smart lock-in circuit600is a feedback circuit that consists of a higher-voltage sensing inverters604and624(i.e., an even number of inverters), two stacked PMOS transistors606and608, two stacked NMOS transistors626and628, a feedback line610, a power-down inverter614, and a power-down PMOS transistor642. In addition, the gate terminal of a PMOS transistor608is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor626is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., VDD, “1”, high, etc.). Furthermore, since the PMOS transistor606is turned off, no current flows out of the drains of the PMOS transistors606and608. Also, VM(H)is the higher midpoint voltage decided by the device aspect ratios of the first higher-voltage sensing inverter604.

The circuit mode changes from p-type power-down mode to normal mode inFIG. 6. Since the first higher-voltage sensing inverter604initially senses a voltage greater than VM(H), the output voltage of the second higher-voltage sensing inverter624is high enough to turn on the NMOS transistor628. The NMOS transistor628generates a current (i.e., IN) to the output until the output voltage, VC, goes down to VM(H). Thus, the lock-in time of the phase-locked loops including the filter connected between VCand power supply is approximately given by

(ωin-ωM⁡(H))2ω03+(VDD-VM⁡(H))⁢⁢CPIN
where ωinis the input signal frequency, ωM(H)is the voltage-controlled oscillator's frequency for VC=VM(H), and ω0is the loop bandwidth. Also, CPis the value of the capacitor in the filter and VM(H)is the higher midpoint voltage determined by the device aspect ratios of the first higher-voltage sensing inverter604. The lock-in time is varied by the current INdepending on the size of the NMOS transistor628.

In design of the p-type smart lock-in circuit ofFIG. 6, it is also desirable to use a value for the higher midpoint voltage, VM(H), greater than VC′. VC′ is the voltage that makes the frequency of the voltage-controlled oscillator equal to the input signal's frequency. The p-type smart lock-in circuit600is used for all types of phase-locked loops including the filter connected between VCand power supply.

The output voltage of the power-down inverter614, VPDB, is zero during power-down mode. As a result, the power-down PMOS transistor642is turned on and thus provides an output pull-up path to VDD. Therefore, VCof the p-type smart lock-in circuit600is VDDso that no current flows into the circuits during power-down mode. On the contrary, it was stated earlier that VCmust be zero when power-down mode occurs inFIG. 4andFIG. 5.

FIG. 7illustrates a p-type dual smart lock-in circuit700in accordance with the present invention. The p-type dual smart lock-in circuit700is a modification of the circuit described inFIG. 6. The gate terminal of a PMOS transistor708is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor726is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., VDD, “1”, high, etc.). Compared toFIG. 6, the first difference to note here is that the lower-voltage sensing inverters702and712(i.e., an even number of inverters) are added intoFIG. 7in order to sense the lower-voltage. The second difference to note here is that the output of the second lower-voltage sensing inverter712is connected to the gate terminal of the PMOS transistor706. The p-type dual smart lock-in circuit700is able to sense the lower-voltage as well as the higher voltage while the p-type smart lock-in circuit600is able to sense only the higher voltage.

No current flows out of the drains of the PMOS transistors706and708if VCis greater than VM. VMis the lower midpoint voltage decided by the device aspect ratios of the first lower-voltage sensing inverter702. If VCis less than VM, the PMOS transistor706is turned on until VCgoes up to VM.

In design of the p-type dual smart lock-in circuit ofFIG. 7, it is also desirable to use a value for the higher midpoint voltage, VM(H), greater than V′Cand a value for the lower midpoint voltage, VM, less than V′C. V′Cis the voltage that makes the frequency of the voltage-controlled oscillator equal to the input signal's frequency. The p-type dual smart lock-in circuit700is used for all types of phase-locked loops including the filter connected between VCand power supply. VC=VDDin the p-type dual smart lock-in circuit700ensures that no current flows into the circuits during power-down mode.

In summary, the five smart lock-in circuits of the present invention simply control how fast the phase-locked loops become locked from an initial condition. Also, they provide a solution for harmonic locking problem. Furthermore, three smart lock-in circuits300,500, and700are highly effective for LC oscillator which has a very narrow tuning range. The balance between PMOS output resistance and NMOS output resistance is important to obtain high output resistance. Furthermore, the CMOS process variations usually must be considered so that the proper value of the midpoint voltage is chosen for all the smart lock-in circuits300,400,500,600, and700. Each bulk of two stacked PMOS transistors can be connected to its own N-well to obtain better immunity from substrate noise in all smart lock-in circuits300,400,500,600, and700.

The smart lock-in circuit214shown inFIG. 2represents the basic smart lock-in circuit300, the smart lock-in circuit400, and the dual smart lock-in circuit500, as shown inFIG. 3,FIG. 4, andFIG. 5, respectively. Also, the p-type smart lock-in circuit224shown inFIG. 2represents the basic smart lock-in circuit300, the p-type smart lock-in circuit600and the p-type dual smart lock-in circuit700, as shown inFIG. 3,FIG. 6, andFIG. 7, respectively. It is noted that SPICE is used for the simulation of phase-locked loops. The conventional phase-locked loop110and the phase-locked loop210including the basic smart lock-in circuit300of the invention are simulated using the same components. As a result, the total simulation time of the conventional phase-locked loop110is 20 hours and that of the phase-locked loop210is 1.9 hours. This improvement can be accomplished by simply inserting a proper one of the five smart lock-in circuits into any conventional phase-locked loop, and the simulation time can be reduced by a factor of 10. So far, it should be noted that the same time step has been used for the SPICE simulation in order to accurately measure and compare the simulation time of all circuits.

All the smart lock-in circuits of the present invention are very efficient to implement in system-on-chip (SOC) or integrated circuit (IC). The present invention provides five different embodiments which achieve a drastic improvement in a very fast lock-in time, lock-in time controllability, performance, time-to-market, power consumption, stand-by time, cost, chip area, and design time. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as being limited by such embodiments, but rather construed according to the claims below.