Input/output routing on an electronic device

An electronic device includes a material having a first dielectric constant (K) value, and a material having a second dielectric constant (K) value. The first dielectric constant (K) value is lower than the second dielectric constant (K) value. The electronic device also includes input/output connection conductors for transmitting signals to and from a die. The input/output connection conductors are routed through the material of the interposer having the first dielectric constant. The electronic device also includes power connection conductors for delivering power to the die, and ground connection conductors. The power and ground connection conductors are routed through the material having the second dielectric constant.

BACKGROUND OF THE INVENTION

The semiconductor industry has seen tremendous advances in technology in recent years that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds (or even thousands) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled semiconductor device packages. As integrated circuit devices, microprocessors and other related components are designed with increased capabilities and increased speed, more input/output or transmission lines are typically needed. In addition, the decreased size of the microprocessor typically results in more closely spaced input/output lines. The emphasis on increased speed and performance requires increased speed for switching on the input/output lines. In addition, little if any cross-talk between the input/output lines is desired. Also, efficient power delivery to a semiconductor is desired.

The description set out herein illustrates the various embodiments of the invention, and such description is not intended to be construed as limiting in any manner.

DETAILED DESCRIPTION

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention can be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments can be utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of present inventions. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments of the invention is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

FIG. 1is a top view of a printed circuit board100having a component136formed according to an example embodiment. The printed circuit board100is a multi-layer plastic board that includes patterns of printed circuits on one or more layers of insulated material. The patterns of conductors correspond to wiring of an electronic circuit formed on one or more of the layers of the printed circuit board100. The printed circuit board100also includes electrical traces110. The electrical traces110can be found on an exterior surface120of the printed circuit board100and also can be found on the various layers within the printed circuit board100. Printed circuit boards also include through holes (not shown inFIG. 1) which are used to interconnect traces on various layers of the printed circuit board100. The printed circuit board100can also include planes of metallized materials such as ground planes, power planes, or voltage reference planes (not shown inFIG. 1).

The printed circuit board100is also populated with various components130,132,134, and138. The components130,132,134,136, and138can either be discrete components or semiconductor chips which include thousands or millions of transistors. The components130,132,134,136,138can use any number of technologies to connect to the exterior surface120of the printed circuit board100. For example, pins may be inserted into plated through holes or pins may be extended through the printed circuit board100. An alternative technology is surface mount technology, where an electrical component, such as component136, mounts to an array of pads on the exterior surface120of the printed circuit board100. For example, component136could be a ball grid array package or device that has an array of balls or bumps that interact or are connected to a corresponding array of pads on the exterior surface120of the printed circuit board100. The printed circuit board100can also include connectors140,142for making external connections to other electrical or electronic devices. The component136includes a first set of conductors routed through a material having a first dielectric constant (K) value, and a second set of conductors routed through a material having a second dielectric constant (K) value. The first dielectric constant (K) value is lower than the second dielectric constant (K) value. Example embodiments of component136are set forth below. It is contemplated that the printed circuit board100can include one or more components, such as component136.

As shown inFIG. 1, the printed circuit board100includes a first edge connector140and a second edge connector142. As shown inFIG. 1there are external traces, such as electrical trace110, on the external surface120of the printed circuit board100that connect to certain of the outputs associated with the first edge connector140. Other traces that connect with the edge connectors140,142may have traces internal to the printed circuit board100. The printed circuit board100can be a motherboard, a daughterboard, a sound card, a video card, a modem, or any other type of board or card for use in any type of product, including a computing product or system.

FIG. 2illustrates a schematic diagram of a die210that is part of a package200, according to an example embodiment. The package200is similar to the component136shown inFIG. 1. The die200includes a first set of conductors220passing through a material222having a first dielectric constant. The package also includes a second set of conductors230passing through a material232having a second dielectric constant. As shown, the first set of conductors220include signal lines or input/output lines, and the second set of conductors230includes power conductors and connections to ground. The input/output lines or first set of conductors220pass through a lower dielectric constant material than the power and ground conductors or second set of conductors230. The dielectric constant is the relative permittivity of a given material compared to the permittivity of vacuum or air. The dielectric constant reflects the relative ability of a given material to store electrostatic energy (per given volume) to that of air.

The material232having a higher value for the dielectric constant is labeled as high K material, and the material222having a lower value for the dielectric constant is labeled as low K material. In one example embodiment the low K material has a dielectric constant in the range of 2–4, and the high K material has a dielectric constant in the range of 2000–7000. In another embodiment of the invention the high K material has a dielectric constant in the range of 300–5000. In an example embodiment, the ratio of the dielectric constant of the high K material232to the dielectric constant of the low K material222is in the range of 150 to 3500. In another example embodiment, the ratio of the dielectric constant of the high K material232to the dielectric constant of the low K material222is in the range of 750 to 2000. In still another example embodiment, the ratio of the dielectric constant of the high K material232to the dielectric constant of the low K material222is in the range of 950 to 1050. In general, the set of conductors230, namely power and ground conductors, passing through the high K material232will short high frequency between the conductors within the set of conductors230. This is desirable since this will also short voltage variations that may occur between power and ground. The set of conductors220passing through the low K material222prevents high frequencies from being transmitted between signal lines, and prevents high frequencies from being transmitted from a signal line to a conductor carrying power or connected to ground.

FIG. 3illustrates a cross-sectional side view of a package300that includes a die310, a ceramic interposer320and a package substrate330, according to an example embodiment. The interposer320is a device including a number of conductive paths that is positioned between the package substrate330and the die310. The interposer320includes a first major surface321and a second major surface322, and has connection pads on each of the first major surface321and the second major surface322. The connections passing through the interposer320include conductors340for power and conductors341to connect to ground as well as conductors350for carrying signals to and from the die310. The conductors340for power and conductors341to connect to ground, are generally paired so that one of the conductors carries current in a positive direction and the other carries current in a negative direction.

FIG. 4illustrates a cross-sectional top view of package300along line4—4ofFIG. 3. The resultant view is of the interposer320of the package300. Now referring to bothFIGS. 3 and 4, the interposer320of the package300also includes a material having a first dielectric constant (K) value, and a material having a second dielectric constant (K) value. The first dielectric constant (K) value is lower than the second dielectric constant (K) value. A layer of high K material324is positioned on at least portions of the first major surface321of the interposer320. A set424of conductors340for carrying power and conductors341connected to ground are routed through the high K material324. The high K material shorts high frequencies between the conductors340for carrying power and the conductors341connected to ground. This is desirable since this will also prevent or substantially reduce voltage variations or parasitic signals that may occur between the conductors341carrying power and conductors341connected to ground in the set424of conductors. The package300also includes another set450of conductors that carry signals. In some embodiments, the signal lines are also arranged in pairs and form transmission lines. As shown inFIG. 4, the set450of conductors includes a first subset451of conductors and a second subset452of conductors that are routed through low K material421and low K material422, respectively. At least a portion on the first major surface321of the interposer320includes the low K material421and low K material422. At least some of the signal-carrying conductors453,454,455of the subset452of conductors are routed over the low K material422.

FIG. 5illustrates a cut-away side view of the interposer320along line5—5inFIG. 4, according to an example embodiment.FIG. 5shows two signal-carrying or I/O (input/output) conductors510,512associated with the subset451of conductors. The I/O conductors510,512are surrounded by a low K material520,522, respectively. The interposer320has a main body portion521made of a ceramic material. The main body portion521includes the first major surface321and the second major surface322. The high K material324is placed on the first major surface321. A bottom metal530is initially placed on the first major surface321. Portions of the bottom metal530are removed to leave plates532. In one embodiment, the portions of the bottom metal530are removed using photolithography to place a pattern on photoresist. Either the unexposed or exposed portions of the photoresist are removed so that a pattern of plates is positioned over the layer of bottom metal530. The surface can then be etched to expose portions of the first major surface321. Next the high K material324is applied to the first major surface321of the interposer320. The high K material can be a dielectric or ceramic. In one embodiment, the high K material324includes perovskite (calcium titanium oxide) or another crystalline mineral. In other embodiments, the high K material may be barium titanate, zirconium titanate, tantalum pentoxide (Ta2O5), oxynitride film (SiONx film), barium titanate (BaTiO3) or barium strontium titanate (BST) or other materials exhibiting a high dielectric constant (K) or any high K material exhibiting a high dielectric constant (K). The high K material324, in another embodiment, can includes a thin-film or thick-film dielectric layer deposited over a conductive plate. In various embodiments, a high K material is sputter deposited, anodically grown, deposited by chemical solution deposition (CSD) or deposited by chemical vapor deposition (CVD).

A top metal540is then placed on the high K material324. Plates541are also formed in the top layer using photolithography techniques or similar techniques. A via551is then formed through plate541, the high K material324, and through the main body portion521of the interposer320. The via551is provided with a conductive surface to form a power connector or conductor550. Similarly, a via561is formed through the high K material324, through plate531, and through the main body portion521The via561is provided with a conductive surface to form a ground connection or conductor560. As formed, a major planar surface of the plate531of the ground conductor560is positioned near a major planar surface of the plate541of the power conductor550. Placing the major planar surface of the plate531near the major planar surface of the plate541enhances the capacitive coupling between the power conductor550and the ground conductor560to aid in filtering out of high frequency perturbations or voltage variations between the ground and power conductors.

FIG. 6illustrates a cut-away side view of the interposer320along line6—6inFIG. 4, according to an example embodiment.FIG. 6shows the routing of a first signal-carrying or I/O conductor610, and the routing of a second signal-carrying or I/O conductor620associated with the first subset of conductors451and the second subset of conductors452(as shown inFIG. 4). The periphery of the ceramic interposer320is devoid of high K material. As shown inFIGS. 4 and 6, the I/O conductor610is routed through the low K material422positioned on the first major surface321of the interposer320. The I/O conductor610is routed over the low K material422and then through the layer of low K material422and through the main body portion521of the interposer320. The I/O conductor620is routed through the layer of low K material421and then through the main body portion521of the interposer320.

FIG. 7illustrates a cut-away side view of a ceramic interposer320and a flexible substrate730attached to the signal-carrying or I/O lines, such as an I/O line710, according to an example embodiment. The flexible substrate730is made of a low K material such as an organic material such as a polyimide, teflon), and the like. As shown inFIG. 7, the perimeter of the ceramic interposer320includes a portion of low K material422. The low K material422is placed on the first major surface321of the ceramic interposer320. The I/O line710is placed on the low K material422. The I/O line carries a signal from the perimeter of the die310to an area closer to the perimeter of the ceramic interposer320. The flex material or flexible substrate730may be attached to the I/O line710with a C-shaped connector720. The C-shaped connector720includes a coupling portion721which couples the I/O line710to the C-shaped connector720. The C-shaped connector720also includes a conductor for carrying the signal from the I/O line710to the flexible substrate730. The C-shaped connector720also is made of a low K material to prevent cross talk between conductors that carry signals through the C-shaped connector720. The C-shaped connector also includes another contact portion722for making connections to I/O lines, such as an I/O line712, that terminates at or on the second major surface322of the ceramic interposer320.

FIG. 8illustrates another embodiment of a ceramic interposer320attached to a flexible substrate830, according to an example embodiment. The flexible substrate830is made from a low K material and includes conductors that correspond to various I/O lines that are routed or terminate near the outer perimeter of the ceramic interposer320. The ceramic interposer320includes a main body portion521which is made of ceramic and also includes a region421and a region422near the perimeter of the first major surface321of the ceramic interposer320which includes a low K material. An I/O line such as I/O line810is placed atop the low K material422. The I/O line includes a conductor that routes signals from the die310over the low K material422and to a position near the perimeter of the ceramic interposer. A flexible substrate830is connected to the I/O line810near the perimeter of the ceramic interposer320. The flexible substrate830includes a connector831which connects to the end or near the end of the I/O line810. The flexible substrate is made of a low K material and includes a conductor or conductors for carrying the signal that is either carried from the die310or to the die310over the I/O line810. The flexible substrate830can include connections to other components or to outputs or inputs as part of an electronic system.

FIG. 9illustrates a cutaway side view of a ceramic interposer320connected to a flexible substrate930, according to another example embodiment. The ceramic interposer320includes a first major surface321, and a second major surface322. The die310includes a plurality of C4-type ball connectors for power and connections to ground as well as for signal-carrying. As shown inFIG. 9, the C4-type ball or bump910and a C4-type ball or bump912are positioned on the outside or perimeter of the die310and carry signals to and from the die310. The flexible substrate930includes conductors which attach to these I/O or signal-carrying C4-type ball connectors910,912. The flexible substrate930is made of a low K material so as to prevent cross talk between adjacent signal-carrying lines or between the signal-carrying line and a nearby power or ground connection. The flexible substrate also includes a number of connectors that pass directly through the flexible substrate, such as conductors931and932. The flexible substrate is made of a low K material and therefore there is little or no capacitive coupling between the conductor931and the conductor932within the flexible substrate930. The ceramic interposer320is provided with a high K material portion324, which is placed on the first major surface321of the ceramic interposer320. Capacitive coupling between the power and ground conductors occurs in the region having the high K material324. In this particular embodiment, the C4-type connector or balls910,912that carry or transmit I/O signals connect directly to the flexible substrate930. The flexible substrate930also includes conductors such as931and932for directly connecting a power connection to a conductor within the ceramic interposer930or a ground connection from the die310to a ground conductor passing through the ceramic interposer320.

FIG. 10illustrates a cutaway side view of a die310attached to an array capacitor1000, according to an example embodiment. The array capacitor1000includes a series of conductive layers1010,1011,1012,1013, which are separated by insulative layers1020,1021,1022. The conductive layer1010and the conductive layer1012are attached to one of either the ground connections or the power connections while the conductive layers1011and1013are attached to the other of the power connections or ground connections. The insulative layers are very thin. In some embodiments, the insulative layers are as thin as one to two microns. The array capacitor formed includes metal layers1010,1011,1012,1013that have capacitive coupling between the metal layers and therefore the array capacitor1000is formed as a high K material with capacitive coupling between the metal layers1010,1011,1012,1013. The array capacitor1000also includes a spacing layer1030. The array capacitor includes a first major surface1001and a second major surface1002. A layer of high K material1032is positioned on a portion of the first major surface1001of the array capacitor1000. A low K material1034is placed about the perimeter or at least a portion of the perimeter of the first major surface1001of the array capacitor1000. The high K material1032, which is on the first major surface1001of the array capacitor1000, is roughly in the shape of the connectors associated with the die310that carry power to and from the die as well as connections for ground also associated with the die310. I/O signal-carrying lines are placed on the surface of the low K material1034. As shown inFIG. 10, a first I/O line1050and a second I/O line1052are placed on top of the low K material1024. The I/O lines1050,1052provide a conductive path from the outer perimeter of the die310to a position near the outer perimeter of the array capacitor1000. The I/O signal-carrying contacts of the die310are positioned as bumps on the outer perimeter or near the outer perimeter of the die310. The bumps associated with power and ground connections are positioned within the I/O bumps on the die310. The high K material1032placed on the first major surface1001is positioned to correspond to the position of the power and ground bumps of the die. Conductors for transporting power, such as a conductor1060, pass through the high K material1032as well as through the array capacitor1000. Similarly, a ground connector, such as a connector1062, passes through the high K material1032as well as the array capacitor1000. The power and ground connections, such as power connection1060and ground connection1062are capacitively coupled by passing through the high K material1032as well as the high K material formed by the array capacitor. The metal layers1010,1011,1012,1013act as plates attached to a set of power connectors or a set of ground connectors and provide capacitive coupling between the power and ground connections.

FIG. 11illustrates a cutaway side view of a die310attached to an array capacitor1100. The array capacitor1100includes a first major surface1101and a second major surface1102. The embodiment shown inFIG. 11differs from the embodiment shown inFIG. 10in that the first major surface1101of the array capacitor1100has a low K material1134positioned over substantially the entire first major surface1101of the array capacitor1100rather than having a high K material positioned between the between the die310and the array capacitor1100, and on the first major surface1101near the balls or bumps that are used for power and ground connections to and from the die310. The array capacitor1110is termed a high K material. The array capacitor1100includes a power connection, such as a power connection1060, and a ground connection, such as a ground connection1062. The array capacitor1100that is formed provides sufficient capacitive coupling between the power and ground connections1060,1062, respectively, to prevent or substantially reduce voltage variations or parasitic signals between power and ground, even in the absence of another high K material on the first major surface1101of the thin film capacitor. The I/O lines are routed over the low K material1134in a similar fashion to that shown and discussed inFIG. 10.

FIG. 12illustrates a cutaway side view of a die310attached to an array capacitor1000, according to another example embodiment. The array capacitor1000includes a first major surface1001and a second major surface1002. In this example embodiment, the array capacitor1110is termed a high K material. The second major surface includes a set of electrical pads, such as an electrical pad1210associated with a power connector and a pad1212associated with a ground connector. Attached to the pad1210and1212are a socket contact1220and a socket contact1222, respectively. As a result, the device1200as shown can be placed on to a circuit board (such as circuit board100shown inFIG. 1) using the socket contact, such as the socket contacts1220and1222.

FIG. 13illustrates a cutaway side view of a die310attached to an array capacitor1100, according to an example embodiment. The array capacitor1100has a first major surface1101and a second major surface1102. In this example embodiment, the array capacitor1110is termed a high K material. On the second major surface1102are a series of pads, such as a pad for a power connection1310, and a pad for a ground connection1320. Formed on the pads are bumps or balls, such as a ball or bump1312associated with the pad1310and the ball or bump1322associated with the pad1320. As a result, the device1300that includes the die310and the array capacitor1100can be attached to a printed circuit board100(seeFIG. 1) on a set of corresponding pads on the printed circuit board100. In other words, the device1300is a ball grid array type of device and can be surface mounted to the printed circuit board100(seeFIG. 1).

FIG. 14illustrates a cutaway side view of a die310attached to an array capacitor1000with a flexible substrate1430connected to an I/O line1050, according to an example embodiment. The I/O line1050includes an I/O pad1052near the perimeter of the array capacitor1000. The I/O line1050passes over the surface of a low K material1034and provides a conductive path between an I/O contact1410associated with the die310and the I/O pad1052. The flexible substrate1430is connected to the I/O pad1052by way of a C-shaped clamp1420. Both the C-shaped clamp1420and the flexible substrate1430are made of or include low K material, so as to prevent cross talk or conductance between other nearby I/O lines either within the connector1420and the within the flexible substrate1430, or in another structure including another C-shaped connector and another flex substrate. The C-shaped connector1420can include one or more conductive paths from the I/O pad1052. The flexible substrate1430can also include one or more electrical paths. The electrical paths within the C-shaped connector1420and the flexible substrate1430provide a conductive path for the signals being carried by the conductors, such as I/O conductor1050. As mentioned previously, the power and ground connections are capacitively coupled by the high K material1032on the surface of the array capacitor1000. The high K material may include a thin film capacitor. In addition, the power and ground connections are capacitively coupled within the array capacitor1000. The array capacitor1000is yet another high K material. The various plates associated with the array capacitor1000(structure detailed and discussion ofFIG. 10) enhance the capacitive coupling between the power and ground connectors.

FIG. 15illustrates a cutaway side view of a die310attached to an array capacitor1000with a flexible substrate1530attached to an I/O line1050. The I/O line1050includes an I/O pad1052. The flexible substrate1530attaches to the I/O pad1052. The I/O line provides a conductive path between an I/O bump contact1510associated with the die310and the I/O pad1052. Flexible substrate1530connects directly to the I/O pad1052positioned near the perimeter of the array capacitor1000. The flexible substrate1530includes a low K material to prevent transmission or conductance between the conductors carrying the I/O signal from the I/O pad1052and other nearby conductors carrying either power connected to ground or carrying other signals to and from the die310associated with a package1500. As mentioned previously, the power and ground connections are capacitively coupled by the high K material1032on the surface of the array capacitor1000. The high K material may include a thin film capacitor. In addition, the power and ground connections are capacitively coupled within the array capacitor1000. The array capacitor1000is yet another high K material. The various plates associated with the array capacitor1000(structure detailed and discussion ofFIG. 10) enhance the capacitive coupling between the power and ground connectors.FIG. 16illustrates a cutaway side view of a die310attached to an array capacitor1000with a flexible substrate1630attached to the die310. Specifically, the die310includes an electrical contact or solder bump1610that carries I/O signals to and from the die. The flexible substrate1630includes a low K material. The flexible substrate1630also includes a conductive path through the flexible substrate1630and away from the die310to a device which uses the signal carrier. The die310also includes a plurality of power and ground connections, such as power connection1060and ground connection1062. The power and ground connections extend through the flexible substrate1630and into the array capacitor1000. There is sufficient capacitive coupling between the high K material1032, as well as within the array capacitor1000, to provide sufficient capacitive coupling between the power and ground connections, such as1060and1062, respectively. As mentioned previously, the array capacitor1000is termed a high K material.

It is also contemplated, that the options for flexible substrates shown inFIGS. 14–16may also be used on an array capacitor1000that does not include a thin, high K layer, such as a thin film capacitor, is placed between the array capacitor1000and the die310.

An electronic device includes a material having a first dielectric constant (K) value, and a material having a second dielectric constant (K) value. The first dielectric constant (k) value is lower than the second dielectric constant (K) value. The electronic device also includes input/output connection conductors610,710,810,910for transmitting signals to and from the die310(such as shown inFIGS. 6–9). The input/output connection conductors610,710,810,910are routed through the material521of the interposer310having the first dielectric constant (shown inFIGS. 6 and 7). The electronic device also includes power connection conductors550for delivering power to the die, and ground connection conductors560(as shown inFIG. 5). The power and ground connection conductors,550,560, respectively, are routed through the material324having the second dielectric constant(as shown inFIG. 5). In some embodiments, the electronic device is adapted to connect to a die310(as shown inFIGS. 6–9). In other embodiments, the electronic device is adapted to connect to a package substrate.

In still other embodiments, the electronic device includes connectors adapted to electrically couple to a die, and connectors adapted to electrically couple to a package substrate. In still other embodiments, the electronic device further includes a material having a third dielectric constant (K) value. The material having the third dielectric constant may include a substrate that includes an array capacitor, a layer of one material placed on the surface of the array capacitor or a layer of another material placed on the surface of an array capacitor. The first dielectric constant (K) value is lower than the third dielectric constant (K) value and the power and ground connection conductors are routed through the material having the third dielectric constant. In some embodiments, the third dielectric constant value is substantially equal to the second dielectric constant. The material having the first dielectric constant value can be glass or silicon, and the material having the second dielectric constant value is a thin film capacitor or an array capacitor. In some embodiments, the material having the second dielectric constant value can be a thin film capacitor and the material having the third dielectric constant value is an array capacitor. The electronic device can also include socket contacts or ball contacts.

A method1700for routing conductors through an electronic device includes routing input/output conductors through a material having a first dielectric constant,1710and routing power conductors and ground conductors through a material having a second dielectric constant1712. The first dielectric constant has a value lower that the second dielectric constant. The method also includes routing power conductors and ground conductors through a material having a third dielectric constant1714. The first dielectric constant has a value lower than the third dielectric constant. In some embodiments, the third dielectric constant has a value substantially equal to the second dielectric constant.

FIG. 18illustrates an example computer system used in conjunction with certain embodiments of the invention. As illustrated inFIG. 18, computer system1800comprises processor(s)1802. The computer system1800also includes a memory unit1830, processor bus1822, and Input/Output controller hub (ICH)1824. The processor(s)1802, memory unit1830, and ICH1824are coupled to the processor bus1822. The processor(s)1802may comprise any suitable processor architecture. The computer system1800may comprise one, two, three, or more processors, any of which may execute a set of instructions.

The memory unit1830includes an operating system1840, which includes an I/O scheduling policy manager1832and I/O schedulers1834. The memory unit1830stores data and/or instructions, and may comprise any suitable memory, such as a dynamic random access memory (DRAM), or FLASH memory, for example. The computer system1800also includes IDE drive(s)1808and/or other suitable storage devices. A graphics controller1804controls the display of information on a display device1806, according to embodiments of the invention.

The Input/Output controller hub (ICH)1824provides an interface to I/O devices or peripheral components for the computer system1800. The ICH1824may comprise any suitable interface controller to provide for any suitable communication link to the processor(s)1802, memory unit1830and/or to any suitable device or component in communication with the ICH1824. For one embodiment of the invention, the ICH1824provides suitable arbitration and buffering for each interface.

For one embodiment of the invention, the ICH1824provides an interface to one or more suitable integrated drive electronics (IDE) drives1808, such as a hard disk drive (HDD) or compact disc read-only memory (CD ROM) drive, or to suitable universal serial bus (USB) devices through one or more USB ports1810. For one embodiment, the ICH1824also provides an interface to a keyboard1812, a mouse1814, a CD-ROM drive1818, and one or more suitable devices through one or more firewire ports1816. The ICH1824also provides a network interface1820though which the computer system1800can communicate with other computers and/or devices on a computer network1840. The network interface couples the network1840to the computer system1800via a link1842. The link1842can include a hard wire coupling or a wireless, or both. The computer system1800can be any type of computer such as a desktop, server or hand-held device coupled to any type of computer network. Uses of the example embodiments described above include use as a processor1802in a desktop, a server, or a mobile type computer system1800. The processor1802could be a microprocessor. The example embodiments described above could be used as a chipset, in a handheld device such as a cell phone or PDA's. The circuit board100(seeFIG. 1) can be a printed circuit board or the like and can include substantially all of the computer system1800or parts of the computer system.

In one embodiment, the computer system1800includes a machine-readable medium that stores a set of instructions (e.g., software) for controlling the computer system1800and sending or receiving information to or from the network1840. The set of instructions (software) can reside, completely or at least partially, within memory unit1830and/or within the processor(s)1802.

Thus, a system, method, and machine-readable medium including instructions for Input/Output scheduling have been described. Although the present invention has been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosed subject matter. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Accordingly, the invention is intended to embrace all such alternatives, modifications, equivalents and variations as fall within the spirit and broad scope of the appended claims.