Micromechanical device and methods to fabricate same using hard mask resistant to structure release etch

A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a structure composed of a silicon layer disposed over an insulating layer that is disposed on a silicon substrate. The silicon layer is differentiated into a partially released region that will function as a portion of the electro-mechanical device. The method further includes forming a dielectric layer over the silicon layer; forming a hardmask over the dielectric layer, the hardmask being composed of hafnium oxide; opening a window to expose the partially released region; and fully releasing the partially released region using a dry etching process to remove the insulating layer disposed beneath the partially released region while using the hardmask to protect material covered by the hardmask. The step of fully releasing can be performed using a HF vapor.

TECHNICAL FIELD

The exemplary embodiments of this invention relate generally to miniaturized electrical-mechanical devices, such as switches, and more specifically to micro-electrical-mechanical systems (MEMS) and to nano-electrical-mechanical systems (NEMS) and devices.

BACKGROUND

MEMS relate to a technology of very small electrically driven mechanical devices. MEMS converges at the nano-scale with NEMS and nanotechnology in general. MEMS are sometimes referred to as micro-machines or as micro systems technology (MST). MEMS include components between about 1 to 100 micrometers in size and larger. NEMS devices are smaller still. At the size scales of MEMS devices, and even more so NEMS devices, the standard constructs of classical physics are not always useful. Due at least to the large surface area to volume ratio surface effects, such as electrostatics and wetting, can dominate the volume effects such as inertia or thermal mass.

MEMS and NEMS can be fabricated using semiconductor device fabrication technologies normally used to make electronic devices. These include photolithographic patterning, sputtering, evaporation, and wet and dry etching.

SUMMARY

In a first aspect thereof the exemplary embodiments of this invention provide a method to fabricate an electro-mechanical device. The method includes providing a structure comprised of a silicon layer disposed over an insulating layer that is disposed on a silicon substrate. The silicon layer is differentiated into a partially released region that will function as a portion of the electro-mechanical device. The method further includes forming a dielectric layer over the silicon layer; forming a hardmask over the dielectric layer, the hardmask being comprised of hafnium oxide; opening a window to expose the partially released region; and fully releasing the partially released region using a dry etching process to remove the insulating layer disposed beneath the partially released region while using the hardmask to protect material covered by the hardmask.

In another aspect thereof the exemplary embodiments of this invention provide a structure that comprises a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor comprising metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer.

In yet another aspect thereof the exemplary embodiments of this invention provide a method to fabricate a device. The method comprises providing a structure comprised of a silicon layer disposed over an insulating layer that is disposed on a silicon substrate, the silicon layer comprising at least one partially released region intended to function as a portion of an electro-mechanical device. The method further includes forming a dielectric layer over the silicon layer; depositing a layer comprised of hafnium oxide over the dielectric layer; opening a window to expose the partially released region; and fully releasing the partially released region using a dry etching process to remove the insulating layer disposed beneath the partially released region while using the layer comprised of hafnium oxide to protect material covered by the hardmask. In the method providing the structure further comprises providing at least one transistor device formed on or in the silicon layer, and the layer comprised of hafnium oxide is deposited to cover the transistor device and metal associated with the transistor device.

DETAILED DESCRIPTION

The use of NEMS (and MEMS) as switches in memory and other applications can be beneficial. For example, as compared to transistors electro-mechanical switches can reduce standby leakage current and potentially can exhibit improved sub-threshold behavior. However the large control gate voltage (typically some tens volts) and overall reliability are two issues that need to be addressed in order to use NEMS as switches.

A silicon-on-insulator (SOI) substrate can be used for NEMS applications. The co-integration of complementary metal oxide semiconductor (CMOS) and NEMS technologies can be achieved using SOI wafers.

There is increased interest in NEMS/MEMS CMOS co-integration to deliver increased functionality and reduced power consumption and/or to provide electrical readout for NEMS/MEMS.

SOI NEMS/MEMS exhibit good mechanical properties. SOI NEMS/MEMS devices have found wide application as sensors and transducers. In addition SOI-based transistors are a mainstream manufacturing technology (e.g., partially depleted SOI or PDSOI) and show promise for next generation CMOS scaling (FinFET/Trigate and extremely thin SOI (ETSOI)). SOI NEMS/MEMS and SOI FinFET/Trigate transistors can be integrated monolithically.

An important step in NEMS/MEMS fabrication is structure release, whereby a moveable portion of the NEMS/MEMS device is physically released from the surrounding silicon material and the underlying layer of oxide (buried oxide or BOX) over which it has been photolithographically defined.

There are certain issues associated with fabricating NEMS/MEMS structures. For example, one issue relates to a conventional wet chemical etch (e.g., one based on hydrofluoric (HF) acid). In general a wet chemical etch can be disadvantageous for achieving the NEMS release and subsequent processing as it can result in an increase in NEMS stiction. Stiction may be generally defined as a force required to cause one body that is in contact with another body to begin to move.

Vapor HF is one known technique to release a MEMS/NEMS structure formed on a sacrificial layer of SiO2.

It is known that concentrated HF will attack photoresist. In response a buffered oxide etch (BOE, HF and ammonium fluoride) is commonly used when photoresist is present. HF vapor is similar to concentrated HF as it can cause integration issues with photoresist.

When HF vapor is employed important requirements for a mask to be used for NEMS/MEMS release, especially when co-integrated with CMOS devices, include a requirement that the mask be resistant to the HF vapor, and that the mask can subsequently be easily removed by a reactive ion etch (RIE) or by dry processing. Ideally the mask removal process should not attack or degrade any already present Si/silicide/metals such as Cu and/or W/nitride.

The exemplary embodiments of this invention provide a process flow that uses HfO2as a hard mask for MEMS/NEMS HF vapor release.

In accordance with the exemplary embodiments of this invention a layer of HfO2is deposited over a structure containing a NEMS/MEMS that is to be released. An opening is formed in the layer of HfO2using photolithography and RIE. The layer of HfO2serves as hard mask during NEMS/MEMS release, as even a very thin layer (˜2 nm) of HfO2is very resistant to HF and oxide RIE chemistries. The HfO2layer is then subsequently removed by, for example, an RIE process after the NEMS/MEMS structure is released by the use of, for example, a dry, vapor HF process to mitigate stiction and other issues.

In accordance with an exemplary embodiment the HfO2hard mask-based process flow can be integrated with a protective spacer (e.g., a spacer formed from a nitride such as Si3N4) to prevent an aggressive undercutting of back end of line (BEOL) dielectrics during the HF mediated release process.

It is pointed out that the teachings of this invention are not limited to the fabrication of NEMS devices per se, but can be applied as well to the fabrication of MEMS devices and, in general, to the fabrication of a variety of miniaturized electrical-mechanical systems and devices. In addition, the embodiments can be applied to both SOI and ETSOI starting wafers.

Note that the various layer thicknesses discussed below are merely exemplary. As such, and by example, embodiments of this invention can be practiced using an extremely thin SOI (ETSOI) wafer, where the BOX layer may have a thickness of about 50 nm or less and where the overlying layer of Si may have a thickness of about 10 nm or less.

Note as well that the layer thicknesses shown inFIGS. 2 and 3are not drawn to scale.

FIG. 1is a top enlarged view of one exemplary and non-limiting embodiment of a (symmetrical) NEMS switch10that could be constructed using the exemplary embodiments of this invention using a SOI wafer. The structure shown may be formed to have a total area of less than 5 μm2. The switch10includes an input terminal12, an output terminal14and control electrodes or terminals16and18(designated Vdd and GND, respectively.) The application of a suitable control input to the terminals16and18results in flexure (motion) of a moveable at least partially electrically conductive structure20between a not actuated state and an actuated state. When in the actuated state (the switch is turned on) an electrically conductive path is established between the input terminal12and the output terminal14via the electrically conductive portion of the structure20that physically contacts the input terminal12and the output terminal14.

FIGS. 2A-2Gshow an exemplary process flow in accordance with certain embodiments of this invention.FIGS. 3A-3Eshow another exemplary process flow further in accordance with the embodiments of this invention. It can be noted that while a single released member is shown as being formed, in practice a large number of such released members can be simultaneously foamed.

The embodiment ofFIGS. 2A-2Gwill be described first.

InFIG. 2Aa starting SOI wafer30is provided. The SOI wafer30includes a substrate (e.g., Si)32, a layer of buried insulator or buried oxide (BOX)34, such as SiO2, and an overlying layer of Si36. The substrate32can have any suitable thickness. The BOX34can have a thickness in the range of, for example, about 100 nm to about 200 nm, with about 140 nm being one suitable value. The Si layer36can have an initial thickness in the range of, for example, about 50 nm to about 100 nm, with about 80 nm being one suitable value. InFIG. 2Ait is assumed that the Si layer36, in which the NEMS structure will be fabricated, has been thinned to a desired thickness in a range of, for example, about 20 nm to about 50 nm, with about 30 nm being one suitable value. The Si layer36is masked and patterned and a reactive ion etch (RIE) process is used to selectively remove a portion of the Si layer36to delineate the desired NEMS structure. InFIG. 2Athe delineated portion is designated38and can correspond to, for example, what will form a part of the moveable electrically conductive structure20shown inFIG. 1. This process also forms what may be referred to as openings or apertures36athrough the thinned Si layer36. The delineated portion38can be considered herein as a “partially released” region of the Si layer36, as it is still disposed on the surface of the underlying BOX34. This partially released region of the Si layer36will be fully released during the performance of the dry etch process described below in reference toFIG. 2FandFIG. 3D.

FIG. 2Aalso shows an example of a transistor40(a CMOS transistor) that has been fabricated in or on the Si layer36. The stage of processing shown inFIG. 2Amay be considered to be at the completion of a front end of line (FEOL) portion of processing wherein the NEMS and CMOS transistor have been co-integrated. The transistor40can be any type of desired transistor, including a FinFET or a Tri-gate FET.

FIG. 2Bshows the structure ofFIG. 2Aafter deposition of transistor metal (e.g., metal1(M1) and metal2(M2)), a back end of line (BEOL) film stack42(oxide, nitride) and an overlying layer of nitride (e.g., Si3N4). The M1can be any desired contact area (CA) metal such as tungsten and can have an exemplary thickness in the range of about 700-800 Å, while the M2could be thicker and be composed of, for example, copper or tungsten.

FIG. 2Cshows the structure ofFIG. 2Bafter deposition of a hardmask (HM) layer46, preferably one composed of HfO2. The HfO2HM layer46can have a thickness in a range of about 1-5 nm, with about 2-3 nm being more preferred. The HfO2HM layer46can be deposited using atomic layer deposition (ALD) and preferably exhibits a high quality, substantially defect free surface. The use of ALD to deposit HfO2is well characterized in the art. As two examples, reference can be made to Synthesis and Surface Engineering of Complex Nanostructures by Atomic Layer Deposition, M. Knez et al., Adv. Mater. 2007, 19, 3425-3438, and to Investigation of Self-Assembled Monolayer Resists for Hafnium Dioxide Atomic Layer Deposition, R. Chen et al., Chem. Mater. 2005, 17, 536-544.

FIG. 2Dshows the structure ofFIG. 2Cafter deposition of a layer of photoresist48, the patterning of the photoresist48to define a NEMS window50, and the selective etching of the underlying HfO2HM layer46, the nitride layer44and the BEOL film stack down to the delineated portion of the NEMS structure38to form the NEMS window50. The selective etching is preferably a multi-step RIE process where the HfO2HM layer46is removed with a 250° C. chuck temperature using BCl3/Ar at a 5:1 ratio. The oxide/nitride RIE can use CFxwith Ar or O2.

FIG. 2Eshows the structure ofFIG. 2Dafter the layer of photoresist48is stripped thereby exposing the upper surface of the underlying HfO2HM layer46.

FIG. 2Fshows the structure ofFIG. 2Eafter a dry etch, more specifically a vapor HF etch process, is performed to completely remove through the NEMS window50remaining portion of the BEOL film stack42adjacent to the delineated portion38of the Si layer36and the underlying material of the BOX34, thereby forming a cavity within the BOX material and releasing the delineated portion38from the BOX layer34to form a released structure38A. InFIG. 2Fa region of connection between the released structure38A and the Si layer36is not shown. The result of the isotropic vapor HF etch process also serves to undercut to some distance the material of the BOX layer34beneath the Si layer36as well as to undercut the BEOL film stack42beneath the nitride layer44. Due to the difference in growth temperatures the BEOL film stack42can be undercut to a greater extent than the BOX34.

In accordance with an aspect of this invention the HfO2HM layer46is resistant to the vapor HF etch, thereby protecting the underlying material layers.

FIG. 2Gshows the structure ofFIG. 2Fafter the HfO2HM layer46is removed. The removal process can include a first step of damaging/degrading the surface of the HfO2HM layer46followed by RIE using the same chemistry as inFIG. 2D, i.e., a 250° C. chuck temperature using BCl3/Ar at a 5:1 ratio. The surface of the HfO2HM layer46can be damaged using, for example, a high energy Ar bombardment. This enables the HfO2HM layer46to be quickly removed by the RIE process with minimal impact of the other structures.

At this point the structure shown inFIG. 2Gcan be further processed as desired, such as by siliciding at least a portion of the released structure38A as described in commonly owned U.S. patent application Ser. No. 13/164,126, filed 20 Jun. 2011, entitled “Silicide Micromechanical Device and Methods to Fabricate Same”, by Michael A. Guillorn, Eric A. Joseph, Fei Liu and Then Zhang.

A description is now made ofFIGS. 3A-3Ewhich show another exemplary process flow further in accordance with embodiments of this invention, specifically the use of a nitride spacer to prevent the undercutting of the BEOL film stack42during the HF etch step.

FIG. 3Ais comparable to the structure shown inFIG. 2E, i.e., the structure ofFIG. 2Dafter the NEMS window50has been opened and the layer of photoresist48has stripped thereby exposing the upper surface of the underlying HfO2HM layer46.

FIG. 3Bshows the structure ofFIG. 3Aafter a nitride layer60has been blanket deposited. The nitride layer (e.g., Si3N4) can have a thickness in a range of several nanometers to several tens of nanometers and covers the top surface of the HfO2HM layer46and the sidewalls and bottom surface of the opened NEMS window50.

FIG. 3Cshows the structure ofFIG. 3Bafter a conventional nitride RIE process that serves to remove the nitride from horizontal surfaces, leaving a nitride sleeve or spacer62that lines the vertical sidewalls of the opened NEMS window50.

FIG. 3Dshows the structure ofFIG. 3Cafter the dry etch is performed, more specifically the vapor HF etch process. As before the vapor HF etch completely removes through the NEMS window50remaining portion of the BEOL film stack42adjacent to the delineated portion38of the Si layer36and the underlying material of the BOX34, thereby forming the cavity within the BOX material and releasing the delineated portion38from the BOX layer34to form the released structure38A. The result of the isotropic vapor HF etch process also serves to undercut to some distance the material of the BOX layer34beneath the Si layer36. However, due to the presence of the nitride spacer62the undercutting of the BEOL film stack42is avoided.

FIG. 3Eshows the structure ofFIG. 3Dafter the HfO2HM layer46is removed. The removal process can be performed as described above forFIG. 2G.

Many modifications and variations can become apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. For example, different materials, metals, thicknesses, processing steps and parameters can be used. Further, the exemplary embodiments are not limited to the fabrication of switches in MEMS or in NEMS devices and structures.

As such, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. As but some examples, the use of other similar or equivalent mathematical expressions may be used by those skilled in the art. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention.