Noise reduction in digital systems

A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to noise reduction in digital systems, and more specifically, to noise reduction by asserting clock signals at different times.

2. Related Art

In the normal operation of a conventional digital system, simultaneous clocking of registers of the conventional digital system can cause signal noise. Therefore, there is a need for a digital system (and a method for operating the same) in which the noise due to the simultaneous clocking of data registers can be reduced compared to prior art.

SUMMARY OF THE INVENTION

The present invention provides a digital system, comprising (a) a first logic circuit and a second logic circuit; (b) a first register electrically coupled to the first logic circuit; (c) a second register electrically coupled to the first logic circuit and the second logic circuit; (d) a third register electrically coupled to the second logic circuit; (e) a clock generator circuit electrically coupled to the first, second, and third registers; and (f) a controller circuit electrically coupled to the clock generator circuit, wherein the first logic circuit is capable of obtaining first data from the first register, processing the obtained first data into second data, and sending the second data to the second register, wherein the second logic circuit is capable of obtaining the second data from the second register, processing the obtained second data into third data, and sending the third data to the third register, wherein the clock generator circuit is capable of asserting a first register clock signal at a first time point to the first register resulting in the first logic circuit obtaining the first data from the first register, wherein the clock generator circuit is further capable of asserting a second register clock signal at a second time point to the second register resulting in the second logic circuit obtaining the second data from the second register, wherein the clock generator circuit is further capable of asserting a third register clock signal at a third time point to the third register, wherein the controller circuit is capable of (i) determining a first processing time for the first logic circuit to obtain the first data, process the obtained first data into the second data, and send the second data to the second register, (ii) determining a second processing time for the second logic circuit to obtain the second data, process the obtained second data into the third data, and send the third data to the third register, (iii) determining a fourth time point after the first time point such that a first time duration between the first time point and the fourth time point is at least the first processing time, (iv) determining a fifth time point before the third time point and after the fourth time point such that a second time duration between the fifth time point and the third time point is at least the second processing time, wherein the fourth time point and the fifth time point define a first clock window, and (v) controlling the clock generator circuit to assert the second register clock signal such that the second time point is within the first clock window.

The present invention provides a digital system operation method, which comprises providing a digital system which includes (a) a first logic circuit and a second logic circuit, (b) a first register electrically coupled to the first logic circuit, (c) a second register electrically coupled to the first logic circuit and the second logic circuit, (d) a third register electrically coupled to the second logic circuit, (e) a clock generator circuit electrically coupled to the first, second, and third registers, and (f) a controller circuit electrically coupled to the clock generator circuit; using the clock generator circuit to assert a first register clock signal at a first time point to the first register; using the clock generator circuit further to assert a second register clock signal at a second time point to the second register; using the clock generator circuit to further assert a third register clock signal at a third time point to the third register; in response to the clock generator circuit asserting the first register clock signal at the first time point to the first register, using the first logic circuit to obtain first data from the first register, process the obtained first data into second data, and send the second data to the second register; in response to the clock generator circuit further asserting the second register clock signal at the second time point to the second register, using the second logic circuit to obtain the second data from the second register, process the obtained second data into third data, and send the third data to the third register; using the controller circuit to (i) determine a first processing time for the first logic circuit to obtain the first data, process the obtained first data into the second data, and send the second data to the second register; (ii) determine a second processing time for the second logic circuit to obtain the second data, process the obtained second data into the third data, and send the third data to the third register; (iii) determine a fourth time point after the first time point such that a first time duration between the first time point and the fourth time point is at least the first processing time; (iv) determine a fifth time point before the third time point and after the fourth time point such that a second time duration between the fifth time point and the third time point is at least the second processing time; wherein the fourth time point and the fifth time point define a first clock window, and (vi) control the clock generator circuit to assert the second register clock signal such that the second time point is within the first clock window.

The present invention provides a digital system, comprising (a) a first logic circuit and a second logic circuit; (b) a first register electrically coupled to the first logic circuit; (c) a second register electrically coupled to the first logic circuit and the second logic circuit; (d) a third register electrically coupled to the second logic circuit; (e) a clock generator circuit electrically coupled to the first, second, and third registers; and (f) a controller circuit electrically coupled to the clock generator circuit, wherein the first logic circuit comprises a fast logic circuit and a slow logic circuit, wherein the fast logic circuit and the slow logic circuit are capable of performing a same function, wherein the first logic circuit is capable of obtaining first data from the first register, processing the obtained first data into second data, and sending the second data to the second register, wherein the second logic circuit is capable of obtaining the second data from the second register, processing the obtained second data into third data, and sending the third data to the third register, wherein the clock generator circuit is capable of asserting a first register clock signal at a first time point to the first register resulting in the first logic circuit obtaining the first data from the first register, wherein the clock generator circuit is further capable of asserting a second register clock signal at a second time point to the second register resulting in the second logic circuit obtaining the second data from the second register, wherein the clock generator circuit is further capable of asserting a third register clock signal at a third time point to the third register, wherein a first plurality of registers receive as input the second register clock signal, wherein a second plurality of registers receive as input the third register clock signal, wherein the controller circuit is capable of (i) determining a first processing time for the first logic circuit to obtain the first data, process the obtained first data into the second data, and send the second data to the second register, (ii) determining a second processing time for the second logic circuit to obtain the second data, process the obtained second data into the third data, and send the third data to the third register, (iii) determining a fourth time point after the first time point such that a first time duration between the first time point and the fourth time point is at least the first processing time, (iv) determining a fifth time point before the third time point and after the fourth time point such that a second time duration between the fifth time point and the third time point is at least the second processing time, wherein the fourth time point and the fifth time point define a first clock window, and (v) controlling the clock generator circuit to assert the second register clock signal such that the second time point is within the first clock window.

The present invention provides a novel digital system (and a method for operating the same) in which the noise due to the simultaneous clocking of data registers can be reduced compared to prior art.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows a digital system100, in accordance with embodiments of the present invention. More specifically, in one embodiment, the digital system100comprises multiple register banks (e.g., register banks110,120, and130). Although the digital system100has many register banks, only the three register banks110,120, and130of the digital system100are shown inFIG. 1. Illustratively, the register bank110comprises multiple registers (e.g., registers111,112,113,114,115, and116). It should be noted that the register bank110comprises many registers but only the six registers111through116are shown inFIG. 1. Similarly, the register banks120and130comprise multiple registers (e.g., registers121,122of the register bank120and registers131,132of the register bank130). In one embodiment, similarly, the other register banks in the digital system100comprise multiple registers. In one embodiment, the digital system100further comprises multiple logic circuits electrically coupled between the register banks110and120(e.g., logic circuits142,144, and146). In one embodiment, the digital system100further comprises multiple logic circuits electrically coupled between the register banks120and130(e.g., logic circuits152,154, and156). In one embodiment, the digital system100further comprises a clock generator circuit170electrically coupled to the register banks110,120and130. In one embodiment, each register of each register bank of the digital system100receives one clock signal from the clock generator circuit170. More specifically, in one embodiment, for illustration, the registers121,122,131, and132receive clock signals CLK121, CLK122, CLK131, and CLK132, respectively, from the clock generator circuit170. Although the clock generator circuit170generates many clock signals, only the four clock signals CLK121, CLK122, CLK131, and CLK132are shown inFIG. 1. In one embodiment, the digital system100further comprises a controller circuit160electrically coupled to the clock generator circuit170.

FIG. 2shows a detail configuration of the logic circuit142ofFIG. 1, in accordance with embodiments of the present invention. More specifically, in one embodiment, the logic circuit142comprises inverters205,240,245, and250. In one embodiment, the logic circuit142further comprises NAND gates210,215,230,235and OR gates220and225. In one embodiment, the inverters, NAND gates, and OR gates of the logic circuit142are electrically coupled together as shown. As can be seen inFIG. 2, the logic circuit142has six inputs IN1, IN2, IN3, IN4, IN5, IN6and two outputs OUT1and OUT2. In one embodiment, the six input signals IN1, IN2, IN3, IN4, IN5, and IN6come from the six registers111through116of the register bank110ofFIG. 1, respectively, and the two output signals OUT1and OUT2go to the two registers121and122of the register bank120ofFIG. 1, respectively. In one embodiment, similar to the logic circuit142, each of the other logic circuits of the digital system100ofFIG. 1can comprise logic elements (e.g., inverters, NAND gates, and OR gates, etc.) which are electrically coupled together and can have multiple inputs and multiple outputs.

FIG. 3shows a detail configuration of the clock generator circuit170ofFIG. 1, in accordance with embodiments of the present invention. More specifically, in one embodiment, the clock generator circuit170comprises multiple delay circuits (e.g., delay circuits310,320, and330) electrically coupled together in a chain. It should be noted that the clock generator circuit170may have many delay circuits but only the three delay circuits310,320, and330are shown inFIG. 3. In one embodiment, the delay circuit310receives a master clock signal and generates a clock signal CLK1to the delay circuit320. In one embodiment, the delay circuit320receives the clock signal CLK1from the delay circuit310and generates a clock signal CLK2to the delay circuits330. Similarly, the delay circuit330receives the clock signal CLK2from the delay circuit320and generates a clock signal CLK3. In one embodiment, similarly, the other delay circuits in the chain of the clock generator circuit170are coupled in a similar manner. In one embodiment, the clock generator circuit170further comprises multiple multiplexer (MUX) circuits (e.g., MUX circuits341and342). Although the clock generator circuit170may have many MUX circuits, only the MUX circuits341and342are shown inFIG. 3for illustration. The way the other MUX circuits are coupled to the delay circuits of the clock generator circuit170will be described later. In one embodiment, the MUX circuits341and342receive the three clock signals: master clock, CLK1, and CLK2. In one embodiment, the MUX circuits341and342also receive control signals161and162, respectively, from the controller circuit160. In one embodiment, the MUX circuits341and342also generate clock signals CLK121and CLK122to the registers121and122of the register bank120ofFIG. 1, respectively. It should be noted that the clock signal CLK121comes from one of the master clock, clock signal CLK1, and clock signal CLK2depending on the control signal161. Similarly, the clock signal CLK122comes from one of the master clock, clock signal CLK1, and clock signal CLK2depending on the control signal162. In one embodiment, the remaining MUX circuits of clock generator circuit170will generate multiple clock signals one to one to the other registers ofFIG. 1.

In one embodiment, with reference toFIGS. 1,2, and3, the operation of the digital system100is as follows. In one embodiment, to simplify the description of the present invention, assume that one clock cycle of the digital system100is one hour. In one embodiment, assume further that in a first clock cycle starting at 8:00 AM, the controller circuit160controls the clock generator circuit170such that all clock signals going to the registers inFIG. 1are asserted at a same time (e.g., at 8:00 AM). In response, each of the logic circuits in the digital system100obtains data from registers of the register bank on the left, processes the obtained data, and sends the processed data to registers of the register bank on the right. More specifically, for instance, at 8:00 AM the logic circuit142obtains data from registers111through116of the register bank110, processes the obtained data, and sends the processed data to the registers121and122of the register bank120. Assume further that in a second clock cycle starting around 9:00 AM, the logic circuit152will obtain the data from the register121, process the obtained data, and send the processed data to the register131. Assume further that in the second clock cycle, the logic circuit154will obtain the data from the register122, process the obtained data, and send the processed data to the register132. Assume further that in a third clock cycle, the clock signals CLK131and CLK132will be asserted at 10:00 AM. In one embodiment, the processed data from the logic circuits152and154will be ready in the registers131and132, respectively, before the clock signals CLK131and CLK132are asserted at 10:00 AM. One recognizes that each group of registers is clocked every cycle. For the purpose of this example, data proprogating thru the pipeline is being illustrated.

Assume that the controller circuit160determines that the logic circuit142takes only 40 minutes to have the processed data ready in the registers121and122. In other words, a first processing time of the logic circuit142is 40 minutes. This means that the processed data is ready in the registers121and122at 8:40 AM. Assume further that the controller circuit160determines that the logic circuit152and154take 45 minutes and 50 minutes to have processed data ready in the registers131and132of register bank130, respectively. In other words, a second processing time and a third processing time of the logic circuits152and154are 45 and 50 minutes, respectively. As a result, the controller circuit160determines that a first clock window for the clock signal CLK121is from 8:40 AM to 9:15 AM (the first clock window is a window in which the clock signal CLK121can be asserted such that the register121has processed data from the logic circuit142and the register131has processed data before the clock signal CLK131is asserted at 10:00 AM). Similarly, the controller circuit160determines that a second clock window for the clock signal CLK122is from 8:40 AM to 9:10 AM (the second clock window is a window in which the clock signal CLK122can be asserted such that the register122has processed data from the logic circuit142and the register132has processed data before the clock signal CLK132is asserted at 10:00 AM). Therefore, in one embodiment, the controller circuit160controls the clock generator circuit170to assert the clock signals CLK121and CLK122in the first and second clock windows, respectively. This ensures that the processed data from the logic circuits152and154will be ready in the registers131and132, respectively, before the clock signals CLK131and CLK132are asserted at 10:00 AM.

In one embodiment, the controller circuit160determines that the clock signal CLK121will be asserted at 9:00 AM (which is within the first clock window) and the clock signal CLK122will be asserted at 9:05 AM (which is within the second clock window). Assume that the master clock is asserted at 8:00 AM, 9:00 AM, 10:00 AM, etc. Assume further that each delay circuit (e.g., delay circuit310,320, and330) delays 5 minutes. As a result, the clock signal CLK1is asserted at 8:05 AM, 9:05 AM, 10:05 AM, etc; the clock signal CLK2is asserted at 8:10 AM, 9:10 AM, 10:10 AM, etc; and the clock signal CLK3is asserted at 8:15 AM, 9:15 AM, 10:15 AM, etc.

In one embodiment, for instance, in order to assert the clock signal CLK121at 9:00 AM, the controller circuit160controls the clock generator170to generate the control signal161so as to cause the MUX circuit341to pass the master clock through it as the clock signal CLK121to the register131. As a result, the clock signal CLK121will be asserted at 9:00 AM which is in the first clock window. This ensures that the processed data from the logic circuit152will be ready in the register131of the register bank130before the clock signal CLK131is asserted at 10:00 AM.

In one embodiment, similarly, in order to assert the clock signal CLK122at 9:05 AM, the controller circuit160controls the clock generator170to generate a control signal162so as to cause the MUX circuit342to pass the clock signal CLK1through it as the clock signal CLK122to the register132. As a result, the clock signal CLK122will be asserted at 9:05 AM which is in the second clock window. This ensures that the processed data from the logic circuit154will be ready in the register132of the register bank130before the clock signal CLK132is asserted at 10:00 AM.

In summary, the clock signals CLK121and CLK122are asserted at different times for the second clock cycle (9:00 AM and 9:05 AM, respectively). As a result, noise is reduced.

In one embodiment, the controller circuit160ofFIG. 1is a state machine. In an alternative embodiment, the controller circuit160ofFIG. 1contains a microcode that helps the controller circuit160perform its functions described above.

In the embodiment described above, it is assumed that the process data is ready in the registers121and122at the same time. In an alternative embodiment, it takes different processing times to have processed data ready in the registers121and122.

In the embodiment described above, with reference toFIG. 3, each of the MUX circuit341and342receive the three clock signals: master clock, CLK1, and CLK2. Alternatively, each of the MUX circuit341and342can receive N clock signals, N being positive integer. For example, the MUX circuit341can receive clock signals CLK1, CLK2, CLK3, and CLK4; and the MUX circuit342can receive clock signals CLK1, CLK3, CLK6, and CLK11. As a result, the clock signal CLK121can be asserted at either 9:05 AM, 9:10 AM, 9:15 AM or 9:20 AM for the second clock cycle around the start of the second clock cycle. Similarly, the clock signal CLK122can be asserted at either 9:05 AM, 9:15 AM, 9:30 AM or 9:55 AM for the second clock cycle around the start of the second clock cycle.

In the embodiments described above, each register of digital system100ofFIG. 1receives a clock signal from the clock generator circuit170. In an alternative embodiment, the registers of one register bank of the digital system100are divided into group, wherein each group receives one clock signal from the clock generator circuit170. For example, the registers111through116can be grouped together, and receive the same clock signal from the clock generator circuit170.

FIG. 4shows a detail configuration of another embodiment of the logic circuit142ofFIG. 1, in accordance with embodiments of the present invention. More specifically, in one embodiment, the logic circuit142comprises a fast logic circuit142a, a slow logic circuit142b, a MUX circuit142c, and a MUX circuit142d, which are electrically coupled together as shown. It should be noted that the MUX circuits142cand142dreceive control signals (not shown) from the controller circuit160. In one embodiment, the fast logic circuit142aand the slow logic circuit142bperform the same function, but the fast logic circuit142ais faster than the slow logic circuit142bin performing the function. However, the fast logic circuit142aconsumes more energy than the slow logic circuit142b. In one embodiment, the other logic circuits of the digital system100have similar structure as the logic circuit142ofFIG. 4. In one embodiment, in each particular clock cycle, one of the fast logic circuit142aand the slow logic circuit142bis selected by the controller circuit160to obtain data from the registers111through116of register bank110via the MUX circuit142c, processes the obtained data, and sends the processed data to the registers121and122of register bank120via the MUX circuit142d. The non-selected circuit of the fast logic circuit142aand the slow logic circuit142bdoes not operate (does not consume energy).

In the embodiments described above, with reference toFIGS. 1,3, and4, in the first clock cycle, the controller circuit160can select the fast logic circuit142ato operate (the slow logic circuit142bdoes not operate). As a result, the first and the second clock window are wider than the case in which the controller circuit160selects the slow logic circuit142bto operate.

In summary, in operation processing of the digital system100ofFIG. 1, the times at which the clock signals CLK121and CLK122are asserted can be spread out. As a result, noise is reduced.

In the embodiments described above, for simplicity, it is assumed that the controller circuit160causes the clock generator circuit170to simultaneously assert the clock signals to all the registers of the digital system100at 8:00 AM and again at 10:00 AM. Only at around 9:00 AM, the clock signals to the registers are asserted at different times. More specifically, the clock signal CLK121to the register121is asserted at 9:00 AM and the clock signal CLK122to the register122is asserted at 9:05 AM. In an alternative embodiment, the clock signals to the registers of the digital system100are asserted at different times around any clock cycle boundary including around 8:00 AM and 10:00 AM.