A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.

BACKGROUND

1. Field of the Invention

This invention relates to generation of clock signals for electronic devices.

2. Description of the Related Art

Electronics devices utilize clock signals to control operation of, e.g., synchronous digital circuits. Clock signals have commonly been generated using crystal oscillators and phase-locked loops. More recently, digital interpolative synthesis has been utilized as described in U.S. Pat. No. 7,417,510. In such an approach, a reference clock is divided by a fractional-N divider, and jitter introduced by the fractional-N divider is reduced by interpolating the output of the fractional-N divider based on the digital quantization error generated by the delta sigma modulator used to control the fractional-N divider. One approach for the interpolation was to interpolate between various phases of the output from the fractional-N divider in order to reduce jitter. In an alternative approach a half clock reference was used to give the interpolator more time to computer interpolated edges since the dynamic range is halved. However, various prior art approaches may have a long absolute delay through the interpolator or require precise duty cycles of the reference clock.

SUMMARY

In an embodiment, an integrated circuit includes a fractional-N divider circuit coupled to receive a first clock signal and supply a divided clock signal. A digital to time converter circuit receives the divided clock signal and a digital value corresponding to a quantization error associated with the fractional-N divider circuit and supplies an adjusted divided clock signal having a delay linearly proportional to the digital quantization error. The digital-to-time converter circuit includes a first capacitor and a second capacitor. The digital-to-time converter circuit further includes a first circuit and a second circuit, which are selectively coupled to supply current to the first and second capacitors. The digital to time converter circuit is configured to generate a first edge of a pulse of the adjusted divided clock signal in response to the first capacitor charging to a predetermined voltage and the digital-to-time converter circuit is configured to generate a next pulse of the adjusted divided clock signal in response to the second capacitor charging to the predetermined level.

In another embodiment a method includes dividing an input clock signal in a divider circuit by integer values. The first capacitor is charged with a first current based on a first quantization error associated with a first integer divide value for the divider circuit. The first capacitor is also charged with a second current having a fixed value. A first pulse of an output clock is generated in response to the first capacitor charging to a predetermined level. A second capacitor is charged with a third current based on a second quantization error associated with a second integer divide value for the divider circuit. The second capacitor is also charged with a fourth current having the fixed value. A second pulse of the output clock signal is generated in response to the second capacitor charging to the predetermined level.

In another embodiment, a method includes supplying a clock signal to a fractional-N divider circuit and supplying a divided clock signal from the fractional-N divider circuit. A first capacitor is charged with a first current corresponding to a first digital quantization error during a first portion of a first period of the divided clock and a second capacitor is charged during a first portion of a next period of the divided clock signal with a second current corresponding to a second digital quantization error. The method further includes charging the first capacitor with a third current having a fixed value during the first period of the divided clock signal and charging the second capacitor with a fourth current having the fixed value during the next period of the divided clock signal. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage. An adjusted divided clock signal is supplied including the first and the next pulse respectively having delays linearly proportional to the first and second digital quantization errors.

DETAILED DESCRIPTION

FIG. 1illustrates an exemplary system100. The system includes a MEMS oscillator101that supplies a reference clock signal102. A fractional-N divider103receives the MEMS clock signal102and divides the MEMS clock signal and supplies the divided signal104to a digital-to-time converter (DTC)107for phase interpolation to adjust the output of the divider103. A delta sigma modulator109controls the fractional-N divider and generates an integer portion106, which is used as a divide value by the divider103. The delta sigma modulator109receives a divide ratio110. Because the MEMS oscillator may be sensitive to temperature variations, a temperature sensor117and compensation circuit111may be used to adjust the divide ratio110. The digital divide ratio may be stored in memory115associated with compensation circuit111. The integer portion generated by the delta sigma modulator109is supplied to the fractional-N divider103as divide control signal106in a stream of integers to approximate the actual divide ratio, which is typically a non-integer number. The digital quantization error118, corresponding to the fractional portion of the divide ratio, is supplied to the digitally controlled DTC107. The jitter introduced by the fractional-N divider103is canceled by DTC107based on the digital quantization error supplied by the delta sigma modulator109as an N bit quantity on118. In addition, errors associated with the MEMS oscillator may be reduced using the temperature compensation circuit111. The DTC107reduces the quantization errors in the output of the fractional-N divider103.

FIG. 2shows additional details of one embodiment of a first order delta sigma modulator109that may be used in the system ofFIG. 1. In an embodiment, the integer portion supplied to the fractional-N divider varies between 2 and 3.

Referring toFIGS. 3A to 3Daspects of the DTC107are illustrated. The illustrated embodiments utilize time interleaving. When an edge of the divided clock104arrives at the digital-to-time converter107the digital-to-time converter generates a delayed edge linearly proportional to the N-bit input code (the digital quantization error) sampled by the arriving edge of the divided clock104. Referring toFIG. 3A, the digital-to-time converter107generates the delayed edge that is linear proportional to the digital quantization error by integrating a current onto a capacitor in two phases. In phase 1 (PH1 A and PH1 B), which lasts for one period of the input clock (seeFIG. 4), the digital-to-time converter integrates a variable current supplied from the quantization error digital to analog converter (DAC)301equal to res[N−1:0]/2N×Iref, where res[N−1:0] is the digital quantization error or residue supplied on node118(seeFIG. 1). The current from the residue current DAC301is supplied to capacitor A303during the first phase (PH1 A) through switch310. The fixed current DAC305supplies a fixed current to capacitor A303through switch310during the second phase (PH2 A) as shown inFIG. 3B. The current from the fixed DAC305is equal to Iref or the full scale of the current from the residue DAC301. Thus, residue DAC301is a variable current source and DAC305is a fixed current source. When the voltage on the capacitor A303reaches a reference or trigger voltage, the delayed edge is generated. Embodiments described herein require no duty cycle calibration, and shorten the input-output absolute delay, thereby allowing for lower divide ratios (and thus the reference oscillator can run at a lower frequency relative to the desired frequency, saving power).

As shown inFIGS. 3C and 3D, in addition to charging capacitor A303, the digital-to-time converter interleaves charging of capacitor A303and capacitor B307. In phase 1 (PH1 B), capacitor B is coupled to the residue DAC301through switch312and in phase 2 (PH2 B), the capacitor B307is coupled to the fixed DAC305through switch312.

FIG. 4illustrates an exemplary timing diagram associated with the operation of the circuits shown inFIGS. 3A to 3D.FIG. 4shows the MEMS oscillator clock102as MEMSCLK, and the output of the divider103as MEMSCLK/2. Note that in the embodiment ofFIG. 2, the divided value varies between MEMSCLK/2 and MEMSCLK/3. As MEMSCLK/3 is slower, the MEMSCLK/2 is the fastest the digital-to-time converter has to operate and is shown in the illustrated timing diagram. Thus, the period of the divided clock from divider103may be longer than shown inFIG. 4.

During the period401of the MEMSCLK/2 clock, in phase 1 (PH1 A) the residue DAC301charges capacitor A. Because the logical value supplied to the residue DAC is a minimum (shown as 0 in res[6:0]), no charging takes place. In PH2 A of period401, corresponding toFIG. 3B, the fixed DAC305charges capacitor A. In the next period403of the divided clock signal MEMSCLK/2, the next phase 1 (PH1 B), the residue DAC301charges capacitor B. The digital value supplied to the residue DAC is 63, approximately mid-scale. Here the phase 1 and phase 2 charging cycles are interleaved between two DACs and two capacitors, thus PH1 A and PH2 A are the two charging phases for capacitor A and PH1 B and PH2 B are the two charging phases for capacitor B. Because the fixed DAC charges the capacitor A and the residue DAC charges capacitor B, both capacitor A and capacitor B can be charged during PH1B of the clock period403as illustrated. When capacitor A reaches the trigger (or threshold) voltage at402, the digital-to-time converter107generates a pulse407in the period403of the divided clock signal MEMSCLK/2 with the leading edge of the pulse being the delayed edge of MEMSCLK/2 from MEMSCLK/2 period401. Responsive to generation of the pulse407the switch312couples capacitor A to the ground node314a shown inFIG. 3Cto discharge capacitor A. That readies capacitor A for the next charging cycle. In an embodiment, the divided clock frequency is one half or one third the frequency of the input clock and each phase 1 (PH1 A and PH1 B) lasts for one half or one third of the divided clock. Each phase 2 (PH2 A and PH2 B) lasts for one or two periods of the input clock (one half or two thirds of the divided clock period).

At the falling edge of MEMSCLK/2 in period403, the switch312switches capacitor307to the fixed DAC305, which charges capacitor B until capacitor B reaches the trigger voltage at409, resulting in pulse411. The pulse411results in capacitor B being discharged to ground by coupling the capacitor B to the ground node314as shown inFIG. 3A. That readies capacitor B for the next charging cycle.

In the period405PH1 A, the switch310connects capacitor A to residue DAC301. Because the digital value110supplied to the residue DAC is close to a maximum of127, in PH1 A capacitor A charges almost as fast as in PH2 A. At417, midpoint of the clock period405, the switch310switches charging of capacitor A to the fixed DAC305. Capacitor A charges to the trigger voltage at417resulting in pulse419.

Referring toFIG. 5, an embodiment of the digital-to-time converter107includes comparators501and503to compare the voltage on the capacitors to a reference voltage (the trigger voltage). When the voltages on the respective capacitors reach the trigger voltage, the comparators supply the signals EDGE A and EDGE B used to indicate the leading edge of pulses by the pulse generation logic507that supplies the output108. The divided clock signal104(seeFIG. 1) and EDGE A and EDGE B are supplied to switch control logic to control the switches310and312in accordance with the timing diagram ofFIG. 4.

Referring toFIG. 6, another embodiment uses single comparator601to compare the voltages on capacitor A and capacitor B to the threshold voltage (VREF). A switch603selects the appropriate capacitor to connect based on a control signal (not shown) from switch control logic605. The switch603switches from capacitor A to capacitor B after capacitor A reaches the threshold voltage and vice versa. Switch control logic605also controls switches310and312(seeFIG. 3) in accordance with the timing diagram ofFIG. 4. Using the single comparator601ensures that the comparator offset is identical for both interleaved measurements, and therefore the comparator offset does not contribute to interleaving jitter. The rising edges of the comparator output are supplied to the control logic605to help prepare the capacitors for the next cycle. In addition, the rising edges are supplied to pulse stretcher607, which, in an embodiment, ensures that the duty cycle of the output clock signal is within predetermined limits, .e.g., 45-55%. Other pulse generation approaches may of course be utilized. Note that in the embodiments illustrated inFIGS. 5 and 6the control logic505and605receives the divided clock signal104. In the particular embodiments illustrated, the divided clock has a high portion with a pulse width equal to a MEMS clock period and has a low portion varying between one and two MEMS periods. Using the divided clock allows the control logic to be run at the lower clock frequency of the divided clock compared to the MEMS clock frequency, which saves power.

The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. Other variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.