Semiconductor device, method of manufacturing semiconductor device and system of processing substrate

Disclosed is a semiconductor device that comprises a gate insulating film formed on a semiconductor substrate; a first conductive metal-containing film formed on the gate insulating film; a second conductive metal-containing film, formed on the first metal-containing film, to which aluminum is added; and a silicon film formed on the second metal-containing film.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC 119 from Japanese Patent Application No. 2011-91248 filed on Apr. 15, 2011 and Japanese Patent Application No. 2012-43872 filed on Feb. 29, 2012, the disclosures of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

Related Art

The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device and a system of processing a substrate, and more particularly to a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a method of manufacturing the same and a system of processing a substrate.

The reduction in a thickness (EOT (Effective Oxide Thickness) scaling) of a gate insulating film has been performed in accordance with a high integration and a high performance of a MOSFET. Hitherto, a SiO2film has been used as a gate insulating film, but the reduction in the gate insulating film remarkably increases in a gate leakage current. Consequently, in order to reduce the gate leakage current, an insulating film (High-k insulating film) having a higher dielectric constant than that of the SiO2film is currently beginning to be applied to the gate insulating film. Among other things, an HfO2film is considered promising. On the other hand, a polycrystalline silicon (Poly-Si) has been hitherto used as a gate electrode material, but use of a polycrystalline silicon electrode causes the formation of a depletion layer, thereby increasing the effective thickness of the gate insulating film by the amount the depletion layer is formed, which results in running counter to the reduction in the thickness of the gate insulating film. Consequently, metal materials in which a depletion layer is not generated are being examined for use for the gate electrode.

In recent years, in a MOSFET stack structure in which such a metal gate electrode and a High-k gate insulating film are used, using a gate electrode having a MIPS (Metal Inserted Poly Silicon) structure in which the metal gate electrode is inserted between a gate insulating film and a polycrystalline silicon gate electrode, a gate first process has attracted attention in which activation annealing of source/drain regions is performed after the formation of the gate electrode (see “A Highly Manufacturable MIPS (Metal Inserted Poly-Si Stack) Technology with Novel Threshold Voltage Control” 2005 Symposium on VLSI Technology Digest of Technical Papers pp. 232-233).

However, in the MIPS structure, there has been a problem that Si in polycrystalline silicon passes through a metal film during activation annealing of the source/drain regions and reaches the interface between the metal electrode and the High-k gate insulating film, causing a phenomenon called Fermi-level pinning, and thus a threshold voltage rises (flat band voltage drops).

SUMMARY OF THE INVENTION

A main object of the present invention is to provide a semiconductor device which is capable of preventing or suppressing a rise in a threshold voltage, and preventing or suppressing a drop in flat band voltage, a method of manufacturing such a semiconductor device, and a system of processing a substrate suitably used in the manufacturing of such a semiconductor device.

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a gate insulating film formed on a semiconductor substrate; a first conductive metal-containing film formed on the gate insulating film; a second conductive metal-containing film, formed on the first metal-containing film, to which aluminum is added; and a silicon film formed on the second metal-containing film.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate insulating film on a semiconductor substrate; forming a first conductive metal-containing film on the gate insulating film; forming a second conductive metal-containing film to which aluminum is added onto the first metal-containing film; and forming a silicon film on the second metal-containing film.

According to a second aspect of the present invention, there is provided a system of processing a substrate, comprising: a first processing unit that forms a gate insulating film on a semiconductor substrate; a second processing unit that forms a first conductive metal-containing film on the gate insulating film; a third processing unit that forms a second conductive metal-containing film to which aluminum is added, on the first metal-containing film; and a fourth processing unit that forms a silicon film on the second metal-containing film.

DETAILED DESCRIPTION

Referring toFIG. 1, a MOSFET100as a semiconductor device according to a preferred embodiment of the present invention includes a silicon substrate10which is a semiconductor substrate, a gate insulating film30provided on one principal surface11of the silicon substrate10, a gate electrode40provided on the gate insulating film30, and a source region21and a drain region22provided in the one principal surface11of the silicon substrate10and located on both sides of the gate electrode40.

The gate insulating film30includes a SiO2film31provided on the one principal surface11of the silicon substrate10and a HfO2film32, which is a high dielectric constant (High-k) insulating film, provided on the SiO2film31. A gate leakage current is reduced by using the HfO2film32which is a high dielectric constant insulating film.

The gate electrode40includes a TiN film41provided on the HfO2film32of the gate insulating film30, a TiAlN film43provided on the TiN film41, and a polycrystalline silicon film45doped with P (P doped poly-Si film) provided on the TiAlN film43. Since the TiN film41which is a metal film is used on the HfO2film32, a depletion layer is not generated, and thus the effective thickness of a gate insulating film is prevented from increasing. In addition, the TiAlN film43is provided between the polycrystalline silicon film45and the TiN film41, and thus when activation annealing of the source region21and the drain region22is performed after the formation of the gate electrode40, it is possible to prevent Si in the polycrystalline silicon film45from being diffused into the TiN film41which is a metal film. As a result, it is possible to prevent Si in the polycrystalline silicon film45from reaching the interface between the TiN film41and the HfO2film32which is a high dielectric constant gate insulating film by passing through the TiN film41, to prevent or suppress a rise in a threshold voltage, and to prevent or suppress a drop in flat band voltage.

Next, a method of manufacturing a MOSFET according to a preferred embodiment of the invention will be described with reference toFIG. 2.

First, the silicon substrate10is treated using, for example, an aqueous HF solution of 1%, and a sacrificial oxide film on the one principal surface11of the silicon substrate10is removed (step S101).

Next, the silicon oxide film (SiO2film)31used as a silicon-based insulating film is formed on the one principal surface11of the silicon substrate10by thermal oxidation (step S102). The SiO2film31is formed as an interface layer at the interface between the silicon substrate10and the HfO2film32which is a high dielectric constant insulating film formed thereafter. The SiO2film31constitutes a portion of the gate insulating film30.

Specifically, for example, using an oxidation furnace, the silicon substrate10is accommodated in a processing chamber of the oxidation furnace, and an oxidizing gas such as an O2gas is supplied into the processing chamber, whereby the SiO2film31is formed as an interface layer on the one principal surface11of the silicon substrate10by thermal oxidation (dry oxidation). The processing conditions are, for example, as follows.

Temperature of the silicon substrate10: 850 to 1,000° C.

Pressure in the processing chamber: 1 to 1,000 Pa

Thickness of the SiO2film31: 0.4 to 1.5 nm

Meanwhile, in place of the dry oxidation, the SiO2film31may be formed using wet oxidation, decompression oxidation, plasma oxidation, or the like.

Next, the hafnium oxide film (HfO2film)32is deposited on the SiO2film31as a high dielectric constant insulating film (High-k film) (step S103). The HfO2film32is formed as the gate insulating film30.

Specifically, for example, using an ALD (Atomic layer Deposition) furnace, the silicon substrate10after the formation of the SiO2film31is accommodated in a processing chamber of the ALD furnace, and the HfO2film32is formed as a gate insulating film on the SiO2film31by an alternate supply of a TDMAH gas and an O3gas into this processing chamber (one cycle of TDMAH gas supply→N2purge→O3gas supply→N2purge is repeated a predetermined number of times). The processing conditions are, for example, as follows.

Temperature of the silicon substrate10: 100 to 400° C.

Pressure in the processing chamber: 1 to 2000 Pa

Thickness of the HfO2film32: 0.9 to 4 nm

As sources containing Hf, organic sources such as tetrakis(ethyl-methyl-amino)hafnium (Hf[N(C2H5)(CH3)]4, abbrev.: TEMAH) and tetrakis(diethylamino)hafnium (Hf[N(C2H5)2]4, abbrev.: TDEAH), or inorganic sources such as hafnium tetrachloride (HfCl4) can be used in place of tetrakis(dimethylamino)hafnium (Hf[N(CH3)2]4, abbrev.: TDMAH). As oxidizing agents, an oxidizing gas (oxygen-containing gas) such as an H2O gas can be used in place of an O3gas. As purge gases (inert gases), rare gases such as Ar, He, Ne, and Xe can be used in place of a N2gas. Meanwhile, when liquid sources, such as TDMAH, which are in a liquid state under ordinary temperature and ordinary pressure are used, the liquid sources are vaporized by a vaporization system such as a vaporizer and a bubbler, and are supplied as a source gas.

After the HfO2film32is deposited, PDA (Post Deposition Annealing) is performed (step S104). Specifically, for example, using a heat-treating furnace (for example, RTP (Rapid Thermal Process) apparatus), the silicon substrate10after the formation of the HfO2film32is accommodated in a processing chamber of the RTP device, and annealing is performed by supplying a N2gas into this processing chamber. The PDA is performed for the purpose of removal of impurities in the HfO2film32, and densification or crystallization of the HfO2film32. The processing conditions are, for example, as follows.

Temperature of the silicon substrate10: 400 to 800° C.

Pressure in the processing chamber: 1 to 1,000 Pa

Next, the titanium nitride film (TiN film)41is formed on the HfO2film32after the PDA as a first metal film, that is, a first conductive metal-containing film (step S105). The TiN film41constitutes a portion of the gate electrode40.

Specifically, for example, using the ALD furnace, the silicon substrate10after the PDA is accommodated in the processing chamber of the ALD furnace, and the TiN film41is formed on the HfO2film32after the PDA by an alternate supply of a TiCl4gas and an NH3gas into this processing chamber (one cycle of TiCl4gas supply→N2purge→NH3gas supply→N2purge is repeated a predetermined number of times). The processing conditions are, for example, as follows.

Temperature of the silicon substrate10: 300 to 450° C.

Pressure in the processing chamber: 1 to 10,000 Pa

Thickness of the TiN film41: 5 to 20 nm

As sources containing Ti, organic sources such as tetrakis(ethyl-methyl-amino)titanium (Ti[N(C2H5)(CH3)]4, abbrev.: TEMAT), tetrakis(dimethylamino)titanium (Ti[N(CH3)2]4, abbrev.: TDMAT), and tetrakis(diethylamino)titanium (Ti[N(C2H5)2]4, abbrev.: TDEAT) can be used in place of titanium tetrachloride (TiCl4) which is an inorganic source. As nitriding agents, nitriding gases (nitrogen-containing gases) such as diazine (N2H2) gas, a hydrazine (N2H4) gas, and an N3H8gas can be used in place of an ammonia (NH3) gas. As purge gases (inert gases), rare gases such as Ar, He, Ne, and Xe can be used in place of a N2gas. Meanwhile, when liquid sources, such as TiCl4, which are in a liquid state under ordinary temperature and ordinary pressure are used, the liquid sources are vaporized by a vaporization system such as a vaporizer and a bubbler, and are supplied as a source gas.

Next, the titanium aluminum nitride film (TiAlN film)43is formed on the TiN film41as a second metal film, that is, a second conductive metal-containing film (step S106). The TiAlN film43is a conductive metal-containing film obtained by adding aluminum (Al) to the same material as the TiN film41and constituted of the same material as the TiN film41to which aluminum is added, and functions as a diffusion barrier film for preventing silicon (Si) from being diffused from the polycrystalline silicon film45formed thereafter to the interface between the TiN film41and the HfO2film32, that is, a Si diffusion block layer. It is possible to prevent Si in the polycrystalline silicon film45from reaching the interface between the TiN film41and the HfO2film32by passing through the TiN film41, using this TiAlN film43. As shown inFIG. 1, the TiAlN film43is formed at the interface between the polycrystalline silicon film45and the TiN film41.

The TiAlN film43constitutes a portion of the gate electrode40together with the TiN film41. Meanwhile, the TiN film41and the TiAlN film43may be separately formed in different film-forming apparatuses, that is, different processing chambers. However, since both films can be formed under the similar conditions, it is preferable that the both films are continuously formed in-situ in the same processing chamber.

Specifically, for example, using the ALD furnace, the silicon substrate10after the formation of the TiN film41is accommodated in the processing chamber of the ALD furnace, and the TiAlN film43in which TiN and AlN are alternately laminated is formed on the TiN film41by an alternate supply of a TiCl4gas, a TMA gas and an NH3gas into this processing chamber (one cycle of TiCl4gas supply→N2purge→NH3gas supply→N2purge is performed a predetermined number of times (m times) to form TiN and then, one cycle of TMA gas supply→N2purge→NH3gas supply→N2purge is performed one time to form AlN, and one cycle of the formation of TiN and the formation of AlN is performed a predetermined number of times (n times)). Meanwhile, the TiN film41and the TiAlN film43are continuously formed in-situ within the same processing chamber. The processing conditions are, for example as follows.

Temperature of the silicon substrate10: 300 to 450° C.

Pressure in the processing chamber: 1 to 10,000 Pa

TMA gas supply flow rate: 10 to 10,000 sccm

When the thickness of the TiAlN film43is reduced to less than 3 nm, a block effect of the Si diffusion deteriorates, and thus the Si diffusion may not be capable of being sufficiently suppressed. When the thickness of the TiAlN film43is set to be equal to or more than 3 nm, the block effect of the sufficient Si diffusion is obtained, and thus the Si diffusion is capable of being sufficiently suppressed. When the thickness of the TiAlN film43is set to be equal to or more than 5 nm, the Si diffusion is capable of being more sufficiently suppressed. On the other hand, when the thickness of the TiAlN film43is set to be more than 20 nm, because the resistivity of TiAlN is larger than the resistivity of TiN, the resistivity in the entirety of the gate electrode40may rise more than necessary. This can be prevented by setting the thickness of the TiAlN film43to be equal to or less than 20 nm. Particularly, the thickness of the TiAlN film43is set to be equal to or less than 10 nm, whereby it is possible to further suppress a rise in the resistivity in the entirety of the gate electrode40, and to set the resistivity to a more appropriate value. Consequently, it is preferable that the thickness of the TiAlN film43is set to preferably 3 to 20 nm, and more preferably 5 to 10 nm. In addition, when the Al concentration of the TiAlN film43is set to be less than 10%, the Al concentration becomes excessively low and the block effect of the Si diffusion deteriorates, and thus the Si diffusion may not be capable of being sufficiently suppressed. When the Al concentration of the TiAlN film43is equal to be equal to or more than 10%, the block effect of the sufficient Si diffusion is obtained, and thus the Si diffusion is capable of being sufficiently suppressed. On the other hand, when the Al concentration of the TiAlN film43is set to be more than 20%, the insulation properties of the TiAlN film43are strengthened and the resistivity increases, and thus the resistivity in the entirety of the gate electrode40may increase more than necessary. This can be prevented by setting the Al concentration of the TiAlN film43to be equal to or less than 20%. Consequently, it is preferable that the Al concentration of the TiAlN film43is set to preferably 10 to 20%.

Meanwhile, as sources containing Ti, nitriding agents, and purge gases (inert gases), it is possible to use the same things as those in the deposition step of the TiN film41(step S105). As sources containing Al, inorganic sources such as trichloroaluminum (AlCl3) can be used in place of trimethylaluminum (Al(CH3)3, abbrev.: TMA) which is an organic source. Meanwhile, when liquid sources, such as TMA, which are in a liquid state under ordinary temperature and ordinary pressure are used, the liquid sources are vaporized by a vaporization system such as a vaporizer and a bubbler, and are supplied as a source gas.

Meanwhile, as shown inFIG. 3, the TiAlN film43may be formed in the TiN film41, that is, between the upper TiN film41and the lower TiN film41. However, in this case, as shown inFIG. 3, the TiAlN film43is preferably separated at a distance of equal to or more than 2 nm from the HfO2film32. When the distance between the TiAlN film43and the HfO2film32is set to be less than 2 nm, for example, 1 nm, a work function of the TiAlN film43may affect the Vfb (flat band voltage). When the TiAlN film43is separated at a distance of equal to or more than 2 nm from the HfO2film32, the influence thereof is eliminated.

Next, the polycrystalline silicon film45, that is, the polysilicon film (poly-Si film)45is formed on the TiAlN film43(step S107). The poly-Si film45is doped with phosphorus (P) or boron (B) as an impurity (dopant) in an ion implantation step described later, and the poly-Si film45becomes a phosphorus doped polycrystalline silicon film (P doped poly-Si film) or a boron doped polycrystalline silicon film (B doped poly-Si film). In the present embodiment, a phosphorus doped polycrystalline silicon film (P doped poly-Si film) is formed. The poly-Si film45constitutes a portion of the gate electrode40together with the TiAlN film43and the TiN film41.

Specifically, for example, using a CVD furnace, the silicon substrate10after the formation of the TiAlN film43is accommodated in a processing chamber of the CVD furnace, and the poly-Si film45is formed on the TiAlN film43by a continuous supply of a monosilane (SiH4) gas into this processing chamber. As silicon source gases, silane-based gases such as a disilane (Si2H6) gas and a dichlorosilane (SiH2Cl2) gas may be used in place of a SiH4gas. At this time, an inert gas such as a N2gas may be simultaneously supplied as a dilution gas. The processing conditions are, for example as follows.

Temperature of the silicon substrate10: 600 to 700° C.

Pressure in the processing chamber: 10 to 48,000 Pa

Thickness of the poly-Si film45: 50 to 200 nm

Thereafter, using a resist (not shown) selectively formed on the gate electrode40as a mask, patterning of the gate electrode40using a photolithography technique and pattern etching thereof using a dry etching technique are performed (step S108). Thereafter, the resist (not shown) is removed (step S109). In this manner, after the gate electrode40is processed, the gate insulating film30is also simultaneously processed, and the one principal surface11of the silicon substrate10is exposed. Meanwhile, the processing of the gate insulating film30may be separately performed by wet etching.

Next, a SiO2film (not shown) is formed on the poly-Si film45(step S110). Specifically, for example, using the CVD furnace, the silicon substrate10after the patterning, the etching and the resist removal is accommodated in the processing chamber of the CVD furnace, and the SiO2film is formed on the poly-Si film45by supplying a TEOS gas into this processing chamber. The SiO2film is formed as a cap film for preventing outward diffusion of phosphorus (P) implanted into the poly-Si film45from the poly-Si film45in the next ion implantation step. In addition, the SiO2film is also formed on the one principal surface11of the silicon substrate10in which the source region21and the drain region22are formed, and also functions as a channeling preventing film or the like when the ion implantation into the source region21and the drain region22is performed. The thickness of the SiO2film is set to, for example, 5 to 20 nm, depending on the thickness of the poly-Si film45and the implantation energy in the ion implantation step.

Next, an impurity (dopant) is implanted into the source region21, the drain region22or the poly-Si film45through the SiO2film by an ion implantation method in an ion implantation apparatus (step S111). In the present embodiment, phosphorus (P) is implanted into the poly-Si film45. Thereby, the poly-Si film45becomes a phosphorus doped polycrystalline silicon film (P doped poly-Si film). In addition, phosphorus (P) or boron (B) is implanted into the source region21or the drain region22. For example, when phosphorus is implanted, a solid source of phosphorus is used. The ion implantation is performed multiple times depending on the impurity concentration distribution or the like of the source region21and the drain region22and the impurity concentration or the like in the poly-Si film45. The injection energy at the time of the ion implantation of phosphorus is set to, for example, 30 keV. Meanwhile, in the step of forming the polycrystalline silicon film (poly-Si film)45(step S107), the P doped poly-Si film45can also be formed in the CVD furnace, using a SiH4gas and PH3.

Next, activation annealing of the source region21, the drain region22and the P doped poly-Si film45is performed (step S112). Specifically, for example, using a heat-treating furnace (annealing apparatus), the silicon substrate10after the ion implantation is accommodated in a processing chamber of the annealing apparatus, and activation annealing is performed at a temperature of 1,000° C. by supplying a N2gas into this processing chamber. The processing conditions are, for example as follows.

Temperature of the silicon substrate10: range of 950 to 1050° C., for example, 1,000° C.

Pressure in the processing chamber: 1 to 1,000 Pa (meanwhile, since heating is a purpose, the pressure may be atmospheric pressure)

Meanwhile, in the embodiment, since the TiAlN film43is formed between the polycrystalline silicon film45and the TiN film41, at the time of the activation annealing, Si in the polycrystalline silicon film45can be prevented from reaching the interface between the TiN film41and the HfO2film32by passing through the TiN film41. That is, the TiAlN film43in the present embodiment functions as a Si diffusion block layer (Si diffusion barrier layer) for blocking the Si diffusion.

Thereafter, an FGA (Forming Gas Annealing) process such as hydrogen gas annealing is performed at a temperature of 400° C. for 10 minutes (step S113). In this manner, a MOS structure having a MIPS structure is formed.

Next, another preferred embodiment of the present invention will be described with reference toFIG. 11. In the MOSFET100according to the preferred one embodiment described above, the gate insulating film30includes the SiO2film31provided on the one principal surface11of the silicon substrate10and the HfO2film32which is a high dielectric constant insulating film provided on the SiO2film31. However, in a MOSFET102according to the another preferred embodiment of the present invention, the gate insulating film30includes the HfO2film32only which is a high dielectric constant insulating film provided on the one principal surface11of the silicon substrate10, and does not include the SiO2film31, which is a point where the MOSFET102is different from the MOSFET100of the one embodiment, but other points are the same as each other.

Even in the present another embodiment, a gate leakage current is reduced by using the HfO2film32which is a high dielectric constant insulating film. In addition, the gate electrode40includes a TiN film41provided on the HfO2film32of the gate insulating film30, a TiAlN film43provided on the TiN film41, and a polycrystalline silicon film45doped with P provided on the TiAlN film43. Since the TiN film41which is a metal film is used on the HfO2film32, a depletion layer is not generated, and thus the effective thickness of a gate insulating film is prevented from increasing. In addition, the TiAlN film43is provided between the polycrystalline silicon film45and the TiN film41, and thus when activation annealing of the source region21and the drain region22is performed after the formation of the gate electrode40, it is possible to prevent Si in the polycrystalline silicon film45from being diffused into the TiN film41which is a metal film. As a result, it is possible to prevent Si in the polycrystalline silicon film45from reaching the interface between the TiN film41and the HfO2film32which is a high dielectric constant gate insulating film by passing through the TiN film41, to prevent or suppress a rise in a threshold voltage, and to prevent or suppress a drop in flat band voltage.

In the above-mentioned preferred embodiments of the present invention, the SiO2film is used as a silicon-based insulating film serving as an interface layer between the silicon substrate and the HfO2film which is a high dielectric constant insulating film, but a silicon oxynitride film (SiON film) may be used in place of the SiO2film. In addition, the HfO2film is used as a high dielectric constant gate insulating film, but a zirconium oxide film (ZrO2film), a titanium oxide film (TiO2film), a niobium oxide film (Nb2O5film), a tantalum oxide film (Ta2O5film), a hafnium silicate film (HfSiOxfilm), a zirconium silicate film (ZrSiOxfilm), a hafnium aluminate film (HfAlOxfilm), a zirconium aluminate film (ZrAlOxfilm), or a film in which these films are combined or mixed may be used in place of the HfO2film.

As metal-containing films on the high dielectric constant gate insulating film constituting a portion of the gate electrode, a hafnium nitride film (HfN film), a zirconium nitride film (ZrN), a tantalum nitride film (TaN film), a tungsten film (W film), a tungsten nitride film (WN film) or the like may be used in place of the TiN film.

In addition, as metal-containing films which are used as a Si diffusion barrier film and constitute a portion of the gate electrode, metal films, containing Al and at least one of nitrogen and carbon, such as a TaAlN film, a TaCAlN film, a TiCAlN film, a TaCAl film, a TiCAl film, a HfAlN film, and a ZrAlN film, or films obtained by adding Al to metal films such as a W film, a Ta film, and a Ti film can be used in place of the TiAlN film.

Meanwhile, in the specification, the term “metal film” means a film constituted by conductive substances containing metal atoms, that is, a conductive metal-containing film, and this film also includes a conductive metal nitride film, a conductive metal oxide film, a conductive metal oxynitride film, a conductive metal carbide film (metal carbide film), a conductive metal carbon nitride film, a conductive metal composite film, a conductive metal alloy film, and a conductive metal silicide film, in place of a conductive elemental metal film constituted by an elemental metal. Meanwhile, the TiN film is a conductive metal nitride film, and the TiAlN film is a conductive metal composite film.

At least a portion of steps S102to S107in the above-mentioned embodiment may be continuously performed using a cluster device used as a substrate processing system.

For example, steps S102and S103may be continuously performed using the cluster device. For example, steps S102to S104may be continuously performed using the cluster device. For example, steps S102to S105may be continuously performed using the cluster device. For example, steps S102to S106may be continuously performed using the cluster device. For example, steps S102to S107may be continuously performed using the cluster device.

In addition, for example, steps S103and S104may be continuously performed using the cluster device. For example, steps S103to S105may be continuously performed using the cluster device. For example, steps S103to S106may be continuously performed using the cluster device. For example, steps S103to S107may be continuously performed using the cluster device.

In addition, for example, steps S105and S106may be continuously performed using the cluster device. For example, steps S105to S107may be continuously performed using the cluster device.

For example, when all of the steps S102to S107may be continuously performed using the cluster device, these steps can be performed using a cluster device200as shown inFIG. 12.

The cluster device200used as a substrate processing system includes processing chambers201,202,203,204, and205used as a processing unit that processes the silicon substrate10, a loading chamber208that loads the silicon substrate10into the cluster device200, an unloading chamber209that unloads the silicon substrate10from the cluster device200, cooling chambers206and207that cool the silicon substrate10, and a transfer chamber210to which the chambers201,202,203,204, and205, the loading chamber208, the unloading chamber209, and the cooling chambers206and207are attached, and which is provided with a transfer mechanism211that transfers the silicon substrate10between these chambers processing. Gate valves201a,202a,203a,204a,205a,208a, and209aare respectively provided between the transfer chamber210, and the processing chambers201,202,203,204, and205, the loading chamber208, and the unloading chamber209. The loading chamber208and the unloading chamber209are provided with gate valves208band209b, respectively, on the opposite side to the gate valves208aand209a.

The cluster device200also includes a gas supply system333that supplies a processing gas or an inert gas through a gas piping334into the processing chambers201,202,203,204, and205, and supplies the inert gas through the gas piping334into the transfer chamber210, the loading chamber208, the unloading chamber209, and the cooling chambers206and207, and an exhaust system336that exhausts the processing chambers201,202,203,204, and205, the transfer chamber210, the loading chamber208, the unloading chamber209, and the cooling chambers206and207through an exhaust pipe337.

Referring toFIGS. 12 and 13, the cluster device200further includes a gate valve control unit231that controls opening and closing operations of the gate valves201a,202a,203a,204a,205a,208a,209a,208b, and209b, a transfer mechanism control unit232that controls an operation of the transfer mechanism211, a gas supply system control unit233that controls the gas supply system333, an exhaust system control unit236that controls the exhaust system336, a temperature control unit237that controls temperatures within the processing chambers201,202,203,204, and205, a pressure control unit238that controls pressures within the processing chambers201,202,203,204, and205, the transfer chamber210, the loading chamber208, the unloading chamber209, and the cooling chambers206and207, and the like. Referring toFIG. 13, the cluster device200further includes a controller220. The controller220will be described later.

In the cluster device200, for example, the silicon substrate10is processed in the following manner.

The gate valve208bis opened, and a wafer10used as the silicon substrate10is loaded into the loading chamber (load lock chamber)208used as a loading spare chamber. After the loading, the gate valve208bis closed, and the loading chamber208is vacuum-exhausted. When the inside of the loading chamber208reaches a predetermined pressure, the gate valve208ais opened. Meanwhile, the inside of the transfer chamber210is vacuum-exhausted in advance, and is maintained to a predetermined pressure.

When the gate valve208ais opened, the wafer10is picked up by the wafer transfer mechanism211, and is extracted from the inside of the loading chamber208into the transfer chamber210. Thereafter, the gate valve208ais closed. When the gate valve208ais closed, the gate valve201ais opened, and the wafer10is loaded from the inside of the transfer chamber210into the first processing chamber201by the wafer transfer mechanism211. After the loading, the gate valve201a is closed, a step of forming the SiO2film on the wafer10is performed within the processing chamber201(step S102).

Thereafter, the gate valve201ais opened, and the wafer10after the SiO2film is formed is picked up by the wafer transfer mechanism211and is extracted from the inside of the processing chamber201into the transfer chamber210. Thereafter, the gate valve201ais closed. When the gate valve201ais closed, the gate valve202ais opened, and the wafer10after the SiO2film is formed is loaded from the inside of the transfer chamber210into the processing chamber202by the wafer transfer mechanism211. After the loading, the gate valve202ais closed, a step of forming the HfO2film on the SiO2film located on the wafer10is performed within the processing chamber202(step S103).

Thereafter, the gate valve202ais opened, and the wafer10after the HfO2film is formed is picked up by the wafer transfer mechanism211and is extracted from the inside of the processing chamber202into the transfer chamber210. Thereafter, the gate valve202ais closed. When the gate valve202ais closed, the gate valve203ais opened, and the wafer10after the HfO2film is formed is loaded from the inside of the transfer chamber210into the processing chamber203by the wafer transfer mechanism211. After the loading, the gate valve203ais closed, a PDA step is performed on the HfO2film located on the wafer10within the processing chamber203(step S104).

Thereafter, the gate valve203ais opened, and the wafer10after the PDA is picked up by the wafer transfer mechanism211and is extracted from the inside of the processing chamber203into the transfer chamber210. Thereafter, the gate valve203ais closed. When the gate valve203ais closed, the gate valve204ais opened, and the wafer10after the PDA is loaded from the inside of the transfer chamber210into the processing chamber204by the wafer transfer mechanism211. After the loading, the gate valve204ais closed, and a step of forming the TiN film on the HfO2film located on the wafer10after the PDA and a step of forming the TiAlN film thereon are continuously performed in-situ within the processing chamber204(steps S105and S106). At this time, the TiN film and the TiAlN film may be laminated and formed as shown inFIG. 1, and may be laminated and formed as shown inFIG. 3.

Thereafter, the gate valve204ais opened, and the wafer10after the formation of the TiN film and the TiAlN film is picked up by the wafer transfer mechanism211and is extracted from the inside of the processing chamber204into the transfer chamber210. Thereafter, the gate valve204ais closed. When the gate valve204ais closed, the gate valve205ais opened, and the wafer10after the formation of the TiN film and the TiAlN film is loaded from the inside of the transfer chamber210into the processing chamber205by the wafer transfer mechanism211. After the loading, the gate valve205ais closed, and a step of forming the poly-Si film on the TiAlN film (seeFIG. 1) or the TiN film (seeFIG. 3) located on the wafer10is performed within the processing chamber205(step S107).

Thereafter, the gate valve205ais opened, and the wafer10after the formation of the poly-Si film is picked up by the wafer transfer mechanism211and is extracted from the inside of the processing chamber205into the transfer chamber210. Thereafter, the gate valve205ais closed. When the gate valve205ais closed, the gate valve209ais opened, and the wafer10in which a series of steps S102to S107are completed is transferred from the inside of the transfer chamber210into the unloading chamber (load lock chamber)209used as an unloading spare chamber by the wafer transfer mechanism211. After the transfer, the gate valve209ais closed. After the inside of the unloading chamber209is restored to atmospheric pressure, the gate valve209bis opened, and the wafer10after a series of steps is extracted.

Meanwhile, the wafer10after each of the steps is carried out may be transferred into the cooling chamber206and the cooling chamber207as necessary, and may be cooled. In that case, the wafer10is stood by in the cooling chamber206or the cooling chamber207until it reaches a predetermined temperature. After the wafer is cooled until a predetermined temperature, the wafer is transferred into the processing chamber for performing the next step, or is unloaded through the unloading chamber209.

Next, another example of the cluster device in which all of the steps S102to S107are continuously performed will be described with reference toFIG. 14. The cluster device200shown inFIG. 12includes five processing chambers201,202,203,204, and205, but a cluster device300shown inFIG. 14includes six processing chambers201,202,203,204,254, and205, which is a point where the cluster device300is different from the cluster device200shown inFIG. 12, but other points are the same as each other.

In the cluster device300shown inFIG. 14, a gate valve254ais provided between the transfer chamber210and the processing chamber254. A processing gas or an inert gas is supplied from the gas supply system333through the gas piping334within the processing chamber254. The processing chamber254is exhausted through the exhaust pipe337by the exhaust system336. The opening and closing operation of the gate valve254ais controlled by the gate valve control unit231, the temperature within the processing chamber254is controlled by the temperature control unit237. The pressure within the processing chamber254is controlled by the pressure control unit238.

In the cluster device200shown inFIG. 12, a step of forming the TiN film on the HfO2film located on the wafer10after the PDA and a step of forming the TiAlN film thereon are continuously performed within the processing chamber204. However, in the cluster device300shown inFIG. 14, a step of forming the TiN film is performed within the processing chamber204, and a step of forming the TiAlN film is performed within the processing chamber254.

Meanwhile, a series of processes mentioned above are performed by controlling the operation of each of the units constituting the cluster devices200and300using the controller220.

Referring toFIG. 13, the controller220which is a control unit (control means) is configured as a computer including a CPU (Central Processing Unit)121a, a RAM (Random Access Memory)121b, a storage device121c, and an I/O port121d. The RAM121b, the storage device121c, and the I/O port121dis configured to be capable of exchanging data with the CPU121athrough an internal bus121e. An input/output device122configured as, for example, a touch panel or the like is connected to the controller220.

The storage device121cis composed of, for example, a flash memory, a HDD (Hard Disk Drive) or the like. A control program for controlling the operation of the cluster device200, a process recipe in which the procedures or conditions of a series of wafer processing mentioned above are described, and the like are stored in the storage device121cso as to be read out. Meanwhile, the process recipe functions as a program and is combined so as to cause the controller220to execute each of the procedures (each of the steps) in the series of wafer processing mentioned above to obtain predetermined results. Hereinafter, the process recipe, the control program and the like are collectively called a program simply. Meanwhile, when the term “program” is used in the specification, there is a case where only the process recipe alone is included, a case where only the control program alone is included, or a case where both of them are included. In addition, the RAM121bis configured as a memory area (work area) in which a program, data or the like read out by the CPU121ais temporarily held.

The I/O port121dis connected, through a bus240, to the gate valve control unit231, the transfer mechanism control unit232, the gas supply system control unit233, the exhaust system control unit236, the temperature control unit237, the pressure control unit238, and the like which are mentioned above.

The CPU121ais configured to read out a control program from the storage device121cand execute the read out control program, and to read out a process recipe from the storage device121cin accordance with an input or the like of an operation command from the input/output device122. The CPU121ais configured to control the gate valve control unit231, the transfer mechanism control unit232, the gas supply system control unit233, the exhaust system control unit236, the temperature control unit237, the pressure control unit238and the like so as to be follow the contents of the read out process recipe, and to control operations of a heater (not shown) and the like for heating the gate valves201a,202a,203a,204a,254a,205a,208a,209a,208b, and209b, the transfer mechanism211, the gas supply system333, the exhaust system336, and the processing chambers201,202,203,204,254, and205.

Meanwhile, the controller220is not limited to a case where it is configured as a special-purpose computer, but may be configured as a general-purpose computer. For example, an external storage device123having the above-mentioned program stored therein (for example, magnetic tapes, magnetic disks such as a flexible disk and a hard disk, optical disks such as a CD and a DVD, magneto-optical disks such as a MO, and semiconductor memories such as a USB memory and a memory card) is prepared, and the controller220according to the embodiment can be configured by installing a program to a general-purpose computer using such an external storage device123. Meanwhile, means for supplying a program to a computer is not limited to a case where the program is supplied through an external storage device123. For example, the program may be supplied without being through the external storage device123, using communication means such as the Internet and the dedicated line. Meanwhile, the storage device121cand the external storage device123are configured as a computer readable recording medium. Hereinafter, these devices are collectively called a recording medium simply. Meanwhile, when the term “recording medium” is used in the specification, there is a case where only the storage device121calone is included, a case where only the external storage device123alone is included, or a case where both of them are included.

Meanwhile, as a substrate processing system, stand-alone type devices which independently perform a process in each of the steps are respectively prepared instead of the cluster device, and a series of processes thereof may be performed. In addition, each of the embodiments, each of the application examples and the like can be used as an appropriate combination thereof.

In addition, the present invention can also be realized, for example, by changing a process recipe of an existing substrate processing system. When the process recipe is changed, the process recipe according to the present invention is installed to the existing substrate processing system through the electric telecommunication line or a recording medium having the corresponding process recipe recorded thereon, or an input/output device of the existing substrate processing system is operated, and thus the process recipe itself can also be changed to the process recipe according to the present invention.

An evaluation sample for a MOSFET according to a preferred embodiment of the present invention and an evaluation sample according to a comparative example are created, and the characteristics such as the electrical characteristics thereof are compared with each other.

First, an evaluation sample of a MOSFET200according to the preferred embodiment of the present invention will be described with reference toFIG. 4. In the MOSFET100ofFIG. 1according to the preferred embodiment of the present invention, the source region21and the drain region22exist, but in the evaluation sample200, the source region21and the drain region22do not exist, which is a point which is different from that of the MOSFET100of the preferred embodiment, but other points are the same as each other, and thus the description thereof will be omitted. In addition, a manufacturing method is the same as the manufacturing method described with reference toFIG. 2, and thus the description thereof will be omitted. However, in the manufacturing of the evaluation sample200, after the FGA step (step S113), Al deposition is performed on the backside of the silicon substrate10for the purpose of anti-oxidation or the like.

Next, an evaluation sample202according to a comparative example will be described with reference toFIG. 5. In the evaluation sample of a MOSFET ofFIG. 4according to the preferred embodiment of the present invention, the TiAlN film43exists. However, in the evaluation sample202according to the comparative example, the TiAlN film43does not exist, and a gate electrode42composed of the polycrystalline silicon film45and the TiN film41is included, which is a point which is different from that of the evaluation sample of the MOSFET according the preferred embodiment. Other points are the same as each other, and thus the description thereof will be omitted. In addition, the method of manufacturing the evaluation sample202does not have the step5106of depositing the TiAlN film43in the method of manufacturing the evaluation sample200. All the rest are the same, and thus the description thereof will be omitted (seeFIG. 6).

FIG. 7is a diagram illustrating the C-V characteristics of the evaluation sample for the MOSFET200according to the preferred embodiment of the present invention, andFIG. 8is a diagram illustrating the C-V characteristics of the evaluation sample202according to the comparative example. The horizontal axes ofFIGS. 7 and 8indicate gate voltage Vg (V) applied to the gate electrode at the time of the measurement of the C-V characteristics, and the vertical axes indicate capacitance C (g/cm2). The ● marks inFIGS. 7 and 8indicate a case where an activation annealing process at 1,000° C. is not performed (hereinafter, called “treatment at 1,000° C. is done”), and the □ marks indicate a case where an activation annealing process at 1,000° C. is performed (hereinafter, called “treatment at 1,000° C. is not done”).FIG. 9is a table indicating EOT (effective oxide thickness) and Vfb (flat band voltage) extracted from each of the C-V curves shown inFIGS. 7 and 8.

FromFIGS. 7,8, and9, in the comparative example, it is understood that compared to a case where treatment at 1,000° C. is not done, the EOT increases in a case where treatment at 1,000° C. is done, and Vfb shifts in the negative direction. This is considered that Si in the polycrystalline silicon film45is diffused into the TiN film41and reaches the interface between the TiN film41and the HfO2film32, whereby a Si—O bond occurs in the interface, and as a result, the EOT increases. In addition, it is considered that Si in the polycrystalline silicon film45reaches the interface between the TiN film41and the HfO2film32, whereby the Fermi-level pinning phenomenon occurs, and as a result, a work function lowers and thus Vfb shifts in the negative direction. Meanwhile, when Vfb shifts in the negative direction, the threshold voltage increases. On the other hand, in the structure according to the preferred embodiment of the present invention, it is understood that compared to a case where treatment at 1,000° C. is not done, the EOT decreases in a case where treatment at 1,000° C. is done, and Vfb shifts in the positive direction. When Vfb shifts in the positive direction, the threshold voltage decreases. The reduction in the EOT is considered to be due to the densification of the HfO2film32based on treatment at 1,000° C. In this manner, the TiAlN film43is provided on the TiN film41, and thus it is possible to prevent or suppress the Si diffusion from the polycrystalline silicon film45, and to thereby prevent or suppress Si in the polycrystalline silicon film45from reaching the interface between the TiN film41and the HfO2film32. Thereby, it is possible to prevent or suppress a rise in the threshold voltage, and to prevent or suppress lowering in Vfb.

Next, an evaluation sample204according to another comparative example will be described with reference toFIG. 10. In the evaluation sample204according to the comparative example, the TiAlN film43is provided on the HfO2film32without providing the TiN film41, and the polycrystalline silicon film45is provided on the TiAlN film43. In this case, the diffusion of Si from the polycrystalline silicon film45is prevented by the TiAlN film43. However, Al in the TiAlN film43is diffused into the HfO2film32and thus the EOT increases. In addition, since the work function of TiAlN is smaller than that of TiN, the gate leakage current increases. On the other hand, in the evaluation sample of the MOSFET200according to the preferred embodiment of the present invention described with reference toFIG. 4, it is not only possible to prevent the diffusion of Si from the polycrystalline silicon film45by providing the TiAlN film43, but also to prevent or suppress the diffusion of Al in the TiAlN film43into the HfO2film32by providing the TiN film41between the TiAlN film43and the HfO2film32. As a result, it is possible to prevent or suppress an increase in the EOT. Further, since the TiN film41exists on the HfO2film32which is a gate insulating film and the work function of TiN is larger than that of TiAlN, the gate leakage current decreases.

(Preferred Aspects of the Present Invention)

Hereinafter, preferred aspects of the present invention will be described.

According to one preferable aspect of the present invention, there is provided

a gate insulating film formed on a semiconductor substrate;

a first conductive metal-containing film formed on the gate insulating film;

a second conductive metal-containing film, formed on the first metal-containing film, to which aluminum is added; and

a silicon film formed on the second metal-containing film.

In the semiconductor device according to Additional Remark 1, preferably, the second metal-containing film is a conductive metal-containing film constituted of the same material as the first metal-containing film to which aluminum is added.

In the semiconductor device according to Additional Remark 1 or 2, preferably, the gate insulating film includes a high dielectric constant insulating film.

In the semiconductor device according to Additional Remark 1 or 2, preferably, the gate insulating film includes a silicon-based insulating film, and a high dielectric constant insulating film formed on the silicon-based insulating film.

In the semiconductor device according to any one of Additional Remarks 1 to 4, preferably, the second metal-containing film includes a TiAlN film.

In the semiconductor device according to any one of Additional Remarks 1 to 4, preferably, the first metal-containing film includes a TiN film, and the second metal-containing film includes a TiAlN film.

According to another preferable aspect of the present invention, there is provided

a method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a semiconductor substrate;

forming a first conductive metal-containing film on the gate insulating film;

forming a second conductive metal-containing film to which aluminum is added onto the first metal-containing film; and

forming a silicon film on the second metal-containing film.

In the method of manufacturing a semiconductor device according to Additional Remark 7, preferably, the second metal-containing film is a conductive metal-containing film constituted of the same material as the first metal-containing film to which aluminum is added.

In the method of manufacturing a semiconductor device according to Additional Remark 7 or 8, preferably, the gate insulating film includes a high dielectric constant insulating film.

In the method of manufacturing a semiconductor device according to Additional Remark 7 or 8, preferably, the gate insulating film includes a silicon-based insulating film, and a high dielectric constant insulating film formed on the silicon-based insulating film.

In the method of manufacturing a semiconductor device according to any one of Additional Remarks 7 to 10, preferably, the second metal-containing film includes a TiAlN film.

In the method of manufacturing a semiconductor device according to any one of Additional Remarks 7 to 10, preferably, the first metal-containing film includes a TiN film, and the second metal-containing film includes a TiAlN film.

The method of manufacturing a semiconductor device according to any one of Additional Remarks 7 to 12, preferably, further comprises performing activation annealing after the forming of the silicon film.

According to still another preferable aspect of the present invention, there is provided

a gate insulating film formed on a semiconductor substrate;

a conductive metal-containing film formed on the gate insulating film; and

a silicon film formed on the metal-containing film, wherein

a diffusion barrier film that prevents silicon from being diffused from the silicon film into the metal-containing film is provided between the metal-containing film and the silicon film.

According to still another preferable aspect of the present invention, there is provided

a gate insulating film formed on a semiconductor substrate;

a conductive metal-containing film formed on the gate insulating film; and

a silicon film formed on the metal-containing film, wherein

a diffusion barrier film that prevents silicon from being diffused from the silicon film into an interface between the metal-containing film and the insulating film is provided in the metal-containing film.

In the semiconductor device according to Additional Remark 14 or 15, preferably, the diffusion barrier film is provided so as to come into contact with the silicon film.

In the semiconductor device according to Additional Remark 14 or 15, preferably, the diffusion barrier film is provided at an interface between the metal-containing film and the silicon film.

In the semiconductor device according to any one of Additional Remarks 14 to 17, preferably, the gate insulating film includes a high dielectric constant insulating film.

In the semiconductor device according to any one of Additional Remarks 14 to 17, preferably, the gate insulating film includes a silicon-based insulating film, and a high dielectric constant insulating film formed on the silicon-based insulating film.

In the semiconductor device according to any one of Additional Remarks 14 to 19, preferably, the diffusion barrier film is a conductive metal-containing film constituted of the same material as the metal-containing film to which aluminum is added.

In the semiconductor device according to Additional Remark20, preferably, the diffusion barrier film includes a TiAlN film.

In the semiconductor device according to Additional Remark20, preferably, the metal-containing film includes a TiN film, and the diffusion barrier film includes a TiAlN film.

According to still another preferable aspect of the present invention, there is provided

a method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a semiconductor substrate;

forming a conductive metal-containing film on the gate insulating film; and

forming a silicon film on the metal-containing film,

wherein a diffusion barrier film that prevents silicon from being diffused from the silicon film into the metal-containing film is formed between the metal-containing film and the silicon film.

According to still another preferable aspect of the present invention, there is provided

a method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a semiconductor substrate;

forming a conductive metal-containing film on the gate insulating film; and

forming a silicon film on the metal-containing film,

wherein in the forming of the metal-containing film, a diffusion barrier film that prevents silicon from being diffused from the silicon film into an interface between the metal-containing film and the gate insulating film is formed in the metal-containing film.

In the method of manufacturing a semiconductor device according to Additional Remark 23 or 24, preferably, the diffusion barrier film is provided so as to come into contact with the silicon film.

In the method of manufacturing a semiconductor device according to Additional Remark 23 or 24, preferably, the diffusion barrier film is provided in an interface between the metal-containing film and the silicon film.

In the method of manufacturing a semiconductor device according to any one of Additional Remarks 23 to 26, preferably, the gate insulating film includes a high dielectric constant insulating film.

In the method of manufacturing a semiconductor device according to any one of Additional Remarks 23 to 26, preferably, the gate insulating film includes a silicon-based insulating film, and a high dielectric constant insulating film formed on the silicon-based insulating film.

In the method of manufacturing a semiconductor device according to any one of Additional Remarks 23 to 28, preferably, the diffusion barrier film is a conductive metal-containing film constituted of the same material as thet metal-containing film to which aluminum is added.

In the method of manufacturing a semiconductor device according to Additional Remarks 29, preferably, the diffusion barrier film includes a TiAlN film.

In the method of manufacturing a semiconductor device according to any one of Additional Remarks 23 to 29, preferably, the metal-containing film includes a TiN film, and the diffusion barrier film includes a TiAlN film.

The method of manufacturing a semiconductor device according to any one of Additional Remarks 23 to 31, preferably, further comprises performing activation annealing after the forming of the silicon film.

According to still another preferable aspect of the present invention, there is provided

a gate insulating film formed on a semiconductor substrate;

a conductive film, formed on the gate insulating film, in which a depletion layer is not generated when a voltage is applied; and

a silicon film formed on the conductive film,

wherein a diffusion barrier film that prevents silicon from being diffused from the silicon film into the conductive film is provided between the conductive film and the silicon film.

According to still another preferable aspect of the present invention, there is provided

a gate insulating film formed on a semiconductor substrate;

a conductive film, formed on the gate insulating film, in which a depletion layer is not generated when a voltage is applied; and

a silicon film formed on the conductive film,

wherein a diffusion barrier film that prevents silicon from being diffused from the silicon film into an interface between the conductive film and the insulating film is provided in the conductive film.

According to still another preferable aspect of the present invention, there is provided

a method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a semiconductor substrate;

forming a conductive film, on the gate insulating film, in which a depletion layer is not generated when a voltage is applied; and

forming a silicon film on the conductive film, wherein

a diffusion barrier film that prevents silicon from being diffused from the silicon film into the conductive film is formed between the conductive film and the silicon film.

According to still another preferable aspect of the present invention, there is provided

a method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a semiconductor substrate;

forming a conductive film, on the gate insulating film, in which a depletion layer is not generated when a voltage is applied; and

forming a silicon film on the conductive film,

wherein in the forming of the conductive film, a diffusion barrier film that prevents silicon from being diffused from the silicon film into an interface between the conductive film and the gate insulating film is formed in the conductive film.

According to still another preferable aspect of the present invention, there is provided

a high dielectric constant insulating film formed on a substrate;

a TiN film formed on the high dielectric constant insulating film;

a TiAlN film formed on the TiN film; and

a silicon film formed on the TiAlN film.

According to still another preferable aspect of the present invention, there is provided

a method of manufacturing a semiconductor device, comprising:

forming a high dielectric constant insulating film on a substrate;

forming a TiN film on the high dielectric constant insulating film;

forming a TiAlN film on the TiN film; and

forming a silicon film on the TiAlN film.

According to still another preferable aspect of the present invention, there is provided

a system of processing a substrate, comprising:

a first processing unit that forms a gate insulating film on a semiconductor substrate;

a second processing unit that forms a first conductive metal-containing film on the gate insulating film;

a third processing unit that forms a second conductive metal-containing film to which aluminum is added, on the first metal-containing film; and

a fourth processing unit that forms a silicon film on the second metal-containing film.

In the substrate processing system according to Additional Remark 39, preferably, the second processing unit and the third processing unit are the same processing unit.

According to still another preferable aspect of the present invention, there is provided

a non-transitory computer-readable medium storing a program that causes a computer to perform a process including:

forming a gate insulating film on a semiconductor substrate using a first processing unit of a substrate processing system;

forming a first conductive metal-containing film on the gate insulating film using a second processing unit of the substrate processing system;

forming a second conductive metal-containing film to which aluminum is added, on the first metal-containing film, using a third processing unit of the substrate processing system; and

forming a silicon film on the second metal-containing film using a fourth processing unit of the substrate processing system.

As stated above, although various typical embodiments of the present invention have been described, the present invention is not limited to these embodiments. Therefore, the invention is intended to be limited only by the appended claims.