System and method of testing through-silicon vias of a semiconductor die

A method includes contacting a first group of through-silicon vias (TSVs) contacts with a multi-contact probe and applying a first voltage value to each of the first group of TSV contacts via the multi-contact probe, where the first group of TSV contacts corresponds to a first group of TSVs. The method also includes determining, based on a second voltage value detected at a particular TSV of the first group of TSVs, whether the particular TSV corresponds to a TSV test result.

The present disclosure is generally related to semiconductor die testing and more specifically to testing through-silicon vias.

II. DESCRIPTION OF RELATED ART

Advances in technology have resulted in smaller and more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular telephones and internet protocol (IP) telephones, can communicate voice and data packets over wireless networks. Further, many such wireless telephones include other types of devices that are incorporated therein. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these wireless telephones can include significant computing capabilities that may be enabled by circuitry on one or more semiconductor dies. Electrical connections to a semiconductor die (e.g., a semiconductor die for a portable personal computing device) may be formed using thru-silicon vias (TSVs), such as to transfer power or signals from one die to another in a stack of dies.

Testing thru-silicon vias and electrical contacts for TSVs (e.g., micro-bumps) of a thinned semiconductor die (e.g., a semiconductor die after a thinning process, such as a grinding process, a polishing process, etc.) may be challenging. For example, TSVs commonly have small dimensions, such as a diameter less than or equal to ten micrometers and pitch (i.e., TSV pattern spacing) less than or equal to twenty micrometers. Such small dimensions impede or prevent traditional probing that involves contacting a single tester probe to a single electrical contact on a die due to the high resolution required for probe positioning and contact. Further, a thinned die, such as a thinned die that is manufactured to create a three-dimensional (3D) stacked integrated circuit (IC), may not be able to sustain the force that typical tester probes can exert during probe touchdowns (i.e., physical contacting of probes with electrical contacts on a semiconductor die).

Systems and methods of testing enable a device to detect of an open condition and/or a short condition of TSVs on a semiconductor die to determine a quality of the semiconductor die (e.g., to classify a die as a known good die (KGD)). TSVs (and bumps) of a KGD may be determined to be capable of transmitting information across multiple dies in a stack of dies.

For example, a multi-contact probe may be positioned to be in contact with one or more TSV contacts (e.g., four adjacent TSV contacts in a 2×2 arrangement) concurrently. The multi-contact probe may be configured to provide a first voltage value, such as a logical high value or a logical low value, to a first group of the one or more TSV contacts. A determination may be made, based on a second voltage value detected at a particular TSV of the first group, whether the particular TSV corresponds to a TSV test result. The TSV test result may be a TSV open condition, a TSV short condition, or a combination thereof.

In a particular embodiment, a method includes contacting a first group of TSV contacts with a multi-contact probe and applying a first voltage value to each of the first group of TSV contacts via the multi-contact probe, where the first group of TSV contacts corresponds to a first group of TSVs. The method also includes determining, based on a second voltage value detected at a particular TSV of the first group of TSVs, whether the particular TSV corresponds to a TSV test result.

In another particular embodiment, an apparatus includes a semiconductor device. The semiconductor device includes one or more TSV contacts coupled to one or more TSVs. Each TSV is coupled to a respective bi-directional buffer circuit that includes an output enable cell, an output buffer cell, and an input buffer cell. The apparatus also includes a TSV test circuit configured, after a first group of the one or more TSV contacts is contacted with a multi-contact probe and a first voltage value is applied to each of the first group of TSV contacts via the multi-contact probe, where the first group of TSV contacts corresponds to a first group of the one or more TSVs, to determine, based on a second voltage value detected at a particular TSV of the first group of TSVs via the respective bi-directional buffer circuits, whether the particular TSV corresponds to a TSV test result.

One particular advantage provided by at least one of the disclosed embodiments is an ability for a device to determine a test result of TSVs of a semiconductor die (e.g., to detect an open condition and/or a short condition), enabling enhanced determination of the quality of the semiconductor die. Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.

V. DETAILED DESCRIPTION

TSVs may be designed to extend from an active area of a semiconductor die to an electrical contact on the bottom of the semiconductor die. For example, a TSV may be formed by etching a region extending from the active area into the substrate of the semiconductor die, depositing a conductive material such as copper into the region, etching or polishing a bottom surface of the semiconductor die to reach the conductive material, and depositing the electrical contact to contact the conductive material. However, an electrical open condition may occur in a TSV where the TSV (i.e., the conductive material in the region) does not form a conductive path between the electrical contact and the active area. For example, an open condition may result from a void being formed within the TSV during a metal fill stage of TSV formation.

TSVs may be designed to be electrically isolated from each other. However, a short condition between TSVs may occur where a conductive path exists between two TSVs. For example, a short condition can be caused by misaligned micro-bumps or defective metallization during TSV formation.

An undetected open condition and/or a short condition of TSVs of a semiconductor die may interfere with transmitting information from the semiconductor die to other dies, thus rendering the semiconductor die defective.

FIG. 1is a diagram to illustrate a particular embodiment of a system100that is operable to test TSVs of a semiconductor die. The system100may include a semiconductor die102(shown in a cross sectional view), a multi-contact probe104(e.g., a membrane probe), and a TSV test circuit106. The semiconductor die102may be a thinned silicon die (e.g., a semiconductor die after a thinning process, such as a grinding process, a polishing process, etc.). The semiconductor die102may include an active area108(e.g., a top side of a semiconductor die), a thinned silicon (Si) backside110, and TSVs112,114,116,118,120, and122that extend from the active area108to the thinned Si backside110. Each TSV112,114,116,118,120, and122may be electrically coupled to a respective TSV contact124,126,128,130,132, and134at a bottom surface142of the semiconductor die102.

Each TSV contact124,126,128,130,132, and134may be a micro-bump and may have a diameter less than or equal to approximately ten micrometer (μm) and a pitch less than or equal to approximately twenty μm. The TSVs112,114,116,118,120, and122(and the TSV contacts124,126,128,130,132, and134) may be arranged according to a grid orientation (e.g., rows and columns). The pitch and/or size may be too small for conventional testing with a single probe.

The multi-contact probe104may include a probe head136and probe contacts138and140coupled to the probe head136. The multi-contact probe104(shown in a cross sectional view) may be dimensioned and positioned to be in electrical contact with a particular number of TSVs (via the TSV contacts) concurrently using the probe contacts138and140and the probe head136. For example, each of the probe contacts138may be in electrical contact with four TSVs via physical contact with a 2×2 array of TSV contacts, as illustrated with respect toFIG. 2. The multi-contact probe104may exert substantially equal force on each TSV contact of the particular number of TSV contacts that are in contact with the multi-contact probe104.

A TSV in electrical contact with the multi-contact probe104may be referred to as a “contact TSV (CTSV).” A TSV not in electrical contact with the multi-contact probe104may be referred to as a “non-contact TSV (NCTSV).” The multi-contact probe104may be configured to provide a conductive path between each of the CTSVs during open-circuit/open condition testing of the TSVs as described with reference toFIG. 3. The multi-contact probe104may also be configured to provide a common voltage (e.g., a logical high value or a logical low value) to a first group of the CTSVs during short-circuit/short condition testing of the TSVs as described with reference toFIG. 2.

The TSV test circuit106may be coupled to the semiconductor die102or integrated as part of the semiconductor die102. The TSV test circuit106may be configured to provide a voltage (e.g., a voltage corresponding to a logical value, a programmable voltage) to each TSV112,114,116,118,120, and122and to detect a voltage value (e.g., a logical value) of each TSV using respective bi-directional buffer circuits and a scan chain. Examples of the bi-directional buffer circuits and the scan chain are described in further detail with reference toFIG. 4andFIG. 5, respectively. A processor integrated into the semiconductor die102may be programmed to determine whether any CTSVs have a short condition or an open condition.

During operation, the multi-contact probe104and the TSV test circuit106may perform a short condition and/or an open condition test on the semiconductor die102to detect the presence of short and/or open conditions in the TSVs112,114,116,118,120, and122(and corresponding TSV contacts124,126,128,130,132, and134). Short condition testing may include determining whether applying a voltage at one TSV affects a voltage at another TSV. For a short condition test, the multi-contact probe104may apply a first voltage (e.g., a logical low value, a logic zero) to the CTSVs (e.g., the TSVs118and120) prior to detecting a second voltage at each CTSV. In a particular embodiment, the first voltage is a weak zero that is weakly applied at the CTSV and may be overcome by applying another voltage (corresponding to a logic one) at the CTSV via a short-circuit path to another TSV. The TSV test circuit106may apply a third voltage (e.g., a logical high value or a logic one) to NCTSVs (e.g., the TSVs116and122) that are adjacent to the CTSVs prior to detecting the second voltage at each CTSV. The TSV test circuit106may detect the second voltage at each CTSV and may compare the second voltage to the third voltage to determine whether a short condition exists in any CTSVs. The TSV test circuit106may determine that the short condition exists in a particular CTSV when the second voltage sensed from the particular CTSV and the third voltage have the same value (e.g., same logical value).

Open condition testing may include determining whether, when two TSV contacts are electrically connected, a change in voltage of one TSV causes a change in voltage of the other TSV. For an open condition test, the multi-contact probe104may apply the first voltage to the CTSVs (e.g., TSVs118and120). The TSV test circuit106may apply the third voltage to a first CTSV (e.g., TSV118) of a group of CTSVs (e.g., TSVs118and120) prior to detecting the second voltage at a second CTSV (e.g., TSV120) of the group of CTSVs. The TSV test circuit106may detect the second voltage at the second CTSV of the group of CTSVs and compare the second voltage to the third voltage to determine whether an open condition exists in the second CTSV (and a corresponding TSV contact). The TSV test circuit106may determine that the open condition exists in the second CTSV when the second voltage and the third voltage have different values.

After performing the short condition and/or the open condition test using a first placement of the multi-contact probe104, the multi-contact probe104or the semiconductor die102may move to other TSVs that have not been tested to perform the short condition and/or open condition test until all the TSVs are tested. The multi-contact probe104may move relative to the semiconductor die102by a distance corresponding to one or more rows of the TSVs in an X-direction, one or more columns of the TSVs in a Y-direction, or a combination thereof. The multi-contact probe104and the TSV test circuit106may also perform other types of tests on the semiconductor die102, such as a TSV impedance test (time required to charge a TSV) or a TSV placement test (whether each TSV is placed in the correct position on a semiconductor die).

In a particular embodiment, the multi-contact probe104is a cantilever probe. In another particular embodiment, the multi-contact probe104is a membrane probe. The TSV test circuit106may be integrated in the semiconductor die102, such as a state machine processor or other circuitry, or may be external to the semiconductor die102(e.g., integrated in a testing device of a test bed). AlthoughFIG. 1illustrates a semiconductor die including TSVs, it should be understood that the present disclosure is not limited to silicon technologies or TSVs and may apply to testing of any type of via that is coupled to a contact on a surface of a semiconductor device. Similarly, althoughFIG. 1illustrates six TSVs, six TSV contacts, and one multi-contact probe, in other embodiments, any number of TSVs, TSV contacts, and/or multi-contact probes may be present.

The system100may thus enable a device (e.g., the multi-contact probe104and/or the TSV test circuit106) to detect an open condition and/or a short condition of TSVs of a semiconductor die (e.g., the semiconductor die102), which may provide determination of the quality of the semiconductor die. The determination of the quality of semiconductor dies using TSV testing may reduce a component failure rate of devices that include the semiconductor dies.

FIG. 2is a diagram to illustrate a particular embodiment of aspects of the system100ofFIG. 1that is operable to test the short condition of the TSVs and is generally designated200. As illustrated inFIG. 2, the semiconductor die102may include a plurality of TSVs (e.g., the TSVs112,114,116,118, and120ofFIG. 1). The plurality of TSVs may include a first group of CTSVs204and a second group of NCTSVs208. The semiconductor die102may also include a scan chain206that may be connected to each TSV of the plurality of TSVs. To perform the short condition test, the multi-contact probe104may be in electrical contact with one or more groups of the plurality of the TSVs during each iteration of a testing process according to the TSV test circuit106until the plurality of TSVs are tested. The TSV test circuit106may be electrically coupled with the plurality of TSVs to apply a voltage via the scan chain206to each TSV and to read a voltage at each TSV for the short condition test.

The first group of CTSVs204may be a group of TSVs that are subjected to the short condition test. The second group of NCTSVs208may be a group of TSVs that are adjacent to the first group of CTSVs204. A voltage detected at the second group of NCTSVs208may serve as a reference point to help determine whether a short condition exists in any TSV of the first group of CTSVs204.

During operation, the multi-contact probe104may apply the first voltage value to the first group of at least four CTSVs204(e.g., a 2×2 array) concurrently. The TSV test circuit106may apply a first set of voltage values via the scan chain206to the first group of CTSVs204and to the second group of NCTSVs208. The application of the first set of voltage values may cause each CTSV of the first group of CTSVs204to have a high-impedance output value (i.e., a voltage of the TSVs is allowed to “float,” (i.e., to be influenced by external voltages)) and may cause each NCTSV of the second group of NCTSVs206to have a logical high voltage value (e.g., the third voltage value). The high-impedance output value in the first group of CTSVs204may enable the first voltage value applied by the multi-contact probe104to be overridden by a voltage of an adjacent NCTSV when a short condition exists between a CTSV and the adjacent NCTSV. The TSV test circuit106may detect the second voltage value at each CTSV of the first group of CTSVs204and compare the second voltage value to the third voltage value to determine whether the short condition is detected in any CTSV of the first group of CTSVs204. The short condition may be determined in response to the second voltage value (detected at a CTSV of the first group of CTSVs204) and the third voltage value (applied to the NCTSVs of the second group of NCTSVs208) having the same value or substantially the same value (e.g., the same logical value). After each CTSV of the first group of CTSVs204has been tested for short condition, the multi-contact probe104may move to test other TSVs until all the TSVs are tested for short condition. Alternatively, the semiconductor die102may be moved (e.g., by a support arm) so that each TSV makes contact with the multi-contact probe104for short condition testing.

FIG. 3is a diagram to illustrate a particular embodiment of aspects of the system100ofFIG. 1that is operable to test the open condition of the TSVs and is generally designated300. As illustrated inFIG. 3, the semiconductor die102may include the plurality of TSVs (e.g., the TSVs112,114,116,118, and120ofFIG. 1). The plurality of TSVs may include the first group of CTSVs204. Similar toFIG. 2, the semiconductor die102may also include the scan chain206that may be connected to each TSV of the plurality of TSVs. To perform the open condition test, the multi-contact probe104may be in electrical contact with groups of the plurality of the TSVs during each iteration of a testing process in accordance with the open condition test until the plurality of the TSVs are tested. The TSV test circuit106may be electrically coupled with the plurality of TSVs to apply a voltage via the scan chain206to each TSV and/or to read a voltage at each TSV for the open condition test.

The first group of CTSVs204may include a particular CTSV302and other TSVs304. The particular CTSV302may be a TSV subjected to the open condition test. The other TSVs304may be TSVs adjacent to the particular CTSV302within the first group of CTSVs204. The other TSVs304may serve as a reference point to help determine whether an open condition exists in the particular CTSV302.

During operation, the multi-contact probe104may apply the first voltage value to the first group of CTSVs204. The TSV test circuit106may apply a second set of voltage values via the scan chain206to the first group of CTSVs204. The application of the second set of voltage values may cause a particular CTSV302of the first group of CTSVs204to have the logical high output value (e.g., the third voltage value) and to cause each CTSV of other CTSVs304of the first group of CTSVs204to have the high-impedance output value. The TSV test circuit106may detect the second voltage value at one of the other CTSVs304and determine whether the open condition exists in the particular CTSV302. The open condition may be determined in response to the second voltage value (detected at one of the other CTSVs304) and the third voltage value (applied to the particular CTSV302) having different values. When the second voltage value and the third voltage value have the same value, an electrical path is detected from the particular CTSV302(via the particular CTSV302's contact, across the multi-contact probe104) to the other TSVs304(and to the other TSVs304's contacts) or vice versa. The electrical path may enable current to travel from the particular CTSV302to the other TSVs304so that the other TSVs304may have the same voltage value or substantially the same voltage value (the third voltage value) as the voltage value (the second voltage value) at the particular CTSV302.

After each CTSV of the first group of CTSVs204has been tested for open condition, the multi-contact probe104may move to test other TSVs until all the TSVs are tested for open condition. Alternatively, the semiconductor die102may be moved (e.g., by a support arm) so that each TSV makes contact with the multi-contact probe104for open condition testing.

FIG. 4is a block diagram to illustrate a particular embodiment400of a bi-directional buffer circuit402configured for use during open and short testing of a TSV414. The bi-directional buffer circuit402may include an output enable cell (OEC)404, an output buffer cell (OBC)406, an input buffer cell (IBC)408, an output buffer410, and an input buffer412. The input buffer412may be coupled to provide a signal to the IBC408based on a voltage value at the TSV414. The output buffer410may be coupled to provide a voltage value to the TSV414based on a value at the OBC406. The output buffer410may also be responsive to a value at the OEC404(e.g., an enable signal) to selectively enter a high impedance state where the output buffer410does not drive a voltage at the TSV414to enable the voltage at the TSV414to float prior to reading a voltage at the TSV414via the input buffer412.

The bi-directional buffer circuit402may be configured to couple with other bi-directional buffer circuits to form one or more scan chains (e.g., the scan chain206ofFIG. 2). The one or more scan chains may enable providing the logical high, the logical low, or the high-impedance output value to each TSV of a semiconductor die (e.g., TSVs112-122of the semiconductor die102ofFIG. 1) and to enable reading a voltage value from each selected TSV of the semiconductor die.

During the short condition test, when the TSV414is a TSV in the first group of CTSVs204ofFIG. 2, the TSV test circuit106may populate the OEC404, the OBC406, and/or the IBC408of the bi-directional buffer circuit402with the first set of voltage values via the one or more scan chains to cause the output buffer410to have the high-impedance output value and to read, via the one or more scan chains, a voltage value of the IBC408to determine whether the TSV414has the short condition. When the TSV414is a TSV in the second group of NCTSVs208ofFIG. 2, the TSV test circuit106may populate the OEC404, the OBC406, and/or the IBC408of the bi-directional buffer circuit402to cause the output buffer410to have the logical high output value.

During the open condition test, when the TSV414is the particular CTSV302ofFIG. 3, the TSV test circuit106may populate the OEC404, the OBC406, and/or the IBC408of the bi-directional buffer circuit402with the second set of voltage values via the one or more scan chains to enable the TSV414to have the logical high output value. When the TSV414is one of the other TSVs304ofFIG. 3, the TSV test circuit106may populate the OEC404, the OBC406, and/or the IBC408of the bi-directional buffer circuit402with the second set of voltage values via the one or more scan chains to cause the output buffer410to have the high impedance output value, and the TSV test circuit106may read, via the one or more scan chains, the voltage value of the IBC408to determine whether the TSV414has the open condition. The one or more scan chains may be controlled via a chain test access module, as described in further detail with reference toFIG. 5.

FIG. 5is a diagram to illustrate a particular embodiment500of a scan chain configuration associated with the system100ofFIG. 1. The scan chain configuration (e.g., how the scan chain206may be configured) may be arranged to enable the TSV test circuit106to test each TSV of the semiconductor die102for the short condition and/or the open condition. In a particular embodiment, the scan chain configuration is arranged to enable a first set of voltage values506and a second set of voltage values508to traverse through each TSV of the semiconductor die102via the scan chain206, starting with a TSV510and ending with a TSV512(in the direction of the arrow). The TSVs510and512may be TSVs of the semiconductor die102ofFIG. 1(e.g., the TSVs112and114).

A chain test access module504may be configured to control scan operations for TSV testing. The chain test access module504may be configured to provide the first set of voltage values506and the second set of voltage values508and to receive test voltage values returned via the scan chain206. The chain test access module504may be integrated with the TSV test circuit106or may be electrically coupled to the TSV test circuit106. In a particular embodiment, the chain test access module504is a joint test access group (JTAG)-type controller.

During operation of the short condition testing, the chain test access module504and/or the TSV test circuit106may populate bi-directional buffer circuits (e.g., the bi-directional buffer circuit402ofFIG. 4) with the first set of voltage values506(e.g., corresponding to a first set of logical values) via one or more scan chains (e.g., the scan chain206) to cause a first group of TSVs (e.g., the first group of CTSVs204ofFIG. 2) to have a floating voltage and to cause a second group of TSVs (e.g., the second group of NCTSVs208) adjacent to the first group of TSVs to have the logical high voltage value. The chain test access module504and/or the TSV test circuit106may also read, via the one or more scan chains, a voltage value (e.g., corresponding to a logical value) of each input buffer cell (e.g., the IBC408) corresponding to the first group of TSVs to determine whether any TSV of the first group of TSVs corresponds to the TSV short condition.

During operation of the open condition testing, the chain test access module504and/or the TSV test circuit106may populate the bi-directional buffer circuits with the second set of voltage values508(e.g., corresponding to a second set of logical values) via the one or more scan chains to enable a particular TSV (e.g., the particular CTSV302ofFIG. 3) of the first group of TSVs to have a logical high voltage value and to enable other TSVs (e.g., the other TSVs304ofFIG. 3) of the first group of TSVs to have a floating voltage. The chain test access module504and/or the TSV test circuit106may also read, via the one or more scan chains, a voltage value (corresponding to logical value) of each input buffer cell corresponding to the other TSVs of the first group of TSVs to determine whether any of the other TSVs of the first group of TSVs corresponds to the TSV open condition. After performing the short condition and/or the open condition test on a particular group of TSVs, the semiconductor die102, the multi-contact probe104ofFIG. 1, or a combination thereof may move to couple the multi-contact probe104to another group of TSVs to perform the short condition and/or open condition test on the other group of TSVs.

A pseudocode example to illustrate a particular embodiment of a method of testing a k×k array of TSVs of a semiconductor die may include:

For each touch-down of a probe head, repeat {

Drive probes to “weak zero” from tester (i.e., apply a logical zero value (low) to CTSVs using the multi-contact probe104, where the logical zero value is weakly applied and may be overcome by the output buffer410generating a logical one output)Drive logic one (High) on all NCTSVs using a TSV scan chain(s) (i.e., load a logical one value into the OEC404and the OBC406of each NCTSV using the scan chain206, load a logical zero value into the OEC404of each CTSC)Capture responses on CTSV IBC cells (i.e., scan a value of the IBC408of each CTSV to the chain test access module504using the scan chain206)If any CTSV IBC cell value=logic one then a short failure is detected between a CTSV and a NCTSVDiagnose short condition using the position of the CTSV that captured the logic one value
2. Detect opens:For each CTSV of the (n×n) CTSVs contacted by a probe (at weak zero):Drive a logic one (high) to the CTSV from the OBC406(e.g., apply a logical one value to the particular CTSV302)Capture response on the remaining (n−1) CTSV IBCs (e.g., scan a value of the IBC408of each of the other TSVs304in the first group of CTSVs204)

If any of the (n−1) IBC values is not a logic one value then the corresponding TSV/micro-bump has a detected open defect

3. Move probe head to next position

} until all TSVs in the k×k array of TSVs have been tested

FIG. 6is a flow chart to illustrate a particular embodiment of a method600of operation at the system100ofFIG. 1. The method600may include contacting a first group of TSV contacts with a multi-contact probe and applying a first voltage value to each of the first group of TSV contacts via the multi-contact probe, where the first group of TSV contacts corresponds to a first group of TSVs, at602. For example, inFIG. 1, the multi-contact probe104may contact the TSVs112and114(via the corresponding TSV contacts124and126) and apply the first logical value to the TSVs112and114.

The method600may also include determining, based on a second voltage value detected at a particular TSV of the first group of TSVs, whether the particular TSV corresponds to a TSV test result, at604. For example, inFIG. 1, the TSV test circuit106may detect the second logical value at each CTSV and compare the second logical value to a third logical value to determine whether a short condition or an open condition exists in any TSV of the semiconductor die102.

In a particular embodiment, the method600further includes applying the third voltage value to each TSV of a second group of TSVs that are adjacent to the first group of TSVs prior to detecting the second voltage value, where the TSV short condition is determined in response to the second voltage value and the third voltage value having a same logical value. In another particular embodiment, the method600further includes applying the third voltage value to a TSV of the first group of TSVs (e.g., the particular CTSV302ofFIG. 3) prior to detecting the second voltage value at another TSV of the first group of TSVs (e.g., the other TSVs304ofFIG. 3), where the TSV open condition is determined in response to the second voltage value and the third voltage value having different logical values.

One particular advantage provided by at least one of the disclosed embodiments is an ability to detect an open condition and/or a short condition of TSVs of a semiconductor device (e.g., a thinned semiconductor die) that may cause defective operation of the defective semiconductor device.

FIG. 7is a block diagram of a particular embodiment of a communication device700that includes a semiconductor die (e.g., the semiconductor die102ofFIG. 1) in a system-on-chip (SoC) device722(or in a system-in-package (SiP) device) that includes a TSV test circuit752(e.g., the TSV test circuit106ofFIG. 1) coupled to multiple TSV contacts754. The communication device700may include a processor710(e.g., a digital signal processor) coupled to a memory732.

The memory732may be a non-transitory tangible computer-readable and/or processor-readable storage device that stores instructions756. The instructions756may be executable by the processor710to implement the functionalities of the TSV test circuit752, such as populating or selecting test data to apply a first set of voltage values, applying a second set of voltage values, etc., to a TSV scan chain to perform one or more functions or methods described herein, such as the method described with reference toFIG. 6.

FIG. 7shows that the communication device700may also include a display controller726that is coupled to the processor710and to a display728. A coder/decoder (CODEC)734can also be coupled to the processor710. A speaker736and a microphone738can be coupled to the CODEC734.FIG. 7also indicates that a wireless controller740may be coupled to the processor710, where the wireless controller740is in communication with an antenna742via a transceiver750. The wireless controller740, the transceiver750, and the antenna742may thus represent a wireless interface that enables wireless communication by the communication device700. The communication device700may include numerous wireless interfaces, where different wireless networks are configured to support different networking technologies or combinations of networking technologies. For example, the communication device700may include an IEEE 802.11ah wireless interface.

In an illustrative embodiment, the TSV test circuit752is operable to perform the functions described with reference to the TSV test circuit106ofFIGS. 1-5. The TSV contacts754are coupled to TSVs (not shown) that are coupled to the TSV test circuit752. In an illustrative embodiment, the TSV contacts754are the TSV contacts124,126,128ofFIG. 1. The TSV test circuit752may be implemented within, or as a part of, the processor710. In a particular embodiment, the TSV test circuit752is implemented as instructions executable by the processor710(e.g., the instructions756). In another particular embodiment, the TSV test circuit752is implemented as a component of the system-on-chip device722(e.g., as test circuitry).

In a particular embodiment, the processor710, the display controller726, the memory732, the CODEC734, the wireless controller740, the transceiver750, the TSV test circuit752, and the TSV contacts754are included in the system-on-chip device722. In a particular embodiment, an input device730and a power supply744are coupled to the system-on-chip device722. Moreover, in a particular embodiment, as illustrated inFIG. 7, the display728, the input device730, the speaker736, the microphone738, the antenna742, and the power supply744are external to the system-on-chip device722. However, each of the display728, the input device730, the speaker736, the microphone738, the antenna742, and the power supply744can be coupled to a component of the system-on-chip device722, such as an interface or a controller.

One or more components of the communication device700or components analogous thereto, may be integrated into a semiconductor device, such as the semiconductor die102ofFIG. 1,2,3or5. For example, the semiconductor die102ofFIG. 1may include a wireless controller, a transceiver, a processor, and a memory storing instructions executable by a processor to perform all or part of the method ofFIG. 6.

In conjunction with the described embodiments, an apparatus may include means for providing a conductive path between a multi-contact probe and one or more TSVs. For example, the means for providing the conductive path may include the TSV contacts124,126,128,130,132, and134ofFIG. 1, the TSV contacts754ofFIG. 7, one or more other devices or circuits configured to provide a conductive path, or any combination thereof. The apparatus may also include means for selectively biasing the one or more TSVs to a programmable voltage and for reading a voltage at the one or more TSVs. For example, the means for selectively biasing and for reading the voltage may include the TSV test circuit106ofFIGS. 1-5, the scan chain206ofFIG. 2, the bi-directional buffer circuit402ofFIG. 4, the chain test access module504ofFIG. 5, the TSV test circuit752ofFIG. 7, one or more other devices or circuits configured to selectively bias a circuit and to read a voltage at the circuit, or any combination thereof.

The apparatus may further include means for determining, based on a second voltage value detected at a particular TSV of the first group of TSVs, whether the particular TSV corresponds to a TSV open condition or a TSV short condition. The means for determining is configured to detect the presence of the TSV open condition or the TSV short condition after a first group of the one or more TSV contacts is contacted with the multi-contact probe and a first voltage value is applied to each of the first group of TSV contacts via the multi-contact probe. The first group of TSV contacts corresponds to a first group of the one or more TSVs. The means for determining may include the TSV test circuit106ofFIGS. 1-5, the scan chain206ofFIG. 2, the bi-directional buffer402ofFIG. 4, the chain test access module504ofFIG. 5, the processor710, the instructions756, the TSV test circuit752ofFIG. 7, one or more devices or circuits configured to determine a TSV short and/or open condition, or any combination thereof.

In an illustrative embodiment, the foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on computer readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip. The chips are then employed in devices described above.FIG. 8depicts a particular illustrative embodiment of an electronic device manufacturing process800.

Physical device information802is received at the manufacturing process800, such as at a research computer806. The physical device information802may include design information representing at least one physical property of a semiconductor device, such as the semiconductor die102ofFIG. 1, the TSV test circuit106ofFIG. 1, the bi-directional buffer circuit402ofFIG. 4, the system-on-chip device722, or any combination thereof. For example, the physical device information802may include physical parameters, material characteristics, and structure information that is entered via a user interface804coupled to the research computer806. The research computer806includes a processor808, such as one or more processing cores, coupled to a computer readable medium such as a memory810. The memory810may store computer readable instructions that are executable to cause the processor808to transform the physical device information802to comply with a file format and to generate a library file812.

In a particular embodiment, the library file812includes at least one data file including the transformed design information. For example, the library file812may include a library of semiconductor devices including a device that includes the semiconductor die102ofFIGS. 1-3and5, the TSV test circuit106ofFIGS. 1-5, the bi-directional buffer circuit402ofFIG. 2, or the system-on-chip device722that is provided for use with an electronic design automation (EDA) tool820.

The library file812may be used in conjunction with the EDA tool820at a design computer814including a processor816, such as one or more processing cores, coupled to a memory818. The EDA tool820may be stored as processor executable instructions at the memory818to enable a user of the design computer814to design a circuit including the semiconductor die102ofFIGS. 1-3and5, the bi-directional buffer circuit402ofFIG. 4, the TSV test circuit106ofFIGS. 1-5, or any combination thereof, of the library file812. For example, a user of the design computer814may enter circuit design information822via a user interface824coupled to the design computer814. The circuit design information822may include design information representing at least one physical property of a semiconductor device, such as the semiconductor die102ofFIGS. 1-3and5, the TSV test circuit106ofFIGS. 1-5, the bi-directional buffer circuit402, the system-on-chip device722ofFIG. 7, or any combination thereof. To illustrate, the circuit design property may include identification of particular circuits and relationships to other elements in a circuit design, positioning information, feature size information, interconnection information, or other information representing a physical property of a semiconductor device.

The design computer814may be configured to transform the design information, including the circuit design information822, to comply with a file format. To illustrate, the file formation may include a database binary file format representing planar geometric shapes, text labels, and other information about a circuit layout in a hierarchical format, such as a Graphic Data System (GDSII) file format. The design computer814may be configured to generate a data file including the transformed design information, such as a GDSII file826that includes information describing the semiconductor die102ofFIGS. 1-3and5, the TSV test circuit106ofFIGS. 1-5, the bi-directional buffer circuit402, the system-on-chip device722, or any combination thereof, in addition to other circuits or information. To illustrate, the data file may include information corresponding to a system-on-chip (SOC) that includes the semiconductor die102ofFIGS. 1-3and5, the TSV test circuit106ofFIGS. 1-5, the bi-directional buffer circuit402ofFIG. 4, the system-on-chip device722ofFIG. 7, or any combination thereof and that also includes additional electronic circuits and components within the SOC.

The GDSII file826may be received at a fabrication process828to manufacture the semiconductor die102ofFIG. 1, the TSV test circuit106ofFIG. 1, the semiconductor die102ofFIG. 2, or any combination thereof, according to transformed information in the GDSII file826. For example, a device manufacture process may include providing the GDSII file826to a mask manufacturer830to create one or more masks, such as masks to be used with photolithography processing, illustrated as a representative mask832. The mask832may be used during the fabrication process to generate one or more wafers834, which may be tested and separated into dies, such as a representative die836. The die836includes a circuit including a device that includes the semiconductor die102ofFIGS. 1-3and5, the TSV test circuit106ofFIGS. 1-5, the bi-directional buffer circuit402ofFIG. 4, the system-on-chip device722ofFIG. 7, or any combination thereof.

The die836can be tested using the multi-contact probe104prior to being incorporated in a package. The die836may be provided to a packaging process838where the die836is incorporated into a representative package840. For example, the package840may include the single die836or multiple dies, such as a system-in-package (SiP) arrangement. The package840may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards.

Information regarding the package840may be distributed to various product designers, such as via a component library stored at a computer846. The computer846may include a processor848, such as one or more processing cores, coupled to a memory850. A printed circuit board (PCB) tool may be stored as processor executable instructions at the memory850to process PCB design information842received from a user of the computer846via a user interface844. The PCB design information842may include physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device corresponding to the package840including the semiconductor die102ofFIGS. 1-3and5, the TSV test circuit106ofFIGS. 1-5, the bi-directional buffer circuit402ofFIG. 4, the system-on-chip device722ofFIG. 7, or any combination thereof.

The computer846may be configured to transform the PCB design information842to generate a data file, such as a GERBER file852with data that includes physical positioning information of a packaged semiconductor device on a circuit board, as well as layout of electrical connections such as traces and vias, where the packaged semiconductor device corresponds to the package840including the semiconductor die102ofFIG. 1, the TSV test circuit106ofFIG. 1, or any combination thereof. In other embodiments, the data file generated by the transformed PCB design information may have a format other than a GERBER format.

The GERBER file852may be received at a board assembly process854and used to create PCBs, such as a representative PCB856, manufactured in accordance with the design information stored within the GERBER file852. For example, the GERBER file852may be uploaded to one or more machines to perform various steps of a PCB production process. The PCB856may be populated with electronic components including the package840to form a representative printed circuit assembly (PCA)858.

The PCA858may be received at a product manufacture process860and integrated into one or more electronic devices, such as a first representative electronic device862and a second representative electronic device864. As an illustrative, non-limiting example, the first representative electronic device862, the second representative electronic device864, or both, may be selected from the group of a set top box, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a video player, a digital video player, a digital video disc (DVD) player, and a portable digital video player, into which the semiconductor die102ofFIG. 1, the TSV test circuit106ofFIG. 1, or any combination thereof, is integrated. As another illustrative, non-limiting example, one or more of the electronic devices862and864may be remote units such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. AlthoughFIG. 8illustrates remote units according to teachings of the disclosure, the disclosure is not limited to these illustrated units. Embodiments of the disclosure may be suitably employed in any device which includes active integrated circuitry including memory and on-chip circuitry.

A device that includes the semiconductor die102ofFIGS. 1-3and5, the TSV test circuit106ofFIGS. 1-5, the bi-directional buffer circuit402ofFIG. 4, the system-on-chip device722ofFIG. 7, or any combination thereof may be fabricated, processed, and incorporated into an electronic device, as described in the illustrative process800. One or more aspects of the embodiments disclosed with respect toFIGS. 1-7may be included at various processing stages, such as within the library file812, the GDSII file826, and the GERBER file852, as well as stored at the memory810of the research computer806, the memory818of the design computer814, the memory850of the computer846, the memory of one or more other computers or processors (not shown) used at the various stages, such as at the board assembly process854, and also incorporated into one or more other physical embodiments such as the mask832, the die836, the package840, the PCA858, other products such as prototype circuits or devices (not shown), or any combination thereof. Although various representative stages of production from a physical device design to a final product are depicted, in other embodiments fewer stages may be used or additional stages may be included. Similarly, the process800may be performed by a single entity or by one or more entities performing various stages of the process800.

One or more of the disclosed embodiments may be implemented in a system or an apparatus that may include a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a tablet, a portable computer, or a desktop computer. Additionally, the system or the apparatus may include a set top box, an entertainment unit, a navigation device, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a video player, a digital video player, a digital video disc (DVD) player, a portable digital video player, any other device that stores or retrieves data or computer instructions, or a combination thereof. As another illustrative, non-limiting example, the system or the apparatus may include remote units, such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. Although one or more ofFIGS. 1-8may illustrate systems, apparatuses, and/or methods according to the teachings of the disclosure, the disclosure is not limited to these illustrated systems, apparatuses, and/or methods. Embodiments of the disclosure may be suitably employed in any device that includes integrated circuitry including memory, a processor, and on-chip circuitry.

As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, “determining” may include resolving, selecting, choosing, establishing and the like. Further, a “channel width” as used herein may encompass or may also be referred to as a bandwidth in certain aspects.

Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or processor executable instructions depends upon the particular application and design constraints imposed on the overall system. Additionally, the various operations of methods described above may be performed by any suitable means capable of performing the operations, such as various hardware and/or software component(s), circuits, and/or module(s). Generally, any operations illustrated in theFIGS. 1-8may be performed by corresponding functional means capable of performing the operations. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

Those of skill in the art would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components (e.g., electronic hardware), computer software executed by a processor, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

In one or more aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer-readable storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable storage media can include random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), register(s), hard disk, a removable disk, a compact disc read-only memory (CD-ROM), other optical disk storage, magnetic disk storage, magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. In the alternative, the computer-readable media (e.g., a storage medium) may be integral to the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.

Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects computer readable medium may include a non-transitory computer readable medium (e.g., tangible media). In addition, in some aspects computer readable medium may include a transitory computer readable medium (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.

Thus, certain aspects may include a computer program product for performing the operations presented herein. For example, such a computer program product may include a computer-readable storage medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. For certain aspects, the computer program product may include packaging material.

Software or instructions (e.g., the instructions756ofFIG. 7) may also be transmitted over a transmission medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of transmission medium.

Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, or a physical storage medium such as a compact disc (CD)). Moreover, any other suitable technique for providing the methods and techniques described herein can be utilized. It is to be understood that the claims are not limited to the precise configuration and components illustrated above.

The previous description of the disclosed embodiments is provided to enable a person skilled in the art to make or use the disclosed embodiments. While the foregoing is directed to aspects of the present disclosure, other and further aspects of the disclosure may be devised without departing from the basic scope thereof, and the scope is determined by the claims that follow. Various modifications, changes and variations may be made in the arrangement, operation, and details of the embodiments described herein without departing from the scope of the disclosure or the claims. Thus, the present disclosure is not intended to be limited to the embodiments herein but is to be accorded the widest scope possible consistent with the principles and novel features as defined by the following claims and equivalents thereof.