Display substrate, manufacturing method thereof, and display panel

A display substrate, a manufacturing method thereof, and a display panel are provided. The display substrate includes a base substrate, a display region on the base substrate and a wiring region surrounding the display region. The wiring region includes at least one signal line and at least one dummy line arranged parallel to the signal line. A distance between a surface of the dummy line away from the base substrate and the base substrate is greater than a distance between a surface of the signal line away from the base substrate and the base substrate. The dummy line is arranged along the signal line, and the distance between the surface of the dummy line and the base substrate is larger than the distance between the surface of the signal line and the base substrate, i.e., a height of the signal line is greater than a height of the signal line.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Chinese Patent Application No. 201710061143.7 filed on Jan. 25, 2017, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a display substrate, a manufacturing method thereof, and a display panel.

BACKGROUND

Flat-panel display has been developed rapidly over recent decades and has attracted more and more attention. A more advanced manufacture technology needs to be adopted by manufacturers, so as to simplify a manufacture process, reduce the manufacture cost and improve the yield, thereby to improve their competitiveness. However, during the manufacture of a display panel, after a cutting process, a color filter substrate above signal lines at a peripheral region of an array substrate may be cut off, and at this time, the peripheral region of the array substrate may be exposed for the subsequent operation. The signal lines at the peripheral region function as to transmit signals from a driving circuit to a display region, so as to turn on or off thin film transistor (TFT) switches in each row and charge pixels in each column. However, usually these signal lines are merely protected by a passivation layer.

After the cutting processing, there are some manufacture processes and check procedures. During the actual manufacture, these signal lines may probably be scratched or cut off, and at this time, a defective display effect may occur and the yield may be adversely affected. Especially in the case that the signal lines at the peripheral region are arranged at two layers, the signal lines formed by a source/drain electrode layer are arranged at a level higher than, e.g., by 220 nm, the signal lines formed by a gate electrode layer, so the signal lines formed by the source/drain electrode layer are usually scratched at first. In addition, the signal lines formed by the source/drain electrode layer are covered merely by the passivation layer, so they may be cut off more easily. Hence, the defective display effect may occur and the yield may be adversely affected.

SUMMARY

An object of the present disclosure is to provide a display substrate, a manufacturing method and a display panel, so as to overcome the above-mentioned defects. During the manufacture of the display panel, a dummy line is arranged along each signal line at a level higher than the signal line. During a cutting process, the dummy line may be cut at first, so as to protect the signal line.

In one aspect, the present disclosure provides in some embodiments a display substrate, including a base substrate, a display region on the base substrate and a wiring region surrounding the display region. The wiring region includes at least one signal line and at least one dummy line arranged along the signal line. A distance between a surface of the dummy line away from the base substrate and the base substrate is greater than a distance between a surface of the signal line away from the base substrate and the base substrate.

Optionally, an orthogonal projection of the dummy line onto the base substrate at least partially overlaps an orthogonal projection of the signal line onto the base substrate.

Optionally, the display region includes at least one of a gate electrode layer, an active layer, a source/drain electrode layer and a pixel electrode layer on the base substrate.

Optionally, the dummy line is arranged at a layer identical to, and insulated from, at least one of the active layer, the pixel electrode layer and the source/drain electrode layer.

Optionally, the signal line includes at least one of a gate signal line arranged at a layer identical to, and electrically connected to, the gate electrode layer, and a data signal line arranged at a layer identical to, and electrically connected to, the source/drain electrode layer.

Optionally, an orthogonal projection of the data signal line onto the base substrate is located between orthogonal projections of adjacent gate signal lines onto the base substrate.

Optionally, at least a portion of at least one of the signal lines is provided with at least two branch lines, first end portions of the branch lines are connected to each other, second end portions of the branch lines are connected to each other, portions of the branch lines apart from the end portions are spaced apart from each other, and at least a portion of each dummy line is arranged between two adjacent branch lines.

Optionally, the display substrate further includes an insulation layer arranged between the dummy line and the signal line.

Optionally, the wiring region includes a plurality of signal lines, and the orthogonal projection of each dummy line onto the base substrate is located between orthogonal projections of two adjacent signal lines onto the base substrate.

Optionally, the orthogonal projection of each dummy line onto the base substrate at least partially overlaps the orthogonal projection of the gate signal line onto the base substrate, and the orthogonal projection of each dummy line onto the base substrate is located between the orthogonal projections of the adjacent data signal lines onto the base substrate.

Optionally, the display substrate further includes an insulation layer between the dummy line and the gate signal line, a passivation layer arranged on the insulation layer, the dummy line and the data signal line, and an electrode layer arranged on the passivation layer. A distance between a surface of the electrode layer above the gate signal line away from the base substrate and the base substrate is greater than a distance between a surface of the electrode layer above the data signal line away from the base substrate and the base substrate.

Optionally, at least a portion of at least one of the signal lines is provided with two branch lines connected in parallel. Orthogonal projections of the two branch lines onto the base substrate surround an orthogonal projection of at least a portion of the dummy line onto the base substrate.

In another aspect, the present disclosure provides in some embodiments a display panel including the above-mentioned display substrate.

In yet another aspect, the present disclosure provides in some embodiments a method for manufacturing a display substrate, including steps of: providing a base substrate including a display region and a wiring region surrounding the display region; and forming at least one signal line and at least one dummy line sequentially at the wiring region. The dummy line is formed along the signal line, and a distance between a surface of the dummy line away from the base substrate and the base substrate is greater than a distance between a surface of the signal line away from the base substrate and the base substrate.

Optionally, an orthogonal projection of the dummy line onto the base substrate at least partially overlaps an orthogonal projection of the signal line onto the base substrate.

Optionally, the method further includes forming at least one of a gate electrode layer, an active layer, a source/drain electrode layer and a pixel electrode layer at the display region.

Optionally, the dummy line is arranged at a layer identical to, and formed simultaneously together with, at least one of the active layer, the pixel electrode layer and the source/drain electrode layer.

Optionally, the step of forming the signal line includes forming at least one of a gate signal line arranged at a layer identical to, and electrically connected to, the gate electrode layer and a data signal line arranged at a layer identical to, and electrically connected to, the source/drain electrode layer while forming the gate electrode layer and the source/drain electrode layer.

Optionally, the method further includes forming an insulation layer between the dummy line and the signal line.

Optionally, the wiring region includes a plurality of signal lines, and the orthogonal projection of the dummy line onto the base substrate is located between orthogonal projections of the adjacent signal lines onto the base substrate.

REFERENCE SIGN LIST

DETAILED DESCRIPTION

During the manufacture of a display substrate, a color filter substrate above a signal line at a peripheral wiring region may be cut off, so as to expose circuits, such as the signal line, at the peripheral wiring region. The signal line may function as to turn on or off a switching element, e.g., a TFT switch, of the display panel and charge a pixel electrode. However, during the cutting process, apart from the cut portion of the color filter substrate, debris may also be dropped onto the wiring region. Usually, merely a passivation layer is arranged above the signal line so as to protect the signal line. The signal line may be scratched or cut-off by such foreign matters as the cut portion of the color filter substrate or the debris, and thereby a defective display effect may occur.

As shown inFIG. 1which is a sectional view of the wiring region of the display substrate in the related art, signal lines200may be arranged at an identical layer, e.g., they may merely include gate signal lines210arranged on a base substrate100. A gate insulation layer110and a passivation layer120are arranged sequentially on the signal lines. The gate signal line210is formed through a patterning process while forming a gate electrode of a TFT switch at a display region. InFIG. 1, A represents a cutting direction, and B-B represents a movement direction of the debris generated during the cutting operation. Because the gate insulation layer110and the passivation layer120on the signal lines200are of insufficient strength, the signal lines200may probably be scratched or cut-off by the debris.

As shown inFIG. 2which is another sectional view of the wiring region of the display substrate in the related art, the signal lines200may be arranged at two layers, e.g., they may include the gate signal lines210and data signal lines220on the base substrate100. The gate insulation layer110and the passivation layer120are arranged on the gate signal lines210, and the passivation layer120is arranged on the data signal lines220. Because the gate insulation layer110is arranged between the data signal lines220and the gate signal lines210, a height of each data signal line220on the base substrate100is usually greater than a height of the gate signal line210by, e.g., about 220 nm. The gate signal line210is formed through a patterning process while forming the source/drain electrode layer of the TFT switch at the display region. InFIG. 2, A represents the cutting direction, and B-B represents the movement direction of the debris generated during the cutting operation. The gate insulation layer110and the passivation layer120on the signal lines200are of insufficient strength, the data signal line220is arranged at a level higher than the gate signal line210, and merely the passivation layer120is arranged on the data signal line220, so the signal lines200, especially the data signal lines220, may probably be scratched.

It should be appreciated that, the so-called height is measured with the base substrate as a reference. A height of a member refers to a vertical distance between a surface of the member away from the base substrate and the base substrate, rather than a thickness of the member. Taking the data signal line220inFIG. 2as an example, its height is the vertical distance between a surface of the data signal line220away from the base substrate100and the base substrate100, and in this case, its height is a sum of a thickness of the gate insulation layer110and a thickness of the data signal line.

An object of the present disclosure is to provide a display substrate, a manufacturing method thereof and a display panel, so as to overcome the above-mentioned defects. The display substrate includes a base substrate, a display region arranged on the base substrate, and a wiring region surrounding the display region. The wiring region includes at least one signal line and at least one dummy line arranged along the signal line. A distance between a surface of the dummy line away from the base substrate and the base substrate is greater than a distance between a surface of the signal line away from the base substrate and the base substrate, i.e., a height of the dummy line on the base substrate is greater than a height of the signal line. During the cutting procedure, because the dummy line is arranged along the signal line and has a height greater than the signal line, the dummy line may be scratched by the resultant debris at first, and even in the case that the kinetic energy of the debris is released subsequently, it is still able to protect the signal line.

As shown inFIG. 3which is a top view of the wiring region of the display substrate, the wiring region includes at least one signal line200(e.g., a gate signal line210) and at least one dummy line300arranged along the signal line200. The dummy line300may be arranged between two adjacent signal lines200and have a height greater than the signal line200. In this way, the dummy line300may be cut at first.

In the case of being arranged along the signal line, the dummy line may be, but not limited to, arranged parallel to the signal line. For example, it may include a plurality of segments each arranged along the signal line and crossing the signal line, or it may be of cylindrical structure arranged on the signal line or between the adjacent signal lines in a multi-point distribution manner. In addition, apart from the segments, the dummy line may also be distributed as a continuous line or dots. It is able for the dummy line to protect the adjacent signal line as long as the dummy line is arranged in proximity to the signal line and has a height greater than the adjacent signal line.

Optionally, at least a portion of at least one of the signal lines is provided with at least two branch lines, first end portions of the branch lines are connected to each other, second end portions of the branch lines are connected to each other, portions of the branch lines apart from the end portions are spaced apart from each other, and at least a portion of each dummy line is arranged between two adjacent branch lines. For example, the signal line has two branch lines, first ends of the two branch lines (i.e., a bifurcation point where the signal line is divided into the two branch lines) are connected to each other, and second ends of the two branch lines (i.e., a merge point where the two branch lines are merged into the signal line) are connected to each other. Apart from the ends, the other portions of the branch lines are separated from each other, and a portion of the dummy line is arranged between the branch lines, so as to protect them.

As shown inFIG. 4which is another top view of the wiring region of the display substrate, at least a portion of at least one of the signal lines is provided with at least two branch lines. The portion of the signal line having the branch lines may be of a mouth-shape structure, i.e., the signal line200may have two portions arranged at two layers at the mouth-type structure, and a portion of the dummy line300may pass through the mouth-type structure. For example, the mouth-type structure may be arranged at a position where the signal line200is to be easily cut, and after one branch line of the signal line200has been scratched or cut off, the signal line200may still work due to the other branch line. After the position where the signal line200is to be easily cut, apart from the mouth-type structure inFIG. 4, the signal line200may also be widened, and a portion of the dummy line300may be arranged on the widened signal line200, so as to protect the signal line200.

It should be appreciated that, in the case that the signal line includes two branch lines, the mouth-type structure may be a square or circular structure, and it is able for the dummy line to protect the portion of the signal line as long as the mouth-type structure has at least two branch lines arranged in parallel and a portion of the dummy line passes through the mouth-type structure.

It should be appreciated that, inFIGS. 3 and 4, the signal lines are arranged at an identical layer, i.e., merely the gate signal lines are provided. However, in the case that the signal lines are arranged at two layers, i.e., they include the gate signal lines and the data signal lines, the arrangement mode for the signal lines and the dummy lines inFIGS. 3 and 4may also be applied.

Optionally, the display region includes at least one of a gate electrode layer, an active layer, a source/drain electrode layer and a pixel electrode layer, which are formed on the base substrate through a patterning process.

Optionally, the dummy line is arranged at a layer identical to, and insulated from, at least one of the active layer, the pixel electrode layer and the source/drain electrode layer.

Optionally, the signal lines may be arranged at an identical layer. As shown inFIG. 5which is a sectional view of the wiring region of the display substrate, the signal lines200and the dummy lines300are arranged sequentially on the base substrate100. The signal line200may be the gate signal line210which is formed through a patterning process while forming the gate electrode. The dummy line300may be arranged between the adjacent signal lines200, or on the signal line200.

Optionally, as shown inFIG. 5, a first dummy line310of the dummy lines300may be arranged at a layer identical to, and insulated from, the active layer at the display region. For example, the first dummy line310may be formed on the base substrate100through a patterning process while forming the active layer, and it may be made of a material identical to the active layer.

Optionally, as shown inFIG. 5, a second dummy line320of the dummy lines300may be arranged at a layer identical to, and insulated from, the pixel electrode layer at the display region. For example, the second dummy line320may be formed on the base substrate100through a patterning process while forming the pixel electrode layer, and it may be made of a material identical to the pixel electrode layer.

Optionally, as shown inFIG. 5, a third dummy line330of the dummy lines300may be arranged at a layer identical to, and insulated from, the source/drain electrode layer at the display region. For example, the third dummy line330may be formed on the base substrate100through a patterning process while forming the source/drain electrode layer, and it may be made of a material identical to the source/drain electrode layer.

It should be appreciated that, in the embodiments of the present disclosure, the dummy lines may include one of the first dummy line, the second dummy line and the third dummy line, or a combination thereof. It is able for the dummy lines to protect the signal lines as long as the dummy line has a height greater than the signal line.

Optionally, the signal lines are arranged at two layers. As shown inFIG. 6awhich is another sectional view of the wiring region of the display substrate, the signal lines200and the dummy lines300are arranged sequentially on the base substrate100. The signal lines200include the gate signal lines210and the data signal lines220, and they may be formed through a patterning process while forming the gate electrode. The data signal lines220may be formed through a patterning process while forming the source/drain electrode layer. Due to the sequence of the formation, the data signal line220is usually formed on the gate signal line210and between the adjacent gate signal lines210, and it has a height greater than the gate signal line210. The dummy line300may be arranged on the gate signal line210, as long as its height is greater than the height of the data signal line220.

Optionally, as shown inFIG. 6a, the first dummy line310of the dummy lines300may be arranged at a layer identical to, and insulated from, the active layer at the display region. For example, the first dummy line310may be formed on the base substrate100through a patterning process while forming the active layer, and it may be made of a material identical to the active layer.

Optionally, as shown inFIG. 6a, the second dummy line320of the dummy lines300may be arranged at a layer identical to, and insulated from, the pixel electrode layer at the display region. For example, the second dummy line320may be formed on the base substrate100through a patterning process while forming the pixel electrode layer, and it may be made of a material identical to the pixel electrode layer.

Optionally, the first dummy line of the dummy lines may be made of a material identical to the active layer at the display region. For example, the active layer may be made of amorphous silicon (a-Si), polycrystalline silicon (p-Si), or a metal oxide such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO) or gallium zinc oxide (GZO).

Optionally, the second dummy line of the dummy lines may be made of a material identical to a pixel electrode at the display region, e.g., a transparent conductive material or a metal material. For example, the pixel electrode may be made of Indium tin oxide (ITO), IZO, indium gallium oxide (IGO), GZO, ZnO, indium oxide (In2O3), aluminium zinc oxide (AZO) or carbon nanotube.

Optionally, the third dummy line of the dummy lines or the data signal line may be made of a material identical to the source/drain electrode layer at the display region. For example, the source/drain electrode layer may be made of a metal material, and it may have a single-layered structure, e.g., a singled-layered aluminium structure or a single-layered molybdenum structure, or a triple-layered structure, e.g., Mo/Al/Mo.

Optionally, as shown inFIGS. 5 and 6a, the display substrate further includes the insulation layer110arranged between the base substrate100and the dummy lines300. The insulation layer100may be a gate insulation layer, i.e., the gate insulation layer may be formed on the gate signal lines210while forming the gate insulation layer of the TFT at the display region. The gate insulation layer may be made of silicon nitride (SiNx), silicon oxide (SiOx), aluminium oxide (Al2O3), aluminium nitride (AlN), or any other appropriate material.

Optionally, as shown inFIGS. 5 and 6a, the display substrate may further include the passivation layer120arranged on the signal lines200and the dummy lines300. For example, the passivation layer120may be made of SiNx or SiOx.

It should be appreciated that, the dummy lines may not be limited to the above combination modes, and any other combination mode may be applied, as long as the dummy line is provided with sufficient strength and has a height greater than signal line.

FIG. 6bis yet another sectional view of the wiring region of the display substrate. In the case that the signal lines are arranged at two layers, as shown inFIG. 6b, an electrode layer1000may be arranged on the base substrate with the dummy lines300and the signal lines100. The first dummy line310, the second dummy line320and the electrode layer1000may be arranged on the gate signal line210, and the electrode layer1000may be arranged on the data signal line220. The electrode layer100on the gate signal line210may be located at a level higher than the electrode layer1000on the data signal line220. In the case that such foreign matters as debris are dropped onto the electrode layer1000on the data signal lines220, they may slide to a higher position, e.g., to the electrode layer1000on the gate signal line210, due to a smooth surface of the electrode layer1000. At this time, the kinetic energy of the foreign matters may be released at the electrode layer1000on the gate signal line210, and thereby the data signal line220may not be damaged.

It should be appreciated that, in the case that the signal lines are arranged at an identical layer, the electrode layer may also be provided so as to protect the signal lines. In addition, apart from being arranged on the dummy lines and the signal lines, the electrode layer may also be arranged merely on the data signal lines, so as to protect the data signal lines. Further, apart from including the first dummy line and the second dummy line, the dummy lines may also include any one of the first dummy line, the second dummy line and the third dummy line, or a combination thereof.

The electrode layer may be made of a transparent conductive material or a metal material. For example, the pixel electrode may be made of ITO, IZO, IGO, GZO, ZnO, In2O3, AZO or carbon nanotube. In the case that the electrode layer is made of ITO, the electrode layer may be provided with a smooth surface, so that the foreign matters such as the debris may slide along the surface.

Optionally, in the case that the signal lines are arranged at an identical layer, as shown inFIG. 7which is still yet another sectional view of the wiring region of the display substrate, the dummy lines300may merely include the third dummy lines330arranged at an identical layer and made of a material identical to the source/drain electrode layer. Due to the sufficient strength, it is able for the third dummy lines330to protect the gate signal lines210.

The dummy lines may be arranged between the adjacent signal lines, or on the signal lines, or both.

Optionally, in the case that the signal lines are arranged at two layers, as shown inFIG. 8which is still yet another sectional view of the wiring region of the display substrate, the dummy lines300may include merely the third dummy lines330arranged at an identical layer. The third dummy lines300and the data signal lines220may be made of a material identical to the source/drain electrode layer, and the third dummy lines330may have sufficient strength. The data signal line220is arranged between the adjacent gate signal lines210, and the third dummy line330is arranged on the gate signal line210. The third dummy line330has a height greater than the data signal line220, and the gate signal line210is arranged below the third dummy line330, so it is able for the third dummy line330to protect the signal line200.

InFIG. 8, the dummy lines300merely include the third dummy lines330, and as compared withFIG. 6a, the first dummy lines310and the second dummy lines320are replaced with the third dummy lines330. It should be appreciated that, the third dummy lines330may also be arranged on the first dummy lines310and the second dummy lines320inFIG. 6a, and at this time, the dummy lines300may include the first dummy lines310, the second dummy lines320and the third dummy lines330arranged at three layers.

The present disclosure further provides in some embodiments a method for manufacturing the display substrate. The method includes steps of: providing the base substrate including the display region and the wiring region surrounding the display region; and forming at least one signal line and at least one dummy line sequentially at the wiring region. The dummy line is formed along the signal line, and a distance between a surface of the dummy line away from the base substrate and the base substrate is greater than a distance between a surface of the signal line away from the base substrate and the base substrate.

Optionally, the method further includes forming at least one of the gate electrode layer, the active layer, the source/drain electrode layer and the pixel electrode layer at the display region.

Optionally, the dummy line is arranged at a layer identical to, and formed simultaneously together with, at least one of the active layer, the pixel electrode layer and the source/drain electrode layer.

Optionally, the step of forming the signal line includes forming at least one of the gate signal line arranged at a layer identical to, and electrically connected to, the gate electrode layer and the data signal line arranged at a layer identical to, and electrically connected to, the source/drain electrode layer while forming the gate electrode layer and the source/drain electrode layer.

Optionally, the method further includes forming the insulation layer between the dummy line and the signal line.

Optionally, the dummy line is arranged on the signal line, or between the adjacent signal lines.

According to the embodiments of the present disclosure, the dummy line is arranged at the wiring region of the display substrate at a level higher than the signal line, so as to prevent the signal line from being scratched. In addition, the dummy line may be made of a material identical to, and formed through a patterning process identical to, the other layers of the display substrate (e.g., the layers of the TFT), so it is unnecessary to provide any additional process.

In the embodiments of the present disclosure, the signal lines may be arranged at an identical layer or two layers. For ease of understanding, the manufacture procedure of the display substrate will be described hereinafter in both cases. It should be appreciated that, the combination modes of the dummy lines have been described hereinabove, and it should be appreciated that, any other combination mode of the dummy lines may also be applied.

It should be appreciated that, the signal lines and the dummy lines at the wiring region may be formed simultaneously with the gate electrode, the active layer, the pixel electrode layer and the source/drain electrode layer of the TFT, so in the following description, the manufacture of the layers of the TFT at the display region will not be particularly defined. For example, in the case that a gate electrode layer film is formed on the base substrate, it may be patterned so as to form the gate electrode (at the display region) and the gate signal line (at the wiring region). Here, merely the manufacture of the display substrate at the wiring region is described, so merely the formation of the gate signal line is particularly defined.

In the case that the signal lines are arranged at an identical layer, as shown inFIGS. 9a-9f, the manufacture method of the display substrate will be described as follows.

As shown inFIG. 9a, the base substrate100may be provided, and a gate electrode layer film may be deposited onto the base substrate100. Then, the gate electrode layer film may be treated through a patterning process, so as to form the signal lines200, i.e., the gate signal lines210.

Optionally, the patterning process may be a photoetching process. To be specific, a photoresist may be applied to the gate electrode layer film, and then exposed with a mask plate. Next, the exposed photoresist may be developed so as to acquire a photoresist pattern, and the gate electrode layer film may be etched using the photoresist pattern. Optionally, the remaining photoresist may be removed.

As shown inFIG. 9b, the insulation layer110may be deposited onto the base substrate with the gate signal lines210.

As shown inFIG. 9c, an active layer film may be formed on the insulation layer110, and then treated through a patterning process so as to form the first dummy line310. The first dummy line310may be arranged between the adjacent gate signal lines210, or on the gate signal line210.

As shown inFIG. 9d, a pixel electrode layer film may be deposited onto the base substrate100with the first dummy line310, and then treated through a patterning process, so as to form the second dummy line320. The second dummy line320may be arranged on the first dummy line310.

As shown inFIG. 9e, a source/drain electrode layer film may be deposited onto the base substrate with the second dummy line320, and then treated through a patterning process so as to form the third dummy line330. The third dummy line330may be arranged on the second dummy line320.

As shown inFIG. 9f, the passivation layer120may be deposited onto the base substrate100with the third dummy line330.

In the case that the signal lines are arranged at two layers, as shown inFIGS. 10a-10f, the manufacture method of the display substrate will be described as follows.

As shown inFIG. 10a, the base substrate100may be provided, and a gate electrode layer film may be deposited onto the base substrate100. Then, the gate electrode layer film may be treated through a patterning process, so as to form parts of the signal lines200arranged at one layer, i.e., the gate signal lines210.

As shown inFIG. 10b, the insulation layer110may be deposited onto the base substrate with the gate signal lines210.

As shown inFIG. 10c, an active layer film may be formed on the insulation layer110, and then treated through a patterning process so as to form the first dummy line310. The first dummy line310may be arranged on the gate signal line210.

As shown inFIG. 10d, a pixel electrode layer film may be deposited onto the base substrate100with the first dummy line310, and then treated through a patterning process, so as to form the second dummy line320. The second dummy line320may be arranged on the first dummy line310.

As shown inFIG. 10e, a source/drain electrode layer film may be deposited onto the base substrate100with the second dummy line320, and then treated through a patterning process so as to form the data signal line220. The data signal line220may be arranged between the adjacent gate signal lines210and arranged at a layer different from the gate signal lines210.

As shown inFIG. 10f, the passivation layer120may be deposited onto the base substrate100with the data signal line220.

As mentioned above, the method for manufacturing the display substrate in the embodiments of the present disclosure includes the steps identical to those of the method for manufacturing the display substrate in the related art. As a result, it is able to form the dummy lines for protecting the signal lines without any additional patterning process.

It should be appreciated that, in the embodiments of the present disclosure, the TFT at the display region is of a bottom-gate structure, and the dummy lines are formed in an order identical to the layers of the bottom-gate TFT. Of course, in the case that the TFT is of a top-gate structure, the dummy lines may be formed in an order identical to the layers of the top-gate TFT. In other words, the first dummy line, the second dummy line and the third dummy line are not formed in a fixed order, and the number of the layers thereof is fixed too. It is able for the dummy line to protect the signal line as long as the dummy line has a height greater than the signal line.

The present disclosure further provides in some embodiments a display panel including the above-mentioned display substrate. The display panel further includes a color filter substrate arranged opposite to the display substrate to form a cell. The wiring region is arranged between the base substrate and the color filter substrate, and the color filter substrate is arranged in such a manner as to expose the wiring region after being cut off.

As shown inFIG. 11which is a topical, sectional view of the display panel, the display panel includes a display substrate1, a color filter substrate2arranged opposite to the display substrate1to form a cell, and a sealant6. The display substrate1includes a display region3and a peripheral region4including a wiring region5a region surrounding the wiring region. The sealant6is arranged between the display region3and the peripheral region4.

During the manufacture of the display panel, it is necessary to cut off a portion of the color filter substrate2along a cutting line A, so as to expose the wiring region5. However, during the cutting procedure, the cut-off portion of the color filter substrate2may be dropped onto the display substrate1, and meanwhile the debris may occur, so the circuit at the wiring region5may easily be scratched. In the embodiments of the present disclosure, due to the dummy lines (not shown) at the wiring region of the display substrate, it is able to protect the circuit, e.g., the signal lines from being scratched, thereby to prevent the occurrence of the defective display effect.

For example, the display panel may be a liquid crystal display panel, which includes the display substrate, the color filter substrate arranged opposite to the display substrate to form a liquid crystal cell, and a liquid crystal material filled within the liquid crystal cell. A pixel electrode of each pixel unit of the display substrate is configured to apply an electric field to the liquid crystal material, so as to control a deflection degree of the liquid crystal material, thereby to display an image.

For another example, the display panel may also be an organic light-emitting diode (OLED) display panel. An organic light-emitting layer is arranged on the display substrate, and a pixel electrode of each pixel unit functions as an anode or a cathode, so as to drive the organic light-emitting layer to emit light, thereby to display an image.

For yet another example, the display panel may also be an electronic paper display panel. An electronic ink layer is formed on the display substrate, and a pixel electrode of each pixel unit is configured to apply a voltage, so as to drive charged particles in electronic ink to move, thereby to display an image.

It should be appreciated that, (1) the drawings in the embodiments of the present disclosure merely refer to the necessary structures, and any other structure may refer to a common design. (2) For clarification, the thicknesses of the layers or regions in the drawings are zoomed in or out, i.e., the drawings are not used to reflect an actual scale. (3) In the case of no conflict, the embodiments of the present disclosure and the features therein may be combined in any form to acquire new embodiments.

The above are merely the preferred embodiments of the present disclosure, but the present disclosure is not limited thereto. Obviously, a person skilled in the art may make further modifications and improvements without departing from the spirit of the present disclosure, and these modifications and improvements shall also fall within the scope of the present disclosure.