Low insertion delay clock doubler and integrated circuit clock distribution system using same

A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.

FIELD

This disclosure relates generally to clock circuits, and more specifically to clock circuits for uses such as integrated circuit clock trees.

BACKGROUND

Modern microprocessors are complex logic circuits that contain many millions of transistors integrated onto a small semiconductor chip. Microprocessors operate in synchronism with a clock signal. They typically include a phase locked loop (PLL) to increase the frequency of an input clock signal to higher operating frequencies. The higher frequency clock signal is distributed to various circuit blocks such as caches, instruction decoders, register files, arithmetic logic units, and the like in a hierarchy known as a “clock tree”. The clock tree has a main trunk from the PLL, major branches that are routed in different directions on the chip, and sub-branches until the clock signals reach the actual circuitry. The clock tree typically re-buffers the clock signals at each branch and sub-branch.

Dynamic power in clocked complementary metal-oxide-semiconductor (CMOS) circuits is a function of the dynamic capacitance and both the frequency of operation and the square of the voltage, according to the formula P=CV2f. The required voltage in turn is related to the frequency of operation; at faster speeds, higher voltages are required for proper operation. Conversely operation at lower speeds reduces power consumption by both reducing the frequency and reducing the required voltage.

Although modern, deep sub-micron CMOS semiconductor manufacturing technologies have allowed microprocessor chips to remain relatively small, the clock signals must be distributed widely around the chip. The signal lines that carry the clock signals have large capacitances because of the distances involved, and therefore they consume a significant portion of the chip's power budget. For example, the clock distribution network may account for about 10% or more of the overall chip power budget.

Because of the high power consumption of the clock tree, some engineers have devised clock trees whose PLLs output the main clock signal at half of the desired operating frequency. The clock tree distributes the half-speed clock signal to save power. Then a set of local clock doublers increase the frequency of the half-speed clock signal at the branches or leaves of the tree back to the desired operating frequency. Unfortunately, known clock doublers have problems themselves, including high power consumption and the inability to provide a symmetrical 50% duty cycle. The drawbacks of known clock doublers have reduced the advantage of using this clock distribution technique.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In one form, a clock doubler includes first and second NAND gates, an output NAND gate, an inverter chain, and a clock signal generation circuit. The first NAND gate has a first input for receiving a clock input signal, a second input, and an output. The second NAND gate has a first input, a second input for receiving a complement of the clock input signal, and an output. The output NAND gate has a first input coupled to the output of the first NAND gate, a second input coupled to the outputs of the second NAND gate, and an output for providing a clock output signal. The inverter chain has an input for receiving the clock input signal and is responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate. The control signal generation circuit provides the first and second control signals in response to the outputs of the first and second NAND gates.

In some embodiments, such a clock doubler may be used in a half-clock distribution system. The clock distribution system may include a phase locked loop having an input for receiving an external clock signal and an output for providing the clock input signal, and a plurality of clock sub-domains each receiving the clock input signal, in which each of the plurality of clock sub-domains comprise the clock doubler.

In other embodiments, the clock doubler can be used in different circuits and operate with low power consumption and small size.

In some embodiments, a clock input signal having a first frequency is received. The clock input signal is selectively buffered during a first phase of a clock output signal to form a first state signal. The first state signal is selectively inverted during a second phase of the clock output signal to form a second state signal. A first phase clock signal is formed in response to a logical combination of the clock input signal and the second state signal. A second phase clock signal is formed in response to a logical combination the first state signal and a complement of the clock input signal. The clock output signal is provided at a second frequency twice the first frequency in response to a logical combination of the first phase clock signal and a second phase clock signal.

FIG. 1illustrates in block diagram form a first clock doubler100known in the prior art. Clock doubler100includes an inverter110, a delay circuit120, a NAND gate130, a delay circuit140, and a NAND gate150, and an NAND gate160. Inverter110has an input for receiving a clock input signal labeled “CLKIN”, and an output. Delay circuit120has an input for receiving the CLKINsignal, and an output. NAND gate130has a first input for receiving the CLKINsignal, a second input connected to the output of delay circuit120, and an output. Delay circuit140has an input for receiving the CLKINsignal, and an output. NAND gate140has a first input connected to the output of delay circuit140, a second input for receiving the CLKINsignal, and an output. NAND gate150has a first input connected to the output of NAND gate130, a second input connected to the output of NAND gate150, and an output for providing a clock output signal labeled “CLKOUT”.

Clock doubler circuit100receives the CLKINsignal at a frequency f and converts it into the CLKOUTsignal at a frequency of 2f. When CLKINhas been stable at a logic low, the first input of NAND gate130is a logic low, whereas the output of delay circuit120, which includes an odd number of inverting stages, is a logic high. Thus the output of NAND gate130is at a logic high. Inverter110provides a logic high at its output, and delay circuit140, which also includes an odd number of inverting stages, provides a logic low at its output, which causes NAND gate150to output a logic high. Since both inputs of NAND gate160are at a logic high, it outputs the CLKOUTsignal at a logic low.

When CLKINswitches to a logic high, the inputs of NAND gate130are temporarily both at a logic high, and NAND gate130temporarily outputs a logic low. The logic low at the first input of NAND gate160causes its output to temporarily switch to a logic high. The output of delay circuit140begins at a logic low, keeping the output of NAND gate150at a logic high. When the logic high at the input of delay circuit120has propagated to the output as a logic low, the output of NAND gate130switches to a logic high. Meanwhile, output of delay circuit140is initially at a logic low. The logic low at the output of inverter110propagates to the output of delay circuit140as a logic high. However since the output of inverter110is a logic low, the output of NAND gate150remains at a logic high.

When CLKINthen switches to a logic low, the inputs of NAND gate130are temporarily both at a logic low, and NAND gate130outputs a logic high. The output of delay circuit120begins at a logic low, keeping the output of NAND gate130at a logic high. The logic low at the input of delay circuit120eventually propagates to the output as a logic high. Meanwhile, output of delay circuit140is initially at a logic high. The logic high at the output of inverter110causes NAND gate150to output a logic low, which causes NAND gate160to temporarily switch to a logic high. When the input of delay circuit140propagates to the output as a logic low, the output of NAND gate150switches to a logic high, causing the output of NAND gate160to switch to a logic low. Thus during each half phase of the CLKINsignal, the CLKOUTsignal initially switches to a logic high before returning to a logic low, resulting in clock doubling.

However clock doubler100has at least two problems. First, the delay stages themselves consume significant amounts of power because the delay stages are made up of CMOS inverters that consume power every time they switch. For example, delay circuits120and140may each require 7 or 9 inverters to provide adequate delay. When combined with many other such clock doublers in a clock tree, the power savings gained from distributing the clock at half frequency are significantly offset by the increased power consumption caused by the operation of the clock doublers at the end of each branch.

Second, clock doubler100is typically required to drive a large load, which may reduce the logic high time and eventually cause failure of load circuits. Moreover, the load will vary throughout the integrated circuit, making it difficult to design a single clock doubler which is capable of adequately driving all loads.

FIG. 2illustrates in block diagram form a second clock doubler200known in the prior art. Clock doubler200includes a delay circuit210and an exclusive NOR gate220. Delay circuit210has an input for receiving the CLKINsignal, and an output. Exclusive NOR gate220has a first input for receiving the CLKINsignal, a second input connected to the output of delay circuit210, and an output for providing the CLKOUTsignal.

Exclusive NOR gate220provides the CLKOUTsignal at a logic high when both of its inputs are in the same logic state, and at a logic one when its inputs are in different logic states. Delay circuit210has an odd number of delay stages so that its output is in the opposite logic state as its input after the input has propagated to the output. Thus when CLKINis initially in a logic low and switches to a logic high, the inputs to exclusive NOR gate220are initially in the same logic state (logic high), and the output of exclusive NOR gate220is initially at a logic low. When the logic high at the input of delay circuit210propagates to a logic low at the output, then the inputs to exclusive NOR gate220are different and exclusive NOR gate220outputs a logic low. When CLKINswitches to a logic low, the inputs to exclusive NOR gate220are initially in the same logic state (logic low), and the output of exclusive NOR gate220is initially at a logic high. When the logic low at the input of delay circuit210propagates to a logic high at the output, then the inputs to exclusive NOR gate220are different and exclusive NOR gate220outputs a logic low. Thus during each half phase of the CLKINsignal, the CLKOUTsignal initially switches to a logic high before returning to a logic low, resulting in clock doubling.

While clock doubler200has reduced area and power compared to clock doubler100ofFIG. 1, the number of inverting delay stages will be about the same. Thus clock doubler200continues to consume a significant amount of area and power.

FIG. 3illustrates in block diagram form a third clock doubler300known in the prior art. Clock doubler300includes a delay circuit310and an exclusive OR gate320. Delay circuit310has an input for receiving the CLKINsignal, and an output. Exclusive OR gate320has a first input for receiving the CLKINsignal, a second input connected to the output of delay circuit310, and an output for providing the CLKOUTsignal.

Exclusive OR gate320provides the CLKOUTsignal at a logic high when its inputs are in different logic states, and at a logic low when its inputs are in the same logic state. Delay circuit310has an even number of delay stages so that its output is in the same logic state as its input after the input has propagated to the output. Thus when CLKINis initially in a logic low and switches to a logic high, the inputs to exclusive OR gate320are initially in different logic states, and the output of exclusive OR gate320is initially at a logic high. When the logic high at the input of delay circuit310propagates to a logic high at the output, then the inputs to exclusive OR gate320are in the same state and exclusive OR gate320outputs a logic low. When CLKINswitches to a logic low, the inputs to exclusive NOR gate320are initially in different logic states, and the output of exclusive OR gate320is initially at a logic high. When the logic low at the input of delay circuit310propagates to a logic low at the output, then the inputs to exclusive OR gate320are the same and exclusive OR gate320outputs a logic low. Thus during each half phase of the CLKINsignal, the CLKOUTsignal initially switches to a logic high before returning to a logic low, resulting in clock doubling.

Clock doubler300is the analog of clock doubler200ofFIG. 2for exclusive OR logic. While clock doubler300also has reduced area and power compared to clock doubler100ofFIG. 1, the number of inverting delay stages will be about the same. Thus clock doubler300(like clock doubler200) also consumes a significant amount of area and power.

FIG. 4illustrates in block diagram form a fourth clock doubler400known in the prior art. Clock doubler400includes an exclusive NOR gate410, a D-type flip flop420, and an inverter430. Exclusive NOR gate410has a first input, a second input for receiving the CLKINsignal, and an output for providing the CLKOUTsignal. D-type flip flop has a D input, a clock input connected to the output of exclusive NOR gate410, and a Q output. Inverter430has an input connected to the Q output of D-type flip flop420, and an output connected to the first input of exclusive NOR gate410and to the D input of D-type flip flop420.

Since clock doubler400uses D-type flip-flop420, it consumes extra power compared to NAND gates130,140and150of clock doubler100, exclusive NOR gate220of clock doubler200, and exclusive OR gate320of clock doubler300. However it also uses the clock-to-Q delay of D-type flip flop420as part of the delay chain, saving area and power in the respective delay chains. However the clock-to-Q delay of flip-flop420sets a lower limit on the delay time of the CLKOUTpulse, potentially providing a wider pulse than necessary when used to directly control register elements like flip-flops and latches.

FIG. 5illustrates in block diagram form an integrated circuit500with a clock distribution system510according to some embodiments. Clock distribution system510includes a bonding pad520, a PLL530, and a set of clock sub-domains540,550,560, and570. Bonding pad520receives an external clock signal labeled “CLKEXT”. PLL530has an input connected to bonding pad520, a control input for receiving a signal labeled “FID”, and an output for providing the CLKINsignal. Clock distribution system510includes a number of clock sub-domains, of which a representative set540,550,560, and570are shown inFIG. 5. Each clock sub-domain has a clock doubler having an input for receiving the CLKINsignal, and an output for providing a respective CLKOUTsignal. Clock sub-domain540includes a clock doubler542having an input for receiving the CLKINsignal, and an output for providing a signal labeled “CLKOUT2” for use in a further distribution to circuits in its clock sub-domain. Clock sub-domains550,560, and570each include clock doublers552,562, and572, respectively, having inputs for receiving the CLKINsignal, and outputs for providing signals labeled “CLKOUT2”, “CLKOUT3”, and “CLKOUT4”, respectively.

FIG. 5illustrates further details of an exemplary clock sub-domain550. Connected to the output of clock doubler552is a set of buffers554each providing buffered CLKOUT2signals to different portions of clocked logic556. Note that integrated circuit500may be a microprocessor or other clocked logic circuit that utilizes a clock tree with half-clock distribution to various clock sub-domains. Moreover, integrated circuit500may include other clock domains besides the domain associated with clock distribution system500. For example as shown inFIG. 5, PLL530receives control signal FID which represents a frequency identification signal that allows the frequency of which the clock domain operates to vary. This is useful in multi-core microprocessors that allow each processor core to operates in a different power state (P-state), wherein each P-state is defined by a different frequency (indicated by FID) and voltage, and which control the P-state of each core to correspond to the processing workload.

FIG. 6illustrates in partial block diagram and partial schematic form a clock doubler600suitable for use in clock distribution system510ofFIG. 5according to some embodiments. Clock doubler600includes generally NAND gates610,620, and630, an inverter640, an inverter chain650, a P-channel MOS transistor660, and a control signal generation circuit670. NAND gate610has a first input for receiving the CLKINsignal, a second input, and an output for providing a signal labeled “pHi”. NAND gate620has first and second inputs, and an output for providing a signal labeled “pLo”. NAND gate630has a first input connected to the output of NAND gate610, a second input connected to the output of NAND gate620, and an output for providing the CLKOUT2signal. Inverter640has an input for receiving the CLKINsignal, and an output connected to the second input of NAND gate620.

Inverter chain650includes a three-state inverter652, an inverter654, and a three-state inverter656. Three-state inverter652has an input for receiving the CLKINsignal, a true control input for receiving an allow clock signal labeled “AC”, a complement control input for receiving a complement of the allow clock signal labeled “AC”, and an output. Inverter654has an input connected to the output of three-state inverter652, and an output connected to the first input of NAND gate620. Three-state inverter656has an input connected to the output of inverter654, a true control input for receiving signalAC, a complement control input for receiving signal AC, and an output connected to the input of inverter654and to the second input of NAND gate610.

Transistor660has a source connected to a power supply voltage terminal labeled “VDD”, a gate for receiving a signal labeled “ENABLE”, and a drain connected to the second input terminal of NAND gate610. Control signal generation circuit670includes a NAND gate672and an inverter674. NAND gate672has a first input for receiving the pHi signal, a second input for receiving the pLo signal, and an output for providing signal AC. Inverter674has an input connected to the output of NAND gate672, and an output for providing signalAC.

When clock doubler600if gated off, a controller (not shown) de-activates the ENABLE signal at a logic low. Transistor660is conductive, forcing a logic high on the second input of NAND gate610. The second input of NAND gate610forms a state node of clock doubler600. The controller also keeps the CLKINsignal at a logic low, thus holding signal pHi at the output of NAND gate610at a logic high. The logic high at the second input of NAND gate610is inverted by inverter654to provide a logic low at the first input of NAND gate620. The logic low forces the output of NAND gate620to a logic high. Since both of its inputs are logic high, NAND gate630provides the CLKOUT2signal at a logic low. Control signal generation circuit670provides signal AC at a logic low and signalACat a logic high, which disables three-state inverter652and enabled three-state inverter656.

When clock doubler600is gated on, the controller activates the ENABLE signal at a logic high, making transistor660non-conductive, but since three-state inverter656is conductive, the logic high on the state node remains. The CLKINsignal begins to toggle as a free-running clock at frequency f and clock doubler600starts to function. The first rising edge of the CLKINsignal causes pHi to go to a logic low since the state node is also at a logic high, which in turn causes CLKOUT2to go to a logic high. Signal pLo is at a logic high since the output of inverter654is a logic low. Control signal generation circuit670provides signal AC at a logic high and signalACat a logic low, enabling three-state inverter652and disabling three-state inverter656. Since transistor660and three-state inverter656are both non-conductive, three-state inverter652drives the state node to a logic low, which the causes signal pHi to return to a logic high and the CLKOUT2signal to return to a logic low. During this sequence, signal pLo remains at a logic high, causing control signal generation circuit670to provide signal AC at a logic low and signalACat a logic high, disabling three-state inverter652and enabling three-state inverter656, and thus maintaining signals pHi and pLo at a logic high.

The next falling edge of the CLKINsignal causes signal pLo to go to a logic low since the output of inverters654and640are both at a logic high, which in turn causes CLKOUT2to go to a logic high. Signal pHi is at a logic high since the CLKINsignal is a logic low. Control signal generation circuit670provides signal AC at a logic high and signalACat a logic low, enabling three-state inverter652and disabling three-state inverter656. Since transistor660and three-state inverter656are both non-conductive, three-state inverter652drives the state node to a logic high, and the output of inverter654to a logic low, which the causes the CLKOUT2signal to return to a logic low. During this sequence, pHi remains at a logic high, causing control signal generation circuit670to provide signal AC at a logic low and signalACat a logic high, disabling three-state inverter652and enabling three-state inverter656, thus maintaining signals pHi and pLo at a logic high.

This operation continues for every rising and falling edge of the CLKINsignal and causes clock doubler600to generate the CLKOUT2signal at twice the frequency of the CLKINsignal. Since an active high pulse is generated for every transition of CLKIN, clock doubler600provides CLKOUT2at twice the frequency of CLKIN. The width of the high pulse is set by the delay through control signal generation circuit670, three-state inverter652, and NAND gate620or NAND gate630.

Since inverter chain650is shared for both the positive and negative phases of the delayed clock input, clock doubler600reduces circuit area and power consumption compared to known clock doubler circuits. Moreover the number of delay stages is reduced due to the use of NAND gates610,620, and630, reducing area and power over known designs that use inverter stages. In addition, clock doubler600has low insertion delay, since a low-to-high transition of the CLKINsignal has only two levels of logic to the CLKOUT2signal, and a high-to-low transition of the CLKINsignal has only three levels of logic to the CLKOUT2signal. Moreover the high pulse width of the CLKOUT2signal can be characterized without regard to the size of the load since control signal generation circuit670uses internal signals pHi and pLo.

Transistor660operates as a keeper transistor to keep the state node at a logic high when the circuit is disabled. Given sufficient initial time, clock doubler600will operate properly even without transistor660, as the state node will resolve itself over time to a stable value. However transistor660adds more control during the enablement phase of clock doubler600.

FIG. 7illustrates in partial block diagram and partial schematic form another clock doubler700suitable for use in clock distribution system510ofFIG. 5according to some embodiments. Clock doubler700is the same as clock doubler600ofFIG. 6except that it includes a different control signal generation circuit770. Control signal generation circuit770includes a NAND gate772, a configurable delay774, and an inverter776. NAND gate772has a first input for receiving signal pHi, a second input for receiving signal pLo, and an output. Configurable delay circuit774has an input connected to the output of NAND gate772, and an output for providing signal AC. Inverter776has an input connected to the output of configurable delay circuit774, and an output for providing signalAC. Configurable delay circuit774allows the user to generate CLKOUT2closer to an ideal 50% duty cycle, with a tradeoff of more area and power.

FIG. 8illustrates in schematic form still another clock doubler800suitable for use in clock distribution system500ofFIG. 5according to some embodiments. Clock doubler800is the same as clock doubler600ofFIG. 6except that it includes a different control signal generation circuit870. Control signal generation circuit870includes a NAND gate872and inverters874and876. NAND gate872has a first input for receiving signal pHi, a second input for receiving signal pLo, and an output. Inverter874has an input connected to the output of NAND gate872, and an output for providing signalAC. Inverter876has an input connected to the output of inverter874, and an output for providing signal AC. Clock doubler800allows approximately equal pulse widths on both the positive and negative phases of the CLKINsignal, as long as the beta ratios of inverts874and876are appropriately skewed.

FIG. 9illustrates in schematic form yet another clock doubler970suitable for use in clock distribution system510ofFIG. 5according to some embodiments. Clock doubler970is the same as clock doubler600ofFIG. 6except that it includes a different control signal generation circuit970. Control signal generation circuit970includes an inverter972having an input for receiving the CLKOUT2signal which it also provides as signal AC, and an output for providing signalAC. Clock doubler900derives the AC andACcontrol signals from the CLKOUT2signal to compensate for load differences. Thus if the CLKOUT2signal is heavily loaded by driving multiple latches or registers or, as is shown inFIG. 5, multiple clock buffers452, the delay contribution of the load is fed back through control signal generation circuit970so it can adjust its pulse width based on the load. However clock doubler900will typically be characterized along with the load circuit since the pulse width and feedback paths depend on the size of the load.

FIG. 10illustrates a flow diagram of a method1000of doubling a clock signal according to some embodiments. Action box1010includes a step of receiving a clock input signal having a first frequency. Action box1020includes a step of selectively buffering the first clock signal during a first phase of a clock output signal to form a first state signal. Action box1030includes a step of selectively inverting the first state signal during a second phase of the clock output signal to form a second state signal. Action box1040includes a step of forming a first phase clock signal in response to a logical combination of the clock input signal and the second state signal. Action box1050includes a step of forming a second phase clock signal in response to a logical combination of the first state signal and a complement of the clock input signal. Action box1060includes a step of providing the clock output signal at a second frequency twice the first frequency in response to a logical combination of the first phase clock signal and the second phase clock signal.

The circuits ofFIGS. 5-9or portions thereof may be described or represented by a computer accessible data structure in the form of a database or other data structure which can be read by a program and used, directly or indirectly, to fabricate integrated circuits with the circuits ofFIGS. 5-9. For example, this data structure may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool which may synthesize the description to produce a netlist comprising a list of gates from a synthesis library. The netlist comprises a set of gates that also represent the functionality of the hardware comprising integrated circuits with the circuits ofFIGS. 5-9. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce integrated circuits ofFIGS. 5-9. Alternatively, the database on the computer accessible storage medium may be the netlist (with or without the synthesis library) or the data set, as desired, or Graphic Data System (GDS) II data.

While particular embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, a clock doubler circuit as described herein is suitable for a variety of applications, including microprocessors, other large clocked logic circuits, programmable gate arrays, and the like. Moreover various features or enhancements can be used in various combinations to achieve a desired clock characteristics with acceptable power and circuit area tradeoffs.

Accordingly, it is intended by the appended claims to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.