Test plan generation for analog integrated circuits

A method of generating a test plan for a circuit designed with blocks of analog, digital, or mixed signal components. Each block is treated as a separate functional unit, with a test having block inputs that are set to predetermined values. A matrix of circuit equations is set up to determine what circuit inputs will result in these block inputs. The required number of equations is obtained by identifying any circuit inputs that need to be set heuristically.

TECHNICAL FIELD OF THE INVENTION 
This invention relates to testing of integrated circuits, and more 
particularly to a method for automatically generating a test plan for an 
integrated circuit having analog and mixed signal components. 
BACKGROUND OF THE INVENTION 
The number of components that can be integrated onto a semiconductor chip 
has been increasing rapidly. At the same time, the number of different 
types of integrable components has also increased. Today's integrated 
circuits (IC's) may have analog, digital, or mixed signal components or 
some combination of these types. 
Testing analog and mixed signal IC's poses problems different from those 
encountered in testing digital integrated circuits. Analog and mixed 
signal IC's deal with analog signals, and the transistors as well as other 
components may or may not operate in a linear manner. 
Analog circuit testing is generally "functional" in that it attempts to 
associate defects in the circuit with failure of the circuit to perform 
its intended function. One approach to functional testing is to 
conceptualize the circuit as a set of functional modules. This reduces the 
complexity of the test operation as compared to testing each primitive 
component of the circuit. 
When the circuit is not integrated, block functional testing is not 
especially difficult. Each block is tested separately by applying input 
signal values and measuring outputs. 
For IC's, functional testing is easily implemented in "end to end" testing 
of the entire circuit, because the circuit inputs and outputs are 
available for applying input signals and measuring outputs. However, for 
block level testing, where a block has one or more inputs or outputs that 
are not the same as the circuit inputs or outputs, test values cannot be 
physically applied to the block inputs and block outputs cannot be 
physically measured. 
One solution to block functional testing is to manually propagate block 
inputs and outputs to circuit inputs and outputs. In the past, this has 
been done manually, but for complex circuit that computational burden is 
large. Automated techniques for backward and forward propagation have also 
been described. U.S. patent Ser. No. 970,973, now abandoned entitled "A 
Method for Generating Analog Test Plans", assigned to Texas Instruments, 
Incorporated, describes a method for testing analog integrated circuits, 
using forward and backward path propagation. Test values to be applied to 
block inputs and expected values at block outputs are attempted to be 
propagated to the circuit inputs and outputs. 
Existing test plan generation methods fail to provide tests under some 
circumstances. For example, they do not provide tests that require current 
setting, ac analysis, or transient analysis. They do not provide tests for 
circuits with feedback. A need exists for a method for generating all 
types of tests for all types of analog circuits. 
SUMMARY OF THE INVENTION 
A first aspect of the invention is a method of using circuit simulation 
techniques to generate a test plan for a circuit comprised of blocks of 
analog, digital, or mixed signal components, or some combination of these 
components. The method treats each block separately, and performs an 
iterative process of attempting tests, methods of tests, and heuristic 
solutions. Accordingly, a first step is selecting a block of the circuit 
as the current block under test. Then, a first test to be performed on 
said block is selected. The test designates certain inputs that are to be 
set with predetermined test values and certain outputs that are to be 
measured and compared to expected values. The block's inputs are set by 
assigning the test values to them. To reduce the number of unknown 
variables, so that a solvable matrix can be formed, it is determined if 
any circuit inputs need to be identified and set heuristically. If so, 
these inputs are identified by using heuristic rules, and set to some 
value. A matrix of circuit equations is formed, which can be solved for 
circuit input values that will result in the test values at the block 
inputs. Now, the matrix can be solved to determine values to be applied to 
circuit inputs during testing. The matrix solution also includes expected 
circuit outputs. The test plan lists these circuit input values, and the 
circuit output(s) to be measured. 
The method of the invention provides a set of circuit input values that are 
"consistent with" block inputs, in the sense that these circuit inputs 
will result in desired block inputs. Likewise, at least one circuit output 
is provided that is consistent with an expected block output. These 
consistent values to be applied and measured at the circuit pins may be 
different from the values specified for block pins by the test model. 
A technical advantage of the invention is that it automatically generates 
tests for linear and non-linear analog sub-circuits within an integrated 
circuit. It can be used with various types of functional tests, including 
DC, AC, and transient response analysis. On the average, the generation of 
the test plan takes less time than previous automated methods. This is at 
least in part due to the use of functional block models as a basis for 
test plan generation, rather than transistor level models. It generates 
tests that could not be generated with previous methods, such as those 
that have current values to be set at block inputs.

DETAILED DESCRIPTION OF THE INVENTION 
I. Test Plan Generation 
FIG. 1 illustrates the basic steps of the process of generating a test 
program in accordance with the invention. Each of the steps of FIG. 1 will 
be explained in general terms in this Part I. In Part II, the same steps 
are described in terms of a simple example circuit. 
As is evident from the following description, this method may be 
implemented with a test generator program for a computer, which accesses 
certain pre-defined data files and libraries and generates a test plan. 
Many of the circuit descriptions, functional models, and test models used 
as input for the test plan generator can be derived from existing 
libraries in the form of computer databases. Various parsing routines can 
be used to adapt data in these libraries to the syntax of the test plan 
generator. 
In general, the method applies to an analog or partly analog modular 
circuit, in which sub-circuits are defined in terms of functional blocks. 
For implementation of the computer-based method, a circuit description, a 
set of functional models for its blocks, and a set of test models for 
these blocks are input to a test plan generator. Block by block, the 
functional and test models are used to determine the relationship between 
known inputs and expected outputs for each block. For each block, the test 
plan generator determines what values should be applied to the circuit 
inputs to produce those block inputs, as well as the value at the circuit 
output that will result from the block output. In other words, the circuit 
inputs will result in the values listed in the test model at the block 
inputs. In this manner, the test plan generator produces a set of 
consistent circuit values to be applied and measured at the circuit level 
when the block is under test. The calculation of the circuit values is 
done by means of circuit simulation, using a matrix of circuit equations. 
The result is a test plan, in which known circuit inputs can be applied to 
an IC, and the resulting outputs compared to expected results for the 
circuit. 
In accordance with the preceding overview, it is assumed that the circuit 
to be tested has a modular design, in which each module can be described 
with a high level functional model. These-modules are referred to herein 
as "blocks". The functional models can be derived or are available from 
electronic design software packages. 
As indicated in step 11, the IC under test is expressed in terms of a 
schematic description, interpretable by computer. Known methods of 
generating such a description may be used, such as schematic capture 
software, circuit synthesis software, or hardware description languages. 
The circuit is expressed in terms of "blocks". One block is the "circuit 
block" which represents the entire circuit. Other blocks represent 
sub-circuits. Each sub-circuit block identifies its own block inputs and 
block outputs, so that circuit simulation can be performed with test 
voltages and currents set at block inputs. As explained below, the circuit 
simulation is in the form of a matrix of equations representing the 
circuit and the unknown currents and voltages in the circuit. The matrix 
is solved for these unknown values. 
For purposes of this description, block input and output nodes, as well as 
those of the circuit, are referred to as "pins". It should be understood, 
however, that although all pins of the circuit are physically accessible, 
those of the blocks may be either internal or the same as those of the 
circuit. 
In step 12, each block of the circuit is described with a functional model 
of its operation, which describes the behavior of the block across its 
inputs and outputs. The functional models are independent of the block 
under test, in the sense that two blocks in the circuit that are 
internally the same, i.e., have the same type of components, will have the 
same functional model with different values to be associated with the 
model's parameters. For example, two resistors would have the same 
functional model, but can have different resistance values. Or, as another 
example, all operational amplifiers (op amps) in a circuit might have 
similar input versus output characteristics, but can have different CMRR, 
open loop gain, etc., parameters. 
The functional models may be created using techniques known in the art of 
electronic circuit analysis. They will generally be a set of mathematical 
parameters and equations describing the characteristics of the block. For 
example, the Shockly equation might be used to describe the operation of a 
diode. For use with a computer as in the invention, known modeling 
languages can be used. Examples of commercially available models are those 
provided by the SPICE circuit simulation program or written in the MAST 
analog behavioral description language used for the SABER simulator. 
Typically, the functional models for the blocks of a particular circuit 
will be already stored in a library of functional models. Thus, in 
practice, step 12 will be implemented by accessing this library and 
parsing the data to form a functional model data structure for each block. 
In step 13, a test model for each block of the circuit is created. A 
block's test model gives information about the tests that may be performed 
on that block. As is the case for functional models, any two or more 
identical blocks will have the same test model. These test models assume 
that the block is a stand-alone circuit, with all inputs and outputs 
accessible for application of test voltages and currents. 
Depending on the type of block, its test model might have more than one 
test. Furthermore, each test might have more than one method. Within each 
method, certain block parameters are "set values" and other parameters are 
"measured values". The set values are set by assigning them specific 
voltage or current values. The measured values represent values that would 
be measured while the block is operating. The measured values are compared 
to an expected output value, or used to calculate some other value that is 
compared to an expected output value. If comparison is favorable, the 
block can be assumed to be operating correctly. The test type may be dc, 
ac, or transient. For ac tests, the test method may also specify frequency 
values. 
As with the functional models, the test models are parsed or otherwise 
processed to create a test model data structure for each block. 
Step 14 is creating a set of rules for heuristically determining whether 
any circuit inputs are to be identified and set during the generation of 
the test for each block in the circuit. If there are such circuit inputs, 
they are identified and set. This step ensures that sufficient equations 
are available for solving a circuit matrix. Details of this step are 
discussed below in connection with FIG. 2. 
In step 15, the test plan generator performs an iterative, block-by-block, 
test generation process. determines how to relate the tests for each block 
to the actual input and output pins of the circuit. Paths from the 
non-heuristically identified circuit inputs to block inputs that are to be 
set with test values are identified. Also, a path from the block output 
that is to be measured for a test output is identified. If there are mixed 
signal blocks in the paths, appropriate pins are identified and set. 
Details of this step, in which each block has different variables for 
simulating the circuit with a different matrix, are explained below in 
connection with FIG. 2. 
In step 16, the output of the test plan generator is a set of tests for 
each block in the circuit that has analog or mixed signals. Each test 
lists the current, voltage and frequency values to be set, as well as 
values to be measured, at circuit pins. This test plan can be converted to 
a test program specific to available test equipment. 
Referring now to FIG. 2, the process of generating the test plan is 
iterative, such that each block of the circuit under test is separately 
analyzed. For each block, different tests, as well as different methods 
within each test, may be attempted. 
The process of FIG. 2 may be implemented with a computer program to be run 
on any computer processing device. It is assumed that the computer program 
is ready with the data structures discussed above in connection with FIG. 
1, in particular, a circuit description, a set of functional models, and a 
set of test models. 
In step 21, a first block of the circuit is selected from the circuit 
description for analysis. Because the method of this invention is designed 
for analog testing, blocks that have completely digital inputs and outputs 
are not considered. However, mixed signal blocks can be tested insofar as 
digital inputs and outputs will be assigned high or low voltage values. 
In step 22a, a first test for that block is selected. In step 22b, a method 
from that test is selected. 
In step 23, the test model is used to provide a set of test input values 
for the block under test. These values are assigned to appropriate block 
input nodes. 
The block inputs to which the test values are assigned may or may not be 
directly accessible by means of the inputs and outputs of the IC. In other 
words, if the block is "internal" one or more of its block inputs or 
outputs will not be the same as the circuit input or output pins. Often, 
the number of circuit inputs and outputs exceeds the number of block 
inputs and outputs. For a given set of block inputs, consistent values at 
circuit inputs can be calculated by means of the matrix calculation of 
steps 27a -27c. However, because there are usually more circuit pins than 
block pins, some pins must be set before the matrix can be solved. A 
feature of the invention is that these pins are heuristically identified 
to provide the best circuit simulation. 
Also, as part of step 23, circuit power pins are identified and set. Values 
for these pins can be provided by the circuit database. 
In step 24, circuit paths are "sensitized" for simulation purposes. For 
this, each measured value from the test model is assigned to an 
appropriate output node and a path to a circuit output selected. A list of 
all circuit outputs connected to the block output is generated, i.e., an 
"output pin list". 
A feature of the invention is that paths containing mixed signal blocks may 
also be sensitized. It is necessary to find any mixed signal blocks in the 
path to a circuit pin and to set certain pins of the mixed signal block so 
that a circuit simulation can be performed. More specifically, to select a 
path, step 24 operates on each pin of the block under test. If the pin is 
a circuit input, no further action is taken. If the pin is a circuit 
output, it is included in the output pin list. 
If the block pin is not a circuit pin, all blocks connected to it are 
identified. Then, for each of these blocks, it is determined whether any 
pin of that block is a "control" type pin, and if so, the block is 
identified as a mixed signal block. If this pin is an output pin, any one 
input pin and this output pin will be activated. If this pin is an input 
pin, any one output pin and this input pin are sensitized. If any 
sensitized pin is a circuit pin, step 24 stops here. If no pin of the 
block is a control type pin, the block is not a mixed signal block, and if 
its connected pin is a circuit output, that output is included in the 
output pin list. 
For each input pin of the block under test, the above routine is performed 
once for each block output. For each output pin of the block under test, 
the function is called once for each block input. Appendix A is an example 
of an implementation of step 24. 
As a result of step 24, all circuit outputs connected to the block under 
test through purely analog blocks are to be measured. In this case, the 
output pin list will contain all circuit outputs. For any mixed signal 
block in the circuit, only a particular path through that block is 
activated and is of importance for measuring an output value. 
Step 25 applies if there are mixed signal blocks in any path to or from the 
block under test to the circuit inputs or outputs, as determined in step 
24. If so, high or low values are set on digital pins, such that the path 
will be active during simulation. Appendix B describes a sensitivity test 
that may be used as part of step 25. 
Step 26 is heuristically determining which, if any, circuit pins are to be 
set prior to the matrix solution. To determine if there are such circuit 
pins, the number of block inputs that will have set values, m, is 
subtracted from the number of circuit inputs, n. The difference is the 
number of circuit pins that are to be heuristically set. The number of set 
values, m, will be the total of block inputs set during step 24, whether 
by the test model or during power pin setting. 
Once it is determined that one or more circuit pins are to be heuristically 
set, various approaches may be used for identifying them. One approach is 
a "distance" approach that involves finding distances between each circuit 
pin and the block under test. The farthest away circuit pin is to be set. 
The following are exemplary rules for these distance heuristics: 
1. The distance across any two pins of a block not under test is equal to 
the number of pins of that block. 
2. The distance across any two pins of the block under test is 1. 
3. The primary inputs of the block under test are excluded. 
4. The inputs of the blocks following the block under test are preferred to 
be excluded. 
A more detailed discussed of an algorithm for these heuristics is set out 
in Part III below. 
The heuristically identified circuit pin(s) are then assigned an input 
value. Where, as is the case in this description, KCL equations are used 
for the matrix, this value will represent an input voltage. The value to 
which a heuristically determined input is set can be any value within the 
range of the input pin. This range may be specified, such as in the test 
block model or elsewhere. For example, if the range is -4.5 volts to 4.5 
volts, the voltage may be set anywhere within that range, including 0. 
As a result of step 26, a number of heuristic circuit pins have set values. 
The remaining circuit pins are those that will receive values set by a 
matrix calculation. This permits formation of a sufficient number of 
circuit equations to feasibly be solved, i.e., the number of unknowns does 
not exceed the number of equations. 
Step 26 may be used to heuristically identify and set either circuit inputs 
or outputs. For example, if an output is farthest from the block it may be 
assigned a value for purposes of matrix solution. However, for purposes of 
test plan generation, if this is to be a measured output, it will be 
designated as a value to be measured rather than set. 
In step 27a, a matrix of equations for solving the circuit is formed. In 
general, the matrix resembles a conventional circuit simulation matrix. 
However, the variables for which it is solved are different from those of 
conventional simulation. Some known variables are set heuristically and 
others are represented in the matrix by block inputs. By solving the 
matrix, consistent circuit input values that will result in the desired 
test input values at the block under test are calculated. 
For forming the matrix, KCL equations are extracted from a circuit graph of 
paths and nodes. These equations are stored in the form of a matrix. Each 
row of the matrix corresponds to a node and each column corresponds to a 
path, as described by the circuit graph. Matrix entries can be -1, 0, or 
1. If the path is not connected to the node, the entry is 0. If current on 
the path is entering the node, the entry is 1. If current on the path is 
leaving the node, the entry is -1. A KCL equation is available for each 
node that is not a circuit input or ground pin. Additional equations are 
supplied by the functional models for the blocks. 
Mathematically speaking, a system of n equations, having n unknowns, is 
formed. As described in step 26, when there is a fewer number of available 
equations than circuit unknowns, some unknowns are set heuristically so 
that the number of unknowns is the same as the number of available 
equations. Thus, the number of equations in the matrix is the sum of the 
number of KCL equations plus a number of equations derived from blocks of 
the circuit. 
In step 27b, the matrix is attempted to be solved. The techniques used to 
solve the matrix include traditional numerical methods. Appendix C 
describes a solution routine in detail. In general, a column matrix, 
G(x(k)), is set up, and its derivative square matrix, J, is calculated. 
During each iteration of a Newton-Raphson procedure, the G matrix and J 
matrix are updated by solving the functional model of the block under 
test. 
If the matrix is not able to be solved, step 26 is repeated with different 
heuristic rules or different heuristically derived pins or with different 
values on the same heuristically derived pins. Step 27a is repeated to 
form a new matrix, and step 27b is repeated to attempt to solve it. If the 
program is unable to create any test for the block, it outputs a message 
to the user so that design engineers can redesign the circuit to make it 
testable. 
Step 28 is performed when step 27b results in a solution to the matrix. The 
solution of the matrix provides circuit input values that are consistent 
with the block input values provided by the block test model. It also 
provides at least one circuit output value consistent with the expected 
block output value provided by the test model. In other words, because the 
block voltages, circuit voltages, and all currents in the circuit block, 
form a part of the circuit matrix, all these values become determined. The 
test method, with the measured circuit output(s) and with the circuit 
inputs heuristically set in step 26 or calculated in step 27b, is added to 
the test plan. 
In step 29a, it is determined whether another test method remains to be 
tried for the block. If so, steps 23-28 can be repeated for that method. 
Step 29a is optional, in the sense that if one test method is successful, 
it may be expedient to immediately go to step 29b to determine if there 
are additional tests for the block, or to step 29c to determine if there 
are additional blocks to be tested. 
The above-described process is especially useful for analog and mixed 
signal integrated circuits. If the circuit has digital blocks, they can be 
masked during test generation. Also, the method could be used for 
functional testing of digital blocks, where instead of logic decisions, 
high and low voltages are set and measured. 
II. Example Circuit for Test Plan Generation 
FIG. 3 is a schematic diagram of a simple circuit, for which a test plan 
may be generated in accordance with the invention. It is referred to 
herein as a "cascaded op amp" circuit, comprised of two operational 
amplifiers with feedback and input resistors. 
In accordance with step 11 of FIG. 1, the circuit is described in terms of 
a circuit block, CASCADE, and two internal blocks, RESISTOR and OP AMP. 
The internal blocks correspond to functional models that are available for 
op amps and resistors. Using these blocks, the circuit description could 
be: 
__________________________________________________________________________ 
BLOCK CASCADE; 
IN1 @ (INPUT); 
IN2 @ (INPUT); 
IN3 @ (INPUT); 
OUT2 @ (OUTPUT); 
GND @ (INOUT); 
STRUCTURE 
RES1 : Resistor 
IN1, IN.sub.-- MINUS; 
OPAMP : Op amp IN.sub.-- MINUS; IN2; OUT; GND; 
RES2 : Resistor 
IN.sub.-- MINUS; OUT; 
RES3 : Resistor 
OUT; IN.sub.-- MINUS; 
OPAMP2 : Op amp IN.sub.-- MINUS2; IN3; OUT2; GND; 
RES4 : Resistor 
IN.sub.-- MINUS2; OUT2; 
END CASCADE; 
BLOCK RESISTOR; 
A @ (INPUT); 
B @ (OUTPUT); 
END RESISTOR; 
BLOCK OPAMP; 
A @ (INPUT); 
B @ (INPUT); 
C @ (OUTPUT); 
GND @ (INOUT); 
END OPAMP; 
__________________________________________________________________________ 
FIG. 4 is an equivalent directional graph of the circuit of FIG. 3, which 
better illustrates its paths and nodes. The circuit has 6 paths and 8 
nodes. Each node is labeled in FIG. 4 with both a variable name and a 
numerical identifier. 
In accordance with step 12 of FIG. 1, each different type of block is 
associated with a functional model. Thus, the resistor blocks will have 
the same functional model, as will the op amp blocks. 
This example makes use of models available from the commercially available 
SABER-MAST set of electrical models. For the op amp blocks, where the 
inputs are at nodes A and B and the output at node C, the model is 
expressed as: 
______________________________________ 
element template opamp A B C GND = gain, voo 
electrical A, B, C, GND 
number gain 
number voo 
val v Vout, Vin 
var i i1 
number tmp 
values { 
Vout = v(C) 
Vin = v(B) - v(A) 
} 
equations { 
i(C) += i1 
i1 : Vout = gain * Vin 
} 
} 
A model for the resistors is: 
template resistor A B = r 
electrical A, B 
number r 
{ 
val v v1, v2 
val i i1 
values { 
v1 = v(A) 
v2 = v(B) 
i1 = (v1 - v2) / r 
} 
equations { 
i (A -&gt; B) += i1 
} 
} 
______________________________________ 
In accordance with step 13 of FIG. 1, test models for each type of block 
are derived. For the op amp blocks, there are two tests, one for output 
voltage, Voo, and one for gain: 
______________________________________ 
OPAMP ( ) { 
TEST VOO { 
TEST.sub.-- TYPE = DC; 
METHOD 1 { 
MTYPE = CHAR; 
ACCESS { C } 
CONTROL { A, B } 
PROCEDURE { 
SET vB = 0 V; 
SET vA = 0 V; 
MEAS vC; 
ASSIGN vO = vC V; 
COME (vO = voo.sub.-- nom ); 
} 
} ENDT TEST.sub.-- VOO 
TEST GAIN { 
TEST.sub.-- TYPE = DC; 
METHOD 1 { 
MTYPE = CHAR; 
ACCESS { C } 
CONTROL { A,B } 
PROCEDURE { 
ASSIGN v1 = (vstart + (vend)) / 2V; 
SET vA = v1 V; 
SET vB = v1 V; 
MEAS vC; 
ASSIGN v2 = vC V; 
SET vB = v1 V; 
ASSIGN v4 = (( (vstart) + (vend) ) 
/ 2) + 0.0001 V; 
SET vA = v4 V; 
MEAS vC; 
ASSIGN v3 = vC V; 
ASSIGN g1 = (v3 - v2) / 0.0001 V; 
COME (g1 = gain.sub.-- nom); 
} 
} 
} ENDT TEST.sub.-- GAIN; 
} ENDF OPAMP; 
The test model for the resistors is: 
RESISTOR ( ) { 
TEST R { 
TEST.sub.-- TYPE = DC; 
METHOD 1 { 
MTYPE = PROD; 
ACCESS { A } 
CONTROL { B } 
PROCEDURE { 
SET vA = 2V; 
SET vB = 0V; 
MEAS iA; 
ASSIGN rval = 1/iA; 
COME (rval = r.sub.-- nom); 
} 
} 
} ENDT TEST.sub.-- R 
TEST RCURR { 
TEST.sub.-- TYPE = DC; 
METHOD 1 { 
MTYPE = PROD; 
ACCESS { A } 
CONTROL { B } 
PROCEDURE { 
SET vA = 2V; 
SET iA = 0.1A; 
MEAS vB; 
} 
} 
} ENDT TEST.sub.-- RCURR; 
}ENDF RESISTOR; 
______________________________________ 
At this point, the inputs for the test plan generator, as illustrated in 
FIG. 1, are complete. Referring now to FIG. 2, each block of the cascaded 
op amp circuit is separately processed to obtain a test plan for that 
block. 
The following description assumes that the block currently being processed 
is the RES1 block of FIG. 3. Thus, in accordance with step 21 of FIG. 2, 
the selected block is RES1. 
In step 22a, a first test for the resistor is selected for consideration. 
This is the R test of the resistor test model described above. It has only 
one method, and step is selecting that method. 
In step 23, the values to the block nodes are set in accordance with the 
test model. Thus, IN1, which corresponds to node A of RES1 is set to 2 
volts. IN.sub.-- MINUS, which corresponds to node B of RES1, is set to 0 
volts. 
In step 24, a path is traced from the block output to a circuit output. 
This identifies OUT2 as a node at which a circuit measurement will be made 
during testing. Also, GND is identified as a power pin and set to 0. 
Step 25 is forming the matrix for the circuit. There are four nodes other 
than circuit input nodes. Referring to FIG. 4, these nodes are OUT2, 
IN.sub.-- MINUS, OUT, and IN.sub.-- MINUS2. The KCL equations for these 
nodes, where imn represents the current, i, between nodes m and n, are: 
______________________________________ 
At OUT2 i73 - i34 = 0 
At IN.sub.-- MINUS 
i05 - i56 = 0 
At OUT i56 - i64 - i67 
= 0 
At IN.sub.-- MINUS2 
i67 - i73 = 0 
______________________________________ 
The KCL matrix for these equations is set up such that each row represents 
a KCL at a different node. Each column represents a path. Thus, where node 
4 (GND) is set at 0 volts: 
______________________________________ 
node 3 000 000 001 -001 000 000 
node 5 -001 000 000 000 001 000 
node 6 000 001 000 000 -001 001 
node 7 000 000 000 001 000 -001 
______________________________________ 
An additional 8 equations are available to represent circuit blocks. 
Referring to the functional models set out above, each resistor 
contributes one equation, and each op amp contributes two. Thus: 
______________________________________ 
RES1 -&gt; i15 = (v0 - v5) / res1 
RES2 -&gt; i56 = (v5 - v6) / res2 
RES3 -&gt; i67 = (v6 - v7) / res3 
RES4 -&gt; i73 = (v7 - v3) / res4 
OPAMP1 -&gt; v6 = (v0 - v1) * gain1 
i64 = i1 (of op amp 1) 
OPAMP2 -&gt; v3 = (v7 - v2) * gain2 
i34 = i1 (of op amp 2) 
______________________________________ 
Thus, the total number of available equations is 12. However, the number of 
unknown variables is 13: i05, i56, i64, i67, i73, i34, v1, v2, v6, v7, v3, 
i1 (op amp 1), i1 (op amp 2). 
Step 26 begins with determining how many values are to be set 
heuristically. For this determination, the number of nodes with set values 
is subtracted from the number of circuit inputs. In this example, there 
are 4 circuit inputs and 3 set values. (As indicated above, the node GND 
is considered a circuit input and its value is set by default to 0). Thus, 
one value needs to be set heuristically. 
Step 26 also involves identifying each node to be set. Using distance 
heuristics, the distances between the input to RES1 and other circuit 
inputs are calculated. Node 2 (IN3) has a distance of 9 units from RES1. 
Node 1 (IN2) has a distance of 3 units. Thus, node 2 is the farthest node 
from the block under test. It is set to an arbitrary value, such as 0. The 
remaining circuit inputs (IN2) is matched to a block inputs. Thus, the 
value to be solved for is IN2, which will provide an input signal to be 
applied during testing so that 0 volts will appear at IN.sub.-- MINUS. 
There are now 12 unknown variables and 12 matrix equations. The matrix may 
now be solved. 
The result of steps 22-28 is a test plan for the block. Appendix D is a 
test plan generated for the example circuit. As indicated, for each test, 
the plan lists provides input values for the IN1, IN2, IN3, and GND. It 
also provides an expected value for the circuit output, OUT2. During 
testing, each test is performed and OUT2 measured. The measured value is 
then compared to the expected output value. 
III. Distance Heuristics 
One method for identifying circuit pins that should be set heuristically is 
to form a D matrix. This matrix has dimension x by x, where x is the 
number of nodes in the circuit. 
The elements of the D matrix are filled with infinity values, i.e., very 
large numbers. Then, the D matrix is weighted such that 
EQU D=[d (i,j)] 
, where 
d (i,j )=complexity of the block through which nodes i and j are connected 
d(i,i)=0. 
In other words, if the complexity of the block at (i,j) is less that 
infinity, that number is used instead of infinity. 
Then, for each pair of pins of the block under test, zeros are entered for 
the corresponding element in D. As a result, all nodes around the block 
are "fused" together as a single block node. Then, the shortest path from 
this "fused" node to each node that is a circuit pin is calculated. An 
algorithm known as Dijkstra's algorithm may be used for this calculation. 
The result is a list of distances from the block to each circuit pin, from 
which the longest distance may be selected. 
Other Embodiments 
Although the invention has been described with reference to specific 
embodiments, this description is not meant to be construed in a limiting 
sense. Various modifications of the disclosed embodiments, as well as 
alternative embodiments, will be apparent to persons skilled in the art. 
It is, therefore, contemplated that the appended claims will cover all 
modifications that fall within the true scope of the invention. 
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