Semiconductor integrated circuit

Voltage transfer switches and voltage input/output circuits are provided on a complementary bus line pair to be shared among a plurality of columns of a memory cell array. After a complementary bit line pair is precharged to a predetermined voltage, the voltage of uninverted bit line and the voltage of inverted bit line are exchanged before any of all memory cells belonging to the same column is selected by a word line. With this structure, a predetermined potential difference is ensured between the complementary bit line pair at the time of an activation of a sense amplifier even if the total sum of the off-leak currents of access transistors in all the memory cells belonging to the same column is almost as large as the ON-current (drive current) of a single drive transistor.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119(a) on Japanese Patent Application No. 2004-161539 filed on May 31, 2004, the entire contents of the specification, drawings and claims of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuit and specifically to a circuit technique for preventing a malfunction caused due to an off-leak current of a transistor.

SRAM (static random access memory) has been known as a conventional semiconductor integrated circuit. An SRAM includes numerous memory cells. Each memory cell includes, for example, first and second access transistors (N-channel MOS transistors), first and second drive transistors (N-channel MOS transistors), and first and second load transistors (P-channel MOS transistors). The drain of the first drive transistor is connected to one of a pair of bit lines through the first access transistor. The drain of the second drive transistor is connected to the other one of the pair of bit lines through the second access transistor. Each bit line is precharged to a predetermined voltage before read/write cycles.

In recent years, the threshold voltage of the transistor has been decreasing along with the advancement of miniaturization of the semiconductor process. As a result, the influence of the off-leak currents of the access transistors in the SRAM has been significantly increasing. If the total sum of off-leak currents of access transistors of a plurality of memory cells included in the same column (bit line leak current) is increased to be equivalent to an ON-current (drive current) flowing in a drive transistor in a single memory cell which is selected in a read operation in the same column, a desired potential difference cannot be secured between the bit line pair. As a result, there is a possibility that a malfunction occurs in a memory read operation. Further, the off-leak currents of the access transistors change depending on the cell data, temperature, or the like.

In order to solve this problem, K. Agawa et al., “A Bit-Line Leakage Compensation Scheme for Low-Voltage SRAM's”, IEEE 2000 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 70–71, discloses a technique wherein the magnitude of the leak current is detected for each bit line in a precharge period of a bit line pair, and in read/write cycles, a compensation current which has the same magnitude as that of the detected bit line leak current is injected to each bit line. However, this conventional technique causes an increase in power consumption due to injection of the compensation current into the bit lines.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a semiconductor integrated circuit including two signal lines and a plurality of transistors, the drains of which are connected to one of the signal lines, wherein the influence of off-leak currents of the transistors is alleviated without causing an increase in power consumption.

In order to achieve this objective, according to the present invention, the precharge voltage is adjusted in advance of an actual operation of the transistors, whereby leak compensation is attained.

Specifically, a semiconductor integrated circuit of the present invention comprises: first and second signal lines; a plurality of transistors, each of which has a drain connected to the first signal line; a precharge circuit for precharging the first and second signal lines to a first voltage; voltage adjustment means for adjusting, when the voltage of the first signal line changes to a second voltage due to off-leak currents of the plurality of transistors after completion of the precharge, the voltage of the second signal line to the second voltage before an actual operation of any of the plurality of transistors; and a differential amplification circuit for amplifying a potential difference between the first and second signal lines at the time of an actual operation of any of the plurality of transistors.

With the above structure, the precharge voltage of the second signal line is adjusted according to a variation in voltage of the first signal line due to leakage. Thus, leak compensation is attained even if off-leak currents of transistors change depending on the temperature, or the like.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, semiconductor memories, which are embodiments of a semiconductor integrated circuit of the present invention, are described with reference to the drawings. It should be noted that a large part of the description of the circuit as to data writing is omitted.

FIG. 1shows a structure of a semiconductor integrated circuit according to the first embodiment of the present invention. It is assumed herein that a large number of tri-state buffers are connected to a bus line which is a common signal line.

Although the semiconductor integrated circuit ofFIG. 1includes a large number of memory macros, only two of the macros, memory macros101and102, are shown for simplicity of illustration. The first memory macro101is connected to a common bus line121through a first tri-state buffer111. The second memory macro102is connected to the common bus line121through a second tri-state buffer112. VDD is the supply voltage, and VSS is the ground voltage.

The first tri-state buffer111includes a P-channel MOS drive transistor11, an N-channel MOS drive transistor12, inverter circuits13and16, a P-channel MOS switching transistor14and an N-channel MOS switching transistor15. The gate of the N-channel MOS drive transistor12is supplied with first output enable signal OE1. The gate of the P-channel MOS drive transistor11is supplied with an inverted signal of first output enable signal OE1. The gates of the switching transistors14and15are supplied with an inverted signal of first data signal DA supplied from the first memory macro101. The drain of the P-channel MOS drive transistor11is connected to the bus line121through the P-channel MOS switching transistor14. The drain of the N-channel MOS drive transistor12is connected to the bus line121through the N-channel MOS switching transistor15. The source of the P-channel MOS drive transistor11is connected to supply voltage VDD. The source of the N-channel MOS drive transistor12is connected to ground voltage VSS. Thus, when first output enable signal OE1is at L-level, the output of the first tri-state buffer111exhibits a high impedance state. When first output enable signal OE1is at H-level and first data signal DA is at H-level (DA=1), the P-channel MOS drive transistor11drives the bus line121to H-level. When first output enable signal OE1is at H-level and first data signal DA is at L-level (DA=0), the N-channel MOS drive transistor12drives the bus line121to L-level.

All of the other tri-state buffers, including the second tri-state buffer112, have the same internal structure as that of the first tri-state buffer111. InFIG. 1, OE2is a second output enable signal, and DB is a second data signal supplied from the second memory macro102.

Reference numeral122denotes a dummy bus line. The dummy bus line122has a line capacitance substantially equal to that of the bus line121. It should be noted that none of the tri-state buffers is connected to the dummy bus line122.

The semiconductor integrated circuit ofFIG. 1further includes a precharge circuit130, a sense amplifier140, a voltage input/output circuit (VIO)150, a voltage transfer switch160and an output buffer170. InFIG. 1, VBUS is the voltage of the bus line121, and VDBUS is the voltage of the dummy bus line122.

When precharge signal PCG is at L-level, the precharge circuit130precharges the bus line121and the dummy bus line122to a voltage which is just an intermediate level between supply voltage VDD and ground voltage VSS (VDD/2). When switch control signal VSW is at H-level, the precharge circuit130precharges only the bus line121to intermediate level voltage VDD/2.

The voltage input/output circuit150takes in input voltage VIN and outputs voltage VOUT which is equal to input voltage VIN. Bias setting voltage Vset, which is slightly lower than supply voltage VDD, is supplied to the voltage input/output circuit150.

When switch control signal VSW is at L-level, the voltage transfer switch160supplies voltage VBUS of the bus line121to the voltage input/output circuit150as input voltage VIN. Thereafter, when switch control signal VSW rises to H-level, the voltage transfer switch160supplies output voltage VOUT of the voltage input/output circuit150to the dummy bus line122.

The sense amplifier140is a differential amplification circuit. When sense amplifier enable signal SAE is at H-level, the sense amplifier140drives the voltages of the bus line121and the dummy bus line122such that the higher one of the voltages is driven to supply voltage VDD and the lower one is driven to ground voltage VSS, thereby amplifying the potential difference between the bus line121and the dummy bus line122.

The output buffer170outputs voltage VBUS of the bus line121, which has been amplified by the sense amplifier140, as data output signal DOUT.

FIG. 2shows the input/output characteristic of the voltage input/output circuit150ofFIG. 1. As illustrated by a solid line inFIG. 2, the input/output characteristic is linear when input voltage VIN has a value near intermediate level voltage VDD/2.

FIG. 3shows exemplary signal waveforms in the semiconductor integrated circuit ofFIG. 1. InFIG. 3, R1is the first read cycle, and R2is the second read cycle. It is assumed herein that, in first read cycle R1, data of “0” (DA=0) is output from the first memory macro101, and in second read cycle R2, data of “1” (DB=1) is output from the second memory macro102. It is also assumed that, in all the tri-state buffers111and112, the off-leak currents of the P-channel MOS drive transistors11are small, whereas the off-leak currents of the N-channel MOS drive transistors12are large.

In the first place, first read cycle R1is described. Periods T1to T3are preparation periods, and periods T4and T5are actual read periods.

In period T1, precharge signal PCG is lowered to L-level while output enable signals OE1and OE2of all the tri-state buffers111and112are kept at L-level, and switch control signal VSW is kept at L-level. In the meantime, the precharge circuit130precharges both the bus line121, which has been charged to supply voltage VDD, and the dummy bus line122, which has been discharged to ground voltage VSS, to intermediate level voltage VDD/2.

In period T2, precharge signal PCG is restored to H-level, whereby the operation of the precharge circuit130is stopped. After the precharge is stopped, voltage VBUS of the bus line121gradually decreases because of the off-leak currents of the N-channel MOS drive transistors12in all the tri-state buffers111and112. In the meantime, the voltage transfer switch160continues to supply voltage VBUS of the bus line121to the voltage input/output circuit150as input voltage VIN. On the other hand, voltage VDBUS of the dummy bus line122scarcely changes.

In period T3, switch control signal VSW is pulled up to H-level. In response to this, the voltage transfer switch160is switched from the input side to output side of the voltage input/output circuit150, such that output voltage VOUT of the voltage input/output circuit150is supplied to the dummy bus line122. In the meantime, the precharge circuit130receives an inverted signal of switch control signal VSW to again precharge only the former of the bus line121and the dummy bus line122to intermediate level voltage VDD/2. As a result, the relationship between voltage VBUS of the bus line121and voltage VDBUS of the dummy bus line122at the end of period T2is inverted before the end of period T3. That is, the precharge voltage of the dummy bus line122is adjusted to a voltage in which the total sum of the off-leak currents of the N-channel MOS drive transistors12of all the tri-state buffers111and112which are in a high impedance output state is reflected.

In period T4, switch control signal VSW is restored to L-level, whereby the voltage transfer switch160is switched to the input side of the voltage input/output circuit150, and the operation of the precharge circuit130is stopped. At the same time, first output enable signal OE1is pulled to H-level, such that the first tri-state buffer111performs an active output operation according to data signal DA of the first memory macro101. Because of “DA=0” as described above, the N-channel MOS switching transistor15in the first tri-state buffer111is turned on. Since output enable signal OE1is at H-level, the N-channel MOS drive transistor12in the first tri-state buffer111is also on. Thus, the first tri-state buffer111performs the L-level output operation. Therefore, voltage VBUS of the bus line121is driven toward L-level by the N-channel MOS drive transistor12of the first tri-state buffer111. On this occasion, the off-leak currents of the N-channel MOS drive transistors12of all the other tri-state buffers including the second tri-state buffer112help a rapid decrease of voltage VBUS of the bus line121. Thus, at the end of period T4, voltage VBUS of the bus line121is lower than voltage VDBUS of the dummy bus line122, and the potential difference between the bus line121and the dummy bus line122exceeds a difference necessary for the operation of the sense amplifier140.

In period T5, sense amplifier enable signal SAE is pulled to H-level, whereby the sense amplifier140is activated. As a result, voltage VBUS of the bus line121is amplified to ground voltage VSS, and voltage VDBUS of the dummy bus line122is amplified to supply voltage VDD. Voltage VBUS of the bus line121which is obtained in period T5is output as data output signal DOUT (=0) through the output buffer170.

The operation during periods T1to T3of second read cycle R2is the same as that of first read cycle R1. At the end of period T3, voltage VDBUS of the dummy bus line122is lower than voltage VBUS of the bus line121.

In period T4of second read cycle R2, second output enable signal OE2is pulled to H-level, such that the second tri-state buffer112performs an active output operation according to data signal DB of the second memory macro102. Because of “DB=1” as described above, the P-channel MOS switching transistor14in the second tri-state buffer112is turned on. Since output enable signal OE2is at H-level, the P-channel MOS drive transistor11in the second tri-state buffer112is also on. Thus, the second tri-state buffer112performs the H-level output operation. Therefore, voltage VBUS of the bus line121is driven toward H-level by the P-channel MOS drive transistor11. On this occasion, even if the total sum of the off-leak currents of the N-channel MOS drive transistors12in all the tri-state buffers111and112is almost as large as the ON-current (drive current) of the P-channel MOS drive transistor11in the second tri-state buffer112, occurrence of a predetermined potential difference between the bus line121and the dummy bus line122at the start of next period T5is ensured because voltage VDBUS of the dummy bus line122has been lowered in advance in period T3.

In next period T5, sense amplifier enable signal SAE is pulled to H-level, whereby the sense amplifier140is activated. As a result, voltage VBUS of the bus line121is amplified to supply voltage VDD, and voltage VDBUS of the dummy bus line122is amplified to ground voltage VSS. Voltage VBUS of the bus line121which is obtained in period T5is output as data output signal DOUT (=1) through the output buffer170.

The length of time from a halt of re-precharging by pulling down switch control signal VSW to activation of the sense amplifier140(period T4) is preferably set to equal the length of time in which a variation in voltage of the bus line121due to the off-leak currents of the N-channel MOS drive transistors12in all the tri-state buffers111and112before the voltage adjustment of the dummy bus line122is allowed (period T2).

FIG. 4shows a structure of a semiconductor integrated circuit according to the second embodiment of the present invention. The semiconductor integrated circuit ofFIG. 4has an SRAM memory cell array200including m+1rows and n+1columns where m and n are integers equal to or greater than 1. It should be noted that, for simplicity of illustration, only four memory cells201,202,203and204, each having the above-described 6-transistor structure, are shown. The first and second memory cells201and202are connected to complementary bit line pair BIT0and NBIT0of column0. The third and fourth memory cells203and204are connected to complementary bit line pair BITn and NBITn of column n. The first and third memory cells201and203are connected to the word line WL0of row0. The second and fourth memory cells202and204are connected to the word line WLm of row m. VDD is the supply voltage, and VSS is the ground voltage. In the following description, BIT0is referred to as “uninverted bit line” and NBIT0is referred to as “inverted bit line” as necessary.

Bus lines BUS and NBUS shown inFIG. 4constitute a complementary bus line pair which is shared among a plurality of columns. In the following description, BUS is referred to as “uninverted bus line” and NBUS is referred to as “inverted bus line” as necessary.

The first memory cell201includes a first P-channel MOS load transistor1, a first N-channel MOS drive transistor2, a second P-channel MOS load transistor3, a second N-channel MOS drive transistor4, a first N-channel MOS access transistor5and a second N-channel MOS access transistor6. The drain of the first N-channel MOS drive transistor2is connected to the uninverted bit line BIT0through the first N-channel MOS access transistor5. The drain of the second N-channel MOS drive transistor4is connected to the inverted bit line NBIT0through the second N-channel MOS access transistor6. The gates of the first and second N-channel MOS access transistors5and6are connected to the word line WL0of row0. Thus, when the word line WL0is at L-level, the first memory cell201exhibits a high impedance state with respect to the complementary bit line pair BIT0and NBIT0. When the word line WL0is at H-level and the cell data is “0”, the first N-channel MOS drive transistor2drives the uninverted bit line BIT0to L-level. When the word line WL0is at H-level and the cell data is “1”, the second N-channel MOS drive transistor4drives the inverted bit line NBIT0to L-level.

The other memory cells, including the second, third and fourth memory cells202,203and204, have the same internal structure as that of the first memory cell201.

Referring toFIG. 4, a precharge circuit210, first and second voltage transfer switches221and222, first and second voltage input/output circuits (VIO)231and232, and a column switch241belong to column0.

When precharge signal PCG is at L-level, the precharge circuit210precharges the complementary bit line pair BIT0and NBIT0to a voltage equal to supply voltage VDD.

The first and second voltage input/output circuits (VIO)231and232have substantially the same circuit structure as that of the voltage input/output circuit150shown inFIG. 1except that the first and second voltage input/output circuit (VIO)231and232ofFIG. 4are supplied with supply voltage VDD2(not shown) which is higher than supply voltage VDD, and a voltage slightly lower than VDD2is also supplied as a bias setting voltage.

When switch control signal VSW is at L-level, the first voltage transfer switch221supplies the voltage of the uninverted bit line BIT0to the first voltage input/output circuit231as an input voltage. Thereafter, when switch control signal VSW rises to H-level, the first voltage transfer switch221supplies the output voltage of the second voltage input/output circuit232to the uninverted bit line BIT0.

When switch control signal VSW is at L-level, the second voltage transfer switch222supplies the voltage of the inverted bit line NBIT0to the second voltage input/output circuit232as an input voltage. Thereafter, when switch control signal VSW is at H-level, the second voltage transfer switch222supplies the output voltage of the first voltage input/output circuit231to the inverted bit line NBIT0.

When column selection signal CA0of column0is at H-level, the column switch241connects the uninverted bit line BIT0and the inverted bit line NBIT0to the uninverted bus line BUS and the inverted bus line NBUS, respectively.

Column n also includes a precharge circuit211, first and second voltage transfer switches223and224, first and second voltage input/output circuits233and234, and a column switch242. Signal CAn is a column selection signal of column n.

The semiconductor integrated circuit ofFIG. 4further includes a sense amplifier250and an output buffer260. The sense amplifier250is a differential amplification circuit shared among a plurality of columns. When sense amplifier enable signal SAE is at H-level, the sense amplifier250drives the higher one of the voltages of the complementary bus line pair BUS and NBUS to supply voltage VDD and drives the lower one to ground voltage VSS, thereby amplifying the potential difference between the complementary bus line pair BUS and NBUS. The output buffer260outputs as data output signal DOUT the voltage of the uninvested bus line BUS which has been amplified by the sense amplifier250.

FIG. 5shows the input/output characteristic of the voltage input/output circuits231to234ofFIG. 4. As illustrated by a solid line inFIG. 5, the input/output characteristic is linear when input voltage VIN is slightly lower than supply voltage VDD.

FIG. 6shows exemplary signal waveforms in the semiconductor integrated circuit ofFIG. 4. InFIG. 6, R1is the first read cycle, and R2is the second read cycle. It is assumed herein that, in first read cycle R1, data of “0” is output from the first memory cell201, and in second read cycle R2, data of “1” is output from the second memory cell202. It is also assumed that, in all the memory cells201and202belonging to column0, the off-leak currents of the first N-channel MOS access transistors5which are closer to the uninverted bit line BIT0is larger than the off-leak currents of the second N-channel MOS access transistors6which are closer to the inverted bit line NBIT0.

In the first place, first read cycle R1is described. Periods T1to T3are preparation periods, and periods T4and T5are actual read periods.

In period T1, precharge signal PCG is lowered to L-level while the word lines WL0and WLm of all the memory cells201and202belonging to column0are kept at L-level, and switch control signal VSW is kept at L-level. In the meantime, the precharge circuit210precharges both the uninverted bit line BIT0, which has been charged to supply voltage VDD, and the inverted bit line NBIT0, which has been discharged to ground voltage VSS, to supply voltage VDD.

In period T2, precharge signal PCG is restored to H-level, whereby the operation of the precharge circuit210is stopped. After the precharge is stopped, the voltage of the uninverted bit line BIT0gradually decreases because of the off-leak currents of the first N-channel MOS access transistors5in all the memory cells201and202belonging to column0. The voltage of the inverted bit line NBIT0also gradually decreases because of the off-leak currents of the second N-channel MOS access transistors6in all the memory cells201and202belonging to column0. Since it is assumed herein that the off-leak currents of the first N-channel MOS access transistors5are larger than those of the second N-channel MOS access transistors6, the voltage decrease is larger in the uninverted bit line BIT0than in the inverted bit line NBIT0. In the meantime, the first voltage transfer switch221continues to supply the voltage of the uninverted bit line BIT0to the first voltage input/output circuit231as an input voltage. The second voltage transfer switch222continues to supply the voltage of the inverted bit line NBIT0to the second voltage input/output circuit232as an input voltage.

In period T3, switch control signal VSW is pulled up to H-level. In response to this, the first voltage transfer switch221supplies the output voltage of the second voltage input/output circuit232to the uninverted bit line BIT0, and the second voltage transfer switch222supplies the output voltage of the first voltage input/output circuit231to the inverted bit line NBIT0. As a result, the relationship between the voltages of the complementary bit line pair BIT0and NBIT0at the end of period T2is inverted before the end of period T3. That is, the voltage exchange occurs between the complementary bit line pair BIT0and NBIT0. In period T3, in order to select column0which includes the first memory cell201that is to be read in this cycle, column selection signal CA0of column0is pulled up to H-level, whereas column selection signals CAn of all the other columns are at L-level. As a result, only the complementary bit line pair BIT0and NBIT0of column0is connected to the complementary bus line pair BUS and NBUS.

In period T4, switch control signal VSW is restored to L-level, whereby the first and second voltage transfer switches221and222are switched to the input side of the first and second voltage input/output circuits231and232. As a result, driving of the complementary bit line pair BIT0and NBIT0by the first and second voltage input/output circuits231and232is halted. At the same time, the word line WL0of row0is pulled to H-level, such that the first memory cell201performs an active output operation according to cell data “0”. That is, the first N-channel MOS drive transistor2of the first memory cell201drives the uninverted bit line BIT0toward L-level through the first N-channel MOS access transistor5. Thus, the voltage of the uninverted bit line BIT0decreases. On this occasion, the off-leak currents of the first N-channel MOS access transistors5of all the memory cells belonging to column0, including the second memory cell202, help a rapid decrease of voltage of the uninverted bit line BIT0. Thus, at the end of period T4, the voltage of the uninverted bit line BIT0is lower than the voltage of the inverted bit line NBIT0, and the potential difference between the complementary bit line pair BIT0and NBIT0(i.e., the potential difference between the complementary bus line pair BUS and NBUS) exceeds a difference necessary for the operation of the sense amplifier250.

In period T5, sense amplifier enable signal SAE is pulled to H-level, whereby the sense amplifier250is activated. As a result, the voltages of the uninverted bit line BIT0and the uninverted bus line BUS are amplified to ground voltage VSS, and the voltages of the inverted bit line NBIT0and the inverted bus line NBUS are amplified to supply voltage VDD. The voltage of the uninverted bus line BUS which is obtained in period T5is output as data output signal DOUT (=0) through the output buffer260.

The operation during periods T1to T3of second read cycle R2is the same as that of first read cycle R1. At the end of period T3, the voltage of the inverted bit line NBIT0is lower than the voltage of the uninverted bit line BIT0.

In period T4of second read cycle R2, the word line WLm of row m is pulled to H-level, such that the second memory cell202performs an active output operation according to cell data “1”. That is, the second N-channel MOS drive transistor4of the second memory cell202drives the inverted bit line NBIT0toward L-level through the second N-channel MOS access transistor6. Thus, the voltage of the inverted bit line NBIT0decreases. In the meantime, the voltage of the uninverted bit line BIT0also decreases due to the off-leak currents of the first N-channel MOS access transistors5in all the memory cells201and202belonging to column0. However, even if the total sum of the off-leak currents of the first N-channel MOS access transistors5in all the memory cells201and202belonging to column0is almost as large as the ON-current (drive current) of the second N-channel MOS drive transistor4in the second memory cell202, occurrence of a predetermined potential difference between the complementary bit line pair BIT0and NBIT0at the start of next period T5is ensured because the voltage of the inverted bit line NBIT0has been lowered in advance in period T3.

In next period T5, sense amplifier enable signal SAE is pulled to H-level, whereby the sense amplifier250is activated. As a result, the voltages of the uninverted bit line BIT0and the uninverted bus line BUS are amplified to supply voltage VDD, and the voltages of the inverted bit line NBIT0and the inverted bus line NBUS are amplified to ground voltage VSS. The voltage of the uninverted bus line BUS which is obtained in period T5is output as data output signal DOUT (=1) through the output buffer260.

The length of time from the falling of switch control signal VSW to activation of the sense amplifier250(period T4) is preferably set to equal the length of time in which a variation in voltages of the complementary bit line pair BIT0and NBIT0due to the off-leak currents before the voltage exchange between the complementary bit line pair BIT0and NBIT0is allowed (period T2).

FIG. 7shows a variation of the semiconductor integrated circuit ofFIG. 4. In the semiconductor integrated circuit ofFIG. 7, the first and second voltage transfer switches221and222and the first and second voltage input/output circuits231and232are provided on the complementary bus line pair BUS and NBUS so as to be shared among a plurality of columns of the SRAM memory cell array200. As seen fromFIG. 7, the chip area of the semiconductor integrated circuit is reduced as compared with the circuit ofFIG. 4where two voltage transfer switches and two voltage input/output circuits are separately provided to each column.

FIG. 8shows exemplary signal waveforms in the semiconductor integrated circuit ofFIG. 7. The example ofFIG. 8is different from the example ofFIG. 6in that all of the column selection signals CA0and CAn are determined at an earlier time in the first period (period T1) of first read cycle R1.

FIG. 9shows another variation of the semiconductor integrated circuit ofFIG. 4. In the semiconductor integrated circuit ofFIG. 9, the precharge circuit210precharges the complementary bit line pair BIT0and NBIT0to supply voltage VDD through the first and second voltage input/output circuits231and232. With such a structure, the size of the transistors which constitute the precharge circuit210is reduced as compared with the structure ofFIG. 4where the precharge circuit210directly precharges the complementary bit line pair BIT0and NBIT0. This also applies to the precharge circuit211of column n.

FIG. 10shows exemplary signal waveforms in the semiconductor integrated circuit ofFIG. 9. The example ofFIG. 10is different from the example ofFIG. 6in that even when precharge signal PCG is lowered to L-level such that the complementary bit line pair BIT0and NBIT0is precharged, switch control signal VSW is pulled to H-level such that the first and second voltage transfer switches221and222are switched to the output side of the first and second voltage input/output circuits231and232.

FIG. 11shows still another variation of the semiconductor integrated circuit ofFIG. 4. In the semiconductor integrated circuit ofFIG. 11, the precharge circuit210precharges the complementary bit line pair BIT0and NBIT0to intermediate level voltage VDD/2 through the first and second voltage input/output circuits231and232. With such a structure, in the first and second voltage input/output circuits231and232ofFIG. 11, the supply voltage is VDD as in the voltage input/output circuit150ofFIG. 1, and the respective input/output characteristics are set as shown inFIG. 2. Thus, it is not necessary to provide a circuit for increasing VDD to VDD2, and therefore, the chip area of the semiconductor integrated circuit is reduced as compared with the examples ofFIGS. 4 and 7. This also applies to the precharge circuit211and the first and second voltage input/output circuits233and234of column n.

FIG. 12shows exemplary signal waveforms in the semiconductor integrated circuit ofFIG. 11. The example ofFIG. 12is different from the example ofFIG. 10in that the precharge voltage of the complementary bit line pair BIT0and NBIT0is intermediate level voltage VDD/2. In the structure ofFIG. 11, a gate-leak reduction effect is attained in the memory cells201to204by reduction of the precharge voltage.

FIG. 13shows a structure of a semiconductor integrated circuit according to the third embodiment of the present invention. The semiconductor integrated circuit ofFIG. 13is realized by applying the precharge voltage adjustment method of the first embodiment to the semiconductor memory of the second embodiment. The memory cells201to204, the sense amplifier250and the output buffer260ofFIG. 13are equivalent to the corresponding circuit blocks ofFIG. 4.

In the SRAM memory cell array200ofFIG. 13, column0includes a dummy bit line DBIT0in addition to the complementary bit line pair BIT0and NBIT0. The dummy bit line DBIT0has a line capacitance substantially equal to that of the uninverted bit line BIT0. It should be noted that none of the memory cells is connected to the dummy bit line DBIT0. Signal line DBITn is a dummy bit line of column n.

Referring toFIG. 13, a precharge circuit311, a voltage transfer switch321, a voltage input/output circuit (VIO)331, a write circuit (WT)341and a column switch241belong to column0.

When precharge signal PCG is at L-level, the precharge circuit311precharges the uninverted bit line BIT0and the dummy bit line DBIT0to intermediate level voltage VDD/2. When inverted switch control signal NVSW (inverted signal of switch control signal VSW) is at L-level, i.e., when switch control signal VSW is at H-level, the precharge circuit311precharges only the uninverted bit line BIT0to intermediate level voltage VDD/2.

The voltage input/output circuit331has the same functions and circuit structure as those of the voltage input/output circuit150ofFIG. 1.

The voltage transfer switch321has the same circuit structure as that of the voltage transfer switch160ofFIG. 1. When switch control signal VSW is at L-level, the voltage transfer switch321supplies the voltage of the uninverted bit line BIT0to the voltage input/output circuit331as an input voltage. Thereafter, when switch control signal VSW rises to H-level, the output voltage of the voltage input/output circuit331is supplied to the dummy bit line DBIT0.

When write enable signal WE is activated, the write circuit341supplies a voltage signal determined according to the write data to the complementary bit line pair BIT0and NBIT0in response to write signal DIN0of column0.

When column selection signal CA0of column0is at H-level, the column switch241connects the uninverted bit line BIT0and the dummy bit line DBIT0to the uninverted bus line BUS and the inverted bus line NBUS, respectively.

Column n also includes a precharge circuit312, a voltage transfer switch322, a voltage input/output circuit332, a write circuit342and a column switch242. Signal DINn is a write signal of column n, and signal CAn is a column selection signal of column n.

FIG. 14shows exemplary signal waveforms in the semiconductor integrated circuit ofFIG. 13. InFIG. 14, R1is the first read cycle, and R2is the second read cycle. It is assumed herein that, in first read cycle R1, data of “0” is read out from the first memory cell201, and in second read cycle R2, data of “1” is read out from the second memory cell202.

In the first place, first read cycle R1is described. Periods T1to T3are preparation periods, and periods T4and T5are actual read periods.

In period T1, precharge signal PCG is lowered to L-level while the word lines WL0and WLm of all the memory cells201and202belonging to column0are kept at L-level, and switch control signal VSW is kept at L-level. In the meantime, the precharge circuit311precharges both the uninverted bit line BIT0, which has been charged to supply voltage VDD, and the dummy bit line DBIT0, which has been discharged to ground voltage VSS, to intermediate level voltage VDD/2.

In period T2, precharge signal PCG is restored to H-level, whereby the operation of the precharge circuit311is stopped. After the precharge is stopped, the voltage of the uninverted bit line BIT0gradually decreases because of the off-leak currents of the first N-channel MOS access transistors5in all the memory cells201and202belonging to column0. In the meantime, the voltage transfer switch321continues to supply the voltage of the uninverted bit line BIT0to the voltage input/output circuit331as an input voltage. On the other hand, the voltage of the dummy bit line DBIT0scarcely changes.

In period T3, switch control signal VSW is pulled up to H-level. In response to this, the voltage transfer switch321is switched from the input side to output side of the voltage input/output circuit331, such that the output voltage of the voltage input/output circuit331is supplied to the dummy bit line DBIT0. In the meantime, the precharge circuit311receives inverted switch control signal NVSW from the voltage transfer switch321to again precharge only the former of the uninverted bit line BIT0and the dummy bit line DBIT0to intermediate level voltage VDD/2. As a result, the relationship between the voltage of the uninverted bit line BIT0and the voltage of the dummy bit line DBIT0at the end of period T2is inverted before the end of period T3. That is, the precharge voltage of the dummy bit line DBIT0is adjusted to a voltage in which the total sum of the off-leak currents of the first N-channel MOS access transistors5in all the memory cells201and202belonging to column0which are in a high impedance output state is reflected. In period T3, in order to select column0which includes the first memory cell201that is to be read in this cycle, column selection signal CA0of column0is pulled up to H-level, whereas the column selection signals CAn of all the other columns are at L-level. As a result, only the uninverted bit line BIT0and the dummy bit line DBIT0of column0are connected to the complementary bus line pair BUS and NBUS.

In period T4, switch control signal VSW is restored to L-level, whereby the voltage transfer switch321is switched to the input side of the voltage input/output circuit331, and the operation of the precharge circuit311is stopped. As a result, driving of the dummy bit line DBIT0by the voltage input/output circuit331is halted. At the same time, the word line WL0of row0is pulled to H-level, such that the first memory cell201performs an active output operation according to cell data “0”. That is, the first N-channel MOS drive transistor2of the first memory cell201drives the uninverted bit line BIT0toward L-level through the first N-channel MOS access transistor5. Thus, the voltage of the uninvested bit line BIT0decreases. On this occasion, the off-leak currents of the first N-channel MOS access transistors5of all the memory cells belonging to column0, including the second memory cell202, help a rapid decrease of voltage of the uninvested bit line BIT0. Thus, at the end of period T4, the voltage of the uninverted bit line BIT0is lower than the voltage of the dummy bit line DBIT0, and the potential difference between the uninverted bit line BIT0and the dummy bit line DBIT0(i.e., the potential difference between the complementary bus line pair BUS and NBUS) exceeds a difference necessary for the operation of the sense amplifier250.

In period T5, sense amplifier enable signal SAE is pulled to H-level, whereby the sense amplifier250is activated. As a result, the voltages of the uninverted bit line BIT0and the uninverted bus line BUS are amplified to ground voltage VSS, and the voltages of the dummy bit line DBIT0and the inverted bus line NBUS are amplified to supply voltage VDD. The voltage of the uninverted bus line BUS which is obtained in period T5is output as data output signal DOUT (=0) through the output buffer260.

The operation during periods T1to T3of second read cycle R2is the same as that of first read cycle R1. At the end of period T3, the voltage of the dummy bit line DBIT0is lower than the voltage of the uninverted bit line BIT0.

In period T4of second read cycle R2, the word line WLm of row m is pulled to H-level, such that the second memory cell202performs an active output operation according to cell data “1”. That is, the second N-channel MOS drive transistor4of the second memory cell202drives the inverted bit line NBIT0toward L-level through the second N-channel MOS access transistor6. The first P-channel MOS load transistor1of the second memory cell202pulls up the uninverted bit line BIT0toward H-level through the first N-channel MOS access transistor5. However, the voltage of the dummy bit line DBIT0scarcely changes. On the other hand, the voltage of the uninverted bit line BIT0decreases due to the off-leak currents of the first N-channel MOS access transistors5in all the memory cells201and202belonging to column0. However, even if the total sum of the off-leak currents of the first N-channel MOS access transistors5in all the memory cells201and202belonging to column0is almost as large as the ON-current (drive current) of the second N-channel MOS drive transistor4in the second memory cell202, occurrence of a predetermined potential difference between the uninverted bit line BIT0and the dummy bit line DBIT0at the start of next period T5is ensured because the voltage of the dummy bit line DBIT0has been lowered in advance in period T3.

In next period T5, sense amplifier enable signal SAE is pulled to H-level, whereby the sense amplifier250is activated. As a result, the voltages of the uninverted bit line BIT0and the uninverted bus line BUS are amplified to supply voltage VDD, and the voltages of the dummy bit line DBIT0and the inverted bus line NBUS are amplified to ground voltage VSS. The voltage of the uninverted bus line BUS which is obtained in period T5is output as data output signal DOUT (=1) through the output buffer260.

The length of time from a halt of re-precharging by pulling down switch control signal VSW to activation of the sense amplifier250(period T4) is preferably set to equal the length of time in which a variation in voltage of the uninverted bit line BIT0due to the off-leak currents of the first N-channel MOS access transistors5in all the memory cells201and202belonging to column0before the voltage adjustment of the dummy bit line DBIT0is allowed (period T2).

As described above, a semiconductor integrated circuit of the present invention is useful because the influence of off-leak currents of transistors can be alleviated without causing an increase in power consumption.