SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including an obverse surface facing one side in a thickness direction, a plurality of semiconductor elements located on the one side in the thickness direction with respect to the substrate and having a switching function, a first layer located between the obverse surface and the plurality of semiconductor elements in the thickness direction and having electrical conductivity, a second layer conductively bonding the obverse surface and the first layer to each other, and a third layer conductively bonding the first layer and the plurality of semiconductor elements to each other.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device.

BACKGROUND ART

Conventionally, semiconductor device with semiconductor elements such as MOSFETs or IGBTs are widely known. In recent years, there has been an increasing demand for semiconductor devices capable of passing a large current. As a response to such a demand, JP-A-2018-182330 discloses a semiconductor device with a plurality of semiconductor elements such as MOSFETs. In the semiconductor device, a metal layer formed from a thin metal film such as copper foil is disposed on a substrate (insulating layer) made of an electrically insulating material. The semiconductor elements are conductively bonded to the metal layer via a conductive bonding layer such as solder. Such a semiconductor device can be easily adapted for a large current by increasing the number of semiconductor elements, for example.

During the use of the semiconductor device disclosed in JP-A-2018-182330, heat is generated from the semiconductor elements. The thermal conductivity of the substrate (insulating layer) is lower than that of the metal layer on which the semiconductor elements are mounted. Therefore, it takes time to dissipate the heat generated by the semiconductor elements to the opposite side of the substrate (insulating layer) from the metal layer. Thus, the heat generated at the semiconductor elements tends to be retained in the metal layer, causing an increase in temperature of the metal layer or the semiconductor elements.

DETAILED DESCRIPTION OF EMBODIMENTS

The following describes preferred embodiments of the present disclosure with reference to the drawings.

In the present disclosure, the terms such as “first”, “second”, and “third” are used merely as labels and are not intended to impose ordinal requirements on the items to which these terms refer.

In the description of the present disclosure, the expression “An object A is formed in an object B”, and “An object A is formed on an object B” imply the situation where, unless otherwise specifically noted, “the object A is formed directly in or on the object B”, and “the object A is formed in or on the object B, with something else interposed between the object A and the object B”. Likewise, the expression “An object A is disposed in an object B”, and “An object A is disposed on an object B” imply the situation where, unless otherwise specifically noted, “the object A is disposed directly in or on the object B”, and “the object A is disposed in or on the object B, with something else interposed between the object A and the object B”. Further, the expression “An object A is located on an object B” implies the situation where, unless otherwise specifically noted, “the object A is located on the object B, in contact with the object B”, and “the object A is located on the object B, with something else interposed between the object A and the object B”. Still further, the expression “An object A overlaps with an object B as viewed in a certain direction” implies the situation where, unless otherwise specifically noted, “the object A overlaps with the entirety of the object B”, and “the object A overlaps with a part of the object B”.

Based onFIGS.1to18, a semiconductor device A10according to a first embodiment of the present disclosure is described below. The semiconductor device A10includes a substrate10, a first layer20, a second layer21, a third layer22, and a plurality of semiconductor elements30. In the present embodiment, the semiconductor device A10includes a plurality of power supply terminals23, an output terminal24, a plurality of gate terminals25, a plurality of element current detection terminals26, a plurality of conductive members40, a case60, and a sealing resin70. For the convenience of understanding, the sealing resin70and the wires, described later, are transparent inFIG.3. The sealing resin70is transparent inFIG.4.

The semiconductor device A10shown inFIG.1is a power module. The semiconductor device A10is used in inverters for various electrical products and hybrid vehicles. As shown inFIGS.1and2, the semiconductor device A10is rectangular (or generally rectangular) as viewed in the thickness direction z of the substrate10. For the convenience of description, a direction orthogonal to the thickness direction z is defined as a first direction x. The direction orthogonal to the thickness direction z and the first direction x is defined as a second direction y. The semiconductor device A10is elongated along the first direction x in the illustrated example, but the present disclosure is not limited to this.

As shown inFIG.11, the substrate10has a first metal layer11, a second metal layer12, and an insulating layer13. The insulating layer13is located between the first metal layer11and the second metal layer12in the thickness direction z. The insulating layer13has an electrically insulating property. Examples of the constituent material of the insulating layer13include ceramic epoxy.

The first metal layer11is laminated on the insulating layer13. The first metal layer11includes an obverse surface11A. The obverse surface11A faces a first side (the upper side inFIG.11) in the thickness direction z. The first metal layer11is made of a metal material having electrical conductivity and composed of metal foil of copper (Cu) or a copper alloy, for example.

The second metal layer12is located opposite to the first metal layer11(on a second side in the thickness direction z) with respect to the insulating layer13. The insulating layer13is laminated on the second metal layer12. The second metal layer12is made of a metal having electrical conductivity as with the first metal layer11and formed from a metal plate made of copper or a copper alloy, for example.

As an example of the thicknesses of the first metal layer11, the second metal layer12and the insulating layer13, the thickness of the first metal layer11may be 0.1 mm to 2.0 mm, the thickness of the second metal layer12may be 0.3 mm to 2.0 mm, and the thickness of the insulating layer13may be 0.12 mm to 0.18 mm. An insulated metal substrate may be used as the substrate10of the present embodiment. The substrate10provided by an insulated metal substrate is composed of a metal plate (the second metal layer12), and the insulating layer13and the first metal layer11laminated on the metal plate. Instead of an insulated metal substrate, a DBC (Direct Bonded Copper) substrate may be used. The DBC substrate is composed of a ceramic plate (the insulating layer13) and a pair of copper foils (the first metal layer11and the second metal layer12) laminated on opposite sides of the ceramic plate in the thickness direction z.

In the present embodiment, the first metal layer11includes a first element mount section111, a second element mount section112, a first conductive section113, a first gate section114, a first detection section115, a pair of thermistor mount sections116, a second gate section117, and a second detection section118. Such sections constituting the first metal layer11are formed, for example, by partially removing the copper foil laminated on the insulating layer13through wet etching. The surfaces of these sections of the first metal layer11may be plated with silver (Ag).

As shown inFIGS.4and9to12, some of the semiconductor elements30are mounted on the first element mount section111. For the convenience of description, the semiconductor elements30mounted on the first element mount section111are referred to as “first elements31”. As shown inFIG.4, etc., the first element mount section111is offset toward one side in the second direction y (the upper side inFIG.4) of the substrate10. The first element mount section111has a band shape extending in the first direction x. In the semiconductor device A10, ten first elements31(semiconductor elements30) are mounted on the first element mount section111, but the number of first elements31is not limited to this. A first power supply pad111ahaving a band shape extending in the second direction y is formed at one end of the first element mount section111in the first direction x (the right side inFIG.4).

As shown inFIGS.4,9,10and12, some of the semiconductor elements30are mounted on the second element mount section112. For the convenience of description, the semiconductor elements30mounted on the second element mount section112are referred to as “second elements31”. As shown inFIG.4, etc., the second element mount section112is located between the first element mount section111and the first conductive section113in the second direction y. The second element mount section112has a band shape extending in the first direction x. In the semiconductor device A10, ten second elements31(semiconductor elements30) are mounted on the second element mount section112, but the number of second element32is not limited to this. An output pad112ahaving a band shape extending in the second direction y is formed at one end of the second element mount section112in the first direction x (the left end inFIG.4). A part of the output pad112athat is offset from the second element mount section112toward one side in the second direction y (the upper side inFIG.4) is located next to the first element mount section111in the first direction x. A part of the output pad112athat is offset from the second element mount section112toward the other side of in the second direction y (the lower side inFIG.4) is located next to the first conductive section113in the first direction x.

As shown inFIGS.4,9and10, the first conductive section113is electrically connected to both the first elements31and the second elements32. The first conductive section113is located opposite to the first element mount section111with respect to the second element mount section112in the second direction y. The first conductive section113has a band shape extending in the first direction x. A second power supply pad113ahaving a band shape extending in the second direction y is formed at one end of the first conductive section113in the first direction x (the right end inFIG.4). As shown inFIG.4, the first conductive section113is formed with a slit113bextending in the first direction x. The slit113bis located in the center of the first conductive section113in the second direction y and extends from one end in the first direction x (the right end inFIG.4) to the center in the first direction x.

As shown inFIGS.4,9and10, the first gate section114is electrically connected to the first elements31. The first gate section114has a band shape extending in the first direction x. The first gate section114is located between the first element mount section111and the case60in the second direction y. In the semiconductor device A10, the first gate section114turns back at one end in the first direction x (the right end inFIG.4) and is formed in two rows in the second direction y. The width (the dimension in the second direction y) of the first gate section114is smaller than the respective widths of the first element mount section111, the second element mount section112and the first conductive section113.

As shown inFIGS.4,9and10, the first detection section115is electrically connected to the first elements31. The first detection section115has a band shape extending in the first direction x. The first detection section115is located between the first element mount section111and the case60in the second direction y. In the semiconductor device A10, the first detection section115turns back at one end in the first direction x (the left end inFIG.4) and is formed in two rows in the second direction y. The width (the dimension in the second direction y) of the first detection section115is the same as the width of the first gate section114.

As shown inFIGS.4and9, the pair of thermistor mount sections116are spaced apart from each other in the second direction y and carry a thermistor33. The thermistor mount sections116are located close to a corner of the substrate10. The first element mount section111, the first gate section114and the first detection section115are located around the pair of thermistor mount sections116.

As shown inFIGS.4,9and10, the second gate section117is electrically connected to the second elements32. The second gate section117has a band shape extending in the first direction x. The second gate section117is located between the first conductive section113and the case60in the second direction y. In the semiconductor device A10, the second gate section117turns back at one end in the first direction x (the left end inFIG.4) and is formed in two rows in the second direction y. The width (the dimension in the second direction y) of the second gate section117is smaller than the respective widths of the first element mount section111, the second element mount section112and the first conductive section113.

As shown inFIGS.4,9and10, the second detection section118is electrically connected to the second elements32. The second detection section118has a band shape extending in the first direction x. The second detection section118is located between the first conductive section113and the case60in the second direction y. In the semiconductor device A10, the second detection section118turns back at one end in the first direction x (the right end inFIG.4) and is formed in two rows in the second direction y. The width (the dimension in the second direction y) of the second detection section118is the same as the width of the second gate section117.

As shown inFIGS.2to4, etc., the power supply terminals23are part of external connection terminals provided in the semiconductor device A10. The power supply terminals23are connected to a DC power supply disposed outside the semiconductor device A10. The power supply terminals23are supported on the case60. The power supply terminals23are formed from a metal plate. The constituent material of the metal plate is copper, for example. The power supply terminals23are, for example, about 1.0 mm in thickness.

The plurality of power supply terminals23include a first power supply terminal23aand a second power supply terminal23b. The first power supply terminal23ais a positive electrode (P terminal). The first power supply terminal23ais connected to the first power supply pad111aof the first element mount section111. The second power supply terminal23bis a negative electrode (N terminal). The second power supply terminal23bis connected to the second power supply pad113aof the first conductive section113. The first power supply terminal23aand the second power supply terminal23bare spaced apart from each other in the second direction y.

As shown inFIGS.9and13, each of the first power supply terminal23aand the second power supply terminal23bhas an external connection section231, an internal connection section232, and an intermediate section233.

The external connection section231is a flat plate exposed from the semiconductor device A10and orthogonal to the thickness direction z. A DC power supply cable, etc. is connected to the external connection section231. The external connection section231is supported on the case60. The external connection section231has a connection hole231apenetrating in the thickness direction z. A fastening member, such as a bolt, is inserted into the connection hole231a. The surface of the external connection section231may be plated with nickel (Ni).

The internal connection section232, which has a comb shape, is connected to the first power supply pad111aof the first element mount section111in the first power supply terminal23aand connected to the second power supply pad113aof the first conductive section113in the second power supply terminal23b. In the semiconductor device A10, the internal connection section232has three teeth, which are arranged along the second direction y. The teeth are bent in the thickness direction z. Thus, each of the teeth has the shape of a hook as viewed in the second direction y. The teeth are connected to the first power supply pad111aor the second power supply pad113aby ultrasonic bonding.

The intermediate section233connects the external connection section231and the internal connection section232to each other. The intermediate section233is L-shaped in cross section with respect to the first direction x. The intermediate section233has a base portion233aand a standing portion233b. The base portion233ais along the first direction x and the second direction y. One end of the base portion233ain the first direction x is connected to the internal connection section232. The standing portion233bstands from the base portion233ain the thickness direction z. One end of the standing portion233bin the thickness direction z is connected to the external connection section231.

As shown inFIGS.2to4, etc., the output terminal24is one of external connection terminals provided in the semiconductor device A10. The output terminal24is connected to a power supply target (e.g., a motor) disposed outside the semiconductor device A10. The output terminal24is supported on the case60and located opposite to the power supply terminals23with respect to the substrate10in the first direction x. The output terminal24is formed from a metal plate. The constituent material of the metal plate is copper, for example. The output terminal24is 1.0 mm in thickness.

In the semiconductor device A10, the output terminal24is separated into two sections, i.e., a first terminal section24aand a second terminal section24b. Alternatively, the output terminal24may be a single member, not separated as in the semiconductor device A10. The first terminal section24aand the second terminal section24bare connected in parallel to the output pad112aof the second element mount section112. Thus, the output terminal24is connected to the second element mount section112. The first terminal section24aand the second terminal section24bare spaced apart from each other in the second direction y.

As shown inFIGS.10and14, each of the first terminal section24aand the second terminal section24bhas an external connection section241, an internal connection section242, and an intermediate section243.

The external connection section241is a flat plate exposed from the semiconductor device A10and orthogonal to the thickness direction z. A cable, etc. electrically connected to the power supply target is connected to the external connection section241. The external connection section241is supported on the case60. The external connection section241has a connection hole241apenetrating in the thickness direction z. A fastening member, such as a bolt, is inserted into the connection hole241a. The surface of the external connection section241may be plated with nickel.

The internal connection section242, which has a comb shape, is connected to the output pad112aof the second element mount section112. In the semiconductor device A10, the internal connection section242has three teeth, which are arranged along the second direction y. The teeth are bent in the thickness direction z. Thus, each of the teeth has the shape of a hook as viewed in the second direction y. The teeth are connected to the output pad112aby ultrasonic bonding.

The intermediate section243connects the external connection section241and the internal connection section242to each other. The intermediate section243is L-shaped in cross section with respect to the first direction x. The intermediate section243has a base portion243aand a standing portion243b. The base portion243ais along the first direction x and the second direction y. One end of the base portion243ain the first direction x is connected to the internal connection section242. The standing portion243bstands from the base portion243ain the thickness direction z. One end of the standing portion243bin the thickness direction z is connected to the external connection section241.

As shown inFIGS.2to5, etc., the gate terminals25are part of external connection terminals provided in the semiconductor device A10. Each of the gate terminals25is electrically connected to the first gate section114or the second gate section117. The gate terminals25are connected to a drive circuit (e.g., a gate driver) of the semiconductor device A10disposed outside. The gate terminals25are supported on the case60. The gate terminals25are formed from metal rods. The constituent material of the metal rods is copper, for example. The surfaces of the gate terminals25may be plated with tin (Sn) or plated with nickel and tin. As shown inFIG.12, the gate terminals25are L-shaped in cross section with respect to the first direction x. Each of the gate terminals25partially protrudes from the case60toward the side which the obverse surface11A of the first metal layer11(the substrate10) faces in the thickness direction z.

The plurality of gate terminals25include a first gate terminal25aand a second gate terminal25b. As shown inFIG.10, the first gate terminal25ais located close to the first gate section114in the second direction y. As shown inFIG.9, the second gate terminal25bis located opposite to the first gate terminal25awith respect to the first metal layer11(the substrate10) in the second direction y. The second gate terminal25bis located close to the second gate section117.

As shown inFIGS.2to5, etc., the element current detection terminals26are part of external connection terminals provided in the semiconductor device A10. Each of the element current detection terminals26is electrically connected to the first detection section115or the second detection section118. The element current detection terminals26are connected to a control circuit of the semiconductor device A10disposed outside. The element current detection terminals26are supported on the case60. The element current detection terminals26are formed from metal rods. The constituent material of the metal rods is copper, for example. The surfaces of the element current detection terminals26may be plated with tin or plated with nickel and tin. As shown inFIG.12, the element current detection terminals26are L-shaped in cross section with respect to the first direction x. Each of the element current detection terminals26partially protrudes from the case60toward the side which the obverse surface11A of the first metal layer11(the substrate10) faces in the thickness direction z.

The plurality of element current detection terminals26include a first detection terminal26aand a second detection terminal26b. As shown inFIG.10, the first detection terminal26ais located next to the first gate terminal25ain the first direction x. As shown inFIG.9, the second detection terminal26bis located next to the second gate terminal25bin the first direction x.

As shown inFIGS.2to5and10, the semiconductor device A10includes a power supply current detection terminal27. The power supply current detection terminal27is one of external connection terminals provided in the semiconductor device A10. The power supply current detection terminal27is connected to a control circuit of the semiconductor device A10disposed outside. The power supply current detection terminal27is supported on the case60. The power supply current detection terminal27is formed from a metal rod. The constituent material of the metal rod is copper, for example. The surface of the power supply current detection terminal27may be plated with tin or plated with nickel and tin. The shape of the power supply current detection terminal27is the same as that of the gate terminals25shown inFIG.12. As with the gate terminals25shown inFIG.12, the power supply current detection terminal27partially protrudes from the case60toward the side which the obverse surface11A of the first metal layer11(the substrate10) faces in the thickness direction z. In the second direction y, the position of the power supply current detection terminal27is the same as the position of the first gate terminal25a. The power supply current detection terminal27is spaced apart from the first gate terminal25atoward the first terminal section24a(the output terminal24) in the first direction x.

As shown inFIG.10, the semiconductor device A10includes a power supply current detection wire45. The power supply current detection wire45is a conductive member and connected to the power supply current detection terminal27and the first element mount section111. Thus, the power supply current detection terminal27is electrically connected to the first element mount section111. The constituent material of the power supply current detection wire45is aluminum, for example.

As shown inFIGS.2to5and9, the semiconductor device A10includes a pair of thermistor terminals28. The thermistor terminals28are part of external connection terminals provided in the semiconductor device A10. The thermistor terminals28are connected to a control circuit of the semiconductor device A10disposed outside. The thermistor terminals28are supported on the case60. The thermistor terminals28are formed from metal rods. The constituent material of the metal rods is copper, for example. The surfaces of the thermistor terminals28may be plated with tin or plated with nickel and tin. The shape of the thermistor terminals28is the same as that of the gate terminals25shown inFIG.12. As with the gate terminals25shown inFIG.12, each of the thermistor terminals28partially protrudes from the case60toward the side which the obverse surface11A of the first metal layer11(the substrate10) faces in the thickness direction z. In the second direction y, the position of the thermistor terminals28is the same as the position of the first gate terminal25a. The thermistor terminals28are spaced apart from the first gate terminal25atoward the first power supply terminal23ain the first direction x. The thermistor terminals28are spaced apart from each other in the first direction x.

As shown inFIG.9, the semiconductor device A10includes a pair of thermistor wires46. The thermistor wires46are conductive members and individually connected to the thermistor terminals28and the thermistor mount sections116. Thus, the thermistor terminals28are electrically connected to the thermistor mount sections116. The constituent material of the thermistor wires46is aluminum, for example.

Each of the semiconductor elements30(the first elements31and the second elements32) has a semiconductor layer containing silicon carbide (SiC), for example, and has a switching function. The semiconductor elements30are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) made by using a semiconductor material mainly composed of silicon carbide. The semiconductor elements30are not limited to MOSFETs and may be IGBTs (Insulated Gate Bipolar Transistor). For the semiconductor device A10, an example in which the semiconductor elements30are MOSFETs is described. As shown inFIGS.15and17, each of the semiconductor elements30is rectangular (square in the semiconductor device A10) as viewed in the thickness direction z. In the semiconductor device A10, the thickness of each semiconductor element30is, for example, 400 μm or less, and more preferably, 150 μm or less.

As shown inFIGS.15to18, each of the semiconductor elements30has a source electrode301, a drain electrode302, and a gate electrode303. The source electrode301is provided at the upper end of the semiconductor element30that faces in the same sense of the thickness direction z as the obverse surface11A of the first metal layer11(the substrate10). Source current flows from inside the semiconductor element30to the source electrode301.

The drain electrode302is provided at the lower end of the semiconductor element30that faces in the opposite sense of the thickness direction z from the obverse surface11A of the first metal layer11(the substrate10). Drain current flows from inside of the semiconductor element30to the drain electrode302.

The gate electrode303is provided at the upper end of the semiconductor element30that faces in the same sense of the thickness direction z as the obverse surface11A of the first metal layer11(the substrate10). Gate voltage for driving the semiconductor elements30is applied to the gate electrode303. As viewed in the thickness direction z, the area of the gate electrode303is smaller than the area of the source electrode301.

The plurality of semiconductor elements30include a plurality of first elements31and a plurality of second elements32. The first elements31are mounted on the first element mount section111. The first elements31are arranged at predetermined intervals in the first direction x. The second elements32are mounted on the second element mount section112. The second element32are arranged at predetermined intervals in the first direction x.

As shown inFIGS.11,12, and15to18, the first layer20is located between the obverse surface11A of the first metal layer11(the first element mount section111and the second element mount section112) and the semiconductor elements30in the thickness direction z. The first layer20is made of a metal material having electrical conductivity. The first layer20is made of a material having the same thermal conductivity as the second metal layer12or a material having a greater thermal conductivity than the second metal layer12. The first layer20is made of copper or a copper alloy, for example. When the constituent material of the first layer20is copper, the thermal conductivity of the first layer20is 398 W/mk. Examples of the constituent material of the first layer20include aluminum, iron, and carbon, in addition to copper and a copper alloy. The thickness of the first layer20is larger than that of the second metal layer12. Preferably, the thickness of the first layer20is one to ten times the thickness of the second metal layer12. The thickness of the first layer20is, for example, 1 mm to 4 mm, and preferably, 2 mm to 3 mm.

In the semiconductor device A10, the first layer20includes a plurality of individual sections201separated from each other. In the semiconductor device A10, the plurality of individual sections201are disposed individually for the plurality of semiconductor elements30. Each of the semiconductor elements30is supported on one of the individual sections201. In the semiconductor device A10, the individual sections201corresponding to the first elements31are supported on the first element mount section111and arranged at predetermined intervals in the first direction x. The individual sections201corresponding to the second elements32are supported on the second element mount section112and arranged at predetermined intervals in the first direction x. The individual sections201are larger than the semiconductor elements30as viewed in the thickness direction z. The individual sections201are rectangular (square in the semiconductor device A10) as viewed in the thickness direction z.

The second layer21is located between the first metal layer11(the first element mount section111and the second element mount section112) and the first layer20(the individual sections201) in the thickness direction z. The second layer21has electrical conductivity and conductively bonds the respective obverse surfaces11A of the first element mount section111and the second element mount section112to the individual sections201. The constituent material of the second layer21is, for example, lead-free solder containing tin as the main component. The thickness of the second layer21is 0.02 mm to 0.20 mm, for example.

In the semiconductor device A10, the second layer21includes a plurality of regions separated from each other. The plurality of regions of the second layer21individually correspond to the plurality of individual sections201. The second layer21may include a region common to some of the individual sections201. For example, the second layer21may be configured to include a region common to the individual sections201supported on the first element mount section111and a region common to the individual sections201supported on the second element mount section112.

The third layer22is located between the first layer20(the individual sections201) and the semiconductor elements30in the thickness direction z. The third layer22has electrical conductivity and conductively bonds the individual sections201and the semiconductor elements30to each other. More specifically, the drain electrode302of each semiconductor element30and the first layer20(individual section201) are conductively bonded to each other by the third layer22. The third layer22is made of a bonding material containing a metal material. In the semiconductor device A10, the constituent material of the third layer22includes silver. In the semiconductor device A10, the third layer22is sintered silver. Alternatively, the third layer22may be composed of sintered metal containing metals other than silver (e.g., sintered copper), aluminum subjected to solid-phase diffusion bonding, solder, or metal paste material. The thickness of the third layer22is 0.02 mm to 0.20 mm, for example.

As shown inFIGS.12and15to18, etc., the conductive members40are bonded to the source electrodes301of the semiconductor elements30and the second element mount section112or the first conductive section113. The conductive members are formed from metal plates. The metal may be copper or a copper alloy. The conductive members40are formed by bending the metal plates.

The plurality of conductive members40include a plurality of first conductive members41and a plurality of second conductive members42. Each of the first conductive members41is bonded to the source electrode301of one of the first elements31and the second element mount section112. The first conductive members41and the second element mount section112are bonded to each other via conductive member bonding layers48. The first conductive members41and the source electrodes301of the first elements31are bonded to each other via conductive member bonding layers49. The conductive member bonding layers48and the conductive member bonding layers49bonded to the first conductive members41are solder, metal paste, or sintered metal, for example.

Each of the second conductive members42is bonded to the source electrode301of one of the second elements32and the first conductive section113. The second conductive members42and the first conductive section113are bonded to each other via conductive member bonding layers48. The second conductive members42and the source electrodes301of the second elements32are bonded to each other via conductive member bonding layers49. The conductive member bonding layers48and the conductive member bonding layers49bonded to the second conductive member42are solder, metal paste, or sintered metal, for example.

As shown inFIGS.4and9, the semiconductor device A10includes the thermistor33. The thermistor33is electrically bonded to the pair of thermistor mount sections116. In the semiconductor device A10, the thermistor33is an NTC (Negative Temperature Coefficient) thermistor. NTC thermistors have the characteristic that their resistance gradually decreases as the temperature rises. The thermistor33is used as a temperature detection sensor of the semiconductor device A10. The thermistor33is electrically connected to the pair of thermistor terminals28via the pair of thermistor mount sections116and the pair of thermistor wires46.

As shown inFIGS.9,10,15and17, the semiconductor device A10includes a plurality of first gate wires431, a plurality of second gate wires432, a third gate wire433, and a fourth gate wire434. Each of the first gate wires431is a conductive member having one end connected to the gate electrode303of one of the first elements31and another end connected to the first gate section114. Each of the second gate wires432is a conductive member having one end connected to the gate electrode303of one of the second elements32and another end connected to the second gate section117. The constituent material of the first gate wires431and the second gate wires432is aluminum, for example.

The third gate wire433is a conductive member and connected to the first gate terminal25aand the first gate section114. Thus, the first gate terminal25ais electrically connected to the gate electrodes303of the first elements31mounted on the first element mount section111. The fourth gate wire434is a conductive member and connected to the second gate terminal25band the second gate section117. Thus, the second gate terminal25bis electrically connected to the gate electrodes303of the second elements32mounted on the second element mount section112. The constituent material of the third gate wire433and the fourth gate wire434is aluminum, for example.

As shown inFIGS.9,10,15and17, the semiconductor device A10includes a plurality of first detection wires441, a plurality of second detection wires442, a third detection wire443, and a fourth detection wire444. Each of the first detection wires441is a conductive member having one end connected to the source electrode301of one of the first elements31and another end connected to the first detection section115. Each of the second detection wires442is a conductive member having one end connected to the source electrode301of one of the second elements32and another end connected to the second detection section118. The constituent material of the first detection wires441and the second detection wires442is aluminum, for example.

The third detection wire443is a conductive member and connected to the first detection terminal26aand the first detection section115. Thus, the first detection terminal26ais electrically connected to the source electrodes301of the first elements31mounted on the first element mount section111. The fourth detection wire444is a conductive member and connected to the second detection terminal26band the second detection section118. Thus, the second detection terminal26bis electrically connected to the source electrodes301of the second elements32mounted on the second element mount section112. The constituent material of the third detection wire443and the fourth detection wire444is aluminum, for example.

As shown inFIGS.3to7, the case60is an electrically insulating member surrounding the first metal layer11(the substrate10) as viewed in the thickness direction z. The constituent material of the case60is a synthetic resin with excellent heat resistance, such as PPS (polyphenylene sulfide). The case60includes a pair of first side walls611, a pair of second side walls612, a plurality of mount portions62, a power supply terminal base63and an output terminal base64.

As shown inFIGS.2and4, the pair of first side walls611are spaced apart from each other in the first direction x. The pair of first side walls611are disposed along the second direction y and the thickness direction z.

As shown inFIGS.2and4, the pair of second side walls612are spaced apart from each other in the second direction y. The second side walls612are disposed along the first direction x and the thickness direction z. The opposite ends of each of the second side walls612in the first direction x are connected to the first side walls611. The first gate terminal25a, the first detection terminal26a, the power supply current detection terminal27and the pair of thermistor terminals28are disposed on the inner side of one of the second side walls612. The second gate terminal25band the second detection terminal26bare disposed on the inner side of the other second side wall612. As shown inFIGS.9,10and12, the ends of these terminals that are closer to the first metal layer11(the substrate10) in the thickness direction z are supported on the pair of second side walls612.

As shown inFIGS.2,9and10, the mount portions62are provided at four corners of the case60as viewed in the thickness direction z. Each of the mount portions62is formed with a through-hole penetrating in the thickness direction z, and a mounting member621is fitted in each of the through-holes. Each of the mounting members621has a mounting hole621apenetrating in the thickness direction z. Fitting a fastening member, not shown, into each mounting hole621aallows a heat dissipation member (e.g., a heat sink), not shown, to be attached to the semiconductor device A10.

As shown inFIGS.2,6and9, the power supply terminal base63protrudes outward in the first direction x from one of the first side walls611. The power supply terminal base63supports the power supply terminals23. The power supply terminal base63includes a first terminal base631and a second terminal base632. The first terminal base631and the second terminal base632are spaced apart from each other in the second direction y. The first terminal base631supports the first power supply terminal23a. The external connection section231of the first power supply terminal23ais exposed from the first terminal base631. The second terminal base632supports the second power supply terminal23b. The external connection section231of the second power supply terminal23bis exposed from the second terminal base632. A plurality of grooves633extending in the first direction x are formed between the first terminal base631and the second terminal base632. As shown inFIGS.9and13, a pair of nuts634and a pair of intermediate members635are disposed inside the first terminal base631and the second terminal base632. Each intermediate member635is located on the second side in the thickness direction z (the lower side inFIG.13) with respect to a nut634and held in contact with the nut634. One of the nuts634and the relevant intermediate member635are held in engagement with the external connection section231and the intermediate section233of the first power supply terminal23a. The other nut634and the relevant intermediate member635are held in engagement with the external connection section231and the intermediate section233of the second power supply terminal23b. Each of the intermediate members635is partially exposed from the power supply terminal base63. The pair of nuts634correspond to the pair of connection holes231aprovided in the first power supply terminal23aand the second power supply terminal23b. Fastening members such as bolts inserted in the connection holes231amesh with the nuts634.

As shown inFIGS.2,7and10, the output terminal base64protrudes outward in the first direction x from the other first side wall611. The output terminal base64supports the output terminal24. The output terminal base64includes a first terminal base641and a second terminal base642. The first terminal base641and the second terminal base642are spaced apart from each other in the second direction y. The first terminal base641supports the first terminal section24aof the output terminal24. The external connection section241of the first terminal section24ais exposed from the first terminal base641. The second terminal base642supports the second terminal section24bof the output terminal24. The external connection section241of the second terminal section24bis exposed from the second terminal base642. A plurality of grooves643extending in the first direction x are formed between the first terminal base641and the second terminal base642. As shown inFIGS.10and14, a pair of nuts644and a pair of intermediate members645are disposed inside the first terminal base641and the second terminal base642. Each intermediate member645is located on the second side in the thickness direction z (the lower side inFIG.14) with respect to a nut644and held in contact with the nut644. One of the nuts644and the relevant intermediate member645are held in engagement with the external connection section241and the intermediate section243of the first terminal section24a. The other nut644and the relevant intermediate member645are held in engagement with the external connection section241and the intermediate section243of the second terminal section24b. Each of the intermediate members645is partially exposed from the output terminal base64. The pair of nuts644correspond to the pair of connection holes241aprovided in the first terminal section24aand the second terminal section24b. Fastening members such as bolts inserted in the connection holes241amesh with the nuts644.

As shown inFIGS.11and12, the sealing resin70is contained in the area enclosed by the case60and the substrate10. The sealing resin70covers the semiconductor elements30. The constituent material of the sealing resin70is black epoxy resin, for example. Other materials, such as silicone gel, may be selected as the constituent material of the sealing resin70.

In the semiconductor device A10, two switching circuits, i.e., an upper arm circuit and a lower arm circuit are formed. The upper arm circuit is constituted of the first element mount section111and the first elements31mounted on the first element mount section111. The first elements31mounted on the first element mount section111are connected in parallel between the first power supply terminal23aand the output terminal24. The gate electrodes303of the first elements31in the upper arm circuit are all connected in parallel to the first gate terminal25a. When a gate voltage is applied to the first gate terminal25aby a drive circuit such as a gate driver disposed outside the semiconductor device A10, the first elements31in the upper arm circuit are driven simultaneously. The source electrodes301of the first elements31in the upper arm circuit are all connected in parallel to the first detection terminal26a. The source current flowing in the first elements31in the upper arm circuit is inputted to the control circuit of the semiconductor device A10disposed outside the semiconductor device A10.

The lower arm circuit is constituted of the second element mount section112and the second element32mounted on the second element mount section112. The second elements32mounted on the second element mount section112are connected in parallel between the output terminal24and the second power supply terminal23b. The gate electrodes303of the second elements32in the lower arm circuit are all connected in parallel to the second gate terminal25b. When a gate voltage is applied to the second gate terminal25bby a drive circuit such as a gate driver disposed outside the semiconductor device A10, the second elements32in the lower arm circuit are driven simultaneously. The source electrodes301of the second elements32in the lower arm circuit are all connected in parallel to the second detection terminal26b. The source current flowing in the second elements32in the lower arm circuit is inputted to the control circuit of the semiconductor device A10disposed outside the semiconductor device A10.

When a DC power supply is connected to the first power supply terminal23aand the second power supply terminal23band the semiconductor elements30(the first elements31and the second elements32) in the upper arm circuit and the lower arm circuit are driven, AC voltages of various frequencies are output from the output terminal24. The AC voltages outputted from the output terminal24are supplied to a power supply target, such as a motor.

The advantages of the semiconductor device A10are described below.

The semiconductor device A10includes the first layer20, the second layer21, and the third layer22. The first layer20is located between the obverse surface11A of the first metal layer11(the first element mount section111and the second element mount section112) and the semiconductor elements30and has electrical conductivity. The second layer21conductively bonds the obverse surface11A of the first metal layer11(the first element mount section111and the second element mount section112) and the semiconductor elements30to each other. The third layer22conductively bonds the first layer20and the semiconductor elements30. Such a configuration including the first layer20can increase the heat capacity of the portion between the semiconductor elements30and the substrate10, preventing the heat saturation of the portion. The heat generated at each semiconductor element30diffuses in the first layer20and is quickly dissipated toward the first metal layer11(the substrate10). Thus, the semiconductor device A10is capable of efficiently dissipating the heat generated at the semiconductor elements30. The semiconductor device A10is thus capable of suppressing the temperature rise around the semiconductor elements30and suitable for passing a large current.

The substrate10on which the semiconductor elements30are mounted includes the first metal layer11, the second metal layer12, and the insulating layer13. The first metal layer11includes the obverse surface11A facing the first side in the thickness direction z. The second metal layer12is located on the second side in the thickness direction z with respect to the first metal layer11. The insulating layer13is located between the first metal layer11and the second metal layer12. The substrate10is constituted of the second metal layer12, the insulating layer13and the first metal layer11deposited in this order. The first metal layer11(the first element mount section111and the second element mount section112) functions as a circuit layer on which the semiconductor elements30are mounted and has a relatively small thickness. In the semiconductor device A10, the heat generated at the semiconductor elements30can be quickly dissipated in the first layer20located between the semiconductor elements30and the first metal layer11. Thus, the heat from the semiconductor elements30is prevented from being retained in the first metal layer11deposited on the insulating layer13.

The first layer20includes a plurality of individual sections201separated from each other. Each of the semiconductor elements30is supported on one of the individual sections201. With such a configuration, the heat generated at the semiconductor elements30does not interfere with each other.

The constituent material of the first layer20includes copper. The thickness of the first layer20is larger than that of the second metal layer12. Such a configuration can enhance thermal conductivity and heat dissipation in the first layer20. As a preferable example, the thickness of the first layer20is 2 mm to 3 mm and one to ten times the thickness of the second metal layer12. Such a configuration further enhances the heat dissipation in the first layer20.

The constituent material of the third layer22includes silver. The third layer22is sintered silver (sintered metal). Therefore, the third layer22has excellent thermal conductivity. Thus, the heat generated at the semiconductor elements30is quickly transferred to the second layer21via the third layer22. This is favorable for efficient dissipation of the heat generated at the semiconductor elements30.

FIGS.19to23show a semiconductor device according to a variation of the first embodiment. InFIG.19and the subsequent figures, the elements that are identical or similar to those of the semiconductor device A10of the foregoing embodiment are denoted by the same reference signs as those used for the foregoing embodiment, and the description thereof is omitted.

The semiconductor device A11of the present variation differs from the semiconductor device A10of the foregoing embodiment mainly in configuration of the first layer20. In the present variation, each of the individual sections201forming the first layer20is made larger in dimension in the second direction y as compared with the foregoing embodiment and has an elongated rectangular shape as viewed in the thickness direction. As shown inFIGS.20and22, in each of the individual sections201, the dimension L2in the second direction y is larger than the dimension L1in the first direction x. In the illustrated example, the dimension L2in the second direction y of each individual section201is larger than the dimension L1in the first direction x. However, the dimension L2is not necessarily larger than the dimension L1. The dimension L1and the dimension L2are limited by the package size of the semiconductor device A11. To efficiently diffuse the heat from the semiconductor elements30in the first layer20, it is desirable that both the dimension L1in the first direction x and the dimension L2in the second direction y are large relative to the size in plan view of each semiconductor element30within the range limited by the package size. As an example, the dimension L2in the second direction y of each individual section201is 0.5 to 2.0 times the dimension L1in the first direction x of the individual section201. The dimension L2in the second direction y of each individual section201is 1.2 to 4.0 times the dimension in the second direction y of each semiconductor element30.

The semiconductor device A11of the present variation has the same effect as the semiconductor device A10of the foregoing embodiment. In the present variation, in each of the individual sections201, the dimension L2in the second direction y is larger than the dimension L1in the first direction x, which is the arrangement direction of the semiconductor elements30. Such a configuration can increase the volume of the first layer20(the plurality of individual sections201) and hence increase the heat capacity of the first layer20. Thus, the heat generated at the semiconductor elements30can be diffused in the individual sections201in the second direction y and efficiently dissipated.

FIGS.24to26show a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device A20of the present variation differs from the semiconductor device A10of the first embodiment mainly in configuration of the first layer20.

In the semiconductor device A20, the first layer20includes a plurality of individual sections201separated from each other, as with the first embodiment. In the semiconductor device A20, however, each of the individual sections201is made larger in dimension in the first direction x than in the first embodiment. Each of the individual sections201supports a plurality of semiconductor elements30. In the illustrated example, each individual section201supports two adjacent semiconductor elements30in the first direction x. Alternatively, each individual section201may support three or more semiconductor elements30.

The semiconductor device A20of the present embodiment has the same effect as the semiconductor device A10of the first embodiment. Moreover, in the semiconductor device A20, the volume of the first layer20is increased by the amount corresponding to the gaps between adjacent individual sections201in the first direction x in the semiconductor device A10. This can further increase the heat capacity of the first layer2. Thus, the heat generated at the semiconductor elements30can be diffused in the first layer20in the first direction x and efficiently dissipated.

The semiconductor device according to the present disclosure is not limited to the foregoing embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure can be varied in design in many ways.

The present disclosure includes the embodiments described in the following clauses.

A semiconductor device comprising:a substrate including an obverse surface facing one side in a thickness direction;a plurality of semiconductor elements located on the one side in the thickness direction with respect to the substrate and having a switching function;a first layer located between the obverse surface and the plurality of semiconductor elements in the thickness direction and having electrical conductivity;a second layer conductively bonding the obverse surface and the first layer to each other; anda third layer conductively bonding the first layer and the plurality of semiconductor elements to each other.

The semiconductor device according to clause 1, wherein the substrate includes a first metal layer including the obverse surface, a second metal layer located on an opposite side in the thickness direction with respect to the first metal layer, and an insulating layer interposed between the first metal layer and the second metal layer.

The semiconductor device according to clause 2, wherein the first layer includes a plurality of individual sections separated from each other.

The semiconductor device according to clause 3, wherein each of the plurality of semiconductor elements is supported on one of the plurality of individual sections.

The semiconductor device according to clause 4, wherein the plurality of semiconductor elements are arranged at predetermined intervals in a first direction orthogonal to the thickness direction, andeach of the plurality of individual sections is larger in dimension in a second direction orthogonal to the thickness direction and the first direction than in a dimension in the

The semiconductor device according to any one of clauses 2 to 5, wherein the first layer contains copper.

The semiconductor device according to any one of clauses 2 to 6, wherein a thickness of the first layer is larger than a thickness of the second metal layer.

The semiconductor device according to clause 7, wherein the thickness of the first layer is ten times or less than the thickness of the second metal layer.

The semiconductor device according to clause 7 or 8, wherein the thickness of the first layer is 2 mm to 3 mm.

The semiconductor device according to clause 9, wherein the thickness of the second metal layer is 0.3 mm to 2.0 mm.

The semiconductor device according to any one of clauses 2 to 10, wherein the thickness of the first metal layer is 0.1 mm to 2.0 mm.

The semiconductor device according to any one of clauses 2 to 11, wherein the first layer is made of a material having a same thermal conductivity as the second metal layer or a material having a greater thermal conductivity than the second metal layer.

The semiconductor device according to any one of clauses 1 to 12, wherein the third layer contains silver.

The semiconductor device according to any one of clauses 1 to 13, wherein the third layer contains sintered metal.

The semiconductor device according to any one of clauses 1 to 14, wherein each of the plurality of semiconductor elements includes a semiconductor layer containing SiC.

The semiconductor device according to any one of clauses 1 to 15, wherein each of the plurality of semiconductor elements includes a gate electrode, a source electrode, and a drain electrode, andthe drain electrode and the first layer are conductively bonded by the third layer.

REFERENCE NUMERALS

A10, A11, A20: Semiconductor device10: Substrate11: First metal layer11A: Obverse surface111: First element mount section111a: First power supply pad112: Second element mount section112a: Output pad113: First conductive section113a: Second power supply pad113b: Slit114: First gate section115: First detection section116: Thermistor mount section117: Second gate section118: Second detection section12: Second metal layer13: Insulating layer20: First layer201: Individual section21: Second layer22: Third layer23: Power supply terminal23a: First power supply terminal23b: Second power supply terminal231: External connection section231a: Connection hole232: Internal connection section233: Intermediate section233a: Base portion233b: Standing portion24: Output terminal24a: First terminal section24b: Second terminal section241: External connection section241a: Connection hole242: Internal connection section243: Intermediate section243a: Base portion243b: Standing portion25: Gate terminal25a: First gate terminal25b: Second gate terminal26: Element current detection terminal26a: First detection terminal26b: Second detection terminal27: Power supply current detection terminal28: Thermistor terminal30: Semiconductor element301: Source electrode302: Drain electrode303: Gate electrode31: First element32: Second element40: Conductive member41: First conductive member42: Second conductive member431: First gate wire432: Second gate wire433: Third gate wire434: Fourth gate wire441: First detection wire442: Second detection wire443: Third detection wire444: Fourth detection wire45: Power supply current detection wire46: Thermistor wire48,49: Conductive member bonding layer60: Case611: First side wall612: Second side wall62: Mount portion621: Mounting member621a: Mounting hole63: Power supply terminal base631: First terminal base632: Second terminal base633: groove634: nut635: Intermediate member64: Power supply terminal base641: First terminal base642: Second terminal base643: groove644: nut645: Intermediate member70: Sealing resinL1: Dimension (in the first direction of individual sections)L2: Dimension (in the second direction of individual sections)x: First direction y: Second directionz: Thickness direction