Composite photoresist for modifying die-side bumps

A composite photoresist comprises a photoresist material and a filler material dispersed within the photoresist material, wherein the filler material includes a plurality of nanoparticles. The photoresist material may comprise an acrylic-based photoresist, a novolak-based photoresist, a polyhydroxystyrene-based photoresist, a SLAM, or a BARC. The filler material may comprise base-soluble styrene-butadiene rubber nanospheres, nitrile-butadiene rubber nanospheres, polystyrene-based nanoparticles, acrylic-based nanoparticles, or inorganic nanoparticles. The nanoparticles may have an average diameter that is between around 10 nm and around 1000 nm and may have a loading in the photoresist material that is between around 5% and 50%. The composite photoresist may be used to form die-side metal bumps for use in a C4 connection that have a roughened sidewall surface but a smooth top surface.

BACKGROUND

After a microelectronic chip or die has been manufactured, it is typically packaged before it is sold. The package provides electrical connection to the chip's internal circuitry, protection from the external environment, and heat dissipation. In one package system, a chip is flip-chip connected to a package substrate. In a flip-chip package, also known as a controlled-collapse chip connection (C4), electrical leads on the die are distributed on its active surface and the active surface is electrically connected to corresponding leads on a package substrate.

FIGS. 1A through 1Cillustrate a prior art method for flip-chip packaging a microelectronic chip or die. InFIG. 1A, a portion of a integrated circuit (IC) die100including a conductive metal bump114is illustrated. For clarity, the conductive metal bump will herein be referred to as a die-side bump. The IC die100includes a substrate102, a device layer104, an interconnect region106, and an IC pad108. The device layer104typically includes a variety of electrical circuit elements (not shown), such as transistors, conductors, and resistors, formed in and on a semiconductor substrate material. The interconnect region106includes layers of interconnected metal vias and metal lines, which are separated by dielectric materials, that provide electrical connection between the devices of the device layer104and electrical routing to conductive IC pads, including the IC pad108. Typically, a dielectric layer110, a barrier metal112, and a die-side bump114are formed over the IC pad108, with the die-side bump114providing a structure for electrical connection from the die100to an external package substrate.

As shown inFIGS. 1B and 1C, in a common C4 flip-chip package system, the IC die100is flip-chip bonded to a package substrate116such that its active surface, including its die-side bumps114, faces a surface of the package substrate116that includes solder bumps118. An electrical connection is formed between the die-side bumps114and the solder bumps118at a joint120. As shown, the joint120typically includes a portion of the die-side bumps114being depressed into the solder bumps118. Heat may be applied to reflow at least the solder material to create a fixed connection between the solder bumps118and the die-side bumps114.

Also illustrated inFIG. 1Cis an underfill material122that is provided between the IC die100and the package substrate116. In some processes, the underfill material is a capillary underfill material and the die-side bumps114are copper. In such systems, the underfill material122may not adhere well to the die-side bumps114of the IC die100. The lack of adhesion between the die-side bumps114and the underfill material122may cause numerous difficulties. For example, it may cause cracking of the dielectric material in the interconnect region106of the IC die100, or in the dielectric layer110, leading to device failure. Further, lack of adhesion may cause undesirable gaps and cracks in the underfill material122itself.

Attempts have been made to address the adhesion issue, however, currently there is no good solution to this problem. Modifications to the underfill material formulation have been researched but only minor improvements in underfill-to-die-side bump adhesion have been observed thus far. Roughening the sidewalls of the die-side bumps114using a wet chemical microetchant is another method of improving adhesion. Unfortunately, the wet chemical microetchant also roughens the top surface of the die-side bumps114, leading to packaging issues such as entrapped flux that causes voids in the die-side bump-to-solder bump connection after the semiconductor chip is attached. The microetchant also tends to damage other films on the wafer, such as the buffer coating material. Accordingly, alternate methods of roughening the sidewalls of the die-side bumps114are needed.

DETAILED DESCRIPTION

Implementations of the invention improve adhesion between a die-side bump, generally formed from copper metal, and an epoxy underfill material. In accordance with implementations of the invention, die-side bumps are formed with physically roughened sidewalls relative to conventional die-side bumps. The roughened sidewalls improve adhesion because the imperfections in the sidewalls (e.g., peaks and valleys on the sidewall surface) mechanically secure the epoxy underfill material to the sidewall, substantially locking the epoxy material in place. Unlike the prior art, however, the top surfaces of the die-side bumps remain substantially smooth, eliminating known issues that arise when the top surfaces of the die-side bump are roughened, and layers of the integrated circuit die are not damaged by the use of microetchants.

FIG. 1Dillustrates a novel die-side bump130having roughened sidewalls132in accordance with implementations of the invention. The die-side bump130is mounted upon a substrate, such as an integrated circuit (IC) die100. A top surface134of the die-side bump130remains substantially smooth. The roughened sidewalls132of the die-side bump130include depressed areas136, such as craters, pits, and valleys, as well as elevated areas138, such as protrusions and peaks.

Turning toFIG. 1E, a C4 process is shown where two die-side bumps130on an IC die100are flip-chip connected to two solder bumps118on a package substrate116. An epoxy underfill material122is injected between the IC die100and the package substrate116to fill-in voids around the die-side bumps130and the solder bumps118. In accordance with the invention, the roughened sidewalls132of the die-side bumps130, namely the depressed areas136and the elevated areas138, tend to mechanically secure or lock the epoxy underfill material122in place, thereby significantly decreasing the likelihood of delamination.

In implementations of the invention, a composite sacrificial material may be used to fabricate the die-side bump130shown inFIG. 1D. In some implementations, the composite sacrificial material includes a photoresist material. Conventional photoresist materials that are well known in the art may be used in implementations of the invention. For instance, specific photoresist materials that may be used include, but are not limited to, acrylic-based photoresists (e.g., JSR THB-150N, manufactured by JSR Micro of Sunnyvale, Calif.), novolak-based photoresists, or polyhydroxystyrene-based photoresists. As is known in the art, the photoresist material may be a positive photoresist or a negative photoresist. In other implementations, the composite sacrificial material may include a sacrificial light absorbing material (SLAM) or a bottom anti-reflecting coating material (BARC).

In accordance with implementations of the invention, the composite sacrificial material may also include a filler material. The filler material may consist of nanoparticles that can disperse and become substantially suspended in the sacrificial material, by either a chemical or a physical means. The size of the filler material (e.g., nanoparticle diameter) and its loading in the sacrificial material may be optimized to provide the desired surface roughness in the die-side bump to be formed. In various implementations of the invention, the particle size of the filler may range from around 10 nanometers (nm) to around 1000 nm. For purposes of this disclosure, particles having an average diameter of between around 10 nm and 1000 nm are considered nanoparticles. In implementations of the invention, the loading of the filler material in the sacrificial material may range from around 5% to around 50%.

In implementations of the invention, the nanoparticles used should be soluble, or at least capable of being removed by, a chemical that may also be used to remove the sacrificial material. For instance, if a photoresist developer solution (e.g., a TMAH solution) is used to remove the sacrificial material, then the selected nanoparticles must also be capable of being removed by the developer solution. In further implementations, surface modifications to the nanoparticles may be used to render insoluble nanoparticles soluble in the chemical used to remove the sacrificial material. Generally, the chemical used to remove the sacrificial material will have a basic pH level, therefore, in most implementations of the invention, the filler material should be base-soluble or at least capable of being removed by a basic solution.

Although a wide variety of filler materials are available, some specific filler materials that may be used in implementations of the invention include, but are not limited to, base-soluble styrene-butadiene rubber (SBR) or nitrile-butadiene rubber (NBR) nanospheres, polystyrene-based nanoparticles, acrylic-based nanoparticles, or inorganic nanoparticles.

FIG. 2is a method200of forming die-side bumps130with roughened sidewalls132and smooth top surfaces134in accordance with an implementation of the invention.FIGS. 3A to 3Fillustrate the various process stages of the method200.

The method200begins with the preparation of a composite sacrificial material (process202ofFIG. 2). In implementations of the invention, the sacrificial material may be a photoresist, a SLAM, a BARC, or another acceptable sacrificial material. A filler material, such as a material that includes nanoparticles, is mixed with the sacrificial material to form the composite sacrificial material. In the method ofFIG. 2, a photoresist material is used as the sacrificial material.

In some implementations, the filler material may be added to the sacrificial material using a batch process. The sacrificial material and the filler material may be combined as a batch and then mixed. In other implementations, the filler material may be added to the sacrificial material using an in-line mixing process. For example, the filler material and the sacrificial material may be combined and mixed in-line prior to being deposited on an IC die or a semiconductor wafer. As described above, the loading of the filler material in the sacrificial material may range from 5% to 50%.

In one specific implementation of the invention, an acrylic-based photoresist is used, such as the JSR THB-150N, with base-soluble SBR or NBR rubber nanospheres added to the photoresist material. In such an implementation, the size of the rubber nanospheres may range from 10 nm to 100 nm and the loading may range from 1% to 25%.

An IC die is provided that includes IC pads upon which the die-side bumps are to be formed (204). The IC pads are electrically conductive surfaces that couple underlying interconnect layers within the IC die to electrical elements outside of the IC die through the die-side bumps. The IC pads may be formed using a metal such as copper or aluminum and may be mounted within a passivation layer. Under-bump metallurgy (UBM) layers may also be formed on the IC die. The UBM layers generally consist of a barrier layer and a metal seed layer. The barrier layer may be formed from conventional barrier materials for UBM layers, such as titanium or tungsten. The metal seed layer may consist of copper metal, or it may consist of another metal such as iridium (Ir), platinum (Pt), palladium (Pd), rhodium (Rh), osmium (Os), gold (Au), silver (Ag), rhenium (Re), ruthenium (Ru), tungsten (W), nickel (Ni), or cobalt (Co). Deposition processes such as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD) may be used to deposit the UBM layers.

FIG. 3Aillustrates an IC die300that includes IC pads302. A passivation layer304is formed around the IC pads302. The passivation layer may be formed using materials such as nitrides, polyimides, oxides, or oxynitrides. A UBM layer consisting of a barrier layer305may be formed over the passivation layer304and the IC pads302. A second UBM layer consisting of a metal seed layer306may be formed upon the barrier layer305. The metal seed layer306is used to catalyze a subsequent electroplating process.

The composite photoresist material is then applied over the metal seed layer on the IC die (206). In implementations of the invention, the composite photoresist material may be applied using a spin-on deposition (SOD) process. This results in a composite photoresist layer being deposited on the IC die.FIG. 3Billustrates the IC die300with a composite photoresist layer308that has been deposited over the metal seed layer306. The composite photoresist layer308includes a plurality of nanoparticles310that form the filler material.

Next, the composite photoresist layer may be patterned to form openings in which die-side bumps may be formed. As is well known in the art, the photoresist may be patterned using a lithography process that irradiates the photoresist layer with ultraviolet (UV) radiation through an optical mask (208). The optical mask contains a pattern for the bump openings and this pattern is transferred into the composite photoresist layer by way of the ultraviolet radiation.

FIG. 3Cillustrates the composite photoresist layer308after it has been exposed to the ultraviolet radiation. If a positive photoresist material is used in the composite photoresist layer308, then portions312of the composite photoresist layer308have been exposed to the radiation while portions314have been masked from exposure. Alternately, if a negative photoresist is used in the composite photoresist layer308, it is portions314that have been exposed to the radiation while portions312have been masked from exposure. In both instances, the portions312define openings in the photoresist layer308that will be used to form the die-side bumps.

In implementations of the invention, the lithography process may be optimized for the filler material used in the composite photoresist. For instance, for larger filler sizes, the lithography process may be optimized to reduce or prevent scattering of the ultraviolet radiation. In one implementation, if the filler material has an average diameter of between around 10 nm and around 100 nm, then ultraviolet radiation having a wavelength of 365 nm (i.e., i-line lithography), 436 nm (i.e., g-line lithography), or 405 nm (i.e., h-line lithography) may be used. In general, an appropriate diameter for the filler material would be a diameter that is smaller than the wavelength of the radiation used, and more specifically, a diameter that is less than one-fourth of the size of the wavelength used.

The composite photoresist layer may then be baked (often referred to as post-exposure bake), thereby assisting any reactions occurring in the photoresist areas that were exposed to radiation (210). The baking process facilitates the chemical conversion of the exposed areas so that exposed and unexposed areas will have different solubility in developer and thus allow the pattern to be developed. For example, in a positive photoresist, baking will facilitate the chemical reaction in portions312that converts the resist from insoluble in developer to soluble in developer. Likewise, in a negative photoresist, baking will facilitate the chemical transformation in portions314that converts the resist from soluble in developer to insoluble in developer.

A developer solution is then applied that removes soluble portions of the composite photoresist layer, leaving behind openings in the composite photoresist layer (212). As described above, the developer solution can be a basic solution that is capable of removing the photoresist material and filler material (in the exposed areas of a positive photoresist or the unexposed areas of a negative photoresist), such as TMAH, potassium hydroxide (KOH), tetrabutyl ammonium hydroxide (TBAH), or a similar basic solution. As such, the developer solution removes the photoresist material as well as the filler material within the area to be opened. Alternatively, organic photoresist developers (such as cyclohexanone, cyclopentanone, or isopropanol) can be used as is commonly known by those skilled in the art.

FIG. 3Dillustrates openings316that are formed when the developer-soluble portions312of the composite photoresist layer308are removed. As shown inFIG. 3D, when the developer-soluble composite photoresist material312is removed, the filler material310imparts a roughed surface to the sidewalls318of the openings316. The roughened sidewalls318include depressed areas and elevated areas. These roughed areas are generally formed due to impressions left in the composite photoresist layer308by the nanoparticles310, as well as embedded nanoparticles310that still remain.

The openings may be cleaned to remove any remaining unwanted material. Next, die-side bumps may be fabricated within the openings in the composite photoresist layer using an electroplating process (214). As known to those of skill in the art, in such an electroplating process, metal layers are deposited within the openings in the composite photoresist layer by putting a negative bias on the IC die and immersing it into a plating bath that contains a salt of the metal to be deposited. The metallic ions of the salt carry a positive charge and are attracted to the metal seed layer on the IC die. When the ions reach the metal seed layer, the negatively charged IC die provides the electrons to “reduce” the positively charged ions to metallic form, thereby causing the metal to become deposited on the metal seed layer. The metal seed layer provides an area of attachment for the metal ions. The use of an electroplating process therefore fills the openings in the composite photoresist layer with a metal that conforms to the roughened sidewalls of the openings while maintaining a smooth top surface.

Copper metal is generally the metal used to fill the openings and form the die-side bumps. In alternate implementations, other metals including, but not limited to, aluminum, tungsten, gold, nickel, cobalt, platinum, palladium, osmium, iridium, ruthenium, rhodium, silver, copper alloys, and lead/tin alloys may be used as well.

FIG. 3Eillustrates copper die-side bumps320that have been formed by using an electroplating process to fill the openings316with copper metal. As shown, the copper die-side bumps320have sidewalls that conform to the roughened sidewalls318of the openings316while maintaining a smooth top surface322.

Once the openings are filled with metal to form the copper die-side bumps, the remaining composite photoresist is removed (216). Conventional processes known for removing remaining photoresist material may be used. One such process uses a solvent or solvent mixture, as is known in the art. Such a process removes both the developer-insoluble photoresist material as well as the remaining filler material. The end result is one or more copper die-side bumps that have roughened sidewalls but smooth top surfaces.

In addition, unnecessary portions of the metal seed layer and underlying barrier layer may also be etched away at this stage in the process. Conventional processes for removing the seed and barrier layers may be used, for instance, using conventional wet or dry etch processes that are well known in the art.

FIG. 3Fillustrates the copper die-side bumps320after the composite photoresist layer308has been removed and exposed portions of the seed and underlying barrier layers have been etched away. The end result is the IC die300with one or more die-side bumps320formed thereon. Generally, the end result is the IC die300with an array of die-side bumps320. And unlike the prior art, the die-side bumps320that are formed in accordance with implementations of the invention have roughened sidewalls324but do not have roughened top surfaces322. Furthermore, the underlying IC die300has not suffered damage by avoiding the use of a microetchant.

The completed die-side bumps320may now be sent through a conventional “flip-chip” packaging process where the roughened surface of the sidewalls324will improve adhesion to an epoxy underfill material. As described above, the roughened sidewalls324improve adhesion because the imperfections in the sidewalls324(e.g., elevated and depressed areas on the die-side bump sidewalls) mechanically secure the epoxy underfill material to the sidewall, substantially locking the epoxy material in place and thereby leading to better reliability performance.