Multipath hybrid regulator

The present document describes a power converter configured to convert electrical power at an input voltage at an input of the power converter to electrical power at an output voltage at an output of the power converter. The power converter comprises a first flying capacitor, a second flying capacitor and a third flying capacitor, as well as an inductor and a set of power switches. Furthermore, the power converter comprises a control unit configured to control the set of power switches such that during an operation cycle the power converter is operated in a first state and in a second state in a mutually exclusive manner.

TECHNICAL FIELD

The present document relates to a DC-DC power converter, in particular to a voltage regulator which is optimized for a 4-to-1-conversion ratio.

BACKGROUND

For many years, the intermediate bus architecture (IBA) has been widely used in data centers and telecommunications systems to step-down the 48V backplane to a 12V bus (4-to-1 conversion ratio). The 4-to-1 conversion ratio may also be used in charger applications, e.g., for converting an input voltage VIN=16V to an output voltage VOUT=4V.

A way to improve efficiency of a Switched Mode Power Supply (SMPS), which comprises a voltage regulator, is to lower the power loss associated with the inductor. This may be achieved by lowering the current ripple and/or the average current. For a single-phase, 2-level, step-down SMPS, the average inductor current is equal to the load current. The ripple current is a function of the conversion ratio (CR) and is minimized (or “nulled”) when CR=0 or 1. “Nulling” means that the voltage across the inductor is so small that the inductor current becomes non-linear. Non-linear inductor current is a characteristic of resonant or quasi-resonant operation. Multilevel Converters (MLCs) provide inductor ripple nulls at additional values of CR. For example, a 3-level converter (3LC) has an additional ripple current null at CR=0.5. In other words, the 3LC essentially operates in resonant or quasi-resonant mode when CR=0.5. A 4-level converter (4LC) has inductor ripple nulls at CR=0.33 and 0.67.

SUMMARY

The present document is directed at the technical problem of providing a power converter, in particular a voltage regulator, which allows for an accurate voltage regulation over a wide operating range, i.e., over a wide range of CR, and which is particularly power efficient at a 4-to-1 conversion ratio.

According to an aspect, a power converter, in particular a voltage regulator, configured to convert electrical power at an (DC) input voltage at an input of the power converter to electrical power at an (DC) output voltage at an output of the power converter. The power converter comprises a first flying capacitor, a second flying capacitor and a third flying capacitor. Furthermore, the power converter comprises an inductor and a set of power switches (e.g., MOSFETs).

In addition, the power converter comprises a control unit configured to control the set of power switches such that during an operation cycle the power converter is operated in a first state and in a second state. The power converter exhibits within the first state a first current path from ground through the second flying capacitor, through the first flying capacitor and through the inductor to the output, and a second current path from the input through the third flying capacitor to the output (without passing through the inductor). The power converter exhibits within the second state a first current path from ground through the third flying capacitor, through the second flying capacitor and through the inductor to the output, and a second current path from ground through the first flying capacitor to the output (without passing through the inductor).

According to a further aspect a corresponding method for operating a power converter is described.

It should be noted that the methods and systems including its preferred embodiments as outlined in the present document may be used stand-alone or in combination with the other methods and systems disclosed in this document. In addition, the features outlined in the context of a system are also applicable to a corresponding method. Furthermore, all aspects of the methods and systems outlined in the present document may be arbitrarily combined. In particular, the features of the claims may be combined with one another in an arbitrary manner.

In the present document, the term “couple” or “coupled” refers to elements being in electrical communication with each other, whether directly connected e.g., via wires, or in some other manner

DESCRIPTION

As indicated above, the present document is directed at providing a voltage regulator which is particularly efficient at a conversion ratio of 4-to-1.

FIG.1Ashows the topology of an example voltage regulator100, which comprises eleven power switches, M1-M11, and an optional 12thpower switch, M12, which may be used for over-voltage protection in a multi-phase application. InFIG.1athe power switches are represented as NMOS (n-type metaloxide semiconductor) switches. It should be noted that other types of switches may be used such as PMOS, bipolar transistors, and/or mechanical switches (e.g., relays).

The switches M1, M2, M3, M7, M10, M11may be arranged in series between the input voltage VIN and ground (GND). The switch M9may be arranged between the node which directly couples M1with M2and the node which directly couples M4and M5. In the present document, the node between two directly adjacent power switches Mx and My is referred to as node Mx/My.

The voltage regulator100comprises a first current path101and a second current path102for providing current to the load at the output of the voltage regulator100. The first current path101comprises an inductor105, and may be used for regulating the output voltage VOUT. The second current path102bypasses the inductor105, thereby lowering the current through the inductor105.

Furthermore, the voltage regulator100comprises a first flying capacitor CFLY1between the node M3/M7and the node M8/M4. In addition, the voltage regulator100comprises a second flying capacitor CFLY2between the node M2/M3and the node M5/M6. In addition, the voltage regulator100comprises a third flying capacitor CFLY3between the node M1/M2and the node M10/M11.

Hence, a single inductor105, dual output path hybrid step-down regulator100with optimized efficiency for 4-to-1 conversion is described. The regulator100comprises an inductor-based hybrid converter (for the first current path101) and a charge pump converter (for the second current path102), which may also be referred to as a switch capacitor converter. The charge pump (on the second current path102) supplements the inductor current (on the first current path101) to deliver the required energy to the load. The hybrid dual path topology reduces the ripple current and the average current of the inductor105, thereby lowering the core loss and the DCR (direct current resistance) loss. The reduced current levels allow for the use of a smaller inductor105and for a reduced PCB (printed circuit board) footprint. The regulator100operates over a relatively wide range of operating conditions, in particular a relatively wide range of CRs. The regulated output voltage VOUT can range from close to 0V to near VIN.

Control of the voltage regulator100may be based on a dual ramp PWM (pulse width modulation) scheme that produces two PWM pulses of equal duration. The duty cycle of the pulses with respect to the switching period (also referred to as an operation cycle) may be designated as a first phase or state D1and as a second phase or state D2. The states D1and D2may be generated using PWM ramps and/or using a digital controller. InFIG.1ba low duty cycle situation is illustrated, where the first state D1111and the second state D1112do not overlap. The intervening interval may be designated as a first intermediate state DV113. InFIG.1ca high duty cycle situation is illustrated, where the first state D1111and the second state D1112overlap. The overlap interval may be designated as a second intermediate state DP123. In addition,FIGS.1band1cillustrate the current114through the inductor105. It should be noted that inFIG.1b, the periods, where the PWM signals111,112are high may be used as duty cycles for D1and D2, respectively. On the other hand, inFIG.1c, the periods, where the PWM signals111,112are low may be used as duty cycles for D1and D2, respectively.

For relatively low conversion ratios (CR=VOUT/VIN) between 0 and 0.5, there are four switch states or phases111,112,113,123which may be used to create a complete switching or operation cycle. These states or phases may be designated as D1111, D2112, DV113and DP123. The different switch states or phases are illustrated inFIGS.2A to2D. The dotted traces correspond to the inductor current path101(which is also referred to as the first current path) towards the load. The dashed traces correspond to the bypass current path102(which is also referred to as the second current path) with current that flows from the input to the output through one or more of the charge pump capacitors CFLY1, CFLY2, CFLY3(without passing through the inductor105). The voltages for the flying capacitors CFLY1and CFLY3may be maintained at VOUT and VIN−VOUT, respectively, by the commutation action of the charge pump stage. The voltage for the flying capacitor CFLY2may be internally controlled to be equal to VIN−2*VOUT, with a minimum value being equal to VOUT (e.g., using the voltage control circuit400which is described in the present document).

FIG.2Aillustrates the first current path101(dotted line) and the second current path102(dashed line) for the first state D1111. In the first state D1111, the optional switch M12is closed. Furthermore, the switches M1, M3, M10, M4, M6are closed. On the other hand, the switches M2, M7, M11, M8, M5are open. Furthermore, M9is open. The first current path101(dotted line) couples the output, via the inductor105, via M4, via CFLY1, via M3, via M6to ground. The second current path102(dashed line) couples the output, via M10, via CFLY3and via M1to the input.

It should be noted that the components which are listed to be on a current path101,102may be the only components which are on the current path101,102. Furthermore, the different components on a current path101,102may be located on the current path101,102in the given order.

During a D1state111(for low CR operation), the external energy storage elements may change as follows:The inductor105is magnetized if the duty cycle D1≤0.5;The inductor105is demagnetized if the duty cycle 0.75≥D1≥0.5;The second flying capacitor CFLY2is discharged; and/orThe first flying capacitor CFLY1and the second flying capacitor CLFY3are charged.

FIG.2Billustrates the first current path101(dotted line) and the second current path102(dashed line) for the second state D2112. In the second state D2112, the optional switch M12may be open or closed. Furthermore, the switches M2, M7, M11, M8, M5are closed. On the other hand, the switches M1, M3, M10, M4, M6are open. Furthermore, M9is open. Hence, the switching state of the switches M1to M11(without M9) in the second state D2112may be opposite to the switching state of the switches M1to M11(without M9) in the first state D1111. The first current path101(dotted line) couples the output, via the inductor105, via M5, via CFLY2, via M2, via CFLY3, via M11to ground. The second current path102(dashed line) couples the output, via M7, via CFLY1and via M8to ground.

During a D2state112(for low CR operation), the external energy storage elements may change as follows:The inductor105remains substantially neutral (and is substantially neither magnetized nor demagnetized) if the duty cycle D1≤0.6;The inductor105is demagnetized if the duty cycle 0.75≥D1≥0.6;The second flying capacitor CFLY2is charged; and/orThe first flying capacitor CFLY1and the third flying capacitor CLFY3are discharged.

FIG.2Cillustrates the first current path101(dotted line) and the second current path102(dashed line) for the intermediate state DV113. In the intermediate state DV113, the optional switch M12is closed. Furthermore, the switches M1, M10, M7, M8, M4, M5, M6are closed. On the other hand, the switches M2, M3, M11are open. Furthermore, M9is open. The first current path101(dotted line) couples the output, via the inductor105, via M4, via M8to ground and/or the inductor105, via M5, via M6to ground. The second current path102(dashed line) couples the output, via M10, via CFLY3and via M1to the input. Furthermore, the second current path102(dashed line) couples the output via M7, via CLFY1, via M8to ground.

During a DV state113, the external energy storage elements may change as follows:The inductor105is demagnetized;The second flying capacitor CFLY2is coupled to an internal circuit to adjust its voltage as needed (as discussed later);The first flying capacitor CFLY1is coupled between VOUT and ground (GND); and/orThe third flying capacitor CFLY3is coupled between VIN and VOUT.

FIG.2Dillustrates the first current path101(dotted line) and the second current path102(dashed line) for the intermediate state DP123. In the intermediate state DP123, the optional switch M12is closed. Furthermore, the switches M1, M7, M10, M8, M6are closed. On the other hand, the switches M2, M3, M11, M4, M5are open. Furthermore, M9is closed. The first current path101(dotted line) couples the output, via the inductor105, via M9, via M1to the input. The second current path102(dashed line) couples the output, via M10, via CFLY3and via M1to the input, and via M7, via CFLY1, via M8to ground.

During a DP state123, the external energy storage elements may change as follows:The inductor150is magnetized;The second flying capacitor CFLY2is coupled to an internal circuit to adjust its voltage as needed (discussed later);The first flying capacitor CFLY1is coupled between VOUT and GND; and/orThe third flying capacitor CFLY3is coupled between VIN and VOUT.

For high conversion ratio operation, where 1≥CR≥0.5, the regulator100undergoes a mode transition and operates as a 3-level converter. The D1and D2switch states are replaced by D13LCand D23LC(which are illustrated inFIGS.3A and3B, respectively). When transitioning from the low CR operation to the high CR operation, the controller for the converter100may make a step change in the duty cycle from 75% to 50%.

FIG.3Aillustrates the first current path101(dotted line) and the second current path102(dashed line) for the modified first state D13LC111. In the first state D13LC111, the optional switch M12may be open or closed. Furthermore, the switches M2, M7, M11, M8, M6are closed. On the other hand, the switches M1, M3, M10, M4, M5are open. Furthermore, M9is closed. The first current path101(dotted line) couples the output, via the inductor105, via M9, via M2, via CFLY2, via M6to ground. The second current path102(dashed line) couples the output, via M7, via CFLY1and via M8to ground. Furthermore, CFLY3is arranged in parallel to CFLY2.

During a D13-LCstate (for high CR operation), the external energy storage elements may change as follows:The inductor105is demagnetized;The second flying capacitor CFLY2is discharged;The first flying capacitor CFLY1is connected in parallel with the output capacitor COUT at the output of the regulator100; and/orThe third flying capacitor CLFY3is connected in parallel with the second flying capacitor CFLY2.

FIG.3Billustrates the first current path101(dotted line) and the second current path102(dashed line) for the modified second state D23LC112. In the second state D23LC112, the optional switch M12is closed. Furthermore, the switches M1, M2, M7, M10, M8, M5are closed. On the other hand, the switches M3, M11, M4, M6are open. Furthermore, M9is open. The first current path101(dotted line) couples the output, via the inductor105, via M5, via CFLY2, via M2, via M1to the input. The second current path102(dashed line) couples the output, via M7, via CFLY1, via M8to ground. Furthermore, CFLY3is arranged between the input and the output via the M10and M1.

During a D23LCstate (for high CR operation), the external energy storage elements may change as follows:The inductor105is demagnetized;The second flying capacitor CFLY2is charged;The first flying capacitor CFLY1is connected in parallel with COUT; and/orThe third flying capacitor CLFY3is connected between the input and the output.

As can be seen inFIGS.3A and3B, the flying capacitors CFLY1and CFLY3do not commutate during 3-level operation. They remain static, and only CFLY2commutates. The switching pattern for relatively high CR may be D13LC→DP→D23LC→DP→D13LC→ ⋅ ⋅ ⋅ . The voltages of the flying capacitors CFLY1and CFLY3are maintained at the same level as for low CR operation. The voltage for CFLY2may be maintained to be equal VIN−VOUT. This is accomplished by the fact that CFLY2is coupled in parallel with CFLY3during the D13LCstate. It should also be noted that the CFLY2voltage at 75% duty cycle for low CR operation is the same as at 50% duty cycle for high CR operation (which is also referred to herein as the 3LC mode). This means that CFLY2typically does not undergoes a voltage change during a mode change from low CR operation to high CR operation.

In order to avoid inadvertent body diode conduction during 3-LC operation, switches M2and M3should be replaced by back-to-back switches M2a/band M3a/b, respectively. Table 1 shows different operation modes of the power converter100. The DV modes comprise the states D1, D2and DV. The DP1and DP2modes comprise the states D1, D2and DP. The 3-LC mode comprises the states D13LC, D23LCand DP. It should be noted that the duty cycle of D1is equal to the duty cycle of D2.

It can be shown that the inductor current null (i.e., the quasi-resonant mode) occurs at a duty cycle of 50%. This corresponds to CR=0.25 for the hybrid dual path mode (i.e., DV or DP1) and CR=0.5 for the 3-LC mode. For both modes of operation, the inductor current ripple is lower than the ripple from a conventional 2-level buck converter.

Furthermore, it can be shown that the charge pump output102of the dual path topology supplies a significant portion of the total load current. This alleviates the current requirements for the inductor105, especially around the middle range of duty cycles (around 50%).

FIG.4shows an example voltage control circuit400for controlling the voltage across the second flying capacitor CFLY2. The output port401of the circuit400is coupled to the node M2/M3which is coupled to the second flying capacitor CFLY2. The circuit400may be used (e.g., only) during low CR operation (e.g., the DV, DP1or DP2modes), where the target voltage for CFLY2is VIN−2*VOUT with a minimum limit of VOUT. A difference amplifier402senses the voltage across the second flying capacitor CFLY2. Over and under voltage (OV, UV) comparators403,404monitor the output of the difference amplifier402. If V(CFLY2) exceeds VIN−2*VOUT+VTOLERANCE, the OV comparator404turns on an internal switch406connected in parallel with the second flying capacitor CFLY2. This removes excess charge from the second flying capacitor CFLY2. If V(CFLY2) falls below VIN−2*VOUT−VTOLERANCE, the UV comparator403turns on a switch405connected between VMID (or VIN) and CFP2. This adds charge to the second flying capacitor CFLY2. The UV switch405is restricted to turn on only during a DV or DP event when the second flying capacitor CFLY2is floated. In lieu of comparators, an ADC (Analog-to-Digital Converter) in conjunction with a digital controller may be used to determine when to turn on/off the CFLY2charge maintenance switches405,406. Controlled current sources may be used in place of the switches405,406.

During high CR operation (i.e., 3-level converter mode), the CFLY2voltage control is not needed and may be disabled. This is because the second flying capacitor CFLY2is connected in parallel with the third flying capacitor CFLY3during D13-LC. The third flying capacitor CFLY3is connected between VIN and VOUT during D23-LC, DV and DP. This combination of switch states results in charge redistribution which ensures a second flying capacitor CFLY2that is maintained at VIN−VOUT.

FIG.5shows a flow chart of an example method500for operating a power converter100. The power converter100is configured to convert electrical power at an (DC) input voltage VIN at an input of the power converter100to electrical power at an (DC) output voltage VOUT at an output of the power converter100.

The power converter100may comprise a first flying capacitor CFLY1, a second flying capacitor CFLY2and a third flying capacitor CFLY3. Furthermore, the power converter100may comprise an inductor105, and a set of power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6.

The method500comprises controlling501the set of power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6such that during an operation cycle the power converter100is operated in a first state D1and in a second state D2in a mutually exclusive manner. The power converter100may be operated in a sequence of (identical) operation cycles. An operation cycle may have a fixed duration. The duty cycles of the first and/or second state D1, D2within the different operations cycles may vary (e.g., in order to regulate the conversion ratio of the power converter100to a target conversion ratio, such as 0.25).

The set of power switches may be controlled such that within the first state D1, the power converter100exhibits a first current path101from ground through the second flying capacitor CFLY2, through the first flying capacitor CFLY1and through the inductor105to the output (no other components (apart from closed power switches) may be located on the first current path101). Furthermore, the set of power switches may be controlled such that within the first state D1, the power converter100exhibits a second current path102from the input through the third flying capacitor CFLY3to the output (no other components (apart from closed power switches) may be located on the second current path102). The different components may be located on the respective current path101,102in the listed order.

The set of power switches may be controlled such that within the second state D2, the power converter100exhibits a first current path101from ground through the third flying capacitor CFLY3, through the second flying capacitor CFLY2and through the inductor105to the output (no other components (apart from closed power switches) may be located on the first current path101). Furthermore, the set of power switches may be controlled such that within the second state D2, the power converter100exhibits a second current path102from ground through the first flying capacitor CFLY1to the output (no other components (apart from closed power switches) may be located on the second current path102). The different components may be located on the respective current path101,102in the listed order.

Hence, a (DC-DC) power converter100, in particular a voltage regulator, configured to convert electrical power at an input voltage VIN at an input of the power converter100to electrical power at an output voltage VOUT at an output of the power converter100is described. The power converter100may comprise a first flying capacitor CFLY1, a second flying capacitor CFLY2and a third flying capacitor CFLY3. Furthermore, the power converter100may comprise an inductor105, and a set of power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6(e.g., field effect transistors, FETs).

The set of power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6may comprise a series of power switches which are arranged in series between the input voltage VIN and ground (GND). In particular, the set of power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6may comprise: a first power switch M1with an input node (directly) coupled to the input (of the power converter100) and an output node (directly) coupled to a second power switch M2; the second power switch M2with an input node (directly) coupled to the output node of the first power switch M1and an output node (directly) coupled to a third power switch M3; the third power switch M3with an input node (directly) coupled to the output node of the second power switch M2and an output node (directly) coupled to a seventh power switch M7; the seventh power switch M7with an input node (directly) coupled to the output node of the third power switch M3and an output node (directly) coupled to a tenth power switch M10; the tenth power switch M10with an input node (directly) coupled to the output node of the seventh power switch M7and an output node (directly) coupled to an eleventh power switch M11; the eleventh power switch M11with an input node (directly) coupled to the output node of the tenth power switch M10and an output node (directly) coupled to an eighth power switch M8;

the eighth power switch M8with an input node (directly) coupled to the output node of the eleventh power switch M11and an output node (directly) coupled to a fourth power switch M4; the fourth power switch M4with an input node (directly) coupled to the output node of the eighth power switch M8and an output node (directly) coupled to a fifth power switch M5; the fifth power switch M5with an input node (directly) coupled to the output node of the fourth power switch M4and an output node (directly) coupled to a sixth power switch M6; and/or the sixth power switch M6with an input node (directly) coupled to the output node of the fifth power switch M5and an output node (directly) coupled to ground.

The inductor105may be arranged (directly) between the output node of the fourth switch M4and the output of the power converter100. Alternatively, or in addition, the first flying capacitor CFLY1may be arranged (directly) between the output node of the third switch M3and the output node of the eighth switch M8. Alternatively, or in addition, the second flying capacitor CFLY2may be arranged (directly) between the output node of the second switch M2and the output node of the fifth switch M5. Alternatively, or in addition, the third flying capacitor CFLY3may be arranged (directly) between the output node of the first switch M1and the output node of the tenth switch M10.

Furthermore, the power converter100may comprise a nineth power switch M9with an input node (directly) coupled to the output node of the first power switch M1and an output node (directly) coupled to the input node of the fifth power switch M5.

The power converter100comprises a control unit120which is configured to control the set of power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6such that during an operation cycle the power converter100is operated in a first state D1and in a second state D2in a mutually exclusive manner. In particular, the control unit120may be configured to control the set of power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6during a sequence of subsequent operation cycles, wherein each operation cycle comprises a (exactly one) first state D1and a (exactly one) second state D2.

Alternatively, or in addition, the control unit120may be configured to control the set of power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6such that the first state and the second state are repeated in an alternating manner, and/or such that the duty cycle and/or the duration of the first state D1is equal to the duty cycle and/or the duration of the second state D2.

The repeated operation of the power converter100in different states may be used to regulate the output voltage VOUT to a target voltage and/or to regulate the conversion ratio to a target conversion ratio. In particular, the control unit120may be configured to regulate the output voltage VOUT to one fourth of the input voltage VIN. Alternatively, or in addition, the control unit120may be configured to set, in particular to regulate, the target conversion ratio between the input voltage VIN and the output voltage VOUT, in particular to a target conversion ratio of 0.25. In particular, the control unit120may be configured to adjust the duty cycle of the first state and of the second state to modify the conversion ratio between the input voltage VIN and the output voltage VOUT.

The power converter100exhibits within the first state D1a first current path101from ground through the second flying capacitor CFLY2, through the first flying capacitor CFLY1and through the inductor105to the output.

In the present document, the current may flow through a current path101,102in the direction indicated by the order of the different components on the respective current path101,102. Furthermore, there may be no other components on a current path101,102(apart from the listed ones and apart from closed power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6, M9, M12).

Furthermore, the power converter100exhibits within the first state D1a second current path102from the input through the third flying capacitor CFLY3to the output.

The control unit120may be configured to cause the first power switch M1, the third power switch M3, the tenth power switch M10, the fourth power switch M4and the sixth power switch M6to be closed; and to cause the second power switch M2, the seventh power switch M7, the eleventh power switch M11, the eighth power switch M8and the fifth power switch M5to be open, for putting the power converter100in the first state D1.

On the other hand, the power converter100may exhibit within the second state D2a first current path101from ground through the third flying capacitor CFLY3, through the second flying capacitor CFLY2and through the inductor105to the output. Furthermore, the power converter100may exhibit within the second state D2a second current path102from ground through the first flying capacitor CFLY1to the output.

The control unit120may be configured to cause the first power switch M1, the third power switch M3, the tenth power switch M10, the fourth power switch M4and/or the sixth power switch M6to be open; and to cause the second power switch M2, the seventh power switch M7, the eleventh power switch M11, the eighth power switch M8and/or the fifth power switch M5to be closed, for putting the power converter100in the second state D2.

The first state D1may be such that the inductor105is magnetized, the second flying capacitor CFLY2is discharged, the first flying capacitor CFLY1is charged and/or the third flying capacitor CFLY3is charged. The second state D2may be such that the inductor105remains neutral, the second flying capacitor CFLY2is charged, the first flying capacitor CFLY1is discharged and/or the third flying capacitor CFLY3is discharged.

It can be shown that the power converter100can be operated in a particularly efficient manner with a conversion ratio of 0.25.

The control unit120may be configured to control the set of power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6such that during an (in particular during each) operation cycle the power converter100is operated in a first intermediate state DV, which in particular lies in between the first state D1and the second state D2and/or in between the second state D2and the first state D1. As such, the power converter100may be operated repeatedly in the states D1, DV, D2, DV. In other words, an operation cycle may (exactly) comprise the D1, DV, D2, DV.

The power converter100may exhibit within the first intermediate state DV a first current path101from ground through the inductor105to the output, and/or a second current path102from the input through the third flying capacitor CFLY3to the output, and from ground through the first flying capacitor CFLY1to the output. The power switches may be controlled as outlined in the context ofFIG.2c. By making use of a first intermediate state, the conversion ratio may be regulated to a target conversion ratio in a particularly precise and robust manner.

Alternatively, or in addition, the control unit120may be configured to control the set of power switches M1, M2, M3, M7, M10, M11, M8, M4, M5, M6such that during an (in particular during each) operation cycle the power converter100is operated in a second intermediate state DP, which in particular lies in between the first state D1and the second state D2and/or in between the second state D2and the first state D1. As such, the power converter100may be operated repeatedly in the states D1, DP, D2, DP. In other words, an operation cycle may (exactly) comprise the D1, DP, D2, DP.

The power converter100may exhibit within the second intermediate state DP a first current path101from input through the inductor105to the output, and/or a second current path102from the input through the third flying capacitor CFLY3to the output, and from ground through the first flying capacitor CFLY1to the output. The power switches may be controlled as outlined in the context ofFIG.2d. By making use of a second intermediate state, the conversion ratio may be regulated to a target conversion ratio in a particularly precise and robust manner.

The power converter100may comprise a voltage control circuit400which is configured to set the voltage across the second flying capacitor CFLY2to a target voltage. The target voltage may be the input voltage VIN minus two times the output voltage VOUT. By making use of a voltage control circuit400the precision and robustness of the power converter100can be further increased.

The control unit120may be configured to determine whether the target conversion ratio between the input voltage VIN and the output voltage VOUT is equal to or smaller than 0.5, or greater than 0.5. The power converter100may be operated alternately in the first state D1and in the second state D2, if the target conversion ratio is equal to or smaller than 0.5.

On the other hand, the power converter100may be operated alternately in a modified first state D13LC(as outlined in the context ofFIG.3a) and in a modified second state D23LC(as outlined in the context of Fig. b), if the target conversion ratio is greater than 0.5. The power converter100may exhibit within the modified first state D13LCa first current path101from ground through the second flying capacitor CFLY2and through the inductor105to the output, and/or a second current path102from ground through the first flying capacitor CFLY1to the output. Furthermore, the power converter100may exhibit within the modified second state D23LCa first current path101from the input through the second flying capacitor CFLY2and through the inductor105to the output, and/or a second current path102from the input through the third flying capacitor CFLY3to the output, and from ground through the first flying capacitor CFLY1to the output. As a result of this, an efficient power conversion at relatively high conversion ratios is enabled.