Image signal processor for obtaining digital image signals

An analog image signal is converted into a digital image signal which is in turn subjected to various types of processing procedures. The resulting digital image data is added to synchronizing data having the same range of data change as that of the image data to generate image data containing the synchronizing data. This image data is then converted into an analog image signal. An offset signal is applied to the analog image signal to adjust the voltage level of the synchronizing signal for obtaining an image signal containing a correct synchronizing signal.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to an image signal processor for treating 
image signals from an image sensor as digital data. 
2. Description of the Prior Art 
In general, a composite video signal for color image is obtained by 
subjecting color component signals (R, G and B) representing three primary 
colors of red, green and blue to color difference matrix, balanced 
adjustment and so on. These processes are carried out by such an image 
signal processor as shown in FIG. 1, which is called a "color encoder". 
A color separation circuit 1 is adapted to break down image signals (Y1), 
including color components of three primary colors (or combinations with 
their complementary colors) repeated in a given sequence, to the 
respective components in order to generate independent color component 
signals (R, G and B). The image signals (Y1) are provided by the outputs 
of an image sensor which may include a color filter comprising red-, 
green- and blue-color filters arranged in a mosaic and have a vertical 
scan cycle formed by a predetermined number of horizontal scan lines and a 
horizontal scan cycle formed by a predetermined number of image data. A 
white balance adjustment circuit 2 is adapted to provide a gain inherent 
in the respective one of the color component signals (R, G and B) to 
equalize the average level of each of the color component signals (R, G 
and B) such that the white color of a white-colored object can be 
reproduced on a reproduced scene. The white balance adjustment circuit 2 
may be feedback controlled to approximate the integrated values of color 
difference signals (R-Y and B-Y), which will be described later, to 
predetermined values. A color difference matrix circuit 3 receives three 
types of color component signals (R, G and B) from the white balance 
adjustment circuit 2 and combines these color components in a given 
proportion (R:30%, G:59% and B:11%) to generate a brightness signal 
(Y:Y=0.3R+0.59G+0.11B). The circuit 3 is further adapted to subtract the 
brightness signal (Y) from two color component signals (R and B), in order 
to generate two types of color difference signals (R-Y and B-Y). A 
modulation circuit 4 is adapted to modulate the amplitudes of two color 
subcarriers (SC1 and SC2) different from each other by 90 degrees, with 
the color difference signals (R-Y and B-Y) so as to combine them to 
generate a chromatic signal (C). 
A color burst signal generation circuit 5 is adapted to generate a color 
burst signal (CB). This color burst signal (CB) has a given phase 
difference from the color subcarriers (SC1 and SC2) with the same cycle as 
those of these color subcarriers and is generated through every 8 or 9 
cycles at a given timing in the horizontal blanking term. An addition 
circuit 6 adds the chromatic signal (C) and brightness signal (Y) to the 
color burst signal (CB) and a composite synchronizing signal (CS) supplied 
from a synchronizing signal generation circuit 7, which will be described 
later, to generate an image signal (Y2) according to a television system. 
The synchronizing signal generation circuit 7 generates various types of 
sync-signals according to a reference clock (CK) which has a frequency 
defined by the television system such as NTSC, or SECAM. These 
sync-signals are then supplied to the respective units to synchronize them 
in operation. At the same time, the synchronizing signal generation 
circuit 7 generates two different color subcarriers (SC1 and SC2) from the 
reference clock (CK), which are in turn supplied to the modulation circuit 
4. 
As shown in FIG. 2, the image signal (Y2) thus generated includes 
continuous image data corresponding to one horizontal line for every 
horizontal scan cycle and also includes a color burst signal (CB) and a 
horizontal synchronizing signal (HD) which are inserted into a horizontal 
blanking term partitioning between horizontal scan cycles adjacent to each 
other. 
In recent TV camera systems or the like, it has been considered to replace 
the conventional image signal processors which use analog signal 
processing procedure with an image signal processor that uses a digital 
signal processing procedure which can be more easily adjusted and provides 
less degradation of the image signal. In such a case, the image signal 
(Y1) is subjected to analog/digital (A/D) conversion at the input step 
such that the color component signals (R, G and B) and color difference 
signals (R-Y and B-Y) can be handled as digital data during the respective 
signal processing procedures. After a given processing procedure has been 
completed, the signals are subjected to digital/analog (D/A) conversion to 
form the image signal (Y2). 
It is to be noted herein that the image signal (Y2) shown in FIG. 2 is 
formed by image components (including brightness and color components) and 
synchronizing components (including scan timing and color 
synchronizations) which are different from each other in terms of the 
range of voltage to be taken. When the signal is handled as digital data, 
therefore, the gradation representing the image components becomes 
insufficient depending on the resolution of the D/A conversion circuit. 
Since the image and synchronous components of the image signal (Y2) are 
different from each other, the range of voltage substantially assigned to 
the image components becomes smaller than the range of reference voltage 
if the maximum and minimum voltages that can be taken by the image signal 
(Y2) are selected as reference voltages in the D/A conversion circuit. 
Even if the resolution of the D/A conversion circuit is sufficient, 
therefore, the gradation will be reduced by a reduced range of voltage 
assigned to the image components. 
SUMMARY OF THE INVENTION 
It is therefore an object of the present invention to provide an image 
signal processor for treating image signals as digital data, which can 
make sufficient use of the resolution of the D/A conversion circuit and 
secure the gradation of the image signals. 
According to the present invention, a given offset is provided to an image 
signal from the D/A conversion circuit through a horizontal blanking term 
into which the synchronizing components are inserted. Thus, the image 
components can have their range of voltage different from that of the 
synchronizing components at the output side of the D/A conversion circuit, 
even if they exhibit the same range of voltage at the input side. 
Therefore, the whole range of reference voltage from the maximum to 
minimum level in the D/A conversion circuit can be matched to the image 
components, thereby using the gradation capable of being represented by 
the D/A conversion circuit relative to the image components. 
The present invention is particularly effective for color image signal 
processing, but may be similarly applied to monochrome image signals. 
Further, the present invention may be similarly applied to digital input 
image data.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 3 is a block diagram of an image signal processor according to the 
present invention. 
An A/D conversion circuit 11 is adapted to convert an image signal (Y1) 
into digital output image signal data (D1) for every one pixel. The image 
signal (Y1) is provided by the output of an image sensor as in FIG. 1 and 
may contain the color components of three primary colors repeated in a 
given sequence, for example. A color separation circuit 12 receives the 
image data (D1) from the A/D conversion circuit 11 and separates it into 
the respective color components for generating independent color component 
data (R1, G1 and B1). A white balance adjustment circuit 13 multiplies the 
color component data (R1, G1 and B1) by their inherent gain data to 
generate color component data (R2, G2 and B2) having an equalized average 
level within a given cycle. The white balance adjustment circuit 13 is 
feedback controlled to set the gain data such that the integrated value of 
color difference data (RY and BY) approximates to a given value. A color 
difference matrix circuit 14 fetches three types of color component data 
(R2, G2 and B2) subjected to the white balance adjustment to multiply them 
by given coefficients (R2.times.0.30, G2.times.0.59 and B2.times.0.11). 
Thereafter, these data are summed to generate brightness data 
(YD=0.30R2+0.59G2+0.11B2). At the same time, the color difference matrix 
circuit 14 subtracts the brightness data (YD) from the color component 
data (R2 and B2) to generate two different color difference data (RY=R2-Y 
and BY=B2-Y). A modulation circuit 15 causes these color difference data 
(RY and BY) to be subjected to the modulation to generate chromatic data 
(CD). Such a modulation is carried out by modulating the amplitudes of the 
two color subcarriers, different in phase from each other by 90 degrees, 
with the color difference data (R-Y and B-Y) in the normal signal 
processing procedure. However, the modulation will be made relative to the 
digitized color difference data (RY and BY) in the following manner. To 
perform the same procedure as in the modulation of the amplitudes of the 
color subcarriers, as shown in FIG. 4, the color difference data (RY) may 
be sampled through a sampling clock having its frequency equal to four 
times that of color subcarriers in a repeated sequence of (RY), 0, -(RY), 
0 and (RY) as described. Similarly, the color difference data (BY) may be 
sampled through a sampling clock having its frequency equal to four times 
that of color subcarriers in a repeated sequence of 0, (BY), 0, -(BY) and 
0 as described. The addition of all such sampled data can provide 
chromatic data (CD). In the actual process, the chromatic data (CD) can be 
generated by matching the sampled data of (RY), (BY), -(RY), -(BY), (RY) 
etc. to the color difference data (RY and BY). 
A synchronizing data generation circuit 16 generates color burst data (BD) 
corresponding to the color sync-signals in synchronism with the chromatic 
data (CD). The color burst data (BD) may be formed, for example, by data 
repeated in a sequence of 0, 1, 0, -1, 0 according to data corresponding 
to sampled data which are provided by sampling color sync-signals of a 
frequency equal to 3.58 MHz for an NTSC system with a reference clock of 
frequency equal to four times 3.58 MHz, namely, a frequency equal to 14.32 
MHz. The color burst data (BD) has a phase difference from that of the 
chromatic data (CD) and is generated by every 32-36 data at a special 
timing in the horizontal blanking term. The synchronizing data generation 
circuit 16 further generates a composite synchronizing data (SD) 
corresponding a composite synchronizing signal which is provided by 
combining the vertical and horizontal sync-signals. 
The composite synchronizing data (SD) is provided by digitizing such a 
composite synchronizing signal as is shown in FIG. 6. The composite 
synchronizing signal is represented by "0" in a period from a trailing 
edge to the next leading edge and by "1" in another period from a leading 
edge to the next trailing edge. More particularly, the composite 
synchronizing signal becomes "0" during a section representing the 
horizontal synchronizing signal and "1" during another period representing 
the remaining section. Within the vertical blanking term, the composite 
synchronizing signal becomes "0" during a section representing equivalent 
pulses in a cycle equal to one-half the horizontal scan and "1" during the 
remaining section. Within a period representing vertical synchronizing 
pulses in part of the vertical blanking term, the composite synchronizing 
signal becomes "1" during a period representing serrated pulses of the 
same cycle as the equivalent pulses and "0" during the remaining section. 
Although these color burst data (BD) and composite synchronizing data (SD) 
have been described as being represented by data of 1, 0 and -1, they are 
actually matched to digital data of suitable bits which depend on the 
amplitudes of the color and composite synchronizing signals and represent 
the same range of voltage as can be taken by the image components. 
An addition circuit 17 adds the brightness and chromatic data (YD, CD) to 
the color and composite synchronizing data (BD, SD) to generate image data 
(D2). A D/A conversion circuit 18 sequentially converts the image data 
into analog values to form an output image signal (Y2). The image signal 
(Y2) from the D/A conversion circuit 18 has the color burst signal (CB) 
corresponding to the color burst data (BD) and the horizontal 
synchronizing signal (HD) corresponding to the composite synchronizing 
data (SD) all of which are represented substantially by the same range of 
voltage as in the image components, as shown in FIG. 7. An offset voltage 
generation circuit 19 is responsive to a horizontal blanking signal (HB) 
from a timing control circuit 21, which will be described later, to 
generate an offset voltage V.sub.OF (negative voltage) concurrent with the 
horizontal blanking term of the image signal (Y2), such an offset voltage 
then being applied to a voltage addition circuit 20. The voltage addition 
circuit 20 adds the offset voltage V.sub.OF to the horizontal blanking 
term of the image signal (Y2) to form an output image signal (Y3) whose 
color and horizontal synchronizing signals (CB, HD) are represented by a 
range of voltage lower than that of the image components, as shown in FIG. 
7. However, a positive offset voltage may be added to a cycle other than 
the horizontal trace line cycle of the image signal (Y2), rather than the 
addition of the negative offset voltage to the horizontal trace line 
cycle. 
The timing control circuit 21 generates various types of timing signals 
based on a reference clock (CK) which has its frequency defined by the 
television system used. These timing signals are supplied to the 
respective units to synchronize the color separation circuit 12, 
modulation circuit 15, synchronizing data generation circuit 16 and offset 
voltage generation circuit 19 during operation. For example, the timing 
control circuit 21 may provide a horizontal scan cycle timing signal to 
the synchronizing data generation circuit 16 produce data for every 
horizontal blanking term. The timing control circuit 21 also generates and 
provides horizontal and vertical scan synchronizing signals to the image 
sensor such that the scan timing of the image sensor will be synchronized 
with the operations of the respective units. Thus, the image signal (Y1) 
inputted into the A/D conversion circuit 11 will be synchronized with the 
operations of the respective units to process the signals at an 
appropriate timing. 
Although the above embodiment has been described as to the output side D/A 
conversion circuit 18 which is of voltage type, the D/A conversion circuit 
18 may be replaced by another D/A conversion circuit which is of current 
type such as current addition or the like. In such a case, the offset 
voltage generation circuit 19 may be replaced by a source of constant 
current while the voltage addition circuit 20 may be replaced by a current 
addition circuit. 
If the image signal (Y1) inputted into the A/D conversion circuit 11 
represents a monochrome image, the white balance adjustment and modulation 
are not required while the color burst signal (CB) is also not required. 
Therefore, the offset voltage V.sub.OF may be added as a synchronizing 
signal (CS). 
More particularly, as shown in FIG. 8, the A/D conversion circuit 11 
converts the image signal (Y1) only comprising the brightness signal into 
the digital image signal (D1) which is in turn inputted into a signal 
processing circuit 30. The signal processing circuit 30 applies digital 
treatments such as contrast adjustment and others to the image data. An 
image signal (D2) obtained by the signal processing circuit 30 is then 
converted by the D/A conversion circuit 18 into an analog image signal 
(Y2) which is in turn inputted into an adder 20. The adder 20 has received 
the offset voltage V.sub.OF which is added to the image signal (Y2) to 
form an image signal (Y3) containing the horizontal synchronizing signal 
(HD). 
As shown in FIG. 9, the image signal (Y2) from the D/A conversion circuit 
18 does not contain any brightness component during the horizontal 
blanking cycle. The timing control circuit 21 provides a horizontal 
synchronizing signal (CS) to the offset voltage generation circuit 19. The 
offset voltage generation 19 is responsive to the horizontal synchronizing 
signal (CS) to generate the offset voltage V.sub.OF used to apply the 
horizontal synchronizing signal (HD) to the image signal. The offset 
voltage V.sub.OF is then supplied to the adder 20 wherein it is added to 
the image signal (Y2) to form the image signal (Y3). 
When the offset voltage generation circuit 19 is actuated by the 
synchronizing signal (CS) in place of the horizontal blanking signal (HB), 
it can provide the image signal (Y3) to which the horizontal synchronizing 
signal (HD) has been added. 
If the voltage of the image signal (Y2) is at an unacceptable level during 
the horizontal blanking cycle, another offset voltage V.sub.OF2 different 
from that of the horizontal synchronizing signal may be applied to the 
horizontal blanking cycle to adjust the voltage level during the 
horizontal blanking cycle. 
Although the above embodiments have been described as to conversion of the 
image signal (Y1) from the image sensor or the like into the digital image 
signal (D1), the latter may be generated directly by a personal computer 
or the like. 
According to the present invention, an offset is added to the horizontal 
blanking term of the image signal at the output side of the D/A conversion 
circuit to assign all the voltages taken out from between two reference 
voltages which are given by the D/A conversion circuit to the image 
components of the image signal. As a result, the resolution of the D/A 
conversion circuit can be effectively used without reduction of the 
gradation that can be represented by the D/A conversion circuit.