Method for fabricating source/drain devices

A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor process, and more particularly to a source/drain (S/D) device fabrication process used in a high voltage circuit element.

2. Description of the Related Art

FIGS. 1 a to 1 i are cross-sections of the conventional method for fabricating S/D device.

In FIG. 1 a , a semiconductor substrate 101 , such as silicon, is provided, and a first isolation area 105 a and a second isolation area 105 b are formed thereon. A pad layer 102 , such as oxide, a conductive layer 103 , such as poly, and a first patterned photo resist layer 104 are sequentially formed in the area between the first isolation area 105 a and the second isolation area 105 b . The area surrounding the isolation area areas is an active area (AA).

In FIG. 1 b , after the conductive layer 103 is etched using the first patterned photo resist layer 104 as a mask to form a gate 103 a , the first patterned photo resist layer 104 is removed. Then, the area of the semiconductor substrate 101 between the gate 103 a and the first isolation area 105 a is doped to form a lightly doped area 106 .

In FIG. 1 c , an isolating layer 107 , such as nitride, is conformably formed on the surface of the pad layer 102 and the gate 103 a.

In FIG. 1 d , the isolating layer 107 is isotropically etched to form a spacer 107 a on the sidewall of the gate 103 a.

In FIG. 1 e , a second patterned photo resist layer 108 having a first opening 109 a and a second opening 109 b is formed on the semiconductor substrate 101 . The first opening 109 a is positioned in the area between the gate 103 a and the first isolation area 105 a , and the second opening 109 b is positioned in the area between the gate 103 a and the second isolation area 105 b.

First ion implantation is performed on the semiconductor substrate 101 using the second patterned photo resist layer 108 as a mask with As or B ions.

FIG. 2 is a top view of FIG. 1 e . In FIG. 2 , part of the active area and half the width of the gate 103 a are exposed by the first opening 109 a in the second patterned photo resist layer 108 .

In FIG. 1 f , a first doped area 110 a is formed at the bottom of the first opening 109 a and a second doped area 110 b is formed at the bottom of the second opening 109 b . After the first ion implantation, the second patterned photo resist layer 108 is removed.

In FIG. 1 g , a third patterned photo resist layer 111 having a third opening 112 is formed on the semiconductor substrate 101 , and half the width of the gate 103 a is exposed by the third opening 112 in the third patterned photo resist layer 111 . The third opening 112 is positioned in the area between the gate 103 a and the second isolation area 105 b.

Second ion implantation is performed on the semiconductor substrate 101 using the third patterned photo resist layer 111 as a mask and the semiconductor substrate 101 is annealed with As or B ions.

FIG. 3 is a top view of FIG. 1 f . In FIG. 3 , part of the active area and half the width of the gate 103 a are exposed by the first opening 112 in the third patterned photo resist layer 111 , and the area between the gate 103 a and the first isolating 105 a is covered with the third patterned photo resist layer 111 .

In FIG. 1 h , a deeply doped area 113 is formed at the bottom of the third opening 112 . After the second ion implantation, the third patterned photo resist layer 111 is removed. The deeply doped area 113 is 6-7 times the depth of the first doped area 11 a and the second doped area 110 b . The deeply doped area 113 expands after annealing, such that the depth and the width of the deeply doped area 113 are both increased. When the deeply doped area 113 increases, the concentration of dopant inside the deeply doped area 113 decreases and the breakdown voltage of the deeply doped area 113 increases accordingly.

By varying the energy of the ions to form the deeply doped area 113 in the semiconductor substrate 101 , implantation depth into the substrate can be controlled. Meanwhile, the ions also penetrate the gate 103 a and the spacer 107 a into the semiconductor substrate 101 , and the size increases after annealing.

The channel between the S/D consisting of the first doped area 110 a and another S/D consisting of the second doped area 110 b and deeply doped area 113 is decreased, resulting in Short Channel Effect. When the two S/D devices are both deeply doped areas, the channel between the S/D devices below the gate 103 a and spacer 107 a punches through, such that electrons are injected into the channel from source region before applying a gate voltage.

SUMMARY OF THE INVENTION

The present invention is directed to a method for fabricating source/drain devices in a high voltage circuit element without additional process.

Accordingly, the present invention provides a method for fabricating a source/drain device, in which, first, a semiconductor substrate having a gate is provided. A hard mask layer is formed on the gate. A first doped area is positioned on a first side of the gate on the semiconductor substrate, and a second doped area is positioned on a second side of the gate on the semiconductor substrate and spaced between. A patterned photo resist layer having an opening on the second side of the gate is formed on the semiconductor substrate, and the exposed gate is equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.

Accordingly, the present invention also provides a method for fabricating source/drain devices. A silicon substrate having a gate is provided. A hard mask layer is formed on the gate. A first doped area is positioned on a first side of the gate on the silicon substrate, and a second doped area is positioned on a second side of the gate on the silicon substrate and spaced between. A patterned photo resist layer having an opening on the second side of the gate is formed on the semiconductor substrate, and the width of the exposed gate is equal to half the width of the gate. The silicon substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.

Accordingly, the present invention also provides a method for fabricating a source/drain device. A semiconductor substrate having a pad layer over the semiconductor substrate, a gate formed on the pad layer, a hard mask layer over the gate, a first isolation area positioned on a first side of the gate, and a second isolation area positioned on a second side of the gate, is provided. The gate has a spacer on the sidewall of the gate. A first patterned photo resist layer is formed. Ions are implanted into the semiconductor substrate to form a first doped area and a second doped area using the patterned photo resist as a mask. The first doped area is positioned between the gate and the first isolation area, and the second doped area is positioned between the gate and second isolation area. A second patterned photo resist layer having an opening on the second side between the gate and the second isolation area is formed on the semiconductor substrate. The width of the exposed gate is equal to half the width of the gate. The semiconductor substrate is implanted and annealed using the patterned photo resist layer and the hard mask layer as masks to form a dual diffusion area on the second side of the gate. The second patterned photo resist layer is removed.

Accordingly, the present invention also provides a method for fabricating a source/drain device. A silicon substrate having a pad oxide layer over the semiconductor substrate, a gate formed on the pad layer, a hard mask layer over the gate, a first isolation area positioned on a first side of the gate, and a second isolation area positioned on a second side of the gate is provided. The gate has a spacer on the sidewall of the gate. A first patterned photo resist layer is formed as a mask to implant the silicon substrate to form a first doped area and a second doped area. The first doped area is positioned between the gate and the first isolation area, and the second doped area is positioned between the gate and second isolation area. The first patterned photo resist layer is removed. A second patterned photoresist layer having an opening on the second side between the gate and the second isolation area is formed on the silicon substrate. The width of the exposed gate is equal to half the width of the gate. The silicon substrate is implanted and annealed using the patterned photo resist layer and the hard mask layer as masks to form a dual diffusion area on the second side of the gate. The second patterned photo resist layer is removed.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 4 a to 4 i are cross-sections of the method for fabricating S/D devices of the present invention.

In FIG. 4 a , first, a semiconductor substrate 401 , such as silicon, is provided, and a first isolation area 406 a and a second isolation area 406 b are formed thereon. A pad layer 402 , such as oxide, a conductive layer 403 , such as poly, a hard mask layer 404 , such as nitride or Tetraethylorthosilicate (TEOS), and a first patterned photo resist layer 405 are sequentially formed on the area between the first isolation area 406 a and the second isolation area 406 b . The area surrounding by the first isolation area 406 a and the second isolation area 406 b is regarded as an active area (AA).

In FIG. 4 b , the hard mask layer 404 and the conductive layer 403 are sequentially etched to form a gate 403 a using the first patterned photo resist layer 405 as a mask, next, the first patterned photo resist layer 405 is removed, and then, the area of the semiconductor substrate 401 between the gate 403 a and the first isolation area 406 a is doped to form a lightly doped area 407 .

In FIG. 4 c , an insulation layer 408 , such as nitride, is conformably formed on the surface of the pad layer 402 and the gate 403 a.

In FIG. 4 d , the insulation layer 408 is isotropically etched to form a spacer 408 a on the sidewall of the gate 403 a.

In FIG. 4 e , a second patterned photo resist layer 409 having a first opening 410 a and a second opening 410 b is formed on the semiconductor substrate 401 . The first opening 410 a is positioned on the area between the gate 403 a and the first isolation area 406 a , and the second opening 410 b is positioned on the area spaced between the gate 403 a and the second isolation area 406 b.

FIG. 5 is the top view of FIG. 4 e . In FIG. 5 , part of the active area and half the width of the gate 403 a are exposed by the first opening 410 a in the second patterned photo resist layer 409 .

In FIG. 4 f , a first doped area 411 a is formed at the bottom of the first opening 410 a and a second doped area 411 b is formed at the bottom of the second opening 410 b . After the first ion implantation, the second patterned photo resist layer 409 is removed.

In FIG. 4 g , a third patterned photo resist layer 412 having a third opening 413 is formed on the semiconductor substrate 401 , and the width of the gate 403 a exposing because of the third opening 413 in the third patterned photo resist layer 412 is equal to half the width of the gate 403 a . The third opening 413 is positioned on the area between the gate 403 a and the second isolation area 406 b.

Second ion implantation is performed on the semiconductor substrate 401 using the third patterned photo resist layer 412 and the hard mask layer 404 as masks, and the semiconductor substrate 401 is annealed with As or B ions.

FIG. 6 is a top view of FIG. 4 g . In FIG. 4 , part of the active area and the width of the gate 403 a are exposed by the first opening 413 in the third patterned photo resist layer 411 . The width of the first opening 413 is equal to half the width of the gate 403 a , and the area between the gate 403 a and the first isolative 406 a is covered with the third patterned photo resist layer 412 .

In FIG. 4 h , a deeply doped area 414 is formed at the bottom of the third opening 413 . After the second ion implantation, the third patterned photo resist layer 412 is removed. The deeply doped area 414 is 6-7 times the depth of the first doped area 411 a and the second doped area 411 b . The deeply doped area 414 expands after annealing, such that the depth and the width of the deeply doped area 414 are both increased. When the size of the deeply doped area 414 increases, the concentration of dopant inside the deeply doped area 414 decreases and the breakdown voltage of the deeply doped area 414 increases accordingly.

By varying the energy of the ions to form the deeply doped area 414 in the semiconductor substrate 401 , the implantation depth into the substrate can be controlled.

When the width of the third opening 413 is equal to half the width of the gate, the high energy ions do not penetrate through the gate 403 a and the spacer 408 a into the semiconductor substrate 401 because the top layer of the gate 403 a is the hard mask layer 404 .

When the two SID devices are both deeply doped areas, the channel between the S/D devices below the gate 403 a and spacer 408 a will not punch through, which means electrons are not injected into the channel from the source region before applying a gate voltage.

The advantage of the present invention is that the channel between the S/D devices below the gate will not punch through, which means the electric field intensity is reduced to avoid the channel short, and breakdown voltage is increased effectively.