Semiconductor device and fabrication process thereof

A semiconductor device includes a semiconductor substrate of a first conductivity type, a well of the first conductivity type formed in the semiconductor substrate, a transistor formed in the well, a diffusion region of a second conductivity type formed in the semiconductor substrate so as to cover a lateral side and a bottom edge of the well, a terminal formed on the semiconductor substrate at an outside part of the diffusion region, and a conductive region contacting with the well, the well being in ohmic contact with the terminal via the conductive region and the semiconductor substrate, the conductive region having an impurity concentration level exceeding an impurity concentration level of the semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is based on Japanese priority application No. 2005-096276 filed on Mar. 29, 2005, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention generally relates to semiconductor devices and fabrication process thereof and more particularly to a semiconductor device including a field effect transistor and fabrication process thereof.

With demand for improvement of performance in semiconductor devices in recent years, there is also a demand of improved performance in the field effect transistors (FET) such as a metal-oxide-semiconductor (MOS) transistor used in such semiconductor devices. Typically, a MOS transistor has a structure in which a source region and a drain regions are formed in a diffusion layer called well formed in a semiconductor substrate in the form of diffusion regions of opposite conductivity type.

In order to improve the resistance of such MOS transistors against noise, there is proposed the use of a so-called triple well structure in which a well used for a device region is formed in a substrate in a manner surrounded by an impurity diffusion region of opposite conductivity type. With such a structure, the well forming the device region is isolated from the influence of other circuits or the semiconductor substrate itself.

In this technology of triple well, it is proposed to provide a terminal outside the triple well and control the potential of the well inside the triple well via a conduction region formed so as to conduct the interior of the triple well with the external terminal (Patent Reference 1).

REFERENCE

Patent Reference 1 Japanese Laid-Open Patent Application 10-199993

SUMMARY OF THE INVENTION

FIG. 1is a diagram showing the construction of a conventional semiconductor device10that uses a MOS transistor20, wherein the drawing shows the semiconductor device10in a plan view in the lower part thereof, whileFIG. 1shows a cross-sectional view of the semiconductor device10taken along an A-A′ line of the plan view in the upper part thereof. In the plan view, it should be noted that some part of the structure shown in the cross-sectional view is omitted.

Referring toFIG. 1, the semiconductor device10has a construction in which there is formed a device region21of p-type in a silicon substrate11of p-type such that the device region21forms a p-type well defined by a device isolation region14of shallow trench isolation (STI) structure. Further, the semiconductor device20, which may be an n-channel MOS transistor, is formed in the device region21thus formed on the substrate11.

More specifically, the n-channel MOS transistor20includes a gate insulation film23formed on the p-type well21and a gate electrode24is formed on the gate insulation film23in correspondence to a channel region in the p-type well21. Typically, the p-type well21has an impurity concentration level exceeding the impurity concentration level of the substrate11.

Further, diffusion regions22A and22B of n-type are formed in p-type well21as source and drain regions of the n-channel MOS transistor20at respective lateral sides of the gate electrode24, wherein the source and drain regions22A and22B are formed so as to oppose with each other in the p-type well21across the channel region formed right underneath the gate electrode24. Thereby, the diffusion regions22A and22B are formed with a reduced depth and reduced impurity concentration level for those parts thereof covered with sidewall insulation films25formed on respective sidewall surfaces of the gate electrode24and with an increased depth and increased impurity concentration level in those parts not covered with the sidewall insulation films25.

In order to improve the robustness of the transistor20against noise from the substrate101, the semiconductor device10is constructed on a so-called triple well structure, and thus, the p-type well21constituting the device region of the n-channel MOS transistor20is surrounded laterally by a diffusion region31of n−-type. With this, the substrate11is substantially divided into the p-type well21and remaining p-type region of the substrate11by the n−-type diffusion region31.

Further, there is formed a diffusion region13of n+-type further underneath the p-type well21in contact with a bottom edge thereof and further a bottom edge of the n−-type well diffusion region31laterally surrounding the p-type well21. Thereby, the n+-type diffusion region13forms, together with the diffusion region31of n−-type, a semiconductor isolation structure50of n-type surrounding the p-type well21at the lateral edge and the bottom edge thereof.

Further, it should be noted that there is provided a terminal44in the part of the substrate11outside the p-type well21with the semiconductor device10such that the terminal44is connected to a p-type part of the substrate11via a contact layer43of p+-type, wherein there is provided another terminal42in a part of the n−-type diffusion region31via a contact layer41of n+-type. It should be noted that the terminal44is used to control a potential of the well21from outside by applying a reverse bias voltage therebetween.

With such a construction, the semiconductor isolation structure50isolates the p-type well21, and hence the transistor20formed thereon, from the remaining p-type region of the substrate11, which may function as noise source.

In order to allow control of potential of the p-type well21from the terminal44, there is formed an “opening”12in the semiconductor isolation structure50at the bottom part thereof, more specifically in the diffusion layer13of n+-type, wherein the “opening”12is in fact a region of the p-type silicon substrate11not formed with the diffusion region13of n+-type and thus has the impurity concentration level substantially identical with the impurity concentration level of the silicon substrate11. Thereby, the potential of the p-type substrate11is controlled externally by applying a reverse bias to the terminals42and44as noted above, and the potential of the silicon substrate11thus controlled is transmitted to the p-type well21via the opening12.

With the construction ofFIG. 1, there is further provided a p-channel MOS transistor30in the diffusion region31of n-type, which constitutes a part of the semiconductor isolation structure50, while using the diffusion region31as an n-type well.

In the transistor30, it should be noted that there is formed a gate insulation film33on the diffusion region31used for the n-type well and a gate electrode34is formed on the gate insulation film33in correspondence to a channel region formed in the well31. Further, diffusion regions32A and32B of p-type are formed in the n-type well31so as to oppose with each other across the channel region formed right underneath the gate electrode34.

With such a construction, sidewall insulation films35are formed on the respective sidewall surface of the gate electrode34, and the source and drain regions32A and32B are formed with a reduced depth and reduced impurity concentration level in those parts thereof covered with the sidewall insulation film35and with increased depth and increased impurity concentration level in those parts not covered with the insulation film35.

On the other hand, with advanced semiconductor devices of these days, there is imposed a severe demand of device miniaturization in addition to the demand of reducing the electric power consumption, and associated with this, there have been caused various problems with the semiconductor devices constructed on a triple well structure.

From the viewpoint of reducing the electric power consumption, it is desirable to apply as large bias voltage as possible across the terminals42and44, and thus it is desirable that the potentials of the p-type well21and the semiconductor isolation structure50are controllable over wide range from a zero bias state to large reverse bias state. On the other hand, from the viewpoint of miniaturization of the semiconductor device, the size of the opening12has to be reduced as much as possible.

Thus, in the case there is applied a large reverse bias voltage across the electrodes42and44with a semiconductor device in which the size of the opening12is reduced, extension of the depletion layer formed in the opening12at the p/n junction between the p−-type semiconductor constituting the opening12and the n+-type diffusion region13is no longer ignorable with regard to the size of the opening12, and it becomes difficult to transmit the potential of the substrate11controlled by the electrode44to the p-type well21via the opening12. Depending on the magnitude of the potential difference and the size of the opening12, there is even a possibility that a complete pinch-off is caused at the opening12.

Thus, with the semiconductor device having a transistor constructed on a triple-well structure, there have been cases in which it becomes difficult to achieve both device miniaturization and reduction of electric power consumption simultaneously.

Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and fabrication process thereof wherein the foregoing problems are eliminated.

A more specific object of the present invention is to achieve device miniaturization and decrease of electric power consumption at the same time in a semiconductor device having a transistor of triple-well structure.

In a first aspect, the present invention provides a semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a well of said first conductivity type formed in said semiconductor substrate;

a transistor formed in said well;

a diffusion region of a second conductivity type formed in said semiconductor substrate so as to cover a lateral side and a bottom edge of said well;

a terminal formed on said semiconductor substrate at an outside part of said diffusion region; and

a conductive region contacting with said well,

said well being in ohmic contact with said terminal via said conductive region and said semiconductor substrate,

said conductive region having an impurity concentration level exceeding an impurity concentration level of said semiconductor substrate.

According to the present invention, it is possible to achieve miniaturization and reduction of electric power consumption simultaneously in a semiconductor device that includes a transistor of triple well structure.

According to a second aspect, the present invention provides a method of fabricating a semiconductor device comprising a semiconductor substrate of a first conductivity type, a well of said first conductivity type formed in said semiconductor substrate, a transistor formed in said well, a diffusion region of a second conductivity type formed in said semiconductor substrate so as to cover a sidewall surface and a bottom surface of said well, a terminal formed on said semiconductor substrate at an outside part of said diffusion region, and a conductive region contacting with said well, said well being in ohmic contact with said conductive region via said semiconductor substrate, said conductive region having an impurity concentration level exceeding an impurity concentration level of said semiconductor substrate, said method comprising the steps of:

forming a conductive region in said semiconductor substrate by introducing a first impurity element of a first conductivity type; and

forming said diffusion region by introducing a second impurity element of second conductivity type into said semiconductor substrate.

According to the present invention, it becomes possible to achieve miniaturization of the device size and reduction of electric power consumption simultaneously in a semiconductor device having a transistor of triple well structure.

Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.

DETAILED DESCRIPTION OF THE INVENTION

With the present invention, it becomes possible to achieve the object of reduction of electric power consumption and device miniaturization at the same time in a transistor constructed on a triple well structure.

With the transistor constructed on a triple well structure, there is formed a semiconductor isolation region around the well on which the transistor is formed, wherein the semiconductor isolation region has a conductivity type opposite to the conductivity type of the well. Thereby, the well is isolated from noise coming from outside of the semiconductor isolation region. Further, such a semiconductor isolation region includes therein an opening for allowing control of potential of the well from outside.

In order to reduce the electric power consumption while achieving device miniaturization at the same time with such a semiconductor device constructed on a triple well structure, it is desirable to apply a large reverse bias voltage across the semiconductor isolation region and the well while decreasing the size of the opening at the same time. Thereby, there is a concern that the depletion region formed in the opening as a result of the reverse biasing may no longer be ignorable and that there may be caused a pinch-off phenomenon in such an opening as a result of such a large reverse biasing.

In view of the foregoing, the present invention forms a conductive region of first conductivity type in such an opening with high impurity concentration level higher than the impurity concentration level of the substrate.

With such a construction, extension of the depletion region in the opening is effectively suppressed, and it becomes possible to achieve reduction of electric power consumption and device miniaturization at the same time with the transistor constructed on such a triple well structure.

Hereinafter, the present invention will be explained with reference to embodiments.

FIRST EMBODIMENT

FIG. 2is a diagram showing a part of a semiconductor device100including therein a MOS transistor200according to a first embodiment of the present invention, whereinFIG. 2shows, in the bottom part of the drawing, the semiconductor device100of the present invention in a plan view, while the top part ofFIG. 2shows the same semiconductor device100in a cross-sectional view taken along a B-B′ line of the plan view. In the plan view ofFIG. 2, it should be noted that illustration is omitted for some part of the semiconductor device structure shown in the cross-sectional view.

Referring toFIG. 2, the semiconductor device100has a construction in which a device200such as an n-channel MOS transistor is formed in a device region defined on a substrate101of p-type (or a p-type well) by a device isolation region104of STI structure, wherein it should be noted that designation “P” provided to the substrate101in the drawing does not mean any specific impurity concentration level and it is possible to choose the impurity concentration level for the substrate101appropriately.

The n-channel MOS transistor200has a construction such that there is formed a p-type well201on the substrate101with an impurity concentration level higher than that of the substrate101, and a gate insulation film203is formed on such a p-type well201in correspondence to a channel region to be formed therein. Further, a gate electrode204is formed on the gate insulation film203, and source and drain regions202A and202B of n-type are formed in the p-type well201so as to oppose with each other across the channel region formed underneath the gate electrode204.

Further, sidewall insulation films205are formed on respective sidewall surfaces of the gate electrode204, and the source and drain regions202A and202B are formed with a shallow depth and smaller impurity concentration level in the part thereof covered by the sidewall insulation films25and with increased depth and larger impurity concentration level in the part thereof not covered by the sidewall insulation films205.

The semiconductor device100uses a so-called triple well structure for eliminating noise from the substrate101to the transistor200, wherein the triple well structure includes the p-type well201surrounded by a diffusion region301forming an n-type well. Thereby, the p-type substrate101is substantially divided into a part that includes therein the p-type well201and other p-type part not including the p-type well201.

More specifically, in the structure ofFIG. 2, there is further formed an n-type diffusion region forming the n-type well301in the silicon substrate101in the same plane of the p-type well201so as to surround the p-type well201laterally, and another n-type well103is formed underneath the p-type well201in contact with the bottom edge of the p-type well201and further the bottom edge of the surrounding n-type well301, wherein the n-type diffusion region103has an impurity concentration level exceeding the impurity concentration level of the n-type well301and forms a semiconductor isolation structure500together with the n-type well301such that the semiconductor isolation structure500surrounds the p-type well201at the lateral edge and bottom edge thereof.

Thus, with formation of the semiconductor isolation structure500, the p-type well201is isolated from other p-type region of the substrate101, which may function as noise source.

Further, it should be noted that, in the outside region of the p-type well201isolated therefrom by the semiconductor isolation structure500, there is formed a terminal404providing a potential to the p-type well201, such that the terminal404is in ohmic contact with the p-type silicon constituting the p-type silicon substrate101, via a highly-doped p-type contact layer410and a metallization layer403formed on the contact layer410.

Similarly, there is provided a terminal402in a part of the diffusion region301of n−-type constituting the semiconductor isolation structure500, wherein the terminal402makes an ohmic contact with the diffusion region301via a metallization401and a contact layer411of n+-type formed underneath the metallization401.

Further, at the bottom part of the semiconductor isolation structure500, more specifically, in a part of the n-type region103, there is formed a conductive region102of p+-type so as to extend from the silicon substrate101to the p-type well201, wherein the conductive region102transmits the potential provided to the substrate101from the terminal404to the p-type well201.

Thus, by applying a reverse bias voltage across the terminals402and404, the potential of the p-type silicon substrate101controlled by the bias voltage applied to the terminal404is transmitted to the p-type well201via the conductive region102, wherein it should be noted that formation of depletion layer in the conductive region102at the p/n junction between the conductive region102of p+-type and the diffusion region103of n+-type is suppressed effectively because of the increased impurity concentration level in the conductive region102. Thereby, it becomes possible to apply a large reverse bias voltage across the terminals402and404and a large potential difference can be induced between the p-type well201and the semiconductor isolation structure500while minimizing extension of the depletion layer.

Thus, with the present invention, it becomes possible to achieve device miniaturization and reduction of electric power consumption at the same time in the semiconductor device that uses a transistor formed on triple well structure.

For example, with the semiconductor device100ofFIG. 2, it becomes possible to suppress the occurrence of pinch-off and reduce the electric power consumption even in such a case in which the width d of the conductive region102is set to 0.01-20 μm and a reverse bias voltage of 0-10V is applied between the conductive region102and the isolation region103, by setting the impurity concentration level of the conductive region102to 3×1015cm−3or more. Particularly, it is advantageous to suppress the occurrence of depletion layer when the difference of impurity concentration level between the substrate101and the conductive region102is equal to or larger than 3×1015cm−3.

In the construction of the present embodiment, it is also possible to form a p-channel MOS transistor300in the n-type diffusion region constituting a part of the isolation region500. In this case, a part of the n-type diffusion region301is used as the n-type well on which the transistor300is formed.

More specifically, the MOS transistor is formed on the n-type well301formed in the substrate101and includes a gate insulation film303and a gate electrode304is formed on the gate insulation film303. Further, source and drain regions302A are formed in the n-type well301in the form of p-type diffusion region such that the source and drain regions302A laterally define the channel region of the p-channel MOS transistor right underneath the gate electrode304.

Thereby, the gate electrode304carries sidewall insulation films305on respective sidewall surfaces thereof, wherein the source and drain regions302A and302B are formed with a reduced depth and reduced impurity concentration level for the part covered by the sidewall insulation films305and with increased depth and increased impurity concentration level for the part not covered by the sidewall insulation films305.

FIG. 3shows the construction of a semiconductor device100′ according to a modification of the semiconductor device100, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 3, it will be noted that no transistor is formed in a diffusion region301′ of n-type corresponding to the diffusion region300with the semiconductor device100′, wherein the diffusion region301′ functions as a part of a semiconductor isolation structure500′ corresponding to the semiconductor isolation structure500ofFIG. 2. In this modification, it is possible to form a well for another transistor adjacent to the n-type diffusion region301′.

SECOND EMBODIMENTS

FIG. 4is a diagram showing a part of a semiconductor device10A including therein the MOS transistor200according to a second embodiment of the present invention, whereinFIG. 4shows, in the bottom part of the drawing, the semiconductor device100A of the present embodiment in a plan view, while the top part ofFIG. 4shows the same semiconductor device100A in a cross-sectional view taken along a C-C′ line of the plan view. In the plan view ofFIG. 4, it should be noted that illustration is omitted for some part of the semiconductor device structure shown in the cross-sectional view. InFIG. 4, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 4, the semiconductor device100A forms a conductive region102A in a part of the semiconductor isolation structure500in correspondence to the conductive region102of the previous embodiment except that the conductive region102A has a reduced lateral size as compared with the conductive region102of the previous embodiment.

In the plan view, it will be noted that the area of the conductive region102A is reduced as compared with the conductive region102of the previous embodiment in correspondence to the reduced lateral size thereof.

With the construction of the present embodiment, there is formed a p-type region of reduced impurity concentration level between the p+-type conductive region102A and the diffusion region103of n+-type with an impurity concentration level lower than that of the conductive region102A, such as the impurity concentration level of the silicon substrate101.

With such a construction, it is possible to reduce the parasitic capacitance between the conductive region102A and the diffusion region103.

Thus, it should be noted that the size and shape of the conductive region102A formed in the semiconductor isolation structure500can be changed variously according to the needs.

THIRD EMBODIMENT

FIG. 5is a diagram showing a part of a semiconductor device100B including therein the MOS transistor200according to a third embodiment of the present invention, whereinFIG. 5shows, in the bottom part of the drawing, the semiconductor device100B of the present embodiment in a plan view, while the top part ofFIG. 5shows the same semiconductor device100B in a cross-sectional view taken along a D-D′ line of the plan view. In the plan view ofFIG. 5, it should be noted that illustration is omitted for some part of the semiconductor device structure shown in the cross-sectional view. InFIG. 5, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 5, it will be noted that there is formed a diffusion region103B of n-type corresponding to the n-type diffusion region103ofFIG. 2such that the diffusion region103B extends over a wide area of the substrate101.

Further, the present embodiment uses a conductive region102B of p30-type in correspondence to the conductive region102ofFIG. 2, wherein the conductive region102B of the present embodiment is formed by introducing a p-type impurity element to a part of the n30-type diffusion region103B such that the concentration level of the p-type impurity element exceeds the concentration level of the n-type impurity element in the diffusion region103B.

Here, it should be noted that the conductive region102B is formed such that at least a part thereof makes a contact with the p-type well201. In the present embodiment, for example, the conductive region102B is formed in correspondence to a boundary of the p-type well201and the diffusion region301of n−-type, and thus, it will be noted that the conductive region102B makes a contact with both the p-type well201and the n-type diffusion region301.

It should be noted further that the conductive region102B has a circular cross-sectional shape contrary to the rectangular cross-sectional shape of the conductive region102used with the embodiment ofFIG. 2, while such a difference in the shape does not influence the effect achieved with the present embodiment.

Thus, various shapes can be used for the conductive region102B for transmitting the potential of the substrate101to the p-type well201.

With the present embodiment, it should be noted that application of potential to the substrate101is achieved differently over the previous embodiments in that there is formed a contact layer101A of highly doped p-type at the rear side of the substrate101and a terminal101B is provided to the contact layer101A thus formed for application of the potential. Thereby, the terminal101B functions similarly to the terminal404of the previous embodiments. In this way, various embodiments are possible for the terminal404used for applying a potential to the p-type well201.

Thus, with the semiconductor device of the present embodiment, it is possible to change the shape and location of the conductive region variously, and large degree of freedom is provided at the time of designing or making layout of the semiconductor device.

FIG. 6is a diagram showing a semiconductor device100C according to a modification of the semiconductor device100B of the present embodiment, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 6, it will be noted that the conductive region102C corresponding to the conductive region102ofFIG. 2is formed with an increased size with the semiconductor device100C ofFIG. 6. Further, with reference to the plan view, it will be noted that the conductive region102C is provided at a location different from that of the conductive region102. Further, it will be noted that the conductive region102C is distinct over the conductive region102in that the conductive region102C has a rounded rectangular shape when viewed in a plan view diagram. With such a construction, too, the conductive region102C can function similarly to the conductive region102.

Further, it should be noted that the n-type diffusion region103B can be formed with various shapes and sizes with the present embodiment. For example, the diffusion region103may be formed over the entire substrate surface.

FOURTH EMBODIMENT

FIG. 7is a diagram showing a part of a semiconductor device100C including therein the MOS transistor200according to a fourth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 7, the diffusion region103of n+-type is formed over a wide area with the semiconductor device100D of the present embodiment as compared with the semiconductor device100explained with reference toFIG. 2, and thus, the diffusion region103extends over an area larger than the area of the diffusion region103of the device100ofFIG. 2.

Further, the contact layer410is formed on a diffusion region405of p-type formed with the same fabrication process of the p-type well and thus have the impurity concentration level identical with the impurity concentration level of the p-type well201, wherein the p-type diffusion region405is formed on a p-type diffusion region406having an impurity concentration level exceeding the impurity concentration level of the diffusion region405. Thereby, the diffusion region406is formed with the same fabrication process of the conductive region102, and thus, the impurity diffusion region406and the conductive region have the same impurity concentration level.

Further, in the outer side of the p-type diffusion region405and hence in the p-type diffusion region406, there are formed diffusion regions407and408of n-type respectively at a side away from the MOS transistor200, wherein the diffusion regions407and408are formed so as to isolate the p-type diffusion regions405and406, respectively.

Thereby, it should be noted that the n-type diffusion region407is formed in the same fabrication process of the n-type diffusion region301, and the n-type diffusion region408is formed in the same fabrication process of the n-type diffusion region103.

Next, fabrication process of the semiconductor device100D will be explained with reference toFIGS. 8A-8H, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

First, in the step ofFIG. 8A, formation of the device isolation structure104of STI structure is conducted on the silicon substrate101of p-type, and ion implantation process of a p-type impurity element is conducted in the step ofFIG. 8Binto the substrate101while using a resist pattern501formed on the silicon substrate101as a mask. Thereby, the conductive region102and the p-type diffusion region406are formed simultaneously in the form of highly doped p-type diffusion region.

Next, in the step ofFIG. 8C, the resist pattern501is removed, and a resist pattern502is formed on the substrate102so as to cover the region where the conductive region102and the p-type diffusion region406are formed. Further, an ion implantation process of an n-type element is conducted into the silicon substrate101not covered with the resist pattern502, and there are formed highly doped n-type diffusion regions as the n-type diffusion regions103and408. Thus, with the process of the present embodiment, the conductive region102and the p-type diffusion region406are formed with the same impurity concentration level, and the n-type diffusion region103and the n-type diffusion region408are formed with the same impurity concentration level.

Further, the conductive region102, the p-type diffusion region406, the n-type diffusion region103and the n-type diffusion region408are formed substantially on the same plane.

Next, in the step ofFIG. 8D, a resist pattern503is formed on the substrate101and ion implantation of a p-type impurity element is conducted, and with this, the p-type well201and the p-type diffusion region405of p−-type are formed in the silicon substrate101in correspondence to the opening of the resist pattern503, wherein the p−-type well201and the p−-type diffusion region405thus formed have an impurity concentration level higher than that of the silicon substrate101, while the impurity concentration level of the p−-type well201and the p−-type diffusion regions405is lower than that of the p+-type conductive region102and the p+-type diffusion region406.

Next, in the step ofFIG. 8E, the resist pattern503is removed, and a new resist pattern504is formed on the silicon substrate101so as to cover the p-type well and the p-type diffusion region405. Further, by conducting an ion implantation process of an n-type impurity element in this state, the diffusion regions301and407of n−-type are formed in correspondence to the part of the silicon substrate101not covered with the resist pattern504. Thus, the n-type diffusion regions301and407have a lower impurity concentration level as compared with the n-type diffusion regions103and408.

Further, because of the foregoing process of fabrication, the p-type well201and the p-type diffusion region405have the same impurity concentration level, and n-type diffusion region301and the n-type diffusion region407have the same impurity concentration level. It should be noted that the p-type well201, the p-type diffusion region405, the n-type diffusion region301and the n-type diffusion region407are formed a substantially in the same plane in the silicon substrate101.

Next, in the step ofFIG. 8F, the resist pattern504is removed, and a gate insulation film is formed on the p-type well201and further on the n-type diffusion region301. Further, by depositing and patterning a polysilicon layer on the gate insulation film thus formed, the gate electrode204is formed on the p-type well201via the gate insulation film203and the gate electrode304is formed on the n-type well301via the gate insulation film303.

Next, in the step ofFIG. 8F, a resist pattern505is formed on the silicon substrate101with resist openings corresponding to the p-type well201and the n-type diffusion region411, and ion implantation process of an n-type impurity element is conducted into the substrate101while using the resist pattern505as a mask. With this, the source and drain regions202A and202B are formed in the p-type well201and an n+-type diffusion region is formed as the contact layer411.

Next, in the step ofFIG. 8G, the resist pattern505is removed and a new resist pattern506is formed on the silicon substrate such that the resist pattern506forms resist openings in correspondence to the n-type well to be formed in the n-type diffusion region301as the device region of the p-channel MOS transistor300and the p-type diffusion region410. Further, by conducting an ion implantation process of a p-type impurity element while using the resist pattern506as a mask, the source and drain regions302A of p+-type are formed in the n-type well301and the p+-type contact region410is formed on the p-type region405.

Next, the resist pattern506is removed, and the sidewall insulation films205and305are formed on the respective sidewall surfaces of the gate electrodes204and304.

Further, formation of resist pattern and ion implantation of the impurity element are conducted similarly to the steps ofFIGS. 8F-8G, and with this, the source and drain regions202A and202B are formed with reduced depth in the part closer to the gate electrode204and covered with the sidewall insulation films205and increased depth in the part far from the gate electrode304and not covered with the sidewall insulation films205. Similarly, the source and drain regions302A and302B are formed with reduced depth in the part closer to the gate electrode304and covered with the sidewall insulation films305and increased depth in the part far from the gate electrode304and not covered with the sidewall insulation films305.

Further, the metallization layers401and403are formed, and with formation of the terminals402and404, the semiconductor device100D shown inFIG. 7is obtained.

After formation of the structure ofFIG. 7, an interlayer insulation film is formed according to the needs, and a multilayer interconnection structure is formed on the transistors thus formed.

FIFTH EMBODIMENT

While the previous embodiment has formed the n-type diffusion region103after formation of the conductive region102, the present invention is by no means limited to such a process and it is possible to form the conductive region102after formation of the n-type diffusion region103.

In such a process, the steps ofFIGS. 8B-8Cof the previous embodiment are replaced with the steps9A and9B explained below. In the drawings, those parts corresponding to the parts explained previously are designated by the same reference numerals and the description thereof will be omitted. Further, in the drawings explained below, only those parts related to the conductive region102and the n-type diffusion region103will be represented and some parts of the structure shown inFIGS. 8A-8Gwill be omitted.

Referring toFIG. 9A, a resist pattern502A is formed on the silicon substrate101, and the n-type diffusion region103is formed in the silicon substrate101by conducting an ion implantation process of an n-type impurity element into the substrate101while using the resist pattern502as a mask.

Next, the resist pattern502A is removed, and a resist pattern501A is formed on the substrate101so as to cover a part thereof corresponding to the diffusion region103. Thereby, the conductive region102of highly doped p-type region is formed in the part not covered with the resist pattern501A by conducting an ion implantation process of a p-type impurity element.

Thus, with the present embodiment, it is possible to reverse the order of formation of the conductive region102of p+-type and the semiconductor isolation structure formed of the diffusion regions301and103of n− or n+-type.

SIXTH EMBODIMENT

Further, it should be noted that the resist pattern501shown inFIG. 8Band the resist pattern502shown inFIG. 8Care in a reversal relationship in that the part covering the substrate and the part forming a resist opening are reversed from each other. In the case of forming such resist patterns in reversal relationship, it is possible to use the same mask pattern and forming the respective resist patterns by using a positive resist and a negative resist as represented inFIGS. 10A and 10B. InFIGS. 10A and 10B, those parts corresponding to the parts explained before with reference to the fourth embodiment are designated by the same reference numerals and the description thereof will be omitted.

In the description below, only those parts related to formation of the conductive region102and the n-type diffusion region103are represented and the remaining parts of the structure shown inFIGS. 8A-8Gare omitted.

FIG. 10Ashows an example of formation of the resist pattern501shown inFIG. 8B.

In the step ofFIG. 10A, a mask pattern M1exposing a part corresponding to the resist opening of the resist pattern501is used for exposing a positive resist film501a, and thus, the resist pattern501shown inFIG. 8Bis obtained after development of the resist film501athus exposed.

FIG. 10Bon the other hand shows an example of formation of the resist pattern502shown inFIG. 8C.

With the step ofFIG. 10B, a mask pattern M1exposing a part of the resist pattern502covering the substrate is used for exposing a negative resist film502a, and the resist pattern shown inFIG. 8Cis obtained after development of the resist film502athus exposed.

Thus, by using a negative resist and a positive resist appropriately, it is possible to use the same mask patter for the formation of the conductive region102and formation of the n-type diffusion region103forming a part of the semiconductor isolation structure500.

Further, it is possible to change the order of the step ofFIG. 10Aand the step ofFIG. 10B.

SEVENTH EMBODIMENT

FIGS. 11A and 11Bare diagrams showing the fabrication process of a semiconductor device according to a seventh embodiment of the present invention, wherein those parts corresponding to he parts described previously with preceding embodiments are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 11A, an n-type impurity element is introduced into the part of the silicon substrate101by an ion implantation process to form an n+-type diffusion layer103B′ of high impurity concentration level in the part where the n-type diffusion region103B is to be formed including the region of the conductive region102.

Next, in the step ofFIG. 11B, a resist pattern507is formed on the silicon substrate101so as to cover the part thereof in which the n-type diffusion region103B is to be formed, and ion implantation process of a p-type impurity element is conducted. Thereby, the conductive region102B of p+-type is formed in the part not covered with the resist pattern507, while remaining region of the n+-type diffusion region103B′ forms the diffusion region103. In this case, it is necessary to conduction implantation of the p-type impurity element such that the concentration level of the p-type impurity element in the conductive region102B exceeds the concentration level of the n-type impurity element in the diffusion region103B of n+-type.

EIGHTH EMBODIMENT

FIGS. 12A and 12Bare diagrams showing the fabrication process of a semiconductor device according to an eighth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.

Referring toFIG. 12A, there is formed a diffusion region102B′ of p+-type by introducing a p-type impurity element into the silicon substrate101with high concentration level including the region in which the conductive region102B is to be formed, and in the step ofFIG. 12B, there is conducted an ion implantation process of an n-type impurity element into the silicon substrate101while covering the part of the silicon substrate101corresponding to the conducive region102B by providing a resist pattern508.

As are result, the diffusion region103B of n+-type is formed in the part not covered with the resist pattern508, while the part of the p+-type diffusion region102B′ not formed with the diffusion region103B of n+-type forms the conductive region102B of p+-type. Thereby, it is necessary to conduct the ion implantation of the n-type impurity element such that the concentration level of the n-type impurity element in the diffusion region103B exceeds the concentration level of the p-type impurity element therein.

NINTH EMBODIMENT

Next, the effect of suppressing the pinch-off achieved with the semiconductor device of the present invention will be described as a ninth embodiment of the present invention.

FIG. 13shows the construction of a semiconductor device used for investigating the effect of the present invention.

Referring toFIG. 13, the semiconductor device has a structure similar to that of the semiconductor device100explained with reference toFIG. 2except that source and drain regions, gate insulation film and gate electrode are eliminated.

More specifically, the semiconductor device ofFIG. 13is constructed on a silicon substrate901of p-type and includes therein a well904of p−-type defined by a device isolation region906of STI structure and surrounded laterally by a diffusion region905of n−-type, wherein there is provided a diffusion region of n+-type underneath the p-type well904and the surrounding diffusion region905of n−-type.

By using the device ofFIG. 13, the electric characteristics thereof was investigated while setting the substrate901to a reference potential (0V).

First, the potential of the p-type well is fixed at 0.5V, and the current Ip flowing to the well904is investigated while changing the voltage Vn of the n-type diffusion region903.

FIG. 14shows the result of this investigation, wherein it will be noted that the experiment have been conductive for different impurity concentration levels for the conductive region902as represented by experiments EX1, EX2and EX3.

More specifically, Experiment EX1uses the same impurity concentration level of the substrate901for the conductive region902, and thus, this experiment corresponds to the semiconductor device of conventional art.

In the case of experiment EX2, on the other hand, the impurity concentration level of the conductive region902is increased over the impurity concentration level of the substrate901, while in the case of experiment EX3, the impurity concentration level of the conductive region902is increased further as compared with the case of experiment EX2.

Referring toFIG. 14, it will be noted that there occurs a sharp decrease of the current Ip flowing to the p-type well904with increase of the voltage Vn applied to the n-type diffusion region903, indicating that there is taking place the phenomenon of pinch-off in the conductive region902because of extension of the depletion region from the p/n junction between the conductive region902and the n-type diffusion region903. Particularly, in the case of the voltage Vn of about 1V, it will be noted that no substantial current flows anymore to the p-type well904.

On the other hand, in the case of the experiments EX2and EX3, there is caused substantial increase of the current Ip for the same voltage Vn as compared with the experiment EX1, indicating that formation of the depletion layer and subsequent occurrence of pinch-off are successfully suppressed. Further, with the case of experiment Ex3, the degree of drop of the current Ip is reduced as compared with the case of experiment EX2for the same increase of the voltage Vn, while this clearly indicates that extension of the depletion region in the conductive region902is suppressed effectively by increasing the impurity concentration level of the conducive region902.

Further, while explanation has been made heretofore with regard to the case of using a p-type substrate, it is also possible to use the present invention for a semiconductor device constructed on an n-type substrate by reversing the conductivity type of the respective regions.

Further, the present invention is not limited to the embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the invention.