Die identification by optically reading selectively blowable fuse elements

Many integrated circuit die are fabricated on a wafer. Each die includes integrated functional circuitry with an array of fuse elements that are visible to optical inspection. An electrical wafer sort is performed to test the integrated functional circuitry of each die. The array of fuse elements for each die on the wafer are programmed through the electrical wafer sort process with data bits defining a die identification that specifies a location of the die on the wafer. The die is then encapsulated in a package. In the event of package failure, a decapsulation is performed to access the die. Optical inspection of the array of fuse elements is then made to extract the die identification.

TECHNICAL FIELD

The present disclosure generally relates to the provision of manufacturing-related information on an integrated circuit die and, in particular, to the provision of optically readable manufacturing-related information programmed into a fuse array of the integrated circuit die.

BACKGROUND

Reference is made toFIG. 1showing a top plan view of a semiconductor wafer10including a plurality of integrated circuit die12arranged in a matrix or array format. For tracking and quality control purposes, each wafer10is assigned a wafer identification (wafer_id) and that identification is typically etched into the top surface of the wafer at a location devoid of integrated circuit die12(for example, at or near a peripheral edge of the wafer). The wafer_id provides information specific to the wafer and/or the lot from which the wafer is obtained. For similar tracking and quality control purposes, each individual integrated circuit die12is also assigned a die identification (die_id). The die_id provides information specific to the integrated circuit die12such as its location (i.e., coordinates) within the matrix or array format of the wafer10. It is also possible for the die_id to further include wafer identification information such that the die_id provides information as to both the identification of the wafer10and the location within that wafer10from which the integrated circuit die12was obtained.

The prior art teaches a number of ways for including the die_id within each integrated circuit die12. For example, the die_id may be micro-etched in a layer of the integrated circuit die12(FIG. 2A) separate from any included integrated functional circuitry16. Alternatively, the die_id may be stored in an electrically-readable non-volatile memory (NVM) circuit (FIG. 2B) within the integrated functional circuitry16. A concern with prior art die identification techniques is that damage to the die may render the die_id unreadable. For example, in connection with theFIG. 2Bimplementation, damage to the die may damage the non-volatile memory circuit and/or related read circuitry making it impossible to recover the stored die_id.

SUMMARY

In an embodiment, a process comprises: fabricating a plurality of integrated circuit die on a wafer, each integrated circuit die including integrated functional circuitry; providing within each integrated functional circuitry an array of fuse elements, wherein said array of fuse elements is visible to optical inspection through a top surface of the integrated circuit die; performing an electrical wafer sort process on the wafer to test the integrated functional circuitry of each integrated circuit die; and accessing the array of fuse elements for each integrated circuit die on the wafer through the electrical wafer sort process to program individual fuses within the array of fuse elements with data bits defining a die identification that specifies a location of the integrated circuit die on the wafer.

In an embodiment, an integrated circuit die comprises: integrated functional circuitry; an array of fuse elements, wherein said array of fuse elements is visible to optical inspection through a top surface of the integrated circuit die; and a programming circuit configured to program individual fuse elements within the array of fuse elements with data bits defining a die identification that specifies a location of the integrated circuit die on a wafer from which the integrated circuit die was singulated.

In an embodiment, an integrated circuit package comprises: an integrated circuit die including integrated functional circuitry; a package block which encapsulates the integrated circuit die; an array of fuse elements supported within the integrated circuit die; and a programming circuit configured to program individual fuse elements within the array of fuse elements corresponding to data bits defining a die identification that specifies a location of the integrated circuit die on a wafer from which the integrated circuit die was singulated; wherein said array of fuse elements is visible so as to allow a determination of the data bits defining the die identification by optical inspection through a top surface of the integrated circuit die after at least a partial removal of the package block.

In an embodiment, a process comprises: receiving an integrated circuit package that includes an integrated circuit die having failed integrated functional circuitry, the integrated functional circuitry including an array of fuse elements programmed in accordance with data bits defining a die identification that specifies a location on a wafer where the integrated circuit die was fabricated; decapping the integrated circuit package to expose a top surface of the integrated circuit die; and visually examining the array of fuse elements through the top surface of the integrated circuit die to detect data bits of the die identification of the integrated circuit die from the programmed fuse elements within the array of fuse elements.

The foregoing and other features and advantages of the present disclosure will become further apparent from the following detailed description of the embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the disclosure, rather than limiting the scope of the invention as defined by the appended claims and equivalents thereof.

DETAILED DESCRIPTION

Reference is now made toFIGS. 3A and 3Bwhich show circuit diagrams for an optically readable fuse memory circuit100,100′ configured to store die information. The circuits100and100′ differ from each other in terms of how the control signaling (i.e., control signals WR_FUSE, RD_FUSE, ADDRESS_BITS, ENABLE) is generated. In circuit100, the control signaling is generated by a serial interface circuit102that is coupled to a serial interface pad104of the integrated circuit die12. The data of the control signaling is received in serial format over the pad104and converted to generate the various control signals. In the circuit100′, on the other hand, the individual pads104′ of the integrated circuit die12receive the various control signals.

The circuits100,100′ include a fuse array108formed by a plurality of individual fuse elements FUSE_0 to FUSE_2n−1. With reference toFIG. 4, each fuse element FUSE_x may be formed by a serpentine-shaped metal line110connected between a first fuse terminal112and a second fuse terminal114. The first fuse terminals112of the fuses within the fuse array108are connected to a fuse sensing node (FUSE_SENSING). The second fuse terminals114of the fuses within the fuse array108are connected to a demultiplexer circuit120. The fuse sensing node (FUSE_SENSING) is connected to a power supply node (SUPPLY) through a transistor switch (WR_SW). The transistor switch (WR_SW) is selectively actuated by the control signal WR_FUSE to apply a voltage to the fuse array108during a write (WR) operation to program the data for the die_id to the fuses within the fuse array108. The fuse sensing node (FUSE_SENSING) is also connected to a current generator through a transistor switch (RD_SW). The transistor switch (RD_SW) is selectively actuated by the control signal RD_FUSE to apply a current to the fuse array108during a read (RD) operation to sense the data for the die_id that was programmed into the fuses within the fuse array108.

The demultiplexer circuit120includes a decoder circuit having an address input coupled to an address bus to receive the control signal ADDRESS_BITS specifying a certain one of the 2n−1fuses to be accessed. The decoder circuit is enabled for operation in response to the control signal ENABLE. The 2n−1outputs of the decoder circuit are connected to the control gates of transistor switches SW0 to SW2n−1. Each transistor switch is an n-channel MOSFET device having a source terminal connected to ground and a drain terminal connected to the second fuse terminal114of one of the fuses within the fuse array108.

In write mode, when writing the bits of the die_id to the fuses of the fuse array108, the control signal WR_FUSE is asserted. The ADDRESS_BITS specifying a certain one of the 2n−1fuses to be blown are applied to the address bus and the control signal ENABLE is then asserted. Current flows through the FUSE_x selected by the ADDRESS_BITS and the serpentine-shaped metal line110melts. This process is repeated for each fuse that needs to be blown in order to program a certain logic state of the bits of the die_id in the fuse array108. As an example, assume that the die_id is <01001 . . . 1> and further assume that a blown fuse indicates a logic 1 value. The ADDRESS_BITS would specify the x=1, x=4, . . . , x=2n−1ones of the fuses FUSE_x to be blown.

The process for writing the bits of the die_id to the fuses of the fuse array108is performed during the electrical wafer sort (EWS) process. Electrical wafer sort is a testing process performed on the wafer10to test operation of the included integrated circuit die12. A probe card coupled to automated test equipment (ATE) makes electrical connection to pads of each integrated circuit die12and executes a series of electrical tests. If the integrated circuit die12passes those tests, it is approved for further manufacturing processing such as encapsulation within an integrated circuit package. While the probe card is in contact with the integrated circuit die12, the automated test equipment can be used to operate the circuits100,100′ (through connection to pads104,104) to program the die_id data bits into the fuse array108. The wafer10is then diced to separate (i.e., singulate) the integrated circuit die12from the wafer. Integrated circuit die that pass testing in the EWS process are passed on for further manufacturing processing. Integrated circuit die12that fail testing in the EWS process are segregated out to be discarded and, if needed, subjected to a debug examination to determine why testing was failed.

In read mode, when reading the bits of the die_id from the fuses of the fuse array108, the control signal RD_FUSE is asserted. The ADDRESS_BITS for each FUSE_x of the fuse array108are sequentially generated along with assertion of the control signal ENABLE. The voltage at the fuse sensing node (FUSE_SENSING) is then detected for each applied address to determine the programmed state (blown/not blown) of each FUSE_x. The sensed voltage may be detected, for example, at a pin106of the integrated circuit12. Electrical sensing of the programmed state of each FUSE_x is typically performed during a debug examination of the integrated circuit. Such electrical sensing may also be performed in connection with the EWS process to confirm accurate programming of the die_id information.

FIG. 5is a photograph of a portion of the integrated circuit12showing six fuses within the fuse array108after programming. The distinction between blown fuses130and not blown fuses132is clearly visible and may be easily observed using imaging equipment such as a camera or a microscope. Although only six fuses are shown inFIG. 5, it will be understood that the fuse array108will include many more fuses. In an embodiment, 32 fuses are provided in the fuse array (i.e., n=5).

The fuse array108is arranged in a region109of the integrated circuit die12where it is visible to inspection. In other words, the region109of the integrated circuit die12does not include overlying circuits or structures (i.e., metal lines, vias, bonding pads, capacitor plates, inductor windings, etc.) which would obstruct an optical viewing of the fuse array108and evaluation of the blown/not blow fuse status. This is generally illustrated inFIG. 6which shows a perspective view of an integrated circuit die12showing the bonding pads140located about the periphery of the integrated circuit die, but without any obstruction by those bonding pads,140(or other circuits and structures—not explicitly shown) preventing visual observation of the fuse array108in the region109.

A cross-section of a package200including the integrated circuit die12is shown inFIG. 7. The integrated circuit die12is mounted to a die pad202with the bonding pads140of the integrated circuit die12electrically connected to package leads204by bonding wires206. The assembly is encapsulated within a package block208with the package leads204extending from the package block.

It is recognized that integrated circuit devices may fail long after leaving the factory. In such cases, the failed integrated circuit device may be returned to the manufacturer for post-mortem analysis to determine the cause of the failure. To perform the post-mortem analysis, at least a portion210of the package block208is removed to expose the top surface of the integrated circuit die12. This process is commonly referred to in the art as “decapping” (or decapsulating). With the top surface of the integrated circuit die12now exposed, a visual inspection (reference220) can be made of the integrated circuit die12. As noted above, the fuse array108is arranged in a region109of the integrated circuit die12where it is visible to inspection through the top surface of the die and without further processing of the die such as layer removal. An advantage of the implementation for die identification disclosed herein is that the blown fuses130and not blown fuses132of the fuse array108are clearly visible (FIG. 5) through the top surface of the integrated circuit die12using imaging equipment such as a camera or a microscope to perform the visible inspection. The bits of the die_id (reference226) may then be recovered from the integrated circuit die12from the blown/not blown fuse markings within the image228of the fuse array even if the damaged electronic circuits of the integrated circuit die12would otherwise preclude a circuit reading of the fuse array108(for example, using the demultiplexer circuit120, fuse sensing node (FUSE_SENSING) and pin106). From the bits of the die_id optically read from the image228of the visible fuse array108, the integrated circuit die12may be traced back to the location within the wafer10where the integrated circuit die12was manufactured as well as the specific wafer10from which that integrated circuit die12was obtained.