Vector signal alignment for digital vector processing using vector transforms

A processor receives a first vector signal and a second vector signal from a circuit in response to the circuit receiving the first vector signal. The processor transforms the second vector signal from a time domain to a transform domain. The processor rotates the transformed second vector signal by a phase that is proportional to a time delay between the first and second vector signals to time-align the second vector signal to the first vector signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 14/475,066, entitled “FRACTIONAL DELAY ESTIMATION FOR DIGITAL VECTOR PROCESSING USING VECTOR TRANSFORMS” and filed on Sep. 2, 2014, the entirety of which is incorporated by reference herein.

BACKGROUND

Field of the Disclosure

The present disclosure relates generally to signal processing and, more particularly, to digital vector signal processing.

Description of the Related Art

Temporal alignment of signals is crucial to many aspects of wireless communication systems. For example, time alignment of input signals and feedback signals reduces cross-channel interference in the power amplifiers implemented in base stations and user equipment to amplify signals for transmission over the air interface. The power amplifiers are typically operated in a non-linear mode to achieve higher efficiency and reduce power consumption. However, the non-linear response of the power amplifier increases the frequency bandwidth of the output signal (relative to the frequency bandwidth of the input signal), which increases interference between different radio frequency carriers.

Digital predistortion can compensate for the effects of the non-linear power amplifier on the output signal by applying an inverse distortion to the input signal. The inverse distortion is determined by comparing the input signal to time-aligned feedback from the output of the power amplifier. Time alignment is conventionally performed using polynomial based interpolators such as a Farrow structure. Errors or inaccuracies in the time alignment of the input and feedback signals reduce the effectiveness of predistortion. The precision of the time alignment can be increased by increasing the degree or the number of taps implemented by the interpolator, e.g., the Farrow structure. However, polynomial interpolation is computationally intensive and improving the accuracy of the interpolators requires increasing the computation time and power consumption, which is not feasible for many current and future products.

SUMMARY OF EMBODIMENTS

The following presents a simplified summary of the disclosed subject matter in order to provide a basic understanding of some aspects of the disclosed subject matter. This summary is not an exhaustive overview of the disclosed subject matter. It is not intended to identify key or critical elements of the disclosed subject matter or to delineate the scope of the disclosed subject matter. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

In some embodiments, a method is provided for aligning vector signals using vector transforms. The method includes receiving, at a processor, a first vector signal and a second vector signal from a circuit in response to the circuit receiving the first vector signal. The method also includes transforming, at the processor, the second vector signal from a time domain to a transform domain. The method further includes rotating, at the processor, the transformed second vector signal by a phase that is proportional to a time delay between the first and second vector signals to time-align the second vector signal to the first vector signal.

In some embodiments, an apparatus is provided to align vector signals using vector transforms. The apparatus includes a circuit to receive a first vector signal and generate a second vector signal in response to receiving the first vector signal. The apparatus also includes a processor to transform the second vector signal from a time domain to a transform domain and rotate the transformed second vector signal by a phase that is proportional to a time delay between the first and second vector signals to time-align the second vector signal to the first vector signal.

In some embodiments, a non-transitory computer readable medium is provided that embodies a set of executable instructions for aligning vector signals using vector transforms. The set of executable instructions manipulate a processor to receive a first vector signal and a second vector signal from a circuit in response to the circuit receiving the first vector signal. The set of executable instructions also manipulate the processor to transform the second vector signal from a time domain to a transform domain and rotate the transformed second vector signal by a phase that is proportional to a time delay between the first and second vector signals to time-align the second vector signal to the first vector signal.

DETAILED DESCRIPTION

Feedback vector signals can be accurately time-aligned with corresponding input vector signals by transforming the feedback vector signals from a time domain to a transform domain, rotating the transformed feedback vector signals in the transform domain based on a measured time delay between the feedback vector signals and the corresponding input vector signals, and then transforming the transformed feedback vector signals back into the time domain. Examples of transform kernels that may be used to transform the feedback vector signals between the time domain and the transform domain include Fourier transforms, wavelet transforms, Hartley transforms, and the like. In some embodiments, a DC offset is calculated for the feedback vector signal and removed from the feedback vector signal prior to transforming to the transform domain. The feedback vector signal may also be scaled by a gain factor determined by a ratio of power in the feedback signal (after the DC offset correction) to power in the input signal prior to transforming to the transform domain. The aligned feedback vector signal may also be scaled (after transformation back into the time domain) by a scaling factor determined based on the input signal and the aligned feedback vector signal. Aligning the feedback vector signal to the input vector signal in the transform domain may result in a minimal residue between the aligned feedback vector signal and the input vector signal.

FIG. 1is a block diagram of a wireless communication system100according to some embodiments. The communication system100includes a base station105that provides wireless connectivity according to one or more radio access technologies. For example, the base station105may be an integrated device that implements LTE communication and a Wi-Fi access point. The base station105includes a transceiver110for transmitting and receiving signals using one or more antennas115. Some embodiments of the transceiver110include one or more power amplifiers for amplifying signals that are then provided to the one or more antennas115for transmission over an air interface120.

The base station105also includes a processor125and a memory130. The processor125may be used to execute instructions stored in the memory130and to store information in the memory130such as the results of the executed instructions. Some embodiments of the processor125operate on information representative of vector signals such as digital vector signals. For example, the digital vector signals may be complex signals with in-phase (I) and quadrature (Q) components. The length of the digital vector signals may be determined by the number of samples of the signal in a predetermined time interval, such as a frame.

Some embodiments of the processor125implement a predistortion module (PD)135that is used to pre-distort input signals before providing the input signals to the transceiver110. The predistortion module135may therefore receive feedback signals from the transceiver110that correspond to the amplified output signals provided to the antenna115. The predistortion module135compares the input signal to the feedback signal to determine the predistortion that is applied to the input signal. Predistortion of the input signals compensates for nonlinearities in power amplifiers in the transceiver110so that amplifying the pre-distorted signal produces an amplified signal that is substantially equal to (e.g., within a predetermined tolerance) a linear amplification of the original input signal. Techniques for implementing predistortion are known in the art.

Signal delays in the processor125or the transceiver110can generate a temporal misalignment between the input signal and the amplified output signal, which can reduce the efficacy of predistortion in the predistortion module135. For example, if the delay between the input and output waveforms is not accurately cancelled, the residual delay causes additional dispersion in the amplitude modulation/amplitude modulation (AM/AM) and amplitude modulation/phase modulation (AM/PM) characteristics of look up tables (LUTs) that are used to define the predistortion coefficients applied to the input signal.

The processor125implements a vector alignment processor (VA)140to time-align a feedback signal from the power amplifier to the corresponding input signal. Some embodiments of the processor125receive the input vector signal and the feedback vector signal and transform the feedback vector signal from a time domain to a transform domain. For example, the vector alignment processor140may transform the feedback vector signal from the time domain to a transform domain using a Fourier transform, a wavelet transform, a Hartley transform, or other transform. The vector alignment processor140then rotates the transformed feedback vector signal by a phase that is proportional to a time delay between the input and feedback vector signals to phase-align the feedback vector signal to the input vector signal. Thus, the feedback vector signal is time-aligned to the input vector signal when the feedback vector signal is transformed back into the time domain. The time-aligned feedback vector signal may then be provided to the predistortion module135, which uses the time-aligned feedback vector to generate the predistortion that is applied to the input signal, e.g., by defining the appropriate LUTs.

The wireless communication system also includes one or more user equipment145. The user equipment145includes a transceiver150for transmitting and receiving signals over the air interface120via antenna155. The user equipment145also includes a processor160and a memory165. The processor160may be used to execute instructions stored in the memory165and to store information in the memory165such as the results of the executed instructions. Some embodiments of the processor160include a predistortion module170and a vector alignment processor175. The predistortion module170may pre-distort input signals based on time-aligned signals provided by the vector alignment processor175to compensate for nonlinearities in power amplifiers implemented in the transceiver150, as discussed herein.

FIG. 2is a block diagram of a circuit200for converting one or more digital signals into amplified analog signals suitable for transmission over an air interface by an antenna according to some embodiments. The circuit200may be implemented in some embodiments of the base station105or the user equipment145shown inFIG. 1. The circuit200receives input signals at corresponding input nodes201,202. In some embodiments, the input signals received at the input nodes201,202are digital vector signals that are generated by a processor such as the processors125,160shown inFIG. 1. Although the circuit200includes two input nodes201,202for receiving input vector signals, some embodiments of the circuit200may be configured with more or fewer input nodes to receive more or fewer input vector signals.

The circuit200includes digital-to-analog (DAC) converters205,206that are used to convert the input vector signals received at the input nodes201,202from the digital domain to the analog domain. The analog signals are then provided to corresponding low pass filters (LPF)210,211, which may be used to filter out extraneous high frequency components and provide the filtered analog signals to an up-converter215. A local oscillator (LO)220provides a signal corresponding to a transmission frequency to the up-converter215so that the up-converter215can combine the filtered analog signals and up convert the combined signals from the baseband frequency to the transmission frequency used for transmissions over the air interface. The up-converted signal is provided to a bandpass filter (BPF)225to filter out portions of the signal outside of the transmission bandwidth and provide the filtered, up-converted signal to a driver230and a power amplifier235. The amplified signal may then be provided to one or more antennas such as the antennas115,155shown inFIG. 1for transmission over the air interface.

A coupler240is used to couple a portion of the analog vector output signal generated by the power amplifier235into a feedback path245. The signal portion (referred to herein as the feedback vector signal) is provided to a down-converter250that uses a baseband frequency signal provided by a local oscillator255to down-convert the feedback vector signal from the transmission frequency to the baseband frequency. The down-converter250may also de-multiplex the feedback vector signal into multiple feedback vector signals that correspond to the input vector signals received at the input nodes201,202. The feedback vector signals are then provided to LPFs260,261to filter out high frequency components and the filtered feedback vector signals are provided to analog-to-digital converters (ADCs)265,266to convert the filtered feedback vector signals from the analog domain to the digital domain to form digital feedback vector signals.

The circuit200is coupled to a vector signal processor270that receives the input vector signals received at the input nodes201,202and the feedback vector signals corresponding to the amplified input signals generated by the power amplifier235. Portions of the circuit200between the input nodes201,202and the outputs of the ADCs265,266introduce a time delay (Tdelay) between the input vector signals and the feedback vector signals received at the vector signal processor270. As discussed herein, timing delays between the input and feedback vector signals can degrade the quality of the predistortion coefficients used to pre-distort the input vector signals to compensate for nonlinearities in the power amplifier235. The vector signal processor270may therefore use vector transforms to time align the feedback vector signals with the corresponding input vector signals. Some embodiments of the vector signal processor270use a vector forward transform to transform the feedback vector signals from a time domain to a transform domain. The vector signal processor270may then rotate the transformed feedback vector signal by a phase that is proportional to the time delay (Tdelay) between the input vector signals and the feedback vector signals received at the vector signal processor270. A vector inverse transform is applied to the rotated feedback vector signal to transform it from the transform domain back into the time domain, where it is now time aligned with the input vector signal. The input vector signal and the time-aligned feedback vector signal may be provided to the predistortion module such as the predistortion modules135,170shown inFIG. 1.

FIG. 3is a block diagram of a vector signal processor300according to some embodiments. The vector signal processor300may be used to implement some embodiments of the vector signal processor270shown inFIG. 2. The vector signal processor300receives one or more feedback vector signals at the feedback node301and one or more input vector signals at the input node302. The feedback vector signals and the input vector signals are provided to a preprocessing module305that is used to perform operations such as DC offset compensation on the feedback vector signal to remove DC offsets produced by sampling, gain control, and the like in a circuit such as the circuit200shown inFIG. 2. The preprocessing module305may also be used to scale the feedback vector signal by an amount determined by the relative powers of the input vector signal and the feedback vector signal.

The preprocessed feedback vector signal and the input vector signal are provided to a delay estimation module310, which estimates the timing delay between the preprocessed feedback vector signal and the input vector signal. In some embodiments, the delay estimation module310estimates a timing delay Tdelay=τint+τfrac, wherein τintis the integer delay and τfracis the fractional delay of the sampling period. The delay estimation module310provides the estimated timing delay to a signal alignment module315. The preprocessed feedback signal (from the preprocessing module305) is also provided to the signal alignment module315. Thus, the signal alignment module315time aligns the input vector signal with the preprocessed feedback vector signal using the estimated timing delay. A post-processing module320receives the time-aligned feedback vector signal and the input vector signal. Some embodiments of the post-processing module320perform operations such as calculating a scaling factor based on a ratio of a product of the input vector signal and the time-aligned feedback vector signal to a magnitude of the time-aligned feedback vector signal. The post-processing module320may then scale the time-aligned feedback vector signal using the scaling factor.

FIG. 4is a flow diagram of a method400for time aligning a feedback vector signal with an input vector signal according to some embodiments. The method400may be implemented in some embodiments of processor such as the vector signal processor300shown inFIG. 3, the vector signal processor270shown inFIG. 2, or the processors125,160shown inFIG. 1.

At block405, the processor shifts the feedback vector signal to compensate for a DC offset. For example, the processor may calculate the mean value,x, of the feedback vector signal, SigB:

x_=1N⁢∑k=0N-1⁢⁢SigBk
where N is the length of the feedback vector signal SigB. For example, N may indicate the number of samples of the signal in a frame. The processor may then subtract the mean value to shift the feedback vector signal to an offset-corrected feedback vector signal, MSigB:
MSigB=SigB−x

At block410, the processor calculates a gain factor using an input vector signal and the offset-corrected feedback vector signal. For example, the processor calculates a vector power PFfor the input vector signal, SigF:

PF=∑k=0N-1⁢SigFk*SigFk*
where SigF*, is the complex conjugate of the input vector signal SigF. The processor also calculates a vector power PBfor the offset-corrected feedback vector signal:

PB=∑k=0N-1⁢⁢MSigBk*MSigBk*
where MSigB* is the complex conjugate of the offset-corrected feedback vector signal MSigB. The gain factor is then computed based on a ratio of the vector powers for the input vector signal and the offset-corrected feedback vector signal:

At block415, the processor scales the offset-corrected feedback vector signal by the gain factor:
SigBP=MSigB*Gfactor

At block420, the processor transforms the scaled feedback vector signal from a time domain to a transform domain. For example, the processor may compute the vector forward transform (VFT) of the scaled feedback vector signal SigBP to obtain XB.
XB=VFT (SigBP)
where the vector forward transform (VFT) can be carried out by equation (1) or equation (2):

At block425, the processor rotates the transformed feedback vector signal based on a delay, such as a timing delay between the input vector signal and the feedback vector signal. For example, the processor may rotate the vector signal XBby a phase that is proportional to the delay Tdelayestimated by the delay estimation module310shown inFIG. 3to obtain the rotated signal vector XBR.
XBR=Rotate(XB,Tdelay)
Some embodiments of the processor may also multiply the signal vector XBby the rotated vector signal XBRto obtain the variance of the vector signal, XBS:
XBS=XB*XBR

At block430, the processor transforms the phase-aligned feedback vector signal from the transform domain to the time domain. For example, the processor may compute the inverse of the signal vector XBSby the vector inverse transform (VIT) to obtain the shifted signal vector SSigB:
SSigB=VIT(XBS)
where the vector inverse transform (VIT) can be carried out by equation (3) or equation (4):

x⁡(m)=1N⁡[∑k=0N2-1⁢⁢X⁡(2⁢⁢k)⁢UN/2-mk+UN-k⁢∑k=0N2-1⁢⁢X⁡(2⁢⁢k+1)⁢UN/2-mk](3)x⁡(m)=1N⁡[∑k=0N2-1⁢⁢X⁡(2⁢⁢k)⁢UN-2⁢⁢mk+∑k=0N2-1⁢⁢X⁡(2⁢⁢k+1)⁢UN-m⁡(2⁢⁢k+1)](4)
where U is the transform kernel and X is the signal vector. Transforming the phase-aligned feedback vector signal from the transform domain to the time domain generates the time-aligned feedback vector signal.

At block435, the processor scales the time-aligned feedback vector signal by a scaling factor. For example, the processor can compute Cnum:

Cnum=∑k=0N-1⁢⁢SigFk*SSigBk*
The processor also computes Cden:

Cden=∑k=0N-1⁢⁢SSigBk*SSigBk*
The processor may then use these quantities to compute the scaling factor:

Sfac=CnumCden
The processor shifts the time-aligned feedback vector signal by multiplying with the scaling factor:
SSigBF=SSigB*Sfac
The vector signal SSigBF is the vector signal aligned with the feed-forward signal with minimal residue.

The timing delays, gains, scaling factors, and other quantities used to time align the input vector signal and the feedback vector signal may change between different time intervals. For example, some or all these quantities may change from frame-to-frame during transmissions over an air interface between a base station and one or more user equipment. Some embodiments of the method400may therefore be iterated at a predetermined time interval or in response to other events such as detecting changes in one or quantities used to time align the input vector signal and the feedback vector signal.