Bias circuit and analog integrated circuit comprising the same

Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefits, under 35 U.S.C. §119, of Korean Patent Application No. 10-2010-0128376 filed Dec. 15, 2010, the entirety of which is incorporated by reference herein.

BACKGROUND

Exemplary embodiments relate to an analog integrated circuit, and more particularly, relate to a bias circuit of an analog integrated circuit.

A switched-capacitor circuit may be widely used to design analog integrated circuits such as an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a sigma-delta analog-to-digital converter, and the like. The switched-capacitor circuit may necessitate an excellent settling characteristic to secure an exact operation of the analog integrated circuit.

A settling time of the settling characteristic of the switched-capacitor circuit may be reduced by increasing a bandwidth and a slew rate. In particular, if the slew rate is low, the settling time of the switched-capacitor circuit may increase due to a long slew time.

SUMMARY

A bias circuit and an analog integrated circuit including the same may be provided to improve a slew rate.

One aspect of embodiments of the inventive concept is directed to provide a bias circuit which comprises a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals.

In this embodiment, the bias circuit further comprises a source follower part configured to receive the at least two input signals and to increase or decrease the voltage levels of the at least two input signals.

In this embodiment, the source follower part comprises a first source follower configured to receive first and second input signals of the at least two input signals and to output first and second signals having voltage levels lower than the first and second input signals; and a second source follower configured to receive the first and second input signals and to output third and fourth signals having voltage levels higher than the first and second input signals.

In this embodiment, the current adjusting part comprises a first branch configured to form a current path for providing the variable current to the bias voltage generating part in response to the first and fourth signals; and a second branch configured to form a current path for providing the variable current to the bias voltage generating part in response to the second and third signals.

In this embodiment, if a voltage level of the first input signal is identical to that of the second input signal, the first and second branches break the current paths for providing the variable current to the bias voltage generating part.

In this embodiment, if a voltage difference between the first and second input signals is over a predetermined level, one of the first and second branches forms the current path for providing the variable current to the bias voltage generating part.

In this embodiment, the first branch includes a first transistor forming a current path in response to the first signal and a second transistor forming a current path in response to the fourth signal, and the second branch includes a third transistor forming a current path in response to the second signal and a fourth transistor forming a current path in response to the third signal.

In this embodiment, the first and third transistors are formed of a PMOS transistor and the second and fourth transistors are formed of an NMOS transistor. The first and second transistors in the first branch are connected in series each other and the third and fourth transistors in the second branch are connected in series each other.

In this embodiment, each of the source follower part and the current adjusting part includes a plurality of transistors and sizes of transistors in the source follower are larger than those in the current adjusting part.

Another aspect of embodiments of the inventive concept is directed to provide an analog integrated circuit which comprises an operational amplifier configured to receive and amplify at least two input signals; and a bias circuit configured to receive the at least two input signals and to supply a bias voltage to the operational amplifier, wherein the bias circuit adjusts a voltage level of the bias voltage supplied to the operational amplifier according to voltage levels of the at least two input signals.

DETAILED DESCRIPTION

FIG. 1is a diagram illustrating a switched-capacitor circuit according to an exemplary embodiment of the inventive concept. InFIG. 1, a sample-and-hold circuit (hereinafter, referred to as an S/H circuit) is exemplarily illustrated as an example of a switched-capacitor circuit. For ease of description, it is assumed that the switched-capacitor circuit100receives two input signals Vinp and Vinn. However, the inventive concept is not limited thereto. For example, the switched-capacitor circuit100may receive at least two input signals. Referring toFIG. 1, the switched-capacitor circuit100may include a plurality of switches SW1to SW10, a plurality of capacitors C1to C4, a bias circuit110, and an operational amplifier120.

FIG. 2is a timing diagram illustrating a sampling phase P1and an amplification phase P2for controlling a sampling operation and an amplification operation of a switched-capacitor circuit inFIG. 1. If the sampling phase P1is at a logic high level, a sampling operation may be carried. If the amplification phase P2is at a logic high level, an amplification operation may be performed.

Referring toFIGS. 1 and 2, when the sampling phase P1is at a logic high level, switches SW1, SW2, SW5, SW6, SW9, and SW10may be turned on. At this time, the first and second input signals Vinp and Vinn may be sampled by the first and second capacitors C1and C2, respectively. A voltage difference between the first and second input signals Vinp and Vinn may be referred to as a differential input signal.

When the amplification phase P2is at a logic high level, switches SW3, SW4, SW7, and SW8may be turned on. At this time, the differential input signal may be amplified, and the first and second output signals Voutp and Voutn may be issued. A voltage difference between the first and second output signals Voutp and Voutn may be referred to as a differential output signal.

FIGS. 3 and 4are diagrams illustrating a settling time according to a slew rate of a switched-capacitor circuit inFIG. 1. A settling time when a switched-capacitor circuit100has a low slew rate is illustrated inFIG. 3, and a settling time when the switched-capacitor circuit100has a high slew rate is illustrated inFIG. 4.

As illustrated inFIG. 3, if the switched-capacitor circuit100has a low slew rate, a slew time may be generated, and a settling time may increase due to the slew time. A long settling time may hinder a high-speed operation of the switched-capacitor circuit100. For this reason, a high-speed operation of the switched-capacitor circuit100may be accomplished by improving a slew rate. The slew rate may be expressed by the following equation.
SR=dVo/dt=Ibs/C2
Vo=Voutp−Voutn

Herein, ‘SR’ may indicate a slew rate, and ‘Vo’ may indicate a differential output signal. ‘Ibs’ may indicate a maximum current signal capable of being supplied to an operational amplifier. The slew rate may be improved by reducing a size of a capacitor or increasing the maximum current signal Ibs of the operational amplifier. A method of improving a slew rate by adjusting a capacitor size of the switched-capacitor circuit100may cause an increase in noise and lowering of the stability. The switched-capacitor circuit100inFIG. 1may improve the slew rate by increasing the maximum current signal Ibs of the operational amplifier.

A method of increasing the maximum current signal Ibs of the operational amplifier may cause an increase in power consumption. That is, power consumption may increase by increasing the maximum current signal Ibs regardless of a magnitude of a differential input signal (i.e., a voltage difference between the first input signal Vinp and the second input signal Vinn). Below, a switched-capacitor circuit according to another exemplary embodiment of the inventive concept will be more fully described. As will be described below, the switched-capacitor circuit according to another exemplary embodiment of the inventive concept may prevent an increase in power consumption and may improve a slew rate at the same time.

FIG. 5is a block diagram illustrating a switched-capacitor circuit according to another exemplary embodiment of the inventive concept. InFIG. 5, an S/H circuit is exemplarily illustrated as an example of a switched-capacitor circuit200. LikeFIG. 1, for ease of description, it is assumed that the switched-capacitor circuit100receives two input signals Vinp and Vinn. However, the inventive concept is not limited thereto. For example, the switched-capacitor circuit200may receive at least two input signals.

The switched-capacitor circuit200inFIG. 5may be similar to that inFIG. 1. A difference between the switched-capacitor circuits100and200inFIGS. 1 and 5will be described.

Referring toFIG. 5, the switched-capacitor circuit200may include a plurality of switches SW1to SW10, a plurality of capacitors C1to C4, a dynamic bias circuit210, and an operational amplifier220. Unlike the switched-capacitor circuit100inFIG. 1, the switched-capacitor circuit200may include the dynamic bias circuit210. The dynamic bias circuit210may include a current adjusting part213.

While a bias circuit100inFIG. 1supplies a fixed bias voltage (or, a bias current) to an operational amplifier120inFIG. 1, the dynamic bias circuit210inFIG. 5may provide the operational amplifier220with a bias voltage (or, a bias current) varied according to a magnitude of a differential input signal. For example, as a magnitude of the differential input signal becomes large (i.e., as a voltage difference between the first and second input signals Vinp and Vinn becomes large), the dynamic bias circuit210may provide a high level of a bias voltage to the operational amplifier.

As a level of the bias voltage is controlled according to a magnitude of the differential input signal, the switched-capacitor circuit200may improve a slew rate to power consumption as compared with the switched-capacitor circuit100inFIG. 1. The dynamic bias circuit210will be more fully described with reference toFIGS. 6 and 7.

FIG. 6is a block diagram illustrating a dynamic bias circuit inFIG. 5according to an exemplary embodiment of the inventive concept. Referring toFIG. 6, a dynamic bias circuit210may include a reference current source part211, a source follower part212, a current adjusting part213, and a bias voltage generating part214.

The reference current source part211may provide a current source to the dynamic bias circuit210. For example, the reference current source part211may generate a reference current to supply it to the source follower part212and the bias voltage generating part214.

The source follower part212may receive the first amplifier input signal AMP_INP and the second amplifier input signal AMP_INN. Herein, the first amplifier input signal AMP_INP and the second amplifier input signal AMP_INN may be provided to an operational amplifier220, respectively. A voltage difference between the first amplifier input signal AMP_INP and the second amplifier input signal AMP_INN may be proportional to a voltage difference (i.e., a differential input signal) between the first input signal Vinp and the second input signal Vinn.

The source follower part212may have a predetermined voltage gain (e.g., a voltage gain of 1), and may generate a plurality of voltages Vinp_psf, Vinn_nsf, Vinp_nsf, and Vinn_psf. Herein, the voltages Vinp_nsf and Vinn_nsf may be lower in level than the first and second amplifier input signal AMP_INP and AMP_INN, respectively. The voltages Vinp_psf and Vinn_psf may be higher in level than the first and second amplifier input signal AMP_INP and AMP_INN, respectively.

The current adjusting part213may include the first branch213_1and the second branch213_2. The first branch213_1may receive the voltages Vinn_psf and Vinn_nsf from the source follower part212, and the second branch213_2may receive the voltages Vinp_psf and Vinn_nsf from the source follower part212. The current adjusting part213may provide a variable current Iv to the bias voltage generating part214.

The current adjusting part213may adjust the amount of the variable current Iv provided to the bias voltage generating part214according to the voltages Vinp_psf, Vinn_nsf, Vinp_nsf, and Vinn_psf input from the source follower part212. That is, the current adjusting part213may adjust the amount of the variable current Iv according to a voltage difference between the first and second amplifier input signal AMP_INP and AMP_INN.

If a voltage difference between the first and second amplifier input signal AMP_INP and AMP_INN is less than a predetermined level, the first and second branches213_1and213_2may be turned off, and no variable current Iv may be supplied to the bias voltage generating part214.

If a voltage difference between the first and second amplifier input signal AMP_INP and AMP_INN is more than a predetermined level, the first or second branch213_1or213_2may be turned on, and the variable current Iv may be supplied to the bias voltage generating part214. In this case, the amount of the variable current Iv provided to the bias voltage generating part214may be proportional to a voltage difference between the first and second amplifier input signal AMP_INP and AMP_INN.

The bias voltage generating part214may receive a reference current from the reference current source part211and the variable current Iv from the current adjusting part. The bias voltage generating part214may generate a bias voltage Vbs for an operational amplifier220inFIG. 5using the reference current and the variable current Iv. Since the amount of the variable current Iv is proportional to a voltage difference between the first and second amplifier input signal AMP_INP and AMP_INN, a voltage level of the bias voltage Vbs may be varied according to a voltage difference between the first and second amplifier input signal AMP_INP and AMP_INN.

FIG. 7is a circuit diagram illustrating a dynamic bias circuit inFIG. 6.

A reference current source part211may include a plurality of transistors MP1, MP2, MN1, and MN4. The reference current source part211may generate a reference current Iref and may provide a current to a source follower part212and a bias voltage generating part214using a current mirror structure.

The source follower part212may receive the first amplifier input signal AMP_INP, and may generate voltages Vinp_nsf and Vinp_psf via the NMOS source follower MNS1and MN2and the PMOS source follower MPS2and MP3, respectively. The source follower part212may receive the second amplifier input signal AMP_INN, and may generate voltages Vinn_nsf and Vinn_psf via the NMOS source follower MNS2and MN3and the PMOS source follower MPS1and MP4, respectively.

Herein, the voltage Vinp_nsf may have a voltage level lower by a gate-source voltage Vgsn of a transistor MNS1than a voltage level of the first amplifier input signal AMP_INP. The voltage Vinn_nsf may have a voltage level lower by a gate-source voltage Vgsn of a transistor MNS2than a voltage level of the second amplifier input signal AMP_INN. Further, the voltage Vinp_psf may have a voltage level lower by a gate-source voltage Vgsn of a transistor MPS2than a voltage level of the first amplifier input signal AMP_INP. The voltage Vinn_psf may have a voltage level lower by a gate-source voltage Vgsn of a transistor MPS1than a voltage level of the second amplifier input signal AMP_INN.

The current adjusting part213may be formed of two branches, each of which is formed of a PMOS transistor and an NMOS transistor. In particular, the first branch may be formed of a PMOS transistor MPC1and an NMOS transistor MNC1. The PMOS transistor MPC1and the NMOS transistor MNC1in the first branch may form current paths in response to the voltage Vinp_nsf and the voltage Vinn_psf, respectively. The second branch may be formed of a PMOS transistor MPC2and an NMOS transistor MNC2. The PMOS transistor MPC2and the NMOS transistor MNC2in the second branch may form current paths in response to the voltage Vinn_nsf and the voltage Vinp_psf, respectively.

The transistors MPC1, MPC2, MNC1, and MNC2of the current adjusting part213may be designed to have less sizes (or, a width/length ratio) than the transistors MNS1, MNS2, MPS1, and MPS2of the source follower part212.

The bias voltage generating part214may include a plurality of transistors MN5to MN9and MP5to MP10. The bias voltage generating part214may generate bias voltages Vbs1to Vbs4for an operational amplifier220inFIG. 5using a current Imn5flowing via a transistor MN5and a current Imp5flowing via a transistor MP5. The bias voltage generating part214may generate four bias voltages. However, the inventive concept is not limited thereto. The number of bias voltages generated by the bias voltage generating part214may be determined variously.

Below, an operation of the dynamic bias circuit will be more fully described. For ease of description, there will be described the cases that a voltage level of the first amplifier input signal AMP_INP is identical to that of the second amplifier input signal AMP_INN and that a voltage level of the first amplifier input signal AMP_INP is higher than that of the second amplifier input signal AMP_INN.

In the event that a voltage level of the first amplifier input signal AMP_INP is identical to that of the second amplifier input signal AMP_INN, a voltage difference (Vinn_psf−Vinp_nsf) of voltages provided to transistors MPC1and MNC1of the first branch may become (Vgsp+Vgsn). Since a size (or, a width/length ratio) of transistors of a current adjusting part213is smaller than that of transistors of a source follower part212, the transistors MPC1and MNC1of the first branch may be turned off due to the voltage difference being (Vgsp+Vgsn).

Like transistors MPC1and MNC1of the first branch, a voltage difference (Vinn_psf−Vinp_nsf) of voltages provided to transistors MPC2and MNC2of the second branch may become (Vgsp+Vgsn). Like the transistors MPC1and MNC1of the first branch, the transistors MPC2and MNC2of the second branch may be turned off.

As a result, the current adjusting part213may break a current path of a current (i.e., a variable current Iv inFIG. 6) provided to the bias voltage generating part214via the first or second branch. Accordingly, a current flowing via transistors MN5and MP5of the bias voltage generating part214may be identical in amount to a current Imn4flowing via a transistor MN4of the reference current source part211. The bias voltage generating part214may generate the bias voltages Vbs1to Vbs4on the basis of the current Imn4.

Below, the case that a voltage level of the first amplifier input signal AMP_INP is higher than that of the second amplifier input signal AMP_INN will be described. In this case, it is assumed that a difference between the first amplifier input signal AMP_INP and the second amplifier input signal AMP_INN is Vdiff.

In the event that a difference between the first amplifier input signal AMP_INP and the second amplifier input signal AMP_INN is Vdiff, a voltage difference (Vinn_psf−Vinp_nsf) of voltages provided to transistors MPC1and MNC1of the first branch may become (Vgsp+Vgsn−Vdiff). Accordingly, the transistors MPC1and MNC1of the first branch may be turned off.

However, a voltage difference (Vinn_psf−Vinp_nsf) of voltages provided to the transistors MPC2and MNC2of the second branch may become (Vgsp+Vgsn+Vdiff). Accordingly, the transistors MPC2and MNC2of the second branch may be turned on. In this case, the higher a voltage level of Vdiff, the more the amount of a current (i.e., a variable current Iv) flowing via the transistors MPC2and MNC2of the second branch.

A current Imp5flowing via a transistor MP5of the bias voltage generating part214and a current Imn5flowing via a transistors MN5thereof may increase by the amount corresponding to a sum of a current Imn4provided to the reference current source part211and the variable current Iv provided from the current adjusting part213. Accordingly, the bias voltage generating part214may generate high bias voltages Vbs1to Vbs4as a voltage difference between the first and second amplifier input signals AMP_INP and AMP_INN becomes large.

As a voltage difference between the first input signal Vinp and the second input signal Vinn becomes large, the dynamic bias circuit210may provide a high level of a bias voltage to an operational amplifier220inFIG. 5. A slew rate may be improved by increasing a maximum current signal Ibs using the bias voltages Vbs1to Vbs4.

In a case where a voltage level of the second amplifier input signal AMP_INN is higher than that of the first amplifier input signal AMP_INP, the transistors MPC1and MNC1of the first branch may be turned on, and the transistors MPC2and MNC2of the second branch may be turned on. This may be similar to the case that a voltage level of the first amplifier input signal AMP_INP is higher than that of the second amplifier input signal AMP_INN, and description thereof is thus omitted.

InFIGS. 6 and 7, the dynamic bias circuit210may receive two amplifier input signals AMP_INN and AMP_INP. However, the inventive concept is not limited thereto. For example, the dynamic bias circuit210may receive at least two amplifier input signals.

FIG. 8is a circuit diagram illustrating an operational amplifier supplied with bias voltages from a dynamic bias circuit inFIG. 6. For ease of description, it is assumed that an operational amplifier220inFIG. 8receives two input signals Vinp and Vinn and four bias voltages Vbs1to Vbs4. However, the inventive concept is not limited thereto. The number of input signals and bias voltages provided to the operational amplifier may be changed variously.

Referring toFIG. 8, a rail-to-rail cascode operational amplifier is exemplarily illustrated as an example of an operational amplifier. The rail-to-rail cascode operational amplifier may be used as a source driver of a liquid crystal display device, as well known in the art. A slew time of the operational amplifier220inFIG. 8may be proportional to a time taken to discharge or charge a capacitor Cc, and may be determined according to a size of the capacitor Cc and an inner current Iss.

The operational amplifier inFIG. 8may be supplied with bias voltages Vbs1to Vbs4from the dynamic bias circuit210inFIG. 6. Voltages Vbp and Vbn may be also supplied to the operational amplifier. Internal currents Ip, Iss, and Ip−Iss flow through transistors in the operation amplifier as shown inFIG. 8. In the event that a large differential input signal is provided to the operational amplifier220(i.e., a voltage difference between the first input signal Vinp and the second input signal Vinn is large), an internal current Iss of the operational amplifier may increase. This means that a slew rate of the operational amplifier220is improved.

As described inFIGS. 5 to 8, the dynamic bias circuit210may be applied to an S/H circuit. However, the inventive concept is not limited thereto. For example, the dynamic bias circuit210can be applied to various analog integrated circuits.

FIG. 9is a diagram illustrating a switched-capacitor integrator including a dynamic bias circuit according to an exemplary embodiment of the inventive concept. For ease of description, it is assumed that a switched-capacitor integrator300inFIG. 9receives two input signals Vinp and Vinn. However, the inventive concept is not limited thereto. For example, the switched-capacitor integrator300inFIG. 9can receive at least two input signals.

The switched-capacitor integrator300inFIG. 9may be mainly used at an analog filter or a sigma-delta ADC. The switched-capacitor integrator300may perform a switching operation according to a sampling phase P1and an integration phase P2, and may the sampling and integration phases P1and P2may be similar to sampling and amplification phases P1and P2inFIG. 2.

The switched-capacitor integrator300may include a dynamic bias circuit310. The dynamic bias circuit310may be configured the same as that210described with reference toFIGS. 6 and 7. Accordingly, like the S/H circuit, the switched-capacitor integrator300may prevent an increase in power consumption and improve a slew rate at the same time.