Tilted array geometry for improved MRAM switching

An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with a corresponding set of mutually parallel conductive traces wherein individual conductive traces within the sets intersect adjacent individual MRAM cells and wherein the tilting of the at least one set of conductive traces acts to induce both a vertical and horizontal component of a magnetic field such that the net vector addition of magnetic fields induced by the sets of conductive traces is greater than the untilted or perpendicular configuration so as to induce a greater net magnetic field to effect more reliable switching of the underlying MRAM cells. The tilted array also enables reducing the current supplied by the conductive traces while maintaining a comparable net magnetic field to the untilted configuration.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of magnetoresistive random access memory (MRAM) and, in particular, to a tilted array geometry for improved MRAM switching.

2. Description of the Related Art

Traditional electronic memory media have included magnetic core memory, magnetic tapes, and semiconductor based memory. Semiconductor based memory includes such types as random access memory (RAM), read-only-memory (ROM), and flash memory. Semiconductor RAM offers the advantage of fast access, however, it suffers the liability of volatility. The transistors and capacitors comprising semiconductor RAM depend on their conductive or charge state, respectively, to store digital data. Accordingly, the transistors and capacitors must be powered to maintain data stored therein and periodically refreshed. If the circuit loses power even briefly, the information is lost. Thus, semiconductor RAM is referred to as volatile memory.

Semiconductor based memories also suffer from a susceptibility to radiation corruption. Incident radiation can create stray carriers and resultant currents in the semiconductor devices and corrupt information stored therein. Radiation exposure occurs routinely in terrestrial unshielded applications, however, the level of radiation can be several orders of magnitude greater in space. Space vehicles and military equipment are, therefore, typically provided with specially hardened and shielded electronics. However, the shielding and hardening add substantial cost and complexity to such systems.

MRAM is a developing technology that offers the advantages of non-volatility, radiation hardness, and high density. MRAM employs the spin property of electrons and a physical property known as giant magnetoresistance (GMR). A spinning charged body, such as an electron, induces a magnetic field. In the presence of an external magnetic field, the spin of the electron is in one of two directions, either “up spin” or aligned with the magnetic field, or “down spin” or anti-parallel to the magnetic field. Thus, the magnetic field of the electron is either directed “up” or “down” or parallel or anti-parallel with the external magnetic field.

The electrons in most materials are randomly oriented with an electron of any particular orientation being compensated for by an oppositely oriented electron so that the material has no bulk magnetization. However, certain metals, such as Co, Fe, and Ni, as well as certain compounds, can exhibit a bulk magnetization. The electrons in such materials gain energy when they are aligned together and, when they do so, the material retains and exhibits a gross, bulk magnetization. Such materials are termed ferromagnetic.

When thin layers (100-101atoms thick) of certain ferromagnetic and non-ferromagnetic metals (for example alternating layers of Fe and Cr or Co and Cu) are layered in particular ways, they exhibit variable electrical conductivity depending on the magnetization state of the layers. In particular, if the layers are magnetized in the same direction, the layered material exhibits low electrical resistivity whereas if adjacent layers are magnetized in opposite directions, the layered material exhibits a high electrical resistivity. The up or down spin of the electrons are believed to interact with the bulk magnetization of the layered materials to either facilitate or impede the flow of the electrons under an electric field. When the layers are aligned in the same direction, either the “up” or “down” electrons can travel through the material with minimal scattering and, thus, with low resistivity. The complementary type of electrons will be scattered and experience a higher resistivity. However, in the case where adjacent layers are oppositely magnetized, both “up” and “down” electrons will be scattered by one orientation of layers and, thus, all electrons will be scattered with none seeing an advantageously oriented material.

MRAM employs this variable resistivity to define logic states wherein the high and low resistivity states represent a logical “1” or “0”. Individual cells of layered GMR materials are magnetized or not to form a binary logic state and thus a memory circuit element.

MRAM circuits typically employ an array of conductive lines arranged in an orthogonal geometry as illustrated in FIG.1. The row and column lines are positioned to intersect adjacent each MRAM cell. When an electrical current is supplied to one of the lines, a magnetic field is induced according to well-understood electromagnetic principles. A row current Irowgenerates a transverse magnetic field Hyand a column current Icolgenerates a longitudinal magnetic field Hxthrough the MRAM cells. The induced magnetic field Hyor Hximpinges on all cells in the corresponding row or column and partially magnetizes those cells. The magnitude of the current in the row and column lines as well as the dimensions and materials of the MRAM cells are chosen such that both a row and a column current is required for the cell to exceed a write threshold in order to switch logic states. In particular, a row or column current by itself should be insufficient to switch a cell, however, applying both a row and a column current will switch the cell at the intersection of the two lines.

FIG. 2illustrates the switching/no-switching regions of operation for an MRAM cell array. The half-select points are the condition where exclusively a row or a column current is applied. The half-select condition should not switch the cells in the corresponding row or column unless a complementary column or row current is also applied to a particular cell. The full-select point represents a cell where both a row and a column current are applied. The dashed line indicates the condition of equal row and column fields and orthogonal row and current lines. The curve illustrates that the row and column current can be independently varied and the boundary between switching and non-switching conditions. The vector addition of Hxand Hymust result in a total H magnitude to the right of the curve to reliably switch the cell.

This switching protocol places severe requirements on the process tolerances as well as the line currents. An excessive row or column current can inadvertently switch cells in the corresponding row or column that are not intended to be switched. Conversely, an inadequate row or column current can fail to switch a cell when desired. In a similar manner, if the materials or dimensions of a cell vary excessively, the cell can be unintentionally switched or not-switched. These considerations place design constraints on the process as well as present obstacles to scaling the devices for increased circuit density.

Another design goal of electronic circuits in general, including MRAM technologies, is to reduce the drive current for switching. Reducing the drive current reduces the power consumption of the circuit, and incurs less resistive heating within the circuit, and can reduce the size and weight of power supplies. Particularly as the conductive line widths are reduced through scaling, the need to minimize resistive heating becomes acute.

From the foregoing, it can be appreciated that there is a need for an MRAM array geometry that offers improved switching. There is also a need for an array geometry that offers increased fault tolerance and reduced current switching requirements.

SUMMARY OF THE INVENTION

The aforementioned needs are satisfied by the invention, which, in one aspect, is an MRAM array comprising a substrate, a plurality of MRAM devices distributed over the substrate, a first set of parallel conductors that are positioned adjacent a first side of the plurality of MRAM devices, and a second set of parallel conductors that are positioned adjacent a second side of the plurality of MRAM devices wherein the first set and second set of parallel conductors intersect in at least one plane at a plurality of locations adjacent the plurality of MRAM devices such that at the plurality of locations, each of the first and second set of conductors intersect at an angle offset from perpendicular wherein the angle is selected to increase the net magnetic field sensed by one of the plurality of MRAM devices when current is simultaneously applied to a corresponding one of the first set and the second set of conductors.

In one aspect, the first set of parallel conductors comprise a column address array and the second set of parallel conductors comprise a row address array. The first set of parallel conductors may be positioned in the substrate underneath the plurality of MRAM devices and the second set of parallel conductors may be positioned over the plurality of MRAM elements such that the plurality of MRAM elements are interposed between the first and second plurality of conductors.

In another aspect, the plurality of MRAM devices have a first lateral dimension defining a major axis and a second lateral dimension defining a minor axis wherein the first lateral dimension is greater than the second lateral dimension. The first set of parallel conductors may be positioned with respect to the plurality of MRAM devices such that the direction of the first set of parallel conductors is offset from the major axis by the angle. In certain aspects, the angle is between approximately 0 degrees and 45 degrees and the plurality of MRAM devices include a pinned layer a sense layer and a tunnel layer interposed between pinned and sense layer.

In a further aspect, the invention is a memory device comprising a memory cell, wherein the memory cell is configured to have at least a first and a second magnetic state and to switch therebetween in response to the application of an external magnetic field and wherein the memory cell has a first dimension defining a first axis and a second dimension, less than the first dimension, defining a second axis, a first conductor positioned adjacent the memory cell, and a second conductor positioned adjacent the memory cell, wherein the memory cell changes between the first and second magnetic states when current is simultaneously applied in both the first and second conductors and wherein the first and second conductors are positioned with respect to each other so as to intersect in at least one plane adjacent the memory cell and wherein the first conductor is positioned so as to be directed at an angle with respect to the first axis of the memory cell that is selected to enhance the strength of the magnetic field sensed by the memory cell when current is applied to the first and second set of conductors to thereby enhance the reliability of the magnetic cell switching as a result of the applied external magnetic field.

In certain aspects, the memory cell comprises an MRAM cell and the MRAM device may include a pinned layer, a sense layer, and a tunnel layer interposed therebetween. In particular aspects, the MRAM device is interposed between the first and second conductor and the memory device further comprises a substrate wherein the first conductor is formed in the substrate and wherein the MRAM device is formed on a surface of the substrate adjacent the first conductor. The memory device may also include an interlayer dielectric layer formed adjacent the MRAM device wherein the second conductor is positioned on the interlayer dielectric layer so as to be positioned adjacent an upper surface of the MRAM device. The angle is between 0 and 45 degrees in particular aspects of the invention.

In yet another aspect, the invention is a memory device comprising a substrate, a plurality of MRAM devices formed on the substrate wherein each of the plurality of MRAM devices have a major axis and are changeable between a first and second memory state as a result of an applied magnetic field, a first set of conductors positioned adjacent the plurality of MRAM devices, and a second set of conductors positioned adjacent the plurality of MRAM devices wherein the MRAM devices are configured to only change between the first and second memory state by a simultaneous current flow through a corresponding first and second conductor and wherein the simultaneous current flow through the conductors creates two orthogonal components of the magnetic field and wherein the plurality of second conductors are oriented with respect to the plurality of MRAM devices such that one of the orthogonal components is increased while the second component is decreased such that the overall net magnetic field applied to the corresponding MRAM device is increased in the direction of the major axis thereby improving the reliability of switching the MRAM device between the first and second memory state.

In certain aspects, the first plurality of conductors are positioned in the substrate underneath the plurality of MRAM devices and the second plurality of conductors are positioned over the plurality of MRAM elements such that the plurality of MRAM elements are interposed between the first and second plurality of conductors. The first plurality of conductors may be positioned with respect to the plurality of MRAM devices such that the direction of the first plurality of conductors is offset from the major axis by an acute angle and the acute angle may be between approximately 0 degrees and 45 degrees.

These and other objects and advantages of the present invention will become more fully apparent from the following description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference will now be made to the drawings wherein like numerals refer to like parts throughout.FIG. 3illustrate a single MRAM cell112of an array of MRAM cells112schematically illustrated in FIG.4A. As is illustrated inFIG. 3, the MRAM cell112is formed on a substrate150and two orthogonal conductors102and104are formed adjacent the cell112. In this embodiment, the substrate includes a trench151in which the column conductor line104is formed. Typically, the column conductor line104is formed of copper using well known damascene processing techniques and the substrate150is typically an isolation material such as boro-phosphosilicate glass (BPSG).

The cell112is then formed on an upper surface152of the substrate150using known patterning and etching techniques. As is generally understood, the cell112typically includes three layers: a magnetic pinned layer154, a magnetic sense layer156, and an interposed tunnel layer158. The magnetic pinned layer154in this illustration is electrically connected to the conductor line104and the magnetic sense layer156is connected to the conductor line102in a manner that will be described in greater detail hereinbelow. The operation of the cell112is typical to the operation of any of a number of well known MRAM cells and the cell illustrated inFIG. 3is a simple example of these types of devices.

As is illustrated inFIG. 3, an interlayer dielectric (ILD)162is formed on the upper surface152of the substrate150after formation of the cell112using known patterning and etching techniques. The conductor102is then formed on the ILD162using known techniques and is electrically connected to the sense layer156through a via or other known structure. Hence, the cell112is positioned between the two conductors102,104. The cell112is programmed as a result of simultaneous application of current to the two conductors102,104.

In particular, the pinned layer154of the cell112has a fixed magnetic field but the sense layer156can be programmed to have one of two magnetic fields such that the electrical resistance through the cell112can be varied between two logic states. It will be appreciated from the following description that the structure and formation of the MRAM element112can be any of the number of different structures without departing from the spirit of the present invention and the MRAM cell112is simply exemplary of one such element.

As is illustrated inFIGS. 3,4A, and4B, the conductors102and104intersect in a vertical plane at a point106. The tilted array geometry100results in the intersection being at an angle α from perpendicular.

As shown inFIG. 4A, the tilted array geometry100comprises a plurality of mutually parallel row lines102and mutually parallel column lines104wherein the row lines102and column lines104intersect at a plurality of intersections106at the angle α110from perpendicular.

As discussed above, the intersections106are adjacent the plurality of MRAM cells112. In this embodiment, the MRAM cells112are elongate structures having a major axis113. In this embodiment, the row lines102are tilted by the angle α110from perpendicular with the column lines104as well as from the major axis113of the MRAM cells112. During fabrication of the array of cells112, mask structures are formed so as to offset the row lines102from the major axis113of the cells112by the angle α110. In the embodiment of the cell112illustrated inFIG. 3, this requires the ILD layer162and the conductor102to be patterned so as to extend in the tilted manner.

By tilting the array of cells by the pre-selected angle α110, the magnitude of the net magnetic field that is applied to the cells112can be increased without increasing the current through the row102or column104lines. As discussed above, the sense layer156is programmed by the application of a magnetic field resulting from current flowing simultaneously through the conductors102and104. Preferably, the sense layer156is configured such that current flowing through only one of the conductors102,104is insufficient to switch the magnetic state and, thus, the logic state of the corresponding individual cells112. However, individual cells112of the array can be switched through simultaneous application of a row102and column104current. Since the row102in this embodiment is tilted, the net magnetic force applied to the sense layer156is increased.

Specifically, supplying an electrical current to a row line102will induce a longitudinal magnetic field Hy114and supplying a current to a column line104will induce a transverse magnetic field Hx116through the MRAM cell112adjacent the intersection106of the row102and column104lines. In this embodiment, the tilted row lines102induce a lower longitudinal magnetic field ΔHy120and a higher transverse magnetic field Hx116through the MRAM cell112. In particular, Hx116increases by ΔHx122=HyoSin α and Hy114decreases by ΔHy120=Hyo(1−Cos α) where Hxo=Hyo=Hoand where Hois the transverse and longitudinal magnetic field of an untilted array wherein the row and column lines are orthogonal and a is the angle α110.

As a result of these relationships, an angular value can be selected for the angle α110such that it results in greater αHx122than the corresponding αHy120. Specifically, for angles α110less than 45 degrees, there is a net increase in the total magnetic field applied to the cell112.

As an example, for an angle α110of 5°, αHx122=0.09Hyoand αHy120=−0.004Hyo. Thus, the increase in Hx116is approximately 23 times greater than the decrease in Hy114for an angle α110of 5° and the net magnetic field is increased. In this embodiment, the increased Hx116is aligned with the major axis113of the MRAM cells112so as to increase the magnetization of the MRAM cells112to improve the write performance of the tilted array geometry100.FIG. 5illustrates the changes αHx122and αHy120in Hx116and Hy114for angles α110between 0° and 180°. In order to maximize the gain in Hx116while minimizing impact on circuit topography, the angle α110is preferably maintained around 45 degrees.

FIG. 6illustrates the switching/non-switching regions of operation as well as a tilted full-select point124for the tilted array geometry100as previously described. In particular, the tilted full-select point124is further into the switching region and thus provides additional reliability in MRAM cell112switching than a non-tilted system. Specifically, the boundary between the switching region and the non-switching region defines the curve200in FIG.6. In the prior art, when the magnitude of the magnetic field components Hyand Hx. are approximately the same, the minimum amount of current needed to activate the switch occurs as point202. However, at this point202, small variations in the current may result in the MRAM cell112not being activated when desired or the cell112being unintentionally activated. Consequently, in the prior art, larger amounts of current are typically used to activate the device at a greater cost in power consumption and generated heat.

However, as illustrated inFIG. 6, the full-select point124for the tilted array geometry100is shifted to the right in the diagram of FIG.6. As the boundary between the switching region and the non-switching region is decreasing, the full-select activation point124is farther from the boundary thereby resulting in more reliable activation of the MRAM cell112.

In an alternative embodiment, the current in the column lines104can be reduced so that Hx116=Hxoand Hy114is only slightly less than Hyo. For the unselected MRAM cells112in the corresponding column line104, this corresponds to shifting the full-select distribution profile to the left inFIG. 6which also improves the tilted array geometry's100write performance in the manner previously described.

It should be noted that the other unselected MRAM cells112in the corresponding row line102receive only the longitudinal field of Hosin α and a transverse field of Hocos α. This level of magnetic field is generally insufficient to unintentionally switch non-selected MRAM cells112. For the unselected cells112in the selected column line104, only the longitudinal field Hois applied and the cells112have a minimal chance of being unintentionally switched.

Hence, from the foregoing, it will be appreciated that the tilted array geometry100can be used to achieve more reliable activation of the MRAM devices of the array without requiring increased current. While the illustrated embodiments have shown the row line102as being tilted, it will be appreciated that the column line104could also have been tilted to achieve the same benefit.

Although the preferred embodiments of the present invention have shown, described and pointed out the fundamental novel features of the invention as applied to those embodiments, it will be understood that various omissions, substitutions and changes in the form of the detail of the device illustrated may be made by those skilled in the art without departing from the spirit of the present invention. Consequently, the scope of the invention should not be limited to the foregoing description but is to be defined by the appended claims.