Buffer circuit

A buffer circuit having an input terminal and an output terminal comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter, a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal, a fifth inverter having an input node and an output node coupled to the output terminal, a sixth inverter having an input node and an output node coupled to the output node of the second inverter, a first resistive element is coupled between the output terminal and the input node of the fifth inverter, and a second resistive element is coupled between the output node of the second inverter and the input node of the sixth inverter.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a buffer circuit, and more particularly, to a buffer circuit that may be used in digital devices or systems.

2. Background of the Invention

Buffers are commonly used in data transmission systems. For example, a signal buffer circuit may be used at an input interface to receive or amplify signals, enhance signal driving capability, and/or reduce signal transition time.

Buffer circuits are usually designed using analog circuits. An example of an analog buffer circuit may include a differential pair with various passive elements, including inductors, capacitors and resistors.FIG. 1Ashows an analog buffer circuit100A for Pseudo Emitter Coupled Logic (PECL). The PECL buffer100A ofFIG. 1Ahas input terminals102and112, which receive separate PECL signals that are complementary to each other. The input terminal102is connected to the gate of an NMOS transistor106, which is coupled to a PMOS transistor104having its gate coupled to ground. The input terminal112is connected to the gate of an NMOS transistor116, which is coupled to a PMOS transistor114having its gate coupled to ground. The PMOS transistors104and114have their sources connected to a power supply Vdd(e.g., +4 volts). The drain of the PMOS transistor104is connected to the drain of the NMOS106, and the drain of the PMOS transistor114is connected to the drain of the NMOS transistor116. The sources of the NMOS transistors106and116are connected to the NMOS transistor130which may provide a constant current. The drain of the PMOS transistor104is connected to an output terminal140via an NMOS transistor108which serves as a level shifter. The drain of the PMOS transistor114is connected to an output terminal150via an NMOS transistor118which serves as a level shifter. Similar to the NMOS transistor130, the NMOS transistors132and134serve as a current source to provide constant current sources. The PECL buffer100A constitutes a current switching differential buffer circuit. Such a circuit may also be designed to reduce signal swing and optimize signal differential, thus improving the operating bandwidth and noise tolerance. A feedback circuit to compensate certain parameters, such as bias, bandwidth and gain, may be employed to prevent process drift from affecting product yield.

Although an analog buffer circuit may provide high efficiency in certain applications, such circuit has complicated designs, consumes more power, and requires large circuit areas. Thus, some systems use digital circuits instead to reduce power consumption and circuit area. However, digital circuits may suffer from poor noise tolerance. In addition, when digital circuits operate in high frequency, the resulting switching noise may decrease the system efficiency.

FIG. 1Bshows a digital buffer disclosed in U.S. Pat. No. 6,483,347. The buffer circuit100B ofFIG. 1Bmay include eight inverters arranged as illustrated. The inverters12and22form a differential inverter pair. The inverters40and50constitute self bias circuit. The inverters60and70form a common mode noise-rejection circuit.

BRIEF SUMMARY OF THE INVENTION

One example consistent with the invention provides a buffer circuit having an input terminal and an output terminal, which comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter, a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal, a fifth inverter having an input node and an output node coupled to the output terminal, a six inverter having an input node and an output node coupled to the output node of the second inverter, a first resistive element is coupled between the output terminal and the input node of the fifth inverter, and a second resistive element is coupled between the output node of the second inverter and the input node of the sixth inverter.

In another example, a buffer circuit comprises a first inverter having an input node coupled to a first input terminal and an output node coupled to a first output terminal, a second inverter having an input node coupled to a second input terminal and an output node coupled to a second output terminal, a third inverter having an input node coupled to the first output terminal and an output node coupled to the second output terminal, a fourth inverter having an input node coupled to the second output terminal and an output node coupled to the first output terminal, a fifth inverter having an input node and an output node coupled to the first output terminal, a sixth inverter having an input node and an output node coupled to the second output terminal, a first resistive element is coupled between the first output terminal and the input node of the fifth inverter and a second resistive element is coupled between the second output terminal and the input node of the sixth inverter.

Another example consistent with the invention provides a method of operating a buffer circuit with at least one buffer interface stage. The method comprises the steps of providing input signals to a differential pair, generating amplified signals from the input signals by the differential pair, filtering noises in the input signals by a noise reduction circuit, and controlling bandwidth distributions of the amplified signals by a bandwidth control circuit.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2illustrates an exemplary circuit diagram of a buffer circuit200in examples consistent with the present invention. The buffer circuit may have a first input terminal202, a second input terminal204, a first output terminal206and a second output terminal208. The first input terminal202may be coupled to an input signal Vin. The first output terminal206may provide an output signal Vout. The second input terminal204may be coupled to a complementary input signal Vin*, in which case the terminal208is used as a complementary output terminal to provide a complementary output signal Vout*. Alternatively, the second input terminal204may be coupled to a reference voltage Vref, in which case the output at the terminal208is usually not used.

Referring toFIG. 2, the buffer circuit200includes a differential pair which receives input signals and generates amplified signals from the input signals. The differential pair may enhance signal driving capability as well as improving signal slew rate. In one example consistent with the present invention, the differential pair may include a first inverter210and a second inverter220. The first inverter210has an input node212coupled to the input terminal202of the buffer circuit200to receive an input signal Vin. The first inverter210has an output node214coupled to the output terminal206of the buffer circuit200to provide an output signal Vout. Similarly, a second inverter220has an input node222and an output node224. The input node222of the second inverter220is coupled to the terminal204of the buffer circuit200. The output node224of the second inverter220is coupled to the second output terminal208if a complementary input signal Vin* applies to the terminal204, or to the first output terminal206if a reference voltage Vrefapplies to the terminal204.

Referring toFIG. 2, the buffer circuit200also includes a noise reduction circuit coupled to the differential pair to filter noises in the input signals. The noise reduction circuit may include a third inverter230and a fourth inverter240. The third inverter230has an input node232and an output node234. The input node232of the third inverter230is coupled to the output node214of the first inverter210. The output node234of the third inverter230is coupled to the output node224of the second inverter220. Similarly, a fourth inverter240has an input node242and an output node244. The input node242of the fourth inverter240is coupled to the output node224of the second inverter220while the output node244is coupled to the output node214of the first inverter210. In the noise reduction circuit, the positive output signal Voutis applied to the inverter230which in turn provides the negative output signal Vout*. In addition, the negative output signal Vout* is applied to the inverter240which in turn provides the positive output signal Vout. As a result, hysteresis phenomena occur in the buffer circuit200. In this regard, the noise reduction circuit having the inverters230and240provides a differential mode voltage offset at the input terminals202and204. Thus, the differential voltage between the input signals Vinand Vin* (or Vref) must overcome the voltage offset in order to change the state of the buffer circuit200, thereby providing good common mode rejection and reducing the input common mode noise.

Referring toFIG. 2again, the buffer circuit200further includes a bandwidth control circuit coupled to the differential pair and the noise reduction circuit. The bandwidth control circuit may operate for controlling bandwidth distributions of the amplified signals. In one example consistent with the present invention, the bandwidth control circuit of the buffer circuit200may include a fifth inverter250and a sixth inverter260each having its input node and its output node respectively coupled to the two ends of a resistive element. For example, the input node252of the fifth inverter250is coupled to one of the two terminals of a transmission gate270. The other terminal of the transmission gate270and the output node254of the fifth inverter250are both coupled to the output node214of the first inverter210. Similarly, the input node262is coupled to one of the two terminals of a transmission gate280. The other terminal of the transmission gate280and the output node264of the sixth inverter260are both coupled to the output node224of the second inverter220. Depending on the design and/or the application of the buffer circuit200, different resistive elements may be used to be coupled with the inventers250and260. Examples of the resistive elements may include transmission gates, MOS transistors, resistors, etc.

FIG. 3illustrates an exemplary circuitry of an inverter having its two terminals coupled to a resistive element, such as inverter260and transmission gate280. Referring toFIG. 3, the inverter260may include a PMOS transistor265with its source coupled to a supply voltage Vcc, its gate serving as the input node262coupled to one of the terminals of the transmission gate280, and its drain serving as the output node264to coupled to the other terminal of the transmission gate280and the output node224of the second inverter220. The inverter260may also include an NMOS transistor267having its source coupled to ground, its drain coupled to the drain of the PMOS transistor265, and its gate coupled to the gate of the PMOS transistor265. The transmission gates270and280may be a switch device, which in one example may include a parallel combination of an NMOS transistor281and a PMOS transistor283as shown atFIG. 3. The gate of the NMOS transistor281may be coupled to the power supply Vccand the gate of the PMOS transistor283may be coupled to ground. The source of the NMOS transistor281is connected to the drain of the PMOS transistor283as well as the output node264of the inverter260. The drain of the NMOS transistor281is connected to the source of the PMOS transistor283as well as the input node262of the inverter260. Note that the inverter260may be any presently known or hereinafter developed inverters, and the transmission gates270and280may be replaced by any types of resistive elements, such as MOS transistors and resistors.

In one example, the bandwidth control circuit having inverters250and260and the transmission gates270and280may establish common mode level and/or increase signal bandwidth.FIG. 4Ashows an equivalent circuit of an exemplary circuit with the inverter260and the transmission gate280. In one example, the transmission gate280constitutes a resistor with resistance value Rtgcoupled between the gate and drain terminals of the PMOS transistor265. The same resistor with resistance value Rtgalso coupled between the gate and drain terminals of the NMOS transistor267.FIG. 4Bis a chart comparing output resistance of a self bias circuit ofFIG. 1Bwith the bandwidth control circuit of a buffer circuit ofFIG. 2. With reference toFIG. 4B,410shows output resistance of a self bias circuit including only an inverter (as shown atFIG. 1B) without a transmission gate or resistive element coupled to the inverter. Since an inverter functions as a diode with flat frequency response, the output resistance of such a self bias circuit remains at the level of 1/gm throughout change of frequency.420shows output resistance of a circuit ofFIG. 3with a transmission gate or resistive element. When the buffer circuit200operates in low frequency430, the output resistance may remain 1/gm. When the buffer circuit200operates in high frequency450, the output resistance may be equal to the resistance value (Rtg) of the transmission gate. That is, for the circuit ofFIG. 3, when the resistance value of the transmission gates is over 1/gm, the output resistance becomes larger with the increase of frequency from low to high. The transmission gates may serve as inductance load when the operating frequency falls in440. The generated inductance load may offset the dominant pole of the circuit200. As a result, the signal bandwidth may be increased.FIG. 4Cis a chart comparing bandwidth of a buffer circuit ofFIG. 1Bwith that of a buffer circuit ofFIG. 2. 460shows the gain margin of the buffer circuit ofFIG. 1Bwhere the self bias circuit includes only an inverter.470shows the gain margin of the buffer circuit ofFIG. 2where the bandwidth control circuit includes an invert and a transmission gate. As illustrated inFIG. 4C, the bandwidth of the buffer circuit ofFIG. 2is increased comparing to that of the buffer circuit ofFIG. 1B.

The inverters210,220,230,240,250and260may be any presently known or hereinafter developed inverters, including inverting amplifiers and the inverters shown inFIGS. 5A-E.FIG. 5Ashows an exemplary inverter510that includes a PMOS transistor512with its source coupled to a supply voltage Vcc, a gate serving as an input node to receive an input signal IN, and a drain serving as an output node to provide an output signal OUT. The inverter510also includes an NMOS transistor514having a source coupled to ground, a drain coupled to the drain of the PMOS transistor512, and a gate coupled to the gate of the PMOS transistor512. When the input signal IN is high, the NMOS transistor514is turned on to connect the output node to ground, thereby making the output signal OUT low. When the input signal IN is low, the PMOS transistor512is turned on to connect the output mode to Vcc, thereby making the output signal OUT high.

FIG. 5Bshows another exemplary inverter520that includes a PMOS transistor522with its source coupled to a supply voltage Vcc, a gate coupled to a reference voltage Vref, and a drain serving as the output node to provide an output signal OUT. The magnitude of the reference voltage is set to a level to keep the PMOS transistor522always in an on condition. The inverter520also includes an NMOS transistor524having a source coupled to ground, a drain coupled to the drain of the PMOS transistor522, and a gate serving as an input node to receive an input signal IN. When the input signal IN is high, the NMOS transistor524is turned on to connect the output node to ground despite the PMOS transistor522being on. Thus, the output signal OUT is low. When the input signal IN is low, the NMOS transistor524is turned off, thereby allowing the output node to connect to Vccvia the PMOS transistor522and making the output signal OUT high.

In another exemplary inverter530shown atFIG. 5C, a PMOS transistor532has its source coupled to a supply voltage Vcc, a gate serving as an input node to receive an input signal IN, and a drain serving as the output node to provide an output signal OUT. The inverter530also includes an NMOS transistor534having a source coupled to ground, a drain coupled to the drain of the PMOS transistor532, and a gate coupled to a reference voltage Vrefwhich is set to a level to keep the NMOS transistor534always in an on condition. When the input signal IN is high, the PMOS transistor532is turned off, thereby allowing the output node to be coupled to ground via the NMOS transistor534. When the input signal IN is low, the PMOS transistor532is turned on, thereby coupling the output node to Vccdespite the NMOS transistor534being on.

FIG. 5Dshows another exemplary inverter540that includes an NMOS transistor542with its source coupled to ground, a gate serving as an input node to receive an input signal IN, and a drain serving as an output node by providing an output signal OUT. The inverter540further includes a resistor544coupled between a supply voltage Vccand the output node of the inverter540. The operation of the inverter540is the same as the inverter520because the resistor544performs the same function as the PMOS transistor522of the inverter520.

FIG. 5Eshows an inverter550that includes a PMOS transistor552with its source coupled to Vcc, a gate serving as input node to receive an input signal IN, and a drain serving as an output node by providing an output signal OUT. The inverter550further includes a resistor554coupled between ground and the output node of the inverter550. The operation of the inverter550is the same as the inverter530because the resistor554performs the same function as the NMOS transistor534of the inverter530.

One example consistent with the invention provides a method of operating a buffer circuit with at least one buffer interface stage. In the exemplary method, the first step may include applying input signals to a differential pair, which in turn generates amplified signals from the input signals in the second step. One example of the differential pair may include inverters210and220as shown atFIG. 2. The noises in the signals are filtered by a noise reduction circuit in a following step. One example of the noise reduction circuit may include inverters230and240at shown atFIG. 2. Another step in the exemplary method may include the step of controlling bandwidth distributions of the amplified signals by a bandwidth control circuit. One example of the bandwidth control circuit may include inverters250and260as well as resistive elements270and280shown atFIG. 2.

An exemplary simulation is conducted by using TSMC 0.18 μm Mixed Signal SALICIDE (1P6M, 1.8V/3.3V), version 1.3 to compare the operating bandwidth of four stages of buffer circuits consistent with the present invention with that of a four-stage buffer amplifier using the buffer circuit ofFIG. 1B. The purpose of this exemplary simulation is to determine the optimal bandwidth by real-time jitter analysis with the input data transmission rate changing from 2 Gbps to 7 Gps. The simulated circuit is a four-stage buffer amplifier as shown atFIG. 6. The four-stage buffer amplifier includes four sets of buffer circuits, S1, S2, S3and S4. The parallel connection numbers corresponding to buffer circuits S1, S2, S3and S4are 1, 2, 4 and 8. In other words, there are two buffer circuits of S1connected in parallel to form buffer circuit S2. Four buffer circuits of S1connected in parallel form buffer circuit S2while eight buffer circuits of S1connected in parallel to form buffer circuit S4. The first test circuit610uses the buffer circuit ofFIG. 2as buffer circuit S1, wherein the parallel connection numbers for inverters210and220are four, the parallel connection numbers for inverters250and260are2and the parallel connection numbers for inverters230and240and transmission gates270and280. The second test circuit610uses buffer circuits of prior artFIG. 1Bas buffer circuit S1. With respect to parameter setting, the transition time is set as 100 ps, the high voltage is set as 1.8 V and the low voltage is 0 V. There is a load circuit connected to the output of the simulated circuit. The configuration of the load circuit is identical to that of the four-stage buffers and the size of it is as twice as the last stage buffer circuit. The size of the transistors is set forth in Table 1 below.

TABLE 1W/LNMOS Transistor1.87μ/0.18μPMOS Transistor0.45μ/0.18μ
In order to simulate non-ideal environment, the simulated circuit also includes equivalent circuit models of packaging620as shown atFIG. 6. The inductance is 2 nH and the capacitance is 1 pF.

FIG. 7shows the results of the exemplary simulation ofFIG. 6. The second row720has diagrams of output signals of a four-stage buffer amplifier using four buffer circuits consistent with the present invention with input data transmission rate at 3 Gbps, 5 Gbps, and 7 Gbps. In comparison, the first row710has diagrams of output signals of a four-stage buffer amplifier the buffer circuit illustratedFIG. 1B. Referring toFIG. 7, diagrams in row720show less real-time jitter than corresponding diagrams in row610.FIG. 8is a line chart comparing the data jitter results810of a four-stage buffer amplifier using the buffer circuit ofFIG. 1Bwith those results820of a four-stage buffer amplifier using a buffer circuit consistent with the present invention. Table 2 below illustrates the data jitter results corresponding to the results shown atFIG. 8.