Low-power cache system and method

The invention provides a cache architecture that selectively powered-up a portion of data array in a pipelined cache architecture. A tag array is first powered-up, but the data array is not powered-up during this time, to determine whether there is a tag hit from the decoded index address comparing to the tag compare data. If there is a tag hit, during a later time, a data array is then powered-up at that time to enable a cache line which corresponds with the tag hit for placing onto a data bus. The power consumed by the tag represents a fraction of the power consumed by the data array. A significant power is conserved during the time in which the tag array is assessing whether a tag hit occurs while the data array is not powered-on at this point.

BACKGROUND INFORMATION

1. Field of the Invention

The invention relates to integrated circuits, and particularly to memory system designs of a cache architecture.

2. Description of Related Art

In a mobile society at the start of a new millennium, a challenge in designing a compact or handheld device is to extend the battery power duration after a charge-up. A cache is an integral part of a computing system but draws a significant amount of system power. A design trend in the past has a dominant focus on finding new ways to increase the speed of a computing system. However, prolonging a battery power has become a primary focus in the design of wireless and mobile devices.

A cache refers to a storage architecture in integrated circuits and software where the most commonly used data is tagged and stored for quick retrieval. A principle usage of a cache is to speed-up processing of information of an application program. A cache tags a piece of data or information using a tagging algorithm. The tag itself and the related data are stored. When a processor seeks to retrieve a piece of data, the same tagging algorithm is applied to generate a tag in which the tag is used to identify whether the data exists in the cache.

FIG. 1is a prior art diagram illustrating a conventional two-way associativity cache architecture10. Cache architecture10includes two one-way of associativities11and12. An address decoder13decodes an index address25for use in a tag array14, and a separate address decoder16is used for a data array17in associativity11. Similarly, an address decoder19is used for a tag array20, and a separate address decoder22is used for a data array23in associativity12. The same index line25is fed feed to all four address decoders13,16,19, and22.

When index line-25is received by cache architecture10, all four address decoders13,16,19, and22are powered-up. A tag look-up and a data look-up are performed simultaneously in tag array14, data array17, tag array20, and data array23. A comparator15compares the tag from tag array14with a tag compare data26in associativity11, while a comparator21compares the tag from tag array20with a tag compare data26in associativity12. One of the two data enables18and24is enabled to generate the output on a data bus27. A shortcoming of this conventional cache architecture10is that a large amount of power is consumed by simultaneous activation of tag array14, tag array20, data array17, and data array23. When additional associativities are stacked over existing associativities, cache architecture draws an even greater amount of power as well as causing potential timing problems.

Accordingly, it is desirable to have a cache architecture that is modular and scalable that consumes low-power.

SUMMARY OF THE INVENTION

The invention provides a cache architecture that selectively powered-up a portion of data array in a pipelined cache architecture. A tag array is first powered-up, but the data array is not powered-up during this time, to determine whether there is a tag hit from the decoded index address comparing to the tag compare data. If there is a tag hit, during a later time, a data array is then powered-up at that time to enable a cache line which corresponds with the tag hit for placing onto a data bus. The power consumed by the tag represents a fraction of the power consumed by the data array. A significant power is conserved during the time in which the tag array is assessing whether a tag hit occurs while the data array is not powered-on at this point.

Advantageously, the cache architecture in the present invention reduces power dissipation, increases modularity, and provides scalable associativity. The complexity of the cache architecture is also simplified by sharing circuits among tag and data arrays. Moreover, additional associativity can be added to the cache architecture without incurring additional costs.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

FIG. 2is a block diagram illustrating a cache pipelined architecture30, with an associativity31, and an associativity32. An address decoder33is shared by a tag array34and data array35in associativity31. Similarly, a common address decoder38is used in associativity32for decoding with a tag array39, and a data array40.

Address decoder33serves to decode the incoming index address43in associativity31. Initially, tag array34is powered-up without supplying power to data array35. A comparator36compares the tag from tag array34with a tag compare data44. Comparator36generates an output signal that enables or disables a data enable37for powering up or not powering up data array35. When data array35is powered-up, and there is a tag hit, data enable37enables output to place data on a data bus45.

Similar type of flow is generated through associativity32. Address decoder38decodes the incoming index address43. Initially, tag array39is powered-up without supplying power to data array40. A comparator41compares the tag from tag array39with a tag compare data44. Comparator41generates an output signal that enables or disables a data enable42on whether to powered-up data array40. When data array40is powered-up, and there is a tag hit, data enable42enables output to place data on a data bus45.

Cache architecture30is designed in a serial or pipelined process with only one address decoder, i.e. address decoder33, rather than two decoders. The serial process allows cache architecture30to powered-up tag array34, while saving power supplied to data array35since data array35is not powered-up until a next phase if there is a tag hit.

Tag array34has an array size which is only a percentage of the array size of data array35. For example, in one design implementation, the array size in tag array34is only 10% relative to the size of data array35, which would be 90%. In terms of power consumption, tag array34draws 10% of power while data array is not powered-on. Therefore, there is a saving of 90% power that is typically required had data array35be powered-on simultaneously with tag array34. The ratio of an array size between tag array34and data array35is merely an illustration. Other desirable ratio or representation of ratio such as fraction, a portion to, relative to, or similar types of fractional relationship can be designated in the design of associativity31.

FIG. 3is a flow diagram illustrating a pipelined cache access method50. Pipelined cache access method50starts51while waiting52for a new clock edge to arrive. If there is no clock edge, pipelined cache method50continues to wait for a new clock edge. After a new clock edge has arrived, pipelined cache method50detects whether a cache power is enabled53. When a cache power is enabled, pipelined cache method50decodes54the index address43. Pipelined cache method50then look-up55tag array34. After a tag in a tag array is found or not found, pipelined cache method50waits until the next clock edge to arrive. Optionally, a tag compare kill signal can be added57for halting the process flow. If the tag compare kill is not enabled, comparator36compares the tag from tag array34with tag compare data44. Pipelined cache method50determines59whether a tag hit occurs. On the one hand, if comparator36generates a tag miss, then the process returns to51. On the other hand, if comparator36determines that there is a tag hit, then pipelined cache method50waits60until the next block edge arrives. When the next clock edge arrives, pipelined cache method50performs61a data look-up in data array35and enables an output on data bus45.

Pipelined cache access method50is generally divided into three phases or cycles. During the first phase, pipelined cache access method50detects52a new clock edge, enables or disables53cache power, decodes address54, and look-up55of tag array34. During the second phase, pipelined cache access method50receives or did not receive57a tag compare kill, compare58of a tag from tag array34with tag compare data44, and detects59a tag hit or a tag miss. During the third phase, pipelined cache access method50performs61a data look-up and enables data onto output data bus45.

Preferably, a wide data is generated from data array35to data enable37in one-way of associativity31. Similarly, a wide data is generated from data array40to data enable42in one- way of associativity32.

FIG. 4is a timing diagram illustrating a pipelined cache access in a cache pipelined architecture. During a T1 phase, cache pipelined architecture30waits to receive a new clock edge from a clock signal70in T1 for decoding an index address or tag address71, and for powering and accessing tag array34. During a T2 phase, cache pipelined architecture30waits to receive a new clock edge in T2 for comparing index address43with a tag in tag array34to determine whether there is tag hit72or tag miss. During a T3 phase, if there is a tag hit, data array35is powered-on in T3 where a cache wordline73is asserted for locating the corresponding cache line in data array40. A cache data out signal74is enabled in data array35for enabling data onto data bus45.

Optionally, the signals depicted in cache architecture30and pipelined cache architecture method50can be implemented in various forms. For example, the triggering of a clock signal and a tag compare kill signal can be designed for assertion singularly or in various combinations in address decoder33, tag array34, data array35, comparator36, or data enable37. Additionally, one of ordinary skilled in the art should recognize that the block diagram arrangement in cache architecture30can be modified in various sequence and combinations to achieve the power-saving in data array35while tag array34is initially powered-up.

The above embodiments are only illustrative of the principles of this invention and are not intended to limit the invention to the particular embodiments described. For example, it is apparent to one of ordinary skilled in the art that a cache architecture can be implemented as a two-way of associativities, a four-way of associativities, or any binary or odd combination of associativities. Furthermore, although the term “phase”, which equals to one-half clock cycle, is used, other types of time units can be implemented, such as self-time, one or more clock cycles, or units less than a phase. The clock70can be triggered on a rising edge, a fallen edge, or in response to another signal. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the appended claims.