Utilization of doped glass on the sidewall of the emitter window in a bipolar transistor structure

A bipolar transistor device architecture and method of manufacture uses doped glass on the sidewall of the emitter window opening to reduce the emitter-base overlap capacitance while at the same time improving the polysilicon plugging effect. The doped glass sidewall also improves dopant loss in the oxide in the case in which an in-situ doped poly emitter is used. By using a doped sidewall glass, the sensitivity of dopant absorption that can potentially occur in un-doped spacers is removed. The proposed technique also provides a simple method for achieving narrow emitter window openings while simultaneously improving doping uniformity compared to implanted poly techniques. The technique also allows a self-aligned base to be performed, thereby allowing tighter spacing between the extrinsic base and the intrinsic base.

FIELD OF THE INVENTION

The present invention relates to semiconductor integrated circuit device structures and, in particular, to utilization of a doped glass on the sidewalls of the emitter window opening of a bipolar transistor structure to improve plugging effects.

DISCUSSION OF THE RELATED ART

Conventional bipolar transistor structures typically utilize an implanted polysilicon emitter or an in-situ doped polysilicon emitter. These bipolar emitter structures often suffer from a plugging effect that limits the uniformity of the dopant implanted in the polysilicon emitter and results in WE dependencies in the electrical parameters, such as beta (current gain), of the bipolar transistor.

The present invention provides a bipolar device architecture that reduces the emitter-base overlap capacitance while at the same time improving the polysilicon plugging effect. Use of doped glass as a solid diffusion source allows for better control of the dopant uniformity compared to implanted poly. The doped glass sidewall also improves dopant loss in the oxide for the case in which an in-situ doped poly emitter is used in bipolar technologies. By using a doped sidewall glass in the emitter architecture, such as phosphosilicate glass (PSG) for an NPN emitter or borosilicate glass (BSG) for a PNP emitter, the sensitivity of dopant absorption that can potentially occur in un-doped oxide spacers is removed. The proposed structure also allows a simple method for achieving narrow emitter window openings while simultaneously improving doping uniformity. The structure also allows a self-aligned extrinsic base to be performed, allowing tighter spacing between the extrinsic base and the intrinsic base. This technique also allows the total thermal budget to be reduced in advanced very narrow emitter width bipolar transistors, since it does not require significant thermals to drive the dopants out of the doped glass and into the emitter poly, particularly if combined with an implant into the emitter.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1-7illustrate fabrication steps typically utilized in a BiCMOS process flow for SiGe NPN transistors. Those skilled in the art will appreciate that the process steps shown inFIGS. 1-7are only an example of an embodiment of an NPN process in accordance with the concepts of the present invention and are not to be considered as limiting the invention.

Standard processing for a bipolar transistor begins with formation of the epitaxial base with a TEOS/nitride layer deposited on the base.FIG. 1shows a buried oxide layer100formed in a semiconductor substrate, represented by the designation “NPN” inFIG. 1. As stated above, in this embodiment, the semiconductor substrate comprises SiGe. A layer of epitaxial silicon102is formed on the buried oxide layer100. Shallow trench isolation (STI) regions104are formed in the upper surface of the epitaxial layer102with deep trench isolation regions106extending down to the buried oxide layer100to define an isolated epi-layer active region “box” for formation of the NPN bipolar device. As shown inFIG. 1, the isolated epi “box” encloses an N-type buried layer (NBL)108that provides the collector region for the NPN device. Those skilled in the art will appreciate that the dopant profile for the N-type buried layer is chosen to be consistent with a particular device application. The N-type buried layer108includes a collector surface contact region108athat is defined by shallow trench isolation (STI) region110. The conductive intrinsic base region112and extrinsic base region114of the NPN device are defined over the collector region108and STI regions110. A thin layer of silicon dioxide116is formed over the above-described structure and a thin layer if silicon nitride118is formed on the oxide layer116.

As further shown inFIG. 1, an embodiment of a process for forming a bipolar transistor emitter structure in accordance with the concepts of the present invention begins by depositing a thick TEOS layer120and a second silicon nitride layer122. Photoresist (PR)124is then spun on and patterned in accordance with well known photolithographic techniques, resulting in the formation of an NPN emitter mask opening126. The mask opening126is preferably formed have a width consistent with the minimum feature size (CD) that can be achieved with the process module in use. The mask opening126is then used to etch the nitride layer122and the TEOS layer120using well known etch techniques, stopping on the bottom nitride layer118as shown inFIG. 2. The photoresist mask124is then stripped and a layer of doped silicate glass128, e.g., phosphosilicate glass (PSG) in the case of this NPN embodiment of the invention, is deposited as shown inFIG. 3to fill the emitter window opening126and to contact the upper surface of the bottom nitride layer118. The PSG should contain a high phosphorus concentration to act as a solid solubility limited diffusion source, typically on the order of 3-10 wt % phosphorus, preferably about 6 wt % phosphorous. Those skilled in the art will appreciate that the phosphorous concentration may be adjusted to achieve the desired emitter dopant diffusion goals.

As shown inFIG. 4, doped PSG sidewall spacers130are then formed by performing a blanket etch of the PSG layer128, stopping on the top nitride layer122and the bottom nitride layer118. The use of the doped PSG spacers130allows achievement of emitter window openings smaller than the typical critical dimension (CD) control. As mentioned above, the PSG spacers130will serve as a dopant source for the poly emitter, the formation of which is discussed below. In high concentration PSG (>3 wt % phosphorous), the phosphorous is incorporated as P═O bonds or in a pentavalent structure P2O5in SiO2atomic network. The solid state diffusion of phosphorous occurs when the film is heated at a temperature of 900° C. or greater and at which the P═O bonds are disassociated and the phosphorous diffuses out into the emitter poly. Emitter doping levels as high as 1E20 cm3can be achieved, depending upon the time and temperature of the annealing process. The rapid thermal anneal (RTA) normally used in advanced bipolar or BiCMOS processing to activate the implanted dopant atoms can thus act also as a diffusion driver, causing the doping species in the highly doped glass to diffuse out of the glass and into the poly emitter regions. Those skilled in the art will appreciate that optimization of the RTA or spike anneals can be done to provide best uniformity of the emitter dopant profile.

After formation of the PSG spacers130, the emitter window is opened to the upper surface112aof the intrinsic base region112through the use of a blanket etch of nitride layer118and a breakthrough etch of the oxide layer116, as shown inFIG. 5.

After cleaning the silicon surface112aof the intrinsic base112, a layer of emitter polysilicon132is deposited, as shown inFIG. 6.

Next, a photoresist (PR) emitter poly mask134is formed and used to cut the emitter poly132and the TEOS/nitride/oxide stack, as shown inFIG. 7. At this point, the same mask134is used to block the intrinsic base112and the NPN emitter poly132while implanting the exposed extrinsic base regions114.

As discussed above, an annealing step is then performed that causes phosphorous to diffuse from the PSG spacers130into the poly emitter132.

The structure is then completed using a conventional process.

It should be understood that the particular embodiments of the invention described above have been provided by way of example and that other modifications may occur to those skilled in the art without departing from the scope and spirit of the invention as express in the appended claims and their equivalents.