Liquid crystal display device and method of driving the same

A driver circuit for an LCD display includes; a gate line; a data line crossing the gate line; a feed TFT connected to the gate line; a feed control line connected to the feed TFT to switch on the feed TFT; and a feed signal line connected to the feed TFT to supply a feed signal to the gate line.

This application claims the benefit of Korean Patent Application No. 2006-0059402, filed on Jun. 29, 2006, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device including a plurality of auxiliary thin film transistors (TFTs) and a method of driving the LCD device.

2. Discussion of the Related Art

With the advance of the information age, devices for displaying information are actively being developed. In particular, flat panel display (FPD) devices having a thin profile, light weight and low power consumption are actively being developed as substitutes for cathode ray tube (CRT) devices. For example, liquid crystal display (LCD) devices, plasma display panels (PDP), field emission display (FED) devices and electroluminescent display (ELD) devices have been researched and developed as FPD devices. Of these FPD devices, liquid crystal display (LCD) devices are widely used as monitors for notebook computers and desktop computers because of their high resolution, high contrast ratio, color rendering capability and superior performance for displaying moving images.

A liquid crystal display (LCD) device relies on the optical anisotropy and polarizing properties of liquid crystal to produce an image. Due to the optical anisotropy of liquid crystal molecules, refraction of light incident onto a liquid crystal depends on the alignment direction of the liquid crystal molecules. Liquid crystal molecules have directional alignment characteristics resulting from their long, thin shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal.

FIG. 1is a schematic cross-sectional view showing a liquid crystal display device according to the related art, andFIG. 2is a schematic equivalent circuit diagram showing an array substrate for a liquid crystal display device according to the related art. In addition,FIG. 3is a schematic magnified view of a portion “III” ofFIG. 2.FIGS. 1 and 2show an active matrix liquid crystal display (AM-LCD) device having thin film transistors (TFTs) and pixel electrodes arranged in a matrix form.

As illustrated inFIGS. 1,2and3, an LCD device10of the related art includes a first substrate20and a second substrates30referred to as a color filter substrate and an array substrate, respectively. A common electrode24and a pixel electrode32are formed on the first substrate20and the second substrate30, respectively, with the common electrode24facing the pixel electrode32. A liquid crystal layer50is interposed between the first and second substrates20and30.

A black matrix26is formed on the first substrate20and a color filter layer22is formed on the black matrix26and the first substrate20. The common electrode24is formed on the color filter layer22. The color filter layer22may include red, green and blue color filters. The black matrix26disposed between adjacent two color filters to block light not passing through a color filter. A plurality of gate lines “G1” to “Gn” and a plurality of data lines “D1” to “Dm” are formed on the second substrate30with the gate lines and data lines crossing each other to define pixel regions “P.” A thin film transistor (TFT) “T” is connected to a gate line “G1” to “Gn” and a data line “D1” to “Dm,” and the pixel electrode32is connected to the TFT “T.” The TFT “T” and the pixel electrode32are formed in each pixel region “P.”

The common electrode24, the pixel electrode32and the liquid crystal layer50constitute a liquid crystal capacitor “CLC.” In addition, a storage capacitor “CST” in parallel with the liquid crystal capacitor “CLC” is connected to the TFT “T.” First and second polarizing plates28and34are formed on outer surfaces of the first and second substrates20and30, respectively.

A gate driver38and a data driver42are disposed at respective sides of the second substrate. The gate driver38is connected to the plurality of gate lines “G1” to “Gn” and sequentially supplies gate pulses to the plurality of gate lines “G1” to “Gn.” The data driver42is connected to the plurality of data lines “D1” to “Dm” and supplies data pulses to the plurality of data lines “D1” to “Dm.” The gate pulse is an ON voltage turning on the TFT “T” and a data pulse is a liquid crystal driving voltage for changing the alignment of liquid crystal molecules.

The TFT “T” includes a gate electrode, a source electrode and a drain electrode. The gate electrode and the source electrode are connected to the gate line “G1” to “Gn” and the data line “D1” to “Dm,” respectively. The drain electrode is connected to the liquid crystal capacitor “CLC.” The TFT “T” is turned on and off according to the gate pulse and functions as a switch for application of a data pulse to the liquid crystal capacitor “CLC.”

The LCD device10displays images by frames. The gate driver38sequentially supplies the gate pulses to the plurality of gate lines “G1” to “Gn” during each frame. In addition, the data driver42supplies the data pulses corresponding to the gate pulses to the plurality of data lines “D1” to “Dm.” As shown inFIG. 3, when a gate pulse is supplied to the (n−1)thgate line “Gn−1”, for example, the data pulses are supplied concurrently to all of the plurality of data lines “D1” to “Dm”. Accordingly, the first to mthTFTs “T1” to “Tm” connected to the (n−1)thgate line “Gn−1” are turned on and the data pulses are supplied to the liquid crystal capacitors “CLC” of pixel regions “P” through the plurality of data lines “D1” to “Dm.” As a result, the liquid crystal capacitors “CLC” are charged with a voltage and the alignment of the liquid crystal molecules are changed according to the charged voltage. The change in alignment of the liquid crystal molecules causes a change in transmittance of the liquid crystal layer50and the LCD device displays color images by color combination of light transmitted through red, green and blue color filters.

The LCD device10further includes a backlight unit60under the second substrate30. Since the LCD device10is a non-emissive display device, the backlight unit60supplies light to the liquid crystal layer50for generating an image. Even though not shown inFIGS. 1 to 3, a seal pattern is formed at a boundary of the first and second substrates20and30to prevent leakage of the liquid crystal layer50. In addition, a first orientation film is formed between the common electrode24and the liquid crystal layer50and a second orientation film is formed between the pixel electrode32and the liquid crystal layer50to establish an initial orientation of the molecules of the liquid crystal layer50.

During operation of the LCD device10, the gate pulse is transmitted from one end to the other end of each of the gate lines “G1” to “Gn.” Since the gate lines “G1” to “Gn” each has a resistance and a capacitance, the shape of the gate pulse is distorted due to an RC delay as the pulse propagates from end to end along a gate line.

FIGS. 4A and 4Bare schematic graphs showing the shapes of a gate pulse and a data pulse supplied to first and mthpixel regions, respectively, corresponding to an (n−1)thgate line ofFIG. 3. Gate pulses and the data pulses having the shapes shown inFIGS. 4A and 4Bare applied to each of the plurality of gate lines “G1” to “Gn” and data lines “D1” to “Dm,” respectively. The first to mthTFTs “T1” to “Tm” are connected to the (n−1)thgate line “Gn−1.” The first and mthTFT “T1” and “Tm” correspond to first and second ends of the (n−1)thgate line “Gn−1,” respectively.FIG. 4Ashows an initial shape of an (n−1)thgate pulse “G(N−1)” applied to the first TFT “T1” corresponding to the first end of the (n−1)thgate line “Gn−1” andFIG. 4Bshows a final shape of the (n−1)thgate pulse “G(N−1)” applied to the mthTFT “Tm” corresponding the second end of the (n−1)thgate line “Gn−1.”

The (n−1)thdata pulse “D(N−1)” is transmitted to the first to mthTFTs “T1” to “Tm” while the gate pulse is applied to the (n−1)thgate line “Gn−1.” In addition, the (n−2)thdata pulse “D(n−2)” is transmitted to the first to mthTFTs “T1” to “Tm” while the gate pulse is applied to the (n−2)thgate line “Gn−2,” and the nthdata pulse “D(N)” is transmitted to the first to mthTFTs “T1” to “Tm” while the gate pulse is applied to the nthgate line “Gn.”FIG. 4Ashows a shape of the (n−1)thdata pulse “D(N−1)” transmitted to the first TFT “T1” corresponding to the first end of the (n−1)thgate line “Gn−1” andFIG. 4Bshows a shape of the (n−1)thdata pulse “D(N−1)” transmitted to the mthTFT “Tm” corresponding the second end of the (n−1)thgate line “Gn−1.”

The (n−1)thgate pulse “G(N−1)” and the (n−1)thdata pulse “D(N−1)” each have a rising time and a falling time. A voltage of the (n−1)thgate pulse “G(N−1)” and the (n−1)thdata pulse “D(N−1)” increases from an initial value to a final value during the rising time and decreases from the final value to the initial value during the falling time. The voltage of the (n−1)thgate pulse “G(N−1)” and the (n−1)thdata pulse “D(N−1)” is maintained at constant value for a time period between the rising time and the falling time. When the (n−1)thgate pulse “G(N−1)” rises to a voltage greater than a threshold voltage “Vth,” the first to mthTFTs “T1” to “Tm” are turned on and the (n−1)thdata pulse “D(N−1)” is applied to the liquid crystal capacitor “CLC” to charge up the liquid crystal capacitor “CLC.” When the (n−1)thgate pulse “G(N−1)” falls to a voltage smaller than the threshold voltage “Vth,” the first to mthTFTs “T1” to “Tm” are turned off and the (n−1)thdata pulse “D(N−1)” is not applied to the liquid crystal capacitor “CLC.”

As a result, the (n−1)thdata pulse “D(N−1)” charges up the liquid crystal capacitor “CLC” in the first pixel region “PXL1” during a first charging time period “Ta(1)” and charges up the liquid crystal capacitor “CLC” in the mthpixel region “PXLm” during an mthcharging time period “Ta(m).” Further, the first TFT “T1” is turned off after the (n−1)thgate pulse “G(N−1)” falls during a first off time period “Tb(1)” to have the threshold voltage “Vth” and the mthTFT “Tm” is turned off after the (n−1)thgate pulse “G(N−1)” falls during an mthoff time period “Tb(m)” to have the threshold voltage “Vth.”

To prevent a noise signal due to the nthdata pulse “D(N),” the (n−1)thdata pulse “D(N−1)” is maintained a constant value during a predetermined time period after the (n−1)thgate pulse “G(N−1)” begins to fall, and then begins to fall only after the (n−1)thgate pulse “G(N−1)” voltage falls below the threshold voltage of the first to mthTFTs “T1” to “Tm.” The first to mthTFTs “T1” to “Tm” each are in an ON state even after the (n−1)thgate pulse “G(N−1)” begins to fall until the time when the (n−1)thgate pulse “G(N−1)” reaches the threshold voltage “Vth.” A TFT may be in a slight or partial ON state even when the (n−1)thgate pulse “G(N−1)” has a voltage smaller than the threshold voltage “Vth” due to a property of the TFT device. Were the (n−1)thgate pulse “G(N−1)” and the (n−1)thdata pulse “D(N−1)” start to fall simultaneously, the nthdata pulse “D(N)” for the nthgate line “Gn” might be applied to the liquid crystal capacitor “CLC” currently charged up with the (n−1)thdata pulse “D(N−1)” before the first to mthTFTs “T1” to “Tm” connected to the (n−1)thgate line “Gn−1” are turned off. Accordingly, the nthdata pulse “D(N)” may be mixed with the (n−1)thdata pulse “D(N−1)” in the liquid crystal capacitor “CLC” causing a noise signal. In order to prevent the noise signal, the (n−1)thdata pulse “D(N−1)” is maintained at constant voltage for a predetermined time period after the (n−1)thgate pulse “G(N−1)” begins to fall, and only begins to fall after the (n−1)thgate pulse “G(N−1)” voltage falls below the threshold voltage turning off the first to mthTFTs “T1” to “Tm”.

The initial shape of the (n−1)thgate pulse “G(N−1)” inFIG. 4Ais different from the final shape of the (n−1)thgate pulse “G(N−1)” inFIG. 4Bdue to the equivalent resistance and equivalent capacitance of the (n−1)thgate line “Gn−1.” The (n−1)thgate pulse “G(N−1)” applied to the first TFT “T1” is transmitted to the mthTFT “Tm” through the (n−1)thgate line “Gn−1.” The (n−1)thgate line “Gn−1” includes a conductive material having a resistance and a capacitance. The total resistance and capacitance of the (n−1)thgate line “Gn−1” may be represented by an equivalent resistance and an equivalent capacitance, respectively. The equivalent resistance and the equivalent capacitance of the (n−1)thgate line “Gn−1” generate an RC delay applied to the (n−1)thgate pulse “G(N−1)” transmitted through the (n−1)thgate line “Gn−1.” As a result, the (n−1)thgate pulse “G(N−1)” is distorted such that the rise time and the falling time are extended. As the equivalent resistance and the equivalent capacitance increase the RC delay increases. The distortion of the gate pulse shape due to the RC delay causes a deterioration of the display quality of the LCD device.

As described above, to solve the problem of the interference from the nthdata pulse “D(N)” for the nthgate line “Gn,” the (n−1)thdata pulse “D(N−1)” is maintained at constant voltage during a predetermined time period after the (n−1)thgate pulse “G(N−1)” begins to fall, and only begins to fall after the (n−1)thgate pulse “G(N−1)” falls to a voltage smaller than the threshold voltage “Vth”

As shown inFIG. 4B, as the falling time is extended due to the RC delay, the mthoff time period “Tb(m)” must be extended and the mthcharging time period “Ta(m)” is shortened to prevent the noise signal problem due to the nthdata pulse “D(N)” for the nthgate line “Gn.” However, when the mthcharging time period “Ta(m)” is shortened, the time available for charging the liquid crystal capacitor “CLC” with the (n−1)thdata pulse “D(N−1)” is insufficient and the alignment of the liquid crystal molecules is not completely changed to achieve the required transmittance. The insufficient transmittance change results in a non-uniformity of brightness and contrast ratio between right and left portions of the LCD device display, as well as image sticking and flicker. As a result the display quality of the LCD device is reduced.

As a solution for the insufficient charging problem described above, new conductive materials having a relatively low resistance for the gate line have been researched. Additionally, methods using additional circuitry to for gate modulation and employing gate drivers disposed at both ends of the gate lines have been suggested. However, these solutions increase the cost of the LCD device and do not sufficiently address the problems due to the RC delay along the gate line.

SUMMARY OF THE INVENTION

An advantage of the present invention is to provide a liquid crystal display device addressing the problem of falling time extension due to an RC delay and a method of driving the liquid crystal display device.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a driver circuit for an LCD display includes; a gate line; a data line crossing the gate line; a feed TFT connected to the gate line; a feed control line connected to the feed TFT to switch on the feed TFT; and a feed signal line connected to the feed TFT to supply a feed signal to the gate line.

In another aspect of the present invention, a method of driving an LCD display includes: applying a gate pulse to a gate line of the LCD display; and supplying a feed signal pulse synchronized with the gate pulse to the gate line.

In another aspect, an LCD device includes: a gate line and crossing a data line on a first substrate; a second substrate separated from the first substrate by a predetermined distance; a liquid crystal layer disposed between the first and second substrates; a feed TFT connected to the gate line; a feed control line connected to the feed TFT to switch on the feed TFT; and a feed signal line connected to the feed TFT to supply a feed signal to the gate line.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to embodiments of the present invention, an example of which is illustrated in the accompanying drawings. Wherever possible, similar reference numbers will be used to refer to the same or similar parts.

FIG. 5is a schematic equivalent circuit diagram showing a liquid crystal display device according to an embodiment of the present invention.

InFIG. 5, a liquid crystal display (LCD) device includes a display area “AA” in which an image is displayed and a non-display area “NA” provided with a black matrix in which an image. A plurality of gate lines “G1” to “Gn” and a plurality of data lines “D1” to “Dm” are formed in the display area “AA.” The gate lines “G1” to “Gn” cross the data lines “D1” to “Dm” to define a pixel regions “P.” A thin film transistor (TFT) “T” is connected to the gate line “G1” to “Gn” and the data line “D1” to “Dm,” and a liquid crystal capacitor “CLC” and a storage capacitor “CST” in each pixel region “P” are connected to the TFT “T.” Gate pulses, each having a low level voltage “Vg1” (ofFIG. 6) and a high level voltage “Vgh” (ofFIG. 6) are sequentially supplied to the plurality of gate lines “G1” to “Gn.” For example Vg1may be about −5V and Vgh may be about +25V. In addition, data pulses synchronized with the gate pulses are supplied to the plurality of data lines “D1” to “Dm.”

A plurality of feed TFTs “Tf1” to “Tfn” are formed in the non-display area “NA.” The each of the plurality of feed TFTs “Tf1” to “Tfn” are connected to a respective gate line of the plurality of gate lines “G1” to “Gn.” Each gate line has first and second ends, and a gate driver and the feed TFT are connected to the first and second ends of each gate line, respectively. Further, each of the plurality of feed TFTs “Tf1” to “Tfn” are connected to a feed control line “FCL” and a feed signal line “FSL.” Each of the plurality of feed TFTs “Tf1” to “Tfn” has a gate electrode, a source electrode and a drain electrode. The drain electrode of each of the plurality of feed TFTs “Tf1” to “Tfn” is connected a respective one of the plurality of gate lines “G1” to “Gn.” In addition, the gate electrode of each of the plurality of feed TFTs “Tf1” to “Tfn” is connected to the feed control line “FCL” and the source electrode of each of the plurality of feed TFTs “Tf1” to “Tfn” is connected to the feed signal line “FSL.” A feed control signal “Vf-con” is transmitted to the gate electrode through the feed control line “FCL” to turn on and off the plurality of feed TFTs “Tf1” to “Tfn.” A feed signal “Vf” is transmitted to the source electrode through the feed signal line “FSL.” Each of the plurality of feed TFTs “Tf1” to “Tfn” may be formed through the same process as the TFT “T” in the display area “AA” so that the plurality of feed TFTs “Tf1” to “Tfn” can be of the same type as the TFT “T.” For example, the plurality of feed TFTs “Tf1” to “Tfn” and the TFT “T” may have an N (negative) type.

The feed control signal “Vf-con” when supplied to the feed control line “FCL” turns on each of the plurality of feed TFTs “Tf1” to “Tfn.” For example, the feed control signal “Vf-con” may have a voltage within a range of about 20V to about 30V. In addition, the feed signal “Vf” supplied to the feed signal line “FSL” may have a voltage within a range of about −10V to about −5V. The feed signal “Vf” is applied to the plurality of gate lines “G1” to “Gn” through the plurality of feed TFTs “Tf1” to “Tfn” turned on by the feed control signal “Vf-con” during a feed time period. The feed time period may have a range of about 1 μsec to about 3 μsec. The feed control signal “Vf-con” may be at the high level voltage “Vgh” of the gate pulse supplied to the plurality of gate lines “G1” to “Gn”. Alternatively, the feed signal “Vf” may be at the low level voltage “Vg1” of the gate pulse. Since the feed signal “Vf” and the feed control signal “Vf-con” may have voltage levels equal to those of the gate pulse, the feed signal “Vf” and the feed control signal “Vf-con” may be generated by using a gate driver for the gate pulse. Alternatively, a separate feed control circuit independent of the gate driver may be used to generate the feed signal “Vf” and the feed control signal “Vf-con.” For example, a gate output enable signal “GOE” to be transmitted from a timing controller to the gate driver may be amplified using a level shifter in the gate driver and then supplied to the feed control line “FCL” as the feed control signal “Vf-con” in synchrony with an input timing of the gate output enable signal “GOE.”

FIG. 6is a timing diagram showing signals used in a liquid crystal display device according to an embodiment of the present invention.

As illustrated inFIG. 6, the feed signal “Vf” is applied to the plurality of gate lines “G1” to “Gn” such that the feed signal “Vf” is synchronized with a falling timing of the gate pulse “Vg1” to “Vgn” supplied to the plurality of gate lines “G1” to “Gn.” Because the feed signal “Vf” has a negative voltage, the feed signal “Vf” shortens the falling time of the gate pulse “Vg1” to “Vgn” from the high level voltage “Vgh” to the threshold voltage “Vth” for each TFT “T1” to “Tm.”

FIG. 7is a magnified view of a portion “VII” ofFIG. 5, andFIGS. 8A and 8Bare waveform diagrams showing a gate pulse, a data pulse and a feed signal supplied to first and mthpixel regions, respectively, corresponding to an (n)thgate line ofFIG. 7.

Gate pulses and the data pulses shaving the shapes shown inFIGS. 8A and 8Bmay be applied to each of the plurality of gate lines “G1” to “Gn” and data lines “D1” to “Dm,” respectively. The first to mthTFTs “T1” to “Tm” are connected to the (n)thgate line “Gn.” The first and mthTFT “T1” and “Tm” correspond to first and second ends of the (n)thgate line “Gn,” respectively.FIG. 8Ashows a shape of a gate pulse “G(N)” applied to the first TFT “T1” corresponding to the first end of the (n)thgate line “Gn” andFIG. 8Bshows a shape of the gate pulse “G(N)” applied to the mthTFT “Tm” corresponding the second end of the (n)thgate line “Gn.”

In addition, the nthdata pulse “D(N)” is transmitted to the first to mthTFTs “T1” to “Tm” while the gate pulse “G(N)” is applied to the (n)thgate line “Gn.”FIG. 8Ashows a shape of the nthdata pulse “D(N)” transmitted to the first TFT “T1” corresponding to the first end of the (n)thgate line “Gn” andFIG. 8Bshows a shape of the nthdata pulse “D(N)” transmitted to the mthTFT “Tm” corresponding the second end of the (n)thgate line “Gn.” For example, the gate pulse “G(N)” may be supplied to the (n)thgate line “Gn” and the data pulse “D(N)” may be supplied to the plurality of data lines “D1” to “Dm” at the same time.

The gate pulse “G(N)” and the data pulse “D(N)” each have a rising time period and a falling time. A voltage of the gate pulse “G(N)” and the data pulse “D(N)” increases from an initial value to a final value during the rising time and decreases from the final value to the initial value during the falling time. The voltage of the gate pulse “G(N)” and the data pulse “D(N)” are each maintained at a constant voltage for a time period between its respective rising time and the falling time. When the gate pulse “G(N)” rises to have a voltage greater than a threshold voltage “Vth,” the first to mthTFTs “T1” to “Tm” are turned on and the data pulse “D(N)” is applied to the liquid crystal capacitor “CLC” to charge up the liquid crystal capacitor “CLC.” When the gate pulse “G(N)” falls to have a voltage smaller than the threshold voltage “Vth,” the first to mthTFTs “T1” to “Tm” are turned off and the data pulse “D(N)” ceases to be applied to the liquid crystal capacitor “CLC”.

As a result, the data pulse “D(N)” charges up the liquid crystal capacitor “CLC” in the first pixel region “PXL1” during a first charging time period “Ta(1)” and charges up the liquid crystal capacitor “CLC” in the mthpixel region “PXLm” during an mthcharging time period “Ta(m).” Further, the first TFT “T1” is turned off after the gate pulse “G(N)” falls during a first off time period “Tb(1)” to have the threshold voltage “Vth” and the mthTFT “Tm” is turned off after the gate pulse “G(N)” falls during an mthoff time period “Tb(m)” to have the threshold voltage “Vth.”

The feed signal “Vf” is applied to the (n)thgate line “Gn” by turning on the (n)thfeed TFT “Tfn” in synchrony with the feed control signal “Vf-con” corresponding to the falling timing of the gate pulse “G(N).” Since the feed signal “Vf” has the low level voltage “Vg1” of about −10V to about −5V, the (n)thgate line “Gn” may be rapidly charged to the low level voltage “Vg1.” In the mthpixel region “PXLm,” the mthoff time period “Tb(m)” is shortened and the mthcharging time period “Ta(m)” is extended compared with those of the related art. As a result, the time available for charging the liquid crystal capacitor “CLC” with the data pulse “D(N)” is increased so that the liquid crystal molecules can be sufficiently re-aligned and the required transmittance can be obtained.

In addition, the first charging time period “Ta(1)” and the mthcharging time period “Ta(m)” are substantially equal in duration to each other, and the first off time period “Tb(1)” and the mthoff time period “Tb(m)” are substantially equal in duration to each other. Therefore, the first pixel region “PXL1” and the mthpixel region “PXLm” may have substantially the same available time period for charging the data pulse “D(N)” regardless of the RC delay, and display quality deteriorating effects such as image sticking and flicker may be reduced or eliminated.

FIG. 9is a schematic block diagram showing a liquid crystal display device according to an embodiment of the present invention.

InFIG. 9, a liquid crystal display (LCD) device includes a liquid crystal panel110, a timing controller120, a gate driver130, a data driver140, a source voltage supply150and a feed control circuit160.

A plurality of gate lines “G1” to “Gn” and a plurality of data lines “D1” to “Dm” are formed in the liquid crystal panel110and are driven respectively by the gate driver130and the data driver140. The plurality of gate lines “G1” to “Gn” and the plurality of data lines “D1” to “Dm” cross each other to define a plurality of pixel regions. For each pixel region, a thin film transistor (TFT) “T” is connected to the corresponding gate line and the corresponding data line, and a liquid crystal capacitor (not shown) connected to the TFT “T” is formed in each pixel region. The liquid crystal capacitor is turned on/off by the TFT “T,” thereby modulating the transmittance of an incident light and displaying images. A plurality of feed TFTs “Tf1” to “Tfn” are connected to ends of the plurality of gate lines “G1” to “Gn,” respectively.

RGB data and timing sync signals, such as clock signals, horizontal sync signals, vertical sync signals and data enable signals, are input from an external driving system (not shown), such as a personal computer, to the timing controller120through an interface (not shown). The timing controller120generates gate control signals for the gate driver130, including a plurality of gate integrated circuits (ICs), and data control signals for the data driver140, including a plurality of data ICs. Moreover, the timing controller120outputs data signals to the data driver140. The timing controller120further generates a gate output enable signal “GOE” so that the gate driver130can output a gate signal.

The gate driver130controls the ON/OFF operation of the thin film transistors (TFTs) in the liquid crystal panel110according to the gate control signals from the timing controller120. The gate driver130sequentially enables the plurality of gate lines “G1” to “Gn.” Accordingly, the data signals from the data driver140are supplied to pixel electrodes in the pixel regions of the liquid crystal panel110through the TFTs “T.” The source voltage supply150supplies source voltages to elements of the LCD device and a common voltage to the liquid crystal panel110. The source voltage supply150may generate a low level voltage “Vg1” that can be used as the feed signal “Vf” (ofFIG. 7).

The data driver140determines reference voltages for the data signals according to the data control signals and outputs the determined reference voltages to the liquid crystal panel110to control a rotation angle of liquid crystal molecules.

The feed control circuit160may include a feed signal generator and a feed control signal generator generating a feed signal “Vf” (ofFIG. 7) and a feed control signal “Vf-con” (ofFIG. 7), respectively. The feed signal “Vf” (ofFIG. 7) is supplied to the plurality of feed TFTs “Tf1” to “Tfn” through a feed signal line “FSL” and the feed control signal “Vf-con” (ofFIG. 7) is supplied to the plurality of feed TFTs “Tf1” to “Tfn” through a feed control line “FCL.” For example, the feed control circuit160may include a level shifter. The gate output enable (GOE) signal of the timing controller120may be supplied to the level shifter of the feed control circuit160and amplified to be used as the feed control signal “Vf-con” (ofFIG. 7).

In the liquid crystal display device and the method of driving the liquid crystal display device according to the present invention, display quality deteriorating effects such as flicker, non-uniform brightness, and vertical cross-talk and image sticking resulting from distortion of the gate pulse due to the RC delay of the gate line may be reduced or eliminated, thereby providing images of high display quality.