Semiconductor device and method of controlling warpage in reconstituted wafer

A semiconductor device has a substrate with a plurality of active semiconductor die disposed over a first portion of the substrate and a plurality of non-functional semiconductor die disposed over a second portion of the substrate while leaving a predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die. The predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die includes a central area, checkerboard pattern, linear, or diagonal area of the substrate. The substrate can be a circular shape or rectangular shape. An encapsulant is deposited over the active semiconductor die, non-functional semiconductor die, and substrate. An interconnect structure is formed over the semiconductor die. The absence of active semiconductor die and non-functional semiconductor die from the predetermined areas of the substrate reduces bending stress in that area of the substrate.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of controlling warpage in a reconstituted wafer by die depopulation to leave open areas of a temporary substrate devoid of semiconductor die.

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, and various signal processing circuits.

Semiconductor devices exploit the electrical properties of semiconductor materials. The structure of semiconductor material allows the material's electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support, electrical interconnect, and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

In manufacture of a semiconductor package, a plurality of semiconductor die can be mounted to a temporary substrate. An encapsulant is deposited over the semiconductor die and substrate. The temporary substrate is then removed. The reconstituted wafer is subject to warpage or bending after removal of the substrate due to differences in CTE of the semiconductor die and encapsulant. The warpage of the reconstituted wafer creates defects and handling issues during subsequent manufacturing steps, such as during formation of an interconnect structure over the semiconductor die and encapsulant.

DETAILED DESCRIPTION OF THE DRAWINGS

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

FIG. 1illustrates electronic device50having a chip carrier substrate or PCB52with a plurality of semiconductor packages mounted on a surface of PCB52. Electronic device50can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device50can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device50can be a subcomponent of a larger system. For example, electronic device50can be part of a tablet, cellular phone, digital camera, or other electronic device. Alternatively, electronic device50can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, radio frequency (RF) circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.

For the purpose of illustration, several types of first level packaging, including bond wire package56and flipchip58, are shown on PCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip substrate (BCC)62, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, quad flat package72, embedded wafer level ball grid array (eWLB)74, and wafer level chip scale package (WLCSP)76are shown mounted on PCB52. In one embodiment, eWLB74is a fan-out wafer level package (Fo-WLP) and WLCSP76is a fan-in wafer level package (Fi-WLP). Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device50includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIG. 2ashows a semiconductor wafer120with a base substrate material122, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material for structural support. A plurality of semiconductor die or components124is formed on wafer120separated by a non-active, inter-die wafer area or saw street126as described above. Saw street126provides cutting areas to singulate semiconductor wafer120into individual semiconductor die124. In one embodiment, semiconductor wafer120has a width or diameter of 100-450 millimeters (mm).

FIG. 2bshows a cross-sectional view of a portion of semiconductor wafer120. Each semiconductor die124has a back or non-active surface128and an active surface130containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface130to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die124may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer132is formed over active surface130using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer132can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer132operates as contact pads electrically connected to the circuits on active surface130. Conductive layer132can be formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die124, as shown inFIG. 2b. Alternatively, conductive layer132can be formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row is disposed a second distance from the edge of the die.

Semiconductor wafer120undergoes electrical testing and inspection as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on semiconductor wafer120. Software can be used in the automated optical analysis of semiconductor wafer120. Visual inspection methods may employ equipment such as a scanning electron microscope, high-intensity or ultra-violet light, or metallurgical microscope. Semiconductor wafer120is inspected for structural characteristics including warpage, thickness variation, surface particulates, irregularities, cracks, delamination, and discoloration.

The active and passive components within semiconductor die124undergo testing at the wafer level for electrical performance and circuit function. Each semiconductor die124is tested for functionality and electrical parameters, as shown inFIG. 2c, using a test probe head136including a plurality of probes or test leads138, or other testing device. Probes138are used to make electrical contact with nodes or conductive layer132on each semiconductor die124and provide electrical stimuli to components on active surface130. Semiconductor die124responds to the electrical stimuli, which is measured by computer test system139and compared to an expected response to test functionality of the semiconductor die. The electrical tests may include circuit functionality, lead integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, threshold current, leakage current, and operational parameters specific to the component type. The inspection and electrical testing of semiconductor wafer120enables semiconductor die124that pass to be designated as known good die (KGD) for use in a semiconductor package.

InFIG. 2d, semiconductor wafer120is singulated through saw street126using a saw blade or laser cutting tool141into individual semiconductor die124. The individual semiconductor die124can be inspected and electrically tested for identification of KGD post singulation.

FIGS. 3a-3hillustrate, in relation toFIG. 1, a process of forming a reconstituted wafer with reduced warpage by die depopulation to leave open areas of a temporary substrate devoid of semiconductor die.FIG. 3ashows a cross-sectional view of a portion of a temporary substrate140containing sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. A foil layer142is laminated to substrate140. Foil layer142can be copper or other stiffening material to reduce warpage effects. Alternatively, an interface layer or double-sided tape142is formed over substrate140as a temporary adhesive bonding film, etch-stop layer, or thermal release layer.

Substrate140can be a round or rectangular panel (greater than 300 mm) with capacity for multiple semiconductor die124. Substrate140may have a larger surface area than the surface area of semiconductor wafer120. A larger substrate reduces the manufacturing cost of the semiconductor package as more semiconductor die can be processed on the larger substrate thereby reducing the cost per unit. Semiconductor packaging and processing equipment are designed and configured for the size of the wafer or substrate being processed.

To further reduce manufacturing costs, the size of substrate140is selected independent of the size of semiconductor die124or size of semiconductor wafer120. That is, substrate140has a fixed or standardized size, which can accommodate various size semiconductor die124singulated from one or more semiconductor wafers120. In one embodiment, substrate140is circular with a diameter of 330 mm. In another embodiment, substrate140is rectangular with a width of 560 mm and length of 600 mm. Semiconductor die124may have dimensions of 10 mm by 10 mm, which are placed on the standardized substrate140. Alternatively, semiconductor die124may have dimensions of 20 mm by 20 mm, which are placed on the same standardized substrate140. Accordingly, standardized substrate140can handle any size semiconductor die124, which allows subsequent semiconductor processing equipment to be standardized to a common substrate, i.e., independent of die size or incoming wafer size. Semiconductor packaging equipment can be designed and configured for a standard substrate using a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized substrate140lowers manufacturing costs and capital risk by reducing or eliminating the need for specialized semiconductor processing lines based on die size or incoming wafer size. By selecting a predetermined substrate size to use for any size semiconductor die from all semiconductor wafer, a flexible manufacturing line can be implemented.

InFIG. 3b, semiconductor die124fromFIG. 2dare mounted to substrate140and foil layer142using, for example, a pick and place operation with active surface130oriented toward the substrate.FIG. 3cshows semiconductor die124mounted to foil layer142of substrate140as reconstituted or reconfigured wafer144having a width or diameter of 330 mm.

Reconstituted wafer144can be processed into many types of semiconductor packages, including embedded wafer level ball grid array (eWLB), fan-in wafer level chip scale packages (WLCSP), reconstituted or embedded wafer level chip scale packages (eWLCSP), fan-out WLCSP, flipchip packages, three dimensional (3D) packages, such as package-on-package (PoP), or other semiconductor packages. Reconstituted wafer144is configured according to the specifications of the resulting semiconductor package. In one embodiment, semiconductor die124are placed on substrate140in a high-density arrangement, i.e., 300 micrometers (μm) apart or less, for processing fan-in devices. In another embodiment, semiconductor die124are separated by a distance of 50 μm on substrate140. The distance between semiconductor die124on substrate140is optimized for manufacturing the semiconductor packages at the lowest unit cost. The larger surface area of substrate140accommodates more semiconductor die124and lowers manufacturing cost as more semiconductor die124are processed per reconstituted wafer144. The number of semiconductor die124mounted to substrate140can be greater than the number of semiconductor die124singulated from semiconductor wafer120. Substrate140and reconstituted wafer144provide the flexibility to manufacture many different types of semiconductor packages using different size semiconductor die124from different sized semiconductor wafers120.

InFIG. 3d, an encapsulant or molding compound146is deposited over semiconductor die124and substrate140using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. In particular, encapsulant146covers the four side surfaces and back surface128of semiconductor die124with a thickness of 470 μm. Encapsulant146can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant146is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. Encapsulant146also protects semiconductor die124from degradation due to exposure to light.

InFIG. 3e, substrate140and foil layer142are removed by chemical etching, mechanical peeling, chemical mechanical planarization (CMP), mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping to expose active surface130and conductive layer132. Back surface128of semiconductor die124, as well as the sides of the semiconductor die, remain covered by encapsulant146as a protective panel to increase yield, particularly when surface mounting the semiconductor die.

Reconstituted wafer144is subject to warpage or bending, as shown inFIG. 3f, after removal of substrate140and foil layer142due to differences in CTE of semiconductor die124and encapsulant146, as well as chemical cure shrinkage effect of the encapsulant. For a circular substrate140with a diameter of 305 mm, reconstituted wafer144may exhibit a warpage or bend of −2.0 mm.

Having noted the warpage issue,FIG. 5areturns to the state of reconstituted wafer144prior to removal of substrate140and foil layer142. In particular,FIG. 5ashows a plan view of circular reconstituted wafer144with semiconductor die124mounted to foil layer142and substrate140and covered by encapsulant146, i.e., consistent withFIG. 3d. Substrate140has sufficient size to accommodate multiple semiconductor die124arranged in columns and rows across the substrate.

A conventional layout of substrate140would suggest that a maximum number of semiconductor die124should be placed on substrate140, i.e., all available substrate space should be utilized. The layout of semiconductor die should use all available space of the substrate for maximum throughput of die per substrate. However, to reduce the warpage of reconstituted wafer144, certain areas of substrate140are depopulated of semiconductor die124to leave open space, i.e., no semiconductor die124are mounted to predetermined and selected areas of substrate140. In the case ofFIG. 5a, no semiconductor die124is mounted to central area147of substrate140. In other words, whereas central area147could have accommodated at least one semiconductor die124, the central area of substrate140is devoid of the potential semiconductor die124.FIG. 5bshows a cross-sectional view of reconstituted wafer144taken along line segment5b-5bofFIG. 5awith no semiconductor die124mounted to central area147of substrate140.

In another embodiment,FIG. 6ashows a plan view of circular reconstituted wafer144prior to removal of substrate140with semiconductor die124mounted to foil layer142and substrate140and covered by encapsulant146. To reduce the warpage of reconstituted wafer144after removal of substrate140, central area148is depopulated of semiconductor die124to leave open space, i.e., no semiconductor die124are mounted to central area148of substrate140. Whereas central area148could have accommodated multiple semiconductor die124in one or more partial rows and columns of available space, the central area of substrate140is devoid of those potential semiconductor die124. In particular, area148that is devoid of semiconductor die124has a “+” shape, as shown inFIG. 6a.FIG. 6bshows a cross-sectional view of reconstituted wafer144taken along line segment6b-6bofFIG. 6awith no semiconductor die124mounted in central area148of substrate140.

In another embodiment,FIG. 7ashows a plan view of circular reconstituted wafer144prior to removal of substrate140with semiconductor die124mounted to foil layer142and substrate140and covered by encapsulant146. To reduce the warpage of reconstituted wafer144after removal of substrate140, areas150is depopulated of semiconductor die124to leave open space, i.e., no semiconductor die124are mounted to areas150of substrate140. Whereas areas150could have accommodated multiple semiconductor die124in one or more partial rows and columns of available space, areas150of substrate140are devoid of those potential semiconductor die124. In particular, areas150that are devoid of semiconductor die124include a central region of substrate140and interstitial locations within the rows and columns of semiconductor die124, as shown inFIG. 7a. For example, the leftmost column of semiconductor die124in substrate140has no open locations. The second leftmost column of semiconductor die124in substrate140has one open interstitial location between the upper two semiconductor die124and the lower two semiconductor die124. The third leftmost column of semiconductor die124in substrate140has two open interstitial locations. The center column of semiconductor die124in substrate140has three open interstitial locations alternating between semiconductor die124. The rightmost column of semiconductor die124in substrate140has no open locations. The second rightmost column of semiconductor die124in substrate140has one open interstitial location between the upper two semiconductor die124and the lower two semiconductor die124. The third rightmost column of semiconductor die124in substrate140has two open interstitial locations.FIG. 7bshows a cross-sectional view of reconstituted wafer144taken along line segment7b-7bofFIG. 7awith no semiconductor die124mounted in areas150of substrate140.FIG. 7cshows a cross-sectional view of reconstituted wafer144taken along line segment7c-7cofFIG. 7awith no semiconductor die124mounted in areas150of substrate140.

The absence of semiconductor die124from selected areas147-148or150of substrate140reduces bending stress in that area of the substrate. By leaving selected areas147-148or150of substrate140devoid of semiconductor die124, the warping effect of any mismatch between the CTE of semiconductor die124and the CTE of encapsulant146on reconstituted wafer144after removal of substrate140is reduced. In the case of circular substrate140, depopulating semiconductor die124from central areas147-148or areas150of substrate140has a significant effect on out-of-plane deformation. Without semiconductor die124in central areas147-148or areas150, CTE mismatch and modulus are reduced as the deflection point is shifted away from the center of the substrate. Any warpage at peripheral regions of substrate140should dominate after removal of the substrate. Retaining semiconductor die124around a perimeter of substrate140helps maintain structural rigidity for the ease of handling. Alternatively, non-functional (dummy) die or other stiffening support components are disposed around a perimeter of substrate140for structural rigidity and ease of handling.

The number and location of areas147-148or150of substrate140absent semiconductor die124is a function of the size and shape of the substrate. For circular substrate140with a diameter of 305 mm and given five to ten semiconductor die124absent from a “+” shape area148, the post substrate removal warpage is reduced to about −1.4 mm in a 14×14 eWLB package. The reduction in warpage increases yield through subsequent manufacturing processes, e.g., formation of the interconnect structure ofFIG. 3g, without significant loss of overall throughput, even given the fact there are fewer semiconductor die124per substrate140. The yield loss due to the absence of some semiconductor die124from substrate140is mitigated in part by the lower failure rate of the semiconductor die during formation of the interconnect structure in subsequent manufacturing processes.

In addition, the absence of semiconductor die124from central areas147-148or areas150reduces stiffness of reconstituted wafer144. Depending on the device structure, some reconstituted wafers exhibit an abrupt change of warpage, for example, directly from −2.0 mm to +2.0 mm. By selectively removing semiconductor die124from central areas147-148or areas150, reconstituted wafer144relaxes and the warpage can be adjusted to the acceptable range.

FIG. 8shows a plan view of rectangular reconstituted wafer144prior to removal of substrate140with semiconductor die124mounted to foil layer142and substrate140and covered by encapsulant146. To reduce the warpage of reconstituted wafer144after removal of substrate140, areas152is depopulated of semiconductor die124to leave open space, i.e., no semiconductor die124are mounted to areas152of substrate140. Whereas areas152could have accommodated multiple semiconductor die124in one or more partial rows and columns of available space, areas152of substrate140are devoid of those potential semiconductor die124. In particular, areas152that are devoid of semiconductor die124include a central region of substrate140and interstitial locations within the rows and columns of semiconductor die124, as shown inFIG. 8. The leftmost column of semiconductor die124in substrate140has no open locations. The second leftmost column of semiconductor die124in substrate140has two open interstitial locations. The third leftmost column of semiconductor die124in substrate140has one open interstitial location. The center column of semiconductor die124in substrate140has three open and concurrent interstitial locations. The rightmost column of semiconductor die124in substrate140has no open locations. The second rightmost column of semiconductor die124in substrate140has two open interstitial locations. The third rightmost column of semiconductor die124in substrate140has one open interstitial location.

FIG. 9shows a plan view of another embodiment of rectangular reconstituted wafer144prior to removal of substrate140with semiconductor die124mounted to foil layer142and substrate140and covered by encapsulant146. To reduce the warpage of reconstituted wafer144after removal of substrate140, areas154is depopulated of semiconductor die124to leave open space, i.e., no semiconductor die124are mounted to areas154of substrate140. Whereas areas154could have accommodated multiple semiconductor die124in one or more partial rows and columns of available space, areas154of substrate140are devoid of those potential semiconductor die124. In particular, areas154that are devoid of semiconductor die124include a central region of substrate140and interstitial locations within the rows and columns of semiconductor die124, as shown inFIG. 9. The leftmost column of semiconductor die124in substrate140has no open locations. The second leftmost column of semiconductor die124in substrate140has two open interstitial locations. The third leftmost column of semiconductor die124in substrate140has two open interstitial locations. The center column of semiconductor die124in substrate140has one open interstitial location. The rightmost column of semiconductor die124in substrate140has no open locations. The second rightmost column of semiconductor die124in substrate140has two open interstitial locations. The third rightmost column of semiconductor die124in substrate140has two open interstitial locations.

FIG. 10shows a plan view of another embodiment of rectangular reconstituted wafer144prior to removal of substrate140with semiconductor die124mounted to foil layer142and substrate140and covered by encapsulant146. To reduce the warpage of reconstituted wafer144after removal of substrate140, areas156is depopulated of semiconductor die124to leave open space, i.e., no semiconductor die124are mounted to areas156of substrate140. Whereas areas156could have accommodated multiple semiconductor die124in one or more partial rows and columns of available space, areas156of substrate140are devoid of those potential semiconductor die124. In particular, areas156that are devoid of semiconductor die124include a central region of substrate140and interstitial locations within the rows and columns of semiconductor die124, as shown inFIG. 10.

FIG. 11shows a plan view of another embodiment of rectangular reconstituted wafer144prior to removal of substrate140with semiconductor die124mounted to foil layer142and substrate140and covered by encapsulant146. To reduce the warpage of reconstituted wafer144after removal of substrate140, areas158is depopulated of semiconductor die124to leave open space, i.e., no semiconductor die124are mounted to areas158of substrate140. Whereas areas158could have accommodated multiple semiconductor die124in one or more partial rows and columns of available space, areas158of substrate140are devoid of those potential semiconductor die124. In particular, areas158that are devoid of semiconductor die124include a central region of substrate140and interstitial locations within the rows and columns of semiconductor die124, as shown inFIG. 11.

FIG. 12ashows a plan view of circular reconstituted wafer144with die attach area200on substrate140. Active semiconductor die124and non-functional dummy semiconductor die202are mounted to foil layer142and substrate140in die attach area200. Active semiconductor die124and dummy semiconductor die202are covered by encapsulant146, i.e., consistent withFIG. 3d. Substrate140has sufficient size to accommodate multiple semiconductor die124and dummy semiconductor die202arranged in columns and rows across the substrate. In particular, active semiconductor die124are mounted to die attach area200ain an interior region of substrate140. The interior die attach areas200acontain clusters of multiple active semiconductor die124, e.g., four or more active semiconductor die124per cluster. Active semiconductor die124and/or dummy semiconductor die202are also mounted to die attach area200baround a perimeter of substrate140. The perimeter die attach areas200bis a ring of active semiconductor die124and/or dummy semiconductor die202, e.g., one or more active semiconductor die124disposed across a width of the ring. Dummy semiconductor die202and/or dummy semiconductor die202are disposed in die attach area200clocated between die attach areas200a-200b. Alternatively, active semiconductor die124are disposed in die attach areas200b.

To reduce the warpage of reconstituted wafer144, certain areas of substrate140are depopulated of semiconductor die124and dummy semiconductor die202to leave open space206shown as solid black areas, i.e., no semiconductor die are disposed in predetermined and selected areas206of substrate140. In the case ofFIG. 12a, no semiconductor die124or dummy semiconductor die202are disposed in central area206of substrate140. In other words, whereas central area206could have accommodated one or more semiconductor die124or dummy semiconductor die202, central area206of substrate140is devoid of the potential semiconductor die. Central area206that is devoid of semiconductor die124or dummy semiconductor die202includes a “+” shape, e.g., four solid black locations on each side around one central solid black location.FIG. 12bshows a focused view of area206in solid black devoid of semiconductor die124and202, and die attach areas200aand200cwith active semiconductor die124and dummy semiconductor die202.FIG. 12cshows a focused view of die attach areas200band200cwith active semiconductor die124and dummy semiconductor die202.

FIG. 13ashows a plan view of circular reconstituted wafer144with die attach area210on substrate140. Active semiconductor die124and non-functional dummy semiconductor die212are mounted to foil layer142and substrate140in die attach area210. Active semiconductor die124and dummy semiconductor die212are covered by encapsulant146, i.e., consistent withFIG. 3d. Substrate140has sufficient size to accommodate multiple semiconductor die124and dummy semiconductor die212arranged in columns and rows across the substrate. In particular, active semiconductor die124are mounted to die attach area210ain an interior region of substrate140. The interior die attach areas210acontain clusters of multiple active semiconductor die124, e.g., four or more active semiconductor die124per cluster. Active semiconductor die124and/or dummy semiconductor die212are also mounted to die attach area210baround a perimeter of substrate140. The perimeter die attach areas210bis a ring of active semiconductor die124and/or dummy semiconductor die212, e.g., one or more active semiconductor die124and/or dummy semiconductor die212disposed across a width of the ring. Dummy semiconductor die212are disposed in die attach area210clocated between die attach areas210a-210b. Alternatively, active semiconductor die124are disposed in die attach areas210b.

To reduce the warpage of reconstituted wafer144, certain areas of substrate140are depopulated of semiconductor die124and dummy semiconductor die212to leave open space216shown as solid black areas, i.e., no semiconductor die are disposed in predetermined and selected areas216of substrate140. In the case ofFIG. 13a, no semiconductor die124or dummy semiconductor die212are disposed in area216of substrate140. In other words, whereas area216could have accommodated one or more semiconductor die124or dummy semiconductor die212, area216of substrate140is devoid of the potential semiconductor die. The area216that is devoid of semiconductor die124or dummy semiconductor die212includes a checkerboard pattern shown in solid black with semiconductor die124or dummy semiconductor die212disposed within the checkerboard pattern.FIG. 13bshows a focused view of area216in solid black devoid of semiconductor die124and212and with semiconductor die124or dummy semiconductor die212disposed within the checkerboard pattern, and die attach areas210aand210cwith active semiconductor die124and dummy semiconductor die212.

FIG. 14shows a plan view of circular reconstituted wafer144with die attach area220on substrate140. Active semiconductor die124and non-functional dummy semiconductor die222are mounted to foil layer142and substrate140in die attach area220. Active semiconductor die124and dummy semiconductor die222are covered by encapsulant146, i.e., consistent withFIG. 3d. Substrate140has sufficient size to accommodate multiple semiconductor die124and dummy semiconductor die222arranged in columns and rows across the substrate. In particular, active semiconductor die124are mounted to die attach area220ain an interior region of substrate140. The interior die attach areas220acontain clusters of multiple active semiconductor die124, e.g., four or more active semiconductor die124per cluster. Active semiconductor die124and/or dummy semiconductor die222are also mounted to die attach area220baround a perimeter of substrate140. The perimeter die attach areas220bis a ring of active semiconductor die124and/or dummy semiconductor die222, e.g., one or more active semiconductor die124and/or dummy semiconductor die222disposed across a width of the ring. Dummy semiconductor die222are disposed in die attach area220clocated between die attach areas220a-220b. Alternatively, active semiconductor die124are disposed in die attach areas220b.

To reduce the warpage of reconstituted wafer144, certain areas of substrate140are depopulated of semiconductor die124and dummy semiconductor die222to leave open space226shown as solid black areas, i.e., no semiconductor die are disposed in predetermined and selected areas226of substrate140. In the case ofFIG. 14, no semiconductor die124or dummy semiconductor die222are disposed in area226of substrate140. In other words, whereas area226could have accommodated one or more semiconductor die124or dummy semiconductor die222, area226of substrate140is devoid of the potential semiconductor die. The area226that is devoid of semiconductor die124or dummy semiconductor die222includes a checkerboard pattern226ain solid black with semiconductor die124or dummy semiconductor die222disposed within the checkerboard pattern and diagonal area226bin solid black extending from the checkerboard pattern across substrate140to die attach area220b.

FIG. 15ashows a plan view of circular reconstituted wafer144with die attach area230on substrate140. Active semiconductor die124and non-functional dummy semiconductor die232are mounted to foil layer142and substrate140in die attach area230. Active semiconductor die124and dummy semiconductor die232are covered by encapsulant146, i.e., consistent withFIG. 3d. Substrate140has sufficient size to accommodate multiple semiconductor die124and dummy semiconductor die232arranged in columns and rows across the substrate. In particular, active semiconductor die124are mounted to die attach area230ain an interior region of substrate140. The interior die attach areas230acontain clusters of multiple active semiconductor die124, e.g., four or more active semiconductor die124per cluster. Active semiconductor die124and/or dummy semiconductor die232are also mounted to die attach area230baround a perimeter of substrate140. The perimeter die attach areas230bis a ring of active semiconductor die124and/or dummy semiconductor die232, e.g., one or more active semiconductor die124and/or dummy semiconductor die232disposed across a width of the ring. Dummy semiconductor die232are disposed in die attach area230clocated between die attach areas230a-230b. Alternatively, active semiconductor die124are disposed in die attach areas230b.

To reduce the warpage of reconstituted wafer144, certain areas of substrate140are depopulated of semiconductor die124and dummy semiconductor die232to leave open space236shown as solid black areas, i.e., no semiconductor die are disposed in predetermined and selected areas236of substrate140. In the case ofFIG. 15a, no semiconductor die124or dummy semiconductor die232are disposed in area236of substrate140. In other words, whereas area236could have accommodated one or more semiconductor die124or dummy semiconductor die232, area236of substrate140is devoid of the potential semiconductor die. The area236that is devoid of semiconductor die124or dummy semiconductor die232includes a central area236aand diagonal area236bin solid black. Diagonal area236bextends from the central area236adiagonally across substrate140to die attach area230b.FIG. 15bshows a focused view of central area236aand a portion of diagonal area236bin solid black devoid of semiconductor die124and232, and die attach areas230aand230cwith active semiconductor die124and dummy semiconductor die232.

FIG. 16shows a plan view of circular reconstituted wafer144with die attach area240on substrate140. Active semiconductor die124and non-functional dummy semiconductor die are mounted to foil layer142and substrate140in die attach area240, similar toFIG. 15b. Active semiconductor die124and dummy semiconductor die are covered by encapsulant146, i.e., consistent withFIG. 3d. Substrate140has sufficient size to accommodate multiple semiconductor die124and dummy semiconductor die arranged in columns and rows across the substrate. In particular, active semiconductor die124are mounted to die attach area240ain an interior region of substrate140. The interior die attach areas240acontain clusters of multiple active semiconductor die124, e.g., four or more active semiconductor die124per cluster. Active semiconductor die124and/or dummy semiconductor die are also mounted to die attach area240baround a perimeter of substrate140. The perimeter die attach areas240bis a ring of active semiconductor die124and/or dummy semiconductor die, e.g., one or more active semiconductor die124and/or dummy semiconductor die disposed across a width of the ring. The dummy semiconductor die are disposed in die attach area240clocated between die attach areas240a-240b. Alternatively, active semiconductor die124are disposed in die attach areas240b.

To reduce the warpage of reconstituted wafer144, certain areas of substrate140are depopulated of semiconductor die124and dummy semiconductor die to leave open space246shown as solid black areas, i.e., no semiconductor die are disposed in predetermined and selected areas246of substrate140. In the case ofFIG. 16, no semiconductor die124or dummy semiconductor die are disposed in area246of substrate140. In other words, whereas area246could have accommodated one or more semiconductor die124or dummy semiconductor die, area246of substrate140is devoid of the potential semiconductor die. The area246that is devoid of semiconductor die124or dummy semiconductor die includes a central area246aand diagonal area246bin solid black extending from the central area across substrate140.

FIG. 17shows a plan view of circular reconstituted wafer144with die attach area250on substrate140. Active semiconductor die124and non-functional dummy semiconductor die are mounted to foil layer142and substrate140in die attach area250, similar toFIG. 15b. Active semiconductor die124and dummy semiconductor die are covered by encapsulant146, i.e., consistent withFIG. 3d. Substrate140has sufficient size to accommodate multiple semiconductor die124and dummy semiconductor die arranged in columns and rows across the substrate. In particular, active semiconductor die124are mounted to die attach area250ain an interior region of substrate140. The interior die attach areas250acontain clusters of multiple active semiconductor die124, e.g., four or more active semiconductor die124per cluster. Active semiconductor die124and/or dummy semiconductor die are also mounted to die attach area250baround a perimeter of substrate140. The perimeter die attach areas250bis a ring of active semiconductor die124and/or dummy semiconductor die, e.g., one or more active semiconductor die124and/or dummy semiconductor die disposed across a width of the ring. The dummy semiconductor die are disposed in die attach area250clocated between die attach areas250a-250b. Alternatively, active semiconductor die124are disposed in die attach areas250b.

To reduce the warpage of reconstituted wafer144, certain areas of substrate140are depopulated of semiconductor die124and dummy semiconductor die to leave open space256shown as solid black areas, i.e., no semiconductor die are disposed in predetermined and selected areas256of substrate140. In the case ofFIG. 17, no semiconductor die124or dummy semiconductor die are disposed in area256of substrate140. In other words, whereas area256could have accommodated one or more semiconductor die124or dummy semiconductor die, area256of substrate140is devoid of the potential semiconductor die. The area256that is devoid of semiconductor die124or dummy semiconductor die includes a central area256aand diagonal area256bin solid black extending across substrate140.

FIG. 18shows a plan view of circular reconstituted wafer144with die attach area260on substrate140. Active semiconductor die124and non-functional dummy semiconductor die are mounted to foil layer142and substrate140in die attach area260. Active semiconductor die124and dummy semiconductor die are covered by encapsulant146, i.e., consistent withFIG. 3d. Substrate140has sufficient size to accommodate multiple semiconductor die124and dummy semiconductor die arranged in columns and rows across the substrate. In particular, active semiconductor die124are mounted to die attach area260ain an interior region of substrate140. The interior die attach areas260acontain clusters of multiple active semiconductor die124, e.g., four or more active semiconductor die124per cluster. Active semiconductor die124and/or dummy semiconductor die are also mounted to die attach area260baround a perimeter of substrate140. The perimeter die attach areas260bis a ring of active semiconductor die124and/or dummy semiconductor die, e.g., one or more active semiconductor die124and/or dummy semiconductor die disposed across a width of the ring. The dummy semiconductor die are disposed in die attach area260clocated between die attach areas260a-260b. Alternatively, active semiconductor die124are disposed in die attach areas260b.

To reduce the warpage of reconstituted wafer144, certain areas of substrate140are depopulated of semiconductor die124and dummy semiconductor die to leave open space266shown as solid black areas, i.e., no semiconductor die are disposed in predetermined and selected areas266of substrate140. In the case ofFIG. 18, no semiconductor die124or dummy semiconductor die are disposed in area266of substrate140. In other words, whereas area266could have accommodated one or more semiconductor die124or dummy semiconductor die, area266of substrate140is devoid of the potential semiconductor die. The area266that is devoid of semiconductor die124or dummy semiconductor die includes a central area266aand linear or diagonal areas266bin solid black extending across substrate140.

FIG. 19shows a plan view of circular reconstituted wafer144with die attach area270on substrate140. Active semiconductor die124and non-functional dummy semiconductor die are mounted to foil layer142and substrate140in die attach area270. Active semiconductor die124and dummy semiconductor die are covered by encapsulant146, i.e., consistent withFIG. 3d. Substrate140has sufficient size to accommodate multiple semiconductor die124and dummy semiconductor die arranged in columns and rows across the substrate. In particular, active semiconductor die124are mounted to die attach area270ain an interior region of substrate140. The interior die attach areas270acontain clusters of multiple active semiconductor die124, e.g., four or more active semiconductor die124per cluster. Active semiconductor die124and/or dummy semiconductor die are also mounted to die attach area270baround a perimeter of substrate140. The perimeter die attach areas270bis a ring of active semiconductor die124and/or dummy semiconductor die, e.g., one or more active semiconductor die124disposed across a width of the ring. The dummy semiconductor die and/or dummy semiconductor die are disposed in die attach area270clocated between die attach areas270a-270b. Alternatively, active semiconductor die124are disposed in die attach areas270b.

To reduce the warpage of reconstituted wafer144, certain areas of substrate140are depopulated of semiconductor die124and dummy semiconductor die to leave open space276shown as solid black areas, i.e., no semiconductor die are disposed in predetermined and selected areas of substrate140. In the case ofFIG. 19, no semiconductor die124or dummy semiconductor die are disposed in area276of substrate140. In other words, whereas area276could have accommodated one or more semiconductor die124or dummy semiconductor die, area276of substrate140is devoid of the potential semiconductor die. The area276that is devoid of semiconductor die124or dummy semiconductor die includes a central area276aand multiple linear or diagonal areas276bextending across substrate140to die attach area270b.

The absence of semiconductor die124from selected areas152-158,206,216,226,236,246,256,266, and276of substrate140inFIGS. 8-19reduces bending stress in that area of the substrate. By leaving selected areas152-158,206,216,226,236,246,256,266, and276of substrate140devoid of semiconductor die124, the warping effect of any mismatch between the CTE of semiconductor die124and the CTE of encapsulant146on reconstituted wafer144after removal of substrate140is reduced. In the case of a rectangular substrate140, depopulating semiconductor die124from areas152-158,206,216,226,236,246,256,266, and276of substrate140has a significant effect on out-of-plane deformation. Without semiconductor die124in areas152-158,206,216,226,236,246,256,266, and276, CTE mismatch and modulus are reduced as the deflection point is shifted away from the center of the substrate. Any warpage at peripheral regions of substrate140should dominate after removal of the substrate. Retaining semiconductor die124around a perimeter of substrate140helps maintain structural rigidity for the ease of process handling.

The reduction in warpage increases yield through subsequent manufacturing processes, e.g., formation of the interconnect structure ofFIG. 3g, without significant loss of overall throughput, even given the fact there are fewer semiconductor die124per substrate140. The yield loss due to the absence of some semiconductor die124from substrate140is mitigated in part by the lower failure rate of the semiconductor die during formation of the interconnect structure in subsequent manufacturing processes.

In addition, the absence of semiconductor die124from areas152-158,206,216,226,236,246,256,266, and276reduces stiffness of reconstituted wafer144. Depending on the device structure, some reconstituted wafers exhibit an abrupt change of warpage, for example, directly from −2.0 mm to +2.0 mm. By selectively removing semiconductor die124from areas152-158,206,216,226,236,246,256,266, and276, reconstituted wafer144relaxes and the warpage can be adjusted to the acceptable range.

Returning toFIG. 3gand again after removal of substrate140, a build-up interconnect structure280is formed over semiconductor die124and encapsulant146. Build-up interconnect structure280includes an electrically conductive layer or redistribution layer (RDL)282formed using a patterning and metal deposition process such as sputtering, electrolytic plating, or electroless plating. Conductive layer282can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. One portion of conductive layer282is electrically connected to conductive layer132. Other portions of conductive layer282can be electrically common or electrically isolated depending on the design and function of semiconductor die124.

An insulating or passivation layer284is formed around and between conductive layers282using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer284contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties. A portion of insulating layer284is removed by an etching process or laser direction ablation (LDA) to expose conductive layer282.

An electrically conductive bump material is deposited over conductive layer282using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer282using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps286. In some applications, bumps286are reflowed a second time to improve electrical contact to conductive layer282. In one embodiment, bumps286are formed over an under bump metallization (UBM) layer. Bumps286can also be compression bonded or thermocompression bonded to conductive layer282. Bumps286represent one type of interconnect structure that can be formed over conductive layer282. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

InFIG. 3h, semiconductor die124are singulated through encapsulant146with saw blade or laser cutting tool288into individual eWLB290.FIG. 4shows eWLB290after singulation. Semiconductor die124is electrically connected to conductive layer282and bumps286for external interconnect. The eWLB290may undergo electrical testing before or after singulation. The absence of semiconductor die124from selected areas of substrate140reduces bending stress in that area of the substrate. By leaving selected areas of substrate140devoid of semiconductor die124, the warping effect of any mismatch between the CTE of semiconductor die124and the CTE of encapsulant146on reconstituted wafer144after removal of substrate140is reduced. The reduction in warpage increases yield through subsequent manufacturing processes using standard semiconductor processing tools without significant loss of overall throughput, even given the fact there are fewer semiconductor die124per substrate140.