Detection of abnormality subsequent to power activation trigger or power stop command

An information processing apparatus includes a main controller which issues a control command and a sub-controller which operates in accordance with the control command. The sub-controller includes a detection unit which detects an abnormality of the information processing apparatus, and a display processing unit which displays information on a display unit in accordance with the control command from the main controller when the detection unit detects no abnormality and displays the information on the display unit without the control command when the detection unit detects an abnormality.

FIELD OF THE INVENTION

The present invention relates to an information processing apparatus and, more particularly, to an information processing apparatus with reduced power consumption such as a mobile phone, PDA (personal digital assistant), digital camera, printer with a display screen, or the like.

BACKGROUND OF THE INVENTION

In recent years, mobile information processing apparatuses such as a mobile phone, PDA (personal digital assistant), digital camera, and the like have come into widespread use. Also, a mobile printer which can operate on a battery has prevailed.

Since these mobile information processing apparatuses continuously operate on a battery, a reduction in power consumption is a significant design factor.

Along with an increase in integration degree of semiconductors, more and more circuits are packaged in a semiconductor chip. The price of a semiconductor chip increases with an increase in the number of I/O pins of the chip. It costs a large sum to manufacture a semiconductor chip including a key input circuit and a display processing circuit both of which require a large number of I/O pins.

For this reason, there has conventionally been proposed the following apparatus. In the apparatus, a sub-CPU comprises a key input circuit and a display processing circuit both of which require a large number of I/O pins, and a main CPU operating on a high-speed clock performs processes which need to be performed at high speed. In a standby state, the main CPU is inactivated, and the sub-CPU processes key inputs and performs display processing.

A main CPU is an LSI which employs a microprocessor or DSP (digital signal processor) and executes main functions of an information processing apparatus, i.e., image processing, communication processing, and the like. Examples of the main CPU include one in which gate arrays constitute an image processing circuit. On the other hand, a sub-CPU is an LSI which operates on a low-speed clock and performs display processing and key input processing that need not be performed at high speed.

To control the state of a main CPU by a sub-CPU, there is proposed a facsimile apparatus using a sub-CPU which receives an instruction for shifting to an energy-efficient mode to interrupt power supply to a main CPU. This apparatus forcibly resumes power supply to the main CPU by detecting any abnormality in a watchdog timer or the like in the sub-CPU (e.g., see Japanese Patent Laid-Open No. 2000-232540).

Also, as an apparatus using a sub-CPU, there is proposed an information processing apparatus in which a sub-CPU performs control operation processing in accordance with input commands, and a main CPU performs data processing (e.g., see Japanese Patent Laid-Open No. 4-309110).

Additionally, there is proposed a facsimile in which a main CPU monitors the operation output signal with a predetermined period from the sub-CPU, detects any abnormality in a sub-CPU from the period of the operation output signal, and turns off the driving power source of the sub-CPU (e.g., see Japanese Patent Laid-Open No. 3-230666).

Assume that in an information device using a plurality of control unit such as a CPU, an abnormality occurs in a main CPU or power supply unit. Since the power supply amount of the power supply unit is larger than the power supply amount for a sub-CPU, the abnormality may lead to a serious accident such as ignition or smoking. Accordingly, any abnormality must be detected, and the user must be warned of the abnormality.

In Japanese Patent Laid-Open No. 2000-232540, if a malfunction is detected in the sub-CPU, the main CPU is forced to operate, and power supply is forcibly resumed. Japanese Patent Laid-Open No. 2000-232540 does not consider a case wherein an abnormality occurs in the main CPU or a power supply unit.

In Japanese Patent Laid-Open No. 4-309110, the sub-CPU does not control the power supply unit, and no abnormality is detected in the information processing apparatus. Thus, Japanese Patent Laid-Open No. 4-309110 does not solve the above-mentioned problems.

In Japanese Patent Laid-Open No. 3-230666, any abnormality in the sub-CPU is detected from its operation signal. The sub-CPU does not control a power supply unit, and no abnormality is detected in the entire information processing apparatus.

Therefore, the above-mentioned conventional techniques do not solve the above-mentioned problems.

SUMMARY OF THE INVENTION

As means for solving the above-mentioned problems, according to the present invention, there is provided an information processing apparatus comprising a main controller which issues a control command and a sub-controller which operates in accordance with the control command, wherein the sub-controller includes detection means for detecting an abnormality of the information processing apparatus, and display processing means for displaying information on a display unit in accordance with the control command from the main controller when the detection means detects no abnormality, and displaying the information on the display unit independently of the control command when the detection means detects an abnormality.

According to the present invention, the foregoing object is attained by providing a method of controlling an information processing apparatus comprising a main controller which issues a control command and a sub-controller which operates in accordance with the control command,

wherein the sub-controller performs

a detection step of detecting an abnormality of the information processing apparatus, and

a display processing step of displaying information on a display unit in accordance with the control command from the main controller when no abnormality is detected in the detection step, and displaying the information on the display unit without the control command, when an abnormality is detected in the detection step.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 1is a block diagram of a printer which can operate on a battery according to the first embodiment.

Referring toFIG. 1, a main CPU1comprises control circuits with a large number of gates and is driven at a high frequency by a high-speed clock circuit3. The control circuits incorporated in the main CPU1include a microcontroller which sequentially executes microinstructions, a gate circuit which performs image processing at high speed, a timer which counts time, a flash memory which stores the microinstructions, a RAM which stores data, and the like.

The flash memory, RAM, or the like may be formed as an external chip and may be connected through an external data bus.

The main CPU1converts image data inputted from a communication connector4into print data at high speed while being driven by the high-speed clock3. After that, the main CPU1controls a print station unit2to print the converted print data.

The main CPU1, in which the large-scale control circuits are driven by the high-speed clock circuit3, consumes a large current. Under the circumstances, in this embodiment, when image processing or printing ends, power supply to a VDD terminal (power supply voltage VDD)24is stopped under the control of a sub-CPU5(to be described later). This aims at minimizing current consumption in the main CPU1.

The print station unit2comprises a mechanism including a motor and carriage, an ink tank, an ink jet head for discharging ink, and the like. The print station unit2is controlled by the main CPU1to drive the mechanism and ink jet head, thereby printing an image.

The high-speed clock circuit3is an oscillator which generates a high frequency of several ten to several hundred MHz. The high-speed clock circuit3generates the fundamental frequency for the main CPU1and supplies the frequency to the main CPU1.

The communication connector4is a connector for obtaining image data from a personal computer (PC) or digital camera (not shown) serving as a host machine. In this embodiment, image data is obtained using a communication unit in compliance with the USB standard, which is a serial communications standard. However, image data may be obtained in compliance with a communications standard for a LAN (local area network), Bluetooth, a communications standard for a wireless LAN, or the like. Alternatively, image data may be obtained through a connector from a CF card or SD card (either of which is a registered trademark) having a semiconductor memory and serving as a communications partner.

InFIG. 5, a flag display unit30includes an INDEX-P indicator which illuminates when an index print setting is selected, a DPOF indicator which illuminates in printing using designation information in compliance with the DPOF standard, a Number indicator which illuminates when the number of image data is input using an input unit7, a Copy indicator which illuminates when the number of copies to be printed of image data is input using the input unit7, and a Battery indicator which blinks when the voltage of a battery decreases.

An 8-digit 7-segment display unit31displays the number or the number of copies of input image data. As will be described later, the 7-segment display unit31displays error messages as shown inFIGS. 4A to 4D. Although the flag display unit and 7-segment display unit are adopted in this embodiment, a dot-matrix display unit or color liquid crystal display may be employed instead.

Referring back toFIG. 1, a sub-CPU5receives display commands from the main CPU1through an SCLK signal11and SDATA signal12serving as serial data communication lines. The sub-CPU5analyzes a display command by internal control circuits and causes the display unit6to display the result. When a power ON key or any other key disposed on the input unit7is operated, a key code corresponding to the pressed key is generated and is sent to the main CPU1using the SDATA signal12.

When the sub-CPU5receives a power OFF command from the main CPU1, it controls a PCON signal14serving as a power supply control signal by the internal control circuits. Opening a switch circuit23stops power supply to the VDD terminal24of the main CPU1. This process is one of the features of this embodiment, and its detailed description will be given with reference to the processing flowchart inFIG. 2.

An ACC signal13from the main CPU1is at “H” level while the main CPU1is in operation. When supply of the power supply voltage VDD is stopped, the ACC signal13changes to “L” level.

The sub-CPU5monitors the ACC signal13, thereby performing abnormality detection for a power supply circuit20and the main CPU1. In the event of an abnormality, an error message is generated and displayed. This process is also one of the features of this embodiment, and its detailed description will be given with reference to the processing flowchart inFIG. 2.

A timer15serving as one of the internal circuits of the sub-CPU5is a timing unit for counting time in accordance with the frequency of a timer clock circuit10(to be described later). The timer15is so configured as to overflow when the count reaches a value set at the start of timing.

The sub-CPU5is powered by a backup battery8and can operate even when the power supply voltage VDD is inactivated.

A frequency of several MHz which is lower than that of the high-speed clock circuit3for the main CPU1is generated by a low-speed clock circuit9and is supplied to the sub-CPU5. The sub-CPU5performs display processing, key input processing, power supply control processing, and the like in accordance with the frequency of the low-speed clock circuit.

A timer clock circuit10operates at several ten KHz. The timer clock circuit10is used as a timing clock for the timer15. When the printer according to this embodiment is in the OFF state, the low-speed clock circuit9is stopped, and the sub-CPU5is operated by supplying timer clocks of an extremely low frequency. This aims at reducing the current consumption of the sub-CPU5.

A power supply circuit20receives power from an AC adaptor21and main battery22and generates the power supply voltage VDD for the main CPU1.

A switch circuit23operates in response to the PCON signal14from the sub-CPU5and controls power supply/power interruption.

Although the switch circuit23is depicted as a switch inFIG. 1, it is configured using a transistor, FET, and the like.FIG. 1shows only the power supply voltage VDD as the output of the power supply circuit20. However, the power supply circuit20generates a head voltage, motor voltage, and the like.

In this embodiment, power supply from the AC adaptor21and main battery22serving as power sources is directly interrupted. Power supply may be interrupted by inputting a control signal to a circuit such as a DCDC converter which generates the power supply voltage VDD.

FIG. 2shows flowcharts of power supply control processing for the printer according to this embodiment. InFIG. 2, the left flowchart shows the processing flow of the main CPU1while the right one shows the processing flow of the sub-CPU5.

When the printer is in a standby state, the switch circuit23is open, and the power supply voltage VDD is not supplied to the main CPU1. The sub-CPU5operates on the timer clock circuit10. The printer consumes an extremely small current in the standby state.

At this time, if a power ON key of the input unit7which serves as an activation factor (activation trigger) is pressed (YES in step S70), the clock for the sub-CPU5switches from the timer clock circuit10to the low-speed clock circuit9in step S71.

After the timer15is started in step S72, the PCON signal14is set at “H” level in step S73, and the switch circuit23is closed. This activates the power supply circuit20, and the main CPU1is supplied with the power supply voltage VDD (step S50).

In step S51, the main CPU1performs initialization processing. In step S52, the ACC signal is set at “H” level. In step S53, a command indicating that the main CPU1operates normally is sent to the sub-CPU5using the SDATA signal12and SCLK signal11.

If the sub-CPU5receives the command indicating normal operation in step S75before the timer15which has started counting overflows (OVF) in step S74, the flow advances to step S76to perform normal processing.

On the other hand, if an abnormality occurs in the main CPU1, the sub-CPU5cannot receive the command indicating normal operation in step S75, and the timer15which has started counting in step S72overflows in step S74. In this case, the flow advances to step S82to perform abnormality processing.

Examples of a case wherein an abnormality occurs in the main CPU1will be described. More specifically, the examples are a case wherein the power supply circuit20is out of order, a case wherein the wiring from the power supply circuit20to the main CPU1or the wiring of a PCB (print circuit board) is disconnected, and the power supply voltage VDD is not supplied, a case wherein the high-speed clock circuit3is not in operation, a case wherein a failure occurs in the internal processing circuits of the main CPU1, and the like. In these cases, the command indicating normal operation is not sent from the main CPU1in step S53, and an overflow of the timer15is detected in step S75. The flow advances to step S82.

In this embodiment, normal operation of the main CPU1is detected by the sub-CPU on the basis of the command from the main CPU1. However, normal operation may be detected by the ACC signal, which has been set at “H” level in step S52.

The processes from step S54of the flowchart for the main CPU1and the processes from step S76of the flowchart for the sub-CPU5are ones in a normal state.

Image data is received through the communication connector4in step S54. The received image data is temporarily stored in a RAM serving as a storage mean in the main CPU1.

When the main CPU1sends a display command in step S55, the sub-CPU5performs display processing in accordance with the display command in step S76. A display command to be sent from the main CPU1in this embodiment is six-byte long and comprises an instruction field which instructs an indication to illuminate, blink, or shut off, a position designation field for designating the position of the indication, and a data field containing display contents in ASCII codes.

To display a character string “Data” by a display command in step S55, ASCII codes corresponding to the character string “Data” are sent from the main CPU1. Then, the sub-CPU5displays the string. A display command for the character string “Data” is sent in order to notify the user that the printer according to this embodiment is performing image processing.

FIG. 4Ashows an image in which the display unit6displays the character string “Data”. In this embodiment, the display unit6employs a 7-segment display unit as shown inFIG. 4A. A more detailed message may be displayed using a dot-matrix display. Alternatively, an estimated time required to convert image data into print data may be received from the main CPU1, and the sub-CPU5may display the remaining processing time.

In step S56, the image data temporarily stored in the RAM is converted into print data. In step S57, the main CPU1resends a display command. Upon receipt, the sub-CPU5performs display processing in accordance with the display command in step S76.

FIG. 4Bshows an image in which the display unit6displays a character string “Print”. The character string “Print” is displayed to notify the user that the printer according to this embodiment is performing printing.

As described in step S55, in this embodiment, the display unit6employs the 7-segment display unit as shown inFIG. 4B. A more detailed message may be displayed using a dot-matrix display means. Alternatively, an estimated time required to perform printing may be received from the main CPU1, and the sub-CPU5may display the remaining processing time.

In step S58, printing is performed. In step S59, it is determined whether to perform the next print operation. If it is determined that further printing is necessary, the processes in steps S54to S59are repeated. When desired printing ends, the flow advances to step S60. In step S60, an OFF execution command for execute the power OFF is sent to the sub-CPU5using the SDATA signal12and SCLK signal11.

The sub-CPU5receives the OFF execution command and changes the PCON signal14to “L” (step S77). When the PCON signal14changes to “L”, the switch circuit23is opened, and the power supply circuit20is deactivated. The VDD of the main CPU1is stopped, and the main CPU1enters a power OFF state (step S61).

Since the power supply VDD24is not supplied, the ACC signal13serving as an output signal of the main CPU1changes to “L” level. In the normal state, it is detected in step S79of the flowchart for the sub-CPU5that ACC=“L” (step S62).

If ACC=“L” is detected in step S79of the flowchart for the sub-CPU5, the flow advances to step S81. The clock for the sub-CPU5switches from the low-speed clock circuit9to the timer clock circuit10, and the sub-CPU5enters the standby state.

In this embodiment, even when the PCON signal14is changed to “L” due to an abnormality of the power supply circuit20, the processes from S78are performed to detect a case the power supply voltage VDD24is continuously supplied.

In step S78, the timer restarts to count a predetermined period of time, e.g., 30 sec. A determination in step S79whether the timer overflows and a determination in step S80whether ACC=“L” are repeated. In the case of the abnormal state, the ACC does not change to “L”. Then, the timer overflow occurs in step S79, and the flow advances to step S82.

In steps S82and S83, the sub-CPU5performs display processing alone in order to notify the user of the abnormal state.

In step S82, display data indicating abnormal display is generated. In step S83, the generated abnormal display data is sent to the display unit6to be displayed.

FIG. 4Cshows a display image indicating abnormal indication. InFIG. 4C, a character string “Error123” is displayed. The error number 123 notifies the user of what type of an abnormality has occurred. If a manual for the product contains a description of error numbers and countermeasures against the errors, the user can cope with the errors.

As described in steps S55and S57, in this embodiment, the display unit6employs the 7-segment display unit as shown inFIG. 4C. A more detailed message may be displayed using a dot-matrix display. Alternatively, the printer may comprise a buzzer and sound a beep to notify the user that an abnormality has occurred.

The significant point in steps S82and S83will be described. The sub-CPU5in the normal state processes a simple function such as reception and display of a display command. In this embodiment, only the sub-CPU5is activated when the apparatus is in a low power consumption mode. In the event of an abnormality, the sub-CPU5performs unique processing to generate display data, without depending on a display command from the main CPU1.

The first embodiment has been described. As a characteristic feature of this embodiment, as shown inFIG. 2, the abnormal state of the apparatus is detected by detecting the normal command in step S75or detecting the ACC signal in step S80, and display data is generated in step S82to notify the user that an abnormality has occurred. For this reason, a simple circuit arrangement and processing procedure implements detection and display of an abnormality of the apparatus.

In this embodiment, the ACC signal13is output from the main CPU1. To prevent an increase in number of the I/O pins of the main CPU1, the SDATA signal12or SCLK signal11may also be used as the ACC signal13. Alternatively, a motor signal to the print station unit2may also be used as the ACC signal13.

In the block diagram ofFIG. 1, the backup battery8is used as the power supply for the sub-CPU5. If the sub-CPU5is also powered by the AC adapter or main battery, it may be powered by the power supply circuit20.

In this embodiment, abnormal display process is performed and the process ends in step S83ofFIG. 2. The abnormal indication may be eliminated by pressing a key in the input unit7. After elimination of the indication, the clock for the sub-CPU5may switch from the low-speed clock circuit9to the timer clock circuit10.

Second Embodiment

FIG. 3shows a block diagram of a printer according to the second embodiment. Referring toFIG. 3, a description of blocks with the same arrangements as in the first embodiment will be omitted.

InFIG. 3, a bus line100comprises a 16-bit data bus and an address bus.

A memory110is such as an SDRAM which stores intermediate data in image processing by a main CPU1or print data to be output.

A line102is a bus connection between the bus line100and the main CPU1. A line103is a bus connection between the bus line100and the memory110.

A line101is a bus connection between the bus line100and a sub-CPU5. The sub-CPU5receives a display command or power supply stop command from the main CPU1through the bus line100.

Similar to the first embodiment, upon reception of the power supply stop command, the sub-CPU5changes a PCON signal14to “L”, and a power supply circuit20stops power supply to a power supply voltage VDD24of the main CPU1.

An input terminal104is an input terminal for monitoring whether the power supply circuit20has generated the power supply voltage VDD of the main CPU1. In this embodiment, monitoring the input terminal104makes it possible to detect an abnormality in a power supply circuit.

The second embodiment has been described. According to this embodiment, the main CPU1and sub-CPU5are connected to each other by bus lines. By sending commands to the sub-CPU5, the same process as described in the first embodiment can be implemented.

Note that in this embodiment, monitoring the power supply voltage VDD allows detection of the apparatus.

Third Embodiment

FIG. 6is a block diagram of a printer according to the third embodiment.

A description of blocks having the same arrangements as those in the block diagram ofFIG. 1described in the first embodiment will be omitted.

This embodiment illustrates a case wherein a main battery22is a rechargeable battery such as a lithium-ion battery.

A rechargeable battery such as a lithium-ion battery has a problem of overcharge. For this reason, in a charging circuit, the output voltage of a normal battery is detected. If the output voltage reaches a predetermined voltage or more, supply of a charging current stops.

However, if the charging circuit is broken or if an output transistor or FET which supplies a charging current is broken and has shorted, the control cannot be performed. Even if the output voltage reaches the predetermined voltage or more, a charging current is continuously supplied. If this state continues, the temperature of the battery rises extremely, and a serious accident such as smoking, ignition, explosion, or the like may occur at the worst.

This embodiment comprises a circuit which prevents a serious accident under abnormal conditions as described above.

InFIG. 6, the main battery22is supplied with a charging current by a CHG signal204serving as a charging signal from a charging circuit202and is charged.

A HDET signal205is an output signal from a temperature sensor such as a thermister. The line for the HDET signal205is connected to an AD converter201incorporated in a sub-CPU5. If the AD converter201detects that a digitized temperature reaches a predetermined value or more, the sub-CPU5controls a CCON signal206serving as a charging control signal and disconnects a switch circuit203from the output of an AC adaptor21, thereby deactivating the charging circuit202.

With the above-mentioned arrangement, even if an abnormality such as a circuit breakage occurs, a serious accident can be prevented.

FIG. 7shows the processing procedure of the sub-CPU5in abnormality detection according to the third embodiment.

Steps S250to S252are part of a process in which the printer according to this embodiment shifts to a standby state. In step S250, the CCON signal206is changed to H level, the switch203is closed, and the charging circuit202is activated. With this process, when the AC adaptor21is connected, the main battery22is charged.

In step S251, the timer15starts. The timer15is set to overflow every predetermined period of time (e.g., one min). In step S252, the clock for the sub-CPU5switches to the timer clock circuit10, and the entire apparatus is set in the standby state.

Although not described as the processing procedure, the PCON signal14is set at “L”, and the switch circuit23is in an open state in order to suppress the current in the main CPU1. Accordingly, the power supply voltage VDD is not supplied to the main CPU1.

In step S253, it is detected whether the timer15overflows. If the timer15overflows, temperature check is performed in step S254. The AD converter201converts the voltage of the HDET signal205serving as an output signal of the temperature sensor from the analog voltage into a digital value.

AD conversion by the AD converter201at predetermined intervals (every one minute) aims at suppressing the current due to the AD conversion. Although not shown, a process which does not require AD conversion may be added if the AC adaptor21is not connected.

It is determined in step S255whether the digitized temperature is equal to or more than a predetermined value N (e.g., 70° C.). If YES, it is determined that a breakage occurs somewhere in the circuit, and the apparatus is in an abnormal state. The flow advances to step S256.

The processes in steps S256to S258are to be performed if the apparatus is in an abnormal state.

In step S256, the CCON signal206is set at “L”, and the switch203is set in the open state. The charging circuit202is deactivated, and charging of the main battery22is inhibited.

Steps S257and S258are processing steps in which the sub-CPU5performs display processing alone to notify the user of an abnormality.

In step S257, display data indicating abnormal display is generated. In step S258, the generated abnormal display data is sent to the display unit6and is displayed on the display unit6.

FIG. 4Dshows a display image of the abnormal display.FIG. 4Dshows a character string “bat-Err”. A description of the character string “bat-Err” and actions required for this case in the product manual enables the user to take countermeasures against the error.

Similarly to the first embodiment, in this embodiment, the display unit6employs the 7-segment display unit as shown inFIG. 4D. A more detailed message may be displayed using a dot-matrix display means. Alternatively, the printer may comprise a buzzer and sound a beep to notify the user that an abnormality has occurred.

The significant point in steps S257and S258will be described. Even if an abnormality is detected in the charging circuit for the battery, the sub-CPU5performs unique processing to generate display data without depending on display commands from the main CPU1.

The third embodiment has been described. As a characteristic feature of this embodiment, the abnormal state of the charging circuit202is detected by the temperature check in step S254and comparison processing in step S255, and display data is generated to notify the user that an abnormality has occurred. This makes it possible to achieve the object of the present invention. More specifically, this makes it possible to detect and display an abnormality of the apparatus with a simple circuit arrangement and processing procedure.

The above-mentioned first to third embodiments are characterized by a mode of performing display in accordance with a command from the main CPU1, and a mode of performing display under the exclusive control of the charging circuit202without depending on commands from the main CPU1in the event of detection of an abnormality.

It is to be understood by those skilled in the art that the spirit and scope of the present invention are not limited to the specific description and drawings of the invention, and the contents described in the appended claims can be variously modified and changed.

As has been described above, according to the present invention, abnormality detection of the apparatus and warning display to the user can be performed while suppressing the standby current of the apparatus.

The above-mentioned embodiments have illustrated printers which can operate on a battery. The present invention, however, is not limited to this. For example, the present invention can be applied to a device which can operate on a battery and has a display screen such as a mobile phone, PDA (personal digital assistant), digital camera, or the like. An arbitrary combination of some of the first to third embodiments can be implemented in accordance with the purpose and object.

The present invention is not limited to the above embodiments and various changes and modifications can be made within the spirit and scope of the present invention. Therefore, to appraise the public of the scope of the present invention, the following claims are made.

Other Embodiments

In this case, so long as the system or apparatus has the functions of the program, the program may be executed in any form, such as an object code, a program executed by an interpreter, or scrip data supplied to an operating system.