System and method for effectuating the transfer of data blocks including a header block across a clock boundary

A system and method for effectuating the transfer of data blocks including a header block across a clock boundary between a first clock domain and a second clock domain. In one embodiment, a first circuit portion provides the data blocks including the header block to a second circuit portion. Control logic associated with the second circuit portion is operable to process the header block and generate in response to the header block a hint signal which is transferred via a synchronizer at least one data cycle prior to the transfer of the data blocks to a third circuit portion disposed in the second clock domain. A control block associated with the third circuit portion operates responsive to the hint signal to generate data transfer control signals for controlling the third circuit portion in order to control output of the data blocks in a particular ordered grouping.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application discloses subject matter related to the subject matter disclosed in the following commonly owned co-pending patent application: “System and Method for Effectuating the Transfer of Data Blocks Across a Clock Boundary,” U.S. patent application Ser. No. 10/625,365, filed Jul. 23, 2003, in the name(s) of: Richard W. Adkisson and Huai-Ter Victor Chong, which is hereby incorporated by reference.

BACKGROUND

By way of example,FIG. 1depicts a timing sequence100of two clock domains having an N:(N−1) frequency ratio wherein data transfer across the clock boundary between the domains results in an extra data cycle or “dead cycle” in which data cannot be transferred. As is well known, data transfer operations between circuitry of a first clock domain and circuitry of a second clock domain are effectuated by synchronizer circuitry disposed therebetween. Further, the first and second clock domains are operable with clock signals that have a particular cycle ratio. For instance, the circuitry of the first clock domain (“fast clock domain”) may be clocked with a first clock signal (CLK1) that is faster than a second clock signal (CLK2) used for clocking the circuitry of the second clock domain (“slow clock domain”) such that there are N first clock cycles to (N−1) second clock cycles. In one application, core clock circuitry and bus clock circuitry of a computer system may represent the first and second clock domains, respectively, wherein CLK1and CLK2signals correspond to the core clock (CC) and bus clock (BC) signals.

A synchronizer controller circuit (not shown inFIG. 1) is usually provided for controlling the operation of synchronizer circuitry disposed between the two clock domains. Additionally, a control signal such as a SYNC pulse may be generated based on a predetermined temporal relationship between CLK1and CLK2for synchronizing the data transfer operations. For example, the SYNC pulse may be generated when a rising edge of the CLK1signal coincides with a rising edge of the CLK2signal, which commences a data transmit window for the transfer of data blocks, which may include one or more data bits, from one clock domain to the other clock domain.

The timing sequence100ofFIG. 1illustrates an embodiment of CLK1104, CLK2106and SYNC pulse signal108, wherein for every five ticks of CLK1there are four ticks of the slow clock (i.e., CLK2). A cycle count102refers to the numbering of CLK1cycles in a particular data transmit window of the timing sequence100. Data to be transferred from the fast clock domain is clocked at CLK1, that is, 5 data block pulses per window are available.

As alluded to before, the SYNC pulse108is high on coincident rising edges of CLK1and CLK2and the data transfer operations across the clock boundary between the two clock domains are timed with reference to the SYNC pulse. In a normal condition where there is no skew (or, jitter, as it is sometimes referred to) between CLK1and CLK2, the coincident edges occur on the rising edges of the first cycle (cycle0) as shown inFIG. 1. Since there are five CLK1cycles and only four CLK2cycles, CLK1domain circuit portion cannot transmit data during one cycle resulting in what is known as a “dead tick,” as CLK2domain circuit portion does not have a corresponding time slot for receiving it. Typically, the cycle that is least skew tolerant is the one where data is not transmitted and, in the exemplary timing sequence shown inFIG. 1, it is the fourth cycle (i.e., cycle3).

Skew between CLK1and CLK2signals can cause, for example, a variance in the positioning of the SYNC pulse which affects the data transfer operations between CLK1and CLK2domains. In the exemplary 5:4 frequency ratio scenario set forth above, if CLK2leads CLK1by a quarter cycle for instance, then instead of the edges being coincident at the start of cycle0, they will be coincident at the start of cycle1and the dead tick's location may accordingly vary. In similar fashion, if CLK2lags CLK1by a quarter cycle, the edges will be coincident at the start of the last cycle (i.e., cycle4). Regardless of the skew between the clock cycles, however, there will be a cycle where a data block cannot be sent, resulting in data transfer at less than full bandwidth. Furthermore, in channelized data transmission scenarios, where multiplexed data blocks are transmitted from a fast clock domain to a slow clock domain sequentially as contiguous data blocks, the latency introduced by dead cycles presents problems. Additionally, these problems can be particularly limiting where header blocks associated with multiplexed data blocks require excessive processing time.

SUMMARY

A system and method are disclosed that effectuate the transfer of data blocks including a header block across a clock boundary between a first clock domain and a second clock domain. In one embodiment, a first circuit portion provides the data blocks including the header block to a second circuit portion. Control logic associated with the second circuit portion is operable to process the header block and generate in response to the header block a hint signal which is transferred via a synchronizer at least one data cycle prior to the transfer of the data blocks to a third circuit portion disposed in the second clock domain. A control block associated with the third circuit portion operates responsive to the hint signal to generate data transfer control signals for controlling the third circuit portion in order to control output of the data blocks in a particular ordered grouping.

DETAILED DESCRIPTION OF THE DRAWINGS

In the drawings, like or similar elements are designated with identical reference numerals throughout the several views thereof, and the various elements depicted are not necessarily drawn to scale. Referring now toFIG. 2, therein is depicted a system200for effectuating the transfer of data blocks including a header block across a clock boundary between a first clock domain (e.g., a core clock domain) having N fast clock cycles and a second clock domain (e.g., a bus clock domain) having M slow clock cycles such that N/M>1. Received data, e.g., core data generated by circuitry in the first clock domain, is provided on an incoming data path202at full bandwidth for transport to a first circuit portion204that includes a channeled packet interface206. The received data may include a data packet comprising N data pulses or blocks including a header block in a timing cycle window. The header block may provide protocol control information about the data packet and may be positioned at the beginning of a data packet, e.g., H0A0B0C0D0.

In one embodiment, the data blocks are intervaled and each intervaled data block may include one or more bits that are spaced apart by an interval element which may include empty cycles. For example, the data may take the form H0—A0—B0—C0—D0wherein each “_” represents an empty cycle. In one embodiment, the received data may be multiplexed data that includes at least two sets of interleaved data blocks. In this embodiment, the data blocks are positioned in a spaced arrangement. For example, the data may take the form H0H1A0A1B0B1C0C1D0D1if two packets of interleaved data blocks, i.e., data blocks H0A0B0C0D0and data blocks H1A1B1C1D1, are present, or H0H1H2A0A1A2B0B1B2C0C1C2D0D1D2if three packets of interleaved data blocks, i.e., H0A0B0C0D0, H1A1B1C1D1and H2A2B2C2D2, are present. It should be appreciated, however, that the teachings presented herein are equally applicable to intervaled and non-intervaled data blocks.

The first circuit portion204provides the data blocks to a second circuit portion208via data path210. Second circuit portion208includes at least one queue, for example, queues214athrough214n, for transmitting data blocks to a multiplexer (MUX) block216via data paths220athrough220n, respectively. In one embodiment, the queues are first-in-first-out (FIFO) queues. In order to transmit the incoming intervaled data including a header block received via data path210as contiguous data, portions of the intervaled data are temporarily stored. The series of queues214athrough214nprovide temporary storage for the incoming data blocks received from the data path210. The duration of the temporary storage, if required for a particular data block, depends on the total number of data blocks in the received data and the number of dead cycles. In one embodiment, the number of dead cycles equals N-M. Data path218transmits data received from the data path210to the MUX block216without queuing.

The header is stripped or removed from the incoming data packet and forwarded to a control logic block222associated with the second circuit portion208. The control logic block222processes the header block and generates, in response to the header block, a hint signal244which is transferred at least one data cycle prior to the transfer of the data blocks to a third circuit portion240associated with the second clock domain. It should be appreciated that depending on the complexity of the data packet, the processing time of the header will vary. Accordingly, the transmission from the first clock domain and the receipt in the second clock domain of the data blocks contained in the data packet may be affected by the processing of the header.

To minimize the latency associated with header processing and solve associated timing issues, the control logic block222provides the third circuit portion240in the second clock domain with advance notice via the hint signal244which includes protocol control information relative to the processing of the header block. This enables the third circuit portion240and other circuitry in the second clock domain time to prepare for the arrival of the data blocks. For example, depending on the processing time of the header, the data blocks associated with the header may need to be temporarily queued in the second clock domain or immediately forwarded to other circuitry in the second clock domain. Based on the information stored in the header and the number of dead cycles, the control logic block222, which may take the form of a state machine, calculates the number of data blocks in the intervaled data and, accordingly, the length of time to store each data block and the appropriate location for the hint signal.

A synchronizer controller224is in communication with a core-to-bus synchronizer226as illustrated by a data flow line228. The synchronizer controller224provides a series of dead cycle control signals, c2b_valid_ff230and c2b_valid_m_ff[4:1]232, which provide zero to four cycles advance notice of the location or locations of the dead cycles between the first and second clocks. The synchronizer controller224provides its advance knowledge of the position of the dead cycles to the control logic block222so that the second circuit portion208may be controlled to send data to the synchronizer226whereby the sent data may be optimally arranged about the dead cycles, which dead cycles are to be removed by the synchronizer226in operation, resulting in an ordered and contiguous data output to the second clock domain. The control logic222associated with the second circuit portion provides a MUX selection control signal234to the MUX1block216and a series of control signals (control signals238a-238nfor clocking out data blocks stored in the queues214a-214n) so that appropriate data blocks can be selected as MUX output.

Control block242(CLK2domain) associated with the third circuit portion240operates responsive to the hint signal244transferred via the synchronizer226to generate a plurality of CLK2domain control signals in order to anticipate the arrival of data and prepare the hardware of the second clock domain accordingly. One CLK2domain control signal246may be registered using a control register248for generating a MUXSEL2control signal250which controls a MUX2252. The remaining CLK2control signals254a-254dcontrol a SWAP block256, a direct data path258, a queue block260, and a logic0block262so that the MUX2252can output the appropriate sequence of data blocks to an I/O data pad264via data path266in the second clock domain. Depending on the time taken by control logic block222to process the header, different control signals254a-254dare employed. For example, if the processing of the header is delayed, then the control signal254cmay be sent to the queue260in order to buffer the transfer of the data from the synchronizer226into the second clock domain. Alternatively, if the processing of the header is occurring quickly, the control signal254band the data path258may be employed to forward the data directly to the I/O pad264of the second clock domain. Hence, the control block242operates responsive to the hint signal to generate data transfer control signals for controlling the third circuit portion in order to control output of the data blocks in a particular ordered grouping whether the ordered grouping involves temporarily storing the data blocks or providing the data blocks to circuitry in the second clock domain without queuing.

Accordingly, the data blocks received from the channeled packet interface206are transmitted as contiguous data output with one or more interleaved dead cycles from the MUX1block216to the synchronizer226, i.e., a fast-to-slow synchronizer such as a core-to-bus synchronizer, operating under the control of the synchronizer controller224. Additionally, as described, the hint signal is sent to circuitry in the second clock domain at least one cycle prior to the sending of the contiguous data output with one or more interleaved dead cycles. By way of illustration, continuing with the example of receiving multiplexed data, for instance, having two interleaved data packets including header blocks, such as H0H1A0A1B0B1C0C1D0D1, the data is transmitted sequentially and contiguously to a second clock domain third circuit portion240as SA0B0C0D0A1B1C1D1, wherein “S” is the hint signal. By providing the circuitry in the second clock domain with advance knowledge that a data block transfer may occur via a hint signal, the hardware of the second clock domain may make decisions in anticipation of the data blocks to move the data blocks into the second clock domain faster or slower, as required, thereby solving timing and throughput problems. Moreover, by interleaving the dead cycles between the first and second clocks, based on the advance knowledge provided by the synchronizer controller, into the contiguous data transmitted to the core-to-bus synchronizer, the present system minimizes latency and provides for the efficient transfer of data across clock boundaries.

FIG. 3depicts a timing drawing of the various signals associated with the system200described hereinabove. As illustrated, the timing sequence300exemplifies an embodiment of a FIRST CLOCK302, a SECOND CLOCK304and a SYNC pulse signal306, wherein within each timing window, five FIRST CLOCK signals302are present for every four SECOND CLOCK signals304. A cycle COUNT308refers to the numbering of FIRST CLOCK signals302in a particular data transmit window of the timing sequence300. Received data310, i.e., core data, includes two multiplexed data packets, packets0and1which are to be transferred from the fast clock domain as represented by the FIRST CLOCK signal302to the slow clock domain as represented by the SECOND CLOCK signal304. The data blocks of each packet are designed by their respective subscripts0and1. For example, packet0comprises data blocks A0, B0, C0, and D0(with a header H0) that are interleaved with the data blocks of packet1which include data blocks A1, B1, C1, and D1(with a header H1). The SYNC pulse signal306may be generated based on a predetermined temporal relationship between the FIRST CLOCK and the SECOND CLOCK. As illustrated, the SYNC pulse is high on the coincident rising edges of the FIRST CLOCK and the SECOND CLOCK and the data processing operations of the second circuit portion are timed with reference to the SYNC pulse. As alluded to in the Background, since the FIRST CLOCK has five cycles and the SECOND CLOCK has four cycles, the FIRST CLOCK domain circuit portion cannot transmit data during one cycle resulting in one dead cycle, as the SECOND CLOCK domain circuit portion does not have a corresponding time slot for receiving it. The dead cycle control signals, c2b_valid_ff312, c2b_valid_m_ff[1]314, c2b_valid_m_ff[2]316, c2b_valid_m_ff[3]318, and c2b_valid_m_ff[4]320, provided by the synchronizer controller to the control logic are advance notice indicative of the location of the dead cycle between the FIRST CLOCK domain and the SECOND CLOCK domain. Specifically, the c2b_valid_ff control signal312indicates that the dead cycle is occurring at the 5th cycle, cycle4, the c2b_valid_m_ff[1] control signal314provides one cycle advance notice that the dead cycle is at the 5th cycle, cycle4, the c2b_valid_m_ff[2] control signal316provides two cycles advance notice that the dead cycle is at the 5th cycle, cycle4, the c2b_valid_m_ff[3] control signal318provides three cycles advance notice that the dead cycle is at the 5th cycle, cycle4, and the c2b_valid m_ff[4] control signal320provides four cycles advance notice that the dead cycle is at the 5th cycle, cycle4.

FIG. 4depicts a flow chart of an embodiment of a method for effectuating the transfer of data blocks using a hint signal across a clock boundary between a first clock domain and a second clock domain. At block400, a header block is processed in association with the data blocks that will be sent from the first clock domain to the second clock domain via a synchronizer. At block402, a hint signal is generated responsive to the header block, which hint signal is positioned at least one cycle prior to the location of the data blocks. At block404, the hint signal is transmitted to a control block in the second clock domain, thereby indicating that the data blocks may be sent to receiver circuitry in the second clock domain. At block406, appropriate control signals are generated based on the hint signal for controlling output of the data blocks in a particular ordered grouping.

FIG. 5A-5Edepict a plurality of timing drawings of received data and sent data associated with a plurality of control signals described above. As illustrated inFIG. 3, with reference to the timing drawing500ofFIG. 5A, five FIRST CLOCK signals302are present within each timing window for every four SECOND CLOCK signals304. Also, a SYNC pulse306is present that affects the transfer operations between the FIRST CLOCK domain and the SECOND CLOCK domain. Since five FIRST CLOCK signals302are present for every four SECOND CLOCK signals304, one dead cycle per transmission window is present. Multiplexed packets0and1provide interleaved data blocks, i.e., H0, H1, A0, A1, B0, B1, C0, C1, D0, and D1, or channeled packet data. In the timing drawing500ofFIG. 5A, the synchronizer controller provides advance notice of the location of the dead cycle by sending control signal c2b_valid_ff312to the control logic. Control signal c2b_valid_ff312indicates that the fifth cycle, cycle4, of the timing window is a dead cycle for the transmission of data from the fast clock domain to the slow clock domain. It should be appreciated that althoughFIGS. 5A-5Eare described with relation to control signal c2b_valid_ff312, the systems and methods of the present invention may be practiced with any of the aforementioned control signals312-320. Accordingly, the control logic and MUX of the present system transmit sent data502including the hint signal contiguously, i.e., SXA0B0C0D0XA1B1C1D1X, optimally positioning the hint signal (S) and data blocks about the dead cycles (X). In the embodiment described, the hint signal prepares the third circuit portion circuitry to forward the data blocks to receiving circuitry in the second clock domain without queuing. In particular, the positioning of the hint signal is adjusted so as not to coincide with a dead cycle. It should be appreciated that although timing drawing500only depicts packet0being transmitted (sent data502), packet1, i.e., A1B1C1D1, is transmitted as well. In particular, the following table illustrates the operations of one embodiment of the second circuit portion operating under control signal c2b_valid_ff312wherein data is received at the first cycle:

TABLE 1Operation of Second Circuit Portion Under Control Signalc2b_valid_ff Upon Receiving Data at Cycle 0CYCLEOPERATION(S)0Receive header block H0at control logic1Receive header block H1at control logic2Receive data block A0from channeled packet interface (CPI)Temporarily store data block A0in a first queue3Receive data block A1from CPITemporarily store data block A1in second queueSend hint signal generated responsive to header block H0Prepare third circuit portion to pass through data blockswithout queuing4Receive data block B0from CPITemporarily store data block B0in the first queueReceive zero cycle advance notice of the location of the deadcycle at cycle 4No Transmission—Dead Cycle0Receive data block B1from CPITemporarily store data block B1in the second queueSend data block A01Receive data block C0from CPITemporarily store data block C0in the first queueSend data block B02Receive data block C1from CPITemporarily store data block C1in the second queueSend data block C03Data block D0passes through via a register without queuing4Receive data block D1from CPITemporarily store data block D1in the second queueReceive zero cycle advance notice of the location of the deadcycle at cycle 4No Transmission—Dead Cycle0Send data block A11Send data block B12Send data block C13Send data block D14No Transmission—Dead Cycle

Similarly,FIGS. 5B-Edepict various configurations of sent data having contiguous data blocks with a hint signal positioned relative to a dead cycle. For example, with reference to timing drawing504ofFIG. 5B, the received data310is received at the second cycle and control signal c2b_valid_ff312indicates that the dead cycle is positioned at the fifth cycle, cycle4. Accordingly, the sent data506including the hint signal is transmitted as SA0B0C0XD0. It should be appreciated that the dead cycle may appear to be interleaved in between two data blocks or at the leading end, i.e., before A0, or at the trailing end, i.e., after D0, of a data packet. By way of example, the dashed lines of data blocks A0, B0, C0, and D0indicate that due to the processing of the header block H0, the data blocks A0, B0, C0and D0were not transmitted/received between the clock domains. For example, the processing of header block H0is time-consuming and the data blocks A0, B0, C0and D0are temporarily queued in the second clock domain before being forwarded to circuitry in the second clock domain. The hint signal minimizes timing problems by providing advance knowledge to the second clock domain that the processing of the header is on-going. This allows the data blocks A0, B0, C0, and D0to be temporarily stored in the second clock domain (i.e., CLK2) before being forwarded to the receive circuitry therein. The following table illustrates the operations of one embodiment of the second circuit portion operating under control signal c2b_valid_ff312during the first ten cycle counts wherein data is received at the second cycle:

TABLE 2Operation of Second Circuit Portion Under Control Signalc2b_valid_ff Upon Receiving Data at Cycle 1CYCLEOPERATION(S)1Receive header block H0at control logic2Receive header block H1at control logic3Receive data block A0from CPITemporarily store data block A0in a first queue4Receive data block A1from CPITemporarily store data block A1in second queueReceive zero cycle advance notice of the location of the deadcycle at cycle 40Receive data block B0from CPITemporarily store data block B0in the first queueSend hint signal generated responsive to header block H0Prepare third circuit portion to queue the data blocks1Receive data block B1from CPITemporarily store data block B1in the second queueSend data block A0Queue data block A0 in CLK2 domain2Receive data block C0from CPITemporarily store data block C0in the first queueSend data block B0Queue data block B0in CLK2 domain3Receive data block C1from CPITemporarily store data block C1in the second queueSend data block C0Queue data block C0in CLK2 domain4Receive data block D0from CPITemporarily store data block D0in the first queueReceive zero cycle advance notice of the location of the deadcycle at cycle 4No Transmission—Dead Cycle0Receive data block D1from CPITemporarily store data block D1in the second queueSend data block D0Queue data block D0in CLK2 domain

Similarly, with reference to timing drawing508ofFIG. 5C, the received data310is received at the third cycle and the control signal c2b_valid_ff312indicates that the dead cycle is positioned at the fifth cycle, cycle4. Accordingly, sent data510including the hint signal is transmitted as SA0B0C0XD0to the synchronizer. With reference to timing drawing512ofFIG. 5D, the received data310is received at the fourth cycle and the control signal c2b_valid_ff312provides advance notice that the dead cycle is located at the fifth cycle, cycle4. The circuit therefore transmits sent data514including the hint signal as SA0B0XC0D0. Similar to the sent data506ofFIG. 5B, the data blocks A0, B0, C0, and D0of sent data514are exemplified with dashed lines to indicate that the processing of the header is consuming additional cycles and the data blocks will be temporarily queued in the second clock domain before being forwarded to I/O receive circuitry therein. With reference to timing drawing516ofFIG. 5E, the received data310is received at the fifth cycle and the control signal c2b_valid_ff312indicates that the dead cycle is located at the fifth cycle, cycle4. Hence, sent data518including a hint signal is transmitted SA0XB0C0D0. Importantly, the control logic block sends the hint signal in a manner that accommodates the dead cycle. As illustrated by the variable arrival times of the received data310inFIGS. 5A-5E, the hint signal described herein provides notice of a possible data transfer regardless of the cycle at which data is received.

Accordingly, it should be appreciated that by practicing the teachings described herein, latency may be reduced during the transmission of received data which includes a header. In particular, during the processing of the header block in the first clock domain, a hint signal is generated and positioned at least one cycle before the transmission of the data so that the hardware in the second clock domain can anticipate the arrival of the data and prepare accordingly. Moreover, it should be appreciated that the systems and methods described herein may be practiced with non-intervaled and any intervaled data, including multiplexed data, having any number of dead cycles.

Although the embodiments herein have been particularly described with reference to certain illustrations, it is to be understood that the forms of the invention shown and described are to be treated as exemplary embodiments only. Various changes, substitutions and modifications can be realized without departing from the spirit and scope of the invention as defined by the appended claims.