Regulated voltage systems and methods using intrinsically varied process characteristics

A regulator system includes a multi-bit detector system and a multi-cell charge/discharge circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of detectors has a predetermined threshold voltage. The multi-cell charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge. Each of the charge pumps is associated with a predetermined threshold voltage of the detector circuit.

BACKGROUND

DC/DC voltage regulators generally consist of a reference system, a clock generator, and a boosting/bucking circuit. The regulator receives an input voltage and generates a boosted (stepped-up) or bucked (stepped-down) voltage as an output. In certain applications, such as memory or LED drivers, an input voltage is provided at a predetermined supply or ground and an output is a positive voltage higher than the supply voltage or a negative voltage less than the ground voltage.

A boosting/bucking circuit can be activated according to a reference system to produce an output at a predetermined level. The reference system determines the accuracy of the output. Current reference systems can utilize one or more architectures, such as a voltage comparator including a tapped output compared to a predetermined reference voltage or a level shifter configured to compare a segmented level voltage to a reference voltage.

Current reference systems generate large ripples and die-to-die inaccuracies in an average output voltage due to process variations. The process variations are caused by process deviations such as variations in device (e.g., MOS and/or resistor) dimensions, threshold voltage, mismatch in MOS/resistor ladders, and/or other sources. If the reference system has a variation from a predetermined level, the output cannot be set to a reliable level.

DETAILED DESCRIPTION

In various embodiments, a regulator circuit is disclosed having a smaller ripple across a current load and a reference circuit having a fixed decision level across the current load and process. The regulator circuit is separated into a plurality of unit charge pumps. The output of each of the unit charge pumps is shunted together. The reference system has a compensation approach for minimum decision level variation to provide a fixed level across the current load and process.

FIG. 1illustrates one embodiment of a regulator circuit2, in accordance with some embodiments. The regulator circuit2includes a level detector4(or reference/comparison circuit), a clock6, and a charge/discharge circuit8. The level detector4has a first input10coupled to a reference voltage Vref. The reference voltage Vrefcan be a predetermined value and can be any suitable value, for example, a value greater than a supply voltage and/or less than ground. The level detector4has a second input12coupled to an output (Vout)14of the charge/discharge circuit8. The level detector4compares the reference voltage Vrefto the output14of the charge/discharge circuit8and compensates for variations in the output14. In some embodiments, the regulator system circuit2includes a multi-cell detector and/or a multi-cell pumping circuit to reduce ripple in the output14, as discussed in further detail below.

FIG. 2illustrates one embodiment of a regulator circuit2aincluding a multi-level detector4aand a multi-cell charge/discharge circuit8a. The multi-level detector4aincludes a plurality of detectors each configured to detect a predetermined voltage, current load, and/or other circuit parameter within a predetermined range. One embodiment of a detector is discussed in more detail below with respect toFIG. 6. The multi-level detector4acan include a plurality of detectors each having a different detector level. In some embodiments, the detector level is determined intrinsically by process variations in the detectors that occur during formation thereof. The detectors can be compensated, for example, by a compensation circuit, to decrease the intrinsic trigger levels for one or more charge pumps18_1-18_n, as discussed in more detail below with respect toFIG. 6. In some embodiments, the each of the detector levels is equal to M*x, where M is the detector number within the plurality of detectors and x is the voltage value between each level. For example, in some embodiments, each of the detector levels is separated by a voltage value x of 0.45 volts such that a first detector of the multi-bit detector has a trigger voltage of 0.45 volts, a second detector has a trigger voltage of 0.90 volts, etc. up to a maximum value of M*0.45 volts, where M is the total number of detectors in the multi-bit detector4a. Although an example of 0.45 volts has been recited herein, it will be appreciated that the voltage value between each detector level can be smaller or greater than 0.45 volts and/or may vary from detector to detector.

In some embodiments, the multi-level detector4agenerates an n-bit output16corresponding to the plurality of levels activated by the detector4afor a given output (Vout)14. In some embodiments, the number of bits n in the output16corresponds to the number of levels M of the multi-level detector4a. In other embodiments, the number of bits n can be greater than the number of levels M of the multi-level detector4a(activating multiple cells in the n-bit pumping cell8aper detector level) and/or smaller than the number of levels M of the multi-level detector4a. The n-bit output16can be provided to multi-cell charge/discharge circuit8ahaving a plurality of charging pumps18_1-18_n. Each of the charging pumps18_1-18_nis configured to generate a predetermined charge, i.e., a predetermined energy value to maintain the output of the regulator circuit2aat a predetermined value, such as a predetermined boost and/or buck value. One or more of the plurality of charge pumps18_1-18_nare activated to maintain a predetermined output14to drive the load current Iload20. In some embodiments, the n-bit output16has a number of bits equal to the number of charge pumps18_1-18_nin the multi-cell charge/discharge circuit8a. Although embodiments having an n-bit output signal and n charging pumps18_1-18_nare discussed herein, it will be appreciated that the number of bits in the output signal16may be greater than or less than the number of charge pumps18_1-18_nin the multi-cell charge/discharge circuit8a. For example, in some embodiments, an output signal16having fewer bits than cells in the charge/discharge circuit8acan activate two or more pumping cells per bit change. In other embodiments, the charge pumps18_1-18_ncan include additional control logic configured to respond to a plurality of bits in the output signal16to control each of the pumping cells in the charge/discharge circuit8a.

FIG. 3illustrates the average voltage VPP(also referred to herein as Vout) of the n-bit pumping cell8aas Iloadincreases, in accordance with one embodiment in which M=4. A plurality of voltage drops20a-20care shown inFIG. 3. Each of the voltage drops20a-20ccorresponds to activation of an additional charge pump18_2-18_nwithin the 4-bit pumping cell8a. The drop-off size is proportional to the size and number (n) of charge pumps18_1-18_nwithin the charge/discharge circuit8a. For example, a greater number of charge pumps, each having a smaller capacity, to generate the same voltage as a smaller number of larger charge pumps produces a smaller drop and provides a flatter voltage output than a smaller number of larger charge pumps.

FIG. 4illustrates one embodiment of a regulator circuit2bincluding a plurality of pumping cells24_1-24_n. Each of the pumping cells24_1-24_nincludes a charge pump18and a controller/detector4a, for example, as illustrated inFIG. 2. Each of the pumping cells24_1-24_nis coupled to a load25. In the illustrated embodiment, the load25is represented by a diode, although it will be appreciated that any suitable load can be included in each of the pumping cells24_1-24_n. Each of the controllers4acan be configured to activate a charge pump18at a predetermined detector level. The plurality of charge pumps18have their outputs14coupled together. The outputs14can be coupled in any suitable configuration, such as, for example, one or more serial connections and/or shunt connections, in accordance with various embodiments. The charge pumps18generate a predetermined charge configured to maintain a predetermined output voltage. As the load (Iload) on the regulator circuit2bincreases, additional charge pump18_1-18_nare activated to generate additional pumping energy, or charge, up to a predetermined shut-off load. In some embodiments, each of the pumping cells24_1-24_nhas a predetermined detector level. The predetermined detector level is set by one or more process variations in the formation of the pumping cells24_1-24_n. In some embodiments, a compensator (as described below with respect toFIG. 6) is configured to modify the intrinsic detector level by compensating for one or more of the process defects in the pumping cells24_1-24n.

In some embodiments, the plurality of pumping cells24_1-24_nare identical and configured to generate substantially identical charge levels when activated (e.g., the charge generated by the charge pumps18_1-18_ncan vary by a predetermined margin of error). In other embodiments, the pumping cells24_1-24_ncan be configured to generate a plurality of charges when activated. For example, in some embodiments, the plurality of charge pumps18_1-18_ncan be configured to generate up to n charges, where n is equal to the number of charge pump18s_1-18_nin the voltage regulator2b. Each of the charge pumps18_1-18_ngenerate a predetermined charge. For example, in some embodiments, each pumping cell24_1-24nis configured to generate a pre-charge voltage and a boost voltage, as discussed in more detail below with respect toFIGS. 9-14. In some embodiments, the pre-charge voltage is 1V and the boost voltage is 2V. When additional current loading is added to a circuit, one or more charge pumps18are activated to add additional charge to maintain a constant voltage and/or are transitioned to a boost state. In some embodiments, each of the charge pumps18is configured to generate the same predetermined charge (or energy).

FIG. 5is chart100illustrating a ripple in various embodiments of pumping cells each having the same maximum load capacity. An output voltage (VPP) is illustrated on the Y-axis and a current load (Iload) is illustrated on the X-axis. A first ripple102and a second ripple104are provided for regulator circuits having a single charging pump configured to produce a predetermined voltage, X. A third ripple106and a fourth ripple108are illustrated for 4-bit regulator circuits having four individually controlled charging pumps each configured to produce a predetermined charge. As shown inFIG. 5, each of the single charging pump pumping cells have a larger ripple102,104than the ripple106,108of the 4-bit regulator circuits. In some embodiments, the regulator circuits include control process compensation for one or more detectors configured to detect the voltage level of the load and to control the pumping cells as discussed in more detail below with respect toFIGS. 6-8C. For example, as shown inFIG. 5, a one-bit regulator circuits having a single detector without control process variation compensation produces a ripple102greater than a ripple104of a one-bit regulator circuits having a single detector with control process variation compensation. Similarly, a 4-bit regulator circuits using a multi-level detector without control process compensation produces a ripple106greater than a ripple108generated by a 4-bit regulator circuits using a multi-level detector including a plurality of detectors having control process variation compensation, as discussed below.

FIG. 6illustrates one embodiment of a detector50including a compensation circuit54to compensate for one or more process variations, such as, current bias variation from a constant transconductance bias current and/or compensation for device aspect ratio and/or threshold voltage variation in the charge pumps18_1-18_n. The detector50provides a faster response and smaller size than traditional detector circuits. The detector50includes a current comparator52and a compensator54. The current comparator52is configured to compare a trigger current (Ide) to a predetermined transconductance current (Igm). The transconductance current is predetermined during manufacture of the current comparator52and corresponds to the detection level (e.g., the trigger voltage Vtrig, which is described in more detail below) that the current comparator52is configured to detect. In some embodiments, a multi-level detector4aincludes a plurality of detectors50each having a different transconductance current corresponding to a different detection level of the multi-level detector4ainFIG. 2. In other embodiments, a regulator circuit2binFIG. 4includes a plurality of pumping cells24_1-24_neach having a detector50therein.

In some embodiments, the current comparator52includes two diode-connected MOS and a transistor (PMOS/NMOS) current sources58a,58bbiased by a constant-transconductance biasing current (Igm). A resistor56is coupled in series between the reference voltage Vrefand the transistor current sources58a,58bto generate the constant-transconductance biasing current (Igm). In some embodiments, the current comparator52includes a positive reference system configured to provide level detection during a positive phase of the load current Iload20and a negative reference system configured to provide level detection during a negative phase of Iload20(as shown inFIG. 2).

In some embodiments, the positive reference system includes a PMOS current source58a. The PMOS current source58aincludes a first PMOS transistor60aand a second PMOS transistor60b. The first PMOS transistor60ais coupled to an input resistor56. The input resistor has a predetermined resistance R and is coupled to a reference voltage input Vref. The first PMOS transistor60adraws a constant transconductance biasing current (Igm). The first PMOS transistor60ais further coupled to ground and can be coupled to ground through one or more additional circuit elements, such as a negative reference system, as discussed in more detail below. The drain of the second PMOS transistor60bis also coupled to the reference voltage Vref. The gates of each of the PMOS devices60a,60bof the PMOS current source58aare coupled together and are further coupled to the source of the second PMOS transistor60b.

The output of the PMOS current source58ais provided as a pass-gate voltage (VPG) to a gate of a PMOS pass-gate62. A first gate-source voltage Vgs1develops between the gate and the source of the PMOS pass-gate62. The drain of the PMOS pass-gate62is coupled to the drain of a first compensation transistor68having a source coupled to ground and a gate coupled to the gates of transistors60aand60b. The source of the PMOS pass-gate62is coupled to the drain and gate of an adjustment transistor64. The adjustment transistor64can include a tapped point transistor. The adjustment transistor64is configured to adjust the default Vtrigvoltage, for example, by providing a compensation for the bias current (Igm). The source of the adjustment transistor64is coupled to a voltage input66. In some embodiments, the voltage input66is equal to the output voltage Voutof a pumping cell24_1-24_n24_1-24_n(for example, 1V) associated with the detector50. A second gate-source voltage Vgs2develops between the gate and the source of the adjustment transistor64. Although embodiments are described herein including an adjustment transistor64, it will be appreciated that the adjustment transistor64can be omitted and the voltage input66can be coupled directly to the PMOS pass-gate62, in accordance with alternative embodiments.

In some embodiments, a trigger voltage of the current comparator52is determined according to the equation:
Vtrig=VPG+Vov1+Vt1+Vov2+Vt2
where Vov1is the overdrive voltage of the PMOS pass-gate62, Vt1is the threshold voltage of the PMOS pass-gate62, Vov2is the overdrive voltage of the adjustment transistor64, and Vt2is the threshold voltage of the adjustment transistor64. The overdrive voltage of each of the PMOS pass-gate62and the adjustment transistor64is determined according to the equation:
Vov=Vgs−Vt
where Vgsis the gate-source voltage of the transistor and Vtis the threshold voltage of the transistor.

In operation, in accordance with some embodiments, the voltage input66is coupled to the output of the n-bit pumping cell8a, as described above. The voltage input66is configured to activate the pumping cell24_1-24_nassociated with the detector50. For example, in some embodiments, at a threshold condition where Vout=Vtrig, the drain of the PMOS pass-gate62is at a high impedance point and VDis equal to Vref. If Voutdrop below Vtrig, VDalso drops, causing Vgs1to drop and the drain of PMOS pass-gate62to drop off sharply. The inverter output78is set to high and the pumping cell24_1-24_nis activated (and/or transitioned to a boost mode). If Voutexceeds Vtrig, Vgs1is also high, and the drain of the PMOS pass-gate62increases. The output78is set low and the pumping cell24_1-24_nstops pumping.

In some embodiments, the output78is passed through one or more static CMOS inversion circuits72a-72cbefore being provided to an output16. The one or more CMOS inversion circuits72a-72ccan provide one or more adjustments to the output, such as a timing delay, a voltage shift, and/or any other suitable adjustment. Although CMOS inversion circuits72a-72care illustrated, it will be appreciated that one or more of the CMOS inversion circuits72a-72ccan be replaced with any other suitable inversion circuit, such as, for example, a pseudo-NMOS inversion circuit. As shown inFIG. 2, the output is provided as part of an n-bit output16to the n-bit pumping cell8aand causes one or more cells18_1-18_nwithin the n-bit pumping cell8ato charge and/or discharge, adjusting the output of the n-bit pumping cell8ahigher or lower (e.g., charging or discharging) to maintain an average output voltage. Process variations can occur during formation of each of the circuit elements resulting in process variations in one or more circuit elements, such as, for example, the resistor56, the PMOS current source58, and/or any other circuit element that can affect the detector level of the current comparator52.

In some embodiments, a compensation circuit54is provided to compensate for process variations in the current comparator52. In some embodiments, the compensation circuit54includes a first compensation transistor68configured to provide compensation for current bias variations from the predetermined constant transconductance bias current (Igm). For example, in some embodiments, as Igmdecreases, the pass-gate voltage (VPG) increases, and each of the trigger current (Ide), the gate-source voltages (Vgs2) decrease, resulting in a trigger voltage (Vtrig) less than the predetermined voltage. The decreased trigger voltage causes the detector50to output an activation bit to one or more pumping cells18_1-18_nat a lower voltage than required. The first compensation transistor68provides a current injection to the current comparator52to compensate for Igmvariations, as described in more detail below.

In some embodiments, the first compensation transistor68includes an NMOS transistor having a gate coupled to the gates of the current source58a. The source of the first compensation transistor68is coupled to the drain of the PMOS pass-gate62. When the gate-source voltage (Vgs) of the compensation transistor68is greater than the gate-drain voltage (Vgd) of the transistor68, a compensation current (Icom1) flows across the first compensation transistor68. The compensation current (Icom1) causes an increase and/or a decrease of the trigger current (Idc) to adjust the trigger current (Ide) to compensate for transconductance current (Igm) variations.

In some embodiments, a second compensation transistor70is configured to provide compensation for device aspect ratio and/or threshold voltage variations in one or more transistors, such as, for example, the PMOS pass-gate62. For example, variations in the threshold voltage of the PMOS pass-gate62increase the gate-source voltage necessary to allow a detector current to flow through the PMOS pass-gate62. The gate-source voltage (Vgs1) for the PMOS pass-gate62is determined by the equation:
Vgs1=Vov1+Vt1
where Vov1is the overdrive voltage of the PMOS pass-gate62and Vt1is the threshold voltage of the PMOS pass-gate62. Therefore, variations in the threshold voltage Vt1of the PMOS pass-gate62results in changes to the detection level of the detector50. As another example, in some embodiments, for a given (e.g., predetermined) pass-gate voltage (VPG), any device aspect ratio (width (W)/Length (L)) variation or threshold variation in the PMOS pass-gate62causes a drop in the drain voltage (VD) of the adjustment transistor68, an increase in the detector current (Ide), an increase in the overdrive voltages (Vov1, Vov2) and an increase in the trigger voltage (Vtrig). The increased trigger voltage (Vtrig) causes the detector50to output an activation bit to one or more pumping cells18_1-18_nclose to the predetermined detector level. The second compensation transistor70provides a current injection to the current comparator52to compensate for aspect ratio and/or threshold voltage variations. In some embodiments, level shifting transistors76a,76bare configured to shift the voltage VDfrom a supply voltage to a lower, predetermined voltage to activate the second compensation transistor70.

In some embodiments, the detector50includes a negative reference system. The negative reference system includes an NMOS current source58b. The negative reference system58bis configured to provide level detection during a negative phase of the load current Iload. The output of the NMOS current source58bis coupled to a NMOS pass-gate74. The NMOS current source58band the NMOS pass-gate74operate similar to the PMOS current source58aand the PMOS pass-gate62described above in conjunction with the positive reference system, with the exception that the negative reference system is configured to generate a high control bit voltage when a trigger voltage is less than a reference voltage. Thus, a similar description is not repeated herein.

Although specific combinations and/or connections of MOS devices are illustrated herein, it will be appreciated by those skilled in the art that alternative connection schemes, for example flipping the drain and source connections of one or more MOS devices, would be apparent and are within the scope of this disclosure.

FIGS. 7A-7Dprovide charts80a-80d, respectively, each chart illustrating a graph of Vtrigsensitivity (Y-axis) to various parameter variations (X-axis) with and without the compensation circuit54.FIG. 7Aillustrates Vtrigsensitivity with respect to length (L) variations of the PMOS pass-gate62and/or the NMOS pass-gate74. As shown inFIG. 7A, the Vtrigsensitivity82awithout a compensation circuit54has much greater variance than the Vtrigsensitivity82bwith the compensation circuit54. Similarly,FIG. 7Billustrates Vtrigsensitivity with respect to threshold variations in the NMOS pass-gate74without (84a) the compensation circuit54and with (84b) the compensation circuit.FIG. 7Cillustrates Vtrigsensitivity with respect to threshold variations in the PMOS pass-gate62without (86a) and with (86b) the compensation circuit54.FIG. 7Dillustrates Vtrigsensitivity with respect to width (W) variations of the PMOS pass-gate62and/or the NMOS pass-gate74without (88a) and with (88b) the compensation circuit54. As shown in each ofFIGS. 7B-7D, the compensation circuit54reduces the variation of Vtrigfor each of the identified parameters.

FIGS. 8A-8Cprovide charts90a-90c, respectively, each chart illustrating Vtrigdistribution by statistic model simulation for detectors with and without a compensation circuit54. As shown inFIGS. 8A-8C, the compensation circuit54produces detectors50having a smaller statistical variation92bthan the statistical variation92aof detectors without compensation circuits. The values for each of the detectors illustrated inFIGS. 8A-8Care provided below as example embodiments. It will be appreciated that the provided examples are non-limiting and the compensation circuit54disclosed herein can be applied to any suitable detector50and/or comparison circuit52.FIG. 8Aillustrates a comparison of a detector having the following parameters:

N65Vmax(mV)Vmin(mV)Vpkpk(mV)Vavg(mV)Vstdev(mV)V-3sigma(mV)W/O Comp.437.2377.260.0407.910.2730.82With Comp.422.8397.225.6408.73.039.09
FIG. 8Cillustrates a comparison of a silicon detector having the following parameters:

Vmax(mV)Vmin(mV)Vpkpk(mV)Vavg(mV)Vstdev(mV)V-3sigma(mV)W/O Comp.4423628040326.1478.41With Comp.420394264077.3021.90
As can be seen in each of the above tables, the V-3sigma value of each of the circuits with compensation is about two to three times less than the V-3sigma value of each of the circuits without compensation.

FIG. 9illustrates one embodiment of a regulator circuit202, in accordance with some embodiments. The regulator circuit202includes a level detector204, a charge/discharge circuit208, and a ring oscillator206. The level detector204is configured to detect an output214of the charge pump208. As discussed above, the level detector204detects when the output Vppof the charge/discharge circuit208drops below a predetermined trigger voltage. As shown inFIG. 10, the level detector204generates a pump_enable signal242(Vppmp) when the output Vppdrops below the trigger voltage Vtrig. The pump_enable signal242is provided to a ring oscillator206, which generates an input clock signal to the charge/discharge circuit208to control one or more pumping cells222of the charge/discharge circuit208.

FIG. 11Aillustrates a circuit schematic of one embodiment of the charge/discharge circuit208of the regulator circuit202ofFIG. 9. The charge/discharge circuit208includes a plurality of charge pumps218. Each of the charge pumps218is configured to generate a predetermined charge, such as, for example, a charge sufficient to maintain a predetermined voltage output Vpp. The charge pump208includes one or more logic elements, such as the S-R latch124, configured to control the plurality of charge pumps218. The S-R latch224is configured to activate a first charge pump218awhen Vppis below a trigger voltage. The S-R latch224activates a second charge pump218bif Vppremains below the trigger voltage for a predetermined time period, as determined by the ring oscillator206. In some embodiments, the S-R latch224the timing between the first charge pump218aand the second charge pump218bis equal to a pre-charge time for each of the pumps218a,218b.

FIG. 11Billustrates one embodiment of the oscillator206of the regulator circuit202ofFIG. 9. The oscillator206generates an output clock signal zck for the charge/discharge circuit208. The oscillator206receives a pump_enable signal242from the detector204. When the pump_enable signal242is high, the oscillator206outputs the clock signal zck, which is generated by a plurality of oscillation elements244. The clock signal zck is provided as an input to the charge/discharge circuit208and drives activation of the charge pumps218a,218btherein.FIG. 12illustrates one embodiment of the oscillator clock zck, control clock ck, and inverse control clock signals ckb configured to control the charge pump108as illustrated inFIG. 11A.

FIG. 13illustrates a circuit view of one embodiment of an output Vppof a charge pump208aconfigured to provide a pre-charge voltage of 1V and a boost voltage of 2V. A pre-charge configuration250ais represented by an open switch252coupled between the gate of a transistor254and a capacitor256. When the switch252is in an open position, the capacitor256is charged and the capacitor voltage is one-volt. When the switch250is closed, the charge pump208ais transitioned to a boost mode250b, and the capacitor254maintains a one-volt charge, which causes the output voltage Vppto increase to two-volts (due to charge conservation).

In various embodiments, a system including a detector circuit having a plurality of detectors and a multi-cell charge/discharge circuit. Each of the plurality of detectors has a predetermined threshold voltage. The charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge.

In various embodiments, a detector circuit includes a current comparator configured to generate an output by comparing a reference voltage to a trigger voltage and a compensation circuit comprising at least one compensation transistor configured to compensate for at least one process variation of the current comparator.

In various embodiments, a regulator system includes a plurality of detectors. Each of the plurality of detectors includes a current comparator configured to generate an output by comparing a reference voltage to a trigger voltage and a compensation circuit having at least one compensation transistor configured to compensate for at least one process variation of the current comparator. A multi-cell charge/discharge circuit includes a plurality of charges pump. Each of the charge pumps is associated with at least one of the plurality of detectors and is configured to generate a predetermined charge.