Controller and method employed in optical storage apparatus for generating control signals each having minimum transmission pulse length corresponding to more than one power symbol period

A controller of an optical storage apparatus for generating a plurality of control signals is provided. The controller includes a code generator implemented for determining a plurality of control codes according to an input data associated with data recording, and generating the control signals to deliver the control codes. Each of the control codes represents one power level. Besides, regarding each of the control signals, a minimum transmission pulse length thereof corresponds to more than one power symbol period.

FIELD OF INVENTION

The present invention relates to write pulse transmission between a controller and a laser diode driver, and more particularly, to a controller and method employed in an optical storage apparatus (e.g., an optical disc drive) for generating a plurality of control signals (e.g., at least three write enable signals) each having minimum transmission pulse width corresponding to more than one power symbol period.

BACKGROUND OF THE INVENTION

Optical discs have become popular storage media nowadays. An optical storage apparatus, such as an optical disc drive, is therefore equipped with the data recording capability to record user data onto an optical storage medium, such as an optical disc. In general, a laser diode driver (LDD) is electrically connected between a controller and a laser diode for receiving driving and control signals generated from the controller to drive a laser diode (LD) to emit a laser beam with a designated laser power for data recording.FIG. 1is a block diagram illustrating a conventional laser diode driving system100. As one can see, the exemplary LDD104includes a plurality of current amplifiers112_1,112_2,112_3and a plurality of switches114_1,114_2,114_3. The controller102outputs driving currents IIN1, IIN2, IIN3to the current amplifiers112_1,112_2,112_3, respectively; in addition, the controller102generates write enable signals WEN1, WEN2, WEN3to the LDD104to serve as output enable signals OE1, OE2, OE3which control on/off states of the respective switches114_1,114_2,114_3. With proper control of the switches114_1,114_2,114_3, the amplified currents generated from the current amplifiers112_1,112_2,112_3are selectively combined at the output node N to drive the following LD106to emit a laser beam with a specific laser power P which is in proportion to the LD driving current received from the output node N.

Please refer toFIG. 2, which is a waveform diagram illustrating the laser power P (or the LD driving current) and the write enable signals WEN1, WEN2, WEN3. Taking a Blu-ray disc (BD) for example, the adopted write strategy supports power shape types including a block type, an L-shape type and a castle type. As shown inFIG. 2, the power symbols include a cooling power Pc, a space power Ps, a write power Pw, and a middle power Pm. For clarity and simplicity, each power symbol (power level) has duration equal to 1T (i.e., one power symbol period is 1T). Regarding the conventional write pulse transmission design, a minimum transmission pulse width equal to 1T may occur. For example, to produce the desired power shape type (i.e., block type, L-shape type or castle type), the length of the high transmission pulse of the write enable signal WEN2between T1and T2is required to be 1T; regarding the write enable signal WEN1, the length of one low transmission pulse between T2and T3, the length of another low transmission pulse between T6and T7, and the length of yet another low transmission pulse between T11and T12are required to be 1T; additionally, regarding the write enable signal WEN3, the length of a first high transmission pulse between T1and T2, the length of a second high transmission pulse between T4and T5, the length of a third high transmission pulse between T8and T9, and the length of a fourth high transmission pulse between T10and T11are required to be 1T. As the controller102is generally an unmovable control chip disposed in the optical storage apparatus, and the LDD104and LD106are disposed on a movable optical pick-up head of the optical storage apparatus, a flex cable is therefore used to electrically connect the controller102to the LDD104. However, in a case where the high-speed data recording is enabled, the transmission period of 1T may be 1.26 ns or less, which is shorter than the flex cable's minimum transmission pulse period, say, 2 ns. Therefore, the effective bandwidth of the flex cable fails to meet the requirements for transmitting 1T short transmission pulses generated under the high-speed data recording operation, leading to poor signal transmission quality between the controller102and the LDD104. As a result, the write quality is significantly degraded because the switches114_1,114_2,114_3cannot be accurately controlled to make the LD106produce laser pulses with the desired power shape.

Due to factors deteriorating the transmission quality including the impedance discontinuity and the signal loss and crosstalk of the flex cable connected between the controller and the LDD, it is better to avoid the delivery of any short transmission pulses (e.g., 1T transmission pulses) from the controller to the LDD. Therefore, an innovative scheme of transmitting the control signals, such as the write enable signals, via the flex cable connected between the controller and the LDD is needed.

SUMMARY OF THE INVENTION

In accordance with exemplary embodiments of the present invention, a controller and method employed in an optical storage apparatus (e.g., an optical disc drive) for generating a plurality of control signals (e.g., at least three write enable signals) each having minimum transmission pulse width corresponding to more than one power symbol period are proposed.

According to one aspect of the present invention, a controller of an optical storage apparatus for generating a plurality of control signals is disclosed. The controller includes a code generator implemented for determining a plurality of control codes according to an input data associated with data recording, and generating the control signals to deliver the control codes. Each of the control codes represents at least one power level. Besides, regarding each of the control signals, a minimum transmission pulse length thereof corresponds to more than one power symbol period.

According to another aspect of the present invention, a method employed in an optical storage apparatus for generating a plurality of control signals is disclosed. The method includes: determining a plurality of control codes according to an input data associated with data recording, wherein each of the control codes represents at least one power level; and generating the control signals to deliver the control codes, wherein regarding each of the control signals, a minimum transmission pulse length thereof corresponds to more than one power symbol period.

DETAILED DESCRIPTION

To put it simply, the present invention proposes a controller and related method of an optical storage apparatus for generating a plurality of control signals by: determining a plurality of control codes according to information transmitted via an input data associated with data recording, where each of the control codes corresponds to a power symbol (power level), and generating the control signals to deliver the control codes, where bits of each of the control codes are respectively delivered via the control signals, and in each of the control signals, a minimum transmission pulse length corresponds to more than one power symbol period. To more clearly describe technical features of the present invention, certain exemplary embodiments are given as follows.

FIG. 3is a block diagram illustrating a laser diode driving system300which employs an exemplary controller302of the present invention. The controller (e.g., a control chip of an optical storage apparatus)302includes, but is not limited to, a write strategy (WSR) circuit322and a code generator324coupled to the WSR circuit322. The code generator324serves as an encoder configured to refer to an input data, either the non-return-to zero (NRZ) data (i.e., data to be recorded) or an output generated from the WSR circuit322through processing the NRZ data, for sequentially determining a plurality of control codes according to information transmitted via the input data associated with data recording, where each of the control codes corresponds to one power symbol (power level), such as a cooling power Pc, a space power Ps, a write power Pw, or a middle power Pm. Besides, the code generator324is also implemented for generating at least three control signals WEN1, WEN2, WEN3to sequentially deliver the control codes, where bits of each of the control codes are respectively delivered via the control signals WEN1, WEN2, WEN3. Particularly, regarding each of the control signals WEN1, WEN2, WEN3in this exemplary embodiment of the present invention, a minimum transmission pulse length corresponds to more than one power symbol period. More specifically, in one preferred implementation, the minimum transmission pulse length corresponds to at least two power symbol periods to effectively alleviate the undesired effects caused by the flex cable connected between the controller302and the LDD304.

In addition to current amplifiers312_1,312_2,312_3and switches314_1,314_2,314_3, the LDD304includes a decoder316for receiving each control code having bits respectively transmitted via the control signals WEN1, WEN2, WEN3. When receiving one control code generated from the controller302, the decoder316decodes the received control code to set the output enable signals OE1, OE2, OE3for selectively switching on or switching off the respective switches314_1,314_2,314_3. In this way, the LD306is driven to generate a laser beam with a designated laser power P′ in response to the LD driving current at the output node N′. As the output enable signals OE1, OE2, OE3are generated from the decoder316included in the LDD304, rather than generated from the controller302and then transmitted via the flex cable, the output enable signals OE1, OE2, OE3can meet the requirements of the high-speed data recording operation. Besides, in this exemplary embodiment, the code generator324is configured to properly set each code transmitted via the flex cable so that there is no short transmission pulse (i.e., 1T transmission pulse) included in the control signals WEN1, WEN2, WEN3. In other words, the code generator324is implemented to guarantee that a minimum transmission pulse length must correspond to more than one power symbol period. In this way, as the signal transmission quality of the control signals WEN1, WEN2, WEN3will not be significantly degraded due to limited bandwidth of the flex cable, the write quality can be improved accordingly.

It should be noted that the exemplary implementation of the LDD304shown inFIG. 3is for illustrative purposes only. Other LDD implementations which can generate the desired LD driving current based on the control code delivered via control signals generated from the exemplary controller302of the present invention are feasible.

FIG. 4is a block diagram illustrating an exemplary implementation of the controller302shown inFIG. 3. In this exemplary implementation, the WSR circuit322processes data to be recorded (i.e., the NRZ data) according to a reference clock CLK, and is capable of deriving power shape data Data_PS which are indicative of the power shape types (e.g., a block type, an L-shape type, and a castle type as defined in the Blu-ray disc specification) to be used and generating input codes Code_1which are indicative of power levels (e.g., a cooling power, a space power, a write power, and a middle power) to be used. The code generator324includes, but is not limited to, a code table402, a state machine404and a multiplexer (MUX)406, and selectively uses the NRZ data, the power shape data Data_PS, or the input codes Code_1as an input data to thereby determine the control codes Code_2. In this exemplary implementation, the code table402and the state machine404are individual functional blocks. In this way, the code table402external to the state machine404is programmable, and can be programmed easily when needed. However, in an alternative design, the code table402can be integrated in the state machine404to simplify the overall hardware implementation. This also obeys the spirit of the present invention.

The state machine404is operated according to the input data (i.e., the NRZ data, the power shape data Data_PS, or the input codes Code_1), and has a plurality of states respectively corresponding to a plurality of control codes, respectively. Therefore, the state machine404outputs a specific control code of a specific state when entering the specific state according to the input data. The code table402is implemented for storing control codes mapped to the states. In this exemplary implementation, the state machine404requests the code table402for the specific control code mapped to the specific state when entering the specific state.FIG. 5shows one implementation of the code table402shown inFIG. 4, andFIG. 6shows a first exemplary state diagram of the state machine404shown inFIG. 4. When the state machine404enters the state S0, a corresponding control code outputted to the multiplexer406will be Code_2=c1=000′b (i.e., binary code 000). Next, when there is a power transition (i.e., a transition from the cooling power Pc to the space power Ps), the state machine404leaves the current state S0and enters the next state S1. Accordingly, a corresponding control code outputted to the multiplexer406will be Code_2=s1=001′b.

Similarly, when there is a power transition (i.e., a transition from the space power Ps to the write power Pw), the state machine404leaves the current state S1and enters the next state S5. Accordingly, a corresponding control code outputted to the multiplexer406will be Code_2=w1=101′b. As shown inFIG. 6, there are three possible paths (power transitions) from the same state S5to different states S4, S6, S7. In one implementation, a power shape type corresponding to the next control code is determined according to the power shape data Data_PS, and the state machine404enters a proper state to set the next control code according to the determined power shape type. For example, the state machine404leaves the current state S5and enters the next state S4if the power shape type is the L-shape type, the state machine404leaves the current state S5and enters the next state S6if the power shape type is the castle type, and the state machine404leaves the current state S5and enters the next state S7if the power shape type is the block type.

Generally speaking, T-patterns of the NRZ data are related to the used power shape types. For example, the power shape with a block type is used for recording a 2T pattern, the power shape with an L-shape type is used for recording a 3T pattern, and the power shape with a castle type is used for recording a pattern selected from a group consisting of 4T-9T patterns. The T-pattern therefore can also be used to decide the path (state transition) from one state to another state. In another implementation, a T-pattern corresponding to the next control code is determined according to the data to be recorded (i.e., the NRZ data), and the state machine404enters a proper state to set the next control code according to the determined T-pattern. For instance, the state machine404leaves the current state S5and enters the next state S4if the determined T-pattern is a 2T pattern which implies that a power shape with a block type will be used correspondingly, the state machine404leaves the current state S5and enters the next state S6if the determined T-pattern is a 3T pattern which implies that a power shape with an L-shape type will be used correspondingly, and the state machine404leaves the current state S5and enters the next state S7if the determined T-pattern is one of 4T-9T patterns which implies that a power shape with a castle type will be used correspondingly.

In yet another implementation, a look-ahead scheme is employed to decide the state transition. Assume that the state machine404is currently staying at a current state S5for outputting a current control code Code_2=w1. If a current power transition is from the current write power Pw to the next cooling power Pc, the state machine404leaves the current state S5and enters the next state S7without considering a next power transition immediately following the current power transition. However, if the current power transition is from the current write power Pw to the next middle power Pm, there are two possible state transition options, i.e., S5->S4and S5->S6. Therefore, the look-ahead scheme is active to take the next power transition, either from the middle power Pm to the cooling power Pc or from the middle power Pm to the write power Pw, into consideration for deciding the actual state transition. In this implementation, the state machine404refers to the input codes Code_1to determine at least one second input code following a first input code corresponding to the next control code, and enters a proper state to set the next control code according to the at least one second input code. For example, when the first input code and the second input code following the first input code are indicative of middle power Pm and cooling power Pc, respectively, the state machine404therefore leaves the current state S5and enters the next state S4; on the other hand, when the first input code and the second input code following the first input code are indicative of middle power Pm and write power Pw, respectively, the state machine404leaves the current state S5and enters the next state S6.

As a person skilled in the art can readily understand the state transitions of other states shown inFIG. 6after reading above paragraphs, further description is omitted here for brevity.

The multiplexer406shown inFIG. 4is responsible for outputting the control signals WEN1, WEN2, WEN3to deliver each control code Code_2generated from the state machine404. As clearly shown inFIG. 5, bits of each control code Code_2are respectively delivered via the control signals WEN1, WEN2, WEN3generated from the state machine404. With the proper design of the control codes assigned to the power symbols Pc, Ps, Pw, Pm, where each power symbol has two different control codes assigned thereto, a minimum transmission pulse length of the control signals WEN1, WEN2, WEN3is guaranteed to correspond to more than one power symbol period. Please refer toFIG. 7, which is a waveform diagram illustrating the laser power P (or the LD driving current) and the control signals WEN1, WEN2, WEN3generated from the controller302. Taking a Blu-ray disc for example, the adopted write strategy supports power shape types including a block type, an L-shape type and a castle type. For clarity and simplicity, each power symbol has duration equal to 1T. That is, one power symbol period is 1T. As one can see fromFIG. 7, each of the transmission pulses, including high transmission pulses and low transmission pulses, has a length equal to or longer than 2T in this exemplary embodiment. That is, each of the transmission pulses corresponds to at least two power symbol periods. For instance, the high transmission pulse of the control signal WEN1between T1and T3corresponds to two power symbols Pw and Pc, and the low transmission pulse of the control signal WEN1between T3and T5corresponds to two power symbols Ps and Pw.

As shown inFIG. 7, at the time point T9, the control signal WEN1has a transition from logic low (i.e., “0”) to logic high (i.e., “1”), and the control signal WEN2has a transition from logic high to logic low. In other words, the 3-bit control code has two bits changed simultaneously, which may lead to a glitch problem under certain conditions. To solve this problem, additional states are added to the state diagram shown inFIG. 6. Please refer toFIG. 8, which shows a second exemplary state diagram of the state machine404shown inFIG. 4. One state S4″ is inserted between states S5and S6, and another state S6″ is inserted between states S2′ and S4′. It should be noted that the control codes for the states S4″ and S6correspond to the same power symbol (power level) Pm, and the control codes for the states S6″ and S4′ correspond to the same power symbol (power level) Pm. Therefore, when the state machine404decides to leave the state S5due to a required power transition from write power Pw to middle power Pm, the state machine404enters the state S4″ temporarily before entering the state S6; similarly, when the state machine404decides to leave the state S2′ due to a required power transition from write power Pw to middle power Pm, the state machine404enters the state S6″ temporarily before entering the state S4′. As the state machine404stays at the intermediate state S4″ or S6″ in a short period, the minimum transmission pulse length is slightly shorter than a length corresponding to two power symbol periods, but still corresponds to more than one power symbol period. Compared to the conventional design, such an exemplary embodiment still effectively mitigates the undesired effects caused by the flex cable connected between the controller302and the LDD304.

As shown inFIG. 4, the multiplexer406also receives the input codes Code_1indicative of the power levels from the WSR circuit322. Therefore, the multiplexer406determines the final control signals WEN1, WEN2, WEN3according to either an output of the state machine404or an output of the WSR circuit322, where bits of each of the control codes Code_1and Code_2are respectively delivered via control signals generated from the WSR circuit322and the state machine404. In this embodiment, the controller302is configured to support the novel control signal transmission scheme proposed in the present invention which guarantees that the minimum transmission pulse length corresponding to more than one power symbol period and the conventional control signal transmission scheme which may include short transmission pulse. This increases the flexibility in the use of the controller302. That is, the controller302can selectively use the novel control signal transmission scheme or the conventional control signal transmission scheme, depending upon actual application requirements. It should be noted that such a design is for illustrative purposes, and is not meant to be a limitation to the scope of the present invention. Any controller employing the novel control signal transmission scheme proposed in the present invention falls within the scope of the present invention. By way of example, not limitation, the multiplexer406is an optional element, and can be omitted in an alternative design where the novel control signal transmission scheme proposed in the present invention is employed by the controller302only.

Please note that mapping between the control codes and the power symbols (power levels) as shown inFIG. 5merely serves as one example. Provided that the result is substantially the same, other code table design can be employed. For example, the mapping between the control codes and the power symbols (power levels) can be set according to one code table selected from following exemplary code table set, where the code values in decimal format include 0-7. Please note that only five code tables are illustrated for simplicity; however, this by no means implies that the total number of all available code tables is limited to 5.

In above exemplary embodiments, each control code is assigned to one power symbol (power level) according to a one-to-one mapping rule. However, with proper modification made to the decoder316shown inFIG. 3, mapping one control code to a plurality of different power symbols (power levels) is feasible.FIG. 9shows a third exemplary state diagram of the state machine404shown inFIG. 4. The control codes c1, c2, c3and c4are mapped to the power symbol (power level) Pc, the control codes s1and s2are mapped to the power symbol (power level) Ps, the control codes m1and m2are mapped to the power symbol (power level) Pm, and the control codes w1and w2are mapped to the power symbol (power level) Pw. As can be, seen fromFIG. 9, the control codes s1and c4are identical to each other (i.e., s1=c4=100′b), and the control codes s2and c3are identical to each other (i.e., s2=c3=101′b). As the mapping between the control code and the power symbol (power level) does not follow the one-to-one mapping rule, the decoder316therefore needs additional information to decode the received control code correctly. For example, the decoder316employs a look-backward scheme when decoding the incoming control codes. Specifically, in a case where the received control code is 100′b (or 101′b), the decoder316determines that the power symbol mapped to the received control code is Ps when a previous control code or state corresponds to c1/c3(or c2/c4) or the previous power symbol is Pc; on the other hand, the decoder316determines that the power symbol mapped to the received control code is Pc when a previous control code or state corresponds to w1(or w2) or the previous power symbol is Pw. Please refer toFIG. 10in conjunction withFIG. 11andFIG. 12.FIG. 10is a diagram illustrating an exemplary implementation of the decoder316shown inFIG. 3.FIG. 11shows an exemplary implementation of a first look-up table shown inFIG. 10.FIG. 12shows an exemplary implementation of a second look-up table shown inFIG. 10. As shown inFIG. 10, the exemplary decoder316includes a first look-up table (LUT)1002, a second LUT1004, a multiplexer (MUX)1006, a selector1008, an edge detector1009, and a latch1010. The selector1008includes a plurality of decision logics1012-1018, a plurality of logic gates (e.g., OR gates)1020and1022, a latch1024, and a delay unit1026. The decision logics1012and1014are implemented to detect if the first LUT1002should be used for decoding following control codes transmitted by the control signals WEN1-WEN3, and the decision logics1016and1018are implemented to detect if the second LUT1004should be used for decoding following control codes transmitted by the control signals WEN1-WEN3. The delay unit1026is implemented to delay the selection signal SEL generated from the latch1024to the multiplexer1006. Therefore, the timing of switching between the first LUT1002and the second LUT1004is between the timing when the current control code (e.g., c1/c2/c3/c4or w1/w2) arrives at the decoder316and the timing when the next control code (e.g., s1/s2or c3/c4) arrives at the decoder316. Bits of each of the mapped control code found in the selected look-up table are respectively delivered via output enable signals to the multiplexer1006. The selection signal SEL generated from the selector1006controls the multiplexer1006to couple an input node which receives an output of the selected look-up table to an output node which is electrically connected to the latch1010. The latch1010is used to refer to an output of the multiplexer1006for generating the final output enable signals OE1, OE2, OE3to the switches314_1,314_2,314_3, respectively; however, it should be noted that the latch1010in this embodiment does not change the output enable signals OE1, OE2, OE3according to the output of the multiplexer1006unless triggered by a trigger signal TR generated from the edge detector1009. Specifically, the edge detector1009is used to perform control code transition detection (or WEN's edge detection) according to the incoming control signals WEN1-WEN3, and generates the trigger signal TR upon detecting a control code transition (or a WEN's edge). In this way, the actual laser power P′ of the LD306shown inFIG. 3is changed only when a power transition is actually needed.

FIG. 9shows that certain state transitions are controlled according to the power shapes (e.g., block type, L-shape type, and castle type as defined in the Blu-ray disc specification); however, any decision rule mentioned above can be implemented to control the state transition from a current state to a next state when the current state in the state diagram has multiple state transition options. These alternative designs all fall within the scope of the present invention.

Please note that mapping between the control codes and the power symbols (power levels) as shown inFIG. 5merely serves as one example. Provided that the result is substantially the same, other code table design can be employed. For example, the mapping between the control codes and the power symbols (power levels) can be set according to one code table selected from following exemplary code table set, where the code values in decimal format include 0-7. Please note that only five code tables are illustrated for simplicity; however, this by no means implies that the total number of all available code tables is limited to 5.

In above exemplary embodiments, the controller302is configured to employ a write strategy supporting power shape types including a block type, an L-shape type and a castle type as defined in the Blu-ray disc specification. However, in an alternative implementation, the controller302can be configured to employ a write strategy supporting power shape types only including a block type and a castle type. Please refer toFIG. 13andFIG. 14.FIG. 13shows a fourth exemplary state diagram of the state machine404shown inFIG. 4, andFIG. 14shows a fifth exemplary state diagram of the state machine404shown inFIG. 4. The control codes c1and c2are mapped to the power symbol (power level) Pc, the control codes s1and s2are mapped to the power symbol (power level) Ps, the control codes m1and m2are mapped to the power symbol (power level) Pm, and the control codes w1and w2are mapped to the power symbol (power level) Pw. Regarding the exemplary state diagram shown inFIG. 13, when the control code is changed from w1to m2(or from w2to m1) due to a state transition, there are two bits changed in the control code at the same time, which may lead to a glitch problem as mentioned above. Similar to the exemplary state diagram shown inFIG. 8, the state diagram shown inFIG. 14has one state placed in the path between a state with the control code w1and a state with the control code m2, and another state placed in the path between a state with the control code w2and a state with the control code m1. In this way, the glitch problem can be avoided. As the state machine stays at the intermediate state in a short period, the minimum transmission pulse length is slightly shorter than a length corresponding to two power symbol periods in this exemplary embodiment, but still corresponds to more than one power symbol period. Compared to the conventional design, such an exemplary embodiment still effectively mitigates the undesired effects caused by the flex cable connected between the controller302and the LDD304.

FIG. 13andFIG. 14show that certain state transitions are controlled according to the power shapes (e.g., block type, L-shape type, and castle type as defined in the Blu-ray disc specification); however, any decision rule mentioned above can be implemented to control the state transition from a current state to a next state when the current state in the state diagram has multiple state transition options. These alternative designs all fall within the scope of the present invention.

Besides, the mapping between the control codes and the power symbols (power levels) as shown inFIG. 13andFIG. 14merely serves as one example. Provided that the result is substantially the same, other code table design can be employed. For example, the mapping between the control codes and the power symbols (power levels) can be set according to one code table selected from following exemplary code table set, where the code values in decimal format include 0-7. Please note that only five code tables are illustrated for simplicity; however, this by no means implies that the total number of all available code tables is limited to 5.

In another alternative implementation, the controller302can be configured to employ a 2T multi-pulse write strategy which is commonly used for a BD-RE or DVD-RW disc under higher recording speed. For clarity, an exemplary 2T multi-pulse write strategy is shown inFIG. 15, where each power symbol has duration equal to 1T. As one can see from the figure, the duration of the write power Pw and the following cooling power Pc is equal to 2T rather than 1T, and the 2T multi-pulse write strategy is therefore applicable to high-speed data recording. Since the 2T multi-pulse write strategy is clearly defined in the optical disc specification and known to those skilled in the art, further description is omitted here for brevity. Based on the power sequence of the 2T multi-pulse write strategy for different T-patterns (e.g., 2T-9T for a Blu-ray disc), states of a state machine can be configured by referring to one of the following exemplary code tables, where the code values in decimal format include 0-7. Please note that only five code tables are illustrated for simplicity; however, this by no means implies that the total number of all available code tables is limited to 5.

In above exemplary embodiments, three control signals WEN1, WEN2, WEN3are used to deliver control codes from the controller302to the LDD304. However, using more than three control signals to deliver the control codes is also feasible.FIG. 16shows an exemplary state diagram of a state machine used for generating control codes each having four bits respectively transmitted via four control signals. Taking a Blu-ray disc for example, the adopted write strategy supports power shape types including a block type, an L-shape type and a castle type. The control codes c1-c6are mapped to the power symbol (power level) Pc, the control codes s1and s2are mapped to the power symbol (power level) Ps, the control codes m1and m2are mapped to the power symbol (power level) Pm, and the control codes w1-w4are mapped to the power symbol (power level) Pw. As a person skilled in the pertinent art can readily understand operations of the state machine operated according to the state diagram shown inFIG. 16after reading above paragraphs, further description is omitted here for brevity.

Briefly summarized, in accordance with the exemplary embodiments of the present invention, the controller and related method can effectively prevent the control signals from having the undesired short transmission pulse. More specifically, by configuring a code generator to employ adequate control codes mapped to power symbols (power levels) defined in the write strategy for data recording, a minimum transmission pulse length is guaranteed to correspond to more than one power symbol period. In this way, the high-speed recording of any optical storage medium, such as a Blu-ray disc or a digital versatile disc, can benefit from the exemplary control signal transmission scheme of the present invention to thereby achieve better write quality.