Methods for fabricating a memory device including a dual bit memory cell

Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.

TECHNICAL FIELD

The present invention generally relates to methods for fabricating memory devices, and more particularly relates to methods for fabricating memory devices that include a dual bit memory cell.

BACKGROUND

One form of semiconductor memory is a nonvolatile memory in which the memory state of a memory cell is determined by whether or not an electrical charge is stored on a charge storage layer built into the gate structure of a field effect transistor. To enhance the storage capacity of such a nonvolatile memory, two storage nodes can be built into each memory cell. The storage nodes are associated with locations in charge storage layers at opposite sides of the gate structure. As the capacity of semiconductor memories increases, the size of each individual device used to implement the memory shrinks in size. With a memory that uses dual storage nodes per memory cell, the reduction in device size means that the spacing between the two storage nodes of a memory cell decreases. As the spacing between storage nodes decreases, problems arise with respect to the reliability and retention of the memory data. Charge stored in one memory node of the memory cell may leak through the gate structure to the other memory node to corrupt the memory stored at that other memory node. Additionally, as device size decreases, programming of one memory node can disturb the data stored in the other memory node due to relatively wide charge distributions in the charge storage layer. Such problems limit the possible choices for erasing such dual bit memory cells.

Accordingly, it is desirable to provide methods for fabricating semiconductor memory devices that have enhanced isolation between memory storage nodes of a dual bit memory cell. In addition, it is desirable to provide methods for fabricating semiconductor memory devices in which a gate insulator separating two memory storage nodes can be formed independently of the insulators of the charge storage node. Additionally, it is desirable to provide methods for fabricating dual bit memory cell devices that can be erased by Fowler-Nordheim (FN) tunneling for less power consumption. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

BRIEF SUMMARY

Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.

DETAILED DESCRIPTION

FIG. 1illustrates schematically, in cross section, a non-volatile memory device20that includes a plurality of dual bit memory cells22fabricated in accordance with an embodiment of the invention. Although portions of only four dual bit memory cells are illustrated, those of skill in the art will appreciate that memory device20may include a large number of such cells. Each of dual bit memory cells22includes a central gate electrode24that overlies a gate dielectric26formed at a surface28of a semiconductor substrate30. A first memory storage node32is formed at one side of gate dielectric26and a second memory storage node34is formed at the opposite side of the gate dielectric. Each of the memory storage nodes includes, in accordance with one embodiment of the invention, a thin tunnel dielectric layer36, a charge storage layer38, a blocking dielectric layer40and a control gate42. A conductive word line44is coupled to the central gate electrode and the control gates of each of a plurality of memory cells in a row of memory device20. Alternating first bit lines46and second bit lines48are formed in the semiconductor substrate in the semiconductor substrate in alignment with the charge storage nodes. The bit lines are shared between adjacent memory cells.

FIGS. 2-12schematically illustrate, in cross section, method steps for fabricating a memory device such as memory device20in accordance with various embodiments of the invention. Many of the steps employed in the fabrication of semiconductor devices are well known and so, in the interest of brevity, some of those conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details.

The method begins, as illustrated inFIG. 2, with a semiconductor substrate60, preferably a silicon substrate, at the surface of which is formed a gate dielectric layer62. A layer of conductive gate electrode forming material64is deposited on the gate dielectric layer. The conductive gate electrode forming material is preferably a layer of polycrystalline silicon, and the layer will hereinafter be referred to, for convenience but without limitation, as a layer of polycrystalline silicon. Although not illustrated, a layer of hard mask material may be deposited on the layer of polycrystalline silicon. Gate dielectric layer62is preferably a thermally grown layer of silicon dioxide having a thickness of about 5-30 nanometers (nm), although the layer can be formed of other dielectric materials that are grown or deposited at surface66of the semiconductor substrate. As is well known, dielectric materials can be deposited, for example, by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The layer of polycrystalline silicon can be deposited by, for example, LPCVD by the reduction of silane (SiH4) or other silicon source material and can be deposited either as an undoped or as an impurity doped layer. The layer of polycrystalline silicon preferably has a thickness of about 30-120 nm.

Semiconductor substrate60will hereinafter be referred to, for convenience of discussion but without limitation, as a silicon substrate. As used herein, the term “silicon substrate” will be used to encompass the relatively pure or lightly impurity doped monocrystalline silicon materials typically used in the semiconductor industry as well as silicon admixed with other elements such as germanium, carbon, and the like to form substantially monocrystalline semiconductor material. The silicon substrate can be a bulk silicon wafer as illustrated or can be a thin layer of silicon on an insulator (SOI) that, in turn is supported by a semiconductor carrier substrate.

As illustrate inFIG. 3, polycrystalline silicon layer64and gate dielectric layer62are patterned and etched to form a central gate electrode68and gate dielectric70for each memory cell22of semiconductor device20. The polycrystalline silicon and gate dielectric layer can be etched using conventional photolithography and etch techniques.

In accordance with one embodiment of the invention a layer of oxide72is deposited over the gate electrodes and gate dielectric and a layer of charge storage material74is deposited over the layer of oxide. A further charge barrier layer of oxide76is deposited over the layer of charge storage material with the three layers forming an O—R—O layered storage node structure77as illustrated inFIG. 4where “R” indicates a generic charge storage material. Although described for convenience as a deposited oxide layer, layer of oxide72(the first “O” of O—R—O) also can be a thermally grown layer of silicon dioxide or can be formed of a dielectric material other than an oxide. Layer of oxide72preferably is preferably a tunneling layer having a thickness of about 3-12 nm that allows tunneling of charge carriers between the semiconductor substrate and the charge storage layer. In accordance with an embodiment of the invention, layer72is formed independently of layer70of gate dielectric. By forming the two layers independently, the thickness of the two layers and their composition can be independently specified. Independently forming layer72and layer70has beneficial implications for allowing Fowler-Nordheim erasing of the memory cells as explained below.

Charge storage layer74can be a deposited layer of silicon nitride, silicon rich silicon nitride, polycrystalline silicon, or other charge storage material. Silicon rich silicon nitride is a silicon nitride having a silicon content greater than the silicon content of stoichiometric silicon nitride. Silicon rich nitride is more conductive than stoichiometric silicon nitride and tends to have shallower trap energy levels and higher trap density, both of which allow electrons to move easily to enable Fowler-Nordheim erase of the memory storage node. The charge storage layer can be deposited, for example by LPCVD to a thickness of preferably about 4-12 nm. If the charge storage layer is silicon nitride or silicon rich silicon nitride, the layer can be deposited, for example, by the reaction of dichlorosilane (SiH2Cl2) and ammonia. If the charge storage layer is polycrystalline silicon, the layer can be deposited by, for example, the reduction of silane. Charge barrier layer76(the second “O” of O—R—O) can be a silicon oxide or a high dielectric constant (high-K) insulator such as HfSiO, or the like. Preferably the layer is deposited by LPCVD to a thickness of about 4-15 nm. The charge barrier layer can also be formed of a layer of silicon oxide together with a layer of high-K dielectric material (not illustrated).

The method continues, in accordance with an embodiment of the invention by the deposition of a layer of conductive material78over charge barrier layer76as illustrated inFIG. 5. Preferably the layer of conductive material is a layer of polycrystalline silicon, and the layer will hereinafter be referred to, for convenience of description but without limitation, as a layer of polycrystalline silicon. The layer of polycrystalline silicon is deposited to a thickness sufficient to substantially fill the spaces between gate electrodes68. Preferably the layer of polycrystalline silicon is deposited as a doped layer of polycrystalline silicon by the addition of an impurity dopant species such as arsenic to the reactants used to deposit the layer.

As illustrated inFIG. 6, layer of polycrystalline silicon78is etched back to expose a portion80of layered structure72,74,76at a sidewall81of central gate electrode68. A portion of sidewall81and portion80of the layered structure thus extend above surface82of the etched polycrystalline silicon layer78. The polycrystalline silicon layer can be etched, for example, by plasma etching in a Cl or HBr/O2chemistry.

In accordance with an embodiment of the invention a layer of silicon nitride or other sidewall spacer forming material is deposited over the etched back polycrystalline silicon layer and exposed portion80of the layered structure on sidewall81. The sidewall spacer forming material is anisotropically etched, for example by reactive ion etching (RIE) in a CHF3, CF4, or SF6chemistry to form sidewall spacers84on exposed portion80of the layered structure and adjacent sidewalls81of the central gate electrodes as illustrated inFIG. 7. The sidewall spacers expose a portion86of surface82of etched back polycrystalline silicon layer78.

Sidewall spacers84are used as an etch mask to etch the exposed portion of polycrystalline silicon layer78, the layered structure overlying the top of central gate electrode68and the portion of layered structure77subsequently exposed after the etching of layer78. The etching also removes a portion of the layered structure along sidewalls81. The etching can be accomplished, for example by plasma etching in a Cl or HBr/O2chemistry to etch the polycrystalline silicon and in a CHF3, CF4, or SF6chemistry to etch the layered O—R—O structure. The etching exposes the top of central gate electrode68and a portion90of surface66of the semiconductor substrate. The etching also forms control gates92and94adjacent opposite sides96and98, respectively, of central gate electrode68and overlying a charge storage node portion79of layered structure77as illustrated inFIG. 8.

As illustrated inFIG. 9, sidewall spacers84are also used as an ion implantation mask and conductivity determining ions are implanted into exposed portions90of the semiconductor substrate as indicated by arrows100to form bit lines102and104. The bit lines are formed adjacent to and aligned with the memory storage nodes. Bit lines are shared between adjacent memory cells. The ion implantation also impurity dopes central gate electrodes68. The implanted ions can be arsenic or phosphorus to form N-type bit lines. Those of skill in the art will understand that additional ion implantations, either N-type or P-type, may also be used to dope the channel region of the memory storage cell to control threshold voltage, punch through voltage, and the like.

The method continues by the deposition of a dielectric layer110. The dielectric layer is deposited to a thickness at least sufficient to fill the spaces between the gate electrode structures as illustrated inFIG. 10. Layer110can be, for example, a layer of silicon oxide deposited by a high temperature (HTO) deposition process, a high density plasma (HDP) deposition process, or by an LPCVD or PECVD process using, for example, tetraethylorthosilicate (TEOS) as a reactant source. The resultant structure, if the insulator is deposited by an HTO process, is illustrated inFIG. 10and the following figures. The topography of layer110would be somewhat different, as would be understood by those of skill in the art, if the layer is deposited by a HDP process.

In accordance with one embodiment of the invention dielectric layer110is etched back or is polished back, for example by a CMP process, to a thickness about the same as the height of or slightly less than the height of central gate electrodes68. In a CMP process the silicon nitride sidewall spacers can be used as a polish stop. The CMP process can be followed by a chemical etch. Following the etch back or CMP step, sidewall spacers84and a portion of silicon nitride or silicon rich silicon nitride portion74of layered structure77are removed, for example by etching in hot phosphoric acid (H3PO4). Layers72and76of the layered O—R—O structure can then be etched in a dilute hydrofluoric acid solution to reduce the height of the layered structure along sidewall81(or respectively96and98) of central gate electrode68as illustrated inFIG. 11.

A further layer of conductive material, preferably polycrystalline silicon, is deposited onto the etched back dielectric layer110and in contact with central gates68and control gates92and94. The polycrystalline silicon can be deposited as an impurity doped layer or can be deposited as an undoped layer that is subsequently impurity doped. The further layer of conductive material is photolithographically patterned and etched to form a word line120coupling all of the control gates and central gate electrodes in a row as illustrated inFIG. 12. Those of skill in the art will understand that other processing, either before, during, or after the above described method steps, can be used to form the other devices and interconnects used to implement the remainder of the memory device.

In this structure, in accordance with an embodiment of the invention, central gate electrode68overlies a gate dielectric layer70. On either side of central gate electrode68are control gates92and94, and each of the control gates overlies a layered structure charge storage node structure79(originally part of layered structure77) that includes a tunnel dielectric72, a charge storage layer74, and a charge barrier layer76. Gate dielectric layer70and tunnel dielectric layer72are formed independently and can be formed of different materials and can have different thicknesses. Charge storage nodes79of a memory cell22and the charge storage layers74of those nodes are separated by gate dielectric70. Prior art dual bit memory storage cells relied upon a continuous charge storage layer with opposite extremities of the layer able to independently store data in the form of stored charge. Unfortunately such prior art structures were susceptible to problems relating to reliability and data retention, especially if the charge storage layer was formed of the slightly conductive silicon rich silicon nitride, because charge could leak across the gate structure from one storage node site to the other. These problems were especially prevalent as a result of repeated cycling of program, erase, and read cycles. Separating the charge storage nodes by an independently formed, relatively thick (in comparison to the tunnel dielectric) gate dielectric avoids the problem of charge leakage or spillage from one storage node to the other. In addition, the memory device fabricated in accordance with the various embodiments of the invention can be effectively erased by Fowler-Nordheim tunneling. FN erasing is desirable because such erasing is faster and requires less power. A FN erase cycle requires the application of relatively high voltages to the word line. In prior art structures such high voltages might cause injection through the central gate dielectric which, in turn, might cause data disturb in the adjacent memory storage node as well as in the memory storage node intended to be erased. Devices fabricated in accordance with the invention are able to be FN erased because the central gate dielectric is relatively thicker that the tunnel dielectric of the memory storage nodes, and that under erase conditions tunneling can occur through the tunnel dielectrics, but there is no charge injection through the thicker central gate dielectric.