Integration of word line switches with word line contact via structures

Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact via structures to the electrically conductive layers for word lines. Via cavities in a dielectric material portion overlying stepped surfaces of the electrically conductive layers can be filled with a conductive material and recessed to form contact via structures. After forming lower active regions in the recesses, gate electrodes can be formed and patterned to form openings in areas overlying the contact via structures. Gate dielectrics can be formed on the sidewalls of the openings, and transistor channels can be formed inside the openings of the gate electrodes. Upper active regions can be formed over the transistor channels.

FIELD

The present disclosure relates generally to the field of semiconductor devices and specifically to three-dimensional non-volatile memory devices, such as vertical NAND strings and other three-dimensional devices, and methods of making the same.

BACKGROUND

Recently, ultra high density storage devices have been proposed using a three-dimensional (3D) stacked memory stack structure sometimes referred to as a Bit Cost Scalable (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductive and dielectric layers. A memory opening is formed through the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory opening with appropriate materials. A straight NAND string extends in one memory opening, while a pipe- or U-shaped NAND string (p-BiCS) includes a pair of vertical columns of memory cells. Control gates of the memory cells may be provided by the conductive layers.

SUMMARY

According to an aspect of the present disclosure, a memory device comprises an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the electrically conductive layers form stepped surfaces, memory stack structures extending through the alternating stack and including a memory film and a vertical semiconductor channel, and vertical field effect transistors which are located over the stepped surfaces and which electrically contact a respective electrically conductive layer.

According to another aspect of the present disclosure, a method of making a memory device includes forming memory stack structures that extend through an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the memory stack structure includes a memory film and a vertical semiconductor channel, forming contact via structures on the electrically conductive layer, and forming vertical field effect transistors on respective contact via structures.

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed to three-dimensional non-volatile memory devices, such as vertical NAND strings and other three-dimensional devices, and methods of making the same, the various aspects of which are described below. The embodiments of the disclosure can be employed to form various semiconductor devices such as three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings. The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure.

The various three dimensional memory devices of the present disclosure include a monolithic three-dimensional NAND string memory device, and can be fabricated employing the various embodiments described herein. The monolithic three dimensional NAND string is located in a monolithic, three dimensional array of NAND strings located over the substrate. At least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings.

Referring toFIG. 1, a word line decoder circuitry310including vertical field effect transistors315for a three-dimensional memory device is shown. The vertical field effect transistors315have a source to drain direction which is substantially perpendicular to the top surface7of the substrate (9,10) shown inFIG. 2. In other words, one of source or drain of a vertical transistor is located above the channel and the other one of the source or drain of the vertical transistor. The vertical transistors315may be word line and control gate electrode switching transistors. The three-dimensional memory device can include a three-dimensional memory cell array100that includes m vertical NAND strings101, where m is an integer that may range from 64 to 1024, for example. A level shifter circuitry54A can be employed to provide two output signals via nodes (e.g., lines) N10, N20to the vertical field effect transistors.

Each vertical NAND string101is connected to a bit line BLi for which the index i runs from 1 to m at the drain side, and connected to a common source electrode labeled “Cell-Source.” Each of the m vertical NAND strings can include K memory elements Mj that are vertically stacked and controlled by respective control gate electrodes, for which the index j runs from 1 to K.FIG. 1illustrates an example in which K is 8. However, K can be any suitable integer, such as 8 to 1024, such as 64 to 256. Read, programming, and erase operations on the memory elements can be performed employing K control gate electrodes CG(j) for which the index j runs from 1 to K. Select gate electrodes SGp where p is any suitable integer (e.g., SG1, SG2) can be provided above, and/or below, the memory elements in each vertical NAND string. The select gate electrodes comprise electrodes of drain side select transistors (e.g., S1) or source side select transistors (e.g., S2)

The vertical field effect transistors QNt (where t is any suitable integer) are formed over word line contact via structures81that contact electrically conductive layers that function as the word lines and select gate electrodes of the vertical NAND strings101. The number of the vertical field effect transistors QNt may be at lease the sum of the total number of word lines and select gate electrodes. First active regions (which may be source regions or drain regions) of the vertical field effect transistors QNt can be electrically shorted to respective underlying word line contact via structures81. Second active regions (which may be drain regions or source regions) of the vertical field effect transistors QNt can be electrically shorted to various control nodes, which can include control gate output nodes CGDj (for which the index j runs from 1 to K), at least one source-side select gate node SGS, at least one drain-side select gate node SGD, and a source and drain select gate node SGDS. The vertical field effect transistors QNt can include one or more vertical field effect transistors that controls select gate electrodes (such as QN0, QN9, QN10and QN11). Node N10connects to the gate electrodes of all of the switching transistors shown inFIG. 1except transistors QN9and QN11, while node N20connects to the gate electrodes of transistors QN9and QN11.

The three-dimensional memory cell array100can be formed prior to formatting the vertical field effect transistors QNt. Referring toFIG. 2, an exemplary structure including a three-dimensional memory cell array100, a peripheral device region200(which can include the level shifter circuitry54A and the various control nodes (CGDj, SGS, SGD, SGDS)), and a stepped terrace region300including terraces of electrically conductive layers46on which the word line contact via structures81can be subsequently formed. In an embodiment, the peripheral device region200includes a substrate level peripheral device region220containing one or more devices, such as capacitors, diodes or transistors201located on or in the substrate (9,10). The transistors201may include the transistors of the data latch/level shifter circuitry54A. Thus, the word line/row driver circuitry is split into a data latch/level shifter/other row driver circuitry portion54A/220which is located in or on the substrate, and the word line switching transistors315which are located above the stepped word line contact region300, which reduces the area and the die size of the device.

Referring toFIG. 2, an exemplary structure according to an embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a device structure containing vertical NAND memory devices. The exemplary structure includes a substrate, which can be a semiconductor substrate. The substrate can include a substrate semiconductor layer9. The substrate semiconductor layer9is a semiconductor material layer, and can include at least one elemental semiconductor material, at least one III-V compound semiconductor material (e.g., single crystal silicon wafer), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface7, which can be, for example, a topmost surface of the substrate semiconductor layer9. The major surface7can be a semiconductor surface. In one embodiment, the major surface7can be a single crystalline semiconductor surface.

As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm, and is capable of producing a doped material having electrical resistivity in a range from 1.0 S/cm to 1.0×105S/cm upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105S/cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−6S/cm. All measurements for electrical conductivities are made at the standard condition. Optionally, at least one doped well (not expressly shown) can be formed within the substrate semiconductor layer9.

At least one semiconductor device for a peripheral circuitry can be formed on a portion of the substrate semiconductor layer9. The at least one semiconductor device can include, for example, field effect transistors201. For example, at least one shallow trench isolation structure120can be formed by etching portions of the substrate semiconductor layer9and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer9, and can be subsequently patterned to form at least one gate structure (150,152,154,158), each of which can include a gate dielectric150, at least one gate electrode (152,154), and a gate cap dielectric158. A gate electrode (152,154) may include a stack of a first gate electrode portion152and a second gate electrode portion154. At least one gate spacer156can be formed around the at least one gate structure (150,152,154,158) by depositing and anisotropically etching a conformal dielectric layer. Active regions130can be formed in upper portions of the substrate semiconductor layer9, for example, by introducing electrical dopants employing the at least one gate structure (150,152,154,158) as masking structures. Additional masks may be employed as needed. The active region130can include source regions and drain regions of field effect transistors. A first dielectric liner161and a second dielectric liner162can be optionally formed. Each of the first and second dielectric liners (161,162) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner161can be a silicon oxide layer, and the second dielectric liner162can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device.

A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer170. In one embodiment the planarized top surface of the planarization dielectric layer170can be coplanar with a top surface of the dielectric liners (161,162). Subsequently, the planarization dielectric layer170and the dielectric liners (161,162) can be removed from an area to physically expose a top surface of the substrate semiconductor layer9.

An optional semiconductor material layer10can be formed on the top surface of the substrate semiconductor layer9by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The deposited semiconductor material can be the same as, or can be different from, the semiconductor material of the substrate semiconductor layer9. The deposited semiconductor material can be any material that can be employed for the semiconductor substrate layer9as described above. The single crystalline semiconductor material of the semiconductor material layer10can be in epitaxial alignment with the single crystalline structure of the substrate semiconductor layer9. Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer170can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer10can have a top surface that is coplanar with the top surface of the planarization dielectric layer170.

The region including the semiconductor devices is herein referred to as a peripheral device region200. The peripheral device region200can include various peripheral devices needed to operate the memory devices of the present disclosure, and can include components of the word line driver/row driver circuitry (e.g., level shifter circuitry or other row driver circuitry) ofFIG. 1other than the vertical field effect transistors315which are used as word line and select gate electrode switches.

Referring toFIGS. 3A and 3B, a gate dielectric layer12can be optionally formed above the semiconductor material layer10and the planarization dielectric layer170. The gate dielectric layer12can be, for example, silicon oxide layer. The thickness of the gate dielectric layer12can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed.

Each first material layer includes a first material, and each second material layer includes a second material that is different from the first material. In one embodiment, each first material layer can be an insulating layer32, and each second material layer can be a sacrificial material layer. In this case, the stack can include an alternating plurality of insulating layers32and sacrificial material layers42, and constitutes a prototype stack of alternating layers comprising insulating layers32and sacrificial material layers42. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein. The sacrificial material layers42(which are spacer material layers) are subsequently replaced with control gate electrodes, source select gate electrodes, and drain select gate electrodes for a NAND string.

In one embodiment, the insulating layers32can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The first material of the insulating layers32can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the insulating layers32, tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the sacrificial material layers42can be formed, for example, CVD or atomic layer deposition (ALD).

The sacrificial material layers42can be suitably patterned so that conductive material portions to be subsequently formed by replacement of the sacrificial material layers42can function as electrically conductive electrodes, such as the control gate electrodes of the monolithic three-dimensional NAND string memory devices to be subsequently formed. The sacrificial material layers42may comprise a portion having a strip shape extending substantially parallel to the major surface7of the substrate.

Optionally, an insulating cap layer70can be formed over the alternating stack (32,42). The insulating cap layer70includes a dielectric material that is different from the material of the sacrificial material layers42. In one embodiment, the insulating cap layer70can include a dielectric material that can be employed for the insulating layers32as described above. The insulating cap layer70can have a greater thickness than each of the insulating layers32. The insulating cap layer70can be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer70can be a silicon oxide layer.

A lithographic material stack (not shown) including at least a photoresist layer can be formed over the insulating cap layer70and the alternating stack (32,42), and can be lithographically patterned to form openings therein. The pattern in the lithographic material stack can be transferred through the insulating cap layer70and through entirety of the alternating stack (32,42) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the alternating stack (32,42) underlying the openings in the patterned lithographic material stack are etched to form memory openings49. In other words, the transfer of the pattern in the patterned lithographic material stack through the alternating stack (32,42) forms the memory openings49that extend through the alternating stack (32,42). The chemistry of the anisotropic etch process employed to etch through the materials of the alternating stack (32,42) can alternate to optimize etching of the first and second materials in the alternating stack (32,42). The anisotropic etch can be, for example, a series of reactive ion etches. Optionally, the gate dielectric layer12may be used as an etch stop layer between the alternating stack (32,42) and the substrate. The sidewalls of the memory openings49can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing.

The memory openings49are formed through the gate dielectric layer12so that the memory openings49extend from the top surface of the alternating stack (32,42) to at least the top surface of the semiconductor material layer10. In one embodiment, an overetch into the semiconductor material layer10may be optionally performed after the top surface of the semiconductor material layer10is physically exposed at a bottom of each memory opening49. The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the semiconductor material layer10may be vertically offset from the undressed top surfaces of the semiconductor material layer10by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surface of each memory opening49can be coplanar with the topmost surface of the semiconductor material layer10. Each of the memory openings49can include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. The region in which the array of memory openings49is formed is herein referred to as a device region. The substrate semiconductor layer9and the semiconductor material layer10collectively constitutes a substrate (9,10), which can be a semiconductor substrate. Alternatively, the semiconductor material layer10may be omitted, and the memory openings49can be extend to a top surface of the semiconductor material layer10.

Each memory opening49extends through the insulating cap layer70, the alternating stack (32,42), the gate dielectric layer12, and optionally into an upper portion of the semiconductor material layer10. The recess depth of the bottom surface of each memory opening with respect to the top surface of the semiconductor material layer10can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the sacrificial material layers42can be laterally recessed partially to form lateral recesses (not shown), for example, by an isotropic etch.

Referring toFIG. 4, an optional epitaxial channel portion11can be formed at the bottom portion of each memory opening49, for example, by selective epitaxy. Each epitaxial channel portion11comprises a single crystalline semiconductor material in epitaxial alignment with the single crystalline semiconductor material of the semiconductor material layer10. In one embodiment, the epitaxial channel portion11can be doped with electrical dopants of the same conductivity type as the semiconductor material layer10. In one embodiment, the top surface of each epitaxial channel portion11can be formed above a horizontal plane including the top surface of a sacrificial material layer42. In this case, at least one source select gate electrode can be subsequently formed by replacing each sacrificial material layer42located below the horizontal plane including the top surfaces of the epitaxial channel portions11with a respective conductive material layer.

A blocking dielectric layer52and a charge trapping layer54can be sequentially deposited in the memory openings49. The blocking dielectric layer52can include a single dielectric material layer or a layer stack of multiple dielectric material layers. The blocking dielectric layer52can be deposited on the sidewalls of each memory opening49by a conformal deposition method. The blocking dielectric layer52can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the blocking dielectric layer52can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. The blocking dielectric layer52can subsequently function as a dielectric material portion that blocks leakage of stored electrical charges to control gate electrodes.

In one embodiment, the blocking dielectric layer52includes a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer52can include a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than the dielectric constant of silicon nitride. Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. In one embodiment, the blocking dielectric layer52includes aluminum oxide.

Alternatively or additionally, the blocking dielectric layer52can include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer52can include silicon oxide. The blocking dielectric layer52can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the blocking dielectric layer52can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed.

Subsequently, the charge trapping layer54can be deposited as a continuous material layer over the blocking dielectric layer52. In one embodiment, the charge trapping layer54can be deposited as a conformal layer having a substantially same thickness throughout. As used herein, an element has a substantially same thickness throughout if the thickness of the element does not deviate from the average thickness of the element by more than 20% at all locations of the element. In one embodiment, the charge trapping layer54can be a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. In one embodiment, the charge trapping layer54includes a silicon nitride layer.

The charge trapping layer54can be formed as a single charge trapping layer of homogeneous composition, or can include a stack of multiple charge trapping layers. The charge trapping layer54can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the charge trapping layer54can be in a range from 2 nm to 20 nm, although lesser and greater final thicknesses can also be employed.

A tunneling dielectric layer56can be deposited on the physically exposed surfaces of the blocking dielectric layer52and the charge trapping layer54. The tunneling dielectric layer56can be formed directly on the physically exposed inner sidewall of the upper portion of the blocking dielectric layer52and directly on a sidewall of the remaining lower portions of the charge trapping layer54. The tunneling dielectric layer56includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer56can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer56can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer56can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer56can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG. 5, an optional first semiconductor channel layer can be formed on the tunneling dielectric layer56. The first semiconductor channel layer includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer includes amorphous silicon or polysilicon. The first semiconductor channel layer can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed.

The optional first semiconductor channel layer, the tunneling dielectric layer56, the charge trapping layer54, the blocking dielectric layer52are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the first semiconductor channel layer, the tunneling dielectric layer56, the charge trapping layer54, and the blocking dielectric layer52located above the top surface of the insulating cap layer70can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the first semiconductor channel layer, the tunneling dielectric layer56, the charge trapping layer54, and the blocking dielectric layer52at a bottom of each cavity49′ can be removed to form openings in remaining portions thereof.

Each remaining portion of the first semiconductor channel layer constitutes a first semiconductor channel portion. A surface of the epitaxial channel portion11can be physically exposed underneath the opening through the first semiconductor channel portion, the tunneling dielectric layer56, the charge trapping layer54, and the blocking dielectric layer52. Optionally, the physically exposed portion of the epitaxial channel portion11can be vertically recessed. Each tunneling dielectric layer56is surrounded by a charge trapping layer54.

Within each memory opening, a set of the tunneling dielectric layer56, the charge trapping layer54, and the blocking dielectric layer52collectively constitutes a memory film50. In one embodiment, the first semiconductor channel portion, the tunneling dielectric layer56, the charge trapping layer54, and the blocking dielectric layer52can have vertically coincident sidewalls. As used herein, a first surface is “vertically coincident” with a second surface if there exists a vertical plane including both the first surface and the second surface. Such a vertical plane may, or may not, have a horizontal curvature, but does not include any curvature along the vertical direction, i.e., extends straight up and down.

A second semiconductor channel layer can be deposited directly on the semiconductor surface of the epitaxial channel portion11over the substrate (9,10), and directly on the first semiconductor channel portion. The second semiconductor channel layer includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer includes amorphous silicon or polysilicon. The second semiconductor channel layer can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The second semiconductor channel layer may partially fill the cavity49′ in each memory opening, or may fully fill the cavity in each memory opening.

The materials of the first semiconductor channel portion and the second semiconductor channel layer are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel portion and the second semiconductor channel layer.

In case the cavity49′ in each memory opening is not completely filled by the second semiconductor channel layer, a dielectric core layer can be deposited in the cavity49′ to fill any remaining portion of the cavity49′ within each memory opening. The dielectric core layer includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG. 5, the horizontal portion of the dielectric core layer above the insulating cap layer70can be removed, for example, by a recess etch from above the top surface of the insulating cap layer70. Further, the horizontal portion of the second semiconductor channel layer located above the top surface of the insulating cap layer70can be removed by a planarization process, which can employ a recess etch or chemical mechanical planarization (CMP). Each remaining portion of the second semiconductor channel layer within a memory opening constitutes a second semiconductor channel portion.

Each adjoining pair of a first semiconductor channel portion and a second semiconductor channel portion can collectively form a vertical semiconductor channel60through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel60is turned on. A tunneling dielectric layer56is surrounded by a charge trapping layer54, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a blocking dielectric layer52, a charge trapping layer54, and a tunneling dielectric layer56collectively constitute a memory film50, which can store electrical charges with a macroscopic retention time. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.

The top surface of the remaining portion of the dielectric core layer can be further recessed within each memory opening, for example, by a recess etch to a depth that is located between the top surface of the insulating cap layer70and the bottom surface of the insulating cap layer70. Each remaining portion of the dielectric core layer constitutes a dielectric core62. Each vertical semiconductor channel60is formed within a respective memory film50. Each dielectric core62is formed inside a respective vertical semiconductor channel60.

A drain region63can be formed at an upper end of the vertical semiconductor channel60. The drain regions63can be formed by depositing a doped semiconductor material within each recessed region above the dielectric cores62. The doped semiconductor material can be, for example, doped polysilicon formed by at least one of in-situ doping and ion implantation doping or a combination thereof. The highly doped drain regions near the drain side select gates provide a low resistive contact region for a bit line connection. Excess portions of the deposited semiconductor material can be removed from above the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP) or a recess etch to form the drain regions63.

Each set of a memory film50and a vertical semiconductor channel60in a same memory opening constitutes a memory stack structure55. The memory stack structures55are formed through the in-process alternating stack of the insulating layers32and sacrificial material layers42.

Referring toFIG. 6, an optional first contact level dielectric material layer71can be formed over the substrate (9,10). As an optional structure, the first contact level dielectric material layer71may, or may not, be formed. In case the first contact level dielectric material layer71is formed, the first contact level dielectric material layer71includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, porous or non-porous organosilicate glass (OSG), or a combination thereof. If an organosilicate glass is employed, the organosilicate glass may, or may not, be doped with nitrogen. The first contact level dielectric material layer71can be formed over a horizontal plane including the top surface of the insulating cap layer70and the top surfaces of the drain regions63. The first contact level dielectric material layer71can be deposited by chemical vapor deposition, atomic layer deposition (ALD), spin-coating, or a combination thereof. The thickness of the first contact level dielectric material layer71can be in a range from 10 nm to 300 nm, although lesser and greater thicknesses can also be employed.

In one embodiment, the first contact level dielectric material layer71can be formed as a dielectric material layer having a uniform thickness throughout. The first contact level dielectric material layer71may be formed as a single dielectric material layer, or can be formed as a stack of a plurality of dielectric material layers. Alternatively, formation of the first contact level dielectric material layer71may be merged with formation of at least one line level dielectric material layer (not shown). While the present disclosure is described employing an embodiment in which the first contact level dielectric material layer71is a structure separate from an optional second contact level dielectric material layer or at least one line level dielectric material layer to be subsequently deposited, embodiments in which the first contact level dielectric material layer71and at least one line level dielectric material layer are formed at a same processing step, and/or as a same material layer, are expressly contemplated herein.

Optionally, a portion of the alternating stack (32,42) can be removed, for example, by applying and patterning a photoresist layer with an opening and by transferring the pattern of the opening through the alternating stack (32,42) employing an etch such as an anisotropic etch. An optional trench extending through the entire thickness of the alternating stack (32,42) can be formed within an area that includes a peripheral device region200and a portion of a contact region300, which is adjacent to a device region100that includes an array of memory stack structures55. Subsequently, the trench can be filled with an optional dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the first contact level dielectric material layer71by a planarization process such as chemical mechanical planarization and/or a recess etch. The top surfaces of the first contact level dielectric material layer71can be employed as a stopping surface during the planarization. The remaining dielectric material in the trench constitutes a dielectric material portion64.

A stepped cavity can be formed within the contact region300, which can straddle the dielectric material portion64and a portion of the alternating stack (32,42). Alternatively, the dielectric material portion64may be omitted and the stepped cavity69may be formed directly in the stack (32,42). The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the top surface of the substrate (9,10). In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

Referring toFIGS. 7A and 7B, at least one dielectric support pillar7P may be optionally formed through the retro-stepped dielectric material portion65and/or through the first contact level dielectric material layer71and/or through the alternating stack (32,42). The plane A-A′ inFIG. 7Bcorresponds to the plane of the vertical cross-sectional view ofFIG. 7A. In one embodiment, the at least one dielectric support pillar7P can be formed in the contact region300, which is located adjacent to the device region100. The at least one dielectric support pillar7P can be formed, for example, by forming an opening extending through the retro-stepped dielectric material portion65and/or through the alternating stack (32,42) and at least to the top surface of the substrate (9,10), and by filling the opening with a dielectric material that is resistant to the etch chemistry to be employed to remove the sacrificial material layers42.

In one embodiment, the at least one dielectric support pillar can include silicon oxide and/or a dielectric metal oxide such as aluminum oxide. In one embodiment, the portion of the dielectric material that is deposited over the first contact level dielectric material layer71concurrently with deposition of the at least one dielectric support pillar7P can be present over the first contact level dielectric material layer71as a second contact level dielectric material layer73. Each of the at least one dielectric support pillar7P and the second contact level dielectric material layer73is an optional structure. As such, the second contact level dielectric material layer73may, or may not, be present over the insulating cap layer70and the retro-stepped dielectric material portion65. The first contact level dielectric material layer71and the second contact level dielectric material layer73are herein collectively referred to as at least one contact level dielectric material layer (71,73). In one embodiment, the at least one contact level dielectric material layer (71,73) can include both the first and second contact level dielectric material layers (71,73), and optionally include any additional via level dielectric material layer that can be subsequently formed. In another embodiment, the at least one contact level dielectric material layer (71,73) can include only the first contact level dielectric material layer71or the second contact level dielectric material layer73, and optionally include any additional via level dielectric material layer that can be subsequently formed. Alternatively, formation of the first and second contact level dielectric material layers (71,73) may be omitted, and at least one via level dielectric material layer may be subsequently formed, i.e., after formation of a substrate contact via structure.

The second contact level dielectric material layer73and the at least one dielectric support pillar7P can be formed as a single continuous structure of integral construction, i.e., without any material interface therebetween. In another embodiment, the portion of the dielectric material that is deposited over the first contact level dielectric material layer71concurrently with deposition of the at least one dielectric support pillar7P can be removed, for example, by chemical mechanical planarization or a recess etch. In this case, the second contact level dielectric material layer73is not present, and the top surface of the first contact level dielectric material layer71can be physically exposed.

A photoresist layer (not shown) can be applied over the alternating stack (32,42) and/or the retro-stepped dielectric material portion65, and lithographically patterned to form at least one trench. Each of the at least one trench is herein referred to as a backside trench79, i.e., a trench that is located in a different region than the memory stack structures55that are formed in the memory openings (which are referred to as front side openings). Each backside trench79can be formed in an area in which formation of a substrate contact via structure is desired. The trench79may extend through region100or through both regions100and300. The pattern in the photoresist layer can be transferred through the alternating stack (32,42) and/or the retro-stepped dielectric material portion65employing an anisotropic etch to form the at least one backside trench79, which extends at least to the top surface of the substrate (9,10). In one embodiment, the at least one backside trench79can include a source contact opening in which a source contact via structure can be subsequently formed.

Referring toFIG. 8, an etchant that selectively etches the second material of the sacrificial material layers42with respect to the first material of the insulating layers32can be introduced through the at least one backside trench79, for example, employing an etch process. Backside recesses43are formed in volumes from which the sacrificial material layers42are removed.

The removal of the second material of the sacrificial material layers42can be selective to the first material of the insulating layers32, the material of the at least one dielectric support pillar7P, the material of the retro-stepped dielectric material portion65, the semiconductor material of the semiconductor material layer10, and the material of the outermost layer of the memory films50. In one embodiment, the sacrificial material layers42can include silicon nitride, and the materials of the insulating layers32, the at least one dielectric support pillar7P, and the retro-stepped dielectric material portion65can be selected from silicon oxide and dielectric metal oxides. In another embodiment, the sacrificial material layers42can include a semiconductor material such as polysilicon, and the materials of the insulating layers32, the at least one dielectric support pillar7P, and the retro-stepped dielectric material portion65can be selected from silicon oxide, silicon nitride, and dielectric metal oxides. In this case, the depth of the at least one backside trench79can be modified so that the bottommost surface of the at least one backside trench79is located within the gate dielectric layer12, i.e., to avoid physical exposure of the top surface of the semiconductor substrate layer10.

Each of the plurality of backside recesses43can extend substantially parallel to the top surface of the substrate (9,10). A backside recess43can be vertically bounded by a top surface of an underlying insulating layer32and a bottom surface of an overlying insulating layer32. In one embodiment, each backside recess43can have a uniform height throughout. Optionally, a backside blocking dielectric layer can be formed in the backside recesses.

Physically exposed surface portions of the optional epitaxial channel portions11and the semiconductor material layer10can be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and/or plasma conversion can be employed to convert a surface portion of each epitaxial channel portion11into a dielectric spacer116, and to convert each physically exposed surface portion of the semiconductor material layer10into a sacrificial dielectric portion616. In one embodiment, each dielectric spacer116can be topologically homeomorphic to a torus, i.e., generally ring-shaped. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without destroying a hole or forming a new hole into the shape of a torus. The dielectric spacers116include a dielectric material that includes the same semiconductor element as the epitaxial channel portions11and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of the dielectric spacers116is a dielectric material. In one embodiment, the dielectric spacers116can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the epitaxial channel portions11. Likewise, each sacrificial dielectric portion616includes a dielectric material that includes the same semiconductor element as the semiconductor material layer10and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of the sacrificial dielectric portions616is a dielectric material. In one embodiment, the sacrificial dielectric portions616can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the semiconductor material layer10.

Referring toFIG. 9, a backside blocking dielectric layer (not shown) can be optionally formed. The backside blocking dielectric layer, if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the backside recesses43. In case a blocking dielectric layer52is present within each memory opening, the backside blocking dielectric layer is optional. In case a blocking dielectric layer52is omitted, the backside blocking dielectric layer is present.

At least one metallic material can be deposited in the plurality of backside recesses43, on the sidewalls of the at least one the backside trench79, and over the top surface of the second contact level dielectric material layer73. As used herein, a metallic material refers to an electrically conductive material that includes at least one metallic element.

The metallic material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The metallic material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof. Non-limiting exemplary metallic materials that can be deposited in the plurality of backside recesses43include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metallic material can comprise a metal such as tungsten and/or metal nitride. In one embodiment, the metallic material for filling the plurality of backside recesses43can be a combination of titanium nitride layer and a tungsten fill material.

In one embodiment, the metallic material can be deposited by chemical vapor deposition or atomic layer deposition. In one embodiment, the metallic material can be employing at least one fluorine-containing precursor gas as a precursor gas during the deposition process. In one embodiment, the molecule of the at least one fluorine-containing precursor gas cam comprise a compound of at least one tungsten atom and at least one fluorine atom. For example, if the metallic material includes tungsten, WF6and H2can be employed during the deposition process.

A plurality of electrically conductive layers46can be formed in the plurality of backside recesses43, and a continuous metallic material layer46L can be formed on the sidewalls of each backside trench79and over the at least one contact level dielectric material layer (71,73). Thus, each sacrificial material layer42can be replaced with an electrically conductive layer46. A backside cavity79′ is present in the portion of each backside trench79that is not filled with the backside blocking dielectric layer66and the continuous metallic material layer46L.

Referring toFIG. 10, the deposited metallic material of the continuous metallic material layer46L is etched back from the sidewalls of each backside trench79and from above the second contact level dielectric material layer73, for example, by an isotropic wet etch or dry etch or the combination of isotropic wet etch and dry etch. Each remaining portion of the deposited metallic material in the backside recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the sacrificial material layers42are replaced with the electrically conductive layers46.

Each electrically conductive layer46can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer46are the control gate electrodes for the vertical memory devices including the memory stack structures55. In other words, each electrically conductive layer46can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices. Optionally, the sacrificial dielectric portions616can be removed from above the semiconductor material layer10during the last processing step of the anisotropic etch.

In one embodiment, the spacer material layers in the initial alternating stack can include sacrificial material layers42, and the sacrificial material layers42can be replaced with electrically conductive layers46. In this case, the in-process alternating stack of the insulating layers32and sacrificial material layers42is modified during the processing steps ofFIGS. 8-10to form an alternating stack of the insulating layer32and the electrically conductive layers46. In one embodiment, the remaining portions of the charge trapping layer54comprises charge storage regions for a NAND string.

Alternatively, the spacer material layers can be formed as electrically conductive layers46. In this case, the epitaxial channel portions11can be omitted, or can be formed to a lesser height, to avoid electrical shorts with the electrically conductive layers46, and the processing steps ofFIGS. 8-10can be omitted.

Referring toFIG. 11, a source region61can be formed in a surface portion of the substrate (e.g., in the semiconductor material layer10) underneath each backside trench79. Each source region61can be formed by implanting electrical dopants through each backside trench79into a semiconductor portion located on, or within, the substrate (9,10). For example, a source region61may be formed by implantation of dopant atoms into a portion of the semiconductor material layer10through each backside trench79. Alternatively, a source region61can be formed on the substrate (9,10) as a doped semiconductor portion by deposition of a semiconductor material, for example, by selective epitaxy, and by implantation of electrical dopants into the deposited semiconductor portion.

An insulating material layer74can be deposited by a conformal deposition process such as a chemical vapor deposition process. The insulating material layer includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, the insulating material can include undoped silicate glass (USG). The thickness of the insulating material layer can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed.

An anisotropic etch can be performed to remove horizontal portions of the insulating material layer from above the at least one contact level dielectric material layer (71,73) and from a bottom portion of each backside trench79. The anisotropic etch can be a reactive ion etch that etches the dielectric material of the insulating material layer selective to the aluminum oxide material of the continuous conformal aluminum oxide layer. In one embodiment, the reactive ion etch can employ at least one fluorocarbon etchant such as CF4and/or CHF3, and optionally oxygen. Such fluorocarbon-based reactive ion etch chemistries are generally selective to aluminum oxide. Each remaining portion of the insulating material layer constitutes an insulating spacer74.

In case a portion of the backside trench79has a substantially rectangular horizontal cross-sectional area, the insulating spacer74can have a pair of parallel vertical portions laterally spaced from each other by a uniform distance. Further, each parallel vertical portion of the insulating spacer74can have a uniform lateral thickness at a bottom portion and a middle portion. The anisotropic etch can cause formation of tapers at the top portion of each insulating spacer74. In this case, each insulating spacer74can have a tapered profile at a top portion. In other words, the lateral thickness of each insulating spacer74can decrease with a vertical distance from the top surface of the substrate (9,10).

At least one conductive material can be deposited to fill each backside cavity laterally surrounded by a respective insulating spacer74. The at least one conductive material can include, for example, a combination of a conductive metallic nitride (such as TiN, TaN, or WN) that can be employed to form a conductive diffusion barrier layer, and a conductive fill material (such as W, Cu, Al, Ru, Co, and/or a heavily doped conductive semiconductor material). The at least one conductive material can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or a combination thereof. Excess portions of the at least one conductive material can be removed from above the top surface of the at least one contact level dielectric material layer (71,73) by a planarization process, which may employ a recess etch or chemical mechanical planarization (CMP). A contact via structure is formed within each backside trench79, which is herein referred to as a substrate contact via structure76. Each substrate contact via structure76can physically contact a portion of the substrate (9,10,61) such as a source region61of the substrate. In this case, the substrate contact via structure76can be a source contact via structure that can be employed to apply electrical bias to a respective source region61.

Referring toFIG. 12A, contact via cavities69can be formed over the stepped surfaces of the electrically conductive layers46, for example, by application of a photoresist layer, lithographic patterning of the photoresist layer with openings that overlie the terraces of the electrically conductive layers, and transferring the pattern of the photoresist layer through the retro-stepped dielectric material portion65onto top surfaces of the terraces of the electrically conductive layers46. Via cavities having various heights can be formed through the retro-stepped dielectric material layer65. The via cavities are herein referred to as conductive line contact via cavities69.

Referring toFIG. 12B, at least one conductive material can be deposited in the conductive line contact via cavities69. The at least one conductive material can include at least one doped semiconductor material or at least one metallic material. Excess portions of the at least one conductive material above a horizontal plane including a topmost surface of the at least one contact level dielectric material layer (71,73) can be removed by a planarization process, which can employ a recess etch and/or chemical mechanical planarization. In case the at least one conductive material includes a doped semiconductor, then it may comprise heavily doped polysilicon of a first conductivity type (e.g., n-type or p-type) having a dopant concentration of 1.0×1019/cm3to 2.0×1021/cm3. In case the at least one conductive material includes at least one metallic material, then it may comprise a combination of a conductive metallic liner such as TiN, TaN, or WN and a conductive fill material such as W. The at least one conductive material may be vertically recessed within the word line contact via trenches so that remaining portions of the at least one conductive material have top surfaces that are recessed from the topmost surface of the at least one contact level dielectric material layer (71,73). Each remaining portion of the at least one conductive material in the conductive line contact via cavities constitutes a contact via structure81. Each contact via structure81can be formed directly on respective top surfaces of the electrically conductive layers46in a terrace region in which the electrically conductive layers46horizontally extend with different lateral extents. The contact via structures81that contact the electrically conductive layers46that function as word lines constitute word line contact via structures. The contact via structures81that contact the electrically conductive layers46that function as drain select gate electrodes constitute drain select gate contact via structures. The contact via structures81that contact the electrically conductive layers46that function as source select gate electrodes constitute source select gate contact via structures. The top surfaces of the contact via structures81can be recessed from the topmost surface of the at least one contact level dielectric material layer (71,73) by a vertical recess distance, which can be in a range from 20 nm to 100 nm, although lesser and greater vertical recess distances can also be employed.

Referring toFIG. 12C, a doped semiconductor material including electrical dopants can be deposited in the recesses above the contact via structures81, for example, by chemical vapor deposition. The doped semiconductor material can have a p-type doping or an n-type doping. The dopant concentration in the doped semiconductor material can be in a range from 1.0×1016/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The electrical dopants can be introduced into the deposited semiconductor material by in-situ doping or by implantation of the electrical dopants by ion implantation or by plasma doping into intrinsic semiconductor material. Excess portions of the doped semiconductor material can be removed from above the horizontal plane including the topmost surface of the at least one contact level dielectric material layer (71,73) by a planarization process such as chemical mechanical planarization. Each remaining portion of the doped semiconductor material constitutes a lower active region82for a vertical field effect transistor. The lower active region may be at least a portion of a source region or a drain region. For example, if the contact via structures81comprise heavily doped polysilicon of a first conductivity type, then the lower active region may82may comprise a lightly doped polysilicon of the first conductivity type having a dopant concentration of 1.0×1016/cm3to 1.0×1018/cm3to form a so-called “low doped drain” (LDD) source or drain structure (81,82). Each lower active region82can be formed within recesses of the via cavities that overlie the contact via structures81. In one embodiment, the doped semiconductor material comprises doped polysilicon, which may be deposited as polycrystalline material or deposited as an amorphous material and subsequently annealed to become polycrystalline.

In an alternative embodiment, the at least one conductive material employed to form the contact via structures81may include a doped semiconductor material. In this case, contact via structures81and the lower active regions82can be formed as integral structures employing a same deposition and planarization process. In other words, each of the conductive line contact via cavities69can be filled with a doped semiconductor material, and excess portions of the doped semiconductor material may be removed from above the horizontal plane including the topmost surface of the at least one contact level dielectric material layer (71,73). Each remaining portion of the deposited doped semiconductor material can constitute a single doped semiconductor material portion that functions as a combination of a contact structure81and a lower active region82.

Referring toFIG. 12D, patterned conductive material portions can be formed over the lower active regions82by depositing and patterning a conductive material layer. The conductive material layer can include a doped semiconductor material such as doped amorphous silicon or doped polysilicon. The thickness of the conductive material layer is selected to be about the target gate length of the field effect transistors to be formed. For example, the thickness of the conductive material layer can be in a range from 20 nm to 200 nm, although lesser and greater thicknesses can also be employed. The conductive material layer is patterned into discrete conductive material portions to form conductive material portions85′. The conductive material portions85′ are in-process structures that are subsequently patterned further into gate electrodes. The conductive material portions85′ can contact, and cover, the entire top surfaces of the lower active regions82. The conductive material portions85′ are formed over the retro-stepped dielectric material portion65. The contact via structures81extend through the portion65. An optional insulating layer (e.g., silicon oxide layer, not shown) may be formed between layer73and portions85′ to prevent a short circuit between portions82(e.g., source or drain) and85′ (e.g., gate).

Referring toFIG. 12E, a dielectric material layer can be formed over the conductive material portions85′. The dielectric material layer is herein referred to as a transistor level dielectric material layer78because the gate electrodes and upper active regions of vertical field effect transistor are subsequently formed within the transistor level dielectric material layer78. The transistor level dielectric material layer78can include a dielectric material such as undoped silicate glass (i.e., silicon oxide), doped silicate glass, or organosilicate glass. Optionally, the top surface of the transistor level dielectric material layer78can be planarized, for example, by chemical mechanical planarization, or by employing a self-planarizing process for deposition of the dielectric material layer78(such as spin-coating). The thickness of the transistor level dielectric material layer78, as measured above the top surfaces of the conductive material portions85′, can be in a range from 20 nm to 400 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG. 12F, openings89are formed through regions of the transistor level dielectric material layer78and the conductive material portions85′ that overlie the contact via structures81. For example, a photoresist layer (not shown) can be applied over the transistor level dielectric material layer78and lithographically patterned to form openings therein. The openings in the photoresist layer can overlap with the areas of the underlying lower active regions82. The pattern of the openings in the photoresist layer can be transferred through the transistor level dielectric material layer78by an anisotropic etch that employs the patterned photoresist layer as an etch mask. Each opening89extends from the top surface of the transistor level dielectric material layer78to the bottom surfaces of the conductive material portions85′. Each opening89is formed through a respective conductive material portion85′ in areas that overlie an underlying conductive via structure82.

In one embodiment, the dimensions of the openings89are selected such that the areas of the openings89includes at least the entirety of the area of the top surface of the respective underlying lower active region82. In one embodiment, the entire areas of the top surfaces of the lower active regions82can be physically exposed underneath the openings89. Thus, each electrically conductive portion85′ can be electrically isolated from the lower active regions82. The openings89can have substantially vertical sidewalls.

Referring toFIG. 12G, gate dielectrics84can be formed on the sidewalls of the openings89on the conductive material portions85′. Each remaining portion of the conductive material portions85′ constitutes a gate electrode85for a respective vertical field effect transistor. One or more gate electrodes85can be employed as the common gate electrode for a subset of the vertical field effect transistors. In one embodiment, the conductive material portions85′ can include a doped semiconductor material (such as doped polysilicon or doped amorphous silicon), and the gate dielectrics84can be formed by conversion of surface portions of the conductive material portions85′ into a dielectric material. For example, thermal oxidation, thermal nitridation, plasma oxidation, and/or plasma nitridation of the surface portions of the doped semiconductor material of the conductive material portions85′ can be employed to form the gate dielectrics84. Each gate dielectric84can be formed as an annular spacer (i.e., a ring-shaped spacer) having the same height as the height of the gate electrodes85. As such, the gate dielectrics84are self-aligned to the gate electrodes85, and can have top surfaces that are substantially coplanar (i.e., located within the same horizontal plane as) as the top surfaces of the gate electrodes85, and can have bottom surfaces that are substantially coplanar as the bottom surfaces of the gate electrodes85. Alternatively, the gate dielectric84may be deposited into the openings89.

Referring toFIG. 12H, semiconductor fill material portions83′ can be formed within the openings89through the transistor level dielectric material layer78and the gate electrodes85. The semiconductor fill material portions83′ are formed directly on the inner sidewalls of the gate dielectrics84. The semiconductor fill material portions83′ can include an intrinsic semiconductor material or a lightly doped semiconductor material including dopants at a concentration less than 1.0×10′7/cm3, although a greater dopant concentration may be employed in some cases. The dopants may be provided in-situ or implanted into the semiconductor material after deposition. In one embodiment, the conductivity type of the dopants in the semiconductor fill material portions83′ can be the opposite of the conductivity type of the dopants in the lower active regions82. The semiconductor material of the semiconductor fill material portions83′ can be deposited by a conformal deposition process such as chemical vapor deposition. The semiconductor material of the semiconductor fill material portions83′ may be deposited as a polycrystalline semiconductor material, or may be deposited as an amorphous semiconductor material and subsequently annealed to be converted into a polycrystalline semiconductor material. Excess portions of the deposited semiconductor material can be removed from above a horizontal plane including the top surface of the transistor level dielectric material layer78, for example, by chemical mechanical planarization.

Referring toFIG. 12I, optional doped extension regions86can be formed by implanting electrical dopants around, or within, regions of the semiconductor fill material portions83′ that are located above a first horizontal plane including the top surfaces of the gate electrodes85and below a second horizontal plane including the top surface of the transistor level dielectric material layer78. The optional doped extension regions86can have a doping of the same conductivity type as the lower active regions82, and can have the opposite type of doping from portions of the semiconductor fill material portions83′ located adjacent to the gate dielectric84. Upper active regions87can be formed above the doped extension regions86such that each upper active region87adjoins an underlying doped extension region86. Each region87may be heavily doped while each region86may be lightly doped to form the LDD structure of the source or drain. In case the doped extension regions86are not employed, the upper active regions87can extend from the first horizontal plane including the top surfaces of the gate electrodes85to the second horizontal plane including the top surface of the transistor level dielectric material layer78. In one example, the upper active regions87may comprise N+ polysilicon drain regions, regions86may comprise N− polysilicon LDD drain regions, regions83may comprise P− polysilicon channel regions, regions82may comprise N− polysilicon LDD source regions and regions81may comprise vertical N+ polysilicon pillar source regions which contact the word lines or select gate electrodes46.

Each portion of the semiconductor fill material portions83′ located adjacent to the gate dielectric84constitutes a semiconductor channel83of a respective vertical field effect transistor. In one embodiment, the lower active region82of a vertical field effect transistor can be a source region and the upper active region87of the vertical field effect transistor can be a drain region. In another embodiment, the lower active region82of a vertical field effect transistor can be a drain region and the upper active region97of the vertical field effect transistor can be a source region.

Referring toFIG. 12J, a via level dielectric material layer90can be formed over the transistor level dielectric material layer78by deposition of another dielectric material. The dielectric material of the via level dielectric material layer90can include, for example, silicon oxide, organosilicate glass, silicon nitride, and/or nitrogen-doped organosilicate glass. The thickness of the via level dielectric material layer90can be in a range from 100 nm to 500 nm, although lesser and greater thicknesses can also be employed.

Various transistor contact via structures (881,882,887) can be formed through the via level dielectric material layer90to provide electrical contact to the upper active regions87of the vertical field effect transistors and to the gate electrodes85of the field effect transistors. Further, drain contact via structures885can be formed through the via level dielectric material layer90, the transistor level dielectric material layer78, and the at least one contact level dielectric material layer (71,73) to contact the drain regions63of the NAND strings101containing the memory stack structures55.

Referring toFIGS. 13A and 13BandFIG. 1collectively, an exemplary wiring scheme for the various transistor contact via structures (881,882,887) is illustrated. Two level shifter output nodes N10and N20can be connected to the various input nodes of the vertical field effect transistors. In this case, two metal lines98A,98B that extend along a first horizontal direction hd1can be provided over the vertical field effect transistors at a bit line level, or at a line level above the bit line level. The two metal lines98A,98B can be a pair of bus lines that transmit the output signals from the two respective output nodes N10and N20of the level shifter circuitry54A to the gate electrodes85of a subset of the vertical field effect transistors. Thus, each gate electrode85of the subset of the vertical field effect transistors can be electrically biased by a respective signal provided by one of two metal lines98. First-type transistor contact via structures881can be a set of gate contact via structures connected to line98A to transmit a first output signal N10from the level shifter circuitry to first type gate electrodes85of switching transistors QN0to QN8and QN10, and second-type transistor contact via structures882can be a set of the gate contact via structures connected to line98B to transmit a second output signal N20from the level shifter circuitry to second type gate electrodes85of transistors QN9and QN11. Active region contact via structures887can be employed to provide electrical signals to the upper active regions87of the vertical field effect transistors.

Additional metal lines can be formed, which extend along a second horizontal direction hd2that is different from the first horizontal direction hd1. Each upper active region87of the vertical field effect transistors can be electrically shorted to a respective additional metal line. The additional metal lines can be electrically shorted to the various nodes CGDj, SGS, SGD, and SGDS illustrated inFIG. 1.

In one embodiment, the electrically conductive layers46can form stepped surfaces that extend along a first horizontal direction hd1with different lateral extents. The edge98of each stepped surface (i.e., the edge of each terrace) of layer46is shown by a partial line inFIG. 13B. Each gate electrode85of the vertical field effect transistors can be electrically biased by a respective signal from nodes N10or N20provided by one of two metal lines98A,98B that extend along the first horizontal direction hd1. In one embodiment, each upper active region87of the vertical field effect transistors can be biased by metal lines that extend along a second horizontal direction hd2that is different from the first horizontal direction hd1.

According to various embodiments of the present disclosure, a memory device is provided, which comprises an alternating stack of insulating layers32and electrically conductive layers46located over a substrate (9,10); a memory stack structure55extending through the alternating stack and including a memory film50and a vertical semiconductor channel60; contact via structures81in contact with a respective electrically conductive layer46; and vertical field effect transistors including a bottom active region82overlying a respective contact via structure81.

In one embodiment, a subset of the vertical field effect transistors can comprise a common gate electrode85. In one embodiment, each of the subset of the vertical field effect transistors can comprise a cylindrical gate dielectric84contacting a respective inner sidewall of the common gate electrode85and enclosing a transistor channel83. In one embodiment, the common gate electrode85can comprises a semiconductor material and electrical dopant atoms, and each of the vertical field effect transistors can comprise a gate dielectric84including a dielectric oxide of the semiconductor material.

In one embodiment, an insulating cap layer70and contact level dielectric layer(s) (71,73) can overlie the alternating stack (32,46). Each of the vertical field effect transistors can have an interface between a respective transistor channel83and a respective lower active region82within the horizontal plane including the top surface of the contact level dielectric layer(s) (71,73). A transistor level dielectric material layer78can be provided, which laterally surrounds, and overlies, gate electrodes85of the vertical field effect transistors. A via level dielectric material layer90can be provided, which overlies the transistor level dielectric material layer78and through which transistor contact via structures (881,882,887) extend.

In one embodiment, each of the vertical field effect transistors can comprise a transistor channel83that is self-aligned to a respective upper active region87thereof. In one embodiment, the transistor channel83and the overlying upper active region87can have substantially the same horizontal cross-sectional areas at a same location. In one embodiment, at least one transistor channel83of the vertical field effect transistors may be laterally offset from a respective lower active region82due to overlay variations that can be present during the lithographic alignment of the pattern for the openings89through the gate electrodes85to the pattern of the lower active region82.

In one embodiment, the electrically conductive layers46can comprise word lines464for memory elements within the memory stack structure55. The vertical field effect transistors can comprise word line switches that control application of a bias voltage to the word lines464. In one embodiment, the electrically conductive layers46can further comprise at least one select gate electrode (462,466) that controls activation of the memory stack structure55of each NAND string101. The at least one select gate electrode (462,466) can include one or more source side select gate electrodes462, and/or one or more drain side select gate electrodes466. The vertical field effect transistors further comprise at least another select gate electrode switch (i.e., the vertical field effect transistors that are connected to the select gate electrodes (462,466)) that controls application of another bias voltage to the select gate electrode.

Referring toFIGS. 14 and 15, exemplary layouts for a memory device for implementing the vertical field effect transistors of the present disclosure are illustrated. The memory device can include a memory element array100, which can be a three-dimensional array of memory elements. The three-dimensional array can include a two-dimensional array of memory blocks102of vertical NAND strings101, each including a vertical array of memory elements therein.

A memory block102includes common word lines and select gate electrodes for all NAND strings101in the block102. Adjacent blocks102may be separated by the backside trench79which extends through the entire stack (32,46) and separates all select gate electrodes and word lines of adjacent blocks or by a shallow trench which separates only one or more drain select electrodes of adjacent blocks. Thus, adjacent blocks102may share the same word lines and source select gate electrodes, but have different drain select gate electrodes.

At least one word line decoder including a substrate level peripheral device region220(e.g., containing the devices201, such as CMOS devices, of the level shifter/data latch and/or other row driver circuitry in or on the substrate) and region of vertical word line switching field effect transistors315located in the stepped terraced contact region300are provided per memory element array100. The word line decoder (220,315) may be provided only on one side of the memory element array100as illustrated inFIG. 14, or can be provided on two opposing sides of the memory element array100as illustrated inFIG. 15. Alternatively, the vertical word line switching transistors315may be located on opposite row sides of the array100, while the substrate level peripheral device region220may be located on only one side of the array100. Two metal lines98A,98B can be provide per memory block102that shares the same set of source select and drain select gate electrodes to transmit a pair of output signals from nodes N10and N20of the level shifter circuitry54A through the transistors315to the memory block. A bit line decoder240(e.g., sense amplifier) can be located on the column side of the memory element array100. The bit lines BLi are connected to the bit line decoder240. The bit lines extend perpendicular to the lines98A,98B, and to the word lines and select gate electrodes.

In one embodiment, the memory device of the embodiments of the present disclosure can include a monolithic three-dimensional NAND memory device. The electrically conductive layers46can include a first electrically conductive layer located at a first level and a second electrically conductive layer located at a second level that is different from the first level. The first and second electrically conductive layers can comprise, or can be electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device. The substrate (9,10) can comprise a silicon substrate. The monolithic three-dimensional NAND memory device can comprise an array of monolithic three-dimensional NAND strings over the silicon substrate. At least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings can be located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate can contain an integrated circuit comprising a driver circuit for the memory device located thereon. The array of monolithic three-dimensional NAND strings can comprises a plurality of semiconductor channels. At least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate. The array of monolithic three-dimensional NAND strings can comprises a plurality of charge storage elements. Each charge storage element can be located adjacent to a respective one of the plurality of semiconductor channels. The array of monolithic three-dimensional NAND strings can comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate. The plurality of control gate electrodes can comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

The embodiments of the present disclosure containing vertical thin film transistor word line switching transistors315located over the contact region300provide the following non-limiting advantages compared to prior art devices in which the entire word line decoder (including the word line and select gate switching transistors) is formed in or on the substrate.

First, the word line switching transistors315may be formed over the existing word line contact area300which reduces the die size and reduces device cost. Second, the memory block102size may be reduced because complex metal wiring having more than three metal lines is not required. Instead, two metal lines98A,98B which extend in the row direction (i.e., in the word line direction hd1) may be used per block102. Thus, the metal layout becomes very relaxed (i.e., only metal lines98A,98B per block which connect to respective nodes N10, N20). The reduction in the number of metal lines increases the device reliability and speed and decreases the device manufacturing cost.

Since, metal lines are very relaxed (i.e., only two lines98A,98B may be used per memory block102), both row sides of the memory array100may be connected to separate word line switching transistors315located on the opposite row sides of the memory array, as shown inFIG. 15. Thus, the word lines may be driven from both left and right side of the array. This configuration is approximately the same as a configuration where the word line length becomes half in terms of RC delay, which provides almost four times faster word line ramp speed with minimum impact on the die size.