WAFER STACKING METHOD

A wafer stacking method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 112114574, filed on Apr. 19, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The disclosure relates to a semiconductor process, and in particular, relates to a wafer stacking method.

Description of Related Art

At present, a wafer stack structure has been developed. In the wafer stack structure, wafers are bonded together to form the structure. However, after the wafers are bonded, an edge defect (e.g., a crack and/or a bubble) occurs most of the time between two adjacent wafers in the wafer stack structure. Therefore, how to effectively remove the edge defect is an important issue.

SUMMARY

The disclosure provides a wafer stacking method capable of effectively removing an edge defect.

The disclosure provides a wafer stacking method, and the method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.

According to an embodiment of the disclosure, in the wafer stacking method, a machine used for the first edge defect inspection is, for example, a C-mode scanning acoustic microscope (CSAM).

According to an embodiment of the disclosure, the wafer stacking method further includes the following steps. A thinning process is performed on the second wafer after the first trimming process is performed.

According to an embodiment of the disclosure, in the wafer stacking method, the second wafer includes a through-substrate via (TSV). The wafer stacking method further includes the following steps. A portion of the second wafer is removed to expose the through-substrate via. A redistribution layer structure is formed on the second wafer. The redistribution layer structure is electrically connected to the through-substrate via.

According to an embodiment of the disclosure, the wafer stacking method further includes the following steps. A passivation layer is formed on the first wafer stack structure after the first trimming process is performed and before the through-substrate via is exposed.

According to an embodiment of the disclosure, the wafer stacking method further includes the following steps. A third wafer is bonded to the second wafer to form a second wafer stack structure. A second edge defect inspection is performed on the second wafer stack structure to find a second edge defect and measure a second distance in the radial direction between an edge of the second wafer stack structure and an end of the second edge defect away from the edge of the second wafer stack structure. A second trimming process with a range of a second width is performed from the edge of the second wafer stack structure to remove the second edge defect. Herein, the second width is greater than or equal to the second distance.

According to an embodiment of the disclosure, in the wafer stacking method, the second width is greater than the first width.

According to an embodiment of the disclosure, the wafer stacking method further includes the following steps. A thinning process is performed on the third wafer after the second trimming process is performed.

According to an embodiment of the disclosure, in the wafer stacking method, the third wafer includes a through-substrate via. The wafer stacking method further includes the following steps. A portion of the third wafer is removed to expose the through-substrate via. A redistribution layer structure is formed on the third wafer. The redistribution layer structure is electrically connected to the through-substrate via.

According to an embodiment of the disclosure, the wafer stacking method further includes the following steps. A passivation layer is formed on the second wafer stack structure after the second trimming process is performed and before the through-substrate via is exposed.

According to an embodiment of the disclosure, the wafer stacking method further includes the following steps. A fourth wafer is bonded to the third wafer to form a third wafer stack structure. A third edge defect inspection is performed on the third wafer stack structure to find a third edge defect and measure a third distance in the radial direction between an edge of the third wafer stack structure and an end of the third edge defect away from the edge of the third wafer stack structure. A third trimming process with a range of a third width is performed from the edge of the third wafer stack structure to remove the third edge defect. Herein, the third width is greater than or equal to the third distance.

According to an embodiment of the disclosure, in the wafer stacking method, the third width is greater than the second width.

According to an embodiment of the disclosure, the wafer stacking method further includes the following steps. A thinning process is performed on the fourth wafer after the third trimming process is performed.

According to an embodiment of the disclosure, in the wafer stacking method, the fourth wafer includes a through-substrate via. The wafer stacking method further includes the following steps. A portion of the fourth wafer is removed to expose the through-substrate via. A redistribution layer structure is formed on the fourth wafer. The redistribution layer structure is electrically connected to the through-substrate via.

According to an embodiment of the disclosure, the wafer stacking method further includes the following steps. A passivation layer is formed on the third wafer stack structure after the third trimming process is performed and before the through-substrate via is exposed.

According to an embodiment of the disclosure, the wafer stacking method further includes the following steps. A third wafer is provided. A fourth wafer is bonded to the third wafer to form a second wafer stack structure. A second edge defect inspection is performed on the second wafer stack structure to find a second edge defect and measure a second distance in the radial direction between an edge of the second wafer stack structure and an end of the second edge defect away from the edge of the second wafer stack structure. A second trimming process with a range of a second width is performed from the edge of the second wafer stack structure to remove the second edge defect. Herein, the second width is greater than or equal to the second distance.

According to an embodiment of the disclosure, the wafer stacking method further includes the following steps. The fourth wafer is bonded to the second wafer to form a third wafer stack structure. A third edge defect inspection is performed on the third wafer stack structure to find a third edge defect and measure a third distance in the radial direction between an edge of the third wafer stack structure and an end of the third edge defect away from the edge of the third wafer stack structure. A third trimming process with a range of a third width is performed from the edge of the third wafer stack structure to remove the third edge defect. Herein, the third width is greater than or equal to the third distance.

According to an embodiment of the disclosure, in the wafer stacking method, the third width is greater than the first width and the second width.

According to an embodiment of the disclosure, in the wafer stacking method, the first width and the second width are the same width.

According to an embodiment of the disclosure, in the wafer stacking method, the first width and the second width are different widths.

To sum up, in the wafer stacking method provided by the disclosure, the first edge defect inspection is performed on the wafer stack structure including the first wafer and the second wafer to find the first edge defect (e.g., a crack and/or a bubble) and measure the first distance in the radial direction between the edge of the first wafer stack structure and the end of the first edge defect away from the edge of the first wafer stack structure. Next, the first trimming process with the range of the first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance. Therefore, through the wafer stacking method provided by the disclosure, the first edge defect is effectively removed, and the yield is thus further improved.

DESCRIPTION OF THE EMBODIMENTS

Embodiments accompanied with drawings are provided below to further describe the disclosure in details, but the embodiments provided below are not intended to limit the scope of the disclosure. To facilitate understanding, the same components will hereinafter be denoted by the same reference numerals. In addition, the accompanying drawings are provided for illustrative purposes only and are not drawn according to the original dimensions. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.

FIG.1AtoFIG.1Oare cross-sectional views of a wafer stacking method according to some embodiments of the disclosure.

With reference toFIG.1A, a wafer W1is provided. In some embodiments, the wafer W1may include a substrate100, a dielectric layer102, an interconnect structure104, and a bonding pad106. The substrate100may be a semiconductor substrate, such as a silicon substrate. The dielectric layer102is located on the substrate100. Besides, although not shown in the figure, required semiconductor devices (e.g., active devices and/or passive devices) may be provided on the substrate100. In some embodiments, the dielectric layer102may be a multilayer structure. A material of the dielectric layer102is, for example, silicon oxide, silicon nitride, or a combination of the foregoing. The interconnect structure104is located in the dielectric layer102. A material of the interconnect structure104is, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination of the foregoing. Further, a person having ordinary skill in the art can adjust the number of layers and configuration of the interconnection structure104according to needs. The bonding pad106is located in the dielectric layer102and may be electrically connected to the interconnect structure104. A material of the bonding pad106is, for example, a conductive material such as copper.

Next, a wafer W2is bonded to the wafer W1to form a wafer stack structure WS1. In some embodiments, the wafer W2may include a substrate108, a dielectric layer110, an interconnect structure112, a bonding pad114, and a through-substrate via116. The substrate108may be a semiconductor substrate, such as a silicon substrate. The dielectric layer110is located on the substrate108. Besides, although not shown in the figure, required semiconductor devices (e.g., active devices and/or passive devices) may be provided on the substrate108. In some embodiments, the dielectric layer110may be a multilayer structure. A material of the dielectric layer110is, for example, silicon oxide, silicon nitride, or a combination of the foregoing. The interconnect structure112is located in the dielectric layer110. A material of the interconnect structure112is, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination of the foregoing. Further, a person having ordinary skill in the art can adjust the number of layers and configuration of the interconnection structure112according to needs. The bonding pad114is located in the dielectric layer110and may be electrically connected to the interconnect structure112. A material of the bonding pad114is, for example, a conductive material such as copper. The through-substrate via116is located in substrate108and may further be located in dielectric layer110. The through-substrate via116may be electrically connected to the interconnect structure112. A material of the through-substrate via116is, for example, copper, tantalum, tantalum nitride, or a combination of the foregoing.

In some embodiments, the method of bonding the wafer W2to the wafer W1includes a hybrid bonding method. For instance, the bonding pad114may be bonded to the bonding pad106, the dielectric layer110may be bonded to the dielectric layer102, and the wafer W2may be bonded to the wafer W1through the hybrid bonding method, but the disclosure is not limited thereto.

Next, an edge defect inspection DI1is performed on the wafer stack structure WS1to find an edge defect ED1(e.g., a crack and/or a bubble) and measure a distance D1in a radial direction between an edge of the wafer stack structure WS1and an end of the edge defect ED1away from the edge of the wafer stack structure WS1. In some embodiments, the edge defect ED1may be located between the wafer W2and the wafer W1. In some embodiments, the distance D1is, for example, 1 millimeter (mm) to 2.5 millimeters. In some embodiments, a machine used for the edge defect inspection DI1is, for example, a C-mode scanning acoustic microscope (CSAM).

With reference toFIG.1B, a trimming process TP1with a range of a width WD1is performed from the edge of the wafer stack structure WS1to remove the edge defect ED1. Herein, the width WD1is greater than or equal to the distance D1. In this way, the edge defect ED1may be effectively removed, and the yield is thus further improved. In some embodiments, the trimming process TP1may completely remove the edge defect ED1. In some embodiments, the width WD1is, for example, 1 millimeter to 2.5 millimeters. In some embodiments, the trimming process TP1may remove a portion of the substrate108, a portion of the dielectric layer110, a portion of the dielectric layer102, and a portion of the substrate100, but the disclosure is not limited thereto. As long as the trimming process TP1can remove the edge defect ED1, it falls within the scope of the disclosure. In some embodiments, the trimming process TP1is, for example, a grinding process. For instance, a grinder may be used to perform the trimming process TP1.

With reference toFIG.1C, after the trimming process TP1is performed, the wafer W2may be subjected to a thinning process. In some embodiments, the thinning process may be performed on the substrate108. In some embodiments, the thinning process is, for example, a grinding process, a chemical mechanical polishing (CMP) process, or a combination of the foregoing.

With reference toFIG.1D, a passivation layer118may be formed on the wafer stack structure WS1. A material of the passivation layer118is, for example, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the foregoing. A method of forming the passivation layer118is, for example, an atomic layer deposition (ALD) method or a plasma-enhanced chemical vapor deposition (PECVD) method. In some embodiments, after the trimming process TP1is performed, since the passivation layer118covers the wafer stack structure WS1, metal materials (not shown) in the dielectric layer110and the dielectric layer102may be prevented from being exposed, so that cross-contamination is prevented from occurring in subsequent processes. In some other embodiments, the passivation layer118may be omitted.

With reference toFIG.1E, a portion of the wafer W2may be removed to expose the through-substrate via116. In some embodiments, a portion of the substrate108may be removed to expose the through-substrate via116. The method for removing a portion of the wafer W2is, for example, an etch-back method, such as a dry etching method. Besides, during the process of removing a portion of the wafer W2, a portion of the passivation layer118may be removed.

With reference toFIG.1F, a wafer W3may bonded to the wafer W2to form a wafer stack structure WS2. In some embodiments, the wafer W3may include a substrate125, a dielectric layer126, an interconnect structure128, a bonding pad130, and a through-substrate via132. The substrate125may be a semiconductor substrate, such as a silicon substrate. The dielectric layer126is located on the substrate125. Besides, although not shown in the figure, required semiconductor devices (e.g., active devices and/or passive devices) may be provided on the substrate125. In some embodiments, the dielectric layer126may be a multilayer structure. A material of the dielectric layer126is, for example, silicon oxide, silicon nitride, or a combination of the foregoing. The interconnect structure128is located in the dielectric layer126. A material of the interconnect structure128is, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination of the foregoing. Further, a person having ordinary skill in the art can adjust the number of layers and configuration of the interconnection structure128according to needs. The bonding pad130is located in the dielectric layer126and may be electrically connected to the interconnect structure128. A material of the bonding pad130is, for example, a conductive material such as copper. The through-substrate via132is located in substrate125and may further be located in dielectric layer126. The through-substrate via132may be electrically connected to the interconnect structure128. A material of the through-substrate via132is, for example, copper, tantalum, tantalum nitride, or a combination of the foregoing.

In some embodiments, the method of bonding the wafer W3to the wafer W2includes a hybrid bonding method. For instance, the bonding pad130may be bonded to the redistribution layer124, the dielectric layer126may be bonded to the dielectric layer122, and the wafer W3may be bonded to the wafer W2through the hybrid bonding method, but the disclosure is not limited thereto.

Next, an edge defect inspection DI2may be performed on the wafer stack structure WS2to find an edge defect ED2(e.g., a crack and/or a bubble) and measure a distance D2in the radial direction between an edge of the wafer stack structure WS2and an end of the edge defect ED2away from the edge of the wafer stack structure WS2. In some embodiments, the edge defect ED2may be located between the wafer W3and the wafer W2. In some embodiments, the distance D2is, for example, 1.8 millimeters to 3.3 millimeters. In some embodiments, a machine used for the edge defect inspection DI2is, for example, a C-mode scanning acoustic microscope (CSAM).

With reference toFIG.1G, a trimming process TP2with a range of a width WD2is performed from the edge of the wafer stack structure WS2to remove the edge defect ED2. Herein, the width WD2may be greater than or equal to the distance D2. In this way, the edge defect ED2may be effectively removed, and the yield is thus further improved. In some embodiments, the trimming process TP2may completely remove the edge defect ED2. The width WD2of the trimming process TP2may be greater than the width WD1of the trimming process TP1. In some embodiments, the width WD2is, for example, 1.8 millimeters to 3.3 millimeters. In some embodiments, the trimming process TP2may remove a portion of the substrate125, a portion of the dielectric layer126, a portion of the redistribution layer structure120, a portion of the passivation layer118, a portion of the substrate108, a portion of the dielectric layer110, a portion of the dielectric layer102, and a portion of the substrate100, but the disclosure is not limited thereto. As long as the trimming process TP2can remove the edge defect ED2, it falls within the scope of the disclosure. In some embodiments, the trimming process TP2is, for example, a grinding process. For instance, a grinder may be used to perform the trimming process TP2.

With reference toFIG.1H, after the trimming process TP2is performed, the wafer W3may be subjected to a thinning process. In some embodiments, the thinning process may be performed on the substrate125. In some embodiments, the thinning process is, for example, a grinding process, a chemical mechanical polishing process, or a combination of the foregoing.

With reference toFIG.1I, a passivation layer134may be formed on the wafer stack structure WS2. A material of the passivation layer134is, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination of the foregoing. A method of forming the passivation layer134is, for example, an atomic layer deposition method or a plasma-enhanced chemical vapor deposition method. In some embodiments, after the trimming process TP2is performed, since the passivation layer134covers the wafer stack structure WS2, metal materials (not shown) in the dielectric layer126, the dielectric layer122, the dielectric layer110, and the dielectric layer102may be prevented from being exposed, so that cross-contamination is prevented from occurring in subsequent processes. In some other embodiments, the passivation layer134may be omitted.

With reference toFIG.1J, a portion of the wafer W3may be removed to expose the through-substrate via132. In some embodiments, a portion of the substrate125may be removed to expose the through-substrate via132. The method for removing a portion of the wafer W3is, for example, an etch-back method, such as a dry etching method. Besides, during the process of removing a portion of the wafer W3, a portion of the passivation layer134may be removed.

Next, a redistribution layer structure136may be formed on the wafer W3. The redistribution layer structure136may be electrically connected to the through-substrate via132. In some embodiments, the redistribution layer structure136may include a dielectric layer138and a dielectric layer140. The dielectric layer138is located on the wafer W3. A material of the dielectric layer138is, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination of the foregoing. The redistribution layer140is located in the dielectric layer138. The redistribution layer140may be electrically connected to the through-substrate via132. A material of the redistribution layer140is, for example, a conductive material such as copper. Further, the redistribution layer structure136may be fabricated by a conventional method, and description thereof is not repeated herein. Besides, a person having ordinary skill in the art can adjust the number of layers and configuration of the dielectric layer138and the redistribution layer140according to needs.

With reference toFIG.1K, a wafer W4may bonded to the wafer W3to form a wafer stack structure WS3. In some embodiments, the wafer W4may include a substrate142, a dielectric layer144, an interconnect structure146, a bonding pad148, and a through-substrate via150. The substrate142may be a semiconductor substrate, such as a silicon substrate. The dielectric layer144is located on the substrate142. Besides, although not shown in the figure, required semiconductor devices (e.g., active devices and/or passive devices) may be provided on the substrate142. In some embodiments, the dielectric layer144may be a multilayer structure. A material of the dielectric layer144is, for example, silicon oxide, silicon nitride, or a combination of the foregoing. The interconnect structure146is located in the dielectric layer144. A material of the interconnect structure146is, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination of the foregoing. Further, a person having ordinary skill in the art can adjust the number of layers and configuration of the interconnection structure146according to needs. The bonding pad148is located in the dielectric layer144and may be electrically connected to the interconnect structure146. A material of the bonding pad148is, for example, a conductive material such as copper. The through-substrate via150is located in substrate142and may further be located in dielectric layer144. The through-substrate via150may be electrically connected to the interconnect structure146. A material of the through-substrate via150is, for example, copper, tantalum, tantalum nitride, or a combination of the foregoing.

In some embodiments, the method of bonding the wafer W4to the wafer W3includes a hybrid bonding method. For instance, the bonding pad148may be bonded to the redistribution layer140, the dielectric layer144may be bonded to the dielectric layer138, and the wafer W4may be bonded to the wafer W3through the hybrid bonding method, but the disclosure is not limited thereto.

Next, an edge defect inspection DI3may be performed on the wafer stack structure WS3to find an edge defect ED3(e.g., a crack and/or a bubble) and measure a distance D3in the radial direction between an edge of the wafer stack structure WS3and an end of the edge defect ED3away from the edge of the wafer stack structure WS3. In some embodiments, the edge defect ED3may be located between the wafer W4and the wafer W3. In some embodiments, the distance D3is, for example, 2.6 millimeters to 4.1 millimeters. In some embodiments, a machine used for the edge defect inspection DI3is, for example, a C-mode scanning acoustic microscope (CSAM).

With reference toFIG.1L, a trimming process TP3with a range of a width WD3is performed from the edge of the wafer stack structure WS3to remove the edge defect ED3. Herein, the width WD3may be greater than or equal to the distance D3. In this way, the edge defect ED3may be effectively removed, and the yield is thus further improved. In some embodiments, the trimming process TP3may completely remove the edge defect ED3. The width WD3of the trimming process TP2may be greater than the width WD2of the trimming process TP2. In some embodiments, the width WD3is, for example, 2.6 millimeters to 4.1 millimeters. In some embodiments, the trimming process TP3may remove a portion of the substrate142, a portion of the dielectric layer144, a portion of the redistribution layer structure136, a portion of the passivation layer134, a portion of the substrate125, a portion of the dielectric layer126, a portion of the redistribution layer structure120, a portion of the substrate108, a portion of the dielectric layer110, a portion of the dielectric layer102, and a portion of the substrate100, but the disclosure is not limited thereto. As long as the trimming process TP3can remove the edge defect ED3, it falls within the scope of the disclosure. In some embodiments, the trimming process TP3is, for example, a grinding process. For instance, a grinder may be used to perform the trimming process TP3.

With reference toFIG.1M, after the trimming process TP3is performed, the wafer W4may be subjected to a thinning process. In some embodiments, the thinning process may be performed on the substrate142. In some embodiments, the thinning process is, for example, a grinding process, a chemical mechanical polishing process, or a combination of the foregoing.

With reference toFIG.1N, a passivation layer152may be formed on the wafer stack structure WS3. A material of the passivation layer152is, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination of the foregoing. A method of forming the passivation layer152is, for example, an atomic layer deposition method or a plasma-enhanced chemical vapor deposition method. In some embodiments, after the trimming process TP3is performed, since the passivation layer152covers the wafer stack structure WS3, metal materials (not shown) in the dielectric layer144, the dielectric layer138, the dielectric layer126, the dielectric layer122, the dielectric layer110, and the dielectric layer102may be prevented from being exposed, so that cross-contamination is prevented from occurring in subsequent processes. In some other embodiments, the passivation layer152may be omitted.

With reference toFIG.1O, a portion of the wafer W4may be removed to expose the through-substrate via150. In some embodiments, a portion of the substrate142may be removed to expose the through-substrate via150. The method for removing a portion of the wafer W4is, for example, an etch-back method, such as a dry etching method. Besides, during the process of removing a portion of the wafer W4, a portion of the passivation layer152may be removed.

Next, a redistribution layer structure154may be formed on the wafer W4. The redistribution layer structure154may be electrically connected to the through-substrate via150. In some embodiments, the redistribution layer structure154may include a dielectric layer156and a dielectric layer158. The dielectric layer156is located on the wafer W4. A material of the dielectric layer156is, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination of the foregoing. The redistribution layer158is located in the dielectric layer156. A material of the redistribution layer158is, for example, a conductive material such as copper. The redistribution layer158may be electrically connected to the through-substrate via150. Further, the redistribution layer structure154may be fabricated by a conventional method, and description thereof is not repeated herein. Besides, a person having ordinary skill in the art can adjust the number of layers and configuration of the dielectric layer156and the redistribution layer158according to needs.

In this embodiment, adjacent two of the wafers W1to W4may be bonded by a hybrid bonding method, but the disclosure is not limited thereto. In some other embodiments, adjacent two of the wafers W1to W4may be bonded by a fusion bonding method, but description thereof is omitted herein.

Based on the foregoing embodiments, it can be seen that in the wafer stacking method, the edge defect inspection DI1is performed on the wafer stack structure WS1including the wafer W1and the wafer W2to find the edge defect ED1(e.g., a crack and/or a bubble) and measure the distance D1in the radial direction between the edge of the wafer stack structure WS1and the end of the edge defect ED1away from the edge of the wafer stack structure WS1. Next, the trimming process TP1with the range of the width WD1is performed from the edge of the wafer stack structure WS1to remove the edge defect ED1. Herein, the width WD1is greater than or equal to the distance D1. In this way, through the wafer stacking method, the edge defect ED1may be effectively removed, and the yield is thus further improved.

FIG.2AtoFIG.2Kare cross-sectional views of the wafer stacking method according to some other embodiments of the disclosure.

With reference toFIG.2A, a structure as shown inFIG.1Eis provided. In addition, for details of the structure ofFIG.1E, reference may be made to the descriptions ofFIG.1AtoFIG.1E, which will not be repeated herein.

With reference toFIG.2B, a wafer W5may be provided. In some embodiments, the wafer W5may include a substrate200, a dielectric layer202, an interconnect structure204, a bonding pad206, and a through-substrate via207. The substrate200may be a semiconductor substrate, such as a silicon substrate. The dielectric layer202is located on the substrate200. Besides, although not shown in the figure, required semiconductor devices (e.g., active devices and/or passive devices) may be provided on the substrate200. In some embodiments, the dielectric layer202may be a multilayer structure. A material of the dielectric layer202is, for example, silicon oxide, silicon nitride, or a combination of the foregoing. The interconnect structure204is located in the dielectric layer202. A material of the interconnect structure204is, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination of the foregoing. Further, a person having ordinary skill in the art can adjust the number of layers and configuration of the interconnection structure204according to needs. The bonding pad206is located in the dielectric layer202and may be electrically connected to the interconnect structure204. A material of the bonding pad206is, for example, a conductive material such as copper. The through-substrate via207is located in substrate200and may further be located in dielectric layer202. The through-substrate via207may be electrically connected to the interconnect structure204. A material of the through-substrate via207is, for example, copper, tantalum, tantalum nitride, or a combination of the foregoing.

Next, a wafer W6is bonded to the wafer W5to form a wafer stack structure WS4. In some embodiments, the wafer W6may include a substrate208, a dielectric layer210, an interconnect structure212, a bonding pad214, and a through-substrate via216. The substrate208may be a semiconductor substrate, such as a silicon substrate. The dielectric layer210is located on the substrate208. Besides, although not shown in the figure, required semiconductor devices (e.g., active devices and/or passive devices) may be provided on the substrate208. In some embodiments, the dielectric layer210may be a multilayer structure. A material of the dielectric layer210is, for example, silicon oxide, silicon nitride, or a combination of the foregoing. The interconnect structure212is located in the dielectric layer210. A material of the interconnect structure212is, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination of the foregoing. Further, a person having ordinary skill in the art can adjust the number of layers and configuration of the interconnection structure212according to needs. The bonding pad214is located in the dielectric layer210and may be electrically connected to the interconnect structure212. A material of the bonding pad214is, for example, a conductive material such as copper. The through-substrate via216is located in substrate208and may further be located in dielectric layer210. The through-substrate via216may be electrically connected to the interconnect structure212. A material of the through-substrate via216is, for example, copper, tantalum, tantalum nitride, or a combination of the foregoing.

In some embodiments, the method of bonding the wafer W6to the wafer W5includes a hybrid bonding method. For instance, the bonding pad214may be bonded to the bonding pad206, the dielectric layer210may be bonded to the dielectric layer202, and the wafer W6may be bonded to the wafer W5through the hybrid bonding method, but the disclosure is not limited thereto.

Next, an edge defect inspection DI4may be performed on the wafer stack structure WS4to find an edge defect ED4(e.g., a crack and/or a bubble) and measure a distance D4in the radial direction between an edge of the wafer stack structure WS4and an end of the edge defect ED4away from the edge of the wafer stack structure WS4. In some embodiments, the edge defect ED4may be located between the wafer W6and the wafer W5. In some embodiments, the distance D4is, for example, 1 millimeter to 2.5 millimeters. In some embodiments, a machine used for the edge defect inspection DI4is, for example, a C-mode scanning acoustic microscope (CSAM).

With reference toFIG.2C, a trimming process TP4with a range of a width WD4is performed from the edge of the wafer stack structure WS4to remove the edge defect ED4. Herein, the width WD4may be greater than or equal to the distance D4. In this way, the edge defect ED4may be effectively removed, and the yield is thus further improved. In some embodiments, the trimming process TP4may completely remove the edge defect ED4. In some embodiments, the width WD4is, for example, 1 millimeter to 2.5 millimeters. In some embodiments, the width WD1of the trimming process TP1and the width WD4of the trimming process TP4may be the same width. In some other embodiments, the width WD1of the trimming process TP1and the width WD4of the trimming process TP4may be different widths. In some embodiments, the trimming process TP4may remove a portion of the substrate208, a portion of the dielectric layer210, a portion of the dielectric layer202, and a portion of the substrate200, but the disclosure is not limited thereto. As long as the trimming process TP4can remove the edge defect ED4, it falls within the scope of the disclosure. In some embodiments, the trimming process TP4is, for example, a grinding process. For instance, a grinder may be used to perform the trimming process TP4.

With reference toFIG.2D, after the trimming process TP4is performed, the wafer W6may be subjected to a thinning process. In some embodiments, the thinning process may be performed on the substrate208. In some embodiments, the thinning process is, for example, a grinding process, a chemical mechanical polishing process, or a combination of the foregoing.

With reference toFIG.2E, a passivation layer218may be formed on the wafer stack structure WS4. A material of the passivation layer218is, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination of the foregoing. A method of forming the passivation layer218is, for example, an atomic layer deposition method or a plasma-enhanced chemical vapor deposition method. In some embodiments, after the trimming process TP4is performed, since the passivation layer218covers the wafer stack structure WS4, metal materials (not shown) in the dielectric layer210and the dielectric layer202may be prevented from being exposed, so that cross-contamination is prevented from occurring in subsequent processes. In some other embodiments, the passivation layer218may be omitted.

With reference toFIG.2F, a portion of the wafer W6may be removed to expose the through-substrate via216. In some embodiments, a portion of the substrate208may be removed to expose the through-substrate via216. The method for removing a portion of the wafer W6is, for example, an etch-back method, such as a dry etching method. Besides, during the process of removing a portion of the wafer W6, a portion of the passivation layer218may be removed.

With reference toFIG.2G, the wafer W6may bonded to the wafer W2to form a wafer stack structure WS5. In some embodiments, the method of bonding the wafer W6to the wafer W2includes a hybrid bonding method. For instance, the redistribution layer224may be bonded to the redistribution layer124, the dielectric layer222may be bonded to the dielectric layer122, and the wafer W6may be bonded to the wafer W2through the hybrid bonding method, but the disclosure is not limited thereto.

Next, an edge defect inspection DI5may be performed on the wafer stack structure WS5to find an edge defect ED5(e.g., a crack and/or a bubble) and measure a distance D5in the radial direction between an edge of the wafer stack structure WS5and an end of the edge defect ED5away from the edge of the wafer stack structure WS5. In some embodiments, the edge defect ED5may be located between the wafer W6and the wafer W2. In some embodiments, the distance D5is, for example, 1.8 millimeters to 3.3 millimeters. In some embodiments, a machine used for the edge defect inspection DI5is, for example, a C-mode scanning acoustic microscope (CSAM).

With reference toFIG.2H, a trimming process TP5with a range of a width WD5is performed from the edge of the wafer stack structure WS5to remove the edge defect ED5. Herein, the width WD5may be greater than or equal to the distance D5. In this way, the edge defect ED5may be effectively removed, and the yield is thus further improved. In some embodiments, the trimming process TP5may completely remove the edge defect ED5. The width WD5of the trimming process TP5may be greater than the width WD1of the trimming process TP1and the width WD4of the trimming process TP4. In some embodiments, the width WD5is, for example, 1.8 millimeters to 3.3 millimeters. In some embodiments, the trimming process TP5may remove a portion of the substrate200, a portion of the dielectric layer202, a portion of the dielectric layer210, a portion of the substrate208, a portion of the passivation layer218, a portion of the redistribution layer structure220, a portion of the redistribution layer structure120, a portion of the passivation layer118, a portion of the substrate108, a portion of the dielectric layer110, a portion of the dielectric layer102, and a portion of the substrate100, but the disclosure is not limited thereto. As long as the trimming process TP5can remove the edge defect ED5, it falls within the scope of the disclosure. In some embodiments, the trimming process TP5is, for example, a grinding process. For instance, a grinder may be used to perform the trimming process TP5.

With reference toFIG.2I, after the trimming process TP5is performed, the wafer W5may be subjected to a thinning process. In some embodiments, the thinning process may be performed on the substrate200. In some embodiments, the thinning process is, for example, a grinding process, a chemical mechanical polishing process, or a combination of the foregoing.

With reference toFIG.2J, a passivation layer226may be formed on the wafer stack structure WS5. A material of the passivation layer226is, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination of the foregoing. A method of forming the passivation layer226is, for example, an atomic layer deposition method or a plasma-enhanced chemical vapor deposition method. In some embodiments, after the trimming process TP5is performed, since the passivation layer226covers the wafer stack structure WS5, metal materials (not shown) in the dielectric layer202, the dielectric layer210, the dielectric layer222, the dielectric layer122, the dielectric layer110, and the dielectric layer102may be prevented from being exposed, so that cross-contamination is prevented from occurring in subsequent processes. In some other embodiments, the passivation layer226may be omitted.

With reference toFIG.2K, a portion of the wafer W5may be removed to expose the through-substrate via207. In some embodiments, a portion of the substrate200may be removed to expose the through-substrate via207. The method for removing a portion of the wafer W5is, for example, an etch-back method, such as a dry etching method. Besides, during the process of removing a portion of the wafer W5, a portion of the passivation layer226may be removed.

Next, a redistribution layer structure228may be formed on the wafer W5. The redistribution layer structure228may be electrically connected to the through-substrate via207. In some embodiments, the redistribution layer structure228may include a dielectric layer230and a dielectric layer232. The dielectric layer230is located on the wafer W5. A material of the dielectric layer230is, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination of the foregoing. The redistribution layer232is located in the dielectric layer230. The redistribution layer232may be electrically connected to the through-substrate via207. A material of the redistribution layer232is, for example, a conductive material such as copper. Further, the redistribution layer structure228may be fabricated by a conventional method, and description thereof is not repeated herein. Besides, a person having ordinary skill in the art can adjust the number of layers and configuration of the dielectric layer230and the redistribution layer232according to needs.

In this embodiment, adjacent two of the wafer W1, wafer W2, wafer W5, and wafer W6may be bonded by a hybrid bonding method, but the disclosure is not limited thereto. In some other embodiments, adjacent two of the wafer W1, wafer W2, wafer W5, and wafer W6may be bonded by a fusion bonding method, but description thereof is omitted herein.

In view of the foregoing, the wafer stacking method provided by the embodiments includes the edge defect inspections and the trimming processes. As such, an edge defect (e.g., a crack and/or a bubble) may be effectively removed, and the yield may thus be further improved.