Memory cell array with low resistance common source and high current drivability

In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates generally to memory devices, and more particularly, to a memory array which includes a plurality of resistive memory devices.

2. Background Art

FIG. 1is a schematic representation of a portion of a DRAM memory array100proposed for 1-mega-bit class density. The array100includes a plurality of word lines (two shown at WL0, WL1), and a plurality of bit lines (one shown at BL0). The array includes a large number of similar memory cells (two memory cells MC0, MC1shown inFIG. 1). The memory cell MC0includes a capacitor C0having one plate C0P1connected to bit line BL0and the other plate C0P2connected to the drain D0of an MOS transistor T0. The word line WL0is connected to the gate G0of the transistor T0. Likewise, the memory cell MC1includes a capacitor C1having one plate C1P1connected to bit line BL0and the other plate C1P2connected to the drain D1of an MOS transistor T1. The sources S0, S1of these transistors T0, T1are connected together, resulting in what is called a common-source (CS) memory array100. It will be understood that the two cells MC0, MC1shown and described are part of a large number of such memory cells in the array100.

The data storing mechanism of each memory cell is based upon the presence or absence of electric charge accumulated in the capacitor. The presence or absence of the electric charge in the capacitor can be sensed by means of sense amplifier SA (connected to a bit line BL0), sensing current in the bit line BL0.

FIG. 2is a cross-sectional view of an implementation of the structure ofFIG. 1. As shown, the structure ofFIG. 2includes a p type silicon semiconductor substrate SS having spaced n+ diffused regions n+1, n+2, n+3 therein. The region n+1 and the region n+2 make up the drain and source of transistor T0which includes gate oxide and gate WL0(G0), while the region n+3 and the region n+2 make up the drain and source of transistor T1which includes gate oxide and gate WL1(G1). Polycrystalline silicon layers C0P2, C1P2are provided in contact with the respective drain regions n+1, n+3 of the transistors T0, T1, and a dielectric film I is provided as shown, separating the layers C0P2, C1P2from the gates WL0, WL1of the transistors T0, T1. A layer of metal BL0is formed over the dielectric film I. The metal layer BL0is separated from the polycrystalline silicon layers C0P2, C1P2by the dielectric film I, so that metal layer BL0and layer C0P2form capacitor C0, while metal layer BL0and layer C1P2form capacitor C1. The central n+ region n+2, commonly used by the transistors T0, T1, acts as the common source of the transistors T0, T1.

FIG. 3is a graph illustrating typical drain-to-source (IDS) current flow through a transistor of the array as described above, for increasing drain-to-source voltage (VDS), based on increasing steps in the gate-to-source voltage (VGS) of the transistor. If VDS and VGS are kept relatively low (for example with VGS limited to 2 V, and VDS limited to 3 V, current through the transistor is limited to 30 ua).

FIG. 4illustrates a two-terminal metal-insulator-metal (MIM) resistive memory device130. The memory device130includes a metal, for example copper electrode132, an active layer134of for example copper oxide on and in contact with the electrode132, and a metal, for example copper electrode136on and in contact with the active layer134. With reference toFIG. 5, initially, assuming that the memory device130is unprogrammed, in order to program the memory device130, ground is applied to the electrode132, while a positive voltage is applied to electrode136, so that an electrical potential Vpg(the “programming” electrical potential) is applied across the memory device130from a higher to a lower electrical potential in the direction from electrode136to electrode132. Upon removal of such potential the memory device130remains in a conductive or low-resistance state having an on-state resistance.

In the read step of the memory device130in its programmed (conductive) state, an electrical potential Vr(the “read” electrical potential) is applied across the memory device130from a higher to a lower electrical potential in the direction from electrode136to electrode132. This electrical potential is less than the electrical potential Vpgapplied across the memory device130for programming (see above). In this situation, the memory device130will readily conduct current, which indicates that the memory device130is in its programmed state.

In order to erase the memory device130, a positive voltage is applied to the electrode132, while the electrode136is held at ground, so that an electrical potential Ver(the “erase” electrical potential) is applied across the memory device130from a higher to a lower electrical potential in the direction of from electrode132to electrode136.

In the read step of the memory device130in its erased (substantially non-conductive) state, the electrical potential Vris again applied across the memory device130from a higher to a lower electrical potential in the direction from electrode136to electrode132as described above. With the active layer134(and memory device130) in a high-resistance or substantially non-conductive state, the memory device130will not conduct significant current, which indicates that the memory device130is in its erased state.

FIG. 6is a schematic representation of a portion of a typical resistive memory device array200. The array200includes a plurality of word lines (two shown at WL0, WL1), and a plurality of bit lines (one shown at BL0). The array200includes a large number of similar memory cells (two memory cells M0, M1shown inFIG. 6). The memory cell M0includes a resistive memory device RM0as described above and as illustrated inFIG. 4, having one electrode RM0E1connected to bit line BL0and the other electrode RM0E2connected to the drain D0of an MOS transistor T0. The word line WL0is connected to the gate G0of the transistor T0. Likewise, the memory cell M1includes a resistive memory device RM1having one electrode RM1E1connected to bit line BL0and the other electrode RM1E2connected to the drain D1of an MOS transistor T1. The sources S0, S1of these transistors T0, T1are connected together, resulting in a common-source (CS) memory array. It will be understood that the two cells M1, M2shown and described are part of a large number of such memory cells in the array200. A sense amplifier SA is connected to bit line.

It will be seen that the structure ofFIG. 6is similar to that ofFIG. 1, but with the capacitors replaced by resistive memory devices.

FIG. 7illustrates a larger portion of the array200ofFIG. 6, with the common source CS connected to ground. Typically, the programming and erasing of a resistive memory device of the array200requires a substantially larger current therethrough than the current described above for a DRAM cell. In addition, and with reference toFIG. 7, with a large number of bit lines connected to each word line (for example bit lines BL0-BL7connected to a word line WL0, or in actual implementation more than 256 bit lines connected to the same section driving line to minimize array area), it will be seen that upon selection of a word line, for example word line WL0, all current in the bit lines BL0-BL7will flow through the common source CS to ground. These conditions result in the common source CS carrying high levels of current. In such situation, it is highly desirable to provide a low common source resistance, to reduce voltage drop therein, so as to keep the operating speed at an appropriate level, and to also provide high transistor drivability attributable to the grounded source bias condition to insure high performance of the array.

Therefore, what is needed is a resistive memory device array which includes a low-resistance common source and high drivability characteristics.

DISCLOSURE OF THE INVENTION

Broadly stated, the present semiconductor device comprises a substrate, a plurality of source regions in the substrate, and an elongated conductor connecting the plurality of source regions, the elongated conductor, along the length thereof, being positioned adjacent to the substrate to form, with the plurality of source regions, a common source.

The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there are shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

Reference is now made in detail to specific embodiments of the present invention which illustrate the best mode presently contemplated by the inventor for practicing the invention. In the plan views shown and described, some of the structure is removed for clarity.

FIG. 8is a schematic representation of a resistive memory device array300made in accordance with the present invention. It will be understood thatFIG. 8illustrates a very small portion of the overall array. The array300includes a plurality of word lines WL0, WL1, WL2, WL3, WL4. . . and a plurality of bit lines BL0, BL1. . . orthogonal to the word lines. Common source line CS0is provided between word lines WL0, WL1, common source line CS1is provided between WL2, WL3, etc. as shown. Word lines WL1, WL2are separated by isolation region ISO0, word lines WL3, WL4are separated by isolation region ISO1, etc., as shown. A plurality of memory cells M0, M1, M2, M3. . . are provided, each including a resistive memory device (RM0, RM1, RM2, RM3. . . respectively) which may take the form of that shown and described above in regard toFIGS. 3 and 4, and an access MOS transistor (T0, T1, T2, T3) in series with the associated resistive memory device. That is, for example, the memory cell M0includes resistive memory device RM0having one electrode RM0E1thereof connected to bit line BL0and the other electrode RM0E2thereof connected to the drain D0of transistor T0, with the source S0of that transistor T0connected to the common source line CS0. Similarly, the memory cell M1includes resistive memory device RM1having one electrode RM1E1thereof connected to bit line BL0and the other electrode RM1E2thereof connected to the drain D1of transistor T1, with the source S1of that transistor connected to the common source line CS1. Isolation regions ISO0, ISO1. . . separate adjacent pairs of memory devices. It will be seen that the other memory cells of the array300are configured and connected in the manner as shown and described.

A method of fabricating the array300ofFIG. 8is illustrated inFIGS. 9-23. Initially, and with reference toFIGS. 9 and 10, a p type silicon semiconductor substrate302is provided, and through the use of well-known techniques, a plurality of isolated n+ diffused regions304-334are provided in the substrate302. Spaced oxide strips336-348are provided on the substrate302as shown, over and on which are provided respective polysilicon strips350-362. Next, with reference toFIGS. 11 and 12, a dielectric layer364is provided over the resulting structure, a layer of photoresist366is provided over the dielectric layer364, and the photoresist layer366is patterned to provide photoresist bodies366A,366B,366C,366D with elongated openings367,369,371through the photoresist layer366. Using the remaining photoresist as a mask, the dielectric layer364is etched to provide elongated openings368,370,372therethrough to the n+ regions thereunder. After removal of the photoresist, (FIG. 13), a metal layer374is provided over the resulting structure, the metal layer374contacting the respective n+ regions306,312,318,322,328,334. With reference toFIGS. 14 and 15, a layer of photoresist376is provided over the metal layer374, and the photoresist layer376is patterned as shown, to provide elongated photoresist bodies376A,376B,376C. Using the remaining photoresist as a mask, the metal layer374is etched, and the photoresist is removed to provide the structure shown inFIGS. 16 and 17. This step provides spaced-apart elongated metal conductors378,380,382running parallel to the polysilicon strips350-362, elongated metal conductor378contacting and connecting the n+ regions306,322, elongated metal conductor380contacting and connecting the n+ regions312,328, and elongated metal conductor382contacting and connecting the n+ regions318and334.

Next, with reference toFIGS. 18 and 19, additional dielectric is provided over the resulting structure to form the dielectric layer383, a layer of photoresist384is provided over the dielectric layer383, and the photoresist layer384is patterned as shown. Using the remaining photoresist as a mask, the dielectric layer383is etched to provide openings therethrough to respective n+ regions. (The following description references openings386,388,390,392and n+ regions324,326,330,332, but it will be understood that this description is applicable to n+ regions308,310,314,316also). Conductive metal plugs394,396,398,400are provided in the openings formed by this etching to contact the exposed n+ regions324,326,330,332respectively. A dielectric layer402is formed over the resulting structure and is patterned in the manner described above to provide openings404,406,408,410therethrough to the respective plugs394,396,398,400(FIG. 19). Referring toFIGS. 20 and 21, the openings404,406,408,410in the dielectric layer402are partially filled with copper412,414,416,418, in contact with the respective plugs394,396,398,400. The openings404,406,408,410are then filled with active material layer, for example, copper oxide420,422,424,426. The resulting structure is planarized, and metal, for example copper strips428,430are formed over the resulting structure orthogonal to the polysilicon strips350-362, each strip428,430in contact with a series of copper oxide active layers as shown (FIGS. 22 and 23).

The polysilicon strips350,352,356,358,362are the gates (overlying gate oxide) of respective access transistors434,436,438,440,442and make up the word lines of the array300, while the metal strips428,430make up the bit lines thereof. As an example, the access transistor434includes n+ drain region320, gate350and n+ source region322, while the access transistor436includes n+ drain region324, gate352and n+ source region322. The plug394contacts the drain region324of access transistor436, connecting the drain region324thereof to the resistive memory device450made up of the copper body412, copper oxide body420, and copper bit line430. Similarly, the access transistor438includes n+ drain326, gate356and n+ source region328, while the access transistor440includes n+ drain region330, gate358and n+ source region328. The plug396contacts the drain region326of access transistor438, connecting the drain region326thereof to the resistive memory device452made up of the copper body414, copper oxide body422, and copper bit line430. The resistive memory devices450,452are thus positioned between the source regions306,322and the source regions312,328, and in turn between the conductor378and the conductor380. The structure between the adjacent memory devices (for example between memory devices450,452) acts as an isolation region in the array300.

As will be seen, each elongated metal conductor378,380,382is positioned adjacent to and on the substrate302and connects a plurality of spaced source regions arranged in a column of source regions. As such, each elongated metal conductor378,380,382forms with the source regions connected thereto a common source. Each conductor378,380,382is substantially straight along its length, and the conductors378,380,382are substantially parallel and in spaced relation. Each conductor is generally T-shaped in cross-section, that is each conductor includes a relatively narrow elongated first portion (for example portion378A of conductor378) in contact with the source regions (306,322), that first portion378A being narrower in cross-sectional width than the cross-sectional width of each of the associated source regions306,322. Each conductor further includes a relatively wide elongated second portion (for example portion378B of conductor378) connected to the first portion (378A) and spaced from the substrate302, elongated in the same direction as the elongated first portion, and wider in cross-sectional width than the cross-sectional width of the first portion, so that the first and second portions together defined the generally T-shaped cross-section perpendicular to its length. Parts of the second portion of each conductor overlie portions of the gates of adjacent transistors (for example parts of portion378B of conductor378overlie portions of the gates350,352).

The inclusion of the conductors378,380,382as configured connecting a series of source regions greatly reduces common source resistance. Each of the conductors378,380,382is relatively large in cross-section, providing minimal resistance to current flowing therethrough. With the particular cross-section of each conductor378,380,382as shown and described, each conductor takes up minimal substrate area, being relatively narrow in the area of contact to the substrate302. Meanwhile, the conductor is much wider in the portion away from the substrate, where otherwise unused area is available. Thus, a common source is provided which meets the relatively high-current needs of resistive memory devices as described above, meanwhile using minimal substrate area.

A second method of fabricating the array300ofFIG. 8is illustrated inFIGS. 24-33. With reference toFIGS. 24 and 25, similar toFIGS. 9 and 10, a p type silicon semiconductor substrate302is provided, and through the use of well-known techniques, a plurality of isolated n+ diffused regions304-334are provided in the substrate302. Spaced oxide strips336-348are provided on the substrate302as shown, over and on which are provided respective polysilicon strips350-362. After undertaking process steps similar to those shown and described with regard toFIGS. 11-13above, a photoresist layer600is provided over the metal layer374(FIGS. 26 and 27). The photoresist layer600is patterned as shown, wherein elongated bodies600A,600B,600C are provided, similar to the elongated bodies376A,376B,376C of the previous embodiment (FIGS. 14 and 15). In addition, as part of the same lithographic process, generally rectangular bodies600D-600K also remain as shown. Using the remaining photoresist as a mask, the metal layer374is etched, and the photoresist is removed to provide the structure shown inFIGS. 28 and 29. This step provides spaced-apart elongated metal conductors602,604,606running parallel to the polysilicon strips350-362, elongated metal conductor602contacting and connecting the n+ regions306,322, elongated metal conductor604contacting and connecting the n+ regions312,328, and elongated metal conductor606contacting and connecting the n+ regions318,334, similar to the previous embodiment. In addition, this process forms conductive metal pedestals608-622in contact with the respective n+ regions308,310,314,316,324,326,330,332in the substrate302. Each pedestal, while not elongated, is similar in configuration and cross-section to the conductors602,604,606. That is, each pedestal is generally T-shaped in cross-section, i.e., each pedestal includes a relatively narrow first portion (for example first portion616A of pedestal616in contact with a drain region324), that first portion616A being narrower in cross-sectional width than the cross-sectional width of the associated drain region324. Each pedestal further includes a relatively wide second portion (for example second portion616B of pedestal616connected to the first portion616A), spaced from the substrate302, wider in cross-sectional width than the cross-sectional width of the first portion616A, so that the first and second portions together defined the generally T-shaped cross-section thereof.

Next (FIGS. 30 and 31), a dielectric layer628is provided over the resulting structure and is patterned to provide openings to the pedestals (openings630-636shown inFIG. 31). Copper electrodes640-646and active regions648-654are formed in the openings as previously shown and described, and copper bit lines656,658are provided (FIGS. 32 and 33).

It will be seen that the pedestals608-622replace the conductive plugs of the previous embodiment, and are formed using the same masking steps as in the formation of the conductive bodies378-382. Thus, the present approach requires fewer processing steps than the previous approach.

FIG. 34is a schematic representation of another embodiment of resistive memory device array700made in accordance with the present invention. It will be understood thatFIG. 34illustrates a very small portion of the overall array. The array700includes a plurality of word lines WL0, WL1, WL2. . . , and a plurality of bit lines BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7. . . orthogonal to the word lines. A plurality of memory cells MEM0, MEM1, MEM2, MEM3. . . are provided, each including a resistive memory device (for example resistive memory device RM0of memory cell MEM0, etc.) which may take the form of that shown and described above in regard toFIGS. 3 and 4(including first and second spaced electrodes and an active region therebetween and in contact therewith), a diode in series therewith (for example diode DI0in series with memory device RM0, etc.), and an access transistor (for example access transistor TR0). The memory devices MEM0, MEM1, MEM2, MEM3are connected to the respective bit lines BL0, BL1, BL2, BL3, and diodes DI0, DI1, DI2, DI3connect the respective memory devices MEM0, MEM1, MEM2, MEM3with the drain D0of the transistor TR0through a common line CL, with each diode being forward oriented in the direction from its associated bit line to the drain D0of the transistor TR0. As will be seen, multiple sets of bit lines and resistive memory device-diode structures are associated with a single, large area transistor (in this example four sets of memory devices and diodes in series associated with a transistor), with each such memory device-diode structure connecting a bit line with the drain of the transistor. The word line WL0is connected to the gate of the transistor TR0. The group of bit lines BL0, BL1, BL2, BL3is accessed by a switching transistor ST1connecting sense and write amplifiers SA, WA to lines which may connect to the respective bit lines BL0, BL1, BL2, BL3by respective switching transistors ST2, ST3, ST4, ST5. For example, to select the memory cell MEM1, word line WL0is selected, the switch ST1is closed, the switch ST3is closed, and the switches ST2, ST4, ST5are open, so that bit line BL1is selected. In programming the memory device RM0of memory cell MEM1, a voltage is applied to the bit line BL1through the switch ST1and switch ST3, and the source SO of the transistor TR0is grounded, i.e. common source CS is connected to ground. A relatively large current then passes through the memory device MEM1and the diode DI1(forward biased in the direction of such current) to the drain D0of the transistor TR0and to the grounded source S0thereof.

In this high-current programming situation, the large transistor TR0provides high current drivability so as to achieve proper and rapid programming of the memory device. This large transistor TR0, operatively connected to other cells in the group, provides the same advantage for any of the memory cells of that group.

The diodes of the unselected memory cells insure that current flowing in the common line CL (from the selected memory cell MEM1) cannot flow back through other resistive memory devices, which current, if it were allowed to flow, could undesirably alter the state of such memory devices.

Fabrication of the array700ofFIG. 34is illustrated inFIGS. 35-55. Initially, and with reference toFIGS. 35 and 36, a p type silicon semiconductor substrate701is provided, and through the use of well-known techniques using silicon nitride masking (702,704,706,708,710), spaced gate oxide strips712,714,716,718,720, and metal strips722,724,726,728,730are provided, and a plurality of isolated n+ diffused regions732-754are provided in the substrate701, the n+ diffused regions732-742being separated from the n+ diff-used regions744-754by silicon trench isolation region756. Next, with reference toFIGS. 37 and 38, a silicon nitride layer758is provided over the resulting structure, and is planarized to provide a substantially flat upper surface. A layer of photoresist760is provided over the nitride layer758, and the photoresist layer760is patterned as shown (FIGS. 39 and 40). Using the remaining photoresist as a mask, the nitride layer758is etched to provide elongated openings762,764therethrough, the opening762exposing the n+ regions736,748, the opening764exposing the n+ regions742,754(FIGS. 41 and 42). After removal of the photoresist760, a metal layer766, for example, tungsten, is provided over the resulting structure, the metal layer766contacting and connecting the n+ regions736,748,742,754(FIGS. 43 and 44). A layer of photoresist768is provided over the metal layer766, and the photoresist layer768is patterned as shown (FIGS. 45 and 46). Using the remaining photoresist as a mask, the metal layer766is etched to provide openings780-802therethrough to the nitride layer758(FIGS. 47 and 48), patterning the metal layer766while retaining the plate-like configuration of the metal layer766.

With reference toFIGS. 49 and 50, another silicon nitride layer804is provided over the resulting structure, and using appropriate photoresist masking techniques, openings806-822are etched through the nitride layer804and the nitride layer758to the n+ regions in the substrate701(openings812,814,816shown inFIG. 50, which will serve as an example for all openings806-822and processes related thereto). P type silicon regions824,826,828are grown in the openings812,814,816on the respective n+ regions734,738,740of the substrate701(FIG. 51). Tungsten plugs830,832,834are formed in the respective openings812,814,816on and in contact with the p type silicon regions824,826,828respectively, and copper bodies836,838,840are provided in the openings812,814,816on and in contact with the respective tungsten plugs830,832,834(FIGS. 52 and 53). An oxidation process is undertaken to form copper oxide842,844,846on the respective copper bodies836,838,840, and copper bit line850, one of a plurality of copper bit lines848,850,852formed over the structure as previously described, contacts the exposed copper oxide842,844,846,FIGS. 54 and 55(metal strips724,726,728are the word lines, as previously shown and described).

In this embodiment, consistent withFIG. 34, each memory device-diode structure is made up of an n+ region and a p type silicon region in contact therewith (the diode), and a copper body, copper oxide portion, and copper bit line (the memory device), the tungsten plug connecting the diode and memory device in series.

The n+ regions736,748,742,754are source regions, commonly connected by the plate-like metal conductor766which has portions in contact with these source regions, and other portions spaced from the substrate701and connected to the portions in contact with the source regions. As will be seen, the plate-like conductor766forms with the source regions736,748,742,754a common source. The plate-like conductor766, as shown and described above, defines openings780-802through the portions thereof spaced from the substrate701, wherein the resistive memory devices communicate with the substrate701through the respective openings in the plate-like conductor766. Similar to the previous embodiments, isolation regions (such as isolation region756) are provided between adjacent pluralities of source regions.

Using the masking technology as described above, it will be seen that the contacts to the substrate701are self-aligned to the respective n+ source regions, using silicon nitride as a mask, so that proper placement of these contacts is achieved in an efficient manner.

The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Other modifications or variations are possible in light of the above teachings.

The embodiments were chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill of the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally and equitably entitled.