Self-alignment structure for wafer level chip scale package

A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

BACKGROUND

Wafer-level packaging (WLP) is to package an integrated circuit (IC) at wafer level, which is essentially a true chip scale package (CSP) technology, because the resulting package is practically of the same size as the die. In general, the formation of a packaged semiconductor device with under-bump metallurgy (UBM) between a solder bump and a redistribution line (RDL) requires three or four lithographic level masks, and has higher fabrication cost. A packaged semiconductor device containing no UBM between a solder bump and a RDL can lower fabrication cost, because only two lithographic level masks are required for manufacturing the UBM-free packaged semiconductor device. However, in the UBM-free packaged semiconductor device, the solder bumps (balls) are directly mounted on the RDLs, and thus a ball shift problem is likely to be caused during a ball mount process. The ball shift problem results in an inclined printed circuit board mounted on the solder bumps, and degrades the board-level temperature cycling (TC) performance of the device, thus inducing low yield of the ball mount process.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments. The present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. When a layer is referred to as being on another layer or “on” a substrate, it may be directly on the other layer or on the substrate, or intervening layers may also be present. Throughout this disclosure, the term “copper (Cu) post” refers to a copper protrusion, a copper pillar, a thick copper pad and/or a copper-containing protrusion. As used throughout this disclosure, the term “copper” or “copper-containing” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium, etc.

Embodiments of the present disclosure are directed to providing a copper support structure to hold a conductive bump. The conductive bump can be held firmly on the copper support structure, thus avoiding a ball shift problem to increase the yield of a ball mount process and enhance the board-level TC performance for a device, such as a low-cost UBM-free packaged semiconductor device. However, embodiments of the present disclosure are also applicable to other types of packaged semiconductor devices, for example, a packaged semiconductor device with UBM and/or copper posts. In some embodiments, the cooper support structure is formed in the same mask with a RDL, and is raised by a metal base which is formed in the same mask with a metal pad. No additional masks are needed for constructing the copper support structure, thus not significantly increasing the fabrication cost.

FIG. 1Ais a schematic cross-sectional view of a packaging structure for various embodiments. As shown inFIG. 1A, a packaging structure100includes a semiconductor substrate110, a metal base122, a polymer insulating layer140, a copper-containing structure150, an encapsulation layer160and a conductive bump170. The semiconductor substrate110is defined as any construction including semiconductor materials, including, but is not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used. In some embodiments, the metal base122includes aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), alloys thereof, and/or multi-layers thereof. A passivation layer130, such as silicon nitride or silicon oxide, may overlie the semiconductor substrate110and the metal base122, such that portions of the passivation layer130overlying the metal base122are raised.

The polymer insulating layer140overlies the passivation layer130, such that portions of the polymer insulating layer140overlying the raised portions of the passivation layer130are also raised. In some embodiments, the polymer insulating layer140includes an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. The copper-containing structure150is disposed over the polymer insulating layer140. The copper-containing structure150includes a support structure152and a post-passivation interconnect (PPI) line154. The PPI line154may also function as a power line, a RDL, an inductor, a capacitor or any passive component. The PPI line154is located partially within the support structure152. In other words, a portion of the PPI line154is surrounded by the support structure152. The conductive bump170, such as a Sn/Pb or Sn/Ag solder bump, is disposed over the PPI line154and is held by the support structure152. The encapsulation layer160encapsulates the copper-containing structure150and a portion of the conductive bump170. In some embodiments, the encapsulation layer160is formed from a liquid molding compound or a transfer molding compound.

The support structure152overlies the raised portions of the polymer insulating layer140, and is aligned with the metal base122. The support structure152is elevated higher than the PPI line154by about a thickness of the metal base122. The support structure152and the PPI line154are of about the same thickness. However, in some embodiments, the thickness of the support structure152may be greater than that of the PPI line154when no metal base122is disposed underneath. In other words, as long as a top of the support structure152is elevated sufficiently higher than a top of the PPI line154, the height difference between the support structure152and the PPI line154is enough to hold the conductive bump170firmly with or without the metal base122disposed underneath. In some embodiments, the support structure152may be a copper ring with an inner diameter r1 or at least three copper blocks defining a plane, such as a circular plane with an inner diameter r1, for example, about 200 μm.

FIG. 1BandFIG. 1Care schematic top views of a copper-containing structure150and an metal base122shown inFIG. 1A, according to some embodiments. As shown inFIG. 1B, the support structure of the copper-containing structure150is a copper ring152awith an opening, and the PPI line154is located partially within the copper ring152aand extends out through the opening. The copper ring152ais spaced from the PPI line154at a distance d1. In some embodiments, the distance d1 ranges from about 10 μm to about 20 μm, and the width w1 of the copper ring152aranges from about 10 μm to about 20 μm. The distance d1 provides a non-wetting area between the copper ring152aand the PPI line154. In certain embodiments, the distance d1 can be 0, meaning that the PPI line154can be connected to the copper ring152a. As shown inFIG. 1C, the metal base122ofFIG. 1Ais a metal ring122a, such as an aluminum ring. In some embodiments, the width w2 of the metal ring122aranges from about 10 μm to about 20 μm.

FIG. 1DandFIG. 1Eare schematic top views of an copper-containing structure150and an metal base122shown inFIG. 1A, according to some embodiments. As shown inFIG. 1D, the support structure of the copper-containing structure150is constructed from at least three copper blocks152bdefining a plane for holding the conductive bump. The PPI line154is located partially within the plane and extends out through an opening between two adjacent copper blocks152b. The copper blocks152bare spaced from the PPI line154at a distance d1. In some embodiments, the distance d1 ranges from about 10 μm to about 20 μm, and the width w1 of each copper block152branges from about 10 μm to about 20 μm. A semiconductor fab customer may specify the shape and size of the PPI line154to achieve desirable electrical properties. The distance d1 provides a non-wetting area between the copper blocks152band the PPI line154to define the shape and size of the PPI line154as those in the customer specification that does not include copper blocks152b. In certain embodiments, the distance d1 can be 0; meaning that the copper blocks152band the PPI line154can be connected together. As shown inFIG. 1E, the metal base is constructed from at least three metal blocks122b, such as aluminum blocks. In some embodiments, the width w2 of each metal block122branges from about 10 μm to about 20 μm.

FIG. 2Ais a schematic cross-sectional view of a packaging structure for some embodiments. As shown inFIG. 2A, a packaging structure200includes a semiconductor substrate210, a metal base222, a metal pad224, a polymer insulating layer240, a copper-containing structure250, an encapsulation layer260and a conductive bump270. The semiconductor substrate210is defined as any construction including semiconductor materials, including, but is not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used. In some embodiments, the metal base222and the metal pad224include aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), alloys thereof, and/or multi-layers thereof. A passivation layer230, such as silicon nitride or silicon oxide, may overlie the semiconductor substrate210, the metal base222and the metal pad224. An opening in the passivation layer230exposes a portion of the metal pad224. Portions of the passivation layer230overlying the metal base222are raised. The polymer insulating layer240overlies the passivation layer230. An opening in the polymer insulating layer240exposes the portion of the metal pad224. Portions of the polymer insulating layer240overlying the portions of the passivation layer230are raised. In some embodiments, the polymer insulating layer240includes an epoxy, polyimide, BCB, PBO, or the like.

The copper-containing structure250is disposed over the polymer insulating layer240and the exposed portion of the metal pad224. The copper-containing structure250includes a support structure252and a PPI line254. The PPI line254includes a first portion254aand a second portion254b. The first portion254ais located within the support structure252, and the second portion254bextends out through an opening of the support structure252. In some embodiments, the PPI line254is a RDL electrically connected to the metal pad224. The conductive bump270, such as a Sn/Pb or Sn/Ag solder bump, is disposed over the first portion254aof the PPI line254and is held by the support structure252. The encapsulation layer260encapsulates the copper-containing structure250and a portion of the conductive bump270. In some embodiments, the encapsulation layer260is formed of a liquid molding compound or a transfer molding compound.

The support structure252overlies the raised portions of the polymer insulating layer240, and is aligned with the metal base222. The support structure252is elevated higher than the PPI line254by about a thickness of the metal base222, in which the support structure252and the PPI line254are of about the same thickness. In some embodiments, the support structure252may be a copper ring with an inner diameter r1 or at least three copper blocks defining a plane, such as a circular plane with a diameter r1, for example, about 200 μm.

FIG. 2BandFIG. 2Care schematic top views of an exemplary copper-containing structure and an exemplary metal base shown inFIG. 2A. As shown inFIG. 2B, the support structure of the copper-containing structure250is a copper ring252awith an opening, and the first portion254aof the PPI line254is located within the copper ring252a, and the second portion254bof the PPI line254extends out through the opening. The copper ring252ais spaced from the first portion254aof the PPI line254at a distance d1. In some embodiments, the distance d1 ranges from about 10 μm to about 20 μm, and the width w1 of the copper ring252aranges from about 10 μm to about 20 μm. The distance d1 provides a non-wetting area between the copper ring252aand the PPI line254, such that the PPI line254can meet the customer specification in which no copper ring252ais designed. In certain embodiments, the distance d1 can be 0, meaning that the PPI line254can be connected to the copper ring252a. As shown inFIG. 2C, the metal base is a metal ring222a, such as an aluminum ring. In some embodiments, the width w2 of the metal ring222aranges from about 10 μm to about 20 μm.

FIG. 2DandFIG. 2Eare schematic top views of another exemplary copper-containing structure and another exemplary metal base shown inFIG. 2A. As shown inFIG. 2D, the support structure of the copper-containing structure250is constructed from at least three copper blocks252bdefining a plane for holding the conductive bump. The first portion254aof the PPI line254is located within the copper blocks252b, and the second portion254bof the PPI line254extends out through an opening between two adjacent copper blocks252b. The copper blocks252bare spaced from the PPI line254at a distance d1. In some embodiments, the distance d1 ranges from about 10 μm to about 20 μm, and the width w1 of each copper block252branges from about 10 μm to about 20 μm. The distance d1 provides a non-wetting area between the copper blocks252band the PPI line254, such that the PPI line254can meet the customer specification in which no copper blocks252bare designed. In certain embodiments, the distance d1 can be 0; meaning that the copper blocks252band the PPI line254can be connected together. As shown inFIG. 2E, the metal base is constructed from at least three metal blocks222b, such as aluminum blocks. In some embodiments, the width w2 of each metal block222branges from about 10 μm to about 20 μm.

FIG. 3A-FIG.3G are schematic cross-sectional views of intermediate stages showing a method for fabricating a packaging structure in accordance with some embodiments, in which cut lines are used to show the stages for fabricating a support structure with a first portion of a PPI line and a second portion of the PPI line. As shown inFIG. 3A, a metal layer320is deposited on a semiconductor substrate310. In some embodiments, the metal layer320includes aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), alloys thereof, or multi-layers of these. As shown inFIG. 3B, the metal layer320is patterned with one mask to form a metal pad324and a metal base322on the semiconductor substrate310. As shown inFIG. 3C, a passivation layer330, such as silicon nitride or silicon oxide, is formed over the semiconductor substrate310, the metal base. Portions of the passivation layer330are raised by the metal base322. A polymer insulating layer340is formed over the passivation layer330. Portions of the polymer insulating layer340are also raised by the raised portions of the passivation layer330. In some embodiments, the polymer insulating layer340includes an epoxy, polyimide, BCB, PBO, or the like. An opening342passing through the passivation layer330and the polymer insulating layer340is formed to expose a portion of the metal pad324.

As shown inFIG. 3D, a copper-containing layer350is deposited in the opening342and over the polymer insulating layer340. Portions of the copper-containing layer350are also raised by the raised portions of the polymer insulating layer340. The methods for depositing the copper-containing material include sputtering, printing, electro plating, electroless plating, or chemical vapor deposition (CVD) methods. For example, electro-chemical plating (ECP) may be carried out to deposit the copper-containing material. Then, the copper-containing layer350is patterned with one mask to form a support structure352, a first portion354aof a PPI line in the support structure352, and a second portion354bof the PPI line, as shown inFIG. 3E. In some embodiments, the second portion354bof the PPI line is a RDL electrically connected to the exposed portion of the metal pad324. In certain embodiments, the portion354bof the PPI line is a passive component. The support structure352is aligned with the meal base322. The support structure352may be a copper ring as shown inFIG. 2Bor constructed from at least three copper blocks as shownFIG. 2D. The metal base322may be a metal ring as shown inFIG. 2Cor constructed from at least three metal blocks as shownFIG. 2E.

As shown inFIG. 3F, a conductive bump370is formed on the support structure352and contacts a portion354aof the PPI line354. The conductive bump370can be held firmly by the support structure352, and thus the ball shift problem can be avoided. As shown inFIG. 3G, an encapsulation layer360is formed to encapsulate the PPI line354, the support structure352and a portion of the conductive bump370. In some embodiments, the encapsulation layer360is formed of a liquid molding compound or a transfer molding compound. In the aforementioned embodiments of the present disclosure, the support structure352and the PPI line (RDL)354are formed with the same mask, and the metal base322and the metal pad324are formed with the same mask, and thus the fabrication cost can be kept low.

Referring toFIG. 4withFIG. 3A-FIG.3G,FIG. 4is a flow chart of a method for fabricating a packaging structure in accordance with various embodiments. The method begins at operation410, where a metal layer320is deposited over a semiconductor substrate310, as shown inFIG. 3A. At operation420, the metal layer320is patterned to form a metal pad324and a metal base322on the semiconductor substrate310. At operation430, a polymer insulating layer340is formed over the semiconductor substrate310, the metal pad324and the metal base322, as shown inFIG. 3C. At operation440, a first opening342passing through the polymer insulating layer340is formed to expose a portion of the metal pad324, as shown inFIG. 3C. At operation450, a copper-containing layer350is deposited over the polymer insulating layer340, as shown inFIG. 3D. At operation460, the copper-containing layer350is patterned to form a support structure352with a second opening and a PPI line354extending through the second opening, as shown inFIG. 3EandFIG. 2BorFIG. 2D. At operation470, a conductive bump370is formed on the support structure352, as shown inFIG. 3F. At operation480, an encapsulation layer360is formed to encapsulate the PPI line354, the support structure352and a portion of the conductive bump370, as shown inFIG. 3G.

In accordance with an embodiment, the present disclosure discloses a device including a semiconductor substrate, a metal pad, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad is disposed on the semiconductor substrate. The polymer insulating layer overlies the semiconductor substrate and exposes a portion of the metal pad. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure having an opening, and a PPI line. The PPI line is located partially within the support structure and extends out through the opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

In accordance with another embodiment, the present disclosure discloses a device including a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate, and exposes a portion of the metal pad. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a PPI line. The support structure is aligned with the metal base, and has an opening. The metal base and the support structure are of about the same width. The PPI line is located partially within the support structure, and extends out through the opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

In accordance with yet another embodiment, the present disclosure discloses a method for forming a device. In this method, a metal layer is deposited over a semiconductor substrate, and is patterned to form a metal pad and a metal base on the semiconductor substrate. A polymer insulating layer is formed over the semiconductor substrate, the metal pad and the metal base. A first opening passing through the polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing layer is deposited over the polymer insulating layer, and is patterned to form a support structure with a second opening and a PPI line extending through the second opening. A conductive bump is formed on the support structure.

Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.