Method for passivating gate dielectric films

The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH3 or CN species.

BACKGROUND

The present disclosure relates generally to semiconductor devices and methods of manufacturing semiconductor devices, and more particularly to methods and devices for passivating gate dielectric films.

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and designs have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of these advances, functional density has generally increased while geometry size has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.

During the scaling trend, various materials have been implemented for a gate electrode and gate dielectric for MOS or CMOS devices. More specifically, high-k dielectric films have been employed for the gate dielectric to achieve the required equivalent oxide thickness (EOT) while keeping the leakage current of the device to a minimum. However, using high-K dielectric films for the gate dielectric may adversely affect a threshold voltage due to Fermi-level pinning phenomenon at the gate dielectric/electrode interface and thus, may lead to poor device performance and reliability.

Therefore, what is needed is a simple and cost-effective method and device for passivating a gate dielectric film in semiconductor devices.

DETAILED DESCRIPTION

Referring now toFIG. 1, illustrated is a cross-sectional view of part a semiconductor device100having a conventional gate structure. The semiconductor device100may comprise a substrate102, an interfacial layer104formed directly on the substrate, a dielectric layer106formed on the interfacial layer, and a conductive layer108formed on the dielectric layer. In the present example, the substrate102may include silicon (Si). Alternatively, the substrate102may include other suitable semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), and gallium arsenide (GaAs). The substrate102may include other suitable elementary semiconductor materials, such as diamond. The substrate102may further include other suitable compound semiconductor materials, such as silicon carbide (SiC), indium arsenide (InAs), and indium phosphide (InP). The substrate102may also include other suitable alloy semiconductor materials, such as silicon-germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), and indium gallium phosphide (InGaP). In other embodiments, the substrate102may include a semiconductor-on-insulator such as silicon-on-insulator (SOI). In some other embodiments, the substrate102may include a gradient semiconductor layer, and/or may further include a semiconductor layer overlying another semiconductor layer of a different type such as a silicon layer on a silicon germanium layer. The substrate102may further include various features such as doped regions, buried layer, and/or an epitaxy layer (not shown).

The interfacial layer104may include a silicon oxide. The interfacial layer104may be formed by rapid thermal oxidation (RTO). Alternatively, the interfacial layer104may optionally include silicon oxynitride (SiON). The interfacial layer104may be configured to prevent chemical reactions between adjacent layers, such as the substrate102and dielectric layer106.

The dielectric layer106may be formed on the interfacial layer104by various techniques, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), metal-organic chemical deposition (MOCVD), and other suitable techniques. The dielectric layer106may include a high-k dielectric film, such as a metal oxide having a dielectric constant (k) greater than or equal to about 3.9. More specifically, examples of high-k dielectric films include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium titanium tantalum oxide (HfTiTaO), hafnium aluminum iodine oxynitride (HfAlON), and hafnium zirconium oxide (HfZrO). Alternatively, the dielectric layer106may optionally include a multilayer structure. For example, the dielectric layer106may include a dielectric stack with a layer of silicon oxide and a layer of high-k dielectric film.

The conductive layer108may include polysilicon formed on the dielectric layer106by various techniques such as low pressure chemical vapor deposition (LPCVD). The polysilicon may further be doped with negative type (N-type) dopants or positive type (P-type) dopants. Alternatively, the conductive layer108may include a metal, such as Al, Ni, Ru, W, Pd, TaC, Yb, La, Hf, Ti, and other suitable conductive material. The process to form a gate electrode from the conductive layer108may include a patterning and etching step.

The semiconductor device100may include other various features, such as gate spacers that may be formed on both sides of gate structure formed by a deposition and etching step. The gate spacers may include a suitable dielectric material such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or combinations thereof. Additionally, source and drain regions may be formed in the substrate102using ion implantation or diffusion.

It is understood that the semiconductor device100is not limited to a specific transistor and may include negative metal-oxide-semiconductor transistor (NMOS), positive metal-oxide-semiconductor transistor (PMOS), complementary metal-oxide-semiconductor transistor (CMOS), a MOSFET transistor, or combinations thereof. The semiconductor device may further include a bipolar transistor, capacitor, resistor, diode, or combinations thereof.

As previously noted, using high-k dielectric films for the gate dielectric may cause a threshold voltage to drift due to Fermi-level pinning at a polysilicon/metal oxide interface110. Furthermore, other possible regions that may contribute to the drift include a silicon substrate/interfacial layer interface112, a bulk interfacial layer charge114, a metal oxide/interfacial layer interface116, and a bulk metal oxide charge118. Additionally, the interfacial layer104may cause an increase in an equivalent oxide thickness (EOT) of the gate stack. As a result, the semiconductor device100may suffer from poor device performance and reliability. Therefore, what is need is a cost-effective method and semiconductor device for passivating the high-k dielectric film without utilizing an interfacial layer.

Referring toFIG. 2, illustrated is one embodiment of a method200for fabricating a gate structure of a semiconductor device. The method200begins with step210in which a semiconductor substrate such as a silicon substrate (Si-substrate) may be provided. The semiconductor substrate may be similar to the one discussed inFIG. 1. The method200continues with step220in which a gate dielectric layer may be formed on the silicon substrate by a deposition process. The gate dielectric layer may include a high-k dielectric film similar to the one discussed inFIG. 1. Additionally, the gate dielectric layer may include silicon oxide. The silicon oxide may be formed using a process such as thermal oxidation. The high-k dielectric film may have a dielectric constant greater than or equal to about 3.9.

The method200continues with step230in which the gate dielectric layer may be treated with a carbon containing group. The carbon containing group may include an OCH3or CN species. For example, the gate dielectric layer on the silicon substrate may be immersed in a solution containing the OCH3or CN species. The time period for the treatment may vary depending on a particular recipe. The OCH3species may include R—OCH3, where R equals CxHy, where x,y equals an integer: 1, 2, 3, 4, etc. The CN species may include a KCN, HCN, or other suitable solution.

The method200continues with step240in which a gate conductor layer of polysilicon may be formed on the treated gate dielectric layer. Alternatively, the gate conductor layer may optionally include a metal as was discussed inFIG. 1. The OCH3or CN species may readily react with the silicon forming Si—OCH3or Si—CN bonds at the interface (e.g., the dangling bonds at the surface may be terminated by the OCH3or CN bond). The OCH3or CN bonds at the interface may be detected. It has been observed that Si—OCH3and Si—CN bonds (approximately 96 kcal/mol and 153 kcal/mol, respectively) have a higher bond energy than Si—H bonds. Accordingly, the interface between the gate dielectric layer and the gate conductor layer may be passivated and stabilized. It is understood that other types of OCH3or CN bonds, such as Hf—OCH3or Hf—CN, may be formed depending on the type of high-k dielectric film that is utilized.

The method200continues with step250in which a gate structure may be formed from the gate dielectric layer and gate conductor layer by a patterning and etching step. Due to the passivation of the gate dielectric layer with the treatment step230, drifting of a threshold voltage of the semiconductor device may be reduced and thus, better device performance and reliability may be achieved.

Now referring toFIG. 3, illustrated is another embodiment of a method300for fabricating a gate structure of a semiconductor device. The method300ofFIG. 3is similar to the method200ofFIG. 2. The method300begins with step310in which a semiconductor substrate such as a silicon substrate (Si-substrate) may be provided. The semiconductor substrate may be similar to the one discussed inFIG. 1. The method300continues with step320in which the silicon substrate may be treated with a carbon containing group. The carbon containing group may include an OCH3or CN group. For example, the silicon substrate may be immersed in a solution containing the OCH3or CN group. The time period for the treatment may vary depending on a particular recipe. The OCH3group may include R—OCH3, where R equals CxHy, where x,y equals an integer: 1, 2, 3, 4, etc. The CN group may include a KCN or HCN solution. The method300continues with step330in which the OCH3or CN may readily react with the silicon substrate forming Si—OCH3or Si—CN bonds at a first interface (e.g., the dangling bonds at the surface may be terminated by the OCH3or CN bond). The OCH3or CN bonds at the first interface may be detected. It has been observed that Si—OCH3and Si—CN bonds have a high bond energy at approximately 96 kcal/mol and 153 kcal/mol, respectively.

The method300continues with step340in which a gate dielectric layer may be formed on the treated silicon substrate by a deposition process. The gate dielectric layer may include a high-k dielectric film similar to the one discussed inFIG. 1. Additionally, the gate dielectric layer may include silicon oxide. The silicon oxide may be formed using a technique such as thermal oxidation. The high-k dielectric film may have a dielectric constant greater than or equal to about 3.9. Due to the treatment step320, the second interface between the silicon substrate and the gate dielectric layer may be passivated and stabilized.

The method300continues with step350in which the gate dielectric layer may also be treated with the carbon containing group as was discussed in step320. The method300continues with step360in which a gate conductor layer of polysilicon may be formed on the treated gate dielectric layer. The OCH3or CN may readily react with the silicon forming Si—OCH3or Si—CN bonds at a second interface (e.g., the dangling bonds at the surface may be terminated by the OCH3or CN bond). The OCH3or CN bonds at the second interface may be detected. It has been observed that Si—OCH3and Si—CN bonds have a greater bond energy than Si—H. Accordingly, the second interface between the gate dielectric layer and gate conductor layer may be passivated and stabilized. It is understood that other types of OCH3or CN bonds, such as Hf—OCH3or Hf—CN, may be formed depending on the type of high-k dielectric film that is utilized.

The method300continues with step370in which a gate structure may be formed from the gate dielectric layer and the gate conductor layer by a patterning and etching step. Due to the passivation of the gate dielectric layer with the treatment steps320and350, drifting of a threshold voltage of the semiconductor device may be reduced and thus, better device performance and reliability may be achieved.

Referring toFIG. 4, illustrated is a flow chart of another embodiment of a method400for fabricating a gate electrode of a semiconductor device. The method400ofFIG. 4may be similar to the method200ofFIG. 2. The method400begins with step410in which a semiconductor substrate such as a silicon substrate (Si-substrate) may be provided. The semiconductor substrate may be similar to the one discussed inFIG. 1. The method400continues with step420in which a gate dielectric layer may be formed on the silicon substrate by a deposition technique. The gate dielectric layer may include a high-k dielectric film similar to the one discussed inFIG. 1. Additionally, the gate dielectric layer may include silicon oxide. The silicon oxide may be formed using a technique such as thermal oxidation. The high-k dielectric film may have a dielectric constant greater than or equal to about 3.9.

The method400continues with step430in which the gate dielectric layer may be treated with a supercritical fluid (SCF) carrying a carbon containing group. The supercritical fluid may have favorable properties that allow it to carry the carbon containing group into the bulk film of the gate dielectric layer and passivate it. For example, the supercritical fluid may have low surface tension, good diffusivity, and good solubility. The supercritical fluid may include various types, such as N2, Ar, Xe, CO2, propane, ammonia, isopropanol, methanol, and water. It is understood that for a particular type of supercritical fluid a temperature and pressure are required to achieve the supercritical state. For example, supercritical CO2(SCCO2) may have a required temperature of about 31 degree C. (or greater) and a pressure of about 1072 psi (or greater). Accordingly, SCCO2is preferred since the required temperature and pressure are compatible with current semiconductor fabrication techniques and equipment. The carbon containing group may include an OCH3or CN species. The time period for the treatment may vary depending on a particular recipe. The OCH3species may include R—OCH3, where R equals CxHy, where x,y equals an integer: 1, 2, 3, 4, etc. The CN species may include a KCN, HCN, or other suitable solution.

The method400continues with step440in which a gate conductor layer of polysilicon may be formed on the treated gate dielectric layer. Alternatively, the gate conductor layer may optionally include a metal as was discussed inFIG. 1. The OCH3or CN may readily react with the silicon forming Si—OCH3or Si—CN bonds at the interfaces of the gate dielectric layer (e.g., the dangling bonds at the surface may be terminated by the OCH3or CN bond). The OCH3or CN bonds at the interfaces may be detected. It has been observed that Si—OCH3and Si—CN bonds (approximately 96 kcal/mol and 153 kcal/mol, respectively) have a higher bond energy than Si—H bonds. Accordingly, the interface between the gate dielectric layer and the gate conductor layer and the interface between the silicon substrate and the gate dielectric layer may be passivated and stabilized. It is understood that other types of OCH3or CN bonds, such as Hf—OCH3or Hf—CN, may be formed depending on the type of high-k dielectric film that is utilized.

The method400continues with step450in which a gate structure may be formed from the gate dielectric layer and gate conductor layer by a patterning and etching step. Due to the passivation of the gate dielectric layer with the treatment step430, drifting of a threshold voltage of the semiconductor device may be reduced and thus, better device performance and reliability may be achieved.

Referring toFIG. 5, illustrated is a cross-sectional view of a gate structure of a semiconductor device500fabricated by the methods discussed inFIGS. 2-4. The semiconductor device500may comprise a substrate502such as a silicon substrate (Si-substrate). Alternatively, the substrate502may include other types as was discussed inFIG. 1. The semiconductor device may comprise a dielectric layer504formed on the substrate502. The dielectric layer504may include a high-k dielectric film such as a metal oxide or silicon oxide. The dielectric layer504may be configured to have a dielectric constant (k) greater than or equal to about 3.9. The semiconductor device500may further comprise a conductive layer506formed on the dielectric layer504. The conductive layer506may include a polysilicon or metal as was discussed inFIG. 1. The gate structure may be formed from the dielectric layer504and the conductive layer506by a patterning and etching step.

It is noted that the gate structure of the semiconductor device500does not include an interfacial layer to prevent chemical reactions of adjacent layers. This is due to the passivation and stabilization of the dielectric layer504during the treatment step with the carbon containing group discussed inFIGS. 2-4. Accordingly, Si—OCH3or Si—CN (or other X—OCH3or X—CN) bonds form at an interface A508between the substrate502and the dielectric layer504and at an interface B510between the dielectric layer504and the conductive layer506. The thickness at the interfaces may almost not be measurable since only the dangling bonds of the surface are terminated by the OCH3or CN bonds. As a result, drifting of a threshold voltage of the semiconductor device500may be reduced. Additionally, an equivalent oxide thickness (EOT) of the gate dielectric may be minimized by omitting the interfacial layer.

The semiconductor device500may include other various features, such as gate spacers may be formed on both sides of gate structure formed by a deposition and etching step. The gate spacers may include a suitable dielectric material such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or combinations thereof. Additionally, source and drain regions may be formed in the substrate102using ion implantation or diffusion. It is understood that although the methods and devices discussed above are directed at a transistor, other types of devices implementing high-k dielectric films, such as capacitors, resistors, and diodes, may be fabricated with various aspects of the present disclosure.

Thus, the present disclosure provide a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer on the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer on the dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. In some embodiments, the step of forming the dielectric layer includes configuring the dielectric layer to include a dielectric constant (k) greater than or equal to about 3.9. In other embodiments, the step of forming the dielectric layer includes configuring the dielectric layer to include a type selected from a group consisting of: HfO2, SrTiO3, ZrO2, HfSiO, TiO2, and Ta2O5. In other embodiments, forming the conductive layer includes configuring the conductive layer to include a polysilicon or metal. In still other embodiments, the step of treating the dielectric layer includes configuring the carbon containing group to include a OCH3group. In some embodiments, the OCH3group comprises R—OCH3, wherein R equals CxHywherein x,y equals an integer.

In other embodiments, treating the dielectric layer includes configuring the carbon containing group to include a CN group. In some embodiments, the CN group comprises a KCN or HCN solution. In still other embodiments, the method further includes the step of treating the semiconductor substrate with a carbon containing group before forming the dielectric layer.

Additionally, the present disclosure also provides another embodiment of a method including providing a semiconductor substrate; forming a high-k dielectric layer over the semiconductor substrate; treating the high-k dielectric layer with a carbon containing group; forming a conductive layer over the treated high-k dielectric layer; and pattering and etching the conductive and high-k dielectric layer as part of forming a semiconductor device. In some embodiments, the step of treating the high-k dielectric layer includes immersing the high-k dielectric layer in a OCH3containing solution. In some other embodiments, the step of treating the high-k dielectric layer includes immersing the high-k dielectric layer in a CN containing solution. In other embodiments, the method further includes treating the semiconductor substrate with a carbon containing group.

The present disclosure also provides another embodiment of a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a supercritical fluid containing a OCH3or CN group. In some embodiments, the supercritical fluid is of a type selected from a group consisting of: N2, Ar, Xe, CO2, propane, ammonial, isopropanol, methanol, and water. In some other embodiments, the dielectric layer has a dielectric constant greater than or equal to about 3.9. In still some other embodiments, the conductive layer is of a type selected from a group consisting of a polysilicon and a metal. In other embodiments, the OCH3group comprises R—OCH3, wherein R equals CxHy, wherein x,y equals an integer. In other embodiments, the CN group includes a KCN or HCN solution. In still other embodiments, the step of treating the dielectric layer includes treating the semiconductor substrate at the same time.

Several advantages exist with these and other embodiment. In addition to providing a simple and cost-effective method and device for passivating gate dielectric film, the method and device disclosed herein may be implemented and integrated with current semiconductor fabrication techniques and equipment. The method and device may be utilized with a variety of devices such as transistors, capacitors, resistors, diodes, and combinations thereof. Additionally, the method and device disclosed herein reduces drifting of a threshold voltage while maintaining a small effective oxide thickness of the semiconductor device. The thickness of the passivated interface may almost be not measurable. The passivated interface is not a “dense layer.” This allows the method and device disclosed herein to be effectively implemented even as feature sizes continue to get smaller with emerging technologies.