SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING SAME

The present disclosure relates to a semiconductor device and a manufacturing method thereof; wherein the semiconductor device comprises a semiconductor device layer including one or more semiconductor devices; a first electrode interconnection layer disposed on a first side of the semiconductor device layer; one or more first metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection molding material; and a second electrode interconnection layer disposed on a second side opposite to the first side of the semiconductor device layer. In the technical scheme of the present disclosure, the temporary substrate is not required to achieve better support strength and complete the related processes of the semiconductor manufacturing process, which is convenient, convenient and low in cost.

FIELD OF THE INVENTION

The present disclosure relates to the field of semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof.

BACKGROUND OF THE INVENTION

Group III nitride semiconductors are important semiconductor materials, mainly including AlN, GaN, InN and their compounds such as AlGaN, InGaN, AlInGaN, and the like. Due to the advantages of direct band gap, wide band gap and high breakdown electric field strength, group III nitride semiconductors represented by GaN have broad application prospects in the fields of light-emitting devices, power electronics, and radio frequency devices.

Different from conventional non-polar semiconductor materials such as Si, group III nitride semiconductors have polarity, that is, they are polar semiconductor materials. Polar semiconductors have many unique characteristics. It is particularly important that there are fixed polarization charges on the surface of the polar semiconductor or at the interface of two different polar semiconductors. The presence of these fixed polarization charges can attract movable electron or hole carriers to form two-dimensional electron gas 2 DEG or two-dimensional hole gas 2 DHG. The generation of these two-dimensional electron gas 2 DEG or two-dimensional hole gas 2 DHG does not require an additional electric field, nor does it depend on the doping effect in the semiconductor, and is generated spontaneously. The two-dimensional electron gas or the two-dimensional hole gas at the polar semiconductor interface may have a high surface charge density. At the same time, since doping is not required, the ion scattering and other effects of two-dimensional electron gas or two-dimensional hole gas are greatly reduced, so it has high mobility. The high surface charge density and mobility make the two-dimensional electrons or hole gas generated spontaneously at the interface have good conduction ability and high response speed.

In combination with the inherent advantages of nitride semiconductor such as high breakdown electric field strength, this two-dimensional electron gas or two-dimensional hole gas can be used to fabricate high mobility transistors, and its neutral energy is significantly superior to traditional Si or GaAs devices in high energy, high voltage or high frequency applications. However, the existing structure has many defects, which seriously restricts its application range.

SUMMARY OF THE INVENTION

In view of the technical problems existing in the prior art, the present disclosure provides a semiconductor device, which comprises a semiconductor device layer including one or more semiconductor devices; a first electrode interconnection layer disposed on a first side of the semiconductor device layer; one or more first metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection molding material; and a second electrode interconnection layer disposed on a second side opposite to the first side of the semiconductor device layer.

The semiconductor device as described above, wherein one or more semiconductor devices in the semiconductor device layer comprise: one or more of a Schottky diodes, HEMTs, and HHMTs.

The semiconductor device as described above, wherein one or more of the semiconductor devices in the semiconductor device layer have vertical channels.

The semiconductor device as described above, wherein the second electrode interconnection layer is electrically connected to a second electrode on the second side of the semiconductor device layer.

The semiconductor device as described above, wherein the first metal pillars are copper pillars.

The semiconductor device as described above, wherein the height of the first metal pillars are greater than 60 microns, greater than 80 microns, or greater than 100 microns.

The semiconductor device as described above, wherein the first insulating material is distributed, by injection molding, around the one or more metal pillars.

The semiconductor device as described above, wherein the first insulating material is an organic material.

The semiconductor device as described above, wherein the first insulating material is one or more of epoxy resin EP, polystyrene PS, ABS, polycarbonate PC, high density polyethylene (HDPE), polypropylene (PP), and polyvinyl chloride

The semiconductor device as described above further comprises one or more second metal pillars disposed on a second side of the semiconductor device layer and electrically connected to the second electrode interconnection layer; and a second insulating material disposed around the one or more second metal pillars, wherein the second insulating material is an injection molding material.

The semiconductor device as described above further comprises a third electrode interconnection layer disposed on the first side of the semiconductor device layer; and one or more third metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the third electrode interconnection layer; wherein the first insulating material is configured to also be distributed around the one or more third metal pillars.

According to another aspect of the present disclosure, there is proposed a semiconductor device obtained by dicing from the semiconductor device according to any one.

According to another aspect of the present disclosure, there is proposed a semiconductor device obtained by dicing and packaging a semiconductor device according to any one of the above.

According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising forming one or more first metal pillars on the first electrode interconnection layer on the first side of a semiconductor device layer; injecting a first insulating material so that the first insulating material is distributed around the one or more first metal pillars; Removing the substrate; and forming a second electrode interconnection layer on a second side opposite to the first side of the semiconductor device layer; wherein the height of the first metal pillar is greater than 60 microns, greater than 80 microns, or greater than 100 microns.

The method as described above further comprises forming a second electrode on the second side opposite to the first side of the semiconductor device layer after removing the substrate.

The method as described above further comprises removing part of the first insulating material and exposing the one or more first metal pillars.

The method as described above further comprises forming a third electrode interconnection layer on the first side of the semiconductor device layer, and forming one or more third metal pillars on the third electrode interconnection layer on the first side of the semiconductor device layer; wherein the step of injecting the first insulating material further comprises distributing the first insulating material around the one or more third metal pillars.

The method as described above, further comprises: forming one or more second metal pillars on the second electrode interconnection layer on the second side of the semiconductor device layer; injecting a second insulating material such that the insulating material is distributed around the one or more second metal pillars.

According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: forming a semiconductor device layer on a substrate, which includes one or more semiconductor devices; forming a first electrode interconnection layer on a first side of the semiconductor device layer; forming one or more first metal pillars on the first electrode interconnection layer on the first side of the semiconductor device layer; injecting a first insulating material so that the first insulating material is distributed around the one or more first metal pillars; removing the substrate; and forming a second electrode interconnection layer on a second side opposite to the first side of the semiconductor device layer; wherein the height of the first metal pillar is greater than 60 microns, greater than 80 microns, or greater than 100 microns.

The method as described above further comprises forming one or more third metal pillars on the third electrode interconnection layer on the first side of the semiconductor device layer; wherein the step of injecting the first insulating material further comprises distributing the first insulating material around the one or more third metal pillars.

The method as described above, further comprising: forming one or more second metal pillars on the second electrode interconnection layer on the second side of the semiconductor device layer; injecting a second insulating material such that the insulating material is distributed around the one or more second metal pillars.

The method as described above, further comprising: dicing the semiconductor device layer so that the one or more semiconductor devices are separated.

The method as described above, further comprising: packaging the separated one or more semiconductor devices.

In the technical scheme of the present disclosure, the temporary substrate is not required to achieve better support strength and complete the related processes of the semiconductor manufacturing process, which is convenient, convenient and low in cost.

SPECIFIC IMPLEMENTATION

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in combination with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. All the other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts will fall within the scope of protection of the present disclosure.

In the following detailed description, reference may be made to the drawings of the specification which are a part of the present application to explain specific embodiments of the present application. In the drawings, similar reference numerals describe generally similar components in different figures. Each specific embodiment of the present application is described in sufficient detail below, so that ordinary technicians with relevant knowledge and technology in the art can implement the technical solution of the present application. It is understood that other embodiments may be utilized, or structural, logical or electrical changes may be made to the embodiments of the present application.

The present disclosure provides a semiconductor device, wherein two electrodes are respectively positioned on both sides of the semiconductor device. In some embodiments of the present disclosure, such a structure can not only improve the withstand voltage of the semiconductor device, but also facilitate the circuit interconnection of the semiconductor device. In some embodiments of the present disclosure, the substrate can be partially or completely removed, thereby reducing or avoiding the influence of the substrate (especially the heterogeneous substrate, such as the silicon substrate) on the device performance.

The semiconductor device proposed by the present disclosure can be Schottky diode, HEMT, HHMT or other semiconductor devices. The following takes HEMT as an example for description.

FIG.1is a schematic structural diagram of a HEMT according to an embodiment of the present disclosure. In this embodiment, the HEMT100is a dual-channel device, which includes two vertical two-dimensional electron gas 2 DEGs as conductive channels. Referring to the embodiment shown inFIG.1, those skilled in the art can fully obtain a single-channel device including only one vertical 2 DEG, which is also within the protection scope of the present disclosure.

As shown in the figure, the HEMT100includes a substrate101, a first nucleation layer102A and a second nucleation layer102B. The first nucleation layer102A and the second nucleation layer102B are formed on the opposite vertical interface of the substrate101. In some embodiments, the nucleation layers102A and102bmay be AlN. Herein, the nucleation layer may also include a buffer layer (not shown). The buffer layer may have a single-layer or multi-layer structure, including one or more of AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN.

The first channel layer103A and the second channel layer103B are formed by epitaxial growth from the nucleation layers102A and102B, respectively. Further, the first barrier layer104A and the second barrier layer104B are formed by epitaxial growth from the first channel layer103A and the second channel layer103B, respectively. The first barrier layer104A is formed on the right side of the first channel layer103A, and the two are arranged horizontally to form a first heterojunction therebetween, and a vertical 2 DEG is formed in the first heterojunction. The second barrier layer104B is formed on the left side of the second channel layer103B, and the two are arranged horizontally to form a second heterojunction therebetween, and a vertical 2 DEG is formed in the second heterojunction. Under normal growth conditions, the surface of the channel layer and the barrier layer grown on the Si (111), Al2O3 (0001) and SiC (0001) planes is the (0001) plane, that is, the direction from the Si substrate to the channel layer and the barrier layer is the <0001> crystal direction. In such a crystal direction, there is 2 DEG in the channel layer near the interface between the channel layer and the barrier layer. As those skilled in the art know, if the first barrier layer104A is formed on the left side of the first channel layer103A, or the second barrier layer104B is formed on the right side of the second channel layer103B, there are two-dimensional hole gas 2 DHG in the channel layer near the interface between the channel layer and the barrier layer according to the crystal direction. Thus, a dual channel HHMT can be obtained.

As shown inFIG.1, the first channel layer103A and the second channel layer103B are partially formed on the side surfaces of the nucleation layers102A and102B, and extend to occupy the space between the nucleation layers102A and102B. In some embodiments, other portions before the nucleation layers102A and102B may be filled with an insulating material112, such as SiO2 or the like.

As shown inFIG.1, the portions of the substrate101that extend horizontally below and above the nucleation layers102A and102B may include spacer layers111A and111B, respectively, to cover the horizontal surface of the substrate101and separate the substrate101from other parts of the device, thereby further improving the withstand voltage capability. The spacer layers111A and111B are electrically insulating and include one or more of silicon oxide, silicon nitride, and the like.

In some embodiments, the shielding layer113may be included above the partition layer111B extending horizontally above the nucleation layer102A. An insulating layer114may be included on the shielding layer113. The shielding layer113and the insulating layer114can provide support and protection for the device. The shielding layer113and the insulating layer114are electrically insulated and include one or more of silicon oxide, silicon nitride, and the like.

In some embodiments, the first and second channel layers103A and103B may be defined by holes. For example, after forming the nucleation layers102A and102B, the shielding layer113may be deposited. The height of the shielding layer113may be determined according to the height of the desired heterojunction. A first hole and a second hole may be formed on the shielding layer113. The first hole extends downward to expose the nucleation layer102A. The first hole extends downward to expose the nucleation layer102B. Further, the first and second channel layers103A and103B may be epitaxially grown from the nucleation layers102A and102B, and the first and second holes may be filled. Thus, the shapes of the first and second channel layers103A and103B may be defined by the first and second holes.

Further, the first and second barrier layers104A and104B may be defined by holes. For example, after forming the first and second channel layers103A and103B, two other third and fourth holes are formed on the shield layer113, exposing the left and right sides of the first and second channel layers103A and103B, respectively; then, the first and second barrier layers104A and104B may be epitaxially grown on the side surface of the channel layer exposed in the hole, respectively, and the hole may be filled. Thus, the shapes of the first and second barrier layers104A and104B may also be defined by holes.

The heterojunction structure defined by the hole according to the present disclosure has the following advantages: according to the actual needs, a hole structure that can meet the needs can be formed first, and then devices that are difficult to realize by conventional means can be gradually formed in the hole. For example, in the prior art, it is easy to form a structure with a low aspect ratio by epitaxial growth; however, it is often difficult to form a structure with an aspect ratio. When its vertical height is high and its width is small, the traditional epitaxial growth method is difficult to achieve. As disclosed in some embodiments of the present disclosure, such a structure can be easily realized by the hole structure proposed by the present disclosure. On the other hand, a 2 DEG having a high height can be formed by groove definition. In the HEMT formed in this way, when the horizontal projection distance between the electrodes is constant, the on current between the source and drain stages is larger, so that it is easier to obtain a high-power HEMT.

In some embodiments, the aspect ratio of the channel layer to the barrier layer of the semiconductor device of the present disclosure may be 1:2, 1:5, or 1:20. For example, the length of the bottom of both the channel layer and the barrier layer is 1 1 μm (micrometer), and the height of the channel layer103and the barrier layer104may be 2 μm, 5 μm, 20 μm. In fact, through the definition of the hole, any desired aspect ratio can be realized with the help of the hole.

In a general application, the channel layer and the barrier layer are lower than or equal to the height of the hole defined therein. In some special applications, the channel layer and the barrier layer may also extend higher than these holes. However, the growth of the channel layer and the barrier layer may be more difficult to control due to the loss of the limitation of the hole. Therefore, even if the channel layer and the barrier layer are higher than these holes, the higher height will be limited.

In this embodiment, the HEMT100includes a first electrode107and a second electrode108. The first electrode107is positioned on the upper side of the first heterojunction and is in electrical contact with the 2 DEG in the first heterojunction.

The upper side mentioned here refers to the part above the center line of the first heterojunction. Based on the height of the first heterojunction, the horizontal line position at ½ of the height is the center line position of the first heterojunction. Refer to the position of the dotted line inFIG.1. The region above the center line position is the upper side of the first heterojunction. The first electrode may be positioned at any position on the upper side that can make electrical contact with the vertical 2 DEG of the first heterojunction. For example, the first electrode107may be in contact with the vertical 2 DEG from the upper surface of the first heterojunction as shown inFIG.1; alternatively, the first electrode107may be in electrical contact with the 2 DEG perpendicular to the first heterojunction from the first barrier layer side; alternatively, the first electrode107may be in electrical contact with the 2 DEG perpendicular to the first heterojunction from the first channel layer side. The present disclosure is not limited thereto.

Similarly, the second electrode108is positioned on the lower side of the first heterojunction and is in electrical contact with the 2 DEG within the first heterojunction. The lower side mentioned here refers to the part below the center line of the first heterojunction. For example, as shown inFIG.1, the second electrode108is in electrical contact with the 2 DEG perpendicular to the first heterojunction from the side of the first barrier layer. Preferably, the first electrode107and the second electrode108are as far away as possible to maximize the length of the vertical conductive channel and improve the voltage withstand performance of the device.

Referring toFIG.1, since the first electrode107and the second electrode108are positioned on the upper side and the lower side of the center line of the first heterojunction, respectively, the projection of the first electrode and its connecting conductor on the vertical channel plane does not overlap the projection of the second electrode and its connecting conductor on the vertical channel plane. Further, on the third plane perpendicular to the vertical channel plane and the horizontal plane, the projection of the first electrode and its connecting conductor on the vertical channel plane does not overlap with the projection of the second electrode and its connecting conductor on the vertical channel plane.

As shown inFIG.1, for the dual channel HEMT100, the first electrode107and the second electrode108are also in electrical contact with the vertical 2 DEG of the second heterojunction as the other channel, thereby forming a dual channel semiconductor device. The increased conductive channel can increase the on current and thus have higher power; moreover, the double conductive channel has better pressure resistance and heat resistance than the single conductive channel Also, the same attribute electrodes of the double conductive channel structure may be shared. Those skilled in the art should note that although the first electrode107inFIG.1includes two parts corresponding to the first heterojunction and the second heterojunction, these two parts are electrically connected to the same conductor interconnection layer, and thus can be considered as one electrode.

In some embodiments, one of the first electrode107and the second electrode108may be in ohmic contact with the first and second heterojunction; the other is in contact with the first and second heterojunction Schottky, and forms a Schottky diode by using the characteristics of the Schottky contact, which is also a semiconductor device protected by the present disclosure.

In some embodiments, above the first heterojunction shown inFIG.1, a first conductor interconnection layer131is included, which is electrically connected to the first electrode107. Not surprisingly, the first conductor interconnection layer131is also positioned on the upper side of the first heterojunction. The fabrication and interconnection of the first conductor interconnection layer131are well known to those skilled in the art and will not be described here again.

In some embodiments, the lower part of the first heterojunction shown inFIG.1includes a second conductor interconnection layer132, which is electrically connected to the second electrode108. Not surprisingly, the second conductor interconnection layer132is also positioned on the lower side of the second heterojunction. As known to those skilled in the art, the second conductor interconnection layer132can be formed in various ways and electrically connected to the second electrode108. For example, the semiconductor device shown inFIG.1may be turned over, and then through holes may be formed on the substrate101to expose the turned over second electrode108; next, the second conductor interconnection layer132may be formed on the substrate101by depositing metal or the like, and the through hole may be filled to electrically connect the second conductor interconnection layer132and the second electrode108, thereby obtaining the structure shown inFIG.1.

In this embodiment, the HEMT100further includes a third electrode109. The third electrode109is provided between the first electrode107and the second electrode108. As a gate electrode, it is possible to control the current intensity between the first electrode107and the second electrode108to form a HEMT structure. Specifically, the voltage of the third electrode109can control the depth of the heterojunction potential well formed by the channel layer barrier layer, control the surface charge density of 2 DEG in the potential well, and further control the working current between the first electrode107and the second electrode108. In some embodiments, the length of the third electrode109extending horizontally is not less than the length of the 2 DEG105A to realize the control of the current path between the first electrode107and the second electrode108.

In some embodiments, the second electrode108is in ohmic contact with the first and second channel layers103A and103B and the first and second barrier layers104A and104B, and is preferably connected to a high voltage as a drain. The first electrode107is also in ohmic contact, and is preferably used as a source electrode as far as possible from the drain electrode of the second electrode. Further, the center line position of the third electrode109is also positioned on the upper side of the first heterojunction, and is as close to the first electrode107as possible, so as to increase the distance between the drain and the gate, and effectively improve the withstand voltage performance of the HEMT100.

In some embodiments, above the first heterojunction shown inFIG.1, a third conductor interconnection layer133is included, which is electrically connected to the third electrode109. Not surprisingly, the third conductor interconnection layer133is also positioned on the upper side of the first heterojunction. The fabrication and interconnection of the third conductor interconnection layer133are well known to those skilled in the art and will not be described here. Referring toFIG.1, since the third electrode is also positioned on the upper side of the first heterojunction, the projection of the third electrode and its connecting conductor on the vertical channel plane does not overlap with the projection of the second electrode and its connecting metal on the vertical channel plane, the projection of the third electrode and its connecting conductor on the third plane does not overlap with the projection of the second electrode and its connecting metal on the third plane.

It should be noted that the interconnection structure of the third electrode109passes through the interconnection structure of the first electrode107, and the entire interconnection structure is positioned within the area defined by the first electrode107. In this way, there is no need to occupy additional chip area and is conducive to improving the integration of the device.

FIGS.2A and2Bare schematic structural diagrams of an HEMT according to another embodiment of the present disclosure. As shown in the figure, HEMT200is also a dual channel device. The structure of the HEMT200is similar to that of the HEMT100shown inFIG.1, and includes a substrate201, first and second nucleation layers202A and202B, first and second channel layers203A and203B, and first and second barrier layers204A and204B; Wherein a first heterojunction and a second heterojunction are formed between the first and second channel layers203A and203B and the first and second barrier layers204A and204B, respectively. Further, portions of the substrate201extending horizontally above and below the first and second nucleation layers202A and202B include separation layers211A and211B, respectively, to separate the substrate201from other portions of the device. The HEMT200further includes an insulating material212between the first and second barrier layers204A and204B, and a shielding layer213above the spacer layer211B and a protective layer214above the shielding layer213. The HEMT200further includes a first electrode207, a second electrode208and a third electrode209. Parts similar to the structure of the embodiment shown inFIG.1have similar functions, and will not be described here.

The difference from the embodiment shown inFIG.1is that the first and second channel layers203A and203B and the first and second barrier layers204A and204B are positioned above the first and second nucleation layers202A and202B, so that the first and second heterojunctions are further away from the substrate201. This can further improve the performance of the HEMT200. The second conductor interconnection layer232is shown inFIGS.2A and2B, but the first and third conductor interconnection layers are not shown. The manufacturing of the second conductor interconnection layer232and the interconnection with the second electrode208may be similar to the embodiment ofFIG.1. The difference betweenFIG.2AandFIG.2Bis that inFIG.2B, the second electrode is positioned below the first and second nucleation layers202A and202B, and electrically contacts the first and second heterojunction through the first and second nucleation layers202A and202B, respectively. Preferably, the first and second nucleation layers202A and202B are doped to have improved conductivity. In some embodiments, the first and second nucleation layers202A and202B are doped immediately after the vertical sides of the substrate201are formed, and then the first and second channel layers203A and203B are formed. In some embodiments, the first and second nucleation layers202A and202B are doped after being inverted and exposed again. This can avoid the influence of doping on the lattice of nucleation layer and facilitate the subsequent epitaxial growth. In some embodiments, the first and second nucleation layers202A and202B may be the same nucleation layer, and there is no insulating material between them.

It is worth noting that in the embodiment shown inFIG.2AandFIG.2B, since the first and second heterojunctions are both positioned above the substrate201, the insulating material212between the entire substrate201and the first and second nucleation layers202A and202B and between them can be removed without affecting the structure above them. Thus, the influence of the heterogeneous substrate, such as the silicon substrate, on the device performance can be completely avoided.

FIG.3is a schematic structural diagram of an HEMT according to another embodiment of the present disclosure. In order to more clearly illustrate the structure of this embodiment, three dual channel HEMTs300A-300C are shown inFIG.3.

Taking HEMT300A as an example, its structure is similar to that of HEMT100shown inFIG.1, including substrate301, first and second nucleation layers302A and302B, first and second channel layers303A and303B, and first and second barrier layers304A and304B; wherein a first heterojunction and a second heterojunction are formed between the first and second channel layers303A and303B and the first and second barrier layers304A and304B, respectively. Further, portions of the substrate301horizontally extending above and below the first and second nucleation layers302A and302B include separation layers311A and311B, respectively, to separate the substrate301from other portions of the device. The HEMT300further includes an insulating material312between the first and second barrier layers304A and304B and a shielding layer313above the separation layer311B. Parts similar to the structure of the embodiment shown inFIG.1have similar functions, and will not be described here. Unlike the embodiment ofFIG.1, the first and second channel layers303A and303B are covered with a protective layer314to provide further protection.

The HEMT300further includes a first electrode307, a second electrode308and a third electrode309. The first electrode307and the third electrode309are similar to the embodiment ofFIG.1. The second electrode308can be manufactured in different ways. For example, the semiconductor device shown inFIG.2may be inverted, and then a hole may be formed on the substrate301to expose the first and second heterojunctions after the inversion; next, the second electrode308may be formed on the first and second heterojunctions by depositing metal or the like. Filling the hole with an insulating material315after forming the second electrode; Then, through holes are formed in the insulating material315. Next, a metal is deposited on the entire device surface to form a second conductor interconnection layer332, and the through hole is filled to electrically connect the second conductor interconnection layer332and the second electrode308, thereby obtaining the structure shown inFIG.3. In the HEMT structure described inFIG.3, the substrate301only serves as a device support and is sufficiently separated from the active part of the semiconductor device, so that the influence on the device can be further reduced and the performance of the device can be greatly improved.

FIG.4is a schematic structural diagram of an HEMT according to another embodiment of the present disclosure. In order to more clearly explain the structure of this embodiment, three dual channel HEMTs400A-400C are shown inFIG.4.

Taking HEMT400A as an example, its structure is similar to that of HEMT100shown inFIG.1, including first and second nucleation layers402A and402B, first and second channel layers403A and403B, and first and second barrier layers404A and404B; wherein a first heterojunction and a second heterojunction are formed between the first and second channel layers403A and403B and the first and second barrier layers404A and404B, respectively. Further, the spacer layers411A and411B extending horizontally are included above and below the first and second nucleation layers402A and402B. The HEMT400further includes an insulating material412between the first and second barrier layers404A and404B and a shielding layer414above the separation layer411B. The HEMT400further includes a first electrode407, a second electrode408and a third electrode409. The first electrode407and the third electrode409are similar to the embodiment ofFIG.1. Parts similar to the structure of the embodiment shown inFIG.1have similar functions, and will not be described here. Unlike the embodiment ofFIG.1, the first and second channel layers403A and403B are covered with a protective layer414to provide further protection.

The embodiment shown inFIG.4is different from the embodiment shown inFIGS.1-3in that the substrate is completely removed. A manufacturing method of the embodiment ofFIG.4will be described based on the embodiment shown inFIG.2. For example, the semiconductor device shown inFIG.1may be inverted, the substrate401may be thinned first, and then the entire semiconductor device may be placed in an etching liquid to completely remove the substrate401, and the first and second heterojunctions after the inversion may be exposed; next, the second electrode408may be formed on the first and second heterojunctions by depositing metal or the like, and then the second conductor interconnection layer432may be further formed to obtain the structure shown inFIG.4. The hole between the respective HEMTs may be filled with an insulating material415. This step may be performed before or after the second electrode408is formed. Those skilled in the art should note that althoughFIG.4shows the spacer layer411A and the insulating material415filled after the removal of the parallel substrate, this schematic illustration cannot be used due to the thin thickness of the spacer layer411A represents the actual structure.

In the HEMT structure described inFIG.4, the substrate401is completely removed, so that the influence of the substrate, especially the heterogeneous substrate (such as silicon substrate), on the device can be avoided, and the performance of the device can be greatly improved. Further,FIG.4shows a semiconductor device formed by removing a substrate from the structure ofFIG.2.

In some embodiments, in the step of removing the substrate as described above, the substrate, the nucleation layer and the insulating material between the nucleation layers may also be completely removed, and only the part above the substrate in the structure shown inFIG.2may be retained; and then the second electrode and the second conductor interconnection layer are formed. Similarly, from the structure ofFIG.1, a semiconductor device after substrate removal can also be obtained. These modes are also within the scope of the present disclosure.

The present disclosure also includes a method for manufacturing a semiconductor device. Taking the manufacturing process of the dual channel HEMT shown inFIG.4as an example, the manufacturing method of the semiconductor device of the present disclosure will be described. Semiconductor devices of other structures can also be manufactured by similar methods.

FIG.5AA-FIG5VBare flow charts of a manufacturing method of a high electron mobility transistor HEMT according to an embodiment of the present disclosure;FIG.5AA-FIG.5VAare top views of each step of a HEMT manufacturing method according to an embodiment of the present disclosure, andFIG.5AB-FIG5VBare cross-sectional views of each step of a HEMT manufacturing method according to an embodiment of the present disclosure. In this embodiment, a semiconductor device is fabricated on a silicon substrate. As understood by those skilled in the art, other substrates such as intrinsic GaN, Al2O3(sapphire), SiC, etc. can also realize similar structures.

As shown in the figure, the preparation method500of HEMT includes: in step is5001, as shown inFIGS.5AA and5AB, a Si substrate501is provided.

In step5002, a plurality of first holes are formed on the substrate, as shown inFIGS.5BA and5BB. For example, the substrate501is etched by photolithography, and a plurality of rectangular first holes521are formed on the substrate501to expose the vertical interfaces541and542of the substrate501; wherein, the substrate vertical interfaces541and542in the first hole521are (111) planes of the Si substrate. There are other ways to obtain the first hole521in the art, and these methods can also be applied to this.

In some embodiments, the number of the first holes provided on the same substrate depends on the specific requirements of integration and pressure resistance. Here, only three holes are taken as an example. The method according to the present disclosure can pre configure the shape and size of the hole according to the actual needs. For example, when forming a semiconductor device with high withstand voltage, the hole depth is also deep.

In step5003, a protective layer531is formed on the substrate and the first hole surface on the substrate, as shown inFIGS.5CA and5CB. A SiN protective layer531is grown on the substrate501using a technique such as LPCVD to cover the surfaces of the substrate501and the plurality of holes521.

In step5004, the protective layer531horizontally extending on the bottom surface of the first hole and the upper surface of the substrate is removed, and the protective layer531on the sidewall of the first hole is retained, as shown inFIGS.5DA and5DB. The Si substrate501on the bottom surface of the hole521is exposed by the etching technique having the vertical orientation, leaving only the protective layer531formed of SiN on the vertical interfaces541and542. The protective layer531covers the substrate vertical interfaces541and542of the substrate hole521.

In step5005, a first spacer layer is formed on the substrate and the first hole, as shown inFIGS.5EA and5EB. The partition layer511is covered on the bottom surface of the first hole521. In some embodiments, SiO2may be formed using a deposition technique to form the first spacer layer515on the substrate501. Since the vertical interfaces541and542of the substrate501are covered with the protective layer531, the vertical interfaces541and542of the substrate501are substantially free of the growth separation layer515.

In step5006, the protective layer of the hole sidewall is removed, as shown inFIGS.5FAand SFB. The spacer layer511over the substrate501covers a mask, and the protective layer531on the sidewall of the first hole521is partially etched by a selective etching technique. For example, etching may include removing a portion of the sidewall of the first hole521. After etching, the vertical interfaces541and542of the substrate501are exposed. There are other methods in the art to remove the protective layer and expose the vertical interface of the substrate. These methods can also be applied to this.

In step5007, a first nucleation layer and a second nucleation layer are formed at the vertical interface, as shown inFIGS.5GA and5GB. The first and second nucleation layers502A and502B are grown on the exposed vertical surfaces541and542of the substrate501. The nucleation layers502A and502B include AlN. In some embodiments, after forming AlN, one or more buffer materials of AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN may be further grown. In some embodiments, the nucleation layer may grow in the vertical direction (not shown) while growing horizontally. Through the control of process parameters, the growth of nucleation layer can be made as horizontal as possible. Moreover, although there is growth in the vertical direction, it does not affect the device structure.

In step5008, a shielding layer is formed on the entire surface of the device, as shown inFIGS.5HA and5HB. On the structure shown inFIGS.5GA and5GB, the SiO2shielding layer512is formed by a deposition process. The shielding layer512fills the hole521and forms a SiO2shielding layer512of a certain height on the substrate. In some embodiments, if it is desired to form a semiconductor device with a large aspect ratio, the height of the shielding layer512will be correspondingly increased.

In step5009, the shielding layer is patterned to form a plurality of second holes, as shown inFIGS.5IAand SIB. The vertical second holes523and524are etched on the shield layer512by a vertical etching technique. Basically, the second holes523and524define the height of the second layer of the semiconductor device and limit the height of the nucleation layer to the first layer. At the bottom of the holes523and524, the upper surfaces and side surfaces of the nucleation layers502A and502B are exposed.

Those skilled in the art should note that the nucleation layers502A and502B are formed on the surface of the Si substrate (111), so the nucleation layers502A and502B have hexagonal symmetry. Other structures formed in the holes523and524also have hexagonal symmetry after exposing the upper surfaces and side surfaces of the nucleation layers502A and502B.

In step5010, the first and second channel layers are grown in the plurality of second holes, as shown inFIGS.5JA and5JB. Channel layers503A and503B are formed on the nucleation layer502by epitaxial growth. For traditional epitaxial growth, the horizontal growth is not easy to control, so it is difficult for the semiconductor structure to maintain completely vertical growth, and multiple growth planes may appear. The structure of the invention can maintain the continuous growth of the same surface and improve the electrical characteristics of the device.

In step5011, a third hole is formed between the first channel layer and the second channel layer, as shown inFIGS.5KA and5KB. In some embodiments, the shield layer512between the nucleation layers503A and503B is etched to form the third hole525. Since the third hole525is formed between the two second holes523and524, it can be considered that the third hole545and the second holes523and524together form a larger hole with the shielding layer as the sidewall.

In step5012, in the third hole, a first barrier layer and a second barrier layer are formed on one side of the first channel layer and the second channel layer, respectively, as shown inFIGS.5LA and5LB. Barrier layers504A and504B are formed by epitaxial growth in the third hole525. In some embodiments, a barrier layer may be grown to fill the third hole525, and then the barrier layers504A and504B may be formed by etching the barrier layers504A and504B. In some embodiments, the barrier layer may be the same height as the channel layer. In the preferred embodiment, in order to save the process and avoid unnecessary etching from damaging the crystal structure, two barrier layers are epitaxially grown from the channel layers on both sides of the third hole525to reserve the space between the two barrier layers. Thus, as shown in the figure, part of the barrier layer is also formed on the upper surface of the channel layer.

In step5013, a second spacer layer is formed on the entire device, as shown inFIGS.5MA and5MB. SiO2is deposited on the semiconductor device by a deposition process to fill the space between the barrier layers504A and504B and partially cover the channel layer and the barrier layer to form the second spacer layer513.

In step5014, the second spacer layer is patterned, and part of the second spacer layer between the first barrier layer504aand the second barrier layer504bis removed, as shown inFIGS.5NA and5NB. A portion of the second partition layer513between the barrier layers504A and504B is partially removed by a vertical etching technique.

In step5015, a third electrode is formed between the first barrier layer and the second barrier layer, as shown inFIGS.5OA and5OB. The third electrode509is formed on the separation layer513remaining between the first and second barrier layers by an electrode deposition method. In some embodiments, the electrode509as a gate is arranged closer to the upper position, and the electrode509as a gate is as far away from the second electrode508(drain) as possible to improve the overall voltage resistance of the device.

In step5016, a third spacer layer is formed on the third electrode, as shown inFIGS.5PA and5PB. SiO2is deposited on the third electrode509by a deposition process to fill the space between the first barrier layer and the second barrier layer above the third electrode509to form the third partition layer515.

In step5017, the upper surfaces of the first and second heterojunctions are exposed, and a first electrode507is formed on the first and second heterojunctions, as shown inFIGS.5QA and5QB. As shown in the figure, the upper surfaces of the first and second heterojunctions are exposed by removing the second partition layer above the first and second heterojunctions and the possible horizontally extending first and second barrier layers by patterning. In some embodiments, portions of the first and second channel layers and the first and second barrier layers may be further removed to ensure good electrical contact. Next, the first electrode507is formed by filling the electrode material. Although the first electrode507shown in the figure includes two parts respectively contacting the first heterojunction and the second heterojunction, these two parts are electrically connected to the same interconnection layer, and thus can be considered as the same electrode.

In some embodiments, the subsequent steps include forming the first conductor interconnection layer and the third conductor interconnection layer and electrically connecting them to the first electrode and the third electrode, respectively. These steps are well known to those skilled in the art and will not be described here.

In step5018, the entire semiconductor device is turned over and the substrate501is removed, as shown inFIGS.5RA and5RB. As shown in the figure, after the semiconductor device is turned over, the substrate501faces upward. The substrate501is first thinned, and then the entire substrate501is removed from the semiconductor device by wet etching.

In step5019, the first heterojunction and the second heterojunction are exposed, as shown inFIG.5SAandFIG.5SB. As shown in the figure, after the substrate501is removed, the spacer layer above the first and second heterojunctions and part of the insulating material between them are removed to expose the first and second heterojunctions. In some embodiments, over etching may be appropriately performed to ensure good electrical contact.

In step5020, the second electrode508is formed, as shown inFIG.5TAandFIG.5TB. As shown in the figure, a metal electrode, i.e., a second electrode508, is formed on the first heterojunction and the second heterojunction by depositing metal. The second electrode508is in electrical contact with the vertical 2 DEG in both the first heterojunction and the second heterojunction.

In step5021, a passivation layer is formed, and then part of the passivation layer is etched to expose the second electrode508, as shown inFIGS.5UA and5UB. As shown in the figure, a passivation layer is formed by depositing SiO2to fill the space between each HEMT. Of course, SiO2is also partially deposited on the second electrode508. Then, SiO2on the second electrode508is removed by an etching technique to expose the second electrode.

In step5022, a second conductor interconnection layer is formed, as shown inFIG.5VAandFIG.5VB. As shown in the figure, a second conductor interconnection layer is formed by depositing metal to electrically connect the plurality of electrodes508. In some embodiments, the electrode of the second electrode508and the second conductor interconnection layer may be the same material. In some embodiments, the step of forming the second conductor interconnection layer is not necessary. In step5020, the second electrode508and the second conductor interconnection layer may be formed simultaneously.

In the embodiment shown inFIG.5, the shapes of the first and second channel layers503A and503B and the first and second barrier layers504A and504B are defined by holes. As mentioned above, such a structure has many advantages. In some embodiments, the first and second channel layers503A and503B and the first and second barrier layers504A and504B may not be defined by holes, but the epitaxial growth of the first and second channel layers and the first and second barrier layers may be controlled by adjusting process parameters.

Those skilled in the art should note that the embodiment described inFIGS.5AA-5VBis only an exemplary method for manufacturing the semiconductor device according to the present disclosure. There are other manufacturing processes and methods in the art, which can also be applied to obtain the semiconductor device of the present disclosure. These methods are also within the scope of the present disclosure.

As understood by those skilled in the art, the height of the vertical channel semiconductor device formed on the substrate of the present disclosure is generally limited. The height of the semiconductor device is small compared to the height of the substrate. For example, the height of the substrate is generally more than 500 microns, while the height of the semiconductor device is generally several to several tens of microns. A problem caused by this is that the semiconductor device itself is thin, the mechanical strength is insufficient, the self-supporting force is weak, and it is easy to be damaged in the process of removing the substrate.

In order to solve this problem, the prior art method is to fix the wafer including the substrate and the semiconductor device on a temporary substrate before removing the substrate. After removing the substrate and forming the second electrode and the second conductor interconnection layer, the temporary substrate is removed. When using the temporary substrate, the mechanical strength of the semiconductor device can be improved by thickening the metal of the conductor interconnection layer, and the semiconductor device itself can have better self-supporting ability after completing the process.

However, the method steps of the prior art are cumbersome and the cost is high. The present disclosure provides a process that can achieve better support strength and complete the process without temporary substrate.

FIGS.6A-6Gare flowcharts of a semiconductor device fabricating method according to one embodiment of the present disclosure.FIG.6Ashows a state of a semiconductor device (i.e., a wafer) before substrate removal. As shown in the figure, the wafer includes a substrate601and a semiconductor device layer602above it. The semiconductor device layer602includes the vertical channel semiconductor device of the present disclosure, including, but not limited to, one or more of Schottky diode, HEMTs, and HHMTs. A plurality of first conductor interconnection layers603(e.g., source interconnection layers) and a plurality of third conductor interconnection layers604(e.g. gate interconnect layers) are included over the semiconductor device layer602. As understood by those skilled in the art, the semiconductor device layer602can be realized using the above described method or other methods in the art, and will not be described here.

The substrate removal method of this embodiment includes the following steps: in step610, a plurality of metal pillars, such as copper pillars, are formed on the plurality of first electrode interconnection layers603and the plurality of third electrode interconnection layers604; as shown inFIG.6B. A plurality of metal pillars are formed on each electrode interconnection layer and electrically connected to each electrode interconnection layer. The height of the metal column is high to provide sufficient supporting force in subsequent steps. In some embodiments, the height of the metal pillar is greater than 50 microns, 80 microns, or 100 microns.

In some embodiments, if the semiconductor device layer is a device such as a Schottky diode, the third electrode interconnection layer604does not appear on the semiconductor device. Therefore, the third electrode interconnection layer604is not necessary.

In step620, an insulating material is injected between the plurality of metal columns by an injection molding process, as shown inFIG.6C. The insulating material includes two states of flow state and condensed state. During the injection molding process, the insulating material is in a flow state, and flows between the metal columns after injection. After a period of time, the insulating material turns into a solid state, which has good mechanical strength and can provide support in the subsequent substrate removal step. In some embodiments, the insulating material includes at least one or more organic materials, such as epoxy resin EP, polystyrene PS, ABS, polycarbonate PC, high density polyethylene HDPE, polypropylene PP, and polyvinyl chloride PVC.

In this embodiment, an injection molding process is adopted. Injection molding process is a traditional process, easy to integrate with semiconductor process, and relatively low cost. In the process of injection molding, the insulating material is heated to become a flow state. However, the temperature of the insulating material does not cause damage to the semiconductor device. After injection molding, the insulating material enters between the plurality of metal columns and is distributed around the plurality of metal columns. The insulating material becomes a solid state as the temperature decreases, which can not only protect the metal column, but also provide sufficient mechanical strength without using a temporary substrate.

It should be understood by those skilled in the art that the state change of insulating material caused by temperature change is only one way. There are other ways in the art to cause phase change of insulating materials, including but not limited to: ultraviolet irradiation, laser curing, chemical reaction, etc. Depending on the characteristics of the semiconductor device, these kinds of insulating materials can also be selected.

In step630, part of the insulating material is removed and a plurality of metal pillars are exposed, as shown inFIG.6D. This step can also be completed in a later step. Exposing a plurality of metal pillars can prepare for subsequent electrical connection. Similarly, for the metal column and insulating material formed on the other side, a similar method can be adopted to remove part of the insulating material and expose the metal column to ensure electrical connection.

In step640, the silicon substrate is removed, as shown inFIG.6E. The wafer still has a good mechanical strength due to the support of a plurality of metal columns and solid insulating materials. The substrate is not easily damaged in the process of removing the substrate. In some embodiments, the entire wafer is turned over and supported in a support device; then the substrate is thinned first, and then the whole substrate is removed by wet etching. In the process of substrate removal, since the insulating material provides sufficient mechanical strength, the entire wafer is supported in the support device without causing damage.

In step650, a second electrode and a second electrode interconnection layer are formed, as shown inFIG.6F. Those skilled in the art should note that the formation of the second electrode and the formation of the second electrode interconnection layer can be completed in the same step; or may be completed in different steps. In some embodiments, after the substrate is removed, the second electrode may be formed at an appropriate position of the exposed half electrode device layer602, thereby forming the second electrode interconnection layer632electrically connected to the second electrode. In some embodiments, other steps may be included between forming the second electrode and forming the second electrode interconnection layer. These steps include, but are not limited to, depositing an insulating material such as SiO2to form a passivation layer.

In some embodiments, the wafer can be cut after step650. After the semiconductor device layer is cut, one or more semiconductor devices are separated. Next, a packaging step may also be included to obtain a semiconductor device capable of practical application.

In step660, a plurality of metal pillars, such as copper pillars, are formed on the second electrode interconnection layer; then, an injection molding process is used to inject insulating materials between the metal columns, as shown inFIG.6GSimilar to steps610and620, a plurality of metal pillars may also be formed on one side of the second electrode and an insulating material may be injected to further improve the physical strength of the half electrode device. At the same time, the insulating material also encloses the entire semiconductor device layer. In some embodiments, subsequent packaging steps can be saved. The wafer can be cut after step660. In some embodiments, one or more semiconductor devices after dicing may also be packaged again, so as to obtain a semiconductor device that can be applied in practice.

The semiconductor device obtained with reference toFIG.6Gincludes a first electrode interconnection layer, a third electrode interconnection layer, and metal pillars each for electrical connection on a first side (upper side); and the insulating material is distributed between the metal pillars to provide the semiconductor device with the required mechanical strength. A second electrode and a second electrode interconnection layer are included on the second side (lower side) of the semiconductor device. Alternatively, the semiconductor device may also include metal pillars for electrically connecting the second electrode interconnection layer and insulating materials distributed between the metal pillars. Thus, additional mechanical strength is provided on the second side of the semiconductor device.

The above embodiments are only for the purpose of explaining the invention, and are not intended to limit the invention. Ordinary technicians in the relevant technical field can also make various changes and modifications without departing from the scope of the invention. Therefore, all equivalent technical solutions should also belong to the scope of the disclosure of the invention.