An RF amplifier can include multiple gain stages, wherein each gain stage can be DC coupled to an adjacent gain stage. Each input gain stage can include either n-type gain transistors or p-type gain transistors. Multiple input gain stages can be designed/built by interleaving input gain stages of different types. Notably, an input gain stage including n-type gain transistors has a p-type bias transistor. Similarly, an input gain stage including p-type gain transistors has an n-type bias transistor. In this configuration, the bias transistor is the same type as the downstream gain transistors. Therefore, each bias transistor can accurately track the behavior of the transconductance devices of the next gain stage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multi-stage radio frequency (RF) amplifier and in particular to a multi-stage RF amplifier with DC coupled RF gain stages.

2. Related Art

FIG. 1illustrates a conventional two-stage CMOS RF amplifier100that uses AC coupling between the RF gain stages. In RF amplifier100, a first gain stage111includes an inductor101and an NMOS transistor103connected in series between a first voltage source VDD and a second voltage source VSS. Transistor103receives the positive differential input signal Vin(+) on its gate. First gain stage111further includes an inductor102and an NMOS transistor104connected in series between first voltage source VDD and second voltage source VSS. Transistor104receives the negative differential input signal Vin(−) on its gate.

In RF amplifier100, a second gain stage112includes an inductor106and an NMOS transistor108connected in series between first voltage source VDD and second voltage source VSS. Node115, which is located between inductor106and transistor108, provides the negative differential output signal Vout (−). Second gain stage112further includes an inductor107and an NMOS transistor109connected in series between first voltage source VDD and second voltage source VSS. Node116, which is located between inductor107and transistor109, provides the positive differential output signal Vout (+).

The gate of transistor108is connected to node114(which is located between inductor102and transistor104) via a capacitor105. Similarly, the gate of transistor109is connected to node113(which is located between inductor101and transistor103) via a capacitor110. Capacitors105and110provide AC coupling between gain stages111and112.

Notably, the load being driven by each gain stage can be characterized as capacitive. Inductors101and102can be used to tune out such capacitance. Using resistive elements instead of inductors would not permit the RF amplifier to drive the load with sufficient amplitude at high frequencies. Because the frequency of operation is represented by
f=1/2π√{square root over (LC)}  Equation 1
wherein L is the inductance of an inductor and C is the capacitance of the load, then the inductance of each inductor can be computed by
L=1/C(2πf)2Equation 2

Note that gain stages111and112can be biased independently, typically through high value resistors, which can be connected to nodes between capacitors105/110and the gates of transistors108/109. InFIG. 1, one such high value resistor120is shown coupled between a node124and a bias node121. Bias node121can be biased with a voltage provided by a constant current source123and a transistor122, which are connected in series between VDD and VSS. The gate and the drain of transistor122are connected to both bias node121and current source123. In this configuration, at a jigh frequency, the resistance of resistor120is much higher than the impedance of capacitor105, thereby effectively negating the loss due to the biasing elements. Note that similar biasing elements can be connected to a node between capacitor110and the gate of transistor109.

Unfortunately, the AC coupling capacitors (i.e. capacitors105and110) introduce parasitic capacitance at one or both of its terminals. Because of this extra parasitic capacitance, smaller tuning inductors (i.e. inductors101,102,106, and107) must be used, which can result in lower gain for RF amplifier100. In addition, the input parasitic capacitance associated with second gain stage112forms a voltage divider with the AC coupling capacitors (i.e. capacitors105and110), which can result in further gain reduction of RF amplifier100. When second gain stage112is large and has large input capacitance (particularly the case between the gain stages of an on-chip high-power RF amplifier), the performance of RF amplifier100suffers significantly because of the above-described parasitic capacitance and voltage divider configuration. To satisfy a normal gain requirement under such conditions, extra power needs to be consumed. Moreover, the AC coupling capacitors are usually large devices, thereby using significant silicon area.

Therefore, a need arises for an RF amplifier that eliminates the AC coupling between its gain stages, thereby improving performance and saving silicon area.

SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, an RF amplifier can include multiple RF gain stages, wherein each gain stage can be DC coupled to an adjacent gain stage. Each input gain stage can include n-type gain transistors or p-type gain transistors. Advantageously, multiple input gain stages can be designed/built by interleaving input gain stages including p-type gain transistors and input gain stages including n-type gain transistors.

Notably, an input gain stage including n-type gain transistors has a p-type bias transistor. Similarly, an input gain stage including p-type gain transistors has an n-type bias transistor. In this configuration, the bias transistor is the same type as the downstream gain transistors. Therefore, each bias transistor can accurately track the behavior of the transconductance devices of the next gain stage.

In one embodiment, the RF amplifier can include N gain stages. The Nth gain stage of this RF amplifier can include first and second inductors as well as first and second gain transistors. The first inductor and the first gain transistor can be connected in series between a first voltage source and a second voltage source. The second inductor and the second transistor can be connected in series between the first voltage source and the second voltage source.

The N−1 gain stage can include third and fourth gain transistors, third and fourth inductors, and a first bias transistor. The third gain transistor and the third inductor can be connected in series between the first voltage source and a first bias node. The fourth gain transistor and the fourth inductor can be connected in series between the first voltage source and the first bias node. The first bias transistor can be connected between the first bias node and the second voltage source, wherein the gate of the first bias transistor is also connected to the first bias node.

Notably, the first gain transistor, the second gain transistor, and the first bias transistor can be n-type transistors, whereas the third and fourth gain transistors can be p-type transistors. A first node between the first inductor and the first gain transistor can provide the negative differential output signal of the RF amplifier, whereas a second node between the second inductor and the second gain transistor can provide the positive differential output signal of the RF amplifier.

In accordance with one aspect of the invention, a third node between the third gain transistor and the third inductor can directly drive a gate of the first gain transistor, whereas a fourth node between the fourth gain transistor and the fourth inductor can directly drive a gate of the second gain transistor. Note that if N=2, then the positive differential input signal of the RF amplifier can be provided to the gate of the third gain transistor and the negative differential input signal of the RF amplifier can be provided to the gate of the fourth gain transistor.

The RF amplifier can further include an N−2 gain stage. The N−2 gain stage can include fifth and sixth inductors, fifth and sixth gain transistors, and a second bias transistor. The fifth inductor and fifth gain transistor can be connected in series between the second bias node and the second voltage source. The sixth inductor and the sixth gain transistor can be connected in series between the second bias node and the second voltage source. The second bias transistor can be connected between the second bias node and the first voltage source, wherein the gate of the second bias transistor can also be connected to the second bias node. Notably, in the N−2 gain stage, the fifth gain transistor and the sixth gain transistor can be n-type transistors, whereas the second bias transistor can be a p-type transistor.

In accordance with another aspect of the invention, a fifth node between the fifth inductor and the fifth gain transistor can directly drive a gate of the third gain transistor, whereas a sixth node between the sixth inductor and the sixth gain transistor can directly drive a gate of the fourth gain transistor. Note that if N=3, then the positive differential input signal of the RF amplifier can be provided to the gate of the fifth gain transistor and the negative differential input signal of the RF amplifier can be provided to the gate of the sixth gain transistor. Additional gain stages to the RF amplifier can advantageously alternate between the inductor/transistor configurations associated with the N−1 gain stage and the N−2 gain stage.

DETAILED DESCRIPTION OF THE FIGURES

Conventional RF amplifiers use AC coupling between gain stages. This AC coupling introduces undesirable parasitic capacitance at one or both terminals of the gain stage. Unfortunately, such parasitic capacitance significantly lowers amplifier gain.

In accordance with one aspect of the invention, an RF amplifier can include multiple RF gain stages, wherein each gain stage can be DC coupled (not AC coupled) to an adjacent gain stage. Each input gain stage can include either n-type gain transistors or p-type gain transistors. Advantageously, multiple input gain stages can be designed/built by interleaving input gain stages including p-type gain transistors and input gain stages including n-type gain transistors.

FIG. 2illustrates an RF amplifier200with DC coupled RF gain stages. In RF amplifier200, a first gain stage211includes a PMOS transistor201and an inductor203connected in series between a first voltage source VDD and a bias node210. Bias node210is further connected to a second voltage source VSS via an NMOS transistor205, wherein the gate and the drain of transistor205are connected to bias node210. Transistor201receives the positive differential input signal Vin(+) on its gate. First gain stage211further includes a PMOS transistor202and an inductor204connected in series between first voltage source VDD and bias node210. Transistor202receives the negative differential input signal Vin(−) on its gate.

In RF amplifier200, a second gain stage212includes an inductor206and an NMOS transistor208connected in series between first voltage source VDD and second voltage source VSS. Node215, which is located between inductor206and transistor20e, provides the negative differential output signal Vout(−). Second gain stage212further includes an inductor207and an NMOS transistor209connected in series between first voltage source VDD and second voltage source VSS. Node216, which is located between inductor207and transistor209, provides the positive differential output signal Vout(+).

Advantageously, RF amplifier200avoids AC coupling and its problems. Specifically, a node213between transistor201and inductor203is connected directly to the gate of transistor208. Similarly, a node214between transistor202and inductor204is connected directly to the gate of transistor209. Thus, first gain stage211and second gain stage212are DC (not AC) coupled.

Notably, by using an appropriately sized bias transistor205, the connection between the gain stages can be biased. Specifically, bias transistor205can advantageously track the behavior of the NMOS transconductance devices of second gain stage212, i.e. approximately mirroring the bias current of first gain stage211to second gain stage212.

In this configuration, first and second gain stages211and212are no longer biased independently However, the bias of second gain stage212can be adjusted for the given bias current of first gain stage211by adjusting the size of bias transistor205. For example, by making bias transistor205smaller, a larger gate-to-source voltage develops, thereby generating a higher current. The size of bias transistor205can be determined based on the desired gain of second gain stage212(or, in general, the size of the bias transistor can be based on the desired gain of the next gain stage).

Note that some limited gain reduction may occur because of the lower mobility of transistors201/202(i.e. the use of PMOS devices instead of NMOS devices). Additionally, linearity may be somewhat reduced at high voltage swings because the headroom has been reduced by the voltage drop across bias transistor205. However, from a cost-benefit analysis, the advantages of DC (rather than AC) coupling outweigh the minor limitations that can result from this configuration.

FIG. 3illustrates an N-stage RF amplifier300with DC coupled RF gain stages. In this embodiment, RF amplifier has 3 gain stages (i.e. a first gain stage321, a second gain stage322, and a third gain stage323), although an RF amplifier in accordance with the present invention could include any number of gain stages. As described in further detail below, each gain stage other than the output gain stage has a flipped location (i.e. connected to VDD or VSS) and type (e.g. NMOS or PMOS) of the bias transistor compared to an adjacent gain stage.

In RF amplifier300, first gain stage321includes a PMOS (bias) transistor301connected between a voltage source VDD and a bias node324, wherein the gate and the drain of bias transistor301are connected to bias node324. First gain stage321further includes an inductor302and an AMOS transistor304connected in series between bias node324and a second voltage source VSS. First gain stage321yet further includes an inductor303and an NMOS transistor305connected in series between bias node324and second voltage source VSS. The gates of transistors304and305receive the differential input signals Vin(+) and Vin(−), respectively.

Second gain stage322includes a PMOS transistor306and an inductor308connected in series between first voltage source VDD and a bias node329. Bias node329is further connected to second voltage source VSS via an NMOS (bias) transistor310, wherein the gate and the drain of bias transistor310are connected to bias node329. Second gain stage322further includes a PMOS transistor307and an inductor309connected in series between first voltage source VDD and bias node329.

Third (output) gain stage323includes an inductor311and an NMOS transistor313connected in series between first voltage source VDD and second voltage source VSS. Node329, which is between inductor311and transistor313, provides negative differential output signal Vout(−). Third gain stage323further includes an inductor312and an NMOS transistor314connected in series between first voltage source VDD and second voltage source VSS. Node330, which is located between inductor312and transistor314, provides positive differential output signal Vout(+).

In RF amplifier300, a node325between inductor302and transistor304is connected to the gate of transistor306. A node326between inductor303and transistor305is connected to the gate of transistor307. A node327between transistor306and inductor308is connected to the gate of transistor313. A node328between transistor307and inductor309is connected to the gate of transistor314. Thus, RF amplifier300provides DC coupling between its gain stages.

As mentioned above, each gain stage of RF amplifier300other than output gain stage323has a flipped location (i.e. connected to VDD or VSS) and type (e.g. NMOS or PMOS) of both the bias and gain transistors compared to an adjacent gain stage. Specifically, each input gain stage (i.e. any gain stage other than the output gain stage) can include either PMOS gain transistors (and an NMOS bias transistor) or NMOS gain transistors (and a PMOS bias transistor). For example, if the input gain stage includes PMOS drivers connected to VDD, then the bias transistor is an NMOS device connected to VSS. On the other hand, if the input gain stage includes NMOS drivers connected to VSS, then the bias transistor is a PMOS device connected to VDD.

Thus, in general, each gain stage with a first gain transistor type has an adjacent gain stage with a second gain transistor type. For example, if a four-stage RF amplifier was desired, then the first gain stage could include p-type gain transistors, the second gain stage could include n-type gain transistors, the third gain stage could include p-type gain transistors, and the fourth (output) gain stage could include n-type gain transistors. Note that because the bias transistor of the gain stage has an opposite type than the gain transistors, each gain stage with a first bias transistor type also has an adjacent gain stage with a second bias transistor type.

Moreover, although CMOS amplifiers are described above, DC coupled gain stages can also be implemented with bipolar devices. For example, PMOS transistors could be replaced with pnp transistors, and NMOS transistors could be replaced with npn transistors. Therefore, a “p-type” transistor could refer to a PMOS or pnp transistor. Similarly, an “n-type” transistor could refer to an NMOS or npn transistor.

Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying figures, it is to be understood that the invention is not limited to those precise embodiments. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. As such, many modifications and variations will be apparent.

For example, in one embodiment of a bipolar RF amplifier output gain stage400shown inFIG. 4A, capacitive neutralization using capacitors401and402(capacitor401being connected between the gate of npn gain transistor403and the drain of npn gain transistor404, and capacitor402being connected between the gate of npn gain transistor404and the drain of npn gain transistor403) can be used to cancel any parasitic capacitive feedback associated with gain transistors403and404, thereby ensuring stability in high frequency applications.

Another embodiment of such capacitive neutralization is provided in RF amplifier output gain stage410, illustrated inFIG. 4B, using capacitors405and407as parasitic transistor capacitors and capacitors406and408as neutralization capacitors used to counteract the effect of parasitic transistors405and407(wherein capacitors405and407are connected between the gates and drains of NMOS gain transistors409and410, respectively, capacitor406is connected between the gate of gain transistor409and the drain of gain transistor410, and capacitor408is connected between the gate of gain transistor410and the drain of gain transistor409). In yet another embodiment, a CMOS RF amplifier Output stage420, as shown inFIG. 4C, can also include cascoded transistors411and412, wherein transistor411can be connected between inductor311and transistor313and transistor412can be connected between inductor312and transistor314. In this configuration, cascoded transistors411and412can receive a fixed bias voltage on their gates.

Note that the described DC coupling technique can be equally applied to cascoded, linear, and switching power amplifiers.

Accordingly, it is intended that the scope of the invention be defined by the following Claims and their equivalents.