A demodulator is described which includes a hard limiter, reference generator and a phase determiner. The hard limiter produces a binary phase-modulated signal from an analog phase modulated input signal having a first frequency. The reference generator provides a binary reference signal having a second frequency generally equivalent to the first frequency. The phase determiner is operative during a sampling period and determines the phase between the phase-modulated and the reference binary signals during the sampling period.

FIELD OF THE INVENTION 
The present invention relates generally to demodulators implemented in 
digital hardware and to demodulators of intermediate frequency (IF) 
signals which are implemented in digital hardware in particular. 
BACKGROUND OF THE INVENTION 
Digital signal processing is increasingly utilized in communication 
systems. In order to digitize the communication signal which is comprised 
of consecutive symbols or phasors, an interface is required. The 
traditional interface consists of a balanced, analog, demodulator 
providing two phase shifted signals followed by two falters and two analog 
to digital converters (ADCs) to determine both the inphase and quadrature 
values of each symbol. 
For differential phase modulated intermediate (IF) signals, an IF 
differential detector can be utilized, comprising a .pi./2 phase shifter, 
a one symbol delay line, two mixers, a low pass filter, a symbol rate 
sampler, and two ADCs. 
An IF differential detector operates as follows: The IF signal is 
multiplied with a version of itself delayed, via the symbol delay line, by 
one symbol. The result is passed through the low pass filter and the 
symbol rate sampler producing the inphase component of the modulated 
signal. The delayed signal is also passed through the .pi./2 phase shifter 
and the result is multiplied with the input IF signal. The result is 
passed through the low pass filter and the symbol rate sampler producing 
thereby the quadrature component of the demodulated signal. 
The inphase and quadrature signals are then converted to digital signals by 
the ADCs. The phase difference ("phase shift") between two consecutive 
symbols is computed from the inphase-quadrature pair. All of the 
components of the IF differential detector are analog except the digital 
portion of the ADCs. 
Other interfaces include a limiter discriminator receiver which comprises a 
limiter, a discriminator, an integrate and dump filter and an ADC. The IF 
signal is passed through the limiter and the discriminator and the result 
is integrated over one symbol period. The resultant signal corresponds to 
phase differences between consecutive symbols and is sampled once per 
symbol by the ADC. 
The prior art demodulators mix analog and digital elements with ADCs and 
usually consume a lot of power and are generally difficult to implement 
and integrate into a digital system. 
SUMMARY OF THE PRESENT INVENTION 
It is therefore an object of the present invention to provide a demodulator 
for phase and frequency modulated signals which consumes little power and 
is almost entirely formed of digital components. 
There is therefore provided, in accordance with a preferred embodiment of 
the present invention, a demodulator formed of a hard limiter, binary 
reference generating apparatus and a digital phase determining unit. The 
hard limiter provides a binary form of the input analog phase modulated 
input signal. The reference generating apparatus provides a binary 
reference signal having a frequency generally equivalent to the frequency 
of the input signal. Since the input signal is now binary as is the 
reference signal, the phase determining unit operates digitally and 
determines the phase between the phase-modulated and reference binary 
signals during the sampling period. 
Additionally, in accordance with a preferred embodiment of the present 
invention, the digital phase shift determiner includes a) a XOR gate for 
indicating when the phase-modulated and reference binary signals have the 
same binary value, b) a clock having a frequency greater than the 
frequency of the input signal and c) first and second counters. The first 
counter provides a ST.sub.-- COUNT signal having a first and a second edge 
and the second counter counts the number of clock pulses N1 between the 
first and second edges in which the output of the XOR gate is positive. 
Moreover, in accordance with a preferred embodiment of the present 
invention, the phase determining unit also includes a phase shift 
calculator for determining the phase from the number of clock pulses N1. 
Furthermore, in accordance with a preferred embodiment of the present 
invention, the demodulator also includes a phase-shifting unit for 
phase-shifting said reference binary signal thereby producing a 
phase-shifted reference binary signal. The phase shifter typically is an 
inverter followed by a divider for dividing the frequency of the reference 
binary signal in two. 
In another preferred embodiment of the present invention, the phase 
determining unit additionally includes a second XOR gate for indicating 
when the phase-modulated and phase-shifted reference binary signals have 
the same binary value and a third counter for counting the number of clock 
pulses N2 between the first and second edges in which the output of the 
second XOR gate is positive. In this embodiment, the phase calculator 
determines the phase from the number of clock pulses N1 and the sign of 
the phase from the number of clock pulses N2. 
There is also provided, in accordance with a preferred embodiment of the 
present invention, a method for demodulating phase-modulated signals. The 
method performs the steps implemented by the elements of the demodulator, 
as described hereinabove.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT 
Reference is now made to FIGS. 1, 2, and 4. FIG. 1 illustrates a 
demodulator for phase-shift modulated analog signals, constructed and 
operative in accordance with a preferred embodiment of the present 
invention. FIG. 2 illustrates an alternative embodiment for 2PSK coherent 
demodulation. FIG. 4 is a timing diagram of the signals of FIG. 1. 
The demodulator typically comprises a reference generator 8, a phase 
sensing unit 10 and a phase shift determining unit 12. The reference 
generator 8 provides a reference signal at a base frequency of an input, 
analog, phase-modulated IF signal. The phase sensing unit 10 digitally 
senses the phase of the input IF signal with respect to the reference 
signal and the phase shift determining unit 12 determines the size of the 
phase shift, quantizing the phase shift to the levels desired by the 
modulation method. 
Thus, if M-ary differential phase shift keying (MDPSK) is utilized, the 
phase shift between consecutive symbols is determined by subtracting two 
consecutive phase measurements. If M-ary phase shift keying (MPSK) 
coherent demodulation is implemented, then the phase shift is quantized to 
L levels, where L.dbd.M if hard decision coding is desired. 
If the input IF signal was created with two phase shift keying 2PSK, the 
phase shift is quantized to two levels, 0.degree. and 180.degree., for 
hard decision output. 
The reference generator 8 typically generates two square waves (binary 
signals) LO.sub.-- I and LO.sub.-- Q with frequencies of generally the 
expected IF frequency F.sub.-- IF. The two signals LO.sub.-- I and 
LO.sub.-- Q are phase shifted by 90.degree.. Graphs (c) and (f) of FIG. 4 
indicate the incoming IF signal and graphs (d) and (g) respectively 
indicate the reference signals LO.sub.-- I and LO.sub.-- Q. 
The reference generator 8 typically comprises a local oscillator 16, a NOT 
gate 18, and two one stage counters 20 and 22. The local oscillator 16 
typically produces a square wave SQ having a frequency F.sub.-- LO 
generally of twice F.sub.-- IF. One stage counter 20 produces the 
reference signal LO.sub.-- I by dividing the frequency of SQ by two. The 
phase shifted reference signal LO.sub.-- Q is produced by first inverting 
SQ (via NOT gate 18) and then dividing its frequency by 2 (via counter 
22). 
It is noted that if coherent modulation is utilized for the input IF 
signal, the reference signal LO.sub.-- I must be locked to the phase of 
the IF signal. 
The phase sensing unit 10 typically comprises a hard limiter 14, and two 
XOR gates 24 and 26. The hard limiter 14 limits the input analog IF signal 
to two values, thereby producing a binary signal. A typical hard limiter 
is a comparator. 
The reference signals LO.sub.-- I and LO.sub.-- Q are XORed, via XOR gates 
24 and 26 respectively, with the hard limited IF signal and the resultant 
XORed output signals are provided to the phase determining unit 12. The 
XORed signals indicate when the hard limited IF signal has the same binary 
value as the reference signals LO.sub.-- I and LO.sub.-- Q. 
The phase determining unit 12 typically comprises three counters 30, 32 and 
34 and a phase shift calculator 36. The counters 30-34 operate at a clock 
frequency F.sub.-- CL which is typically N times the frequency F.sub.-- 
IF. Graph (a) of FIG. 4 indicates the high frequency clock signal. 
The first counter 30 is a sampling counter which provides a ST.sub.-- COUNT 
signal indicating that counting should occur. When first counter 30 
reaches a count of N, it ceases providing the signal ST.sub.-- COUNT at 
which point sampling of the data in the counters 32 and 34 occurs. Graph 
(b) of FIG. 4 indicates the ST.sub.-- COUNT signal and the period during 
which it is active. 
While the ST.sub.-- COUNT signal is active, the second counter 32 counts 
the number of clock periods N1 in which the local oscillating signal has 
the same sign as the hard limited IF signal. Graph (d) of FIG. 4 indicates 
the output of the second counter 32. The sum of the four groups of pulses 
shown is the value of N1. N1 indicates the percentage of the time when 
ST.sub.-- COUNT was active in which the IF signal and the reference signal 
LO.sub.-- I have the same sign. Thus, the magnitude of the phase between 
LO.sub.-- I and the IF signal is determined by: 
EQU abs(phase)=.pi.(N-N1)/N (1) 
N1 only indicates the magnitude of the phase; it does not indicate whether 
the input IF signal is phase shifted positively or negatively with respect 
to the reference signal LO.sub.-- I. The output of the third counter 34 
provides the sign of the phase, as follows. 
The third counter 34 counts the number of clock periods N2, while the 
ST.sub.-- COUNT signal is active, in which the hard limited IF signal has 
the same sign as the reference signal LO.sub.-- Q. Graph (h) of FIG. 4 
indicates the output of the third counter 34. The sum of the four groups 
of pulses shown is the value of N2. For example, if the input IF signal is 
not phase shifted from LO.sub.-- I, then N1 will equal N and N2 will equal 
N/2. If the input IF signal is positively phase shifted by 10%, then N1 
will be 0.9N and N2 will be 0.6N. If the input IF signal is negatively 
phase shifted by 10%, then N1 will still be 0.9N but N2 will be 0.4N. 
Thus, the sign is determined as follows: 
##EQU1## 
Using equations 1 and 2, the phase shift calculator 36 determines the phase 
and sign between the IF signal and the reference signal from the local 
oscillator 16. Equation 2 can be implemented in a simpler manner, as 
follows: 
EQU If N=2.sup.q, then bit D.sub.q-1 from counter 34 represents the sign bit. 
EQU If N&lt;2.sup.q and N&gt;2.sup.q-1 then counter 34 should be preset to the value 
of 2.sup.q-1 -N/2. In this condition, bit D.sub.q-1 from counter 34 
represents the sign bit. 
The demodulator must also determine the phase shift between consecutive 
samples of the IF signal. This is determined by calculator 36 as follows: 
EQU phase.sub.-- shift=[phase(t)-phase(t-.tau.)]mod.pi. (3) 
wherein .tau. is the length of time between consecutive samples and 
"mod.pi." means that: 
EQU if phase.sub.-- shift&gt;.pi. then phase.sub.-- shift=phase.sub.-- shift-2.pi. 
EQU if phase.sub.-- shift&lt;-.pi. then phase.sub.-- shift=phase.sub.-- 
shift+2.pi.(4) 
If differential phase shift keying modulation was employed, then the phase 
shift is computed once per symbol rather than once per sample as described 
hereinabove. 
If a hard decision is required of the demodulator, the phase calculator 36 
quantizes the resultant value for the phase shift in accordance with the 
desired number of quantization levels. If a soft decision is required, the 
value of the phase shift calculated by equation 1 is provided on output. 
It will be appreciated that because the hard limiter 14 and the local 
oscillator 16 produce binary signals, the remainder of the elements of the 
demodulator of the present invention are digital. 
In order to maximize performance and utilize the minimum power, the ratios 
between the modulation bandwidth, IF frequency and N should be optimized. 
As a rule, the IF frequency F.sub.-- IF must be more than 5 times the 
modulation bandwidth. In order to reduce the affect of aliasing, 
N*F.sub.-- IF must be much larger than F.sub.-- IF. In order to achieve 
little degradation, N should be greater than 100. 
It is possible to implement the present invention with a very low power 
clock, such as one which operates at a clock frequency F.sub.-- CL of 
N*F.sub.-- IF/K, where K is a positive integer greater than 1. In this 
embodiment, the resolution of the output is N, but it takes K IF cycles, 
rather than one cycle, to produce each sample. 
If the local oscillator frequency is not exactly F.sub.-- IF, the phase 
shift calculator 36 can compensate for the error delta.sub.-- psi 
resulting from this mismatching of frequencies as follows: 
EQU delta.sub.-- psi=2.pi.(F.sub.-- IF-F.sub.-- LO.sub.-- I).tau.(5) 
where F.sub.-- LO.sub.-- I is the frequency of the reference signal 
LO.sub.-- I. 
The demodulator of the present invention can also be utilized to demodulate 
IF signals with non-constant envelope modulation, provided that the 
envelope is constant during each sampling period. Examples of non-constant 
demodulation are MPSK and MDPSK produced with a raised cosine shaping 
filter. 
The present invention can also be utilized to demodulate frequency 
modulated signals by estimating the instantaneous frequency. This is 
produced in the phase calculator 36 by subtracting two consecutive phase 
measurements and dividing the result by .tau.. 
It will further be appreciated that the elements utilized in the 
demodulator of the present invention are generally simple and that the 
demodulator utilizes less power than those of the prior art. 
For a 2PSK demodulator producing hard decisions wherein it must be 
determined whether the phase shift is either of 0.degree. or 180.degree., 
only the first and second counters 30 and 32 are utilized and the local 
oscillator, labeled 40, provides a signal at the frequency F.sub.-- IF 
which is locked to the IF signal. This is illustrated in FIG. 2. 
Reference is now briefly made to FIGS. 3A, 3B, 3C, 3D and 3E which are 
circuit diagrams of an exemplary implementation of the demodulator of FIG. 
1. Since the circuit diagrams are believed to be self-explanatory, in the 
interest of conciseness, the following discussion will be brief. 
FIG. 3A illustrates the main elements, "div.sub.-- clk", "lo", "time.sub.-- 
bas" and "ph.sub.-- met" which are respectively detailed in FIGS. 3B, 3C, 
3D and 3E. The input signal of the circuit of FIG. 3A is an already 
hard-limited signal RX.sub.-- IF and the output are the values N1 and N2. 
Thus, the hard limiter 14 and the phase shift calculator 36 are not shown 
in FIGS. 3A-3E. A digital signal processing chip, located outside of the 
circuit of FIGS. 3A-3E, implements the phase shift calculator 36. 
Element div.sub.-- clk provides clock signals throughout the demodulator. 
Element lo implements the reference generator 8. Element time.sub.-- bas 
is equivalent to first counter 30 and produces the ST.sub.-- COUNT signal. 
Element ph.sub.-- met implements the XOR gates 24 and 26 and counters 32 
and 34. 
It will be appreciated by persons skilled in the art that the present 
invention is not limited to what has been particularly shown and described 
hereinabove. Rather the scope of the present invention is defined only by 
the claims which follow: