Switching system with linearizing circuit

A transistor-based switch is coupled to a replica circuit that includes transistor circuitry similar to that of the switch. The replica circuit biases a switched transistor to promote linear operation of the switch.

BACKGROUND

A metal-oxide semiconductor (MOS) field-effect transistor (MOSFET) can be operated as a switch in the transistor's triode or linear region. Such a switch can be conceptualized as a resistor whose value is controlled by the transistor gate-source voltage. When the gate voltage causes the switch to be closed, the resistance may be only a few ohms, which effectively presents a closed circuit. When the gate voltage causes the switch to be open, the resistance is so high as to effectively present an open circuit. However, in reality there are parasitic capacitances in the transistor. In some instances, the resistance can be non-linear, where the resistance becomes dependent upon the transistor source terminal voltage due to the charging times of capacitances. For example, a MOS transistor-based switch in a mixer of the type used in some wireless telephone handset circuits can be driven into non-linear operation by the larger voltage signals that are commonly employed in direct-conversion radio receivers and transmitters to provide noise immunity. Non-linear operation can result in intermodulation distortion that hampers receiver or transmitter performance.

An exemplary quadrature mixer10having a transmission gate structure to promote linearity is illustrated inFIG. 1. Mixer10has sections that can be referred to for convenience herein as switches12,13,14,15,16,17,18and19. The term “switch” as used herein refers to any circuitry that performs a switching function and can include one or more individual switching elements such as transistors or groups of transistors. Switch12mixes a positive in-phase input signal (Ip, labeled inFIG. 1as “I_P” for readability) with a local oscillator (LO) signal and a frequency-doubled local oscillator (2LO) signal. Switch14mixes a negative in-phase input signal (Im, labeled inFIG. 1as “I_M” for readability) with the LO and2LO signals. Switch16mixes a positive quadrature input signal (Qp, labeled inFIG. 1as “Q P” for readability) with the LO and2LO signals. Switch18mixes a negative quadrature (Qm, labeled inFIG. 1as “Q_M” for readability) input signal with the LO and2LO signals. As known in the art, timing circuitry (not shown) causes each of these input signals to be asserted sequentially while the others are de-asserted: Ip, Qp, Im, Qm, Ip, Qp . . . . Accordingly, the mixer output signals OUT__P and OUT__M sequentially represent the result of mixing Ip, Qp, Im, Qm, etc., with the LO and2LO signals. The architecture of mixer10is sometimes referred to as “L0-2L0.”

The LO signals are coupled to the gate terminals of transistors22,24,28,30,40,42,46,48,58,60,64,66,76,78,82and84, while the2LO signals are coupled to the gate terminals of transistors34,36,52,54,70,72,88and90. The LO signals are coupled to the gate terminals via capacitors92, although only one such capacitor92is shown for purposes of clarity. (The ellipsis symbol (“. . .”) is used herein to indicate circuitry or connections not shown.) Similarly, the2LO signals are coupled to the gate terminals via capacitors93, although only one such capacitor93is shown for purposes of clarity. The gate terminals are also coupled to a fixed or constant bias voltage, V_BIAS, via resistors94, although only one such resistor94is shown for purposes of clarity. It can be noted that the above-referenced gate terminals are coupled to various time-shifted versions of the LO and2LO signals, which can be referred to as LO_I_P, L0_I_M, LO_Q_P, L0_Q_M,2LO__P and2L0_M, although inFIG. 1all such signals are simply labeled either “LO” or “2LO” (i.e., without differentiation) for purposes of clarity.

Including the pMOS transistors promotes linear switch operation. It is known that by sizing the pMOS transistor on the order of three times larger than the nMOS transistor in each transmission gate, the transmission gate can be made to switch substantially linearly (i.e., the transmission gate resistance is made linear) over the range of voltages commonly employed in mixers used in some direct-conversion radio receivers and transmitters. If the pMOS transistors were not present (i.e., only nMOS transistors were present) or were not sized in this manner, and if no other measures were taken to promote linear operation, the switching would be susceptible to non-linear operation due to parasitic capacitances between switches. In non-linear operation, the transition time from one output signal, Ip, Qp, Im, Qm, etc., to the next in the sequence depends upon the voltages of those signals, due to the charging times of the capacitances. That is, the previous voltage state of the parasitic capacitance introduces a memory effect, which is the source of the non-linearity.

Other techniques for improving switch linearity have been described, such as feeding back the signal at the source terminal of the switching transistor to the gate of an nMOS transistor to cause the gate voltage to follow the source voltage, such that the gate-to-source voltage is nearly constant. Such a “feedback” or “bootstrapping” technique may not provide good results in a passive mixer of the type used in some direct conversion radio receivers and transmitters because the source and drain terminal voltages of symmetric CMOS transistors interchange, i.e., switch, with one another during mixer operation.

SUMMARY

Embodiments of the invention relate to a switching system and method in which a replica circuit that includes transistor circuitry similar to the switching circuitry of a corresponding switch linearizes the operation of the switch, i.e., linearizes the switch resistance during switching, by adjusting a transistor gate bias voltage. In exemplary embodiments of the invention, the switch switches between at least two signals in response to a switching signal. For example, the switch can be a mixer in a radio receiver or transmitter that mixes one or more local oscillator signals with received signals as part of a downconversion or similar step. In a mixer, the local oscillator signals act as the switching signals. The signals between which the switch switches in response to the local oscillator signals can include, for example in a quadrature mixer, a positive in-phase (Ip) signal, a negative in-phase (Im) signal, a positive quadrature (Qp) signal, and a negative quadrature (Qm) signal. (As used herein, the “p” in such signal names refers to the “positive” or “plus” side of a differential signal, and the “m” refers to the negative or “minus” side.) The switch has one or more switching elements, each comprising one or more transistors including at least one switched transistor that can be switched on and off in response to the switching signal. For example, in a quadrature mixer, there can be Ip, Im, Qp and Qm switching elements. The replica circuit produces a bias voltage, which is applied to a gate terminal or other control terminal of the switched transistor to promote linear switch operation. Embodiments of the invention can include any number of switches, each having any number of switching elements. Each switching element can have any number of transistors. In an embodiment having more than one switching element, there can a corresponding replica circuit for each switching element.

In exemplary embodiments of the invention, the replica circuit includes a replica switching element circuit, a reference resistance, and an operational amplifier (op-amp) circuit. The replica switching element circuit has one or more transistors that correspond to the transistors of the corresponding switching element. (As used in this context herein with regard to the exemplary embodiment, “correspond” means that the transistors of the replica switching element circuit are arranged in substantially the same arrangement as the transistors of the switching element, and are either of substantially the same size and structure as the transistors of the switching element or are scaled versions of the transistors of the switching element.) In either case, the transistor circuitry of the replica switching element replicates or is similar to the transistor circuitry of the switching element of the switch. (The term “replica” is not intended to mean that the two circuits are exactly identical.) Similarly, the reference resistance has a value that corresponds to (i.e., is substantially the same as, or is a scaled version of) the resistance of the switching element. The reference resistance has a first terminal coupled to a first terminal of the replica switching element circuit. The op-amp circuit has a first input coupled to a second terminal of the reference resistance, a second input coupled to a second terminal of the replica switching element circuit, and an output coupled to a control terminal of the switched transistor and a corresponding control terminal of the replica switching element circuit.

Other systems, methods, features, and advantages of the invention will be or become apparent to one with skill in the art upon examination of the following figures and detailed description.

DETAILED DESCRIPTION

As illustrated inFIG. 2, in accordance with an illustrative or exemplary embodiment of the invention, a switching system100, which as described below in further detail can comprise, for example, a mixer, can be linearized, i.e., made to switch more linearly, by coupling a switch102, which performs part or all of the switching function of switching system100, to a linearizing replica circuit (LRC)104. Although the mixer or other switching system100may include any number of switches, the portion represented by switch102in the exemplary embodiment includes a switched transistor106and a second transistor108. In the case of a mixer having an LO-2LO architecture, switched transistor106can be any transistor that has an LO signal coupled to its gate terminal, and second transistor108can be any transistor that correspondingly has a2LO signal coupled to its gate terminal. The LO signal is coupled to the gate terminal of switched transistor106via a capacitor110. The2LO signal is coupled to the gate terminal of second transistor108via a capacitor111. (As used herein, the term “coupled” means connected via zero or more intermediate elements.) The drain terminal of switched transistor106is connected to the source terminal of transistor108. The source terminal of switched transistor106is coupled to the signal IN__A that is switched by switch102. For example, in a quadrature mixer IN__A can be any one of the Ip, Qp, Im and Qm signals. The signal IN__A is also provided to LRC104. In a mixer that transitions its output from one of the mixer input signals (e.g., Ip, Qp, Im, Qm, etc.) to the next in the sequence, both of the signals between which the mixer transitions as a result of the operation of switch102are provided to LRC104. Thus, while the signal IN__A is provided to switch102for switching, both IN__A and another signal IN__B are provided to LRC104. For example, IN__A can be the signal to which the mixer transitions, while IN__B can be the signal from which the mixer transitions. Based upon the feedback provided by IN__A and IN_B, LRC104produces a bias signal, V_BIAS. The bias signal V_BIAS is coupled to the gate terminal of switched transistor106via a resistor112to promote linearization of the operation of switched transistor106.

As illustrated inFIG. 3, LRC104includes a replica switching element circuit114, a reference resistance116, replica load resistances118and120, and an operational amplifier (op-amp) circuit122. The load resistance represents the average load at the mixer output (e.g., OUT_P and0UT__M inFIG. 6, described below), i.e., the time-averaged impedance of the capacitance seen at each mixer output (e.g., OUT_P or0UT_M). The resistance of load resistances118and120are equal to one another. Replica switching element circuit114includes transistors124and126, which are substantially the same as, and arranged in substantially the same arrangement as, a switching element128comprising switching transistor106and second transistor108. Switching element128and the corresponding replica switching element circuit114each comprises two transistors because in the exemplary embodiment switch102is part of an LO-2LO mixer. However, in embodiments in which the switch is of another type or included in a different type of switching system, a switching element can include more than two transistors or as few as a single transistor.

Reference resistance116has a value substantially the same as the resistance of replica switching element circuit114, i.e., the resistance of transistors124and126in series. (As used herein, the term “substantially” refers to the recognition that while it is desirable to make reference resistance116have the same value as the resistance of switching element128, it may not be possible to precisely achieve this goal, and the value of reference resistance116may be greater or smaller than the resistance of switching element128by an amount that is too insubstantial to prevent the circuit from operating in the intended manner.) The value of reference resistance116can also be selected so as to ensure that the output of op-amp circuit122does not saturate at any expected operational input signal level.

The first terminals of load resistances118and120are connected together and to the signal IN_B. A first terminal of reference resistance116is coupled to a first terminal of replica switching element circuit114(specifically, to the source terminal of transistor124. A second terminal of reference resistance116is coupled to a first input of op-amp circuit122(e.g., the positive or non-inverting input) and to a second terminal of load resistance118. A second terminal of op-amp circuit122(e.g., the negative or inverting input) is coupled to a second terminal of replica switching element circuit114and a second terminal of load resistance120. The output of op-amp circuit122is coupled to the gate terminal of transistor124. The signal that op-amp circuit122outputs is first level-shifted by a level shifter130, and the shifted signal is the bias signal V_BIAS. The gate terminal of transistor126is connected to a source of a “high” voltage (V_HIGH) that maintains transistor126in an “on” state. The voltage V_HIGH is the same as the voltage level at which the2LO signal coupled to the gate terminal of second transistor108is sufficient to cause second transistor108to turn on.

Op-amp circuit122includes an op-amp or, alternatively, circuitry that operates in a manner similar to an op-amp. In operation, op-amp circuit122causes the voltages at its input terminals to be equal to each other by adjusting its output signal. Thus, the voltage drop across replica switching element circuit114(i.e., across transistors124and126in series) must equal the voltage drop across reference resistance116. To achieve this operational state, the output of op-amp circuit122adjusts the gate voltage of transistor124so that the resistance of replica switching element circuit114(i.e., the series resistance of transistors124and126) is equal to the value of reference resistance116. The adjusted gate voltage of transistor124is also applied (via level-shifter130) to the gate terminal of switched transistor106as the bias voltage V_BIAS. As reference resistance116responds linearly to a change in voltage across it, the resistance of replica switching element circuit114likewise responds linearly to a change in voltage across it. As the bias voltage V_BIAS that causes replica switching element circuit114to behave linearly is also applied to switched transistor106, switched transistor106and its switching element128likewise behave linearly.

As illustrated inFIGS. 4 and 5, in other embodiments a switched op-amp circuit132can be included in a similar LRC104′ instead of op-amp circuit122(FIG. 3). Op-amp circuit122operates in the manner described above so long as the signal IN__A is greater than the signal IN_B. However, in some instances, such as embodiments in which the switching system is a passive mixer of the type described above, signal IN__A can be greater than signal IN__B at times, while at other times signal IN__B can be greater than signal IN_A. When IN_B is greater than IN_A, the direction of the currents is reversed, and the circuit generates positive rather than negative feedback, preventing op-amp circuit122from achieving a state in which the resistance of replica switching element circuit114is equal to the value of reference resistance116. In the embodiment shown inFIG. 5, switched op-amp circuit132includes additional circuitry that outputs a signal having a polarity that depends upon which of IN_A and IN_B is greater than the other.

Switched op-amp circuit includes an op-amp134or, alternatively, circuitry that operates in a manner similar to an op-amp, two transmission gates136and138that form a polarity selection circuit140, and a comparator circuit142. Comparator circuit142can comprise a comparator, op-amp or similar circuitry that can determine which of two signals is greater than the other. One input of comparator circuit142(e.g., the positive or non-inverting input) is coupled to signal IN_A, and the other input of comparator circuit142(e.g., the negative or inverting input) is coupled to signal IN_B. If signal IN__A is greater than signal IN_B, comparator circuit142asserts its positive or non-inverting output and de-asserts its negative or inverting output. If signal IN__B is greater than signal IN_A, comparator circuit142asserts its negative or inverting output and de-asserts its positive or non-inverting output. The positive or non-inverting output of comparator circuit142is coupled to the gate terminal of one transistor of each transmission gate, and the negative or inverting output of comparator circuit142is coupled to the gate terminal of the other transistor of each transmission gate. Polarity selection circuit140has a first input coupled to the positive or non-inverting output of op-amp134and a second input coupled to the negative or inverting output of op-amp134. Thus, if comparator circuit142determines that IN__A is greater than IN_B, then the output signal from comparator circuit142closes or activates transmission gate136, which thus passes the signal provided by the positive or non-inverting output of op-amp134, and opens or deactivates transmission gate138, which thus blocks the signal provided by the negative or inverting output of op-amp134. Conversely, if comparator circuit142determines that IN__B is greater than IN_A, then the output signal from comparator circuit142closes or activates transmission gate136, which thus passes the signal provided by the positive or non-inverting output of op-amp134, and opens or deactivates transmission gate138, which thus blocks the signal provided by the negative or inverting output of op-amp134. The signal that polarity selection circuit140passes (by the above-described operation of transmission gates136and138) is provided as the bias signal V_BIAS (via level shifter130).

As illustrated inFIG. 6, LRCs144,146,148and150of the type described above with regard toFIGS. 2-5(e.g., LRC104or104′) can be used in a switching system152that comprises a quadrature mixer of the type used in some radio receivers. Note that switching system152includes only nMOS transistors154,156,158,160,162,164,166,168,170,172,174and176, and does not include any pMOS transistors. The use of pMOS transistors increases the load to the circuitry (not shown) that generates the LO and2LO signals and thus the current. It is desirable to minimize current in portable radio receivers, such as those of wireless telephone handsets, so as to minimize battery drain. Therefore, in the embodiment shown inFIG. 6the switching elements of the mixer do not include pMOS. As LRCs144,146,148and150promote linear switch operation, no pMOS is needed for that purpose.

Switching system152has an LO-2LO architecture that is generally analogous to that described above with regard toFIG. 1except that the gate terminals of transistors154,156,158,160,162,164,166and168are coupled to LRCs144,146,148and150to provide the bias voltage V_BIAS instead of a fixed or constant bias voltage. More specifically, the gate terminals of transistors154and156are coupled to LRC144via resistors178and180, respectively; the gate terminals of transistors158and160are coupled to LRC144via resistors182and184, respectively; the gate terminals of transistors162and164are coupled to LRC148via resistors186and188, respectively; and the gate terminals of transistors166and168are coupled to LRC150via resistors190and192, respectively. The LO signals are coupled to the gate terminals of transistors154,156,158,160,162,164,166and168via corresponding capacitors194, although only one such capacitor194is shown for purposes of clarity. Similarly, the2LO signals are coupled to the gate terminals of transistors170,172,174and176via other capacitors196, although only one such capacitor196is shown for purposes of clarity. It can be noted that these gate terminals are coupled to various time-shifted versions of the LO and2LO signals, which can be referred to as LO_I_P, L0_I_M, LO_Q_P, L0_Q_M,2LO_P and2L0_M, although inFIG. 6all such signals are simply labeled “LO” and “2LO” (i.e., without differentiation) for purposes of clarity. Persons skilled in the art are familiar with such signals and their timing relationships and will readily be capable of providing suitable circuitry for generating these signals and providing them to the appropriate transistors.

While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this invention. Accordingly, the invention is not to be restricted except in light of the following claims.