Methods of manufacturing light to current converter devices

Processes for making light to current converter devices are provided. The processes can be used to make light to current converter devices having P-N junctions located on only the top surface of the cell, located on the top surface and symmetrically or asymmetrically along a portion of the inner surface of the via holes, located on the top surface and full inner surface of the via holes, or located on the top surface, full inner surface of the via holes, and a portion of the bottom surface of the cell. The processes may isolate the desired P-N junction by etching the emitter, forming a via hole after forming the emitter, using a barrier layer to protect portions of the emitter from etching, or using a barrier layer to prevent the emitter from being formed on portions of the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Chinese Patent Application Numbers 201120175836.7, 201120176094.X, 201110141250.3, 201110141621.8, 201110141259.4, 201110141575.1, and 201110141248.6, filed May 27, 2011, which are incorporated by reference herein in their entirety. This application is also related to U.S. patent application Ser. No. 13/193,433 entitled “Light to Current Converter Devices and Methods of Manufacturing the Same”, which is incorporated by reference herein in its entirety.

BACKGROUND

The present disclosure relates generally to light to current converter devices (e.g., solar cells), and, more particularly, to back contact solar cells.

2. Related Art

In recent years, interest in new forms of renewable energy has increased due to problems associated with conventional energy sources. For example, rising oil prices, global warming, exhaustion of fossil fuel energy, nuclear waste disposal, locating construction sites for new power plants, and the like, have caused interest in photovoltaic devices or solar cells, which are pollution-free energy sources, to grow. As a result, research and development in this field has actively progressed.

A solar cell, which is an apparatus that converts light energy into electrical energy using the photovoltaic effect, may fall into any one of a number of different cell types, such as silicon solar cells, thin film solar cells, dye-sensitized solar cells, and the like. Silicon solar cells occupy the largest portion of current markets due to its high conversion efficiency. In standard-structured solar cells, positive and negative contacts are located on opposite sides of the solar cell. Therefore, shadow loss on the front or illuminated surface by the corresponding contacts limits the light to current conversion efficiency.

Some alternative solar cells have been developed to solve the above problem, one of which is called a “back contact solar cell.” In a back contact solar cell, both ohmic contacts (positive and negative contacts) are placed on the back or non-illuminated surface of the solar cell. In this way, shadow loss can be reduced or avoided.

One conventional way to fabricate back contact solar cells is to place the carrier collecting junction formed between oppositely doped semiconductor regions close to the back surface of the cell, rather than the front surface of the cell. This type of back contact solar cell is called a “back junction cell,” and is described in “1127.5-Percent Silicon Concentrator Solar Cell” (R. A. Sinton, Y. Kwark, J. Y. Gan, R. M. Swanson, IEEE Electron Device Letters, Vol. ED-7. No. 10, October 1986). However, since the majority of photons are absorbed close to the front surface of the back junction cell, the carriers generated in these regions must diffuse through the entire base region of the cell before reaching the carrier collecting junction located near the back surface. Thus, these types of solar cells require high quality wafers having minority carrier diffusion lengths longer than the wafer thickness as well as very high minority carrier lifetimes.

Another way to fabricate back contact solar cells is to place both external contacts for the oppositely doped regions on the back surface of the solar cell and to place the collecting junction close to the front surface of the solar cell. In these devices, the collection current from the front surface is lead through openings, through-holes, or vias, which extend through the entire wafer to the back surface. Using this structure, shading losses caused by the front metallization may be reduced. The document WO 1998/054763 (EP0985233B1) describes such a structure, referred to herein as “Metal Wrap Through (MWT).” Furthermore, additional patents and patent applications, such as, WO2010126346, JP2010080576, JP2010080578, US20100276772, US20090188550, US20090178707, KR1020100098993, and DE102008033632, describe additions to the MWT structure. However, the described structures generally include a double junction with the emitter located on the front of the cell, back of the cell, and inside walls of the via holes. To illustrate,FIG. 1shows a cross-sectional view of a P-N junction having an emitter2that covers the front surface, the full inner surface of the via hole3, and the adjacent back side to the via hole of the substrate1. To generate this type of P-N junction, double sided diffusion is needed, causing throughput loss during manufacturing. Additionally, back contact isolation using a laser is required to eliminate the short circuit that would otherwise occur between the backside emitter and the back contact. The use of the laser increases the breakage ratio of the solar cell, increases the production costs, and causes damage in the crystalline material leading to more recombination of charge carriers in the area around the laser groove.

To omit the back contact isolation step and reduce the excessive shunt, such as that occurring in the via and under the back emitter bus bars, the back side emitter can be removed and a dielectric layer can be positioned to cover the via and the adjacent back side of the solar cell, as disclosed in, for example, patents and patent applications: US20100319766, US20100258177, EP2068369, WO2009071561, CN101889349, US20110005582, US20090084437. Among these, some describe the emitter as being located on only the front surface, while others describe the emitter as being located on both the front surface and inner via holes. In general, these MWT structures involve the additional step of dielectric layer deposition, and other steps to remove the dielectric layer where it is not need. To illustrate,FIG. 2shows a P-N junction having an emitter2that covers the front surface of the substrate1and a dielectric layer12that covers the full inner surface of the via hole3. Additionally,FIG. 3shows a P-N junction having an emitter2that covers the front and full inner surface of the substrate1and a dielectric layer12covering the full inner surface of the via hole3.

Thus, efficient light to current converter devices and processes for making the same are desired.

BRIEF SUMMARY

Processes for making light to current converter devices are provided. In one embodiment, the process may include generating a via hole through a semiconductor substrate of a first conductive type, the via hole extending from a front surface of the semiconductor substrate to a rear surface of the semiconductor substrate. The process may further include forming a textured front surface on the front surface of the semiconductor substrate, forming a textured rear surface on the rear surface of the semiconductor substrate, forming a semiconductor layer of a second conductive type on at least the textured front surface, the textured rear surface, and an inner surface of the via hole, wherein the second conductive type is opposite the first conductive type, and etching the semiconductor layer of the second conductive type, wherein etching the semiconductor layer of the second conductive type includes removing the semiconductor layer of the second conductive type formed on the textured rear surface.

In some embodiments, etching the semiconductor layer of the second conductive type may further include removing at least a portion of the semiconductor layer of the second conductive type formed on the inner surface of the via hole. In other embodiments, etching the semiconductor layer of the second conductive type may further include removing all of the semiconductor layer of the second conductive type formed on the inner surface of the via hole.

In another embodiment, the process may include forming a textured front surface on the front surface of the semiconductor substrate and forming a semiconductor layer of a second conductive type on at least the textured front surface, wherein the second conductive type is opposite the first conductive type. The process may further include generating a via hole through the semiconductor substrate and semiconductor layer of the second conductive type and etching the semiconductor layer of the second conductive type, wherein after etching the semiconductor layer of the second conductive type, the semiconductor layer of the second conductive type is located on only the textured front surface.

In yet another embodiment, the process may include generating a via hole through a semiconductor substrate of a first conductive type, the via hole extending from a front surface of the semiconductor substrate to a rear surface of the semiconductor substrate. The process may further include forming a textured front surface on the front surface of the semiconductor substrate and forming a semiconductor layer of a second conductive type on at least the textured front surface and an inner surface of the via hole, wherein the second conductive type is opposite the first conductive type. The process may further include depositing a barrier layer on the semiconductor layer of the second conductive type formed on the inner surface of the via hole, etching the semiconductor layer of the second conductive type, wherein the barrier layer prevents etching of the semiconductor layer of the second conductive type that is covered by the barrier layer, and wherein after etching the semiconductor layer of the second conductive type, the semiconductor layer of the second conductive type is located on only the textured front surface and the inner surface of the via hole, and removing the barrier layer.

In some embodiments, the process may further include forming a textured rear surface on the rear surface of the semiconductor substrate and forming the semiconductor layer of the second conductive type on the textured rear surface of the semiconductor substrate.

In yet another embodiment, the process may include generating a via hole through a semiconductor substrate of a first conductive type, the via hole extending from a front surface of the semiconductor substrate to a rear surface of the semiconductor substrate. The process may further include forming a textured front surface on the front surface of the semiconductor substrate, forming a textured rear surface on the rear surface of the semiconductor substrate, depositing a barrier layer on the textured rear surface and an inner surface of the via hole, and forming a semiconductor layer of a second conductive type on the semiconductor substrate, wherein the barrier layer prevents formation of the semiconductor layer of the second conductive type on portions of the textured rear surface and the inner surface of the via hole that are covered by the barrier layer, and wherein the second conductive type is opposite the first conductive type. The process may further include removing the barrier layer and etching the semiconductor layer of the second conductive type, wherein after etching the semiconductor layer of the second conductive type, the semiconductor layer of the second conductive type is located on only the textured front surface.

In some embodiments, the barrier layer may be deposited on the textured rear surface such that the barrier layer extends between 0.1 mm to 10 cm from an edge of the via hole. In other embodiments, the barrier layer may be deposited on all of the textured rear surface. In some embodiments, the barrier layer may be deposited on a full inner surface of the via hole.

In yet another embodiment, the process may include generating a via hole through a semiconductor substrate of a first conductive type, the via hole extending from a front surface of the semiconductor substrate to a rear surface of the semiconductor substrate. The process may further include forming a textured front surface on the front surface of the semiconductor substrate, forming a textured rear surface on the rear surface of the semiconductor substrate, depositing a barrier layer on the textured rear surface, removing a portion of the barrier layer around the via hole, and forming a semiconductor layer of a second conductive type on the semiconductor substrate, wherein the barrier layer prevents formation of the semiconductor layer of the second conductive type on portions of the textured rear surface that are covered by the barrier layer, wherein the second conductive type is opposite the first conductive type. The process may further include removing the barrier layer and etching the semiconductor layer of the second conductive type formed on side surfaces of the semiconductor substrate.

In some embodiments, removing a portion of the barrier layer around the via hole may include removing the barrier layer formed within a threshold distance from an edge of the via hole, wherein the threshold distance is between 0.1 mm and 10 cm. In some embodiments, removing a portion of the barrier layer around the via hole may be performed with a chemical erosion paste, wherein the chemical erosion paste is washed away with a lye solvent or ion solvent. In some embodiments, the chemical erosion paste may include ammonium bifluoride or phosphoric acid.

In some examples, the barrier layer described in the embodiments above may be deposited using a printing paste, plasma-enhanced chemical vapor deposition, chemical oxidating, rapid thermal processing, magnetron sputtering, or vacuum evaporating. In some examples, the barrier layer described in the embodiments above may include a polymer resin, silicon resin, silicon oxide, silicon nitride, titanium oxide, or zinc oxide.

In some examples, the barrier layer described in the embodiments above may be removed by washing the barrier layer with lye having a temperature between 20-90° C. and a concentration between 0.05%-10%.

In some examples of the embodiments described above, the processes may further include forming a front electrode operable to collect current from the front surface, the front electrode being electrically coupled to the semiconductor layer of the second conductive type, forming a through-hole electrode disposed at least partially within the via hole and coupled to the front electrode, forming a back electrode electrically coupled to the rear surface of the semiconductor substrate, the back electrode being isolated from the through-hole electrode, and forming an impurity layer on the rear surface of the semiconductor substrate.

In some examples of the embodiments described above, the through-hole electrode may include an inner via hole electrode disposed within the via hole, a via front collector covering at least a portion of a front side of the via hole, the via front collector being coupled to the front electrode and the inner via hole electrode, and a via rear collector covering at least a portion of a rear side of the via hole, the via rear collector being coupled to the inner via hole electrode.

In some examples of the embodiments described above, forming the through-hole electrode may include printing the via front collector on the front surface of the semiconductor substrate, printing the inner via hole electrode into the via hole, printing the via rear collector on the rear surface of the semiconductor substrate, and co-firing the printed via front collector, inner via hole electrode, and via rear collector.

In some examples of the embodiments described above, the processes may further include etching a front side edge of the semiconductor layer of the second conductive type formed on the textured front surface

In some examples of the embodiments described above, the processes may further include removing impurities from the semiconductor substrate after the etching the semiconductor layer of the second conductive type and depositing a film on the front surface of the semiconductor substrate. In some embodiments, the film may include an anti-reflective film.

In some examples of the embodiments described above, generating the via hole through a semiconductor substrate may be performed using a laser. In some examples of the embodiments described above, etching the semiconductor layer of the second conductive type may be performed using a chemical solvent, chemical erosion paste, or plasma gas. In some examples of the embodiments described above, etching using the chemical solvent may be performed by infiltrating the semiconductor layer of the second conductive type with the chemical solvent. In some examples of the embodiments described above, etching using the chemical erosion paste may be performed by printing the chemical erosion paste onto the semiconductor layer of the second conductive type. In some examples of the embodiments described above, etching using the plasma gas may be performed by contacting the semiconductor layer of the second conductive type with the plasma gas.

In some examples of the embodiments described above, the first conductive type may be N-type and the second conductive type may be P-type. In other examples of the embodiments described above, the first conductive type may be P-type and the second conductive type may be N-type.

In some examples of the embodiments described above, forming the textured front surface on the front surface of the semiconductor substrate may include etching the front surface of the semiconductor substrate, and forming the textured rear surface on the rear surface of the semiconductor substrate may include etching the rear surface of the semiconductor substrate.

In some examples of the embodiments described above, etching the semiconductor layer of the second conductive type may further include removing the semiconductor layer of the second conductive type formed on a side surface of the semiconductor substrate. In some examples of the embodiments described above, the processes may further include etching the semiconductor layer of the second conductive type formed on the textured rear surface and the semiconductor layer of the second conductive type formed on the side surface at the same time.

DETAILED DESCRIPTION

As used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural reference unless the context clearly indicates otherwise. Additionally, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, alone or in combination with other elements, components, or steps that are not expressly referenced.

Various embodiments are described below relating to processes for making light to current converter devices, such as solar cells. The processes can be used to make light to current converter devices having P-N junctions located on only the top surface of the cell, located on the top surface and symmetrically along a portion of the inner surface of the via holes, located on the top surface and asymmetrically along a portion of the inner surface of the via holes, located on the top surface and full inner surface of the via holes, or located on the top surface, full inner surface of the via holes, and a portion of the bottom surface of the cell. The processes may isolate the desired P-N junction by etching the emitter, forming a via hole after forming the emitter, using a barrier layer to protect portions of the emitter from etching, or using a barrier layer to prevent the emitter from being formed on portions of the substrate. Light to current converter devices that can be made using the processes are also provided.

FIGS. 4-7illustrate exemplary P-N junctions that may be used in a light to current converter device, such as a solar cell. Unlike the P-N junctions shown inFIGS. 1-3, the exemplary P-N junctions shown inFIGS. 4-7do not include a deposited dielectric layer or an emitter located on the back surface of the substrate. The absence of a back side emitter allows a device having a P-N junction like that shown inFIGS. 4-7to be manufactured without performing double side diffusion or back contact isolation. Additionally, the absence of a deposited dielectric layer allows the device to be manufactured without performing dielectric layer deposition and removal as is required to manufacture the P-N junctions shown inFIGS. 2-3. As a result, a device having a P-N junction similar or identical to those shown inFIGS. 4-7may be cheaper and quicker to manufacture than those having a P-N junction similar to those shown inFIGS. 1-3.

Specifically,FIG. 4illustrates an exemplary P-N junction having an emitter2that covers the front surface of the substrate1and the full inner surface of the via hole3. The substrate1may include monocrystalline silicon or polycrystalline silicon having a first doping type (e.g., P or N) while the emitter2may have an opposite doping type (e.g., N or P). In this example, since the emitter2may not cover the backside of substrate1, the backside of substrate1may remain the same doping type as substrate1. In other examples, other types of opposite conductivity type semiconductors may be used for substrate1and emitter2.

FIG. 5illustrates another exemplary P-N junction having an emitter2that covers the front surface of the substrate1and symmetrically covers a portion of the inner surface of the via hole3. The substrate1may include monocrystalline silicon or polycrystalline silicon having a first doping type (e.g., P or N) while the emitter2may have an opposite doping type (e.g., N or P). In this example, since the emitter2may not cover a portion of the inner surface of via hole3and the backside of substrate1, the uncovered portion of the inner surface of via hole3and the backside of substrate1may remain the same doping type as substrate1.

FIG. 6illustrates yet another exemplary P-N junction having an emitter2that covers the front surface of the substrate1and asymmetrically covers a portion of the inner surface of the via hole3. The substrate1may include monocrystalline silicon or polycrystalline silicon having a first doping type (e.g., P or N) while the emitter2may have an opposite doping type (e.g., N or P). In this example, since the emitter2may not cover a portion of the inner surface of via hole3and the backside of substrate1, the uncovered portion of the inner surface of via hole3and the backside of substrate1may remain the same doping type as substrate1.

FIG. 7illustrates yet another exemplary P-N junction having an emitter2that covers only the front surface of the substrate1. The substrate1may include monocrystalline silicon or polycrystalline silicon having a first doping type (e.g., P or N) while the emitter2may have an opposite doping type (e.g., N or P). In this example, since the emitter2may not cover the inner surface of via hole3and the backside of substrate1, the inner surface of via hole3and the backside of substrate1may remain the same doping type as substrate1.

Exemplary processes for manufacturing light to current converter devices having exemplary P-N junctions similar or identical to those shown in FIGS.1and4-7are described below with respect toFIGS. 8-54.

FIG. 8illustrates an exemplary process80that may be used to make light to current converter devices, such as those described above. In particular, exemplary process80may be used to manufacture devices having P-N junctions similar or identical to those shown inFIGS. 4-7. Various embodiments of process80are described below with reference to figures showing exemplary light to current converter devices at various stages of manufacture.

In the first example, process80may be used to make exemplary light to current converter device90(and devices similar to light to current converter device90), as shown inFIG. 9. Device90includes a P-N junction similar to that shown inFIG. 4.

At block81of process80, and as shown inFIG. 10, vias may be opened into a semiconductor substrate. Specifically, a via hole3having an inner hole wall31may be formed in a P-type or N-type semiconductor substrate1. In some examples, the semiconductor substrate1may have a resistance between 0.5-3 Ω-cm. The via hole3may be formed by applying a laser having a wavelength of 1064 nm, 1030 nm, 532 nm, 355 nm, or other appropriate wavelength to the semiconductor substrate. However, it should be appreciated that other known processes may be used to form via hole3, such as mechanical drilling or chemical corroding. Additionally, the size and shape of via hole3can be varied depending on the particular application. For example, the via hole3may be a square, rectangle, circle, and the like.

At block82, and as shown inFIG. 11, the surface of substrate1may be textured. Specifically, in some examples, an acid or alkali solution may be applied to the top surface25(front surface) and bottom surface27(rear surface) of the substrate1to form textured surface23. In other examples, only the top surface25of substrate1may be textured. The textured surface23may include, for example, an irregular surface having concave or pyramid shaped protrusions having a height of about 1-7 μm. This may be done to improve light absorption. Additionally, the acid or alkali solution may be used to remove residue caused by the laser within via hole3. In some examples, the surface of substrate1may be cleaned to remove dirt and metal impurities prior to texturing surfaces25and27.

At block83, and as shown inFIG. 12, the emitter may be formed. Specifically, the emitter2may be formed on the surface of the P-type or N-type semiconductor substrate1. In some examples, the emitter2may be formed on the top surface25/textured surface23, back surface27/textured surface23, the inner hole wall31, and sides of substrate1. In other examples, the emitter2may be formed on the top surface25/textured surface23, the inner hole wall31, and sides of substrate1. In some examples, the emitter2may be formed by introducing N-type impurities into the surfaces of the P-type semiconductor substrate1or by introducing P-type impurities into the surfaces of the N-type semiconductor substrate1. It should be appreciated that the process for forming N-type or P-type emitter2is not limited to the example described above, and that the emitter2may be formed, for example, by high temperature diffusion of POCL3or BBR3into the surface of substrate1or by implanting N-type impurities or P-type impurities into the P-type or N-type semiconductor substrate1. The performance of device90depends at least in part on the density, deepness, and uniformity of the diffusion.

At block84, and as shown inFIG. 13, the silicon may be etched. Specifically, etching may be performed on the front side edge35, back side27, and side surfaces of substrate1, and may be performed at the same time. In some examples, the etching may be performed using an acid or alkali solution, such as HF/HNO3 acid. In these examples, the device may float on the top of the solution with a portion of the silicon semiconductor contacting the solution. In this way, the submerged portions of the device (e.g., back side emitter2) may be removed, while leaving the P-N junction formed within via hole3and on the top surface of substrate1intact. Additionally or alternatively, etching may be performed using a chemical erosion paste. In these examples, the chemical pastes may be coated or printed on the surface of the front side edge emitter35, bottom surface27of substrate1, and sides of substrate1. In this way, the front side edge emitter35, back side emitter2, and side surface emitter2may be selectively removed while leaving the remaining P-N junction intact. In some examples, the silicon semiconductor may be dried at room temperature for about 3 minutes, after which it may be cleaned using water at about 30° C. to complete the etching process. In yet other examples, the etching may be performed using other known processes, for example, by using a reactive plasma, such as SF6, O2, N2, and the like. In some examples, the emitter may be exposed to the reactive plasma for about 15 minutes. In these examples, the flow of SF6, may be about 200 sccm, the flow of O2may be about 30 sccm, the flow of N2may be about 300 sccm, the pressure may be about 50 Pa, and the power of the glow discharge may be about 700 W.

At block85, phosphor-silicate glass (PSG) may be removed using any known PSG removal process.

At block86, and as shown inFIG. 14, an anti-reflective film may be deposited to reduce the amount of light reflection and increase the utilization ratio of the light. Specifically, an anti-reflective film4may be formed on the N-type or P-type emitter2. In some examples, the anti-reflective film4may include SiN, SiO2/SiN, two layers of SiN, three layers of SiN, Si3N4, TiO2, or the like. In some examples, the anti-reflective film4may be formed, for example, by using a plasma chemical vapor deposition process. The surface of the front side emitter2may also be textured to improve the light-trapping properties of the cell. For example, the surface may be textured with a random arrangement of pyramids, inversed pyramids, honeycomb structures, and the like. Using these structures, a ray of light may be reflected toward a neighboring structure resulting in a greater amount of light absorption. To further improve the absorption of light, the light-trapping surface may be optically dark or black.

At block87, and as shown inFIG. 15, contacts, or electrodes, and impurity layers may be formed. Specifically, some or all of the front electrodes5(not shown), rear electrodes7, via hole electrode9, via front collector10, via rear collector8, and impurity layer6may be formed at the same or at different times, and may be formed using printing-firing methods, deposition methods, plating methods, vacuum evaporating methods, spurting methods, or any other known process. For instance, in some printing-firing examples, front electrodes5(not shown), rear electrodes7, via hole electrode9, via front collector10, via rear collector8, and impurity layer6may be formed by screen printing, stencil printing, or the like, using a conductive paste composed mainly of glass frit and a conductive metal powder, such as silver, aluminum, copper, nickel, or the like. As discussed in greater detail below, the conductive paste may be fired at about 500 to 900° C. to form the electrode. There are many commercially available conductive pastes that are suitable for forming electrodes in a solar cell. For example, DuPont Microcircuit Materials has several types of silver-based DuPont Solamet photovoltaic metallization pastes for specific applications, including Solamet PV17A, PV16x, PVD2A, PV173, PV502, PV505, PV506, and PV701, as described by the website at http://www2.dupont.com/Photovoltaics/en_US/assets/downloads/pdf/PV_SolametProductOverview. pdf of Dupont. Targray Technology International Inc. of Canada also offers many types of the HeraSol Ag Paste compositions, including SOL953, SOL953, SOL90235H, SOL9273M, SOL9318, SOL230, CL80-9381M, CL80-9383M, SOL108, and SOL9400, as described by the website at http://www.targray.com/solar/cystalline-cell-materials/silver-paste.php of Targray. Furthermore, some suppliers can customize their pastes to the specific manufacturing process to increase efficiency and provide wider processing windows. While specific pastes have been provided above, it should be appreciated that other known pastes may be used.

In some examples, such as that shown inFIG. 57, front electrodes5, via front collector10, via hole electrode9, and via rear collector8may be formed from the same material. In other examples, such as those shown inFIGS. 55,58,60, and61, some or all of front electrodes5, via front collector10, via hole electrode9, and via rear collector8may be formed from the same or different materials. Additionally, as shown inFIG. 61, one or more of front electrodes5, via front collector10, via hole electrode9, and via rear collector8may be formed from more than one type of material. Rear electrodes7can be formed from the same or a different material as via front collector10, via hole electrode9, and via rear collector8. For instance, in some examples, front electrodes5(not shown), via hole electrode9, via front collector10, via rear collector8, may formed be using a printing-firing method and may be made of silver. Rear electrodes7may also be formed using a printing-firing method but may be made of aluminum. In other examples, front electrodes5(not shown), via hole electrode9, via front collector10, via rear collector8may be made of aluminum while rear electrodes7may be made of silver.

Additionally, any one or more of via front collector10, via hole electrode9, and via rear collector8may be fully filled or hollow in shape. For example, as shown inFIG. 55, each of via front collector10, via hole electrode9, and via rear collector8may be fully filled. In some examples, this may be done by printing a fully filled via front collector10onto the surface of substrate1, printing a fully filled via hole electrode9into via hole3, and printing a fully filled via rear collector8onto the surface of substrate1. In other examples, this may be done by printing a fully filled via front collector10onto the surface of substrate1, inserting a fully filled via hole electrode9into via hole3, and covering the bottom of via hole3with a fully filled via rear collector8. In some examples, such as those shown inFIGS. 57,58, and61, each of via front collector10, via hole electrode9, and via rear collector8may be hollow. This may be done by printing a hollow front collector10onto the surface of substrate1, printing a hollow via hole electrode9into via hole3, and printing a hollow via rear collector8on the bottom of via hole3. In yet other examples, such as those shown inFIG. 60, some of via front collector10, via hole electrode9, and via rear collector8may be fully filled while the remaining components are hollow. This may be done by printing a fully filled or hollow front collector10onto the surface of substrate1, printing a fully filled or hollow via hole electrode9into via hole3, and printing the bottom of via hole3with a fully filled or hollow via rear collector8.

At block88, the device may be co-fired, for example, between 500-900° C., to alloy together the electrodes that were printed on substrate1at block87.

Using exemplary process80, device90may be formed having no P-N junction on the back side of the device and without performing a separate laser isolation step to isolate the back surface from the via hole.

It should be appreciated by one or ordinary skill that the above described process may be used to make light to current converter devices having any combination of materials for impurity layer6, front electrodes5, rear electrodes7, via hole electrode9, via front collector10, and via rear collector8, and having a hole through all, a portion, or none of via hole electrode9, via front collector10, and via rear collector8, such as those shown inFIGS. 55,57,58,60, and61.

In the second example, process80may be used to make exemplary light to current converter device160(and devices similar to light to current converter device160), as shown inFIG. 16. Device160includes a P-N junction similar to that shown inFIG. 5.

In the second example, blocks81-83may be similar or identical to blocks81-83described above with respect toFIGS. 10-12of the first example. At block84, and as shown inFIG. 17, the silicon may be etched in a manner similar, but not identical, to that described above with respect toFIG. 13. Specifically, the front side edge35etching (not shown), back side27etching, side surface etching, and a portion of inner hole emitter2etching may be performed, and may be performed at the same time.

At block85, PSG may be removed using any known PSG removal process.

At block86, and as shown inFIG. 18, an anti-reflective film may be deposited to reduce the amount of light reflection and increase the utilization ratio of the light. Specifically, an anti-reflective film4may be formed on the N-type or P-type emitter2in a manner similar to that described above with respect toFIG. 14. The surface of the front side emitter2may also be textured to improve the light-trapping properties of the cell in a manner similar to that described above with respect toFIG. 14.

At blocks87and88, and as shown inFIG. 19, contacts, or electrodes, and impurity layers may be formed. Specifically, the front electrodes5(not shown), rear electrodes7, via hole electrode9, via front collector10, via rear collector8, and impurity layer6may be formed in a manner similar to that described above with respect toFIG. 15. For instance, the electrodes and impurity layers may be screen printed, stencil printed, vacuum evaporated, or spurted onto substrate1and co-fired to alloy together the electrodes deposited on substrate1.

Using exemplary process80, device160may be formed having no P-N junction on the back side of the device and without performing a separate laser isolation step to isolate the back surface from the via hole.

It should be appreciated by one or ordinary skill that the above described process may be used to make light to current converter devices having any combination of materials for front electrodes5, rear electrodes7, via hole electrode9, via front collector10, and via rear collector8, and having a hole through all, a portion, or none of via hole electrode9, via front collector10, and via rear collector8, such as those shown inFIGS. 56 and 59.

In the third example, process80may be used to make exemplary light to current converter device200(and devices similar to light to current converter device200), as shown inFIG. 20. Device200includes a P-N junction similar to that shown inFIG. 7.

In the third example, blocks81-83may be similar or identical to blocks81-83described above with respect toFIGS. 10-12of the first example. At block84, and as shown inFIG. 21, the silicon may be etched in a manner similar, but not identical, to that described above with respect toFIG. 13. Specifically, the front side edge35etching (not shown), back side27etching, side surface etching, and inner via hole3etching may be performed, and may be performed at the same time.

At block85, PSG may be removed using any known PSG removal process.

At block86, and as shown inFIG. 22, an anti-reflective film may be deposited to reduce the amount of light reflection and increase the utilization ratio of the light. Specifically, an anti-reflective film4may be formed on the N-type or P-type emitter2in a manner similar to that described above with respect toFIG. 14. The surface of the front side emitter2may also be textured to improve the light-trapping properties of the cell in a manner similar to that described above with respect toFIG. 14.

At blocks87and88, and as shown inFIG. 23, contacts, or electrodes, and impurity layers may be formed. Specifically, the front electrodes5(not shown), rear electrodes7, via hole electrode9, via front collector10, via rear collector8, and impurity layer6may be formed in a manner similar to that described above with respect toFIG. 15. For instance, the electrodes and impurity layers may be screen printed, stencil printed, vacuum evaporated, or spurted onto substrate1and co-fired to alloy together the electrodes deposited on substrate1.

Using exemplary process80, device200may be formed having no P-N junction on the back side of the device and without performing a separate laser isolation step to isolate the back surface from the via hole.

It should be appreciated by one or ordinary skill that the above described process may be used to make light to current converter devices having any combination of materials for front electrodes5, rear electrodes7, via hole electrode9, via front collector10, and via rear collector8, and having a hole through all, a portion, or none of via hole electrode9, via front collector10, and via rear collector8, such as those shown inFIGS. 62-67.

FIG. 24illustrates another exemplary process240that may be used to make light to current converter devices, such as those described above. In particular, exemplary process240may be used to manufacture devices having P-N junctions similar or identical to those shown inFIG. 7. Various embodiments of process240are described below with reference to figures showing exemplary light to current converter devices at various stages of manufacture.

In the first example, process240may be used to make exemplary light to current converter device200(and devices similar to light to current converter device200), as shown inFIG. 20. Device200includes a P-N junction similar to that shown inFIG. 7.

At block241of process240, and as shown inFIG. 25, the surface of substrate1may be textured. Specifically, an acid or alkali solution may be applied to the top surface25of the substrate1to form textured surface23. The textured surface23may include, for example, an irregular surface having concave or pyramid shaped protrusions having a height of about 1-7 μm. This may be done to improve light absorption. Additionally, the acid or alkali solution may be used to remove residue caused by the laser within via hole3. In some examples, the surface of substrate1may be cleaned to remove dirt and metal impurities prior to texturing surface25. In some examples, the semiconductor substrate1may have a resistance between 0.5-3 Ω/cm.

At block242, and as shown inFIG. 26, the emitter may be formed. Specifically, the emitter2may be formed on the surface of the P-type or N-type semiconductor substrate1. For example, the emitter2may be formed on the top surface25/textured surface23and sides of substrate1in a manner similar to that described above with respect to block83, as shown inFIG. 12.

At block243, and as shown inFIG. 27, vias may be opened into a semiconductor substrate in a manner similar to that described above with respect to block81of process80, as shown inFIG. 10.

At block244, and as shown inFIG. 18, the silicon may be etched in a manner similar, but not identical, to that described above with respect toFIG. 13. Specifically, the front side edge35etching (not shown) and side etching may be performed.

At block245, PSG may be removed using any known PSG removal process.

At block246, and as shown inFIG. 29, an anti-reflective film may be deposited to reduce the amount of light reflection and increase the utilization ratio of the light. Specifically, an anti-reflective film4may be formed on the N-type or P-type emitter2in a manner similar to that described above with respect toFIG. 14. The surface of the front side emitter2may also be textured to improve the light-trapping properties of the cell in a manner similar to that described above with respect toFIG. 14.

At block247, and as shown inFIG. 30, contacts, or electrodes, and impurity layers may be formed. Specifically, the front electrodes5(not shown), rear electrodes7, via hole electrode9, via front collector10, via rear collector8, and impurity layers6may be formed in a manner similar to that described above with respect toFIG. 15. For instance, the electrodes and impurity layers may be screen printed, vacuum evaporated, or spurted onto substrate1and co-fired to alloy together the electrodes deposited on substrate1.

Using exemplary process240, device200may be formed having no P-N junction on the back side of the device and without performing a separate laser isolation step to isolate the back surface from the via hole.

It should be appreciated by one or ordinary skill that the above described process may be used to make light to current converter devices having any combination of materials for front electrodes5, rear electrodes7, via hole electrode9, via front collector10, and via rear collector8, and having a hole through all, a portion, or none of via hole electrode9, via front collector10, and via rear collector8, such as those shown inFIGS. 62-67.

FIGS. 31-33illustrate a second example of process240for making exemplary light to current converter device200(and devices similar to light to current converter device200) having a P-N junction similar to that shown inFIG. 7.

At block241of process240, and as shown inFIG. 31, the surface of substrate1may be textured. Specifically, an acid or alkali solution may be applied to the top surface25and bottom surface27of the substrate1to form textured surface23. The textured surface23may include, for example, an irregular surface having concave or pyramid shaped protrusions having a height of about 1-7 μm. This may be done to improve light absorption. Additionally, the acid or alkali solution may be used to remove residue caused by the laser within via hole3. In some examples, the surface of substrate1may be cleaned to remove dirt and metal impurities prior to texturing surfaces25and27. In some examples, the semiconductor substrate1may have a resistance between 0.5-3 Ω/cm.

At block242, and as shown inFIG. 32, the emitter may be formed. Specifically, the emitter2may be formed on the surface of the P-type or N-type semiconductor substrate1. For example, the emitter2may be formed on the top surface25/textured surface23, bottom surface27/textured surface23, and sides of substrate1in a manner similar to that described above with respect to block83, as shown inFIG. 12.

At block243, and as shown inFIG. 33, vias may be opened into a semiconductor substrate in a manner similar, but not identical, to that described above with respect toFIG. 10.

In this second example, block244may be similar to block244described above with respect toFIG. 28. However, in addition to the front side edge35etching (not shown) and side etching performed in the first example described above with respect toFIG. 28, back side27etching may also be performed.

In this second example, blocks245-247may be similar or identical to blocks245-247described above with respect toFIGS. 29-30of the first example.

Using exemplary process240, device200may be formed having no P-N junction on the back side of the device and without performing a separate laser isolation step to isolate the back surface from the via hole.

It should be appreciated by one or ordinary skill that the above described process may be used to make light to current converter devices having any combination of materials for front electrodes5, rear electrodes7, via hole electrode9, via front collector10, and via rear collector8, and having a hole through all, a portion, or none of via hole electrode9, via front collector10, and via rear collector8, such as those shown inFIGS. 62-67.

FIG. 34illustrates another exemplary process340that may be used to make light to current converter devices, such as those described above. In particular, exemplary process340may be used to manufacture exemplary light to current converter device90(and devices similar to light to current converter device90), as shown inFIG. 9. Device90includes a P-N junction similar to that shown inFIG. 4. Process340is described below with reference to figures showing exemplary light to current converter device90at various stages of manufacture.

In the second example, blocks341-342may be similar to blocks81-82of exemplary process80described above with respect toFIGS. 10-11. However, at block343, and as shown inFIG. 35, the emitter may be formed in a manner similar, but not identical, to that described above with respect toFIG. 12. Specifically, in some examples, the emitter2may be formed on the top surface25/textured surface23, side surfaces, and the inner hole wall31of substrate1. In other examples, the emitter2may be formed on the top surface25/textured surface23, back surface27/textured surface23, side surfaces, and the inner hole wall31of substrate1.

At block344, and as shown inFIG. 36, a barrier layer may be deposited. Specifically, a barrier layer33may be deposited on the inner hole wall31of semiconductor substrate1. In some examples, barrier layer33may include silicon oxide, silicon resin, silicon nitride, other silicon material, titanium oxide, zinc oxide, or the like. In some examples, the barrier layer33may be deposited using processes, such as printing paste deposition, plasma-enhanced chemical vapor deposition, chemical oxidating, rapid thermal processing, magnetron sputtering, vacuum evaporating, and the like. In some examples, barrier layer33may include silicon oxide having a thickness of about 70 nm and may be deposited using plasma-enhanced chemical vapor deposition. During deposition, the temperature may be about 500° C., the flow of N2O may be about 7 slm, the flow of SiH4may be about 200 sccm, the pressure may be about 10 mTorr, and the time for depositing may be about 9 minutes.

At block345, and as shown inFIG. 37, the silicon may be etched and the barrier layer may be removed. Specifically, front side edge35(not shown) may be etched into emitter2and textured surface23using a chemical solution, such as HF/HNO3. Additionally, back side27etching and side surface etching may be performed, and may be performed at the same time. In some examples, the etching may be performed using an acid or alkali solution. In these examples, the device may float on the top of solution with a portion of the silicon semiconductor contacting the solution. In this way, the submerged portions of the device (e.g., back side emitter2and side surface emitter2) may be removed, while leaving the P-N junction formed within via hole3and on the top surface of substrate1. In these examples, the barrier layer33may protect the P-N junction within via hole3from being etched away. Additionally or alternatively, etching may be performed using a chemical erosion paste. In these examples, the chemical pastes may be coated or printed on the surface of the front side edge emitter35, bottom surface27of substrate1, and side of substrate1. In this way, the front side edge emitter35and back side emitter2, and side surface emitter2may be selectively removed while leaving the remaining P-N junction intact. In yet other examples, the etching may be performed using other known processes, for example, by using a reactive plasma, such as SF6, O2, N2, and the like. In some examples, the emitter may be exposed to the reactive plasma for about 15 minutes. In these examples, the flow of SF6, may be about 200 sccm, the flow of O2may be about 30 sccm, the flow of N2may be about 300 sccm, the pressure may be about 50 Pa, and the power of the glow discharge may be about 700 W. The barrier layer33may then be removed using a chemical etching process, with the chemical solution depending on the material used for barrier layer33. For example, lye having a temperature of about 20° C.-90° C. and a concentration of 0.05%-10% may be used.

Blocks346-348may be similar to blocks85-88of exemplary process80described above with respect toFIGS. 14-15.

Using exemplary process340, device90may be formed having no P-N junction on the back side of the device and without performing a separate laser isolation step to isolate the back surface from the via hole.

It should be appreciated by one or ordinary skill that the above described process may be used to make light to current converter devices having any combination of materials for front electrodes5, rear electrodes7, via hole electrode9, via front collector10, and via rear collector8, and having a hole through all, a portion, or none of via hole electrode9, via front collector10, and via rear collector8, such as those shown inFIGS. 55,57,58,60, and61.

FIG. 38illustrates another exemplary process380that may be used to make light to current converter devices, such as those described above. In particular, exemplary process380may be used to manufacture exemplary light to current converter device200(and devices similar to light to current converter device200) having a P-N junction similar to that shown inFIG. 7. Process380is described below with reference to figures showing exemplary light to current converter device200at various stages of manufacture.

Blocks381-382of process380may be similar or identical to blocks81-82of exemplary process80described above with respect toFIGS. 10-11. However, at block383, and as shown inFIG. 39, a barrier layer may be deposited in a manner similar, but not identical, to that described above with respect block344and shown inFIG. 36. Specifically, a barrier layer33may be deposited on the back surface27/textured surface23and the inner hole wall31of semiconductor substrate1. In some examples, barrier layer33may include silicon oxide, silicon resin, silicon nitride, other silicon material, titanium oxide, zinc oxide, or the like. In some examples, the barrier layer33may be deposited using processes, such as printing paste deposition, plasma-enhanced chemical vapor deposition, chemical oxidating, rapid thermal processing, magnetron sputtering, vacuum evaporating, and the like. In some examples, barrier layer33may include silicon oxide having a thickness of about 70 nm and may be deposited using plasma-enhanced chemical vapor deposition. During deposition, the temperature may be about 500° C., the flow of N2O may be about 7 slm, the flow of SiH4may be about 200 sccm, the pressure may be about 10 mTorr, and the time for depositing may be about 9 minutes.

At block384, and as shown inFIG. 40, the emitter may be formed. Specifically, the emitter2may be formed on the surface of the P-type or N-type semiconductor substrate1. For example, the emitter2may be formed on the top surface25/textured surface23and side surfaces of substrate1by introducing N-type impurities into the surfaces of the P-type semiconductor substrate1or by introducing P-type impurities into the surfaces of the N-type semiconductor substrate1. The barrier layer33prevents the emitter2from being formed on the back surface27/textured surface23and the inner hole wall31of semiconductor substrate1. It should be appreciated that the process for forming N-type or P-type emitter2is not limited to the example described above, and that the emitter2may be formed, for example, by high temperature diffusing of POCL3or BBR3into the surface of substrate1or by implanting N-type impurities or P-type impurities into the P-type or N-type semiconductor substrate1. The performance of device730depends at least in part on the density, deepness, and uniformity of the diffusion.

At block385, and as shown inFIG. 41, the barrier layer may be removed in a manner similar to that described above with respect to block345, as shown inFIG. 37.

At block386, and as shown inFIG. 42, the silicon may be etched. Specifically, the front side edge35etching (not shown), back side27etching, and side surface etching may be performed in a manner similar to that described above with respect to block84, and as shown inFIG. 13.

Using exemplary process380, device200may be formed having no P-N junction on the back side of the device and without performing a separate laser isolation step to isolate the back surface from the via hole.

It should be appreciated by one or ordinary skill that the above described process may be used to make light to current converter devices having any combination of materials for front electrodes5, rear electrodes7, via hole electrode9, via front collector10, and via rear collector8, and having a hole through all, a portion, or none of via hole electrode9, via front collector10, and via rear collector8, such as those shown inFIGS. 62-67.

FIGS. 43-45illustrate a second example of process380for making exemplary light to current converter device200(and devices similar to light to current converter device200) having a P-N junction similar to that shown inFIG. 7.

Blocks381-382of process380may be similar or identical to blocks81-82of exemplary process80described above with respect toFIGS. 10-11. However, at block383, and as shown inFIG. 43, a barrier layer may be deposited in a manner similar, but not identical, to that described above with respect block344and shown inFIG. 36. Specifically, the barrier layer may be formed on the inner hole wall31and a portion of back surface27/textured surface23of semiconductor substrate1. In some examples, barrier layer33may extend about 0.1 mm to 10 cm from the edge of via hole3.

At block384, and as shown inFIG. 44, the emitter may be formed in a manner similar to that described above with respect to block83, as shown inFIG. 12. However, the barrier layer33may prevent the emitter from being formed no the inner surface of via hole3and the portion of back surface27/textured surface23covered by barrier layer33.

At blocks385and386, and as shown inFIG. 45, the barrier layer may be removed in a manner similar to that described above with respect to block345of exemplary process340, as shown inFIG. 37. The silicon may then be etched in a manner similar to that described above with respect to block345of exemplary process340, as shown inFIG. 37.

Using exemplary process380, device200may be formed having no P-N junction on the back side of the device and without performing a separate laser isolation step to isolate the back surface from the via hole.

It should be appreciated by one or ordinary skill that the above described process may be used to make light to current converter devices having any combination of materials for front electrodes5, rear electrodes7, via hole electrode9, via front collector10, and via rear collector8, and having a hole through all, a portion, or none of via hole electrode9, via front collector10, and via rear collector8, such as those shown inFIGS. 62-67.

FIG. 46illustrates another exemplary process460that may be used to make light to current converter devices, such as those described above. In particular, exemplary process460may be used to manufacture exemplary light to current converter device471(and devices similar to light to current converter device471) having a P-N junction similar to that shown inFIG. 1. Process460is described below with reference to figures showing exemplary light to current converter device471at various stages of manufacture.

Blocks461-462of process460may be similar or identical to blocks81-82of exemplary process80described above with respect toFIGS. 10-11. At block463, and as shown inFIG. 48, a barrier layer may be deposited in a manner similar to that described above with respect toFIG. 36. However, at block463, the barrier layer33may be deposited on only the back surface27/textured surface23of semiconductor substrate1.

At block464, and as shown inFIG. 49, a portion of the barrier layer33around vias3may be removed. In some examples, the barrier layer33within 0.1 mm to 10 cm from the edge of vias3may be removed. The barrier layer33may be removed in a manner similar to that described above with respect to block345, as shown inFIG. 37. For example, a chemical erosion paste may be printed onto the portion of barrier layer33to be removed and the substrate1may be dried for about 3 minutes. After that time, water at about 30° C. may be used to wash the substrate. In some examples, the chemical erosion paste may include ammonium bifluoride or phosphoric acid.

At block465, and as shown inFIG. 50, the emitter may be formed in a manner similar to that described above with respect to block83, as shown inFIG. 12. Specifically, the emitter2may be formed on the top surface25/textured surface23, side surfaces of substrate1, full inner surface of vias3, and a portion of back surface27/textured surface23that is not covered by barrier layer33.

At block466, and as shown inFIG. 51, the remaining barrier layer33may be removed in a manner similar to that described above with respect to with respect to block345, as shown inFIG. 37. After removal of barrier layer33, the emitter2located on the side surfaces, top surface25, and bottom surface27of the substrate1may remain.

At block467, and as shown inFIG. 52the silicon may be etched in a manner similar to that described above with respect to block84, as shown inFIG. 13. Specifically, the side surfaces of substrate1may be etched away.

Using exemplary process460, device471may be formed having a P-N junction on only a portion of the back side of the device and without performing a separate laser isolation step to isolate the back surface from the via hole.

It should be appreciated by one or ordinary skill that the above described process may be used to make light to current converter devices having any combination of materials for front electrodes5, rear electrodes7, via hole electrode9, via front collector10, and via rear collector8, and having a hole through all, a portion, or none of via hole electrode9, via front collector10, and via rear collector8.

Various embodiments of light to current converter devices having exemplary P-N junctions similar or identical to those shown inFIGS. 4-7and that may be made using the processes described above are described with respect toFIGS. 55-68.

FIG. 55illustrates an exemplary light to current converter device550having a P-N junction similar to that shown inFIG. 4and that may be made using exemplary processes80and340. Specifically, device550includes a P-type or N-type semiconductor substrate1with one or more via holes3(e.g., 9, 13, 20, 25, 40, 48, 60, or 80 via holes3) penetrating the substrate1. An N-type (for P-type substrate1) or P-type (for N-type substrate1) emitter2may be formed on the front surface of the substrate1and the full inner surface of the via hole3.

Device550may further include front electrodes5and one or more anti-reflective films4, for example, one or more layers of SiN, SiO2/SiN, Si3N4, TiO2, SiNx, or the like. The one or more anti-reflective films4may be used to absorb additional light and improve light conversion efficiency. A via front collector10(electrode) may also be placed on a portion of emitter2and above via hole3. Via hole3may be at least partially filled with a via hole electrode9that is electrically coupled to via front collector10and a via rear collector8(electrode) that may be disposed below via hole3. Via front collector10, via hole electrode9(electrode), and via rear collector8may collectively be referred to herein as a “through-hole electrode.” Device550may further include rear electrodes7(or back electrodes) disposed below substrate1. Front electrodes5, via front collector10, inner via hole electrode9, via rear collector8, and rear electrodes7may be made of any conductive material, such as metals, alloys, conductive pastes, conductive compounds, conductive films, or the like. In some examples, commercially available conductive pastes suitable for forming electrodes in a solar cell may be used. For example, DuPont Microcircuit Materials of the United States offers several types of silver-based DuPont Solamet photovoltaic metallization pastes, including Solamet PV17A, PV16x, PVD2A, PV173, PV502, PV505, PV506, and PV701, as described by the website at http://www2.dupont.com/Photovoltaics/en_US/assets/downloads/pdf/PV_SolametProductOverview. pdf of Dupont. Targray Technology International Inc. of Canada also offers many types of the HeraSol Ag Paste compositions, including SOL953, SOL953, SOL90235H, SOL9273M, SOL9318, SOL230, CL80-9381M, CL80-9383M, SOL108, and SOL9400, as described by the website at http://www.targray.com/solar/cystalline-cell-materials/silver-paste.php of Targray. Furthermore, some suppliers can customize their pastes to the specific manufacturing process to increase efficiency and provide wider processing windows. While specific pastes have been provided above, it should be appreciated that other known pastes may be used.

Additionally, front electrodes5, via front collector10, inner via hole electrode9, via rear collector8, and rear electrodes7may be made from the same or different materials, and may each be made of one or more materials. For instance, in some examples, front electrodes5, via front collector10, inner via hole electrode9, and via rear collector8may be made of silver, while the rear electrodes7may be made of aluminum, or vice versa. In other examples, front electrodes5, via front collector10, inner via hole electrode9, and via rear collector8may be made of aluminum, while the rear electrodes7may be made of silver. Moreover, the via front collector10, the inner via hole electrode9, and the via rear collector8can be hollow, partially filled, or fully filled, and may form a unitary body or may form multiple segments. In the example shown inFIG. 55, the via front collector10, the inner via hole electrode9, and the via rear collector8are fully filled.

Front electrodes5, via front collector10, inner via hole electrode9, and the via rear collector8may be coupled together such that during operation, electric current may be generated by the light receiving surface of device550and directed to via front collector10by front electrodes5. From via front collector10, the current may be directed through via hole electrode9to via rear collector8. Rear electrodes7may be electrically isolated from via rear collector8and may collect opposite conductivity current on the back surface of device550. In this way, electrodes of opposite conductivity may be placed on the same side (back surface) of device550without interfering with light absorption on the front surface of the device.

Device550may further include impurity layer6. In some examples, an N+(for N-type substrate1) or P+(for P-type substrate1) impurity layer6may be positioned on the bottom of substrate1to form a back surface field. In other examples, impurity layer6may include an N+(for N-type substrate1) doping region, P+(for P-type substrate1) doping region, SiNx, SiO2, or combinations thereof. Device550may further include light-trapping structures on the light-receiving surface of the device. In some examples, the surface may be textured with a random arrangement of pyramids, inversed pyramids, honeycomb structures, and the like. Using these structures, a ray of light may be reflected toward a neighboring structure resulting in a greater amount of light absorption. To further improve the absorption of light, the light-trapping surface may be optically dark or black.

FIG. 56illustrates another exemplary light to current converter device560having a P-N junction similar to that shown inFIG. 5and that may be made using exemplary process80. Device560may be similar to device550, except that the emitter2may symmetrically cover only a portion of the inner surface of the via hole3.

FIG. 57illustrates another exemplary light to current converter device570having a P-N junction similar to that shown inFIG. 4and that may be made using exemplary processes80and340. Device570may include features similar to device550, except that via front collector10, via hole electrode9, and a via rear collector8of device570may be hollow. Additionally, in the illustrated example, front electrodes5, via front collector10, via hole electrode9, and via rear collector8may be made from the same material.

FIG. 58illustrates another exemplary light to current converter device580having a P-N junction similar to that shown inFIG. 4and that may be made using exemplary processes80and340. Device580may be similar to device570, except that in device580, front electrodes5may be made from the same material as via front collector10, while via hole electrode9may be made from the same material as via rear collector8.

FIG. 59illustrates another exemplary light to current converter device590having a P-N junction similar to that shown inFIG. 5and that may be made using exemplary process80. Device590may be similar to device560, except that in device590, front electrodes5, via front collector10, and via hole electrode9may be made from the same material while via rear collector8may be made from a different material.

FIG. 60illustrates another exemplary light to current converter device600having a P-N junction similar to that shown inFIG. 4and that may be made using exemplary processes80and340. Device600may be similar to device550, except that in device600, via front collector10and via hole electrode9may be hollow while via rear collector8is fully filled. Additionally, front electrodes5may be made from a first material, via front collector10and via rear collector8may be made from a second material, and via hole electrode9may be made from a third material.

FIG. 61illustrates another exemplary light to current converter device610having a P-N junction similar to that shown inFIG. 4and that may be made using exemplary processes80and340. Device610may be similar to device570, except that in device610, front electrodes5, via front collector10, and a portion of via hole electrode9may be made from the same material, while the remaining portion of via hole electrode9and via rear collector8may be made from a different material. Additionally, impurity layer6may include a layer of SiNx and SiO2.

FIG. 62illustrates an exemplary light to current converter device620having a P-N junction similar to that shown inFIG. 7and that may be made using exemplary processes80,340, and380. Device620may be similar to device550, except that the emitter2covers only the front surface of substrate1and does not cover the inner surface of the via hole3.

FIG. 63illustrates an exemplary light to current converter device630having a P-N junction similar to that shown inFIG. 7and that may be made using exemplary processes80,340, and380. Device630may be similar to device620, except that front electrodes5and via front collector10may be made of the same material while via hole electrode9and via rear collector8may be made from a different material. Additionally, in some examples, impurity layer6may include a layer of an N+(for N-type substrate1) and SiO2.

FIG. 64illustrates an exemplary light to current converter device640having a P-N junction similar to that shown inFIG. 7and that may be made using exemplary processes80,340, and380. Device640may be similar to device620except that via front collector10, via hole electrode9, and via rear collector8may be hollow. Additionally, front electrodes5, via front collector10, via hole electrode9, and via rear collector8may be made from the same material and may form a unitary body.

FIG. 65illustrates another exemplary light to current converter device650having a P-N junction similar to that shown inFIG. 7and that may be made using exemplary processes80,340, and380. Device650may be similar to device620except that via front collector10and via hole electrode9may be hollow while via rear collector8may be fully filled. Additionally, front electrodes5, via front collector10, and via hole electrode9may be made from the same material while via rear collector8may be made from a different material.

FIG. 66illustrates another exemplary light to current converter device660having a P-N junction similar to that shown inFIG. 7and that may be made using exemplary processes80,340, and380. Device660may be similar to device620except that via front collector10and via rear collector8may be fully filled while via hole electrode9may be hollow. Additionally, front electrodes5may be made from a first material, via front collector10and via rear collector8may be made from a second material, and via hole electrode9may be made from a third material.

FIG. 67illustrates another exemplary light to current converter device670having a P-N junction similar to that shown inFIG. 7and that may be made using exemplary processes80,340, and380. Device670may be similar to device640except that front electrodes5, via front collector10, and a portion of via hole electrode9may be made from the same material, while the remaining portion of via hole electrode9and via rear collector8may be made from a different material.

FIG. 68illustrates another exemplary light to current converter device680having a P-N junction similar to that shown inFIG. 6. Device680may be similar to device550, except that the emitter2asymmetrically covers only a portion of the inner surface of the via hole3.

It should be appreciated by one or ordinary skill that any one of the P-N junctions shown in FIGS.1and4-7may be used to make light to current converter devices having any combination of materials for front electrodes5, rear electrodes7, via hole electrode9, via front collector10, and via rear collector8, and having a hole through all, a portion, or none of via hole electrode9, via front collector10, and via rear collector8.

In some examples, the light to current converter devices described above may have an average cell efficiency (photo to current efficiency) of about 18.7% and a cell power of about 4.47 W when using a monocrystalline silicon substrate. Conventional light to current converter devices having a monocrystalline silicon substrate may typically have a cell efficiency of about 17.8% and produce a cell power of about 4.25 W.

In other examples, the light to current converter devices described above may have an average cell efficiency of about 17.3% and a cell power of about 4.21 W when using a polycrystalline silicon substrate. Conventional light to current converter devices having a polycrystalline silicon substrate may typically have a cell efficiency of about 16.5% and produce a cell power of about 4.01 W.

Although embodiments have been fully described with reference to the accompanying drawings, it is to be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications are to be understood as being included within the scope of the various embodiments as defined by the appended claims.