Non-destructive determination of the moisture content in an electronic circuit board using comparison of capacitance measurements acquired from test coupons, and design structure/process therefor

Two test coupons are utilized in an apparatus, method and design process/structure for determining the moisture content in an electronic circuit board (e.g., a printed circuit board (PCB) or panel). The first coupon has a laminate stack-up with voltage planes separated from each other by dielectric material. These voltage planes include etched clearances with neither plated through holes (PTHs) nor drilled holes extending therethrough. The second coupon is substantially identical to the first coupon except that each of the voltage planes of the first coupon includes PTHs extending through etched clearances corresponding to the etched clearances of the first coupon. In one embodiment, an alarm indicating unacceptably high moisture content is generated if a delta capacitance calculated as a difference between capacitance measurements acquired from the respective coupons is greater than a threshold. Preferably, the alarm notifies a user that at least one aqueous process related to PTH formation is implicated.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates in general to the field of testing electronic circuit boards. More particularly, the present invention relates to a method of determining the moisture content in an electronic circuit board (e.g., a printed circuit board, a panel that includes one or more printed circuit boards, or a special printed circuit board test panel) using two test coupons and a comparison of capacitance measurements acquired from the two coupons, and an apparatus, design process and design structure therefor.

2. Background Art

The structure of the laminate within module sites of printed circuit boards (PCBs) may be damaged when the PCBs are subjected to soldering operations. The likelihood that this damage will occur increases with increasing soldering temperatures and, as a result, reliability risks for the PCBs increase as well. Plated through holes (PTHs) in the PCB, especially PTHs within module sites, are particularly vulnerable to this failure mechanism. Higher soldering temperatures are a consequence of compliance with the Restriction of Hazardous Substances Directive or RoHS. Under RoHS, eutectic tin/lead solder is replaced by lead-free solders (e.g., Sn—Ag—Cu solder) with higher melting temperatures.

A key factor in this failure mechanism is the rapid volatilization (during soldering) of water that is entrapped within the laminate during fabrication of the PCB. Specifically, water may be entrapped during aqueous processes that occur after the PCB is drilled and up to the early phases of plating of the drilled holes (to form PTHs). For a given PCB design and laminate material, the amount of water that is entrapped will vary (up to a point) with the details of some aspects of the fabrication process. Similarly, the effects of entrapped water upon the structural integrity of the laminate within a given PCB will vary with the PCB design, the laminate material, and some aspects of the fabrication process. It is important that a PCB fabricator take steps to minimize the amount of entrapped water within a given PCB. Unfortunately, direct measurements of water content (especially within module sites) are not practical.

Typically, direct measurement of the water content in a PCB, especially within module sites, is performed through a destructive testing technique. For example, the water content in a PCB may be determined by Karl Fischer (KF) titration, which requires the sample to be ground to a fine powder and then subjected to coulometric analysis.

It is also known to indirectly measure the water content in a PCB through capacitance. This concept is based upon the fact that the capacitance of a given laminate increases with increasing water content. Such a scheme is disclosed in U.S. Pat. No. 7,571,637 B2, issued Aug. 11, 2009 to Chen et al., entitled “DESIGN STRUCTURE FOR AN ON-CHIP REAL-TIME MOISTURE SENSOR FOR AND METHOD OF DETECTING MOISTURE INGRESS IN AN INTEGRATED CIRCUIT CHIP”, assigned to the same assignee as the present application. In the Chen et al. patent, an integrated circuit (IC) chip includes one or more moisture-sensing units and a moisture monitor. The moisture monitor can be configured to provide a real-time moisture detected-signal for signaling that moisture ingress into the integrated circuit chip has occurred by comparing the sense signals of the moisture-sensing units (e.g., the voltage on a voltage node Vc across a metal-insulator-metal (MIM) capacitor) to a threshold voltage. While the design structure disclosed in the Chen et al. patent may be effective for monitoring ingress of moisture into an integrated chip during the operational lifetime of the chip, the design structure does not address monitoring the ingress of moisture during fabrication of the integrated chip.

Another scheme for indirectly measuring moisture content in a PCB using capacitance is disclosed in an article by O'Toole et al., entitled “Pb-Free Reflow, PCB Degradation and Moisture Absorption”, published by DfR Solutions, College Park, Md., dated Jul. 16, 2009. In the O'Toole et al. article, two coupon designs were utilized to investigate the effect of Pb-free solder reflow on the degradation of PCBs. Each coupon contained three sections (i.e., Sections 1, 2 and 3) and a total of six test structures (i.e., Test Structures A, B, C, D, E and F) were incorporated into the design. The three sections of the PCB all consisted of the basic shield-over-shield copper plane design; however, they differed in their content of PTHs and non-functional pads. Section 1 of each coupon, which included Test Structure A, contained only copper planes without PTHs. Section 1 resulted in the largest shield-over-shield capacitance measurements and facilitated observation of clear trends for this data. Section 2 of each coupon, which included Test Structures B and C, contained copper planes, PTHs and nonfunctional pads on every layer. Section 2 allowed capacitance measurements to be made for both shield-over-shield and PTH-shield trends on the same coupon. Section 3 of each coupon, which included Test Structures D, E and F, contained copper planes, PTHs and nonfunctional pads on every other layer. In reflow simulation, Test Structures B and C showed much greater change in shield-over-shield capacitance measurements compared to Test Structure A.

The scheme disclosed in the O'Toole article has a number of disadvantages. Unfortunately, because Test Structure A contained only copper planes without PTHs, the clearances etched in the copper planes (sometimes referred to as a “swiss-cheese” pattern or “anti-pads”) for the PTHs were omitted along with the PTHs. The omission of the etched clearances from Test Structure A diminishes the usefulness of the comparison of the shield-over-shield capacitance measurements between Test Structure A and Test Structures B and C. In essence, this is an “apples and oranges” comparison because the area of copper planes without the etched clearances is larger than the area of the copper planes with the etched clearances—this is why the Section 1 resulted in the largest shield-over-shield capacitance measurements. Moreover, for each test structure disclosed in the O'Toole article, alternating planes of the PCB stack-up (i.e., the PCB stack-up consists of 26 layers of copper foil with dielectric between each layer) are tied to two different nodes (i.e., nodes A1 and A2 for Test Structure A, nodes B1 and B2 for Test Structure B, nodes C1 and C2 for Test Structure C). This arrangement does not facilitate capacitance measurements between individual planes of the PCB stack-up and, hence, it is not possible to measure water content in a particular area of the PCB stack-up. Finally, the scheme disclosed in the O'Toole article requires coupons taken from production panels to be exposed to reflow simulation—a costly and time-consuming step.

Therefore, a need exists for an enhanced mechanism for the non-destructive determination of the moisture content in an electronic circuit board (e.g., a PCB, a panel that includes one or more PCBs, or a special PCB test panel) using test coupons during fabrication.

SUMMARY OF THE INVENTION

According to the preferred embodiments of the present invention, an apparatus, method, design process, and design structure for determining the moisture content in an electronic circuit board (e.g., a printed circuit board (PCB), a panel that includes one or more PCBs, or a special PCB test panel) employ one or more coupon sets, each set having two test coupons. The first coupon has a laminate stack-up with voltage planes separated from each other by dielectric material. These voltage planes include etched clearances with neither plated through holes (PTHs) nor drilled holes extending therethrough. The second coupon is substantially identical to the first coupon except that each of the voltage planes of the second coupon includes PTHs extending through etched clearances corresponding to the etched clearances of the first coupon.

One or more coupon sets in accordance with the preferred embodiments of the present invention, provides a quick, non-destructive, semi-quantitative means of accessing the effects of process changes or process variability upon water content in the laminate of a production part (e.g., a PCB or a panel). The present invention, which takes advantage of the fact that the capacitance of a given laminate increases with increasing water content, may be used as a moisture management tool. Moisture management is desirable to reduce the propensity for laminate damage that may occur as the result of exposure of a PCB to higher soldering temperatures.

In one embodiment, an alarm indicating unacceptably high moisture content is generated if a delta capacitance calculated as a difference between capacitance measurements acquired from the respective coupons is greater than a threshold. Preferably, the alarm notifies a user that at least one aqueous process related to PTH formation is implicated. An alarm indicating unacceptably high moisture content is also generated if a capacitance measurement acquired from the first coupon without PTHs is greater than a threshold. Preferably, this alarm notifies the user that a raw laminate used to fabricate the first coupon without PTHs had unacceptably high moisture content “as delivered” and/or a clearance etch process used to produce the etched clearances in the raw laminate is/are implicated in the unacceptably high moisture content.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to the preferred embodiments of the present invention, an apparatus, method, design process, and design structure for determining the moisture content in an electronic circuit board (e.g., a printed circuit board (PCB), a panel that includes one or more PCBs, or a special PCB test panel) employ one or more coupon sets, each set having two test coupons. The first coupon has a laminate stack-up with voltage planes separated from each other by dielectric material. These voltage planes include etched clearances with neither plated through holes (PTHs) nor drilled holes extending therethrough. The second coupon is substantially identical to the first coupon except that each of the voltage planes of the second coupon includes PTHs extending through etched clearances corresponding to the etched clearances of the first coupon.

One or more coupon sets in accordance with the preferred embodiments of the present invention, provides a quick, non-destructive, semi-quantitative means of accessing the effects of process changes or process variability upon water content in the laminate of a production part (e.g., a PCB or a panel). The present invention, which takes advantage of the fact that the capacitance of a given laminate increases with increasing water content, may be used as a moisture management tool. Moisture management is desirable to reduce the propensity for laminate damage that may occur as the result of exposure of a PCB to higher soldering temperatures.

In one embodiment, an alarm indicating unacceptably high moisture content is generated if a delta capacitance calculated as a difference between capacitance measurements acquired from the respective coupons is greater than a threshold. Preferably, the alarm notifies a user that at least one aqueous process related to PTH formation is implicated. An alarm indicating unacceptably high moisture content is also generated if a capacitance measurement acquired from the first coupon without PTHs is greater than a threshold. Preferably, this alarm notifies the user that a raw laminate used to fabricate the first coupon without PTHs had unacceptably high moisture content “as delivered” and/or a clearance etch process used to produce the etched clearances in the raw laminate is/are implicated in the unacceptably high moisture content.

2. Detailed Description

In accordance with the preferred embodiments of the present invention, a set of at least two test coupons, i.e., at least one test coupon with plated through holes (PTHs) and at least one test coupon without PTHs, is incorporated into an electronic circuit board. Suitable electronic circuit boards into which the set of test coupons may be incorporated include, but are not limited to, a printed circuit board (an exemplary embodiment is described below with reference toFIG. 1), a panel that also incorporates one or more printed circuit boards (an exemplary embodiment is described below with reference toFIG. 2), or a special printed circuit board test panel (an exemplary embodiment is described below with reference toFIG. 3). One skilled in the art will appreciate, however, that the set of test coupons may be incorporated into other electronic circuit boards such as flex circuits, backplanes, backpanels, organic chip carriers, and the like.

For each capacitance measurement region within the laminate stack-up of the coupons, capacitances are measured and compared between the test coupon without PTHs and the test coupon with PTHs. Typically, the measured capacitance of the test coupon with PTHs will be higher than that of the test coupon without PTHs. This capacitance difference can be attributed to water that is entrapped within the laminate between the PTHs during aqueous processes that occur between when the laminate is drilled and partially into the PTH plating process. Changes in the capacitance difference can be attributed to changes in the amount of water entrapped in the laminate between PTHs.

The test coupon without PTHs and the test coupon with PTHs are, in essence, akin to a control sample and an experimental sample, respectively, in a controlled experiment. In a controlled experiment, the effect of an independent variable is tested by comparing the results obtained from an experimental sample against a control sample, which is nearly identical to the experimental sample except for the independent variable. In accordance with the preferred embodiments of the present invention, the test coupons with and without PTHs are substantially identical to each other except for the independent variable, which is the presence of the PTHs (along with various structural features associated with the PTHs, such as drilled holes, as well as various processes used to form the PTHs).

Typically, it is desirable in a controlled experiment for the control sample to be as near as possible to being identical to the experimental sample. As a consequence, in accordance with the preferred embodiments of the present invention, the test coupon without PTHs has etched clearances (described below with reference toFIG. 6) in voltage planes used for capacitance measurement just like the corresponding etched clearances (described below with reference toFIG. 7) in corresponding voltage planes in the test coupon with PTHs. Otherwise, the capacitance measurements obtained from the test coupon without PTHs would be skewed relative to the capacitance measurements obtained from the test coupon with PTHs (i.e., the capacitance measured between the voltage planes would be greater if the etched clearances were omitted from the test coupon without PTHs because the capacitance increases with plane area). Similarly, for the test coupon with PTHs, it is critical that the web within the array on the voltage planes be manufactured as defined, at least with normal manufacturing tolerances (e.g., there shall be no breaks in “swiss cheese” between the vias on the voltage planes, which is a solution manufacturers have been known to employ against etched clearance/drilled hole registration problems).

In the test coupon without PTHs and the test coupon with PTHs, the voltage planes used for capacitance measurements are separated from each other by a dielectric material. Layers in addition to the dielectric material may separate the voltage planes. Also, each of the test coupons typically includes more than a single pair of voltage planes from which capacitance measurements may be acquired. The voltage planes used for capacitance measurements are identically located in the laminate stack-up (an exemplary stack-up is described below with reference toFIG. 5) of the test coupons. Typically, the laminate stack-up of the test coupons substantially replicates the laminate stack-up of the electronic circuit board. In addition, as discussed in more detail below, the test coupons replicate selected design features of the electronic circuit board, i.e., at least one design feature of the electronic circuit board that is known or predicted to be associated with solder reflow-induced damage to the laminate of the electronic circuit board. Such design features include, but are not limited to, via-to-via pitch, drilled via diameter, drilled via clearance diameter, array size, and the like.

FIG. 1is a block diagram illustrating a printed circuit board (PCB)100that incorporates a set105of two coupons, i.e., one coupon110without plated through holes (PTHs) and one coupon115with PTHs in accordance with an embodiment of the present invention. The coupon110without PTHs and the coupon115with PTHs are substantially identical but for the absence and presence, respectively, of PTHs and drilled holes through the laminate stack-up (an exemplary layout and an exemplary stack-up of these coupons are described below with reference toFIG. 4andFIG. 5, respectively).

Typically, the coupons105and110replicate the laminate stack-up and selected design features of the PCB100. The coupons105and110preferably include one or more design features that reflect at least one feature of the PCB100that is known or predicted to be associated with solder reflow-induced damage to the laminate of the PCB110within or near the at least one PCB feature. Such design features include, without limitation, via-to-via pitch, drilled via diameter, drilled via clearance diameter, array size, and the like. Typically, the aforementioned PCB feature(s) is/are within or near one or more module sites on the PCB110(e.g., a module site120).

The coupons105and110are preferably removable from the PCB100. For example, the PCB100may be scored to facilitate removal of the coupons105and110from the PCB100. However, scoring is but one technique known in the art to facilitate removal of test coupons from a PCB. One skilled in the art will appreciate that any other technique known in the art may be used to facilitate removal of the coupons105and110from the PCB100.

The moisture content of the PCB100may be determined using the apparatus illustrated inFIG. 1. Preferably, as discussed below with reference to the method illustrated inFIG. 8, the coupons105and110are removed from the PCB100and the moisture content of the PCB100determined before the PCB100is subjected to reflow conditions.

Preferably, as illustrated inFIG. 1, the coupons105and110are located adjacent to each other. By locating the coupons110and115adjacent to one another, each coupon is exposed to substantially the same conditions during fabrication of the PCB100. Typically, it is desirable in a controlled experiment to expose a control sample to the same conditions as an experimental sample. Accordingly, but for the presence of the PTHs (along with various structural features associated with the PTHs, such as drilled holes, as well as various processes used to form the PTHs), the coupons110and115would likely have the same moisture content as each other.

One skilled in the art will appreciate, however, that the coupons110and115may be located anywhere with respect to one another on the PCB100.

Typically, it is desirable to locate the coupons110and115near a module site120on the PCB100that is known or predicted to be associated with solder reflow-induced damage to the laminate of the PCB100. By locating the coupons110and115near the module site120, the coupons and the module site are exposed to substantially the same conditions during fabrication of the PCB100. Accordingly, at least the coupon115with PTHs will likely have the same moisture content as the module site120. The coupon110without PTHs, on the other hand, may have lower moisture content than either the coupon115with PTHs or the module site120, owing to the omission of PTHs in the coupon110.

By locating the coupons110and115near the module site120as illustrated inFIG. 1, it is possible in accordance with the preferred embodiments of the present invention to indirectly quantify the effects of changes in fabrication processes upon water content within the module site120(e.g., optimize fabrication processes based on water content) or variations in the water content in the module site120due to process variations for a given design of the PCB100, using a given laminate material (e.g., monitor the water content in production PCBs for variations due to process variations).

One skilled in the art will appreciate, however, that the coupons110and115may be located anywhere in the PCB100and need not be located near the module site120.

Moreover, it may be desirable to provide the PCB100with more than a single coupon set105. For example, it may be desirable to provide a plurality of coupon sets105at different locations on the PCB100so that each coupon set105may experience different conditions during fabrication of the PCB100. Likewise, it may be desirable to locate a plurality of coupon sets105, respectively, near a plurality of module sites on the PCB100that are known or predicted to be associated with solder reflow-induced damage to the laminate of the PCB100.

FIG. 2is a block diagram illustrating a panel200incorporating one or more printed circuit boards (PCBs)205and set215of two coupons, i.e., one coupon220without plated through holes (PTHs) and one coupon225with PTHs in accordance with another embodiment of the present invention. The coupon220without PTHs and the coupon225with PTHs are substantially identical but for the absence and presence, respectively, of PTHs and drilled holes through the laminate stack-up (an exemplary layout and an exemplary stack-up of these coupons are described below with reference toFIG. 4andFIG. 5, respectively).

Typically, as illustrated inFIG. 2, the PCBs205and the coupon set215are accommodated in separate areas of the panel200. The PCBs205and the coupons220and225are preferably removable from the panel200. For example, the panel200may be scored to facilitate removal of the PCBs205and the coupons220and225from the panel200. However, scoring is but one technique known in the art to facilitate removal of PCBs and test coupons from a panel. One skilled in the art will appreciate that any other technique known in the art may be used to facilitate removal of the PCBs205and the coupons220and225from the panel200.

The moisture content of a plurality of PCBs205that are simultaneously fabricated in separate areas of the panel200may be determined using the apparatus illustrated inFIG. 2(i.e., the panel200). Preferably, as discussed below with reference to the method illustrated inFIG. 8, the coupons220and225are removed from the panel200and the moisture content of the panel200determined before the panel200is subjected to reflow conditions.

Typically, the coupons220and225replicate the laminate stack-up and selected design features of the PCBs205. The coupons220and225preferably include one or more design features that reflect at least one feature of the PCBs205that is known or predicted to be associated with solder reflow-induced damage to the laminate of the PCBs205within or near the at least one PCB feature. Such design features include, without limitation, via-to-via pitch, drilled via diameter, drilled via clearance diameter, array size, and the like. Typically, the aforementioned PCB feature(s) is/are within or near one or more module sites on the PCBs205(e.g., the module site120inFIG. 1).

Preferably, as illustrated inFIG. 2, the coupons220and225are located adjacent to each other. By locating the coupons220and225adjacent to one another, each coupon is exposed to substantially the same conditions during fabrication of the panel200. Typically, it is desirable in a controlled experiment to expose a control sample to the same conditions as an experimental sample. Accordingly, but for the presence of the PTHs (along with various structural features associated with the PTHs, such as drilled holes, as well as various processes used to form the PTHs), the coupons220and225would likely have the same moisture content as each other.

One skilled in the art will appreciate, however, that the coupons220and225may be located anywhere with respect to one another on the panel200.

Moreover, it may be desirable to provide the panel200with more than a single coupon set215. For example, it may be desirable to provide a plurality of coupon sets215at different locations on the panel200so that each coupon set215may experience different conditions during fabrication of the panel200. Likewise, it may be desirable to locate a coupon set215near each of the PCBs205and/or near a module site on the PCBs205known or predicted to be associated with solder reflow-induced damage to the laminate of the PCBs205.

By locating a coupon set215near each of the PCBs205and/or near a module site on the PCBs205, it is possible in accordance with the preferred embodiments of the present invention to indirectly quantify the effects of changes in fabrication processes upon water content within the PCB and/or module site (e.g., optimize fabrication processes based on water content) or variations in the water content in the PCB and/or module site due to process variations for a given PCB design, using a given laminate material (e.g., monitor the water content in production PCBs for variations due to process variations).

FIG. 3is a block diagram illustrating a special printed circuit board (PCB) test panel300incorporating a set305of two coupons, i.e., one coupon310without plated through holes (PTHs) and one coupon315with PTHs in accordance with yet another embodiment of the present invention. The coupon310without PTHs and the coupon315with PTHs are substantially identical but for the absence and presence, respectively, of PTHs and drilled holes through the laminate stack-up (an exemplary layout and an exemplary stack-up of these coupons are described below with reference toFIG. 4andFIG. 5, respectively).

Typically, the special PCB test panel300accommodates a plurality of coupon sets305(only one set is shown inFIG. 3). For example, the respective coupon sets305at different locations on the special PCB test panel300may include coupons built with varying moisture content to obtain pass/fail criteria data (e.g., discussed below with reference toFIG. 9). Likewise, it may be desirable to provide a plurality of coupon sets305at different locations on the special PCB test panel300so that each coupon set305may experience different conditions during fabrication of the special PCB test panel300.

The coupons310and315in each coupon set305are preferably removable from the special PCB test panel300. For example, the special PCB test panel300may be scored to facilitate removal of the coupons310and315from the special PCB test panel300. However, scoring is but one technique known in the art to facilitate removal of test coupons from a panel. One skilled in the art will appreciate that any other technique known in the art may be used to facilitate removal of the coupons310and315from the special PCB test panel300.

Typically, the coupons310and315replicate the laminate stack-up and selected design features of a production PCB (not shown inFIG. 3). The coupons310and315preferably include one or more design features that reflect at least one feature of the production PCB that is known or predicted to be associated with solder reflow-induced damage to the laminate of the production PCB within or near the at least one production PCB feature. Such design features include, without limitation, via-to-via pitch, drilled via diameter, drilled via clearance diameter, array size, and the like. Typically, the aforementioned production PCB feature(s) is/are within or near one or more module sites on the production PCBs (e.g., the module site120inFIG. 1).

Preferably, as illustrated inFIG. 2, the coupons310and315are located adjacent to each other. By locating the coupons310and315adjacent to one another, each coupon is exposed to substantially the same conditions during fabrication of the special PCB test panel300. Typically, it is desirable in a controlled experiment to expose a control sample to the same conditions as an experimental sample. Accordingly, but for the presence of the PTHs (along with various structural features associated with the PTHs, such as drilled holes, as well as various processes used to form the PTHs), the coupons310and315would likely have the same moisture content as each other.

One skilled in the art will appreciate, however, that the coupons310and315may be located anywhere with respect to one another on the special PCB test panel300.

FIG. 4is an enlarged top surface view illustrating an exemplary layout400of the two coupons shown inFIG. 1-3. As illustrated inFIG. 4, a set of coupons includes a coupon405without PTHs (corresponding to coupons110,220and310inFIGS. 1-3, respectively) and a coupon410with PTHs (corresponding to coupons115,225and315inFIGS. 1-3, respectively). The coupons405and410are identical in size and, as discussed below, include an equal number of clearances. The particular layout of the coupons405and410illustrated inFIG. 4is merely one example of a suitable coupon layout and is not intended to limit the present invention. One skilled in the art will appreciate that any suitable coupon layout may be used in accordance with the preferred embodiments of the present invention in lieu of the exemplary coupon layout400illustrated inFIG. 4.

As illustrated inFIG. 4, the coupons405and410each include a 20×20 array. One skilled in the art will appreciate, however, that the coupons405and410may include any size array. The coupon410with PTHs includes a 20×20 array420of vias (e.g., 8-mil vias) and clearances422(e.g., 26-mil clearances) on a predetermined pitch grid (e.g., 0.8-mm pitch grid). These vias and clearances422are better illustrated inFIG. 7, which shows them in the context of a voltage plane layer. The coupon405without PTHs, includes a 20×20 array425of clearances427(e.g., 26-mil clearances) on the predetermined pitch grid (e.g., 0.8-mm pitch grid). These clearances427are better illustrated inFIG. 6, which shows them in the context of a voltage plane layer. The clearances427have the same diameter and are on the same predetermined pitch grid as the clearances422. The array425of the coupon405without PTHs is identical to the array420of the coupon410with PTHs except for omission of the vias (and the drilled holes for the vias) present in the array420of the coupon410with PTHs.

As also illustrated inFIG. 4, the coupons405and410each include8PTHs430(e.g., 40-mil PTH diameter) for measuring capacitance. The PTHs430for measuring capacitance are labeled “C−4”, “C−3”, “C−2”, “C−1”, “C+1”, “C+2”, “C+3”, and “C+4” inFIG. 4, as denoted by markings immediately adjacent to the corresponding PTHs430on the top surface of the coupons. The PTHs430for measuring capacitance are located above the 20×20 array, with a PTH-to-PTH spacing of 100 mils to accommodate probes for capacitance measurement. One skilled in the art will appreciate that the coupons405and410may include any number of such PTHs for measuring capacitance. Each marking is a code (e.g., “C+1”) that refers to the specific layer to which the immediately adjacent PTH430for measuring capacitance is uniquely connected. Typically, a translation table is used to translate the code to the actual layer number of the specific layer used. Alternatively, each marking may refer directly to the actual layer number of the specific layer to which the immediately adjacent PTH430is connected.

The PTHs430for measuring capacitance are connected to selected internal layers within the coupons405and410to allow dielectric capacitance measurements (up to 7 dielectric layers). An exemplary laminate stack-up of the coupons405and410is described below with reference toFIG. 5, including the selected internal layers to which the PTHs430for measuring capacitance are connected.

The exemplary layout400of the coupons405and410illustrated inFIG. 4is based on the IBM Part Number 44V5528 (WIC20B) printed circuit board test vehicle design package, available from International Business Machines Corporation, Armonk, N.Y., that was developed primarily to allow indirect assessments of bulk and localized water content within the laminate within a 20×20 array of 8-mil vias on a 0.8-mm pitch grid. The WIC20B design also allows assessments of the effects of environmental stresses upon the structure and/or chemistry of the laminate used in its construction.

Although the WIC20B design package is conventional, its use in a set of coupons that includes one coupon without PTHs and one coupon with PTHs for comparison of capacitance measurements is new. A brief description of the WIC20B design package is presented below in order to provide a foundation from which to describe concepts of the present invention. Greater detail about the WIC20B design package is set forth in the document, W. Rothschild, “Description of IBM PN 44V5528 (WIC20B)”, International Business Machines Corporation, Armonk, N.Y., pages 1-13, Apr. 10, 2009, which is hereby incorporated herein by reference in its entirety.

The WIC20B design package includes several features that are not pertinent to the present invention. Such features include PTHs for measuring inductance, traces used in inductance measurement, and a material characterization coupon for material characterization and other studies. These non-pertinent features of the WIC20B design package are not further described herein.

There is no established lay-up or overall thickness for the WIC20B design. Rather, the WIC20B design package consists of 2 external signal planes, 18 internal signal planes, and 26 voltage planes, as well as 3 solder mask layers (including none) for each external surface. A wide variety of different lay-ups (and, thus, a wide range of overall thicknesses) may be constructed by selecting layers from the WIC20B design package in accordance with a set of guidelines that are presented in the WIC20B design document. The WIC20B design package also allows for selection among different diameters of the clearance around the 8-mil vias. This WIC20B design defines the pitch (0.8-mm) and allows a range of drill sizes and clearances around those drilled holes on the voltage planes. The WIC20B design also includes the option of inclusion of unused lands on any signal plane, as well as choices of clearance diameters for each solder mask layer.

WIC is an acronym that describes the measurements that the WIC20B design package was designed to accommodate—W(eight), I(mpedance) and C(apacitance). The small size of the test coupon facilitates high precision gravimetric (weight) analyses. Most internal layers are wired to allow dielectric capacitance measurements (up to 7 dielectric layers) when following the guidelines that are provided in the WIC20B design document. Changes in these parameters may occur upon exposure of the test coupon to environmental stresses, such as solder reflow simulation or storage at ambient condition or at high temperature and/or high relative humidity. These changes may be indicative of changes in the composition of the laminate within the area array. Changes include migration of water, creation of air pockets (e.g., due to the creation of laminate cracks), and changes in resin chemistry (e.g., due to oxidation). Note that some of these changes might be detected electrically but not gravimetrically.

In the WIC20B design, a voltage divider on each voltage plane layer separates the 20×20 array and the PTHs used to measure capacitance from the remainder of the voltage plane. In accordance with the preferred embodiments of the present invention, a voltage divider (not shown inFIG. 4) on each voltage plane is provided between the coupons405and410.

Also in the WIC20B design, pairs of voltage planes that are to be connected to PTHs for capacitance measurements are placed as close as possible to the dielectric layers that are being tested for anticipated changes of interest. Typically, this will include layers near the middle of the lay-up. Two voltage planes that are connected to the capacitance measuring PTHs typically flank each of the dielectric layers that are being focused on. The layers that are typically most sensitive to reflow-induced damage (mainly cracking in module areas) are those layers that are closer to the center of the stack-up. The ability of the present invention to focus on these “center of the stack-up layers” is a significant advantage over test structures that do not facilitate capacitance measurements between individual planes of the PCB stack-up (such as the test structure disclosed in the O'Toole article, discussed above in the “Background Art” Section).

FIG. 5is a cross-sectional view illustrating an exemplary laminate stack-up500of the exemplary coupon layout400shown inFIG. 4. The exemplary laminate stack-up500illustrated inFIG. 5is used for each of the coupons405and410shown inFIG. 4.

The particular laminate stack-up illustrated inFIG. 5is merely one example of a suitable coupon laminate stack-up and is not intended to limit the present invention. One skilled in the art will appreciate that any suitable laminate stack-up may be used in accordance with the preferred embodiments of the present invention in lieu of the exemplary laminate stack-up500illustrated inFIG. 5.

As illustrated inFIG. 5, the exemplary laminate stack-up500includes twenty electrically conductive planes (i.e., eight voltage planes505and twelve signal planes510) each separated by one or more layers515of dielectric material. The electrically conductive planes typically comprise copper, but may be any suitable electrically conductive material. The voltage planes505are typically power planes or ground planes. Typically, the one or more layers515of dielectric material comprise one or more sheets of prepreg or laminate, but may be any suitable electrically nonconductive material.

FIG. 5further denotes which of the voltage planes505are connected to which of the PTHs430. For the sake of clarity, the actual connections are not shown inFIG. 5. These connections, which are conventional, are identical for each of the coupons405and410shown inFIG. 4.

The voltage plane505denoted as “P3” inFIG. 5is further denoted therein as “C+4, REF (I+4)” to indicate that this voltage plane layer is connected to the PTH430denoted with the marking “C+4” inFIG. 4.

The voltage plane505denoted as “P5” inFIG. 5is further denoted therein as “C+3, REF (I+3)” to indicate that this voltage plane layer is connected to the PTH430denoted with the marking “C+3” inFIG. 4.

The voltage plane505denoted as “P7” inFIG. 5is further denoted therein as “C+2, REF (I+2)” to indicate that this voltage plane layer is connected to the PTH430denoted with the marking “C+2” inFIG. 4.

The voltage plane505denoted as “P9” inFIG. 5is further denoted therein as “C+1, REF (I+1)” to indicate that this voltage plane layer is connected to the PTH430denoted with the marking “C+1” inFIG. 4.

The voltage plane505denoted as “P12” inFIG. 5is further denoted therein as “C−1, REF (I−1)” to indicate that this voltage plane layer is connected to the PTH430denoted with the marking “C−1” inFIG. 4.

The voltage plane505denoted as “P14” inFIG. 5is further denoted therein as “C−2, REF (I−2)” to indicate that this voltage plane layer is connected to the PTH430denoted with the marking “C−2” inFIG. 4.

The voltage plane505denoted as “P16” inFIG. 5is further denoted therein as “C−3, REF (I−3)” to indicate that this voltage plane layer is connected to the PTH430denoted with the marking “C−3” inFIG. 4.

The voltage plane505denoted as “P18” inFIG. 5is further denoted therein as “C−4, REF (I−4)” to indicate that this voltage plane layer is connected to the PTH430denoted with the marking “C−4” inFIG. 4.

Seven dielectric capacitance measurements (i.e., in different regions of the laminate stack-up) may be acquired for each of the coupons405and410(shown inFIG. 4) by placing two probes on the PTHs430(shown inFIG. 4) that are adjacent to each other. A first capacitance measurement (i.e., the dielectric material between the voltage planes505denoted as “P9” and “P12” inFIG. 5) can be acquired by placing one probe on the PTH430denoted with the marking “C+1” inFIG. 4and the other probe on the PTH430denoted with the marking “C−1” inFIG. 4. In this case, three layers515of dielectric material (as well as the signal planes510denoted as “S10” and “S11” inFIG. 5) lie in the capacitance measurement region between the voltage planes505denoted as “P9” and “P12” inFIG. 5.

A second capacitance measurement (i.e., the dielectric material between the voltage planes505denoted as “P3” and “P5” inFIG. 5) can be acquired by placing the probes on the PTHs430denoted with markings “C+4” and “C+3” inFIG. 4. In this case, two of the layers515of dielectric material (as well as the signal plane510denoted as “S4” inFIG. 5) lie in the capacitance measurement region between the voltage planes505denoted as “P3” and “P5” inFIG. 5.

A third capacitance measurement (i.e., the dielectric material between the voltage planes505denoted as “P5” and “P7” inFIG. 5) can be acquired by placing the probes on the PTHs430denoted with markings “C+3” and “C+2” inFIG. 4. In this case, two of the layers515of dielectric material (as well as the signal plane510denoted as “S6” inFIG. 5) lie in the capacitance measurement region between the voltage planes505denoted as “P5” and “P7” inFIG. 5.

A fourth capacitance measurement (i.e., the dielectric material between the voltage planes505denoted as “P7” and “P9” inFIG. 5) can be acquired by placing the probes on the PTHs430denoted with markings “C+2” and “C+1” inFIG. 4. In this case, two of the layers515of dielectric material (as well as the signal plane510denoted as “S8” inFIG. 5) lie in the capacitance measurement region between the voltage planes505denoted as “P7” and “P9” inFIG. 5.

A fifth capacitance measurement (i.e., the dielectric material between the voltage planes505denoted as “P12” and “P14” inFIG. 5) can be acquired, by placing the probes on the PTHs430denoted with markings “C−1” and “C−2” inFIG. 4. In this case, two of the layers515of dielectric material (as well as the signal plane510denoted as “S13” inFIG. 5) lie in the capacitance measurement region between the voltage planes505denoted as “P12” and “P14” inFIG. 5.

A sixth capacitance measurement (i.e., the dielectric material between the voltage planes505denoted as “P14” and “P16” inFIG. 5) can be acquired by placing the probes on the PTHs430denoted with markings “C-2” and “C-3” inFIG. 4. In this case, two of the layers515of dielectric material (as well as the signal plane510denoted as “S15” inFIG. 5) lie in the capacitance measurement region between the voltage planes505denoted as “P14” and “P16” inFIG. 5.

A seventh capacitance measurement (i.e., the dielectric material between the voltage planes505denoted as “P16” and “P18” inFIG. 5) can be acquired, by placing the probes on the PTHs430denoted with markings “C−3” and “C−4” inFIG. 4. In this case, two of the layers515of dielectric material (as well as the signal plane510denoted as “S17” inFIG. 5) lie in the capacitance measurement region between the voltage planes505denoted as “P16” and “P18” inFIG. 5.

Generally, any number of the layers515of dielectric material and the signal planes510may lie within the capacitance measurement region. However, care should be exercised in the use of voltage planes that do not have connections to PTHs for capacitance measurement. For example, consider the case of a blank voltage plane that is between two voltage planes that are both connected to PTHs430for capacitance measurements. Any such capacitance measurements made between these two voltage planes may be more difficult to interpret due to the presence of the blank voltage plane between the two voltage planes.

FIG. 6is a top view illustrating a portion of a voltage plane layer505shown inFIG. 5in the coupon405without plated through holes (PTHs) shown inFIG. 4. Clearances427are etched in the voltage plane505to expose the underlying dielectric layer515where the PTHs of the 20×20 array would otherwise be located. That is, each of the clearances427in the coupon405without PTHs is provided in the same locations as each of the corresponding clearances422in the coupon410with PTHs (described below with reference toFIG. 7). Also, no holes are drilled in the clearances427. Typically, a hole would be drilled in each such clearance to accommodate a PTH.

FIG. 7is a top view illustrating a portion of a voltage plane layer505shown inFIG. 5in the coupon410with plated through holes (PTHs) shown inFIG. 4. Clearances422are etched in the voltage plane505to expose the underlying dielectric layer515where the PTHs of the 20×20 array are to be located. A hole705is then typically drilled through each of the clearances422. Then a PTH710is formed in each of the holes705.

As made clear inFIGS. 6 and 7, the number of the clearances427etched in the voltage plane505of the coupon405without PTHs is identical to the number of the clearances422etched in the voltage plane505of the coupon410with PTHs. The clearances422and427are identical in number, location and configuration.

FIG. 8is a flow diagram illustrating a method800of determining moisture content in an electronic circuit board in accordance with the preferred embodiments of present invention. In the method800, the steps discussed below (steps805-840) are performed. These steps are set forth in their preferred order. It must be understood, however, that the various steps may occur simultaneously or at other times relative to one another. Moreover, those skilled in the art will appreciate that one or more steps may be omitted.

The method800begins with pass/fail criteria data being obtained (step805). The criteria data (which are described in more detail below with reference toFIGS. 9 and 10) include one or more capacitance threshold values for each capacitance measurement region of the laminate stack-up of both types of coupons (i.e., coupons without PTHs and coupons with PTHs). Preferably, at least one of these capacitance threshold values is based on a comparison of a capacitance measurement made in a capacitance measurement region of a coupon with PTHs versus a capacitance measurement made in the same capacitance measurement region of a coupon without PTHs.

In accordance with the preferred embodiments of the present invention, the criteria data obtained in step805may include: a “no-PTH capacitance threshold” for each capacitance measurement region of coupons without PTHs; and a “delta capacitance threshold” for each capacitance measurement region of coupons with PTHs relative to coupons without PTHs. These preferred capacitance threshold values and their establishment are discussed below with reference toFIGS. 9 and 10.

The criteria data may be obtained during step805either by accessing previously established criteria data (e.g., criteria data that was previously established and stored in a database) or by performing the method900(which is described below with reference toFIG. 9) and/or the method1000(which is described below with reference toFIG. 10).

The method800continues by acquiring a capacitance measurement from a coupon without PTHs (step810). This capacitance measurement is referred to as “CAP1” inFIG. 8. For example, a capacitance measurement may be acquired from a coupon without PTHs that has been removed from a PCB (e.g., the coupon110without PTHs that has been removed from the PCB100shown inFIG. 1) or a coupon without PTHs that has been removed from a panel (e.g., the coupon220without PTHs that has been removed from the panel200shown inFIG. 2). In accordance with the preferred embodiments of the present invention, the coupon without PTHs corresponds to the coupon405without PTHs shown inFIG. 4. Step810may be repeated for each capacitance measurement region of the coupon without PTHs.

In accordance with the preferred embodiments of the present invention, no reflow simulation has occurred with respect to the coupon without PTHs when the capacitance measurement(s) is/are acquired from the coupon in step810. Likewise, in accordance with the preferred embodiments of the present invention, no reflow simulation has occurred with respect to the coupon with PTHs when its capacitance measurement(s) is/are acquired from the coupon in step825(described below). Avoiding the necessity of reflow simulation is a significant advantage of the present invention. The coupons are merely removed from the production part, and subsequently subjected to capacitance measurement.

Next, the method800determines if the capacitance measurement from the coupon without PTHs acquired in step810is larger than the “no-PTH capacitance threshold” (step815). This threshold, which is referred to as “NO-PTH CAP THRESHOLD” inFIG. 8, is preferably one of the criteria data obtained in step805. Step815may be omitted if a “no-PTH capacitance threshold” has not been established.

If the method800determines that the capacitance measurement from the coupon without PTHs acquired in step810is larger than the “no-PTH capacitance threshold” (step815=Yes), then an alarm is generated indicating that unacceptably high moisture content has been detected (step820). Detection of unacceptably high moisture content in the coupon without PTHs infers that the PCB or panel from which the coupon was removed likely also has unacceptably high moisture content. Preferably, the alarm notifies a user that a raw laminate used to fabricate the coupon without PTHs (as well as to fabricate the PCB or panel from which the coupon was removed) had unacceptably high moisture content “as delivered” and/or a clearance etch process used to produce the etched clearances in the raw laminate is/are implicated in the unacceptably high moisture content. The alarm may also identify specific items related to the raw laminate (e.g., manufacturer, storage parameters, and the like.) and the clearance etch process (e.g., aqueous bath parameters, bake cycle parameters, and the like) that the user should check.

In the embodiment illustrated inFIG. 8, the method ends after the alarm/notification of step820. In an alternative embodiment, the method800continues after step820by returning to step815to determine if the capacitance measurement from any of other capacitance measurement regions of the coupon without PTHs is larger than the “no-PTH capacitance threshold”. In another alternative embodiment, the method800continues after step820by advancing to step825(described below).

If the method800determines that the capacitance measurement from the coupon without PTHs acquired in step810is not larger than the “no-PTH capacitance threshold” (step815=No), then the method800continues by acquiring a capacitance measurement from a coupon with PTHs (step825). This capacitance measurement is referred to as “CAP2” inFIG. 8. For example, a capacitance measurement may be acquired from a coupon with PTHs that has been removed from a PCB (e.g., the coupon115with PTHs that has been removed from the PCB100shown inFIG. 1) or a coupon with PTHs that has been removed from a panel (e.g., the coupon225with PTHs that has been removed from the panel200shown inFIG. 2). In accordance with the preferred embodiments of the present invention, the coupon with PTHs corresponds to the coupon410with PTHs shown inFIG. 4. Step825may be repeated for each capacitance measurement region of the coupon with PTHs.

The method800then calculates a delta capacitance by subtracting the capacitance measurement acquired from the coupon without PTHs from the capacitance measurement acquired from the coupon with PTHs (step830). The delta capacitance is referred to as “DELTA CAP” inFIG. 8. Step830may be repeated for each capacitance region of the coupons.

Next, the method800determines if the delta capacitance calculated in step830is larger than the “delta capacitance threshold” (step835). This threshold, which is referred to as “DELTA CAP THRESHOLD” inFIG. 8, is one of the criteria data obtained in step805.

If the method800determines that the delta capacitance calculated in step830is larger than the “delta capacitance threshold” (step835=Yes), then an alarm is generated indicating that unacceptably high moisture content has been detected (step840). Detection of unacceptably high moisture content infers that the PCB or panel from which the coupons were removed likely also has unacceptably high moisture content. Preferably, the alarm notifies a user that at least one aqueous process related to the PTH formation is implicated in the unacceptably high moisture content. The alarm may also identify specific items related to the implicated aqueous processes that the user should check, e.g., aqueous bath parameters, bake cycle parameters, and the like.

In the embodiment illustrated inFIG. 8, the method ends after the alarm/notification of step840. In an alternative embodiment, the method800continues after step840by returning to step835to determine if the delta capacitance calculated in step830for any of the other capacitance measurement regions is larger than the “delta capacitance threshold”.

If the method800determines that the delta capacitance calculated in step830is not larger than the “delta capacitance threshold” (step835=No), then the method800ends. In an alternative embodiment, the method continues after step835by repeating the above steps with respect to each of the other capacitance measurement regions of the coupons.

FIG. 9is a flow diagram illustrating an exemplary method for performing the step of obtaining pass/fail criteria data in the method800shown inFIG. 8. In the method900, the steps discussed below (steps905-940) are performed. These steps are set forth in their preferred order. It must be understood, however, that the various steps may occur simultaneously or at other times relative to one another. Moreover, those skilled in the art will appreciate that one or more steps may be omitted.

The method900begins with the fabrication of a plurality of coupons without PTHs (also referred to herein as “not-drilled coupons”) identical to the coupon without PTHs in method800shown inFIG. 8but with varying moisture content (step905). These not-drilled coupons may be, for example, fabricated on one or more special PCB test panels (e.g., corresponding to the at least one coupon310without PTHs on the special PCB test panel300shown inFIG. 3). In accordance with the preferred embodiments of the present invention, each of these not-drilled coupons corresponds to the coupon405without PTHs shown inFIG. 4.

The method900continues with the fabrication of a plurality of coupons with PTHs (also referred to herein as “drilled coupons”) identical to the coupon with PTHs in the method800shown inFIG. 8but with varying moisture content (step910). These drilled coupons may be, for example, fabricated on one or more special PCB test panel (e.g., corresponding to the at least one coupon315with PTHs on the special PCB test panel300shown inFIG. 3). In accordance with the preferred embodiments of the present invention, each of these drilled coupons corresponds to the coupon410with PTHs shown inFIG. 4.

The varying moisture content of the not-drilled coupons in step905and the drilled coupons in step910may be achieved by using materials and manufacturing processes that are within (or just beyond) “defined process limits” that are predicted to influence coupon water content. The terminology “defined process limits” refers to the process limits that define the materials and manufacturing processes for the fabrication of the actual production parts (e.g., the PCB100shown inFIG. 1or the panel200shown inFIG. 2) on which the coupons in the method800shown inFIG. 8are fabricated.

Next, the method900continues by measuring the capacitance of the drilled and not-drilled coupons (step915). Step915may be repeated for each capacitance measurement region of the not-drilled and drilled coupons.

The method900then continues by subjecting the drilled and not-drilled coupons to simulated reflow (step920). Each coupon is subjected to reflow conditions that simulate the process that the actual production parts (e.g., the PCB100shown inFIG. 1or the panel200shown inFIG. 2) will experience. For example, the production parts may be subjected to five passes through a reflow profile that has a peak temperature of 245 C.

Next, the method900continues with the inspection of the drilled and not-drilled coupons for internal and/or external damage (step925). For example, the coupons may be cross sectioned and inspected for internal defects (e.g., laminate crack, inner layer separation, and the like) and for external defects (e.g., blisters).

The method900then continues by establishing a “no-PTH capacitance threshold” for each capacitance measurement region, if possible (step930). The “no-PTH capacitance threshold” is established in step930only if the inspection in step925shows unacceptable defects in at least one not-drilled coupon. The lowest capacitance corresponding to the first signs of unacceptable defects defines the highest allowed capacitance (i.e., the “no-PTH capacitance threshold”) for each capacitance measurement region of the not-drilled coupons. In the event no defects are observed in the not-drilled coupons, even for the coupons that are predicted to have the highest water content, the method1000(which is described below with reference toFIG. 10) may be used to establish this piece of the criteria data.

Next, the method900continues by establishing a “PTH capacitance threshold” for each capacitance measurement region, if possible (step935). The “PTH capacitance threshold” is established in step935only if the inspection in step925shows unacceptable defects in at least one drilled coupon. The lowest capacitance corresponding to the first signs of unacceptable defects defines the highest allowed capacitance (i.e., the “PTH capacitance threshold”) for each capacitance measurement region of the drilled coupons. In the event no defects are observed in the drilled coupons, even for the coupons that are predicted to have the highest water content, the method1000(which is described below with reference toFIG. 10) may be used to establish this piece of the criteria data.

It is possible that the method900will lead to the establishment of the “PTH capacitance threshold” in step935, but not the “no-PTH capacitance threshold” in step930.

Then, the method900continues by establishing a “delta capacitance threshold” for each capacitance measurement region, if possible (step940). For example, the “delta capacitance threshold” may be calculated as the difference between the “PTH capacitance threshold” and the “no-PTH capacitance threshold”. Alternatively, the “delta capacitance threshold” may be calculated as the difference between the “PTH capacitance threshold” and a statistically derived (e.g., the average or mean) capacitance value measured in the step915with respect to the not-drilled coupons.

FIG. 10is a flow diagram illustrating another exemplary method for performing step of obtaining pass/fail criteria data in the method shown inFIG. 8. In the method1000, the steps discussed below (steps1005-1035) are performed. These steps are set forth in their preferred order. It must be understood, however, that the various steps may occur simultaneously or at other times relative to one another. Moreover, those skilled in the art will appreciate that one or more steps may be omitted.

The method1000relies on the actual variations in materials and manufacturing processes as the causes of variations in water content in actual production parts (e.g., the PCB100shown inFIG. 1or the panel200shown inFIG. 2). Typically, the method1000will be used if the method900shown inFIG. 9fails to establish criteria data, to refine criteria data established using the method900shown inFIG. 9, or if preferred by the user (i.e., the criteria data established using the method1000are more representative of actual production parts).

The method1000begins with the fabrication of a plurality of actual production parts each incorporating at least one coupon without PTHs (also referred to herein as “not-drilled coupons”) and at least one coupon with PTHs (also referred to herein as “drilled coupons”) identical to the coupon without PTHs and the coupon with PTHs in method800shown inFIG. 8(step1005). These drilled and not-drilled coupons may be, for example, fabricated on PCBs (e.g., corresponding to the coupons110and115on the PCB100shown inFIG. 1) or a panel (e.g., corresponding to the coupons220and225on the panel200shown inFIG. 2). In accordance with the preferred embodiments of the present invention, these drilled and not-drilled coupons correspond to the coupons405and410shown inFIG. 4.

Next, the method1000continues by measuring the capacitance of the drilled and not-drilled coupons (step1010). Step1010may be repeated for each capacitance measurement region of the not-drilled and drilled coupons.

The method1000then continues by subjecting the drilled and not-drilled coupons to simulated reflow (step1015). Each coupon is subjected to reflow conditions that simulate the process that the actual production parts (e.g., the PCB100shown inFIG. 1or the panel200shown inFIG. 2) will experience. For example, the production parts may be subjected to five passes through a reflow profile that has a peak temperature of 245 C.

Next, the method1000continues with the inspection of the drilled and not-drilled coupons for internal and/or external damage (step1020). For example, the coupons may be cross sectioned and inspected for internal defects (e.g., laminate crack, inner layer separation, and the like) and for external defects (e.g., blisters).

The method1000then continues by establishing a “no-PTH capacitance threshold” for each capacitance measurement region (step1025). The “no-PTH capacitance threshold” is established in step1025when the inspection in step1020shows unacceptable defects in at least one not-drilled coupon. The lowest capacitance corresponding to the first signs of unacceptable defects defines the highest allowed capacitance (i.e., the “no-PTH capacitance threshold”) for each capacitance measurement region of the not-drilled coupons.

Next, the method1000continues by establishing a “PTH capacitance threshold” for each capacitance measurement region (step1030). The “PTH capacitance threshold” is established in step1030when the inspection in step1020shows unacceptable defects in at least one drilled coupon. The lowest capacitance corresponding to the first signs of unacceptable defects defines the highest allowed capacitance (i.e., the “PTH capacitance threshold”) for each capacitance measurement region of the drilled coupons.

Then, the method1000continues by establishing a “delta capacitance threshold” for each capacitance measurement region (step1035). For example, the “delta capacitance threshold” may be calculated as the difference between the “PTH capacitance threshold” and the “no-PTH capacitance threshold”. Alternatively, the “delta capacitance threshold” may be calculated as the difference between the “PTH capacitance threshold” and a statistically derived (e.g., the average or mean) capacitance value measured in the step1010with respect to the not-drilled coupons.

As mentioned above, the method1000is more representative of actual production parts. Nonetheless, the use of the method1000as the first definition of the criteria data can be more costly than the method900shown inFIG. 9. This is because the production parts from which failed coupons were taken in the method1000may need to be scrapped. Hence, it is typically more desirable to use the method900shown inFIG. 9to establish initial criteria that may be refined by the subsequent use of the method1000.

Design flow1100may vary depending on the type of representation being designed. For example, a design flow1100for building an application specific IC (ASIC) may differ from a design flow1100for designing a standard component or from a design flow1100for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

FIG. 11illustrates multiple such design structures including an input design structure1120that is preferably processed by a design process1110. Design structure1120may be a logical simulation design structure generated and processed by design process1110to produce a logically equivalent functional representation of a hardware device. Design structure1120may also or alternatively comprise data and/or program instructions that when processed by design process1110, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure1120may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure1120may be accessed and processed by one or more hardware and/or software modules within design process1110to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown inFIGS. 1-3. As such, design structure1120may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

Design process1110may include hardware and software modules for processing a variety of input data structure types including netlist1180. Such data structure types may reside, for example, within library elements1130and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, and the like). The data structure types may further include design specifications1140, characterization data1150, verification data1160, design rules1170, and test data files1185which may include input test patterns, output test results, and other testing information. Design process1110may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, die press forming, and the like. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process1110without deviating from the scope and spirit of the invention. Design process1110may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, and the like.

Design structure1190may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure1190may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown inFIGS. 1-3. Design structure1190may then proceed to a stage1195where, for example, design structure1190: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, and the like.

One skilled in the art will appreciate that many variations are possible within the scope of the present invention. Thus, while the present invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that these and other changes in form and detail may be made therein without departing from the spirit and scope of the present invention.