Hard macro-to-user logic interface

A hard macro-to-user logic interface of an integrated circuit is described. The integrated circuit includes a core as an application specific circuit block with a transaction interface of a first bit width and includes programmable logic capable of being programmed to instantiate user logic. The user logic has a user interface of a second bit width substantially less than the first bit width. A wrapper circuit couples the user interface and the transaction interface for coupling the core to the user logic.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to the following co-pending U.S. patent applications: U.S. patent application entitled “Interface Lane Device Configuration,” by Patrick C. McCarthy, et al., U.S. patent application entitled “Interface Device Reset,” by Dai D. Tran, et al., U.S. patent application entitled “Configurable Interface” by Paige A. Kolze, et al., and U.S. patent application entitled “Reconfiguration of a Hard Macro via Configuration Registers,” by Jerry A. Case, each of which was filed on the same day as the present application and each of which is assigned to the assignee of the present application. The entire contents of each of the above-referenced co-pending patent applications are incorporated herein by reference for all purposes.

FIELD OF THE INVENTION

One or more aspects of the invention relate generally to integrated circuits, and, more particularly, to a hard macro-to-user logic interface of a programmable logic device.

BACKGROUND OF THE INVENTION

One such FPGA is the Xilinx Virtex™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.

For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”

Heretofore, performance of a design instantiated in programmable logic of an FPGA (“FPGA fabric”) using a Peripheral Component Interconnect (“PCI”) Express (“PCIe”) internal to such FPGA was limited to performance of a PCIe design for instantiation in FPGA fabric (“soft core”). Additional details regarding examples of PCIe soft cores are available from Xilinx, Inc. of San Jose, Calif. and are described in “PCI Express PIPE Endpoint LogiCORE Product Specification,” DS321 (v1.1), Apr. 11, 2005 and in “PCI Express Endpoint Cores v3.4 Product Specification,” DS506, Feb. 15, 2007, both available from Xilinx, Inc.

PCIe soft cores have been implemented as “Endpoint” architectures. Target applications for such Endpoint architecture include: test equipment, consumer graphics boards, medical imaging equipment, data communication networks, telecommunication networks, broadband deployments, cross-connects, workstation and mainframe backbones, network interface cards, chip-to-chip and backplane interconnect, crossbar switches, wireless base stations, high bandwidth digital video, and high bandwidth server applications, among other known add-in cards, host bus adapters, and other known applications.

Accordingly, it would be desirable and useful to provide a PCIe Endpoint internal to an FPGA having enhanced performance over that of a PCIe soft core instantiated in FPGA fabric.

SUMMARY OF THE INVENTION

One or more aspects of the invention generally relate to a hard macro-to-user logic interface of a programmable logic device.

An aspect of the invention is an integrated circuit including a core located in a programmable logic device as an application specific circuit block. The core has a transaction interface having a first bit width. The integrated circuit also includes programmable logic capable of being programmed to instantiate user logic. The user logic has a user interface for coupling with the transaction interface, the user interface having a second bit width substantially less than the first bit width. A wrapper circuit couples the user interface and the transaction interface for coupling the core to the user logic. The wrapper circuit is configured to couple first information of the first bit width from the transaction interface to the user interface and is configured to couple second information of the second bit width from the user interface to the transaction interface.

Another aspect of the invention is a method for coupling a user design instantiated in programmable logic and a hard macro, both of which are implemented in an integrated circuit. A phase signal is generated which alternates between a first logic state and a second logic state synchronously with reference to a first clock signal. Output data associated with the hard macro is sent to a wrapper block. The output data is received in first pairs, each of which includes first output data and second output data. The output data in the wrapper block is first registered responsive to a second clock signal which is substantially slower than the first clock signal. The output data is output from the wrapper block to the user design responsive to the phase signal. The output data output from the wrapper block is output as first bitstreams, each of which includes a first alternating sequence of the first output data and the second output data for each of the first pairs associated therewith. Input data associated with the user design is sent to the wrapper block in second bitstreams. The input data is provided in second pairs, wherein each second pair of the second pairs includes first input data and second input data. Each second bitstream of the second bitstreams includes a second alternating sequence of the first input data and the second input data for each of the second pairs associated therewith. A first portion of the input data in the wrapper block is second registered responsive to the first clock signal and the phase signal. A second portion of the input data in the wrapper block is third registered responsive to the second clock signal. The first portion of the input data in the wrapper block is fourth registered responsive to the second clock signal. The input data is output from the wrapper block to the hard macro responsive to the second clock signal, the input data output from the wrapper block being output as the first input data and the second output data respectively from the fourth registering and the third registering. The first input data and the second input data are output from the wrapper block as separate signals for each of the second bitstreams.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative embodiments the items may be different.

FIG. 1illustrates an FPGA architecture100that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”)101, configurable logic blocks (“CLBs”)102, random access memory blocks (“BRAMs”)103, input/output blocks (“IOBs”)104, configuration and clocking logic (“CONFIG/CLOCKS”)105, digital signal processing blocks (“DSPs”)106, specialized input/output ports (“I/O”)107(e.g., configuration ports and clock ports), and other programmable logic108such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)110.

In some FPGAs, each programmable tile includes a programmable interconnect element (“INT”)111having standardized connections to and from a corresponding interconnect element111in each adjacent tile. Therefore, the programmable interconnect elements111taken together implement the programmable interconnect structure for the illustrated FPGA. Each programmable interconnect element111also includes the connections to and from any other programmable logic element(s) within the same tile, as shown by the examples included at the right side ofFIG. 1.

In the pictured embodiment, a columnar area near the center of the die (shown shaded inFIG. 1) is used for configuration, I/O, clock, and other control logic. Vertical areas109extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated inFIG. 1include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, the processor block110shown inFIG. 1spans several columns of CLBs and BRAMs.

Note thatFIG. 1is intended to illustrate only an exemplary FPGA architecture. The numbers of logic blocks in a column, the relative widths of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the right side ofFIG. 1are purely exemplary. For example, in an actual FPGA more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic. FPGA100illustratively represents a columnar architecture, though FPGAs of other architectures, such as ring architectures for example, may be used. FPGA100may be a Virtex-4™ FPGA from Xilinx of San Jose, Calif.

FIG. 2is a block diagram depicting an exemplary embodiment of a portion of an FPGA200. FPGA200may be substantially similar to FPGA100ofFIG. 1. However, in place of a column of BRLs113are located PCIe Application Specific Integrated Circuit (“ASIC”) cores, namely PCIe hard cores. Notably, rather than using a column of BRLs113, other columns in FPGA100ofFIG. 1may be used. PCIe hard cores201-1through201-4are illustratively shown between two columns of INTs111. Though four PCIe hard cores201-1through201-4are illustratively shown, fewer or more than four PCIe hard cores may be implemented in an FPGA.

FIG. 3is a block diagram depicting an exemplary embodiment of PCIe system300. PCIe system300may be implemented in an FPGA. PCIe system300includes a PCIe hard core (“PCIe core”)210, which may be a PCIe hard core of PCIe hard cores201-1through201-4ofFIG. 2, coupled to a Root Complex321, user logic327, host interface325, and system resources323. PCIe core210includes a physical layer module (“PLM”)305, a datalink layer module (“DLM”)303, a transaction layer module (“TLM”)301, a configuration management module (“CMM”)307, a management block302, and a reset block309.

Within PCIe core210, TLM301is coupled to DLM303for bidirectional communication, and DLM303is coupled to PLM305for bidirectional communication. Additionally, each of TLM301, DLM303, and PLM305is coupled to CMM307for bidirectional communication. Reset block309is coupled to TLM301, DLM303, PLM305, CMM307, and management block302, though not illustratively shown inFIG. 3for purposes of clarity. Management block302is coupled via a read/write interface to CMM307.

PLM305is coupled to Root Complex321via PCIe interface318. Additionally, PLM305may be coupled to system resources323for receiving a clock signal. Reset block309may be coupled to system resources323for receiving reset signaling. Management block302may be coupled to system resources323for dynamic configuration and status monitoring. Configuration interface314may couple host interface325to management block302, and host interface325may thus be coupled to CMM307via configuration interface314and management block302. User logic327, which may be instantiated in FPGA fabric, is coupled to TLM301via transaction interface312.

With continuing reference toFIG. 3, it should be understood that a PCIe core210may be what is known as an “Endpoint.” Examples of applications of PCIe Endpoints include graphics cards, memory cards, and the like. In this example, a PCIe core210is implemented in an FPGA as an ASIC. However, user logic327may be configured for an application implemented with FPGA resources which would interface to such PCIe core210. Additionally, multiple PCIe cores210may be coupled to a Root Complex321to provide a PCIe network, an example of which is described in additional detail with reference toFIG. 4below.

Host interface325may be an interface to a processor of a processor block110ofFIG. 1, namely an embedded processor, or may be a host interface to another type of host. Examples of other types of hosts include a microprocessor instantiated in FPGA fabric, such as a MicroBlaze microprocessor available from Xilinx, Inc. of San Jose, Calif. Another example of a host may be a sequencer instantiated in FPGA fabric, or other known host device that may be instantiated in FPGA fabric.

FIG. 4is a network diagram depicting an exemplary embodiment of a PCIe network400. PCIe network400includes Root Complexes (“RC”)321-1, and Endpoints (“EPs”)322-1through322-3. Although a Root Complex321and three Endpoints322-1through322-3are illustratively shown, it should be appreciated that fewer or more of each than four root complexes may be implemented. PCIe network400may be implemented using FPGAs, where switch matrix410is implemented using programmable interconnects, among other details described below.

Having this understanding of a PCIe network400and a PCIe core210ofFIG. 3, both of which may be implemented in an FPGA, a detailed description of an interface between a hard macro, such as PCIe core210, and user logic instantiated in programmable logic of an FPGA is provided.

FIG. 5Ais a block diagram depicting an exemplary embodiment of interface configuration500for a non-bypass mode. In interface configuration500, hard macros501and502are coupled to respective portions of a user design, namely user design527and user design528. User designs527and528may be instantiated in whole or part in programmable logic, such as programmable logic of an FPGA100ofFIG. 1, for example. Notably, hard macros501and502in the example ofFIG. 5A, as well as the example ofFIG. 5B, are respective PCIe hard cores (“PCIe cores”), as previously described herein. Although it is assumed that hard macros501and502are PCIe cores by way of example, it should be appreciated that one or more other known types of hard macros may be implemented, which may or may not be in combination with a PCIe core.

When placing a hard macro block into FPGA fabric, it may be useful to use routing associated with an adjacent hard macro block to provide sufficient routes for a wider bandwidth than would be available with only a single hard macro block. Another reason for sharing routing between hard macro blocks may be to share pins associated with one or more features as between hard macro blocks. Yet another reason may be to overcome physical routing constraints. Regardless of the reason, it should be appreciated that it may be desirable to operate user logic and a hard macro at same or different frequencies.

FIG. 5Bis a block diagram depicting an exemplary embodiment of interface configuration550for a bypass mode. Interface configuration550includes hard macros501and502coupled to a user design529. User design529may be instantiated in programmable logic, such as programmable logic of FPGA100ofFIG. 1.

With simultaneous reference toFIGS. 5A and 5B, interface configurations500and550, respectively, are further described. Notably, user designs527and528, as well as user design529, may be user logic327ofFIG. 3. Accordingly, transaction interface312ofFIG. 3may be transaction interface505A or505B, respectively, ofFIGS. 5A and 5B. Transaction interfaces505A and505B may include wrapper circuit blocks (“wrapper blocks”)510, which are only illustratively shown in transaction interface505A ofFIGS. 5A and 5B. Alternatively, wrapper blocks510of interface configurations500and550may be part of PCIe cores501and502, where each of those cores includes a respective wrapper block510.

In this example implementation, each PCIe core501and502has a native 64-bit transaction layer side interface, namely 64 input bit paths and 64 output bit paths. InFIG. 5A, PCIe cores501and502are respectively coupled to user designs527and528, which may be separate parts of a single user design, via respective wrapper blocks510. In this example, each user design has a 32-bit wide user interface, namely 32 input bit paths and 32 output bit paths. Notably, for purposes of clarity and not limitation, only data busing is described though other types of signaling associated with PCIe may be implemented. Thus respective wrapper blocks510allow a user interface instantiated in FPGA fabric to use half the number of pins in this example than the number of pins of the native transaction interface of a corresponding PCIe core. Because only half the native transaction interface of a PCIe core may be used, such PCIe core may be operated at approximately half the frequency of a user design associated therewith, as described below in additional detail.

In contrast,FIG. 5Bdoes not illustratively show a separate set of 64 input pins and 64 output pins of PCIe core502and does not illustratively show respective wrapper blocks510. Notably, these pins of PCIe core502and wrapper blocks may exist in interface505B, but are not illustratively shown as they are not used in the bypass mode of operation illustratively shown inFIG. 5B. InFIG. 5B, user design529employs two sets of 32 input pins and two sets of 32 output pins for a total of 64 input pins and 64 output pins. Accordingly, bypass circuitry511, which is not illustratively shown inFIG. 5Aas it is not used in the non-bypass mode illustratively shown inFIG. 5A, is invoked to bypass wrapper blocks510and input and output pins of PCIe core502. Notably, bypass circuitry511may be implemented using multiplexers, with control signaling to select between a bypass mode and a non-bypass mode. InFIG. 5B, a 64-bit wide interface between PCIe core501and user design529is provided.

Accordingly, it should be appreciated that PCIe cores501and502have a configurable width bus interface. In a non-bypass mode, a 32-bit data interface is presented to user logic for packet data input and output by a user of transaction interface505A. And, in a bypass mode, a 64-bit data interface is presented to user logic for packet data input and output by a user of interface505B. As implementation for bypass circuitry511should be understood by one of ordinary skill in the art, an example of such implementation is not described for purposes of clarity.

FIG. 6is a circuit diagram depicting an exemplary embodiment of a portion of a hard macro to user logic interface configuration600. Generally, there are three clock domains associated with interface configuration600, namely a user logic clock domain641, a wrapper clock domain642, and a hard macro clock domain643. Wrapper clock domain642of wrapper block510may include a mix of clock frequencies, where one of those mix of frequencies is associated with clock domain641and another one of those mix of frequencies is associated with clock domain643. For purposes of clarity by way of example and not limitation, it shall be assumed that a portion of transaction interface505A ofFIG. 5Ais being described for coupling hard macro501and user design527.

For purposes of clarity by way of example and not limitation, some frequencies of operation are assumed. However, it should be understood that other frequencies, as well as other data bit widths, may be used. It shall be assumed that clock domain641operates at approximately 250 megahertz (“MHz”), and clock domain643operates at approximately 125 MHz. Furthermore, it shall be assumed that clock domain642associated with wrapper block510operates at approximately 125 MHz and at approximately 250 MHz.

Continuing the example of the PCIe core as the hard macro, as described above, it shall be assumed that PCIe core clock domain643is approximately a 125 MHz clock domain. However, for PCIe, approximately a 250 MHz frequency of operation may be used as is known for an eight physical lane usage, where each lane is eight bits wide. Accordingly, I/Os of PCIe core501may be timed for the approximate 250 MHz operation. However, because data bit width for this example is 32-bits in and 32-bits out of user design527, namely half the available bit width of PCIe core501, PCIe core501may be clocked at half of this frequency, namely approximately 125 MHz.

Interface configuration600includes an output data path portion640for passing data from a PCIe core to user logic and an input data path portion650for passing data from user logic to a PCIe core, respectively. With respect to output data path portion640, a user interface-side647receives data out signal633and an associated phase signal634. Though a single user data out signal633is illustratively shown as only a single instance of a portion of wrapper block510is shown for purposes of clarity by way of example not limitation, it should be appreciated that there are multiple instances within each wrapper block510of input and output data path portions640and650, as shall be described in additional detail below with reference toFIG. 7.

In this example, output data path portion640and input data path portion650are coupled to one another via a control circuit portion, which in this example is implemented with a flip-flop620. Output and input data path portions640and650are coupled to receive output from flip-flop620.

FIG. 7is a block/circuit diagram depicting an exemplary embodiment of 32 instances of each of portions640and650ofFIG. 6for an interface configuration700. Interface configuration700may be a wrapper block510ofFIG. 6. Interface configuration700includes flip-flop620which is configured to provide a phase signal634to each of 32 instances of output data path portion640, namely output data path portions640-1through640-32and to each of 32 instances of input data path portion650, namely input data path portions650-1through650-32. Notably, multiple synchronized flip-flops may be used rather than the single flip-flop620.

Returning toFIG. 6, a PCIe core interface-side644is associated with an input side to output data path portion640of wrapper block510. Additionally, a PCIe core interface-side645is associated with an output side of data input path portion650of wrapper block510. A user logic interface-side647is associated with an output side of output data path portion640of wrapper block510. Additionally, a user logic interface-side646is associated with an input side to data input path portion650of wrapper block510.

Output data path portion640of wrapper block510includes multiplexer613and flip-flops611and612. Input data path portion650of wrapper block510includes flip-flops610,614, and615. Additionally, wrapper block510includes a flip-flop620, the output of which is provided to data path portions640and650as a phase signal634.

With reference to output data path portion640, data is input to flip-flops611and612from respective data input signals661and662of PCIe core501. Flip-flops611and612are clocked responsive to clock signal622. Clock signal622may be obtained by dividing the frequency of clock signal621by two. For example, clock signal622may operate at approximately 125 MHz and clock signal621may operate at approximately 250 MHz. Notably, a clock divider circuit is not illustratively shown; however it should be appreciated that integrated circuits, such as FPGA100ofFIG. 1, may include circuitry for dividing a clock down by two as is known.

Output of flip-flops611and612is coupled to respective data inputs of multiplexer613. Output of flip-flop611is indicated as out 1 signal631, and output of flip-flop612is indicated as out 2 signal632to indicate that these are a pair of separate data bits.

Flip-flop620is clocked responsive to clock signal621, which again is approximately a 250 MHz clock signal. Flip-flop620may be set to an initial state such as a logic 0 or a logic 1. Output of an inverter663is coupled to a data input port of flip-flop620. Output of flip-flop620is coupled to an input port of inverter663, as well as being coupled to a control port of multiplexer613and a clock enable port of flip-flop610.

Output of flip-flop620is phase signal634. Thus, it should be appreciated that output of flip-flop620will toggle between logic 1 and logic 0 responsive to each leading edge of clock signal621. Thus, for example, for a logic 1 used to select out 1 signal631as output from multiplexer613, out 1 signal631is selected to be output from multiplexer613to provide user data out signal633on one clock signal cycle, and on the immediately following clock signal cycle, out 2 signal632is selected to be output from multiplexer613to provide user data out signal633. Thus, user data out signal633output from multiplexer613will be a sequence of out 1, out 2, out 1, out 2, . . . as respectively associated with portions of each of signals631and632. In other words, for this example, a logic 1 for phase signal634may be for selecting a portion of out 1 signal631and a logic 0 for phase signal634may be for selecting a portion of out 2 signal632which portions are respectively combined and provided via user data out signal633. As both user data out signal633and phase signal634are synchronously provided to user design527, user design527may be configured to parse data as between out 1 signal631and out 2 signal632.

For information from user design527to PCIe core501, user data in signal635may include a sequence of input data, namely for example in 1, in 2, in 1, in 2, . . . as respectively associated with in 1 signal601and in 2 signal602. User design527may be configured to multiplex separate input data bits to a single signal, for example such as was described above with reference to output data path portion640.

User data input signal635is provided to a data input port of flip-flop610, and to a data input port of flip-flop615. With respect to user data input signal635provided to a data input port of flip-flop615, this data is indicated as in 2 signal602to be differentiated from in 1 signal601output from flip-flop610. Output from flip-flop610is input to a data input port of flip-flop614.

Flip-flop610is clocked responsive to clock signal621, which as was previously indicated for this example is approximately 250 MHz. Flip-flops614and615are clocked responsive to clock signal622, which for this example is approximately 125 MHz.

Flip-flop610is clock enabled responsive to output of flip-flop620. Because flip-flop610and620are both operated responsive to clock signal621, and because output of flip-flop620correspondingly toggles between a logic 0 and a logic 1, output of flip-flop610on one cycle will be output and on an immediately following signal will not be output. For example, when output from flip-flop620is a logic 1, flip-flop610is clock enabled responsive to such logic 1. Thus, while flip-flop610is clock enabled, output from flip-flop610is provided from user data input signal635responsive to clock signal621. However, on a next cycle, output from flip-flop620is a logic 0, and thus flip-flop610is not clock enabled for that cycle. Accordingly, no output from user data input signal635is provided from flip-flop610responsive to clock signal621when a clock enable input is a logic low in this example.

Recall that user logic clock domain641operates at approximately 250 megahertz. Thus, user data in signal635provided as an input to flip-flop615is clocked out of flip-flop615on every other cycle, as flip-flop615, like flip-flop614, is clocked responsive to clock signal622. Also recall that clock signal622may operate at approximately 125 MHz. By synchronizing clock signals621and622with data propagated via user data input signal635, it should be appreciated that output of flip-flops614and615may be approximately 180 degrees out of phase. In other words, data output from flip-flop614may correspond to approximately one half of the data on user data in signal635, namely data output signal671provided as an input to PCIe core501, and data output from flip-flop615may correspond to approximately the other half of the data propagated via user data in signal635, namely data output signal672provided as an input to PCIe core501. Thus, by clocking both flip-flops614and615responsive to clock signal622, output of flip-flops614and615may be used to provide parsed user input. In other words, as described above, user data in signal635is parsed into in 1 signal601and in 2 signal602. In 1 signal601and in 2 signal602are respectively output from flip-flops614and615via data output signal671and data output signal672, respectively, responsive to leading edges of clock signal622.

Returning toFIG. 7, for PCIe core interface-side644being a 64-bit wide output, data propagated via PCIe core interface-side644may be provided as a 32-bit wide input to interface configuration700, which may be wrapper block510ofFIG. 6, for user interface-side647along with at least one additional input pin to user design527for phase signal634. Moreover, data input to wrapper block510from a 32-bit wide user interface-side646may be converted to a 64-bit wide output from wrapper block510for PCIe core interface-side645.

Accordingly, it should be appreciated that wrapper block510may be used to couple data bit widths of different sizes and different clock rates. Furthermore, it should be appreciated that for a user design having a smaller bit width than a hard macro, operating frequency of the hard macro may be reduced.