A TIA converts an input current into a output voltage. The TIA includes a feedback circuit that controls a bypass current to be extracted from the input current. The feedback circuit includes: a filter that passes low frequency components of the output voltage; a voltage shifter which includes a current source and converts an output signal of the filter into a first shift signal with a time constant; a voltage shifter which includes a current source, and converts a first threshold reference into a second shift signal with another time constant; a comparator which generates a control signal to control the bypass circuit by comparing the first shift signal with the second shift signal; and a comparator which controls the time constant by comparing the control signal with a second threshold reference.

TECHNICAL FIELD

The present invention relates to a transimpedance amplifier used in an optical receiver.

BACKGROUND

In a 10G-EPON (10 Gigabit Ethernet Passive Optical Network) which is a next generation system of optical access systems such as FTTx (Fiber To The x) system or the like, a receiver part of Optical Line Terminal (OLT) in a station building needs to receive burst mode signals with various strengths sent from a plurality of homes. Therefore, a TIA (Trans-Impedance Amplifier) configuring the receiver part of the OLT is required to have high speed responsiveness to the burst mode signals. Furthermore, since a photo detector of the receiver part of the OLT is required to have high receiver sensitivity, an APD (Avalanche PhotoDiode) is used as such a photo detector, for instance. Conventionally, there is a TIA including a control circuit to keep an average of outputs from a TIA to be constant (see Japanese Patent No. 3284506, for example). In such a TIA including the control circuit, a circuit such as a low-pass filter configured by a resistor and a capacitor is used.

CITATION LIST

Here, in the TIA, suitable response time of the control circuit depends on a reception state of burst signals. That is, in receiving the burst signals, a larger time constant is preferable, because it makes the response time longer so as to surpress signal errors against consecutive identical digits (CIDs) within the burst signals. On the other hand, in an interval from an end of one burst signal to a start of another burst signal, a shorter response time is preferable so as for the control circuit to quickly respond to a burst signal coming just after the interval, and to improve communication efficiency by reducing a time of the interval.

In order to change the response time depending on the reception state of the burst signals, a configuration capable of at least increasing the time constant is needed with respect to the longer response time. Therefore, conventionally, a value of the resistor or the capacitor is set large to increase the time constant of the low-pass filter. Such a large resistor or a large capacitor, however, may prevent downsizing of the TIA.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a downsized transimpedance amplifier with an widely adjustable response time.

SUMMARY

The present invention relates to a transimpedance amplifier as one aspect thereof. The transimpedance amplifier is a transimpedance amplifier comprising: a core unit configured to convert a current signal to a output voltage; a bypass circuit configured to generate the current signal by extracting a bypass current from an input current; and a feedback circuit configured to adjust the bypass current based on the output voltage. The feedback circuit includes a filter configured to generates low frequency components of the output voltage; a first shifter configured to generate a first shift signal from the low frequency components with a time constant; a second shifter configured to generate a second from a first threshold reference; a first comparator configured to control the bypass current by comparing the first shift signal and the second shift signal; and a second comparator configured to control the time constant and the another time constant by comparing an output of the first comparator with a second threshold reference.

DETAILED DESCRIPTION

Description of an Embodiment of the Claimed Invention

First, contents of an embodiment of the claimed invention will be listed and described.

The present invention relates to a transimpedance amplifier as one aspect thereof. The transimpedance amplifier is a transimpedance amplifier that converts an input current into an output voltage, comprising: a core unit configured to convert a current signal to the output voltage; a bypass circuit configured to generate the current signal by extracting a bypass current from the input current; and a feedback circuit configured to adjust the bypass current based on the output voltage, wherein the feedback circuit includes a filter configured to generate low frequency components of the output voltage; a first shifter configured to generate a first shift signal from the low frequency components with a time constant; a second shifter configured to generate a second shift signal from a first threshold reference with another time constant; a first comparator configured to control the bypass current by comparing the first shift signal with the second shift signal; and a second comparator configured to control the time constant and the another time constant by comparing an output of the first comparator with a second threshold reference.

In this transimpedance amplifier, the first comparator outputs the first control signal for adjusting the amount of the bypass current on the basis of the first shift signal for which the voltage is increased or reduced according to the output signal of the filter, and the second shift signal for which the voltage is increased or reduced according to the first threshold reference. Therefore, by setting the first threshold reference so as to start extraction of the bypass current by the bypass circuit in the case that the first shift signal becomes a predetermined value for example, the extraction of the current is automatically started according to the output signal of the filter, and a gain is controlled. Also, the second comparator control the time constant and the another time constant by comparing an output of the first comparator with a second threshold reference. Therefore, the time constant, that is, the response time, of the feedback circuit can be appropriately adjusted by setting of the second threshold reference. Since the response time of the feedback circuit can be adjusted independent of values of a resistor and a capacitor, enlargement of the transimpedance amplifier can be suppressed. From the above, according to the present invention, miniaturization of the transimpedance amplifier can be realized while appropriately adjusting the response time of the feedback circuit.

Also, in the transimpedance amplifier, the first shifter may include a series circuit of a first diode and a first parallel circuit, the first diode being put between the filter and the first comparator, the first parallel circuit including a first capacitor and a first current source connected in parallel to the first capacitor, the first current source generating a discharging current for the first capacitor, and the second shifter may include a series circuit of a second diode and a second parallel circuit, the second diode being put between the fast threshold reference and the first comparator, the second parallel circuit including a second capacitor and a second current source connected in parallel to the second capacitor, the second current source generating another discharging current for the second capacitor. Further, the first comparator generates a first control signal to control the bypass circuit and the second comparator, and adjusts the bypass current by changing the first control signal. Further, the second comparator generates a second signal to control the first current source and the second current source. Since the capacitor and the current source are connected in parallel, a discharge current from the capacitor can be increased or reduced, and the response time of the feedback circuit can be appropriately adjusted. Also, by increasing or reducing the respective current amounts of the first current source and the second current source, an operating current source can be stopped (or, the current amount can be made smaller than a predetermined value), or a stopped current source can be operated (or, the current amount can be made larger than the predetermined value). In the state that the current source is stopped (or, the state that the current amount is smaller than the predetermined value. Sometimes it is described as an “OFF state” hereinafter), compared to the state that the current source is operated (or, the state that the current amount is larger than the predetermined value. Sometimes it is described as an “ON state” hereinafter), a flowing current is reduced, and the response time of the feedback circuit is prolonged. In this way, by switching an operating state of a power supply of the current source, the response time of the feedback circuit can be appropriately adjusted.

Also, in the transimpedance amplifier, the time constant of the first shifter may become shorter by increasing the discharging current of the first current source when the first control signal becomes higher than the second threshold reference. Further, the time constant of the first shifter may become longer by decreasing the discharging current of the first current source when the first control signal becomes lower than the second threshold reference. Thus, in the state that the power supply of the first current source is operated (ON state), the discharge current from the capacitor can be increased and the response time of the feedback circuit can be shortened. Also, in the state that the power supply of the first current source is stopped (OFF state), the discharge current from the capacitor can be reduced and the response time of the feedback circuit can be prolonged. That is, by switching the operating state of the current source, the response time of the feedback circuit can be appropriately adjusted.

Also, in the transimpedance amplifier, the second threshold reference may include a first threshold and a second threshold, the first threshold being lower than the second threshold. Further, the time constant of the first shifter becomes shorter by increasing the discharging current of the first current source when the first controls signal becomes higher than the second threshold. Further, the time constant of the first shifter becomes longer by decreasing the discharging current of the first current source when the first control signal becomes lower than the first threshold. By turning the second comparator to the hysteresis comparator and setting thresholds of different values as thresholds based on the second threshold reference, frequent alternate transition to the respective states at the boundary of increasing or reducing the output current of the first current source can be suppressed. As a result, instability of a circuit operation can be suppressed.

DETAILS OF THE EMBODIMENT OF THE CLAIMED INVENTION

First, as one example of a communication system according to the embodiment of the present invention, a PON (Passive Optical Network) system will be described.FIG. 1Ais a block diagram of the PON system. An Optical Line Terminals (OLTs)82inside a station building80is connected with individual Optical Network Units (ONUs)72inside a plurality of homes70a-70c, for example, through communication lines L1and L2which are optical fibers. The OLT82is connected with an optical splitter74through one communication line L1. Further, the optical splitter74is connected with the individual ONUs72through the respective communication lines L2. The optical splitter74distributes an optical signal output from the OLT82to the respective communication lines L2, and contrarily relays optical signals from the ONUs to the communication line L1. The communication lines L1and L2propagate optical signals bidirectionally between the OLT82and the respective ONUs72. The OLT82includes a control circuit84, a transmission unit (transmitter)86and a reception unit (receiver)88. The transmission unit86transmits optical signals into the communication line L1. The reception unit88receives optical signals from the communication line L1. The control circuit84controls the transmission unit86and reception unit88. The wavelength of optical signals transmitted from the transmission unit86and the wavelength of optical signals received in the reception unit88are different from each other.

FIG. 1Bshows waveforms illustrating transition of optical signals input to a photo detector89(seeFIG. 2) of the reception unit88. During a period Ton1, the optical signal from the ONU72of the home70ais input. No optical signal is input during a period Toff1, and the optical signal from the ONU (not shown in the figure) of the home70bis input in a period Ton2. Further, no optical signal is input during a period Toff2, and the optical signal from the ONU (not shown in the figure) of the home70cis input in a period Ton3. Amplitudes of output signals output from the individual ONU72and optical losses of the individual communication lines L2are respectively different from others. Therefore, amplitudes of the optical signals in the periods Ton1, Ton2and Ton3(input signal periods) become different from others like amplitudes A1, A2and A3respectively. In this way, the reception unit88for the PON receives the optical signals with different amplitude from others non-periodically. Also, in the periods Toff1and Toff2(interval periods) for the reception unit88prepares a standby state for the next optical signal. In an amplifier circuit used in the reception unit88, since the amplitudes of the optical signals to be input are different, a feedback circuit is used.

Next, a configuration of the reception unit88included in the OLT82will be described.FIG. 2is a diagram illustrating an example of a configuration of the reception unit88inFIG. 1A. The reception unit88is a 10G-EPON (10 Gigabit Ethernet Passive Optical Network) receiver for example. The reception unit88includes a photo detector89, a transimpedance amplifier (TIA: Trans-Impedance Amplifier)1and a limiting amplifier (LIA: Limiting Amplifier)50.

The photo detector89converts optical signals to electric signals, current signals more specifically. An avalanche photodiode (APD: Avalanche Photo Diode) is used as a photo detector, for example. The current signals output by the photo detector89is input to the TIA1.

The TIA1is an IC (Integrated Circuit) that converts an input current to a voltage signal and outputs an amplified voltage signal. The gain of the TIA1is set to a high value when strength of the input current is small, and set to a low value when the strength of the input current is large. Differential signals (voltage signals) amplified by the TIA1are input to the LIA50. Also, the TIA1and the LIA50are connected to each other through a capacitor51. The capacitor51configures AC coupling appropriate for high-speed responses to burst signals. Therefore, a capacitance of the capacitor51is set to a value smaller than that of a capacitor used in a receiver that receives mainly continuous signals for a trunk line system or the like is used. Details of the TIA1will be described later.

The LIA50is an IC that amplifies the voltage signals with various strengths to the voltage signals with a fixed amplitude. The LIA50equalizes respective DC levels of positive-phase signal and negative-phase of the differential signals. A CDR (Clock and Data Recovery) (not shown in the figure) generates a clock signal with small jitters from the output signal of the LIA50. Then, data decision processing is performed by the clock signal.

Next, the TIA1will be described in detail.FIG. 3is a circuit diagram illustrating the TIA1according to the present embodiment. As illustrated inFIG. 3, the TIA1includes a TIA core unit11(core unit), a differential amplifier12(amplifier unit), a bypass circuit13, and a feedback circuit14. An anode of the photo detector89is connected with an input terminal Tin. Also, a cathode of the photo detector89is connected to a power supply Vpd. An input signal (input current) Iin input to the input terminal Tin is split to a current signal Itia of the TIA core unit11and a bypass current Iagc of the bypass circuit13.

The TIA core unit11includes an amplifier15and a feedback resistor R0, converts the current signal to the voltage signal and outputs the voltage signal. The TIA core unit11amplifies the input current Itia, and outputs an output signal (output voltage) Vtia1to a node Ntia1.

The differential amplifier12amplifies Vtia1-Vref1which is a difference between the output voltage Vtia1output from the TIA core unit11and a reference voltage Vref1applied to a reference voltage terminal Tref1. For example, in the differential amplifier12, when the output voltage Vtia1is equal to the reference voltage Vref1, output voltages Vout and Voutb become equal to each other. The voltage is defined as a center voltage Vcenter. When the output voltage Vtia1is larger than the reference voltage Vref1, the differential amplifier12outputs the output voltage Vout larger than the center voltage Vcenter to an output terminal Tout, and outputs the output voltage Voutb smaller than the center voltage Vcenter to an output terminal Toutb. Also, when the output voltage Vtia1is smaller than the reference voltage Vref1, the differential amplifier12outputs the output voltage Vout smaller than the center voltage Vcenter to the output terminal Tout, and outputs the output voltage Voutb larger than the center voltage Vcenter to the output terminal Toutb. The output voltages Vout and Voutb are complementary signals whose phases are different from each other by 180 degrees.

The bypass circuit13extracts the bypass current Iagc from the input current Iin to generate the current signal Itia according to a control signal from the feedback circuit14. The bypass circuit13includes a diode16and a buffer17. An anode of the diode16is connected to the input terminal Tin, and a cathode of the diode is connected to the buffer17. A control signal Vagc1(details will be described later) output from the feedback circuit14is input to the buffer17. When a control signal Vagc1is lowered, the bypass circuit13lowers a potential between the anode of the diode16and the buffer17, and increases a bypass current Iagc.

In this way, the bypass circuit13bypasses the bypass current Iagc from the input current Iin according to the control signal Vagc1. By the bypassing mechanism described above, a time average of the current signal Itia input to the TIA core unit11is reduced and the gain of the TIA1is reduced as a result. That is, the bypass circuit13is controlled by the feedback circuit14so as to increase the bypass current Iagc and reduce the time average of the input current Itia input to the TIA core unit11when the output voltage Vtia1becomes large.

The feedback circuit14automatically controls an amount of the bypass circuit13based on the output voltage Vtia1output from the TIA core unit11. Details of the feedback circuit14will be described with reference toFIG. 4as well.FIG. 4is a circuit diagram illustrating the feedback circuit14inFIG. 3.

As illustrated inFIG. 4, the feedback circuit14includes a filter18, shifter19and20(first first shifter, second shifter), a comparator21(first comparator), and a hysteresis comparator22(second comparator).

The filter18includes a series circuit of resistor R1and capacitor C1, and a buffer23. The filter18generates low frequency components of the output voltage Vtia1output from the TIA core unit11and outputs them as an output voltage Vtia2at a node between the resistor R1and the capacitor C1. As illustrated inFIG. 6, as the input current Iin input to the input terminal Tin increases, the output voltage Vtia1output from the TIA core unit11and the output voltage Vtia2decreases. The ordinate inFIG. 6is a DC voltage (time average of a voltage signal), and the output voltage Vtia1and the output voltage Vtia2substantially coincide with each other. However, in transient response, the output voltage Vtia2changes with a delay according to a time constant (R1×C1) in contrast with a change of the output voltage Vtia1.

The resistor R1is connected between the node Ntia1and the buffer23. The output voltage Vtia1output from the TIA core unit11is input to one of two ends of the resistor R1. One of two ends of the capacitor C1is connected with an input terminal of the buffer23and another of the two ends of the resistor R1. Another of the two end of the capacitor C1is grounded. Electric charges are charged to the capacitor C1according to the change of the output voltage Vtia1. The buffer23is connected with a node Ntia2between the resistor R1and the capacitor C1, and the output voltage Vtia2is input to the buffer23. The buffer23outputs an output voltage to the shifter19according to the output voltage Vtia2.

The shifter19includes a series circuit of a diode (first diode) D1and a parallel circuit (first parallel circuit). The parallel circuit (first parallel circuit) includes a capacitor (first capacitor) C2, and a current source (first current source) IS1. A current flowing in the current source IS1is changed according to the input signal input to the current source IS1. The output voltage of the buffer23, is input to an anode D1A of the diode D1, namely an input terminal of the shifter19. Also, a cathode D1K of the diode D1is connected with a parallel circuit24including the capacitor C2and the current source IS1. The cathode D1K of the diode D1is connected with a positive input terminal “+” of the comparator21. Also, one of two terminals of the parallel circuit24is connected to the cathode D1K of the diode D1, and the another of the two terminals of the parallel circuit24is grounded. The shifter19generates an output signal (output voltage) Vtia3(first shift signal) based on the output voltage of the buffer23, and outputs it to one input terminal of the comparator21. That is, the shifter19outputs the output signal Vtia3(first shift signal) which changes according to the output signal of the filter18. Details of the output voltage Vtia3will be described later.

The shifter20includes the same configuration as the shifter19. That is, the shifter20includes a series circuit of a diode (second diode) D2of the same electrical characteristic as the diode D1, and a parallel circuit (second parallel circuit). The parallel circuit (second parallel circuit) includes a capacitor (second capacitor) C3of the same electrical characteristic as the capacitor C2; and a current source (second current source) IS2of the same electrical characteristic as the current source IS1. An anode D2A of the diode D2is connected to a reference voltage terminal Tref2. A reference signal (first threshold reference) Vref2is applied to the reference voltage terminal Tref2. Also, a cathode D2K of the diode D2is connected to one of two ends of a parallel circuit including the capacitor C3and the current source IS2. The cathode D2K of the diode D2is connected with a negative input terminal “−” of the comparator21. Another of the two ends of the the parallel circuit is grounded. The shifter20generates an output signal (output voltage) Vtia3′ (second shift signal) based on the reference voltage Vref2input from the reference voltage terminal Tref2, and outputs it to the negative input terminal (not the input terminal to which the Vtia3is input) of the comparator21. That is, the shifter20outputs the output signal Vtia3′ (second shift signal) which changes according to the reference voltage Vref2. The current sources IS1and IS2have a control terminal respectively, and increase a current flowing in the current source (ON state) when the voltage input there is larger than a predetermined value, and decrease the current (OFF state) when the voltage input is smaller than or equal to the predetermined value. For example, NPN type bipolar transistors may be used as the current sources IS1and IS2. In that case, a base (terminal) becomes the control terminal, and a collector current IC is increased or decreased according to a base-emitter voltage VBE (the predetermined value in this case is generally 0.6 to 0.8 V).

The comparator21outputs the control signal Vagc1(first control signal) by comparing the output signal (the output voltage Vtia3) of the shifters19with the output signal of the shifter20(the output voltage Vtia3′). The control signal Vagc1controls the bypass circuit13(adjusts an amount of the bypass current Iagc). Specifically, the comparator21compares the output voltage Vtia3with the output voltage Vtia3′, and outputs the control signal Vagc1determined by a result of the comparison to the bypass circuit13and the hysteresis comparator22. Then, the bypass circuit13controls the bypass current based on the control signal Vagc1. Thus, by adjusting the threshold reference Vref2, as the value of the control signal Vagc1to start a extracting the bypass current, the gain can be automatically controlled. Therefore, the reference Vref2is a threshold reference (first threshold reference) that determines a start timing to extract the bypass current by the bypass circuit13.

The hysteresis comparator22outputs an output signal (output voltage) Vsw1(second control signal) for controlling respective time constants of the shifters19and20according to the control signal Vagc1and a reference signal (second threshold reference) Vref3. Specifically, the hysteresis comparator22turns the output signal (output voltage) Vsw1to a low level (LOW) or a high level (HIGH) by comparing the control signal Vagc1with the reference (second threshold reference) Vref3, and controls the current sources IS1and IS2. That is, the hysteresis comparator22decreases the respective currents flowing in the current sources IS1and IS2and stops the current sources IS1and IS2(OFF state) by setting the output voltage Vsw1to LOW, and increases the respective currents flowing in the current sources IS1and IS2and operates the current sources IS1and IS2(ON state) by setting the output voltage Vsw1to HIGH. Also, the hysteresis comparator22may control the current sources IS1and IS2by adjusting the respective currents flowing in the current sources IS1and IS2. That is, instead of stopping the current sources IS1and IS2, the output currents of the current sources IS1and IS2may be reduced in the ON state. Or, instead of operating the current sources IS1and IS2, the currents flowing in the current sources IS1and IS2may be increased in the OFF state.

The hysteresis comparator22sets two different thresholds, that is, a first threshold and a second threshold larger than the first threshold, based on the reference Vref3which is a second threshold reference applied to a reference terminal Tref3. The hysteresis comparator22defines one of the first threshold and the second threshold as a threshold according to the control signal Vagc1, and compares it with the control signal Vagc1.

Specifically, when the control signal Vagc1starts to decrease from the voltage thereof higher than the first threshold, the hysteresis comparator22defines the first threshold as the threshold reference Vref3. Then, when the control signal Vagc becomes lower than the first threshold, the hysteresis comparator22turns the output voltage Vsw1LOW, and stops the current sources IS1and IS2(OFF state). That is, as illustrated inFIG. 8, when the control signal Vagc1ddecreasing from the voltage higher than a first threshold reference T1becomes smaller than the first threshold T1and the current input to the input terminal Tin becomes an input current IinF, the output voltage Vsw1is turned LOW. Also, when the current input to the input terminal Tin becomes the input current IinF and the output voltage Vsw1is turned LOW, since the current sources IS1and IS2are stopped (OFF state), as illustrated inFIG. 7, the output voltage Vtia3and the output voltage Vtia3′ become high.

On the other hand, the control signal Vagc1starts to increase from the voltage thereof lower than the first threshold, the hysteresis comparator22defines the second threshold as the threshold reference Vref3. Then, when the control signal Vagc1becomes higher than the second threshold, the hysteresis comparator22turns the output voltage Vsw1HIGH, and operates the current sources IS1and IS2(ON state). That is, as illustrated inFIG. 8, when the control signal Vagc1uincreasing from the voltage value lower than the first threshold T1becomes higher than a second threshold T2and the current input to the input terminal Tin becomes an input current IinN, the output voltage Vsw1is turned HIGH. Also, when the current input to the input terminal Tin becomes the input current IinN and the output voltage Vsw1is turned HIGH, the current sources IS and IS2are activated. Therefore, as illustrated inFIG. 7, the output voltage Vtia3and the output voltage Vtia3′ become low.

In each of the case that the current source IS1is operated and the case that it is stopped, a current flowing in the current source IS1and a current flowing into the comparator21from the current source IS1will be described. When the current source IS1is operated, a current IS(ON) flows in the current source IS1, and a current Icomp(ON) flows into the comparator21. At that time, the current IS(ON) is several dozens to several hundreds of the current Icomp(ON).

On the other hand, when the current source IS1is stopped, a current IS(OFF) flows in the current source IS1, and a current Icomp(OFF) flows into the comparator21. At that time, the current IS(OFF) is a negligible small, and is sufficiently small compared to the current Icomp(OFF). Also, the current Icomp(ON) when the current source IS1is operated and the Icomp(OFF) when the current source IS1is stopped have similar levels to one another. Also, even if they are several times different, by appropriately determining the IS(OFF) and IS(ON), a similar effect can be obtained.

Next, response time of the feedback circuit14will be described. The response time of the feedback circuit14is determined based on the time constant of the filter18, or a discharge current of the feedback circuit14.

In the shifter19, when the output voltage Vtia2decreases to a certain level, the current hardly flows to the diode D1, and the voltage of the capacitor C2is turned to the output voltage of the shifter19. A speed at which the output voltage decreases is determined by the discharge current from the capacitor C2. The discharge current from the capacitor C2when the current source IS1is operated becomes a sum of the current Icomp(ON) flowing into the comparator21and the current IS(ON) flowing in the current source IS1. As described above, since the current IS(ON) is several dozens to several hundreds of the current Icomp(ON), the discharge current from the capacitor C2becomes large, and the output voltage decreases relatively quickly. Therefore, the response time is shortened. In this case, by setting the response time determined by the time constant of the filter18longer than the response time determined by the discharge current of the feedback circuit14, the response time of the feedback circuit14is determined dominantly by the time constant of the filter18.

On the other hand, the discharge current from the capacitor C2when the current source IS1is stopped becomes a sum of the current Icomp(OFF) flowing into the comparator21and the current IS(OFF) flowing in the current source IS1. As described above, since the current IS (OFF) is a vary small and negligible, it can be considered that the discharge current from the capacitor C2is substantially the current Icomp(OFF) only. Therefore, the output voltage relatively slowly decreases. Thus, the response time is prolonged. In this case, by setting the response time determined by the discharge current of the feedback circuit14longer than the response time determined by the time constant of the filter18, the response time of the feedback circuit14becomes the time based on the discharge current of the feedback circuit14.

Thus, the response time of the feedback circuit14is changed according to whether the current source IS1is stopped (OFF state) or operated (ON state). That is, as illustrated inFIG. 9, when the current input to the input terminal Tin becomes the input current IinF and the current source IS1is stopped, the response time becomes a response time RTF based on the discharge current flowing in the shifter19. When the minute current IS(OFF) is neglected, capacitance of the capacitor C2is defined as Cx, the current Icomp(OFF) is defined as Ix, and a voltage of the capacitor C2is defined as Δvx, the response time RTF is obtained by a formula (1).
RTF=(Cx/Ix)×ΔVx(1)

On the other hand, as illustrated inFIG. 9, when the current input to the input terminal Tin becomes the input current IinN and the current source IS1is operated, the response time becomes a response time RTN based on the time constant of the filter18. Thus, when a resistance of the resistor R1of the filter18is defined as Ry, the capacitance of the capacitor C1is defined as Cy, and the time constant of the filter18is defined as τ, the response time RTN is obtained by a formula (2).
RTN=τ=Ry×Cy(2)

Next, with reference toFIG. 5, transitions of internal signals of the feedback circuit will be described.FIG. 5is a timing chart illustrating waveforms of the internal signals of the feedback circuit inFIG. 4. The respective waveforms indicate the output voltage Vtia1, the output voltage Vtia2, the output voltage Vtia3, the output voltage Vtia3′, the control signal Vagc1, the reference Vref3, the control signal Vsw1, and the response time of the feedback circuit14in order from the top.

As illustrated inFIG. 5, input burst signals include a preamble part and a payload part. The preamble part includes a predetermined stream of signals input before the payload part is input. The payload part includes the true signals for transmitting and receiving data. While the preamble part is input to the reception unit, an internal state of the feedback circuit14is adjusted to an appropriate state by the above-described feedback operation. Thus, the control signal Vagc1is stabilized and the output voltage is averaged.

Here, in a filter such as a low-pass filter, when the same data (“1” for example) continues in input signals or when a ratio of the same data increases, a level of the signals of the same data becomes closer to a center value (that is, a threshold that the signal changes from “1” to “0”). In this state, the “1” level is close to the center level and the amplitude of the signals from the center level to the “1” level decreases. Therefore, decision errors of two values “1” and “0” tend to occur on a reception unit side. When the time constant is small, since a low-cutoff frequency in the filter becomes high, vulnerability to the consecutive identical digit (CID) becomes more remarkable. On the other hand, when the time constant is large, that is, when the response time is long, since the time before the signal level gets close to the center level becomes long even when the same data (CID) continues, it becomes hard for the signal level to get close to the center level. Thus, in order to maintain tolerance against the CID, it is preferable that the response time is prolonged. Therefore, in a period of receiving the payload part including the signals for transmitting and receiving data (a period of the time t2-t3inFIG. 5), it is preferable that the response time of the feedback circuit14is prolonged.

On the other hand, in an interval from an end of a burst signal to a start of another burst signal, there is a period during which the input signal becomes zero (no signal changes). In such a period, it is needed to stop the feedback circuit and return to a standby state so as to receive the next burst signal. Since a period before returning to the standby state does not contribute to the true communication in any way, it is preferable that the interval time is made as short as possible. In order to shorten the period after stopping the feedback circuit and before returning to the standby state (a period of the time t3-t5inFIG. 5), it is needed to shorten the response time of the feedback circuit14.

In the TIA1according to the present embodiment, the reference Vref2and Vref3are set so that the current sources IS1and IS2are operated and the bypass current is not extracted from the input current by the bypass circuit (AGC OFF) when no signal is received and the input current Iin is very small or substantially zero. Then, as illustrated inFIG. 5, when the preamble part start at the time t0, the output voltage Vtia2and the output voltage Vtia3start to decrease. Specifically, the output voltage Vtia2decreases more slowly than the output voltage Vtia1, because a filter of the resistor R1and the capacitor C1passes only low frequency components of the output voltage Vtia1. Also, though a potential of the anode D1A of the diode D1decreases, a potential of the cathode D1K does not rapidly decreases because of influence of the capacitor C2. Therefore, the output voltage Vtia3decreases at a speed of discharging the electric charges of the capacitor C2by the current flowing in the current source IS1. At a timing at which the output voltage Vtia3decreases to a certain value, the control signal Vagc1starts to decrease. Then, when the output voltage Vtia3becomes smaller than the output voltage Vtia3′, and further decreases to the certain value, the control signal Vagc1becomes the value to start the current extraction, and the extraction of the current is started by the bypass circuit13(AGC ON).

Then, at a timing (the time t1) at which the output voltage Vtia3further decreases and the control signal Vagc1becomes smaller than the first threshold T1based on the reference Vref3, the output voltage Vsw1becomes LOW, and the current sources IS1and IS2are stopped (OFF state). The first threshold T1based on the reference Vref3is set such that at least the time t1is before a timing (the time t2) of starting reception of the payload part. When the current sources IS1and IS2are stopped, the response time of the feedback circuit14becomes the response time RTF based on the discharge current that flows in the feedback circuit14. Since the response time RTF depends on a speed of discharging the capacitor C2by the minute current, it is relatively long. Also, when the current sources IS1and IS2are stopped, the output voltage Vtia3and the output voltage Vtia3′ become high. Also, the threshold based on the reference Vref3is turned to the second threshold T2higher than the first threshold T1.

The payload part starts at the time t2and ends at the time t3. When the payload part ends the output voltage Vtia2and the output voltage Vtia3start to increase, and the control signal Vagc1becomes high accordingly. Specifically, the output voltage Vtia2becomes high by the time constant determined by the resistor R1and the capacitor C1. Since charging by the diode D1is at a sufficiently high speed, the output voltage Vtia3also becomes high by the time constant of the resistor R1and the capacitor C1. Then, when the control signal Vagc1becomes large to a certain value, the current extraction is stopped (AGC OFF). Further, at a timing (the time t4) at which the control signal Vagc1becomes higher than the second threshold based on the reference Vref3, the output voltage Vsw1becomes HIGH, and the current sources IS1and IS2are operated (ON state). When the current sources IS1and IS2are operated, the response time of the feedback circuit14becomes the response time RTN based on the time constant τ of the filter18. The response time RTN is the response time based on a resistance of the resistor R1and the capacitance of the capacitor C1, and may be short compared to the response time RTF.

In this way, since the response time can be turned to the relatively long response time RTF in the period of the time t1-t4, the response time can be prolonged in the period of receiving the payloadpart, and the tolerance against the CID can be maintained. Also, since the response time can be turned to the relatively short response time RTN at the time t4after the time t3at which the payload part ends, the recovery time to the standby state after stopping the current extraction can be shortened.

Next, effects of the TIA1according to the present embodiment will be described.

In the TIA1according to the present embodiment, the comparator21outputs the control signal Vagc1that controls the bypass circuit13from the output signal of the shifter19, that is, the output voltage Vtia3, and the output signal of the shifter20, that is, the output voltage Vtia3′ based on the reference Vref2which is the first threshold reference. Therefore, by setting the reference Vref2so as to start the extraction of the current by the bypass circuit13when the output voltage Vtia3of the shifter19becomes a predetermined value, for example, the extraction of the current is automatically started according to the output voltage Vtia3, and a time average of the current signal input to the TIA core unit11is controlled so as to be a predetermined value (Also, while the gain of the output voltage to the input current of the TIA core unit11changes depending on the time average of the current signal, this control may be performed with adjustment of the gain to a predetermined value as a target. In that case, this control is called automatic gain control (AGC: Auto Gain Control)).

Also, the hysteresis comparator22outputs the control signal (output voltage) Vsw1for controlling the time constants of the shifters19and20by comparing the control signal Vagc1output by the comparator21with the reference Vref3which is the second threshold reference. Therefore, the response time of the feedback circuit14can be appropriately adjusted by the setting of the reference Vref3. Since the response time of the feedback circuit14can be adjusted independent of the values of the resistor and the capacitor, enlargement of the TIA1can be suppressed.

Also, in the TIA1according to the present embodiment, the shifter19includes a series circuit of the diode D1and the parallel circuit24. The parallel circuit24includes the capacitor C2and the current source IS1connected in parallel to the capacitor C2. Then, the anode D1A of the diode D1is connected to the output of the filter18. One of two ends of the parallel circuit24and the input of the comparator21are connected to the cathode D1K of the diode D1, and another of the two ends of the parallel circuit24is grounded. Also, the shifter20includes a series circuit of the diode D2and another parallel circuit. The another parallel circuit includes the capacitor C3and the current source IS2connected in parallel to the capacitor C3. Then, the anode D2A of the diode D2is connected to the reference voltage terminal Tref2. The input of the comparator21is connected to the cathode D2K of the diode D2, and another of the two ends in the parallel circuit is grounded. Then, the control signal (output voltage) Vsw1is input to the current sources IS1and IS2, and the respective currents flowing in the current sources IS1and IS2are increased or reduced according to the control signal (output voltage) Vsw1.

In this way, since the capacitor C2is included in the shifter19and the capacitor C2and the current source IS1are connected in parallel to each other, the response time of the feedback circuit14can be appropriately adjusted utilizing the discharge current from the capacitor C2. Also, by setting the reference Vref3so as to stop the operating current sources IS1and IS2or to operate the stopped current sources IS1and IS2by increasing or reducing the current flowing in the current sources IS1and IS2according to the control signal (output voltage) Vsw1, the operating state of the current sources IS1and IS2can be controlled according to the control signal Vagc1.

In the state that the current sources IS1and IS2are stopped (OFF state), the respective currents flowing therein decreases and the response time of the feedback circuit14becomes long compared to the state that the current sources IS1and IS2are operated (ON state). In this way, by switching the operating state of the current sources IS1and IS2, the response time of the feedback circuit14can be appropriately adjusted. Then, since the response time of the feedback circuit14can be adjusted by switching an activation state of the current sources IS1and IS2independent of the values of the resistor and the capacitor, the enlargement of the TIA1can be suppressed. From the above, according to the present invention, miniaturization of the transimpedance amplifier can be realized while appropriately adjusting the response time of the feedback circuit14.

Also, In the TIA1according to the present embodiment, when the output currents of the current sources IS1and IS2are increased (ON state) such as the case that the high level (HIGH) higher than the predetermined value is input to the current sources IS1and IS2by the hysteresis comparator22and they are operated, the current that flows flowing in the current source IS1of the shifter19is larger than the current input from the shifter19to the comparator21. On the other hand, when the output currents of the voltage sources IS1and IS2are reduced (OFF state) such as the case that the low level (LOW) smaller than or equal to the predetermined voltage is input to the current sources IS1and IS2by the hysteresis comparator22and they are stopped, the current flowing in the current source IS1of the shifter19is smaller than the current input from the shifter19to the comparator21.

Thus, the discharge current from the capacitor C2can be increased and the response time of the feedback circuit14can be shortened in the state that the current source IS1is activated, and the discharge current from the capacitor C2can be reduced and the response time of the feedback circuit14can be prolonged in the state that the current source IS1is stopped. That is, by switching the activation state of the current source IS1, the response time of the feedback circuit14can be appropriately adjusted.

Also, in The TIA1according to the present embodiment, in the hysteresis comparator22, the first threshold T1and the second threshold T2larger than the first threshold T1, which are based on the reference voltage Vref3, are set. Then, when the control signal Vagc1becomes lower than the first threshold T1, the current source IS1is stopped or the like, and the current flowing in the current source IS1is reduced to a very small value. Also, when the control signal Vagc1increases from the state of being lower than the first threshold T1and becomes higher than the second threshold T2, the current source IS1is activated or the like, and the current flowing in the current source IS1is increased. By setting the first threshold T1and the second threshold T2of different values as the thresholds based on the reference Vref3, frequent alternate transition between the respective states of increasing and reducing the current flowing in the current source IS1can be suppressed. As a result, instability of such a circuit operation like an oscillation can be suppressed.

The embodiment of the present invention has been described above, however, the present invention is not limited to the above-described embodiment. For example, it has been described that both of the shifter19and20include the capacitor, however, without being limited to that, a configuration may be such that the shifter20does not include the capacitor as in a feedback circuit14A illustrated inFIG. 10.

Also, a configuration of the diode included in the shifter19is not limited either, and the diode may be configured by two diodes that are diodes D1and D1′ as in a feedback circuit14B illustrated inFIG. 11for example, or the number of steps may be larger. Also, the diode may be configured by diode connection of a bipolar transistor or diode connection of a MOS transistor. Also, in the case of turning the diode of the shifter19to the configuration by the two diodes D1and D1′, the diode of the shifter20may be also turned to the configuration by other two diodes D2and D2′, the electrical characteristic of the diode D2may be the same as the electrical characteristic of the diode D1, and the electrical characteristic of the diode D2′ may be the same as the electrical characteristic of the diode D1′.

Also, it has been described that the current sources IS1and IS2are grounded in the shifter19and20, however, without being limited thereto, for example, as in a feedback circuit14C illustrated inFIG. 12, the current sources IS1and IS2may be connected to a negative power supply ns. By the configuration, a margin can be provided in an operation characteristic of the current sources IS1and IS2against fluctuation of a power supply voltage.

Also, the current sources IS1and IS2may not be independent from each other and may be, for example, configured by a current mirror circuit so that the current flowing in the current source IS2is in proportional to the current flowing in the current source IS1. In that case, the output of the hysteresis comparator22may be connected only with a control terminal of the current source IS1(for example, base of a bipolar transistor).

Also, it has been described that the first threshold and the second threshold are set by the hysteresis comparator22, however, without using the hysteresis comparator, an activation operation state of the current source may be controlled by one threshold.