Pixel structure

A pixel structure includes a first substrate, a thin-film transistor, a second insulation layer, a first transparent conduction layer and a second substrate. The thin-film transistor includes a gate electrode formed on the first substrate, a semiconductor layer formed on the gate electrode, a first insulation layer located between the semiconductor layer and the gate electrode, and an electrode layer including a source electrode and a drain electrode. The source electrode covers a portion of the semiconductor layer. The drain electrode covers a portion of the semiconductor layer. The second insulation layer covers the thin-film transistor. The first transparent conduction layer is formed on the second insulation layer. An opening is formed in the first transparent conduction layer along a fringe of the semiconductor layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a pixel structure, and more particularly, to a pixel structure capable of reducing induced current.

2. Description of the Prior Art

In general, a liquid crystal display panel in current industry is heading to high contrast ratio, high brightness, high color saturation, fast response and wide viewing angle. For maximizing the aperture ratio within limited space, ITO (Indium Tin Oxide) in a pixel structure usually covers with a whole piece as a common electrode. The induced current is generated between the TFT (Thin-film transistor) and the ITO above the TFT. The induced current is generated even if the TFT is off, such that the TFT has leakage current when the TFT is off. The leakage current of the TFT causes problems of uneven brightness of display panel and cross-talk.

SUMMARY OF THE INVENTION

The present invention provides a pixel structure capable of reducing induced current, in order to solve problems of the prior art.

According to an embodiment of the present invention, a pixel structure comprises a first substrate, a thin-film transistor, a second insulation layer, a first transparent conduction layer and a second substrate. The thin-film transistor comprises a gate electrode, a semiconductor layer, a first insulation layer and an electrode layer. The gate electrode is formed on the first substrate. The semiconductor layer is formed on the gate electrode. The first insulation layer is located between the semiconductor layer and the gate electrode. The electrode layer comprises a source electrode and a drain electrode. The source electrode covers a portion of the semiconductor layer. The drain electrode covers a portion of the semiconductor layer. The second insulation layer covers the thin-film transistor. The thickness of the second insulation layer is less than 11000 Å. The first transparent conduction layer is formed on the second insulation layer. The second substrate is arranged above the first substrate. An opening is formed in the first transparent conduction layer along a fringe of the semiconductor layer. A shape of the opening is corresponding to an outline of the fringe of the semiconductor layer.

According to another embodiment of the present invention, a pixel structure comprises a first substrate, a thin-film transistor, a second insulation layer, a first transparent conduction layer and a second substrate. The thin-film transistor comprises a gate electrode, a semiconductor layer, a first insulation layer and an electrode layer. The gate electrode is formed on the first substrate. The semiconductor layer is formed on the gate electrode. The first insulation layer is located between the semiconductor layer and the gate electrode. The electrode layer comprises a source electrode and a drain electrode. The source electrode covers a portion of the semiconductor layer. The drain electrode covers a portion of the semiconductor layer. The second insulation layer covers the thin-film transistor. The first transparent conduction layer is formed on the second insulation layer. The second substrate is arranged above the first substrate. An opening is formed in the first transparent conduction layer along a fringe of a region of the semiconductor layer not covered by the electrode layer.

DETAILED DESCRIPTION

Please refer toFIG. 1.FIG. 1is a cross-sectional view of a first pixel structure according to a first embodiment of the present invention. As shown inFIG. 1, a first pixel structure10aof a first embodiment of the present invention comprises a first substrate11, a thin-film transistor12, a transistor insulation layer16, a transparent conduction layer17aand a second substrate18. The thin-film transistor12is formed on the first substrate11. The thin-film transistor12comprises a gate electrode13, a semiconductor layer14and an electrode layer15. The gate electrode13is formed on the first substrate11. The semiconductor layer14is formed on the gate electrode13. A gate insulation layer131is formed between the semiconductor layer14and the gate electrode13. The electrode layer15comprises a source electrode151and a drain electrode152. The source electrode151and the drain electrode152respectively cover a portion of the semiconductor layer. The transistor insulation layer16covers the thin-film transistor12. The transparent conduction layer17ais formed on the transistor insulation layer16. The second substrate18is arranged above the first substrate11. In addition, a pixel electrode layer19is formed between the transistor insulation layer16and the gate insulation layer131. In the present embodiment, the pixel electrode layer19is made of the same material as the transparent conduction layer17a, but the present invention is not limited thereto.

Please refer toFIG. 2, and also refer toFIG. 1.FIG. 2is a top view of the first pixel structure ofFIG. 1. For simplification, some elements of the pixel (such as the first substrate11, the second substrate18, the transistor insulation layer16and the gate electrode13) structure is omitted inFIG. 2.FIG. 1is the cross-sectional view in a direction A-A ofFIG. 2(points A inFIG. 2are configured to show the direction, not to show the exact positions of the points). In the present embodiment, an opening171ais formed in the transparent conduction layer17aalong a fringe of the semiconductor layer14(area of dotted line inFIG. 2), such that the transparent conduction layer17ais not formed above the semiconductor layer14. In other words, a shape of the opening171aof the transparent conduction layer17ais corresponding to an outline of the fringe of the semiconductor layer14. In the present embodiment, the semiconductor layer14is a polygon which has more than four edges, but the present invention is not limited thereto. In another embodiment, the semiconductor layer14can be a triangle, quadrilateral, or rectangle. The shape of the opening171aof the transparent conduction layer17ais the same as the outline of the fringe of the semiconductor layer14, but the present invention is not limited thereto. For example, the shape of the opening171aof the transparent conduction layer17acan be any other shape close to the outline of the fringe of the semiconductor layer14. A portion of the opening171aof the transparent conduction layer17acan be aligned with or be overlapped or be away from the semiconductor layer14. When the transparent conduction layer17ais formed above the semiconductor layer14, an induced current is generated between the transparent conduction layer17aand the semiconductor layer14of the thin-film transistor12. In general, the induced current can be reduced by thickening the transistor insulation layer16. When a thickness of the transistor insulation layer16is above 30000 Å, the induced current between the transparent conduction layer17aand the semiconductor layer14of the thin-film transistor12is too small to affect characteristic of the thin-film transistor12. Such arrangement is able to prevent a display panel from uneven brightness and cross-talk. However, the thickness of the transistor insulation layer16is too thick, such that a distance between the transparent conduction layer17aand the pixel electrode layer19is so far that the electric field between them is affected, so as to further affect the liquid crystal layer being driven. In the present embodiment, the thickness of the transistor insulation layer16is preferred less than 11000 Å. The induced current is reduced by forming the opening171ain the transparent conduction layer17a, not by thickening the transistor insulation layer16. The transparent conduction layer17ais not formed above the semiconductor layer14in order to prevent the induced current between the transparent conduction layer17aand the semiconductor layer14of the thin-film transistor12from being generated.

Please refer toFIG. 1again. A distance51is between a fringe of the orthographic projection of the transparent conduction layer17aon the first substrate11and a fringe of the orthographic projection of the semiconductor layer14on the first substrate11. In the present embodiment, the distance51is between 0 micrometers and 5 micrometers. In other words, the orthographic projection of the transparent conduction layer17aon the first substrate11does not overlap the orthographic projection of the semiconductor layer14on the first substrate11. In the present embodiment, the fringe of the orthographic projection of the transparent conduction layer17aon the first substrate11is separated from the fringe of the orthographic projection of the semiconductor layer14on the first substrate11by a fixed distance, but the present invention is not limited thereto. In another embodiment of the present invention, the distance between the fringe of the orthographic projection of the transparent conduction layer17aon the first substrate11and the fringe of the orthographic projection of the semiconductor layer14on the first substrate11can be changed and be arranged between 0 micrometers and 5 micrometers.

According to the above arrangement, the opening171ais formed in the transparent conduction layer17aof the first pixel structure10aof the present invention, such that the transparent conduction layer17ais not formed above the semiconductor layer14, in order to reduce the induced current between the transparent conduction layer17aand the semiconductor layer14of the thin-film transistor12, so as to further reduce the leakage current of the thin-film transistor12when the thin-film transistor12is off. Therefore, the first pixel structure10aof the present invention is able to solve problems of uneven brightness of display panel and cross-talk.

Please refer toFIG. 3and also refer toFIG. 4.FIG. 3is a cross-sectional view of a first pixel structure according to a second embodiment of the present invention.FIG. 4is a top view of the first pixel structure ofFIG. 3.FIG. 3is the cross-sectional view along a direction B-B ofFIG. 4(points B inFIG. 4are configured to show the direction, not to show the exact positions of the points). As shown inFIG. 3andFIG. 4, a first pixel structure10bof the second embodiment of the present invention is similar to the first pixel structure10aof the first embodiment. The difference between them is a smaller opening171bis formed in a transparent conduction layer17bof the first pixel structure10bof the second embodiment. The opening171bis smaller than the opening171a, such that a portion of the transparent conduction layer17bis formed above the semiconductor layer14. In other words, a portion of the orthographic projection of the transparent conduction layer17bon the first substrate11overlaps the orthographic projection of the semiconductor layer14on the first substrate11. An overlapping distance S2is between two fringes of the two orthographic projections on the first substrate11. The overlapping distance S2can be less than 1.5 micrometers. In the overlapped region, even a portion of the transparent conduction layer17bis formed above the semiconductor layer14, since the source electrode151covers the semiconductor layer14, the induced current between the transparent conduction layer17band the semiconductor layer14is small enough to ignore the leakage current of the thin-film transistor12when the thin-film transistor12is off. In the present embodiment, a dimension of the opening of the transparent conduction layer17bis decreased. The induced current between transparent conduction layer17band the semiconductor layer14of the thin-film transistor12is controlled in an allowable range. It is worth noting that, the shape of the opening171bof the transparent conduction layer17binFIG. 4is a rectangle, but the present invention is not limited thereto. For example, the shape of the opening171bof the transparent conduction layer17bcan be any other shape close to the outline of the fringe of the semiconductor layer14.

Please refer toFIG. 5and also refer toFIG. 6.FIG. 5is a cross-sectional view of a first pixel structure according to a third embodiment of the present invention.FIG. 6is a top view of the first pixel structure ofFIG. 5.FIG. 5is the cross-sectional view along a direction C-C ofFIG. 6(points C inFIG. 6are configured to show the direction, not to show the exact positions of the points). As shown inFIG. 5andFIG. 6, a first pixel structure10cof the third embodiment of the present invention is similar to the first pixel structure10aof the first embodiment. The difference between them is an opening171cis formed in the transparent conduction layer17cof the first pixel structure10calong a fringe of a region of the semiconductor layer14not covered by the electrode layer15(area of dotted line inFIG. 6). In other words, a shape of the opening171cof the transparent conduction layer17cis corresponding to an outline of the fringe of the region of the semiconductor layer14not covered by the electrode layer15. In the present embodiment, the shape of the opening171cof the transparent conduction layer17cis the same as the outline of the fringe of the region of the semiconductor layer14not covered by the electrode layer15, but the present invention is not limited thereto. For example, the shape of the opening171cof the transparent conduction layer17ccan be any other shape close to the outline of the fringe of the region of the semiconductor layer14not covered by the electrode layer15. A portion of the opening171cof the transparent conduction layer17ccan be aligned with or be overlapped or be away from the semiconductor layer14. Since the induced current of the transparent conduction layer17cis mainly generated on the region of the semiconductor layer14not covered by the electrode layer15. If the transparent conduction layer17cis formed above the region of the semiconductor layer14not covered by the electrode layer15, the induced current between the transparent conduction layer17cand the semiconductor layer14of the thin-film transistor12is generated. In the present embodiment, the opening171cof the transparent conduction layer17cis formed along the fringe of the region of the semiconductor layer14not covered by the electrode layer15, such that the transparent conduction layer17cis not formed above the region of the semiconductor layer14not covered by the electrode layer15. The arrangement of the opening171cof the present embodiment is able to not only reduce the induced current between the transparent conduction layer17cand the semiconductor layer14of the thin-film transistor12, but also decrease the dimension of the opening.

Please refer toFIG. 5again. A distance S3is between a fringe of the orthographic projection of the transparent conduction layer17con the first substrate11and a fringe of the orthographic projection of the region of the semiconductor layer14not covered by the electrode layer15on the first substrate11. In the present embodiment, the distance S3is between 0 micrometers and 3.5 micrometers. In other words, the orthographic projection of the transparent conduction layer17aon the first substrate11does not overlap the orthographic projection of the region of the semiconductor layer14not covered by the electrode layer15on the first substrate11. In the present embodiment, the fringe of the orthographic projection of the transparent conduction layer17aon the first substrate11is separated from the fringe of the orthographic projection of the region of the semiconductor layer14not covered by the electrode layer15on the first substrate11by a fixed distance, but the present invention is not limited thereto. In another embodiment of the present invention, a distance between the fringe of the orthographic projection of the transparent conduction layer17aon the first substrate11and the fringe of the orthographic projection of the region of the semiconductor layer14not covered by the electrode layer15on the first substrate11can be changed and be arranged between 0 micrometers and 3.5 micrometers.

Please refer toFIG. 7and also refer toFIG. 8.FIG. 7is a cross-sectional view of a first pixel structure according to a fourth embodiment of the present invention.FIG. 8is a top view of the first pixel structure ofFIG. 7.FIG. 7is the cross-sectional view along a direction D-D ofFIG. 8(points D inFIG. 8are configured to show the direction, not to show the exact positions of the points). As shown inFIG. 7andFIG. 8, a first pixel structure10dof the fourth embodiment of the present invention is similar to the first pixel structure10cof the third embodiment. The difference between them is a smaller opening171dis formed in a transparent conduction layer17dof the first pixel structure10dof the fourth embodiment. The opening171dis smaller than the opening171c, such that a portion of the transparent conduction layer17dis formed above the region of the semiconductor layer14not covered by the electrode layer15. Since a portion of the drain electrode152covers the semiconductor layer14, the direction D-D of the cross-sectional view is arranged at a side of the drain electrode152to clearly show the opening171dof the transparent conduction layer17don a region of the semiconductor layer14not covered by the drain electrode152. Wherein, a portion of the orthographic projection of the transparent conduction layer17don the first substrate11overlaps the orthographic projection of the region of the semiconductor layer14not covered by the electrode layer15on the first substrate11. An overlapping distance S4is between two fringes of the two orthographic projections beside the drain electrode152on the first substrate11. The overlapping distance S4can be less than 1 micrometers. In the overlapped region, even a portion of the transparent conduction layer17dis formed above the region of the semiconductor layer14not covered by the electrode layer15, the induced current between the transparent conduction layer17dand the semiconductor layer14of the thin-film transistor12is small enough to ignore the leakage current of the thin-film transistor12when the thin-film transistor12is off. In the present embodiment, a dimension of the opening of the transparent conduction layer17dis further decreased. The induced current between transparent conduction layer17dand the semiconductor layer14of the thin-film transistor12is controlled in an allowable range. It is worth noting that, the shape of the opening171dof the transparent conduction layer17dinFIG. 8is a rectangle, but the present invention is not limited thereto. For example, the shape of the opening171dof the transparent conduction layer17dcan be any other shape close to the outline of the fringe of the semiconductor layer14.

In the above embodiments, the first pixel structure can further comprise a liquid crystal layer22. Moreover, the transparent conduction layer17a,17b,17cand17dcan be a common electrode. In addition, the materials of the thin-film transistor and the insulation layer of the pixel structure of the present invention are not limited. The thin-film transistor of the pixel structure of the present invention can be made of oxide semiconductor materials. For example, the semiconductor layer of the thin-film transistor can be made of indium gallium zinc oxide (InGaZnOx), indium tin zinc oxide, indium gallium oxide, indium zinc oxide, gallium oxide, cadmium oxide, magnesium oxide, calcium Oxide, strontium oxide, barium oxide, titanium oxide, tantalum oxide, aluminum oxide, indium oxide, niobium oxide, hafnium oxide, tin oxide, zinc oxide, zirconia oxide, copper oxide, yttrium oxide, barium yttrium oxide and tin samarium oxide or made of a combination of them. A position of the gate insulation layer131adjacent to the semiconductor layer14comprises silicate (SixOy). The gate insulation layer131can be a double layer structure comprising a lower layer made of silicon nitride and a upper layer made of silicon oxide, or the gate insulation layer131can be a single layer structure made of silicon nitride or silicon oxide. The transistor insulation layer16can be a double layer structure comprising a lower layer made of silicon oxide and a upper layer made of silicon nitride, or the transistor insulation layer16can be a single layer structure made of silicon nitride or silicon oxide. In additional, an oxygen content of a position the transistor insulation layer16adjacent to the semiconductor layer14can be greater than an oxygen content of a position of the transistor insulation layer16away from the semiconductor layer14. The pixel structure of the embodiments of the present invention can be made of above materials, but the present invention is not limited thereto.

According to above embodiments andFIG. 1toFIG. 8, the first pixel structure is made by a manufacturing process of six photomasks, but the present invention is not limited thereto. The arrangement of the opening in the transparent conduction layer of first to fourth embodiments of the first pixel structure can be applied to different pixel structures. For simplification, here are three examples.FIG. 9,FIG. 11andFIG. 12are cross-sectional views for showing the present invention applied in different pixel structures. Please refer toFIG. 9.FIG. 9is a cross-sectional view of a second pixel structure of the present invention. As shown inFIG. 9, a second pixel structure90of the present invention is similar to the first pixel structure10a. The difference between them is the second pixel structure90is made by a manufacturing process of seven photomasks. The second pixel structure90further comprises a cover insulation layer92. The pixel electrode layer19is formed between the transistor insulation layer16and the cover insulation layer92. A transparent conduction layer97is formed on the cover insulation layer92. Similar to the first embodiment of the first pixel structure, the distance is between a fringe of the orthographic projection of the transparent conduction layer97on the first substrate11and the fringe of the orthographic projection of the semiconductor layer14on the first substrate11. The arrangement of the opening of the transparent conduction layer97of the second pixel structure90is similar to the arrangement of the opening of the first embodiment of the first pixel structure, but the present invention is not limited thereto. The arrangement of the opening of the transparent conduction layer97of the second pixel structure90can be similar to the arrangement of the opening of the second embodiment, the third embodiment or the fourth embodiment of the first pixel structure. Please refer toFIG. 10andFIG. 11.FIG. 10is a diagram showing a display area and a surrounding area of the present invention.FIG. 11is a cross-sectional view of a third pixel structure of the present invention. As shown inFIG. 10andFIG. 11, the first substrate11of the present invention comprises a display area302and a surrounding area304. The semiconductor layer14of the display area302of the third pixel structure100comprises oxide semiconductor materials (such as InGaZnOx, IGZO). An active insulation layer102covers the semiconductor layer14. Two via holes are formed in the active insulation layer102and configured to be penetrated through respectively by the source electrode151and the drain electrode152such that the source electrode151and the drain electrode152can be connected to the semiconductor layer14. The transistor insulation layer16covers the thin-film transistor12. A transparent conduction layer107is formed on the transistor insulation layer16. Similar to the second embodiment of the first pixel structure of the present invention, a portion of an orthographic projection of the transparent conduction layer107on the first substrate11overlaps the orthographic projection of the semiconductor layer14on the first substrate11. An overlapping distance S2is between two fringes of the two orthographic projections on the first substrate11. The arrangement of the opening of the transparent conduction layer107of the third pixel structure100is similar to the arrangement of the opening of the second embodiment of the first pixel structure, but the present invention is not limited thereto. The arrangement of the opening of the transparent conduction layer107of the third pixel structure100can be similar to the arrangement of the opening of the first embodiment, the third embodiment or the fourth embodiment of the first pixel structure. In addition, a trace-change structure108is formed on the first substrate11in the surrounding area304. When a trace is formed but is blocked by some structures on the same surface, the trace-change structure108is configured to bypass the structures. The trace-change structure comprises a first trace122, a second trace124, a third trace126, a connecting electrode128and a block structure130. The first trace122is formed on the first substrate11and made of the same material as the gate electrode13. The second trace124is formed on the gate insulation layer131and made of the same material as the electrode layer15. A via hole is formed in the gate insulation layer131and configured to be penetrated through by the second trace124such that the second trace124can be electrically connected to the first trace122. The block structure130is formed on the gate insulation layer131and made of the same material as the active insulation layer102. The third trace126is formed on the block structure130and made of the same material as the electrode layer15. The connecting electrode128is formed on the transistor insulation layer16and made of the same material as the transparent conduction layer107. Two via holes are formed in transistor insulation layer16and configured to be penetrated through by the connecting electrode128such that the connecting electrode128can be respectively electrically connected to the second trace124and the third trace126. It is noteworthy that the block structure130is configured to reduce the depth of the via hole for the third trace126in the transistor insulation layer16. For example, when a trace layout in the surrounding area304is designed, the block structure130is pre-arranged at a position for forming the trace-change structure108, such that the depth of the via hole for the third trace126in the transistor insulation layer16can be reduced, in order to further save manufacturing time. Please refer toFIG. 12.FIG. 12is a cross-sectional view of a fourth pixel structure of the present invention. As shown inFIG. 12, a fourth pixel structure110is a TN-type pixel structure with high aperture ratio. Since the electric field in TN-type pixel structure is vertical, an opposite electrode layer111is formed between the second substrate18and the liquid crystal layer22. A transparent conduction layer117is formed on the transistor insulation layer16. A covering insulation layer112covers the transparent conduction layer117. The pixel electrode layer19is formed on the covering insulation layer112and connected to the electrode layer15through a via hole. A spacer PS is formed on the covering insulation layer112for support. In addition, the opposite electrode layer111can be made of the same material as the transparent conduction layer117, but the present invention is not limited thereto. Similar to the third embodiment of the first pixel structure, the distance S3is between a fringe of the orthographic projection of the transparent conduction layer117on the first substrate11and a fringe of the orthographic projection of the region of the semiconductor layer14not covered by the electrode layer15on the first substrate11. The arrangement of the opening of the transparent conduction layer117of the fourth pixel structure110is similar to the arrangement of the opening of the third embodiment of the first pixel structure, but the present invention is not limited thereto. The arrangement of the opening of the transparent conduction layer117of the fourth pixel structure110can be similar to the arrangement of the opening of the first embodiment, the second embodiment or the fourth embodiment of the first pixel structure.

In contrast to the prior art, the pixel structure of the present invention has an opening formed in the transparent conduction layer above the semiconductor layer to reduce the induced current between the transparent conduction layer and the thin-film transistor, in order to further reduce the leakage current of the thin-film transistor when the thin-film transistor is off. Therefore, the pixel structure of the present invention is able to solve problems of uneven brightness of display panel and cross-talk. Moreover, the pixel structure of the present invention is able to adjust the shape and dimension of the opening of the transparent conduction layer according to the aperture ratio and allowable range of induced current. Therefore, the pixel structure of the present invention can meet different design requirements for reducing the induced current.