SEMICONDUCTOR STRUCTURE INCLUDING VERTICAL DIODE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor structure includes a base structure, at least one diode device and a semiconductor device. The base structure has a first base region and a second base region. The at least one diode device includes a first feature formed in the first base region, and a second feature formed over the first feature and having a conductivity type opposite to that of the first feature. The semiconductor device is formed on the second base region.

BACKGROUND

To meet the demand of semiconductor devices with reduced size and improved working performance, new semiconductor structures are developed using new technologies including more advanced fabrication processes.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “on,” “above,” “top,” “bottom,” “bottommost,” “upper,” “uppermost.” “lower,” “lowermost,” “over,” “beneath,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A diode may be included in a semiconductor structure to allow a current passing therethrough in a predetermined direction. In advanced node technology, in which super power rail scheme is adopted, dopant wells may be absent from the semiconductor structure, and p-n junction is formed by directly implanting n-type dopants and p-type dopants at an upper surface of a semiconductor stack of the semiconductor structure (in which the semiconductor stack may include a plurality of semiconductor layers), thereby forming a diode. Lateral diodes may be formed in the semiconductor stack, and current flows laterally (in a direction perpendicular to stacking direction of the semiconductor layers). The industry strives to improve working performance of the diode, and to integrate manufacturing of the diode into manufacturing of other complementary metal oxide semiconductor (CMOS) elements.

The present disclosure is directed to a semiconductor structure, and a method for manufacturing the same. The semiconductor structure includes a vertical diode and a semiconductor device formed on a base structure. Elements of the vertical diode are arranged in a direction normal to a back surface of the base structure (such direction is also referred to as a normal direction). That is, in the vertical diode, a p-type region and an n-type region are faced to each other in the normal direction, such that an electric current is permitted to pass through the vertical diode in the normal direction. The semiconductor device may be a fin-type transistor (FinFET), a nanosheet semiconductor device, such as a gate-all-around-field-effect transistor (GAA FET), a forksheet-based device, a complementary transistors (CFET), but is not limited thereto.

FIGS.1and3show different semiconductor structures in accordance with some embodiments of the present disclosure. Referring toFIG.1, a semiconductor structure100includes a base structure10, a diode device20, and a semiconductor device30.

The base structure10has a first base region11formed with the diode device20, and a second base region12formed with the semiconductor device30. The base structure10has a front surface101, and a back surface102opposite to the front surface101.

The base structure10may be made of elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The material for forming the base structure10may be doped with p-type impurities or n-type impurities, or undoped. In addition, base structure10may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. Other suitable materials for the base structure10are within the contemplated scope of disclosure. In some embodiments, the base structure10is made of silicon (Si) and has an intrinsic conductivity type.

The diode device20includes a first feature21formed in the first base region11, and a second feature22formed over the first feature21. In some embodiments, the second feature22is disposed on the first feature21over the front surface101, such that the first and second features21,22face to each other along a Z direction normal to the back surface102of the base structure10.

In some embodiments, the second feature22is formed on the first base region11in a semiconductor stack40. The semiconductor stack40has an upper surface401, and a lower surface402opposite to the upper surface401and connected to the front surface101of the base structure10at the first base region11. The first feature21extends from the back surface102at the first base region11toward the second feature22, and the second feature22extends from the upper surface401toward the first feature21.

The first and second features21,22have opposite conductivity type. As such, the first and second features21,22having different polarities face to each other along the Z direction, and an electric current is permitted to pass through the diode device20in the Z direction. The diode device20may be regarded as a vertical diode. In some embodiments, the first feature21has a p-type conductivity, and the second feature22has an n-type conductivity, or vice versa in other embodiments. In such case, the first feature21having the p-type conductivity serves as a p-type region or an anode of the diode device20, and the second feature22having the n-type conductivity serves as an n-type region or a cathode of the diode device20. An electrical current is permitted to flow form the anode (e.g., the p-type first feature21) to the cathode (e.g., the n-type second feature22) of the diode device20.

In some embodiments, the first feature21may have a p-type conductivity and may include a p-type dopant such as boron, or other suitable materials, or combinations thereof, with a dopant concentration ranging from about 1E19 atoms/cm3to about 1E21 atoms/cm3. The first feature21may have a thickness (measured along the Z direction) ranging from about 30 nm to about 50 nm. The second feature22may have an n-type conductivity and may include an n-type dopant such as phosphorous, nitrogen, arsenic, antimony, other suitable materials, or combinations thereof, with a dopant concentration ranging from about 1E19 atoms/cm3to about 1E21 atoms/cm3. The second feature22may have a thickness (measured along the Z direction) ranging from about 40 nm to about 70 nm. Other suitable dopants, dopant concentration, or thickness for each of the first and second features21,22are within the contemplated scope of disclosure.

The semiconductor stack40includes a plurality of first semiconductor layers41, and a plurality of second semiconductor layers42disposed to alternate with the first semiconductor layers41along the Z direction. A number of the first semiconductor layers41and a number of the second semiconductor layers42are determined according to practical requirements. In the exemplary example shown inFIG.1, the number of the first semiconductor layers41and the number of the second semiconductor layers42are both three. Materials suitable for making the first and second semiconductor layers41,42are similar to those for making the base structure10, and the first semiconductor layers41are made of a material different from that of the second semiconductor layers42. In some embodiments, the first semiconductor layers41are made of silicon germanium (SiGe), and the second semiconductor layers42are made of silicon (Si), but are not limited thereto. Other suitable materials for the first and second semiconductor layers41,42are within the contemplated scope of disclosure.

In the case that the first semiconductor layers41are made of SiGe and the second semiconductor layers42are made of Si, and that the p-type region and the n-type region (not shown) are both formed in the semiconductor stack40and are spaced apart from each other by a portion of the semiconductor stack40in an X direction transverse (e.g., perpendicular) to the Z direction, the lattice mismatch defects between SiGe and Si may cause an electric current flowing through the portion of the semiconductor stack40along interfaces between SiGe and Si undesirably deviates from an ideal value. In the present disclosure, as aforementioned, the first and second features21,22having different polarities face to each other along the Z direction, which is along a disposal direction of the first and second semiconductor layers41,42, and which is, perpendicular to interfaces between the first and second semiconductor layers41,42. An electric current passing through the diode device20flows in a manner perpendicular to the interfaces between the first and second semiconductor layers41,42. Such electric current is found to be less impacted by the lattice mismatch defects between Si and SiGe, and results in an improved ideal factor. That is, charge carriers in the electric current travelling in the semiconductor stack40may be less likely to be trapped by the defects, thereby prolonging lifetime of the charge carriers and obtaining a higher forward current output, and the diode device20may behave in a manner rather similarly to an ideal diode. In some embodiments, the second feature22is formed covering as much interfaces between the first and second semiconductor layer41,42(e.g., along the Z direction) as possible, so as to case impacts due to the lattice mismatch defects.

In addition, in the case that the p-type region and the n-type region formed in the semiconductor stack40are spaced apart from each other, the p-type and n-type regions are usually spaced apart by a relatively large distance (e.g. about or greater than 100 nm) in the X direction due to constrains of process flow and/or apparatus used in manufacturing of the semiconductor structure. In the present disclosure, by arranging the first and second features21,22of the diode device20vertically, the aforementioned constrains are resolved, which is beneficial to reduce size of the semiconductor structure100(e.g., reducing area of the diode device20on the base structure10). Besides, in the present disclosure, it is not necessary for the first and second features21,22to be spaced apart from each other by a certain distance. In some embodiments, the first and second features21,22are in contact with each other, and the diode device20is a PN diode.

In some embodiments, the diode device20further includes a third feature23disposed between the first and second features21,22, such that the first and second features21,22are spaced apart from each other by the third feature23. A portion of the third feature23is formed in the first base region11, and a portion of the third feature23is formed in the semiconductor stack40. The third feature23may have a dopant concentration lower than that of each of the first and second features21,22. In some embodiments, the third feature23has an intrinsic conductivity type, and the diode device20is a PIN diode. The third feature23may have a thickness (measured along the Z direction) approximately greater than 0 and not greater than about 100 nm.

As shown inFIG.1, in some embodiments, the semiconductor structure100may have two the aforementioned diode devices20, or more in some other embodiments, but are not limited thereto.

The first features21of the two diode devices20are formed in the first base region11, and are spaced apart from each other in the X direction by a first in-between region15. The second features22of the two diode devices20are formed in the semiconductor stack40, and are spaced apart from each other in the X direction by a second in-between region43which is located above the first in-between region. The X direction is transverse (e.g., perpendicular) to the Z direction.

The semiconductor structure100may further include a back dielectric layer90B formed on the back surface102of the base structure10, and a front dielectric layer90F formed on the upper surface401of the semiconductor stack40. The back and front dielectric layers90B,90F may include a dielectric material such as silicon oxide, silicon nitride, or the like, or combinations thereof, but are not limited thereto. Other materials suitable for forming the dielectric layers90B,90F are within the contemplated scope of the present disclosure.

The semiconductor structure100may further include two back side contacts81and two front side contacts82. The back side contacts81are formed in the back dielectric layer90B on the first base region11, and are respectively connected to the first features21of the two diode devices20. The front side contacts82are formed in the front dielectric layer90F and are respectively connected to the second features22of the two diode devices20. The back side contacts81and the front side contacts82cooperatively permit the diode devices20to be connected to an external power source from back side, and front side of the semiconductor structure100, respectively. In some embodiments, the back side contacts81and the front side contacts82may each include for example, but not limited to, tungsten (W), aluminum (Al), ruthenium (Ru), cobalt (Co), copper (Cu), palladium (Pd), nickel (Ni), platinum (Pt), a low resistivity metal, or the like, or combinations thereof.

In some embodiments, the semiconductor structure100further includes a dummy gate61in the front dielectric layer90F on the upper surface401over the first in-between region15and the second in-between region43. The dummy gate61elongates along a Y direction transverse (e.g., perpendicular) to both the X direction and the Z direction. In some embodiments, the dummy gate61does not necessarily serve any functional purpose in the diode devices20and is not connected to an external power source.

In some embodiments, the semiconductor stack40is elongated in the X direction. Referring toFIG.2, in some embodiments, the base structure10has a substrate13, and a plurality of fins14that are formed on the substrate13. In some embodiments, a plurality of isolation sections (not shown, which may include silicon-based dielectric material(s) such as silicon oxide, silicon nitride, or other suitable materials) may be formed on the base structure100to isolate the fins14from each other. The fins14are each elongated in the X direction and are spaced apart from each other in the Y direction. In some embodiments, the semiconductor device30and the diode devices20may be located on the same fin14(i.e., the semiconductor device30and the diode devices20are displaced from each other in the X direction); while in other embodiments, the semiconductor device30and the diode devices20may be located on different fins14(i.e., the semiconductor device30and the diode devices20are displaced from each other in the Y direction).

The semiconductor device30is formed on the second base region12of the base structure10. Exemplarily, the semiconductor device30shown inFIG.1is a GAA device, but is not limited thereto. Other suitable devices serving as the semiconductor device30are within the contemplated scope of the present disclosure.

The semiconductor device30includes two source/drain features31spaced apart from each other in the X direction and respectively disposed in recesses (not shown) formed in the fin14at the second base region12. Please note that the source/drain features31may refer to a source or a drain, individually or collectively dependent upon the context. The source/drain features31may be made of a single crystalline silicon, a polycrystalline silicon, a single crystalline silicon germanium, a polycrystalline silicon germanium, or other suitable materials, and may be doped with n-type dopant(s) or p-type dopants. Other suitable materials for the source/drain features31are within the contemplated scope of the present disclosure.

In some embodiments, each of the source/drain features31may include multiple epitaxy layers (e.g., epitaxy layers311,312) that are formed by an epitaxy growth process, and that are in situ doped with different dopant concentrations. The epitaxy layer(s) located closer to the base structure10may have a relatively lower dopant concentration, while the epitaxy layer(s) located away from the base structure10may have a relatively higher dopant concentration. In some embodiments, as shown inFIG.1, each of the source/drain features31has an intrinsic epitaxy layer (L0, e.g., the epitaxy layer311) disposed on the base structure10, and an in situ doped epitaxy layer (e.g., the epitaxy layer312including L1, L2, L3. . . ) disposed on the intrinsic epitaxy layer311opposite to the base structure10. In some embodiments, the in situ doped epitaxy layer312of each of the source/drain features31may have a conductivity type same as or different from that of the second features22of the diode devices20. Suitable dopants for the in situ doped epitaxy layer312are similar to those for the first features21and the second features22, and details thereof are omitted for the sake of brevity. In this case, since the second features22of the diode devices20can be formed on the first base region11from the semiconductor stack40, and since the semiconductor devices30can be formed on the second base region12from the semiconductor stack40(seeFIGS.1and10), preparation of the diode devices20shown inFIG.1may be readily integrated into preparation of the semiconductor devices30, or any other CMOS devices.

The semiconductor device30includes active channel features32that are spaced apart from each other in the Z direction and that are made of a material same as that of the second semiconductor layers42of the semiconductor stack40(i.e., Si), or materials for making the base structure10. Other suitable materials for the active channel features32are within the contemplated scope of disclosure. Each of the active channel features32interconnects the two source/drains features31.

The semiconductor device30includes an active gate feature33formed around the active channel features32. In some embodiments, the active gate feature33may include an upper gate331and a plurality of lower gates332, each of which includes a gate dielectric and a gate electrode (not shown). The upper gate331is formed over the active channel features32. Each of the lower gates332is disposed around a respective one of the active channel features32. The gate electrode may be configured as a multi-layered structure including (i) at least one work function metal (which is provided for adjusting threshold voltage of an n-FET or a p-FET), and, (ii) an electrically conductive material having a low resistance (which is provided for reducing electrical resistance of the gate electrode), other suitable materials, or combinations thereof. In some embodiments, the work function metal of the gate electrode for forming an n-FET may be different from that for forming a p-FET so as to permit the n-FET and the p-FET to have different threshold voltages. Other methods suitable for adjusting the threshold voltages are within the contemplated scope of the present disclosure. In some embodiments, the gate electrode may include a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), or ruthenium (Ru)), a metal-containing nitrides (e.g., titanium nitride (TiN), or tantalum nitride (TaN)), a metal-containing silicide (e.g., nickel silicide (NiSi)), a metal-containing carbide (e.g., tantalum carbide (TaC)), or combinations thereof. The gate dielectric is disposed to entirely separate the gate electrode from the active channel features32, and may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or combinations thereof. Other suitable materials for the gate electrode and the gate dielectric are within the contemplated scope of disclosure. In some embodiments, the dummy gate61may be formed together with the upper gate331of the active gate feature33, and thus may be similar to that of the upper gate331in terms of configurations and materials. In some other embodiments, two gate spacers (not shown) are formed at two opposite sides of each of the dummy gate61and the upper gate331. Each of the gate spacers may be a single or multiple layers which may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Other suitable materials for the gate spacers are within the contemplated scope of disclosure.

The semiconductor device30further includes a plurality of inner spacers34that are disposed to separate the two sources/drain features31from the active gate features33. The inner spacers34may be made of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, other suitable materials, or combinations thereof. Other suitable materials for the inner spacers34are within the contemplated scope of disclosure.

The semiconductor device30further includes a plurality of source/drain contacts35that are respectively connected to the source/drain features31. Suitable materials for forming the source/drain contacts35are similar to those for forming the back side contacts81and the front side contacts82, and thus details thereof are omitted for the sake of brevity.

The front dielectric layer90F is also configured to surround the upper gate331and the source/drain contacts35at the second base region12. The back dielectric layer90B also covers the back surface102at the second base region12.

In the diode devices20of the semiconductor structure100, the second features22are formed in the semiconductor stack40, through for example, but not limited to, ex-situ doping, such as performing ion implantation to the semiconductor stack40over the first base region11. The method for preparing the diode devices20will be described later inFIGS.4to8.

Referring toFIG.3, in other embodiments, the second features22may also be formed in an epitaxy layer through for example, but not limited to, in situ doping, during an epitaxy growth process. The semiconductor structure200will be described in the following paragraphs, and the method for preparing the same will be discussed inFIGS.9to14.

In the semiconductor structure200shown inFIG.3, the second base region12and the semiconductor device30are similar to those described in the semiconductor structure100with reference toFIG.1, and thus details thereof are omitted for the sake of brevity.

The differences between the two semiconductor structures100,200are that, in the semiconductor structure200, a plurality of epitaxy units (that are formed from the semiconductor stack40, seeFIGS.9to14) are formed on the first base region11, and the second features22are respectively formed in the epitaxy units (seeFIG.3), instead of in the semiconductor stack40(seeFIG.1).

The epitaxy units are similar to the source/drain features31of the semiconductor devices30in terms of materials and configurations, and the details thereof are omitted for the sake of brevity. In some embodiments, each of the epitaxy units includes an intrinsic epitaxy layer (L0, e.g., an epitaxy layer201, which is similar to the epitaxy layer311of each of the source/drain features31) disposed on the base structure10, and an in situ doped epitaxy layer (e.g., an epitaxy layer202including L1, L2, L3, which is similar to the epitaxy layer312of each of the source/drain features31) disposed on the intrinsic epitaxy layer201opposite to the base structure10.

Each of the epitaxy units, together with a portion of the base structure10thereunder, form a respective one of the diode devices20. To be specific, for each of the epitaxy unit, (i) a portion of the epitaxy layer201located proximate to the back surface102, and the portion of the base structure10underneath are subjected to an ion implantation process at the back surface102, thereby forming the first feature21of the respective diode device20; (ii) a remaining portion of the epitaxy layer201that is not subjected to the ion implantation process serves as the third feature23of the respective diode device20; and (iii) the epitaxy layer202serves as the second feature22of the respective diode device20. As such, the respective one of the diode devices20is formed as a vertical diode, in which an electric current passing therethrough flows in the Z direction. In some embodiments, the epitaxy layers201,202for each of the epitaxy units are respectively formed together with the epitaxy layers311,312for each of the source/drain features31, and thus, the configuration and the conductivity type of the epitaxy units are similar to or the same as those of the source/drain features31. Other details of the diode devices20, such as suitable dopants, dopant concentrations, and thickness of the first, second and third features21,22,23are similar to those as described with reference toFIG.1, and thus are omitted for the sake of brevity.

The two diode devices20are spaced apart from each other in the X direction. The semiconductor structure200further includes a plurality of dummy channel features50, a dummy gate feature60and a plurality of first inner spacers70. The dummy channel features50are spaced apart from each other in the Z direction, each of which interconnects the second features22of the two diode devices20. The dummy gate feature60is formed around the dummy channel features50. In some embodiments, the dummy gate feature60includes an upper gate61(equivalent to the dummy gate61described inFIG.1) and a plurality of lower gates62, each of which includes a gate dielectric and a gate electrode (not shown). The upper gate61is formed over the dummy channel features50. Each of the lower gates62is disposed around a respective one of the dummy channel features50. The first inner spacers70are disposed to separate the second features22of the two diode devices20from the dummy gate feature60. The dummy channel features50, the dummy gate feature60, and the first inner spacers70are formed respectively together with and thus have configurations respectively similar to the active channel features32, the active gate feature33and second inner spacers34of the semiconductor device30(equivalent to the inner spacers34of the semiconductor device30discussed inFIG.1), and thus details thereof are omitted for the sake of brevity. Since the dummy gate feature60does not necessarily serve any functional purpose in the diode devices20and is not connected to an external power source, the second features22of the diode devices20will not be in electrical connection through the dummy channel features50. Each of the dummy channel features50, the dummy gate feature60, and the first inner spacers70are made of a material similar to that of the active channel features32, the active gate feature33, and the second inner spacers34, and thus details thereof are omitted for the sake of brevity.

Similar to the semiconductor structure100, the semiconductor structure200also includes the back and front dielectric layers90B,90F, the back side contacts81and the front side contacts82, and details thereof are omitted for the sake of brevity. Since the elements201,202,50,60,70at the first base region11can be respectively formed together with the elements311,312,32,33,34at the second base region12, preparation of the diode devices20shown inFIG.3may be readily integrated into preparation of the semiconductor devices30, or any other CMOS devices.

FIG.4is a flow diagram illustrating a method300for manufacturing the diode devices20of the semiconductor structure100shown inFIG.1in accordance with some embodiments of the present disclosure.FIGS.5to8illustrate schematic views of intermediate stages of the method300in accordance with some embodiments. Some repeating structures are omitted inFIGS.5to8for the sake of brevity. Additional steps can be provided before, after or during the method, and some of the steps described herein may be replaced by other steps or be eliminated.

FIG.5is a cross-sectional view taken along line A-A ofFIG.2in accordance with some embodiments. Referring toFIG.4, and the example illustrated inFIG.5, the method begins with step301, where the semiconductor stack40is formed on the base structure10. The lower surface402of the semiconductor stack40is connected to the front surface101of the base structure10. For the base structure10, the first base region11is configured to be formed with the diode devices20, and the second base region12(not shown inFIGS.5to8) is configured to be formed with the semiconductor device30(not shown inFIGS.5to8). In some embodiments, the semiconductor stack40and the base structure10may have an intrinsic conductivity type to serve as a basis for forming the intrinsic third features23in subsequent step. In some embodiments, step301is performed by (i) sequentially depositing material layers for forming the first and second first and second semiconductor layers41,42on a starting substrate (not shown) using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable techniques, and (ii) patterning the material layers and the starting substrate using one or more photolithography processes which may include, for example, coating a photoresist, exposing the photoresist through a photomask, developing the photoresist, etching the material layers and/or the starting substrate exposed from the developed photoresist using dry etching, wet etching, other suitable processes, combinations thereof, stripping or ashing the developed photoresist, and/or other suitable processes. Thereafter, the starting substrate is formed into the substrate13and the fins14shown inFIG.2, and the material layers are formed into the semiconductor stack40on each of the fins14.

Referring toFIG.4and the example illustrated inFIG.6, the method proceeds to step302, where a sacrificial gate feature61′ is formed on the upper surface401of the semiconductor stack40. In some embodiments, the sacrificial gate feature61′ may include a sacrificial gate electrode (not shown) which may include polysilicon and a sacrificial gate dielectric which may include a silicon-based dielectric material. Other suitable materials for the sacrificial gate feature61′ are within the contemplated scope of disclosure. The sacrificial gate feature61′ is to be replaced by the dummy gate61(seeFIG.1). In some embodiments, in step302, after forming the sacrificial gate feature61′, the gate spacers (not shown) are formed at two opposite sides of the sacrificial gate feature61′ in the X direction. In some embodiments, step302includes (i) depositing material layers for forming the sacrificial gate feature61′ using CVD, ALD or other suitable techniques, (ii) patterning the material layers using one or more photolithography processes (which may include, for example, coating a photoresist, exposing the photoresist through a photomask, developing the photoresist, etching the material layers forming the sacrificial gate feature61′ exposed from the developed photoresist using dry etching, wet etching, other suitable processes, combinations thereof, stripping or ashing the developed photoresist, and/or other suitable processes), and (iii) forming the gate spacers (which may include depositing material layer(s) for forming the gate spacers, followed by anisotropic etching).

Referring toFIG.4and the example illustrated inFIG.7, the method proceeds to step303where upper features22(equivalent to the second features22described inFIG.1) are formed by performing a front-side ion implantation process at the upper surface401exposed from the sacrificial gate feature61′. In the front-side ion implantation process, first dopants are implanted into the semiconductor stack40through the upper surface401to form the two upper features22, each of which extends from the upper surface401toward the base structure10. The first dopants are responsible for the conductivity type of the upper features22(i.e. second features22).

Parameters for the front-side ion implantation process may be adjusted to obtain the desired upper features22. For instance, in some embodiments, the upper features22are formed as thick as possible (along the Z direction) by allowing the first dopants penetrating into the semiconductor stack40, such that the electric current passing through the diode devices20formed thereby is less affected by the lattice mismatch defects between the first and second semiconductor layers41,42.

Referring toFIG.4and the example illustrated inFIG.8, the method proceeds to step304, where lower features21(equivalent to the first features21described inFIG.1) are formed by performing a back-side ion implantation process at the back surface102of the first base region11in position corresponding to the upper features22.

To obtain the structure shown inFIG.8, the following sub-steps are performed: (i) forming the front dielectric layer90F over the upper surface401surrounding the sacrificial gate feature61′ (which may include depositing a material layer for forming the front dielectric layer90F over the upper surface401to cover the sacrificial gate feature61′ using CVD, ALD or other suitable technique, followed by removing an upper portion of the material layer for forming the front dielectric layer90F to expose the sacrificial gate feature61′ using chemical mechanical polishing (CMP) or other suitable techniques); (ii) replacing the sacrificial gate feature61′ with the dummy gate61(which may include removing the sacrificial gate feature61′ using a suitable etching process, depositing material layers for forming the dummy gate61using CVD, ALD or other suitable techniques, and removing an upper portion of material layers for forming the dummy gate61using CMP or other suitable techniques; (iii) forming the front side contacts82in the front dielectric layer90F so as to be respectively connected to the second features22(which may include patterning the front dielectric layer90F using one or more suitable photolithography processes to form openings to expose the second features22, filling the openings with materials for forming the front side contacts82using CVD. ALD or other suitable techniques, and removing excess materials using CMP or other suitable techniques to expose the front dielectric layer90F); and (iv) performing the back-side ion implantation process at the back surface102of the base structure10. In some embodiments, the gate spacers (not shown) formed in step302are located at two opposite sides of the dummy gate61in the X direction.

In sub-step (iv), second dopants are implanted into the first base region11through the back surface102to form the lower features21. The second dopants are responsible for the conductivity type of the lower features21(i.e., the first features21). Each of the lower features21extends from the back surface102toward a respective one of the upper features22. In some embodiments, the second dopants may be further implanted into the semiconductor stack40, although not shown inFIG.8.

Parameters for the back-side ion implantation process may be adjusted according to practical needs. Please note that the first dopants used in the front-side ion implantation process should be in opposite conductivity with the second dopants used in the back-side ion implantation process, so as to form the lower and upper features21,22with opposite conductivity types.

In some embodiments, for each of the diode devices20, a portion of the base structure10and a portion of the semiconductor stack40that are not subjected to the front-side and back-side ion implantation processes and that are located between the lower and upper features21,22serve as the third features23. In such case, the diode devices20are known as PIN diodes.

In other embodiments, for each of the diode devices20, the lower and upper features21,22formed are in contact with each other, and the third feature23is omitted. In such case, the diode devices20are known as PN diodes.

Referring toFIG.4and the example illustrated inFIG.1, the method proceeds to step305, where the back side contacts81are formed. Step305includes the following sub-steps: (i) forming the back dielectric layer90B over the back surface102(seeFIG.8) using CVD, ALD or other suitable techniques, (ii) patterning the back dielectric layer90B using one or more suitable photolithography processes to form openings (not shown) that respectively expose the lower features21, and (iii) forming the back side contacts81by filling material(s) for forming respectively in the openings using CVD, ALD or other suitable techniques, followed by removing an excess of the material(s) using CMP or other suitable techniques to expose the back dielectric layer90B, so as to obtain the structure shown in left side ofFIG.1.

In some other embodiments, for the semiconductor structure200, where elements at the first and second base regions11,12having similar configurations can be formed together.FIG.9is a flow diagram illustrating a method500for manufacturing the semiconductor structure200shown inFIG.3in accordance with some embodiments of the present disclosure. In method500, preparation of the diode devices20is integrated into preparation of the semiconductor device30.FIGS.10to14illustrate schematic views of intermediate stages of the method500in accordance with some embodiments. Some repeating structures are omitted inFIGS.10to14for the sake of brevity. Additional steps can be provided before, after or during the method, and some of the steps described herein may be replaced by other steps or be eliminated.

Referring toFIG.9and the example illustrated inFIG.10, the method begins with step501, where the semiconductor stack40is formed on each of the first and second base regions11,12of the base structure10. Step501is similar to step301described with reference toFIG.5, and details thereof are omitted for the sake of brevity.

Referring toFIG.9and the example illustrated inFIG.11, the method proceeds to step502, where a first sacrificial gate feature61′ is formed on the semiconductor stack40at the first base region11, and a second sacrificial gate feature331′ is formed on the semiconductor stack40at the second base region12. The first and second sacrificial gate features61′,331′ are each formed in a manner similar to that of the sacrificial gate feature61′ described with reference toFIG.6, and may be formed simultaneously, and details thereof are omitted for the sake of brevity.

Referring toFIG.9and the example illustrated inFIG.12, the method proceeds to step503, where two first recesses20′ are formed in the semiconductor stack40and the base structure10at the first base region11, and two second recesses31′ are formed in the semiconductor stack40and the base structure10at the second base region12. The first and second recesses20′,31′ may be formed simultaneously by etching the semiconductor stack40at the first base region11exposed from the first sacrificial gate features61′ and etching the semiconductor stack40at the second base region12exposed from the second sacrificial gate features311′ (seeFIG.11) using any suitable processes, such as a dry etching process, a wet etching process, or a combination thereof, but are not limited thereto.

After step503, at the first base region11, the first semiconductor layers41(seeFIG.11) are formed into sacrificial semiconductor layers411(which are to be formed into the lower gates62and the first inner spacers70as shown inFIG.3), and the second semiconductor layers42are formed into the dummy channel features50. At the second base region12, the first semiconductor layers41(seeFIG.11) are formed into sacrificial semiconductor layers411(which are to be formed into the lower gates332and the second inner spacers34as shown inFIG.3), and the second semiconductor layers42are formed into the active channel features32. The sacrificial semiconductor layers411at the first base region11and the sacrificial semiconductor layers411at the second base region12are similar to each other in terms of configurations and materials, while the dummy channel features50at the first base region11and the active channel features32at the second base region12are similar to each other in terms of configurations and materials.

Referring toFIG.9and the example illustrated inFIG.13, the method proceeds to step504, where the epitaxy units (each including the epitaxy layers201,202) and the first inner spacers70are formed at the first base region11, and the source/drain features31and the second inner spacers34are formed at the second base region12.

Step504may include the following sub-steps: (i) simultaneously removing opposite ends of each of the sacrificial semiconductor layers411shown inFIG.12at both the first and second base regions11,12(the remaining sacrificial semiconductor layers shown inFIG.13are denoted as411′); (ii) simultaneously forming the first inner spacers70respectively at the opposite ends of the remaining sacrificial semiconductor layers411′ at the first base region11, and forming the second inner spacers34respectively at the opposite ends of the remaining sacrificial semiconductor layers411at the second base region12; and (iii) simultaneously forming the epitaxy units respectively in the first recesses20′, and the source/drain features31respectively in the second recesses31′. In some embodiments, in step504, sub-step (i) may involve one or more selective etching processes (e.g., dry etching, wet etching, or a combination thereof, sub-step (ii) may involve one or more deposition processes (e.g., CVD, ALD or other suitable techniques) and one or more etching processes (e.g., an anisotropic etching process or other suitable processes), and sub-step (iii) may involve CVD, molecular-beam epitaxy (MBE), an epitaxial deposition/partial etch process, such as a cyclic deposition-etch (CDE) process and/or a selective epitaxial growth (SEG) process. In sub-step (iii) of step504, the epitaxy units and the source/drain features31are formed simultaneously, and thus have the same conductivity type.

In sub-step (iii), any suitable epitaxy growth process may be adopted to simultaneously form the epitaxy units and the source/drain features31. The intrinsic epitaxy layers (the epitaxy layers201of the epitaxy units and the epitaxy layers311of the source/drain features31) and the in situ doped epitaxy layers (the epitaxy layers202of the epitaxy units and the epitaxy layers312of the source/drain features31) are sequentially formed.

Referring toFIG.9and the example illustrated inFIG.14, the method proceeds to step505, where lower features21(equivalent to the first features21described inFIG.3) are formed by performing a back-side ion implantation process (which may be performed in a way similar to that described with reference toFIG.8) at the back surface102of the first base region11in position corresponding to the epitaxy layers202of the epitaxy units.

To obtain the structure shown inFIG.14, the following sub-steps are performed: (i) forming the front dielectric layer90F on the epitaxy units and the source/drain features31surrounding the first and second sacrificial gate features61′,331′ in a manner similar to sub-step (i) of step304; (ii) simultaneously replacing the first sacrificial gate feature61′ (see alsoFIG.13) with the dummy gate feature60, and replacing the second sacrificial gate feature331′ with the active gate feature331in a manner similar to sub-step (ii) of step304; (iii) simultaneously forming the front side contacts82and the source/drain contacts35in the front dielectric layer90F in a manner similar to sub-step (iii) of step304such that the first side contacts82are respectively connected to the epitaxy layers202and the source/drain contacts35are respectively connected to the epitaxy layers312; and (iv) performing an ion implantation process on the back surface102of the first base region11.

In sub-step (iv), dopants which are responsible for the conductivity type of the lower features21are implanted into the first base region11and into the epitaxy layers201through the back surface102to form the lower features21. Each of the lower features21extends from the back surface102toward a respective one of the epitaxy layers202. Parameters for the ion implantation process in sub-step (iv) may be adjusted according to practical needs. Please note that the dopants used in the ion implantation process should be in opposite conductivity with that of the dopants used in forming the epitaxy layers202. As such, the lower features21may serve as the first features21described inFIG.3, and the epitaxy layers202may serve as the second features22inFIG.3. Each of the lower features21, a portion of a corresponding one of the epitaxy layers201that is not subjected to the ion implantation process, and a corresponding one of the epitaxy layers202cooperatively form the vertical PIN diode device20.

In some embodiments, in sub-step (iii) of step504, the intrinsic epitaxy layers may be omitted, i.e., the in situ doped epitaxy layers are directly formed on the base structure10, and/or in sub-step (iv) of step505, the lower features21are formed to be in direct contact with the epitaxy layers202so as to form the diode devices20as vertical PN diodes.

Referring toFIG.9and the example illustrated inFIG.3, the method proceeds to step506, where the back side contacts81are formed. Since step506includes the following sub-steps: (i) forming the back dielectric layer90B over the back surface102of the base structure10(seeFIG.14) in a manner similar to sub-step (i) of step305, (ii) patterning the back dielectric layer90B to form openings (not shown) in a manner similar to sub-step (ii) of step305such that the lower features21are exposed from the openings, and (iii) forming the back side contacts81in a manner similar to sub-step (iii) of step305, so as to obtain the semiconductor structure200shown inFIG.3.

In addition, a process for forming the semiconductor device30shown in the right side ofFIG.1is similar to that for forming the semiconductor device30shown inFIG.3, and thus, details thereof are omitted for sake of brevity. In some embodiments, the semiconductor structure100shown inFIG.1may be made using method500but the recesses20′, the first inner spacers70and the epitaxy units are not formed at the first base region11in steps503and504, instead, before or after steps503and504, the upper features22are formed in the semiconductor stack40in a manner similar to step303of method300.

The embodiments of the present disclosure have the following advantageous features. By forming the diode devices20as vertical diodes in the semiconductor stack40having the alternately arranged semiconductor layers41,42, the electric current passing therethrough in the normal direction (i.e., the direction normal to the back surface102of the base structure10) is less likely to be impacted by the lattice mismatch defects between the semiconductor layers41,42, and thus the diode devices20may behave like ideal diodes. In addition, the vertical configuration of the diode devices20is beneficial in reducing the size of the semiconductor structure of the present disclosure. Moreover, since various elements on the first base region11and the second base region12are similar to each other, preparation of the diode devices20at the first base region11may be readily integrated into preparation of the semiconductor devices30at the second base region12, thereby simplifying the manufacturing process of such semiconductor structure.

In accordance with some embodiments of the present disclosure, a semiconductor structure includes a base structure, at least one diode device and a semiconductor device. The base structure has a first base region and a second base region. The at least one diode device includes a first feature formed in the first base region, and a second feature formed over the first feature and having a conductivity type opposite to that of the first feature. The semiconductor device is formed on the second base region.

In accordance with some embodiments of the present disclosure, the semiconductor structure further includes a semiconductor stack formed on the first base region. The semiconductor stack includes first semiconductor layers and second semiconductor layers which are disposed to alternate with the first semiconductor layers, and which are made of a material different from that of the first semiconductor layers. The second feature is formed in the semiconductor stack.

In accordance with some embodiments of the present disclosure, the base structure has a front surface and a back surface opposite to the front surface. The semiconductor stack has an upper surface and a lower surface which is opposite to the upper surface and which is connected to the front surface of the base structure at the first base region. The semiconductor device is formed on the front surface at the second base region. The first feature extends from the back surface at the first base region toward the second feature. The second feature extends from the upper surface toward the first feature.

In accordance with some embodiments of the present disclosure, the at least one diode device further includes a third feature that includes a portion of the first base region and a portion of the semiconductor stack and that is disposed between the first feature and the second feature. The third feature has a dopant concentration lower than that of each of the first feature and the second feature.

In accordance with some embodiments of the present disclosure, the third feature has an intrinsic conductivity type.

In accordance with some embodiments of the present disclosure, the at least one diode device is a PIN diode.

In accordance with some embodiments of the present disclosure, the third feature has a thickness greater than 0 nm and not greater than 100 nm.

In accordance with some embodiments of the present disclosure, the at least one diode device includes two diode devices. The first features of the two diode devices are formed in the first base region and spaced apart from each other in an X direction by a first in-between region. The second features of the two diode devices are formed in the semiconductor stack and spaced apart from each other in the X direction by a second in-between region which is located above the first in-between region. The first feature and the second feature of each of the two diode devices are displaced from each other in a Z direction transverse to the X direction.

In accordance with some embodiments of the present disclosure, the semiconductor structure further includes a dummy gate formed over the first in-between region and the second in-between region, and elongated in a Y direction transverse to both the X direction and the Z direction.

In accordance with some embodiments of the present disclosure, the at least one diode device includes two diode devices. The first features of the two diode devices are formed in the first base region and spaced apart from each other in an X direction. The first feature and the second feature of each of the two diode devices are displaced from each other by the third feature in a Z direction transverse to the X direction. The semiconductor structure further includes dummy channel features and a dummy gate feature. The dummy channel features are spaced apart from each other in the Z direction. Each of the dummy channel features interconnects the second features of the two diode devices. The dummy gate feature is formed around the dummy channel features.

In accordance with some embodiments of the present disclosure, the semiconductor device includes two source/drain features, active channel features and an active gate feature. The two source/drain features are spaced apart from each other in the X direction. The active channel features are spaced apart from each other in the Z direction. Each of the active channel features interconnects the two source/drain features. The active gate feature is formed around the active channel features.

In accordance with some embodiments of the present disclosure, the semiconductor structure further includes a plurality of first inner spacers disposed to separate the second features of the two diode devices from the dummy gate feature. The semiconductor device further includes a plurality of second inner spacers disposed to separate the two source/drain features from the active gate features.

In accordance with some embodiments of the present disclosure, the semiconductor structure further includes a back side contact disposed on the first base region and connected to the first feature, and a front side contact connected to the second feature.

In accordance with some embodiments of the present disclosure, a semiconductor structure includes a base structure, and a vertical diode including a first feature, a second feature, and a third feature. The first feature is formed in the base structure. The second feature is disposed on the first feature over a front surface of the base structure such that the first feature and the second feature face each other along a Z direction normal to a back surface of the base structure opposite to the front surface. The third feature is formed between the first feature and the second feature along the Z direction. The first feature has a conductivity type opposite to that of the second feature, and the third feature has a dopant concentration lower than that of each of the first feature and the second feature.

In accordance with some embodiments of the present disclosure, the second feature is formed in a semiconductor stack disposed on the base structure. The third feature includes a portion of the first base region and a portion of the semiconductor stack.

In accordance with some embodiments of the present disclosure, the semiconductor stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are disposed to alternate with the first semiconductor layers, and that are made of a material different from that of the first semiconductor layers.

In accordance with some embodiments of the present disclosure, the base structure has a first base region and a second base region. The vertical diode is disposed at the first base region. The semiconductor structure further includes a semiconductor device disposed on the second base region.

In accordance with some embodiments of the present disclosure, the semiconductor structure further includes an epitaxy unit disposed on the first base region. The epitaxy unit includes a lower epitaxy layer and an upper epitaxy layer formed on the lower epitaxy layer. The upper epitaxy layer serves as the second feature. The first feature is formed in the first base region and extends into a lower part of the lower epitaxy layer such that an upper part of the lower epitaxy layer serves as the third feature. The semiconductor device includes a source/drain feature having an upper epitaxy layer and a lower epitaxy layer which are made of materials same as those, respectively, of the upper epitaxy layer and the upper part of the lower epitaxy layer of the epitaxy unit.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes: forming a base structure having a first base region and a second base region; forming a diode device on the first base region, the diode device being formed with a first feature formed in the first base region, a second feature formed over the first feature, and a third feature disposed between the first feature and the second feature, the first feature having a conductivity type opposite to that of the second feature, the third feature having a dopant concentration lower than that of each of the first feature and the second feature; and forming a semiconductor device on the second base region, the semiconductor device including source/drain features having a conductivity type same as that of the second feature.

In accordance with some embodiments of the present disclosure, the method further includes forming an epitaxy unit on the first base region, the epitaxy unit including a lower epitaxy layer and an upper epitaxy layer formed on the lower epitaxy layer, the upper epitaxy layer serving as the second feature; the source/drain features and the epitaxy unit are formed simultaneously; and the first feature is formed in the first base region and extends into a lower part of the lower epitaxy layer such that an upper part of the lower epitaxy layer serves as the third feature.