Limiting skew between different device types to meet performance requirements of an integrated circuit

Methods and systems are provided for that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. More specifically, a method is provided for that includes setting device skew requirements for at least one library element, setting device skew test dispositions for the at least one library element based on the set device skew requirements, designing the at least one library element using device skew assumptions, fabricating the at least one library element on a product that includes at least one device skew monitor, determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor, and determining whether the fabricated product meets target specifications.

FIELD OF THE INVENTION

The invention relates to integrated circuit designs and, more particularly, to methods and systems that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power.

BACKGROUND

The conventional design of some library elements (e.g., memory) or products (e.g., application-specific integrated circuits (ASIC) chips) that are designed for newer technology nodes (e.g., 22 nm technology) typically cannot meet performance or functionality requirements at technology minimum or lower voltages. Consequently, the conventional design methods and systems redesign these library elements or products to meet performance requirements at the technology minimum or lower supply voltages using a modulation of a device threshold voltage (e.g., using a lower threshold voltage improves conductivity at the lower supply voltage) of at least one semiconductor switching element (e.g., a field effect transistor) on the library elements or products. The threshold voltage of a switching element is the value of the gate-source voltage when the conducting channel begins to connect the source and drain contacts of the switching element, allowing significant current. The threshold voltage may be dependent upon a number of design constraints including implant type in the channel region, channel sizes, and oxide thicknesses. Accordingly, the conventional modulation of the threshold voltage may include redesigning or altering the doping, the channel size, or the oxide thickness of the switching element.

The use of modulated or lower threshold voltage assists in the switching of the at least one semiconductor switching element on the library elements or products at a faster rate such that the library elements or products meet performance or functionality requirements at technology minimum or lower voltages. However, the use of the modulated or lower threshold voltages in conventional redesigns results in a substantial increase of leakage current, which causes the redesigned devices to require higher power to replace the leaked current and achieve the assisted switching. The increased leakage current and power requirements may also generate heat as the current leaks away, which leads to degraded performance for the redesigned devices.

SUMMARY

In a first aspect of the invention, a method is provided for that includes setting device skew requirements for at least one library element. The method further includes setting device skew test dispositions for the at least one library element based on the set device skew requirements. The method further includes designing the at least one library element using device skew assumptions that are based on the set device skew requirements. The method further includes fabricating the at least one library element on a product that includes at least one device skew monitor. The method further includes determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor. The method further includes determining whether the fabricated product meets target specifications based on a comparison of the determined actual device skew to the set device skew test dispositions.

In another aspect of the invention, a method is provided for that includes setting device skew requirements for at least one library element by process window bin. The method further includes setting device skew test dispositions for each process window bin based on the set device skew requirements. The method further includes designing the at least one library element using device skew assumptions that are based on the set device skew requirements. The method further includes fabricating the at least one library element on a product that includes at least one performance monitor and at least one device skew monitor. The method further includes setting a process window bin for the fabricated product using a performance measured by the at least one performance monitor. The method further includes determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor. The method further includes determining whether the fabricated product meets target specifications based on a comparison of the determined actual device skew to the set device skew test disposition for the set process window bin.

In yet another aspect of the present invention, a system is provided for that includes a CPU, a computer readable memory and a computer readable storage media. The system further includes program instructions to set device skew requirements for at least one library element. The system further includes program instructions to set device skew test dispositions for the at least one library element based on the set device skew requirements. The system further includes program instructions to design the at least one library element using device skew assumptions that are based on the set device skew requirements. The system further includes program instructions to fabricate the at least one library element on a product that includes at least one device skew monitor. The system further includes program instructions to determine an actual device skew of the fabricated at least one library element using the at least one device skew monitor. The system further includes program instructions to determine whether the fabricated product meets target specifications based on a comparison of the determined actual device skew to the set device skew test dispositions. The program instructions are stored on the computer readable storage media for execution by the CPU via the computer readable memory.

DETAILED DESCRIPTION

The invention relates to integrated circuit designs and, more particularly, to methods and systems that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. Embodiments of the present invention use a manufacturing screen or line tailoring to limit skew between integrated circuit devices (e.g., p-type and n-type devices) such that the library elements or products are capable of meeting performance requirements (e.g., minimum voltage requirements for a given technology node) without having the overhead costs associated with modifying the integrated circuit and the additional problems introduced into the integrated circuit that may result from such modification (e.g., increase leakage current and higher power requirements). More specifically, implementations of the present invention provide a method for setting device skew requirements, designing library elements or products using device skew assumptions, monitoring the device skew in manufactured library elements or products, optionally binning or separating the manufactured library elements or products based on process limitations or skew limitations, and shipping those library elements or products that meet the device skew requirements.

Advantageously, the systems and methods described herein for designing, monitoring, and shipping library elements and products allows for designers or manufacturers to control device skew such that those library elements or products that are capable of achieving lower voltages or minimum voltage requirements while still achieving a similar performance at a lower power are shipped to customers. Advantageously, the systems and methods also improve the timing of the library elements and products such that the closing of timing becomes easier than in conventional methodologies.

FIG. 1illustrates the challenges discussed herein of scaling and designing library elements or products for newer technology nodes (e.g., 22 nm technology) while meeting performance requirements at technology minimum or lower voltages. As should be understood, a library element may be a set of devices (i.e. transistors, diodes, resistors, capacitors, and inductors) wired together in a circuit, which perform a function. The n-type devices10and p-type devices15of the library elements or products may be scaled and fabricated over a wide process distribution due to process variation such that at one end20of the process distribution25the n-type devices10and p-type devices15may be characterized as fast and at the other end30of the process distribution25the n-type devices10and p-type devices15may be characterized as slow (i.e., beyond nominal). Specifically, FF (i.e., fast/fast) represents the fast n-type devices10and fast p-type devices15process corner, and SS (i.e., (slow/slow) represents the slow n-type devices10and slow p-type devices15process corner. These outliers are typically limited from the overall manufacturing yield using performance screen ring oscillators (PSROs).

On the other hand, SF (i.e., slow n-type devices/fast p-type devices) and FS (i.e., fast n-type devices/slow p-type devices) represent process corners where n-type devices10to p-type devices15skew issues typically occur. As should be understood, the n-type devices10and p-type devices15at these process corners are proceeding in different directions (i.e., n/p skew) generating outliers beyond nominal. These outliers are conventionally limiting on the minimum voltage obtainable for the entire yield area35because they require designers to redesign the library elements and products to close timing for the SF and FS process corners using buffers and modified circuits (e.g., switching elements with altered doping, channel sizes, or the oxide thickness). However, as discussed above, this has lead to a substantial increase of leakage current, which causes the redesigned devices to require higher power to replace the leaked current. Accordingly, aspects of the present invention discussed in further detail herein provide for the ability to constrain the yield area35to a smaller area (e.g., a narrower n/p skew) such that it is easier to meet the performance requirements in the constrained FS and SF process corners with a lower voltage.

FIG. 2illustrates an exemplary constraint placed on the yield area35in accordance with aspects of the present invention to achieve a constrained yield area40to limit pieces of the process distribution25and obtain a design capability. Specifically, the constrained yield area40shows a narrower n/p skew disposition with a small amount of the process distribution25(i.e., yield loss) outside of the tightened limits. In embodiments, the tighter n/p skew disposition can be set up as a function of the process distribution (e.g., as a function of voltage). The tighter disposition for the n/p skew may be applied to part of a Gaussian manufacturing distribution where most library elements or products are manufactured (e.g., middle of the process distribution25) but still achieve a small yield loss.

Advantageously, application of the tighter skew disposition in accordance with aspects of the present invention results in being able to meet functionality or performance at a lower voltage. The achievement of lower voltages with similar functionality or performance also means lower power requirements for the library elements or products since active power is a function of voltage squared and leakage current is also lower at lower voltages. In embodiments, library elements or products that cannot meet the tighter skew disposition may still be used in higher power budget or lower performance applications, eliminating cost implications. Optionally as discussed further herein, the constraint techniques illustrated inFIG. 2may be used in conjunction with selective voltage binning in order to run faster library elements or products at lower voltage and slower library elements or products at higher voltage, and thus further reduce the maximum power for the distribution of library elements or products.

FIG. 3shows an illustrative environment100for managing the processes in accordance with the invention. To this extent, the environment100includes a server or other computing system112that can perform the processes described herein. In particular, the server112includes a computing device114. The computing device114can be resident on a network infrastructure or computing device of a third party service provider (any of which is generally represented inFIG. 3).

The computing device114also includes a processor120, memory122A, an I/O interface124, and a bus126. The memory122A can include local memory employed during actual execution of program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. In addition, the computing device includes random access memory (RAM), a read-only memory (ROM), and an operating system (O/S).

The computing device114is in communication with the external I/O device/resource128and the storage system122B. For example, the I/O device128can comprise any device that enables an individual to interact with the computing device114(e.g., user interface) or any device that enables the computing device114to communicate with one or more other computing devices using any type of communications link. The external I/O device/resource128may be for example, a handheld device, PDA, handset, keyboard, etc.

In general, the processor120executes computer program code (e.g., program control144), which can be stored in the memory122A and/or storage system122B. Moreover, in accordance with aspects of the invention, the program control144controls a test tool150and/or an assessment tool155to perform the processes described herein. The test tool150and the assessment tool155can be implemented as one or more program code in the program control144stored in memory122A as separate or combined modules. Additionally, the test tool150and assessment tool155may be implemented as separate dedicated processors or a single or several processors to provide the function of these tools. While executing the computer program code, the processor120can read and/or write data to/from memory122A, storage system122B, and/or I/O interface124. The program code executes the processes of the invention. The bus126provides a communications link between each of the components in the computing device114.

In embodiments, the test tool150can be used to set device skew requirements, set device skew dispositions by process bin or other PSRO type identifiers, and allow for the design of library elements or chips using device skew assumptions. For example in accordance with aspects of the invention, the test tool150can set n/p skew requirements for devices of library elements and chips, set an n/p skew test disposition by bin or identifier as a function of the PSRO, and design the library elements or chips using n/p skew assumptions.

In embodiments, the assessment tool155can be used execute the design of the library elements or chips, receive performance and skew data, and effect shipment of product based on the received performance and skew data. For example, in accordance with aspects of the invention, the assessment tool155can execute the design of the library elements or chips using n/p skew assumptions to fabricate the library elements or chips, receive performance data from the fabricated library elements or chips, bin the library elements or chips based on the performance data, test the binned library elements or chips to determine the actual n/p skew of each library element or chip, and effect shipment of product that meets the set device skew requirements.

FIGS. 4 and 6show exemplary flows for performing aspects of the present invention. The steps ofFIGS. 4 and 6may be implemented in the environment ofFIG. 3, for example.

FIG. 4shows a process200for narrowing process corners of a process distribution for at least one library element or product to constrain the design and fabrication of the at least one library element or product at a lower voltage while achieving a similar performance at a lower power. In embodiments, the process200may comprise a design phase205configured to set a N-type device to p-type device skew (i.e., n/p skew) and control design of the at least one library element or product based on device skew, and a fabrication phase210configured to control fabrication and shipping of at least one library element or product based on performance of the device and the n/p skew. As should be understood, in embodiments, the processes of design phase205may be implemented by test tool150(as discussed with respect toFIG. 3) and the processes of fabrication phase210may be implemented by assessment tool155(as discussed with respect toFIG. 3). However, in alternative or additional embodiments, the processes of design phase205and fabrication phase210may be performed on a single processor or tool (e.g., the test tool150) or split into various conceivable processes implemented on multiple processors or tools (e.g., test tool150and assessment tool155) without departing from the spirit and scope of the present invention.

At step215, device n/p skew requirements for at least one library element of a product may be set. In embodiments, this may include setting n/p skew requirements as a design point such that the at least one library element can be designed to meet performance in one or more constrained process corners at a lower voltage. For example, the n/p skew requirement may be set by initially setting maximum and minimum performance limits for n-type devices and p-type devices, and then using those limits to calculate a range of acceptable ratios for n-type devices to p-type devices skew. To set the ratio, the parameter to be measured (Ion, VT, etc.) is selected and the measurement macro (which may be put in every product chip) is designed. The ratio is calculated by dividing the parameter value for the n-type by the parameter value for the p-type measurement. While parameter values corresponding to a process sigma value are typically used, it may also be possible to create ratios that apply process sigma values. For example, ratios may be individually set for each part of the process window within the allowed process distribution. In embodiments, the set limits and calculated range of ratios may be designed to constrain at least one process corner (e.g., the FS process corner) of the normal process distribution for the at least one library element in such a manner that the width of the normal process distribution is narrowed. In other words, the set limits and calculated range of ratios may be designed for each process corner (e.g., SF and FS process corners) at a point or sigma where a yield loss is acceptable while still achieving performance at lower voltages.

In additional or alternative embodiments, the set limits and calculated range of ratios may be designed to be the same or different for each of the process corners (e.g., SF and FS process corners) in such a manner that the width of the normal process distribution is narrowed. Consequently, the narrowing of the normal process distribution reduces the limitations placed on the minimum voltage achievable via a larger process distribution that includes library elements with too large of an n/p skew for achieving the minimum voltage without redesign or modification (e.g., modulation of the voltage) of the library elements. The set n/p skew requirements may then be placed into the target specifications (i.e., the spec).

At step220, device skew test dispositions may be set based on the set n/p skew requirements. In embodiments, the n/p skew test dispositions may be set as a function of the process distribution to match design criteria limits imposed by the set n/p skew requirements. For example, the device skew test dispositions may be set as a function of voltage, voltage and temperature, temperature, other parameters individually or in combination, etc.

In embodiments, the setting the n/p skew test dispositions may include setting up a different n/p skew disposition requirement at different points within the process distribution. Library elements that are very slow or very fast (e.g., at the SS and FF corners of the process distribution) may have a limit set where n/p skew is very close together (lower n/p value) and not impact product yield. Library elements that are around nominal (e.g., at the SF and FS corners of the process distribution) may have a higher allowed n/p ratio since a tighter ratio would result in significant yield fallout. Accordingly, as the process distribution shifts to the slow side or the fast side, the n/p ratio may be adjusted such that all products are contained within the ellipse (shown inFIG. 2as the constrained yield area40) allowed for the product.

FIG. 5is a chart illustrating the concept of setting the n/p skew requirements and test dispositions as discussed with respect to steps215and220. Specifically,FIG. 5shows that a set n/p device skew requirement of +/−3 sigma allows for all product manufactured across a process distribution to achieve a minimum voltage requirement of 0.70V. However, constraining the n/p device skew requirements for example to meet smaller voltage requirements (e.g., 0.65V and 0.60V) changes the number product manufactured across the process distribution capable of achieving the smaller voltage requirements. In accordance with these aspects of the present invention, the n/p skew dispositions perform as a screen for eliminating a small yield percentage216of library elements or products that have too large of an n/p skew while at the same time allowing a larger yield percentage217of library elements or products to be designed, fabricated, and shipped with improved low voltage operation and low power requirements.

At step225, the at least one library element of the product may be designed using n/p skew assumptions that are based on the set n/p skew requirements. In embodiments, the assumptions comprise the n/p skew requirements (i.e., the range of acceptable ratios for n-type devices to p-type devices skew) and additional performance data for the n-type devices and p-type devices (e.g., the maximum and minimum performance limits). In accordance with aspects of the invention, the at least one library element is capable of being designed without using buffers and modified circuits (e.g., switching elements with altered doping, channel sizes, or the oxide thickness) because of the constraints imposed by the n/p skew assumptions. In other words, the at least one library element is being design in an environment or process distribution constrained by the n/p skew assumptions.

At step230, the design of the library elements may be executed to fabricate a product in accordance with target specifications of the design. In embodiments, the fabrication of the product may include forming at least one device skew monitor (e.g., scaling parametric macros, see, e.g., U.S. Pat. No. 7,382,149, issued on Jun. 3, 2008, which is incorporated herein by reference in its entirety) within the library elements or product. The skew monitors may be configured to measure the performance of each of the n-type devices and the p-type devices, generate performance data, and optionally calculate a difference or ratio in the performances using the performance data to obtain an actual n/p skew of the fabricated product.

At step235, each fabricated product may be tested to obtain the actual n/p skew of the product, and the actual n/p skew may be used to determine product that meets n/p skew target specifications. In embodiments, this may comprise either: (i) receiving performance data from the device skew monitors implemented on each product and calculating a difference or ratio in the performances of the n-type device and p-type devices to obtain an actual n/p skew of each fabricated product, or (ii) receiving the already calculated actual n/p skew of each fabricated product from the device skew monitors.

Additionally, this may comprise comparing the actual n/p skew for each product to at least one set n/p skew test disposition to determine whether the product meets n/p skew target specifications. For example, the actual n/p skew for each product may be compared to at least one set n/p skew test disposition, and when the actual n/p skew falls under or over the at least one set test dispositions a determination is made as to whether the product meets n/p skew target specifications dependent upon how the test dispositions are set. The at least on set device skew test disposition may be determined based on where the fabricated product falls within the process distribution (e.g., near nominal, or at slow or fast end of the process distribution).

At step240, the product that meets n/p skew target specifications may be shipped to a customer. The product that does not meet n/p skew target specifications may be scraped. In embodiments, this may include scrapping all the product that does not meet the n/p skew target specifications, or the product that cannot meet the tighter skew disposition could still be used in higher power budget or lower performance applications where applicable and the remaining product scraped.

As discussed herein with respect to process200, the concept of applying a constraint in a product manufacturing process to limit pieces of the distribution, and thus obtain a design capability may be used in conjunction with process window binning, such as selective voltage binning (SVB), systems and methods to achieve greater power and/or performance optimization. Specifically,FIG. 6shows a process300for narrowing process corners of a process distribution for at least one library element or product to constrain the design and fabrication of the at least one library element or product for each process window bin (e.g., SVB bin). In embodiments, the process300may comprise a design phase305configured to set a N-type device to p-type device skew (i.e., n/p skew) by process window bin and control design of the at least one library element or product based on device skew, and a fabrication phase310configured to control fabrication and shipping of at least one library element or product based on performance of the device and the n/p skew. As should be understood, in embodiments, the processes of design phase305may be implemented by test tool150(as discussed with respect toFIG. 3) and the processes of fabrication phase310may be implemented by assessment tool155(as discussed with respect toFIG. 3). However, in alternative or additional embodiments, the processes of design phase305and fabrication phase310may be performed on a single processor or tool (e.g., the test tool150) or split into various conceivable processes implemented on multiple processors or tools (e.g., test tool150and assessment tool155) without departing from the spirit and scope of the present invention.

At step315, device n/p skew requirements for at least one library element may be set by process window bin. In embodiments, this may include setting n/p skew requirements as a design point for each process window bin (e.g., 16 bins) set for process binning procedures (e.g., SVB) or PSRO identifiers. For example, SVB procedures typically use several PSRO measurements to quantify chip performance after manufacturing. Voltage binning of individual integrated circuit devices is achieved by operating the integrated circuits at a plurality of required clock frequencies, and, for each of those frequencies, determining the minimum supply voltage level that produces a pass result for a series of applied test vectors. The bin voltage establishes a minimum voltage needed for performance of the integrated circuit device at normal operating conditions. Thus, SVB is essentially an open loop technique that provides a bin identifier associated with a voltage and performance criteria for each integrated circuit device are set to define each bin identifier. Accordingly, in embodiments of the present invention, device n/p skew requirements may be set for each of the determined process window bin identifiers such that the at least one library element can be designed to meet performance in one or more constrained process corners for each bin.

For example, the n/p skew requirement for each bin may be set by initially setting maximum and minimum performance limits for n-type devices and p-type devices, and then using those limits to calculate a range of acceptable ratios for n-type devices to p-type devices skew. To set the ratio, the parameter to be measured (Ion, VT, etc.) is selected and the measurement macro (which may be put in every product chip) is designed. The ratio is calculated by dividing the parameter value for the n-type by the parameter value for the p-type measurement. While parameter values corresponding to a process sigma value are typically used, it may also be possible to create ratios that apply process sigma values. For example, ratios may be individually set for each part of the process window within the allowed process distribution. In embodiments, the set limits and calculated range of ratios may be designed to constrain at least one process corner (e.g., the FS process corner) of the normal process distribution for the at least one library element in such a manner that the width of the normal process distribution is narrowed. In other words, the set limits and calculated range of ratios may be designed for each process corner (e.g., SF and FS process corners) at a point or sigma where a yield loss is acceptable while still achieving performance at lower voltages.

In additional or alternative embodiments, the set limits and calculated range of ratios may be designed to be the same or different for each of the process corners (e.g., SF and FS process corners) in such a manner that the width of the normal process distribution is narrowed. Consequently, the narrowing of the normal process distribution reduces the limitations placed on the minimum voltage achievable via a larger process distribution that includes library elements with too large of an n/p skew for achieving the minimum voltage without redesign or modification (e.g., modulation of the voltage) of the library elements. The set n/p skew requirements for each process window bin may then be placed into the target specifications (i.e., the spec).

At step320, device skew test dispositions are set for each process window bin based on the set n/p skew requirements. In embodiments, the n/p skew test dispositions may be set for each process window bin as a function of the process distribution to match design criteria limits imposed by the set n/p skew requirements. For example, the device skew test disposition for each process window bin may be set as a function of voltage, voltage and temperature, temperature, other parameters individually or in combination, etc.

In embodiments, the setting the n/p skew test dispositions may include setting up a different n/p skew disposition requirement for each process window bin throughout the process distribution. Process window bins that may comprise library elements that are very slow or very fast (e.g., at the SS and FF corners of the process distribution) may have a limit set where n/p skew is very close together (lower n/p value) and not impact product yield. Process window bins that may comprise library elements that are around nominal (e.g., at the SF and FS corners of the process distribution) may have a higher allowed n/p ratio since a tighter ratio would result in significant yield fallout. Accordingly, as the process distribution shifts to the slow side or the fast side, the n/p ratio may be adjusted such that all products are contained within the ellipse (shown inFIG. 2as the constrained yield area40) allowed for the product.

At step325, the at least one library element of the product may be designed using n/p skew assumptions that are based on the set n/p skew requirements for each process window bin. In embodiments, the assumptions comprise the n/p skew requirements (i.e., the range of acceptable ratios for n-type devices to p-type devices skew) and additional performance data for the n-type devices and p-type devices (e.g., the maximum and minimum performance limits). In accordance with aspects of the invention, the at least one library element is capable of being designed without using buffers and modified circuits (e.g., switching elements with altered doping, channel sizes, or the oxide thickness) because of the constraints imposed by the n/p skew assumptions. In other words, the at least one library element is being design in an environment or process distribution constrained by the n/p skew assumptions.

At step330, the design of the library elements may be executed to fabricate a product in accordance with target specifications of the design. In embodiments, the fabrication of the product may include forming at least one performance monitor (e.g., a PSRO or some set of sample/reference logic paths) within the library elements or product. The at least one performance monitor may be configured to take measurements during testing of the library elements or product, which may be used quantify the library element or product performance after fabrication. The performance monitor measurements are essentially a statement of the aggregate effect of a wide variety of different parameters upon a circuit within the library element or product connected to the performance monitor. However, different types of circuits are typically present within a single library element or product, and some of these different types of circuits will exhibit different sensitivities to the variety of parameters. Thus, if a performance monitor is used to determine the bin voltage, there will likely be some circuits that inevitably track differently such that they are at a slightly different point in their best-case to worst-case performance range. Consequently, it is preferable to use more than one performance monitor within the library element or product to obtain a robust indication of performance for the single library element or product.

In embodiments, the fabrication of the product may also include forming at least one device skew monitor (e.g., scaling parametric macros) within the library elements or product. The skew monitors may be configured to measure the performance of each of the n-type devices and the p-type devices, generate performance data, and optionally calculate a difference or ratio in the performances using the performance data to obtain an actual n/p skew of the fabricated product.

At step335, the at least one performance monitor may be used to set the process window bins. In embodiments, after the library elements and product have been fabricated according to the design using fabrication equipment, performance monitor measurements may be obtained to quantify library element or product performance. Based on the performance monitor measurements, a number (e.g., 16) of process window bins (SVB bins) may be identified. Each bin has a minimum requirement (e.g., voltage) for circuit performance. The requirement (e.g., voltage) for each bin may be represented by an electronic chip identification data (ECID) that may be stored on the product. Thus, the ECID value is burned into the product based on process, the customer reads the ECID (which can be tied to an input/output (IO)) to determine requirement (e.g., voltage) levels on board, and the customer handles setting corresponding input values (e.g., power supplies) differently based upon the ECID value. Further, timing closure runs may be adjusted for the process window bins. Thus, the ECID defines the performance sorting and criteria for a particular bin on each product. A portion of this information includes the identification of the cut point to supply information to an onboard management unit such as a voltage management unit.

At step340, each fabricated product may be tested to obtain the actual n/p skew of the product, and the actual n/p skew may be used to determine product that meets n/p skew target specifications by process window bin. In embodiments, this may comprise either: (i) receiving performance data from the device skew monitors implemented on each product and calculating a difference or ratio in the performances of the n-type device and p-type devices to obtain an actual n/p skew of each fabricated product, or (ii) receiving the already calculated actual n/p skew of each fabricated product from the device skew monitors. Additionally, this may comprise comparing the actual n/p skew for each product to the set n/p skew test disposition for the process window bin upon which the product was identified as falling within at step335to determine whether the product meets n/p skew target specifications. For example, the actual n/p skew for each product may be compared to the set n/p skew test disposition for the process window bin indentified as being met by the performance of the product at step335, and when the actual n/p skew falls under or over the set test disposition, a determination is made as to whether the product meets n/p skew target specifications dependent upon how the test dispositions are set.

At step345, the product that meets n/p skew target specifications may be shipped to a customer. The product that does not meet n/p skew target specifications may be scraped. In embodiments, this may include scrapping all the product that does not meet the n/p skew target specifications, or the product that cannot meet the tighter skew disposition could still be used in higher power budget or lower performance applications where applicable and the remaining product scraped.

In accordance with these aspects of the present invention, the systems and methods of controlling device skew to meet performance requirements are hereafter discussed in detail as they pertain to the exemplary use for memory elements (e.g., SRAM). However, those of ordinary skill in the art should understand that the use of the systems and methods described herein with respect to memory elements is illustrative of one exemplary use and that other uses (e.g., other library elements or whole chips) for the systems and methods described herein are contemplated by the invention, all of which achieve similar advantages and do not depart from the scope and spirit of the invention.

FIG. 7is a diagram of a typical memory element400, comprising p-type devices405and n-type devices410. In embodiments, the p-type devices405and n-type devices410may be fabricated over a wide process distribution due to process variation such that at one end of the process distribution the p-type devices405and n-type devices410may be characterized as fast and at the other end of the distribution the p-type devices405and n-type devices410may be characterized as slow (i.e., beyond nominal). Thus, the n-type to p-type device skew (i.e., n/p skew) may be understood to be the difference between the strength of the n-type devices410to pull the pass gates415low and the strength of the p-type device to pull the pass gates415high. The resultant strengths of the pass gates415typically affect the writeability or stability (e.g., the ability of the memory cell to maintain a stored value or the likelihood that the stored value flips during a reading process) of the memory element400.

FIG. 8is a chart illustrating this relationship between writeability and stability for memory elements manufactured from a common design but that are different because of different processing conditions that occur within acceptable manufacturing tolerances. Typically the strengths of the pass gates trade off stability for writeability. For example, as shown inFIG. 8, memory elements, such as static random access memory (SRAM), conventionally comprise an assist circuit that is configured to modulate the pass gates to satisfy a targeted sigma (e.g., 5.5 s) in the process distribution for both stability and writeability (i.e., modulates the tradeoff between stability and writeability) such that the SRAM works appropriately. However, as the area requirements for memory elements shrink with respect to physically smaller device requirements in smaller technology nodes, such as 22 nm technology nodes, there are a number of challenges facing designers to modulate the tradeoff between stability and writeability while burning less power or achieving lower voltage requirements.

FIG. 9is a chart illustrating the relationship between physical area scaling and power or voltage scaling for memory elements. Specifically, area420illustrates that the voltage or power requirements of memory elements within the 32−14 nm technologies has not traditionally scaled appropriately with respect to the physical area scaling of the memory element. This absence of voltage scaling is mainly attributable to the challenges inherent in meeting both stability and writeability requirements for the memory element. Accordingly, aspects of the present invention provide for the ability to control the n/p skew of devices in order to achieve these lower voltage or minimum voltage requirements and have voltage scaling track with physical area scaling of the library elements or chips across multiple technology nodes.

This scaling challenge is further illustrated in the chart shown inFIG. 10. For example, elements425and430represent p-type and n-type devices that demonstrate leakage and read timing limitations, respectively. Specifically, element425represents the fast nFET and fast pFET process corner, and element430represents the slow nFET and slow pFET process corner. These outliers are typically limited from the overall manufacturing yield using PSROs.

On the other hand, elements435and440represent p-type and n-type devices that demonstrate stability and writing limitations, respectively. Specifically, element435represents the fast nFET and slow pFET process corner, and element440represents the slow nFET and fast pFET process corner. As should be understood, the n-type and p-type devices at these process corners are proceeding in different directions generating outliers beyond nominal. These outliers are conventionally not limited from the overall manufacturing yield, and instead the tradeoffs between stability and writeability are modulated to achieve design requirements. However, as discussed herein, this has lead to voltage scaling issues whereby it has become difficult to achieve minimum voltage requirements at smaller technology nodes. Accordingly, aspects of the present invention provide for the ability to constrain the yield area445to a smaller area such that only the functional chips450capable of achieving these lower voltage or minimum voltage requirements are shipped to customers.

Design process910employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure920together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure990.