Three-dimensional semiconductor device

A three-dimensional semiconductor device includes a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion covering the pattern portions, the plate portion having a width greater than a width of each of the pattern portions and being connected to the pattern portions, a lower structure between the first substrate and the second substrate, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2018-0101721, filed on Aug. 29, 2018, in the Korean Intellectual Property Office, and entitled: “Three-Dimensional Semiconductor Device,” is incorporated by reference herein in its entirety.

BACKGROUND

Embodiment relates to a three-dimensional semiconductor device.

2. Description of the Related Art

In order to increase the price competitiveness of products, there is growing demand for improvements in a degree of integration of semiconductor devices.

SUMMARY

Embodiments are directed to a three-dimensional semiconductor device, including a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion covering the pattern portions, the plate portion having a width greater than a width of each of the pattern portions and being connected to the pattern portions, a lower structure between the first substrate and the second substrate, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns.

Embodiments are also directed to a three-dimensional semiconductor device, including a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion in contact with the pattern portions while covering the pattern portions, a lower structure between the first substrate and the second substrate, and an upper structure on the second substrate. The lower structure may include a peripheral wiring, the plate portion may include a semiconductor layer, and the plate portion may have a width greater than a width of each of the pattern portions.

Embodiments are also directed to a three-dimensional semiconductor device, including a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion connected to the pattern portions while covering the pattern portions, a lower structure between the first substrate and the second substrate, and including a peripheral wiring, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns. The pattern portions may have a linear shape, and the plate portion may include a semiconductor layer.

DETAILED DESCRIPTION

FIG. 1Ais a schematic block diagram illustrating a semiconductor device according to an example embodiment.

Referring toFIG. 1A, a semiconductor device1according to an example embodiment may include a memory array region MA, a row decoder3, a page buffer4, a column decoder5, and a control circuit6. The memory array region MA may include memory blocks BLK.

The memory array region MA may include memory cells arranged in a plurality of rows and a plurality of columns. The memory cells, included in the memory array region MA, may be electrically connected to the row decoder3through word lines WL, at least one common source line CSL, string select lines SSL, and at least one ground select line GSL, and may be electrically connected to the page buffer4and the column decoder5through bit lines BL.

In an example embodiment, among the memory cells, memory cells arranged on a common row may be connected to a single word line WL, and memory cells arranged in a common column may be connected to a single bit line BL.

The row decoder3may be commonly connected to the memory blocks BLK, and may provide a driving signal to word lines WL of the memory blocks BLK, selected according to a block select signal. For example, the row decoder3may receive address information ADDR from an external source, and may decode the address information ADDR, having been received, to determine a voltage provided to at least a portion of the word lines WL, the common source line CSL, the string select lines SSL, and the ground select line GSL, electrically connected to the memory blocks BLK.

The page buffer4may be electrically connected to the memory array region MA through the bit lines BL. The page buffer4may be connected to a bit line BL selected according to an address decoded by the column decoder5. The page buffer4may temporarily store data to be stored in memory cells or may sense data stored in the memory cell, according to a mode of operation. For example, the page buffer4may be operated as a write driver circuit during a programming operation mode, and may be operated as a sense amplifier circuit during a reading operation mode. The page buffer4may receive power (for example, voltage or current) from a control logic, and may provide the power to the bit line BL, having been selected.

The column decoder5may provide a data transmission path between the page buffer4and an external device (for example, a memory controller). The column decoder5may decode address input from an external source, and may thus select one among the bit lines BL.

The column decoder5may be commonly connected to the memory blocks BLK, and may provide data information to the bit lines BL of the memory block BLK, selected according to a block select signal.

The control circuit6may control the overall operation of the semiconductor device1. The control circuit6may receive a control signal and an external voltage, and may be operated according to the control signal, having been received. The control circuit6may include a voltage generator for generating voltages (for example, a programming voltage, a reading voltage, an erasing voltage, or the like) required for internal operation using an external voltage. The control circuit6may control reading, writing, and/or erasing operations in response to the control signals.

FIG. 1Bis a conceptual circuit diagram illustrating the memory array region (MA inFIG. 1A).

Referring toFIGS. 1A and 1B, a semiconductor device according to an example embodiment may include a common source line CSL, bit lines BL, and a plurality of cell strings CSTR between the common source line CSL and the bit lines BL. The common source line CSL, the bit lines BL, and the plurality of cell strings CSTR may be disposed in the memory array region MA.

The plurality of cell strings CSTR may be connected to each of the bit lines BL in parallel. The plurality of cell strings CSTR may be commonly connected to the common source line CSL. Each of the plurality of cell strings CSTR may include a lower select transistor GST, memory cells MCT, and an upper select transistor SST, connected in series.

The memory cells MCT may be connected in series between the lower select transistor GST and the upper select transistor SST. Each of the memory cells MCT may include data storage regions capable of storing data.

The upper select transistor SST may be electrically connected to the bit lines BL, while the lower select transistor GST may be electrically connected to the common source line CSL.

The upper select transistor SST may be provided as a plurality of upper select transistors, and may be controlled by string select lines SSL. The memory cells MCT may be controlled by a plurality of word lines WL.

The lower select transistor GST may be controlled by a ground select line GSL. The common source line CSL may be commonly connected to a source of the ground select transistor GST.

In an example, the upper select transistor SST may be a string select transistor, while the lower select transistor GST may be a ground select transistor.

FIG. 2is a schematic perspective view illustrating an example of a three-dimensional semiconductor device according to an example embodiment.

Referring toFIG. 2, a three-dimensional semiconductor device1according to an example embodiment may include a first substrate10, a lower structure50on the first substrate10, a second substrate60on the lower structure50, and an upper structure100on the second substrate60.

The first substrate10may be a semiconductor substrate which may be formed of a semiconductor material such as silicon, or the like. For example, the first substrate10may be a single crystal semiconductor substrate, for example, a single crystal silicon substrate. The lower structure50may include at least one among the row decoder3, the page buffer4, and/or the column decoder5, illustrated inFIG. 1A.

The second substrate60may include pattern portions70, and a plate portion80covering the pattern portions70. The plate portion80may include a semiconductor layer, for example, a polycrystalline semiconductor layer. The polycrystalline semiconductor layer may include a polysilicon layer. The upper structure100may include the memory array region MA, described above.

FIG. 3Ais a plan view illustrating a portion of a three-dimensional semiconductor device according to an example embodiment,FIG. 3Bis a plan view illustrating a portion of a three-dimensional semiconductor device according to an example embodiment,FIG. 4is a schematic cross-sectional view illustrating a region taken along line I-I′ ofFIGS. 3A and 3B, andFIG. 5is a schematic cross-sectional view illustrating a region taken along line II-II′ ofFIGS. 3A and 3B.

Referring toFIGS. 3A to 5, the lower structure50may be on the first substrate10. The first substrate10may be a single crystal semiconductor substrate, as described above.

The lower structure50may include lower insulating layers25,35, and45, peripheral wirings30and40, as well as peripheral transistors PTR. The isolation regions15i, defining peripheral active regions15a, may be disposed in the first substrate10.

The peripheral transistors PTR may include peripheral gates PG on the peripheral active regions15a, and peripheral source/drains S/D disposed in the peripheral active regions15aon both sides of the peripheral gates PG.

The peripheral wirings30and40may include first peripheral wirings30, electrically connected to the peripheral transistors PTR, and second peripheral wirings40, electrically connected to the first peripheral wirings30.

The lower insulating layers25,35, and45may include a first lower insulating layer25surrounding a side surface of the first peripheral wirings30, a second lower insulating layer35on the second lower insulating layer25and surrounding a side surface of the second peripheral wirings30, and a third lower insulating layer45on the second lower insulating layer35. The lower insulating layers25,35, and45may include silicon oxide.

The peripheral transistors PTR and the peripheral wirings30and40may configure a peripheral circuit of at least one among the row decoder3, the page buffer4, and/or the column decoder5, illustrated inFIG. 1A.

A second substrate60may be on the lower structure50. The lower structure50may be between the first substrate10and the second substrate60. The second substrate60may include pattern portions70, and a plate portion80connected to the pattern portions70. The plate portion80may have a width greater than that of each of the pattern portions70and may be connected to the pattern portions70. The plate portion80may be in contact with the pattern portions70.

In an example, the second substrate60may further include a connection portion (62ofFIG. 3A) connecting the pattern portions70. The pattern portions70may have a linear shape, and the connection portion62may connect the pattern portions70having the linear shape. The pattern portions70and the connection portion62may have an integrated structure.

In an example, the third lower insulating layer45may have recess regions45r, and the pattern portions70may fill the recess regions45r. Thus, a bottom surface and a side surface of the pattern portions70may be covered by the third lower insulating layer45.

The plate portion80may include a semiconductor layer. For example, the plate portion80may include a polysilicon layer.

An intermediate insulating layer90may be on a side surface of the plate portion80.

A stacked structure170may be on the plate portion80.

The stacked structure170may include interlayer insulating layers110and horizontal conductive patterns160. The horizontal conductive patterns160may be stacked on the second substrate60while being spaced apart from each other in a vertical direction Z, perpendicular to an upper surface80sof the second substrate60. The interlayer insulating layers110and the horizontal conductive patterns160may be repeatedly and alternately stacked. The interlayer insulating layers110may be formed of silicon oxide. The horizontal conductive patterns160may be gate patterns.

The horizontal conductive patterns160may include a lower horizontal conductive pattern160L, an upper horizontal conductive pattern160U, and intermediate horizontal conductive patterns160M between the lower horizontal conductive pattern160L and the upper horizontal conductive pattern160U. The lower horizontal conductive pattern160L may be lower gate pattern, the upper horizontal conductive pattern160U may be upper gate pattern, and the intermediate horizontal conductive patterns160M may be intermediate horizontal gate patterns.

The horizontal conductive patterns160are stacked in a first region A1on the second substrate60while being spaced apart from each other in the direction Z perpendicular to an upper surface80sof the second substrate60, and may include pad regions P extended from the first region A1to an interior of the second region A2to be arranged in a staircase shape. In an example embodiment, the pad regions P may be modified into various forms.

In an example embodiment, the first region A1may be the memory array region (MA ofFIGS. 1A and 1B), illustrated inFIGS. 1A and 1B, or a region in which the memory array region (MA ofFIGS. 1A and 1B) is located. Thus, the first region A1may be referred to as a ‘memory array region MA.’

In an example embodiment, the second region A2may be located on one side or on both sides of the first region A1. The second region A2may be a region provided with the pad regions P, in which the horizontal conductive patterns160are extended from the first region A1and arranged in the staircase shape. The second region A2may be referred to as an ‘extended region’ or a ‘staircase shape region.’

In an example, the lower horizontal conductive pattern160L may include the ground select line GSL illustrated inFIGS. 1A and 1B.

In an example, the upper horizontal conductive pattern160U may include the string select line SSL illustrated inFIGS. 1A and 1B.

In an example, the intermediate horizontal conductive patterns160M may include the word lines WL illustrated inFIGS. 1A and 1B.

An upper insulating layer115may be on the second substrate60and the intermediate insulating layer90. The upper insulating layer115may cover the pad regions P of the horizontal conductive patterns160.

A first capping insulating layer150and a second capping insulating layer185may be sequentially on the stacked structure170and the upper insulating layer115. The upper insulating layer115, as well as the first capping insulating layer150and the second capping insulating layer185, may include silicon oxide.

In the first region A1, vertical structures120, passing through the stacked structure170, may be disposed. The vertical structures120may have a side surface opposing the horizontal conductive patterns160. At least a portion of the vertical structure120may be a channel.

Separation structures175, passing through the stacked structure170, may be provided. The separation structures175may have an upper surface located at a level higher than a level of the vertical structures120. The separation structures175may pass through the stacked structure170, may be extended upwardly, and may pass through the first capping insulating layer150. The separation structures175may be disposed in separation trenches155, passing through the first capping insulating layer150and the stacked structure170.

The separation structures175may have a linear shape, extended in a first direction X. The first direction X may be a direction parallel to an upper surface80sof the second substrate60.

In an example, when viewed in plan, the separation structures175may intersect the stacked structure170.

Bit lines195, gate connection wirings196, and a peripheral connection wiring198may be on the second capping insulating layer185.

Between the bit lines195and the vertical structures120, bit line contact plugs190, electrically connecting the bit lines195to the vertical structures120, may be disposed.

Gate contact structures180, electrically connected to the horizontal conductive patterns160, may be on the pad regions P of the horizontal conductive patterns160.

Between the gate connection wirings196and the gate contact structures180, gate contact plugs192, electrically connecting the gate connection wirings196to the gate contact structures180, may be disposed.

A peripheral contact structure182may be on a peripheral contact region40P of the second peripheral wirings40. The peripheral contact structure182may pass through the third lower insulating layer45, the intermediate insulating layer90, the upper insulating layer115, and the first capping insulating layer150.

Between the peripheral connection wiring198and the peripheral contact structure182, a peripheral contact plug194, electrically connecting the peripheral connection wiring198to the peripheral contact structure182, may be disposed.

In an example, in the second substrate60, an end portion80′ of the plate portion80may have a form protruding as compared with an end portion70′ of the pattern portions70. Various examples of the end portion of the plate portion80and the end portion of the pattern portions70will be described with reference toFIGS. 6A and 6B, respectively.

FIGS. 6A and 6Bare partially enlarged cross-sectional views illustrating the end portion of the plate portion80and the end portion of the pattern portions70.

In a modified example, referring toFIG. 6A, the pattern portions70may have an end portion70a′ in the form protruding as compared with an end portion80′ of the plate portion80.

In a modified example, referring toFIG. 6B, the pattern portions70may have an end portion70b′ vertically aligned with an end portion80′ of the plate portion80.

Referring again toFIGS. 3A to 5, each of the vertical structures120, described above, may include a vertical structure, and each of the horizontal conductive patterns160, described above, may include different material layers. An example of the vertical structures120and the horizontal conductive patterns160, described above, will be described with reference toFIG. 7.

FIG. 7is a partially enlarged cross-sectional view illustrating an enlarged portion indicated by ‘B’ inFIG. 5.

Referring toFIGS. 3A to 5, and 7, each of the vertical structures120may include a channel semiconductor layer140and a gate dielectric structure130, between the channel semiconductor layer140and the stacked structure170.

In an example, each of the vertical structures120may further include a semiconductor pattern125, an insulating core pattern145on the semiconductor pattern125, and a pad pattern147on the insulating core pattern145.

The channel semiconductor layer140may be disposed to surround an outer side surface of the insulating core pattern145while being in contact with the semiconductor pattern135. The gate dielectric structure130may be disposed to surround an outer side surface of the channel semiconductor layer140. The semiconductor pattern125may be an epitaxial material layer which may be formed using a selective epitaxial growth (SEG) process. The insulating core pattern145may be formed of an insulating material (e.g., silicon oxide, or the like). The pad pattern147may be formed of polysilicon having N-type conductivity, and may be a drain region. The pad pattern147may be on a level higher than a level of the upper horizontal conductive pattern160U. The pad pattern147of the vertical structure120may be in contact with the bit line contact plug190, described above, and may be electrically connected thereto.

In an example, the channel semiconductor layer140may pass through the horizontal conductive patterns160. When the vertical structure120further includes the semiconductor pattern125, the semiconductor pattern125may pass through the lower horizontal conductive pattern160L, and the channel semiconductor layer140may pass through the intermediate horizontal conductive pattern160M and the upper horizontal conductive pattern160U. The channel semiconductor layer140may be formed of a polysilicon layer.

In an example, the semiconductor pattern125may be referred to as a channel semiconductor layer. For example, the semiconductor pattern125may be referred to as a lower channel semiconductor layer located in a relatively lower portion, while the channel semiconductor layer140may be referred to as an upper channel semiconductor layer located in a relatively upper portion.

In an example, an additional dielectric158between the semiconductor pattern125and the lower horizontal conductive pattern160L may be further included. The additional dielectric158may include silicon oxide.

The gate dielectric structure130may include a tunnel dielectric layer136, a data storage layer134, and a blocking dielectric layer132. The data storage layer134may be between the tunnel dielectric layer136and the blocking dielectric layer132. The blocking dielectric layer132may be between the data storage layer134and the stacked structure170.

The tunnel dielectric layer136may be between the data storage layer134and the channel semiconductor layer140. The tunnel dielectric layer136may include silicon oxide and/or impurity-doped silicon oxide. The blocking dielectric layer132may include silicon oxide and/or high-k dielectric material. The data storage layer134may be formed of a material which may store data, for example, silicon nitride.

The data storage layer134may include regions to store data between the channel semiconductor layer140and the intermediate horizontal conductive patterns160M (the intermediate horizontal conductive patterns160M may include the word lines WL, illustrated inFIGS. 1A and 1B). For example, depending on operating conditions of a non-volatile memory device such as a flash memory device, an electron that is injected from the channel semiconductor layer140into the data storage layer134through the tunnel dielectric layer136may be trapped to be retained, or the electron that is trapped in the data storage layer134may be erased.

Thus, as described above, regions of the data storage layer134, located between intermediate horizontal conductive patterns160M, which may be the word lines (WL ofFIGS. 1A and 1B), and the channel semiconductor layer140may be defined as data storage regions, and the data storage regions may configure the memory cells (MCT ofFIG. 1B) illustrated inFIG. 1B.

Each of the horizontal conductive patterns160may include a first material layer162and a second material layer164that are different from each other. In an example, the first material layer162may be a high-k dielectric material such as aluminum oxide, or the like, while the second material layer164may be formed of a conductive material including, for example, one, or two or more, among metal nitride (e.g., TiN or WN), metal (e.g., W), metal silicide (e.g., TiSi or WSi), or doped silicon. In another example, the first material layer162and the second material layer162may be formed of different conductive materials. The first material layer162may be extended between the second material layer162and the vertical structures120while covering an upper surface and a lower surface of the second material layer162.

FIG. 8Ais a partially enlarged cross-sectional view illustrating an enlarged region indicated by ‘C’ inFIG. 5.

Referring toFIGS. 3A to 5, and 8A, each of the horizontal conductive patterns160may include the first material layer162and the second material layer164, as described with reference toFIG. 7. The first material layer162may cover an upper surface and a lower surface of the second material layer162, while the second material layer162may be directly in contact with the separation structures175.

In an example, the separation structures175may be formed of an insulating material such as silicon oxide filling the separation trenches155. A modified example of the separation structures175will be described with reference toFIG. 8B.

FIG. 8Bis a partially enlarged cross-sectional view illustrating an enlarged region indicated by ‘C’ inFIG. 5.

In a modified example, referring toFIG. 8B, each of the separation structures175may include a separation spacer176and a separation core pattern178. The separation spacer176may include an insulating material such as silicon oxide, or the like. The separation core pattern178may be formed of a conductive material including, for example, one or two or more among metal nitride (e.g., TiN or WN), metal (e.g., W), metal silicide (e.g., TiSi or WSi), or doped silicon.

Referring again toFIGS. 3A to 5, the plate portion80and the pattern portions70of the second substrate60may be in direct contact with each other and may be formed of different materials. The plate portion80may include a semiconductor layer, and the pattern portions70may be formed of a material of one or two or more among an insulating material, a doped semiconductor material, or a metallic material.

In an example, the pattern portions70may be formed of silicon nitride, and the plate portion80may be formed of a semiconductor layer.

In another example, the pattern portions70may be formed of polysilicon, and the plate portion80may be formed of a semiconductor layer forming an interface with the pattern portions70.

Next, referring toFIGS. 9A to 12B, various examples of the second substrate60will be described.FIGS. 9A to 12Bare partially enlarged cross-sectional views illustrating an enlarged region indicated by ‘A’ inFIG. 4.

In an example, referring toFIG. 9A, a second substrate60amay include pattern portions70aand a plate portion80aon the pattern portions70a. The plate portion80amay be formed of a semiconductor layer, for example, a doped polysilicon layer. For example, the plate portion80amay be formed of a polysilicon layer having N-type conductivity.

The second substrate60amay further include a barrier layer64covering a side surface and a bottom surface of the pattern portions70a. The barrier layer64may be formed of a conductive barrier layer such as Ti/TiN, or the like, while the pattern portions70amay be formed of a metal material such as tungsten or the like having electrical resistance lower than that of a semiconductor layer of the plate portion80a. Thus, the second substrate60amay include the pattern portions70ahaving low electrical resistance and the plate portion80ahaving semiconductor characteristics. The second substrate60a, described above, may improve electrical characteristics of the three-dimensional semiconductor device.

In a modified example, referring toFIG. 9B, a second substrate60bmay include pattern portions70b, a barrier layer64covering a side surface and a bottom surface of the pattern portions70b, and a plate portion80bon the pattern portions70b. The pattern portions70band the barrier layer64may be the same as the pattern portions70aand the barrier layer64, described with reference toFIG. 9A.

The plate portion80bmay include a first plate layer80b1and a second plate layer80b2on the first plate layer80b1.

The second plate layer80b2may be a semiconductor layer. For example, the second plate layer80b2may be formed of a doped polysilicon layer. For example, the second plate layer80b2may be formed of a polysilicon layer having N-type conductivity.

The first plate layer80b1may be formed of a material capable of increasing adhesion between the second plate layer80b2and the pattern portions70b, or improving electrical characteristics by lowering resistance between the second plate layer80b2and the pattern portions70b. For example, the first plate layer80b1may include metal silicide such as WSi or TiSi and/or metal nitride such as TiN or TiSiN.

In a modified example, referring toFIG. 9C, a second substrate60cmay include pattern portions70cand a plate portion80con the pattern portions70c, while the pattern portions70cand the plate portion80cmay have an integrated structure. For example, the pattern portions70cand the plate portion80cmay be formed of a semiconductor layer. For example, the pattern portions70cand the plate portion80cmay be formed of a polysilicon layer having N-type conductivity or P-type conductivity.

In a modified example, referring toFIG. 10A, a second substrate60dmay include pattern portions70dand a plate portion80don the pattern portions70d. The plate portion80dmay include a first plate layer80d1and a second plate layer80d2on the first plate layer80d1.

The first plate layer80d1may have an integrated structure with the pattern portions70d. Thus, the first plate layer80d1and the pattern portions70dmay be continuously connected to each other without boundaries and may be formed of the same material.

In an example, the first plate layer80d1and the pattern portions70dmay be formed of an insulating material, for example, silicon nitride.

In another example, the first plate layer80d1and the pattern portions70dmay be formed of a conductive material, for example, doped silicon or a metal material such as tungsten.

The second plate layer80d2may be a semiconductor layer. For example, the second plate layer80d2may be formed of a polysilicon layer having N-type conductivity or P-type conductivity.

In a modified example, referring toFIG. 10B, a second substrate60emay include pattern portions70eand a plate portion80eon the pattern portions70e. The plate portion80emay include a first plate layer80e1and a second plate layer80e2on the first plate layer80e1.

The first plate layer80e1may have an integrated structure with the pattern portions70e. For example, the first plate layer80e1and the pattern portions70emay be formed of a conductive material.

The second plate layer80e2may be formed of a semiconductor layer. For example, the second plate layer80e2may be formed of a semiconductor layer having N-type conductivity, for example, polysilicon.

The second substrate60emay further include a conductive barrier layer65, extended between the first plate layer80e1and the lower structure50while covering a side surface and a bottom surface of the pattern portions70e. The conductive barrier layer65may be formed of a conductive material such as Ti/TiN, or the like.

In a modified example, referring toFIG. 10C, a second substrate60fmay include pattern portions70f, a plate portion80fon the pattern portions70f, and a barrier layer65extended between the plate portion80fand the lower structure50while covering a side surface and a bottom surface of the pattern portions70f.

The plate portion80fmay include a first plate layer80f1, a second plate layer80f2on the first plate layer80f1, and an additional conductive layer81between the first plate layer80f1and the second plate layer80f2.

The first plate layer80f1and the pattern portions70fmay have an integrated structure. For example, the first plate layer80f1and the pattern portions70fmay be formed of a conductive material such as tungsten. The second plate layer80f2may be formed of a semiconductor layer. The additional conductive layer81may be formed of a material capable of increasing adhesion between the first plate layer80f1and the second plate layer80f2, or improving electrical characteristics by lowering resistance between the first plate layer80f1and the second plate layer80f2. For example, the additional conductive layer81may include one or two or more among metal silicide such as WSi or TiSi, metal nitride such as WN, TiN, or TiSiN, and metal such as Ti.

In a modified example, referring toFIG. 11A, a second substrate60gmay include pattern portions70gand a plate portion80gon the pattern portions70g. Each of the pattern portions70gmay include a first pattern portion70g1and a second pattern portion70g2on the first pattern portion70g1.

The plate portion80gmay have an integrated structure, continuously connected to the second pattern portion70g2without boundaries. Thus, the plate portion80gand the second pattern portion70g2may be formed of the same material, for example, a semiconductor layer. The plate portion80gmay be formed of a semiconductor layer having N-type conductivity or P-type conductivity.

In an example, the first pattern portion70g1may be formed of an insulating material, for example, silicon nitride.

In another example, the first pattern portion70g1may be formed of a conductive material, for example, metal nitride such as TiN and/or metal such as W.

In a modified example, referring toFIG. 11B, a second substrate60hmay include pattern portions70hand a plate portion80hon the pattern portions70h. Each of the pattern portions70hmay include a first pattern portion70h1and a second pattern portion70h2on the first pattern portion70h1.

The second substrate60hmay further include a barrier layer64covering a side surface and a bottom surface of the first pattern portion70h1.

The plate portion80hmay have an integrated structure, continuously connected to the second pattern portion70h2without boundaries. The plate portion80gmay be formed of a semiconductor layer having N-type conductivity or P-type conductivity.

The first pattern portion70h1may be formed of metal such as W, and the barrier layer64may be formed of a conductive material such as Ti/TiN.

In a modified example, referring toFIG. 11C, a second substrate60imay include pattern portions70iand a plate portion80ion the pattern portions70i. Each of the pattern portions70imay include a first pattern portion70i1and a second pattern portion70i2on the first pattern portion70i1.

The plate portion80imay have an integrated structure, continuously connected to the second pattern portion70i2without boundaries. The plate portion80imay be formed of a semiconductor layer having N-type conductivity or P-type conductivity.

The second substrate60imay further include a barrier layer64covering a side surface and a bottom surface of the first pattern portion70i1. The barrier layer64may be formed of a conductive material such as Ti/TiN, or the like.

The second substrate60imay further include an additional conductive layer75, extended between the plate portion80iand the lower structure50while covering a side surface and a bottom surface of the second pattern portion70i2. The additional conductive layer75may include one or two or more among metal silicide such as WSi or TiSi, metal nitride such as WN, TiN, or TiSiN, and metal such as Ti.

In a modified example, referring toFIG. 12A, as described above, the second substrate60may include the pattern portions70and the plate portion80on the pattern portions70.

The third interlayer insulating layer45of the lower structure50may include a lower insulating portion45aand an upper insulating portion45b. The lower insulating portion45amay be disposed below a lower surface of the pattern portions70, and the upper insulating portion45bmay be between side surfaces of the pattern portions70.

In a modified example, referring toFIG. 12B, a second substrate60jmay include pattern portions70, the plate portion80on the pattern portions70, and barrier layers64′ covering a lower surface of the pattern portions70.

The third interlayer insulating layer45of the lower structure50may include a lower insulating portion45aand an upper insulating portion45b. The upper insulating portion45bmay cover side surfaces of the barrier layers64′ and the pattern portions70, sequentially stacked, and the lower insulating portion45amay be disposed below the barrier layers64′.

Next, with reference toFIG. 13, a modified example of a three-dimensional semiconductor device according to an example embodiment will be described.

Referring toFIG. 13, as described above, a lower structure50may be on a first substrate10, and a second substrate60kmay be on the lower structure50. The first substrate10may be a semiconductor substrate, and the lower structure50may include the peripheral transistor PTR, the peripheral wirings30and40, and the first to third lower insulating layers25,35, and45, described above. On the second substrate60k, the stacked structure170, the vertical structures120, and the bit lines195, described with reference toFIGS. 3A to 5, may be disposed.

The second substrate60kmay include pattern portions70kand a plate portion80k.

In an example, the plate portion80kmay cover an upper surface and a side surface of the pattern portions70k.

In an example, the plate portion80kmay include a polycrystalline semiconductor layer. For example, the plate portion80kmay be formed of a polysilicon layer having N-type conductivity or P-type conductivity.

In an example, the pattern portions70kmay be formed of an insulating material, for example, silicon nitride. In another example, the pattern portions70kmay include a conductive material, for example, a metal nitride such as TiN and/or a metal such as W.

As described above, various modified examples of the pattern portions70kand the plate portion80k, covering an upper surface and a side surface of the pattern portions70k, will be described with reference toFIGS. 14A and 14B.FIGS. 14A to 14Bare partially enlarged cross-sectional views illustrating an enlarged region indicated by ‘A’ inFIG. 13.

In a modified example, referring toFIG. 14A, a second substrate60lmay include pattern portions70land a plate portion80l. The second substrate60lmay further include barrier layers66disposed below the pattern portions70l. The plate portion80lmay cover an upper surface of the pattern portions70lwhile covering side surfaces of the barrier layers66and the pattern portions70l, sequentially stacked. The barrier layers66may be formed of a conductive material such as Ti/TiN, or the like.

In a modified example, referring toFIG. 14B, a second substrate60mmay include pattern portions70mand a plate portion80m. The second substrate60mmay further include barrier layers66disposed below the pattern portions70m, and an additional conductive layer76interposed between the pattern portions70mand the plate portion80mand extended between the plate portion80mand the lower structure50. The additional conductive layer76may include one or two or more among a metal silicide such as WSi or TiSi, a metal nitride such as WN, TiN, or TiSiN, and a metal such as Ti.

Next, with reference toFIGS. 15 and 16, modified examples of a three-dimensional semiconductor device according to an example embodiment will be described.FIGS. 15 and 16are schematic cross-sectional views illustrating a region taken along line I-I′ ofFIGS. 3A and 3B.

In a modified example, referring toFIG. 15, the lower structure50may be on the first substrate10, described above. A second substrate260a, including pattern portions270aand a plate portion280aconnected to the pattern portions270awhile covering an upper surface of the pattern portions270a, may be on the lower structure50.

The second substrate260amay be the same as the second substrate60described with reference toFIGS. 3A to 5. Further, the second substrate260amay be modified as second substrates60ato60jaccording to various modified examples, described with reference toFIGS. 9A to 12B. Thus, the second substrate260amay be understood to be the same as those described with reference toFIGS. 3A to 12B, so a detailed description thereof will not be repeated.

A stacked structure270may be on the second substrate260a. The stacked structure270may include interlayer insulating layers210and horizontal conductive patterns260, alternately and repeatedly stacked.

A first capping insulating layer250and a second capping insulating layer285, sequentially stacked, may be on the stacked structure270. A separation structure275may be disposed in a separation trench255, passing through the first capping insulating layer250and the stacked structure270. The separation structure275may be formed of an insulating material such as silicon oxide, or the like.

Vertical structures220v, passing through the stacked structure270, may be provided.

Each of the vertical structures220vmay include an insulating core pattern245passing through the stacked structure270, a channel semiconductor layer240surrounding an outer side surface of the insulating core pattern245, a gate dielectric structure230surrounding an outer side surface of the channel semiconductor layer240, and a pad pattern247on the channel semiconductor layer240and the insulating core pattern245. The channel semiconductor layer240, the insulating core pattern245, and the pad pattern247may be formed of a material the same as that of the channel semiconductor layer140, the insulating core pattern145, and the pad pattern147, described with reference withFIG. 7. In an example, the gate dielectric structure230may be formed of a material and a structure, the same as the gate dielectric structure130, described with reference toFIG. 7.

The vertical structures220vmay include a first vertical structure220v1and a second vertical structure220v2, located on both sides of the separation structure275.

A horizontal connection structure220h, extended from the first vertical structure220v1and the second vertical structure220v2and disposed in the plate portion280aof the second substrate260abelow the separation structure275, may be provided. The gate dielectric structure230, the channel semiconductor layer240, and the insulating core pattern245, of the first vertical structure220v1and the second vertical structure220v2, are extended from the first vertical structure220v1and the second vertical structure220v2, downwardly of the separation structure275, and thus a horizontal connection structure220hmay be provided.

The plate portion280amay be formed of a semiconductor layer having N-type conductivity, for example, polysilicon having N-type conductivity. The plate portion280amay be a back gate electrode.

A source line284may be on the first capping insulating layer250. A source contact plug282, electrically connecting the source line284to the second vertical structure220v2, may be between the source line284and the second vertical structure220v2.

A bit line295may be on the second capping insulating layer285. A bit line contact plug290, electrically connecting the bit line295to the first vertical structure220v1, may be between the bit line295and the first vertical structure220v1.

In a modified example, referring toFIG. 16, the lower structure50may be on the first substrate10, described above. A second substrate260b, including pattern portions270band a plate portion280bconnected to the pattern portions270bwhile covering an upper surface and a side surface of the pattern portions270b, may be on the lower structure50.

The second substrate260bmay be the same as the second substrate60kdescribed with reference toFIG. 13. Further, the second substrate260bmay be modified as second substrates60land60maccording to various modified examples, described with reference toFIGS. 14A and 14B. Thus, the second substrate260bmay be understood to be the same as those described with reference toFIGS. 13 to 14B, so a detailed description thereof will not be repeated.

On the second substrate260b, as described with reference toFIG. 15, the stacked structure270, the separation structure275, the vertical structures220v, the source line284, and the bit line295may be disposed.

Referring again toFIGS. 3A to 5, as described above, in an example, the second substrate60may include pattern portions70extended in a first direction X, the connection portion62connecting the pattern portions70and having an integrated structure with the pattern portions70, and the plate portion80overlapping the pattern portions70and the connection portion62.

In an example, the pattern portions70and the separation structures175may have linear shapes, extended in the same direction, for example, the first direction X. Next, referring toFIGS. 17 to 21, various modified examples of the second substrate60will be described. Hereinafter, when described with reference toFIGS. 17 to 21, a structure on the second substrate may be the same as that described with reference toFIGS. 3A to 5. Thus, modified examples of the second substrate inFIG. 3Amay be described with reference toFIGS. 17 to 21, while a structure on a second substrate, which may be modified, may be described with reference toFIGS. 3B to 5.

In a modified example, referring toFIG. 17, withFIGS. 3B to 5, a second substrate360amay include pattern portions370ahaving a linear shape, a connection portion362aformed integrally with the pattern portions370awhile connecting the pattern portions370a, and a plate portion380acovering the pattern portions370aand the connection portion362a.

The pattern portions370aand the separation structures (175ofFIG. 3B) may have linear shapes extended in directions perpendicular to each, other. For example, the separation structure175may have a linear shape extended in a first direction X, while the pattern portions70may have a linear shape extended in a second direction Y, perpendicular to the first direction X. At least one of the pattern portions370ahas a linear shape extended in the first direction X. At least one of the horizontal conductive patterns (160ofFIG. 4) has a linear shape extended in the second direction Y. The pattern portions370aand the horizontal conductive patterns (160ofFIG. 4) may have linear shapes extended in directions perpendicular to each other.

In a modified example, referring toFIG. 18, withFIGS. 3B to 5, a second substrate360bmay include pattern portions370bhaving a linear shape, a connection portion362bformed integrally with the pattern portions370bwhile connecting the pattern portions370b, and a plate portion380bcovering the pattern portions370band the connection portion362b.

The pattern portions370band the separation structures (175ofFIG. 3B) may have linear shapes crossing each other diagonally.

In a modified example, referring toFIG. 19, withFIGS. 3B to 5, a second substrate360cmay include pattern portions370chaving a linear shape, a connection portion362cformed integrally with the pattern portions370cwhile connecting the pattern portions370c, and a plate portion380ccovering the pattern portions370cand the connection portion362c.

The connection portion (362aofFIG. 17), described above, may have a linear shape, continuously connected in one direction. In another example, as illustrated inFIG. 19, the connection portion362cmay have a bar shape extended in a direction perpendicular to the pattern portions370c. The connection portion362chaving a bar shape, described above, may be provided as a plurality of connection portions, and the plurality of connection portions362cmay be spaced apart from each other in the first direction X, and may be spaced apart from each other in the second direction Y.

In a modified example, referring toFIG. 20, withFIGS. 3B to 5, a second substrate360dmay include pattern portions370dhaving a linear shape, a connection portion362dformed integrally with the pattern portions370dwhile connecting the pattern portions370d, and a plate portion380dcovering the pattern portions370dand the connection portion362d. The pattern portions370dand the connection portion362dmay be arranged in a mesh shape.

In a modified example, referring toFIG. 21, withFIGS. 3B to 5, a second substrate360emay include pattern portions370e, a connection portion362eformed integrally with the pattern portions370ewhile connecting the pattern portions370e, and a plate portion380ecovering the pattern portions370eand the connection portion362e.

The pattern portions370ato370c, described above, may have a straight line shape. In another example, as illustrated inFIG. 21, the pattern portions370emay have a bent shape or a curved shape.

Next, with reference toFIG. 22, a modified example of a three-dimensional semiconductor device according to an example embodiment will be described.FIG. 22is a cross-sectional view illustrating a region taken along line II-II′ ofFIGS. 3A and 3B.

Referring toFIG. 22, withFIGS. 3A, 3B, and 4, as described with reference toFIGS. 3A to 5, the lower structure50may be on the first substrate10, and the second substrate60may be on the lower structure50. As described with reference toFIGS. 3A to 5, the lower structure50may include the peripheral transistor PTR, the peripheral wirings30and40, and the first to third lower insulating layers25,35, and45. Moreover, on the second substrate60, the stacked structure170, the upper insulating layer115, the first second capping insulating layer150and the second capping insulating layer185, the vertical structures120, the gate contact structures180, the bit line contact plugs190, the gate contact plugs192, the peripheral contact plug194, the gate connection wirings196, and the bit lines195, described with reference toFIGS. 3A to 5, may be disposed.

In an example, the plate portion80may include a semiconductor layer having N-type conductivity. Thus, the plate portion80may serve as the common source line CSL, described with reference toFIGS. 1A and 1B. A source contact structure183may be on the plate portion80, which may be the common source line (CSL ofFIGS. 1A and 1B) described above. A source contact plug193may be on the source contact structure183. A peripheral connection wiring198′, electrically connected to the source contact plug193and the peripheral contact plug194simultaneously, may be on the second capping insulating layer185.

Thus, the plate portion80may be electrically connected to the peripheral wirings40, configuring a peripheral circuit in the lower structure50below the second substrate60, through the peripheral connection wiring198′. A modified example, in which the plate portion80and the peripheral wirings40, configuring a peripheral circuit in the lower structure50, are electrically connected to each other will be described with reference toFIGS. 23 and 24.

FIGS. 23 and 24are cross-sectional views illustrating a region taken along line II-II′ ofFIGS. 3A and 3B.

In a modified example, referring toFIG. 23, the plate portion80of the second substrate60, described above, may be a semiconductor layer having N-type conductivity, while the pattern portions70may be formed of a conductive material (e.g., TiN, W, doped polysilicon, or the like). A contact plug55, interposed between the pattern portions70of the second substrate60and the peripheral pad region40P′ of the peripheral wirings30and40, and electrically connecting the pattern portions70to the peripheral pad region40P′ of the peripheral wirings30and40, may be provided. Thus, the plate portion80of the second substrate60may include a semiconductor layer having N-type conductivity, and the plate portion80may serve as the common source line CSL, described with reference toFIGS. 1A and 1B. The plate portion80may be electrically connected to the peripheral wirings40, configuring a peripheral circuit in the lower structure50below the second substrate60, through the contact plug55.

In a modified example, referring toFIG. 24, the plate portion80of the second substrate60, described above, may be a semiconductor layer having N-type conductivity or P-type conductivity, or including a portion having N-type conductivity or a portion having P-type conductivity, while the pattern portions70may be formed of a conductive material (e.g., TiN, W, doped polysilicon, or the like) or an insulating material (e.g., SiN, or the like). In this case, the separation structure175may include a separation core pattern178, formed of a conductive material, and a separation spacer176, on a side surface of the separation core pattern178and separating the separation core pattern178from the stacked structure170. The separation spacer176may be formed of an insulating material. The separation core pattern178, in the separation structure175, may be electrically connected to a semiconductor layer having N-type conductivity of the plate portion80, which may be the common source line CSL illustrated inFIGS. 1A and 1B.

Next, with reference toFIGS. 25 to 29, an example of a method for forming a three-dimensional semiconductor device according to an example embodiment will be described.

Referring toFIG. 25, a peripheral transistor PTR may be formed on a first substrate10. The first substrate10may be a single crystal semiconductor substrate. Forming the peripheral transistor PTR may include forming an isolation region15idefining a peripheral active region15aon the first substrate10, forming a peripheral gate PG on the peripheral active region15a, and forming a peripheral source/drain region S/D in the peripheral active region15aon both sides of the peripheral gate PG.

A first lower insulating layer25covering the peripheral transistor PTR may be formed on the first substrate10. A first peripheral wiring30, electrically connected to the peripheral transistor PTR, may be formed in the first lower insulating layer25. A second lower insulating layer35may be formed on the first lower insulating layer25and the first peripheral wiring30. A second peripheral wiring40, which may be electrically connected to the first peripheral wiring30, may be formed in the second lower insulating layer35. A third lower insulating layer45may be formed on the second lower insulating layer35. The peripheral transistor PTR, the first peripheral wiring30and the second peripheral wiring40, as well as the first to third lower insulating layers25,35, and45may form a lower structure50. The third lower insulating layer45is patterned, and thus recess regions45rmay be formed.

Referring toFIG. 27, pattern portions70may be formed in the recess regions45r. A plate portion80may be formed on the pattern portions70and the third lower insulating layer45. The pattern portions70and the plate portion80may form a second substrate60.

Forming the second substrate60may include forming a first material layer covering the third lower insulating layer45while filling the recess regions45r, exposing the third lower insulating layer45by flattening the first material layer, and then forming the plate portion80on the third insulating layer45by performing a deposition process.

In one example, the first material layer may be formed of an insulating material.

In another example, the first material layer may be formed of a metallic material.

In another example, the first material layer may be formed of a doped semiconductor layer.

In another example, before the first material layer is formed, forming a conductive barrier layer (64ofFIG. 9A) such as Ti/TiN, or the like, may be further included.

In one example, the plate portion80may include a semiconductor layer. For example, the plate portion80may include an N-type semiconductor layer or a P-type semiconductor layer.

In another example, the plate portion80may be provided as a first plate layer (80b1ofFIG. 9B) and a second plate layer (80b2ofFIG. 9B), sequentially stacked.

In another example, the plate portion80and the pattern portions70may have an integrated structure.

In another example, forming the second substrate60may include forming a first material layer covering the third lower insulating layer45while filling the recess regions45r, flattening the first material layer to have a constant thickness on the third lower insulating layer45, and forming a second material layer on the first material layer. Thus, the first material layer may remain on the third lower insulating layer45while filling the recess regions45r. Thus, the first material layer, remaining in the recess regions45r, may form pattern portions (70dofFIG. 10A), a first material layer, remaining on the third lower insulating layer45, may form a first plate layer (80d1ofFIG. 10A) of the plate portion80, and the second material layer may form a second plate layer (80d2ofFIG. 10A) of the plate portion80.

In another example, when the second substrate60, described above, is provided, before a first material layer covering the third lower insulating layer45while filling the recess regions45ris provided, forming a barrier layer (65ofFIG. 10B) may be further included. Moreover, before the second material layer is formed on a first material layer remaining on the third lower insulating layer45, forming an additional conductive layer (81ofFIG. 10C) may be further included.

In another example, after a first material layer partially filling the recess regions45ris provided, forming the second substrate60may include forming a second material layer covering the third lower insulating layer45while filling a remaining region of the recess regions45r.

In another example, forming the second substrate60may include forming pattern portions (70kofFIG. 13) using a deposition and etching process on the lower structure50, and forming the plate portion (80kofFIG. 13), covering a side surface and an upper surface of the pattern portions (70kofFIG. 13).

Referring toFIG. 28, a mold structure105may be formed on the second substrate60. The mold structure105may include interlayer insulating layers110and mold layers116, alternately and repeatedly stacked. The interlayer insulating layers110may be formed of silicon oxide, while the mold layers116may be formed of a material having etch selectivity with respect to the interlayer insulating layers110. For example, the mold layers116may be formed of silicon nitride.

Vertical structures120, passing through the mold structure105, may be provided.

In an example, the vertical structures120may be the vertical structure described with reference toFIG. 7. For example, forming the vertical structures120may include forming a hole passing through the mold structure105and exposing the plate portion80of the second substrate60, forming a semiconductor pattern (125ofFIG. 7) epitaxially grown from the plate portion80exposed by the hole, forming a gate dielectric structure (130ofFIG. 7) on a side wall of the hole on the semiconductor pattern (125ofFIG. 7), forming a channel semiconductor layer (140ofFIG. 7) in contact with the semiconductor pattern (125ofFIG. 7) while covering the gate dielectric structure130, forming a core pattern (145ofFIG. 7) partially filling the hole on the channel semiconductor layer140, and forming a pad pattern147on the channel semiconductor layer140and the core pattern (145ofFIG. 7).

A first capping insulating layer150covering the vertical structures120may be formed on the mold structure105. A separation trench155, passing through the first capping insulating layer150and the mold structure105, may be provided.

Referring toFIG. 29, the mold layers116(seeFIG. 28), exposed by the separation trench155, are removed to form empty spaces, and horizontal conductive patterns160may be formed in the empty spaces. Then, a separation structure175, filling the separation trench155, may be provided.

Referring again toFIGS. 3A to 5, gate contact structures180of pad regions P of the horizontal conductive patterns160and a peripheral contact structure182on a peripheral contact region40P of the second peripheral wirings40may be provided. Then, after a second capping insulating layer185is provided, contact plugs190,192, and194are formed, and bit lines195, gate connection wirings196, and a peripheral connection wiring198may be provided on the contact plugs190,192, and194.

In an example embodiment, the second substrate60may include the pattern portions70and the plate portion80. The plate portion80may include a semiconductor layer, and the pattern portions70may be formed of a conductor having electrical resistance lower than that of the semiconductor layer of the plate portion80. Thus, the pattern portions70may improve electrical characteristics of the second substrate60. For example, when the plate portion80includes a polysilicon layer having N-type conductivity, which may serve as a common source line CSL, the pattern portions70, which may be formed of tungsten, or the like, having electrical resistance lower than that of the polysilicon layer, may help to improve electrical characteristics of the common source line CSL.

In an example embodiment, the second substrate60may include the pattern portions70and the plate portion80. When a three-dimensional semiconductor device according to an example embodiment is provided in the form of a semiconductor chip, or a semiconductor process is carried out in the form of a semiconductor wafer, the pattern portions70may help to prevent warpage of a three-dimensional semiconductor device, including the second substrate60. For example, in the three-dimensional semiconductor device as illustrated inFIG. 2, when stress is generated in any one direction or three-dimensionally by the upper structure (100ofFIG. 2) disposed above the second substrate60, the pattern portions70of the second substrate60may help to prevent a three-dimensional semiconductor device from warping by the upper structure100. The pattern portions70may be selected and provided in the form of one among various flat shapes as illustrated inFIGS. 3A, and 17 to 21, according to a shape of warpage generated by the upper structure100.

Thus, the pattern portions70and various pattern portions70ato70m,270aand270b, as well as370ato370eto be modified may be referred to as a ‘warpage preventing pattern’, ‘stress pattern’ or ‘supporting pattern.’

By way of summation and review, to improve a degree of integration of a semiconductor device, a peripheral circuit may be on a lower substrate and an upper substrate, and a memory array region may be on the upper substrate.

As described above, a peripheral circuit, an upper substrate, and a memory cell array may be sequentially disposed in a vertical direction on the lower substrate, so warpage of a semiconductor device may be reduced or prevented.

As described above, embodiments may provide a three-dimensional semiconductor device including a lower structure on a first substrate, a second substrate on the lower structure, and an upper structure on the second substrate. The lower structure may include a peripheral circuit, and the upper structure may include a memory cell array. Thus, embodiments may provide a three-dimensional semiconductor device with an improved degree of integration.

Embodiments may provide a three-dimensional semiconductor device capable of preventing or significantly reducing warpage. The second substrate may include pattern portions and a plate portion covering the pattern portions. The plate portion may include a semiconductor layer. The pattern portions may prevent warpage of a three-dimensional semiconductor device, or may significantly reduce warpage. As described above, a three-dimensional semiconductor device, capable of preventing warpage or significantly reducing warpage, may be provided, so a defect generated by the warpage may be reduced. Thus, productivity may be improved.