SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes bonding a first wafer with a second wafer. The second wafer includes a substrate, an isolation structure in the substrate, a transistor on the substrate, and a interconnect structure over the second transistor. A first etching process is performed to form a first via opening and a second via opening in the substrate. The second via opening extends to the isolation structure, and the second via opening is deeper than the first via opening. A second etching process is performed such that the first via opening exposes the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure, and the second via opening penetrates the isolation structure. A first via is formed in the first via opening and a second via is formed in the second via opening.

BACKGROUND

Field of Disclosure

The present disclosure relates to a semiconductor device and a manufacturing method thereof.

Description of Related Art

The through substrate vias may be used to connect a semiconductor chip to another semiconductor chip or to a package substrate. For example, through substrate vias may be used in various semiconductor devices such as an image sensor, a stacked memory, or an interposer. A connection method using through substrate vias may be advantageous in terms of speed, power consumption, and/or miniaturization compared to a connection method using wire bonding.

SUMMARY

Some embodiments of the present disclosure provides a method of manufacturing a semiconductor device including bonding a first wafer with a second wafer. The second wafer includes a substrate, an isolation structure embedded in the substrate, a transistor on the substrate, and a interconnect structure over the transistor. A first etching process is performed to form a first via opening and a second via opening in the substrate. The second via opening extends to the isolation structure, the transistor is between the first via opening and the second via opening, and the second via opening is deeper than the first via opening. A second etching process is performed such that the first via opening extends to a bottom of the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure, and the second via opening penetrates the isolation structure. A first via is formed in the first via opening and a second via is formed in the second via opening.

In some embodiments, the second via opening is wider than the first via opening.

In some embodiments, before performing the first etching process, the method further includes grinding the substrate of the second wafer at a backside surface of the substrate of the second wafer, and forming a dielectric layer at the backside surface of the substrate.

In some embodiments, the method further includes forming a photoresist layer at a backside surface of the substrate of the second wafer. The photoresist layer includes a first opening and a second opening, and the first opening is narrower than the second opening. The first etching process is performed to form the first via opening connecting the first opening of the photoresist layer and the second via opening connecting the second opening of the photoresist layer.

In some embodiments, the method o further including forming a liner layer along sidewalls of the first via opening and the second via opening after performing the third etching process and before forming the first via and the second via.

In some embodiments, forming the first via and the second via includes depositing a conductive material in the first via opening and the second via opening and over the second wafer, and planarizing the second wafer to remove an excess portion of the conductive material to form the first via and the second via.

In some embodiments, the first etching process etches the substrate faster than the isolation structure.

In some embodiments, the first etching process and the second etching process use the same etchant gas.

In some embodiments, a depth of the second via opening remains the same during the second etching process.

In some embodiments, performing the first etching process to form the first via opening includes forming the first via opening in the substrate by a photoresist layer having an opening, forming a passivation layer along sidewalls and a bottom surface of the first via opening, removing the passivation layer at the bottom surface of the first via opening, etching the bottom of the first via opening to deepen the first via opening, and repeating forming the passivation layer, removing the passivation layer at the bottom surface of the first via opening and etching the bottom of the first via opening until the bottom of the first via opening reached a predetermined level.

Some embodiments of the present disclosure provides a semiconductor device including a first wafer, a second wafer, a first via and a second via. The second wafer is bonded to the first wafer, and the second wafer includes a substrate, an isolation structure embedded in the substrate, a transistor between the substrate and the first wafer, and an interconnect structure between the transistor and the first wafer. The first via is in a central region of the second wafer and in contact with the interconnect structure. The second via is in a peripheral region of the second wafer and in contact with the interconnect structure, and the isolation structure partially surrounds the second via.

In some embodiments, the second via is wider than the first via.

In some embodiments, the first via includes a first portion and a second portion under the first portion, and the second portion is narrower than the first portion.

In some embodiments, a height of the second portion of the first via is greater than a height of a source/drain region of the second transistor.

In some embodiments, the semiconductor device further includes a liner layer wrapped around the second via.

In some embodiments, the liner layer is in contact with both the substrate and the isolation structure.

In some embodiments, the semiconductor device further includes a dielectric layer over the substrate and surrounding the first via and the second via.

Some embodiments of the present disclosure provide a semiconductor device, including a first wafer, a second wafer, a power via and a signal via. The second wafer is over the first wafer, and the second wafer includes a substrate, an isolation structure in the substrate, a first transistor and a second transistor adjacent the isolation structure, and an interconnect structure between the substrate and the first wafer. The power via penetrated the substrate and the isolation structure to the interconnect structure. The signal via penetrating the substrate to the interconnect structure, wherein the signal via is between the first transistor and the second transistor but spaced apart from the isolation structure.

In some embodiments, the signal via comprises a first portion and a second portion between the first portion and the interconnect structure, and the first portion is wider than the second portion.

In some embodiments, a top of the second portion is higher than a top of the isolation structure.

The present disclosure of is related to a method of controlling the etching rate difference of via openings with different width. For example, an isolation structure may be used as a etch stop layer for the via opening with greater width. Therefore, the etching time difference between the via openings with different width may be reduced. Moreover, the signal via in some embodiments has a narrow bottom portion. The transistors are less easily affected by the signal via, and the transistors may be arranged densely. Therefore, the number of transistors per area increases.

The manufacturing method of the semiconductor device in some embodiments of the present disclosure may control the etching rate difference of via openings with different width. Therefore, the etching time difference between the via openings with different width may be reduced. Moreover, the narrow second portion of the signal via makes the signal via affect transistors less.

DETAILED DESCRIPTION

The present disclosure is related to a method of controlling the etching rate difference of via openings with different width. Therefore, vias having different widths are formed in the semiconductor device, and vias having different widths may be used for different usage.

FIGS.1A-7,9,11-14illustrate cross-sectional views of intermediate stages in the manufacturing process of a semiconductor device in accordance with some embodiments of the present disclosure. Referring toFIG.1A, a first wafer100is provided. The first wafer100may include a substrate102, transistors104, a interconnect structure106, a dielectric layer108and bonding pads110. The substrate102may include any suitable materials, such as semiconductor materials (e.g. silicon). The transistors104are disposed on the substrate102, and the transistors104include source/drain regions105in the substrate102. The interconnect structure106are used to provide electrical interconnection between the transistors104and are made of conductive materials. The interconnect structure106is over the transistors104. In some embodiments, the interconnect structure106is a multi-layer structure include conductive vias and conductive lines. The conductive vias may connect the conductive lines in different level to form the interconnect structure106. The dielectric layer108covers the substrate102, the transistors104and the interconnect structure106to electrically isolate adjacent conductive vias and conductive lines in the interconnect structure106. The dielectric layer108may be made of any suitable material. In some embodiments, the dielectric layer108is made of SiO2, SiC, low-k materials, or the like. The bonding pads110may be disposed over the interconnect structure106, and the bonding pads110may be electrically connect to the interconnect structure106.

Referring toFIG.1B, a second wafer200is provided. The second wafer200may include a substrate202, transistors204, a interconnect structure206, a dielectric layer208, bonding pads210, and an isolation structure212. The transistors204are disposed in a central region R1of the substrate202, and the isolation structure212is embedded in a peripheral region R2of the substrate202. The term “central region” herein refers to the region where transistors204are densely formed, and the term “peripheral region” refers to the region surrounding the central region. The peripheral region R2is farther from the transistors204. The isolation structure212may be formed of any suitable dielectric material, such as SiO2, and material of the isolation structure212is different from the substrate202. The substrate202, the transistors204, the source/drain regions205, the interconnect structure206, the dielectric layer208and the bonding pads210are similar to or the same as the substrate102, the transistors104, the source/drain regions105the interconnect structure106, the dielectric layer108and the bonding pads110, respectively; therefore, detailed descriptions are not discussed herein.

Referring toFIG.2, a hybrid bonding process is performed, and the first wafer100is bonded with the second wafer200. During the hybrid bonding process, the second wafer200is flipped upside down and disposed over the first wafer100to form a semiconductor device. The front-side surface of the first wafer100is bonded with the front-side surface of the second wafer200such that the bonding pads110are bonded to the bonding pads210, respectively. Moreover, the dielectric layer108of the first wafer100is also bonded to the dielectric layer208of the second wafer200. After the first wafer100is bonded with the second wafer200, the isolation structure212is still in the peripheral region of the substrate202.

Referring toFIG.3, the substrate202of the second wafer200is grinded at a backside surface of the substrate202of the second wafer200. The substrate202may be grinded by any suitable method, such as chemical mechanical polish. Referring toFIG.4, a dielectric layer220is formed at the backside surface of the substrate202. In some embodiments, the dielectric layer220is formed of SiO2, SiN, SiCN, SiC, combinations thereof, or the like.

Referring toFIG.5, a photoresist layer PR is formed at the backside surface of the substrate202of the second wafer200. More specifically, a photoresist material is first disposed over the backside surface of the substrate202of the second wafer200. Subsequently, a photolithography process is performed to form the photoresist layer PR with patterns. The photoresist layer PR includes a first opening O1and a second opening O2, and the first opening O1is narrower than the second opening O2. The first opening O1is formed over the central region R1of the substrate202, but not directly over the transistors104and the transistors204. The second opening O2is formed over the peripheral region R2of the substrate202, and is directly over the isolation structure212. In some embodiments, the first openings O1may be arranged in an array. The first openings O1and the second opening O2expose the dielectric layer220.

Referring toFIG.6, the first opening O1and the second opening O2are extended into the dielectric layer220. More specifically, the dielectric layer220is etched by using the photoresist layer PR as a mask. The first opening O1and the second opening O2expose the substrate202of the second wafer200.

Referring toFIG.7, a first etching process is performed to form a first via opening V1and a second via opening V2in the substrate202. The second via opening V2extends to the isolation structure212, the transistor204is between the first via opening V1and the second via opening V2, and the second via opening V2is deeper than the first via opening V1. InFIG.7, a first portion V11of the first via opening V1is formed.

More specifically, the first etching process is performed by using the photoresist layer PR with the patterned dielectric layer220as a mask. Therefore, the first via opening V1connects to the first opening O1of the photoresist layer PR, and the second via opening V2connects to the second opening O2of the photoresist layer PR. Since the second opening O2is wider than the first opening01, the second via opening V2is wider than the first via opening V1. The width difference between the second via opening V2and the first via opening V1leads to loading effect during the first etching process, and the loading effect leads to the etching rate difference between the second via opening V2and the first via opening V1. Since the etching gas moves to the bottom of the wider opening more easily, the wider opening, such as second via opening V2, is etched at a faster etching rate than the narrower opening, such as first via opening V1. When the bottom of the second via opening V2reaches and exposes the isolation structure212, the bottom of the first via opening V1is higher than the second via opening V2. That is, the first via opening V1is shallower than the second via opening V2. The isolation structure212is made of the material different from the substrate202. Therefore, the isolation structure212is able to stop the etching of the second via opening V2, while the etching of the first via opening V1continues until the bottom of the first via opening V1reaches a predetermined level. In other words, the first etching process etches the substrate202faster than the isolation structure212. The first via opening V1does not expose the substrate202during the first etching process.

FIGS.8A-8Eillustrate a detailed mechanism of the first etching process in region M inFIG.7. It is noted that, althoughFIGS.8A-8Etake the first via opening V1as example, the second via opening V2is also formed by the similar method. Referring toFIG.8A and8B, the substrate202is etched through the opening O1of the photoresist layer PR to form the first via opening V1in the substrate202. The substrate202is etched by an etchant gas, such as SF6. The duration of the process inFIG.8Bis short and the depth of the first via opening V1inFIG.8Bis shallow. However, the first etching process also laterally etches the substrate202, such that the width of the first via opening V1is wider than the first opening O1. Referring toFIG.8C, subsequently, a passivation layer PL1is formed along the sidewall of the dielectric layer220and the photoresist layer PR, and the sidewall and the bottom surface of the first via opening V1. The passivation layer PL is formed by using a deposition gas different from the etching gas used inFIG.8B, and the chemicals in the deposition gas react to each other to form a polymer liner along the sidewall of the first via opening V1, the dielectric layer220and the photoresist layer PR. The polymer liner layer may be the passivation layer PL1. In some embodiments, the deposition gas may be fluorine-containing gas, such as C4F8, or C5HF7. Referring toFIG.8D, the passivation layer PL1at the bottom surface of the first via opening V1and the top of the photoresist layer PR is removed by the etching gas used inFIG.8B. Subsequently, the substrate202exposed at the bottom surface of the first via opening V1is etched and the first via opening V1is deepened. The etching process inFIG.8Eis same as that inFIG.8B. Forming the passivation layer PL1, removing the passivation layer PL1at the bottom surface of the first via opening V1and etching the bottom surface of the first via opening V1are repeated until the bottom of the first via opening V1reaches a predetermined level. The passivation layer PL1inFIG.8Cmay serve as a mask at the vertical sidewall of the first via opening V1, such that the first via opening V1inFIG.8Dis etched vertically but not horizontally.

Referring toFIG.9, a second etching process is performed such that the first via opening V1extends to a bottom of the substrate202. InFIG.9, a second portion V12of the first via opening V1is formed. The second portion V12of the first via opening V1is narrower than the first portion V11of the first via opening V1, and the reason will be explained inFIGS.10A-10D. That is, the second via opening V2is wider than the first portion V11of the first via opening V1, and the first portion V11of the first via opening V1is wider than the second portion V12of the first via opening V1. The narrow second portion V12of the first via opening V1may reduce the disturbance caused by the via subsequently formed in the first via opening V1to the transistors204, since the lateral distance between the transistors204and the first via opening V1increases. If the first via opening V1is formed as shown inFIG.9, the formation of the first portion V11may be used to reduce the loading effect during the second etching process. For example, if the width of the first via opening V1is entirely the same as the second portion V12of the first via opening V1, the width difference between the first via opening V1and the second via opening V2is so significant, such that the loading effect will be severe. If the width of the first via opening V1is entirely the same as the first portion V11of the first via opening V1, the distance between the subsequently formed via and the transistors204is small. The subsequently formed via may easily affect the transistors204accordingly. The first etching process and the second etching process use the same etchant gas. Therefore, the depth of the second via opening V2remains the same during the second etching process.

FIGS.10A-10Dillustrate a detailed mechanism of the first etching process in region N inFIG.9. Referring toFIG.10A, the substrate202is etched by the passivation layer PL along the sidewall of the first portion V11of the first via opening V1to form the second portion V12of the first via opening V1in the substrate202. The substrate202may be etched by the etchant gas used inFIG.8B. The duration of the process inFIG.10Ais short and the depth of the via opening V2inFIG.10Ais shallow. Referring toFIG.10B, subsequently, a passivation layer PL2is formed along the sidewall of the dielectric layer220and the photoresist layer PR, and the sidewall and the bottom surface of the first via opening V1. The passivation layer PL2may be formed by using the deposition gas used inFIG.8C. The duration of deposition of the passivation layer PL2is longer, such that the passivation layer PL2is thicker than the passivation layer PL1. Referring toFIG.10C, the passivation layer PL2at the bottom surface of the first via opening V1is removed by the etching gas used inFIG.10A. Subsequently, the substrate202exposed at the bottom surface of the first via opening V1is etched and the first via opening V1is deepened. The passivation layer PL2in may serve as a mask at the vertical sidewall of the first via opening V1, such that the first via opening V1is etched vertically but not horizontally. Since the passivation layer PL2is thicker than the passivation layer PL1, the width of the second portion V12of the first via opening V1become narrower. The etching process inFIG.10Dis same as that inFIG.10A. Forming the passivation layer PL2, removing the passivation layer PL2at the bottom surface of the first via opening V1and etching the bottom surface of the first via opening V1are repeated until the bottom of the first via opening V1reaches the bottom of the substrate202. Subsequently, the passivation layer PL2is removed. It is noted that althoughFIGS.8A-8EandFIGS.10A-10Dillustrate that the sidewall of the first via opening V1is scallop-shaped, the sidewalls of the first via opening V1and the second via opening V2may also be straight. Further, the overall sidewall of the first via opening V1and the overall sidewall of the second via opening V2may also be regarded as straight as shown inFIG.9.

Referring toFIG.11, a third etching process is performed such that the first via opening V1and the second via opening V2exposes the interconnect structure206. The second via opening V2penetrates the isolation structure212. Due to the existence of the isolation structure212, the difference between etching the first via opening V1and the second via opening V2is reduced. More specifically, the third etching process etches the second via opening V2at a faster rate due to the loading effect. However, the etching distance is greater for the second via opening V2. Therefore, the second via opening V2and the first via opening V2may reach the interconnect structure206substantially at the same time. Subsequently, the photoresist layer PR is stripped.

Referring toFIG.12, liner layers230are formed along the sidewalls of the first via opening V1and the second via opening V2after performing the third etching process. In some embodiments, a dielectric layer is first conformally along the sidewalls and the bottom of the first via opening V1and the second via opening V2, and the top surface of the dielectric layer220. Subsequently, the dielectric layer at the bottom of the first via opening V1and the second via opening V2, and the top surface of the dielectric layer220is removed to form the liner layers230along the sidewalls of the first via opening V1and the second via opening V2. In some embodiments, the liner layers230may be any made of any suitable dielectric material, such as SiO2, and the liner layers230may be formed by CVD, or ALD.

Referring toFIGS.13-14, a first via250is formed in the first via opening V1and a second via260is formed in the second via opening V2. More specifically, conductive materials240are deposited in the first via opening V1and the second via opening V2and over the second wafer200. The conductive materials240may include barrier layers, seed layers, metal layers deposited in sequence on the sidewalls of the first via opening V1and the second via opening V2. The conductive materials240may be made of TiN, TaN, Ta, Ti, Cu, combinations thereof, or the like. Subsequently, the second wafer200is planarized to remove an excess portion of the conductive materials240to form the first via250and the second via260.

The resulting semiconductor device is illustrated inFIG.14, andFIG.15illustrates a top view of a semiconductor device according to some embodiments of the present disclosure.FIG.14is a cross-section view taken along the line A-A inFIG.15. The semiconductor device includes the first wafer100, the second wafer200, the first via250and the second via260. The second wafer200is bonded to the first wafer100, and the second wafer200includes the substrate202, the isolation structure212embedded in the substrate202, the transistors204between the substrate202and the first wafer100, and the interconnect structure206between the transistors204and the first wafer100. The transistors204are adjacent the isolation structure212. That is, one of the transistors204is between the isolation structure212and another transistor204. The first via250is in the central region R1of the second wafer200and in contact with the interconnect structure206. The second via260is in a peripheral region R2of the second wafer200and in contact with the interconnect structure206. The isolation structure212partially surrounds the second via260. InFIG.15, the first vias250may be arranged in an array, and the second vias260are arranged at the peripheral region of the array.

The first via250is a signal via used for signal transmission, and is between the transistor204and transistors but spaced apart from the isolation structure212. The second via260is a power via used for power transmission (e.g., VDD and VSS), and penetrates the substrate202and the isolation structure212to the interconnect structure206. The second via260is wider than the first via250, and the first via250includes a first portion252and a second portion254under the first portion252. In other words, the second portion254is between the first portion252and the interconnect structure206, and the first portion252is wider than the second portion254. The second portion254is narrower than the first portion252. The narrower second portion254of the first via250may be spaced apart from the adjacent transistors204by a keep-out zone. If the distance between the first via250and the transistors204is less than the keep-out zone, the transistors204may be adversely affected by the first vias250. Therefore, the transistors204in some embodiments of the present disclosure are able to be arranged more densely, since the second portion254of the first via250is formed more narrowly. Moreover, a height of the second portion254of the first via250is greater than a height of the source/drain region205of the transistor204. Therefore, the wider first portion252of the first via250cannot adversely affect the transistors204. A top of the second portion254is also higher than a top of the isolation structure212.

The semiconductor device further includes liner layers230and the dielectric layer220. The liner layers230are wrapped around the first via250and the second via260, and the liner layers230are in contact with both the substrate202and the isolation structure212. The dielectric layer220is over the substrate202and surrounds the first via250and the second via260.

The manufacturing method of the semiconductor device in some embodiments of the present disclosure may control the etching rate difference of via openings with different width. For example, an isolation structure may be used as a etch stop layer for the via opening with greater width. Therefore, the etching time difference between the via openings with different width may be reduced. Moreover, the signal via in some embodiments has a narrow bottom portion. Due to the existence of the narrow bottom portion of the signal via, the transistors are less easily affected by the signal via. The transistors may be arranged densely. Therefore, the number of transistors per area increases.