Semiconductor device

A semiconductor device including a field effect transistor having a buffer layer subjected to lattice relaxation, a channel layer, and an electron supply layer formed in this order with group-III nitride semiconductors respectively in a growth mode parallel with a [0001] or [000-1] crystallographic axis over a substrate and having a source electrode and a drain electrode, those being coupled electrically to the channel layer, and a gate electrode formed over the electron supply layer, in which, in the buffer layer and the electron supply layer, a layer existing on the group-III atomic plane side of the channel layer has an A-axis length larger than a layer existing on the group-V atomic plane side of the channel layer; and the electron supply layer has a bandgap larger than the channel layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2011-41277 filed on Feb. 28, 2010 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates: to a semiconductor device; in particular to a semiconductor device equipped in a field effect transistor (hereunder abbreviated as “FET”) containing a group-III nitride semiconductor as a chief material.

RELATED ART 1

FIG. 14is a view schematically showing a sectional structure of an FET according to Related Art 1. The FET shown inFIG. 14is referred to in the description of UMESH K. MISHRA et al., “AlGaN/GaN HEMTs—An Overview of Device Operation and Applications”, PROCEEDINGS OF THE IEEE, VOL. 90, NO. 6, June 2002, pp. 1022-1031, for example. As shown inFIG. 14, a buffer layer81, a channel layer82, and an electron supply layer83are formed in this order over a substrate80. In the example ofFIG. 14, the buffer layer81comprises undoped gallium nitride (GaN), the channel layer82comprises undoped GaN, and the electron supply layer83comprises undoped aluminum gallium nitride AlaGa1-aN. Here, the group-III nitride semiconductor layered structure is formed by Ga plane growth parallel with a [0001] crystallographic axis.

The Al composition ratio a of the electron supply layer (AlaGa1-aN)83is set at such a value (0.3 or less for example) as to sufficiently decrease difference from GaN in lattice constant.

A gate electrode85is formed on the electron supply layer83and a source electrode841and a drain electrode842are formed opposite the gate electrode85.

A two dimension electron gas (hereunder abbreviated as “2DEG”) layer86acting as an electron transit layer is formed in the vicinity of an interface with the electron supply layer83in the channel layer82and the source electrode841and the drain electrode842formed over the electron supply layer83are in ohmic contact with the 2DEG layer86.

RELATED ART 2

FIG. 17is a view schematically showing a sectional structure of an FET according to Related Art 2. The FET shown inFIG. 17is referred to in the description of F. Medjdoub et al., “Characteristics of Al2O3/AlInN/GaN MOSHEMT”, ELECTRONICS LETTERS, 7 Jun. 2007 Vol. 43, No. 12 for example. As shown inFIG. 17, a buffer layer91comprising undoped GaN, a channel layer92comprising undoped GaN, and an electron supply layer93comprising undoped indium aluminum nitride InbAl1-bN are formed in this order over a substrate90. Here, the group-III nitride semiconductor layered structure is formed by Ga plane growth parallel with a hexagonal [0001] crystallographic axis.

The In composition ratio b of the electron supply layer (InbAl1-bN)93is set at such a value (0.17 to 0.18 for example) as to exhibit lattice matching with GaN.

A gate electrode95is formed on the electron supply layer93and a source electrode941and a drain electrode942are formed opposite the gate electrode95.

A 2DEG layer96is formed in the vicinity of an interface with the electron supply layer93in the channel layer92and the source electrode941and the drain electrode942formed over the electron supply layer93are in ohmic contact with the 2DEG layer96.

Here, although a spacer layer (AlN spacer) comprising aluminum nitride (AlN) is formed at the interface between an electron supply layer93comprising InAlN and a GaN channel layer92in F. Medjdoub et al., “Characteristics of Al2O3/AlInN/GaN MOSHEMT”, ELECTRONICS LETTERS, 7 Jun. 2007 Vol. 43, No. 12, it is not shown inFIG. 17.

Japanese Unexamined Patent Publication No. 2001-274375 discloses an FET, as a heterojunction FET, having a channel layer comprising InxGa1-xN (0≦x≦1), an electron supply layer comprising AlyGa1-yN (0y≦1), an intermediate layer, and an n-type cap layer comprising GaN, which are formed over a substrate in sequence, wherein a gate electrode is formed on a gate insulation film and a source electrode and a drain electrode are formed respectively on the n-type cap layer; the intermediate layer includes at least a single-layered n-type impurity layer; and thereby polarization negative charge generated between the electron supply layer and the n-type cap layer can be offset by ionization positive charge of the intermediate layer, hence a barrier against electrons decreases, and a source resistance and a drain resistance can decrease.

SUMMARY

Related arts are analyzed hereunder.

FIG. 15is a graph schematically showing the dependency of an amount of lattice strain on a drain voltage in an electron supply layer (AlaGa1-aN)83of an FET according to Related Art 1 shown inFIG. 14. The transverse axis represents a drain voltage and the longitudinal axis represents an amount of strain.FIG. 16is a graph schematically showing the dependency of a strain energy of a relevant lattice strain on a drain voltage. The transverse axis represents a drain voltage and the longitudinal axis represents a strain energy. Here,FIGS. 15 and 16are shown for facilitating the comprehension of the following analyses in the present specification and are not disclosed in UMESH K. MISHRA et al., “AlGaN/GaN HEMTs—An Overview of Device Operation and Applications”, PROCEEDINGS OF THE IEEE, VOL. 90, NO. 6, JUNE 2002, pp. 1022-1031 and the like.

In an FET ofFIG. 14, an electron supply layer (AlaGa1-aN)83has an internal strain in a tensile direction in a thermal equilibrium state of zero voltage (drain voltage=0) and hence the internal strain increases nearly in proportion to the drain voltage still in the tensile direction as the drain voltage increases. Consequently, the strain energy monotonically increases with the increase of the drain voltage and, if it exceeds a critical value Ecrit, crystal defects (dislocations) appear. A problem in the structure ofFIG. 14has been that a degradation commencement voltage is for example about 180 V and is relatively low. The principles of such behaviors of a lattice strain and a strain energy are explained hereunder.

In an FET according to Related Art 1, since the lattice constant (A-axis length in crystal axis) of AlaGa1-aN making up an electron supply layer83is smaller than the lattice constant of GaN making up a buffer layer81, a strain vector (∈1(a), ∈2(a), 0) exists in a tensile direction along a plane as a strain accompanying lattice mismatch in the electron supply layer83in a thermal equilibrium state (∈1(a)>0, ∈2(a)>0).

Further, when a voltage is applied to a drain electrode842so that a drain may have a potential more positive than a gate electrode85, an electric field vector (0, 0, F3) is generated in a direction from a substrate80toward the surface in the electron supply layer83(F30). According to the theory of inverse piezoelectric effect, if an electric field F3is applied to a dielectric substance in the vertical direction (Z direction), a strain deviation (Δ∈1(a), Δ∈2(a), 0) (strain caused by the inverse piezoelectric effect) proportional to a relevant electric field strength is generated in the horizontal direction (in an X-Y plane). Here, Δ∈i(a)(i=1, 2) is represented by the following expression (1).
Δ∈i(a)=di3(a)F3(1)

Here, di3(a)(i=1, 2) is a piezoelectricity component connecting an electric field in the longitudinal direction (vertical direction) F3to a strain in the horizontal direction Δ∈i(a)(i=1, 2) in an electron supply layer (AlGaN)83.

The strain deviation is directed toward a tensile direction when a semiconductor layered structure is Ga plane growth parallel with a [0001] crystallographic axis and an electric field F3is directed from a substrate80toward a surface.

Consequently, a strain vector (∈T1(a), ∈T2(a), 0) generated in the electron supply layer (AlGaN)83is represented by the following expression (2).
∈Ti(a)=∈i(a)+di3(a)F3(2)

Since a strain ∈i(a)(i=1, 2) accompanying lattice mismatch is directed in the tensile direction and a strain Δ∈i(a)caused by inverse piezoelectric effect is also directed in the tensile direction, they are reinforced by each other and an internal strain in the electron supply layer (AlGaN)83increases.

An amount of strain increases in proportion to the electric field component F3in the longitudinal direction (vertical direction). Since the electric field F3is proportional to a drain voltage, the relationship between an amount of strain and a voltage (drain voltage) shownFIG. 15is obtained.

According to Hooke's law, a strain energy Eaat the time is represented by the following expression (3).
Ea=EY(a)ha(∈1(a)+d13(a)F3)2(3)

In the above expression (3), EY(a)represents the Young's modulus of the electron supply layer (AlGaN)83. harepresents the thickness of the electron supply layer (AlGaN)83at a part under a gate electrode85. Here, it is assumed that the directions along a plane (i=1, 2) are equivalent to each other because of the Ga plane growth.

Since the strain energy Eaincreases in proportion to the square of the vertical direction electric field component F3(the coefficient of the square of F3is a positive value), the relationship between a strain energy and a voltage shown inFIG. 16is obtained.

In this way, a problem of an FET according to Related Art 1 has been that an internal strain ∈1(a)accompanying lattice mismatch and a strain Δ∈1(a)caused by inverse piezoelectric effect are reinforced by each other, hence a strain energy rapidly increases undesirably with the increase of a drain voltage, and a degradation commencement voltage lowers.

FIG. 18is a graph schematically showing the dependency of an amount of lattice strain on a drain voltage in an electron supply layer93comprising InAlN in an FET according to Related Art 2 shown inFIG. 17. The transverse axis represents a drain voltage and the longitudinal axis represents an amount of strain.FIG. 19schematically shows the dependency of a strain energy on a drain voltage. The transverse axis represents a drain voltage and the longitudinal axis represents a strain energy.FIGS. 18 and 19are shown for facilitating the comprehension of the following analyses in the present specification and are not disclosed in F. Medjdoub et al., “Characteristics of Al2O3/AlInN/GaN MOSHEMT”, ELECTRONICS LETTERS, 7 Jun. 2007 Vol. 43, No. 12 and the like.

An electron supply layer (InAlN)93inFIG. 17does not have an internal stress in thermal equilibrium of zero voltage (drain voltage=0). With the increase of a drain voltage however, an internal strain is generated in a tensile direction and the absolute value thereof increases nearly in proportion to voltage.

In an FET according to Related Art 2, an internal strain caused by thermal equilibrium is not generated. As a result, a degradation commencement voltage is 240 V for example and thus is improved better than an FET according to Related Art 1 inFIG. 14. That has been insufficient however.

The principles of such behaviors of a lattice strain and a strain energy are explained hereunder.

In an FET according to Related Art 2, since the lattice constant (A-axis length) of InbAl1-bN making up an electron supply layer93inFIG. 17is nearly equal to GaN making up a buffer layer91, a strain does not exist in the electron supply layer (InAlN)93in a thermal equilibrium state. When a voltage is applied so that a drain electrode942may have a potential more positive than a gate, an electric field vector (0, 0, F3) is generated in a direction from a substrate90toward a surface in the electron supply layer (InAlN)93(F3<0). According to the theory of inverse piezoelectric effect, if an electric field F3is applied to a dielectric substance in the vertical direction, strain deviation (Δ∈1(b), Δ∈2(a), 0) proportional to an electric field strength is generated in the horizontal direction. Here, Δ∈i(b)(i=1, 2) is represented by the following expression (4).
Δ∈i(b)=di3(b)F3(4)

Here, di3(b)(i=1, 2) is a piezoelectricity component connecting an electric field in the longitudinal direction to a strain in the horizontal direction in an electron supply layer (InAlN)93. The strain deviation is directed toward a tensile direction when a semiconductor layered structure is Ga plane growth parallel with a [0001] crystallographic axis and an electric field F3is directed from a substrate90toward a surface.

Consequently, a strain vector (∈T1(b), ∈T2(b), 0) generated in the electron supply layer (InAlN)93is represented by the following expression (5).
∈Ti(b)=di3(b)F3(5)

An amount of strain increases in proportion to the electric field component F3in the longitudinal direction and hence the relationship between an amount of strain and a voltage shownFIG. 18is obtained.

According to Hooke's law, a strain energy Ebat the time is represented by the following expression (6).
Eb=EY(b)hb(d13(b)F3)2(6)

Here, EY(b)represents the Young's modulus of InAlN. hbrepresents the thickness of the electron supply layer (InAlN)93at a part under a gate electrode95. Here, it is assumed that the directions along a plane (i=1, 2) are equivalent to each other because of the Ga plane growth.

Since the strain energy increases in proportion to the square of the longitudinal direction electric field component F3, the relationship between a strain energy and a voltage shown inFIG. 19is obtained.

In this way, a problem of an FET according to Related Art 2 has been that, even though an internal strain accompanying lattice mismatch does not exist, a strain Δ∈1(b)caused by inverse piezoelectric effect is proportional to an electric field, hence a strain energy monotonically increases undesirably with the increase of a voltage, and a degradation commencement voltage lowers.

As stated above, a problem of an FET according to the related arts has been that, when a high voltage is applied between a gate and a drain, lattice relaxation accompanied by the generation of dislocations (misfit dislocations) is caused easily and device characteristics are likely to deteriorate.

Consequently, the present invention has been invented in view of the above problems in a field effect transistor containing a group-III nitride semiconductor as a chief material and a chief object thereof is to provide a semiconductor device equipped with an FET that makes it possible to inhibit a device from deteriorating and increase reliability even when a high voltage is applied between a gate and a drain.

According to an aspect of the present invention, provided is a semiconductor device equipped with a field effect transistor having a buffer layer subjected to lattice relaxation, a channel layer, and an electron supply layer formed in this order with group-III nitride semiconductors respectively in a growth mode parallel with a [0001] or [000-1] crystallographic axis over a substrate and having a source electrode and a drain electrode, those being coupled electrically to the channel layer, and a gate electrode formed over the electron supply layer, wherein in the buffer layer and the electron supply layer, a layer existing on the group-III atomic plane side of the channel layer has an A-axis length larger than a layer existing on the group-V atomic plane side of the channel layer; and the electron supply layer has a bandgap larger than the channel layer.

According to the aspect of the present invention, in a field effect transistor containing a group-III nitride semiconductor as a chief material, it is possible to inhibit a device from degrading and increase reliability even when a high voltage is applied between a gate and a drain.

DETAILED DESCRIPTION

Preferred forms and embodiments according to the present invention are explained hereunder.

In some preferred forms, in a field effect transistor having a buffer layer subjected to lattice relaxation, a channel layer, and an electron supply layer formed in this order with group-III nitride semiconductors respectively in a growth mode parallel with a [0001] or [000-1] crystallographic axis over a substrate and having a source electrode and a drain electrode, those being coupled electrically to the channel layer, and a gate electrode formed over the electron supply layer: in the buffer layer and the electron supply layer, a layer existing on the group-III atomic plane side of the chamber layer has an A-axis length larger than a layer existing on the group-V atomic plane side of the channel layer; and the electron supply layer has a bandgap larger than the channel layer. “A growth mode parallel with a [0001] or [000-1] crystallographic axis” means a growth mode in which a growth direction is parallel with a [0001] or [000-1] crystallographic axis. In other words, the above field effect transistor is formed on a (0001) or a (000-1) crystal plane.

In some preferred forms: the buffer layer, the channel layer, and the electron supply layer are formed in this order in a group-III atomic plane growth mode parallel with the crystallographic axis over the substrate; and the A-axis length of the electron supply layer existing on the group-III atomic plane side of the channel layer is larger than the A-axis length of the buffer layer existing on the group-V atomic plane side of the channel layer. “A group-III atomic plane growth mode parallel with the [0001] crystallographic axis” means a group-III atomic-plane growth mode in which a growth direction is parallel with a [0001] crystallographic axis. In other words, the buffer layer, the channel layer and the electron supply layer are formed in this order on a (0001) group-III atomic-plane of the substrate.

In some preferred forms, characteristics are that: the buffer layer, the channel layer, and the electron supply layer are formed in this order in a group-V atomic plane growth mode parallel with the [000-1] crystallographic axis over the substrate; and the A-axis length of the electron supply layer existing on the group-V atomic plane side of the channel layer is smaller than the A-axis length of the buffer layer existing on the group-III atomic plane side of the channel layer. “A group-V atomic plane growth mode parallel with the [000-1] crystallographic axis” means a group-V atomic plane growth mode in which a growth direction is parallel with the [000-1] crystallographic axis. In other words, the buffer layer, the channel layer and the electron supply layer are formed in this order on a (000-1) group-V atomic plane of the substrate.

In some preferred forms: the buffer layer comprises GaN; the channel layer comprises GaN; and the electron supply layer comprises InxAl1-xN (0.18<x<0.53) having a compressive strain.

In some preferred forms: the buffer layer comprises Alz1Ga1-z1N (0<z1≦1); the channel layer comprises GaN; and the electron supply layer comprises Alz2Ga1-z2N (0≦z2<1, z2<z1) having a compressive strain.

In some preferred forms: the buffer layer comprises GaN; the channel layer comprises GaN; and the electron supply layer comprises InyAl1-yN (0<y<0.17) having a tensile strain.

In some preferred forms: the buffer layer comprises Alu1Ga1-u1N (0≦u1<1); the channel layer comprises GaN; and the electron supply layer comprises Alu2Ga1-u2N (0<u2≦1, u1<u2) having a tensile strain.

In some preferred forms: a top surface of the buffer layer has a (0001) Ga-face crystal plane or a (000-1) N-face crystal plane.

In some preferred forms: The channel layer may be formed on a (0001) Ga-face crystal plane of the buffer layer.

In some preferred forms: The channel layer may be formed on a (000-1) N-face crystal plane of the buffer layer.

In some preferred forms: the device has an insulation film over the electron supply layer; the lower part of the gate electrode is embedded into an opening formed in the insulation film; and the sides of the upper part thereof opposing the source electrode and the drain electrode protrude respectively toward the source electrode side and the drain electrode side and cover the insulation film (field plate structure).

In such a field effect transistor, since an internal strain at thermal equilibrium accompanying lattice mismatch and a strain deviation accompanying inverse piezoelectric effect offset each other, a strain energy during the application of a drain voltage is inhibited. By the present invention therefore, it is possible to improve a degradation commencement voltage in comparison with field effect transistors according to Related Arts. As a result, it is possible to inhibit device degradation from occurring and improve reliability even when a high voltage is applied between a gate and a drain. Exemplary embodiments are explained hereunder in reference to drawings.

First Embodiment

FIG. 1is a view schematically showing the sectional structure of a semiconductor device according to the exemplary first embodiment of the present invention. InFIG. 1, the numeral10represents a substrate,11a buffer layer subjected to lattice relaxation,12a channel layer, and13an electron supply layer. The semiconductor layered structure is formed by group-III atomic plane growth in which the growth direction is parallel with a [0001] crystallographic axis, the bandgap of the electron supply layer13is larger than that of the channel layer12, and the A-axis length of the electron supply layer13is larger than that of the buffer layer11. That is, a compressive strain is generated at thermal equilibrium of zero voltage in the electron supply layer13.

Here, in the buffer layer11and the electron supply layer13, a layer existing on the group-III atomic plane side of the channel layer12is the electron supply layer13and a layer existing on the group-V atomic plane side of the channel layer12is the buffer layer11. Then, the A-axis length of the layer on the group-III atomic plane side (electron supply layer13) is larger than that of the layer on the group-V atomic plane side (buffer layer11).

A 2DEG layer16is formed in the channel layer12and a source electrode141and a drain electrode142, those being coupled electrically to the 2DEG layer16, are formed in an opposing manner. A gate electrode15is formed over a part of the electron supply layer13interposed between the source electrode141and the drain electrode142. The channel layer12may be formed on a (0001) Ga-face crystal plane of the buffer layer or a (000-1) N-face crystal plane of the buffer layer.

FIG. 2is a graph schematically showing the dependency of an amount of lattice strain on a drain voltage in the electron supply layer13of an FET shown inFIG. 1.FIG. 3is a graph schematically showing the dependency of a strain energy on a drain voltage. The characteristics of FETs according to Related Arts 1 and 2 are also shown inFIGS. 2 and 3. An electron supply layer13has an internal strain in the compressive direction at thermal equilibrium of zero drain voltage and the internal strain turns from compressive to tensile with the increase of a drain voltage.

Consequently as shown inFIG. 3, the strain energy once reduces and then turns to increase as the drain voltage increases from zero. As a result, a degradation commencement voltage is about 360 V for example and improves considerably in comparison with 180 V and 240 V of Related Arts 1 and 2.

The principles of such behaviors of a lattice strain and a strain energy in the present embodiment are explained hereunder.

In the present embodiment, since the lattice constant (A-axis length) of an electron supply layer13is larger than that of a buffer layer11, a strain vector (−∈1(x), −∈2(x), 0) in a compressive direction along a plane exists in the electron supply layer13in a thermal equilibrium state (here, ∈1(x)>0, ∈2(x)>0).

When a drain voltage is applied to a gate so that a drain may have a positive electric potential, an electric field vector (0, 0, F3) is generated in the direction from a substrate10toward a surface in the electron supply layer13(F30). According to the theory of inverse piezoelectric effect, if a vertical direction electric field F3is applied to a dielectric substance, a strain deviation in the horizontal direction (Δ∈1(x), Δ∈2(x), 0) proportional to an electric field strength is generated. Δ∈i(x)(i=1, 2) is represented by the following expression (7).
Δ∈i(x)=di3(x)F3(7)

Here, di3(x)(i=1, 2) is a piezoelectricity component connecting a vertical direction electric field component F3to a horizontal direction strain Δ∈i(x)in a material making up the electron supply layer13.

The strain deviation is directed toward the tensile direction when a semiconductor layered structure is group-III atomic plane growth in which the growth direction is parallel with a [0001] crystallographic axis and an electric field F3is directed from a substrate10toward a surface.

Consequently, a strain vector (∈T1(x), ∈T2(x), 0) generated in the electron supply layer13is represented by the following expression (8).
∈Ti(x)=−∈i(x)+di3(x)F3(8)

Since a strain ∈i(x)(i=1, 2) accompanying lattice mismatch is directed in the compressive direction and a strain Δ∈i(x)(=di3(x)F3) (i=1, 2) caused by inverse piezoelectric effect is directed in the tensile direction in the expression (8), they offset each other and an internal strain (∈Ti(x)) in the electron supply layer13decreases.

From the expression (8), an amount of strain increases in proportion to a vertical direction electric field component F3. Since the longitudinal direction electric field component F3is proportional to a drain voltage, the relationship between an amount of strain (lattice strain) and a voltage (drain voltage) shownFIG. 2is obtained.

According to Hooke's law, a strain energy Exat the time is represented by the following expression (9).
Ex=EY(x)hx(−∈1(x)+d13(x)F3)2(9)

In the above expression (9), EY(x)represents the Young's modulus of the material making up the electron supply layer13. hxrepresents the thickness of the electron supply layer13at a part under a gate electrode15. Here, it is assumed that the directions along a plane (i=1, 2) are equivalent to each other because of the group-III atomic plane growth.

From the above expression (9), the strain energy Exincreases in proportion to the square of the vertical direction electric field component F3(the coefficient of the square of F3is a positive value). Consequently, the relationship between a strain energy and a voltage (drain voltage) shown inFIG. 3is obtained.

In this way, in the present embodiment, since the internal strain −∈1(x)accompanying lattice mismatch and the strain Δ∈1(x)caused by inverse piezoelectric effect offset each other, the internal strain in the electron supply layer13is compressive at thermal equilibrium and turns from compressive to tensile with the increase of a voltage (drain voltage).

Consequently, the strain energy once decreases and then turns to increase with the increase of a voltage, and the degradation commencement voltage that is a drain voltage when the strain energy reaches a critical value Ecrit is 360 V in the example shown inFIG. 3and improves considerably in comparison with the degradation commencement voltages of 180 V and 240 V in the cases of Related Arts 1 and 2.

Then, since the bandgap of the electron supply layer13is larger than that of the channel layer12, the 2DEG layer16is accumulated in the interior of the channel layer12, electrons travel in the channel layer12of a high electron mobility, and hence high-speed motion can be realized.

A concrete crystal structure for realizing such a structure is explained hereunder.

FIG. 4shows the dependency of an A-axis length (longitudinal axis: unit=angstrom=10−10m=0.1 nanometer) on an In composition ratio (transverse axis) (Characteristic2) and the dependency of a bandgap (longitudinal axis: unit=eV (electron volt)) on an In composition ratio (Characteristic1) of InxAl1-xN. From the dependencies on an In composition ratio (Characteristics1and2) shown inFIG. 4, it is understood that, by setting an In composition ratio x in the range of 0.18<x<0.53, it is possible to make the A-axis length of InxAl1-xN larger than the A-axis length of GaN (=3.19 angstroms) and the bandgap of InxAl1-xN larger than the bandgap of GaN (=3.4 eV).

Consequently, in such a device structure as shown inFIG. 1, by forming a buffer layer11with GaN, a channel layer12with GaN, and an electron supply layer13with InxAl1-xN (In composition ratio x: 0.18<x<0.53) for example, the A-axis length of the electron supply layer13is larger than that of the buffer layer11and the bandgap of the electron supply layer13is larger than that of the channel layer12.

FIG. 5is a graph showing the computation result of the dependency of a strain energy (longitudinal axis: J/m2) on a vertical direction electric field strength (transverse axis: V/cm) when the In composition ratio x of an electron supply layer13comprising InxAl1-xN is varied in an FET according to the present embodiment shown inFIG. 1. InFIG. 5, the dotted line (x=0.175) shows the dependency of a strain energy on an In composition ratio when an electron supply layer13comprising InAlN lattice-matches with a buffer layer11comprising GaN and that corresponds to an FET according to Related Art 2 (comparative example). The characteristics in the cases where the In composition ratio x is 0.20, 0.225, and 0.25 take the forms of quadratic functions.

As a result of analyses, it is found that a tentative effect of offsetting a strain energy can be obtained when the In composition ratio x of an electron supply layer13comprising InxAl1-xN is in the range of 0.18<x<0.53.

In the case of an In composition ratio x0.25 however, lattice mismatch increases and undesirably a strain energy increases excessively at thermal equilibrium of an electric field strength=0 as shown inFIG. 5. Consequently, it is desirable to set an In composition ratio x in the range of 0.19<x<0.25.

As a result of further analyses, it is found that the strain energy in the interior of an FET can be minimized when an In composition ratio x is set at about 0.2 as shown inFIG. 5. In the case of an In composition ratio x=0.20, the characteristic takes the form of a quadratic function showing a minimum strain energy (=0) at an electric field strength of about 1.5×107V/cm.

In a practical application, it is possible to sufficiently obtain the functions and effects of the present invention by setting an In composition ratio x in the range of 0.19<x<0.21 for example.

A manufacturing method of an FET according to the above embodiment is explained hereunder in reference toFIG. 1(here, the In composition ratio x is set at 0.2).

A nucleation layer 200 nm in thickness (not shown in the figure) comprising a superlattice formed by stacking undoped AlN and undoped GaN alternately, a buffer layer11(layer thickness: 1 μm) comprising undoped GaN, a channel layer12(layer thickness: 50 nm) comprising undoped GaN, and an electron supply layer13(layer thickness: 20 nm) comprising undoped In0.2Al0.8N are grown in this order over a (111) plane silicon (Si) substrate10for example by a metal organic chemical vapor deposition (abbreviated as MOCVD) method. Here, the semiconductor layered structure is formed by Ga plane growth in which the growth direction is parallel with a [0001] crystallographic axis. The channel layer is grown on a (0001) Ga-face crystal plane of the buffer layer. The thickness of the electron supply layer (InAlN)13is set so as to be thinner than a critical film thickness of generating dislocations over the buffer layer (GaN)11. By so doing, it is possible to obtain a good crystal quality of inhibiting dislocations from being generated.

On the basis of spontaneous polarization effect and piezoelectric polarization effect, positive electric charge having an area density of about 3×1013cm−2is generated at the interface between an electron supply layer13comprising InAlN and a channel layer12comprising GaN. Consequently, whereas both the electron supply layer13and the channel layer12are undoped, a 2DEG layer16is formed in the channel12comprising GaN.

A source electrode141and a drain electrode142are formed respectively over the electron supply layer13for example by evaporating and alloying a metal such as titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) and are in ohmic contact with the 2DEG layer16.

Successively, device isolation is applied by ion implantation of nitrogen (N) or the like.

A gate electrode15is formed over the electron supply layer13comprising InAlN in the region interposed between the source electrode141and the drain electrode142by evaporating and lifting off a metal such as Ni/Au. Such an FET as shown inFIG. 1is manufactured in this way.

Second Embodiment

FIG. 6is a view schematically showing the sectional structure of an FET according to the second embodiment of the present invention. InFIG. 6, the numeral20represents a substrate,21a buffer layer comprising Alz1Ga1-z1N subjected to lattice relaxation,22a channel layer comprising GaN, and23an electron supply layer comprising Alz2Ga1-z2N. Here, z1and z2have the relation of 0≦z2<z1≦1. The semiconductor layered structure is formed by Ga plane growth in which a growth direction is parallel with a [0001] crystallographic axis, the bandgap of the electron supply layer23is larger than that of the channel layer22, and the A-axis length of the electron supply layer23is larger than that of the buffer layer21. A compressive strain is generated at thermal equilibrium in the electron supply layer23.

A 2DEG layer26is formed in the channel layer22and a source electrode241and a drain electrode242, those being coupled electrically to the 2DEG layer26, are formed in an opposing manner.

An insulation film27is formed over the electron supply layer23and a gate electrode25is formed in the manner of being embedded into an opening28formed in the insulation film27. The gate electrode25is formed so as to cover the insulation film27at the source side end part and the drain side end part thereof and has a shape of eaves. The eave-shaped parts function as a field plate structure to alleviate so-called electric field concentration.

A semiconductor layered structure according to the present embodiment has a strain layer formed by a Ga plane growth with a growth direction of a [0001] crystallographic axis wherein the bandgap of the electron supply layer23is larger than that of the channel layer22, and the A-axis length of the electron supply layer23is larger than that of the buffer layer21. Consequently, on the basis of the principle similar to the first embodiment, the internal strain of the electron supply layer23at thermal equilibrium and the strain deviation accompanying inverse piezoelectric effect offset each other (refer to the expression (8)) and hence a strain energy when a drain voltage is applied is inhibited.

In the present embodiment further, electric field concentration generated at the drain side end of the gate is alleviated by the effect of a field plate. Consequently, a vertical direction electric field F3decreases and a strain energy caused by inverse piezoelectric effect is further inhibited from increasing in accordance with the expression (9).

FIG. 7is a graph showing the computation result of the dependency of a strain energy on a vertical direction electric field strength when the Al composition ratio z2of an electron supply layer (Alz2Ga1-z2N)23is varied in an FET structure shown inFIG. 6. The Al composition ratio z1of a buffer layer (Alz1Ga1-z1N)21is fixed to 0.2. InFIG. 7, the dotted line (Z2=0.2, Z1=0) shows the dependency of a strain energy on a vertical direction electric field strength corresponding to an FET according to Related Art 1.

As a result of analyses, it is found that a tentative effect of offsetting a strain energy can be obtained if the expression z2<z1is satisfied.

As a result of further analyses, it is found that it is possible to minimize the strain energy in the interior of an FET when the value z1-z2is set at about 0.1 as the result of z2=0.1, z1=0.2 shows inFIG. 7. In a practical application, when the expression 0.05<z1-z2<0.15 is satisfied, intended functions and effects can be obtained sufficiently.

A manufacturing method of an FET according to the second embodiment of the present invention is explained hereunder (the case of z2=0.1, z1=0.2).

A nucleation layer 200 nm in thickness (not shown in the figure) comprising a superlattice formed by stacking undoped AlN and undoped GaN alternately, a buffer layer21(layer thickness: 1 μm) comprising undoped Al0.2Ga0.8N, a channel layer22(layer thickness: 50 nm) comprising undoped GaN, and an electron supply layer23(layer thickness: 20 nm) comprising n-type Al0.1Ga0.9N are grown in this order over a (111) plane Si substrate20for example by an MOCVD method. Here, the semiconductor layered structure is formed by Ga plane growth in which a growth direction is parallel with a [0001] crystallographic axis. The channel layer22is grown on a (0001) Ga-face crystal plane. The thicknesses of the channel layer (GaN)22and the electron supply layer (AlGaN)23are set so as to be thinner than a critical film thickness of generating dislocations over the buffer layer (AlGaN)21. By so doing, it is possible to obtain a good crystal quality of inhibiting dislocations from being generated.

Si for example is used as an n-type impurity added to the electron supply layer (AlGaN)23and the concentration of the impurity is set at about 5×1018cm−3for example.

On the basis of spontaneous polarization effect and piezoelectric polarization effect, negative electric charge having an area density of about 1×1013cm−2is generated at the interface between a buffer layer (AlGaN)21and a channel layer (GaN)22. Further, positive electric charge having an area density of about 5×1012cm−2is generated at the interface between an electron supply layer (AlGaN)23and a channel layer (GaN)22.

Since an n-type impurity of a high concentration is added to the electron supply layer (AlGaN)23however, a 2DEG layer26is formed in the channel layer (GaN)22.

A source electrode241and a drain electrode242are formed respectively over the electron supply layer23for example by evaporating and alloying a metal such as Ti/Al/Ni/Au and are in ohmic contact with the 2DEG layer26.

Successively, device isolation is applied by ion implantation of N or the like. Subsequently, an insulation film27(film thickness: 60 nm) comprising silicon nitride (Si3N4) is formed for example by a plasma-enhanced chemical vapor deposition (abbreviated as “PECVD”) method.

After an opening pattern is formed by an ordinary photolithography method, an opening28is formed by removing the insulation film27and exposing the electron supply layer23for example by a dry etching method with a reactive gas such as sulfur fluoride (SF6).

Successively, a gate electrode25is formed in the manner of being embedded into the opening28for example by evaporating and lifting off a metal such as Ni/Au. Such an FET as shown inFIG. 6is manufactured in this way.

Third Embodiment

FIG. 8is a view schematically showing a sectional structure according to the third embodiment of the present invention. InFIG. 8, the numeral30represents a substrate,31a buffer layer subjected to lattice relaxation,32a channel layer, and33an electron supply layer. Here, the semiconductor layered structure is formed by group-V atomic plane growth in which a growth direction is parallel with a [000-1] crystallographic axis, the bandgap of the electron supply layer33is larger than that of the channel layer32, and the A-axis length of the electron supply layer33is smaller than that of the buffer layer31. That is, a tensile strain is generated at thermal equilibrium in the electron supply layer33.

Here, in the buffer layer31and the electron supply layer33, a layer existing on the group-III atomic plane side of the channel layer32is the buffer layer31and a layer existing on the group-V atomic plane side of the channel layer32is the electron supply layer33, and the A-axis length of the layer on the group-III atomic plane side (buffer layer31) is larger than the A-axis length of the layer on the group-V atomic plane side (electron supply layer33).

A 2DEG layer36is formed in the channel layer32and a source electrode341and a drain electrode342, those being coupled electrically to the 2DEG layer36, are formed in an opposing manner.

A gate electrode35is formed over a part of the electron supply layer33interposed between the source electrode341and the drain electrode342.

FIG. 9is a graph schematically showing the dependency of an amount of lattice strain on a drain voltage in the electron supply layer33of an FET shown inFIG. 8.FIG. 10is a graph schematically showing the dependency of a strain energy on a drain voltage. The characteristics of FETs according to Related Arts 1 and 2 are also shown inFIGS. 9 and 10as comparative examples.

The electron supply layer33has an internal strain in the tensile direction at thermal equilibrium of zero voltage (drain voltage=0) and the internal strain turns from tensile to compressive in proportion to the increase in the drain voltage and the strain energy once reduces and then turns to increase with the increase in the voltage. As a result, a degradation commencement voltage is about 360 V for example and improves considerably in comparison with 180 V and 240 V of Related Arts 1 and 2.

The principles of such behaviors of a lattice strain and a strain energy in the present embodiment are explained hereunder.

In the present embodiment, since the lattice constant (A-axis length) of an electron supply layer33is smaller than the lattice constant (A-axis length) of a buffer layer31, a strain vector (∈1(y), ∈2(y), 0) in a tensile direction exists along a plane in the electron supply layer33in a thermal equilibrium state (∈1(y)0, ∈2(y)0).

When a voltage is applied to a gate so that a drain may have a positive electric potential, an electric field vector (0, 0, F3) is generated in the direction from a substrate30toward a surface in the electron supply layer33(F30). According to the theory of inverse piezoelectric effect, if a vertical direction electric field F3is applied to a dielectric substance, strain deviation (Δ∈1(y), Δ∈2(y), 0) proportional to an electric field strength is generated in the horizontal direction. Here, Δ∈i(y)(i=1, 2) is represented by the following expression (10).
Δ∈i(y)=−di3(y)F3(10)

In the expression (10), di3(y)(i=1, 2) is a piezoelectricity component connecting a vertical direction electric field component F3to a horizontal direction strain Δ∈i(y)in a material making up the electron supply layer33.

The strain deviation is directed toward the compressive direction when a semiconductor layered structure is group-V atomic plane growth in which a growth direction is parallel with a [000-1] crystallographic axis and an electric field is directed from a substrate toward a surface.

Consequently, a strain vector (∈T1(y), ∈T2(y), 0) generated in the electron supply layer33is represented by the following expression (11).
∈Ti(y)=∈i(y)−di3(y)F3(11)

Since a strain ∈i(y)accompanying lattice mismatch is directed in the tensile direction and a strain Δ∈i(y)caused by inverse piezoelectric effect is directed in the compressive direction, they offset each other and an internal strain in the electron supply layer33decreases.

Since an amount of strain increases in proportion to the vertical direction electric field component F3, the relationship between a lattice strain and a voltage shown FIG.9is obtained.

According to Hooke's law, a strain energy Eyat the time is represented by the following expression (12).
Ey=EY(y)hy(∈1(y)+d13(y)F3)2(12)

In the above expression (12), EY(y)represents the Young's modulus of the material making up the electron supply layer33. hyrepresents the thickness of the electron supply layer33at a part under a gate electrode35. Here, it is assumed that the directions along a plane (i=1, 2) are equivalent to each other because of the group-V atomic plane growth.

Since the strain energy Eyincreases in proportion to the square of the vertical direction electric field component F3(the coefficient of the square of F3is a positive value), the relationship between a strain energy and a voltage shown inFIG. 10is obtained.

In this way, in the present embodiment, since the internal strain ∈1(y)accompanying lattice mismatch and the strain Δ∈1(y)caused by inverse piezoelectric effect offset each other, the internal strain is tensile at thermal equilibrium and turns from tensile to compressive with the increase of a voltage. Consequently, the strain energy Eyonce decreases and then turns to increase with the increase of a voltage (drain), and the degradation commencement voltage (drain voltage when the strain energy equals Ecrit: 360 V) improves considerably in comparison with Related Arts 1 and 2.

Then, since the bandgap of the electron supply layer33is larger than that of the channel layer32, the 2DEG layer36is formed in the interior of the channel layer32, electrons travel in the channel layer32of a high electron mobility, and hence high-speed motion can be realized.

A concrete crystal structure for realizing a structure according to the third embodiment is explained hereunder.

FromFIG. 4, by setting an In composition ratio y in the range of 0<y<0.17, the A-axis length of InyAl1-yN is smaller than that of GaN and the bandgap of InyAl1-yN is larger than that of GaN.

Consequently, in such a device structure as shown inFIG. 8, by forming a buffer layer31with GaN, a channel layer32with GaN, and an electron supply layer33with InyAl1-yN (0<y<0.17) for example, the A-axis length of the electron supply layer33is smaller than that of the buffer layer31and the bandgap of the electron supply layer33is larger than that of the channel layer32.

FIG. 11is a graph showing the computation result of the dependency of a strain energy on a vertical direction electric field strength when the In composition ratio y of an electron supply layer33comprising InyAl1-yN is varied in an FET structure shown inFIG. 8. InFIG. 11, the dotted line (x=0.175) shows the case where an InAlN electron supply layer33lattice-matches a GaN buffer layer31and corresponds to an FET according to Related Art 2.

As a result of analyses, it is found that a tentative effect of offsetting a strain energy can be obtained when the In composition ratio y of an electron supply layer33comprising InyAl1-yN is in the range of 0<y<0.17.

In the case of y<0.1, however, lattice mismatch increases and undesirably a strain energy increases excessively at thermal equilibrium. Consequently, it is desirable to set y in the range of 0.1<y<0.16.

As a result of further analyses, it is found that the strain energy in the interior of an FET can be minimized when y is set at about 0.15 as shown inFIG. 11. In a practical application, it is possible to sufficiently obtain intended effects by setting y in the range of 0.14<y<0.16.

A manufacturing method of an FET according to the third embodiment is explained (the case of y=0.15).

A nucleation layer 200 nm in thickness (not shown in the figure) comprising a superlattice formed by stacking undoped AlN and undoped GaN alternately, a buffer layer31(layer thickness: 1 μm) comprising undoped GaN, a channel layer32(layer thickness: 50 nm) comprising undoped GaN, and an electron supply layer33(layer thickness: 20 nm) comprising n-type In0.15Al0.85N are grown in this order over a (111) plane Si substrate30for example by an MOCVD method. Here, the semiconductor layered structure is formed by N plane growth in which a growth direction is parallel with a [000-1] crystallographic axis. The channel layer32is grown on a (000-1) N-face crystal plane of the buffer layer31.

The thickness of the electron supply layer33comprising In0.15Al0.85N is set so as to be thinner than a critical film thickness of generating dislocations over the buffer layer31comprising GaN. By so doing, it is possible to obtain a good crystal quality of inhibiting dislocations from being generated.

Si for example is used as an n-type impurity added to the electron supply layer33comprising In0.15Al0.85N and the concentration of the impurity is set at about 5×1019cm−3for example.

On the basis of spontaneous polarization effect and piezoelectric polarization effect, negative electric charge having an area density of about 3×1013cm−2is generated at the interface between an electron supply layer (In0.15Al0.85N)33and a channel layer (GaN)32. Since an n-type impurity of a high concentration is added to the electron supply layer33however, a 2DEG layer36is formed in the channel layer (GaN)32.

A source electrode341and a drain electrode342are formed respectively over the electron supply layer33for example by evaporating and alloying a metal such as Ti/Al/Ni/Au and are in ohmic contact with the 2DEG layer36.

Successively, device isolation is applied by ion implantation of N or the like. A gate electrode35is formed over a part of the electron supply layer33interposed between the source electrode341and the drain electrode342by evaporating and lifting off a metal such as Ni/Au. Such an FET as shown inFIG. 8is manufactured in this way.

Fourth Embodiment

FIG. 12is a view schematically showing the sectional structure according to the fourth embodiment of the present invention. InFIG. 12, the numeral40represents a substrate,41a buffer layer comprising Alu1Ga1-u1N subjected to lattice relaxation,42a channel layer comprising GaN, and43an electron supply layer comprising Alu2Ga1-u2N. Here, u1and u2have the relation of 0≦u1u2≦1. The semiconductor layered structure is formed by N plane growth in which a growth direction is parallel with a [000-1] crystallographic axis, the bandgap of the electron supply layer43is larger than that of the channel layer42, and the A-axis length of the electron supply layer43is smaller than that of the buffer layer41. That is, a tensile strain is generated at thermal equilibrium in the electron supply layer43. The channel layer42is formed on a (000-1) Ga-face crystal plane of the buffer layer41.

A 2DEG layer46is formed in the channel layer42and a source electrode441and a drain electrode442, those being coupled electrically to the 2DEG layer46, are formed in an opposing manner.

An insulation film47is formed over the electron supply layer43and a gate electrode45is formed in the manner of being embedded into an opening48formed in the insulation film47. The gate electrode45is formed so as to cover the insulation film47at the source side end part and the drain side end part thereof and has a shape of eaves. The eave-shaped parts function as a so-called field plate.

A semiconductor layered structure according to the present embodiment has a strain layer formed by N plane growth with a growth direction of [000-1] crystallographic axis in which the bandgap of the electron supply layer43is larger than that of the channel layer42; and the A-axis length of the electron supply layer43is smaller than that of the buffer layer41.

Consequently in the present embodiment, on the basis of the principle similar to the third embodiment, the internal strain of the electron supply layer43at thermal equilibrium and the strain deviation accompanying inverse piezoelectric effect offset each other and hence a strain energy when a voltage is applied is inhibited.

In the present embodiment further, electric field concentration generated at the drain side end of the gate is alleviated by the effect of a field plate. Consequently, the vertical direction electric field component F3decreases and a strain energy caused by inverse piezoelectric effect is further inhibited from increasing in accordance with the expression (12).

FIG. 13is a graph showing the computation result of the dependency of a strain energy on a vertical direction electric field strength when the Al composition ratio u2of an electron supply layer43comprising Alu2Ga1-u2N is varied in an FET structure shown inFIG. 12. The Al composition ratio u1of a buffer layer41comprising Alu1Ga1-u1N) is fixed to 0.1. InFIG. 13, the dotted line (u2=0.2, u1=0) shows the dependency of a strain energy on a vertical direction electric field strength in an FET (Ga plane growth) according to Related Art 1.

As a result of analyses, it is found that a tentative effect of offsetting a strain energy can be obtained if the Al composition ratio u1of a buffer layer and the Al composition ratio u2of an electron supply layer43satisfy the expression ui<u2.

As a result of further analyses, it is found that it is possible to minimize the strain energy in the interior of an FET when the value of u2-u1is set at about 0.1 as the result of u2=0.2, u1=0.1 shows inFIG. 13. In a practical application, when the expression 0.05<u2-u1<0.15 is satisfied, intended functions and effects can be obtained sufficiently.

A manufacturing method of an FET according to the present embodiment is explained hereunder (here, the case of u2=0.1 and u1=0.0).

A nucleation layer 200 nm in thickness (not shown in the figure) comprising a superlattice formed by stacking undoped AlN and undoped GaN alternately, a buffer layer41(layer thickness: 1 μm) comprising undoped GaN, a channel layer42(layer thickness: 50 nm) comprising undoped GaN, and an electron supply layer43(layer thickness: 20 nm) comprising n-type Al0.1Ga0.9N are grown in this order over a (111) plane Si substrate40for example by an MOCVD method.

Here, the semiconductor layered structure is formed by N plane growth in which a growth direction is parallel with a [000-1] crystallographic axis. The channel layer42is grown on a (000-1) N-face crystal plane of the buffer layer41.

The thicknesses of the electron supply layer43comprising Al0.1Ga0.9N is set so as to be thinner than a critical film thickness of generating dislocations over the buffer layer41comprising GaN. By so doing, it is possible to obtain a good crystal quality of inhibiting dislocations from being generated.

Si for example is used as an n-type impurity added to the electron supply layer43comprising Al0.1Ga0.9N and the concentration of the impurity is set at about 5×1018cm−3for example.

On the basis of spontaneous polarization effect and piezoelectric polarization effect, negative electric charge having an area density of about 5×1012cm−2is generated at the interface between an electron supply layer (AlGaN)43and a channel layer (GaN)42. Since an n-type impurity of a high concentration is added to the electron supply layer43however, a 2DEG layer46is formed in the GaN channel layer42.

A source electrode441and a drain electrode442are formed respectively over the electron supply layer43for example by evaporating and alloying a metal such as Ti/Al/Ni/Au and are in ohmic contact with the 2DEG layer46.

Successively, device isolation is applied by ion implantation of N or the like.

Subsequently, an insulation film47(60 nm) comprising Si3N4is formed for example by a PECVD method.

After an opening pattern is formed by an ordinary photolithography method, an opening48is formed by removing the insulation film47and exposing the electron supply layer43for example by a dry etching method with a reactive gas such as SF6.

Successively, a gate electrode45is formed in the manner of being embedded into the opening48for example by evaporating and lifting off a metal such as Ni/Au. Such an FET as shown inFIG. 12is manufactured in this way.

Although the present invention has been explained in accordance with the above embodiments, it is a matter of course that the present invention is not limited to the above embodiments and includes various embodiments corresponding to the principles of the present invention.

For example, although Si is used as a substrate in the above embodiments, another substrate comprising silicon carbide (SiC), sapphire (Al2O3), GaN, diamond (C), or the like may be adopted.

Although a superlattice of AlN and GaN is used as a nucleation layer in the above embodiments, a single layer of AlN, AlGaN, GaN, or the like may be used.

Although GaN or AlGaN is used as the material of a buffer layer in the above embodiments, another group-III nitride semiconductor comprising AlN, indium gallium nitride (InGaN), InAlN, InAlGaN, or the like may be used.

Although GaN is used as the material of a channel layer in the above embodiments, another group-III nitride semiconductor having a bandgap smaller than an electron supply layer may be used. For example, another group-III nitride semiconductor comprising AlGaN, InAlN, InAlGaN, InGaN, indium nitride (InN), or the like may be adopted.

Although InAlN or AlGaN is used as the material of an electron supply layer in the above embodiments, another group-III nitride semiconductor having a bandgap larger than a channel layer may be adopted. For example, AlN, GaN, InAlGaN, InGaN, or the like may be adopted.

Although an electron supply layer is undoped or an n-type in the above embodiments, a multi-layered structure such as a double-layered structure comprising an undoped layer and an n-type layer or a triple-layered structure comprising an undoped layer, an n-type layer, and an undoped layer may be adopted.

Although Si3N4is used as an insulation film in the above embodiments, another insulating material comprising aluminum oxide (Al2O3), silicon oxide (SiO2), or the like may be used.

Although Ti/Al/Ni/Au is used as the material of a source electrode and a drain electrode in the above embodiments, another material such as Ti/Al, Ti/Al/molybdenum (Mo)/Au, or Ti/Al/niobium (Nb)/Au may be used.

Although Ni/Au is used as the material of a gate electrode in the above embodiments, another material such as Ni/palladium (Pd)/Au, Ni/platinum (Pt)/Au, Ti/Au, Ti/Pd/Au, or Ti/Pt/Au may be used.

Although a gate electrode is formed on an electron supply layer in the above embodiments, for example a cap layer several nm in thickness comprising a group-III nitride semiconductor such as AlN, AlGaN, GaN, InAlN, InAlGaN, InGaN, or InN may be interposed between the electron supply layer and the gate electrode.

Although a channel layer is formed on an electron supply layer in the above embodiments, for example a spacer layer several nm in thickness comprising a group-III nitride semiconductor such as AlN, AlGaN, GaN, InAlN, InAlGaN, InGaN, or InN may be interposed between the electron supply layer and the channel layer.

Although a Schottky type gate is formed by forming a gate electrode on an electron supply layer in the above embodiment, a metal-insulation film-semiconductor (MIS) type gate formed by interposing an insulation film of Al2O3, SiO2, Si3N4, or the like between the electron supply layer and the gate electrode may be used.

Although device isolation is applied by ion implantation of N or the like in the above embodiments, another ion such as boron (B) may be used for the ion implantation. Otherwise, the device isolation may be applied by mesa etching.

Although a protection film is not formed over the outermost surface of a device in the above embodiments, a protection film comprising an insulating material such as Si3N4, SiO2, or Al2O3may be formed.

The present invention makes it possible to obtain an FET comprising a nitride semiconductor of a high degradation commencement voltage and contributes largely to the improvement in the performance of electronic devices used for a portable phone base-station, fixed radio transmission equipment, a digital broadcasting ground-based station, radar equipment, a motor controller, a high-frequency generator, power supply equipment, an inverter illumination lamp, and the like.

The disclosures in aforementioned Patent Literatures and Nonpatent Literatures are incorporated in the present specification by reference. It is possible to modify and adjust embodiments within the tenor of all the disclosures (including claims) in the present invention and further on the basis of the basic technological thought thereof. Further, it is possible to variously combine or select various disclosure components within the scope of claims in the present invention. That is, it is a matter of course that the present invention includes various modifications and amendments that can be done by those skilled in the art in accordance with all the disclosures including claims and technological thought.