Performing logical operations using a logical operation component based on a rate at which a digit line is discharged

An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses and methods related to logical operations using a logical operation component.

BACKGROUND

Computing systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processing resource can comprise a number of functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and a combinatorial logic block, for example, which can be used to execute instructions by performing logical operations such as AND, OR, NOT, NAND, NOR, and XOR, and invert (e.g., inversion) logical operations on data (e.g., one or more operands). For example, functional unit circuitry may be used to perform arithmetic operations such as addition, subtraction, multiplication, and division on operands via a number of logical operations.

A number of components in a computing system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be executed, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed) may be stored in a memory array that is accessible by the functional unit circuitry. The instructions and data may be retrieved from the memory array and sequenced and/or buffered before the functional unit circuitry begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the functional unit circuitry, intermediate results of the instructions and data may also be sequenced and/or buffered.

In many instances, the processing resources (e.g., processor and/or associated functional unit circuitry) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Data movement between and within arrays and/or subarrays of various memory devices, can affect processing time and/or power consumption.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods related to logical operations using a logical operation component. An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier.

In many instances, the processing resources (e.g., processor and/or associated functional unit circuitry) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Processing performance may be improved in a processing-in-memory (PIM) device, in which a processing resource may be implemented internal and/or near to a memory (e.g., directly on a same chip as the memory array). A PIM device may reduce time in processing and may also conserve power. Data movement between and within arrays and/or subarrays of various memory devices, such as PIM devices, can affect processing time and/or power consumption.

Dynamic random-access memory (DRAM) may be provided as part of a computing system to store data associated with the computing system. In some approaches, DRAM may comprise multiple one transistor, one capacitor (1T1C) memory cells, which may be coupled together to form a memory array. In 1T1C DRAM environments, binary data information may be stored in the capacitor in the form of an electric charge. Once a 1T1C memory cell has been read (e.g., once a read operation has been performed using data stored in the 1T1C memory cell), the electric charge corresponding to the binary data information stored in the capacitor may discharge (e.g., leak, become depleted, etc.) thereby destroying the binary data information that was stored in the capacitor. This phenomenon may be referred to as a “destructive read” or “destructive memory cell read.”

In contrast, DRAM memory cells having three transistors (3T) may preserve the binary data information (e.g., may preserve the charge stored therein) subsequent to performance of a read operation. This may allow for multiple word lines (e.g., read row lines, write row lines, etc.) to be fired without the need to refresh the memory cells or re-write data to the memory cells subsequent to performance of a read operation. This may reduce power consumption of a memory device since the memory cells do not need to be re-written or refreshed in comparison to conventional 1T1C DRAM memory cells, and may reduce an amount of time (e.g., a read-to-read delay) required between performance of read operations in comparison to conventional 1T1C DRAM memory cells.

In some approaches, performing logical operations between binary data (e.g., operands) stored in memory cells and binary data stored in an accumulator may need to be inverted (e.g., using a latch in addition to a sense amplifier latch) prior to performance of a logical operation. For example, in some approaches, data would be transferred to a first latch to be inverted, and the inverted data stored in the first latch may have been used as an operand in a logical operation between the inverted operands and operands stored in an accumulator.

Further, in some approaches, performing logical operations between binary data (e.g., operands) stored in memory cells and binary data stored in an accumulator may require multiple latches per column because binary data may need to be transferred multiple times prior to execution of a logical operation. For example, data stored in memory cells may be transferred to a first latch, then data may be transferred to a second latch in two discrete operations prior to performance of a logical operation using the data values.

In contrast, embodiments disclosed herein allow for logical operations to be performed between binary data (e.g., operands) stored in the memory cells without using an additional latch to perform the inversion. For example, a 3T memory cell may be controlled to invert the data stored therein without the need for an additional latch. In some embodiments, the inverted data associated with the 3T memory cell may then be used as an operand for a logical operation.

Further, in some embodiments, logical operations may be performed between binary data stored in sense amplifiers without performing multiple operations to transfer the data from memory cells to the sense amplifiers. For example, in some embodiments, data values may be concurrently transferred from memory cells to multiple sense amplifiers. Subsequent to transfer of the data, logical operations may be performed using the data values stored in the sense amplifiers. In some embodiments, performance of the logical operation may be facilitated through the use of a logical operation component, which may be configured to cause performance of a logical operation such as an XOR logical operation between the data values stored in the sense amplifiers.

Some embodiments herein may allow for logical operations such as NOR logical operations and/or NAND logical operations to be performed using two sense amplifiers with different reference voltages. For example, a pair of sense amplifiers having different reference voltages (e.g., trip points) can be operated to perform a NOR operation or a NAND operation depending on which sense amplifier of the pair of sense amplifiers is enabled. As described in more detail herein, a logical operation component coupled to the pair of sense amplifiers can be operated such that the sensing circuitry outputs a XOR of the data values stored in the sense amplifiers, which can correspond to a XOR operation between data values stored in a pair of cells sensed by the sense amplifiers.

FIG. 1is a block diagram of an apparatus in the form of a computing system100including a memory device120in accordance with a number of embodiments of the present disclosure. As used herein, a memory device120, controller140, channel controller143, memory array130, and/or sensing circuitry150might also be separately considered an “apparatus.”

System100includes a host110coupled (e.g., connected) to memory device120, which includes a memory array130. Host110can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, or a memory card reader, among various other types of hosts. Host110can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system100can include separate integrated circuits or both the host110and the memory device120can be on the same integrated circuit. The system100can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown inFIG. 1illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

For clarity, the system100has been simplified to focus on features with particular relevance to the present disclosure. The memory array130can be a DRAM array (e.g., a 3T DRAM array), SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array130can comprise memory cells arranged in rows coupled by word lines, which may be referred to herein as row lines, access lines, or select lines, and columns coupled by digit lines, which may be referred to herein as data lines or sense lines. Although a single array130is shown inFIG. 1, embodiments are not so limited. For instance, memory device120may include a number of arrays130(e.g., a number of banks of DRAM cells, NAND flash cells, etc.). In some embodiments, the memory array may include the sensing circuitry150in addition to the memory cells arranged in rows coupled by word lines and columns coupled by digit lines.

The memory device120includes address circuitry142to latch address signals for data provided over a data bus156(e.g., an I/O bus) through I/O circuitry144. Status and/or exception information can be provided from the controller140on the memory device120to a channel controller143, through a high speed interface (HSI) including an out-of-band bus157, which in turn can be provided from the channel controller143to the host110. Address signals are received through address circuitry142and decoded by a row decoder146and a column decoder152to access the memory array130. Data can be read from memory array130by sensing voltage and/or current changes on the digit lines using sensing circuitry150. The sensing circuitry150can read and latch a page (e.g., row) of data from the memory array130. The I/O circuitry144can be used for bi-directional data communication with host110over the data bus156. The write circuitry148can be used to write data to the memory array130.

Controller140(e.g., memory controller) decodes signals provided by control bus154from the host110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array130, including data read, data write, and data erase operations. In various embodiments, the controller140is responsible for executing instructions from the host110and sequencing access to the array130. The controller140can be a state machine, sequencer, or some other type of controller, and include hardware and/or firmware (e.g., microcode instructions) in the form of an application specific integrated circuit (ASIC), field programmable gate array, etc. The controller140can control, for example, performance of logical operations between operands stored in the memory array130.

As described further below, in a number of embodiments, the sensing circuitry150and/or the array130can comprise one or more sense amplifiers and/or a logical operation component. The sense amplifier(s) can be used in the performance of logical operations. For example, the sense amplifiers and/or the logical operation component may be used to perform logical operations such as XOR, NOR, NAND, etc. logical operation between operands stored in the sense amplifier(s). Embodiments are not so limited, however, and in some embodiments, the sense amplifiers may be configured to latch data values corresponding to NOR and/or NAND operations based on the reference voltages (e.g., trip points) of the sense amplifiers.

For example, as described herein, a first sense amplifier may be configured to latch a data value corresponding to a NOR of a data value stored in a memory array coupled to the first sense amplifier, while a second sense amplifier may be configured to latch a data value corresponding to a NAND of a data value stored in the memory array coupled to the second sense amplifier. The data values latched in the first sense amplifier and/or the second sense amplifier may be transferred back the memory array. In some embodiments, the data values latched in the first and second sense amplifiers may be used as operands by a logical operation component to output a XOR.

In a number of embodiments, the sensing circuitry150can be used to perform logical operations using data stored in array130as inputs and/or store the results of the logical operations back to the array130without transferring data via a digit line address access (e.g., without firing a column decode signal). As such, various compute functions can be performed using, and within, sensing circuitry150rather than (or in association with) being performed by processing resources external to the sensing circuitry (e.g., by a processing resource associated with host110and/or other processing circuitry, such as ALU circuitry, located on device120(e.g., on controller140or elsewhere)). Stated alternatively, various logical operations may be performed using, and within, the sensing circuitry150without transferring data or commands to or from the host110.

In various previous approaches, data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines (e.g., via local I/O lines and/or global I/O lines). The external ALU circuitry could include a number of registers and would perform compute functions using the operands, and the result would be transferred back to the array via the I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry150is configured to perform logical operations on data stored in memory array130and store the result back to the memory array130without enabling an I/O line (e.g., a local I/O line) coupled to the sensing circuitry150. The sensing circuitry150can be formed on pitch with the memory cells of the array.

In a number of embodiments, circuitry external to array130and sensing circuitry150is not needed to perform compute functions as the sensing circuitry150can perform the appropriate logical operations to perform such compute functions without the use of an external processing resource. Therefore, the sensing circuitry150may be used to complement and/or to replace, at least to some extent, such an external processing resource (or at least the bandwidth consumption of such an external processing resource).

However, in a number of embodiments, the sensing circuitry150may be used to perform logical operations (e.g., to execute instructions) in addition to logical operations performed by an external processing resource (e.g., host110). For instance, host110and/or sensing circuitry150may be limited to performing only certain logical operations and/or a certain number of logical operations.

Enabling an I/O line can include enabling (e.g., turning on) a transistor having a gate coupled to a decode signal (e.g., a column decode signal) and a source/drain coupled to the I/O line. However, embodiments are not limited to performing logical operations using sensing circuitry (e.g.,150) without enabling column decode lines of the array. Whether or not local I/O lines are used in association with performing logical operations via sensing circuitry150, the local I/O line(s) may be enabled in order to transfer a result to a suitable location other than back to the array130(e.g., to an external register).

FIG. 2Ais a schematic drawing illustrating a portion of a memory array in accordance with a number of embodiments of the present disclosure.FIG. 2Aillustrates one memory cell232, which can be one of a number of memory cells corresponding to memory array130shown inFIG. 1. In the example shown inFIG. 2, the memory cell232is a 3T DRAM memory cell. In this example, the memory cell232comprises three transistors202-1,202-2, and202-3. The memory cell232may be operated to store a data value (e.g., a stored charge at node204). In some embodiments, a charge associated with the data value may be stored at node204using the parasitic capacitance generated between transistor202-3and transistor203-2. Embodiments are not so limited; however, and the memory cell232may optionally include a discrete capacitor203to store the data value.

The memory cell232includes two word lines209-1/209-2(e.g., row lines) and two digit lines205-1/205-2(e.g., bit lines). Word line209-1may be referred to herein as a read row line, and the word line209-2may be referred to herein as a write row line. Digit line205-1may be referred to herein as a write digit line, and digit line205-2may be referred to herein as a read digit line. The word lines209-1/209-2and the digit lines205-1/205-2may be enabled and/or disabled in conjunction with reading and writing data to the node204of the memory cell232.

As shown inFIG. 2A, the transistors203-2,203-2, and203-3are coupled to the word lines209-1/209-2and digit lines205-1/205-2. In association with performing a write operation, the write row line209-2may be enabled, and data may be placed on the write digit line205-1, thereby causing the data to be stored at node204. Similarly, in association with performing a read operation, the read row line209-1may be enabled and the data may be transferred out of the node204via the read digit line205-2. In some embodiments, the data value read out of the memory cell232as part of a read operation may be inverted in comparison to the data value written to the memory cell232as part of the write operation. For example, if a value of “1” is written to the memory cell232, a value of “0” may be read out of the memory cell232. Conversely, if a value of “0” is written to the memory cell232, a value of “1” may be read out of the memory cell232.

For example, memory cell232can be coupled to different digit lines205-1/205-2and word lines209-1/209-2. For instance, in this example, a first source/drain region of transistor202-3is coupled to digit line205-1, a second source/drain region of transistor202-3is coupled to node204, and a gate of transistor202-3is coupled to word line209-2. A first source/drain region of transistor202-1is coupled to digit line205-2, a second source/drain region of transistor202-1is coupled to a first source/drain region of transistor202-2, and a gate of transistor202-1is coupled to word line209-1.

In some embodiments, the data value stored at node204of the memory cell232may be used as an operand for performance of a logical operation. For example, a data value stored at node204of the memory cell232may be used as an operand to perform a logical operation with a data value stored at node204of a different memory cell, as described in more detail in association withFIGS. 3-5. For example, the data value stored at node204of the memory cell232may be transferred to a sense amplifier and subsequently used as an operand to perform a logical operation with a data value stored at node204of a different memory cell and transferred to a different sense amplifier. In some embodiments, the logical operation may comprise an XOR operation; however, embodiments are not so limited, and various logical operations such as ANDS, ORs, XORs, NANDs, etc. operations may be performed in the manner described herein.

In some embodiments, the memory cell232may be controlled to store a data value at node204subsequent to performance of a read operation. For example, the memory cell232may be controlled such that read operations are non-destructive. This may allow for multiple rows (e.g., read rows) to be fired without refreshing or re-writing data to the memory cell232, which may allow for improved performance and reduced power consumption in comparison with previous approaches that utilize destructive read cells such as 1T1C memory cells.

Although schematically represented in a planar orientation, the transistors202-1,202-2, and/or202-3may be arranged in a vertical orientation (e.g., extending upward out of the page or downward into the page inFIG. 2). In some embodiments, the transistors202-1,202-2, and/or202-3of the memory cell232may be formed such that the transistors202-1,202-2, and/or202-3are contained within an area defined by the digit lines205-1/205-2. For example, the transistors202-1,202-2, and/or202-3of the memory cell232may be formed on pitch with digit lines205-1/205-2of the memory cell232. In some embodiments, the memory cell232may be formed such that the transistors202-1,202-2, and/or202-3of the memory cell232are disposed within an area that equal to or less than an area used by a conventional 1T1C DRAM memory cell.

FIG. 2Bis another schematic drawing illustrating a portion of a memory array230in accordance with a number of embodiments of the present disclosure. As shown inFIG. 2B, the memory array230comprises a plurality of memory cells232. For clarity, only one memory cell232is labeled inFIG. 2B; however, each set of three transistors illustrated inFIG. 2Brepresents one of a plurality of memory cells232associated with the memory array230.

A plurality of memory cells232are coupled to a plurality of digit lines205and row lines209. For example, a first memory cell232is coupled to digit lines205-10/205-20(e.g., write digit0 line205-10and read digit0 line205-20) and row lines209-10/209-20(e.g., read row0 line209-10and write row0 line209-20). Similarly, a second memory cell is coupled to digit lines205-11/205-21(e.g., write digit1 line205-11and read digit1 line205-21) and word lines209-10/209-20(e.g., read row0 line209-10and write row0 line209-20), a third memory cell is coupled to digit lines205-10/205-20(e.g., write digit0 line205-10and read digit0 line205-20) and word lines209-11/209-21(e.g., read row1 line209-11and write row1 line209-21, etc.

In some embodiments, if one or more memory cells232coupled to a particular digit line205-20, . . . ,205-2N(e.g., if one or more memory cells in a particular column of memory cells) contains a high voltage (e.g., a logical value of “1”), the associated digit line205-20, . . . ,205-2Nwill be driven to a ground reference potential. For example, if memory cell232(or any other memory cell in the column of memory cells coupled to digit line205-20) contains a high voltage, digit line205-20will be driven to a ground reference potential.

As described in more detail in association withFIG. 3, herein, a sense amplifier (e.g., sense amplifier306illustrated inFIG. 3) is coupled to respective pairs of digit lines205-10, . . . ,205-1Nand205-20, . . . ,205-2N. The sense amplifier may sense a low voltage (e.g., a logical value of “0”) if one or more of the memory cells coupled to a same pair of digit lines205-10, . . . ,205-1Nand205-20, . . . ,205-2Nthat are also coupled to the sense amplifier contains a high voltage (e.g., a logical value of “1”). Conversely, the sense amplifier may sense a high voltage (e.g., a logical value of “1”) if one or more of the memory cells coupled to a same pair of digit lines205-10, . . . ,205-1Nand205-20, . . . ,205-2Nthat are also coupled to the sense amplifier contains a low voltage (e.g., a logical value of “0”). That is, in some embodiments, the sense amplifier may sense a particular value (e.g., a “1” or a “0”) based on the value stored in the memory cell that is coupled thereto.

As mentioned above, because a read operation using the memory cell232described inFIGS. 2A and 2Bmay be non-destructive, the memory cell232may still contain the original data value (e.g., the same high or low voltage) that was stored therein prior to performance of the read operation and/or performance of the logical operation, while the sense amplifier may contain a result of the logical operation after performance of the logical operation. In some embodiments, the data value (e.g., the logical value of “0” or “1”) stored in the sense amplifier subsequent to performance of the logical operation may be written back to any memory cell232(or row of memory cells) in the memory array230, as described in more detail in association withFIG. 3, herein.

FIG. 3is a block diagram of sensing circuitry in accordance with a number of embodiments of the present disclosure. As shown inFIG. 3, the sensing circuitry350may include a first sense amplifier (SENSE AMP1)306, a second sense amplifier (SENSE AMP2)307, and a logical operation component311. As shown inFIG. 3, the logical operation component311is an exclusive or (XOR) logical operation component. For example, the logical operation component311may be configured to cause performance of an XOR363logical operation between an operand (e.g., a data value or charge corresponding to a logical “1” or “0”) stored in the first sense amplifier306and an operand stored in the second sense amplifier307. In some examples, as described in more detail in connection withFIG. 4, herein, the first sense amplifier306may have a reference voltage (e.g., a trip point) associated therewith that causes a logical NOR of the data value to be stored in the first sense amplifier306, while the second sense amplifier307may have a reference voltage associated therewith that causes a logical NAND of the data value to be stored in the second sense amplifier307. The logical operation component311is described in more detail in connection withFIG. 5, herein.

As used herein, a “component” is an electrical circuit (e.g., circuitry), hardware device (e.g., one or more processing resources and/or one or more memory resources), logic device, application-specific integrated circuit, field-programmable gate array, or combinations thereof, to perform one or more tasks or functions. A “logical operation component” is a component configured to cause performance of a logical operation, such as a XOR logical operation.

The first sense amplifier306and may be coupled to the logical operation component311, and the second sense amplifier307may be coupled to the logical operation component311. In some embodiments, the second sense amplifier307may be coupled to the logical operation component311via an inverter314. The inverter314may, in some embodiments, function as a NOT gate. When the logical operation component311is invoked, performance of a XOR logical operation between an operand stored in the first sense amplifier306and an operand stored in the second sense amplifier307may be facilitated.

As discussed in further detail in connection withFIG. 7, herein, in some embodiments, the sensing circuitry350may be configured to store a data value corresponding to a logical NOR of a data value stored in a memory cell (e.g., memory cell232illustrated inFIG. 2, herein) to be stored in the first sense amplifier306, and/or the sensing circuitry350may be configured to store a data value corresponding to a logical NAND of a data value stored in a memory cell to be stored in the second sense amplifier307. For example, if the data value stored in the first sense amplifier306is not passed through the logical operation component311, the sensing circuitry350may be configured to output a data value corresponding to a NOR361logical operation from the first sense amplifier306. Similarly, if the data value stored in the second sense amplifier307is not passed through the logical operation component311, the sensing circuitry350may be configured to output a data value corresponding to a NAND365logical operation from the second sense amplifier307. In some embodiments, the data value corresponding to the NOR logical operation361, the XOR logical operation363, and/or the NAND logical operation365may be read from the first sense amplifier306and/or the second amplifier307by enabling a column select line (e.g., Column Select transistor534illustrated inFIG. 5, herein).

FIG. 4is a graph illustrating the behavior of a plurality of digit lines responsive to activation of row lines associated with sensing circuitry in accordance with a number of embodiments of the present disclosure. The graph illustrated inFIG. 4may correspond to a voltage sensing scheme associated with sensing circuitry (e.g., sensing circuitry550illustrated inFIG. 5, herein). The upper horizontal curve shown inFIG. 4corresponds to a voltage magnitude of Vcc, while the lower horizontal curve shown inFIG. 4corresponds to a voltage magnitude associated with a ground reference potential (Gnd).

As shown inFIG. 4, one or more sense amplifiers (e.g., SENSE AMP1 and/or SENSE AMP2 illustrated inFIG. 3, herein) may be activated. The sense amplifier(s) may have a reference voltage (e.g., a trip point) somewhere between a pair of rail voltages (e.g., a supply voltage Vcc and applied to the read digit line405and the diagonal curve(s) illustrated inFIG. 4.

For example, upon activation (e.g., upon enabling) of a first sense amplifier (e.g., SENSE AMP1 illustrated inFIG. 3, herein), the first sense amplifier may have a reference voltage somewhere in between Vccand the diagonal curve corresponding to a voltage associated with the first sense amplifier (e.g., the SENSE AMP1 Reference Voltage shown inFIG. 4). Similarly, upon activation of a second sense amplifier (e.g., SENSE AMP2 illustrated inFIG. 3, herein), the second sense amplifier may have a reference voltage somewhere in between Vccand the diagonal curve corresponding to a voltage associated with the second sense amplifier (e.g., the SENSE AMP2 Reference Voltage shown inFIG. 4).

In some embodiments, the first sense amplifier and the second sense amplifier may each have a different reference voltage (e.g., trip point). The reference voltage may refer to a voltage at which at least one memory cell associated with the sense amplifier is conducting. For example, the first sense amplifier may be configured to have a reference voltage corresponding to a first voltage and the second sense amplifier may be configured to have a reference voltage corresponding to a second voltage. The first voltage may have a greater magnitude than the second voltage, or vice versa.

FIG. 4illustrates an example in which two row lines are activated. When two row lines are activated, there may be three different cases for how the digit lines (e.g., digit lines205-1and205-2illustrated inFIG. 2, herein) respond. The first case corresponds to a case in which both memory cells coupled to the row lines contain a logical value of “0” (as shown at “0,0 in cells”). In this case, the read digit line (e.g., read digit lines205-2illustrated inFIG. 2, herein) stay at a precharged level of Vcc. For example, in the first case, the reference voltages of the sense amplifiers may be selected such that, after a particular amount of time (e.g., at the point labeled SENSE AMP DECIDE), neither of the sense amplifiers are “tripped” corresponding to the memory cells coupled to the row lines contain logical values of “0.”

The second case corresponds to a case in which one of the memory cells contains a logical value of “1” and the other memory cell contains a logical value of “0” (as shown at “0,1 in cells or 1,0 in cells). In this case the read digit line may discharge from Vccto the ground reference potential as shown by the curve462. For example, in the second case, the reference voltages of the sense amplifiers may be selected such that, after a particular amount of time (e.g., at the point labeled SENSE AMP DECIDE), one of the sense amplifiers is “tripped” corresponding to one of the memory cells coupled to the row lines containing a logical value of “0,” while another memory cell coupled to the row lines contains a logical value of “1.”

In the second case, the data value latched by the first sense amplifier in response to the sense amplifier being tripped may correspond to a logical NOR (or NAND) of the data value stored in the corresponding memory cell. Similarly, the data value latched by the second sense amplifier may correspond to a logical NAND (or NOR) of the data value stored in the corresponding memory cell. Whether the data value latched by the respective sense amplifier corresponds to a logical NOR or a logical NAND corresponds to the reference voltage associated with the sense amplifier that is tripped.

For example, as shown inFIG. 4, the SENSE AMP1 Reference Voltage is higher than a voltage corresponding a voltage on the READ DIGIT LINE at a time corresponding to the SENSE AMP DECIDE curve, which may result in the first sense amplifier latching a data value corresponding to a logical NOR of a data value stored in the memory cell corresponding to the first sense amplifier. In contrast, the SENSE AMP2 Reference Voltage is lower than a voltage corresponding a voltage on the READ DIGIT LINE at a time corresponding to the SENSE AMP DECIDE curve, which may result in the second sense amplifier latching a data value corresponding to a logical NAND of a data value stored in the memory cell corresponding to the second sense amplifier.

The third case corresponds to a case in which both memory cells contain a logical value of “1” (as shown at “1,1 in cells”). In this case, the read digit line may discharge from Vccto the ground reference potential as shown by the curve464. For example, in the third case, the reference voltages of the sense amplifiers may be selected such that, after a particular amount of time (e.g., at the point labeled SENSE AMP DECIDE), both of the sense amplifiers are “tripped” responsive to the memory cells coupled to the row lines containing a logical value of “1.” In some embodiments, the rate of discharge exhibited by the curve464may be twice the rate of discharge exhibited by the curve462. For example, in the case corresponding to the curve464, there may be twice as much current in the memory cells as there is in the case corresponding to the curve462.

In some embodiments, a reference voltage for the first sense amplifier may be set to a particular value (as shown at “SENSE AMP1 Reference Voltage”), and/or a reference voltage for the second sense amplifier may be set to a different particular value (as shown at “SENSE AMP2 Reference Voltage”). Embodiments are not limited to the case shown inFIG. 4in which there are two sense amplifiers, however, and in some embodiments, a single sense amplifier may be used. In examples in which a single sense amplifier is used, the sense amplifier may be sensed twice to correspond to the two particular sense amplifier reference voltage levels illustrated inFIG. 4.

For example, a first reference voltage may be set for a single sense amplifier and a data value may be latched by the sense amplifier. In some embodiments, the data value latched by the sense amplifier using the first reference voltage may correspond to a logical NOR of a data value stored in the memory cell corresponding to the sense amplifier. Subsequently, a second reference voltage may be set for the sense amplifier. A data value latched by the sense amplifier using the second reference voltage may correspond to a logical NAND of a data value stored in the memory cell corresponding to the sense amplifier. The data value corresponding to the logical NOR and/or the data value corresponding to the logical NAND may be transferred to a storage location for use in a subsequent logical operation (e.g., in performance of a XOR logical operation using the data value corresponding to the NOR and the data value corresponding to the NAND as operands for the XOR logical operation).

FIG. 5is a schematic diagram illustrating sensing circuitry having a logical operation component in accordance with a number of embodiments of the present disclosure.FIG. 5illustrates a first sense amplifier506(e.g., SENSE AMP1), a second sense amplifier507(e.g., SENSE AMP2), and a logical operation component511.FIG. 5illustrates one sensing component550which can be one of a number of sensing components corresponding to sensing circuitry150shown inFIG. 1. The sensing component550may be coupled to a memory array530, via the digit line505-2(e.g., read digit line505-2) and the digit line505-1(e.g., write digit line505-1).

The read digit line505-2may be coupled to a first source/drain region of a transistor516-1(e.g., Precharge1 transistor516-1). A second source/drain region of the transistor516-1may be coupled to a voltage source configured to provide Vcc/2 to the second source/drain region of the transistor516-1. The write digit line505-1may be coupled to a first source/drain region of a transistor516-2(e.g., Precharge2 transistor516-2). A second source/drain region of the transistor516-2may be coupled to a voltage source configured to provide Vccto the second source/drain region of the transistor516-2.

As described in more detail below, the read digit line505-2and the write digit line505-1may be coupled to the sensing circuitry550, a Column Select transistor534, and/or a Local input/output (I/O) line. The Column Select transistor534may be controlled to select various columns of the memory array530to, for example, allow data values to be transferred between the memory array530and the sensing circuitry550and/or to circuitry external to the memory array550. In some embodiments, the Local I/O line may be controlled to transfer data values from the memory array530and/or sensing circuitry550to circuitry external to the memory array530.

The sense amplifiers506and507can be operated to determine a data value (e.g., logic state) stored in a selected memory cell of the memory array530. The sense amplifiers506and507can each include a cross-coupled latch512-1/512-2(e.g., gates of a pair of transistors, such as n-channel transistors that are cross coupled with the gates of another pair of transistors, such as p-channel transistors); however, embodiments are not limited to this example.

The cross-coupled latch512-1of SENSE AMP1506may be coupled to a Read Enable1 transistor531-1, which may be coupled to the read digit line505-2and a Write Enable1 transistor513-1, which may be coupled to the write digit line505-1. Similarly, the cross-coupled latch512-2of SENSE AMP2507may be coupled to a Read Enable2 transistor531-2, which may be coupled to the read digit line505-2and a Write Enable2 transistor513-2, which may be coupled to the write digit line505-1.

The sensing circuitry506may further include a Reference Enable1 transistor519-1, which may be coupled to the cross-coupled latch512-1at a first source/drain region of the transistor519-1. In some embodiments, a second source/drain region of the transistor519-1may be coupled to a reference potential (e.g., a ground reference potential). Similarly, the sensing circuitry507may further include a Reference Enable2 transistor519-2, which may be coupled to the cross-coupled latch512-2at a first source/drain region of the transistor519-2. In some embodiments, a second source/drain region of the transistor519-2may be coupled to a reference potential (e.g., a ground reference potential).

In some embodiments, an XOR logical operation as described above in connection withFIG. 3and below in connection withFIGS. 7 and 8may be performed between data values stored in the memory array530by precharging the ACT1 (active pull-up) node of the cross-coupled latch512-1of SENSE AMP1506and precharging the ACT2 node of the cross-coupled latch512-2of the SENSE AMP2507, and/or precharging the RNL1 (activation) node of the cross-coupled latch512-1of SENSE AMP1506and precharging the RNL2 node of the cross-coupled latch512-2of the SENSE AMP2507. In some embodiments, the ACT1 node, the ACT2 node, the RNL1 node, and/or the RNL2 node may be precharged to Vcc/2 prior to performance of the logical operation.

Subsequent to, or concurrently with precharging the ACT1 node, the ACT2 node, the RNL1 node, and/or the RNL2 node, the Precharge1 transistor516-1may be enabled to precharge the read digit line505-2to Vcc/2. In some embodiments, the Read Enable1 transistor531-1and the Read Enable2 transistor531-2may be enabled such that the charge on the digit line505-2may pass through the Read Enable1 transistor531-1and the Read Enable2 transistor531-2. Subsequently, the Reference Enable1 transistor519-1and the Reference Enable2 transistor519-2may be enabled.

A plurality of rows (e.g., rows209-1/209-2illustrated inFIG. 2, herein) may be subsequently activated (e.g., opened). In some embodiments, two rows, such as write row0209-20and write row1209-21may be activated. The rows209-1/209-2may be activated to allow a data value stored in a memory cell (e.g., memory cell232illustrated inFIG. 2) to be transferred to the sense amplifiers506/507(e.g., SENSE AMP1 and/or SENSE AMP2).

In some embodiments, the data values stored in memory cells coupled to the rows (e.g., rows209-1/209-2) may be sensed by the SENSE AMP1 and/or the SENSE AMP2. For example, a signal may develop on the SENSE AMP1 and/or the SENSE AMP2 in response to activation of the rows. Once the signal has developed on the SENSE AMP1 and/or the SENSE AMP2, the Reference Enable1 transistor519-1and the Reference Enable2 transistor519-2may be disabled, and/or the Read Enable1 transistor531-1and the Read Enable2 transistor531-2may be disabled.

The ACT1 node the ACT2 node, the RNL1 node, and/or the RNL2 node may subsequently be enabled (e.g., fired) to sense a state corresponding to the read digit line505-2. For example, the ACT1 node the ACT2 node, the RNL1 node, and/or the RNL2 node may subsequently be enabled to sense the data values present on the read digit line505-2in the SENSE AMP1506and/or the SENSE AMP2507.

In some embodiments, once the data values are sensed by the SENSE AMP1 and/or the SENSE AMP2, the rows may be deactivated (e.g., closed). In some embodiments, the write digit line505-1may be precharged to Vcc. For example, the Precharge2 transistor516-2may be enabled to precharge the write digit line505-1to Vcc. Subsequently, a row different than the rows previously activated may be activated. For example, write rowN209-2Nmay be activated (e.g., opened).

The XOR Enable transistor518may be subsequently enabled to transfer a result of the XOR logical operation between the data value sense by SENSE AMP1 and the SENSE AMP2 to the row different than the rows previously activated (e.g., to write rowN209-2N). In some embodiments, the result of the XOR logical operation may be stored in a memory cell coupled to the write row (e.g., to a memory cell coupled to write rowN209-2N). After the result of the XOR logical operation has been transferred to the write row that is different than the rows previously activated, the write row that is different than the rows previously activated may be disabled (e.g., closed).

In some embodiments, the result of the XOR logical operation may be read out of the sensing circuitry550via the Column Select line and/or via the Local I/O line. As described above, the data value sensed by the SENSE AMP1 may be read out of the sensing circuitry the write row that is different than the rows previously activated, the Column Select line and/or via the Local I/O line. As described above in connection withFIG. 3, the resulting data value read out of the SENSE AMP1 may correspond to a data value having a NOR logical operation applied thereto or performed thereon. Similarly, the data value sensed by the SENSE AMP2 may be read out of the sensing circuitry the write row that is different than the rows previously activated, the Column Select line and/or via the Local I/O line. As described above in connection withFIG. 3, the resulting data value read out of the SENSE AMP2 may correspond to a data value having a NAND logical operation applied thereto or performed thereon.

FIG. 6is a schematic diagram illustrating a portion of a memory array including sensing circuitry having a logical operation component in accordance with a number of embodiments of the present disclosure.FIG. 6shows a number of sense amplifiers606/607coupled to respective digit lines605and605. The sense amplifiers606/607shown inFIG. 6can correspond to sensing circuitry150shown inFIG. 1, sense amplifiers306/307shown inFIG. 3and/or sense amplifiers506/507shown inFIG. 5.

Although not explicitly shown, memory cells, such as those described inFIG. 2B, are coupled to the respective digit lines605-1and605-2The cells of the memory array630can be arranged in rows coupled by word lines and columns coupled by pairs of digit lines, etc. The individual digit lines corresponding to each pair of respective digit lines can also be referred to as data lines. Although only five pairs of digit lines605-1/605-2(e.g., five columns) are shown inFIG. 6, embodiments of the present disclosure are not so limited.

A data value present on a digit line605can be loaded into the corresponding sense amplifier606and/or sense amplifier607. For example, as described in connection withFIG. 5, data values present on the digit lines605-2may be sensed by the sense amplifier606and/or the sense amplifier607.

Each column may be coupled to memory cells632, which can be coupled to a Column Select transistor634(e.g., a column decode line) that can be activated to transfer data values from corresponding sense amplifiers606/607to a control component external to the array such as an external processing resource (e.g., host processor and/or other functional unit circuitry). The column decode line can be coupled to a column decoder. In a number of embodiments, the data values may be transferred to the sense amplifiers606/607and/or transferred out of the sense amplifiers606/607without transferring data to a control component and/or a processing resource external to the array (e.g., without transferring data from the memory device to a host such as host110illustrated inFIG. 1), for instance. In some embodiments, a logical operation may be performed using operands stored in the sense amplifiers506/507without encumbering a host such as host110shown inFIG. 1. As used herein, the term “encumbering” refers to utilizing processing resources and/or transferring commands and/or data. For example, a logical operation may be performed using operands stored in the sense amplifiers506/507without utilizing processing resources and/or transferring commands and/or data from the memory device to the host.

As used herein, transferring data, which may also be referred to as moving data or shifting data is an inclusive term that can include, for example, copying data from a source location to a destination location and/or moving data from a source location to a destination location without necessarily maintaining a copy of the data at the source location (e.g., at the sense amplifier606and/or at the sense amplifier607).

Logical operation components611may be coupled to the digit lines605-1/605-2and/or to the sense amplifiers606/607. The logical operation components611may be analogous to the logical operation component311illustrated inFIG. 3and/or logical operation component511illustrated inFIG. 5, herein.

In some embodiments, the logical operation component611may be configured to cause performance of a logical operation (e.g., a XOR logical operation) between data values (e.g., operands) stored in the sense amplifier606and the sense amplifier607. Performance of said logical operations may be carried out using the logical operation component611by enabling and/or disabling various transistors that comprise the logical operation component611, as shown and described in connection withFIG. 5, herein.

The result of a logical operation performed by use of the logical operation component611may be transferred via the Local I/O line from the memory array630and/or sensing circuitry (e.g., sensing circuitry550shown inFIG. 5) to circuitry external to the memory array. Embodiments are not so limited, however, and the result of the logical operation may be transferred via activation of the Column Select transistors634from the memory array and/or sensing circuitry to circuitry external to the memory array.

FIG. 7is a logic table illustrating selectable logical operation results implementable in accordance with a number of embodiments of the present disclosure. InFIG. 7, each column corresponds to a data value associated with a particular component or portion of a memory array (e.g., memory array130illustrated inFIG. 1) and/or a particular component or portion of the sensing circuitry (e.g., sensing circuitry150illustrated inFIG. 1).

The first column corresponds to a data value associated with a first row709-10of the memory array (e.g., ROW 1). The second column corresponds to a data value associated with a first row709-20of the memory array (e.g., ROW 2). The third column corresponds to a first sense amplifier706of the sensing circuitry, while the fourth column corresponds to a second sense amplifier707of the sensing circuitry. In the third and fourth columns, the data values correspond to data values output by the first sense amplifier and the second sense amplifier, respectively. For example, as described above in connection withFIG. 3, a data value output by the first sense amplifier706may correspond to performance of a NOR logical operation761by the first sense amplifier, and a data value output by the second sense amplifier707may correspond to performance of a NAND logical operation765by the first sense amplifier. The fifth column corresponds to a result of a XOR logical operation763performed by a logical operation component (e.g., logical operation component511illustrated inFIG. 5) using a data value stored in the first sense amplifier706and a data value stored in the second sense amplifier707.

In the second row of the logic table illustrated inFIG. 7(e.g., the first row of the logic table containing numbers), ROW 1 and ROW 2 may each include a logical value of “0.” In this case, the first sense amplifier706may be configured to store and/or output a logical value of “1,” corresponding to performance of a logical NOR operation761. The second sense amplifier707may be configured to store and/or output a logical value of “1,” corresponding to performance of a logical NAND operation765. If the logical operation component is invoked to cause performance of a XOR logical operation763between an operand stored in the first sense amplifier706(e.g., a data value with a logical value of “1”) and an operand stored in the second sense amplifier707(e.g., a data value with a logical value of “1”), the result will have a logical value of “0,” as shown inFIG. 7.

In the third row of the logic table illustrated inFIG. 7(e.g., the second row of the logic table containing numbers), ROW 1 may include a logical value of “0” and ROW 2 may include a logical value of “1.” In this case, the first sense amplifier706may be configured to store and/or output a logical value of “0,” corresponding to performance of a logical NOR operation761. The second sense amplifier707may be configured to store and/or output a logical value of “1,” corresponding to performance of a logical NAND operation765. If the logical operation component is invoked to cause performance of a XOR logical operation763between an operand stored in the first sense amplifier706(e.g., a data value with a logical value of “0”) and an operand stored in the second sense amplifier707(e.g., a data value with a logical value of “1”), the result will have a logical value of “1,” as shown inFIG. 7.

In the fourth row of the logic table illustrated inFIG. 7(e.g., the third row of the logic table containing numbers), ROW 1 may include a logical value of “1” and ROW 2 may include a logical value of “0.” In this case, the first sense amplifier706may be configured to store and/or output a logical value of “0,” corresponding to performance of a logical NOR operation761. The second sense amplifier707may be configured to store and/or output a logical value of “1,” corresponding to performance of a logical NAND operation765. If the logical operation component is invoked to cause performance of a XOR logical operation763between an operand stored in the first sense amplifier706(e.g., a data value with a logical value of “0”) and an operand stored in the second sense amplifier707(e.g., a data value with a logical value of “1”), the result will have a logical value of “1,” as shown inFIG. 7.

In the fifth row of the logic table illustrated inFIG. 7(e.g., the fourth row of the logic table containing numbers), ROW 1 and ROW 2 may each include a logical value of “1.” In this case, the first sense amplifier706may be configured to store and/or output a logical value of “0,” corresponding to performance of a logical NOR operation761. The second sense amplifier707may be configured to store and/or output a logical value of “0,” corresponding to performance of a logical NAND operation765. If the logical operation component is invoked to cause performance of a XOR logical operation763between an operand stored in the first sense amplifier706(e.g., a data value with a logical value of “0”) and an operand stored in the second sense amplifier707(e.g., a data value with a logical value of “0”), the result will have a logical value of “0,” as shown inFIG. 7.

FIG. 8is a flow diagram870for performing logical operations using sensing circuitry having a logical operation component in accordance with a number of embodiments of the present disclosure. In some embodiments, the logical operation may be a XOR logical operation, as described in connection withFIGS. 3, 4, 5, and 7, herein. Performance of the logical operation may include operating sense amplifiers at different reference voltages and/or enabling a XOR Enable transistor (e.g., XOR Enable transistor518illustrated inFIG. 5). The logical operation may be performed between data values stored in one or more memory cells and/or between data values stored in the first sense amplifier and the second sense amplifier.

At block871, a digit line (e.g., read digit line505-2illustrated inFIG. 5) may be precharged to VCC/2. In some embodiments, prior to precharging the digit line, an ACT1 (active pull-up) node of a first sense amplifier (e.g., SENSE AMP1506illustrated inFIG. 5), an ACT2 node of a second sense amplifier (e.g., SENSE AMP2507illustrated inFIG. 5), and/or an RNL1 (activation) node of the first sense amplifier and an RNL2 node of the second sense amplifier may be precharged to Vcc/2.

At block872, a read enable transistor and a reference enable transistor may be activated (e.g., opened). In some embodiments, the read enable transistor may correspond to Read Enable1 transistor531-1and/or Read Enable2 transistor531-2illustrated inFIG. 5. The read enable transistor(s) may be enabled such that the charge on the digit line may pass through the read enable transistor(s). Subsequently, the reference enable transistor(s), which may correspond to Reference Enable1 transistor519-1and the Reference Enable2 transistor519-2illustrated inFIG. 5, may be enabled.

At block873, one or more rows of a memory array (e.g., memory array130illustrates inFIG. 1) may be activated. In some embodiments, two rows, such as write row0209-20and write row1209-21, illustrated inFIG. 2, may be activated. The rows may be activated to allow a data value stored in a memory cell (e.g., memory cell232illustrated inFIG. 2) to be transferred to the first sense amplifier and the second sense amplifier. In some embodiments, the data values stored in memory cells coupled to the rows may be sensed by the first sense amplifier and/or the second sense amplifier. For example, a signal may develop on the first sense amplifier and/or the second sense amplifier in response to activation of the rows. Subsequently, in some embodiments, the read enable transistor(s) and the reference enable transistor(s) may be disabled, as described in connection withFIG. 5, herein.

At block874, the ACT1 node, ACT2 node, RNL1 node, and/or RNL2 node may be activated (e.g., fired). In some embodiments, activating the ACT1 node, ACT2 node, RNL1 node, and/or RNL2 node may allow a state corresponding to the digit line to be sensed by the first sense amplifier and/or the second sense amplifier. For example, activating the ACT1 node, ACT2 node, RNL1 node, and/or RNL2 node may allow for a data value present on the digit line to be sensed by the first sense amplifier and/or the second sense amplifier.

In some embodiments, once the data values are sensed by the first sense amplifier and/or the second sense amplifier, the rows may be deactivated (e.g., closed). In some embodiments, the write digit line (e.g., write digit line505-1illustrated inFIG. 5) may be precharged to Vcc. For example, a precharge transistor such as Precharge2 transistor516-2shown inFIG. 5may be enabled to precharge the write digit line to Vcc. Subsequently, a row different than the rows previously activated may be activated, as described in connection withFIG. 5.

Once the logical operation has been performed, a result of the XOR logical operation may be transferred to a row different than the rows previously activated (e.g., to write rowN209-2Nshown inFIG. 2). In some embodiments, the result of the XOR logical operation may be stored in a memory cell coupled to the write row (e.g., to a memory cell coupled to write rowN209-2Nillustrated inFIG. 2). After the result of the XOR logical operation has been transferred to the write row that is different than the rows previously activated, the write row that is different than the rows previously activated may be disabled (e.g., closed).

In some embodiments, the result of the XOR logical operation may be read out of the sensing circuitry via a Column Select line and/or via a Local I/O line, as described in connection withFIGS. 5 and 6, herein. As described above in connection withFIG. 3, a resulting data value read out of the first sense amp (in the absence of performance of the XOR logical operation) may correspond to a data value having a NOR logical operation applied thereto or performed thereon. In some embodiments, resulting data value read out of the second sense amp (in the absence of performance of the XOR logical operation) may correspond to a data value having a NAND logical operation applied thereto or performed thereon

Operations to perform a logical XOR operation in accordance with the disclosure can be summarized as follows:

Precharge read digit line to VCC/2

Activate Read Enable1 and Read Enable2

Activate Reference Enable1 and Reference Enable2

Activate two row lines (e.g., a first row line and a second row line)

Wait for signal to develop on a first sense amplifier and a second sense amplifier

Disable Reference Enable1 and Reference Enable2

Disable Read Enable1 and Read Enable2

Disable first row line and second row line

Precharge write digit line to VCC

Enable a third row line

Active XOR logical operation component

Disable third row line