Power control unit that provides one of a plurality of voltages on a common power rail

A system comprises a bridge, a slot coupled to the bridge, and a power control unit coupled to the slot via a common power rail and coupled to the bridge. An add-in card having one of a plurality of types can be installed in the slot. Upon installing the add-in card, the bridge determines the type of add-in card and asserts a logic signal to the power control unit. Based on the logic signal, the power control unit provides one of a plurality of direct current (“DC”) voltages on the common power rail to the slot.

BACKGROUND

Some computer systems may permit “add-in” cards to be installed into one or more available “slots” in the system. An add-in card may perform any one of a variety of functions such as providing extra memory, providing network connectivity, and providing a graphics accelerator. Add-in cards usually receive power from the system in which the cards are installed. Some add-in cards, however, may require one operating voltage, while other cards may require a different voltage.

BRIEF SUMMARY

In accordance with at least some embodiments of the invention, a system comprises a bridge, a slot coupled to the bridge, and a power control unit coupled to the slot via a common power rail and coupled to the bridge. An add-in card may having one of a plurality of types can be installed in the slot. Upon installing the add-in card, the bridge determines the type of add-in card and asserts a logic signal to the power control unit. Based on the logic signal, the power control unit provides one of a plurality of direct current (“DC”) voltages on the common power rail to the slot.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, various companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to.” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. Further, a reference to a specific voltage level (e.g., 0 VDC, 1.5 VDC, 3.3 VDC, 12 VDC) reflects the exact voltage referenced or an approximation to the referenced voltage. The term “rail” may include any suitable type of electrical connectivity such as a wire, a trace on a circuit board, or a layer or a portion of a layer on, or in, a printed circuit board.

DETAILED DESCRIPTION

FIG. 1shows a system100that may comprise a central processing unit (“CPU”)102, memory104, a north bridge106, a bridge108, a slot110and a power control unit120. The CPU102and memory104couple to the north bridge106. The north bridge106couples via a bus107to bridge108. In at least some embodiments, bridge108may comprise a Peripheral Component Interconnect Extended (“PCI-X”) bus bridge. Slot110includes a connector to which an add-in card125may be installed. As a PCI-X-compliant bridge, bridge108provides a PCI-X-compliant bus118to the slot110. As such, PCI or PCI-X-compliant add-in cards may be installed in slot110. The system100may be representative of variety of electronic systems such as a computer system. Other components (not specifically shown) may be included as well.

In accordance with at least some embodiments of the invention, an add-in card125that may be installed in slot110may receive operating voltage from the power control unit120. Different types of add-in cards (e.g., PCI, PCI-X mode 1, PCI-X mode 2) may have different voltage requirements. In the embodiment shown inFIG. 1, the power control unit120is adapted to provide a plurality of DC voltages to the slot110via the VIO PWR power rail116. Such voltages may comprise a first operating voltage117or a second operating voltage119. Additional or different voltages can be provided as desired depending on the requirements of whatever add-in cards the system is designed to accommodate.

The slot110provides logic signals111and113to the PCI-X bridge108. Other signals may be provided as well. Signal111is a PCI-X capability (“PCIXCAP”) signal and specifies whether the add-in card125that is installed in slot110is PCI-X capable. The PCIXCAP signal111may be encoded so that, for example, a logic low (“0”) may signify that the add-in card125is not PCI-X-compliant and that a logic high (“1”) may signify that the add-in card is PCI-X-compliant.

A PCI-X add-in card125may be operable in a plurality of modes, for example, “mode 1” and “mode 2.” Mode 1 generally permits operation at a first predetermined frequency (e.g., 133 MHz), while mode 2 permits operation at a higher second predetermined frequency (266 MHz). Signal113is labeled as “mode 2” and specifies whether the add-in card125is mode 2 compliant. As asserted mode 2 signal means that the card is mode 2 compliant, while a deasserted mode 2 card means that the card is mode 1 compliant. Further, a mode 1 card may require a first operating voltage, while a mode 2 card may require a second operating voltage. In accordance with at least some embodiments of the invention, the first operating voltage associated with mode 1 cards may be voltage117(e.g., 3.3 VDC), while the second operating voltage associated with mode 2 cards may be voltage119(e.g., 1.5 VDC).

Referring still toFIG. 1, during system initialization the PCI-X bridge108receives the PCIXCAP and mode2signals111and113, respectively. In response, the PCI-X bridge108asserts a VIO signal112to the power control unit120. The VIO signal encodes whether the power control unit120is to provide voltage117(3.3 VDC) or119(1.5 VDC) to the add-in card125installed in slot110. In some embodiments, a logic high for the VIO signal may indicate the presence of a mode 1 (3.3 VDC) add-in card125. A logic low for the VIO signal may indicate the presence of a mode 2 (1.5 VDC) add-in card. The PCI-X bridge108or other suitable logic in the system100also may assert a power good (“PGOOD”) signal114when the power voltage(s) in the system are at an equilibrium state and functional. Armed with information indicating whether the first or second operating voltage117or119is to be provided to the card and whether the power voltage(s) are equilibrated, the power control unit120provides the correct operating voltage on rail116to the add-in card125in slot110. As such, rail116comprises a common power rail over which one of a plurality of voltages can be provided to a card.

Referring now toFIG. 2, an embodiment of the power control unit120is shown as comprising a time delay130, a pair of power switches132and134, a first logic gate136, a second logic gate138, and an inverter140. The logic gates136and138may comprise AND or other suitable logic gates. The VIO logic signal112is provided as an input to each of the logic gates136,138. The inverter140inverts the VIO logic signal112and thus provides an inverted form of the VIO signal to logic gate138. The PGOOD signal114is provided to a time delay130and then from the time delay to each of the logic gates136,138. The output signals137and139from the logic gates136,138are asserted high by the respective logic gates when both input signals to each gate are asserted high. The PGOOD signal114is asserted high when the bridge determines that the power voltages in the system are at an equilibrium state and functional. As such, the output signal137of logic gate136is asserted high when the VIO logic signal112is asserted high. When the VIO logic signal is high (indicating mode 1 and thus 3.3 VDC is to be provided to the slot's VIO PWR rail116), the inverter140causes the VIO signal to be low as provided to logic gate138thereby forcing the output139of logic gate138to be low. Conversely, when the VIO signal is low (indicating mode 2 and thus 1.5 VDC is to be provided to the slot), the output signal137of gate136will be low and the output signal139of gate138will be high.

The time delay130comprises resistors R1, R2, C1, diode D1and a pair of Schmidt triggers150coupled together as shown. The time delay130implements an RC time constant by resistor R2and capacitor C1which slows down the assertion of the PGOOD signal114and causes the rising and/or falling edges of PGOOD to change at a slower rate. The Schmidt triggers150cause the falling and rising edges of the PGOOD to change at a faster rate as is commonly known.

The resistors R3, R4, R5and R6function as pull down resistors on the input signals to gates136and138to strap the inputs to a ground potential during initialization. These resistors prevent the inputs to gates136,138from floating.

The power switch132comprises resistors R7-R11, diode D2, and transistors Q1, Q2and Q3. Resistor R7and diode D2are coupled in series and to the base of transistor Q1. Resistor R8couples the base of transistor Q1to a ground potential thereby functions to maintain transistor in an “off” (i.e., non-conducting) state during at least an initial portion of the system initialization. Transistor Q1couples through resistor R9to the base of transistor Q2. Resistors R10and R11couple transistors Q1and Q2to a12VDC supply as shown. Transistor R12couples to the collector of transistor Q2and to the gate of transistor Q3, which may be implemented as a field effect transistor (“FET”). The power switch134is configured similarly but may have two output FETs Q6and Q7to provide sufficient current capacity to the add-in card. The FET Q3functions to switch 3.3 VDC voltage onto the common power rail (VIO PWR116), while FETs Q6and Q7function to switch 1.5 VDC voltage onto the power rail.

The operation of the power control unit120is as follows. The R8and R14pull down resistors force transistors Q1and Q4to be off initially (i.e., before the system performs its initialization). As such, all output FETs Q3, Q6and Q7are off thereby forcing the voltage on the VIO PWR116to be at the ground potential initially. As will be explained below, the power control unit120permits either FET Q3to be on or FETs Q6and Q7to be on, but not all three FETs to be on simultaneously. Thus, the power control unit120prevents a voltage contention situation from occurring in which FET Q3would be attempting to force 3.3 VDC onto VIO PWR116at the same time FETs Q6and Q7are attempting to force 1.5 VDC onto VIO PWR116.

The operation of the power control unit120now will be explained when the VIO signal112transitions from the logic low (0) to logic high (1) states thereby indicating that the add-in card should be operated as a mode 1 card meaning that 3.3 VDC is to be provided on the VIO PWR rail116. When the VIO signal112transitions from 0 to 1,the output signal137of logic gate136changes from logic 0 to logic 1. In response, transistor Q1turns on and transistor Q2turns off by action of transistor Q1. Once Q2is off, the gate input of transistor Q3transitions from 0 VDC to 12 VDC, thereby turning on transistor Q3. With transistor Q3on, 3.3 VDC is provided on the common power rail (VIO PWR116).

With VIO at the logic 1 state, the output signal from inverter140is 0 thereby causing output signal139from logic gate138to be low and forcing transistor Q4to be off. With transistor Q4off, transistor Q5turns on thereby forcing transistors Q6and Q7to remain off. As such, only the 3.3 VDC voltage through transistor Q3(not the 1.5 VDC voltage via transistors Q6and Q7) is provided on VIO PWR116.

The operation of the power control unit120now will be explained when the VIO signal112transitions from the logic high to low states thereby indicating that the add-in card should be operated as a mode 2 card meaning that 1.5 VDC is to be provided on the VIO PWR rail116. When VIO transitions from 1 to 0,the output of inverter140transistors from 0 to 1,and the output signal139of logic gate138changes from logic 0 to logic 1. In response, transistor Q4turns on and transistor Q5turns off by action of transistor Q4. Once Q5is off, the gate inputs of transistors Q6and Q7transitions from 0 VDC to 12 VDC, thereby turning transistor on transistors Q6and Q7. With transistors Q6and Q7on, 1.5 VDC is provided on the common power rail (VIO PWR116).

With VIO at the logic 0 state, the output signal137from logic gate136is low which causes transistor Q1to be off. With transistor Q1off, transistor Q2turns on thereby forcing transistor Q3to remain off. As such, only the 1.5 VDC voltage through transistors Q6and Q7(not the 3.3 VDC voltage via transistor Q3) is provided on VIO PWR116.

A variety of components values may be used for the resistors and capacitors depicted inFIG. 2. The values provided in Table 1 below are exemplary only.

During power down of system100, the power control unit120shuts off power to the slot110generally when the power voltages in the system begin to droop (i.e., fall below predetermined threshold levels). Specifically, the power switches132and134cause the output FETs Q3, Q6and Q7to be off when the 12 VDC power drops to a level that precludes the FETs from being kept on. Accordingly, the power control unit120ensures safe shutting down of the system in a manner that precludes voltage contention on the VIO power rail116.

FIGS. 3 and 4illustrate an embodiment of the invention that supports “hot plug” capability. Hot plug capability permits a card to be removed from or added to a system100while the system is otherwise fully operational.FIG. 3illustrates the creation of two signals, VIO_3.3_SEL181and VIO_1.5_SEL183, based on the VIO signal112. When asserted, signal VIO_3.3_SEL181causes the 3.3 VDC FET Q3to turn on. Further, when asserted, signal VIO_1.5_SEL183causes the 1.5 VDC FETs Q6and Q7to turn on. The VIO signal112is provided to one input of an AND gate180and via resistor R20and inverters170and172to another input of AND gate180. Capacitor C10couples to the resistor R20thereby forming an “RC” time delay. Resistor R20and capacitor C10may be any suitable values such as 10 kohms and 0.10 microfarads, respectively. The AND gate180thus receives the same signal on its inputs, but one input includes a time delay.

The other branch of the circuit shown inFIG. 3includes an AND gate182and is similarly or identically configured to that described. Resistor R21and capacitor C11form an RC time delay for the input to the AND gate182. Inverter182causes the VIO signal to be inverted as it is provided to the branch of the circuit comprising the AND gate182. The inverter184generally causes the VIO_3.3_SEL and VIO_1.5_SEL signals181and183to be at opposite polarities from each other. In general, VIO_3.3_SEL181is high when VIO112is high and VIO_1.5_SEL is high when VIO112is low. The time delays caused by the R20/C10combination and the R21/C11combination prevent both the VIO_3.3_SEL and VIO_1.5_SEL signals from being high simultaneously, thereby preventing voltage contention on the VIO power rail116.

FIG. 4illustrates a portion of the power control unit120with hot plug capability. Specifically,FIG. 4shows the time delay130for the PGOOD signal114and the AND gates136and138as described above. The PGOOD signal, with time delay, is provided as an input to both AND gates136. The AND gate136further receives the VIO_3.3_SEL signal, generated as shown in the exemplary embodiment ofFIG. 3, as an additional input. Similarly, the AND gate138further receives the VIO_1.5_SEL signal as an additional input. The output signals137,139from gates136,138are processed as shown inFIG. 2.

The embodiment ofFIG. 4permits a card to be added to or removed from the slot110while the system100is in operation. For example, a 3.3 VDC card may be removed from the system and, in its place, a 1.5 VDC card may be installed. Such a change in configuration thus may result in a change in the VIO voltage to the slot110. The embodiment ofFIGS. 3 and 4will permit this transition to occur without voltage contention on the VIO power rail116.