Interface circuit as well as method for receiving and/or for decoding data signals

In order to provide an interface circuit (100; 100′) as well as a method for receiving and/or for decoding, in particular for recovering, data signals (D; R, G, B), in particular high speed data signals, for example high speed sequential digital data signals, wherein at least one sampling clock signal (SC), in particular at least one multi-phase sampling clock signal (PC[n-1:0]) with n different phases, and/or the data signals (D; R, G, B) are delayed, and wherein it is possible to optimize the components, in particular the analog components, for a fixed operating frequency, it is proposed that the sampling clock signal (SC), in particular the multi-phase sampling clock signal (PC[n-1:0]), is asynchronous—to at least one interface clock signal (IC), by which the interface circuit (100; 100′), in particular the input of the interface circuit (100; 100′), can be provided with, and/or to the data signals (D; R, G, B).

The present invention relates to an interface circuit for receiving and/or for decoding, in particular for recovering, data signals, in particular high speed data signals, for example high speed sequential digital data signals, the interface circuit comprising the features of the preamble of claim1.

The present invention further relates to a method for receiving and/or for decoding, in particular for recovering, such data signals, the method comprising the steps of the preamble of claim8.

Conventional interfaces convey high bandwidth information over a limited number of transmission lines; this is achieved by high speed sequential binary transmission techniques. For graphic applications, for example the D[igital]V[isual]I[nterface] standard according to the DVI version 1.0 specification dated Apr. 2, 1999 (cf. http://www.ddwg.org/) has become increasingly popular and replaces more and more prior analog interfaces.

Beside the DVI standard, H[igh-]D[efinition]M[ultimedia]I[nterface] (cf. http://www.hdmi.org/) is an industry-supported, uncompressed, all-digital audio/video interface. HDMI provides an interface between any compatible digital audio/video source, such as a set-top box, a D[igital]V[ersatile]D[isc] player, or an A[udio]/V[ideo] receiver and a compatible digital audio and/or video monitor, such as a D[igital]T[ele]V[ision]. In this context, the HDMI standard is basically backwards-compatible with the DVI standard, i. e. a DVI source can drive an HDMI monitor, or vice versa, by means of a suitable adapter or cable.

The DVI standard demands transmission rates up to 1.65 Gigabit per second; however, due to long transmission lines and/or due to low quality cables, the skew between the data channels as well as between the data channel and the clock channel can be well above the bit duration. A receiver has to compensate for these skews and has to adapt to varying skews under changing transmission conditions (for example bending cables).

A conventional method to cope with high skews is to dynamically adjust the relation between the data D and a sampling clock SC (=synchronous sampling technique with phase adjust; cf.FIG. 4A). A prior art synchronous sampling architecture A as shown inFIG. 1(with the elements to the left of the dotted line L residing in the analog/mixed signal design domain and with the elements to the right of the dotted line L residing in the digital domain) regenerates the sampling clock SC (bit-clock or fractions of it) from the interface clock IC via a phase-locked loop PLL.

A delay-locked loop DLL delays the sample clock SC such that sampling takes place in a sampler S right in the middle of the eye diagram of the transmitted data signal (for instance by correlating the non-sampling edge of a fifty percent duty cycle sampling clock with data transitions).

Alternatively, the delay-locked loop DLL may delay the data signal (cf. dotted wires inFIG. 1). In other words, the correlation of interface clock IC and data D is adjusted with the delay-locked loop DLL either in the clock path (=upper path inFIG. 1) or in the data path (=lower path inFIG. 1).

To reduce the maximum system frequency an architecture with multiple sampling phases based on the same principle can be constructed.

Finally, the sampled payload bits are accumulated or aggregated to a sequence containing at least one full word. This is achieved in a collector C by collecting a number of bits which is equal to twice the maximum word length, i. e. to two words. Since a phase correlation between data D and interface clock IC cannot be assumed, the word boundaries can only be detected from the data stream itself in a frame detector FD. Special coding techniques are employed on the transmitter side in order to allow proper word selection in a word selecter WS.

A further conventional method to cope with high skews is represented by the synchronous super sampling technique ofFIG. 4B. An example for a receiver circuit for high speed sequential binary data can be found in prior art document U.S. Pat. No. 5,905,769. Synchronous super sampling replaces the analog adjustment of the sampling phase by collecting a multitude of samples per bit (also called over-sampling) and selecting the proper sample afterwards, in the digital domain.

In a prior art synchronous super sampling architecture as A′ shown inFIG. 2(with the elements to the left of the dotted line L being analog and with the elements to the right of the dotted line L being digital), the sampling clock SC (bit-clock or fractions of it) is derived from the interface clock IC with a phase-locked loop PLL. A delay-locked loop DLL generates a multi-phase sampling clock PC[n-1:0] with n different phases. The multitude of sampling phases may also be directly generated by means of a multi-phase PLL.

The n individual sampling clocks PC[n-1], . . . , PC[0] are skewed by a phase delay of phi=t_SC/n, like depicted inFIG. 3. N samples in the form of an n-bit vector of samples are collected with the synchronous multi-phase clock, i. e. with every sampling clock SC, which contains p payload bits; s super samples per payload bit p are provided (n=p*s); in other words, several (namely p) payload bits may be extracted from aggregated or collected samples s.

Some of the samples s may have been taken during transitions of the data line and are therefore not reliable but super sampling assures that a majority of samples is correct; the optimal sampling phase is calculated and/or selected and/or filtered based on this majority assumption.

The word recovery is typically performed as described with reference to the conventional synchronous sampling example ofFIG. 1(inFIG. 2, the reference numeral BS denotes a bit select unit and the reference numeral PD denotes a phase detect unit).

Regarding an interface circuit as defined above in the chapter “Technical field” as well as a method as defined above in the chapter “Technical field”, multi-phase clocks are used; however, these multi-phase clocks have a fixed ratio to the data rate, as can be taken for instance from the following prior art documents:

Prior art document U.S. Pat. No. 6,272,193 B1 refers to a receiver to recover data encoded in a serial communication channel wherein it is relied on a (fixed) plurality of samples per symbol; a data phase record is kept.

In prior art document U.S. Pat. No. 6,556,640 B1, a digital phase-locked loop circuit as well as a signal regeneration method are disclosed. A multi-phase sampling frequency being almost the same like the bit rate is required in prior art document U.S. Pat. No. 6,556,640 B1; sampling takes place by selecting the right clock and by delaying the data.

Prior art document U.S. Pat. No. 6,611,219 B1 discloses an oversampling data recovery apparatus as well as a corresponding method. However, a fixed (integer) ratio of samples per bit is assumed; besides, according to prior art document U.S. Pat. No. 6,611,219 B1 counters for each group of phases are employed in order to count the occurrence of data transitions for this phase.

Prior art document US 2003/0091137 A1 refers to a transition detection, validation and memorization circuit. It is relied on a fixed ratio between sampling clock and data rate; for phase detection a rather special algorithm is employed.

In prior art document US 2004/0091073 A1, a data recovery circuit, a phase detection circuit as well as a method for detecting and correcting phase conditions are revealed. A first group of samples and a second group of samples are separated by half a data period; moreover the sampling clock is adjusted in a traditional phase-locked loop kind of way.

Starting from the disadvantages and shortcomings as described above and taking the prior art as discussed into account, an object of the present invention is to further develop an interface circuit as defined above in the chapter “Technical field” as well as a method as defined above in the chapter “Technical field” in such way that the components, in particular the analog components, as for example the phase-locked loop unit, the delay-locked loop unit and the sampling means, can be optimized for a fixed operating frequency.

The object of the present invention is achieved by an interface circuit comprising the features of claim1as well as by a method comprising the features of claim8. Advantageous embodiments and expedient improvements of the present invention are disclosed in the respective dependent claims.

The present invention is principally based on the technical idea of an asynchronous sampling and data recovery architecture and method for high speed digital interfaces; therefor, an apparatus as well as a method for reception and data recovery of high speed sequential digital signals are provided.

The present invention supports interfaces with a dedicated clock signal and with an implicit clocking by transitions in the data signal; according to the present teaching, the reception and the decoding of high speed sequential digital signals, for example on D[igital]V[isual]I[nterface] basis and/or on H[igh-]D[efinition]M[ultimedia]I[nterface] basis, is enabled. In this way, the present invention exhibits higher design robustness and flexibility compared to conventional solutions.

In particular, the present innovation utilizes an asynchronous super sampling architecture. Thus the at least one sampling clock can be maintained independent of the transmission frequency, i. e. at least one free running sampling clock is provided.

In particular, the present invention neither tries to determine a correct sampling phase nor assumes a fixed (integer) ratio of samples per bit nor has counters for each group of phases in order to count the occurrence of data transitions for this phase (like for instance in prior art document U.S. Pat. No. 6,611,219 B1). However, the data is extracted from measuring the run-length of the data and/or from measuring the run-time of the data.

Unlike various prior art solutions where a multi-phase sampling frequency being almost the same like the bit rate is required (cf. for example prior art document U.S. Pat. No. 6,556,640 B1), the sampling frequency according to the present invention is arbitrary. Whereas sampling takes place in prior art by selecting the right clock and by delaying the data, according to a preferred implementation of the present invention the clocks are not selected but the correct sample is processed and selected from the oversampled data without further sampling.

According to an advantageous embodiment of the present invention, sampling circuitry, such as P[hase-]L[ocked]L[oop], D[elay-]L[ocked]L[oop] and sampler(s), can be optimized for a fixed sampling frequency. Skews between the clock and the data channels can be compensated with digital processing. Adaptation of varying skews happens instantly and is not limited by analog filter loops.

Optionally the clock period can be obtained from data channels with an appropriate clocking scheme. For lower bit rates robustness improves due to the increased number of samples per bit. There is no minimum transmission rate implied by the bandwidth of analog components.

The advantages of the fixed clock super sampling architecture according to the present invention can be summarized as follows:optimization of analog components, as for example of P[hase-]L[ocked]L[oop], of D[elay-]L[ocked]L[oop] and of sampler(s), for a fixed operating frequency;high speed adaptation to phase variations as well as to bit rate variations, not limited by analog filter loops;optional clock recovery from the data stream;increased robustness for lower bit rates;no lower frequency limit, operation down to D[irect]C[urrent] bit rate.

The present invention finally relates to the use of at least one interface circuit as described above and/or of the method as described above for receiving and/or for decoding, in particular for recovering, high speed sequential digital data signals on the basis of the D[igital]V[isual]I[nterface] standard and/or on the basis of the H[igh-]D[efinition]M[ultimedia]I[nterface] standard by way of an asynchronous sampling technique, in particular by way of an asynchronous super sampling technique, for example by maintaining the sampling clock signal independent of the transmission phase and/or of the transmission frequency of the data signals.

The present invention is particularly suited for applications with a high and/or varying skew between clock channel and data channel. One or multiple serial data streams are supported.

The same reference numerals are used for corresponding parts inFIG. 1toFIG. 12.

In order to avoid unnecessary repetitions, the following description regarding the embodiments, characteristics and advantages of the present invention relates (unless stated otherwise)to the first embodiment of the interface circuit100according to the present invention (cf.FIG. 5) as well asto the second embodiment of the interface circuit100′ according to the present invention (cf.FIG. 12),

all embodiments100,100′ being operated according to the method of the present invention.

The present invention is based on receiving and decoding high speed serial data with a sampling clock SC having neither a fixed phase relation nor a fixed frequency relation to the interface clock IC and to the data D (=asynchronous sampling technique; cf.FIG. 4C); in other words, the sampling clock can be maintained independent of the transmission frequency. It is assumed that the sampling clock SC is sufficiently higher than the interface bit rate to guarantee a minimum number of super-samples and that its jitter is well below the phase resolution.

An embodiment100of an asynchronous super sampling architecture is shown inFIG. 5. The elements to the left of the dotted line L are analog; the elements to the right of the dotted line L are digital.

Basically, the asynchronous super sampling device100works as follows:n samples are collected with an asynchronous multi-phase clock PC[n-1:0];up to p payload bits are extracted from every array of n samples;the period and the phase are calculated and/or filtered from edge transitions with sub-sample precision (fractions of the sampling phase resolution);temporal information is processed in binary timestamp arithmetic; andtwo words or more are collected, boundaries are detected and a word is selected.

In more detail, the multi-phase sampling clock SC with n different phases is generated from a free running (crystal) reference clock RC by means of a P[hase-]L[ocked]L[oop]10; this P[hase-]L[ocked]L[oop]10is part of a multi-phase clock generating means10,12.

In this context, it has to be seen with respect to the implementation of the present invention that any means10,12for generating a multi-phase clock can be provided; in other words, such means10,12are not to be coupled to the explicit presence of a P[hase-]L[ocked]L[oop] and/or of a D[elay]L[ocked]L[oop] (some P[hase-]L[ocked]L[oop]s can generate multi-phase clocks directly); only the presence of a multi-phase clock is relevant, and it does not matter how such multi-phase clock has been generated.

The number n of different phases and the sample clock SC have to be high enough to maintain a number s of minimum samples per data bit at the highest possible data rate. The number s of minimum samples has to be equal to or higher than three; a higher number s of minimum samples makes detection more robust.

It is advantageous for the later calculations but not required that the number n of different phases is a power of two. The sampling clock SC has to be low enough to allow the arithmetic processing in the later stages. A lower sampling clock frequency is traded against a higher number of sampling phases; this does not necessarily meanmore multi-phase sampling clock lines PC[n-1:0] originating from the D[elay-]L[ocked]L[oop]12(n phases), this D[elay-]L[ocked]L[oop]12being also part of the multi-phase clock generating means10,12, and/ormore samplers16,18.

The multi-phase sampling clock frequency can alternatively be a multiple of the sampling clock SC, and multiple samples can be accumulated for the n-bit vector. Moreover both edges of PC[n-1:0], i. e. PC[n-1] and PC[0] might be used for sampling.

The interface clock IC is sampled with all phases of the multi-phase sampling clock lines PC[n-1:0] in the samplers16,18. The occurrence (reference numeral det inFIG. 5) and the phase position (reference numeral pos inFIGS. 5 and 6) of negative and/or positive clock edges within a sampling clock cycle is detected from the sampled pattern; in this context, the sampling clock cycles are counted in a cycle counter20.

Regarding the occurrence det and the phase position pos of negative and/or positive clock edges within a sampling clock cycle, reference is also made toFIG. 6where a transition recording is illustrated. A pre-filter may be applied to the sampled pattern to eliminate spikes. With a sampling clock SC higher than the interface clock IC, a maximum of one edge of a given polarity P within one sampling clock cycle can be assured.

A signal transition phase (reference numeral pos inFIGS. 5 and 6) together with the number (reference numeral cnt inFIGS. 5 and 6) of the sampling clock cycle it is occurring in, shall be called the timestamp T=cnt.pos of the transition. A free-running sampling clock cycle counter20delivers continuous increments of the cycle number cnt-Timestamps T can be related to each other with simple binary arithmetic.

A clock calculator40as shown inFIG. 5and in more detail inFIG. 7determines the time between two subsequent I[nterface]C[lock] transitions of equal polarity P (H[igh]-L[ow] or L[ow]-H[igh]) by subtracting their timestamps T=cnt.pos. The binary result represents the actual I[nterface]C[lock] period t_ifc_r[aw].

Subsequent I[nterface]C[lock] period measurements are combined to a filtered result t_ifc_f[iltered] with fractional precision, using a filter function42, for instance a F[inite]I[mpulse]R[esponse] filter or an I[nfinite]I[mpulse]R[esponse]. The I[nterface]C[lock] period is a known multiple (factor r; cf. alsoFIGS. 1 and 2) of the bit clock period. With a binary division the bit clock period t_bit (cf. alsoFIG. 5) can be calculated.

The clock information is not necessarily derived from a interface clock unit or from a interface clock channel14(leading to a so-called explicit interface clock) but may also be derived from the data (leading to a so-called implicit or data-embedded interface clock); for instance, the I[nterface]C[lock] period may also be derived form the transition information (pos[ ], pol[ ], N) of the data stream between the edge position decoder unit32and the run-length decoder unit or run-time decoder unit60(cf.FIG. 5); this however requires a coding scheme that facilitates clock recovery.

One or multiple data signals are sampled with all n phases of the clock PC[n-1:0]. A maximum of 1+floor(n/s) data transitions may occur in one sampling clock cycle (wherein “floor” returns the next lowest integer value by rounding down the input value, i. e. the ratio of the number n of different phases to the number s of super samples per payload bit p). The position pos[ ] and the resulting signal polarity pol[ ] of each transition is decoded from the sampled pattern in the transition recording (cf.FIG. 6). A pre-filter may be applied to the sampled pattern to eliminate spikes.

FIG. 8illustrates the run-length data decoding of the present invention being implemented by a run-length data decoding algorithm or by a run-time data decoding algorithm. The payload bits p are extracted from the position information pos[ ] and from the polarity information pol[ ] by measuring the time t[x]=T[x+1]−T[x] between signal transitions T[x]=cnt.pos. The timestamp T[0] marks the last transition prior to the current sampling clock cycle.

The pulse duration t[x]=T[x+1]−T[x] between signal transitions T[x] is converted with a rounding function “round” into a code-run-length run[x]=round(t[x]/t_bit) in units of bits. In this context, the rounding function round works such thatpulse durations t[x] shorter than half the bit clock period t_bit (, i. e. t[x]/t_bit less than 0.5) are considered invalid,pulse durations t[x] between half the bit clock period t_bit and 1.5 times the bit clock period t_bit (, i. e. 0.5<t[x]/t_bit<1.5) represent one bit,pulse durations t[x] between 1.5 times the bit clock period t_bit and 2.5 times the bit clock period t_bit (, i. e. 1.5<t[x]/t_bit<2.5) represent two bits,pulse durations t[x] between 2.5 times the bit clock period t_bit and 3.5 times the bit clock period t_bit (, i. e. 2.5<t[x]/t_bit<3.5) represent three bits,

and so on.

In case of asymmetric rise times and/or in case of asymmetric fall times, different rounding thresholds can be used for high sequences and/or for low sequences. Dependencies of the rise time and/or of the fall time on the preceding run-length run[x] can be taken into account by varying the rounding thresholds per run-length r[x]. Rounding thresholds may also be dynamically adjusted based on information extracted from the data stream.

Additionally the time period t[N]=(cnt+1).0−T[N] elapsing from the last signal transition T[N] within the actual sampling clock cycle to the end of the cycle is computed. The number run[N]=floor(t[N]/t_bit) of complete bits fitting into this time period t[N] is calculated using the floor function, i. e. rounding down to the next integer value.

If no bits fit into this time period t[N], the last actual transition is stored for the next sampling clock cycle. If payload bits p can be extracted already, a hypothetic last transition position T*[0]=T[N]+run[N]*t_bit is calculated and stored for the next sampling clock cycle.

Long bit-clock-cycles (t_bit) or long code-runs lead to sampling clock cycles with no signal transition T. In this case the last signal transition T[N] equals the timestamp T[0] and may have occurred several sampling clock cycles in the past.

If the bit clock period t_bit is longer than the sampling clock cycle time t_SC, several sampling clock cycles may pass without a payload bit p being extracted. The width of the digital sampling clock cycle counter20(cf.FIG. 5) has to be dimensioned accordingly.

For long code-runs with the bit clock period t_bit shorter than a sampling clock cycle time t_SC, the timestamp T[0] will always be in the previous sampling clock cycle because payload bits p are extracted even without transitions happening. However, a high maximum run-length requires more precision in the calculation of the bit clock period t_bit. If a code-run spans over several I[nterface]C[lock] cycles, the bit clock period t_bit will be updated several times. This desirable integration effect reduces the required accuracy for the bit clock period t_bit.

The run-length decoding algorithm (cf.FIG. 8) may also be used with synchronous super-sampling. In this case the sampling clock time base correlates with the interface clock, and the bit clock period t_bit=s*Phi (cf.FIG. 3) is constant. Sampling the I[nterface]C[lock] signal as well as the clock calculation becomes obsolete.

FIG. 9Adepicts in more detail the run-length decoder circuit60(as also shown inFIG. 5) for up to four transitions T[1]=cnt.pos[1], T[2]=cnt.pos[2], T[3]=cnt.pos[3], T[4]=cnt.pos[4] within one sampling clock cycle. The unused transition timestamps are “shifted” out of the subtraction chain64using four multiplexers62a,62b,62c,62dbeing connected in advance of the subtraction chain64.

As can be taken fromFIG. 9A, said subtraction chain64computes the time differences t[x]=T[x+1]−T[x] between the timestamps T[x]=cnt.pos a; to this aim, said subtraction chain64comprises five subtractor units64a,64b,64c,64d,64eeach of which being assigned to a network66,68as shown inFIGS. 10A and 10B. By way of run-length comparison, the computed time differences t[0], t[1], t[2], t[3], t[4] are compared against multiples of the bit clock period t_bit by means of the networks66,68.

In more detail, the so-called round network66accordingFIG. 10Ais designed to compare the time differences t[0]=T[1]−T[0], t[1]=T[2]−T[1], t[2]=T[3]−T[2] and t[3]=T[4]−T[3] against half-numbered multiples of the bit clock period t_bit:by the first (, inFIG. 10Aleft) comparison path66athe time differences t[0], t[1], t[2], t[3] are compared against half the bit clock period t_bit,by the second comparison path66bthe time differences t[0], t[1], t[2], t[3] are compared against 1.5 times the bit clock period t_bit,by the third comparison path66cthe time differences t[0], t[1], t[2], t[3] are compared against 2.5 times the bit clock period t_bit,by the fourth comparison path66dthe time differences t[0], t[1], t[2], t[3] are compared against 3.5 times the bit clock period t_bit, andby the fifth (, inFIG. 10Aright) comparison path66ethe time differences t[0], t[1], t[2], t[3] are compared against 4.5 times the bit clock period t_bit,

the five comparison paths66a,66b,66c,66d,66ebeing parallel to each other.

The multiplications with constant half-numbered factors (0.5, 1.5, 2.5, 3.5, 4.5) can be economically built with shift and add operations to the binary t_bit (=bit clock period); reference numeral66fdenotes a thermometer decoder the output signal run[0], run[1], run[2], run[3] is treated with.

In contrast thereto, the so-called floor network68accordingFIG. 10Bis designed to compare the time difference t[4]=T[5]−T[4] against whole-numbered multiples of the bit clock period t_bit:by the first (, inFIG. 10Bleft) comparison path68athe time difference t[4] is compared against (one times) the bit clock period t_bit,by the second comparison path68bthe time difference t[4] is compared against two times the bit clock period t_bit,by the third comparison path68cthe time difference t[4] is compared against three times the bit clock period t_bit,by the fourth comparison path68dthe time difference t[4] is compared against four times the bit clock period t_bit, andby the fifth (, inFIG. 10Bright) comparison path68ethe time difference t[4] is compared against five times the bit clock period t_bit,

the five comparison paths68a,68b,68c,68d,68ebeing parallel to each other.

The multiplications with constant whole-numbered factors (1, 2, 3, 4, 5) can be economically built with shift and add operations to the binary t_bit (=bit clock period);

reference numeral68fdenotes a thermometer decoder the output signal run[4] is treated with.

The circuitry inFIG. 9Bis also part of the run-length decoder circuit60and is designed to align the respective signal polarity values pol[0], pol[1], pol[2], pol[3], pol[4] of the respective transition T[0], T[1], T[2], T[3], T[4] with the respective run-length result run[0]=round(t[0]/t_bit), run[1]=round(t[1]/t_bit), run[2]=round(t[2]/t_bit), run[3]=round(t[3]/t_bit), run[4]=floor(t[4]/t_bit), resulting in the respective bit-value bit[0], bit[1], bit[2], bit[3], bit[4].

(both output from the run-length decoder60as shown inFIG. 5andFIGS. 9A,9B) are accumulated or aggregated into code words by means of the word aggregator/collecting unit70also shown inFIG. 5.

A resulting bit vector vec contains the history of decoded bits in temporal order. New bits bit[ ] are shifted in (<--> reference numeral SH inFIG. 11) by a run-length run[ ] number of times and in temporal order. A number of run[ ] old bits are shifted out (<--> reference numeral SH inFIG. 11); the reference numeral BSH denotes the respectively assigned barrel shifter.

The bit vector vec carries twice the number of bits per word. This assures that the bit vector vec always contains one complete word. Moreover, the total number of newly inserted bits is calculated in order to support the word selection. Whenever the bit vector vec contains sufficient new bits for one word, they are aligned and validated for one output cycle.

A frame detector80as shown inFIG. 5recognizes word boundaries based on the encoding scheme. This may only be possible for a few synchronization words, which are inserted on a regular basis. Without synchronization, words are output only based on the number of newly decoded bits.

FIG. 12depicts the block diagram of an architecture for a high speed digital interface, namely for a D[igital]V[isual]I[nterface] receiver circuit (with the elements to the left of the dotted line L being analog and with the elements to the right of the dotted line L being digital), employing the asynchronous sampling and data recovery architecture and method according to the present invention, as exemplified byFIGS. 4C to 11.

A fixed reference clock SC of 250 Megahertz is derived from a free running 25 Megahertz crystal oscillator8by means of a P[hase-]L[ocked]L[oop]10; this P[hase-]L[ocked]L[oop]10is part of a multi-phase clock generating means10,12. A D[elay-]L[ocked]L[oop]12being also part of the multi-phase clock generating means10,12generates thirty-two sampling phases PC[31], PC[30], . . . , PC[1], PC[0] with equidistant spacing and with low jitter, thus providing a sampling resolution of 125 Picoseconds=1/(32*250 Megahertz).

The 25 Megahertz to 165 Megahertz [--> maximal bit duration 606 Picoseconds=1/(10*165 MHz)] clock channel14and all data channels R[ed], G[reen], B[lue] are sampled with arrays of samplers (=D-type register16assigned to the clock channel14, respective D-type registers18assigned to the respective data channels R[ed], G[reen], B[lue]).

Edge position decoders30,32are respectively assigned to the samplers16,18and detect signal transitions of the clock signal with positive or negative polarity; the edge position decoders30,32signalize their position within the sampling clock cycle as well as the fact that a transition occurred. The DVI symbol clock period is computed in a clock calculator40and divided by ten in a divider unit50in order to obtain the duration of one bit.

InFIG. 12, only the red data channel R[ed] is depicted but the green data channel G[reen] and the blue data channel B[lue] are to be replicated. For the red data channel R[ed], for the green data channel G[reen] and for the blue data channel B[lue], edge position decoders30,32are used; these edge position decoders30,32are designed to detect up to five bit transitions (each vector of thirty-two samples contains up to five bit transitions).

The number run[ ] of bits between transitions is computed in the run-length-decoder60(cf. alsoFIGS. 8 to 10B). D[igital]V[isual]I[nterface] uses an eight to ten bit D[irect]C[urrent]-balanced encoding scheme advantageously limiting the maximum run-length. Newly decoded bits are accumulated or aggregated to a twenty bit vector in the word aggregator unit or word accumulating unit70.

DVI provides word synchronization with reserved control words during video blanking. These words are recognized with the frame detector80, and initialize the word selection in the word selection unit90whenever they occur. After initialization the word selection unit90packages ten bit words purely based on the number of new bits arriving.

For a complete DVI receiver the ten bit symbols have to be decoded to eight bit color data, data enable information and two bits of control information. Moreover, a channel alignment is required, i. e. the color information has to be aligned between the three data transmission channels using the data enable information; this can be performed like with traditional sampling schemes.

The interface clock IC of DVI is equivalent to the word clock WC. It may be desirable to resynchronize the data from the sampling clock domain to the interface clock domain IC.

List of Reference Numerals

100interface circuit (first embodiment; cf.FIG. 5)100′ interface circuit (second embodiment; cf.FIG. 12)8oscillating unit, in particular free running crystal oscillator10,12multi-phase clock generating means10P[hase-]L[ocked]L[oop] unit of multi-phase clock generating means10,1212D[elay-]L[ocked]L[oop] unit (n phases) of multi-phase clock generating means10,1214interface clock unit or interface clock channel16first sampler unit, in particular D-type register, assigned to the interface clock channel1418second sampler unit, in particular respective D-type register, assigned to the respective data channel R[ed], G[reen], B[lue]20cycle counting unit30first edge position decoding unit32second edge position decoding unit40clock calculating unit42filter, in particular function, for instance F[inite]I[mpulse]R[esponse] filter or I[nfinite]I[mpulse]R[esponse], of clock calculating unit4050dividing unit60run-length decoder unit or run-time decoder unit62afirst multiplexing unit of run-length decoding unit6062bsecond multiplexing unit of run-length decoding unit6062cthird multiplexing unit of run-length decoding unit6062dfourth multiplexing unit of run-length decoding unit6064subtraction chain of run-length decoding unit6064afirst subtracting unit of subtraction chain6464bsecond subtracting unit of subtraction chain6464cthird subtracting unit of subtraction chain6464dfourth subtracting unit of subtraction chain6464efifth subtracting unit of subtraction chain6466first network unit, in particular network with function “round”, of run-length decoding unit6066afirst comparison path of first network unit6666bsecond comparison path of first network unit6666cthird comparison path of first network unit6666dfourth comparison path of first network unit6666efifth comparison path of first network unit6666fthermometer decoding unit of first network unit6668second network unit, in particular network with function “floor”, of run-length decoding unit6068afirst comparison path of second network unit6868bsecond comparison path of second network unit6868cthird comparison path of second network unit6868dfourth comparison path of second network unit6868efifth comparison path of second network unit6868fthermometer decoding unit of second network unit6870word aggregating unit or word collecting unit80frame detecting unit90word selecting unitA synchronous sampling architecture (prior art; cf.FIG. 1)A′ synchronous super-sampling architecture (prior art; cf.FIG. 2)bit bit valueB[lue] third data signal or third data channelBS bit selecting unit (prior art; cf.FIGS. 1 and 2)BSH barrel shifting unitBVAL third value signalC word aggregating unit or word collecting unit (prior art; cf.FIGS. 1 and 2)cnt number of cycle of sampling clock SCD data signal or data channeldet occurrence of positive clock edges and/or of negative clock edges within a cycle of the sampling clock SCDLL delay-locked loop unit (prior art; cf.FIGS. 1 and 2)EN enableFD frame detecting unit (prior art; cf.FIGS. 1 and 2)G[reen] second data signal or second data channelGVAL second value signalIC interface clock signal or interface clock unit or interface clock channel (prior art; cf.FIGS. 1 and 2)L dotted line separating analog elements of interface circuit100,100′ from digital elements of interface circuit100,100′n (=p*s) phaseN number of samples, in particular in the form of n-bit vector of samplesp payload bitPC[n-1:0] multi-phase sampling clock signal with n different phasesPD phase detecting unit (prior art; cf.FIGS. 1 and 2)phi phase delayPLL phase-locked loop unit (prior art; cf.FIGS. 1 and 2)pol signal polarity of transitionpos phase position of positive clock edges and/or of negative clock edges within a cycle of the sampling clock SCR[ed] first data signal or first data channelrun code-run-lengthRVAL first value signals super sampleS sampler unit (prior art; cf.FIGS. 1 and 2)SC sampling clock signalSH shifting unitt timet[ ] time difference, in particular pulse durationt_bit time period of bit clockt_ifc time period of interface clock unit14t_ifc_f filtered time periodt_ifc_r raw time periodt_SC cycle time of sampling clock SCT timestampT*[0] hypothetic last transition positionvec resulting bit vectorW word signalWC word clock signalWS word selecting unit (prior art; cf.FIGS. 1 and 2)WVAL word value signal