Physical coding sublayer with modified bit ordering to improve error burst resiliency

Techniques are provided to provide modified bit sequences generated by the Physical Coding Sublayer (PCS) functional block in a way that considers the subsequent bit-mux operation of the Physical Media Attachment (PMA) sublayer functional block, in order to create symbol sequences for transmission over the physical channels with properties that optimize the performance of the Forward Error Correction (FEC) decoder with error bursts.

TECHNICAL FIELD

The present disclosure relates to network communication.

BACKGROUND

The Ethernet Physical Coding Sublayer (PCS) functional block creates bit sequences for each of its logical output lanes. These bit sequences may then be bitwise-multiplexed (bit-mux) by a Physical Media Attachment (PMA) functional block to create sequences of physical symbols. These symbols are transmitted over noisy channels and may be received with errors, often with bursts of consecutive errors. A Reed-Solomon Forward Error Correction (RS-FEC) code may be used to correct occasional error bursts.

The PCS functional block defined in clause 119 of IEEE 802.3, which followed the RS-FEC of clause 91, creates bit sequences that are handled well by the RS-FEC decoder even with bursts of errors if there is no bit-mux PMA. However, when bit-muxing is applied, the RS-FEC performance is degraded (the higher the muxing ratio, the more degradation is caused).

If a PCS functional block based on clause 119 of IEEE 802.3 is used at 800 Gb/s over four physical lanes (200 Gb/s per lane), the multiplexing (muxing) level is 8:1, which creates an unacceptable degradation.

DETAILED DESCRIPTION

Overview

Presented herein are techniques to provide modified bit sequences generated by the Physical Coding Sublayer (PCS) functional block in a way that considers the subsequent bit-mux operation of the Physical Media Attachment (PMA) sublayer functional block, in order to create symbol sequences for transmission over the physical channels with properties that optimize the performance of the Forward Error Correction (FEC) decoder with error bursts.

In one form, a method is provided for a transmit process including, for each forward error corrected (FEC) codeword of a plurality of FEC codewords of data to be transmitted over a channel, obtaining a symbol from each logical lane of a plurality of logical lanes to which the plurality of FEC codewords have been multiplexed; storing bits for the symbol from each logical lane of the plurality of logical lanes into a memory; and re-ordering bits stored in the memory according to a mapping that permutes the bits stored in memory to produce a re-ordered block of bits such that when the re-ordered block of bits is distributed to a plurality of modified logical lanes equal in number to the plurality of logical lanes and the plurality of modified logical lanes are bit-multiplexed to at least one physical lane, the at least one physical lane obtains a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.

In another form, a method is provided for a receive process including: obtaining a stream of bits received for at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, which plurality of modified logical lanes is equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to a mapping that permuted the original block of bits to produce a re-ordered block of bits distributed to the plurality of modified logical lanes such that when the plurality of modified logical lanes was bit-multiplexed to the at least one physical lane, the at least one physical lane contains a sequence of a groups of bits for a symbol from one forward error corrected (FEC) codeword followed by a sequence of groups of bits for a symbol from another FEC codeword; storing the re-ordered block of bits obtained from the plurality of modified logical lanes to a memory; performing an inverse of the mapping on the re-ordered block of bits stored in the memory to obtain the original block of bits; and distributing the original block of bits to the plurality of logical lanes.

In still another form, a method is provided that is performed by a first device that is in communication with a second device, including: configuring a transmit function to use a modified bit ordering that maps bits from a plurality of logical lanes to a plurality of modified logical lanes that are bit-multiplexed to at least one physical lane for transmission to a second device; configuring a receive function to use a modified bit ordering for processing a stream of bits received from the second device on at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, the plurality of modified logical lanes being equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to the modified bit ordering; receiving an incoming bit stream from the second device; attempting to process the incoming bit stream from the second device with the receive function using the modified bit ordering; and when processing the incoming bit stream using the modified bit ordering is not successful, configuring the receive function of the first device to use an un-modified bit ordering for processing the incoming bit stream from the second device.

Example Embodiments

Presented herein are techniques to generate bit sequences by the PCS functional block in a way that considers the subsequent bit-mux operation of the PMA functional block, in order to create symbol sequences for transmission over the physical channels with properties that optimize the performance of FEC decoder when error bursts occur.

The modified bit sequences are created by relatively simple re-ordering of bits relative to the clause 119 PCS definition of IEEE 802.3. As a result, the change from existing PCS implementations (on both receive and transmit sides) is very easy to implement. In addition, it is easy to switch between the original order and the modified order, to provide backward compatibility with PCS implementations that do not use this bit order (such as the Ethernet Technology Consortium (ETC) PCS).

Similar bit sequences can be generated for 400 Gb/s and 200 Gb/s PCSs when used with 200 Gb/s per lane (two lanes or one lane respectively), to improve the RS-FEC performance in these cases. Backward compatibility with existing PCS designs can be implemented similarly.

While the bit sequences are optimized for 200 Gb/s per physical lane, they also provide an improvement (albeit smaller) over existing PCS bit ordering when used at 100 Gb/s per lane.

Referring first toFIG.1, a diagram is shown of a network communication environment100showing, for simplicity, a first device110-1and a second device110-2configured to engage in network communication with each other. The first device110-1and the second device110-2may be any device capable of engaging in network communication, such as endpoint devices (computers, user devices, etc.) or intervening network devices such as switches, routers, gateways, wireless access points, etc. The first device110-1includes a network interface module112-1that performs operations to enable network communication. Similarly, the second device110-2includes a network interface module112-2. Depending on the particular application, the first device110-1may include a host processor114-1and similarly the second device110-1may include a host processor114-2. The first and second devices110-1and110-2may include one or more additional components related to the application of the device, but for simplicity, those additional components are not shown inFIG.1. There is a connection116between the first device110-1and the second device110-2. The connection116may be a wire or cable, or an optical fiber.

The network interface modules112-1and112-2shown inFIG.1may be configured to implement a network communication protocol according to one or more industry standards, such as specified in IEEE 802.3. To do so, the network interface modules112-1and112-2perform various signal processing operations for a PCS block and a PMA sublayer. Thus, network interface module112-1includes digital logic to implement a PCS block120-1that includes a receive function122-1and a transmit function124-1. The PCS block120-1interacts with a PMA sublayer126-1. The network interface module112-1may further include memory130-1that is used to execute various operations. Similarly, the network interface module112-2includes digital logic to implement a PCS block120-2that includes a receive function122-2and a transmit function124-2. The PCS block120-2interacts with a PMA sublayer126-2. The network interface module112-2may also include memory130-2.

The network interface modules112-1and112-2may be implemented as digital logic in one or more Application Specific Integrated Circuits (ASICs) or in one or more programmable gate arrays (e.g., field programmable gate arrays) or in any combination of fixed or programmable digital processing devices now known or hereinafter developed. Moreover, the functions of the network interface modules112-1and112-2may be implemented partially or entirely as software instructions executed by a microprocessor (or several microprocessors), such as host processors114-1and114-2.

According to the techniques presented herein, the transmit function of a network interface module of a given device may have the capability to be configured to use a modified PCS bit order for transmitting data that minimizes the impact of errors and thus improves FEC performance. In a simple case, the PCS block120-1of the network interface module112-1of the first device110-1has the capability to use the modified PCS bit ordering and the PCS block120-2of the network interface module112-2of the second device110-2has the capability to use the modified PCS bit ordering. In this case, the transmit function124-1(in the first device110-1) is configured to use the modified PCS bit ordering and the receive function122-2(in the second device110-2) is configured to use the modified PCS bit ordering (performing the inverse of the bit ordering performed by the first device110-1), to support use of the modified bit ordering for transmissions from the first device110-1to the second device110-2. Likewise, the transmit function124-2(in the second device110-2) is configured to use the modified PCS bit ordering and the receive function122-1(in the first device110-1) is configured to use the modified PCS bit ordering, to support the modified bit ordering transmissions from the second device110-2to the second device110-1.

However, it is also possible that a given device in the field may not have the capability to be configured to use the modified PCS bit ordering. For example, the first device110-1may have the capability of the modified PCS bit ordering but the second device110-2does not have the capability of the modified PCS bit ordering. Techniques are presented herein for the first device110-1to learn whether or not the second device110-2has the modified PCS bit ordering capability, and to configure the transmit function124-1and receive function122-1according to such determination. When the first device110-1learns that the second device110-2does not have the modified PCS bit ordering capability, then the network interface module112-1of the first device110-1will configure the transmit function124-1to use un-modified PCS bit ordering for transmissions from the first device110-1to the second device110-2, and will configure the receive function122-1to use un-modified PCS bit ordering for processing transmissions received from the second device110-1. Conversely, when the first device110-1learns that the second device110-2does have the modified PCS bit ordering capability, then the network interface module112-1of the first device110-1will configure the transmit function124-1to use modified PCS bit ordering for transmissions from the first device110-1to the second device110-2, and will configure the receive function122-1to use modified PCS bit ordering for processing transmissions received from the second device110-1.

Thus, the techniques presented herein provide for leveraging the benefits of the modified PCS bit ordering when both devices on the ends of the link can use the modified PCS bit ordering, and to revert to un-modified PCS bit ordering when one device on the link cannot use the modified PCS bit ordering. A process for learning whether a far end device is configured to use the modified PCS bit ordering is described in more detail below in connection withFIG.17.

Turning now toFIG.2, a functional block diagram of a PCS block200of the network interface modules112-1and112-2ofFIG.1are shown. The functional block diagram ofFIG.2is derived from theFIG.119-2of the IEEE 802.3 standard specification, with some modifications to explain the modified PCS bit ordering techniques presented herein. The PCS block200includes a sequence of operations for a transmit function (also referred to as a transmit path or transmit process)202of the PCS block, and a sequence of operations for a receive function (also referred to as a receive path or receive process)204of the PCS block200.

The transmit function202includes an encode and rate matching operation210, a transcode operation212, a scramble operation214, an alignment marker insertion operation216, a pre-FEC bit distribution operation218, an FEC encode operation220, a distribution and interleave operation222and a modified bit ordering operation224. Operations210-222may be, in one example, implemented in accordance with the IEEE 802.3 standard specification, or any other standard now known or hereinafter developed. The modified bit ordering operation224corresponds to the modified PCS bit ordering operations mentioned above and is described in more detail below in connection withFIGS.8-14.

Similarly, the receive function204includes a lane deskew operation230, a modified bit re-ordering operation232, an alignment marker lock operation234, a de-skew control operation235, a lane recorder and de-interleave operation236, an FEC decode operation238, a post-FEC interleave operation240, an alignment marker removal operation242, a descramble operation244, a reverse transcode operation246and a decode and rate matching operation248. The lane deskew operation230, modified bit re-ordering operation232, alignment marker lock operation234and de-skew control operation235, are operations performed to undo the modified PCS bit ordering in PMA receive data (if such modified PCS bit ordering was performed in transmitting data from the far end device), and are described in more detail below in connection withFIGS.8-14. Operations236-248may be, in one example, implemented in accordance with the IEEE 802.3 standard specification, or any other standard now known or hereinafter developed.

The transmit function202of the PCS block200operates on transmit data and provides PMA transmit data to a PMA sublayer250. Conversely, the PMA sublayer250provides PMA receive data to the receive function204of the PCS block200.

The PCS block200provides the functions to map packets between the 200GMII/400GMII format, for example, and the PMA service interface format. When communicating with 200GMII/400GMII, as an example, the PCS block200uses an eight octet-wide, synchronous data path, with packet delineation provided by transmit control signals and receive control signals, not specifically shown inFIG.2. When communicating with the PMA sublayer250, the PCS block200, for 200GBASE-R, uses 8 encoded bit streams (also known as PCS lanes) and for the 400GBASE-R, the PCS block200uses 16 encoded bit streams.

According to the techniques presented herein, no changes are made to the PMA sublayer. The re-ordering of bits among the plurality of logical lanes is performed in the PCS transmit and receive functions so that the PMA bit-muxing operation in the transmit direction to create the physical lane content, and the PMA bit de-muxing operation to provide the logical lane content in the receive direction, are not changed. The PMA operations are performed according to the existing relevant standard. A selection may be made as to whether to re-order the bits in the PCS or not, without changing the width of the interface between the PCS and the PMA sublayer, and this can be done separately in the transmit direction and in the receive direction.

Turning now toFIG.3, with continued reference toFIG.2, the modified PCS bit ordering operation224used in the transmit function of the PCS block200is now described. The modified PCS bit ordering operation224is performed after the FEC encode operation220and bit distribution and interleave operation222. For context and as an example, the codewords output by the FEC encode operation220are shown at300-1and300-2. The FEC encode operation220, in accordance with IEEE 802.3, employs a Reed-Solomon FEC (RS-FEC) encoder, denoted RS(n,k), where the symbol size is 10 bits and the RS-FEC code corrects for errors in symbols. The encoder processes k message symbols to generate 2t parity symbols, which are then appended to the message to produce a codeword of n=k+2t symbols. The FEC encoder is an RS(544,514) based FEC encoder, for example. The PCS block200distributes a group of 40×257-bit blocks from tx scrambled am on a 10-bit round robin basis into two 5140-bit message blocks, mA and mB, as described in 119.2.4.5 of the IEEE 802.3 standard specification. These message blocks are then encoded using RS(544,514) encoder into codeword A and codeword B, respectively, and shown at reference numerals300-1and300-2inFIG.3. The RS(544,514) code is based on the generating polynomial given by Equation (119-1) of the IEEE 802.3 standard specification for 400GBASE-R. The codeword polynomial c(x) is a sum of a message polynomial m(x) and a parity polynomial p(x), where the coefficient of the highest power of x, cn-1=mk-1is first and the coefficient of the lowest power of x, c0=p0is last, as defined in Equations 119-2 and 119-3 of the IEEE 802.3 standard specification.

After the data has been FEC encoded, the two FEC codewords300-1and300-2are interleaved on a 10-bit basis by multiplex and 10-bit symbol distribution operation302(which is a more detailed statement of the bit distribution and interleave operation222shown inFIG.2). The IEEE 802.3 standard specification specifies the interleaving of two codewords for the 200GBASE-R PCS and the 400GBASE-R PCS. Taking 400GBASE-R as an example, the result of operation302is that 10-bit symbols are distributed to each of the logical lanes sequentially, the result of which is a plurality of logical lanes.

The modified PCS bit ordering operation224is now described in more detail. At step310, bits for one 10-bit symbol is stored from each of the plurality of logical lanes (e.g., 16 logical lanes) into a block in memory, e.g., a 16×10 bit block. This is referred to as 16×10_block_original, for example. Next, a re-ordering operation312is performed from the stored 16×10_block_original, and the re-ordered block of bits is referred to as 16×10_block_reordered. The re-ordering operation312involves re-ordering bits stored in memory according to a mapping that permutes the bits stored in memory to produce a re-ordered block of bits such that when the re-ordered block of bits is distributed to a plurality of modified logical lanes equal in number to the plurality of logical lanes and the plurality of modified logical lanes are bit-multiplexed to at least one physical lane, the at least one physical lane obtains a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword. The “groups of bits” may be two or more bits, and in one example presented herein, the “groups of bits” is a pair (2) bits. There may be applications where higher order modulation is used, possibly using more than 2 bits at a time on a physical lane (such as QAM16 which encodes 4 bits at a time).

This re-ordering may be performed according to a mapping represented byFIGS.8,10and12, for example. In other words, the re-ordering operation312involves applying a mapping between one block (e.g., 16×10 block) ordering of bits and another block ordering of bits, according to the arrangement of a reordering or mapping.

At step314, the reordered block of bits is distributed to modified logical lanes, such as 16 logical lanes. Thus, the result step314is a plurality of modified logical lanes that are equal in number to the plurality of logical lanes provided as input to the bit ordering operation224, but the content of the plurality of modified logical lanes is different (insofar as the arrangement/ordering of bits). The PMA sublayer250operates on the content of the plurality of modified logical lanes it receives from step314to produce one or more physical lanes, and the PMA sublayer250need not be modified in any way to account for the modified bit ordering, if the modified bit ordering operation224is performed by the PCS transmit function. The PMA sublayer250operates as it normally would, according to the IEEE 802.3 specification, and the error resiliency benefits of the modified bit order are achieved in the one or more physical lanes when the modified bit ordering operation224is performed. If the modified bit ordering operation224is not performed/invoked by the PCS transmit function, then the PMA sublayer250operations of the plurality of logical lanes output by the bit interleave and distribution operation222.

When the PMA sublayer250is configured to distribute a plurality of (more than one) physical lanes, the re-ordering operation312involves re-ordering bits stored in the memory according to the mapping to produce the re-ordered block of bits such that when the re-ordered block of bits is distributed to each of the plurality of modified logical lanes and the plurality of modified logical lanes are bit-multiplexed to create a plurality of physical lanes, each physical lane of the plurality of physical lanes obtains a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.

Reference is now made toFIG.4for a description of the PCS receive function with modified bit re-ordering for the example of the 400GBASE-R PCS. Following the paradigm ofFIG.2, the receive function processing progresses from the bottom of the page towards the top of the page. In the PCS block for handling receive bits that have not been re-ordered according to the process ofFIG.3, the de-skew control is part of the alignment lock and lane deskew operation. According to the techniques presented herein, the alignment lock and lane deskew operation is split into three separate operations: lane deskew operation230, alignment marker lock operation234and de-skew control operation235.

The lane deskew operation230receives bits for at least one physical (PMA) lane that has been transmitted from a far end device. In the case of 400GBASE-R, there a 16 logical (PCS) lanes, but the number of physical (PMA) lanes is typically smaller, and can be as low as 2 (as depicted inFIG.9). If the bits have been re-ordered according to the techniques ofFIG.3at the far end device, then the output of the lane deskew operation230is a plurality of modified logical lanes from which the at least one physical lane has been de-multiplexed by the PMA sublayer. The plurality of modified logical lanes is equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to a mapping that permuted the original block of bits to produce a re-ordered block of bits distributed to the plurality of modified logical lanes such that when the plurality of modified logical lanes was bit-multiplexed to the at least one physical lane, the at least one physical lane contains a sequence of a groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.

The lane deskew operation230involves applying a different delay amount to the data for each physical lane (if there were multiple physical lanes) to account for different delays on the different physical lanes, to produce, for example, in the case of 16 modified logical lanes, deskewed data denoted lane0_deskewed to lane15_deskewed.

Next, as part of the modified bit-ordering operation232, at step410, bits (e.g., 10 bits) received for each modified logical lane are stored into a block in memory, e.g., a 16×10 bit block. The stored block of bits is referred to as 16×10_block_reordered, as an example.

At step420, the block of bits stored in memory are re-ordered (performing the inverse or reverse of operation312ofFIG.3). In the other words, at step420, an inverse of the re-ordered mapping is performed on the re-ordered block of bits stored in the memory to obtain an original block of bits. Said another way, the re-ordering step420is essentially the inverse of the mapping between the re-ordered block of bits and the original block ordering of bits, as depicted by a re-ordering table, such as that shown inFIG.8.

At step430, the original block of bits read from memory and are distributed to each of a plurality of logical lanes.

The alignment marker lock operation234involves detecting and locking to alignment markers inserted into the bitstream. Since the alignment markers were shuffled by the modified ordering (at the transmit side), the alignment marker lock operation234is performed after the inverse re-ordering is performed in order to recover the alignment markers. The output of the alignment marker lock operation234is provided to the lane re-order and de-interleave operation236, and then on to the other operations of the receive function204of the PCS block200, as shown inFIG.2. In addition, the de-skew control operation235involves providing control input to the lane deskew operation230to apply an appropriate delay to the receive data for the respective physical lanes until the alignment marker lock operation234succeeds. As one example, the de-skew control operation235may perform an exhaustive search of all “lane deskew” combinations until the alignment mark lock succeeds.

FIG.5shows a table500representing the PCS bit ordering of the existing clause 119 400GBASE-R PCS functional block or module of the IEEE 802.3 standard specification. This is representative of one of example of the aforementioned un-modified bit ordering. InFIG.5, each column is a logical (PCS) lane (16 total). Each row represents a group of logical bits that are delivered as a group to the PMA sublayer for bitwise multiplexing. The order of generation is from bottom (early) to top (late).

The bits are labeled by the codeword they belong to (A or B, for the example where there are two codewords) and the running bit index within that codeword. 80 consecutive bits are taken from each of the two codewords, creating a block of 160 bits. The bit order within each of these blocks alternates such that each lane has 10 bits from codeword A and then 10 bits from codeword B. For example, in lane 0, 10 bits (A0-A9) from codeword A are transmitted, followed by 10 bits (B80-B89) are transmitted. Similarly, in lane 1, bits B0-B9 from codeword B are transmitted, followed by bits A80-A89. Thus, lane 1 is the mirror of lane 0 but for codeword B. This pattern repeats for consecutive lanes as shown inFIG.5.

On transmission, the 16 logical lanes are bit-muxed to (or combined into) four physical lanes, at 100 Gb/s per lane or 400 Gb/s over 4 lanes, as shown. The physical lanes use PAM4 modulation with two bits per symbol. The resulting symbol sequences (with a particular choice of bit muxing) is shown in the table600ofFIG.6. Note that another bit muxing order can be applied that would result in a different physical lane symbol composition, but the effects shown below are independent of the bit muxing order.

The symbol sequences are presented inFIG.6by transmission order from bottom (early) to top (late). As shown inFIG.6, the bit-muxing operation results in pairs of bits (PAM4 symbols) from different codewords to be transmitted at each time index, and every group of 2 consecutive PAM4 symbols on each lane has bits with index difference of 40±1. Since the RS-FEC code used in clause 119 has 10 bits per FEC symbol, this means that, error bursts of 2 consecutive PAM4 symbols often affect bits from two different symbols on the same codeword (e.g., A0 and A40), and occasionally error bursts of 4 consecutive PAM4 symbols can affect four different FEC symbols on the same codeword (e.g., A9, A49, A80, and A120) in rows 18, 19, 20 and 21 inFIG.6. Thus, the performance of the code becomes sub-optimal with error bursts.

If the PCS content was bit-muxed to two physical lanes at 200 Gb/s per lane (not part of the Ethernet specification at the time of this writing, but a likely future extension), the result would be as shown by the table700inFIG.7. As shown inFIG.7, the bits in four consecutive PAM4 symbols would have index differences of 20, so error bursts of 4 consecutive PAM4 symbols would often affect four different symbols of the same codeword (e.g., A0, A20, A40, A60), and occasionally error bursts of 8 consecutive PAM4 symbols would affect eight different FEC symbols on the same codeword (e.g., A9, A29, A49, A69, A80, A100, A120, and A140) corresponding to rows 36-43. Thus, the performance of the code would be significantly degraded with error bursts. Moreover, it is understood that there is a non-negligible probability that the error burst will continue to subsequent time instances. This can consume a significant portion of the correction capability of the RS-FEC code, with a single error burst event, even when the RS-FEC code can correct up to 15 symbols per codeword.

Bit Order Modification of the Existing 400 Gb/s PCS

FIG.8shows a table800representing a mapping or modified PCS bit ordering (the aforementioned “re-ordering”) presented herein for the 400 Gb/s PCS (400GBASE-R) specified in clause 119 of IEEE Std 802.3. This order is replacement of the existing PCS bit order shown inFIG.5. The change involves re-ordering of the bits from the order shown inFIG.5(in every 160-bit block) to the ordering shown inFIG.8, which is applied in both the transmitter and then the inverse of such re-ordering in the receiver. The 400GBASE-R PCS has only 2-way codeword interleaving, and this has not been changed by this modified bit ordering scheme. Thus, the table800shown inFIG.8represents how bits are re-ordered according to a mapping that permutes the bits to produce a re-ordered block of bits that is distributed to a plurality of modified logical lanes (equal in number of the plurality of logical lanes).

If the modified bit order ofFIG.8is applied instead of the one shown inFIG.5and the PCS output is bit-muxed to two physical lanes at 200 Gb/s per lane (with a particular choice of bit muxing order), the result would be as shown by the table900inFIG.9. Note that the choice of bit muxing order is important in this case—different muxing order could create very different symbol composition and possibly worse results.

As shown inFIG.9, with the bit ordering modification depicted inFIG.8, the bit-muxing operation now results in pairs of bits (PAM4 symbols) from the same codeword, and every group of 5 consecutive PAM4 symbols on each lane has 10 consecutive bits. This effectively means that symbols are transmitted on each physical lane separately and consecutively. As a result, error bursts of up to 10 consecutive PAM4 symbols will affect at most one FEC symbol on each of the two codewords. This is the best symbol ordering possible with 2-way codeword interleaving.

The re-ordering of the bits is such that, when the plurality of modified logical lanes are bit-multiplexed to at least one physical lane, the at least one physical lane obtains a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.

In the example ofFIG.9there are 2 physical lanes and each group of bits in the sequence of groups of bits is a group of two bits (i.e., a pair of bits). Thus, each physical lane is allowed a sequence of pairs of bits for a symbol from one codeword followed by a sequence of pairs of bits for a symbol for another codeword. Consider time indexes 0-4, as an example. Physical lane 0 is allowed (or assigned) a pair of bits A0-A1 at time index 0, a pair of bits A2-A3 at time index 1, a pair of bits A4-A5 at time index 2, a pair of bits A6-A7 at time index 3 and a pair of bits A8-A9 at time index 4. The forms a sequence of pairs of bits: A0-A1, A2-A3, A4-A5, A6-A7 and A8-A9, all assigned to physical lane 0 and all of these bits are for the same symbol for the same FEC codeword. This sequence of pairs of bits could be sent in any combination in any order, as long as they are all for the same symbol for a given codeword. After that sequence of pairs of bits (spanning A0-A9 for a symbol for one codeword), a sequence of pairs of bits are allocated to lane 0 from another FEC codeword, e.g., codeword B. That is, from time index 5 to time index 9, the sequence of pairs of bits are sent: B10-B11 at time index 5, B12-B13 at time index 6, B14-B15 at time index 7, B16-B17 at time index 8 and B18-B19 at time index 9. Again, this sequence of pairs of bits are for the same symbol for the same codeword, but for a different codeword that the prior sequence (spanning time indices 0-4). This pattern repeats in lane 0.

A similar bit allocation/assignment is made by the re-ordering scheme for lane 1. At time indices 0-4, a sequence of pairs of bits (bits B0-B9) for a symbol from codeword B are assigned, and then a sequence of pairs of bits (bits A10-A19) for a symbol from codeword A are assigned.

Thus, in the example the bit re-ordering techniques depicted byFIGS.8and9, the number of the plurality of FEC codewords is two FEC codewords, and the sequence of groups of bits alternates, over time for symbols between the two FEC codewords. Moreover,FIGS.8and9depict an example in which the number of the plurality of modified logical lanes is 16 and the number of physical lanes is 2.

Modification of the Existing 200 Gb/s PCS

A 200GBASE-R PCS (similar to 400GBASE-R but with 8 logical lanes) has the same issues when its output is bit-muxed. A similar bit order modification (depicted by table1000inFIG.10) can be applied to the PCS for transmission on one physical lane (at 200 Gb/s).

The resulting symbol order mapped to a single physical lane is shown by table1100inFIG.11. As in the modified 400GBASE-R, error bursts of up to 10 consecutive PAM4 symbols will affect at most one FEC symbol on each of the two codewords. This is the best symbol ordering possible with 2-way codeword interleaving.

FIGS.10and11depict an example of the bit re-ordering techniques in which the number of the plurality of modified logical lanes is 8 and the number of physical lanes is one.

Modified Bit Order for the Future 800 Gb/s PCS

The PCS bit order modification techniques described above can be applied to future more sophisticated and higher bandwidth schemes. For example, table1200inFIGS.12A and12Bshows a modified PCS bit ordering for the 800 Gb/s PCS (800GBASE-R) that is being specified in IEEE P802.3df. Each column is a logical lane (32 total acrossFIGS.12A and12B). Each row represents a group of logical bits that are delivered as a group to the PMA for bitwise multiplexing. The order of generation is from bottom (early) to top (late).

The bits are labeled by the FEC codeword they belong to (A, B, C, or D) and the running bit index within that codeword. 20 consecutive bits are taken from each of the four codewords, creating a block of 80 bits. The bit order within each of these blocks is the same. Two such groups are generated in parallel as shown, one on logical lanes 0 through 15 (left), and the other on logical lanes 16 through 31 (right).

On transmission, the 32 logical lanes are bit-muxed to four physical lanes, at 200 Gb/s per lane. The physical lanes use PAM4 modulation with two bits per symbol. The resulting symbol sequences (with a particular choice of bit muxing order) is shown by table1300inFIG.13. Note that the choice of bit muxing is important in this case—different muxing order could create very different symbol composition and possibly worse results.

The symbol sequences appear inFIG.13by transmission order from bottom (early) to top (late). As can be seen, the bit-muxing operation results in pairs of bits (PAM4 symbols) from the same codeword, and every group of 5 consecutive PAM4 symbols on each lane has 10 consecutive bits. Moreover, each physical lane obtains a sequence of pairs of bits for a symbol from one FEC codeword followed by a sequence of pairs of bits from another FEC codeword. For example, for physical lane 0, the sequence of pairs of bits assigned is: A0-A1 at time index 0, A2-A3 at time index 1, A4-A5 at time index 2, A6-A7 at time index 3, and A8-A9 at time index 4. Bits A0-A9 are from the same symbol of FEC codeword A. This is followed by on physical lane 0, a sequence of pairs of bits from bits B0-B9, which are from the same symbol of FEC codeword B. This is followed by, on physical lane 0 a sequence of pairs of bits from bits C0-C9, which are from the same symbol of FEC codeword C. This in turn is followed by, on physical lane 0, a sequence of pairs of bits from bits D0-D9, which are from the same symbol of FEC codeword D. A similar pattern occurs for physical lane 1, starting with a sequence of pairs of bits A10-A11, A12-A13, A14-A15, A16-A17, and A18-A19, which are from the same symbol for FEC codeword A; followed by a sequence of pairs of bits B10-B11, B12-B13, B14-B15, B18-B19, which are from the same symbol for FEC codeword B, and so on. A similar pattern also occurs for physical lane 2 and physical lane 3. Again, the pairs of bits of a sequence can be in any order and the bits of a pair can be in any order. Thus,FIGS.12A and12Bdepicts an example of the re-ordering techniques when the number of the plurality of FEC codewords is four FEC codewords, and the sequence of groups of bits alternates, over time, for symbols between the four FEC codewords.

Since the RS-FEC code using in clause 119 has 10 bits per FEC symbol, this effectively means that symbols are transmitted on each physical lane separately and consecutively. As a result, error bursts of up to 20 consecutive PAM4 symbols will affect at most one FEC symbol on each of the four codewords.

FIG.14shows a table1400depicting the resulting symbol order when bit-muxing to eight physical lanes (100 Gb/s each) instead of to four physical lanes. As can be seen, the PAM4 symbols on each lane are still composed of bits from the same FEC codeword and symbol, but FEC symbols are spread across two physical lanes; for example, bits A0 through A9 are spread across lanes 0 and 2. Moreover, the pattern of a sequence of pairs of bits from one codeword followed by a sequence of pairs of bits for another codeword is followed for each physical lane. For example, for physical lane 0, the sequence of pairs of bits is: A0-A1 at time index 0, A4-A5 at time index 1, and A8-A9 at time index 2. All of these bits (A0, A1, A4, A5, A8 and A9) are from the same symbol of FEC codeword A. This is followed by the sequence of pairs of bits: B2-B3 at time index 3, B6-B7 at time index 4, and all of these bits are from the same symbol of FEC codeword B. This is followed by the sequence of pairs of bits: C0-CI at time index 7, C4-05 at time index 6, and C8-C9 at time index 7, and all of these bits are from the same symbol for FEC codeword C. This is followed by the sequence of pairs of bits: D2-D3 at time index 8 and D6-D7 at time index 9, and all of these bits are from the same symbol for codeword D. The pattern then starts again with a sequence of pairs of bits for a given symbol of FEC codeword A, etc. The same sort of pattern is used for physical lanes 1-7. As a result, error bursts of length up to 10 (instead of 20 above) consecutive PAM4 symbols will affect at most one FEC symbol on each of the four codewords. This is better than the existing 400GBASE-R PCS even at 100 Gb/s per lane.

Thus, in the example ofFIGS.12-14, the number of the plurality of modified logical lanes is 32 and the number of the plurality of physical lanes is 4 (inFIG.13) or 8 (inFIG.14).

Switching between the new bit order and the existing bit order is possible with very small logic implementation. As a result, it is possible to implement both bit the modified bit ordering and un-modified bit ordering, and implement backward comparability with a simple detection mechanism. A device starts transmitting with the new bit order, and on its receiver, it attempts to decode the FEC with that order. If many errors are found, the device can try decoding using the “old” bit order. If it succeeds, it means that the link partner is not using the modified order, and the device switches its transmit bit order to the old order as well. A process for determining and adjusting a configuration of one device based on the capability learned for another device is described below in connection withFIG.17.

The effect of the physical lane symbol composition on FEC performance, in terms of coding gain (or the desired SNR to achieve a given codeword error ratio), can be analyzed rigorously (as has been done in past work, e.g. in IEEE contributions anslow_3ck_adhoc_01_041019, anslow_3ck_adhoc_01_072518, and anslow_01_0815_logic), but such analysis is beyond the scope of this document. Nonetheless, it is apparent from inspection ofFIGS.8-14, that the modified PCS bit ordering (the bit re-ordering) always makes error bursts affect fewer FEC symbols than with the PCS bit order presented the original clause 119 of the IEEE 802.3 standard specification, with a significant difference for long bursts. Thus, it is apparent from such inspection that the modified order improves the coding gain. The effect of the modified bit order is similar to the result with no error bursts at all. In that case, the coding gain would be improved by 0.5 to 1 dB.

Reference is now made toFIG.15, which illustrates a flow chart depicting a method1500performed at one device when transmitting data to another device, according to the techniques presented herein. The method1500involves, for each FEC codeword of a plurality of FEC codewords of data to be transmitted over a channel, at step1510, obtaining a symbol from each logical lane of a plurality of logical lanes to which the plurality of FEC codewords have been multiplexed. At step1520, the method1500includes storing bits for the symbol from each logical lane of the plurality of logical lanes into a memory. At step1530, the method1500includes re-ordering bits stored in the memory according to a mapping that permutes the bits stored in memory to produce a re-ordered block of bits such that when the re-ordered block of bits is distributed to a plurality of modified logical lanes equal in number to the plurality of logical lanes and the plurality of modified logical lanes are bit-multiplexed to at least one physical lane, the at least one physical lane obtains a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.

FIG.16illustrates a flow chart depicting a method1600performed at one device when receiving data transmitted from another device, according to the techniques presented herein. The method1600includes, at step1610, obtaining a stream of bits received for at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, which plurality of modified logical lanes is equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to a mapping that permuted the original block of bits to produce a re-ordered block of bits distributed to the plurality of modified logical lanes such that when the plurality of modified logical lanes was bit-multiplexed to the at least one physical lane, the at least one physical lane contains a sequence of a groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword. At step1620, the method1600includes storing the re-ordered block of bits obtained from the plurality of modified logical lanes to a memory. At step1630, the method1600includes performing an inverse of the mapping on the re-ordered block of bits stored in the memory to obtain the original block of bits. At step1640, the method1600includes distributing the original block of bits to the plurality of logical lanes.

In summary, the techniques presented herein maximize the performance of the RS-FEC code, for 200 Gb/s per lane signaling. As a result, the probability of having uncorrectable codewords (data loss) on a given link is reduced by several orders of magnitude. Alternatively, the link performance can be met with longer channels and/or lower Serializer-Deserializer (SerDes) power.

Reference is now made toFIG.17.FIG.17is a flow chart depicting a method1700performed at a device, e.g., a first device, when conducting network communications with a second device. Reference is also made toFIG.1for purposes of the description of method1700. At step1705, the method1700involves configuring a transmit function, e.g., a PCS transmit function, to use a modified bit ordering that maps bits from a plurality of logical lanes to a plurality of modified logical lanes that are bit-multiplexed to at least one physical lane for transmission to a second device. At step1710, the method1700involves configuring a receive function (e.g., a PCS receive function) to use a modified bit ordering for processing a stream of bits received from the second device on at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, the plurality of modified logical lanes being equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to the modified bit ordering.

Next, at step1715, the receive function of the first device attempts to process (lock to) an incoming bit stream received from the second device (for some period of time T). At step1720, if the attempt to process (lock to) the incoming bit stream with the receive function using the modified bit ordering is successful, then the method1700ends. The first device can thereafter continue to use the modified bit ordering with the receive function for processing transmissions received from the second device, and can continue to use the modified bit ordering with the transmit function for making transmissions to the second device. In other words, through steps1705,1710,1715and1720, the first device has learned that the second device is also capable of using the modified (PCS) bit ordering (the aforementioned re-ordering) since it was able to successfully process a received transmission from the second device using the modified (PCS) bit ordering.

On the other hand, if the first device is not successful in processing (locking to) a receive transmission from the second device using the modified bit ordering, then the method1700proceeds to step1725where the first device configures its (PCS) receive function to use an un-modified bit ordering. Next, at step1730, the first device tries to process (lock to) a received incoming bit stream from the second device (for some time T) using the un-modified bit ordering.

At step1735, it is determined whether the first device is successful in processing (locking to) a received incoming bit pattern using the un-modified bit ordering. If successful, then at step1740, the first device configures the (PCS) transmit function to use the un-modified bit ordering for transmissions to the second device. If not successful at step1735, then the process reverts to step1710and steps1715and1720are repeated.

Referring now toFIG.18, a hardware block diagram is shown of a device1800that may perform functions associated with operations discussed herein in connection with the techniques presented herein. In various embodiments, the device1800may be a networking device, a computing device or any device that may be configured to perform networking communications using the techniques presented herein.

In at least one embodiment, the device1800may be any apparatus that may include one or more processor(s)1802, one or more memory element(s)1804, storage1806, a bus1808, one or more network processor unit(s)1810interconnected with one or more network input/output (I/O) interface(s)1812, one or more I/O interface(s)1814, and control logic1820. In various embodiments, instructions associated with logic for device1800can overlap in any manner and are not limited to the specific allocation of instructions and/or operations described herein.

In at least one embodiment, processor(s)1802is/are at least one hardware processor configured to execute various tasks, operations and/or functions for device1800as described herein according to software and/or instructions configured for device1800. Processor(s)1802(e.g., a hardware processor) can execute any type of instructions associated with data to achieve the operations detailed herein. In one example, processor(s)1802can transform an element or an article (e.g., data, information) from one state or thing to another state or thing. Any of potential processing elements, microprocessors, digital signal processor, baseband signal processor, modem, PHY, controllers, systems, managers, logic, and/or machines described herein can be construed as being encompassed within the broad term ‘processor’.

In at least one embodiment, memory element(s)1804and/or storage1806is/are configured to store data, information, software, and/or instructions associated with device1800, and/or logic configured for memory element(s)1804and/or storage1806. For example, any logic described herein (e.g., control logic1820) can, in various embodiments, be stored for device1800using any combination of memory element(s)1804and/or storage1806. Note that in some embodiments, storage1806can be consolidated with memory element(s)1804(or vice versa), or can overlap/exist in any other suitable manner.

In one form, the operations of the transmit function described herein may be embodied in an apparatus that includes a memory; and one or more integrated circuits configured with digital logic, or a processor device configured with instructions, to perform operations including: for each forward error corrected (FEC) codeword of a plurality of FEC codewords of data to be transmitted over a channel, obtaining a symbol from each logical lane of a plurality of logical lanes to which the plurality of FEC codewords have been multiplexed; storing in the memory bits for the symbol from each logical lane of the plurality of logical lanes; and re-ordering bits stored in the memory according to a mapping that permutes the bits stored in memory to produce a re-ordered block of bits such that when the re-ordered block of bits is distributed to a plurality of modified logical lanes equal in number to the plurality of logical lanes and the plurality of modified logical lanes are bit-multiplexed to at least one physical lane, the at least one physical lane obtains a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.

Similarly, the operations of the receive function described herein may be embodied in an apparatus that includes a memory; and one or more integrated circuits configured with digital logic, or a processor device configured with instructions, to perform operations including: obtaining a stream of bits received for at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, which plurality of modified logical lanes is equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to a mapping that permuted the original block of bits to produce a re-ordered block of bits distributed to the plurality of modified logical lanes such that when the plurality of modified logical lanes was bit-multiplexed to the at least one physical lane, the at least one physical lane contains a sequence of a groups of bits for a symbol from one forward error corrected (FEC) codeword followed by a sequence of groups of bits for a symbol from another FEC codeword; storing the re-ordered block of bits obtained from the plurality of modified logical lanes to a memory; performing an inverse of the mapping on the re-ordered block of bits stored in the memory to obtain the original block of bits; and distributing the original block of bits to the plurality of logical lanes.

In at least one embodiment, bus1808can be configured as an interface that enables one or more elements of device1800to communicate in order to exchange information and/or data. Bus1808can be implemented with any architecture designed for passing control, data and/or information between processors, memory elements/storage, peripheral devices, and/or any other hardware and/or software components that may be configured for device1800. In at least one embodiment, bus1808may be implemented as a fast kernel-hosted interconnect, potentially using shared memory between processes (e.g., logic), which can enable efficient communication paths between the processes.

In various embodiments, network processor unit(s)1810may enable communication between device1800and other systems, entities, etc., via network I/O interface(s)1812(wired and/or wireless, e.g., ports or interfaces) to facilitate operations discussed for various embodiments described herein. In various embodiments, network processor unit(s)1810can be configured to perform the network communication techniques presented herein as a combination of hardware and/or software, such as one or more Ethernet driver(s) and/or controller(s) or interface cards, Fibre Channel (e.g., optical) driver(s) and/or controller(s), wireless receivers/transmitters/transceivers, baseband processor(s)/modem(s), and/or other similar network interface driver(s) and/or controller(s) now known or hereafter developed to enable communications between device1800and other systems, entities, etc. to facilitate operations for various embodiments described herein. In various embodiments, network I/O interface(s)1812can be configured as one or more Ethernet port(s), Fibre Channel ports, any other I/O port(s), and/or antenna(s)/antenna array(s) now known or hereafter developed. Thus, the network processor unit(s)1810and/or network I/O interface(s)1812may include suitable interfaces for receiving, transmitting, and/or otherwise communicating data and/or information in a network environment.

In various embodiments, control logic1820can include instructions that, when executed, cause processor(s)1802to perform operations, which can include, but not be limited to, providing overall control operations of computing device; interacting with other entities, systems, etc. described herein; maintaining and/or interacting with stored data, information, parameters, etc. (e.g., memory element(s), storage, data structures, databases, tables, etc.); combinations thereof; and/or the like to facilitate various operations for embodiments described herein.

Variations and Implementations

In some aspects, the techniques described herein relate to a method including: for each forward error corrected (FEC) codeword of a plurality of FEC codewords of data to be transmitted over a channel, obtaining a symbol from each logical lane of a plurality of logical lanes to which the plurality of FEC codewords have been multiplexed; storing bits for the symbol from each logical lane of the plurality of logical lanes into a memory; and re-ordering bits stored in the memory according to a mapping that permutes the bits stored in memory to produce a re-ordered block of bits such that when the re-ordered block of bits is distributed to a plurality of modified logical lanes equal in number to the plurality of logical lanes and the plurality of modified logical lanes are bit-multiplexed to at least one physical lane, the at least one physical lane obtains a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.

In some aspects, the re-ordering includes re-ordering bits stored in the memory according to the mapping to produce the re-ordered block of bits such that when the re-ordered block of bits is distributed to each of the plurality of modified logical lanes and the plurality of modified logical lanes are bit-multiplexed to create a plurality of physical lanes, each physical lane of the plurality of physical lanes obtains a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.

In some aspects, the sequence of groups of bits are for the same symbol for an FEC codeword.

In some aspects, a number of the plurality of FEC codewords is two FEC codewords, and the sequence of groups of bits alternates, over time, for symbols between the two FEC codewords. In some aspects, the number of the plurality of modified logical lanes is 16 and the number of physical lanes is 2, or the number of the plurality of modified logical lanes is 8 and the number of physical lanes is one.

In some aspects, a number of the plurality of FEC codewords is four FEC codewords, and the sequence of groups of bits alternates, over time, for symbols between the four FEC codewords. In some aspects, the number of the plurality of modified logical lanes is 32 and the number of the plurality of physical lanes is 4 or 8.

In some aspects, the bits in each sequence of groups of bits are in any order for a symbol for an FEC codeword.

In some aspects, each group in the sequence of groups is two or more bits.

In some aspects, the techniques described herein relate to a method including: obtaining a stream of bits received for at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, which plurality of modified logical lanes is equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to a mapping that permuted the original block of bits to produce a re-ordered block of bits distributed to the plurality of modified logical lanes such that when the plurality of modified logical lanes was bit-multiplexed to the at least one physical lane, the at least one physical lane contains a sequence of a groups of bits for a symbol from one forward error corrected (FEC) codeword followed by a sequence of groups of bits for a symbol from another FEC codeword; storing the re-ordered block of bits obtained from the plurality of modified logical lanes to a memory; performing an inverse of the mapping on the re-ordered block of bits stored in the memory to obtain the original block of bits; and distributing the original block of bits to the plurality of logical lanes.

In some aspects, the obtaining includes obtaining streams of bits received for each of a plurality of physical lanes from which the plurality of modified logical lanes have been de-multiplexed.

In some aspects, the method further includes: prior to storing, deskewing the streams of bits of the plurality of physical lanes. In some aspects, the method further includes: determining an alignment marker for bits of the plurality of logical lanes; and adjusting the deskewing until alignment marker lock is successful.

In some aspects, each group in the sequence of groups is two or more bits.

In some aspects, the techniques described herein relate to a method performed by a first device that is in communication with a second device, including: configuring a transmit function to use a modified bit ordering that maps bits from a plurality of logical lanes to a plurality of modified logical lanes that are bit-multiplexed to at least one physical lane for transmission to a second device; configuring a receive function to use a modified bit ordering for processing a stream of bits received from the second device on at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, the plurality of modified logical lanes being equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to the modified bit ordering; receiving an incoming bit stream from the second device; attempting to process the incoming bit stream from the second device with the receive function using the modified bit ordering; and when processing the incoming bit stream using the modified bit ordering is not successful, configuring the receive function of the first device to use an un-modified bit ordering for processing the incoming bit stream from the second device.

In some aspects, the techniques described herein relate to a method, further including: attempting to process the incoming bit stream with the receive function using the un-modified bit ordering; and when processing the incoming bit stream using the un-modified bit ordering is successful, configuring the transmit function to use the un-modified bit ordering for transmissions to the second device.

In some aspects, the techniques described herein relate to a method, when processing the incoming bit stream using the modified bit ordering is successful, continuing to use the modified bit ordering with the receive function for processing transmissions received from the second device.

In some aspects, an apparatus is provided including: a memory; and one or more integrated circuits configured with digital logic, or a processor device configured with instructions, to perform operations including: for each forward error corrected (FEC) codeword of a plurality of FEC codewords of data to be transmitted over a channel, obtaining a symbol from each logical lane of a plurality of logical lanes to which the plurality of FEC codewords have been multiplexed; storing in the memory bits for the symbol from each logical lane of the plurality of logical lanes; and re-ordering bits stored in the memory according to a mapping that permutes the bits stored in memory to produce a re-ordered block of bits such that when the re-ordered block of bits is distributed to a plurality of modified logical lanes equal in number to the plurality of logical lanes and the plurality of modified logical lanes are bit-multiplexed to at least one physical lane, the at least one physical lane obtains a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.

In some aspects, the techniques described herein relate to an apparatus, wherein re-ordering includes re-ordering bits stored in the memory according to the mapping to produce the re-ordered block of bits such that when the re-ordered block of bits is distributed to each of the plurality of modified logical lanes and the plurality of modified logical lanes are bit-multiplexed to create a plurality of physical lanes, each physical lane of the plurality of physical lanes obtains a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.

In some aspects, an apparatus is provided including: a memory; and one or more integrated circuits configured with digital logic, or a processor device configured with instructions, to perform operations including: obtaining a stream of bits received for at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, which plurality of modified logical lanes is equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to a mapping that permuted the original block of bits to produce a re-ordered block of bits distributed to the plurality of modified logical lanes such that when the plurality of modified logical lanes was bit-multiplexed to the at least one physical lane, the at least one physical lane contains a sequence of a groups of bits for a symbol from one forward error corrected (FEC) codeword followed by a sequence of groups of bits for a symbol from another FEC codeword; storing the re-ordered block of bits obtained from the plurality of modified logical lanes to a memory; performing an inverse of the mapping on the re-ordered block of bits stored in the memory to obtain the original block of bits; and distributing the original block of bits to the plurality of logical lanes.