Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has chip and a redistribution layer. The redistribution layer is disposed on the chip. The redistribution layer includes joining portions having first pads and second pads surrounding the chip. The first pads are arranged around a location of the chip and the second pads are arranged over the location of the chip. The second pads located closer to the chip are narrower than the first pads located further away from the chip.

BACKGROUND

Semiconductor devices and integrated circuits are typically manufactured on a single semiconductor wafer. The dies of the wafer may be processed and packaged with other semiconductor devices or dies at the wafer level, and redistribution layers are included for routing and interconnecting the dies and/or semiconductor devices for the wafer level packaging.

DETAILED DESCRIPTION

In addition, terms, such as “first,” “second,” “third,” “fourth,” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description.

FIG. 1toFIG. 8are schematic cross sectional views of various stages in a manufacturing method of a semiconductor package according to some exemplary embodiments. In exemplary embodiments, the semiconductor manufacturing method is part of a wafer level packaging process. In some embodiments, two dies are shown to represent plural dies of the wafer, and one or more packages10are shown to represent plural semiconductor packages obtained following the semiconductor manufacturing method. Referring toFIG. 1, in some embodiments, a carrier102is provided, and the carrier102may be a glass carrier or any suitable carrier for the manufacturing method of the semiconductor package. In some embodiments, the carrier102is provided with a debond layer104coated thereon, and the material of the debond layer may be any material suitable for debonding the carrier102from the above layers or die(s) disposed thereon. Referring toFIG. 2, in some embodiments, through interlayer vias (TIVs)110are formed on the carrier102. In some embodiments, the TIVs110are through integrated fan-out (InFO) vias. In some embodiments, the TIVs110may be formed by forming a mask pattern (not shown) on the debond layer104with openings exposing the debond layer104on the carrier102, forming a metallic material filling the openings to form the TIVs by electroplating or deposition and then removing the mask pattern. In some embodiments, as shown inFIG. 2, the dotted line represents the cutting line of the package structure100in the subsequent cutting process and the TIVs110may be arranged close to and/or along the cutting line but not on the cutting line. In alternative embodiments, the TIVs are optional and the formation of the TIVs may be omitted.

Referring toFIG. 3, dies120are provided and placed over the carrier102. In some embodiments, a die attach film106is provided between the debond layer104and the dies120for better adhering the dies120to the debond layer104of the carrier102. In exemplary embodiments, as shown inFIG. 3, the dies120may include different types of dies or the same types of dies. In some embodiments, the die120may include one or more types of chips selected from application-specific integrated circuit (ASIC) chips, analog chips, sensor chips, wireless and radio frequency chips, voltage regulator chips or memory chips. In certain embodiments, dies and chips may be used interchangeably. In certain embodiments, the die120is provided with contacts or pads122on the substrate121of the die120, a passivation layer124formed over the substrate121with openings exposing the pads122and conductive posts126located within the openings and connected to the pads122. In some embodiments, the pads122are aluminum pads, copper pads or other suitable metallic pads. In some embodiments, the material of the passivation layer124includes silicon nitride, silicon oxynitride, a polymer material or a dielectric material. In some embodiments, the conductive posts124are copper posts or copper alloy posts. In one embodiment, the die120is provided and bonded to the carrier102with its active surface120afacing upward (as seen inFIG. 3). In certain embodiments, the TIVs110are arranged along the periphery of the die(s)120. However, depending on product design, some of the TIVs110may be arranged at locations other than the periphery of the die120. In certain embodiments, in addition to the dies120stacked over the carrier102side-by-side as shown inFIG. 3, the package structure100may further include other dies stacked at different levels, and the number of the dies arranged side-by-side or stacked over another die(s) may be adjusted or modified based on the product design but are not limited by the exemplary embodiments.

Referring toFIG. 4, in some embodiments, the dies120and the TIVs110located over the carrier102are molded and encapsulated in a molding compound160. In one embodiment, the molding compound160fills the space between the dies120and the TIVs110and covers the dies120and the TIVs110over the debond layer104. In one embodiment, the material of the molding compound160includes epoxy resins, phenolic resins or silicon-containing resins. In some embodiments, the molding compound160is then planarized to expose tops110aof the TIVs110and the active surfaces120aof the dies120. In some embodiment, the over-molded molding compound160and the TIVs110are polished until the conductive posts126of the dies120are exposed. In one embodiment, after the planarization, the tops110aof the TIVs110, the top surface160aof the molding compound160, and the active surface120aof the dies120become substantially levelled and flush with one another. In some embodiments, the molding compound160and/or the TIVs110are planarized through a grinding process or a chemical mechanical polishing (CMP) process.

Referring toFIG. 5, in some embodiments, a redistribution layer170is formed on the molding compound160, over the TIVs110and on the dies120. In some embodiment, the redistribution layer170is electrically connected to the TIVs110and the dies120. The formation of the redistribution layer170includes sequentially forming more than one dielectric material layers and more than one metallization layers in alternation.

Referring toFIG. 5, in certain embodiments, the redistribution layer170is formed by sequentially forming a lower dielectric material layer171, a first metallization layer172, a middle dielectric material layer173, a second metallization layer174and a top dielectric material layer175on the molding compound160, over the TIVs110and on the dies120. In some embodiments, the formation of the redistribution layer170includes forming the lower dielectric material layer171with openings exposing the conductive posts126of the dies120, forming a metal layer (not shown) over the lower dielectric material layer171filling the openings, and patterning the metal layer to form the first metallization layer172. In some embodiments, the formation of the redistribution layer170further includes forming the middle dielectric material layer173with openings exposing portions of the first metallization layer172, forming another metal layer (not shown) over the middle dielectric material layer173filling the openings, and then patterning the metal layer to form the second metallization layer174. In some embodiments, the formation of the redistribution layer170further includes forming the top dielectric material layer175with openings S1, S2and S3exposing portions of the second metallization layer174. In some embodiments, the first metallization layer172is electrically connected with the dies120through the conductive posts126and is electrically connected with the TIVs110. In some embodiments, the second metallization layer174is electrically connected with the first metallization layer172.

In some embodiments, the materials of the dielectric material layers171,173,175may be the same or different. In some embodiments, the materials of the dielectric material layers171,173,175include one or more polymer dielectric materials such as polyimide, benzocyclobutene (BCB), polybenzooxazole (PBO), or any other suitable polymer-based dielectric materials. In some embodiments, the materials of the metallization layers172,174may be the same or different, and the materials of the metallization layers172,174may be selected from copper, nickel, aluminum, tungsten or combinations thereof.

FIG. 5′ is a schematic enlarged partial cross sectional view showing a portion of the redistribution layer170ofFIG. 5. In some embodiments, the second metallization layer174has joining portions174A, including contact pads such as ball pads, and routing portions174B, including trace lines such as routing traces or fan-out traces. In certain embodiments, the joining portions174A of the second metallization layer174are exposed by the top dielectric material layer175, while the routing portions174B are covered by the top dielectric material layer175. In some embodiments, the joining portions174A includes first pads1741, second pads1742and third pads1743respectively exposed by the openings S1, S2and S3. In some embodiments, a seed layer (not shown) may be formed on top surfaces of the pads1741,1742,1743for better adhesion between the pads and the top dielectric material layer175. In some embodiments, the first, second and third pads1741,1742,1743are of different shapes and sizes, while the first, second and third openings S1, S2and S3are of the same shape and of the same size. In some embodiments, the first, second and third openings S1, S2and S3are round openings with the same diameter D.

Referring toFIG. 6, under-ball metallurgy (UBM) patterns180are formed on the joining portions174A. In some embodiments, the UBM patterns180are disposed on the exposed top surfaces of the first, second and third pads1741,1742,1743, for electrically connecting with the subsequently formed conductive elements. As shown inFIG. 6, for example, the UBM patterns180are formed covering the openings S1, S2, S3and the first, second and third pads1741,1742,1743exposed by the openings S1, S2, S3and portions of the top dielectric material layer175. In some embodiments, the UBM patterns180are formed conformal to the profiles of the openings S1, S2, S3and the pads1741,1742,1743. In some embodiments, the sizes of the UBM patterns180correspond to the sizes of the openings S1, S2, S3. In one embodiment, the openings S1, S2, S3has substantially the same size, and the respectively formed UBM patterns180may be of one size. In some embodiments, the materials of the UBM patterns180may include copper, nickel, titanium, tungsten, alloys and/or combinations thereof. In some embodiments, the UBM patterns180may be formed by sputtering, electroplating or deposition, for example. In alternative embodiments, the formation of the UBM patterns may be optional and omitted for the package structure100. In some embodiments, no UBM patterns are formed before bonding the conductive elements to the pads of the joining portions, but a seed layer may be formed on the surfaces of the pads for enhancing adhesion between the pads and the overlying dielectric material layer and between the pads and the subsequently disposed conductive elements.

Referring toFIG. 7, conductive elements190are disposed on the UBM patterns180. In some embodiments, the conductive elements190may be disposed on and fixed to the UBM patterns180by performing a ball placement process and then through a reflow process. In some embodiments, the conductive elements190are, for example, solder balls or ball grid array (BGA) balls. In some embodiments, the conductive elements190are connected to the UBM patterns180through a solder flux. As shown in theFIG. 7, some of the conductive elements190are electrically connected to the dies120through the joining portions174A of the second metallization layer174and the first metallization layer172, and some of the conductive elements190are electrically connected to the TIVs110through the joining portions174A of the second metallization layer174and the first metallization layer172.

Referring toFIGS. 7-8, in some embodiments, the package structure is flipped (turned upside down) and the carrier102is removed from the molding compound160and the dies110. In some embodiments, a dicing process is later performed to cut the whole package structure100(at least cutting though the redistribution layer170and the molding compound160) along the cutting line (the dotted line) into individual and separated semiconductor packages10. In one embodiment, the dicing process is a wafer dicing process including mechanical sawing or laser cutting.

In alternative embodiments, the semiconductor package10may further include additional dies or sub-package units disposed over the die110and another redistribution layer(s) may be formed to electrically connect the additional dies or sub-package units. The structures and/or the processes of the present disclosure are not limited by the exemplary embodiments.

FIG. 9Ais a schematic top view illustrating the exemplary layout of the joining portions174A of the redistribution layer170in the package structure according to some exemplary embodiments of the present disclosure. InFIG. 9A, the routing portions174B are not shown for illustration purposes.FIGS. 9B-9Dare schematic cross sectional views illustrating the first, second and third pads of the joining portions inFIG. 9Arespectively along the cross section lines A-A′, B-B′ and C-C′. InFIG. 9A, the dotted line represents the location of the die. In some embodiments, as seen inFIG. 9A, the first, second and third pads1741,1742,1743are arranged in ring shapes surrounding the die around the location of the die. In certain embodiments, the first pads1741are round pads, and the first pads1741of the first size d1(i.e. the diameter of the round pad) are arranged with a fixed spacing P1in a shape of a first rectangular ring (referred to as the first ring R1). In certain embodiments, the second pads1742are elliptical pads, and the second pads1742of the first size d2(i.e. the length at the semi-minor axis) are arranged with a fixed spacing P2in a shape of a second rectangular ring (referred to as the second ring R2). In certain embodiments, the third pads1743are elliptical pads and the third pads1743of the first size d3(i.e. the length at the semi-minor axis) are arranged with a fixed spacing P3in the shape of a third rectangular ring (referred to as the third ring R3). Compared with the round pads, the elliptical pads are narrower at the semi-minor axis, and the length at the semi-minor axis is referred as the width of the elliptical pads. In some embodiments, the first pads1741are arranged most far away from the die, while the third pads1743are arranged closest to the die. In some embodiments, the third pads1743are arranged above and distributed over the location of the underlying die. The pad arranged closer or farer to the chip or die (or the periphery of the chip or die) is decided by the shortest distance of the pad to the periphery of the chip or die. In addition, the pad located over or above the chip location is considered located closer to the chip or die when compared with the pad located around or surrounding the chip location. In some embodiments, the second pads1742are arranged between the first and third pads1741,1743. In some embodiments, the first size d1is larger than the second size d2and the second size d2is larger than the third size d3. In some embodiments, the size d1of the round pads is substantially the same as the length L at the semi-major axis of the elliptical pads, but is different from the length d2, d3at the semi-minor axis of the elliptical pads. In some embodiments, the shrinking ratios may range from 0.99 to 0.50. In some embodiments, the shrinking ratios may range from 0.9 to 0.8. Taking the shrinking ratio being 0.9 as an example, d2is about 0.9*d1, and d3is about 0.9*d2or 0.81*d1. That is, at least one dimension of these pads (e.g. the size d1of the round pads or the length L at the semi-major axis of the elliptical pads) remains to be the same (unchanged) and the pads arranged closer to the die are smaller in sizes at the semi-minor axis (for the elliptical pads). In certain embodiments, all these pads have one dimension (e.g. length) set to be the same (i.e. the diameter d1of the round pads being equivalent to the length L at the semi-major axis of the elliptical pads) along the direction approaching a periphery of the die (e.g. radial inward direction shown as the arrow), while the pads become narrower in another dimension (e.g. width, along the direction at a 90 degree angle to the radial inward direction). In certain embodiments, the set dimension (e.g. the diameter of the round pads or the length at the semi-major axis of the elliptical pads) of the pads is predetermined and correspond to the size of the subsequently disposed conductive elements or balls.

In certain embodiments, by arranging elliptical pads in the inner region surrounding the die and round pads in the outer region surrounding the die, larger space allowance between the adjacent pads are saved for routing portions or traces passing through there-between, thus enhancing the layout flexibility and improving the reliability of the package. In certain embodiments, the pads closer to the die, the shorter the sizes at the semi-minor axis of the elliptical pads. In certain embodiments, the changes in sizes at the semi-minor axis of the pads may be in a linear relationship or a non-linear relationship relative to the distance between the die and the pad(s). In some embodiments, the decrease in sizes at the semi-minor axis of the pads may be in a stepwise manner relative to the distance between the die and the ring(s) of the pads. In some embodiments, the pads most distant from the die may be round pads. In the exemplary embodiments, round pads and elliptical pads are used as examples, but the shapes of the pads are not limited by the embodiments herein and other polygonal shapes may be adopted

FIG. 10Ais a schematic top view illustrating the exemplary layout of a portion of the redistribution layer in the package structure according to some exemplary embodiments of the present disclosure. InFIG. 10A, the UBM patterns are shown to illustrate the relative locations and sizes of the UBM patterns and joining portions JP and routing portions RP of the redistribution layer170A. InFIG. 10A, the location of the via portions VA connected to the joining portions JP are shown as dotted lines.FIGS. 10B-10Dare schematic cross sectional views illustrating the first, second and third pads of the joining portions JP inFIG. 10Arespectively along the cross section lines A-A′, B-B′ and C-C′.

InFIG. 10A, in some embodiments, portions of the joining portions JP of the redistribution layer170A are connected with portions of the routing portions RP. In some embodiments, the joining portions JP include first pads1010, second pads1020and third pads1030, and the routing portions RP include first routing traces1040, second routing traces1050, third routing traces1060and fourth routing trace1070. Referring toFIGS. 10A-10D, in certain embodiments, the first pads1010are connected with the first routing traces1040through first joining neck portions1015of the first pads1010. In some embodiments, the first pad1010may be shaped as an almost round pad with the first joining neck portion1015protruding outward and tapering from the pad1010to the first routing trace1040. In certain embodiments, the second pads1020are connected with the second routing traces1050through second joining neck portions1025of the second pads1020. In some embodiments, the second pad1020may be shaped as an almost elliptical pad with the second joining neck portion1025protruding outward and tapering from the pad1020to the second routing trace1050. In certain embodiments, the third pads1030are connected with the third routing traces1060through third joining neck portions1035of the third pads1030. In some embodiments, the third pad1030may be shaped as an almost elliptical pad with the third joining neck portion1035protruding outward and tapering from the pad1030to the third routing trace1060. In certain embodiments, the extending directions (e.g. the direction approaching the chip, arrow inFIG. 9A) of the joining neck portions and of the routing traces are along the semi-major axis of the almost elliptical pads. In some embodiments, the joining neck portions are designed to smoothly joining the pads and the routing traces, improving the reliability of the redistribution layer. In some embodiments, inFIG. 10A, the joining neck portions1015,1025,1035are located outside the span of the UBM patterns180, thus lowering the line or trace break issues. One dimension (length) d1of the first, second and third pads is set to be the same dimension (e.g. the diameter of the round pads or the length at the semi-major axis of the elliptical pads).

FIG. 11Ais a schematic top view illustrating the exemplary layout of a portion of the redistribution layer170B in the package structure according to some exemplary embodiments of the present disclosure.FIG. 11Bis a schematic cross sectional view illustrating the first pads of the joining portions JP inFIG. 11Aalong the cross section line A-A′. Compared with the redistribution layer170A ofFIG. 10A, the redistribution layer170B ofFIG. 11Ahas no UBM patterns formed thereon. In some embodiments, no UBM patterns are formed before bonding the conductive elements to the pads of the joining portions, as shown inFIG. 11B, but a seed layer1012may be formed on the surfaces of the pads1010for enhancing adhesion between the pads and the overlying dielectric material layer and between the pads and the subsequently disposed conductive elements.

FIG. 12is a schematic cross sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. InFIG. 12, in certain embodiments, a redistribution layer270is located on the active surface210aof a chip210. The redistribution layer270includes a lower dielectric material layer271, a first metallization layer272, a middle dielectric material layer273, a second metallization layer274and a top dielectric material layer275sequentially stacked on the chip210. In some embodiments, UBM patterns280are located on and connected to the joining portions JP of the second metallization layer274. In some embodiments, conductive elements290are located and connected to the UBM patterns280. In some embodiments, some or all of the conductive elements290are electrically connected with the chip210through the UBM patterns280and the redistribution layer270.

In some embodiments, the joining portions JP of the redistribution layer270includes first pads2741, second pads2742and third pads2743. In some embodiments, the first, second and third pads2741,2742, and2743are of different shapes and sizes. In some embodiments, the first pads2741of a size d1are arranged most far away from the center of the chip210, while the third pads2743of a size d3are arranged near or at the center of the chip210. In some embodiments, the second pads2742of a size d2are arranged between the first and third pads2741,2743. In some embodiments, the first size d1is larger than the second size d2and the second size d2is larger than the third size d3. In some embodiments, the configuration and layout of the first, second and third pads2741,2742,2743are similar to the configuration and layout of the first, second and third pads1741,1742,1743ofFIG. 9A, except the span of the chip210is substantially equivalent to the distribution span of the pads.

According to the above exemplary embodiments, the layout and configuration of the redistribution layer may be suitably formed within the integrated fan-out (InFO) wafer-level package structure or a fan-in wafer-level package structure. Although one redistribution layer is described in the above embodiments, more than one or multiple redistribution layers (RDLs) may be provided in the package structure or arranged on both front side and back side of the die(s) or chip(s) for signal redistributions among multiple dies or chips.

In certain embodiments, for the ball pads of the joining portions in the redistribution layer, by arranging narrower or elliptical pads in the inner region surrounding the die and larger or round pads in the outer region surrounding the die, more space between the adjacent pads is provided allowing routing portions or traces passing through, providing higher routing density and improving the reliability of the package. In certain embodiments, the pads closer to the die, the shorter the sizes at the semi-minor axis of the elliptical pads. In some embodiments, joining neck portions are formed between the pads and the routing traces of the redistribution layer, and the joining neck portions are designed to smoothly joining the pads and the routing traces, improving the reliability of the redistribution layer. In some embodiments, the joining neck portions are located outside the span of the UBM patterns, thus lowering the line or trace break issues.

According to some embodiments, a semiconductor package has at least a chip and a redistribution layer. The redistribution layer is disposed on the chip. The redistribution layer includes joining portions having first pads and second pads surrounding the chip. The first pads are arranged around a location of the chip and the second pads are arranged over the location of the chip. The second pads located closer to the chip are narrower than the first pads located further away from the chip.

According to some embodiments, a semiconductor package at least has a chip and a redistribution layer. The redistribution layer is disposed on the chip and electrically connected with the chip. The redistribution layer includes joining portions and routing portions. The joining portions include first pads and second pads surrounding the chip, and the first pads are located further away from the chip and the second pads are located closer to the chip. The routing portions include first routing traces and second routing traces respectively connected to the first and second pads and extending in a first direction approaching the chip. A first size in the first direction of the first pads is substantially equivalent to a second size in the first direction of the second pads, and the second pads have a third size in a second direction that is perpendicular to the first direction, and the third size is smaller than the second size.

According to some embodiments, a manufacturing method for semiconductor packages is provided. A chip is provided on a carrier. A redistribution layer having joining portions is formed on the chip, and the chip is electrically connected to the redistribution layer. The redistribution layer is formed by forming first pads located further away from the chip and forming second pads that are located closer to the chip and are narrow than the first pads. Conductive elements are disposed on the redistribution layer. The carrier is removed.