Dual edge command in DRAM

A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

FIELD OF THE INVENTION

The present invention relates to memory circuits and, in particular, to circuitry associated with command and address pins of a DRAM (dynamic random access memory).

BACKGROUND OF THE INVENTION

In order to perform data transfers, such as a store and an access, to and from conventional DRAM devices, the command and address signals are generally initiated on a rising edge (the transition from logic level “zero” to “one”) or alternatively a falling edge of a clock signal. In a high speed DRAM design, using the current scheme to store and access the data from a DRAM can result in requiring a significantly higher number of command and address pins. Further, any increase in the number of command and address pins, can also result in a significant overhead for the DRAM controller performing data transfers via multiple DRAMs. For example, a DRAM controller coupled to access 8×32 DRAMs in a system, parallelly or concurrently, can require nearly 256 bit input/output (I/O) interfaces. Furthermore, for efficient handling of the command and address signals, the DRAM controller may also have to assign a similar number of command and address pins. Therefore, any increase in the number of command and address pins in a DRAM, in the above system, can also result in requiring similar increase in the command and address pins in each DRAM for the DRAM controller. This is because of operating the command and address signals at half cycles and because of using the command and address pins for a single purpose or a single cycle in conventional double data rate (DDR) DRAM devices.

In addition, during the last several decades, memory technology has progressed dramatically. The density of commercial memory devices, such as the DRAM, has increased from 1 Kbit to 256 Mbits per chip, a factor of 256,000. Unfortunately, as the density goes up the number of command and address pins required to store and access data has also increased considerably. Increasing the number of command and address pins can result in a bigger package size for reasons described-above. As the packaging density increases, accommodating more number of command and address pins in a smaller package becomes more difficult.

Accordingly, there is a need in the art for a technique to reduce the number of command and address pins required in DRAMs to perform data transfers to and from the DRAMs.

SUMMARY OF THE INVENTION

The present invention provides techniques to send command and address signals on both the rising and falling edges and/or on two consecutive rising or falling edges of a clock cycle (timing signal), thereby essentially reducing the number of command and address pins required by the DRAMs.

In one aspect, the invention provides techniques for reducing the number of command and address pins required in a DRAM. In this aspect, the invention includes sending command and address signals to one or more DRAMs to transfer data to and from the DRAMs upon both the rising and falling edges of a clock cycle. In accordance with another aspect of the present invention, a technique for reducing the number of command and address pins required on a DRAM includes sending the command and address signals on the first edge of a clock cycle and further sending address signals on the following edge of the clock cycle.

In accordance with yet another aspect of the present invention, a technique for reducing the number of required command and address pins on a DRAM includes sending the command and address signals on two consecutive rising edges (or falling edges) of a clock signal. In accordance with yet another aspect of the present invention, a technique for reducing the number of required command and address pins on a DRAM includes sending the command and address signals on a rising edge of a clock cycle and further sending the address signals on a subsequent rising edge of the clock cycle.

Additional advantages and features of the present invention will be more apparent from the detailed description and accompanying drawings, which illustrate preferred embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to various specific embodiments in which the invention may be practiced. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural, logical, electrical, and process changes may be made without departing from the teachings of the invention.

The present invention provides techniques to reduce number of command and address pins required in a DRAM to reduce the package size and to essentially increase the number of command and address signals sent for a given set of command and address pins in the DRAM. The terms “sending” and “initiating” are used interchangeably throughout the document. References to “rising edge” and “falling edge” of a clock or control signal is for illustrative purposes only since those skilled in the art readily know that true or complementary clock and control signals may be used in which a rising edge may be substituted for a falling edge. Therefore, a clock or control signal may substitute any clock transition (rising or falling) and still fall within the scope of this description and claims.

Referring now toFIG. 1, there is illustrated one conventional technique employed in initiating command and address signals by a DRAM controller to access data from a DRAM upon the rise (active edge) of a timing signal. As shown in the timing diagram100ofFIG. 1, the DRAM controller sends the command signals120, such as Chip Select (CS#), Row Address Strobe (RAS#), Column Address Strobe (CAS#), and Write Enable (WE#) and the address signals130, such as BA0˜2and A11˜A0during a rising edge112of a clock (CK) signal110. Also shown inFIG. 1is clock signal (CK#)115which is an inverse of the CK signal110. It can be envisioned that the command and address signals can also be initiated, similarly as described-above, during a falling edge of the CK# signal115. As described-above, the problem with this technique is as the density of the DRAMs goes up the number of command and address pins required to store and access data can also increase proportionately in each DRAM. Increasing the number of command and address pins can result in a significantly bigger package size. As the packaging density increases, accommodating more number of command and address pins in a smaller package becomes difficult.

Referring now toFIG. 2, there is illustrated an example timing diagram200of initiating command and address signals by a controller to an integrated circuit memory device according to the present invention. As shown inFIG. 2, the command signals220, such as CS#, RAS#, CAS#, and WE# and address signals230, such as BA0˜2and A0˜11are initiated by the controller during both rising and falling edges202and204of a timing cycle of a timing signal210to increase the transfer rate of the command and address signals during the timing cycle. In some embodiments, the timing cycle of the timing signal is a clock cycle in a clock signal (CK). In these embodiments, the rising and falling edges202and204comprise transition from a logic level “zero” to a logic level “one” and transition from the logic level “one” to the logic level “zero”, respectively.

Also in these embodiments, the controller can be a device, such as a central processing unit (CPU), a graphics processing unit (GPU), a processor, and/or a dynamic random access memory (DRAM) controller. In these embodiments, the integrated circuit memory device is a DRAM device. It can be seen fromFIG. 2that by sending the command and address signal upon both the rising and falling edges of a clock cycle the number of command and address signals sent during a clock cycle can be significantly more than the conventional technique described-above with reference toFIG. 1. It can be envisioned that by increasing the sending of the number of command and address signals in a clock cycle, the number of required command and address pins can be considerably reduced to achieve a higher packaging density in a DRAM.

The clock signal (CK#)215is an inverse of the clock signal (CK)210shown inFIG. 2. Again, it can be envisioned that by initiating the command and address signals during the rising and falling edges of CK#215, similar to initiating the command and address signals during the rising and falling edges of CK210as described-above, the transfer rate of the command and address signals220and230sent during the clock cycle can be increased.

Referring now toFIG. 3, there is illustrated another example timing diagram300of initiating command and address signals by a controller to an integrated circuit memory device according to the present invention. As shown inFIG. 3, the command signals320, such as CS#, RAS#, CAS#, and WE# and address signals330, such as BA0˜2and A12˜8are initiated by the controller during a rising edge302of a clock cycle of a CK310. In addition, the address signals, such as A0˜7are initiated during a falling edge304of the clock cycle of the CK310to increase the transfer rate of the command and address signals during the clock cycle for a given number of command and address pins in a DRAM device. Again it can be envisioned that using an inverse clock signal (CK#)312shown inFIG. 3and initiating command and address signals as described-above can also increase the transfer rate of the command and address signals320and330sent by the controller during the clock cycle.

Referring now toFIG. 4, there is illustrated an example timing diagram400of initiating command and address signals by a controller to an integrated circuit memory device according to the present invention. As shown inFIG. 4, the command signals420, such as CS#, RAS#, CAS#, and WE# and address signals430, such as BA0˜2and A0˜11are initiated by the controller during two substantially consecutive rising edges402of a CK410to increase the transfer rate of the command and address signals during the two substantially consecutive cycles. The transfer rate of the command and address signals achieved by using this method400is lower than the transfer rate achieved with the method200described-above with reference toFIG. 2. Because, the method400essentially requires one additional clock cycle to complete sending all of the command and address signals420and430. But, in the GHz clock frequency era, adding one additional clock cycle to send the command and address signals420and430does not significantly lower the transfer rates.

Referring now toFIG. 5, there is illustrated another example timing diagram500of initiating command and address signals by a controller to an integrated circuit memory device according to the present invention. As shown inFIG. 5, the command signals520, such as CS#, RAS#, CAS#, and WE# and address signals530, such as BA0˜2and A11˜9are initiated by the controller during a rising edge502of a clock cycle of a CK510. In addition, the address signals, such as A0˜8are initiated during a rising edge504of a substantially subsequent clock cycle of the CK510to increase the transfer rate of the command and address signals during two substantially subsequent clock cycles for a given number of command and address pins in an integrated circuit memory device. Again, it can be envisioned that an inverse of the CK510can also be used, as described-above, to increase the transfer rate of the command and address signals sent during the clock cycle. Again, it can also be seen that in the GHz range, adding one additional clock cycle to send the address signals530does not significantly lower the transfer rates of the command and address signals between the controller and one or more integrated circuit memory devices. The hatched state shown inFIGS. 1-5for the command and address signals indicate that the signals must be held in one state so they may be read. The signal portion marked with vertical lines indicate that the signals may be in any state since they are not being read during that time period.

Referring now toFIG. 6, there is illustrated an example embodiment of a memory circuit600according to the present invention. The memory circuit600includes one or more DRAMs610. Each of the DRAMs610includes multiple data pins640and multiple command and address pins630. The memory circuit600further includes a controller620coupled to the one or more DRAMs610via the data pins640and the command and address pins630. In some embodiments, the controller is a device, such as a CPU, a GPU, a processor, and a DRAM controller. Also in these embodiments, the DRAMs can be any integrated circuit memory devices, such as flash memory device, a volatile memory device, a non-volatile memory device, a static random access memory (SRAM) device, and/or a static memory device. In some embodiments, the multiple command and address pins630are coupled to the controller620through a coupling medium650, such as input/output interface and/or a bus.

In operation, the controller620sends command and address signals to each integrated circuit memory device610via the associated multiple command and address pins630, respectively, during a clock cycle of a clock signal so as to increase the transfer rate of the command and address signals during the clock cycle. This is accomplished by sending a higher number of command and address signals than available number of command and address pins630in each integrated circuit memory device610.

In some embodiments, the controller620sends the command and address signals upon both rising and falling edges of a clock cycle when transferring data to and from each integrated circuit memory device610to increase transfer rate of the command and address signals within the clock cycle for a given number of the command and address pins630in each integrated circuit memory device610. In other embodiments, the controller620sends the command and address signals upon a rising edge of a clock cycle and further sends remaining address signals upon a falling edge of the clock cycle when transferring the data to and from the integrated circuit memory device610.

In some embodiments, the controller620sends the command and address signals to each integrated circuit memory device610via its associated multiple command and address pins630, respectively, upon two substantially consecutive rising edges of a clock signal to increase transfer rate of the command and address signals. In other embodiments, the controller620sends the command and address signals to each integrated circuit memory device610via its associated multiple command and address pins630, respectively, upon a rising edge of a clock cycle in a clock signal. Further, the controller620sends the address signals upon a rising edge of a substantially subsequent clock cycle to each integrated circuit memory device610via its associated multiple command and address pins630, respectively, to increase transfer rate of the command and address signals to each integrated circuit memory device610in the two substantially consecutive clock cycles. In the above described embodiments, each of the integrated circuit memory devices610perform the memory command in response to receiving the set of command and address signals. The advantages in using the above techniques to send command and address signals are described-above in more detail with reference toFIGS. 2-5.

FIG. 7is a block diagram of a system according to one embodiment of the present invention. Computer system700contains a processor710and a memory system702housed in a computer unit705. Computer system700is but one example of an electronic system containing another electronic system, e.g., memory system702, as a subcomponent. The memory system702includes a memory device that includes a multichip module as discussed in various embodiments of the present invention. Computer system700optionally contains user interface components. These user interface components include a keyboard720, a pointing device730, a monitor740, a printer750, and a bulk storage device760. It will be appreciated that other components are often associated with computer system700such as modems, device driver cards, additional storage devices, etc. It will further be appreciated that the processor710and memory system702of computer system700can be incorporated on a single integrated circuit. Such single-package processing units reduce the communication time between the processor and the memory circuit. Any of these components of the system may contain a memory controller to initiate command and address signals to retrieve data from a memory device according to the present invention. This is particularly true of graphics subsystem770ofFIG. 7utilizing SGRAM that includes a solid film formed as discussed in various embodiments of the present invention.

FIG. 8is a block diagram of a system according to one embodiment of the present invention. Memory system800contains one or more multichip modules802and a memory controller812. Each memory module802includes at least one memory device810. Memory controller812provides and controls a bidirectional interface between memory system800and an external system bus820. Memory system800accepts a command signal from the external bus820and relays it to the one or more memory modules802on a command link830. Memory system800provides for data input and data output between the one or more memory modules802and external system bus820on data links840. At least one of the memory devices810includes the DRAM controller to initiate command and address signals to retrieve data from one or more DRAMs according to the present matter.

With reference toFIG. 9, in one embodiment, a semiconductor die910is produced from a silicon wafer900. A die is an individual pattern, typically rectangular, on a substrate that contains circuitry to perform a specific function. A semiconductor wafer will typically contain a repeated pattern of such dies containing the same functionality. Die910may contain multichip modules, as discussed above. Die910may further contain additional circuitry to extend to such complex devices as a monolithic processor with multiple functionality. Die910includes a DRAM controller coupled to one or more DRAMs as discussed in various embodiments of the present invention.

Conclusion

The above description illustrates preferred embodiments, which achieve the features and advantages of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Modifications and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.