Hard mask for low-k interlayer dielectric patterning

Described herein are embodiments of a hard mask including a surface to reduce adhesion to an anti-reflective material deposited on a surface, wherein the surface to reduced adhesion provides use of a process to remove the anti-reflective material deposited on the surface that minimizes damage to an interlayer dielectric layer below the hard mask and methods of manufacturing the same.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor devices and more specifically to patterning of an interlayer dielectric layer.

2. Discussion of Related Art

The fabrication of semiconductor devices with smaller dimensions and the increasing switching speeds of transistors necessitate the use of copper lines and low-k interlayer dielectric (ILD) layers to accommodate the high speed signals. The use of the copper and low-k interlayer dielectric layers reduces the resistance of the metal interconnects and the capacitance between the metal interconnects to enable the high speed signals to be transmitted. Because low-k interlayer dielectric layers are affected by similar process techniques that are used to pattern and remove other layers used to create a semiconductor device, the low-k interlayer dielectric layer is susceptible to being altered from the shape or characteristics the layer was designed to exhibit.

A current solution to protect a low-k interlayer dielectric layer is to form a hard mask layer over a low-k interlayer dielectric to protect the low-k interlayer dielectric layer from processes performed on other layers. For example, an anti-reflective layer and a photoresist layer may be formed over an interlayer dielectric layer for patterning the interlayer dielectric layer as necessary to form a semiconductor device. Once the low-k interlayer dielectric layer is patterned, the remaining photoresist and anti-reflective layer must be removed. In the absence of using a hard mask layer that separates the interlayer dielectric layer from the anti-reflective and the photoresist layers, an etch process or a chemical mechanical polishing process performed to remove an anti-reflective layer and a photoresist layer would result in degradation of the interlayer dielectric layer. As mentioned above, the degradation results because the chemistries that are used to etch or remove photoresist and anti-reflective layers are the same chemistries that may be used to remove an ILD layer. Therefore, the characteristics or dimensions of the patterns in the ILD may be significantly altered during the etching or removal of an anti-reflective and photoresist layers. This ultimately would result in unreliable operation of semiconductor devices or low manufacturing yields of properly operating semiconductor devices. Therefore, the use of a hard mask is needed to protect the ILD layer from the processes used to alter other layers.

Problems arise in the use of a hard mask when the material used for the hard mask reacts with the layer deposited above the hard mask. Such a reaction may create a strong adhesion between the hard mask and the upper adjoining layer, such as an anti-reflective layer, making an adjoining layer more difficult to remove. Therefore, a more aggressive chemistry must be used, longer exposure to a removal process must be used, or a combination of an aggressive chemistry and longer exposure to a removal process must be used to remove the upper layers from the hard mask. The use of a more aggressive chemistry and longer exposure to a removal process results in excessive degradation of an interlayer dielectric layer. Such degradation includes the interlayer dielectric layer unpredictably undercutting the hard mask. Because degradation of the interlayer dielectric layer, such as undercutting, effects the characteristics and dimensions of the interlayer dielectric layer the operating characteristics of a semiconductor device and reliability of a semiconductor device are degraded.

SUMMARY

Described herein are embodiments of a hard mask including a surface to reduce adhesion to an anti-reflective material deposited on a surface, wherein the surface to reduced adhesion provides use of a process to remove the anti-reflective material deposited on the surface that minimizes damage to an interlayer dielectric layer below the hard mask and methods of manufacturing the same.

DETAILED DESCRIPTION

In the following description numerous specific details are set forth in order to provide an understanding of the claims. One of ordinary skill in the art will appreciate that these specific details are not necessary in order to practice the disclosure. In other instances, well-known semiconductor fabrication processes and techniques have not been set forth in particular detail in order to prevent obscuring the present invention.

Embodiments of the present invention include a hard mask that reduces exposure of an interlayer dielectric layer (ILD) to aggressive chemistries during a semiconductor fabrication process to prevent damage to a fragile interlayer dielectric layer. Embodiments of the hard mask reduce the adhesion between a hard mask and other layers, such as an anti-reflective layer, in contact with the hard mask used during a semiconductor fabrication process. The reduced adhesion between the hard mask and the other layers provides for the other layers to be removed from the hard mask using less aggressive removal processes. Since the adhesion between embodiments of the hard mask and a layer formed over the hard mask is reduced, chemistries that are less likely to damage or change the characteristics of an interlayer dielectric layer, such as a low-k interlayer dielectric layer, may be used to remove a layer formed over the hard mask. Likewise, the reduction in adhesion between embodiments of the hard mask and a layer formed over the hard mask enables removal of the layer in less time. Because removal of a layer over an embodiment of the hard mask may be removed in less time the interlayer dielectric layer is exposed to the semiconductor process for less time, which reduces the amount of damage that may result from the semiconductor process.

Embodiments of the hard mask that result in the reduction of the adhesion between the hard mask and an adjoining layer through methods including the choice of a material to form a hard mask from, a bilayer hard mask, doping a hard mask with a particular element to reduce adhesion, and modifying the surface of the hard mask to reduce the adhesion. Certain embodiments reduce the adhesion by using a hard mask formed from materials that result in less reactivity between a hard mask and an adjoining layer to minimize adhesion between the layers.FIG. 1illustrates an embodiment that uses a bulk layer hard mask115composed of a material, such as titanium nitride, to reduce the adhesion with an anti-reflective layer120, such as a sacrificial light absorbing material (SLAM), formed over hard mask115.

TheFIG. 1embodiment illustrates an example of a formation of layers used in a semiconductor manufacturing process. An interconnect layer101may be formed from materials including copper, aluminum, tantalum, and tungsten. An etch stop layer105in theFIG. 1embodiment is formed over interconnect layer101. The etch stop layer105may be formed from silicon carbonate, silicon nitride, or any other material known in the art that can be used as an etch-stop layer. In some embodiments the etch-stop layer105is also used as a barrier layer to prevent the migration of the metal used in the interconnect layer101from migrating into other layers.

As shown inFIG. 1, an interlayer dielectric layer110may be formed over etch stop layer105. For an embodiment, an interlayer dielectric layer110is a low-k interlayer dielectric. Another layer illustrated in theFIG. 1embodiment is a hard mask layer115formed over an interlayer dielectric layer110to protect the interlayer dielectric layer110from processing preformed on the other layers. For certain embodiments, an interlayer dielectric layer110needs to be pattered; therefore, an anti-reflective layer120is formed over the hard mask layer115, as illustrated inFIG. 1. For some embodiments, a sacrificial light absorbing material (SLAM) may be used to form an anti-reflective layer120to coat hard mask layer115to prevent reflections of the hard mask layer115from interfering with lithographic patterning. A photoresist layer125is then deposited on the anti-reflective layer120of theFIG. 1embodiment. The photoresist layer125may then be exposed to a photolithograpy process to define a pattern in the photoresist. The pattern formed in the photoresist layer125may then be used to etch the lower layers such as an anti-reflective layer120, a hard mask layer115, and an interlayer dielectric layer110. The etching may be preformed by a wet etch or a dry etch process. Examples of a dry etch processes include reactive ion etching (RIE), plasma etching, and physical sputtering.

For another embodiment, hard mask layer125may be composed of a single uniform layer that is doped to reduce the adhesion between hard mask layer115and anti-reflective layer120. Materials that may be used to form a single uniform layer that is doped to reduce adhesion include materials such as titanium, tantalum, silicon or any other material known in the art that may be used as a hard mask. One example of a doped uniform layer is a titanium layer doped with nitrogen.

FIG. 2illustrates an embodiment using a bilayer hard mask to reduce the adhesion between a hard mask layer115and another layer such as an anti-reflective layer120. In theFIG. 2embodiment, the hard mask layer115is formed from a lower hard mask layer114and an upper hard mask layer116. The lower hard mask layer114may be formed from materials known in the art to provide protection to an interlayer dielectric layer110, such as a low-k interlayer dielectric layer. Examples of materials that may be used for the lower hard mask layer114include titanium and tantalum. Moreover, theFIG. 2embodiment of a hard mask layer115that is formed from a bilayer includes an upper layer116. The upper layer116of an embodiment is chosen as one that reduces the adhesion between a hard mask layer115and an anti-reflective layer120. For one embodiment, a hard mask layer115formed from a bilayer including a lower layer114and an upper layer116includes a lower layer114formed from titanium and an upper layer116formed from titanium nitride.

TheFIG. 3illustration shows an embodiment of a hard mask used to form vias305and a Dual Damascene structure301. An embodiment of the hard mask115is used inFIG. 3to protect an interlayer dielectric layer110from a process used to form vias305and a Dual Damascene structure301. Because an embodiment of the hard mask layer115is used in theFIG. 3embodiment less aggressive clean chemistries may be used to remove the anti-reflective layer120from the surface of the hard mask layer115. Furthermore, the resulting lower adhesion between an anti-reflective layer120and an embodiment of the hard mask layer115provides the use of shorter duration processes to remove the anti-reflective layer120. For example, an embodiment of a hard mask layer115, such as a titanium nitride layer, may reduce clean times by 75%. The use of less aggressive wet chemistries and the reduction of time that the Interlayer dielectric layer110is exposed to a removal process, such as via and trench cleans, result in less damage to an interlayer layer dielectric layer110. Thus, hard mask undercut is reduced and hard mask delamination margin for baseline processes with and without lithographic rework may increase.

As mentioned above an embodiment of the hard mask may be used in a Dual Damascene process.FIGS. 4A-4Hillustrate a Dual Damascene process that employs an embodiment of the hard mask that reduces adhesion between an anti-reflective layer120, thus providing the ability to use less aggressive clean chemistries and the ability to reduce the amount time an interlayer dielectric layer110is exposed to a process that could alter the characteristics of an interlayer dielectric layer110.FIG. 4Ashows an embodiment of a lower interconnect layer401including a first interconnect405. The first interconnect405may be formed from any material known in the art for creating interconnects, such as copper, aluminum, titanium, and tantalum. An embodiment, such as the one illustrated inFIG. 4Amay include an etch stop layer410or a hard mask formed over interconnect layer401. Etch stop layer410is used to protect the lower interconnect layer401from a process performed on upper layers. Alternatively, etch stop layer410may be used to prevent diffusion of metal into an interlayer dielectric layer110, such as copper diffusion from a copper first interconnect405into an interlayer dielectric layer415. Etch stop layer410may be formed from any material known in the art to protect lower layers from a process preformed on upper layers, such materials include silicon nitride and silicon carbide.

For an embodiment, an interlayer dielectric layer415may be formed over an interconnect layer401as illustrated in theFIG. 4Aembodiment. The interlayer dielectric layer415may be formed from any material known in the art for forming interlayer dielectric layers. For one embodiment the interlayer dielectric layer is a low-k dielectric layer such as silicon dioxide or carbon-doped oxide. An embodiment of the interlayer dielectric layer415may be formed from any method known in the art, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and sputtering. As illustrated inFIG. 4B, an embodiment includes forming a hard mask layer420over an interlayer dielectric layer415. An embodiment of a hard mask layer420may be formed to a thickness including 10 nanometers to 30 nanometers. The hard mask layer420may be formed by any method known in the art for forming hard masks including chemical vapor deposition, plasma enhanced chemical vapor deposition, and sputtering. For an embodiment, a hard mask layer420is formed of a bulk material that reduces the adhesion between the hard mask layer and another layer formed over the hard mask layer420. An embodiment of a hard mask layer420may be formed from a bulk material such as titanium nitride.

Alternatively, one embodiment includes a hard mask layer420formed from a material and then doped to reduce the adhesion between the contact surface of a hard mask layer420. Materials that may be used include materials known in the art to be used for a hard mask such as the materials discussed above. Moreover, the hard mask layer420may be formed by processes known in the art to form a hard mask such as those discussed above. Such a hard mask layer420may be doped by processes known in the art including diffusion and ion implantation. One such embodiment includes forming a titanium layer over dielectric layer415and then doping the titanium layer with nitrogen to form a hard mask layer420.

Another embodiment includes a hard mask layer420formed from a bilayer. For a bilayer embodiment of hard mask layer420, the hard mask layer420may be formed from at least two layers. The first layer may be a hard mask material known in the art, such as titanium, tantalum, and silicon nitride. The second layer for the bilayer embodiment of hard mask layer420may be a layer modified to reduce the adhesion between that layer and a layer formed over a bilayer embodiment of a hard mask layer420. The first and second layers may be formed by any process known in the art for forming a hard mask layer including chemical mechanical deposition, plasma enhanced chemical mechanical deposition and sputtering techniques. For an embodiment, the first layer of a bilayer hard mask layer420may be formed from titanium and the second layer may be formed from titanium nitride. One such embodiment of a bilayer hard mask layer420includes forming a bilayer such that the thickness ratio of a first layer of the bilayer hard mask layer420to a second layer of the bilayer hard mask layer420includes a ratio of less than seven to one.

An embodiment of a hard mask layer420that reduces the adhesion between layers is formed by modifying a contact surface of a hard mask layer420to achieve a weak adhesion between the hard mask layer420and a layer formed over the hard mask layer420. For an embodiment the surface of the hard mask layer420is modified to reduce the adhesion between the hard mask layer420and a layer deposited over the hard mask layer420. Such an embodiment includes modifying a contact surface of a hard mask layer420with a plasma or chemical process. For example, a contact surface of a hard mask layer420formed of titanium may by chemically modified to reduce the adhesion between the hard mask layer and a layer of anti-reflective material over the hard mask layer420.

Once a hard mask layer420is formed, other layers may be formed over the hard mask layer420. As illustrated in theFIG. 4Cembodiment, an anti-reflective layer425is formed over a hard mask layer420that reduces the adhesion between the anti-reflective layer425and the hard mask layer420. The anti-reflective layer425may be formed from any anti-reflective material known in the art that prevents profile degradation caused by reflections from a reflective hard mask including an organic anti-reflective coating or an in organic anti-reflective coating. For an embodiment a sacrificial light absorbing material (SLAM) may be used as anti-reflective layer425. For another embodiment the anti-reflective layer may be an organic anti-reflective material.

Moreover, theFIG. 4Cembodiment illustrates a photoresist layer430formed over anti-reflective layer425. For an embodiment as illustrated inFIG. 4Dthe photoresist layer430is pattered to expose an area to be etched to form a via for the Dual Damascene process represented inFIGS. 4A-4H. Once photoresist layer430is patterned, the lower layers may be etched to form a via as illustrated inFIG. 4E. The via may be etched using techniques known in the art including chemical etch processes and a plasma etch processes. The via shown inFIG. 4Eis formed through an anti-reflective layer425, a hard mask layer420and an interlayer dielectric layer415.

For an embodiment of a Dual Damascene process using a hard mask layer420that reduces adhesion with another layer, once the via is formed anti-reflective layer425and photoresist layer430are removed. For an embodiment anti-reflective layer425and photoresist layer430are removed using wet chemistries. Because adhesion between a hard mask layer420and an anti-reflective layer425are reduced less aggressive clean chemistries, such as may be used to remove the anti-reflective layer425and less time is needed for the cleaning process. As a result of the ability to use less aggressive clean chemistries because of the reduced adhesion between an embodiment of the hard mask layer420and another layer such as an anti-reflective layer425as illustrated inFIG. 4D, less damage to an interlayer dielectric layer415results because of exposure to a process such as those using wet chemistries. Therefore, undercut of an interlayer dielectric layer415is reduced and that in turn allows an increase in hard mask delamination margin for baseline processes.

As shown inFIG. 4F, a second anti-reflective layer440may be formed over a hard mask layer420. Similar to anti-reflective layer425, a second anti-reflective layer440is used to minimize the reflectivity of a hard mask layer420residing below to prevent degradation of a photolithograpy process. A second photoresist layer445may also be formed over a second anti-reflective layer440, as illustrated inFIG. 4F. Similar to photoresist layer430, a second photoresist layer445is patterned to expose the underlying layer for forming the trench for the Dual Damascene process. As shown inFIG. 4G, trench450is etched through an anti-reflective layer440, a hard mask layer420, an interlayer dielectric layer415, and an etch stop layer410. The metal interconnect405as shown inFIG. 4Gis now exposed by the etch process.

Once the etch process is complete, a second photoresist layer445and a second anti-reflective layer440may be removed. For an embodiment, a wet etch chemistry may be used to remove the second photoresist layer445and the second anti-reflective layer440illustrated in theFIG. 4Gembodiment. As discussed above, hard mask layer420reduces the adhesion between a second anti-reflective layer440and a hard mask layer420, as illustrated inFIG. 4G. The weak adhesion between a second anti-reflective layer440and a hard mask layer420provides the ability for the second anti-reflective mask layer440to be removed using less aggressive chemistries and requiring less time. Because the exposed layers below a hard mask layer420may be exposed to less aggressive chemistries during a clean process and for less time the lower layers, such as an interlayer dielectric layer415are less likely to be effected by the process. Therefore, hard mask undercut of an interlayer dielectric layer415is reduced and hard mask delamination margin for basline processes is increased.

Now that trench450of the Dual Damascene process, as illustrated inFIG. 4G, is complete, hard mask layer420may be removed. For an embodiment, a hard mask layer420may be removed using a chemical mechanical polishing (CMP) technique. Another embodiment may include removing hard mask layer420using a lift-off process. One such lift-off process may be used for a bilayer embodiment of hard mask layer420. For a lift-off process used to remove a bilayer embodiment of hard mask layer420, a wet etchant may be used to undercut a lower layer of a bilayer embodiment of hard mask layer420until the hard mask layer420lifts from a lower adjoining layer, such as an interlayer dielectric layer415. One embodiment of a bilayer hard mask layer420using a lift-off process includes a titanium lower layer with a titanium nitride upper layer. For such an embodiment, a wet etchant such as a chlorine or a bromine based wet etchant may be used to etch the lower titanium layer until the bilayer hard mask layer may be removed.

For an embodiment, a second interconnect455is formed in trench450created in interlayer dielectric layer415, as illustrated inFIG. 4H. The second interconnect455may be formed by a technique known in the art for forming interconnects such as chemical vapor deposition, plasma enhanced chemical vapor deposition, electroplating, and sputtering. For embodiments of the second interconnect455metals such as copper, aluminum, titanium, and tantalum may be used. Other embodiments include depositing a barrier layer on the sides of trench455and via435prior to depositing a second interconnect455. One such embodiment includes using a tantalum barrier layer and depositing copper over the tantalum barrier layer.

Although embodiments of the present invention have been described in language specific to structural features and/or methodological acts, it is to be understood that the embodiments of the present invention defined in the appended claims are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as particularly graceful implementations of the claimed invention.