MANUFACTURING METHOD OF DISPLAY AND DISPLAY

Provided is a manufacturing method of a display including a vertical organic light-emitting transistor in which a wider light-emitting area is secured while manufacturing time and manufacturing cost are suppressed. In the manufacturing method of the display including the vertical organic light-emitting transistor, a gate electrode layer of the vertical organic light-emitting transistor and one of current-carrying electrode layers of a thin-film transistor connected to the gate electrode layer of the vertical organic light-emitting transistor are formed integrally in the same layer.

TECHNICAL FIELD

The present invention relates to a manufacturing method of a display and a display.

BACKGROUND ART

In recent years, the practical use of a light source element using an organic semiconductor light-emitting element has progressed, and a display using an organic semiconductor light-emitting element as a light source element has become commercially available. In the development of displays that use organic semiconductor light-emitting elements as light source elements, studies on higher brightness, higher definition, lower power consumption, and longer life have still been conducted in order to further improve performance.

Pixels of conventional display using the organic semiconductor light-emitting element as the light-emitting element are constituted of an organic light-emitting diode (also referred to as “OLED”) and a transistor that controls a current flowing through the organic light-emitting diode. The organic light-emitting diode is a device that emits light in response to the current input from a thin-film transistor (also referred to as “TFT”) formed on a substrate to an organic electroluminescent (EL) layer sandwiched between an anode electrode and a cathode electrode.

However, with respect to this configuration, Patent Document 1 below describes a vertical organic light-emitting transistor (also referred to as “VOLET”), as an element configured to reduce the number of control elements and increase the brightness by increasing the light-emitting area, which is configured to adjust the flowing current by controlling the voltage applied to a gate electrode, and meanwhile, emit light according to an amount of current flowing through the transistor itself. Further, Patent Document 2 below describes a display using a vertical organic light-emitting transistor, and the above described elements are expected to significantly increase the brightness of the display.PTL 1: Patent Document 1: WO 2009/036071 APTL 2: Patent Document 2: JP-A-2014-505324

SUMMARY OF THE INVENTION

A display using organic EL is expected to be applied not only to home televisions and smartphones, but also to advertising displays displayed on pillars installed in such as train stations. Therefore, the organic EL display is required to be provided at a lower cost while improving the performance and quality such as brightness and resolution according to the usage mode.

However, without optimizing the process flow, a display provided with a vertical organic light-emitting transistor has more number of manufacturing processes and a higher manufacturing cost than a display provided with the conventional organic light-emitting diode.

The display provided with the vertical organic light-emitting transistor has an advantage that the number of thin-film transistors can be reduced as compared with the display provided with the conventional organic light-emitting diode. However, because the thin-film transistors are formed at different positions in the same layer at the same time, the influence on the number of manufacturing processes and the manufacturing cost due to the increase in the number of transistors is small.

Further, based on the standard, non-optimized process flow, the display provided with the vertical organic light-emitting transistor requires more manufacturing processes to form an additional gate electrode and a gate insulating film layer than a display provided with a simple organic light-emitting diode. Therefore, in the manufacturing process of the display including the organic light-emitting diode, simply replacing the process of forming the organic light-emitting diode with the process of forming the vertical organic light-emitting transistor increases the time and cost required for manufacturing.

In view of the above problems, it is an object of the present invention to provide a manufacturing method of a display including a vertical organic light-emitting transistor in which a wider light-emitting area is secured while suppressing manufacturing time and manufacturing cost.

A manufacturing method of a display according to the present invention is a manufacturing method of a display including a vertical organic light-emitting transistor, the method including:forming integrally on a same layer, a gate electrode layer of the vertical organic light-emitting transistor and one of current-carrying electrode layers of a thin-film transistor connected to the gate electrode layer of the vertical organic light-emitting transistor.

In the present specification, the current-carrying electrode layer of the thin-film transistor is used as a general term for a source electrode layer and a drain electrode layer of the thin-film transistor. In many thin-film transistors formed as components of a display, the source electrode layer and the drain electrode layer are formed in the same layer separated by a channel length. The current-carrying electrode layer of the thin-film transistor is classified into the source electrode layer or the drain electrode layer according to wiring and nodes to be connected.

A display in which a pixel is constituted of the organic semiconductor light-emitting element and the thin-film transistor is formed with, on the lower layer side, a thin-film transistor, a gate line for transmitting a signal to the thin-film transistor for each pixel, a current supply line for supplying the current to the organic semiconductor light-emitting element, and others. Then, the organic semiconductor light-emitting element is formed on the upper layer side of the thin-film transistor, the current supply line, and the others. In the following description, for convenience of explanation, the configuration is described assuming that the upper layer side indicates a direction of laminating each layer from the substrate side.

The display using the organic light-emitting diode as the light-emitting element requires at least two thin-film transistors for current control and for supply switching as a configuration for driving and controlling one organic light-emitting diode. On the other hand, the display using the vertical organic light-emitting transistor as the light-emitting element has a configuration of driving and controlling one vertical organic light-emitting transistor, in which only one thin-film transistor whose current-carrying electrode layer (which is assumed to be the drain electrode layer in the following description) is connected to the gate electrode layer of the vertical organic light-emitting transistor.

Further, because the gate electrode layer of the vertical organic light-emitting transistor is a terminal for controlling the electric field between the source electrode layer and the drain electrode layer of the vertical organic light-emitting transistor, the gate electrode will not be connected with low impedance to nodes other than the current-carrying electrode layer of the thin-film transistor. For this reason, even if the gate electrode layer of the vertical organic light-emitting transistor and one of the current-carrying electrode layers of the thin-film transistor connected to the gate electrode layer are formed integrally, a problem of voltage IR drop due to high current separately flowing through a parallel conductive path with other nodes will not occur.

Therefore, by adopting the above manufacturing method, the process of forming the gate electrode layer of the vertical organic light-emitting transistor and the process of forming the current-carrying electrode layer of the thin-film transistor can be performed at the same time. Therefore, the number of processes is reduced as compared with the case of forming the above transistors by separate processes.

Further, because the display manufactured by the above manufacturing method does not require a contact hole between the gate electrode layer of the vertical organic light-emitting transistor and the current-carrying electrode layer of the thin-film transistor, the wider light-emitting area can be secured.

In the manufacturing method, the vertical organic light-emitting transistors may have at least two or more source electrode layers formed integrally on the same layer.

By using the manufacturing method, the source electrode layer and the current supply line of the vertical organic light-emitting transistor provided in each light-emitting area are not necessarily connected to each other by another wiring. That is, the number and area of the current supply lines that supply current to the source electrode layer of each vertical organic light-emitting transistor are reduced.

Conventionally, the current supply lines are formed in a grid pattern over the entire display between the vertical organic light-emitting transistors formed in an array. However, according to the manufacturing method, when a driver that supplies the current for driving the vertical organic light-emitting transistor is connected to at least one vertical organic light-emitting transistor, the current is supplied to the remaining vertical organic light-emitting transistors through the integrally constituted source electrode. That is, the number and area of the current supply lines that supply the current to the source electrode layer are reduced, the area for forming the current supply lines is significantly reduced, and the materials required for forming the current supply lines are significantly reduced.

In the case of forming the current supply line on the gate insulating film of the vertical organic light-emitting transistor and forming the source electrode of the vertical organic light-emitting transistor integrally so as to straddle the plurality of vertical organic light-emitting transistors, because the formation of the contact holes for connection is not required and a complicated pattern does not need to be formed, the manufacturing time and the manufacturing cost do not increase significantly.

Further, because the source electrode layer of the vertical organic light-emitting transistor formed integrally on the same layer has a function of sharing the current flowing through the current supply line, the influence of voltage drop due to parasitic resistance or the like is suppressed. Further, the area created by reducing the current supply line can be used to expand the light-emitting area.

In the manufacturing method, the source electrode layer of the vertical organic light-emitting transistor may be formed after a surface layer serving as a base is formed, by forming a thin film or a percolating network of a conductive material on a main surface of the surface layer.

By using the manufacturing method, for example, the source electrode layer of the vertical organic light-emitting transistor can be formed of conductive material such as carbon material, which is difficult to fix and form the electrode layer by itself. Further, for example, the surface layer can be formed so as to straddle the plurality of vertical organic light-emitting transistors, and the source electrode can be formed so as to straddle a part of the vertical organic light-emitting transistors. By adopting the above configuration, the material cost can be suppressed by forming the source electrode layer with the configuration in consideration of the influence of the wiring impedance of the current supply line.

Here, as the conductive material laminated on the main surface of the surface layer, for example, carbon nanotubes, graphene, graphite, metal nanowires and the like can be adopted.

In the manufacturing method, after the surface layer is formed, a part of the main surface of the surface layer may be formed with a current supply line configured to supply current to the source electrode layer of the vertical organic light-emitting transistor, andafter the current supply line is formed, the source electrode layer of the vertical organic light-emitting transistor may be formed of the conductive material so as to straddle the surface layer and the current supply line.

By the manufacturing method, the current supply line can be formed in an area sandwiched between the vertical organic light-emitting transistors. This eliminates the need to secure an area for forming the current supply line in a layer below the vertical organic light-emitting transistor. This configuration can secure the wider light-emitting area, particularly in the above-described display in which a bottom emission method is adopted.

In the manufacturing method, the gate electrode layer of the vertical organic light-emitting transistor may be formed of a material made of metal oxide that exhibits conductivity and transparency to light.

In addition, the manufacturing method may further include forming a color filter layer that transmits light in a part of a wavelength band of light emitted from the vertical organic light-emitting transistor.

The display according to the present invention includes: a vertical organic light-emitting transistor; and a thin-film transistor in which one of the current-carrying electrode layers is connected to a gate electrode layer of the vertical organic light-emitting transistor, in which the gate electrode layer of the vertical organic light-emitting transistor and the one of the current-carrying electrode layer of the thin-film transistor are formed integrally on a same layer. Typically, both current-carrying electrodes of the thin-film transistor, namely the source electrode and the drain electrode will be formed integrally on the same layer in the same process. Additionally, the source electrode of the thin-film transistor and the data line will be formed integrally on the same layer in the same process. Therefore, the data line, the source electrode and drain electrode of the thin-film transistor, and the gate electrode of the vertical organic light-emitting transistor can all be formed integrally on the same layer in the same process. Higher electrical conductivity is desired for the data line to ensure refresh rate, while high optical transparency is needed for the gate electrode of the vertical organic light-emitting transistor for a bottom emission display method. Good balance between electrical conductivity and optical transparency of the layer is desirable. Alternatively, the gate electrode of the vertical organic light-emitting transistor can be formed as a transparent and conductive component of a multi-layered structure, where in the data line, the source electrode and drain electrode of the thin-film transistor portion of the multi-layered structure in which optical transparency is not required, opaque but highly conductive metal layer component can be incorporated to enhance electrical conductivity.

In the display, the vertical organic light-emitting transistors may have at least two or more source electrode layers formed integrally on the same layer.

In the display, the vertical organic light-emitting transistor may have a source electrode layer made of a conductive material and formed on a main surface of a surface layer as a base.

In the display, a part of the main surface of the surface layer may be formed with a current supply line configured to supply current to the source electrode layer of the vertical organic light-emitting transistor, and the source electrode layer of the vertical organic light-emitting transistor may be formed of the conductive material so as to straddle the surface layer and the current supply line.

The display may further include, on an outer side of the thin-film transistor when viewed from a direction of laminating each layer, a color filter layer that transmits light in a part of a wavelength band of light emitted from the vertical organic light-emitting transistor, in which the gate electrode layer of the vertical organic light-emitting transistor may be formed of a material made of metal oxide that exhibits conductivity and transparency to light.

Here, “the outer side of the thin-film transistor when viewed from the direction of laminating each layer” means an area where the gate electrode layer of the thin-film transistor overlaps with the source electrode layer and the drain electrode layer when viewed from the direction, and further means the outer side of an area in between the source electrode layer and the drain electrode layer, that is, an area in which a channel of the thin-film transistor is formed.

The display may further include a resin layer between the source electrode layer and an organic semiconductor layer of the vertical organic light-emitting transistor, in which the resin layer may be formed with, in an active area of the display, an opening in an area where the source electrode layer and the gate electrode layer of the vertical organic light-emitting transistor overlap with each other when viewed from the direction of laminating each layer.

The “active area” here means a light-emitting area when viewed from the direction of laminating each layer. Specifically, the terms are described with reference toFIG.1in the section of “Detailed description of the preferred embodiments”.

The display may further include an auxiliary line that is directly or indirectly connected with one or more current supply lines to help supply and distribute current.

In the display, the auxiliary line may be formed on a same layer in the same process with one of the current-carrying electrode layer of the thin-film transistor.

In the display, the auxiliary line may be formed on a same layer in the same process with the gate electrode layer of the thin-film transistor.

According to the present invention, a manufacturing method of a display including a vertical organic light-emitting transistor in which a wider light-emitting area is secured while suppressing manufacturing time and manufacturing cost is realized.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a manufacturing method of a display of the present invention and a configuration of the display manufactured by the method are described with reference to the drawings. In addition, each of the following drawings is schematically shown, and the dimensional ratio and the number of constituents in the drawings do not always match the actual dimensional ratio and the number.

FIG.1is a schematic configuration diagram of a part of an embodiment of the display1. As shown inFIG.1, the display1of the present embodiment includes light-emitting units10including later-described vertical organic light-emitting transistors20, which are aligned in an array, data lines11, current supply lines12, and gate lines13, and auxiliary lines14.

Further, the display1includes, on the outer edge thereof, a source driver15athat applies to the data line11the voltage corresponding to an image data displayed on a gate electrode of the vertical organic light-emitting transistor20, a current supply unit15bthat supplies the current to the current supply line12and supplies the current to a source electrode of the vertical organic light-emitting transistor20, and a gate driver15cthat outputs a control signal of a thin-film transistor21to the gate line13. Here, as shown inFIG.1, in the display1, an area A2in which the light-emitting units10are aligned corresponds to an active area, excluding the area in which the drivers (15a,15b,15c) and the like are arranged.

FIG.2is a detailed circuit diagram of the light-emitting unit10in an area A1of the display1ofFIG.1. As shown inFIG.2, the light-emitting unit10includes the vertical organic light-emitting transistor20, the thin-film transistor21that controls voltage application to the gate electrode of the vertical organic light-emitting transistor20, and a capacitor23formed between the source electrode and the gate electrode of the vertical organic light-emitting transistor20. In the description ofFIGS.1and2, a direction in which the current supply line12is wired is described as an X direction, and a direction in which the auxiliary line14is wired is described as an Y direction.

The data line11is wiring that applies the voltage output from the source driver15ato the gate electrode of the vertical organic light-emitting transistor20through the thin-film transistor21, in order to adjust the emission brightness of the vertical organic light-emitting transistor20according to an image to be displayed. In the present embodiment, the data line11is formed in the X direction, but may be formed in the Y direction.

A plurality of the current supply lines12are wired in the X direction on the outer side of the vertical organic light-emitting transistors20so as to be connected to a group consisting of a plurality of the vertical organic light-emitting transistors20aligned in the X direction. Each current supply line12supplies the current output from the current supply unit15bto the source electrode of each vertical organic light-emitting transistor20included in the vertical organic light-emitting transistor20group.

The gate line13is connected to the gate electrode of the thin-film transistor21, transmits the control signal output from the gate driver15ctoward the gate electrode of the thin-film transistor21, and switches the thin-film transistor21on/off to control the current flowing through the gate electrode of the vertical organic light-emitting transistor20and the data line11. In the present embodiment, the gate line13is formed in the Y direction, but may be formed in the X direction.

The auxiliary line14is wired in the Y direction between the light-emitting units10aligned in the X direction to connect the plurality of current supply lines12. The auxiliary line14may not be formed between all the light-emitting units10aligned in the X direction. In the present embodiment, the current supply line12is formed in the X direction and the auxiliary line14is formed in the Y direction, but the current supply line12may be formed in the Y direction and the auxiliary line14may be formed in the X direction.

The capacitor23is an element for holding the voltage between the gate electrode and the source electrode of the vertical organic light-emitting transistor20, and is arranged to maintain the displayed image for a predetermined time while the thin-film transistor21is in the off state.

Next, a structure of each element formed on a substrate is described.FIG.3Ais a top view of a schematic element configuration of the light-emitting unit10and its periphery according to the embodiment, andFIG.3Bis a view showing a state in which the current supply lines12are removed fromFIG.3A.FIG.4is a cross-sectional view taken along line A-A′ ofFIG.3A. As shown inFIGS.3B and4, the vertical organic light-emitting transistor20and the thin-film transistor21are formed in a set in an area divided by the data lines11and the gate lines13.

Further, as described above, the vertical organic light-emitting transistor20shown inFIGS.3A and3Bis shown by cutting out a part of the area, but a drain electrode layer20d, light-emitting layers (an organic semiconductor layer20aand an organic EL layer20c), a source electrode layer20s, and the like of the vertical organic light-emitting transistor20of the present embodiment are formed so as to straddle the plurality of vertical organic light-emitting transistors20as shown inFIG.4.

The substrate30is transparent to light and emits light radiated from the vertical organic light-emitting transistor20to the outside. Specific materials are described later.

In the following description, the direction in which the data line11and the current supply line12are wired are referred to as the X direction, the direction in which the gate line13is wired is referred to as the Y direction, and the direction orthogonal to these is referred to as a Z direction (third direction). In addition, in the case of expressing the direction while distinguishing the positive and negative directions, positive and negative signs are added in the expression such as “+Z direction” and “—Z direction”, and in the case of expressing the direction without distinguishing the positive and negative directions, the expression of “Z direction” is simply used.

The vertical organic light-emitting transistor20is constituted of, from the layer on the +Z side, the drain electrode layer20dcorresponding to the cathode electrode, the organic EL layer20cand the organic semiconductor layer20aforming the light-emitting layer, the source electrode layer20smade of conductive material (in the present embodiment, carbon nanotubes) formed on the surface of the surface layer31, then further on a −Z side, a gate insulating film layer20hmade of dielectric material, and further, a gate electrode layer20g.

In the vertical organic light-emitting transistor20having the above configuration, when the voltage is applied to the gate electrode layer20g, the Schottky barrier between the organic semiconductor layer20aand the source electrode layer20schanges and when a predetermined threshold is exceeded, carriers are injected and the current flows from the source electrode layer20sto the organic semiconductor layer20aand the organic EL layer20c, which causes light to be emitted.

Although the X direction is not shown inFIG.4, the source electrode layer20sis also applied to the +Z side of the current supply line12formed on the surface layer31so as to be in direct contact with the current supply line12. Then, in order to define the active light emission area in which the carrier injection is controlled by overlapping gate electrode layer20gby electrically insulating the organic semiconductor layer20aand the source electrode layer20sof the vertical organic light-emitting transistor20off the active light emission area, a bank layer24provided with an opening24ais formed in an area where the gate electrode layer20gand the source electrode layer20soverlap with each other in the Z direction. As shown inFIG.4, an area in which the opening24ais formed is preferably formed on the inner side of the area where the gate electrode layer20gand the source electrode layer20soverlap with each other, from the viewpoint of ensuring an overlap margin.

The display1of the present embodiment is configured such that the substrate30is made of material transparent to visible light, and the gate electrode layer20gand the source electrode layer20sare configured to have an optical gap and/or morphology through which the visible light can pass. With this configuration, the light emitted from the organic EL layer20cpasses through the substrate30and is emitted to the outside to display an image. In addition, the above method of emitting the light is called the “bottom emission method”.

In the thin-film transistor21, the source electrode layer21sand the drain electrode layer21dare connected via the oxide semiconductor layer21a, and a gate electrode layer21gis formed below the oxide semiconductor layer21awith an insulating film layer or a dielectric layer interposed therebetween. When the voltage is applied to the gate electrode layer21g, a channel is formed in the oxide semiconductor layer21a, and the current flows through the source electrode layer21sand the drain electrode layer21d, which are current-carrying electrode layers.

In the thin-film transistor21, the source electrode layer21sis connected to the data line11. As shown inFIG.4, some of the conductive layer component of the drain electrode layer21dof the thin-film transistor21is formed integrally with the gate electrode layer20gof the vertical organic light-emitting transistor20.

As shown inFIG.3B, the vertical organic light-emitting transistor20is formed so as to fill almost the entire area divided by the data lines11and the gate lines13in order to maximize the aperture ratio and increase the brightness. The thin-film transistor21is formed as small as possible at the corner of the divided area so as to have only a small effect on the light-emitting area of the vertical organic light-emitting transistor20.

Although the capacitor23is not shown in the drawings, inFIGS.3A to4, as shown inFIG.4, in the vertical organic light-emitting transistor20of the present embodiment, the source electrode layer20sand the gate electrode layer20gare arranged facing each other with the gate insulating film layer20hinterposed therebetween. As a result, the vertical organic light-emitting transistor20has the capacitor23as a parasitic element, and the capacitor23can also exhibit a voltage maintenance function. If the capacitance value of the capacitor23of such a parasitic element is insufficient, another capacitor may be additionally formed.

The materials used for each layer are listed below as examples.

The material adopted for the gate line13and the auxiliary line14may include aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), niobium (Nb), magnesium (Mg), silver (Ag), copper (Cu), and an alloy of combination thereof.

The material adopted for the substrate30may include a glass material and a plastic material such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyimide.

The drain electrode layer20dof the vertical organic light-emitting transistor20may be a single layer or a multilayer, and the material adopted therefor may include carbon nanotube, graphene, Al, lithium fluoride (LiF), molybdenum oxide (MoxOy), indium tin oxide (ITO), zinc oxide (ZnO), Mg, Ag, gold (Au), and alloys of other combinations.

The material adopted for the gate electrode layer20gof the vertical organic light-emitting transistor20may include ITO and indium gallium zinc oxide (IGZO), which are metal oxide materials exhibiting transparency to light and electrical conductivity. Further, in a configuration in which light is emitted from the side opposite to the gate electrode layer20g(for example, in a top emission method), a material not having transparency to light may be adopted, and the gate electrode layer20gmay adopt the material such as metal-doped or non-doped transparent conductive oxide including ZnO, indium oxide (In2O3), tin dioxide (SnO2), cadmium oxide (CdO), which are doped with metal such as Al, tin (Sn), yttrium (Y), scandium (Sc), or gallium (Ga), or a material including combination thereof, or Al, Au, Ag, platinum (Pt), cadmium (Cd), nickel (Ni), or tantalum (Ta), or a combination thereof, or further, p or n-doped silicon (Si), or gallium arsenic (GaAs).

The material adopted for the gate insulating film layer20hbetween the surface layer31and the gate electrode layer20gof the vertical organic light-emitting transistor20may include inorganic and organic compounds such as silicon oxide (SiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), yttrium oxide (Y2O3), lead titanate (PbTiO), aluminum titanate (AlTiO), glass and parylene polymers, polystyrene, polyimide, polyvinylphenol, polymethylmethacrylate, and fluoropolymer.

Here, by appropriately selecting organic semiconductors having compatible energy levels, the vertical organic light-emitting transistor20can preferably utilize a hole injection layer, a hole transport layer, an organic EL layer, an electron transport layer, an electron injection layer, and the like which are standardly used in a display provided with an organic light-emitting diode. Then, the color of the light emitted to the outside is adjusted so as to emit light of colors such as red, green, and blue by selecting the material constituting the above-described organic EL layer20c. Further, as described later as another embodiment, the vertical organic light-emitting transistor20may be configured to emit white light, and may be configured to select and emit light of a desired color by the color filter layer using the same vertical organic light-emitting transistor20. Additionally, the vertical organic light-emitting transistor20may be configured to emit light of short wavelength such as blue light, and in some pixels may be configured to excite an optical down-conversion layer to emit light of a longer wavelength of desired color such as red and green. The down-conversion layer can include phosphors and semiconductor quantum dots.

The surface layer31is a layer formed on the gate insulating film layer20hfor various purposes including fixing the source electrode layer20s. The material for forming the surface layer31can be formed by applying a composition containing a binder resin formed of a silane coupling material, an acrylic resin, or the like.

The material of the bank layer24may include inorganic insulating materials such as SiO, Si3N4, Al2O3, and aluminum nitride (AlN), and organic insulation materials such as polyimide resin, siloxane resin, acrylic resin, and novolac resin.

In the present embodiment, the thin-film transistor21is a thin-film transistor with the semiconducting channel layer made of an oxide semiconductor, but may be a thin-film transistor made of an amorphous silicon, a low temperature polysilicon (LTPS), or a high temperature polysilicon (HTPS). Further, the thin-film transistor may be either p-type or n-type. Further, as a specific configuration, any configuration such as a staggerd type, an inverted staggerd type, a coplanar type, and an inverted coplanar type can be adopted.

As the vertical organic light-emitting transistor20, the vertical organic light-emitting transistors20described in Patent Documents 1 and 2 can also be adopted.

Next, the manufacturing process of each layer is briefly described.FIGS.5A to5Gare schematic views of the periphery of the vertical organic light-emitting transistor20of the display1in the middle of the manufacturing process when viewed from the +Z side. Hereinafter, each process is described with reference to the drawings.

In addition, the description is made referring to the drawing in which three vertical organic light-emitting transistors20are aligned in the Y direction so that the positional relationship with the adjacent vertical organic light-emitting transistors20and the structure between the vertical organic light-emitting transistors20, that is, the structure on the outer side of the vertical organic light-emitting transistors20can be understood.

The outside of the illustrated area does not have to be repeated in the same pattern. For example, as shown inFIG.5Dand the like, the thin-film transistors21are formed on the (+X, −Y) side, but in the entire display1, on the −X side of the central portion in the X direction, the thin-film transistor may be formed in any pattern such as on the (−X, +Y) side. Further, in the display1, the size of the pixels may be optionally changed for each pixel displaying a different color.

After step S1, as shown inFIG.5B, the gate electrode layer21gof the thin-film transistor21and the gate line13connected to the gate electrode layer21gare formed on the substrate30(step S2).

After step S2, an insulating film (not shown) is formed over the entire surface, and as shown inFIG.5C, the oxide semiconductor layer21ais formed on the +Z side of the gate electrode layer21gof the thin-film transistor21(step S3).

The term “formed over the entire surface” here means that the layer is formed over the entire image forming area in which the vertical organic light-emitting transistor20is formed, and does not mean that the layer is formed over the entire outer edge portion where the driver is arranged. This also applies to the following description.

After step S3, as shown inFIG.5D, the drain electrode layer21dand the data line11are formed on the oxide semiconductor layer21aof the thin-film transistor21to be separated in the Y direction (step S4). The data line11constitutes the source electrode layer21sof the thin-film transistor21at a portion overlapping with the oxide semiconductor layer21ain the Z direction. In the present embodiment, in step S4, the configuration has a shape as shown inFIG.5Ebecause a two-step forming process by halftone exposure is performed, but step S4may not be the forming process by halftone exposure.

After step S4, a passivation film is formed over the entire surface, and then the surface layer31is formed over the entire surface (step S5). The passivation film can serve as the gate insulating film layer20h, or a separate gate insulating film layer20hcan be formed. The passivation film and the surface layer31are not shown for convenience of explanation.

After step S5, as shown inFIG.5F, the current supply line12is formed in the X direction, and the auxiliary line14is formed so as to connect the current supply line12to other current supply lines in the Y direction (step S6). In the present embodiment, because the current supply line12and the auxiliary line14are formed in different layers, contact holes14cconnecting the layers are also formed. The contact holes14cmay be formed at any location and in an appropriate shape and number.

After step S6, on the main surface of the surface layer31formed in step S4and the current supply line12formed in step S5, the source electrode layer20sis integrally formed over the entire surface layer31across the plurality of vertical organic light-emitting transistors aligned in the X direction (step S7). Similarly to the surface layer31, the source electrode layer20sis not shown for convenience of explanation.

After step S7, as shown inFIG.5G, the bank layer24, which is a resin layer, is formed (step S8). When viewed from the Z direction, the bank layer24is formed with the opening24aformed in the area where the gate electrode layer20gand the source electrode layer20soverlap with each other. The bank layer24may be formed of the inorganic insulating material as described above.

After step S8, the organic semiconductor layer20aand the organic EL layer20c, which are to be the light-emitting layers, and the drain electrode layer20dare formed over the entire surface to form the configurations shown inFIGS.3A to4.

In the manufacturing process as described above, the gate electrode layer20gof the vertical organic light-emitting transistor20and the drain electrode layer21dof the thin-film transistor21are formed at the same time. Therefore, the display can be manufactured with fewer processes than in the conventional manufacturing process.

In the present embodiment, all of the drain electrode layer20d, the organic semiconductor layer20a, the organic EL layer20c, and the source electrode layer20sof the vertical organic light-emitting transistor20straddle the plurality of vertical organic light-emitting transistors20. However, any of the above may be formed for each vertical organic light-emitting transistor20.

Other Embodiments

Hereinafter, other embodiments are described.

<1>FIGS.6and7are cross-sectional views of schematic element configurations of the light-emitting units10and their peripheries of another embodiment when the configurations are cut in the YZ plane. As shown inFIG.6, the current supply line12may be formed in a layer on the −Z side of the surface layer31. Further, as shown inFIG.7, the auxiliary line14may be formed in a layer on the −Z side of the current supply line12.

In the case of configuring the light-emitting unit10ofFIG.6, for example, the current supply line12is formed by halftone exposure in step S4. Further, in the case of configuring the light-emitting unit10ofFIG.7, for example, the auxiliary line14is formed at the same time as the gate electrode layer21gof the thin-film transistor21is formed in step S2.

The light-emitting unit10having the configuration as shown inFIG.6can have the current supply line12formed at the same time when each electrode layer of the thin-film transistor21is formed, and in that case, the process of forming contact holes12cis required. However, the process of forming these contact holes12cis a process that is originally performed for the connection between the electrode layers in the peripheral portion of the display even in the conventional manufacturing process of the light-emitting diode display, and does not become a factor that increases the number of processes. Therefore, the number of processes is reduced as compared with the conventional manufacturing method.

The light-emitting unit10having the configuration as shown inFIG.7can have the auxiliary line14formed at the same time when each electrode layer of the thin-film transistor21is formed, and in that case, the process of forming the contact holes14care required in addition to the configuration shown inFIG.6. However, the number of processes of forming the contact holes14cis less than the number of processes of newly creating the current supply line12in the upper layer, and the auxiliary line14can be formed while the number of processes is suppressed, and further, the process of forming the contact holes14ccan be alternatively utilized as the process of connecting between the wirings. Therefore, the number of processes is reduced as compared with the conventional manufacturing method. Therefore, both of the configurations shown inFIGS.6and7can be manufactured at a lower cost as compared with the manufacturing processes described with reference toFIGS.5A to5G.

<2>FIG.8is a cross-sectional view a schematic element configuration of the light-emitting unit10provided with a color filter layer80and its periphery of another embodiment when the configuration is cut along the YZ plane.FIG.9Ais an enlarged view of the periphery of the thin-film transistor21ofFIG.8, andFIG.9Bis a view showing a state before the oxide semiconductor layer21aof the thin-film transistor21ofFIG.9Ais formed. As shown inFIGS.8and9A, the color filter layer80may be formed on the −Z side of the gate electrode layer20gof the vertical organic light-emitting transistor20. The process of forming the color filter layer80is performed before the oxide semiconductor layer21aof the thin-film transistor21is formed in step S3.

At this time, an opening80ais created in the color filter layer80around the position where the thin-film transistor21is formed and the color filter layer80is not formed in the opening, and as shown inFIG.9B, the opening80aof the color filter layer80is formed in a forward tapered shape that gradually narrows toward the substrate30, and as a result, the thin-film transistor21can be formed and operated. The color filter layer80may be formed by such as a method of exposing a photosensitive color filter material through a photomask and developing the same to form a color filter with a predetermined pattern, a method of forming the color filter layer80once on the entire surface and thereafter, performing an etching process, or a method of forming the color filter while the area in which the thin-film transistor21is formed is treated with masking processing.

FIGS.10A and10Bare schematic views of a periphery of one vertical organic light-emitting transistor of the display in the middle of the manufacturing process when viewed from the +Z side, in the case of forming the color filter layer80.FIG.10Ashows an example in the case where the color filter layer80is formed over the entire surface after step S2and then the opening80ais formed, andFIG.10Bshows an example in the case where the color filter layer80is individually formed for each light-emitting unit10.

The configuration shown inFIG.8is an example of the case where the bottom emission method is adopted in which the light is emitted from the substrate30side through the color filter layer80. Among the light emitted from the vertical organic light-emitting transistor20, the light in a part of the wavelength band is filtered by the color filter layer80, and the light in the remaining wavelength band is emitted from the substrate30.

In the case of this configuration, the gate electrode layer20gis preferably formed of a material exhibiting transparency to light so that the light emitted from the organic EL layer20cof the vertical organic light-emitting transistor20reaches the substrate30, and for example, the metal oxide materials such as ITO and IGZO as described above may be adopted.

<3> Although each of the above-described embodiments has been described on the premise of the bottom emission method, the “top emission method” that emits light from the side opposite to the substrate30may be adopted. In this case, in the vertical organic light-emitting transistor20, the drain electrode layer20dis formed of a material exhibiting transparency to light so that the light emitted from the organic EL layer20cis taken out.

<4> The configurations, materials, and manufacturing processes included in the display1described above in each embodiment are merely examples, and the present invention is not limited to the configurations described above and the processes shown.

REFERENCE SIGNS LIST