Vertical power MOSFET with planar channel and vertical field plate

A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. Alternating N and P-type columns are formed over the drift layer with a higher dopant concentration. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and next to the sidewalls as a vertical field plate. A source electrode contacts the P-well and source region. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls. Current between the source and drain flows laterally and then vertically through the various N layers. On resistance is reduced and the breakdown voltage is increased.

FIELD OF INVENTION

The present invention relates to power MOSFETs and, in particular, to a vertical, super junction MOSFET including a planar DMOS portion and a vertical conduction portion.

BACKGROUND

Vertical MOSFETs are popular as high voltage, high power transistors due to the ability to provide a thick, low dopant concentration drift layer to achieve a high breakdown voltage in the off state. Typically, the MOSFET includes a highly doped N-type substrate, a thick low dopant concentration N-type drift layer, a P-type body layer abutting the drift layer, an N-type source at the top of the body layer, and a gate separated from the body region by a thin gate oxide. It is common to provide a vertical trenched gate. A source electrode is formed on the top surface, and a drain electrode is formed on the bottom surface. When the gate is sufficiently positive with respect to the source, the channel region of the P-type body between the N-type source and the N-type drift layer inverts to create a vertical conductive path between the source and drain.

In the device's off-state, when the gate is shorted to the source or negative, the drift layer depletes and large breakdown voltages, such as exceeding 600 volts, can be sustained between the source and drain. However, due to the required low doping of the thick drift layer, the on-resistance suffers. Increasing the doping of the drift layer reduces the on-resistance but lowers the breakdown voltage.

It is known to form alternating vertical columns of P and N-type silicon, extending to the substrate, instead of a single N-type drift layer, where the charges in the columns are balanced and where the P and N-type columns completely deplete at a high voltage when the MOSFET is off. This is referred to as a super junction. In such a configuration, the dopant concentration of the N-type column can be higher than that of a conventional N-type drift layer. As a result, on-resistance can be reduced for the same breakdown voltage. A super junction MOSFET can be formed by a multiple epitaxial growth and implantation process. Forming thick and alternating P and N-type columns extending to the substrate requires many cycles of epitaxially growing a portion of the column thickness, then masking and implanting the P and N-type dopants, then growing more of the column thickness and repeating the masking and implantation process. The number of implantation steps may exceed twenty, depending on the thickness. Between each implant cycle, the dopants undesirably laterally spread due to the high process temperatures. This greatly increases the required cell pitch in an array of cells, making the die larger. As a result, the MOSFET is not optimally formed and the process is very time-consuming.

Alternatively, a super junction can be formed by etching deep trenches in N-type silicon that are refilled by a P-type epitaxial layer. The trenches must be deep so that there is a sufficiently long vertical drift layer to support a depletion region for a high breakdown voltage. Forming deep trenches is time-consuming and therefore expensive.

Such power MOSFETs are formed to have a large number of identical parallel cells. Any variation between the devices can cause non-uniform currents and temperatures to result across the MOSFET, reducing its efficiency and breakdown voltage.

What is needed is a power MOSFET that does not suffer from the above-described drawbacks and limitations of the prior art.

SUMMARY

In one embodiment, a MOSFET is formed having a planar channel region, for a lateral current flow, and a vertical conduction path for a vertical current flow.

In one embodiment, a P-well (a body region) is formed in an N-type layer, where there is a trench formed in the N-type layer, deeper than the P-well, resulting in vertical sidewalls of the N-type layer. The N-type layer is more highly doped than an N-type drift layer in the MOSFET. The MOSFET includes a shielded vertical field plate formed by a conductive material, such doped polysilicon, filling the trench and insulated from the sidewalls by a dielectric material, such as oxide. A P-shield layer is formed at the bottom of the trench and abuts the bottom portion of the sidewall. The P-shield layer also abuts the top of a P-column. An N-column is below the channel region and laterally abuts the P-column. The N and P columns are relatively highly doped for a low on-resistance. The trench field plate is deeper than the P-well to provide an effective electric field reduction in the N-layer. The field plate and the P-shield help to deplete the N-layer laterally when the MOSFET is off, allowing the N-layer to be relatively highly doped for a low on-resistance. The combined effect of the trench field plate, the P-shield, the N-type layer, a reduced thickness N-type drift layer, and relatively highly doped P and N columns provides an increased breakdown voltage, lower on-resistance, and a lower cost per die. The conducting field plate electrode can be connected to the gate electrode or the source electrode to provide lower gate-drain capacitance for faster switching.

The lower on-resistance per unit area allows more dies to be formed per wafer.

In one preferred embodiment the field plate trench depth, its insulated material thickness, the N-layer doping and thickness and the P-shield doping and depth are chosen such that the N-layer is fully depleted at the breakdown voltage. Furthermore, the P and N column doping, depth and width are such that the P and N columns are fully depleted at the breakdown voltage.

In one embodiment, a power MOSFET includes a highly doped N-type substrate with a low dopant concentration first N-type layer (the drift layer), approximately 30 microns thick, epitaxially grown over the substrate. This first N-type layer is much thinner than the prior art drift layers since it is not required to sustain the entire source-drain voltage in the off state.

The first N-type layer is masked and implanted with dopants to form alternating P and N-type regions, approximately 4 microns thick, which are referred to as columns. The N-type dopant concentration in the N-type columns is much higher than the dopant concentration in the N-type drift layer. Only one implantation for each type dopant needs to be used in one embodiment to form the columns, since the column layer is relatively thin compared to the column layer in the prior art. Therefore, there is less lateral spreading of the dopants compared to the prior art, and the columns are optimized.

Over the column layer is formed a second N-type layer, such as 8 microns thick, having a dopant concentration higher than that of the first N-type layer.

Within the second N-type layer is formed a P-well and within the P-well is formed an N-type source region at the surface. The top surface of the P-well between the source region and the top of the second N-type layer forms a lateral channel along the top surface of the device.

A trench is etched in the second N-type layer between the P-wells in each cell and is deeper than the P-wells. A thin gate dielectric is then formed over the top lateral channel and along the sidewall of the trench. A polysilicon gate is then formed over the top channel and along the vertical sidewall of the trench to a depth deeper than the P-well. The dielectric layers separating the gate from the channel and the sidewall may have the same thickness or different thicknesses for different advantages. The trench field plate results in a lower electric field and a higher breakdown voltage, which allows the increase of the doping of the second N-type layer thus lowering the on-resistance.

A metal source electrode contacts the P-well and the source regions, and a metal drain electrode contacts the bottom surface of the substrate.

In another embodiment the P-columns can be formed during the same step of forming P-shield by using single or multiple high energy implantations.

In one example, a load is coupled between the source electrode and ground, and a positive voltage is applied to the drain. When the gate is sufficiently biased positive with respect to the source electrode, the top lateral channel between the source region and the second N-type layer inverts, and electrons accumulate along the vertical sidewall of the trench in the second N-type layer. This lateral and vertical accumulation of electrons forms a low resistance path between the source and the N-type column below the channel. The N-type column and first N-type layer then complete the vertical conductive path to the drain electrode.

Since there is no thick, low-dopant-concentration drift region between the channel and the drain electrode, the on-resistance per unit area (specific on-resistance Ron*Area) is lower than that of the conventional vertical power MOSFET. The on-resistance is lower due, in part, to the use of the higher-dopant-concentration N-column and second N-type layer, as well as the higher doping of the second N-type layer, where the higher doping of the second N-type layer is enabled by the trench field plate effect, the P-shield, and the accumulation of electrons along the vertical sidewall of the second N-type layer when the gate is positively biased. In one embodiment the specific on-resistance achieved is 4.5 Ohms-mm2, which is about half that of a conventional power MOSFET.

Due to the much lower on-resistance per unit area, the die size may be smaller than prior art die sizes, resulting in double the number of dies per wafer for the same on-resistance per die.

In the MOSFET's off state, and with a source-drain voltage slightly lower than the breakdown voltage, the first N-type layer, the columns, and the second N-type layer completely deplete. The breakdown voltage may be the same as the prior art vertical MOSFETs having the same thickness, but the on-resistance is less. Conversely, the breakdown voltage may be increased above the prior art breakdown voltage by forming thicker layers, while the on-resistance may be the same as the prior art. Further, the processing complexity for the resulting vertical MOSFET is much less than the processing complexity for the prior art vertical MOSFETs having a super junction due to the thinner column layer and the shallower trench.

The MOSFET structure also lowers the recovery time after the PN diode in the MOSFET is biased on. If the MOSFET is used with an alternating voltage, the diode will conduct when the drain is more negative than the source. When the polarity reverses and the diode is reverse biased, there is a stored charge that must be removed prior to the MOSFET being fully turned on after the gate is biased to an on state. Since there is a higher dopant level in the second N-type layer and the N-column, this stored charge is removed faster, enabling a faster switching time.

In a preferred embodiment, a P-type shield layer is formed above the P-columns under the trench so as to abut the sidewall of the second N-type layer. This P-type shield layer helps to laterally deplete the second N-type layer to increase the breakdown voltage.

Gate configurations are described that also help to laterally deplete the second N-type layer to increase the breakdown voltage.

Many variations of the above described cell using a top lateral channel, a vertical field plate facing an enhanced vertical “channel” portion, and a super junction are described. Inventive techniques for forming the vertical MOSFETs are also described.

An insulated gate bipolar transistor (IGBT) may instead be formed by using a P-type substrate.

Elements that are the same or equivalent in the various figures are labeled with the same numeral.

DETAILED DESCRIPTION

FIG. 1is a cross-sectional view of a single vertical MOSFET cell10in a large array of identical contiguous MOSFET cells in accordance with one embodiment of the invention. The width of the cell shown is about 8-11 microns. The MOSFET cell10may have a breakdown voltage exceeding 600 volts, and the number of cells10in an array of identical cells determines the current handling ability, such as 20 Amps. The array of cells may be in strips, squares, hexagons, or other known shapes.

During normal operation, a positive voltage is applied to the bottom drain electrode12and a load is connected between ground and the top source electrode14. When a positive voltage is applied to the conductive gate16that is greater than the threshold voltage, the top surface of the P-well18is inverted and electrons accumulate along the vertical sidewalls of the N− layer20. The gate extends along the sidewalls below the P-well18and creates a field plate to lower an electric field in the N− layer20. The N++ source region22, the P-well18, and the N− layer20top surface form a lateral DMOS transistor portion of the MOSFET10. Therefore, in the on-state, there is a conductive N-type channel between the source electrode14and the drain electrode12via the N++ source region22, the inverted channel of the P-well18, the sidewalls of the N− layer20, the N-column24under the channel, the N−− layer26(the drift layer), and the N++ substrate28.

The combination of the lateral DMOS transistor portion, the higher doping of the N layer20(allowed by the trench field plate effect and the vertical gate portion accumulating electrons along the sidewall of the N− layer20), the alternating highly doped N and P-type columns24and30, and the N−− layer26reduce the on-resistance compared to the prior art, as later described. This structure also increases the breakdown voltage compared to the prior art and speeds up the switching time if the MOSFETs internal PN diode becomes forward biased, as later described.

In the cross-sectional views, the depth of the P-well18is exaggerated for ease of illustration, and the polysilicon gate16along the sidewall of the N− layer20extends below the P-well18. For example, the polysilicon gate16along the sidewall of the N− layer20(and any other vertical field plate along the sidewall) may extend 1-4 microns below the P-well18.FIG. 3illustrates more accurate relative dimensions of the gate16relative to the P-well18sinceFIG. 3is from a simulation.

FIGS. 2A-2Rillustrate various steps used to fabricate the MOSFET10ofFIG. 1.

FIG. 2Aillustrates the N−− layer26being epitaxially grown over an N++ silicon substrate28while being doped in-situ during growth, or the N−− layer26is periodically implanted with N-type dopants at a dosage of about 1.5E12 cm2. The substrate28may have a dopant concentration of about 5E19 cm3. The final dopant density in the N−− layer26is about 3.5E14 cm3for a device with about a 600V breakdown voltage. The N−− layer26may be 30 microns thick.

FIG. 2Billustrates a thin thermal oxide layer34grown over the N−− layer26, followed by a blanket phosphorus35implant to form an N-column layer36. The implant dosage may be about 1-2E12 cm2.

FIG. 2Cillustrates a patterned photoresist layer38formed over the intended location of the N-columns24. Boron40is then blanket implanted at a dosage of about 1E13 cm2to form P-columns30.

InFIG. 2D, the photoresist and oxide are stripped and an N− layer20is epitaxially grown to have a dopant density of about 2.3E15 cm3, which is higher than the dopant density in the N−− layer26. The N− layer20is about 8 microns thick. In another embodiment, the dopant density in the N− layer20is the same as that in the N−− layer26.

InFIG. 2E, a thermal oxide layer42is grown over the N− layer20. The dopants in the N and P-columns24and30are driven in and diffuse to form a column layer about 4-5 microns thick, with an N-type dopant concentration in the N-columns24of about 2E15 cm3, and a P-type dopant concentration in the P-columns30of about 1E16 cm3. The dopant density in the N-columns24may be greater than that of the N− layer20or less.

InFIG. 2F, a polysilicon layer about 1000 Angstroms thick is formed, followed by a nitride layer46about 2000 Angstroms thick, followed by a thick oxide layer48about 10,000 Angstroms thick.

InFIG. 2G, a layer of photoresist50is patterned and the exposed portions of the layers42,44,46, and48are etched away.

InFIG. 2H, the photoresist is stripped and a dry etch is performed on the exposed silicon to form trenches52in the N-layer20. The trench etch leaves about 3-4 microns of the N− layer20below the trench52. Next, boron54is implanted in the trenches52at a dosage of about 4E12 cm2to form P-shields56.

InFIG. 2I, the thick oxide layer is stripped by dry etching, and a thermal sacrificial oxide layer58about 1000 Angstroms thick is grown over the P-shield56and over the sidewalls of the N− layer20.

InFIG. 2J, the sacrificial oxide layer is stripped, and an oxide layer60about 6000 Angstroms thick is formed, using a LOCOS process, over the P-shield56and over the sidewalls of the N− layer20.

InFIG. 2L, a thin gate oxide layer, having a thickness of about 900 Angstroms, is grown over the N− layer20. A conductive polysilicon layer64is then deposited and patterned

InFIG. 2M, a photoresist layer66is patterned to expose a center portion of the polysilicon layer64, followed by a dry etch to form the gate16.

InFIG. 2N, the photoresist layer is stripped, and boron68is implanted into the N-layer20, and driven in to form the P-well18, having a depth of about 2-3 microns, self-aligned with the gate16.

InFIG. 2O, arsenic or phosphorus70is implanted at a dosage of about 5E15 cm2and driven in to form an N++ source region22about 0.2-0.5 microns deep, self-aligned with the gate16.

InFIG. 2P, an insulating layer72is deposited over and around the gate16consisting of a liner oxide layer, having a thickness of about 800 Angstroms, followed by a BPSG layer, having a thickness of about 10,000 Angstroms. The center portion of the insulating layer72is then masked with photoresist and etched to expose the N++ source region22. The photoresist is then stripped.

InFIG. 2Q, the exposed portion of the N++ source region22is etched through to expose the P-well18. Boron74is then implanted at a dosage of about 2E15 cm2and driven in to form a P+ contact region76in the P-well18. The lateral width of the P+ contact region76is about 1 micron. If the P-well18extends to the edge of the die, the P+ contact region76needs only to be located at the edge of the die.

InFIG. 2R, the structure is metallized, such as by sputtering, to form a top source electrode14, contacting the P+ contact region76and the sides of the N++ source region22to electrically short the regions together. The source electrode14may be formed by sputtering AlCu or AlSiCu and may be about 4 microns thick. A bottom drain electrode12is formed by sputtering layers of Ti, Ni, and Ag having respective thicknesses of 1000, 2000, and 10,000 Angstroms. The structure is then passivated with a passivation layer, and the passivation layer is patterned/etched to expose the electrodes for contact with leads of a package. For example, a wire bond may bond the source electrode14to one lead of the package, and the drain electrode12may be directly bonded to a heat sink plate electrode of the package.

FIG. 3illustrates equi-potential contours in a depletion region between the substrate28top surface and P-well18of the device in an off state and with a voltage slightly less than the breakdown voltage, illustrating a substantially uniform distribution of the voltage. This uniform distribution of the voltage maximizes the breakdown voltage. Note that, with a maximum allowable voltage in the off state, the entire area below the P-well18and above the substrate28is depleted.

The P-shield56increases the breakdown voltage by effectively increasing the vertical size of the P-column30without having to grow an additional epitaxial layer. When the gate is grounded or negative, the P-shield56, in addition to the vertical field plate extension of the gate16next to the N− layer20sidewall, helps to deplete the N− layer20laterally to achieve the uniform distribution of the voltage shown inFIG. 3. This lateral depletion allows a higher doping of the N− layer20for decreasing on-resistance.

Referring back toFIG. 1, the N−− layer26is thinner than the prior art drift layer since it does not extend all the way to the channel region. Forming adjacent P-columns30and N-columns24results in a super junction, where the columns completely deplete and the charges in the P and N areas are balanced. In the on state (gate positively biased), the current flows from the source electrode14, through the source regions22, through the lateral channel, then vertically through the N− layer20(including through an electron accumulation layer along its sidewalls), then vertically through the underlying N-column24, N−− layer26, and substrate28to the drain electrode12.

Since the N-column24has a much higher dopant concentration than the N−− layer26, it is much more conductive than the N−− layer26, which reduces the on-resistance. Further, the N− layer20is fairly heavily doped and has an enhanced electron population along its sidewall due to the proximity to the positively biased gate16, making the vertical path between the lateral channel and the N-column24very conductive. The specific on-resistance (Ron*Area) is thus low, and the overall on-resistance of the cell array is less than 1 Ohm. In one embodiment the specific on-resistance achieved is 4.5 Ohms-mm2, which is about half that of a conventional power MOSFET. This enables smaller dies and double the yield per wafer.

Since there is no vertical channel that is inverted by a trenched gate, the trench ofFIG. 1can be fairly shallow (e.g., 4-10 microns), so is easier to form. The MOSFET10ofFIG. 1can be formed using standard processing equipment and, since there is no deep trench formed, the processing is fairly simple, reducing the cost per wafer.

In addition to the MOSFET10having an increased breakdown voltage and lower on-resistance, it has a faster recovery time after the MOSFET PN diode was biased on. The delay in gate-controlled switching after the PN diode has been biased on, followed by a reversal of the source/drain voltage, is due to stored charge when the diode is reversed biased. That stored charge must be removed for the diode to turn off and the MOSFET to turn on. The removal of charge in the MOSFET10is accelerated by the fairly highly doped N-column24and N− layer20as well as the effect of the positive gate on the sidewalls of the N− layer20drawing electrons to the sidewalls.

There are many variations of the basic MOSFET10ofFIG. 1that retain the various benefits of lower on-resistance and higher breakdown voltage.FIGS. 4-15Eillustrate some of these variations.

FIG. 4illustrates a MOSFET with a shallower column layer so the P-shield56does not contact the underlying P-column30. The P-shield56still has the effect of laterally depleting the N-layer20so the N− layer20can be relatively highly doped to reduce on-resistance.

FIG. 5illustrates a MOSFET with N-columns80deeper than P-columns82. This serves to spread the current to avoid hot spots and further reduce on-resistance since the N-column80is more highly doped than the N−− layer26.

FIG. 6illustrates a MOSFET where the P-well84extends to the trench sidewall. The overlying gate16and sidewall portion of the gate16inverts the top and side surfaces of the P-well84when the gate16is positively biased to turn on the MOSFET. This structure reduces the likelihood of the top thin gate oxide breaking down with a high drain-gate voltage since the thin gate oxide only overlies the P-well84and the P-well84is at the source voltage.

FIGS. 7A and 7Billustrate MOSFETs without N and P columns. In these embodiments, the benefit of the super junction ofFIG. 1is not utilized so the N−− layer26is thicker. Hence, on-resistance is not as good as with the MOSFET ofFIG. 1. However, the gate structure combined with the N− layer20structure still results in an on-resistance that is reduced from the prior art.

FIGS. 8A and 8Billustrate MOSFETs with multiple column layers86and88. This allows the use of thinner column layers to achieve more uniform dopant concentrations in the columns. With a thick column layer, the implanted dopants need to be driven in a longer time, which also diffused the dopants laterally. By using multiple thinner column layers, less drive in time is required so the dopants do not laterally diffuse as much. This allows for a smaller cell pitch and a smaller die size. The multiple column layers deplete when the MOSFET is off, assuming a sufficiently high source-drain voltage, and the P and N-columns allow the dopant concentration in the columns to be fairly high due to the depletion characteristics of the super junction.

FIG. 9illustrates a MOSFET with a thicker trench oxide90at the upper edges of the N− layer20. Since there is usually electric field crowding at low radius corners, the thicker oxide helps prevent breakdown of the oxide layer between the N− layer20and the gate16. The different oxide thicknesses are achieved by a masked etch.

FIG. 10Aillustrates a MOSFET with a more uniform thickness gate polysilicon layer92, compared with the gate polysilicon layer inFIG. 1. This may reduce processing time due to the thinner polysilicon layer.

FIG. 10Billustrates a MOSFET with a split polysilicon layer94and96, where the gap overlies the N− layer20. The gate portion above the P-well18channel inverts the channel. The polysilicon layer96may be connected to the source or be floating and acts as a field plate for spreading the electric field distribution to achieve a more uniform electric field profile. The polysilicon layer96is inherently at a lower voltage than the gate when the MOSFET is on. This results in less voltage differential between the polysilicon layer96and the N− layer20and the P-shield56. Since the gate portion only inverts the channel, there is less of a conductivity modulation in the N− layer20. The gate to drain capacitance (the Miller capacitance) is reduced substantially, reducing the switching losses. Therefore, the conduction of the MOSFET vs. gate voltage is slightly more linear than that of the MOSFET ofFIG. 1, with a slight increase in on-resistance, and switching power losses are reduced.

FIG. 10Cillustrates a MOSFET with a split polysilicon layer98and100where the gap overlies the P-shield56. Thus the gate over the P-well18and sidewall of the N− layer20inverts the channel and accumulates electrons along the sidewall of the N− layer20for a lower on-resistance. The polysilicon layer100is connected to the source or floating.

FIG. 10Dillustrates a MOSFET with a split polysilicon layer102and104where there is no polysilicon facing the edge of the N− layer20. Therefore, there is less likelihood of oxide breakdown between the edge of the N-layer20and the polysilicon due to field crowding at the edge.

FIG. 11Aillustrates a MOSFET where a uniform thin gate oxide106overlies the lateral channel, the trench sidewall, and the P-shield56. Thus, the effect of the gate16is most pronounced with this embodiment in reducing on-resistance; however, the likelihood of gate oxide breakdown is increased.

FIGS. 11B and 11Cillustrate MOSFETs with a thicker oxide108over the P-shield56to reduce the likelihood of oxide breakdown over the P-shield56.

FIG. 11Dillustrates a MOSFET with a variable thickness oxide110next to the trench to reduce the likelihood of oxide breakdown due to field crowding.

In the previous embodiments, a wide N-column was vertically positioned under the P-well18.FIGS. 12A and 12Billustrate MOSFETs with a narrow P-column112below the P-well18and narrow N-columns114next to the center P-column112. The narrower columns improve the lateral depletion of the columns when the MOSFET is off, so the columns can be more highly doped to reduce on-resistance. Since the current path is primarily along the edges of the N− layer20, and there are N-columns114under those edges, the positioning the narrow P-column122under the middle of the P-well18does not adversely affect on-resistance.

InFIG. 12B, the center P-column116extends to the P-well18. This helps laterally deplete the N− layer20in the off-state, allowing the N− layer20to be more highly doped to improve on-resistance.

FIGS. 13A and 13Billustrate MOSFETs similar to the MOSFET ofFIG. 10B(with the split polysilicon layer) but where the as inFIG. 10B, but where the middle P-column118extending to the P-well18and a conductive polysilicon portion120, connected to the source electrode14, protruding into the P-column118and insulated from the P-column118. This helps deplete the P-column118in the off-state.

FIGS. 14A-14Cillustrate MOSFETs with a conformal N-layer124around the P-column118, and the P-column118extending to the P-well18. The N-layer24has a dopant concentration about equal to the dopant concentration in the P-column118. The N− layer124reduces carrier injection into the P-column118when the PN diode is forward biased to enable faster recovery when the source and drain voltage change polarity. This enables a faster switching time after the polarity has reversed. The N-layer124also reduces current spreading resistance to lower on-resistance.

FIGS. 14B and 14Cadd another N− layer126around the P-well18that is more highly doped than the N− layer20to reduce on-resistance. The N− layer126helps spread the current along the entire width of the P-well18, and the N-layer124vertically conducts this current, along with the N-columns24, to the N−− layer26.

FIGS. 15A-15Eillustrates various MOSFET embodiments converted to IGBTs (insulated gate bipolar transistor) by using a P+ type substrate130. A thin N-type buffer layer132is added. The buffer layer132is used to control hole injection from the P+ substrate130and the breakdown characteristics of the IGBT. The drain electrode is now the collector electrode134of a PNP transistor, and the source electrode is now an emitter electrode of an NPN transistor. Thus, a vertical NPN transistor and PNP transistor are formed, which block current when the gate bias is low. When there is a sufficiently positive gate bias, an initial current flows between the source and drain, which injects sufficient carriers to forward bias the NPN and PNP transistors to create the IGBT action. This results in lower on-resistance than a vertical MOSFET. The maximum switching frequency is lowered however. The general operation of IGBTs is well-known.

FIG. 15Billustrates an N-type buffer layer with differently doped N-type regions136and138. The doping concentrations of regions136and138are about 1E17 cm3and 2E17 cm3, respectively. A higher doping concentration reduces the breakdown voltage from the collector to the emitter, but increases the device turn-off switching speed. In addition, a different doping level of regions136and138can improve the trade-off between the breakdown voltage and the forward voltage of the device.

FIG. 15Cillustrates that the collector electrode134is connected directly to the P+ region140of a substrate and N+ regions142of the substrate. The regions142allow the IGBT to be a PN diode when the collector electrode134is sufficiently negative with respect to the source (emitter) electrode. This integrates a free-wheeling diode into an IGBT, which is useful for certain applications where the voltages change polarity.

FIG. 15Dadds an N-buffer layer144over the P+ region140to adjust the hole injection efficiency from the P+ region140(collector).

FIG. 15Ecombines many of the previously described features into a single IGBT.

FIG. 16is a top down view of one type of cellular array using any of the MOSFET cells or IGBT cells described herein, where the cells are arranged as stripes. Only the gate16, source region22, and P+ contact region76are shown. The P+ contact region76may be only at one end of each strip.

FIG. 17is a top down view of another type of cellular array using any of the MOSFET cells or IGBT cells described herein, where the cells are arranged as squares. Only the gate16, source region22, and P+ contact region76are shown. Hexagons or other shapes may also be used.

Any of the disclosed features can be combined in any combination in a MOSFET or IGBT to achieve the particular benefits of that feature for a particular application.