Thin film transistor array panel and method of manufacturing the same

A thin film transistor (TFT) array panel and method of manufacturing the same are provided. The method includes forming a semiconductor layer and an ohmic contact layer over a gate line, forming a conductive layer on the ohmic contact layer, forming a first photosensitive layer pattern on the conductive layer, etching the conductive layer using the first photosensitive layer pattern as an etching mask, etching the ohmic contact layer and the semiconductor layer by a fluorine-containing gas, a chloride-containing gas, and an oxygen (O2) gas using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern to a predetermined thickness to form a second photosensitive layer pattern, and etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2006-0008878 filed in the Korean Intellectual Property Office on Jan. 27, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND

(a) Field of the Invention

The present invention relates to a thin film transistor (TFT) array panel and a method of manufacturing the same.

(b) Description of the Related Art

A liquid crystal display (LCD) is one of the most widely used flat panel displays (FPD). An LCD includes two substrates on which electrodes are formed and a liquid crystal layer that is interposed therebetween so that a voltage is applied to the electrodes to re-arrange the liquid crystal molecules of the liquid crystal layer and thereby control the amount of transmitted light.

Among the various types of LCDs, an LCD in which field generating electrodes are provided in two display panels is mainly used. In this type of LCD, a plurality of pixel electrodes are arranged in a matrix on one display panel (hereinafter, referred to as a thin film transistor array panel) and the other display panel (hereinafter, referred to as a common electrode panel) is covered with one common electrode. Different voltages are respectively applied to the pixel electrodes in the LCD, to display an image. Therefore, thin film transistors (TFT) are formed in the display panel for switching the voltages applied to the pixel electrodes. The TFTs have three terminal elements respectively connected to the pixel electrodes, gate lines for transmitting signals for controlling the TFTs, and data lines for transmitting the voltages to be applied to the pixel electrodes.

The TFTs operate as switching elements for transmitting the image signals transmitted through the data lines to the pixel electrodes or for preventing the image signals transmitted through the data lines from being transmitted to the pixel electrodes in accordance with scanning signals transmitted through the gate lines.

A TFT array panel includes a conductive layer including the gate lines and the data lines, and a plurality of thin films including a semiconductor layer and an insulation layer. Each of the thin films is patterned using a separate mask.

As each mask is sequentially added, photosensitive layer application, exposure, development, and cleaning processes must be repeated so that time and cost required for the processes remarkably increase. Therefore, it is desirable to reduce the number of masks used to increase efficiency and reduce cost. Consequently, a method of etching a metal data layer and a semiconductor layer with one mask is suggested.

Furthermore, the entire metal data layer of a typical TFT resides on the upper surface of the semiconductor layer and the semiconductor layer protrudes from the sides of the metal data layer. Therefore, areas of the semiconductor layer that are exposed to the light supplied by a light source increase so that photo leakage current increases and deteriorates the characteristics of the TFTs, which results in an after image that can be recognized. Consequently, an advantageous structure and method for reducing after images are suggested.

SUMMARY

The present invention has been made in an effort to reduce the amount of the semiconductor layer that protrudes from the sides of a metal data layer and to thus improve the characteristics of the thin film transistors (TFT), which results in reduction of an after image.

A method of manufacturing a TFT array panel according to an embodiment of the present invention includes the processes of forming a semiconductor layer and an ohmic contact layer on a gate line, forming a conductive layer on the ohmic contact layer, forming a first photosensitive layer pattern on the conductive layer, etching the conductive layer using the first photosensitive layer pattern as an etching mask, etching the ohmic contact layer and the semiconductor layer by a fluorine-containing gas, a chloride-containing gas, and an oxygen (O2) gas using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern by a predetermined thickness to form a second photosensitive layer pattern, and etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer. The flow ratio between the fluorine containing gas and the oxygen (O2) gas may be in the range of about 4:1 to about 1:1.

A TFT array panel according to an embodiment of the present invention includes a substrate, gate lines formed on the substrate, a gate insulation layer formed on the gate lines, a semiconductor layer formed on the gate insulation layer, data lines formed on the semiconductor layer and including source electrodes, drain electrodes formed on the semiconductor layer to face the source electrodes, and pixel electrodes connected to the drain electrodes. The semiconductor layer may have the same planar shape as the data lines and the drain electrodes. The length of side projections of the semiconductor layer may be no more than 1.5 μm.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so as to be easily understandable to those skilled in the art. As those skilled in the art will realize, the described embodiments may be modified in various ways, all without departing from the spirit or scope of the present invention.

To clarify multiple layers and regions, the thicknesses of the layers may be enlarged in the drawings. Like reference numerals designate like elements throughout the specification. When it is said that any part, such as a layer, film, area, or plate is positioned on another part, it means the part may be directly on the other part or above the other part with at least one intermediate part. On the other hand, if any part is said to be positioned directly on another part it means that there is no intermediate part between the two parts.

A thin film transistor (TFT) array panel according to an embodiment of the present invention will now be described in detail with reference toFIGS. 1 to 3.FIG. 1is a layout view of a TFT array panel according to an exemplary embodiment of the present invention, andFIGS. 2 and 3are cross-sectional views respectively taken along the lines II-II′ and III-III′ of the TFT array panel ofFIG. 1.

A plurality of gate lines121and a plurality of storage electrode lines131are formed on an insulation substrate110that is made of transparent glass or plastic in one example. The gate lines121transmit gate signals and mainly extend in a horizontal direction. The gate lines121include a plurality of gate electrodes124that protrude downward and ends129each having a large area to be connected to other layers or external driving circuits. The storage electrode lines131receive a predetermined voltage and include lines that run almost parallel to the gate lines121and a plurality of pairs of storage electrodes133aand133b. However, the shape and arrangement of the storage electrode lines131may vary.

The gate lines121and storage electrode lines131include lower layers124p,131p,133ap, and133bpincluding an aluminum based metal, such as aluminum (Al) or an aluminum alloy, and upper layers124q,131q,133aq, and133bqincluding a molybdenum based metal, such as molybdenum (Mo) or a Mo alloy. InFIG. 2, for the gate electrode124and the storage electrode line131, p is added to the reference numerals that denote the lower layers and q is added to the reference numerals that denote the upper layers.

A gate insulation layer140made of silicon nitride (SiNx) or silicon oxide (SiOx), in one example, is formed on the gate line121and the storage electrode line131.

A plurality of semiconductor stripes151made of hydrogenated amorphous silicon (a-Si) in one example are formed on the gate insulation layer140. The semiconductor stripes151mainly extend in a vertical direction and include a plurality of projections154that protrude toward the gate electrodes124. The width of the semiconductor stripes151increases in the vicinity of the gate lines121and the storage electrode lines131so that the semiconductor stripes151substantially cover the gate lines121and the storage electrode lines131.

A plurality of ohmic contact stripes and islands161and165are formed on the semiconductor stripes151. In one example, the ohmic contacts161and165are made of a material such as n+ hydrogenated amorphous silicon doped with n-type impurities such as phosphor (P) with high concentration or silicide. The ohmic contact stripes161have a plurality of projections163so that the projections163and the ohmic contact islands165make pairs to be arranged on the projections154of the semiconductor stripes151.

A plurality of data lines171and a plurality of drain electrodes175are formed on the ohmic contacts161and165. The data lines171transmit data signals and mainly extend in the vertical direction to intersect the gate lines121. The data lines171include a plurality of source electrodes173that extend toward the gate electrodes124and ends179each having a large area to be connected to other layers or external driving circuits. The drain electrodes175are separated from the data lines171and face the source electrodes173about the gate electrodes124.

One gate electrode124, one source electrode173, and one drain electrode175constitute one TFT together with the projection154of one semiconductor stripe151, and the channel of the TFT is formed in the projection154between the source electrode173and the drain electrode175.

The data line171has a three-layer structure that includes a lower layer171p, an intermediate layer171q, and an upper layer171r. The drain electrode175also has a three-layer structure that includes a lower layer175p, an intermediate layer175q, and an upper layer175r. The lower layers171pand175pmay be made of a molybdenum based metal, such as pure molybdenum or a molybdenum alloy such as MoN, MoNb, MoV, MoTi, and/or MoW. The intermediate layers171qand175qmay be made of aluminum or an aluminum alloy such as AlNd that has low resistivity. The upper layers171rand175rmay be made of a molybdenum based metal, such as pure molybdenum or a molybdenum alloy such as MoN, MoNb, MoV, MoTi, and/or MoW that is easily connected to ITO or IZO. In general, the sides of the data line171are inclined to the substrate, preferably, at an angle of about 30° to 80°. InFIGS. 2 and 3, for the data line171and the drain electrode175, including the source electrode173and the end179, p is added to the reference numerals that denote the lower layers, q is added to the reference numerals that denote the intermediate layers, and r is added to the reference numerals that denote the upper layers.

The ohmic contacts161and165are positioned on the semiconductor stripe and projection151and154beneath the data line171and the drain electrode175, respectively, so as to reduce contact resistance therebetween.

The semiconductor stripe151, excluding the projection154in which the TFT is positioned, has substantially the same planar shape as the data line171, the drain electrode175, and the ohmic contact layers161,163, and165. That is, the semiconductor stripe151is formed under the ohmic contact layers161,163, and165, and the data line171and the drain electrode175to be exposed between the source electrode173and the drain electrode175. On the other hand, the ohmic contacts161and165and the semiconductor stripe151protrude from the data line171and the data electrode175based on the surfaces that are connected to the data line171and the drain electrode175. Based on the surfaces where the ohmic contacts and the semiconductor layers are connected to the data line and the drain electrode, the parts that protrude from the data line and the drain electrode will be hereinafter referred to as “semiconductor layer side projections”.

The sides of the ohmic contacts and the semiconductor layers are commonly inclined to the substrate, preferably, at an angle of about 30° to 80°. The surfaces where the data line171and the drain electrode175are connected to the ohmic contacts161and165are determined as first reference surfaces and the boundaries of the data line171and the drain electrode175on the first reference surfaces are determined as first lines.

The surfaces where the semiconductor layer and the gate insulation layer are connected to each other are determined as second reference surfaces and the boundaries of the semiconductor layer on the second reference surfaces are determined as second lines. Virtual tangent surfaces (tangent lines) that are connected to the sides of the semiconductor layer on the second lines are determined and lines where the virtual tangent surfaces are connected to the first reference surfaces are determined as third lines. At this time, the distance between the first lines and the third lines may be determined as the length of the semiconductor layer side projections. The length of the semiconductor layer side projections is no more than 1.5 μm in one example, with the length being more advantageous as the length is made smaller.

A protective layer (passivation layer)180is formed on the data line171, the drain electrode175, and the exposed semiconductor stripe151. The protective layer180is made of a non-organic insulator such as silicon nitride or silicon oxide, an organic insulator, and a low dielectric constant insulator. The dielectric constants of the organic insulator and the low dielectric constant are preferably no more than 4.0 in one example. A plurality of contact holes182and185that expose the ends179of the data lines171and the drain electrodes175are formed in the protective layer180, and a plurality of contact holes181that expose the ends129of the gate lines121and a plurality of contact holes184that expose parts of the storage electrode lines131are formed in the protective layer180and the gate insulation layer140.

A plurality of pixel electrodes191, a plurality of overpasses84, and a plurality of contact assistants81and82are formed on the protective layer180. The pixel electrodes191, the overpasses84, and the contact assistants81and82may be formed of a transparent conductive material, such as ITO and IZO, or a reflective metal, such as aluminum, silver, or an alloy of aluminum and silver.

The pixel electrode191is physically and electrically connected to the drain electrode175through a contact hole185to receive a data voltage from the drain electrode175. The pixel electrode191that receives the data voltage generates an electric field together with a common electrode (not shown) of another display panel (not shown) that receives a common voltage so that the direction of the liquid crystal molecules of the liquid crystal layer (not shown) between the two electrodes is determined. The pixel electrode191and the common electrode form a capacitor (hereinafter, referred to as a “liquid crystal capacitor”) to sustain the applied voltage after the TFT is turned off.

The contact assistants81and82are connected to the end129of the gate line121and the end179of the data line171through the contact holes181and182, respectively.

Each overpass84crosses a gate line121and is connected to the exposed part of a storage electrode line131and the exposed end of the free end of a storage electrode133bthrough a pair of contact holes184that are on the opposite sides with the gate line121interposed.

Now, a method of manufacturing the TFT array panel illustrated inFIGS. 1 to 3will be described in detail with reference toFIGS. 4 to 23.

FIGS. 4,18, and21are layout views sequentially illustrating a method of manufacturing a TFT array panel according to an embodiment of the present invention.FIGS. 5 and 6are cross-sectional views respectively taken along the lines V-V′ and VI-VI′ of the TFT array panel ofFIG. 4.FIGS. 7 to 17are cross-sectional views sequentially illustrating a method of manufacturing a TFT array panel according to the embodiment of the present invention.FIGS. 19 and 20are cross-sectional views respectively taken along the lines XIX-XIX′ and XX-XX′ of the TFT array panel ofFIG. 18.FIGS. 22 and 23are cross-sectional views respectively taken along the lines XXII-XXII′ and XXIII-XXIII′ of the TFT array panel ofFIG. 21.

First, as illustrated inFIGS. 4 to 6, a lower layer made of AlNd and a lower layer made of a molybdenum based metal are sequentially laminated on an insulation substrate110made of transparent glass or plastic, in one example. The lower layer and the upper layer are then wet etched to form a plurality of gate lines121, including gate electrodes124and ends129, and a plurality of storage electrode lines131, including storage electrodes133aand133b.

Then, as illustrated inFIGS. 7 and 8, a gate insulation layer140made of silicon nitride (SiNx), an intrinsic amorphous silicon (a-Si) layer150that is not doped with impurities, and an amorphous silicon (n+ a-Si) layer160that is doped with impurities are formed on the gate lines121and the storage electrode lines131by a plasma enhanced chemical vapor deposition (PECVD) method in one example. The intrinsic amorphous silicon layer150is made of hydrogenated amorphous silicon and the amorphous silicon layer160that is doped with impurities is made of amorphous silicon that is doped with n-type impurities such as phosphorus (P) with high concentration or silicide.

A metal data layer170, including a lower molybdenum layer170pmade of a molybdenum based metal, an aluminum layer170qmade of an aluminum based metal, and an upper molybdenum layer170rmade of a molybdenum based metal, are sequentially laminated on the amorphous silicon layer160that is doped with impurities by sputtering.

Then, as illustrated inFIGS. 9 and 10, a photosensitive layer pattern formed on the upper molybdenum layer170ris exposed and developed to form photosensitive layer patterns52and54having different thicknesses. For convenience sake, the parts of the metal data layer170, the amorphous silicon layer160that is doped with impurities160, and the intrinsic amorphous silicon layer150in which wiring lines are to be formed are referred to as wiring line parts A, the part on the gate electrode124where a channel is formed is referred to as a channel part B, and the regions excluding the wiring line parts A and the channel part B are referred to as parts C. In the photosensitive layer pattern, first parts52that are positioned in the wiring line parts A are formed to be thicker than a second part54that is positioned in the channel part B, and the photosensitive layer pattern in the remaining parts C is removed. The ratio of the thickness of the second part54to the thickness of the first parts52varies with the conditions of the etching process that will be described later so that the thickness of the second part54is preferably no more than ½ of the thickness of the first parts52in one example. Various methods may be used for making the thickness of the photosensitive layer pattern vary with position. For example, a semi-transparent region, as well as a transparent region and a light blocking region, may be provided in an exposure mask.

Then, as illustrated inFIGS. 11 and 12, the metal data layer170that is exposed to the remaining parts C is removed by wet etching using the first parts52of the photosensitive layer pattern.

Next, as illustrated inFIGS. 13 and 14, the amorphous silicon layer160that is doped with impurities and the intrinsic amorphous silicon layer150that reside in the remaining parts C are dry etched using the first parts52of the photosensitive layer pattern. In accordance with the present invention, a fluorine containing gas, a chloride containing gas, and an oxygen gas are used as a dry etching gas. The fluorine containing gas may include fluorine atoms (F) such as SF6and CF4. The chloride containing gas may include chloride atoms (Cl) such as Cl2, HCl, BCl3, CCl4, and SiCl2H2. The oxygen gas (O2) is supplied together with the fluorine containing gas and the chloride containing gas.

Etching pressure can be properly selected in accordance with a device used, a device mode, and the size of the substrate. For example, the etching process may be performed at the etching pressure of about 100 to 500 mT in a PE mode device. More preferably, the etching process is performed at the etching pressure of 200 mT. Also, in an RIE mode device, the etching process may be performed at the etching pressure of about 5 to 30 mT.

When SF6, HCl, and O2are used together, the flow ratio between SF6and O2is preferably about 4:1 to 1:1. More preferably, the flow ratio between SF6and O2is about 2:1. The flow ratio between SF6and HCl may be about 1:1 to 5:1; however, it is preferably sustained as 5:1. When the amorphous silicon layer160and the intrinsic amorphous silicon layer150are dry etched at the above-described ratio examples, it is possible to improve the characteristics of the TFT.

As described above, when the metal data layer170and the intrinsic amorphous silicon layer150are etched using the same photosensitive layer pattern, the data lines171, including the source electrodes173and the ends179, and the semiconductor stripes151, including the projections154, have the same planar shape. However, as a result, the semiconductor stripes151formed in a liquid crystal display (LCD) have semiconductor layer side projections that protrude from the data lines171and the drain electrodes175based on the surfaces that are connected to the data lines171and the drain electrodes175.

Therefore, according to the present invention, in the process of dry etching the amorphous silicon layer160, which is doped with impurities, and the intrinsic amorphous silicon layer150that reside in the remaining parts C using the first parts52of the photosensitive layer pattern, the flow ratio among the fluorine containing gas, the chloride containing gas, and the oxygen gas is controlled to be in a predetermined range to reduce the length of the semiconductor layer side projections.

Thereafter, the second part54of the photosensitive layer pattern that is positioned in the channel part B is removed using an etch back process. During this process, the thickness of the first parts52of the photosensitive layer pattern is reduced to some extent.

Next, as illustrated inFIGS. 15 and 16, wet etching is performed using the first parts52of the photosensitive layer pattern from which the second part54is removed to divide the metal data pattern174into the source electrode173and the drain electrode175(see, e.g.,FIG. 2). Then, an amorphous silicon pattern164(FIG. 13) that is doped with impurities is exposed to the channel region between the source electrode173and the drain electrode175.

At this time, since the sides of the metal data pattern174under the photosensitive layer pattern are exposed to the wet etchant, the sides of the metal data pattern174are etched. Therefore, the semiconductor layer side projections that protrude based on the surfaces where the semiconductor stripes151are connected to the data lines171and the drain electrodes175are generated. According to the present invention, the ratio of the etching gas is controlled in the process of dry etching the intrinsic amorphous silicon layer and the amorphous silicon layer to first etch the intrinsic amorphous silicon layer and the amorphous silicon layer inward so that it is possible to reduce the semiconductor layer side projections.

Next, the amorphous silicon pattern164(FIG. 13) that is doped with impurities and is positioned in the channel region is dry etched using the first parts52of the photosensitive layer pattern as an etching mask.

FIG. 17illustrates the lengths of the semiconductor layer side projections that are formed when the flow amounts of dry etching gases SF6, HCl, and O2are 100 sccm, 20 sccm, and 50 sccm, respectively. Referring toFIG. 17, the thickness of the gate insulation layer that was formed at an initial stage was 4,500 Å; however, it is noted that the thickness of the residing gate insulation layer is reduced.

Table 1 illustrates experimental examples of the thickness of the semiconductor layer side projections and the residing gate insulation layers when the amorphous silicon layer and the intrinsic amorphous silicon layer are etched with different flow ratios between the fluorine containing gas and the oxygen gas that are used in accordance with an embodiment of the present invention.

In the experimental examples, the supply amount of HCl was sustained at 20 sccm. Also, in the device in the PE mode, the experiment was performed under the conditions of 200 mT and 400 W. The flow amount of SF6(i.e., the fluorine containing gas) was sustained at 100 sccm, and the flow amount of the oxygen gas (O2) was controlled in the range of 25 sccm to 100 sccm to supply SF6and O2.

As illustrated in Table 1, when the flow ratio between SF6and O2is 4:1 to 1:1, the lengths of the semiconductor layer side projections are reduced. Therefore, it is expected that an after image is reduced. According to the ratio of oxygen contained in the dry etching gas, the length of the semiconductor layer side projections can be reduced; however, the thickness of the residing gate insulation layer is also reduced. When the flow ratio between SF6and O2is 4:1 to 1:1, the gate insulation layer is etched to about 1,540 Å to 2,440 Å. However, the thickness of the residing lower gate insulation layer is sustained at no less than 2,000 Å. When the thickness of the residing lower gate insulation layer is no more than 2,000 Å, a short circuit between the gate lines and the data lines may be generated.

In general, the oxygen gas is used for anisotropic etching and the etching rate in a direction parallel to the substrate increases as the amount of the oxygen gas increases. Therefore, when the amount of oxygen gas used during the dry etch is increased, the amorphous silicon layer160and the intrinsic amorphous silicon layer150are etched inward based on the metal data layer170. Therefore, it is possible to reduce the length of the semiconductor layer side projections that are formed in the LCD.

The ratio of the chloride containing gas may vary. However, in order to improve the effect of the anisotropic etching that is caused by the oxygen gas, the flow ratio between the fluorine containing gas and the chloride containing gas is preferably in the range of about 1:1 to 5:1. According to an embodiment of the present invention, the flow ratio between the fluorine containing gas and the chloride containing gas is 5:1.

In another embodiment, when the fluorine containing gas, the chloride containing gas, and the oxygen gas are mixed with each other, the flow ratio between the fluorine containing gas and the oxygen gas may change in the range of 4:1 to 1:1 in accordance with time.

As illustrated inFIGS. 18,19, and20, the first parts52of the photosensitive layer pattern are then removed.

Next, the protective layer180is formed to cover the semiconductor projection154that is not covered with the data line171and the drain electrode175, as illustrated inFIGS. 21 to 23. Then, the protective layer180is etched by a lithographic process to form a plurality of contact holes181,182,184, and185.

Finally, as illustrated inFIGS. 1 to 3, after depositing a transparent conductive material such as ITO or IZO on the protective layer180by sputtering, the conductive material is patterned to form the pixel electrodes191, the contact assistants81and82, and the overpasses84.

As described above, the data lines are made of a multi-layer film including an aluminum layer and a molybdenum layer and the ohmic contact layers and the semiconductor layers are etched by an etching gas with a predetermined flow ratio so that it is possible to improve the characteristics of the TFT and to prevent the generation of an after image.

While embodiments of the present invention have been described in detail above, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention. For example, although the present invention was described above based on four processes, the present invention can be used for three processes. Accordingly, the scope of the invention is defined only by the following appended claims.