Parameter collapsing and corner reduction in an integrated circuit

Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

BACKGROUND

The present invention relates generally to the field of static timing analysis of a microchip or an integrated circuit design, and more particularly to analysis and reduction of runtime overhead needed for statistical static timing analysis of an integrated circuit design.

BRIEF SUMMARY

Embodiments of the present invention disclose a method, system, and computer program product for using a computing device to reduce runtime overhead needed for testing of an integrated circuit design. The computing device determines parameters that clock routing and data routing in the integrated circuit are dependent upon. The computing device determines whether the parameters are suitable for compaction by determining whether the parameters are utilized in only one of clock routing and data routing. The computing device redefines the parameters suitable for compaction into at least one proxy compacted parameter. The computing device performs a timing analysis for the integrated circuit using the at least one proxy compacted parameter, instead of performing the timing analysis using the parameters suitable for compaction.

In an alternative embodiment, the present invention discloses a method, system, and computer program product for using a computing device to reduce the runtime overhead needed for testing of an integrated circuit design. Parameters of the integrated circuit design suitable for compaction are determined. The parameters suitable for compaction are defined into at least one proxy compacted parameter set. A timing analysis is performed for the integrated circuit design utilizing the proxy compacted parameter set.

DETAILED DESCRIPTION

Integrated circuits continue to increase in complexity, while consumers and corporations demand increasingly accelerated design and testing phases to send a finished product to the market in the fastest way possible. As manufacturing process and environmental variation in the integrated circuit increases more process corners are required to cover variation which may slow down development of the integrated circuit into a commercial product. Process corners are the extremes of parameter variation under which the integrated circuit must be designed to function. A need therefore exists for a more efficient manner of testing an integrated circuit design before production. Presented is a method, system and computer program product for parameter collapsing and corner reduction, allowing the collapsing of integrated circuit parameters during the course of testing to allow multiple parameters to be tested as one, and corresponding reduction in the number of corners needed for testing of the integrated circuit.

“Parameters” as described with reference to this patent application are any of sources of variation which arise in the course of design of an integrated circuit which impact the delay or slew of voltage through elements of the integrated circuit, and hence impact circuit performance. Since integrated circuits are engineered and fabricated on a very small scale, the nearly microscopic or microscopic components utilized in the integrated circuit are subject to some variation simply because of their extremely small size. Parameters may include, by means of non-limiting example, variation in a width of a fabricated component in the integrated circuit, variation in a thickness of a fabricated component in the integrated circuit, variation in a wire segment or a silicon transistor shape in the integrated circuit, line edge roughness of a metal or a silicon in the integrated circuit, variation in dopants or implants utilized in the manufacture of the integrated circuit, variations in device threshold voltage, variations in supply voltage for the integrated circuit, and variations in a temperature across the integrated circuit. The effects of these parameters on circuit performance must be evaluated, as further described herein, to ensure the design functions with adequate yield over the full range of manufacturing and environmental conditions.

FIG. 1is a functional block diagram illustrating an environment for testing and improving runtime overhead for an integrated circuit100, in accordance with an embodiment of the present invention. In an exemplary embodiment, included in the environment100is an IC Testing Computer Device120and a Computer-Aided Design Terminal130, all interconnected via a network140.

In various embodiments, network140represents, for example, an intranet, a local area network (LAN), a wide area network (WAN) such as the Internet, and includes wired, wireless, or fiber optic connections. In general, network140may be any combination of connections and protocols that will support communications between IC Testing Computer Device120and Computer-Aided Design Terminal130, in accordance with an embodiment of the invention.

In various embodiments, IC Testing Computer Device120and Computer-Aided Design Terminal130may be, for example, a mainframe or a mini computer, a terminal, a laptop, a tablet, a netbook personal computer (PC), a mobile device, or a desktop computer, or any other sort of computing, in accordance with the embodiments described herein. IC Testing Computer Device120and Computer-Aided Design Terminal130may include internal and external hardware components as depicted and described in further detail below with reference toFIG. 6, below. In other embodiments, each of IC Testing Computer Device120and Computer-Aided Design Terminal130may be implemented in a cloud computing environment, as described in relation toFIGS. 7 and 8, below. In a still further embodiment, the IC Testing Computer Device120and Computer-Aided Design Terminal130are embodied in physically the same computing device, with all communications between various components made internally.

IC Testing Computer Device120, in effect, represents any sort of computing device possessing sufficient processing power to execute software to be utilized in testing of an integrated circuit design. The IC Testing Computer Device120terminal may, in testing the integrated circuit design, utilize a hosted workload96as displayed in connection withFIG. 8below, and/or perform other tasks as further described herein. In the exemplary embodiment, IC Testing Computer Device120includes a User Interface121, a CAD Interface Tool123, a Parameter Assessment Tool125, a Parameter Compaction Tool127, Timing Analysis Software128, and a Design Update Module129.

User Interface121represents an IC Testing Computer Device120installation of a software interface for accessing and utilizing the IC Testing Computer Device120. In practice, the User Interface121may accessed by a keyboard, mouse, touch screen, or any other type of input device. The User Interface121may not be present at all in embodiments of the invention where all the functionality such as further described below occurs in a purely automated fashion.

CAD Interface Tool123represents software for accessing, downloading, and analyzing integrated circuit designs such as prepared on the Computer-Aided Design Terminal130, as is further discussed below. In a further embodiment, the CAD Interface Tool123also provides functionality by which a proposed update circuit design is transmitted back to the Computer-Aided Design Terminal130for implementation as a new design (as discussed further below in connection with the Design Update Module129).

Parameter Assessment Tool125represents software for determining parameters that clock routing and data routing in an integrated circuit are dependent upon. A clock signal, such as propagated through clock routing, as is commonly understood by one of skill in the art, is at least one oscillating signal used within the integrated circuit to keep time so as to sync actions of the integrated circuit. Syncing actions of the integrated circuit is particularly important with regard to data signal(s) which travel through varied logic circuits within the integrated circuit, and, depending on routing decisions made, could arrive at the same portions of the logic circuits at different times because of the different relative lengths of the path of the logic circuit, different paths, etc. Syncing actions of the data signal may include, for example, ascertaining that the data signal arrives at various points within the integrated circuit at the correct time. As the signals propagate through the integrated circuit, each of clock routing and data routing travels through a variety different components that are composed of different “parameters.” Whether the parameters be varying levels of fabricated components within the integrated circuit, certain wire segments, etc., since the parameters could have the effect of speeding up or delaying the various clock signals and data signals at issue, they must be modeled before manufacture. The Parameter Assessment Tool125, in effect, evaluates sources of variation unique to the clock routing, evaluates sources of variation unique to the data routing, and/or determines parameters having insignificant impact on either. In an alternative embodiment, the Parameter Assessment Tool125leverages design knowledge of which parameters are suitable for compaction, the design knowledge obtained during an initial design phase.

Parameter Assessment Tool125also represents software for determining whether the parameters that clock routing and data routing are dependent upon are suitable for compaction, via a determination of whether the parameters appear in and are utilized in only one of clock routing and data routing. If the parameters appear in both clock routing and data routing, the parameters may not be suitable for compaction. The Parameter Assessment Tool125may further determine whether it is physically feasible to compact parameters (i.e. is it physically legitimate to compact the parameters, such as because they are all of the same family of parameter variation (for example, metal layer thickness), or because independent modeling is otherwise not required for any needed analysis).

Parameter Compaction Tool127represents software which redefines parameters for compaction into at least one proxy compacted parameter, if appropriate. In effect, the Parameter Compaction Tool127redefines the parameters to be compacted into a lesser number of parameters, so as to lower the number of parameters tested. This process is further described below.

Timing Analysis Software128represents software for actually performing a timing analysis and testing the parameters in the integrated circuit. If any parameters have been combined into proxy compacted parameters, the timing analysis is performed upon the proxy compacted parameter rather than independently upon each parameter which has been compacted. This serves to realize an advantage of the invention in reducing runtime overhead, obviating the need to test each parameter individually. The timing analysis, as understood by one of skill in the art, is typically a statistical static timing analysis (“SSTA”). SSTA, or other timing analysis, is an important step in design of integrated circuits because it is the step in design where race conditions or hazards which could cause an integrated circuit to malfunction are identified, the speed of the integrated circuit is determined, and obstacles which lower the operational speed of the integrated circuit are found, among other reasons.

The proxy compacted parameters may be tested by an SSTA path-based algorithm, an SSTA block-based algorithm, or another. Block-based algorithms, the most efficient technique, compute signal arrival times (or signal required arrival times) as functions of process parameters for each circuit node in its topological order. Path-based SSTA algorithms, on the other hand, analyze each signal propagation path separately, and calculate the probability distribution for circuit delay as the probabilistic maximum of all path delays. Path-based SSTA algorithms are less commonly used than block-based algorithms. The end result of a timing analysis performed by the Timing Analysis Software128is dependent upon the number of parameters that may be collapsed. The runtime needed for testing of the integrated circuit design scales nearly linearly with the number of parameters being modeled, and so the runtime reduction introduced by collapsing of parameters scales roughly linearly with the number of parameters collapsed.

In a further embodiment, the Timing Analysis Software128may also test all other parameters present in the integrated circuit individually which have not been proxy compacted. The results of the Timing Analysis Software128may simply be a “pass” or a “fail.” In a further embodiment, the proxy compacted parameter is not analyzed independently, but rather applied as a mean shift after calculation. In this embodiment, once the collapsed level of variation has been quantified with the proxy compacted parameter(s), it is applied as a shift to the mean of the timing distribution for propagation, rather than being propagated as an additional independent source of variation.

The Design Update Module129generates an updated circuit design for the integrated circuit if the timing analysis fails, the updated circuit design allowing the integrated circuit design to pass the timing tests presented. The Design Update Module129is shown as implemented in the IC Testing Computer Device120, but in a further embodiment is implemented directly in the Computer-Aided Design Terminal130, or elsewhere. The updated circuit design is targeted at a correction of the flaw in the integrated circuit leading to the failure of the timing analysis, and serves to allow the integrated circuit to pass a subsequent timing analysis. The newly updated design as well may require testing, such as presented by the current invention. Alternately, instead of suggesting an updated circuit design by the Design Update Module129, the Design Update Module129may automatically present a waiver to a user. The waiver provides informed consent that the integrated circuit design has failed testing to the user, but allows the failed design to proceed to manufacture, if desired.

Continuing with regard toFIG. 1, Computer-Aided Design Terminal130, as stated previously, represents any sort of computing platform possessing sufficient processing power to execute software to be utilized in testing of an integrated circuit design, and perform the other tasks as further described herein. In the exemplary embodiment, Computer-Aided Design Terminal130includes a User Interface131, an IC Design Module133, and an Interface Module135. The Computer-Aided Design Terminal130, as described in more detail below, is involved in the generation of computer-aided design plans for integrated circuits.

User Interface131allows a user to access and utilize the Computer-Aided Design Terminal130for the design of integrated circuits. Various tools are available for the design of various aspects of the integrated circuit, as well as visualize the results in various stages of completion. As would be understood by one of skill in the art, the design of integrated circuits is at least in-part automated, to account for their extremely complex nature.

IC Design Module133, after receiving inputs from the User Interface131regarding various characteristics of the IC design requested by the user, produces a design of the integrated circuit accounting for design objectives, various known rules, and design limitations, some of which may be unique to the design and some of which are general to all integrated circuit design.

The Interface Module135is a software module for communication with the IC Testing Computer Device120. In effect, the interface module135transmits a proposed IC design to the IC Testing Computer Device120(specifically via the CAD Interface Tool123), and, after the IC Testing Computer Device120has finished testing the proposed design, receives the results of testing performed.

FIG. 2is a process flow diagram showing a process of redefining parameters for compaction and performing a timing analysis for the integrated circuit, in accordance with an embodiment of the present invention. The IC Testing Computer Device120is pictured. The IC Testing Computer Device120receives an integrated circuit design for testing (such as from the Computer-Aided Design Terminal130), through the CAD Interface Tool123associated with the IC Testing Computer Device120. The IC Testing Computer Device120, utilizing the Parameter Assessment Tool125, determines the parameters that clock routing and data routing are dependent upon, or, in effect those parameters encountered in the various circuit elements traveled. The results are shown210. Clock routing and data routing depend upon parameters P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, and P15, as displayed210.

Continuing with regard toFIG. 2, the IC Testing Computer Device120, again using the Parameter Assessment Tool125, then determines which parameters are encountered in only one of clock routing and data routing, but not both, and are therefore suitable for compaction. The IC Testing Computer Device120determines that clock routing230encounters only parameters P2, P3, P4, and P5, as displayed235, whereas data routing220encounters all of parameters P1through P15, as displayed225. Such data is stored for later use by the IC Testing Computer Device120, and the computer device120determines parameters P1, P6, P7, P8, P9, P10, P11, P12, P13, P14, and P15are encountered exclusively in data routing265. These parameters are, therefore, appropriate for redefinition and collapse into a proxy compacted parameter, for timing analysis purposes. The IC Testing Computer Device120then, via the Parameter Compaction Tool127, redefines the parameters suitable for compaction265into at least one proxy compacted parameter, displayed Pcollapse270inFIG. 2. The IC Testing Computer Device120, via the Timing Analysis Software128, then performs the timing analysis for the integrated circuit using the proxy compacted parameter Pcollapse270, rather than directly on the individual parameters suitable for compaction, and determines whether the integrated circuit passes or fails. On the other hand, parameters P2, P3, P4, and P5, as displayed251,253,255, and257, are encountered in both clock routing and data routing, so are not appropriate for compaction. The IC Testing Computer Device120proceeds to test each of these parameters individually, and determines whether each passes or fails.

FIG. 3is a simplified circuit300diagram of clock paths and data paths, in accordance with an embodiment of the present invention. As understood by one of skill in the art, clock signal310is generated to be utilized by various components of the circuit300in maintaining synchronization among various components of the integrated circuit. The clock signal310on clock path can only have clock inverters and clock buffers as its elements. The common clock path320, as displayed, along which the clock signal travels before traveling through junction325.

The capture clock path350receives the clock signal transmitted along the clock path317from junction325, before the clock signal arrives at clock input367, and latches the data signal at data input363into capture storage element latch360. As is displayed inFIG. 3, the clock signal travels through circuit elements sensitive to parameters P2, P3, P4, and P5, as displayed235. The capture clock path350is also responsible for indicating to the latch340that data from the data path312is be stored in the latch340, as further discussed below.

Launch clock path330is responsible for carrying a data signal once the clock signal reaches the launch storage element340at input343. The data path312is then launched via output Q347. The data signal on data path312can have any combination of gate along data path312. The data signal at launch storage element output Q347travels along the data path312to data input363of capture storage element360. As is displayed inFIG. 3, parameters P1through P15are utilized by the data signal traveling along the data path312, as shown225. As discussed elsewhere herein, knowledge of parameters that clock routing and data routing are dependent upon is necessary for the operation of the presently disclosed invention. So long as the data signal arrives at input363and the clock signal arrives at input367within a certain window of time of each other, the capture storage element360state changes, and further logical executions may occur in the simplified circuit300(not displayed here).

FIG. 4is a flowchart depicting operational steps that a hardware and software component of a hardware appliance may execute, in accordance with an embodiment of the invention. At step405, the Parameter Assessment Tool125determines parameters that clock routing and data routing in the integrated circuit are dependent upon. The Parameter Assessment Tool125may, in order to determine parameters that clock routing and data routing are dependent upon, evaluate sources of variation unique to the clock routing, evaluate sources of variation unique to the data routing, and/or determine parameters having insignificant impact on either. At step410, the Parameter Assessment Tool125determines whether the parameters are suitable for compaction via a determination of whether the parameters are encountered in only one of clock routing and data routing in the integrated circuit. At step415, the Parameter Compaction Tool127redefines the parameters suitable for compaction into at least one proxy compacted parameter. At step420, Timing Analysis Software128performs a timing analysis for the integrated circuit using the at least one proxy compacted parameter instead of performing a timing analysis on the same parameters which have been compacted individually. The timing analysis may be, as discussed previously, an SSTA block-based analysis or an SSTA path-based analysis. Alternately, the proxy compacted parameter may not be analyzed independently but rather applied as a mean shift after calculation. At step425, if the timing analysis fails, the Design Update Module129suggests an updated circuit design for the integrated circuit. The updated circuit design allows the integrated circuit to pass testing, as discussed elsewhere herein.

FIG. 5is a flowchart depicting operation steps that a hardware component of a hardware appliance may execute, in accordance with an embodiment of the invention. At step505, the Parameter Assessment Tool125determines parameters of an integrated circuit design suitable for compaction. At step510, the Parameter Compaction Tool127defines the parameters suitable for compaction into at least one proxy compacted parameter set. At step515, the Timing Analysis Software128performs a timing analysis for the integrated circuit using the at least one proxy compacted parameter set. As in previous embodiments, the timing analysis may be an SSTA block-based analysis or an SSTA path-based analysis. At step520, the Design Update Module129suggest an updated circuit design for the integrated circuit.

FIG. 6depicts a block diagram of components of IC Testing Computer Device120of the environment for testing and improving runtime overhead for an integrated circuit design ofFIG. 1, in accordance with an embodiment of the present invention. It should be appreciated thatFIG. 6provides only an illustration of one implementation and does not imply any limitations with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made.

IC Testing Computer Device120may include one or more processors902, one or more computer-readable RAMs904, one or more computer-readable ROMs906, one or more computer readable storage media908, device drivers912, read/write drive or interface914, network adapter or interface916, all interconnected over a communications fabric918. Communications fabric918may be implemented with any architecture designed for passing data and/or control information between processors (such as microprocessors, communications and network processors, etc.), system memory, peripheral devices, and any other hardware components within a system.

One or more operating systems910, and one or more application programs911, for example, presentation program110, are stored on one or more of the computer readable storage media908for execution by one or more of the processors902via one or more of the respective RAMs904(which typically include cache memory). In the illustrated embodiment, each of the computer readable storage media908may be a magnetic disk storage device of an internal hard drive, CD-ROM, DVD, memory stick, magnetic tape, magnetic disk, optical disk, a semiconductor storage device such as RAM, ROM, EPROM, flash memory or any other computer-readable tangible storage device that can store a computer program and digital information.

IC Testing Computer Device120may also include a R/W drive or interface914to read from and write to one or more portable computer readable storage media926. Application programs911on IC Testing Computer Device120may be stored on one or more of the portable computer readable storage media926, read via the respective R/W drive or interface914and loaded into the respective computer readable storage media908.

IC Testing Computer Device120may also include a display screen920, a keyboard or keypad922, and a computer mouse or touchpad924. Device drivers912interface to display screen920for imaging, to keyboard or keypad922, to computer mouse or touchpad924, and/or to display screen920for pressure sensing of alphanumeric character entry and user selections. The device drivers912, R/W drive or interface914and network adapter or interface916may comprise hardware and software (stored on computer readable storage media908and/or ROM906).

The present invention may be a method, system, and/or computer program product at any possible technical detail level of integration. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.

Characteristics are as follows:

Service Models are as follows:

Deployment Models are as follows:

Based on the foregoing, a method, system, and computer program product have been disclosed. However, numerous modifications and substitutions can be made without deviating from the scope of the present invention. Therefore, the present invention has been disclosed by way of example and not limitation.