Non-volatile memory device manufacturing process testing systems and methods thereof

Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.

FIELD OF THE INVENTION

The present invention relates to non-volatile memory devices, and more particularly to non-volatile memory device (NVMDs) manufacturing testing systems and methods.

BACKGROUND OF THE INVENTION

Personal computers have become mainstream computing devices for the past two decades. One of the core components of a personal computer whether desktop or laptop is a mother board, which is the central or primary circuit board providing attachment points for one or more of the following: processor (CPU), graphics card, sound card, hard disk drive controller, memory (Random Access Memory (RAM), Read-Only Memory (ROM)), and other external devices. Traditionally, hard disk drives have been used as data storage in a computing device. With advance of non-volatile memory (e.g., flash memory), some attempts have been made to use non-volatile memory as the data storage.

Advantages of using non-volatile memory as data storage over hard disk drive are as follows:

(2) No noise or vibration caused by the moving parts;

(4) Faster startup (i.e., no need to wait for spin-up to steady state);

(6) Faster boot and application launch time;

(7) Lower read and write latency (i.e., seek time);

Non-volatile memory (NVM) modules are generally manufactured in two stages by two manufacturers: a memory chip maker and a memory module assembler. The memory chip maker (e.g., fab or foundry) makes NMV chips or integrated circuits first. Then memory module manufacturers use the NVM chips to make NVM modules. Traditionally, NVM chips are tested by memory chip makers to guarantee certain level of quality, such that memory module manufacturers can confidently use the tested NVM chips to assemble NVM modules. To ensure the quality of the NVM modules assembled, the memory module manufacturers must conduct a series of tests.

However, testing NVM modules in mass quantity is a challenging problem. For example, just assembled NVM modules generally contain blank NVM chips, which are not accessible by users. There may also be different types of NVM chips from different chip manufacturers.

Therefore it would be desirable to provide efficient and effective systems and methods of testing non-volatile memory modules in mass quantity by a memory module assembler.

BRIEF SUMMARY OF THE INVENTION

This section is for the purpose of summarizing some aspects of the present invention and to briefly introduce some preferred embodiments. Simplifications or omissions in this section as well as in the abstract and the title herein may be made to avoid obscuring the purpose of the section. Such simplifications or omissions are not intended to limit the scope of the present invention.

Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are disclosed. According to one aspect of the present invention, an apparatus of testing NVM modules during manufacturing comprises a main testing platform, a central processing unit (CPU) coupling to the main testing platform and a plurality of system bus slots. Each of the system bus slots is configured to receive a respective one of a plurality of NVM test modules. Each of the NVM test modules is configured to test one NVM module. The CPU is configured to issue a master test command to all of the NVM test modules adapted thereon thru the system slots. Each of the NVM test modules comprises an interface to transmit data, control signals and power between the main testing platform and the each of the NVM test modules. A test vector is generated and written to the NVM module under test. The test vector comprises a repeatable sequence of data bits. The sequence may comprise a regular pattern or a random pattern. The stored values are then retrieved and compared with the known test vector to determine whether the NVM module under test passes the function test.

According to another aspect, a system for testing NVM modules during manufacturing comprises a computer and a NVM tester coupling to the computer via an external bus (e.g., Universal Serial Bus (USB)). The NVM tester comprises a plurality of slots for accommodating the NVM modules to be tested, one slot for each module. The NVM tester is configured to include an external bus interface, a microcontroller with associated random access memory (RAM) and a read-only memory (ROM), a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test according to the start and end addresses generated by the address generator. The known test vector is then compared with the data retrieved or read from the NVM module after the test vector has been written into. The test result is shown in the test result indicator.

According to one embodiment of the present invention, A method of testing a plurality of non-volatile memory (NVM) modules comprises at least the following: conducting an initial open/short test on each of the plurality of NVM modules; dividing the plurality of NVM modules into first and second groups, the first group contains said each of the plurality of NVM modules fails in the initial open/short test, while the second group contains said each of the plurality of NVM modules passes the initial open/short test; conducting a temperature and voltage test on each of the second group of the NVM modules; dividing the second group into third and fourth groups, the third group contains said each of the second group that fails the temperature and voltage test and the fourth group contains said each of the second group that passes the temperature and voltage test; conducting a function test on each of the fourth group of the NVM modules; dividing the fourth group into fifth and sixth groups, the fifth group includes said each of the fourth group that fails the function test and the sixth group includes said each of the fourth group that passes the function test; and sending all of the first, third and fifth group of the NVM modules to a rework unit for fixing failure-causing defect; wherein the open/short test is configured to detect any open and/or short condition, wherein the temperature and voltage test is configured to determine whether operating temperature and voltage tolerance are met, and wherein the function test is configured to verify whether data stored in NVM cells are reliable.

The function test further comprises coupling at least one of the sixth group of the NVM modules to a plurality of NVM test modules mounted on a main testing platform, each of the at least one of the sixth group of the NVM modules corresponds to a respective one of the plurality of NVM test modules; initializing each of the at least one of the sixth group of the NVM modules by the main testing platform; and verifying data written to said each the at least one of the sixth group with a test vector created by the respective one of the NVM test modules. The initializing each of the at least one of the sixth group of the NVM modules by the main testing platform further comprises receiving a command from the host at said each of the at least one of the sixth group of the NVM modules to check manufacturer's identification (ID) of NVM; sending the ID to the main testing platform to obtain a set of specific characteristics corresponding to the ID in a database stored thereon; receiving a boot code and a run code to perform a self test; and when the self test passes, formatting said each of the at least one of the sixth group of the NVM modules and loading an operating system image thereto.

According to another embodiment, the present invention includes an apparatus for testing a plurality of non-volatile memory (NVM) modules comprises at least the following: a main testing platform with a central processing unit mounted thereon; a plurality of NVM test modules coupling to the main testing platform, each of the test modules is configured to receive respective one of the plurality of NVM modules to be tested and each of the plurality of NVM test modules comprises: an input/output (I/O) interface configured to transmit commands and data between the main testing platform and said each of the plurality of the NVM test modules; a data generator configured for generating a repeatable sequence of data for a test vector to be written to the respective one of the plurality of NVM modules under test; an address generator configured for creating start and end addresses for the test vector; a comparator configured to compare the repeatable sequence of data of the test vector and data retrieved from the respective one of the NVM modules after the test vector has been written into; a memory space configured to store comparison status; and a set of indicators configured to show test result.

According to yet another embodiment, the present invention includes a system for testing a plurality of non-volatile memory (NVM) modules comprises at least the following: a computer; a NVM tester coupling to the computer via an external bus, the NVM tester comprises a plurality of slots, each of the slots is configured to receive respective one of the plurality of NVM modules to be tested; the NVM tester further comprises: an external bus interface configured to transmit data, control signals and power between the NVM tester and the computer; a data generator configured for generating a repeatable sequence of data for a test vector to be written to the plurality of NVM modules under test; an address generator configured for creating start and end addresses for the test vector; a comparator configured to compare the repeatable sequence of data of the test vector and data retrieved from the NVM modules after the test vector have been written into; a memory space configured to store comparison status; and a set of indicators configured to show test result.

One of the objects, features, and advantages in the present invention is that a plurality of non-volatile memory (NVM) modules may be tested with a main testing platform or a NVM tester for a function test that simulates usage of the NVM device by users. Other objects, features, and advantages of the present invention will become apparent upon examining the following detailed description of an embodiment thereof, taken in conjunction with the attached drawings.

DETAILED DESCRIPTION

Referring now to the drawings,FIGS. 1A-Bcollectively is a flowchart100illustrating an exemplary manufacturing and testing procedure of a non-volatile memory module by a memory module assembler in accordance with one embodiment of the presented invention. The process100may be implemented using a series of computer based tests combined with manual inspection and rework procedures.

The process100starts by preparing a bill of materials required for assembler an NVM device at102. Then, at104, a plurality of non-volatile memory (NVM) chips or integrated circuits and other components are acquired. NVM may include, but not necessarily limited to, single-level cell flash memory (SLC), multi-level cell flash memory (MLC), phase-change memory (PCM), Magnetoresistive random access memory, Ferroelectric random access memory, Nano random access memory.

At106, the process100prints solders to a first surface of a print circuit board (PCB) according to specific requirements using a custom made stencil. Components (e.g., NVM chips, NVM controller, capacitors, resistors, etc.) are then placed on the specific locations. Next, at108, the PCB with the components placed thereon is put into an infra-red oven to melt the solders with a target temperature. The melted solders fuse the pins or contacts to form electrical connections. The process100repeats a substantially similar procedure for a second surface of the PCB at110. Once a NVM module is assembled, the process100may optionally attach another NVM module to form a larger capacity NVM device at112.FIGS. 2A-2Dshow various stages of the steps described herein.

After an NVM module is assembled together, an initial open/short test is conducted at120. If the NVM module fails the open/short test, the failed module is sent back to a manual inspection and rework unit to correct the defects at122. Otherwise an operating temperature and voltage test is conducted to those NVM modules that passed the open/short test at124. Again, the failed NVM modules are sent to the rework unit at122. Remaining NVM modules that passed the temperature and voltage test are put into a main testing platform or a NVM tester to conduct a function test at125. Detailed procedure of the function test is described inFIGS. 5A-Cand corresponding descriptions thereof. The main testing platform and a NVM tester are described inFIGS. 3A-Band4A-B, respectively. If ‘fail’, the NVM modules are sent back to the rework unit at122.

Once passed the function test, the process100moves to decision132conducting a final quality assurance (QA) test. If ‘fail’, any modules that failed the final QA test is sent back to the rework unit at122. Otherwise, those NVM devices passed the industrial grade final QA test are packaged and shipped at134before the process100ends.

FIG. 1Cis a flowchart illustrating an alternative to the steps of process110shown inFIG. 1B. The open/short, temperature and voltage and function tests are exactly the same as shown in decisions120,124and125, respectively. After passed the function test125, the NVM modules are at least commercial grade ready after passing the function test. Next, a more stringent industrial grade test is conducted at126. For example, the industrial grade NVM devices must be able to operate in temperature range between −40 to 85 degree Celsius. If ‘pass’, the process100covers the passed NVM modules with a layer conformal coating at128. It is noted that connectors and pins are not coated. Then the coated NVM modules are encased in an industrial grade casing at130. A final industrial grade quality assurance (QA) test is conducted at132. Those NVM devices passed the industrial grade final QA test are packaged and shipped at134.

Otherwise the NVM devices fails either the industrial grade test at126or the final industrial grade QA test at132are downgraded to a commercial grade at136. Next, at138, a commercial grade casing is used to encase a NVM module to form a commercial grade NVM device. Similarly, a final commercial grade QA test is conducted at140. If ‘pass’, the NVM devices can be packaged and shipped at134. Otherwise, the NVM devices that fail the final commercial grade QA test are sent back to the rework unit at122.

FIG. 2Ashows an exemplary NVM module200after a first surface201has been mounted with a plurality of components during assembling process. The NVM module200comprises a Serial Advanced Technology Attachment (SATA) connector211, a converter212(i.e., converting SATA to Parallel ATA), a oscillator213, a Redundant Array of Independent Disks (RAID) controller214, a plurality of passive components215(i.e., capacitors and resistors), an Integrated Drive Electronics (IDE) controller216and a plurality of NVM chips217mounted on the first surface201of a PCB.

FIG. 2Bshows the NVM module200ofFIG. 2Aafter both sides have been mounted with components. On the second surface202of the PCB, there are a plurality of passive components215and a plurality of NVM chips217.

FIG. 2Cis a cross-sectional view showing the non-volatile memory module200ofFIG. 2Bincluding a first add-on module230adapted thereon. To adapt the first add-on module230to the NVM module200, a connector231and a spacer232are used. A second add-on module240is shown inFIG. 2D. Similarly, a connector241and a pair of spacers242are used to adapt the second add-on module240with the NVM module200. The connectors231and241are configured to connect power and signal lines between two modules.

Referring toFIG. 3A, it is a perspective block diagram showing a main testing platform302with a plurality of NVM test modules330a-nmounted thereon, each of the NVM test modules330a-nis configured for testing a respective NVM module320a-n, according to an embodiment of the present invention. The main testing platform302(i.e., host) comprises a central processing unit (CPU)304and a plurality of system bus (e.g., Peripheral Component Interconnect Express (PCI-e)) slots315a-n. Each of the slots315a-nis configured to accommodate a respective one of a plurality of NVM test modules330a-n. Each of the NVM test modules330a-nis configured to receive one of a plurality of NVM modules320a-nto be tested. The CPU304of the main testing platform302is configured to issue a master test command. Each of the NVM test modules330a-nis then conducting a self contained function test with the respective one of the NVM modules320a-nadapted thereon. In one embodiment, the main testing platform302may comprises a mother board of a personal computer with a plurality of PCI-e buses mounted thereon.

FIG. 3Bis a block diagram showing one of the exemplary NVM test modules330a-nadapted to one of the system bus slots315a-nand coupled to one of the NVM modules320a-nto be tested in accordance with one embodiment of the present invention. The NVM test module330a-ncomprises a command receiver332, a pseudo random number generator (RNG)338, a seed register334, an address generator336, a comparator342, a comparison result storage space344and a test result indicator346. The command receiver332is configured to receive the master test command issued by the main testing platform302. The seed register334is configured to store a seed for generating pseudo random number sequence by the pseudo RNG338. Value of the seed may be determined by the received master test command in one embodiment. The seed may be set by each of the NVM test modules330a-nto a fixed value. The pseudo RNG338is configured to generate a repeatable random sequence of data bits (e.g.,FIG. 8B). The repeatable random sequence of data bits is used as a test vector to verify the same data that have been written to the respective one of the NVM modules320a-nunder test. The address generator336is configured to create a start and an end address of the NVM module under test. The start and end addresses are configured for writing and read the test vector to and from the NVM module under test. The start and end addresses may only cover a portion of the NVM module320a-n, such that only a portion of the NVM module may be tested. In other words, entire NVM module under test may be tested multiple times, each time with a different test vector. The test vector may also comprise a sequence of fixed pattern of data bits (e.g.,FIG. 8A). In such case, the pseudo RNG338and the seed register334are not required. Instead a data generator (not shown inFIG. 3B) may be used.

Once created, the test vector is written to the NVM module320a-nunder test from the starting to the end address. The stored data are retrieved or read back to the NVM test module330a-nthereafter. The retrieved data is compared with the test vector at the comparator342. The comparison status is stored in a storage space344and reported back to the main testing platform302. When the test vector is a repeatable random sequence, the test vector may need to be regenerated during the comparison phase of the testing. The test result indicator346is configured to show the test result in an easy and intuitive manner, for example, a color light with green, red and yellow. The green represents a ‘passed’ status, while the red represents a ‘failed’ status, and the yellow may represent a test is running or other meanings.

FIG. 4Ais block diagram showing a host computer402with an exemplary high speed external bus (e.g., Universal Serial Bus (USB)) based NVM tester410configured for testing a plurality of NVM modules, according to another embodiment of the present invention. The NVM tester410comprises an external bus connector412(e.g., USB connector) and a plurality of external bus slots415a-n. The external bus connector412is configured for connecting the host computer402via a connector cable406, which is configured to transmit data, control signals and power. The plurality of the external bus slots415a-nis configured to accommodate a plurality of NVM modules420a-nunder test, respectively.

A function block diagram of the NVM tester410is shown inFIG. 4Baccording to an embodiment of the present invention. The tester410comprises an external bus interface431, a controller434, a read-only memory (ROM)433, a general purpose random access memory (RAM)432, a data generator438, an address generator436, a comparator442, a comparison status storage space444, a test result indicator446and a NVM module detector450.

The external bus interface431(e.g., USB interface) is configured to facilitate data, control signals and power transmission between the host computer402and the NVM tester410. The controller434is configured to manage and control all of the functions of the NVM tester410. Coupling to the controller434, the RAM432is configured to be a main memory space for the controller434, while the ROM433is configured to be a memory space for storing firmware or other software. The data generator438is configured to generate a test vector containing a sequence of repeatable data bits used in the function test of the NVM module420a-n. The data generator may comprise a pseudo RNG and a seed register in one embodiment. The address generator436is configured to generate a starting address and an end address, such that the function test may be conducted in only a portion of the NVM module under test420a-n. The comparator442, the comparison status storage space444and the test result indicator446are the same as or substantially similar to those of the NVM test module330a-ndescribed above inFIG. 3B.

Due to multiple NVM modules420a-nbeing tested within one NVM tester410, the NVM module detector450is configured to determine which slots are occupied by NVM modules. The detector450comprises detection logic448and resource allocation logic449.

Referring now toFIGS. 5A-C, there is shown a flowchart illustrating an exemplary process500of the function test used in the exemplary process100ofFIGS. 1A-Bin accordance with one embodiment of the present invention. The process500is preferably understood in conjunction with other figures especiallyFIGS. 1A-B,3A-B,4A-B, and8A-B. The process500starts by receiving a command at each of the NVM modules320a-nunder test from a main test platform302(i.e., referred to hereinafter as “host” inFIGS. 5A-C) to check the manufacturer's identification (ID) of the respective one of the NVM modules320a-nunder test at502. Next, at504, the ID is retrieving or read using a predetermined relatively slow timing cycles in all of the NVM data channels and all of the NVM chip selections. For example, address ‘90h’ of a flash memory chip is generally reserved for storing such ID.

At506, the process500then sends the retrieved ID back to the host302to obtain specific characteristics corresponding to the ID from a database stored on the host302. For example, ID may show the NVM module320a-nunder test containing a particular manufacturer's flash memory chip. The entry corresponding to the ID in the database that contains the particulars. Next, at508, the particular timing parameter corresponding to the ID is received in the timing register of the NVM module interface. Using the appropriate timing parameter, the NVM module320a-ncan receive a boot code from the host302at510, for example, clock rate, number of timing cycles, etc.

With the boot code installed, the NVM module320a-nthen scans all blocks of the NVM to build a bad block list at512. Next at decision514, it is determined whether the number of the bad blocks exceeds a predefined threshold. If ‘yes’, an error message is sent to the host302indicating a defective NVM module320a-nat516. Otherwise at522, the NVM module320a-nreceives a customized run code from the host302. With both the boot code and run code installed, the NVM module320a-nperforms a self check with a predefined data pattern at524. At decision526, it is determined if the NVM module320a-nhas passed the self check. If ‘no’, the NVM module320a-nsends an error message to the host302to indicate the module is defective at532. Otherwise, the process500erases all of the data blocks in the NVM module at528. Then, the NVM module320a-nis formatted with an operating system image (e.g., master boot record, file allocation table, etc.) at530.

After formatting is done, the NVM module320a-nis finally ready for receiving data from a user. The function test in the manufacturing and testing process100ofFIGS. 1A-Bis a test to simulate usage of the NVM module320a-nby such user. At542, each of the NVM test modules330a-nreceives a function test command from the host302. Accordingly, each of the test modules330a-ncreates a test vector at544. The test vector is repeatable deterministic sequence of data bits. In one embodiment, the test vector comprises a fixed pattern such as an exemplary sequence shown inFIG. 8A. In another embodiment, the test vector comprises a random pattern such as the exemplary sequence shown inFIG. 8B. The fixed pattern may be generated by the test module330a-nbased on the function test command, for example, a particular command may trigger a test vector containing alternating zeros and ones. The random pattern is generated by a pseudo random number generator with a seed. The seed may be determined by a particular command such that the random pattern can be reproduced with the same seed.

Next, at546, a section of the NVM module320a-nunder test is defined with a starting and an end address. The NVM module320a-nmay be divided into at least one section. At548, the test vector is written to the defined section of the NVM module320a-n. Then the stored values in the section is retrieved or read back to the NVM test module320a-nat550. The retrieved values are compared with the known test vector at552. The known test vector may be regenerated such that there is no requirement of storing the known test vector. At decision554, it is determined whether the NVM module320a-npasses the comparison. If ‘no’ an error message is sent to the host302at556indicating the module is defective (e.g., a red indictor light is turned on). Otherwise, the process500moves to another decision558to determine whether there is another section to conduct further function test. If ‘yes’, the process500moves back to544to repeat the steps described in process500herein. Otherwise the process500ends and shows the NVM module320a-nunder test has passed the function test (e.g., a green indicator light is turned on).

FIGS. 6A-Bcollectively is a flowchart illustrating an exemplary process600of boot code during a power on or reset in a NVM device, according to an embodiment of the present invention. The process600starts when the NVM device receives a ‘power_on_reset’ signal at602. In response to the signal, the NVM device fetches the boot code from first fixed address. Next a self check is performed at decision604. If ‘failed’, the process600sets a warning message at611. Otherwise a NVM connection check is performed at decision606. Similarly if ‘failed’, the process500sets the warning message at611. Otherwise the process600moves to another decision608, it is determined whether the capacity matches the predefined number. The warning message is set if ‘failed’. If ‘pass’, the process600moves to decision610to determine whether embedded parameters are matched with the predefined values. If ‘pass’, the NVM device scans spare area of the NVM to retrieve logical block address and bad block (BB) information at612. A logical-to-physical block address look up table (LUT) is built using the retrieved information at614.

Next, the process600moves to decision622to determine if there is any abnormal logical block address (LBA). If ‘no’, the NVM device checks volume and generates free and occupied statistics at624and the process600ends. Otherwise, if ‘yes’, the process600moves to another decision626, it is determined whether the LBA is duplicated. If ‘yes’, a warning message is set at630. Otherwise if ‘no’, another decision628determines whether the LBA is outside of a predetermined range. If ‘no’, a warning message is set at630. Otherwise, the duplicated LBA is erased for reuse.

FIGS. 7A-Bcollectively shows various parameters may be included in testing of NVM modules according one embodiment of the present invention.FIG. 7Ashows parameters used in public area702, secure area704and ‘autorun’ area706of a NVM module320a-nunder test. Vendor area708and parameters710are shown inFIG. 7B.

FIG. 8Ais a diagram showing a fixed pattern sequence of data bits used in a test vector andFIG. 8Bis a diagram showing a random sequence of data bits used in a test vector in the function test ofFIGS. 5A-C.

FIG. 9is a block diagram showing salient components of an exemplary NVM module900under the function test shown inFIGS. 5A-C, according to an embodiment of the present invention. The NVM module900comprises a NVM input/output (I/O) interface902, a microcontroller904with coupled random access memory (RAM)908and read-only memory (ROM)906, a logical-to-physical address look up table (LUT)914, a timing controller910, at least one data channel buffer912and at least one NVM chip820. The NVM I/O interface902is configured to transmit data between the NVM module900and a computing device when adapted to. The microcontroller904is configured to control the data transfer operations of the NVM module900. The RAM908is configured as a primary storage space for the microcontroller904and the ROM906is configured to store firmware and other software for the microcontroller904. The LUT914is configured to correlate logical block address with a physical block address in a one-to-one mapping scheme. The at least one data channel buffer912is configured to facilitate data transfer operations to and from the NVM920. The timing controller910is configured to provide appropriate timing to access the NVM based on the manufacturer's ID. The at least one NVM920is configured to hold a boot code921, a run code922and an operating system image (OS)923in the first one or few data blocks. In the reserved area928of the at least one NVM920, a bad block (BB) list is kept. The reserved area928is also configured to perform data block swapping and other NVM related functions.

FIGS. 10A-10Care block diagrams illustrating three electronic environments, in which one embodiment of the present invention may be deployed in three respective exemplary electronic flash memory devices. Shown inFIG. 10Ais a first electronic environment. A first flash memory device1000is adapted to be accessed by a card reader1011that couples to a host computing device1009via an interface bus1013. The first flash memory device1000includes a card body1001a, a processing unit1002, at least one flash memory module1003, a fingerprint sensor1004, a card reader input/output (I/O) interface circuit1005, an optional display unit1006, an optional power source (e.g., battery)1007, and an optional function key set1008. The host computing device1009may include, but not be limited to, a desktop computer, a laptop computer, a mother board of a personal computer, a cellular phone, a digital camera, a digital camcorder, a personal multimedia player.

The card body1001ais configured for providing electrical and mechanical connection for the processing unit1002, the flash memory module1003, the I/O interface circuit1005, and all of the optional components. The card body1001amay comprise a printed circuit board (PCB) or an equivalent substrate such that all of the components as integrated circuits may be mounted thereon. The substrate may be manufactured using surface mount technology (SMT) or chip on board (COB) technology.

The processing unit1002and the I/O interface circuit1005are collectively configured to provide various control functions (e.g., data read, write and erase transactions) of the flash memory module1003. The processing unit1002may also be a standalone microprocessor or microcontroller, for example, an 8051, 8052, or 80286 Intel® microprocessor, or ARM®, MIPS® or other equivalent digital signal processor. The processing unit1002and the I/O interface circuit1005may be made in a single integrated circuit, for application specific integrated circuit (ASIC).

The at least one flash memory module1003may comprise one or more flash memory chips or integrated circuits. The flash memory chips may be single-level cell (SLC) or multi-level cell (MLC) based. In SLC flash memory, each cell holds one bit of information, while more than one bit (e.g., 2, 4 or more bits) are stored in a MLC flash memory cell.

The fingerprint sensor1004is mounted on the card body1001a, and is adapted to scan a fingerprint of a user of the first electronic flash memory device1000to generate fingerprint scan data. Details of the fingerprint sensor1004are shown and described in a co-inventor's U.S. Pat. No. 7,257,714, entitled “Electronic Data Storage Medium with Fingerprint Verification Capability” issued on Aug. 14, 2007, the entire content of which is incorporated herein by reference.

The input/output interface circuit1005is mounted on the card body1001a, and can be activated so as to establish communication with the host computing device1009by way of an appropriate socket via an interface bus1013. The input/output interface circuit1005may include circuits and control logic associated with a Universal Serial Bus (USB) interface structure that is connectable to an associated socket connected to or mounted on the host computing device1009. The input/output interface circuit1005may also be other interfaces including, but not limited to, Secure Digital (SD) interface circuit, Micro SD interface circuit, Multi-Media Card (MMC) interface circuit, Compact Flash (CF) interface circuit, Memory Stick (MS) interface circuit, PCI-Express interface circuit, a Integrated Drive Electronics (IDE) interface circuit, Serial Advanced Technology Attachment (SATA) interface circuit, external SATA, Radio Frequency Identification (RFID) interface circuit, fiber channel interface circuit, optical connection interface circuit.

The processing unit1002is controlled by a software program module (e.g., a firmware (FW)), which may be stored partially in a ROM (not shown) such that processing unit1002is operable selectively in: (1) a data programming or write mode, where the processing unit1002activates the input/output interface circuit1005to receive data from the host computing device1009and/or the fingerprint reference data from fingerprint sensor1004under the control of the host computing device1009, and store the data and/or the fingerprint reference data in the flash memory module1003; (2) a data retrieving or read mode, where the processing unit1002activates the input/output interface circuit1005to transmit data stored in the flash memory module1003to the host computing device1009; or (3) a data resetting or erasing mode, where data in stale data blocks are erased or reset from the flash memory module1003. In operation, host computing device1009sends write and read data transfer requests to the first flash memory device1000via the interface bus1013, then the input/output interface circuit1005to the processing unit1002, which in turn utilizes a flash memory controller (not shown or embedded in the processing unit) to read from or write to the associated at least one flash memory module1003. In one embodiment, for further security protection, the processing unit1002automatically initiates an operation of the data resetting mode upon detecting a predefined time period has elapsed since the last authorized access of the data stored in the flash memory module1003.

The optional power source1007is mounted on the card body1001a, and is connected to the processing unit1002and other associated units on card body1001afor supplying electrical power (to all card functions) thereto. The optional function key set1008, which is also mounted on the card body1001a, is connected to the processing unit1002, and is operable so as to initiate operation of processing unit1002in a selected one of the programming, data retrieving and data resetting modes. The function key set1008may be operable to provide an input password to the processing unit1002. The processing unit1002compares the input password with the reference password stored in the flash memory module1003, and initiates authorized operation of the first flash memory device1000upon verifying that the input password corresponds with the reference password. The optional display unit1006is mounted on the card body1001a, and is connected to and controlled by the processing unit1002for displaying data exchanged with the host computing device1009.

Shown inFIG. 10B, a second electronic flash memory device1040includes a card body1001bwith a processing unit1002, an I/O interface circuit1005and at least one flash memory module1003mounted thereon. Similar to the first flash memory device, the second flash memory device1040couples to the host computing device1009via the interface bus1013.

FIG. 10Cshows a third electronic flash memory device1080couples to the host computing device1009via the interface bus1013. The third flash memory device1080comprises a card body1001cwith an integrated processing unit1082and at least one flash memory module1003mounted thereon. The integrated processing unit1082(e.g., System on a Chip (SoC)) includes an I/O interface1085and a flash memory controller1081. The I/O interface1085is configured to transmit data, control signals and power between the computing device1009and the flash memory device1080. The flash memory controller1081is configured to manage data transfer operations from and to the at least one flash memory module1003.

Although the present invention has been described with reference to specific embodiments thereof, these embodiments are merely illustrative, and not restrictive of, the present invention. Various modifications or changes to the specifically disclosed exemplary embodiments will be suggested to persons skilled in the art. For example, whereas the main testing platform302has been described and shown in the exemplary process500of function test, the NVM tester402may also be used to accomplish the same. Additionally, whereas the test vector with a sequence of a fixed pattern has been shown and described as alternative zeros and ones. Other combinations may be used, for example, all zeros or all ones. Furthermore, whereas a USB bus has been described and shown in the NVM tester, other external interface may be used to achieve the same purpose. In summary, the scope of the invention should not be restricted to the specific exemplary embodiments disclosed herein, and all modifications that are readily suggested to those of ordinary skill in the art should be included within the spirit and purview of this application and scope of the appended claims.