Method of fabricating non-volatile memory device having small contact and related devices

A sacrificial pattern is formed to partially cover the pipe-shaped electrode. A sacrificial spacer is formed on a lateral surface of the sacrificial pattern. The sacrificial spacer extends across the pipe-shaped electrode. The sacrificial spacer has a first side and a second side opposite the first side. The sacrificial pattern is removed to expose the pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer. The pipe-shaped electrode exposed on both sides of the sacrificial spacer may be primarily trimmed. The pipe-shaped electrode is retained under the sacrificial spacer to form a first portion, and a second portion facing the first portion. The second portion of the pipe-shaped electrode is secondarily trimmed. The sacrificial spacer is removed to expose the first portion of the pipe-shaped electrode. A data storage plug is formed on the first portion of the pipe-shaped electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0107159 filed on Oct. 19, 2011, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Embodiments of the inventive concept relate to a method of fabricating a non-volatile memory device and related devices.

2. Description of Related Art

Research has been conducted on various approaches for reducing a program current in a non-volatile memory device, such as a phase-change random access memory (PRAM).

SUMMARY

Embodiments of the inventive concepts provide a method of fabricating a non-volatile memory device, which may shorten a contact area between a lower electrode and a data storage plug, and reduce a program current.

Other embodiments of the inventive concepts provide a non-volatile memory device, which may shorten a contact area between a lower electrode and a data storage plug, and reduce a program current.

Aspects of the inventive concepts should not be limited by the above description, and other unmentioned aspects will be clearly understood by one of ordinary skill in the art from example embodiments described herein.

In accordance with an aspect of the inventive concepts, a method of fabricating a non-volatile memory device is provided. The method includes forming a pipe-shaped electrode on a substrate having a word line. A sacrificial pattern is formed to partially cover the pipe-shaped electrode. A sacrificial spacer is formed on a lateral surface of the sacrificial pattern. The sacrificial spacer extends across the pipe-shaped electrode. The sacrificial spacer has a first side and a second side opposite the first side. The sacrificial pattern is removed to expose the pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer. The pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer is primarily trimmed. The pipe-shaped electrode is retained under the sacrificial spacer to form a first portion, and a second portion facing the first portion. The second portion of the pipe-shaped electrode is secondarily trimmed. The sacrificial spacer is removed to expose the first portion of the pipe-shaped electrode. A data storage plug is formed on the first portion of the pipe-shaped electrode.

In an embodiment, the formation of the sacrificial spacer includes forming a spacer layer to cover a top surface of the substrate having the sacrificial pattern, and removing the spacer layer until the pipe-shaped electrode is exposed. In an embodiment, the formation of the spacer layer is performed using an atomic layer deposition (ALD) method.

In an embodiment, a third portion and a fourth portion of the pipe-shaped electrode may be formed in response to the primary trimming of the pipe-shaped electrode. The third and fourth portions are lower than a top end of the first portion, and higher than the second portion.

In an embodiment, at least one lateral surface of the data storage plug is self-aligned with the first portion of the pipe-shaped electrode.

In an embodiment, one lateral surface of the data storage plug is vertically aligned with one lateral surface of the first portion of the pipe-shaped electrode.

In an embodiment, the first portion of the pipe-shaped electrode has a substantially same horizontal width as the data storage plug.

In an embodiment, before forming the sacrificial pattern, the method further includes forming a core pattern to fill the inside of the pipe-shaped electrode. In an embodiment, before forming the data storage plug, the method further includes recessing the first portion of the pipe-shaped electrode. In an embodiment, a bottom end of the data storage plug extends lower than a top end of the core pattern. In an embodiment, the data storage plug contacts a lateral surface of the core pattern.

In accordance with another aspect of the inventive concepts, a method of fabricating a non-volatile memory device is provided. The method includes forming a molding layer on a substrate. A plurality of contact holes are formed in the molding layer. Lower electrodes are formed on sidewalls of the contact holes. A plurality core patterns are formed. Each core pattern fills a contact hole of the contact holes, respectively. Sacrificial spacers are formed that extend across the contact holes and are parallel to one another. The lower electrodes, the core patterns, and the molding layer are primarily trimmed in a first direction using the sacrificial spacers as a mask to form a plurality of first grooves. Here, first portions of the lower electrodes and second portions facing the first portions are retained under the sacrificial spacers. First insulating patterns are formed in the first grooves. The sacrificial spacers, the first insulating patterns, the second portions of the lower electrodes, the core patterns, and the molding layer are secondarily trimmed in a second direction orthogonal to the first direction to form a plurality of second grooves. Second insulating patterns are formed in the second grooves. The sacrificial spacers are removed to form trenches exposing the first portions of the lower electrodes. Data storage plugs are formed within the trenches. The data storage plugs are respectively formed between the first insulating patterns and the second insulating patterns.

In an embodiment, a horizontal width of the first portions of the lower electrodes is less than half a diameter of the contact holes. In an embodiment, the horizontal width of the first portions of the lower electrodes is between 1 nm and 10 nm.

In an embodiment, the method further comprises, before forming the lower electrodes, forming a plurality of diodes in the contact holes, and forming metal silicide patterns on the diodes. In an embodiment, the lower electrodes are self-aligned on the diodes.

In accordance with another aspect of the inventive concepts, a non-volatile memory device is provided. The non-volatile memory device comprises a substrate, a word line at the substrate, and a lower electrode on the substrate. The lower electrode has a first portion extending in a vertical direction relative to a horizontal direction of extension of the substrate from a first side of the lower electrode and a second portion extending in the vertical direction from a second side of the lower electrode opposite the first side. The first portion has a greater length than the second portion. A data storage plug is on the first portion of the lower electrode.

In an embodiment, the non-volatile memory device further comprises a diode between the lower electrode and the word line. The lower electrode is self-aligned on the diode.

In an embodiment, the non-volatile memory device further comprises an upper electrode on the diode.

In an embodiment, the lower electrode has a third portion and a fourth portion opposite the fourth portion, the third and fourth portions having top surfaces that are lower than a top surface of the first portion, and higher than a top surface of the second portion.

In an embodiment, the non-volatile memory device further comprises a core pattern. The first and second portions are positioned along sidewalls of the core pattern.

Specific particulars of other embodiments are included in detailed descriptions and drawings.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. This inventive concept may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of the inventive concept to one skilled in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate or intervening layers may also be present. In addition, like numbers refer to like element throughout.

Spatially relative terms, such as “top end”, “bottom end”, “top surface”, “bottom surface”, “upper”, and “lower”, and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1Ais a perspective view of main components of a non-volatile memory device according to embodiments of the inventive concept, andFIG. 1Bis an exploded perspective view of the memory device ofFIG. 1A.FIG. 2is a layout illustrating the non-volatile memory device shown inFIGS. 1A and 1B.FIG. 3Ais a cross-sectional view taken along line I-I′ ofFIG. 2.FIG. 3Bis a cross-sectional view taken along line II-II′ ofFIG. 2.FIG. 3Cis a cross-sectional view taken along line III-III′ ofFIG. 2.

Referring toFIGS. 1A and 1B, a diode33may be formed on a word line25. The diode33may include a first semiconductor pattern31and a second semiconductor pattern32stacked sequentially. A metal suicide pattern35may be formed on the diode33. A lower electrode41may be formed on the metal silicide pattern35. A core pattern48may be formed within the lower electrode41. A data storage plug63may be formed on the lower electrode41. An upper electrode65may be formed on the data storage plug63. A bit line75may be formed on the upper electrode65. The bit line75may include a barrier metal layer71, a seed layer72, and a conductive layer73.

The metal silicide pattern35and the lower electrode41may be self-aligned on the diode33. A first portion41A of the lower electrode41may protrude from the main body of the lower electrode41, for example, in an upward direction. The data storage plug63may be self-aligned with respect to the first portion41A of the lower electrode41. A lateral surface of the data storage plug63may be vertically aligned with a protruding surface of the first portion41A of the lower electrode41.

Referring toFIG. 2, word lines25may be formed in a cell array region of the non-volatile memory device and aligned parallel to one another. One or more upper electrodes65may be formed to cross over the word lines25. One or more bit lines75may be formed on the upper electrodes65. Diodes33, lower electrodes41, and data storage plugs63may be formed at intersections between the word lines25and the bit lines75.

Referring toFIGS. 2 and 3Athrough3C, an isolation layer23defining one or more active regions22may be formed at predetermined regions of a substrate21. Word lines25may be formed within the active regions22. A molding layer29may be formed on the word lines25and the isolation layer23. Contact holes29H may be formed through the molding layer29. A first semiconductor pattern31, a second semiconductor pattern32, and a metal silicide pattern35may be sequentially stacked within each of the contact holes29H. The first and second semiconductor patterns31and32may constitute the diode33. The lower electrodes41may be formed on the metal silicide patterns35. Core patterns48may be formed within the lower electrodes41.

Data storage plugs63may be formed on first portions41A of the lower electrodes41. First insulating patterns55and second insulating patterns61may be formed on both sides of the first portions41A and the data storage plugs63. The first insulating patterns55may intersect the second insulating patterns61. The upper electrodes65may be formed on the data storage plugs63. An upper insulating layer67may be formed on the first insulating patterns55, the second insulating patterns61, and the upper electrodes65. The bit lines75may be formed to penetrate the upper insulating layer67and contact the upper electrodes65. Each of the bit lines75may include the barrier metal layer71, the seed layer72, and the conductive layer73stacked sequentially.

Each of the lower electrodes41may include the first portion41A, a recessed second portion41E disposed opposite the first portion41A, and a third portion41C and a fourth portion41D disposed opposite each other on both sides of the first portion41A and the recessed second portion41E. The third and fourth portions41C and41D may be formed lower than a top end of the first portion41A. The recessed second portion41E may be formed at a lower region than the top surfaces of the third and fourth portions41C and41D. Lateral surfaces of the data storage plugs63may be vertically aligned with lateral surfaces of the first portions41as shown inFIG. 3B.

The second insulating patterns61may have bar shapes parallel to one another. The second insulating patterns61may partially cross the lower electrodes41, the core patterns48, and the molding layer29. Bottom surfaces of the second insulating patterns61may be formed at lower levels than bottom surfaces of the first insulating patterns55. The bottom portions of the second insulating patterns61may contact the recessed second portions41E of the lower electrodes41, the core patterns48, and the molding layer29, respectively. Lateral surfaces of the second insulating patterns61may contact the data storage plugs63, the core patterns48, the molding layer29, and the first insulating patterns55, respectively.

The first insulating patterns55may cross the second insulating patterns61at right angles. The first insulating patterns55may at least partially cross the lower electrodes41, the core patterns48, and the molding layer29. Bottoms of the first insulating patterns55may be formed lower than top ends of the first portions41A of the lower electrodes41. The bottoms of the first insulating patterns55may contact the third and fourth portions41C and41D of the lower electrodes41, the core patterns48, and the molding layer29. Lateral surfaces of the first insulating patterns55may contact the data storage plugs63, the core patterns48, the first portions41A of the lower electrodes41, and the second insulating patterns61. The first portions41A and the data storage plugs63may be vertically aligned between the first insulating patterns55.

The bottom of the data storage plug63may contact top ends of the first portion41A of the lower electrode41, the core pattern48, and the molding layer29, respectively. The top end of the first portion41A may be formed at substantially the same level as the top ends of the core pattern48and/or the molding layer29.

Referring toFIGS. 4A and 4B, a recess region41R may be formed on first portions41A of lower electrodes41. That is, the first portions41A of the lower electrodes41may be recessed lower than top ends of core patterns48and a molding layer29. Data storage plugs63A may be formed on the first portions41A of the lower electrodes41. The data storage plugs63A may fill the recess region41R and contact the first portions41A.

Referring toFIGS. 5A and 5B, bottoms of second insulating patterns61A may be formed at higher levels than bottoms of the first insulating patterns55. In the first and second embodiments, the bottoms of the second insulating patterns61A may be formed at lower levels than the bottoms of the first insulating patterns55. The bottoms of the second insulating patterns61A may contact recessed second portions41E of the lower electrodes41, the core patterns48, and the molding layer29. Lateral surfaces of the second insulating patterns61A may contact the data storage plugs63A, the core patterns48, the molding layer29, and the first insulating patterns55. Top ends of the recessed second portions41E of the lower electrodes41may be formed at higher levels than third and fourth portions41C and41D of the lower electrodes41, and at lower levels than top ends of the first portions41A.

FIGS. 6A through 19Aare cross-sectional views taken along line I-I′ ofFIG. 2, illustrating a method of fabricating a non-volatile memory device according to embodiments of the inventive concept.FIGS. 6B through 19Bare cross-sectional views taken along line II-II′ ofFIG. 2.FIGS. 10C through 19Care cross-sectional views taken along line III-III′ ofFIG. 2. The layout and cross-sectional views ofFIGS. 2 and 6Athrough19C may correspond to a cell region of a phase-change memory device.

Referring toFIGS. 2,6A, and6B, an isolation layer23defining active regions22may be formed in predetermined regions of a substrate21. Word lines25may be formed in the active regions22. The word lines25may be parallel to one another. The isolation layer23may be formed between the word lines25.

The substrate21may be a semiconductor substrate, such as a single crystalline silicon wafer or a silicon-on-insulator (SOI) wafer. Hereinafter, it will be assumed that the substrate21is a silicon wafer containing p-type impurity ions. The isolation layer23may be formed using a shallow trench isolation (STI) technique. The isolation layer23may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The word lines25may be formed by implanting n-type impurity ions into the active regions22.

In other embodiments, the word lines25may be conductive patterns formed on the substrate21, a detailed description thereof will be omitted for brevity.

Referring toFIGS. 2,7A, and7B, a molding layer29may be formed on the substrate21having the word lines25. Contact holes29H may be formed to penetrate the molding layer29and expose the word lines25. The contact holes29H may be aligned at predetermined intervals along the word lines25. The contact holes29H may be separated from one another by a predetermined distance.

The molding layer29may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The molding layer29may cover the word lines25and the isolation layer23. Although an etch stop layer may be further formed between the word lines25and the molding layer29, a detailed description thereof will be omitted for brevity. The contact holes29H may be formed using a patterning technique. For example, the formation of the contact holes29H may be performed using photolithography and anisotropic etching processes. Each of the contact holes29H may have one of various shapes, such as a circular shape, a tetragonal shape, or a tetragonal shape with round corners. Each of the contact holes29H may have a diameter less than a width of the word lines25.

Referring toFIGS. 2 and 8Aand8B, a first semiconductor pattern31and a second semiconductor pattern32may be sequentially formed in each of the contact holes29H. The first and second semiconductor patterns31and32may constitute a diode33. The diode33may be formed such that a top surface of the diode33is at a lower level than a top surface of the molding layer29. The diode33may serve as a switching element.

The first and second semiconductor patterns31and32may be formed in the contact holes29H using a selective epitaxial growth (SEG) technique. The first semiconductor pattern31may be formed between the second semiconductor pattern32and the word lines25. The first semiconductor pattern31may include a silicon layer containing n-type impurity ions. The second semiconductor pattern32may include a silicon layer containing p-type impurity ions. In other embodiments, the first and second semiconductor patterns31and32are stacked in a reverse order, i.e., the first semiconductor pattern31is formed on the second semiconductor pattern32.

Referring toFIGS. 2 and 9Aand9B, a metal silicide pattern35may be formed on the diode33. The metal silicide pattern35may be formed in the contact holes29H to contact the second semiconductor pattern32. A top surface of the metal silicide pattern35may be formed at a lower level than the top surface of the molding layer29. Sidewalls of the contact holes29H may be exposed above the metal silicide pattern35. The metal silicide pattern35may include cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), titanium silicide (TiSi), or tantalum silicide (TaSi). For example, the metal silicide pattern35may include a CoSi layer.

Referring toFIGS. 2 and 10Athrough10C, a lower electrode layer41L may be formed on the metal silicide pattern35to cover sidewalls of the contact holes29H, and may also cover a top surface of the molding layer29and the metal silicide pattern in the contact hole29H. A core layer48L may be formed on the lower electrode layer41L. The core layer34and the lower electrode layer41L may be planarized until the molding layer29is exposed, thereby forming lower electrodes41and core patterns48. Each of the lower electrodes41may have a cup shape or a pipe shape, for example, shown inFIG. 3A. The lower electrode41may be self-aligned on the diode33.

The lower electrodes41may contact the metal silicide pattern35and cover the sidewalls of the contact holes29H. The core pattern48may completely fill the contact holes29H. The planarization of the core layer48L and the lower electrode layer41L may include a chemical mechanical polishing (CMP) process and/or an etchback process. As a result, top surfaces of the lower electrodes41, the core patterns48, and the molding layer29may extend along a substantially same plane surface.

The lower electrodes41may include titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbon nitride (TiCN), titanium silicon nitride (TiSiN), titanium oxynitride (TiON), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), C, CN, CoSi, CoSiN, W, WN, WSi, WSiN, Ni, or a combination thereof. The core patterns48may include a material having a higher electric resistance than the lower electrodes41. Also, the core patterns48may include a different material from the molding layer29. For example, the molding layer29may include silicon oxide, while the core patterns48may include silicon nitride.

Referring toFIGS. 2 and 11Athrough11C, a sacrificial pattern52may be formed on the molding layer29. The sacrificial pattern52may have a bar shape. The sacrificial pattern52may cover a surface of the molding layer29between the contact holes29H and extend across at least a portion of the contact holes29H. The sacrificial pattern52may also at least partially cover the top surfaces of the lower electrodes41and the core patterns48.

The sacrificial pattern52may be formed using a thin-film forming process and a patterning process. The patterning process may include a photolithography process. The sacrificial pattern52may include a material having an etch selectivity with respect to the core pattern48and the molding layer29. For example, the sacrificial pattern52may include a spin-on-hardmask (SOH).

Referring toFIGS. 2 and 12Athrough12C, a spacer layer53L may be formed on the surface of the substrate21. The spacer layer53L may cover lateral surfaces of the sacrificial pattern52and partially cover the lower electrodes41and the core patterns48. The spacer layer53L may be anisotropically etched until the lower electrodes41are exposed, thereby forming sacrificial spacers53on the lateral surfaces of the sacrificial pattern52.

The sacrificial spacers53may be aligned across the centers of the contact holes29H. The sacrificial patterns53may extend in a first direction. Accordingly, the sacrificial spacers53may cross the top surfaces of the lower electrodes41and the core patterns48in the first direction. Each of the lower electrodes41may include a first portion41A corresponding to a first lateral surface of the lower electrode41and a second portion41B corresponding to a second lateral surface of the lower electrode41opposite the first portion41A. At least one of the first and second portions41A and41B may be covered with a sacrificial spacer53.

The sacrificial spacers53may include a material having an etch selectivity with respect to the sacrificial pattern52, the core patterns48, and the molding layer29. For example, the sacrificial spacers53may include atomic-layer-deposition (ALD) oxide.

A horizontal width of the sacrificial spacers53may depend on a deposited thickness of the spacer layer53L. The ALD oxide obtained using an ALD method enables easy control of a deposition of the spacer layer53L, thereby establishing the thickness of the spacer layer53L. Thus, the ALD method can control the thickness of the sacrificial spacers53to have a horizontal width that is about 10 nm or less. In an embodiment, the sacrificial spacers53are formed having a horizontal width between 1 nm and 10 nm.

Referring toFIGS. 2 and 13Athrough13C, the sacrificial pattern52may be removed to expose the top surfaces of the molding layer29, the lower electrodes41, and the core patterns48on both sides of each of the sacrificial spacers53. Subsequently, first grooves43G may be formed on both sides of each of the sacrificial spacers53. The first grooves43G may be formed by trimming the molding layer29, the lower electrodes41, and the core patterns48, referred to as primary trimming, using the sacrificial patterns53as an etch mask. The primary trimming of the molding layer29, the lower electrodes41, and the core patterns48may include partially removing exposed portions of the core patterns48. Since the primary trimming process uses the sacrificial spacers53extending in the first direction as an etch mask, the primary trimming process may be defined as being performed in the first direction. The primary trimming of the molding layer29, the lower electrodes41, and the core patterns48may be performed using an anisotropic etching process. As a result, the first and second portions41A and41B of the lower electrodes41may be retained under the sacrificial spacers53. Also, the core patterns48and the molding layer29may be retained under the sacrificial spacers53.

Third portions41C of the lower electrodes41and fourth portions41D facing the third portions41C may be exposed by bottoms of the first grooves43G. The sacrificial spacers53, the first portions41A, the second portions41B, the core patterns48, and the molding layer29may be exposed by sidewalls of the first grooves43G. The first and second portions41A and41B may be vertically aligned under the sacrificial spacers53. The first and second portions41A and41B may be self-aligned with the sacrificial spacers53. A horizontal width of the first and second portions41A and41B may be substantially the same as the horizontal width of the sacrificial spacers53. Top surfaces of the first and second portions41A and41B may be retained at substantially the same level as the top surfaces of the core patterns48and the molding layer29. The third and fourth portions41C and41D of the lower electrodes41may be retained having lower levels than top ends of the first and second portions41A and41B.

Referring toFIGS. 2 and 14Athrough14C, a first insulating layer55L may be formed to fill the first grooves43G and cover the sacrificial spacers53. The first insulating layer55L may be planarized until the sacrificial spacers53are exposed, thereby forming first insulating patterns55in the first grooves43G. The first insulating patterns55may include a material having an etch selectivity with respect to the sacrificial spacers53. For example, the first insulating patterns55may include silicon nitride.

Referring toFIGS. 2 and 15Athrough15C, a mask pattern57may be formed on the sacrificial spacers53and the first insulating patterns55. The mask pattern57may cross the sacrificial spacers53and the first insulating patterns55, for example, by extending in a second direction orthogonal to first direction. Accordingly, the mask pattern57may cross the sacrificial spacers53and the first insulating patterns55at right angles. The mask pattern57may cover the first portions41A of the lower electrodes41. Also, the mask pattern57may partially cover the core patterns48and the molding layer29adjacent to the first portion41A. The mask pattern57may be formed using a photolithography process.

The sacrificial spacers53, the first insulating patterns55, the second portions41B of the lower electrodes41, the core patterns48adjacent to the second portions41B, and the molding layer29adjacent to the second portions41B may be secondarily trimmed using the mask pattern57as an etch mask, thereby forming second grooves59. Since the second trimming process uses the mask pattern57extending in the second direction as an etch mask, the second trimming process may be defined as being performed in the second direction. The secondary trimming of the sacrificial spacers53, the first insulating patterns55, the second portions41B, the core patterns48, and the molding layer29may be performed using an anisotropic etching process. As a result, the second portions41B of the lower electrodes41may be partially removed, forming recessed second portions41E from the second portions41B on bottoms of the second grooves59. The second grooves59may intersect the first grooves43G in right angles.

The sacrificial spacers53, the first insulating patterns55, the core patterns48, and the molding layer29may be exposed by sidewalls of the second grooves59. Bottoms of the second grooves59may be formed at a different level from bottoms of the first insulating patterns55. For example, the bottoms of the second grooves59may be formed at lower levels than the bottoms of the first insulating patterns55. In this case, top ends of the recessed second portions41E may be formed at lower levels than top ends of the third and fourth portions41C and41D. In other embodiments, the bottoms of the second grooves59are formed at higher levels than the bottoms of the first insulating patterns55.

Referring toFIGS. 2 and 16Athrough16C, second insulating patterns61may be formed to fill the second grooves59. The formation of the second insulating patterns61may be performed using a thin-film forming process and a planarization process. Top surfaces of the second insulating patterns61, the sacrificial spacers53, and the first insulating patterns55may be exposed on substantially the same plane surface. The second insulating patterns61may include a material having an etch selectivity with respect to the sacrificial spacers53. For example, the second insulating patterns61may include silicon nitride.

The mask pattern57may be removed during the formation of the second insulating patterns61. In another embodiment, the mask pattern57may be removed before formation of the second insulating patterns61.

Referring toFIGS. 2 and 17Athrough17C, the sacrificial spacers53may be removed to form trenches53H. The first portions41A of the lower electrodes41, the core patterns48adjacent to the first portions41A, and the molding layer29adjacent to the first portions41A may be exposed by bottoms of the trenches53H. Lateral surfaces of the first and second insulating patterns55and61, respectively, may be exposed by sidewalls of the trenches53H.

Referring toFIGS. 2 and 18Athrough18C, data storage plugs63may fill the trenches53H. The formation of the data storage plugs63may be performed using a thin-film forming process and a planarization process. The data storage plugs63may be self-aligned at the first portions41A of the lower electrodes41. At least one lateral surface of the data storage plug63may be vertically aligned on one lateral surface of the first portion41A. Accordingly, a horizontal width of the data storage plug63may be substantially equal to the horizontal width of the first portion41A.

The data storage plugs63may include phase-change plugs, polymer plugs, nanoparticle plugs, or resistance-change plugs. For example, the resistance-change plugs may include a strontium titanate (SrTiO3) layer. Also, when the data storage plugs63include phase-change plugs, the phase-change plugs may include germanium-antimony-telluride (GeSbTe), germanium-antimony-arsenide (GeTeAs), tin-tellurium-tin (SnTeSn), GeTe, SbTe, selenium-tellurium-tin (SeTeSn), GeTeSe, antimony-selenium-bismuth (SbSeBi), GeBiTe, GeTeTi, indium-selenium (InSe), gallium-tellurium-selenium (GaTeSe), or InSbTe. Furthermore, the phase-change plugs may include a material layer obtained by adding one selected from the group consisting of carbon (C), nitrogen (N), Si, and oxygen (O) to one selected from the group consisting of a GeSbTe layer, a GeTeAs layer, a SnTeSn layer, a GeTe layer, a SbTe layer, a SeTeSn layer, a GeTeSe layer, a SbSeBi layer, a GeBiTe layer, a GeTeTi layer, an InSe layer, a GaTeSe layer, and an InSbTe layer.

Referring back toFIGS. 2 and 19Athrough19C, upper electrodes65may be formed on the data storage plugs63. The upper electrodes65may cross the word lines25, and may have a greater width than the data storage plugs63. The upper electrodes65may include W, WN, WSi, WSiN, Ti, TiN, TiAlN, TiCN, TiSiN, TiON, Ta, TaN, TaAlN, TaCN, TaSiN, C, CN, CoSi, CoSiN, Ni, or a combination thereof.

Referring again toFIGS. 2 and 3Athrough3C, an upper insulating layer67may be formed to cover the upper electrodes65. Bit lines75may be formed to penetrate the upper insulating layer67and contact the upper electrodes65. Each of the bit lines75may include a barrier metal layer71, a seed layer72, and a conductive layer73stacked sequentially.

In a method of fabricating a PRAM that depends on a conventional patterning technique, controlling the width of a contact area between a phase-change pattern and a lower electrode to about 15 nm or less may be impossible due to technical limits, such as the resolution limit of a photolithography process. In contrast, in the above-described embodiments of the inventive concept, the width of a contact area between the data storage plug63and the lower electrode41may depend on the horizontal width of the sacrificial spacers53. Also, the diameter of the contact hole29H may depend on the resolution limit of the photolithography process. The horizontal width of the sacrificial spacers53may depend on the deposited thickness of the spacer layer53L. The spacer layer53L may be formed of an ALD oxide using an ALD method, which can permit the thickness of the spacer layer53L to be precisely determined

Thus, the horizontal width of the first portion41A of the lower electrode41may be controlled to be less than half the diameter of the contact hole29H. For example, the first portion41A may be formed to a horizontal width between 1 nm and 10 nm. Furthermore, the horizontal width of the contact area between the data storage plug63and the lower electrode41may also be controlled to be less than half the diameter of the contact hole29H. Also, the contact area between the data storage plug63and the lower electrode41may be formed to a horizontal width between 1 nm and 10 nm. As a result, the contact area between the data storage plug63and the lower electrode41may be greatly reduced as compared with the conventional case.

FIGS. 20A,21,22A, and23A are cross-sectional views taken along line I-I′ ofFIG. 2, illustrating a method of fabricating a non-volatile memory device according to other embodiments of the inventive concept.FIGS. 20B,22B, and23B are cross-sectional views taken along line II-II′ ofFIG. 2.

Referring toFIGS. 2 and 20Aand20B, sacrificial spacers53, first insulating patterns55, lower electrodes41, core patterns48, and a molding layer29may be anisotropically etched, thereby forming second grooves59A. As a result, the lower electrodes41may be partially removed so that recessed second portions41E can be retained on bottoms of the second grooves59A. The second grooves59A may intersect the first insulating patterns55at right angles.

The sacrificial spacers53, the first insulating patterns55, the core patterns48, and the molding layer29may be exposed by sidewalls of the second grooves59A. Bottoms of the second grooves59A may be formed at higher levels than bottoms of the first insulating patterns55. In this case, top ends of the recessed second portions41E may be formed at higher levels than third and fourth portions41C and41D of the lower electrodes41.

Referring toFIGS. 2 and 21, second insulating patterns61A may be formed to fill the second grooves59A. Top surfaces of the second insulating patterns61A, the sacrificial spacers53, and the first insulating patterns55may be exposed on substantially the same planar surface.

Referring toFIGS. 2 and 22Aand22B, the sacrificial spacers53may be removed to form trenches53H. The first portions41A of the lower electrodes41, the core patterns48adjacent to the first portions41A, and the molding layer29adjacent to the first portions41A may be exposed by bottoms of the trenches53H. Lateral surfaces of the first and second insulating patterns55and61A may be exposed by sidewalls of the trenches53H.

Subsequently, the first portions41A of the lower electrodes41may be recessed at lower levels than top ends of the core patterns48and the molding layer29. As a result, recess regions41R may be formed on the first portions41A of the lower electrodes41. The recess regions41R may be formed by etching back the first portions41A of the lower electrodes41.

Referring toFIGS. 2 and 23Aand23B, data storage plugs63A may fill the trenches53H. The data storage plugs63A may fill the recess regions41R and contact the first portions41A of the lower electrodes41. The data storage plugs63A may be self-aligned at the first portions41A of the lower electrodes41. At least one lateral surface of the data storage plugs63A may be vertically aligned on one lateral surface of the first portions41A of the lower electrodes41. As shown inFIG. 23A, a lateral surface of bottom portions of the data storage plugs63A may be in contact with lateral surfaces of the core patterns48.

Referring back toFIGS. 2 and 5Aand5B, upper electrodes65may be formed on the data storage plugs63A. An upper insulating layer67may be formed to cover the upper electrodes65. Bit lines75may be formed to penetrate the upper insulating layer67and contact the upper electrodes65.

FIG. 24is a system block diagram of an electronic device according to another embodiment of the inventive concepts. The electronic device may be a data storage device, for example, a solid-state disk (SSD)1100.

Referring toFIG. 24, the SSD1100may include an interface1113, a controller1115, a non-volatile memory1118, and a buffer memory1119.

The SSD1100may be configured to store information using a semiconductor device. As compared with a hard disk drive (HDD), the SSD1100may operate at high speeds, reduce mechanical delay, failure rate, generation of heat, and noise, and be downscaled and made lightweight. The SSD1100may be widely used for laptop personal computers (laptop PCs), desktop PCs, MP3 players, or portable storage devices.

The controller1115may be formed adjacent to and electrically connected to the interface1113. The controller1115may be a microprocessor (MP) that includes a memory controller and a buffer controller. The non-volatile memory1118may be formed adjacent to and electrically connected to the controller1115. The SSD1100may have a data capacity corresponding to the non-volatile memory1118. The buffer memory1119may be formed adjacent to and electrically connected to the controller1115.

The interface1113may be connected to a host1002and serve to transmit and receive electric signals, such as data. For example, the interface1113may be an apparatus using a standard, such as serial advanced technology attachment (SATA), integrated drive electronics (IDE), small computer system interface (SCSI), and/or a combination thereof. The non-volatile memory1118may be connected to the interface1113through the controller1115. The non-volatile memory1118may store data received through the interface1113. Even if power supplied to the SSD1100is interrupted, the non-volatile memory1118may be characterized by retaining the stored data.

The buffer memory1119may include a volatile memory device. The volatile memory device may be a dynamic random access memory (DRAM) and/or a static random access memory (SRAM). The buffer memory1119may operate at higher speed than the non-volatile memory device1118.

Data processing speed of the interface1113may be higher than operation speed of the non-volatile memory device1118. Here, the buffer memory1119may function to temporarily store data. After data received through the interface1113is temporarily stored in the buffer memory1119through the controller1115, the received data may be permanently stored in the non-volatile memory1118at a data write speed of the non-volatile memory1118. Also, among data stored in the non-volatile memory1118, frequently used data may be previously read and temporarily stored in the buffer memory1119. That is, the buffer memory1119may function to increase the effective operating speed of the SSD1100and reduce an error rate.

The non-volatile memory1118may include a non-volatile memory device, which is about the same as described with reference to the devices illustrated atFIGS. 1A through 23B. For example, the non-volatile memory device1118may include memory cells, which may have about the same configuration as shown inFIG. 1A. In this case, the non-volatile memory1118may exhibit a lower program current than in the conventional case, due to the configurations of the first portion41A of the lower electrode41and the data storage plug63. Thus, electrical properties of the SSD1100may be markedly improved as compared with the conventional case.

FIGS. 25 and 26are respectively a perspective view and system block diagram of an electronic device according to another embodiment of the inventive concept.

Referring toFIG. 25, a non-volatile memory device, which is about the same as described with reference toFIGS. 1A through 23B, may be effectively applied to electronic systems, such as a portable phone1900, a netbook, a laptop computer, or a tablet PC. For instance, the non-volatile memory device, which is about the same as described with reference toFIGS. 1A through 23B, may be mounted on a main board of the portable phone1900. Furthermore, the non-volatile memory device, which is about the same as those described with reference toFIGS. 1A through 23B, may be provided to an expansion device, such as an external memory card, and combined with the portable phone1900.

Referring toFIG. 26, the non-volatile memory device, which is about the same as those described with reference toFIGS. 1A through 23A, may be applied to an electronic system2100. The electronic system2100may include a body2110, an MP unit2120, a power unit2130, a function unit2140, and a display controller unit2150. The body2110may include a mother board including a printed circuit board (PCB). The MP unit2120, the power unit2130, the function unit2140, and the display controller unit2150may be mounted on the body2110. The display unit2160may be disposed inside or outside the body2110. For example, the display unit2160may be disposed on the surface of the body2110and display an image processed by the display controller unit2150.

The power unit2130may receive a predetermined voltage from an external battery (not shown), divide the voltage into required voltage levels, and supply the divided voltages to the MP unit2120, the function unit2140, and the display controller unit2150. The MP unit2120may receive a voltage from the power unit2130and control the function unit2140and the display unit2160. The function unit2140may serve various functions of the electronic system2100. For example, when the electronic system2100is a portable phone, the function unit2140may include several components capable of serving various functions of the portable phone, for example, outputting an image to the display unit2160or outputting a voice to a speaker, by dialing or communicating with an external apparatus2170. When a camera is also mounted, the function unit2140may serve as a camera image processor.

In applied embodiments, when the electronic system2100is connected to a memory card to increase capacity, the function unit2140may be a memory card controller. The function unit2140may transmit/receive signals to/from the external apparatus2170through a wired or wireless communication unit2180. Furthermore, when the electronic system2100requires a universal serial bus (USB) to increase functionality, the function unit2140may serve as an interface controller. In addition, the function unit2140may include a mass storage device.

A non-volatile memory device, which is about the same as described with reference toFIGS. 1A through 23B, may be applied to the function unit2140. For example, the function unit2140may include the substrate21, the lower electrodes41, the data storage plugs63, and the upper electrodes65. The data storage plugs63may be electrically connected to the body2110. In this case, the electronic system2100may exhibit a lower program current than in the conventional case, due to the configurations of the first portion41A of the lower electrode41and the data storage plug63of the embodiments described herein. Thus, electrical properties of the electronic system2100may be markedly improved as compared with the conventional case.

According to embodiments of the inventive concept, a data storage plug contacting a first portion of a lower electrode may be provided. A horizontal width of the first portion of the lower electrode may depend on a horizontal width of a sacrificial spacer. That is, the horizontal width of the first portion may be greatly reduced as compared with the conventional case. As a result, a contact area between the lower electrode and the data storage plug may be greatly reduced as compared with the conventional case. Therefore, a non-volatile memory device that may be driven at a low program current may be embodied.