Synchronizing unit for receiving section of PCM station

Incoming data words organized in a succession of multi-channel frames, arriving at a receiving section of a PCM station, are fed in parallel therewith to a correlation circuit forming part of a synchronizing unit which includes a timer stepped by line-clock pulses extracted from the incoming bit stream. The correlation circuit includes a decoder which recognizes predetermined bits or bit combinations in alignment words A and B respectively appearing at the beginning of alternate frames. Recurrent noncoincidences of either of these alignment words with a corresponding marking pulse emitted by the timer, in a time slot designating the No. 0 channel of a frame, causes a readjustment of the timer and thus a shifting of clock signals emitted thereby to the receiving section. The synchronizing unit, embodied in an integrated-circuit chip, further includes a malfunction detector responsive to signals emitted by the timer and by the decoder of the correlation circuit.

FIELD OF THE INVENTION 
My present invention relates to a PCM station of a telecommunication system 
operating in the time-division-multiplex (TDM) mode and, more 
particularly, to a synchronizing unit controlling the operation of a 
receiving section of such a station, this unit being designed to maintain 
the necessary alignment between the formats of arriving and retransmitted 
messages. 
BACKGROUND OF THE INVENTION 
In commonly owned U.S. Pat. No. 4,081,611 there has been disclosed a PCM 
station of this type, acting under the control of a central processor as a 
coupling network or transit exchange between incoming and outgoing links, 
in which arriving messages are fed to a line unit via a receiving 
interface while departing messages pass through a transmitting interface. 
The line unit comprises a resynchronization circuit including a pair of 
flexible registers forming part of an expandable memory as described in an 
earlier commonly owned U.S. Pat. No. 3,928,725; another expandable memory 
has been disclosed in commonly owned U.S. Pat. No. 4,058,682. 
In such a PCM/TDM system, international regulations call for the 
organization of transmitted data in a succession of frames each consisting 
of a multiplicity of channels accommodating multibit words, usually 8-bit 
bytes; a channel may be defined as a time slot subdivided into as many 
clock cycles or phases as there are bits in a word. For proper 
synchronization of the clocks controlling the operation at the 
transmitting and receiving ends of a signal path, certain alignment words 
are used in an initial channel of each frame which may be referred to as 
the No. 0 channel. These alignment words generally differ from each other 
in odd-numbered or "first" and even-numbered or "second" frames F.sub.A, 
F.sub.B ; thus, they will alternately assume two different forms referred 
to hereinafter as "word A" and "word B". Word "A", appearing in the No. 0 
channel of the recurrent first frame F.sub.A, may have a large number of 
its bits (e.g. 7 out of 8) arranged in an invariable configuration 
facilitating the recognition of that word by a detector at the receiving 
end; word "B", present in the No. 0 channel of the immediately following 
second frame F.sub.B, need only have one particular bit in a predetermined 
time position to serve as a confirmation of alignment. 
Reference may be made to my concurrently filed application Ser. No. 278,064 
for a description of a frame former generating these alignment words in a 
transmitting section of a PCM station. 
OBJECTS OF THE INVENTION 
The general object of my present invention is to provide a relatively 
simple circuit arrangement for initially establishing synchronism between 
the frames of an incoming PCM message and a local timer used in rerouting 
the data words of that message, as well as for re-establishing such 
synchronism after it has been lost for any reason. 
Another object is to provide means for signaling to an associated processor 
the existence or nonexistence of such synchronism. 
It is also an object of my invention to provide means capable of 
determining, for statistical purposes, whether the rate of occurrence of 
loss of synchronism remains within acceptable limits. 
SUMMARY OF THE INVENTION 
A synchronizing unit according to my invention comprises timing means 
stepped by extracted line-clock pulses for generating clock signals that 
are fed to the associated receiving section, the timing means emitting 
first and second marking pulses TA and TB in a time slot assigned to the 
No. 0 channel of each first frame F.sub.A and each second frame F.sub.B, 
respectively. The unit further comprises correlation means including a 
decoder which receives the incoming bit stream and emits respective 
identification pulses AX and BX upon recognizing the alignment words A and 
B; logic circuitry, forming part of the correlation means, generates an 
error signal FAT upon noncoincidence of marking pulses TA and TB with the 
respective identification pulses AX and BX, this logic circuitry feeding 
corrective signals to the timing means for readjusting same to 
re-establish coincidence between respective marking and identification 
pulses. Finally, a malfunction detector connected to the correlation and 
the timing means receives therefrom at least one identification pulse and 
the corresponding marking pulse, the detector including gating means for 
producing an alarm indication AW in the absence of coincidence between 
these pulses. 
According to a more particular feature of my invention, the logic circuitry 
includes first and second counters which are respectively stepped by 
marking pulses TA and TB, a first gate receiving pulses AX and TA for 
emitting a first alignment pulse ATA upon coincidence thereof to clear the 
first counter, a second gate receiving pulses BX and TB for emitting a 
second alignment pulse BTB coincidence thereof to clear the second 
counter, and bistable means such as a JK-type flip-flop settable by either 
of these counters upon attainment of a predetermined count (preferably 
after three steps) for generating the error signal. 
The malfunction detector may include pulse-counting means stepped by a 
noncoincidence pulse from the correlation means and controlled by the 
timing means for generating a high-error-rate signal EPT whenever the 
number of noncoincidence pulses generated within a predetermined 
multiframe interval exceeds a given limit a certain number of times in 
succession. 
The various components of a synchronizing unit according to my invention 
can be readily incorporated in a single integrated-circuit chip.

SPECIFIC DESCRIPTION 
FIG. 1 shows part of a PCM station as described above, specifically a 
receiving section PR thereof to which an incoming data stream is supplied 
on a line 20. A conventional extractor EC emits, on a connection 21, 
line-clock pulses CLK to a timer T and to a correlation circuit AT forming 
part of a synchronizing unit TR which conforms to my present invention and 
is incorporated in a single integrated-circuit chip. That unit further 
includes a malfunction detector RA receiving, in parallel with correlation 
circuit AT, first and second marking pulses TA and TB generated by timer T 
in the last (eighth) phase of a time slot assigned by that timer to the 
No. 0 channel of alternate frames F.sub.A, F.sub.B. Timer T sends locally 
generated clock pulses CK via a lead 22 to receiving section PR, these 
clock pulses being accompanied by special signals generated ahead of 
marking pulses TA and TB to indicate to the station and to an associated 
processor the beginning of each new frame. In the absence of synchronism, 
determined by a recurrent noncoincidence between marking pulses TA, TB and 
corresponding alignment words "A" and "B" formed by the bit stream DE, 
correlation circuit AT emits an error signal FAT to the processor; this 
signal is also sent to timer T together with corrective signals AX, 
Q.sub.2 and Q.sub.3 whose significance will be explained below. 
Malfunction detector RA generates an alarm indication AW, a 
high-error-rate signal EPT and a confirmation signal ATL under 
circumstances discussed hereinafter. 
In FIG. 2 I have shown details of correlation circuit AT which comprises a 
decoder CD receiving the incoming bit stream DE from line 20. Upon 
recognizing a first alignment word "A", decoder CD emits an identification 
pulse AX representing one of the corrective signals referred to in 
connection with FIG. 1. A similar identification pulse BX is generated by 
the decoder upon recognition of a second alignment word "B". 
Decoder CD may have the structure shown in FIG. 6, including a 7-stage 
shift register RG consecutively loaded by the bits of incoming stream DE 
under the control of extracted clock pulses CLK. In conformity with the 
example given in my copending application Ser. No. 278,064, it will be 
assumed that the first alignment word "A" has the configuration 
EQU X-0-0-1-1-0-1-1, 
with the first bit X having a logical value immaterial for present 
purposes. An AND gate G.sub.11 has seven inputs, some of them inverting, 
respectively connected to the stages of register RG so as to conduct when 
the bits loaded into this register correspond to the second to eighth bits 
of alignment word "A"; this will give rise to the identification pulse AX 
in the output of gate G.sub.11. As likewise described in my copending 
application, the only bit of word "B" significant for alignment purposes 
is its second bit B.sub.2 which, when present in the corresponding stage 
of register RG, produced the identification pulse BX. The third bit 
B.sub.3 of alignment word "B" signifies an unusual condition at the 
originating terminal, as also described in my copending application, and 
is therefore fed on a lead 23 to malfunction detector RA (FIG. 1) in order 
to generate the confirmation signal ATL as explained hereinafter with 
reference to FIG. 3. 
FIG. 2 further shows two AND gates G.sub.7 and G.sub.8 feeding alignment 
pulses ATA and BTB to resetting inputs of two counters C.sub.1 and C.sub.2 
which are stepped by pulses TA and TB, respectively. Gate G.sub.7 
generates the alignment pulses ATA whenever the marking pulse TA emitted 
by timer T (FIG. 1) is accompanied by an identification pulse AX 
simultaneously generated by decoder CD. In an analogous manner, gate 
G.sub.8 generates the alignment pulse BT whenever the marking pulse TB 
from the timer coincides with an identification pulse BX from the decoder. 
Since during synchronous operation the marking pulses TA and TB come into 
existence only at a time when the last seven bits of the corresponding 
alignment word occupy all the stages of the shift register RG of FIG. 6, 
pulses TA and ATA as well as TB and BTB will substantially coincide so 
that the corresponding counter C.sub.1 or C.sub.2 will not be stepped. If 
such coincidence is lacking in three successive odd-numbered frames 
F.sub.A or in three successive even-numbered frames F.sub.B, counter 
C.sub.1 or C.sub.2 will reach the limit of its counting capacity and 
through an OR gate G.sub.1 will set a normally reset flip-flop D.sub.4 
emitting the error signal FAT on its set output. Whenever the next 
alignment word "A" is recognized by decoder CD, the resulting 
identification pulse AX traverses an AND gate G.sub.12 in timer T which 
has been unblocked by the signal FAT as illustrated in FIG. 7. Timer T 
comprises essentially a pulse counter PC with a counting cycle spanning 
two frames; marking pulses TA and TB are respectively generated at the end 
and in the middle of this cycle while the end of a frame is signaled to 
receiving section PR (FIG. 1) eight clock pulses CLK before pulse TA. AND 
gate G.sub.12 works into a resetting input of counter PC which is thus 
readjusted to re-emit the pulse TA two frames later, i.e. at an instant 
assumed to coincide with the next recurrence of pulse AX so that alignment 
pulse ATA will again be generated by gate G.sub.7 of FIG. 2. In the 
absence of signal FAT, however, gate G.sub.12 is cut off in order to 
prevent an untimely restarting of counter PC by a fortuitous bit 
combination giving rise to pulse AX. 
The logic circuitry shown in FIG. 2 includes three further flip-flops 
D.sub.1, D.sub.2 and D.sub.3. Flip-flop D.sub.1 has a setting input 
receiving the alignment pulse BTB from gate G.sub.8, its set output 
emitting a signal Q.sub.1 to an inverting input of an AND gate G.sub.2 and 
to noninverting inputs of two other AND gates G.sub.3 and G.sub.4. AND 
gate G.sub.2 has a noninverting input connected, in parallel with a 
similar input of gate G.sub.4 and an inverting input of gate G.sub.3, to 
the output of gate G.sub.7 carrying the alignment pulse ATA; the latter 
pulse is also transmitted to one of three non-inverting inputs of an AND 
gate G.sub.6 which has two other such inputs connected to the reset output 
of flip-flop D.sub.3 and to the set output of flip-flop D.sub.4 carrying 
the error signal FAT. A fourth, inverting input of gate G.sub.6 is 
connected to the output of gate G.sub.2 in parallel with an input of an OR 
gate G.sub.5 having another input connected to an output of gate G.sub.3 
and working into a resetting input of flip-flop D.sub.3 whose setting 
input is tied to the output of gate G.sub.6 in parallel with the resetting 
input of flip-flop D.sub.1. A third input of gate G.sub.3 is tied to the 
lead carrying the marking pulses TA while an inverting third input of gate 
G.sub.4 is connected to the reset output of flip-flop D.sub.3. The setting 
input of flip-flop D.sub.2 is connected to lead 21 carrying the clock 
pulses CKL. 
The set output of flip-flop D.sub.2 and the reset output of flip-flop 
D.sub.3 are respectively connected to a setting input and a resetting 
input of a flip-flop D.sub.9, FIG. 7, responsive to the leading edges of 
pulses Q.sub.2 and Q.sub.3 respectively emitted thereby. Flip-flop D.sub.9 
has its reset output connected to a further input of gate G.sub.12. 
Whenever either counter C.sub.1, C.sub.2 is stepped three times in 
succession without intervening clearing, flip-flop D.sub.4 is set to 
generate the error signal FAT. As long as alignment pulse ATA continues to 
recur regularly, however, flip-flops D.sub.1 -D.sub.3 are all in their set 
state; gates G.sub.2 and G.sub.6 are cut off under these circumstances. 
When decoder CD fails to recognize the alignment word "A" at the instant 
of occurrence of marking pulse TA, flip-flop D.sub.3 is reset by way of 
gates G.sub.3 and G.sub.5 ; this blocks the gate G.sub.4 but unblocks the 
gate G.sub.6 in the presence of error signal FAT for possible conduction 
upon the next recurrence of pulse ATA. The resetting of flip-flop D.sub.3 
also resets flip-flop D.sub.9 in FIG. 7 whereby gate G.sub.12 is enabled 
to give passage to the next identification pulse AX emitted by decoder CD. 
When this occurs, pulse counter PC of timer T is restarted in the 
aforedescribed manner so that, if pulse AX was indeed due to an incoming 
alignment word "A", pulse ATA will reappear two frames later and will pass 
the gate G.sub.6 so as to set flip-flop D.sub.3 while resetting flip-flops 
D.sub.1 and D.sub.2. Flip-flop D.sub.2, however, will be promptly set 
again by the next clock pulse CKL to re-emit the signal Q.sub.2 which sets 
the flip-flop D.sub.9 of timer T (FIG. 7) and reblocks the gate G.sub.12, 
thereby preventing another restarting of counter PC by spurious 
identification pulses due to bit configurations which happen to conform to 
the one described above with reference to FIG. 6. If word "A" is properly 
followed by word "B" in the corresponding time position of the next frame, 
flip-flop D.sub.1 wil again be set by a pulse BTB and will unblock the 
gate G.sub.4 for a resetting of flip-flop D.sub.4 by the next pulse ATA, 
thus terminating the error signal FAT. If, however, pulse BTB or the next 
pulse ATA does not occur at the appointed time, gate G.sub.2 or G.sub.3 
wil conduct to reset the flip-flop D.sub.3 by way of gate G.sub.5 with 
resulting unblocking of the previously blocked gate G.sub.6 and resetting 
of flip-flop D.sub.9 in timer T (FIG. 7) to restore the situation 
previously described. A new realignment search will then commence. 
It will be noted that the establishment or re-establishment of synchronism 
requires the occurrence of alignment words "A", "B" and "A" in three 
consecutive frames. 
In FIG. 3 I have shown a monitoring circuit which forms part of malfunction 
detector RA and is designed to generate the confirmation signal ATL upon 
two successive occurrences of a bit B.sub.3 of logical value "1" in 
alignment word "B". Lead 23, which carries the bit B.sub.3, extends to the 
data input of a D-type flip-flop D.sub.5 whose clock input receives the 
marking pulse TB concurrently with the clock input of a similar flip-flop 
D.sub.6 in cascade therewith, the data input of the latter flip-flop being 
tied to the set output of flip-flop D.sub.5 carrying a signal Q.sub.5. The 
set outputs of both flip-flops D.sub.5 and D.sub.6 are connected to 
respective inputs of an AND gate G.sub.9 which has a third, inverting 
input connected to the set output of flip-flop D.sub.4 (FIG. 2) carrying 
the error signal FAT. The blocking of gate G.sub.9 by that error signal is 
desirable since the signal on lead 23 is unrelated to the third bit of 
alignment word "B" in the absence of synchronism. A first occurrence of 
the critical bit B.sub.3 sets the flip-flop D.sub.5 which, however, will 
be reset if lead 23 carries a bit "0" during the next recurrence of pulse 
TB. If, on the contrary, the critical bit B.sub.3 apears in two 
consecutive even-numbered frames, both stages D.sub.5 and D.sub.6 of the 
monitoring circuit will be set so that signal ATL is emitted by gate 
G.sub.9. This signal may be retransmitted for supervisory purposes as 
described in my copending application identified above. 
In FIG. 4 I have illustrated another part of malfunction detector RA 
serving to generate the alarm indication AW in the event of a 
noncoincidence of pulses TA and AX which are respectively fed to a 
noninverting and an inverting input of an AND gate G.sub.10. A 
noncoincidence pulse TA then appears in the output of gate G.sub.10 and is 
fed to the data input of a D-type flip-flop D.sub.7 whose clock input 
receives the pulse TA through a delay circuit .tau. bypassing that gate. 
This delay is so chosen that signal AW will be generated on the set output 
of flip-flop D.sub.7 only after a time allowing for a possible belated 
occurrence of identification pulse AX. 
Another part of malfunction detector RA, shown in FIG. 5, is designed to 
measure the error rate and comprises a time-interval generator GM which 
includes a counter C.sub.3 stepped by the marking pulses TB. Counter 
C.sub.3 has a counting capacity of p pulses corresponding to a multiframe 
interval of 2p frames. At the end of that period, a monoflap M is tripped 
by the counter to generate a pulse P fed to a stepping input of an n-pulse 
counter C.sub.5 designed as an n-stage shift register. Pulses AA from gate 
G.sub.10 of FIG. 4 are delivered to a noninverting input of an AND gate 
G.sub.16 whose output is tied to a stepping input of an n-pulse counter 
C.sub.4. The latter has an output connected to a data input of counter 
C.sub.5 and to an inverting input of gate G.sub.16 in parallel with a 
noninverting input of another AND gate G.sub.14. As long as counter 
C.sub.4 has not reached the limit of its capacity, gate G.sub.16 conducts 
and passes the noncoincidence pulses AA. When that limit is reached, 
counter C.sub.4 emits a pulse K which blocks the gate G.sub.16 and loads 
the first shift-register stage of counter C.sub.5. A bit of logical value 
"1", which may be termed a mark, is thereby stored in that first stage and 
will thereafter be advanced through the shift register by successive 
pulses P at the end of each multiframe interval measured by generator GM. 
If such a mark is loaded into counter C.sub.5 during n consecutive 
multiframe intervals, a bit "1" will eventually appear in each of its 
stages. These stages are connected to respective inputs of an AND gate 
G.sub.18 and, in parallel therewith, to respective inputs of a NOR gate 
G.sub.19. Gate G.sub.18 emits in such a case a setting pulse S to a 
flip-flop D.sub.8 whose set output then carries a signal Q.sub.8 
corresponding to the aforedescribed high-error-rate signal EPT. This 
signal is fed to a second input of AND gate G.sub.14 which thus passes the 
pulse K in the output of counter C.sub.4 whereby that counter is reset via 
an OR gate G.sub.15 and an AND gate G.sub.17 upon the occurrence of the 
next pulse P emitted by monoflop M. Such resetting in response to pulse P 
also takes place when AND gate G.sub.17 is unblocked by a signal Q.sub.8 
normally appearing on the reset output of flip-flop D.sub.8. 
The resetting of flip-flop D.sub.8, once it has been set by a signal S from 
gate G.sub.18, occurs only when all n stages of pulse counter C.sub.5 
carry a bit "0" so as to activate the NOR gate G.sub.19, i.e. when counter 
C.sub.4 has failed to reach the limit of its capacity in n consecutive 
intervals measured by circuit GM. The integers m, n and p may, of course, 
be selected at will in accordance with existing operating conditions and 
may or may not be equal to one another. 
It will be understood that the particular logic circuitry of FIGS. 2-7 is 
given only by way of example and that the described mode of operation can 
be achieved in a variety of alternative ways which will be readily 
apparent to persons skilled in the art.