Semiconductor memory device and memory system including the same

A memory system includes: a memory device including at least one bank; and a memory controller suitable for: dividing the bank into a plurality of sub-regions according to an active address, generating an aging signal for the bank based on a plurality of counting values generated by counting a number of inputs of an active command for each of the sub-regions, and providing the active command, the active address, the aging signal, and a target refresh command, wherein the memory device is suitable for: generating a sampling address by sampling the active address according to the active command, and performing a target refresh operation on a word line corresponding to the sampling address according to the target refresh command while adjusting a refresh period of the bank according to the aging signal.

BACKGROUND

Various embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a memory system including a semiconductor memory device that performs a target refresh operation.

2. Description of the Related Art

A memory cell of a semiconductor memory device includes a transistor that functions as a switch and a capacitor that stores charges (or data). Data is determined to be at a logic high level (logic level 1) and at a logic low level (logic level 0) according to whether there is any charge in the capacitor of a memory cell, that is, whether the terminal voltage of the capacitor is high or low.

Data are stored in a form in which charges are accumulated in a capacitor, and theoretically, there is no power consumption. However, since there may be a leakage current due to such reasons such as a PN coupling of a transistor, the initial amount of charges stored in the capacitor may disappear, which leads to the loss of data. To prevent this from occurring, the data in a memory cell is read before the data gets lost, and a normal amount of charges according to the read data should be recharged back into the memory cell. The data may be retained only when such an operation is repeated periodically, and the process of recharging cell charges is referred to as a refresh operation which will be, hereinafter, referred to as a normal refresh operation.

Recently, in addition to the normal refresh operation, an additional refresh operation which will be, hereinafter, referred to as a ‘target refresh operation’, is being performed on the memory cells of a specific word line that is likely to lose data due to row hammering. The row hammering phenomenon refers to a phenomenon in which data of memory cells coupled to a specific word line or the word lines disposed adjacent to the word line are damaged due to a high number of activations of the corresponding word line. In order to prevent the row hammering phenomenon, a target refresh operation is performed on a word line that is activated more than a predetermined number of times which is, hereinafter, referred to as a ‘target word line’, and the word lines disposed adjacent to the word line.

In order to select a word line to be refreshed during the target refresh operation, the memory device needs to count all of the addresses inputted with an active command. The memory device has counting circuits to count the number of inputs of the addresses, and as technological scaling progresses, the smaller the size of the memory device, the larger the portion the counting circuits occupy.

SUMMARY

Embodiments of the present invention are directed to a memory system including a memory controller capable of providing information that analyzes patterns with high risk of row hammer per bank, and a memory device capable of adjusting a target refresh period per bank based on the analyzed information.

According to an embodiment of the present invention, a memory system includes a memory device including at least one bank; and a memory controller suitable for: dividing the bank into a plurality of sub-regions according to an active address, generating an aging signal for the bank based on a plurality of counting values generated by counting a number of inputs of an active command for each of the sub-regions, and providing the active command, the active address, the aging signal, and a target refresh command, wherein the memory device is suitable for: generating a sampling address by sampling the active address according to the active command, and performing a target refresh operation on a word line corresponding to the sampling address according to the target refresh command while adjusting a refresh period of the bank according to the aging signal.

According to an embodiment of the present invention, a memory system includes a memory device including at least one bank; and a memory controller suitable for: dividing the bank into a plurality of sub-regions according to an active address, generating an aging signal for the bank based on a plurality of counting values generated by counting a number of inputs of an active command for each of the sub-regions, generating a row hammer address according to the aging signal, and providing the aging signal, and a target refresh command with the row hammer address, wherein the memory device is suitable for performing a target refresh operation on a word line corresponding to the row hammer address according to the target refresh command while adjusting a refresh period of the bank according to the aging signal.

According to an embodiment of the present invention, a memory controller includes a processor suitable for generating an active command and an active address corresponding to a request from a host; a sub-counting circuit suitable for: dividing at least one bank of a memory device into a plurality of sub-regions according to the active address, and generating a plurality of counting values by counting a number of inputs of the active command for each of the sub-regions based on the active address; an aging decision circuit suitable for generating an aging signal for the bank and a count reset signal by calculating an average of the counting values and calculating a standard deviation based on the average, wherein the count reset signal initializes the sub-counting circuit; and a tracking circuit suitable for: generating a target refresh command based on the active command, and generating a row hammer address corresponding to the active address according to the aging signal and the counting values when the number of inputs of the active command for the bank is greater than a preset number.

According to an embodiment of the present invention, a memory system includes a memory device including a group of plural memory regions; and a memory controller configured to generate a shortening signal when activation counts of the memory regions are statistically concentrated by a set amount or greater, wherein the memory device is configured to perform a target refresh operation on the group at a shortened period in response to the shortening signal, and wherein the activation count of each of the memory regions is a number of active commands provided for the memory region for a set amount of time.

Further, according to embodiments of the present invention, the memory system may achieve the row hammer mitigation with a minimum area in a way that the memory controller divides each bank into a plurality of sub-regions to analyze the number of activations per sub-region, and the memory device adjusts the target refresh period for each bank according to the information analyzed by the memory controller.

DETAILED DESCRIPTION

It will be understood that when an element is referred to as being “coupled” or “connected” to another element, it may mean that the two are directly coupled or the two are electrically connected to each other with another circuit intervening therebetween. It will be further understood that the terms “comprise”, “include”, “have”, etc. when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, components, and/or combinations of them but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or combinations thereof. In the present disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Hereinafter, to focus on a refresh operation, a description of a configuration associated with a data input/output operation will be omitted. In particular, for ease of description, an address used by a memory controller in a memory system may be assigned by a reference numeral “_ADD”, and an address used in a memory device may be assigned by a reference numeral “ADD_”.

FIGS.1A and1Bare graphs illustrating the number of inputs for an active address per refresh cycle in accordance with an embodiment of the present invention.

Referring toFIG.1A, it is illustrated that addresses (hereinafter defined as “active addresses”) that are entered with an active command during one refresh cycle are evenly distributed. That is,FIG.1Ashows a case where the row hammer risk is lower since the number of activations per address is evenly distributed. In this case, since the number of activations per address within one refresh cycle (hereinafter defined as “active aggressor”) is small, a memory device may respond to the row hammer risk through a target refresh operation performed therein.

Referring toFIG.1B, it is illustrated that the active addresses during one refresh cycle are concentrated only on some particular addresses. That is,FIG.1Bshows a case where the active aggressor per address is abnormally increased due to a special occurrence such as hacking, resulting in the high row hammer risk. In this case, since the target refresh operation performed within the memory device alone makes it difficult to respond to the row hammer risk, additional help from a memory controller is needed.

Disclosed hereinafter is a scheme of achieving the row hammer mitigation of the memory system. In accordance with an embodiment of the present invention, the memory controller may analyze a case where the row hammer risk is high, that is, the active aggressor is concentrated only on some particular address types, as shown inFIG.1B. Then, the memory device may adjust a target refresh period (or cycle) for each bank according to the information analyzed by the memory controller.

FIG.2is a block diagram illustrating a memory system10in accordance with an embodiment of the present invention.

Referring toFIG.2, the memory system10may include a memory controller100, and a semiconductor memory device200.

The memory controller100may control the general operation of the memory system10and it may control general data exchange between a host and the semiconductor memory device200. The memory controller100may generate a command/address signal C/A according to a request REQ from the host, and provide the generated command/address signal C/A to the semiconductor memory device200. The memory controller100may provide a clock CK together with the command/address signal C/A to the semiconductor memory device200. The memory controller100may provide data DQ corresponding to host data HDATA provided from the host to the semiconductor memory device200together with a data strobe signal DQS. The memory controller100may receive the data DQ read from the semiconductor memory device200together with the data strobe signal DQS, and provide the data DQ and the data strobe signal DQS to the host as the host data HDATA.

In detail, the memory controller100may include a host interface (host I/F)110, a processor120, a refresh analysis module130, a command/address (CMD/ADD) generation module140, a memory interface (memory I/F)150, and a bus170.

The host interface110may be configured to communicate with the host connected to the memory system10under the control of the processor120. For example, the host interface110may receive the request REQ and the host data HDATA from the host, and provide the host data HDATA to the host by receiving the data DQ read from the semiconductor memory device200through the memory interface150.

The processor120may perform various types of computational and/or other operations for controlling the semiconductor memory device200, and/or may execute instructions in the form of firmware or other types of software. The processor120may receive the request REQ and the host data HDATA provided from the host through the host interface110. The processor120may generate various commands corresponding to the request REQ, such as an active command ACT, a read command, a write command, and an address, to provide the commands to the refresh analysis module130and the command/address generation module140. The processor120may transmit the host data HDATA to the memory interface150. The address generated with the active command ACT may be defined as an active address ACT_ADD. The processor120may control overall operations of the host interface110, the refresh analysis module130, the command/address generation module140, and the memory interface150.

The refresh analysis module130may generate commands relating to a refresh operation, such as a normal refresh command REF and a target refresh command TREF, based on the active command ACT provided from the processor120. The refresh analysis module130may generate the target refresh command TREF after generating a set number of the normal refresh commands REF at regular intervals whenever the number of inputs of the active command ACT reaches a certain number. In accordance with a first embodiment of the present invention, the refresh analysis module130may divide at least one bank BK of the semiconductor memory device200, into a plurality of sub-regions SUB0 to SUBn, and generate an aging signal AG_EN for the bank based on counting values generated by counting the number of inputs of the active command ACT per sub-region within the bank. A detailed configuration of the refresh analysis module130in accordance with the first embodiment will be described inFIGS.3to5B. In accordance with a second embodiment of the present invention, the refresh analysis module130may additionally generate a row hammer address RH_ADD corresponding to the active address ACT_ADD according to the aging signal AG_EN when the number of inputs of the active command ACT for each bank BK is greater than a set number. A detailed configuration of the refresh analysis module130in accordance with the second embodiment will be described inFIGS.11to13.

The command/address generation module140may generate the command/address signal C/A by scheduling the commands and address provided from the processor120and the refresh analysis module130. The command/address generation module140may provide the active address ACT_ADD together with the active command ACT, as the command/address signal C/A, and provide the normal refresh command REF, the target refresh command TREF or the aging signal AG_EN as the command/address signal C/A. The command/address generation module140may provide a bank address including information on the banks BKs of the semiconductor memory device200, together with the normal refresh command REF, the target refresh command TREF or the aging signal AG_EN, as the command/address signal C/A.

The memory interface150may be configured to communicate with the semiconductor memory device200under the control of the processor120. For example, the memory interface150may transmit the command/address signal C/A and the data DQ to the semiconductor memory device200, and transmit the data DQ read from the semiconductor memory device200to the host interface110.

The processor120may transmit data between the host interface110, the refresh analysis module130, the command/address generation module140, and the memory interface150via the bus170. According to an embodiment, the host interface110, the refresh analysis module130, the command/address generation module140, and the memory interface150may communicate with each other independently without passing through the bus170. For example, the refresh analysis module130and host interface110may communicate directly with each other without passing through the bus170. The refresh analysis module130and the memory interface150may communicate with each other directly without passing through the bus170. The host interface110and the memory interface150may also communicate directly with each other without passing through the bus170.

The semiconductor memory device200may perform a refresh operation, a write operation, and a read operation according to the clock CK, the command/address signal C/A, the data strobe signal DQS, and/or the data DQ that are provided from the memory controller100. The refresh operation may include a normal refresh operation in which the semiconductor memory device200sequentially refreshes a plurality of word lines during a normal refresh period, and a target refresh operation in which one or more neighboring word lines disposed adjacent to a word line having a large number of activations or a high frequency of activations are refreshed, during a target refresh period.

The semiconductor memory device200may generate an internal command (ICMD ofFIG.6) and an internal address (IADD ofFIG.6) by buffering the command/address signal C/A, and may generate an active command ACT, a precharge command PCG, a normal refresh command REF, a target refresh command TREF, and an aging signal AG_EN, which are related to a row control operation, by decoding the command ICMD. The semiconductor memory device200may perform the normal refresh operation according to the normal refresh command REF and perform the target refresh operation according to the target refresh command TREF while adjusting a refresh period according to the aging signal AG_EN. For reference, the internal address IADD may correspond to the active address ACT_ADD when the active command ACT is generated. Depending on an embodiment, the internal address IADD may correspond to the row hammer address RH_ADD when the target refresh command TREF is generated. Further, the semiconductor memory device200may additionally generate commands related to data input/output operations (e.g., a read command or a write command) by decoding the internal command ICMD.

In detail, the semiconductor memory device200may include a memory cell array210and a refresh control circuit230.

The memory cell array210may include a plurality of banks BKs. In each of the banks BKs, a plurality of memory cells (not shown) coupled to a plurality of word lines (not shown) and a plurality of bit lines (not shown) may be arranged in the form of an array. Each of the banks BKs may be divided into the sub-regions SUB0 to SUBn. The sub-regions SUB0 to SUBn may be configured to have different word lines. For example, when 4096 word lines are disposed in each bank, first to eighth sub-regions SUB0 to SUB7 may be sequentially separated to include 512 word lines.

The refresh control circuit230may provide a target address TADD to select a word line to be refreshed during the target refresh operation, among the word lines. In accordance with the first embodiment, the refresh control circuit230may sample the active address ACT_ADD according to the active command ACT to generate a sampling address per bank and perform the target refresh operation on a word line corresponding to the sampling address according to the target refresh command TREF while adjusting a refresh period per bank according to the aging signal AG_EN. A detailed configuration of the refresh control circuit230in accordance with the first embodiment will be described inFIGS.6to9. In accordance with the second embodiment, the refresh control circuit230may perform the target refresh operation on a word line corresponding to the row hammer address RH_ADD provided from the memory controller100, according to the target refresh command TREF, while adjusting a refresh period per bank according to the aging signal AG_EN. A detailed configuration of the refresh control circuit230in accordance with the second embodiment will be described inFIG.14.

As described above, in accordance with an embodiment of the present invention, the memory controller100may divide each bank BK into the plurality of sub-regions SUB0 to SUBn to analyze the number of activations per sub-region within the bank, and the semiconductor memory device200may adjust the target refresh period for each bank BK according to the information analyzed by the memory controller100. Accordingly, the memory system10may achieve the row hammer mitigation with a minimum area.

Hereinafter, a detailed configuration of the memory system10in accordance with the first embodiment will be described. In the following embodiments, it is described that the semiconductor memory device200has first to (k+1)th banks BK0 to BKk and each bank has first to (n+1)th sub-regions SUB0 to SUBn, as an example.

FIG.3is a detailed block diagram illustrating the memory controller100shown inFIG.1, in accordance with the first embodiment of the present invention. InFIG.3, to focus on the characteristics of the embodiment, additional configurations (e.g., the host interface110and the memory interface150) have been omitted.

Referring toFIG.3, the processor120may receive the request REQ from the host through the host interface110. The processor120may generate the active command ACT and the active address ACT_ADD corresponding to the request REQ.

The refresh analysis module130may include a plurality of analysis circuits130_0to130_krespectively corresponding to the banks BK0 to BKk of the semiconductor memory device200. Each of the analysis circuits130_0to130_kmay include an aging analysis circuit132and a refresh command issue circuit134.

The aging analysis circuit132may generate a plurality of counting values CNT_SUB0 to CNT_SUBn by counting the number of inputs of the active command ACT per sub-region of a corresponding bank among the banks BK0 to BKk, based on the active address ACT_ADD. The number of inputs of the active command ACT per sub-region may be counted for a set amount of time. The number of inputs of the active command ACT per sub-region may be counted periodically. At each amount of time, the number of inputs of the active command ACT per sub-region may be initialized when a count reset signal CNT_RST is generated, which will be described later. The aging analysis circuit132may calculate a standard deviation of the counting values CNT_SUB0 to CNT_SUBn, and generate the aging signal AG_EN for the corresponding bank according to the standard deviation.

In detail, the aging analysis circuit132may include a sub-counting circuit1322and an aging decision circuit1324.

The sub-counting circuit1322may generate the counting values CNT_SUB0 to CNT_SUBn by counting the number of inputs of the active command ACT per sub-region of the corresponding bank, based on the active address ACT_ADD. The sub-counting circuit1322may be initialized by a count reset signal CNT_RST.

The aging decision circuit1324may generate the aging signal AG_EN and the count reset signal CNT_RST of the corresponding bank by calculating an average of the counting values CNT_SUB0 to CNT_SUBn and calculating the standard deviation based on the average. When the standard deviation is greater than a reference value, the aging decision circuit1324may disable the aging signal AG_EN but enable the count reset signal CNT_RST. When the standard deviation is less than or equal to the reference value, the aging decision circuit1324may enable the aging signal AG_EN but disable the count reset signal CNT_RST

The refresh command issue circuit134may generate the normal refresh command REF and the target refresh command TREF, based on the active command ACT provided from the processor120. The refresh command issue circuit134may issue the target refresh command TREF or the normal refresh command REF when the number of inputs of the active command ACT reaches a certain number.

For example, the refresh command issue circuit134may include a command counter1342and a counter analyzer1344.

The command counter1342may generate a count value by counting the number of inputs of the active command ACT. The counter analyzer1344may issue a set number of the normal refresh commands REF at regular intervals whenever the count value reaches the certain number. The counter analyzer1344may issue the target refresh command TREF after issuing the set number of the normal refresh commands REF. For example, the counter analyzer1344may issue at least one target refresh command TREF after issuing4096normal refresh commands REF whenever the count value reaches 10.

The command/address generation module140may generate the command/address signal C/A by scheduling the active command ACT and the active address ACT_ADD provided from the processor120, and the normal refresh commands REF, the target refresh command TREF and the aging signal AG_EN provided from the refresh analysis module130. The command/address generation module140may output the active address ACT_ADD together with the active command ACT, as the command/address signal C/A, and provide the normal refresh command REF, the target refresh command TREF or the aging signal AG_EN together with the bank address including the bank information, as the command/address signal C/A.

FIG.4is a detailed configuration diagram illustrating the sub-counting circuit1322ofFIG.3in accordance with an embodiment of the present invention.

Referring toFIG.4, the sub-counting circuit1322may include a sub-decoder310, an active combiner320, and a plurality of sub-counters C0 to Cn.

The sub-decoder310may decode the active address ACT_ADD to generate a plurality of sub-region signals BK_SUB0 to BK_SUBn for respectively designating the sub-regions SUB0 to SUBn of the corresponding bank. In an embodiment, the sub-decoder310may generate the sub-region signals BK_SUB0 to BK_SUBn by decoding some of bits in the active address ACT_ADD, which specify the word lines. When the active address ACT_ADD<0:x> is composed of (x+1) bits, the sub-decoder310may decode (m+1) bits (e.g., ACT_ADD<0:m>) in the active address ACT_ADD<0:x>, wherein (m+1) bits ACT_ADD<0:m> correspond to a row address for designating the word lines. For example, the sub-decoder310may enable the first sub-region signal BK_SUB0 when the active address ACT_ADD<0:x> for designating a second word line included in the first sub-region SUB0 is inputted.

The active combiner320may respectively output the sub-region signals BK_SUB0 to BK_SUBn as a plurality of sub-region activation signals ACT_SUB0 to ACT_SUBn, when the active command ACT is inputted. For example, the active combiner320may be implemented with a plurality of AND gates for performing a logic AND operation on the active command ACT and the sub-region activation signals ACT_SUB0 to ACT_SUBn, respectively.

The sub-counters C0 to Cn may respectively correspond to the sub-regions SUB0 to SUBn. Each of the sub-counters C0 to Cn may generate a corresponding counting value of the counting values CNT_SUB0 to CNT_SUBn by increasing its counting value by +1 when a corresponding sub-region activation signal of the sub-region activation signals ACT_SUB0 to ACT_SUBn is enabled. The sub-counters C0 to Cn may be initialized when the count reset signal CNT_RST is enabled.

With the above configuration, the sub-counting circuit1322may generate the counting values CNT_SUB0 to CNT_SUBn by counting the number of inputs of the active command ACT per sub-region of the corresponding bank, based on the active address ACT_ADD.

FIG.5Ais a detailed configuration diagram andFIG.5Bis a flow chart illustrating the aging decision circuit1324ofFIG.3.

Referring toFIG.5A, the aging decision circuit1324may include an average calculator410, a deviation calculator420, and an aging analyzer430.

The average calculator410may calculate an average AVG of the counting values CNT_SUB0 to CNT_SUBn. For example, the average calculator410may output the average AVG by dividing the sum of the counting values CNT_SUB0 to CNT_SUBn, by n+1.

The deviation calculator420may calculate a standard deviation STD based on the average AVG. For example, the deviation calculator420may calculate a variance by dividing the sum of the squares of the deviation between the average AVG and the counting values CNT_SUB0 to CNT_SUBn, by n+1, and output the square root of the variance as the standard deviation STD.

For reference, the standard deviation STD may be a parameter indicating how much the counting values CNT_SUB0 to CNT_SUBn deviate from the average AVG. A smaller standard deviation STD may mean that the counting values CNT_SUB0 to CNT_SUBn are concentrated near the average AVG. A larger standard deviation STD may mean that the counting values CNT_SUB0 to CNT_SUBn deviate more from the average AVG.

The aging analyzer430may generate the aging signal AG_EN and the count reset signal CNT_RST based on the standard deviation STD. When the standard deviation STD is greater than the reference value, the aging analyzer430may determine that the row hammer risk is lower since the number of activations per address is evenly distributed as shown inFIG.1A, thereby disabling the aging signal AG_EN but enabling the count reset signal CNT_RST. When the standard deviation STD is less than or equal to the reference value, the aging analyzer430may determine that the row hammer risk is higher since the active aggressor per address is abnormally increased as shown inFIG.1B, thereby enabling the aging signal AG_EN but disabling the count reset signal CNT_RST.

Referring toFIG.5B, the average calculator410may calculate the average AVG from the counting values CNT_SUB0 to CNT_SUBn (at S410). The deviation calculator420may calculate the standard deviation STD based on the average AVG (at S420). When the standard deviation STD is greater than the reference value (“YES” of S430), the aging analyzer430may disable the aging signal AG_EN but enable the count reset signal CNT_RST (at S440). On the contrary, when the standard deviation STD is less than or equal to the reference value, the aging analyzer430may enable the aging signal AG_EN but disable the count reset signal CNT_RST (at S450).

FIG.6is a detailed block diagram illustrating the semiconductor memory device200corresponding to the memory controller100shown inFIG.3, in accordance with an embodiment of the present invention.FIG.7is a detailed circuit diagram illustrating an output control circuit235ofFIG.6in accordance with an embodiment of the present invention.FIG.8is a detailed circuit diagram illustrating an input control circuit238ofFIG.6in accordance with an embodiment of the present invention.FIG.9is a detailed configuration diagram illustrating an address storing circuit239ofFIG.6in accordance with an embodiment of the present invention.FIG.6shows that the semiconductor memory device200includes first to eighth banks BK0 to BK7 in the memory cell array210.

Referring toFIG.6, the semiconductor memory device200may include the memory cell array210, a row control circuit212, a clock buffer221, a command/address (CA) buffer222, a command decoder223, an address decoder224, an address latch225, and the refresh control circuit230.

The memory cell array210may include the first to eighth banks BK0 to BK7. In each of the first to eighth banks BK0 to BK7, memory cells MC coupled to word lines WL and bit lines may be arranged in the form of an array. Each of the first to eighth banks BK0 to BK7 may be divided into a plurality of sub-regions SUB0 to SUBn. The sub-regions SUB0 to SUBn may be configured to have different word lines. The number of banks BK0 to BK7 or the number of memory cells MC may be determined depending on the capacity of the semiconductor memory device200.

The clock buffer221may receive a clock CK from the memory controller100. The clock buffer221may generate an internal clock CLK by buffering the clock CK. Depending on an embodiment, the memory controller100may transfer system clocks CK_t and CK_c to the semiconductor memory device200in a differential manner, and the semiconductor memory device200may include clock buffers that receive the differential clocks CK_t and CK_c, respectively.

The CA buffer222may receive a command/address signal C/A from the memory controller100based on the clock CK. The CA buffer222may sample the command/address signal C/A based on the clock CK and output the internal command ICMD and the internal address IADD. Consequently, the semiconductor memory device200may be synchronized with the clock CK.

The command decoder223may decode the internal command ICMD which is output from the CA buffer222to generate an active command ACT, a precharge command PCG, a normal refresh command REF, a target refresh command TREF, and an aging signal AG_EN. Although not illustrated, the command decoder223may additionally generate a read command RD, a write command WT, a mode register command MRS, and the like by decoding the internal command ICMD.

The address decoder224may generate a bank address BA<0:3> by decoding the internal address IADD. The bank address BA<0:3> may be used to designate the first to eighth banks BK0 to BK7. Depending on an embodiment, a certain bit of the bank address BA<0:3> may be used to select all of the first to eighth banks BK0 to BK7. Although not illustrated, the address decoder224may generate a row address and a column address by decoding the internal address IADD, and provide the addresses to the row control circuit212and a column control circuit (not shown).

The address latch225may latch the internal address IADD according to the active command ACT to output an active address ADD_ACT. That is, the address latch225may provide the internal address IADD inputted with the active command ACT as the active address ADD_ACT.

The refresh control circuit230may store a plurality of sample addresses ADD_SAM0 to ADD_SAM7 per bank by sampling the active address ADD_ACT according to the active command ACT and the bank address BA<0:3> at random points of time. The refresh control circuit230may generate first to eighth bank refresh signals SR_BK<0:7> according to the target refresh command TREF and the bank address BA<0:3>, while controlling an activation of the first to eighth bank refresh signals SR_BK<0:7> such that a refresh period (or refresh rate) per bank is adjusted by the aging signal AG_EN. The refresh control circuit230may provide a target address TADD by selecting any from the sample addresses ADD_SAM0 to ADD_SAMn, according to the first to eighth bank refresh signals SR_BK<0:7>. As a result, the refresh control circuit230may control an output interval (i.e., timing) of the target address TADD such that the refresh period (or refresh rate) per bank is adjusted, according to the aging signal AG_EN.

In detail, the refresh control circuit230may include an aging decoder232, a refresh decoder233, a period adjusting circuit234, the output control circuit235, an active decoder236, a sampling signal generation circuit237, the input control circuit238, and the address storing circuit239.

The aging decoder232may generate first to eighth aging bank signals AG_BK<0:7> respectively corresponding to the first to eighth banks BK0 to BK7, by decoding the bank address BA<0:3> according to the aging signal AG_EN. For example, the aging decoder232may generate the second aging bank signal AG_BK<1> corresponding to the second bank BK1 according to the aging signal AG_EN, when the bank address BA<0:3> for designating the second bank BK1 is inputted.

The refresh decoder233may generate first to eighth target refresh bank signals TREF_BK<0:7> respectively corresponding to the first to eighth banks BK0 to BK7, by decoding the bank address BA<0:3> according to the target refresh command TREF. For example, the refresh decoder233may generate the second target refresh bank signal TREF_BK1 corresponding to the second bank BK1 when the bank address BA<0:3> for designating the second bank BK1 is inputted.

The period adjusting circuit234may generate first to eighth period control signals SR_EN_BK<0:7> for adjusting the refresh period (refresh rate) of the first to eighth banks BK0 to BK7, according to the first to eighth aging bank signals AG_BK<0:7>, respectively. The period adjusting circuit234may increase an activation section of a period control signal corresponding to an enabled aging bank signal, while decreasing or maintaining an activation section of a period control signal corresponding to a disabled aging bank signal. For example, the period adjusting circuit234may increase an activation section of the second period control signal SR_EN_BK<1> when the second aging bank signal AG_BK<1> corresponding to the second bank BK1 is enabled.

The output control circuit235may generate the first to eighth bank refresh signals SR_BK<0:7>, according to the first to eighth target refresh bank signals TREF_BK<0:7> and the first to eighth period control signals SR_EN_BK<0:7>. The output control circuit235may enable a corresponding bank refresh signal when both of a corresponding target refresh bank signal and a corresponding period control signal are enabled. Referring toFIG.7, the output control circuit235may be implemented with first to eighth AND gates235_AD1to235_AD8for performing a logic AND operation on the first to eighth target refresh bank signals TREF_BK<0:7> and the first to eighth period control signals SR_EN_BK<0:7>, respectively.

The active decoder236may generate first to eighth active bank signals ACT_BK<0:7> respectively corresponding to the first to eighth banks BK0 to BK7, by decoding the bank address BA<0:3> according to the active command ACT. For example, the active decoder236may generate the second active bank signal ACT_BK<1> corresponding to the second bank BK1 according to the active command ACT, when the bank address BA<0:3> for designating the second bank BK1 is inputted.

The sampling signal generation circuit237may generate first to eighth sampling signals SAEN_BK<0:7> that are randomly enabled. Depending on an embodiment, the sampling signal generation circuit237may generate first to eighth sampling signals SAEN_BK<0:7> that are sequentially enabled based on the internal clock CLK. The sampling signal generation circuit237may be implemented with a pseudo-random binary sequence (PRBS) based random pattern generator, or a linear feedback shift register (LFSR) based random pattern generator.

The input control circuit238may generate first to eighth input control signals SAM_BK<0:7>, according to the first to eighth active bank signals ACT_BK<0:7> and the first to eighth sampling signals SAEN_BK<0:7>. The input control circuit238may enable a corresponding input control signal when both of a corresponding active bank signal and a corresponding sampling signal are enabled. Referring toFIG.8, the input control circuit238may be implemented with first to eighth AND gates238_AD1to238_AD8for performing a logic AND operation on the first to eighth active bank signals ACT_BK<0:7> and the first to eighth sampling signals SAEN_BK<0:7>, respectively.

The address storing circuit239may store the active address ADD_ACT as the sample addresses ADD_SAM0 to ADD_SAM7 per bank, according to the first to eighth input control signals SAM_BK<0:7>. The address storing circuit239may output, as the target address TADD, any of the sample addresses ADD_SAM0 to ADD_SAM7 according to the first to eighth bank refresh signals SR_BK<0:7>. The address storing circuit239may include first to eighth latch circuits LAT_B0 to LAT_B7 respectively corresponding to the first to eighth banks BK0 to BK7. Referring toFIG.9, each of the latch circuits LAT_B0 to LAT_B7 may store the active address ADD_ACT as its sample address when a corresponding control signal of the first to eighth input control signals SAM_BK<0:7> is enabled. Each of the latch circuits LAT_B0 to LAT_B7 may output the stored sample address as the target address TADD when a corresponding bank refresh signal of the first to eighth bank refresh signals SR_BK<0:7> is enabled.

The row control circuit212may activate a word line WL corresponding to the internal address IADD according to the active command ACT (i.e., the first to eighth active bank signals ACT_BK<0:7>), and precharge the activated word line WL according to the precharge command PCG. In order to select a word line to be refreshed during the normal refresh operation, a refresh counter (not shown) for generating a counting address that is sequentially increasing according to the normal refresh command REF may be additionally provided. The row control circuit212may perform the normal refresh operation of sequentially refreshing the plurality of word lines WL corresponding to the counting address according to the normal refresh command REF. The row control circuit212may perform the target refresh operation of refreshing one or more neighboring word lines of a word line WL corresponding to the target address TADD according to the target refresh command TREF (i.e., first to eighth bank refresh signals SR_BK<0:7>).

FIG.10is a timing diagram for describing a method for adjusting a refresh period of each bank, in accordance with an embodiment of the present invention.FIG.10shows a case where the bank address BA<0:3> for designating all banks BK0 to BK7 is inputted, and all of the target refresh bank signals TREF_BK<0:7> are simultaneously enabled according to the target refresh command TREF.

Referring toFIG.10, the eighth aging bank signal AG_BK<7> corresponding to the eighth bank BK7 is enabled.

The aging decoder232may select the eighth bank BK7 from the first to eighth banks BK0 to BK7 by decoding the bank address BA<0:3> and enable the eighth aging bank signal AG_BK<7> corresponding to the eighth bank BK7 according as the aging signal AG_EN is enabled. The period adjusting circuit234may increase an activation section of the eighth period control signal SR_EN_BK<7> corresponding to the enabled eighth aging bank signal AG_BK<7>, while maintaining the activation sections of the first to seventh period control signals SR_EN_BK<0:6>. The output control circuit235may enable the first to eighth bank refresh signals SR_BK<0:7>, according to the first to eighth period control signals SR_EN_BK<0:7> whenever the target refresh command TREF is inputted. At this time, the output control circuit235may enable the eighth bank refresh signal SR_BK<7> more frequently according to the eighth period control signal SR_EN_BK<7>. As a result, the target refresh period of the eighth bank BK<7> with the aging signal AG_EN enabled may be shorter.

As described above, in the memory system10in accordance with the first embodiment, the refresh analysis module130may divide at least one bank BK of the semiconductor memory device200, into the plurality of sub-regions SUB0 to SUBn, and generate the aging signal AG_EN for each bank based on counting values generated by counting the number of inputs of the active command ACT per sub-region within the bank. Thus, the memory controller100may generate the aging signal AG_EN by analyzing a case where the row hammer risk is high when the active aggressor is concentrated only on particular addresses, due to a special occurrence such as hacking. The semiconductor memory device200may adjust the target refresh period (or cycle) for each bank according to the aging signal AG_EN. Accordingly, the memory system10may achieve the row hammer mitigation with a minimum area.

Hereinafter, a detailed configuration of the memory system10in accordance with the second embodiment will be described

FIG.11is a detailed block diagram illustrating the memory controller100shown inFIG.1, in accordance with the second embodiment of the present invention.FIG.12is a detailed configuration diagram illustrating a tracking circuit136ofFIG.11in accordance with an embodiment of the present invention.FIG.13is a detailed configuration diagram illustrating an address sampling circuit530ofFIG.12in accordance with an embodiment of the present invention.

Referring toFIG.11, the processor120may receive a request REQ from the host through the host interface110. The processor120may generate an active command ACT and an active address ACT_ADD corresponding to the request REQ.

The refresh analysis module130may include a plurality of analysis circuits130_0to130_krespectively corresponding to the banks BK0 to BKk of the semiconductor memory device200. Each of the analysis circuits130_0to130_kmay include an aging analysis circuit132and the tracking circuit136.

The aging analysis circuit132may include a sub-counting circuit1322and an aging decision circuit1324. The aging analysis circuit132may have substantially the same configuration and operation of the aging analysis circuit132ofFIG.3.

The tracking circuit136may generate a normal refresh command REF and a target refresh command TREF, based on an active command ACT provided from the processor120. The refresh command issue circuit134may issue the target refresh command TREF or the normal refresh command REF when the number of inputs of the active command ACT reaches a certain number. Further, the tracking circuit136may generate a row hammer address RH_ADD corresponding to the active address ACT_ADD according to an aging signal AG_EN and a plurality of counting values CNT_SUB0 to CNT_SUBn when the number of inputs of the active command ACT for each bank BK is greater than a set number.

Referring toFIG.12, the tracking circuit136may include a refresh command issue circuit510, an enable signal generation circuit520, and the address sampling circuit530.

The refresh command issue circuit510may generate the normal refresh command REF and the target refresh command TREF, based on the active command ACT. For example, the refresh command issue circuit510may include a command counter512and a counter analyzer514. The refresh command issue circuit510may have substantially the same configuration and operation of the refresh command issue circuit134ofFIG.3.

The enable signal generation circuit520may generate a sampling enable signal SAM_EN according to the aging signal AG_EN when the target refresh command TREF is generated. The enable signal generation circuit520may enable the sampling enable signal SAM_EN when the aging signal AG_EN and the target refresh command TREF are enabled. For example, the enable signal generation circuit520may be implemented with an AND gate for performing a logic AND operation on the aging signal AG_EN and the target refresh command TREF.

The address sampling circuit530may generate the row hammer address RH_ADD corresponding to the active address ACT_ADD based on the counting values CNT_SUB0 to CNT_SUBn when the sampling enable signal SAM_EN is enabled.

Referring toFIG.13, the address sampling circuit530may include a maximum selector532, a comparator534, and a sampler536.

The maximum selector532may select a maximum counting value from the counting values CNT_SUB0 to CNT_SUBn, and output some of bits in the active address ACT_ADD, which specify a sub-region corresponding to the maximum counting value, as a maximum address MAX_ADD<0:m>. In an embodiment, the active address ACT_ADD is composed of (x+1) bits, the maximum selector532may store lower (m+1) bits (e.g., ACT_ADD<0:m>) for designating the sub-regions SUB0 to SUBn of the corresponding bank, among the active address ACT_ADD<0:x>, as a table form. The maximum selector532may output the (m+1) bits ACT_ADD<0:m> corresponding to the maximum counting value, as the maximum address MAX_ADD<0:m>.

The comparator534may be activated according to the sampling enable signal SAM_EN. The comparator534may output a comparison signal HIT by comparing the maximum address MAX_ADD<0:m> with (m+1) bits ACT_ADD<0:m> of the active address ACT_ADD. The comparator534may enable the comparison signal HIT when respective bits of the maximum address MAX_ADD<0:m> are identical to the (m+1) bits ACT_ADD<0:m>.

The sampler536may sample the active address ACT_ADD as the row hammer address RH_ADD when the comparison signal HIT is enabled.

With the above configuration, in a case where the aging signal AG_EN is enabled and the number of inputs of the active command ACT for each bank is greater than the set number, the tracking circuit136may output the currently inputted active address ACT_ADD as the row hammer address RH_ADD, when (m+1) number of bits ACT_ADD<0:m> of the currently inputted active address ACT_ADD are identical to (m+1) number of bits ACT_ADD<0:m> for specifying a sub-region corresponding to the maximum counting value among the counting values CNT_SUB0 to CNT_SUBn.

Referring back toFIG.11, the command/address generation module140may generate a command/address signal C/A by scheduling the active command ACT and the active address ACT_ADD provided from the processor120, and the normal refresh commands REF, the target refresh command TREF, the aging signal AG_EN, and the row hammer address RH_ADD provided from the refresh analysis module130. The command/address generation module140may output the active address ACT_ADD together with the active command ACT, as the command/address signal C/A, and provide the normal refresh command REF or the aging signal AG_EN together with the bank address including the bank information as the command/address signal C/A. The command/address generation module140may provide the target refresh command TREF together with the row hammer address RH_ADD, as the command/address signal C/A.

FIG.14is a detailed block diagram illustrating the semiconductor memory device200corresponding to the memory controller shown inFIG.11, in accordance with an embodiment of the present invention.

Referring toFIG.14, the semiconductor memory device200may include the memory cell array210, a row control circuit212, a clock buffer221, a command/address (CA) buffer222, a command decoder223, an address decoder224, and the refresh control circuit230′.

The memory cell array210, the row control circuit212, the clock buffer221, the CA buffer222, the command decoder223, and the address decoder224ofFIG.14may have configurations substantially the same as those ofFIG.6.

The refresh control circuit230′ may provide a target address TADD by latching an internal address IADD according to a target refresh command TREF. The refresh control circuit230′ may generate first to eighth bank refresh signals SR_BK<0:7> according to the target refresh command TREF and a bank address BA<0:3>, while controlling an activation of the first to eighth bank refresh signals SR_BK<0:7> such that a refresh period (or refresh rate) per bank is adjusted by an aging signal AG_EN.

In detail, the refresh control circuit230′ may include an address latch251, an aging decoder252, a refresh decoder253, a period adjusting circuit254, and an output control circuit255.

The address latch251may provide the target address TADD by latching the internal address IADD according to the target refresh command TREF. At this time, since the internal address IADD inputted together with the target refresh command TREF may correspond to a row hammer address ADD_RH, the row hammer address ADD_RH (i.e., RH_ADD ofFIG.11) provided from the memory controller100may be provided as the target address TADD.

The aging decoder252may generate first to eighth aging bank signals AG_BK<0:7> respectively corresponding to the first to eighth banks BK0 to BK7, by decoding the bank address BA<0:3> according to the aging signal AG_EN.

The refresh decoder253may generate first to eighth target refresh bank signals TREF_BK<0:7> respectively corresponding to the first to eighth banks BK0 to BK7, by decoding the bank address BA<0:3> according to the target refresh command TREF.

The period adjusting circuit254may generate first to eighth period control signals SR_EN_BK<0:7> for adjusting the refresh period (refresh rate) of the first to eighth banks BK0 to BK7, according to the first to eighth aging bank signals AG_BK<0:7>, respectively. The period adjusting circuit254may have a configuration and operation substantially the same as the period adjusting circuit234ofFIG.6.

The output control circuit255may generate the first to eighth bank refresh signals SR_BK<0:7>, according to the first to eighth target refresh bank signals TREF_BK<0:7> and the first to eighth period control signals SR_EN_BK<0:7>. The output control circuit255may have a configuration and operation substantially the same as the output control circuit235ofFIG.6.

The row control circuit212may activate a word line WL corresponding to the internal address IADD according to an active command ACT, and precharge the activated word line WL according to a precharge command PCG. The row control circuit212may perform a normal refresh operation of sequentially refreshing the plurality of word lines WL corresponding to a counting address according to a normal refresh command REF. The row control circuit212may perform a target refresh operation of refreshing one or more neighboring word lines of a word line WL corresponding to the target address TADD according to the target refresh command TREF (i.e., first to eighth bank refresh signals SR_BK<0:7>).

As described above, in the memory system10in accordance with the second embodiment, the memory controller100may generate the aging signal AG_EN and the row hammer address RH_ADD corresponding thereto, by analyzing a case where the row hammer risk is high when the active aggressor is concentrated only on particular addresses, due to a special occurrence such as hacking. The semiconductor memory device200may adjust the target refresh period (or cycle) for each bank according to the aging signal AG_EN. Accordingly, the memory system10may achieve the row hammer mitigation with a minimum area.

It should be noted that although the technical spirit of the disclosure has been described in connection with embodiments thereof, this is merely for description purposes and should not be interpreted as limiting. It should be appreciated by one of ordinary skill in the art that various changes may be made thereto without departing from the technical spirit of the disclosure and the following claims.

For example, for the logic gates and transistors provided as examples in the above-described embodiments, different positions and types may be implemented depending on the polarity of the input signal.