Pitch-halving integrated circuit process and integrated circuit structure made thereby

A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner. The above patterns are trimmed. A spacer is formed on the sidewalls of each base line pattern and the corresponding hammerhead pattern, including a pair of derivative line patterns, a loop pattern around the hammerhead pattern, and a turning pattern at the other end of the base line pattern. The base line patterns and the hammerhead patterns are removed. A portion of each loop pattern and at least a portion of each turning pattern are removed to disconnect each pair of derivative line patterns.

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to integrated circuit (IC) fabrication, and particularly to a pitch-halving IC process and an IC structure made by the same process.

2. Description of Related Art

The resolution in a photolithography process depends on the wavelength of the exposure light, the numerical aperture (NA) of the optical system and the design of the photomask, and has a certain limit according to the exposure conditions. When the resolution required by an array of patterns exceeds the resolution of the lithographic system, for example, in a case of forming the gate line array of a high-density memory like a DRAM of next generation, a pitch reduction method is needed, mainly based on the spacer forming technique.

For example, patterns of dense conductive lines beyond lithographic resolution can be formed as follows. Parallel base line patterns are lithographically defined and trimmed, linear spacers having a smaller width/pitch and a double number are formed on the sidewalls of the base line patterns, and then the base line patterns are removed, leaving the linear spacers as the target line patterns beyond the lithographic resolution.

However, the contact pads of such small-pitch conductive lines are difficult to form at the line ends, due to their larger width for sufficient electrical contact.

SUMMARY OF THE INVENTION

In view of the foregoing, this invention provides a pitch-halving IC process, which is particularly suitable for definition and formation of dense conductive lines beyond the lithographic resolution and their contact pads.

This invention also provides an IC structure that is made by the pitch-halving IC process of this invention.

The pitch-halving IC process of this invention is described as follows. A plurality of parallel base line patterns is formed over a substrate, each being connected with a hammerhead pattern at a first side or a second side of the plurality of base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner. Each base line pattern and each hammerhead pattern are trimmed. A spacer is then formed on the sidewalls of each base line pattern and the corresponding hammerhead pattern, including a pair of derivative line patterns, a loop pattern around the hammerhead pattern, and a turning pattern at an end of the base line pattern without the corresponding hammerhead pattern. The base line patterns and the hammerhead patterns are then removed. A portion of each loop pattern and at least a portion of each turning pattern are removed to disconnect each pair of derivative line patterns, wherein the remaining loop pattern includes two contact pad patterns.

In an exemplary embodiment, the above process further includes transferring the patterns of the derivative line patterns and the remaining loop patterns to an underlying conductive layer. The patterned underlying conductive layer includes: a plurality of conductive lines corresponding to the derivative line patterns, and a plurality of contact pads corresponding to the remaining loop patterns. In another exemplary embodiment, the derivative line patterns and the remaining loop patterns are directly conductive lines and their contact pads, respectively.

In addition, the pitch-halving IC process of this invention may further include forming a plurality of contact plugs over the contact pads.

The IC structure includes of this invention a plurality of parallel conductive lines and their contact pads. The conductive lines are arranged in a plurality of pairs. Each contact pad is connected with a conductive line at one end thereof, wherein the two contact pads of each pair of conductive lines form an opened loop, the opened loops are arranged at a first side and a second side of the plurality of conductive lines alternately, and the opened loops at the first or second side are arranged in a staggered manner.

The above IC structure may further comprise a plurality of contact plugs over the contact pads.

By arranging the hammerhead patterns at the same side of the base line patterns in a staggered manner and utilizing the loop patterns formed as spacers around the hammerhead patterns to form the contact pad patterns, this invention allows the contact pads of the dense conductive lines to be formed with a sufficient distance between each other as well as in a high die-area utilization efficiency.

In order to make the aforementioned and other objects, features and advantages of this invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.

DESCRIPTION OF EMBODIMENTS

This invention is further explained with the following embodiments referring to the accompanying drawings, which are not intended to limit the scope of this invention. For example, though the outer hammerhead patterns at the first side and the second side of the plurality of base line patterns have the same dimension as the inner ones in the direction perpendicular to the line, they can alternatively have a greater dimension in the perpendicular direction, as long as a sufficient distance can be provided between the two loop patterns formed around any two neighboring outer hammerhead patterns to make a sufficient distance between the two neighboring contact plugs that will be defined from the two loop patterns latter.

FIGS. 1,2,3and4illustrate, in a top view, a pitch-halving IC process according to an embodiment of this invention, andFIGS. 1A,2A,3A and4A respectively illustrate, in a cross-sectional view along the line A-A′, the structures illustrated inFIGS. 1,2,3and4, respectively.

Referring toFIGS. 1 and 1A, a conductive layer102, an etching mask layer103, an anti-reflection coating (ARC)104, and a patterned photoresist layer106a+bof positive or negative type are formed over a substrate100in sequence. The conductive layer102may include doped poly-Si, metal or a combination thereof. The etching mask layer103may include a carbon layer. The substrate100as provided may have been formed with other material layer. For example, in a case where the conductive layer102is to be defined into gate lines, the substrate has been formed with a gate dielectric layer, such as a gate oxide layer or a high-k layer, before the conductive layer102is formed. The patterned photoresist layer106a+bis defined by a lithography process.

The patterned photoresist layer includes a plurality of parallel base line patterns106a, each of which is connected with a hammerhead pattern106bat a first side12or a second side14of the plurality of base line patterns106a. The hammerhead patterns106bare arranged at the first side12and the second side14alternately, while the hammerhead patterns106bat the first side12or the second side14are arranged in a staggered manner. In addition, when the process of this invention is applied to form half-pitch conductive lines of a high-density memory array, there is an array area10on the substrate100, in which almost the entirety of each base line pattern106ais located. The high-density memory array may be a high-density DRAM array.

It is noted that though the hammerhead patterns106bat the first side12or the second side14as illustrated herein include only inner and outer sets of hammerhead patterns that are arranged in a 2-tiered manner, this invention is not limited thereto. The hammerhead patterns106bat each side may alternatively include multiple levels or multiple tiers of staggered hammerhead patterns, such as 3 or 4 levels of staggered hammerhead patterns.

Though the base line patterns106aand the hammerhead patterns106binclude a photoresist material and are defined by a lithography process in the above case, the base line patterns and hammerhead patterns formed in this invention are not limited thereto. They may alternatively include other material that can be trimmed narrowed, such as a suitable hard mask material, e.g., SiOx, Si3N4, carbon or poly-Si, etc. In such a case, the base line patterns and hammerhead patterns are defined by a patterned photoresist layer (not shown), and no anti-reflection coating is required under the unpatterned layer (not shown) from which the base line and hammerhead patterns are defined.

Referring toFIGS. 2 and 2A, each of the base line patterns106aand each of the hammerhead patterns106bare trimmed to be narrower. When the base line patterns106aand the hammerhead patterns106binclude a photoresist material, the trimming may utilize a dry etching process.

Thereafter, a spacer110a+b+cis formed on the sidewalls of each trimmed base line pattern106cand the corresponding trimmed hammerhead pattern106d, including a pair of derivative line patterns110a, a loop pattern110baround the trimmed hammerhead pattern106d, and a turning pattern110cat the end of the trimmed base line pattern106cwithout the corresponding trimmed hammerhead pattern106d. The spacers are usually formed by depositing a substantially conformal material layer on the trimmed (photoresist) patterns106cand106dand the exposed portions of the ARC104and then anisotropically etching the same, such that only the portions of the material layer on the vertical sidewalls of the trimmed patterns106cand106dremain but the portions of the same on the horizontal surfaces are removed, wherein the material layer may include silicon oxide. The width of each spacer or derivative line pattern110ais controlled by the deposition thickness. The spacers may include low-temperature oxide (LTO) or ALD (atomic layer deposition) oxide when the base line patterns106aand the hammerhead patterns106binclude a photoresist material. When the base line patterns and the hammerhead patterns include a hard mask material, the spacers may include another material that can have a much lower removal rate than the hard mask material, such as SiOx, Si3N4, carbon or poly-Si.

Referring toFIGS. 3 and 3A, all of the trimmed base line patterns106cand the trimmed hammerhead patterns106dare removed, possibly by using O2-plasma ashing or solvent stripping, leaving the derivative line patterns110a, the loop patterns110band the turning patterns110c(FIG. 2). For example, when the base line patterns106aand the hammerhead patterns106binclude a photoresist material and the spacers include LTO, oxygen plasma can be used to remove the trimmed base line patterns106cand the trimmed hammerhead patterns106d.

Thereafter, each turning pattern110cand a portion of each loop pattern110bare removed to disconnect each pair of derivative line patterns110a, such that each remaining loop pattern110dincludes two contact pad patterns. The removed portions of the loop patterns110band the removal of the turning patterns110ccan be defined by chop openings120aand120b, respectively. The chop openings120aand120bare lithographically formed in a mask layer, such as a photoresist layer.

In addition, though each turning pattern110cis entirely removed in the above case, it is feasible to remove just a portion of each turning pattern110cas long as the connection between the corresponding pair of derivative line patterns110ais broken.

Referring toFIGS. 4 and 4A, after the patterned mask layer having the chop openings120aand120btherein is removed, the patterns of the derivative line patterns110aand the remaining loop patterns110dare transferred to the underlying etching mask layer103and then to the underlying conductive layer102, basically by etching the etching mask layer103and the conductive layer102with the derivative line patterns110aand the remaining loop patterns110das a mask. The remaining etching mask layer103that serves as an etching mask during the final etching stage is then removed or stripped away to leave only the patterned conductive layer102. The patterned conductive layer102includes a plurality of conductive lines102acorresponding to the derivative line patterns110a, and a plurality of contact pads102bcorresponding to the remaining loop patterns110d. The conductive lines102amay serve as a plurality of conductive lines of a memory array, such as the word lines of a memory array. The memory array may be a DRAM array.

Then, a plurality of contact plugs130are formed over the contact pads102b, wherein each contact plug130is formed over a contact pad102b. The contact plugs130may include a metal, such as tungsten (W).

Though the derivative line patterns110aand the remaining loop patterns110dare formed for defining an underlying conductive layer102into half-pitch conductive lines and their contact pads in the above case, this invention is not limited thereto. It is also possible to omit an underlying conductive layer, choose a suitable material for the base line and hammerhead patterns, and form a conductive spacer, such as a metal (e.g., TiN) spacer, on the sidewalls of each trimmed base line pattern and the corresponding trimmed hammerhead pattern, including a pair of conductive derivative lines and a conductive loop pattern. Thus, after the trimmed base line patterns and the trimmed hammerhead patterned are all removed and each conductive loop pattern is partially removed through an aforementioned chop opening, the derivative lines and the opened loop patterns can directly serve as conductive lines and their contact pads.

On other hand, when the original base line patterns106ahave a line/space (L/S) width of F1/F1, each trimmed base line pattern106chas a feature size F2, each derivative line pattern110aalso has a feature size of F2, and F2=0.5 F1, the derivative line patterns110ahave a constant pitch of 2F2(=F1). In an embodiment, F1is the lithography-limit feature size, F2=0.5 F1, the original base line patterns106ahave an L/S width of F1/F1substantially, the trimmed base line patterns106chave an L/S width of F2/3F2substantially, the derivative line patterns110ahave an L/S width of F2/F2substantially, so that a maximal density of the derivative line patterns110awith a constant pitch of 2F2are formed.

FIG. 4also illustrates an IC structure according to the above embodiment of this invention. The structure includes a plurality of parallel conductive lines102aarranged in a plurality of pairs, and a plurality of contact pads102b. Each contact pad102bis connected with a conductive line102aat one end of the conductive line102a, wherein the two contact pads102bof each pair of conductive lines102aform an opened loop102c. The opened loops102care arranged at a first side12and a second side14of the plurality of conductive lines102aalternately, and the opened loops102cat the first side12or the second side14are arranged in a staggered manner.

The conductive lines102amay have an L/S width of 0.5 F/0.5 F substantially, wherein F is the lithography-limited feature size. Such conductive lines102amay serve as dense conductive lines of a high-density memory array, such as dense word lines of a high-density memory array. The memory array may be a DRAM array.

As described above, by arranging the hammerhead patterns at the same side of the base line patterns in a staggered manner and utilizing the loop patterns formed as spacers around the hammerhead patterns to form the contact pad patterns, this invention allows the contact pads of the dense conductive lines to be formed with a sufficient distance between each other as well as in a high die-area utilization efficiency. This allows larger contacts to be defined while lowering the risk of shorting to an adjacent contact or corresponding landing pad. It is well known that defining larger contacts is easier than defining smaller contacts.

The method of this invention also allows for more overlay or registration error between the contact layer and the underlying word line layer, as explained above.

This invention has been disclosed above in the preferred embodiments, but not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.