Multi-port memory cell

An improved multi-port memory cell circuit which has a smaller number of write lines and/or transistors than conventional multi-port memory cells, and hence occupies a smaller area, is provided. The reduced area memory cell circuit includes: word lines associated with each bit line of a set of bit lines; a first word line for selecting a subset of the set of bit lines; a second word line for selecting a bit line of the subset of bit lines; and a memory cell for storing a bit value on the selected bit line.

FIELD OF THE INVENTION

The invention relates generally to the field of circuit design, and in particular to an improved multi-port memory cell.

BACKGROUND OF THE INVENTION

In super-scalar, Very Long Instruction Word (VLIW) processors and in network processors, memory cells with multiple write ports are typically required. These multiple write ports are associated with multiple bit lines that allow both writing the same data to many memory cells as well as allowing direct communication paths from the multiple execution units to one memory cell.

Prior art multi-port register memory cells used a single write word line for each differential write bit line or a differential write word line for each single write bit line. Using differential word or bit lines caused a large line count which in turn increased the layout area for the memory cell.

FIG. 1 is an example of another prior art multi-write port memory cell. FIG. 1 was a first step in reducing the layout area over the above differential word or bit line memory cell. For illustration purposes, only the write ports are shown. FIG. 1 shows only one memory cell in an array of memory cells in a multi-port register file. The memory cell has back-to-back inverters 156 and 158 , which have nodes 152 and 154 . There are six word lines (WLs), i.e., WLA, WLB, WLC, WLD, WLE, and WLF, and six write ports shown by six data bit lines (BLs), i.e., BLA, BLB, BLC, BLD, BLE, and BLF. There is a one-to-one correspondence between a write word line and a write bit line (i.e., a write port). For example, word line WLA has transistor 112 which is a switch to allow a connection of bit line BLA to node 152 . Word line WLA also is connected to transistor 114 , which is a switch to allow a connection to ground of node 154 through transistor 140 , when bit line BLA is 1 . The one-to-one correspondence holds also for WLB and BLB, WLC and BLC, WLD and BLD, WLE and BLE, and WLF and BLF.

An example of the operation of the circuit 110 in FIG. 1 is when word line WLA is 1 . Transistors 112 and 114 are turned on. Subsequently, if bit line BLA is 1 , transistor 140 is turned on and pulls node 154 down to ground gnd. The bit line BLA value of 1 goes through transistor 112 to node 152 . Back-to-back inverters 156 and 158 will maintain node 152 at 1 and node 154 at 0 . Similarly, for example, when word line WLD is 1 , transistors 122 and 124 are turned on. If bit line BLD is 1 , then transistor 146 is turned on pulling node 154 to ground gnd. Node 152 has the value of bit line BLD. If bit line BLD is 0 then transistor 146 is off. Node 152 is pulled to 0 and node 154 is pulled to 1 by inverter 156 .

A conventional final decoding circuit of the prior art, applicable to FIG. 1 , is shown in FIG. 2 . This example assumes that addresses for write ports A through F, i.e., word lines WLA to WLF of FIG. 1 , have been pre-decoded, such that the final decode consists of a 2-input AND gate, implemented here using a dynamic circuit. For instance the AND gate of port A includes a transistor 214 with address input A 0 and a transistor 216 with an address input A 1 . The signal pc is a precharge signal, usually a clock signal. When pc 0 , node 213 is precharged to a 1 via transistor 212 . An AND gate, i.e., transistor 214 connected in series to transistor 216 , is disabled because transistor 218 is turned off. The address A 0 and A 1 is then read when pc 1 . Transistor 218 is turned on, hence enabling the AND gate, i.e., transistors 214 and 216 . Node 213 is pulled to ground when both A 0 and A 1 are 1 , otherwise node 213 remains 1 . When node 213 is 0 , WLA is 1 via inverter 270 . The other five AND gates having address lines B 0 , B 1 to F 0 , F 1 operate in a similar manner as the AND gate for A 0 , A 1 . The outputs of decoder circuit 210 are word lines WLA to WLF which is then input into word lines WLA to WLF of FIG. 1 .

While the circuit of FIG. 1 gives a reduced area compared to its predecessors, there is still need for improvement, because there is a continuing demand for more memory in a smaller area. Thus a new circuit is needed which uses less area than the prior art.

SUMMARY OF THE INVENTION

The present invention provides an improved multi-port memory cell circuit which has fewer write lines than conventional multi-port memory cells, and hence occupies a smaller area. In addition, according to the preferred embodiment, there are fewer transistors than FIG. 1 . Power consumption may also be reduced.

One embodiment of the present invention comprises a method for reducing an area of a memory cell circuit, where the memory cell includes a first plurality of bit lines and a plurality of word lines associated with each bit line. First, a first word line is used for selecting a second plurality of bit lines from the first plurality of bit lines. Next a second word line is used for selecting a bit line of the second plurality of bit lines. And then, a bit value on the bit line is stored in a memory cell.

An aspect of the present invention includes a reduced area memory cell circuit comprising: a plurality of word lines associated with each bit line of a first plurality of bit lines; a first word line of the plurality of word lines for selecting a second plurality of bit lines from the first plurality of bit lines; a second word line of the plurality of word lines for selecting a bit line of the second plurality of bit lines; and a memory cell for storing a bit value on said bit line.

Another embodiment of the present invention comprises a memory cell circuit comprising: a memory cell for storing data; a first word line and a second word line; a plurality of bit lines; a first switch controlled by the first word line, where the first switch connects a first bit line of said plurality of bit lines to a first node; and a second switch controlled by the second word line, where the second switch connects the first node to the memory cell.

Yet another embodiment of the present invention comprises a system for writing data to a memory cell. The system comprises: a first multiplexer for selecting a first bit line of a plurality of bit lines, when a first word line selects the first bit line; a second multiplexer for selecting a second bit line of the plurality of bit lines, when the first word line selects the second bit line; and a third multiplexer for selecting between an output of the first multiplexer and an output of the second multiplexer based on a second word line, wherein an output of the third multiplexer writes data to the memory cell.

A further embodiment of the present invention comprises a system for providing a plurality of selector signals to a first multiplexer and a second multiplexer, wherein the first multiplexer receives data from a bit line having a bit line address, and wherein the second multiplexer receives data from the first multiplexer and writes the data to a memory cell. The system comprises: a first plurality of decoders for receiving a first plurality of bit line addresses and producing a first plurality of write enable signals; at least one logic gate for combining the first plurality of write enable signals into a first selector signal of the plurality of selector signals, where the first selector signal controls the first multiplexer; a second plurality of decoders for receiving a second plurality of bit line addresses and producing a second plurality of write enable signals; and at least one logic gate for combining a write enable signal of the first plurality of write enable signals and a write enable signal of the second plurality of write enable signals into a second selector signal of the plurality of selector signals, where the second selector signal controls the second multiplexer.

Another aspect of the present invention provides a memory cell circuit having a first plurality of bit lines. The memory cell circuit includes: means for selecting a second plurality of bit lines from the first plurality of bit lines; means for selecting a bit line of the second plurality of bit lines; and means for writing a bit value on the bit line to a memory cell.

These and other embodiments, features, aspects and advantages of the invention will become better understood with regard to the following description, appended claims and accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It is apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention.

The circuit of FIG. 1 may be viewed as a single six input multiplexer (bit lines BLA to BLF) with six selector lines (word lines WLA to WLF), where a multiplexer, as used herein, is a circuit for selecting one of a number of inputs and switching its information to the output or outputs. In FIG. 1 , each word line selects the associated bit line, for example, word line WLA selects bit line BLA. In order to reduce the number of word lines one preferred embodiment of the present invention uses a plurality of smaller cascaded multiplexers with each word line now selecting one or more bit lines.

FIG. 3 is a schematic of a multi-write port memory cell of an embodiment of the present invention. Circuit 300 has five word lines, i.e., WLAB, WLCD, WLEF, WLBDF, and WLACE, and six bit lines, i.e., BLA, BLB, BLC, BLD, BLE, and BLF. The letters following WL in the word line labels were picked to indicate in the alternative which bit line may be selected, when the word line is asserted. For example, when word line WLAB is asserted, then either bit line BLA or BLB may be selected, or when word line WLBDF is asserted, then either bit line BLB, BLD, or BLF may be selected. Word line WLAB is connected to the gates of transistors m 3 and m 4 . Word line WLCD is connected to the gates of transistors m 2 and m 5 . Word line WLEF is connected to the gates of transistors m 1 and m 6 . Word line WLBDF is connected to the gates of transistors m 7 and m 11 . One conduction terminal of transistor m 7 is connected to transistors m 4 , m 5 , and m 6 via node n 1 . The other conduction terminal of transistor m 7 is connected to node n 4 . Transistor m 11 is connected to transistor m 12 and to node n 3 . The gate of the transistor m 12 is connected to transistors m 4 , m 5 and m 6 via node 1 . Word line WLACE is connected to the gates of transistors m 8 and m 10 . One conduction terminal of transistor m 8 is connected to transistors m 1 , m 2 , and m 3 via node n 2 . The other conduction terminal of transistor m 8 is also connected to node n 4 . Transistor m 10 is connected to transistor m 9 . The gate of transistor m 9 is connected to transistors m 1 , m 2 , and m 3 via node n 2 . Back-to-back inverters Inv 1 and Inv 2 form the one bit memory cell. The output of inverter Inv 1 is connected to the input of inverter Inv 2 via node n 3 . The output of inverter Inv 2 is connected to the input of inverter Inv 1 via node n 4 . Bit line BLE is connected to transistor m 1 . Bit line BLC is connected to transistor m 2 . Bit line BLA is connected to transistor m 3 . Bit line BLB is connected to transistor m 4 . Bit line BLD is connected to transistor m 5 . Bit line BLF is connected to transistor m 6 .

In FIG. 3 the word lines are asserted (i.e., set to 1 ) in pairs in order to select one of the bit lines: 1) word line WLBDF with word line WLAB, WLCD, or WLEF, or 2) word line WLACE with word line WLAB, WLCD, or WLEF. When word line WLAB is asserted, then transistors m 3 and m 4 are turned on selecting bit lines BLA and BLB, respectively. When word line WLCD is asserted, then transistors m 2 and m 5 are turned on selecting bit lines BLC and BLD, respectively. When word line WLEF is asserted, then transistors m 1 and m 6 are turned on selecting bit lines BLE and BLF, respectively. When word line WLBDF is asserted, transistors m 7 and m 11 are turned on, hence selecting bit line BLB, BLD, or BLF depending on which word line, i.e., WLAB, WLCD, or WLEF, respectively, is asserted. When word line WLACE is asserted, transistors m 8 and m 10 are turned on, hence selecting bit line BLA, BLC, or BLE depending on which word line, i.e., WLAB, WLCD, or WLEF, respectively, is asserted. The selected bit line then may set the value of the memory cell (e.g., node n 4 ) to 0 or 1 .

When, for example, word lines WLEF and WLBDF are asserted, bit line BLF is selected. As WLBDF turns on transistors m 7 and m 11 , the value on BFL sets node n 4 . If the value is 1 , then m 12 is turned on and node n 3 is pulled to ground gnd. If the value is 0 , then node n 3 is changed by node n 4 via inverter Inv 1 . When word line WLACE is asserted instead of WLBDF, then bit line BLE is selected instead of BLF. Then, the value on BLE sets node n 4 similar to when BLF sets node n 4 when WLBDF is asserted.

FIG. 4 is a schematic of a final line decoding circuit 410 corresponding to the memory cell circuit 300 of FIG. 3 of an embodiment of the present invention. FIG. 4 is similar to final decode circuit of FIG. 2 , except the inverters of FIG. 2 have been replaced by NAND gates in FIG. 4 . As in FIG. 2 when address lines, e.g., A 0 and A 1 are 1 , then the value on the corresponding bit line, in this case BLA in FIG. 3 , is written to the memory cell. With A 0 and A 1 at 1 NAND gate 420 and NAND gate 424 asserts word line WLACE and WLAB, respectively. With B 0 and B 1 at 1 NAND gate 422 and NAND gate 424 asserts word line WLBDF and WLAB, respectively. With C 0 and C 1 at 1 NAND gate 420 and NAND gate 426 asserts word line WLACE and WLCD, respectively. With D 0 and D 1 at 1 NAND gate 422 and NAND gate 426 asserts word line WLBDF and WLCD, respectively. With E 0 and E 1 at 1 NAND gate 420 and NAND gate 428 asserts word line WLACE and WLEF, respectively. With F 0 and F 1 at 1 NAND gate 422 and NAND gate 428 asserts word line WLBDF and WLEF, respectively. Thus, for example, assertion of WLAB causes the write data on BLA to be written to node n 2 through transistor m 3 in FIG. 3 . At the same time, the assertion of WLACE causes the data on node n 2 to be written onto node n 4 through transistor m 8 .

FIG. 5 is a re-arranged schematic of FIG. 3 showing an example of cascading multiplexers of an aspect of the present invention. The circuits of FIG. 3 and FIG. 5 operate in the same way. The multiplexers are in two stages. The first stage has multiplexers 510 and 512 . Multiplexer 510 includes transistors m 1 , m 2 , and m 3 which act as switches. There are three input data lines to multiplexer 510 , bit lines BLA, BLC, and BLE with selector lines WLAB, WLAC, and WLEF, respectively. The output of multiplexer 510 is node n 1 . Multiplexer 512 includes transistors m 4 , m 5 , and m 6 which act as switches. There are three input data lines to multiplexer 512 , bit lines BLB, BLD, and BLF with selector lines WLAB, WLAC, and WLEF, respectively. The output of multiplexer 512 is node n 2 . Multiplexer 520 has two inputs at nodes n 1 and n 2 from multiplexers 510 and 512 , respectively. The selector lines for multiplexer 520 are WLACE and WLBDF. WLACE is used to select multiplexer 510 and WLBDF is used to select multiplexer 512 . There is a differential output of multiplexer 520 with the output at node n 3 and the inverted output at node n 4 . When WLACE is 1 , then node n 3 is set equal to the value at node n 1 , as transistor m 7 is turned on. When WLBDF is 1 , then node n 3 is set equal to the value at node n 2 , as transistor m 8 is turned on. The memory cell 525 includes back-to-back inverters Inv 1 and Inv 2 .

FIG. 6 is a schematic of a generalized memory cell circuit for n*m write ports (i.e., write bit lines) of another embodiment of the present invention, where the variables n and m are positive numbers. Preferably, n>1 and m>2. As shown in FIG. 6 , the memory cell circuit 610 comprises n instances of m-to- 1 NMOS pass-gate multiplexers 612 , 614 , to 616 , followed by a single n-to- 1 multiplexer 618 , followed by a back-to-back inverter pair, i.e., memory cell 688 , that stores the data. The bit lines (i.e., write ports) are labeled BL 11 to BLnm. The bit lines can be viewed as n groups with m bit lines, e.g., BL 11 , BL 12 , . . . , BL 1 m, in each group. The word lines are labeled WL 11 to WL 1 m and WL 21 to WL 2 n, where word lines WL 11 to WL 1 m are the selector lines for multiplexers 612 , 614 to 616 and word lines WL 21 to WL 2 m are the selector lines for multiplexer 618 .

The selector lines to the first stage of multiplexers 612 , 614 to 616 , are set up so that, when a word line is asserted, one bit line per multiplexer is selected. For example, when word line WL 11 is selected, transistors 620 , 630 , to 640 are turned on and bit lines BL 11 , BL 21 , to BLn 1 are selected to go to multiplexer outputs 626 , 636 , to 646 , respectively. When word line WL 12 is selected, transistors 622 , 632 , and 642 are turned on and bit lines BL 12 , BL 22 , to BLn 2 are selected to go to multiplexer outputs 626 , 636 , to 646 , respectively. And so on, until when word line WL 1 m is selected, transistors 624 , 634 , to 644 are turned on and bit lines BL 1 m, BL 2 m, to BLnm are selected to go to multiplexer outputs 626 , 636 , to 646 , respectively.

The selector lines to the second stage multiplexer 618 select which output from the first stage multiplexers 612 , 614 to 616 is sent to node 680 , i.e., one input into the memory cell of back-to-back inverters 684 and 686 . When word line WL 21 is asserted, multiplexer 612 is selected and its output 626 is sent to node 680 . When word line WL 22 is asserted, multiplexer 614 is selected and its output 636 is sent to node 680 . And so on until, when word line WL 2 n is asserted, multiplexer 616 is selected and its output 646 is sent to node 680 . Similar to the operation of FIG. 3 , when, for example, WL 21 is asserted and output 626 is 1 , transistors 654 and 656 are turned on and node 682 is pulled to ground at the same time node 680 is pulled to 1 (as transistor 652 is also turned on).

In an alternative embodiment of circuit 610 of FIG. 6 the transistors 654 , 656 , 662 , 664 , to transistors 672 , and 674 are not present. Transistors 654 and 656 are used to pull node 682 to 0 when transistor 652 is pulling node 680 to 1 . Transistors 662 and 664 are used to pull node 682 to 0 when transistor 660 is pulling node 680 to 1 . Transistors 672 and 674 are used to pull node 682 to 0 when transistor 670 is pulling node 680 to 1 . Without transistors 654 , 656 , 662 , 664 , 672 , and 674 , multiplexer 618 looks similar to the structure of the first stage multiplexers, e.g., multiplexer 612 .

FIG. 7 is a schematic of a generalized circuit for providing the word line signals for circuit 610 of FIG. 6 of another embodiment of the present invention. The Addresses 701 , 702 , 703 , 704 , 705 , 706 , 707 , 708 , and 709 are sent by, for example, a processor, to select one or more of the bit lines BL 11 , BL 21 , BLn 1 , BL 12 , BL 22 , BLn 2 , BL 1 m, BL 2 m, and BLnm, respectively, of FIG. 6 . Each address label has one or more address signal lines connecting it to a decoder. The bit line addresses 701 , 702 , to 703 are connected to decoders 712 , 714 , to 716 , respectively, which decode the address signals to give write enable signals we_ 11 , we_ 21 , to we_n 1 , respectively. These write enable signals are then combined using an OR gate 740 to give word line signal WL 11 , that is used as a select signal for multiplexers 612 , 614 , to 616 of FIG. 6 . The bit line addresses 704 , 705 , to 706 are connected to decoders 720 , 722 , to 724 , respectively, which decode the address signals to give write enable signals we_ 12 , we_ 22 , to we_n 2 , respectively. These write enable signals are then combined using an OR gate 742 to give word line signal WL 12 , that is used as another select signal for multiplexers 612 , 614 , to 616 of FIG. 6 . The bit line addresses 707 , 708 to 709 are connected to decoders 730 , 732 , to 734 , respectively, which decode the address signals to give write enable signals we_ 1 m, we_ 2 m, to we_nm, respectively. These write enable signals are then combined using an OR gate 744 to give word line signal WL 1 m, that is used as yet another select signal for multiplexers 612 , 614 , to 616 of FIG. 6 .

The word line select signals used for the first stage of multiplexers in FIG. 6 , i.e., multiplexers 612 , 614 , to 616 , can also be expressed by the following Boolean equations:

where denotes the logical OR operator, and we_ij is the write enable (decoded address) for bit line BLij. The write enable signal we_ij has value 1 , when the address for bit line BLij indicates that the bit line has been selected. While, normally for this memory cell, only one bit line is selected to supply the data to be written to this memory cell, one or more of the other memory cells also may have data written to them simultaneously. This allows another memory cell with the same bit lines to be written to from another bit line at the same time this memory cell is being written to. Thus performance is increased compared with writing to the two memory cells serially.

The above write enable signals are combined together differently to produce the word lines used as select lines for the second stage multiplexer 618 of FIG. 6 . Write enable signals we_ 11 , we_ 12 to we_ 1 m are input into OR gate 750 to produce word line WL 21 . Write enable signals we_ 21 , we_ 22 to we_ 2 m are input into OR gate 752 to produce word line WL 22 . Write enable signals we_n 1 , we_n 2 to we_nm are input into OR gate 754 to produce word line WL 2 m.

The word line select signals used for the second stage of multiplexers in FIG. 6 , i.e., mux 2 , can also be expressed by the following Boolean equations:

From the Boolean logic equivalence of NOT(NOT(X) AND NOT(Y)) X OR Y, the circuit 810 of FIG. 8 can be modified to be a subset of the circuit 710 of FIG. 7 with n 2 and m 3. Each precharge circuit of FIG. 8 , e.g., precharge circuit having transistors 212 , 214 , 216 , 218 , has a write enable bar output, i.e., we_b_ 11 , and thus has an inverted output being input into the appropriate NAND gates, e.g., 420 and 424 . Adding an inverter (not shown) to the output of each precharge circuit and applying the above Boolean logic equivalence, the NAND gates, i.e., 420 , 422 , 424 , 426 , and 428 , may be replaced by OR gates. Thus each decoder in FIG. 7 can be implemented in one embodiment of the present invention by a precharge circuit, e.g., a precharge circuit having transistors 212 , 214 , 216 , 218 , with its write enable bar output, i.e., we_b_ 11 , connected to a converter, to produce, e.g., we_ 11 and the NAND gates, e.g., 420 , replaced by OR gates. In other embodiments, the decoder may either fully or partially decode the bit line address and need not be the final decode stage. In addition, in other embodiments the OR gates are replaced by any logically equivalent gates in order to produce the select signals for the multiplexers of FIG. 6 .

Table 1 shows how embodiments of this invention reduce the number of write word lines and transistors for various numbers of bit lines compared to FIG. 1 . The number of word lines required in the prior art is equal to the number of bit lines. From FIG. 1 , the prior art has three transistors per bit line.

TABLE 1 Number of No. Word No. of Word lines Transistors bit lines n m lines transistors saved saved 6 2 3 5 12 1 6 8 2 4 6 14 2 10 9 3 3 6 18 3 9 10 2 5 7 20 3 10 12 3 4 7 24 5 12 As can be seen from Table 1 above, the number of word lines in an embodiment of the present invention (n m), while in the prior art the number of word lines is (n*m). The general trend is that as the number of bit lines increases, the number of word lines saved and the number of transistors saved increases. In any case there is a savings when the number of write ports increases.

Some of the advantages of embodiments of the invention compared to the prior art include: both fewer transistors and fewer word lines passing through the memory cell; a smaller bit line capacitance (e.g., one NMOS drain per bit line in FIG. 3 compared to one NMOS drain and one NMOS gate in FIG. 1 ); and fewer word lines to drive. Thus there is a smaller area and lower power consumption for the memory cell circuit of embodiments of the present invention.

The specification and drawings are provided for illustrative purposes. It will be evident that additions, subtractions, deletions, and other modifications and changes may be made there unto without departing from the broader spirit and scope of the invention as set forth in the claims.