Thin film transistor and manufacturing method thereof, display substrate and display apparatus

The disclosure provides a thin film transistor, a manufacturing method thereof, a display substrate and a display apparatus. The thin film transistor comprises a base substrate, and an active layer disposed on the base substrate, and the active layer comprises a channel region, and a source contact region and a drain contact region respectively positioned at two sides of the channel region; and a portion of at least one of the source contact region and the drain contact region close to the channel region includes a plurality of first sub-grooves disposed at a side of the active layer proximal to the base substrate and a plurality of second sub-grooves disposed at a side of the active layer distal to the base substrate, and the plurality of first sub-grooves and the plurality of second sub-grooves being alternately disposed along a direction parallel to an extension of the channel region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a National Phase Application filed under 35 U.S.C. 371 as a national stage of PCT/CN2020/083683, filed Apr. 8, 2020, an application claiming the benefit of Chinese Application No. 201910281442.0, filed Apr. 9, 2019, the content of each of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The disclosure relates to the field of display technology, and particularly relates to a thin film transistor and a manufacturing method thereof, a display substrate and a display apparatus.

BACKGROUND

When a thin film transistor is manufactured, a conductive treatment is performed on semiconductor portions on both sides of a channel region of an active layer. Due to the diffusion effect, there is also a risk that the channel region of the active layer is transformed into a conductor, which may cause poor uniformity of the thin film transistor, resulting in undesirable phenomena such as bright spots on the display panel.

SUMMARY

The present disclosure is directed to solving at least one of the technical problems of the related art and to providing a thin film transistor that effectively prevents a channel region of an active layer from being conducted.

The technical solution adopted for solving the technical problem of the disclosure is providing a thin film transistor including a base substrate and an active layer disposed on the base substrate, and the active layer includes a channel region, and a source contact region and a drain contact region respectively located at two sides of the channel region; and a portion of at least one of the source contact region and the drain contact region close to the channel region includes a plurality of first sub-grooves disposed at a side of the active layer proximal to the base substrate and a plurality of second sub-grooves disposed at a side of the active layer distal to the base substrate, and the plurality of first sub-grooves and the plurality of second sub-grooves are disposed alternately along a direction parallel to an extension of the channel region.

In some embodiments, the plurality of first sub-grooves and the plurality of second sub-grooves have a same depth.

In some embodiments, the thin film transistor further includes an insulating layer disposed between the active layer and the base substrate; and a side of the insulating layer proximal to the active layer is provided with a plurality of first grooves, the plurality of first grooves are provided in the insulating layer at positions corresponding to the at least one of the source contact region and the drain contact region of the active layer close to the channel region, the plurality of first grooves are in one-to-one correspondence with the plurality of second sub-grooves, and orthographic projections of the plurality of first grooves and the plurality of second sub-grooves on the base substrate are overlapped, respectively.

In some embodiments, the thin film transistor further includes a light-shielding layer disposed between the base substrate and the insulating layer.

In some embodiments, a side of the light-shielding layer proximal to the insulating layer is provided with a plurality of second grooves, the plurality of second grooves are provided in the light-shielding layer at positions corresponding to the at least one of the source contact region and the drain contact region of the active layer close to the channel region, the plurality of second grooves are in one-to-one correspondence with the plurality of second sub-grooves, and orthographic projections of the plurality of second grooves and the plurality of second sub-grooves on the base substrate are overlapped, respectively.

In some embodiments, the thin film transistor further includes a gate insulating layer, a gate, a source and a drain sequentially disposed on the active layer.

In some embodiments, a material of the light-shielding layer includes aluminum, molybdenum, or copper.

In some embodiments, the plurality of second grooves penetrate through the light-shielding layer.

The present disclosure also provides a method for manufacturing a thin film transistor including forming a base substrate, and forming an active layer on the base substrate such that the active layer includes a channel region, and a source contact region and a drain contact region respectively located at two sides of the channel region; and forming a plurality of first sub-grooves at a side of the active layer proximal to the base substrate and a plurality of second sub-grooves at a side of the active layer distal to the base substrate at a portion of at least one of the source contact region and the drain contact region of the active layer close to the channel region, and the plurality of first sub-grooves and the plurality of second sub-grooves are disposed alternately along a direction parallel to an extension of the channel region.

In some embodiments, the plurality of first sub-grooves and the plurality of second sub-grooves have a same depth.

In some embodiments, before the forming an active layer on the base substrate, the method further includes: forming an insulating layer on the base substrate, and forming a plurality of first grooves on a side of the insulating layer proximal to the active layer at positions corresponding to the portion of the at least one of the source contact region and the drain contact region of the active layer close to the channel region; and forming an active layer on the base substrate on which the insulating layer is formed, such that the plurality of first grooves are in one-to-one correspondence with the plurality of second sub-grooves and orthographic projections of the plurality of first grooves and the plurality of second sub-grooves on the base substrate are overlapped.

In some embodiments, before the forming an insulating layer on the base substrate, the method further includes forming a light-shielding layer on the base substrate.

In some embodiments, the forming a light-shielding layer on the base substrate includes: forming a light-shielding layer on a base substrate by a patterning process, and forming a plurality of second grooves on a side of the light-shielding layer proximal to the insulating layer at positions corresponding to the portion of the at least one of the source contact region and the drain contact region of the active layer close to the channel region, such that the plurality of second grooves are in one-to-one correspondence with the plurality of second sub-grooves, and orthographic projections of the plurality of second grooves and the plurality of second sub-grooves on the base substrate are overlapped, respectively.

In some embodiments, the method further includes forming a gate insulating layer on the active layer, and forming a gate, a source and a drain on the gate insulating layer.

In some embodiments, the thin film transistor is a top-gate thin film transistor.

In some embodiments, a material of the light-shielding layer includes aluminum, molybdenum, or copper.

In some embodiments, the plurality of second grooves penetrate through the light-shielding layer.

The present disclosure also provides a display substrate including a base substrate, and a thin film transistor disposed on the base substrate; and the thin film transistor includes any one of the thin film transistors described above.

The disclosure also provides a display apparatus including the above display substrate.

DETAILED DESCRIPTION

In order to make a person skilled in the art will better understand the technical solutions of the present disclosure, the following detailed description is given with reference to the accompanying drawings and the specific embodiments.

According to some embodiments of the present disclosure, as shown inFIG.1, the present embodiment provides a thin film transistor, which includes a base substrate1, and an active layer2, a gate insulating layer5, a gate6, a source and a drain sequentially disposed on the base substrate1, and the source and the drain includes a source7and a drain8. The active layer2includes a channel region21and a source contact region22and a drain contact region23respectively located at two sides of the channel region21; a portion of at least one of the source contact region22and the drain contact region23of the active layer2close to the channel region21includes a plurality of first sub-grooves25disposed at a side of the active layer2proximal to the base substrate1and a plurality of second sub-grooves24disposed at a side of the active layer2distal to the base substrate1, and the plurality of first sub-grooves25and the plurality of second sub-grooves24are disposed alternately along a direction parallel to an extension of the channel region21.

It should be noted that, the plurality of first sub-grooves24and the plurality of second sub-grooves25have a same depth.

It should be understood that, the source contact region22and the drain contact region23of the active layer2each are of a semiconductor structure, and the source contact region22is electrically coupled to the source7, and the drain contact region23is electrically coupled to the drain8.

As shown inFIG.1, in the present embodiment, a portion of at least one of the source contact region22and the drain contact region23of the active layer2close to the channel region21may be configured as a wave structure, such that the length of the active layer2is extended, particularly the length of the portion of the at least one of the source contact region22and the drain contact region23close to the channel region21is extended, and the thickness of the active layer2is reduced, thereby a transmission path of a conductive diffusion effect is extended effectively when the source contact region22and the drain contact region23of the active layer2are made to be conductive, which may eliminate an influence on the channel region21, thereby good performance and uniformity of the thin film transistor can be ensured. Meanwhile, in the active layer2with a wave structure, atoms of a material of the active layer2are arranged distorted and disordered, to prevent the conductive diffusion effect from reaching the channel region21, and good performance and uniformity of the thin film transistor can be ensured.

In some embodiments, the thin film transistor is a top-gate thin film transistor. In order to more clearly and specifically describe the thin film transistor in this embodiment, a top-gate thin film transistor is described as an example.

In some embodiments, the top-gate thin film transistor further includes an insulating layer3disposed on a side of the active layer2proximal to the base substrate1; a plurality of first grooves31are formed in the insulating layer3on one side proximal to the active layer2and at positions corresponding to the portion of at least one of the source contact region22and the drain contact region23close to the channel region21of the thin film transistor, the plurality of first grooves31define the wave structure of the active layer2, and the plurality of first grooves31are in one-to-one correspondence with the plurality of second sub-grooves24and orthographic projections of the plurality of first grooves31and the plurality of second sub-grooves24are overlapped on the base substrate.

That is, as shown inFIG.1, the insulating layer3is in contact with the active layer2, and the first grooves in the upper surface (the side distal to the base substrate1) of the insulating layer3define the wave structure of the active layer2. Specifically, when the thin film transistor is manufactured, the insulating layer3may be first formed on the base substrate1, and the first grooves31are formed in the insulating layer3distal to the base substrate1and at positions corresponding to the source contact region22and the drain contact region23close to the channel region21. Then, the active layer2is formed on the base substrate1with the insulating layer3, and the wave structure of the active layer2is naturally formed at positions corresponding to the first grooves31(i.e., at positions where the source contact region22and the drain contact region23close to the channel region21) with a height difference between different parts of a surface of the insulating layer3, and the plurality of first grooves31are in one-to-one correspondence with the plurality of second sub-grooves24and orthographic projections of the plurality of first grooves31and the plurality of second sub-grooves24are overlapped on the base substrate.

It should be noted that, the plurality of second sub-grooves24and the plurality of first sub-grooves25are defined by a corrugated structure of an upper surface of the insulating layer3formed by an etching process. A thickness of the insulating layer3may include 2000 Å to 6000 Å, and in some embodiments, an etched depth at the upper surface of the insulating layer3may be 1000 Å. At this time, a depth of each of the plurality of second sub-grooves24and the plurality of first sub-grooves25may be 1000 Å. A material of the insulating layer may be silicon oxide, silicon nitride or a composite material of the silicon oxide and the silicon nitride.

In some embodiments, the top-gate thin film transistor may further include a light-shielding layer4, which is disposed between the base substrate1and the insulating layer3, and the insulating layer3is disposed between the light-shielding layer4and the active layer2. As shown inFIG.1, the light-shielding layer4is disposed on a side of the active layer2proximal to the base substrate1for blocking external light, which may prevent the active layer2from being influenced by the external light and further damage the performance of the thin film transistor. A material of the light-shielding layer4may include metal, and a metal with good light reflectivity is required, which is conventionally Al, Mo, or Cu. In order to avoid conductive properties of the light-shielding layer4from conducting the source contact region22and the drain contact region23of the active layer2, the light-shielding layer4should be separated from the active layer2by the insulating layer3.

In some embodiments, the light-shielding layer4is provided with a plurality of second grooves41at positions corresponding to the portion of at least one of the source contact region22and the drain contact region23close to the channel region21, the plurality of second grooves41define the plurality of first grooves31and further define the wave structure, and the plurality of second grooves41are in one-to-one correspondence with the plurality of second sub-grooves24and orthographic projections of the plurality of second grooves and the plurality of second sub-grooves are overlapped on the base substrate. That is, in the procedure for manufacturing the thin film transistor, when the light-shielding layer4is formed on the base substrate1, a plurality of second grooves41are formed on the upper surface (a surface distal to the base substrate1) of the light-shielding layer4at positions corresponding to the source contact region22and the drain contact region23close to the channel region21, and then the insulating layer3is formed, and the first grooves31is naturally formed on the insulating layer3at positions corresponding to the second grooves41, so that the wave structure is formed subsequently at the positions of the source contact region22and the drain contact region23of the active layer2close to the channel region21. The plurality of second grooves41are in one-to-one correspondence with the plurality of second sub-grooves24and orthographic projections of the plurality of the plurality of second grooves41and the second sub-grooves24are overlapped on the base substrate. By forming the light-shielding layer4with the second grooves41formed by an etching process, additional process steps are not required, so that the manufacturing procedure for the thin film transistor can be simplified and the production cost can be reduced.

It should be noted that, since a corrugated structure is formed on the upper surface of the light-shielding layer4with an etching process, after the insulating layer3is disposed on the light-shielding layer4, a same corrugated structure also exists on the upper surface of the insulating layer3, to define the plurality of second sub-grooves24and the plurality of first sub-grooves25. The thickness of the light-shielding layer4may include 500 Å to 1000 Å, and when the thickness of the light-shielding layer4is 1000 Å, an etched depth on the upper surface of the light-shielding layer4may be less than or equal to 1000 Å.

In some embodiments, the second grooves41may penetrate through the light-shielding layer4(not shown in the drawings), and at this time, the etched depth on the upper surface of the light-shielding layer4is equal to the thickness of the light-shielding layer4. It should be understood that, the second grooves41are disposed at positions corresponding to the portion of at least one of the source contact region22and the drain contact region23of the active layer2close to the channel region21. Therefore, even if the second grooves41penetrate through the light-shielding layer4, the light-shielding effect on the channel region21of the active layer2is not substantially affected, and the performance of the thin film transistor is not greatly affected.

It should be noted that, when the light-shielding layer4is formed, the plurality of second grooves41may not be formed on the upper surface (i.e., the surface distal to the base substrate1) of the light-shielding layer4by an etching process. That is, the upper surface of the light-shielding layer4is flat. The wave structure may then be defined by etching a plurality of first grooves31on the upper surface of the insulating layer3disposed on the light-shielding layer4, and the plurality of first grooves31are in one-to-one correspondence with the plurality of second sub-grooves24and orthographic projections of the plurality of first grooves31and the plurality of second sub-grooves24are overlapped on the base substrate.

The present disclosure also provides a method for manufacturing a thin film transistor, as shown inFIGS.2to5, and the method for manufacturing a thin film transistor provided in this embodiment may be used to manufacture the thin film transistor provided in the above embodiment.

The method for manufacturing the thin film transistor of the present embodiment is described below by taking the manufacturing of the top-gate thin film transistor as an example.

The manufacturing method provided by the embodiment may comprise the following two examples.

The first manufacturing method provided in this embodiment is as shown inFIGS.2to4, and includes the following steps S11to S13.

At step S11, a base substrate1is formed, a light-shielding layer4is formed on the base substrate1by a patterning process, and a plurality of second grooves41are formed on an upper surface of the light-shielding layer4at positions corresponding to a part of at least one of the source contact region22and the drain contact region23close to the channel region21.

A material of the light-shielding layer4may include an opaque material such as metal, for example, Al, Mo, or Cu.

Specifically, in this step, as shown inFIG.2, a photoresist layer is coated on the light-shielding layer4, and then a pattern of the light-shielding layer4having a plurality of second grooves41is formed on the base substrate1by exposure, development, and etching processes.

At step S12, an insulating layer3is formed on the base substrate1with the light-shielding layer4formed thereon, and a plurality of first grooves31are formed on an upper surface of the insulating layer3at positions corresponding to the portion of the at least one of the source contact region22and the drain contact region23of the active layer4close to the channel region21.

As shown inFIG.3, an entire material layer of the insulating layer3is formed directly on the base substrate1with the light-shielding layer4formed thereon, and with the second grooves41in the light-shielding layer4, the insulating layer3will naturally have concaves at positions corresponding to the second grooves41. That is, the first grooves31are formed at positions corresponding to the portion of the at least one of the source contact region22and the drain contact region23close to the channel region21.

At step S13, an active layer2is formed on the base substrate1with the insulating layer3formed thereon.

It should be noted that, the wave structure refers to a plurality of first sub-grooves25disposed on a side of the active layer2proximal to the base substrate1and a plurality of second sub-grooves24disposed on a side of the active layer distal to the base substrate1, and the plurality of first sub-grooves25and the plurality of second sub-grooves24are disposed alternately along a direction parallel to an extension of the channel region21. It should be noted that, the plurality of first sub-grooves24and the plurality of second sub-grooves25have a same depth.

Specifically, as shown inFIG.4, in this step, a material layer of the active layer2is directly formed on the base substrate1on which the insulating layer3is formed. Since the insulating layer3has the plurality of first grooves31, when the material layer of the active layer2is formed, the active layer2will naturally have concaves at positions of the portion of the at least one of the source contact region22and the drain contact region23close to the channel region21to form the wave structure, and the plurality of first grooves41are in one-to-one correspondence with the plurality of second sub-grooves24, and orthographic projections of the plurality of first grooves41and plurality of second sub-grooves24are overlapped with each other on the base substrate.

Since a corrugated structure is formed by etching the upper surface of the light-shielding layer4, after the insulating layer3is formed on the light-shielding layer4, the same corrugated structure also exists on the upper surface of the insulating layer3, and then the plurality of second sub-grooves24and the plurality of first sub-grooves25are formed. The thickness of the light-shielding layer4may include 500 Å to 1000 Å, and when the thickness of the light-shielding layer4is 1000 Å, an etched depth of the upper surface of the light-shielding layer4may be less than or equal to 1000 Å.

It is to be understood that, in this step, after a material of the active layer2is formed on the base substrate1with the insulating layer3formed thereon, a step of performing a conductive treatment on the source contact region22and the drain contact region23of the active layer2is further included. The method for the conductive treatment may be an ion implantation method including an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method, or a solid diffusion implantation method. The method for the conductive treatment may also be performed by ion bombardment, which hydrogenates or de-oxidizes an oxide semiconductor material in a region to be subjected to the conductive treatment.

In some embodiments, as shown inFIG.5, the method of the present embodiment may further include a step of forming a gate insulating layer5, a gate6, a source7, and a drain8of the thin film transistor on the base substrate1, which is not described herein again.

The second manufacturing method provided in this embodiment, referring toFIGS.6to8, includes the following steps S21to S23.

The second manufacturing method is similar to the first manufacturing method except that the plurality of first grooves31are formed directly on the upper surface of the insulating layer3without forming the plurality of second grooves41on the light-shielding layer4in the second manufacturing method. Specifically, the method comprises the following steps.

At step S21, a base substrate1is formed, and a light-shielding layer4is formed on the base substrate1.

As shown inFIG.6, a light-shielding layer4is first formed on the base substrate1, and the light-shielding layer4is configured to shield external light to prevent the active layer2from being affected by the external light and damaging the performance of the thin film transistor. The material of the light-shielding layer4may include metal, and the metal with good light reflectivity is required, which is conventionally Al, Mo, or Cu.

It should be noted that, the upper surface of the light-shielding layer4is a flat surface, and therefore it is not necessary to form the plurality of second grooves41while forming the pattern of the light-shielding layer4by the patterning process.

At step S22, an insulating layer3is formed on the base substrate1on which the light-shielding layer4is formed, and forming a plurality of first grooves31on an upper surface of the insulating layer3at positions corresponding to at least one of the source contact region22and the drain contact region23of the active layer2close to the channel region21by a patterning process.

It should be noted that, when the material of the insulating layer3was coated, a common light-shielding agent may be injected into the insulating layer3to make the insulating layer3opaque, to play a role of shielding light and avoid the influence of light on the active layer2. At this time, since the insulating layer3can simultaneously realize the insulating function and the light-shielding function, the light-shielding layer4may not be additionally provided (not shown in the drawings).

At step S23, an active layer2is formed on the base substrate1on which the insulating layer3is formed.

It should be noted that, the wave structure refers to a plurality of first sub-grooves25disposed on a side of the active layer2proximal to the base substrate and a plurality of second sub-grooves24disposed on a side of the active layer distal to the base substrate, and the plurality of first sub-grooves25and the plurality of second sub-grooves24are disposed alternately along a direction parallel to an extension of the channel region21. It should be noted that the plurality of first sub-grooves24and the plurality of second sub-grooves25have the same depth.

Specifically, in this step, as shown inFIG.7, the material layer of the active layer2may be directly formed on the base substrate1on which the insulating layer3is formed. Since the insulating layer3has the plurality of first grooves31, when the material layer of the active layer2is formed, the material layer of the active layer2certainly have concaves at positions of the portion of the source contact region22and the drain contact region23close to the channel region21to form the wave structure, and the plurality of first grooves31are in one-to-one correspondence with the plurality of second sub-grooves24and orthographic projections of the plurality of first grooves31and the plurality of second sub-grooves24are overlapped with each other on the base substrate.

The plurality of second sub-grooves24and the plurality of first sub-grooves25are formed by the corrugated structure of the upper surface of the insulating layer3formed by an etching process. The thickness of the insulating layer3may include 2000 Å to 6000 Å, and in some embodiments, the etched depth on the upper surface of the insulating layer3may be 1000 Å. At this time, the depth of the plurality of second sub-grooves24and the plurality of first sub-grooves25is 1000 Å.

It will be appreciated that in this step, after the material layer of the active layer2material is formed on the base substrate1on which the insulating layer3is formed, a step of performing a conductive treatment on the source contact region22and the drain contact region23is also included. The method for the conductive treatment may be an ion implantation method including an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method, or a solid diffusion implantation method. The method for the conductive treatment may also be performed by ion bombardment, which hydrogenates or de-oxidizes an oxide semiconductor material in a region to be subjected to the conductive treatment.

In some embodiments, as shown inFIG.8, the method of this embodiment may further include a step of forming a gate insulating layer5, a gate6, a source7, and a drain8of the thin film transistor on the base substrate1, which is not described herein again.

In this embodiment, since the portion of the source contact region22and the drain contact region23close to the channel region21has the wave structure, compared with the thin film transistor in the prior art, the thin film transistor in this embodiment has a longer transmission path of the conductive diffusion effect and a smaller influence of the conductive diffusion effect on the channel region21, so that good performance and uniformity of the manufactured thin film transistor can be ensured. Meanwhile, in the wave structure of the portion of the active layer2, the atoms of the material of the active layer2are arranged distorted and disordered, so that the conductive diffusion effect on the channel region21can be well blocked, and good performance and uniformity of the thin film transistor can be ensured.

In some embodiments, a plurality of second sub-grooves24may alternatively be formed at positions of the part of at least one of the source contact region22and the drain contact region23directly when the active layer2is formed by a patterning process (not shown).

Embodiments of the present disclosure also provide a display substrate, including: a base substrate1and a thin film transistor disposed on the base substrate1. The thin film transistor in this embodiment may be any one of the thin film transistors provided in the above embodiments.

Since the display substrate in this embodiment includes the thin film transistor in the above embodiment, the thin film transistor in this embodiment has a low degree of conductivity in the channel region21of the active layer2, and has good performance and good display effect.

The embodiment of the present disclosure further provides a display apparatus, which includes the display substrate provided by the above embodiment.

Specifically, the display apparatus in this embodiment may be: a display apparatus including any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Since the display apparatus of the embodiment includes the display substrate provided in the above embodiment, the display apparatus of the embodiment has a better display effect than the display apparatus in the prior art.

It will be understood that, the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to a person skilled in the art that, various changes and modifications can be made without departing from the spirit and scope of the disclosure, and these changes and modifications are to be considered within the scope of the disclosure.