Semiconductor device, method of manufacturing the same, and massive data storage system including the same

A semiconductor device includes a gate electrode structure, a channel, first division patterns, and a second division pattern. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each gate electrode extends in a second direction parallel to the substrate. The channel extends in the first direction through the gate electrode structure. The first division patterns are spaced apart from each other in the second direction, and each first division pattern extends in the second direction through the gate electrode structure. The second division pattern is between the first division patterns, and the second division pattern and the first division patterns together divide a first gate electrode in a third direction parallel to the substrate and crossing the second direction. The second division pattern has an outer contour that is a curve in a plan view.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2020-0144930, filed on Nov. 3, 2020 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

Inventive concepts relate to a semiconductor device, a method of manufacturing the same, and a massive data storage system including the same.

In an electronic system requiring data storage needs a high capacity semiconductor device that may store high capacity data. Thus, a method of increasing the data storage capacity of the semiconductor device has been studied. For example, a semiconductor device including memory cells that may be 3-dimensionally stacked has been suggested.

As the number of stacks of the memory cells in the semiconductor device increases, the memory cells may be bent according to the shapes of underlying structures, and the electrical and/or mechanical characteristics of the memory cells may be deteriorated.

SUMMARY

Some example embodiments provide a semiconductor device having improved characteristics.

Alternatively or additionally some example embodiments provide a method of manufacturing/fabricating a semiconductor device having improved characteristics.

Alternatively or additionally some example embodiments provide a massive data storage system including a semiconductor device having improved characteristics.

According to some example embodiments of inventive concepts, there is provided a semiconductor device. The semiconductor device may include a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate, a channel on the substrate and extending rough the gate electrode structure in the first direction, first division patterns apart from each other in the second direction, each of the first division patterns extending in the second direction through the gate electrode structure, and a second division pattern between the first division patterns, the second division pattern and the first division patterns together dividing a first gate electrode among the gate electrodes in a third direction parallel to the upper surface of the substrate and crossing the second direction. The second division pattern has an outer contour that has a curve in a plan view.

According to some example embodiments of inventive concepts, there is provided a semiconductor device. The semiconductor device may include a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate, a channel on the substrate and extending in the first direction through the gate electrode structure, first division patterns spaced apart from each other in the second direction, each of the first division patterns extending in the second direction through the gate electrode structure, and a second division pattern between the first division patterns, the second division pattern and the first division patterns together dividing a first gate electrode among the gate electrodes in a third direction parallel to the upper surface of the substrate and crossing the second direction. The second division pattern includes a horizontal portion at a same level as the first gate electrode, the horizontal portion and the first division patterns together dividing the first gate electrode in the third direction, and a vertical portion connected to the horizontal portion, the vertical portion extending in the first direction from the horizontal portion.

According to some example of inventive concepts, there is provided a semiconductor device. The semiconductor device may include lower circuit patterns on a substrate, the lower circuit patterns including a cell array region and an extension region at least partially surrounding the cell array region, a common source plate (CSP) over the lower circuit patterns, a gate electrode structure on the CSP, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate, a memory channel structure extending through the gate electrode structure on the cell array region of the substrate to contact an upper surface of the CSP, the memory channel structure including a channel extending in the first direction, and a charge storage structure on an outer sidewall of the channel, a first division pattern at each of opposite sides of the gate electrode structure in a third direction parallel to the upper surface of the substrate and crossing the second direction, the division pattern extending in the second direction, second division patterns spaced apart from each other in the second direction, each of the second division patterns extending in the second direction through the gate electrode structure between the first division patterns, a third division pattern between the second division patterns, the second and third division patterns dividing a first gate electrode in the third direction, the first gate electrode among the gate electrodes, an insulation pattern structure extending through a portion of the gate electrode structure on the CSP, a through via extending in the first direction through the insulation pattern structure and the CSP, the through via contacting one of the lower circuit patterns to be electrically connected to the one of the lower circuit patterns, a contact plug extending in the first direction to contact an upper surface of an end portion in the second direction of each of the gate electrodes, and a support structure extending in the first direction through the gate electrode structure to contact an upper surface of the CSP, the support structure being adjacent to the contact plug. The third division pattern has an outer contour that has a curve in a plan view.

According to some example embodiments of inventive concepts, there is provided a method of manufacturing a semiconductor device including alternately and repeatedly stacking a first insulation layer and a sacrificial layer on a substrate in a first direction perpendicular to an upper surface of the substrate, forming a second insulation layer on an uppermost one of the sacrificial layers, forming a hole through the second insulation layer, the hole exposing the uppermost one of the sacrificial layers, partially removing the exposed uppermost one of the sacrificial layers through the hole to form a first gap exposing an uppermost one of the first insulation layers, forming a division layer on the first and second insulation layers to fill the first gap and the hole, alternately and repeatedly stacking an additional first insulation layer and an additional sacrificial layer on the division layer in the first direction to form a mold layer on the substrate, the mold layer including the first and second insulation layers, the sacrificial layers, and the division layer, forming a first opening through the mold layer to extend in a second direction parallel to the upper surface of the substrate, the first opening extending through at least a portion of the division layer in the first gap, removing the sacrificial layers through the first opening to form second gaps, and forming gate electrodes in the second gaps, respectively.

According to some example embodiments of inventive concepts, there is provided a method of manufacturing a semiconductor device including alternately and repeatedly stacking a first insulation layer and a sacrificial layer on a substrate in a first direction perpendicular to an upper surface of the substrate, partially removing an uppermost one of the sacrificial layers by performing an isotropic etching process thereon to form a first gap exposing an uppermost one of the first insulation layers, forming a division layer on the uppermost one of the first insulation layers and the uppermost one of the sacrificial layers to fill the first gap, alternately and repeatedly stacking an additional first insulation layer and an additional sacrificial layer on the division layer in the first direction to form a mold layer on the substrate, the mold layer including the first insulation layers, the sacrificial layers, and the division layer, forming a first opening through the mold layer to extend in a second direction parallel to the upper surface of the substrate, the first opening extending through at least a portion of the division layer in the first gap, removing the sacrificial layers through the first opening to form second gaps, and forming gate electrodes in the second gaps, respectively.

According to some example embodiments of inventive concepts, there is provided a massive data storage system. The massive data storage system may include (I) a semiconductor device comprising (A) a memory cell structure including (1) a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate, (2) a channel extending in the first direction through the gate electrode structure on the substrate, (3) first division patterns spaced apart from each other in the second direction, each of the first division patterns extending in the second direction through the gate electrode structure, and (4) a second division pattern between the first division patterns, the second division pattern and the first division patterns together dividing a first gate electrode among the gate electrodes in a third direction parallel to the upper surface of the substrate and crossing the second direction with the second division pattern has an outer contour that has a curve in a plan view; (B) peripheral circuit wirings configured to apply electrical signals to the memory cell structure, and (C) an input/output pad electrically connected to the peripheral circuit wirings. The system further comprises (II) a controller circuitry electrically connected to the semiconductor device through the input/output pad, the controller circuitry configured to control the semiconductor device.

In the method of manufacturing the semiconductor device in accordance with some example embodiments, the sacrificial layer for forming the GSL may be partially removed to form a gap, and the division layer may be formed on the sacrificial layer to fill the gap. The division layer may have a flat upper surface, so that additional sacrificial layers and insulation layers may be alternately and repeatedly stacked to be parallel to the upper surface of the substrate. Thus, portions of the sacrificial layers that are bent and/or crooked might not be excessively removed to increase the process margin, and the gate electrodes substituted for the sacrificial layers may have enhanced electrical characteristics.

DETAILED DESCRIPTION OF SOME EXAMPLE EMBODIMENTS

The above and other aspects and features of the semiconductor devices, the methods of manufacturing the same, and the electronic system, e.g., massive data storage system including the same in accordance with some example embodiments will become readily understood from detail descriptions that follow, with reference to the accompanying drawings. It will be understood that, although the terms “first,” “second,” and/or “third” may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another region, layer or section. Thus, a first element, component, region, layer and/or section discussed below could be termed a second or third element, component, region, layer and/or section without departing from the teachings of inventive concepts.

FIG.1is a schematic diagram illustrating an electronic system including a semiconductor device in accordance with some example embodiments.

Referring toFIG.1, an electronic system1000may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The electronic system1000may be a storage device including one or a plurality of semiconductor devices1100or an electronic device including a storage device. For example, the electronic system1000may be or may include at least one of a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device that may include one or a plurality of semiconductor devices1100.

The semiconductor device1100may be or may include a non-volatile memory device, for example, a NAND flash memory device that will be illustrated with reference toFIGS.43to54. The semiconductor device1100may include a first structure1100F and a second structure1100S on the first structure1100F. In the drawings, the first structure1100F is under the second structure1100S, however, inventive concepts may not be limited thereto, and the first structure1100F may be beside, e.g. adjacent to or partially adjacent to or sharing a portion of a common border, or may be on the second structure1100S. The first structure1100F may be or may include a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second structure1100S may be or may include a memory cell structure including a bit line BL, a common source line CSL, word lines WL, first and second upper gate lines UL1and UL2, first and second lower gate lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of the lower transistors LT1and LT2and the number of the upper transistors UT1and UT2may be varied in accordance with some example embodiments. The lower transistors LT1and LT2and/or the upper transistors UT1and UT2may be MOSFET transistors such as NMOS transistors and/or PMOS transistors, and may include planar transistors and/or three-dimensional transistors; however, example embodiments are not limited thereto.

In some example embodiments, the upper transistors UT1and UT2may include string selection transistors, and the lower transistors LT1and LT2may include ground selection transistors. The lower gate lines LL1and LL2may be or correspond to gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be or correspond to gate electrodes of the memory cell transistors MCT, respectively, and the upper gate lines UL1and UL2may be or correspond to gate electrodes of the upper transistors UT1and UT2, respectively.

In some example embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground selection transistor LT2that may be connected with each other in serial, e.g. may have their source/drain regions connected to or directly connected to each other. The upper transistors UT1and UT2may include a string selection transistor UT1and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1and the upper erase control transistor UT2may be used in an erase operation for erasing data stored in the memory cell transistors MCT through a gate induced drain leakage (GIDL) phenomenon.

The common source line CSL, the first and second lower gate lines LL1and LL2, the word lines WL, and the first and second upper gate lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection wirings1115extending to the second structure1110S in the first structure1100F. The bit lines BL may be electrically connected to the page buffer1120through second connection wirings1125extending to the second structure1100S in the first structure1100F.

In the first structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation for at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through an input/output pad1101that is electrically connected to the logic circuit1130. The input/output pad1101may be electrically connected to the logic circuit1130through an input/output connection wiring1135extending to the second structure1100S in the first structure1100F.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. The electronic system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control operations of the electronic system1000including the controller1200. The processor1210may be operated by firmware; however, example embodiments are not limited thereto. The processor1210and may control the NAND controller1220to access the semiconductor device1100. The NAND controller1220may include a NAND interface1221for communicating with the semiconductor device1100. Through the NAND interface1221, communication such as at least one of control commands for controlling the semiconductor device1100, data to be written in the memory cell transistors MCT of the semiconductor device1100, data to be read from the memory cell transistors MCT of the semiconductor device1100, etc., may be transferred. The host interface1230may provide communication between the electronic system1000and an outside host. When a control command is received from the outside host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

FIG.2is a schematic perspective view illustrating an electronic system including a semiconductor device in accordance with some example embodiments.

Referring toFIG.2, an electronic system2000may include a main substrate2001, a controller2002mounted on the main substrate2001, at least one semiconductor package2003, and a buffer such as a dynamic random access memory (DRAM) device2004. The semiconductor package2003and the DRAM device2004may be connected to the controller2002by wiring patterns2005on the main substrate2001.

The main substrate2001may include a connector2006having a plurality of pins connected to an outside host. The number and/or the layout of the plurality pins in the connector2006may be changed depending on a communication interface between the electronic system2000and the outside host. In some example embodiments, the electronic system2000may communicate with the outside host according to at least one of a USB, peripheral component interconnect express (PCI-Express), serial advanced technology attachment (SATA), M-Phy for universal flash storage (UFS), etc. In some example embodiments, the electronic system2000may be operated by power source provided from the outside host through the connector2006. The electronic system2000may further include power management integrated circuit (PMIC) for distributing the power source provided from the outside host to the controller2002and the semiconductor package2003.

The controller2002may write data in the semiconductor package2003and/or read data from the semiconductor package2003, and may enhance the operation speed of the electronic system2000.

The DRAM device2004may be or correspond to or include a buffer memory for reducing the speed difference between the semiconductor package2003for storing data and the outside host. The DRAM device2004included in the electronic system2000may serve as a cache memory, and/or may provide a space for temporarily storing data during the control operation for the semiconductor package2003. If the electronic system2000includes the DRAM device2004, the controller2002may further include a DRAM controller for controlling the DRAM device2004in addition to the NAND controller for controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bspaced apart from each other. The first and second semiconductor packages2003aand2003bmay be semiconductor packages each of which may include a plurality of semiconductor chips2200, e.g. may include the same or different number of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, the semiconductor chips2200, bonding layers2300disposed under the semiconductor chips2200, a connection structure2400for electrically connecting the semiconductor chips2200and the package substrate2100, and a mold layer2500covering the semiconductor chips2200and the connection structure2400on the package substrate2100.

The package substrate2100may be or include a printed circuit board (PCB) including package upper pads2130. Each semiconductor chip2200may include an input/output pad2210. The input/output pad2210may correspond to the input/output pad1101ofFIG.1. Each semiconductor chip2200may include gate electrode structures3210, memory channel structures3220extending through the gate electrode structures3210, and division structures3230for dividing the gate electrode structures3210. Each semiconductor chip2200may include a semiconductor device that will be illustrated with reference toFIGS.43to54.

In some example embodiments, the connection structure2400may be or include a bonding wire for electrically connecting the input/output pad2210and the package upper pads2130. Thus, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected with each other by a bonding wire method, and may be electrically connected to the package upper pads2130of the package substrate2100. Alternatively or additionally, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected with each other by a connection structure including a through silicon via (TSV), instead of or in addition to the connection structure2400of the bonding wire method.

In some example embodiments, the controller2002and the semiconductor chips2200may be included in one package. In some example embodiments, the controller2002and the semiconductor chips2200may be mounted on an interposer substrate different from the main substrate2001, and the controller2002and the semiconductor chips2200may be connected with each other by a wiring on the interposer substrate.

FIGS.3and4are schematic cross-sectional views illustrating semiconductor packages each of which may include a semiconductor device in accordance with some example embodiments.FIGS.3and4illustrate some example embodiments of the semiconductor package2003shown inFIG.2, and show a cross-section taken along a line I-I′ of the semiconductor package2003inFIG.2.

Referring toFIG.3, in the semiconductor package2003, the package substrate2100may be or may include a PCB. The package substrate2100may include a substrate body part2120, upper pads2130(as indicated inFIG.2) on an upper surface of the substrate body part2120, lower pads2125on a lower surface of the substrate body part2120or exposed through the lower surface of the substrate body part2120, and inner wirings2135for electrically connecting the upper pads2130and the lower pads2125in an inside of the substrate body part2120. The upper pads2130may be electrically connected to the connection structures2400. The lower pads2125may be connected to wiring patterns2005of the main substrate2010in the electronic system2000through conductive connection parts2800, as shown inFIG.2.

Each semiconductor chip2200may include a semiconductor substrate3010, and a first structure3100and a second structure3200sequentially stacked on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region in which peripheral circuit wirings3110may be formed. The second structure3200may include a common source line3205, a gate electrode structure3210on the common source line3205, memory channel structures3220and division structures3230(refer toFIG.2) extending through the gate electrode structure3210, bit lines3240electrically connected to the memory channel structures3220, and gate connection wirings3235electrically connected to the word lines WL of the gate electrode structure3210(refer toFIG.1).

The second structure3200may further include a first division pattern335as illustrated in more detail below with reference toFIGS.43and44.

Each semiconductor chip2200may include a through wiring3245being electrically connected to the peripheral circuit wirings3110of the first structure3100and extending in the second structure3200. The through wiring3245may be disposed at an outside of the gate electrode structure3210, and at least some through wirings3245may extend through the gate electrode structure3210. Each semiconductor chip2200may further include the input/output pad2210(refer toFIG.2) electrically connected to the peripheral circuit wirings3110of the first structure3100.

Referring toFIG.4, in a semiconductor package2003A, each semiconductor chip2200amay include a semiconductor substrate4010, a first structure4100on the semiconductor substrate4010, and a second structure4200on and bonded with the first structure4100by a wafer bonding method.

The first structure4100may include a peripheral circuit region in which a peripheral circuit wiring4110and first bonding structures4150are formed. The second structure4200may include a common source line4205, a gate electrode structure4210between the common source line4205and the first structure4100, memory channel structures4220and the division structure3230(refer toFIG.2) extending through the gate electrode structure4210, and second bonding structures4250electrically connected to the memory channel structures4220and the word lines WL (refer toFIG.1) of the gate electrode structure4210. For example, the second bonding structures4250may be electrically connected to the memory channel structures4220and the word lines WL (refer toFIG.1) through the bit lines4240electrically connected to the memory channel structures4220and the gate connection wirings4235electrically connected to the word lines WL (refer toFIG.1), respectively. The first bonding structures4150of the first structure4100and the second bonding structures4250of the second structure4200may contact each other to be bonded with each other. The first bonding structures4150and the second bonding structures4250may include a conductive material such as a metal, such as at least one of copper, aluminum, tungsten, or gold, and/or an alloy thereof.

The second structure4200may further include the first to third support structures432,434and436as shown inFIGS.11to13,FIGS.43and44described below in more detail.

Each semiconductor chip2200amay further include the input/output pad2210(refer toFIG.2) electrically connected to the peripheral circuit wirings4110of the first structure4100.

The semiconductor chips2200ofFIG.3and the semiconductor chips2200aofFIG.4may be electrically connected with each other by the connection structures2400in a bonding wire method. However, in some example embodiments, semiconductor chips such as the semiconductor chips2200ofFIG.3and the semiconductor chips2200aofFIG.4in the same semiconductor package may additionally or alternatively be electrically connected with each other by a connection structure including a TSV.

FIGS.5to49are plan views and cross-sectional views illustrating a method of manufacturing/fabricating a vertical memory device in accordance with some example embodiments. Particularly,FIGS.5-6,9,11-12,17,21,30,37,40and43-44are the plan views, and theFIGS.7-8,10,13-16,18-20,22-29,31-36,41-42and45-49are the cross-sectional views.

FIGS.7-8,16,18-19,41-42,45and46are cross-sectional views taken along lines A-A′, respectively, of corresponding plan views,FIGS.10,13-15,22,28and47are cross-sectional views taken along lines B-B′, respectively, of corresponding plan views,FIG.20is a cross-sectional view taken along line C-C′ of a corresponding plan view, andFIGS.23,25-27,31-33,35,38and48are cross-sectional views taken along lines D-D′ of corresponding plan views, respectively, andFIGS.24,29,34,36,39and49are cross-sectional views taken along lines E-E′ of corresponding plan views, respectively.FIGS.6to49are drawings of region X inFIG.5,FIGS.12and44are enlarged cross-sectional views of region Y inFIGS.11and43, respectively, andFIG.19is an enlarged cross-sectional view of region Z inFIG.18, andFIG.42is an enlarged cross-sectional view of region W inFIG.41.

Hereinafter, although not necessarily in the claims, a direction substantially perpendicular to an upper surface of a first substrate may be defined as a first direction D1, and two directions substantially parallel to the upper surface of the first substrate and crossing each other may be defined as second and third directions D2and D3, respectively. In some example embodiments, the second and third directions D2and D3may be perpendicular or substantially perpendicular to each other.

Referring toFIG.5, a substrate100may include a first region I and a second region II surrounding the first region I.

The substrate100may include at least one of silicon, germanium, silicon-germanium or a III-V compound such as GaP, GaAs, GaSb, etc., and may be in single-crystal or polycrystalline phase. In some example embodiments, the substrate100may be or include a silicon-on-insulator (SOI) substrate and/or a germanium-on-insulator (GOI) substrate. In some example embodiments, the substrate100may be doped, e.g. lightly doped, with p-type impurities, e.g., boron or n-type impurities, e.g., phosphorus and/or arsenic.

In some example embodiments, the first region I may be or correspond to a cell array region, the second region II be a pad region or extension region, and the first and second cell regions I and II together may form a cell region. For example, memory cells each of which may include a gate electrode, a channel, and a charge storage structure may be formed on the first region I of the substrate100, and upper contact plugs for transferring electrical signals to the memory cells and pads of the gate electrodes contacting the upper contact plugs may be formed on the second region II of the substrate100. In the drawings, the second region II entirely surrounds the first region I, however, inventive concepts may not be limited thereto. For example, the second region II may be formed only on each of opposite sides in the second direction D2of the first region I. Additionally in the drawings, the first region I is in a center of the second region II; however, example embodiments are not limited thereto. Additionally in the drawings, each of the first region I and the second region II are illustrated as square-shaped; however, example embodiments are not limited thereto.

The substrate100may further include a third region surrounding the second region II, and upper circuit patterns for applying electrical signals to the memory cells through the upper contact plugs may be formed on the third region of the substrate100.

Hereinafter, only structures bounded by X partially including the first and second regions I and II of the substrate100will be illustrated.

Referring toFIGS.6and7, lower circuit patterns may be formed on the substrate100, and first and second insulating interlayers150and170may be formed on the substrate100to cover the lower circuit patterns.

The substrate100may include a field region on which an isolation pattern110is formed and an active region101on which no isolation pattern is formed. The isolation pattern110may be formed by a shallow trench isolation (STI) process and/or a high-density plasma (HDP) deposition process and/or a spin-on glass (SOG) process, and may include an oxide, e.g., silicon oxide.

In some example embodiments, the semiconductor device may have a cell over periphery (COP) structure. For example, the lower circuit patterns may be formed on the substrate100, and memory cells, upper contact plugs, and upper circuit patterns may be formed over the lower circuit patterns.

Referring toFIG.23together withFIGS.6and7, for example, first and second transistors may be formed on the second and first regions II and I, respectively, of the substrate100. The first transistor may include a first lower gate structure142on the substrate100and first and second regions102and103serving as/corresponding to source/drain regions at upper portions of the active region101adjacent to the first lower gate structure142, and the second transistor may include a second lower gate structure146on the substrate100and third and fourth regions106and107serving as/corresponding to source/drain regions at upper portions of the active region101adjacent to the second lower gate structure146. Either or both of the first transistors and the second transistors may be NMOS transistors, or either of both of the first transistors and the second transistors may be PMOS transistors, or one of the first transistor or the second transistor may be an NMOS transistor and the other of the first transistor or the second transistor may be a PMOS transistor; however, example embodiments are not limited thereto.

The first lower gate structure142may include a first lower gate insulation pattern122and a first lower gate electrode132sequentially stacked on the substrate100, and the second lower gate structure146may include a second lower gate insulation pattern126and a second lower gate electrode136sequentially stacked on the substrate100. The first lower gate insulation pattern122and/or the second lower gate insulation pattern may be or include silicon oxide; however, example embodiments are not limited thereto. Either or both of the first lower gate electrode132or the second lower gate electrode136may include a conductive material such as at least one of doped polysilicon or a metal such as tungsten; however, example embodiments are not limited thereto.

A first insulating interlayer150may be formed on the substrate100to cover the first and second transistors, and first, second, fourth and fifth lower contact plugs162,163,168and169extending through the first insulating interlayer150to contact the first to fourth impurity regions102,103,106and107, respectively, and a third lower contact plug164extending through the first insulating interlayer150to contact the first lower gate electrode132may be formed. The first insulating interlayer150may be or may include oxide; however, example embodiments are not limited thereto. First through fifth lower contact plugs162,163,168, and169may include doped polysilicon and/or tungsten; however, example embodiments are not limited thereto.

First to fifth lower wirings182,183,184,188and189may include a metal such as aluminum and/or copper and be formed on the first insulating interlayer150to contact upper surfaces of the first to fifth lower contact plugs162,163,164,168and169, respectively. A first lower via192, a sixth lower wiring202, a third lower via212and an eighth lower wiring222may include a metal such as aluminum and/or copper and may be sequentially stacked on the first lower wiring182, and a second lower via196, a seventh lower wiring206, a fourth lower via216and a ninth lower wiring226may include a metal such as aluminum and/or copper and may be sequentially stacked on the fourth lower wiring188.

The second insulating interlayer170may be formed on the first insulating interlayer150to cover the first to ninth lower wirings182,183,184,188,189,202,206,222and226and the first to fourth lower vias192,194,212and216.

Each element included in the lower circuit patterns may be formed by, e.g., a patterning process and/or a damascene process.

Referring toFIG.8, a common source plate (CSP)240, a first sacrificial layer structure290and a first support layer300may be sequentially formed on the second insulating interlayer170.

The CSP240may include or consist of polysilicon doped with, e.g., n-type impurities such as at least one of arsenic or phosphorus. Alternatively, the CSP240may include a metal silicide layer and a polysilicon layer doped with, e.g., n-type impurities sequentially stacked. The metal silicide layer may include, e.g., tungsten silicide.

The first sacrificial layer structure290may include first, second and third sacrificial layers260,270and280sequentially stacked in the first direction D1. The first and third sacrificial layers260and280may include an oxide, e.g., silicon oxide, and may not include a nitride, and the second sacrificial layer270may include a nitride, e.g., silicon nitride and may not include an oxide.

The first support layer300may include a material having an etching selectivity with respect to the first to third sacrificial layers260,270and280, e.g., polysilicon doped with n-type impurities. A portion of the first support layer300may extend through the first sacrificial layer structure290to contact an upper surface of the CSP240, which may form a first support pattern.

A first insulation layer310and a fourth sacrificial layer320may be alternately and repeatedly stacked on the first support layer300, and a second insulation layer311may be formed on an uppermost one of the fourth sacrificial layers320. A thickness of each of the first insulation layers310and the fourth sacrificial layers320may be the same, or may different. In some example embodiments, the first insulation layers310and the fourth sacrificial layers320are formed at three levels, respectively, however, inventive concepts may not be limited thereto. For example, the numbers of levels at which the first insulation layers310and the fourth sacrificial layers320are formed may be changed according to the number of the GIDL gate electrodes used in the erase operation for deleting data stored in the memory channel structure430using GIDL phenomenon.

The first and second insulation layers310and311may include an oxide, e.g., silicon oxide and may or may not include a nitride, and the fourth sacrificial layer320may include a material having an etching selectivity with respect to the first insulation layer310, e.g., a nitride such as silicon nitride and may or may not include an oxide.

Referring toFIGS.9and10, a first hole312may be formed through the second insulation layer311to contact an upper surface of the uppermost one of the fourth sacrificial layers320.

In some example embodiments, a plurality of first holes312may be formed to be adjacent to each other in the second direction D2on the second region II of the substrate100to form a first hole group, and a plurality of first hole groups may be spaced apart from each other in the second direction D2to form a first hole group column. In some example embodiments, a plurality of first hole group columns may be spaced apart from each other in the third direction D3.

In the drawings, the first hole group includes two first holes312adjacent to each other in the second direction D2and three first holes312adjacent to each other in the second direction D2, however, inventive concepts may not be limited thereto, and the first hole group may include one or a plurality of first holes312adjacent to each other in the second direction D2.

In some example embodiments, each of the first holes312may have a shape of at least one of a circle, an ellipse, a polygon, or a rounded polygon with rounded corners, and each of the first circle holes312may have the same shape or different shapes and may have the same diameter or different diameters.

Referring toFIGS.11to13, the upper surface of the uppermost one of the fourth sacrificial layers320may be partially removed to form a first gap322.

In some example embodiments, the fourth sacrificial layer320may be partially removed by an isotropic process such as a wet etching process using an etching solution including, e.g., phosphoric acid (H3PO4). The wet etching process is an isotropic etching process, and thus an outer contour of the first gap322may be blown out or have or be shaped as a curve, e.g., a shape of a circle or an ellipse in a plan view. The first holes312adjacent to each other in the second direction D2are formed, and thus in a plan view, e.g. from a perspective looking down on from a direction parallel to the plane formed by the directions D2and D3, the shape of the outer contour of the first gap322may be a shape including circles or ellipses arranged in the second direction D2in which the circles or ellipses partially overlap each other.

Referring toFIG.14, a first division layer330may be formed on the uppermost one of the fourth sacrificial layer320and the second insulation layer311to fill the first gaps322and the first holes312.

In some example embodiments, the first division layer330may be formed by an atomic layer deposition (ALD) process, and may include, e.g. may consist of, an oxide, e.g., silicon oxide.

A first recess may be formed on a portion of the first division layer330on each of the first holes312. The first gap322and/or the first hole312might not be filled with the first division layer330during the ALD process, and a void may be formed in the first division layer330.

Referring toFIG.15, an etch-back process and/or buffing chemical mechanical polishing (CMP) process may be performed on an upper surface of the first division layer330, so as to remove the first recesses332.

A fourth sacrificial layer320and the first insulation layer310may be alternately and repeatedly stacked on the first division layer330. The first insulation layers310, the fourth sacrificial layers320, the second insulation layer311and the first division layer330may form a mold layer. The fourth sacrificial layer320and the first insulation layer310may have the same, or different, thicknesses from one another.

In some example embodiments, the first division layer330may include a first horizontal portion330ain the first gap322, a vertical portion330bin the first hole312, and a second horizontal portion330con the second insulation layer311and the vertical portion330b. The vertical portion330bmay be formed between the first and second horizontal portions330aand330cto be connected thereto. In some example embodiments, one or a plurality of vertical portions330bmay be formed on the first horizontal portion330a. A plurality of first horizontal portions330amay be spaced apart from each other in the second direction D2to form a first horizontal portion column, and a plurality of first horizontal portion columns may be formed to be spaced apart from each other in the third direction D3.

Referring now toFIG.16, a photoresist pattern (not shown) may be formed on an uppermost one of the first insulation layers310, and the uppermost one of the first insulation layers310and an uppermost one of the fourth sacrificial layers320may be etched using the photoresist pattern as an etching mask. Thus, one of the first insulation layers310directly under the uppermost one of the fourth sacrificial layers320may be partially exposed.

A trimming process in which an area of the photoresist pattern is reduced by a given (e.g. a variable and/or a predetermined) ratio may be performed, and the uppermost one of the first insulation layers310, the uppermost one of the fourth sacrificial layers320, the exposed one of the first insulation layers310, and one of the fourth sacrificial layers320directly under the exposed one of the first insulation layers310may be etched using the photoresist pattern having the reduced area. The trimming process and the etching process may be alternately and repeatedly performed to form a mold having a staircase shape/step shape including a plurality of step layers each of which may include one fourth sacrificial layer320and one first insulation layer310sequentially stacked.

Hereinafter, the “step layer” may be defined as not only an exposed portion but also a non-exposed portion of the fourth sacrificial layer320and the first insulation layer310at the same level, and the exposed portion thereof may be defined as a “step.” In some example embodiments, the steps may be arranged in the second direction D2. Alternatively or additionally, the steps may also be arranged in the third direction D3.

In some example embodiments, lengths in the second direction D2of the steps included in the mold may be uniform except for lengths of some ones, which may be greater than the lengths of other ones. Hereinafter, ones of the steps having relatively small lengths may be referred to as first steps, and other ones of the steps having relatively large lengths may be referred to as second steps.FIG.16shows two second steps. The steps will be denoted by dotted lines in plan views hereinafter.

The mold may be formed on the first support layer300on the first and second regions I and II of the substrate100, and an edge upper surface of the first support layer300may not be covered by the mold but exposed. The steps of the mold may be formed on the second region II of the substrate100.

Referring toFIGS.17to20, a third insulating interlayer340may be formed on the CSP240to cover the mold and the first support layer300, and may be planarized e.g. with an etch back and/or with a CMP process, until an upper surface of the uppermost one of the first insulation layers310of the mold may be exposed. Thus, a sidewall of the mold, an upper surface and a sidewall of the first support layer300, and a sidewall of the first sacrificial layer structure290may be covered by the third insulating interlayer340. A fourth insulating interlayer350may be formed on upper surfaces of the mold and the third insulating interlayer340.

A channel hole extending in the first direction D1may be formed through the fourth insulating interlayer350, the mold, the first support layer300and the first sacrificial layer structure290on the first region I of the substrate100to expose an upper surface of the CSP240, and a dummy channel hole extending in the first direction D1may be formed through the third and fourth insulating interlayers340and350, a portion of the mold, the first support layer300and the first sacrificial layer structure290on the second region II of the substrate100to expose an upper surface of or a partially etched surface of the CSP240. In some example embodiments, a plurality of channel holes may be formed in each of the second and third directions D2and D3on the first region I of the substrate100, and a plurality of dummy channel holes may be formed in each of the second and third directions D2and D3on the second region II of the substrate100.

The channel holes and the dummy channel holes may be simultaneously formed by the same etching process, or may be sequentially formed by independent etching processes. A diameter of the channel holes may be the same as, or different from, a diameter of the dummy holes.

A charge storage structure layer and a channel layer may be sequentially formed on sidewalls of the channels hole and the dummy channel holes, the exposed upper surface of the CSP240, and an upper surface of the fourth insulating interlayer350, and a filling layer may be formed on the channel layer to fill the channel holes and the dummy channel holes. The filling layer, the channel layer and the charge storage structure layer may be planarized e.g. with an etch back and/or a CMP process until the upper surface of the fourth insulating interlayer350is exposed.

Thus, a charge storage structure390, a channel400and a first filling pattern410sequentially stacked may be formed on the channel hole, a dummy charge storage structure392, a dummy channel402and a dummy filling pattern412sequentially stacked may be formed on the dummy channel hole.

In some example embodiments, the charge storage structure390may include a tunnel insulation pattern380, a charge storage pattern370and a first blocking pattern360sequentially stacked from an outer sidewall of the channel400in a horizontal direction substantially parallel to the upper surface of the substrate100. The tunnel insulation pattern380and the first blocking pattern360may include or consist of an oxide, e.g., silicon oxide, the charge storage pattern370may include a nitride or consist of, e.g., silicon nitride, the channel400may include or consist of, e.g., doped or undoped polysilicon and/or doped or undoped single crystalline silicon, and the filling pattern410may include or consist of an oxide, e.g., silicon oxide.

In some example embodiments, the dummy charge storage structure392may include, e.g. may consist of, the same material as the charge storage structure390, the dummy channel402may include, e.g. may consist of, the same material as the channel400, and the dummy filling pattern412may include, e.g. may consist of, the same material as the filling pattern410. Thus, the dummy charge storage structure392may include a dummy tunnel insulation pattern, a dummy charge storage pattern and a dummy blocking pattern sequentially stacked from an outer sidewall of the dummy channel402in the horizontal direction.

Upper portions of the filling pattern410and the channel400may be removed to form a first trench, a capping layer may be formed on the filling pattern410, the channel400, the charge storage structure390and the fourth insulating interlayer350, and may be planarized e.g. with an etch back and/or a CMP process until the upper surface of the fourth insulating interlayer350is exposed to form a capping pattern420filling the first trench. The capping pattern420may include, e.g., polysilicon doped with impurities such as boron and/or arsenic and/or phosphorus.

When the first trench is formed, the dummy filling pattern412and the dummy channel402may also be removed to form a second trench, and when the capping pattern420is formed, a dummy capping pattern422may also be formed in the second trench. Thus, the dummy capping pattern422may include or consist of the same material as the capping pattern420.

The filling pattern410, the channel400, the charge storage structure390and the capping pattern420may form a memory channel structure430, which may correspond to the memory channel structures3220and4220shown inFIGS.3and4. Additionally, the dummy filling pattern412, the dummy channel402, the dummy charge storage structure392and the dummy capping pattern422may form a dummy memory channel structure432, which may not be electrically active. However, the dummy memory channel structure432might not serve as a memory channel structure of the memory cell, but may support the mold, and thus may be referred to as a support structure432, hereinafter.

In some example embodiments, each of the memory channel structure430and the support structure432may have a shape of a pillar or cylinder extending in the first direction D1. Each of the memory channel structure430and the support structure432may have a shape of, e.g., a circle, an ellipse, a rectangle, or a rounded rectangle having rounded corners in a plan view. The numbers and/or layouts of the memory channel structure430and the support structure432may not be limited to those shown in the drawings, but may be varied.

In some example embodiments, a plurality of memory channel structures430may be formed in each of the second and third directions D2and D3to form a memory group, and a plurality of memory groups may be formed in the third direction D3to form a memory block. The erase operation of the semiconductor device may be performed in units of the memory block.FIG.17shows two memory blocks arranged in the third direction D3, and each memory block includes two memory groups arranged in the third direction D3.

The fourth insulating interlayer350and some of the first insulation layers310and the fourth sacrificial layers320may be etched to form a first opening extending in the second direction D2, and a second division pattern440may be formed in the first opening.

The second division pattern440may extend through some of the channels400, particularly, upper portions of the channels400included at a central portion in the third direction D3in each memory group. Additionally or alternatively, the second division pattern440may also extend through the fourth insulating interlayer350, ones of the fourth sacrificial layers320at upper two levels, and ones of the first insulation layers310at upper two levels, and may further extend through one of the first insulation layers310at a third level from above. The second division pattern440may extend in the second direction D2on the first and second regions I and II of the substrate100, and may extend through upper two step layers of the mold. Thus, the fourth sacrificial layers320at two upper levels of the mold may be divided in the third direction D3by the second division pattern440.

However, the number of levels of the fourth sacrificial layers320divided by the second division pattern440may increase according to the number of levels of GIDL gate electrodes as explained below.

Referring toFIGS.21to24, a fifth insulating interlayer450may be formed on the fourth insulating interlayer350, the capping pattern420, and the second division pattern440, and second to fourth openings460,465and467may be formed through the third to fifth insulating interlayers340,350and450and the mold by an etching process.

In some example embodiments, the second opening460may extend in the second direction D2on the first and second regions I and II of the substrate100, and may extend to opposite ends in the second direction D2of the mold having a staircase shape. In some example embodiments, a plurality of second openings460may be spaced apart from each other in the third direction D3. Thus, the mold may be divided into a plurality of parts in the third direction D3by the second openings460. In some example embodiments, each of the second openings460may be formed between the memory blocks. For example, the memory blocks may be divided by the second openings460to be spaced apart from each other in the third direction D3.

As the second opening460is formed, the first and second insulation layers310and311and the fourth sacrificial layers320of the mold may be divided into first and second insulation patterns315and316and fourth sacrificial patterns325, respectively, each of which may extend in the second direction D2. Additionally or alternatively, the second horizontal portion330cof the first division layer330may also be divided into a plurality of parts each of which may extend in the second direction D2. Hereinafter, the first division layer330may be referred to as a first division pattern335, and the first and second horizontal portions330aand330cand the vertical portion330bwill be denoted by reference numerals335a,335cand335b, respectively.

In some example embodiments, the third opening465may continuously extend in the second direction D2on the first region I of the substrate100, however, a plurality of third openings465may be spaced apart from each other in the second direction D2on the second region II of the substrate100. The third openings465arranged in the second direction D2may be formed between neighboring ones of the second openings460in the third direction D3. In some example embodiments, the third openings465may be formed between memory groups in each of the memory blocks spaced apart from each other by the second openings460. For example, the memory groups may be spaced apart from each other in the third direction D3by the third openings465in each of the memory blocks.

However, the third openings465may be spaced apart from each other in the second direction D2, which may be different from the second opening460continuously extending in the second direction D2to opposite ends in the second direction D2of the mold, and thus the memory groups in each memory block may not entirely divided from each other by the third opening465. In some example embodiments, each of ends in the second direction D2of each third opening465may partially penetrate through the first horizontal portion335aof the first division pattern335, and may partially or entirely penetrate through the vertical portions335bneighboring in the second direction D2.

In the drawings, end portions of the third openings465may entirely penetrate through two second vertical portions335bneighboring in the second direction D2in a portion of the first division pattern335having the two second vertical portions335b, and end portions of the third openings465may entirely penetrate through two second vertical portions335bat opposite sides in the second direction D2in a portion of the first division pattern335having three second vertical portions335bneighboring in the second direction D2, however, inventive concepts may not be limited thereto. As end portions of the third openings465partially penetrate through a portion of the first horizontal portion335a, the first horizontal portion335amay have a shape including circles or ellipses arranged in the second direction D2but partially overlapping each other and opposite sides of the circles or ellipses in the second direction D2are removed.

Each of the third openings465may continuously extend in the second direction D2on the first region I of the substrate100, and may continuously extend to end portions in the second direction D2of the step layers of the mold at upper two levels even on the second region II of the substrate100. Thus, the fourth sacrificial patterns325at the upper two levels of the mold may be divided by the third opening465and the second division patterns440at opposite sides in the third direction D3of the third opening465. However, as mentioned above, the number of levels of the fourth sacrificial patterns325divided by the second division patterns440may increase according to the number of the GIDL gate electrodes.

The fourth opening467may be formed on the second region II of the substrate100, and may have a closed ring shape in a plan view. Hereinafter, portions of the first and second insulation patterns315and316and the fourth sacrificial pattern325surrounded by the fourth opening467having the closed ring shape may be referred to as third, fourth and fifth insulation patterns317,318and319, respectively, and may form an insulation pattern structure600together with a portion of the first division pattern335surrounded by the fourth opening467(in the drawing, a portion of the vertical portion335band a portion of the second horizontal portion335c). In some example embodiments, the fourth opening467may extend through the second step having a relatively large length in the second direction D2, and may be formed between neighboring ones of the second openings460in the third direction D3.

In an example embodiment, the fourth opening467may have a rectangular ring shape in a plan view, and opposite sides in the third direction D3of the rectangular ring shape may be aligned with the second division pattern440in the second direction D2. However, inventive concepts may not be limited thereto, and the fourth opening467may have, e.g., a rounded rectangular ring shape, an elliptical ring shape, a circular ring shape, etc.

In some example embodiments, the fourth opening467may be formed between neighboring ones of the third openings465in the second direction D2, but at least a portion of the fourth opening467may partially penetrate through the first horizontal portion335aof the first division pattern335. Thus, one of the fourth sacrificial patterns325at a lowermost level of the mold between the second openings460may be divided in the third direction D3by the third opening465extending in the second direction D2on the first region I of the substrate100, and may be divided in the third direction D3by the third openings465spaced apart from each other in the second direction D2, the fourth openings467between the third openings465, the insulation pattern structure600surrounded by the fourth openings467, and the first horizontal portion335aof the first division pattern335.

Even though the mold may be divided into a plurality of parts spaced apart from each other in the third direction D3each of which may extend in the second direction D2by the etching process for forming the second to fourth openings460,465and467, the mold may not lean or fall down by the support structures432and the memory channel structures430extending through the mold.

In some example embodiments, the etching process may be performed until the second to fourth openings460,465and467expose an upper surface of the first support layer300, and further extend through an upper portion of the first support layer300.

A first spacer layer may be formed on sidewalls of the second to fourth openings460,465and467and an upper surface of the fifth insulating interlayer450, and may be anisotropically etched so that portions of the first spacer layer on bottoms of the second to fourth openings460,465and467may be removed to form a first spacer470. Thus, an upper surface of the first support layer300may be partially exposed.

The exposed first support layer300and a portion of the first sacrificial layer structure290thereunder may be removed to enlarge the second to fourth openings460,465and467downwardly. Accordingly, each of the second and third openings460and465may expose an upper surface of the CSP240, and further extend through an upper portion of the CSP240.

In some example embodiments, the first spacer470may include, e.g., undoped polysilicon. When the first sacrificial layer structure290is partially removed, the sidewalls of the second to fourth openings460,465and467may be covered by the first spacer470, and thus the first and second insulation patterns315and316and the fourth sacrificial pattern325included in the mold may not be removed.

Referring toFIG.25, the first sacrificial layer structure290exposed by the second to fourth openings460,465and467may be removed by, e.g., an isotropic etching process such as a wet etching process to form a second gap295.

The wet etching process may be performed using, e.g., hydrofluoric acid such as buffered hydrofluoric acid and/or phosphoric acid such as hot phosphoric acid.

As the second gap295is formed, a lower portion of the first support layer300and an upper surface of the CSP240may be exposed. Additionally, a sidewall of the charge storage structure390may be partially exposed by the second gap295, and the exposed sidewall of the charge storage structure390may also be removed to expose an outer sidewall of the channel400. Accordingly, the charge storage structure390may be divided into an upper portion extending through the mold to cover most portion of the outer sidewall of the channel400and a lower portion covering a lower surface of the channel400on the CSP240.

Referring toFIG.26, after removing the first spacer470, a channel connection layer may be formed on the sidewalls of the second to fourth openings460,465and467and in the second gap295, and a portion of the channel connection layer in the second to fourth openings460,465and467may be removed to form a channel connection pattern480in the second gap295.

As the channel connection pattern480is formed, the channels400between neighboring ones of the second and third openings460and465in the third direction D3, for example, the channels400included in each channel group may be connected with each other.

An air gap485may be formed in the channel connection pattern480.

Referring toFIGS.27to29, second and third sacrificial layer structures520and525and an etch stop structure527may be formed in the second, third and fourth openings460,465and467, respectively.

The second and third sacrificial layer structures520and525and the etch stop structure527may be formed by sequentially forming an etch stop layer and a second spacer layer on the sidewalls of the second to fourth openings460,465and467and the exposed upper surface of the CSP240, forming a fifth sacrificial layer on the second spacer layer to fill the second to fourth openings460,465and467, and planarizing the fifth sacrificial layer, the second spacer layer and the etch stop layer until the upper surface of the fifth insulating interlayer450is exposed.

The second sacrificial layer structure520may include a first etch stop pattern490, a second spacer500and a fifth sacrificial pattern510sequentially stacked, the third sacrificial layer structure525may include a second etch stop pattern495, a third spacer505and a sixth sacrificial pattern515sequentially stacked, and the etch stop structure527may include a third etch stop pattern497, a fourth spacer507and a second filling pattern517sequentially stacked.

The etch stop layer may include a material having an etching selectivity with respect to the fourth sacrificial pattern325, e.g., an oxide such as silicon oxide. The second spacer layer may include, e.g., a nitride such as silicon nitride, and the fifth sacrificial layer may include, e.g., polysilicon or silicon oxide.

Referring toFIGS.30and31, a second support layer530may be formed on the fifth insulating interlayer450, the second and third sacrificial layer structures520and525, and the etch stop structure527, and may be partially etched to form fifth and sixth openings540and545.

In some example embodiments, the fifth opening540may overlap the second sacrificial layer structure520in the first direction D1. In the drawing, the fifth opening540continuously extends in the second direction D2on the second region II of the substrate100, and a plurality of fifth openings540is spaced apart from each other in the second direction D2on the first region I of the substrate100. However, inventive concepts may not be limited thereto, and a plurality of fifth openings540may be spaced apart from each other in the second direction D2even on the second region II of the substrate100. In an example embodiment, the fifth opening540may have a width in the third direction D3greater than that of the second sacrificial layer structure520, however, inventive concepts may not be limited thereto.

In some example embodiments, the sixth opening545may overlap the third sacrificial layer structure525in the first direction D1. Thus, a plurality of sixth openings545may be spaced apart from each other in the second direction D2on the second region II of the substrate100. Additionally, a plurality of sixth openings545may be spaced apart from each other in the second direction D2on the same third sacrificial layer structure525even on the first region I of the substrate100. In an example embodiment, the sixth opening545may have a width in the third direction D3greater than that of the third sacrificial layer structure525, however, inventive concepts may not be limited thereto.

In some example embodiments, the fifth and sixth openings540and545may be arranged in a zigzag pattern in the second direction D2on the first region I of the substrate100. The fifth and sixth openings540and545may partially overlap each other in the third direction D3.

The second support layer530may include an oxide, e.g., silicon oxide. The etch stop structure527may be entirely covered by the second support layer530, and may not be exposed.

Referring toFIG.32, the second and third sacrificial layer structures520and525may be removed by an etching process through the fifth and sixth openings540and545, and thus the second and third openings460and465may be formed again.

As illustrated above, the fifth and sixth openings540and545might not entirely expose but partially cover upper surfaces of the second and third sacrificial layer structures520and525, respectively, on the first region I of the substrate100, an thus, even though the second and third openings460and465are formed again by the etching process, the upper surfaces of the second and third sacrificial layer structures520and525may be at least partially covered by the second support layer530. Accordingly, even though an upper surface of the mold is high and an extension length in the second direction D2is large, the mold might not lean or fall down in the third direction D3, due to the second support layer530at least partially covering portions of the mold where the second and third openings460and465are formed.

A plurality of third openings465is spaced apart from each other in the second direction D2on the second region II of the substrate100so that a portion of the mold remain between the third openings465, and the support structures432extend through the mold, and thus the mold may not lean or fall down in the third direction D3due to the portion of the mold and the support structures432.

In some example embodiments, the second and third sacrificial layer structures520and525may be removed by a wet etching process.

An oxidation process may be performed on a layer structure including silicon and exposed by the second and third openings460and465to form a protection layer550. In some example embodiments, as the oxidation process is performed, the protection layer550may be formed on the upper surface of the CSP240exposed by the second and third openings460and465, a sidewall of the channel connection pattern480, and a sidewall of the first support layer300. The protection layer550may include, e.g., silicon oxide.

Referring toFIGS.33and34, the fourth sacrificial patterns325exposed by the second and third openings460and465may be removed to form a third gap560between the first insulation patterns315, and an outer sidewall of the charge storage structure390included in the memory channel structure430and an outer sidewall of the dummy charge storage structures392included in the support structure432may be partially exposed by the third gap560.

In some example embodiments, the fourth sacrificial patterns325may be removed by a wet etching process using, e.g., phosphoric acid (H3PO4) and/or sulfuric acid (H2SO4).

The wet etching process may be performed through the second and third openings460and465, and a portion of the fourth sacrificial pattern325between the second and third openings460and465may be entirely removed by an etching solution provided through the second and third openings460and465in two ways. However, the etching solution may be provided only in one way through the second opening460at an area where the etch stop structure527is formed, and thus the fourth sacrificial pattern325might not be entirely removed but partially remain.

An outer sidewall of the etch stop structure527may be exposed by the wet etching process, however, the third etch stop pattern497having an etching selectivity with respect to the fourth sacrificial pattern325may be formed on the outer sidewall of the etch stop structure527, so that the etch stop structure527might not be removed by the wet etching process. Accordingly, portions of the third to fifth insulation patterns317,318and319surrounded by the etch stop structure527might not be removed, either.

Referring toFIGS.35and36, a second blocking layer570may be formed on the outer sidewall of the charge storage structure390exposed by the second and third openings460and465, the outer sidewall of the dummy charge storage structure392included in the support structure432exposed by the second and third openings460and465, inner walls of the third gaps560, surfaces of the first insulation patterns315, an upper surface of the protection layer550, a sidewall and an upper surface of the fifth insulating interlayer450, and a sidewall and an upper surface of the second support layer530, and a gate electrode layer may be formed on the second blocking layer570.

The gate electrode layer may include a gate barrier layer and a gate conductive layer sequentially stacked. The gate electrode layer may include a low resistance metal, and the gate barrier layer may include a metal nitride. The second blocking layer570may include a metal oxide, e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.

The gate electrode layer may be partially removed to form a gate electrode in each of the third gaps560. In some example embodiments, the gate electrode layer may be partially removed by a wet etching process. As a result, the fourth sacrificial pattern325in the mold having the staircase shape including the fourth sacrificial pattern325and the first insulation pattern315sequentially stacked as a step layer may be replaced with the gate electrode and the second blocking layer570covering lower and upper surfaces of the gate electrode.

In some example embodiments, the gate electrode may extend in the second direction D2, and a plurality of gate electrodes may be spaced apart from each other in the first direction D1to form a gate electrode structure. The gate electrodes may be staked in a staircase shape in which extension lengths in the second direction D2decrease in a stepwise manner from a lowermost level toward an uppermost level. An end portion in the second direction D2of each of the gate electrodes that is not overlapped with upper gate electrodes in the first direction D1, that is, the step of each of the step layers may be referred to as a pad. The gate electrode structure may include first pads having a relatively short length in the second direction D2and second pads having a relatively large length in the second direction D2. The numbers of the first and second pads might not be limited.

Additionally, a plurality of gate electrode structures may be formed in the third direction D3. That is, the gate electrode structures may be spaced apart from each other in the third direction D3by the second openings460. As illustrated above, the third opening465might not extend in the second direction D2to opposite ends in the second direction D2of the gate electrode structure, but a plurality of third openings465may be spaced apart from each other in the second direction D2, and thus the gate electrode structure might not be divided by the third openings465. However, one of the gate electrodes at a lowermost level may be divided in the third direction D3by the third and fourth openings465and467, the first division pattern335and the insulation pattern structure600, and each one of the gate electrodes at upper two levels may be divided in the third direction D3by the third opening465and the second division pattern440.

In some example embodiments, the gate electrode structure may include first to fourth gate electrodes751,752,754and756sequentially stacked in the first direction D1. In some example embodiments, the first gate electrode751may be formed at a lowermost level and a second level from below, and may serve as a GIDL gate electrode for being used in erase operation. The second gate electrode752may be formed on the first gate electrode751, and may serve as a ground selection line (GSL). The fourth gate electrode756may be formed at an uppermost level and a second level from above, and may serve as a string selection line (SSL). The third gate electrode754may be formed at a plurality of levels between the second and fourth gate electrodes752and756, and may serve as word lines, respectively. However, the numbers of levels at which the first to fourth gate electrodes751,752,754and756are formed might not be limited to the above, and may be varied.

Additionally, the first gate electrode751may be further formed on the fourth gate electrode756. For example, if the first gate electrode751is further formed at an uppermost level and a second level from above, the first and fourth gate electrodes751and756at upper four levels, respectively, of the mold may be divided in the third direction D3by the third opening465and the second division patterns440at opposite sides in the third direction D3.

In some example embodiments, each of the memory blocks between neighboring ones of the second openings460in the third direction D3may include two GSLs, one word line and four SSLs at each level, however, inventive concepts might not be limited thereto.

Referring toFIGS.37to39, a third division pattern580filling the second and fifth openings460and540and a fourth division pattern585filling the third and sixth openings465and545may be formed on the second blocking layer570, and may be planarized until an upper surface of the second support layer530is exposed. Thus, the second blocking layer570may be transformed into a second blocking pattern575.

The third and fourth division patterns580and585may include an oxide, e.g., silicon oxide.

Referring toFIGS.40to42, first to fourth upper contact plugs610,620,622and624may be formed through the second support layer530, the third to fifth insulating interlayers340,350and450, and the first insulation pattern315on the second region II of the substrate100.

The first to fourth contact plugs610,620,622and624may contact pads of the fourth, third, second and first gate electrodes756,754,752and751, respectively. In some example embodiments, each of the first to fourth upper contact plugs610,620,622and624may be formed in an area surrounded by the support structure432in each of the first and second pads of the gate electrode structure. For example, the support structures432may be disposed at vertices of a rectangle in a plan view, and each of the first to fourth upper contact plugs610,620,622and624may be formed in an inside of the rectangle.

FIG.40shows exemplary layouts of the first to fourth upper contact plugs610,620,622and624, however, inventive concepts may not be limited thereto, and thus the numbers and layouts of the first to fourth upper contact plugs610,620and622may be varied.

Referring toFIGS.43to45, a sixth insulating interlayer630may be formed on the second support layer530and the first to fourth upper contact plugs610,620,622and624, and a through via650may be formed through the insulation pattern structure600surrounded by the etch stop structure527, the first support layer300, the channel connection pattern480, the CSP240and the second insulating interlayer170on the second region II of the substrate100to contact an upper surface of the eighth lower wiring222.

A plurality of through vias650may be formed to be spaced apart from each other in an area where the insulation pattern structure600is formed. In the drawing, six through vias650are formed in each area, however, inventive concepts might not be limited thereto.

A sixth insulation pattern640may be formed on a sidewall of the through via650, and may be electrically connected to the first support layer300, the channel connection pattern480and the CSP240. However, the through via650may extend through the insulation pattern structure600, that is, the third to fifth insulation patterns317,318and327to be electrically insulated from the first to fourth gate electrodes751,752,754and756, and thus, if an additional insulation pattern is formed on sidewalls of the first support layer300, the channel connection pattern480and the CSP, the sixth insulation pattern640might not be formed.

The first to fourth contact plugs610,620,622and624and the through via650may include, e.g., a metal, a metal nitride, a metal silicide, etc., and the sixth insulation pattern640may include an oxide, e.g., silicon oxide.

A common source contact plug may be further formed through a portion of the first support layer300that is not covered by the gate electrode structure.

Referring toFIGS.46to49, a seventh insulating interlayer660may be formed on the sixth insulating interlayer630, the sixth insulation pattern640and the through via650, and fourth and fifth upper contact plugs672and674, sixth and seventh upper contact plugs, and eighth and ninth upper contact plugs680and690may be formed.

The fourth and fifth upper contact plugs672and674and the sixth and seventh upper contact plugs may extend through the sixth and seventh insulating interlayers630and660to contact upper surfaces of the first to fourth upper contact plugs610,620,622and624, respectively, the eighth upper contact plug680may extend through the seventh insulating interlayer660to contact an upper surface of the through via650, and the ninth upper contact plug690may extend through the second support layer530and the fifth to seventh insulating interlayers450,630and660to contact an upper surface of the capping pattern420.

An eighth insulating interlayer700may be formed on the seventh insulating interlayer660, the fourth and fifth upper contact plugs672and674, the sixth and seventh upper contact plugs, and the eighth and ninth upper contact plugs680and690, and first and second upper wirings712and714, third and fourth upper wirings, and fifth and sixth upper wirings720and730may be formed.

The first and second upper wirings712and714may contact upper surfaces of the fourth and fifth upper contact plugs672and674, respectively, the third upper wiring may contact upper surfaces of the sixth and seventh upper contact plugs, respectively, and the fifth and sixth upper wirings720and730may contact upper surfaces of the eighth and ninth upper contact plugs680and690, respectively.

In some example embodiments, the sixth upper wiring730may extend in the third direction D3, and a plurality of sixth upper wirings730may be formed. The sixth upper wiring may serve as a bit line. Alternatively, an additional upper via and a seventh upper wiring may be further formed on the sixth upper wiring730, and the seventh upper wiring may serve as a bit line.

The numbers and layouts of the first and second upper wirings712and714, the third and fourth upper wirings, and the fifth upper wiring720on the second region II of the substrate100may be varied.

The fabrication of the semiconductor device may be completed by the above processes.

As illustrated above, the first insulation layer310and the fourth sacrificial layer320may be alternately and repeatedly stacked in the first direction D1, the second insulation layer311may be formed on the uppermost one of the fourth sacrificial layers320, and the first holes312may be formed through the second insulation layer311to expose the uppermost one of the fourth sacrificial layers320. The exposed uppermost one of the fourth sacrificial layers320may be removed by, e.g., a wet etching process, which is an isotropic etching process, to form the first gap322exposing the uppermost one of the first insulation layers310, the first division layer330may be formed on the uppermost one of the first insulation layers310and the second insulation layer311to fill the first gap322and the first holes312, and an upper portion of the first division layer330may be planarized by, e.g., a buffing CMP process. The fourth sacrificial layer320and the first insulation layer310may be further stacked on the first division layer330alternately and repeatedly to form the mold layer.

The first division layer330may have a flat upper surface, and thus the fourth sacrificial layers320and the first insulation layers310alternately and repeatedly stacked on the first division layer330may not be bent but have uniform heights at an area overlapping the first gap322in the first direction D1. Conventionally, due to the bending of a portion of the mold layer on a division pattern for dividing the GSL, the electrical characteristics of the semiconductor device may be deteriorated, and thus, the portion of the mold layer has to be excessively removed in order to the deterioration of the electrical characteristics, which may aggravate the process margin in order to secure a distance from neighboring structures, e.g., the support structures432. However, in some example embodiments, the first division layer330filling the first gap322on the second insulation layer311may have the flat upper surface, and thus the portion of the mold layer overlapping the first gap322may not be bent, so as not to be excessively removed, which may increase the process margin. Additionally, the gate electrodes751,752,754and756that may be formed by replacing the fourth sacrificial layers320each of which may be stacked at a uniform height may have enhanced electrical characteristics.

The semiconductor device may have the following structural characteristics.

Referring toFIGS.43and44andFIGS.46to49, the semiconductor device may include the lower circuit patterns on the substrate100including the first region I and the second region II at least partially surrounding the first region I; the CSP240over the lower circuit patterns; the gate electrode structure including the gate electrodes752,754and756, each of which may extend in the second direction D2, spaced apart from each other in the first direction D1on the CSP240; the memory channel structure430including the channel400extending in the first direction D1through the gate electrode structure on the first region I of the substrate100to contact the upper surface of the CSP230and the charge storage structure390on the outer sidewall of the channel400; the third division pattern580extending in the second direction D2on each of opposite sides in the third direction D3of the gate electrode structure; the fourth division patterns585, each of which may extend in the second direction D2through the gate electrode structure between the third division patterns580, spaced apart from each other in the second direction D2; the first division pattern335between the fourth division patterns585and dividing the second gate electrode752in the third direction D3together with the fourth division patterns585; the insulation pattern structure600extending through a portion of the gate electrode structure on the CSP240; the through via650extending in the first direction D1through the insulation pattern structure600and the CSP240to contact and be electrically connected to one of the lower circuit patterns; the contact plugs610,620,622and624extending in the first direction D1to contact end portions in the second direction D2, that is, the pads of the gate electrodes752,754and756; and the support structure432extending in the first direction D1through the gate electrode structure to contact the upper surface of the CSP240, which may be adjacent to the contact plugs610,620,622and624.

In some example embodiments, the first division pattern335may include the first horizontal portion335aat the same level as the second gate electrode752serving as the GSL and dividing the second gate electrode752, the vertical portion connected to and extending from the first horizontal portion335athrough the second insulation pattern315in the first direction D1, and the second horizontal portion335cconnected to an upper end of the vertical portion335band on the second insulation pattern316.

In some example embodiments, the first horizontal portion335aof the first division pattern335may have a curved outer contour in a plan view. For example, the first horizontal portion335aof the first division pattern335may extend in the second direction D2, and may have an outer contour of a shape of a peanut, e.g. a two pea or three pea or more than three pea peanut, from which opposite ends in the second direction D2are removed when viewed in a plan view. Alternatively or additionally, the first horizontal portion335aof the first division pattern335may extend in the third direction D3, and may have an outer contour of a shape of a peanut from which opposite ends in the third direction D3are removed when viewed in a plan view. Alternatively or additionally, the first horizontal portion335aof the first division pattern335may extend in a fourth direction having an acute angle with the second and third directions D2and D3, and may have an outer contour of a shape of a peanut from which opposite ends in the fourth direction are removed when viewed in a plan view.

In some example embodiments, the first horizontal portion335aof the first division pattern335may partially overlap the fourth division pattern585in the third direction D3. That is, the fourth division pattern585may extend through opposite ends of the first horizontal portion335aof the first division pattern335in an extension direction thereof, and thus the first horizontal portion335aof the first division pattern335may have a shape of a peanut from which opposite ends are removed.

In some example embodiments, the vertical portion335bof the first division pattern335may have an outer contour of a shape of a circle or ellipse in a plan view.

In some example embodiments, the third gate electrode754serving as a word line may be formed on the second horizontal portion335cof the first division pattern335. Additionally, the first gate electrode751under the second gate electrode752may be or correspond to a GIDL gate electrode, and the first gate electrode751may be further formed over the fourth gate electrode756serving as an SSL.

In some example embodiments, the insulation pattern structure600may be surrounded by the etch stop structure527, and the etch stop structure527may partially extend through the second horizontal portion335cof the first division pattern335and the first horizontal portion335aand/or the vertical portion335bas well. The etch stop structure527may include a first extension portion extending in the second direction D2and a second extension portion extending in the third direction D3, and the second extension portion may partially extend through the first horizontal portion335aand/or the vertical portion335bof the first division pattern335.

In some example embodiments, the gate electrode structure and the third and fourth division patterns580and585may be formed on the first and second regions I and II of the substrate100, the memory channel structure430may be formed on the first region I of the substrate100, and the first division pattern335may be formed on the second region II of the substrate100.

In some example embodiments, the memory channel structure430may include the channel400having a cup-like shape, the charge storage structure390on the outer sidewall of the channel400, the first filling pattern410filling the inner space defined by the channel400, and the capping pattern420on the channel400and the first filling pattern410and contacting the inner sidewall of the charge storage structure390.

In some example embodiments, the support structure432may have the same structure as the memory channel structure430, however, the support structure432may be or correspond a dummy memory channel structure so as not serve as the channel400or the charge storage structure390, but may support, e.g. mechanically support, the semiconductor device.

FIG.50is a plan view illustrating a shape of the first division pattern included in a semiconductor device in accordance with some example embodiments, which may correspond toFIG.44.

Referring toFIG.50, the vertical portion335bof the first division pattern335may have, e.g., a bar shape extending in the second direction D2in a plan view. Alternatively, the vertical portion335bof the first division pattern335may have, e.g., a bar shape extending in the third direction D3in a plan view.

FIG.51is a plan view illustrating layouts of the etch stop structure and the first and fourth division patterns in a semiconductor device in accordance with some example embodiments, which shows one memory block of the semiconductor device.

Referring toFIG.51, the fourth division patterns585each of which may extend in the second direction D2may be spaced apart from each other in the third direction D3between the third division patterns580each of which may extend in the second direction D2on the first region I of the substrate100and a portion of the second region II of the substrate100where the pads of the gate electrodes at upper two levels, respectively, are formed.

The fourth division patterns585may be spaced apart from each other in the second direction D2between the third division patterns580each of which may extend in the second direction D2to form a fourth division pattern column, and a plurality of fourth division pattern columns may be spaced apart from each other in the third direction D3on a portion of the second region II of the substrate100where the pads of the gate electrodes at other levels, respectively, are formed.

The etch stop structure527may extend through the second pad of the gate electrode between the third division pattern580and the fourth division pattern585spaced apart from the third division pattern580in the third direction D3, and may be formed between the fourth division patterns585spaced apart from each other in the second direction D2.

Ends of the fourth division patterns585spaced apart from each other in the second direction D2, or ends of the fourth division patterns585spaced apart from each other in the second direction D2and the second extension portion of the etch stop structure527may extend through the first horizontal portion335aof the first division pattern335. Additionally or alternatively, portions of the fourth division patterns585spaced apart from each other in the third direction D3may also extend through the first horizontal portion335aof the first division pattern335. Thus, the memory block may include desired numbers of the GSL, the word line and the SSL by using the fourth division patterns585, the etch stop structure527and the first division pattern335. In the drawings, the memory block includes six SSLs, one word line, and three GSLs at each level, however, inventive concepts may not be limited thereto.

FIG.52is a cross-sectional view illustrating a semiconductor device in accordance with some example embodiments, which may correspond toFIG.48. This semiconductor device may be substantially the same as or similar to that ofFIGS.43,44and46to49, except for the memory channel structure430, the channel connection pattern480and the first support layer300.

The memory channel structure430may further include a semiconductor pattern590on the substrate100, and the charge storage structure390, the channel400, the first filling pattern410and the capping pattern420may be formed on the semiconductor pattern590.

The semiconductor pattern590may include, e.g., doped or undoped single crystalline silicon or polysilicon. In some example embodiments, an upper surface of the semiconductor pattern590may be formed at a height between lower and upper surfaces of the first insulation pattern315between the second and third gate electrodes752and754. The charge storage structure390may have a cup-like shape of which a central lower surface is opened, and may contact an edge upper surface of the semiconductor pattern590. The channel400may have a cup-like shape, and may contact a central upper surface of the semiconductor pattern590. Thus, the channel400may be electrically connected to the CSP240through the semiconductor pattern590.

The channel connection pattern480and the first support layer300may not be formed between the CSP240and the first gate electrode752.

FIG.53is a cross-sectional view illustrating a semiconductor device in accordance with some example embodiments, which may correspond toFIG.48. This semiconductor device may be substantially the same as or similar to that ofFIGS.43,44and46to49, except for the memory channel structure430.

The memory channel structure430may include lower and upper portions sequentially stacked, and each of the lower and upper portions may have a width gradually increasing from a bottom toward a top thereof. In some example embodiments, a lower surface of the upper portion of the memory channel structure430may have an area less than that of an upper surface of the lower portion thereof.

In the drawings, the memory channel structure430includes two portions, for example, the lower and upper portions, however, inventive concepts may not be limited thereto, and may include more than two portions. Each of the portions of the memory channel structure430may have a width gradually increasing from a bottom toward a top thereof, and an area of a lower surface of an upper portion may be less than that of an upper surface of a lower portion that is directly under the upper portion.

FIG.54is a cross-sectional view illustrating a semiconductor device in accordance with some example embodiments, which may correspond toFIG.48. This semiconductor device may be substantially the same as or similar to that ofFIGS.43,44and46to49, except that upper structures are overturned and bonding structures are further formed. The lower circuit patterns may corresponding to the peripheral circuit wirings4110ofFIG.4, and circuit structures including the lower circuit patterns may correspond to the first structure4100ofFIG.4.

In some example embodiments, ninth to twelfth insulating interlayers800,820,840and860may be sequentially stacked on the eighth and ninth lower wirings222and226and the second insulating interlayer170. Additionally or alternatively, a first bonding pattern extending through the ninth insulating interlayer800to contact the eight lower wiring222, and a second bonding pattern810extending through the ninth insulating interlayer800to contact the ninth lower wiring226may be formed. Furthermore, a third bonding pattern extending through the tenth insulating interlayer820to contact the first bonding pattern, and a fourth bonding pattern830extending through the tenth insulating interlayer820to contact the second bonding pattern810may be formed. The first to third bonding patterns and the second and fourth bonding patterns810and830may include a metal, e.g., copper, aluminum, etc., and may be formed by, e.g., a dual damascene process.

A seventh upper wiring extending through the eleventh insulating interlayer840to contact the third bonding pattern, and an eighth upper wiring850extending through the eleventh insulating interlayer840to contact the fourth bonding pattern830may be formed, and a first upper via extending through the twelfth insulating interlayer860to contact the seventh upper wiring, and a second upper via870extending through the twelfth insulating interlayer860to contact the eighth upper wiring850may be formed.

At least some of the first and second upper wirings712and714, the third upper wiring, the fourth and fifth upper wirings720and730, and the sixth upper wiring may be electrically connected to the lower circuit patterns through the first and third bonding patterns or the second and fourth bonding patterns.