Methods and apparatus for managing defective processors through power gating

Methods and apparatus provide for: selectively supplying a first source of power to a plurality of circuit blocks of a system using a plurality of gate circuits responsive to respective control signals provided by at least one control circuit; and providing a second source of power to operate the control circuit before the first source of power is available to the gate circuits such that the control signals are valid before such availability.

BACKGROUND

The present invention relates to methods and apparatus for managing defective processors of a multiprocessing system within an integrated circuit.

Large scale integrated circuits are being designed to accommodate an ever increasing number of circuits in order to achieve higher and higher functionality. For example, digital circuits (or analog circuits) are being designed with very high numbers of gates and other functional circuitry to meet processing objectives in the marketplace. As the complexity of integrated circuits (ICs) continue to increase, however, the number of transistors and other components used to implement the circuitry also increases and the probability of a faulty component or circuit occurring in an IC approaches one. The existence of a faulty circuit or component may require that the IC be discarded.

It has been proposed to use redundant circuits on the IC in order to permit replacement of the circuitry containing a faulty component. For example,FIG. 1illustrates an IC10employing digital circuit A, digital circuit B, digital circuit C, and digital circuit D, where one or more of the circuits may be redundant. Thus, even when a fault occurs, the IC10may be salvaged by enabling the redundant circuit. This can increase the IC yield and save the IC manufacturer a considerable amount of money. While the redundant circuit(s) may be activated and used in place of the faulty components, the faulty component may be deactivated. Conventional techniques for activating good circuits and deactivating faulty circuits include blowing fuses, such as electrical fuses (e-fuses) and/or laser-trimmed fuses.

The components or circuits of an IC may be faulty due to improper fabrication. For example, an imperfection may have been present on the substrate during fabrication or the fabrication procedure itself may be faulty. Improperly fabricated ICs may be discovered during IC testing, prior to packaging. If a faulty component is discovered on an IC during pre-packaging IC testing, the faulty component may be deactivated and a redundant circuit activated to take its place through the blowing of certain fuses, preferably, laser fuses since access to the IC is possible because the IC has yet to be packaged.

ICs may also be damaged after the pre-packaging IC testing. The components or circuits of an IC may be faulty due to damage during the packaging of the IC, for example, when the die is cut from the wafer, when the wafer is cleaned, when the die is bonded to the packaging, and so forth. ICs that become faulty due to packaging are usually not discovered until post-packaging testing. Since the packaging of an IC can be a considerable amount of the overall cost of manufacturing the IC, simply discarding a faulty IC could be expensive. A conventional technique proposes the use of additional redundant circuits that can be activated in place of the faulty components discovered in post-packaging IC testing. These additional redundant circuits can be activated through the use of electrical fuses (e-fuses), rather than laser fuses, since direct access to the IC is not possible. This can permit the use of a packaged IC that would have otherwise been discarded.

In order to minimize the complexity of the power and clock distribution networks of the IC, the redundant circuitry usually shares common power and clock distribution networks with the other circuits of the IC. Thus, in the majority of IC, the redundant circuitry is being actively clocked and powered although it is not being used. This can increase power consumption of the IC. Similarly, when a circuit containing a fault is disabled, it is still actively clocked and powered, which also contributes to the power consumption problem.

U.S. Patent Publication 2005-0036259, which is incorporated herein by reference, addresses the power consumption problem by proposing to gate the signaling and power to the redundant circuitry, such that the unused redundant circuitry does not receive clock signals or power. The decision as to whether to enable or disable the signaling and power to the unused redundant circuitry is based on the state of fuses used to enable/disable the redundant circuitry.

Unfortunately, the gating of clock signals and power (as well as other signaling) to unused redundant circuitry of an IC is not always practical or desirable.

Further, improper power and/or clock gating to faulty circuitry may arise during power up conditions because control signaling to the power gating devices may be unstable. Such improper gating may result in undesirable circuit operation on a temporary or permanent basis. For example, if during power up the control circuit commands one or more gating devices to permit power and/or clock signals to an associated faulty circuit, such circuit may affect neighboring circuits. This might occur, for example, if the faulty circuit exhibits electromagnetic interference that prevents proper operation of an adjacent circuit. Even if the faulty circuit receives power and/or clocking for a limited duration (e.g., prior to stabilization of the control signaling to the gating devices), the interference may require a re-initialization of the adjacent circuit in order to clear the effects of the interference.

Thus, another technique to permit enabling and disabling of circuitry on an IC is needed that limits unnecessary power dissipation by disabled circuitry and also insures that improper activation of the disabled circuitry is avoided.

SUMMARY OF THE INVENTION

It is noted that some ICs are designed with a plurality of circuits that are intended more for parallel functionality as opposed to redundancy. For example, in a parallel processing system, a number of processing circuits may be disposed in an IC, where each of the processors may operate in series or parallel to achieve a processing objective. While the processors may be redundant in the sense that they can perform the same functions, they are primarily provided for operation in parallel (and/or series) to increase processing performance.

By way of example, a multiprocessing system may have a potential of eight valid sub-processing units (SPUs processors) in a common IC. As discussed above, some of the SPUs may be faulty and, therefore, the overall performance of the IC may be reduced. Instead of enabling a redundant SPU to replace the faulty SPU, one or more embodiments of the invention contemplate disabling the faulty SPU and using the reduced performance multiprocessing system in an application (e.g., a product) that does not require a full complement of SPUs. For example, a high performance video game product may require a full complement of SPUs; however, a digital television (DTV) might not require a full complement of SPUs. Depending on the complexity of the application in which the multiprocessing system is to be used, a lesser number of SPU processors may be employed by disabling the faulty SPU processors and using the resulting multiprocessing system in a less demanding environment (such as a DTV).

Although it is desirable that disabling the unwanted SPU processors reduces the power dissipation within the CELL processor, conventional techniques have not adequately disconnected unwanted SPU processors from the power supply. Thus, one or more embodiments of the invention contemplate providing a means for disabling the unwanted SPU that also considerably reduces the power dissipation thereof by substantially interrupting power supply current from flowing through the SPU.

In accordance with one or more further embodiments of the invention, an SPU may be disabled even though it is not faulty. Indeed, in order to reduce power consumption in a particular application, one or more SPUs may be disabled when the application does not require a full complement of SPUs to achieve its performance goals.

In accordance with one or more embodiments of the present invention, methods and apparatus provide for: selectively supplying a first source of power to a plurality of circuit blocks of a system using a plurality of gate circuits responsive to respective control signals provided by at least one control circuit; and providing a second source of power to operate the control circuit before the first source of power is available to the gate circuits such that the control signals are valid before such availability.

Preferably, the control signaling, when valid, indicate not supplying the first source of power to any of the circuit blocks that are predetermined to be disabled.

In one or more embodiments, the second source of power is produced by gating the first source of power in accordance with a delay. The delay is predetermined and/or fixed. Alternatively, the first and second sources of power are separate power supplies, where the second power supply is initiated before the first power supply.

Other aspects, features, advantages, etc. will become apparent to one skilled in the art when the description of the invention herein is taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

With reference to the drawings, wherein like numerals indicate like elements, there is shown inFIG. 2a system100that may be adapted for carrying out one or more features of the present invention. For the purposes of brevity and clarity, the block diagram ofFIG. 2will be referred to and described herein as illustrating an apparatus100, it being understood, however, that the description may readily be applied to various aspects of a method with equal force. Reference is also made toFIG. 3, which is a flow diagram illustrating a process that may be carried out by the system100(or other system described herein) according to one or more further embodiments of the present invention.

The apparatus100preferably includes a plurality of circuit blocks102A-H, a plurality of gate circuits150A-H, and a control circuit152. In an alternative embodiment of the invention, the system100may also include a master gate circuit140.

It is understood that any number of circuit blocks102may be employed without departing from the spirit and scope of the one or more embodiments of the invention. The circuit blocks102are generally operable to produce one or more output signals in response to operating power and one or more input signals. For example, the circuit blocks102may be digital circuits, such as combinational logic circuits, processing circuits, microprocessor circuits, digital signal processing circuits, etc.

In a preferred embodiment, circuit blocks102are processors102that may be implemented utilizing any of the known technologies that are capable of requesting data from a system memory (not shown), and manipulating the data to achieve a desirable result. For example, the processors102may be implemented using any of the known microprocessors that are capable of executing software and/or firmware, including standard microprocessors, distributed microprocessors, etc. By way of example, the processors102may be graphics processors that are capable of requesting and manipulating data, such as pixel data, including gray scale information, color information, texture data, polygonal information, video frame information, etc.

The gate circuits150are each preferably operable to selectively supply operating power VDC1the circuit blocks102in response to one or more respective control signals154output from the control circuit152. It is understood that each gate circuit150may selectively supply the operating power VDC1to a single circuit block102(as shown) or to multiple blocks102. When utilized, the master gate circuit140is preferably operable to supply the operating power VDC1to the gate circuits150in response to a delay functionality (discussed in more detail below).

With reference toFIG. 3, the circuit blocks102are preferably tested during manufacture to determine whether they are faulty (action200) In an alternative embodiment, some circuit blocks102may be designated faulty even if they function properly in order to reduce the number of operational circuits102in the system100. In either case, the designation of a faulty circuit is preferably noted and used to program the control circuit152(action202). In a general sense, the control circuit152is programmed such that it is operable to produce the control signaling154to indicate, when valid, not to supply the first operating power to any of the circuit blocks102that are predetermined to be disabled.

FIG. 4is a block diagram illustrating a configuration suitable for implementing the control circuit152in accordance with one or more embodiments of the present invention. The control circuit152includes a memory circuit152A and a driver circuit152B coupled to one another by way of one or more signal lines152C. In one or more embodiments, the memory circuit152A may be a plurality of e-fuses, or the like, that are permanently configured during the manufacturing process to provide appropriate signaling that conveys the fault status of the plurality of circuit blocks102. In one or more further embodiments, the memory circuit152A may be a read only memory (ROM). The ROM may thus contain information that indicates failure status for the circuit blocks102. The driver circuit152B may be implemented using appropriate circuitry to interface between the memory circuit152A and the gate circuits150. As noted above, the circuit blocks102are preferably tested during manufacture to determine whether they are faulty (or otherwise designated as being faulty) such information is programmed into the control circuit152(action202).

Thereafter, the system is powered up (action204) The control circuit152requires operating power to produce the control signals154, although it may take some period of time before the control signals are “valid,” e.g., at a state that properly indicates whether the associated gate circuit(s)150should or should not permit operating power VDC1to pass to the circuit blocks102. Thus, operating power is preferably provided to the control circuit152before the operating power VDC1is available to the gate circuits150(action206). At some appropriate time, the operating power VDC1is then made available to the gate circuits150(action208). The delay between application of the operating power to the control circuit152and the availability of the operating power VDC1to the gate circuits150is preferably long enough to ensure that the control signals154are valid.

In accordance with one or more embodiments of the present invention the delay between application of the operating power to the control circuit152and the availability of the operating power VDC1to the gate circuits150may be achieved using the master gate circuit140. The master gate circuit140is preferably operable to produce the operating power VDC1on node112in response to the operating power VDC input thereto by gating the power VDC in accordance with a delay. Those skilled in the art will appreciate the numerous ways in which such gating may be implemented, such as by way of controlled transistor switching, RC timing circuits, etc. Preferably, the delay in gating the power VDC to node112is predetermined and/or fixed.

In accordance with one or more further embodiments of the present invention the delay between application of the operating power to the control circuit152and the availability of the operating power VDC1to the gate circuits150may be achieved using a first power supply (without master gate circuit140) operable to produce the operating power VDC1for the gate circuits150, and a second power supply operable to produce the operating power VDC2for the control circuit152. The second power supply may be operable to provide the operating power VDC2to the control circuit152before the first power supply makes the power VDC1available to the gate circuits150.

Once the control signals154are stable and valid, the gate circuits150may then selectively supply operating power VDC1the circuit blocks102in response to one or more respective control signals154output from the control circuit152(action210).

It is advantageous for the control signals154to stabilize before the gate circuits150receive operating power VDC1on node112because, otherwise, a defective circuit block102might receive power for some period of time before the control signals154stabilize. Such a situation is undesirable since power is thus wasted and interference with other processors may occur. For example, if the circuit blocks102are processors, then the processors will attempt various initialization routines at power up. Excessive electromagnetic interference or other types of noise caused by defective processors improperly receiving power might disrupt the initialization. At best the affected processor might be initialized through a repeated power up sequence; at worst, the processor might never initialize.

With reference toFIG. 5, the gate circuit150is preferably operable to produce the operating power VDC1on the respective power terminals110of the circuit blocks102by gating the power VDC1on terminal112in accordance with the control signals154. With reference toFIG. 6, those skilled in the art will appreciate the numerous ways in which such gating may be implemented, such as by way of controlled transistor switching156.

With reference toFIG. 5, the gate circuit150is also preferably operable to use the control signaling154to gate clock signal(s) to the disabled circuit blocks102. For example, the gate circuit150(FIG. 6) may include a logic gate158(such as an AND gate or the like) to enable/disable the clock signal CLK to the circuit block102. The gate circuits150nare also preferably operable to use the control signaling154to gate one or more outputs from the disabled circuit blocks102. For example, the gate circuit150(FIG. 6) may include a plurality of logic gates162(such as AND gates or the like) to enable/disable the output signals from the disabled circuit block102. Still further, the gate circuits150are preferably operable to use the control signaling154to gate one or more inputs to the disabled circuit blocks102. For example, the gate circuit150(FIG. 6) may include a plurality of logic gates160(such as AND gates or the like) to enable/disable the input signals to the disabled circuit block102.

The circuit blocks102are preferably implemented as an integrated circuit (illustrated by way of dashed line inFIG. 2) and are each powered by way of a respective power grid (not shown) that receives the operating power VDC1from the associated gate circuit150. Each circuit block102preferably powered by way of voltage potential between Vss and Vdd terminals (not shown) Usually, Vdd will be at ground potential (0V), although one or more embodiments of the present invention may provide for a negative potential for Vdd. In this regard, it is understood that the term “ground” is a name that may be associated with a node in the system to which reference will be made. Thus, “ground” may be OV or may represent some other reference potential.

It is noted that the circuit blocks102may be integrated separately from the gate circuits150,140and the control circuit152. In this situation, the integrated circuit would preferably include a plurality of separate power pins (or terminals)110that may be connected to the respective gate circuits150. Alternatively, the circuit blocks102may be integrated with the gate circuits150, in which case only one power pin (terminal)112need be provided to the circuit.

FIG. 7is a block diagram of a multi-processing system100A that may be adapted to implement the features discussed herein and one or more further embodiments of the present invention. The system100A includes a plurality of processors102A-D, associated local memories104A-D, and a shared memory106interconnected by way of a bus108. The shared memory106may also be referred to herein as a main memory or system memory. The methods and/or circuit functionality discussed above may also be applied to the circuit configuration ofFIG. 7, where the processors102are the circuit blocks discussed above.

Although four processors102are illustrated by way of example, any number may be utilized without departing from the spirit and scope of the present invention. Each of the processors102may be of similar construction or of differing construction. The local memories104are preferably located on the same chip (same semiconductor substrate) as their respective processors102; however, the local memories104are preferably not traditional hardware cache memories in that there are no on-chip or off-chip hardware cache circuits, cache registers, cache memory controllers, etc. to implement a hardware cache memory function.

The processors102preferably provide data access requests to copy data (which may include program data) from the system memory106over the bus108into their respective local memories104for program execution and data manipulation. The mechanism for facilitating data access is preferably implemented utilizing a direct memory access controller (DMAC), not shown. The DMAC of each processor is preferably of substantially the same capabilities as discussed hereinabove with respect to other features of the invention.

The system memory106is preferably a dynamic random access memory (DRAM) coupled to the processors102through a high bandwidth memory connection (not shown). Although the system memory106is preferably a DRAM, the memory106may be implemented using other means, e.g., a static random access memory (SRAM), a magnetic random access memory (MRAM), an optical memory, a holographic memory, etc.

Each processor102is preferably implemented using a processing pipeline, in which logic instructions are processed in a pipelined fashion. Although the pipeline may be divided into any number of stages at which instructions are processed, the pipeline generally comprises fetching one or more instructions, decoding the instructions, checking for dependencies among the instructions, issuing the instructions, and executing the instructions. In this regard, the processors102may include an instruction buffer, instruction decode circuitry, dependency check circuitry, instruction issue circuitry, and execution stages.

In one or more embodiments, the processors102and the local memories104may be disposed on a common semiconductor substrate. In one or more further embodiments, the shared memory106may also be disposed on the common semiconductor substrate or it may be separately disposed.

In one or more alternative embodiments, one or more of the processors102may operate as a main processor operatively coupled to the other processors102and capable of being coupled to the shared memory106over the bus108. The main processor may schedule and orchestrate the processing of data by the other processors102. Unlike the other processors102, however, the main processor may be coupled to a hardware cache memory, which is operable cache data obtained from at least one of the shared memory106and one or more of the local memories104of the processors102. The main processor may provide data access requests to copy data (which may include program data) from the system memory106over the bus108into the cache memory for program execution and data manipulation utilizing any of the known techniques, such as DMA techniques.

A description of a preferred computer architecture for a multi-processor system will now be provided that is suitable for carrying out one or more of the features discussed herein. In accordance with one or more embodiments, the multi-processor system may be implemented as a single-chip solution operable for stand-alone and/or distributed processing of media-rich applications, such as game systems, home terminals, PC systems, server systems and workstations. In some applications, such as game systems and home terminals, real-time computing may be a necessity. For example, in a real-time, distributed gaming application, one or more of networking image decompression, 3D computer graphics, audio generation, network communications, physical simulation, and artificial intelligence processes have to be executed quickly enough to provide the user with the illusion of a real-time experience. Thus, each processor in the multi-processor system must complete tasks in a short and predictable time.

To this end, and in accordance with this computer architecture, all processors of a multi-processing computer system are constructed from a common computing module (or cell). This common computing module has a consistent structure and preferably employs the same instruction set architecture. The multi-processing computer system can be formed of one or more clients, servers, PCs, mobile computers, game machines, PDAs, set top boxes, appliances, digital televisions and other devices using computer processors.

A plurality of the computer systems may also be members of a network if desired. The consistent modular structure enables efficient, high speed processing of applications and data by the multi-processing computer system, and if a network is employed, the rapid transmission of applications and data over the network. This structure also simplifies the building of members of the network of various sizes and processing power and the preparation of applications for processing by these members.

With reference toFIG. 8, the basic processing module is a processor element (PE)500. The PE500comprises an I/O interface502, a processing unit (PU)504, and a plurality of sub-processing units508, namely, sub-processing unit508A, sub-processing unit508B, sub-processing unit508C, and sub-processing unit508D. A local (or internal) PE bus512transmits data and applications among the PU504, the sub-processing units508, and a memory interface511. The local PE bus512can have, e.g., a conventional architecture or can be implemented as a packet-switched network. If implemented as a packet switch network, while requiring more hardware, increases the available bandwidth.

The PE500can be constructed using various methods for implementing digital logic. The PE500preferably is constructed, however, as a single integrated circuit employing a complementary metal oxide semiconductor (CMOS) on a silicon substrate. Alternative materials for substrates include gallium arsinide, gallium aluminum arsinide and other so-called III-B compounds employing a wide variety of dopants. The PE500also may be implemented using superconducting material, e.g., rapid single-flux-quantum (RSFQ) logic.

The PE500is closely associated with a shared (main) memory514through a high bandwidth memory connection516. Although the memory514preferably is a dynamic random access memory (DRAM), the memory514could be implemented using other means, e.g., as a static random access memory (SRAM), a magnetic random access memory (MRAM), an optical memory, a holographic memory, etc.

The PU504and the sub-processing units508are preferably each coupled to a memory flow controller (MFC) including direct memory access DMA functionality, which in combination with the memory interface511, facilitate the transfer of data between the DRAM514and the sub-processing units508and the PU504of the PE500. It is noted that the DMAC and/or the memory interface511may be integrally or separately disposed with respect to the sub-processing units508and the PU504. Indeed, the DMAC function and/or the memory interface511function may be integral with one or more (preferably all) of the sub-processing units508and the PU504. It is also noted that the DRAM514may be integrally or separately disposed with respect to the PE500. For example, the DRAM514may be disposed off-chip as is implied by the illustration shown or the DRAM514may be disposed on-chip in an integrated fashion.

The PU504can be, e.g., a standard processor capable of stand-alone processing of data and applications. In operation, the PU504preferably schedules and orchestrates the processing of data and applications by the sub-processing units. The sub-processing units preferably are single instruction, multiple data (SIMD) processors. Under the control of the PU504, the sub-processing units perform the processing of these data and applications in a parallel and independent manner. The PU504is preferably implemented using a PowerPC core, which is a microprocessor architecture that employs reduced instruction-set computing (RISC) technique. RISC performs more complex instructions using combinations of simple instructions. Thus, the timing for the processor may be based on simpler and faster operations, enabling the microprocessor to perform more instructions for a given clock speed.

It is noted that the PU504may be implemented by one of the sub-processing units508taking on the role of a main processing unit that schedules and orchestrates the processing of data and applications by the sub-processing units508. Further, there may be more than one PU implemented within the processor element500.

In accordance with this modular structure, the number of PEs500employed by a particular computer system is based upon the processing power required by that system. For example, a server may employ four PEs500, a workstation may employ two PEs500and a PDA may employ one PE500. The number of sub-processing units of a PE500assigned to processing a particular software cell depends upon the complexity and magnitude of the programs and data within the cell.

FIG. 9illustrates the preferred structure and function of a sub-processing unit (SPU)508. The SPU508architecture preferably fills a void between general-purpose processors (which are designed to achieve high average performance on a broad set of applications) and special-purpose processors (which are designed to achieve high performance on a single application). The SPU508is designed to achieve high performance on game applications, media applications, broadband systems, etc., and to provide a high degree of control to programmers of real-time applications. Some capabilities of the SPU508include graphics geometry pipelines, surface subdivision, Fast Fourier Transforms, image processing keywords, stream processing, MPEG encoding/decoding, encryption, decryption, device driver extensions, modeling, game physics, content creation, and audio synthesis and processing.

The sub-processing unit508includes two basic functional units, namely an SPU core510A and a memory flow controller (MFC)510B. The SPU core510A performs program execution, data manipulation, etc., while the MFC510B performs functions related to data transfers between the SPU core510A and the DRAM514of the system.

The SPU core510A includes a local memory550, an instruction unit (IU)552, registers554, one ore more floating point execution stages556and one or more fixed point execution stages558. The local memory550is preferably implemented using single-ported random access memory, such as an SRAM. Whereas most processors reduce latency to memory by employing caches, the SPU core510A implements the relatively small local memory550rather than a cache. Indeed, in order to provide consistent and predictable memory access latency for programmers of real-time applications (and other applications as mentioned herein) a cache memory architecture within the SPU508A is not preferred. The cache hit/miss characteristics of a cache memory results in volatile memory access times, varying from a few cycles to a few hundred cycles. Such volatility undercuts the access timing predictability that is desirable in, for example, real-time application programming. Latency hiding may be achieved in the local memory SRAM550by overlapping DMA transfers with data computation. This provides a high degree of control for the programming of real-time applications. As the latency and instruction overhead associated with DMA transfers exceeds that of the latency of servicing a cache miss, the SRAM local memory approach achieves an advantage when the DMA transfer size is sufficiently large and is sufficiently predictable (e.g., a DMA command can be issued before data is needed).

A program running on a given one of the sub-processing units508references the associated local memory550using a local address, however, each location of the local memory550is also assigned a real address (RA) within the overall system's memory map. This allows Privilege Software to map a local memory550into the Effective Address (EA) of a process to facilitate DMA transfers between one local memory550and another local memory550. The PU504can also directly access the local memory550using an effective address. In a preferred embodiment, the local memory550contains556kilobytes of storage, and the capacity of registers552is 128×128 bits.

The SPU core504A is preferably implemented using a processing pipeline, in which logic instructions are processed in a pipelined fashion. Although the pipeline may be divided into any number of stages at which instructions are processed, the pipeline generally comprises fetching one or more instructions, decoding the instructions, checking for dependencies among the instructions, issuing the instructions, and executing the instructions. In this regard, the IU552includes an instruction buffer, instruction decode circuitry, dependency check circuitry, and instruction issue circuitry.

The instruction buffer preferably includes a plurality of registers that are coupled to the local memory550and operable to temporarily store instructions as they are fetched. The instruction buffer preferably operates such that all the instructions leave the registers as a group, i.e., substantially simultaneously. Although the instruction buffer may be of any size, it is preferred that it is of a size not larger than about two or three registers.

In general, the decode circuitry breaks down the instructions and generates logical micro-operations that perform the function of the corresponding instruction. For example, the logical micro-operations may specify arithmetic and logical operations, load and store operations to the local memory550, register source operands and/or immediate data operands. The decode circuitry may also indicate which resources the instruction uses, such as target register addresses, structural resources, function units and/or busses. The decode circuitry may also supply information indicating the instruction pipeline stages in which the resources are required. The instruction decode circuitry is preferably operable to substantially simultaneously decode a number of instructions equal to the number of registers of the instruction buffer.

The dependency check circuitry includes digital logic that performs testing to determine whether the operands of given instruction are dependent on the operands of other instructions in the pipeline. If so, then the given instruction should not be executed until such other operands are updated (e.g., by permitting the other instructions to complete execution). It is preferred that the dependency check circuitry determines dependencies of multiple instructions dispatched from the decoder circuitry112simultaneously.

The instruction issue circuitry is operable to issue the instructions to the floating point execution stages556and/or the fixed point execution stages558.

The registers554are preferably implemented as a relatively large unified register file, such as a 128-entry register file. This allows for deeply pipelined high-frequency implementations without requiring register renaming to avoid register starvation. Renaming hardware typically consumes a significant fraction of the area and power in a processing system. Consequently, advantageous operation may be achieved when latencies are covered by software loop unrolling or other interleaving techniques.

Preferably, the SPU core510A is of a superscalar architecture, such that more than one instruction is issued per clock cycle. The SPU core510A preferably operates as a superscalar to a degree corresponding to the number of simultaneous instruction dispatches from the instruction buffer, such as between 2 and 3 (meaning that two or three instructions are issued each clock cycle). Depending upon the required processing power, a greater or lesser number of floating point execution stages556and fixed point execution stages558may be employed. In a preferred embodiment, the floating point execution stages556operate at a speed of32billion floating point operations per second (32GFLOPS), and the fixed point execution stages558operate at a speed of32billion operations per second (32GOPS).

The MFC510B preferably includes a bus interface unit (BIU)564, a memory management unit (MMU)562, and a direct memory access controller (DMAC)560. With the exception of the DMAC560, the MFC510B preferably runs at half frequency (half speed) as compared with the SPU core510A and the bus512to meet low power dissipation design objectives. The MFC510B is operable to handle data and instructions coming into the SPU508from the bus512, provides address translation for the DMAC, and snoop-operations for data coherency. The BIU564provides an interface between the bus512and the MMU562and DMAC560. Thus, the SPU508(including the SPU core510A and the MFC510B) and the DMAC560are connected physically and/or logically to the bus512.

The MMU562is preferably operable to translate effective addresses (taken from DMA commands) into real addresses for memory access. For example, the MMU562may translate the higher order bits of the effective address into real address bits. The lower-order address bits, however, are preferably untranslatable and are considered both logical and physical for use to form the real address and request access to memory. In one or more embodiments, the MMU562may be implemented based on a 64-bit memory management model, and may provide 264bytes of effective address space with 4K-, 64K-, 1M-, and 16M-byte page sizes and 256 MB segment sizes. Preferably, the MMU562is operable to support up to 265bytes of virtual memory, and 242bytes (4 TeraBytes) of physical memory for DMA commands. The hardware of the MMU562may include an 8-entry, fully associative SLB, a 256-entry, 4 way set associative TLB, and a 4×4 Replacement Management Table (RMT) for the TLB-used for hardware TLB miss handling.

The DMAC560is preferably operable to manage DMA commands from the SPU core510A and one or more other devices such as the PU504and/or the other SPUs. There may be three categories of DMA commands: Put commands, which operate to move data from the local memory550to the shared memory514; Get commands, which operate to move data into the local memory550from the shared memory514; and Storage Control commands, which include SLI commands and synchronization commands. The synchronization commands may include atomic commands, send signal commands, and dedicated barrier commands. In response to DMA commands, the MMU562translates the effective address into a real address and the real address is forwarded to the BIU564.

The SPU core510A preferably uses a channel interface and data interface to communicate (send DMA commands, status, etc.) with an interface within the DMAC560. The SPU core510A dispatches DMA commands through the channel interface to a DMA queue in the DMAC560. Once a DMA command is in the DMA queue, it is handled by issue and completion logic within the DMAC560. When all bus transactions for a DMA command are finished, a completion signal is sent back to the SPU core510A over the channel interface.

FIG. 10illustrates the preferred structure and function of the PU504. The PU504includes two basic functional units, the PU core504A and the memory flow controller (MFC)504B. The PU core504A performs program execution, data manipulation, multi-processor management functions, etc., while the MFC504B performs functions related to data transfers between the PU core504A and the memory space of the system100.

The PU core504A may include an L1cache570, an instruction unit572, registers574, one or more floating point execution stages576and one or more fixed point execution stages578. The L1cache provides data caching functionality for data received from the shared memory106, the processors102, or other portions of the memory space through the MFC504B. As the PU core504A is preferably implemented as a superpipeline, the instruction unit572is preferably implemented as an instruction pipeline with many stages, including fetching, decoding, dependency checking, issuing, etc. The PU core504A is also preferably of a superscalar configuration, whereby more than one instruction is issued from the instruction unit572per clock cycle. To achieve a high processing power, the floating point execution stages576and the fixed point execution stages578include a plurality of stages in a pipeline configuration. Depending upon the required processing power, a greater or lesser number of floating point execution stages576and fixed point execution stages578may be employed.

The MFC504B includes a bus interface unit (BIU)580, an L2cache memory, a non-cachable unit (NCU)584, a core interface unit (CIU)586, and a memory management unit (MMU)588. Most of the MFC504B runs at half frequency (half speed) as compared with the PU core504A and the bus108to meet low power dissipation design objectives.

The BIU580provides an interface between the bus108and the L2cache582and NCU584logic blocks. To this end, the BIU580may act as a Master as well as a Slave device on the bus108in order to perform fully coherent memory operations. As a Master device it may source load/store requests to the bus108for service on behalf of the L2cache582and the NCU584. The BIU580may also implement a flow control mechanism for commands which limits the total number of commands that can be sent to the bus108. The data operations on the bus108may be designed to take eight beats and, therefore, the BIU580is preferably designed around128byte cache-lines and the coherency and synchronization granularity is 128KB.

The L2cache memory582(and supporting hardware logic) is preferably designed to cache 512 KB of data. For example, the L2cache582may handle cacheable loads/stores, data pre-fetches, instruction fetches, instruction pre-fetches, cache operations, and barrier operations. The L2cache582is preferably an 8-way set associative system. The L2cache582may include six reload queues matching six (6) castout queues (e.g., six RC machines), and eight (64-byte wide) store queues. The L2cache582may operate to provide a backup copy of some or all of the data in the L1cache570. Advantageously, this is useful in restoring state(s) when processing nodes are hot-swapped. This configuration also permits the L1cache570to operate more quickly with fewer ports, and permits faster cache-to-cache transfers (because the requests may stop at the L2cache582). This configuration also provides a mechanism for passing cache coherency management to the L2cache memory582.

The NCU584interfaces with the CIU586, the L2cache memory582, and the BIU580and generally functions as a queueing/buffering circuit for non-cacheable operations between the PU core504A and the memory system. The NCU584preferably handles all communications with the PU core504A that are not handled by the L2cache582, such as cache-inhibited load/stores, barrier operations, and cache coherency operations. The NCU584is preferably run at half speed to meet the aforementioned power dissipation objectives.

The CIU586is disposed on the boundary of the MFC504B and the PU core504A and acts as a routing, arbitration, and flow control point for requests coming from the execution stages576,578, the instruction unit572, and the MMU unit588and going to the L2cache582and the NCU584. The PU core504A and the MMU588preferably run at full speed, while the L2cache582and the NCU584are operable for a 2:1 speed ratio. Thus, a frequency boundary exists in the CIU586and one of its functions is to properly handle the frequency crossing as it forwards requests and reloads data between the two frequency domains.

The CIU586is comprised of three functional blocks: a load unit, a store unit, and reload unit. In addition, a data pre-fetch function is performed by the CIU586and is preferably a functional part of the load unit. The CIU586is preferably operable to: (i) accept load and store requests from the PU core504A and the MMU588; (ii) convert the requests from full speed clock frequency to half speed (a 2:1 clock frequency conversion); (iii) route cachable requests to the L2cache582, and route non-cachable requests to the NCU584; (iv) arbitrate fairly between the requests to the L2cache582and the NCU584; (v) provide flow control over the dispatch to the L2cache582and the NCU584so that the requests are received in a target window and overflow is avoided; (vi) accept load return data and route it to the execution stages576,578, the instruction unit572, or the MMU588; (vii) pass snoop requests to the execution stages576,578, the instruction unit572, or the MMU588; and (viii) convert load return data and snoop traffic from half speed to full speed.

The MMU588preferably provides address translation for the PU core540A, such as by way of a second level address translation facility. A first level of translation is preferably provided in the PU core504A by separate instruction and data ERAT (effective to real address translation) arrays that may be much smaller and faster than the MMU588.

In a preferred embodiment, the PU504operates at 4 -6 GHz,10F04, with a 64-bit implementation. The registers are preferably 64 bits long (although one or more special purpose registers may be smaller) and effective addresses are 64 bits long. The instruction unit570, registers572and execution stages574and576are preferably implemented using PowerPC technology to achieve the (RISC) computing technique.

Additional details regarding the modular structure of this computer system may be found in U.S. Pat. No. 6,526,491, the entire disclosure of which is hereby incorporated by reference.

In accordance with at least one further aspect of the present invention, the methods and apparatus described above may be achieved utilizing suitable hardware, such as that illustrated in the figures. Such hardware may be implemented utilizing any of the known technologies, such as standard digital circuitry, any of the known processors that are operable to execute software and/or firmware programs, one or more programmable digital devices or systems, such as programmable read only memories (PROMs), programmable array logic devices (PALs), etc. Furthermore, although the apparatus illustrated in the figures are shown as being partitioned into certain functional blocks, such blocks may be implemented by way of separate circuitry and/or combined into one or more functional units. Still further, the various aspects of the invention may be implemented by way of software and/or firmware program(s) that may be stored on suitable storage medium or media (such as floppy disk(s), memory chip(s), etc.) for transportability and/or distribution.