TSV check circuit with replica path

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

BACKGROUND

A semiconductor chip used in a memory device such as an HBM (High Bandwidth Memory) includes a number of TSVs (Through Silicon Vias) each provided to penetrate through a semiconductor substrate in some cases. A TSV provided in each semiconductor chip is connected to a TSV provided at the same plane position in another semiconductor chip via a microbump, so that a signal path that penetrates through a plurality of semiconductor substrates is formed. If a certain TSV has a conduction failure or a connecting portion between two TSVs has a connection failure, the corresponding signal path becomes defective and cannot be used actually. In this case, a spare signal path is used in place of the signal path with the failure, so that the failure is recovered. Inspection of each signal path and replacement with a spare signal path may be performed not only in a manufacturing stage but also in actual use, i.e., an initialization period after a power is turned on. In a case where inspection of signal paths is performed in the initialization period, an inspection time that can be assigned to each signal path is very short. Therefore, it is not easy to perform correct inspection for all the signal paths.

DETAILED DESCRIPTION

Various embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structural, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

A semiconductor device shown inFIG. 1is an HBM having a configuration in which eight memory core chips20to27are stacked on an interface chip10. However, the semiconductor device to which the present invention is applicable is not limited to an HBM. The memory core chips20to27are each a semiconductor chip in which a memory core including a memory cell array is integrated. The interface chip10is a semiconductor chip that controls the memory core chips20to27. The interface chip10and the memory core chips20to26each have a plurality of TSVs30that are provided to penetrate through a semiconductor substrate. All the interface chip10and the memory core chips20to27are stacked in a face-down manner, that is, in such a manner that a main surface with transistors and a wiring pattern (both not shown) formed thereon faces down. Therefore, no TSV30is required in the memory core chip27located in an uppermost layer. However, the memory core chip27located in the uppermost layer may have the TSV30. Almost all the TSVs30provided in the memory core chips20to26are connected to front-surface TSV pads31A located at the same plane positions, respectively. Meanwhile, most of the TSVs30provided in the interface chip10and most of the front-surface TSV pads31A provided on the interface chip10are present at different plane positions from each other. Among the TSVs30provided in the interface chip10and the memory core chips20to26, the TSVs30located at the same plane position are connected to each other in cascade connection via the front-surface TSV pad31A, a TSV bump31B, and a rear-surface TSV pad31C. In this manner, a plurality of signal paths32are formed. A command and write data output from the interface chip10are supplied to the memory core chips20to27via the signal paths32. Read data output from the memory core chips20to27is supplied to the interface chip10via the signal paths32. External terminals33are provided on the interface chip10, via which signal transmission and reception to/from an external circuit are performed.

As shown inFIG. 2, the TSVs30are arranged in a matrix form in each of the interface chip10and the memory core chips20to26. A selection circuit34is assigned to each TSV30. The selection circuits34are used in inspection of the signal paths32performed in a manufacturing stage and an initialization period after a power is turned on. As shown inFIG. 2, to the TSVs30arranged in an x-direction, a corresponding one of selection-signal lines Y0, Y1, Y2, Y3, . . . is assigned. To the TSVs30arranged in a y-direction, a corresponding one of selection-signal lines X0, X1, X2, X3, . . . is assigned. The selection-signal lines Y0, Y1, Y2, Y3. . . supply selection signals Ysel0, Ysel1, Ysel2, Ysel3, . . . to the corresponding selection circuits34, respectively. The selection-signal lines X0, X1, X2, X3, . . . supply selection signals Xsel0, Xsel1, Xsel2, Xsel3, . . . to the corresponding selection circuits34, respectively. A selection circuit12activates any one of the selection signals Ysel0, Ysel1, Ysel2, Ysel3, . . . and deactivates all the remaining signals. A selection circuit14activates any one of the selection signals Xsel0, Xsel1, Xsel2, Xsel3, . . . and deactivates all the remaining signals. In this manner, any one of the selection circuits34is activated, so that one of the TSVs30corresponding thereto is selected.

Each selection circuit34included in each of the memory chips20to27includes a P-channel MOS transistor41and a NAND gate circuit42that controls the transistor41, as shown inFIG. 3. The NAND gate circuit42receives a corresponding one of the selection signals Xsel0, Xsel1, Xsel2, Xsel3, . . . , a corresponding one of the selection signals Ysel0, Ysel1, Ysel2, Ysel3. . . , and a selection signal SliceEn that selects one of the memory core chips20to27in which that NAND gate circuit42is included, and activates a selection signal XYselF to a low level when all the received signals are at an active level (a high level). In each of the memory core chips20to27, a P-channel MOS transistor43and the P-channel MOS transistor41are connected in series between a power supply VDD and the TSV30. A test signal TESTF is supplied to a gate electrode of the transistor43. Therefore, when both the test signal TESTF and the selection signal XYselF are activated to a low level, the TSV30is connected to the power supply VDD. The power supply VDD is a high-potential side power supply for example. In this case, when both the test signal TESTF and the selection signal XYselF are activated, the signal path32is charged via the TSV30.

The selection circuit34included in the interface chip10has the same circuit configuration as the selection circuit34included in the memory core chips20to27, as shown inFIG. 4. In the interface chip10, the transistor41and an N-channel MOS transistor47are connected in series between the TSV30and a power supply VSS. A test clock signal CLK is supplied to a gate electrode of the transistor47. Therefore, when the test clock signal CLK is activated to a high level and the selection signal XYselF is activated to a low level, the TSV30is connected to the power supply VSS. The power supply VSS is a low-potential side power supply, for example. In this case, when both the test clock signal CLK and the selection signal XYselF are activated, the signal path32is discharged via the TSV30.

As shown inFIGS. 3 and 4, an output buffer45and an input receiver46are connected in parallel between an internal circuit44and the TSV30included in each of the interface chip10and the memory core chips20to27. Therefore, data, a command, and the like output from the internal circuit44are supplied to the signal path32via the output buffer45and the TSV30. Further, data, a command, and the like supplied from the signal path32are input to the internal circuit44via the TSV30and the input receiver46.

As shown inFIG. 5, the plural signal paths32include a replica path32R. The replica path32R is used as a reference in inspection of the other signal paths32and has the same configuration as the signal paths32except that a transistor48for receiving an enable signal EnF is used in place of the transistor41and a dummy resistor Rd is inserted in series. The enable signal EnF is always activated during a test period. A parasitic capacitance C1added to each signal path32and a parasitic capacitance C2added to the replica path32R are designed to have substantially the same values as each other. Each signal path32is connected to a node N1via the transistor41provided on the interface chip10, and the replica path32R is connected to a node N2via the transistor48provided on the interface chip10. The interface chip10includes a comparator circuit49that compares a level at the node N1and a level at the node N2with each other in response to a comparison signal COMP.

An operation of the circuit shown inFIG. 5is described referring toFIGS. 6 and 7.FIG. 6shows a waveform in a case where there is no failure in each signal path32, andFIG. 7shows a waveform in a case where there is a failure in a part of the signal paths32. First, in a state where any of the selection signals Xsel0, Xsel1, Xsel2, Xsel3, . . . (the selection signal Xsel0in the example shown inFIGS. 6 and 7) is activated to a high level, the selection signals Ysel0, Ysel1, Ysel2, Ysel3, . . . are activated to a high level sequentially. Therefore, the TSVs30arranged in a matrix form as shown inFIG. 2are selected sequentially and, via the selected TSV30, a corresponding one of the signals paths32is charged. It suffices that charging of the signal path32is performed in any one of the memory core chips20to27, and charging in the other memory core chips is not required. It is preferable to perform charging of each signal path32in the memory core chip27in the uppermost layer. By charging each signal path32in the memory core chip27in the uppermost layer, all the TSVs30included in that signal path32can be tested. Meanwhile, by charging each signal path32in any one of the memory core chips20to26that are not in the uppermost layer, it is possible to specify which one of the memory core chips20to26includes a defective TSV30in a case where there is a failure in the signal path32. In a case of charging each signal path32in the memory core chip27in the uppermost layer, it suffices to activate the selection signal SliceEn corresponding to the memory core chip27in the uppermost layer to a high level and to deactivate the selection signals SliceEn corresponding to the other memory core chips20to26to a low level. Also for the interface chip10, the corresponding selection signal SliceEn is activated to a high level. The replica path32R is also charged by activating the enable signals EnF for the memory core chip27in the uppermost layer and the interface chip10.

As shown inFIGS. 6 and 7, one cycle of the test clock signal CLK is coincident with an activation period of the selection signals Ysel0, Ysel1, Ysel2, Ysel3, . . . . Therefore, during a first half of a period during which one of the signal paths32is selected, the transistor47is on, and therefore the selected signal path32and the replica path32R are discharged and the nodes N1and N2are placed at a VSS level. Meanwhile, during a latter half of the period during which one of the signal paths32is selected, the transistor47is off, and therefore discharging of the selected signal path32and the replica path32R stops. When discharging of the selected signal path32and the replica path32R stops, the selected signal path32and the replica path32R are charged via the transistors41and48, respectively, so that the levels at the nodes N1and N2rise. At this time, a rate of rise of the level at the node N1is determined by the resistance value and the parasitic capacitance C1of the signal path32. Further, a rate of rise of the level at the node N2is determined by the resistance value and the parasitic capacitance C2of the replica path32R. Although the parasitic capacitance C2of the replica path32R is substantially the same as the parasitic capacitance C1of the signal path32as described above, a charging rate of the replica path32R is lower than that of the signal path32unless the signal path32has a failure, because the dummy resistor Rd is inserted in series to the replica path32R.FIG. 6shows a waveform in a case where each signal path32does not have a failure, and the level at the node N1rises faster than the level at the node N2. The comparison signal COMP is activated at a timing after the test clock signal CLK is changed from a high level to a low level and before the test clock signal CLK is changed to a high level again. When the comparison signal COMP is activated, the comparator circuit49performs an operation of comparing the level at the node N1and the level at the node N2with each other, and places its output signal OUT at a high level when the level at the node N1is higher. This means that the signal path32has no failure, and a fail signal FAIL is kept inactive.

Meanwhile,FIG. 7shows a waveform in a case where the signal path32corresponding to the selection signals Xsel0and Ysel2has a failure. When there is a failure in the signal path32, its resistance value is high and a charging rate of the signal path32is lowered. As a failure in the signal path32, cases can be considered where the resistance of the TSV30itself becomes high and where the resistance of the signal path32becomes high because of a failure in a connecting portion via the TSV bump31B. If the resistance value of the signal path32is higher than the resistance value of the replica path32R, the level at the node N1rises more slowly than the level at the node N2. In this case, when the comparison signal COMP is activated, the comparator circuit49places its output signal OUT at a low level. This means that the signal path32has a failure, and the fail signal FAIL is activated. When the fail signal FAIL is activated, the corresponding signal path32is disabled and is replaced with a spare signal path.

As a method of inspecting the signal paths32, a method can also be considered in which the replica path32R is not used as a reference, but a constant reference voltage is used. That is, a method is considered which connects one of input terminals of the comparator circuit49to the node N1and the constant reference voltage is applied to the other input terminal of the comparator circuit49. In this method, however, a result of determination of pass or fail may be changed by the frequency of the test clock signal CLK. For example, in a case where the actual frequency of the test clock signal CLK is higher than a designed value, a charging time of the signal path32is shorter than expected, and therefore the signal path32that is not defective may be determined as being defective. To the contrary, in a case where the actual frequency of the test clock signal CLK is lower than the designed value, the charging time of the signal path32is longer than expected, and therefore the signal path32that is defective is determined as being non-defective. Furthermore, an off-leak current from the output buffer45also flows into the signal path32. Therefore, when the charging time of the signal path32becomes longer than expected, the risk of determining the defective signal path32as being not defective is increased, and even the signal path32that is completely disconnected may be determined as being non-defective. To the contrary, a semiconductor device according to the present embodiment uses the replica path32R as a reference. Therefore, even if the actual frequency of the test clock signal CLK is different from that of a designed value, this difference affects the signal path32and the replica path32R evenly. Further, the off-leak current from the output buffer45also affects the signal path32and the replica path32R evenly. Accordingly, correct inspection can be performed for each signal path32. Further, because correct inspection can be performed even if the frequency of the test clock signal CLK is designed to be higher, it is possible to complete inspection for a number of signal paths32with sufficient margin within an initialization period after a power is turned on, even in a case where the inspection is performed in the initialization period.

Further, a plurality of dummy resistors Rd0to Rd2connected in parallel may be inserted into the replica path32R, as shown inFIG. 8. By further inserting transistors50to52in series to the respective dummy resistors Rd0to Rd2and turning on one of the transistors50to52or two or more of them by using one, or two or more of selection signals S0to S2, it is possible to change the resistance value of the replica path32R. Therefore, it is possible to switch a resistance value in which the signal path32is determined as being defective by the selection signals S0to S2. In this case, it is preferable that the resistance values of the dummy resistors Rd0to Rd2are different from one another.

Furthermore, as shown inFIG. 9, two TSVs30may be used to configure the replica path32R in each of the memory core chips20to26and the interface chip10, while the two TSVs30are connected in parallel. With this configuration, even in a case where there is a failure in a part of the TSVs30that configure the replica path32R, inspection of the signal path32can be performed correctly. In this case, the resistance value of the replica path32R is slightly lowered because of parallel connection of the two TSVs30. However, the total resistance value of eight TSVs30included in the replica path32R is about 1Ω and is sufficiently low as compared with an on-resistance of the transistor48. Therefore, lowering of the resistance value of the replica path32R has almost no influence on the inspection. Further, three or more of the TSVs30may be connected in parallel.

Further, a dummy capacitance Cd may be connected to the replica path32R instead of inserting the dummy resistor Rd into the replica path32R, as shown inFIG. 10. Also in this case, an operation that is basically the same as that of the circuit shown inFIG. 5can be performed because a time constant of the replica path32R is larger than a time constant of the signal path32.

Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the inventions extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the inventions and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this invention will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the inventions. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying mode of the disclosed invention. Thus, it is intended that the scope of at least some of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above.