SOI compact contactless flash memory cell

A compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Floating gates are then formed by patterning the first polysilicon layer. Source/drain buried bitlines for the flash memory array are formed. A first BPSG (borophosphosilicate glass) layer is deposited and then reflown and etched back. An oxide-nitride-oxide layer is formed. A second polysilicon layer is deposited with in-situ dope. A WSi.sub.x layer then forms. Stacked gates for the flash array are formed by patterning into the formed oxide-nitride-oxide, second polysilicon and WSi.sub.x layers. The stacked gates are then covered with a second BPSG layer. Contact openings for the source/drain buried lines are formed. Metal lines leading into the contact openings are then formed for interconnecting the memory cells in the flash memory array with peripheral control circuits of the semiconductor EEPROM devices.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates in general to a memory cell configuration of 
high-density semiconductor electrically-erasable programmable read-only 
memory (EEPROM) devices. In particular, the present invention relates to 
compact contactless memory arrays on Silicon-On-Insulator (SOI) for flash 
EEPROM devices. More particularly, the present invention relates to the 
memory cell configuration of the compact contactless flash array on SOI 
for the flash EEPROM devices and provides for the elimination of the short 
channel effect during a hot carrier programming phase of the devices. 
2. Technical Background 
Scaling down of the physical dimensions of the memory cell configuration 
for semiconductor flash EEPROM devices is indispensable for the upcoming 
next generation of high-density non-volatile memory devices. In the effort 
conducted for the scaling down of the basic memory cell units in these 
flash EEPROM devices, several configurations have been proposed. For 
example, R. Kirisawa, S. Aritome, R. Nakauama, T. Endoh, R. Shirota and F. 
Masuoka proposed a NAND structure in their paper "A NAND structured cell 
with a new programming technology for highly reliable 5-V only flash 
EEPROM," 1990 Symposium on VLSI Technology, pp. 129-130. This NAND 
structure does need special design on source and drain regions, which 
suffer from band-to-band tunneling or even junction breakdown during 
extraction of electrons out of floating gates. This problem leads to 
unintentional damage on the thin oxide and difficulty in scaling the 
sources and drains of flash cells. 
On the other hand, B. J. Woo, T. C. Ong, A. Gazio, C. Park, G. Atwood, M. 
Holler, S. Tam and S. Lai proposed another "FACE" structure in their paper 
"A novel memory cell using flash array contactless EPROM (FACE) 
Technology," 1990 IEDM, pp. 90-94. This basic structure, although 
featuring compact cells for the high-density flash EEPROM devices, does 
suffer significant short channel effects during the hot carrier 
programming phase of use. As is well known, short channel effect in memory 
cell units will easily and likely lead to device punch-through. As device 
miniaturization technology in semiconductor fabrication advances, this 
problem represents a serious drawback in the down-scaling of the device 
memory cells. 
SUMMARY OF THE INVENTION 
It is therefore the primary object of the present invention to provide a 
compact contactless flash array on SOI for EEPROM semiconductor devices 
and its process of fabrication that has a configuration suitable for high 
memory cell density. 
It is another object of the present invention to provide a compact 
contactless flash array on SOI for EEPROM semiconductor devices and its 
process of fabrication that has a high-density memory cell array 
configuration without exhibiting short channel effect during the hot 
carrier programming phase of the device. 
It is still another object of the present invention to provide a compact 
contactless flash array on SOI for EEPROM semiconductor devices and its 
process of fabrication that allows for better programming control over 
smaller number of individual memory cells. 
To achieve the above-identified objects, the present invention provides a 
process for fabricating the disclosed device. Field oxide layers for the 
flash memory array are first grown over the surface of an SOI wafer. Gate 
oxide layers are then grown followed by first polysilicon layer 
deposition, and floating gates are then formed by patterning first 
polysilicon layer, and source/drain buried bitlines for the flash memory 
array are then formed. A first BPSG (borophosphosilicate glass) layer is 
then deposited and then reflown and etched back. An oxide-nitride-oxide 
layer is then formed, a second polysilicon layer deposited with in-situ 
dope, and a WSi.sub.x layer then forms. Stacked gates for the flash array 
are then formed by patterning into the formed WSi.sub.x, second 
polysilicon and oxide-nitride-oxide layers. The stacked gates are then 
covered with a second BPSG layer. Contact openings for the source/drain 
buried lines and n.sup.+ second polysilicon word lines are then formed. 
Metal lines leading into the contact openings are then formed for 
interconnecting the memory cells in the flash memory array with peripheral 
control circuits of the semiconductor EEPROM devices. 
To achieve the above-identified objects, the present invention further 
provides a compact contactless flash memory array for semiconductor EEPROM 
devices which includes a number of memory cell units. Each of the cell 
units has a body line, source and drain lines and a stacked gate 
constructed over a silicon-on-insulator (SOI) wafer. The source and drain 
lines are buried lines. The body line is isolated by the surrounding 
buried source/drain lines and the SiO.sub.2 layer of the SOI wafer. The 
stacked gate includes a gate oxide, a first polysilicon layer, an 
oxide-nitride-oxide configuration and a second polysilicon layer. The 
source and drain buried lines sandwiches the body line, while the stacked 
gate substantially sits directly atop the body line. The resulting flash 
memory array is free from the serious problems of short channel effect. 
Other objects, features and advantages of the present invention will become 
apparent by way of the following detailed description of the preferred but 
non-limiting embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
For the fabrication of the compact contactless flash array for the EEPROM 
device in accordance with a preferred process of the present invention, 
the starting material may be, for example, a &lt;100&gt; oriented p-type SOI 
wafer. The process is described in the depicted procedural steps outlined 
below. Note that the dimensions of the component configuration shown in 
the drawing for the description of the present invention are not drawn to 
the exact scale. The drawings are prepared to schematically exemplify the 
characteristics of the present invention, rather than showing the precise 
relative dimensions therein. 
Step 1 
Field oxide layers for the flash array are first grown over the surface of 
an SOI wafer. 
FIG. 1 is the top view of the basic SOI wafer carrying the memory array 
region 12, together with the field oxides 14, for the flash memory device 
to be fabricated. To form the field oxide layers 14 for the memory cells 
in the memory array region 12, a layer of pad oxide (not shown in FIG. 1) 
with a thickness of about 200 to 400 .ANG. is first grown over the surface 
of the SOI wafer, followed by the deposition of a nitride layer (not shown 
in FIG. 1) having a thickness of about 500 to 1,000 .ANG.. The nitride 
layer is then patterned, and the photoresist then removed. Afterwards, 
field oxide layers 14 having a thickness of about 4,000 to 5,000 .ANG. are 
grown under a temperature of about 900.degree. to 950.degree. C. utilizing 
the patterned nitride layer as the shielding mask. Then, after the 
formation of the field oxide layers 14, the nitride and pad oxide layers 
are removed. FIG. 1A shows the cross-sectional view of the SOI wafer 10 at 
the completion of this procedural step that reveals the cross section of 
the field oxide layer 14. Note that FIG. 1 shows the top view of the SOI 
wafer with the field oxide layers for the flash array being fabricated 
while FIG. 1A is the cross-sectional view taken along the 1A--1A line in 
FIG. 1. 
Step 2 
Gate oxide is grown followed by first polysilicon deposition, floating 
gates are formed by patterning the first polysilicon layer, and 
source/drain buried bitlines for the flash array are formed. 
As is seen in FIG. 2, a layer of gate oxide 16 with a thickness of about 60 
to 100 .ANG. is grown at the appropriate location within the flash array 
region 12 (FIG. 1) on the SOI wafer, after which a first polysilicon layer 
with a thickness of about 1,500 .ANG. is deposited. The first polysilicon 
layer is then patterned into the first polysilicon layers 20 in a 
photolithography procedure, followed by arsenic implantation at an energy 
level of about 25 KeV, achieving a dose of about 3E15/cm.sup.2 to form 
n.sup.+ buried bitlines 18. Then photoresist employed in the 
photolithography procedure is removed, followed by the surface reoxidation 
of the first polysilicon layers 20 at the temperature of about 900.degree. 
to 950.degree. C., resulting in a layer of oxide having a thickness of 
about 100 to 200 .ANG. for the sake of sealing. Note that the 
cross-sectional view of FIG. 2 depicts the SOI wafer configuration at a 
different location from that shown in FIG. 1A. 
Step 3 
A first BPSG (borophosphosilicate glass) layer is deposited followed by 
reflow and etch back. 
As is seen in FIG. 3A, a layer of BPSG 22 with a thickness of about 5,000 
to 8,000 .ANG. is then deposited in, for example, a low temperature oxide 
(LTO) deposition procedure in order to cover the first polysilicon layers 
20 completely. Afterwards, the BPSG layer 22 is then reflown to achieve 
planarity and etched back until the first polysilicon layers 20 expose 
themselves, as is seen in FIG. 3B. Note that the cross-sectional view of 
FIGS. 3A and 3B are taken along the same location with that of FIG. 2 
described in the previous procedural step. 
Step 4 
An oxide-nitride-oxide (ONO) layer is formed. A second polysilicon layer 
with in-situ dope is then deposited. A WSi.sub.x layer is then formed. 
As is seen in FIG. 4A, an ONO layer 24 with a thickness of about 100 to 150 
.ANG. is formed by means of, for example, first reoxidizing the first 
polysilicon layers 20 shown in FIG. 3B, followed by the deposition of a 
nitride layer having a thickness of about 50 to 100 .ANG., and then 
reoxidizing the deposited nitride subsequently to form the top oxide layer 
having a thickness of about 50 to 100 .ANG. for the ONO configuration 24. 
A second polysilicon layer having a thickness of about 1,500 .ANG. is then 
deposited atop the ONO configuration 24 with arsenic in-situ doping 
achieving a dose of about 5E15/cm.sup.2. This results in an n.sup.+ 
second polysilicon layer 26 as shown in the drawing. Then, a WSi.sub.x 
layer 28 is formed further atop in order to reduce the resistance of the 
n.sup.+ second polysilicon layer 26. Note that the cross-sectional view 
of FIG. 4A is taken along the 4A--4A line in the top view FIG. 4 for the 
device configuration on the SOI wafer up to this stage. This cross-cutting 
reveals the stacked gates 34 (FIG. 4) for the memory cells in the flash 
array region 12 (FIG. 1). 
Step 5 
Stacked gates for the flash array are formed by patterning into the 
WSi.sub.x, second polysilicon and oxide-nitride-oxide layers. 
Stacked gates are then defined by, for example, plasma etching to remove 
unwanted portions of the WSi.sub.x, second polysilicon, ONO and first 
polysilicon layers 28, 26, 24 and 20 respectively, followed by a 
reoxidation procedure at the temperature of about 900.degree. to 
950.degree. C. to seal the stacked gate with an oxide layer having a 
thickness of 100 to 200 .ANG. (not shown in the drawing). The sealing of 
the formed stacked gates facilitates the securing of device reliability in 
terms of reduced leakage current between floating gates and other regions. 
FIG. 4B is the cross-sectional view taken along the 4B--4B line in FIG. 4 
that shows the SOI wafer configuration up to this fabrication stage. As is 
seen in FIG. 4B, all the WSi.sub.x, second polysilicon, ONO and first 
polysilicon layers 28, 26, 24 and 20 respectively that are not relevant to 
the areas defined by stacked gates 34 have all been removed in the plasma 
etching procedure described above, and the BPSG layers 22 are directly 
exposed. 
Step 6 
Stacked gates are covered with a second BPSG layer. 
A BPSG layer 30 shown in FIG. 5A with thickness of about 10,000 to 14,000 
.ANG. is then deposited to cover stacked gates completely which is 
subsequently reflown and etched back to achieve planarity. Each of the 
formed BPSG layers that covers the corresponding stacked gates has a 
thickness of about 8,000 to 12,000 .ANG. that stacks atop the 
corresponding WSi.sub.x layers 28 (FIG. 4A). 
Step 7 
Contact openings for the source/drain buried lines and n.sup.+ second 
polysilicon word lines are formed. 
FIG. 5 schematically shows the top view of the SOI wafer having a 
completely fabricated flash array for the device of the present invention. 
As is seen in FIG. 5, contact openings 32 for n.sup.+ source/drain 
buried-lines are then opened by etching for, for example, every 16 or more 
flash cells, meanwhile, contact opening 32 for every n.sup.+ second 
polysilicon word lines are performed simultaneously. Thus the subsequently 
low resistive metal 36 shown in FIG. 5A can efficiently reduce the 
resistance of n.sup.+ buries source/drain diffusion lines by connection 
of both parallelly. Here the low resistance enhances the read current of 
flash cells and thereby improves read speed. On the other hand, body lines 
may have their contact openings 32 opened around the flash memory arrays. 
Step 8 
Metal lines leading into the contact openings are formed for 
interconnecting the memory cells in the flash array with relevant 
peripheral control circuits. 
Metal lines 36 may then be defined to interconnect the device memory cells 
with peripheral control circuit via the contact openings 32 as shown in 
FIG. 5. And, finally, the devices may be protected by passivation 38 shown 
in FIG. 5A. Note that in FIG. 5, hatches are employed to show the 
locations the stacked gates 34. 
Step 8 generally concludes the process for the fabrication of the compact 
contactless flash array for EEPROM semiconductor devices in accordance 
with the preferred embodiment of the present invention. To describe the 
structural configuration of the compact contactless flash array of the 
present invention in further detail, three cross sectional views FIGS. 5A, 
5B and 5C are taken along the 5A-5A', 5B-5B' and 5C-5C' lines respectively 
in the top view of the fabricated SOI wafer shown in FIG. 5. These three 
depicted cross-sectional views, which include the cross sections of the 
stacked gates, the region between consecutive stacked gates, and the field 
oxide at the periphery of the flash array region, are helpful in the 
understanding of the characteristics of the structural configuration of 
the flash array of the present invention, as well as the functional 
characteristics it can achieve. 
In addition to the cross-sectional views FIGS. 5A, 5B and 5C, a perspective 
view of the fabricated flash array of the present invention is also shown 
in FIG. 6 to further demonstrate the spatial characteristics of the 
device's structural configuration. Simultaneous reference to the drawings 
of FIG. 5, FIGS. 5A, 5B and 5C and FIG. 6 will help identify the relative 
spatial relationships of the components for the construction of the flash 
array of the present invention. 
FIG. 7A of the drawing schematically shows the structural configuration of 
one memory cell unit of the flash array of the present invention, while 
FIG. 7B shows the corresponding equivalent circuit symbol thereof. As is 
seen in FIGS. 7A and 7B, each of the fabricated memory cell unit includes 
a pair of n.sup.+ source/drain buried lines S and D respectively, a body 
line B, and a stacked gate G that generally includes a first polysilicon 
layer, an ONO configuration and a second polysilicon layer. The pair of 
n.sup.+ source/drain buried lines sandwiches the body line B, and the 
stacked gate G directly sits atop the body line B. 
FIG. 8 schematically shows, in perspective manner, the connection of a 
group of memory cell units arranged in a portion of the flash array of the 
device of the present invention. In the drawing, circuit symbol of FIG. 7B 
has been employed to schematically exemplify the configuration of an array 
of memory cell units for the present invention. As is seen, a set of 
memory cell units may be cascaded in a row (or column) that have their 
stacked gates G all tied together and triggered by a word line signal 
G.sub.a (or, G.sub.b or G.sub.c). Similarly, another set of memory cell 
units may be cascaded in a column (or row) that have their sources/drains 
S and D, as well as body lines B tied together respectively and be 
controlled by the body line signal B1 (or B2). In the arrangement shown in 
FIG. 8, each row (or column) of the memory cell units in the array may be 
directly addressed in either the read, erase or program mode via the 
selection of the attached metal line, such as the one exemplified by metal 
I that controls the body line B1 (or B2) and the word line G.sub.a (or 
G.sub.b or G.sub.c). 
Thus, in the flash array configuration of the present invention, each of 
the compact cells may share its source/drain with adjacent cells. The body 
lines isolated by source/drain lines allow for the flash memory cells of 
the present invention to make use of the FN (Fowler-Nordheim) tunneling 
effect between the floating gate and the substrate to implement both the 
programming and erasing operation. Due to the use of SOI wafer, the 
substrate portion of each of the adjacent cells is isolated by source and 
drain. By setting the voltage difference between substrate and gate, cell 
programming and erase can be performed, as is exemplified in the table 
below. 
In terms of the applied electric potential at the control terminals of each 
of the memory cell units, Table 1 below lists such a control scheme for 
the read, erase and program of selected number of memory cells, assuming 
the activation of word line G.sub.a and body line B.sub.1 in the array of 
FIG. 8. 
TABLE 1 
______________________________________ 
Single cell 
Operation Program Erase Read 
______________________________________ 
G.sub.a V.sub.ppt (13 V) 
V.sub.BB2 (-13 V) 
V.sub.CG (5 V) 
S.sub.1 0 V Floating 0 V 
B.sub.1 V.sub.BB1 (-7 V) 
7 V 0 V 
D.sub.1 = D.sub.2 
0 V Floating V.sub.D (1 V) 
B.sub.2 0 V 0 V 0 V 
S.sub.2 0 V 0 V 0 V 
G.sub.b /G.sub.c 
0 V 0 V 0 V 
______________________________________ 
When compared to the flash array of the prior art, the present invention is 
advantageously distinguishable in that the body line of the memory cell 
units of the present invention is being isolated by the surrounding buried 
n.sup.+ source/drain lines and the SiO.sub.2 layer of the SOI wafer. This 
allows the memory cells of the flash array of the present invention to be 
erased and programmed utilizing the body line and word line in an FN 
(Fowler-Nordheim) tunneling effect. 
A majority of prior flash array memory cell configurations, on the other 
hand, would have to rely on the drain, source and word line thereof in a 
hot carrier transport mode to implement the memory cell programming. In 
the continuous trend of device dimensional scaling down for the 
improvement of memory density, the short channel effect that is inevitable 
in the prior art devices which rely on hot carrier program/erase 
operations constitutes a serious drawback when compared to the 
characteristics of the flash array of the present invention. 
While the present invention has been described by way of example and in 
terms of preferred embodiments, it is to be understood that the invention 
need not be limited to the disclosed embodiments. On the contrary, it is 
intended to cover various modifications and similar arrangements included 
within the spirit and scope of the appended claims, the scope of which 
should be accorded the broadest interpretation so as to encompass all such 
modifications and similar structures.