SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a conductive portion, a sealing resin, a plurality of semiconductor chips, and a plurality of temperature detection elements. The substrate has a substrate obverse surface and a substrate reverse surface that face opposite sides in a thickness direction. The conductive portion is formed on the substrate obverse surface. The sealing resin covers at least a part of the substrate. The sealing resin also covers the entire conductive portion. The plurality of semiconductor chips are disposed on the substrate obverse surface. The plurality of temperature detection elements are disposed on the substrate obverse surface. The number of temperature detection elements is equal to or greater than the number of semiconductor chips.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device.

BACKGROUND ART

Conventionally, various semiconductor devices provided with switching elements have been proposed. For example, Patent Document 1 discloses a semiconductor device in which two switching elements that constitute a bridge circuit and a thermistor element are disposed on a substrate, and the thermistor element detects the temperature of the substrate.

The two switching elements that constitute the bridge circuit do not necessarily have the same current flowing through them, and there may be a temperature difference between the two switching elements. The temperature detected by the thermistor element is the temperature of the substrate, which is an average of the temperatures of the switching elements. Accordingly, if there is a temperature difference between the two switching elements, even if one of the switching elements exceeds a predetermined design temperature, this situation cannot be detected and this switching element may exhibit thermal runaway.

A switching element with a diode for detecting temperature in a chip has also been proposed. However, this configuration has a problem in that temperature detection is susceptible to noise caused by switching.

PRIOR ART DOCUMENTS

Patent Document

SUMMARY OF THE INVENTION

Problem to be Solved by the Invention

In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device in which temperature detection is not susceptible to noise caused by switching and that is capable of suppressing thermal runaway caused by uneven current.

Means for Solving the Problem

A semiconductor device provided according to a first aspect of the present disclosure includes: a substrate having a substrate obverse surface and a substrate reverse surface that face opposite sides in a thickness direction; a conductive portion formed on the substrate obverse surface; a sealing resin covering at least a part of the substrate and an entirety of the conductive portion; a plurality of semiconductor chips disposed on the substrate obverse surface; and a plurality of temperature detection elements mounted on the substrate obverse surface, where the number of temperature detection elements is equal to or greater than the number of semiconductor chips.

Advantages of the Invention

According to the semiconductor device of the present disclosure, a greater number of temperature detection elements than the number of semiconductor chips are utilized. Accordingly, the respective temperatures of the plurality of semiconductor chips can be detected by different temperature detection elements. This configuration makes it possible to separately compare the respective temperatures of the semiconductor chips with the design temperature even if the currents flowing through the semiconductor chips are uneven. Thus, thermal runaway can be suppressed. Further, the temperature detection elements are mounted on the substrate obverse surface, and are therefore less susceptible to noise caused by switching than a temperature detection unit incorporated within a semiconductor chip.

Further features and advantages of the present disclosure will become more apparent through the following detailed description with reference to the attached drawings.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferable embodiments of the present disclosure will be described in detail with reference to the drawings.

In the present disclosure, “an object A being formed in an object B” and “the object A being formed on the object B” includes “the object A being directly formed in the object B” and “the object A being formed in the object B with another object interposed therebetween”, unless otherwise noted. Similarly, “an object A being arranged in an object B” and “the object A being arranged on the object B” includes “the object A being directly arranged in the object B” and “the object A being arranged in the object B with another object interposed therebetween”, unless otherwise stated. Similarly, “an object A being located on an object B” includes “the object A being located on the object B in contact with the object B” and “the object A being located on the object B with another object interposed therebetween”, unless otherwise stated. Further, “an object A overlapping an object B as viewed in a direction” includes “the object A overlapping the entire object B” and “the object A partially overlapping the object B”, unless otherwise stated.

FIGS.1to8show a semiconductor device according to the first embodiment of the present disclosure. A semiconductor device A1of the present embodiment includes a plurality of leads1, a substrate2, a plurality of bonding portions25, a conductive portion3, two semiconductor chips4, two protective elements9, two control chips5, a plurality of passive elements6, a plurality of wires71, a plurality of wires72, a plurality of wires73, a plurality of wires74, and a sealing resin8. In the present embodiment, the semiconductor device A1is an IPM (Intelligent Power Module). The semiconductor device A1is used, for example, in an air conditioner, a motor control device, or the like.

FIG.1is a perspective view of the semiconductor device A1.FIG.2is a plan view of the semiconductor device A1.FIG.3is a plan view of the semiconductor device A1, with the sealing resin8shown in a transparent manner. Note thatFIG.3shows the outer shape of the sealing resin8with imaginary lines (dash-double dot lines).FIG.4is a bottom view of the semiconductor device A1.FIG.5is a cross-sectional view taken along a line V-V inFIG.3.FIG.6is a cross-sectional view taken along a line VI-VI inFIG.3.FIG.7is a cross-sectional view taken along a line VII-VII inFIG.3.FIG.8is a plan view of the substrate2.

For convenience of description, the thickness direction of the substrate2is referred to as the z direction, the direction parallel to one side of the substrate2that is orthogonal to the z direction (left-right direction inFIGS.2to4) is referred to as the x direction, and the direction orthogonal to the z direction and the x direction (vertical direction inFIGS.2to4) is referred to as the y direction.

The substrate2has a rectangular shape elongated in the x direction as viewed in the z direction (namely, “in a plan view”). The substrate2has a thickness (length in the z direction) of about 0.1 mm to 1.0 mm, for example. Note that the dimensions of the substrate2are not specifically limited. The substrate2is made of an insulating material. The material of the substrate2is not specifically limited. The material of the substrate2is, preferably, a material with a higher thermal conductivity than that of the material of the sealing resin8, for example. Examples of the material of the substrate2include ceramics such as alumina (Al2O3), silicon nitride (SiN), aluminum nitride (AlN), and alumina containing zirconia.

The substrate2has a substrate obverse surface21and a substrate reverse surface22. The substrate obverse surface21and the substrate reverse surface22are surfaces facing in opposite directions in the z direction, and are both flat surfaces that are orthogonal to the z direction. The substrate obverse surface21is a surface facing upward inFIGS.5to7. The conductive portion3and the plurality of bonding portions25are formed and the plurality of leads1and a plurality of electronic components are mounted on the substrate obverse surface21. The plurality of electronic components include the two semiconductor chips4, the two protective elements9, the two control chips5, and the plurality of passive elements6. The substrate reverse surface22is a surface facing downward inFIGS.5to7. As shown inFIG.4, the substrate reverse surface22is exposed from the sealing resin8. The substrate obverse surface21and the substrate reverse surface22both have a rectangular shape. Note that the shape of the substrate2is not specifically limited.

The conductive portion3is formed on the substrate2. In the present embodiment, the conductive portion3is formed on the substrate obverse surface21of the substrate2. The conductive portion3is made of a conductive material. The conductive material that constitutes the conductive portion3is not specifically limited. Examples of the conductive materials of the conductive portion3include materials containing silver (Ag), copper (Cu), gold (Au), or the like, for example. The following description will take an example where the conductive portion3contains silver. Note that the conductive portion3may contain copper instead of silver, or may contain gold instead of silver or copper. Alternatively, the conductive portion3may contain Ag—Pt, Ag—Pd, or the like. The method for forming the conductive portion3is not specifically limited. For example, the conductive portion3is formed by sintering a paste containing these metals. The thickness of the conductive portion3is not specifically limited, and is, for example, about 5 μm to 30 μm.

The shape and other attributes of the conductive portion3are not specifically limited. In the present embodiment, the conductive portion3includes a plurality of pads31and a plurality of interconnects32as shown inFIG.8, for example.

Each pad31has a rectangular shape, for example, and any of the leads15(described later), a control device50(described later), the passive elements6, and the wires72to74is conductively bonded to the pad31. Note that the shape of each pad31is not specifically limited. The pads31are arranged spaced apart from each other.

The plurality of pads31include two pads31a, two pads31b, two pads31c, two pads31d, and a pad31e, as shown inFIGS.3and8. The two pads31aare arranged side by side in the x direction near the upper right corner of the substrate obverse surface21, as shown inFIG.8. Terminals of a thermistor6a(described later) are bonded to the two pads31a, as shown inFIG.3. The two pads31bare arranged side by side in the x direction near the upper left corner of the substrate obverse surface21, as shown inFIG.8. Terminals of a thermistor6b(described later) are bonded to the two pads31b, as shown inFIG.3. The two pads31care arranged between the two pads31aand an edge in the y direction of the substrate obverse surface21near the upper right corner of the substrate obverse surface21, as shown inFIG.8. Leads15a(described later) are bonded to the two pads31c, as shown inFIG.3. The two pads31dare arranged between the two pads31band an edge in the y direction of the substrate obverse surface21near the upper left corner of the substrate obverse surface21, as shown inFIG.8. Leads15b(described later) are bonded to the two pads31d, as shown inFIG.3. The pad31eis arranged near the center of the substrate obverse surface21, as shown inFIG.8. A control chip5b(described later) is bonded to the pad31e, as shown inFIG.3.

Each interconnect32is connected to the plurality of pads31and serves as a conduction path between the connected pads31. The plurality of interconnects32include two interconnects32aand two interconnects32b, as shown inFIGS.3and8. Each interconnect32ais connected to a pad31aand a pad31c. Each interconnect32bis connected to a pad31band a pad31d.

The plurality of bonding portions25are formed on the substrate2, as shown inFIG.8. In the present embodiment, the plurality of bonding portions25are formed closer to one side (lower side inFIG.8) in the y direction of the substrate obverse surface21of the substrate2. The material of the bonding portions25is not specifically limited, and is, for example, a material capable of bonding the substrate2to the leads1. The bonding portions25are made of a conductive material, for example. The conductive material that constitutes the bonding portions25is not specifically limited. Examples of the conductive materials of the bonding portions25include materials containing silver (Ag), copper (Cu), gold (Au), or the like, for example. The following description will take an example where the bonding portions25contain silver. The bonding portions25in this example contain the same conductive material as that of the conductive portion3. Note that the bonding portions25may contain copper instead of silver, or may contain gold instead of silver or copper. Alternatively, the bonding portions25may contain Ag—Pt, Ag—Pd, or the like. The method for forming the bonding portions25is not specifically limited. For example, the bonding portions25are formed by sintering a paste containing these metals, as the conductive portion3is. The thickness of the bonding portions25is not specifically limited, and is about 5 μm to 30 μm, for example.

In the present embodiment, the plurality of bonding portions25include bonding portions251and252, as shown inFIG.8. The bonding portions251and252are separated from each other. The bonding portion251is formed closer to one side in the x direction (right side inFIG.8) when the substrate2is viewed in the z direction. A lead11(described later) is bonded to the bonding portions251. The bonding portion252is formed closer to the other side in the x direction (left side inFIG.8) when the substrate2is viewed in the z direction. A lead12(described later) is bonded to the bonding portions252. Note that the shape and arrangement of the bonding portions251and252are not specifically limited.

The plurality of leads1contain metal, and have a higher thermal conductivity than that of the substrate2, for example. The metal that constitutes the leads1is not specifically limited, and is, for example, copper (Cu), aluminum, iron (Fe), oxygen-free copper, or an alloy of these metals (e.g., Cu—Sn alloy, Cu—Zr alloy, Cu—Fe alloy etc.). The plurality of leads1may also be nickel (Ni) plated. The plurality of leads1may be formed, for example, by pressing a die against a metal plate, or by patterning a metal plate by means of etching. Note that the method for forming the plurality of leads1is not specifically limited. The thickness of each lead1is not specifically limited, and is about 0.4 to 0.8 mm, for example. The leads1are separated from each other.

In the present embodiment, the plurality of leads1include a lead11, a lead12, a lead13, a lead14, and a plurality of leads15. The lead11, the lead12, the lead13, and the lead14constitute conduction paths to the semiconductor chips4, and protrude from a side of the semiconductor device A1that faces one side in the y direction (lower side inFIGS.2and3). The plurality of leads15constitute conduction paths to the control chips5or the passive elements6, and protrude from a side face of the semiconductor device A1that faces the other side in the y direction (upper side inFIGS.2and3).

The lead11is arranged on the substrate2. In the present embodiment, the lead11is arranged on the substrate obverse surface21. The lead11is an example of a “first lead”. The lead11is bonded to a bonding portion25via a bonding material75. The bonding material75need only be capable of bonding the lead11to the bonding portion25. From the viewpoint of efficiently transmitting heat from the lead11to the substrate2, a bonding material75with higher thermal conductivity is preferable. For example, a silver paste, a copper paste, solder, or the like is used. However, the bonding material75may alternatively be an insulating material such as an epoxy resin or a silicone resin. If the bonding portions25are not formed in the substrate2, the lead11may alternatively be bonded to the substrate2.

The configuration of the lead11is not specifically limited. In the description of the present embodiment, the lead11is divided into a mounting portion111, a protruding portion112, an inclined connecting portion113, and a parallel connecting portion114, as shown inFIG.5.

The mounting portion111has a substantially rectangle shape as viewed in the z direction, and has an obverse surface111aand a reverse surface111b. The obverse surface111aand the reverse surface111bare surfaces facing opposite sides in the z direction, and are both surfaces orthogonal to the z direction. The obverse surface111ais a surface facing upward inFIGS.5and6. A semiconductor chip4aand a protective element9aare mounted on the obverse surface111a. The reverse surface111bis a surface facing downward inFIGS.5to7. The reverse surface111bis bonded to the bonding portion25by the bonding material75. The inclined connecting portion113and the parallel connecting portion114are covered by the sealing resin8. The inclined connecting portion113is connected to the mounting portion111and the parallel connecting portion114, and is inclined with respect to the mounting portion111and the parallel connecting portion114. The parallel connecting portion114is connected to the inclined connecting portion113and the protruding portion112, and is parallel to the mounting portion111. The protruding portion112is continuous with an end of the parallel connecting portion114, and is a portion of the lead11that protrudes from the sealing resin8. The protruding portion112protrudes on the opposite side, in the y direction, to the mounting portion111. The protruding portion112is used to electrically connect the semiconductor device A1to an external circuit, for example. In the example shown in the figures, the protruding portion112is bent toward the side on which the obverse surface111aof the mounting portion111faces in the z direction.

The lead12is arranged on the substrate2. In the present embodiment, the lead12is arranged on the substrate obverse surface21. The lead12is an example of a “second lead”. The lead12is bonded to a bonding portion25via the bonding material75. The configuration of the lead12is not specifically limited. In the description of the present embodiment, the lead12is divided into a mounting portion121, a protruding portion122, an inclined connecting portion123, and a parallel connecting portion124, as shown inFIG.7.

The mounting portion121has a substantially rectangle shape as viewed in the z direction, and has an obverse surface121aand a reverse surface121b. The obverse surface121aand the reverse surface121bare surfaces facing opposite sides in the z direction, and are both surfaces orthogonal to the z direction. The obverse surface121ais a surface facing upward inFIG.7. A semiconductor chip4band a protective element9bare mounted on the obverse surface121a. The reverse surface121bis a surface facing downward inFIG.7. The reverse surface121bis bonded to a bonding portion25by the bonding material75. The inclined connecting portion123and the parallel connecting portion124are covered by the sealing resin8. The inclined connecting portion123is connected to the mounting portion121and the parallel connecting portion124, and is inclined with respect to the mounting portion121and the parallel connecting portion124. The parallel connecting portion124is connected to the inclined connecting portion123and the protruding portion122, and is parallel to the mounting portion121. The protruding portion122is continuous with an end of the parallel connecting portion124, and is a portion of the lead12that protrudes from the sealing resin8. The protruding portion122protrudes on the opposite side, in the y direction, to the mounting portion121. The protruding portion122is used to electrically connect the semiconductor device A1to an external circuit, for example. In the example shown in the figures, the protruding portion122is bent toward the side on which the obverse surface121aof the mounting portion121faces in the z direction.

In the present embodiment, the lead13is not arranged on the substrate2, and is supported by the sealing resin8. The lead13does not include portions corresponding to the mounting portion111and the inclined connecting portion113of the lead11. Note that the configuration of the lead13is not limited thereto. In the description of the present embodiment, the lead13is divided into a protruding portion132and a wire bonding portion134, as shown inFIG.6.

The wire bonding portion134is covered by the sealing resin8. Wires71are bonded to the wire bonding portion134. The protruding portion132is continuous with an end of the wire bonding portion134, and is a portion of the lead13that protrudes from the sealing resin8. The protruding portion132protrudes toward the opposite side, in the y direction, to the mounting portion111of the lead11. The protruding portion132is used to electrically connect the semiconductor device A1to an external circuit, for example. In the example shown in the figures, the protruding portion132is bent toward the side on which the obverse surface111aof the lead11faces in the z direction.

In the present embodiment, the lead14is not arranged on the substrate2, and is supported by the sealing resin8. The lead14has the same configuration as that of the lead13. Note that the configuration of the lead14is not limited thereto. In the description of the present embodiment, the lead14is divided into a protruding portion142and a wire bonding portion144.

The wire bonding portion144is covered by the sealing resin8. Wires71are bonded to the wire bonding portion144. The protruding portion142is continuous with an end of the wire bonding portion144, and is a portion of the lead14that protrudes from the sealing resin8. The protruding portion142protrudes toward the opposite side, in the y direction, to the mounting portion111of the lead11. The protruding portion142is used to electrically connect the semiconductor device A1to an external circuit, for example. In the example shown in the figures, the protruding portion142is bent toward the side on which the obverse surface111aof the lead11faces in the z direction.

The plurality of leads15are arranged on the substrate2. In the present embodiment, the plurality of leads15are arranged on the substrate obverse surface21. Each lead15is an example of a “control lead”. The leads15are bonded to respective pads31the conductive portion3via a conductive bonding material76. The conductive bonding material76need only be capable of bonding the leads15to the pads31and electrically connecting the leads15to the pads31. The conductive bonding material76is, for example, a silver paste, a copper paste, solder, or the like.

The configuration of the leads15is not specifically limited. In the description of the present embodiment, each lead15is divided into a bonding section151, a protruding portion152, an inclined connecting portion153, and a parallel connecting portion154, as shown inFIGS.5to7.

The bonding section151has an obverse surface151aand a reverse surface151b. The obverse surface151aand the reverse surface151bare surfaces facing opposite sides in the z direction, and are both surfaces orthogonal to the z direction. The obverse surface151ais a surface facing upward inFIGS.5to75. The reverse surface151bis a surface facing downward inFIGS.5to7. The reverse surface151bis bonded to a pad31by the conductive bonding material76. The inclined connecting portion153and the parallel connecting portion154are covered by the sealing resin8. The inclined connecting portion153is connected to the bonding section151and the parallel connecting portion154, and is inclined with respect to the bonding section151and the parallel connecting portion154. The parallel connecting portion154is connected to the inclined connecting portion153and the protruding portion152, and is parallel to the bonding section151. The protruding portion152is continuous with an end of the parallel connecting portion154, and is a portion of the lead15that protrudes from the sealing resin8. The protruding portion152protrudes on the opposite side, in the y direction, to the bonding section151. The protruding portion152is used to electrically connect the semiconductor device A1to an external circuit, for example. In the example shown in the figures, the protruding portion152is bent toward the side on which the obverse surface151aof the bonding portion151faces in the z direction.

In the present embodiment, the plurality of leads15include two leads15aand two leads15b. The two leads15aare conductively bonded to different pads31c. The two leads15bare conductively bonded to different pads31d.

Each of the two semiconductor chips4is arranged on one of the leads1. When the two semiconductor chips4are distinguished, one is referred to as a semiconductor chip4aand the other as a semiconductor chip4b. When the two semiconductor chips4are not distinguished, they are referred to simply as the semiconductor chip(s)4. The type and the function of the semiconductor chips4are not specifically limited. The present embodiment will describe an example of the case where the semiconductor chips4are power transistors for controlling power. Each semiconductor chip4is, for example, a MOSFET (metal-oxide-semiconductor field-effect transistor) that includes a SiC (silicon carbide) substrate. Note that each semiconductor chip4may alternatively be a MOSFET that includes a Si (silicon) substrate instead of a SiC substrate, and may include an IGBT element, for example. Further, each semiconductor chip4may alternatively be a MOSFET that contains GaN (gallium nitride).

Each semiconductor chip4has a rectangular plate-like shape as viewed in the z direction, and includes an element obverse surface41, an element reverse surface42, a source electrode43, a gate electrode44, and a drain electrode45. The element obverse surface41and the element reverse surface42face opposite sides in the z direction. The element obverse surface41is a surface facing upward in theFIGS.5to7. The element reverse surface42faces downward inFIGS.5to7. The source electrode43and the gate electrode44are arranged on the element obverse surface41, as shown inFIG.3. The drain electrode45is arranged on the element reverse surface42, as shown inFIGS.5to7. Note that the shape and the arrangement of the source electrode43, the gate electrode44, and the drain electrode45are not specifically limited.

The semiconductor chip4ais arranged on the lead11, as shown inFIGS.3,5, and6. The semiconductor chip4ais bonded to the lead11by a conductive bonding material (not shown) with the element reverse surface42facing toward the lead11, as shown inFIGS.5and6. Thus, the drain electrode45of the semiconductor chip4ais conductively connected to the lead11by the conductive bonding material. The conductive bonding material is, for example, a silver paste, a copper paste, solder, or the like. The source electrode43of the semiconductor chip4ais conductively connected to the lead13by wires71, as shown inFIG.3. The wires71are made of aluminum (Al), copper (Cu), or the like, for example. Note that the material, the wire diameter, and the number of wires71are not specifically limited. The semiconductor chip4bis arranged on the lead12, as shown inFIGS.3and7. The semiconductor chip4bis bonded to the lead12by a conductive bonding material (not shown) with the element reverse surface42facing toward the lead12, as shown inFIG.7. Thus, the drain electrode45of the semiconductor chip4bis conductively connected to the lead12by the conductive bonding material. The source electrode43of the semiconductor chip4bis conductively connected to the lead14by wires71, as shown inFIG.3.

The gate electrode44of the semiconductor chip4ais connected to the conductive portion3by the wires72and is conductively connected to the control chip5a, as shown inFIG.3. The source electrode43of the semiconductor chip4ais connected to the conductive portion3by the wires73and is conductively connected to the control chip5a. The wires72and73are made of gold (Au), silver (Ag), copper (Cu), aluminum (Al), or the like, for example. Note that the material, the wire diameter, and the number of wires72and73are not specifically limited. The control chip5ainputs a drive signal to the gate electrode44of the semiconductor chip4a. The gate electrode44of the semiconductor chip4bis connected to the conductive portion3by the wires72and is conductively connected to the control chip5b. The control chip5binputs a drive signal to the gate electrode44of the semiconductor chip4b.

The semiconductor chip A1has the leads12and13that are conductively connected outside the device, and is used as a bridge circuit with the semiconductor chip4aserving as a switching element at the upstream stage and the semiconductor chip4bserving as a switching element at the downstream stage. In this case, a DC voltage is applied between the lead11and the lead14, and the semiconductor device A1outputs, from the lead12, a switching signal whose voltage switches in accordance with a drive signal by inputting the drive signal to the gate electrodes44of the semiconductor chips4aand4b.

The two protective elements9are arranged on respective leads1. When the two protective elements9are distinguished, one is referred to as a protective element9aand the other as a protective element9b. When the two protective elements9are not distinguished, they are referred to simply as the protective element(s)9. The type and the function of the protective elements9are not specifically limited. The present embodiment will describe an example of the case where the protective elements9are diodes for preventing a reverse voltage from being applied to the semiconductor chips4.

Each protective element9has a rectangular plate-like shape as viewed in the z direction, and includes a protective element obverse surface91, a protective element reverse surface92, an anode electrode93, and a cathode electrode94. The protective element obverse surface91and the protective element reverse surface92face opposite sides in the z direction. The protective element obverse surface91is a surface facing upward in theFIGS.5and6. The protective element reverse surface92faces downward inFIGS.5and6. The anode electrode93is arranged on the protective element obverse surface91, as shown inFIG.3. The cathode electrode94is arranged on the protective element reverse surface92, as shown inFIGS.5and6. Note that the shape and the arrangement of the anode electrode93and the cathode electrode94are not specifically limited.

The protective element9ais arranged on the lead11on one side in the y direction (lower side inFIG.3) of the semiconductor chip4a, as shown inFIGS.3,5, and6. The protective element9ais bonded to the lead11by a conductive bonding material (not shown) with the protective element reverse surface92facing toward the lead11, as shown inFIGS.5and6. Thus, the cathode electrode94of the protective element9ais conductively connected to the lead11by the conductive bonding material. The conductive bonding material is, for example, a silver paste, a copper paste, solder, or the like. The cathode electrode94of the protective element9ais conductively connected to the drain electrode45of the semiconductor chip4avia the lead11. Further, the anode electrode93of the protective element9ais conductively connected to the semiconductor chip4aand the lead13by wires71, as shown inFIG.3. In the present embodiment, these wires71each have one end bonded to the source electrode43of the semiconductor chip4a, an intermediate portion bonded to the anode electrode93of the protective element9a, and the other end bonded to the lead13. Note that the source electrode43may alternatively be connected to the anode electrode93by wires71, and the anode electrode93may be connected to the lead13by other wires71. Further, the source electrode43may be connected to the lead13by wires71, and the anode electrode93may be connected to the lead13by other wires71. As described above, the protective element9ais connected to the semiconductor chip4ain inverse parallel.

The protective element9bis arranged on the lead12on one side in the y direction (lower side inFIG.3) of the semiconductor chip4b, as shown inFIG.3. The protective element9bis bonded to the lead12by a conductive bonding material (not shown) with the protective element reverse surface92facing toward the lead12. Thus, the cathode electrode94of the protective element9bis conductively connected to the lead12by the conductive bonding material. The cathode electrode94of the protective element9bis conductively connected to the drain electrode45of the semiconductor chip4bvia the lead12. Further, the anode electrode93of the protective element9bis conductively connected to the semiconductor chip4band the lead14by wires71, as shown inFIG.3. In the present embodiment, these wire71each have one end bonded to the source electrode43of the semiconductor chip4b, an intermediate portion bonded to the anode electrode93of the protective element9b, and the other end bonded to the lead14. Note that the source electrode43may alternatively be connected to the anode electrode93by wires71, and the anode electrode93may be connected to the lead14by other wires71. Further, the source electrode43may be connected to the lead14by wires71, and the anode electrode93may be connected to the lead13by other wires71. As described above, the protective element9bis connected to the semiconductor chip4bin inverse parallel. Note that the semiconductor device A1need not have the protective elements9.

The two control chips5are for controlling the driving of the semiconductor chips4, and are arranged on the substrate obverse surface21of the substrate2. When the two control chips5are distinguished, one is referred to as a control chip5aand the other as a control chip5b. When the two control chips5are not distinguished, they are referred to simply as the control chip(s)5.

The control chips5aand5bare arranged between the leads11and12, spaced apart from the leads11and12, as shown inFIG.3. The control chip5ais located closer to the lead11, and the control chip5bis located closer to the lead12. Note that the arrangement of the control chips5aand5bis not specifically limited.

The control chip5acontrols the drive of the semiconductor chip4a. Specifically, the control chip5agenerates a drive signal and inputs the generated drive signal to the gate electrode44of the semiconductor chip4a, thereby driving the semiconductor chip4a. In the present embodiment, the control chip5aconstitutes a control device50together with a die pad and a plurality of wires (not shown), as well as a plurality of leads53and a resin54. The die pad and the plurality of leads53are plate-like members made of copper (Cu), for example. The control chip5ais mounted on the die pad. Each lead53are electrically continuous with the control chip5athrough a wire. The resin54covers the control chip5a, the entire wires, and a part of each lead53, and is made of an insulating material such as an epoxy resin or a silicone gel, for example. The leads53are arranged on both ends in the y direction of the resin54, spaced apart from each other in the x direction, as shown inFIG.3. The leads53extend in the y direction, and a part of each lead53protrudes from one of the two side faces in the y direction of the resin54. The portion of each lead53that protrudes from the resin54is conductively bonded to a corresponding pad31of the conductive portion3. In the present embodiment, the control device50is a SOP (Small Outline Package) package. Note that the package type of the control device50is not limited to the SOP type, and may alternatively be, for example, any other type of package such as the QFP (Quad Flat Package) type or the SOJ (Small Outline J-lead Package) type. Note that the size and the shape of the control device50, the number of leads, and so on, are not specifically limited. The control device50may also include a circuit chip other than the control chip5a.

The control chip5bcontrols the drive of the semiconductor chip4b. Specifically, the control chip5bgenerates a drive signal and inputs the generated drive signal to the gate electrode44of the semiconductor chip4b, thereby driving the semiconductor chip4b. In the present embodiment, the control chip5bis arranged as-is on the substrate obverse surface21. The control chip5bhas one face bonded to the pads31c, and a plurality of electrodes arranged on the other face are conductively connected to respective pads31by wires74. The wires74are made of gold (Au), silver (Ag), copper (Cu), aluminum (Al), or the like, for example. Note that the material, the wire diameter, and the number of wires74are not specifically limited.

Note that the control chip5amay alternatively be arranged as-is on the substrate obverse surface21, as the control chip5bis. Alternatively, the control chip5bmay be arranged as the control device50on the substrate obverse surface21, as the control chip5ais.

The plurality of passive elements6are arranged on the substrate obverse surface21of the substrate2, and are conductively bonded to the pads31of the conductive portion3. The passive elements6are, for example, resistors, capacitors, coils, diodes, or the like. The passive elements6include a thermistor6aand a thermistor6b.

The thermistors6aand6bare temperature detection elements and are mounted on the substrate obverse surface21of the substrate2. The thermistors6aand6bare resistors whose electrical resistance greatly changes in response to temperature changes, and the voltage across terminals changes as the resistance value changes in response to the surrounding temperature. The temperature around the thermistors6aand6bis detected based on the voltage across the terminals of the thermistors6aand6b. Note that the characteristics of the thermistors6aand6bare not specifically limited. The thermistors6aand6bmay be NTC (negative temperature coefficient) thermistors, PTC (Positive temperature coefficient) thermistors, or may be thermistors with any other characteristics.

The thermistor6ais for detecting the temperature of the semiconductor chip4a, and is arranged adjacent to the mounting portion111of the lead11on which the semiconductor chip4ais mounted, as shown inFIG.3. The thermistor6ais insulated from the lead11. The thermistor6aspans between the two pads31aof the conductive portion3. One terminal of the thermistor6ais conductively bonded to one pad31a, and the other terminal is conductively bonded to the other pad31a. Each pad31ais conductively connected to the respective leads15avia the interconnects32aand the pads31c. That is, the pads31a, the interconnects32a, and the pads31care conduction paths that allow the thermistor6ato be electrically continuous with the leads15a. The two leads15aserve as terminals for detecting the temperature of the semiconductor chip4aand output the voltage across the terminals of the thermistor6a. In the present embodiment, the thermistor6ais an example of a “first temperature detection element”.

The thermistor6bis for detecting the temperature of the semiconductor chip4b, and is arranged adjacent to the NC mounting portion121of the lead12on which the semiconductor chip4bis mounted, as shown inFIG.3. The thermistor6bis insulated from the lead12. The thermistor6bspans between the two pads31bof the conductive portion3. One terminal of the thermistor6bis conductively bonded to one pad31b, and the other terminal is conductively bonded to the other pad31b. Each pad31bis conductively connected to the respective leads15bvia the interconnects32band the pads31d. That is, the pads31b, the interconnects32b, and the pads31dare conduction paths that allow the thermistor6bto be electrically continuous with the leads15b. The two leads15bserve as terminals for detecting the temperature of the semiconductor chip4band output the voltage across the terminals of the thermistor6b. In the present embodiment, the thermistor6bis an example of a “second temperature detection element”.

Note that the semiconductor device A1may have any other have temperature detection elements instead of the thermistors6aand6b. Other temperature detection elements may be semiconductor temperature sensors. A semiconductor temperature sensor is a Si diode, whose forward voltage greatly changes in response to temperature changes, or the like, and detects the surrounding temperature based on the voltage across the terminals when a predetermined current is applied.

The other passive elements6are conductively bonded to the pads31of the conductive portion3, and are electrically continuous with NC the control chips5or the semiconductor chips4via the interconnects32and the pads31. Note that the type and the number of passive elements6and the positions at which the passive elements6are arranged are not specifically limited.

The sealing resin8at least partially covers the semiconductor chips4aand4b, the protective elements9aand9b, the control device50(control chip5a), the control chip5b, the plurality of passive elements6, the wires71to74, the plurality of leads1, and the substrate2. The material of the sealing resin8is not specifically limited. For example, an insulating material such as an epoxy resin or a silicone gel is used as appropriate.

The sealing resin8has a resin obverse surface81, a resin reverse surface82, and four resin side surfaces83. The resin obverse surface81and the resin reverse surface82face opposite sides in the z direction, and are both flat surfaces orthogonal to the z direction. The resin obverse surface81is a surface facing upward inFIGS.5to7. The resin reverse surface82is a surface facing downward inFIGS.5to7. The resin side surfaces83are continuous with the resin obverse surface81and the resin reverse surface82, and face in the x direction or the y direction. The substrate reverse surface22of the substrate2is exposed from the resin reverse surface82of the sealing resin8, as shown inFIG.4. In the present embodiment, the substrate reverse surface22is flush with the resin reverse surface82, as shown inFIGS.5to7.

Next, an example of a method for producing the semiconductor device A1will be described below with reference toFIG.9. Note that the production method described below is one means for realizing the semiconductor device A1, and the present disclosure is not limited thereto.

As shown inFIG.9, the production method of this example has a conductive portion forming step (step S1), a lead frame bonding step (step S2), a semiconductor chip mounting step (step S3), a control device mounting step (step S4), a wire connecting step (step S5), a resin forming step (step S6), and a frame cutting step (step S7).

In the conductive portion forming step (step S1), first, the substrate2is prepared. The substrate2is made of ceramic, for example. Next, the conductive portion3and the plurality of bonding portions25are formed on the substrate obverse surface21of the substrate2. In this example, the conductive portion3and the plurality of bonding portions25are collectively formed. For example, the conductive portion3and the plurality of bonding portions25that contain a metal such as silver (Ag) serving as a conductive material can be obtained by printing a metal paste and then sintering it.

In the lead frame bonding step (step S2), first, a bonding paste is printed on the plurality of bonding portions25, and a conductive bonding paste is printed on some of the pads31of the conductive portion3. The bonding paste and the conductive bonding paste are, for example, an Ag paste, a solder paste, or the like. Next, a lead frame is prepared. The lead frame includes a plurality of leads1, and have a frame to which the plurality of leads1are connected. Note that the shape or the like of the lead frame is not limited in any way. Next, the leads11and12, of the plurality of leads1, are made to face the plurality of bonding portions25via the bonding paste. Also, the plurality of leads15, of the plurality of leads1, are made to face the conductive portion3(pads31) via the conductive bonding paste. For example, the bonding material75is formed by the bonding paste and the conductive bonding material76is formed by the conductive bonding paste by heating and then cooling the bonding paste and the conductive bonding paste. Thus, the leads11and12are bonded to the plurality of bonding portions25via the bonding material75, and the plurality of leads15are bonded to the conductive portion3via the conductive bonding material76.

In the semiconductor chip mounting step (step S3), first, a conductive bonding paste is printed at predetermined positions on the leads11and12. The conductive bonding paste is, for example, an Ag paste, a solder paste, or the like. Next, the semiconductor chip4aand the protective element9aare attached to the conductive bonding paste printed on the lead11, and the semiconductor chip4band the protective element9bare attached to the conductive bonding paste printed on the lead12. Then, the conductive bonding material is formed by the conductive bonding paste by heating and then cooling the conductive bonding paste, for example. Thus, the semiconductor chip4aand the protective element9aare bonded to the lead11via the conductive bonding material, and the semiconductor chip4band the protective element9bare bonded to the lead12via the conductive bonding material.

In the control device mounting step (step S4), a conductive bonding paste is printed on some of the pads31of the conductive portion3. The conductive bonding paste is, for example, an Ag paste, a solder paste, or the like. Next, the leads53of the control device50are attached to the conductive bonding paste. Also, the control chip5bis attached to the conductive bonding paste printed on the pad31e. Next, the leads53and the control chip5bof the control device50are bonded to respective pads31via the conductive bonding material by heating and then cooling the conductive bonding paste, for example. Further, the thermistors6aand6band the other passive elements6are bonded to respective pads31of the conductive portion3via the conductive bonding material through a similar step.

In the wire connecting step (step S5), first, the plurality of wires71are connected. In this example, wire materials made of aluminum (Al) are sequentially connected by means of a wedge bonding method, for example. In the present embodiment, a leading end of each wire material is bonded to the source electrode43of the semiconductor chip4a, a capillary is moved while pulling out the wire material to bond the wire material to the anode electrode93of the protective element9a, and the capillary is further moved while pulling out the wire material to bond the wire material to the wire bonding portion134of the lead13, thereby connecting wires71. Similarly, wires71are connected by sequentially bonding wire materials to the source electrode43of the semiconductor chip4b, the anode electrode93of the protective element9b, and the wire bonding portion144of the lead14. Thus, the plurality of wires71are obtained. Next, the plurality of wires72,73, and74are connected. In this example, wire materials made of gold (Au) are sequentially connected by means of a capillary bonding method, for example. Thus, the plurality of wires72,73, and74are obtained.

In the resin forming step (step S6), for example, a part of the lead frame, a part of the substrate2, the semiconductor chips4aand4b, the protective elements9aand9b, the control device50(control chip5a), the control chip5b, the plurality of passive elements6, and the plurality of wires71to74are enclosed by a mold. Next, a liquid resin material is injected into a space defined by the mold. Subsequently, this resin material is cured, and the sealing resin8is thus obtained.

In the frame cutting step (step S7), appropriate portions of a part of the lead frame that is exposed from the sealing resin8are cut. Thus, the plurality of leads1are divided. Thereafter, the plurality of leads1are bent or otherwise processed as necessary to obtain the above-described semiconductor device A1.

Next, the operation and effects of the semiconductor device A1will be described.

According to the present embodiment, the thermistor6ais arranged adjacent to the mounting portion111of the lead11on which the semiconductor chip4ais mounted, and detects the temperature of the semiconductor chip4a. The thermistor6bis arranged adjacent to the mounting portion121of the lead12on which the semiconductor chip4bis mounted, and detects the temperature of the semiconductor chip4b. Accordingly, even if a current unevenly flows through the semiconductor chips4aand4band causes a temperature difference, the respective temperatures can be separately detected and compared properly with the design temperature. This configuration makes it possible to suppress thermal runaway. Further, the thermistors6aand6bare mounted on the substrate obverse surface21of the substrate2. Accordingly, the thermistors6aand6bare less affected by noise caused by switching of the semiconductor chips4aand4bthan in the case where temperature detection units are incorporated into the semiconductor chips4aand4b.

According to the present embodiment, the conductive portion3is formed on the substrate obverse surface21of the substrate2. The conductive portion3has the pads31to which the control device50and the control chip5bare conductively bonded. This configuration enables conduction paths to the control device50and the control chip5bto be constituted by the conductive portion3formed on the substrate obverse surface21. Accordingly, it is possible to make the conduction paths thinner and denser than in the case of constituting the conduction paths with metal leads, for example.

According to the present embodiment, the plurality of leads1have a higher thermal conductivity than that of the substrate2, and can therefore suppress a decrease in heat dissipation from the semiconductor chips4that may deteriorate as a result of employing the substrate2. Further, the semiconductor chip4ais directly bonded to the lead11by the conductive bonding material, and the semiconductor chip4bis directly bonded to the lead12by the conductive bonding material. Accordingly, the semiconductor chip4a(4b) can be made electrically continuous with the lead11(12), and heat from the semiconductor chip4a(4b) can be efficiently transmitted to the lead11(12). Since the plurality of leads1are exposed from the sealing resin8, it is possible to form the conduction paths to the semiconductor chips4from the outside and further ensure heat dissipation characteristics of the semiconductor chips4. The bonding portions25are formed on the substrate2, and the leads11and12are bonded to the substrate2via the bonding portions25. For example, the surfaces of the bonding portions25can be finished more smoothly relative to the surface roughness of the substrate obverse surface21of the substrate2, which is made of ceramic. This configuration makes it possible to suppress generation of an unintended minute gap or the like in heat transfer paths from the leads11and12to the substrate2, and further promote heat dissipation of the semiconductor chips4and other members. The substrate reverse surface22of the substrate2is exposed from the sealing resin8. This configuration allows heat transferred from the semiconductor chips4or other members to the substrate2to be more efficiently dissipated to the outside.

According to the present embodiment, the conductive portion3and the bonding portions25contain the same conductive material. Therefore, the conductive portion3and the bonding portions25can be collectively formed on the substrate2. This is preferable to improving production efficiency of the semiconductor device A1. The plurality of leads15are bonded to the pads31of the conductive portion3via the conductive bonding material76. This configuration allows the plurality of leads15to be more firmly fixed to the substrate2. In addition, the resistance between the plurality of leads15and the conductive portion3can be lowered.

According to the present embodiment, the control chip5aand the control chip5bare arranged on the substrate obverse surface21between the lead11, on which the semiconductor chip4ais arranged, and the lead12, on which the semiconductor chip4bis arranged. Accordingly, the difference between the distance from the control chip5ato the semiconductor chip4aand the distance from the control chip5bto the semiconductor chip4bcan be reduced. As a result, the difference in transmission time between the drive signal input from the control chip5ato the semiconductor chip4aand the drive signal input from the control chip5bto the semiconductor chip4bcan be reduced.

Note that the present embodiment has described the case where the semiconductor device A1includes two temperature detection elements, namely the thermistor6afor detecting the temperature of the semiconductor chip4aand the thermistor6bfor detecting the temperature of the semiconductor chip4b. However, this need not be the case. The semiconductor device A1may include a larger number of temperature detection elements than the number of semiconductor chips4.

FIGS.10to14show other embodiments of the present disclosure. Note that, in these figures, the same or similar elements as those in the above embodiment are assigned the same reference signs in the above embodiment.

FIG.10is a diagram for illustrating a semiconductor device A2according to the second embodiment of the present disclosure.FIG.10is a plan view of the semiconductor device A2and corresponds toFIG.3.FIG.10shows the sealing resin8in a transparent manner, and indicates the outer shape of the sealing resin8with imaginary lines (dash-double dot lines), asFIG.3does. The semiconductor device A2of the present embodiment is different from the first embodiment in the positions at which the thermistors6aand6bare arranged and the shapes of the leads11and12.

In the semiconductor device A2according to the present embodiment, the thermistors6aand6bare arranged closer to an edge on one side in the y direction (upper edge inFIG.10) of the substrate obverse surface21than in the case of semiconductor device A1. That is, compared with the semiconductor device A1, the thermistor6ais arranged away from the mounting portion111of the lead11, and the thermistor6bis arranged away from the mounting portion121of the lead12.

The lead11further includes an extended portion115that extends from the mounting portion111toward the thermistor6ain the y direction. That is, the thermistor6ais arranged close to a leading end of the extended portion115. The thermistor6ais kept away from the mounting portion111and the semiconductor chip4amounted on the mounting portion111, but is adjacent to the lead11due to the presence of the extension unit115. Accordingly, heat generated by the semiconductor chip4ais transmitted to the thermistor6avia the lead11.

The lead12further includes an extended portion125that extends from the mounting portion121toward the thermistor6bin the y direction. That is, the thermistor6bis arranged close to a leading end of the extended portion125. The thermistor6bis kept away from the mounting portion121and the semiconductor chip4bmounted on the mounting portion121, but is adjacent to the lead12due to the presence of the extension unit125. Accordingly, heat generated by the semiconductor chip4bis transmitted to the thermistor6bvia the lead12.

According to the present embodiment, the thermistor6ais arranged adjacent to the extended portion115extending from the mounting portion111of the lead11on which the semiconductor chip4ais mounted, and detects the temperature of the semiconductor chip4a. The thermistor6bis arranged adjacent to the extended portion125extending from the mounting portion121of the lead12on which the semiconductor chip4bis mounted, and detects the temperature of the semiconductor chip4b. Accordingly, the temperatures can be separately detected, and thermal runaway can therefore be suppressed. The thermistors6aand6bare mounted on the substrate obverse surface21of the substrate2, and are therefore unlikely to be affected by noise caused by switching of the semiconductor chips4aand4b. Furthermore, according to the present embodiment, the thermistor6a(6b) is kept further away from the semiconductor chip4a(4b) than in the semiconductor device A1. Accordingly, the thermistors6aand6bare less affected by noise caused by switching of the semiconductor chips4aand4b.

FIG.11is a diagram for illustrating a semiconductor device A3according to the third embodiment of the present disclosure.FIG.11is a plan view of the semiconductor device A3and corresponds toFIG.3.FIG.11shows the sealing resin8in a transparent manner, and indicates the outer shape of the sealing resin8with imaginary lines (dash-double dot lines), asFIG.3does. The semiconductor device A3of the present embodiment is different from the first embodiment in the positions at which the semiconductor chips4and the protective elements9are arranged.

In the semiconductor device A3according to the present embodiment, the positions at which the semiconductor chip4aand the protective element9aare arranged are switched, and the positions at which the semiconductor chip4band the protective element9bare arranged are switched. That is, the protective element9ais arranged on the lead11on the other side in the y direction (upper side inFIG.11) of the semiconductor chip4a, and the protective element9bis arranged on the lead12on the other side in the y direction of the semiconductor chip4b. That is, the thermistor6ais arranged on the opposite side to the semiconductor chip4awith respect to the protective element9a, and the thermistor6bis arranged on the opposite side to the semiconductor chip4bwith respect to the protective element9b.

In the present embodiment as well, the thermistor6ais arranged adjacent to the mounting portion111of the lead11on which the semiconductor chip4ais mounted, and detects the temperature of the semiconductor chip4a. The thermistor6bis arranged adjacent to the mounting portion121of the lead12on which the semiconductor chip4bis mounted, and detects the temperature of the semiconductor chip4b. Accordingly, the temperatures can be separately detected, and thermal runaway can therefore be suppressed. The thermistors6aand6bare mounted on the substrate obverse surface21of the substrate2, and are therefore unlikely to be affected by noise caused by switching of the semiconductor chips4aand4b. Furthermore, according to the present embodiment, the thermistor6a(6b) is kept further away from the semiconductor chip4a(4b) than in the semiconductor device A1. Accordingly, the thermistors6aand6bare less affected by noise caused by switching of the semiconductor chips4aand4b.

FIG.12is a diagram for illustrating a semiconductor device A4according to the fourth embodiment of the present disclosure.FIG.12is a plan view of the semiconductor device A4and corresponds toFIG.3.FIG.12shows the sealing resin8in a transparent manner, and indicates the outer shape of the sealing resin8with imaginary lines (dash-double dot lines), asFIG.3does. The semiconductor device A4of the present embodiment is different from the first embodiment in that a control device50having one control chip5cis provided instead of the control device50(control chip5a) and the control chip5b.

The control chip5cgenerates a drive signal for the semiconductor chip4aand a drive signal for the semiconductor chip4b, and outputs the generated signals to the respective semiconductor chips. In the present embodiment, the control chip5cconstitutes the control device50together with a die pad and a plurality of wires (not shown), a plurality of leads53, and a resin54. The leads53are arranged on both ends in the x direction of the resin54, spaced apart from each other in the y direction. The leads53extend in the x direction, and a part of each lead53protrudes from one of the two side faces in the x direction of the resin54. The portion of each lead53that protrudes from the resin54is conductively bonded to a corresponding pad31of the conductive portion3. In the present embodiment, the control device50is an SOP package. Note that the package type of the control device50is not specifically limited. Note that the control chip5cmay alternatively be arranged as-is on the substrate obverse surface21without constituting the control device50.

The semiconductor device A4according to the fourth embodiment employs the control device50having the control chip5c, and is therefore different from the semiconductor device A1in the arrangement of the passive elements6and the arrangement and the shape of the conductive portion3. In addition, the shapes of the leads13and14and the shapes and the arrangement of the leads15aand15bare also different.

In the present embodiment as well, the thermistor6ais arranged adjacent to the mounting portion111of the lead11on which the semiconductor chip4ais mounted, and detects the temperature of the semiconductor chip4a. The thermistor6bis arranged adjacent to the mounting portion121of the lead12on which the semiconductor chip4bis mounted, and detects the temperature of the semiconductor chip4b. Accordingly, the temperatures can be separately detected, and thermal runaway can therefore be suppressed. The thermistors6aand6bare mounted on the substrate obverse surface21of the substrate2, and are therefore unlikely to be affected by noise caused by switching of the semiconductor chips4aand4b.

FIG.13is a diagram for illustrating a semiconductor device A5according to the fifth embodiment of the present disclosure.FIG.13is a plan view of the semiconductor device A5, with the sealing resin8shown in a transparent manner. Note thatFIG.13shows the outer shape of the sealing resin8with imaginary lines (dash-double dot lines). The semiconductor device A5of the present embodiment is different from the first embodiment in that the semiconductor device A5includes four semiconductor chips4ato4d.

Compared with the semiconductor device A1, the semiconductor device A5according to the present embodiment further includes leads16to19, semiconductor chips4cand4d, and thermistors6cand6d. The semiconductor device A5also includes two control chips5caccording to the third embodiment. The leads16and17are the same as the leads11and12. The leads18and19are the same as the leads13and14. The semiconductor chips4cand4dare the same as the semiconductor chips4aand4b. The semiconductor chip4cis mounted on the lead16, and is connected to the lead18by a wire71. The semiconductor chip4dis mounted on the lead17, and is connected to the lead19by a wire71. One of the control chips5cgenerates a drive signal for the semiconductor chip4aand a drive signal for the semiconductor chip4band outputs the generated drive signals to the respective semiconductor chips to control the drive of the semiconductor chips4aand4b. The other one of the control chips5cgenerates a drive signal for the semiconductor chip4cand a drive signal for the semiconductor chip4dand outputs the generated drive signals to the respective semiconductor chips to control the drive of the semiconductor chips4cand4d.

The thermistors6cand6dare the same as the thermistors6aand6b. The thermistor6cis arranged adjacent to a mounting portion of the lead16on which the semiconductor chip4cis mounted, and detects the temperature of the semiconductor chip4c. The thermistor6dis arranged adjacent to a mounting portion of the lead17on which the semiconductor chip4dis mounted, and detects the temperature of the semiconductor chip4d. That is, the semiconductor device A5has four semiconductor chips, and therefore includes four thermistors for detecting the temperatures of the respective semiconductor chips.

According to the present embodiment, the thermistor6ais arranged adjacent to the mounting portion111of the lead11on which the semiconductor chip4ais mounted, and detects the temperature of the semiconductor chip4a. The thermistor6bis arranged adjacent to the mounting portion121of the lead12on which the semiconductor chip4bis mounted, and detects the temperature of the semiconductor chip4b. The thermistor6cis arranged adjacent to the mounting portion of the lead16on which the semiconductor chip4cis mounted, and detects the temperature of the semiconductor chip4c. The thermistor6dis arranged adjacent to the mounting portion of the lead17on which the semiconductor chip4dis mounted, and detects the temperature of the semiconductor chip4d. Accordingly, the temperatures can be separately detected, and thermal runaway can therefore be suppressed. The thermistors6ato6dare mounted on the substrate obverse surface21of the substrate2, and are therefore unlikely to be affected by noise caused by switching of the semiconductor chips4ato4d.

Note that the present embodiment has described the case where four semiconductor chips are provided, whereas the first to fourth embodiments have described the case where two semiconductor chips are provided. However, this need not be the case. The number of semiconductor chips may be three, or may be five or more. The number of thermistors may be determined in accordance with the number of semiconductor chips. Further, the number of thermistors may be greater than the number of semiconductor chips.

FIG.14is a diagram for illustrating a semiconductor device A6according to the sixth embodiment of the present disclosure.FIG.14is a plan view of the semiconductor device A6, with the sealing resin8shown in a transparent manner. Note thatFIG.14shows the outer shape of the sealing resin8with imaginary lines (dash-double dot lines). The semiconductor device A6of the present embodiment is different from the first embodiment in that the semiconductor chips4aand4bare not mounted on the leads1but are arranged on the conductive portion3.

In the semiconductor device A6according to the present embodiment, the conductive portion3further includes a first conductive portion33and a second conductive portion34. The first conductive portion33is spaced apart from the second conductive portion34. The first conductive portion33includes a mounting portion33aand an extended portion33b. The semiconductor chip4ais mounted on the mounting portion33a. The semiconductor chip4ais bonded to the mounting portion33aby a conductive bonding material (not shown), with the element reverse surface42facing toward the mounting portion33a. Thus, the drain electrode45of the semiconductor chip4ais conductively connected to the mounting portion33aby the conductive bonding material. The extended portion33bis a portion extending from the mounting portion33atoward the thermistor6ain the y direction. That is, the thermistor6ais arranged close to a leading end of the extended portion33b. The thermistor6ais arranged insulated from the first conductive portion33. Note the first conductive portion33need not include the extended portion33b. In this case, the thermistor6amay be arranged adjacent to the mounting portion33a.

Similarly, the second conductive portion34includes a mounting portion34aand an extended portion34b. The semiconductor chip4bis mounted on the mounting portion34a. The semiconductor chip4bis bonded to the mounting portion34aby a conductive bonding material (not shown), with the element reverse surface42toward the mounting portion34a. Thus, the drain electrode45of the semiconductor chip4bis conductively connected to the mounting portion34aby the conductive bonding material. The extended portion34bis a portion extending from the mounting portion34atoward the thermistor6bin the y direction. That is, the thermistor6bis arranged close to a leading end of the extended portion34b. The thermistor6bis arranged, insulated from the second conductive portion34. Note the second conductive portion34need not include the extended portion34b. In this case, the thermistor6bmay be arranged adjacent to the mounting portion34a.

The conductive portion3further includes pads31f,31g,31h, and31i, and interconnects32cand32d. The lead11is conductively bonded to the pad31f, and the lead12is conductively bonded to the pad31g. The lead13is conductively bonded to the pad31h, and is conductively connected to the source electrode43of the semiconductor chip4aby wires71. The lead14is conductively bonded to the pad31i, and is conductively connected to the source electrode43of the semiconductor chip4bby wires71. The interconnect32cis connected to the first conductive portion33and the pad31fand serves as a conduction path between the first conduction portion33and the pad31f. The interconnect32dis connected to the second conductive portion34and the pad31gand serves as a conduction path between the second conductive portion34and the pad31g.

According to the present embodiment, the thermistor6ais arranged adjacent to the extended portion33bextending from the mounting portion33aof the first conductive portion33on which the semiconductor chip4ais mounted, and detects the temperature of the semiconductor chip4a. The thermistor6bis arranged adjacent to the extended portion34bextending from the mounting portion34aof the second conductive portion34on which the semiconductor chip4bis mounted, and detects the temperature of the semiconductor chip4b. Accordingly, the temperatures can be separately detected, and thermal runaway can therefore be suppressed. The thermistors6aand6bare mounted on the substrate obverse surface21of the substrate2, and are therefore unlikely to be affected by noise caused by switching of the semiconductor chips4aand4b.

The first to sixth embodiments have described the case where the semiconductor devices A1to A6are IPMs, but this need not be the case. The semiconductor device according to the present disclosure may be any semiconductor device other than an IPM.

The semiconductor device according to the present disclosure is not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present may be freely designed and changed in various manners. The present disclosure includes embodiments described in the following clauses.

A semiconductor device comprising:

a substrate including a substrate obverse surface and a substrate reverse surface that face opposite sides in a thickness direction;

a conductive portion formed on the substrate obverse surface;

a sealing resin covering at least a part of the substrate and an entirety of the conductive portion;

a plurality of semiconductor chips disposed on the substrate obverse surface; and

a plurality of temperature detection elements disposed on the substrate obverse surface, wherein the number of the temperature detection elements is equal to or greater than the number of the semiconductor chips.

The semiconductor device described in Clause 1, wherein the plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip,

the plurality of temperature detection elements include a first temperature detection element and a second temperature detection element,

the first temperature detection element is disposed at a position closer to the first semiconductor chip than the second temperature detection element is, and

the second temperature detection element is disposed at a position closer to the second semiconductor chip than the first temperature detection element is.

The semiconductor device described in Clause 2, further including a first lead and a second lead that are spaced apart from each other on the substrate obverse surface and have a higher thermal conductivity than that of the substrate,

wherein the first semiconductor chip is disposed on the first lead, and

the second semiconductor chip is disposed on the second lead.

The semiconductor device according to Clause 3, wherein the first temperature detection element is adjacent to the first lead and insulated from the first lead, and

the second temperature detection element is adjacent to the second lead and insulated from the second lead.

The semiconductor device according to Clause 4, further comprising an electronic component disposed on the first lead,

wherein the first temperature detection element is disposed opposite to the first semiconductor chip with respect to the element component.

The semiconductor device according to Clause 4 or 5, wherein the first lead includes a mounting portion on which the first semiconductor chip is mounted, and an extended portion extending from the mounting portion, and

the first temperature detection element is close to a leading end of the extended portion.

The semiconductor device according to any one of Clauses 3 to 6, further comprising a bonding portion formed on the substrate obverse surface and including a same conductive material as the conductive portion,

wherein the first lead and the second lead are bonded to the bonding portion via a bonding material.

The semiconductor device according to any one of Clauses 3 to 7, wherein a part of the first lead and a part of the second lead are covered by the sealing resin, and another part of the first lead and another part of the second lead are exposed from the sealing resin.

The semiconductor device according to any one of Clauses 3 to 8, further comprising a control lead spaced apart from the first lead and the second lead and bonded to the conductive portion via a conductive bonding material,

wherein a part of the control lead is covered by the sealing resin and another part of the control lead is exposed from the sealing resin.

The semiconductor device according to Clause 2, wherein the conductive portion includes a first conductive portion and a second conductive portion that are spaced apart from each other,

the first semiconductor chip is disposed on the first conductive portion,

the second semiconductor chip is disposed on the second conductive portion,

the first temperature detection element is adjacent to the first conductive portion and insulated from the first conductive portion, and

the second temperature detection element is adjacent to the second conductive portion and insulated from the second conductive portion.

The semiconductor device according to Clause 10, wherein the first conductive portion includes a mounting portion on which the first semiconductor chip is mounted, and an extended portion extending from the mounting portion, and

the first temperature detection element is close to a leading end of the extended portion.

The semiconductor device according to any one of Clauses 1 to 11, wherein the temperature detection elements comprise thermistors.

The semiconductor device according to any one of Clauses 1 to 11, wherein the temperature detection elements comprise semiconductor temperature sensors.

The semiconductor device according to any one of Clauses 1 to 13, wherein the number of semiconductor chips and the number of temperature detection elements are each two.

The semiconductor device according to any one of Clauses 1 to 13, wherein the number of semiconductor chips and the number of temperature detection elements are each four.

The semiconductor device according to any one of Clauses 1 to 15, wherein the semiconductor chips comprise power transistors for controlling electric power.

The semiconductor device according to any one of Clauses 1 to 16, wherein each of the semiconductor chips includes:

a chip obverse surface and a chip reverse surface that face opposite sides in the thickness direction;

an obverse-surface electrode disposed on the chip obverse surface; and

a reverse-surface electrode disposed on the chip reverse surface.

The semiconductor device according to any one of Clauses 1 to 17, wherein the substrate reverse surface is exposed from the sealing resin.

The semiconductor device according to any one of Clauses 1 to 18, wherein the substrate is made of ceramic.