On-chip sensor hub, and mobile device and multi-sensor management method therefor

An on-chip sensor hub fabricated on a chip with a main processor of a mobile device, and the mobile device, and a method for multi-sensor management on the mobile device. An on-chip sensor hub includes a co-processor and uses an inter-process communication interface. The co-processor and main processor of the mobile device are fabricated on the same chip and communicate with each other via the inter-process communication interface. The co-processor controls a plurality of sensors in the mobile device in accordance with requests issued from the main processor. The co-processor further collects and manages sensor data from the sensors to be processed by the main processor.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of China Patent Application No. 201510342546.X, filed on Jun. 19, 2015, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an on-chip sensor hub and mobile devices using the same and multi-sensor management methods therefor.

Description of the Related Art

A mobile device usually has several sensors. For controlling the sensors and collecting and managing the sensor data, there is a sensor hub on the mobile device. Lowering the cost and power consumption of the sensor hub is the key design point.

BRIEF SUMMARY OF THE INVENTION

In the disclosure, a sensor hub and a main processor of a mobile device are fabricated on a single chip. An on-chip sensor hub based on single-chip integration is shown.

An on-chip sensor hub in accordance with an exemplary embodiment of the disclosure comprises a co-processor and an IPC interface (an inter-process communication interface). The co-processor and a main processor of a mobile device are fabricated on a chip. The co-processor and the main processor communicate within the chip through the IPC interface. Based on the requests issued from the main processor, the co-processor controls a plurality of sensors of the mobile device and collects and manages sensor data from the plurality of sensors to be processed by the main processor.

An on-chip sensor hub may use a volatile memory module that provides multiple divisions powered separately (i.e. in a distributed architecture). Thus, power consumption is reduced.

In another exemplary embodiment, the on-chip sensor hub may adjust the operation clock of the co-processor to reduce power consumption.

In another exemplary embodiment, the on-chip sensor hub may perform the co-processor with a clock gate control to reduce power consumption.

In another exemplary embodiment, the on-chip sensor hub may operate the clock-gate-controlled co-processor at low operating voltages when the main processor is in the power-saving state.

In another exemplary embodiment, a mobile device using the on-chip sensor hub is shown, which further includes a main processor integrated with the on-chip sensor hub and a plurality of sensors. Through the on-chip sensor hub, the main processor controls the sensors and collects and manages sensor data from the sensors.

A multi-sensor management method for a mobile device in accordance with an exemplary embodiment of the disclosure comprises: providing a co-processor, the co-processor is fabricated with a main processor of a mobile device on a chip; and building communications between the co-processor and the main chip in the chip via the inter-process interface. Based on the requests issued from the main processor, the co-processor controls a plurality of sensors of the mobile device and collects and manages sensor data from the plurality of sensors to be processed by the main processor.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1depicts a mobile device100in accordance with an exemplary embodiment of the disclosure, which includes a chip102, a plurality of sensors S1, S2, S3, S4and so on, and a power management integrated circuit PMIC. As shown, the main processor104of the mobile device100and an on-chip sensor hub106are integrated in the chip102based on single-chip integration. The on-chip sensor hub106includes a co-processor108, an inter-process communication interface IPC and a non-volatile memory module110in a distributed architecture.

The inter-process communication interface IPC is provided for establishing communication between the co-processor108and the main processor104within the chip102. In this manner, the communication speed between the main processor104and the on-chip sensor hub106is much faster than those using a conventional design. In a conventional design, a sensor hub is external to the chip of the main processor. The communication between the on-chip sensor hub106and the sensors S1, S2, S3, S4. . . of the mobile device100is based on an inter-integrated circuit bus I2C. The sensors S1, S2, S3, S4. . . may output an interrupt signal IRQ to the on-chip sensor hub106. The requests output from the main processor104are conveyed to the co-processor108through the inter-process communication interface IPC and, accordingly, the co-processor108controls the sensors S1, S2, S3, S4. . . through the inter-integrated circuit bus I2C. The sensor data detected by the sensors S1, S2, S3, S4. . . is conveyed to the co-processor108through the inter-integrated circuit bus I2C. The co-processor108collects and manages the sensor data and, through the inter-process communication interface IPC, the collected and managed sensor data is conveyed to the main processor104to be processed by the main processor104. The co-processor108further performs task scheduling, power management, and sensor data fusion and calibration and management on the sensors S1, S2, S3, S4. . . . The co-processor108works as a sensor driver of the sensors S1, S2, S3, S4. . . .

In the exemplary embodiment ofFIG. 1, the distributed non-volatile memory module110in a distributed architecture is implemented by a distributed SRAM. The distributed SRAM provides a memory space SRAM1and a memory space SRAM2which are powered separately. The memory space SRAM1and the memory space SRAM2are allocated for different operations that the co-processor108performs on the sensors S1, S2, S3, S4. . . , examples of which are discussed below. The memory space SRAM1may correspond to the normal operations that the co-processor108performs on the sensors S1, S2, S3, S4. . . . The normal operations are performed on the sensors in normal states, including intelligent waking up procedures, activity monitoring, interrupt request (IRQ) detection, and so on. The memory space SRAM2may correspond to the infrequent operations that the co-processor108performs on the sensors S1, S2, S3, S4. . . . The infrequent operations are performed on the sensors for particular and infrequent scenarios. The co-processor108performs an analysis on the requests issued from the main processor104. When the infrequent operations are not performed, the co-processor108switches the memory space SRAM2into a low-power data retention state without affecting the power of the memory space SRAM1. In the low-power data retention state, the memory space SRAM1retains data in a power-saving mode which results in a significant energy savings. In an exemplary embodiment, the size of the memory space SRAM1is much smaller than the size of the memory space SRAM2. When the memory space SRAM2is switched to the low-power data retention state, the memory space SRAM1with a small size only consumes a limited amount of power.

In an exemplary embodiment, the main processor104and the on-chip sensor hub106are fabricated in different power areas of the chip102. For example, the main processor104may be fabricated in an on/off voltage domain and the on-chip sensor hub106may be fabricated in an always-on voltage domain. The power management of the main processor104may be separated from the power management of the on-chip sensor hub106.

The on-chip sensor hub106may adjust the operation clock of the co-processor108to reduce power consumption in a technique named clock switching.

The on-chip sensor hub106may operate the co-processor108with clock gating to reduce power consumption. Furthermore, when the main processor104is in a power-saving state (e.g., only the background detection is running), the co-processor108with clock gating is driven by the on-chip sensor hub106to operate at low voltages and thereby reduce power consumption. The power management integrated circuit PMIC may be switched by the co-processor108to operate the co-processor108at low voltages (e.g. down to 0.7V).

FIG. 2shows the management method for the multiple sensors S1, S2, S3, S4. . . of the mobile device100.

The control requests for the sensors (e.g. turning on or off a sensor) and data requests issued by the main processor104are conveyed to the co-processor108through the inter-process communication interface IPC, and the co-processor108thereby executes the sensor driver202to operate the sensors S1, S2, S3, S4. . . through the inter-integrated circuit bus I2C and to collect sensor data and return the sensor data to the main processor104.

The co-processor108analyzes further the tasks of the sensors S1, S2, S3, S4. . . (i.e. the task analysis204) based on the requests issued from the main processor104, to properly switch the memory space SRAM2to the low-power data retention state independently from the memory space SRAM1. For example, when the memory space SRAM1is allocated for normal operations and the memory space SRAM2is allocated for infrequent operations, the memory space SRAM2is usually operated in the low-power data retention state.

Based on the task analysis204, the co-processor108may further change the operation clock of the co-processor108based on the workload of the sensors S1, S2, S3, S4. . . and power consumption is reduced by switching the operation clock.

Based on the task analysis204, the co-processor108may operate the co-processor108with clock gating when the sensors S1, S2, S3, S4. . . are idle (e.g., in a task idle state). Furthermore, the co-processor108may perform a further low-voltage judgment206to determine whether the main processor104is in a power-saving state. When the main processor104is in a power-saving state (222), the low-voltage operation condition is satisfied, the co-processor108is switched to low operating voltages, and the power-gating technique is turned on (state208). When the main processor104is not in a power-saving state (224, e.g., playing video and audio), the low-voltage operation condition is not satisfied and the co-processor108is operated with clock gating (state210) without being switched to low operating voltages.

As for a power recovery process, one of the sensors S1, S2, S3, S4. . . may output an interrupt signal IRQ, or a timer212may periodically output an interrupt signal IRQ. The co-processor108may perform a self-examination to check whether the co-processor108itself is operating at low operating voltages (referring to the low voltage examination214). When being operated at low operating voltages, the co-processor108performs a power recovery process216to leave the low voltage operation and to process the interrupt signal IRQ. Otherwise, the co-processor108process the received interrupt signal IRQ without performing the power recovery process216.

FIG. 3is a flowchart depicting a power management method for the on-chip sensor hub106in accordance with an exemplary embodiment of the disclosure. In step S302, based on a task analysis (204), the co-processor108determines whether a power-saving requirement for the distributed volatile memory module is reached, the distributed volatile memory stated above comprises the memory space SRAM1and the memory space SRAM2. If yes, the memory space SRAM2is switched to the low-power data retention state independently from the memory space SRAM1(S304) and then the co-processor108keeps doing the task analysis, and step S306is performed to determine whether to keep the power-saving state of the memory space SRAM2. If not, step S308is performed and the memory space SRAM2leaves the low-power data retention state and returns to normal operations.

FIG. 4is a flowchart depicting a power management method for the on-chip sensor hub106in accordance with another exemplary embodiment of the disclosure. In step S312, the operation clock of the co-processor108is switched based on task workload. In step S314, the sensors S1, S2, S3, S4. . . are monitored to recognize the task load. When there is no task load, step S316is performed for a low-voltage judgment (206). When a low-voltage operation condition is satisfied, steps S318and S320are performed. In step S318, the power management integrated circuit PMIC is controlled to switch the co-processor108to low operating voltages. In step S320, the co-processor108is operated with clock gating. When the low-voltage operation condition is not satisfied, step S320is performed when S318is bypassed. After step S320, step S322is performed. In step S322, the co-processor108waits for the interrupt signal IRQ from the timer212or any of the sensors S1, S2, S3, S4. . . to leave the power-saving state.

Techniques for sensor management of mobile device based on the aforementioned concept are within the scope of the invention. Multi-sensor management methods for mobile device based on the aforementioned concept are also developed.