Long wavelength VCSEL bottom mirror

A vertical cavity surface emitting laser having an InP substrate and a lower mirror stack comprised of a plurality of alternating layers of AlPSb and GaPSb over the InP substrate. An InP spacer is over the lower mirror stack. An active region is over the InP spacer, and a tunnel junction is over the active region. Then a top mirror structure comprised of a low-temperature formed first GaAs buffer layer, a high-temperature formed second GaAs seed layer, an insulating structure having an opening, and a GaAs/Al(Ga)As mirror stack that is grown by lateral epitaxial overgrowth.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to vertical cavity surface emitting lasers. More specifically, it relates to bottom mirrors used in vertical cavity surface emitting lasers.

2. Discussion of the Related Art

Vertical cavity surface emitting lasers (VCSELs) represent a relatively new class of semiconductor lasers. While there are many variations of VCSELs, one common characteristic is that they emit light perpendicular to a wafer's surface. Advantageously, VCSELs can be formed from a wide range of material systems to produce specific characteristics.

VCSELs include semiconductor active regions, which can be fabricated from a wide range of material systems, distributed Bragg reflector (DBR) mirrors, current confinement structures, substrates, and contacts. Because of their complicated structure, and because of their material requirements, VCSELs are usually grown using metal-organic chemical vapor deposition (MOCVD).

FIG. 1illustrates a typical VCSEL10. As shown, an n-doped gallium arsenide (GaAs) substrate12has an n-type electrical contact14. An n-doped lower mirror stack16(a DBR) is on the GaAs substrate12, and an n-type graded-index lower spacer18is disposed over the lower mirror stack16. An active region20, usually having a number of quantum wells, is formed over the lower spacer18. A p-type graded-index top spacer22is disposed over the active region20, and a p-type top mirror stack24(another DBR) is disposed over the top spacer22. Over the top mirror stack24is a p-type conduction layer9, a p-type cap layer8, and a p-type electrical contact26.

Still referring toFIG. 1, the lower spacer18and the top spacer22separate the lower mirror stack16from the top mirror stack24such that an optical cavity is formed. As the optical cavity is resonant at specific wavelengths, the mirror separation is controlled to resonant at a predetermined wavelength (or at a multiple thereof. At least part of the top mirror stack24includes an insulating region40that provides current confinement. The insulating region40is usually formed either by implanting protons into the top mirror stack24or by forming an oxide layer. In any event, the insulating region40defines a conductive annular central opening42that forms an electrically conductive path though the insulating region40.

In operation, an external bias causes an electrical current21to flow from the p-type electrical contact26toward the n-type electrical contact14. The insulating region40and the conductive central opening42confine the current21such that the current flows through the conductive central opening42and into the active region20. Some of the electrons in the current21are converted into photons in the active region20. Those photons bounce back and forth (resonate) between the lower mirror stack16and the top mirror stack24. While the lower mirror stack16and the top mirror stack24are very good reflectors, some of the photons leak out as light23that travels along an optical path. Still referring toFIG. 1, the light23passes through the p-type conduction layer9, through the p-type cap layer8, through an aperture30in the p-type electrical contact26, and out of the surface of the vertical cavity surface emitting laser10.

It should be understood thatFIG. 1illustrates a typical VCSEL, and that numerous variations are possible. For example, the dopings can be changed (say, by providing a p-type substrate), different material systems can be used, operational details can be tuned for maximum performance, and additional structures, such as tunnel junctions, can be added. Furthermore, with long wavelengths it is often beneficial to insert a reversed biased n++/p++ tunnel junction between the top spacer22and the active region20, and to change the doping type of the top structures to n-type. This is because p-doped materials absorb more light than n-doped materials, and with longer wavelengths the optical gain become more critical. The tunnel junction converts electrons into holes, which are then injected into the active region.

While generally successful, VCSELs have problems. For example, a major problem in realizing commercial quality long wavelength VCSELs is the available mirror materials. Long wavelength VCSELs are often based on InP material systems. For proper lattice matching, an InP-based VCSEL usually uses InP/InGaAsP or AlInAs/AlInGaAs mirrors. However, because those materials have relatively low refractive index contrasts, 40-50 mirror pairs are typically needed to achieve the required high reflectivity. Growing that number of mirror pairs takes a long time, which increases the production costs.

Other mirror material systems have been tried. For example, “Metamorphic DBR and tunnel-Junction Injection: A CW RT Monolithic Long-Wavelength VCSEL,” IEEE Journal of Selected topics In Quantum Electronics, vol. 5, no. 3, May/June 1999, describes an InP-InGaAsP DBR, a GaAlAsSb-AlAsSb DBR, and a GaAlInSb-AlAsSb DBR. Furthermore, that article describes using a reversed biased n++/p++ tunnel junction for injecting current into the active layer. While such mirror material systems are advantageous, their lattice match, refractive index contrast, and thermal conductivity characteristics are not optimal. Additionally, GaAs/Al(Ga) is still considered to form the best distributed Bragg reflector mirrors because of its high refractive index contrast, high thermal conductivity, and the feasibility of using oxidation to enable the formation of oxide insulating regions40. Thus, new long wavelength VCSELS would be beneficial. Even more beneficial would be new bottom mirror systems for long wavelength VCSELS. Still more beneficial would be new bottom mirror systems that enable GaAs/Al(Ga) top mirror systems.

SUMMARY OF THE INVENTION

Accordingly, the principles of the present invention are directed to new mirror systems for long wavelength VCSELS. Those principles specifically provide for new bottom DBR mirror material systems, and VCSELs that use such new DBR bottom mirror systems. Beneficially, the principles of the present invention provide for VCSELS that incorporate new bottom mirror systems and that use GaAs/Al(Ga) top mirror DBRs.

A bottom mirror according to one aspect of the present invention provides for AlPSb/GaPSb DBR mirrors on an InP substrate, beneficially n-doped. Then, an n-doped bottom InP spacer is grown on the AlPSb/GaPSb DBR. Beneficially, an active region having a plurality of quantum wells is then grown on the n-doped InP spacer. Beneficially, a reversed biased tunnel junction is disposed over the active region. An n-doped top InP spacer is beneficially grown on the tunnel junction. Also beneficially, an n-doped GaAs/Al(Ga)As top DBR is grown on the n-doped top InP spacer.

Preferably, the GaAs/Al(Ga)As top DBR is grown by a multi-step process using MOCVD. First, the growth temperature is set to 400-450° C. Then, a 20-40 nanometer thick low temperature GaAs layer is grown on the n-doped top InP spacer. After that, the temperature is increased to around 600° C. A high temperature GaAs seed layer, about 100 nm thick, is then grown on the low temperature GaAs layer. Then an insulation layer comprised of SiO2or Si2N4is formed on the GaAs seed layer. The insulation layer is patterned to form an opening. A high temperature GaAs layer is then grown on the GaAs seed layer, followed by a GaAs/Al(Ga)As top DBR. The high temperature GaAs layer and the GaAs/Al(Ga)As mirror are beneficially grown using lateral epitaxial overgrowth.

According to another aspect of the present invention, a bottom AlGaInAs/AlInAs DBR is grown on an n-doped InP substrate. Then, an n-doped bottom InP spacer is grown on the grown on the AlGalnAs/AlInAs DDR. Beneficially, an active region having a plurality of quantum wells is then grown on the n-doped InP spacer, followed by a reversed biased n++/p++tunnel junction over the active region. An n-doped top InP spacer is beneficially grown on the tunnel junction. Also beneficially, an n-doped GaAs/Al(Ga)As top DER is grown on the n-doped top InP spacer.

Preferably, the GaAs/Al(Ga)As top DBR is grown by a multi-step process using MOCVD. First, the growth temperature is set to 400-450° C. Then, a 20-40 nanometer thick low temperature GaAs layer is grown on the n-doped top InP spacer. After that, the temperature is increased to around 600° C. A high temperature GaAs seed layer, about 100 nm thick, is then grown on the low temperature GaAs layer. Then, an insulation layer comprised of SiO2or Si2N4is formed on the GaAs seed layer. That insulation layer is then patterned to form an opening. A high temperature GaAs layer is then grown on the GaAs seed layer. Then, a GaAs/Al(Ga)As top DBR is grown on the high temperature GaAs layer. The GaAs layer and the GaAs/Al(Ga)As mirror are beneficially grown using lateral epitaxial overgrowth.

Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from that description, or may be learned by practice of the invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The principles of the present invention are incorporated in a first embodiment VCSEL having a bottom AlPSb/GaPSb DBR mirror grown on an InP substrate. An example of such a VCSEL is the VCSEL100illustrated in FIG.2.

As shown inFIG. 2, the VCSEL100includes an n-doped InP substrate112having an n-type electrical contact (not shown for clarity). Over the InP substrate112is an n-doped lower mirror stack116(a DBR) comprised of a plurality of alternating layers of AlPSb/GaPSb. Over the lower mirror stack116is an n-doped InP spacer118. The lower mirror stack116is beneficially grown on the InP substrate using TMAl, TMSb, and PH3in an MOCVD process. Then, the InP spacer118is grown, also using MOCVD. An active region120comprised of P-N junction structures and a large number of quantum wells is then formed over the InP spacer118. The composition of the active region120is beneficially AlInGaAs or InGaAsP.

Over the active region120is a tunnel junction122comprised of a reverse biased n++/p++ junction. Beneficially, the tunnel junction includes a p-layer comprised of MOCVD-grown GaAs(1-x)Sbx. During MOVCD, TMGa (or TEGa), TMSb, and AsH3(or TBAs) are beneficially used to produce the GaAs(1-x)Sbxlayer. Beneficially, that layer's solid composition is controlled by controlling the ratio of As to Sb. The MOCVD growth temperature is between 500° C. and 650° C. Doping is beneficially performed using CCl4or CBr4such that the resulting p-doping is greater 1×1019cm−3. In practice, a p-doping greater than 5×1019cm−3is beneficial. It should be noted that the GaAs(1-x)Sbxlayer can have a doping as high as 1×1020cm−3without annealing. By setting x=0.5 a tunnel junction that is lattice matched to InP is produced (but GaAs(0.5)Sb0.5has a bandgap of 0.71 eV at 300K). An alternative is to set x=0.4, 0.3, or 0.23, which produce GaAs(1-x)Sbxlayers with bandgaps of 0.8 eV, 0.91 eV, or 1 eV, but which are not lattice matched to the InP active region120. At x=0.3, or 0.23 the strains respectively become 1.4% or 1.95%, which, while not ideal, are much better than the 3.55% strain of AlAs on InP.

The tunnel junction122further includes an n-doped layer of InP, AlInAs, or of a lower bandgap material such as AlInGaAs or InGaAsP. The n-doped layer should also be heavily doped (greater than 5×1019cm−3) and very thin (less than about 10 nanometers). For good lattice matching, the VCSEL100uses an InP n-type layer in the tunnel junction122.

Over the tunnel junction122is an n-type InP top spacer124. Then, a top mirror structure (which includes another DBR) is disposed over the top spacer124.

The top mirror structure is beneficially comprised of a low temperature grown GaAs buffer layer126over the top spacer124, a high temperature GaAs buffer layer128(which acts as a seed layer) over the GaAs buffer layer126, an insulating structure (beneficially comprised of SiO2)130over most of the GaAs buffer layer128, and a GaAs/Al(Ga)As mirror stack132over the insulating structure130. A shown, the insulating structure includes an opening131, which enables current flow through the VCSEL100.

The top mirror structure implements a device quality GaAs/Al(Ga)As mirror stack132over the top spacer124. In many applications, GaAs/Al(Ga)As is considered the best material for Bragg mirrors because of its high refractive index contrast (GaAs:AlAs=3.377:2.893), high thermal conductivity (GaAs:AlAs=0.46:0.8), and its oxidation potential. However, GaAs/Al(Ga)As is seriously lattice mismatched with InP. Thus, to produce a device-quality GaAs/Al(Ga)As mirror stack, MOCVD is used in a two-step process to form intermediate GaAs buffer layers.

FIG. 3illustrates the first step of the two-step process. A low temperature GaAs buffer layer126is formed over the InP spacer124. The low temperature GaAs buffer layer126is produced by adjusting the MOCVD growth temperature to about 400-450° C., and then MOCVD growing the low temperature GaAs buffer layer126to a thickness of about 20-40 nm.

Referring now toFIG. 4, after the low temperature GaAs buffer layer126is formed, the temperature is increased to around 600° C. Then, the high temperature GaAs buffer layer128is grown. The GaAs buffer layer128acts as a seed layer for subsequent growths.

Referring now toFIG. 5, after the GaAs buffer layer128is grown, a dielectric layer of SiO2(alternatively of Si3N4) is deposited and patterned to form the insulating structure130. To do so, the intermediate structure shown inFIG. 4is removed from the MOCVD reactor vessel. Then, a dielectric layer of SiO2(alternatively Si3N4) is deposited on the insulating structure130. Then, the deposited dielectric layer is patterned to produce the insulating structure130having the opening131. The insulating structure130provides a suitable surface for lateral epitaxial overgrowth. After the insulating structure130formed, the intermediate structure ofFIG. 5is inserted into the MOCVD reactor vessel. Referring once again toFIG. 2, the GaAs/Al(Ga)As mirror stack132is then grown by MOCVD. That mirror stack is produced by lateral epitaxial overgrowth from the GaAs buffer layer128through the opening131. The result is a high-quality mirror stack132having current confinement.

With the mirror stack132formed, an n-type conduction layer (similar to the p-type conduction layer9of FIG.1), an n-type GaAs cap layer (similar to the p-type GaAs cap layer8of FIG.1), and an n-type electrical contact (similar to the p-type electrical contact26ofFIG. 1) are produced.

An alternative embodiment VCSEL200that is in accord with the principles of the present invention is illustrated in FIG.6. The VCSEL200includes an n-doped InP substrate212having an n-type electrical contact (which is not shown for clarity). Over the InP substrate222is n-doped lower mirror stack216(a DBR) comprised of a plurality of alternating layers of AlGaInAs and AlInAs. Over the lower mirror stack216is an InP spacer218. The lower mirror stack216is beneficially grown on the InP substrate using TMAl, TMSb, and PH3in an MOCVD process. Then, the InP spacer218is grown, also using MOCVD.

An active region220comprised of P-N junction structures and a large number of quantum wells are then formed over the InP spacer218. The composition of the active region220is beneficially InP. Over the active region220is a tunnel junction222comprised of a reverse biased n++/p++ junction. Beneficially, the tunnel junction22is as described above (and thus includes a MOCVD-grown GaAs(1-x)Sbxlayer).

Over the tunnel junction222is an n-type InP top spacer224. Then, a top mirror structure (which includes another DBR) is disposed over the top spacer224. The top mirror structure is beneficially comprised of a low temperature GaAs buffer layer226over the top spacer224, a high temperature GaAs buffer layer228over the GaAs buffer layer226, an insulating structure (beneficially comprised of SiO2)130over most of the GaAs buffer layer228, and a GaAs/AI(Ga)As mirror stack232over the insulating structure230. Beneficially, the top mirror structure is fabricated in the same manner as the top mirror structure ofFIG. 2(as discussed with regard to FIGS.3-5).

With the mirror stack232formed, an n-type conduction layer (similar to the p-type conduction layer9of FIG.1), an n-type GaAs cap layer (similar to the p-type GaAs cap layer8of FIG.1), and an n-type electrical contact (similar to the p-type electrical contact26ofFIG. 1) are produced.

The VCSELs100and200have significant advantages over prior art long wavelength InP VCSELs. First, the two-step MOCVD process enables a device quality GaAs/Al(Ga)As top mirror to be used with an InP active region120and an InP top spacer124. Another advantage is that the tunnel junction122enables n-doped top layers to be used, which reduces optical absorption (which can be critically important in long wavelength VCSELs). Yet another advantage is the avoidance of InP/InGaAsP mirror stacks, which requires a large numbers of mirror pairs. Consequently, a reduction in mirror growth times and costs is possible. Furthermore, the mirrors stacks used in the VCSEL100and in the VCSEL200enable improved thermal performance. Still another advantage is the ease of forming current confinement in the top mirror structure, and the use of lateral epitaxial overgrowth to produce the top mirror. The overall result is VCSELs having improved performance, increased reliability, faster fabrication, and reduced cost.