Phase-locked/frequency-locked loop and phase/frequency comparator therefor

A phase/frequency comparator is described which includes two edge-triggered storage elements, each set by an edge of a reference frequency signal of a phase—or frequency-locked loop (PLL) and by an edge of an output frequency signal of the PLL. The storage elements are each reset by an output signal of a resetting logic unit, which is activated when both output signals of the storage elements are activated and then deactivated when the output signals are deactivated.

FIELD OF THE INVENTION

The invention relates to a stable digital phase/frequency comparator for a phase/frequency-locked loop having resetting logic of a new kind, which comparator is optimised for implementation by programmable logic modules (e.g. FPGA's).

BACKGROUND OF THE INVENTION

What are used to generate signals of exact frequency are generally called PLL circuits (PLL=phase-locked loop). In a PLL circuit, the frequency of a frequency-generating oscillator is set in such a way that it matches a preset reference frequency such that the phase shift between the output frequency of the frequency-generating oscillator and the reference frequency remains stable or constant. In principle, a distinction can be made between analogue and digital PLL circuits. In the case of digital PLL circuits, which are what will be further considered below, the digital implementation is generally confined to the phase/frequency comparator and to the frequency divider which may be implemented as an option.

The task of the phase/frequency comparator is to compare the frequency of an output-frequency signal from a frequency-generating oscillator in the PLL circuits with the frequency of a preset reference-frequency signal and, if there is a difference, to generate one or more correcting signals which correct the frequency of the output-frequency signal from the frequency-generating oscillator in the PLL circuit in the appropriate way. The way in which a phase/frequency comparator is implemented digitally is generally either in the form of an exclusive-OR gate, an edge-triggered JK flip-flop, or a phase/frequency detector using edge-triggered D flip-flops and resetting logic.

The phase/frequency detector using edge-triggered D flip-flops and resetting logic is a variant digital implementation for phase/frequency comparators that is widely employed because it makes the least demands on the input signals (the exclusive-OR gate requires symmetrical input signals, and the edge-triggered JK flip-flop requires input signals which are not subject to fading).

In the case of the phase/frequency detector using edge-triggered flip-flops and resetting logic, the correcting signal for correcting the frequency of the frequency-generating oscillator comprises, as is known from, for example, Roland E. Best, “Phase Locked Loops”, 3rd edition, McGraw Hill, 1997, ISBN 0-07-006051-7, pages 91-101, two signals, a first signal for the upward correction of the frequency of the frequency-generating oscillator in the event of a positive difference in frequency between the reference frequency and the output frequency, and a second signal for the downward correction of the frequency of the frequency-generating oscillator in the event of a negative difference in frequency between the reference frequency and the output frequency. These two correcting signals are generated by respective edge-triggered D flip-flops which are set by the reference-frequency signal and the output-frequency signal respectively. Because of the phase and frequency relationships which are possible between the reference-frequency signal and the output-frequency signal, there are a total of four possible states for the two D flip-flop outputs (00, 01, 10, 11). Because the last state (11) of the two flip-flop outputs makes no sense (frequency of frequency-generating oscillator to be corrected upward and downward simultaneously), if this state occurs the two flip-flops are reset by means of resetting logic. What is generally used for this purpose is an AND gate whose inputs are connected to the outputs of the two flip-flops and whose output is connected to the resetting inputs of the two flip-flops.

The phase/frequency comparator thus has an asynchronous structure employing feedback, whose behaviour in operation can be characterised as follows: in a phase/frequency detector using edge-triggered D flip-flops, plus resetting logic as above, in the event of a positive difference in frequency (reference frequency fdesired>output frequency factual) the output of the flip-flop which is set by the reference-frequency signal (signal: Correctupward) is set for longer, as a statistical mean, than the flip-flop which is set by the output-frequency signal (signal: Correctdownward). In the event of a negative difference in frequency (reference frequency fdesired<output frequency factual), the output of the flip-flop which is set by the output-frequency signal is set for longer, as a statistical mean, than the flip-flop which is set by the reference-frequency signal. These relationships are shown inFIGS. 1A to 1Dfor positive and negative differences in frequency fdesired-factualbetween the reference-frequency signal and the output-frequency signal and for positive and negative differences in phase φdesired-φactualbetween the two said signals (to make things clearer, the frequency and phase differences that are assumed to exist in the plots are extreme ones).

If a digital phase/frequency comparator of this kind is implemented with programmable logic modules (e.g. FPGA's PAL's, LCA's), the following problems may arise:

Under certain circumstances, the two edge-triggered D flip-flops may not be reset at exactly the same time. The reason for this may be different transit times for the resetting signals due to different lengths of conductor from the resetting logic to the resetting inputs of the edge-triggered D flip-flops, and different resetting times of the two edge-triggered D flip-flops. In the extreme case, an edge-triggered D flip-flop may not be reset at all because, due to appreciable differences in transit time and resetting time, the resetting signal for the edge-triggered D flip-flop which has not yet been reset may have been cancelled again even before the resetting process has been completed due to the resetting of the other edge-triggered D flip-flop. Generally speaking, it is relatively unlikely that circumstances of this kind, and particularly the extreme case which has been described, will occur but, in programmable logic modules, they cannot be ruled out if the placing of the individual logic units is unsatisfactory.

When programming the logic modules, there is generally only a limited amount the user can do to affect the transit times of the individual signals or the resetting times of the flip-flops, which means that if irregularities of this kind occur, the dynamic performance of the PLL circuit can no longer be accurately controlled. Hence there will no longer be a precise deterministic relationship between on the one hand the two correcting signals from the digital phase/frequency comparator and on the other hand the difference in frequency between the reference frequency and the output frequency. This will lead to undesirable jumps in frequency at the output of the frequency-generating oscillator of the PLL circuit and to drifts in phase between the reference frequency and the output frequency. These system deviations on the part of the phase/frequency-locked loop, which appreciably reduce the quality of the control performed by the PLL circuit, cannot generally be corrected and in the extreme case may cause instability on the part of the control loop.

SUMMARY OF THE INVENTION

A need exists therefore to provide, for a digital phase/frequency-locked loop, suitable resetting logic for the phase/frequency comparator, in which the resetting logic is constructed from edge-triggered storage devices (D flip-flops), in order to obtain deterministic and stable phase/frequency-locking in a digital implementation employing for example programmable logic modules, despite transit-time effects that may occur.

In accordance with one aspect of the invention, in order to obtain resetting processes which are reliable in a defined way for the two edge-triggered storage devices (e.g. D flip-flops), what is used to obtain the resetting signal from the output signals of the edge-triggered storage devices (D flip-flops) is not a static gate module but a digital storage device. What is used for this purpose is for example, preferably, an asynchronous level-triggered RS flip-flop which is only set when both outputs of the two first-mentioned edge-triggered storage devices (D flip-flops) have been set. The resetting signal for the two edge-triggered storage devices (D flip-flops) is only reset when both the edge-triggered storage devices (D flip-flops) have been reset. This ensures that the process of resetting the two edge-triggered storage devices (D flip-flops) comes to an end in a defined way.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The resetting logic according to an embodiment of the invention for a digital phase/frequency comparator will be described below by reference toFIGS. 2 to 5. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It is apparent, however, to one skilled in the art that the present invention may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the present invention.

FIG. 2is a schematic block diagram of a phase/frequency-locked loop (PLL)1. The loop1comprises a frequency divider2to whose input a reference-frequency signal3is applied. The frequency of the reference-frequency signal is divided in the frequency divider2by a factor M. The reference-frequency signal4, of a frequency obtained by dividing by the factor M, is emitted from the output of the frequency divider2. The phase/frequency-locked loop1has a second frequency divider5which divides the frequency of the output-frequency signal6which is applied to its input by a factor N. The output-frequency signal7, of a frequency obtained by dividing by the factor N, is emitted from the output of the frequency divider5. By selecting M and N in a suitable way, it must be ensured that the reference-frequency signal3whose frequency has been divided by the factor M, and the output-frequency signal6whose frequency has been divided by the factor N, are of the same frequency when the phase/frequency-locked loop1is in a steady-state (settled) condition. Both the frequency divider2and the frequency divider5are optional functional units within the phase/frequency-locked loop.

The reference-frequency signal4and the output-frequency signal7, whose frequencies may have been divided, as an option, in frequency dividers2and51respectively, are fed to respective inputs of a phase/frequency comparator8. In the phase/frequency comparator8, the two frequencies or phases of the reference-frequency signal4and the output-frequency signal7are compared. The comparison produces a correcting variable9to correct a frequency-generating oscillator10, which is generally current-controlled or voltage-controlled. The correcting variable9comprises the two correcting signals Correctupward9A to correct the frequency of the frequency-generating oscillator10upwards and Correctdownward9B to correct the frequency of the frequency-generating oscillator10downwards.1Translator's note: Mis-identified in the original as 3.

The correcting variable9, in the form of its two correcting signals Correctupward9A and Correctdownward9B, is fed to the input of a loop filter11. The loop filter has a given characteristic dynamic response which enables it to have a targeted influence on the dynamic behaviour of the phase/frequency-locked loop in respect of stability. The output signal12from the loop filter11is fed to the input of the frequency-generating oscillator10to control the frequency of the output-frequency signal6.

In this way, the frequency of the output-frequency signal6is controlled to suit the variation over time of the frequency of the reference-frequency signal3, as a function of the gain of the phase/frequency-locked loop1, which gain is determined by, amongst other things, the dividing factors N and M of the frequency dividers2and5. If there is a change in the frequency of the reference-frequency signal3over time or if a disruption occurs which affects the phase/frequency-locked loop1, the dynamic response of the phase-frequency-locked loop1is determined by the dynamic behaviour of the individual functional units in the phase/frequency-locked loop1, and particularly that of the loop filter1and the frequency-generating oscillator10.

Whereas the loop filter11and the frequency-generating oscillator10are functional units which are often implemented in analogue form, the frequency dividers2and5and the phase/frequency comparator8may be implemented in analogue or digital form. In the case of digital implementation, the phase/frequency detector (PFD) employing edge-triggered D flip-flops and resetting logic which will be used in the vast majority of applications will be further described below.

A block circuit diagram of the phase/frequency detector (PFD) is shown inFIG. 3. The PFD comprises two edge-triggered storage devices13and14, which are preferably edge-triggered D flip-flops. In the case of the edge-triggered D flip-flop13, when a positive-going edge of the reference-frequency signal4, whose frequency may, as an option, have been divided in the frequency divider2, is applied to the clock input Clk, the level present at input D, which is set to a constant logic “1”, is switched to the output Q. The correcting signal Correctupward9A which is present at the output Q of the D flip-flop13is used to correct the frequency of the frequency-generating oscillator10upwards. In a similar way, in the case of the edge-triggered D flip-flop14, when a positive-going edge of the output-frequency signal7, whose frequency may, as an option, have been divided in the frequency divider5, is applied to the clock input Clk, the level present at input D, which is set to a constant logic “1”, is switched to the output Q. The correcting signal Correctdownward9B which is present at the output Q of the D flip-flop14is used to correct the frequency of the frequency-generating oscillator10downwards. The two correcting signals Correctupward9A and Correctdownward9B are fed to the inputs of the resetting logic15.

In the prior art, the resetting logic15comprises an AND gate. The resetting logic15generates a resetting signal16, which is fed to the resetting input R of the D flip-flop13as a resetting signal16A and to the resetting input R of the D flip-flop14as a resetting signal16B. Hence, if the two outputs Q of the two D flip-flops13and14are set simultaneously, the output of the resetting logic15is also activated and this, via the resetting signals16A and16B to their respective resetting inputs R, causes the two D flip-flops13and14to be reset.

In a first embodiment of the resetting logic15, which is shown inFIG. 4, use is made of an asynchronous level-triggered RS flip-flop17whose logic is inverse (=low is active). The setting input S of the asynchronous level-triggered RS flip-flop17has the output signal18from an inverted AND gate19supplied to it. The two correcting signals Correctupward9A and Correctdownward9B are fed to the inputs of the inverted AND gate19. The output signal20from an OR gate21is fed to the resetting input R of the asynchronous level-triggered RS flip-flop17. The two inputs of the OR gate21have the two correcting signals Correctupward9A and Correctdownward9B supplied to them. The resetting signal16is generated at the output Q of the asynchronous level-triggered RS flip-flop17. To implement the inverse logic, the asynchronous level-triggered RS flip-flop17has an inverted AND gate22whose output is connected to the output Q and whose inputs have the input S and the output of a further inverted AND gate23supplied to them. The inputs of the further inverted AND gate23have the resetting input R and the output of the first inverted AND gate22supplied to them.

If the two correcting signals Correctupward9A and Correctdownward9B are activated simultaneously (“1” state), the output signal18from the inverted AND gate19, and hence the setting input S of the asynchronous level-triggered RS flip-flop17, are activated (are set to the “0” state). At the same time, the output signal20from the OR gate21, and hence the resetting input R of the asynchronous level-triggered RS flip-flop17, are deactivated (are set to the “1” state). Because of the inverse logic of the RS flip-flop17, the output Q and hence the resetting signal16are set. If on the other hand the two correcting signals Correctupward9A and Correctdownward9B are de-activated simultaneously (“0” state), the output signal18from the inverted AND gate19, and hence the setting input S of the RS flip-flop17, are set to the “1” state. The output signal20from the OR gate21, and hence the resetting input R of the RS flip-flop17, are set to the “0” state. Because of the inverse logic of the flip-flop, the output Q of the RS flip-flop17is reset.

This ensures that the resetting signal16is set when the two correcting signals Correctupward9A and Correctdownward9B have been set. Resetting of the resetting signal16only takes place when the two correcting signals Correctupward9A and Correctdownward9B are reset simultaneously. In this way, the frequency of the frequency-generating oscillator10can be corrected in line with the nature of the correcting signals Correctupward9A and Correctdownward9B without causing any unwanted jumps in frequency and hence instabilities in the phase/frequency-locked loop. The behaviour of the PLL circuit is thus behaviour which can be controlled.

In a second embodiment of the resetting logic15, which is shown inFIG. 5, use is made of an asynchronous level-triggered RS flip-flop24which is of non-inverse logic. The setting input S of the asynchronous level-triggered RS flip-flop24has the output signal25from an AND gate26supplied to it. The two correcting signals Correctupward9A and Correctdownward9B are fed to the inputs of the AND gate26. The output signal27from an inverted OR gate28is fed to the resetting input R of the asynchronous level-triggered RS flip-flop24. The two inputs of the inverted OR gate28have the two correcting signals Correctupward9A and Correctdownward9B supplied to them. The resetting signal16is generated at the output Q of the asynchronous level-triggered RS flip-flop24. To implement the non-inverse logic, the asynchronous level-triggered RS flip-flop24has an inverted OR gate29whose output is connected to the output Q and whose inputs have the input S and the output of a further inverted OR gate30supplied to them. The inputs of the further inverted OR gate30have the resetting input R and the output of the first inverted OR gate29supplied to them.

If the two correcting signals Correctupward9A and Correctdownward9B are activated simultaneously (“1” state), the output signal25from the AND gate26, and hence the setting input S of the asynchronous level-triggered RS flip-flop24, are activated (“1” state). At the same time, the output signal27from the inverted OR gate28, and hence the resetting input R of the asynchronous level-triggered RS flip-flop24, are not set (“0” state). Because of the non-inverted logic of the RS flip-flop24, the output Q and hence the resetting signal16are set. If on the other hand the two correcting signals Correctupward9A and Correctdownward9B are de-activated simultaneously (“0” state), the output signal25from the AND gate26, and hence the setting input S of the RS flip-flop, are reset (“0” state). The output signal27from the inverted OR gate28, and hence the resetting input R of the RS flip-flop24, are activated (“1” state). Because of the non-inverted logic of the flip-flop, the output Q of the RS flip-flop24is reset.

In this embodiment too, having an asynchronous level-triggered RS flip-flop24and non-inverted logic, it is ensured that the resetting signal16is set only when the two correcting signals Correctupward9A and Correctdownward9B have been set simultaneously. Resetting of the resetting signal16only takes place when the two correcting signals Correctupward9A and Correctdownward9B have been reset. In this embodiment too the behaviour of the PLL circuit is thus behaviour which is controllable because no unwanted jumps in frequency occur, and there are thus no instabilities in the phase/frequency-locked loop.