Semiconductor storage device

According to the embodiment, in a first period, the semiconductor storage device maintains the switch in an ON state. In a second period, the semiconductor storage device performs a first operation, a second operation and a third operation while maintaining the switch in an OFF state. The second period is a period after the first period. The first operation is an operation to supply the first pulse having the first polarity from the first pulse generation circuit to the other end of the first capacitive element. The second operation is an operation to supply the second pulse having the second polarity from the second pulse generation circuit to the other end of the second capacitive element. The third operation is an operation to connect the first bit line to the first data line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-152244, filed on Sep. 10, 2020; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor storage device.

BACKGROUND

In a semiconductor storage device including a memory cell, a bit line, a data line, and a sense amplifier, when the memory cell is connected to the sense amplifier via the bit line and the data line, a level of a signal output from the memory cell via the bit line and the data line is detected by the sense amplifier. At this time, it is desirable to appropriately detect the level of the signal of the memory cell.

DETAILED DESCRIPTION

In general, according to one embodiment, there is provided a semiconductor storage device including a first bit line, a first data line, a second bit line, a second data line, a sense amplifier, a switch, a voltage generation circuit, a first capacitive element, a second capacitive element, a first pulse generation circuit, and a second pulse generation circuit. The first bit line is connected to a first memory cell. The first data line is connectable to and disconnectable from the first bit line. The second bit line is connected to a second memory cell. The second data line is connectable to and disconnectable from the second bit line. The sense amplifier has a first input node connected to the first data line and a second input node connected to the second data line. The switch is capable of connecting the first data line and the second data line. The voltage generation circuit is capable of supplying a reference voltage to at least one of the first data line and the second data line. The first capacitive element has one end connected to the first data line. The second capacitive element has one end connected to the second data line. The first pulse generation circuit generates a first pulse having first polarity. The second pulse generation circuit generates a second pulse having second polarity. In a first period, the semiconductor storage device maintains the switch in an ON state. In a second period, the semiconductor storage device performs a first operation, a second operation and a third operation while maintaining the switch in an OFF state. The second period is a period after the first period. The first operation is an operation to supply the first pulse having the first polarity from the first pulse generation circuit to the other end of the first capacitive element. The second operation is an operation to supply the second pulse having the second polarity from the second pulse generation circuit to the other end of the second capacitive element. The third operation is an operation to connect the first bit line to the first data line.

Exemplary embodiments of a semiconductor storage device will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

Embodiment

A semiconductor storage device according to an embodiment includes a memory cell, a bit line, a data line, and a sense amplifier. In the semiconductor storage device, when the memory cell is connected to the sense amplifier via the bit line and the data line, a signal level output from the memory cell via the bit line and the data line is detected by the sense amplifier.

The sense amplifier may be configured by a comparator in which one ends of two capacitive elements are connected to two input nodes. In this configuration, after one ends of the two capacitive elements are equipotential (equalized), the reference voltage is accumulated in one capacitive element, and the signal output from the memory cell via the bit line and the data line is accumulated in the other capacitive element. Then, by comparing the reference voltage accumulated in the one capacitive element with the signal level accumulated in the other capacitive element by the comparator, it is possible to detect which signal level of data values of 0 and 1 the signal level corresponds to.

At this time, when the signal level corresponding to the data value 0 is close to the level of the reference voltage, there is a possibility that the comparator makes an error in the magnitude determination of the reference voltage and the signal level and cannot appropriately detect the signal level.

On the other hand, when the capacitance value of the capacitive element in which the reference voltage is accumulated is increased in order to ensure a large signal amount, which is a level difference between the signal for the data value 0 and the reference voltage, the accumulation time of the signal in the capacitive element is long, and the sense amplifier operation tends to be delayed. It is desirable to secure the signal amount while speeding up the sense amplifier operation.

Therefore, in the present embodiment, in the sense amplifier operation, the semiconductor storage device supplies a positive potential pulse to the other end of the capacitive element in which the reference voltage is accumulated and supplies a negative potential pulse to the other end of the capacitive element in which the signal is accumulated, thereby securing the signal amount while speeding up the sense amplifier operation.

Specifically, a semiconductor storage device1can be configured as illustrated inFIG. 1.FIG. 1is a diagram illustrating a configuration of the semiconductor storage device1. The semiconductor storage device1includes a memory cell array MCA, a plurality of word lines WL0to WL15, a plurality of bit lines BL0to BL15, a row control unit2, a column control unit3, a sense amplifier block4, a voltage generation circuit5, and a pulse A generation circuit6.

In the memory cell array MCA, as illustrated inFIG. 2, a plurality of memory cells MC is disposed in a matrix at positions where a plurality of word lines WL and a plurality of bit lines BL intersect.FIG. 2is a diagram illustrating a configuration of the memory cell array MCA.FIG. 2illustrates a configuration in which 16×16 memory cells MC are disposed at positions where 16 word lines WL0to WL15intersect with 16 bit lines BL0to BL15. Each word line WL extends in the direction along the row (row direction), and each bit line BL extends in the direction along the column (column direction).

The row control unit2illustrated inFIG. 1is disposed toward one end of the memory cell array MCA in the row direction, and is connected to the plurality of word lines WL. The row control unit2receives an address signal from the semiconductor storage device1, selects a word line WL from the plurality of word lines WL according to the address signal, supplies a selected voltage (for example, the power supply voltage) to the selected word line WL, and supplies an unselected voltage (for example, the ground voltage) to the unselected word line WL. The row control unit2can be configured as a multiplexer (MUX). The row control unit2includes a first node to which the selected voltage is supplied and a second node to which the unselected voltage is supplied. In the default state, the plurality of word lines WL is connected to the second node and the word line WL corresponding to the address value decoded from the address signal is selectively connected to the first node.

The column control unit3is disposed toward one end of the memory cell array MCA in the column direction, and is connected to the plurality of bit lines BL. The column control unit3is connected between the plurality of bit lines BL and a plurality of local data lines LDL. The column control unit3receives the address signal from the semiconductor storage device1, selects a bit line BL from the plurality of bit lines BL according to the address signal, and connects the selected bit line BL to the local data line LDL, and the signal from the selected memory cell MC is read out to the local data line LDL via the selected bit line BL. The column control unit3can be configured as a multiplexer (MUX).

The column control unit3groups the plurality of bit lines BL into a plurality of groups in units of the number of local data lines LDL, and can connect the plurality of bit lines BL to the plurality of local data lines LDL in unit of group. The column control unit3may select a group including the selected bit line BL corresponding to the address value decoded from the address signal and connect the selected group to the plurality of local data lines LDL.

The sense amplifier block4includes a comparator and two capacitive elements. The comparator and the two capacitive elements are connected via two data lines. As an initial setting, the sense amplifier block4short-circuits the two data lines to equalize them. Thereafter, the sense amplifier block4accumulates a reference signal Vref in one capacitive element of the two capacitive elements via one data line of the two data lines.

The sense amplifier block4is connected to the column control unit3via the plurality of local data lines LDL. The sense amplifier block4receives an address signal from the semiconductor storage device1and selects a local data line LDL from the plurality of local data lines LDL according to the address signal. As a result, in the sense amplifier block4, the signal from the selected memory cell MC is read out to the other data line of the two data lines via the bit line BL and the local data line LDL. The sense amplifier block4accumulates a signal in the other capacitive element of the two capacitive elements via the other data line.

The one data line is at a level corresponding to the reference signal Vref, and the other data line is at a level corresponding to the signal. In this state, the sense amplifier block4compares the level of the one data line with the level of the other data line to perform a sense amplifier operation of detecting which signal level of data values of 0 and 1 the signal level corresponds to. The voltage generation circuit5is connected to the sense amplifier block4. The voltage generation circuit5can supply the reference signal Vref to the sense amplifier block4. For example, when performing the sense amplifier operation, the sense amplifier block4supplies the reference signal Vref received from the voltage generation circuit5to the selected local data line LDL as the selected voltage. As a result, the sense amplifier block4can cause the signal from the selected memory cell MC to be read out to the data line via the local data line LDL.

The pulse A generation circuit6is connected to the sense amplifier block4. The pulse A generation circuit6can supply a pulse A to the sense amplifier block4when the sense amplifier block4performs a sense amplifier operation. In the sense amplifier operation, the pulse A generation circuit6supplies the positive potential pulse A to the other end of the capacitive element in which the reference voltage is accumulated.

A pulse B generation circuit7is connected to the sense amplifier block4. The pulse B generation circuit7can supply a pulse B to the sense amplifier block4when the sense amplifier block4performs a sense amplifier operation. In the sense amplifier operation, the pulse B generation circuit7supplies the negative potential pulse B to the other end of the capacitive element in which the signal is accumulated.

Each memory cell MC can be configured as illustrated inFIGS. 3A and 3B.FIGS. 3A and 3Bare diagrams illustrating a configuration of the memory cell MC.FIG. 3Ais a circuit diagram illustrating a circuit configuration of each memory cell MC, andFIG. 3Bis a perspective view illustrating a layer configuration of each memory cell MC.

Each memory cell MC in the memory cell array MCA is disposed at a position where the word line WL extending in the row direction and the bit line BL extending in the column direction intersect. The memory cell MC has one end connected to the word line WL and the other end connected to the bit line BL.

As illustrated inFIG. 3A, each memory cell MC includes a variable resistance element VR and a switch element SE. The variable resistance element VR can be in a low resistance state and a high resistance state. The variable resistance element VR holds one-bit data using a difference in resistance state between the low resistance state and the high resistance state. For example, the switch element SE is in a high resistance state (non-conducting state, OFF state) when the applied voltage is less than the threshold value, and is in a non-conducting state (conducting state, ON state) when the applied voltage is equal to or greater than the threshold value. As a result, the switch element SE functions as a rectifying element having a rectifying function.

AlthoughFIG. 3Aillustrates the configuration in which the direction from the word line WL to the bit line BL is the rectification direction of the switch element SE, the direction from the bit line BL to the word line WL may be the rectification direction of the switch element SE. Alternatively, the switch element SE may be a bidirectional rectifying element.

In addition, althoughFIG. 3Aillustrates a configuration in which the switch element SE is disposed toward the word line WL and the variable resistance element VR is disposed toward the bit line BL in the memory cell MC, the switch element SE may be disposed toward the bit line BL and the variable resistance element VR may be disposed toward the word line WL in the memory cell MC.

In the layer configuration, as illustrated inFIG. 3B, the word line WL extending in the row direction is away from the bit line BL extending in the column direction in the stacking direction. Each memory cell MC is disposed between the bit line BL and the word line WL at a position where the bit line BL and the word line WL intersect. As a result, the cross-point memory cell array MCA in which the plurality of memory cells MC is disposed in a matrix in plan view is configured.

In each memory cell MC, for example, a layer of the variable resistance element VR and a layer of the switch element SE are disposed in the stacking direction. AlthoughFIG. 3Billustrates the configuration in which the layer of the switch element SE is stacked on the layer of the variable resistance element VR, the configuration may be such that the layer of the variable resistance element VR is stacked on the layer of the switch element SE.

Note thatFIG. 3Billustrates an example in which each of the bit line BL and the word line WL is one layer, and one layer of the memory cell MC is disposed therebetween, but the present invention is not limited thereto. The number of layers in which the memory cells MC are disposed may be further increased, and correspondingly, the number of layers of the bit line BL and/or the word line WL may be further increased. That is, in the memory cell array MCA, a three-dimensional array of the memory cells MC may be realized by stacking a two-dimensional array (memory layer) of the memory cells MC.

For example, the plurality of bit lines BL extending in a direction orthogonal to the direction in which the word lines WL extend may be further provided at intervals on the plurality of word lines WL inFIG. 3B, and the plurality of memory cells MC may be further disposed at intersections of the plurality of word lines WL and the plurality of upper bit lines BL. In this case, the memory cell MC has two layers, and the wiring layer (the layer of the bit line BL and the layer of the word line WL) has three layers.

The column control unit3is configured as illustrated inFIG. 4.FIG. 4is a diagram illustrating a configuration of the column control unit3.FIG. 4illustrates a configuration in which eight bit lines BL[0] to BL[7] are connected to the column control unit3, and four local data lines LDL[0] to LDL[3] are connected to the column control unit3. The eight bit lines BL[0] to BL[7] are grouped into two groups GR[0] to GR[1] in unit of four. In the column control unit3, four NMOS transistors for the group GR[0] are electrically connected between the bit lines BL[0] to BL[3] and the local data lines LDL[0] to LDL[3], and four PMOS transistors for the group GR[0] are electrically connected between the bit lines BL[0] to BL[3] and the reference voltage VUB. The selection signal SEL[0] is supplied to the gate of each transistor for the group GR[0]. In the column control unit3, four NMOS transistors for the group GR[1] are electrically connected between the bit lines BL[4] to BL[7] and the local data lines LDL[0] to LDL[3], and four PMOS transistors for the group GR[1] are electrically connected between the bit lines BL[4] to BL[7] and the unselected voltage VUB. The selection signal SEL[0] is supplied to the gate of each transistor for the group GR[1].

For example, when the bit line BL corresponding to the address value decoded from the address signal is the bit line BL[0], the column control unit3generates the selection signal SEL[0:1]=(1, 0) to supply the generated selection signal SEL[0:1]=(1, 0) to the gate of each transistor. As a result, as illustrated inFIG. 4, the group GR[0] is selected, the four NMOS transistors for the group GR[0] are turned on, the four PMOS transistors are turned off, and the bit lines BL[0] to BL[3] are connected to the local data lines LDL[0] to LDL[3]. The column control unit3applies a selected voltage to the local data line LDL[0], and applies an unselected voltage to the local data lines LDL[1] to LDL[3]. As a result, the signal from the selected memory cell MC is read out to the local data line LDL[0] via the selected bit line BL[0]. On the other hand, the four NMOS transistors for the group GR[1] are turned off, and the four PMOS transistors are turned on. As a result, the group GR[1] is unselected, and the unselected voltage VUB is supplied to the bit lines BL[4] to BL[7].

As illustrated inFIG. 5, the sense amplifier block4includes a sense amplifier41and two capacitive elements C1and C2.FIG. 5is a diagram illustrating a configuration of the sense amplifier block4. The sense amplifier block4includes the sense amplifier41, selectors SEL1and SEL2, data lines DL[0] and DL[1], the capacitive elements C1and C2, and a plurality of switches SW1to SW8.

The sense amplifier41is configured by, for example, a comparator, and includes an input node41acorresponding to a non-inverting input terminal, an input node41bcorresponding to an inverting input terminal, an output node41c, and a control node41dthat receives a sense amplifier enable signal SAE. When receiving the sense amplifier enable signal SAE at the non-active level, the sense amplifier41stops the output thereof. When receiving the sense amplifier enable signal SAE at the active level, the sense amplifier41compares the level of the input node41awith the level of the input node41b, to output a comparison result SAOUT. The sense amplifier41outputs the H level SAOUT from the output node41cwhen the level of the input node41ais higher than the level of the input node41b, and outputs the L level SAOUT from the output node41cwhen the level of the input node41ais lower than the level of the input node41b.

The selector SEL1is electrically connected between the plurality of local data lines LDL[0] to LDL[k] and the data line DL[0]. The selector SEL1includes a plurality of switches AX[0] to AX[k] corresponding to the plurality of local data lines LDL[0] to LDL[k]. Each switch AX is, for example, an NMOS transistor or a transfer gate, and connects the corresponding local data line LDL to the data line DL[0] when an active control signal AX is received at the control terminal (gate), and disconnects the corresponding local data line LDL from the data line DL[0] when a non-active control signal AX is received at the control terminal. When the control signals AX[0] to AX[k] include the active control signal AX (that is, in a case where a signal is read out to the data line DL[0]), the selector SEL1selects one local data line LDL from the plurality of local data lines LDL[0] to LDL[k] according to the active control signal AX, and connects the selected local data line LDL to the data line DL[0].

The selector SEL2is electrically connected between the plurality of local data lines LDL[k+1] to LDL[2k] and the data line DL[1]. The selector SEL2includes a plurality of switches AX [k+1] to AX[2k] corresponding to the plurality of local data lines LDL[k+1] to LDL[2k]. Each switch AX is, for example, an NMOS transistor or a transfer gate, connects the corresponding local data line LDL to the data line DL[1] when an active control signal AX is received at the control terminal (gate), and disconnects the corresponding local data line LDL from the data line DL[1] when a non-active control signal AX is received at the control terminal. When the control signals AX[k+1] to AX[2k] include an active control signal AX (that is, in a case where a signal is read out to the data line DL[1]), the selector SEL2selects one local data line LDL from the plurality of local data lines LDL[k+1] to LDL[2k] according to the active control signal AX, and connects the selected local data line LDL to the data line DL[1].

The data line DL[0] is electrically connected to the output node of the selector SEL1and the input node41aof the sense amplifier41. The data line DL[0] is electrically connected to the data line DL[1] via the switch SW1, and is electrically connected to one end of the capacitive element C1via the switch SW3.

The data line DL[1] is electrically connected to the output node of the selector SEL2, one end of the capacitive element C2, and the input node41bof the sense amplifier41. The data line DL[1] is electrically connected to the data line DL[0] via the switch SW1, and is electrically connected to one end of the capacitive element C2via the switch SW4. The data line DL[1] is electrically connected to the voltage generation circuit5via the switch Sw2.

One end of the capacitive element C1is electrically connected to the data line DL[0] via the switch SW3. The other end of the capacitive element C1is electrically connected to the pulse A generation circuit6and the pulse B generation circuit7via the switches SW5and SW6, respectively.

One end of the capacitive element C2is electrically connected to the data line DL[1] via the switch SW4. The other end of the capacitive element C2is electrically connected to the pulse A generation circuit6and the pulse B generation circuit7via the switches SW7and SW8, respectively.

The switch SW1is electrically connected between the data line DL[0] and the data line DL[1]. The switch SW1electrically connects the data line DL[0] and the data line DL[1] in response to the active level control signal EQ, and electrically disconnects the data line DL[0] and the data line DL[1] in response to the non-active level control signal EQ. The switch SW1includes, for example, the NMOS transistor. The NMOS transistor receives the control signal EQ at the gate, and one of the source and the drain is connected to the data line DL[0] and the other is connected to the data line DL[1].

The switch SW2is electrically connected between the data line DL[1] and the voltage generation circuit5. The switch SW2electrically connects the output node of the voltage generation circuit5to the data line DL[1] in response to the active level control signal Ref, and electrically disconnects the output node of the voltage generation circuit5from the data line DL[1] in response to the non-active level control signal Ref. The switch SW2includes, for example, the NMOS transistor. The NMOS transistor receives the control signal Ref at the gate, has the source connected to the data line DL[1], and has the drain connected to an output node of the voltage generation circuit5.

The switch SW3is electrically connected between the data line DL[0] and the capacitive element C1. The switch SW3electrically connects the data line DL[0] to one end of the capacitive element C1in response to the active level control signal φSW3, and electrically disconnects the data line DL[0] from one end of the capacitive element C1in response to the non-active level control signal φSW3. The switch SW3includes, for example, the NMOS transistor. The NMOS transistor receives a control signal φSW3at a gate, has the source connected to one end of the capacitive element C1, and has the drain connected to the data line DL[0].

The switch SW4is electrically connected between the data line DL[1] and the capacitive element C2. The switch SW4electrically connects the data line DL[1] to one end of the capacitive element C2in response to the active level control signal φSW4, and electrically disconnects the data line DL[1] from one end of the capacitive element C2in response to the non-active level control signal φSW4. The switch SW4includes, for example, the NMOS transistor. The NMOS transistor receives the control signal φSW4at the gate, has the source connected to one end of the capacitive element C2, and has the drain connected to the data line DL[1].

The switch SW5is electrically connected between the capacitive element C1and the pulse A generation circuit6. The switch SW5electrically connects the other end of the capacitive element C1to the output node of the pulse A generation circuit6in response to the active level control signal φSW5, and electrically disconnects the other end of the capacitive element C1from the output node of the pulse A generation circuit6in response to the non-active level control signal φSW5. The switch SW5includes, for example, the NMOS transistor. The NMOS transistor receives the control signal φSW5at the gate, has the source connected to the other end of the capacitive element C1, and has the drain connected to the output node of the pulse A generation circuit6.

The switch SW6is electrically connected between the capacitive element C1and the pulse B generation circuit7. The switch SW6electrically connects the other end of the capacitive element C1to the output node of the pulse B generation circuit7in response to the active level control signal φSW6, and electrically disconnects the other end of the capacitive element C1from the output node of the pulse B generation circuit7in response to the non-active level control signal φSW6. The switch SW6includes, for example, the NMOS transistor. The NMOS transistor receives the control signal φSW6at the gate, has the source connected to the other end of the capacitive element C1, and has the drain connected to the output node of the pulse B generation circuit7.

The switch SW7is electrically connected between the capacitive element C2and the pulse A generation circuit6. The switch SW7electrically connects the other end of the capacitive element C2to the output node of the pulse A generation circuit6in response to the active level control signal φSW7, and electrically disconnects the other end of the capacitive element C2from the output node of the pulse A generation circuit6in response to the non-active active level control signal φSW7. The switch SW7includes, for example, the NMOS transistor. The NMOS transistor receives the control signal φSW7at the gate, has the source connected to the other end of the capacitive element C2, and has the drain connected to the output node of the pulse A generation circuit6.

The switch SW8is electrically connected between the capacitive element C2and the pulse B generation circuit7. The switch SW8electrically connects the other end of the capacitive element C2to the output node of the pulse B generation circuit7in response to the active level control signal φSW8, and electrically disconnects the other end of the capacitive element C2from the output node of the pulse B generation circuit7in response to the non-active level control signal φSW8. The switch SW8includes, for example, the NMOS transistor. The NMOS transistor receives the control signal φSW8at the gate, has the source connected to the other end of the capacitive element C2, and has the drain connected to the output node of the pulse B generation circuit7.

Next, the operation of the sense amplifier block4when a signal is read out to the data line DL[0] will be described with reference toFIGS. 6 to 8.FIGS. 6 and 8are waveform diagrams illustrating the operation of the sense amplifier block (when a signal is read out to the DL[0]).FIGS. 7A and 7Bare diagrams illustrating operation of each component in the sense amplifier block4.

When a signal corresponding to the data value 1 is read out to the data line DL[0], a sense amplifier operation as illustrated inFIG. 6is performed.

Immediately before timing t1, the sense amplifier block4maintains the switches AX[0] to AX[k] and AX[k+1] to AX[2k] of the selectors SEL1and SEL2in an OFF state as illustrated inFIG. 7A. In addition, the sense amplifier block4maintains the switches SW1to SW8in an OFF state. As a result, the potentials of the data lines DL[0] and DL[1], the one ends of the capacitive elements C1and C2, and the other ends of the capacitive elements C1and C2are all at the reference level (for example, the ground level).

At timing t1, the sense amplifier block4turns on the switches SW1to SW4as illustrated inFIG. 7A. As a result, the data line DL[0], the data line DL[1], one end of the capacitive element C1, and one end of the capacitive element C2are connected, the reference voltage Vref is supplied from the voltage generation circuit5to the data lines DL[0] and DL[1] and the one ends of the capacitive elements C1and C2, and the potential thereof rises. That is, the electric charge is accumulated in the parasitic capacitance of the data line DL[0], the parasitic capacitance of the data line DL[1], one end of the capacitive element C1, and one end of the capacitive element C2by the voltage generation circuit5. As a result, the potential of the data line DL[0], the potential of the data line DL[1], the potential Vs[0] at one end of the capacitive element C1, and the potential Vs[1] at one end of the capacitive element C2are equipotential to each other, and all are substantially equal to the level of the reference voltage Vref. Thus, the reference for comparison by the sense amplifier (comparator)41is equally set.

When the data lines DL[0] and DL[1] and the one ends of the capacitive elements C1and C2reach the level of the reference voltage Vref at timing t2, the sense amplifier block4turns off the switches SW1and SW2at timing t3as illustrated inFIG. 7B. As a result, each of the data line DL[0], the data line DL[1], one end of the capacitive element C1, and one end of the capacitive element C2is in a floating state while being held at the level of the reference voltage Vref.

At timing t4, as illustrated inFIG. 7B, the sense amplifier block4turns on the switch SW7while maintaining the switch SW8in an OFF state. As a result, the pulse A having the amplitude of the positive potential is supplied from the pulse A generation circuit6to the other end of the capacitive element C2, and the potential Vs[1] at the other end of the capacitive element C2is shifted to the positive side by an amount corresponding to the amplitude V1of the pulse A as indicated by a dot-and-dash line inFIG. 6to reach V1(>0).

As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[1] and one end of the capacitive element C2according to the ratio between the parasitic capacitance value of the data line DL[1] and the capacitance value of the capacitive element C2. In response to this, the potential of the data line DL[1] is shifted in a direction in which the amplitude increases by a shift amount ΔVref corresponding to the shift amount of the potential Vs[1] as indicated by a dot-and-dash line inFIG. 6to reach V2(>Vref). That is, the following Expression 1 is established.
ΔVref=V2−Vref=k2×(V1−0)  Expression 1

In Expression 1, the shift amount ΔVref is an absolute value of the shift amount and is a positive value. k2is a positive coefficient that changes depending on the capacitance value of the capacitive element C2(for example, in proportion to the capacitance value of the capacitive element C2), and has a larger value as the capacitance value of the capacitive element C2is larger.

At timing t5, as illustrated inFIG. 7B, the sense amplifier block4selectively turns on one switch AX[0] of the plurality of switches AX[0] to AX[k] in the selector SEL1. Accordingly, one selected local data line LDL[0] of the plurality of local data lines LDL[0] to LDL[k] is connected to the data line DL[0].

When the data value 1 is stored in the memory cell MC, a signal corresponding to the data value 1 is read out from the memory cell MC to the data line DL[0] via the selected bit line BL and the selected local data line LDL[0], and the potential of the data line DL[0] rises from the level of the reference voltage Vref.

At timing t6, the potential of the data line DL[0] reaches the level V3increased by the voltage ΔVMC1corresponding to the data value 1 from the level of the reference voltage Vref. That is, the following Expression 2 is established.
V3=Vref+ΔVMC1Expression 2

At timing t7, as illustrated inFIG. 7B, the sense amplifier block4turns on the switch SW6while maintaining the switch SW5in an OFF state. As a result, the pulse B having the amplitude of the negative potential is supplied from the pulse B generation circuit7to the other end of the capacitive element C1, and the potential Vs[0] at the other end of the capacitive element C1is shifted to the negative side by an amount corresponding to the amplitude of the pulse B to reach V4(<0) as indicated by the solid line inFIG. 6.

As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[0] and one end of the capacitive element C1according to the ratio between the parasitic capacitance value of the data line DL[0] and the capacitance value of the capacitive element C1. Accordingly, as indicated by a solid line inFIG. 6, the potential of the data line DL[0] is shifted in a direction in which the amplitude decreases by a shift amount ΔVs proportional to the shift amount of the potential Vs[0] to reach V5(<V3). That is, the following Expression 3 is established.
ΔVs=V3−V5=k1×(0−V4)  Expression 3

In Expression 3, the shift amount ΔVs is an absolute value of the shift amount and is a positive value. k1is a positive coefficient that changes depending on the capacitance value of the capacitive element C1, and has a larger value as the capacitance value of the capacitive element C1is larger.

When the sense amplifier enable signal SAE is at the active level at timing t8, the sense amplifier41compares the level of the data line DL[0] with the level of the data line DL[1] at timing t9.

At this time, a signal amount ΔS1, which is a level difference between the signal for the data value 1 and the reference voltage, is expressed by the following Expression 4.
ΔS1=V5−V2Expression 4

According to Expressions 1 to 3, Expression 4 can be transformed into the following Expression 5.
ΔS1=ΔVMC1−ΔVref−ΔVsExpression 5

As illustrated inFIG. 6and Expression 5, the signal amount ΔS1for the data value 1 is reduced by the amount by which the shift amount ΔVref of the data line DL[1] and the shift amount ΔVs of the data line DL[0] are subtracted from the voltage ΔVMC1corresponding to the data value 1, but is secured at a level sufficient for the comparison operation of the sense amplifier41.

As a result, the sense amplifier41can detect that the level of the data line DL[0] is higher than the level of the data line DL[1], and can output the comparison result SAOUT of the H level. The comparison result SAOUT of the H level indicates that the data value 1 is detected by the sense amplifier41.

On the other hand, in a case where a signal corresponding to the data value 0 is read out to the data line DL[0], a sense amplifier operation as illustrated inFIG. 8is performed.

At timings t11to t14, the sense amplifier block4performs the operation same as that at timings t1to t4illustrated inFIG. 6.

At timing t15, as illustrated inFIG. 7B, the sense amplifier block4selectively turns on one switch AX[0] of the plurality of switches AX[0] to AX[k] in the selector SEL1. Accordingly, one selected local data line LDL[0] of the plurality of local data lines LDL[0] to LDL[k] is connected to the data line DL[0].

When the data value 0 is stored in the memory cell MC, a signal corresponding to the data value 0 is read out from the memory cell MC to the data line [0] via the selected bit line BL and the selected local data line LDL.

At timing t16, the potential of the data line DL[0] reaches the level V6changed by the voltage ΔVMC0(≈0) corresponding to the data value 0 with respect to the level of the reference voltage Vref. That is, the following Expression 6 is established.
V6=Vref+ΔVMC0≈Vref  Expression 6

At timing t17, the sense amplifier block4turns on the switch SW6while maintaining the switch SW5in an OFF state as illustrated inFIG. 7B. As a result, the pulse B having the amplitude of the negative potential is supplied from the pulse B generation circuit7to the other end of the capacitive element C1, and the potential Vs[0] at the other end of the capacitive element C1is shifted to the negative side by an amount corresponding to the amplitude of the pulse B to reach V4(<0) as indicated by the solid line inFIG. 8.

As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[0] and one end of the capacitive element C1according to the ratio between the parasitic capacitance value of the data line DL[0] and the capacitance value of the capacitive element C1. Accordingly, as indicated by a solid line inFIG. 8, the potential of the data line DL[0] is shifted in a direction in which the amplitude decreases by a shift amount ΔVs proportional to the shift amount of the potential Vs[0] to reach V5(<V3). That is, the following Expression 7 is established.
ΔVs=V6−V7=k1×(0−V4)  Expression 7

In Expression 7, the shift amount ΔVs is an absolute value of the shift amount and is a positive value. k1is a positive coefficient that changes depending on the capacitance value of the capacitive element C1, and has a larger value as the capacitance value of the capacitive element C1is larger.

When the sense amplifier enable signal SAE is at the active level at timing t18, the sense amplifier41compares the level of the data line DL[0] with the level of the data line DL[1] at timing t19.

At this time, a signal amount ΔS0, which is a level difference between the signal for the data value 0 and the reference voltage, is expressed by the following Expression 8.
ΔS0=V2−V7Expression 8

According to Expressions 1 to 3, 6, and 7, Expression 8 can be transformed into the following Expression 9.
ΔS0=ΔVMC0+ΔVref+ΔVsExpression 9

As illustrated inFIG. 8and Expression 9, the signal amount ΔS0for the data value 0 is increased by the addition of the shift amount ΔVref of the data line DL[1] and the shift amount ΔVs of the data line DL[0] with respect to the voltage ΔVMC0(≈0) corresponding to the data value 0, and is secured at a level sufficient for the comparison operation of the sense amplifier41.

As a result, the sense amplifier41can detect that the level of the data line DL[0] is lower than the level of the data line DL[1], and can output the comparison result SAOUT of the L level. The comparison result SAOUT of the L level indicates that the data value 0 is detected by the sense amplifier41.

Next, the operation of the sense amplifier block4when a signal is read out to the data line DL[1] will be described with reference toFIGS. 9 to 11.FIGS. 9 and 11are waveform diagrams illustrating the operation of the sense amplifier block (when a signal is read out to the DL[1]).FIGS. 10A and 10Bare diagrams illustrating operation of each component in the sense amplifier block4.

When a signal corresponding to the data value 1 is read out to the data line DL[1], a sense amplifier operation as illustrated inFIG. 9is performed.

Immediately before timing t21, the sense amplifier block4maintains the switches AX[0] to AX[k] and AX[k+1] to AX[2k] of the selectors SEL1and SEL2, respectively, in an OFF state as illustrated inFIG. 10A. In addition, the sense amplifier block4maintains the switches SW1to SW8in an OFF state. As a result, the potentials of the data lines DL[0] and DL[1], the one ends of the capacitive elements C1and C2, and the other ends of the capacitive elements C1and C2are all at the reference level (for example, the ground level).

At timing t21, the sense amplifier block4turns on the switches SW1to SW4as illustrated inFIG. 10A. As a result, the data line DL[0], the data line DL[1], one end of the capacitive element C1, and one end of the capacitive element C2are connected, the reference voltage Vref is supplied from the voltage generation circuit5to the data lines DL[0] and DL[1] and the one ends of the capacitive elements C1and C2, and the potential thereof rises. That is, the electric charge is accumulated in the parasitic capacitance of the data line DL[0], the parasitic capacitance of the data line DL[1], one end of the capacitive element C1, and one end of the capacitive element C2by the voltage generation circuit5. As a result, the potential of the data line DL[0], the potential of the data line DL[1], the potential Vs[0] at one end of the capacitive element C1, and the potential Vs[1] at one end of the capacitive element C2are equipotential to each other, and all are substantially equal to the level of the reference voltage Vref. Thus, the reference for comparison by the sense amplifier (comparator)41is equally set.

When the data lines DL[0] and DL[1] and the one ends of the capacitive elements C1and C2reach the level of the reference voltage Vref at timing t22, the sense amplifier block4turns off the switches SW1and SW2at timing t23as illustrated inFIG. 10B. As a result, each of the data line DL[0], the data line DL[1], one end of the capacitive element C1, and one end of the capacitive element C2is in a floating state while being held at the level of the reference voltage Vref.

At timing t24, the sense amplifier block4turns on the switch SW5while maintaining the switch SW6in an OFF state as illustrated inFIG. 10B. As a result, the pulse A having the amplitude of the positive potential is supplied from the pulse A generation circuit6to the other end of the capacitive element C1, and the potential Vs[0] at the other end of the capacitive element C1is shifted to the positive side by an amount corresponding to the amplitude V1of the pulse A to reach V11(>0) as indicated by a dot-and-dash line inFIG. 9.

As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[0] and one end of the capacitive element C1according to the ratio between the parasitic capacitance value of the data line DL[0] and the capacitance value of the capacitive element C1. In response to this, the potential of the data line DL[0] is shifted in a direction in which the amplitude increases by a shift amount ΔVref1corresponding to the shift amount of the potential Vs[0] to reach V12(>Vref) as indicated by a dot-and-dash line inFIG. 9. That is, the following Expression 10 is established.
ΔVref1=V12−Vref=k1×(V11−0)  Expression 10

In Expression 10, the shift amount ΔVref1is an absolute value of the shift amount and is a positive value. k1is a positive coefficient that changes depending on the capacitance value of the capacitive element C1(for example, in proportion to the capacitance value of the capacitive element C1), and has a larger value as the capacitance value of the capacitive element C1is larger.

At timing t25, as illustrated inFIG. 10B, the sense amplifier block4selectively turns on one switch AX [k+1] of the plurality of switches AX [k+1] to AX[2k] in the selector SEL2. Accordingly, one selected local data line LDL[k+1] of the plurality of local data lines LDL[k+1] to LDL[2k] is connected to the data line DL[1].

When the data value 1 is stored in the memory cell MC, a signal corresponding to the data value 1 is read out from the memory cell MC to the data line DL[1] via the selected bit line BL and the selected local data line LDL, and the potential of the data line DL[1] rises from the level of the reference voltage Vref.

At timing t26, the potential of the data line DL[1] reaches the level V13increased by the voltage ΔVMC1corresponding to the data value 1 from the level of the reference voltage Vref. That is, the following Expression 11 is established.
V13=Vref+ΔVMC11Expression 11

At timing t27, the sense amplifier block4turns on the switch SW8while maintaining the switch SW7in an OFF state as illustrated inFIG. 10B. As a result, the pulse B having the amplitude of the negative potential is supplied from the pulse B generation circuit7to the other end of the capacitive element C2, and the potential Vs[1] at the other end of the capacitive element C2is shifted to the negative side by an amount corresponding to the amplitude of the pulse B to reach V14(<0) as indicated by the solid line inFIG. 9.

As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[1] and one end of the capacitive element C1according to the ratio between the parasitic capacitance value of the data line DL[1] and the capacitance value of the capacitive element C1. Accordingly, as indicated by a solid line inFIG. 9, the potential of the data line DL[1] is shifted in a direction in which the amplitude decreases by a shift amount ΔVs1proportional to the shift amount of the potential Vs[1] to reach V15(<V13). That is, the following Expression 12 is established.
ΔVs1=V13−V15=k1×(0−V14)  Expression 12

In Expression 12, the shift amount ΔVs1is an absolute value of the shift amount and is a positive value. k1is a positive coefficient that changes depending on the capacitance value of the capacitive element C1, and has a larger value as the capacitance value of the capacitive element C1is larger.

When the sense amplifier enable signal SAE is at the active level at timing t28, the sense amplifier41compares the level of the data line DL[1] with the level of the data line DL[0] at timing t29.

At this time, a signal amount ΔS11, which is a level difference between the signal for the data value 1 and the reference voltage, is expressed by the following Expression 13.
ΔS11=V15−V12Expression 13

According to Expressions 10 to 12, Expression 13 can be transformed into the following Expression 14.
ΔS11=ΔVMC11−ΔVref1−ΔVs1  Expression 14

As illustrated inFIG. 9and Expression 14, the signal amount ΔS11for the data value 1 is reduced by the amount by which the shift amount ΔVref1of the data line DL[0] and the shift amount ΔVs1of the data line DL[1] are subtracted from the voltage ΔVMC11corresponding to the data value 1, but is secured at a level sufficient for the comparison operation of the sense amplifier41.

As a result, the sense amplifier41can detect that the level of the data line DL[1] is higher than the level of the data line DL[0], and can output the comparison result SAOUT of the L level. The comparison result SAOUT of the L level indicates that the data value 1 is detected by the sense amplifier41. That is, in a case where a signal is read out to the data line DL[1], the data line DL[1] is connected to the inverting input terminal (−) of the sense amplifier41(comparator). Therefore, a value 1 logically inverted with respect to the comparison result SAOUT=L level (or 0) of the sense amplifier41is a data value to be detected.

On the other hand, in a case where a signal corresponding to the data value 0 is read out to the data line DL[1], a sense amplifier operation as illustrated inFIG. 11is performed.

At timings t31to t34, the sense amplifier block4performs the operation same as that at timings t21to t24illustrated inFIG. 9.

At timing t35, as illustrated inFIG. 10B, the sense amplifier block4selectively turns on one switch AX[k+1] of the plurality of switches AX[k+1] to AX[2k] in the selector SEL2. Accordingly, one selected local data line LDL[k+1] of the plurality of local data lines LDL[k+1] to LDL[2k] is connected to the data line DL[1].

When the data value 0 is stored in the memory cell MC, a signal corresponding to the data value 0 is read out from the memory cell MC to the data line DL[1] via the selected bit line BL and the selected local data line LDL. At timing t36, the potential of the data line DL[1] reaches the level V16changed by the voltage ΔVMC10(≈0) corresponding to the data value 0 with respect to the level of the reference voltage Vref. That is, the following Expression 15 is established.
V16=Vref+ΔVMC10≈Vref  Expression 15

At timing t37, the sense amplifier block4turns on the switch SW8while maintaining the switch SW7in an OFF state as illustrated inFIG. 10B. As a result, the pulse B having the amplitude of the negative potential is supplied from the pulse B generation circuit7to the other end of the capacitive element C2, and the potential Vs[1] at the other end of the capacitive element C2is shifted to the negative side by an amount corresponding to the amplitude of the pulse B to reach V14(<0) as indicated by the solid line inFIG. 11.

As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[1] and one end of the capacitive element C1according to the ratio between the parasitic capacitance value of the data line DL[1] and the capacitance value of the capacitive element C1. Accordingly, as indicated by a solid line inFIG. 11, the potential of the data line DL[1] is shifted in a direction in which the amplitude decreases by a shift amount ΔVs1proportional to the shift amount of the potential Vs[1] to reach V15(<V13). That is, the following Expression 16 is established.
ΔVs1=V16−V17=k1×(V14−0)  Expression 16

In Expression 16, the shift amount ΔVs1is an absolute value of the shift amount and is a positive value. k1is a positive coefficient that changes depending on the capacitance value of the capacitive element C1, and has a larger value as the capacitance value of the capacitive element C1is larger.

When the sense amplifier enable signal SAE is at the active level at timing t38, the sense amplifier41compares the level of the data line DL[1] with the level of the data line DL[0] at timing t39.

At this time, a signal amount ΔS10, which is a level difference between the signal for the data value 0 and the reference voltage, is expressed by the following Expression 17.
ΔS10=V12−V17Expression 17

According to Expressions 10 to 12, 15, and 16, Expression 17 can be transformed into the following Expression 18.
ΔS10=ΔVMC10+ΔVref1+ΔVs1  Expression 18

As illustrated inFIG. 11and Expression 18, the signal amount ΔS10for the data value 0 is increased by the addition of the shift amount ΔVref1of the data line DL[0] and the shift amount ΔVs1of the data line DL[1] with respect to the voltage ΔVMC10(≈0) corresponding to the data value 0, and is secured at a level sufficient for the comparison operation of the sense amplifier41.

As a result, the sense amplifier41can detect that the level of the data line DL[1] is lower than the level of the data line DL[0], and can output the comparison result SAOUT of the H level. A comparison result SAOUT of the H level indicates that the data value 0 is detected by the sense amplifier41. That is, the value 0 logically inverted with respect to the comparison result SAOUT=H level (or 1) of the sense amplifier41is a data value to be detected.

For example, in a case where there is no supply of the pulse B having the negative potential amplitude to the sense amplifier block4, the signal amount ΔS1′ when the signal corresponding to the data value 1 is read out to the data line DL[0] is expressed by the following Expression with ΔVs=0 in Expression 5.
ΔS1′=ΔVMC1−ΔVref  Expression 5′

The signal amount ΔS0′ when the signal corresponding to the data value 0 is read out to the data line DL[0] is expressed by the following Expression with ΔVs=0 in Expression 9.
ΔS0′=ΔVMC0+ΔVref  Expression 9′

At this time, since ΔVMC0≈0, in order to secure the signal amount ΔS0′, it is required to secure a large capacitance value of the capacitive element C2, set k2indicated in Expression 1 to a large value, and increase the ΔVref. The capacitance value of the capacitive element C2at this time is represented by Cref.

In addition, in a case where the pulse B is not supplied, the signal amount ΔS11′ when the signal corresponding to the data value 1 is read out to the data line DL[1] is expressed by the following Expression with ΔVs1=0 in Expression 14.
ΔS11′=ΔVMC11−ΔVref1  Expression 14′

The signal amount ΔS10′ at the time when the signal corresponding to the data value 0 is read out to the data line DL[1] is expressed by the following Expression with ΔVs1=0 in Expression 18.
ΔS10′=ΔVMC10+ΔVref1  Expression 18′

At this time, since ΔVMC10≈0, in order to secure the signal amount ΔS10′, it is required to secure a large capacitance value of the capacitive element C1, set k1indicated in Expression 10 to a large value, and increase the ΔVref1. The capacitance value of the capacitive element C1at this time is represented by Cref.

That is, when the pulse B is not supplied, the capacitance values of the capacitive elements C1and C2are set to a relatively large value Cref. Therefore, as illustrated inFIG. 12A, the length of a period Tpr in which electric charges are accumulated in the parasitic capacitance of the data line DL[0], the parasitic capacitance of the data line DL[1], one end of the capacitive element C1, and one end of the capacitive element C2to make the potentials equipotential at the reference voltage Vref is prolonged. In addition, after the potentials are held at the reference voltage Vref for the predetermined period Thd, the parasitic capacitance of the data line DL[1] and one end of the capacitive element C2are shifted at a level corresponding to the amplitude of the pulse A, and the length of a period Tsn in which electric charges are accumulated in the parasitic capacitance of the data line DL[0] and one end of the capacitive element C1to have the potential corresponding to the signal level is prolonged.

On the other hand, since there is the supply of the pulse B, the securing of a signal amount ΔS0expressed by Expression 9 can be shared by a ΔVref and a ΔVs, and the securing of the signal amount ΔS10expressed by Expression 18 can be shared by a ΔVref1and a ΔVs1, k2represented by Expression 1 and k1represented by Expression 10 can be set to values about half of those in a case where there is no supply of the pulse B, and the capacitance values of the capacitive elements C1and C2can be set to half the value, that is Cref/2. Therefore, as illustrated inFIG. 12B, the length of a period Tpr1in which electric charges are accumulated in the parasitic capacitance of the data line DL[0], the parasitic capacitance of the data line DL[1], one end of the capacitive element C1, and one end of the capacitive element C2to make the potentials equipotential at the reference voltage Vref can be shortened (for example, to less than or equal to half). In addition, after the potentials are held at the reference voltage Vref for the predetermined period Thd, the parasitic capacitance of the data line DL[1] and one end of the capacitive element C2are shifted at a level corresponding to the amplitude of the pulse A, and electric charge are accumulated in the parasitic capacitance of the data line DL[0] and one end of the capacitive element C1to have a potential corresponding to the signal level, and the length of a period Tsn1in which the potential is shifted at the level corresponding to the amplitude of the pulse B can be shortened (for example, to less than or equal to half).FIGS. 12A and 12Bare diagrams illustrating an increase in speed of the sense amplifier operation according to the capacitance value of the capacitive element;FIG. 12Aillustrates a sense amplifier operation when a signal is read out to the data line DL[0] in a case where the capacitance values of the capacitive elements C1and C2are a relatively large value Cref, andFIG. 12Billustrates a sense amplifier operation when a signal is read out to the data line DL[0] in a case where the capacitance values of the capacitive elements C1and C2are a small value Cref/2.

Since there is the supply of the pulse B, the timing at which the equipotential is completed can be advanced by ΔT1, and the timing at which the preparation for the comparison operation by the sense amplifier41is completed can be advanced by ΔT2, as indicated by white arrows inFIGS. 12A and 12B.

As described above, in the present embodiment, in the sense amplifier operation, the semiconductor storage device1supplies the positive potential pulse to the other end of the capacitive element in which the reference voltage Vref is accumulated and supplies the negative potential pulse to the other end of the capacitive element in which the signal is accumulated. As a result, the signal amount can be secured while speeding up the sense amplifier operation.

In the operation illustrated inFIG. 6, the operation at timing t4, the operation at timing t5, and the operation at timing t7may be completed by timing t8at which the sense amplifier enable signal SAE is active. In addition, the order of the operation at timing t4, the operation at timing t5, and the operation at timing t7may be changed.

In the operation illustrated inFIG. 8, the operation at timing t14, the operation at timing t15, and the operation at timing t17may be completed by timing t18at which the sense amplifier enable signal SAE is active. In addition, the order of the operation at timing t14, the operation at timing t15, and the operation at timing t17may be changed.

In the operation illustrated inFIG. 9, the operation at timing t24, the operation at timing t25, and the operation at timing t27may be completed by timing t28at which the sense amplifier enable signal SAE is active. In addition, the order of the operation at timing t24, the operation at timing t25, and the operation at timing t27may be changed.

In the operation illustrated inFIG. 11, the operation at timing t34, the operation at timing t35, and the operation at timing t37may be completed by timing t38at which the sense amplifier enable signal SAE is active. In addition, the order of the operation at timing t34, the operation at timing t35, and the operation at timing t37may be changed.

Alternatively, the positive potential amplitude of the pulse A supplied to the sense amplifier block4may be variable. For example, as illustrated inFIGS. 13 and 14, the pulse A generation circuit6may have V1and V21as candidates for the positive potential amplitude of the pulse A.FIGS. 13 and 14are waveform diagrams illustrating an operation of the sense amplifier block in the first modification of the embodiment. V21is, for example, an amplitude value satisfying
0<V21<V1Expression 19.

Immediately before the timings t4iand t14i, the semiconductor storage device1identifies, from a bit error rate or the like for the data value obtained in the previous sense amplifier operation, in which sense amplifier operation of the data value 1 and the data value 0 a bit error is likely to occur. The semiconductor storage device1controls the pulse A generation circuit6so as so as to generate the pulse A with an amplitude according to the identified result. The pulse A generation circuit6generates the pulse A with an amplitude according to control from the semiconductor storage device1to supply the generated pulse A to the sense amplifier block4.

In a case where the pulse A with the amplitude V21is supplied, the sense amplifier block4turns on the switch SW7while maintaining the switch SW8in an OFF state as illustrated inFIG. 7Bat timing t4iillustrated inFIG. 13. As a result, the pulse A having the amplitude V21of the positive potential is supplied from the pulse A generation circuit6to the other end of the capacitive element C2, and the potential Vs[1] of the other end of the capacitive element C2is shifted to the positive side by an amount corresponding to the amplitude V21of the pulse A to reach V21(>0) as indicated by a two-dot chain line inFIG. 13.

As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[1] and one end of the capacitive element C2according to the ratio between the parasitic capacitance value of the data line DL[1] and the capacitance value of the capacitive element C2. Accordingly, as indicated by a two-dot chain line inFIG. 13, the potential of the data line DL[1] is shifted in a direction in which the amplitude increases by a shift amount ΔVref2corresponding to the shift amount of the potential Vs[1] to reach V22(>Vref). That is, the following Expression 20 is established.
ΔVref2=V22−Vref=k2×(V21−0)  Expression 20

At this time, the following Expression 21 is established from Expressions 19 and 20.
0<ΔVref2<ΔVref  Expression 21

When the sense amplifier enable signal SAE is at the active level at timing t8i, the sense amplifier41compares the level of the data line DL[0] with the level of the data line DL[1] at timing t9i.

At this time, a signal amount ΔS21, which is a level difference between the signal for the data value 1 and the reference voltage, is expressed by the following Expression 22.
ΔS21=V5−V22Expression 22

According to Expressions 2, 3, and 20, Expression 22 can be transformed into the following Expression 23.
ΔS21=ΔVMC1−ΔVref2−ΔVsExpression 23

The following Expression 24 is established from Expressions 5, 21, and 23.
ΔS1<ΔS21Expression 24

In a case where the pulse A with the amplitude V21is supplied, the sense amplifier block4turns on the switch SW7while maintaining the switch SW8in an OFF state as illustrated inFIG. 7Bat timing t14iillustrated inFIG. 14. As a result, the pulse A having the amplitude V21of the positive potential is supplied from the pulse A generation circuit6to the other end of the capacitive element C2, and the potential Vs[1] of the other end of the capacitive element C2is shifted to the positive side by an amount corresponding to the amplitude V21of the pulse A to reach V21(>0) as indicated by a two-dot chain line inFIG. 14.

As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[1] and one end of the capacitive element C2according to the ratio between the parasitic capacitance value of the data line DL[1] and the capacitance value of the capacitive element C2. Accordingly, as indicated by a two-dot chain line inFIG. 14, the potential of the data line DL[1] is shifted in a direction in which the amplitude increases by a shift amount ΔVref2corresponding to the shift amount of the potential Vs[1] to reach V22(>Vref). That is, the following Expression 25 is established.
ΔVref2=V22−Vref=k1×(V21−0)  Expression 25

At this time, the following Expression 26 is established from Expressions 19 and 25.
0<ΔVref2<ΔVref  Expression 26

When the sense amplifier enable signal SAE is at the active level at timing t18i, the sense amplifier41compares the level of the data line DL[0] with the level of the data line DL[1] at timing t19i.

At this time, a signal amount ΔS20, which is a level difference between the signal for the data value 0 and the reference voltage, is expressed by the following Expression 27.
ΔS20=V22−V7Expression 27

According to Expressions 2, 3, and 25, Expression 27 can be transformed into the following Expression 28.
ΔS21=ΔVMC0+ΔVref2+ΔVsExpression 28

The following Expression 29 is established from Expressions 9, 21, and 28.
ΔS0>ΔS20Expression 29

Here, as shown in Expressions 24 and 29, in a case where the amplitude of the pulse A is controlled to V21, the signal amount for the data value 1 increases, and the signal amount for the data value 0 decreases. Therefore, the semiconductor storage device1may control the pulse A generation circuit6so as to generate the pulse A with the amplitude V21in a case where the bit error is likely to occur in the data value 1, and may control the pulse A generation circuit6so as to generate the pulse A with the amplitude V1in a case where the bit error is likely to occur in the data value 0. As a result, the semiconductor storage device1can dynamically improve the bit error rate.

Alternatively, the negative potential amplitude of the pulse B supplied to the sense amplifier block4may be variable. For example, as illustrated inFIGS. 15 and 16, the pulse B generation circuit7may have V4and V34as candidates for the negative potential amplitude of the pulse B.FIGS. 15 and 16are waveform diagrams illustrating an operation of the sense amplifier block4in the second modification of the embodiment. V34is an amplitude value satisfying
0>V34>V4Expression 30.

Immediately before the timings t7jand t17j, the semiconductor storage device1identifies, from a bit error rate or the like for the data value obtained in the previous sense amplifier operation, in which sense amplifier operation of the data value 1 and the data value 0 a bit error is likely to occur. The semiconductor storage device1controls the pulse B generation circuit7so as to generate the pulse B with an amplitude according to the identified result. The pulse B generation circuit7generates the pulse B with an amplitude according to control from the semiconductor storage device1to supply the generated pulse B to the sense amplifier block4.

In a case where the pulse B with the amplitude V34is supplied, the sense amplifier block4turns on the switch SW6while maintaining the switch SW5in an OFF state as illustrated inFIG. 7Bat timing t7jillustrated inFIG. 15. As a result, the pulse B having the amplitude V34of the negative potential is supplied from the pulse B generation circuit7to the other end of the capacitive element C1, and the potential Vs[1] at the other end of the capacitive element C1is shifted to the negative side by an amount corresponding to the amplitude V34of the pulse B to reach V34(<0) as indicated by a dotted line inFIG. 15.

As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[0] and one end of the capacitive element C1according to the ratio between the parasitic capacitance value of the data line DL[0] and the capacitance value of the capacitive element C1. Accordingly, as indicated by a dotted line inFIG. 15, the potential of the data line DL[0] is shifted in a direction in which the amplitude decreases by a shift amount ΔVs3corresponding to the shift amount of the potential Vs[1] to reach V35(<V3). That is, the following Expression 31 is established.
ΔVs3=V3−V35=k1×(0−V34)  Expression 31

At this time, the following Expression 32 is established from Expressions 30 and 31.
0<ΔVs<ΔVs3  Expression 32

When the sense amplifier enable signal SAE is at the active level at timing t8j, the sense amplifier41compares the level of the data line DL[0] with the level of the data line DL[1] at timing t9j.

At this time, a signal amount ΔS31, which is a level difference between the signal for the data value 1 and the reference voltage, is expressed by the following Expression 33.
ΔS31=V35−V2Expression 33

According to Expressions 2, 3, and 31, Expression 33 can be transformed into the following Expression 34.
ΔS31=ΔVMC1−ΔVref−ΔVs3  Expression 34

The following Expression 35 is established from Expressions 5, 32, and 34.
ΔS1<ΔS31Expression 35

In a case where the pulse B with the amplitude V34is supplied, the sense amplifier block4turns on the switch SW6while maintaining the switch SW5in an OFF state as illustrated inFIG. 7Bat timing t17jillustrated inFIG. 16. As a result, the pulse B having the amplitude V34of the negative potential is supplied from the pulse B generation circuit7to the other end of the capacitive element C1, and the potential Vs[0] of the other end of the capacitive element C1is shifted to the negative side by an amount corresponding to the amplitude V34of the pulse B to reach V34(<0) as indicated by a dotted line inFIG. 16.

As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[0] and one end of the capacitive element C1according to the ratio between the parasitic capacitance value of the data line DL[0] and the capacitance value of the capacitive element C1. Accordingly, as indicated by a dotted line inFIG. 16, the potential of the data line DL[0] is shifted in a direction in which the amplitude decreases by a shift amount ΔVs3corresponding to the shift amount of the potential Vs[0] to reach V37(<Vref). That is, the following Expression 36 is established.
ΔVs3=V6−V37=k1×(0−V34)  Expression 36

At this time, the following Expression 37 is established from Expressions 30 and 36.
0<ΔVs3<ΔVsExpression 37

When the sense amplifier enable signal SAE is at the active level at timing t18j, the sense amplifier41compares the level of the data line DL[0] with the level of the data line DL[1] at timing t19j.

At this time, a signal amount ΔS30, which is a level difference between the signal for the data value 0 and the reference voltage, is expressed by the following Expression 38.
ΔS30=V2−V37Expression 38

According to Expressions 2, 3, and 36, Expression 38 can be transformed into the following Expression 39.
ΔS30=ΔVMC0+ΔVref+ΔVs3  Expression 39

The following Expression 40 is established from Expressions 9, 32, and 39.
ΔS0>ΔS30Expression 40

Here, as shown in Expressions 35 and 40, in a case where the amplitude of the pulse B is controlled to V34, the signal amount for the data value 1 increases, and the signal amount for the data value 0 decreases. Therefore, the semiconductor storage device1may control the pulse B generation circuit7so as to generate the pulse B with the amplitude V34in a case where the bit error is likely to occur in the data value 1, and may control the pulse B generation circuit7so as to generate the pulse B with the amplitude V4in a case where the bit error is likely to occur in the data value 0. As a result, the semiconductor storage device1can dynamically improve the bit error rate.

Alternatively, the positive potential amplitude of the pulse A supplied to the sense amplifier block4may be variable, and the positive potential amplitude of the pulse B supplied to the sense amplifier block4may be variable. For example, as illustrated inFIGS. 17 and 18, the pulse A generation circuit6may have V1and V21as candidates for the positive potential amplitude of the pulse A, and the pulse B generation circuit7may have V4and V34as candidates for the negative potential amplitude of the pulse B.FIGS. 17 and 18are waveform diagrams illustrating an operation of the sense amplifier block in the third modification of the embodiment. That is, as the third modification of the embodiment, an operation in which the operation of the first modification and the operation of the second modification are combined may be performed. Immediately before the timings t4kand t14k, the semiconductor storage device1identifies, from a bit error rate or the like for the data value obtained in the previous sense amplifier operation, in which sense amplifier operation of the data value 1 and the data value 0 a bit error is likely to occur. The semiconductor storage device1controls the pulse A generation circuit6so as to generate the pulse A with an amplitude according to the specified result, and controls the pulse B generation circuit7so as to generate the pulse B with an amplitude according to the identified result. The pulse A generation circuit6generates the pulse A with an amplitude according to control from the semiconductor storage device1to supply the generated pulse A to the sense amplifier block4. The pulse B generation circuit7generates the pulse B with an amplitude according to control from the semiconductor storage device1to supply the generated pulse B to the sense amplifier block4.

In a case where the pulse A with the amplitude V21is supplied and the pulse B with the amplitude V34is supplied, in the sense amplifier block4, the potential Vs[1] at the other end of the capacitive element C2is shifted to the positive side by an amount corresponding to the amplitude V21of the pulse A to reach V21(>0) at timing t4killustrated inFIG. 17as illustrated by a two-dot chain line inFIG. 17. As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[1] and one end of the capacitive element C2according to the ratio between the parasitic capacitance value of the data line DL[1] and the capacitance value of the capacitive element C2. Accordingly, as indicated by a two-dot chain line in FIG.18, the potential of the data line DL[1] is shifted in a direction in which the amplitude increases by a shift amount ΔVref2corresponding to the shift amount of the potential Vs[1] to reach V22(>Vref).

At timing t17k, in the sense amplifier block4, the potential Vs[0] at the other end of the capacitive element C1is shifted to the negative side by an amount corresponding to the amplitude V34of the pulse B to reach V34(<0) as indicated by a dotted line inFIG. 18. As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[0] and one end of the capacitive element C1according to the ratio between the parasitic capacitance value of the data line DL[0] and the capacitance value of the capacitive element C1. Accordingly, as indicated by a dotted line inFIG. 16, the potential of the data line DL[0] is shifted in a direction in which the amplitude decreases by a shift amount ΔVs3corresponding to the shift amount of the potential Vs [0] to reach V37(<Vref). When the sense amplifier enable signal SAE is at the active level at timing t18k, the sense amplifier41compares the level of the data line DL[0] with the level of the data line DL[1] at timing t19k.

At this time, a signal amount ΔS41, which is a level difference between the signal for the data value 0 and the reference voltage, is expressed by the following Expression 41.
ΔS44=V35−V22Expression 41

In addition, in a case where the pulse A with the amplitude V21is supplied and the pulse B with the amplitude V34is supplied, in the sense amplifier block4, the potential Vs[1] at the other end of the capacitive element C2is shifted to the positive side by an amount corresponding to the amplitude V21of the pulse A to reach V21(>0) at timing t14killustrated inFIG. 18as illustrated by a two-dot chain line inFIG. 18. As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[1] and one end of the capacitive element C2according to the ratio between the parasitic capacitance value of the data line DL[1] and the capacitance value of the capacitive element C2. Accordingly, as indicated by a two-dot chain line inFIG. 18, the potential of the data line DL[1] is shifted in a direction in which the amplitude increases by a shift amount ΔVref2corresponding to the shift amount of the potential Vs[1] to reach V22(>Vref).

At timing t18k, in the sense amplifier block4, the potential Vs[0] at the other end of the capacitive element C1is shifted to the negative side by an amount corresponding to the amplitude V34of the pulse B to reach V34(<0) as indicated by a dotted line inFIG. 18. As a result, the sense amplifier block4redistributes the electric charge accumulated in the data line DL[0] and one end of the capacitive element C1according to the ratio between the parasitic capacitance value of the data line DL[0] and the capacitance value of the capacitive element C1. Accordingly, as indicated by a dotted line inFIG. 18, the potential of the data line DL[0] is shifted in a direction in which the amplitude decreases by a shift amount ΔVs3corresponding to the shift amount of the potential Vs[0] to reach V37(<Vref).

When the sense amplifier enable signal SAE is at the active level at timing t18k, the sense amplifier41compares the level of the data line DL[0] with the level of the data line DL[1] at timing t19k.

At this time, a signal amount ΔS40, which is a level difference between the signal for the data value 0 and the reference voltage, is expressed by the following Expression 42.
ΔS40=V22−V37Expression 42

That is, as illustrated inFIGS. 17 and 18and Expressions 4, 8, 22, 27, 33, 38, 41, and 42, the sense amplifier block4can vary the signal amount in a plurality of stages by a combination of the amplitude of the supplied pulse A and the amplitude of the supplied pulse B. The sense amplifier block4may vary signal amounts ΔS1, ΔS31, ΔS21, and ΔS41in four stages illustrated inFIG. 17as signal amounts for the data value 1. The magnitude relationship of each signal amount can vary depending on how the amplitude level of the pulse A and the amplitude level of the pulse B are taken. As an example, the signal amount for the data value 1 may have a magnitude relationship expressed in Expression 43.
ΔS1<ΔS31<ΔS21<ΔS41Expression 43

Similarly, the sense amplifier block4may vary the signal amounts ΔS0, ΔS30, ΔS20, and ΔS40in four stages illustrated inFIG. 18as the signal amount for the data value 0. The magnitude relationship of each signal amount can vary depending on how the amplitude level of the pulse A and the amplitude level of the pulse B are taken. As an example, the signal amount for the data value 0 may have a magnitude relationship expressed in Expression 44.
ΔS0<ΔS30<ΔS20<ΔS40Expression 44

Alternatively, as illustrated inFIG. 19, in the sense amplifier block4p, the capacitance values of the capacitive elements connected to the two input nodes41aand41bof the sense amplifier41may be variable.FIG. 19is a diagram illustrating a configuration of the sense amplifier block4paccording to the fourth modification of the embodiment.

When n is an arbitrary integer of 2 or more, the sense amplifier block4pincludes a plurality of capacitive elements C1-1to C1-n, a plurality of capacitive elements C2-1to C2-n, a plurality of switches SW3-1to SW3-n, a plurality of switches SW4-1to SW4-n, a plurality of switches SW5-1to SW5-n, a plurality of switches SW6-1to SW6-n, a plurality of switches SW7-1to SW7-n, and a plurality of switches SW8-1to SW8-n.

The plurality of capacitive elements C1-1to C1-ncorresponds to the plurality of switches SW3-1to SW3-n, corresponds to the plurality of switches SW5-1to SW5-n, and corresponds to the plurality of switches SW6-1to SW6-n. Each of the capacitive elements C1-1to C1-nis connected to the data line DL[0] via the corresponding switch SW3, connected to the pulse A generation circuit6via the corresponding switch SW5, and connected to the pulse B generation circuit7via the corresponding switch SW6. Each of the capacitive elements C1-1to C1-nhas an equal capacitance value, for example, Cref/n.

The plurality of capacitive elements C2-1to C2-ncorresponds to the plurality of switches SW4-1to SW4-n, corresponds to the plurality of switches SW7-1to SW7-n, and corresponds to the plurality of switches SW8-1to SW8-n. Each of the capacitive elements C2-1to C2-nis connected to the data line DL[1] via the corresponding switch SW4, connected to the pulse A generation circuit6via the corresponding switch SW7, and connected to the pulse B generation circuit7via the corresponding switch SW8. Each of the capacitive elements C2-1to C2-nhas an equal capacitance value, for example, Cref/n.

The sense amplifier block4pcan vary the combined capacitance value of the capacitive element C1connected to the input node41aof the sense amplifier41by controlling the number of switches to be turned on of the plurality of switches SW3-1to SW3-n, and can vary the combined capacitance value of the capacitive element C2connected to the input node41aof the sense amplifier41by controlling the number of switches to be turned on of the plurality of switches SW4-1to SW4-n. The sense amplifier block4pcan set the combined capacitance value of the capacitive element C1connected to the input node41aof the sense amplifier41to m×Cref/n by turning on the m switches SW3(m is an integer of n or less), and can set the combined capacitance value of the capacitive element C2connected to the input node41bof the sense amplifier41to m×Cref/n by turning on the m switches SW4. As a result, the switching operation of the amplitudes of the data lines DL[0] and DL[1] as illustrated inFIGS. 13 to 18can be realized by varying the combined capacitance value of the capacitive elements C1and C2.

Alternatively, unlike the configuration illustrated inFIG. 19, the sense amplifier block4smay have a configuration in which capacitance values of a plurality of capacitive elements are varied to be different in binary as illustrated inFIG. 20.FIG. 20is a diagram illustrating a configuration of a sense amplifier block4saccording to the fifth modification of the embodiment. The sense amplifier block4sincludes a plurality of capacitive elements C1s-1to C1s-nand a plurality of capacitive elements C2s-1to C2s-nin place of the plurality of capacitive elements C1-1to C1-nand the plurality of capacitive elements C2-1to C2-n(seeFIG. 19). The plurality of capacitive elements C1s-1, C1s-2, . . . , and C1s-nhas capacitance values different from each other, which are Cref/21, Cref/22, . . . , and Cref/2n, respectively. The plurality of capacitive elements C2s-1, C2s-2, . . . , and C2s-nhas capacitance values different from each other, which are Cref/21, Cref/22, . . . , and Cref/2n, respectively.

The combined capacitance value of the capacitive element C1connected to the input node41aof the sense amplifier41can be varied in a binary manner by controlling a switch to be turned on of the plurality of switches SW3-1to SW3-n, and the combined capacitance value of the capacitive element C2connected to the input node41aof the sense amplifier41can be varied in a binary manner by controlling a switch to be turned on of the plurality of switches SW4-1to SW4-n.

The sense amplifier block4pcan set the combined capacitance value of the capacitive element C1connected to the input node41aof the sense amplifier41to Cref/4 by selectively turning on the switch SW3-2of the plurality of switches SW3-1to SW3-n, and can set the combined capacitance value of the capacitive element C2connected to the input node41bof the sense amplifier41to Cref/4 by selectively turning on the switch SW4-2of the plurality of switches SW4-1to SW4-n.

The sense amplifier block4pcan set the combined capacitance value of the capacitive element C1connected to the input node41aof the sense amplifier41to Cref/2 by selectively turning on the switch SW3-1of the plurality of switches SW3-1to SW3-n, and can set the combined capacitance value of the capacitive element C2connected to the input node41bof the sense amplifier41to Cref/2 by selectively turning on the switch SW4-1of the plurality of switches SW4-1to SW4-n.

The sense amplifier block4pcan set the combined capacitance value of the capacitive element C1connected to the input node41aof the sense amplifier41to 3Cref/4 by selectively turning on the switches SW3-1and SW3-2of the plurality of switches SW3-1to SW3-n, and can set the combined capacitance value of the capacitive element C2connected to the input node41bof the sense amplifier41to 3Cref/4 by selectively turning on the switches SW4-1and SW4-2of the plurality of switches SW4-1to SW4-n.

As a result, the switching operation of the amplitudes of the data lines DL[0] and DL[1] as illustrated inFIGS. 13 to 18can be realized by varying the combined capacitance value of the capacitive elements C1and C2.