Increase in deep trench capacitance by a central ground electrode

A semiconductor device includes a trench formed in a substrate, and a diffusion region surrounding the trench to form a buried plate. A first conductive material is formed in the trench and connects to the buried plate through a bottom of the trench to form a first electrode. A second conductive material is disposed in the trench to form a second electrode. A node dielectric layer is formed between the first electrode and the second electrode.

BACKGROUND

1. Technical Field

This disclosure relates to semiconductor fabrication, and more particularly, to a structure and method to significantly increase the capacitance by forming a central ground electrode in a deep trench.

2. Description of the Related Art

Trench capacitor cells in dynamic random access memories (DRAMs) are commonly formed in a substrate. Trench capacitor cells include a trench having a storage node formed therein. The storage node acts as a first electrode to the trench capacitor. A buried plate is formed externally to the trench to form an outer plate of the trench capacitor, that is, the second electrode of the capacitor. The buried plate is formed by doping the silicon surrounding the etched trench which is then coated with a node dielectric and filled with a conductive material serving as the storage node or inner plate of the capacitor. The inner plate (or storage node) stores the signal charge and is connected to the drain of a transfer transistor switched by a wordline.

As smaller feature sizes are needed for future generations of trench capacitors, the conventional trench capacitors are pushed to the limits of their capabilities in terms of performance. One primary problem with dynamic random access (DRAM) designs using deep trench capacitor storage cells is maintaining a high capacity with decreasing feature size and keeping the charge in the deep trench from leaking out of the storage node. The conventional trench capacitors begin to lose capacitive area with smaller feature sizes and are susceptible to current leakage.

Therefore, a need exists for an improved trench capacitor for increasing capacitance and reducing current leakage therefrom.

SUMMARY OF THE INVENTION

A semiconductor device includes a trench formed in a substrate, and a diffusion region surrounding the trench to form a buried plate. A first conductive material is formed in the trench and connects to the buried plate through a bottom of the trench to form a first electrode. A second conductive material is disposed in the trench to form a second electrode. A node dielectric layer is formed between the first electrode and the second electrode.

A method for forming a trench capacitor provides a trench in a semiconductor substrate, forms a dopant rich layer in contact with the substrate in the trench and forms a spacer layer over the dopant rich layer in the trench. The substrate is exposed at a bottom of the trench. The spacer layer may optionally be removed. A first doped conductive material is formed in the trench and etched to form at least one pillar which extends from a bottom of the trench. Dopants are driven into the substrate from the dopant rich layer and the first doped conductive material to form a buried plate. The buried plate and the first doped conductive material form a first electrode. The dopant rich layer is removed and a dielectric layer is formed over the substrate in the trench and over the first doped conductive material. A second conductive material is formed in the trench over the dielectric layer to form a second electrode.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention provides a structure and method for forming a central electrode in a deep trench. The central ground electrode provides an increase in capacitance for deep trench capacitors by providing increased surface area for a deep trench capacitor electrodes. The present invention is not limited to deep trench capacitors and may be employed in other semiconductor structures.

Referring now in specific detail to the drawings in which like reference numerals identify similar or identical elements throughout the several views, and initially toFIG. 1, a partially fabricated semiconductor device10is shown. Semiconductor device10includes a substrate12, preferably monocrystalline silicon, although other substrate materials may be employed. Device10may be included as part of a semiconductor wafer and device10may include a dynamic random access memory (DRAM), a static random access memory (SRAM) or any other device structure, which includes trenches.

A trench mask14is patterned on substrate12by known lithography processes. Trench mask14may include a pad stack, and or a hard mask (e.g., a silicate glass material). Openings16in patterned trench mask14are employed to permit etching of the underlying substrate12. Substrate12is etched, preferably by an anisotropic etch process (e.g., reactive ion etching) to form a trench18in substrate12.

Referring toFIG. 2, a doped oxide layer20is deposited in trench18and over trench mask14. This may be performed as a non-conformal fill of trench18. In one embodiment, layer20includes a doped TEOS material which may include, for example, Arsenic dopants or a doped silicate glass, such as, for example, Arsenic silicate glass (ASG). Layer20is preferably deposited to a thickness of approximately ¼ of the thickness of the trench at a bottom dimension (e.g., the bottom dimension being, for example, a critical dimension (CD) or width of trench18), although other thicknesses may be employed.

A sidewall-spacer layer22is formed over layer20. Layer22may include, for example, a doped amorphous silicon layer. Dopants in layer22may include, for example, Arsenic. Layer22is deposited to a thickness sufficient to protect sidewalls of trench18(e.g., layer20on sidewalls) during an etch step which removes spacer layer22from a bottom of trench18, as described herein below.

Referring toFIG. 3, layer22is opened up at the bottom of trench18. This is preferably provided by performing an anisotropic silicon etch. Spacer layer22on sidewalls of trench18remains and protects layer20on the sidewalls. Etching continues until layer20is exposed in at a bottom portion17of trench18.

A wet etch, for example an HF or dilute HF wet etch, is employed to remove layer22from the bottom of trench18. Exposed portions26of layer22are not completely removed by the wet etch. Wet etch may employ other etchants, for example, ammonium hydroxide, etc. It is preferably however, to employ an HF as a last step in the wet etch process to ensure native oxide is removed from a surface28of substrate12. Layer22may then be removed from layer20on the sidewalls of trench18(FIG.4). This may be performed by removing layer22by a wet etch selective to layer20. Removing layer22is optional.

Referring toFIG. 4, a conductive material30, for example, doped polysilicon or doped amorphous silicon, is deposited in trench18. In one embodiment, conductive material includes Arsenic doped polysilicon or Arsenic doped amorphous silicon. Conductive material30is deposited to fill trench18and contacts the remaining portions of layer20(and layer22, if present). Conductive material30will be employed to form a center electrode.

Referring toFIG. 5, conductive material30is recessed in trench18. Recessing may be performed by an anisotropic silicon etch. In one embodiment, trench18is about 6 microns deep, the etch process may etch conductive material30to a top-most level of about 2 microns down into trench18and enhance a seam or center trench32. Center trench32is expanded down into trench18through conductive material30. One or more pillars are formed in material30as a result of the trench geometry and the nature of RIE.

In alternate embodiments, the etching process may be employed with lithographic patterning or other etching techniques to pattern one or more pillars within trench18. An etch mask may be formed on a top surface to begin seam32, which can be extended deeper into trench by extended etching.

Referring toFIG. 6, exposed portions of layer20are removed by, for example, a wet etch selective to conductive material30, for example using HF, dilute HF or buffered HF. Portions34of layer20which are covered by conductive material30remain in trench18.

A high temperature anneal is performed to drive dopants from portions34of layer20into substrate12and into conductive material30. In addition, dopants are driven from conductive material30into substrate12. The anneal temperatures are preferably between about 600 degrees Celsius and 1200 degrees Celsius. The anneal is preferably performed in an inert environment. Flowing oxygen may be employed during temperature ramp up of the anneal to minimize autodoping of the upper part of the trench. Outdiffusion from the anneal process forms a buried plate35which surrounds trench18.

Portions34of layer20are removed by, for example, a wet etch selective to conductive material30, using for example HF.

Referring toFIG. 7, remaining portions of layer20are removed from the sidewalls of trench18. A wet etch process which selectively removes layer20relative to conductive material30and substrate12is employed. Wet etching may include, for example, HF, dilute, HF or buffered HF etchants. Substrate12and conductive material30should be exposed in places where layer20existed.

A node dielectric layer40is deposited over all surfaces to cover exposed sidewalls of substrate12and exposed surfaces of conductive material30. Conductive material30forms a center electrode44. Node dielectric layer40preferably includes a nitride material, such as silicon nitride or silicon oxy-nitride. In one embodiment, an oxidation may be performed to oxidize a silicon nitride node dielectric layer to from silicon oxy-nitride.

Node dielectric layer40forms a capacitor dielectric layer. Node dielectric layer40may be from about 1 nm to about 7 nm in thickness. Other thicknesses may be employed depending of the specific needs of a given design.

Referring toFIG. 8, trench18is filled with a conductive material42. Conductive material42may include a doped amorphous silicon, preferably an Arsenic-doped amorphous silicon, to fill trench18. Conductive material42is preferably deposited by a chemical vapor deposition (CVD) process or a plasma enhanced CVD process. In this way, conductive material42fills in any gaps or spaces between portions of electrode44and between electrode44and substrate12.

An anisotropic etch process is performed to recess conductive material42in trench18. Node dielectric layer40which is exposed by the recessing of conductive material42is removed by using a wet etch process. Processing continues on device10as is known in the art. For example, a trench collar deposition and formation process are followed by shallow trench isolation, gate formation, access transistor dopant implantation and device formation, contact and metallization formation, etc.

Center electrode44and buried plate35form a first electrode of a deep trench capacitor. A second electrode of the deep trench capacitor is formed by conductive material42. By the present invention, surface area shared between the first and second electrodes is significantly increased, for example, an increase in surface area of between about 10% and about 150% may be achieved. Greater surface areas are contemplated and may depend on the design of the device.

It is to be understood that the present invention may include a plurality of different formations for center electrode44. For example, center electrode may include a single pillar extending from a bottom portion of the trench, or include a plurality of pillars extending from a bottom portion of the trench. As illustratively shown inFIG. 9, a single pillar48is depicted for electrode44. A collar deposition layer50is also shown for forming a collar in later processing steps. Based on the foregoing one skilled in the art may envision other variation and embodiments of the present invention.