Implementing bufferless Direct Memory Access (DMA) controllers using split transactions

According to one embodiment a method for implementing bufferless DMA controllers using split transaction functionality is presented. One embodiment of the method comprises, generating a write command from a disk controller directed to a destination unit, the write command including an identifier, generating a read command from the disk controller directed to a source unit, the read command including an identifier which matches the identifier in the write command, the source unit transmitting read data on a split transaction bus, the read data including the identifier of the read command, and receiving the read data at the destination unit via the split transaction bus if the identifier of the read data matches the identifier of the write command.

FIELD OF THE INVENTION

The present embodiments of the invention relate generally to input/output (I/O) processors and, more specifically, relate to direct memory access (DMA) controllers.

BACKGROUND

Many storage, networking, and embedded applications require fast input/output (I/O) throughput for optimal performance. I/O processors allow servers, workstations, and storage subsystems to transfer data faster, reduce communication bottlenecks, and improve overall system performance by offloading I/O processing functions from a host central processing unit (CPU).

Typically, the CPU(s) in the I/O processors program direct memory access (DMA) controller(s) to move data between specified sources and destinations, such as between local memory and host memory. Once the DMA controller is programmed, it will generate a read command to the source's interface or controller. This controller or interface will generate the read command for the source, and once it obtains the read data will place that data on the bus to the DMA controller. Typical DMA controllers include buffers to temporarily store data when the data is moved between sources and destinations, such as between host and local memories. The DMA controller will accept the read data and store it in the DMA controller data buffers. At this time, the DMA controller will generate a write command to the destination's interface or controller. The destination interface or controller will accept this write command. Finally, the DMA controller provides the write data being stored in the DMA controller data buffers to the destination interface or controller in order to be written to the destination.

The use of DMA controller data buffers can lead to increased area requirements, increased power requirements, and added complexity to the I/O processor. The use of DMA controller data buffers also slows down performance and increases costs for I/O processors.

DETAILED DESCRIPTION

A method and apparatus to implement bufferless direct memory access (DMA) controllers using split transactions are described. Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

FIG. 1is a block diagram of one embodiment of a computer system100to implement bufferless DMA controllers using split transactions. The system100includes a local memory110, an I/O processor120, an external bus132, a host system140, and a host memory145. Embodiments of the invention are not limited to being implemented with local and host memories, but may generally be implemented between any source and destination units accessed by an I/O processor.

The I/O processor120further includes a memory controller122, a split transaction bus124, a CPU126, a DMA controller128, and an external bus interface130. Although embodiments of the invention reference the use of DMA controllers, alternatively other disk controllers may be used. The I/O processor120provides for intelligent I/O with the help of the CPU126and memory controller122coupled to the split transaction bus124. In one embodiment, CPU126is a processor in the Pentium® family of processors including the Pentium® II processor family, Pentium® III processors, and Pentium® IV processors available from Intel Corporation of Santa Clara, Calif. Alternatively, other CPUs may be used.

The memory controller interfaces the local memory110, and that local memory110may include random access memory (RAM) such as Synchronous Dynamic RAM (SDRAM). The local memory154includes the instructions and data for execution and use by the CPU126.

The split transaction bus124is a bus that is capable of supporting explicit split transactions of both read and write commands. In one embodiment, split transaction bus124is a XSI on-chip-bus. Alternatively, other split-transaction-capable buses may be used.

Generally, split transactions split the address and data information phases of a data transfer. Splitting these phases is implemented by using an identifier, for example a Sequence ID. The address and data phases of the split transaction are coupled using the identifier. During the address phase, the requesting unit provides an identifier with command and attributes.

During the data transfer phase, the unit supplying data uses the same identifier in order to tie the commands together at each unit. During reads, the agent which claimed the read command will supply data, while during writes the agent that generated the write command provides data. Additionally, a byte count may be used, along with the identifier, to couple the address and data phases of a split transaction.

In one embodiment, the DMA controller128moves data from local memory110to host memory145, or alternatively, from host memory145to local memory110. The data transfer may take place without the use of data buffers in the DMA controller.

For example, to perform a data transfer from the host memory145to the local memory110, the CPU126first programs the DMA controller128to perform the data transfer. The DMA controller128will then generate a write command to the memory controller122. This write command includes an Identifier (ID) and, in some embodiments, a Byte Count. The DMA controller128then generates a read command to the external interface130with the same ID and Byte Count information.

The external interface130will then claim the read command and generate the read command on the external bus132. Once the external interface130receives the read data from host system140, it places the read data, with the corresponding ID and Byte Count, on the split transaction bus124. Finally, memory controller122will accept the read data because the ID and Byte Count of the read data match the ID and Byte Count of the write command the memory controller122previously received from the DMA controller128.

In another embodiment, to perform a data transfer from the local memory110to host memory145, the CPU126first programs the DMA controller128to perform the data transfer. The DMA controller128will then generate a write command to the external bus interface130. This write command includes an Identifier (ID) and, in some embodiments, a Byte Count. The DMA controller128then generates a read command to the memory controller122with the same ID and Byte Count information.

The memory controller122will then claim the read command and place the read data from local memory110, with corresponding ID and Byte Count, on to the split transaction bus124. Finally, external bus interface130accepts the read data on the split transaction bus124because the ID and Byte Count match the ID and Byte Count of the write command the external bus interface130previously received from the DMA controller128.

In another embodiment, to perform a data transfer from one local memory location110to another local memory location110, the CPU126first programs the DMA controller128to perform the data transfer. The DMA controller128will then generate a write command to the memory controller122. This write command includes an Identifier (ID) and, in some embodiments, a Byte Count. The DMA controller128then generates a read command to the memory controller122with the same ID and Byte Count information.

The memory controller122will then claim the read command and place the read data from local memory110, with corresponding ID and Byte Count, on to the split transaction bus124. Finally, the memory controller122accepts the read data on the split transaction bus124because the ID and Byte Count match the ID and Byte Count of the write command the memory controller122previously received from the DMA controller128.

In another embodiment, to perform a data transfer from one host memory location145to another host memory location145, the CPU126first programs the DMA controller128to perform the data transfer. The DMA controller128will then generate a write command to the external bus interface130. This write command includes an Identifier (ID) and, in some embodiments, a Byte Count. The DMA controller128then generates a read command to the external bus interface130with the same ID and Byte Count information.

The external interface130will then claim the read command and generate the read command on the external bus132. Once the external interface130receives the read data from host system140, it places the read data, with the corresponding ID and Byte Count, on the split transaction bus124. Finally, external bus interface130accepts the read data on the split transaction bus124because the ID and Byte Count match the ID and Byte Count of the write command the external bus interface130previously received from the DMA controller128.

FIG. 2depicts a flow diagram of one embodiment of implementing bufferless DMA controllers using split transactions. More specifically, the flow diagram depicts a data transfer from a host memory to a local memory, under one embodiment of the invention. At processing block210, the CPU programs the DMA controller to perform a data transfer. Using the split transaction functionality of the bus the DMA controller generates a write command to the memory controller with a unique ID and a Byte Count at processing block220.

At processing block230, the DMA controller generates a read command to the external interface (using the source address) with the same ID and Byte Count as the write command that was previously given to the memory controller. The external interface claims the read command at processing block240and generates the read command on the external bus at processing block250. Once the external interface receives the read data from the host system at processing block260, it places this data on the split transaction bus at processing block270. Finally, at processing block280, the memory controller accepts the read data found on the split transaction bus that matches the ID and Byte Count of the write command earlier given to it by the DMA controller.

FIG. 3depicts a flow diagram of one embodiment of implementing bufferless DMA controllers using split transactions. More specifically, the flow diagram depicts a data transfer from a local memory to a host memory, under one embodiment of the invention. At processing block310, the CPU programs the DMA controller to perform a data transfer. The DMA then generates a write command (using the destination address) to the external interface with a unique ID and Byte Count at processing block320.

The DMA controller generates a read command (using the source address) to the memory controller with the same ID and Byte Count found in the write command at processing block330. At processing block340, the memory controller claims the read command, and, at processing block350, returns the read data onto the split transaction bus. At processing block360, the external interface accepts the read data found on the split transaction bus that matches the ID and Byte Count of the write command it accepted previously.

FIG. 4depicts a flow diagram of one embodiment of implementing bufferless DMA controllers using split transactions. More specifically, the flow diagram depicts a data transfer from one location in local memory to another location in local memory, under one embodiment of the invention. At processing block410, the CPU programs the DMA controller to perform a data transfer. Using the split transaction functionality of the bus, the DMA controller generates a write command to the memory controller with a unique ID and a Byte Count at processing block420.

The DMA controller then generates a read command to the memory controller with the same ID and Byte Count found in the write command at processing block430. At processing block440, the memory controller claims the read command, and, at processing block450, returns the read data onto the split transaction bus. At processing block460, the memory controller accepts the read data found on the split transaction bus that matches the ID and Byte Count of the write command it accepted previously.

FIG. 5depicts a flow diagram of one embodiment of implementing bufferless DMA controllers using split transactions. More specifically, the flow diagram depicts a data transfer from one location in host memory to another location in host memory, under one embodiment of the invention. At processing block510, the CPU programs the DMA controller to perform a data transfer. Using the split transaction functionality of the bus, the DMA controller generates a write command to the external interface with a unique ID and a Byte Count at processing block520.

At processing block530, the DMA controller generates a read command to the external interface with the same ID and Byte Count as the write command that was previously given to the external interface. The external interface claims the read command at processing block540and generates the read command on the external bus at processing block550. Once the external interface receives the read data from the host system at processing block560, it places this data on the split transaction bus at processing block570. Finally, at processing block580, the external interface accepts the read data found on the split transaction bus that matches the ID and Byte Count of the write command earlier given to it by the DMA controller.

AlthoughFIGS. 2 through 5present implementing bufferless DMA controllers using split transactions in the context of data transfers between and within host and local memories, other embodiments may be implemented, such as transferring data between a peripheral and the host memory. Generally the apparatus and methods presented can be implemented between any source and destination units between which an I/O processor transfers data.

Embodiments of the invention use split transaction functionality provided by split-transaction-capable buses to implement DMA controllers without data buffers. Removing data buffers from the DMA controller may result in increased performance and lower costs, as data is moved directly from one memory to the other memory, instead of being intermediately stored in the DMA data buffer.