SEMICONDUCTOR DEVICE WITH POWER SUPPLY DISTRIBUTION NETWORKS ON FRONTSIDE AND BACKSIDE OF A CIRCUIT

One or more systems, devices, and/or methods of use provided herein relate to a semiconductor device with separate power supplies for front side and backside stacked power distribution. A semiconductor device can include one or more circuits, a first power supply, a second power supply, and a third power supply. The first power supply can be disposed on a first side of the one or more circuits. The second power supply can be disposed on the first side of the one or more circuits. Further, the third power supply can be disposed on a second side of the one or more circuits. Additionally, the first side of the one or more circuits can be opposite to the second side of the one or more circuits.

BACKGROUND

One or more embodiments described herein relate generally to optimizing semiconductor devices with respect to the various connected components. Embodiments relate to connecting power supplies to both the frontside and backside of a circuit, and more specifically, to systems and methods to facilitate semiconductor devices having voltage domains on both sides of the circuit without voltage supply blockage.

SUMMARY

The following presents a summary to provide a basic understanding of one or more embodiments described herein. This summary is not intended to identify key or critical elements or delineate any scope of the particular embodiments or any scope of the claims. The sole purpose of the summary is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, devices, and/or methods, that facilitate semiconductor devices with power supply distribution networks on frontside and backside of a circuit without voltage supply layout blockage are described.

According to an embodiment, a semiconductor device can comprise one or more circuits, and a first power supply disposed on a first side of the one or more circuits. The semiconductor device can include a second power supply that can be disposed on the first side of the one or more circuits. The semiconductor device can include a third power supply that can be disposed on a second side of the circuit. Additionally, the first side of the circuit can be opposite to the second side of the circuit. The one or more circuits can receive power from the first power supply, the second power supply, and the third power supply within the same circuit row.

According to another embodiment, a semiconductor device can comprise one or more circuits coupled to a frontside power distribution network and a backside power distribution network. The semiconductor device can include one or more connecting vias that can be disposed between the frontside power distribution network and the backside power distribution network that can couple the frontside power distribution network with the backside power distribution network. Additionally, the backside power distribution network can include a first power supply, a second power supply, and a first portion of a third power supply. The frontside power distribution network can include a second portion of the third power supply coupled to the first portion of the third power supply by at least one of the one or more connecting vias. Further, the one or more circuits can receive power from the first power supply, the second power supply, and the third power supply within the same circuit row.

According to yet another embodiment, a semiconductor device can comprise one or more circuits coupled to a frontside power distribution network and a backside power distribution network. The semiconductor device can also include one or more connecting vias that can be disposed between the frontside power distribution network and the backside power distribution network that can couple the frontside power distribution network with the backside power distribution network. The backside power distribution network can include a first power supply, a second power supply having a first portion and a second portion. The frontside power distribution network can include a third power supply. The first portion of the second power supply can be coupled to the one or more circuits. Further, the second portion of the first power supply can provide power to the third power supply on the frontside power distribution network. The one or more circuits can receive power from the first power supply, the second power supply, and the third power supply within the same circuit row.

DETAILED DESCRIPTION

Discussion is provided herein relative to configuration, including fabrication, of an electronic structure that can comprise and/or be comprised by a controller, payload and/or other chip-based structure. In one or more embodiments, the electronic structure can be configured for use in a quantum system. However, as there are many uses for devices comprising silicon chips, the discussion herein need not apply solely to quantum computer electronics, but can also apply to many other control, radio, radar, cryogenic and/or signal-based applications, among others. Description and discussion herein is therefore not limited to use in a quantum computing system.

In some cases, it can be desirable to optimize conductive lines and/or vias of a semiconductor to cause optimal performance of coupled devices (e.g., inverters, transistors, etc.). One or more various devices and/or circuits can be coupled to the semiconductor device, and the one or more various devices and/or circuits can utilize different connection configurations with the conductive lines and/or vias to perform optimally (e.g., at various voltages). Further, it can be desirable to supply power to the various devices and/or circuits from a frontside of the semiconductor device (e.g., a frontside power distribution network). With embodiments, the frontside of the semiconductor device can provide power for memory control logic disposed on a top of the semiconductor device.

It can also be desirable to supply power to the various devices and/or circuits from a backside of the semiconductor device (e.g., a backside power distribution network). Supplying power to the one or more various devices and/or circuits from both a frontside and a backside of the semiconductor device can improve the efficiency of components distributed on and/or coupled to the semiconductor device. For example, and without limitation, such efficient structure can facilitate additional area for signal wiring to be disposed on the front side of the semiconductor device due to the multiple voltage domains provided across the same circuit row. The backside of the semiconductor device can be responsible for providing core voltages to the components connected with the semiconductor device. In embodiments, components connected with the semiconductor device can access a variety of voltage sources within the same circuit row.

Additionally, the resulting profile of the backside power distribution can be a repeatable pattern of ground sources and voltage sources. Such a repeating profile on the backside of the non-limiting semiconductor device can facilitate a more efficiently distributed power distribution network (e.g., and in some cases additional space for signal wiring to be disposed). The non-limiting semiconductor device can support a common set of standard circuit cells (e.g., one or more various circuit configurations for operating I/O devices, IP cores, logic cores, IP Blocks, IP Cells, and/or other IP and/or I/O circuitry). Further, the standard cells can be used for both frontside power distribution and backside power distribution; and can be coupled to the semiconductor device with one or more of a plurality of voltage sources and ground sources.

Additional description of functionalities will be further described below with reference to the example embodiments ofFIG.1, where repetitive description of like elements and/or processes employed in respective embodiments is omitted for sake of brevity. The non-limiting semiconductor device can comprise one or more circuits, a first power supply, a second power supply, and a third power supply. The first power supply can be disposed on a first side of the one or more circuits (e.g., the frontside). Additionally, the second power supply can be disposed on the first side of the one or more circuits. The third power supply can be disposed on a second side of the one or more circuits. Further, the first side of the one or more circuits can be opposite to the second side of the one or more circuits (e.g., in the Z-direction). With examples, the first power supply can be a ground source. The second power supply and the third power supply can supply power from the backside of the one or more circuits, and the third power supply can supply power from the frontside of the one or more circuits. The second power supply and the third power supply can include one or more of a variety of voltage ranges. For example, and without limitation, voltages of each of the second power supply and the third power supply can range from about 1.2V to about 3.3V.

In embodiments,FIG.1illustrates a cross-sectional view of an example, non-limiting semiconductor device100that can address the challenges of power optimization for circuits and devices coupled to both frontside and backside voltages. The cross-sectional view ofFIG.1can be seen as taken along the Y plane ofFIG.2. Turning back toFIG.1, the semiconductor device100can include a first side102and a second side104. The first side102can be a backside of the semiconductor device100, and the second side104can be a frontside of the semiconductor device100. Further, as seen inFIG.1, the first side102can be disposed opposite the second side104(e.g., vertically, in the Z-direction).

With embodiments, the non-limiting semiconductor device100can include one or more circuits110, a first power supply112, a second power supply114, and a third power supply116. The first power supply112can be disposed on the first side102of the one or more circuits110, and, additionally, the second power supply114can be disposed on the first side102of the one or more circuits110. The third power supply116can be disposed on the second side104of the one or more circuits110. Further, the third power supply116can be disposed opposite the first power supply112and the second power supply114(e.g., in the Z-direction).

In embodiments, the one or more circuits110can be coupled with the first power supply112and the second power supply114with one or more of a variety of via connection formations. For example, and without limitation, the semiconductor device100can include a first via connection formation120and a second via connection formation122. The first via connection formation120can be disposed vertically between (e.g., in the Z-direction) the first power supply112and the circuit110. The second via connection formation122can be disposed vertically between (e.g., in the Z-direction) the second power supply114and the one or more circuits110.

With embodiments, the one or more circuits110can include a plurality of circuits (e.g., a plurality of standard circuit cells as referenced above) including a first circuit130and a second circuit132. The first circuit130can be electrically coupled to the first power supply112by the first via connection formation120. Similarly, the second circuit132can be electrically coupled to the second power supply114by the second via connection formation122. The third power supply116can be generated by the first circuit130and the second circuit132(e.g., indirectly coupled with the first power supply112and the second power supply114). Further, the second power supply114and the third power supply116can utilize the first power supply112as a grounding source for the first circuit130and the second circuit132.

In embodiments, such as generally illustrated inFIG.2(e.g., a top-down view from the backside of the one or more circuits110), the third power supply116can be the voltage domain available to the one or more circuits110on the frontside, and the second power supply114can be the voltage domain available to the one or more circuits110on the backside. The second power supply114and the third power supply116can be coupled with the first power supply112(e.g., a ground source/connection).

With examples, the non-limiting semiconductor device100can include a third circuit134and a fourth circuit136. The third circuit134and the fourth circuit136can be coupled to the first power supply112and the second power supply114. The third circuit134and the fourth circuit136can be disposed adjacent to the first circuit130and the second circuit132, respectively (e.g., in the X-direction). For example, and without limitation, the third circuit134and the fourth circuit136can be offset/misaligned (e.g., in the X-direction) such as to not contact the third power supply116. The first circuit130, the second circuit132, the third circuit134, and the fourth circuit136can access a variety of voltages from coupled sources to the semiconductor device100on the frontside and the backside (e.g., to be supplied to components coupled with the semiconductor device100).

In embodiments, such as generally shown inFIG.3, the first power supply312, the second power supply314, and the third power supply316can be substantially parallel rails (e.g., continuous rails in the X-direction). The third power supply316can comprise two parallel rails (a first rail316A, and a second rail316B) with the first power supply312disposed between (e.g., in the Y-direction) which can be single rail. The second power supply314can comprise two parallel rails (a first rail314A, and a second rail314B). The first circuit330and the third circuit334of the semiconductor device100can be coupled to the first power supply312, the first rail314A of the second power supply314, and the first rail316A of the third power supply316. Additionally, the second circuit332and the fourth circuit336can be coupled to the first power supply312, the second rail314B of the second power supply314, and the second rail316B of the third power supply316.

With embodiments, such as generally shown inFIG.4, the non-limiting semiconductor device100can include the third power supply416formed as one or more of a variety of rail segments (e.g., staples, portions, etc.). The third power supply416can be formed as a first segment416A, a second segment416B, a third segment416C, a fourth segment416D, a fifth segment416E, and a sixth segment416F. The first segment416A, the second segment416B, and the third segment416C can be coupled to the first rail414A of the second power supply414. The fourth segment416D, the fifth segment416E, and the sixth segment416F can be coupled to the second rail414B of the second power supply414. Further, the first power supply412can be coupled to the first circuit430, the second circuit432, the third circuit434, and the fourth circuit436. The first circuit430can be coupled to the first rail414A of the second power supply414, the first segment416A and the second segment416B of the third power supply, and the first power supply412. Additionally, the second circuit432can be coupled to the first power supply412, the second rail414B of the second power supply, the fourth segment416D and the fifth segment416E of the third power supply416.

For example, and without limitation, in additional embodiments, the third circuit434can be coupled with the first power supply412, the first rail414A of the second power supply414, and the second segment416B and the third segment416C of the third power supply416. The fourth circuit436can be coupled to the first power supply412, the second rail414B of the second power supply414, and the fifth segment416E and the sixth segment416F of the third power supply416.

In embodiments, such as generally shown inFIG.5, the non-limiting semiconductor device100can include the second power supply514and the third power supply516formed as one or more of a variety of rail segments (e.g., staples, portions, etc.). The second power supply514can be formed as a first segment514A, a second segment514B, a third segment514C, and a fourth segment514D. The first segment514A and the second segment514B can be aligned substantially parallel in the X-direction. Additionally, the third segment514C and the fourth segment514D can be aligned substantially parallel in the X-direction. The third power supply516can be formed as a first segment516A, a second segment516B, a third segment516C, a fourth segment516D, a fifth segment516E, and a sixth segment516F. The first segment516A, the second segment516B, and the third segment516C can be aligned substantially parallel in the X-direction. The fourth segment516D, the fifth segment516E, and the sixth segment516F can be aligned substantially parallel in the X-direction. The first segment514A of the second power supply514can be coupled to the first segment516A of the third power supply516. Additionally, the third segment516C of the third power supply516can be coupled to the second segment514B of the second power supply514. The third segment514C of the second power supply514can be coupled to the fourth segment516D of the third power supply516. Similarly, the fourth segment514D of the second power supply514can be coupled to the sixth segment516F of the third power supply516.

With embodiments, the second segment516B of the third power supply516can be coupled to the first circuit530and the third circuit534. The fifth segment516E of the third power supply516can be coupled to the second circuit532and the fourth circuit536. Further, the power supply512can be coupled to the first circuit530, the second circuit532, the third circuit534, and the fourth circuit536.

In embodiments, such as generally illustrated inFIG.6, the non-limiting semiconductor device100can include the third power supply616disposed substantially perpendicular to (e.g., in the X-Y plane) the first power supply612and the second power supply614. The second power supply614can be formed as a plurality of rails. The plurality of rails can include a first rail614A and a second rail614B. Additionally, the third power supply616can include a plurality of rails, which can include a first rail616A, a second rail616B, and a third rail616C. The plurality of rails that comprise the second power supply614can be disposed in a substantially parallel manner with respect to each other. Similarly, the plurality of rails that comprise the third power supply616can be disposed in a substantially parallel manner with respect to each other. The first power supply612can be disposed between (e.g., in the Y-direction) between the first rail614A and the second rail614B.

With embodiments, the first circuit630can be in contact with the first power supply612, the first rail614A of the second power supply614, and the first rail616A and the second rail616B of the third power supply616. The second circuit632can be in contact with the first power supply612, the first rail614A of the second power supply614, and the first rail616A and the second rail616B of the third power supply616. The third circuit634can be in contact with the first power supply612, the first rail614A of the second power supply, and the second rail616B and the third rail616C of the third power supply616. The fourth circuit636can be in contact with the first power supply612, the second rail614B of the second power supply614, and the second rail616B and the third rail616C of the third power supply616.

In embodiments, such as generally illustrated inFIG.7, the non-limiting semiconductor device100can include drawing power from the backside702of the circuit710from the third power supply716with a third via connection formation724to connect the third power supply716to the frontside704of the circuit710(e.g., such that the third power supply716can be accessed from the backside702and the frontside704). The second power supply714can include a first portion714A and a second portion714B (e.g., disposed on the backside702). The third power supply716can include a first portion716A disposed on the backside702and a second portion716B disposed on the frontside704. The first portion716A can be coupled to the second portion716B with the via connection formation724that can extend vertically (e.g., in the Z-direction) between the first portion716A and the second portion716B.

With embodiments, such as generally illustrated inFIG.8, the non-limiting semiconductor device100can include a voltage regulation circuit840to manage the voltage of the third power supply816(e.g., to change the voltage to a user desired level within a range generally of about 1.2V to about 3.3V). The second power supply814can include a first portion814A, a second portion814B, and a third portion814C. The third portion814C can be coupled with the voltage regulation circuit840to generate a greater or lesser voltage than the second power supply814as the voltage of the third power supply816. Further, the voltage regulation circuit840can be coupled vertically (e.g., in the Z-direction) between the third portion814C of the second power supply814and the third power supply816.

In further embodiments, such as generally illustrated inFIG.9, the non-limiting semiconductor device100can include a power gating circuit942to turn on and turn off the voltage generated within the semiconductor device100from contacting the third power supply916. Such voltage control facilitated by the power gating circuit942can be utilized in power mitigation schemes for various circuits and semiconductor devices. The second power supply914can include a first portion914A, a second portion914B, and a third portion914C that can be disposed substantially parallel to each other. The power gating circuit942can be coupled vertically (e.g., in the Z-direction) between the third portion914C of the second power supply914and the third power supply916.

With embodiments, such as illustrated inFIG.10, the non-limiting semiconductor device100can include a power gating circuit1042to mitigate voltages from the second power supply1014, and, additionally, a third via connection formation1024can connect the third power supply1016to the backside1002and the frontside1004of the one or more circuits1010. The second power supply1014can include a first portion1014A, a second portion1014B, and a third portion1014C that can be disposed on the backside1002of the one or more circuits1010. The third power supply1016can include a first portion1016A disposed on the backside1002of the one or more circuits110, and a second portion1016B disposed on the frontside1004of the one or more circuits110. Such as can be seen fromFIG.10, the power gating circuit1042can be disposed horizontally adjacent to the third via connection formation1024(e.g., in the Y-direction). Due to power consumption considerations, the non-limiting semiconductor device100can utilize the above connection structure to selectively shut down and power various IP cores of the one or more circuits1010.

In embodiments, such as generally illustrated byFIG.11, a method1100of fabricating the non-limiting semiconductor device100, by a fabrication system can include providing one or more circuits110, a first power supply112, a second power supply114, and a third power supply116(step1102). The method1100of fabricating the non-limiting semiconductor device100can comprise disposing, by the fabrication system, the first power supply112on a first side102(e.g., the backside) of the one or more circuits110, and disposing, by the fabrication system, a second power supply114on the first side102of the one or more circuits110(step1104).

With embodiments, the method1100can further comprise disposing, by the fabrication system, the third power supply116on the second side104of the one or more circuits110, where the first side102can be opposite the second side (step1106). Additionally, the method1100can further include providing power, by the fabrication system, to the one or more circuits from the first power supply, the second power supply, and the third power supply within the same circuit row (step1108). Further, the one or more circuits110can include a first circuit130and a second circuit132.

The method1100can further comprise providing, by the fabrication system, the first circuit130with a first voltage, and providing, by the fabrication system, the second circuit132with a second voltage, where the first voltage is different than the second voltage (step1110).

For example, one or more embodiments described herein of the non-limiting semiconductor device100and/or one or more components thereof can employ one or more computing resources of the computing environment1200described below with reference to the illustration ofFIG.12. For instance, the system and/or components thereof can employ one or more classical and/or quantum computing resources to execute one or more classical and/or quantum: mathematical functions, calculations and/or equations; computing and/or processing scripts; algorithms; models (e.g., artificial intelligence (AI) models, machine learning (ML) models and/or like model); and/or another operation in accordance with one or more embodiments described herein.

It is to be understood that although one or more embodiments described herein include a detailed description on cloud computing, implementation of the teachings recited herein are not limited to a cloud computing environment. Rather, one or more embodiments described herein are capable of being implemented in conjunction with any other type of computing environment now known or later developed.

Characteristics are as follows:

Service Models are as follows:

A cloud computing environment is service oriented with a focus on statelessness, low coupling, modularity and/or semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

Computing environment1200contains an example of an environment for the execution of at least some of the computer code involved in performing the inventive methods, such as translation of an original source code based on a configuration of a target system by the power distribution circuit execution code block1300. In addition to block1300, computing environment1200includes, for example, computer1201, wide area network (WAN)1202, end user device (EUD)1203, remote server1204, public cloud1205, and private cloud1206. In this embodiment, computer1201includes processor set1210(including processing circuitry1220and cache1221), communication fabric1211, volatile memory1212, persistent storage1213(including operating system1222and block1300, as identified above), peripheral device set1214(including user interface (UI), device set1223, storage1224, and Internet of Things (IoT) sensor set1225), and network module1215. Remote server1204includes remote database1230. Public cloud1205includes gateway1240, cloud orchestration module1241, host physical machine set1242, virtual machine set1243, and container set1244.

COMPUTER1201can take the form of a desktop computer, laptop computer, tablet computer, smart phone, smart watch or other wearable computer, mainframe computer, quantum computer or any other form of computer or mobile device now known or to be developed in the future that is capable of running a program, accessing a network or querying a database, such as remote database1230. As is well understood in the art of computer technology, and depending upon the technology, performance of a computer-implemented method can be distributed among multiple computers and/or between multiple locations. On the other hand, in this presentation of computing environment1200, detailed discussion is focused on a single computer, specifically computer1201, to keep the presentation as simple as possible. Computer1201can be located in a cloud, even though it is not shown in a cloud inFIG.12. On the other hand, computer1201is not required to be in a cloud except to any extent as can be affirmatively indicated.

PROCESSOR SET1210includes one, or more, computer processors of any type now known or to be developed in the future. Processing circuitry1220can be distributed over multiple packages, for example, multiple, coordinated integrated circuit chips. Processing circuitry1220can implement multiple processor threads and/or multiple processor cores. Cache1221is memory that is located in the processor chip package(s) and is typically used for data or code that should be available for rapid access by the threads or cores running on processor set1210. Cache memories are typically organized into multiple levels depending upon relative proximity to the processing circuitry. Alternatively, some, or all, of the cache for the processor set can be located “off chip.” In some computing environments, processor set1210can be designed for working with qubits and performing quantum computing.

VOLATILE MEMORY1212is any type of volatile memory now known or to be developed in the future. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, the volatile memory is characterized by random access, but this is not required unless affirmatively indicated. In computer1201, the volatile memory1212is located in a single package and is internal to computer1201, but, alternatively or additionally, the volatile memory can be distributed over multiple packages and/or located externally with respect to computer1201.

PERIPHERAL DEVICE SET1214includes the set of peripheral devices of computer1201. Data communication connections between the peripheral devices and the other components of computer1201can be implemented in various ways, such as Bluetooth connections, Near-Field Communication (NFC) connections, connections made by cables (such as universal serial bus (USB) type cables), insertion type connections (for example, secure digital (SD) card), connections made though local area communication networks and even connections made through wide area networks such as the internet. In various embodiments, UI device set1223can include components such as a display screen, speaker, microphone, wearable devices (such as goggles and smart watches), keyboard, mouse, printer, touchpad, game controllers, and haptic devices. Storage1224is external storage, such as an external hard drive, or insertable storage, such as an SD card. Storage1224can be persistent and/or volatile. In some embodiments, storage1224can take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer1201is required to have a large amount of storage (for example, where computer1201locally stores and manages a large database) then this storage can be provided by peripheral storage devices designed for storing large amounts of data, such as a storage area network (SAN) that is shared by multiple, geographically distributed computers. IoT sensor set1225is made up of sensors that can be used in Internet of Things applications. For example, one sensor can be a thermometer and another sensor can be a motion detector.

END USER DEVICE (EUD)1203is any computer system that is used and controlled by an end user (for example, a customer of an enterprise that operates computer1201) and can take any of the forms discussed above in connection with computer1201. EUD1203typically receives helpful and useful data from the operations of computer1201. For example, in a hypothetical case where computer1201is designed to provide a recommendation to an end user, this recommendation would typically be communicated from network module1215of computer1201through WAN1202to EUD1203. In this way, EUD1203can display, or otherwise present, the recommendation to an end user. In some embodiments, EUD1203can be a client device, such as thin client, heavy client, mainframe computer and/or desktop computer.

REMOTE SERVER1204is any computer system that serves at least some data and/or functionality to computer1201. Remote server1204can be controlled and used by the same entity that operates computer1201. Remote server1204represents the machine(s) that collect and store helpful and useful data for use by other computers, such as computer1201. For example, in a hypothetical case where computer1201is designed and programmed to provide a recommendation based on historical data, then this historical data can be provided to computer1201from remote database1230of remote server1204.

PUBLIC CLOUD1205is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and/or other computer capabilities, especially data storage (cloud storage) and computing power, without direct active management by the scale. The direct and active management of the computing resources of public cloud1205is performed by the computer hardware and/or software of cloud orchestration module1241. The computing resources provided by public cloud1205are typically implemented by virtual computing environments that run on various computers making up the computers of host physical machine set1242, which is the universe of physical computers in and/or available to public cloud1205. The virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set1243and/or containers from container set1244. It is understood that these VCEs can be stored as images and can be transferred among and between the various physical machine hosts, either as images or after instantiation of the VCE. Cloud orchestration module1241manages the transfer and storage of images, deploys new instantiations of VCEs and manages active instantiations of VCE deployments. Gateway1240is the collection of computer software, hardware and firmware allowing public cloud1205to communicate through WAN1202.

PRIVATE CLOUD1206is similar to public cloud1205, except that the computing resources are only available for use by a single enterprise. While private cloud1206is depicted as being in communication with WAN1202, in other embodiments a private cloud can be disconnected from the internet entirely and only accessible through a local/private network. A hybrid cloud is a composition of multiple clouds of different types (for example, private, community or public cloud types), often respectively implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technology that enables orchestration, management, and/or data/application portability between the multiple constituent clouds. In this embodiment, public cloud1205and private cloud1206are both part of a larger hybrid cloud.

Aspects of the one or more embodiments described herein are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to one or more embodiments described herein. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions. These computer readable program instructions can be provided to a processor of a general-purpose computer, special purpose computer and/or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, can create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein can comprise an article of manufacture including instructions which can implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks. The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus and/or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus and/or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus and/or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality and/or operation of possible implementations of systems, computer-implementable methods and/or computer program products according to one or more embodiments described herein. In this regard, each block in the flowchart or block diagrams can represent a module, segment and/or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function. In one or more alternative implementations, the functions noted in the blocks can occur out of the order noted in the Figures. For example, two blocks shown in succession can be executed substantially concurrently, and/or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and/or combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that can perform the specified functions and/or acts and/or carry out one or more combinations of special purpose hardware and/or computer instructions.

While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and/or computers, those skilled in the art will recognize that the one or more embodiments herein also can be implemented at least partially in parallel with one or more other program modules. Generally, program modules include routines, programs, components and/or data structures that perform particular tasks and/or implement particular abstract data types. Moreover, the aforedescribed computer-implemented methods can be practiced with other computer system configurations, including single-processor and/or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), and/or microprocessor-based or programmable consumer and/or industrial electronics. The illustrated aspects can also be practiced in distributed computing environments in which tasks are performed by remote processing devices that are linked through a communications network. However, one or more, if not all aspects of the one or more embodiments described herein can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.