Ruthenium-based liner for a copper interconnect

In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

BACKGROUND

A semiconductor device, such as an integrated circuit, may include interconnects made of copper to reduce propagation delays and power consumption, when compared with other metal interconnects, when the semiconductor device is in operation. Additionally, a semiconductor device that uses copper interconnects may have interconnects with narrower dimensions than a semiconductor device that uses another metal (e.g., aluminum) for interconnects.

DETAILED DESCRIPTION

A semiconductor device with copper interconnects may have improved performance when compared with a semiconductor device that includes interconnects made from other metals, such as aluminum. For example, a semiconductor device with copper interconnects may have reduced power consumption and/or reduced propagation delay, during operation, based on characteristics of the copper material. Additionally, because of the characteristics of the copper material, the copper interconnects may be narrower than interconnects made from other metals. However, during manufacturing processes, filling a via with the copper material may be challenging.

In some manufacturing processes, when attempting to fill a via having narrow dimensions (e.g., less than about 12 nanometers), the copper material may not penetrate into the via and may leave other materials (e.g., a gas) within a volume of the via. For example, some manufacturing processes may include depositing a cobalt liner within the via before attempting to fill the via with the copper material. The cobalt liner may result in a cobalt protrusion and a copper protrusion from a top portion of the via toward a center of the via, resulting in a pinch point at the top portion of the via. When attempting to fill the via with the copper material, the pinch point may inhibit flow of copper material into the via during a copper reflow process and/or may prevent the copper from fully filling a lower portion of the via. This may result in air voids within the via (e.g., portions without copper), which may reduce performance of the copper interconnect within the semiconductor device.

Some implementations described herein provide techniques and apparatuses for forming a semiconductor device with a ruthenium-based liner for a copper interconnect. In some implementations, the semiconductor device may include a barrier layer, such as a tantalum nitride-based barrier, deposited within a via. The semiconductor device may include a ruthenium-based liner on the barrier layer and, optionally, a cobalt liner deposited on the ruthenium-based liner. If using the optional cobalt liner in addition to the ruthenium-based liner, material of the cobalt liner and material of the ruthenium-based liner may mix to form a ruthenium-based liner that includes ruthenium material and cobalt material. The semiconductor device may include a copper plug disposed within the via on the ruthenium-based liner (e.g., a ruthenium-based liner that does not include cobalt material or a ruthenium-based liner that includes cobalt material). The semiconductor device may include one or more caps on the copper plug. For example, the one or more caps may include a ruthenium cap (e.g., if a cobalt liner is not included in the via) and/or a cobalt cap.

Based on using a ruthenium-based liner within the via, copper material may fill (e.g., completely fill or generally fill) the via, even when the via is narrow (e.g., less than about 12 nanometers). In some implementations, the ruthenium-based liner may reduce a protrusion into a top portion of the via and/or may reduce a pinch point at the top portion of the via. This may facilitate deposition of the copper plug within the via, which may improve uniformity of copper material within the via, reduce voids within the via, and improve performance of the copper plug as a copper interconnect within the semiconductor device.

FIG.1is a diagram of an example environment100in which systems and/or methods described herein may be implemented. As shown inFIG.1, environment100may include a plurality of semiconductor processing tools102-108and a wafer/die transport device110. The plurality of semiconductor processing tools102-108may include a deposition tool102, an etching tool104, a chemical-mechanical polishing (CMP) tool106, and/or a pre-cleaning tool108, among other examples. The semiconductor processing tools included in example environment100may be included in a semiconductor clean room, a semiconductor foundry, and/or a semiconductor processing and/or manufacturing facility, among other examples.

Deposition tool102is a semiconductor processing tool that is capable of depositing various types of materials onto a substrate. In some implementations, deposition tool102includes a spin coating tool that is capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, deposition tool102includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some implementations, deposition tool102includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the example environment100includes a plurality of types of deposition tools102.

Etching tool104is a semiconductor processing tool that is capable of etching (e.g., removing) various types of materials of a substrate, wafer, or semiconductor device. For example, etching tool104may include a wet etching tool, a dry etching tool, a laser etching tool, a chemical etching tool, a plasma etching tool, a reactive ion etching tool, a sputter etching tool, and/or a vapor phase etching tool, among other examples. A wet etching tool may include a chamber that is filled with an etchant, and the substrate may be placed in the chamber for a particular time period to remove particular amounts of one or more portions of the substrate. A dry etching tool may remove one or more portions of the substrate using a plasma etch technique (e.g., a plasma sputtering technique) and/or a plasma-assisted etch, which may involve using an ionized gas to isotopically or directionally etch the one or more portions. In some implementations, etching tool104may remove a layer from a semiconductor device as described herein.

CMP tool106is a semiconductor processing tool that includes one or more devices capable of polishing or planarizing various layers of a wafer or semiconductor device. In some implementations, CMP tool106may polish or planarize a layer of deposited or plated material. The CMP tool106may polish or planarize a surface of a semiconductor device with a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The CMP tool may utilize an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring (e.g., typically of a greater diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head may rotate with different axes of rotation to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planar.

Pre-clean tool108is a semiconductor processing tool that includes a pre-cleaning chamber and/or one or more devices capable of performing a pre-cleaning process on a semiconductor device to remove material (e.g., residue from a CMP operation and/or an oxide layer, among other examples) from the semiconductor device. The one or more devices may include a gas source, a plasma source, a heat source, and/or the like. The gas source may supply various gasses to pre-clean chamber, such as a hydrogen gas and/or ammonia plasma, among other examples. The plasma source may generate a plasma that causes a reaction between gasses supplied to the pre-clean chamber. For example, the plasma source may include an inductively coupled plasma source, a transformer coupled plasma source, or another type of plasma source capable of causing a reaction between an ammonia gas and a nitrogen trifluoride gas to cause the formation of an ammonium fluoride gas. The heat source may be capable of heating a semiconductor device in the pre-clean chamber to cause one or more layers on the semiconductor device to decompose, as described herein. For example, the heat source may include a heat lamp, a heating coil, or another type of heating device that heats the semiconductor device to cause a protection layer on the semiconductor device to decompose into an ammonia gas and a hydrogen fluoride gas. Pre-clean tool108may be integrated with Deposition tool102to prevent, or reduce a likelihood of, a vacuum break.

Wafer/die transport device110includes a mobile robot, a robot arm, a tram or rail car, and/or another type of device that is used to transport wafers and/or dies between semiconductor processing tools102-108and/or to and from other locations such as a wafer rack, or a storage room, among other examples. In some implementations, wafer/die transport device110may be a programmed device to travel a particular path and/or may operate semi-autonomously or autonomously.

The number and arrangement of devices shown inFIG.1are provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or differently arranged devices than those shown inFIG.1. Furthermore, two or more devices shown inFIG.1may be implemented within a single device, or a single device shown inFIG.1may be implemented as multiple, distributed devices. Additionally, or alternatively, a set of devices (e.g., one or more devices) of environment100may perform one or more functions described as being performed by another set of devices of environment100.

FIGS.2A-2Hare diagrams of one or more example implementations described herein. Example implementation(s) may include one or more example implementations of a process for manufacturing a semiconductor device200, as described herein. As described below, example implementation(s) may include a process of manufacturing the semiconductor device200with a ruthenium-based liner and a copper plug within a via of the device200.

As shown inFIG.2A, the semiconductor device200may include a substrate202and a via204. In some implementations, the substrate may include a silicon-based material. In some implementations, one or more semiconductor processing tools may form the via204within the substrate202. For example, an etching tool (e.g., etching tool104) may etch a portion of the substrate202to form the via204(e.g., a recessed portion of the substrate202).

As shown byFIG.2B, one or more semiconductor processing tools may deposit a tantalum nitride-based liner206(e.g., a barrier layer) on the substrate202within the via204and/or outside of the via204of the semiconductor device200(e.g., on an upper surface of the semiconductor device200). In some implementations, a deposition tool (e.g., deposition tool102) may deposit the tantalum nitride-based liner206onto the substrate202of the semiconductor device200. In some implementations, the deposition tool may use high density plasma deposition, plasma-enhanced chemical vapor deposition, chemical vapor deposition, or physical vapor deposition, among other examples, to deposit the tantalum nitride-based liner206onto the substrate202of the semiconductor device200. In some aspects, the tantalum nitride-based liner206may form a barrier between the substrate202and the via204. The tantalum nitride-based liner206may prevent and/or reduce diffusion of materials from within the via (e.g., copper material) into the substrate202, which may damage the semiconductor device200.

As shown byFIG.2C, one or more semiconductor processing tools may deposit a ruthenium-based liner208(e.g., a barrier layer) within the via204and/or outside of the via204of the semiconductor device200(e.g., on the upper surface of the semiconductor device200). In some implementations, the ruthenium-based liner208may be disposed on the tantalum nitride-based liner206. In some implementations, a deposition tool (e.g., deposition tool102) may deposit the ruthenium-based liner208within the via204(e.g., on the tantalum nitride-based liner206) of the semiconductor device200. In some implementations, the deposition tool may use high density plasma deposition, plasma-enhanced chemical vapor deposition, chemical vapor deposition, or physical vapor deposition, among other examples, to deposit the ruthenium-based liner208within the via204(e.g., on the tantalum nitride-based liner206). In some implementations, the ruthenium-based liner208may have a thickness in a range from approximately 0.5 to 3 nanometers (e.g., 0.5 to 2 nanometers).

As shown byFIG.2D, one or more semiconductor processing tools may deposit a cobalt-based liner210(e.g., a barrier layer) within the via204and/or outside of the via204of the semiconductor device200(e.g., on the upper surface of the semiconductor device200). In some implementations, the cobalt-based liner210may be disposed on the ruthenium-based liner208or on another barrier layer of the semiconductor device200. In some implementations, a deposition tool (e.g., deposition tool102) may deposit the cobalt-based liner210within the via204(e.g., on the ruthenium-based liner208) of the semiconductor device200. In some implementations, the deposition tool may use high density plasma deposition, plasma-enhanced chemical vapor deposition, chemical vapor deposition, or physical vapor deposition, among other examples, to deposit the cobalt-based liner210within the via204(e.g., on the ruthenium-based liner208).

In some implementations, the ruthenium-based liner208and the cobalt-based liner210may intermix to form a combined ruthenium-based liner that includes ruthenium material and cobalt material. For example, ruthenium material of the ruthenium-based liner208may diffuse into the cobalt-based liner210to form a partially mixed or fully mixed ruthenium-cobalt-based liner (e.g., shown inFIGS.3E and3F). The ruthenium material may diffuse into the cobalt-based liner based on a reaction (e.g., a chemical reaction) between the ruthenium material and cobalt material that is triggered upon deposition of the cobalt-based liner210on the ruthenium-based liner208. In some implementations, the cobalt-based liner210may be ruthenium-doped based on diffusion of the ruthenium material into the cobalt-based liner210. The combined ruthenium-based liner may include some ruthenium material on an inner surface of the cobalt-based liner210(e.g., a surface exposed in the via204that will contact a copper plug214shown inFIG.2F) and/or some cobalt material on the inner surface of the ruthenium-based liner208(e.g., a surface opposite the tantalum nitride-based layer206). Based on ruthenium material being on the inner surface of the cobalt-based liner210, the ruthenium material may reduce a pinch point at a top portion of the via204and may improve deposition of a metal material (e.g., a copper material) within the via204.

In some implementations, the ruthenium material and the cobalt material may partially mix. For example, atoms of the ruthenium material may react (e.g., bond) with atoms of the cobalt material. In some implementations, based on the ruthenium material and the cobalt material partially or fully intermixing, the cobalt-based liner210may have a more-uniform thickness (e.g., based on a reduced surface tension at a top portion of the via204) and may reduce a pinch point at the top portion of the via204.

The cobalt-based liner210may be an optional layer of the semiconductor device200. The semiconductor device200may include the cobalt-based liner210between the ruthenium-based liner208and another material within the via204(e.g., copper material212shown atFIG.2E). In implementations that include the cobalt-based liner210, the cobalt-based liner210may have a thickness in a range of approximately 0.5 to 3 nanometers (e.g., as deposited and before mixing with the ruthenium-based liner208). A combined ruthenium layer (e.g., including the ruthenium-based liner208and the cobalt-based liner210) may have a thickness in a range of approximately 1 to 5 nanometers. In some implementations, the semiconductor device200may not include the cobalt-based liner210, and the ruthenium-based liner208may be in contact with another material within the via204(e.g., the copper material212shown atFIG.2E).

As shown byFIG.2E, one or more semiconductor processing tools may deposit a copper material212within the via204and/or outside of the via204of the semiconductor device200(e.g., on the upper surface of the semiconductor device200). In some implementations, the copper material may be disposed on the ruthenium-based liner208, on the cobalt-based liner210, or on the combined ruthenium-based liner. In some implementations, a deposition tool (e.g., deposition tool102) may deposit the copper material212within the via204(e.g., on the ruthenium-based liner208, on the cobalt-based liner210, or on the combined ruthenium-based liner) of the semiconductor device200. In some implementations, the deposition tool may use high density plasma deposition, plasma-enhanced chemical vapor deposition, chemical vapor deposition, or physical vapor deposition, among other examples, to deposit the copper material212within the via204(e.g., on the ruthenium-based liner208, on the cobalt-based liner210, or on the combined ruthenium-based liner). In some implementations, the deposition tool may deposit the copper material212and then perform a reflow deposition operation, such as plating the copper material212and/or heating the copper material to cause the copper material212to flow into the via204.

As shown byFIG.2F, one or more semiconductor processing tools may remove an upper portion of the semiconductor device200. In some implementations, a CMP tool (e.g., CMP tool106) may planarize the upper surface of the semiconductor device200and remove the upper portion of the semiconductor device200. In some implementations, the CMP tool may remove one or more materials, such as the tantalum nitride-based liner206, the ruthenium-based liner208, the cobalt-based liner210, and/or the copper material212from the semiconductor device200in a region outside of the via204(e.g., from the upper surface of the semiconductor device200).

In some implementations, the CMP tool may form a copper interconnect within the via204that comprises a copper plug214(e.g., from the copper material212within the via204), the cobalt-based liner210, the ruthenium-based liner208, and/or the tantalum nitride-based liner206, among other example materials.

As shown by reference number2G, one or more semiconductor processing tools may deposit a ruthenium cap216on an upper portion of the semiconductor device200(e.g., an upper surface of copper plug214, an upper surface of the cobalt-based liner210, an upper surface of the ruthenium-based liner, an upper surface of the combined ruthenium-based liner, and/or an upper surface of the tantalum nitride-based liner, among other example materials). In some implementations, deposition of the ruthenium cap216may include multiple operations by one or more semiconductor processing tools.

For example, a pre-cleaning tool (e.g., pre-cleaning tool108) may remove residue (e.g., remaining from an operation of the CMP tool) from the upper surface of the semiconductor device200before depositing the ruthenium cap216. In some implementations, the pre-cleaning tool may apply, directly or remotely, hydrogen gas and/or ammonia plasma to the upper surface of the semiconductor device to perform a pre-cleaning operation.

Additionally, or alternatively, one or more semiconductor processing tools (e.g., deposition tool102and/or pre-cleaning tool108) may apply one or more low-k surface (e.g., a material with a small dielectric constant) modifications to the upper surface of the semiconductor device200. In some implementations, applying the one or more low-k surface modifications to the upper surface of the semiconductor device200may include applying one or more surfactants (e.g., an amonsilane) to the upper surface of the semiconductor device200. In some implementations, the one or more surfactants may react with an upper surface of the substrate202to resist and/or prevent deposition of ruthenium on the upper surface of the substrate202. In some implementations, the one or more surfactants may cause the upper surface of the substrate202to become hydrophobic.

Additionally, or alternatively, one or more semiconductor processing tools (e.g., deposition tool102and/or pre-cleaning tool108) may perform a soaking operation to improve ruthenium deposition selectivity (e.g., to facilitate deposition of the ruthenium on materials in the via204and to resist deposition of the ruthenium on the substrate202). In some implementations, the one or more semiconductor processing tools may apply methanol and/or a hydrogen soak to the upper surface of the semiconductor device200(e.g., on upper surfaces of the substrate202and/or materials in the via204) to improve the ruthenium deposition selectivity.

In some implementations, a deposition tool (e.g., deposition tool102) may deposit ruthenium material to form the ruthenium cap216on an upper surface of materials within the via204of the semiconductor device200. In some implementations, the deposition tool may use high density plasma deposition, plasma-enhanced chemical vapor deposition, chemical vapor deposition, or physical vapor deposition, among other examples, to deposit the ruthenium material on the materials within the via204(e.g., the copper plug214and/or or one or more liners).

In some implementations, the one or more semiconductor processing tools may repeat one or more of the multiple operations, including application of one or more low-k surface modifications, a soaking operation, and/or deposition of ruthenium material. In other words, the one or more semiconductor processing tools may iteratively perform the multiple operations to form the ruthenium cap216on the upper surface of the materials within the via204. In some implementations, the ruthenium cap216may have a thickness of approximately 0.5 to 3 nanometers.

In some implementations, the one or more semiconductor processing tools may optionally deposit the ruthenium cap216(e.g., the ruthenium cap216may be included or excluded from the semiconductor device200). For example, the one or more semiconductor processing tools may deposit the ruthenium cap216based on the semiconductor device200including the ruthenium-based liner208and not including the cobalt-based liner210(e.g., or a combined ruthenium-based liner208that includes cobalt material). In some implementations, the ruthenium cap216may prevent leaking and/or electromigration of material of a cobalt cap (e.g., cobalt cap218ofFIG.2H) into the cobalt-based liner210.

As shown byFIG.2H, one or more semiconductor processing tools may deposit a cobalt cap218on the material within the via204and/or on the ruthenium cap216. In some implementations, the cobalt cap218may be disposed on the ruthenium cap216, if included in the semiconductor device200, or on material within the via204of the semiconductor device200(e.g., the copper plug214and/or or one or more liners). In some implementations, the cobalt cap may have a thickness of approximately 1 to 5 nanometers. In some implementations, a deposition tool (e.g., deposition tool102) may deposit the cobalt cap218on the ruthenium cap216and/or on material within the via204of the semiconductor device200. In some implementations, the deposition tool may use high density plasma deposition, plasma-enhanced chemical vapor deposition, chemical vapor deposition, or physical vapor deposition, among other examples, to deposit the cobalt cap218on the ruthenium cap216and/or on material within the via204of the semiconductor device200. In some implementations, the cobalt cap may reduce electromigration between the copper plug214and one or more materials that may be formed on the copper interconnect.

In some implementations, the ruthenium cap216and the cobalt cap218may intermix to form a combined cap that includes ruthenium material and cobalt material. In some implementations, the combined cap may include some ruthenium material on a lower surface of the combined cap and some cobalt material on the lower surface of the combined cap.

The number and arrangement of structures and/or layers, among other examples, shown inFIGS.2A-2Hare provided as an example. In practice, a semiconductor device including additional structures and/or layers, fewer structures and/or layers, different structures and/or layers, or differently arranged structures and/or layers than those shown inFIGS.2A-2Hmay be processed according to the techniques described above in connection withFIGS.2A-2H.

FIGS.3A-3Fare diagrams of a examples semiconductor devices200A-200F formed based on the example techniques described in connection withFIGS.2A-2H.

As shown inFIG.3A, the semiconductor device200A includes a substrate202that includes a via, a tantalum nitride-based liner206deposited within the via on the substrate202, a ruthenium-based liner208within the via on the tantalum nitride-based liner206, and a cobalt-based liner210on the ruthenium-based liner208. The semiconductor device200A also includes a copper plug214within the via and on the cobalt-based liner210. As described above, the cobalt-based liner210and the ruthenium-based liner208may intermix so that the copper plug214is in contact with ruthenium material of the ruthenium-based liner208and cobalt material of the cobalt-based liner210. The semiconductor device200A further includes a ruthenium cap216disposed on the copper plug214and/or one or more other materials within the via and a cobalt cap218disposed on the ruthenium cap216.

As shown inFIG.3B, the semiconductor device200B includes a substrate202that includes a via, a tantalum nitride-based liner206deposited within the via on the substrate202, and a ruthenium-based liner208within the via on the tantalum nitride-based liner206. The semiconductor device200B also includes a copper plug214within the via and on the ruthenium-based liner208. In this example, semiconductor device200B includes no cobalt-based liner210(e.g., the ruthenium-based liner208does not include cobalt-based material). The semiconductor device200B further includes a ruthenium cap216disposed on the copper plug214and/or one or more other materials within the via and a cobalt cap218disposed on the ruthenium cap216.

As shown inFIG.3C, the semiconductor device200C includes a substrate202that includes a via, a tantalum nitride-based liner206deposited within the via on the substrate202, a ruthenium-based liner208within the via on the tantalum nitride-based liner206, and a cobalt-based liner210on the ruthenium-based liner208. The semiconductor device200C also includes a copper plug214within the via and on the cobalt-based liner210. As described above, the cobalt-based liner210and the ruthenium-based liner208may intermix so that the copper plug214is in contact with ruthenium material of the ruthenium-based liner208and cobalt material of the cobalt-based liner210. The semiconductor device200C further includes a cobalt cap218disposed on the copper plug214and/or one or more other materials within the via.

As shown inFIG.3D, the semiconductor device200D includes a substrate202that includes a via, a tantalum nitride-based liner206deposited within the via on the substrate202, a ruthenium-based liner208within the via on the tantalum nitride-based liner206, and no cobalt-based liner210on the ruthenium-based liner208. The semiconductor device200D also includes a copper plug214within the via and on the ruthenium-based liner208. In some implementations, the ruthenium-based liner208may be a combined ruthenium-based liner that includes cobalt material. The semiconductor device200D further includes a ruthenium cap216disposed on the copper plug214and/or one or more other materials within the via.

As shown inFIG.3E, the semiconductor device200E includes a substrate202that includes a via, a tantalum nitride-based liner206deposited within the via on the substrate202, a combined liner302(e.g., including ruthenium-based material and cobalt-based material) on the tantalum nitride-based liner206. The semiconductor device200E also includes a copper plug214within the via and on the cobalt-based liner210. As described above, the combined liner302may be formed from the cobalt-based liner210and the ruthenium-based liner208intermixing. The semiconductor device200E further includes a cobalt cap218disposed on the copper plug214and/or one or more other materials within the via (e.g., the combined liner302).

As shown inFIG.3F, the semiconductor device200F includes a substrate202that includes a via, a tantalum nitride-based liner206deposited within the via on the substrate202, a combined liner302(e.g., including ruthenium-based material and cobalt-based material) on the tantalum nitride-based liner206. The semiconductor device200F also includes a copper plug214within the via and on the cobalt-based liner210. As described above, the combined liner302may be formed from the cobalt-based liner210and the ruthenium-based liner208intermixing. The semiconductor device200F further includes a ruthenium cap216disposed on the copper plug214and/or one or more other materials within the via (e.g., the combined liner302).

As indicated above,FIGS.3A-3Fare provided as examples. Other examples may differ from what is described with regard toFIGS.3A-3F.

FIG.4is a diagram of example components of a device400. In some implementations, deposition tool102, etching tool104, CMP tool106, pre-cleaning tool108and/or wafer/die transport device110may include one or more devices400and/or one or more components of device400. As shown inFIG.4, device400may include a bus410, a processor420, a memory430, a storage component440, an input component450, an output component460, and a communication component470.

Bus410includes a component that enables wired and/or wireless communication among the components of device400. Processor420includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor420is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor420includes one or more processors capable of being programmed to perform a function. Memory430includes a random access memory, a read only memory, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory).

Storage component440stores information and/or software related to the operation of device400. For example, storage component440may include a hard disk drive, a magnetic disk drive, an optical disk drive, a solid state disk drive, a compact disc, a digital versatile disc, and/or another type of non-transitory computer-readable medium. Input component450enables device400to receive input, such as user input and/or sensed inputs. For example, input component450may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system component, an accelerometer, a gyroscope, and/or an actuator, among other examples. Output component460enables device400to provide output, such as via a display, a speaker, and/or one or more light-emitting diodes. Communication component470enables device400to communicate with other devices, such as via a wired connection and/or a wireless connection. For example, communication component470may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna, among other examples.

Device400may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory430and/or storage component440) may store a set of instructions (e.g., one or more instructions, code, software code, and/or program code, among other examples) for execution by processor420. Processor420may execute the set of instructions to perform one or more processes described herein. In some implementations, execution of the set of instructions, by one or more processors420, causes the one or more processors420and/or the device400to perform one or more processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

FIG.5is a flowchart of an example process of manufacturing a semiconductor device. In some implementations, one or more process blocks ofFIG.5may be performed by one or more semiconductor processing tools (e.g., one or more of deposition tool102, etching tool104, CMP tool106, pre-cleaning tool108, and/or wafer/die transport device110). Additionally, or alternatively, one or more process blocks ofFIG.5may be performed by one or more components of device400, such as processor420, memory430, storage component440, input component450, output component460, and/or communication component470.

As shown inFIG.5, process500may include forming a via within a substrate of the semiconductor device (block510). For example, the one or more semiconductor processing tools may form a via204within a substrate202of the semiconductor device200, as described above.

As further shown inFIG.5, process500may include depositing a ruthenium-based liner within the via (block520). For example, the one or more semiconductor processing tools may deposit a ruthenium-based liner208within the via204, as described above.

As further shown inFIG.5, process500may include depositing, after depositing the ruthenium-based liner, a copper plug within the via (block530). For example, the one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner208, a copper plug214within the via204, as described above.

In a first implementation, process500includes depositing, before depositing the ruthenium-based liner208within the via204, a tantalum nitride-based liner206within the via204, wherein depositing the ruthenium-based liner208within the via204comprises depositing the ruthenium-based liner208on the tantalum nitride-based liner206.

In a second implementation, alone or in combination with the first implementation, process500includes depositing, before depositing the copper plug214within the via204, a cobalt-based liner210within the via204, wherein depositing the copper plug214within the via204comprises depositing the copper plug214on the cobalt-based liner210.

In a third implementation, alone or in combination with one or more of the first and second implementations, depositing the copper plug214within the via204comprises depositing copper material212within the via204and on an upper surface of the semiconductor device200, and performing, after depositing the copper material212, a chemical-mechanical polishing process to remove the copper material212from the upper surface of the semiconductor device200.

In a fourth implementation, alone or in combination with one or more of the first through third implementations, process500includes depositing, after depositing the copper plug214, a ruthenium cap216on an upper surface of the via204.

In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, process500includes performing, before depositing the ruthenium cap216and after performing a chemical-mechanical polishing process on an upper surface of the copper plug214, a pre-cleaning operation on an upper surface of the semiconductor device200.

In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, performing the pre-cleaning operation comprises application of one or more of hydrogen or ammonia plasma.

In a seventh implementation, alone or in combination with one or more of the first through sixth implementations, process500includes applying, before depositing the ruthenium cap216, a surfactant material to an upper surface of the substrate202, wherein the surfactant material is configured to react with the substrate202to resist deposition of ruthenium material on the upper surface of the substrate202.

In an eighth implementation, alone or in combination with one or more of the first through seventh implementations, process500includes applying, before depositing the ruthenium cap216, one or more of methanol or a hydrogen soak to an upper surface of the substrate202, wherein the one or more of the methanol or the hydrogen soak are configured to react with the substrate202to resist deposition of ruthenium material on the upper surface of the substrate202.

In a ninth implementation, alone or in combination with one or more of the first through eighth implementations, process500includes depositing a cobalt cap218on an upper surface of the ruthenium cap216.

In a tenth implementation, alone or in combination with one or more of the first through ninth implementations, depositing the copper plug214comprises depositing the copper plug214using a reflow deposition operation.

Based on using a ruthenium-based liner within the via, copper material may penetrate the via during a deposition process, even when using a narrow via (e.g., less than about 12 nanometers). In some implementations, the ruthenium-based liner may reduce protrusion into a top portion of the via and/or may reduce a pinch point at the top portion of the via. This may facilitate deposition of the copper plug within the via, which may improve uniformity of copper material within the via, reduce voids within the via, and improve performance of the copper plug as a copper interconnect within the semiconductor device.

As described in greater detail above, some implementations described herein provide a method of manufacturing a semiconductor device. The method includes forming a via within a substrate of the semiconductor device. The method includes depositing a ruthenium-based liner within the via. The method includes depositing, after depositing the ruthenium-based liner, a copper plug within the via.

As described in greater detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a via within a substrate. The semiconductor device includes a ruthenium-based liner disposed within the via. The semiconductor device includes a copper plug disposed on the ruthenium-based liner within the via.

As described in greater detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a via within a substrate. The semiconductor device includes a liner, including ruthenium material and cobalt material, disposed within the via. The semiconductor device includes a copper plug disposed on at least a portion of the liner.