High density film for IC package

The present invention discloses a high density film for IC package. The process comprises: a redistribution layer is fabricated following IC design rule, with a plurality of bottom pad formed on bottom, and with a plurality of first top pad formed on top; wherein the density of the plurality of bottom pad is higher than the density of the plurality of first top pad; and a top redistribution layer is fabricated following PCB design rule, using the plurality of the first top pad as a starting point; with a plurality of second top pad formed on top; wherein a density of the plurality of first top pad is higher than a density of the plurality of second top pad.

BACKGROUND

Technical Field

The present invention relates to a high density film for IC package, especially relates to a high density film without having any interposer. A traditional interposer includes such as a semiconductor interposer with through silicon via (TSV) or a glass interposer with through glass via (TGV) embedded therein.

Description of Related Art

FIG. 1shows a prior art substrate for IC package

FIG. 1shows a prior art substrate for IC package disclosed in US2014/0102777A1 which has an embedded silicon interposer20. The silicon interposer20has four later sides206. A molding compound22wraps the silicon interposer20around the four lateral sides206. A plurality of via metal200is made through the silicon interposer20. An insulation liner201is made between the through via200and the silicon interposer20for an electrical insulation there-between. A top redistribution layer21is made on top of the silicon interposer20with a plurality of metal pad210exposed on top. The plurality of metal pad210on top is provided for accommodating an IC chip (not shown) to mount. A circuit built-up layer25is made on bottom of the silicon interposer20with a plurality of metal pad220configured on bottom. A plurality of solder ball4is configured and each solder ball4is configured on bottom of a corresponding bottom metal pad220.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 2A˜2M show a process for fabricating a high density film according to the present invention.

FIG. 2Ashows a temporary carrier I is prepared, a first release layer31is applied on top of the temporary carrier I, and a seed layer32, such Ti/Cu, is formed on top of the first release layer31.

FIG. 2Bshows a patterned photoresist33is formed on top of the seed layer32.

FIG. 2Cshows a plurality of bottom pad341is formed on top of the seed layer32.

FIG. 2Dshows the patterned photoresist33is removed and a plurality of bottom pad341is left.

FIG. 2Fshows a first redistribution circuitry342is formed following IC design rule, using the plurality of bottom pad341as a starting point, comprising the steps: a first dielectric layer351is applied on top of the bottom pad341, and then a first redistribution circuitry342is formed through traditional technique.

FIG. 2Gshows a plurality of first top pad343is formed comprising the following steps: a second dielectric layer352is applied on top of the first redistribution circuitry342, a plurality of first top pad343is formed through traditional technique. A first redistribution circuitry342and a plurality of first top pad343are exemplified in this embodiment. The redistribution circuitry layer can be repeatedly processed to even more layers to fan out the circuitry if desired. The bottom pad341, the first redistribution circuitry342and the first top pad343are collectively called circuitry film RDL I.

FIG. 2Hshows the temporary carrier I is removed to form a circuitry film RDL I. And then a singulating process is performed to produce a plurality of single unit of circuitry film RDL I.

FIG. 2Ishows a single unit of circuitry film RDL I.

FIG. 2Jshows a temporary carrier II is prepared. A second release layer311is applied on top of the temporary carrier II. A plurality of circuitry film RDL I is arranged on top of the second release layer311.

FIG. 2Kshows a second redistribution circuitry441is formed following PCB design rule, using the plurality of first top pad343as a starting point, comprising the steps: a third dielectric layer451is applied on top of the circuitry film RDL I, and then a second redistribution circuitry441is formed through traditional technique.

The dielectric layer used for PCB process can be one of Ajinomoto build-up films (ABF) or Pre-preg (PP).

FIG. 2Lshows a plurality of second top pad442is formed, comprising the steps: a fourth dielectric layer452is applied on top of the second redistribution circuitry441and the third dielectric layer451, a plurality of second top pad442is formed through traditional technique. A second redistribution circuitry441and a plurality of second top pad442are exemplified in this embodiment. The redistribution circuitry can be repeatedly processed to even more layers to fan out the circuitry if desired. The redistribution circuitry441and the second top pad442are collectively called circuitry film RDL II. A high density film (RDL I+RDL II) is formed on top of the second release layer311.

FIG. 2Mshows the temporary carrier II is removed, and a high density film (RDL I+RDL II) is released.

FIGS. 2N˜2S show a fabricating process for an IC package using the high density film according to the present invention.

FIG. 2Nshows at least one chip51is mounted on a bottom of the bottom pad341.

FIG. 2Oshows a molding compound511is applied to encapsulate the chip or chips51.

FIG. 2Pshows a thinning process is applied onto the molding compound511to reveal a bottom surface of the chip51for heat dissipation of the chip.

FIG. 2Qshows a dielectric layer521is applied between the second top pads442, and a plurality of solder ball52is planted, each solder ball52is configured on top of a corresponding top pad442.

FIG. 2Rshows a heat sink53is configured on a bottom surface of the chip51for further heat dissipation.

FIG. 2Sshows a single unit of the IC package is formed after a singulating process applied on the product ofFIG. 2R.

FIG. 3shows a process flow for fabricating a high density film according to the present invention, comprises:

fabricating a bottom redistribution layer RDL I following IC design rule, with a plurality of bottom pad341formed on bottom, and with a plurality of first top pad343formed on top; wherein the density of the plurality of bottom pad341is higher than the density of the plurality of first top pad343; and

fabricating a top redistribution layer RDL II following PCB design rule, using the plurality of the first top pad343as a starting point; with a plurality of second top pad442formed on top; wherein a density of the plurality of first top pad343is higher than a density of the plurality of second top pad442.

FIG. 4shows a further process flow for fabricating a high density film, comprises:

preparing a temporary carrier I;

applying a first release layer31on top of the temporary carrier I;

forming a seed layer32on top of the first release layer31;

forming a plurality of bottom pad341on top of the seed layer;

etching the seed layer between the bottom pads341;

forming a bottom redistribution layer RDL I following IC design rule, using the bottom pad341as a starting point; with a plurality of first top pad343formed on top, to form circuitry film RDL I;

removing the temporary carrier I to release the circuitry film RDL I;

singulating the circuitry film RDL I to produce a plurality of RDL I unit

preparing a temporary carrier II;

applying a second release layer311on top of the temporary carrier II;

arranging a plurality of the RDL I unit on top of the second release layer311;

forming a second top redistribution layer RDL II following PCB design rule on top of the plurality of RDL I unit, using the first top pad343as a starting point; with a plurality of second top pad442formed on top; and

removing the temporary carrier II to release a high density film (RDL I+RDL II).

FIG. 5shows a process flow for fabricating an IC package using the high density film according to the present invention, comprises:

removing the temporary carrier I to release the bottom redistribution layer RDL I;

singulating the bottom redistribution layer RDL I to produce a plurality of RDL I unit;

preparing a temporary carrier II;

applying a second release layer311on top of the temporary carrier II;

arranging a plurality of the RDL I unit on a top of the second release layer311;

forming a second top redistribution layer RDL II following PCB design rule on top of the plurality of RDL I unit, using the plurality of first top pad343as a starting point; with a plurality of second top pad442formed on top;

removing the temporary carrier II to release a high density film (RDL I+RDL II);

mounting at least one chip51on bottom of the plurality of bottom pad341;

molding the chip51with a molding compound511;

thinning the molding compound511from bottom to reveal the bottom surface of the chip51;

mounting a heat sink53on bottom of the chip51; and

singulating to produce a plurality of separated unit.

While several embodiments have been described by way of example, it will be apparent to those skilled in the art that various modifications may be configured without departs from the spirit of the present invention. Such modifications are all within the scope of the present invention, as defined by the appended claims.