Semiconductor equipment

Semiconductor equipment includes a semiconductor substrate with a semiconductor layer embedded therein and a vertical type transistor. The substrate has a principal side, a rear side opposite to the principal side, and a trench disposed in the rear side of the substrate. The vertical type transistor has a first electrode disposed in the principal side of the substrate, a second electrode disposed in the rear side, and a diffusion region disposed in the principal side. The first electrode connects to the diffusion region through an interlayer insulation film. The second electrode is disposed in the trench and connects to the semiconductor layer exposed in the trench. This vertical transistor has a low ON-state resistance.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on Japanese Patent Applications No. 2002-273117 filed on Sep. 19, 2002, and No. 2003-307286 filed on Aug. 29, 2003, the disclosures of which are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to semiconductor equipment, specifically, the present invention relates to semiconductor equipment having a low ON-state resistance transistor.

BACKGROUND OF THE INVENTION

Semiconductor equipment200having a metal oxide semiconductor transistor (i.e., a MOS transistor) according to a prior art is disclosed in Japanese Patent No. 3257057-B2 (Japanese Unexamined Patent Application Publication No. H05-198758). As shown inFIG. 14, the semiconductor equipment200includes a semiconductor substrate3. An insulation layer4having a box shape (i.e., a box type insulation layer) is disposed in the substrate3. The insulation layer4has three openings for opening upside of the substrate3. Each opening is divided by a vertical wall of the insulation layer4, and accommodates a control unit5and two MOS field effect transistors (two MOSFETS)2A,2B. The control unit5provides a logic circuit or a gate drive circuit.

Each MOSFET2A,2B is disposed on the right or left side of the control unit5, respectively, and is a lateral double-diffused MOSFET (i.e., a L-DMOS). Each L-DMOS2A,2B includes a source21, a drain22, and a gate23. The source21and the drain22are separated in a horizontal direction, and are formed with an impurity diffusion method. Specifically, the source21of each L-DMOS2A,2B is formed by a double diffusion method, which provides to diffuse from the surface of the substrate3, and the source21is grounded.

A vertical double-diffused MOSFET (i.e., a V-DMOS)1A,1B is disposed on both sides of the box type insulation layer4, i.e., each V-DMOS1A,2B is disposed on right or left side of the insulation layer4, respectively. Each V-DMOS1A,1B includes a source11, a drain12, and a gate13. The source11is formed by the double diffusion method, which provides to diffuse from the surface of the substrate3. Both V-DMOS1A,1B have the common drain12, which is disposed on a rear side of the substrate3and connects to an electric power source B.

To form the box type insulation layer4in the semiconductor equipment200, it is necessary to form a silicon on insulator structure (i.e., an SOI structure) selectively, as described above. Therefore, the manufacturing cost of the semiconductor equipment200becomes higher. Moreover, the drain12of the V-DMOS1A,1B is common, so that degree of freedom for designing a multi-channel switch formed by a plurality of V-DMOSs becomes lower.

It is considered that an SOI substrate embedding an insulation film therein is used as the substrate4so as to lower the manufacturing cost of the semiconductor equipment200and to increase the degree of freedom for designing. In this case, an N+type semiconductor layer as the drain12is formed on the insulation layer in the SOI substrate. A resistance of the N+type semiconductor layer in the V-DMOS becomes a rate-determining factor, so that it is difficult to reduce an ON-state resistance of the V-DMOS.

SUMMARY OF THE INVENTION

In view of the above problem, it is an object of the present invention to provide semiconductor equipment having a low ON-state resistance transistor. Further, it is another object of the present invention to provide semiconductor equipment having highly degree of freedom for forming a multi-channel switch.

Semiconductor equipment includes a semiconductor substrate with a semiconductor layer embedded therein and a vertical type transistor. The substrate has a principal side, a rear side opposite to the principal side, and a trench disposed in the rear side of the substrate. The vertical type transistor has a first electrode disposed in the principal side of the substrate, a second electrode disposed in the rear side, and a diffusion region disposed in the principal side. The first electrode connects to the diffusion region through an interlayer insulation film. The second electrode is disposed in the trench and connects to the semiconductor layer exposed in the trench. Preferably, the first electrode includes a first metal layer, and the second electrode includes a second metal layer.

In the above equipment, the trench is disposed in the rear side of the substrate, and the second metal layer embedded in the trench provides the second electrode. Therefore, a current path between the first and second electrodes becomes short, so that the resistance between the first and second electrodes is reduced. Thus, an ON-state resistance between the first and second electrodes is also decreased, i.e., the vertical transistor has a low ON-state resistance.

Preferably, the trench has a taper shape. In this case, the second metal layer disposed in the trench radiates heat generated in the vertical transistor effectively. Moreover, since the trench can be formed by a wet etching method, a manufacturing cost of the semiconductor equipment is reduced.

Preferably, the trench is filled with the second metal layer. In this case, the second metal layer disposed in the trench radiates heat generated in the vertical transistor effectively. Moreover, the resistance of the second electrode is decreased.

Preferably, the vertical type transistor is a metal oxide semiconductor transistor, and the first electrode provides a source electrode of the metal oxide semiconductor transistor, and the second electrode provides a drain electrode of the metal oxide semiconductor transistor. In this case, an ON-state resistance between the source and the drain of the MOS transistor is decreased.

Preferably, the semiconductor substrate includes a first semiconductor layer having a first conductive type and a second semiconductor layer having the first conductive type, the second semiconductor layer being disposed on the first semiconductor layer and having a low dope concentration lower than that of the first semiconductor layer. Further, the trench reaches the first semiconductor layer, and the metal oxide semiconductor transistor includes a drain provided by the first semiconductor layer, a channel diffusion region having a second conductive type and disposed on a surface portion of the second semiconductor layer, a source diffusion region having the first conductive type and disposed on a surface portion of the channel diffusion region, and a gate electrode contacting a part of the channel diffusion region through a gate insulation film. In this case, the resistance of the first semiconductor layer is reduced, so that an ON-state resistance between the source and the drain is decreased.

Preferably, the semiconductor substrate includes a silicon on insulator substrate having an insulation film embedded therein. The fist and second semiconductor layers are disposed on the principal side with respect to the insulation film. The trench penetrates the insulation film and reaches the first semiconductor layer. In this case, the second metal layer contacts the first semiconductor layer exposed in the trench. Accordingly, the resistance of the first semiconductor layer as the drain is reduced, so that the ON-state resistance between the source and the drain is decreased.

Preferably, the metal oxide semiconductor transistor further includes a drain connection diffusion region having the first conductive type. The drain connection diffusion region is disposed from a principal side surface of the second semiconductor layer to the first semiconductor layer so as to contact the first semiconductor layer. In this case, a drain current flowing through the MOS transistor can be monitored.

Preferably, the gate electrode penetrates the channel diffusion region, and reaches the second semiconductor layer. In this case, the current path between the source and the drain becomes short, so that the ON-state resistance between the source and the drain is further decreased.

Preferably, the vertical type transistor is an insulated gate bipolar transistor. The first electrode provides an emitter electrode of the insulated gate bipolar transistor, and the second electrode provides a collector electrode of the insulated gate bipolar transistor. In this case, an ON-state resistance between the emitter and the collector is decreased.

Preferably, the vertical type transistor is a bipolar transistor. The first electrode provides an emitter electrode of the bipolar transistor, and the second electrode provides a collector electrode of the bipolar transistor. In this case, an ON-state resistance between the emitter and the collector is decreased.

Preferably, the semiconductor substrate further includes a separator for surrounding a main part of the vertical type transistor. The separator reaches the insulation film so that the main part of the vertical type transistor is isolated from surroundings by the separator. In this case, the vertical transistor is limited to be affected by other device disposed around the vertical transistor.

Preferably, the trench has a sidewall covered with a sidewall insulation film. The second metal layer disposed in the trench is isolated from surroundings by the sidewall insulation film. In this case, the vertical transistor is limited to be affected by other device disposed around the vertical transistor.

Preferably, the semiconductor equipment is mounted on a printed circuit board by a flip chip mounting method in such a manner that the principal side with respect to the insulation film faces the printed circuit board. In this case, heat generated in the vertical transistor radiates through the second metal layer effectively, so that heat radiation of the semiconductor equipment is improved.

Preferably, the second metal layer is connected to a heat sink with solder. In this case, the heat generated in the vertical transistor radiates through the second metal layer to the heat sink effectively, so that heat radiation of the semiconductor equipment is further improved.

Preferably, the semiconductor equipment is mounted in a multi-layer printed circuit board in such a manner that the semiconductor equipment is embedded in the multi-layer printed circuit board. The semiconductor equipment can be mounted compactly.

Preferably, the vertical type transistor includes a plurality of transistors for providing a multi-channel switch. In this case, the multi-channel switch has a low ON-state resistance.

Preferably, the multi-channel switch further includes an electric load impedance. A plurality of transistors and the electric load impedance are disposed between a power source and a ground for providing a high side switch, in which the vertical type transistor is disposed on a power source side and the electric load impedance is disposed on a ground side. In this case, the multi-channel high side switch has a low ON-state resistance.

Further, semiconductor equipment includes a semiconductor substrate, and a metal oxide semiconductor transistor disposed on the semiconductor substrate. The semiconductor substrate includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a first conductive type for providing a drain of the metal oxide semiconductor transistor. The second semiconductor layer has the first conductive type, is disposed on the first semiconductor layer, and has a low dope density lower than that of the first semiconductor layer. The metal oxide semiconductor transistor includes a channel diffusion region, a source diffusion region, and a gate electrode. The channel diffusion region has a second conductive type, and is disposed on a surface portion of the second semiconductor layer. The source diffusion region has the first conductive type, and is disposed on a surface portion of the channel diffusion region. The gate electrode contacts a part of the channel diffusion region through a gate insulation film. The first semiconductor layer includes a trench disposed from a surface of the first semiconductor layer to the second semiconductor layer, and a metal layer as an electrode disposed in the trench.

In the above equipment, a current path between the first semiconductor layer and the source diffusion region becomes short, so that the resistance between them is reduced. Thus, an ON-state resistance between them is also decreased, i.e., the MOS transistor has a low ON-state resistance.

Furthermore, semiconductor equipment includes a semiconductor substrate provided by a silicon on insulator substrate having an insulation film embedded therein, and a metal oxide semiconductor transistor disposed on the semiconductor substrate. The semiconductor substrate includes a first semiconductor layer and a second semiconductor layer, which are disposed on a principal side of the substrate with respect to the insulation film. The first semiconductor layer has a first conductive type for providing a drain of the metal oxide semiconductor transistor. The second semiconductor layer has the first conductive type, is disposed on the first semiconductor layer, and has a low dope density lower than that of the first semiconductor layer. The metal oxide semiconductor transistor includes a channel diffusion region, a source diffusion region, and a gate electrode. The channel diffusion region has a second conductive type, and is disposed on a surface portion of the second semiconductor layer. The source diffusion region has the first conductive type, and is disposed on a surface portion of the channel diffusion region. The gate electrode contacts a part of the channel diffusion region through a gate insulation film. The semiconductor substrate further includes a trench and a metal layer. The trench is disposed on a rear side of the substrate opposite to the principal side, is disposed from a rear surface of the substrate, penetrates the insulation film, and reaches the first semiconductor layer. The metal layer as an electrode is disposed in the trench and contacts the first semiconductor layer.

In the above equipment, a current path between the first semiconductor layer and the source diffusion region becomes short, so that the resistance between them is reduced. Thus, an ON-state resistance between them is also decreased, i.e., the MOS transistor has a low ON-state resistance.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Semiconductor equipment100according to a first embodiment of the present invention is shown in FIG.1. The semiconductor equipment100includes a vertical type MOS transistor101and a lateral type bipolar transistor102formed on a semiconductor substrate30. The substrate30is an SOI substrate (i.e., a silicon on insulator substrate) embedding an insulation film32therein. The insulation film32, an N+type first semiconductor layer33, and an N type second semiconductor layer34are formed on a silicon substrate (i.e., a Si substrate)31in this order. The first semiconductor layer33is an N+type semiconductor, and the second semiconductor layer34is an N type semiconductor, a dope density of which is lower than that of the N+type semiconductor.

A P type diffusion layer40is formed on a surface portion of the second semiconductor layer34. Further, an N+type diffusion layer41and a P+type diffusion layer42are formed on a surface portion of the diffusion layer40. Outside of the diffusion region40in a horizontal direction, a P type diffusion region47and a P+type diffusion region48are disposed. Further, outside of the P type diffusion region47in the horizontal direction, an N+type diffusion region45is disposed. The bottom of the N+type diffusion region45reaches the first semiconductor layer33.

In the MOS transistor101, the first semiconductor layer33corresponds to a drain, the P type diffusion region40to a channel, and the N+type diffusion region41to a source. Here, the first semiconductor layer33is the N+type semiconductor and disposed on a principal side of the substrate30, i.e., the first semiconductor layer33is disposed on the principal side with respect to the insulation film32. Here, both the P type diffusion region47and the P+type diffusion region48disposed outside of the diffusion region40in the horizontal direction relieve an electric field outside the diffusion region40, so that the withstand voltage of the MOS transistor101is limited to decrease.

A gate electrode39is disposed on the principal side with respect to the insulation film32, and contacts a part of the diffusion region40through an insulation film (not shown). The diffusion regions41,42,48disposed on the surface of the substrate30are connected mutually to an electrode44through an interlayer insulation film43. In this case, the electrode44provides a source electrode. The N+type diffusion region45disposed between the surface of the substrate30and the first semiconductor layer33connects to the drain, i.e., the first semiconductor layer33so that it performs to monitor the current of the MOS transistor101. Therefore, the diffusion region45can be omitted from the semiconductor equipment100.

On the rear side of the substrate30, which is opposite to the principal side and disposed under the insulation film33, a trench35is disposed such that the trench35is disposed perpendicular to the surface, penetrates the insulation film32, and reaches the first semiconductor layer33. On a sidewall of the trench35, a sidewall insulation film36is formed. A metal layer37as a drain electrode is embedded in the trench35through the sidewall insulation film36so that the metal layer37contacts the first semiconductor layer33, which exposes from the silicon substrate31by the trench35.

The MOS transistor101disposed on the principal side with respect to the insulation film32is isolated and separated from surroundings by a separator38. Also, the metal layer37disposed on the rear side of the insulation film32is isolated and separated from surroundings by the sidewall insulation film36formed on the sidewall of the trench35. A local oxidation of silicon (i.e., a LOCOS) region49is disposed on the separator38.

Next, manufacturing process for manufacturing the semiconductor equipment100is described as follows.

At first, an SOI wafer as the semiconductor substrate30is prepared, as shown in FIG.2A. The separator38, the MOS transistor101, and the bipolar transistor102are formed on the principal side with respect to the insulation film32, so that the principal side of the semiconductor substrate30is accomplished.

Then, the rear surface of the substrate30is polished so that the thickness of the silicon substrate31becomes a predetermined thickness. After that, an oxide film50is deposited on the rear surface of the substrate30by chemical vapor deposition (i.e., CVD) method. The oxide film50is processed and patterned such that a part of the oxide film50disposed under the diffusion region40and the P type diffusion region47is removed so as to expose the silicon substrate31. Then, the silicon substrate31and the insulation film32are etched using the patterned oxide film50as a mask by an anisotropic dry-etching method. Thus, the first semiconductor layer33is exposed from the oxide film50, and the trench35is formed on the rear side of the substrate30.

As shown inFIG. 2B, after the oxide film50is removed, another oxide film (not shown) is deposited on the rear surface of the substrate30by the CVD method. Then, a part of the oxide film is etched by the anisotropic dry-etching method in such a manner that the oxide film disposed on the sidewall of the trench35as the sidewall insulation film36is left only. Thus, the sidewall insulation film36is formed on the sidewall of the trench35.

As shown inFIG. 2C, after metallic material is formed on the rear side of the substrate30by a copper plating method and the like so as to fill the metallic material as the metal layer37in the trench35, the metallic material on the rear side is polished until the silicon substrate31is exposed on the rear surface. Thus, the metal layer37is embedded in the trench35through the sidewall insulation film36. The semiconductor equipment100is accomplished.

In the semiconductor equipment200shown inFIG. 14, the SOI structure is formed selectively in the N+type semiconductor substrate3, so that the V-DMOS1A,1B and the L-DMOS2A,2B as a power device are formed. However, the semiconductor equipment100according to the first embodiment shown inFIG. 1is manufactured by using the SOI substrate30, in which the insulation film32is embedded. Therefore, the semiconductor equipment100is manufactured easily compared with the semiconductor equipment200shown inFIG. 14, so that the manufacturing cost of the semiconductor equipment100is reduced.

Moreover, the MOS transistor101is separated and isolated from surroundings by the insulation film32, the separator38disposed on the insulation film32, and the sidewall insulation film36disposed under the insulation film32. Therefore, it is easy to form a multi-channel switch by using a plurality of isolated MOS transistors. Thus, degree of freedom for forming the multi-channel switch is increased.

As shown as arrows inFIG. 1, electrons are outputted from the N+type diffusion region41as a source, pass through the diffusion region40and the first semiconductor layer33as a drain, and are collected to the metal layer37as a drain electrode. In the MOS transistor101, the N+type first semiconductor layer33formed on the insulation film32in the SOI substrate30corresponds to the N+semiconductor substrate3of the semiconductor equipment200shown in FIG.14. The thickness of the first semiconductor layer33shown inFIG. 1is much thinner than that of the N+semiconductor substrate3shown in FIG.14.

Moreover, in the MOS transistor101, the trench35is formed so as to penetrate the insulation film32and to reach the first semiconductor layer33. Also the metal layer37is embedded in the trench35, and contacts the first semiconductor layer33exposed in the trench35. Therefore, current path between the source and the drain, i.e., current path between the N+diffusion region41and the first semiconductor layer33becomes short, so that the drain resistance of the MOS transistor101(i.e., the resistance between the source and the drain) is much reduced, which is much smaller than that of the V-DMOS1A,1B shown in FIG.14. Thus, the ON-state resistance of the MOS transistor101is also reduced compared with that of the V-DMOS1A,1B shown in FIG.14.

Three semiconductor equipments110,120,130according to a second embodiment of the present embodiment are shown inFIGS. 3-5, respectively.

In a vertical type MOS transistor111of the semiconductor equipment110shown inFIG. 3, the trench35is formed on the rear side of the substrate30, and disposed under the insulation film32. The trench35is disposed perpendicularly to the surface of the substrate30. Comparing with the semiconductor equipment100shown inFIG. 1, no sidewall insulation film is formed on the sidewall of the trench35shown inFIG. 3, so that the metal layer37embedded in the trench35is not isolated and separated from surroundings.

When only one MOS transistor111is formed on the substrate30, or when a plurality of vertical type MOS transistors111having the same drain potential is formed on the substrate30, the semiconductor equipment110having no sidewall insulation film can be used for them. In this case, the forming process for forming the sidewall insulation film is omitted, so that the manufacturing process of the semiconductor equipment110is simplified. Thus, the manufacturing cost of the semiconductor equipment110is reduced.

In a MOS transistor121of the semiconductor equipment120shown inFIG. 4, a trench35A is formed on the rear side of the substrate30such that the trench has a taper shape. The trench35A is disposed under the insulation film32in the substrate30. The trench35A having a taper shape is formed by using alkali etching method. Therefore, the etching process for forming the trench35A is simplified compared with the dry-etching method, so that the manufacturing cost of the semiconductor equipment120is decreased.

In a MOS transistor131of the semiconductor equipment130shown inFIG. 5, the trench35A is formed on the rear side of the substrate30such that the trench has a taper shape. A metal layer37A in the trench35A is a metallic thin film, so that the metal layer37A covers the sidewall of the trench35A. Therefore, the metal layer37A is not embedded in the trench, i.e., the metal layer37A does not fill the trench completely.

The metal layer37A is made of, for example, a multi-layer film of titanium/nickel/gold formed by a sputtering method, or a copper film formed by a plating method. When the trench35A is too deep to embed the metal layer35in the trench35A, the metal layer37A composing the metallic thin film is usable for the semiconductor equipment130instead of the metal layer37embedded in the trench35A shown in FIG.4.

Semiconductor equipment140according to a third embodiment of the present invention is shown in FIG.6. In a vertical type MOS transistor141of the semiconductor equipment140, a P type diffusion region40A is disposed on the surface portion of the second semiconductor layer34. Further, an N+type diffusion region41A is disposed on the surface portion of the diffusion region40A. A gate electrode39A penetrates the diffusion region40A, and reaches the second semiconductor layer34. The gate electrode39A contacts the diffusion regions40A,41A and the second semiconductor layer34through a gate insulation film (not shown).

As shown as arrows inFIG. 6, electrons are outputted from the diffusion region41A as a source, pass through the diffusion region40A as a channel and the first semiconductor layer33as a drain straightly, and are collected into the metal layer37. Therefore, the current path between the source and the drain becomes short compared with that of the MOS transistor101shown inFIG. 1, so that the drain resistance of the MOS transistor141(i.e., the resistance between the source and the drain) is much reduced. Thus, the ON-state resistance of the MOS transistor141is also reduced.

Semiconductor equipment150according to a fourth embodiment of the present invention is shown inFIGS. 7A and 7B.FIG. 7Ais a schematic cross-sectional view showing the semiconductor equipment150, andFIG. 7Bis a schematic cross-sectional view explaining a mounting configuration of the semiconductor equipment150mounted on a printed circuit board153.

In the semiconductor equipment150, only one vertical type MOS transistor151is formed on a semiconductor substrate30A, which includes the first semiconductor layer33A and the second semiconductor layer34. Therefore, the semiconductor equipment150provides a discrete device. A trench35B is disposed in the first semiconductor layer33A, and a metal layer37B is embedded in the trench35B. The first semiconductor layer33A is used as a support substrate. Here, a passivation film50A is disposed on the surface of the substrate30A for protecting the semiconductor equipment150.

As shown inFIG. 7B, the semiconductor equipment150as a discrete device is mounted on the printed circuit board153by using flip chip mounting method. In other words, the semiconductor equipment150is reversed, and the electrode44of the semiconductor equipment150and a solder land52of the printed circuit board153are connected with a solder ball51. That is, the principal side of the substrate30A faces the printed circuit board153.

The metal layer37B dose not connect to a printed circuit on the board153. Therefore, in the MOS transistor151of the semiconductor equipment150, electrons moves along with arrows shown in FIG.7B. In this case, the metal layer37B does not work as a drain electrode. Instead of the metal layer37B, an electrode44D connected to the N+type diffusion region45works as a drain electrode.

The trench35B is formed in the first semiconductor layer33A, and the metal layer37B is formed in the trench35B. Therefore, the resistance of the first semiconductor layer33A as a drain is reduced, so that the ON-state resistance of the MOS transistor151is decreased. Further, heat generated in the MOS transistor151is radiated through the metal layer37B. Therefore, heat radiation of the semiconductor equipment150is improved.

Here, the metal layer37B can attach to a heat sink with a solder. In this case, the heat generated in the MOS transistor151radiates to the heat sink through the metal layer37B, so that the heat radiation of the semiconductor equipment150is further improved.

Semiconductor equipment160according to a fifth embodiment of the present invention is shown in FIG.8.FIG. 8is a schematic cross-sectional view explaining a mounting configuration of the semiconductor equipment160mounted on a printed circuit board165. The semiconductor equipment160includes two vertical type MOS transistors161,162, and two lateral type bipolar transistors163,164. Each MOS transistor161,162has the same structure as the MOS transistor101shown in FIG.1. Each MOS transistor161,162is isolated and separated by the separator38disposed on the principal side of the substrate30and by the sidewall insulation film36disposed on the rear side of the substrate30.

The semiconductor equipment160is mounted on the printed circuit board165by the flip chip mounting method. The electrode44of the MOS transistor161,162and the solder land52S are connected with the solder ball51. The metal layer37as a drain electrode and the solder land52D of the printed circuit board165are connected with a wire53. Thus, heat generated in the MOS transistors161,162is radiated through the metal layer37B, so that the heat radiation of the semiconductor equipment160is improved.

FIG. 9is a schematic cross-sectional view explaining another mounting configuration of the semiconductor equipment160mounted on a multi-layer printed circuit board166. The electrode44of the MOS transistor161,162and the solder land52S of the multi-layer printed circuit board166are connected with the solder ball51. The metal layer37as a drain electrode and the solder land52D of the multi-layer printed circuit board166are connected with a solder54. Thus, the semiconductor equipment160can be mounted compactly, since the semiconductor equipment160is embedded in the multi-layer printed circuit board166.

In the semiconductor equipment160, each MOS transistor161,162is isolated and separated each other. Therefore, by using these two MOS transistors, a low ON-state resistance multi-channel switch is formed.

Semiconductor equipment170according to a sixth embodiment of the present invention is shown inFIGS. 10A and 10B.FIG. 10Ais a circuit diagram explaining a high side switch of the semiconductor equipment170, andFIG. 10Bis a schematic cross-sectional view explaining a mounting configuration of the semiconductor equipment170as the high side switch mounted on a heat sink175.

As shown inFIG. 10A, the high side switch is provided such that vertical type MOS transistors171,172and electric load impedances R1, R2are inserted between an electric power source B and a ground GND. Specifically, the MOS transistors171,172are disposed on the power source side, and the electric load impedances R1, R2are disposed on the ground side. The semiconductor equipment170having two MOS transistors171,172provides a dual-channel high side switch. As shown inFIG. 10A, in a multi-channel high side switch such as the dual-channel high side switch, a drain circuit D of each switch disposed on the power source side can be integrated into one drain circuit. However, a source S of each MOS transistor171,172connects to the electric load impedance R1, R2, respectively.

As shown inFIG. 10B, the semiconductor equipment170as a dual-channel high side switch is mounted on the heat sink175. The semiconductor equipment170includes two MOS transistors171,172and two bipolar transistors173,174. Each MOS transistor171,172has the same structure as the MOS transistor111shown in FIG.3. Each MOS transistor171,172is isolated and separated by the separator38disposed on the principal side of the substrate30in the horizontal direction. However, on the rear side of the substrate30in the vertical direction, no sidewall insulation film is formed on the sidewall of the trench35. The metal layer37in the trench35is connected to the heat sink175with a solder55. Therefore, in the semiconductor equipment170, electrons are outputted from the electrode44, pass through the metal layer37as a drain electrode, and flow into the heat sink175. Since two MOS transistors171,172provides the high side switch, the metal layers37of the MOS transistors171,172as a drain electrode are connected together, so that the drain circuit D is integrated.

Thus, two MOS transistors171,172work as a low ON-state resistance dual-channel high side switch. Heat generated in the two MOS transistors171,172conducts through the metal layer37, which has high thermal conductivity. Then, the heat is radiated to the heat sink175. Therefore, thermal radiation of the semiconductor equipment170is improved.

FIG. 11Ais a circuit diagram explaining an H-bridge circuit of semiconductor equipment180according to a seventh embodiment of the present invention, andFIG. 11Bis a schematic cross-sectional view explaining a mounting configuration of the semiconductor equipment180as the H-bridge circuit switch mounted on a heat sink185.

In the H-bridge circuit, a motor M and four MOS transistors181-184are disposed between the electric power source B and the ground GND, and formed to have a H-shape. Each MOS transistor181-184provides a switch for an electric current circuit. The motor M is switched between a forward drive and a reverse drive. Two vertical type MOS transistors181,182provide high side switches, respectively. Two lateral type MOS transistors183,184provide low side switches, respectively.

As shown inFIG. 11B, the semiconductor equipment180is mounted on a heat sink185. Each of two MOS transistor181,182has the same structure as the vertical type MOS transistor111shown in FIG.3. Each MOS transistor181,182is isolated and separated by the separator38disposed on the principal side of the substrate30in the horizontal direction. However, on the rear side of the substrate30in the vertical direction, no sidewall insulation film is formed on the sidewall of the trench35. The metal layer37in the trench35is connected to the heat sink185with a solder56. Since two MOS transistors181,182are high side switches, the metal layers37of the MOS transistors181,182as a drain electrode are connected together, so that a drain circuit D of each switch can be integrated into one drain circuit. Each of two MOS transistors183,184has a L-DMOS structure, so that each transistor183,184provides a low side switch.

Thus, two MOS transistors181,182work as a low ON-state resistance dual-channel high side switch in the H-bridge circuit. Moreover, heat generated in the two MOS transistors181,182conducts through the metal layer37, which has a high thermal conductivity. Then, the heat is radiated to the heat sink185. Therefore, thermal radiation of the semiconductor equipment180is improved.

Semiconductor equipment190according to an eighth embodiment of the present invention is shown in FIG.12. The semiconductor equipment190includes a vertical type insulated gate bipolar transistor (i.e., IGBT)191and a lateral type MOS transistor192formed on a semiconductor substrate60.

The semiconductor substrate60is the SOI substrate with the insulation film32embedded therein. The insulation film32, a P+type third semiconductor layer63, and the N type fourth semiconductor layer64are stacked on the substrate31in this order. The P type diffusion region40is formed on a primary side of the fourth semiconductor layer64. The N+type diffusion region41and the P+type diffusion region42are formed on the surface portion of the diffusion region40. Outside of the diffusion region40in the horizontal direction, the P type diffusion region47and the P+type diffusion region48are formed. Further, a P+type diffusion region65is formed outside of the P type diffusion region47for relieving an electric field concentrated at an edge of the IGBT191.

In the IGBT191, the P+type third semiconductor layer63formed on the principal side with respect to the insulation film32corresponds to a collector, the P type diffusion region40formed on the surface corresponds to a channel, and the N+type diffusion region41corresponds to an emitter. The P type diffusion region47and the P+type diffusion region48relieve an electric field outside the diffusion region40, so that the withstand voltage of the IGBT191is limited to decrease.

The gate electrode39is formed on the principal side with respect to the insulation film32so as to connect to a part of the diffusion region40as the channel through a gate insulation film (not shown). The diffusion regions41,42,48formed on the principal side commonly connect to the electrode44as the emitter electrode E through the interlayer insulation film43.

The trench35is formed on a rear side of the substrate60under the third semiconductor layer63, is disposed perpendicular to the surface, penetrates the insulation film32, and reaches the third semiconductor layer63. The sidewall insulation film36is formed on the sidewall of the trench35. The metal layer37as a collector electrode C is embedded in the trench35so as to contact the third semiconductor layer63exposed in the trench35.

Comparing the vertical type IGBT191shown inFIG. 12to the vertical MOS transistor101shown inFIG. 1, the P+type third semiconductor layer63inFIG. 12is disposed instead of the N+type first semiconductor layer33in FIG.1. As described before, in the MOS transistor101, electrons are outputted from the N+type diffusion region41as a source, pass through the diffusion region40as a channel and the first semiconductor layer33as a drain, and are collected to the metal layer37as a drain electrode. On the other hand, in the IGBT191, not only electrons but also holes work as a carrier. Therefore, the electrons in the IGBT191flow similar to those in the vertical MOS transistor101shown as arrows in FIG.1. Moreover, the holes in the IGBT191flow in the opposite direction of the electrons.

In the IGBT191, the trench35penetrates the insulation film32, and reaches the third semiconductor layer63. The third semiconductor layer63is exposed in the trench35, so that the metal layer37as the collector electrode contact the third semiconductor layer63. Accordingly, in the IGBT191, current path between the emitter and the collector becomes short, so that the ON-state resistance between the emitter and the collector is reduced.

Although the vertical MOS transistors101,111,121,131,141,151,161,162,171,172,181,182are used in the semiconductor equipments100,110,120,130,140,150,160,170,180shown inFIGS. 1-11, the IGBT191can be used in the semiconductor equipments100,110,120,130,140,150,160,170,180.

Semiconductor equipment195according to a ninth embodiment of the present invention is shown in FIG.13. The semiconductor equipment195includes a vertical type bipolar transistor196and a lateral type MOS transistor197formed on a semiconductor substrate70. The semiconductor substrate70is the SOI substrate with the insulation film32embedded therein. The insulation film32, a N+type fifth semiconductor layer73, and the N type sixth semiconductor layer74are stacked on the substrate31in this order.

A P type diffusion region80is formed on a primary side of the sixth semiconductor layer74. An N+type diffusion region81and a P+type diffusion region82are formed on the surface portion of the diffusion region80. The P+type diffusion region65is formed outside the diffusion region80for relieving an electric field concentrated at an edge of the bipolar transistor196.

The bipolar transistor196is a vertical type NPN bipolar transistor. Therefore, the N+type fifth semiconductor layer73formed on the principal side with respect to the insulation film32corresponds to a collector, the P type diffusion region80formed on the principal side corresponds to a base, and the N+type diffusion region81corresponds to an emitter. The P+type diffusion region82is a base connection diffusion region. Each of the diffusion regions81,82formed on the principal side connects to the electrode44through the interlayer insulation film43, each of which provides the emitter electrode E and the base electrode B, respectively.

The trench35is formed on a rear side of the substrate31under the fifth semiconductor layer73, is disposed perpendicular to the surface, penetrates the insulation film32, and reaches the fifth semiconductor layer73. The sidewall insulation film36is formed on the sidewall of the trench35. The metal layer37as a collector electrode C is embedded in the trench35so as to contact the fifth semiconductor layer73exposed in the trench35.

In the vertical type bipolar transistor196, not only electrons but also holes work as a carrier. Therefore, both of electron current and the hole current flow through the substrate70in the vertical direction. The electron current flows opposite to the hole current, i.e., the electrons in the bipolar transistor196flow in the opposite direction of the holes.

In the bipolar transistor196, the trench35penetrates the insulation film32, and reaches the fifth semiconductor layer73. The fifth semiconductor layer73is exposed in the trench35, so that the metal layer37as the collector contact the fifth semiconductor layer73. Accordingly, in the bipolar transistor196, current path between the emitter and the collector becomes short, so that the ON-state resistance between the emitter and the collector is reduced.

Although the vertical MOS transistors101,111,121,131,141,151,161,162,171,172,181182is used in the semiconductor equipments100,110,120,130,140,150,160,170,180shown inFIGS. 1-11, the vertical type bipolar transistor196can be used in the semiconductor equipments100,110,120,130,140,150,160,170,180.