Method of forming an inverted T shaped channel structure for an inverted T channel field effect transistor device

A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises providing a semiconductor substrate, providing a first layer of a first semiconductor material over the semiconductor substrate, and providing a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. The method further comprises removing a portion of the first layer and a portion of the second layer selectively according to the different rates of removal so as to provide a lateral layer and the vertical channel portion of the inverted T shaped channel structure and removing a portion of the lateral layer so as to provide the horizontal channel portion of the inverted T shaped channel structure.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a National Stage Entry under 37 C.F.R. §371 of International Application No. PCT/IB2007/055365, filed Oct. 3, 2007, entitled “METHOD OF FORMING AN INVERTED T SHAPED CHANNEL STRUCTURE FOR AN INVERTED T CHANNEL FIELD EFFECT TRANSISTOR DEVICE,” which is hereby expressly incorporated by reference in its entirety.

FIELD OF THE DISCLOSURE

This disclosure relates to method of forming an inverted T shaped channel structure for an Inverted T channel Field Effect Transistor (ITFET) device, a method of forming an ITFET device and an ITFET device.

BACKGROUND

New transistor device architectures such as double gate transistor devices have been developed to provide improved short channel control which results in improved current characteristics. A FinFET device is an example of such a double gate device. A simplified cross-section of part of a FinFET device is shown inFIG. 1. A FinFET device is a non-planar device which includes a conducting channel that is formed on the two opposite faces of or is wrapped around a thin silicon ‘fin’14formed on a substrate12which forms the body of the device. A gate18overlies the fin14and a gate dielectric16. The dimensions of the fin and the number of fins in the device determine the effective channel width of the device. The FinFET has some limitations due to the space between the fins being electrically inactive.

An ITFET device has been developed which is a FinFET-type device with lateral extensions at the bottom of the fin so as to provide active thin body devices in the unused regions between the fins which increases the current drive compared to a FinFET device. A simplified cross-section of part of an ITFET device is shown inFIG. 2. The fin24and lateral extensions25form an inverted T shaped channel structure providing horizontal and vertical channels which are controlled by multiple contiguous gate segments: gate28overlies the fin24and a gate dielectric26. Thus, an ITFET device is a multi gate device combining vertical and planar thin body structures within a single device. More details of the ITFET device can be found in US patent application no. 2007/050317 and an article entitled ‘Inverted T channel FET (ITFET)—Fabrication and Characteristics of Vertical-Horizontal, Thin Body, Multi-Gate, Multi-Orientation Devices, ITFET SRAM Bit-cell operation. A Novel Technology for 45 nm and Beyond CMOS’, by L. Mathew et al, Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International 5-7 Dec. 2005, pages 713-716.

In order not to compromise device performance, the inverted T shaped channel structure needs to be patterned reliably and repeatedly which is a challenge particularly since the structure has eight corners. Currently, as discussed in the above two documents, the lateral extensions of the inverted T shaped channel structure of the ITFET device is manufactured by a timed etch. However, generally, a timed etch process (i.e. a main etch process that is performed for a predetermined time) does not offer much control and uniformity in a manufacturing environment. In other words, with the current process, the thickness of the horizontal channel provided by the lateral extensions is hard to control reliably and uniformly.

Thus, there is therefore a need for an improved method of forming an ITFET device.

SUMMARY

The present invention provides a method of forming an inverted T shaped channel structure for an ITFET device, a method of forming an ITFET device and an ITFET device as described in the accompanying claims.

DETAILED DESCRIPTION OF THE DRAWINGS

In the description that follows and inFIGS. 3-8, certain regions are identified as being of a particular material, conductivity and/or type. However, this is merely for convenience of explanation and not intended to be limiting. Those of skill in the art will understand based on the description given herein that various semiconductor materials can be used and that the doping of various regions of the device may be altered in order to obtain different device functions.

A method of forming an inverted T shaped channel structure for an Inverted T channel Field Effect Transistor ITFET device in accordance with an embodiment of the present disclosure will now be described with reference toFIGS. 3-8. Only part of the ITFET device is shown for simplicity.

InFIG. 3, a first layer304of a first semiconductor material is formed over a semiconductor substrate302. In an embodiment, semiconductor substrate302is a silicon oxide substrate (e.g. a SOI substrate) or a substrate with a silicon oxide layer, or other electrical insulator, at the top. The semiconductor substrate302may be formed from other materials. A second layer306of a second semiconductor material is formed over the first layer304and a mask308, such as a hard mask or photoresist, is formed over the second layer306. In an embodiment, mask308is a layer of silicon nitride but could be another material or combination of materials that is effective as an etch mask to the first and second semiconductor materials. Typically, the first layer304has a thickness in the range of 10-150 nm and the second layer306has a thickness in the range of 20-180 nm.

The silicon nitride layer308is patterned and etched to from a nitride cap310(seeFIG. 4). A portion of the first304layer is then removed to provide a lateral layer312and a portion of the second layer306is then removed so as to form the vertical channel portion or active region or fin314of an inverted T shaped channel structure.

The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal or etch rate which is less than the rate of removal or etch rate of the second semiconductor material during the same removal or etch conditions so that portions of the first layer and second layer are removed selectively according to the different rates of removal. The first semiconductor material and second semiconductor material may be selected from the following semiconductor materials: intrinsic semiconductor material, intrinsic semiconductor alloy, doped semiconductor material, doped semiconductor alloy and thus includes the following example semiconductor materials: silicon; silicon germanium alloy; silicon carbon alloy; silicon, germanium and carbon alloy; doped silicon; doped silicon germanium alloy; doped silicon carbon alloy; and doped silicon, germanium and carbon alloy. The doped semiconductor materials may be doped in situ or the dopants may be introduced for example by implantation. In an embodiment, the first and second semiconductor materials are monocrystalline but may instead be polycrystalline or amorphous.

Thus, by selecting the appropriate semiconductor materials for the first304and second306layers according to their different etch rates during the etch process, the lateral layer312and the vertical channel portion314of the inverted T shaped channel structure can be formed. Dry etching or wet etching processes may be used to remove the portions of the first304and second306layers.

In one example, the first semiconductor material is silicon germanium alloy and the second semiconductor material is silicon. The first SiGe layer304is grown epitaxially on the substrate302and the second Si layer306is grown epitaxially on the first SiGe layer304. One of the following etchants is then used to etch selectively the first304and second306layers to form the lateral layer312and the vertical channel portion314: a combination of carbon tetrafluoride CF4, oxygen O2, Argon Ar and nitrogen N2. For example, a reactive ion plasma etch may be used to selectively etch the first SiGe layer304and the second Si layer306with gases: CF4, O2, Ar. The following combination of gases may also be used in an etch process: CF4/CH2F2/N2/O2/Ar.

The etch rate of the SiGe of the first layer304depends on the concentration of germanium in the SiGe alloy: the higher the concentration of germanium, the greater the etch rate. When the concentration of silicon to germanium in the first layer304is in the ratio 8:2, the Si etch rate is 250 nm/min and a selectivity of over 100 can be readily achieved. This means that the second Si layer306is etched at a greater rate than the first SiGe layer304.

In another example, the first semiconductor material is silicon Si and the second semiconductor material is silicon germanium SiGe alloy. The first Si layer304is grown epitaxially on the substrate302and the second SiGe layer306is grown epitaxially on the first Si layer304. One of the following etchants is then used to etch selectively the first304and second306layers to form the lateral layer312and the vertical channel portion314: nitric acid HNO3, and a combination of hydrogen peroxide H2O2, hydrogen fluoride HF and acetic acid CH3COOH. For example, a wet etch using a solution containing HNO3, H2O2, and HF may be used to selectively etch the first Si layer304and second SiGe layer306. A dry etch, for example, using the plasma etch processes described above may also be used.

The etch rate of the SiGe of the second layer306depends on the concentration of germanium in the SiGe alloy: the higher the concentration of germanium, the greater the etch rate. When the concentration of silicon to germanium in the second layer306is in the ratio 9:1, the selectivity to the SiGe alloy compared to Si is about 25. When the concentration of silicon to germanium in the second layer306is in the ratio 71:39, the selectivity to the SiGe alloy compared to Si is about 60. For both example concentrations of Ge, the second layer306is etched at a greater rate than the first layer304(but at a greater rate for the second example).

In principle, the selectivity could be maximised and hence the etch rate of the SiGe alloy increased by having the Ge concentration in the SiGe alloy greater than 50%. However, higher Ge concentrations (for example over 60%) may induce high mechanical stresses which could render the device inoperable because of the high level of defects or delamination effects. It will be appreciated that the range of Ge concentration is slightly different for the case when the first layer304is Si and the second layer306is SiGe compared to the case when the first layer304is SiGe and the second layer306is Si and depends on the etch chemistry.

In the examples described above, the first304and second306layers are grown epitaxially on the substrate302, which may be a SOI wafer provided by a wafer vendor, such as SOITEC. Alternatively, the wafer vendor may provide an SOI wafer (substrate302) with crystalline Si first layer304on the oxide layer302or an SOI wafer with crystalline SiGe first layer304on the oxide layer302. The second layer306would then be grown epitaxially on the pre-existing first layer304provided by the wafer vendor.

In another example, the first semiconductor material comprises at least two semiconductor materials and the second semiconductor material comprise the same at least two semiconductor materials but in different concentrations to that of the first semiconductor material. For example, the first semiconductor material is silicon germanium alloy with 10% Ge concentration and the second semiconductor material is silicon germanium alloy with 40% Ge concentration and the solution HNO3is used in the etch process. In another example, the first semiconductor material is silicon germanium alloy with 30% Ge concentration and the second semiconductor material is silicon germanium alloy with 10% Ge concentration and the solution CF4/O2/N2is used in the etch process.

Other examples include: the first semiconductor material is Si and the second semiconductor material is any one of SiC, Si/Ge/C, doped SiC, doped Si/Ge/C; the first semiconductor material is SiGe and the second semiconductor material is any one of SiC, Si/Ge/C, doped SiC, doped Si/Ge/C; the first semiconductor material is SiC and the second semiconductor material is any one of SiC (with different concentrations of C to the first semiconductor material), Si/Ge/C, doped SiC, doped Si/Ge/C; the first semiconductor material is Si/Ge/C and the second semiconductor material is any one of SiC, Si/Ge/C (with different concentrations of C and Ge to the first semiconductor material), doped SiC, doped Si/Ge/C; or any other suitable combinations of first and second semiconductor materials. The appropriate etchants (wet or dry) are selected in order to achieve selective etching of the first and second semiconductor materials.

The subsequent process steps follow the conventional method of forming an ITFET.

Referring now toFIG. 5, a liner318is then formed over lateral layer312, nitride cap310and vertical channel portion314. Liner318may be silicon oxide that is thermally grown or deposited. Sidewall spacer320is then formed on the sidewalls of vertical channel portion314. In a preferred embodiment, sidewall spacer320is formed of silicon nitride but could be formed of another material that can function as an etch mask.

A portion of the lateral layer312is then removed using sidewall spacer320as a mask and an etching process so as to form horizontal channel portion or horizontal active region322of the ITFET device, as shown inFIG. 6. Thus, the width of the horizontal channel portion322is determined by the width of the sidewall spacer320. Sidewall spacer320, liner318and nitride cap310are then removed. A gate dielectric324is formed over the horizontal channel portion322and vertical channel portion314and then a gate326is formed over the dielectric gate324. In an embodiment, the gate dielectric324is formed by a high temperature growth of silicon oxide. Other dielectric materials, such as metal oxides HfO2or ZrO2, or any suitable high-k dielectric material, may alternatively be used. The gate326may be formed of a conductive material such as polysilicon or polysilicon on metal. The source and drain regions328are formed in conventional fashion as for a FinFET device.

FIG. 7is a top perspective view of part of the ITFET device ofFIG. 6(but not showing the gate dielectric324separately) and shows source/drain regions328on either side of the gate326and formed over the semiconductor substrate302. In the example shown inFIG. 7, the source/drain regions328are formed over part of the lateral layer312.

In an ITFET device comprising a plurality of ‘fins’ or inverted T shaped channel structures, each of the plurality of ‘fins’ are formed in the same ways as described above.

The inverted T shaped channel structure of an ITFET device has eight corners. When the corners are pointed or not rounded, premature inversion can take place in the convex corner regions with the result that different parts of the ITFET device are switched on at different gate voltages. Acute concave corners are likely to suffer from deferred onset of inversion. In order to avoid premature or deferred inversion at the corners and to provide the same inversion properties along the length of the ITFET device, it is desirable to have rounded active corners on the vertical channel portion314and the horizontal channel portion322of the inverted T shaped channel structure.

In an embodiment of the disclosure, one of the first and second semiconductor materials is selected to be an intrinsic semiconductor alloy comprising at least a first semiconductor and a second semiconductor, with the concentration of the second semiconductor increasing as a distance from the junction between the first304and second306layers increases to a predetermined distance after which the concentration of the second semiconductor is constant. By varying the concentration of the second semiconductor as a function of distance from the junction between the first304and second306layers, desired and relatively precise corner rounding can be engineered.

FIG. 8shows the corner rounding at342in an example where the first layer304is Si and the second layer306is SiGe. The graph inFIG. 8shows how the concentration of Ge in the second layer306(which forms the vertical channel portion314) varies with distance z from the junction340between the first304and second306layers. The Ge concentration in the second semiconductor material is varied when the second SiGe layer306is formed by epitaxial growth in accordance with well known processes.

More precise corner rounding can be achieved due to the fact that the rate of removal of the second SiGe layer306is determined by the local concentration of Ge and the corner rounding is achieved by the increasing Ge concentration as the distance from the Si/SiGe junction increases until a predetermined distance is reached at344where the Ge concentration is kept constant for the upper part of the vertical channel portion314. In this way a more precise corner rounding can be engineered. The curvature of radius of the rounded convex and concave corners can be anywhere between 2-15 nm. The distance from the Si/SiGe junction to344may be in the range 3-30 nm.

In an embodiment where the first semiconductor layer304is a SiGe layer and the second semiconductor layer306is a Si layer, the concentration of Ge in the first SiGe semiconductor layer304decreases from the bottom of the SiGe layer304towards the top of the SiGe layer304adjacent the junction with the second Si layer306.

Typically, the percentage of Ge used in the SiGe material is 5-50%.

Since the selectivity of the selective removal of portions of the first304and second306layers can be controlled by selecting the appropriate first and second semiconductor materials for the first304and second306layers, the thickness316of the lateral layer312can be controlled more precisely than a timed etch process. Since the horizontal channel portion of the ITFET device is formed from the lateral layer312, the thickness of the horizontal channel portion or horizontal active area of the ITFET device can therefore be controlled more precisely (e.g. within a few nanometers) than a timed etch process. Typically, the horizontal channel portion of the ITFET has a thickness in the range of 2-50 nm.

By having a graded concentration of a semiconductor alloy which forms one of the first and second layers which is graded away from the junction between the first and second layers, well controlled rounding of the active corners of the inverted T shaped channel structure can be provided. As discussed above, corner rounding avoids premature or deferred inversion in the corner regions. Since well controlled rounding of the corners can be obtained by the above described graded method in accordance with an embodiment of the invention, the threshold voltage Vt can be selected according to the degree of rounding and is kept the same in all parts of the ITFET device so that proper operation of the ITFET device can be achieved.

Thus, in summary, the method in accordance with the present disclosure provides a highly robust and manufacturable method of producing the inverted T channel shaped structure of an ITFET device with the benefit of mobility enhancement. In an embodiment which provides for corner rounding, the method in accordance with the embodiment provides convenient corner rounding and convenient adjusting of the threshold voltage.