Shared quiet line flip-flop

A quiet line flip-flop is connected to a plurality of lines (12, 14) for reducing the effect of capacitive coupling between the lines (12, 14) and a line (18). A node (26) is precharged by a transistor (34) to render conductive transistors (30, 32) which connect the respective lines (12, 14) to a ground node (24). When either of the lines (12, 14) is forced to a voltage above a preset voltage the corresponding transistors (22, 28) are respectively rendered conductive to discharge the node (26) which causes the transistors (30, 32) to be rendered nonconductive thereby disconnecting the lines (12, 14) from the ground node (24).

TECHNICAL FIELD 
The present invention pertains to semiconductor integrated circuits and 
more particularly to a circuit for reducing the effect of capacitive 
coupling between bit lines and unselected row lines in a memory circuit. 
BACKGROUND ART 
In a semiconductor memory circuit each of the memory cells is accessed by 
applying a high voltage to a row line that drives an access transistor for 
the addressed memory cell. The row line is activated by a decoder circuit 
which is driven in response to a multi-bit memory address signal. The row 
line selected by the address is driven to a high level by the decoder 
circuit. Heretofore, it has been a frequent practice to permit the row 
lines to float at times when another row line is selected by the decoder. 
But in memory circuits in which multiple bit lines can go high during an 
active cycle, the capacitive coupling between these bit lines and the 
floating row lines causes these floating row lines to be capacitively 
charged positive. This positive voltage can turn on the access transistors 
for the memory cells connected to the floating row lines. This inadvert 
activation of memory cells can destroy the data state stored therein. 
Thus, when these memory cells are later accessed, erroneous data can be 
read out. 
In view of this problem, there exists a need for a circuit which holds 
nonselected row lines at a low voltage state to reduce the effect of 
capacitive coupling but also permits a selected row line to be charged 
without drawing a substantial amount of current from the row driver 
transistor. Further this circuit must have a topological configuration 
adaptable for integration in a very dense integrated memory circuit. 
DISCLOSURE OF THE INVENTION 
A quiet line flip-flop for a semiconductor memory is provided for reducing 
capacitively coupled noise on a group of row lines. The quiet line circuit 
includes means for precharging a first node to a first state in response 
to a precharge signal where the first node corresponds to the group of row 
lines. Further circuit means are included for providing a conductive path 
between each of the row lines and a low voltage node when the first node 
is charged to a first state. Further circuitry is provided for opening the 
conductive path between the lines and the low voltage node when at least 
one of the lines is forced to a voltage above a preset voltage.

DETAILED DESCRIPTION OF THE INVENTION 
A representative embodiment of the circuit of the present invention is 
illustrated in the FIGURE. A quiet line flip-flop 10 is used in 
conjunction with a group of row lines 12 and 14 within a semiconductor 
memory. Row line 12 receives a driver signal RD1 which charges the row 
line to a high state thereby turning on a memory cell 16 which transmits 
and receives data through a bit line 18. The row line 14 likewise receives 
a row driver signal RD2 which activates a memory cell 20 for transferring 
data states through the bit line 18. The row driver signals RD1 and RD2 
are generated in response to a memory address as described in co-pending 
patent application Ser. No. 231,240, filed June 2, 1980 to R. Proebsting. 
The quiet line flip-flop 10 includes a discharge transistor 22 which has 
the gate terminal thereof connected to the row line 12, the source 
terminal thereof connected to a common ground node 24 and the drain 
terminal thereof connected to a precharge node 26. 
The gate terminal of a discharge transistor 28 is connected to row line 14, 
the source terminal thereof is connected to ground and the drain terminal 
thereof is connected to node 26. 
A row hold down transistor 30 has the drain terminal thereof connected to 
the row line 12 and the source terminal thereof connected to the common 
ground node 24. The gate terminal of row hold down transistor 30 is 
connected to node 26. A second row hold down transistor 32 has the drain 
terminal thereof connected to row line 14, the source terminal thereof 
connected to the common ground node 24 and the gate terminal thereof also 
connected to node 26. 
A precharge transistor 34 is connected to receive a precharge signal P at 
the gate terminal thereof, the source terminal thereof is connected to 
node 26 and the drain terminal thereof connected to a power terminal 36 
which receives the supply voltage V.sub.cc. 
Stray capacitive coupling between the bit line 18 and the row line 12 is 
indicated by capacitor 40. Stray capacitive coupling between the bit line 
18 and the row line 14 is indicated by capacitor 42. 
In a further embodiment of the present invention the precharge signal P is 
replaced by a connection 46 from the gate terminal of transistor 34 to the 
power terminal 36 which receives the supply voltage V.sub.cc. When the 
connection 46 is in place there is effectively provided a resistive path 
between V.sub.cc and node 26. When transistors 22 and 28 are turned off, 
node 26 is charged through transistor 34 and transistors 30 and 32 are 
turned on. But when either of transistors 22 or 28 is turned on, the 
voltage on node 26 is pulled sufficiently low to turn off transistors 30 
and 32. In this condition there will be a current flow path through 
transistor 34 and the one of transistors 22 and 28 which is turned on. 
When the voltage on the row line holding transistor 22 or 28 on is 
removed, both of transistors 22 and 28 are rendered nonconductive and node 
26 is again charged through transistor 34 to turn on transistors 30 and 
32. 
Operation of the circuit of the present invention is now described in 
reference to the FIGURE. The row lines 12 and 14 are two row lines within 
a large array of row lines. When bit lines are charged or discharged a 
voltage can be capacitively coupled into the row lines 12 and 14 by the 
stray capacitance indicated by capacitors 40 and 42. This capacitively 
coupled voltage can inadvertently turn on the memory cells 16 and 20 and 
destroy the data states stored therein. In accordance with the present 
invention, the circuit 10 is precharged by signal P before the start of 
each memory cycle. The signal P goes to a high voltage state which drives 
transistor 34 conductive and precharges node 26 to a high voltage level. 
The high voltage level on node 26 turns on transistors 30 and 32 thereby 
connecting the row lines 12 and 14 to the ground node 24. Thus, the row 
lines 12 and 14 are held affirmatively to ground and any charge induced on 
the row lines is discharged to the ground node. 
But in order for the memory circuit to function as desired, the selected 
row line must be charged in order to activate the corresponding memory 
cells. The quiet line circuit 10 thus must be deactivated when it is 
desired to charge one of the row lines 12 or 14. The transistors 30 and 32 
are fabricated to provide a low enough impedance to limit the voltage on 
the row lines due to capacitive coupling, but to have a high enough 
impedance to be overcome by the row driver signals. The signals RD1 and 
RD2 drive the row lines with a typically lower impedance than that of the 
transistors 30 and 32. 
When the signal RD1 forces row line 12 to a voltage above the threshold 
level of transistor 22, the discharge transistor 22 will be rendered 
conductive thereby discharging node 26 which in turn deactivates 
transistors 30 and 32. When transistors 30 and 32 are turned off, the 
conductive path between the row lines and ground is opened. A similar 
operation occurs with transistor 28 when row driver signal RD2 forces the 
voltage on row line 14 above the threshold of transistor 28. Thus, when 
either one of the row lines 12 and 14 is activated, the node 26 is 
discharged and the hold down transistors 30 and 32 are turned off. 
Prior quiet line flip-flops have been provided in semiconductor memories, 
but such circuits have included individual precharge nodes for each of the 
row lines. The use of precharge nodes for each row line often causes the 
quiet line flip-flop to become the limiting factor in how closely spaced 
the row lines can be configured. If the spacing of the row lines is 
increased, this results in a substantial increase in circuit area. The 
circuit of the present invention provides a quiet line circuit for a 
plurality of closely spaced row lines and can be implemented such that the 
overall memory array area is reduced. A reduction in the area used in an 
integrated circuit offers many advantages including greater yield and 
lower production costs. 
The quiet line flip-flop 10 shown in the FIGURE is disabled when the 
voltage level on either of the row lines reaches the threshold voltage of 
its discharge transistor. However, the voltage level at which the node 26 
is discharged can be preset to any desired value by the use of well known 
circuit techniques. 
The circuit of the present invention can be utilized in any application 
where it is desired to hold a plurality of lines at ground to eliminate 
undesired electrical noise. But when it is desired to drive one of the 
lines to a high voltage state, the circuit is deactivated to permit such 
action. 
Although one embodiment of the invention has been illustrated in the 
accompanying drawing and described in the foregoing Detailed Description, 
it will be understood that the invention is not limited to the embodiment 
disclosed, but is capable of numerous rearrangements, modifications and 
substitutions without departing from the scope of the invention.