Methods for post offset spacer clean for improved selective epitaxy silicon growth

A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region.

CROSS-REFERENCE TO RELATED APPLICATION(S)

Related subject matter is found in a copending U.S. patent application, application Ser. No. 10/969,771, filed Oct. 20, 2004, entitled “Method of cleaning a surface of a semiconductor substrate”, and having at least one inventor in common with the present application.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to a semiconductor manufacturing process, and more particularly to methods for cleaning devices during a manufacturing process.

DESCRIPTION OF THE RELATED ART

CMOS manufacturing processes through formation of raised source drain regions via selective epitaxial growth (SEG) typically proceed by deposition, patterning and etch of a gate structure, followed by deposition and blanket etch toward formation of a single set or several sets of spacers adjacent to the gate structure sidewalls. These spacers are generally referred to as offset spacers as they serve to offset the distance from the gate sidewalls to the source/drain extension regions during ion implantation of the source/drain extension regions.

Formation of offset spacers is generally by anisotropic etching, which creates surface contamination, near-surface contamination, and damage to the source/drain regions. Current offset spacer formation processes necessitate additional, post offset spacer formation cleaning processes to remove the surface contaminants and surface damage prior to additional processing and prior to selective epitaxial growth. Typical post-offset spacer cleaning utilizes a plasma clean in an oxidizing ambient atmosphere, or a hydrofluoric acid (HF) cleaning process. An HF cleaning cannot be employed when the offset spacers are an oxide, as this would result in removal of the offset spacer. Because the typical post-offset spacer clean occurs in an oxidizing ambient atmosphere, further cleaning must be conducted prior to selective epitaxial growth, adding to the manufacturing cycle time, and the cumulative damage effects during device fabrication.

Therefore a method that overcomes these problems would be useful.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

The present disclosure provides a method for manufacturing a semiconductor device utilizing a cleaning process following offset spacer formation which results in a surface suitable for selective epitaxial growth (SEG) and does not require an additional post-offset spacer clean. In addition to the time- and cost-savings provided by the elimination of an additional post-offset spacer cleaning, the method disclosed results in lower selective epitaxy temperature, which has been correlated with higher device drive current, thus increasing operating speeds and ranges.

The cleaning processes detailed in the present disclosure serve to clean the surface of a semiconductor device by removing contamination such as carbonaceous residue, sub-surface oxygen, and other impurities. These contaminants hinder the SEG process. The cleaning processes disclosed herein allow for a lower temperature H2bake because, following the cleaning processes, the semiconductor devices' surface contamination is lower, thus a higher temperature H2bake is no longer required. Higher H2bake temperatures should be avoided, as dopant diffusion and/or dopant deactivation may occur within doped components of the device, e.g., source/drain extensions or polysilicon gates.

At the stage of manufacture illustrated inFIG. 1, a cross-sectional view of a portion100of a semiconductor device, a conductive gate portion15has been formed over a gate oxide12and overlying a semiconductor substrate10. Semiconductor substrate10can be a mono-crystalline silicon substrate, or can also be other materials, e.g., silicon-on-insulator, silicon on sapphire, gallium arsenide, or the like. Conductive gate portion15is preferably poly-crystalline or amorphous silicon having a width ranging from 350–500 Angstroms, and a height ranging from 900–1200 Angstroms. Gate oxide12typically comprises a thermal silicon oxide ranging in thickness from 10–25 Angstroms.

Following blanket deposition of spacer material and etch, offset spacers are formed immediately adjacent to conductive gate portion15sidewalls. In an embodiment, a single layer spacer material such as a nitride is utilized to form a single material layer offset spacer14. Alternately, more than one deposition and etch may be employed to create a dual material layer offset spacer17, as illustrated inFIG. 2. The example illustration ofFIG. 2shows a first material layer13, and a second material layer16. The resulting combined layers13,16, or layer stack, together comprise the offset spacer17. In an embodiment, spacer material layer13is an oxide, and spacer material16is a nitride, although this order may be reversed, or the two layers may be comprised of the same material. It should be noted that although two layers of material are illustrated as comprising offset spacer17, more than two layers may be utilized to form the offset spacer17. Adjacent to either side of the gate structures ofFIGS. 1 and 2are regions where a transistor source and drain are to be formed. These regions are referred to generally as source/drain region. In one embodiment, offset spacers such as14and17are utilized to demarcate a source/drain extension implantation region.

Following formation of single or multiple layer offset spacers14or17, the source/drain portions of the substrate10of portion100are exposed to a cleaning process comprising hydrofluoric acid, ammonium hydroxide, hydrogen peroxide, and deionized water mixture. An epitaxial layer such as epitaxial layer28(FIG. 12) will be formed overlying the source/drain regions after the source/drain regions have been exposed to the cleaning process. In an embodiment, the source/drain extension regions undergo dopant implantation prior to formation of the epitaxial layer. In a further embodiment, the source/drain extension regions undergo dopant implantation following the step of formation of the epitaxial layer. In another embodiment, the source/drain regions of the substrate10are implanted with a dopant prior to exposing portion100to the cleaning process disclosed herein.

FIG. 3illustrates portion100undergoing exposure to a cleaning process as embodied herein. The cleaning process comprises a first pre-rinse with deionized water, followed by an oxide etch6utilizing an aqueous solution of deionized water and hydrofluoric acid (HF or hydrogen fluoride in water) aqueous solution of approximately 30:1 (volumetric ratio) at 21 degrees Celsius, for a time period ranging from between 50–60 seconds. The weight percentage of HF recommended for the HF aqueous solution is 49% in a balance of deionized water (H2O). Bulk HF aqueous solution can be purchased from various chemical suppliers in the HF weight percent range of 10% to 49%. In semiconductor fabrication facilities, this aqueous HF aqueous solution is typically diluted in the range 10:1 to 200:1. A 10:1 HF is 1 part aqueous HF (at 49% weight percent) and 10 parts H2O. It will be appreciated that the etch rate of the HF aqueous solution is substantially linear with respect to both the concentration of the HF aqueous solution and the etch time. Therefore, various combinations of HF concentrations and etch times can be used to accomplish the oxide etch. Additionally, the temperature may vary.

After the HF etch, an overflow rinse utilizing deionized water is performed for a period ranging from approximately 120 to 600 seconds with a typical rinse being about 400 seconds. The cleaning process of portion100results in etching away of the surface contamination/debris located on substrate10resulting from offset spacer formation and/or dopant implantation. The upper semiconductor surface, i.e. silicon surface, of substrate10is also slightly etched, for example, from one to several mono layers of silicon, during the HF etch6, as illustrated byFIG. 4.

FIG. 4illustrates portion100following the HF etch6(FIG. 3). It should be noted that the amount of material removed during the HF etch6is dependent upon the type of material being removed. For example, when native oxide is present, the HF etch6will remove approximately 20 to 30 Angstroms of oxide. If a deposited oxide layer is present in addition to a native oxide, an over-etch of approximately 30% is generally desirable. For example, if removal of 100 Angstroms of a chemical vapor deposition (CVD) oxide is desired, the HF etch6could be employed to remove approximately 120 to 130 Angstroms oxide removal. This latter example would be applicable in applications where a liner oxide of approximately 100 Angstroms thickness is employed between the gate25and the nitride spacer14.

FIGS. 5 through 7illustrate the next steps in the cleaning process of portion100. A second pre-rinse with deionized water of approximately 30 seconds duration precedes the performance of a Standard Clean-1 (SC-1), a quick dry rinse (QDR), and a Standard Clean-2 (SC-2). The SC-1 and SC-2 components of the cleaning process are denoted by item number7inFIG. 5. The SC-1 and SC-2 components7are followed by a second QDR (not illustrated), and an HF: H2O etch (item8,FIG. 7), a third rinse, and an isopropyl alcohol (IPA) dry. The amount of material removed by the SC-1 and SC-2 components etch ranges from approximately one monolayer of silicon to about 10 to 100 Angstroms.

In an embodiment, the SC-1 utilizes an aqueous solution of ammonium hydroxide: hydrogen peroxide: deionized water at a ratio of approximately 1:1–4:6–40, at a temperature of approximately 60 degrees Celsius for approximately 72 minutes, to etch approximately 100 Angstroms of silicon. Synonyms for ammonium hydroxide (NH4OH) include ammonia solution (typically contains between 12% and 44% ammonia before dilution), dilute ammonia, or concentrated ammonia. A first quick dry rinse is conducted for approximately 3 minutes. In an embodiment, the SC-2 utilizes a solution of hydrochloric acid: hydrogen peroxide: deionized water at an initial ratio of approximately 1:1:50 at a temperature of approximately 60 degrees for about 5 minutes. A second quick dry rinse is then conducted. Synonyms for hydrochloric acid (HCl) are hydrogen chloride, anhydrous hydrogen chloride, aqueous hydrogen chloride, chlorohydric acid, spirit of salts, and muriatic acid.

In a particular embodiment, the SC-1 utilizes a solution of ammonium hydroxide: hydrogen peroxide: deionized water at a ratio of approximately 1:4:20 at a temperature ranging of approximately 60 degrees Celsius for approximately 72 minutes. The SC-1 is the step in the clean sequence that etches the silicon. This occurs because the H2O2(the oxidizer) becomes depleted in the solution with increasing time and increasing temperature. The methods of the present disclosure allow the initial concentration of hydrogen peroxide to be depleted to facilitate etching of the upper-most semiconductor portion. Depletion of the H2O2is greatly enhanced when the solution temperature rises above 80 degrees Celsius, which can lead to an etch that is difficult to control if not carefully monitored. The temperature range of the SC-1 is expected to be approximately 55 to 85 degrees Celsius, with the etch occurring in a shorter period of time at higher temperatures than at lower temperatures. It is expected that the SC-1 etching will be better controlled at temperatures in the range of 55–80 degrees Celsius and better still at temperatures in the range of 55–75 degrees Celsius. Generally, it is expected that the substrate will be exposed to the SC-1 etch process for longer that 60 minutes. When the oxidizer stops protecting the silicon surface, the ammonium hydroxide (NH4OH) starts to etch the silicon. Thus, a small amount of silicon can be etched in a controlled manner. The SC-1 can be performed in a re-usable bath where the solution is re-circulated and heated to maintain the desired temperature.

The mechanism of silicon and SiO2etching by a NH4OH/H2O2solution occurs when the solution is allowed to be depleted of H2O2. An alkaline solution, such as NH4OH4 in our example, will attack silicon by water molecules, according to the reaction:
Si+2H2O+2OH−→Si(OH)2(O−)2+2H2↑
A passivation layer formed by the H2O2prevents this attack by the NH4OH. H2O2decomposes in the course to form O2and H2O.
H2O2→H2O+½O2
When the concentration of H2O2is below 3×10−3M, then silicon will begin to etch, because of the absence of the inhibition layer.

As indicated in the above equations, heat is given off as the H2O2is depleted. If a bath is used that is not recharged with fresh solution all H2O2will be depleted, thereby no longer releasing heat. Therefore, the temperature can be monitored on the low end to indicate when the solution should be refreshed, while the temperature on the high end is monitored to prevent unusually rapid decomposition of the H2O2, which can lead to a process that is difficult to control.

The first quick dry rinse is conducted for approximately 3 minutes. The subsequent SC-2 utilizes a solution of hydrochloric acid: hydrogen peroxide: deionized water at a ratio of approximately 1:1:50 at a temperature of approximately 60 degrees for about 5 minutes. A quick dry rinse with deionized water, followed by an IPA dry process, is performed following the SC-2.

The IPA dry process is an industry standard whereby the semiconductor wafers are lifted from the water rinse tank into a heated IPA vapor at 82 degrees Celsius. The IPA vapor is generated in a separate chamber with 100% N2bubbled through 100% IPA (heated to 82 degrees Celsius). The IPA condenses on the wafer, and the solution drips off the bottom of the wafer. The IPA vapor concentration is slowly diluted to 100% N2before the wafers are removed from the rinsing/drying tank.

FIG. 6illustrates the results of the SC-1, SC-2 etch upon portion100. Substrate10has been further recessed (etched) as a result of the cleaning process. Portion100then undergoes an HF: H2O etch8as shown inFIG. 7. The H2O:HF etch8is conducted at an aqueous solution ratio of 200:1 for about 65 seconds, which typically results in approximately 30 Angstroms of oxide removal. The HF: H2O etch8is followed by a rinse with deionized water for approximately 10 minutes duration. The deionized water rinse is followed by an IPA dry as described in the preceding paragraph.FIG. 8illustrates portion100following the HF: H2O etch8. The source/drain regions (item30,FIG. 9) of substrate10are ready for ion implantation or selective epitaxial growth.

As seen inFIGS. 9 through 12, another embodiment of the present disclosure for a method of manufacturing a semiconductor device is presented. At the stage of manufacture illustrated inFIG. 9, a portion200of the semiconductor device has been formed comprising a gate structure25overlying a semiconductor substrate20, an offset spacer27immediately adjacent the gate structure25, and a source/drain extension region30.

The gate structure25includes a conductive portion25and an insulative portion22. Conductive portion25is preferably poly-crystalline or amorphous silicon having a width ranging from 250 to 10,000 Angstroms, and a height ranging from 500 to 2000 Angstroms. Insulative portion22, the gate oxide, consists of a thermal silicon oxide ranging in thickness from 5 to 30 Angstroms. Semiconductor substrate20can be a mono-crystalline silicon substrate, or can also be other materials, e.g., silicon-on-insulator, silicon on sapphire, gallium arsenide, or the like.

The offset spacer27illustrated inFIGS. 9 through 12is a dual material layer offset spacer27. The example illustrated inFIG. 9shows a first material layer23, and a second material layer26. The resulting multiple layers23,26together comprise the offset spacer27. In an embodiment, spacer material layer23is an oxide, and spacer material26is a nitride, although this order may be reversed, or the two layers may be comprised of the same material. It should be noted that although two layers of material are illustrated as comprising offset spacer27, fewer or more than two layers may be utilized to form the offset spacer27. Offset spacers27serve to define the source/drain extension implantation regions30.

Portion200will undergo various steps in a cleaning process which will result in removal of portions of the surface of semiconductor substrate20, as well as portions of the surface of conductive gate structure25. InFIG. 9, portion200is undergoing an SC-1 cleaning process9, which will be followed by an SC-2 cleaning process (not illustrated), and an oxide etch utilizing a solution of deionized water and hydrofluoric acid (HF) (FIG. 10). After the final step of the cleaning process, an epitaxial layer (FIG. 12) will be formed overlying the source/drain extension implantation regions30.

In a particular embodiment, the SC-1 process9comprises a pre-rinse with deionized water of approximately 30 seconds duration. The pre-rinse is followed by a SC-1 solution9at a ratio of approximately 1:1–4:6–40, which includes the subranges of 0.25:1:5, 0.5:1:5, 1:1:5, 1:1:6, 1:4:20, and 1:1:40, ammonium hydroxide: hydrogen peroxide: deionized water at a temperature of approximately 60 degrees Celsius for approximately 5 minutes. A quick dry rinse (QDR) is then performed for approximately 3 minutes.

Following the SC-1 cleaning process, an SC-2 cleaning process is performed. In an embodiment, the SC-2 cleaning process includes utilizing an aqueous solution of hydrochloric acid: hydrogen peroxide: deionized water at a ratio of approximately 1:1:50 at a temperature of approximately 60 degrees Celsius for approximately 5 minutes. A QDR is then performed, and portion200is ready for the third cleaning, as illustrated inFIG. 10. The weight percent composition of the hydrochloric acid: hydrogen peroxide: deionized water is 29% (weight percent) hydrochloric acid and 30% (weight percent) hydrogen peroxide in a balance of deionized water.

After the SC-1 and SC-2, a third cleaning process comprising an approximate 30 second pre-rinse, an oxide etch, an overflow rinse and an IP dry is performed, as shown inFIG. 10. The oxide etch is accomplished utilizing a solution11of deionized water and hydrofluoric acid at a ratio of approximately 200:1 for a time period ranging from between 450–650 seconds. Following the HF etch, an overflow rinse is performed for approximately 10 minutes. A final isopropyl alcohol (IPA) dry is then performed. Approximately 120–140 Angstroms of the surface of substrate20is removed in this process, as seen inFIG. 11. Portion200is ready to undergo selective epitaxial growth.

FIG. 12illustrates the portion200ofFIG. 11following SEG formation. The SEG process has formed an epitaxial layer28overlying the substrate20, as well as an SEG layer29over the surface of the gate structure25. The etching process discussed with reference toFIGS. 9–11etches the upper surface of the gate structure25in addition to the surface of the substrate20. This produces a slightly recessed gate structure25surface, which, when SEG is conducted, results in the “mushroom-shaped” cap29atop the gate structure25. This mushroom-shaped cap29is due, in part, to being confined by the offset spacers27during the SEG process.

FIG. 13illustrates a cross-sectional view of a portion400of a semiconductor device manufactured according to an embodiment of the present disclosure.FIG. 13is a simplified diagram that does not show all of the features, e.g., silicide regions, of portion400in order to keep the illustration from being cluttered. Illustrated features include interconnects441and442connected to vias/contacts443and444within interconnect dielectric region440.

A passivation layer450has been formed overlying portion400. The conductive gate structure425may include a gate stack comprising a dielectric layer (not shown) and/or an epitaxial layer426. InFIG. 13, source drain regions428in the substrate420, along with the epitaxial layer430are shown integrated into a transistor. The offset spacer shown inFIG. 13is comprised of two material layers, layer423and layer426. In other embodiments, the offset spacers can be a single material layer.

The above-described cleaning process has been found to facilitate formation of an epitaxial layer on a semiconductor surface, specifically silicon. Because various etch processes can etch N- and P-type regions at different rates, it can be useful to amorphize an upper-most surface of the source/drain regions prior to the above-described clean to reduce any preferential etch differences between substrate regions of differing dopant types.

For example, the above-described clean process can etch the N-type silicon preferentially, as compared to the P-type silicon, resulting in a quality difference of the SEG between the N and P regions after SEG processing. Etch rate differences between N- and P-type regions can allow for contaminates to remain in the lesser-etched region. For example, an etch process that does not etch P-type regions at the same rate as N-type regions can result in P-regions maintaining embedded carbon that is incorporated from previous process steps. Without appropriate etching of silicon in the P-type regions during the clean, the carbon will remain, and the SEG will grow inconsistently. A high bake temperature of 900° C. can be used to overcome this growth issue on P areas, however, as stated previously, high bake temperatures can be detrimental to the device in that it causes diffusion and deactivation of the dopants. Amorphizing the source/drain regions can reduce etch differences associated with the above-described cleaning process as well as other processes that are used to etch doped substrate regions, thereby improving the quality of both the N and P regions.

It has been hypothesized by the inventors that the etch bias between the N and P areas arises from the electronegativity difference (also called Electro-Motive Force EMF), between the N and P areas. This electrochemical behavior of silicon in aqueous ammonia solutions has been studied mostly with an emphasis on anodic dissolution. Selective etching of N-type and P-type silicon has been demonstrated, and the electrode potential measured with two electrolyte cells: the first containing the silicon substrate, and the second cell containing a reference electrode of Ag/AgCl. Many factors can influence which substrate is etched (dissolution reaction), and which is not etched (passivation reaction). N-type silicon will provide a supply of electrons to the reaction at the surface, and P-type silicon will provide a supply of holes. In one approach, the EMF is the band offset between the Fermi levels in the N-type and P-type silicon, which is equivalent to approximately leV. The N-type silicon will act as the anode, while the P-type silicon will act as the cathode in this RedOx reaction. When the substrates are immersed in a chemical solution to allow charge transfer in the solution, complex chemical reactions occur.

As a result, a chemical process is occurring along a thin boundary layer in the solution directly in contact with the silicon surface. Along this boundary, the aqueous ammonia oxidizes the silicon to form SiO2. The presence of dopants changes the resistivity of the silicon, thus, higher active dopant concentrations increase the current density, which is proportional to the oxidation and dissolution rate of the silicon.

The higher the doping concentration, the greater the dissolution rate. For P+ silicon, if the doping concentration is not high enough, there will not be a great enough supply of holes to etch the SiO2, and the passivation layer will not be removed. This will inhibit the etching of P+ silicon.

It has been observed that the selective etching may be P-type over N-type, or N-type over P-type depending on the solution temperature, flow rate of the aqueous ammonia, concentration of the aqueous ammonia, agitation, or illumination of light.

Assuming that the EMF potential is originating from the difference in Efermibetween N and P silicon, then a method that reduces or nullifies the potential difference between Efermito Eintrisiccould be used to reduce the etch selectivity between N- and P-type regions. In other words, a method that inactivates the silicon can be used. One method of inactivating silicon is to bombard the silicon surface with heavy ions, such as Si, Ge or Xe. This destroys the silicon crystallinity, and inactivates the dopants, thus eliminating the supply of electrons in the N area (dissolution substrate), and eliminating the holes in the P area (passivation substrate). By amorphizing the silicon in this manner to a pre-defined depth, unbiased etching to the depth of the amorphized silicon can be achieved.

In one embodiment, N- and P-type extensions formed in the source/drain regions are implanted with the Xe, at a dose of 2E14 and energy of 10 keV, to create an amorphous depth of 100 A. Reference toFIG. 6, N and P-type regions are represented by extensions36and46respectively. Results indicate a significant reduction in the etch bias subsequent to inactivating the surface regions. For example, when a sample is not amorphized, the N area will etch100A, while the P area will etch little or none at all. For a surface that is amorphized, the N area will etch110A, while the P area will etch80A (seeFIG. 2). As a result, the final silicon thickness is much closer between N and P areas, after SEG growth, when the substrate is amorphized, as compared to when it is not amorphized.

The resulting SEG morphology was smooth in the P area, even with an 800° C. H2bake. Previously, this low bake temperature resulted in a rough surface when a wet clean only was applied. Lower bake temperatures are expected down to approximately to 750° C. Though not specifically illustrated, it will be appreciated that the gate structures may be masked during the implementation process.

The method and apparatus herein provides for a flexible implementation. Although described using certain specific examples, it will be apparent to those skilled in the art that the examples are illustrative, and that many variations exist. For example, the disclosure is discussed herein primarily with regard to a cleaning process following offset spacer formation which results in a surface suitable for selective epitaxial growth (SEG) and does not require an additional post-offset spacer clean for a CMOS device, however, the disclosure can be employed with other device technologies. Additionally, various types of deposition and etch devices are currently available which could be suitable for use in employing the method as taught herein. Note also, that although an embodiment of the present disclosure has been shown and described in detail herein, along with certain variants thereof, many other varied embodiments that incorporate the teachings of the disclosure may be easily constructed by those skilled in the art. Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. Accordingly, the present disclosure is not intended to be limited to the specific form set forth herein, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents, as can be reasonably included within the spirit and scope of the disclosure.