SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME

A semiconductor device includes a substrate; a stack structure including a first gate layer, a first interlayer insulating layer, and a second gate layer; and a channel structure penetrating through the stack structure and in contact with the substrate, the channel structure including a channel layer, a vertical tunneling layer surrounding the channel layer, a charge storage pattern on an outer surface of the vertical tunneling layer, and a blocking pattern on an outer surface of the charge storage pattern, the charge storage pattern includes first and second charge storage material layers vertically spaced apart and adjacent to the gate layers, the blocking pattern includes vertically spaced blocking material layers between the charge storage material layers and the gate layers, and the blocking pattern contacts the outer surface of the charge storage pattern and includes a vertical protrusion extending longer than the outer surface of the charge storage pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2021-0146505 filed on Oct. 29, 2021, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

Embodiments relate to a semiconductor device and a data storage system including the same.

2. Description of the Related Art

In a data storage system, a semiconductor device capable of storing high-capacity data may be used.

SUMMARY

The embodiments may be realized by providing a semiconductor device including a lower structure including a substrate; a stack structure including a first gate layer, a first interlayer insulating layer, and a second gate layer sequentially stacked on the lower structure; and a channel structure penetrating through the stack structure and in contact with the lower structure, the channel structure including a channel layer, a vertical tunneling layer surrounding the channel layer, a charge storage pattern on an outer side surface of the vertical tunneling layer, and a blocking pattern on an outer side surface of the charge storage pattern, wherein the charge storage pattern includes a first charge storage material layer and a second charge storage material layer spaced apart from each other in a vertical direction of an upper surface of the substrate and adjacent to the first gate layer and the second gate layer, respectively, the blocking pattern includes a first blocking material layer between the first charge storage material layer and the first gate layer and a second blocking material layer spaced apart from the first blocking material layer in the vertical direction and between the second charge storage material layer and the second gate layer, and the blocking pattern is in contact with the outer side surface of the charge storage pattern and includes a vertical protrusion part extending longer than the outer side surface of the charge storage pattern in the vertical direction.

The embodiments may be realized by providing a semiconductor device including a substrate; gate layers stacked on the substrate, the gate layers being spaced apart from each other in a vertical direction of an upper surface of the substrate; and channel structures penetrating through the gate layers and extending in the vertical direction, the channel structures respectively including a channel layer and a channel dielectric layer covering an outer side surface and a lower surface of the channel layer, wherein the channel dielectric layer includes a vertical tunneling layer, a charge storage pattern, and a blocking pattern sequentially stacked on the outer side surface and the lower surface of the channel layer, the charge storage pattern includes a first charge storage material layer and a second charge storage material layer on an outer side surface of the vertical tunneling layer and spaced apart from each other in the vertical direction, each of the first and second charge storage material layers including a first side surface in contact with the outer side surface of the vertical tunneling layer and a second side surface opposing the first side surface, the blocking pattern includes a first blocking material layer on the second side surface of the first charge storage material layer and a second blocking material layer spaced apart from the first blocking material layer in the vertical direction and on the second surface of the second charge storage material layer, each of the first and second blocking material layers includes a third side surface in contact with the charge storage pattern and a fourth side surface opposing the third side surface, a first length of the first side surface in the vertical direction is greater than a thickness, in the vertical direction, of each of the gate layers, and a second length of the second side surface in the vertical direction and a third length of the third side surface in the vertical direction are different from each other.

The embodiments may be realized by providing a data storage system including a semiconductor storage device including a lower structure including a lower substrate, circuit elements on the lower substrate, and an upper substrate on the circuit elements; a stack structure including a first gate layer, a first interlayer insulating layer, and a second gate layer sequentially stacked on the lower structure; a channel structure penetrating through the stack structure and in contact with the lower structure, and including a channel layer, a vertical tunneling layer surrounding the channel layer, an charge storage pattern on an outer side surface of the vertical tunneling layer, and a blocking pattern on an outer side surface of the charge storage pattern; and an input/output pad electrically connected to the circuit elements, the charge storage pattern including first and second charge storage material layers spaced apart from each other in a vertical direction of an upper surface of the lower structure and adjacent to the first and second gate layers, respectively, the blocking pattern including a first blocking material layer in contact with the first charge storage material layer and the first gate layer and a second blocking material layer spaced apart from the first blocking material layer in the vertical direction and in contact with the second charge storage material layer and the second gate layer, and the blocking pattern being in contact with the outer side surface of the charge storage pattern and including vertical protrusion part extending to be longer than the outer side surface of the charge storage pattern in the vertical direction; and a controller electrically connected to the semiconductor storage device through the input/output pads and controlling the semiconductor storage device.

The embodiments may be realized by providing a method of manufacturing a semiconductor device, the method including forming a molded structure including first material layers and second material layers, the first material layers being stacked on a substrate so as to be spaced apart from the substrate in a vertical direction and each having a first thickness, and the second material layers being stacked alternately with the first material layers and each having a second thickness; forming a hole penetrating through the molded structure and sequentially forming a preliminary blocking pattern, a preliminary charge storage pattern, a vertical tunneling layer, and a channel layer in the hole; forming trenches through the molded structure; forming first tunnel parts by selectively removing the second material layers with respect to the first material layers through the trenches; forming a blocking pattern by removing at least a portion of the preliminary blocking pattern exposed through the first tunnel parts; and forming a charge storage pattern including a plurality of charge storage material layers by removing at least a portion of the preliminary charge storage pattern exposed by the removed preliminary blocking pattern, wherein forming the charge storage pattern includes removing portions of the first material layers together with the preliminary charge storage pattern, and a third thickness of each of the first material layers removed in the vertical direction is smaller than the first thickness and is smaller than a length of each of the plurality of charge storage material layers in the vertical direction.

DETAILED DESCRIPTION

FIG.1is a plan view of a semiconductor device100according to example embodiments, andFIG.2is a cross-sectional view of the semiconductor device100according to example embodiments.FIG.2is a cross-sectional view of the semiconductor device100taken along line I-I′ ofFIG.1.FIG.3Ais a partially enlarged view of a region corresponding to region ‘A’ of the semiconductor device100ofFIG.2.

Referring toFIGS.1to3A, the semiconductor device100may include a substrate101, a first horizontal conductive layer102, a second horizontal conductive layer104, gate layers130stacked on the substrate101, interlayer insulating layers120stacked alternately with the gate layers130on the substrate101, isolation structures MS extending and penetrating through a stack structure GS including the gate layers130and the interlayer insulating layers120, channel structures CH penetrating through the stack structure GS and respectively including a channel layer140, and an upper insulating layer180.

The substrate101may have an upper surface extending in an X-direction and a Y-direction (e.g., in an X-Y plane). The substrate101may include a semiconductor material, e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. In an implementation, the group IV semiconductor may include, e.g., silicon, germanium, or silicon-germanium. In an implementation, the substrate101may be, e.g., a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B.

The first and second horizontal conductive layers102and104may be sequentially stacked on the upper surface of the substrate101. The first horizontal conductive layer102may function as at least a portion of a common source line of the semiconductor device100, e.g., may function as the common source line with the substrate101. As illustrated inFIG.2, the first horizontal conductive layer102may be in direct contact with and electrically connected to the channel layer140at a periphery of the channel layer140. The first and second horizontal conductive layers102and104may include a semiconductor material, e.g., polycrystalline silicon. In an implementation, the first horizontal conductive layer102may be a layer doped with impurities of the same conductivity-type as the substrate101, and the second horizontal conductive layer104may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer102.

In an implementation, the semiconductor device100may further include horizontal insulating layers. The horizontal insulating layers may be spaced apart from the first horizontal conductive layer102and may be parallel to the first horizontal conductive layer102on the upper surface of the substrate101. The horizontal insulating layers may be layers remaining after a portion thereof are replaced with the first horizontal conductive layer102in a process of manufacturing the semiconductor device100. The second horizontal conductive layer104may cover the first horizontal conductive layer102and the horizontal insulating layers. The horizontal insulating layers may include first to third horizontal insulating layers that are sequentially stacked. The horizontal insulating layers may include, e.g., silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first and third horizontal insulating layers may include an insulating material different from that of the second horizontal insulating layer. The first and third horizontal insulating layers may include the same material. In an implementation, the first and third horizontal insulating layers may be formed of the same material as the interlayer insulating layers120, and the second horizontal insulating layer may be formed of the same material as sacrificial first material layers118(seeFIG.12A).

In an implementation, a lower structure may include the substrate101, the first horizontal conductive layer102, the second horizontal conductive layer104, and the horizontal insulating layers. In an implementation, the lower structure may not include the first and second horizontal conductive layers102and104and the horizontal insulating layers.

The gate layers130may be stacked on the lower structure and spaced apart from an upper surface of the lower structure in a Z-direction, which is a vertical direction, to constitute the stack structure GS. The gate layers130may be stacked to be vertically spaced apart from each other on a first region of the substrate101, and may extend at different lengths from the first region to a second region of the substrate101to form a step structure having a stair shape. The first region may correspond to a memory array region, and the second region may be a region for electrical connection with word lines of the memory array region. The first region may be referred to as a ‘memory cell region’ or a ‘memory cell array region,’ and the second region may be referred to as a ‘stair region’ or a ‘connection region.’ In an implementation, at least some of the gate layers130, e.g., a predetermined number of gate layers130such as two to six gate layers130, may constitute one gate group, and a step structure may be formed between the gate groups along the X-direction.

The gate layers130may include a lower gate electrode including a gate of a ground select transistor, middle gate electrodes constituting gates of a plurality of memory cells, and an upper gate electrode including gates of a string select transistor. The lower gate electrode may be a ground selection line, the upper gate electrode may be a string selection line, and the middle gate electrodes may be word lines. The number of middle gate electrodes constituting the plurality of memory cells may be determined according to a capacity of the semiconductor device100. In an implementation, each of the numbers of upper and lower gate electrodes may be one or two or more, and the upper and lower gate electrodes may have structures that are the same as or different from those of the middle gate electrodes. In an implementation, the gate layers130may further include a gate electrode above the upper gate electrode or below the lower gate electrode and constituting an erase transistor used for an erase operation using a gate induced drain leakage (GIDL) phenomenon. In addition, some of the gate layers130, e.g., the middle gate electrodes adjacent to the upper or lower gate electrodes may be dummy gate electrodes.

In an implementation, each of the gate layers130may include a gate conductive layer131and a gate dielectric layer132. The gate conductive layer131may be a gate electrode. The gate dielectric layer132may cover side surfaces of the gate conductive layer131facing the channel structures CH while covering upper and lower surfaces of the gate conductive layer131. Accordingly, the gate dielectric layer132may extend between the gate conductive layer131and the interlayer insulating layers120while being between the gate conductive layer131and the channel structures CH. The gate conductive layer131may include a conductive material such as tungsten (W). In an implementation, the gate conductive layer131may include polycrystalline silicon or a metal silicide material. The gate dielectric layer132may be formed of a dielectric material, and may include, e.g., aluminum oxide (AlO). The gate dielectric layer132may serve as a blocking layer for preventing electrical charges in a charge storage pattern141bfrom moving to the gate conductive layer131, together with a blocking pattern141c. In an implementation, the semiconductor device100may include a diffusion barrier surrounding the gate conductive layer131unlike the gate dielectric layer132. The diffusion barrier may include, e.g., silicon nitride, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof. In an implementation, the gate layers130of the semiconductor device100may include all of the gate conductive layer, the diffusion barrier, and the gate dielectric layer surrounding the diffusion barrier.

The interlayer insulating layers120may be between the gate layers130. The interlayer insulating layers120may be stacked alternately with the gate layers130to constitute the stack structure GS. The interlayer insulating layers120may include an insulating material such as silicon oxide or silicon nitride.

In an implementation, the gate layers130may include a first gate layer130-1and a second gate layer130-2adjacent to each other, and the interlayer insulating layers120may include a first interlayer insulating layer120-1(e.g., on a level) between the first gate layer130-1and the second gate layer130-2. Accordingly, the stack structure GS may include the first gate layer130-1, the first interlayer insulating layer120-1, and the second gate layer130-2that are sequentially stacked.

The isolation structures MS may penetrate through the gate layers130, the interlayer insulating layers120, and the first and second horizontal conductive layers102and104and may be connected to the substrate101. In an implementation, the isolation structures MS may extend into the substrate101to be in contact with the substrate101, or may be in contact with the upper surface of the substrate101without penetrating through the substrate101, or may be spaced apart from the substrate101. In an implementation, the isolation structures MS may have a shape of which a width (e.g., as measured in the X direction or Y direction) decreases toward or closer to the substrate101due to a high aspect ratio. The isolation structures MS may be respectively positioned in trenches extending (e.g., lengthwise) along the X-direction. The isolation structures MS may be spaced apart from each other in the Y-direction. In an implementation, the isolation structures MS may isolate the gate layers130from each other along the Y-direction. In an implementation, the isolation structures MS may include a metal material or an insulating material in the trenches. In an implementation, each of the isolation structures MS may include an isolation pattern and spacers on side surfaces of the isolation pattern. The isolation pattern may include a conductive material, and the spacers may include an insulating material such as silicon oxide.

Upper isolation structures SS may extend in the X-direction between the isolation structures MS adjacent to each other in the Y-direction. The upper isolation structures SS may penetrate through some of the gate layers130U, including the uppermost gate layer130U of the gate layers130. In an implementation, as illustrated inFIG.2, the upper isolation structures SS may isolate, e.g., one gate layer130U in the Y-direction, or the number of gate layers isolated by the upper isolation structures SS may be variously modified. The number of isolated gate layers130may be determined according to the number of string selection lines. The upper isolation structures SS may include an insulating material.

The channel structures CH may penetrate through the stack structure GS including the gate layers130and the interlayer insulating layers120. In an implementation, the channel structures CH may penetrate through the first and second horizontal conductive layers102and104and extend into the substrate101. The channel structures CH may each constitute one memory cell string, and may be spaced apart from each other while forming rows and columns on the substrate101. The channel structures CH may form a lattice pattern in the X-Y plane or may be in a zigzag shape in one direction. The channel structures CH may have a hole shape and a pillar shape, and may have inclined side surfaces that become narrower as they become closer to the substrate101, e.g., according to an aspect ratio. In an implementation, as illustrated inFIGS.2and3A, each of the channel structures CH may further include a channel dielectric layer141surrounding the channel layer140and a channel pad145on an upper end of the channel layer140, in addition to the channel layer140. In an implementation, each of the channel structures CH may further include a channel filling insulating layer144covering inner side surfaces of the channel layer140.

In an implementation, the channel layer140may have an annular shape surrounding the channel filling insulating layer144therein, or may have a pillar shape such as a cylindrical shape or a prismatic shape without the channel filling insulating layer144. The channel layer140may be connected to the first horizontal conductive layer102at a lower portion thereof. The channel layer140may include a semiconductor material, e.g., polycrystalline silicon or single crystal silicon, and the semiconductor material may be an undoped material or a material including p-type or n-type impurities.

The channel dielectric layer141may include a vertical tunneling layer141acovering an outer side surface of the channel layer140, a charge storage pattern141bon an outer side surface of the vertical tunneling layer141a, and a blocking pattern141con an outer side surface of the charge storage pattern141b. In a horizontal direction perpendicular to the Z-direction, (e.g., as measured in the X direction or Y direction) each of the vertical tunneling layer141a, the charge storage pattern141b, and the blocking pattern141cmay have a uniform thickness.

The vertical tunneling layer141amay have an annular shape surrounding the channel layer140. The vertical tunneling layer141amay have a shape covering a side surface and a lower surface of the channel layer140. Accordingly, an inner side surface of the vertical tunneling layer141amay be in contact (e.g., direct contact) with the channel layer140. The outer side surface of the vertical tunneling layer141amay be in contact with the charge storage pattern141band the interlayer insulating layers120. The vertical tunneling layer141amay tunnel electrical charges of the channel layer140to the charge storage pattern141b, and may include, e.g., silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof.

The charge storage pattern141bmay be on the outer side surface of the vertical tunneling layer141a. The charge storage pattern141bmay be between the vertical tunneling layer141aand the blocking pattern141c. The charge storage pattern141bmay have a uniform thickness and may surround the vertical tunneling layer141a. In an implementation, an upper surface and a lower surface of the charge storage pattern141bmay be curved surfaces. The charge storage pattern141bmay be a charge trap layer. In an implementation, the charge storage pattern141bmay trap and retain electrons injected from the channel layer140through the vertical tunneling layer141ainto the charge trap layer or erase electrons trapped in the charge trap layer, according to operation conditions of a nonvolatile memory element such as a flash memory element. The charge storage pattern141bmay include a plurality of charge storage material layers spaced apart from each other in the Z-direction. The plurality of charge storage material layers may be electrically isolated from each other by the interlayer insulating layers120. The plurality of charge storage material layers may be spaced apart from each other, and thus, an electrical charge loss problem that could otherwise occur in the Z-direction may be addressed.

In an implementation, the plurality of charge storage material layers may include a first charge storage material layer141b-1and a second charge storage material layer141b-2adjacent to each other in the Z-direction. A maximum length L1of each of the first and second charge storage material layers141b-1and141b-2in the Z-direction may be greater than a maximum length L3of each of the first and second gate layers130-1and130-2in the Z-direction. This may be because the charge storage pattern141bincludes a material of which an etch rate may be controlled to be slower than that of first material layers118(seeFIG.12A) in a region corresponding to the gate layers130under a specific etching condition. In an implementation, the maximum length L3of each of the first and second gate layers130-1and130-2in the Z-direction may refer to a maximum length of the gate conductive layer131in the Z-direction. In the horizontal direction perpendicular to the Z-direction, e.g., the Y-direction the first and second gate layers130-1and130-2may overlap the first and second charge storage material layers141b-1and141b-2, respectively. Accordingly, an electrical charge loss problem that could otherwise occur in the horizontal direction may be addressed.

The charge storage pattern141bmay include, e.g., a nitride, a silicon nitride, or a nitride material. The charge storage pattern141bmay include a material having an etch rate lower than that of the first material layer118(seeFIG.12A) under a specific etching condition. The charge storage pattern141band the first material layer118may be layers etched in the same etching process. In an implementation, the charge storage pattern141bmay include the same material as the first material layer118, or may have a composition ratio different from that of the first material layer118.

The blocking pattern141cmay be between the charge storage pattern141band the gate layers130. The blocking pattern141cmay have a uniform thickness (e.g., as measured in the X direction or Y direction) on the outer side surface of the charge storage pattern141b. In an implementation, an upper surface and a lower surface of the blocking pattern141cmay be curved surfaces. The blocking pattern141cmay be a blocking layer that helps prevent the electrical charges trapped in the charge storage pattern141bfrom moving to the gate layers130. In an implementation, the blocking layer may include the charge storage pattern141band the gate dielectric layer132. In an implementation, the blocking pattern141cmay include a plurality of blocking material layers spaced apart from each other in the Z-direction.

In an implementation, the plurality of blocking material layers may include a first blocking material layer141c-1and a second blocking material layer141c-2adjacent to each other in the Z-direction. The first blocking material layer141c-1may be between the first charge storage material layer141b-1and the first gate layer130-1, and the second blocking material layer141c-2may be between the second charge storage material layer141b-2and the second gate layer130-2. The first blocking material layer141c-1may be in contact with the first charge storage material layer141b-1and the first gate layer130-1, and the second blocking material layer141c-2may be in contact with the second charge storage material layer141b-2and the second gate layer130-2. A maximum length L2of each of the first and second blocking material layers141c-1and141c-2in the Z-direction may be greater than the maximum length L3of each of the first and second gate layers130-1and130-2in the Z-direction. In the horizontal direction perpendicular to the Z-direction, the first and second gate layers130-1and130-2may overlap the first and second blocking material layers141c-1,141c-2, respectively. In an implementation, the maximum length L2of each of the first and second blocking material layers141c-1and141c-2in the Z-direction may be substantially the same as the maximum length L1of each of the first and second charge storage material layers141b-1and141b-2in the Z-direction, or may be smaller than the maximum length L1of each of the first and second charge storage material layers141b-1and141b-2in the Z-direction.

In an implementation, each of the first and second charge storage material layers141b-1and141b-2may include a first side surface S1in contact with the outer side surface of the vertical tunneling layer141aand a second side surface S2, which is an outer side surface opposing the first side surface S1. A first length of the first side surface S1in the Z-direction may be greater than a second length of the second side surface S2in the Z-direction. The first length may be greater than a thickness of each of the gate layers130. Each of the first and second blocking material layers141c-1and141c-2may include a third side surface S3in contact with the charge storage pattern141band a fourth side surface S4being an outer side surface opposing the third side surface S3and in contact with the gate layers130. A third length of the third side surface S3in the Z-direction may be greater than a fourth length of the fourth side surface S4in the Z-direction. The second length of the second side surface S2may be smaller than the third length of the third side surface S3. In an implementation, the blocking pattern141cmay further include vertical protrusion parts141VP extending in the Z-direction from a surface thereof in contact with the charge storage pattern141b. Accordingly, the channel dielectric layer141may include steps (e.g., discontinuities or level differences) between the charge storage pattern141band the blocking pattern141c. The vertical protrusion parts141VP or the steps may be structures generated while performing an etching process for the blocking pattern141cand an etching process for the charge storage pattern141bin two steps. The blocking pattern141cmay be in contact with the outer side surface of the charge storage pattern141b, and the vertical protrusion parts141VP may extend to be longer than the outer side surface of the charge storage pattern141bin the Z-direction.

In an implementation, the first gate layer130-1may be in contact with the first blocking material layer141c-1, the second gate layer130-2may be in contact with the second blocking material layer141c-2, and the first interlayer insulating layer120-1may be (e.g., on or at the level) between the first gate layer130-1and the second gate layer130-2. The first interlayer insulating layer120-1may extend between the first gate layer130-1and the second gate layer130-2to cover the first and second blocking material layers141c-1and141c-2and the first and second charge storage material layers141b-1and141b-2, and may be in contact with the vertical tunneling layer141a.

The first interlayer insulating layer120-1may include a first horizontal protrusion part120PP1extending in a direction toward the vertical tunneling layer141aand a second horizontal protrusion part120PP2extending in a direction from the first horizontal protrusion part120PP1toward the vertical tunneling layer141a. The first horizontal protrusion part120PP1may isolate the first blocking material layer141c-1and the second blocking material layer141c-2from each other, and the second horizontal protrusion part120PP2may isolate the first charge storage material layer141b-1and the second charge storage material layer141b-2from each other. Each of the first and second horizontal protrusion parts120PP1and120PP2may have a convex shape in the direction toward the vertical tunneling layer141a. In the first interlayer insulating layer120-1, a first thickness W1of the second horizontal protrusion part120PP2(as measured in the Z direction) may be smaller than a second thickness W2in a region between the first gate layer130-1and the second gate layer130-2(as measured in the Z direction). In an implementation, a distance (in the Z direction) between the first and second charge storage material layers141b-1and141b-2spaced apart from each other may be smaller than a distance (in the Z direction) between the first and second gate layers130-1and130-2spaced apart from each other. This may be because the charge storage pattern141bmay include a material of which an etch rate may be controlled to be slower than that of the first material layers118(seeFIG.12A) in the region corresponding to the gate layers130under a specific etching condition, e.g., a material different from that of the first material layers118(seeFIG.12A). At least portions of the vertical protrusion parts141VP of the first and second blocking material layers141c-1and141c-2may be in contact with the first horizontal protrusion part120PP1and the second horizontal protrusion part120PP2.

The channel pad145may be on the channel layer140in each of the channel structures CH. The channel pad145may cover an upper surface of the channel filling insulating layer144and may be electrically connected to the channel layer140. The channel pad145may include, e.g., doped polycrystalline silicon.

In an implementation, the semiconductor device100may further include dummy channel structures DCH having the same structure as the channel structures CH. The dummy channel structures DCH may be spaced apart from each other while forming rows and columns with the channel structures CH on the substrate101, and may be, e.g., in a region overlapping the upper isolation structures SS. In an implementation, the dummy channel structures DCH may penetrate through the gate layers130and the upper isolation structures SS, or an arrangement relationship and structure of the dummy channel structures DCH may be variously modified.

The upper insulating layer180may cover the stack structure GS including the gate layers130and the interlayer insulating layers120and the channel structures CH. The upper insulating layer180may be formed of an insulating material, and may include, e.g., silicon oxide, silicon nitride, or silicon oxynitride. In an implementation, the upper insulating layer180may include a first upper insulating layer181, a second upper insulating layer182on the first upper insulating layer181, and a third upper insulating layer183on the second upper insulating layer182. The first upper insulating layer181may cover the stack structure GS, the second upper insulating layer182may cover the channel structures CH, the dummy channel structures DCH, and the first upper insulating layer181, and the third upper insulating layer183may cover the isolation structures MS and the second upper insulating layer182. The isolation structures MS may penetrate through the second upper insulating layer182and have an upper surface coplanar with an upper surface of the third upper insulating layer183.

In an implementation, the semiconductor device100may further include an upper wiring structure190including upper contact structures191and an upper wiring pattern192. The upper contact structures191may penetrate through the second and third upper insulating layers182and183and be connected to the channel structures CH. The upper contact structures191may include a conductive material, e.g., tungsten (W), copper (Cu), or aluminum (Al). The upper wiring pattern192may be on the third upper insulating layer183, and may constitute an upper wiring structure electrically connected to the channel structures CH. The upper wiring pattern192may be bit lines. The upper wiring pattern192may include a conductive material, e.g., tungsten (W), copper (Cu), or aluminum (Al). In an implementation, the upper contact structures191and the upper wiring pattern192may include the same material. In an implementation, the upper wiring pattern192and the upper contact structures191may be formed by different processes, or may be formed integrally with each other.

FIG.3Bis a partially enlarged cross-sectional view of a modified example of a semiconductor device100aaccording to example embodiments.FIG.3Bis a partially enlarged view illustrating a region corresponding to region ‘A’ ofFIG.2.

Referring toFIG.3B, the maximum length L2of the first blocking material layer141c-1in the Z-direction may be greater than the maximum length L1of the first charge storage material layers141b-1in the Z-direction and the maximum length L3of the first gate layers130-1in the Z-direction. This may be a structure generated because an etch rate difference of the charge storage pattern141band a first material layer118(seeFIG.12A) in a region corresponding to the first gate layer130-1may be relatively small as compared with an example embodiment ofFIG.3A. The first charge storage material layer141b-1may include a material of which an etch rate is slower than that of the first material layers118under a specific etching condition. In an implementation, in a process of etching portions of the first material layers118to make a region corresponding to the maximum length L3of the first gate layer130-1in the Z-direction remain, an etch rate for the first charge storage material layer141b-1may relatively increase as compared with an example embodiment ofFIG.3A, such that the maximum length of the first charge storage material layer141b-1in the Z-direction may decrease.

In an implementation, each of the first and second charge storage material layers141b-1and141b-2may include a first side surface S1in contact with the outer side surface of the vertical tunneling layer141aand a second side surface S2, which is an outer side surface opposing the first side surface S1. A first length of the first side surface S1in the Z-direction may be greater than a second length of the second side surface S2in the Z-direction. The first length may be greater than a thickness (in the Z direction) of each of the gate layers130. Each of the first and second blocking material layers141c-1and141c-2may include a third side surface S3in contact with the charge storage pattern141b-1and a fourth side surface S4being an outer side surface opposing the third side surface S3and in contact with the gate layers130. A third length of the third side surface S3in the Z-direction may be greater than a fourth length of the fourth side surface S4in the Z-direction. The second length of the second side surface S2may be smaller than the third length of the third side surface S3. The first length of the first side surface S1may be smaller than the third length or the fourth length.

In an implementation, in the first interlayer insulating layer120-1, a first thickness W1of the second horizontal protrusion part120PP2may be smaller than a second thickness W2in a region between the first gate layer130-1and the second gate layer130-2. In addition, the first thickness W1may be greater than a thickness of the first horizontal protrusion part120PP1in the Z-direction.

The second charge storage material layer141b-2may have the same structure as the first charge storage material layer141b-1, the second blocking pattern141c-2may have the same structure as the first blocking pattern141c-1, the second gate layer130-2may have the same structure as the first gate layer130-1, and a repeated description may be omitted.

FIG.3Cis a partially enlarged cross-sectional view of a modified example of a semiconductor device100baccording to example embodiments.FIG.3Cis a partially enlarged view illustrating a region corresponding to region ‘A’ ofFIG.2.

Referring toFIG.3C, the semiconductor device100bmay include the same structure as the semiconductor device100ofFIG.3Aexcept for a structure of the gate layers130.

In the gate layers130, a thickness L4(in the Z direction) of a region in contact with the blocking pattern141cmay be greater than a thickness L3of the other regions (e.g., distal to the blocking pattern141). The gate layers130may have a uniform thickness in the other regions and may have an increasing thickness toward the blocking pattern141cin the region in contact with or adjacent to the blocking pattern141c. This may be caused by the first material layers118that are not etched to have a uniform thickness and remain in a process of etching the first material layers118(seeFIG.12A) in regions corresponding to the gate layers130.

FIG.3Dis a partially enlarged cross-sectional view of a modified example of a semiconductor device100caccording to example embodiments.FIG.3Dis a partially enlarged view of a region corresponding to region ‘A’ ofFIG.2.

Referring toFIG.3D, the semiconductor device100cmay include the same structure as the semiconductor device100ofFIG.3Aexcept for a structure of the charge storage pattern141b.

The charge storage pattern141bmay be a charge storage material layer that continuously extends (e.g., along the entire height or length of the channel dielectric layer141in the Z direction). The charge storage material layer may not be a plurality of charge storage material layers spaced apart from each other, and may be a single charge storage material layer having a non-uniform thickness on the outer side surface of the vertical tunneling layer141a. The charge storage material layer may have a relatively great thickness (e.g., in a horizontal direction) in a region in contact with the blocking pattern141cand a relatively small thickness in a region in contact with the interlayer insulating layers120. This may be a structure generated because in a process of forming an opening in a region corresponding to the second protrusion part120PP2, the opening may not be formed so as to penetrate through the charge storage pattern141band may be in contact with the vertical tunneling layer141a.

FIG.3Eis a partially enlarged cross-sectional view of a modified example of a semiconductor device100daccording to example embodiments.FIG.3Eis a partially enlarged view of a region corresponding to region ‘A’ ofFIG.2.

Referring toFIG.3E, the semiconductor device100dmay include a structure of a charge storage pattern141bdifferent from that ofFIG.3A. The charge storage pattern141bmay have upper and lower surfaces convex toward an inner portion of the charge storage pattern141b(e.g., may have inwardly recessed upper and lower surfaces) This may be a structure generated by using an etching process or an etching material different from that ofFIG.3A. However, also in this case, as described above with reference toFIG.3A, the charge storage pattern141band the first material layers118(seeFIG.12A) may be etched in the same etching process, and the maximum length L1of each of the first and second charge storage material layers141b-1and141b-2in the Z-direction may be greater than the maximum length L3of each of the first and second gate layers130-1and130-2in the Z-direction.

In an implementation, the blocking pattern141cmay have upper and lower surfaces convex toward an inner portion of the blocking pattern141c, similar to the charge storage pattern141b. In an implementation, the blocking pattern141cmay include the upper and lower structures ofFIG.3Aunlike the charge storage pattern141b.

FIG.4is a cross-sectional view of a semiconductor device100eaccording to example embodiments.FIG.4illustrates a region corresponding to a cross section of the semiconductor device100etaken along line I-I′ ofFIG.1.

Referring toFIG.4, the semiconductor device100emay have structures of a lower structure and channel structures different from those of the semiconductor device100ofFIG.1to3A. Accordingly, a repeated description of structures similar to those described above with reference toFIG.1to3Amay be omitted.

The lower structure may include the substrate101, and may not include the first horizontal conductive layer102, the second horizontal conductive layer104, and the horizontal insulating layers, unlikeFIG.2. The semiconductor device100emay include the stack structure GS including the interlayer insulating layers120and the gate layers130spaced apart from each other and alternately stacked on the lower structure.

Each of the channel structures CH may further include a lower epitaxial layer146together with the channel layer140, the vertical tunneling layer141a, the charge storage pattern141b, the blocking pattern141c, the channel filling insulating layer144, and the channel pad145.

The lower epitaxial layer146may be on the upper surface of the substrate101at a lower end of each of the channel structures CH, and may be on a side surface of the at least one lower gate layer130. The lower epitaxial layer146may be connected to the channel layer140. The lower epitaxial layer146may be in a recessed region of the substrate101. An insulating layer147may be between the lower epitaxial layer146and the lower gate layer130. In an implementation, the lower epitaxial layer146may be omitted. In this case, the channel layer140may be directly connected to the substrate101or may be connected to a separate conductive layer on the substrate101.

The channel layer140may cover a lower surface and side surfaces of the channel filling insulating layer144, and may be in contact with an upper surface of the epitaxial layer146on the lower epitaxial layer146. The vertical tunneling layer141amay cover side surface of the channel layer140. In an implementation, the vertical tunneling layer141amay not cover a lower surface of the channel layer140.

FIG.5is a cross-sectional view of a semiconductor device100faccording to example embodiments.FIG.5illustrates a region corresponding to a cross section of the semiconductor device100ftaken along line I-I′ ofFIG.1.

Referring toFIG.5, in the semiconductor device100f, the stack structure GS may include a lower stack structure GS1and an upper stack structure GS2on the lower stack structure GS1, and each of the channel structures CH may include a lower channel structure CH1and an upper channel structure CH2on the lower channel structure CH1. Such a structure of each of the channel structures CH may be introduced in order to stably form the channel structures CH when the number of stacked gate layers130is relatively large. In an implementation, the number of stacked channel structures may be variously modified.

The lower stack structure GS1may include lower interlayer insulating layers120aand lower gate layers130aalternately stacked on the substrate101, and the upper stack structure GS2may include upper interlayer insulating layers120band upper gate layers130balternately stacked on the lower stack structure GS1. In an implementation, the lower stack structure GS1may further include a connection insulating layer121at the uppermost end thereof and having a thickness (in the Z direction) relatively greater than that of the interlayer insulating layers120. The connection insulating layer121may include an insulating material, e.g., silicon oxide, silicon nitride, or silicon oxynitride. The connection insulating layer121may include the same material as the interlayer insulating layers120.

Each of the channel structures CH may include the lower channel structure CH1penetrating through the lower stack structure GS1and the upper channel structure CH2penetrating through the upper stack structure GS2. The upper channel structure CH2may penetrate through the upper stack structure GS2and be connected to the lower channel structure CH1. In an implementation, the lower channel structure CH1and the upper channel structure CH2may have a connected form. The channel layer140, the vertical tunneling layer141, and the channel filling insulating layer144may have a connected form between the lower channel structure CH1and the upper channel structure CH2. In an implementation, the channel pad145may be only at an upper end of the upper channel structure CH2, or the lower channel structure CH1and the upper channel structure CH2may each include the channel pad145and the channel pad145of the lower channel structure CH1may be connected to the channel layer140of the upper channel structure CH2.

Each of the lower channel structure CH1and the upper channel structure CH2may have inclined side surfaces such that the channel structures may become narrower as it becomes closer to the substrate101. In an implementation, a width of the uppermost portion of the lower channel structure CH1may be greater than a width of the lowermost portion of the upper channel structure CH2. Accordingly, each of the channel structures CH may include a bent part formed due to a change in the width on a level of a region in which the lower channel structure CH1and the upper channel structure CH2are connected to each other.

The form of the stack structure GS and the plurality of channel structures CH described above may also be applied to example embodiments ofFIGS.1to4.

FIG.6is a cross-sectional view of a semiconductor device100gaccording to example embodiments.FIG.6illustrates a region corresponding to a cross section of the semiconductor device100gtaken along line I-I′ ofFIG.1.

Referring toFIG.6, the semiconductor device100gmay include a memory cell region CELL and a peripheral circuit region PERI that are vertically stacked. The memory cell region CELL may be on an upper end of the peripheral circuit region PERI. In an implementation, in a case of the semiconductor device100ofFIG.2, the peripheral circuit region PERI may be on the substrate101in a region that is not illustrated, or as in the semiconductor device100gaccording to the present example embodiment, the peripheral circuit region PERI may be beneath the substrate101. In an implementation, the memory cell region CELL may be on a lower end of the peripheral circuit region PERI. A description provided above with reference toFIGS.1to5may be equally applied to a description of the memory cell region CELL.

The peripheral circuit region PERI may include a base substrate201and circuit elements220, circuit contact plugs270, and circuit wiring lines280disposed on the base substrate201.

The base substrate201may have an upper surface extending in the X-direction and the Y-direction. In the base substrate201, separate element isolation layers may be formed, such that an active region may be defined. Source/drain regions205including impurities may be in a portion of the active region. The base substrate201may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The base substrate201may also be provided as a bulk wafer or an epitaxial layer. In an implementation, the substrate101may be provided as a polycrystalline semiconductor layer such as a polycrystalline silicon layer or an epitaxial layer.

The circuit elements220may include horizontal transistors. Each of the circuit elements220may include a circuit gate dielectric layer222, a spacer layer224, and a circuit gate electrode225. Source/drain regions205may be disposed in the base substrate201on both sides of the circuit gate electrode225. The circuit elements220may be electrically connected to the gate layers130or the channel structures CH.

A peripheral region insulating layer290may be on the circuit elements220on the base substrate201. The circuit contact plugs270may penetrate through the peripheral region insulating layer290and be connected to the source/drain regions205. Electrical signals may be applied to the circuit elements220by the circuit contact plugs270. In a region that is not illustrated, the circuit contact plugs270may also be connected to the circuit gate electrode225. The circuit wiring lines280may be connected to the circuit contact plugs270and may be arranged as a plurality of layers.

In the semiconductor device100g, the peripheral circuit region PERI may be first manufactured, and the substrate101of the memory cell region CELL may then be formed on the peripheral circuit region PERI, such that the memory cell region CELL may be manufactured. The substrate101may have the same size as the base substrate201or may be formed to be smaller than that of the base substrate201. In an implementation, the lower structure may refer to a structure including the peripheral circuit region PERI and the substrate101. The memory cell region CELL and the peripheral circuit region PERI may be connected to each other in a region that is not illustrated. In an implementation, one ends of the gate layers130in the Y-direction may be electrically connected to the circuit elements220. The form in which the memory cell region CELL and the peripheral circuit region PERI are vertically stacked as described above may also be applied to example embodiments ofFIGS.1to5.

FIG.7is a cross-sectional view of a semiconductor device100haccording to example embodiments.FIG.7illustrates a region corresponding to a cross section of the semiconductor device100htaken along line I-I′ ofFIG.1.

Referring toFIG.7, the semiconductor device100hmay include a first structure S1and a second structure S2bonded to each other in a wafer bonding manner.

The description of the peripheral circuit region PERI described above with reference toFIG.6may be applied to the first structure S1. In an implementation, the first structure S1may further include first bonding vias298and first bonding pads299, which are bonding structures.

The first bonding vias298may be on the uppermost circuit wiring lines280and may be connected to the circuit wiring lines280. At least some of the first bonding pads299may be connected to the first bonding vias298on the first bonding vias298. The first bonding pads299may be connected to second bonding pads199of the second structure S2. The first bonding pads299may provide electrical connection paths according to bonding between the first structure S1and the second structure S2, together with the second bonding pads199. Each of the first bonding vias298and the first bonding pads299may include a conductive material such as copper (Cu).

The description provided above with reference toFIGS.1to6may be equally applied to the second structure S2, unless otherwise described. The second structure S2may further include second bonding vias198and the second bonding pads199, which are bonding structures. The second structure S2may further include a protective layer covering an upper surface of the substrate101.

The second bonding vias198and the second bonding pads199may be below the lowermost wiring lines. The second bonding vias198may be connected to the wiring lines and the second bonding pads199, and the second bonding pads199may be bonded to the first bonding pads299of the first structure S1. Each of the second bonding vias198and the second bonding pads199may include a conductive material such as copper (Cu).

The first structure S1and the second structure S2may be bonded to each other by copper (Cu)-copper (Cu) bonding by the first bonding pads299and the second bonding pads199. The first structure S1and the second structure S2may also be bonded to each other by dielectric-dielectric bonding, in addition to the copper (Cu)-copper (Cu) bonding. The dielectric-dielectric bonding may be bonding dielectric layers constituting a portion of each of the peripheral region insulating layer290and the upper insulating layer180and surrounding each of the first bonding pads299and the second bonding pads199. Accordingly, the first structure S1and the second structure S2may be bonded to each other without a separate adhesive layer.

FIG.8is a schematic block diagram of a data storage system1000including a semiconductor device according to example embodiments.

Referring toFIG.8, the data storage system1000may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The data storage system1000may be a storage device including one semiconductor device1100or a plurality of semiconductor devices1100or an electronic device including the storage device. In an implementation, the data storage system1000may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communications device including one semiconductor device1100or a plurality of semiconductor devices1100.

The semiconductor device1100may be a nonvolatile memory device, and may be, e.g., the NAND flash memory device described above with reference toFIGS.1to7. The semiconductor device1100may include a first semiconductor structure1100F and a second semiconductor structure1100S on the first semiconductor structure1100F. In an implementation, the first semiconductor structure1100F may be next to the second semiconductor structure1100S. The first semiconductor structure1100F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second semiconductor structure1100S may be a memory cell structure including bit lines BL, a common source line CSL, word lines WL, first and second gate upper lines UL1and UL2, first and second gate lower lines LL1and LL2, and memory cell strings CSTR between the bit lines BL and the common source line CSL.

In the second semiconductor structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit lines BL, and a plurality of memory cell transistors MCT between the lower transistors LT1and LT2and the upper transistors UT1and UT2. In an implementation, the number of lower transistors LT1and LT2and the number of upper transistors UT1and UT2may be variously modified.

In an implementation, the upper transistors UT1and UT2may include a string selection transistor, and the lower transistors LT1and LT2may include a ground selection transistor. The gate lower lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrode layers of the memory cell transistors MCT, and the gate upper lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively.

In an implementation, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground select transistor LT2connected to each other in series. The upper transistors UT1and UT2may include a string select transistor UT1and an upper erase control transistor UT2connected to each other in series. At least one of the lower erase control transistor LT1and the upper erase control transistor UT1may be used for an erase operation of erasing data stored in the memory cell transistors MCT using a gate induced drain leakage (GIDL) phenomenon.

The common source line CSL, the first and second gate lower lines LL1and LL2, the word lines WL, and the first and second gate upper lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection wirings1115extending from the first semiconductor structure1100F to the second semiconductor structure1100S. The bit lines BL may be electrically connected to the page buffer1120through second connection wirings1125extending from the first semiconductor structure1100F to the second semiconductor structure1100S.

In the first semiconductor structure1100F, the decoder circuit1110and the page buffer1120may execute a control operation for at least one selection memory cell transistor of the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through input/output pads1101electrically connected to the logic circuit1130. The input/output pads1101may be electrically connected to the logic circuit1130through input/output connection wirings1135extending from the first semiconductor structure1100F to the second semiconductor structure1100S.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In an implementation, the data storage system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control a general operation of the data storage system1000including the controller1200. The processor1210may operate according to predetermined firmware, and may access the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221processing communications with the semiconductor device1100. A control command for controlling the semiconductor device1100, data to be written to the memory cell transistors MCT of the semiconductor device1100, data to be read from the memory cell transistors MCT of the semiconductor device1100, and the like, may be transmitted through the NAND interface1221. The host interface1230may provide a communications function between the data storage system1000and an external host. When a control command is received from the external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

FIG.9is a schematic perspective view of a data storage system including a semiconductor device according to an example embodiment.

Referring toFIG.9, a data storage system2000according to example embodiments may include a main board2001and a controller2002, one or more semiconductor packages2003, and a dynamic random access memory (DRAM)2004that are mounted on the main board2001. The semiconductor package2003and the DRAM2004may be connected to the controller2002by wiring patterns2005formed on the main board2001.

The main board2001may include a connector2006including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector2006may vary depending on a communications interface between the data storage system2000and the external host. In an implementation, the data storage system2000may communicate with the external host according to any one of interfaces such as universal serial bus (USB), peripheral component interconnect express (PCI-Express), serial advanced technology attachment (SATA), and M-PHY for universal flash storage (UFS). In an implementation, the data storage system2000may operate by power supplied from the external host through the connector2006. The data storage system2000may further include a power management integrated circuit (PMIC) distributing the power supplied from the external host to the controller2002and the semiconductor package2003.

The controller2002may write data to or read data from the semiconductor package2003, and may improve an operation speed of the data storage system2000.

The DRAM2004may be a buffer memory for alleviating a speed difference between the semiconductor package2003, which is a data storage space, and the external host. The DRAM2004included in the data storage system2000may operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package2003. When the data storage system2000includes the DRAM2004, the controller2002may further include a DRAM controller for controlling the DRAM2004, in addition to a NAND controller for controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bspaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be a semiconductor package including a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, the semiconductor chips2200on the package substrate2100, adhesive layers2300on lower surfaces of the semiconductor chips2200, connection structures2400electrically connecting the semiconductor chips2200to the package substrate2100, and a molding layer2500covering the semiconductor chips2200and the connection structures2400on the package substrate2100.

The package substrate2100may be a printed circuit board including package upper pads2130. Each semiconductor chip2200may include input/output pads2210. The input/output pads2210may correspond to the input/output pads1101ofFIG.8. Each of the semiconductor chips2200may include gate molded structures3210and channel structures3220. Each of the semiconductor chips2200may include the semiconductor device described above with reference toFIGS.1to7.

In an implementation, the connection structures2400may be bonding wires electrically connecting the input/output pads2210to the package upper pads2130. Accordingly, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other in a bonding wire manner, and be electrically connected to the package upper pads2130of the package substrate2100. In an implementation, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other by connection structures including through silicon vias (TSVs) instead of bonding wire-type connection structures2400.

In an implementation, the controller2002and the semiconductor chips2200may be included in one package. In an implementation, the controller2002and the semiconductor chips2200may be mounted on a separate interposer substrate different from the main board2001, and the controller2002and the semiconductor chips2200may be connected to each other by wirings formed on the interposer substrate.

FIG.10is a schematic cross-sectional view of a semiconductor package according to an example embodiment.FIG.10illustrates an example embodiment of the semiconductor package2003ofFIG.9, and conceptually illustrates a region of the semiconductor package2003taken along line II-II′ ofFIG.9.

Referring toFIG.10, in the semiconductor package2003, the package substrate2100may be a printed circuit board. The package substrate2100may include a package substrate body part2120, package upper pads2130(seeFIG.9) on an upper surface of the package substrate body part2120, package lower pads2125on or exposed through a lower surface of the package substrate body part2120, and internal wirings2135electrically connecting the package upper pads2130and the package lower pads2125to each other in the package substrate body part2120. The package upper pads2130may be electrically connected to the connection structures2400. The package lower pads2125may be connected to the wiring patterns2005of the main board2001of the data storage system2000as illustrated inFIG.9through conductive connection parts2800.

Each of the semiconductor chips2200may include a semiconductor substrate3010and a first semiconductor structure3100and a second semiconductor structure3200that are sequentially stacked on the semiconductor substrate3010. The first semiconductor structure3100may include a peripheral circuit region including peripheral wirings3110. The second semiconductor structure3200may include a common source line3205, a gate molded structure3210on the common source line3205, channel structures3220and isolation regions3230penetrating through the gate molded structure3210, bit lines3240electrically connected to the channel structures3220, and cell contact plugs electrically connected to word lines WL (seeFIG.8) of the gate molded structure3210. As described above with reference toFIGS.1to7, each of the semiconductor chips2200may include channel structures CH including a charge storage pattern141band a blocking pattern141c.

Each of the semiconductor chips2200may include through wirings3245electrically connected to the peripheral wirings3110of the first semiconductor structure3100and extending into the second semiconductor structure3200. The through wiring3245may be outside the gate molded structure3210, and may penetrate through the gate molded structure3210. Each of the semiconductor chips2200may further include input/output pads2210(seeFIG.9) electrically connected to the peripheral wirings3110of the first semiconductor structure3100.

FIG.11is a flowchart of a process sequence of a method of manufacturing a semiconductor device100according to example embodiments.FIGS.12A to16are cross-sectional views of stages in a method of manufacturing a semiconductor device100according to example embodiments.FIGS.12A,13A,14A,15, and16illustrate a region corresponding toFIG.2,FIG.12Billustrates a region corresponding to region ‘B’ ofFIG.12A,FIG.13Billustrates a region corresponding to region ‘C’ ofFIG.13A, andFIG.14Billustrates a region corresponding to region ‘D’ ofFIG.14A.

Referring toFIGS.11,12A, and12B, horizontal insulating layers110and a second horizontal conductive layer104may be sequentially formed on a substrate101, a first preliminary stack structure GS′ may be formed by alternately stacking first material layers118and second material layers120, and a preliminary channel dielectric layer141′ including a preliminary blocking pattern141c, a preliminary charge storage pattern141b, and a vertical tunneling layer141a, a channel layer140, a channel filling insulating layer144, and a channel pad145may be sequentially formed in a hole penetrating through the first preliminary stack structure GS′ (S10).

First, the horizontal insulating layers110and the second horizontal conductive layer104may be formed on the substrate101. The horizontal insulating layers110may include first to third horizontal insulating layers, and the first horizontal insulating layer and the third horizontal insulating layer may include the same material. The first horizontal insulating layer and the second horizontal insulating layer may include different materials. In an implementation, the first horizontal insulating layer and the third horizontal insulating layer may be formed of the same material as the interlayer insulating layers120, and the second horizontal insulating layer may be formed of the same material as the first material layers118. The horizontal insulating layers110may be layers of which some are replaced with the first horizontal conductive layer102(seeFIG.2) through a subsequent process. The lower structure may include the substrate101, the horizontal insulating layers110, and the second horizontal conductive layer104.

Next, the first preliminary stack structure GS′ including the first material layers118and the second material layers119alternately stacked in the Z-direction on the lower structure may be formed. In an implementation, the first preliminary stack structure GS′ may also be referred to as a molded structure. The first material layers118may be layers, at least some of which will be replaced by the gate layers130(seeFIG.2) through a subsequent process. The first material layers118may be formed of a material different from that of the second material layers119, and may be formed of a material that may be etched with etching selectivity with respect to the second material layers119under a specific etching condition. In an implementation, the first material layers118may include, e.g., a nitride, a silicon nitride, or a nitride material, and the second material layers119may include, e.g., silicon. The silicon may be, e.g., polysilicon. In an implementation, each of the first material layers118may have a first thicknessh1(e.g., in the Z direction), each of the second material layers119may have a second thicknessh2, and the first thicknessh1may be greater than the second thicknessh2. In example embodiments, the thicknesses of each of the first material layers118and the second material layers119may not all be the same as each other. In an implementation, the thicknesses of the first material layers118and the second material layers119and the number of films constituting the first material layers118and the second material layers119may be variously modified.

Next, a first upper insulating layer181covering the first preliminary stack structure GS′ on the substrate101may be formed, and a hole penetrating through the first upper insulating layer181and the molded structure GS′ may be formed. The hole may penetrate through the second horizontal conductive layer104and the horizontal insulating layers110together with the first preliminary stack structure GS′ and extend into the substrate101. In an implementation, the hole may not penetrate through the substrate101, and may be in contact with an upper surface of the substrate101. In an implementation, the hole may have a pillar shape having inclined side surfaces.

Next, the preliminary channel dielectric layer141′, the channel layer140, the channel filling insulating layer144, and the channel pad145may be sequentially formed in the hole. The preliminary channel dielectric layer141′ may be formed to have a uniform thickness by conformally covering an inner portion of the hole sequentially with the preliminary blocking pattern141c′, the preliminary charge storage pattern141b′, and the vertical tunneling layer141a. The channel layer140may be formed on the preliminary channel dielectric layer141′, and the channel filling insulating layer144may be formed to fill a space between the channel layers140and may be formed of an insulating material. In an implementation, the channel filling insulating layer144may fill the space between the channel layers140with a conductive material. The channel pad145may be made of a conductive material such as polycrystalline silicon. The preliminary charge storage pattern141b′ may include, e.g., a nitride, a silicon nitride, or a nitride material. The preliminary charge storage pattern141b′ may be etched together with the first material layers118under a specific etching condition, and may have an etch rate slower than that of the first material layers118under the specific etching condition. The preliminary charge storage pattern141b′ may include the same material as the first material layers118, and may have a composition ratio different from that of the first material layers118.

Referring toFIGS.11,13A, and13B, trenches OP penetrating through the first preliminary stack structure GS′ may be formed, first tunnel parts LT1may be formed by removing the second material layers119through the trenches OP, and the blocking pattern141cmay be formed by removing at least a portion of the preliminary blocking pattern141c′ through the first tunnel parts LT1(S20).

First, a second upper insulating layer182covering the first upper insulating layer181and the channel pad145may be formed, and the trenches OP penetrating through the first preliminary stack structure GS′ and the first and second upper insulating layers181and182may be formed in regions corresponding to the isolation structures MS (seeFIGS.1and2). The trenches OP may be formed to penetrate through the second horizontal conductive layer104and to extend in the X-direction.

In an implementation, the second horizontal insulating layer may be exposed by an etch-back process while forming separate sacrificial spacer layers in the trenches OP, through which the horizontal insulating layer110may be removed. In a process of removing the horizontal insulating layer110, a portion of the vertical tunneling layer141aexposed in a region from which the horizontal insulating layers110are removed may also be removed together with the horizontal insulating layer110. The first horizontal conductive layer102may be formed by depositing a conductive material in the region in the horizontal insulating layer110has been removed, and the sacrificial spacer layers may then be removed in the trenches OP.

Next, the first tunnel parts LT1may be formed by removing the second material layers119exposed through the trenches OP. The second material layers119may be selectively etched with respect to the first material layers118under a specific etching condition. The second material layers119may be removed through, e.g., a wet etching process. A thickness of each of the first tunnel parts LT1may be substantially the same as the second thicknessh2of each of the second material layers119.

Next, the blocking pattern141cmay be formed by removing at least a portion of the preliminary blocking pattern141c′ exposed through the first tunnel parts LT1. The blocking pattern141c, including a plurality of blocking material layers141c-1and141c-2spaced apart from each other in the Z-direction, may be formed through a wet etching process for the preliminary blocking pattern141c′.

Referring toFIGS.11,14A, and14B, the charge storage pattern141bincluding the plurality of charge storage material layers141b-1and141b-2spaced apart from each other in the Z-direction may be formed by removing at least a portion of the preliminary charge storage pattern141b′ exposed by the removed preliminary blocking pattern141c′ (S30).

A portion of the preliminary charge storage pattern141b′ may be removed by an etching process such as a wet etching process. The etching process may include a process of removing portions of the first material layers118together with a portion of the preliminary charge storage pattern141b.′ In an implementation, the etching process may be a process of selectively etching the preliminary charge storage pattern141b′ and the first material layers118with respect to the blocking pattern141c. Accordingly, a third thicknessh3of each of the first material layers118remaining through or after the etching process may be smaller than the existing first thicknessh1(seeFIGS.12A and12B) and a fourth thicknessh4of each of the expanded first tunnel parts LT1may be greater than the second thicknessh2(seeFIGS.12A and12B) of each of the second material layers119. The first material layers118may include a material having an etch rate faster than that the preliminary charge storage pattern141b′ in the etching process. Accordingly, a thickness T1of the material of the first material layers118removed in the vertical direction may be greater than a thickness T2of the material of the preliminary charge storage pattern141b′ removed in the vertical direction. In an implementation, the third thicknessh3of each of the first material layers118remaining through or after the etching process may be smaller than a length of each of the plurality of charge storage material layers141b-1and141b-2in the Z-direction.

The charge storage pattern141bmay be formed by partially removing the preliminary charge storage pattern141b′, such that the channel dielectric layer141including the vertical tunneling layer141a, the charge storage pattern141b, and the blocking pattern141cmay be formed.

Referring toFIGS.11and15, interlayer insulating layers120may be formed through the first tunnel parts LT1(S40).

The interlayer insulating layers120may be formed by filling insulating materials between the first material layers118, between the plurality of charge storage material layers141b-1and141b-2, and between the plurality of blocking material layers141c-1and141c-2through the trenches OP and the first tunnel parts LT1and removing the insulating materials filled in the trenches OP. Accordingly, a second preliminary stack structure GS” in which the interlayer insulating layers120and the first material layers are alternately stacked may be formed. The interlayer insulating layers120may include, e.g., an oxide, a silicon oxide, or an oxide material.

Referring toFIGS.11and16, gate layers130may be formed through second tunnel parts formed by selectively removing the first material layers118exposed through the trenches OP (S50).

The first material layers118may be selectively removed with respect to the interlayer insulating layers120using, e.g., a wet etching process. Accordingly, the second tunnel parts may be formed between the interlayer insulating layers120. Gate dielectric layers132may be formed by depositing dielectric materials having a uniform thickness while covering the interlayer insulating layers120and the blocking pattern141cin the second tunnel parts, and gate conductive layers131may be formed by filling conductive materials between the gate dielectric layers132. The conductive material may include a metal, polycrystalline silicon, or a metal silicide material. Accordingly, a stack structure GS in which the gate layers130respectively including the gate dielectric layer132and the gate conductive layer131and the interlayer insulating layers120are alternately stacked may be formed.

Next, isolation structures MS may be formed by removing the dielectric materials and the conductive materials deposited in the trenches OP through an additional process and then filling insulating materials in the trenches OP.

Next, the semiconductor device100ofFIG.2may be formed by forming a third upper insulating layer183(seeFIG.2) covering the isolation structures MS and the second upper insulating layer182and forming upper contact structures191penetrating through the second and third upper insulating layers182and183and in contact with the channel pads145and upper wiring patterns192on the upper contact structures191.

By way of summation and review, increasing a data storage capacity of a semiconductor device has been considered. For example, a semiconductor device may include three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells.

The semiconductor device according to an embodiment may exhibit improved electrical characteristics, e.g., because a thickness of each of the plurality of charge storage material layers spaced apart from each other may be relatively greater than the thickness of each of the gate layers.

One or more embodiments may provide a semiconductor device of which electrical characteristics are improved.

One or more embodiments may provide a method of manufacturing a semiconductor device of which electrical characteristics are improved.