Fabrication of capacitors with low voltage coefficient of capacitance

A method of fabricating of a capacitor with low voltage coefficient of capacitance is described. A silicon substrate with field oxide isolations is provided. A buried layer is formed by doping N-type impurities into the substrate as the bottom plate of the capacitor. A dielectric layer is formed by thermal oxidation for the capacitor, and then a polysilicon layer is formed by the low pressure chemical vapor deposition method. A thermal diffusion step is performed to dope phosphorus into the polysilicon layer. After formation of a polysilicide layer by the low pressure chemical vapor deposition method, arsenic ions are implanted into the polysilicon layer and the polysilicide layer. Finally the polysilicide layer and the polysilicon layer are partially etched in consequence, and the top plate of the capacitor is formed.

BACKGROUND OF THE INVENTION 
(1) Field of the Invention 
The present invention relates to a method of fabricating capacitors of 
integrated circuits, and more particularly to the buried 
N+silicon-to-polysilicide capacitors with low voltage coefficient of 
capacitance(hereinafter referred as VCC) of high density ICs. 
(2) Description of the Related Art 
A mixed-mode circuit includes logic circuits and analog circuits. A 
capacitor is one of the most important devices in the mixed-mode circuit 
and the voltage coefficient of capacitance is a key parameter to determine 
the operation performance of a capacitor. For the actual application to 
the IC manufacture, the VCC value is generally demanded to be less than 
100 ppm/V. 
The definition of the voltage coefficient of capacitance is the partial 
derivative of capacitance relative to voltage per standard capacitance. 
Please refer to the following formula: 
##EQU1## 
For the early mixed-mode process, the VCC values of obtained capacitors are 
generally less than 50 ppm/V, and match the specification of IC 
manufacturers. However, in recent years, the cell amount of ICs has been 
enhanced significantly, and the packing densities of ICs have been 
increasing considerably. In order to achieve high packing density, the 
cell sizes of ICs cell must be shrunk. As the sizes of the capacitors 
become smaller, the capacitance values of the capacitors are decreasing 
and the VCC values are dramatically increasing, causing the performance 
problem. 
FIG. 1 shows a cross-sectional view of a conventional buried 
N+silicon-to-polysilicide capacitor. The process steps are briefly 
described as follows: A silicon substrate 1 with field oxide isolations 2 
is provided. A buried layer 5 is formed by doping N-type impurities into 
the substrate 1 as the bottom plate of the capacitor. A dielectric layer 6 
is then formed by thermal oxidation for the capacitor, and then a 
polysilicon layer 7 and a polysilicide layer 8 are formed by the low 
pressure chemical vapor deposition (LPCVD) method in consequence. Finally 
the polysilicide layer 8 and the polysilicon layer 7 are partially etched 
in consequence, and then the top plate 9 of the capacitor is formed. 
The wafer numbers 1-3 of FIG. 2a show the capacitors formed by the 
conventional process with plate size 100*100 .mu.m.sup.2 having VCC values 
between 132 and 334 ppm/V, all of which are much higher than the 
application standard value 100 ppm/V. The wafer numbers 1-3 of FIG. 2b 
show the capacitors formed by the conventional process with plate size 
40*40 .mu.m.sup.2 having VCC values between 148 and 2538 ppm/V, which are 
also much higher than the application standard value 100 ppm/V. 
The present invention discloses a new method to fabricate a buried 
N+silicon-to-polysilicide capacitor with low voltage coefficient of 
capacitance. 
SUMMARY OF THE INVENTION 
Accordingly, it is a primary object of the present invention to provide a 
method of fabricating a buried N+silicon-to-polysilicide capacitor with 
low voltage coefficient of capacitance(VCC). 
It is another object of the present invention to provide a capacitor 
structure with low VCC for mixed mode IC applications. 
In accordance with the objects of this invention, there is shown a method 
of fabricating a IC's capacitor. A silicon substrate, having field oxide 
isolations which define a capacitor region, is provided. A buried 
conducting layer is formed by doping N-type impurities into the substrate 
as the bottom plate of the capacitor. A dielectric layer is formed by 
thermal oxidation for the capacitor, and then a polysilicon layer is 
formed by the low pressure chemical vapor deposition method. Thereafter, a 
thermal diffusion step is performed to dope phosphorus into the 
polysilicon layer at a temperature range from 800.degree. C. to 
950.degree. C. After forming of a polysilicide layer by the low pressure 
chemical vapor deposition method, arsenic ions are then implanted into the 
polysilicon layer and the polysilicide layer, in order to increase the 
dopant concentration of the capacitor's top plate and thus lower the VCC 
value of the capacitor. Finally the polysilicide layer and the polysilicon 
layer are partially etched in consequence, and the top plate of the 
capacitor is formed.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring now in detail to the drawings for the purpose of illustrating 
preferred embodiments of the present invention, the process for 
fabricating capacitors with low voltage coefficient as shown in FIGS. 3 to 
8 comprises the following steps: 
FIG. 3 shows a forming step of a buried layer in a silicon substrate 1 as 
the bottom plate of a capacitor. A silicon substrate, having field oxide 
isolation, is provided. A photo resist 3 is spread and then a capacitor 
region is defined. Thereafter, N-type ions 4 such as arsenic are implanted 
into the substrate at an energy level from 60 keV to 120 keV, and a dose 
in the range from 2E14 cm.sup.-2 to 5E15 cm.sup.-2, and the bottom plate 
of the capacitor is formed. 
FIG. 4 shows a forming step of a dielectric layer 6 on said silicon 
substrate 1 for the capacitor. The dielectric layer is formed to a 
thickness of about 100-750 Angstroms by thermal oxidation at a temperature 
range from 750.degree. C. to 950.degree. C. 
FIG. 5 shows a depositing step of a polysilicon layer 7 on the dielectric 
layer 6. The polysilicon layer is formed to a thickness of about 1000-2500 
Angstroms by the low pressure chemical vapor deposition method. 
Thereafter, a thermal diffusion step is performed to dope phosphorus into 
the polysilicon layer at a temperature range from 800.degree. C. to 
950.degree. C. 
The purpose of the thermal diffusion is to lower the sheet resistance of 
the polysilicon layer 7, and the higher the dose, the lower the sheet 
resistance of the polysilicon is. The dose of the thermal diffusion is 
controlled to obtain the sheet resistance of the polysilicon layer 7 in a 
range of 30.OMEGA. per square to 50.OMEGA. per square. 
FIG. 6 shows a depositing step of a polysilicide layer 8 on the polysilicon 
layer 7. The polysilicide layer 8 is formed to a thickness of about 
1500-2500 Angstroms by the low pressure chemical vapor deposition method. 
The polysilicon layer 7 and the polysilicide layer 8 are prepared for 
being patterned as the top plate of the capacitor. The purpose of the 
polysilicide layer is to lower the resistance of the capacitor's top 
plate. 
FIG. 7 shows a doping step, the most importance step of the present 
invention. Arsenic ions 4a are implanted into the polysilicon layer and 
the polysilicide layer at an energy level from 60 keV to 120 keV, and a 
dose in a range from 5E15 cm.sup.-2 to 1E16cm.sup.-2. The purpose of this 
step is to increase the dopant concentration of the capacitor's top plate 
and thus lower the VCC of the capacitor. 
FIG. 8 shows a patterning step of the top plate 9 of the capacitor. After 
the capacitor region is defined, the polysilicide layer 8 and the 
polysilicon layer 7 are etched in consequence except the capacitor region. 
The different VCC performances between the conventional art and the present 
invention are shown in FIG. 2a and FIG. 2b. FIG. 2a shows the VCC values 
of capacitors with plate size 100*100 .mu.m.sup.2. The wafer numbers 1-3 
of FIG. 2a are formed by using the conventional art and the wafer numbers 
4-6 are formed by the process according to the present invention. As shown 
in FIG. 2a, the VCC values of capacitors formed by using the conventional 
art are between 132 and 334 ppm/V, but the VCC values of capacitors formed 
by the process according to the present invention are only between 23 and 
28 ppm/V. FIG. 2b shows the VCC values of capacitors with plate size 40*40 
.mu.m.sup.2. The wafer numbers 1-3 of FIG. 2b are formed by using the 
conventional art and wafer numbers 4-6 are formed by using by the present 
invention. As shown in FIG. 2b, the VCC values of capacitors formed by 
using the conventional art are between 148 and 2538 ppm/V, while the VCC 
values of capacitors formed by using the present invention are only 
between 42 and 85 ppm/V. 
Therefore, as shown in FIG. 2a and FIG. 2b, the present invention makes a 
great improvement about the performance of the capacitors, whose VCC 
values are much lower than the standard value 100 ppm/V. 
The invention being thus described, it will be obvious that the same may be 
varied in many ways. Such variations are not to be regarded as a departure 
from the spirit and scope of the invention, and all such modifications as 
would be obvious to one skilled in the art are intended to be included in 
the scope of the following claims.