NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE

A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer, a gate electrode, an insulation layer covering the electron supply layer, the gate layer, and the gate electrode and including a first opening and a second opening, a source electrode, and a drain electrode. The source electrode includes a source field plate covering the insulation layer and including an end located between the second opening and the gate layer in plan view. The insulation layer includes a first insulation layer part and a second insulation layer part. The first insulation layer part is disposed on the electron supply layer in contact with the drain electrode and has a first thickness. The second insulation layer part is disposed on the gate electrode in contact with the source field plate and has a second thickness. The second thickness is greater than the first thickness.

BACKGROUND

The following description relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

2. Description of Related Art

In recent years, a high electron mobility transistor (hereafter referred to as HEMT) that uses a nitride semiconductor as the main material of an active region has been developed and applied to a power device. The nitride semiconductor is a semiconductor that includes nitrogen as a group V element in a group III-V semiconductor. As compared to a typical silicon carbide (SiC) power device, a power device that uses a nitride semiconductor is recognized as a device having a low on-resistance property, which is similar to the SiC power device, and capable of operating at higher speeds and higher frequencies than the SiC power device.

Japanese Laid-Open Patent Publication No. 2017-73506 discloses an example of a HEMT including a gate portion that includes a GaN layer (p-type GaN layer) containing an acceptor impurity and a gate electrode formed on the p-type GaN layer.

DETAILED DESCRIPTION

Embodiments of a nitride semiconductor device according to the present disclosure will be described below with reference to the drawings.

First Embodiment

FIG.1is a schematic cross-sectional view showing an exemplary nitride semiconductor device10of a first embodiment. The term “plan view” used in the present disclosure refers to a view of the nitride semiconductor device10in the Z-axis direction when the XYZ-axes are orthogonal to each other as shown inFIG.1. In the nitride semiconductor device10shown inFIG.1, the +Z direction defines the upper side, and the −Z direction defines the lower side. The +X direction defines the right, and the −X direction defines the left. Unless otherwise specified, “plan view” refers to a view of the nitride semiconductor device10taken from above along the Z-axis.

The nitride semiconductor device10is a high electron mobility transistor (HEMT) that uses a nitride semiconductor. The nitride semiconductor device10includes a substrate12, a buffer layer14formed on the substrate12, an electron transit layer16formed on the buffer layer14, and an electron supply layer18formed on the electron transit layer16.

In an example, a silicon (Si) substrate is used as the substrate12. Alternatively, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a sapphire substrate may be used instead of the Si substrate. The thickness of the substrate12may be, for example, greater than or equal to 200 μm and less than or equal to 1500 μm. The term “thickness” in the following description refers to a dimension extending in the z-direction shown inFIG.1unless otherwise specifically described.

The buffer layer14may be disposed between the substrate12and the electron transit layer16and may be formed of any material that reduces the lattice mismatching between the substrate12and the electron transit layer16. The buffer layer14may include one or more nitride semiconductor layers, for example, at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer including a different aluminum (Al) composition. In an example, the buffer layer14may be composed of a single film of AlN, a single film of AlGaN, a film having a superlattice structure of AlGaN/GaN, a film having a superlattice structure of AlN/AlGaN, or a film having a superlattice structure of AlN/GaN.

In an example, the buffer layer14may include a first buffer layer, which is an AlN layer formed on the substrate12, and a second buffer layer, which is an AlGaN formed on the AlN layer. In an example, the first buffer layer may be an AlN layer having a thickness of 200 nm. In an example, the second buffer layer may be an AlGaN layer having a thickness of 100 nm. To inhibit current leakage from the buffer layer14, a portion of the buffer layer14may be doped with an impurity so that the buffer layer14excluding an outer layer region is semi-insulating. In this case, the impurity is, for example, carbon (C) or iron (Fe). The concentration of the impurity may be, for example, greater than or equal to 4×1016cm−3.

The electron transit layer16is composed of a nitride semiconductor and may be, for example, a GaN layer. The electron transit layer16may have a thickness that is, for example, greater than or equal to 0.5 μm and less than or equal to 2 μm. To inhibit current leakage from the electron transit layer16, a portion of the electron transit layer16may be doped with an impurity so that the electron transit layer16excluding an outer layer region is semi-insulating. In this case, the impurity is, for example, C. The concentration of the impurity is, for example, greater than or equal to 4×1016cm−3. More specifically, the electron transit layer16may include GaN layers having different impurity concentrations, for example, a C-doped GaN layer and a non-doped GaN layer. In this case, the C-doped GaN layer may be formed on the buffer layer14and have a thickness of greater than or equal to 0.5 μm and less than or equal to 2 μm. The C concentration in the C-doped GaN layer may be greater than or equal to 5×1017cm−3and less than or equal to 5×1019cm−3. The non-doped GaN layer may be formed on the C-doped GaN layer and have a thickness of greater than or equal to 0.05 μm and less than or equal to 0.3 μm. The non-doped GaN layer is in contact with the electron supply layer18. In an example, the electron transit layer16includes a non-doped GaN layer having a thickness of 0.1 μm and a C-doped GaN layer having a thickness of 0.911 m. The concentration of C in the C-doped GaN layer is approximately 1×1018cm−3.

The electron supply layer18is composed of a nitride semiconductor having a band gap that is larger than that of the electron transit layer16and may be, for example, an AlGaN layer. In the nitride semiconductor, the band gap becomes larger as the composition of Al is increased. Therefore, the electron supply layer18, which is an AlGaN layer, has a larger band gap than the electron transit layer16, which is a GaN layer. In an example, the electron supply layer18is composed of AlxGa1-xN, where 0<x<0.4, and more preferably, 0.1<x<0.3. The electron supply layer18may have a thickness of, for example, greater than or equal to 5 nm and less than or equal to 20 nm.

The electron transit layer16and the electron supply layer18have different lattice constants in a bulk region. This results in the lattice mismatching between the electron transit layer16and the electron supply layer18. In the vicinity of the heterojunction interface between the electron transit layer16and the electron supply layer18, the energy level in the conduction band of the electron transit layer16is lower than the Fermi level due to spontaneous polarization of the electron transit layer16and the electron supply layer18and piezoelectric polarization caused by compressive stress received by a heterojunction of the electron supply layer18. As a result, at a location close to the heterojunction interface between the electron transit layer16and the electron supply layer18(for example, approximately a few nanometers away from the interface), two-dimensional electron gas20(2DEG) spreads in the electron transit layer16.

The nitride semiconductor device10further includes a gate layer22formed on the electron supply layer18and a gate electrode24formed on the gate layer22.

The gate layer22, formed on the electron supply layer18, is formed from a nitride semiconductor having a band gap that is smaller than that of the electron supply layer18and including an acceptor impurity. The gate layer22may be formed of any material having a band gap that is smaller than that of the electron supply layer18, which is, for example, an AlGaN layer. In an example, the gate layer22is a GaN layer (p-type GaN layer) doped with an acceptor impurity. The acceptor impurity may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor impurity in the gate layer22is, for example, greater than or equal to 1×1018cm−3and less than or equal to 1×1020cm−3. The gate layer22may have, for example, a thickness of greater than or equal to 80 nm and less than or equal to 150 nm and have a cross section that is rectangular, trapezoidal, or, ridged.

As described above, the acceptor impurity included in the gate layer22increases the energy levels of the electron transit layer16and the electron supply layer18. As a result, in a region immediately below the gate layer22, the energy level of the conduction band of the electron transit layer16in the vicinity of the heterojunction interface between the electron transit layer16and the electron supply layer18is substantially equal to or greater than the Fermi level. Therefore, when no voltage is applied to the gate electrode24, that is, in the zero bias state, the 2DEG20is not formed in the electron transit layer16in the region immediately below the gate layer22. On the other hand, in a region other than the region immediately below the gate layer22, the 2DEG20is formed in the electron transit layer16.

As described above, when the gate layer22is doped with the acceptor impurity, the 2DEG20is depleted in the region immediately below the gate layer22. As a result, the nitride semiconductor device10performs a normally-off operation. When an appropriate on-voltage is applied to the gate electrode24, the 2DEG20forms a channel in the electron transit layer16in the region immediately below the gate electrode24. This electrically connects the source and the drain.

The gate electrode24is formed on the gate layer22. The gate electrode24includes a lower surface24A (first surface) in contact with the gate layer22, an upper surface24B (second surface) opposite to the lower surface24A, and a side surface24C (third surface) extending between the lower surface24A and the upper surface24B. The gate electrode24is composed of one or more metal layers, an example of which is a titanium nitride (TiN) layer. Alternatively, the gate electrode24may include a first metal layer composed of Ti and a second metal layer composed of TiN and disposed on the first metal layer. The gate electrode24may have a thickness that is, for example, greater than or equal to 50 nm and less than or equal to 200 nm. The gate electrode24may form a Schottky junction with the gate layer22.

The nitride semiconductor device10further includes an insulation layer26, a source electrode28, and a drain electrode30. The insulation layer26covers the electron supply layer18, the gate layer22, and the gate electrode24and includes a first opening26A and a second opening26B. The first opening26A and the second opening26B are separated from the gate layer22. The gate layer22is located between the first opening26A and the second opening26B. More specifically, the gate layer22is located closer to the first opening26A than the second opening26B between the first opening26A and the second opening26B. The source electrode28is in contact with the electron supply layer18through the first opening26A. The drain electrode30is in contact with the electron supply layer18through the second opening26B.

The source electrode28and the drain electrode30are composed of one or more metal layers (for example, Ti, Al, TiN). The source electrode28and the drain electrode30are each in ohmic contact with the electron supply layer18through the first opening26A and the second opening26B.

The source electrode28includes a source contact28A and a source field plate28B continuous with the source contact28A. The source contact28A corresponds to a portion of the source electrode28filling the first opening26A. The source field plate28B is formed integrally with the source contact28A. The source field plate28B covers the insulation layer26and includes an end28C located between the second opening26B and the gate layer22in plan view. Thus, the source field plate28B is separated from the drain electrode30, which is formed in the second opening26B. The source field plate28B extends from the source contact28A to the end28C along the surface of the insulation layer26toward the drain electrode30. The insulation layer26covers the upper surface of the electron supply layer18, the side surface and the upper surface of the gate layer22, the side surface24C and the upper surface24B of the gate electrode24. Therefore, the source field plate28B, which extends along the surface of the insulation layer26, has a non-flat surface. When no gate voltage is applied to the gate electrode24, that is, in the zero bias state, the source field plate28B reduces the concentration of electric field in the vicinity of the end of the gate electrode24.

The insulation layer26includes a first insulation layer part26P1having a first thickness D1and a second insulation layer part26P2having a second thickness D2.

The first insulation layer part26P1is disposed on the electron supply layer18in contact with the drain electrode30. The first insulation layer part26P1corresponds to a part of the insulation layer26having the first thickness D1, which is a constant thickness, between the gate layer22and the drain electrode30. The first insulation layer part26P1is partially covered by the source field plate28B. More specifically, a portion of the first insulation layer part26P1located toward the gate layer22is covered by the source field plate28B. Therefore, the end28C of the source field plate28B is located on the first insulation layer part26P1. In other words, the first insulation layer part26P1is a part of the insulation layer26on which the end28C of the source field plate28B is disposed.

The second insulation layer part26P2is disposed on the gate electrode24in contact with the source field plate28B. The second insulation layer part26P2corresponds to a part of the insulation layer26disposed on the gate electrode24and having the second thickness D2, which is a constant thickness. The second insulation layer part26P2is entirely covered by the source field plate28B.

The second thickness D2of the second insulation layer part26P2is greater than the first thickness D1of the first insulation layer part26P1. The second thickness D2may be greater than or equal to 1.2 times the first thickness D1and less than or equal to 5.0 times the first thickness D1. The first thickness D1may be greater than or equal to 50 nm and less than or equal to 200 nm. The second thickness D2may be greater than or equal to 100 nm and less than or equal to 400 nm.

The first thickness D1is a thickness of the insulation layer26where the end28C of the source field plate28B is located in plan view. In other words, the first thickness D1is a distance between the electron supply layer18and the source electrode28where the end28C of the source field plate28B is located in plan view. The second thickness D2is a distance between the gate electrode24and the source electrode28in a region of the gate electrode24in plan view. Thus, an increase in the second thickness D2decreases the gate-source capacitance Cgs.

Theoretically, as the second thickness D2is increased, the gate-source capacitance Cgscan be decreased more. However, when the nitride semiconductor device10is used to form a circuit, if the ratio (input capacitance Ciss/feedback capacitance Crss) of input capacitance Ciss(=gate-drain capacitance Cgd+gate-source capacitance Cgs) to feedback capacitance Crss(=gate-drain capacitance Cgd) becomes smaller than a certain value (for example, 100), a self-turn-on phenomenon may occur, resulting in shoot-through current. Therefore, the second thickness D2may be set in a range so that the ratio of input capacitance Cissto feedback capacitance Crsswill not become below a value (for example, 150) determined in accordance with the circuit design.

The insulation layer26includes a spacer layer32, formed on the gate electrode24, and a passivation layer34covering the electron supply layer18, the gate layer22, the gate electrode24, and the spacer layer32. The passivation layer34includes a first opening34A and a second opening34B.

The first opening34A and the second opening34B of the passivation layer34respectively correspond to the first opening26A and the second opening26B of the insulation layer26. The first insulation layer part26P1is formed of the passivation layer34. The second insulation layer part26P2is formed of the spacer layer32and the passivation layer34. For the sake of brevity, the part of the passivation layer34forming the first insulation layer part26P1is referred to as a first passivation layer part34P1. Also, a part of the passivation layer34disposed on the spacer layer32forming the second insulation layer part26P2together with the spacer layer32is referred to as a second passivation layer part34P2.

The spacer layer32may be composed of, for example, one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In an example, the spacer layer32is composed of SiO2. As shown inFIG.1, the spacer layer32has a third thickness D3. The spacer layer32disposed on the gate electrode24increases the distance between the gate electrode24and the source electrode28in the z-direction. This decreases the gate-source capacitance Cgs.

The passivation layer34may be composed of, for example, one of SiN, SiO2, SiON, Al2O3, AlN, and AlON. In an example, the passivation layer34is composed of SiN. The passivation layer34may serve as a protection film.

As shown inFIG.1, the passivation layer34has the first thickness D1in the first insulation layer part26P1and a fourth thickness D4in the second insulation layer part26P2. In other words, the first passivation layer part34P1has the first thickness D1. The second passivation layer part34P2has the fourth thickness D4. In the present embodiment, the first thickness D1is substantially equal to the fourth thickness D4. In this specification, “substantially equal” means that the difference is within a manufacturing variation range (for example, 20%).

As described above, in the second insulation layer part26P2, the spacer layer32has the third thickness D3, and the passivation layer34has the fourth thickness D4. Thus, the second thickness D2of the second insulation layer part26P2is the sum of the third thickness D3and the fourth thickness D4. In addition to the passivation layer34, the spacer layer32increases the second thickness D2. This decreases the gate-source capacitance Cgs.

FIG.2is a schematic plan view showing an exemplary pattern100formed in the nitride semiconductor device10shown inFIG.1. To facilitate understanding, inFIG.2, the same reference characters are given to those components that are the same as the corresponding components shown inFIG.1. Also, inFIG.2, the source electrode28, the drain electrode30, and the passivation layer34are transparently shown so that components of layers underneath (for example, the spacer layer32and the gate layer22) are visible. The source electrode28and the drain electrode30are shown by broken lines indicating only the outer edges. In the passivation layer34, only the first opening34A and the second opening34B (corresponding to the first opening26A and the second opening26B of the insulation layer26) are shown.

As shown inFIG.2, the pattern100includes active regions102that contribute to operation of the transistor and inactive regions104that do not contribute to operation of the transistor. The active region102refers to a region in which, when voltage is applied to the gate electrode24, current flows between the source and the drain.

In the active region102, multiple (in the example shown inFIG.2, four) nitride semiconductor devices are continuously formed in an X-axis direction. Each nitride semiconductor device shown inFIG.2corresponds to the nitride semiconductor device10shown inFIG.1. More specifically, the cross-sectional view shown inFIG.1corresponds to a cross-sectional view of the pattern100in the active region102enlarging a portion including one nitride semiconductor device (including gate electrode, and source electrode and drain electrode associated with the gate electrode). In the active region102, the source field plate28B of the source electrode28includes the end28C located between the second opening34B (corresponding to the second opening26B) and the gate layer22. The drain electrode30is formed in the second opening34B. The drain electrode30is not formed in the inactive region104.

As shown inFIG.2, the gate layer22, the spacer layer32, and the source electrode28are continuously formed over the active region102and the inactive region104in the Y-axis direction.

An example of a method for manufacturing the nitride semiconductor device10shown inFIG.1will be described.

FIGS.3to7are schematic cross-sectional views showing exemplary manufacturing steps of the nitride semiconductor device10. To facilitate understanding, inFIGS.3to7, the same reference characters are given to those components that are the same as the corresponding components shown inFIG.1. Elements that will ultimately become the elements of the nitride semiconductor device10are denoted by the corresponding reference characters shown inFIG.1in parentheses.

A method for manufacturing the nitride semiconductor device10includes forming the electron transit layer16composed of a nitride semiconductor, forming the electron supply layer18on the electron transit layer16, the electron supply layer18being composed of a nitride semiconductor having a band gap that is larger than that of the electron transit layer16, forming the gate layer22on the electron supply layer18, the gate layer22composed of a nitride semiconductor including an acceptor impurity, forming the gate electrode24on the gate layer22, and forming the insulation layer26(refer toFIG.1) that covers the electron supply layer18, the gate layer22, and the gate electrode24and includes the first opening26A and the second opening26B. The forming the insulation layer26includes forming the spacer layer32on the gate electrode24and forming the passivation layer34that covers the electron supply layer18, the gate layer22, the gate electrode24, and the spacer layer32and includes the first opening34A and the second opening34B. The first opening34A and the second opening34B of the passivation layer34respectively correspond to the first opening26A and the second opening26B of the insulation layer26.

As shown inFIG.3, for example, the buffer layer14, the electron transit layer16, the electron supply layer18, a nitride semiconductor layer52, a metal layer54, and a spacer insulation layer56are sequentially formed on the substrate12, which is a Si substrate.

Metal organic chemical vapor deposition (MOCVD) may be used to epitaxially grow the buffer layer14, the electron transit layer16, the electron supply layer18, and the nitride semiconductor layer52.

Although not shown in detail, in an example, the buffer layer14is multilayer. An AlN layer (the first buffer layer) is formed on the substrate12, and then a graded AlGaN layer (the second buffer layer) is formed on the AlN layer. The graded AlGaN layer is formed, for example, by stacking three AlGaN layers having Al compositions of 75%, 50%, and 25% in the order from the side of the AlN layer.

A GaN layer is formed on the buffer layer14as the electron transit layer16. An AlGaN layer is formed on the electron transit layer16as the electron supply layer18. Thus, the electron supply layer18has a band gap that is larger than that of the electron transit layer16. Then, a GaN layer including an acceptor impurity is formed on the electron supply layer18as the nitride semiconductor layer52.

The buffer layer14, the electron transit layer16, the electron supply layer18, and the nitride semiconductor layer52are composed of nitride semiconductors having lattice constants relatively close to each other. This allows for sequential epitaxial growth of the layers.

Subsequently, the metal layer54is formed on the nitride semiconductor layer52. In an example, the metal layer54is a TiN layer formed through sputtering. Then, the spacer insulation layer56is formed on the metal layer54. In an example, the spacer insulation layer56is a SiO2layer formed by plasma CVD.

FIG.4is a schematic cross-sectional view showing a manufacturing step subsequent toFIG.3. As shown inFIG.4, the metal layer54and the spacer insulation layer56are selectively removed by lithography and etching to form the gate electrode24and the spacer layer32.

FIG.5is a schematic cross-sectional view showing a manufacturing step subsequent toFIG.4. As shown inFIG.5, the nitride semiconductor layer52is selectively removed by lithography and etching to form the gate layer22. As a result, a stacking structure including the gate layer22, the gate electrode24formed on the gate layer22, and the spacer layer32formed on the gate electrode24is formed on a portion of the upper surface of the electron supply layer18.

FIG.6is a schematic cross-sectional view showing a manufacturing step subsequent toFIG.5. As shown inFIG.6, a passivation insulation layer58is formed to cover the entirety of exposed surfaces of the electron supply layer18, the gate layer22, the gate electrode24, and the spacer layer32. In an example, the passivation insulation layer58is a SiN layer formed by low-pressure chemical vapor deposition (LPCVD). The passivation insulation layer58may have a thickness that is greater than or equal to 50 nm and less than or equal to 200 nm.

FIG.7is a schematic cross-sectional view showing a manufacturing step subsequent toFIG.6. As shown inFIG.7, the passivation insulation layer58is selectively removed by lithography and etching to form the passivation layer34including the first opening34A and the second opening34B. More specifically, the passivation insulation layer58is patterned so that the gate layer22is disposed between the first opening34A and the second opening34B. The passivation layer34covers the electron supply layer18, the gate layer22, the gate electrode24, and the spacer layer32and includes the first opening34A and the second opening34B. The insulation layer26is defined to include the spacer layer32and the passivation layer34. The first opening34A and the second opening34B of the passivation layer34respectively correspond to the first opening26A and the second opening26B of the insulation layer26.

The method for manufacturing the nitride semiconductor device10further includes forming the source electrode28(refer toFIG.1), which is in contact with the electron supply layer18through the first opening26A, and forming the drain electrode30(refer toFIG.1), which is in contact with the electron supply layer18through the second opening26B.

In a manufacturing step subsequent to the step shown inFIG.7, a metal layer is formed to fill the first opening26A and the second opening26B and cover the entirety of exposed surfaces of the passivation layer34(the insulation layer26). The metal layer (e.g., one or more metal layers including Ti, Al, TiN, and the like) is patterned by lithography and etching to form the source electrode28and the drain electrode30. The source electrode28includes the source field plate28B covering the insulation layer26. The source field plate28B includes the end28C located between the second opening26B and the gate layer22in plan view. This obtains the nitride semiconductor device10shown inFIG.1.

The operation of the nitride semiconductor device10of the present embodiment will be described below.

In the nitride semiconductor device10, the insulation layer26includes the first insulation layer part26P1having the first thickness D1and the second insulation layer part26P2having the second thickness D2that is greater than the first thickness D1. The second thickness D2corresponds to the distance between the gate electrode24and the source electrode28in a region of the gate electrode24in plan view. In this structure, the distance between the gate electrode24and the source electrode28in the Z-direction is increased as compared to a structure in which the second thickness D2is equal to the first thickness D1. Thus, the gate-source capacitance Cgsof the nitride semiconductor device10is decreased.

More specifically, in the present embodiment, the insulation layer26includes the spacer layer32in addition to the passivation layer34. Therefore, in the present embodiment, the distance between the gate electrode24and the source electrode28in the Z-direction is increased by the thickness of the spacer layer32(the third thickness D3) from a structure in which the spacer layer32is not disposed on the gate electrode24. Thus, the gate-source capacitance Cgsof the nitride semiconductor device10is decreased.

The operation characteristics of the nitride semiconductor device10will now be described using test example 1 and test example 2.

In test example 1 of a nitride semiconductor device, the second thickness D2is approximate 2.0 times the first thickness D1. In test example 2 of a nitride semiconductor device, the second thickness D2is substantially equal to the first thickness D1. The nitride semiconductor devices of test example 1 and text example 2 have the same structure except for the second thickness D2. The nitride semiconductor device of test example 1, in which the second thickness D2is greater than the first thickness D1, may correspond to the nitride semiconductor device10.

FIG.8is a graph showing the relationship between input capacitance Cissand drain voltage Vdsof nitride semiconductor devices in test example 1 and test example 2. In the graph, the horizontal axis indicates the drain voltage Vds, and the vertical axis indicates the input capacitance Ciss. In the graph, test example 1 is indicated by a solid line, and test example 2 is indicated by a broken line.

As shown inFIG.8, for example, the input capacitance Cissof test example 1 is decreased by approximately 18% from the input capacitance Cissof test example 2 at a given drain voltage Vds. The input capacitance Cissis the sum of the gate-source capacitance Cgsand the gate-drain capacitance Cgd. This shows that an increase in the second thickness D2from the first thickness D1decreases the gate-source capacitance Cgs, thereby decreasing the input capacitance Ciss.

FIG.9is a graph showing the relationship between total gate charge Qgand gate voltage Vgsof the nitride semiconductor devices in test example 1 and test example 2. In the graph, the horizontal axis indicates the total gate charge Qg, and the vertical axis indicates the gate voltage Vgs. In the graph, test example 1 is indicated by a solid line, and test example 2 is indicated by a broken line.

As shown inFIG.9, the total gate charge Qgof test example 1 is decreased by approximately 30% from the total gate charge Qgof test example 2 at a given gate voltage Vgs. This shows that when the second thickness D2is increased from the first thickness D1, the total gate charge Qgof the nitride semiconductor device is decreased.

The total gate charge Qgrepresents an amount of charge necessary to be supplied to the gate electrode in order to activate the transistor. When the total gate charge Qgis large, charging to the amount necessary to activate the transistor takes a longer time. This increases switching loss. Therefore, as the total gate charge Qgis decreased, switching loss will be decreased. This allows for high-speed switching.

The nitride semiconductor device10of the first embodiment has the following advantages.(1-1) The insulation layer26includes the first insulation layer part26P1having the first thickness D1and the second insulation layer part26P2having the second thickness D2. The first insulation layer part26P1is disposed on the electron supply layer18in contact with the drain electrode30. The second insulation layer part26P2is disposed on the gate electrode24in contact with the source field plate28B. The second thickness D2of the second insulation layer part26P2is greater than the first thickness D1of the first insulation layer part26P1.

In this structure, the distance between the gate electrode24and the source electrode28in the Z-direction is increased as compared to a structure in which the second thickness D2is equal to the first thickness D1. This results in a decrease in the gate-source capacitance Cgs, thereby limiting an increase in the input capacitance Cissand the total gate charge Qg.(1-2) The second thickness D2is greater than or equal to 1.2 times the first thickness (D1) and less than or equal to 5.0 times the first thickness (D1).

In this structure, the gate-source capacitance Cgsis decreased by a relatively large amount. Thus, increases in the input capacitance Cissand the total gate charge Qg. are further effectively limited.(1-3) The insulation layer26includes the spacer layer32, formed on the gate electrode24, and the passivation layer34covering the electron supply layer18, the gate layer22, the gate electrode24, and the spacer layer32. The first insulation layer part26P1is formed of the passivation layer34. The second insulation layer part26P2is formed of the spacer layer32and the passivation layer34.

In this structure, the spacer layer32disposed on the gate electrode24increases the distance between the gate electrode24and the source electrode28in the z-direction. Thus, the gate-source capacitance Cgsis decreased.

Second Embodiment

FIG.10is a schematic cross-sectional view showing an exemplary nitride semiconductor device200of a second embodiment. InFIG.10, the same reference characters are given to those components that are the same as the corresponding components of the nitride semiconductor device10of the first embodiment. Such components will not be described in detail.

In a semiconductor device of a nitride semiconductor device200, the spacer layer32and the passivation layer34are composed of the same material. In an example, each of the spacer layer32and the passivation layer34is composed of SiN. Hence, the border between the spacer layer32and the passivation layer34of the insulation layer26is not drawn inFIG.10. In the nitride semiconductor device200, an interface may, but does not necessarily have to, be formed between the spacer layer32and the passivation layer34. However, there may be no visible interface formed between the spacer layer32and the passivation layer34that are composed of the same material. An exemplary pattern formed in the nitride semiconductor device200is similar to the pattern100shown inFIG.2.

The method for manufacturing the nitride semiconductor device200is substantially the same as that of the nitride semiconductor device10. In the second embodiment, each of the spacer insulation layer56and the passivation insulation layer58may be a SiN layer formed by LPCVD.

The operation characteristics of the nitride semiconductor device200may correspond to test example 1 shown inFIGS.8and9in the same manner as the nitride semiconductor device10. Therefore, the increase in the second thickness D2from the first thickness D1decreases the gate-source capacitance Cgs, thereby decreasing the input capacitance Cissand the total gate charge Qg.

As described above, the nitride semiconductor device200of the second embodiment has the same advantages as the nitride semiconductor device10of the first embodiment.

Third Embodiment

FIG.11is a schematic cross-sectional view showing an exemplary nitride semiconductor device300of a third embodiment. InFIG.11, the same reference characters are given to those components that are the same as the corresponding components of the nitride semiconductor device10of the first embodiment. Such components will not be described in detail.

The nitride semiconductor device300of the third embodiment includes an insulation layer302instead of the insulation layer26(refer toFIG.1). The insulation layer302covers the electron supply layer18, the gate layer22, and the gate electrode24and includes a first opening302A and a second opening302B. The first opening302A and the second opening302B are separated from the gate layer22. The gate layer22is located between the first opening302A and the second opening302B. More specifically, the gate layer22is located closer to the first opening302A than the second opening302B between the first opening302A and the second opening302B. The source electrode28is in contact with the electron supply layer18through the first opening302A. The drain electrode30is in contact with the electron supply layer18through the second opening302B.

The insulation layer302includes a first insulation layer part302P1having a first thickness D1and a second insulation layer part302P2having a second thickness D2.

The first insulation layer part302P1is disposed on the electron supply layer18in contact with the drain electrode30. The first insulation layer part302P1corresponds to a part of the insulation layer302having the first thickness D1, which is a constant thickness, between the gate layer22and the drain electrode30. The first insulation layer part302P1is partially covered by the source field plate28B. More specifically, a portion of the first insulation layer part302P1located toward the gate layer22is covered by the source field plate28B. Therefore, the end28C of the source field plate28B is located on the first insulation layer part302P1. In other words, the first insulation layer part302P1is a part of the insulation layer302on which the end28C of the source field plate28B is disposed.

The second insulation layer part302P2is disposed on the gate electrode24in contact with the source field plate28B. The second insulation layer part302P2corresponds to a part of the insulation layer302disposed on the gate electrode24and having the second thickness D2, which is a constant thickness. The second insulation layer part302P2is entirely covered by the source field plate28B.

The second thickness D2of the second insulation layer part302P2is greater than the first thickness D1of the first insulation layer part302P1. The second thickness D2may be greater than or equal to 1.2 times the first thickness D1and less than or equal to 5.0 times the first thickness D1. The first thickness D1may be greater than or equal to 50 nm and less than or equal to 200 nm. The second thickness D2may be greater than or equal to 100 nm and less than or equal to 400 nm.

The first thickness D1is a thickness of the insulation layer302where the end28C of the source field plate28B is located in plan view. In other words, the first thickness D1is a distance between the electron supply layer18and the source electrode28where the end28C of the source field plate28B is located in plan view. The second thickness D2is a distance between the gate electrode24and the source electrode28in a region of the gate electrode24in plan view. Thus, an increase in the second thickness D2decreases the gate-source capacitance Cgs. In the same manner as the first embodiment, the second thickness D2may be set in a range so that the ratio of input capacitance Cissto feedback capacitance Crsswill not become below a value (for example, 150) determined in accordance with the circuit design.

In the present embodiment, the insulation layer302is a passivation layer304. Each of the first insulation layer part302P1and the second insulation layer part302P2is formed of the passivation layer304. That is, the insulation layer302is formed of only the passivation layer304.

The nitride semiconductor device300differs from the nitride semiconductor device10of the first embodiment in that the nitride semiconductor device300does not include the spacer layer32. In the first embodiment, the second insulation layer part26P2is formed of the spacer layer32and the passivation layer34. In the third embodiment, the second insulation layer part302P2is formed of the passivation layer304.

The insulation layer302(the passivation layer304) may be composed of, for example, one of SiN, SiO2, SiON, Al2O3, AlN, and AlON. In an example, the insulation layer302is composed of SiN. The insulation layer302may serve as a protection film.

An exemplary pattern formed in the nitride semiconductor device300is similar to the pattern100shown inFIG.2. In the pattern formed in the nitride semiconductor device300, the insulation layer302(the passivation layer304) is used in lieu of the insulation layer26(the passivation layer34) of the pattern100.

An example of a method for manufacturing the nitride semiconductor device300shown inFIG.11will be described.

FIGS.12to18are schematic cross-sectional views showing exemplary manufacturing steps of the nitride semiconductor device300. To facilitate understanding, inFIGS.12to18, the same reference characters are given to those components that are the same as the corresponding components shown inFIG.11. Elements that will ultimately become the elements of the nitride semiconductor device300are denoted by the corresponding reference characters shown inFIG.11in parentheses.

A method for manufacturing the nitride semiconductor device300includes forming the electron transit layer16composed of a nitride semiconductor, forming the electron supply layer18on the electron transit layer16, the electron supply layer18being composed of a nitride semiconductor having a band gap that is larger than that of the electron transit layer16, forming the gate layer22on the electron supply layer18, the gate layer22composed of a nitride semiconductor including an acceptor impurity, forming the gate electrode24on the gate layer22, and forming the insulation layer302(refer toFIG.11) that covers the electron supply layer18, the gate layer22, and the gate electrode24and includes the first opening302A and the second opening302B.

In the present embodiment, the insulation layer302is the passivation layer304(refer toFIG.11). Therefore, forming the insulation layer302includes forming the passivation layer304that covers the electron supply layer18, the gate layer22, and the gate electrode24and includes a first opening304A and a second opening304B. The first opening304A and the second opening304B of the passivation layer304respectively correspond to the first opening302A and the second opening302B of the insulation layer302.

Forming the insulation layer302(the passivation layer304) includes selectively etching the insulation layer302(the passivation layer304) so that the first insulation layer part302P1differs in thickness from the second insulation layer part302P2(refer toFIG.11).

As shown inFIG.12, for example, the buffer layer14, the electron transit layer16, the electron supply layer18, a nitride semiconductor layer352, and a metal layer354are sequentially formed on the substrate12, which is a Si substrate.

The buffer layer14, the electron transit layer16, the electron supply layer18, and the nitride semiconductor layer352may be epitaxially grown by MOCVD.

Although not shown in detail, in an example, the buffer layer14is multilayer. An AlN layer (the first buffer layer) is formed on the substrate12, and then a graded AlGaN layer (the second buffer layer) is formed on the AlN layer. The graded AlGaN layer is formed, for example, by stacking three AlGaN layers having Al compositions of 75%, 50%, and 25% in the order from the side of the AlN layer.

A GaN layer is formed on the buffer layer14as the electron transit layer16. An AlGaN layer is formed on the electron transit layer16as the electron supply layer18. Thus, the electron supply layer18has a band gap that is larger than that of the electron transit layer16. Then, a GaN layer including an acceptor impurity is formed on the electron supply layer18as the nitride semiconductor layer352.

The buffer layer14, the electron transit layer16, the electron supply layer18, and the nitride semiconductor layer352are composed of nitride semiconductors having lattice constants relatively close to each other. This allows for sequential epitaxial growth of the layers.

Subsequently, the metal layer354is formed on the nitride semiconductor layer352. In an example, the metal layer354is a TiN layer formed through sputtering.

FIG.13is a schematic cross-sectional view showing a manufacturing step subsequent toFIG.12. As shown inFIG.13, the metal layer354is selectively removed by lithography and etching to form the gate electrode24.

FIG.14is a schematic cross-sectional view showing a manufacturing step subsequent toFIG.13. As shown inFIG.14, the nitride semiconductor layer352is selectively removed by lithography and etching to form the gate layer22. As a result, a stacked structure including the gate layer22and the gate electrode24formed on the gate layer22is formed on a portion of the upper surface of the electron supply layer18.

FIG.15is a schematic cross-sectional view showing a manufacturing step subsequent toFIG.14. As shown inFIG.15, a passivation insulation layer356is formed to cover the entirety of exposed surfaces of the electron supply layer18, the gate layer22, and the gate electrode24. In an example, the passivation insulation layer356is a SiN layer formed by LPCVD. The passivation insulation layer356may have a thickness that is greater than or equal to 100 nm and less than or equal to 400 nm.

FIG.16is a schematic cross-sectional view showing a manufacturing step subsequent toFIG.15. As shown inFIG.16, a mask358(e.g., photoresist) is formed to cover a portion of the upper surface of the passivation insulation layer356. In an example, a photoresist is applied to the entire surface of the passivation insulation layer356, and exposure is performed to form the mask358on a portion of the upper surface of the passivation insulation layer356.

The region in which the mask358is formed includes a formation region in which at least the gate layer22and the gate electrode24are formed in plan view. In plan view, the mask358is greater in size than the formation region and is formed in a region that does not cover the first opening302A and the second opening302B shown inFIG.11.

FIG.17is a schematic cross-sectional view showing a manufacturing step subsequent toFIG.16. As shown inFIG.17, the passivation insulation layer356is selectively etched using the mask358. As a result, while the thickness of the passivation insulation layer356is maintained in a region covered by the mask358, the thickness of the passivation insulation layer356is decreased in a region that is not covered by the mask358. In the region that is not covered by the mask358, after etching, the passivation insulation layer356may have a thickness that is greater than or equal to 50 nm and less than or equal to 200 nm. The mask358is removed after etching. Such selective etching of the passivation insulation layer356allows the first insulation layer part302P1and the second insulation layer part302P2to have different thicknesses in the resultant nitride semiconductor device300.

FIG.18is a schematic cross-sectional view showing a manufacturing step subsequent toFIG.17. As shown inFIG.18, the passivation insulation layer356is selectively removed by lithography and etching to form the insulation layer302including the first opening302A and the second opening302B. More specifically, the passivation insulation layer356is patterned so that the gate layer22is disposed between the first opening302A and the second opening302B. This forms the insulation layer302that covers the electron supply layer18, the gate layer22, and the gate electrode24and includes the first opening302A and the second opening302B.

The method for manufacturing the nitride semiconductor device300further includes forming the source electrode28(refer toFIG.11), which is in contact with the electron supply layer18through the first opening302A, and forming the drain electrode30(refer toFIG.11), which is in contact with the electron supply layer18through the second opening302B.

In a manufacturing step subsequent to the step shown inFIG.18, a metal layer is formed to fill the first opening302A and the second opening302B and cover the entirety of exposed surfaces of the insulation layer302. The metal layer (e.g., one or more metal layers including Ti, Al, TiN, and the like) is patterned by lithography and etching to form the source electrode28and the drain electrode30. The source electrode28includes the source field plate28B covering the insulation layer302. The source field plate28B includes the end28C located between the second opening302B and the gate layer22in plan view. This obtains the nitride semiconductor device300shown inFIG.11.

The operation of the nitride semiconductor device300of the present embodiment will be described below.

In the nitride semiconductor device300, the insulation layer302includes the first insulation layer part302P1having the first thickness D1and the second insulation layer part302P2having the second thickness D2that is greater than the first thickness D1. The second thickness D2corresponds to the distance between the gate electrode24and the source electrode28in a region of the gate electrode24in plan view. In this structure, the distance between the gate electrode24and the source electrode28in the Z-direction is increased as compared to a structure in which the second thickness D2is equal to the first thickness D1. Thus, the gate-source capacitance Cgsof the nitride semiconductor device300is decreased.

The operation characteristics of the nitride semiconductor device300may correspond to test example 1 shown inFIGS.8and9in the same manner as the nitride semiconductor device10of the first embodiment. Therefore, the increase in the second thickness D2from the first thickness D1decreases the gate-source capacitance Cgs, thereby decreasing the input capacitance Cissand the total gate charge Qg.

The nitride semiconductor device300of the third embodiment has the following advantages.(3-1) The insulation layer302includes the first insulation layer part302P1having the first thickness D1and the second insulation layer part302P2having the second thickness D2. The first insulation layer part302P1is disposed on the electron supply layer18in contact with the drain electrode30. The second insulation layer part302P2is disposed on the gate electrode24in contact with the source field plate28B. The second thickness D2of the second insulation layer part302P2is greater than the first thickness D1of the first insulation layer part302P1.

In this structure, the distance between the gate electrode24and the source electrode28in the Z-direction is increased as compared to a structure in which the second thickness D2is equal to the first thickness D1. This results in a decrease in the gate-source capacitance Cgs, thereby limiting an increase in the input capacitance Cissand the total gate charge Qg.(3-2) The second thickness D2is greater than or equal to 1.2 times the first thickness (D1) and less than or equal to 5.0 times the first thickness (D1).

In this structure, the gate-source capacitance Cgsis decreased by a relatively large amount. Thus, increases in the input capacitance Cissand the total gate charge Qg. are further effectively limited.

Modified Examples

The embodiments described above may be modified as follows. The embodiments described above and the modified examples described below can be combined as long as the combined modifications remain technically consistent with each other.

In the first embodiment, from the viewpoint of decreasing the gate-source capacitance Cgs, the spacer layer32may be composed of a material having a lower electric permittivity than a material of the passivation layer34.

InFIG.1, the spacer layer32is formed on the entire upper surface24B of the gate electrode24. Instead, the spacer layer32may be formed on a portion of the upper surface24B of the gate electrode24. Alternatively, the spacer layer32may be formed on the upper surface24B and the side surface24C of the gate electrode24.

In the embodiments, each of the passivation layer34, the spacer layer32, and the insulation layer302is composed of one of SiN, SiO2, SiON, Al2O3, AlN, and AlON. Alternatively, each of the passivation layer34, the spacer layer32, and the insulation layer302may be a composite film including two or more of SiN, SiO2, SiON, Al2O3, AlN, and AlON.

The gate electrode24may be formed on at least a portion of the gate layer22. In an example, in the embodiments, the gate electrode24may be formed on the entire gate layer22.

In this specification, “at least one of A and B” should be understood to mean “only A, or only B, or both A and B”.

In the present disclosure, the term “on” includes the meaning of “above” in addition to the meaning of “on” unless otherwise clearly indicated in the context. Therefore, the phrase “first layer formed on second layer” is intended to mean that the first layer may be formed on the second layer in contact with the second layer in one embodiment and that the first layer may be located above the second layer without contacting the second layer in another embodiment. In other words, the term “on” does not exclude a structure in which another layer is formed between the first layer and the second layer. For example, the above embodiment in which the electron supply layer18is formed on the electron transit layer16includes a structure in which an intermediate layer is disposed between the electron supply layer18and the electron transit layer16to stably form the 2DEG20.

The Z-axis direction as referred to in the present disclosure does not necessarily have to be the vertical direction and does not necessarily have to fully conform to the vertical direction. In the structures according to the present disclosure (e.g., the structure shown inFIG.1), “upward” and “downward” in the Z-axis direction as referred to in the present description are not limited to “upward” and “downward” in the vertical direction. For example, the X-axis direction may conform to the vertical direction. The Y-axis direction may conform to the vertical direction.

CLAUSES

The technical aspects that are understood from the embodiments and the modified examples will be described below. To facilitate understanding without intention to limit, the reference signs of the elements in the embodiments are given to the corresponding elements in the clause with parentheses. The reference signs used as examples to facilitate understanding, and the elements in each clause are not limited to those elements given with the reference signs.A1. A nitride semiconductor device, including:an electron transit layer (16) composed of a nitride semiconductor;an electron supply layer (18) formed on the electron transit layer (16), the electron supply layer (18) being composed of a nitride semiconductor having a band gap that is larger than that of the electron transit layer (16);a gate layer (22) formed on the electron supply layer (18), the gate layer (22) being composed of a nitride semiconductor including an acceptor impurity;a gate electrode (24) formed on the gate layer (22);an insulation layer (26) covering the electron supply layer (18), the gate layer (22), and the gate electrode (24) and including a first opening (26A) and a second opening (26B);a source electrode (28) in contact with the electron supply layer (18) through the first opening (26A); anda drain electrode (30) in contact with the electron supply layer (18) through the second opening (26B), wherethe gate layer (22) is located between the first opening (26A) and the second opening (26B),the source electrode (28) includes a source field plate (28B) covering the insulation layer (26), the source field plate (28B) includes an end (28C) located between the second opening (26B) and the gate layer (22) in plan view,the insulation layer (26) includesa first insulation layer part (26P1) that is disposed on the electron supply layer (18) in contact with the drain electrode (30) and has a first thickness (D1), anda second insulation layer part (26P2) that is disposed on the gate electrode (24) in contact with the source field plate (28B) and has a second thickness (D2), the end (28C) of the source field plate (28B) is disposed on the first insulation layer part (26P1), andthe second thickness (D2) of the second insulation layer part (26P2) is greater than the first thickness (D1) of the first insulation layer part (26P1).A2. The nitride semiconductor device according to clause A1, where the second thickness (D2) is greater than or equal to 1.2 times the first thickness (D1) and less than or equal to 5.0 times the first thickness (D1).A3. The nitride semiconductor device according to clause A1 or A2, wherethe first thickness (D1) is greater than or equal to 50 nm and less than or equal to 200 nm, andthe second thickness (D2) is greater than or equal to 100 nm and less than or equal to 400 nm.A4. The nitride semiconductor device according to any one of clauses A1 to A3, in whichthe insulation layer (26) includesa spacer layer (32) formed on the gate electrode (24), anda passivation layer (34) covering the electron supply layer (18), the gate layer (22), the gate electrode (24), and the spacer layer (32) and including the first opening (26A) and the second opening (26B),the first insulation layer part (26P1) is formed of the passivation layer (34), andthe second insulation layer part (26P2) is formed of the spacer layer (32) and the passivation layer (34).A5. The nitride semiconductor device according to clause A4, wherein the first insulation layer part (26P1), the passivation layer (34) has the first thickness (D1),in the second insulation layer part (26P2), the spacer layer (32) has a third thickness (D3), and the passivation layer (34) has a fourth thickness (D4), andthe second thickness (D2) is a sum of the third thickness (D3) and the fourth thickness (D4).A6. The nitride semiconductor device according to clause A5, where the first thickness (D1) is substantially equal to the fourth thickness (D4).A7. The nitride semiconductor device according to any one of clauses A4 to A6, in which the spacer layer (32) is composed of any one of SiN, SiO2, SiON, Al2O3, AlN, and AlON.A8. The nitride semiconductor device according to any one of clauses A4 to A7, in which the spacer layer (32) and the passivation layer (34) are composed of a same material.A9. The nitride semiconductor device according to any one of clauses A4 to A8, in which each of the spacer layer (32) and the passivation layer (34) is composed of SiN.A10. The nitride semiconductor device according to any one of clauses A4 to A7, in which the spacer layer (32) is composed of a material having a lower electric permittivity than a material of the passivation layer (34).A11. The nitride semiconductor device according to any one of clauses A4 to A10, in whichthe gate electrode (24) includes a first surface (24A) in contact with the gate layer and a second surface (24B) opposite to the first surface (24A), andthe spacer layer (32) is formed on a portion of the second surface (24B) of the gate electrode (24).

Al2. The nitride semiconductor device according to any one of clauses A4 to A10, in whichthe gate electrode (24) includes a first surface (24A) in contact with the gate layer (22), a second surface (24B) opposite to the first surface (24A), and a third surface (24C) extending between the first surface (24A) and the second surface (24B), andthe spacer layer (32) is formed on the second surface (24B) and the third surface (24C) of the gate electrode (24).A13. The nitride semiconductor device according to any one of clauses A1 to A3, in whichthe insulation layer (302) is a passivation layer (304), andeach of the first insulation layer part (302P1) and the second insulation layer part (302P2) is formed of the passivation layer (304).A14. The nitride semiconductor device according to any one of clauses A4 to A13, in which the passivation layer (34;304) is formed of any one of SiN, SiO2, SiON, Al2O3, AlN, and AlON.A15. The nitride semiconductor device according to any one of clauses A1 to A14, in whichthe first thickness (D1) is a thickness of the insulation layer (26) where the end (28C) of the source field plate (28B) is located in plan view, andthe second thickness (D2) is a distance between the gate electrode (24) and the source electrode (28) in a region of the gate electrode (24) in plan view.B1. A method for manufacturing a nitride semiconductor device, the method including:forming an electron transit layer (16) composed of a nitride semiconductor;forming an electron supply layer (18) on the electron transit layer (16), the electron supply layer (18) being composed of a nitride semiconductor having a band gap that is larger than that of the electron transit layer (16);forming a gate layer (22) on the electron supply layer (18), the gate layer (22) being composed of a nitride semiconductor including an acceptor impurity;forming a gate electrode (24) on the gate layer (22);forming an insulation layer (26) that covers the electron supply layer (18), the gate layer (22), and the gate electrode (24) and includes a first opening (26A) and a second opening (26B);forming a source electrode (28) that is in contact with the electron supply layer (18) through the first opening (26A); andforming a drain electrode (30) that is in contact with the electron supply layer (18) through the second opening (26B), wherethe gate layer (22) is located between the first opening (26A) and the second opening (26B),the source electrode (28) includes a source field plate (28B) covering the insulation layer (26), the source field plate (28B) includes an end (28C) located betweenthe second opening (26B) and the gate layer (22) in plan view,the insulation layer (26) includesa first insulation layer part (26P1) that is disposed on the electron supply layer (18) in contact with the drain electrode (30) and has a first thickness (D1), anda second insulation layer part (26P2) that is disposed on the gate electrode (24) in contact with the source field plate (28B) and has a second thickness (D2),the end (28C) of the source field plate (28B) is disposed on the first insulation layer part (26P1),the second thickness (D2) of the second insulation layer part (26P2) is greater than the first thickness (D1) of the first insulation layer part (26P1).B2. The method according to clause B1, where the second thickness (D2) is greater than or equal to 1.2 times the first thickness (D1) and less than or equal to 5.0 times the first thickness (D1).B3. The method according to clause B1 or B2, wherethe first thickness (D1) is greater than or equal to 50 nm and less than or equal to 200 nm, andthe second thickness (D2) is greater than or equal to 100 nm and less than or equal to 400 nm.B4. The method according to any one of clauses B1 to B3, in whichthe forming an insulation layer (26) includesforming a spacer layer (32) on the gate electrode (24), andforming a passivation layer (34) that covers the electron supply layer (18), the gate layer (22), the gate electrode (24), and the spacer layer (32) and includes the first opening (26A) and the second opening (26B),the first insulation layer part (26P1) is formed of the passivation layer (34), andthe second insulation layer part (26P2) is formed of the spacer layer (32) and the passivation layer (34).B5. The method according to clause B4, wherein the first insulation layer part (26P1), the passivation layer (34) has the first thickness (D1),in the second insulation layer part (26P2), the spacer layer (32) has a third thickness (D3), and the passivation layer (34) has a fourth thickness (D4), andthe second thickness (D2) is a sum of the third thickness (D3) and the fourth thickness (D4).B6. The method according to clause B5, where the first thickness (D1) is substantially equal to the fourth thickness (D4).B7. The method according to any one of clauses B4 to B6, in which the spacer layer (32) is composed of any one of SiN, SiO2, SiON, Al2O3, AlN, and AlON.B8. The method according to any one of clauses B4 to B7, in which the spacer layer (32) and the passivation layer (34) are composed of a same material.B9. The method according to any one of clauses B4 to B8, in which each of the spacer layer (32) and the passivation layer (34) is composed of SiN.B10. The method according to any one of clauses B4 to B7, in which the spacer layer (32) is composed of a material having a lower electric permittivity than a material of the passivation layer (34).B11. The method according to any one of clauses B4 to B10, in whichthe gate electrode (24) includes a first surface (24A) in contact with the gate layer (22) and a second surface (24B) opposite to the first surface (24A), andthe spacer layer (32) is formed on a portion of the second surface (24B) of the gate electrode (24).B12. The method according to any one of clauses B4 to B10, in whichthe gate electrode (24) includes a first surface (24A) in contact with the gate layer (22), a second surface (24B) opposite to the first surface (24A), and a third surface (24C) extending between the first surface (24A) and the second surface (24B), andthe spacer layer (32) is formed on the second surface (24B) and the third surface (24C) of the gate electrode (24).B13. The method according to any one of clauses B1 to B3, in whichthe forming an insulation layer (302) includes forming a passivation layer (304) that covers the electron supply layer (18), the gate layer (22), and the gate electrode (24) and includes the first opening (304A) and the second opening (304B), andeach of the first insulation layer part (302P1) and the second insulation layer part (302P2) is formed of the passivation layer (304).B14. The method according to any one of clauses B4 to B13, in which the passivation layer (34;302) is formed of any one of SiN, SiO2, SiON, Al2O3, AlN, and AlON.B15. The method according to any one of clauses B1 to B14, in whichthe first thickness (D1) is a thickness of the insulation layer (26) where the end (28C) of the source field plate (28B) is located in plan view, andthe second thickness (D2) is a distance between the gate electrode (24) and the source electrode (28) in a region of the gate electrode (24) in plan view.B16. The method according to any one of clauses B13 to B15, in which the forming a passivation layer (304) includes selectively etching the passivation layer (304) so that the first insulation layer part (302P1) differs in thickness from the second insulation layer part (302P2).B17. The method according to any one of clauses B1 to B3, in which the forming an insulation layer (302) includes selectively etching the insulation layer (302) so that the first insulation layer part (302P1) differs in thickness from the second insulation layer part (302P2).