Semiconductor storage device

A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of and priority to Japanese Patent Application No. 2019-053449, filed Mar. 20, 2019, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor storage device.

BACKGROUND

Some comparative devices include a semiconductor storage device capable of storing data in a nonvolatile manner, such as a NAND flash memory. In such a semiconductor storage device, a three-dimensional memory structure may be adopted for high integration and large capacity. A structure for leading out a contact connected to a stacked wiring layer in this three-dimensional memory structure can be implemented.

DETAILED DESCRIPTION

Embodiments described herein provide for semiconductor storage devices capable of improved connection between a select gate line and a contact.

In general, according to one embodiment, a semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.

Hereinafter, embodiments will be described with reference to the drawings. The description includes an example of a device or a method for practicing the technical aspects of the embodiments. The drawings are schematic or conceptual, and a dimension, a ratio, and the like of each of the drawings are not necessarily the same as the actual ones. The technical aspects of the present disclosure are not necessarily limited to a disclosed shape, a structure, an arrangement, and the like of a component.

In the following description, components having substantially the same functions and configurations are represented by the same reference numerals. A number attached to characters constituting a reference numeral is referred to by a reference numeral including the same characters and is used to distinguish between elements having the same configuration. When it is not necessary to distinguish between elements represented by reference numerals including the same characters, these elements are referred to by reference numerals consisting of only the characters.

In addition, in the following description, “diameter” of a layer refers to an average outer diameter of the layer in a cross-section parallel to a stacked surface of the layer. “Center” of a cross-section of a layer refers to the center of gravity of the cross-section.

1. First Embodiment

A semiconductor storage device according to a first embodiment will be described.

First, a configuration of the semiconductor storage device according to the first embodiment will be described.

1.1.1 Semiconductor Storage Device

FIG. 1is a block diagram illustrating the configuration of the semiconductor storage device according to the first embodiment. The semiconductor storage device1according to the first embodiment is a NAND flash memory capable of storing data in a nonvolatile manner and is controlled by an external memory controller2. Communication between the semiconductor storage device1and the memory controller2supports, for example, NAND interface standards.

As illustrated inFIG. 1, the semiconductor storage device1includes, for example, a memory cell array10, a command register11, an address register12, a sequencer13, a driver module14, a row decoder module15, and a sense amplifier module16.

The memory cell array10includes a plurality of blocks BLK0to BLKn (n represents an integer of 1 or more). The block BLK is an aggregation of a plurality of memory cells capable of storing data in a nonvolatile manner and is used, for example, as a unit of data erasure. In the memory cell array10, a plurality of bit lines and a plurality of word lines are provided. Each of the memory cells is associated with, for example, one bit line and one word line. A detailed configuration of the memory cell array10will be described below.

The command register11stores a command CMD that is received from the memory controller2by the semiconductor storage device1. The command CMD includes, for example, a command that causes the sequencer13to execute a read operation, a write operation, an erasing operation, and the like.

The address register12stores address information ADD that is received from the memory controller2by the semiconductor storage device1. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used for selection of the block BLK, the word line, and the bit line.

The sequencer13controls an overall operation of the semiconductor storage device1. For example, the sequencer13controls the driver module14, the row decoder module15, the sense amplifier module16, and the like to execute a read operation, a write operation, an erasing operation, and the like based on the command CMD stored in the command register11.

The driver module14generates a voltage used for the read operation, the write operation, the erasing operation, or the like. The driver module14applies the generated voltage to a signal line corresponding to the selected word line based on, for example, the page address PA stored in the address register12.

The row decoder module15selects one block BLK in the corresponding memory cell array10based on the block address BA stored in the address register12. The row decoder module15transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

In the write operation, the sense amplifier module16applies a desired voltage to each of the bit lines according to write data DAT received from the memory controller2. In the read operation, the sense amplifier module16determines data stored in the memory cell based on the voltage of the bit line and transfers the determination result to the memory controller2as read data DAT.

A combination of the semiconductor storage device1and the memory controller2described above may configure at least a portion of one semiconductor device. Examples of the semiconductor device include a memory card such as a SD™ card and an SSD (solid state drive).

1.1.2. Circuit Configuration of Memory Cell Array

FIG. 2is a circuit diagram illustrating a configuration of the memory cell array of the semiconductor storage device according to the first embodiment.FIG. 2illustrates one block BLK among the blocks BLK in the memory cell array10.

As illustrated inFIG. 2, the block BLK includes, for example, four string units SU0to SU3. Each of the string units SU includes a plurality of NAND strings NS that are associated with bit lines BL0to BLm (m represents an integer of 1 or more), respectively. Each of the NAND strings NS includes memory cell transistors MT0to MT7and select transistors ST1and ST2. The memory cell transistor MT includes a control gate and a charge storage layer and stores data in a nonvolatile manner. Each of the select transistors ST1and ST2is used for selection of the string unit SU in various operations.

In each of the NAND strings NS, the memory cell transistors MT0to MT7are connected in series to each other. A drain of the select transistor ST1is connected to the associated bit line BL, and a source of the select transistor ST1is connected to one end of the memory cell transistors MT0to MT7that are connected in series to each other. A drain of the select transistor ST2is connected to another end of the memory cell transistors MT0to MT7that are connected in series to each other. A source of the select transistor ST2is connected to a source line SL.

Control gates of the memory cell transistors MT0to MT7in the same block BLK are connected in common to word lines WL0to WL7, respectively. Gates of the select transistors ST1in the string units SU0to SU3are connected in common to select gate lines SGD0to SGD3. Gates of the select transistors ST2are connected in common to a select gate line SGS.

In the circuit configuration of the memory cell array10described above, the bit line BL is shared by the NAND strings NS to which the same column address is assigned in the respective string units SU. The source line SL is shared between, for example, a plurality of blocks BLK.

An assembly including a plurality of memory cell transistors MT that are connected to the common word line WL in one string unit SU will be referred to as, for example, “cell unit CU”. For example, the storage capacity of the cell unit CU including the memory cell transistors MT each of which stores 1-bit data is defined as “1-page data”. The cell unit Cu may include a storage capacity of 2-page data or more according to the number of bits in data stored in the memory cell transistor MT.

The circuit configuration of the memory cell array10in the semiconductor storage device1according to the first embodiment is not limited to the above-described configuration. For example, the numbers of the memory cell transistors MT1and the select transistors ST1and ST2in each of the NAND strings NS may be designed to any appropriate numbers, respectively. The number of the string units SU in each block BLK may be any appropriate number.

1.1.3 Structure of Memory Cell Array

Hereinafter, an example of the structure of the memory cell array of the semiconductor storage device according to the first embodiment will be described.

In the drawings that will be referred to below, an X-axis corresponds to an extending direction of the word lines WL. A Y-axis corresponds to an extending direction of the bit line BL. A Z-axis corresponds to a direction perpendicular to a surface of a semiconductor substrate on which the semiconductor storage device1is to be formed. In order to easily understand a plan view, the drawing is appropriately hatched. A hatched area in the plan view does not necessarily relate to a material or characteristics of a hatched component. In a cross-sectional view, a component such as an insulator layer (interlayer insulating film), a wiring, or a contact may be omitted from the illustrations in order to better explain the drawing.

FIG. 3is a plan view illustrating a planar layout of the memory cell array of the semiconductor storage device according to the first embodiment. For example,FIG. 3illustrates apart of a cell region CA that includes structures corresponding to the string units SU0to SU3in one block BLK and a hookup region HA where a contact CC is led out from a stacked wiring layer in each of the string units SU.

As illustrated inFIG. 3, the memory cell array10includes, for example, a slit SHE, a plurality of slits SLT, a memory pillar MP, contacts CP and CC, the bit line BL, and a stacked wiring layer. The slit SHE includes a plurality of slits SHE_X and a slit SHE_Y. A plurality of stacked wiring layers include, for example, three layers of select gate lines SGD (each of which includes SGD0to SGD3and SGDX located in the same layer), seven layers of word lines WL0to WL7, and a single layer of select gate line SGS. A plurality of memory pillars MP, the contact CP, and the bit line BL are provided in the cell region CA, and a plurality of contacts CC are provided in the hookup region HA.

The stacked wiring layers are stacked along the Z-axis in order of the select gate line SGS, the word lines WL0to WL7, and the select gate lines SGD from the semiconductor substrate side.

Each of the slits SLT extends along a predetermined direction (inFIG. 3, the X-axis) of a memory cell array plane and are arrayed along a direction (inFIG. 3, the Y-axis as a direction perpendicular to the X-axis) perpendicular to the predetermined direction. Each of the slits SHE_X extends along the X-axis and are arrayed along the Y direction between adjacent slits SLT. The slit SHE_Y extends along the Y-axis and between adjacent slits SLT. For example, the width of the slit SLT is wider than the width of the slit SHE. The slits SLT, SHE_X, and SHE_Y include an insulator. The slit SHE_X may be an example of a first insulator layer, and the slit SHE_Y may be an example of a second insulator layer. The slit SHE_X may be connected to the slit SHE_Y. For example, the slit SLT divides the stacked wiring layers corresponding to the word line WL, the select gate line SGD, and the select gate line SGS described below with reference toFIG. 4. That is, the slit SLT insulates and separates the string units SU0to SU3from other string units (not illustrated) adjacent to the string units SU0to SU3. In addition, the slits SHE_X and SHE_Y divides the stacked wiring layers corresponding to the select gate lines SGD into the select gate lines SGD0to SGD3that correspond to the string units SU0to SU3, respectively, and the select gate line SGDX that does not correspond to any string unit SU such that the select gate lines SGD0to SGD3and the select gate line SGDX are insulated and separated from each other.

This way, regions divided by the slits SLT, SHE_X, and SHE_Y constitute the string units SU0to SU3, respectively. In the memory cell array10, the same layout as illustrated inFIG. 3is repeatedly arranged along the Y-axis.

In the cell region CA illustrated inFIG. 3, the memory pillars MP are arranged in a region between adjacent slits SLT, for example, in a staggered arrangement of 16 rows. That is, in each of the string units SU0to SU3, the memory pillars MP are arranged in a staggered arrangement of 4 rows. Each of the memory pillars MP include: a portion (lower pillar LP) that is formed in a memory hole; and a portion (upper pillar UP) that is formed in a SGD hole. The upper pillar UP is higher than the lower pillar LP and, for example, has a smaller diameter than the lower pillar LP.

A set including the upper pillar UP and the lower pillar LP, that is, a memory cell array plane has an overlapping portion in a plan view when seen from the top. In this plan view, a central axis of the upper pillar UP and a central axis of the lower pillar LP may overlap each other or may not overlap each other. Here, the central axis is defined as an axis that passes through the center of each of the upper pillar UP and the lower pillar LP on any XY cross-section along the Z-axis. The XY cross-section refers to, for example, a surface where the upper pillar UP and the lower pillar LP are in contact with each other. In a plan view ofFIG. 3, the lower pillar LP is arranged not to overlap the slit SHE_X. In addition, in the memory pillar MP that is arranged in the vicinity of a slit SHE_X or a slit SLT (e.g. nearest the slit SHE_X or the slit SLT, of the memory pillars MP in a given strung unit SU) the central axis of the upper pillar UP is arranged to deviate from the central axis of the lower pillar LP in a direction away from the slit SHE_X or SLT. This way, in the semiconductor storage device1according to the first embodiment, a layout for avoiding contact with the memory pillar MP may be designed for the slit SHE_X or SLT.

Each of the bit lines BL extends along the Y-axis and are arrayed along the X-axis. In a plan view, each of the bit lines BL is arranged to overlap at least one upper pillar UP per string unit SU. In each of the upper pillars UP, two bit lines BL overlap each other. The contact CP is provided between one bit line BL among the bit lines BL that overlap the upper pillar UP and the upper pillar UP. The string unit Su is electrically connected to the corresponding bit line BL via the contact CP formed in the upper pillar UP.

In the hookup region HA ofFIG. 3, in the three layers of select gate lines SGD, a portion corresponding to the select gate line SGDX forms a staircase shape in a direction away from the cell region CA along the X-axis. That is, in a plan view, three stacked wiring layers constituting the select gate line SGDX have a region in which a lower wiring layer extends longer along the X-axis and does not overlap an upper wiring layer.

A set including the word lines WL5to WL7, a set including the word lines WL2to WL4, and a set including the select gate line SGS and the word lines WL0and WL1form a staircase shape along the X-axis. That is, in a plan view, the set including the word lines WL5to WL7have a region that is longer than the select gate lines SGD along the X-axis and does not overlap the select gate lines SGD. The set including the word lines WL2to WL4has a region B that is longer than the set including the word lines WL5to WL7along the X-axis and does not overlap the region A of the set including the word lines WL5to WL7. The set including the select gate line SGS and the word lines WL0and WL1has a region C that is longer than the set including the word lines WL2to WL4along the X-axis and does not overlap the region B of the set including the word lines WL2to WL4.

In addition, each of the set including the word lines WL5to WL7, the set including WL2to WL4, and the set including the select gate line SGS and the word lines WL0and WL1further forms a staircase shape along the Y-axis at an end portion of the staircase shape along the X-axis. That is, in the region A, the word line WL6has a region T_WL6that does not overlap a region T_WL7of the word line WL7, the word line WL5has a region T_WL5that does not overlap the regions T_WL6and T_WL7, and the regions T_WL5to T_WL7are aligned along the Y-axis. In the region B, the word line WL3has a region T_WL3that does not overlap a region T_WL4of the word line WL4, the word line WL2has a region T_WL2that does not overlap the regions T_WL3and T_WL4, and the regions T_WL2to T_WL4are aligned along the Y-axis. In the region C, the word line WL0has a region T_WL0that does not overlap a region T_WL1of the word line WL1, the select gate line SGS has a region T_SGS that does not overlap the regions T_WL0and T_WL1, and the regions T_SGS, T_WL0, and T_WL1are aligned along the Y-axis.

Contacts CC_SGD0to CC_SGD3, CC_WL0to CC_WL7, and CC_SGS are provided on the select gate lines SGD0to SGD3, the regions T_WL0to T_WL7of the word lines WL0to WL7, and the region T_SGS of the select gate line SGS. The contacts CC_SGD0to CC_SGD3are in contact with upper surfaces of the three layers of stacked wiring layers of the select gate lines SGD0to SGD3, respectively. The diameter of the contact CC_SGD on the upper surface of the uppermost layer of the select gate lines SGD is larger than the diameters of the contacts CC_WL and CC_SGS. The diameter of the contact CC_SGD will be described in detail inFIG. 8.

The planar layout of the memory cell array10described above is merely an example, and the present disclosure is not limited thereto. For example, the number of the slits SHE or the number of the string units SU arranged between adjacent slits SLT may be designed according to specifications. In addition, the number and arrangement of the memory pillars MP, the bit lines BL connected to the memory pillars MP, and the like may be designed according to specifications. The number of steps in the staircase shape along the Y-axis in the arrangement of the regions T_SGS and T_WL0to T_WL7may be designed according to specifications, and the stair along the Y-axis is not necessarily provided.

1.1.3.2 Cell Region

FIG. 4illustrates an example of a cross-sectional structure of the memory cell array10of the semiconductor storage device according to the first embodiment ofFIG. 3taken along line IV-IV. As illustrated inFIG. 4, a conductor layer21is provided above the semiconductor substrate20via an insulator layer (not illustrated). In this insulator layer, a circuit such as the sense amplifier module16may be provided. The conductor layer21is formed, for example, in a plate shape spread along an XY plane and forms the source line SL. The conductor layer21includes, for example, silicon (Si).

A conductor layer22is provided above the conductor layer21via an insulator layer (not illustrated). The conductor layer22is used as the select gate line SGS.

A plurality of insulator layers (not illustrated) and a plurality of conductor layers23are alternately stacked above the conductor layer22. For example, the conductor layers23are used as the word lines WL0to WL7in order from the semiconductor substrate20side. The conductor layers22and23are formed, for example, in a plate shape spread along an XY plane and include, for example, tungsten (W).

A plurality of insulator layers (not illustrated) and a plurality of conductor layers24are alternately stacked above the conductor layer23stacked as the uppermost layer. The distance between the conductor layer23as the uppermost layer and the conductor layer24as the lowermost layer in the Z direction is more than the distance between adjacent conductor layers23or between adjacent conductor layers24in the Z direction. That is, the thickness of the insulator layer (INS, not illustrated) between the conductor layer23as the uppermost layer and the conductor layer24as the lowermost layer is more than the thickness of the insulator layer between adjacent conductor layers23or between adjacent conductor layers24(e.g., by a factor of approximately 1.5 or more, approximately 2 or more, approximately 5 or more, or greater). The stacked conductor layers24are used as select gate lines SGDa, SGDb, and SGDc in order from the semiconductor substrate20side, respectively. The select transistor ST1is provided in a portion of the upper pillar UP corresponding to the select gate lines SGDa to SGDc. The conductor layer24is formed, for example, in a plate shape spread along the XY plane and includes, for example, tungsten (W).

A conductor layer25is provided above the conductor layer24stacked as the uppermost layer via an insulator layer (not illustrated). For example, a plurality of conductor layer25extends along the Y-axis, are linearly arranged along the X-axis, and are used as the bit lines BL, respectively. The conductor layer25includes, for example, copper (Cu).

The memory pillar MP extends along the Z-axis. Specifically, the lower pillar LP in the memory pillar MP penetrates the conductor layers22and23, and the bottom portion thereof is in contact with the conductor layer21. The upper pillar UP in the memory pillar MP penetrates the conductor layers24and is in contact with the lower pillar LP.

In addition, in the memory pillar MP, the lower pillar LP includes, for example, a core member30, a semiconductor layer31, a stacked film32, and a semiconductor portion33, and the upper pillar UP includes, for example, a core member40, a semiconductor layer41, a semiconductor layer42, a stacked film43, and a semiconductor portion44. The upper pillar UP is formed such that apart of the semiconductor layer41is buried in an upper end of the lower pillar LP. As a result, the upper pillar UP is electrically connected to the lower pillar LP in an improved manner.

The core member30of the lower pillar LP extends along the Z-axis, an upper end of the core member30is located to be higher than, for example, the conductor layer23as the uppermost layer, and a lower end of the core member30of the upper pillar UP is located, for example, in the conductor layer21. The core member30includes, for example, an insulator such as silicon oxide (SiO2).

The semiconductor layer31covers a bottom surface and a side surface of the core member30and includes, for example, a cylindrical portion. A lower end of the semiconductor layer31(e.g. a protruding portion) is in contact with the semiconductor layer21, and an upper end of the semiconductor layer31is located to be higher than the conductor layer23as the uppermost layer.

The stacked film32covers a side surface and a bottom surface of the semiconductor layer31other than the portion where the conductor layer21and the semiconductor layer31are in contact with each other, and includes, for example, a cylindrical portion. A layer structure of the stacked film32will be described in detail with reference toFIG. 5.

The semiconductor portion33covers an upper surface of the core member30and is in contact with an inner wall portion of the semiconductor layer31located above the core member30and a lower end of the semiconductor layer41formed immediately above the semiconductor portion33. The semiconductor portion33is, for example, cylindrical.

The core member40extends along the Z-axis. A lower end of the core member40is located between the conductor layer23as the uppermost layer and the conductor layer24as the lowermost layer. An upper end of the core member40is located to be higher than a layer where the conductor layer24as the uppermost layer is provided.

The semiconductor layer41covers a bottom surface and a side surface of the core member40and includes, for example, a cylindrical portion. A lower end of the semiconductor layer41(e.g. a protruding portion) is in contact with the semiconductor portion33such that the semiconductor layer41and the lower pillar LP are electrically connected to each other, and an upper end of the semiconductor layer41is located to be higher than the conductor layer24as the uppermost layer.

The semiconductor layer42includes a cylindrical portion of the semiconductor layer41that covers at least a side surface of a portion intersecting the conductor layer24.

The stacked film43is a gate insulating film of the select transistor, covers a side surface of the semiconductor layer42, and includes a cylindrical portion. A layer structure of the stacked film43will be described in detail with reference toFIG. 7.

The semiconductor portion44covers an upper surface of the core member40and is in contact with an inner wall of a portion of the semiconductor layer41that is provided above the core member40. The semiconductor portion44is provided, for example, in a cylindrical shape and reaches an upper end of the upper pillar UP.

The columnar contact CP is provided on upper surfaces of the semiconductor layer41, the semiconductor layer42, and the semiconductor portion44in the memory pillar MP. A cross-sectional view ofFIG. 4illustrates the contacts CP corresponding to two memory pillars MP among four memory pillars MP. Regarding the remaining two memory pillars MP for which the contacts CP are not illustrated, the contacts CP are provided in a cross-section on a depth side or a front side ofFIG. 4. An upper surface of each of the contacts CP is in contact with one conductor layer25(bit line BL) corresponding thereto and is electrically connected thereto.

The slit SLT extends in a plate shape along, for example, an XZ plane and divides the conductor layers22to24in the Y direction. An upper end of the slit SLT is located between the conductor layer24and the conductor layer25. A lower end of the slit SLT is located, for example, in a layer where the conductor layer21is provided. The slit SLT includes, for example, an insulator such as silicon oxide.

The slit SHE_X extends in a plate shape along, for example, an XZ plane and divides the conductor layers24in the Y direction. An upper end of the slit SHE_X is located between the conductor layer24and the conductor layer25. A lower end of the slit SHE_X is located, for example, between a layer where the conductor layer23as the uppermost layer is provided and a layer where the conductor layer24is provided. The slit SHE_X includes, for example, an insulator such as silicon oxide.

The upper end of the slit SLT, the upper end of the slit SHE_X, and the upper end of the memory pillar MP may be aligned or may not be aligned.

FIG. 5is an XY cross-sectional view illustrating the memory pillar MP ofFIG. 4taken along line V-V and illustrates an example of a cross-sectional structure including the lower pillar LP and the conductor layer23formed around the lower pillar LP.

As illustrated inFIG. 5, the core member30is provided substantially at the center of the lower pillar LP. Further, the semiconductor layer31and the stacked film32are concentrically provided around the core member30. That is, the semiconductor layer31and the stacked film32are formed along the Z direction to surround the entire side surface of the core member30. The stacked film32is a film in which a tunnel insulating film35, an insulating film36, and a block insulating film37are stacked in this order.

Each of the tunnel insulating film35and the block insulating film37includes, for example, silicon oxide. The insulating film36includes, for example, silicon nitride (SiN).

FIG. 6is an XY cross-sectional view illustrating the memory pillar MP ofFIG. 4taken along line VI-VI and illustrates an example of a cross-sectional structure of the upper pillar UP.

As illustrated inFIG. 6, the core member40is provided substantially at the center of the upper pillar UP. Further, the semiconductor layer41, the semiconductor layer42, and the stacked film43are concentrically provided around the core member40. That is, the semiconductor layer41, the semiconductor layer42, and the stacked film43are formed along the Z direction to surround the entire side surface of the core member40. The stacked film43is a film in which a tunnel insulating film45, an insulating film46, and a block insulating film47are stacked in this order.

Each of the tunnel insulating film45and the block insulating film47includes, for example, silicon oxide. The insulating film46includes, for example, silicon nitride (SiN).

In the structure of the memory pillar MP described above, a portion where the memory pillar MP and the conductor layer22intersect each other functions as the select transistor ST2. A portion where the memory pillar MP and the conductor layer23intersect each other functions as the memory cell transistor MT. A portion where the memory pillar MP and the conductor layer24intersect with each other functions as the select transistor ST1.

That is, the semiconductor layer31is used as a channel of each of the memory cell transistor MT and the select transistor ST2. The insulating film36is used as a charge storage layer of the memory cell transistor MT and the select transistor ST2. The semiconductor layer41is used as a channel of the select transistor ST1and as an electrical connection portion between the upper pillar UP and the lower pillar LP. The insulating film46is used as a charge storage layer of the select transistor ST1. As a result, each of the memory pillars MP functions as, for example, one NAND string NS.

The structure of the memory cell array10described above is merely exemplary, and the memory cell array10may have another structure. For example, the number of the conductor layers23is designed based on the number of the word lines WL. The number of layers of the select gate lines SGD is not limited to three and may be any appropriate number. The conductor layers22that are provided in a plurality of layers may be assigned to the select gate line SGS. When the select gate line SGS is provided in a plurality of layers, a conductor different from the conductor layer22may also be used. The memory pillar MP and the conductor layer25may be electrically connected to each other via two or more contacts or may be electrically connected to each other via another wiring. The inside of the slit SLT may be configured with multiple kinds of insulators.

FIG. 7illustrates an example of a cross-sectional structure of the memory cell array10of the semiconductor storage device according to the first embodiment ofFIG. 3taken along line VII-VII. As illustrated inFIG. 7, the conductor layers21to24extend along the X-axis and reach the hookup region HA.

Columnar contacts CC_WL1, CC_WL4, and CC_WL7are provided on upper surfaces of the conductor layers23used as the word lines WL1, WL4, and WL7. Upper surfaces of the contacts CC_WL1, CC_WL4, and CC_WL7are in contact with one conductor layer80_1, one conductor layer80_4, and one conductor layer80_7corresponding thereto and are electrically connected thereto. On upper surfaces of the conductor layers23that are used as the word lines WL0, WL3, and WL6among the remaining word lines WL for which the contacts CC_WL are not illustrated, the contacts CC_WL0, CC_WL3, and CC_WL6are provided in a cross-section on a front side ofFIG. 7, respectively. On an upper surface of the conductor layer22used as the select gate line SGS and on upper surfaces of the conductor layers23that are used as the word lines WL2and WL5, the contacts CC_SGS, CC_WL2, and CC_WL5are provided on a front side further than the cross-section where the contacts CC_WL0, CC_WL3, and CC_WL6are provided, respectively.

The columnar contact CC_SGD is in contact with upper surfaces of the three layers of conductor layers24used as the select gate lines SGDa, SGDb, and SGDc, respectively. A cross-sectional view ofFIG. 7illustrates the contact CC_SGD0corresponding to the string unit SU0among the four contacts CC_SGD. The remaining three contacts CC_SGD1to CC_SGD3(not illustrated) are provided in a cross-section on a front side ofFIG. 7. An upper surface of each of the contacts CC_SGD is in contact with one conductor layer81corresponding thereto and is electrically connected thereto.

The contact CC_SGD has a cross-section having a diameter Δ1 along a lower surface of the select gate line SGDb as the second layer from the bottom, has a cross-section having a diameter Δ1+2Δ2 more than the diameter Δ1 along a lower surface of the select gate line SGDc as the third layer (uppermost layer) from the bottom, and has a diameter Δ3 more than the diameter Δ1+2Δ2 along an upper surface of the select gate line SGDc as the uppermost layer. An XY cross-section of the contact CC_SGD on the lower surface of the select gate line SGDb and an XY cross-section of the contact CC_SGD on the lower surface of the select gate line SGDc are similar to each other, and the centers thereof match each other in a plan view.

The slit SHE_Y extends in a plate shape along, for example, an YZ plane and divides the conductor layers24in the X direction. The slit SHE_Y includes an upper end and a lower end, for example, at the same height as that of the slit SHE_X and includes an insulator such as silicon oxide as in the slit SHE_X.

The three layers of conductor layers24are divided into a portion including the select gate lines SGDa to SGDc and a portion including the select gate line SGDX by the slit SHE_Y. In the portion including the select gate line SGDX, the conductor layer24as the lowermost layer is longer than the conductor layer24as the second layer from the bottom along the X-axis by a difference δ1, and the conductor layer24as the second layer from the bottom is longer than the conductor layer24as the uppermost layer by a difference Δ2. This way, the difference Δ2 between the length of the conductor layer24as the second layer from the bottom and the length of the conductor layer24as the uppermost layer along the X-axis corresponds to the difference (2Δ2) between the diameter of the contact CC_SGD along the lower surface of the conductor layer24as the second layer from the bottom and the diameter of the contact CC_SGD along the lower surface of the conductor layer24as the uppermost layer. The difference Δ1 may be “0” (that is, the conductor layer24as the lowermost layer and the conductor layer24as the second layer from the bottom may have the same length along the X-axis).

FIG. 8illustrates an example of an enlarged plan view of a region VIII ofFIG. 3in the three layers of select gate lines SGD according to the first embodiment when seen from the top. InFIG. 8, the contact CC_SGD and the interlayer insulator layer are not illustrated, and an outer edge of the surface of the contact CC_SGD having the diameter Δ3 that is in contact with the upper surface of the conductor layer24as the uppermost layer is indicated by a chain line.

As illustrated inFIG. 8, a through via hole having the diameter Δ1+2Δ2 is formed in the conductor layer24as the uppermost layer used as the select gate line SGDc. A through via hole having the diameter Δ1 is formed in the conductor layer24as the second layer from the bottom used as the select gate line SGDb. The shape of the through via hole having the diameter Δ1+2Δ2 is similar to that of the through via hole having the diameter Δ1, and the center of the through via hole having the diameter Δ1+2Δ2 matches the center of the through via hole having the diameter Δ1 in a plan view.

The example ofFIG. 8shows a case where the through via hole having the diameter Δ1 and the through via hole having the diameter Δ1+2Δ2 are circular, but the present disclosure is not limited thereto. For example, the through via hole having the diameter Δ1 and the through via hole having the diameter Δ1+2Δ2 may have any appropriate shape such as a rectangular shape (e.g. in which widths of the rectangles may correspond to the diameters disclosed herein). InFIG. 8, the outer edge of the surface of the contact CC_SGD that is in contact with the upper surface of the conductor layer24as the uppermost layer may have any appropriate shape in a range including the through via hole having the diameter Δ1+2Δ2. The outer edge does not necessarily match the shape of the through via hole having the diameter Δ1 and the through via hole having the diameter Δ1+2Δ2 and may not match the centers of the through via holes.

1.2 Method of Manufacturing Semiconductor Storage Device

Hereinafter, an example of a series of manufacturing steps of the semiconductor storage device according to the first embodiment from the formation of a stacked structure corresponding to the word lines WL to a step of the formation of the contact CC_SGD corresponding to the select gate lines SGD will be described. Each ofFIGS. 9 to 24illustrates an example of a cross-sectional structure that includes a structure corresponding to the memory cell array in a manufacturing step of the semiconductor storage device according to the first embodiment. The cross-sectional view of the manufacturing step referred to below includes a cross-section perpendicular to the surface of the semiconductor substrate20. In addition, a region illustrated in the cross-sectional view of each of the manufacturing steps includes a region where the contacts CC_WL1, CC_WL4, CC_WL7, and CC_SGD0and the slit SHE_Y in the hookup region HA and one memory pillar MP in the cell region CA are to be formed.

First, as illustrated inFIG. 9, a sacrificial material52corresponding to the select gate line SGS and sacrificial materials53corresponding to the word lines WL are stacked, and then a staircase structure is formed in a portion corresponding to the regions A to C of the hookup region HA.

Specifically, first, the insulator layer50and the conductor layer21are sequentially stacked on the semiconductor substrate20. The insulator layer51and the sacrificial material52are stacked on the conductor layer21, and the insulator layer51and the sacrificial material53are alternately stacked on the sacrificial material52multiple times.

Next, a mask (not illustrated) is provided on an upper surface of the sacrificial material53, and a pattern is formed by lithography in a portion of the mask corresponding to the regions A to C. Next, an operation of performing anisotropic etching on the stacked structure of the sacrificial materials52and53and the insulator layer51based on the obtained pattern and an operation of slimming the mask pattern to remove a portion of the mask pattern are sequentially repeated. As a result, etching can be performed such that the portion of the stacked structure corresponding to the regions A to C form a staircase shape along the X direction and the Y direction. In this step, anisotropic etching is, for example, RIE (Reactive Ion Etching).

Next, the staircase structure is buried up to the position of the sacrificial material53as the uppermost layer by an insulator layer54, and an insulator layer55is stacked on the insulator layer54and the sacrificial material53as the uppermost layer. The insulator layers51,54, and55include, for example, silicon oxide (SiO2). The number of the sacrificial materials52and53formed correspond to the number of the select gate line SGS and the word lines WL to be stacked. The sacrificial materials52and53include, for example, silicon nitride (SiN).

Next, as illustrated inFIG. 10, a memory hole H0corresponding to the lower pillar LP is formed. Specifically, first, a mask in which a region corresponding to the memory hole H0is open is formed by lithography. Next, the memory hole H0is formed by anisotropic etching using the formed mask.

The memory hole H0formed in this step penetrates the insulator layer51, the sacrificial materials52and53, and the insulator layer55and reaches the conductor layer21(and may extend through a portion of the conductor layer21). In this step, anisotropic etching is, for example, RIE (Reactive Ion Etching).

Next, as illustrated inFIG. 11, a stacked structure in the memory hole H0, that is, the lower pillar LP is formed.

Specifically, the block insulating film37, the insulating film36, and the tunnel insulating film35are sequentially formed on a side surface and a bottom surface of the memory hole H0and an upper surface of the insulator layer55such that the stacked film32is formed. After removing the stacked film32in the bottom portion of the memory hole H0(e.g. to expose the conductor21), the semiconductor layer31and the core member30are sequentially formed to bury the inside of the memory hole H0. Next, the core member30in a range from the upper end of the memory hole H0to a predetermined depth is removed together with a portion that remains being higher than the insulator layer54.

Next, the semiconductor portion33is formed to bury the inside of the memory hole H0. Next, the semiconductor portion33, the semiconductor layer31, and the stacked film32that are higher than the insulator layer54are removed. As a result, the lower pillar LP is formed.

Next, as illustrated inFIG. 12, after forming the insulator layer56on the upper surfaces of the lower pillar LP and the insulator layer55, sacrificial materials57corresponding to the select gate lines SGD and insulator layers58are alternately stacked. An insulator layer59is formed on the sacrificial material57as the uppermost layer. The insulator layers56,58, and59include silicon oxide, and the sacrificial material57includes silicon nitride.

Next, as illustrated inFIG. 13, the insulator layer59and the sacrificial material57as the uppermost layer corresponding to the regions A to C are removed. Specifically, a mask (not illustrated) is provided on an upper surface of the insulator layer59, and a portion of the mask corresponding to the regions A to C is removed by lithography. Next, anisotropic etching is performed on the insulator layer59and the sacrificial material57based on the obtained mask. The position of an end portion of the sacrificial material57that is formed in this step and extends along the Y-axis corresponds to the position of an end portion of the conductor layer24as the lowermost layer.

Next, as illustrated inFIGS. 14 to 16, a staircase shape is formed at end portions of the three layers of sacrificial materials57in the hookup region HA, and a hole for enabling the contact CC_SGD to reach the conductor layer24as the lowermost layer is formed.

Specifically, as illustrated inFIG. 14, in the mask formed in the step described with reference toFIG. 13, a portion corresponding to a region within δ1 from the end portion of the sacrificial material57along the X-axis and a portion corresponding to the region having the diameter Δ1 with which the contact CC_SGD is to come into contact on the upper surface of the conductor layer24as the lowermost layer are removed by lithography to form a mask pattern. Next, anisotropic etching is performed on the insulator layer59and the sacrificial material57based on the obtained mask pattern. As a result, the end portion of the sacrificial material57as the uppermost layer is shortened along the X-axis by δ1. In addition, a hole H1including the through via hole having the diameter Δ1 is formed in the sacrificial material57as the uppermost layer. In this step, anisotropic etching is, for example, RIE (Reactive Ion Etching).

Next, as illustrated inFIG. 15, by slimming the mask pattern on the insulator layer59, in the mask pattern, a portion corresponding to a region within Δ2 from the end portion of the sacrificial material57as the uppermost layer along the X-axis and a portion corresponding to a region that is isotropically widened from an outer edge of the hole H1by42are removed. Next, anisotropic etching is performed on the insulator layer59and the sacrificial material57based on the obtained mask pattern. As a result, the end portion of the sacrificial material57as the uppermost layer is further shortened along the X-axis by Δ2, and the end portion of the sacrificial material57as the second layer from the bottom is further shortened along the X-axis by δ1. In addition, a hole H2including the through via hole having the diameter Δ1+2Δ2 that is formed in the sacrificial material57as the uppermost layer and the through via hole having the diameter Δ1 that is formed in the sacrificial material57as the second layer from the bottom is formed. In this step, anisotropic etching is, for example, RIE (Reactive Ion Etching).

Next, as illustrated inFIG. 16, an insulator layer60is filled in the portion of the sacrificial material57and the insulator layers58and59removed in the steps described with reference toFIGS. 14 and 15.

Next, as illustrated inFIG. 17, a SGD hole H3corresponding to the upper pillar UP is formed. Specifically, first, a mask in which a region corresponding to the SGD hole H3is open is formed by lithography. Next, the SGD hole H3is formed by anisotropic etching using the formed mask.

The SGD hole H3penetrates the insulator layers59,58, and56and the sacrificial material57and reaches the semiconductor portion33of the lower pillar LP. In this step, anisotropic etching is, for example, RIE (Reactive Ion Etching).

Next, as illustrated inFIG. 18, a stacked structure in the SGD hole H3is formed. Specifically, the block insulating film47, the insulating film46, and the tunnel insulating film45are sequentially formed to form the stacked film43, and then the semiconductor layer42is formed. The semiconductor layer42and the stacked film43in the bottom portion of the SGD hole H3are removed by anisotropic etching (for example, RIE), and the upper surface of the semiconductor portion33is exposed.

Next, in the SGD hole H3, the semiconductor layer41is formed to be in contact with the semiconductor portion33(e.g., to protrude into the semiconductor portion33). As a result, the semiconductor layer31and the semiconductor layer41form a current path (channel path) of a cell current flowing through the inside of the memory pillar MP via the semiconductor portion33.

Next, the core member40is formed on the semiconductor layer41in the SGD hole H3. Next, a part of the core member40in an upper portion of the SGD hole H3is removed, and this space is filled with the semiconductor portion44. The stacked film43, the semiconductor layer42, the semiconductor layer41, the core member40, and the semiconductor portion44that are higher than the insulator layer59are removed, for example, by CMP. As a result, the upper pillar UP is formed in the SGD hole H3.

Specifically, first, a hole (not illustrated) corresponding to the slit SLT is formed. The hole formed in this step divides the insulator layers51, the sacrificial materials52and53, the insulator layers55and56, the sacrificial materials57, and the insulator layers58and59. Next, a surface of the conductor layer21exposed in the hole is oxidized, and a protective oxide film (not illustrated) is formed. Next, the sacrificial materials52,53, and57are selectively removed, for example, by wet etching using hot phosphoric acid. The structure from which the sacrificial materials52,53, and57are removed is maintained as a three-dimensional structure by a plurality of memory pillars MP and the like.

Next, the space formed by removing the sacrificial materials52,53, and56is filled with a conductor via the hole, and an insulator layer corresponding to the slit SLT is formed in the hole. In this step, for example, CVD is used. A portion of the conductor that is formed in the hole and on the upper surface of the insulator layer59is removed by an etch-back process. As a result, a conductor formed between adjacent wiring layers is separated, and the conductor layer22, the conductor layers23, and the conductor layers24are formed. The conductor layers22,23, and24formed in this step may include a barrier metal. In this case, during the formation of the conductor after the removal of the sacrificial materials52,53, and57, for example, titanium nitride (TiN) is deposited as the barrier metal, and tungsten is formed.

Next, as illustrated inFIG. 20, a hole H4corresponding to the slits SHE_X and SHE_Y is formed.FIG. 20illustrates a portion of the hole H4corresponding to the slit SHE_Y. Specifically, first, a mask in which a region corresponding to the slits SHE_X and SHE_Y is open is formed by lithography. Next, the hole H4is formed by anisotropic etching (for example, RIE) using the formed mask. The hole H4formed in this step divides the insulator layers59and58and the conductor layers24and reaches the insulator layer56(e.g. extends into the insulator layer56).

Next, as illustrated inFIG. 21, an insulator layer61corresponding to the slits SHE_X and SHE_Y is formed on the insulator layers59and60to fill the hole H4. The insulator layer61formed to be higher than the insulator layers59and60is removed, for example, by an etch-back process. The insulator layer61includes, for example, silicon oxide.

Next, as illustrated inFIG. 22, a conductor layer62is formed on an upper surface of the semiconductor portion44of the memory pillar MP. While forming the conductor layer25on an upper surface of the conductor layer62, an insulator layer63is formed to bury the conductor layer62and the conductor layer25over the surface.

Next, as illustrated inFIG. 23, a plurality of holes H5corresponding to the contacts CC_SGD0to CC_SGD3, respectively, and a plurality of holes H6corresponding to the contacts CC_SGS and CC_WL0to CC_WL7, respectively, are formed. Among the holes H5and the holes H6,FIG. 23illustrates one hole H5corresponding to the contact CC_SGD0and three holes H6corresponding to the contacts CC_WL1, CC_WL4, and CC_WL7.

Specifically, first, a mask in which a region corresponding to the holes H5and H6is open is formed by lithography. Next, the holes H5and H6are formed by anisotropic etching using the formed mask. An opening corresponding to the hole H6is formed to include the through via hole having the diameter Δ1+2Δ2 that is formed on the conductor layer24as the uppermost layer.

In this step, anisotropic etching is, for example, RIE (Reactive Ion Etching), and a condition where substantially no conductor layers22to24are etched while selectively removing oxides and nitrides is implemented. As a result, the hole H5reaches an upper surface of each of the conductor layer24as the uppermost layer, the conductor layer24as the second layer, and the conductor layer24as the lowermost layer. The hole H5has a diameter Δ3 on the upper surface of the conductor layer24as the uppermost layer, has the diameter Δ1+2Δ2 on the upper surface of the conductor layer24as the second layer from the bottom, and has the diameter Δ1 on the upper surface of the conductor layer24as the lowermost layer. The hole H6penetrates the insulator layers63,60,56, and55, reaches the conductor layer23as the uppermost layer, further penetrates the insulator layer54, and reaches another conductor layer23and the conductor layer22.

Next, as illustrated inFIG. 24, conductor layers64and65are formed to fill the inside of the holes H5and H6. Next, the conductor layers64and65that are higher than the insulator layer63are removed.

In the manufacturing steps of the semiconductor storage device according to the first embodiment described above, the memory pillar MP, the source line SL, the word lines WL, and the select gate lines SGS and SGD connected to the memory pillar MP, and the contacts CC_SGS, CC_WL0to CC_WL7, and CC_SGD0to CC_SGD3are formed. The manufacturing steps described above are merely exemplary. Another process may be inserted between the manufacturing steps, and the order of the manufacturing steps may be switched within a range where no problems arise.

1.3 Effect of Embodiment

With the configuration of the first embodiment, the select gate lines SGD and the contact CC_SGD can be connected to each other in an improved manner. More specifically, the contact CC_SGD is in contact with the upper surfaces of the conductor layers24that function as the select gate lines SGD, respectively. Therefore, a sufficient contact area with the conductor layers24can be sufficiently secured. Therefore, the resistance of the connection portions can be reduced.

In addition, all the conductor layers24can be electrically connected by one contact CC_SGD. Therefore, a terrace region for forming the contact CC_SGD can be omitted from the conductor layers24. Therefore, the lengths of the select gate lines SGD along the X-axis can be shortened.

In addition, in order to form the above-described contact CC_SGD, the step of performing etching based on the mask pattern formed by slimming is appropriately repeated according to the number of the select gate lines SGD stacked. As a result, in the sacrificial materials57, the through via hole of which the diameter decreases stepwise toward the lower layer is formed, and a staircase shape having a terrace width corresponding to the diameter of the through via hole is formed. The difference Δ2 between the diameter of the through via hole of the sacrificial material57as the second layer from the bottom and the diameter of the through via hole of the sacrificial material57as the uppermost layer matches the difference Δ2 between the length of the sacrificial material57as the second layer from the bottom and the length of the sacrificial material57as the uppermost layer along the X-axis.

In addition, with the configuration of the first embodiment, the slit SHE includes the slit SHE_X that extends along the X-axis and the slit SHE_Y that extends along the Y-axis. As a result, the select gate lines SGD are divided into the select gate lines SGD0to SGD3that correspond to the string units SU0to SU3, respectively, and the select gate line SGDX that does not correspond to any string unit SU and is located at the end portion of the select gate lines SGD along the X-axis. Therefore, the slit SHE_X can insulate and divide the select gate lines SGD for each of the string units SU without dividing all the select gate lines SGD along the X-axis (without dividing all the select gate lines SGD up to the slit SHE_Y).

The effects of the configuration will be further described usingFIGS. 25 and 26.FIG. 25illustrates a comparative example to describe the effects of the semiconductor storage device according to the first embodiment and corresponds toFIG. 3of the first embodiment.FIG. 26is a cross-sectional view taken along line XXVI-XXVI ofFIG. 25. In the comparative examples ofFIGS. 25 and 26, each of a plurality of slits SHE_X extends along the X-axis to be longer than a plurality of conductor layers24. As a result, the slits SHE_X divide the wiring layers corresponding to the select gate lines SGD into the select gate lines SGD0to SGD3without forming the select gate lines SGDX such that the select gate lines SGD0to SGD3are insulated and separated from each other. Accordingly, the insulator layer corresponding to the slit SHE_Y that divides the three layers of conductor layers24in the hookup region HA along the Y direction is not present. In the comparative example ofFIGS. 25 and 26, a contact CC_SGDp extends upward from the upper surface of the conductor layer24as the lowermost layer and is in contact with a side surface of another conductor layer24.

As can be seen fromFIG. 25, when the slit SHE_Y is not formed, the slit SHE_X reaches a region OEA not including the three layers of conductor layers24in a plan view. In addition, as can be seen fromFIG. 26, in the region OEA, a stacked structure is formed with an oxide or a nitride and a metal layer is not provided up to a depth of the conductor layers23.

Under an etching condition that is applied to the formation of the hole H4corresponding to the slit SHE_X, etching rapidly progresses in the stacked structure formed of an oxide or a nitride, but etching is not likely to progress in the metal layer. Therefore, during the formation of the hole H4, the region OEA may be over-etched up to a depth of the conductor layers23. In this case, the conductor layers23have a distorted shape after etching such that an unintended leakage current or the like may be generated.

According to the first embodiment, by forming the slit SHE_Y, the slit SHE_X does not reach the region OEA. As a result, the layer structure that is etched during the formation of the hole H4is limited to a region including the three layers of conductor layers24in a plan view. Therefore, the etching of the hole H4up to the conductor layers23can be avoided from progressing up to the conductor layers23. Accordingly, the slit SHE_X and the conductor layers23can be prevented from having a distorted shape, and the generation of an unintended leakage current in the conductor layers23can be prevented.

1.4 Modification Example

The above-described first embodiment may be modified in various ways.

1.4.1 First Modification Example

In the description of the first embodiment, the structure in which the contact CC_SGD is in contact with the upper surface of each of the conductor layers24is provided, but the present disclosure is not limited thereto. For example, a via having a sufficient contact area with a side surface of each of the conductor layers24may be formed, and a contact may be formed on an upper surface of the via. In the following description, the same configuration and manufacturing method as those of the first embodiment will not described, and different points from those of the first embodiment will be mainly described.

FIG. 27is a plan view illustrating a planar layout of a memory cell array of a semiconductor storage device according to a first modification example of the first embodiment and corresponds toFIG. 3of the first embodiment.

As illustrated inFIG. 27, vias CV_SGD0to CV_SGD3are in contact with the select gate lines SGD0to SGD3, respectively. Contacts CC′_SGD0to CC′_SGD3are provided on upper surfaces of the vias CV_SGD0to CV_SGD3. The diameter of the via CV_SGD is more than that of the contact CC′_SGD.

FIG. 28illustrates an example of a cross-sectional structure of the memory cell array10ofFIG. 27taken along line XXVIII-XXVIII and corresponds toFIG. 7of the first embodiment. As illustrated inFIG. 28, the via CV_SGD is provided on the upper surface of the conductor layer24as the lowermost layer and extends in the other conductor layers24(in the example ofFIG. 28, the conductor layer24as the second layer from the bottom and the conductor layer24as the uppermost layer) excluding the conductor layer24as the lowermost layer along the Z-axis. That is, the via CV_SGD is in contact with the upper surface of the conductor layer24as the lowermost layer and is in contact with side surfaces of the other conductor layers24.

As described above, the diameter of the via CV_SGD is more than that of the contact CC′_SGD. Therefore, a sufficient contact area with the conductor layers24in contact with the via on the side surfaces can be secured. As a result, the contact resistance between the select gate lines SGD and the contact CC′_SGD can be reduced.

In addition, the conductor layers24are electrically connected to the contact CC′_SGD using one via CV_SGD. Therefore, it is not necessary to form the conductor layers24stepwise in order to form a plurality of contacts corresponding to the conductor layers24, respectively. As a result, the area of a region for forming the contact CC′_SGD can be further reduced as compared to a case where the contact CC′_SGD is formed for each of the conductor layers24. Accordingly, as in the first embodiment, the configuration in which the conductor layers24are divided into the portion corresponding to the select gate lines SGD0to SGD3and the portion corresponding to the select gate line SGDX by the slits SHE_X and SHE_Y can be applied. Accordingly, during the formation of the slit SHE_X, the occurrence of shape abnormality in the conductor layer23caused by over-etching can be prevented.

In the first modification example, the via CV_SGD does not adopt the structure in contact with the upper surface of each of the conductor layers24. Therefore, in the first modification example, it is not necessary that the step of performing etching using the mask pattern formed by slimming is repeatedly performed on the plural layers of sacrificial materials57. Therefore, end portions of the conductor layers24along the −X direction can have a shape having the same length without forming a staircase shape.

1.4.2 Second Modification Example

In addition, in the description of the first modification example, the select gate lines SGD and the contact CC_SGD are shunted from each other using the via CV_SGD, but the present disclosure is not limited thereto. In the following description, the same configuration and manufacturing method as those of the first modification example of the first embodiment will not described, and different points from those of the first modification example of the first embodiment will be mainly described.

FIG. 29is a plan view illustrating a planar layout of a memory cell array of a semiconductor storage device according to a second modification example of the first embodiment and corresponds toFIG. 27of the first modification example of the first embodiment.

As illustrated inFIG. 29, contacts CC″_SGD0to CC″_SGD3are in contact with the select gate lines SGD0to SGD3, respectively.

FIG. 30illustrates an example of a cross-sectional structure of the memory cell array10ofFIG. 29taken along line XXX-XXX and corresponds toFIG. 28of the first modification example of the first embodiment. As illustrated inFIG. 30, the contact CC″_SGD is provided on the upper surface of the conductor layer24as the lowermost layer and extends in the other conductor layers24(in the example ofFIG. 30, the conductor layer24as the second layer from the bottom and the conductor layer24as the uppermost layer) excluding the conductor layer24as the lowermost layer along the Z-axis. That is, the contact CC″_SGD is in contact with the upper surface of the conductor layer24as the lowermost layer and is in contact with side surfaces of the other conductor layers24. For example, the diameter of the contact CC″_SGD is substantially the same as that of the contact CC_WL.

As described above, certain effects similar to those of the first embodiment and the first modification example of the first embodiment can be exhibited with the configuration where the side surfaces of the select gate lines SGD and the contact CC_SGD are in direct contact with each other.

2. Second Embodiment

Next, a semiconductor storage device according to a second embodiment will be described. The second embodiment is different from the second modification example of the first embodiment, in that both of a hole for forming the contact CC_SGD connected to the select gate lines SGD and a hole for forming the slit SHE are formed. In the following description, the same configuration and manufacturing method as those of the second modification example of the first embodiment will not be described, and different points from those of the second modification example of the first embodiment will be mainly described.

2.1 Configuration of Semiconductor Storage Device

FIG. 31is a cross-sectional view illustrating a hookup region of a memory cell array of the semiconductor storage device according to the second embodiment and corresponds toFIG. 30of the second modification example of the first embodiment.

As illustrated inFIG. 31, a contact CC2_SGD extends in the conductor layers24along the Z-axis, and a lower end thereof is located to be lower than the lower surface of the conductor layer24as the lowermost layer. Lower ends and upper ends of a slit SHE2_Y (and a slit SHE2_X (not illustrated)) and the contact CC2_SGD are located substantially at the same heights along the Z direction, respectively. That is, the length L from the lower ends of the slits SHE2_X and SHE2_Y to the upper ends thereof substantially matches the length L from the lower end of the contact CC2_SGD to the upper end thereof.

2.2 Method of Manufacturing Semiconductor Storage Device

Hereinafter, an example of a series of manufacturing steps of the semiconductor storage device according to the second embodiment from the formation of a stacked structure corresponding to the word lines WL to a step of the formation of the contact CC_SGD corresponding to the select gate lines SGD will be described. Each ofFIGS. 32 to 43illustrates an example of a cross-sectional structure that includes a structure corresponding to the memory cell array in a manufacturing step of the semiconductor storage device according to the second embodiment.

First, in the same steps as those described above with reference toFIGS. 9 to 12in the first embodiment, the insulator layer50and the conductor layer21are sequentially stacked on the semiconductor substrate20. The insulator layer51and the sacrificial material52are stacked on the conductor layer21, and the insulator layer51and the sacrificial material53are alternately stacked on the sacrificial material52multiple times. After forming a staircase structure in the hookup region HA of the stacked structure, the lower pillar LP is formed in the cell region. Next, the insulator layer56is formed on the stacked structure. Further, the sacrificial materials57corresponding to the select gate lines SGD and the insulator layers58are alternately stacked. The insulator layer59is formed on the sacrificial material57as the uppermost layer.

Next, as illustrated inFIGS. 33 and 34, the SGD hole H3corresponding to the upper pillar UP is formed, and the stacked structure corresponding to the upper pillar UP is formed in the SGD hole H3.

Next, a hole (not illustrated) corresponding to the slit SLT is formed. Next, as illustrated inFIG. 35, the sacrificial materials52,53, and56are replaced with the conductor layers22to24via the hole, respectively. The above-described hole used in the replacement step is filled with an insulator layer (not illustrated), and the slit SLT is formed.

Next, as illustrated inFIG. 36, the conductor layer62is formed on an upper surface of the semiconductor portion44of the memory pillar MP. While forming the conductor layer25on an upper surface of the conductor layer62, the insulator layer63is formed to bury the conductor layer62and the conductor layer25over the surface.

Next, as illustrated inFIG. 37, a hole H11corresponding to the slits SHE2_X and SHE2_Y and a hole H12corresponding to the contact CC2_SGD are formed.FIG. 37illustrates a portion of the hole H11corresponding to the slit SHE2_Y. Specifically, first, a mask in which a region corresponding to the slits SHE2_X and SHE2_Y and the contact CC2_SGD is open is formed by lithography. Next, the holes H11and H12are formed by anisotropic etching (for example, RIE) using the formed mask.

The holes H11and H12formed in this step divide the insulator layers63,59, and58and the conductor layers24and reach the insulator layer56(e.g. extend into the insulator layer56). The depths of the holes H11and H12are substantially equal to each other and substantially match the length L inFIG. 31.

Next, as illustrated inFIG. 38, insulator layers72and73are formed to fill the inside of the holes H11and H12. Next, the insulator layers72and73that are higher than the insulator layer63are removed. The insulator layers72and73include, for example, silicon nitride.

Next, as illustrated inFIG. 39, the insulator layer72is selectively removed, and the hole H11is formed again. Specifically, for example, after forming a resist (not illustrated) on the insulator layer73to protect the insulator layer73, the insulator layer72is removed by wet etching or the like for selectively removing silicon nitride.

Next, as illustrated inFIG. 40, an insulator layer74is formed to fill the hole H11again. Next, the insulator layer74that is higher than the insulator layer63is removed. The insulator layer74includes, for example, silicon oxide.

Next, as illustrated inFIG. 41, a plurality of holes H13corresponding to the contacts CC_SGS and CC_WL0to CC_WL7, respectively, are formed. Specifically, first, a mask in which a region corresponding to the holes H13is open is formed by lithography. Next, the holes H13are formed by anisotropic etching using the formed mask.

Next, as illustrated inFIG. 42, the insulator layer73is selectively removed by wet etching or the like for selectively removing silicon nitride, and the hole H12is formed again.

Next, as illustrated inFIG. 43, conductor layers64A and65are formed to fill the inside of the holes H12and H13. Next, the conductor layers64A and65that remain to be higher than the insulator layer63are removed.

In the manufacturing steps of the semiconductor storage device according to the second embodiment described above, the slits SHE2_X and SHE2_Y and the contacts CC2_SGD0to CC2_SGD3of which the lower ends and the upper ends substantially match each other are formed. The manufacturing steps described above are merely exemplary. Another process may be inserted between the manufacturing steps, and the order of the manufacturing steps may be switched within a range where no problems arise.

2.3 Effect of Embodiment

According to the second embodiment, the contact CC2_SGD is in contact with the side surface of each of the conductor layers24. As a result, it is not necessary to form a contact for each of the conductor layers24. Accordingly, it is not necessary to form a terrace region for contacts for each of the conductor layers24. Therefore, for the conductor layers24, the staircase shape along the −X direction can be omitted, and the chip area can be reduced.

In addition, the hole H13corresponding to the contact CC_WL is formed in the different step from that of the hole H12corresponding to the contact CC2_SGD. As a result, a difference between the etching depths of holes formed in the same etching step can be reduced.

To supplement, when the holes H12and H13are formed in the same step, among the formed holes, the deepest hole is the hole H13that reaches the conductor layer22, and the shallowest hole is the hole H12that reaches the conductor layer24as the uppermost layer. On the other hand, when the holes H12and H13are formed in different steps, among the formed holes, the deepest hole is the hole H13that reaches the conductor layer22as the lowermost layer, whereas the shallowest hole is the hole H13that reaches the conductor layer23as the uppermost layer. Therefore, a difference between the etching depths of the deepest hole and the shallowest hole can be reduced, the risk of over-etching the conductor layer24corresponding to the shallowest hole can be reduced, and the generation of an unintended leakage current can be prevented.

The hole H12that is formed in a different step from that of the hole H13is formed in the same step as that of the hole H11corresponding to the slits SHE2_X and SHE2_Y. As a result, an increase in the number of manufacturing steps can be reduced. Accordingly, the upper ends and the lower ends of the contact CC2_SGD and the slits SHE2_X and SHE2_Y are located substantially at the same heights along the Z direction.

3. Other Modifications

The first embodiment and the second embodiment may be modified in various ways.

For example, in the description of the first embodiment and the second embodiment, the memory pillar MP is constituted by the upper pillar UP and the lower pillar LP, but the present disclosure is not limited thereto. For example, the memory pillar MP may have an integrally formed structure including: a semiconductor layer that extends in the conductor layers22to24along the Z-axis; and a charge storage layer that is arranged between the conductor layers22to24and the semiconductor layer.

In addition, in the description of the examples of the first embodiment and the second embodiment, the stacked film43includes the tunnel insulating film45, the insulating film46, and the block insulating film47such that the threshold voltage of the select transistor ST2can be adjusted, but the present disclosure is not limited thereto. For example, the stacked film43may not include the tunnel insulating film45and the insulating film46.

In addition, in the description of the examples of the first embodiment and the second embodiment, the semiconductor storage device1has the structure in which the circuit such as the sense amplifier module16is provided below the memory cell array10, but the present disclosure is not limited thereto. For example, the semiconductor storage device1may have a structure in which the memory cell array and the sense amplifier module16are formed on the semiconductor substrate20. In addition, the semiconductor storage device1may have a structure in which a chip where the sense amplifier module16and the like are provided and a chip where the memory cell array10is provided are bonded to each other.

In the description of the first embodiment and the second embodiment, the structure where the word lines WL and the select gate line SGS are adjacent to each other and the word lines WL and the select gate lines SGD are adjacent to each other is provided, but the present disclosure is not limited thereto. For example, a dummy word line may be provided between the word line WL as the uppermost layer and the select gate line SGD. Likewise, a dummy word line may be provided between the word line WL as the lowermost layer and the select gate line SGS. In addition, when a structure in which a plurality of pillars is linked is present, a conductor layer in the vicinity of the linked portion may be used as a dummy word line.

In the description of the examples of the first embodiment and the second embodiment, the semiconductor layer31and the conductor layer21are electrically connected to each other via a bottom portion of the memory pillar MP, but the present disclosure is not limited thereto. The semiconductor layer31and the conductor layer21may be electrically connected to each other via a side surface of the memory pillar MP. In this case, a part of the stacked film32formed on the side surface of the memory pillar MP is removed, and a structure in which the semiconductor layer31and the conductor layer21are in contact with each other via the portion is formed.