Method for fabricating dual work function metal gates

A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.

BACKGROUND OF THE INVENTION

This invention relates to the fabrication of dual work function metal gates for CMOS devices.

DETAILED DESCRIPTION OF THE INVENTION

Referring to the drawings,FIG. 1is a cross-sectional view of a semiconductor wafer10in accordance with the present invention. In the example application, CMOS transistors60,70are formed within a semiconductor substrate20having an NMOS region30and a PMOS region40. However, it is within the scope of the invention to fabricate a semiconductor wafer10that contains any one of a variety of semiconductor devices, such as a bipolar junction transistors, capacitors, or diodes.

The CMOS transistors60,70are electrically insulated from other active devices (not shown) by shallow trench isolation structures50formed within the semiconductor substrate30,40; however, any conventional isolation structure may be used such as field oxide regions or implanted isolation regions. The semiconductor substrate20is any semiconducting material that is doped with n-type and p-type dopants.

Transistors, such as CMOS transistors60,70, are generally comprised of a gate, source, and drain. More specifically, as shown inFIG. 1, the active portion of the transistors are comprised of sources/drains80, source/drain extensions90, and a gate that is comprised of a gate dielectric100and gate electrode110.

The example PMOS transistor60is a p-channel MOS transistor. Therefore it is formed within a n-well region40of the semiconductor substrate20. In addition, the deep sources and drains80and the source and drain extensions90have p-type dopants such as boron. The sources/drains80are usually heavily doped. However, the source/drain extensions90may be lightly doped (“LDD”), medium doped (“MDD”), or highly doped (“HDD”). The PMOS gate is created from a p-type doped polysilicon electrode110and gate oxide dielectric100.

Similarly, the example NMOS transistor70is a n-channel MOS transistor. Therefore it is formed within a p-well region30of the semiconductor substrate20. In addition, the deep sources and drains80and the source and drain extensions90have n-type dopants such as arsenic, phosphorous, antimony, or a combination of n-type dopants. The sources/drains80of NMOS transistor70are also heavily doped. However, the source/drain extensions90may be either LDD, MDD, or HDD. The NMOS gate70is created from an n-type doped polysilicon electrode110and gate oxide dielectric100.

An offset structure comprising extension sidewalls140and spacer sidewalls150are used during fabrication to enable the proper placement of the source/drain extensions90and the sources/drains80, respectively. More specifically, the source/drain extensions90are usually formed using the gate stack and extension sidewalls140as a mask. In addition, the sources/drains80are usually formed with the gate stack and spacer sidewalls150as a mask.

The top portion of the extension sidewalls140and the spacer sidewalls150are at the same level as—or extend past—the top surface of the gate electrode110in accordance with the invention. As described more fully below, this structure helps protect the polysilicon gate electrode from unwanted silicidation during the fabrication process step of source/drain silicidation.

In this example application, the sources/drains80have a layer of silicide120that is formed within the top surface of the sources/drains80during the fabrication process (as described below). The silicide layer120formed within the top surface of the sources/drains80is preferably CoSi2; however, it is within the scope of the invention to fabricate the silicide120with other metals (such as nickel, platinum, titanium, tantalum, molybdenum, tungsten, or alloys of these metals). In addition, the silicide layer120formed on the top surface of the sources/drains80may be a self-aligned silicide (i.e. a “salicide”)

Moreover, the gate electrode110is also silicided during the semiconductor fabrication process (as also described below). Preferably, the gate is fully silicided (“FUSI”); however, it is within the scope of the invention to form the silicide within only a portion of the gate electrode. FUSI gate electrodes have the advantage of low resistance and no poly depletion in comparison to polycrystalline silicon (i.e. “polysilicon” or “poly”) gate electrodes. The purpose of the silicide formed within the gate electrode110and the top portion of the sources/drains80is the reduction of the contact resistance between the transistors60,70and the electrical contacts170,180. The gate electrode silicide is preferably comprised of NiSi; however, other metals may be used, such as cobalt, platinum, titanium, tantalum, molybdenum, tungsten, or an alloy.

Referring again toFIG. 1, a layer of dielectric insulation160surrounds the transistors60,70. The composition of dielectric insulation160may be any suitable material such as SiO2or organosilicate glass (“OSG”). The dielectric material160electrically insulates the metal contacts170that electrically connect the CMOS transistors60,70that are shown inFIG. 1to other active or passive devices (not shown) that are located throughout the semiconductor wafer20. An optional dielectric liner (not shown) may be formed before the placement of the dielectric insulation layer160. If used, the dielectric liner may be any suitable material such as silicon nitride.

In this example application, the contacts170are comprised of W; however, any suitable material (such as Cu, Ti, Al, or an alloy) may be used. In addition, an optional liner material180such as Ti, TiN, or Ta (or any combination or layer stack thereof) may be used to reduce the contact resistance at the interface between the liner180and the silicided regions of the gate electrode110and sources/drains80.

Subsequent fabrication will create the “back-end” portion of the integrated circuit (not shown). The back-end generally contains one or more interconnect layers (and possibly via layers) that properly route electrical signals and power though out the completed integrated circuit.

Referring again to the drawings,FIGS. 2A-2Nare cross-sectional views of a partially fabricated semiconductor wafer10illustrating a process for forming an example PMOS transistor60in accordance with the present invention. Those skilled in the art of semiconductor fabrication will easily understand how to modify this process to manufacture other types of transistors (such as a NMOS transistor70) in accordance with this invention.

FIG. 2Ais a cross-sectional view of a transistor structure60after the formation of the gate oxide layer105and the gate polysilicon layer115on the top surface of a semiconductor substrate20. In the example application, the semiconductor substrate20is silicon; however any suitable material such as germanium or gallium arsenide may be used. The example PMOS transistor60is formed within a n-well region40of the semiconductor substrate20.

The gate oxide layer105and the gate polysilicon layer115are formed using well-known manufacturing techniques. A first layer formed over the surface of the semiconductor substrate20is a gate oxide layer105. As an example, the gate oxide layer105is silicon dioxide formed with a thermal oxidation process. However, the gate oxide layer105may be any suitable material, such as nitrided silicon oxide, silicon nitride, or a high-k gate dielectric material, and may be formed using any one of a variety of processes such as an oxidation process, thermal nitridation, plasma nitridation, physical vapor deposition (“PVD”), or chemical vapor deposition (“CVD”).

A gate polysilicon layer115is then formed on the surface of the gate oxide layer105. The gate polysilicon layer115is comprised of polycrystalline silicon in the example application. However, it is within the scope of the invention to use other materials such as an amorphous silicon, a silicon alloy (e.g. SiGe), or other suitable materials. The gate polysilicon layer115may be formed using any process technique such as CVD or PVD.

In accordance with the best mode of the invention, an ion implantation is performed after the formation of the gate polysilicon layer115. In the example application shown inFIG. 2B, the semiconductor wafer10is initially subjected to a blanket ion implantation of a p-type dopant, preferably boron. This implantation process will move the work function of the gate electrode of the PMOS transistors higher. Therefore, by using ion implantation at this point in the fabrication process the work function of the PMOS transistor may be customized to the desired level-independent of the dopant level used later in the fabrication process to form the source/drain extension junctions.

Any suitable machine may be used to perform the ion implant such as the xRLeapII or the xRLeapQ (made by Applied Materials), the GSD Ultra or the GSD HC E2(made by Axcelis Technologies), or the VIISTA80 (made by Varian Semiconductor Equipment). The implant angle is 0-10°; however, 0° is preferred. The implant energy and dose depends on the dopant species, the thickness of the gate electrode layer, and the threshold voltage required for the devices. It is to be noted that this ion implant may be followed by a standard post ion implantation clean.

In another embodiment, shown inFIG. 2C, patterned photoresist200is used to cover the NMOS regions during the ion implantation of the p-type dopants. Once the implantation process is complete the photoresist200is removed (with a standard ashing and cleaning process). If this alternative process flow is used then the resulting PMOS regions40will be similar to the structure shown inFIG. 2B.

Next, the semiconductor wafer10is subjected to an n-type ion implantation process (for NMOS regions). As shown inFIG. 2D, a layer of photoresist200is formed and patterned to expose the NMOS regions30. The n-type dopant is preferably phosphorous. However, other n-type dopants or combinations of n-type dopants may be used; such as arsenic, antimony, or a combination of n-type dopants. This implantation process will move the work function of the gate electrodes of the NMOS transistors lower. Like the p-type ion implant process described above, this n-type implantation process is preferably used to customize the work function of the gate electrodes of the NMOS transistors-independent of the source/drain extension implant parameters.

Referring again to the fabrication of the example PMOS transistor60, the next step in the example application is the formation of a protection layer215over the entire semiconductor wafer, as shown inFIG. 2E. Preferably, the protection layer is formed using a CVD process; however, any suitable process may be used. In the best mode application, the protection layer is comprised of a silicon oxide layer (having a thickness between 0.5-10 nm) and a silicon nitride layer (having a thickness between 20-70 nm). The purpose of the silicon oxide layer is to serve as a buffer for better process control, as described more fully in the commonly assigned patent application having patent application Ser. No. 11/007,569 and incorporated herein by reference but not admitted to be prior art with respect to the present invention by its mention in this section. It is to be noted that the silicon nitride layer is the main component of the protection layer215.

Alternatively, the protection layer215may be comprised of SixNy, SiC, other metal nitrides, or combinations and stacks thereof. More specifically, the protection layer215may be Si3N4, or a stack consisting of SiO2/ Si3N4/ SiO2. In the example application the protection layer215is at least 20 nm thick in order to control the height of the sidewalls140,150and thereby protect the doped gate polysilicon layer113during the silicidation process (described below). Preferably, the protection layer215is between 30-50 nm thick. In the example application the protection silicon nitride layer215is deposited by a rapid thermal CVD process using silane or dichlorosilane and ammonia precursors.

After a pattern and etch process, a gate stack having a gate dielectric100, a gate electrode112, and gate protection layer210will be formed from the gate oxide layer105, the doped gate polysilicon layer113, and the protection layer215respectively. This gate stack, shown inFIG. 2F, may be created through a variety of processes. For example, the gate stack may be created by forming a layer of photoresist over the semiconductor wafer, patterning the photoresist, and then using the photoresist pattern to etch the gate oxide layer105, the doped gate polysilicon layer113, and the protection layer215. This gate stack may be etched using a suitable etch process, such as an anisotropic etch using plasma or reactive ions.

The fabrication of the PMOS transistor60now continues with standard process steps. Generally, the next step in the fabrication of the PMOS transistor60is the formation of the extension regions95using the extension sidewalls140as a template.

As shown inFIG. 2G, extension sidewalls140are formed on the outer surface of the gate stack using any suitable processes and materials. The extension sidewalls140may be formed from a single material or may be formed from more than one layer of materials. For example, the extension sidewalls140may be comprised of an oxide, oxi-nitride, silicon dioxide, nitride, or any other dielectric material or layers of dielectric materials. The material layers for the extension sidewalls140may be formed with any suitable process, such as thermal oxidation, or deposition by ALD, CVD, or PVD. Preferably, at least one layer of the extension sidewall140is comprised of a silicon nitride that is formed with a CVD process that uses a bis-t-butylaminosilane (“BTBAS”) precursor. Forming the silicon nitride layer with that precursor will help guard against the etching of the extension sidewalls140during the process of removing the gate protection layer later in the fabrication process (due to the low etch rate of BTBAS in the etching solution that is used for the protection layer removal). It is to be noted that the anisotropic etch process that is used to shape the material layer or layers into the extension sidewalls140will cause the highest point of the extension sidewalls140to be recessed from the top surface of the gate protection layer210, as shown inFIG. 2G.

These extension sidewalls140are now used as a template to facilitate the proper doping of the extension regions95. However, it is within the scope of the invention to form the extension regions95at any point in the manufacturing process.

The extension regions95are formed near the top surface of the semiconductor substrate40using any standard process. For example, the extension regions95may be formed by low-energy ion implantation, a gas phase diffusion, or a solid phase diffusion. The dopants used to create the extension regions95for a PMOS transistor120are p-type (i.e. boron). The dopants used to create the extension regions95for a NMOS transistor70are n-type (i.e. phosphorous or arsenic). However, other dopants or combinations of dopants may be used.

In the example application shown inFIG. 2G, the extension sidewalls140are used to direct the dopant implantation to the proper location95within the semiconductor substrate40. Due to lateral straggling of the implanted species, the extension regions95initiate from points in the semiconductor substrate40that are slightly inside the outer corner of the extension sidewalls140.

At some point after the implantation of the extension regions95, the extension regions95are activated by an anneal process (performed now or later) to form source/drain extensions90(as shown inFIG. 2H). This anneal step may be performed with any suitable process such as rapid thermal anneal (“RTA”). The annealing process will likely cause a lateral migration of each extension region toward the opposing extension region.

Referring toFIG. 2H, spacer sidewalls150are now formed proximate to the extension sidewalls140. The spacer sidewalls150may be formed using any standard process and materials. In addition the spacer sidewalls150may be formed from a single material or from two or more layers of materials. For example, the spacer sidewalls150may be comprised of a cap oxide and a silicon nitride layer that are formed with a CVD process and subsequently anisotropically etched (preferably using standard anisotropic plasma etch processes). However, it is within the scope of the invention to use more layers (i.e. a spacer oxide layer, a silicon layer, and a final oxide layer) or less layers (i.e. just a silicon oxide layer or a silicon nitride layer) to create the spacer sidewalls150. It is to be noted that the semiconductor wafer10is usually subjected to a standard post-etch cleaning process after the formation of the spacer sidewalls150. It is also to be noted that the height of the extension sidewalls140and the spacer sidewalls150at this point (FIG. 2H) is lower than the previous height of the extension sidewalls (FIG. 2G) due to the additional anisotropic etching process.

Now the source/drain sidewalls150are used as a template for the implantation of dopants into the source/drain regions85. However, it is within the scope of the invention to form the source/drain regions85at another point in the manufacturing process.

The source/drain regions85may be formed through any one of a variety of processes, such as deep ion implantation or deep diffusion. The dopants used to create the source/drain regions85for a PMOS transistor are typically boron; however, other dopants or combinations for dopants may be used. The dopants used to create the source/drain regions85for a NMOS transistor are typically phosphorous or arsenic; however, other dopants or combinations for dopants may be used.

The implantation of the dopants is self-aligned with respect to the outer edges of the source/drain sidewalls150. However, it is to be noted that due to lateral straggling of the implanted species, the source/drain regions85initiate slightly inside the outer corner of the spacer sidewalls150.

In the example application, the source/drain regions85are activated by a second anneal step to create sources/drains80. (However, the extension region anneal and the source/drain region anneal may be combined and performed at this point in the fabrication process.) This anneal step acts to repair the damage to the semiconductor wafer and to activate the dopants. The activation anneal may be performed by any technique such as RTA, flash lamp annealing (“FLA”), or laser annealing. This anneal step often causes lateral and vertical migration of dopants in the source/drain extensions90and the sources/drains80. In addition, this anneal step will cause the recrystallization of the ion implant areas80,90(or the full crystallization of the ion implant areas80,90if this is the first anneal).

As shown inFIG. 21, a layer of silicidation metal220is now formed over the top surface of the semiconductor wafer10. The silicidation metal layer220is preferably comprised of cobalt; however, other suitable materials such as nickel, platinum, titanium, tantalum, molybdenum, tungsten, or alloys may be used. In the example application, the silicidation metal layer220is between 4-10 nm thick and is formed using a PVD process.

An optional capping layer230may also be formed over the silicidation metal layer220. If used, the capping layer230acts as a passivation layer that prevents the diffusion of oxygen from ambient into the silicidation metal layer220. The capping layer may be any suitable material, such as TiN. In the example application, the capping layer230is between 5-30 nm thick.

In accordance with the invention, the semiconductor wafer is now annealed with any suitable process, such as RTA. In the example application, the silicide anneal is performed for 10-60 seconds at a temperature between 400-600° C.

This anneal process will cause a silicide120(i.e. a Co-rich silicide or Co mono-silicide) to form at the surface of the sources/drains80as shown inFIG. 2J. It is to be noted that the silicidation metal layer220will only react with the active substrate (i.e. exposed Si); namely, the sources/drains80and the exposed surfaces of Si (such as the areas for diodes). Therefore, the silicide120formed by the annealing process is a salicide. It is important to note that the gate electrode112was not modified by the anneal process because the gate electrode112was protected by the gate protection layer210and the extension sidewalls140(which overlap the gate protection layer210).

The next step is the removal of the un-reacted portions of the silicidaton metal layer220, as shown inFIG. 2K. The silicidaton metal layer220(and the capping layer230, if used) is removed with any suitable process such as a wet etch process (e.g. using a fluid mixture of sulfuric acid, hydrogen peroxide, and water).

It is within the scope of the invention to perform another silicide anneal (such as a RTA) at this point in the manufacturing process in order to further react the silicide120with the sources/drains80. In the example application, a second silicide anneal is performed for 10-60 seconds at a temperature between 650-800° C. If the initial anneal process did not complete the silicidation process, this second anneal will ensure the formation of a mono-silicide CoSi, which lowers the sheet resistance of the silicide120.

The gate protection layer210is now removed, as shown inFIG. 2L. The gate protection layer210may be removed by any suitable process such as a wet etch using a solution containing phosphoric acid at elevated temperatures in the range of 100-600° C. Alternatively, the protection layer can be removed by using a dilute HF solution at elevated temperatures. Because the extension sidewalls140and the spacer sidewalls150were formed with the gate protection layer210in place over the gate electrode112, the extension sidewall and the spacer sidewall structures140,150will now stretch beyond the top surface of the gate electrode112. With the gate protection layer210removed, the gate electrode112is now exposed and therefore available for gate electrode silicidation.

As shown inFIG. 2M, a second layer of silicidation metal220is now formed over the top surface of the semiconductor wafer10. The silicidation metal layer220is preferably comprised of nickel; however, other suitable materials such as cobalt, platinum, titanium, tantalum, molybdenum, tungsten, or an alloy may be used. Preferably, the silicidation metal220is designed to fully silicidize the polysilicon electrode250. As it takes approximately 1 nm of nickel to fully silicidize approximately 1.8 nm of polysilicon, the thickness of the silicidation metal220should be at least 56% of the thickness of the polysilicon gate electrode112. To be comfortable however, it is suggested that the thickness of the silicidation metal220should be at least 60% of the thickness of the polysilicon gate electrode112. Thus, where the thickness of the polysilicon gate electrode112ranges from about 50 nm to about 150 nm, in the example application, the thickness of the silicidation metal220should range from approximately 30 nm to about 90 nm.

In an alternative embodiment of the invention, a thinner layer of silicidation metal220may be formed over the exposed portions of the polysilicon gate electrode112as well as over the remainder of the semiconductor device. In this instance, the thinner layer of silicidation metal220will only react with the top portion of the polysilicon gate electrode112to form a partially silicided gate electrode, as shown inFIG. 20. The thickness of the thinner layer of silicidation metal220could range from about 3 nm to about 15 nm to only partially silicide the silicided gate electrode. This embodiment is particularly useful for applications where a poly-gate oxide interface is used, rather than a silicide-gate oxide interface, as is the case in the fully silicided gate electrode discussed directly above.

An optional capping layer230may also be formed over the silicidation metal layer220. If used, the capping layer230acts as a passivation layer that prevents the diffusion of oxygen from ambient into the silicidation metal layer220. The capping layer may be any suitable material, such as TiN or Ti. In the example application, the capping layer230is between 5-30 nm thick.

In accordance with the invention, the semiconductor wafer is now annealed with any suitable process, such as RTA. In the example application, the silicide anneal is performed for 10-60 seconds at a temperature between 300-500° C. In the example application, the gate electrode110is fully silicided (“FUSI”), as shown inFIG. 2M. Alternatively, as shown inFIG. 20, an anneal process may form only a gate silicide film240(i.e. a nickel-rich silicide or nickel mono-silicide) at the top potion of the gate electrode112. It is to be noted that the silicidation metal layer220will not react with the silicided sources/drains80and the silicided surfaces of the n-well40because they are protected from further silicidation by their previously formed silicide layer120.

The next step is the removal of the un-reacted portions of the silicidaton metal layer220, as shown inFIG. 2N. The silicidaton metal layer220(and the capping layer230, if used) is removed with any suitable process such as a selective wet etch process (i.e. using a fluid mixture of sulfuric acid, hydrogen peroxide, and water).

It is within the scope of the invention to perform another silicide anneal (such as a RTA) at this point in the manufacturing process in order to further react the gate silicide. In the example application, the second silicide anneal is performed for 30-120 seconds at a temperature between 400-600° C. If the initial anneal process did not complete the silicidation process, this second anneal will ensure the formation of a NiSi having a lowered sheet resistance. As stated above, the gate electrode110is fully silicided (“FUSI”) through the silicidation process in the example application.

It is to be noted that the work function of gate electrode110is modulated by the dopants that were implanted before the formation of the protection layer210. The protection layer210also prevented the loss of dopants during the source/drain anneal process; thereby further controlling the tuning of the gate electrode work function during the fabrication of the semiconductor wafer10.

One of the variations to the present invention is to form the extension sidewalls140and spacer sidewalls150with the protection layer215in place but then remove a portion of the protection layer215so that the gate polysilicon layer115receives dopants during the implantation of the source/drain regions85(for work function tuning of the gate electrode110). With this alternative fabrication process, standard manufacturing steps (as described above) would be used to build the gate oxide layer105and gate polysilicon layer115of the example PMOS transistor60, as shown inFIG. 3A.

The protection layer215of this alternative process flow is comprised of multiple layers in order to remove a portion of the protection layer215after the formation of the spacer sidewalls150. In this example application the protection layer is comprised of a bottom layer of silicon nitride215A (preferably 2-15 nm thick), a middle layer of silicon oxide215B (preferably 2-10 nm thick), and a top layer of silicon nitride215C (preferably 20-70 nm thick).

Next, the gate stack is formed using any suitable etch processes (as described above). The gate stack contains a gate dielectric100, a gate electrode114, and a three part gate protection layer210, as shown inFIG. 3B. After the gate stack is formed, standard processes and materials are used to form the extension sidewalls140, implant and anneal the source/drain extensions90, and then form the spacer sidewalls150.

As shown inFIG. 3C, the top layer of silicon nitride210C is then removed by hot phosphoric acid solution, which uses the middle layer210B as an etch stop layer. The middle layer of silicon oxide210B is now removed with a standard wet etch process such as dilute HF solution. Next, the semiconductor wafer10is subjected to the source/drain ion implantation process. Because of the reduced thickness of the protection layer210, the dopants implanted into the source/drain regions85will also be implanted into the gate electrode111; thereby tuning the work function of the final FUSI gate electrode110.

The semiconductor wafer10is now annealed, forming sources/drains80, as shown inFIG. 3D. Using the processes describe above, a first layer of silicidation metal220and a capping layer230is formed over the semiconductor wafer10and then the wafer is annealed (using an RTA process) in order to form the source/drain silicide films120(as also shown inFIG. 3D). Because the extension sidewalls140extend past the gate protection layer210A, the gate electrode111is fully protected against accidental silicidation during this silicidation process.

As shown inFIG. 3E, the un-reacted first layer of silicidation metal220and the capping layer230are now removed with a wet etch process and the semiconductor wafer10may now be subjected to a second RTA silicide anneal, as described above. Once the source/drain silicides120are formed, the gate protection layer210A is removed with a wet etch process using phosphoric acid, as shown inFIG. 3F.

The fabrication process then continues with the formation of the FUSI gate electrode110, as described above in reference toFIGS. 2M-2N. The transistor60fabricated with this alternative process flow will have a work function that is modulated by the source/drain80implantation process.

After the formation of source/drain silicides120and the gate FUSI110using any process flow described above, the fabrication of the semiconductor wafer10now continues, using standard process steps, until the semiconductor device is complete. Generally, the next step is the formation of the dielectric insulator layer160using plasma-enhanced chemical vapor deposition (“PECVD”) or another suitable process (seeFIG. 1). The dielectric insulator160may be comprised of any suitable material such as SiO2or OSG.

The contacts170are formed by etching the dielectric insulator layer160to expose the desired gate, source and/or drain. The etched spaces are usually filled with a liner180to improve the electrical interface between the silicide and the contact170. Then contacts170are formed within the liner180; creating the electrical interconnections between various semiconductor components located within the semiconductor substrate20.

As discussed above, the fabrication of the final integrated circuit continues with the fabrication of the back-end structure. Once the fabrication process is complete, the integrated circuit will be tested and then packaged.

Various additional modifications to the invention as described above are within the scope of the claimed invention. As an example, interfacial layers may be formed between any of the layers shown. In addition, an anneal process may be performed after any step in the above-described fabrication process. When used, the anneal process can improve the microstructure of materials and thereby improve the quality of the semiconductor structure.

This invention may be implemented in a sidewall spacer structure that is comprised of different materials or layers than is described above. Moreover, this invention may be implemented in other semiconductor structures such as capacitors or diodes, and also in different transistor structures such as biCMOS and bipolar transistors.