Switching converter with output current estimator circuit

A system includes a switching converter circuit and a monitoring circuit coupled to the switching converter circuit. The monitoring circuit includes a current estimation circuit configured to estimate an output current of the switching converter circuit. The monitoring circuit also includes a compare circuit configured to compare the estimated average output current with a threshold, wherein the compare circuit is configured to output an alert signal in response to the estimated output current being greater than the threshold.

BACKGROUND

Power supplies and power converters are used in a variety of electronic systems. Electrical power is generally transmitted over long distances as an alternating current (AC) signal. The AC signal is divided and metered as desired for each business or home location, and is often converted to direct current (DC) for use with individual electronic devices or components. Modern electronic systems often employ devices or components designed to operate using different DC voltages. Accordingly, different DC-DC converters, or a DC-DC converter that supports a wide range of output voltages, are needed for such systems.

There are many different DC-DC converter topologies. The available topologies differ with regard to the components used, the amount of power handled, the input voltage(s), the output voltage(s), efficiency, reliability, size and/or other characteristics. One example DC-DC converter topology is a single-input multiple-output (SIMO) converter, which provides multiple outputs by charging and selectively discharging a single inductor to different nodes. In some SIMO converter scenarios, low efficiency and output oscillations may occur due to the components used as well as control issues.

SUMMARY

In accordance with at least one example of the disclosure, a system comprises a switching converter circuit and a monitoring circuit coupled to the switching converter circuit. The monitoring circuit includes a current estimation circuit configured to estimate an output current of the switching converter circuit. The monitoring circuit also includes a compare circuit configured to compare the estimated average output current with a threshold, wherein the compare circuit is configured to output an alert signal in response to the estimated output current being greater than the threshold.

In accordance with at least one example of the disclosure, a converter circuit comprises a first switch coupled between a first inductor node and a voltage supply node. The converter circuit also comprises a second switch coupled between the first inductor node and a negative supply output node. The converter circuit also comprises a third switch coupled between a second inductor node and a positive output supply node. The converter also comprises a fourth switch coupled between the second inductor node and a ground node. The converter circuit also comprises a controller coupled to the first, second, third, and fourth switches. The converter circuit also comprises a monitoring circuit coupled to at least one of the negative supply output node and the positive supply output node, wherein the monitoring circuit comprises a current estimation circuit and a compare circuit coupled to the current estimation circuit.

In accordance with at least one example of the disclosure, a converter device comprises a first switch coupled between a first inductor node and a voltage supply node. The converter device also comprises a second switch coupled between the first inductor node and a negative supply output node. The converter device also comprises a third switch coupled between a second inductor node and a positive output supply node. The converter device also comprises a fourth switch coupled between the second inductor node and a ground node. The converter device also comprises a monitoring circuit coupled to at least one of the negative supply output node and the positive supply output node. The monitoring circuit is configured to estimate an output current and to provide an alert signal in response to the estimated output current being greater than a threshold.

DETAILED DESCRIPTION

Disclosed herein are switching converter topologies involving a current monitor circuit configured to estimate an output current for the switching converter. The estimated output current is used, for example, to detect an overcurrent condition (e.g., the current is above a threshold for more than a predetermined interval). In some examples, the current monitor circuit includes a switch “on” (conduction) detection stage, a current estimation stage, and a compare stage. The conduction detection stage detects a high-side switch “on” condition or a low-side switch “on” condition. The current estimation stage provides a scaled estimate of the current associated with the detected switch “on” condition. In some examples, an integration stage is used to integrate the estimated current for a time interval. The compare stage compares a current estimate from the current estimation stage or the integration stage with a reference value. If the current estimate is greater than the reference value, the compare stage outputs an overcurrent signal or alert. If the current estimate is not greater than the reference value, the compare stage does not output an overcurrent signal or alert. Alternatively, the compare stage may output an undercurrent signal in response to the current estimate being equal to or less than the reference value. In some examples, the compare stage avoids outputting a signal in response to the current estimate being equal to or less than the reference value (i.e., the compare stage only outputs a signal in response to an overcurrent condition).

In some examples, the switching converter has a single-input multiple-output (SIMO) converter topology. An example SIMO converter includes an inductor, a first switch between a first end of the inductor and a power supply node, a second switch between the first end of the inductor and a negative output supply node, a third switch coupled between a second end of the inductor and a positive output supply node, and a fourth switch coupled between the second end of the inductor and a ground node. The SIMO converter also includes a controller coupled to the first, second, third, and fourth switches, where controller directs operations of the first, second, third, and fourth switches to transition from a rest state, to at least one boost iteration, and back to a rest state. In some examples, each boost iteration involves performing an inductor charge mode followed by a positive or negative boost mode. As needed, multiple boost iterations are performed before transitioning back to the rest state. In some examples, the current monitor circuit is used to detect and respond to overcurrent conditions in a SIMO converter, where the detection occurs during a switch “on” or forward bias diode condition related to one or more boost iterations. In other examples, the current monitor circuit is used to detect and respond to overcurrent conditions in another switching converter that occur during a switch “on” or forward biased diode condition. To provide a better understanding, various switching converter options and current monitor circuit options are described using the figures as follows.

FIG. 1is a block diagram showing a switching converter system100in accordance with various examples. InFIG. 1, the system100represents a consumer product, an integrated circuit or chip, a printed circuit board (PCB) with integrated circuit and/or discrete components, and/or another electrical device. As shown, the system100comprises a SIMO converter circuit102coupled to a controller104. The system100also comprises a sense circuit108coupled to the SIMO converter circuit102and to the controller104. The system100also comprises a first load126coupled to a positive output supply node116of the SIMO converter circuit102. The system100also comprises a second load128coupled to a negative output supply node114of the SIMO converter circuit102.

In the example ofFIG. 1, the SIMO converter circuit102comprises a first switch (S1) coupled between a power supply (VIN) node112and a first inductor node (labeled “LY”)122. The SIMO converter circuit102also comprises a second switch (S2) coupled between the first inductor node122and the negative output supply node114. The SIMO converter circuit102also comprises a third switch (S3) coupled between a second inductor node (labeled “LX”)124and the positive output supply node116. The SIMO converter circuit102also comprises a fourth switch (S4) coupled between the second inductor node124and a ground node118.

InFIG. 1, an inductor120is coupled between the first and second inductor nodes122and124. In some examples, the inductor120is a discrete component that is added to the SIMO converter circuit102by coupling respective terminals of the inductor120to the first and second inductor nodes122and124. In contrast, the other components of the SIMO converter circuit102may be part of an integrated circuit. In some examples, the integrated circuit also includes the controller102and the sense circuit108. In other examples, the controller102and/or the sense circuit108are part of an integrated circuit that is separate from the SIMO converter circuit102. Also, in some examples, the first and second loads126and128are separate components or circuits relative to the SIMO converter circuit102, the controller104, and the sense circuit108.

In the example ofFIG. 1, the controller104supports various modes for the SIMO converter circuit102as well as at least one rest state. More specifically, the controller104is configured to provide an inductor charge mode, a positive boost mode, a negative boost mode, and at least one rest state. For the inductor charge mode, the controller104is configured to close S1and S4and to open S2and S3. For the positive boost mode, the controller104is configured to close S1and S3and to open S2and S4. For the negative boost mode, the controller104is configured to close S2and S4and to open S1and S3. In one example rest state, the controller104is configured to close S1and to open S2, S3, and S4. In another example rest state, the controller104is configured to close S4and to open S1, S2, and S3.

In some examples, the controller104comprises an asynchronous state machine configured to adjust control signals (CS1-CS4) for S1-S4of the SIMO converter circuit102to achieve the various modes or rest states described herein without a clock signal. More specifically, in the example ofFIG. 1, the controller104receives various input signals from the sense circuit108and adjusts the operations of S1-S4to achieve the various modes or rest states described herein

In some examples, the controller104performs a state machine cycle that includes starting at one of the first or second rest states. The state machine cycle also includes performing at least one boost iteration that includes the inductor charge mode and the positive or negative boost mode. The state machine cycle also includes returning to one of the first or second rest states. In some examples, the controller104includes arbitration logic (see e.g., the arbitration logic240inFIG. 2) configured to determine whether the positive boost mode or the negative boost mode is used in a given boost iteration. In some examples, the arbitration logic uses sense signals from the sense circuit108to determine whether the positive boost mode or the negative boost mode is used in a given boost iteration.

Once a boost iteration is triggered, the controller104performs an inductor charge mode by closing S1and S4while S2and S3are open. In some examples, the inductor charge mode continues until the inductor charge is above a programmable threshold. After the inductor charge mode is complete, the controller104transitions to the positive boost mode or the negative boost mode depending on arbitration results (e.g., which output supply voltage is farthest from a respective target and/or other criteria). After a positive or negative boost mode is complete, the controller104transitions to another boost iteration or to one of the rest states depending on the input signals to the controller104.

In the example ofFIG. 1, the system100includes a current monitor circuit130coupled to the LY node122and/or the LX node124. As shown, the current monitor circuit130includes an “on” detect circuit131, a current estimation circuit132, and a compare circuit134. In operation, the “on” detect circuit131detects a switch “on” condition. In some examples, when the SIMO converter circuit102transitions from an inductor charge mode to a negative boost mode, “the on” detect circuit131detects that S2is closed. On the other hand, when the SIMO converter circuit102transitions from an inductor charge mode to a positive boost mode, the “on” detect circuit131detects that S3is closed.

The current estimation circuit132determines an estimate of the current to the positive output supply node116during a positive boost mode and/or the current to the negative output supply node114during a negative boost mode. In some examples, the estimated current corresponds to a voltage value. As shown, the current monitor circuit132also comprises a compare circuit134. The compare circuit134compares a current estimate133output from the current estimation circuit132with a programmable threshold138. If the current estimate133is greater than the programmable threshold138, the compare circuit134outputs an overcurrent signal or alert signal136. In other examples, the compare stage134outputs an undercurrent signal in response to the current estimate133being equal to or less than the programmable threshold138. In some examples, the compare stage134avoids outputting a signal in response to the current estimate being equal to or less than the reference value (i.e., the compare stage only outputs a signal in response to an overcurrent condition).

FIG. 2is a set of schematic diagrams showing a boost iteration scenario200in accordance with various examples. In scenario200, a boost iteration is initiated by transitioning from a rest state (not shown) to an inductor charge mode arrangement210for the SIMO converter circuit102. As shown inFIG. 2, the inductor charge mode arrangement210corresponds to S1and S2being closed while S2and S3are open. After the inductor charge mode is complete, arbitration logic240determines whether a positive boost or a negative boost will be performed.

In scenario200, a positive boost is performed by transitioning from the inductor charge mode arrangement210for the SIMO converter circuit102to the positive boost arrangement220for the SIMO converter circuit102. As shown, the positive boost mode arrangement220corresponds to S1and S3being closed while S2and S4are open. After the positive boost mode is complete, arbitration logic240determines whether another boost iteration is needed. If so, the scenario200returns to the inductor charge mode arrangement210for the SIMO converter circuit102, and subsequently another positive or negative boost. Otherwise, if another boost iteration is not needed, the boost iteration scenario200is complete and the SIMO converter circuit102is placed in a rest state as described herein. In some examples, the use of the different rest states depends on enable signals (e.g., VPOS_enabled and/or S1_IDLE) as described herein.

In scenario200, a negative boost is performed by transitioning from the inductor charge mode arrangement210for the SIMO converter circuit102to the negative boost arrangement230for the SIMO converter circuit102. As shown, the negative boost mode arrangement230corresponds to S2and S4being closed while S1and S3are open. After the negative boost mode is complete, arbitration logic240determines whether another boost iteration is needed. If so, the scenario200returns to the inductor charge mode arrangement210for the SIMO converter circuit102, and subsequently another positive or negative boost is performed. Otherwise, if another boost iteration is not needed, the boost iteration scenario200is complete and the SIMO converter circuit102is placed in a rest state.

In some scenarios, a current monitor circuit (e.g., the current monitor circuit130ofFIG. 1) performs its operations during a positive boost mode (when the SIMO converter circuit102in is the positive boost arrangement220). In other scenarios, a current monitor circuit (e.g., the current monitor circuit130ofFIG. 1) performs its operations during a negative boost mode (when the SIMO converter circuit102in is the negative boost arrangement220).

FIGS. 3-5are block diagrams showing current monitoring circuits in accordance with various examples. InFIG. 3, a current monitoring circuit300for low-side monitoring (e.g., negative boost mode monitoring) is represented. As shown, the current monitoring circuit300includes a power stage302, a low-side “on” detection stage312, an integration stage322, and a compare stage332. The power stage302ofFIG. 3includes SIMO converter circuit components in a negative boost arrangement230A. As shown, the negative boost arrangement230A is represented inFIG. 3using the supply voltage node112, S1open (where S1corresponds to a transistor with a diode across its current terminals), the LY node122, the inductor120, the ground node118, S2closed (where S2corresponds to a diode (D1) when closed), S4closed, and the negative output supply node114. Other components described for the SIMO converter circuit102may be present as well (e.g., S3, the LX node124, and the positive output supply node116), but are not represented in the negative boost arrangement230A ofFIG. 3.

In the example ofFIG. 3, the low-side “on” detection stage312includes a detection circuit314coupled to the LY node122. As shown, the detection circuit314includes a Schmitt trigger316. During an inductor charge mode, S1turns on and current flowing through the inductor120(from the VIN node112to the ground node118) starts to increase. When sufficient current has built on the inductor120, S1is turned off causing current to steer from the transistor of S1to the diode D1. As this event occurs, the voltage at the LY node122rapidly decreases below the voltage at the VNEG node114, which causes D1to turn on. Since the voltage at the LY node122decreases quickly, a capacitor (e.g., the capacitor704inFIG. 7) causes the input of the Schmitt trigger316to toggle. As the discharge cycle finishes and the inductor current reverses, the voltage at the LY node122increases above the voltage at the VNEG node114at a slower rate. As this happens, a capacitor (e.g., the capacitor704inFIG. 7) pushes charge on the input of the Schmitt trigger316and immediately toggles its state, even before the voltage at the LY node122increases all the way to the input supply voltage (VIN) provided at node112. In some examples, the low-side “on” detection stage312can detect a switch “on” time with a very short duration (e.g., 20-100 ns).

As shown, the integration stage322includes an integration circuit324with a peak current value (e.g., the same value as the inductor charging phase threshold) and a current threshold value (Ith_sel). In some examples, the integration circuit324pushes a divided version of the estimated peak current into C1whenever the low-side diode/switch (S2) is on. In some examples, the peak inductor charging current is programmable using a signal (Ipk_sel). Also, the integration circuit324calculates the average output current minus the threshold current. In this case, when the average output current exceeds the threshold current, the voltage of C1increases. In another example, the integration circuit324calculates the average output current into a node voltage by charging C1in parallel with an optional resistor. In some examples, the integration circuit324uses a known fraction, (e.g., α= 1/10000), of the peak inductor current setting. Since this current is programmable, a scaling factor is applied to match the programmed value. This arrangement effectively estimates the average output current of the converter by utilizing the peak inductor current setting and S2“on” time information. The reason the current is estimated rather than measured is to avoid an ultra-high bandwidth, high quiescent current (Iq), large area, sense amp to precisely measure the current.

The compare stage332includes a compare circuit334with a comparator336. The inputs to the comparator336are the C1voltage from the integration stage322and a reference voltage (VREF). In response to the output of the integrator being above VREF, the compare circuit334outputs an overcurrent signal (IAVG_TH_EXCEEDED). In some examples, as inFIG. 3, the overcurrent signal is an indication that an average current estimate provided by the integration stage322exceeds a threshold. In some examples, the comparator336is used to detect when the current has exceeded the selected average current threshold, where the detection and filtering time can be chosen by the value of C1.

InFIG. 4, a current monitoring circuit400for high-side monitoring (e.g., positive boost mode monitoring) is represented. As shown, the current monitoring circuit400includes a power stage402, a high-side “on” detection stage412, an integration stage422, and a compare stage432. The power stage402ofFIG. 4includes SIMO converter circuit components in a positive boost arrangement220A. In other examples, a positive-only switching converter may include only S3and S4. As shown, the positive boost arrangement220A is represented inFIG. 4using the supply voltage node112, S1closed (or replaced by a short) (e.g., S1corresponds to a transistor with a diode across its current terminals), the LX node124, the inductor120, the ground node118, S3closed (in the form of a transistor with a diode across its current terminals), S4open (in the form of a transistor with a diode across its current terminals). Other components described for the SIMO converter circuit102may be present as well (e.g., S2the LY node122, and the negative output supply node114), but are not represented in the positive boost arrangement220A ofFIG. 4.

In the example ofFIG. 4, the high-side “on” detection stage412includes a detection circuit414coupled to the LX node124. As shown, the detection circuit414includes a Schmitt trigger416. During an inductor charge mode, S4turns on and current flowing through the inductor120(from the VIN node112to the ground node118) starts to increase. When sufficient current has built on the inductor120, S4is opened and S3is closed causing current to flow to the positive output supply node116. As this event occurs, the inductor120discharges and the voltage at the LX node124rapidly increases. Since the voltage at the LX node124increases quickly, C2inFIG. 4causes the input of the Schmitt trigger416to toggle. As the discharge cycle finishes, the inductor current reverses and the voltage at the LX node124decreases at a slower rate. As this happens, a capacitor (e.g., the capacitor704inFIG. 7) pushes charge on the input of the Schmitt trigger416and immediately toggles its state. In some examples, the high-side “on” detection stage412can detect a switch “on” time with a very short duration (e.g., 20-100 ns).

As shown, the integration stage422includes an integration circuit424with a peak current value (e.g., the same value as the inductor charging phase threshold) and a current threshold value (Ith_sel). In some examples, the integration circuit424pushes a divided version of the estimated peak current into C2whenever the high-side diode (part of S1) in on. In some examples, the peak current is programmable using a signal (Ipk_sel). Also, the integration circuit424calculates the average output current minus the threshold current. In this case, when the average output current exceeds the threshold current, the voltage of C2increases. In another example, the integration circuit424calculates the average output current into a node voltage by charging C2in parallel with an optional resistor. In some examples, the integration circuit424uses a known fraction, (e.g., α= 1/10000), of the estimated peak inductor current. Since this current is programmable, a scaling factor is applied to match the programmed value. The reason the current is estimated rather than measured is to avoid an ultra-high bandwidth, high quiescent current (Iq), large area, sense amp to precisely measure the current.

The compare stage432includes a compare circuit434with a comparator436. The inputs to the comparator436are the current estimate output from the integration stage422and a reference voltage (VREF). In response to the current estimate being above VREF, the compare circuit434outputs an overcurrent signal (IAVG_TH_EXCEEDED). In some examples, as inFIG. 4, the overcurrent signal is an indication that an average current estimate provided by the integration stage422exceeds a threshold. In some examples, the comparator436is used to detect when the current has exceeded the selected average current threshold, where the detection and filtering time can be chosen by the value of C2.

InFIG. 5, a current monitoring circuit500for high-side monitoring or low-side monitoring (e.g., positive boost mode monitoring and negative boost mode monitoring) is represented. As shown, the current monitoring circuit500includes a power stage502, an “on” detection stage512, an integration stage522, and a compare stage532. The power stage502ofFIG. 5includes SIMO converter circuit components. In a positive boost mode, S1and S3are closed, while S2and S4are open. In a negative boost mode, S2and S4is closed, while S1and S3are open. Also represented in the power stage502are the inductor120, the LY node122, the LX node124, the power supply node112, D1, the negative output power supply node114, the positive output power supply node116, and the ground node118. In other examples, the components included in the power stage502may vary.

In the example ofFIG. 5, the “on” detection stage512includes a first detection circuit514coupled to the LY node122. As shown, the first detection circuit514includes a Schmitt trigger515. The first detection circuit514operates is much the same manner as the detection circuit314described forFIG. 3. The “on” detection stage512also includes a second detection circuit516coupled to the LX node122. As shown, the second detection circuit516includes a Schmitt trigger518. The second detection circuit514operates is much the same manner as the detection circuit414described forFIG. 4.

As shown, the integration stage522includes an integration circuit524with a peak current value and a current threshold value (Ith_sel). In some examples, the integration circuit524pushes a divided version of the estimated peak current into C1or C2. In some examples, the peak current is programmable using a signal (Ipk_sel).

The compare stage532includes a compare circuit534with a first comparator536and a second comparator538. The inputs to the first comparator536(when used) are the current estimate output from the integration stage522to C2and a first reference voltage (VREF1). In response to the current estimate from the integration stage522being above VREF1, the compare circuit534outputs an overcurrent signal (IAVG_TH_EXCEEDED). The inputs to the second comparator538(when used) are the current estimate output from the integration stage522to C1and a second reference voltage (VREF2). In response to the current estimate from the integration stage522being above VREF2, the compare circuit534outputs IAVG_TH_EXCEEDED. In some examples, as inFIG. 5, the overcurrent signal is an indication that an average current estimate provided by the integration stage522exceeds a threshold.

FIGS. 6 and 7are schematic diagram showing current monitoring circuits600and700in accordance with various examples. InFIG. 6, the current monitoring circuit600includes a detector circuit602, an integrator circuit604, and a comparator606. More specifically, the integrator circuit604includes a first current digital-to-analog converter (DAC)612, a second current DAC608, and a reset device610. The first current DAC612modulates the current replica as the peak current changes. The second current DAC608sets the average current target threshold. The reset device610zeroes out the integrator circuit604.

InFIG. 7, the current monitoring circuit700includes a transistor702, a capacitor704, and a Schmitt trigger710. The current monitoring circuit700also includes circuits706and708. In the current monitoring circuit700, the transistor702and the capacitor704are part of an “on” detection circuit (see e.g., the “on” detection circuit314inFIG. 3) where the input to the detector circuit is the LY node122. Meanwhile, the circuit706is a “trim” circuit configured to align the rising and falling edge delays. In some examples, the characteristic delay difference is found via characterization and the best fit number is used for all parts. Also, the circuit708is a level translator configured to convert the signal to the integrator voltage domain.

The moment S1(see e.g.,FIG. 2) turns on for an inductor charge mode, inductor current flowing from a power supply node (e.g., the power supply node112inFIG. 1) to a ground node (e.g., the ground node118inFIG. 1) starts to increase. When sufficient current has built on the inductor, S1turns off, which causes current to steer from the transistor of S1to the parasitic capacitance at the LY node122. As this event occurs, the LY node122voltage rapidly decreases below the voltage of a negative output supply node (e.g., the negative output supply node114inFIG. 1) and causes a diode of S2(see e.g., D1inFIG. 3) to turn on. Since the voltage of the LY node122decreases quickly, the capacitor704below causes the input of the Schmitt trigger710to toggle. In the example ofFIG. 7. a low Vt NMOS device adjacent to Schmitt trigger710keeps the input of the Schmitt trigger710from going much below ground. As the discharge cycle finishes and the inductor current reverses, the LY node122increases above the voltage at the negative output supply node114at a slower rate. As this happens, the capacitor704pushes charge on the input of the Schmitt trigger710, causing its input voltage to increase from close to 0V to Vin, immediately toggling its state even before voltage at the LY node122increases all the way to the voltage at the power supply node112.

FIG. 8is a schematic diagram800of part of a current monitoring circuit802in accordance with various examples. As shown, the current monitoring circuit802includes an integration circuit803and a comparator804. More specifically, the integration circuit803includes a plurality of transistors, Q1-Q6, each having a first current terminal, a second current terminal, and a control terminal. The first current terminals of Q1and Q2are coupled to a power supply node806. The control terminals of Q1and Q2are coupled to each other. The second current terminal of Q1is coupled to the control terminal of Q1and to a first current source807A, where the first current source807A is between the second current terminal of Q1and a ground node808. In the example ofFIG. 8, the current through Q2corresponds to peak current setting divided by 20000 (I_peak_setting/20000). In different examples, the peak current setting and/or scaling of the peak current setting varies. The second current terminal of Q2is coupled to the first current terminals of Q3and Q4. The control terminal of Q3is directed by a clock signal (CS2), and the control terminal of Q4is directed by another clock signal (CS2_Z, where CS2_Z is the inverse of CS2). In some examples, CS2also directs S2(e.g., the switch to the negative output supply node114inFIG. 1). In other examples, a detector (e.g., the detection circuit314inFIG. 3) may be used to drive CS2and CS2_Z The second current terminal of Q4is coupled to the ground node808.

The second current terminal of Q3is coupled to the first current terminal of Q6and to one of the inputs of the comparator804. In some examples, as inFIG. 8, the current at the second current terminal of Q3is an average estimated current (Ireplica_avg). As shown, the second current terminal of Q6is coupled to the ground node808. Meanwhile, the control terminal of Q6is coupled to the control terminal of Q5and to a current source8076. More specifically, the current source807B is between the power supply node806and the control terminals of Q5and Q6. As shown, the control terminal of Q5is also coupled to the first current terminal of Q5. Finally, the second current terminal of Q5is coupled to the ground node808. In the example ofFIG. 8, the current through Q6is a threshold current (Ith), where Ith=2*Ilimit/20000=Ilimit/10000.

In the example ofFIG. 8, the second current terminal of Q3is also coupled to the top plate of a variable capacitor, C3. The bottom plate of C3is coupled to the ground node808. In the example ofFIG. 8, C3has a value of 50 pF. In operation, the difference between Ireplica_avgand Ith causes charge to build up at C3, to provide a voltage value to the comparator804, where an increasing voltage is a representation of the average output current exceeding a desired converter output threshold value. The other input to the comparator804is a reference voltage (VREF), which does not need to be precise. The output of the comparator804is a value Ilimit_det, where Ilimit_detcorresponds to IAVG_TH_EXCEEDED inFIGS. 3-5.

FIG. 9is a timing diagram900showing a current waveform912and an estimated current waveform922as a function of time in accordance with various examples. As shown, the current waveform912includes pulses914A and914B, where the average current of the current waveform912is Ilimit916. In the example ofFIG. 9, Ilimit=IpkDlim/2, where Ipkis the peak current and Dlimis the duty cycle (or the mathematical expression tS2/(tS2+tS1,S4), where ts2 is the amount of time where only S2is on). In the example ofFIG. 9, the estimated current waveform922has pulses924A and924B, where the average current of the estimated current waveform922is Ith926. In different examples, choosing pulses of Ipk/20000 results in Ith=Ipk/20000*Dlim, or Ilimit/10000. Example values for Ilimitand Ith are: ILIM=5 mA; and Ith=500 nA. Note: in the current estimator examples described herein, the estimator assumes an output current with a triangular shape. This is the case for a switching converter since the inductor behavior follows the equation: V=L*di/dt. For a constant V and L, di/dt is constant (e.g. the inductor current is linearly decreasing). Meanwhile, the estimated current waveform includes square shapes since switches can switch a constant current with ease in a circuit implementation.

In this description, the term “couple” or “couples” means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. Also, in this description, the recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, then X may be a function of Y and any number of other factors.