Method of forming crystallized silicon and method of fabricating thin film transistor and liquid crystal display using the same

A method of crystallizing amorphous silicon comprises forming an amorphous silicon layer on a substrate; forming an insulating layer on the amorphous silicon layer; forming a heat distributing metal layer on the insulating layer; and forming a thermite layer on the heat distributing metal layer. Ignition heat is then applied to ignite the thermite layer and generate sufficient localized exothermic heat from the ignited thermite layer so as to crystallize the amorphous silicon layer. The substrate beneath the amorphous silicon layer can be a heat sensitive substrate which is not substantially deformed by the localized crystallizing heat applied to the top portion of the amorphous silicon layer by way of the heat distributing metal layer and the insulating layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application relies for priority upon Korean Patent Application No. 2008-89975 filed on Sep. 11, 2008, the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

1. Field of the Invention

The present disclosure of invention relates to a method of crystallizing amorphous silicon and a method of fabricating a thin film transistor and liquid crystal display using the same. More particularly, the present invention relates to a method of crystallizing amorphous silicon using thermite and a method of fabricating a thin film transistor using the same.

2. Description of Related Technology

Recently, with the development of a more informational society, research and study have been actively performed on various flat screen display apparatuses. In order to selectively drive elements of the flat screen display apparatus, an active matrix scheme has been employed. According to such an active matrix scheme, an amorphous silicon thin film transistor (TFT) or a polycrystalline silicon TFT is used as a switching device.

The polycrystalline silicon TFT can be fabricated by crystallizing amorphous silicon. However, because such a crystallizing method conventionally requires a high-temperature process, the underlying substrate of the flat screen display apparatus may be compressed, expanded, or otherwise damaged.

SUMMARY

Therefore, the present disclosure provides a method of crystallizing amorphous silicon where the method is capable of minimizing heat-induced damage to an underlying substrate such as a plastic substrate for example.

The present disclosure also provides a method of fabricating a thin film transistor using the method of crystallizing the amorphous silicon.

According to one method of fabricating a polycrystalline silicon layer, a polycrystalline silicon thin film is directly deposited on an appropriate substrate. In an alternate approach, after depositing an amorphous silicon thin film on a substrate, the resultant structure is subjected to a heat treatment of sufficient temperature so that the entire amorphous thin film becomes crystallized. However, in order to employ a low-priced glass substrate or a low-priced plastic substrate that has only low temperature resistance, a low-temperature process is required, one below the temperature needed for conventional crystallization of the entirety of an amorphous silicon thin film. Nonetheless, the present disclosure provides a method of depositing an amorphous silicon layer on a low-temperature substrate and then crystallizing the amorphous silicon.

In order to deposit an amorphous silicon layer on a substrate and then crystallize the amorphous silicon layer without excessively damaging the underlying substrate, the present disclosure employs a localized heat treatment technology, namely, one using thermite. A method of crystallizing amorphous silicon according to the present disclosure is as follows. First, an amorphous silicon layer is formed on a substrate, and an insulating layer is formed on the amorphous silicon layer. Then, after a metal layer and a thermite layer are sequentially formed on the insulating layer, the substrate is heated to thereby ignite the thermite layer, generate localized heat on a top side of the amorphous silicon layer and thereby crystallize the amorphous silicon layer with the exothermic heat released from the reaction of the thermite layer.

In one embodiment, the insulating layer includes at least one of silicon oxide (SiOx) and silicon nitride (SiNx), and the metal layer includes at least one metal selected from the group consisting of silver (Ag), copper (Cu), gold (Au), aluminum (Al), rhodium (Rh), iridium (Ir), tungsten (W), molybdenum (Mo), cobalt (Co), zinc (Zn), nickel (Ni), cadmium (Cd), ruthenium (Ru), osmium (Os), platinum (Pt), palladium (Pd), tin (Sn), rubidium (Rb), chromium (Cr), tantalum (Ta), and niobium (Nb), or alloy of the metal.

In one embodiment, the thermite layer includes a mixture of very small particles (e.g., nano-particles) of metal, such as aluminum (Al), adjacent to very small particles (e.g., nano-particles) of one or more metal oxides. Nano-particles are sized between 1 and 100 nanometers in terms of diameter. When ignited to react, the combination of the particles of aluminum (Al) and the particles of metal oxide(s) exhibits an exothermic reaction temperature of about 1000° C. or more under adiabatic conditions. In one embodiment, the metal oxide is at least one oxide of an element selected from the group consisting of: silver (Ag), iron (Fe), nickel (Ni), titanium (Ti), cobalt (Co), chromium (Cr), vanadium (V), thallium (Ti), molybdenum (Mo), tungsten (W), niobium (Nb), boron (B), lead (Pb), manganese (Mn), silicon (Si), and uranium (U).

In one embodiment, the thermite layer is deposited on the metal layer in a liquid phase which contains a dispersion medium. Accordingly, the thermite layer may be formed on the metal layer through a spin-coating or an ink-jetting process. After drying of the dispersion medium, the thermite layer can be ignited by applying at least a prespecified minimum ignition temperature.

Since the localized high temperature occurs on a top side of the amorphous thin film, away from the side where the substrate is located, the substrate may include a flexible substrate material (e.g., a plastic material) having relatively low heat resistance.

The present disclosure provides a method of fabricating a thin film transistor substrate for a liquid crystal display or an organic light emitting display using the method of locally crystallizing the amorphous silicon. In the method of fabricating the thin film transistor substrate, after preparing a substrate, a gate electrode is formed on the substrate, and a gate insulating layer is formed on the substrate. Thereafter, an amorphous silicon layer is formed on the gate insulating layer, and the amorphous silicon layer is crystallized through the method of crystallizing the amorphous silicon. Source and drain electrodes are formed on the substrate having the crystallized amorphous silicon.

The thin film transistor substrate is applicable to various display apparatuses. The liquid crystal display can be manufactured by preparing a substrate facing the thin film transistor substrate and interposing a liquid crystal layer between the two substrates.

Since heat is locally applied using thermite to crystallize a silicon thin film, the method of crystallizing the amorphous silicon according to the present disclosure is applicable to a substrate having low temperature resistance.

DETAILED DESCRIPTION

Hereinafter, a display apparatus according to an exemplary embodiment will be described in detail with reference to accompanying drawings. It should be understood that the present disclosure is not to be taken as limited to what is shown in the drawings but rather as also teaching various modifications, equivalents and alternatives that are within the spirit and scope of the present disclosure. The drawings can be simplified or magnified to clearly express a plurality of layers and regions. In the drawings, the same reference numerals are used to designate same elements.

As used herein, the expression, “one film (layer) is formed (disposed) ‘on’ another film (layer) includes not only a case wherein the two films (layers) are in contact with each other but also a case wherein an additional film (layer) is present between the two films (layers).

FIGS. 1A to 1Dare sectional views sequentially showing the method of crystallizing amorphous silicon according to an exemplary embodiment.

As shown inFIG. 1A, a substantially amorphous silicon layer24is formed on a top major surface of a substrate10, where the top major surface defines a transparent and electrically insulating layer (e.g., a plastic layer).

The substrate10may include a flexible substrate which is heat-sensitive (e.g., is deformed by high temperatures) such as a plastic substrate. The substrate10may also include a typical glass layer or a quartz layer.

In order to deposit the amorphous silicon layer24, low temperature and low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) may be carried out.

Further, although not shown, a blocking layer (barrier layer) may be interposed between the substrate10and the amorphous silicon layer24. The blocking layer blocks impurities such as sodium (Na) that may exist in the substrate10from infiltrating into an upper layer in the process of the crystallization.

An insulating layer31is formed on the deposited amorphous silicon layer24. The insulating layer31prevents metal from a next provided metal layer33, from infiltrating into the amorphous silicon layer24. For example, infiltrating metal may react with the silicon and form undesirable metal silicides directly on or in silicon layer24. The insulating layer31may include insulating materials such as one or more silicon oxides (SiOx) and/or silicon nitrides (SiNx), where x represents compositional variables here.

The metal layer33is formed on the insulating layer31. The metal layer33is preferably one that can transfer heat uniformly over the entire surface of the to-be-crystallized amorphous silicon layer24. Preferably, the metal layer33includes metal having high thermal conductivity. Preferably, the metal having the high thermal conductivity includes silver (Ag), copper (Cu), gold (Au), aluminum (Al), rhodium (Rh), iridium (Ir), tungsten (W), molybdenum (Mo), cobalt (Co), zinc (Zn), nickel (Ni), cadmium (Cd), ruthenium (Ru), osmium (Os), platinum (Pt), palladium (Pd), tin (Sn), rubidium (Rb), chromium (Cr), tantalum (Ta), niobium (Nb), or alloy thereof. In particular, silver (Ag), which has the highest thermal conductivity among the listed options is most preferred to be included in metal layer33. Of course, silver tends to be expensive and thus metal layer33will often comprise other metals besides just silver.

Next, as shown inFIG. 1B, a first thermite layer40is formed on the metal layer33. In one embodiment, the first thermite layer40includes a mixture of small sized particles (e.g., nano-particles) of metal, such as aluminum (Al), magnesium (Mg), calcium (Ca), titanium (Ti), silicon (Si) and boron (B), and small sized particles (e.g., nano-particles) of an appropriate metal oxide that will exothermally react with the metal particles. Though silicon is not comprised in metal group conventionally, however, it should be understood that silicon will be described as a kind of metal due to its metallic property.

If nano-particles of aluminum (Al) and nano-particles of metal oxide are used, reaction contact area between the aluminum (Al) and the metal oxide is maximized, so that chemical reaction between the two can proceed rapidly and uniformly. In addition, the thermite layer40having nano-particles of both reactants can be easily coated over the substrate10.

In order to form the first thermite layer40on the metal layer33, thermite is preferably prepared in the form of a liquid phase to be easily coated on the substrate10. According to one embodiment, the nano-particles of aluminum (Al) and the nano-particles of the metal oxide are dispersed in a desired dispersion medium and mixed at a cool temperature. Any solvent that is capable of dispersing the mixture of the nano-particles of the aluminum (Al) and nano-particles of the metal oxide such that the mixture has a desired viscosity in a liquid phase can be used as the dispersion medium. However, the present disclosure does not limit the type of solvent to be used.

The first thermite layer40may be formed through an ink-jetting scheme, a spin-coating scheme, or a printing scheme. The spin-coating scheme may be employed when the first thermite layer40is formed on the entire surface of the substrate10. When the first thermite layer40is to be formed only on one or more specific regions of the substrate10, then the ink-jetting scheme or the printing scheme is preferably employed.

After forming the first thermite layer40, the dispersion medium (e.g., solvent) is removed through a low temperature drying process or the like, so that only the nano-particles of the aluminum (Al) and nano-particles of the metal oxide remain in mixed disposition with each other for later causing the exothermic thermite reaction to take place on top of the metal heat transfer layer33.

Thereafter, the first thermite layer40is heated, for example by heating the substrate10so as to thereby ignite and react the first thermite layer40. A possible reaction of the first thermite layer40is shown in the below first chemical reaction formula 1. The “Q” in the first chemical reaction formula 1 represents heat exothermically released by the reaction. In this case, the reaction of the first thermite layer40corresponds to an exothermic reaction wherein “Q” has a positive value, and the heat, which is released by the thermite reaction is sufficient to crystallize the amorphous silicon layer24.
Aluminum (Al)+Metal oxide→Aluminum oxide (Al2O3)+Metal+Q  Chemical Reaction Formula 1

The metal oxide, which participates in the thermite reaction with the aluminum (Al) as shown in chemical reaction formula 1 may include one or more oxides of silver (Ag), iron (Fe), nickel (Ni), titanium (Ti), cobalt (Co), chromium (Cr), vanadium (V), thallium (Ti), molybdenum (Mo), tungsten (W), niobium (Nb), boron (B), lead (Pb), manganese (Mn), silicon (Si), or uranium (U), or mixtures of the above oxides.

Since a high local temperature is required to crystallize the amorphous silicon layer24, the metal oxide is preferably selected among metal oxides which have a reaction temperature of at least 1000° C. during the thermite reaction. Table 1 shows chemical reaction formulae and reaction temperatures of the metal oxides causing the thermite reactions that have reaction temperatures of about 1000° C. and more under adiabatic conditions (see “Journal of Material Science 28 (1993) 3693-3708).

FIG. 2is a graph showing free energy of various metal oxides that are usable in accordance with the disclosure. As shown inFIG. 2, since free energy of the metal oxide participating in the thermite reaction with aluminum (Al) has a negative value (at least for temperatures of about 1000° K.), spontaneity of reaction is very great. Accordingly, even if heat is applied to the extent that only a starting thermite reaction is ignited, the full thermite reaction may occur. According to one embodiment, heat is applied to only a portion of the substrate10to ignite the initiating thermite reaction. In this case, ignition temperatures are different from each other according to the type of metal oxide used. For example, an initial ignition temperature may be in the range of about 550° C. to about 650° C. in thermite reaction based on iron oxide (Fe3O4) and an ignition temperature may be about 600° C. in thermite reaction based on molybdenum oxide (MoO3). An ignition temperature is about 650° C. in thermite reaction based on tungsten oxide (WO3). In addition, since the thermite reaction is exothermic reaction having a large negative value of enthalpy, even if reaction is started at a portion of the substrate10, chain reaction is subsequently caused by released heat.

As shown inFIG. 1C, after the thermite reaction is completed, a polycrystalline silicon layer24′ is formed under insulating layer31, metal layer33, and the post-ignition second thermite layer40′, where the latter includes aluminum oxide and the reduced metal obtained from the thermite reaction.

If the thermite layer40is selectively formed only on one or more specific regions of the substrate10, heat is locally applied to the amorphous silicon layer24corresponding to the regions of formation of the thermite layer40. Accordingly, the polycrystalline silicon layer24′ can be fabricated without substantial damage to the heat sensitive substrate10.

Next, as shown inFIG. 1D, the insulating layer31, the metal layer33, and the second thermite layer40′ formed on the polycrystalline silicon layer24′ are selectively removed (for example by chemical mechanical polishing or CMP), thereby leaving behind an exposed polycrystalline silicon layer,24″.

FIG. 3is a photographic view showing a case in which the amorphous silicon layer24is crystallized by using the thermite layer40when both of the insulating layer31and the metal layer33are not formed, andFIGS. 4A to 4Care views sequentially showing Raman spectroscopy for regions A to C ofFIG. 3. As shown inFIGS. 4A to 4C, it can be recognized that the polycrystalline silicon layer is formed in the region A ofFIG. 3, because only a peak of polycrystalline silicon is shown in the region A. However, only a peak of amorphous silicon is observed in the region B instead of the peak of the polycrystalline silicon. For the region C, both peaks of the polycrystalline silicon and the amorphous silicon are observed inFIG. 4Cthus indicating a mixture of both. Accordingly, it can be recognized that crystallization irregularly occurs in the regions A, B, and C.

In addition, since the thermite reaction occurs on the amorphous silicon substrate, a metal participating in the thermite reaction of aluminum (Al) and metal oxide may infiltrate into the polycrystalline silicon layer24′.FIG. 5is a graph showing energy dispersive X-ray spectroscopy (EDX) of the polycrystalline silicon layer24′ when the amorphous silicon layer24is crystallized using the thermite layer40in a state in which both the insulating layer31and the metal layer33are not formed and thus do not protect the silicon from metal infiltration. As shown in the graph ofFIG. 5, iron (Fe) and aluminum (Al) are contained in the polycrystalline silicon layer24′.

Therefore, according to the present disclosure, the metal layer33is formed to uniformly transfer heat to the amorphous silicon layer24. In this case, even if the thermite layer40is itself not coated uniformly, the metal layer33transfers heat to the amorphous silicon uniformly.

However, when only the metal layer33is formed on the amorphous silicon layer24, while thermite reaction is occurring, metal of the metal layer33tends to react with silicon atoms of the amorphous silicon layer24to form metal silicide.

FIG. 6is a photographic view showing a silicon layer after the thermite reaction when silver (Ag) is used for the metal layer33.FIG. 6shows an area which is surrounded by a dotted line and has been subject to the thermite reaction after a silver (Ag) layer is formed on the amorphous silicon layer24. As shown inFIG. 6, dark-colored silver silicide (AgSi) is observed in place of the metal layer33.

Accordingly, in order to prevent metal silicide from being formed due to the metal layer33and prevent metal used for the thermite layer40from infiltrating into crystallized silicon as impurities, the insulating layer31is additionally formed to make a double layer with the metal layer33.

FIGS. 7 and 8are respectively a photographic view and an EDX graph showing the substrate10that is crystallized after the thermite layer40is formed on the amorphous substrate having the insulating layer31and the metal layer33. As shown inFIG. 7, when the double layer of the insulating layer31and the metal layer33is provided, the polycrystalline silicon layer24′ is uniformly formed, and metal impurities used for the thermite layer40are rarely observed in the substrate10.

When the double layer is provided, the thickness of the insulating layer31may be adjusted according to the desired polycrystalline silicon layer24′ or surrounding conditions. As the insulating layer31becomes thinned, a degree of crystallization is improved. If the insulating layer31having a relatively large thickness is formed, heat may not be sufficiently transferred to the amorphous silicon layer24due to an insulating substance having a characteristic heat insulating effect.

FIGS. 9A and 9Bare respectively graphs showing Raman spectroscopy of a crystallized silicon thin film according to variations in the thickness of the insulating layer31and showing the size (see curve (i) ofFIG. 9B) of full width of half maximum (FWHM) and a peak position (see curve (ii)) according to the thickness (marked as “buffer oxide thickness” in drawings) of the insulating layer31. The FWHM represents a peak width at a half position of the maximum peak intensity in the Raman spectroscopy.

Referring toFIGS. 9A and 9B, as the thickness of the insulating layer31becomes smaller, the peak of the silicon layer goes closer to corresponding to a peak of just polycrystalline silicon. As the thickness of the insulating layer31(buffer oxide) becomes greater, the FWHM is gradually increased, resulting in appearance of the peak of amorphous silicon remarkably even when the thickness of the insulating layer31is as large as about 600 nm. As shown inFIG. 9B, when the thickness of the insulating layer31is about 100 nm, a peak appears at about 520 cm−1which is a peak position of polycrystalline silicon. However, as the thickness of the insulating layer31increases, the peak moves into closer correspondence with a peak position of the amorphous silicon, resulting in appearance of the peak appears at a peak position of about 517 cm−1when the thickness of the insulating layer31is about 600 nm. In addition, when the thickness of the insulating layer31is about 100 nm, the FWHM is about 4 cm−1. When the thickness of the insulating layer31is about 600 nm, the FWHM is about 12 cm−1and more. In this case, it can be recognized fromFIG. 9Athat the FWHM is enlarged due to overlap with the peak of the amorphous silicon.

As a result, the insulating layer31preferably has the thickness sufficient to prevent metal of the metal layer33from forming metal silicide and also to prevent infiltration of metal of the thermite layer40but also thin enough to assure substantial crystallization.

As described above, in the method of crystallizing amorphous silicon according to the present disclosure, the insulating layer31and the metal layer33are formed to uniformly transfer heat, thereby forming uniform polycrystalline silicon while minimizing the infiltration of impurities.

In addition, since a high-temperature heat is applied to a narrow region for a short time through a local heat treatment technology, the method of crystallizing amorphous silicon according to the present disclosure is applicable to a substrate having sensitivity to heat. In particular, the method of crystallizing amorphous silicon according to the present disclosure may be applicable to a flexible substrate such as a plastic substrate.

A silicon thin film crystallized according to an exemplary embodiment may be used when a semiconductor device such as a thin film transistor, a solar battery, or an image sensor is to be manufactured. The thin film transistor employing the crystallized silicon thin film can be used for various display apparatuses such as a liquid crystal displays and an organic electro-luminescence displays. Hereinafter, the thin film transistor including the crystallized silicon thin film and a liquid crystal panel having the same will be described as an example.

Hereinafter, a method for manufacturing a liquid crystal display (LCD) according to an embodiment of the present disclosure will be described in detail with reference to accompanying drawings.

FIG. 10is a plan view showing a portion of a thin film transistor substrate110of the LCD according to an exemplary embodiment. Although the thin film transistor substrate110includes N gate lines and M data lines crossing each other to form M×N pixel areas, only an (M×N)thone of the pixels is shown inFIG. 10for the convenience of explanation.

As shown inFIG. 10, the thin film transistor substrate110is provided. On the thin film transistor substrate an nthgate line116nand an mthdata line117mare formed and arranged horizontally and vertically to define an (m×n)thpixel area. A thin film transistor, which is a switching element, is formed at an interconnection area of the nthgate line116nand the mthdata line117m, and a pixel electrode118is connected to the thin film transistor in the (m×n)thpixel area to drive liquid crystal material (not shown) in cooperation with a common electrode of a color filter substrate (not shown).

The thin film transistor includes a gate electrode121connected to or formed as a portion of the nthgate line116n, a source electrode122connected to the mthdata line117m, and a drain electrode123connected to the pixel electrode118. In addition, the thin film transistor includes a first insulating layer (not shown) to insulate the gate electrode121from the source and drain electrodes122and123and an active pattern (not shown) used to form a conductive channel between the source electrode122and the drain electrode123by a gate voltage applied to the gate electrode121.

A portion of the source electrode122is connected to the mthdata line117mto form a portion of the mthdata line117m, and a portion of the drain electrode123extends to the pixel area to be electrically connected to the pixel electrode118through a contact hole139formed in a second insulating layer (not shown).

Hereinafter, the manufacturing process of the thin film transistor substrate110having the above structure according to the present embodiment will be described.

FIGS. 11A to 11Eare sectional views taken along line XII-XII′ of the thin film transistor substrate110shown inFIG. 10to sequentially show the manufacturing process of the thin film transistor substrate110.

As shown inFIG. 11A, a patterned gate electrode121and a patterned gate line116n-1are formed on a thin film transistors supporting substrate (TFT substrate)110where a top major surface of substrate110is composed of a transparent insulating material such as a glass or a plastic. In this case, the gate electrode121and the gate line116n-1may be formed by depositing a first conductive film on the entire surface of the thin film transistor substrate110and then patterning the first conductive film through a photolithography process.

Next, as shown inFIG. 11B, after sequentially depositing a gate insulating layer115A and an amorphous silicon layer124(seeFIG. 12A) on the entire surface of the thin film transistor substrate110which has the gate electrode121and the gate line116n-1preformed thereon, the amorphous silicon layer124is crystallized to a polycrystalline silicon layer124′ using reaction of a first thermite layer140(see intermediate step shown inFIG. 12B).

FIGS. 12A and 12Bare sectional views showing a process of crystallizing the amorphous silicon layer124. Referring toFIG. 12A, an insulating layer131is formed on the entire surface of the thin film transistor substrate110having the gate electrode121and the gate line116n-1by using an insulating substance such as a silicon oxide (SiOx), and then a metal layer133is formed on the entire surface of the thin film transistor substrate110.

Thereafter, as shown inFIG. 12B, the first thermite layer140is formed on the thin film transistor substrate110having the metal layer133. The first thermite layer140may be blanket formed on the entire surface of the thin film transistor substrate110through a spin coating process, or selectively formed across the surface using an ink-jetting, or a printing process. In one embodiment, the first thermite layer140is formed only on a preset region of the thin film transistor substrate110corresponding to where polysilicon is to be formed through crystallization of amorphous silicon.

Then, the thin film transistor substrate110is heated to ignite the reaction of the first thermite layer140, so that heat is released to crystallize the amorphous silicon layer124, thereby forming the polycrystalline silicon layer124′.

In this case, a post-ignition or second thermite layer140′ after the thermite reaction, and the metal layer133and the insulating layer131formed below the second thermite layer140′ may be selectively removed if so desired by selective CMP or other selective removal processes as deemed appropriate.

FIG. 11Bshows a polycrystalline silicon substrate obtained by removing the second thermite layer140′, the metal layer133, and the insulating layer131.

Thereafter, as shown inFIG. 11C, after implanting impurity ions onto the polycrystalline silicon layer124′ and depositing a second conductive layer (122,123,125) on the resultant structure, the polycrystalline silicon layer124′ and the second conductive layer are selectively patterned through a photolithography process, thereby forming a patterned active pattern124″ including a polycrystalline silicon channel region disposed over the gate electrode121and also forming the spaced-apart source electrode122and the drain electrode123on opposed sides of the channel region where each of the source and drain electrodes122,123is defined by a respective patterned section of the second conductive layer (122,123,125).

The ohmic contact layer125″ portion of the second conductive layer is formed on the active pattern124″. Under the ohmic contact layer125″, a heavily doped, n+ polycrystalline silicon layer is patterned in the same shape as that of the source electrode122and the drain electrode123, such that a predetermined region of the active pattern124″ makes good ohmic-contact with the source and drain electrodes122and123. In this case, the source electrode122corresponds to a portion of a data line117mcrossing the gate line116n-1to define a pixel area.

Although for the illustrated embodiment the active pattern124″, the ohmic-contact layer125″, the source electrode122, and the drain electrode123are simultaneously formed through one photolithography process using a diffraction mask or a half-tone mask, the present disclosure is not limited to such one-step patterning. For example, according to another exemplary embodiment, after implanting impurity ions onto the polycrystalline silicon layer124′, the resultant structure is selectively patterned through a photolithography process to form the active pattern124″ and the ohmic-contact layer125″. Then, after depositing the second conductive layer on the entire surface of the thin film transistor substrate110, a photolithography process may be performed to form the source and drain electrodes122and123.

Then, as shown inFIG. 11D, after depositing a protective layer115B (transparent passivation layer) on the entire surface of the thin film transistor substrate110having the source and drain electrodes122and123, a portion of the protective layer115B is removed through a photolithography process to form the drain contact hole139exposing a portion of the drain electrode123.

Thereafter, as shown inFIG. 11E, after depositing a transparent conductive material (e.g., ITO, IZO) on the entire surface of the thin film transistor substrate110, the resultant structure is selectively patterned through the photolithography process, thereby forming a pixel electrode118electrically connected with the drain electrode123through the contact hole139.

In this case, the transparent material includes indium tin oxide (ITO) or indium zinc oxide (IZO), which have optical transmittance.

The thin film transistor substrate110having the above structure is aligned in opposition to a color filters substrate (not shown) by a sealant (not shown) formed on an outer peripheral portion of an image display area, and a liquid crystal layer is interposed between the two substrates, that is, the thin film transistors substrate110and the color filters substrate, thereby constructing a liquid crystal panel.

Although the thin film transistor substrate110of the LCD has been described as an example according to one embodiment, the present disclosure is not limited to just LCD's. In other words, the here disclosed technique of forming TFT's having a crystallized active layer is applicable to other display technologies where formation of a transistor or other electronic switching element is desirable. For example, the here disclosed technique may be applicable to other display apparatuses including a thin film transistor, for example, an organic electro-luminescence display, in which a driving transistor is connected to an organic light emitting diode (OLED), or a plasma display panel (PDP) display.

Although exemplary embodiments have been described, it is understood that the present disclosure should not be limited to these exemplary embodiments but various changes and modifications can be made by one ordinary skilled in the art in view of the present disclosure and within the spirit and scope of the present disclosure.