On demand knockout of coarse sensing based on dynamic source bounce detection

Systems, apparatuses and methods may provide for determining a magnitude of a bounce voltage on a source line associated with one or more memory cells and conducting, if the magnitude of the bounce voltage exceeds a threshold, a coarse-level program verification and a fine-level program verification of the one or more memory cells. Additionally, if the magnitude of the bounce voltage does not exceed the threshold, only the fine-level program verification of the one or more memory cells may be conducted. In one example, the coarse-level program verification is bypassed if the magnitude of the bounce voltage does not exceed the threshold.

TECHNICAL FIELD

Embodiments generally relate to programming memory structures.

BACKGROUND

Programming conventional NAND flash memory may involve applying a sequence of program pulses to the cells of the flash memory, with each program pulse being followed by coarse-level program verification and optional fine-level program verification for the memory cells that are not verified during the coarse-level program verification. Such an approach may increase programming time and have a negative impact on performance.

DESCRIPTION OF EMBODIMENTS

Turning now toFIG. 1, a program waveform10is shown for a memory structure. The program waveform10can be used for a NAND flash memory, three-dimensional (3D) NAND memory array devices, or other memory devices. In the illustrated example, a sequence of program pulses12(12a-12e) are generated (e.g., beginning at voltage Vpgm_start) for different programming levels (e.g., n levels), with successive instances of the pulses12being incremented by a step value (e.g., n*Vpgm_step). Thus, a leftmost program pulse12amay represent an initial pulse for level one, a middle program pulse12dmay represent an initial pulse for level two, a rightmost program pulse12emay represent an initial pulse for level three, and so forth. Programming verification operations may generally be conducted after each program pulse12, wherein the programming verification operations determine whether the program pulse12has successfully set the memory cell voltage for the programming level(s) involved. Thus, first verification pulses14(e.g., Pv_L1) may be generated after level one program pulses12, second verification pulses16(e.g., Pv_L2) may be generated after level two program pulses12, third verification pulses18(e.g., Pv_L3) may be generated after level three program pulses, and so forth, wherein the verification pulses14,16,18may be applied to the memory cells in question.

The programming verifications may include coarse-level and/or fine-level program verifications. As will be discussed in greater detail, information regarding the difference from the target voltage to the source voltage (e.g., voltage “source bounce” due to bus current multiplied by bus resistance) may be used to selectively bypass the coarse-level program verification. Such an approach may decrease programming time and enhance performance.

FIG. 2Ashows a memory subsystem20that includes a plurality of memory cells22coupled to a source line24of a memory bus.FIG. 2Bshows a first NAND string31of transistors and a second NAND string21of transistors, wherein the NAND strings21,31(e.g., nodes, cells) may be included in the plurality of memory cells22(FIG. 2A). In general, the first NAND string31is relatively close to a source driver29and the second NAND string21is relatively far away from the source driver29. The illustrated second NAND string21includes a selected word line23(selWL) and one or more unselected word lines (unselWL). The second NAND string21may also include a bit line25(bl) connection on a drain side of the second NAND string21and the source line24(src) connection on a source side of the second NAND string21. In addition, a select gate drain-side (sgd) device may couple the second NAND string21to the bit line25connection and a select gate source-side (sgs) may couple the second NAND string21to the source line24connection. The illustrated first NAND string31is the nearest node to the source driver29and may be coupled to the source driver29via a source return line35(src_return) connection. The source line24and the source return line35may be part of a source mesh having a resistance33that increases as the distance from the source driver29increases.

Referring again toFIG. 2A, a memory controller apparatus26(26a,26b) may also be coupled to the source line24of the memory bus, wherein a source bounce detector26amay determine a magnitude of a bounce voltage on the source line24. In this regard, a program verify operation may include sensing a voltage and/or current change of a bit line coupled to a target/selected cell in the plurality of memory cells22in order to determine the data state of the target cell. The sensing operation may involve applying a signal to (e.g., driving or biasing) a bit line associated with a target memory cell above a signal (e.g., bias voltage) applied to a source line associated with the target memory cell. The sensing operation may therefore include pre-charging the bit line followed by discharge when the target cell begins to conduct, and sensing the discharge. Thus, the source bounce may be considered the difference from the target voltage to the source voltage, wherein the difference is due to bus current multiplied by bus resistance. In one example, the source bounce detector26asamples a return voltage and a source voltage on the source line24in order to determine the source bounce.

The source bounce detector26amay include a buffer stage32and an amplification stage34coupled to the buffer stage32. Moreover, the source bounce detector26amay sample the source voltage from a selected node in the plurality of memory cells22, wherein the distance between the selected node and a driver such as the source driver29(FIG. 2B) coupled to the source line24is greater than a distance between one or more other nodes in the plurality of memory cells22and the driver. The selected node may therefore be considered a “worst case” node due to a relatively high source mesh resistance that may result in a highest expected bounce voltage magnitude at the selected node. For example, the selected node might be the farthest NAND string such as, for example, the second NAND string21(FIG. 2B) in the plurality of memory cells22, relative to the source driver. In another example, the selected node in a 3D NAND architecture might be the farthest in a tile column when the source driver is referring to a local source return that is relatively close to the driver.

The source bounce determined by the source bounce detector26amay be used by a verification manager26bto determine whether the one or more memory cells were programmed successfully. More particularly, the illustrated verification manager26bincludes a coarse component28and a fine component30. If the magnitude of the bounce voltage exceeds a threshold such as, for example, a maximum system-tolerable technology-determined threshold, the verification manager26bmay use the coarse component28to conduct a coarse-level program verification of the one or more memory cells and use the fine component30to conduct a fine-level program verification of the one or more memory cells. If, on the other hand, the magnitude of the bounce threshold equals or falls below the threshold, the verification manager26bmay only use the fine component30to conduct the fine-level program verification of the one or more memory cells. In this regard, a relatively low source bounce may indicate that the coarse-level program verification may be bypassed without concern over the ability of the fine component30to tolerate the source bounce.

Although depicted as part of a memory controller apparatus, either or both of the source bounce detector26aand verification manager26bmay be implemented within a memory device.

Turning now toFIG. 3, a set of program waveforms are shown for a particular program pulse. In the illustrated example, a program pulse40is used to program one or more memory cells such as, for example, the memory cells22(FIG. 2A). The illustrated timings may be described as follows—tsen_ko: sense time for coarse sensing; tsen: sense time for fine sensing; and tko_bl: bit line cleanup time after sensing.

The program pulse40may generally correspond to the rightmost program pulse12e(FIG. 1), already discussed, that initiates the level three programming sequence. Additionally, a first region54(54a,54b) may correspond to the first verification pulse14(FIG. 1) following the level three program pulse, wherein the first region54includes a coarse-level region54aand a fine-level region54b. Similarly, a second region56(56a,56b) may correspond to the second verification pulse16(FIG. 1) following the level three program pulse, wherein the second region56includes a coarse-level region56aand a fine level region56b. A third region57(57a,57b) may correspond to the third verification pulse18(FIG. 1) following the level three program pulse, wherein the third region57includes a coarse-level region57aand a fine-level region57b.

Of particular note is that the coarse-level region57amay be selectively skipped based on whether a magnitude of a bounce voltage46exceeds a threshold48. As already noted, the bounce voltage46may be sampled from a selected node that represents a worst case node. For example, a skip knockout signal50may be asserted in response to the magnitude of the bounce voltage46equaling or falling below the threshold48in the coarse-level region57a. A delay between assertion of the skip knockout signal50and the magnitude of the bounce voltage equaling or falling below the threshold48may be due to propagation delay and/or decision timing of the system. In this regard, the assertion of the skip knockout signal50may be made by its value transitioning to either logical high or logical low. As a result, the time associated with the coarse-level program verification (e.g., tsen_ko and tko_bl) may be skipped/avoided and fine-level program verification can be used instead for program verify. Accordingly, the illustrated approach may substantially enhance performance by reducing programming verification time via on demand knockout of coarse sensing.

FIG. 4shows a method58of verifying memory programming. The method58may generally be implemented in a memory controller apparatus such as, for example, the memory controller apparatus26(FIG. 2), already discussed. More particularly, the method58may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as, for example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), in fixed-functionality logic hardware using circuit technology such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof.

Illustrated processing block60provides for determining a magnitude of a bounce voltage on a source line associated with one or more memory cells, wherein a determination may be made at block62as to whether the magnitude of the bounce voltage exceeds a threshold. If not, illustrated block63conducts only a fine-level program verification of the one or more memory cells. Otherwise, a coarse-level program verification of the one or more memory cells may be conducted at block64and illustrated block66conducts a fine-level program verification of the memory cell(s) that were not knocked out by the coarse-level program verification.

FIG. 5shows one approach to implementing a source bounce detector such as, for example, the source bounce detector26a(FIG. 2). In the illustrated example, a buffer stage68having a source follower (SF) transistor76(e.g., NMOS/N-type Metal Oxide Semiconductor) and a current source69is coupled, via switches67, to a source line72(72a,72b) and an amplification stage70is coupled to the buffer stage68. The amplification stage70may include an operational amplifier74that is optionally auto-zeroed at time to (e.g., during an auto-zero phase). Auto-zeroing may be considered the removal of any voltage offset associated with the operational amplifier74. At time t1(e.g., during a first active phase), a return portion72aof the source line72may be sampled via the buffer stage68in order to determine a return voltage (e.g., src_return). The return voltage may be applied to the gate of the SF transistor76, wherein an initial charge as indicated in Expression (1) below may be stored onto a first capacitor C1.
Q1_i=C1(src_return−Vth−Vref)  (1)

Where Vth is the threshold voltage of the SF transistor and Vref is a general reference voltage that is common to the operational amplifier74and a comparator75(discussed in greater detail below). At time t2(e.g., during a second active phase), a source portion72bof the source line72may be sampled via the buffer stage68in order to determine a source voltage (e.g., src). The source voltage may be applied to the gate of the source follower transistor76, wherein a new final charge as indicated in Expression (2) below may be stored onto the capacitor C1.
Q1_f=C1(src−Vth−Vref)  (2)

Thus, the difference in charge may be given by.
ΔQ=Q1_f−Q1_i=C1(src−src_return)  (3)

Accordingly, the voltage threshold is a common mode that disappears from the expression. Additionally, any threshold mismatch at the SF transistor76may be disregarded. The amplification stage70may also include a second capacitor C2and a switch71, wherein,
ΔQ=Q2=C2(Vout−Vref)  (4)

Where the switch71is closed at time t1, the switch71is open at time t2and Vout is the output voltage. The node common to C1and C2may be an isolated node, wherein any charge moving away from C1may necessarily be stored on C2. Accordingly,
C1(src−src_return)=C2(Vout−Vref)  (5)
Vout=C1/C2(src−src_return)+Vref  (6)

At time t3(e.g., a final comparison phase), a comparator75may compare Vref+threshold*N to Vref+(C1/C2)*Δ, where N=C1/C2(e.g., gain factor) and Δ is the source bounce. If Vout=Vcc coarse-level program verification may be bypassed.

FIG. 6shows a performance-enhanced computing system80. The computing system80may generally be part of an electronic device/platform having computing functionality (e.g., personal digital assistant/PDA, notebook computer, tablet computer, server), communications functionality (e.g., smart phone), imaging functionality, media playing functionality (e.g., smart television/TV), wearable functionality (e.g., watch, eyewear, headwear, footwear, jewelry), vehicular functionality (e.g., car, truck, motorcycle), etc., or any combination thereof. In the illustrated example, the system80includes a power source82to supply power to the system80and a processor84having an integrated memory controller (IMC)86, which may use a bus88to communicate with a system memory90. The system memory90may include, for example, volatile dynamic RAM (DRAM) configured as one or more memory modules such as, for example, dual inline memory modules (DIMMs), small outline DIMMs (SODIMMs), etc.

The illustrated system80also includes an input output (IO) module92implemented together with the processor84on a semiconductor die94as a system on chip (SoC), wherein the JO module92functions as a host device and may communicate with, for example, a display96(e.g., touch screen, liquid crystal display/LCD, light emitting diode/LED display), a network controller98, and mass storage100(e.g., hard disk drive/HDD, optical disk, flash memory, etc.). The mass storage100may include logic102that determines a magnitude of a bounce voltage on a source line associated with one or more memory cells in the mass storage100. The logic102may also conduct a coarse-level program verification and a fine-level program verification of the one or more memory cells if the magnitude of the bounce voltage exceeds a threshold. If, on the other hand, the magnitude of the bounce voltage equals or falls below the threshold, the logic102may conduct only the fine-level program verification of the one or more memory cells. Thus, the logic102may implement one or more aspects of the method58(FIG. 4), already discussed. The logic102, which may be implemented in logic instructions, configurable logic and/or fixed-functionality logic hardware, may optionally be implemented elsewhere in the system80such as, for example, in the IMC86, IO module92, and so forth.

Additional Notes and Examples

Example 1 may include a performance-enhanced computing system comprising a system on chip (SoC), a bus coupled to the SoC, the bus including a source line, and a memory subsystem coupled to the bus, the memory subsystem including a plurality of memory cells associated with the source line and a controller apparatus comprising, a source bounce detector to determine a magnitude of a bounce voltage on the source line, and a verification manager to conduct a coarse-level program verification and a fine-level program verification of one or more of the plurality of memory cells if the magnitude of the bounce voltage exceeds a threshold, and conduct the fine-level program verification of the one or more memory cells if the magnitude of the bounce voltage equals or falls below the threshold, wherein the coarse-level program verification is to be bypassed if the magnitude of the bounce voltage equals or falls below the threshold.

Example 2 may include the system of Example 1, wherein the source bounce detector is to sample a return voltage on the source line and sample a source voltage on the source line.

Example 3 may include the system of Example 2, wherein the source bounce detector includes a buffer stage, and an amplification stage coupled to the buffer stage, the amplification stage comprising an operational amplifier, wherein the return voltage and the source voltage are to be sampled via the buffer stage.

Example 4 may include the system of Example 3, wherein the verification manager is to auto-zero the operational amplifier prior to determining whether the magnitude of the bounce voltage exceeds the threshold.

Example 5 may include the system of any one of Examples 2 to 4, wherein the source bounce detector is to sample the source voltage from a selected node.

Example 6 may include the system of Example 5, wherein a distance between the selected node and a driver coupled to the source line is greater than a distance between one or more other nodes and the driver.

Example 7 may include the system of claim1, further comprising at least one processor communicatively coupled to the memory subsystem and a network interface communicatively coupled to the at least one processor.

Example 8 may include a memory controller apparatus comprising a source bounce detector to determine a magnitude of a bounce voltage on a source line associated with one or more memory cells, and a verification manager to conduct a coarse-level program verification and a fine-level program verification of the one or more memory cells if the magnitude of the bounce voltage exceeds a threshold, and conduct the fine-level program verification of the one or more memory cells if the magnitude of the bounce voltage equals or falls below the threshold, wherein the coarse-level program verification is to be bypassed if the magnitude of the bounce voltage equals or falls below the threshold.

Example 9 may include the apparatus of Example 8, wherein the source bounce detector is to sample a return voltage on the source line and sample a source voltage on the source line.

Example 10 may include the apparatus of Example 9, wherein the source bounce detector includes a buffer stage, and an amplification stage coupled to the buffer stage, the amplification stage comprising an operational amplifier, wherein the return voltage and the source voltage are to be sampled via the buffer stage.

Example 11 may include the apparatus of Example 10, wherein the verification manager is to auto-zero the operational amplifier prior to determining whether the magnitude of the bounce voltage exceeds the threshold.

Example 12 may include the apparatus of any one of Examples 9 to 11, wherein the source bounce detector is to sample the source voltage from a selected node.

Example 13 may include the apparatus of Example 12, wherein a distance between the selected node and a driver coupled to the source line is greater than a distance between one or more other nodes and the driver.

Example 14 may include a method of verifying memory programming, comprising determining a magnitude of a bounce voltage on a source line associated with one or more memory cells, conducting a coarse-level program verification and a fine-level program verification of the one or more memory cells if the magnitude of the bounce voltage exceeds a threshold, and conducting the fine-level program verification of the one or more memory cells if the magnitude of the bounce voltage equals or falls below the threshold, wherein the coarse-level program verification is bypassed if the magnitude of the bounce voltage equals or falls below the threshold.

Example 15 may include the method of Example 14, wherein determining the magnitude of the bounce voltage includes sampling a return voltage on the source line, and sampling a source voltage on the source line.

Example 16 may include the method of Example 15, wherein the return voltage and the source voltage are sampled via a buffer stage coupled to an amplification stage.

Example 17 may include the method of Example 16, further including auto-zeroing an operational amplifier of the amplification stage prior to determining whether the magnitude of the bounce voltage exceeds the threshold.

Example 18 may include the method of any one of Examples 15 to 17, further including sampling the source voltage from a selected node.

Example 19 may include the method of Example 18, wherein a distance between the selected node and a driver coupled to the source line is greater than a distance between one or more other nodes and the driver.

Example 20 may include a memory controller apparatus comprising means for determining a bounce voltage on a source line associated with one or more memory cells, means for conducting a coarse-level program verification and a fine-level program verification of the one or more memory cells if the magnitude of the bounce voltage exceeds a threshold, and means for conducting the fine-level program verification of the one or more memory cells if the magnitude of the bounce voltage equals or falls below the threshold, wherein the coarse-level program verification is to be bypassed if the magnitude of the bounce voltage equals or falls below the threshold.

Example 21 may include the apparatus of Example 20, wherein the means for determining the magnitude of the bounce voltage includes means for sampling a return voltage on the source line, and means for sampling a source voltage on the source line.

Example 22 may include the apparatus of Example 21, wherein the return voltage and the source voltage are to be sampled via a buffer stage coupled to an amplification stage.

Example 23 may include the apparatus of Example 21, further including means for auto-zeroing an operational amplifier of the amplification stage prior to determining whether the magnitude of the bounce voltage exceeds the threshold.

Example 24 may include the apparatus of any one of Examples 21 to 23, further including means for sampling the source voltage from a selected node.

Example 25 may include the apparatus of Example 24, wherein a distance between the selected node and a driver coupled to the source line is greater than a distance between one or more other nodes and the driver.

Techniques described herein may therefore achieve programming time savings via an on demand knockout feature that uses dynamic source bounce detection to skip coarse sensing if the observed bounce is less than a predetermined threshold.