SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a semiconductor substrate; a semiconductor element disposed on a first surface of the semiconductor substrate; an insulation film, which is disposed on the first surface of the semiconductor substrate to cover the semiconductor element and has first contact holes exposing a region in the first surface of the semiconductor substrate, and second contact holes exposing the semiconductor element; a first electrode electrically connected to a region in the first surface of the semiconductor substrate through the first contact holes; and a second electrode electrically connected to the semiconductor element through the second contact hole. The insulation film has a first surface, which is flattened and opposite from the first surface of the semiconductor substrate. An interval between the first surface of the insulation film and the first surface of the semiconductor substrate is equal along a planer direction of the semiconductor substrate.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

BACKGROUND

A semiconductor devices may include a temperature sensitive diode element, which is a diode element as a semiconductor element. The temperature sensitive diode element may be formed on a semiconductor substrate. More specifically, such a semiconductor device includes various types of regions formed on the semiconductor substrate, in order to allow an electric current flowing through the semiconductor substrate. These various types of regions are, for example, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) elements, which may include P-type regions and N-type regions.

SUMMARY

The present disclosure describes a semiconductor device, which includes a semiconductor element such as a diode element formed on a semiconductor substrate. Additionally, the present disclosure describes a method for manufacturing the semiconductor device.

DETAILED DESCRIPTION

On one surface of a semiconductor substrate, a temperature sensitive diode element through an insulation film may be formed, and the insulation film covering the temperature sensitive diode element may be formed. In the insulation film covering the temperature sensitive diode element, first contact holes for exposing a region formed in the one surface of the semiconductor substrate and second contact holes for exposing the temperature sensitive diode element may be formed.

On the insulation film covering the temperature sensitive diode element, a first electrode and a second electrode may be formed. The first electrode is electrically connected to a region formed in the one surface of the semiconductor substrate through the first contact holes, and the second electrode is electrically connected to the temperature sensitive diode element through the second contact holes.

Such a semiconductor device may be fabricated as follows. A temperature sensitive diode element is formed on one surface of a semiconductor substrate and, thereafter, an insulation film is formed as to cover the temperature sensitive diode element. Regions to be formed in the one surface of the semiconductor substrate are properly formed before or after the formation of the temperature sensitive diode element. A photoresist is placed on the insulation film. The photoresist is patterned by light exposure and photographic processing, and therefore the regions of the insulation film, where first contact holes and second contact holes are to be formed, are exposed from the photoresist. A first electrode, which is electrically connected to a region in the one surface of the semiconductor substrate through the first contact holes, is formed. A second electrode, which is electrically connected to the temperature sensitive diode element through the second contact holes, is formed. The semiconductor device is manufactured as described above.

However, with such a semiconductor device, when the insulation film has been formed as to cover the temperature sensitive diode element, the insulation film may be bulged at the portion covering the temperature sensitive diode element. The one surface of the insulation film, which is opposite from the one surface of the semiconductor substrate, is not a flattened surface. If the photoresist is placed on the insulation film, the photoresist may be bulged at the portion covering the temperature sensitive diode element, since the photoresist is formed along the one surface of the insulation film, which is opposite from the one surface of the semiconductor substrate.

If the photoresist is subjected to light exposure, the accuracy of the light exposure to the photoresist may be degraded. In cases of using a positive-type photoresist, for example, in performing light exposure to the photoresist, light from a light source is directed, through a photomask, to the portions of the photoresist which are on the regions where the first contact holes are to be formed, and to the portions of the photoresist which are on the regions where the second contact holes are to be formed. Light is directed to the un-bulged portion of the photoresist and light is directed to the bulged portion of the photoresist. For example, if the focal point is made coincident with the portions of the photoresist which are on the regions where the first contact holes are to be formed, the focal point may not be coincident with the portions of the photoresist which are on the regions where the second contact holes are to be formed. This may degrade the accuracy of the light exposure to the portions on the regions where the second contact holes are to be formed. Similarly, if the focal point is made coincident with the portions of the photoresist which are on the regions where the second contact holes are to be formed, the focal point may not be coincident with the portions of the photoresist which are on the regions where the first contact holes are to be formed. This may degrade the accuracy of the light exposure to the portions on the regions where the first contact holes are to be formed. Although the above description is given for describing a positive-type photoresist, the above description may also be applied to a negative-type photoresist.

If the accuracy of the light exposure to the photoresist is degraded, the accuracy of processing for the first and second contact holes may be degraded.

The diode element is placed in the semiconductor device through the insulation film. However, noises generated in the semiconductor substrate and the like may cause changes of the characteristics of the diode element, malfunctions of the diode element and the like. With such a semiconductor device, the accuracy of the detection with the diode element may be degraded. If the semiconductor device includes gate electrodes and is configured to control an electric current flowing through the semiconductor substrate by changing the gate voltage applied to the gate electrodes, the change of the gate voltage applied to the gate electrodes may tend to influence the diode element. This may degrade the accuracy of the detection with the diode element.

In one or more embodiments of the present disclosure, a semiconductor device may suppress degradation of the accuracy of processing for first and second contact holes, and a method for manufacturing the semiconductor may also suppress degradation of the accuracy of processing for first and second contact holes. Additionally, in one or more embodiments of the present disclosure, a semiconductor device may suppress degradation of the accuracy of detection with a diode element.

In a first aspect of the present disclosure, a semiconductor device includes: a semiconductor substrate having first surface; a semiconductor element formed on the first surface of the semiconductor substrate; an insulation film that is disposed on the first surface of the semiconductor substrate to cover the semiconductor element and the insulation film has a first contact hole for exposing a region in the first surface of the semiconductor substrate, and a second contact hole for exposing the semiconductor element; a first electrode electrically connected to a region in the first surface of the semiconductor substrate through the first contact hole; and a second electrode electrically connected to the semiconductor element through the second contact hole; in which the insulation film is flattened over the first surface opposite from the first surface of the semiconductor substrate and is configured such that an interval between the first surface and the first surface of the semiconductor substrate is equal along a planer direction of the semiconductor substrate.

The insulation film is flattened over the first surface. When a photoresist is placed on the insulation film, the photoresist is flattened over the first surface opposite from the insulation film. This may suppress the degradation of the accuracy of light exposure to the photoresist, which may suppress the degradation of the accuracy of processing for forming the first contact hole and the second contact hole using the photoresist as a mask.

In a second aspect of the present disclosure, a semiconductor device includes: a semiconductor substrate having first surface and having a semiconductor element formed thereon, the semiconductor element being configured to allow an electric current flowing through the semiconductor element; and a diode element formed on the first surface of the semiconductor substrate, in which on the first surface of the semiconductor substrate, a shield wiring portion maintained at a predetermined electric potential is formed, and the diode element is formed on the shield wiring portion.

The diode element is formed on the shield wiring portion which is maintained at a predetermined electric potential. This may suppress the degradation of the accuracy of the detection with the diode element due to noises in the semiconductor substrate, and the like.

In a third aspect of the present disclosure, a method for manufacturing a semiconductor device includes: preparing a semiconductor substrate having first surface; forming a semiconductor element on the first surface of the semiconductor substrate; forming an insulation film covering the semiconductor element on the first surface of the semiconductor substrate; forming a first contact hole for exposing a region in the first surface of the semiconductor substrate and further forming a second contact hole for exposing the semiconductor element; forming a first electrode electrically connected to a region in the first surface of the semiconductor substrate through the first contact hole; and forming a second electrode electrically connected to the semiconductor element through the second contact hole, in which a photoresist is placed on the insulation film and patterning the photoresist is patterned by light exposure and photographic processing, before the forming of the first contact hole and the second contact hole. The forming of the first contact hole and the second contact hole includes forming the first contact hole and the second contact hole at the same time, by using the photoresist as a mask and first surface of the insulation film that is opposite from the first surface of the semiconductor substrate is flattened before the placing of the photoresist.

Before the photoresist is placed, the insulation film is flattened at the first surface which is opposite from the first surface of the semiconductor substrate. When the photoresist is placed, the photoresist is flattened at the first surface which is opposite from the insulation film. This may suppress the degradation of the accuracy of light exposure to the photoresist, which may suppress the degradation of the accuracy of processing for forming the first contact hole and the second contact hole using the photoresist as a mask.

The following describes embodiments of the present disclosure with reference to the drawings. In the following respective embodiments, the same or equivalent parts are designated by the same reference signs.

First Embodiment

The following describes a first embodiment with reference to the drawings. In the present embodiment, a semiconductor device including a MOSFET element formed on a semiconductor substrate is described.

As illustrated inFIG. 1, the semiconductor device includes an N−-type semiconductor substrate10which functions as a drift layer11. On the drift layer11(in other words, on a first surface10aof the semiconductor substrate10), a P-type base layer12is formed. On the base layer12, an N+-type source layer13having a higher impurity concentration than that of the drift layer11is formed. In the present embodiment, on the drift layer11, the base layer12and the source layer13in the mentioned order from the side closer to the drift layer11are formed. In the present embodiment, since the source layer13is formed as described above, the semiconductor substrate10includes the source layer13on the first surface10a. In the present embodiment, the source layer13corresponds to a first-conduction-type layer.

In the semiconductor substrate10, multiple trenches14, each of which penetrates through the source layer13and the base layer12to reach the drift layer11, are formed. The base layer12is divided by the multiple trenches14. In the present embodiment, the multiple trenches14are formed at even intervals in a stripe shape, along a predetermined direction out of planer directions of the first surface10aof the semiconductor substrate10. InFIG. 1, the multiple trenches14are each formed along a depthwise direction, as viewed from the drawing ofFIG. 1. In the present embodiment, the regions of the base layer12, which come in contact with the trenches14, correspond to channel regions.

In each of the trenches14, a gate insulation film15formed to cover the wall surfaces of each trench14, and a gate electrode16formed on the gate insulation film15are embedded. Thus, a trench gate configuration is formed. The gate electrodes16are electrically connected to a gate wiring, which is not illustrated, in a cross section different from that ofFIG. 1, in which the gate wiring is formed on the first surface10aof the semiconductor substrate10. The gate electrodes16are configured such that a predetermined gate voltage from a gate control circuit (not illustrated) is applied to the gate electrodes16. In the present embodiment, the gate insulation films15are formed by an oxide film or the like, and the gate electrodes16are formed by a polysilicon (which is referred to as a “Poly-Si”).

On the first surface10aof the semiconductor substrate10, a one-surface insulation film17, which is formed by an oxide film or the like to cover the gate electrodes16, is formed. In the present embodiment, on the one-surface insulation film17, a temperature sensitive diode element18is formed. The temperature sensitive diode element18outputs a detection signal corresponding to heat generated from the operation of the MOSFET element. The temperature sensitive diode element18includes an anode region18aformed by a P-type Poly-Si, and a cathode region18bformed by an N-type Poly-Si. The anode region18aand the cathode region18bare connected to each other. An element protective film19, which is formed by an oxide film or the like, is formed to cover the temperature sensitive diode element18. In the present embodiment, the temperature sensitive diode element18corresponds to a semiconductor element.

On the one-surface insulation film17, an inter-layer insulation film20, which is formed by an oxide film or the like, is formed to cover the element protective film19(namely the temperature sensitive diode element18). The inter-layer insulation film20is flattened over the first surface20a,which is opposite from the first surface10aof the semiconductor substrate10. More specifically, the first surface20aof the inter-layer insulation film20is flattened, such that the interval between the first surface20aof the inter-layer insulation film20and the first surface10aof the semiconductor substrate10is equal along a planer direction of the semiconductor substrate10. In other words, regarding the interval between the first surface20aand the first surface10aof the semiconductor substrate10, the inter-layer insulation film20is configured such that the interval in the portion covering the temperature sensitive diode element18is equal to the interval in the portion other than the portion covering the temperature sensitive diode element18.

In the inter-layer insulation film20, first contact holes21and second contact holes22are formed. The first contact holes21expose the source layer13and the base layer12, and the second contact holes22expose the temperature sensitive diode element18. More specifically, the multiple first contact holes21are formed to penetrate through the source layer13to reach the base layer12, between the respective trenches14adjacent to each other. Thus, the source layer13is exposed from the side surfaces of the first contact holes21, and the base layer12is exposed from the side surfaces and the bottom surfaces of the first contact holes21. In addition, two second contact holes22are formed in which one of the holes is formed to expose the anode region18a,while the other one is formed to expose the cathode region18b.

On the inter-layer insulation film20, a first upper-portion electrode23, which is electrically connected to the source layer13and the base layer12through the first contact holes21, is formed. In addition, a second upper-portion electrode24, which is electrically connected to the temperature sensitive diode element18through the second contact holes22, is formed. In the present embodiment, the first upper-portion electrode23corresponds to a first electrode, and the second upper-portion electrode24corresponds to a second electrode.

In the present embodiment, the first upper-portion electrode23includes a first embedded electrode portion23awhich is embedded in the first contact holes21, and a first upper-layer electrode portion23bwhich is placed on the inter-layer insulation film20and is electrically connected to the first embedded electrode portion23a.Similarly, the second upper-portion electrode24includes a second embedded electrode portion24awhich is embedded in the second contact holes22, and a second upper-layer electrode portion24bwhich is placed on the inter-layer insulation film20and is electrically connected to the second embedded electrode portion24a.In the present embodiment, the first and second embedded electrode portions23aand24aare formed by W (namely, tungsten). In other words, the first and second embedded electrode portions23aand24aare formed to be so-called W plugs. The first and second upper-layer electrode portions23band24bare formed by Al (namely, aluminum) and the like.

On the side of the drift layer11which is opposite from the base layer12(namely, on the other surface10bof the semiconductor substrate10), an N-type drain layer25is formed. The N-type drain layer25has a higher impurity concentration than that of the drift layer11. On the opposite side from the drift layer11across the drain layer25, a lower-portion electrode26is formed. In other words, on the other surface10bof the semiconductor substrate10, the lower-portion electrode26, which is electrically connected to the drain layer25, is formed.

The semiconductor device according to the present embodiment has the structure. In the present embodiment, N+type, N type and N−type correspond to a first conduction type. P type and P+type correspond to a second conduction type. The semiconductor substrate10according to the present embodiment includes the drain layer25, the drift layer11, the base layer12and the source layer13.

The following describes processes for manufacturing the aforementioned semiconductor device with reference to the drawings. The processes for manufacturing the other surface10bside (namely, the drain layer25side) of the semiconductor substrate10are not described in detail herein.

As illustrated inFIG. 2A, a semiconductor substrate10is prepared. Further, a mask is properly formed on first surface10aof the semiconductor substrate10. Multiple trenches14are formed in the semiconductor substrate10through dry etching or the like. Further, thermal oxidation or the like is performed to form gate insulation films15on the wall surfaces of the trenches14and to form a lower-side insulation film17aforming a portion of an one-surface insulation film17on the first surface10aof the semiconductor substrate10.

As illustrated inFIG. 2B, a Poly-Si is deposited in such a way as to be embedded in the trenches14, through a CVD (namely, Chemical Vapor Deposition) method or the like, and therefore gate electrodes16are formed. Further, in a cross section different from that ofFIG. 2B, the Poly-Si deposited on the first surface10aof the semiconductor substrate10is properly patterned to form a gate wiring which is electrically connected to the gate electrodes16. Thereafter, thermal oxidation or the like is performed again, and therefore the one-surface insulation film17covering the gate electrodes16from the lower-side insulation film17ais formed.

As illustrated inFIG. 2C, a Poly-Si is deposited on the one-surface insulation film17through a CVD method or the like and, thereafter, the Poly-Si is subjected to photoetching and the like, and therefore the outer shape of a temperature sensitive diode element18is formed. Further, a mask (not illustrated) is properly placed, and a P-type impurity and an N-type impurity are properly injected into the remaining Poly-Si through ion injection and are thermally diffused. This forms the temperature sensitive diode element18including an anode region18aformed by a P-type Poly-Si, and a cathode region18bformed by an N-type Poly-Si.

A P-type impurity and an N-type impurity are properly injected into the first surface10aof the semiconductor substrate10and are thermally diffused, and therefore a base layer12and a source layer13are formed. Thereafter, thermal diffusion or the like is performed thereon, and therefore an element protective film19for protecting the temperature sensitive diode element18is formed.

In the present embodiment, the ion injection of impurities into the semiconductor substrate10is performed, after the deposition of the Poly-Si, which forms the temperature sensitive diode element18. Therefore, the base layer12and the source layer13are not formed under the temperature sensitive diode element18. However, the base layer12and the source layer13may be also formed over the entirety, thereafter, a Poly-Si, which forms the temperature sensitive diode element18, may be deposited, and impurities may be injected into the Poly-Si, again, through ion injection or the like. Namely, the base layer12and the source layer13may be also formed under the temperature sensitive diode element18. Thus, the region under the temperature sensitive diode element18may be effectively utilized, since the base layer12and the source layer13may be formed under the temperature sensitive diode element18.

As illustrated inFIG. 2D, an inter-layer insulation film20is formed on the one-surface insulation film17, through a CVD method or the like, in such a way as to cover the element protective film19(namely, the temperature sensitive diode element18). Immediately after the formation of the inter-layer insulation film20, the inter-layer insulation film20is in a state of having a level difference formed between the portion covering the temperature sensitive diode element18and the portion which does not cover the temperature sensitive diode element18. In other words, the inter-layer insulation film20is in a state of having a level difference formed in the first surface20a.The inter-layer insulation film20is in a state of being bulged at the portion covering the temperature sensitive diode element18. In this process, the inter-layer insulation film20is formed such that the height of the first surface20ain the portion other than the portion covering the temperature sensitive diode element18is higher than the height of the surface of the temperature sensitive diode element18from the first surface10aof the semiconductor substrate10. The surface of the temperature sensitive diode element18refers to the face of the temperature sensitive diode element18which is opposite from the first surface10aof the semiconductor substrate10.

As illustrated inFIG. 2E, the first surface20aof the inter-layer insulation film20is flattened through a CMP (Chemical Mechanical Polishing) method or the like. More specifically, regarding the interval between the first surface20aof the inter-layer insulation film20and the first surface10aof the semiconductor substrate10, the interval in the portion covering the temperature sensitive diode element18is equal to the interval in the portion other than the portion covering the temperature sensitive diode element18.

As illustrated inFIG. 2F, a photoresist27is placed on the inter-layer insulation film20. At this time, the first surface20aof the inter-layer insulation film20has been flattened. Therefore, the photoresist27may be also placed as to be flattened. In the present embodiment, a positive-type photoresist27is placed on the inter-layer insulation film20.

As illustrated inFIG. 2G, the photoresist27is patterned by light exposure and photographic processing to expose the regions of the inter-layer insulation film20where first contact holes21and second contact holes22are to be formed.

At the time of applying light exposure to the photoresist27, a photomask (not illustrated) is placed on the photoresist27. Then, light from a light source, after passing through the photomask, is directed to the portions of the photoresist27which are positioned on the regions where the first contact holes21are to be formed, and is directed to the portions of the photoresist27which are positioned on the regions where the second contact holes22are to be formed. At this time, the photoresist27is placed as to be flattened in the present embodiment. Therefore, the distance from the light source to the portions of the photoresist27, which are positioned on the regions where the first contact holes21are to be formed, may be substantially equal to the distance from the light source to the portions of the photoresist27, which are positioned on the regions where the second contact holes22are to be formed. This may suppress focal point deviation between light directed to the first portion of the photoresist27and light directed to the second portion of the photoresist27. The first portion of the photoresist27is positioned on the regions where the first contact holes21are to be formed. The second portion of the photoresist27is positioned on the regions where the second contact holes22are to be formed. This may suppress the degradation of the accuracy of light exposure to the photoresist27, and therefore may suppress the degradation of the accuracy of the processing of the photoresist27.

As illustrated inFIG. 2H, dry etching or the like is performed using the photoresist27as a mask, and therefore the first contact holes21and the second contact holes22are formed at the same time. At this time, the degradation of the accuracy of the processing for the first contact holes21and the second contact holes22may be suppressed since the degradation of the accuracy of the processing of the photoresist27has been suppressed. In other words, the first contact holes21and the second contact holes22may be formed with higher accuracy.

As illustrated inFIG. 2I, the photoresist27is removed. The first upper-portion electrode23is formed. A second upper-portion electrode24is formed. The first upper-portion electrode23is electrically connected to the base layer12and the source layer13, and the second upper-portion electrode24is electrically connected to the temperature sensitive diode element18. In the present embodiment, at first, tungsten (W) is embedded in the first contact holes21and the second contact holes22through a CVD method or the like to form first and second embedded electrode portions23aand24a.Next, the tungsten film (W film) deposited on the first surface20aof the inter-layer insulation film20is removed. Thereafter, a metal film formed by aluminum (Al) and the like is formed on the inter-layer insulation film20, through a CVD method or the like. Further, the metal film formed thereon is patterned to form the first upper-layer electrode portion23band the second upper-layer electrode portion24b.The first upper-layer electrode portion23bis electrically connected to the first embedded electrode portion23a.The second embedded electrode portion24ais electrically connected to the second embedded electrode portion24a.A semiconductor device according to the present embodiment is manufactured as described above.

In the present embodiment, the first surface20aof the inter-layer insulation film20is flattened, after the formation of the inter-layer insulation film20. Further, the photoresist27is placed on the first surface20aof the inter-layer insulation film20which has been flattened. Therefore, the photoresist27is placed as to be flattened. Further, the distance from the light source to the portions of the photoresist27, which are positioned on the regions where the first contact holes21are to be formed, may be substantially equal to the distance from the light source to the portions of the photoresist27, which are positioned on the regions where the second contact holes22are to be formed. This may suppress focal point deviation between light directed to the first portion of the photoresist27and light directed to the second portion of the photoresist27. This may suppress the degradation of the accuracy of light exposure. The first portion of the photoresist27is positioned on the regions where the first contact holes21are to be formed. The second portion of the photoresist27is positioned on the regions where the second contact holes22are to be formed.

Since the first contact holes21and the second contact holes22are formed using the photoresist27as a mask, the degradation of the accuracy of the processing for the first contact holes21and the second contact holes22may be suppressed.

In the present embodiment, the inter-layer insulation film20is configured such that the interval between the first surface10aof the semiconductor substrate10and the first surface20ain the portion other than the portion covering the temperature sensitive diode element18is equal to the interval between the first surface10aof the semiconductor substrate10and the first surface20ain the portion covering the temperature sensitive diode element18. Even though the inter-layer insulation film20is formed to cover the temperature sensitive diode element18, for example, the inter-layer insulation film20has a greater thickness, in comparison with cases where the interval between the first surface10aof the semiconductor substrate10and the first surface20ain the portion other than the portion covering the temperature sensitive diode element18is made shorter than the interval between the first surface10aof the semiconductor substrate10and the first surface20ain the portion covering the temperature sensitive diode element18. Therefore, the inter-layer insulation film20placed between the gate electrodes16and the first upper-portion electrode23has a greater thickness, which may reduce parasitic capacitances. According to the present embodiment, noises generated by variations of the gate electric potential at the gate electrodes16may be easily absorbed by the inter-layer insulation film20, which may suppress malfunctions of the semiconductor device and peripheral circuits placed near the semiconductor device.

Second Embodiment

The following describes a second embodiment. In the present embodiment, the structure of the gate electrodes16is changed from that of the first embodiment, and the other structures are the same as those of the first embodiment and are not be described herein.

In the present embodiment, as illustrated inFIG. 3, a semiconductor device includes a cell region1where a MOSFET element is formed, and a peripheral region2different from the cell region1. In this case, the peripheral region2is a different region from the cell region1and includes an outer edge region placed in such a way as to surround the cell region1, and an intermediate region placed between adjacent cell regions1. Namely, in the present embodiment, the peripheral region2is a region which may be positioned near the center of the semiconductor device, for example.

At first, the structure of the cell region1will be described. In the present embodiment, the cell region1has a trench gate configuration, which is a so-called split-gate configuration. More specifically, in each trench14, a first gate insulation film15a,a second gate insulation film15b,a first gate electrode16aand a second gate electrode16bare placed. Within each trench14, the first gate insulation film15aand the first gate electrode16aare placed in the opening portion side of the trench14, and therefore an upper-stage side gate configuration is formed. The second gate insulation film15band the second gate electrode16bare placed in the bottom portion side of the trench14, and therefore a lower-stage side gate configuration is formed.

Each first gate electrode16ais electrically connected to a gate wiring which is not illustrated, in a different cross section from that ofFIG. 3. Thus, each first gate electrode16ais adapted such that a predetermined gate voltage from a gate control circuit is applied thereto. Further, the respective second gate electrodes16bare electrically connected to each other in a different cross section from that ofFIG. 3and are maintained at a predetermined electric potential. In the present embodiment, the second gate electrodes16bare electrically connected to a first upper-portion electrode23and are maintained at the electric potential at the first upper-portion electrode23, as will be described later.

The first gate electrodes16aare formed up to a position deeper than the bottom portion of a base layer12from first surface10aof the semiconductor substrate10. Namely, the first gate electrodes16aare placed in such a way as to form channels, which connect a source layer13and a drift layer11to each other in the base layer12, when the gate voltage is applied to the first gate electrodes16a.The first gate insulation films15aare formed along the first gate electrodes16aand are formed up to a position deeper than the bottom portion of the base layer12from the first surface10aof the semiconductor substrate10.

The second gate electrodes16bare formed by the bottom portion of the upper-stage side gate configuration toward the bottom portions of the trenches14. The second gate insulation films15bare placed along the second gate electrodes16band are placed in the bottom portion sides of the trenches14. The second gate insulation films15bhave a greater thickness than that of the first gate insulation films15a.The first gate insulation films15aare placed between the first gate electrodes16aand the second gate electrodes16b.

In the present embodiment, since the split-gate configuration is formed, occurrences of electric field concentrations at the bottom portions of the trenches14may be suppressed, and therefore the withstand voltage may be improved.

The structure of the peripheral region2is described. In the peripheral region2, trenches14are formed, similarly to in the cell region1. In each trench14, a shield insulation film28formed as to cover the wall surfaces of each trench14, and a shield electrode29formed on the shield insulation film28are embedded. The shield insulation films28and the shield electrodes29, which are formed in the peripheral region2, are similar to the second gate insulation films15band the second gate electrodes16b,which are formed in the cell region1. The shield electrodes29formed in the peripheral region2are electrically connected to the second gate electrodes16bformed in the cell region1, in a different cross section from that ofFIG. 3.

On the first surface10aof the semiconductor substrate10, around the opening portions of the trenches14, a lower-layer insulation film30, which is connected to the shield insulation films28, is formed. On the lower-layer insulation film30, a shield wiring portion31as a lead wiring portion, which is electrically connected to the shield electrodes29, is formed. The shield wiring portion31is electrically connected to the first upper-portion electrode23through a contact hole formed in the inter-layer insulation film20, in a different cross section from that ofFIG. 3. Thus, the shield electrodes29are maintained at the same electric potential as that at the first upper-portion electrode23, through the shield wiring portion31. The second gate electrodes16bformed in the cell region1are electrically connected to the shield electrodes29formed in the peripheral region2and, therefore, are maintained at the electric potential at the first upper-portion electrode23.

A wiring insulation film32is formed as to cover the shield wiring portion31. A temperature sensitive diode element18is formed on the shield wiring portion31through the wiring insulation film32. An element protective film19is formed as to cover the temperature sensitive diode element18. In the present embodiment, the temperature sensitive diode element18is placed in the peripheral region2. The temperature sensitive diode element18is electrically connected to a second upper-portion electrode24, through second contact holes22formed in the inter-layer insulation film20, similarly to in the first embodiment.

The semiconductor device according to the present embodiment has the aforementioned structure. A method for manufacturing the aforementioned semiconductor device is described.

As illustrated inFIG. 4A, trenches14are formed in a semiconductor substrate10and, thereafter, second gate insulation films15band shield insulation films28are formed through thermal oxidation or the like. In this process, an insulation film is also formed on first surface10aof the semiconductor substrate10, and the insulation film forms a lower-layer insulation film30in a peripheral region2.

As illustrated inFIG. 4B, a Poly-Si is deposited through a CVD method or the like, as to be embedded in the trenches14. Further, second gate electrodes16bare formed in the trenches14in a cell region1, and shield electrodes29are formed in the trenches14in a peripheral region2. Subsequently, a mask is properly formed and dry etching or the like is performed to pattern the Poly-Si formed on the first surface10aof the semiconductor substrate10to form a shield wiring portion31, in the peripheral region2. Further, in the cell region1, the Poly-Si placed on the first surface10aof the semiconductor substrate10is removed, and the Poly-Si placed in the portions of the trenches14where first gate electrodes16aare to be placed is removed.

As illustrated inFIG. 4C, a mask (not illustrated) is placed, and the insulation film formed on the first surface10aof the semiconductor substrate10and in the portions of the trenches14where first gate insulation films15aare to be formed is removed, in the cell region1. Further, in the peripheral region2, the insulation film formed on the first surface10aof the semiconductor substrate10is removed, such that the lower-layer insulation film30is left under the shield wiring portion31.

As illustrated inFIG. 4D, thermal oxidation or the like is performed, and therefore the first gate insulation films15ais formed in the trenches14and a lower-layer insulation film17aforming an one-surface insulation film17is formed on the first surface10aof the semiconductor substrate10, in the cell region1. In the peripheral region2, the lower-side insulation film17aforming the one-surface insulation film17is formed on the first surface10aof the semiconductor substrate10and, further, a wiring insulation film32covering the shield wiring portion31is formed.

As illustrated inFIG. 4E, a Poly-Si is deposited through a CVD method or the like as to be embedded in the trenches14, and therefore the first gate electrodes16ais formed. Further, a mask is properly formed and dry etching or the like is performed to properly pattern the Poly-Si formed on the first surface10aof the semiconductor substrate10, and therefore a gate wiring (not illustrated) is formed.

As illustrated inFIG. 4F, the same process as that ofFIG. 2Cis performed, and therefore a temperature sensitive diode element18, a base layer12and a source layer13are formed. In the present embodiment, the temperature sensitive diode element18is formed on the shield wiring portion31. Thereafter, thermal oxidation or the like is performed to form an element protective film19for protecting the temperature sensitive diode element18and, further, to form the one-surface insulation film17covering the first gate electrodes16a.

As illustrated inFIGS. 4G to 4L, the same processes as those ofFIGS. 2D to 2Iare performed. As illustrated inFIG. 4G, an inter-layer insulation film20is formed on the one-surface insulation film17, as to cover the element protective film19(namely, the temperature sensitive diode element18). As illustrated inFIG. 4H, first surface20aof the inter-layer insulation film20which is opposite from the first surface10aof the semiconductor substrate10is flattened through a CMP method or the like. As illustrated inFIG. 4I, a photoresist27is placed on the inter-layer insulation film20.

As illustrated inFIG. 4J, the photoresist27is patterned by light exposure and photographic processing, as to expose the regions of the inter-layer insulation film20where first contact holes21and second contact holes22are to be formed. As illustrated inFIG. 4K, dry etching or the like is performed using the photoresist27as a mask, and therefore the first contact holes21and the second contact holes22are formed at the same time. As illustrated inFIG. 4L, a first upper-portion electrode portion23electrically connected to the base layer12and the source layer13is formed A second upper-portion electrode portion24electrically connected to the temperature sensitive diode element18is formed. A semiconductor device according to the present embodiment is manufactured as described above.

In the present embodiment, the temperature sensitive diode element18is placed in the peripheral region2. The temperature sensitive diode element18is placed on the shield wiring portion31, which is maintained at a predetermined electric potential. This may provide the same effects as those of the first embodiment, while suppressing malfunctions of the temperature sensitive diode element18due to variations of the gate electric potential at the first gate electrodes16a.

Third Embodiment

The following describes a third embodiment. In the present embodiment, the gate configuration according to the second embodiment is combined with the first embodiment, and the other structures are the same as those of the first embodiment and are not be described herein.

In the present embodiment, as illustrated inFIG. 5, a trench gate configuration, which is formed to be a split-gate configuration, is provided, similarly to the second embodiment. Within each trench14, a first gate insulation film15aand a first gate electrode16aare placed in the opening portion side of the trench14,and therefore an upper-stage side gate configuration is formed. A second gate insulation film15band a second gate electrode16bare placed in the bottom portion side of the trench14, and therefore a lower-stage side gate configuration is formed. A temperature sensitive diode element18is placed on the split-gate configuration.

The temperature sensitive diode element18may be placed on the split-gate configuration. With the semiconductor device according to the present embodiment, the same effects as those of the first embodiment may be provided when a first surface20aof an inter-layer insulation film20is flattened.

The semiconductor device according to the present embodiment may be fabricated by properly combining the manufacturing methods described in the first and second embodiments.

Fourth Embodiment

The following describes a fourth embodiment. In the present embodiment, a peripheral region is provided in the first embodiment, and the other structures are the same as those of the first embodiment and are not be described herein.

In the present embodiment, as illustrated inFIG. 6, a cell region1and a peripheral region2are provided and a temperature sensitive diode element18is placed in the cell region1. A one-surface insulation film17positioned under the temperature sensitive diode element18has a greater thickness than that of the first embodiment. More specifically, the one-surface insulation film17is provided with an enough thickness to suppress malfunctions of the temperature sensitive diode element18due to variations of the gate voltage applied to gate electrodes16, noises from a semiconductor substrate10and the like. For example, the one-surface insulation film17has a thickness of 300 nm. In other words, the one-surface insulation film17is provided with a thickness that keeps the characteristics of the temperature sensitive diode element unchanged due to variations of the gate voltage applied to gate electrodes16, noises from the semiconductor substrate10, and the like.

In the present embodiment, the gate electrodes16are formed as to partially protrude from a first surface10aof the semiconductor substrate10. For example, the gate electrodes16protrude from the first surface10aby about 200 nm. The one-surface insulation film17is formed to have a greater thickness than the amount of the protrusion of the gate electrodes16. The one-surface insulation film17is formed as to cover the portions of the gate electrodes16, which protrude from the first surface10aof the semiconductor substrate10. In this case, the thickness of the one-surface insulation film17refers to the interval between the first surface10aof the semiconductor substrate10and the surface of the one-surface insulation film17which is opposite from the semiconductor substrate10.

The peripheral region2is formed to have a multiple-ring configuration including multiple P-type guard rings33, which have a higher impurity concentration than that of a base layer12, in the first surface10aof the semiconductor substrate10. The one-surface insulation film17and an inter-layer insulation film20are also formed in the peripheral region2.

In the one-surface insulation film17and the inter-layer insulation film20formed in the peripheral region2, third contact holes34, which expose the guard rings33, are formed. On the inter-layer insulation film20, a third upper-portion electrode35is formed. The third upper-portion electrode35is electrically connected to the guard rings33through the third contact holes34. The third upper-portion electrode35has the same structure as those of the first upper-portion electrode23and the second upper-portion electrode24, and includes a third embedded electrode portion35aand a third upper-layer electrode portion35b.

In the present embodiment, the one-surface insulation film17in the cell region1is provided with a greater thickness in order to suppress malfunctions of the temperature sensitive diode element18. The one-surface insulation film17in the peripheral region2is provided with the same thickness as that of the one-surface insulation film17in the cell region1. In the present embodiment, the one-surface insulation film17is formed to have a greater thickness over the entirety, rather than only under the temperature sensitive diode element18. The one-surface insulation film17is flattened over the one surface in the opposite side from the semiconductor substrate10.

The one-surface insulation film17may have a greater thickness, in order to suppress malfunctions of the temperature sensitive diode element18due to variations of the gate voltage applied to gate electrodes16. The one-surface insulation film17is flattened over the entirety of the cell region1and the peripheral region2. At the time of formation of the temperature sensitive diode element18in the process inFIG. 2C, the formation of a level difference in the Poly-Si when the Poly-Si has been deposited is suppressed. This may suppress the degradation of the accuracy of processing for performing photo etching on the Poly-Si, which enables forming the temperature sensitive diode element18with higher accuracy.

Similar to the first embodiment, the first surface20aof the inter-layer insulation film20is flattened. This may suppress the degradation of the accuracy of processing for the third contact holes34.

Fifth Embodiment

The following describes a fifth embodiment. In the present embodiment, the second and fourth embodiments are combined, and the other structures are the same as those of the first embodiment and are not be described herein.

In the present embodiment, as illustrated inFIG. 7, trenches14are also formed in a peripheral region2. A shield insulation film28and a shield electrode29are embedded in each trench14. The shield electrodes29are formed as to partially protrude from first surface10aof a semiconductor substrate10, similarly to gate electrodes16. For example, the shield electrodes29protrude from the first surface10aby about 200 nm. In the present embodiment, no shield wiring portion31is formed in the peripheral region2. Although not illustrated in particular, in a different cross section from that ofFIG. 7, the shield electrodes29are connected to a lead wiring portion formed on the first surface10aof the semiconductor substrate10, and this lead wiring portion is connected to a first upper-portion electrode23and, thus, is maintained at the electric potential at the first upper-portion electrode23.

An one-surface insulation film17is formed as to cover the shield electrodes29and the portions of the gate electrodes16which protrude from the first surface10aof the semiconductor substrate10. Similar to the fourth embodiment, the one-surface insulation film17has a thickness of 300 nm in the present embodiment. A temperature sensitive diode element18is placed on the shield electrodes29through the one-surface insulation film17. The cell region1has the same structure as that of the fourth embodiment.

Even when the temperature sensitive diode element18is placed on the shield electrodes29through the one-surface insulation film17, malfunctions of the temperature sensitive diode element may be suppressed since the one-surface insulation film17has a greater thickness.

Sixth Embodiment

The following describes a sixth embodiment. In the present embodiment, the structure of a cell region1is changed from that in the second embodiment, and the other structures are the same as those of the first embodiment and are not be described herein.

In the present embodiment, as illustrated inFIG. 8, trenches formed in a cell region1are referred to as first trenches14a,while trenches formed in a peripheral region2are referred to as second trenches14b.In the present embodiment, the second trenches14bcorrespond to shield trenches.

The cell region1has a trench gate configuration having the same structure as that of the first embodiment. In each first trench14a,a gate insulation film15formed as to cover the wall surfaces of the first trench14a,and a gate electrode16formed on the gate insulation film15are embedded.

As similar to the second embodiment, in the peripheral region2, a shield insulation film28and a shield electrode29are embedded in each second trench14b.The shield insulation film28is formed as to cover the wall surfaces of the second trench14b,and the shield electrode29is formed on the shield insulation film28. In the present embodiment, the shield electrodes29are electrically connected to a first upper-portion electrode23and are at the same electric potential as that at the first upper-portion electrode23.

The shield insulation films28according to the present embodiment are formed to have a greater thickness than that of the gate insulation films15, since the shield electrodes29are maintained at a predetermined electric potential, in order to improve the withstand voltage. In other words, the gate insulation films15are provided with a smaller thickness than that of the shield insulation film28, such that an inversion layer is formed in a base layer12, when a predetermined gate voltage is applied to the gate electrodes16.

Similar to the second embodiment, in the peripheral region2, a shield wiring portion31, which is electrically connected to the shield electrodes29, is formed on a lower-layer insulation film30. The shield wiring portion31is electrically connected to the first upper-portion electrode23, in a different cross section from that ofFIG. 8. The shield electrodes29are maintained at the same electric potential as that at the first upper-portion electrode23, through the shield wiring portion31. On the surface and the side surfaces of the shield wiring portion31, a wiring insulation film32formed by an oxide film or the like is formed as to cover the shield wiring portion31.

The semiconductor device according to the present embodiment has the aforementioned structure. The following describes processes for manufacturing the aforementioned semiconductor device with reference to the drawings.

As illustrated inFIG. 9A, a semiconductor substrate10provided with first trenches14aand second trenches14bis prepared. Further, thermal oxidation or the like is performed to form shield insulation films28in the second trenches14band to form a lower-layer insulation film30around the opening portions of the second trenches14b.In this process, an insulation film is also formed in the first trenches14a,and on first surface10aof the semiconductor substrate10at the other portions than the peripheries of the opening portions of the second trenches14b.

As illustrated inFIG. 9B, a Poly-Si is deposited as to be embedded in the second trenches14b,through a CVD method or the like. This results in formation of shield electrodes29in the second trenches14bthrough the shield insulation films28in a peripheral region2. A mask (not illustrated) is properly formed, and dry etching or the like is performed to pattern the Poly-Si formed on the first surface10aof the semiconductor substrate10, and therefore a shield wiring portion31is formed in the peripheral region2. In a cell region1, the Poly-Si placed on the first surface10aof the semiconductor substrate10, and the Poly-Si placed in the first trenches14aare removed.

As illustrated inFIG. 9C, a mask (not illustrated) is placed, and the insulation film formed in the process inFIG. 9Ais removed, in the cell region1. In the peripheral region2, the insulation film formed on the first surface10aof the semiconductor substrate10is removed, such that the lower-layer insulation film30placed under the shield wiring portion31is remained.

As illustrated inFIG. 9D, thermal oxidation or the like is performed. In the cell region1, gate insulation films15are formed in the first trenches14a,and a lower-side insulation film17aforming a lower-layer side portion of an one-surface insulation film17is formed on the first surface10aof the semiconductor substrate10. In the peripheral region2, the lower-side insulation film17aforming the lower-layer side portion of the one-surface insulation film17is formed on the first surface10aof the semiconductor substrate10, and a wiring insulation film32covering the shield wiring portion31is formed on the first surface10a.

As illustrated inFIG. 9E, a Poly-Si is deposited through a CVD method or the like as to be embedded in the respective first trenches14a,and therefore gate electrodes16are formed in the cell region1. A mask is properly formed, and dry etching or the like is performed to properly pattern the Poly-Si formed on the first surface10aof the semiconductor substrate10, and therefore a gate wiring (not illustrated) is formed. The Poly-Si formed in the peripheral region2is removed.

As illustrated inFIG. 9F, a Poly-Si is deposited on the shield wiring portion31through a CVD method or the like and, thereafter, photoetching and the like are performed on the Poly-Si, and therefore the outer shape of a temperature sensitive diode element18is formed. A mask (not illustrated) is properly placed, and a P-type impurity and an N-type impurity are properly injected into the remaining Poly-Si through ion injection and are thermally diffused. This forms the temperature sensitive diode element18including an anode region18aformed by a P-type Poly-Si, and a cathode region18bformed by an N-type Poly-Si.

A P-type impurity and an N-type impurity are properly injected into the first surface10aof the semiconductor substrate10and are thermally diffused, and therefore a base layer12and a source layer13are formed. In the present embodiment, the ion injection of impurities is performed after the formation of the shield wiring portion31and the like. The base layer12and the source layer13are not formed under the shield wiring portion31. Thereafter, thermal diffusion or the like is performed thereon, and therefore an element protective film19for protecting the temperature sensitive diode element18is formed, and the one-surface insulation film17from the lower-side insulation film17ais formed.

As illustrated inFIGS. 9G to 9L, the same processes as those ofFIGS. 2D to 2Iare performed. As illustrated inFIG. 9G, an inter-layer insulation film20is formed on the one-surface insulation film17, as to cover the element protective film19(namely, the temperature sensitive diode element18). As illustrated inFIG. 9H, first surface20aof the inter-layer insulation film20which is opposite from the first surface10aof the semiconductor substrate10is flattened through a CMP method or the like. As illustrated inFIG. 9I, a photoresist27is placed on the inter-layer insulation film20.

As illustrated inFIG. 9J, the photoresist27is patterned by light exposure and photographic processing, as to expose the regions of the inter-layer insulation film20where first contact holes21and second contact holes22are to be formed. As illustrated inFIG. 9K, dry etching or the like is performed using the photoresist27as a mask, and therefore the first contact holes21and the second contact holes22are formed at the same time. As illustrated inFIG. 9L, a first upper-portion electrode portion23electrically connected to the base layer12and the source layer13is formed, and a second upper-portion electrode portion24electrically connected to the temperature sensitive diode element18is formed. A semiconductor device according to the present embodiment is manufactured as described above.

In the present embodiment, the temperature sensitive diode element18is formed on the shield wiring portion31, and the shield wiring portion31is electrically connected to the first upper-portion electrode23and is maintained at a predetermined electric potential. This may suppress the degradation of the accuracy of the detection with the temperature sensitive diode element18due to noises in the semiconductor substrate10and the like. More specifically, the degradation of the accuracy of the detection with the temperature sensitive diode element18due to noises caused by changes of the gate voltage applied to the gate electrodes16may be suppressed, for example.

In the present embodiment, the second trenches14bare formed in the peripheral region2, and the shield electrodes29electrically connected to the shield wiring portion31is placed within these second trenches14b.This may improve the withstand voltage in the peripheral region2.

In the present embodiment, the peripheral region2is a region, which may be positioned near the center of the semiconductor device. Therefore, the semiconductor device may be configured such that the peripheral region2is near the center of the semiconductor device, and the temperature sensitive diode element18may be placed in the peripheral region2in order to improve the temperature detection sensitivity.

Other Embodiments

The present disclosure has been described regarding to the embodiments, but it should be understood that the present disclosure may not be limited to these embodiments and configurations. The present disclosure also encompasses various modified examples and changes falling within equivalent ranges. In addition, various combinations and aspects, and other combinations and aspects further including only one element or more or less than in addition thereto are also encompassed within the scope and spirit of the present disclosure.

For example, although, in the respective embodiments, cases where the first conduction type is N type and the second conduction type is P type have been described, semiconductor devices such that the first conduction type is P type and the second conduction type is N type also may be provided. The conduction types of the respective portions having been described in the respective embodiments may be reversed.

In the respective embodiments, the semiconductor element formed on the semiconductor substrate10may be also a Zener diode element, for example, rather than a temperature sensitive diode element18.

In the respective embodiments, a P-type collector layer may be also provided, instead of the drain layer25. An IGBT (namely, Insulated Gate Bipolar Transistor) element may be formed on the semiconductor substrate10. In addition, a semiconductor device having a super-junction configuration including an N-type column region and a P-type column region which are placed on a drain layer25may be provided.

In the respective embodiments, a lateral-type semiconductor device, which includes a drain layer25formed on the surface-layer portion of the drift layer11and is configured to flow an electric current in a planer direction of the semiconductor substrate10, may be provided.

In the respective embodiments, a planer-type gate configuration instead of a trench-type gate configuration may be employed. For example, the same effects may be provided, by flattening the first surface20aof the inter-layer insulation film20in the first embodiment. With this structure, the degradation of the accuracy of processing for the first contact holes21and the second contact holes22due to the gate configuration formed on the first surface10aof the semiconductor substrate10may be suppressed. In the sixth embodiment, even with such a planer-type gate configuration, the degradation of the accuracy of the detection with the temperature sensitive diode element18may be suppressed by placing the temperature sensitive diode element18on the shield wiring portion31.

In the respective embodiments, barrier metals, which are formed by Ti, TiN or the like, may also be formed on the wall surfaces of the first contact holes21and the second contact holes22. Such barrier metals are formed through sputtering or the like, before the formation of the first and second embedded electrode portions23aand24a,for example.

In the respective embodiments, in the first upper-portion electrode23, the first embedded electrode portion23aand the first upper-layer electrode portion23bmay be formed by the same material and, for example, they may be formed by Al. Similarly, in the second upper-portion electrode24, the second embedded electrode portion24aand the second upper-layer electrode portion24bmay be formed by the same material and, for example, they may be formed by Al.

In the respective embodiments, the source layer13may be also selectively formed on the surface-layer portion of the base layer12. The first surface10aof the semiconductor substrate10may be also configured to have a base layer12and a source layer13. In this case, the first contact holes21are not necessarily required to be formed up to a larger depth than that of the first surface10aof the semiconductor substrate10, since only the base layer12and the source layer13are required to be exposed. The first contact holes21are required to be formed only as to expose the base layer12and the source layer13, from the first surface10aof the semiconductor substrate10.

In the respective embodiments, the temperature sensitive diode element18may be also configured to include multiple anode regions18aand cathode regions18b,which are placed in the temperature sensitive diode element18.

In the respective embodiments, the photoresist27for forming the first contact holes21and the second contact holes22may also be a negative type.

In the second embodiment, the shield wiring portion31may be also provided in the cell region1, and the temperature sensitive diode element18may be placed on the shield wiring portion31in the cell region1.

In the fourth embodiment, as illustrated inFIG. 10, the temperature sensitive diode element18may be also placed in the peripheral region2. The gate electrodes16may be also configured not to be placed just beneath the temperature sensitive diode element18. Even with this structure, malfunctions of the temperature sensitive diode element18due to variations of the gate voltage applied to the gate electrodes16may occur. Therefore, such malfunctions of the temperature sensitive diode element18may be suppressed by making the one-surface insulation film17to have a greater thickness, as similar to the fourth embodiment.

In the fifth embodiment, although not illustrated in particular, the shield electrodes29may be also configured not to be placed just beneath the temperature sensitive diode element18.

In the aforementioned fourth embodiment, the one-surface insulation film17is not required to be flattened. In this case, the gate electrodes16from being exposed, by forming the one-surface insulation film17such that it covers at least the portions of the gate electrodes16which protrude from the first surface10aof the semiconductor substrate10. The occurrence of protrusions of portions from the one surface of the one-surface insulation film17which is opposite from the semiconductor substrate10may be suppressed. When the temperature sensitive diode element18is formed in the process ofFIG. 2C, even if the process for flattening the one-surface insulation film17is not performed, the formation of a level difference in the Poly-Si, when the Poly-Si has been deposited, may be suppressed. Similarly, in the fifth embodiment, the one-surface insulation film17is not required to be flattened.

In the sixth embodiment, as illustrated inFIG. 11, no second trench14bmay be formed, and no shield electrode29may be formed. Similarly, in the second embodiment, as illustrated inFIG. 12, no trench14may be formed in the peripheral region2, and no shield electrode29may be formed. In these structures, similarly, the shield wiring portion31is connected to the first upper-portion electrode23, in a different cross section from that ofFIG. 11 or 12.

In the sixth embodiment, as illustrated inFIG. 13, neither second trench14bnor shield electrode29may be formed, and the same trench gate configuration may be provided in the cell region1and the peripheral region2. The shield wiring portion31may be formed on the first trenches14a.In this structure, similarly, the shield wiring portion31is connected to the first upper-portion electrode23, in a different cross section from that ofFIG. 13. In the second embodiment, similarly, as illustrated inFIG. 14, the same trench gate configuration may be provided in the cell region1and the peripheral region2, and no shield electrode29may be formed. The shield wiring portion31is connected to the second gate electrodes16b,in a different cross section from that ofFIG. 14. In these structures, since the same trench gate configuration is provided in the cell region1and the peripheral region2, the temperature sensitive diode element18may be placed either in the cell region1or in the peripheral region2.

With the structures inFIGS. 11 to 14, the degradation of the accuracy of the detection with the temperature sensitive diode element18may be suppressed since the temperature sensitive diode element18is formed on the shield wiring portion31, which is maintained at a predetermined electric potential.

In the second and sixth embodiments, the shield electrodes29and the shield wiring portion31may be formed by different materials. For example, the shield wiring portion31may be formed by Al or the like.