Method of forming split gate memory cells with 5 volt logic devices

A method of forming a memory device on a semiconductor substrate having a memory region (with floating and control gates), a first logic region (with first logic gates) and a second logic region (with second logic gates). A first implantation forms the source regions adjacent the floating gates in the memory region, and the source and drain regions adjacent the first logic gates in the first logic region. A second implantation forms the source and drain regions adjacent the second logic gates in the second logic region. A third implantation forms the drain regions adjacent the control gates in the memory region, and enhances the source region in the memory region and the source/drain regions in the first logic region. A fourth implantation enhances the source/drain regions in the second logic region.

FIELD OF THE INVENTION

The present invention relates to non-volatile memory cells, and more particularly to a method of forming such cells on the same wafer as logic devices.

BACKGROUND OF THE INVENTION

Split-gate type memory cell arrays are known. For example, U.S. Pat. No. 5,029,130, which is incorporated herein by reference for all purposes, discloses a split gate memory cell and its formation, which includes forming source and drain regions in the substrate with a channel region there between. A floating gate is disposed over and controls the conductivity of one portion of the channel region, and the control gate is disposed over and controls the conductivity of the other portion of the channel region. The control gate extends up and over the floating gate.

It is also known to form high voltage logic devices on the same wafer (substrate) as the split-gate memory cell array.FIGS. 1A-10A, 1B-10B and 1C-10Cshow the steps in forming high voltage logic devices (e.g. 12 volt logic devices) on the same wafer as the split gate memory cells. A semiconductor substrate10is masked (i.e. photo resist is deposited, selectively exposed using a mask, and selectively removed, using a photolithographic process, leaving portions of the underlying material covered by remaining photo resist while leaving other portions of the underlying material (here the substrate) exposed). The exposed substrate portions are etched away leaving trenches that are then filled with dielectric material12(e.g. oxide) to form isolation regions in the memory cell region14of the wafer (seeFIG. 1A), in the NMOS logic region16of the wafer (seeFIG. 1B) and in the PMOS logic region18of the wafer (seeFIG. 1C), all shown after the photo resist is removed. The wafer is then masked again, but this time to cover the NMOS logic and memory cell regions16and14with photo resist20, while leaving the PMOS logic region18exposed. A high voltage NWEL implant is then performed on the exposed PMOS logic region18, as shown inFIGS. 2A, 2B and 2C. The photo resist20blocks the implantation from the memory cell and NMOS logic regions14and16of the wafer. The photo resist20is removed. The wafer is then masked to cover the PMOS logic region18with photo resist22, but leaving the NMOS logic and memory cell regions16and14exposed. A high voltage PWEL implant is performed on the exposed NMOS logic and memory cell regions16and14as shown inFIGS. 3A, 3B and 3C.

After the photo resist22is removed, a layer of oxide24(FG oxide) is formed on the substrate10, a layer of polysilicon26(FG poly) is formed on oxide24, and a layer of nitride28(FG nitride) is formed on poly layer24, as shown inFIGS. 4A, 4B and 4C. The wafer is masked, leaving photo resist30on the wafer except on selected locations of the nitride28which are left exposed in the memory cell region14. The exposed nitride28is etched using an appropriate nitride etch to expose portions of poly layer26, as shown inFIGS. 5A, 5B and 5C. The exposed portions of the FG poly layer26are oxidized using an oxidation process, forming oxide areas32on the FG poly26.FIGS. 6A, 6B and 6Cshow the resulting structure after the photo resist30is removed. A nitride etch is used to remove the remaining nitride layer28. An anisotropic poly etch is used to remove exposed portions of the poly layer26, leaving blocks of polysilicon26underneath the oxide areas32in the memory cell region14(which will constitute the floating gates of the memory cells), as shown inFIGS. 7A, 7B and 7C.

An oxide layer34is formed over the structure. After additional masking and implant steps (logic NWEL, IO NWEL, logic PWEL, IO PWEL, LLVOX and LVOX), a layer of polysilicon is deposited over the wafer. The structure is masked leaving portions of the poly layer exposed, which are then removed by a poly etch. The remaining portions of the poly layer constitute the control gates36ain the memory cell region14, logic gate36bin the NMOS logic region16, and logic gate36cin the PMOS logic region18. The resulting structure is shown inFIGS. 8A, 8B and 8C(after the photo resist has been removed). The structure is masked again leaving only portions of the memory cell region between pairs of adjacent floating gate poly blocks26exposed by photo resist38. An implantation is performed to form source regions40in the portions of the substrate between the floating gate poly blocks36a, as shown inFIGS. 9A, 9B and 9C.

After the photo resist38is removed and after additional masking and implant steps (logic NLDD, IO NLDD, logic PLDD and IO PLDD), the wafer is masked again, leaving the PMOS logic and memory cell regions18and14covered by photo resist, but leaving the NMOS logic area16exposed. An LDD implantation is then performed on the NMOS logic region16. The photo resist is removed. The wafer is masked again, leaving the NMOS logic and memory cell regions16and14covered by photo resist, but leaving the PMOS logic region18exposed. An LDD implantation is then performed on the PMOS logic region18. After photo resist removal, the wafer is masked covering portions of the structure with photo resist but leaving the NMOS logic region16exposed and those portions of the memory cell region16adjacent the control gate poly blocks36aexposed. An N+ implantation is used to form the source/drain regions44and45in the NMOS logic region16and drain regions46in the memory cell region14. The photo resist is removed. The wafer is masked leaving just the PMOS logic region18exposed by photo resist, and a P+ implantation is used to form the source/drain regions48and49in the PMOS logic region18.

The photo resist is removed. The process continues by forming insulation spacers50, silicide layers52on the poly blocks36a,36band36cand on all the source/drain regions, and insulation layers54-57, as shownFIGS. 10A, 10B and 10C. This back end processing includes at least two more masking steps (silicide blocking to limit silicide formation, and back end processing to create the contacts58through the insulation over the drain regions in the memory cell region and over the source/drain regions in the logic device regions).

The above technique produces non-volatile memory cells (each with a source40, drain46, floating gate26, control gate36a) on the same substrate as high voltage NMOS logic devices (each with a logic gate36b, source44and drain45) and high voltage PMOS logic devices (each with a logic gate36c, source48and drain49). It would be desirable to reduce the complexity and cost of manufacturing the memory cells and logic devices, including the number of masking steps used.

BRIEF SUMMARY OF THE INVENTION

The aforementioned problems and needs are addressed by a method of forming a memory device that includes:

providing a semiconductor substrate having a memory region, a first logic region and a second logic region;

forming a pair of spaced apart floating gates in the memory region;

forming a pair of control gates in the memory region, wherein each control gate has a first portion adjacent to one of the floating gates and a second portion that extends up and over one of the floating gates;

forming a first logic gate in the first logic region;

forming a second logic gate in the second logic region;

forming a first photo resist that covers the second logic region and portions of the substrate adjacent to the control gates in the memory region, but not the first logic region and not a portion of the substrate between the pair of floating gates;

performing a first implantation that forms a source region in the substrate between the pair of floating gates, a source region in the substrate adjacent a first side of the first logic gate, and a drain region in the substrate adjacent a second side of the first logic gate opposite the first side of the first logic gate;

removing the first photo resist;

forming a second photo resist that covers the first logic region and the memory region, but not the second logic region;

performing a second implantation that forms a source region in the substrate adjacent a first side of the second logic gate and a drain region in the substrate adjacent a second side of the second logic gate opposite the first side of the second logic gate;

removing the second photo resist;

forming a third photo resist that covers the second logic region, but not the memory region and not the first logic region;

performing a third implantation that forms drain regions in the substrate adjacent the control gates;

removing the third photo resist.

DETAILED DESCRIPTION OF THE INVENTION

It has been discovered that by reducing the operating voltages on the logic devices (i.e. from 12 volts to 5 volts), significant reduction on the complexity and cost of manufacturing the memory cells and logic devices can be achieved. In fact, the number of masking steps can be reduced significantly.

FIGS. 11A-23A, 11B-23B and 11C-23Cshow the steps in forming high voltage logic devices (e.g. 5 volt logic devices) on the same wafer (substrate) as the split gate memory cells according to the present invention. A semiconductor substrate60is masked (i.e. photo resist is deposited, selectively exposed using a mask, and selectively removed, using a photolithographic process, leaving portions of the underlying material covered by remaining photo resist while leaving other portions of the underlying material (here the substrate) exposed). The exposed substrate portions are etched away leaving tranches that are then filled with dielectric material62(e.g. oxide) to form isolation regions in the memory cell region64of the wafer (seeFIG. 11A), in the NMOS logic region66of the wafer (seeFIG. 11B) and in the PMOS logic region68of the wafer (seeFIG. 11C). After the photo resist is removed, the wafer is then masked again, but this time to cover the PMOS logic region68with photo resist70, but leaving the memory cell and NMOS logic regions64and66exposed. A 5V PWEL implant is then performed on the exposed memory cell and NMOS logic regions64and66(e.g., to form P-wells in the N type substrate in the memory cell region64and NMOS logic region66), as shown inFIGS. 12A, 12B and 12C. The photo resist blocks the implantation from the PMOS logic region68of the wafer.

After the photo resist70is removed, a layer of oxide72(FG oxide) is formed on the wafer, a layer of polysilicon74(FG poly) is formed on oxide72, and a layer of nitride76(FG nitride) is formed on poly layer74, as shown inFIGS. 13A, 13B and 13C. The wafer is masked, leaving photo resist78on the wafer except on selected portions of the nitride76which are left exposed in the memory cell region64. The exposed nitride76is etched using an appropriate nitride etch to expose portions of poly layer74, as shown inFIGS. 14A, 14B and 14C. The exposed portions of poly layer74are oxidized using an oxidation process, forming oxide areas80on the FG poly.FIGS. 15A, 15B and 15Cshow the resulting structure after the photo resist78is removed. A nitride etch is used to remove the remaining nitride layer76. An anisotropic poly etch is used to remove the poly layer74except those portions underneath the oxide areas80in the memory cell region74, leaving blocks of polysilicon74that will constitute the floating gates of the memory cells, as shown inFIGS. 16A, 16B and 16C.

The wafer is then masked to cover the NMOS logic region66, and the memory cell region (except for those areas between adjacent FG poly blocks), with photo resist82. An implant (5V PMOS/PH) is performed on those areas left exposed by the photo resist82, as shown inFIGS. 17A, 17B and 17C. After the photo resist82is removed, an oxide layer84is formed on the structure and the wafer. After additional masking and implant steps (Core PWEL for logic NMOS and LVOX for open core oxide region), a layer of polysilicon is deposited over the wafer. The structure is masked leaving portions of the poly layer exposed, which are then removed by a poly etch. The remaining portions of the poly layer constitute the control gates86ain the memory cell region64, and the logic gates86band86cin the NMOS and PMOS logic regions66and68respectively. The resulting structure is shown inFIGS. 18A, 18B and 18C(after the photo resist has been removed).

After an additional masking and implant step (Core NLDD for logic NMOS and LDD), the structure is masked again leaving only the NMOS region66and those areas between adjacent floating gate poly blocks74in the memory cell region64exposed by photo resist87, followed by a 5V NLDD implantation to form the source regions88in the portions of the substrate between the floating gate poly blocks74in the memory cell region64and to form the source and drain regions90and91in the NMOS logic region66, as shown inFIGS. 19A, 19B and 19C. After the photo resist87is removed, and after an additional masking and implant step (Core PLDD), the structure is masked to leave only the PMOS logic region68exposed from photo resist92. This is followed by a 5V PLLD PH implantation to form source and drain regions94and95in the PMOS logic region68, as shown inFIGS. 20A, 20B and 20C. The purpose of the NLDD and PLLD implants is to mitigate the effect of hot carrier injection (HCl) damage and make the effective channel length shorter.

After photo resist92is removed, the structure is masked to cover PMOS logic region66with photo resist96, which is followed by an implantation (NNII-N+) to enhance the source region88and form drain regions101in the memory cell region64, and enhance the source and drain regions90and91in the NMOS logic region66, as shown inFIGS. 21A, 21B and 21C. After the photo resist96is removed, the wafer is masked with photo resist98except for the PMOS logic region68, and a P+ implantation is used to enhance the source/drain regions94/95in the PMOS logic region68, as illustrated inFIGS. 22A, 22B and 22C.

The process continues by forming insulation spacers100(e.g. by oxide deposition and etch), silicide layers102on the poly blocks86a,86band86cand on all source/drain regions, and insulation layers104-107, as shown inFIGS. 23A, 23B and 23C. This back end processing includes at least two more masking steps (silicide blocking to limit silicide formation, and back end processing for etching through insulation layers104-107to create contact holes108through the insulation over the drain regions in the memory cell region and over the source/drain regions in the logic device regions).

By forming high voltage logic devices that operate at a lower voltage (e.g. 5 volts) than done in the prior art (e.g. 12 volts), it allows for certain logic region implantations to be shared with the memory cell region that could not be shared before. These different sharing arrangements allow for a reduction of masking steps from 22 down to 15 in forming the memory cells and logic devices on the same wafer.

It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed. Additionally, the above method is illustrated with an N type substrate and P wells formed in the memory cell region and the NMOS logic region. However, a P type substrate can be used, in which case an N well can be formed in the PMOS logic region. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.

It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed there between) and “indirectly on” (intermediate materials, elements or space disposed there between). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.