Oversampled clock and data recovery with extended rate acquisition

In described embodiments, a transceiver supports two or more rates using an oversampling clock and data recovery (CDR) circuit sampling high rate data with a predetermined CDR sampling clock. A timing recovery circuit detects and accounts for extra or missing samples when oversampling lower rate data. An edge detector detects each actual data symbol edge and provides for an edge decision offset in a current instant's block of samples. An edge error is generated from the previous instant's actual and calculated edges; and an edge distance between actual edges of the current and previous instants is generated. Filtered edge distance and error are combined to generate a calculated edge position for the data symbol edge for the current instant. The edge decision offset is applied to the current calculated edge position to identify a sample value to generate a decision for the data symbol to detect the current data value.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to communication transceiver clock and data recovery, and, in particular, to timing recovery when oversampling lower data rates.

2. Description of the Related Art

In many data communication applications, serializer and de-serializer (SerDes) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data. One application for SerDes devices is related to the Universal Serial Bus (USB) specification that establishes communication between host controllers and multiple devices.

The USB standard currently includes three specifications: USB 1.x (“USB1”), USB 2.x (“USB2”), and USB 3.x (“USB3”), where “x” implies a particular version of the specification. USB1 specifies data transfer rates of 1.5 Mbps and 12 Mbps. USB2 specifies a higher data transfer rate of 480 Mbps, and USB3 specifies an even higher data transfer rate of 5 Gbps, termed a “SuperSpeed” bus. A SerDes device operating in accordance with USB3 desirably supports the lower speed specifications of USB1 and USB2, and so must support these data transfer rates (0.48 Gbps, 0.012 Gbps and 0.0015 Gbps). In addition, USB devices often interface with remote or network devices conforming to the Serial Advanced Technology Attachment (SATA) specification and their associated data stream rates. However, a SerDes device implementation supporting such a wide range of data transfer rates faces numerous technical challenges.

One component of a SerDes device is a clock and data recovery (CDR) circuit. The CDR extracts and reconstructs clock and data information from a single data stream that doesn't contain a clock signal during serial data transmission. The receiver of the data stream generates a signal, and then aligns sampling of the data stream with timing of detected transitions in the data stream based on a locally generated clock using a phase-locked loop. In operation at high data rates, SerDes devices are challenged with correctly extracting such timing of the data stream due to jitter, noise, and other effects of the communication channel. Equalization (analog and decision feedback) is often employed, requiring adaptation during acquisition and steady state operation. These factors often dictate that SerDes receiver design, including the CDR circuit, be optimized for a given, relatively narrow range of data transfer rates. Consequently, many existing SerDes designs incorporate separate CDR circuitry to support such a wide range of data transfer rates as specified in USB3.

Backward compatibility for each new standard often requires the new devices operating with the standard support operation in accordance with previous versions of the standard. Unfortunately, to accommodate such a wide range of operating frequencies with USB1, USB2 and USB3, separate receivers operating in parallel is often required.

SUMMARY OF THE INVENTION

In one embodiment, the present invention provides for timing recovery in a receiver having a higher-rate sampling clock for sampling a higher-rate data stream and a lower-rate data stream includes oversampling, with a sampling module, the lower-rate data stream based on the higher rate sampling clock to provide blocks of samples. An edge detector detects one or more data symbol actual edges within the blocks of samples. A calculated edge for a current instant is generated based on i) an edge error and an edge distance between a previous instant and the current instant and ii) a calculated edge of the previous instant. An offset for the current instant is adjusted based on the calculated edge for the current instant; and data of a data symbol from the lower-rate data stream is detected from a sample identified by the adjusted offset for the current instant.

DETAILED DESCRIPTION

In accordance with embodiments of the present invention, a transceiver, such as a universal serial bus (USB) transceiver, supports two or more rates, using an oversampling clock and data recovery (CDR) circuit for data recovery. The CDR circuit samples high rate data with a predetermined CDR sampling clock, and includes a timing recovery circuit that detects and accounts for extra or missing samples when oversampling the lower rate data with the predetermined CDR sampling clock. The timing recovery circuit employs an edge detector to detect each data symbol edge (first sample in a current instant block of the oversampled data symbol) and provide for an edge decision offset (number of samples to the approximate center of the oversampled data symbol) in a current instant block of samples. An actual edge and a calculated edge for a previous instant are compared to provide an edge error. An edge distance for the current instant is generated as the difference (or “distance”) between actual edges of the current and previous instants. Filtered edge distance and filtered edge error are combined to generate a calculated edge position for the data symbol edge for the current instant. From this calculated edge (sample) position for the data symbol, the sample decision (edge) offset is applied to identify a sample value from which a decision can be generated for the data symbol to detect the current data value.

FIG. 1shows a block diagram of receiver system100operating in accordance with exemplary embodiments of the present invention. System100includes multiplexer (MUX)101that selects a given one of four input signal data streams, shown as USB3, USB2, USB (low and full speed) and SATA data streams, for data detection. System100further includes front end circuit102to perform analog-to-digital conversion (ADC) on the input signal, as well as apply equalization (e.g., analog front-end equalization (AFE) and/or decision feedback equalization (DFE)) to the input signal to correct for channel losses, dispersion and inter-symbol interference (ISI). Front end circuit102includes sampling module103, decision circuit (e.g., a slicer)104, and clock recovery105. Sampling module103samples the input data to provide digital samples of data symbols at the highest rate, for example, the USB3 rate of an implementation. Decision circuit104compares the samples with a threshold to make a decision for a data symbol. Clock recovery105extracts timing information from the sampled input data to synchronize local clock signals to the input data to generate the sampling clock employed by sampling module103and for detecting the high rate data. Consequently, front end circuit102performs clock and data recovery (CDR) for the, for example, USB3 data stream. As shown inFIG. 1, decision circuit (e.g., a slicer)104, and clock recovery105exchange information, or provide feedback, for tracking of sampling clock with respect to timing of the detected higher-rate data stream data clock when processing, for example, the USB3 data stream.

However, when processing lower-rate data streams (e.g., the USB2, USB (low and full speed) and SATA data streams) for data detection, the front end circuit102performs oversampling of these lower rate signals without necessarily performing other functions associated with the CDR. When processing lower-rate data streams for data detection, the front end circuit102causes clock recovery105to set the sampling clock rate to a predefined rate. The predefined rate is set to either i) the nominal higher-rate data stream data clock rate or some user-defined clock rate. Under such circumstances, timing extraction from the data stream is not necessarily performed, and so decision feedback, tracking, and other CDR functions might be disabled.

The oversampled data stream for lower rates is applied to edge detector106, timing recovery circuit107, and symbol edge and offset detector108(described below in detail). Edge detector106receives data symbol samples from the input data stream and detects symbol transitions, or edges, between data symbols. Based on the actual detected edges between data symbols, symbol edge and offset detector108applies an offset within the sample value positions to select a sample value corresponding to the relative center of the data symbol. From this offset sample value, a decision might be made as to the data value of the data symbol. However, since the timing of the input data stream might vary in comparison to the decimated sampling clock timing (of, e.g., sampling module103), the offset might vary. Timing recovery circuit107, based on the output of edge detector106, determines this variation in timing and calculates an associated correction to the offset. Therefore, symbol edge and offset detector108, based on the correction, adjusts its offset to account for the variation in timing between the sampling clock and input data stream.

For an exemplary USB system supporting an integrated USB2 and USB3 physical layer (PHY), MUX101is employed to select one of the four input signal data streams, shown as USB3, USB2, USB (low and full speed) and SATA data streams, for data detection. When selected for USB3, front end circuit102operates normally, sampling at the USB3 data at the USB3 baud rate. When selected for USB2, front end circuit102operates so as to oversample the 480 MHz USB2 data at ten-times, or “10×”, data rate to produce a 4.8 GHz output, and operates so as to oversample the 12 MHz full speed USB data at 400× rate to produce a 4.8 GHz output. For low speed USB data, oversampling might occur at 3200× rate. When processing the data rates lower than USB3, front end circuit102operates in a low power mode, allowing for pass-through for the CDR, AFE and DFE processing, thereby consuming less circuit and processing power. Once the symbol edge is determined, the symbol is sampled by selecting an oversampled bit in an oversampling block with a pre-calculated offset. The offset for high-speed USB2 mode is 5 bits, the offset for full speed USB mode is 200 bits, and the offset for full speed USB mode is 1600 bits. Output symbol decision data might be decimated for some embodiments depending on the amount of oversampling of the lower rate data.

Examples of operation without timing recovery for mismatch between sampling of a CDR circuit and the incoming data are shown inFIG. 3(incoming data clock slightly faster than 10× sampling) andFIG. 4(incoming data slower than 10× sampling). As shown inFIGS. 3 and 4, 10 × oversampling of an incoming data symbol value generates a 10-sample (or 10-bit) block of values corresponding to a single incoming data symbol value period.

FIG. 3shows a sequence300of data symbols received with a data rate that is slightly faster than 1/10thof the 10× sampling rate. Sampling generates a series of 10-bit blocks301(1)-301(8). Each data symbol in sequence300has a corresponding edge, shown as edges302(1)-302(11). Decisions for samples are ideally made at the approximate centers of the data symbols, shown as decision points303(1)-303(10). Since each received data symbol is slightly less than the 10-bit block period, each 10-bit block contains less than ten samples of the current data symbol and an increasing number of sample values of the next data symbol. As shown inFIG. 3between edges302(2) and302(4), and between edges302(7) and302(9), if the incoming data rate is faster than 10× sampling, occasionally two sampling decisions would occur during a single 10-bit block.

FIG. 4shows a sequence400of data symbols received with a data rate that is slightly slower than 1/10thof the 10× sampling rate. Sampling generates a series of 10-bit blocks401(1)-401(8). Each data symbol in sequence400has a corresponding edge, shown as edges402(1)-402(8). Decisions for samples are ideally made at the approximate centers of the data symbols, shown as decision points403(1)-403(8). Since each received data symbol is slightly more than the 10-bit block period, each 10-bit block contains ten samples of the current data symbol and the subsequent block contains an increasing number of sample values of the previous data symbol. As shown inFIG. 4between edges402(6) and402(8), if the incoming data rate is slower than 10× sampling, occasionally no sampling decision occurs during a single 10-bit block.

FIG. 5shows an exemplary timing recovery circuit107ofFIG. 1operating in accordance with embodiments of the present invention. Timing recovery circuit107comprises combiners501and502, low pass filters (LPFs)503and504, and combiner505. Operation of timing recovery circuit107in the presence of data with 10× oversampling is now described.

Data value551is over-sampled at a 10× rate into sample block552(1) of ten samples at time n (as employed herein, at a first instant). As shown, sampling is faster than the incoming data rate, so a portion560of the data symbol extends into sampling block552(2) at time n+1 (a second instant). Edge detector106(not shown in theFIG. 5) detects actual edge570at time n, and the CDR circuit operates to make a data decision at sample point580. Timing recovery circuit107then employs the actual and calculated edges at the previous instant (e.g., instant n) along with the detected actual edge571at the current instant (n+1) to generate a calculated edge at the current instant. The CDR circuit then operates to make a data decision at sample point581. In this timing recovery circuit loop, the calculated symbol edge is determined by adding the filtered edge distance and filtered edge error to the previously calculated edge. This filtering tracks the parts per million (ppm) differences between the incoming data rate and the fixed oversampling clock. The CDR circuit then uses this calculated edge value with a symbol decision edge offset to make a decision for the current symbol's data value (e.g., sample point581at instant n+1).

Initially, calculated edge575(e.g., at instant n) is set to the actual edge or some pre-defined offset. A calculated edge (e.g., calculated edge576at instant n+1) is subsequently determined as follows. A filtered edge error is calculated by i) combining actual and calculated edge values at the previous instant in combiner501, and ii) low pass filtering the result in LPF503. A filtered edge distance between the current and previous instants is calculated by i) combining actual edge values at the previous and current instants in combiner502, and ii) low pass filtering the result in LPF504. The filtered edge distance and filtered edge error are added to the previously calculated edge in combiner505to generate the calculated edge for the current instant. Note that low pass filtering of values provides the mean of the associated value.

One skilled in the art might readily modify embodiments of the present invention beyond edge values from the current and previous instants to use edge values from other instants. Further, embodiments of the present invention might employ weighting one or more of the various edge values, or might employ adaptive techniques for tracking changes in incoming data rates to pre-adjust edge and symbol decision offset values used.

A transceiver operating in accordance with one or more embodiments of the present invention might provide for the following advantages. The transceiver might exhibit increased performance by enhanced timing recovery, thereby avoiding slips that generate bursts of bit errors, that might cause loss of lock of the sampling clock to the input data stream, and that might cause sub-optimal symbol decision timing. Consequently, such transceiver might exhibit increased speed and reliability in unfavorable communication environments.

While the exemplary embodiments of the present invention have been described with respect to processes of circuits, including possible implementation as a single integrated circuit, a multi-chip module, a single card, or a multi-card circuit pack, the present invention is not so limited. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing blocks in a software program. Such software may be employed in, for example, a digital signal processor, micro-controller, or general purpose computer.

Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements. Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for purposes here.