SEMICONDUCTOR DEVICE WITH DUAL DAMASCENE AND DUMMY PADS

A semiconductor device is provided. The semiconductor device can have a front side at which circuitry is disposed. The circuitry can include a pad and a plurality of lines. A first layer of dielectric material can be disposed at the front side at least partially over the pad and the plurality of lines. A second layer of dielectric material can be disposed at the front side at least partially over the first layer of dielectric material. A dual damascene pad can extend through the first layer of dielectric material and the second layer of dielectric material to the pad. A dummy pad can be disposed in the second layer of dielectric material above the plurality of lines and spaced from the dual damascene pad. In doing so, a reliable semiconductor device can be implemented.

TECHNICAL FIELD

The present disclosure generally relates to semiconductor device assemblies and more particularly relates to a semiconductor device with dual damascene and dummy pads.

BACKGROUND

Microelectronic devices generally have a die (e.g., a chip) that includes integrated circuitry with a high density of very small components. Typically, dies include an array of bond pads electrically coupled with the integrated circuitry. The bond pads are external electrical contacts through which the supply voltage, signals, etc., are transmitted to and from the integrated circuitry. After dies are formed, they are “packaged” to couple the bond pads to a larger array of electrical terminals that can be more easily coupled with the various power supply lines, signal lines, and ground lines. Conventional processes for packaging dies include electrically coupling the bond pads on the dies to an array of leads, ball pads, or other types of electrical terminals and encapsulating the dies to protect them from environmental factors (e.g., moisture, particulates, static electricity, and physical impact).

DETAILED DESCRIPTION

Semiconductor devices are integrated into many devices to implement memory cells, processor circuits, imager devices, and other functional features. As more applications for semiconductor devices are discovered, designers are tasked with creating improved devices that can perform a greater number of operations per second, store greater amounts of data, or operate with a higher level of security. To accomplish this task, stacked semiconductor devices are implemented to increase the number of circuit elements on a semiconductor device without simultaneously increasing the device footprint. Implementing stacked semiconductor devices, however, may present additional design challenges, some of which are illustrated inFIG.1.

FIG.1illustrates a simplified schematic cross-sectional view of a semiconductor device assembly100. The semiconductor device assembly100includes a semiconductor die102coupled with a semiconductor die104. The semiconductor die102includes circuitry (e.g., contact pads106and lines108) that provide connectivity to internal circuitry of the semiconductor die102. Contact pads110are implemented at the contact pads106and coupled with contact pads112at the semiconductor die104to implement interconnects that electrically couple the semiconductor dies. As illustrated, the semiconductor die102also includes dummy pads114exposed at a surface of the semiconductor die102and coupled with dummy pads116at the semiconductor die104.

As used herein, “a dummy pad” can refer to a conductive pad that is not used to form an interconnect between two semiconductor dies and thus can be disconnected from connective circuitry at the semiconductor dies. Instead, a dummy pad can be implemented to improve the mechanical coupling between dies, to improve the thermal regulation of a semiconductor device assembly, or to increase the uniformity along an exposed coupling surface of a semiconductor die.

For example, the contact pads110can be arranged along the surface of the semiconductor die102differently based on a specific configuration. In some arrangements, the contact pads110can have non-uniform pitch across the semiconductor die102. When chemical-mechanical planarization (CMP) is used to planarize the coupling surface of the semiconductor, large gaps or non-uniformities across the semiconductor dies can cause inconsistencies at the coupling surface that can impact the coupling between the semiconductor dies. For instance, as illustrated between dummy pad114-2and dummy pad116-2, dishing can occur, thereby limiting the adhesion between the semiconductor dies or shorting the interconnects. As another example, erosion118can occur at dielectric material120(e.g., silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride) or dielectric material122(e.g., silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride) at the coupling surface of the semiconductor die102and the semiconductor die104, respectively, which can decrease the adhesion between the semiconductor dies or cause conductive material to bleed into circuitry exposed through the erosion118and short the semiconductor device assembly100.

In yet another aspect, the dummy pads114can short the semiconductor device assembly100through the circuitry at the semiconductor die102. For example, dielectric material124can be disposed at least partially over the circuitry (e.g., contact pads106and lines108). Openings can be created in the dielectric material120and conductive material may be deposited in the opening to implement the dummy pads114. When creating the openings, the dielectric material124can be removed and the conductive material implementing the dummy pads114can directly contact the lines108(e.g., where the dielectric material is removed or through seams in the dielectric material124), as illustrated by dummy pad114-1and lines108-1, thereby shorting the semiconductor device assembly100. In other cases, the dummy pads114and the lines108can form a capacitive coupling through the dielectric material124, as illustrated by dummy pad114-2and lines108-2, which can degrade the performance of the semiconductor device assembly100. Moreover, dummy pads cannot be implemented at some locations, for example, within a short distance above a probe pad, given that these dummy pads can cause deformation when implemented too close to other circuitry (e.g., less than 1 micron away, less than 2 microns away, less than 3 microns away).

To address these drawbacks and others, the present technology discloses a semiconductor device with dual damascene and dummy pads. The semiconductor device can have a front side at which circuitry is disposed. The circuitry can include a pad and a plurality of lines. A first layer of dielectric material can be disposed at the front side at least partially over the pad and the plurality of lines. A second layer of dielectric material can be disposed at the front side at least partially over the first layer of dielectric material. The dual damascene pad can extend through the first layer of dielectric material and the second layer of dielectric material to the pad. The dummy pad can be disposed in the second layer of dielectric material above the plurality of lines to prevent electrical contact therewith. In doing so, a reliable semiconductor device can be implemented, an example of which is illustrated inFIG.2.

FIG.2illustrates a simplified schematic cross-sectional view of a semiconductor device assembly200in accordance with an embodiment of the present technology. The semiconductor device assembly200includes a semiconductor die202coupled with a semiconductor die204. The semiconductor die202includes routing circuitry (e.g., contact pads206, lines208, probe pad210) at a front side that provides connectivity to internal circuitry of the semiconductor die202or additional semiconductor dies coupled with through-silicon vias (TSVs)212exposed at the back side. A layer of dielectric material214(e.g., silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride) can be disposed at least partially over the contact pads206, the lines208, or the probe pad210. A layer of dielectric material216(e.g., silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride) can be disposed at least partially over the layer of dielectric material214. A layer of dielectric material218, a layer of dielectric material220, and a layer of dielectric material222can be layered at the front side of the semiconductor die202over the layer of dielectric material216.

In some cases, the layer of dielectric material214can include a thin layer (e.g., less than 0.1 microns, less than 0.2 microns, less than 0.5 microns) of silicon carbon nitride (e.g., deposited at a temperature greater than 350 degrees Celsius). The layer of dielectric material214can be disposed at the surface at which the contact pads206, the lines208, or the probe pad210is disposed. The layer of dielectric material214can extend over the sides of the contact pads206and partially over a coupling surface of the contact pads206, leaving an exposed surface at which dual damascene pads224are coupled. The layer of dielectric material214can extend over and between the lines208. The layer of dielectric material214can further extend over a portion of the probe pad210such that a portion of the probe pad210is exposed to enable testing of the semiconductor die202.

The layer of dielectric material216can be disposed at least partially over the layer of dielectric material214. In aspects, the layer of dielectric material216is a dielectric block, which can include, for example, silicon oxide (e.g., deposited at a temperature greater than 350 degrees Celsius). In aspects, deposition of the layer of dielectric material216can cause pinch off when deposited around the lines208, causing airgaps226to form in the layer of dielectric material216. The airgaps226can be located above the lines208, laterally between adjacent pairs of the lines208. The layer of dielectric material216can be deposited with a thickness sufficient to keep dummy pads228from contacting the circuitry (e.g., lines208, probe pad210) at the semiconductor die202. For example, the layer of dielectric material216can be deposited with a thickness greater than 1 micron, greater than 2 microns, greater than 3 microns, greater than 5 microns, and so on.

The layer of dielectric material218can be disposed at least partially over the layer of dielectric material216. In aspects, the layer of dielectric material218can include silicon carbon nitride (e.g., deposited at a temperature above 350 degrees Celsius). The layer of dielectric218can be a thin layer of dielectric material (e.g., less than 0.1 microns, less than 0.2 microns, less than 0.5 microns). The layer of dielectric material220can be disposed at least partially over the layer of dielectric material218. The layer of dielectric material220can include a silicon block (e.g., of silicon oxide) with a thickness sufficient to implement an exposed portion of the dual damascene pads224or the dummy pads228(e.g., greater than 0.5 microns, greater than 1 micron, greater than 1.5 microns, greater than 2 microns). The layer of dielectric material222(e.g., a thin layer of silicon carbon nitride) can then be disposed at least partially over the layer of dielectric material220to provide a passivized coupling surface. The layer of dielectric material222can extend over a coupling surface of the semiconductor die202except at the dual damascene pads224and the dummy pads228, thereby exposing a coupling surface of the dual damascene pads224and the dummy pads228.

The dual damascene pads224can be implemented at the front side of the semiconductor die202and extending through the layers of dielectric material (e.g., layer of dielectric material214,216,218,220,222) to the contact pads206(e.g., aluminum pads, copper pads). The dual damascene pads224can be implemented using a conductive material (e.g., copper, gold, silver). The dual damascene pads224can have an outer portion disposed in the layer of dielectric material220and an inner portion disposed in the layer of dielectric material216. The outer portion can be implemented such that it extends to the layer of dielectric material218. The outer portion can have a width greater than the inner portion. For example, the outer portion can have a width greater than 3 microns, greater than 4 microns, greater than 5 microns, and so on, and the inner portion can have a width less than 3 microns, less than 2 microns, and so on.

The dummy pads228can be implemented at the front side of the semiconductor die202laterally spaced from the dual damascene pads224. The dummy pads228can be located at a same lateral location as and spaced above (e.g., by more than 1 micron, by more than 2 microns, by more than 3 microns, by more than 5 microns) the lines208, the airgaps226, or the probe pad210. In this way, electrical contact with the lines208or the probe pad210can be prevented. Moreover, conductive material from the dummy pads228may not leak into the airgaps226. The dummy pads228can extend through the layer of dielectric material220(e.g., and the layer of dielectric material222) to the layer of dielectric material218. In aspects, uniformity can be maintained across the semiconductor die202to control the effects of CMP, provide consistent thermal regulation, etc. In this way, the pitch of the dual damascene pads224and the dummy pads228(e.g., or the dummy pads228alone) can be consistent across the semiconductor die202. For example, the dual damascene pads224and the dummy pads228can have a pitch less than 10 microns, less than 15 microns, less than 20 microns, and so on.

The dual damascene pads224and the dummy pads228can connect to contact pads230(e.g., copper pads) and dummy pads232(e.g., copper pads) at the semiconductor die204, respectively. The contact pads230and the dummy pads232can be implemented within a layer of dielectric material234(e.g., silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride) at a back side of the semiconductor die204. The layer of dielectric material234can bond (e.g., fusion bond) with dielectric material at the semiconductor die202(e.g., the layer of dielectric material222). The contact pads230and the dummy pads232can couple (e.g., metal-metal bond, hybrid bond) with the dual damascene pads224and the dummy pads228, respectively. In doing so, the contact pads230and the dual damascene pads224can form interconnects that electrically couple the semiconductor die202and the semiconductor die204, and the dummy pads232and the dummy pads228can bond to improve the coupling between the semiconductor dies and the thermal regulation of the semiconductor device assembly200. Moreover, the contact pads230can connect to TSVs236to provide connectivity to a substrate (e.g., printed-circuit board (PCB), interposer, semiconductor die) coupled with the semiconductor die204at the TSVs236.

Various techniques can be used to fabricate a semiconductor device with a conductive pillar that includes a thermally conductive material. One example for fabricating such a semiconductor device assembly is illustrated inFIGS.3-6. Specifically,FIG.3illustrates a simplified schematic cross-sectional view of a semiconductor device assembly300. The semiconductor device assembly300includes a substrate302(e.g., organic substrate, semiconductor substrate), which can be a wafer-level, panel-level, or die-level substrate. In aspects, the substrate302is a silicon wafer. The semiconductor device assembly can include TSVs304that extend through the substrate302. Circuitry can be disposed at the front side of the substrate302(e.g., coupled through routing circuitry to the TSVs304). The circuitry can include contact pads306, lines308, or a probe pad310.

A layer of dielectric material312can be disposed over the contact pads306, the lines308, or the probe pad310. The layer of dielectric material312can be deposited using any appropriate technique, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). The layer of dielectric material312can be deposited within the gaps between the lines308. In aspects, the layer of dielectric material312can be removed at some locations to expose the circuitry. For example, the layer of dielectric material312disposed on top of the probe pad310can be removed to expose a testing surface. A testing tool can be used to probe the testing surface of the probe pad310to test the circuitry. Once testing has completed, additional layers of dielectric material can be deposited at the front side, as illustrated inFIG.4.

FIG.4illustrates a simplified schematic cross-sectional view of a semiconductor device assembly400. A layer of dielectric material402(e.g., dielectric block) can be deposited over the layer of dielectric material312. In some cases, after one or more of the layers of dielectric material are deposited, the dielectric material can be planarized (e.g., using CMP). As illustrated, the layer of dielectric material402is deposited over the testing surface of the probe pad310. The layer of dielectric material402can have sufficient thickness to prevent electrical connection (e.g., physical contacting, conductive coupling) with the contact pads306, the lines308, or the probe pad310(e.g., greater than 1 micron, greater than 2 microns, greater than 3 microns, greater than 5 microns). In some cases, depositing the layer of dielectric material402can create airgaps404within the layer of dielectric material402. For example, the airgaps404can form between the lines308. The layer of dielectric material402can have a flat, continuous upper surface (without openings). A layer of dielectric material406can be disposed over the layer of dielectric material402.

A layer of dielectric material408(e.g., dielectric block) can then be disposed over the layer of dielectric material406. The layer of dielectric material408can have a thickness sufficient to implement contact pads (e.g., greater than 0.5 microns, greater than 1 micron, greater than 2 microns). The layer of dielectric material408can be deposited with a continuous upper surface, and openings410can be formed in the layer of dielectric material408. Alternatively, the layer of dielectric material408can be selectively deposited at only portions of the layer of dielectric material406, leaving the openings410void of dielectric material. A layer of dielectric material412can be deposited over the layer of dielectric material408. The openings410can extend through the layer of dielectric material412.

The openings410can be formed by removing the layer of dielectric material408and the layer of dielectric material412using any appropriate method (e.g., etching, drilling). The openings410can extend to the layer of dielectric material406with a width sufficient to implement contact pads. For example, the openings410can have a width greater than 2 microns, greater than 3 microns, greater than 5 microns, and so on. The openings410can be disposed at lateral locations that correspond to the circuitry. For example, the openings410can be formed above the contact pads306, the lines308, or the probe pad310. In some cases, one or more of the openings410can be located above the airgaps404. The openings410can be disposed uniformly across the surface of the semiconductor device assembly400. Additional openings can then be formed at the openings410, as illustrated inFIG.5.

FIG.5illustrates a simplified schematic cross-sectional view of a semiconductor device assembly500. Openings502can extend through the layer of dielectric material312, the layer of dielectric material402, and the layer of dielectric material406. The openings502can be created within one or more of the openings410. For example, the openings502can be created in the openings410that correspond to the contact pads306but not in the openings410that correspond to the lines308or the probe pad310. The openings502can extend entirely through the layers of dielectric material to expose a surface of the contact pads306. The openings502can have a width smaller than the width of the openings410. For example, the openings502can have a width less than 1 micron, less than 2 microns, less than 3 microns, less than 5 microns, and so on. The openings502can be formed using any appropriate technique, for example, a technique the same as or different from the techniques used to create the openings410. Conductive material can then be disposed in the openings410and the openings502to implement circuitry, as illustrated inFIG.6.

FIG.6illustrates a simplified schematic cross-sectional view of a semiconductor device assembly600after conductive material has been disposed in the openings to implement dual damascene pads602and dummy pads604. The conductive material can be disposed through any appropriate method (e.g., dispensing). The dual damascene pads602can extend to the contact pads306and have an exposed coupling surface. In this way, circuitry at the semiconductor device assembly600can be coupled with additional semiconductor dies through the dual damascene pads602. The dummy pads604can be located above the lines308or the probe pad310. The dummy pads604can be separated from the lines308or the probe pad310by a sufficient distance to prevent electrical coupling. In some cases, the dummy pads604can be located above and in a same lateral location as the airgaps404. In this way, the conductive material will not bleed into the airgaps404and short the semiconductor device assembly600.

Once the conductive material has been disposed in the openings, the semiconductor device assembly600can be planarized (e.g., using CMP) to create a planar coupling surface. The planarization can cause material to be removed from the layer of dielectric material412. However, the presence of the dummy pads604can prevent excessive erosion of the layer of dielectric material, which can expose the layer of dielectric material408in some locations and impact bonding or electrical performance. Moreover, the planarization can cause dishing on the dual damascene pads602or the dummy pads604. In aspects, the dummy pads604can help to control CMP dishing, thereby reducing the likelihood of over- or under-expanded interconnects. Additional semiconductor dies (e.g., or a substrate) can then be coupled with the semiconductor device assembly600at the dual damascene pads602and the dummy pads604.

The substrate302can also be planarized (e.g., using CMP) to expose the TSVs304. For example, material can be removed from the back side of the substrate302until the TSVs304are exposed. A layer of dielectric material can be disposed at the back side of the substrate302, and contact pads can be implemented within the dielectric material. The contact pads can be disposed at the exposed portion of the TSVs304. In this way, additional semiconductor dies (e.g., or a substrate) can be coupled with the semiconductor device assembly600at the contact pads. In doing so, a packaged semiconductor device can be assembled, an example of which is illustrated inFIG.7.

FIG.7illustrates a simplified schematic cross-sectional view of a semiconductor device assembly700in accordance with an embodiment of the present technology. Semiconductor dies702can be coupled in a front-to-front arrangement, a front-to-back arrangement, or a back-to-back arrangement. One or more of the semiconductor dies702can include TSVs704to couple contact pads at a back side with a metallization layer (e.g., with traces, lines, vias, or other connection structures) at the front side. The semiconductor dies702can be electrically coupled through interconnects706, for example, formed from dual damascene pads. The semiconductor dies702can also be coupled through dummy pads708.

The semiconductor dies702may be coupled with a package-level substrate710(e.g., PCB, interposer, another semiconductor die). Connective structures712(e.g., solder balls, solder bumps, conductive pillars) can be disposed between contact pads at a lower side of a bottom semiconductor die of the semiconductor dies702and contact pads (not shown) at an upper side of the package-level substrate710to implement interconnects that electrically couple the semiconductor dies702and the package-level substrate710. An underfill material714(e.g., capillary underfill) can be provided between a bottom die of the semiconductor dies702and the package-level substrate710to provide electrical insulation to the connective structures712and structurally support the semiconductor device assembly700. The package-level substrate710can include internal routing circuitry (e.g., traces, lines, vias, and other connection structures) that connects the contact pads at the upper side to contact pads at the lower side. Connective structures716may be disposed at the contact pads at the lower side to provide external connectivity to other devices (e.g., on a motherboard). The semiconductor device assembly700can further include an encapsulant material718(e.g., mold resin compound or the like) that at least partially encapsulates the stack of semiconductor dies702and the package-level substrate710to prevent electrical contact therewith or provide mechanical strength to the semiconductor device assembly700.

In accordance with one aspect of the present disclosure, the semiconductor devices illustrated in the assemblies ofFIGS.1-7could include memory dies, such as dynamic random access memory (DRAM) dies, NOT-AND (NAND) memory dies, NOT-OR (NOR) memory dies, magnetic random access memory (MRAM) dies, phase change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, or the like. In aspects, the semiconductor devices can be high-bandwidth memory (HBM) devices having one or more memory dies assembled onto a logic die (e.g., memory controller). In an embodiment in which multiple dies are provided in a single assembly, the semiconductor devices could include memory dies of a same kind (e.g., both NAND, both DRAM, etc.) or memory dies of different kinds (e.g., one DRAM and one NAND, etc.). In accordance with another aspect of the present disclosure, the semiconductor dies of the assemblies illustrated and described above could be logic dies (e.g., controller dies, processor dies, etc.) or a mix of logic and memory dies (e.g., a memory controller die and a memory die controlled thereby). For example, an HBM device can include a logic die having 8, 12, 16, 20, 24 or any other number of memory dies assembled thereon.

Example Systems

Any one of the semiconductor devices and semiconductor device assemblies described above with reference toFIGS.1-7can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system800shown schematically inFIG.8. The system800can include a semiconductor device assembly802(e.g., a discrete semiconductor device), a power source804, a driver806, a processor808, and/or other subsystems or components810. The semiconductor device assembly802can include features generally similar to those of the semiconductor device assemblies described above with reference toFIGS.1-7. The resulting system800can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems800can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, appliances, and other products. Components of the system800can be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system800can also include remote devices and any of a wide variety of computer-readable media.

This disclosure now turns to methods for fabricating semiconductor device assemblies in accordance with one or more embodiments of the present technology. Although illustrated in a particular configuration, operations within any of the methods may be omitted, repeated, or reorganized. Moreover, any of the methods may include additional operations, for example, those detailed in one or more other methods described herein.

FIG.9illustrates a method900for fabricating a semiconductor device assembly. At902, a substrate having a first side is provided. At904, circuitry, including a pad and a plurality of lines, is disposed at the first side of the substrate. At906, a first layer and a second layer of dielectric material are disposed. The first layer of dielectric material is disposed at the first side at least partially over the pad and the plurality of lines. The second layer of dielectric material is disposed at the first side at least partially over the first layer of dielectric material. At908, a first opening and a second opening are created. The first opening extends through the first layer of dielectric material and the second layer of dielectric material to the pad. The second opening is laterally aligned with the plurality of lines and extends through the first layer of dielectric material to the second layer of dielectric material. At910, conductive material is disposed in the first opening and the second opening to implement a dual damascene pad in the first opening and a dummy pad in the second opening.

Specific details of several embodiments of semiconductor devices, and associated systems and methods, are described above. Depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated, die-level substrate. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using CVD, PVD, atomic layer deposition, plating, electroless plating, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, CMP, or other suitable techniques.

The technology disclosed herein relates to semiconductor devices, systems with semiconductor devices, and related methods for manufacturing semiconductor devices. The term “semiconductor device” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. Furthermore, the term “semiconductor device” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished device. Depending upon the context in which it is used, the term “substrate” can refer to a structure that supports electronic components (e.g., a die), such as a PCB or wafer-level substrate, a die-level substrate, or another die for die-stacking or three-dimensional integration (3DI) applications.

The devices discussed herein, including a memory device, can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or subregions of the substrate, can be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and appended claims. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.