Method and apparatus for detecting end of start up phase

A PSE configured to determine the end of the start up phase at the PD responsive to a condition of the voltage at the PSE output. In one particular embodiment, the startup phase end is determined responsive to a PSE output voltage within a predetermined range of the PSE input voltage. In another particular embodiment, the startup phase end is determined responsive to the voltage drop associated with the PSE current limiter being lower than a predetermined maximum. In yet another particular embodiment, the startup phase end is determined responsive to the absolute value of the rate of change of the PSE output voltage being lower than a predetermined value. In yet another particular embodiment, the startup phase end is determined responsive to the absolute value of the rate of change of the voltage drop associated with the PSE current limiter being lower than a predetermined value.

BACKGROUND OF THE INVENTION

The invention relates generally to the field of power over local area networks, particularly Ethernet based networks, and more particularly to detecting the end of a start up phase.

The growth of local and wide area networks based on Ethernet technology has been an important driver for cabling offices and homes with structured cabling systems having multiple twisted wire pairs. The structure cable is also known herein as communication cabling and typically comprises four twisted wire pairs. In certain networks only two twisted wire pairs are used for communication, with the other set of two twisted wire pairs being known as spare pairs. In other networks all four twisted wire pairs are used for communication. The ubiquitous local area network, and the equipment which operates thereon, has led to a situation where there is often a need to attach a network operated device for which power is to be advantageously supplied by the network over the network wiring. Supplying power over the network wiring has many advantages including, but not limited to; reduced cost of installation; centralized power and power back-up; and centralized security and management.

Several patents addressed to the issue of supplying power over an Ethernet based network exist including: U.S. Pat. No. 6,473,608 issued to Lehr et al.; and U.S. Pat. No. 6,643,566 issued to Lehr et al.; the contents of all of which are incorporated herein by reference.

The IEEE 802.3af-2003 standard, whose contents are incorporated herein by reference, is addressed to powering remote devices over an Ethernet based network. The above standard is limited to a powered device (PD) having a maximum power requirement during operation of 12.95 watts. Power can be delivered to the PD either directly from the switch/hub known as an endpoint power sourcing equipment (PSE) or alternatively via a midspan PSE. In either case power is delivered over a set of two twisted wire pairs.

The above mentioned standard defines certain electrical requirements applicable to normal powering, i.e. steady state operation, and separate limits for a start up phase. In particular, at Table 33-5 of the above standard, an output current limit during the startup phase, denoted IInrush, is defined separately from a maximum output current in normal powering mode, denoted Iport—max. The startup phase is characterized by the initial charging of an input capacitor of the PD, which presents an effective short circuit across the PSE at startup. At the end of the startup phase, the input capacitor of the PD is effectively charged.

A PD according to the above mentioned specification exhibits certain characteristics including polarity independence, a detection resistance, an optional classification functionality, a minimum input capacitance, and a minimum turn on voltage. In the event of a PD input capacitance being greater than or equal to 180 μF, the PD is further operative to control the inrush current during startup mode so as to ensure a maximum Iinrushof 400 mA. After detection and optional classification, the PD is not to close an isolating switch placing the input capacitance and load across the PSE until a minimum turn on voltage is detected by the PD.

The IEEE 802.3 at DTE Power Enhancements Task Force is in the process of developing a standard exhibiting higher power limits than the above IEEE 802.3af-2003 standard. It is anticipated that an increased operating power will be supported over wire pairs during normal powering mode, i.e. once the startup phase has completed. It is further anticipated that little, if any change, is to be made to the current limits of the startup phase, i.e. IInrush, which is set at limits significantly lower than the anticipated normal powering mode current. Thus, before a PD under the IEEE 802.3 at proposed standard can draw increased current, it must first ensure that the startup phase has been completed, and must further ensure that the PSE is aware of the end of the startup phase.

For example, in the event that the PD determines that the startup phase has completed while the PSE is still in the startup phase, the PD will attempt to draw increased current, consonant with the normal powering mode, while the PSE exhibits current limit IInrush. Such a condition will prevent proper operation of the PD, and may further result in increased stress at the PSE. A simple solution is to require a timer at the PD, which prevents the end of the startup phase from being determined before the expiration of a predetermined time period. A similar timer, with a slightly shorter predetermined time period, at the PSE would thus ensure that normal powering mode is achieved without being subject to IInrush. Unfortunately, such a requirement adds cost, requiring timers at both the PD and PSE.

What is needed, and not supplied by the prior art, is a means for determining, at the PSE, the end of the startup phase occurring at the PD.

SUMMARY OF THE INVENTION

According to certain embodiments of the present invention, a PSE is configured to determine the end of the start up phase at the PD responsive to a condition of the voltage at the PSE output.

In one particular embodiment, the end of the startup phase is determined at the PSE responsive to a PSE output voltage within a predetermined range of the PSE input voltage. In another particular embodiment, the end of the startup phase is determined at the PSE responsive to the voltage drop across the PSE current limiter, or the PSE current limiter and switch, being lower than a predetermined maximum. In yet another particular embodiment, the end of the startup phase is determined at the PSE responsive to the absolute value of the rate of change of the PSE output voltage being lower than a predetermined value, preferably for a predetermined amount of time. In yet another particular embodiment, the end of the startup phase is determined at the PSE responsive to the absolute value of the rate of change of the voltage drop across the PSE current limiter, or the PSE current limiter and switch, being lower than a predetermined value, preferably for a predetermined amount of time.

In one embodiment a power sourcing equipment is provided comprising: a voltage sensor; a control circuitry in communication with the voltage sensor; and a current limiter responsive to the control circuitry and operative to set a first current limit associated with a startup phase and a second current limit associated with a normal powering mode, wherein the control circuitry is operative responsive to a voltage condition sensed by the voltage sensor to set the current limit of the current limiter to one of the first current limit and the second current limit.

In one further embodiment the voltage sensor is arranged to sense a voltage associated with the output of the power sourcing equipment, and wherein the voltage condition is a predetermined minimum voltage. In one yet further embodiment, the predetermined minimum voltage is a predetermined maximum voltage drop from an input voltage.

In one further embodiment the voltage sensor is arranged to sense a voltage associated with the output of the power sourcing equipment, and wherein the voltage condition is a rate of change of the sensed output voltage whose absolute value is less than a predetermined value. In one yet further embodiment the rate of change of the absolute value less than the predetermined value is maintained for a predetermined time.

In one further embodiment the voltage sensor is arranged to sense a voltage drop associated with the current limiter, and wherein the voltage condition is a voltage drop less than a predetermined value. In one yet further embodiment the sensed voltage drop associated with the current limiter is one of the voltage drop across the current limiter and the voltage drop across the combination of the current limiter and an electronically controlled switch of the power sourcing equipment.

In one further embodiment the voltage sensor is arranged to sense a voltage drop associated with the current limiter, and wherein the voltage condition is a rate of change of the sensed voltage drop whose absolute value is less than a predetermined value. In one yet further embodiment the sensed voltage drop associated with the current limiting functionality is one of the voltage drop across the current limiter and the voltage drop across the combination of the current limiter and an electronically controlled switch of the power sourcing equipment. In one yet further embodiment, the rate of change of the absolute value less than the predetermined value is maintained for a predetermined time.

In one further embodiment the current limiter comprises a programmable current limiter. In another further embodiment the current limiter comprises a threshold current limiter.

Independently, in one embodiment a method of powering is provided, the method of powering comprising: providing a power source; providing power from the provided power source at a first current limit, the first current limit associated with a startup phase; sensing a voltage associated with the provided power source; and providing, responsive to a condition of the sensed voltage, power from the power source at a second current limit, the second current limit associated with a normal powering mode.

In one further embodiment the sensed voltage is a voltage associated with an output of the provided power source, and wherein the voltage condition is a predetermined minimum output voltage of the provided power source. In one yet further embodiment the predetermined minimum output voltage is a predetermined maximum voltage drop from an input voltage to the provided power source.

In one further embodiment the sensed voltage is a voltage associated with an output of the provided power source, and wherein the voltage condition is a rate of change of the sensed voltage whose absolute value is less than a predetermined value. In one yet further embodiment the rate of change of the absolute value less than the predetermined value is maintained for a predetermined time.

In one further embodiment the sensed voltage is a voltage drop associated with a current limiting functionality providing the first current limit, and wherein the voltage condition is a voltage drop less than a predetermined value. In one yet further embodiment the sensed voltage drop associated with the current limiting functionality is one of the voltage drop across the current limiting functionality and the voltage drop across the combination of the current limiting functionality and an electronically controlled switch of the provided power source.

In one further embodiment, the sensed voltage is a voltage drop associated with a current limiting functionality providing the first current limit, and wherein the voltage condition is a rate of change of the sensed voltage drop whose absolute value is less than a predetermined value. In one yet further embodiment the sensed voltage drop associated with the current limiting functionality is one of the voltage drop across the current limiting functionality and the voltage drop across the combination of the current limiting functionality and an electronically controlled switch of the provided power source. In one yet further embodiment, the rate of change whose absolute value is less than the predetermined value is maintained for a predetermined time.

Independently, in one embodiment a power sourcing equipment is provided comprising: a voltage sensor; a control circuitry in communication with the voltage sensor; and a current limiting functionality responsive to the control circuitry and operative to set a first current limit associated with a startup phase and a second current limit associated with a normal powering mode, wherein the control circuitry is operative responsive to a voltage condition sensed by the voltage sensor to set the current limit of the current limiting functionality to one of the first current limit and the second current limit. In one further embodiment the current limiting functionality comprises a threshold current limiter operative to allow the flow of current less than the set threshold current limit without appreciable resistance, and to limit the current so as to not exceed the set threshold current limit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present embodiments enable a PSE configured to determine the end of the start up phase at the PD responsive to a condition of the voltage at the PSE output.

In one particular embodiment, the end of the startup phase is determined at the PSE responsive to a PSE output voltage within a predetermined range of the PSE input voltage. In another particular embodiment, the end of the startup phase is determined at the PSE responsive to the voltage drop across the PSE current limiter, or the PSE current limiter and switch, being lower than a predetermined maximum. In yet another particular embodiment, the end of the startup phase is determined at the PSE responsive to the rate of change of the PSE output voltage being lower than a predetermined value, preferably for a predetermined amount of time. In yet another particular embodiment, the end of the startup phase is determined at the PSE responsive to the absolute value of the rate of change of the voltage drop across the PSE current limiter, or the PSE current limiter and switch, being lower than a predetermined value, preferably for a predetermined amount of time.

The invention is being described as an Ethernet based network, with a powered device being connected thereto, however this is not meant to be limiting in any way. The invention is equally applicable to any arrangement in which power is supplied to a target device, where it is important to identify the end of the start up phase.

FIG. 1Aillustrates a high level block diagram of a system10providing remote powering from an endpoint PSE and arranged to determine the end of the start up phase of the PD at the PSE responsive to a condition of the output voltage, in accordance with certain embodiments. System10comprises: a switch/hub equipment30comprising a first and a second data pair20, a PSE40comprising a control circuitry42, a voltage sensor44, an electronically controlled switch46, a current limiting functionality47, a detection functionality48and a classification functionality49, and a first and a second data transformers50; a first, a second, a third and a fourth twisted wire pair connection60; and a powered end station70comprising a PD interface80preferably exhibiting a diode bridge85, a first and a second data transformer55, a first and a second data pair25, an isolating switch90, and a PD operating circuitry100comprising a DC/DC converter105and an input capacitor110.

A positive power source lead of an input voltage, denoted VIN, is connected to a first input of voltage sensor44and the center tap of the secondary of first data transformer50. A negative power source lead of input voltage VIN is connected to a first end of current limiting functionality47, and a second end of current limiting functionality47is connected to a first end of electronically controlled switch46. A second end of electronically controlled switch46is connected to a return input of voltage sensor44and the center tap of the secondary of second data transformer50. A first output of control circuitry42is connected to the control input of electronically controlled switch46, a second output of control circuitry42is connected to the control input of current limiting functionality47, and the output of voltage sensor44is connected to an input of control circuitry42. Each of detection functionality48and classification functionality49are in communication with control circuitry42. The primary of first and second data transformers50are each connected to communication devices, represented by first and second data pairs20. The output leads of the secondary of first and second data transformers50are each connected to a first end of first and second twisted wire pair connections60, respectively. The second end of first and second twisted wire pair connections60, are respectively connected to the primary of first and second data transformers55located within powered end station70. The center taps of the primary of first and second data transformer55are connected respectively to a power input and return of PD interface80. In a preferred embodiment, first and second data transformers50are part of PSE40, and first and second data transformers55are part of PD interface80. PD interface80preferably comprises diode bridge85arrange to ensure proper operation of powered end station70irrespective of the polarity of the connection to PSE40. The output of PD interface80is connected via isolating switch90controlled by PD interface80to PD operating circuitry100. The input to PD operating circuitry100is connected to DC/DC converter105and appears across input capacitor110. The secondary of first and second data transformers55are each connected to communication devices, represented by first and second data pairs25, respectively. Powered end station70is alternatively denoted PD70.

Current limiting functionality47and electronically controlled switch46are illustrated as separate elements, however this is not meant to be limiting in any way. In an exemplary embodiment current limiting functionality47and electronically controlled switch46are implemented as a single FET and comparator circuit as described in U.S. Pat. No. 6,473,608 to Lehr et al incorporated by reference above. In one embodiment, current limiting functionality47is implemented by a current limiter, particularly a programmable current limiter. Current limiting functionality47is in one embodiment a threshold current limiter, operative to allow the flow of current less than the threshold level without appreciable resistance, and to effectively limit the current so as to not exceed the threshold level.

In operation, control circuitry42of PSE40detects powered end station70via detection functionality48, optionally classifies powered end station70via classification functionality49, and if power is available, supplies power over first and second twisted wire pair connection60to powered end station70, by closing electronically controlled switch46thus supplying both power and data over first and second twisted wire pair connections60. Third and fourth twisted wire pair connections60are not utilized, and are thus available as spare connections. Third and fourth twisted wire pair connections60are shown connected to PD interface80in order to allow operation alternatively over unused third and fourth twisted wire pair connections60.

PD interface80functions to present a signature resistance to PSE40, optionally present a classification current, and upon detection of a sufficient operating voltage, irrespective of polarity, to close isolating switch90thereby powering PD operating circuitry100. DC/DC converter105is operative to convert the power received from PD interface80to an appropriate voltage to power PD operating circuitry100and exhibits input capacitor110across its input. Thus, upon the closing of isolating switch90, input capacitor110is presented to PSE40through diode bridge85, first and second data transformers55and first and second twisted wire pair connections60.

Control circuitry42is further operative prior to closing electronically controlled switch to set current limiting functionality47to a first value, denoted I_INRUSH, and to receive an indication of the output port voltage, denoted VOUT, via voltage sensor44periodically during the start up phase. In one particular embodiment a voltage measurement of VOUT is taken every 2 μseconds after closing electronically controlled switch46until the end of the start up phase.

Control circuitry42is further operative to determine a voltage condition of VOUT indicative of the end of the startup phase responsive to the periodic indications of voltage sensor44. In one particular embodiment, the voltage condition of VOUT is a minimum output voltage indicative that input capacitor110has charged to a nominal value. In another particular embodiment, the voltage condition is an output voltage within a predetermined range of the input voltage, VIN, indicating that the voltage drop across the combination of current limiting functionality47and electronically controlled switch46is less than a predetermined maximum. It is to be understood that a voltage drop across the combination of current limiting functionality47and electronically controlled switch46less than the predetermined maximum is indicative that current flow is less than I_INRUSH, thus indicative of the end of the startup phase. In yet another particular embodiment the rate of change of the output voltage, i.e. dv/dt, is determined, and the end of the startup phase is indicated by the absolute value of the rate of change of the output voltage being less than a predetermined value. Preferably, the end of the startup phase is determined after the absolute value of the rate of change of the output voltage is less than the predetermined value for a predetermined time period, so as to avoid false results.

Subsequent to control circuitry42determining the end of the startup phase, control circuitry42is further operative to set current limiting functionality47to a current limit associated with a normal powering mode. In certain embodiments, the current limit associated with the normal powering mode is a function of the classification obtained by classification functionality49. In the event of power exceeding 15.4 Watts, the current limit associated with the normal powering mode is greater than I_INRUSH. As described above, in one embodiment the current limit is a current threshold limit, and current less than the threshold level flows without appreciable resistance from current limiting functionality47, with current effectively limited so as to not exceed the threshold level. In such an embodiment, current limiting functionality47functions as a current governor.

FIG. 1Billustrates a high level block diagram of a system150providing remote powering from an endpoint PSE and arranged to determine the end of the start up phase of the PD at the PSE responsive to a condition of the voltage drop across current limiting functionality47, in accordance with certain embodiments. System150is in all respects similar to system10, with the exception that voltage sensor44is arranged to provide an indication of the voltage drop across either current limiting functionality47or the combination of current limiting functionality47and electronically controlled switch46.

In operation, control circuitry42of PSE40detects powered end station70via detection functionality48, optionally classifies powered end station70via classification functionality49, and if power is available, supplies power over first and second twisted wire pair connection60to powered end station70, by closing electronically controlled switch46thus supplying both power and data over first and second twisted wire pair connections60. Third and fourth twisted wire pair connections60are not utilized, and are thus available as spare connections. Third and fourth twisted wire pair connections60are shown connected to PD interface80in order to allow operation alternatively over unused third and fourth twisted wire pair connections60.

PD interface80functions to present a signature resistance to PSE40, optionally present a classification current, and upon detection of a sufficient operating voltage, irrespective of polarity, to close isolating switch90thereby powering PD operating circuitry100. DC/DC converter105is operative to convert the power received from PD interface80to an appropriate voltage to power PD operating circuitry100and exhibits input capacitor110across its input. Thus, upon the closing of isolating switch90, input capacitor110is presented to PSE40through diode bridge85, first and second data transformers55and first and second twisted wire pair connections60.

Control circuitry42is further operative prior to closing electronically controlled switch46to set current limiting functionality47to a first value, denoted I_INRUSH, and to receive an indication of the voltage drop across current limiting functionality47, or the combination of current limiting functionality47and electronically controlled switch46periodically during the start up phase. In one particular embodiment a voltage measurement is taken every 2μ seconds after closing electronically controlled switch46until the end of the start up phase.

Control circuitry42is further operative to determine a voltage condition of the voltage drop across one of current limiting functionality47and the combination of current limiting functionality47and electronically controlled switch46indicative of the end of the startup phase responsive to the periodic indications of voltage sensor44. In one particular embodiment, the voltage condition is a voltage drop less than a predetermined value, indicative that input capacitor110has charged to a nominal value and is no longer attempting to draw current substantially in excess of I_INRUSH. In another particular embodiment the rate of change of the voltage drop across one of current limiting functionality47and the combination of current limiting functionality47and electronically controlled switch46, i.e. dv/dt, is determined, and the end of the startup phase is indicated by the absolute value of the rate of change of the voltage drop being less than a predetermined value. Preferably, the end of the startup phase is determined after the absolute value of the rate of change of the voltage drop is less than the predetermined value for a predetermined time period, so as to avoid false results.

FIG. 2Aillustrates a timing diagram of voltages of system10ofFIG. 1A, from beginning of powering denoted T_ON, through the end of the startup phase, denoted T1, according to certain embodiments, in which the x-axis represents time and the y-axis represents PSE output port voltage, VOUT.FIG. 2Billustrates a timing diagram of current limits applicable to current drawn from PSE40corresponding to the voltages ofFIG. 2A, according to certain embodiments.

At time T_ON, electronically controlled switch46is closed and the output port voltage of PSE40begins to rise, as shown by waveform300, as input capacitor110is charged. The current limit of current limiting functionality47is set to I_INRUSH. Waveform300continues to rise monotonically, until it rises to VNOM, defined as a predetermined voltage ΔV below the input voltage, VIN. At point310, corresponding to time T1, the output port voltage has reached VNOM, and control circuitry42determines the end of the startup phase, T1. Alternatively, as shown by an area320, the rate of change of VOUT is monitored. When the absolute value of the rate of change of VOUT is less than a predetermined value, preferably for a predetermined amount of time, control circuitry42determines the end of the startup phase, T1. Control circuitry42, responsive to the determined end of the startup phase, then changes the setting of current limiting functionality47, to I_NORMAL, indicative of the normal powering mode. As indicated above, in one embodiment current limiting functionality47is a threshold current limiter, operative to allow the flow of current less than the set threshold level without appreciable resistance, and to effectively limit the current so as to not exceed the set threshold level. n such an embodiment, current limiting functionality47functions as a current governor.

FIG. 3Aillustrates a timing diagram of voltages of system150ofFIG. 1B, from beginning of powering denoted T_ON, through the end of the startup phase, denoted T1, according to certain embodiments, in which the x-axis represents time and the y-axis represents the voltage drop across current limiting functionality47.FIG. 3Billustrates a timing diagram of current limits applicable to current drawn from PSE40, through current limiting functionality47, corresponding to the voltages ofFIG. 2A, according to certain embodiments.

At time T_ON, electronically controlled switch46is closed and the voltage drop across one of current limiting functionally47and the combination of current limiting functionality47and electronically controlled switch46begins to fall, as shown by waveform400, as input capacitor110is charged and the voltage thereon rises towards VIN. The current limit of current limiting functionality47is set to I_INRUSH. Waveform400continues to fall monotonically, until it falls to VMIN, defined as a predetermined maximum voltage drop across one of current limiting functionality47and the combination of current limiting functionality47and electronically controlled switch46, indicative that the current attempted to be drawn through current limiting functionality47is no longer substantially above I_INRUSH. At point410, the voltage drop is below VMIN, and control circuitry42determines the end of the startup phase, T1. Alternatively, as shown by an area420, the rate of change of the voltage drop across one of current limiting functionality47and the combination of current limiting functionality47and electronically controlled switch46is monitored. When the absolute value of the rate of change of the voltage drop across one of current limiting functionality47and the combination of current limiting functionality47and electronically controlled switch46is less than a predetermined value, preferably for a predetermined amount of time, control circuitry42determines the end of the startup phase, T1. Control circuitry42, responsive to the determined end of the startup phase, then changes the setting of current limiting functionality47, to I_NORMAL, indicative of the normal powering mode. As indicated above, in one embodiment current limiting functionality47is a threshold current limiter, operative to allow the flow of current less than the set threshold level without appreciable resistance, and to effectively limit the current so as to not exceed the set threshold level. In such an embodiment, current limiting functionality47functions as a current governor.

FIG. 4illustrates a high level flow chart of the operation of PSE40ofFIG. 1Ato determine the end of the startup phase and enable powering of the normal operating mode at a different current limit, according to certain embodiments. In stage1000, PSE40is provided, preferably receiving an input voltage, VIN, and arranged to supply a device having an input capacitor exhibiting an inrush current, such as input capacitor110, thereby exhibiting a startup phase.

In stage1010, a current limiting functionality of the provided power source of stage1000is set to inrush current limit, I_INRUSH. In one embodiment, the current limiting functionality is a programmable current limiter, as described above in relation to current limiting functionality47. In another embodiment, the current limiting functionality is a threshold current limiting functionality. In yet another embodiment, the current limiting functionality is a programmable current limiter exhibiting a threshold current limiting functionality. In stage1020, a voltage associated with the power source of stage1000is monitored. Optionally the voltage monitored is the output port voltage, VOUT, of the power source of stage1000.

In stage1030, the end of the startup phase is determined responsive to a condition of the monitored voltage of stage1020. In one embodiment, the condition of the monitored voltage is a predetermined minimum output voltage, VOUT. In another embodiment, the condition of the monitored voltage is a predetermined maximum voltage drop from an input voltage. In yet another embodiment, the condition of the monitored voltage is a rate of change whose absolute value is less than a predetermined value, preferably maintained for a predetermined time period.

In stage1040, responsive the determined end of the startup phase of stage1030, current limiting functionality47is set to I_NORMAL, i.e. a current limit associated with a normal powering mode.

FIG. 5illustrates a high level flow chart of the operation of PSE40ofFIG. 1Bto determine the end of the startup phase and enable powering of the normal operating mode at a different current limit, according to certain embodiments. In stage1000, PSE40is provided, preferably receiving an input voltage, VIN, and arranged to supply a device having an inrush current, such as input capacitor110, thereby exhibiting a startup phase.

In stage2010, a current limiting functionality of the provided power source of stage2000is set to inrush current limit, I_INRUSH. In one embodiment, the current limiting functionality is a programmable current limiter, as described above in relation to current limiting functionality47. In another embodiment, the current limiting functionality is a threshold current limiting functionality. In yet another embodiment, the current limiting functionality is a programmable current limiter exhibiting a threshold current limiting functionality. In stage2020, a voltage associated with the power source of stage2000is monitored. Optionally, the voltage monitored is one of: the voltage drop across current limiting functionality47of the power source of stage2000; and the voltage drop across the combination of current limiting functionality47and electronically controlled switch46of the power source of stage2000.

In stage2030, the end of the startup phase is determined responsive to a condition of the monitored voltage of stage2020. In one embodiment, the condition of the monitored voltage is a voltage drop less than a predetermined value. In another embodiment, the condition of the monitored voltage drop is a rate of change whose absolute value is less than a predetermined value, preferably maintained for a predetermined time period.

In stage2040, responsive to the determined end of the startup phase of stage2030, current limiting functionality47is set to I_NORMAL, i.e. a current limit associated with a normal powering mode.

Thus the present embodiments enable a PSE configured to determine the end of the start up phase at the PD responsive to a condition of the voltage at the PSE output.

It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. In particular, the invention has been described with an identification of each powered device by a class, however this is not meant to be limiting in any way. In an alternative embodiment, all powered devices are treated equally, and thus the identification of class with its associated power requirements is not required.