BONDING STRUCTURE USING TWO OXIDE LAYERS WITH DIFFERENT STRESS LEVELS, AND RELATED METHOD

A bonding structure for a semiconductor substrate and related method are provided. The bonding structure includes a first oxide layer on the semiconductor substrate, and a second oxide layer on the first oxide layer, the second oxide layer for bonding to another structure. The second oxide layer has a higher stress level than the first oxide layer, and the second oxide layer is thinner than the first oxide layer. The second oxide layer may also have a higher density than the first oxide layer. The bonding structure can be used to bond chips to wafer or wafer to wafer and provides a greater bond strength than just a thick oxide layer.

BACKGROUND

The present disclosure relates to integrated circuit (IC) fabrication, and more particularly, to a structure and method of bonding structures, such as chips to wafers or wafer to wafers, using two oxide layers to provide improved bond strength.

Chip to wafer and wafer to wafer bonding has the potential to improve performance of a wide variety of silicon technologies. Achieving a bond with sufficient bond strength with low stress and high density thin films is a challenge. One approach forms a thick oxide (e.g., 1000-15000 nanometers) at a low deposition temperature for bonding with another wafer. The low deposition temperature prevents damage to devices on the substrate but provides a low density and low stress layer with insufficient bond strength. Where the thick layer is made denser, the wafer bond strength is increased, but the stress is unacceptably high. Other approaches treat the surface of the wafer with ammonia to enhance the bond strength. Additional approaches have tried bonding at elevated temperatures and applying pressure or using a water plasma treatment on the surface. These approaches do not provide sufficient bond strength, and/or can damage preexisting devices.

SUMMARY

All aspects, examples and features mentioned below can be combined in any technically possible way.

An aspect of the disclosure provides a bonding structure for a semiconductor substrate, the bonding structure comprising: a first oxide layer on the semiconductor substrate; and a second oxide layer on the first oxide layer, the second oxide layer for bonding to another structure, wherein the second oxide layer has a higher stress level than the first oxide layer, and the second oxide layer is thinner than the first oxide layer.

Another aspect of the disclosure includes any of the preceding aspects, and the second oxide layer has a higher density than the first oxide layer.

An aspect includes a semiconductor device, comprising: a semiconductor substrate; and a first bonding structure between the semiconductor substrate and a first structure, the first bonding structure including: a first oxide layer on the semiconductor substrate, and a second oxide layer on the first oxide layer coupled to the first structure, wherein the second oxide layer has a higher stress level than the first oxide layer, and the second oxide layer is thinner than the first oxide layer.

Another aspect of the disclosure includes any of the preceding aspects, and the second oxide layer has a higher density than the first oxide layer.

Another aspect of the disclosure includes any of the preceding aspects, and the first oxide layer has a density in a range of 2.31-2.37 grams per cubic centimeter (g/cm3), and the second oxide layer has a density in a range of 2.43-2.52 g/cm3.

Another aspect of the disclosure includes any of the preceding aspects, and further comprising a second bonding structure for bonding a second structure to the first structure, wherein the second bonding structure includes: a third oxide layer on the first structure, and a fourth oxide layer on the third oxide layer, wherein the fourth oxide layer has a higher density and a higher stress level than the third oxide layer, and the fourth oxide layer is thinner than the third oxide layer.

Another aspect of the disclosure includes any of the preceding aspects, and the first oxide layer has a thickness in a range of 5000 to 15000 nanometers (nm), and the second oxide layer has a thickness in a range of 250 to 750 nm.

Another aspect of the disclosure includes any of the preceding aspects, and the first oxide layer has a compressive stress in a range of 70-100 MegaPascals (MPa), and the second oxide layer has a compressive stress in a range of 300-350 MPa.

Another aspect of the disclosure includes any of the preceding aspects, and at least one of the first oxide layer and the second oxide layer has a surface having a root mean square roughness in a range of 0.1 to 0.5 nanometers.

Another aspect of the disclosure includes any of the preceding aspects, and a bond strength between the second oxide layer and the first structure is at least 1.0 Joules per square meter (J/m2).

An aspect of the disclosure includes a method, comprising: forming a first bonding structure, the forming including: forming a first oxide layer on a first structure; forming a second oxide layer on the first oxide layer, wherein the second oxide layer has a higher stress level than the first oxide layer, and the second oxide layer is thinner than the first oxide layer; and bonding the second oxide layer to a second structure.

Another aspect of the disclosure includes any of the preceding aspects, and the second oxide layer has a higher density than the first oxide layer.

Another aspect of the disclosure includes any of the preceding aspects, and the first oxide layer has a density in a range of 2.31-2.37 grams per cubic centimeter (g/cm3), and the second oxide layer has a density in a range of 2.43-2.52 g/cm3.

Another aspect of the disclosure includes any of the preceding aspects, and forming the first oxide layer and forming the second oxide layer each occur at a temperature of less than 300° Celsius (° C.).

Another aspect of the disclosure includes any of the preceding aspects, and forming the first oxide layer includes depositing the first oxide layer to a thickness in a range of 5 to 15 μm, and wherein forming the second oxide layer includes depositing the second oxide layer to a thickness in a range of 0.25 to 0.75 μm.

Another aspect of the disclosure includes any of the preceding aspects, and the first oxide layer has a compressive stress in a range of 70-100 MPa, and the second oxide layer has a compressive stress in a range of 300-350 MPa.

Another aspect of the disclosure includes any of the preceding aspects, and at least one of forming the first oxide layer and forming the second oxide layer includes planarizing a surface of the respective oxide layer to have a root mean square roughness in a range of 0.1 to 0.5 nanometers.

Another aspect of the disclosure includes any of the preceding aspects, and a bond strength between the second oxide layer and the first structure is at least 1.6 J/m2.

Another aspect of the disclosure includes any of the preceding aspects, and further comprising: forming a second bonding structure on the second structure, including: forming a third oxide layer on the second structure, and forming a fourth oxide layer on the third oxide layer, wherein the fourth oxide layer has a higher density and a higher stress level than the third oxide layer, and the fourth oxide layer is thinner than the third oxide layer; and bonding a third structure to the fourth oxide layer.

Another aspect of the disclosure includes any of the preceding aspects, and forming the third oxide layer includes depositing the third oxide layer to a thickness in a range of 5 to 15 μm, and forming the fourth oxide layer includes depositing the fourth oxide layer to a thickness in a range of 0.25 to 0.75 μm.

Two or more aspects described in this disclosure, including those described in this summary section, may be combined to form implementations not specifically described herein.

DETAILED DESCRIPTION

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

Embodiments of the disclosure include a bonding structure for a semiconductor substrate and a related method. The bonding structure includes a first oxide layer on the semiconductor substrate, and another, second oxide layer on the first oxide layer, where the second oxide layer bonds to another structure, e.g., another substrate (wafer) or chips. The bonding structure can be used to bond chips to wafer, or wafer to wafer, with or without conductor-to-conductor features. In any event, the second oxide layer has a higher stress level than the first oxide layer, and the second oxide layer is thinner than the first oxide layer. The second oxide layer may also have a higher density than the first oxide layer. One or more of the bonding structures can be used in a single device. The bonding structure provides a greater bond strength than just a thick oxide layer, e.g., at least 1.0 Joules per square meter (J/m2) compared to about 0.6 J/m2of a conventional thick oxide bonding layer. In other embodiments, the bond strength may be at least 1.6 J/m2. The bonding structure is free of voids therein. The process to form the bonding structure does not require tool modifications. Each oxide forming step uses low temperatures that do not damage pre-existing devices. While the disclosure will be described relative to oxide layers, the teachings of the disclosure are equally applicable to layers of silicon carbo-nitride (SiCN).

FIGS.1-2show cross-sectional views of a method for forming a first bonding structure100(FIG.2), according to embodiments of the disclosure.FIGS.1-2show forming of first bonding structure100in a generic manner that is applicable to a variety of applications. As will be described further herein, first bonding structure100(hereafter “bonding structure100”) can be used in a number of semiconductor fabrication situations to increase bond strength in, for example, chips to wafer and/or wafer to wafer settings.

FIG.1shows forming a first oxide layer110on a first structure112. In the example shown, first structure112may include a semiconductor substrate114, which may be referred to as a handle wafer in some cases. As used herein, any semiconductor substrate (e.g., substrate114) may include, for example, a silicon or silicon-based substrate (e.g., a silicon carbide (SiC) substrate or other material that support epitaxial growth of semiconductor), a sapphire substrate, or any other suitable substrate for a III-V semiconductor device. Those skilled in the art will recognize that a III-V semiconductor refers to a compound obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorous (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). The substrate may include or be devoid of devices (not shown), e.g., transistors or related passive devices such as capacitors, resistors, etc. The terms ‘wafer’ and ‘substrate’ may be used interchangeably herein.

First oxide layer110may be formed using, for example, silane-based (SiH4) plasma enhanced chemical vapor deposition (PECVD), creating a silicon oxide (SiOx). A gas ratio of silicon hydride (SiH4) to nitrous oxide (N2O) of the PECVD may be in a range of, for example, 1:25 to 1:35. In any event, the temperature of the PECVD is less than 300° Celsius (° C.), which protects any preexisting devices, e.g., transistors in semiconductor substrate114, from thermally induced damage. First oxide layer110may be deposited to a thickness in a range of 5000 to 15000 nanometers (nm). First oxide layer110deposition can occur at a rate in a range of, for example, 350-500 nanometers per minute (nm/min). When complete, first oxide layer110may have a density in a range of 2.31-2.37 grams per cubic centimeter (g/cm3). First oxide layer110has a relatively low compressive stress in a range of, for example, 70-100 MegaPascals (MPa). First oxide layer110may have a dielectric constant in a range of, for example, 4.7 to 6.0.

As part of its forming, first oxide layer110may be planarized using any now known or later developed planarization process such as but not limited to chemical mechanical polishing (CMP) (indicated by curved arrow). In certain embodiments, a surface of first oxide layer110has a root mean square (RMS) roughness in a range of 0.1-0.5 nanometers (nm).

FIG.2shows forming a second oxide layer120on first oxide layer110, creating bonding structure100. As will be described, second oxide layer120has a higher stress level than first oxide layer110. For example, in contrast to first oxide layer110, second oxide layer120may have a relatively high compressive stress in a range of, for example, 300-350 MPa. Second oxide layer120may also have a higher density than first oxide layer110. Further, as shown, second oxide layer120is thinner than first oxide layer110, e.g., T2<T1. Second oxide layer120may be deposited to a thickness in a range of 0.25 to 0.75 μm. Second oxide layer120may be formed using, for example, silane-based (SiH4) PECVD, creating a silicon oxide (SiOx).

Forming second oxide layer120uses a higher concentration of the silane than forming first oxide layer110. In addition, a gas ratio of silicon hydride (SiH4) to nitrous oxide (N2O) of the PECVD may be in a range of, for example, 1:200 to 1:250. In any event, the temperature of the PECVD for second oxide layer120is less than 300° C., which continues to protect any preexisting devices, e.g., in semiconductor substrate114, from thermally induced damage. Second oxide layer120deposition can occur at a rate in a range of, for example, 800-1000 Å/min. The duration of depositing second oxide layer120thus could be longer than that first oxide layer110even though layer120is thinner than layer110. When complete, second oxide layer120may have a density in a range of 2.43-2.52 g/cm3. Second oxide layer120may have a dielectric constant in a range of, for example, 4.0 to 4.5. Due to the higher density in second oxide layer120, when second oxide layer120is used to bond to another structure, a bond strength between second oxide layer120and the bonded structure is higher than conventionally possible with a single thick oxide layer. In certain embodiments, the bond strength may be at least 1.0 J/m2. In other embodiments, the bond strength may be at least 1.6 J/m2. The bond strength of bond structure100is thus significantly stronger than that possible with a conventional single thick oxide layer bonding structure, which typically has a bond strength of about 0.6 J/m2. Bonding structure100may include any now known or later developed alignment marks (not shown) for aligning other structure thereto. As will be described, hybrid bond pads may be formed through bonding structure100.

As part of its forming, second oxide layer120may be planarized using any now known or later developed planarization process such as but not limited to CMP (indicated by curved arrow). In certain embodiments, a surface of second oxide layer120has an RMS roughness in a range of 0.1-0.5 nm.

FIG.2shows bonding structure100for a semiconductor substrate114and a semiconductor device102, according to embodiments of the disclosure. Bonding structure100includes first oxide layer110on semiconductor substrate114and second oxide layer120on first oxide layer110. Second oxide layer120can be used to bond to another structure, e.g., as shown inFIG.3, a second structure130including IC chips132. Second oxide layer120has a higher stress level than first oxide layer110. For example, in contrast to first oxide layer110having compressive stress of, for example, 70-100 MPa, second oxide layer120may have a relatively high compressive stress in a range of, for example, 300-350 MPa. Second oxide layer120may also have a higher density than first oxide layer110. In addition, second oxide layer120is thinner than first oxide layer110. For example, first oxide layer110may have a thickness in a range of 5 to 15 μm, and second oxide layer120may have a thickness in a range of 0.25 to 0.75 μm.

FIGS.3-15show cross-sectional views of various ways to use bonding structure100, according to embodiments of the disclosure.

FIGS.3-4show cross-sectional views of one way to use bonding structure100. Notably,FIG.3shows bonding second oxide layer120of bonding structure100to a second structure130. In this example, second structure130includes a plurality of integrated circuit (IC) chips132, each having a dielectric layer134(e.g., silicon oxide or silicon nitride) thereover, which may extend to various thicknesses. Second structure130can be provided in any now known or later developed manner for bonding to structure100, e.g., tape release, die on tape frame or die picked from die pack. Once in position, an anneal (curved arrows inFIG.3) can be carried out on structures100,130. As shown inFIG.4, a planarization (e.g., CMP) of dielectric layer134may then occur. Bonding structure100provides sufficient bond strength to prevent IC chips132removal during the planarization process.

FIGS.5-7show cross-sectional views of another way to use bond structure100.FIG.5shows forming a third oxide layer140over second structure130(as inFIG.4). Third oxide layer140may be formed using processes as described herein relative to first oxide layer110. Third oxide layer140may be formed using, for example, silane-based (SiH4) PECVD, creating a silicon oxide (SiOx). A gas ratio of silicon hydride (SiH2) to nitrous oxide (N2O) of the PECVD may be in a range of, for example, 1:25 to 1:35. In any event, the temperature of the PECVD is less than 300° C., which protects any preexisting devices such as IC chips132from thermal damage. Third oxide layer140may be deposited to a thickness in a range of 5 to 15 μm and may encapsulate IC chips132of second structure130. Third oxide layer140deposition can occur at a rate in a range of, for example, 3500-5000 Å/min. When complete, third oxide layer140may have a density in a range of 2.31-2.37 g/cm3. Third oxide layer140has a relatively low compressive stress in a range of, for example, 70-100 MPa. Third oxide layer140may have a dielectric constant in a range of, for example, 4.7 to 6.0. Once formed, third oxide layer140may be planarized (see planarizing and thinning indicated by dashed boxed inFIG.5) using any now known or later developed processes, e.g., CVD layer planarization and/or CMP.

As shown inFIG.5, in certain embodiments, a third structure150may then be bonded to third oxide layer140—see upper arrow inFIG.5. In the example shown, third structure150may include a semiconductor substrate152, which may include any form of integrated circuit devices and/or interconnect structures, e.g., additional transistors, metal wires and contacts, etc. Semiconductor substrate152may include any semiconductor material such as silicon, silicon germanium, silicon carbide, etc., and may include or be devoid of semiconductor devices (not shown). First structure112may then be removed using any now known or later developed technique, which may thin first oxide layer110.

FIG.6shows the structure after rotating second structure150, as inFIG.5, to be under bonding structure100.FIGS.6and7show bonding a fourth structure160to third structure150using bonding structure100. Here, first oxide layer110of bonding structure100bonds to fourth structure160. In the example shown, fourth structure160may include a substrate162, which may include, for example, any form of interconnect structures such as metal wires and contacts, etc.

Returning toFIG.5and with reference toFIGS.8-10, in another embodiment, a second bonding structure170(FIG.8) may be used with first bonding structure100.FIG.8shows forming second bonding structure170on second structure130(as inFIG.4). As described relative toFIG.5, the process includes forming third oxide layer140on second structure130. In contrast to theFIG.5embodiment, as shown inFIG.8, the process may also include forming a fourth oxide layer180on third oxide layer140. Fourth oxide layer180is formed as described relative to second oxide layer120. That is, fourth oxide layer180may be formed using, for example, silane-based (SiH4) PECVD, creating a silicon oxide (SiOx). Forming fourth oxide layer180uses a higher concentration of the silane than forming first or third oxide layers110,140. In addition, a gas ratio of silicon hydride (SiH2) to nitrous oxide (N2O) of the PECVD may be in a range of, for example, 1:20 to 1:25. In any event, the temperature of the PECVD for fourth oxide layer180is less than 300° C., which continues to protect any preexisting devices, e.g., IC chips132or other devices in first structure114from thermally induced damage. Fourth oxide layer180may be planarized as described relative to second oxide layer120, e.g., to a surface RMS roughness in a range of 0.1 to 0.5 nm.

Fourth oxide layer180has a higher stress level than third oxide layer140. For example, in contrast to third oxide layer140(and similar to second oxide layer120), fourth oxide layer180may have a relatively high compressive stress in a range of, for example, 300-350 MPa. Fourth oxide layer180may also have a higher density than third oxide layer140. Further, as shown, fourth oxide layer180is thinner than third oxide layer110(i.e., T3<T4). Fourth oxide layer180may be deposited to a thickness in a range of 0.25 to 0.75 μm. Fourth oxide layer180deposition can occur at a rate in a range of, for example, 800-1000 Å/min. The duration of depositing fourth oxide layer180thus could be longer than that of first and third oxide layers110,140even though layer180is thinner than layers110,140. When complete, fourth oxide layer180may have a density in a range of 2.43-2.52 g/cm3. Fourth oxide layer180may have a dielectric constant in a range of, for example, 4.0 to 4.5. Due to the higher stress in fourth oxide layer180, when fourth oxide layer180is used to bond to another structure, a bond strength between fourth oxide layer180and that structure is at least 1.0 J/m2. In other embodiments, the bond strength may be at least 1.6 J/m2. The bond strength of second bond structure170is thus significantly stronger than that possible with a conventional single thick oxide layer bonding structure, which typically has a bond strength of about 0.6 J/m2. Second bonding structure170may include any now known or later developed alignment marks (not shown) for aligning other structure thereto. Hybrid bond pads (not shown), as necessary, may be formed through second bonding structure170.

As shown inFIG.8, third structure150is bonded to second bonding structure170, and in particular, fourth oxide layer180. The bonding may include any now known or later developed process. First structure112may then be removed using any now known or later developed technique, which may thin first oxide layer110.

FIG.9shows the structure after rotating second structure150to be under first bonding structure100(and second bonding structure170).FIGS.9and10show bonding a fourth structure160to third structure150using first bonding structure100. Here, first oxide layer110bonds to fourth structure160. In the example shown, fourth structure160may include a substrate162, which may include any form of interconnect structures, e.g., metal wires and contacts, etc. The bonding may include any now known or later developed process.

FIG.10also shows semiconductor device102including second bonding structure170for bonding fourth structure160to another structure, e.g., IC chips132of second structure and/or third structure150. As noted, second bonding structure170includes third oxide layer140on structure150, and fourth oxide layer180on third oxide layer140. As described, fourth oxide layer180has a higher density and a higher stress level than third oxide layer140, and fourth oxide layer180is thinner than third oxide layer140. A bond strength of second bonding structure170between fourth oxide layer180and structure150is at least 1.0 Joules per square meter (J/m2). In other embodiments, the bond strength may be at least 1.6 J/m2.

Referring toFIGS.11-15, cross-sectional views of alternative embodiments and/or applications of bonding structure(s)100,170, are shown. These embodiments include various processes, some of which may be referred to hybrid bond processes in which another device, wafer, or IC chips, are bonded with a direct conductor-to-conductor connection.

FIG.11shows a bonding process similar to that ofFIG.6with face-to-back wafer-to-wafer hybrid bonding. InFIG.11, structure100, including oxide layers110and120, is formed on structure200(e.g., a silicon carrier) including through silicon vias (TSVs)202on the back side(s) of devices204and related interconnect layers206therein. Oxide layers110,120may be formed as described herein after TSV202reveal using, for example, a grinding, etch and planarization process. Hybrid bond pads208would then be formed on TSVs202in any now known or later developed manner, e.g., single copper damascene process and planarization. Structure200would then be bonded to a front side of another structure210including similar, aligned hybrid bond pads212. Hybrid bond pads208,212form a direct conductor-to-conductor (e.g., Cu-Cu) hybrid bond in a known fashion. Bond structure100, however, provides a stronger bond strength between structures200,210, as described herein. While shown on only one structure200, bond structure100may be formed on both structures200,210.

FIG.12shows a bonding process similar to that ofFIG.11but with face-to-face wafer-to-wafer hybrid bonding. Each structure200,210includes hybrid bond pads202,212on a front side of devices204,214. In this case, oxide layers110,120may be formed as described herein on front side of structures200,210, i.e., prior to hybrid bond pad formation. Hybrid bond pads202,212would then be formed in the respective structures200,210in any now known or later developed manner, e.g., a dual copper damascene process to connect to devices204,214with a subsequent planarization. A front side of structure200may be bonded to the front side of structure210using aligned hybrid bond pads202,212. Hybrid bond pads202,212form a direct conductor-to-conductor (e.g., Cu-Cu) hybrid bond in a known fashion. Bond structure100, however, provides a stronger bond strength between structures200,210, as described herein. While shown on both structures200,210, bond structure100may be formed on just one of structures200,210.

FIGS.13-14show cross-sectional views of another application. In this application, as shown inFIG.13, IC chips132may be prepared with bonding structure100thereon, and singulated. IC chips132may be taken from separate wafers with different IC structure and functions, for example, logic and memory chips or IC chips132may be taken from different IP nodes. IC chips132may be tested and determined as “Known Good Dies” with high yield prior to bonding the IC chips from different sources onto a carrier wafer220. IC chips132are fusion bonded onto a first carrier wafer220, which also includes bonding structure100. As shown inFIG.14, IC chips132are encapsulated in a dielectric layer222, and collectively removed from first carrier wafer220(FIG.13). IC chips132are then fusion bonded to a second carrier wafer224. Second carrier wafer224may also include bonding structure(s)100. The structures shown inFIG.15are then fusion bonded face-to-face using bonding structures100to another structure230including interconnects therein, e.g., metal wires and vias. Bonding structure(s)100has/have sufficient bond strength to prevent disconnection of the structures.

FIGS.15and16show cross-sectional views of thinning structures, such as semiconductor substrates, using, for example, planarization (curved arrow).FIG.15shows thinning of theFIG.12embodiment, andFIG.16shows thinning of theFIG.14embodiment. In either case, bond structure(s)100provided improved bond strength to withstand the planarization process.

Embodiments of the disclosure provide various technical and commercial advantages, examples of which are discussed herein. One or more of the bonding structures100,170can be used in a single device. The bonding structure(s)100,170provide a greater bond strength than just a thick oxide layer, e.g., at least 1.0 Joules per square meter (J/m2) compared to about 0.6 J/m2. In other embodiments, the bond strength may be at least 1.6 J/m2. In addition, the bonding structure(s)100,170are free of voids therein. The process to form bonding structure(s)100,170does not require tool modifications, and any oxide forming steps use low temperatures that do not damage pre-existing devices.

The method as described above is used in the fabrication and packaging of integrated circuit chips. The package may be part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. End products can also include mobile displays and other microLED products as well as RF chips, and related mobile displays.