Semiconductor package and method for fabricating the same

A semiconductor package includes a semiconductor chip, an inductor applied to the semiconductor chip. The inductor includes at least one winding. A space within the at least one winding is filled with a magnetic material.

TECHNICAL FIELD

The invention relates generally to semiconductor packages, and more particularly to a semiconductor package with an integrated inductor and a method for fabricating the same.

BACKGROUND

Semiconductor chips are encapsulated in a mold compound in order to protect the chips from environmental impacts to ensure reliability and performance. In many applications such as e.g., RF (radio frequency) devices, inductors are coupled to the chips and embedded in the packages. Such packages may become large, sophisticated and expensive. However, both the manufacturers and the consumers of electronic devices desire devices that are inexpensive, reduced in size and yet have increased device functionality.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Aspects and examples are now described with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the disclosures. It may be evident, however, to one skilled in the art that one or more aspects of the disclosure may be practiced with a lesser degree of the specific details. In other instances, known structures and elements are shown in schematic form in order to facilitate describing one or more aspects of the disclosure. The following description is therefore not to be taken in a limiting sense, and the scope is defined by the appended claims. It should also be noted that the representations of the various layers, sheets, cavities or substrates in the figures are not necessarily drawn to scale.

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which specific examples are shown by way of illustration. In this regard, directional terminology, such as e.g., “upper,” “lower,” “top,” “bottom,” “left-hand,” “right-hand,” “front side,” “backside,” etc., is used with reference to the orientation of the figure(s) being described. Because components of examples can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope as defined in the claims.

It is to be understood that the features of the various examples described herein may be combined with each other, unless specifically noted otherwise.

As employed in this specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together; intervening elements may be provided between the “coupled” or “electrically coupled” elements.

The semiconductor chips described further below may be of different types, may be manufactured by different technologies and may include for example integrated electrical circuits, electro-optical circuits, electro-mechanical circuits such as e.g., MEMS (Micro-Electro-Mechanical System) and/or passives. The semiconductor chips described herein may include RF (radio frequency) circuits, control circuits, logic circuits or microprocessors. The semiconductor chips need not be manufactured from specific semiconductor material, for example Si, SiC, SiGe, GaAs, and, furthermore, may contain inorganic and/or organic materials that are not semiconductors, such as for example discrete passives, antennas, insulators, plastics or metals.

According to one aspect, an encapsulation material is provided. The encapsulation material may at least partially cover the semiconductor chip to form an encapsulation body. The encapsulation material may be based on a polymer material, i.e., may comprise a basis material (also referred to as matrix material in the following) made of any appropriate duroplastic, thermoplastic or thermosetting material or laminate (prepreg). In particular, a matrix material based on epoxy resin may be used. The matrix material may contain a filler material, e.g., SiO2particles, to adjust physical properties of the encapsulation body such as e.g., CTE (coefficient of thermal expansion). The encapsulation material can be comprised of a non-magnetic material. Alternatively, the encapsulation material can be comprised of a magnetic material. In particular, the matrix material may embed a magnetic substance, e.g., in form of magnetic particles. The magnetic substance or particles may be made of iron, nickel and/or molybdenum or mixtures and/or alloys of these materials. By way of example, iron, nickel or molybdenum powder particles may be contained in the encapsulation material. The particles may be coated with an insulating shell in order to avoid short circuits.

After its deposition, the encapsulation material may be hardened by a heat treatment. Various techniques may be employed to form the encapsulation body by the encapsulation material, for example compression molding, transfer molding, injection molding, powder molding, liquid molding, dispensing or laminating.

After deposition, the encapsulation material may be cured to form the solid encapsulation body. The space within the at least one winding of the inductor can be filled with a magnetic material. The relative magnetic permeability (i.e., the ratio of the permeability of the magnetic material to the permeability of the free space) of the winding core made of the magnetic material may be high (between 60-150), medium (between 20-60) and low (between 3-20) depending on the application. The inductance of the inductor may be more than one or tens of μH.

According to one example, the inductor is integrated in the semiconductor chip. To this end, a main surface of the semiconductor chip may be provided with a winding trench filled with metal.

According to one example, the inductor may be externally attached to the semiconductor chip. To this end, wires representing coil windings may be placed (e.g., deposited or wire-bonded) on a main surface of the semiconductor chip.

In these and other examples, the winding core of the inductor is filled with the magnetic material which can be comprised of a matrix material embedding magnetic particles. Thus, a part of the magnetic material body may form the magnetic winding core of the inductor. It is further possible that magnetic material is disposed outside the winding so that magnetic materials inside and outside the winding and the magnetic elements constitute or form part of a magnetic winding core.

According to an example, one central hole is formed in the semiconductor chip which central hole comprises the space within the winding and can be formed as a through-hole extending from a first main face to a second main face of the semiconductor chip. It is also possible that at least one further hole is formed in the semiconductor chip which can also be formed as a through-hole. This at least further hole can also be filled with the magnetic material. Also in this case magnetic material can be disposed outside the holes so that magnetic materials inside and outside the holes constitute or form part of a magnetic winding core. In this case no previously disposed magnetic elements would be necessary.

The magnetic material can also be disposed outside of the hole or holes formed in the semiconductor chips. In these and other examples, the winding core of the inductor.

The encapsulation material may be used to produce fan-out type packages. In a fan-out type package at least some of the external contact pads and/or conductor lines connecting the semiconductor chip to external contact pads of the package are located laterally outside of the outline of the semiconductor chip or do at least intersect the outline of the semiconductor chip. Thus, in fan-out type packages, a peripherally outer part of the package of the semiconductor chip is typically (additionally) used for electrically bonding the package to external applications, such as application boards etc. This outer part of the package encompassing the semiconductor chip effectively enlarges the contact area of the package in relation to the footprint of the semiconductor chip, thus leading to relaxed constraints in view of package pad size and pitch with regard to later processing, e.g., second level assembly.

One or more metal layers having the shape of conductor lines (or conductor tracks or traces) may be placed over the semiconductor chip and the encapsulation body. The metal layers may, for example, be used to produce an electric redistribution structure. The conductor lines may be employed as wiring layers to make electrical contact with the semiconductor chip from outside the semiconductor package and/or to make electrical contact with other semiconductor chips and/or components contained in the semiconductor package. The conductor lines may couple contact pads of the semiconductor chip to the external contact pads. The conductor lines may be manufactured with any desired geometric shape and any desired material composition. Any desired metal, for example aluminum, nickel, palladium, silver, tin, gold or copper, or metal alloys may be used as the material. The conductor lines need not be homogenous or manufactured from just one material, that is to say various compositions and concentrations of the materials contained in the conductor lines are possible. Furthermore, the conductor lines may be arranged above or below or between electrically insulating layers such as e.g., dielectric polymer layers.

FIG. 1Aschematically illustrates a semiconductor package100in cross-section andFIG. 1Bshows a top view of the semiconductor package100. The cross-section ofFIG. 1Ahas been taken along the dashed line ofFIG. 1B. The semiconductor package100includes a semiconductor chip10and an inductor12applied to the semiconductor chip10, the inductor12comprising at least one winding14. A space16within the at least one winding14is filled with a magnetic material18.

More specifically, the at least one winding14(inFIG. 1A, by way of example, 2 windings are depicted) may be integrated in the semiconductor chip10. To this end, one or more winding trenches may be generated in a first main face of the semiconductor chip10. Each one of the winding trenches may have any desired geometry and dimensions depending, for example, on the desired current load and/or magnetic field strength and/or application. By way of example, a width of a winding trench may be about 2 μm, 5 μm, 10 μm or more, and a depth of a winding trench may e.g., be about 10 μm, 30 μm, 50 μm or more. An aspect ratio of e.g., of 10 or more may be obtained. The winding trench and thus the windings14may have e.g., a continuous, spiral extension. The plan view shape of a winding14may be circular, polygonal, etc. The windings14form a coil which may be used as an inductance, e.g., in RF devices, as a frequency filter or in any other suitable applications. Further, multiple inductors12or coils may be formed in or connected to the semiconductor chip10.

The winding trench may be filled with any electrically conducting material, e.g., a metal or an electrically conductive polymer material. In one embodiment, by way of example, the winding trench may be filled with copper or aluminum.

It is to be noted that the semiconductor chip10may be provided with chip contact pads10A and10B. Such chip contact pads are typically coupled to an integrated circuit (not illustrated) formed in the semiconductor chip10and/or to the windings14of the inductor12. Without saying, an integrated circuit formed in the semiconductor chip10may be also electrically coupled to the windings14of the inductor12by chip-internal wiring.

The semiconductor chip10may comprise a hole, e.g., a through-hole, comprising the space within the at least one winding14that is filled with the magnetic material18. The hole can thus extend from a first main face to an opposite second main face of the semiconductor chip10and it can be located in a center of the windings14. Moreover, the hole can have any desired cross-sectional shape like, e.g., a square or quadratic or circular shape.

The semiconductor package100may further comprise at least one magnetic element20located at a distance from the semiconductor chip10. In the example of a semiconductor package100, as shown inFIG. 1A, the semiconductor package100comprises two magnetic elements20, each one located at a distance from the semiconductor chip10so that the magnetic elements20are located in an opposite relationship to each other with the semiconductor chip10between them. The magnetic elements20may be located in such a way that each one of them constitute a part of a magnetic winding core in combination with the magnetic material18filled in the space16within the at least one winding14. The magnetic elements20may be comprised of a soft-magnetic material like, e.g., a soft-magnetic material comprising Fe, Ni, FeNi, FeSiB, Co, CoFe, or ferrite material.

The semiconductor package100may further comprise an encapsulation body30formed of an encapsulation material, the encapsulation material covering side faces of the semiconductor chip10. As shown in the example of a semiconductor package100ofFIGS. 1A,1B, the encapsulation body30may be arranged in such a way that it only covers the side faces of the semiconductor chip10and not the first and second main faces. The encapsulation material of the encapsulation body30may be comprised of a non-magnetic material.

The magnetic material18filled into the space within the at least one winding14may comprise a soft-magnetic material. In particular, it may comprise a polymer material embedding magnetic particles like soft-magnetic particles. The polymer material may be filled with ferrite particles like Zn ferrite particles. The magnetic particles may have microscopic or nanoscopic size.

The magnetic material18filled into the space16within the at least one winding14may also extend over one or both of the first and second main faces of the semiconductor chip10in such a way that it covers one or both of the first and second main faces partially or completely. In the example of a semiconductor package100, as shown inFIG. 1Aand as will be clear inFIGS. 2A to 2K, the magnetic material18covers completely the first main face of the semiconductor chip10and the second main face of the semiconductor chip10. Moreover, it extends completely over a lower surface of the semiconductor package100in the example as shown inFIG. 1A.

The semiconductor package100may further comprise an electrical redistribution structure40having at least one structured metal layer41and one polymer layer42, wherein the redistribution structure40extends over the first main face of the semiconductor chip10. The electrical redistribution structure40may be arranged so as to electrically connect each one of the contact pads10A and10B with solder balls70applied onto an upper surface of the redistribution structure40. As shown inFIG. 1B, four solder balls70are arranged onto the upper surface of the redistribution structure40as an example.

As can be seen in the example of a semiconductor package100ofFIG. 1A, the electrical redistribution structure40can be arranged in such a way that the magnetic material18extending over the first main face of the semiconductor chip10is arranged coplanar with the polymer layer42or, in other words, upper surfaces of the magnetic material18and the polymer layer42are coplanar with each other and lower surfaces of the magnetic material18and the polymer layer42are coplanar with the first main face of the semiconductor chip10. The magnetic material18and the magnetic elements20may form together a magnetic winding core as indicated by the two dashed lines with arrows. The magnetic field lines may extend only through the magnetic material18and the magnetic elements20.

FIGS. 2A-2Kschematically illustrate a method for fabricating a semiconductor package100as shown inFIGS. 1A,1B. First of all, a plurality of semiconductor chips10, such as that shown inFIG. 2A, is fabricated on a wafer made of a semiconductor material. The semiconductor wafer may include bulk silicon in which integrated circuits may be embedded. Chip contact pads10A and10B of each one of the semiconductor chips10are located on a first main face of the semiconductor wafer. The integrated circuits can be electrically accessed via the chip contact pads10A and10B. The chip contact pads10A and10B may be made of a metal, for example aluminum or copper, and may have any desired shape and size. Typically, depending on the integrated circuit, each functional chip region is provided with a plurality of chip contact pads10A and10B. The integrated circuits and the chip contact pads10A and10B are formed on wafer level during so-called frontend wafer processing.

Winding trenches and holes15may be formed in each functional chip region on wafer level. The production of the winding trenches and holes15can be effected in many different ways which may, among others, depend on the material of the wafer. For example, RIE (reactive iron etching) or electro-chemical etching may be used to produce the winding trenches and holes15. Instead of electro-chemical etching or RIE etching, other hole or trench formation techniques may be employed for the production of the trenches and holes15. In principle, all the formation methods known in micro-mechanics such as, for example, drilling, laser drilling, ultra-sonic drilling or sand blasting can be used for this purpose.

By way of example, the wafer may have a thickness within the range of 25-2000 μm, and optionally, within the range of 50-250 μm. The holes15may have a diameter within the range of 2-200 μm, and optionally, with the range of 30-100 μm, e.g., about 50 μm. The ratio of hole length to hole diameter (aspect ratio) may lie within the range of 2-1000, and optionally relatively large aspect ratios above e.g., 5, 10 or even 100 may be available. It is to be noted that the hole15may be a blind hole or a through-hole. Typically, the hole15does at least extend in a space within the winding trench. The depth of the hole15may e.g., be equal or greater than the depth of the winding trench.

An electrically conducting material is introduced into the winding trench to form the windings14of the inductor12(FIG. 1A). In one embodiment the electrically conducting material may be introduced by galvanic plating wherein a seed layer may be deposited in the wiring trench and a further layer may be galvanically deposited onto the seed layer. The further layer may be made of e.g., copper and may have a thickness to completely fill the wiring trench. As an alternative to the galvanic plating process, an electroless plating process such as electroless nickel-palladium plating may be used. Electroless plating is also referred to as chemical plating in the art. Further, other deposition methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or printing may be employed to fill the winding trench with an electrically conducting material.

The functional chip regions of the semiconductor wafer may then be singulated into the semiconductor chips10by dicing the wafer and thereby obtaining a plurality of semi-conductor chips10.

In order to package the semiconductor chips10, a (temporary) carrier50may be provided as illustrated inFIG. 2A. The carrier50may be a plate made of a rigid material, for example a metal, metal alloy, silicon, glass or plastics. The carrier50may have at least one flat surface, and an adhesive tape (not shown), for example a double sided sticky tape, may be laminated onto this surface of the carrier50. Components of the semiconductor device to be fabricated can be placed on this adhesive tape. The shape of the carrier50is not limited to any geometric shape, for example the carrier50may be round or square-shaped. The carrier50may have any appropriate size. Thus, the molded body (often referred to as “molded reconfigured wafer,”) which is formed on the basis of the carrier50, may e.g., be disc-shaped having a diameter of e.g., 200 or 300 mm, or may have any other shape such as a polygonal shape with the same or other lateral dimensions.

The semiconductor chips10are placed on the carrier50, as shown inFIG. 2A, where only one semiconductor chip10is shown. The semiconductor chips10can be fixed on the adhesive tape. Alternatively, a glue material or any other adhesive material or mechanical securing means (such as a clamping device or a vacuum generator) may be associated with the carrier50and used to fix the semiconductor chip10. The semiconductor chips10may be arranged in an array on the carrier50, wherein the spacing between neighboring semiconductor chips10may be determined according to the desired foot print area of the semiconductor package to be fabricated. The spacing between neighboring semiconductor chips10may e.g., be in the range between 0.25 mm and 10 mm. It is to be noted that throughoutFIG. 2A-2Konly a partial section of carrier50and the molded body is illustrated, that is to say in practice, typically much more than two semiconductor chips10(e.g., some tens or more than hundred thereof) are placed on the carrier50.

The semiconductor chips10are relocated on the carrier50in larger spacings as they have been in the wafer bond. The semiconductor chips10may have been manufactured on the same semiconductor wafer, but may alternatively have been manufactured on different semiconductor wafers. Furthermore, the semiconductor chips10may be physically identical, but may also contain different integrated circuits and/or represent other components. The semiconductor chips10may be arranged over the carrier50with their first main faces containing the chip contact pads10A and10B facing the carrier50. In this case, the first main faces and the chip contact pads10A and10B may be in direct contact with the adhesive tape or the carrier50. The semiconductor chips10may be placed onto the carrier50by means of a pick-and-place machine.

After attaching the semiconductor chips10onto the carrier50, magnetic elements20may be placed onto the carrier50. The magnetic elements20may be comprised of soft-magnetic elements which can be made of Fe, Ni, FeNi, FeSiB, Co, CoFe, or ferrite materials. The magnetic elements20can be placed in an opposite relationship to each other on two opposing lateral sides of the semiconductor chip10and in a lateral distance from respective side faces of the semiconductor chips10.

After attaching the semiconductor chips10and the magnetic elements20on the carrier50, they are encapsulated with an encapsulation material forming a molded body30as illustrated inFIG. 2B. The encapsulation material may partly or completely cover the upper main faces of the semiconductor chips10and also the side faces of the semiconductor chips10and the encapsulation material may completely cover the magnetic elements20on all sides. The gaps between the semiconductor chips10may also be filled with the encapsulation material. The encapsulation material can be comprised of a conventional encapsulation material like, e.g., an epoxy resin material. For example, the encapsulation material may be a duro-plastic or thermo-setting mold material. In particular, the encapsulation material may be comprised of a non-magnetic material.

After curing, the encapsulation material provides stability to the array of semiconductor chips10. Various techniques may be employed to cover the semiconductor chips10with the encapsulation material. The encapsulation material may, for example, be applied by compression molding, injection molding, granulate molding, powder molding or liquid molding.

As shown inFIGS. 2A and 2B, the vertical sizes of the semiconductor chips10, the holes15and the magnetic elements20can be chosen such that the vertical size of the semiconductor chips10is greater than the vertical size of the magnetic elements20and the vertical size of the holes15corresponds to the vertical size of the magnetic elements20. This allows in a next step, which is shown inFIG. 2C, to partly grind back the mold body30and the semiconductor chip10from above and thereby open the holes15. The grinding back is performed down to the upper surfaces of the magnetic elements20. The grinding process can be done in different ways, one of which can be mechanical polishing or chemical-mechanical polishing (CMP).

In the next step, as shown inFIG. 2D, a magnetic material60is covered on the second main faces of the semiconductor chips10and on the molded body30and filled into the holes15. It may be possible to cover the whole backside of the molded body30, in particular the whole reconfigured wafer, with the magnetic material60. Alternatively, only those parts of the molded body30can be covered with the magnetic material60which are intended to be fabricated to semiconductor packages100such as that shown inFIG. 1A. The magnetic material60can be applied by, e.g., printing, stencil printing, screen printing, ink-jet printing or other suitable printing technologies.

Thereafter, as shown inFIG. 2E, the carrier50can be removed and the molded body30can be turned upside down for fabricating an electrical redistribution structure40in the next step.

FIGS. 2F and 2Gshow a cross-sectional representation of the molded body30(FIG. 2F) and a top view of the molded body30(FIG. 2G) after a first step of generating an electrical redistribution structure40. A first dielectric layer42.1is deposited onto the entire surface of the molded reconfigured wafer whereafter the first dielectric layer42.1is opened in areas where the contact pads10A and10B are located and then the opened portions are filled with a metallic material and electrical traces41are generated which begin at the metallized openings and end at edge positions of the molded body. The first dielectric layer42.1may be fabricated from a polymer, such as polyimide, and it may be deposited from a gas phase. The openings in the first dielectric layer42.1may, for example, be produced by using photolithographic methods and/or etching methods. The metallic material may be deposited by galvanic deposition into the openings and also the metallic traces41may be fabricated by galvanic deposition.

FIGS. 2H and 2Ishow the result after the second step of the fabrication of the electrical redistribution structure40.FIG. 2Hshows a cross-sectional view along line H-H ofFIG. 2I. In the second step a second dielectric layer42.2is deposited onto the entire surface of the molded body. The second dielectric layer42.2can be fabricated in the same way as the first dielectric layer42.1. After depositing the second dielectric layer42.2, openings are formed above end portions of the electrical traces42.2and thereafter the openings are filled with a metallic material. Further-on, a large square-shaped opening is formed in the second dielectric layer42.2and the underlying first dielectric layer42.1, wherein the opening can be seen in the top view shown inFIG. 2I, and the opening is generated in such a way that it exposes the upper surfaces of the magnetic elements20and the hole15.

In a next step, as shown inFIGS. 2J and 2K, a magnetic material60is filled into the large opening so that magnetic winding cores are generated.FIG. 2Jshows a cross-sectional view along line J-J ofFIG. 2K. The magnetic material60may be comprised of a polymer filled with soft-magnetic particles. In a final step solder balls70are deposited onto the metallized openings resulting in a semiconductor package as already shown inFIG. 1A.

FIGS. 3A and 3Bshow another example of a semiconductor package in a cross-sectional view (FIG. 3A) and in a partial sectional view (FIG. 3B) within a horizontal plane of the inductor. The cross-sectional view ofFIG. 3Ashowing the holes316.1and316.nhas been taken along line A-A ofFIG. 3B. The semiconductor package300ofFIGS. 3A and 3Bis similar to the semiconductor package100ofFIGS. 1A,1B except for the following differences. The semiconductor package300does not comprise magnetic elements20disposed in a lateral distance to side faces of the semiconductor chip. Instead the semiconductor package300comprises a semiconductor chip310comprising a plurality of holes316, wherein the plurality of holes316include one central hole316.1and non-central holes316.n. The semiconductor package300comprises an inductor312applied to the semiconductor chip310, the inductor312comprising at least one winding314. The central hole316comprises a space within the at least one winding314which is filled with a magnetic material. The other non-central holes316.ncan also be filled with the magnetic material thereby generating a plurality of magnetic winding cores as indicated by the dashed lines inFIG. 3A. The semiconductor package300may also comprise an encapsulation body330and an electrical redistribution structure340applied onto a first main face of the semiconductor chip310and solder balls370applied onto exposed metallized portions of the redistribution structure340.

FIGS. 4A-4Iillustrate a method for fabricating the semiconductor package300. As the fabrication procedure is similar to the procedure as outlined above in connection withFIGS. 2A-2K, only the differences will be outlined in the following.

In the first step a plurality of semiconductor chips310is produced, wherein each one of the semiconductor chips310comprises contact pads310A and310B, an inductor312comprising at least one winding314, and a plurality of trenches316. The plurality of semiconductor chips310is placed onto a carrier350as shown inFIG. 4A. In this way a reconfigured wafer is provided.

In a next step, as shown inFIG. 4B, the semiconductor chips310are covered by an encapsulation material for fabricating an encapsulation body330. The encapsulation material can again be comprised of a standard, non-magnetic encapsulation material.

In a next step, as shown inFIG. 4C, the encapsulation body330is partially removed from its front surface until the trenches316are reached so that a plurality of holes316is produced, the holes316comprising a central hole316.1and a plurality of non-central holes316.n.

In a next step, as shown inFIG. 4D, a front surface of the encapsulation body330is covered by a magnetic material360in such a way that the holes316are filled with the magnetic material360and a layer of the magnetic material360is deposited onto the front surface of the semiconductor chips310and the encapsulation body330. The magnetic material360can be comprised of a polymer material embedding magnetic particles.

In a next step, as shown inFIG. 4E, the carrier350is removed and the encapsulation body330is turned upside down.

In a next step, as shown inFIGS. 4F and 4G, an electrical redistribution structure is produced. This can be done by first depositing a first dielectric layer341.1and forming therein openings which are located above the contact pads310A and310B. Thereafter, the openings can be filled with a metallic material. Thereafter, electrical traces342can be fabricated which extend from the metallized openings to edge portions on the first dielectric layer341.1. Thereafter, a second dielectric layer341.2can be deposited onto the first dielectric layer341.1thereafter openings can be formed in the second dielectric layer341.2above end portions of the metallic traces342. Thereafter, a central portion of the dielectric layers above the holes316can be removed.

In a next step, as shown inFIGS. 4H and 4I, a magnetic material460can be filled into the empty portion of the dielectric layers and solder balls370can be applied onto exposed metallized portions of the redistribution structure340.

InFIGS. 5A-Cdifferent examples of semiconductor packages are illustrated, each one showing a partial sectional view in a horizontal plane of the inductor. The examples show different arrangements of holes filled with a magnetic material.FIG. 5Ashows a first example comprising the inductor312and one central hole316.1comprising a space within the inductor312, and a second hole316.2laterally besides the inductor.FIG. 5Bshows the inductor312, a central hole316.1within the inductor312and four non-central holes316.narranged on the corners of a square.FIG. 5Cshows the inductor312, a central hole316.1and eight holes316.ncircumferentially arranged around the inductor312.

FIGS. 6A and 6Bshow different examples of transformers each one showing a partial sectional view in a horizontal plane of the transformer likeFIG. 3B, FIG.4FG, andFIGS. 5A-C. The transformer400shown inFIG. 6Acomprises a first elongated inductor412integrated in a semiconductor chip410wherein the inductor windings414surround six spaces416which are filled with a magnetic material. Within the same horizontal plane four inductors422are arranged along a long side of the elongated inductor412. Each one of the inductors422is comprised of windings424wherein the windings424surround one space426which is filled with a magnetic material. Above and below the plane in which the inductors412and422are arranged, magnetic material is provided (not shown) which is contiguous with the magnetic material disposed in the holes416and426so that magnetic winding cores are formed thereby.

The transformer500as depicted inFIG. 6Bdiffers from the transformer400only in that the holes416of transformer400are combined to one elongated hole436filed with magnetic material.