Solid-state power controller channel protection systems and methods

A scalable solid-state power controller system is provided with channel protection features. A plurality of output channels may be combined to provide a combined channel output. The current provided at the combined channel output is sourced from the plurality of output channels and each channel is protected from faults such as overcurrent events.

FIELD

The present disclosure relates to solid-state power controllers and their components, and more particularly, to the interaction of an overload protection system and a solid-state power controller.

BACKGROUND

Solid-state power controllers (“SSPC”) have been designed to have a current channel that can be combined with current channels of other SSPCs to achieve a desired current capacity. However, the individual channels may experience different load conditions, for example, in the event that one or more individual channel fails, or in the event that outrush current demands vary or component values vary. Some channels may become overloaded while other channels may remain within operating specifications. In some instances, a so-called “instant trip” monitoring circuit is implemented, however, a fault may occur so rapidly that an interrupt signal from an instant trip monitoring circuit cannot reach the SSPCs in time to direct the SSPCs to trip the circuit offline before one or more channels experience an overload condition. Moreover, in the event, that a load draws a prolonged outrush current, a cascading trip may occur as channels are incrementally overloaded and trip offline.

SUMMARY

A scalable solid-state power controller system is disclosed. The scalable solid-state power controller system includes a power source having a channel bank including a plurality of output channels having a first output channel and a second output channel. The scalable solid-state power controller system includes a first solid-state power controller having a first channel current switching circuit, a second solid-state power controller having a second channel current switching circuit, a controller in electrical communication with the first solid-state power controller and the second solid-state power controller, and a combined channel output. In various embodiments, the first channel current switching circuit is disposed in series between the combined channel output and the first output channel, and the second channel current switching circuit is disposed in series between the combined channel output and the second output channel. In various embodiments, the first channel current switching circuit controls a first current supplied by the first output channel in response to the controller, and the second channel current switching circuit controls a second current supplied by the second output channel in response to the controller.

A method of operating a solid-state power controller is disclosed. The method may include providing, by a controller, a control signal directing a channel current switching circuit to provide a current on a current limiter bus in response to a voltage presented on a gate control bus, and varying, by an output feedback circuit, a reactive impedance limiting the current provided to a combined channel output via the current limiter bus. The method may also include sensing, by the output feedback circuit, the current provided to the combined channel output, providing, by the output feedback circuit, feedback to the channel current switching circuit varying the voltage presented on the gate control bus, and maintaining the current provided to the combined channel output within a desired limit in response to the voltage presented on the gate control bus and in response to the varying the reactive impedance.

DETAILED DESCRIPTION

The detailed description of exemplary embodiments herein makes reference to the accompanying drawings, which show exemplary embodiments by way of illustration and their best mode. While these exemplary embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, it should be understood that other embodiments may be realized and that logical changes may be made without departing from the spirit and scope of the disclosure. Thus, the detailed description herein is presented for purposes of illustration only and not of limitation. For example, the steps recited in any of the method or process descriptions may be executed in any order and are not necessarily limited to the order presented. Furthermore, any reference to singular includes plural embodiments, and any reference to more than one component or step may include a singular embodiment or step.

The present disclosure relates to the design of a scalable SSPC system and, more particularly, to the design of a scalable SSPC system comprising a SSPC with self-protection features. Aspects of the designs disclosed herein may be applicable to other power supplies or power sources.

According to various embodiments, and with reference toFIG. 1, a scalable SSPC system10may comprise a system whereby electrical power is provided for use by a load4. Moreover, the scalable SSPC system10may condition the electrical power so that its current and voltage remains within defined boundaries and may protect itself, and/or the load4, by preventing the current and voltage from unwanted deviations. For example, the scalable SSPC system10may terminate the provision of power, and/or restrict the output current in event of an unexpected drop in load4's impedance/resistance, such as, during a short-circuit event, or in the event of another fault. For instance, the scalable SSPC system10may comprise one or more SSPC3, whereby the current and or voltage presented at combined channel output7may be controlled.

In various embodiments, the scalable SSPC system10may comprise a power source1, a controller6, a SSPC3, and a combined channel output7. The power source1may provide electrical power via a channel8to one or more SSPC3, from which it is output at combined channel output7in response to a control signal5comprising directions from controller6to the SSPC3, and in response to protective actions taken by the SSPC3both independently and in response to the control signal5.

With continuing reference toFIG. 1, a scalable SSPC system10may comprise one or more SSPC3. For example, a scalable SSPC system10may comprise a first SSPC3-1, a second SSPC3-2, a third SSPC3-3, a fourth SSPC3-4and/or any number of SSPCs3. Each SSPC may receive electrical power via a channel8. For example, the first SSPC3-1may receive electrical power via a first channel8-1, the second SSPC3-2may receive electrical power via a second channel8-2, the third SSPC3-3may receive electrical power via a third channel8-3, and the fourth SSPC3-4may receive electrical power via a fourth channel8-4. The electrical power may be combined by the various SSPCs at combined channel output7. Each SSPC may receive a corresponding control signal5from the controller6. For example, the first SSPC3-1may receive a first control signal5-1, the second SSPC3-2may receive a second control signal5-2, the third SSPC3-3may receive a third control signal5-3, and the fourth SSPC3-4may receive a fourth control signal5-4. By controlling each SSPC, the controller6may logically combine SSPCs to increase and/or decrease the current provided at combined channel output7, as well as control the amount of current drawn from each channel8.

A power source1may comprise any apparatus whereby electrical power may be provided. For example, the power source1may be a solid-state power supply. The power source1may be a linear power supply, or a switching-mode power supply, or a power supply operating according to a variety of different modes. The power source1may further comprise a generator, an alternator, a fuel cell, or another source of electrical energy and in various embodiments may be configured for aircraft use. For example, the power source1may comprise a generator mechanically connected with a turbine engine, such as an aircraft engine or an aircraft auxiliary power unit engine. Although, scalable SSPC systems10disclosed herein involve power sources1that provide direct current, in further embodiments, a power source1may provide an alternating current, or may provide any form of electrical power.

In various embodiments, the scalable SSPC system10may comprise a controller6. The controller6may comprise a digital controller, an analog controller, or may comprise a combination of digital and analog components. The controller6may comprise a logical division of one or more of an aircraft data bus, a remote data concentrator, a flight computer, a full authority digital engine control (“FADEC”), an electronic engine controller (“EEC”), an engine control unit (“ECU”), and/or any other aircraft system. The controller6may comprise a processor and a tangible non-transitory memory, as well as a digital-to-analog converter (“DAC”), an analog to digital converter (“ADC”), and/or discrete logic components, for example, TTL and/or CMOS level logic devices. The controller6provides a control signal5to the SSPC3as discussed further herein. For example, the controller6may provide a first control signal5-1to the first SSPC3-1a second control signal5-2to the second SSPC3-2, a third control signal5-3to the third SSPC3-3, a fourth control signal5-4to the fourth SSPC3-4, and/or any number of control signals5to any number of SSPCs3.

The scalable SSPC system10may comprise one or more SSPC3. A SSPC3may comprise analog components and/or digital components configured to limit the current and/or voltage output from the power source1to the combined channel output7. For example, the SSPC3may sense overcurrent conditions. Moreover, in embodiments comprising a plurality of SSPCs3, the SSPCs3may be directed by the controller6to balance the total current provided at the combined channel output7among different channels8of the power source1.

Having discussed various aspects of a scalable SSPC system10, the power source1may comprise a channel bank9. The channel bank9may comprise a plurality of output channels. These channels may be combined in parallel. For example, a SSPC may be associated with each channel and the controller may selectively turn different SSPCs on and off in order to logically combine channels together to provide current to the combined channel output7. In this manner, the total current supplied by the power source1may be greater than the power supplied by any one channel. For example, the channel bank9may comprise any number of channels. In various embodiments, the channel bank9comprises two channels, or three channels, or four channels or any number of channels. In further embodiments, the channel bank9comprises only one channel, or comprises various channels combined in various different ways. For the purpose of illustration, a channel bank9is illustrated inFIG. 1, comprising four channels: Channel A8-1, Channel B8-2, Channel C8-3, and Channel D8-4. These channels may be combined in parallel by the SSPCs3and the aggregate current may be provided at combined channel output7. In various embodiments, each channel may have a lesser current capacity than the combined channel output7. In various embodiments, the SSPCs3are configured to maintain each channel within that channel's current capacity and to balance the current drawn among the different channels. In this manner, each channel can be maintained within its limits, even if the combined channel output7is of a significantly greater magnitude than an individual channel's limit.

Moreover, whileFIG. 1shows a channel bank9having four channels8-1,8-2,8-3, and8-4, this grouping is for example only and any number of channels8and/or channel banks9may be combined, depending on the characteristics of the output power desired. For further example, in various embodiments, a channel bank may comprise a single channel, for example, in the event that a single channel can provide the current desired at combined channel output7.

Now, with reference toFIG. 2, a SSPC3is presented in greater detail. In various embodiments, a SSPC3comprises a channel current switching circuit33, an output feedback circuit34, and a control circuit32. These various components are connected in electrical communication.

A channel current switching circuit33is connected to a channel8. For example, Channel A8-1, Channel B8-2, Channel C8-3, and Channel D8-4each are connected to the channel current switching circuit33of a separate first SSPC3-1, second SSPC3-2, third SSPC3-3, and fourth SSPC3-4. The channel current switching circuit33regulates the current flowing from the connected channel, in response to the control circuit32and the output feedback circuit34. The current then passes through the output feedback circuit34and out via the combined channel output7to a load4(seeFIG. 1).

An output feedback circuit34is connected to the channel current switching circuit33and the control circuit32. The output feedback circuit34monitors the current passing out of the SSPC3to the combined channel output7and provides a signal to the control circuit32in response to the current passing out of the SSPC3. For example, the output feedback circuit34may provide a signal indicating that the control circuit32should direct the channel current switching circuit33to reduce and/or limit the current provided to the combined channel output7from the SSPC3in response to the output feedback circuit34detecting that the current is too high and/or is approaching a desired limit. The output feedback circuit34may provide a signal to the control circuit32indicating that the channel current switching circuit33should increase the path resistance between the channel8and the combined channel output7in order to prevent the combined current from all SSPCs3, and/or the individual current from a single SSPC3from becoming too high, or reduce the path resistance to prevent the combined current from all SSPCs3, and/or the individual current from a single SSPC3from becoming too low. Moreover, the output feedback circuit34may contain reactive passive components, for example, to immediately respond to various circuit conditions, for example, inductive components whereby the deleterious effects of an excessive outrush current may immediately be compensated.

A control circuit32may receive a control signal5from a controller6and may receive a voltage reference31. In various embodiments, the voltage reference31may correspond to the nominal voltage presented at the channel8, although it may be any desired value. The control circuit32may adjust the current drawn from the channel8in response to the control signal5and the voltage reference31.

Now, with reference toFIG. 3, a detailed schematic diagram of an example SSPC3is provided. As previously discussed, a SSPC3may comprise a channel current switching circuit33, an output feedback circuit34, and a control circuit32.

A channel current switching circuit33may comprise a circuit arranged to limit the current provided by the channel8. For instance, the channel current switching circuit33may comprise a current limiter bank54. The current limiter bank54may comprise a plurality of current limiters corresponding in number to the maximum amount of current that the connected channel8can provide divided by the current handling capacity of each current limiter. For example, the current limiter bank54may comprise a first current limiter50-1, a second current limiter50-2, a third current limiter50-3, and a fourth current limiter50-4, all connected in parallel. Moreover, the channel current switching circuit33may optionally include an inductive damper64.

Each current limiter may comprise a transistor. The control circuit32and the output feedback circuit34may control the current limiters. In addition, the transistor may comprise a field-effect transistor. Thus, in various embodiments, the control circuit32and the output feedback circuit34may control the current limiters by controlling the gate of each transistor. In this manner, a selectably conductive path may be controlled corresponding to each channel of the channel bank9. In various embodiments, the gate voltage of the transistor may be changed by the control circuit32and the output feedback circuit34. Furthermore, in various embodiments, the transistor gate voltage of each current limiter may be changed by the control circuit32and the output feedback circuit34in unison, for instance, the gates may all be connected to a gate control bus52. In this manner, the resistivity of the source-drain conduction path of the transistors may be varied, thus variously limiting the amount of current flowing through the transistors. One end of each source-drain conduction path of a transistor may be connected in parallel to a channel8, while the other end may be connected in parallel to a current limiter bus51. Thus, the transistors provide overcurrent protection to the channel8, as well as cooperating with the transistors of the channel current switching circuits33of other SSPCs to actively balancing the current drawn by a load among all channels8of the channel bank9, as directed by the controller6and/or the channel current switching circuit's respective corresponding output feedback circuit34.

The transistors may be operated in the linear region (also known as the ohmic or Triode mode). In this manner, the resistivity of the source-drain conduction path may be varied; however, under some circuit conditions, one or more transistors may be operated in the active region, such as when maximum current is desired to be supplied. Each transistor may be a p-channel FET, or an n-channel FET. Alternatively, other transistors such as bipolar junction transistors (“BJTs”), whether NPN or PNP, may be implemented, or other voltage-controlled switches or other current-controlled switches may be implemented. In various embodiments, the current limiter further comprises a protection resistor connected in series with the gate of each transistor.

The current limiter bus51may comprise a bus connecting the current output of each current limiter of the current limiter bank54. These outputs may be combined, and connected to the combined channel output7, for example, via a path through the output feedback circuit34.

Similarly, the gate control bus52may comprise a bus connecting the gates of the transistors of the current limiter bank54together. These gates may be connected together so that the gate voltage may be changed in unison across all current limiters of current limiter bank54(by the control circuit32and the output feedback circuit34). As a result, the current provided by the combined channel output7may be balanced across all the channels8of the channel bank9, via individualized control of each SSPC's gate control bus52via control signals5.

An inductive damper64may be disposed in series with the current limiter bus51and the combined channel output7. The inductive damper64may comprise an inductor or any other component configured to dampen changes in current over time. In this manner, large startup currents may be dampened, protecting the load, and fluctuations/noise caused by the load, such as switching noise, may be dampened, protecting the scalable SSPC system10.

An output feedback circuit34may comprise a circuit arranged to monitor the combined current provided at the combined channel output7and provide feedback to the channel current switching circuit33instructing the channel current switching circuit33to increase or decrease the current provided. For example, the output feedback circuit34may comprise a feedback amplifier62, and a sense resistor65. In various embodiments, the output feedback circuit34may optionally include a signal amplifier63.

A feedback amplifier62may comprise a current controlled amplifier. For example, the feedback amplifier62may comprise a bipolar junction transistor. Moreover, the sense resistor65may comprise a resistor disposed between the channel current switching circuit33and the combined channel output7. As current flows through the sense resistor65, a voltage is developed across the sense resistor65. The base of the bipolar junction transistor and the emitter of the bipolar junction transistor may be connected to opposite sides of the sense resistor65. In this manner, the voltage developed across the sense resistor65controls the resistivity of the bipolar junction transistor collector-emitter pathway. The collector may be connected to a control circuit32(for example, the control circuit/feedback circuit balancer35discussed further herein), which may then connect to the gate control bus52. In this manner, the voltage present on the gate control bus52may be controlled in response to the current flowing through the sense resistor65so that a feedback loop is established wherein the feedback amplifier62controls the gate control bus voltage in response to the current output of the SSPC (which is then combined with that of any other SSPCs and provided to combined channel output7). Thus, the gate control bus52voltage may change in response to the output current to cause the channel current switching circuit33to limit the output current and bring it into compliance with the desired current limit, such as in the event of a fault condition. Some fault conditions may include a short circuit or startup load variations, such as outrush current during a transient event.

A signal amplifier63may be disposed between the sense resistor65and the base of the bipolar junction transistor comprising the feedback amplifier62. The signal amplifier63may increase and/or decrease the sensitivity of the output feedback circuit34, or may otherwise condition the behavior of the output feedback circuit34as desired for a particular application. In various embodiments, the amplifier comprises a solid-state operational amplifier, though any amplifier configuration may be implemented. In further embodiments, the signal amplifier63is omitted.

With ongoing reference toFIG. 3, a control circuit32may be incorporated as well. The control circuit32may include a overvoltage protector41and a control circuit/feedback circuit balancer35. The overvoltage protector41may be in electrical communication with a voltage reference31. The overvoltage protector41may comprise a circuit to condition the voltage reference31and provide power to the gate control bus52during certain scenarios, such as a transient overvoltage condition, to force current limiters50to an on condition until the scenario, such as a transient overvoltage condition, has passed. Thus the overvoltage protector41may provide overvoltage protection, such as lightning protection. In various embodiments, the overvoltage protector41comprises a Zener diode42and a power diode43. The Zener diode42may be arranged in a reverse biased configuration in order to regulate the voltage supplied by the overvoltage protector41while the power diode43may be arranged in a forward biased configuration in order to provide reverse current protection to voltage reference31and enable proper functioning of control circuit/feedback circuit balancer35.

The control circuit32may selectively sink the gate control bus52to ground, thus selectively changing the voltage on the gate control bus52. Thus, the control circuit32may comprise a control circuit/feedback circuit balancer35comprising a voltage divider to join different signals on the gate control bus52. For instance, the control signal5may be connected to the control circuit32. A control resistor44may be disposed in the circuit path. Similarly, the channel current switching circuit33may be connected to the control circuit32and a feedback resistor61may be disposed in the circuit path between the collector of the feedback amplifier62and the overvoltage protector41. The channel current switching circuit33and the control signal5may selectively change the voltage on the gate control bus52. For example, during normal operation, control signal5may control the voltage present on gate control bus52, however, during an overcurrent condition, the output feedback circuit34may lower the voltage on the gate control bus52and during an overcurrent condition, overvoltage protector41may increase the voltage on the gate control bus52. Thus, one may appreciate that a parallel voltage divider may be established by the feedback resistor61and the control resistor44which are connected in parallel (and are in series with the overvoltage protector41). The gate control bus52may also be connected in parallel with the feedback resistor61and the control resistor44. Thus, the voltage presented on the gate control bus52may be varied in response to the control signal5, which may comprise a resistivity of the path through the controller6, and in response to the resistivity of the collector-emitter path through the bipolar junction transistor comprising the feedback amplifier62. In this manner, the controller6may control the current supplied by the SSPC to the combined channel output7through the channel8, and the output feedback circuit34may also control the current supplied at the combined channel output7through the channel8.

The feedback resistor61and control resistor44may be selected to enable a prioritization of the different control functions connected to gate control bus52. For example, if overvoltage protector41conducts due to an overvoltage, overvoltage protector41has the highest priority because, among other reasons, there is no resistor between overvoltage protector41and the gate control bus52. If there is no overvoltage, but there is an overcurrent, feedback resistor61facilitates a controlled reduction in the voltage on gate control bus52. If both an overvoltage and overcurrent condition occur at the same time, then overvoltage protector41may override feedback resistor61and control resistor44because it provides a direct path without a resistor—thus, the current limiters50may be forced on, even though an overcurrent condition exists, in order to address the overvoltage condition as a higher priority condition. Similarly, during normal operation, feedback resistor61may provide no control function and instead the control signal5via control resistor44may control the voltage on gate control bus52.

Having discussed various aspects of a scalable SSPC system10and an SSPC3, a SSPC3may be operated according to various methods. For example, with reference toFIGS. 1, 3, and 4, a method400is provided wherein the controller6may provide a control signal5directing a channel current switching circuit33to provide a current on a current limiter bus51in response to a voltage presented on a gate control bus52(Step410). In various embodiments, the load4may be a reactive load, so that a large outrush current is demanded at initial startup. Thus, the output feedback circuit34may vary a reactive impedance limiting the current provided to a combined channel output7(Step420). Furthermore, the SSPC3may sense, by the output feedback circuit34, the current provided to the combined channel output7(Step430). The output feedback circuit34may provide feedback to the channel current switching circuit33varying the voltage presented on the gate control bus52(Step440). In this manner, the current provided to the combined channel output7may be maintained within a desired limit in response to the voltage presented on the gate control bus52and in response to the varying the reactive impedance (Step450). Thus, the SSPC3may provide active current regulation, such as in response to transient events, for example, a load fault, such as outrush currents short circuits, and/or overload conditions.

While the systems described herein have been described in the context of scalable SSPC systems for implementation in aircraft applications; however, one will appreciate in light of the present disclosure, that the systems described herein may be used in various other applications, for example, different vehicles, different power applications, and different circuit protection arrangements, or any other vehicle or device, or in connection with industrial processes, or propulsion systems, or any other system or process having need for a power supply with channel protection.