SELF-ALIGNED GATE CUT STRUCTURES

Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate layer between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices.

FIELD OF THE DISCLOSURE

The present disclosure relates to integrated circuits, and more particularly, to gate cut structures.

BACKGROUND

As integrated circuits continue to scale downward in size, a number of challenges arise. For instance, reducing the size of memory and logic cells is becoming increasingly more difficult. Certain aspects of lithography technology can impose physical limits on how accurately certain structures can be aligned. Alignment errors can lead to low yield and/or devices that operate slightly differently from one another which can cause timing errors or other failures. Accordingly, there remain a number of non-trivial challenges with respect to structure alignment in semiconductor devices.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. As will be further appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles, and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used.

DETAILED DESCRIPTION

Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells, such as those cells that use finFETs or gate-all-around transistors. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate layer between the neighboring semiconductor devices thus isolating the gate of one semiconductor device from the gate of the other semiconductor device. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices (e.g., such as the example case where the two distances are within 1 nm of each other, or closer). This highly accurate alignment is nearly impossible to consistently achieve using conventional masking techniques. Numerous variations and embodiments will be apparent in light of this disclosure.

General Overview

As previously noted above, there remain a number of non-trivial challenges with respect to alignment of particular semiconductor structures. In more detail, gate cut structures are commonly provided between adjacent semiconductor devices to isolate the gate layer that crosses over each of the adjacent semiconductor devices. Accordingly, gate cut structures are important for the formation of integrated circuits to successfully isolate the gates of two devices from one another. Ideally, the gate cut structure is to be placed directly in the middle between the adjacent semiconductor devices to ensure the same amount of gate material around all sides of each of the semiconductor regions of the semiconductor devices. In practice, however, this is difficult to achieve as alignment tolerances during the masking and lithography process often cause the gate cut to be formed closer to one semiconductor region vs the other. Additionally, due to some other masking limitations, gate cut structures are typically one size anywhere across the integrated circuit.

Thus, and in accordance with an embodiment of the present disclosure, techniques are provided herein to form self-aligned gate cut structures that do not rely on the limitations imposed by conventional lithography. During the formation of the semiconductor devices, spacer structures are formed on the sidewalls of adjacent semiconductor fins to form a region between the spacer structures that is self-aligned to be centralized between the adjacent semiconductor fins. This region can be filled with a sacrificial material that has sufficient etch selectivity to the material used for the spacers in order to selectively remove the sacrificial material and replace it with a suitable gate cut material, such as silicon nitride. Ultimately, the resulting gate cut structures are self-aligned between a first and a second adjacent semiconductor device such that the distance between the gate cut structure and the semiconductor region of the first semiconductor device is substantially the same as the distance between the gate cut structure and the semiconductor region of the second semiconductor device. As used herein, distances that are substantially the same to one another are within 1.5 nm of each other according to some embodiments, such as the example case where the distances are within 1 nm or less of each other, or the example case where the distances are within 0.5 nm or less of each other. In any such cases, the distance can be measured at a consistent height or otherwise within the same imaginary horizontal plane that passes through each of the semiconductor regions and the gate cut structure, such as at the one-third-point or midpoint of the gate cut structure, or a midpoint of the gated portion of the fins. Additionally, the disclosed process for forming the gate cut structures yields gate cut structures that can have different widths across the integrated circuit depending on the distance between the adjacent semiconductor devices.

According to an embodiment, an integrated circuit includes a first semiconductor device having a first semiconductor region extending between a first source region and a first drain region, and a second semiconductor device having a second semiconductor region extending between a second source region and a second drain region. The integrated circuit further includes a gate layer comprising a conductive material that extends over the first semiconductor region and the second semiconductor region, and a gate cut structure that comprises a dielectric material. The gate cut structure is between the first semiconductor device and the second semiconductor device such that the gate cut structure interrupts the gate layer where a first distance between the gate cut structure and the first semiconductor region is substantially the same as a second distance between the gate cut structure and the second semiconductor region (e.g., such as the example case where the two distances are within 1 nm of each other, or closer.

According to another embodiment, a method of forming an integrated circuit includes forming a first fin comprising first semiconductor material and a second fin comprising second semiconductor material, wherein the first fin and the second fin extend parallel to one another, the first fin having a first cap structure on a top surface of the first fin and the second fin having a second cap structure on a top surface of the second fin; forming a first spacer structure comprising a first material on at least a first side of the first fin facing the second fin and a second spacer structure comprising the first material on at least a second side of the second fin facing the first fin; depositing a second material different from the first material into a region between the first and second spacer structures; removing the cap structure and depositing the first material onto the top surface of the first fin and the second fin; removing the second material from between the first and second spacer structures; depositing a dielectric material into the region between the first and second spacer structures; and forming a gate over the first semiconductor material and over the second semiconductor material, wherein the dielectric material interrupts the gate between the first semiconductor material and the second semiconductor material.

The techniques can be used with any type of non-planar transistors, including finFETs (sometimes called double-gate transistors, or tri-gate transistors), or nanowire and nanoribbon transistors (sometimes called gate-all-around transistors), to name a few examples. The source and drain regions can be, for example, doped portions of a given fin or substrate, or epitaxial regions that are deposited during an etch-and-replace source/drain forming process. The dopant-type in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented with a gate-first process or a gate-last process (sometimes called a replacement metal gate, or RMG, process). Any number of semiconductor materials can be used in forming the transistors, such as group IV materials (e.g., silicon, germanium, silicon germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. For instance, in some example embodiments, such tools may indicate substantially the same distance between the gate cut structure and each of the semiconductor regions of adjacent semiconductor devices, as variously explained herein (e.g., where the distances between the gate cut structure and each of the semiconductor regions of adjacent semiconductor devices are within 1.5 nm or less of each other, such as within 1 nm of each other). In some other example embodiments, such tools may indicate different gate cut structures having different sizes (e.g., different widths) between different sets of semiconductor devices. In some other example embodiments, the distance between all gate cut structures and any adjacent semiconductor region is substantially the same, as variously explained herein. Numerous configurations and variations will be apparent in light of this disclosure.

Architecture

FIG.1is a cross sectional view taken across a plurality of semiconductor devices102a-102d,according to an embodiment of the present disclosure. Each of semiconductor devices102a-102dmay be non-planar metal oxide semiconductor (MOS) transistors, such as tri-gate or gate-all-around (GAA) transistors, although other transistor topologies and types could also benefit from the techniques provided herein.

As can be seen, semiconductor devices102a-102dare formed on a substrate104. Any number of semiconductor devices can be formed on substrate104, but four are used here as an example. Substrate104can be, for example, a bulk substrate including group IV semiconductor material (such as silicon, germanium, or silicon germanium), group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and/or any other suitable material upon which transistors can be formed. Alternatively, the substrate can be a semiconductor-on-insulator substrate having a desired semiconductor layer over a buried insulator layer (e.g., silicon over silicon dioxide). Alternatively, the substrate can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers indium gallium arsenide and indium phosphide). Any number of substrates can be used.

The semiconductor material in each of semiconductor devices102a-102dmay be formed from substrate104. Semiconductor devices102a-102dmay each include fins that can be, for example, native to substrate104(formed from the substrate itself) as illustrated, such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins can be formed of material deposited onto an underlying substrate. In one such example case, a blanket layer of silicon germanium (SiGe) can be deposited onto a silicon substrate, and then patterned and etched to form a plurality of SiGe fins extending from that substrate. In another such example, non-native fins can be formed in a so-called aspect ratio trapping based process, where native fins are etched away so as to leave fin-shaped trenches which can then be filled with an alternative semiconductor material (e.g., group IV or III-V material). In still other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitates forming of nanowires and nanoribbons during a gate forming process where one type of the alternating layers are selectively etched away so as to liberate the other type of alternating layers within the channel region, so that a gate-all-around (GAA) process can then be carried out. Again, the alternating layers can be blanket deposited and then etched into fins, or deposited into fin-shaped trenches.

As can further be seen, adjacent semiconductor devices are separated by a dielectric fill106that may include silicon oxide. Dielectric fill106provides shallow trench isolation (STI) between any adjacent semiconductor devices. Dielectric fill106can be any suitable dielectric material, such as silicon dioxide, aluminum oxide, or silicon oxycarbonitride.

Focusing on semiconductor device102a,but applicable to all semiconductor devices, semiconductor device102aincludes a subfin region108and a semiconductor region110. According to some embodiments, subfin region108comprises the same semiconductor material as substrate104and is adjacent to dielectric fill106. According to some embodiments, semiconductor region110extends above the top surface of dielectric fill106and provides an active region for a transistor (e.g., the semiconductor region beneath the gate).

As noted above, semiconductor region110may represent a fin of semiconductor material or several nanowires or nanoribbons that extend between a source region and a drain region. The source and drain regions are not shown in this particular cross-section. According to some embodiments, the source and drain regions are epitaxial regions that are provided on the fins in an etch-and-replace process. In other embodiments one or both of the source and drain regions could be, for example, implantation-doped native portions of the fins or substrate. Any semiconductor materials suitable for source and drain regions can be used (e.g., group IV and group III-V semiconductor materials). The source and drain regions may include multiple layers such as liners and capping layers to improve contact resistance. In any such cases, the composition and doping of the source and drain regions may be the same or different, depending on the polarity of the transistors. In an example, for instance, one transistor is a p-type MOS (PMOS) transistor, and the other transistor is an n-type MOS (NMOS) transistor. Any number of source and drain configurations and materials can be used.

In some embodiments, a buried conductive layer112is provided within the substrate and adjacent to one or more of the semiconductor devices. In the illustrated example, buried conductive layer112is provided within a portion of substrate104between semiconductor device102band semiconductor device102c.Buried conductive layer112can be any conductive material, such as any metal or metal alloy, that may include any of tungsten, molybdenum, ruthenium, cobalt, copper, aluminum, or silver. According to some embodiments, buried conductive layer112provides a VDD or VSS power rail to various semiconductor devices of the integrated circuit. According to some embodiments, liner dielectric layers114are provided on either side of buried conductive layer112to provide electrical isolation between buried conductive layer112and any neighboring semiconductor devices. Liner dielectric layers114may include silicon oxide or silicon nitride. Liner dielectric layers114can be relatively thin, such as 2 to 6 nm, or thinner so long as it electrically isolates buried conductive layer112from the neighboring semiconductor devices, for the given application.

According to some embodiments, a gate layer116extends over the semiconductor regions110of semiconductor devices102a-102d.It should be noted that a gate dielectric layer would also be present between the semiconductor regions110and gate layer116and is not shown for clarity. Gate layer116may include any sufficiently conductive material such as a metal, metal alloy, or doped polysilicon. According to some embodiments, gate layer116may be interrupted between any adjacent semiconductor devices by a gate cut structure such as gate cut118or gate cut120. The gate cut structures effectively isolate portions of gate layer116from one another to form electrically separate gates for certain semiconductor devices. In the illustrated example, a portion of gate layer116connects the gates of both semiconductor devices102aand102bwhile gate cut118and gate cut120isolates a portion of gate layer116only over semiconductor device102c. Similarly, gate cut120isolates a portion of gate layer116over only semiconductor device102d.

Each of gate cut118and120may be formed from a sufficiently insulating material, such as a dielectric material. Example materials for gate cut118and120include silicon nitride, silicon oxide, or silicon oxynitride. According to some embodiments, gate cut118and gate cut120are formed using a spacer process, as will be discussed herein, which self-aligns gate cut118at the midpoint between semiconductor device102band semiconductor device102cand also self-aligns gate cut120at the midpoint between semiconductor device102cand semiconductor device102d.Accordingly, the gate cut structures may each be aligned at a distance d from the adjacent semiconductor regions110of the adjacent semiconductor devices. As noted above, each distance d is substantially the same (e.g., each distance d is within 1 nm of each other, or within 5 angstroms of each other). The distance d may vary between applications, but in some examples is between about 5 nm and about 25 nm. Further note that distance d can be measured in a consistent fashion, such as the example case where distance d is measured in an imaginary horizontal plane that passes through each of gate cuts118and120as well as the fins, such as the illustrated example with dashed line122. Since the size of a given gate cut structure is determined by the distance between the adjacent semiconductor structures, gate cut structures of different sizes (e.g., different widths) can be formed across the integrated circuit. In the illustrated example, gate cut120has a smaller width than gate cut118because semiconductor devices102cand102dare closer together compared to semiconductor devices102band102c.Furthermore, since the gate cut structures do not rely on traditional lithographic patterning, they can be made very small. In some embodiments, gate cut118and gate cut120each have a width between about 5 nm and about 20 nm.

Fabrication Methodology

FIGS.2A-2L′ are cross-sectional or top-down views that collectively illustrate an example process for forming an integrated circuit configured with self-aligned gate cut structures, in accordance with an embodiment of the present disclosure. Each figure shows an example structure that results from the process flow up to that point in time, so the depicted structure evolves as the process flow continues, culminating in the structure shown inFIGS.2L and2L′, which is similar to the structure illustrated inFIG.1. Such a structure may be part of an overall integrated circuit (e.g., such as a processor or memory chip) that includes, for example, digital logic cells and/or memory cells and analog mixed signal circuitry. Thus, illustrated integrated circuit structure may be part of a larger integrated circuit that includes other integrated circuitry not depicted. Example materials and process parameters are given, but the present disclosure is not intended to be limited to any specific such materials or parameters, as will be appreciated. The use of the prime (′) character denotes a figure having a different viewpoint at the same time in the process flow (e.g.,FIGS.2H and2H′ illustrate the structure at the same point in time from two different view points).

FIG.2Aillustrates cross-sectional view taken through and perpendicular to a set of fins of semiconductor devices102a-102dextending from a substrate104, according to an embodiment of the present disclosure. The previous relevant discussion with respect to example configurations and materials for the substrate104and the fins as well as dielectric fill202is equally applicable here. The fins can be native to the substrate, as illustrated, or non-native to the substrate, or multi-layer fins suitable for forming nanowires or nanoribbons. Likewise, the fins can be, for instance, alternating with respect to transistor polarity. For instance, the fin of semiconductor device102acan include an NMOS material fin (e.g., silicon fin doped with p-type dopants) and the fin of semiconductor device102bcan include a PMOS material fin (e.g., SiGe fin or silicon fin doped with n-type dopants) for a first logic or memory cell. Likewise, the fins of semiconductor devices102cand102dcan include a PMOS material fin and an NMOS material fin, respectively, for a second logic or memory cell. Numerous other configurations can be used, including fins included in integrated circuit sections other than memory or logic sections, such as analog mixed signal sections, input/output sections, radio frequency or transducer sections.

In this example case, a protective layer or cap204is left on the top of each fin, so as to provide the fins a degree of protection during subsequent processing. In cases where the fill dielectric202is an oxide (e.g., silicon dioxide), the cap204can be, for instance, a nitride, oxynitride, a carbide, or an oxycarbonitride so as to provide etch selectivity with respect to the fill dielectric202. As can be further seen, a lithography mask205is patterned to provide an opening for a trench to be etched for where a buried power rail will be deposited. Lithography mask205can be any suitable mask such as, for instance, photoresist or one or more layers (e.g., carbon hard mask or an anti-reflective coating film or a silicon oxynitride) that provide the desired etch selectivity to allow for forming the trench. Note how mask205need not be perfectly aligned to the edge of caps204, given like etch selectivities of mask205and caps204with respect to the trench etch scheme.

Any number of wet and/or dry etching techniques can be used to etch the trench where the buried power rail will be deposited. In this example case, the etch scheme includes a dielectric dry etch that is selective to cap204and mask205, to remove any fill dielectric202(e.g., silicon dioxide) exposed by the opening in mask205. Once the base of the substrate104is reached, the example etch scheme includes a reactive ion etch (RIE) to etch the remainder of the trench within the substrate104(e.g., the area below the dashed line). While dimensions can vary from one example embodiment to the next, in one example case, the total height from the bottom of the etched trench in substrate104to the top of cap204can be 250 nm or more, with the portion of substrate104etched by RIE being in the range of 50 to 100 nm, and with the fins thereabove having a height in the range of 50 to 200 nm (e.g., 60 to 130 nm), and the cap204having a height in the range of 5 to 75 nm. The width of the fins can be, for example, in the range of 5 to 200 nm. The pitch between neighboring fins can be, for example, in the range of 25 to 600 nm. In some such example embodiments, a width-to-height aspect ratio of the fins is in the range of about 1:5 to 1:50, such as the specific example case where the fins are about 5 nm wide at their mid-point, and about 200 nm tall, so as to provide a 1:40 width-to-height aspect ratio.

FIG.2Bis the cross-sectional view of the structure depicted inFIG.2A, after removal of mask205and formation of dielectric liner206and the deposition of conductive material208, according to an embodiment of the present disclosure. Mask205can be removed by any suitable means, such as a selective wet chemical etch. Once the structure is free of mask205, dielectric liner206can be formed. In one example case, dielectric liner206is conformally deposited over the entire structure using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The excess dielectric liner206material in the horizontal locations is then removed using a directional etch which in some embodiments is selective to the fill dielectric202and cap204, but it need not be. The resulting dielectric liner206can have a thickness, for instance, in the range of 0.5 to 5 nm. In a more general sense, dielectric liner206can have any thickness suitable to insulate the conductive material208from touching the neighboring fins defining the sidewalls of the trench. In some example embodiments, dielectric liner206can be implemented with, for instance, an oxide, nitride, or carbide, such as silicon oxide or silicon nitride. In one such embodiment, where fill dielectric202is an oxide and cap204is silicon nitride, dielectric liner206is implemented with a dense silicon oxide, so as to provide a degree of etch selectivity with respect to fill dielectric202and cap204.

Once dielectric liner206has been formed, conductive material208can be deposited by, for example, electroplating, CVD, PVD or ALD. Any excess amount of conductive material208extending out of the trench (e.g., above cap layer204) can be polished away by way of a planarization/polishing technique such as chemical mechanical polishing (CMP). Conductive material208can be any number of conductive materials, such as tungsten, molybdenum, ruthenium, cobalt, copper, aluminum, silver, or alloys thereof. Further note that conductive material208can run parallel to the fins for any desired distance.

FIG.2Cis the cross-sectional view of the structure depicted inFIG.2B, after recessing conductive material208, followed by reforming another dielectric fill202′ over conductive material208, according to an embodiment. In some example cases, the recessing of conductive material208is accomplished using an isotropic metal etch process selective to fill dielectric202, cap204, and dielectric liner206. The depth of the recess will depend on the desired height of the final buried power rail, but in some example cases is in the range of 20 to 200 nm (e.g., 50 to 130 nm). The height of the recessed conductive material208can vary as well, but in some example cases, is in the range of about 20 to 500 nm (e.g., 30 to 90 nm).

Following the recess of conductive material208, another dielectric fill202′ is deposited to fill the trench and is planarized before both dielectric fill202and dielectric fill202′ are recessed back together, according to an embodiment. In some embodiments, dielectric fill202′ is the same material as dielectric fill202. Note that dielectric liner206is also recessed in this process. In some such cases, the fins are silicon, and fill dielectric202and202′ along with dielectric liner206are an oxide (e.g., silicon dioxide), so as to allow for a singular etch selectivity with respect to the silicon fins. In some example cases, the remaining thickness of fill dielectric202′ remaining above the recessed conductive material208is in the range of about 5 to 25 nm (e.g., 15 nm).

FIG.2Dis the cross-sectional view of the structure depicted inFIG.2C, after the formation of spacer structures210, according to an embodiment. Spacer structures210may be formed by initially depositing the spacer material over all exposed surfaces, and then etching back the spacer material using an anisotropic etching process (e.g., RIE). The directional etching process results in the spacer material being removed from horizontal surfaces, but remaining along the sidewalls of the fins and also on sidewalls of cap204. Accordingly, the height of spacer structures210is determined by the thickness of cap204and the height of the fins that extend above the top surface of fill dielectric202. Unlike typical gate spacers, spacer structures210comprise an amorphous semiconductor material, such as amorphous silicon (a-Si) or amorphous germanium (a-Ge), according to some embodiments. Although widths may vary based on the application, spacer structures210may have a width between about 5 nm and about 15 nm. The top corners of spacer structures210may be etched away and display a sloped profile (as illustrated) due to the etch-back process. As previously noted,FIG.2Dmay not be drawn to scale in that the height of cap204may be greater than the height of the fin that extends above the top surface of dielectric fill202.

FIG.2Eis the cross-sectional view of the structure depicted inFIG.2D, after the formation of fill material212and the removal of caps204, according to an embodiment. Fill material212substantially fills the regions between adjacent spacer structures from adjacent semiconductor devices. According to some embodiments, fill material212marks locations for potential gate cuts in the final structure. Fill material212may be another semiconductor material that is different from the semiconductor material of spacer structures210such that there can be sufficient etch selectivity between fill material212and spacer structures210. In some examples, fill material212is amorphous silicon germanium (a-SiGe) while spacer structures210are amorphous silicon (a-Si). In some other examples, both fill material212and spacer structures210include a-SiGe but with different germanium concentrations such that sufficient etch selectivity can be achieved between the two materials. Fill material212may be deposited using any conventional deposition technique, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD) followed by a polishing process (e.g., using CMP) to planarize the top surface of fill material212.

FIG.2Fis the cross-sectional view of the structure depicted inFIG.2E, after filling the recesses left behind from the removal of caps204to form capping structures214, according to an embodiment. According to some embodiments, the recesses are filled with the same material as spacer structures210, such that capping structures214include the same material over the sidewalls and top surfaces of the fins. Accordingly, capping structures214may be composed of a-Si, a-Ge, or a-SiGe. The top surface of capping structures214may be planarized using one or more CMP processes. Multiple CMP stages may be used due to the unevenness of the capping structure material following its deposition.

FIG.2Gis the cross-sectional view of the structure depicted inFIG.2F, after polishing back below any sloped corners of capping structures214and depositing gate cap structures216to form additional transistor structures, according to an embodiment. Gate cap structures216may be strips of a dielectric material that run perpendicular to the lengths of the fins. In some embodiments, gate cap structures216include silicon nitride. Once gate cap structures216have been deposited and patterned into strips, additional transistor formation steps can take place to define locations of various transistors and form the source and drain regions for each of the transistors.

FIGS.2G′ and2G″ illustrate top-down views of the process used to define the transistor locations and the source/drain regions, according to some example embodiments. As seen inFIG.2G′, gate cap structures216are patterned across different sections of fin218and fin220. Once gate cap structures216are patterned, all other semiconductor material around fins218and220and not covered by gate cap structures216is etched away (fins218and220may be protected by a thin dielectric layer, such as a thin silicon oxide). Any of the preceding discussion with regards to semiconductor fins applies to both fin218and fin220. The width of gate cap structures216defines the gate lengths of the transistors and may be anywhere in the range of 5 nm to 200 nm. Gate cap structures216may be patterned to be equidistant from one another (as illustrated), though this is not required.

FIG.2G″ illustrates further transistor formation steps that are performed to define individual transistors along fins218and220, according to some embodiments. Gate cap structures216are removed using, for example, dry or wet etchants that selectively remove the material of gate cap structures216(e.g., silicon nitride). Removal of the gate cap structures216exposes the pattern of fill material212and capping structures214that extend orthogonal to fins218and220. According to some embodiments, capping structures214are observed over and around each fin while fill material212is observed between each adjacent pair of capping structures214. Gate spacers222are formed along the sidewalls of the semiconductor material (e.g., both fill material212and capping structures214) that had been masked by the gate cap structures216. The gate spacers222may be formed using a similar etch-back process as the one used to form spacer structures210. Gate spacers222may include a dielectric material, such as silicon nitride, silicon oxy-nitride, or any formulation of those layers incorporating carbon or boron dopants.

Following the formation of gate spacers222, source or drain regions224are formed at the locations of the exposed portions of fins218and220, according to some embodiments. The source and drain regions may be formed using any of the techniques discussed above.

According to some embodiments, the processes used to form the additional transistor structures, such as the formation of source or drain regions224, may involve high temperature processes that affect the material of either or both fill material212and capping structures214. In examples where either fill material212or capping structures214includes an amorphous material, the application of high temperatures may cause the amorphous material to partially crystalize and become a polycrystalline material. Thus, according to some embodiments, the amorphous silicon of capping structures214may become polysilicon and the amorphous silicon germanium of fill material212may become polycrystalline silicon germanium.

FIG.2His the cross-sectional view of the structure depicted inFIG.2G, after forming a mask material226, according to an embodiment. Mask material226may be used to expose certain regions of fill material212and protect other regions of fill material212as seen more clearly inFIG.2H′. Mask material226can be any type of photoresist or hard mask material, such as a carbon hard mask (CHM). Note that due to the etch selectively between fill material212and capping structures214, mask material226does not require perfect alignment over fill material212.

FIG.2H′ illustrates a top-down view of the example structure depicted inFIG.2Hwhere openings228in mask material226are identified by dashed lines. Masked material226itself is not shown for clarity. As is observed in the figure, some regions of fill material212are exposed as they are within any of openings228while other regions of fill material212are protected beneath mask material226(e.g., everywhere outside of the dashed boxes). Any mask material226pattern can be created to expose any number of regions of fill material212.

FIG.21illustrates a top-down view of the structure depicted inFIG.2H′ after removing the exposed regions of fill material212, according to an embodiment. A wet or dry etchant process may be used to selectively remove fill material212while maintaining any exposed portions of capping structures214. In an example where fill material212includes SiGe and capping structures214include Si, the SiGe may be etched in a plasma that includes CF4 at a microwave power between 600 W and 800 W and a pressure between about 300 mTorr and about 400 mTorr. Regions of fill material212that are protected by mask material226are unaffected by the etch. According to some embodiments, fill material212is removed in areas where gate cuts are to be formed.

FIG.2Jillustrates a top-down view of the structure depicted inFIG.21after removing mask material226and forming gate cut structures230within the recesses left behind after removal of the exposed regions of fill material212, according to an embodiment. According to some embodiments, gate cut structures230are formed using any standard deposition technique such as ALD, CVD, or some combination thereof. Gate cut structures230may be formed from any sufficiently electrically insulating material such as a dielectric material. In some embodiments, gate cut structures230comprise silicon nitride. The gate cut structure material may be polished back after deposition using, for example, CMP. At this stage, some regions between adjacent capping structures214include gate cut structures230while other regions include fill material212. Any pattern of gate cut structures230and fill material212may be used depending on the integrated circuit design.

FIG.2Killustrates a top-down view of the structure depicted inFIG.2Jafter removing all fill material212and capping structures214, according to an embodiment. A wet or dry etchant process may be used to remove both fill material212and capping structures214together. In an example where fill material212includes SiGe and capping structures214include Si, an anisotropic RIE process may be used to etch through both the SiGe and the Si at substantially the same rate. This RIE process may be similar to the one used to initially form the fins from substrate104. Note that spacer structures222remain after the etching process to define the trenches where the gate material will be deposited.

The removal of capping structures214expose the fin portions of the various semiconductor devices. Four particular semiconductor devices232-238are identified inFIG.2K. In this example, due to the presence of gate cut structure230, the gate of semiconductor device232will be isolated from the gate of semiconductor device234. Additionally, in this example, since there is no gate cut structure230between semiconductor device236and semiconductor device238, the gates of semiconductor devices236and238will be connected together. In this way, various semiconductor devices can either have their gates isolated from one another or connected together depending on the pattern of gate cut structures230.

It should be noted that remaining steps to complete the formation of the semiconductor regions231of each semiconductor device may be performed at this stage of the process. In some examples, this includes the deposition of a gate dielectric layer over the exposed semiconductor regions231and/or removal of sacrificial layers in the case of GAA structures. The gate dielectric layer may include any suitable dielectric (such as silicon dioxide, and/or a high-k dielectric material). Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

FIG.2Lillustrates a top-down view of the structure depicted inFIG.2Kafter forming gate layer240in all of the regions previously occupied by fill material212and capping structures214, according to an embodiment. Gate layer240can include any conductive material, such as a metal, metal alloy, or polysilicon. Gate layer240may be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD, to name a few examples. According to some embodiments, gate layer240runs orthogonally over a plurality of parallel fins such that it extends over the semiconductor regions of a plurality of different semiconductor devices. According to some embodiments, each gate layer240may be interrupted by one or more of the gate cut structures230to electrically isolate various portions of gate layer240from one another.FIG.2L′ illustrates a cross-section view of the same example structure fromFIG.2Lshowing how gate cut structures230aand230bcut through the entire thickness of gate layer240between adjacent semiconductor devices.

As noted above, due to use of spacer structures210during the fabrication process of the sacrificial gate material, gate cut structures230aand230bare self-aligned at the midpoint between adjacent semiconductor devices. Also, since the size of a given gate cut structure is determined by the original distance between the adjacent semiconductor structures, gate cut structures of different sizes (e.g., different widths) can be formed across the integrated circuit. In the illustrated example, the left gate structure230ais wider than the right gate cut structure230b.

FIG.3illustrates an example embodiment of a chip package300, in accordance with an embodiment of the present disclosure. As can be seen, chip package300includes one or more dies302. One or more dies302may include at least one integrated circuit having semiconductor devices, such as any of the semiconductor devices disclosed herein. One or more dies302may include any other circuitry used to interface with other devices formed on the dies, or other devices connected to chip package300, in some example configurations.

As can be further seen, chip package300includes a housing304that is bonded to a package substrate306. The housing304may be any standard or proprietary housing, and may provide, for example, electromagnetic shielding and environmental protection for the components of chip package300. The one or more dies302may be conductively coupled to a package substrate306using connections308, which may be implemented with any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid array (BGA), pins, or wire bonds, to name a few examples. Package substrate306may be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive pathways (e.g., including conductive vias and lines) extending through the dielectric material between the faces of package substrate306, or between different locations on each face. In some embodiments, package substrate306may have a thickness less than 1 millimeter (e.g., between 0.1 millimeters and 0.5 millimeters), although any number of package geometries can be used. Additional conductive contacts312may be disposed at an opposite face of package substrate306for conductively contacting, for instance, a printed circuit board (PCB). One or more vias310extend through a thickness of package substrate306to provide conductive pathways between one or more of connections308to one or more of contacts312. Vias310are illustrated as single straight columns through package substrate306for ease of illustration, although other configurations can be used (e.g., damascene, dual damascene, through-silicon via, or an interconnect structure that meanders through the thickness of substrate306to contact one or more intermediate locations therein). In still other embodiments, vias310are fabricated by multiple smaller stacked vias, or are staggered at different locations across package substrate306. In the illustrated embodiment, contacts312are solder balls (e.g., for bump-based connections or a ball grid array arrangement), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). In some embodiments, a solder resist is disposed between contacts312, to inhibit shorting.

In some embodiments, a mold material314may be disposed around the one or more dies302included within housing304(e.g., between dies302and package substrate306as an underfill material, as well as between dies302and housing304as an overfill material). Although the dimensions and qualities of the mold material314can vary from one embodiment to the next, in some embodiments, a thickness of mold material314is less than 1 millimeter. Example materials that may be used for mold material314include epoxy mold materials, as suitable. In some cases, the mold material314is thermally conductive, in addition to being electrically insulating.

Methodology

FIG.4is a flow chart of a method400for forming at least a portion of an integrated circuit, according to an embodiment. Various operations of method400may be illustrated inFIGS.2A-2L′. However, the correlation of the various operations of method400to the specific components illustrated in the aforementioned figures is not intended to imply any structural and/or use limitations. Rather, the aforementioned figures provide one example embodiment of method400. Other operations may be performed before, during, or after any of the operations of method400. For example, method400does not explicitly describe many steps that are performed to form common transistor structures. Some of the operations of method400may be performed in a different order than the illustrated order.

Method400begins with operation402where at least first and second parallel semiconductor fins are formed, according to some embodiments. The semiconductor material in the fins may be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins can be formed of material deposited onto an underlying substrate. In one such example case, a blanket layer of silicon germanium (SiGe) can be deposited onto a silicon substrate, and then patterned and etched to form a plurality of SiGe fins extending from that substrate. In another such example, non-native fins can be formed in a so-called aspect ratio trapping based process, where native fins are etched away so as to leave fin-shaped trenches which can then be filled with an alternative semiconductor material (e.g., group IV or III-V material). In still other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitates forming of nanowires and nanoribbons during a gate forming process where one type of the alternating layers are selectively etched away so as to liberate the other type of alternating layers within the channel region, so that a gate-all-around (GAA) process can then be carried out. Again, the alternating layers can be blanket deposited and then etched into fins, or deposited into fin-shaped trenches. The fins also include a cap structure over each fin that is used to define the locations of the fins during, for example, an RIE process. The cap structure may be a dielectric material, such as silicon nitride.

Method400continues with operation404where spacer structures are formed on sidewall portions of at least the first and second fins, according to some embodiments. The spacer structures may also be formed along sidewall portions of the cap structures on the fins. The spacer structures may be formed by initially depositing the spacer material over all exposed surfaces, and then etching back the spacer material using an anisotropic etching process (e.g., RIE). The directional etching process results in the spacer material being removed from horizontal surfaces, but remaining along the sidewalls of the fins and also on sidewalls of the cap structures. Accordingly, the height of the spacer structures is determined by the thickness of the cap structures and the height of the fins that extend above the top surface of a fill dielectric (e.g., STI dielectric). Unlike typical gate spacers, these spacer structures include an amorphous semiconductor material, such as amorphous silicon (a-Si) or amorphous germanium (a-Ge), according to some embodiments.

Method400continues with operation406where a sacrificial material is deposited between adjacent spacer structures from adjacent fins (such as first and second fins), according to some embodiments. The sacrificial material marks locations for potential gate cuts in the final structure. The sacrificial material may be another semiconductor material that is different from the semiconductor material of the spacer structures such that there can be sufficient etch selectivity between the sacrificial material and the spacer structures. In some examples, the sacrificial material is amorphous silicon germanium (a-SiGe) while the spacer structures are amorphous silicon (a-Si). In some other examples, both the sacrificial material and the spacer structures include a-SiGe but with different germanium concentrations such that sufficient etch selectivity can be achieved between the two materials. The sacrificial material may be deposited using any conventional deposition technique, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), Atomic Layer Deposition (ALD) or physical vapor deposition (PVD) followed by a polishing process (e.g., using CMP) to planarize the top surface of the sacrificial material.

Method400continues with operation408where the cap structures over the fins are removed and filled with the material used to form the spacer structures, according to some embodiments. The combination of the newly deposited material and the spacer structures can form capping structures composed of a-Si, a-Ge, or a-SiGe, to name a few examples, that wrap around the sides and top of the fins. The top surface of the capping structures may be planarized using one or more CMP processes.

Method400continues with operation410where the sacrificial material between the spacer structures is removed, according to some embodiments. An isotropic wet or dry etchant process may be used to selectively remove the sacrificial material while maintaining any exposed portions of the capping structures. In an example where the sacrificial material includes SiGe and the capping structures include Si, the SiGe may be etched in a plasma that includes CF4 at a microwave power between 600 W and 800 W and a pressure between about 300 mTorr and about 400 mTorr. Some regions of the sacrificial material may be protected by a mask material (such as a Carbon Hard Mask CHM) and are unaffected by the etch. According to some embodiments, the sacrificial material is removed in areas where gate cuts are to be formed.

Method400continues with operation412where gate cut structures are formed in the recesses created by the removal of the sacrificial material, according to some embodiments. The gate cut structures will ultimately act as the gate cuts after deposition of the gate layer. In some embodiments, the gate cut structures include silicon nitride or some other semiconductor nitride. Due to the formation of the spacer structures of substantially equal width, the gate cut structures will be self-aligned between adjacent fins without the need for any lithography-based alignment.

Method400continues with operation414where a gate layer is formed over at least the first and second fins after removal of the capping structures, according to some embodiments. The gate layer will be interrupted by the presence of any gate cut structures formed during operation412, thus isolating the gates of semiconductor devices on either side of the gate cut structures. In one example where a gate cut structure is formed between the first and second fins, semiconductor devices formed from the first and second fins will have their gates isolated from one another due to the gate cut structure interrupting the gate layer across the first and second fins. The gate layer can include any conductive material, such as a metal, metal alloy, or polysilicon. The gate layer may be deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD, to name a few examples.

Example System

FIG.5is an example computing system implemented with one or more of the integrated circuit structures as disclosed herein, in accordance with some embodiments of the present disclosure. As can be seen, the computing system500houses a motherboard502. The motherboard502may include a number of components, including, but not limited to, a processor504and at least one communication chip506, each of which can be physically and electrically coupled to the motherboard502, or otherwise integrated therein. As will be appreciated, the motherboard502may be, for example, any printed circuit board (PCB), whether a main board, a daughterboard mounted on a main board, or the only board of system500, etc.

The communication chip506also may include an integrated circuit die packaged within the communication chip506. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor504(e.g., where functionality of any chips506is integrated into processor504, rather than having separate communication chips). Further note that processor504may be a chip set having such wireless capability. In short, any number of processor504and/or communication chips506can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

Further Example Embodiments

Example 1 is an integrated circuit that includes a first semiconductor device having a first semiconductor region extending between a first source region and a first drain region, a second semiconductor device having a second semiconductor region extending between a second source region and a second drain region, a gate layer comprising a conductive material and extending over the first semiconductor region and the second semiconductor region, and a gate cut structure comprising a dielectric material. The gate cut structure is between the first semiconductor device and the second semiconductor device such that the gate cut structure interrupts the gate layer. A first distance between the gate cut structure and the first semiconductor region is substantially the same as a second distance between the gate cut structure and the second semiconductor region.

Example 2 includes the subject matter of Example 1, wherein the first semiconductor region is a first fin comprising silicon or germanium or both, and the second semiconductor region is a second fin comprising silicon or germanium or both, the first fin orientated parallel to the second fin.

Example 3 includes the subject matter of Example 1 or 2, wherein the first semiconductor region comprises a first plurality of semiconductor nanoribbons and the second semiconductor region comprises a second plurality of semiconductor nanoribbons.

Example 4 includes the subject matter of Example 3, wherein the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons comprise germanium, silicon, or both.

Example 5 includes the subject matter of any one of Examples 1-4, wherein the first and second semiconductor devices are on or above a substrate, and the integrated circuit further comprises a buried conductive layer within or below the substrate and below the gate cut structure.

Example 6 includes the subject matter of any one of Examples 1-5, wherein the dielectric material comprises silicon and nitrogen or comprises silicon and oxygen.

Example 7 includes the subject matter of any one of Examples 1-6, wherein the gate cut structure is a first gate cut structure and the integrated circuit further comprises a second gate cut structure between the second semiconductor device and a third semiconductor device.

Example 8 includes the subject matter of Example 7, wherein the first gate cut structure has a first width and the second gate cut structure has a second width that is smaller than the first width.

Example 9 includes the subject matter of any one of Examples 1-8, wherein the first distance between the gate cut structure and the first semiconductor region is within 1 nm of the second distance between the gate cut structure and the second semiconductor region.

Example 10 includes the subject matter of any one of Examples 1-9, wherein the first distance between the gate cut structure and the first semiconductor region is within 5 angstroms of the second distance between the gate cut structure and the second semiconductor region.

Example 11 includes the subject matter of any one of Examples 1-10, wherein the gate cut structure has a width between about 5 nm and about 20 nm.

Example 12 is a printed circuit board comprising the integrated circuit of any one of Examples 1-11.

Example 13 is an electronic device that includes a chip package having one or more dies. At least one of the one or more dies includes a first semiconductor device having a first semiconductor region extending between a first source region and a first drain region, a second semiconductor device having a second semiconductor region extending between a second source region and a second drain region, a gate layer comprising a conductive material and extending over the first semiconductor region and the second semiconductor region, and a gate cut structure comprising a dielectric material. The gate cut structure is between the first semiconductor device and the second semiconductor device such that the gate cut structure interrupts the gate layer. A first distance between the gate cut structure and the first semiconductor region is substantially the same as a second distance between the gate cut structure and the second semiconductor region.

Example 14 includes the subject matter of Example 13, wherein the first semiconductor region is a first fin comprising silicon or germanium or both, and the second semiconductor region is a second fin comprising silicon or germanium or both, the first fin orientated parallel to the second fin.

Example 15 includes the subject matter of Example 13 or 14, wherein the first semiconductor region comprises a first plurality of semiconductor nanoribbons and the second semiconductor region comprises a second plurality of semiconductor nanoribbons.

Example 16 includes the subject matter of Example 15, wherein the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons comprise germanium, silicon, or both.

Example 17 includes the subject matter of any one of Examples 13-16, wherein the first and second semiconductor devices are on or above a substrate, and the integrated circuit further comprises a buried conductive layer within or below the substrate and below the gate cut structure.

Example 18 includes the subject matter of any one of Examples 13-17, wherein the dielectric material comprises silicon and nitrogen or comprises silicon and oxygen.

Example 19 includes the subject matter of any one of Examples 13-18, wherein the gate cut structure is a first gate cut structure and the integrated circuit further comprises a second gate cut structure between the second semiconductor device and a third semiconductor device.

Example 20 includes the subject matter of Example 19, wherein the first gate cut structure has a first width and the second gate cut structure has a second width that is smaller than the first width.

Example 21 includes the subject matter of any one of Examples 13-20, wherein the gate cut structure has a width between about 5 nm and about 20 nm.

Example 22 includes the subject matter of any one of Examples 13-21, wherein the electronic device further comprises a printed circuit board, wherein the chip package is attached to the printed circuit board.

Example 23 is a method of forming an integrated circuit. The method includes forming a first fin comprising first semiconductor material and a second fin comprising second semiconductor material, wherein the first fin and the second fin extend parallel to one another, the first fin having a first cap structure on a top surface of the first fin and the second fin having a second cap structure on a top surface of the second fin; forming a first spacer structure comprising a first material on at least a first side of the first fin facing the second fin and a second spacer structure comprising the first material on at least a second side of the second fin facing the first fin; depositing a second material different from the first material into a region between the first and second spacer structures; removing the cap structure and depositing the first material onto the top surface of the first fin and the second fin; removing the second material from between the first and second spacer structures; depositing a dielectric material into the region between the first and second spacer structures; and forming a gate over the first semiconductor material and over the second semiconductor material, wherein the dielectric material interrupts the gate between the first semiconductor material and the second semiconductor material.

Example 24 includes the subject matter of Example 23, wherein forming the first fin and the second fin comprises recessing a dielectric layer between the first and the second fins such that the first and the second fins extend above a top surface of the dielectric layer.

Example 25 includes the subject matter of Example 23 or 24, wherein a first distance between the dielectric material and the first semiconductor material is substantially the same as a second distance between the dielectric material and the second semiconductor material.

Example 26 includes the subject matter of any one of Examples 23-25, wherein the first material comprises amorphous silicon and the second material comprises amorphous silicon and germanium.

Example 27 includes the subject matter of Example 26, further comprising converting the amorphous silicon of the first material into polysilicon and converting the amorphous silicon and germanium of the second material into polycrystalline silicon and germanium.

Example 28 includes the subject matter of any one of Examples 23-27, wherein the first fin and the second fin are formed on a substrate, and the method further comprises forming a buried conductive layer within the substrate.

Example 29 includes the subject matter of Example 28, wherein the region between the first and second spacer structures is over the buried conductive layer.