CMOS circuit for providing a bandcap reference voltage

A low voltage submicron CMOS circuit (10) for providing an output bandgap voltage (V.sub.BG) that is substantially independent of temperature and power supply variations has been provided. The CMOS circuit utilizes parasitic transistors (28-30) to create a delta voltage that has a positive temperature coefficient across a differential pair of NMOS transistors (14, 16). This delta voltage is then converted into differential currents which are amplified and mirrored and summed together to provide an output current (I.sub.O) that has a positive temperature coefficient. This output current is then passed through a series network including a resistor element (52) and a parasitic PNP junction transistor (31) to provide a bandgap voltage of 1.2 volts wherein the voltage across the resistor element has a positive temperature coefficient and the voltage across the parasitic PNP junction transistor has an inherent negative temperature coefficient.

FIELD OF THE INVENTION 
This invention relates to voltage reference circuits and, in particular, to 
a low voltage submicron CMOS circuit for providing a bandgap voltage that 
is referenced to a power supply terminal. 
BACKGROUND OF THE INVENTION 
Bandgap voltage reference circuits are well known and widely used in the 
art for providing an output voltage of 1.2 volts or greater that is 
substantially independent of temperature. The output voltage has a 
substantially zero temperature coefficient and is produced by summing 
together two voltages such that one of the voltages has a positive 
temperature coefficient while the other has a negative temperature 
coefficient. 
Typically, the positive temperature coefficient is produced by using first 
and second bipolar transistors operating at different current densities 
such that the first bipolar transistor is operating at a lower current 
density than the second bipolar transistor. This amplified positive 
temperature coefficient voltage is then combined in series with the 
V.sub.BE voltage of a third bipolar transistor which inherently has a 
negative temperature coefficient such that a composite output voltage 
having a very low or substantially zero temperature coefficient is 
provided. 
It would desirable to provide a bandgap voltage in low voltage submicron 
CMOS technology. However, most CMOS bandgap circuits are manufactured 
utilizing 5 volt CMOS technology. Moreover, many bandgap circuits provide 
a differential bandgap reference voltage that is not referenced to any 
power supply rail. However, in particular applications, such as low 
voltage submicron CMOS applications, it is desirable to provide a bandgap 
reference voltage that will operate at reduced power supply voltages and 
can be referenced to a power supply terminal. 
Hence, there exists a need for an improved bandgap circuit utilizing low 
voltage submicron CMOS technology for providing a bandgap voltage 
referenced to a power supply terminal.

DETAILED DESCRIPTION OF THE DRAWING 
Referring to the sole figure, there is illustrated CMOS circuit 10 for 
providing output voltage V.sub.BG that is a bandgap voltage (1.2 volts) 
which is substantially independent of temperature and power supply 
variations. CMOS circuit 10 is designed with an eye toward low voltage 
(3.3 volts) submicron CMOS technology but it should be understood that 
circuit 10 may also be applicable to higher voltage (5 volt) CMOS 
technology. 
CMOS circuit 10 includes a differential pair of MOS transistors as 
represented by box 12 which includes NMOS transistors 14 and 16. The 
source electrodes of transistors 14 and 16 are coupled through current 
source transistor 18 to a first supply voltage terminal at which the 
operating potential V.sub.SS is applied. In a preferred embodiment, 
operating potential V.sub.SS is ground potential. 
Transistor 18 has a drain electrode coupled to the common source electrodes 
of transistors 14 and 16, and a source electrode returned to ground. The 
control/gate electrode of transistor 18 is coupled to the gate and drain 
electrodes of NMOS transistor 20 wherein NMOS transistor 20 and PMOS 
transistors 22 and 24 comprise bias circuit 26. 
The source electrode of transistor 20 is returned to ground. The drain 
electrode of transistor 20 is coupled to the drain electrode of transistor 
22 the latter having a gate electrode returned to ground and coupled to 
the control electrode of transistor 24. The source electrodes of 
transistors 22 and 24 are coupled to a second supply voltage terminal at 
which the operating potential V.sub.DD is applied. The drain electrode of 
transistor 24 is coupled to the control electrode of NMOS transistor 14. 
Transistors 28 through 31 are parasitic PNP transistors of a CMOS process 
wherein the collector of each parasitic transistor takes the form of the 
P-substrate of the N-well CMOS process, each base takes the form of an 
N-well region, and each emitter takes the form of the P+ source/drain 
implant region of a PMOS transistor. Moreover, it is worth noting that 
although transistors 28-31 are parasitic PNP transistors that are 
typically available in a P-type substrate CMOS process, if an N-type 
substrate CMOS process were utilized, then transistors 28-31 would 
equivalently be parasitic NPN transistors. 
In particular, parasitic transistor 28 has an emitter coupled to the 
control electrode of transistor 14 while the emitter of parasitic 
transistor 29 is coupled to the control electrode of transistor 16. The 
bases of parasitic transistors 28 and 29 are coupled to the emitter of 
parasitic transistor 30 the latter having a base returned to ground. The 
collectors of parasitic transistors 28-30 are also returned to ground. 
The drain electrode of NMOS transistor 14 is coupled to the drain and gate 
electrodes of PMOS transistor 34 and to the gate electrode of PMOS 
transistor 36. The source electrodes of PMOS transistors 34 and 36 are 
coupled to receive operating potential V.sub.DD. 
The drain electrode of NMOS transistor 16 is coupled to the drain and 
control electrodes of PMOS transistor 38 and to the control electrode of 
PMOS transistor 40. The source electrodes of PMOS transistors 38 and 40 
are coupled to receive operating potential V.sub.DD. 
The drain electrode of PMOS transistor 36 is coupled to the drain and 
control electrodes of NMOS transistor 42 and to the control electrode of 
NMOS transistor 44. The source electrodes of NMOS transistors 42 and 44 
are returned to ground. 
The drain electrodes of transistors 40 and 44 are coupled together at 
summing node 46 wherein output voltage V.sub.BG is provided at summing 
node 46. 
Resistor element 50 is coupled between summing node 46 and the emitter of 
parasitic PNP transistor 31 the latter having its base and collector 
returned to ground thereby forming a junction diode. 
Resistor element 50 includes NMOS transistor 52 having a drain electrode 
coupled to summing node 46 and a source electrode coupled to the emitter 
of parasitic PNP transistor 31. The control electrode of transistor 52 is 
coupled to receive operating potential V.sub.DD. 
CMOS circuit 10 further includes bias circuit 54 which includes PMOS 
transistors 56 and 58 each having its source electrode coupled to receive 
operating potential V.sub.DD and their control electrodes returned to 
ground. The drain electrode of PMOS transistor 56 is coupled to the 
control electrode of NMOS transistor 16 while the drain electrode of PMOS 
transistor 58 is coupled to the emitter of parasitic transistor 30. 
In operation, transistors 28-29 are appropriately sized so as to provide a 
delta voltage (.DELTA.V) between the control electrodes of transistors 14 
and 16. Moreover, transistors 28-30 provide an appropriate voltage to the 
control electrodes of transistors 14 and 16 so as to allow the transistors 
to operate in a normal mode. In particular, the delta voltage (.DELTA.V) 
appearing across the control electrodes of transistors 14 and 16 can be 
represented as shown in . 1. 
EQU .DELTA.V=V.sub.G16 -V.sub.G14 . 1 
where 
V.sub.G14, V.sub.G16 are the gate to source voltages of NMOS transistors 14 
and 16, respectively. 
Also, .DELTA.V may be expressed as a logarithmic function of the currents 
flowing through transistors 14 and 16 as shown in . 2. 
##EQU1## 
where 
KT/q represents the thermal voltage of a silicon junction; 
I.sub.x, I.sub.y are the currents flowing through PNP transistors 28 and 
29, respectively; and 
m is a multiple that the emitter area of transistor 28 is with respect to 
transistor 29, i.e., A.sub.E28 =m*A.sub.E29. 
Thus, from . 2 it is clear that the .DELTA.V that is generated between 
the control electrodes of transistors 14 and 16 has a positive temperature 
coefficient since it is a function of the term kT/q. 
One can also express the current I.sub.1 which is the current flowing 
through NMOS transistor 16 as shown in 3. 
EQU I.sub.1 =.beta..sub.1 (.DELTA.V+V.sub.G14 -V.sub.T).sup.2 . 3 
where 
V.sub.T is the NMOS threshold voltage of transistors 14 and 16; and 
.beta..sub.1 is the gain of transistors 14 and 16 which is a function of 
the ratio of the width and length (W/L) of the transistors, mobility 
(.mu.) and unit gate capacitance (C.sub.O). 
Similarly, the current I.sub.2 which is the current flowing through NMOS 
transistor 14 can be represented as shown in . 4. 
EQU I.sub.2 =.beta..sub.1 (V.sub.G14 -V.sub.T).sup.2 . 4 
Referring back to the sole figure, current I.sub.2 (the current flowing 
through transistor 14) is mirrored through transistors 34, 36, 42 and 44 
thereby providing current I.sub.2 ' flowing through NMOS transistor 44. 
Similarly, current I.sub.1 (the current flowing through transistor 16) is 
mirrored through transistors 38 and 40 to provide current I.sub.1 ' 
flowing through transistor 40. 
Currents I.sub.1 ' and I.sub.2 ' are amplified versions of currents I.sub.1 
and I.sub.2, respectively, by adjusting the widths of current mirror 
transistors 34, 36, 42, 44, 38 and 40. For example, in a preferred 
embodiment, suppose that the widths of current mirror transistors 34 and 
38 have a width as denoted by W.sub.0 while current mirror transistors 36, 
40 and 42 have a width as denoted by W.sub.1. Also, suppose that the width 
of transistor 44 has a width of W.sub.2. 
Using these widths for the current mirror transistors and the s. 1-4, 
one can obtain an expression for the output current I.sub.O that flows out 
of summing node 46 and through resistor 50 and transistor 31 as shown in 
s. 5A and 5B. Thus, bias circuits 26 and 54, transistors 14, 16, 34, 
38, 36, 40, 42, and 44, and parasitic transistors 28, 29, and 30 cooperate 
to form a CMOS circuit for providing a current having a positive 
temperature coefficient. 
##EQU2## 
As can be seen from . 5B, the first term represents a term that has a 
positive temperature coefficient since it includes the term .DELTA.V. The 
second term is a DC error term which can be made negligible by 
appropriately choosing the width W.sub.2 of transistors 44. Also, the 
third term is a second order error term which can also be made small by 
setting 2(V.sub.G14 -V.sub.T)&gt;.DELTA.V. 
Since resistor 50 is an NMOS transistor, its resistance value is simply the 
inverse of its transconductance or can be more appropriately expressed as 
shown in . 6. 
##EQU3## 
where .beta..sub.2 is the gain of transistor 52; 
Output voltage V.sub.BG is then equal to current I.sub.O multiplied by 
resistor R plus an emitter voltage appearing across transistor 31 which 
can be expressed as shown in . 7. 
##EQU4## 
where .PHI..sub.E is the base emitter voltage of transistor 31. 
From . 7, it can be seen that the output voltage appearing at circuit 
node 46 is a combination of two terms. The first term, which includes the 
.DELTA.V expression, has a positive temperature coefficient since .DELTA.V 
was a function of KT/q as shown in . 2. The second term (.PHI..sub.E), 
which is the base emitter voltage appearing across transistor 31, has a 
negative temperature coefficient as is well known for bipolar junction 
transistors. Thus, by appropriately choosing the values of .beta..sub.1 
and .beta..sub.2 and W.sub.1 and W.sub.0, the positive temperature 
coefficient of the first term can be made substantially equal to the 
negative temperature coefficient of the second term thereby resulting in 
an output bandgap voltage V.sub.BG that is substantially independent of 
temperature variations. 
Moreover, by using NMOS transistor 52 to function as a resistor, output 
voltage V.sub.BG can be made to be substantially independent of power 
supply variations because the resistance value of NMOS transistor 52 is a 
function of operating potential V.sub.DD as shown in . 6. In 
particular, it has been shown that by adjusting the width of transistor 
52, one can fine tune the positive temperature coefficient while adjusting 
the width of transistor 44 will provide optimum power supply rejection. 
Thus, output V.sub.BG can be made to be substantially independent of 
temperature as well as power supply variations and is referenced with 
respect to operating potential V.sub.SS (ground reference). 
Thus, the present invention utilizes CMOS technology to provide an output 
bandgap voltage that is substantially independent of temperature and power 
supply variations and is referenced to a power supply terminal. 
By now it should be apparent from the foregoing discussion that a novel 
CMOS circuit for providing an output bandgap voltage that is substantially 
independent of temperature and power supply variations has been provided. 
The CMOS circuit utilizes parasitic transistors to create a delta voltage 
that has a positive temperature coefficient across a differential pair of 
NMOS transistors. This delta voltage is then converted into differential 
currents which are amplified and mirrored and summed together to provide 
an output current that has a positive temperature coefficient. This output 
current is then passed through a series network including a resistor 
element and a parasitic PNP junction transistor to provide a bandgap 
voltage wherein the voltage across the resistor element has a positive 
temperature coefficient and the voltage across the parasitic PNP junction 
transistor has an inherent negative temperature coefficient. 
While the invention has been described in specific embodiments thereof it 
is evident that many alterations, modifications and variations will be 
apparent to those skilled in the art. Accordingly, it is intended to 
embrace such alterations, modifications and variations in the appended 
claims.