Duty cycle calibration circuit

A signal-generating circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first inverter, a second inverter, and a third inverter. The first P-type transistor supplies a supply voltage to a first node according to an input signal. Both of the second P-type transistor and the first N-type transistor couple the first node to a second node according to the input signal. The second N-type transistor couples the first node to a ground according to the input signal. The first inverter is coupled to the second node to generate a first signal. The second inverter is coupled between the first node and a third node. The third inverter is coupled to the third node to generate a second signal. The second signal and the first signal are the reverse of each other and synchronous.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of China Patent Application No. 201510885622.1, filed on Dec. 4, 2015, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The disclosure relates generally to duty cycle calibration circuits, and more particularly it relates to duty cycle calibration circuits utilizing a synchronous clock signal generated by a signal-generating circuit to calibrate the duty cycle.

Description of the Related Art

Integrated circuit (IC) devices include circuits or logic elements that may be used to perform any of a variety of functions. Oftentimes, these devices are used in a larger system to perform complex functions. As an example, in a relatively complex system (e.g., a computer system, a communication system, etc.), multiple IC devices may communicate with one another to perform system functions.

Generally, such devices require a clock signal to operate. The clock signal synchronizes communication between two different devices. Circuits that are designed to operate with a clock signal (commonly referred to as synchronous circuits) are generally activated at the rising or falling edge of the clock signal. Certain interfaces, however, allow data transfer on both the rising and falling edges of the clock signal to achieve higher data transfer rates.

Generally, a clock signal is presented as a square wave and the duty cycle may refer to the percentage of clock period that the clock signal remains at a logic high (logic 1) or a logic low level (logic 0). As such, a clock signal that spends half its clock period at logic 1 and the other half at logic 0 is said to have a balanced duty cycle or a 50% duty cycle. In high data rate applications, where both the rising and falling edges of the clock signal are used to sample data, it may be important for the clock signal to have a 50% duty cycle. Once the duty cycle is unbalanced or not 50%, it results in some unnecessary problems in the system. Therefore, devices and methods of generating a 50% duty cycle are urgently required to solve this problem.

BRIEF SUMMARY OF THE INVENTION

For solving the problems described above, the invention provides signal-generating circuits and duty cycle calibration circuits for generating 50% duty cycle clock signals.

In an embodiment, a signal-generating circuit comprises: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first inverter, a second inverter, and a third inverter. The first P-type transistor supplies a supply voltage to a first node according to an input signal. The second P-type transistor couples the first node to a second node according to the input signal. The first N-type transistor couples the second node to the first node according to the input signal. The second N-type transistor couples the first node to a ground according to the input signal. The first inverter generates a first signal according to a signal at the second node. The second inverter is coupled between the first node and a third node. The third inverter generates a second signal according to a signal at the third node. The second signal and the first signal are the inverse of each other and synchronous.

According to an embodiment of the invention, the third inverter has a rising delay time and a falling delay time. The rising delay time is substantially equal to a delay time of the second P-type transistor, and the falling delay time is substantially equal to a delay time of the first N-type transistor, such that the delay time from the input signal to the first signal is substantially equal to the delay time from the input signal to the second signal.

According to an embodiment of the invention, the first P-type transistor and the second P-type transistor have the same width-to-length ratio, and the first N-type transistor and the second N-type transistor have the same width-to-length ratio. The width-to-length ratios of the transistors in the third inverter are less than width-to-length ratios of the transistors in the first inverter and the second inverter. The width-to-length ratios of the transistors in the first inverter are equal to the width-to-length ratios of the transistors in the second inverter.

According to an embodiment of the invention, a width-to-length ratio of the P-type transistor in the third inverter is less than the width-to-length ratio of the second P-type transistor, and a width-to-length ratio of the N-type transistor in the third inverter is less than the width-to-length ratio of the first N-type transistor.

In an embodiment, a duty cycle calibration circuit comprises: a first signal-generating circuit, a second signal-generating circuit, a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate. The first signal-generating circuit receives a clock signal to generate a first signal and a second signal. The second signal and the first signal are the inverse of each other and synchronous. The second signal-generating circuit receives an inverse of the clock signal to generate a third signal and a fourth signal. The fourth signal and the third signal are the inverse of each other and synchronous. The first transmission gate supplies a supply voltage to an adjustment signal according to the first signal and the second signal. The second transmission gate couples the adjustment signal to a ground according to the third signal and the fourth signal. The third transmission gate supplies the supply voltage to an inverse of the adjustment signal according to the third signal and the fourth signal. The fourth transmission gate couples the inverse of the adjustment signal to the ground according to the first signal and the second signal.

According to an embodiment of the invention, each of the first signal-generating circuit and the second signal-generating circuit is a signal-generating circuit, the signal-generating circuit generates an output signal and an inverse of the output signal according to an input signal, and the output signal and the inverse of the output signal are the inverse of each other and synchronous. The signal-generating circuit comprises: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first inverter, a second inverter, and a third inverter. The first P-type transistor supplies the supply voltage to a first node. The second P-type transistor couples the first node to a second node according to the input signal. The first N-type transistor couples the second node to the first node according to the input signal. The second N-type transistor couples the first node to the ground according to the input signal. The first inverter is coupled to the second node to generate the output signal. The second inverter is coupled between the first node and a third node. The third inverter is coupled to the third node to generate the inverse of the output signal.

According to an embodiment of the invention, the third inverter has a rising delay time and a falling delay time. The rising delay time is substantially equal to the delay time of the second P-type transistor, and the falling delay time is substantially equal to the delay time of the first N-type transistor, such that the delay time from the input signal to the first signal is substantially equal to the delay time from the input signal to the second signal.

According to an embodiment of the invention, the first P-type transistor and the second P-type transistor have the same width-to-length ratio, and the first N-type transistor and the second N-type transistor have the same width-to-length ratio. The width-to-length ratios of the transistors in the third inverter are less than the width-to-length ratios of the transistors in the first inverter and the second inverter. The width-to-length ratios of the transistors in the first inverter are equal to the width-to-length ratios of the transistors in the second inverter.

According to an embodiment of the invention, a width-to-length ratio of the P-type transistor in the third inverter is less than the width-to-length ratio of the second P-type transistor, and a width-to-length ratio of the N-type transistor in the third inverter is less than the width-to-length ratio of the first N-type transistor.

According to an embodiment of the invention, the duty cycle calibration circuit further comprises: a first inverter chain and a second inverter chain. The first inverter chain comprises at least one inverter coupled in series and generates an output signal according to the adjustment signal for improving a driving capability of the output signal. The second inverter chain comprises at least one inverter coupled in series and generates an inverse of the output signal for improving a driving capability of the inverse of the output signal. The duty cycle of each of the output signal and the inverse of the output signal is substantially equal to 50%.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a schematic diagram of a duty cycle calibration circuit in accordance with an embodiment of the invention. As shown inFIG. 1, the duty cycle calibration circuit100includes the first signal-generating circuit110, the second signal-generating circuit120, the first signal output circuit130, and the second signal output circuit140.

The first signal-generating circuit110includes the first input inverter111, the first transmission gate112, the second input inverter113, the third input inverter114, and the fourth input inverter115, in which the first signal-generating circuit110is configured to receive the clock signal CLK to generate the first signal S1and the second signal S2. The second signal S2is the inverse of the first signal S1.

The second signal-generating circuit120includes the fifth input inverter121, the second transmission gate122, the sixth input inverter123, the seventh input inverter124, and the eighth input inverter125, in which the second signal-generating circuit120is configured to receive the inverse clock signal CLKB to generate the third signal S3and the fourth signal S4. The fourth signal S4is the inverse of the third signal S3. According to an embodiment of the invention, each of the inverters in the invention could be a complementary inverter which includes a P-type transistor and an N-type transistor.

According to an embodiment of the invention, the clock signal CLK and the inverse clock signal CLKB, which are provided by a phase-locked loop (PLL), are synchronous and the inverse of each other. According to an embodiment of the invention, the first transmission gate112is configured to balance the delay time produced by the third input inverter114, such that the first signal S1and the second signal S2are synchronous. Likewise, the second transmission gate122is configured to balance the delay time produced by the seventh input inverter124, such that the third signal S3and the fourth signal S4are synchronous. Therefore, the first transmission gate112and the second transmission gate122remain in the turned-on state. That is, the delay time from the clock signal CLK to the first signal S1and that from the clock signal CLK to the second signal S2are the same, and the delay time from the inverse clock signal CLKB to the third signal S3and that from the inverse clock signal CLKB to the fourth signal S4are the same.

The first signal output circuit130includes the first output N-type transistor131, the first output P-type transistor132, the second output N-type transistor133, the second output P-type transistor134, the first output inverter135, and the second output inverter136, in which the first output N-type transistor131and the first output P-type transistor132form a transmission gate, and the second output N-type transistor133and the second output P-type transistor134form another transmission gate.

The second signal output circuit140includes the third output N-type transistor141, the third output P-type transistor142, the fourth output N-type transistor143, the fourth P-type transistor144, the third output inverter145, and the fourth output inverter146, in which the third N-type transistor141and the third P-type transistor142form a transmission gate and the fourth output N-type transistor143and the fourth P-type transistor144form another transmission gate.

FIG. 2shows the waveform of the duty cycle calibration circuit in accordance with an embodiment of the invention. According to an embodiment of the invention, when the clock signal CLK and the inverse clock signal CLKB are over a half of the supply voltage VS, the clock signal CLK and the inverse clock signal CLKB are considered as the high logic level. Otherwise, the clock signal CLK and the inverse clock signal CLKB are considered as the low logic level. Therefore, in the time interval I shown inFIG. 2, the clock signal CLK and the inverse clock signal CLKB are both in the high logic level. That is, the clock signal CLK and the inverse clock signal CLKB are nonsynchronous.

The first signal-generating circuit110inFIG. 1generates the first signal S1and the second signal S2, which are the inverse of each other and synchronous, according to the clock signal CLK, and the second signal-generating circuit120generates the third signal S3and the fourth signal S4, which are the inverse of each other and synchronous, according to the inverse clock signal CLKB. In other words, the delay time from the clock signal CLK to the first signal S1, and the delay time from the clock signal CLK to the second signal S2are the same. In addition, the delay time from the inverse clock signal CLKB to the third signal S3and that from the inverse clock signal CLKB to the fourth signal S4are the same.

The first signal output circuit130and the second signal output circuit140respectively generate the adjustment signal SM and the inverse adjustment signal SMB by the first signal S1, the second signal S2, the third signal S3, and the fourth signal S4, in which the waveforms of the adjustment signal SM and the inverse adjustment signal SMB are shown inFIG. 2.

The first output inverter135and the second output inverter136of the first signal output circuit130generate the output signal OUT according to the adjustment signal SM. The third output inverter145and the fourth output inverter146of the second signal output circuit140generate the inverse output signal OUTB according to the inverse adjustment signal SMB. According to an embodiment of the invention, the first output inverter135, the second output inverter136, the third output inverter145, and the fourth output inverter146are configured to improve the driving capability of the output signal OUT and the inverse output signal OUTB. That is, the rise time and the fall time of the output signal OUT and the inverse output signal OUTB are shortened.

The first signal S1and the second signal S2, which are inverse to each other and synchronous, and the third signal S3and the fourth signal S4, which are inverse to each other and synchronous, are required for generating the output signal OUT and the inverse output signal OUTB with 50% duty cycle. However, the delay time of a transmission gate is different from that of an inverter, such that the delay time of the first transmission gate112is different from that of the third input inverter114, and the delay time of the second transmission gate122is different from that of the seventh input inverter124.

However, the inconsistency of the delay time generated by a transmission gate and that generated by an inverter results in the inconsistency of the delay time from the clock signal CLK to the first signal S1and that from the clock signal CLK to the second signal S2, and the inconsistency of the delay time from the inverse clock signal CLKB to the third signal S3and that from the inverse clock signal CLKB to the fourth signal S4. Especially at various levels of process variation, the variations of the delay time are more significant. Being unable to confirm that the first signal S1is synchronous to the second signal S2and the third signal S3is also synchronous to the fourth signal S4, it is impossible to make sure that the duty cycles of the output signal OUT and the inverse output signal OUTB are both 50%.

FIG. 3is a schematic diagram of a signal-generating circuit in accordance with another embodiment of the invention. As shown inFIG. 3, the signal-generating circuit300includes the first P-type transistor301, the second P-type transistor302, the first N-type transistor303, the second N-type transistor304, the first inverter305, the second inverter306, and the third inverter307. According to an embodiment of the invention, for the sake of improving the input driving capability of the clock signal CLK, one or more inverters may be inserted after the input signal CLK.

The first P-type transistor301supplies the supply voltage VS to the first node N1according to the control of the clock signal CLK. The second P-type transistor couples the first node N1to the second node N2according to the control of the clock signal CLK. The first N-type transistor303is coupled between the first node N1and the second node N2and controlled by the clock signal CLK. The second N-type transistor304couples the first node N1to the ground GND according to the clock signal CLK.

The first inverter305is configured to invert the signal at the second node N2and generate the first signal S1. The second inverter306is coupled between the first node N1and the third node N3. The third inverter307inverts the signal at the third node N3to be the second signal S2. According to an embodiment of the invention, in order to make the rise time of an inverter substantially equal to its fall time, the transition point of the inverter is set at a half of the supply voltage VS. That is, when the input signal of the inverter exceeds a half of the supply voltage VS, the inverter outputs the low logic level; when the input signal of the inverter is less than a half of the supply voltage VS, the inverter outputs the high logic level.

According to an embodiment of the invention, when the clock signal CLK converts from the high logic level to the low logic level, the rising delay time of the first P-type transistor301and that of the second P-type transistor302are experienced from the clock signal CLK to the first signal S1, and then the second node N2is charged to the high logic level. Subsequently, the falling delay time of the first inverter305is experienced to convert the first signal S1from the high logic level to the low logic level. That is, when the clock signal CLK is converted from the high logic level to the low logic level, two rising delay times and one falling delay time have been experienced from the clock signal CLK to the first signal S1.

Likewise, when the clock signal CLK is converted from the high logic level to the low logic level, the rising delay time of the first P-type transistor301, the falling delay time of the second inverter306, and the rising delay time of the third inverter307are experienced from the clock signal CLK to the second signal S2. That is, two rising delay times and one falling delay time have been experienced from the clock signal CLK to the second signal S2as well.

In summary, in order to make the path from the clock signal CLK to the first signal S1and that from the clock signal CLK to the second signal S2experience the same delay time, the rising delay time of the second P-type transistor302must be matched with the rising delay time of the third inverter307, and the rising delay time of the first inverter305must be matched with the rising delay time of the second inverter306. Likewise, the falling delay time of the first N-type transistor303must be matched with the third inverter307, and the falling delay time of the first inverter305must be matched with the falling delay time of the second inverter306.

According to an embodiment of the invention, when the width-to-length ratios (i.e., aspect ratios, W/L) of the transistors in the first inverter305are the same as those in the second inverter306, the rise times of the first inverter305and the second inverter306are matched and the fall times of the first inverter305and the second inverter306are matched as well. According to an embodiment of the invention, the width-to-length ratio of the second P-type transistor302and the width-to-length ratio of the P-type transistor in the third inverter307may be adjusted to obtain the same rising delay time. Likewise, the width-to-length ratio of the first N-type transistor303and the width-to-length ratio of the N-type transistor in the third inverter307may be adjusted to obtain the same falling delay time. According to an embodiment of the invention, the width-to-length ratios of the P-type transistor and the N-type transistor in each of the different inverters may be the same or different.

According to another embodiment of the invention, for the convenience of circuit layout, the width-to-length ratio of the first P-type transistor301and that of the second P-type transistor302are the same, and the width-to-length ratio of the first N-type transistor303and that of the second N-type transistor304are the same. However, the width-to-length ratio of the P-type transistor in the third inverter307is less than that of the second P-type transistor302for compensating the greater channel resistance produced by the second P-type transistor302due to the body effect. Likewise, the width-to-length ratio of the N-type transistor in the third inverter307is less than that of the first N-type transistor303for compensating the greater channel resistance produced by the first N-type transistor303due to the body effect.

FIG. 4is a schematic diagram of a duty cycle calibration circuit in accordance with another embodiment of the invention. The duty cycle calibration circuit400includes the first signal-generating circuit410, the second signal-generating circuit420, the first signal output circuit430, and the second signal output circuit440, in which each of the first signal-generating circuit410and the second signal-generating circuit420is the signal-generating circuit300inFIG. 3.

Compared to the signal-generating circuit300inFIG. 3, the first signal-generating circuit410and the second signal-generating circuit420further include the first input inverter411and the fifth input inverter421. According to an embodiment of the invention, the first input inverter411and the fifth input inverter421are respectively configured to improve the driving capability of the clock signal CLK and the inverse clock signal CLKB. The designer may determine whether the first input inverter411and the fifth input inverter421are to be employed.

As shown inFIG. 4, the clock signal CLK drives the first input P-type transistor412, the second input P-type transistor413, the first input N-type transistor414, and the second input N-type transistor415through the first input inverter411, and generates the first signal S1through the second input inverter416and the third input inverter417, and generates the second signal S2through the fourth input inverter418.

According to an embodiment of the invention, the first signal S1and the second signal S2, which are the inverse of each other and synchronous, may be generated by adjusting the relationship between the width-to-length ratios of the transistors in the third input inverter417and the width-to-length ratios of the second input P-type transistor413and the first input N-type transistor414, and keeping the width-to-length ratios of the transistors in the second input inverter416the same as those of the fourth input inverter418.

As shown inFIG. 4, the inverse clock signal CLKB drives the third input P-type transistor422, the fourth input P-type transistor423, the third input N-type transistor424, and the fourth input N-type transistor425through the fifth input inverter421. The third signal S3is generated by the sixth input inverter426and the seventh input inverter427, and the fourth signal S4is generated by the eighth input inverter428.

According to an embodiment of the invention, the third signal S3and the fourth signal S4, which are inverse to each other and synchronous, may be generated by adjusting the relationship between the width-to-length ratios of the transistors in the seventh input inverter427and the width-to-length ratios of the fourth input P-type transistor423and the third input N-type transistor424, and keeping the width-to-length ratios of the transistors in the sixth input inverter426the same as those of the eighth input inverter428.

The first signal output circuit430and the second signal output circuit440shown inFIG. 4are identical to the first signal output circuit130and the second signal output circuit140shown inFIG. 1. The first output N-type transistor431and the first output P-type transistor432form a transmission gate, the second output N-type transistor433and the second output P-type transistor434form another transmission gate, the third output N-type transistor441and the third output P-type transistor442form yet another transmission gate, and the fourth output N-type transistor443and the fourth output P-type transistor444form yet another transmission gate.

According to an embodiment of the invention, the first output inverter435and the second output inverter436form an inverter chain to generate the output signal OUT according to the adjustment signal SM, in which the inverter chain is configured to improve the driving capability of the output signal OUT, and the designer could determine the number of inverters in the inverter chain. Likewise, the third output inverter445and the fourth output inverter446form an inverter chain to generate the inverse output signal OUTB according to the inverse adjustment signal SMB, in which the inverter chain is configured to improve the driving capability of the inverse output signal OUTB, and the designer could determine the number of inverters in the inverter chain.

Since the synchronization of the first signal S1and the second signal S2can be ensured by adjusting the relationship between the width-to-length ratios of the transistors of the third input inverter417and the width-to-length ratios of the second P-type transistor413and the first input N-type transistor414, and the synchronization of the third signal S3and the fourth signal S4can be ensured by adjusting the relationship between the width-to-length ratios of the transistors of the seventh input inverter427and the width-to-length ratios of the fourth input P-type transistor423and the third input N-type transistor424, the first signal output circuit430and the second signal output circuit440are able to generate the output signal OUT and the inverse output signal OUTB with 50% duty cycle by the first signal S1and the second signal S2, which are synchronous, and the third signal S3and the fourth signal S4, which are synchronous. The output signal OUT and the inverse output signal OUTB are the inverse of each other and synchronous.