Receiving apparatus and data transmission apparatus

According to an aspect of the invention, a receiving apparatus includes a receiving unit, a reverse conversion unit, and an extracting unit. The receiving unit receives conversion data which is generated, based on a predetermined first rule, by converting transmission data including a plurality of bits and data including an error detection code for detecting an error of the transmission data. The reverse conversion unit reverse-converts, based on a predetermined second rule, the conversion data received by the receiving unit and reverse data generated by reversing a part of bits of the received conversion data to generate a plurality of reverse conversion data. The extracting unit extracts, from the plurality of the reverse conversion data, the reverse conversion data for which an error is not detected in an error detection based on the error detection code.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims priority under 35 USC 119 from Japanese Patent Application No. 2010-272421, filed Dec. 7, 2010.

BACKGROUND

1. Technical Field

The present invention relates to a receiving apparatus and a data transmission apparatus.

2. Related Art

With respect to transmission data transmitted through a communication line, a data transmission apparatus for performing 8B/10B conversion that improves DC balance by equalizing the number of bit signals ‘0’ and ‘1’ has been known in the related art.

SUMMARY OF THE INVENTION

According to an aspect of the invention, a receiving apparatus includes a receiving unit, a reverse conversion unit, and an extracting unit. The receiving unit receives conversion data which is generated, based on a predetermined first rule, by converting transmission data including a plurality of bits and data including an error detection code for detecting an error of the transmission data. The reverse conversion unit reverse-converts, based on a predetermined second rule, the conversion data received by the receiving unit and reverse data generated by reversing a part of bits of the received conversion data to generate a plurality of reverse conversion data. The extracting unit extracts, from the plurality of the reverse conversion data, the reverse conversion data for which an error is not detected in an error detection based on the error detection code.

DETAILED DESCRIPTION

First Exemplary Embodiment

The first exemplary embodiment is described with reference toFIGS. 1 to 5B.

(Constitution of Data Transmission Apparatus)

FIG. 1is a block diagram showing the constitution of the data transmission apparatus according to the first exemplary embodiment of the present invention. The data transmission apparatus1includes a transmission apparatus2, a communication line3connected to the transmission apparatus2, and a receiving apparatus4capable of communicating with the transmission apparatus2through the communication line3. For example, a differential signal line including a pair of signal lines transmitting differential signals whose polarities are reversed to each other may be used as the communication line3.

(Constitution of Transmission Apparatus)

The transmission apparatus2includes a memory interface21, a memory22connected to the memory interface21, an error detection code addition unit23, a DC balance conversion unit24, and a receiving unit25.

The memory interface21receives transmission data from an external device and first stores the transmission data in a memory22including a storage device such as RAM (Random Access Memory), etc. The memory interface21reads the transmission data stored in the memory22and outputs the read transmission data to the following error detection code addition unit23.

The error detection code addition unit23generates an error detection code for detecting an error of the transmission data based on the transmission data outputted from the memory interface21. The error detection code addition unit23adds the generated error detection code, a header, and a footer to the transmission data and outputs the transmission data to the following DC balance conversion unit24.

The error detection code generated and added by the error detection code addition unit23may detect an error occurred during data transmission by, for example, noise, but may not correct the error. For example, a CRC (Cyclic Redundancy Check) code may be used as the error detection code.

The transmission data and error detection code outputted from the error detection code addition unit23are the subject data of the DC balance conversion unit24. The DC balance conversion unit24performs DC balance conversion to improve DC balance so that signal ‘0’ or ‘1’ does not continue during the transmission through the communication line3.

This exemplary embodiment describes the case where 8B/10B conversion is applied as the DC balance conversion. 8B/10B conversion converts 8-bit byte data into 10-bit data in data unit with reference to a pre-registered conversion table. By 8B/10B conversion, for example, 8-bit data of ‘00000000’ is converted into 10-bit data of ‘1001110100,’ and an 8-bit data of ‘11111111’ is converted into 10-bit data of ‘1010110001.’ 8B/10B conversion causes a 20% of overhead, but may embed a clock signal for the synchronization of a receiving side of a bit stream transmitted in serial so that the 8B/10B conversion may simultaneously transmit data and clock through the same signal line.

The DC balance conversion unit24generates conversion data, in which the subject data converts each 8-bit into 10-bit data with reference to the conversion table, and outputs the conversion data to the following transmission unit25.

The transmission unit25converts the conversion data outputted from the DC balance conversion unit24in parallel/serial and transmits the conversion data by a transmission circuit such as a differential transceiver, etc. to the receiving apparatus4through the communication line3.

FIG. 2Ashows one example of data before DC balance conversion by the DC balance conversion unit24.FIG. 2Bshows one example of data after DC balance conversion by the DC balance conversion unit24.

As shown2A, in a packet10before DC balance conversion, a CRC code13is added to transmission data12as an error detection code. A header is added to the front of the transmission data12and a footer14is added to the back of the CRC code13. In the example shown in this drawing, the transmission data12is 256 bytes (2048 bits), the CRC code13is 2 bytes (16 bits), and the header11and footer14each is 2 bytes (16 bits).

In a packet10A after DC balance conversion, the transmission data12A is 2560 bits, the CRC code13A is 20 bits, and the header11A and footer14A each is 20 bits. Such packet10A is one example of DC balance converted conversion data.

(Constitution of Receiving Apparatus)

The receiving apparatus4includes a receiving unit41connected to the communication line3, a decoding unit50for decoding data received by the receiving unit41, a memory interface42, and a buffer memory43connected to the memory interface42.

The receiving unit41receives serial data transmitted from the transmission apparatus2through the communication line3, converts the serial data into 10-bit parallel data, and outputs the 10-bit parallel data to the decoding unit50. In the decoding unit50following the receiving unit41, 1 set of the 10-bit parallel data is regarded as one unit.

The decoding unit50decodes the parallel data outputted from the receiving unit41, extracts transmission data from the decoded parallel data, and outputs the transmission data to the memory interface42. Detailed explanation of the decoding unit follows.

The memory interface42stores the transmission data outputted from the decoding unit50in a memory43including a storage unit such as RAM, etc. The memory interface42outputs the transmission data stored in the memory43in accordance with a read signal from external.

FIG. 3is a block diagram showing the constitution of the decoding unit50. The decoding unit50includes hardware such as ASIC (Application Specific Integrated Circuit), etc.

The decoding unit50includes a first reverse conversion unit51, a reverse data generation unit52, a second reverse conversion unit53, first to tenth data selection units540-549, first to tenth CRC computing units550-559, a non-reverse data CRC computing unit55, a memory control unit56, and a memory57as a storage unit. The first reverse conversion unit51, the reverse data generation unit52, and the second reverse conversion unit53are examples of the reverse conversion unit of the present invention. The first to tenth CRC computing units550-559, the non-reverse data CRC computing unit55, and the memory control unit56are examples of the extraction unit of the present invention.

The first reverse conversion unit51sequentially performs DC balance reverse conversion of the 10-bit parallel data obtained from the receiving unit41by the one unit with reference to a DC balance conversion table500. The DC balance conversion table500is set to correspond to the conversion table referred to by the DC balance conversion unit24of the transmission apparatus2.

The first reverse conversion unit51outputs DC balance reverse-converted 8-bit data as output data D0to a data bus511. If the 8-bit data, which corresponds to the 10-bit data obtained from the receiving unit41, is not registered in the DC balance conversion table500(if reverse conversion is unavailable), the first reverse conversion unit51outputs an error signal Err indicating there was a reverse conversion error to a signal line512, while outputting 8-bit data with a predetermined value (for example, ‘00000000’) as the output data D0to the data bus511. The error signal Err is maintained ON only when the first reverse conversion unit51outputs the predetermined value.

Additionally, the first reverse conversion unit51outputs the 10-bit data before DC balance conversion is applied (data obtained from the receiving unit41) to the 10-bit data bus513.

The reverse data generation unit52obtains the parallel 10-bit data converted by the receiving unit41through the data bus513and generates reverse data including ten 10-bit, in which each bit from the first bit (least significant bit) to the tenth bit (most significant bit) of the 10-bit data is reversed. That is, one bit of 10-bit is reversed in each of the ten 10-bit.

The second reverse conversion unit53performs DC balance reverse conversion to each of the ten reverse data generated by the reverse data generation unit52with reference to the DC balance conversion table500, and generates ten 8-bit data corresponding to each reverse data.

The first reverse conversion data that is outputted from the first reverse conversion unit51to the data bus511; the second reverse conversion data which is outputted from the second reverse conversion unit53and which is generated by the reverse-conversion of the reverse data (any one of the first to tenth bits is reversed); and an error signal Err outputted from the first reverse conversion unit51to the signal line512are inputted in the first to tenth data selection units540-549. The second reverse conversion data, in which the reverse data (the first bit is reversed) is reverse-converted, is inputted to the first data selection unit540. The second reverse conversion data, in which the reverse data (the second bit is reversed) is reverse-converted, is inputted to the second data selection unit541. The second reverse conversion data, in which the reverse data (the third bit is reversed) is reverse-converted, is inputted to the third data selection unit542. Input data in following data selection units are omitted here.

If the error signal Err is OFF, the first to tenth data selection units540-549output the first reverse conversion data as reverse data D1-D10. If the error signal Err is ON, the first to tenth data selection units540-549output the second reverse conversion data as reverse data D1-D10.

In other words, the first to tenth data selection units540-549output the second reverse conversion data when reverse conversion is unavailable in the first reverse conversion unit51and the predetermined value is outputted as the first reverse conversion data. The first to tenth data selection units540-549output the first reverse conversion data when the reverse conversion is available in the first reverse conversion unit51.

Such output data D1-D10is inputted in the first to tenth CRC computing units550-559and the memory control unit56.

The first to tenth CRC computing units550-559sequentially compute a CRC code as an error detection code based on the first or second reverse conversion data outputted from the first to tenth data selection units540-549, and output the CRC code to the memory control unit56.

The non-reverse data CRC computing unit55connects to the data bus511, sequentially computes the CRC code of the first reverse conversion data outputted from of the first reverse conversion unit51, and outputs the CRC code to the memory control unit56.

The non-reverse data CRC computing unit55and the first to tenth CRC computing units550-559are configured to output the CRC code to the memory control unit56later than the change period of the output data D0-D10by one period.

The memory control unit56sequentially stores the output data D0from the first reverse conversion unit51and the output data D1-D10outputted from the first to tenth data selection units540-549in each different area of the memory57.

When the first reverse conversion unit51obtains a CRC code as a reverse-converted error detection code (CRC code included in the packet received by the receiving unit31), the memory control unit56determines whether the obtained CRC code (hereinafter, this CRC code is referred to as “receiving CRC code”) matches the CRC code inputted from the non-reverse data CRC computing unit55. As a result of such determination, if the two CRC codes match, the memory control unit56reads a series of data sequentially storing the output data D0from the memory57and outputs the data to the following memory interface42.

If the receiving CRC code and the CRC code inputted from the non-reverse data CRC computing unit55do not match, the memory control unit56determines whether there is any matching between the CRC codes inputted from the first to tenth CRC computing units550-559and the receiving CRC. As a result of such determination, if there is matching, the memory control unit56reads a series of data sequentially storing the output data corresponding to the CRC code that matches the receiving code among the output data D1-D10of the first to tenth data selection units540-549, and outputs the data as error-corrected transmission data to the following memory interface42.

For example, if the CRC code inputted from the fourth CRC computing unit553matches the receiving CRC code, the memory control unit56reads a series of data sequentially storing the output data D4of the fourth selection unit543and outputs the data to the following memory interface42.

If there is no matching between the CRC codes inputted from the first to tenth CRC computing units550-559and the receiving CRC, the memory control unit56does not output the data to the memory interface42and outputs a retransmission request signal of a packet to the transmission apparatus2.

The memory control unit56may be configured to output to the memory interface42data sequentially storing any one of the output data D1-D10of the first to tenth data selection units540-549, which corresponds to the CRC code among the CRC codes inputted from the first to tenth CRC computing units550-559that matches the receiving CRC, without determining whether the receiving CRC code matches the CRC code inputted from the non-reverse data CRC computing unit55. Under such constitution, if there is no error in the data received by the receiving unit41, correct data may be outputted because all the CRC codes inputted from the first to tenth CRC computing units550-559match the receiving CRC code. Such constitution may omit the non-reverse data computing unit55.

FIG. 4is a timing chart showing one example of the change in the error signal Err, the output data D0of the first reverse conversion unit51, and the output data D1-D10of the first to tenth data selection units540-549when the reverse conversion of the second byte data d2is unavailable among the transmission data received from the transmission apparatus2.

When the error signal Err is ON, the first to tenth data selection units540-549output the first bit reverse and the reverse-converted second reverse conversion data. Thus, when d2is indicated in the output data D0, the first to tenth bits are indicated as d21-d210, respectively, in the output data D1-D10. When the error signal Err is OFF, data that is the same as the output data D0is indicated in the output data D1-D10of the first to tenth data selection units540-549.

FIGS. 5A and 5Bshow specific examples of error correction by an error correction unit321c.FIG. 5Ashows 10 bits of each of the transmission data transmitted from the transmission apparatus2and the receiving data received by the receiving apparatus.FIG. 5Bshows data, in which each 1 bit of the 10 bits for which an error occurs in DC balance reverse conversion is reversed, and the corresponding 8-bit data.

As shown inFIG. 5A, the transmission is ‘0010111011,’ whereas the receiving data is ‘0010110011,’ in which an error occurs in the fourth bit. In this case, reverse conversion by the first reverse conversion unit51is unavailable and an error signal Err is ON by one period.

As shown inFIG. 5B, the reverse data generation unit52generates ten reverse data, in which each of the first bit to tenth bit of the 10-bit data is reversed. The second reverse conversion unit53reversely converts such reverse data with reference to the DC balance conversion table500and outputs the data to the first to tenth data selection units540-549. If it is not possible to obtain the corresponding 8-bit data in the DC balance conversion table500, the second reverse conversion unit53outputs a predetermined value (for example, ‘0’ inFIG. 5B) to the first to tenth data selection units540-549.

As a result, in a timing when an error signal Err is ON, each data in the right side ofFIG. 5B(decimal notation) is indicated as the output data D1-D10. Among the output data D1-D10, since D4, i.e., output data in which the fourth bit is converted and is reverse-converted, corresponds to the receiving data, the CRC data outputted from the fourth CRC computing unit553matches the receiving CRC data and a series of data sequentially outputted from the fourth data selection unit543and stored in the memory57is outputted to the memory interface as error-corrected transmission data.

Other Exemplary Embodiment

The present invention is not limited to the first exemplary embodiment and various modification of the present invention may be made without changing the summary of the present invention.

For example, in the first exemplary embodiment, the reverse data generation unit52generates a plurality of reverse data, in which 1 bit is reversed among 10 bits. However, the reverse data generation unit52may generate a plurality of reverse data (55reverse data), in which 1 bit and 2 bits are reversed among 10 bits and may provide a second reverse conversion unit, a data selection unit, and a CRC computing unit that correspond to the reverse data. Also, the decoding unit may be configured to reverse at least 3 bits.

In the first exemplary embodiment, the transmission apparatus2performs 8B/10B conversion and the receiving apparatus4performs 8B/10B reverse conversion. However, the present invention is not limited to such embodiment. For example, the transmission apparatus2may perform encoding based on a predetermined rule and the receiving apparatus4may perform decoding based on a predetermined decoding order corresponding to the encoding order in the transmission apparatus2.

In the first exemplary embodiment, the decoding unit50includes hardware such as ASIC (Application Specific Integrated Circuit), etc. However, the present invention is not limited to such embodiment. The function of each unit of the decoding unit50may be implemented by a CPU (Central Processing Unit) that is operated based on a pre-stored program.

DESCRIPTION OF REFERENCE NUMERALS