Thin film transistor array panel and method for manufacturing the same

One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2015-0144680, filed on Oct. 16, 2015, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

Field

The present invention relates to a thin film transistor array panel and a manufacturing method thereof.

Discussion of the Background

Generally, a display device, such as a liquid crystal display, an organic light emitting diode display, or the like includes a plurality of pairs of electric field generating electrodes and electro-optical active layers interposed therebetween. The liquid crystal display may include a liquid crystal layer as the electro-optical active layer, and the organic light emitting diode display may include an organic emission layer as the electro-optical active layer.

One of the pair of electric field generating electrodes is connected to a switching element and receives an electrical signal, and the electro-optical active layer serves to convert the electrical signal to an optical signal, thereby displaying an image.

A thin film transistor (TFT), which is a three-terminal device, is adopted as the switching element in the display device, and a signal line including a gate line for transferring a scanning signal for controlling the thin film transistor, a data line for transferring a signal applied to a pixel electrode, and the like is included in the display device.

Meanwhile, as the display area becoming larger, an oxide semiconductor technique for faster operating speed and reduction of the signal line resistance have been researched. For example, a main wiring layer may be formed of a material such as copper, its alloy, or the like for reducing the signal line resistance. Copper, however, may form a porous metal oxide between the main wiring layer and a passivation layer covering thereon, thereby deteriorating reliability of the device.

SUMMARY

The present invention has been made in an effort to provide a thin film transistor array panel and a manufacturing method thereof, having advantages of preventing a porous metal oxide from being formed between a main wiring layer and a passivation layer.

According to one or more exemplary embodiments, a thin film transistor array panel includes a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.

A channel region of the semiconductor layer may include phosphorus (P).

The metal phosphorus oxide layer may include phosphorus, oxygen, and at least one selected from a group consisting of a copper-based metal, an aluminum-based metal, a silver-based metal, a molybdenum-based metal, and a titanium-based metal.

The metal phosphorus oxide layer may cover an upper surface and a lateral surface of each of the source electrode and the drain electrode.

The thin film transistor array panel may further include a barrier layer interposed between the data wire layer and the semiconductor layer.

Each of the data wire layer and the barrier layer may be configured to expose a channel region of the semiconductor layer to upper layer.

A region of the barrier layer exposing the channel region of the semiconductor layer may be narrower than a region of the data wire layer exposing the channel region of the semiconductor layer.

The thin film transistor array panel may further include a passivation layer configured to cover the metal phosphorus oxide layer, the source electrode, the drain electrode.

The passivation layer may include a silicon oxide.

The semiconductor layer may accord with an edge lateral surface of the source electrode, the drain electrode, and the data line except for the channel region.

Lateral edge portions of the semiconductor layer, the data line, and the drain electrode and lateral portions of the source electrode and the drain electrode exposing a channel region of the semiconductor layer may include lateral surfaces that are inclined at an angle of from about 10° to about 80° with respect to the substrate.

According to one or more exemplary embodiments, a manufacturing method of a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a semiconductor layer on the substrate, forming a data wire layer including a data line intersecting the gate line, a source electrode connected to the data line and placed above the semiconductor layer, and a drain electrode placed above the semiconductor layer and facing the source electrode, performing a phosphine treatment on the data wire layer, and forming a passivation layer on the data wire layer, wherein the forming of the passivation layer includes forming a metal phosphorus oxide layer covering the source electrode and the drain.

The phosphine treatment on the data wire layer may be performed as a heat treatment or a plasma treatment.

The metal phosphorus oxide layer may be formed to cover an upper surface and a lateral surface of each of the source electrode and the drain electrode.

The passivation layer may include a silicon oxide.

The manufacturing method may further include forming a barrier layer configured to expose a channel region of the semiconductor layer after forming of the semiconductor layer.

A region of the barrier layer exposing the channel region of the semiconductor layer may be formed narrower than the data wire layer, exposing the channel region of the semiconductor layer.

Lateral edge portions of the semiconductor layer, the data line, and the drain electrode and lateral portions of the source electrode and the drain electrode exposing a channel region of the semiconductor layer may include lateral surfaces that are inclined at an angle of from about 10° to about 80° with respect to the substrate.

According to one or more exemplary embodiments, a thin film transistor array panel includes a substrate, a semiconductor layer above the substrate, and the semiconductor layer including an oxide semiconductor, first and second data wire layers above the semiconductor layer, the first and second data wire layers facing each other, and a metal phosphorus oxide layer covering the first and second data wire layer from an upper layer.

The upper layer may be on both of the metal phosphorus oxide layer and the semiconductor layer.

The thin film transistor array panel may further include a first barrier layer between the semiconductor layer and the first wire layer, and a second barrier layer between the semiconductor layer and the second wire layer. A distance between the first and second barrier layers on a channel region of the semiconductor layer is narrower than a distance between the first and second data wire layers on the channel region of the semiconductor layer.

According to the exemplary embodiment of the present invention, it is possible to improve reliability of the thin film transistor array panel.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

FIG. 1is a top plan view illustrating a thin film transistor array panel according to one or more exemplary embodiments.FIG. 2is a cross-sectional view taken along line II-II ofFIG. 1.

Referring toFIG. 1andFIG. 2, the thin film transistor array panel100may include a gate line121disposed on an insulation substrate110made of a material such as transparent glass, plastic, or the like.

Each gate line121may be substantially extended in a horizontal direction. The gate line121may serve to transmit a gate signal and substantially. The gate line121includes a plurality of gate electrodes protruded therefrom.

Each gate electrode124may be configured to have a dual-layer structure including a first layer124pand a second layer124q. The first layer124pand the second layer124qmay be formed of an aluminum-based metal such as aluminum (Al), an aluminum alloy, or the like, a silver-based metal such as silver (Ag), a silver alloy, or the like, a copper-based metal such as copper (Cu), a copper alloy, or the like, a molybdenum-based metal such as molybdenum (Mo), a molybdenum alloy, or the like, chromium (Cr), titanium (Ti), tantalum (Ta), manganese (Mn), or the like. For example, the first layer124pmay include titanium, and the second layer124qmay include copper or a copper alloy. In one or more exemplary embodiments, the first layer124pand the second layer124qmay be formed by combining layers having different physical properties. It is contemplated that the gate electrode124may include dual-layers as described with reference toFIG. 1, but embodiments are not limited thereto. The gate electrode124may include a single-layers or triple-layers.

In one or more exemplary embodiments, the gate line121may include multi-layers similar to the gate electrode124, because both of them are formed in the same process. For instance, the gate line121may include third and fourth layers corresponding to, and maybe the same as, the first and second layers124pand124q, respectively.

A gate insulating layer140made of an insulating material such as a silicon oxide or a silicon nitride is disposed on the gate line121. The gate insulating layer140may include a first insulating layer140aand a second insulating layer140b. In one exemplary embodiment, the first insulating layer140amay be formed of a silicon nitride (SiNx) up to about 4000 Å thick, and the second insulating layer140bmay be made of a silicon oxide (SiOx) up to about 500 Å thick. In another exemplary embodiment, the first insulating layer140amay be made of a silicon oxynitride (SiON), and the second insulating layer140bmay be made of a silicon oxide (SiOx). In one or more exemplary embodiments, the gate insulating layer140may be configured to be the single layer or the like.

A semiconductor layer151is disposed on the gate insulating layer140. The semiconductor layers151may be formed of amorphous silicon, crystalline silicon, or an oxide semiconductor. The semiconductor layer151includes a projection154over the gate electrodes124.

In one or more embodiments, the semiconductor layer151may be made of the oxide semiconductor. In this manner, the semiconductor layer151may include at least one of zinc (Zn), indium (In), tin (Sn), gallium (Ga), and hafnium (Hf). For example, the semiconductor layer151may be formed of indium-gallium-zinc oxide.

Data wire layers171,173, and175including a data line171, a source electrode173connected to the data line171, and a drain electrode175are disposed on at least one of the semiconductor layer151and the gate insulating layer140.

Each data line171may substantially extends in the vertical direction and intersects with the gate line121. Each source electrode173extends from the data line171and overlaps the gate electrodes124. In one or more exemplary embodiments, the source electrode173may have a substantially U-shape.

The drain electrode175may be separated from the data line171. In one or more exemplary embodiments, the drain electrode175may extend toward the center of the U-shape of the source electrode173.

The data wire layers171,173, and175may have a region exposing a channel region of the semiconductor layer151. The data wire layers171,173, and175may be formed of at least one metal selected from a copper-based metal, an aluminum-based metal, a silver-based metal, a molybdenum-based metal, and a titanium-based metal.

Barrier layers171p,173p, and175pmay be interposed between the data wire layers171,173, and175, and the semiconductor layer151. The barrier layers171p,173p, and175pmay be formed of a metal oxide such as an indium-zinc oxide, a gallium-zinc oxide, an aluminum-zinc oxide, a titanium oxide, an aluminum oxide, a molybdenum oxide, or the like. The barrier layers171p,173p, and175pserve as diffusion preventing layers preventing a material such as copper or the like from being diffused into the semiconductor layer151.

A metal phosphorus oxide layer177is disposed on the data wire layers171,173, and175. The metal phosphorus oxide layer177may include phosphorus, oxygen, and at least one selected from a copper-based metal, an aluminum-based metal, a silver-based metal, a molybdenum-based metal, and a titanium-based metal. For example, the metal phosphorus oxide layer177may include a compound indicated by CuxPyOz. In one or more exemplary embodiments, the metal phosphorus oxide layer177is configured to cover the source electrode173and the drain electrode175. In one or more exemplary embodiments, the metal phosphorus oxide layer177may cover lateral surfaces A and B of the source electrode173and the drain electrode175, and upper surfaces of the source electrode173and the drain electrode175. The metal phosphorus oxide layer177may directly contact the surfaces of the source electrode173and the drain electrode175. The metal phosphorus oxide layer177may not be formed on a part of the gate insulating layer140and the channel region of the semiconductor layer151, which do not overlap the source electrode173and the drain electrode175.

Hereinafter, the lateral portions A of the source electrode173and the drain electrode175adjacent to the channel region of the semiconductor layer151will be described in detail.

The projection154of the semiconductor layer151includes an exposed part between the source electrode173and the drain electrode175. The semiconductor layer151may be configured to have a substantially identical planar pattern to those of the data line171and the drain electrode175except for the exposed part of the projection154. In other words, lateral edges of the semiconductor layer151may substantially coincide with the lateral edges of the data line171and the drain electrode175except for the exposed part of the projection154.

In this manner, lateral edges of the semiconductor layer151, the data line171, and the drain electrode175and the lateral portions A of the source electrode173and the drain electrode175may include an inclined lateral surface having a predetermined angle with respect to the insulation substrate110. For instance, the lateral edges of the semiconductor layer151, the data line171, and the drain electrode175and the lateral portions A of the source electrode173and the drain electrode175, which are configured to expose the channel region of the semiconductor layer151, may include lateral surfaces that are inclined at an angle of from about 10° to about 80° with respect to the insulation substrate110.

The gate electrode124, the source electrode173, and the drain electrode175constitute one thin film transistor (TFT) together with the projection154of one semiconductor layer151, and a channel region of the thin film transistor is formed in the projection154between the source electrode173and the drain electrode175.

In one or more exemplary embodiments, the source electrode173and the drain electrode175are covered with the metal phosphorus oxide layer177made of the material such as copper and the like.

It is assumed that the lateral portions A of the source electrode173and the drain electrode175are exposed without being covered with the metal phosphorus oxide layer177. In a following process for forming a passivation layer180including a silicon oxide, the material such as copper and the like included in the data wire layers171,173, and175may form a porous oxide, thereby deteriorating a thin film transistor characteristic. When heat-treating the projection154of the semiconductor layer151for suitable channel characteristics, the data wire layers171,173, and175may form a porous oxide.

In one or more embodiments, the metal phosphorus oxide layer177may be provided to cover the lateral portions A of the source electrode173and the drain electrode175. This may prevent the data wire layers171,173, and175from oxidation.

In the present exemplary embodiment, the metal phosphorus oxide layer177may be formed by heat or by plasma.

A passivation layer180is disposed on the metal phosphorus oxide layer177and the projection154. The passivation layer180may further cover the gate insulating layer140. In one or more exemplary embodiments, the passivation layer180is made of an inorganic insulator such as a silicon nitride, a silicon oxide, or the like, or an organic insulator, a low dielectric constant insulator, or the like.

In one or more exemplary embodiments, the passivation layer180may include a lower passivation layer180aand an upper passivation layer180b. For example, the lower passivation layer180amay be formed of a silicon oxide, and the upper passivation layer180bmay be formed of a silicon nitride when the semiconductor layer151includes the oxide semiconductor.

The passivation layer180may contact an exposed part of the semiconductor layer between the source electrode173and the drain electrode175.

A contact hole185may be formed in the passivation layer180to expose one end of the drain electrode175. A pixel electrode191formed on the passivation layer180may be electrically coupled to the drain electrode175through the contact hole185and serve to receive data voltages from the drain electrode175. In one or more exemplary embodiments, the pixel electrode191may be formed of a transparent conductor such as ITO, IZO, or the like.

FIG. 3throughFIG. 10are the cross-sectional views illustrating a manufacturing method of a thin film transistor array panel according to one or more exemplary embodiments. Each ofFIG. 3throughFIG. 10is a cross-sectional views taken along line II-II ofFIG. 1.

Referring toFIG. 3, a double layer is formed by stacking at least one of a molybdenum-based metal such as molybdenum (Mo), a molybdenum alloy, or the like, chromium (Cr), a chromium alloy, titanium (Ti), a titanium alloy, tantalum (Ta), a tantalum alloy, manganese (Mn), and a manganese alloy on the substrate110made of, for example, transparent glass, plastic, or the like, and then stacking thereon one selected from an aluminum-based metal such as aluminum (Al), an aluminum alloy, and the like, a silver-based metal such as silver (Ag), a silver alloy, and the like, and a copper-based metal such as copper (Cu), a copper alloy, and the like. Then, the double layer is patterned, to form the gate line121including the gate electrode124shown inFIG. 1. For example, the lower layer124pmay include titanium and the upper layer124qmay include copper or a copper alloy.

In one or more exemplary embodiments, after the double layer is formed, a photosensitive film (not illustrated) is stacked and patterned, and then the lower layer124pand the upper layer124qare etched together by using a photosensitive film pattern (not illustrated) as a mask. Herein, the etchant used may etch the lower layer124pand the upper layer124qall together.

Referring toFIG. 4, the gate insulating layer140, an oxide semiconductor layer150, a metal oxide layer170p, and a metal layer170are stacked on the gate electrode124. The gate insulating layer140may be formed by depositing the first insulating layer140aincluding a silicon nitride and then depositing the second insulating layer140bincluding a silicon oxide.

In one or more exemplary embodiments, the oxide semiconductor layer150may include at least one of zinc (Zn), indium (In), tin (Sn), gallium (Ga), and hafnium (Hf). In one or more exemplary embodiments, the oxide semiconductor layer150may be substituted by one of amorphous silicon, crystalline silicon, and the like. The metal oxide layer170pmay include any one of indium-zinc oxide, gallium-zinc oxide, and aluminum-zinc oxide, and the metal layer170may include copper or a copper alloy.

Then, after forming a photoresist layer, a first photosensitive film pattern50is patterned. The first photosensitive film pattern50includes a first region50aformed to be relatively thick and a second region50bformed to be relatively thin. A thickness difference of the first photosensitive film pattern50may be formed by a reflow method or by adjusting light radiation amount using a mask. In order to adjust the light radiation amount, a mask having a slit pattern, a lattice pattern, or a translucent layer thereon may be used. The second region50bhaving a thin thickness is configured to correspond to a position where a channel region of the thin film transistor is to be formed.

Referring toFIG. 5, the metal oxide layer170pand the metal layer170are etched by using an etchant for etching the metal oxide layer170pand the metal layer170together with the first photosensitive film pattern50as a mask. Herein, the etchant may be identical to the etchant employed in etching the lower layer124pand the upper layer124qof the gate electrodes124.

Lateral surfaces of the metal oxide layer170pand the metal layer170covered with the first photosensitive film pattern50may be etched by the etchant. As a result, as shown inFIG. 5, an edge (corresponding to a lateral portion C) of a data conductor layer, which is the metal layer170, is disposed at inner sides of regions C, D, and E in which the first photosensitive film pattern50is formed. In this manner, the etchant etching the metal oxide layer170pand the metal layer170does not etch the gate insulating layer140or the oxide semiconductor layer150.

Further, the oxide semiconductor layer150is etched by using the first photosensitive film pattern50as a mask. In this manner, an edge of the oxide semiconductor layer150may be placed within the regions C, D, and E as shown inFIG. 5.

Referring toFIG. 6, the second region50bhaving the thin thickness shown inFIG. 5is removed by an etch-back process. Herein, the first region50ais jointly etched therewith to reduce a width and a height thereof, and becomes a second photosensitive film pattern51. The second photosensitive film pattern51is formed at regions C′, D′, and E′ that are narrower than the regions C, D, and E ofFIG. 5.

Referring toFIG. 7, the metal oxide layer170pand the metal layer170are wet etched by using the etchant and the second photosensitive film pattern51as mask. Herein, the metal layer170is divided to form the data line171, the source electrode173, and the drain electrode175, and the metal oxide layer170pis divided to form the barrier layers171p,173p, and175p. Further, an upper surface of the oxide semiconductor layer150shown inFIG. 6is exposed to form the semiconductor layer151including the projection154forming a channel of the thin film transistor.

As such, the semiconductor layer151and the projection154having substantially identical planar patterns to those of the barrier layers171p,173p, and175pof the data line171, the source electrode173, and the drain electrode175and the data wire layers171,173, and175are formed by using photosensitive film patterns having different thicknesses. Specifically, planar patterns of the semiconductor layer151and the projection154are substantially identical to planar patterns of the data line171, the source electrode173, and the drain electrode175except for the exposed part between the drain electrode175and the source electrode173.

Next, referring toFIG. 8, a phosphine (PH3) treatment may be performed to form the metal phosphorus oxide layer177on surfaces of the source electrode173and the drain electrode175after the photosensitive film pattern is removed by ashing. The phosphine (PH3) treatment may be done by heat treatment or by plasma. In one or more exemplary embodiments, the phosphine (PH3) treatment is performed on an entire surface of the thin film transistor array panel to form a phosphide material layer176along the surfaces of the source electrode173and the drain electrode175.

Referring toFIG. 9, the phosphide material layer176is formed to cover the lateral surfaces of the source electrode173and the drain electrode175exposing the channel region.

Meanwhile, the channel region of the semiconductor layer154may be doped with phosphorus (P) by performing the phosphine treatment on the channel region of the semiconductor layer154. Herein, the phosphorus (P) may serve as a donor to form a conductive layer, reducing defects of the channel region of the semiconductor layer154and improving electrical conductivity may be lowered. This enhances a device characteristic of the thin film transistor array panel.

Referring toFIG. 10, the passivation layer180is disposed on the phosphide material layer176. The passivation layer180may be formed to include the lower passivation layer180aincluding a silicon oxide (SiOx) on the phosphide material layer176and the upper passivation layer180bincluding silicon nitride (SiNx) on the lower passivation layer180a. A nitrogen oxide, e.g., nitrous oxide (N2O), may be treated in a process of forming the lower passivation layer180aincluding a silicon oxide (SiOx), and the phosphide material layer176and nitrogen oxide react with each other, forming the metal phosphorus oxide layer177. The metal phosphorus oxide layer177may be a final form of the phosphide material layer176.

The thin film transistor array panel inFIG. 2may be formed by forming a contact hole185exposing a part of the drain electrode175by patterning the passivation layer180, and by forming the pixel electrode191on the passivation layer180. Herein, the pixel electrode191is formed to be physically connected to the drain electrode175through the contact holes185.

Hereinabove, it has been described that the thin film transistor array panel is configured to have a bottom gate structure that has a gate electrode disposed at a lower portion thereof, but embodiments are not limited thereto. For example, the thin film transistor array panel may adopt a top gate structure in which the gate electrode is disposed at an upper portion thereof.

FIG. 11is a cross-sectional view illustrating a liquid crystal display according to one or more exemplary embodiments.

Referring toFIG. 11, a second substrate210is disposed in such a position so as to face a first substrate110. The second substrate210may be an insulation substrate made of transparent glass, plastic, or the like. A light blocking member220is formed on the second substrate210. The light blocking member220is also called a black matrix and serves to prevent light leakage.

A plurality of color filters230are also disposed on the second substrate210and the light blocking member220. The color filters230are substantially disposed within a region surrounded by the light blocking member220, and may extend along the pixel electrode191. Each color filter230may display one of three primary colors such as red, green, and blue. However, embodiments are not limited thereto. For example, each color filter230may display one of cyan, magenta, yellow, and white series.

The light blocking member220and the color filters230have been described above as being formed in a facing display panel200; however, aspects of the light blocking member220and the color filters230are not limited thereto. For example, at least one of the light blocking member220and the color filters230may be disposed on the thin film transistor array panel100.

An overcoat250is disposed on the color filters230and the light blocking member220. The overcoat250may be made of an insulating material and serves to prevent the color filters230from being exposed and provide a flat surface. The overcoat250may be omitted.

A common electrode270is disposed on the overcoat250.

The pixel electrode191applied with a data voltage and the common electrode270applied with a common voltage generate an electric field, thereby determining a direction of liquid crystal molecules31of a liquid crystal layer3interposed therebetween. The pixel electrode191and the common electrode270constitute a capacitor and maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode191may constitute a storage capacitor by overlapping a storage electrode line (not illustrated), thereby enhancing a voltage-maintaining capacity.

The exemplary embodiment described with reference toFIG. 2may be applied to the thin film transistor array panel100.

Herein, it has been described that the thin film transistor array panel is applied to the liquid crystal display; however, embodiments are not limited thereto. One or more exemplary embodiments may be widely applied to a display device performing a switching operation by using an organic light emitting diode device or other thin film transistors.

FIG. 12is a graph illustrating an on-current characteristic depending on a gate voltage of a thin film transistor according to a comparative embodiment, andFIG. 13is a graph illustrating an on-current characteristic depending on a gate voltage of a thin film transistor according to an exemplary embodiment.

Referring toFIG. 12andFIG. 13, on and off of a source-drain current Ids depending on a gate electrode voltage Vg of the thin film transistor according to the exemplary embodiment are clearly distinguished based on a threshold voltage, and an on current is high, and thus the characteristic of the thin film transistor as a switching element may be improved. Further, the threshold voltage depending on the change of a source-drain voltage Vds is substantially unchanged, so it is seen that a uniform characteristic of the switching device may be maintained.

FIG. 14is a cross-sectional view illustrating a thin film transistor array panel according to one or more exemplary embodiments.

The description of the exemplary embodiment illustrated inFIG. 14is substantially identical to that of the exemplary embodiment illustrated inFIG. 2. Hereinafter, a different part from the exemplary embodiment ofFIG. 2will be described.

Referring toFIG. 14, the barrier layers171p,173p, and175pmay be interposed between the data wire layers171,173, and175, and the semiconductor layer151. The barrier layers171p,173p, and175pmay be formed of a metal oxide such as indium-zinc oxide, gallium-zinc oxide, aluminum-zinc oxide, titanium oxide, aluminum oxide, molybdenum oxide, or the like. The barrier layers171p,173p, and175pserve as diffusion preventing layers preventing the material such as copper or the like from being diffused to the semiconductor layer151.

In one or more exemplary embodiments, regions of the barrier layers171p,173p, and175pexposing the channel regions of the semiconductor layer151may be formed to be narrower than regions of the data wire layers171,173, and175exposing the channel region of the semiconductor layer151by using a mask that is different from a mask for patterning the data wire layers171,173, and175when patterning the barrier layers171p,173p, and175p. The barrier layers171p,173p, and175ptogether with the metal phosphorus oxide layer177surround the data wire layers171,173, and175. Therefore, they may prevent a metal component of the data wire layers171,173, and175from being diffused to an upper or lower layer.

According to one or more exemplary embodiments, the metal phosphorus oxide layer177may cover the data wire layers171,173, and175. The data wire layers171,173, and175may not be oxidized. Therefore, the thin film transistor array panel having improved reliability may be provided.