Serial radio frequency to baseband interface with power control

An interface between an RF processing section and a baseband processing section supports general purpose message transmission as well as satellite positioning system signal sample transmission between the RF processing section and the baseband processing section. The interface includes a bi-directional message interface and a data interface. The message interface supports transmission of power control messages to the RF processing section to provide detailed control over activation or de-activation of individual blocks of hardware circuitry in the RF processing section.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an interface for coupling a radio frequency (RF) processing section to a baseband processing section. More specifically, this invention relates to communicating power control messages from the baseband section to the RF section.

2. Related Art

The worldwide use of wireless devices such as two-way radios, pagers, portable televisions, personal communication system (“PCS”), personal digital assistants (“PDAs”) cellular telephones (also known as “mobile phones”), Bluetooth devices, satellite radio receivers and Satellite Positioning Systems (“SPS”) such as the Global Positioning System (“GPS”), also known as NAVSTAR, is growing at a rapid pace. Current trends are calling for the incorporation of SPS services into a broad range of electronic devices and systems, including PDAs, cellular telephones, portable computers, automobiles, and the like.

At the same time, manufacturers design their devices using very different architectures, spanning a wide variety of processors, frequency references, clock rates, and the like. The manufacturers are also very interested in keeping costs as low as possible while providing as much functionality (including SPS capability) as possible. In particular, architectures which split SPS signal processing between a radio frequency (RF) front end a baseband processing section continue to be popular.

For example, SiRF Technology, Inc. of San Jose, Calif. made popular an SPS chipset that included the GRF1 RF chip and GSP1/LX baseband processing chip. These two devices are described in detail in the SiRFStarg® I GPS Architecture GRF1 and GSP1 data sheets. As shown inFIG. 1, the RF chip102communicated data samples to the baseband chip104using differential sign signal lines (labeled SIGN), differential magnitude signal lines (labeled MAGNITUDE), a GPS clock signal line (labeled GPSCLK), and an acquisition clock signal line (labeled ACQCLK). The baseband chip104could communicate with the RF chip102in a limited single purpose fashion, namely, by using automatic gain control (AGC) clock, data, and strobe signal lines (labeled AGCCLK, AGCDATA, and AGCSTRB respectively) to provide AGC data to the RF chip102.

More recent SPS signal processing chipset solutions include the SiRFStar® IIe (centered around the GRF2i RF chip and GSP2e baseband chip) and SiRFStar® IIt (centered around the GRF2i RF chip and GSP2t baseband chip) solutions. Both retained the multiple signal lines used to communicate data samples from the RF section to the BB section and the unidirectional communication of AGC information from the baseband section to the RF section. However, the BB section communicated AGC information unidirectionally to the RF chip using a single pulse width modulated output that the RF chip sampled. In other words, the SiRFStar® IIe eliminated the multiple signal line AGC communication path in favor of a single output line.

For power control, the RF chip typically included a dedicated power control input, for example, one power control input pin that would enable or disable the majority of the RF chip. Thus, there was little or no ability to exercise detailed control over the power consumed by the RF chip. In other words, when the RF chip was active, so were most of the hardware blocks (e.g., phase locked loops, frequency dividers, digital interface sections, and the like) in the RF chip, whether they were needed at the time or not. As a result, the RF chip would consume greater average power than was otherwise necessary. Particularly when incorporated into a device with limited power reserves, such as a battery operated GPS receiver, excess power consumption was a significant drawback.

Therefore, a need exists to overcome the problems noted above and others previously experienced.

SUMMARY

The invention provides RF power control messaging, as well as related methods of providing RF power control messaging, over an interface between an RF processing section and a baseband processing section. The interface supports general purpose bi-directional message transmission between the RF processing section and the baseband processing section. The interface further supports transmission of SPS signal samples between the two processing sections without adding undue complexity to the interface.

In one implementation, the interface includes a message serial interface and a data serial interface. The data serial interface communicates SPS signal sample data from the RF section to the baseband section. The message serial interface communicates messages, including power control messages, between the RF section and the baseband section.

As noted above, a message serial interface communicates power control messages between the processing sections. The message serial interface may include a message-in signal line, a message-out signal line, and a message clock signal line. In some implementations, the message serial interface may also include a slave-select signal line. A power control message may include, for example, multiple power control bits. Each power control bit may specify a power state (e.g., powered-up or powered-down) for pre-determined circuitry in the RF section.

The complexity of the data serial interface may be reduced, for example, by using a single data bit signal line to serially carry signal samples from the RF section to the baseband section. The data serial interface may also include a data clock signal line that provides timing for the signal samples. In particular, as an example, the data clock signal line may carry a data clock (that includes rising edges and falling edges) nominally running at 16 fo, where fo=1.023 MHz, while the data bit signal line may carry a data signal comprising serially transmitted data bits. In one implementation, a first type of data bit is valid on the rising edge of the data clock and a second type of data bit is valid on the falling edge of the data clock. As an example, the first type of data bit may be a sign bit, while the second type of data bit may be a magnitude bit.

DETAILED DESCRIPTION

A typical satellite positioning system (“SPS”) system has approximately 12 satellites that may be visible at any one time to a wireless device. As used in this document, SPS means any system utilizing satellites and/or land-based communications devices for providing or enabling the determination of a location of the wireless device on the earth, including, but not limited to: a global positioning system (“GPS”) (such as NAVSTAR), GLONASS, LORAN, Shoran, Decca, or TACAN. For the purposes of discussion, specific examples of an interface between a GPS RF processing section and a baseband processing section are described. However, the principles underlying the interface are applicable to interfacing RF processing and baseband processing sections in general.

Turning first toFIG. 2, that figure shows a receiver200of a satellite positioning system. The receiver200includes an RF processing section202coupled to a baseband processing section204using an RF-to-baseband interface206. The RF processing section202receives SPS signals, for example the 1575.42 MHz GPS signal, on the RF input207.

The receiver section200may be generally regarded as including an RF front end224and a baseband back end226. The RF front end224includes the RF processing section202and RF-to-baseband interface206. The RF front end224processes the SPS signals received on the RF input207through a sequence of downconversion, automatic gain control, and analog to digital conversion. The baseband back end226includes the baseband processing section204and RF-to-baseband interface206. The baseband back end226processes (using a microcontroller core, CPU, or other control logic) the sampled data provided by the RF front end224. The baseband back end226communicates the processed data to a digital device (e.g., a digital signal processor, general purpose microcontroller or CPU, or host PC) using one or more address, data, control, and clock signals that comprise the digital communication interface222.

Either or both of the RF front end224and baseband back end226may be implemented as individual single integrated circuits, for example. Thus, the RF front end224may be a single package that includes the RF input207(e.g., a particular input pin on the package), RF processing section202, and interface206(e.g., a set of interface pins as described in more detail below). Similarly, the baseband back end226may be a single package that includes the baseband processing section204, interface206, and digital interface222. The processing performed by the RF processing section204and baseband processing section204may be that set forth in more detail in the SiRFStar® I, II, or III chipset data sheets, while the interface206is described in more detail below. The SiRFStar® chipsets are available from SiRF Technology, Inc. of San Jose Calif.

Although, as shown inFIG. 2, the functional division between the RF front end224and the baseband backend226lends itself to being divided into two separate integrated circuits, many other implementations are possible. As one example, numerous discrete logic and signal processing circuit blocks may implement the RF, baseband, and interface206functionality. As additional examples, any of the circuitry underlying the functionality of the RF front end224and the baseband back end226may be incorporated into a single package (e.g., that encloses multiple integrated circuit dies) or integrated circuit, multiple packages or integrated circuits, or distributed across one or more circuit boards. In these implementations, individual wires, circuit board traces, or VLSI metal or polysilicon layers carry the interface206signals between the RF processing circuitry and the baseband processing circuitry.

Furthermore, any of the circuitry underlying the functionality of the RF front end224and the baseband back end226may be incorporated, with additional functionality, into a single package or integrated circuit, multiple packages or integrated circuits, or distributed across one or more circuit boards. As examples, the RF and baseband circuitry may be integrated on a die with digital or analog processing circuitry for cellular telephony, PDA operation, or engine, instrument, or electronics controllers for automobiles. Thus,FIG. 2, and the examples given above are not limiting; rather, one of ordinary skill in the art will appreciate that the particular implementation, division of functionality, and packaging of the circuitry that implements the RF processing, baseband processing, and interface206may vary widely depending on the application at hand, engineering considerations, cost considerations, and the like.

The interface206includes a message serial interface208and a data serial interface210. The message serial interface208provides for serial communication of general purpose messages bi-directionally between the RF section202and the baseband section204. In contrast, the RF section202employs the data serial interface210to transmit SPS signal samples to the baseband section204.

As an initial matter, it is noted that in general, the interface206signals shown inFIG. 2are CMOS compatible. In particular, the inputs, for logic one, are above 0.7*Vcc V, and, for logic zero, are below 0.3*Vcc V. Outputs, for logic one, are above Vcc-0.4 V, and, for logic zero, are below 0.4 V. The input/output pins generally operate in either the 2.5 V or 3.3 V voltage ranges, depending on the desired implementation. The real time clock (RTC) input/output pins may operate at 1.5 V, although they may be designed to tolerate 3.3 V levels if desired. Any of the signals, however, may be adapted to different voltage ratings or specifications depending on the desired implementation.

The message serial interface208, as shown inFIG. 2, includes the message-in signal line (labeled MSG_DO/MI), a message-out signal line (labeled MSG_DI/MO), a message clock signal line (MSG_CLK/MK) and a slave-select signal line (labeled MSG_CEB/SS_N[0]). The labels on the message signal lines indicate the direction of data flow from the perspective of the RF section202/baseband section204. For example, the message-out signal line (MSG_DI/MO) carries message bits input to the RF section202and output by the baseband section204.

The data serial interface210includes the data clock signal line (labeled ACQCLK) and the data bit signal line (labeled SGNMAG). The data serial interface210generally uses only a single data bit signal line to communicate, serially, data bits to the baseband section204(as discussed below in greater detail with regard toFIG. 3). Thus, the data serial interface210generally includes as few as two signal lines: one for a data clock and one for data bits. The data serial interface210is thus a low complexity solution for a SPS signal sample interface between the RF section202and the baseband section204.

As shown inFIG. 2, the receiver section200, on the RF processing side, also includes a real time clock (RTC) oscillator (OSC) and monitor section212. A 32 KHz crystal (or other clock source) provides an input clock214for the RTC OSC section212. The RTC OSC section212generates a clock output on the RTCLK/RIN signal line that the baseband section204uses to keep, as examples, GPS time or UTC time. The clock output is, for example, a 32,768 Hz 1.5 V CMOS output. The RTC OSC section212continues to run during power down modes to help the baseband section204maintain an accurate timebase.

However, monitoring circuitry (e.g., a rectifier coupled to the clock input and followed by a comparator) in the RTC OSC section212determines when the input clock214has consistently run (e.g., has stopped for no more than 10-30 clock cycles). If the clock has stopped for too long, then the RF section202sets a bit (e.g., sets a flip/flop output or sets a bit in a multi-bit status register) to indicate that the clock output has not been consistent (and, in some cases, that the baseband section204should search over the full range of the received SPS signal to determine the correct time).

The RF section202also accepts clocking input from either a crystal oscillator216or an external clock source218(e.g., a frequency reference provided in a wireless device). The clocking inputs216and218provide a clock source that a PLL divider chain in the RF section202uses to generate the ACQCLK signal. The clocking inputs216and218are collectively referred to below as the OSCCLK, while the PLL divider chain clock is referred to as the PLLCLK. The PLLCLK is typically set to generate a nominal frequency of 16 fo (where fo=1.023 MHz) on the data clock ACQCLK derived from the OSCCLK (or an internal reference).

At power-up, the OSCCLK (generally in the range of 5-27 MHz) is present on the ACQCLK output. A message (described below) commands the RF section202to switch ACQCLK from OSCCLK to the PLLCLK and from the PLLCLK to the OSCCLK. The ACQCLK signal may be a 2.5/3.3 V CMOS output with a duty cycle between 45% and 55% (except when switching clock sources, in which case ACQCLK may have an extended low cycle).

A power control signal (labeled PWRUP/RFPWRUP) may optionally be provided to control whether certain portions of the RF section202are powered-up. The power control signal may be connected, for example, to a voltage regulator enable pin in the RF section202to provide a coarse power-up/power-down control over the majority of the circuitry in the RF section202. On the other hand, the RTC OSC section212is separately powered so that it can continue to provide a clock to the baseband section204. The power control signal may be a 2.5/3.3 V CMOS signal. The baseband processing side includes an RTC logic section220. The RTC logic section220accepts the input clock generated by the RTC OSC and monitor section212as an aide in determining the current time as well as SPS location solutions.

The RTC logic section220also outputs the reset signal GRFRST_N/RESET_N (asserted low). The reset signal may be used to reset the state of control registers in the RTC OSC section212and the RF section202at power-on. For example, when GRFRST_N is asserted, the digital control registers on the RF processing side will be reset to their default states. The default states of the control registers allow the OSCCLK circuits to operate and allow the ACQCLK output to be driven by O CSCLK (when PWRUP) is asserted. When GRFRST_N is not asserted, then the RF section202operates according to its internal logic states.

In one implementation, the message serial interface signals are 2.5/3.3V CMOS I/O signals. The MSG_CLK/MK, MSG_DI/MO, and MSG_CEB/SS_N[0] signals are inputs to the RF section202. The MSG_DO/MI signal is an output from the RF section202with tri-state control. When the MSG_CEB/SS_N[0] is logic high, the MSG_DO/MI output is high impedance and may be driven by other devices that are also connected to the message serial interface208. Thus, the MSG_CEB/SS_N[0] output from the baseband section204operates as a slave selection signal that allows the RF section202to drive data on the MSG_DO/MI signal line. When additional devices are attached to the message serial interface208, the baseband section204may provide additional slave selection signal lines to determine which device is allowed to drive data on the MSG_DO/MI signal line.

The RF section202may also include one or more inputs for external analog sensors (not shown). Thus, a multi-channel analog to digital (A/D) converter in the RF section202may take measurements of analog input signals and communicate the results to the baseband section204. The analog inputs may include, but not be limited to, temperature inputs, gyro turn rate inputs, wheel tick inputs, or a battery voltage inputs.

Table 1 summarizes the operating modes for the receiver section200:

Turning next toFIG. 3, that figure illustrates a timing diagram300that shows the relationship between a data clock302and a data signal304. The data signal304provides SPS signal samples to the baseband section204. The SPS signal samples are derived from an SPS input signal received by an antenna connected to the RF section202. The ACQCLK signal line carries the data clock302, while the SGNMAG signal line carries the data signal304. The data signal304, which may be, for example, a 2.5/3.3 V CMOS output, transmits both sign bit data306and magnitude bit data308on the SGNMAG signal line. In one implementation, the data signal304provides sign and magnitude bit information determined by an A/D converter in the RF section202.

In other implementations, additional bits of information or quantization may be provided, in concert with a predetermined protocol or encoding technique applied to the data bits (e.g., a pseudorandom noise code) to allow the baseband section204to identify the data transmitted. Furthermore, the data signal304may transmit signal samples for different radio chains handled by the RF section202. For example, when the RF section202is processing SPS data, the data signal304may bear the two bits per sample (sign and magnitude) data pairs noted above. In contrast, when the RF section202is processing a different RF signal (e.g., a Bluetooth signal), the data signal304may instead transmit more or less bits per sample (e.g., 4 or 6 bits) in accordance with the guidelines established for processing that RF signal. Similarly, the data clock302may vary in frequency and duty cycle to meet the processing guideline for the RF signal that the RF section202is currently processing.

As shown inFIG. 3, the RF section202outputs the sign bit306when the data clock302is high and outputs the magnitude bit308when the data clock302is low. As shown inFIG. 3, the sign bit306is valid no less than TSETUP-Fbefore the falling edge310of the data clock302. Similarly, the magnitude bit308is valid no less than TSETUP-Rbefore the rising edge312of the data clock302.

The sign bit306remains valid no less than THOLD-Fafter the falling edge310of the data clock302. The magnitude bit308remains valid no less than THOLD-Rafter the rising edge312of the data clock302. The setup and hold times may vary from implementation to implementation. As one example, the setup and hold times may be approximately 5-10 ns.

The message serial interface208may be implemented in a wide variety of ways. In one implementation, the message serial interface208has the characteristics set forth below, although other implementations are also possible.

The message serial interface on the RF section202operates as a slave device to the baseband section204(or other master device that adheres to the characteristics set forth below). The inputs bits to the RF section202(on the MSG_DI line) are shifted into a 32 bit shift register227in the RF section202under control of the MSG_CLK. In one implementation, up to 32 bits are sent in one message block and data is received and transmitted with the most significant bit first. Simultaneously, the MSG_DO output bits are shifted out of the other end of the same shift register227. If output from the RF section202is not needed, then the MSG_DO output need not be connected. In one implementation, the MSG_CLK operates at up to 20 MHz and the message serial interface signals are, approximately, above 0.8*VCC V for logic 1 and below 0.2*VCC V for logic 0.

The slave select signal line (MSG_CEB) is active low for serial data transmission. The MSG_DI and MSG_CLK may therefore be ignored as long as MSG_CEB has been high for a pre-selected period of time (e.g., 5 ns). Data is sampled on the rising edge of MSG_CLK. In one implementation, a transition on MSG_DI or MSG_DO occurs at least 5 ns after the rising edge of MSG_CLK and stabilizes at least 5 ns before the next rising edge of MSG_CLK. The data is shifted on the falling edge of MSG_CLK. Continuing the example, the MSG_CEB signal may be active (logic 0) at least 10 ns before the rising edge of the first MSG_CLK and may remain active (logic 0) at least 10 ns after the last falling edge of MSG_CLK. The time interval in both cases may be, for example, one half of one clock cycle. The MSG_CEB signal may then be held inactive (logic 1) for at least 30 ns to provide time for the RF section202to latch the data.

If the MSG_CEB signal transitions high before all data in a message block have been sent, the data is discarded and not applied to RF section202registers. Unused bits in a message block are set to zero. However, a fast write mode is provided to allow for a shortened, one byte message. The fast write mode is assumed until more than 8 bits have been received. When more than 8 bits have been received, the RF section202expects to receive a full 32 bits for a valid message.

The RF section202outputs data (on MSG_DO) to the baseband section204in response to a message received from the baseband section204that requests the data. The baseband section204then sends a subsequent message to shift out the requested data in the RF section202shift register from the shift register. The subsequent message may be an independent operational message or it may be a dummy message sent for the sole purpose of shifting out the desired data.

FIG. 4illustrates a timing diagram400that shows the relationship between the slave select signal (MSG_CEB)402, the message clock signal (MSG_CLK)404, and the message data bit signals (MSG_DO and MSG_DI)306. Data transmission starts when the slave select signal402falls. The transmitted data are latched when the slave select signal402rises.

As shown inFIG. 4, the message-out signal line (MSG_DI/MO) and message-in signal line (MSG_DO/MI) each carry a serial bit stream. The serial bit stream on the message-out signal line represents a message selected from a group of predefined RF section messages that are transmitted from the baseband section204to the RF section202. Similarly, the serial bit stream on the message-in signal line represents a message selected from a group of predefined baseband section messages that are transmitted from the RF section202to the baseband section204.

The messages are not limited to any particular purpose or format. As explained in more detail below, the messages may include, but not be limited to, RF section power control messages, RF section test messages, clock status messages, analog measurement messages, channel conversion count messages, and the like.

In one implementation, there are four types of message blocks defined. Data [1:0] (in a 32-bit or 8-bit sequence) are address bits that define the four messages as shown in Table 2 below. Each message type is able to support both a fast write mode and a full write mode and spare capacity has been defined for both modes.

Exemplary contents of each message are shown in detail in Tables 3 through 8. Table 3 shows AGC and synthesizer control messages, Table 4 shows power control and synthesizer control messages, and Table 5 shows output request types for a selected message type. Table 6 shows output message types and Tables 7-8 show input message types, The columns define the contents as follows. The first column, labeled Bits, represents the message data bits, with bit0indicating the last bit transmitted. The second column, labeled Field Name, identifies the name of the field in the message. The third column, labeled Length, is the length of the field. The forth column, labeled Default, indicates the contents of the default parameter in the RF section202when power is first applied. The fifth column, labeled Contents, describes the allowed contents of the field. The sixth column, labeled Function, indicates what the field accomplishes. The seventh column, labeled _Pwr, indicates which power domain control bit shown in Table 4, if any, is used to drive these field outputs to zero on the interface to the RF section202.

Message type2provides for implementing output requests using a field that specifies up to 32 types of output requests. Message type3provides for expanding the input message types (or addresses) from 4 to 36. References below to the “synthesizer” are references to the PLL synthesizer clock generation circuitry in the RF section202. The PLL synthesizer is configurable, for example, by setting clock divider values to generate the PLLCLK from a number of different input reference frequencies.

TABLE 3Message Type 0: AGC and Synthesizer Control(Address [1:0] = 0)BitsField NameLengthDefaultContentsFunction_Pwr31:28Spare0 [3:0]400Spare27:8NUM [19:0]20TBD0x00000–0xFFFFFSpecifies the numerator ofSynththe fractional part of theloop divider in the PLLclock generation section ofthe RF section 202.7:2AGC [5:0]600x00–0x3FControls AGC gain in theRxRF section 2021:0Address200Defines message type[1:0]

Output message types are shown in Table 6. Spare messages have been defined for expansion or use in testing the RF section202. Since this data is input to the message interface from the RF section202, these fields are given names denoting input, such as spareInA. When the data is shifted out, it is positioned in the output data stream using the index values given. For example, spareInA [23:0] would be located in the final 24 bits shifted out in the 32 bit output field, so that eight leading zeros would be followed by spareInA [23] through spareInA [0] according to the convention of shifting out the most significant bit first.

Out_Dat [4:0]=4-8 specify 20-bit measurements taken by a dual slope A/D converter in the RF section202. As noted above, the A/D converter may have multiple channels connected to one or more analog measurement devices. As used below, Out_Dat [4:0]=9 specifies the valid clock bit maintained by the RTC OSC section212and described above.

Spare messages (useful for test or expansion purposes) are shown in 8. Because these data represent control bits output by the message interface to the RF section202, the data fields have been named to denote outputs, for example SpareOutA.

A test message has also been define for the SGNMAG output signal line. When TestSignMag [8]=one, the test mode is entered. When the bit is a zero, test mode is turned off. In test mode, the pattern specified in TestSignMag [7:0] is output, as long as ACQCLK is running, beginning with TestSignMag [7] while ACQCLK is high.

The DS_ADC_SEQ message specifies 24 bits that control the order in which the A/D converter performs a conversion on each of four input channels. More specifically, the 24 bits are partitioned into 12 pairs of bits; each pair specifies the next input channel to the analog multiplexer before the A/D converter. The pairs of bits thus control which channel is next digitized by the A/D converter and the four input channels may thereby be sampled at different rates.

Continuing with regard to Table 8. Address [6:2]=9 specifies that the clock status bit in the RTC OSC section212will be set to indicate a good clock, or (if bit8is a one) that the baseband section204is requesting the value of the clock status bit to be output by the RF section202. Address [6:2]=10 controls (e.g., via a multiplexer) the signal that the RF section202provides on the SGNMAG signal line. The default is the sign bit and magnitude bit information, while the alternative is the OSCCLK signal.

Bits2-7in the message format shown in Table 4 are power control bits. Those bits control whether particular hardware elements in the RF section202are powered-up or powered-down. The bits may be transferred from the shift register227in the RF section202and applied to power control circuits that apply or remove power from specific hardware elements. For example, bit5, the PLL_Pwr bit, controls power for a phase locked loop (PLL) circuit and frequency divider in the RF section202. When the RF section202receives a message that has bit5cleared, the RF section202may remove power from the PLL and divider circuitry by opening a switch through which power flows, driving a power regulator control pin, or through another mechanism. Similarly, when the RF section202receives a message that has bit5set, the RF section202may apply power to the PLL and divider circuitry by closing the switch, enabling the power regulator, or the like.

While the message format provides five power control bits for (2,3,4,5, and7), more or fewer power control bits may be provided depending on the implementation. Each bit specifies a power control state (e.g., power-up or power-down) for one or more sections of pre-selected circuitry in the RF section202. Furthermore, in other implementations, multiple bits may be employed to specify a power state that includes multiple levels of power control. Thus, for example, two bits may be employed to specify one of four different power states for a particular set of circuitry in the RF section202.

While Tables 2-8 provide one example of message formats, many other implementations are also possible. Shown below in Tables 9-11 is another exemplary format that employs 56-bit messages without using a 2-bit message block definition.

TABLE 11Charge Pump Programming Fieldscp<3>cp<2>cp<1>cp<0>100050 uA, Normal operation of charge pump1001100 uA, Normal operation of charge pump1010300 uA, Normal operation of charge pump1011500 uA, Normal operation of charge pump1100700 uA, Normal operation of charge pump1101900 uA, Normal operation of charge pump0011Test mode: all charge pump outputs source current0001Test mode: all charge pump outputs sink current0111Test mode: all charge pump outputs source and sinkcurrent simultaneously.

Tables 9-11 show an implementation in which the last eight bits of the message are power control bits. Thus, power control may be communicated through a fast message as set forth previously. As noted above, the power control bits determine whether particular hardware elements in the RF section202are powered-up or powered-down. The power control bits are not limited to controlling the hardware blocks described in Table 10 (or Table 4). Instead, depending on the implementation, the power control bits may be established in the message to control power to any desired hardware circuitry that will be incorporated into the RF section202.

The baseband section204may thereby establish a detailed control over the power consumed by the RF section202. In other words, the baseband section204may determine, at any given time, those hardware blocks in the RF section202that will operate, and those that will be powered down. As a result, the RF section202will consume less average power than an RF section in which all the hardware blocks operate continuously. Such power control is very useful in battery operated devices, or in any other SPS enabled device with a limited power supply.

Turning next toFIG. 5, that Figure shows a flow diagram500that shows a method for interfacing the RF section202and the baseband section204. In particular, with regard to the serial transmission of SPS signal samples to the baseband section204, the RF section202places a sign bit306on the SGNMAG signal line (step502), then provides a falling edge310on the ACQCLK line (step504). Subsequently, the RF section202places a magnitude bit308on the SGNMAG signal line (step506), then provides a rising edge312on the ACQCLK line (step508). This sequence repeats for each sign bit and magnitude bit sample pair transmitted to the baseband section204. SPS signal data is thereby serially transferred to the baseband section204.

With regard to message transmission between the RF section202and the baseband section204, the master device (typically the baseband section204) determines whether it needs to send or receive data over the message serial interface208(step510). If so, the baseband section204determines if the message is a fast write message (step512). If the message is a fast write message, then the baseband section204(if it is transmitting data) or the RF section202(if it is transmitting data) serially places 8 data bits on the appropriate serial message data line. Each data bit is shifted in by a message clock404transition for each data bit. (step514). Otherwise, the baseband section204or the RF section202serially places all the data bits (e.g., 32 or 56 data bits) on the appropriate serial message line, with each data bit accompanied by a message clock404transition (step516).

The slave select signal line may be used to transfer timing between the baseband section204and the RF section202. In particular, the COUNT[19:0] output (see Table 6, Out_Dat=8) represents the value of a counter present in the RF section202that reveals the sampling phase of the dual slope A/D converter in the RF section202. The slave select signal line is connected to circuitry in the RF section202that latches DSP timing. Thus, the COUNT value is the value in the counter at the time the slave select signal causes the message that requests the COUNT output to latch the COUNT value into the shift register for transmission. In the baseband section204, the slave select signal latches a counter (or another representation of time) when the slave selected signal is de-asserted (which is also when the RF section202latches COUNT).

The A/D sample timing may thereby be related to the baseband section204timing. The SHIFT[19:0] input (see Table 8, Address=6) is used to shift the A/D timing to a desired offset from the baseband section204timing. As a result, the baseband section204may change the timing of the RF section202circuitry without additional interface lines.

Thus, systems and methods consistent with the invention provide power control messaging (and methods of operating or providing interfaces) between an RF processing section202and a baseband processing section204. The messaging may be employed for many different purposes, and is particularly useful as part of general power control in an SPS device to reduce average power consumption and extend power supply life.

Typically, powering down as much of the RF section202as possible except when taking SPS signal samples helps reduce average power consumption. Taking the samples may in some instances occupy a time span as short as 10-20 ms in strong signal environments outdoors, or 50-100 ms in less favorable conditions outdoors. Indoors, the RF section202may operate for a time span on the order of a few seconds to obtain SPS signal samples, particularly for when the signal is weak. Note also that powering down the RF oscillator212when the baseband section204enters its own power down mode may also reduce power consumption.

More specifically, an exemplary operational sequence, including power control may proceed as shown below in Table 12:

TABLE 12Operational StepDescriptionInitial PowerupAn alarm, timer, or wakeup circuit connected to or incorporatedinto the RF section 202 or baseband section 204 turns on a powersupply connected to the RF section 202 and the baseband section204.Baseband StartThe RF oscillator 212 powers up and provides a clock signal to thebaseband section 204. The baseband section 204 boots up usingthe clock signal.Baseband InitializationThe baseband section 204 performs housekeeping tasks, Input/Output initialization, or other processing in preparation for RFsection 202 startup.RF Synthesizer StartupThe baseband section 204 powers up the RF clock synthesizer inthe RF section 202 and waits a pre-determined time for the RFclock synthesizer to stabilize.RF Circuitry StartupThe baseband section 204 turns on power to the LNA, AGC, A/D,and other selected circuitry in the RF section 202 and waits a pre-determined time for those sections to stabilize.SamplingThe baseband section 204 starts taking data samples from the RFsection 202.StorageIn some modes of operation, the baseband section 204 directsstorage of a block of data samples obtained from the RF section202.RF Circuitry ShutdownThe baseband section 204 turns off the LNA, AGC, A/D and RFclock synthesizer circuitry in the RF section 202.GPS MeasurementThe baseband section 204 directs processing of the stored datasamples in order to extract GPS measurements from the datasamples.Location UpdateThe baseband section 204 determines a position update anddelivers the update to a recipient over an Input/Output interface.Wakeup ProgrammingThe baseband section 204 programs the timer, alarm, or wakeupcircuit for the next wake up alarm and begins shutdown.ShutdownThe baseband section 204 initiates shutdown, gates off clocks, andpowers down the RF section 202 and the baseband section 204(except for the wakeup alarm circuitry).