Over current protection in a variable output power supply

In accordance with embodiments of the present disclosure, a switch mode power supply may include a transformer, a controller configured to generate a periodic switching signal, a switching transistor coupled between a sense node and the transformer, primarily configured to prevent or permit current flow in the transformer primary winding in accordance with the switching signal, a sense resistor coupled to the switching transistor at a sense node, and a limit circuit configured to obtain a voltage of the sense node at a particular point of the switching period as an indicator of the primary winding current, detect a duration of a demagnetizing interval, and generate a limit signal, based on the sense node voltage and the demagnetizing interval, indicating a power supply output current exceeding a limit threshold.

TECHNICAL FIELD

Disclosed subject matter pertains to switch mode power supplies and, more particularly, variable output power supplies and ensuring compliance with applicable current power limits across all available supply voltages.

BACKGROUND

As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information.

Because information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. Information handling systems may also include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.

Information handling systems may be configured to couple to various peripheral devices over a variety of interfaces that support various peripheral bus protocols including peripheral bus protocols that support different acceptable supply voltages. As one non-limiting example, the universal serial bus (USB) power development (PD) protocol supports 5 V, 12 V, and 20 V supply voltages. Compliance with USB PD or any other protocol that supports multiple supply voltages may require a variable output power supply and the information handling system may have to ensure that the variable output power supply is compliant with power, current, and/or voltage limits and safety standards, regardless of which of the available supply voltages was selected.

Implementing a power supply capable of delivering any one of two or more available voltages and ensuring that the power supply complies with limits specified by peripheral bus standards and safety standards increases the complexity of the information system handling system.

SUMMARY

In accordance with the teachings of the present disclosure, disadvantages and problems associated with ensuring compliance with voltage, current, and power requirements and limits imposed by various electrical standards in systems that employ a variable output power supply may be reduced or eliminated.

In accordance with embodiments of the present disclosure, a switch mode power supply may include a transformer, a controller, a switching transistor, a sense resistor, and a limit circuit. The power supply may be a variable output power supply configured to output any one of multiple supported output voltages. The transformer may include a primary winding configured to receive a primary voltage and a secondary winding configured to couple a secondary voltage, induced by the primary voltage, to an output. The controller may be a pulse width modulator controller configured to control a duty cycle of a signal based upon a control voltage or control current. The controller may be configured to generate a switching signal having a switching frequency, f, and a corresponding switching period, Ts. The switching period Ts, which is also referred to herein as the switching cycle, may include an on phase, Ton, during which the switching transistor conducts primary winding current and an off phase, Toff, during which the switching transistor is off to prevent primary winding current.

A control electrode of the switching transistor may be coupled to the controller to receive the switching signal. First and second output electrodes of the switching transistor may be coupled in series between the transformer primary winding and a sense resistor so that primary winding current flows through a current path between the switching transistor output terminals and into the sense resistor when the switching transistor is activated. In this configuration, the sense resistor voltage is indicative of the primary winding current. The sense resistor may be coupled between ground and a sense node so that the sense node voltage, Vcs, indicates the primary winding current.

The limit circuit may be configured to generate a limit signal indicating an output current or other output parameter exceeding a limit threshold. The power supply may be a variable output power supply and, beneficially, the limit circuit may be configured to determine the limit signal without reference to the output voltage or to any other “secondary parameter” i.e., any parameter measurable at or beyond the secondary winding of the transformer. In addition, the limit signal may be determined independent of a voltage across a bulk capacitor coupled to the primary winding.

The limit circuit may include a sense circuit configured to sample the sense node voltage Vcs or another sense node parameter at a particular point of the switching cycle. The limit circuit may further include a demagnetizing circuit configured to signal a demagnetizing interval of the switching period, a modulating circuit configured to multiply or otherwise modulate the sampled value of the sense node parameter in accordance with a duration of the demagnetizing interval, and a comparator configured to compare the output of the modulating circuit with a limit reference value and produce the limit signal as the comparator output.

In at least one non-limiting embodiment in which the sense node parameter is the sense node voltage, the limit circuit is configured to sample or otherwise sense the sense node midpoint voltage, Vcs_m, which refers to the value of Vcs at a midpoint of the Ton phase of the switching cycle and use Vcs_m as the average value of the sense node voltage Vcs to indicate the average value of the primary winding current during a Ton phase to determine the average value of the output current Iout. Recognizing that the average value of the primary winding current during the Ton phase reflects the average value of the output current during the transformer's demagnetizing interval, the limit circuit may detect the demagnetizing interval and generate the limit signal based on Vcs_m and the duration of the demagnetizing interval.

The sense circuit of the limit circuit may be configured to signal the Ton midpoint, referred to herein as Ton/2, by charging a reference capacitor with a first reference current during a first Ton phase and discharging the reference capacitor with a second reference current during a subsequent Ton phase, where a magnitude of the second reference current discharges the reference capacitor twice as fast as the first reference current charged it. The sense node midpoint voltage, Vcs_m, may be coupled to an input of a voltage-controlled current source for the duration of the demagnetizing period and the output of the voltage controlled current source may be configured to charge a capacitor so that the capacitor's voltage reflects the product of Vcs_m and the duration of the demagnetizing interval.

The limit circuit may be configured to signal a beginning of the demagnetizing interval in accordance with a transition of the switching signal at an end of a Ton phase. The end of the demagnetizing interval may be signaled in accordance with either of two events depending upon whether the transformer is operating in a continuous current mode (CCM) or a discontinuous current mode (DCM). The demagnetizing interval end may be signaled by the end of the switching signal Toff phase for CCM operation and by a transient, negative voltage spike or pulse of the switching signal for DCM operation. Although the description of the figures to follow emphasizes a variable output power supply configured as a flyback voltage converter, other embodiments may implement a forward converter.

In accordance with embodiments of the present disclosure, an information handling system may include a processor, storage, accessible to the processor, one or more input/output (I/O) interfaces for communicating with one or more peripheral devices via respective peripheral buses, and a variable output power supply that includes a limit circuit as described above. The I/O interfaces may include a bus controller configured to communicate with one or more external devices via one or more I/O buses powered by the variable output power supply. The I/O bus may support multiple different supply voltages and the bus controller may select a supply voltage for the I/O bus from a group of available supply voltages.

In at least one embodiment, the limit circuit may be provided within a pulse width modulation (PWM) integrated circuit (IC) that includes a PWM controller.

DETAILED DESCRIPTION

Preferred embodiments and their advantages are best understood by reference toFIGS. 1-8, wherein like numbers are used to indicate like and corresponding parts.

For the purposes of this disclosure, information handling resources may broadly refer to any component system, device or apparatus of an information handling system, including without limitation processors, service processors, basic input/output systems (BIOSs), buses, memories, I/O devices and/or interfaces, storage resources, network interfaces, motherboards, power supplies, air movers (e.g., fans and blowers) and/or any other components and/or elements of an information handling system.

FIG. 1illustrates, in block diagram, a data handling system100that employs a power supply with a limit circuit as described herein or analogous functionality. The data handling system100illustrated inFIG. 1includes a processor101coupled to a peripheral device135by way of a peripheral bus133controlled by a bus controller132. The illustrated bus controller132is coupled to variable output power supply160, which provides a supply voltage165to bus controller132. Bus controller132may couple supply voltage165to a supply interconnect134of peripheral bus133.

The illustrated bus controller132and variable output power supply160may negotiate or communicate via power supply control bus161to determine the particular supply voltage165that variable output power supply160will generate. Variable output power supply160may be configured to generate any one of two or more supply voltages. In one non-limiting embodiment suitable for use in conjunction with a bus controller implementing a universal serial bus in compliance with the USB Power Delivery (USB-PD) specification, variable output power supply160and bus controller132may negotiate or otherwise communicate to identify any one of three different available supply voltages including 5 V, 12 V, and 20 V supply voltages.

The variable output power supply160illustrated inFIG. 1is an AC to DC converter that receives a main supply voltage or another AC signal and generates a DC supply voltage165. In other embodiments, variable output power supply160may receive a DC voltage generated by a battery (not shown) or a different power supply or voltage regulator (now shown). Variable output power supply160is illustrated inFIG. 1communicating with only one bus controller132and providing only a single supply voltage output. Embodiments of variable output power supply160may generate multiple independent supply voltage signals for any one or more of a variety of bus controllers implementing various bus protocols or standards, any one or more of which may be a “variable output” signal if supported by the applicable standard or protocol. In addition, while variable output power supply160is illustrated inFIG. 1providing supply voltage165to peripheral devices, embodiments of variable output power supply160may provide supply voltages for additional components and subsystems of data handling system100including as non-limiting examples, a memory array supply voltage, a processor supply voltage, and a display device supply voltage.

The illustrated bus controller132may be one of multiple bus controllers supported by an I/O chip130of a 2-chip chip set110. The illustrated I/O chip130is coupled to a memory/graphics controller120of chip set110. The memory/graphics controller120illustrated inFIG. 1is coupled to a main memory105via a memory bus106and coupled to a display140via an intervening display controller135and a dedicated graphics bus136. The display controller135is shown inFIG. 1coupled to a dedicated display memory137. The elements of data handling system100illustrated inFIG. 1are exemplary of various types of information handling systems including, as non-limiting examples, desktop and laptop computers. Other types of information handling systems may include additional, fewer, or different elements or devices than the elements and devices shown inFIG. 1. In addition, althoughFIG. 1illustrates a chip set110in a traditional 2-chip north bridge/south bridge configuration, chip set110may be implemented with more, fewer, or different devices than illustrated inFIG. 1and functionality associated with two or more distinct elements illustrated inFIG. 1may be integrated into a common device while elements of the illustrated memory/graphics controller120may be integrated into processor101or display controller135.

FIG. 2illustrates an example variable output power supply160. The variable output power supply160illustrated inFIG. 2is a flyback converter power supply that includes an additive polarity transformer200that provides galvanic isolation between a transformer primary side210, which is coupled to a primary winding201of transformer200, and a transformer secondary side220, which is coupled to a secondary winding202of transformer200.

The transformer primary side210illustrated inFIG. 2includes a rectification stage212that receives an AC input signal103and outputs a rectified signal215. The illustrated rectification stage212includes an electromagnetic interference filter214and a diode bridge216. EMI filter214may filter high-frequency noise associated with diode switching while otherwise preserving the AC input signal. Diode bridge216rectifies AC input signal103to produce rectified signal215.

The transformer primary side210of the variable output power supply160illustrated inFIG. 2further includes a DC stage217that receives the rectified signal215from rectification stage212. The illustrated DC stage217applies the rectified signal215across a bulk capacitor218coupled between ground and a primary DC node203that is coupled to an upper electrode of primary winding201. A low pass filter221comprised of a resistor222in parallel with a capacitor223is coupled in series with a diode224across the primary winding201. Low pass filter221provides high frequency attenuation of any ripple components in the rectified signal215while diode224prevents the formation of a current path bypassing primary winding201.

The transformer secondary side220illustrated inFIG. 2includes a secondary winding202coupled to a rectifying diode225and an output capacitor226. The rectifying diode225is shown with its anode coupled to an upper electrode of secondary winding202at a secondary DC node204and its cathode coupled to an output node227of power supply output port228. Output capacitor226is coupled in parallel with output port228.

The variable output power supply160illustrated inFIG. 2is a switch mode power supply driven by a pulse width modulation (PWM) integrated circuit (IC)240that includes a PWM controller250and a limit circuit270. The PWM controller250illustrated inFIG. 2is configured to generate a periodic switching signal251and provide the switching signal251to a control electrode261of a switching transistor260. Switching transistor260is configured to either prevent or permit current flow in primary winding201in accordance with the switching signal251.

The switching transistor260illustrated inFIG. 2is an n-channel metal-oxide semiconductor (NMOS) transistor that includes a gate electrode as its control electrode261and a drain electrode and source electrode as its output electrodes262and263. Other embodiments of variable output power supply160may employ a p-channel MOS (PMOS) switching transistor, a complementary MOS (CMOS) switching transistor gate that includes an NMOS transistor and a PMOS transistor, a bipolar junction transistor, or another suitable switching device.

Switching transistor260is shown with its output electrode262coupled to a lower electrode of primary winding201and its output electrode263coupled to a node referred to herein as sense node265. A resistor referred to herein as sense resistor266is illustrated inFIG. 2coupled between the sense node265and ground.

As illustrated inFIG. 2, assertion of switching signal251by PWM controller250activates switching transistor260and establishes a low impedance path between the switching transistor output electrodes262and263, thereby enabling the flow of a primary winding current, IP.

Thus, for the NMOS example of switching transistor260illustrated inFIG. 2, the primary winding current IP equals or substantially equals the source-drain current, Ids, of switching transistor260and, ignoring a presumably insignificant current drawn by a sense voltage input, CS, of PWM controller250, all or substantially all of the source-drain current Ids flows through sense resistor266to ground. Accordingly the sense node voltage Vcs is a direct indicator of the switching transistor Ids and the primary winding current IP as follows:
Vcs=Ids/Rs=IP/Rs

where Rs represents the resistance of sense resistor266and the equal signs are understood to ignore leakage currents, stray capacitances, and other non-ideal characteristics of the illustrated circuitry.

The PWM controller250illustrated inFIG. 2, in which sense node265is coupled to the current sense input CS of PWM controller250, is configured to monitor the switching transistor Ids and the primary winding current IP via the sense node voltage Vcs.

In at least one embodiment, the limit circuit270of PWM IC240monitors, via the sense node voltage Vcs, the primary winding current IP as a proxy for the output current Iout and compares a value derived from the primary current IP against a limit threshold that correlates to a particular Iout threshold. Limit circuit270may generate a limit signal271indicating the result of the comparison such that an over current condition is signaled by the limit signal271.

In accordance with embodiments of the present disclosure, limit circuit270may determine the state of limit signal271by sampling the sense node voltage Vcs at a particular juncture of the switching signal's switching period, determining or otherwise obtaining a duration of the transformer's demagnetizing interval, Tdem, modulating the sampled value of Vcs based on Tdem to obtain a limit proxy, and comparing the limit proxy to a limit reference. Because at least some pervasive and emerging peripheral bus protocols that support two or more supply voltages, including as one non-limiting example, USB PD, specify a maximum output power that scales with the supply voltage, limit signal271may simultaneously and beneficially signal an over current condition and an over power condition based on just two sensed inputs, neither of which references the output voltage Vout and both of which are “primary side parameters”, i.e., parameters detectable within the primary side210of transformer200.

By determining the limit signal271based on primary side parameters only, limit circuit270may be integrated with a conventional PWM controller, either within the same integrated circuit or as application specific logic coupled to a conventional PWM controller. The PWM IC240illustrated inFIG. 2illustrates limit circuit270and PWM controller250within a single integrated circuit, with limit circuit270configured to receive, as its inputs, the switching signal251from PWM controller250and the sense node voltage Vcs and further configured to generate limit signal271to signal a condition that indicates the output current Iout exceeding an output current threshold, e.g., an output current maximum value.

The PWM controller250illustrated inFIG. 2may employ features and functionality analogous to features and functionality of any one of various commercially distributed and widely available PMW controllers, which are commonly employed for low and medium power switch mode power supplies. Although specific signals and features of PWM controller250are illustrated inFIG. 2and described below, embodiments of variable output power supply160may employ a PWM controller with different specific features and signals.

The PWM controller250ofFIG. 2receives a supply voltage from an auxiliary winding280of transformer200. The auxiliary winding280is illustrated implemented with additive polarity and coupled between ground and an auxiliary node281. Auxiliary node281is coupled to a VDD input of PWM controller250through a rectifying circuit that includes a resistor283and a diode282configured to charge a storage capacitor284during Toff intervals, which may also be referred to herein as Toff phases, of switching signal251, i.e., intervals or phases within a switching period, Ts, of switching signal251during which the output impedance of switching transistor260is open or very high, e.g., exceeding 1 MΩ, while storage capacitor284provides the supply voltage during Ton phases of switching signal251.

Auxiliary node281is illustrated inFIG. 2further coupled to a PRT input of PWM controller250via a resistive divider circuit286that includes a resistor287, a diode288, and a temperature-controlled resistor or thermistor289. The voltage sensed at PRT input may be used to provide over temperature protection and overvoltage protection.

An FB input of the depicted PWM controller250receives a feedback signal295from an output sensing circuit290on the transformer secondary side220. The FB input of PWM controller250may influence a duty cycle of the switching signal251or other parameters. The output sensing circuit290illustrated inFIG. 2preserves galvanic primary-secondary isolation by employing light emitting diode291in proximity to an optically activated switch293. The voltage of the PWM controller FB input varies with the LED current which, in turn, varies with the output voltage Vout so that the FB input is indicative of Vout.

The CS input of PWM controller indicates the primary winding current IP as described previously. The CS input, like the FB input, may influence the duty cycle or other characteristics of switching signal251.

FIG. 3illustrates example voltage and current signals generated within variable output power supply160. The signals illustrated inFIG. 3, which include three voltage signals and two current signals, reflect the behavior of variable output power supply160during CCM operation.

The three voltage signals illustrated inFIG. 3include a Vds signal indicating the voltage across output electrodes262and263of the NMOS example of switching transistor260, a Vcs signal indicating the voltage across sense resistor266ofFIG. 2, and a VG or gate signal indicating the switching signal251output from the gate pin of PWM controller250and provided to the gate electrode261of switching transistor260.

The two current signals illustrated inFIG. 3include Ids and Iout. Ids represents the source-drain current flowing between output terminals262and263of switching transistor260, which is equal to the primary winding current IP. For purposes of describingFIG. 3andFIG. 4, references to Ids may be understood as referring to the primary winding current and vice versa. The output current Iout represents the current provided to a load (not explicitly depicted inFIG. 2) coupled to output port228. Since Vout is a DC voltage the output capacitor drawings zero or de-minimis steady state current and Iout equals or substantially equals the secondary winding current, IS (the current flowing through secondary winding202). For purposes of describingFIG. 3andFIG. 4, references to Iout may be understood as referring to the secondary winding current and vice versa.

Qualitatively,FIG. 3illustrates a mode of operation in which PWM controller250asserts switching signal251for a first interval or phase, referred to herein as the Ton phase, at the beginning of each switching period Ts. Switching signal251is then deasserted for a second phase referred to herein as the Toff phase. Ignoring rise and fall times of switching signal251, the switching period Ts, which corresponds to a switching frequency, f, where Ts=1/f, equals the sum of Ton and Toff.

Embodiments of variable output power supply160employing an NMOS transistor as switching transistor260assert switching signal251by forcing the control electrode261to a positive voltage exceeding the switching transistor's threshold voltage. Conversely, de-asserting switching signal251refers to forcing the control electrode261to ground or another voltage that is less than the switching transistor threshold voltage. Other embodiments may require signals of opposite polarity, different magnitude, or both.

The CCM operation illustrated inFIG. 3may be recognizable by the finite, non-zero value, Ids_o, of primary winding current at the beginning of each Ton phase and a finite, non-zero value, Iso, of output current Iout, at the end of each Toff phase.

During each Ton phase, Ids increases linearly or substantially so from its initial value Ids_o to its peak value Ids_p at the end of the Ton phase. Similarly, the sense voltage Vcs, which tracks Ids in accordance with Ohm's law, increases linearly or substantially so from its initial value Ids_o to its peak value Ids_p at the end of each Ton phase.

After switching signal251is de-asserted at the beginning of Toff, Ids drops to zero and Vds jumps up to a peak value before settling and then decreasing linearly or substantially linearly for the remainder of Toff. At the beginning of each Toff phase, Iout obtains a peak value Isp and decreases linearly thereafter from Isp to Iso at the end of Toff. The slope of the Ids signal during Ton is proportional to the ratio of the voltage across primary winding201and inversely proportional to the primary winding inductance. Similarly, the slope of Iout during Toff is proportional to the voltage across the secondary winding202, which is substantially equal to Vout, and inversely proportional to the secondary winding inductance.

The instantaneous output power Pout is equal to the product of the output current Iout and the output voltage Vout. Similarly, the average output power Pout_avg equals the product of the Iout_avg and Vout_avg. For a power supply such as variable output power supply160that generates a DC output voltage, Vout_avg equals Vout and Pout_avg is directly proportional to Iout_avg.

During Ton, Iout is 0. During Toff, Iout decreases linearly from Isp to Iso and the average value of Iout during Toff is (Isp+Iso)/2. The average value for the entire switching period may be obtained by multiplying the average value of Iout during Toff by Toff/f, the percentage of the switching period during which this average value output current flows, yielding:

where f is the switching frequency of switching signal251. Equation 1 can be expressed in terms of the duty cycle D, which is defined as Ton/Ts, by noting that (Ton/Ts)+(Toff/Ts)=1, substituting D for Ton/Ts, and rearranging to obtain: Toff/Ts=1−D. Substituting 1−D for Toff/Ts in Equation 1 yields:

The secondary side parameters Isp and Iso may be converted to primary side parameters Ids_p and Ids_o via the turns ratio, n, of transformer200, as follows:
Isp+Iso=n(Ids_p+Ids_o)   Equation 3

where n is the ratio of secondary winding turns to primary winding turns. Substituting the right side of Equation 3 into the Isp+Iso term in Equation 2 yields:

Expressing equation 4 in terms of Toff and the switching frequency, f, yields:

Iout can then be expressed in terms of the sense node voltage Vcs as follows:

Equation 6 expresses a parameter to be monitored, Iout, according to the primary side parameters Vcs, Rs, Toff, and f, and expresses the parameter to be monitored without reference to the output voltage Vout. A limit circuit270that receives the sense voltage Vcs and the switching signal251can determine Toff and set a limit for Iout for any values of n and Rs without sensing or otherwise obtaining the specific output voltage Vout. The USB PD specification, as one non-limiting example, defines five power profiles and supports three supply voltages: 5 V, 12 V, and 20 V. Because each of the USB PD profiles corresponds to a particular maximum output current, variable output power supply160may set a single limit threshold that will accommodate any output voltage supported by the profile. For example, USB PD profile5encompasses 12 V and 20 V supply voltages and specifies a 5 A limit, which translates to a power limit of 60 W for 12 V operation and 100 W for 20 V operation. By setting the limit threshold271to trigger at Iout greater than or equal to 5 A, variable output power supply160provides power and current protection simultaneously for all profile-compliant configurations.

FIG. 4illustrates DCM operation of the power supply using the same signals asFIG. 3. DCM operation is characterized by zero energy in the transformer windings, i.e., zero transformer winding current, at the beginning and end of each switching period. In DCM mode, the sense node voltage Vcs and Ids both increase linearly during Ton from0to peak values Vcs_p and Ids_p respectively at the end of Ton. When switching signal251is deasserted, Ids drops to zero and the output current Iout jumps from zero to a peak value Isp, after which Iout decreases linearly for the remainder of an interval commonly referred to as the demagnetizing interval and denoted inFIG. 4as Tdem. At the end of Tdem, the output current has dropped from Isp to 0 and the transformer inductors are depleted of energy. At the point where the secondary winding energy is first fully dissipated, sometimes referred to as the “knee” point, the Vds of switching transistor260drops suddenly. Due to capacitive coupling between the gate and drain of switching transistor260, the voltage on the gate electrode drops below 0 V, i.e., negative voltage, at the end of Tdem before stabilizing. In at least one embodiment, limit circuit270may be configured to detect the end of the demagnetizing interval during DCM operation by monitoring for the gate electrode voltage dropping sufficiently below 0 V, i.e. The magnitude of the gate voltage drop at the knee point may vary among different implementations, but may be 100 mV or more in some embodiments i.e., the gate electrode voltage may drop to −100 mV or less.

Equation 6 expresses the average output current limit for CCM operation in terms of the peak and initial sense node voltages Vcs, the turns ratio n, the sense resistor resistance Rs, the switching frequency, f, and Toff. An analogous equation for DCM mode operation can be obtained by dropping the Vcs_o term of Equation 6 and substituting Tdem for Toff, resulting in:

Referring back toFIG. 3,FIG. 3illustrates graphically that Iout may be represented in terms of a single value of Vcs and more specifically, the value of Vcs occurring at Ton/2, where Ton/2 represents the chronological midpoint of Ton. Similarly,FIG. 4and Equation 7 illustrate that, for DCM operation, the same applies, i.e., Iout may be expressed in terms of the Vcs midpoint value, Vcs_m, which represents the value of Vcs at the point in time occurring Ton/2 into the switching period Ts. In at least one embodiment, limit circuit270implements this observation by determining the state of limit signal271based on a single sampled value of Vcs, the Ton/2 value of Vcs.

The PWM IC240illustrated inFIG. 2includes limit circuit270configured to sample or otherwise obtain Vcs_m, the Ton/2 value of Vcs, and modulate or otherwise convert Vcs_m to derive a quantity or value referred to herein as a limit proxy, which can be compared to a limit reference to determine the state of limit signal271for indicating over current conditions, i.e., a value of Iout exceeding a particular limit threshold.

FIG. 5illustrates exemplary detail of a limit circuit270configured to receive switching signal251and the sense node voltage Vcs as its inputs. The illustrated limit circuit270includes a Ton/2 circuit502that generates Ton/2 signal504to control a first switch S1, a Tdem circuit510that generates a Tdem signal512to control a pair of switches S2and S2b, a voltage controlled current source520and a comparator530. Switches S1and S2bmay be normally open switches while S2may be normally closed. Switches S2and S2bmay be logically complementary switches, wherein S2closes when S2bopens and vice versa.

The illustrated limit circuit270couples the sense node voltage Vcs to sampling capacitor C1when S1is closed. In at least one embodiment, Ton/2 circuit502, further described inFIG. 6, closes S1at the beginning of a switching period, keeps S1closed for a duration of Ton/2, and opens S1for the remainder of the switching cycle. Because a portion of Ids may be needed to charge capacitor C1after S1is closed, some embodiments may select a C1that results in an RC delay, Rs*C1, less than Ton/2 to ensure that, at Ton/2, substantially all of Ids flows through the sense resistor Rs so that, Vcs at Ton/2 is equal or substantially equal to Rs*Ids at Ton/2.

The Tdem circuit510illustrated inFIG. 5, and further described with respect toFIG. 8, asserts Tdem signal512for a duration equal to the demagnetizing interval. The Tdem signal512controls switches S2and S2bto couple the negative input522of a voltage controlled current source (VCCS)520either to reference capacitor C1or to a reference voltage identified inFIG. 5as limit reference voltage Vref to capacitor C1to a reference voltage Vref apply the sampling capacitor voltage Vc1to a negative input522of a voltage controlled current source (VCCS)520. The positive input524of VCCS520is coupled to a limit reference voltage Vref. For the duration that S2remains closed and switch S2bremains open, VCCS520sources a DC current in accordance with:
Ivccs=Gm*(Vref−Vc1)

where Gm represents an adjustable transconductance of VCCS520. Because Tdem circuit510asserts Tdem signal512for a duration equal to demagnetizing interval, switch S2remains closed and switch S2bremains open for a duration equal to Tdem thereby transferring an electric charge Q2to reference capacitor C2and raising Vc2to a voltage referred to herein as the limit proxy voltage, Vlp, given by
Vlp=Q2/C2

The limit proxy voltage Vlp, which represents the product of Tdem and Vcs_m, is indicative of the peak value of Iout and can be compared to a limit reference voltage Vlr, that correlates to Iomax, a specified maximum value of the output current Iout.FIG. 5illustrates limit circuit270with a comparator530including a negative input532coupled to C2and a positive input534coupled to a limit reference voltage, Vlr. Comparator530outputs limit signal271, which indicates whether the limit proxy voltage, Vlp, is greater or less than the limit reference voltage Vlr.

By generating limit proxy voltage Vlp to be indicative of Vcs_m*Tdem, the illustrated limit circuit270is configured to assert limit signal271when Iout exceeds a limit threshold, i.e., exceeds a maximum specified value.

In this manner, the illustrated limit circuit270samples and stores Vcs_m in sampling capacitor C1and then uses this voltage to deliver output current Ivccs to capacitor C2for a duration equal to Tdem. By appropriate selection of capacitor values, reference voltages, and, Gm, the transconductance of VCCS520, limit signal271provides a precise indicator of an over current condition in which Iout exceeding a specified maximum operating value.

FIG. 6illustrates an example of the Ton/2 circuit502inFIG. 5. The Ton/2 circuit502illustrated inFIG. 6receives switching signal251as its input and generates Ton/2 signal504to control switch S1of the limit circuit270illustrated inFIG. 2andFIG. 5. In at least one embodiment, Ton/2 circuit502includes two current sources601and602, two switches611and612, a capacitor C6, a comparator616, and logic620. Logic620is depicted receiving an output618of comparator616and switching signal251as its inputs and generating switch control signal621and Ton/2 signal504as its outputs. The illustrated Ton/2 circuit502uses switch control signal621to control switch611and Ton/2 signal504, which is also provided to switch S1ofFIG. 5as the output of Ton/2 circuit502, to control switch612.

In some embodiments, not depicted inFIG. 6, switching signal251serves as the switch control signal621and, in these embodiments, Ton/2 circuit502may couple switching signal251directly to switch611rather than routing the signal through logic620. In some embodiments, logic620may suppress or disable switch control signal621during alternating switching cycles so that switch611remains open and switch control signal621may be generated by suppressing switching signal251during alternating switching periods. These alternative embodiments are described below with respect toFIG. 7. The following description ofFIG. 6assumes switch control signal621is equivalent to switching signal251unless noted otherwise.

When switch control signal621transitions at the beginning of a Ton phase, switch611closes and current source601provides a DC charging current, I1, to capacitor C6, thereby increasing the capacitor voltage, Vc6, from a zero or non-zero initial voltage, Vinit, at the beginning of the Ton phase, to a charged voltage, Vchg, at the end of Ton, at which point switch611opens, effectively storing Vchg as the capacitor voltage.

Switch612, when closed, couples second current source602to capacitor C6. The second current source602ofFIG. 6is configured to discharge capacitor C6by drawing a discharge current I2from the capacitor. To generate a condition or signal that occurs at Ton/2, the magnitude of discharge current I2may be selected to discharge capacitor C6in half the time required to charge capacitor C6with current source I1. The value of the discharge current I2may depend upon the manner in which the control signal621for switch611is employed.

The Ton/2 circuit502may distinguish between charge cycles, which refer to switching periods during which the C6capacitor voltage Vc6rises from Vinit to Vchg due to charging current I1, and discharge cycles, which refer to switching periods during which Vc6falls from Vchg to Vinit due to discharge current I2. Ton/2 circuit502may alternate charge cycles and discharge cycles wherein each charge cycle is preceded and followed by a discharge cycle and vice versa.

During discharge cycles, Ton/2 circuit502may cause Vc6to decrease from Vchg to Vinit at twice the rate that Vc6increased from Vinit to Vchg during charge cycles so that the c6capacitor voltage Vc6will fall to Vinit at Ton/2. The comparator616illustrated inFIG. 6is configured to signal the moment at which Vc6falls to Vinit during a discharge phase via output signal618.

In some embodiments of Ton/2 circuit502, the switching signal251serves as the switch control signal621that controls switch611. In these embodiments, switch611will be activated at the beginning of each Ton phase of switching signal251, including those Ton phases associated with discharge cycles. In these embodiments, the discharge current I2must not only discharge capacitor C6twice as fast as the charging current I1charged it, the discharge current I2must also negate the charging current I1. Thus, I2must equal 3*I1for embodiments in which the charging current switch611is asserted in each switching cycle.

In some embodiments, logic620may disable switch control signal621during discharge cycles. In these embodiments, the discharge current I2required to cause comparator616to indicate Ton/2 equals 2*I1and the additional logic required to suppress switch control signal621on alternating cycles is exchanged for the smaller I2current source602.

In some embodiments, the Ton/2 signal504, which also controls discharge current switch612, may be disabled during charge cycles so that switch602remains open and all of the charging current I1from current source601contributes to the charging of capacitor C6.

FIG. 7illustrates example logic620that generates switch control signal621and Ton/2 signal504. The logic illustrated inFIG. 7includes a latch704and logical AND gates710and712. The logic620illustrated inFIG. 7receives switching signal251and the output signal618of theFIG. 5comparator616. Comparator output signal618is coupled to a D input of latch704, which is shown receiving switching signal251at a clock input.

The Q output of latch704reflects the value present at input D when switching signal251last transitioned low to high. Because the comparator output signal618indicates whether the voltage Vc6of capacitor C6is greater or less than a reference voltage, comparator output signal618indicates whether the capacitor C6is charged or not.

A logical 1 at output Q of latch704following a transition of switching signal251indicates a discharge cycle while a logical 0 indicates a charge cycle. When the Q output indicates a discharge cycle, AND gate710is enabled and the output of AND gate710, the Ton/2 signal504follows comparator output signal618. When the Q output of latch704indicates a charge cycle, AND gate710is disabled and Ton/2 signal504remains low.

A logical 1 at output Q′ of latch704following a transition of switching signal251indicates a charge cycle while a logical 0 at Q′ indicates a discharge cycle. When the Q′ output indicates a charge cycle, AND gate712is enabled and the output of AND gate712, the switching control signal621ofFIG. 6follows switching signal251.

The logic620described is suitable for embodiments in which switch611ofFIG. 6is disabled during discharge cycles and enabled during charge cycles and in which switch621ofFIG. 6is disabled during charge cycles and enabled during discharge cycles.

FIG. 8illustrates an example Tdem circuit510for generating the Tdem signal512ofFIG. 5. The illustrated Tdem circuit510is implemented with logic that recognizes the falling edge of switching signal251, i.e., the beginning of the Toff phase, as the beginning of Tdem. Tdem circuit510also recognizes either of two triggers or events indicating the end of Tdem. One trigger occurs at the end of the Toff phase, when switching signal251transitions from low to high. This trigger identifies the end of Tdem in CCM operation. Another trigger, associated with DCM operation, occurs when switching signal251exhibits a transitory negative voltage pulse of an appreciable magnitude at an intermediate point in the Toff phase. The transitory pulse occurs when Vds buckling of switching transistor260at the DCM knee point familiar to those of skill in the field of switch mode voltage converters, is capacitively coupled to the switching transistor gate electrode. In some embodiments, a peak voltage of the gate electrode knee point voltage drop is in the range of approximately −100 to −500 mV with a duration in the range of 0.1 to 1 milliseconds. In other embodiments, the peak voltage and the duration may be of greater or lesser magnitude.

The Tdem circuit510illustrated inFIG. 8generates the Tdem signal512with a comparator802that generates a comparator output803, a logical inverter804that generates an inverter output805, an R-S latch808and a logical AND gate810. Logical inverter804inverters switching signal251and provides the inverted switching signal as its output805to an input of AND gate810. The Tdem signal512generated at the output of AND gate810will follow the inverted switching signal unless the Q output of latch808is low. A set input, S, of the depicted latch808is coupled to switching signal251and a reset input, R, is coupled to receive comparator output signal803from comparator802.

Comparator802is configured to receive a negative value reference voltage, −Vref, at its positive input and switching signal251at its negative input. Configured as illustrated inFIG. 8, comparator output803is normally low and is asserted only during the previously described knee point voltage drop of switching signal251, when the switching transistor gate electrode voltage temporarily becomes more negative than −Vref.

Example waveforms illustrate operation of Tdem circuit510. The Q output of latch808is set high at the beginning of each switching cycle by the switching signal251at the latch's S input. The latch's Q output remains high unless comparator output803is asserted at the knee point voltage drop within a DCM switching cycle. Accordingly, the Tdem signal512at the output of AND gate810follows the inverted switching signal at inverter output805unless and until a knee point voltage drop occurs, at which point comparator output signal803pulses high for a brief duration, thereby resetting the Q output of latch808, which will be latched low until the set input S transitions from low to high at the beginning of the subsequent switching cycle. Example waveforms illustrating the behavior of Tdem circuit510are illustrated withinFIG. 8.