STAIRCASE STRUCTURES FOR ACCESSING THREE-DIMENSIONAL MEMORY ARRAYS

Methods, systems, and devices for staircase structures for accessing three-dimensional (3D) memory arrays are described. A memory system may include an access region (e.g., a staircase region) that includes circuitry for accessing memory cells at respective levels of memory cells. The access region may include a channel through which a conductive pillar may couple a word line at a level of memory cells with decoder circuitry. During manufacture of the memory system, a channel material may be formed in the channel and etched to form a corner portion in the channel. During a partitioning of the channel, a nitride material over the corner portion may be etched and some of the corner portion may remain in the channel, which may prevent formation of a trench that may cause the conductive pillar to be uncoupled from the word line.

FIELD OF TECHNOLOGY

The following relates to one or more systems for memory, including staircase structures for accessing three-dimensional (3D) memory arrays.

BACKGROUND

Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component may write (e.g., program, set, assign) one or more memory cells within the memory device to corresponding states.

DETAILED DESCRIPTION

Memory devices may include one or more arrays of memory cells and associated circuitry over a substrate. For example, a memory device may include three-dimensional (3D) arrays of memory cells that are arranged in levels (e.g., layers, decks, tiers) of memory cells. In some examples, the memory device may include access circuitry (e.g., word lines, digit lines) located at various levels, if not each level, of memory cells to support accessing memory cells located at respective levels. To couple the access circuitry with various control circuitry (e.g., configured to bias the access circuitry to various voltages), the memory device may include a staircase region that may include conductive pillars used to couple a word line at a given level with the control circuitry. Reducing the physical area occupied by the staircase region may support the inclusion of additional levels of memory cells in the memory device, and thus may increase memory storage capacity without increasing the physical area (e.g., lateral area) occupied by the memory device.

Various manufacturing operations may be utilized to reduce the occupied area of the staircase channel. For example, the staircase region may include various channels that may each include a conductive pillar extending through the channel and to a respective word line to couple the word line with the control circuitry. To reduce the staircase region area, channels in the staircase region may be bisected such that twice as many conductive pillars may be included in the same amount of space. For example, based on bisecting a channel, a first conductive pillar in the channel may extend to and be coupled with a first word line at a first level of memory cells, and a second conductive pillar in the channel may extend to a second word line at a second level of memory cells. However, when etching the channel to bisect it, a trench may be formed that results in electrical isolation, or physical isolation, or both of one or more of the conductive pillars to a word line at the level of the memory cell where the trench is located (e.g., electrically isolating, or physically isolating, or both the second conductive pillar from the second word line such that the second conductive pillar is uncoupled from the second word line). As such, the word line may not be used to access memory cells, thereby preventing the benefits of the staircase bisection from coming to fruition and resulting in reduced storage capacity and wasted space, for example, due to some memory cells being inaccessible.

In accordance with the examples herein, a memory device may include a deposited barrier material located in a partitioned (e.g., bisected) channel of a staircase region between a conductive pillar and a channel sidewall to prevent unwanted trench formation, among other benefits. For example, to support bisecting the channel, a material (e.g., a material including nitride) may be deposited in the channel with one side of the material (e.g., one half of the nitride, one portion of the nitride) being implanted with another material, such as a material including carbon (e.g., corresponding to one side of the bisected channel). The non-implanted and implanted material (e.g., nitride) may be subsequently etched such that the material (e.g., nitride) may be removed and the side of the channel that was covered by the non-implanted nitride may be etched down, for example, to a next level of memory cells relative to the side of the channel that was covered by the implanted material (e.g., nitride), thereby bisecting the channel. Before the material (e.g., nitride) is deposited, another material such a material included oxide (e.g., among other materials described herein) may be formed in one or more bottom corners of the channel (and may be referred to as a corner material such as a corner oxide) such that trench formation in the corner of the channel may be prevented or at least inhibited. For example, the nitride deposited over the corner oxide may be implanted at a greater rate than the nitride deposited on the sidewalls of the channel, which will result in a greater resistance to being processed, (e.g., etched) during processing of the non-implanted nitride material. Additionally or alternatively, the corner oxide itself will function as an additional barrier to the formation of the trench during bisection of the channel. Thus, the use of the corner oxide will prevent a trench from forming in the corner of the channel when the channel is subsequently bisected. As such, the channel will be bisected while still supporting access to word lines at each level, thereby supporting increased storage capacity of the memory device without increasing the physical area occupied by the memory device (e.g., the staircase region), among other benefits.

Features of the disclosure are initially described in the context of systems, devices, and circuits with reference toFIGS.1and2. Features of the disclosure are described in the context of a layout with reference toFIGS.3A through3F. These and other features of the disclosure are further illustrated by and described with reference to a flowchart that relates to staircase structures for accessing 3D memory arrays as described with reference toFIG.4.

FIG.1illustrates an example of a memory device100that supports staircase structures for accessing 3D memory arrays in accordance with examples as disclosed herein.FIG.1is an illustrative representation of various components and features of the memory device100. As such, the components and features of the memory device100are shown to illustrate functional interrelationships, and not necessarily physical positions within the memory device100. Further, although some elements included inFIG.1are labeled with a numeric indicator, some other corresponding elements are not labeled, even though they are the same or would be understood to be similar, in an effort to increase visibility and clarity of the depicted features.

The memory device100may include one or more memory cells105, such as memory cell105-α and memory cell105-b. In some examples, a memory cell105may be a NAND memory cell, such as in the blow-up diagram of memory cell105-a. Each memory cell105may be programmed to store a logic value representing one or more bits of information. In some examples, a single memory cell105—such as a memory cell105configured as a single-level cell (SLC)—may be programmed to one of two supported states and thus may store one bit of information at a time (e.g., a logic 0 or a logic 1). In some other examples, a single memory cell105—such a memory cell105configured as a multi-level cell (MLC), a tri-level cell (TLC), a quad-level cell (QLC), or other type of multiple-level memory cell105—may be programmed to one of more than two supported states and thus may store more than one bit of information at a time. In some cases, a multiple-level memory cell105(e.g., an MLC memory cell, a TLC memory cell, a QLC memory cell) may be physically different than an SLC cell. For example, a multiple-level memory cell105may use a different cell geometry or may be fabricated using different materials. In some examples, a multiple-level memory cell105may be physically the same or similar to an SLC cell, and other circuitry in a memory block (e.g., a controller, sense amplifiers, drivers) may be configured to operate (e.g., read and program) the memory cell as an SLC cell, or as an MLC cell, or as a TLC cell, etc.

In some NAND memory arrays, each memory cell105may be illustrated as a transistor that includes a charge trapping structure (e.g., a floating gate, a replacement gate, a dielectric material) for storing an amount of charge representative of a logic value. For example, the blow-up inFIG.1illustrates a NAND memory cell105-athat includes a transistor110(e.g., a metal-oxide-semiconductor (MOS) transistor) that may be used to store a logic value. The transistor110may include a control gate115and a charge trapping structure120(e.g., a floating gate, a replacement gate), where the charge trapping structure120may, in some examples, be between two portions of dielectric material125. The transistor110also may include a first node130(e.g., a source or drain) and a second node135(e.g., a drain or source). A logic value may be stored in transistor110by storing (e.g., writing) a quantity of electrons (e.g., an amount of charge) on the charge trapping structure120. An amount of charge to be stored on the charge trapping structure120may depend on the logic value to be stored. The charge stored on the charge trapping structure120may affect the threshold voltage of the transistor110, thereby affecting the amount of current that flows through the transistor110when the transistor110is activated (e.g., when a voltage is applied to the control gate115, when the memory cell105-ais read). In some examples, the charge trapping structure120may be an example of a floating gate or a replacement gate that may be part of a 2D NAND structure. For example, a 2D NAND array may include multiple control gates115and charge trapping structures120arranged around a single channel (e.g., a horizontal channel, a vertical channel, a columnar channel, a pillar channel).

A logic value stored in the transistor110may be sensed (e.g., as part of a read operation) by applying a voltage to the control gate115(e.g., to control node140, via a word line165) to activate the transistor110and measuring (e.g., detecting, sensing) an amount of current that flows through the first node130or the second node135(e.g., via a bit line155). For example, a sense component170may determine whether an SLC memory cell105stores a logic 0 or a logic 1 in a binary manner (e.g., based on a presence or absence of a current through the memory cell105when a read voltage is applied to the control gate115, based on whether the current is above or below a threshold current). For a multiple-level memory cell105, a sense component170may determine a logic value stored in the memory cell105based on various intermediate threshold levels of current when a read voltage is applied to the control gate115, or by applying different read voltages to the control gate and evaluating different resulting levels of current through the transistor110, or various combinations thereof. In one example of a multiple-level architecture, a sense component170may determine the logic value of a TLC memory cell105based on eight different levels of current, or ranges of current, that define the eight potential logic values that could be stored by the TLC memory cell105.

An SLC memory cell105may be written by applying one of two voltages (e.g., a voltage above a threshold or a voltage below a threshold) to memory cell105to store, or not store, an electric charge on the charge trapping structure120and thereby cause the memory cell105store one of two possible logic values. For example, when a first voltage is applied to the control node140(e.g., via a word line165) relative to a bulk node145(e.g., a body node) for the transistor110(e.g., when the control node140is at a higher voltage than the bulk), electrons may tunnel into the charge trapping structure120. Injection of electrons into the charge trapping structure120may be referred to as programming the memory cell105and may occur as part of a write operation. A programmed memory cell may, in some cases, be considered as storing a logic 0. When a second voltage is applied to the control node140(e.g., via the word line165) relative to the bulk node145for the transistor110(e.g., when the control node140is at a lower voltage than the bulk node145), electrons may leave the charge trapping structure120. Removal of electrons from the charge trapping structure120may be referred to as erasing the memory cell105and may occur as part of an erase operation. An erased memory cell may, in some cases, be considered as storing a logic 1. In some cases, memory cells105may be programmed at a page level of granularity due to memory cells105of a page sharing a common word line165, and memory cells105may be erased at a block level of granularity due to memory cells105of a block sharing commonly biased bulk nodes145.

In contrast to writing an SLC memory cell105, writing a multiple-level (e.g., MLC, TLC, or QLC) memory cell105may involve applying different voltages to the memory cell105(e.g., to the control node140or bulk node145thereof) at a finer level of granularity to more finely control the amount of charge stored on the charge trapping structure120, thereby enabling a larger set of logic values to be represented. Thus, multiple-level memory cells105may provide greater density of storage relative to SLC memory cells105but may, in some cases, involve narrower read or write margins or greater complexities for supporting circuitry.

A charge-trapping NAND memory cell105may operate similarly to a floating-gate NAND memory cell105but, instead of or in addition to storing a charge on a charge trapping structure120, a charge-trapping NAND memory cell105may store a charge representing a logic state in a dielectric material between the control gate115and a channel (e.g., a channel between a first node130and a second node135). Thus, a charge-trapping NAND memory cell105may include a charge trapping structure120, or may implement charge trapping functionality in one or more portions of dielectric material125, among other configurations.

In some examples, each page of memory cells105may be connected to a corresponding word line165, and each column of memory cells105may be connected to a corresponding bit line155(e.g., digit line). Thus, one memory cell105may be located at the intersection of a word line165and a bit line155. This intersection may be referred to as an address of a memory cell105. In some cases, word lines165and bit lines155may be substantially perpendicular to one another and may be generically referred to as access lines or select lines.

In some cases, a memory device100may include a 3D memory array, where multiple two-dimensional (2D) memory arrays may be formed on top of one another. In some examples, such an arrangement may increase the quantity of memory cells105that may be fabricated on a single die or substrate as compared with1D arrays, which, in turn, may reduce production costs, or increase the performance of the memory array, or both. In the example ofFIG.1, memory device100includes multiple levels (e.g., decks, layers, planes, tiers) of memory cells105. The levels may, in some examples, be separated by an electrically insulating material. Each level may be aligned or positioned so that memory cells105may be aligned (e.g., exactly aligned, overlapping, or approximately aligned) with one another across each level, forming a memory cell stack175. In some cases, memory cells aligned along a memory cell stack175may be referred to as a string of memory cells105(e.g., as described with reference toFIG.2).

Accessing memory cells105may be controlled through a row decoder160and a column decoder150. For example, the row decoder160may receive a row address from the memory controller180and activate an appropriate word line165based on the received row address. Similarly, the column decoder150may receive a column address from the memory controller180and activate an appropriate bit line155. Thus, by activating one word line165and one bit line155, one memory cell105may be accessed. Upon accessing, a memory cell105may be read (e.g., sensed) by sense component170. For example, the sense component170may be configured to determine the stored logic value of a memory cell105based on a signal generated by accessing the memory cell105. The signal may include a current, a voltage, or both a current and a voltage on the bit line155for the memory cell105and may depend on the logic value stored by the memory cell105. The sense component170may include various circuitry (e.g., transistors, amplifiers) configured to detect and amplify a signal (e.g., a current or voltage) on a bit line155. The logic value of memory cell105as detected by the sense component170may be output via input/output component190. In some cases, a sense component170may be a part of a column decoder150or a row decoder160, or a sense component170may otherwise be connected to or in electronic communication with a column decoder150or a row decoder160.

A memory cell105may be programmed or written by activating the relevant word line165and bit line155to enable a logic value (e.g., representing one or more bits of information) to be stored in the memory cell105. A column decoder150or a row decoder160may accept data (e.g., from the input/output component190) to be written to the memory cells105. In the case of NAND memory, a memory cell105may be written by storing electrons in a charge trapping structure or an insulating layer.

A memory controller180may control the operation (e.g., read, write, re-write, refresh) of memory cells105through the various components (e.g., row decoder160, column decoder150, sense component170). In some cases, one or more of a row decoder160, a column decoder150, and a sense component170may be co-located with a memory controller180. A memory controller180may generate row and column address signals in order to activate a desired word line165and bit line155. In some examples, a memory controller180may generate and control various voltages or currents used during the operation of memory device100.

In some examples, the memory device100may include access circuitry (e.g., word lines165, bit lines155, select lines) located at each level of memory cells105. In order to couple the access circuitry with various control circuitry, the memory device100may include a staircase region (e.g., a channel) that may support accessing the memory cells105. For example, one or more conductive pillars in the staircase region may be utilized to couple the word lines165with the row decoder160.

In accordance with the examples herein, the memory device100may include a deposited barrier material located in a partitioned (e.g., bisected) channel of the staircase region between one or more conductive pillars and staircase sidewalls to support proper function of the memory device100. For example, nitride may be deposited in the staircase channel with one side of the nitride being implanted with carbon. Before the nitride is deposited, the barrier material may be formed in one or more bottom corners of the channel such that the nitride deposited over the corner barrier material (e.g., the corner oxide) may be implanted at a greater rate than the nitride deposited on the sidewalls of the channel. Additionally or alternatively, the corner barrier material itself may function as an additional barrier, for example, to prevent a trench from forming when the channel is subsequently etched and bisected. As such, the channel may be bisected while still supporting access to word lines165at each level. Thus, an increased storage capacity of the memory device100may be supported without increasing the physical area occupied by the staircase region.

FIG.2illustrates an example of a memory architecture200that supports staircase structures for accessing 3D memory arrays in accordance with examples as disclosed herein. The memory architecture200may be an example of a portion of a memory device, such as a memory device100. Although some elements of a set of elements (e.g., an array of elements) are included inFIG.2, some elements may be omitted for the sake of visibility and clarity of the depicted elements. Moreover, although some elements included inFIG.2are labeled with reference numbers, some other corresponding elements are not labeled, though they are the same or would be understood by a person having ordinary skill in the art to be similar. Aspects of the memory architecture200may be described with reference to an x-direction, a y-direction, and a z-direction of the illustrated coordinate system.

In the example of memory architecture200, the block210may be divided into a set of pages215(e.g., a quantity of o pages215) along the z-direction, including a page215-a-1associated with memory cells205-a-111through205-a-mn1. In some examples, each page215may be associated with a same word line265, (e.g., a word line165described with reference toFIG.1), which may be coupled with a control gate115of each of the memory cells205of the page215. For example, page215-a-1may be associated with a word line265-a-1, and other pages215-a-1may be associated with a different respective word line265-a-i(not shown). In some examples, a word line265in accordance with the memory architecture200may be implemented as planar conductor (e.g., in an xy-plane) that is coupled with each of the memory cells205of the page215.

In the example of memory architecture200, the block210also may be divided into a set of strings220(e.g., a quantity of (m×n) strings220) in an xy-plane, including a string220-a-mnassociated with memory cells205-a-mn1through205-a-mno. In some examples, each string220may include a set of memory cells205connected in series (e.g., along the z-direction, in which a drain of one memory cell205in the string220may be coupled with a source of another memory cell205in the string220). In some examples, memory cells205of a string220may be implemented along a common channel, such as a pillar channel (e.g., a columnar channel, a pillar of doped semiconductor) along the z-direction. Each memory cell205in a string220may be associated with a different word line265, such that a quantity of word lines265in the memory architecture200may be equal to the quantity of memory cells205in a string220. Accordingly, a string220may include memory cells205from multiple pages215, and a page215may include memory cells205from multiple strings220.

In some examples, memory cells205may be programmed (e.g., set to a logic 0 value) and read from in accordance with a granularity, such as at the granularity of the page215, but may not be erasable (e.g., reset to a logic 1 value) in accordance with the granularity, such as the granularity of the page215. For example, NAND memory may instead be erasable in accordance with a different (e.g., higher) level of granularity, such as at the level of granularity the block210. In some cases, a memory cell205may be erased before it may be re-programmed. Different memory devices may have different read, write, or erase characteristics.

In some examples, each string220of a block210may be coupled with a respective transistor230(e.g., a string select transistor, a drain select transistor) at one end of the string220(e.g., along the z-direction) and a respective transistor240(e.g., a source select transistor, a ground select transistor) at the other end of the string220. In some examples, a drain of each transistor230may be coupled with a bit line250of a set of bit lines250associated with the block210, where the bit lines250may be examples of bit lines155described with reference toFIG.1. A gate of each transistor230may be coupled with a select line235(e.g., a string select line, a drain select line). Thus, a transistor230may be used to couple a string220with a bit line250based on applying a voltage to the select line235, and thus to the gate of the transistor230. Although illustrated as separate lines along the x-direction, in some examples, select lines235may be common to all the transistors230associated with the block210(e.g., a commonly biased string select node). For example, like the word lines265of the block210, select lines235associated with the block210may, in some examples, be implemented as a planar conductor (e.g., in an xy-plane) that is coupled with each of the transistors230associated with the block210.

In some examples, a source of each transistor240associated with the block210may be coupled with a source line260of a set of source lines260associated with the block210. In some examples, the set of source lines260may be associated with a common source node (e.g., a ground node) corresponding to the block210. A gate of each transistor240may be coupled with a select line245(e.g., a source select line, a ground select line). Thus, a transistor240may be used to couple a string220with a source line260based on applying a voltage to the select line245, and thus to the gate of the transistor240. Although illustrated as separate lines along the x-direction, in some examples, select lines245also may be common to all the transistors240associated with the block210(e.g., a commonly biased ground select node). For example, like the word lines265of the block210, select lines245associated with the block210may, in some examples, be implemented as a planar conductor (e.g., in an xy-plane) that is coupled with each of the transistors240associated with the block210.

To operate the memory architecture200(e.g., to perform a program operation, a read operation, or an erase operation on one or more memory cells205of the block210), various voltages may be applied to one or more select lines235(e.g., to the gate of the transistors230), to one or more bit lines250(e.g., to the drain of one or more transistors230), to one or more word lines265, to one or more select lines245(e.g., to the gate of the transistors240), to one or more source lines260(e.g., to the source of the transistors240), or to a bulk for the memory cells205(not shown) of the block210. In some cases, each memory cell205of a block210may have a common bulk, the voltage of which may be controlled independently of bulks for other blocks210.

In some cases, as part of a read operation for a memory cell205, a positive voltage may be applied to the corresponding bit line250while the corresponding source line260may be grounded or otherwise biased at a voltage lower than the voltage applied to the bit line250. In some examples, voltages may be concurrently applied to the select line235and the select line245that are above the threshold voltages of the transistor230and the transistor240, respectively, for the memory cell205, thereby activating the transistor230and transistor240such that a channel associated with the string220that includes the memory cell205(e.g., a pillar channel) may be electrically connected with (e.g., electrically connected between) the corresponding bit line250and source line260. A channel may be an electrical path through the memory cells205in the string220(e.g., through the sources and drains of the transistors in the memory cells205of the string220) that may conduct current under some operating conditions.

In some examples, multiple word lines265(e.g., in some cases all word lines265) of the block210—except a word line265associated with a page215of the memory cell205to be read—may concurrently be set to a voltage (e.g., VREAD) that is higher than the threshold voltage (VT) of the memory cells205. VREAD may cause all memory cells205in the unselected pages215be activated so that each unselected memory cell205in the string220may maintain high conductivity within the channel. In some examples, the word line265associated with the memory cell205to be read may be set to a voltage, VTarget. Where the memory cells205are operated as SLC memory cells, VTarget may be a voltage that is between (i) VT of a memory cell205in an erased state and (ii) VT of a memory cell205in a programmed state.

When the memory cell205to be read exhibits an erased VT (e.g., VTarget>VT of the memory cell205), the memory cell205may turn “ON” in response to the application of VTarget to the word line265of the selected page215, which may allow a current to flow in the channel of the string220, and thus from the bit line250to the source line260. When the memory cell205to be read exhibits a programmed VT (e.g., VTarget<VT of the selected memory cell), the memory cell205may remain “OFF” despite the application of VTarget to the word line265of the selected page215, and thus may prevent a current from flowing in the channel of the string220, and thus from the bit line250to the source line260.

A signal on the bit line250for the memory cell205(e.g., an amount of current below or above a threshold) may be sensed (e.g., by a sense component170as described with reference toFIG.1) and may indicate whether the memory cell205became conductive or remained non-conductive in response to the application of VTarget to the word line265of the selected page215. The sensed signal thus may be indicative of whether the memory cell205was in an erased state (e.g., storing a logic 1) or a programmed state (e.g., storing a logic Though aspects of the example read operation above have been explained in the context of an SLC memory cell205for clarity, such techniques may be extended or altered and applied in the context of a multiple-level memory cell205(e.g., through the use of multiple values of VTarget corresponding to the different amounts of charge that may be stored in one multiple-level memory cell205).

In some cases, as part of a program operation for a memory cell205, charge may be added to a portion of the memory cell205such that current flow through the memory cell205, and thus the corresponding string220, may be inhibited when the memory cell205is later read. For example, charge may be injected into a charge trapping structure120as shown in memory cell105-aofFIG.1. In some cases, respective voltages may be applied to the word line265of the page215and the bulk of the memory cell205to be programmed such that a control gate115of the memory cell205is at a higher voltage than the bulk of the memory cell205(e.g., a positive voltage may be applied to the word line). Concurrently, voltages may be applied to the select line235and the select line245that are above the threshold voltages of the transistor230and the transistor240, respectively, thereby activating the transistor230and the transistor240, and the bit line250for the memory cell205to be programmed may be set to a relatively high voltage. This may cause an electric field such that electrons are pulled from the source of the memory cell205towards the drain. The electric field may also cause some of these electrons to be pulled through dielectric material125and thereby injected into the charge trapping structure120of the memory cell205, through a process which may in some cases be referred to as tunnel injection.

In some cases, a single program operation may program some or all memory cells205in a page215, as the memory cells205of the page215may all share a common word line265and a common bulk. For a memory cell205of the page215for which it is not desired to write a logic 0 (e.g., not desired to program the memory cell205), the corresponding bit line250may be set to a relatively low voltage (e.g., ground), which may inhibit the injection of electrons into a charge trapping structure120. Though aspects of the example program operation above have been explained in the context of an SLC memory cell205for clarity, such techniques may be extended and applied to the context of a multiple-level memory cell205(e.g., through the use of multiple programming voltages applied to the word line265, or multiple passes or pulses of a programming voltage applied to the word line265, corresponding to the different amounts of charge that may be stored in one multiple-level memory cell205).

In some cases, as part of an erase operation for a memory cell205, charge may be removed from a portion of the memory cell205such that current flow through the memory cell205, and thus the corresponding string220, may be uninhibited (e.g., allowed, at least to a greater extent) when the memory cell205is later read. For example, charge may be removed from a charge trapping structure120as shown in memory cell105-aofFIG.1. In some cases, respective voltages may be applied to the word line265of the page215and the bulk of the memory cell205to be erased such that a control gate115of the memory cell205is at a lower voltage than the bulk of the memory cell205(e.g., a positive voltage may be applied to the bulk), which may cause an electric field that pulls electrons out of the charge trapping structure120and into the bulk of the memory cell205. In some cases, a single program operation may erase all memory cells205in a block210, as the memory cells205of the block210may all share a common bulk.

In some cases, electron injection and removal processes associated with program and erase operations may cause stress on a memory cell205(e.g., on the dielectric material125). Over time, such stress may in some cases cause one or more aspects of the memory cell205(e.g., the dielectric material125) to deteriorate. For example, charge trapping structure120may become unable to maintain a stored charge. Such deterioration may be an example of a wearout mechanism for a memory cell205, and for this or other reasons, some memory cells205may support a finite quantity of program and erase cycles.

In accordance with the examples herein, a memory device that includes the memory architecture200may include a deposited barrier material located in a partitioned channel of a staircase region between one or more of conductive pillars and channel sidewalls to support proper memory device function. For example, the memory device may include access circuitry (e.g., word lines265, bit lines250, select lines235, select lines245, source lines260) located at the levels of memory cells205. In order to couple the access circuitry with various control circuitry (e.g., decoder circuitry, such as a row decoder160, a column decoder150, a sense component170described with reference toFIG.1), the memory device may include a staircase region (e.g., a channel) that may include one or more conductive pillars used to couple the access circuitry (e.g., a word line265) at a given level with the control circuitry. To support partitioning the channel, nitride may be deposited in the channel with one side of the nitride being implanted with carbon. Before the nitride is deposited, the barrier material may be deposited in one or more bottom corners of the channel such that trench formation in the corner of the channel may be prevented. For example, the nitride deposited over the barrier material in the bottom corner may be implanted at a greater rate than the nitride deposited on the sidewalls of the channel, which may result in a greater resistance to being etched during an etch of non-implanted nitride material. Additionally or alternatively, the corner oxide itself may function as an additional barrier to the formation of the trench during bisection of the channel. Thus, the use of this corner oxide may prevent a trench from forming when the channel is subsequently etched and partitioned. As such, the staircase channel may be bisected while still supporting access to word lines265at each level. Thus, an increased storage capacity of the memory device may be supported without increasing the physical area occupied by the staircase channel.

FIGS.3A through3Fillustrate examples of operations that support a staircase structures for accessing 3D memory arrays in accordance with examples as disclosed herein. For example,FIGS.3A through3Fmay illustrate aspects of a sequence of manufacturing operations for fabricating aspects of a layout300, which may be a portion of a memory device (e.g., a portion of a memory device100, a portion of a memory architecture200). Each view of theFIGS.3A through3Fmay be described with reference to an x-direction, a y-direction, and a z-direction, as illustrated. The manufacturing operations illustrate various cross-sectional views of the layout300. For example, the manufacturing operations illustrate cross-sectional views of the layout300in an xz-plane through the layout300. Although the layout300illustrates examples of certain relative dimensions and quantities of various features, aspects of the layout300may be implemented with other relative dimensions or quantities of such features in accordance with examples as disclosed herein.

Operations illustrated in and described with reference toFIGS.3A through3Fmay be performed by a manufacturing system, such as a semiconductor fabrication system configured to perform additive operations such as deposition or bonding, subtractive operations such as etching, trenching, planarizing, or polishing, and supporting operations such as masking, patterning, photolithography, or aligning, among other operations that support the described techniques. In some examples, operations performed by such a manufacturing system may be supported by a process controller or its components as described herein.

Additionally, it is noted that the aspects of the manufacturing operations are described with reference to bisecting a channel of a staircase region, for clarity. However, the techniques described herein may be adapted and applied to support other partitioning of the channel, such as trisecting the channel, quadrisecting the channel, and so on.

FIG.3Aillustrates a portion of a layout300-aafter a first set of one or more manufacturing operations. The first set of manufacturing operations may include forming various structures and materials over a substrate305. The substrate305may be a semiconductor wafer or other substrate over which a stack of layers310is formed (e.g., deposited). The stack of layers310may include alternating layers of a first material and a second material. For example, the first material in the stack of layers310may be a sacrificial material320and the second material in the stack of layers310may be a dielectric material315. In some examples, the sacrificial material320may be a nitride material and may be subsequently removed (e.g., etched) and replaced by a conductive material to form word lines (e.g., word lines165, word lines265). The quantity of layers depicted in the stack of layers310may be solely for illustrative purposes. For example, the stack of layers310may include any quantity of layers of the dielectric material315and the sacrificial material320, including more or less layers than those illustrated.

Various other layers of materials may be formed over (e.g., on, above) the stack of layers310(e.g., in the z-direction, which is orthogonal to the substrate305). For example, a top dielectric material325may be formed over the stack of layers310. In some examples, the top dielectric material325may be excluded from the layout300.

The stack of layers310may form the basis for a staircase region that includes access circuitry for accessing memory cells at respective levels of memory cells included in the memory device. In some examples, to support the formation and coupling of such access circuitry, the first set of manufacturing operations may include removing (e.g., etching) a portion of the stack of layers310in the z-direction to create (e.g., form) a channel330. For example, the channel330may be formed in the stack of layers310by etching portions of layers of the dielectric material315and the sacrificial material320. In some other examples, the channel330may be formed as the layers of the stack of layers310are formed (e.g., deposited), for example, by using a mask as additional layers over a base layer that is the bottom of the channel330(e.g., a sacrificial material320-a) are deposited.

In some examples, a bottom of the channel330may include (e.g., correspond to, be) a top surface of a portion of a layer of the dielectric material315. For example, the bottom of the channel330may be a top surface of a portion (e.g., an exposed portion) of a sacrificial material320-a. Additionally, the sides (e.g., sidewalls350) of the channel330may include (e.g., correspond to, be) the alternating layers of the dielectric material315and the sacrificial material320that are over the base layer (e.g., the sacrificial material320-a) in the z-direction. For example, the sidewalls350of the channel330may be the exposed sidewalls of the alternating layers of the dielectric material315and the sacrificial material320that are over the sacrificial material320-a. In some examples, the junctions between the bottom of the channel330and the sidewalls350may be referred to as corners (e.g., bottom corners) of the channel330. For example, the channel330may include a first bottom corner at the junction of a first sidewall350and the sacrificial material320-aand a second bottom corner at the junction of a second sidewall350and the sacrificial material320-a. The first set of manufacturing operations may further include forming (e.g., depositing) a material in the channel330(e.g., and over the stack of layers310, over the top dielectric material325). For example, a channel material335may be deposited in the channel330such that a film is deposited over the bottom and sidewalls350of the channel330and the top dielectric material325on top of the stack of layers310(e.g., or a top layer of the stack of layers310in the z-direction). In some examples, the channel material335may be in contact with the surfaces of the channel330(e.g., the bottom and sidewalls350of the channel330) and the top dielectric material325. In some examples, an intermediate layer (not shown) may be deposited such that it is located between the channel material335and the surfaces of the channel330and top dielectric material325.

In some examples, the thickness of the deposited channel material335between the surface of the deposited channel material335and the surface of the junction between the bottom and sidewalls350of the channel330(e.g., a distance340-b) may be greater than that of the thickness of the deposited channel material335between the surface of the channel material335and the bottom of the channel (e.g., a distance340-a) and greater than the thickness of the channel material335between the surface of the channel material335and the sidewall of the channel (e.g., a distance340-c). That is, the distance340-bmay be greater than the distance340-a, and the distance340-bmay be greater than the distance340-c. This variation in thickness of the channel material335may enable a portion of the channel material335to remain in the channel330after subsequent etches (e.g., as described with reference toFIG.3B). In some examples, the variation in thickness of the channel material335(e.g., the greater quantity of channel material335being deposited in the corners of the channel330) may be a natural result of an isotropic deposition of the channel material335in the channel330based on the geometry of the channel330. That is, additional material deposited as part of an isotropic deposition operation may be deposited in corners of a geometrical space relative to other surfaces of the geometrical space.

In some examples, the channel material335may be an oxide material or another non-conductive spacer material. For example, the channel material335may be an oxide material such as silicon oxide, aluminum oxide, or a doped oxide (e.g., phosphorus-doped oxide, boron-doped oxide), among other types of oxide materials. Alternatively, the channel material335may be another non-conductive spacer material such as silicon nitride, or a non-conductive material having a high dielectric constant. In some examples, the channel material335may be associated with a relatively high etch rate (e.g., may be etched relatively quickly). In some examples, the channel material335may be a relatively inexpensive oxide material or non-conductive spacer material, for example, to mitigate costs associated with forming and etching the channel material335.

Although the structures and materials are illustrated as being deposited in direct contact with the substrate305, in some other examples, the layout300-amay include other materials or components between the structures and materials and the substrate305, such as interconnection or routing circuitry (e.g., access lines), control circuitry (e.g., transistors, aspects of a local memory controller, decoders, multiplexers), or other structures and materials (e.g., other structures and materials that have been processed in accordance with examples as disclosed herein), which may include various conductor, semiconductor, or dielectric materials between the structures and materials and the substrate305. Additionally or alternatively, the layout300-amay include a layer of intermediate material between the substrate305and the structures and materials, between the channel material335and the bottom of the channel330, between the channel material335and the sidewalls350of the channel330, or a combination thereof, among other locations where the intermediate material may be formed.

FIG.3Billustrates a portion of a layout300-bafter a second set of one or more manufacturing operations. The second set of manufacturing operations may include further operations (e.g., wet etch operations, isotropic etch operations) that support staircase structures for accessing 3D memory arrays in accordance with examples as disclosed herein. For example, the second set of manufacturing operations may include removing (e.g., etching, such as via an isotropic wet etch) the channel material335from various portions of the channel330, the top dielectric material325, and other structures to form sub-structures. For example, the second set of manufacturing operations may include an etch of the channel material335to form a set of sub-portions of the channel material335. These sub-portions may be referred to as corner oxides345(e.g., a corner oxide345-a, a corner oxide345-b), for clarity, however, it is understood that the sub-portions of the channel material335may be a material other than an oxide material as described with reference toFIG.3A.

Etching the channel material335after its deposition may result in portions of the channel material335remaining in the bottom corners of the channel330(e.g., corner oxide345-a, corner oxide345-b). For example, the corner oxide345-amay remain in the first bottom corner of the channel330and may be located over a portion of the sacrificial material320-a. Similarly, the corner oxide345-bmay be located in the second bottom corner of the channel330, which may be located opposite to the corner oxide345-a(e.g., in the x-direction, which may be parallel to the substrate305).

In some examples, the corner oxides345-aand345-bmay also be adjacent to or in contact with one or more layers of the sidewalls350based on the extent to which the channel material335is etched. For example, in the example ofFIG.3B, the corner oxides345may be in contact with a dielectric material315-aand a sacrificial material320-b, although the corner oxides345may be in contact with (e.g., or adjacent to) any quantity of the layers of the sidewalls350. In some examples, the corner oxides345may be adjacent to one or more layers of the sidewalls350but separated from the layers by one or more intermediate layers. In some examples, the corner oxide345-aand the corner oxide345-bmay remain due to the greater amount of channel material335located in the bottom corners of the channel330relative to the amount of channel material335located along the sidewalls350of the channel330and the bottom of the channel330, as described with reference toFIG.3A. For example, the channel material335may be isotopically etched at a relatively constant rate. Accordingly, because the distance340-bis greater than the distances340-aand340-c, at least some of channel material335may remain in the bottom corners of the channel330while being removed from elsewhere. Additionally, by varying the thickness of the deposited channel material335and the etch of the channel material335(e.g., a duration of the etch), a size of the corner oxides345may be varied and controlled.

In some examples, the second set of manufacturing operations may include exposing some portions of the surfaces of the channel330and top of the stack of layers310after etching. For example, a portion of the bottom of the channel330may be exposed between the corner oxides345-aand345-bbased on the etching of the channel material335. As such, the layers of the exposed portions of the bottom of the channel may include the sacrificial material320-a. In some examples, if an intermediate material separates the corner oxides345from the sacrificial material320-a, then a portion of the intermediate material located between the corner oxides345may be exposed. Additionally, the sidewalls350on either side of the channel330may be exposed above the corner oxides345-aand345-b. As such, some layers of the dielectric material315and some layers of the sacrificial material320of the stack of layers310over the corner oxides345in the z-direction may be exposed after the channel material335is etched. In some examples, if an intermediate material separates the corner oxides345from the sidewalls350, then a portion of the intermediate material located over the corner oxides345in the z-direction and along the sidewalls350may be exposed. In some examples, the top dielectric material325(e.g., or a top layer of the stack of layers310in the z-direction) may also be exposed based on the etching.

FIG.3Cillustrates a portion of a layout300-cafter a third set of one or more manufacturing operations. The third set of manufacturing operations may include further operations (e.g., deposition operations, implantation operations) that support staircase structures for accessing 3D memory arrays in accordance with examples as disclosed herein. For example, the third set of manufacturing operations may include the formation (e.g., deposition) of a nitride material354in the channel330and over the top dielectric material325and the formation of a mask352. The third set of manufacturing operations may further include the implantation of a portion of the nitride material354with a doping material358.

For example, the third set of manufacturing operations may include depositing a nitride material354(e.g., silicon nitride, among other nitride materials) in the channel330and over related aspects of such. In some examples, such as in the example ofFIG.3C, the nitride material354may be deposited in the channel330and may be deposited over and in contact with the corner oxide345-a, the corner oxide345-b, the exposed bottom of the channel330, the exposed sidewalls of the channel330, or a combination thereof. In such examples, the portion of the nitride material354deposited over the exposed bottom of the channel330(e.g., over the exposed top surface of the sacrificial material320-a) may be located between the corner oxide345-aand the corner oxide345-b. In some other examples, the nitride material354may be separated from the corner oxide345-a, the corner oxide345-b, the bottom of the channel330, the sidewalls of the channel330, or a combination thereof, by one or more intermediate materials (not shown). The nitride material354may also be deposited over the top dielectric material325(e.g., or over the top layer of the stack layers310in the z-direction). In some examples, the material354may be a material other than a nitride material. For example, the material354may be a polysilicon material or an oxide material instead of a material that includes nitride.

In some examples, the third set of manufacturing operations may include subsequently forming (e.g., depositing) a mask352over a portion of the deposited nitride material354. For example, the mask352may be formed on the nitride material354such that a first portion of the nitride material354may be shielded from further operations, such as implantation operation, etch operations, or deposition operations, among others, while mask352shields the portion of the nitride material354.

In some examples, the third set of manufacturing operations may include implanting (e.g., doping) a second portion of the nitride material354with a doping material358, such as carbon. For example, the third set of manufacturing operations may include an implant operation (e.g., doping operation) along the z-direction (e.g., negative z-direction) such that the nitride material354unblocked by the mask352in the z-direction (e.g., the second portion of the nitride material354) may be implanted with the doping material358to form an implanted (e.g., doped) nitride material356(e.g., an implanted polysilicon material, an implanted oxide material based on the material354). That is, the implanted nitride material356may be formed by implanting the second portion of the nitride material354with the doping material358(e.g., carbon). As a result of the implant operation, the nitride material354located over the corner oxide345-amay be implanted, while the nitride material354located over the corner oxide345-bmay remain non-implanted.

In some examples, a distribution of the doping material358may vary throughout the implanted nitride material356. For example, different portions of the implanted nitride material356may include (e.g., be implanted with) different quantities of the doping material358. For instance, the implanted nitride material356located over the exposed surface of the bottom of the channel330may be implanted with a first quantity of the doping material358that is greater than a second quantity of the doping material358with which the implanted nitride material356located over the corner oxides345-aand345-bis implanted. Similarly, the second quantity of the doping material358may be greater than a third quantity of the doping material358with which the implanted nitride material356located over the first sidewall350.

These differences in distribution may occur due to the different angles of the nitride-covered surfaces relative to a direction of the implanting with the doping material358. For example, the effectiveness of the implant operation (e.g., the quantity of doping material358that is implanted) may increase as the direction of the implanting approaches orthogonality (e.g., 90°) with a surface of a given material. Similarly, the effectiveness of the implant operation may decrease as the direction of the implanting approaches parallelism (e.g., 0°, 180°). As a result, the first quantity of doping material358may be greater than the second quantity of doping material358, and the second quantity of doping material358may be greater than the third quantity of doping material358. For example, a first angle of the implanted nitride material356located over the exposed surface of the bottom of the channel330relative to the direction of the implanting may be approximately orthogonal. A second angle of the implanted nitride material356located over the first sidewall350relative to the direction of the implanting may approach parallelism (e.g., 0°) and may thus be less than the first angle. A third angle of the implanted nitride material356located over the corner oxide345-arelative to the direction of the implanting may be between the first angle and the second angle (e.g., less than the first angle and greater than the second angle). Accordingly, the effectiveness of the implantation may be greatest for the implanted nitride material356located over the exposed surface of the bottom of the channel330, then the implanted nitride material356located over the corner oxide345-a, and then the implanted nitride material356located over the first sidewall350.

In some examples, the third angle of the first sidewall may be steep enough relative to the angle of implantation (e.g., approach 0°) to render the implantation of the nitride material354on the first sidewall350relatively ineffective. In such cases, the implanted nitride material356located on the first sidewall350may have similar characteristics to that of the non-implanted nitride material354.

FIG.3Dillustrates a portion of a layout300-dafter a fourth set of one or more manufacturing operations. The fourth set of manufacturing operations may include further operations (e.g., etch operations) that support staircase structures for accessing 3D memory arrays in accordance with examples as disclosed herein. For example, the fourth set of manufacturing operations may include the removal (e.g., etching) of the non-implanted nitride material354and a portion of the implanted nitride material356to form the implanted nitride material360-aand360-b.

For instance, the remaining non-implanted nitride material354may be etched, along with the portion of the implanted nitride material356which has characteristics similar to those of the non-implanted nitride material354(e.g., the implanted nitride material356over the first sidewall350of the channel330), for example, based on the third quantity of doping material358with which this portion of implanted nitride material356is implanted failing to satisfy (e.g., being less than, less than or equal to) a threshold quantity of doping material358.

In some examples, this etching operation may result in the exposure of the sidewalls350of the channel330, the exposure of a portion of the bottom of the channel330, the exposure of the corner oxide345-b, the exposure of a portion of the top dielectric material325on top of the stack of layers310, or a combination thereof. In some examples, these exposures may result in portions of the implanted nitride material356remaining (e.g., implanted nitride material360-aand360-b). As such, the implanted nitride material360-amay remain over the corner oxide345-aand a portion of the bottom of the channel330, and the implanted nitride material360-bmay remain on top of the top dielectric material325.

In some examples, the implanted nitride material360-amay remain over the corner oxide345-abased on the second quantity of doping material358with which this portion of implanted nitride material360-ais implanted satisfying (e.g., being greater than, being greater than or equal to) a threshold quantity of doping material358. That is, the implanted nitride material356over the corner oxide345-amay be implanted such that it may resist the etching of the non-implanted nitride material354. In some other examples, a portion of the implanted nitride material356over the corner oxide345-amay be etched based on the second quantity of doping material358with which this portion of implanted nitride material360-ais implanted failing to satisfy the threshold quantity of doping material358. However here, the corner oxide345-amay remain in the channel330after the etch. Thus, in either example, the first bottom corner of the channel330(e.g., the junction between the) may remain unexposed after the etch of the non-implanted nitride material354).

FIG.3Eillustrates a portion of a layout300-eafter a fifth set of one or more manufacturing operations. The fifth set of manufacturing operations may include further operations (e.g., etch operations, deposition operations) that support staircase structures for accessing 3D memory arrays in accordance with examples as disclosed herein. For example, the fifth set of manufacturing operations may include the removal (e.g., etching) of the implanted nitride material360-aand360-b, as well as specific portions of layers of the stack of layers310. The fifth set of manufacturing operations may also include the formation (e.g., deposition) of a fill material365.

For example, the implanted nitride materials360-aand360-bmay be etched such that at least a portion of the corner oxide345-aremains in the channel330(and the implanted nitride material360-bis removed from the top of the stack of layers310), thus exposing a portion of the sacrificial material320-aover which the implanted nitride material360-awas located. In some examples, a portion of the bottom of the channel330may also be etched such that the channel330may be partitioned (e.g., bisected). For example, as part of the etch operation to remove the implanted nitride materials360, the corner oxide345-band portions of the sacrificial material320-aand a dielectric material315-bover which the sacrificial material320-ais located may be etched such that a portion of a sacrificial material320-cmay be exposed, as illustrated. For instance, a portion of the sacrificial material320-athat is uncovered by the implanted nitride material360as well as a portion of the dielectric material315-bunderneath the uncovered portion of the sacrificial material320-ain the z-direction may be etched. As such, a step may be formed in the side of the channel330uncovered by the implanted nitride material360-a, where the step is from the sacrificial material320-cto the sacrificial material320-a. The corner oxide345-bmay be etched based on having been exposed with the etch of the non-implanted nitride material354.

During the etch operation to bisect the channel330, a trench in the first bottom corner of the channel330may be prevented from forming based on the corner oxide345-a. For example, without the presence of the corner oxide345-a, an implantation of nitride material354located in the first bottom corner may be relatively ineffective, for example, due to an angle of the nitride material354relative to the direction of implantation being relatively low. As a result, the implanted nitride material356located in the first bottom corner may be etched, thereby exposing the sacrificial material320-ain the first bottom corner. Here, the sacrificial material320-a(e.g., and the dielectric material315-b) located in the first bottom corner may be etched during bisection of the channel330based on being uncovered by the implanted nitride material360-a(e.g., and/or a corner oxide345) such that the trench (e.g., a cavity to the dielectric material315-bor sacrificial material320-cin the first bottom corner) may be formed. During the deposition of the fill material365, the trench may be filled with the fill material365. The corner oxide345-a, however, may enable implantation of the nitride material354in the first bottom corner such that the trench is not formed during bisection of the channel330. Further, even if a portion of the corner oxide345-ais exposed as a result of etching the non-implanted nitride material354, the corner oxide345-aand the implanted nitride material360-athat does cover a portion of corner oxide345-amay provide sufficient protection to prevent formation of the trench.

In some examples, the fifth set of manufacturing operations may include subsequently filling the channel330with another material. For example, after the etch operation (e.g., bisection of the channel330), the channel330(e.g., including the step) may be filled with a fill material365. As such, the fill material365may cover the remaining corner oxide345-a, along with the exposed surfaces of the sacrificial material320, sidewalls350of the channel330, and all other aspects of the channel330. In some examples, the fill material365may be in contact with at least a portion of the corner oxide345-a. In some other cases, an intermediate material may be between the fill material365and the corner oxide345-ato separate them. The fill material365may be an example of an oxide material different than that of the channel material335as described with reference toFIG.3Aand others. In some examples, the fill material365may be associated with an etch rate, density, or a combination thereof that is different than the etch rate, density, or a combination thereof, of the channel material335.

FIG.3Fillustrates a portion of a layout300-fafter a sixth set of one or more manufacturing operations. The sixth set of manufacturing operations may include further operations (e.g., etch operations, deposition operations) that support staircase structures for accessing 3D memory arrays in accordance with examples as disclosed herein. For example, the sixth set of manufacturing operations may include the removal (e.g., etching) of portions of the fill material365and the sacrificial material320. The sixth set of manufacturing operations may also include the formation (e.g., deposition) of a conductive contacts378, a conductive pillars380, and a word lines382.

In some examples, the sixth set of manufacturing operations may include removing (e.g., etching) the sacrificial material320. For example, the layers of the sacrificial material320may be removed, and the regions once filled with (e.g., locations of the removed) sacrificial material320may be filled with one or more conductive (e.g., metal) materials to form respective word lines382. For example, the sacrificial material320-aand the sacrificial material320-cmay be removed, and a word line382-aand a word line382-bmay be formed at the location of the sacrificial material320-aand the sacrificial material320-c, respectively.

The word lines382may extend into a memory region370over the substrate305of the layout300and may be used to access memory cells at respective levels of memory cells376. For example, the memory region370may include alternating layers of dielectric material315and levels of memory cells376. Aspects of the memory region370may be formed in conjunction with the various sets of manufacturing operations (e.g., the first through sixth set of manufacturing operations). In the example ofFIG.3F, the word line382-amay extend into a level of memory cells376-aand may be used to access one or more memory cells of the level of memory cells376-athat are coupled with the word line382-a. Additionally, the word line382-bmay extend into a level of memory cells376-band may be used to access one or more memory cells of the level of memory cells376-bthat are coupled with the word line382-b.

In some examples, the fill material365may be in contact with word line382-aand word line382-b. In some other examples, the word line382-aand the word line382-bmay each be separated from the fill material365by an intermediate material (not shown).

The sixth set of manufacturing operations may further include etching portions of the fill material365in the z-direction to form a first cavity (illustrated as filled with a conductive pillar380-aand a conductive contact378-a) and a second cavity (illustrated as filled with a conductive pillar380-band a conductive contact378-b). The first cavity may extend from the top surface of the fill material365to the word line382-a, and the second cavity may extend from the top surface of the fill material365to the word line382-b. In some examples, some or all of the corner oxide345-amay be etched as part of etching the first cavity. In some examples, the corner oxide345-amay be unetched by the etching of the first cavity.

The sixth set of manufacturing operations may include forming conductive contacts378(e.g., metal contacts) and conductive pillars380in the etched cavities. For example, the conductive contact378-amay be formed (e.g., deposited) in the base of the first cavity and a conductive material (e.g., metal) may be formed over the conductive contact378-ain the first cavity to form the conductive pillar380-a. The conductive contact378-band the conductive pillar380-bmay be similarly formed in the second cavity (e.g., as part of the same deposition processes to form the conductive contact378-aand the conductive pillar380-a, respectively).

The conductive contacts378may be in contact with (e.g., coupled with) the corresponding word lines382and conductive pillars380. For example, the conductive contacts378may be in contact with a portion of the conductive pillars380and a top surface of the word lines382. The conductive contacts378may also be in contact with the fill material365.

In some examples, the corner oxide345-amay be in contact with the conductive contact378-a, the conductive pillar380-a, the word line382-a, or a combination thereof. For example, based on the etch of the first cavity, a portion of the corner oxide345-amay be exposed. As a result, the conductive contact378-a, the conductive pillar380-a, or both, may be in contact with the exposed portion of the corner oxide345-aafter being deposited. In some other examples, the first cavity may be etched such that the corner oxide345-ais unetched and unexposed (e.g., covered by the fill material365. Here, the conductive contact378-a, the conductive pillar380-a, or both, may be adjacent to the corner oxide345-a(e.g., in the x-direction) but separated from the corner oxide345-aby a portion of the fill material365. In some examples, the word line382-amay be formed such that the corner oxide345-ais in contact with the top surface of the word line382-a. In some examples, an intermediate material may separate the corner oxide345-afrom the top surface of the word line382-a. In the example ofFIG.3F, the corner oxide345-amay be in contact with the word line382-aand a portion of the conductive contact378-abut may be separated from the conductive pillar380-aby a portion of the fill material365.

The layout300may support accessing the levels of memory cells376based on forming the conductive contacts378and conductive pillars380. For example, the layout300may include a channel region372and an access region374. The access region374may correspond to a staircase region of the layout300. That is, the access region374may be a region of the layout300where access circuitry (e.g., word lines382) and circuitry to couple the access circuitry with decoder circuitry may be located. The channel region372may correspond to a region of the access region374that includes the materials and components formed in the channel330(e.g., the fill material365, the corner oxide345-a, the conductive contacts378, and the conductive pillars380). Each level of memory cells376may be coupled with a word line382in the access region374, which may be coupled with the conductive contacts378and the conductive pillars380in the channel region372to support accessing a given level of memory cells376. For example, voltages applied to the word line382-aby decoding circuitry (e.g., a row decoder160) via the conductive contact378-aand the conductive pillar380-amay result in accessing memory cells of the level of memory cells376-aof the memory region370.

In some examples, the use of the corner oxide345-amay prevent trench formation from occurring during bisection of the channel330as described with reference toFIG.3D. Formation of such a trench may result in electric isolation of the word line382-afrom the conductive contact378-a(e.g., and conductive pillar380-a) such that the word line382-amay not be coupled with the decoding circuitry, and thus may be rendered useless in accessing the memory region370. For example, because the fill material365may fill the trench when deposited after bisecting the channel330, the sacrificial material320-alocated in the channel330may be blocked by the fill material365in the trench from being removed and replaced by the word line382-a. Thus, the conductive contact378-adeposited in the first cavity may be uncoupled from (e.g., physically and/or electrically isolated from) the word line382-a. However, utilizing the corner oxide345-amay prevent the trench from forming by acting as a physical buffer (e.g., margin) and/or enabling increased implantation of the nitride material354located over the first bottom corner, and thus may prevent the electrical isolation of the word line382-a. Thus, proper functionality of the word line382-ain regards to accessing the memory cell376-aof the memory region370may be supported in addition to the bisection of the channel330.

FIG.4shows a flowchart illustrating a method400that staircase structures for accessing 3D memory arrays in accordance with examples as disclosed herein. The operations of method400may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally, or alternatively, one or more controllers may perform aspects of the described functions using special-purpose hardware.

At405, the method may include forming an oxide material in a channel of a stack of layers that includes alternating layers of a first material and a second material, where a bottom of the channel includes a top surface of a layer of the first material and sidewalls of the channel include the alternating layers located over the layer of the first material. The operations of405may be performed in accordance with examples as disclosed herein.

At410, the method may include etching a first portion of the oxide material, where a first portion of the top surface of the layer of the first material is exposed and a second portion of the oxide material remains over a second portion of the top surface of the layer of the first material based at least in part on etching the first portion of the oxide material. The operations of410may be performed in accordance with examples as disclosed herein.

At415, the method may include forming a nitride material in the channel over the sidewalls of the channel, the first portion of the top surface of the layer of the first material, and the second portion of the oxide material. The operations of415may be performed in accordance with examples as disclosed herein.

At420, the method may include implanting a portion of the nitride material with carbon. The operations of420may be performed in accordance with examples as disclosed herein.

At425, the method may include etching a non-implanted portion of the nitride material. The operations of425may be performed in accordance with examples as disclosed herein.

At430, the method may include etching the implanted portion of the nitride material, where at least a portion of the second portion of the oxide material remains in the channel after etching the implanted portion of the nitride material. The operations of430may be performed in accordance with examples as disclosed herein.

At435, the method may include forming a third material in the channel over the remaining second portion of the oxide material. The operations of435may be performed in accordance with examples as disclosed herein.

In some examples, an apparatus (e.g., a manufacturing system) as described herein may perform a method or methods, such as the method400. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof for performing the following aspects of the present disclosure:Aspect 1: A method or apparatus including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming an oxide material in a channel of a stack of layers that includes alternating layers of a first material and a second material, where a bottom of the channel includes a top surface of a layer of the first material and sidewalls of the channel include the alternating layers located over the layer of the first material; etching a first portion of the oxide material, where a first portion of the top surface of the layer of the first material is exposed and a second portion of the oxide material remains over a second portion of the top surface of the layer of the first material based at least in part on etching the first portion of the oxide material; forming a nitride material in the channel over the sidewalls of the channel, the first portion of the top surface of the layer of the first material, and the second portion of the oxide material; implanting a portion of the nitride material with carbon; etching a non-implanted portion of the nitride material; etching the implanted portion of the nitride material, where at least a portion of the second portion of the oxide material remains in the channel after etching the implanted portion of the nitride material; and forming a third material in the channel over the remaining second portion of the oxide material.Aspect 2: The method or apparatus of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for removing the layer of the first material and forming, at a location of the removed layer of the first material, a word line associated with accessing one or more memory cells, where the remaining second portion of the oxide material is in contact with a top surface of the word line.Aspect 3: The method or apparatus of aspect 2, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for etching a cavity through the third material to the word line and forming, in the cavity, a contact and a conductive pillar coupled with the word line, the contact and the conductive pillar for coupling the word line with decoder circuitry, where the remaining second portion of the oxide material is in contact with the contact, or the conductive pillar, or both.Aspect 4: The method or apparatus of any of aspects 1 through 3, where the second portion of the oxide material includes a first sub-portion and a second sub-portion and the implanted portion of the nitride material is located over the first sub-portion of the oxide material and the non-implanted portion of the nitride material is located over the second sub-portion of the oxide material.Aspect 5: The method or apparatus of aspect 4, where the first sub-portion of the oxide material is located in a first bottom corner of the channel and the second sub-portion of the oxide material is located in a second bottom corner of the channel that is opposite the first bottom corner and the first portion of the top surface of the layer of the first material is located between the first sub-portion of the oxide material and the second sub-portion of the oxide material.Aspect 6: The method or apparatus of any of aspects 4 through 5, where etching the implanted portion of the nitride material includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for etching the second sub-portion of the oxide material based at least in part on the etch of the non-implanted portion of the nitride material exposing the second sub-portion of the oxide material, where the remaining second portion of the oxide material is the first sub-portion of the oxide material based at least in part on etching the second sub-portion of the oxide material.Aspect 7: The method or apparatus of any of aspects 1 through 6, where different portions of the implanted portion of the nitride material include different quantities of implanted carbon.Aspect 8: The method or apparatus of aspect 7, where a first portion of the implanted portion of the nitride material that is over the first portion of the top surface of the layer of the first material is implanted with a first quantity of carbon; a second portion of the implanted portion of the nitride material that is over the second portion of the oxide material is implanted with a second quantity of carbon that is less than the first quantity of carbon; and a third portion of the implanted portion of the nitride material that is over a first sidewall of the channel is implanted with a third quantity of carbon that is less than the second quantity of carbon.Aspect 9: The method or apparatus of aspect 8, where the first quantity of carbon is greater than the second quantity of carbon based at least in part on a first angle of the first portion of the implanted portion of the nitride material relative to a direction of the implanting being greater than a second angle of the second portion of the implanted portion of the nitride material relative to the direction of the implanting and the second quantity of carbon is greater than the third quantity of carbon based at least in part on the second angle being greater than a third angle of the third portion of the implanted portion of the nitride material relative to the direction of the implanting.Aspect 10: The method or apparatus of any of aspects 8 through 9, where etching the non-implanted portion of the nitride material includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for etching the third portion of the implanted portion of the nitride material that is over the first sidewall of the channel based at least in part on the third quantity of carbon failing to satisfy a threshold quantity of implanted carbon.Aspect 11: The method or apparatus of any of aspects 1 through 10, where etching the implanted portion of the nitride material includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for etching a first portion of the layer of the first material exposed based at least in part on etching the non-implanted portion of the nitride material, where a second portion of the layer of the first material is unetched based at least in part on the remaining second portion of the oxide material being over the second portion of the layer of the first material and etching a first portion of a layer of the second material that is under the first portion of the layer of the first material.Aspect 12: The method or apparatus of any of aspects 1 through 11, where the second portion of the oxide material is in contact with the second portion of the top surface of the layer of the first material, one or more sidewalls of the channel, or any combination thereof.Aspect 13: The method or apparatus of any of aspects 1 through 12, where an intermediate material separates the second portion of the oxide material from the second portion of the top surface of the layer of the first material, one or more sidewalls of the channel, or any combination thereofAspect 14: The method or apparatus of any of aspects 1 through 13, where the first material includes a sacrificial material for replacement by a word line and the second material includes a dielectric material.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:Aspect 15: An apparatus, including: a substrate; a memory region over the substrate and including a plurality of levels of memory cells; an access region over the substrate and including: a plurality of word lines associated with accessing the plurality of levels of memory cells; a conductive pillar for coupling a first word line at a first level of memory cells with decoder circuitry in association with accessing a set of memory cells at the first level, where the conductive pillar is located in a channel region between word lines at levels over the first level and for providing access to the first word line, and where the conductive pillar extends, in a first direction orthogonal to the substrate, from the first word line through a fill material in the channel region over the first word line; and an oxide material in contact with the first word line and a dielectric material located between the first level and a second level of memory cells over the first level.Aspect 16: The apparatus of aspect 15, where the access region further includes: a metal contact coupled with the first word line and the conductive pillar, where the oxide material is in contact with the metal contact, the conductive pillar, or any combination thereof.Aspect 17: The apparatus of any of aspects 15 through 16, where a portion of the fill material is located between the oxide material and the conductive pillar in a second direction parallel to the substrate.Aspect 18: The apparatus of any of aspects 15 through 17, further including: a second conductive pillar for coupling a second word line at a third level of memory cells with the decoder circuitry, where the second conductive pillar is located in the channel region and extends from the second word line through the fill material.Aspect 19: The apparatus of any of aspects 15 through 18, where the fill material includes a second oxide material different from the oxide material.Aspect 20: The apparatus of any of aspects 15 through 19, where: the fill material is associated with a first etch rate, a first density, or any combination thereof, and the oxide material is associated with a second etch rate different from the first etch rate, a second density different from the first density, or any combination thereof.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:Aspect 21: An apparatus, including: a substrate; a plurality of word lines over the substrate and separated from each other by respective dielectric layers; a contact coupled with a first word line of the plurality of word lines; a conductive pillar coupled with the contact and for coupling the first word line with decoder circuitry, the conductive pillar extending through a first oxide material located over the first word line; and a second oxide material over the first word line and adjacent to a first dielectric layer that is over the first word line.Aspect 22: The apparatus of aspect 21, further including: a second contact coupled with a second word line of the plurality of word lines; and a second conductive pillar coupled with the second contact and for coupling the second word line with the decoder circuitry, the second conductive pillar extending through the first oxide material, where the conductive pillar and the second conductive pillar are located in a channel region that is between word lines over the first word line and the second word line and is for providing access to the first word line and the second word line.Aspect 23: The apparatus of any of aspects 21 through 22, where the second oxide material is in contact with the first word line, the first dielectric layer, or any combination thereof.Aspect 24: The apparatus of any of aspects 21 through 22, where the second oxide material is separated from the first word line, the first dielectric layer, or any combination thereof, by an intermediate material.Aspect 25: The apparatus of any of aspects 21 through 24, where the second oxide material is in contact with the contact, the conductive pillar, or any combination thereof.Aspect 26: The apparatus of any of aspects 21 through 24, where the second oxide material is adjacent to the contact and separated from the contact by a portion of the first oxide material in a first direction that is parallel to the substrate.

The term “layer” or “level” used herein refers to a stratum or sheet of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, or materials, or combinations thereof. In some examples, one layer or level may be composed of two or more sublayers or sublevels.