Method and charge-up circuit capable of adjusting charge-up current

A charge-up circuit includes a charge-up transistor configured to supply a charge-up current to a secondary battery in accordance with a control signal, a detection resistor connected in series with the charge-up transistor to detect the charge-up current, a current-to-voltage conversion circuit configured to generate and output a monitor voltage in accordance with the charge-up current based on each voltage at both end terminals of the detection resistor, a reference voltage generator configured to generate a predetermined reference voltage and including a voltage adjusting mechanism to generate the reference voltage from the constant voltage so that the charge-up current becomes a desired current, and a charge-up current control circuit configured to control the charge-up transistor so that the monitor voltage becomes the reference voltage.

TECHNICAL FIELD

The present disclosure relates to a charge-up circuit, and more particularly, to a charge-up circuit capable of adjusting charge-up current.

BACKGROUND ART

Recently, a variety of different types of electric equipment such as mobile phones, digital cameras, personal computers and so on have been widely developed. Such electric equipment commonly includes a secondary battery that supplies power to the electric equipment because the secondary battery can be used repeatedly by recharging using a charge-up circuit.

FIG. 1is a circuit diagram of a known charge-up circuit. InFIG. 1, the charge-up circuit includes a current-to-voltage conversion circuit101, a charge-up current control circuit102, a reference voltage generator103, a PMOS transistor104, a resistor Rsen, and a secondary battery120. The resistor Rsenis used for detecting a charge-up current ichgto the secondary battery120. The current-to-voltage conversion circuit101generates and outputs a charge-up-current monitor voltage CCMON by converting the charge-up current ichgflowing through the resistor Rsento a voltage. The charge-up current control circuit102controls the PMOS transistor104so that the charge-up-current monitor voltage CCMON becomes a predetermined reference voltage CCREF.

The current-to-voltage conversion circuit101includes a differential amplifier111and resistors R101and R102. Generally, the differential amplifier111has an input offset. Accordingly, an offset adjustment mechanism is employed to eliminate the input offset of the differential amplifier111so as to generate the charge-up-current monitor voltage CCMON accurately for the charge-up current ichgflowing through the resistor Rsen.

FIG. 2is a circuit diagram of the differential amplifier111ofFIG. 1. InFIG. 2, the differential amplifier111includes NMOS transistors M111and M112, PMOS transistors M113and M114, resistors R111and R112for trimming, and a current source113. The NMOS transistors M111and M112form a differential pair of the differential amplifier111. Similarly, the PMOS transistors M113and M114also form a differential pair. Each resistor R111and R112is connected in series between the corresponding NMOS transistor M111and M112and the current source113, respectively. The differential amplifier111is adjusted by trimming of the resistors R111and R112so as to eliminate the input offset.

However, when an input offset adjustment is performed for the above-described differential amplifier111, fluctuation of 0.5 mv in the input offset of the differential amplifier111may be generated due to variation in trimming accuracy. When a fluctuation of 0.5 mv in the input offset of the differential amplifier111is generated, the charge-up current ichgdeviates by 1/(2×rsen)mA where the resistance of the resistor Rsenis rsen, indicating that the charge-up current ichgdeviates by 5 mA when the resistance rsen=0.1Ω. Thus, it is difficult to achieve further reduction of the fluctuation in the charge-up current ichg.

BRIEF SUMMARY

This patent specification describes a novel charge-up circuit that includes a charge-up transistor configured to supply a charge-up current to a secondary battery in accordance with a control signal, a detection resistor connected in series with the charge-up transistor to detect the charge-up current, a current-to-voltage conversion circuit configured to generate and output a monitor voltage in accordance with the charge-up current based on each voltage at both end terminals of the detection resistor, a reference voltage generator configured to generate a predetermined reference voltage and including a voltage adjusting mechanism to generate the reference voltage from the constant voltage so that the charge-up current becomes a desired current, and a charge-up current control circuit configured to control the charge-up transistor so that the monitor voltage becomes the reference voltage.

This patent specification further describes a novel control method used in a charge-up circuit that includes a charge-up transistor configured to supply a charge-up current to a secondary battery in accordance with a control signal, and a detection resistor connected in series with the charge-up transistor to detect the charge-up current. The control method comprises generating a voltage in accordance with the charge-up current based on each voltage at both end terminals of the detection resistor, and controlling the charge-up transistor so that a generated voltage becomes a predetermined reference voltage. The reference voltage is adjusted so that the charge-up current becomes a desired current.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, particularly toFIG. 3, a charge-up circuit according to exemplary embodiment is described.

First Embodiment

FIG. 3is a circuit diagram of a charge-up circuit according to a first example embodiment. The charge-up circuit1charges a secondary battery5such as a lithium battery from an AC adapter6that is a power source with a predetermined charge-up current ichg.

InFIG. 3, the charge-up circuit1includes a resistor Rsen, a charge-up transistor M1that is formed of a PMOS transistor, a current-to-voltage conversion circuit2, a reference voltage generator3, a charge-up current control circuit4, and a secondary battery5. The resistor Rsenis used to detect a charge-up current ichgto the secondary battery5. The charge-up transistor M1supplies the charge-up current ichgto the secondary battery5in accordance with a control signal input to a gate of the charge-up transistor M1. The current-to-voltage conversion circuit2generates and outputs a charge-up-current monitor voltage (hereinafter monitor voltage) CCMON by converting the charge-up current ichgflowing through the resistor Rsento a voltage. The reference voltage generator3generates a reference voltage CCREF. The charge-up current control circuit4controls the charge-up transistor M1so that the monitor voltage CCMON becomes the reference voltage CCREF. The current-to-voltage conversion circuit2forms a current-to-voltage conversion circuit unit, the reference voltage generator3forms a reference voltage generation circuit unit, and the charge-up current control circuit4forms a charge-up current control circuit unit. The current-to-voltage conversion circuit2, the reference voltage generator3, and the charge-up current control circuit4may be integrated on a single chip.

The current-to-voltage conversion circuit2includes a differential amplifier11, a PMOS transistor M11and resistors R1and R2. The reference voltage generator3includes a constant voltage generator13that generates and outputs a predetermined voltage Vref, and variable resistors R11and R12. The charge-up current control circuit4includes an error amplifier15. Hereinafter, a resistance of the resistor Rsenis rsen, and resistances of the resistors R1and R2are r1and r2, respectively.

The resistor Rsenand the charge-up transistor M1are connected in series between an output terminal of the AC adapter6and a positive electrode of the secondary battery5. A power supply voltage Vdd is output from the output terminal of the AC adapter6. A connection node between the output terminal of the AC adapter6and the resistor Rsenis connected to a connection terminal7. A connection node between the resistor Rsen, and a source of the charge-up transistor M1is connected to a connection terminal8.

The resistor R1, the PMOS transistor M11, and the resistor R2are connected in series between the connection terminal7and ground. A connection node between the resistor R1and the PMOS transistor M1is connected to a non-inverted input terminal of the differential amplifier11. An inverted input terminal of the differential amplifier11is connected to the connection terminal8. An output terminal of the differential amplifier11is connected to a gate of the PMOS transistor M11. A connection node between the PMOS transistor M11and the resistor R2is an output terminal of the current-to-voltage conversion circuit2to output the monitor voltage CCMON.

The variable resistors R11and R12are connected in series between an output terminal of the constant voltage generator and ground. The reference voltage CCREF is output from a connection node between the variable resistors R11and R12. The monitor voltage CCMON is input to a non-inverted input terminal of the error amplifier15, and the reference voltage CCREF is input to an inverted input terminal of the error amplifier15. An output terminal of the error amplifier15is connected to a gate of the charge-up transistor M1through a connection terminal9.

In this circuit configuration, when the charge-up current ichgflows through the resistor Rsen, a voltage difference (ichg×Rsen) is generated across the resistor Rsen. Each voltage at both terminals of the resistor Rsenis input to the current-to-voltage conversion circuit2. The differential amplifier11amplifies the voltage difference (ichg×Rsen) at a ratio of (r2/r1) and outputs an amplified voltage as the monitor voltage CCMON. When the differential amplifier11has an input offset voltage of +V1in a direction from the inverted terminal to the non-inverted input terminal of the differential amplifier11, the monitor voltage CCMON is expressed by a following formula (1),
CCMON=(ichg×rsen−V1)×(r2/r1)  (1)

The error amplifier15of the charge-up current control circuit4controls the charge-up transistor M1so that the monitor voltage CCMON becomes the reference voltage CCREF. When the error amplifier15has an input offset voltage of +V2in a direction from the inverted terminal to the non-inverted input terminal, the transistor M1is controlled by the error amplifier15so that a following formula (2) holds,
CCREF=CCMON−V2  (2)

From formulas (1) and (2), a relation between the reference voltage CCREF and the charge-up current ichgcan be expressed by a following formula (3),
CCREF=(ichg×rsen−V1)×(r2/r1)−V2  (3)

Since the resistance rsenin formula (3) is a known value, a voltage CCREF1of the reference voltage CCREF can be determined by measuring V1, V2and (r2/r1) with a following formula (4),
CCREF1=(ichg1×rsen−V1)×(r2/r1)−V2  (4)

The charge-up current ichgcan be adjusted to be a setting current value ichg1by adjusting resistances by trimming of the resistors R11and/or R12so that the reference voltage CCREF becomes the voltage value CCREF1expressed by the formula (4).

Thus, the charge-up current ichgcan be adjusted to a desired value without being affected by fluctuation in bias current and fluctuation in absolute value of resistance due to variation during manufacturing. In this case, a voltage of 1 mV in the reference voltage CCREF corresponds to the charge-up current of (r2/r1)×(1/rsen)mA. Accordingly, trimming accuracy can be increased if the ratio of (r2/r1) is made small. For example, when rsen=0.1Ω and r2/r1=0.1, a voltage of 1 mV in the reference voltage CCREF corresponds to the charge-up current of 1 mA. Therefore, it is possible to improve trimming accuracy over that of a conventional circuit with no trimming.

FIG. 4is an actual circuit diagram of the variable resistors R11and R12in the reference circuit3. InFIG. 4, the variable resistor R11includes m number of fixed resistor RA1through RAm connected in series (where m is positive integer), and fuses FA1through FAm each of which is connected in parallel with corresponding fixed resistor RA1through RAm. Similarly, the variable resistor R12includes n number of fixed resistor RB1through RBn also connected in series (where n is positive integer), and fuses FB1through FBn each of which is also connected in parallel with corresponding fixed resistor RB1through RBn.

The resistances of the resistors R11and/or R12is adjusted by selectively cutting the fuses FA1through FAm and FB1through FBn with trimming so that the reference voltage CCREF becomes the voltage value CCREF1as expressed by formula (4) described above. Accordingly, the charge-up current ichgcan be adjusted to a setting current value ichg1. The resistances of the fixed resistors RA1through RAm and the fixed resistors RB1through RBn can be either the same or different.

The charge-up circuit1according to the first example embodiment converts a current flowing through the resistor Rsento a voltage to generate the monitor voltage CCMON, and controls the charge-up transistor M1so that the monitor voltage CCMON becomes the reference voltage CCREF. In this charge-up circuit1, the reference voltage CCREF can be set arbitrarily because the reference voltage CCREF is generated by dividing the constant voltage Vrefwith the variable resistors R11and R12. Consequently, the charge-up current to charge up a secondary battery can be adjusted accurately to a desired current.

Second Embodiment

In the charge-up circuit1according to the first example embodiment, there is a possibility that, if the differential amplifier11of the current-to-voltage conversion circuit2has an input offset that reduces a potential difference generated between both terminals of the resistor R1, the monitor voltage CCMON may become 0 v even when a current flows through the resistor Rsen.

FIG. 5is a circuit diagram of a charge-up circuit according to a second example embodiment. The charge-up circuit according to the second embodiment can adjust an input offset so as to have a large input offset larger than the input offset caused by variation during fabrication.

InFIG. 5, identical reference characters are assigned to identical or similar circuit members shown inFIG. 3and descriptions thereof are omitted. Further, the charge-up circuit1shown inFIG. 3is changed to a charge-up circuit1a. Similarly, the differential amplifier11is changed to a differential amplifier11a, and the current-to-voltage conversion circuit2is changed to a current-to-voltage conversion circuit2a.

The charge-up circuit1acharges the secondary battery5such as a lithium battery from an AC adapter6that is a power source with a predetermined charge-up current ichg.

InFIG. 5, the charge-up circuit1aincludes a resistor Rsen, a charge-up transistor M1, a current-to-voltage conversion circuit2a, a reference voltage generator3, a charge-up current control circuit4, and a secondary battery5. The current-to-voltage conversion circuit2agenerates and outputs a charge-up-current monitor voltage CCMON by converting the charge-up current flowing through the resistor Rsento a voltage. Further, the current-to-voltage conversion circuit2aincludes a differential amplifier11a, a PMOS transistor M11and resistors R1and R2. The current-to-voltage conversion circuit2aforms a current-to-voltage conversion circuit unit. The current-to-voltage conversion circuit2a, the reference voltage generator3and the charge-up current control circuit4may be integrated on a single chip.

FIG. 6is a circuit diagram of the differential amplifier11aused in the current-to-voltage conversion circuit2a. InFIG. 6, the differential amplifier11aincludes NMOS transistors M21and M22, PMOS transistors M23and M24, and a current source21. The NMOS transistors M21and M22are a pair of input transistors, and the PMOS transistors M23and M24are load transistors to form a current mirror circuit. The current source21supplies a predetermined constant current to each input transistor M21and M22. Each source of the PMOS transistors M23and M24is connected to a power supply terminal that supplies a voltage of Vdd. Each gate of the PMOS transistors M23and M24is connected in common, and a connection node between each gate of the PMOS transistors M23and M24is connected to a drain of the PMOS transistor M24.

A drain of the PMOS transistor M23is connected to a drain of the NMOS transistor M21, and a drain of the PMOS transistor M24is connected to a drain of the NMOS transistor M22. Each source of the NMOS transistors M21and M22is connected in common, and the current source21is connected between ground and a connection node between each source of the NMOS transistors M21and M22. A gate of the NMOS transistor M21is an inverted terminal of the differential amplifier11a, and a gate of the NMOS transistor M22is a non-inverted terminal of the differential amplifier11a.

In this circuit configuration, the NMOS transistors M21and M22are formed to have different sizes so that the differential amplifier11ahas an input offset.

Generally, when a gate-source voltage between a gate and a source is Vgs and a threshold voltage is Vth, a saturation current id of the MOS transistor is expressed by a following formula (5),
Id=β/2×(Vgs−Vth)2
β=μ×Cox×(W/L)  (5)
where μ is mobility, Cox is unit capacitance of oxide, W is a channel width, and L is a channel length. In this formula, a channel length modulation term is omitted.

Rewriting formula (5), the gate-source voltage can be expressed by a following formula (6),
Vgs=(2×id/β)1/2+Vth(6)

When β of the NMOS transistor M22is made to have 4×β1 where β of the NMOS transistor M21is β1, a voltage difference ΔVgs between the gate-source voltage Vgs of the NMOS transistors M21and M22is expressed by a following formula (7),
ΔVgs=(2×id/β1)1/2+Vth−[{2×id/(4×β1)}1/2+Vth]=(2×id/β1)1/2/2  (7)

Thus, since the NMOS transistors M21and M22have different values of β, the gate-source voltages Vgs of the NMOS transistors M21and M22are different. Accordingly, it is possible to set a large offset voltage larger than an input offset caused by variation during fabrication.

As above-described, in the charge-up circuit1aaccording to the second example embodiment, the differential amplifier11ahas input transistors formed of NMOS transistors to have different values of β for the NMOS transistors, so that it is possible to set a large offset voltage larger than an input offset caused by variation during fabrication. The charge-up circuit1acan prevent the monitor voltage CCMON from becoming 0 v in addition to providing an effect similar to that of the charge-up circuit1according to the first example embodiment. Accordingly, it is possible to convert a charge-up current ichgto a voltage safely. Consequently, it is possible to adjust reference voltage CCREF more accurately so as to obtain a desired charge-up current ichg.

This patent specification is based on Japanese Patent Application, No. 2007-217223 filed on Aug. 23, 2007 in the Japanese Patent Office, the entire contents of which are incorporated by reference herein.