Display panel, method of manufacturing the same, and liquid crystal display panel

A liquid crystal display panel includes a thin film transistor disposed on an insulating substrate in a display region, an external wiring for connecting the thin film transistor to a terminal electrode, and a planarized film disposed on the thin film transistor, and having a planarized upper surface. The planarized film is not disposed, or a planarized film having a smaller film thickness than that of the planarized film in the display region is disposed, above the external wiring in a frame region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display panel, a method of manufacturing the same, and a liquid crystal display panel having the display panel.

2. Description of the Background Art

Conventionally, as a display mode of a liquid crystal display device, a twisted nematic (TN) mode that generates an electric field in a direction vertical to a liquid crystal display panel has been widely used. Meanwhile, there is proposed a horizontal electric field mode in which liquid crystal molecules are driven in a horizontal direction by an electric field generated in a direction parallel to the liquid crystal display panel (horizontal direction). This horizontal electric field mode has an advantage in enhancing a viewing angle, and implementing high definition and high luminance, so that it is thought that this mode will become the mainstream in a small/medium size panel such as a smartphone or a tablet especially.

The horizontal electric field mode includes an in-plane switching (IPS) mode and a fringe field switching (FFS) mode. A FFS mode liquid crystal display device includes a lower electrode, an upper electrode having slits, and an insulating film provided between those electrodes, and one of the lower electrode and the upper electrode is used as a pixel electrode, and the other is used as an opposed electrode. When a voltage is applied between the pixel electrode and the opposed electrode, an electric field is generated in the liquid crystal layer in roughly a horizontal direction, and the liquid crystal molecules in the liquid crystal layer are driven by the electric field in the horizontal direction.

A signal line and a thin film transistor are formed below the upper electrode and the lower electrode with a protective insulating film interposed between them, in a display region of the liquid crystal display panel. The above-described electric field is generated when a certain signal (voltage) is externally applied to the lower electrode or the upper electrode through a contact hole of the protective insulating film after passing through the signal line, and the thin film transistor.

However, during an operation, parasitic capacity which causes a display quality to degrade is generated between the lower electrode and the signal line. Thus, an insulating film is formed between the lower electrode and the signal line, in order to reduce the parasitic capacity. As the insulating film, Japanese Patent Application Laid-Open No. 2007-226175 proposes using an acrylic resin film having a relatively large thickness that can reduce the parasitic capacity, and can eliminate an uneven surface of the thin film transistor.

The liquid crystal display panel includes not only the above-described display region but also a frame region surrounding the display region. The frame region includes a plurality of terminal electrodes, and a plurality of external wirings extended from the display region and connected to the plurality of the terminal electrodes, and each of the external wirings is covered with a protective insulating film that protects the external wiring from being damaged or corroded with water.

Here, in a process of manufacturing the liquid crystal display device, the terminal electrode of the liquid crystal display panel is electrically connected to an external element (such as a printed substrate or IC chip). More specifically, the terminal electrode exposed in the protective insulating film is bonded to the external element by pressure bonding through an anisotropic conductive film (ACF), whereby the terminal electrode and the external element are connected through conductive particles in the ACF.

However, in the case where the above-described acrylic resin film is formed above the external wiring in the frame region, there is a difference in height (uneven surface) roughly corresponding to a film thickness of the acrylic resin film, between the acrylic resin film formed above the external wiring, and the terminal electrode above which the acrylic resin film is not formed. Therefore, although the terminal electrode and the external element should be connected through the conductive particles in the ACF originally, they cannot be connected because the acrylic resin film is formed in the vicinity of the terminal electrode (the pressure force is dispersed to the acrylic resin film), that is, a contact defect is caused in some cases. Especially, when the external wiring and the terminal electrode are closely provided in order to miniaturize the frame region, it is thought that such problem becomes more conspicuous.

Meanwhile, in a case where the acrylic resin film is not formed above the external wiring, there is a problem that the protective insulating film to cover the external wiring and thus the external wiring are damaged in a process of manufacturing the liquid crystal display panel.

SUMMARY OF THE INVENTION

The present invention was made to solve the above problem, and it is an object of the present invention to provide a technique capable of surely connecting a terminal electrode to an external element.

A display panel according to the present invention includes an insulating substrate, a thin film transistor, a terminal electrode, a wiring, an insulating film, and a planarized film. A display region, and a frame region surrounding the display region are defined in the insulating substrate, the thin film transistor is disposed on the insulating substrate in the display region, and the terminal electrode is disposed on the insulating substrate in the frame region. The wiring is disposed on the insulating substrate to connect the thin film transistor to the terminal electrode, the insulating film has an opening over the terminal electrode and covers the wiring, and the planarized film is disposed on the thin film transistor and has a planarized upper surface. The planarized film is not disposed or a planarized film having a thinner film thickness than that of the planarized film disposed in the display region is disposed, above the wiring in the frame region.

The planarized film is not disposed or the planarized film having the thinner film thickness than that of the planarized film disposed in the display region is disposed, above the wiring in the frame region. Therefore, the terminal electrode and the external element can be surely connected.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In a first preferred embodiment of the present invention, an FFS mode liquid crystal display panel including a display panel according to the present invention will be described, as an example.FIG. 1is a plan view illustrating a configuration of the liquid crystal display panel according to the first preferred embodiment. In addition,FIG. 1shows each component schematically, and a precise size and the like of the component is not reflected in the drawing. In addition, inFIG. 1, components other than a main part of the present invention are omitted and the configuration is partially simplified occasionally, so as not to make the drawing complicated. These are true in the following drawings. Furthermore, in the following drawings, the same component as described in the former drawing is given the same reference sign and its description is omitted.

A liquid crystal display panel1includes a transparent insulating substrate (insulating substrate)100in which a display region101, and a frame region102surrounding the display region101are defined.

As shown inFIG. 1, the liquid crystal display panel1includes a thin film transistor106disposed on the transparent insulating substrate100in the display region101, a terminal electrode107disposed on the transparent insulating substrate100in the frame region102, and a wiring for electrically connecting the thin film transistor106to the terminal electrode107. The wiring is disposed on the transparent insulating substrate100in both of the display region101and the frame region102. Here, the wiring in the display region101corresponds to a signal line103or a scanning line104, and the wiring in the frame region102corresponds to an external wiring117.

In the frame region102, the plurality of the external wirings117extended from the display region101are connected to the plurality of the terminal electrodes107. The terminal electrode107is electrically connected to a terminal of an external element (a printed substrate108or an IC chip109here) through an anisotropic conductive film (ACF), a bump, or the like.

FIG. 2is an enlarged plan view of a region in which the terminal electrodes107are formed (mounted) (hereinafter, referred to as the terminal mounted region), in the frame region102shown inFIG. 1.

The terminal electrode107is connected to an extension portion of the external wiring117, and a width of the terminal electrode107is large compared to a width of the external wiring117. In addition, the one terminal electrode107is not arranged adjacent to the other terminal electrodes107in an arrangement direction of the external wiring117, but adjacent to the two external wirings117so as to be sandwiched between them. In this configuration, the adjacent external wirings117can be arranged closer to each other, so that an area of the frame region102can be more reduced.

Referring toFIG. 1again, the display region101will be described. The plurality of the signal lines103and the scanning lines104which are insulated from each other are arranged so as to intersect with each other in the display region101. Furthermore, a plurality of common wirings105are arranged parallel to the scanning lines104. One pixel is disposed with the one signal line103and the one scanning line104intersecting with each other, and the plurality of the pixels are arranged in the form of a matrix in the whole display region101.

FIG. 3is a plan view illustrating the enlarged pixels disposed in the display region101. The liquid crystal display panel1according to the first preferred embodiment includes a lower electrode71shown by a two-dot chain line inFIG. 3and an upper electrode91. One of the lower electrode71and the upper electrode91is used as a pixel electrode, and the other is used as an opposed electrode. Hereinafter, a description will be given on one configuration in which the lower electrode71serves as the opposed electrode, and the upper electrode91serves as the pixel electrode, as an example, but as the other configuration, the lower electrode71may serve as the pixel electrode, and the upper electrode91may serve as the opposed electrode, as a matter of course.

Here, the liquid crystal display panel1according to the first preferred embodiment includes a liquid crystal layer (not shown) above the upper electrode91. The lower electrode71and the upper electrode91can apply a fringe electric field to the liquid crystal layer under the control of the thin film transistor106serving as a switching element. When a voltage is applied between the lower electrode71(opposed electrode) and the upper electrode91(pixel electrode), an electric field is generated and travels such that it travels from the upper electrode91toward the liquid crystal layer provided above the upper electrode91, travels in a roughly horizontal direction in the liquid crystal layer, and travels toward the lower electrode71after passing through a slit91ain the upper electrode91provided below the liquid crystal layer. Thus, liquid crystal molecules in the liquid crystal layer are driven in response to the electric field in the horizontal direction.

The thin film transistor106is provided between the lower electrode71and the upper electrode91, and the transparent insulating substrate100. A gate electrode11of the thin film transistor106is electrically connected to the scanning line104, and a source electrode41of the thin film transistor106is electrically connected to the signal line103. A drain electrode42of the thin film transistor106is electrically connected to the upper electrode91(pixel electrode) through a contact hole141. Furthermore, the common wiring105is electrically connected to the lower electrode71(opposed electrode) through a contact hole151.

The thin film transistor106turns on or off a supply of a display voltage to the pixel electrode (the upper electrode91), based on a signal from the scanning line104. In addition, the display voltage corresponds to signal data inputted from the external element such as the printed substrate108to the signal line103through the external wiring117.

More specifically, when the signal is supplied from the scanning line104to the gate electrode11of the thin film transistor106, the thin film transistor106applies a current from the source electrode41toward the drain electrode42. That is, when the signal is supplied from the scanning line104, the thin film transistor106applies the voltage corresponding to the signal data of the signal line103to the upper electrode91(pixel electrode).

Meanwhile, when the signal is not supplied from the scanning line104to the gate electrode11of the thin film transistor106, the thin film transistor106does not apply a current from the source electrode41toward the drain electrode42. That is, when the signal is not supplied from the scanning line104, the thin film transistor106does not apply the voltage corresponding to the signal data of the signal line103to the upper electrode91(pixel electrode).

The signal of the scanning line104and the signal data of the signal line103are controlled by the external element (the printed substrate108or the IC chip109in this case) connected to the terminal electrode107, and the voltage corresponding to the external display data is supplied to each pixel.

Next, a configuration of the display region101and a configuration of the frame region102will be described with reference to the cross-sectional views. First, the configuration of the display region101will be described.

<Configuration of Display Region101>

FIG. 4is a cross-sectional view illustrating the configuration of the display region101(configuration of the pixel), and more specifically, the cross-sectional view along a line a-a′ shown inFIG. 3. In addition, the components in the display region101will be described mainly here, but the components in the frame region102will be also described occasionally.

The thin film transistor106according to the first preferred embodiment is provided with the gate electrode11, a gate insulating film2, a semiconductor film31, the source electrode41, and the drain electrode42.

The scanning line104is disposed on the transparent insulating substrate100in the display region101, and a part corresponding to the thin film transistor106, of the scanning line104serves as the gate electrode11. Furthermore, the common wiring105(FIG. 3) is disposed parallel to the scanning line104, on the transparent insulating substrate100in the display region101.

Meanwhile, the external wiring117(FIG. 1) connected to the scanning line104is disposed on the transparent insulating substrate100in the frame region102. In addition, here, the scanning line104(the gate electrode11), the common wiring105, and the external wiring117connected to the scanning line104are formed by patterning the same metal film.

The gate insulating film2is disposed on the transparent insulating substrate100so as to cover the scanning line104(the gate electrode11), the common wiring105, and the external wiring117connected to the scanning line104. The gate insulating film2may be composed of a SiN film. In addition, as will be described below, the gate insulating film2has an opening for exposing the terminal electrode107.

The semiconductor film31is patterned and disposed into an island shape on the gate electrode11with the gate insulating film2interposed between them. The semiconductor film31is made of any of amorphous silicon, microcrystal silicon, and polycrystalline silicon, or a silicon semiconductor provided by laminating the above silicon, or an oxide semiconductor, for example. The semiconductor film31has a channel region, and a source region and a drain region provided so as to sandwich the channel region.

The source electrode41, the drain electrode42, and the signal line103(FIG. 3) connected to the source electrode41are disposed on the gate insulating film2in the display region101. In addition, the source electrode41is disposed so as to be in contact with the source region of the semiconductor film31, and the drain electrode42is disposed so as to be in contact with the drain region of the semiconductor film31.

Meanwhile, the external wiring117(FIG. 1) connected to the signal line103is disposed on the gate insulating film2in the frame region102. In addition, here, it is supposed that the source electrode41, the drain electrode42, the signal line103, and the external wiring117connected to the signal line103are formed by patterning the same metal film.

A protective insulating film5is disposed on the gate insulating film2so as to directly or indirectly cover the thin film transistor106, the signal line103, the external wiring117connected to the signal line103, the scanning line104, and the external wiring117connected to the scanning line104. In addition, as will be described below, the protective insulating film5has an opening for exposing the terminal electrode107.

The protective insulating film5is composed of an inorganic insulating film such as a SiN film or silicon oxide film (SiO film). When the inorganic insulating film is used for the protective insulating film5, it is possible to prevent the signal line103, the scanning line104, and the external wiring117from being damaged because the inorganic insulating film has relatively high mechanical strength. Furthermore, when the inorganic insulating film such as the SiN film is used for the protective insulating film5, water leaching from an organic planarized film6to the signal line103, the scanning line104, and the external wiring117can be prevented, so that it is possible to prevent corrosion by water and deterioration of characteristics of the thin film transistor106.

A planarized film (the organic planarized film6inFIG. 4) having a planarized upper surface is disposed on the thin film transistor106and above the signal line103and the scanning line104in the display region101. An uneven surface in the thin film transistor106is filled with this planarized film, and an upper surface of the planarized film is almost flat without reflecting (transferring) the uneven surface disposed under the planarized film. Thus, the lower electrode71and the upper electrode91are disposed on the planarized plane.

The planarized film is composed of an organic resin film mainly made of acrylic or spin-on-glass (SOG) film, for example. Each of the acrylic resin film and the SOG film has a dielectric constant (about 3 to 4) lower than a dielectric constant (about 6 to 7) of the SiN film, so that when the acrylic resin film or the SOG film is used for the planarized film, it is possible to reduce parasitic capacity between the signal line103and the lower electrode71. That is, it is possible to prevent a noise from the signal line103from harmfully affecting the lower electrode71during an operation of the liquid crystal display panel1, so that a display quality can be improved. In addition, a SiO film has a dielectric constant which is about the same as that of the SOG film, but it is not suitable for the planarized film because it is difficult to be planarized.

Hereinafter, a description will be given, assuming that the organic resin film is used for the planarized film, and the planarized film is referred to as the organic planarized film6. In addition, when a photosensitive organic resin film is used for the organic planarized film6, a desired pattern can be formed in the organic planarized film6by a photolithography process (photoengraving process).

On the organic planarized film6in the display region101, the following components are disposed, that is, the lower electrode71composed of a transparent conductive film made of IZO or ITO, an interlayer insulating film8composed of a SiN film, the upper electrode91composed of a transparent conductive film made of IZO or ITO, and the liquid crystal layer are disposed in this order. That is, the liquid crystal layer is disposed above the organic planarized film6in the display region101, and the upper electrode91(pixel electrode) and the lower electrode71(opposed electrode) are disposed between the organic planarized film6and the liquid crystal layer in the display region101.

Contact holes51,61, and81are formed in the protective insulating film5, the organic planarized film6, and the interlayer insulating film8, respectively. These contact holes51,61, and81compose the contact hole141provided over the drain electrode42. One part of the upper electrode91is electrically connected to the drain electrode42through the contact hole141.

Similarly, contact holes are formed in the gate insulating film2, the protective insulating film5, and the organic planarized film6, respectively, and these contact holes compose the contact hole151(FIG. 3) provided over the common wiring105. One part of the lower electrode71is electrically connected to the common wiring105through the contact hole151.

<Configuration of Frame Region102>

Next, a description will be given on the configuration of the frame region102, and more specifically on a configuration of the terminal mounted region (hereinafter, referred to as the terminal configuration).

In addition, the two terminal configurations exist, that is, the one regarding the external wiring117connected to the scanning line104, and the one regarding the external wiring117connected to the signal line103. However, the terminal configuration of the external wiring117connected to the signal line103is similar to the terminal configuration of the external wiring117connected to the scanning line104except that the gate insulating film2is omitted. Therefore, in the following, the terminal configuration of the external wiring117connected to the scanning line104is only described, and a description of the terminal configuration of the external wiring117connected to the signal line103is omitted.

FIG. 5is a cross-sectional view illustrating a terminal configuration related to the terminal configuration according to the first preferred embodiment (hereinafter, referred to as the related terminal configuration), andFIG. 6is a cross-sectional view illustrating the terminal configuration according to the first preferred embodiment. More specifically,FIGS. 5 and 6are cross-sectional views along a line b-b′ shown in FIG.2.

As shown inFIGS. 5 and 6, in each of the related terminal configuration and the terminal configuration according to the first preferred embodiment, the external wiring117is covered with the insulating films (the gate insulating film2and the protective insulating film5), and the terminal electrode107is exposed in the opening of the insulating films (the gate insulating film2and the protective insulating film5) and in the opening of the organic planarized film6or6a.

Here, it is to be noted that according to the related terminal configuration (FIG. 5), the organic planarized film6having the same film thickness as that of the organic planarized film6in the display region101is disposed above the external wiring117, while according to the terminal configuration in the first preferred embodiment (FIG. 6), the organic planarized film6ahaving a film thickness smaller than that of the organic planarized film6in the display region101is disposed above the external wiring117in the frame region102.

Furthermore, according to the related terminal configuration (FIG. 5), the interlayer insulating film8is disposed above the external wiring117, while according to the terminal configuration in the first preferred embodiment (FIG. 6), the interlayer insulating film8is not disposed above the external wiring117in the frame region102.

According to the terminal configuration in the first preferred embodiment, a difference between a height of a laminated structure including the terminal electrode107, and a height of a laminated structure including the external wiring117(difference in height) can be smaller than that of the related terminal configuration. Therefore, pressure bonding between the terminal electrode107and the external element with the ACF sandwiched between them is not hindered by the organic planarized film6, so that the terminal electrode107and the external element can be surely connected.

Furthermore, the terminal configuration according to the first preferred embodiment is not limited to the configuration shown inFIG. 6, and it may include a configuration in which the organic planarized film is not disposed above the external wiring117in the frame region102as shown inFIG. 7. According to such configuration, a difference between the height of the configuration above the terminal electrode107and the height of the configuration above the external wiring117(difference in height) can be further reduced, so that the terminal electrode107and the external element can be further surely connected.

Next, a production process of the liquid crystal display panel1according to the first preferred embodiment will be sequentially described with reference toFIGS. 8A to 16B.FIGS. 8A,9A, and11A to16A are cross-sectional views each illustrating the configuration of the display region101,FIGS. 8B,9B, and11B to16B are cross-sectional views each illustrating the configuration of the frame region102(terminal mounted region). As can be seen from the following description, the configuration of the display region101and the configuration of the frame region102are formed concurrently.

First, a metal film is formed by sputtering or the like on a whole surface of the transparent insulating substrate100such as a glass substrate. The metal film is made of aluminum (Al), an alloy containing it, molybdenum (Mo), or chrome (Cr), for example. Then, a photoresist composed of photosensitive resin is coated on the metal film by spin coating and the like, and the coated photoresist is exposed and developed in a first photolithography process, whereby the photoresist is patterned.

Then, the metal film is etched with the patterned photoresist used as an etching mask. Thus, the scanning line104(the gate electrode11) and the common wiring105are formed on the transparent insulating substrate100in the display region101, and the external wiring117connected to the scanning line104and the terminal electrode107are formed on the transparent insulating substrate100in the frame region102. That is, the wirings (the scanning line104and the external wiring117) for connecting the thin film transistor106(the gate electrode11) to the terminal electrode107are formed on the transparent insulating substrate100. After that, the photoresist is removed.

Next, the gate insulating film2and the semiconductor film that becomes the semiconductor film31are sequentially formed, for example, by plasma chemical vapor deposition (CVD) on the whole surface of the transparent insulating substrate100having the gate electrode11and the like. In addition, the gate insulating film2may be composed of a SiN film. Then, a photoresist is patterned in a second photolithography process and then ions are implanted, whereby the source region, the channel region, and the drain region of the thin film transistor106are formed in the semiconductor film. In addition, the semiconductor film is patterned into an island shape by etching, whereby the semiconductor film31is formed. After that, the photoresist is removed.

Then, a metal film is formed by sputtering or the like, on the whole surface of the transparent insulating substrate100having the semiconductor film31and the like. The metal film is made of aluminum (Al), an alloy containing it, or molybdenum (Mo), or chrome (Cr), for example. Then, a photoresist is patterned in a third photolithography process, the metal film is etched, and the photoresist is removed, whereby the source electrode41, the drain electrode42, and the signal line103are formed on the transparent insulating substrate100(the gate insulating film2) in the display region101. That is, the thin film transistor106is formed on the transparent insulating substrate100in the display region101.

At the same, the external wiring117connected to the signal line103is formed on the transparent insulating substrate100(the gate insulating film2) in the frame region102. That is, the wirings (the signal line103and the external wiring117) for connecting the thin film transistor106(the source electrode41) to the terminal electrode107are formed on the gate insulating film2(the transparent insulating substrate100). A structure obtained through the above-described process is shown inFIGS. 8A and 8B.

Then, the protective insulating film5is formed by plasma CVD on the whole surface of the transparent insulating substrate100having the source electrode41and the like. That is, the protective insulating film5is formed to cover the thin film transistor106, the terminal electrode107, and the wirings (the signal line103, the scanning line104, and the external wiring117). In addition, the protective insulating film5may be composed of a SiN film, for example.

Then, the organic planarized film6having a planarized upper surface is coated (formed) by spin coating and the like, on the whole surface of the transparent insulating substrate100having the protective insulating film5. In addition, here, the organic planarized film6is composed of a photosensitive organic resin film, and formed to have a thickness of 2 μm to 4 μm, for example. A structure obtained through the above-described process is shown inFIGS. 9A and 9B.

Then, the organic planarized film6is exposed and developed with a photomask200in a fourth photolithography process. Hereinafter, the photomask200will be described in detail.

FIG. 10Ais a plan view illustrating a part of the photomask200, andFIG. 10Bis a side view illustrating a part of the photomask200. The photomask200used in exposing the organic planarized film6includes a half tone mask (hereinafter, referred to as the HT mask) or a gray tone mask (hereinafter, referred to as the GT mask).

The HT mask controls transmittance with a transmittance control layer. Meanwhile, the GT mask has a light-blocking portion having an opening formed of a pattern of fine slits and dots, and irradiated light passing through the opening (transmission amount) can be controlled by adjusting a size of the opening. The HT mask and the GT mask can be used for the photomask200, but the HT mask needs a transmittance control layer other than an ordinary exposure pattern layer, and its cost is higher than that of the GT mask, so that a description will be given below on a case where the GT mask is used for the photomask200.

The photomask200proposed by the inventor has a transparent substrate201, an ordinal light-blocking portion202a, and a light-blocking pattern202bserving as the light-blocking portion having a lattice pattern (a kind of a dot pattern) shown inFIG. 10A. The light-blocking pattern202bhas a plurality of square openings (hereinafter, referred to as the lattices203).

The irradiated light from an exposure device is diffracted when it passes through the lattice203of the light-blocking pattern202b.Thus, an exposure amount in a region corresponding to the light-blocking pattern202bbecomes uniform, and the exposure amount in the region corresponding to the light-blocking pattern202bis less than an exposure amount in a region other than the region corresponding to the light-blocking portion202aor the light-blocking pattern202b.

FIGS. 11A and 11Bshow the process in which the organic planarized film6is exposed with the photomask200, andFIGS. 12A and 12Bshow the process in which the organic planarized film6is developed after exposed.

In the exposure process of the display region101shown inFIG. 11A, the organic planarized film6is not exposed in a region just under the ordinal light-blocking portion202a, but the organic planarized film6is exposed in a region other than that (a certain region on the drain electrode42of the thin film transistor106, and a certain region on the common wiring105). Therefore, in the development process for the display region101shown inFIG. 12A, the exposed organic planarized film6is removed, whereby the contact hole61shown inFIG. 12A, and a contact hole serving as a part of the contact hole151(FIG. 3) are formed in the organic planarized film6.

Meanwhile, in the exposure process of the frame region102shown inFIG. 11B, the organic planarized film6is exposed in a region just under the light-blocking pattern202band in a region other than that region. However, the exposure amount in the region just under the light-blocking pattern202b(region above the external wiring117) is less than an exposure amount in the region (region above the terminal electrode107) other than that region. Therefore, in the development process of the frame region102shown inFIG. 12B, the organic planarized film6above the terminal electrode107is removed, while the organic planarized film6above the external wiring117is removed a little (film is thinned) and its film thickness is reduced. In addition, hereinafter, the organic planarized film whose film thickness is reduced in the development process is referred to as an organic planarized film6b. Here, the organic planarized film6bis thinner than the organic planarized film6by about 0.5 μm to 1.2 μm, for example.

Here, as for the lattice pattern of the photomask200, a sum (pitch) of a size of one lattice203and a distance between the two adjacent lattices203is preferably 3 μm, and the size of the one lattice203is preferably equal to or less than 2 μm which is equal to or less than a resolution of the exposure device (that is, 2 μm or less×2 μm or less). In this case, the exposure amount can be uniform in the region corresponding to the light-blocking pattern202b, and the upper surface of the organic planarized film6bcan be planarized.

In addition, the removed amount of the thickness of the organic planarized film6bin the development process corresponds to the exposure amount directly applied in the exposure process, so that it can be controlled by the irradiated light from the exposure device and its transmittance. However, in the case where the organic planarized film6is composed of the organic resin film mainly made of acrylic which sensitively reacts with the exposure, even when the exposure amount is small, the removed amount of the thickness of the organic planarized film6provided above the external wiring117(film reduction amount) becomes large in the development process.

Thus, it is preferable to use the photomask200in which the size of the one lattice203in the lattice pattern is 2 μm (that is, 2 μm×2 μm), and the distance between the two adjacent lattices203in the lattice pattern is 1 μm. In this case, a ratio of the exposure amount (transmit amount) to the irradiated light is about 20%, so that the removed amount of the thickness of the organic planarized film6(film reduction amount) can be adjusted to be an appropriate amount. Actual measurement was made and it was found that the organic planarized film6bwas thinner than the organic planarized film6by 0.8 μm.

In the above, the description has been given on the case where the photomask200that has the light-blocking portion having the lattice pattern is used, but the photomask is not limited to this. For example, instead of the photomask200having the light-blocking portion having the lattice pattern, a photomask that has a light-blocking portion having a slit pattern may be used. In this case, it is preferable to use a photomask in which a sum (pitch) of a size of the one slit and a distance between the two adjacent slits is 2 μm to 3 μm (more preferably 2.5 μm), and the size of the one slit is equal to or less than about 1 μm which is equal to or less than the resolution of the exposure device.

In each case of the lattice pattern and the slit pattern, when a ratio of the size of the lattice203or the slit is small, the removed amount of the organic planarized film6is small in the development process, and when the ratio is great, the removed amount is great. Furthermore, in the case of the slit pattern, when the pitch is small, the removed amount of the organic planarized film6is great in the development process, and when the pitch is large, the removed amount is small.

After the development process shown inFIGS. 12A and 12B, the protective insulating film5and the gate insulating film2are subjected to dry etching with the organic planarized film6or6bused as an etching mask. A structure obtained by the dry etching is shown inFIGS. 13A and 13B.

Through the dry etching, in the display region101, as shown inFIG. 13A, the contact hole51connected to the contact hole61and having the same shape as that of the contact hole61is formed in the protective insulating film5, and a contact hole serving as one part of the contact hole151(FIG. 3) is formed in the gate insulating film2and the protective insulating film5. Furthermore, in the frame region102, as shown inFIG. 13B, an opening to expose the terminal electrode107is formed in the gate insulating film2and the protective insulating film5. In addition, the dry etching was actually performed and it was found that each of the organic planarized film6in the display region101and the organic planarized film6bin the frame region102was thinned by about 0.4 μm.

Here, in the process of forming the contact hole in the protective insulating film5and the gate insulating film2, an etching mask formed in a different photolithography process may be used without using the organic planarized film6as the etching mask. However, in this case, the different photolithography process is added to the production process, which increases the cost. Furthermore, a size of the contact hole needs to be larger in anticipation of displacement that could be generated when the etching mask is formed, which could deteriorate display characteristics. Therefore, with a view to ensuring a proper size of the contact hole, and reducing the number of photolithography processes and the cost, it is preferable to use the organic planarized film6as the etching mask.

Then, a first transparent conductive film is formed, for example, by sputtering on the whole surface of the transparent insulating substrate100having the contact hole61and the like. The first transparent conductive film may be made of IZO or ITO, for example. Then, a photoresist is patterned in a fifth photolithography process, the first transparent conductive film is etched, and the photoresist is removed. Thus, in the display region101, the lower electrode71is formed on the organic planarized film6so as to be electrically connected to the common wiring105through the contact hole151. Furthermore, in the frame region102, a transparent conductive film72is formed so as to cover the terminal electrode107. A structure obtained through the above-described process is shown inFIGS. 14A and 14B.

Then, the interlayer insulating film8is formed, for example, by plasma CVD on the whole surface of the transparent insulating substrate100having the lower electrode71and the like. In addition, the interlayer insulating film8may be composed of a SiN film, for example. Then, a photoresist is patterned in a sixth photolithography process, the interlayer insulating film8is subjected to dry etching, and the photoresist is removed. Thus, in the display region101, the contact hole81connected to the contact hole61, and a part of the contact hole151(FIG. 3) are formed in the interlayer insulating film8, and in the frame region102, the interlayer insulating film8is completely removed. A structure obtained through the above-described process is shown inFIGS. 15A and 15B.

Here, during the dry etching of the interlayer insulating film8, the organic planarized film6bin the frame region102functions as a mask for protecting the protective insulating film5and the gate insulating film2from being damaged by the dry etching. As a result, the organic planarized film6bis removed a little, and its film thickness is reduced, so that it becomes the organic planarized film6ashown inFIG. 6. Furthermore, the transparent conductive film72protects the terminal electrode107from being damaged by the dry etching.

The surface of the transparent insulating substrate100not having the organic planarized film6aand the transparent conductive film72is removed a little due to the damage by the dry etching, but this does not affect display performance and not damage reliability of the liquid crystal display panel1. Here, it is to be noted that in order to prevent the organic planarized film6bfrom being completely removed by the dry etching, it is necessary to appropriately set the film thickness of the organic planarized film6, and appropriately adjust the exposure amount in the fourth photolithography process in advance.

Then, a second transparent conductive film is formed, for example, by sputtering on the whole surface of the transparent insulating substrate100having the etched interlayer insulating film8. The second transparent conductive film may be made of IZO or ITO, for example. Then, a photoresist is patterned in a seventh photolithography process, and the second transparent conductive film is etched. A structure obtained by the etching is shown inFIGS. 16A and 16B. Thus, in the display region101, the upper electrode91having slits91ais formed on the interlayer insulating film8(above the lower electrode71) so as to be electrically connected to the drain electrode through the contact hole141. Furthermore, in the frame region102, a transparent conductive film92is formed so as to cover the transparent conductive film72.

Then, in the display region101, a photoresist95on the upper electrode91is removed. In this removing process, the organic planarized film6aformed above the external wiring117is not removed. Therefore, in the case where only the removing process is performed, as shown inFIG. 6, the liquid crystal display panel1is completed with the organic planarized film6aleft above the external wiring117. Here, an upper portion of the photoresist95, and the organic planarized film6aabove the external wiring117in the frame region102may be removed by ashing prior to the removing process of the photoresist95. In this case, as shown inFIG. 7, the completed liquid crystal display panel1does not have the organic planarized film above the external wiring117. In this ashing process, for example, removing speed is preferably on the order of 300 nm/min or more. In addition, the timing to perform the ashing process is not limited to the above, and the organic planarized film6amay be removed by ashing before the second transparent conductive film is formed.

According to the liquid crystal display panel1in the first preferred embodiment described above, the organic planarized film is not disposed above the external wiring117, or the organic planarized film6athinner than the organic planarized film6disposed in the display region101is disposed in the frame region102. Therefore, a difference between the height of the laminated structure including the terminal electrode107and the height of the laminated structure including the external wiring117(height difference) can be small. Thus, pressure bonding between the terminal electrode107and the external element with the ACF sandwiched between them is not hindered by the organic planarized film6, so that the terminal electrode107and the external element can be surely connected. As a result, a contact defect can be prevented, and yield and reliability can be enhanced. Furthermore, in the etching process of the protective insulating film5and the like (FIGS. 13A and 13B), and the etching process of the interlayer insulating film8(FIGS. 15A and 15B), the protective insulating film5can be protected with the organic planarized film6b. Therefore, the protective insulating film5can be prevented from being damaged, so that the protective insulating film5can keep protecting the external wiring117, and as a result, the external wiring117can be prevented from being damaged and corroded.

As described in the first preferred embodiment, in the development process of the organic planarized film6(FIGS. 12A and 12B) and in the dry etching process of the protective insulating film5and the like (FIGS. 13A and 13B), the organic planarized films6and6babove the external wiring117are thinned to some extent. However, the organic planarized films6and6bare removed too much depending on a variation in production, so that the protective insulating film5formed above the external wiring117could be partially or wholly exposed during the dry etching process of the protective insulating film5and the like (FIGS. 13A and 13B).

In this case, a surface of the protective insulating film5has been damaged or a residue of the organic planarized film6bhas been attached on that surface in the process of forming the interlayer insulating film8(fromFIGS. 14A and 14Bto15A and15B), which deteriorates an adhesion property between the protective insulating film5and the interlayer insulating film8. As a result, the interlayer insulating film8could come off or be peeled from the surface of the protective insulating film5.

Thus, according to a second preferred embodiment of the present invention, after the interlayer insulating film8has been formed on the whole surface of the transparent insulating substrate100having the lower electrode71and the like, the interlayer insulating film8is patterned in the frame region102so as to cover a laminated structure121including the external wiring117, the gate insulating film2, the protective insulating film5, and the organic planarized film6b. In addition, here, it is assumed that the organic planarized film6above the external wiring117has been removed by about 1 μm during the fourth photolithography process.

FIG. 17is a cross-sectional view illustrating a terminal configuration according to the second preferred embodiment. According to the second preferred embodiment, the protective insulating film5is protected sufficiently, and the interlayer insulating film8is disposed to cover the laminated structure121including the external wiring117, the gate insulating film2, the protective insulating film5, and the organic planarized film6b.Thus, the interlayer insulating film8can be prevented from being peeled from the protective insulating film5. In addition, the interlayer insulating film8protects the external wiring117, so that the external wiring117can be more prevented from being damaged and corroded.

Furthermore, the laminated structure121shown inFIG. 17includes the organic planarized film6b, but in the case where the organic planarized film6bhas been already removed in the dry etching process of the protective insulating film5(FIGS. 13A and 13B), the laminated structure121does not include the organic planarized film6b.

<Variation of First Preferred Embodiment and Second Preferred Embodiment>

The present invention can be applied not only to the terminal mounted region, but also to a region in which the organic planarized film6is to be thinned or removed in the frame region102of the liquid crystal display panel1, or on the transparent insulating substrate100before the liquid crystal display panel1is divided individually. Furthermore, a structure and a production method generally provided with an amorphous silicon semiconductor or a polycrystalline silicon semiconductor can be applied to the above-described thin film transistor106. In other words, the present invention can be applied to any thin film transistor106as long as the organic planarized film6is formed above the thin film transistor106.

Furthermore, the liquid crystal display panel using the display panel according to the present invention has been described in the above, as an example. However, the display panel according to the present invention is not limited to it, and may be used as an organic electroluminescence (EL) panel including a planarized film.