Stopping an etch in a planar layer after etching a 3D structure

A method of etching including providing a plurality of nanostructures extending away from a support, the support comprising a dielectric layer located between the plurality of nanowires, forming a patterned mask over a first portion of the plurality of nanostructures, such that a second portion of the plurality of nanostructures are exposed and are not located under the patterned mask, etching the second portion of the plurality of nanostructures to remove at least a portion of the patterned mask and the second portion of the plurality of nanostructures, monitoring at least one gaseous byproduct of the etching of the plurality of nanostructures during the etching of the plurality of nanostructures and stopping the etching on detecting that the dielectric layer is substantially removed.

BACKGROUND

Nanowire light emitting diodes (LED) are of increasing interest as an alternative to planar LEDs. In comparison with LEDs produced with conventional planar technology, nanowire LEDs offer unique properties due to the three-dimensional nature of the nanowires, improved flexibility in materials combinations due to less lattice matching restrictions and opportunities for processing on larger substrates.

SUMMARY

Embodiments are drawn to a method of etching including providing a plurality of nanostructures extending away from a support, the support comprising a dielectric layer located between the plurality of nanowires, forming a patterned mask over a first portion of the plurality of nanostructures, such that a second portion of the plurality of nanostructures are exposed and are not located under the patterned mask, etching the second portion of the plurality of nanostructures to remove the second portion of the plurality of nanostructures, monitoring at least one gaseous byproduct of the etching of the plurality of nanostructures during the etching of the plurality of nanostructures and stopping the etching on detecting that the dielectric layer is substantially removed.

DETAILED DESCRIPTION

The embodiments of the invention are directed generally to methods of fabricating nanowire semiconductor devices, such as nanowire LED devices, that include forming an insulating layer on a nanowire array to planarize the array, and removing a portion of the insulating layer to define an active region of a nanowire device. Further embodiments are directed to nanowire devices fabricated in accordance with the embodiment methods. The various embodiments may provide a nanowire device with planarized bond pad areas with fewer process steps and a larger active region than can be accomplished using a conventional dry etch active region definition.

In the art of nanotechnology, nanowires are usually interpreted as nanostructures having a lateral size (e.g., diameter for cylindrical nanowires or width for pyramidal or hexagonal nanowires) of nano-scale or nanometer dimensions, whereas its longitudinal size is unconstrained. Such nanostructures are commonly also referred to as nanowhiskers, one-dimensional nano-elements, nanorods, nanotubes, etc. Nanowires can have a diameter or width of up to about 2 micron. The small size of the nanowires provides unique physical, optical and electronic properties. These properties can for example be used to form devices utilizing quantum mechanical effects (e.g., using quantum wires) or to form heterostructures of compositionally different materials that usually cannot be combined due to large lattice mismatch. As the term nanowire implies, the one dimensional nature may be associated with an elongated shape. Since nanowires may have various cross-sectional shapes, the diameter is intended to refer to the effective diameter. By effective diameter, it is meant the average of the major and minor axis of the cross-section of the structure.

All references to upper, top, lower, downwards etc. are made as considering the substrate being at the bottom and the nanowires extending upwards from the substrate. Vertical refers to a direction perpendicular to the plane formed by the substrate and horizontal to a direction parallel to the plane formed by the substrate. This nomenclature is introduced for the ease of understanding only, and should not be considered as limiting to specific assembly orientation etc.

Any suitable nanowire LED structure as known in the art may be used in the methods of the invention. Nanowire LEDs are typically based on one or more pn- or p-i-n-junctions. The difference between a pn junction and a p-i-n-junction is that the latter has a wider active region. The wider active region allows for a higher probability of recombination in the i-region. Each nanowire comprises a first conductivity type (e.g., n-type) nanowire core and an enclosing second conductivity type (e.g., p-type) shell for forming a pn or pin junction that in operation provides an active region for light generation. While the first conductivity type of the core is described herein as an n-type semiconductor core and the second conductivity type shell is described herein as a p-type semiconductor shell, it should be understood that their conductivity types may be reversed.

FIG. 1schematically illustrates the basis for a nanowire LED structure that is modified in accordance with embodiments of the invention. In principle, one single nanowire is enough for forming a nanowire LED, but due to the small size, nanowires are preferably arranged in arrays comprising hundreds, thousands, tens of thousands, or more, of nanowires side by side to form the LED structure. For illustrative purposes the individual nanowire LED devices will be described herein as being made up from nanowire LEDs1having an n-type nanowire core2and a p-type shell3at least partly enclosing the nanowire core2and an intermediate active region4, which may comprise a single intrinsic or lightly doped (e.g., doping level below 1016cm−3) semiconductor layer or one or more quantum wells, such as 3-10 quantum wells comprising a plurality of semiconductor layers of different band gaps. However, for the purpose of embodiments of the invention nanowire LEDs are not limited to this. For example the nanowire core2, the active region4and the p-type shell3may be made up from a multitude of layers or segments. In alternative embodiments, only the core2may comprise a nanostructure or nanowire by having a width or diameter below 2 micron, while the shell3may have a width or diameter above one micron.

The III-V semiconductors are of particular interest due to their properties facilitating high speed and low power electronics and optoelectric devices such as lasers and light emitting diodes (LEDs). The nanowires can comprise any semiconductor material, and suitable materials for the nanowire include but are not limited to: GaAs (p), InAs, Ge, ZnO, InN, GaInN, GaN AlGaInN, BN, InP, InAsP, GaInP, InGaP:Si, InGaP:Zn, GaInAs, AlInP, GaAlInP, GaAlInAsP, GaInSb, InSb, Si. Possible donor dopants for e.g. GaP are Si, Sn, Te, Se, S, etc, and acceptor dopants for the same material are Zn, Fe, Mg, Be, Cd, etc. It should be noted that the nanowire technology makes it possible to use nitrides such as GaN, InN and AlN, which facilitates fabrication of LEDs emitting light in wavelength regions not easily accessible by conventional technique. Other combinations of particular commercial interest include, but are not limited to GaAs, GaInP, GaAlInP, GaP systems. Typical doping levels range from 1018to 1020cm−3. A person skilled in the art is though familiar with these and other materials and realizes that other materials and material combinations are possible.

Preferred materials for nanowire LEDs are III-V semiconductors such as a III-nitride semiconductor (e.g., GaN, AlInGaN, AlGaN and InGaN, etc.) or other semiconductor (e.g., InP, GaAs). In order to function as a LED, the n-side and p-side of each nanowire LED1has to be contacted, and the present invention provides methods and compositions related to contacting the n-side and the p-side of the nanowires in a LED structure.

Although the exemplary fabrication method described herein preferably utilizes a nanowire core to grow semiconductor shell layers on the cores to form a core-shell nanowire, as described for example in U.S. Pat. No. 7,829,443, to Seifert et al., incorporated herein by reference for the teaching of nanowire fabrication methods, it should be noted that the invention is not so limited. For example, in alternative embodiments, only the core may constitute the nanostructure (e.g., nanowire) while the shell may optionally have dimensions which are larger than typical nanowire shells. Furthermore, the device can be shaped to include many facets, and the area ratio between different types of facets may be controlled. This is exemplified by the “pyramid” facets and the vertical sidewall facets. The LEDs can be fabricated so that the emission layer formed on templates with dominant pyramid facets or sidewall facets. The same is true for the contact layer, independent of the shape of the emission layer.

FIG. 2illustrates an exemplary structure that provides a support for the nanowires. By growing the nanowires1on a growth substrate5, optionally using a growth mask, or dielectric masking layer,6(e.g., a nitride layer, such as silicon nitride dielectric masking layer) to define the position and determine the bottom interface area of the nanowires1, the substrate5functions as a carrier for the nanowires1that protrude from the substrate5, at least during processing. The bottom interface area of the nanowires comprises the root area of the core2inside each opening in the dielectric masking layer6. The substrate5may comprise different materials, such as III-V or II-VI semiconductors, Si, Ge, Al2O3, SiC, Quartz, glass, etc., as discussed in Swedish patent application SE 1050700-2 (assigned to GLO AB), which is incorporated by reference herein in its entirety. Other suitable materials for the substrate include, but are not limited to: GaAs, GaP, GaP:Zn, GaAs, InAs, InP, GaN, GaSb, ZnO, InSb, SOI (silicon-on-insulator), CdS, ZnSe, CdTe. In one embodiment, the nanowire cores2are grown directly on the growth substrate5.

Preferably, the substrate5is also adapted to function as a current transport layer connecting to the n-side of each nanowire LED1. This can be accomplished by having a substrate5that comprises a semiconductor buffer layer7arranged on the surface of the substrate5facing the nanowire LEDs1, as shown inFIG. 2, by way of example a III-nitride layer, such as a GaN and/or AlGaN buffer layer7on a Si substrate5. The buffer layer7is usually matched to the desired nanowire material, and thus functions as a growth template in the fabrication process. For an n-type core2, the buffer layer7is preferably also doped n-type. The buffer layer7may comprise a single layer (e.g., GaN), several sublayers (e.g., GaN and AlGaN) or a graded layer which is graded from high Al content AlGaN to a lower Al content AlGaN or GaN. The growth of nanowires can be achieved by utilizing methods described in the U.S. Pat. Nos. 7,396,696, 7,335,908, and 7,829,443, and WO201014032, WO2008048704 and WO 2007102781, all of which are incorporated by reference in their entirety herein.

It should be noted that the nanowire LEDs1may comprise several different materials (e.g., GaN core, GaN/InGaN multiple quantum well active region and AlGaN shell having a different Al to Ga ratio than the active region). In general the substrate5and/or the buffer layer7are referred to herein as a support or a support layer for the nanowires. In certain embodiments, a conductive layer (e.g., a mirror or transparent contact) may be used as a support instead of or in addition to the substrate5and/or the buffer layer7. Thus, the term “support layer” or “support” may include any one or more of these elements.

The use of sequential (e.g., shell) layers gives that the final individual device (e.g., a pn or pin device) may have a shape anywhere between a pyramid or tapered shape (i.e., narrower at the top or tip and wider at the base) and pillar shaped (e.g., about the same width at the tip and base) with circular or hexagonal or other polygonal cross section perpendicular to the long axis of the device. Thus, the individual devices with the completed shells may have various sizes. For example, the sizes may vary, with base widths ranging from 100 nm to several (e.g., 5) μm, such as 100 nm to below 2 micron, and heights ranging from a few 100 nm to several (e.g., 10) μm.

The above description of an exemplary embodiment of a LED structure will serve as a basis for the description of the methods and compositions of the invention; however, it will be appreciated that any suitable nanowire LED structure or other suitable nanowire structure may also be used in the methods and compositions, with any necessary modifications as will be apparent to one of skill in the art, without departing from the invention.

Nanowire LEDs, such as GaN-based nanowire LEDs, show promise in increasing the efficiency and wavelength stability compared to planar LEDs. However, the three-dimensional nature of nanowires can pose challenges in fabrication, notably the wire bonding step where the LED device (i.e., chip) is connected to an external current/voltage source. The wire bonding step involves application of mechanical pressure and vibration from the wire to the device. This pressure and vibration of the wire bonding process can break nanowires due to the leverage from the pressure point at the top of the wire to the weak small nucleation base of the nanowire. Therefore, in areas where a wire will be bonded to the device, it is desirable to planarize the area to avoid developing a lever arm that can break the nanowires.

The fabrication process of a nanowire LED typically also involves defining the active region of a device. This is usually accomplished by a dry etch of a nearly-completed device, which results in a break in the continuity of either the n- or p-side conductive layers, resulting in isolated devices. Alternatively, the nanowires may be etched prior to conductive film deposition (e.g., the top electrode or contact deposition) to define the active region. However, if nanowires are etched prior to conductive film deposition, there will typically be some nanowires that are partially etched, requiring the deposition of a passivating film prior to depositing the conductive film to avoid shorting the exposed p-n junction. This passivation film must be separately masked and etched, which then consumes some of the active region to allow for the transition region to be sufficiently isolated from conductive film deposition.

Various embodiments include methods for fabricating nanowire semiconductor devices, such as nanowire LED devices, that include forming an insulating layer, such as a low temperature oxide (LTO) layer, on a nanowire array to planarize the array, and removing a portion of the insulating layer, such as by wet etching through a patterned mask, to define an active region of a nanowire device. Further embodiments are directed to nanowire devices fabricated in accordance with the embodiment methods. The various embodiments may provide a nanowire device with planarized bond pad areas with fewer process steps and a larger active region than can be accomplished using a conventional dry etch active region definition.

FIG. 3Ais a scanning electric microscopy (SEM) micrograph illustrating a failed wire bond on GaN nanowires1. As can be seen in the micrograph ofFIG. 3A, many of the nanowires1are broken. Further, the micrograph evidences failure of adhesion of the ball bond (not shown) to the metal pad on8the GaN nanowires. That is, much of the metal pad8is attached to the nanowires1but the ball bond has separated from the metal pad8.

FIG. 3Bis a SEM micrograph illustrating etching of the substrate while etching the nanowires during fabrication of an LED device. The SEM micrograph ofFIG. 3Bwas taken at a higher magnification than that ofFIG. 3A. As can be seen inFIG. 3B, etching of the nanowires during device fabrication without providing a material filling the spaces in between the nanowires causes the substrate to be etched. It is believed that this etching of the substrate resulting in a non-planar surface is a contributing factor in the failure of ball bond adhesion.

FIG. 3Cis a SEM micrograph illustrating nanowires before etching. Visible inFIG. 3Care the unetched GaN nanowires and a dielectric mask layer6, such as a SiN (i.e., stoichiometric or non-stoichiometric silicon nitride), between the GaN nanowires.FIG. 3Dis a SEM micrograph illustrating etching of nanowires and the underlying buffer layer7due to overetching. When this occurs, the sidewalls orthogonal to the plane of the wafer are exposed, making contact by a subsequently PVD deposited film difficult.FIG. 3Eillustrates the use of a dielectric mask layer6, such as an etch stop to prevent etching of the underlying buffer layer7. As can be seen in on the left side ofFIG. 3E, absent a dielectric mask, the underlying buffer layer7is overetched. However, on the right side ofFIG. 3E, stopping the etch after removal of the dielectric mask layer6prevent buffer layer7from being overetched. Unetched GaN nanowires1are visible in the background.

An embodiment of a method for fabricating a nanowire device is schematically illustrated inFIGS. 4A-4Jand5A-5E.FIG. 4Aschematically illustrates a nanowire LED device400that includes a plurality of nanowires401, a buffer layer407and a dielectric masking layer406(e.g., SiN layer), as described above in connection withFIGS. 1 and 2. The nanowires401may each comprise a nanowire core of a first conductivity type (e.g., n-type), a shell of a second conductivity type (e.g., p-type), and an intermediate light-generating active region, as described above in connection withFIGS. 1 and 2. The nanowire cores may be in electrical contact with the buffer layer407, and the nanowire shells may be insulated from the buffer layer by the dielectric masking layer406, as described above.

InFIG. 4B, a first mask layer412, which may be a photoresist layer, is formed over the nanowires401. The first mask layer412may be patterned using standard lithographic techniques to cover the nanowires401in an active region413of the device400, and to define exposed regions421,415. The device400may be etched to transfer the pattern of the first mask layer412to the device400. The etch may be a dry etch (e.g., an inductively coupled plasma (ICP) etch), which may utilize a chlorine gas plasma. The exposed nanowires401are removed to “flatten” the device in regions415and421and to expose the masking layer406in these regions415,421, as shown inFIG. 4C. If desired, the masking layer406in regions415,421may also be removed to expose the support (e.g. buffer layer407). These “flattened” regions may later be used to form electrical contacts, as described below. Following the etch, the first mask layer412may be removed to provide the device400as shown inFIG. 4C.FIG. 5Ais a top view of the device400after etching and removal of the patterned first mask layer412. Line E-E′ inFIG. 5Acorresponds to line E-E′ inFIG. 4C, though the device400is not necessarily shown to scale.

FIGS. 6A-6Cillustrate details of a first embodiment for the masking and etching steps illustrated inFIGS. 4B and 4C. In this embodiment, rather than remove the entire first mask layer412from around the nanowires401as illustrated inFIG. 4C, the method ofFIGS. 6A-6Cresults in a portion614of the first mask layer412remaining in the spaces between the nanowires401. In a first step as illustrated inFIG. 6A, a relatively thick first mask layer412of a flowable material, such as a photoresist material, is deposited over the nanowires401. The photoresist is patterned by exposing the photoresist through a photolithography mask602with radiation604, such as optical or ultraviolet (UV) radiation. Electron beam photolithography may be used instead. As illustrated inFIG. 6A, an upper portion606of the photoresist is exposed by the radiation604, while a lower portion608and upper portion610under mask602of the photoresist remain unexposed. The unexposed central portion612of the lower portion608of the photoresist is located under the unexposed upper portion610.

As illustrated inFIG. 6B, the exposed portions606of the photoresist may then be removed, such as by dissolving in a solvent or by reacting with oxygen (“ashing”). The lower, unexposed portions608and upper portion610of the first mask layer412shielded by the photolithography mask602remain after removal of portions606. This photoresist structure608,610may then be etched, such as by an anisotropic dry etching process which etches the resist and the nanowires at about the same rate. As illustrated inFIG. 6C, the upper portion610and the lower portions608of the photoresist as well as the nanowires401embedded in the lower portions608of the photoresist are removed by the etching to define exposed regions415and421. The remaining nanowires401are embedded in a layer612photoresist material.

FIGS. 7A-7Cillustrate details of a second embodiment for the masking and etching steps illustrated inFIGS. 4B and 4C. In this embodiment, a first flowable material712is deposited between the nanowires401as illustrated inFIG. 7A. As illustrated inFIG. 7B, a photoresist layer is deposited on top of the first flowable material712and patterned to leave a pattern710. The first flowable material712and the nanowires401embedded in the first flowable material712are etched using the photoresist pattern710as a mask. When etching is complete, the remaining photoresist710can be striped to form the structure illustrated inFIG. 7Cin which the remaining nanowires401are embedded in a remaining portion712A of the layer of flowable material712, which was covered by photoresist pattern710, surrounded by exposed regions415and421.

FIGS. 8A-8Cillustrate details of a third embodiment for the masking and etching steps illustrated inFIGS. 4B and 4C. In a first step illustrated inFIG. 8A, a first photoresist layer812is deposited over the nanowires401and patterned. A second photoresist layer810is deposited over the first photoresist layer812. Portions814of device in which the first photoresist layer812was removed are covered with the second photoresist layer810while the nanowires401outside of portions814are covered by both the first photoresist layer812and the second photoresist layer810. The resulting structure is illustrated inFIG. 8B. This structure may now be dry etched. The portion of the second photoresist layer810above the patterned first photoresist layer812is removed as the nanowires401and the surrounding second photoresist layer810are removed similar to the method illustrated inFIGS. 6B,6C. The final structure is illustrated inFIG. 8C(which is similar toFIG. 6C).

Thus, in the embodiment illustrated inFIGS. 6A-6C, a single photoresist is partially exposed as a function of thickness. In the embodiment illustrated inFIGS. 8A-8C, two photoresist layers are used. In the embodiment illustrated inFIGS. 7A-7C, a photoresist and other flowable layers are used.

FIGS. 9A-9Cillustrate details of a fourth embodiment for the masking and etching steps illustrated inFIGS. 4B and 4C. In this embodiment a first layer of flowable material912, such as a photoresist or a spin on glass is deposited over and between the nanowires401. A second layer of a photoresist is deposited over the first layer of flowable material912and patterned to form the structure910illustrated inFIG. 9B. This structure is then dry etched to remove the nanowires401with an etchant that does not remove the portion of the photoresist layer910as illustrated inFIG. 9C. After removing the nanowires401and the unprotected first layer of flowable material912, the remaining photoresist910may be removed to leave nanowires401fully embedded in first layer of flowable material912that was protected by the photoresist910. Optionally, a portion of the first layer of flowable material912(e.g. a spin on glass) between the nanowires401may be recessed to leave a reduced thickness layer916of flowable material912between the nanowires401, such that nanowires401tips are exposed above layer916. Optionally, the step of removing a portion of the first layer of flowable material912may be performed with any of the preceding embodiments.

Returning toFIG. 4D, a dielectric layer409is formed over the device, including over the nanowires401in active region413and over the “flattened” regions415,421in which the nanowires have been removed. The dielectric layer409may be a SiO2layer and may be formed by low temperature oxide (LTO) deposition. LTO deposition may be accomplished by chemical vapor deposition (CVD) at low temperature (e.g., less than 750° C., such as 300-400° C., including 400-500° C., or about 450° C.), and at sub-atmospheric pressure, such as 10 Torr or less (e.g., 10−6Torr to 1 Torr, such as 100-500 mTorr, including about 450 mTorr), with flows of SiH4and O2. The O2flow may be in excess of the SiH4flow in standard cubic cm per minute (sccm). Typical flow rates may be, for example, 85 sccm SiH4and 120 sccm O2.

The dielectric layer409may be deposited with an average thickness of 0.01-10 μm (e.g., 0.1 to 1 μm, such as about 0.4 μm) over the device400. A second mask layer414, which may be a photoresist layer, is formed over the dielectric layer409. The second mask layer414may be patterned using standard lithographic techniques to define an opening in the second mask layer414corresponding with the active region413of the device300. The device300may then be etched to transfer the pattern of the second mask layer414to the dielectric layer409. In embodiments, the dielectric layer409, which may be SiO2, may be etched using a wet etch of diluted hydrofluoric acid (HF) to remove the dielectric layer409from the active region413of the device. A typical concentration for a wet etch solution may be, for example, 1 part HF to 3 parts H2O. A HF etch may remove select portions of dielectric layer409while leaving the nanowires401in the active region413undisturbed.

After etching, the second mask layer414may be removed to provide the device400shown inFIG. 4E.FIG. 5Bis a top view of the device400after etching and removal of the patterned second mask layer414. Line F-F′ inFIG. 5Bcorresponds to line F-F′ inFIG. 4E, though the device400is not necessarily shown to scale. The dielectric layer409is removed from the active region413of the device400. The dielectric layer409may extend around a periphery of the active region413to define the boundary of the active region413, as shown inFIG. 5B. The dielectric layer409may provide a generally planar top surface over the “flattened” portions415,421of the device400, and may electrically isolate the top surface of the “flattened” portions415,421from the rest of the device. (The circle422inFIG. 5Bindicates the future location of the n-side contact429, described below).

An acid clean may be performed of the device400and a transparent conductive oxide (TCO) layer419, such as an indium tin oxide (ITO) layer, may be deposited over the device400, including over the nanowires401in the active region413and over the dielectric layer409in the “flattened” regions421,415, as shown inFIG. 4F. The TCO layer419may contact the p-type shells of the nanowires301to form a p electrode or contact layer. Other TCO materials such as aluminum doped zinc oxide can also be used. The TCO layer419may be deposited by physical methods such as evaporation or sputtering, by CVD, or by a combination of methods. In some embodiments, the layer419may be deposited by a sputtering method that preferably does not damage the p-type nanowire shells. The ITO layer419can be about 100 Å to about 10,000 Å thick, most preferably about 8,000 Å.

A third mask layer416, which may be a photoresist layer, is formed over the TCO layer419and may be patterned using standard lithographic techniques to define an opening423in the third mask layer416, as shown inFIG. 4F. The opening423in the third mask layer416defines an n-side contact area423within the “flattened” portion421of the device400. The opening423in the third mask layer416also defines the entire edge periphery of the device. The device400may then be etched to transfer the pattern of the third mask layer416to the device400. The etching may stop at or in the buffer layer407of the device400to expose then n-type buffer layer material in the n-side contact area423(e.g., form a “mesa” structure). The etch may be a dry etch or a wet etch. In one embodiment, a dry etch is used, such as an inductively coupled plasma (ICP) etch, which may utilize a chlorine gas plasma. Chlorine gas will etch SiO2, ITO, SiN and GaN. Following the etch, the third mask layer416is removed to provide the device400as shown inFIG. 4G.FIG. 5Cis a top view of the device400after etching and removal of the patterned third mask layer416. Line G-G′ inFIG. 5Ccorresponds to line G-G′ inFIG. 4G, though the device400is not necessarily shown to scale. As shown inFIG. 5C, for example, the n-side contact area423may be located in the “flattened” region in the lower left hand corner of the device400.

A fourth mask layer418, which may be a photoresist layer, is formed over the device400and may be patterned using standard lithographic techniques to provide a first opening425over the n-side contact area421, and a second opening427over the “flattened” area415, as shown inFIG. 4H. The openings425,427in the fourth mask layer418define the locations for the n- and p-metal contacts, respectively. The opening425for the n-side metal contact may be smaller than the n-side contact area423to isolate the n-side metal contact from the exposed TCO layer419and any partially-etched nanowires401. A metal contact stack, which can include Al, Ti, and Au, may then be deposited by evaporation over the fourth mask layer418and within the openings425,427. The metal stack may be deposited with a thickness of 1-10 μm (e.g., 2-4 μm, such as about 3.3 μm). The metal contact stack may be deposited in the order of aluminum first and gold last, with gold being the film on the surface, where gold does not require thermal processing to make a good ohmic contact. The fourth mask layer418with the deposited metal is then removed (e.g., lifted off the device) to leave n- and p-metal contacts429,431on the device400as shown inFIG. 4I.FIG. 5Dis a top view of the device400after metal deposition and removal (e.g., lift off) of the patterned fourth mask layer418. Line H-H′ inFIG. 5Dcorresponds to line H-H′ inFIG. 4I, though the device400is not necessarily shown to scale.

A fifth mask layer420may then be formed over the device400, as shown inFIG. 4J. The fifth mask layer420may be an SiO2layer masked with a photoresist, which may be used to passivate the device400. The fifth mask layer420may have an average thickness of 5-25 μm (e.g., 10-20 μm, such as about 15 μm). The photoresist of the fifth mask layer420may be processed and developed using standard photolithography techniques. The SiO2layer may be wet or dry etched to remove the fifth mask layer420from an area around the n-metal and p-metal electrodes429,431, as shown inFIG. 4J. The fifth mask layer420may remain over the active region of the device400.FIG. 5Eis a top view of the device400illustrating the fifth mask layer420and n-metal and p-metal electrodes429,431. Line I-I′ inFIG. 5Ecorresponds to line I-I′ inFIG. 4J, though the device300is not necessarily shown to scale. Wires433,435may be bonded to the n-metal and p-metal electrodes429,431, as shown inFIG. 4J.

FIGS. 10A-10Care SEM micrographs showing etched and unetched nanowires protected by photoresist made according to an embodiment of the method.FIG. 10Aillustrates a cross section through a wafer. The nanowires401on the left side of the figure were protected during etching with a photolithographically formed etch mask.FIG. 10Billustrates the same embodiment at a 30° tilt and a higher magnification. As in theFIG. 10A, the nanowires401on the left side of the figure were protected while the nanowires401on the right have been removed.FIG. 10Cis a close up of the right, unprotected side of the wafer.FIG. 10Cdemonstrates that the nanowires can be removed with little or no etching of the buffer layer7.

FIG. 11is a cross sectional scanning electron microscope (XSEM) micrograph of a metal contact on an area where nanowires have been etched. The XSEM micrograph clearly illustrates the GaN buffer layer7, the SiO2layer409on the buffer layer7, the ITO layer419covering the nanowires401and the metal bond pad8over the ITO layer419.

FIGS. 12A-Care scanning electron microscope (SEM) images of a GaN-based nanowire array1201having a patterned dielectric layer1209, which may be a low temperature oxide (LTO), such as SiO2, formed over the array1201in accordance with the embodiment described above in connection withFIGS. 4A-5E.FIG. 12Ais a cross-sectional SEM image of the array1201after deposition of the dielectric layer1209(i.e., LTO).FIG. 12Bis a tilt SEM image of a p contact area after deposition a metal contact pad1231with the photoresist stripped.FIG. 12Cis a cross-sectional SEM image of a p contact area outside of the metal contact pad. As shown inFIG. 12C, the p contact area is “flattened” relative to the nanowires1201, the dielectric layer1209(LTO, such as SiO2) insulates the underlying n-GaN layer1207from the p-electrode layer1219(ITO) above, and the p-electrode layer connects the metal contact1231with the p-GaN shells of the nanowires1201.

FIGS. 13A-13Care side cross sectional views illustrating an embodiment of a method of determining when to stop an etch. The method illustrated inFIGS. 13A-13Cmay be used, for example, in conjunction with the process for fabricating a nanowire LED array illustratedFIGS. 4A-4J, specificallyFIGS. 4A-4C. The nanowire LED device illustrated inFIG. 13Aincludes nanowires401grown on a planar electrically active material (e.g. GaN buffer layer)407. The nanowires401are grown through holes in an electrically insulating (e.g. SiN) masking layer406on the planar electrically active material407.

As illustrated inFIG. 13B, a first mask layer412, which may be a photoresist layer, is formed over the nanowires401. The first mask layer412may be patterned using standard lithographic techniques to cover the nanowires401in an active region413of the device400, and to define exposed regions421,415. The device400(e.g. nanowires and masking layer) may be etched to transfer the pattern of the first mask layer412to the device400. The etch may be a dry etch (e.g., an inductively coupled plasma (ICP) etch), which may utilize a chlorine gas plasma.

The exposed nanowires401are removed to “flatten” the device in regions415and421, as shown inFIG. 13C. In this embodiment, in contrast to the method illustrated inFIG. 4C, a sensor1302, such as an optical sensor, is included to monitor the progress of the etching step. In an embodiment, the optical sensor1302detects gaseous byproducts of the etching process, such as through optical emission spectroscopy (OES). For example, in a GaN system, OES may be used to detect gaseous gallium as GaN, AlGaN and/or InGaN containing nanowires are etched during a plasma dry etch.

FIG. 14illustrates the results of monitoring an etch using optical emission spectroscopy. A plasma etch is used to etch unprotected GaN nanowires401on a GaN planar layer407. The OES method is used to determine the progress of the etching and to determine if the silicon nitride masking layer406, which lacks gallium, had been etched. As can be seen inFIG. 14, the optical sensor1302detects a steady count of gallium as the GaN nanowires are etched. When the nanowires are completely etched, the gallium count drops rapidly as the etch reaches the SiN masking layer406. Thereafter, the gallium count remains low until the etching penetrates the SiN masking layer406and begins to etch the underlying GaN planar buffer layer407(i.e., if the silicon nitride masking layer406is substantially removed and the gallium containing III-nitride semiconductor surface, such as the GaN buffer layer407, is exposed to the plasma). Once the etching penetrates the SiN masking layer, the gallium count rapidly rises as the GaN planar layer407is etched.

Based on the results illustrated inFIG. 14, the etch step may be modified to include monitoring with a sensor1302to determine when the SiN masking layer406and the GaN buffer layer407are reached and when etching should be stopped. The sensor1302may be connected to a controller, such as a personal computer or dedicated system controller which may be programmed to automatically halt etching when it is determined the SiN mask layer406is mostly or completely removed (e.g. after the OES gallium count drops and then increases again). In this manner, the amount of etching of the underlying planar layer407may be minimized. Additionally, the formation of vertical sidewall features in the underlying planar layer407may also be reduced. Further, use of the optical sensor to control the etch step allows for use of a smaller thickness of the underlying planar layer407, thereby reducing cost and decreasing wafer bow. In other words, the planar layer407comprises a GaN, AlGaN or InGaN buffer layer located over a substrate, and the etching is stopped to minimize an amount of etching of the buffer layer, such that a thickness of the buffer layer remaining after stopping the etching is optimized to leave a sufficient thickness of the buffer layer to form an electrical contact to the buffer layer while minimizing substrate bow.

FIG. 15illustrates a schematic cross sectional view of a system1500for etching according to an embodiment. The system1500includes a sample holder1502configured to hold devices such as nanowire LED devices400, one or more etchant sources1504(e.g. inductively coupled plasma (ICP) etch plasma chamber) and a sensor1302, such as an optical sensor (e.g., photodetector, etc.). The system1500also includes a controller1506, such as a personal computer or dedicated system controller configure to control the etching process, such as by stopping the process. The controller1506may be connected to the sensor1302via a wire1508or connected wirelessly. In an embodiment, such as when using ICP, the sensor1302is separated from the sample holder1502with a wall1510to protect the sensor1302from the plasma. During the etching, the sensor1302may receive the emitted or reflected radiation (e.g., visible light, UV or IR radiation) from the device400through a window1512in the wall1510. The system ofFIG. 15and the method ofFIG. 14can be used during etching steps shown inFIGS. 6A-6C,7A-7C,8A-8C,9A-9D and13A-13C.

Although the present invention is described in terms of nanowire LEDs, it should be appreciated that other nanowire based semiconductor devices, such as field effect transistors, diodes and, in particular, devices involving light absorption or light generation, such as, photodetectors, solar cells, laser, etc., can be implemented on any nanowire structures.

In addition, although several example embodiments are described and illustrated as a top emitting nanowire LED, where light is extracted in the direction from base to the tip of the nanowire, it will be understood that embodiments may also include bottom emitting nanowire LEDs. In general, the construction of a bottom emitting nanostructure entails providing reflective structure, such as a minor, at or near i.e. adjacent the top portions of each individual light emitting nanoelement so as to direct the emitted light backwards through the buffer layer of the device. Bottom-emitting electrodes are described further in U.S. Patent Publication No. 2011/0309382, filed on Jun. 17, 2011 and PCT Application No. PCT/US11/40932, filed Jun. 17, 2011, both of which are incorporated herein by reference in their entirety.