Contact structure with silicide and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The advantages of a FinFET include a reduction of the short channel effect and a higher current flow.

Although existing FinFET manufacturing processes have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects, especially as device scaling-down continues. For example, it is a challenge to a semiconductor device structure with reduced parasitic capacitance and resistance while keeping the critical dimensional (CD) of the source/drain contact of the FinFET at smaller and smaller sizes.

DETAILED DESCRIPTION

Embodiments for manufacturing semiconductor device structures are provided. The semiconductor device structures may include a gate electrode layer and a source/drain contact structure over a semiconductor substrate and adjacent to each other. A spacer structure is formed to separate the gate electrode layer from the source/drain contact structure, in which the spacer structure includes a first spacer, a second spacer, and a third spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. A source/drain region is formed in the semiconductor substrate below the source/drain contact structure and is self-aligned to the first spacer of the spacer structure. A silicide region is formed in the source-drain region, self-aligned to the second spacer of the spacer structure and covers the bottom of the third spacer of the spacer structure. The formation of the semiconductor device structures includes forming a gate structure with the first spacer and the second spacer in an insulating layer. Afterwards, an opening is formed in the insulating layer and self-aligned to the second spacer to expose the source/drain region that is self-aligned to the first spacer. Afterwards, the silicide region is formed in the source/drain region through the opening, and then the third spacer and the source/drain contact structure are successively formed in the opening. In such a semiconductor device structure, the top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region. Therefore, the semiconductor device structure has a lower parasitic resistance (Re) induced by the silicide region than the case where the top width of the silicide region is equal to the bottom width of the source/drain contact structure. Moreover, the semiconductor device structure with a lower parasitic resistance (Re) also has a lower parasitic capacitance (Rc) between the gate electrode layer and the source/drain contact structure than the case where the top width of the silicide region less than the top width of the source/drain region.

FIGS.1A to1Dillustrate perspective views of various stages of manufacturing a semiconductor device structure.FIGS.2A to2Lillustrate cross-sectional representations of various stages of manufacturing a semiconductor device structure in accordance with some embodiments, in whichFIGS.2A to2Dillustrate the cross-sectional representations of the semiconductor device structure shown along line1-1′ inFIGS.1A to1Din accordance with some embodiments. In addition,FIGS.3A to3Iillustrate cross-sectional representations of various stages of manufacturing a semiconductor device structure in accordance with some embodiments, in whichFIG.3Aillustrates the cross-sectional representation of the semiconductor device structure shown along line2-2′ inFIG.1Din accordance with some embodiments. In some embodiments, the semiconductor device structure is implemented as a fin field effect transistor (FinFET) structure.

As shown inFIGS.1A and2A, a substrate100is provided. In some embodiments, the substrate100is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g. with a P-type or an N-type dopant) or undoped. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. In some embodiments, the substrate100is a wafer, such as a silicon wafer.

Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate100includes silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. In some embodiments, the substrate100includes silicon. In some embodiments, the substrate100includes an epitaxial layer. For example, the substrate100has an epitaxial layer overlying a bulk semiconductor.

The substrate100may have a PMOS region for P-type FinFETs formed thereon and/or an NMOS region for N-type FinFETs formed thereon. For example, the PMOS region of the substrate100may include Si, SiGe, SiGeB, or an III-V group semiconductor material (such as InSb, GaSb, or InGaSb). The NMOS region of the substrate100may include Si, SiP, SiC, SiPC, or an III-V group semiconductor material (such as InP, GaAs, AlAs, InAs, InAlAs, or InGaAs).

Afterwards, a fin structure101and an isolation structure104formed over the substrate100and adjacent to each other are provided, as shown inFIG.1Ain accordance with some embodiments. In some embodiments, the substrate100is patterned to form at least one fin structure101with slope sidewalls and extend from the patterned substrate100. In some other embodiments, one or more fin structures101are formed with substantially vertical sidewalls and extend from the patterned substrate100.

The isolation structure104is a shallow trench isolation (STI) structure, and the fin structure101is surrounded by and protruded above the isolation structure104, as shown inFIG.1Ain accordance with some embodiments. For example, the isolation structure104may be formed by depositing an insulating layer (not shown) over the substrate100. Afterwards, the insulating layer is recessed. The recessed insulating layer may be made of silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), low-K dielectric materials, and/or another suitable dielectric material and may be deposited by a flowable CVD (FCVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or another applicable process.

After the isolation structure104is formed, dummy gate stacks108a,108b,108c, and108dare formed across the fin structure101over the substrate100and cover the isolation structure104, in accordance with some embodiments. Each of the dummy gate stacks108a,108b,108c, and108dmay include a dummy gate dielectric layer110and a dummy gate electrode layer112formed over the dummy gate dielectric layer110. The dummy gate dielectric layer110may be made of silicon oxide and the dummy gate electrode layer112may be made of polysilicon.

Gate spacers (i.e., spacers114) are formed on the opposing sides (e.g., opposing sidewalls) of the dummy gate stacks108a,108b,108c, and108dafter the formation of the dummy gate stacks108a,108b,108c, and108d, in accordance with some embodiments. Each of the formed spacers114is adjacent to the corresponding dummy gate stack (e.g., the dummy gate stack108a,108b,108c, or108d). The spacer114may be used for protecting the dummy gate stacks108a,108b,108c, and108dfrom damage or loss during subsequent processes (e.g., etching processes). The spacers114may be made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or another applicable dielectric material.

After the formation of the spacers114, conductive features (such as source/drain regions116) are formed in the fin structure101adjacent to and exposed from the dummy gate stacks108a,108b,108c, and108dwith the spacers114, as shown inFIGS.1A and2Ain accordance with some embodiments. Namely, the source/drain region116is self-aligned to the spacers114formed on the sidewalls of the two adjacent dummy gate stacks. As a result, the sidewall of the spacer114is substantially aligned to the first side edge116S1of the source/drain region116extending in the longitudinal direction of the dummy gate stacks108a,108b,108c, and108d, as shown inFIG.2A. In some embodiments, the source/drain region116is formed by recessing the fin structure101exposed from the dummy gate stacks108a,108b,108c, and108dand growing semiconductor materials in the formed recesses in the fin structure101by performing epitaxial (epi) growth processes.

In some embodiments, the semiconductor device structure is an NMOS device, and the source/drain regions116include Si, SiP, SiC, SiPC, or an III-V group semiconductor material (such as InP, GaAs, AlAs, InAs, InAlAs, or InGaAs), or the like. In some other embodiments, the semiconductor device structure is a PMOS device, and the source/drain regions116include Si, SiGe, SiGeB, or an III-V group semiconductor material (such as InSb, GaSb, or InGaSb), or the like. In some embodiments, each of the source/drain regions116protrudes above the isolation structure104.

A contact etch stop layer125and an insulating layer128are successively formed over the isolation structure104after the source/drain regions116are formed, as shown inFIGS.1B and2Bin accordance with some embodiments. The contact stop layer125conformally covers the spacers114over the opposing sidewalls of the dummy gate stacks108a,108b,108c, and108d, the source/drain regions116, and the isolation structure104. The contact etch stop layer125may be used for forming contact holes (not shown) in the source/drain regions116and for protecting subsequent active gate structures from damage or loss during the subsequent processes (e.g., etching processes). The contact etch stop layer125may be made of a material that is different from that of the spacer114. For example, the contact etch stop layer125may include silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or another applicable material.

After the formation of the contact etch stop layer125, the insulating layer128is deposited to cover the contact etch stop layer125and the structure shown inFIGS.1Aand2A. Afterwards, a planarization process is performed to remove the excess insulating layer128and the contact etch stop layer125above the dummy gate stacks108a,108b,108c, and108d, in accordance with some embodiments. In some embodiments, such a planarization process (such as a chemical mechanical polishing (CMP) process) is performed on the insulating layer128until the dummy gate stacks108a,108b,108c, and108dare exposed, so that the exposed top surfaces of the dummy gate stacks108a,108b,108c, and108dare substantially level with the top surface of the remaining insulating layer128.

The remaining insulating layer128(which serves as an interlayer dielectric (ILD) layer) may be made of silicon oxide, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), or the like. The insulating layer128may be deposited by any suitable method, such as a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, flowable CVD (FCVD) process, the like, or a combination thereof. The insulating layer128may be a single layer or include multiple dielectric layers with the same or different dielectric materials.

Afterwards, the dummy gate stacks108a,108b,108c, and108dare removed and replaced by gate stacks120a,120b,120c, and120d, as shown inFIGS.1B and2Bin accordance with some embodiments. In some embodiments, each of the gate stacks120a,120b,120c, and120dat least includes a gate dielectric layer122, a gate electrode layer124. The spacers114and the portions of the contact etch stop layer125are adjacent to the corresponding gate stack.

In some embodiments, the gate dielectric layer122is made of high-k materials, such as metal oxides, metal nitrides, or other applicable dielectric materials. Moreover, the gate electrode layer124is made of a conductive material, such as aluminum, copper, tungsten, titanium, tantalum, or another applicable material. Each of the gate stacks120a,120b,120c, and120dmay further include a work function metal layer (not shown) between the gate dielectric layer122and the gate electrode layer124, so that the gate stacks120a,120b,120c, and120dhave the proper work function values. An exemplary p-type work function metal layer may be made of TiN, TaN, Ru, Mo, Al, WN, or a combination thereof. An exemplary n-type work function metal layer may be made of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, or a combination thereof.

Afterwards, the gate stacks120a,120b,120c, and120dare recessed by etching, so as to form recesses130, as shown inFIGS.1C and2Cin accordance with some embodiments. During the etching, the top of the portions of the contact etch stop layer125adjacent to the spacers114are also recessed. In some embodiments, each of the gate electrode layers124is further recessed by etching after the upper sidewalls of the insulating layer128are exposed by the recesses130, so that the recesses130are extended to form a T-shaped profile, as shown inFIG.2C. Therefore, the upper surface of the spacers114, the portions of the contact etch stop layer125adjacent to the spacers114, and the upper surface of the gate dielectric layers124are higher than the upper surface of the corresponding gate electrode layers124. As a result, the upper surface of the spacers114are higher than the upper surface of the gate stacks120a,120b,120c, and120d, as shown inFIGS.1C and2C.

In some other embodiments, an optional conductive capping layer (not shown) is formed to cover each of the recessed gate electrode layers124. The conductive capping layers and the underlying gate electrode layer124form the gate stacks120a,120b,120c, and120d. In those cases, the upper surface of each spacer114is higher than the upper surface of the conductive capping layer. The conductive capping layers may serve as etch stop layers or protective layers for protecting the gate electrode layers124from damage or loss during the subsequent processes, and be made of a metal material, such as tungsten.

Afterwards, each of insulating capping layers136a,136b,136c, and136dare formed to fill the corresponding recess130(as indicated inFIGS.1C and2C) to cover the corresponding conductive capping layer (if presented) and the corresponding gate electrode layers124, as shown inFIGS.1D and2Din accordance with some embodiments. The insulating capping layers136a,136b,136c, and136dare formed to cover the upper surfaces of the gate stacks120a,120b,120c, and120d.

In some embodiments, an insulating layer (not shown) used for formation of the insulating capping layers136a,136b,136c, and136dis formed over the structure shown inFIGS.1C and2Cand fills the recesses130. For example, the insulating layer is made of a different material than the material of the insulating layer128and includes high-k materials, such as metal oxides including ZrO2, HfO2, or SiN. The insulating layer may be formed by performing a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, low-pressure CVD (LPCVD) process, an atomic layer deposition (ALD) process, or another applicable process. Afterwards, a planarization process (e.g., a chemical mechanical polishing (CMP) process) is performed to remove the excess insulating layer above the insulating layer128in accordance with some embodiments. After the planarization process, the remaining insulating layer forms insulating capping layers136a,136b,136c, and136d, as shown inFIGS.1D and2D.

In some embodiments, the upper surfaces of the insulating capping layers136a,136b,136c, and136dare substantially level with the top surface of the insulating layer128shown inFIG.3A, as shown inFIGS.1D and2D. The insulating capping layers136a,136b,136c, and136dserve as etch stop layers and protect the gate stacks120a,120b,120c, and120din the subsequent processes (e.g., etching processes).

After the insulating capping layers136a,136b,136c, and136dare formed, the insulating layer128is patterned to form openings140in the insulating capping layers136a,136b,136c, and136d, respectively, as shown inFIGS.2E and3B. Each of the opening140exposes a portion of the source/drain region116where a silicide region is formed in the subsequent processes. In some embodiments, portions of the contact etch stop layer125exposed from the openings140are removed to expose the source/drain region116in a corresponding opening140, as shown inFIGS.2E and3B.

Portions of the remaining contact etch stop layer125that covers the spacers114form spacers126on two opposing sides of each gate electrode layer124and on two opposing sides of each opening140extending in a longitudinal direction of the gate electrode layer124, as shown inFIG.2E. The gate electrode layer124, the gate dielectric layer122, and the spacers114and126form a gate structure across the fin structure101(as indicated inFIG.2B). Moreover, in a transversal direction of the gate electrode layer124(which may be orthogonal to the longitudinal direction of the gate electrode layer124), the remaining contact etch stop layer125covers a portions of a second side edge116S2of the source/drain region116and is covered by the insulating layer128, as shown inFIG.3B.

As a result, the spacer114and the spacer126are laterally and successively arranged from the sidewall of the gate electrode layer134. Moreover, the interface between the spacer114and the spacer126is substantially aligned to the first side edge116S1of the source/drain region116extending in a longitudinal direction of the gate electrode layer124(as shown inFIG.2E) and the second side edge116S2of the source/drain region116extending in a transversal direction of the gate electrode layer124is adjacent to the insulating layer128and in direct contact with the remaining contact etch stop layer125(as shown inFIG.3B).

Afterwards, a salicide process may be performed to form a silicide region150(which is also referred to as a salicide region) in the source/drain region116, as shown inFIGS.2F and3C. The silicide region150is self-aligned to the spacers126covering the sidewalls of the two adjacent gate electrode layers124. As a result, the sidewall of the spacer126is substantially aligned to a first side edge150S1of the silicide region extending in the longitudinal direction of the gate electrode layer124, as shown inFIG.2F. Moreover, a sidewall128S of the opening140constructed by the insulating layer128is substantially aligned to and in direct contact with a second side edge150S2of the silicide region150extending in the transversal direction of the gate electrode layer124, as shown inFIG.3C.

As a result, a top width W2of the silicide region150in the transversal direction of the gate electrode layer124is less than a top width W1of the source/drain region116in the transversal direction of the gate electrode layer124, as shown inFIG.2F. Namely, the first side edge116S1of the source/drain region116is laterally extended beyond the first side edge150S1of the silicide region150(as shown inFIG.2F), and the second side edge116S2of the source/drain region116is laterally extended beyond the second side edge150S2of the silicide region150(as shown inFIG.3C).

Since the region of the source/drain region116used for the silicide region150is defined by patterning the insulating layer128(i.e., by forming the opening140), the first side edge150S1of the silicide region150and the first side edge116S1of the source/drain region116can be separated from each other by a distance (which is substantially equal to the bottom width or the thickness of the spacer126in the transversal direction of the gate stack120a,120b,120c, or120d. Moreover, the second side edge150S2of the silicide region150cannot extend onto the second side edge116S2of the source/drain region116. As a result, the silicide landing area in the source/drain region116is reduced, so as to reduce the parasitic capacitance (Cp) between the gate electrode layer124and the subsequent formed source/drain contact structure.

In some embodiments, the silicide region150is formed by forming a metal layer (not shown) over the exposed top surface of the source/drain region116. Afterwards, an annealing process is performed on the metal layer, so that the metal layer reacts with the source/drain region116. Afterwards, the unreacted metal layer is removed to form the silicide region150. Examples for forming the metal layer includes Ti, Co, Ni, NiCo, Pt, Ni(Pt), Ir, Pt(Ir), Er, Yb, Pd, Rh, Nb, TiSiN, and the like.

After the silicide region150is formed, a sacrificial layer152is formed over the structure shown inFIGS.2F and3C, and fills the openings140. Afterwards, a hard mask structure including a first masking layer154, a second masking layer156, and a third masking layer158is formed over the sacrificial layer152, as shown inFIGS.2G and3Din accordance with some embodiments. In some embodiments, the sacrificial layer152is patterned using the hard mask structure as an etch mask. The sacrificial layer152includes an insulating material different than those of the insulating capping layers136a,136b,136c, and136dand the insulating layer128. In some embodiments, the masking layer138includes a tri-layer resist structure including a bottom layer (e.g., the first masking layer154), a middle layer (e.g., the second masking layer156), and a top layer (e.g., the third masking layer158).

For example, the bottom layer is a first layer of the tri-layer resist structure. The bottom layer may contain a material that is patternable and/or have an anti-reflection property, such as a bottom anti-reflective coating (BARC) layer or a nitrogen-free anti-reflective coating (NFARC) layer. In some embodiments, the bottom layer is formed by a spin-on coating process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or another suitable deposition process.

The middle layer is formed over the bottom layer and is a second layer of the tri-layer resist structure. The middle layer (which is also referred to as a hard mask layer) provides hard mask properties for the photolithography process. In addition, the middle layer is designed to provide etching selectivity from the bottom layer and the top layer. In some embodiments, the middle layer is made of silicon oxide, silicon nitride, or silicon oxynitride and is formed by a spin-on coating process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or another suitable deposition process.

The top layer is formed over the middle layer and is a third layer of the tri-layer resist structure. The top layer may be positive photoresist or negative photoresist. In some other embodiments, the tri-layer resist structure includes oxide-nitride-oxide (ONO) layers.

Afterwards, the top layer (e.g., the third masking layer158) is patterned to form a first pattern therein, as shown inFIGS.2G and3Din accordance with some embodiments.

After the first pattern is formed in the third masking layer158, the first pattern is successively transferred to the second masking layer156and the first masking layer154, so as to form a patterned first masking layer154pwith a second pattern therein, as shown inFIGS.2H and3Ein accordance with some embodiments. The patterned first masking layer154pmay be formed by a removing process that includes one or more etching processes. After the formation of the patterned first masking layer154p, the third masking layer158and the second masking layer156are removed and a portion of the sacrificial layer152is exposed from the patterned first masking layer154p.

An etching process is performed on the exposed sacrificial layer152using the patterned first masking layer154pas an etch mask, as shown inFIGS.2I and3Fin accordance with some embodiments. After the etching process is performed, an opening160is formed through the sacrificial layer152and the underlying insulating layer128to expose the top surface of silicide region150, as shown inFIG.3Fin accordance with some embodiments. During the opening160is formed, the insulating capping layers136a,136b,136c, and136d(which is not shown inFIGS.2I and3F) are also used as etch masks for protecting the gate stacks120a,120b,120c, and120d(which is not shown inFIGS.2I and3F).

Afterwards, the patterned first masking layer154pand the remaining sacrificial layer152are removed by one or more etching processes, as shown inFIGS.2J and3Gin accordance with some embodiments. As a result, openings161are formed in the insulating layer128between the gate structures (which includes gate stacks120a,120b,120c, and120dwith spacers114and126) to expose top surfaces of each silicide region150covered by the remaining sacrificial layer152and sidewalls of the spacers126, as shown inFIG.2J.

Afterwards, in some embodiments, spacers162are formed in the openings161to cover and be in direct contact with the exposed sidewalls of the spacer layers126, as shown inFIG.2K, and sidewalls of the openings161constituted by the insulating layer128, as shown inFIG.3H. For example, the spacer162may be separated from the spacer114by the spacer126in the transversal direction of the gate electrode layer124, as shown inFIG.2K. Moreover, the spacer162is in direct contact with the insulating layer128in the longitudinal direction of the gate electrode layer124, as shown inFIG.3H.

In some embodiments, the spacers162are made of an insulating material different from that of the spacers126. For example, the spacers162may be made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or another applicable dielectric material. After the spacers162are formed, the spacer126is covered by the spacer162and the spacer114is covered by the spacer126. The interface between the spacer162and the spacer126is substantially aligned to the first side edge150S1of the silicide region150(as indicated inFIG.2F), and the interface between the126spacer and the spacer114is substantially aligned to the first side edge116S1of the source/drain region116(as indicated inFIG.2F), as shown inFIG.2K. Moreover, the interface between the spacer162and the sidewall of the opening161constituted by the insulating layer128is substantially aligned to the second side edge150S2of the silicide region150(as indicated inFIG.3C), as shown inFIG.3H.

After the spacers162are formed in the openings161, source/drain contact structures164fill the openings161, respectively, as shown inFIGS.2L and3Iin accordance with some embodiments. Each of the source/drain contact structures164is surrounded by a corresponding spacer162and electrically connected to a corresponding source/drain region116through a corresponding silicide region150. The silicide region150is formed prior to the formation of the spacers162. Therefore, the bottom of the spacer162is entirely covered by the corresponding silicide region150, so as to be separated from the source/drain region116by the silicide region150. Moreover, since the source/drain contact structures164is formed after the spacers162are formed, the top width W2of the silicide region150(as indicated inFIG.2F) is greater than the bottom width W3of the source/drain contact structure164. As a result, the parasitic resistance (Re) induced by the silicide region150is reduced while keeping the critical dimension (CD) of the source/drain contact structure164.

In some embodiments, the source/drain contact structure164is made of Co, Ru, W, Cu, or the like. The formation of the source/drain contact structure164may include forming a metal material (not shown) over the structure shown inFIGS.2K and3Hand filling the openings161by a chemical vapor deposition (CVD) process, a physical vapor deposition, (PVD) process, an atomic layer deposition (ALD) process, an electroless deposition (ELD) process, an electrochemical plating (ECP) process, or another applicable process. Afterwards, a planarization process is performed to remove the excess metal material above the insulating capping layers136a,136b,136c, and136d(which is not shown inFIG.2L), in accordance with some embodiments. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

After the planarization process, the remaining metal material forms the source/drain contact structure164between and adjacent to the gate structures including the gate stacks120a,120b,120c, and120d(which is not shown inFIG.2L), as shown inFIG.2L. Those source/drain contact structure164are electrically connected to the corresponding source/drain regions116, and separated from the gate stacks by the spacers114,126and162that are formed over opposing sidewalls of the gate stacks120a,120b,120c, and120d. Moreover, the upper surface of the source/drain contact structure164is substantially level with the upper surface of the insulating capping layers136a,136b,136c, and136d.

Although the semiconductor device structure formed by the methods shown inFIGS.2A to2L and3A to3Iincludes the formation and the patterning of the sacrificial layer152and the hard mask structure including a first masking layer154, a second masking layer156, and a third masking layer158after the silicide region150is formed, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. For example, the formation of the sacrificial layer152and the hard mask structure are omitted.

FIGS.2G-1and2H-1illustrate cross-sectional representations of various stages of manufacturing a semiconductor device structure in accordance with some embodiments. In some embodiments, a structure shown inFIG.2Fis provided, and spacers162are formed in the openings140to cover and be in direct contact with the exposed sidewalls of the spacer layers126, as shown inFIG.2G-1, and sidewalls of the openings161constituted by the insulating layer128(not shown and referred toFIG.3H).

After the spacers162are formed in the openings140, source/drain contact structures164fill the openings140, respectively, as shown inFIG.2H-1in accordance with some embodiments. Each of the source/drain contact structures164is electrically connected to a corresponding source/drain region116through a corresponding silicide region150.

Embodiments of semiconductor device structures and methods for forming the same are provided. The formation of the semiconductor device structure includes forming a gate electrode layer, a first spacer layer, and a second spacer over a semiconductor substrate with a source/drain region therein and forming a silicide region in the source/drain region. Afterwards, a source/drain contact structure is formed over the source/drain region. In the semiconductor device structure, the first spacer and the second spacer are laterally and successively arranged from the sidewall of the gate electrode layer to the source/drain contact structure. Moreover, the silicide region is formed prior to the formation of the second spacer and is self-aligned to the first spacer, so that the bottom of the second spacer is covered by the silicide region. As a result, the top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region. Therefore, the semiconductor device structure has a lower parasitic resistance (Re) induced by the silicide region than the case where the top width of the silicide region is equal to the bottom width of the source/drain contact structure when the critical dimension (CD) of the source/drain contact structure is not increased or changed. Moreover, such a semiconductor device structure with lower parasitic resistance (Re) also has a lower parasitic capacitance (Rc) between the gate electrode layer and the source/drain contact structure than the case where the top width of the silicide region less than the top width of the source/drain region.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed over the semiconductor substrate and adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The sidewall of the first spacer is substantially aligned to the first side edge of the source/drain region extending in the longitudinal direction of the gate electrode layer. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a conductive feature formed in a fin structure of a semiconductor substrate. The conductive feature has a first side edge extending in a first direction and a second side edge extending in a second direction that is orthogonal to the first direction. The semiconductor device structure also includes an insulating layer formed over the semiconductor substrate and adjacent to the second side edge of the conductive feature. The semiconductor device structure further includes a conductive contact structure formed in the insulating layer and corresponding to the conductive feature. In addition, the semiconductor device structure includes a silicide region formed between and electrically connected to the conductive contact structure and the conductive feature. The silicide region has a first side edge extending in the first direction and a second side edge extending in the second direction. The second side edge of the silicide region is in direct contact with the insulating layer.

In some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming an insulating layer over a semiconductor substrate with a fin structure. The fin structure has a source/drain region. The method also includes forming a first gate structure and a second gate structure in the first insulating layer and across the fin structure on both sides of the source/drain region. Each of the first gate structure and the second gate structure includes a gate stack; a first spacer covering the sidewall of the gate stack, and a second spacer covering the sidewall of the first spacer. The method further includes forming an opening in the insulating layer between the first gate structure and the second gate structure to expose the top surface of the source/drain region and the sidewall of the second spacer layer. In addition, the method includes forming a silicide region on the exposed top surface of the source/drain region and forming a third spacer in the opening to cover the exposed sidewall of the second spacer layer and sidewalls of the opening constituted by the insulating layer. The method also includes forming a source/drain contact structure in the opening having the third spacer.