Display device and manufacturing method thereof

A display device includes a substrate, a buffer layer on the substrate, a first semiconductor layer of a first transistor on the buffer layer, a first insulating layer disposed on the first semiconductor layer, a first gate electrode of the first transistor on the first insulating layer, a second insulating layer on the first gate electrode, and a second semiconductor layer of a second transistor disposed on the second insulating layer. A difference between a first distance between a lower side of the buffer layer and an upper side of the second insulating layer and a second distance between an upper side of the first semiconductor layer and an upper side of the second insulating layer is 420 to 520 angstroms.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2017-0122743, filed on Sep. 22, 2017, in the Korean Intellectual Property Office, and entitled: “Display Device and Manufacturing Method Thereof,” is incorporated by reference herein in its entirety.

BACKGROUND

This disclosure relates to a display device and a manufacturing method thereof.

2. Description of the Related Art

Transistors included in various electronic devices such as display devices include a gate electrode, a source electrode, a drain electrode, and a semiconductor layer. The transistors are used as switches or driving elements in the display device. Transistor display panels including the transistors are used as circuit boards for driving pixels in the display devices. The transistor display panel may include a gate line for transmitting a gate signal, a data line for transmitting a data voltage corresponding to an image signal, and a pixel electrode connected to the transistor.

There are increasing demands for high-resolution display devices. When spacing between transistors is reduced, transistor density may be increased to increase resolution, while the area occupied by the transistors may be reduced to increase an aperture ratio of pixels. When transistors are not formed on a same layer, but are stacked on different layers, spacing between transistors may be reduced. This stacked structure may, however, require an additional processing stage.

SUMMARY

An exemplary embodiment provides a display device including: a substrate; a buffer layer disposed on the substrate; a first semiconductor layer of a first transistor disposed on the buffer layer; a first insulating layer disposed on the first semiconductor layer; a first gate electrode of the first transistor disposed on the first insulating layer; a second insulating layer disposed on the first gate electrode; and a second semiconductor layer of a second transistor disposed on the second insulating layer. A difference between a first distance between a lower side of the buffer layer and an upper side of the second insulating layer and a second distance between an upper side of the first semiconductor layer and an upper side of the second insulating layer is 420 to 520 angstroms.

A difference between a third distance between an upper side of the first gate electrode and an upper side of the second insulating layer and the second distance may be 420 to 520 angstroms.

The first distance may correspond to a sum of thicknesses of the buffer layer, the first insulating layer, and the second insulating layer in a region not overlapping the first semiconductor layer.

The second distance may correspond to a sum of thicknesses of the first insulating layer and the second insulating layer in a region overlapping the first semiconductor layer and not overlapping the first gate electrode.

The third distance may correspond to a thickness of the second insulating layer in a region overlapping the first gate electrode.

The second transistor may include a second gate electrode overlapping the second semiconductor layer, and a thickness of the second semiconductor layer may be equal to or less than 500 angstroms.

The first semiconductor layer and the second semiconductor layer may respectively include polysilicon.

The first semiconductor layer may include a first channel overlapping the first gate electrode, and a first source electrode and a first drain electrode positioned at respective sides of the first channel. The second semiconductor layer may include a second channel overlapping the second gate electrode, and a second source electrode and a second drain electrode positioned at respective sides of the second channel.

The display device may further include a third insulating layer disposed between the second semiconductor layer and the second gate electrode, and a fourth insulating layer disposed on the second gate electrode. The first transistor may include a first source connector and a first drain connector connected to the first source electrode and the second drain electrode through contact holes passing through the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer.

The display device may further include: a pixel electrode disposed on the second transistor; a light emitting member disposed on the pixel electrode; and a common electrode disposed on the light emitting member.

Another embodiment provides a method for manufacturing a display device, including: forming a buffer layer on a substrate; forming a first semiconductor layer of a first transistor on the buffer layer; forming a first insulating layer on the first semiconductor layer; forming a first gate electrode of the first transistor on the first insulating layer; forming a second insulating layer on the first gate electrode; and forming a second semiconductor layer of a second transistor on the second insulating layer. The forming of a second semiconductor layer includes forming an amorphous silicon layer and crystallizing amorphous silicon in the amorphous silicon layer, and the first semiconductor layer is activated or annealed when the crystallization is performed.

A difference between a first distance between a lower side of the buffer layer and an upper side of the second insulating layer and a second distance between an upper side of the first semiconductor layer and an upper side of the second insulating layer is 420 to 520 angstroms.

A difference between a third distance between an upper side of the first gate electrode and an upper side of the second insulating layer and the second distance may be 420 to 520 angstroms.

The first semiconductor layer and the second semiconductor layer may respectively include polysilicon.

The first distance may correspond to a sum of thicknesses of the buffer layer, the first insulating layer, and the second insulating layer in a region not overlapping the first semiconductor layer.

The second distance may correspond to a sum of thicknesses of the first insulating layer and the second insulating layer in a region overlapping the first semiconductor layer and not overlapping the first gate electrode.

The third distance may correspond to a thickness of the second insulating layer in a region overlapping the first gate electrode.

A thickness of the second semiconductor layer may be equal to or less than 500 angstroms.

The method may further include: forming a third insulating layer on the second semiconductor layer; forming a second gate electrode of the second transistor on the third insulating layer; forming a fourth insulating layer on the second gate electrode; and forming a first source connector and a first drain connector connected to the first semiconductor layer through the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer, and forming a second source connector and a second drain connector connected to the second semiconductor layer through the third insulating layer and the fourth insulating layer.

Another embodiment provides a display device, including a substrate, a buffer layer on the substrate, a first semiconductor layer of a first transistor on the buffer layer, a first insulating layer on the first semiconductor layer, a first gate electrode of the first transistor on the first insulating layer, a second insulating layer on the first gate electrode, and a second semiconductor layer of a second transistor on the second insulating layer. The buffer layer, the first insulating layer, and the second insulating layer may include a same material having a duty cycle between maximum transmittances with respect to a thickness of the same material. A difference in thickness between a first sum of a thickness of the buffer layer, the first insulating layer, and the second insulating layer, and a second sum of a thickness of the first insulating layer and the second insulating layer may be about half a duty cycle or an odd integer multiple thereof.

DETAILED DESCRIPTION

In the following detailed description, only certain exemplary have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

The size and thickness of each configuration shown in the drawings are arbitrarily shown for better understanding and ease of description, and the embodiments are not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. For better understanding and ease of description, the thicknesses of some layers and areas are exaggerated.

The phrase “on a plane” means viewing the object portion from the top, and the phrase “on a cross-section” means viewing a cross-section of which the object portion is vertically cut from the side.

A display device according to embodiments will now be described in detail with reference to accompanying drawings.

FIG. 1illustrates a cross-sectional view of a display device according to an exemplary embodiment.FIG. 2illustrates a top plan view of a display device shown inFIG. 1.FIG. 3illustrates a graph of optical characteristics according to a thickness of an insulating layer.FIG. 4illustrates a graph of transmittance according to a thickness of a semiconductor layer.

FIG. 1shows a cross-sectional view of a display device shown inFIG. 2with respect to a line I-I′, and a plan view of a display device having a cross-sectional structure as shown inFIG. 1is not limited to that shown inFIG. 2.FIG. 2shows a region corresponding to one pixel of an organic light emitting device including a first transistor T1and a second transistor T2, but embodiments are not limited to the organic light emitting device, and may be applied to other types of display devices, e.g., a liquid crystal display.

Referring toFIG. 1andFIG. 2, the display device includes a substrate110, and a first transistor T1, a second transistor T2, and an organic light emitting diode LD disposed on the substrate110.

In the drawings, a first direction D1and a second direction D2are parallel to a side that is seen in a direction that is perpendicular to a surface of the substrate110, e.g., a surface on which constituent elements are stacked, and are perpendicular to each other. A third direction D3is perpendicular to the first direction D1and the second direction D2and it is substantially perpendicular to the surface of the substrate110. The third direction D3may be mainly indicated in a cross-sectional structure, and is also referred to as a cross-sectional direction, a stacking direction, or a thickness direction. A structure that is seen when a side in parallel to the first direction D1and the second direction D2is observed is referred to as a plane structure. When a first constituent element is on a second constituent element in the cross-sectional structure, it means that the two constituent elements are arranged on one another in the third direction D3, and a third constituent element may be between the constituent elements.

The substrate110may be a flexible substrate, e.g., a plastic substrate. For example, the substrate110may be made of polymers such as polyimide, polyamide, polycarbonate, or polyethylene terephthalate. Alternatively, the substrate110may be a rigid substrate, e.g., a glass substrate.

A buffer layer111may be on the substrate110. The buffer layer111may block an impurity that may diffuse into a first semiconductor layer131afrom the substrate110and may reduce a stress applied to the substrate110during a process for forming the first semiconductor layer131aof the first transistor T1. The buffer layer111may increase adhesiveness of the first semiconductor layer131ato the substrate110. The buffer layer111is an insulating layer, but is called a buffer layer in consideration of its function.

A first transistor T1is on the buffer layer111. The first transistor T1includes the first semiconductor layer131aand a first gate electrode124adisposed thereon along the third direction D3. The first semiconductor layer131aincludes a first channel134aoverlapping the first gate electrode124a, e.g., along the third direction D3, and a first source electrode133aand a first drain electrode135aat respective sides of the first channel134a. The first semiconductor layer131amay include polysilicon formed by crystallizing amorphous silicon by a crystallization method, e.g., excimer laser annealing (ELA). Further, the first source electrode133aand the first drain electrode135aare ion-doped and activated on the first semiconductor layer131a. A first insulating layer141is between the first semiconductor layer131aand the first gate electrode124a.

A second transistor T2is on the first transistor T1along the third direction D3. The second transistor T2includes a second semiconductor layer131band a second gate electrode124b. The second semiconductor layer131bincludes a second channel134boverlapping the second gate electrode124b, and a second source electrode133band a second drain electrode135bat respective sides of the second channel134b. The second semiconductor layer131bincludes polysilicon formed by crystallizing amorphous silicon by a crystallization method, e.g., ELA. Further, the second source electrode133band the second drain electrode135bare ion-doped and activated on the second semiconductor layer131b. A third insulating layer142is between the second semiconductor layer131band the second gate electrode124b.

Regarding one pixel PX of the organic light emitting device, the first transistor T1may be a switching transistor, and the second transistor T2may be a driving transistor. The pixel PX includes two transistors T1and T2in the shown exemplary embodiment. However, the pixel PX may include at least three transistors.

The first transistor T1and the second transistor T2are disposed along the third direction D3with a second insulating layer161therebetween. In further detail, the first transistor T1is between the substrate110and the second insulating layer161, and the second transistor T2is between the second insulating layer161and a fourth insulating layer162. Therefore, the first transistor T1and the second transistor T2form a stacked structure along the third direction D3. The second transistor T2is over the first transistor T1in the shown exemplary embodiment. Alternatively, the first transistor T1may be disposed over the second transistor T2.

According to the above-noted stacked structure, the gap or spacing between the first transistor T1and the second transistor T2may be reduced or the first transistor T1and the second transistor T2may be at least partially overlap each other along the third direction D3, so the freedom of designing transistors increases. Therefore, such a stacked structure may increase the aperture ratio of the pixel and/or increase of the resolution of the display device. However, since the first semiconductor layer131aand the second semiconductor layer131bare formed on different layers and respectively need crystallization and activation, an additional processing stage may be needed.

The buffer layer111, the first insulating layer141, the second insulating layer161, the third insulating layer142, and the fourth insulating layer162may respectively include an inorganic insulating material, e.g., a silicon oxide (SiOX) or a silicon nitride (SiNX). In the present specification, the buffer layer111represents an insulating layer between the substrate110and the first semiconductor layer131a. The first insulating layer141represents an insulating layer between the first semiconductor layer131aand the first gate electrode124a. The second insulating layer161represents an insulating layer between the first gate electrode124aand the second semiconductor layer131b. The third insulating layer142represents an insulating layer between the second semiconductor layer131band the second gate electrode124b. The fourth insulating layer162represents an insulating layer between the second gate electrode124band the gate line171. Each of the insulating layers may be formed as a single layer or multiple layers. For example, the buffer layer111may be formed as dual layers, and a lower layer closer to the substrate110may include a silicon nitride and an upper layer may include a silicon oxide.

According to an exemplary embodiment, additional processing stages may be minimized and/or characteristics of the first semiconductor layer131amay be improved by controlling thicknesses of the buffer layer111, the first insulating layer141, and the second insulating layer161. For example, a first distance d1that is a sum of thicknesses of the buffer layer111, the first insulating layer141, and the second insulating layer161in the first region A1not overlapping the first semiconductor layer131amay be greater than a second distance d2that is a sum of thicknesses of the first insulating layer141and the second insulating layer161in the second region A2overlapping the first semiconductor layer131aand not the first gate electrode124aby about 420 to 520 angstroms, about 440 to 500 angstroms, or about 460 to 480 angstroms. A third distance d3that is a thickness of the first insulating layer141in the third region A3overlapping the first gate electrode124amay be less than the second distance d2by about 420 to 520 angstroms, about 440 to 500 angstroms, or about 460 to 480 angstroms. As shown, the first distance d1corresponds to a distance between a lower side of the buffer layer111and an upper side of the second insulating layer161(or a distance between an upper side of the substrate110and an upper side of the second insulating layer161), the second distance d2corresponds to a distance between an upper side of the first semiconductor layer131aand an upper side of the second insulating layer161, and the third distance d3corresponds to a distance between an upper side of the first gate electrode124aand an upper side of the second insulating layer161.

When the thicknesses of the buffer layer111, the first insulating layer141, and the second insulating layer161are controlled as described above, damage that may generated to the substrate110and the first gate electrode124amay be prevented while activating or annealing the first semiconductor layer131aby using energy applied for crystallization for forming the second semiconductor layer131b. In other words, heat applied to the first source electrode133aand the first drain electrode135aof the first semiconductor layer131awhen the second semiconductor layer131bis crystallized may be maximized and heat applied to the substrate110and the first gate electrode124amay be minimized by setting a difference of thicknesses of the insulating layers disposed between the substrate110and the second semiconductor layer131bin the first region A1, the second region A2, and the third region A3. A detailed description of different transfer of heat caused by the difference of thicknesses of the insulating layers will be provided in a latter portion of the present specification with reference toFIG. 3.

Conventionally, the first semiconductor layer131amay be activated by heating the substrate110on which the first transistor T1is formed, e.g., in a furnace. In this instance, an activation temperature influences the substrate110, so the substrate110may be damaged, particularly when the substrate110is a plastic substrate. Thus, the activation temperature of the first semiconductor layer131ashould not be set too high. However, when the activation temperature is lowered to prevent the substrate110from being damaged, reliability (e.g., deterioration of electron/hole mobility, deterioration of lifespans, and increase of leakage current) of the first transistor T1may be reduced.

According to the exemplary embodiment, high heat may be selectively applied to the first semiconductor layer131athat needs to be activated, so the reliability of the first transistor T1may be improved without damaging the substrate110or the first gate electrode124a. Further, the first semiconductor layer131amay be activated when the second semiconductor layer131bis crystallized, so no additional processing stage for activating the first semiconductor layer131ais needed.

Referring toFIG. 3, a graph for indicating optical characteristics according to a thickness of an insulating layer, particularly calculated values and measured values of transmittance and reflectivity according to a thickness of silicon oxide as the insulating layer, is provided. Following equations are used to find the calculated values of transmittance and reflectivity.

Here, R is reflectivity, nfis a refractive index of a film, nsis a refractive index of a substrate, Φ is a phase difference, d is a thickness of a film, λ0is a wavelength of incident light, and T is transmittance.

Herein, incident light is assumed to have a wavelength of 308 nm; the substrate is assumed to be polysilicon with a refractive index of 3.49 and an extinction coefficient of 4.29; and the film is assumed to be silicon dioxide (SiO2) with a refractive index of 1.48 and an extinction coefficient of 0.2×10−4to output the reflectivity and the transmittance according to the thickness of the silicon dioxide insulating layer as illustrates in the graph ofFIG. 3.

As can be seen from the graph ofFIG. 3, the transmittance and reflectivity of the insulating layer periodically increases and decreases as the thickness of the insulating layer increases. Within each period, a same thickness may provide a minimum value for the reflectivity and has a maximum value for the transmittance, e.g., the transmittance and reflectivity are substantially out of phase. The calculated values and the measured values show the same periodical characteristics of the transmittance and reflectivity. However, the calculated values, as well as differences between thickness providing the minimum and maximum values, are slightly different from the measured values. This is because the actual insulating layer being measured may include various kinds of silicon oxides (SiOX) in addition to the silicon dioxide, while the calculated values assume the insulating layer is pure silicon dioxide (SiO2). Therefore, based upon the measured values, within the range of thicknesses shown inFIG. 3, the insulating layer has maximum transmittance at a thickness of about 390 angstroms, has minimum transmittance at a thickness of about 860 angstroms, and a difference of thicknesses between these is about 470 angstroms. The above-described difference between the first distance d1and the second distance d2and the above-described difference between the second distance d2and the third distance d3are set considering the measured values and errors.

The thickness differences between the maximum and minimum values for the reflectivity and transmittance are almost the same when the thickness of the insulating layer increases, due to the periodicity approximating a sine wave according to the thickness of the insulating layer. Therefore, the maximum or minimum value of transmittance is repeated at a thickness change of about every 470*2 angstroms, e.g., these curves have a duty cycle of about 470*2 angstroms.

Based on the above-noted transmittance characteristic in accordance with the thickness of the insulating layer, the first distance d1and the third distance d3may be set at a thickness corresponding to a minimum value of transmittance, and the second distance d2may be set at a thickness corresponding to a maximum value of transmittance. The maximum amount of heat applied when the second semiconductor layer131bis crystallized may be transmitted to portions (i.e., the first source electrode133aand the first drain electrode135a) of the first semiconductor layer131aprovided in the second region A2, and the minimum amount of heat thereof may be transmitted to the substrate110and the first gate electrode124aprovided in the first region A1and the third region A3.

When the maximum value, the minimum value, and the periodicity of the transmittance due to the thickness of the insulating layer, for example, the intended effect may be maximized when the third distance d3is about (890+470*2l) angstroms, the second distance d2is about (1360+470*2m) angstroms, and the first distance d1is about (1830+470*2p) angstroms (here, l, m, and p are nonnegative integers and may be the same as or different from each other). Therefore, the first distance d1, the second distance d2, and the third distance d3may be set with an optimal value or to be within a predetermined range (e.g., ±5%, ±10%, ±20%, etc.) of the optimal value. In particular, the first and third distances may be set to be a starting value, e.g., a smallest thickness that provides a maximum transmittance value, plus even multiples (or zero for the distance d3) of the thickness difference between maximum and minimum transmittances, while the second distance may be set to be the starting value plus an odd integer multiple of the thickness different between maximum and minimum transmittances. Thus, a difference between the first distance and the second distance may be about half a duty cycle or an odd integer multiple thereof.

However, the exemplary embodiment is not limited thereto the above-noted setting. For example, the first distance d1, the second distance d2, and the third distance d3may be changed by a certain degree according to contributions from the first buffer layer111, the first insulating layer141, and the second insulating layer161or in consideration of other design variables. For example, the third distance d3, the second distance d2, and the first distance d1may be about 1000 angstroms, about 1500 angstroms, and about 2000 angstroms, respectively, and the respective distances may increase by about 1000 angstroms.

The second semiconductor layer131bmay be formed to have a predetermined range of thickness. When the second semiconductor layer131bis very thick, transmittance (more accurately, transmittance of an amorphous silicon layer to a polysilicon layer) of the second semiconductor layer131bis deteriorated, so heat applied when the second semiconductor layer131bis crystallized may not sufficiently reach the first semiconductor layer131a. In relation to this,FIG. 4shows a graph of transmittance of an amorphous semiconductor layer according to thickness. Referring toFIG. 4, when the thickness thereof is greater than about 500 angstroms, its transmittance is almost 0%, so it may be difficult for the heat applied to the semiconductor layer to be transmitted to a layer provided below the semiconductor layer. Therefore, the thickness of the second semiconductor layer131bmay be equal to or less than, for example, about 500 angstroms. However, when the second semiconductor layer131bis very thin, the characteristics of the second transistor T2may be deteriorated, and the constituent elements provided below the same may be damaged because of high transmittance. Therefore, the thickness of the second semiconductor layer131bmay be greater than, for example, about 150 angstroms, about 300 angstroms, or about 350 angstroms. The thickness of the second semiconductor layer131bmay be appropriately changed according to the energy applied at the time of crystallization, and heat transmitted to the first semiconductor layer131amay be controlled by controlling the thickness of the second semiconductor layer131b.

Referring toFIG. 1andFIG. 2, the gate electrodes124aand124bof the first transistor T1and the second transistor T2are on the semiconductor layers131aand131b, so they may be referred to as top gate type of transistors. However, the transistors may have various configurations, and for example, at least one of the first transistor T1and the second transistor T2may be a bottom gate type of transistor in which the gate electrodes124aand124bare disposed below the semiconductor layers131aand131h.

The first transistor T1and the second transistor T2may be nMOS transistors or pMOS transistors, and one of them may be an nMOS transistor and the other may be a pMOS transistor. On the first semiconductor layer131a, the first source electrode133aand the first drain electrode135aof the first transistor T1may be set by a direction of carriers that flow through the first channel134awhen a gate-on voltage is applied to the first gate electrode124a, and the carriers flow to the first drain electrode135afrom the first source electrode133a. Therefore, when the first transistor T1is operated, electrons flow to the first drain electrode135afrom the first source electrode133ain the n-type transistor, and holes flow to the first drain electrode135afrom the first source electrode133ain the p-type transistor. A relationship between the second source electrode133band the second drain electrode135bof the second transistor T2corresponds to that of the first transistor T1.

A first source connector173a, a first drain connector175a, a second source connector173b, and a second drain connector175bare disposed on a fourth insulating layer162for covering a second transistor T2. The first source connector173aand the first drain connector175aare connected to the first source electrode133aand the first drain electrode135aof the first transistor T1through contact holes183aand185apassing through the first insulating layer141, the second insulating layer161, the third insulating layer142, and the fourth insulating layer162. The second source connector173band the second drain connector175bare connected to the second source electrode133band the second drain electrode135bof the second transistor T2through contact holes183band185bpassing through the third insulating layer142and the fourth insulating layer162. Alternatively, at least one of the first source connector173aand the first drain connector175amay be below the fourth insulating layer162. For example, at least one of the first source connector173aand the first drain connector175amay be on the same layer as the second gate electrode124band may be formed of the same material as the second gate electrode124b.

A data line171for transmitting a data signal and a driving voltage line172for transmitting a driving voltage are disposed on the fourth insulating layer162. The data line171and the driving voltage line172may exemplarily extend in the second direction D2. A gate line121for transmitting a gate signal may be disposed between the first insulating layer141and the second insulating layer161in a like manner of the first gate electrode124a. The gate line121may cross the data line171and may extend in the first direction D1.

A pixel electrode191is on a planarized layer180. The pixel electrode191is connected to the second drain connector175bthrough a contact hole185cpassing through the planarized layer180. The second drain connector175bis connected to the second drain electrode135bof the second transistor T2, so the pixel electrode191is electrically connected to the second drain electrode135bof the second transistor T2. In the shown exemplary embodiment, the lower first transistor T1is a switching transistor, and the upper second transistor T2is a driving transistor. Alternatively, when the first transistor T1is a driving transistor, the pixel electrode191may be connected to the first drain connector175aconnected to the first drain electrode135aof the first transistor T1.

Regarding the display device, a portion to the pixel electrode191from the substrate110is also referred to as a transistor display substrate, a transistor array substrate, and a transistor substrate. The transistor display substrate may be applied to other types of display devices such as a liquid crystal display as well as the organic light emitting device.

A pixel defining layer360is on the planarized layer180and the pixel electrode191. The pixel defining layer360includes an opening overlapping the pixel electrode191. A light emitting member370including an emission layer is in the opening of the pixel defining layer360, and a common electrode270is on the light emitting member370. The pixel electrode191, the light emitting member370, and the common electrode270form an organic light emitting diode LD, which is a light-emitting device. The pixel electrode191may be an anode of the organic light emitting diode LD, and the common electrode270may be a cathode of the organic light emitting diode LD.

An encapsulation layer390for protecting the organic light emitting diode LD may be disposed on the common electrode270. The encapsulation layer390may exemplarily be a thin-film encapsulation layer in which at least one inorganic insulating layer and at least one organic insulating layer are alternately stacked.

A storage capacitor Cst of the display device may, e.g., be formed by a first storage electrode129extending from the second gate electrode124b, a second storage electrode179extending from the driving voltage line172, and an insulating layer (e.g., a fourth insulating layer162) between the first storage electrode129and the second storage electrode179. The constituent elements of the storage capacitor Cst, and positions thereof, may be modifiable in various ways.

A method for manufacturing a display device shown with reference toFIG. 1andFIG. 2according to an exemplary embodiment will now be described with reference toFIG. 5toFIG. 9.

Referring toFIG. 5, an inorganic insulating material such as a silicon oxide or a silicon nitride is deposited on the substrate110that may be a plastic substrate by use of a chemical vapor deposition (CVD) method to thus form a buffer layer111. A first transistor T1is formed on the buffer layer111.

In further detail of formation of the first transistor T1, a semiconductor material such as amorphous silicon is deposited on the buffer layer111through CVD to form an amorphous silicon layer, and the amorphous silicon layer is crystallized to form a polysilicon layer. Suitable crystallization methods, without being limited thereto, includes, e.g., ELA, metal induced crystallization (MIC), solid phase crystallization (SPC), sequential lateral solidification (SLS), metal induced lateral crystallization (MILC), and the like. The polysilicon layer is patterned to form a first semiconductor layer131a. In this instance, the first source electrode133aand the first drain electrode135aare not formed on the first semiconductor layer131a.

An inorganic insulating material, e.g., a silicon oxide or a silicon nitride, is deposited to form a first insulating layer141. A conductive material, e.g., a metal, is deposited, e.g., sputtered. on the first insulating layer141to form a conductive layer, and it is patterned to form a first gate electrode124aand a gate line121.

Using the first gate electrode124aas a mask, the first semiconductor layer131ais ion-doped to form a first source electrode133aand a first drain electrode135awith low resistance. Most of the ion-doped impurity dopant is positioned in a crack and not in a lattice position on the first semiconductor layer131a, so it needs to be activated when it is ion-doped. The activation may be performed by, e.g., performing a heat treatment in a furnace at a predetermined temperature for a predetermined time. However, when the substrate110is a plastic substrate and an activation temperature is lowered so as to prevent the substrate110from being damaged, the activation is insufficient to deteriorate reliability of the first transistor T1. According to an exemplary embodiment, when the activation temperature is lowered, annealing for reinforcing the activation may be performed in a subsequent process for forming a second semiconductor layer131bof the second transistor T2. As an option, the activation of the first semiconductor layer131aperformed after the ion doping may be omitted, and the first semiconductor layer131amay be activated in the subsequent process for forming the second semiconductor layer131b.

Referring toFIG. 6, a second insulating layer161is formed by depositing a silicon oxide or a silicon nitride on the first transistor T1on which the first semiconductor layer131ais not activated or is insufficiently activated. In this instance, the second insulating layer161may be formed so that the first distance d1may be greater than the second distance d2by about 420 to 520 angstroms, about 440 to 500 angstroms, or about 460 to 480 angstroms. Further, the second insulating layer161may be formed so that the third distance d3may be less than the second distance d2by about 420 to 520 angstroms, about 440 to 500 angstroms, or about 460 to 480 angstroms. The first distance d1and the second distance d2include the thickness of the buffer layer111and/or the first insulating layer141, so the thickness of the buffer layer111and the first insulating layer141must be considered together with the same.

The meaning, the calculation grounds, and the detailed examples of the first distance d1, the second distance d2, and the third distance d3have been described in detail with reference toFIG. 1andFIG. 3, so they will not be described again. To increase uniformity of the first distance d1, the second distance d2, and the third distance d3in the first region A1, the second region A2, and the third region A3, respectively, a surface of the second insulating layer161may be further planarized, e.g., by performing chemical mechanical planarization (CMP), after formation of the second insulating layer161. The buffer layer111and the first insulating layer141may respectively be uniform in thickness throughout the first region A1, the second region A2, and the third region A3, and the second insulating layer161is the thickest in the first region A1and is the thinnest in the third region A3.

A semiconductor material, e.g., amorphous silicon, may be deposited on the second insulating layer161to form an amorphous silicon layer, and the amorphous silicon layer may be crystallized to form a polysilicon layer130h. The amorphous silicon layer may be formed to have a predetermined range of thickness in consideration of its transmittance and the characteristics of the second transistor T2. The excimer laser annealing method may be used to crystallize the amorphous silicon layer.

By setting the difference of thicknesses of the insulating layers provided between the substrate110and the amorphous silicon layer in the first region A1, the second region A2, and the third region A3, heat transmitted to the first source electrode133aand the first drain electrode135aof the first semiconductor layer131amay be maximized when the amorphous silicon layer is crystallized, and heat transmitted to the substrate110and the first gate electrode124amay be minimized. Therefore, when the amorphous silicon layer is crystallized, the first semiconductor layer131a(particularly, the first source electrode133aand the first drain electrode135a) may be activated and annealed by using the heat applied to the first source electrode133aand the first drain electrode135aof the first semiconductor layer131a, and the substrate110and the first gate electrode124amay be prevented from being damaged. The annealing may be understood as additionally activating the first semiconductor layer131athat is insufficiently activated. Further, at the time of ion doping, the damaged lattice of the first semiconductor layer131amay be recrystallized through annealing.

Referring toFIG. 7, a polysilicon layer130bmay be patterned to form a second semiconductor layer131b, and an inorganic insulating material such as a silicon oxide or a silicon nitride is deposited to form a third insulating layer142. A conductive material, e.g., a metal, may be deposited on the third insulating layer142to form a conductive layer, and is patterned, and thereby a second gate electrode124bis formed. Using the second gate electrode124bas a mask, the second semiconductor layer131bis ion-doped to form the second source electrode133band the second drain electrode135bwith low resistance and activate the same. The second gate electrode124bforms the second transistor T2together with the second semiconductor layer131bincluding the second source electrode133b, the second channel134b, and the second drain electrode135b.

Referring toFIG. 8, an inorganic insulating material, e.g., silicon oxide or silicon nitride, may be deposited on the second transistor T2to form a fourth insulating layer162. Contact holes overlapping the first source electrode133aand the first drain electrode135a, respectively, may be formed in the first insulating layer141, the second insulating layer161, the third insulating layer142, and the fourth insulating layer162, and contact holes overlapping the second source electrode133band the second drain electrode135bare respectively formed in the third insulating layer142and the fourth insulating layer162. A conductive material such as a metal is deposited on the fourth insulating layer162to form a conductive layer, and it is patterned, and thereby a first source connector173aand a first drain connector175aconnected to the first source electrode133aand the first drain electrode135a, a second source connector173band a second drain connector175bconnected to the second source electrode133band the second drain electrode135b, a data line171, and a driving voltage line172are formed.

Referring toFIG. 9, an organic insulating material and/or an inorganic insulating material is deposited to form a planarized layer180. A contact hole overlapping the second drain connector175bis formed in the planarized layer180, a conductive layer is formed on the planarized layer180, and the same is patterned to thus form a pixel electrode191connected to the second drain connector175b.

By forming a pixel defining layer360, a light emitting member370, a common electrode270, and an encapsulation layer390on the pixel electrode191, the display device shown inFIG. 1may be manufactured.

By way of summation and review, a display device including transistors in a stacked structure, the characteristic of the lower transistor may be improved when the upper transistor is formed, and the processing cost may be reduced. In addition, according to the exemplary embodiments, heat may be selectively transmitted to the semiconductor layer of the lower transistor requiring activation or annealing without damaging other portions of the display device, such as a substrate, thereby improving reliability of the display device.