Electronic memory having impedance-matched sensing

An electronic memory, typically a flash EPROM, contains an array of memory sections (40), each containing an array of memory cells (54). Global bit lines (60) fully traverse the memory. Local bit lines (58) partially traverse the memory. Data stored in the memory is sensed with an arrangement that utilizes impedance matching to achieve high sensing accuracy with low noise sensitivity. The impedance matching may be provided solely from the sections and lines of the memory or partially from a separate reference memory section (102) that contains reference memory cells (104).

FIELD OF USE

This invention relates to semiconductor memories, especially erasable programmable read-only memories (“EPROMs”) of the flash-erasable type.

BACKGROUND ART

Semiconductor memories are formed with memory cells that store bits of data. The memory cells are normally very small. As a result, cell data signals that indicate the states of the stored data are electrically small and need to be amplified. Devices commonly referred to as sense amplifiers provide the amplification. A sense amplifier typically amplifies the difference between a data signal received at one input terminal and a reference signal received at another input terminal. Because the cell data signals are small, sense amplifiers must be highly sensitive to correctly read the stored data.

One way to enhance the sensitivity of a sense amplifier is to employ a balanced sensing arrangement that takes advantage of the largely matching impedance characteristics of portions of the circuitry used to access the memory cells. Referring to the drawings,FIG. 1illustrates a conventional balanced sensing arrangement for a semiconductor memory. The memory circuitry inFIG. 1consists of memory sections20and22, multiplexers (“MUXes”)24and26, and sense amplifiers28that provide data output signals.

Each memory section20or22consists of an array of memory cells30accessed through word lines32and bit lines34. Each memory cell30is diagramatically shown as being at the intersection of a word line32and a bit line34. When a word line32in section20is activated, signals indicative of the data in cells30along that word line32are provided on associated bit lines34to MUX24which supplies a subset of the data signals on data lines36to sense amplifiers28. A similar activity occurs when a word line32in memory section22is activated. Signals indicative of the data in cells30along that word line32are furnished on associated bit lines34to MUX26which furnishes a subset of those data signals on data lines38to amplifiers28.

A balanced sensing arrangement is achieved by utilizing one memory section20or22as a reference array when a word line32is activated in the other section22or20for a read operation. During the read operation, none of cells32in the reference array are activated. Substantially no current flows through bit lines34in the reference array. However, both of MUXes24and26are activated so that sense amplifiers28are connected by way of data lines36to a subset of bit lines34in section20and by way of data lines38to a subset of bit lines34in section22.

The subset of bit lines34in memory section22presents largely the same impedance as the subset of bit lines34in memory section20. Accordingly, the impedance “seen” by sense amplifiers28along data lines38and the associated subset of bit lines34in section22largely matches the impedance “seen” by amplifiers28along data lines36and the associated subset of bit lines34in section20. Matching impedances at the input terminals to sense amplifiers28in this way reduces sensitivity to noise, thereby improving the sensing accuracy. Data lines36and38are, however, commonly quite long, especially when the memory ofFIG. 1is a large memory. The resultant increased impedance is disadvantageous.

Pitts, U.S. Pat. No. 6,052,308, describes an extension of the balanced sensing arrangement ofFIG. 1to a flash EPROM containing a group of memory arrays whose memory cells are formed with floating-gate field-effect transistors (“FETs”). In a floating-gate FET, a floating gate lies between a control gate and the FET's channel region. An n-channel floating-gate FET is programmed by placing electrons on the floating gate to raise the FET's threshold voltage. When the FET is selected for reading by providing an access voltage between the control gate and the FET's source, the access voltage is less than the threshold voltage so that the FET is turned off. This defines a low logic state commonly referred to as logic “0”. The FET is erased by removing electrons from the floating gate to reduce the threshold voltage. An access voltage applied between the control electrode and the source is then greater than the threshold voltage. The FET turns on and draws substantial current to establish a high logic state commonly referred to as logic “1”.

The floating-gate memory cells utilized in Pitts are of a type subject to an overerasure phenomenon in which the amount of electronic charge removed from a floating gate during erasure is occasionally so great that the cell is turned on even though the cell's word line is not activated. Such an overerased cell draws substantial current. Pitts can eliminate the overerasure by performing a “soft” programming operation on overerased cells. However, if a read operation were performed on one memory section20or22inFIG. 1at a time when the other section22or20contains an overerased cell, i.e., during erasure and/or prior to “soft” programming, the current flowing through the overerased cell could severely damage the sensing accuracy.

Pitts uses an array switching technique to address the overerasure problem. When a memory cell in one of the memory arrays is being read, the EPROM examines a group of associated memory arrays and chooses, as the reference array, an associated array not then undergoing erasure. This is cumbersome because it requires substantial circuitry to perform the array switching. Also, Pitts still needs to perform soft programming whenever overerasure occurs. It would be desirable to have a simple, highly sensitive arrangement for sensing data stored in the cells of a semiconductor memory, especially a flash EPROM of complex architecture.

GENERAL DISCLOSURE OF THE INVENTION

The present invention furnishes such a data sensing arrangement for an electronic memory having global bit lines that fully traverse the memory and local bit lines that only partially traverse the memory. The sensing arrangement of the invention employs impedance matching to achieve highly accurate data sensing with low sensitivity to noise. Selection/connection circuitry appropriately interconnects different memory portions, including the local and global bit lines, to implement the impedance matching in a highly efficient manner. The memory is preferably a flash EPROM whose memory cells are formed with floating-gate FETs of the split-gate type. Consequently, the present memory system is typically not subjected to cell overerasure difficulties and does not require measures, such as soft programming, to overcome overerasure.

The core of the present memory is a group of memory sections functionally arranged in section rows and section columns. Each memory section, sometimes referred to as a sector or block, contains a multiplicity of storage memory cells and a multiplicity of local bit lines. The memory cells are arranged in cell rows and cell columns. The number of cells in each cell column is typically the same across the memory. Each local bit line is connected to the cells in a different one of the cell columns. When the present memory is implemented as a flash EPROM, all the cells of each memory section are typically erased simultaneously and separately from all the cells in each other memory section.

The present memory is provided with multiple global bit lines, multiple data lines, a sense amplifier, and a reference current source. The global bit lines are allocated into global bit line sets respectively corresponding to the memory section columns. Each global bit line in each global bit line set is associated with a different plurality of the local bit lines in each of the memory sections of the corresponding section column. The data lines respectively correspond to the section columns such that each data line is associated with the global bit lines for the corresponding section column. The sense amplifier has a data input terminal, a reference input terminal, and an output terminal for providing an output signal indicative of a comparison between the signals at the input terminals. The reference current source provides a reference current to the amplifier's reference input terminal.

The memory of the invention contains further circuitry, to be described momentarily, that implements the impedance matching. An understanding of the further circuitry is facilitated by first looking at how the circuitry is to implement impedance matching when the sense amplifier is sensing data contained in a memory cell in one of the memory sections. This memory cell is connected through its local bit line, through the global bit line for that local bit line, and through the data line for the global bit line to the data input terminal of the amplifier. To achieve impedance matching, the reference input terminal needs to be connected to reference circuitry, including one or more reference lines, having largely the same impedance characteristics as the data line, the global bit line, and the local bit line that connect the amplifier's data input terminal to the cell.

In one embodiment of the present memory, the impedance-matching reference circuitry consists of lines that connect the reference input terminal of the sense amplifier to memory cells in a memory section, referred to as the reference memory section, in a different section row and a different section column than the memory section for the cell being read. The reference circuitry is formed with a data line, a global bit line, and a local bit line that connect the amplifier's reference input terminal to memory cells in the reference memory section.

The reference circuitry in the first embodiment is achieved by providing the memory system with suitable selection/connection circuitry. In addition to having the capability for selecting each local bit line, the selection/connection circuitry is operable (a) to connect each selected local bit line in each memory section of each section row and section column to the amplifier's data input terminal by way of (a1) the global bit line for the selected local bit line and (a2) the data line for that global bit line and (b) to largely simultaneously connect a reference one of the local bit lines in a reference one of the memory sections in another section row and another section column to the amplifier's reference input terminal by way of (b1) the global bit line, termed the reference global bit line, for the reference local bit line and (b2) the data line for the reference global bit line.

By operating the memory so that none of the memory cells along the local bit lines associated with the reference global bit line is selected, the sense amplifier reads a selected one of the cells along the selected local bit line. Due to the architecture of the memory, the reference local bit line, the reference global bit line, and the data line connected to the reference global bit line respectively have largely the same impedance characteristics as the local bit line, the global bit line, and the data line for the cell being read. Impedance matching thereby occurs at the input terminals of the sense amplifier to produce highly accurate data sensing.

The present memory system is provided with a separate reference memory section in a second embodiment. The reference memory section contains a reference bit line and a column of reference memory cells. The reference bit line is connected to the reference cells and to the reference input terminal of the sense amplifier. In the second embodiment, the impedance-matching reference circuitry is formed with the reference bit line, a global bit line for a section column different from the one that includes the memory section for the cell being read, and a data line which connects that global bit line to the amplifier's reference input terminal.

The reference circuitry is achieved by providing the memory with selection/connection circuitry that, in addition to having the capability for selecting each local bit line, is operable (a) to electrically connect each selected local bit line in each memory section of each of the section columns to the sense amplifier's data input terminal by way of (a1) the global bit line for the selected local bit line and (a2) the data line for the selected local bit line and (b) to largely simultaneously electrically connect a reference one of the global bit lines for another of the section columns to the amplifier's reference input terminal by way of the data line for the reference global bit line. By again operating the memory so that none of the cells along the local bit lines associated with the reference global bit line is selected, the sense amplifier reads a selected cell along the selected local bit line. Appropriately configuring the reference bit line, including arranging for the number of reference memory cells to be the same as the number of memory cells in each cell column of each memory section, enables the reference bit line, the reference global bit line, and the data line connected to the reference global bit line to respectively have largely the same impedance characteristics as the local bit line, the global bit line, and the data line for the cell being read. The resultant impedance matching at the amplifier's input terminals produces accurate data sensing.

A memory provided with impedance matching according to the invention typically includes a group of sense amplifiers, one for each bit of a word stored in the memory. For example, an implementation of the present memory may have sixteen sense amplifiers for reading a 16-bit word. In that case, the circuit connections and the circuit functions for the sense amplifier described above are basically repeated for each other sense amplifier.

The designation of one global bit line as a reference global bit line for another global bit line is typically done in advance. In contrast to what occurs in Pitts, the memory system of the invention typically does not require circuitry for switching the reference global bit lines for each so-selected global bit line. Similar comments apply to the local bit lines that serve as reference local bit lines for each local bit line in the first embodiment of the present memory system. The impedance-matched sensing circuitry of the present invention is thus less cumbersome than that of Pitts. In short, the present invention provides a substantial advance over the prior art.

Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same, or very similar, item or items.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description, elements that fall into sequences or are grouped into two-dimensional arrays are generally collectively identified by reference symbols without subscripts. An element's position in a sequence or two-dimensional array is indicated by using the collective reference symbol for the element followed by a subscript position indicator. Each of subscripts “i”, “j”, and “k” is a running integer for an arbitrary position in a sequence or two-dimensional array. Symbols “M”, “N”, “P”, “Q”, “R”, “S”, and “T” are fixed integers.

As used below, “connection” means an electrical connection except as otherwise indicated. Similarly, “line” means an electrical line or conductor. All FETs described below are n-channel insulated-gate FETs except as otherwise indicated.

FIG. 2illustrates a memory configured according to the invention for achieving impedance-matched data sensing. The memory ofFIG. 2contains a group of largely identical local storage memory sections40, a global row decoder42, a local column decoder44, a global column decoder46, data line control circuitry48, n largely identical sense amplifiers50, and n largely identical reference current sources52respectively corresponding to sense amplifiers50. Integer n is the number, e.g., 16, of bits contained in words stored in the memory.

Local memory sections40are functionally arranged in an array of M section rows and N section columns. Memory sections40are numbered40i,jinFIG. 2where section row number i runs from 0 to M−1, and section column number j runs from 0 to N−1. Each section40contains a multiplicity of storage memory cells54functionally arranged in an array of P cell rows and Q cell columns. Since sections40are largely identical, cell row size P and cell column size Q are respectively constant across the array of sections40. Likewise, cells54are largely identical.

Memory cells54are accessed through global word lines56and local bit lines58. Each cell54is specifically accessed through one global word line56and one local bit line58and, for illustration simplicity, is shown as being at the intersection of those two lines56and58.FIG. 6, dealt with below, presents further information on how each cell54is connected to its word line56and its local bit line58.

Word lines56extend fully across the array. Each word line56is associated with one memory section row, i.e., row of memory sections40, and is connected to all of memory cells54in one of the cell rows in each section40of the associated section row. Consequently, there are MP word lines56. InFIG. 2, word lines56are numbered56iwhere global row number i runs from 0 to MP−1.

Responsive to suitable address signals, global row decoder42provides row access signals on word lines56for selectively accessing memory cells54in order to perform read and write operations on cells54. More particularly, the row access signals normally cause cells54along only a selected one of word lines56to be activated at a time. Since word lines56pass fully through the array of memory sections40, cells54in one row of each of sections40along a memory section row are accessed together. Normally only part of cells54in a selected one of sections40in a section row are actually subjected to a read or write operation at a time. This column selection is achieved with column decoders44and46and data line control circuitry48as discussed below.

Local bit lines58extend only partially across the array of memory sections40. In particular, local bit lines58are divided into MN groups of Q lines58. Each group of Q local bit lines58extends fully across memory cells54in one of sections40but does not extend across cells54in any other section40. Accordingly, each group of Q lines58is local to one section40and essentially forms part of that section40. Each local bit line58is connected to all of cells54in a corresponding different one of the cell columns in that local bit line's section40. For each section40, local bit lines58are numbered58jinFIG. 2where local bit line number j runs from 0 to Q−1.

Responsive to suitable address signals, local column decoder44selectively connects local bit lines58to R global bit lines60that extend fully across the array of memory sections40. Global bit lines60are numbered60jinFIG. 2where global bit line number j runs from 0 to R−1. Global bit lines60are allocated into N global bit line sets respectively corresponding to the memory section columns. Each global bit line set consists of R/N lines60. For example, the global bit line set corresponding to the first memory section column (left-most inFIG. 2) is formed with R/N lines600–60R/N−1.

Each line60in each global bit line set is associated with a different plurality of S consecutive local bit lines50in each memory section40of the corresponding memory section column. For instance, global bit line60jis associated with local bit lines580–58S−1in each of sections40of the corresponding section column. Since there N section columns, each global bit line60is associated with N different pluralities of S local bit lines58. S equals NQ/R.

Local column decoder44selectively connects each global bit line60to the associated N pluralities of S local bit lines58but not to any other local bit line58. More particularly, decoder44normally connects each global bit line60to no more than one local bit line58in the N associated pluralities of S local bit lines58in memory sections40of the corresponding memory section column at a time.

Global column decoder46selectively connects global bit lines60to Nn data lines62in response to suitable address signals where, as indicated above, n is the number of sense amplifiers50. InFIG. 2, data lines62are numbered62jwhere data line number j runs from 0 to Nn−1. Each data line62is associated with a different plurality of T consecutive global bit lines60where T equals R/Nn because there are R lines60. For example, data line620is associated with global bit lines600–60T−1. Decoder46selectively connects each data line62to the associated plurality of T global bit lines60but not to any other global bit line60. More particularly, decoder46normally connects each data line62to no more than one of the associated plurality of T global bit lines60at a time.

Data lines62are allocated into n data line groups respectively corresponding to the n sense amplifiers50. Each data line group thereby contains N lines62. Lines62in each data line group respectively correspond to the memory section columns. That is, one line62in each data line group corresponds to each different section column. For example, the first data line group consists of the N lines620,62n,622n, . . .62Nn−n. The last data line group is formed with the N lines62n−1,622n−1,623n−1, . . .62Nn−1. In other words, the members of each data line group consists of every nth line62j.

Each of sense amplifiers50has a data input terminal (−), a reference input terminal (+), and a data output terminal. Each amplifier50amplifies the difference between the currents at its input terminals to provide its output terminal with an amplified data output signal B indicative of a comparison between the currents at the input terminals. The data input terminal of each amplifier50is connected to a corresponding different one of n amplifier data input lines64. The reference input terminal of each amplifier50is similarly connected to a corresponding different one of n amplifier reference input lines66. Amplifiers50are number50kinFIG. 2where sense amplifier number k, i.e., the data bit number, runs from 0 to n−1.

Data line control circuitry48selectively connects data input line64extending from each sense amplifier50to one or more, but not all, of data lines62in the corresponding data line group. Control circuitry48simultaneously connects reference input line66extending from that amplifier50to another one or more, but not all, of lines62in the corresponding data line group. None of data lines62connected to a data input line66at any time is simultaneously connected to corresponding reference input line64, and vice versa.

To the extent that any amplifier input line64or66is connected to more than one data line62at a time, global column decoder46nulls the effect of each connection in excess of one. As a result, the two input terminals of each sense amplifier50are respectively effectively connected to only two different lines62of the corresponding data line group at a time. In light of how column decoders44and46are controlled, these connections enable the impedance seen at the reference input terminal of each amplifier50to largely match the impedance seen at the data input terminal of that amplifier50.

Reference current sources52are respectively connected through reference input lines66to the reference input terminals of sense amplifiers50. Similar to amplifiers50, current sources52are numbered52kinFIG. 2where data bit number k again runs from 0 to n−1. Circuitry suitable for implementing each current source52is illustrated inFIG. 7and described below.

Each current source52provides a reference current IREFthat is supplied to the reference input terminal of corresponding sense amplifier50via corresponding reference input line66. Reference currents IREFare largely equal. Each current IREFis approximately 50% of the current flowing through a memory cell54when it is fully conductive. More particularly, each current IREFis normally 30–70% of the current flowing through a fully conductive one of cells54. Column decoders44and46and data line control circuitry48are controlled so that substantially no current is provided to the reference input terminal of each amplifier50by way of a path going through lines62,60, and58to any of cells54. Accordingly, the current at the reference input terminal of each amplifier50is normally substantially IREF.

The data input terminal of each sense amplifier50receives an input current IIN. When a memory cell is turned off, it draws essentially zero current and is typically considered to be in a low logic, or “0”, state. A cell54which is turned on and draws substantially the full memory cell current is, in a complementary manner, typically considered to be in a high logic, or “1”, state. Due to the connections which column decoders44and46and data line control circuitry48provide for sense amplifiers50by way of lines58,60,62, and64, current IINat the data input terminal of each sense amplifier50is normally either substantially zero or substantially the full memory cell current when that amplifier50is reading an associated one of cells54. If input current IINto each amplifier50sufficiently exceeds reference current IREF, that amplifier50generates its output signal B at a value indicating that cell54being read contains a “1”, and vice versa.

With the foregoing in mind, let each memory section40be referred to as “selected” when a read operation is to be performed on certain memory cells54in that section40. The basic principle for achieving impedance-matched sensing in the memory ofFIG. 2is to provide each section40, when it is selected, with a predesignated reference one of sections40in a different memory section row and a different memory section column than selected section40. For example, section40M−1,N−1could be the reference memory section for section400,0, and vice versa. Similarly, section40M−1,0could be the reference memory section for section400,N−1, and vice versa.

In reading n memory cells54along a selected word line56in a selected memory section40, column decoders44and46and control circuitry48selectively connect the data input terminal of a sense amplifier50to a different one of those n cells54by way of (a) local bit line58, referred to as the selected local bit line, for that cell54, (b) global bit line60, referred to as the selected global bit line, for selected bit line58, (c) data line62, referred to as the selected data line, for selected global bit line60, and (d) data input line64for that amplifier50. The data input terminal of each amplifier50thereby sees an input impedance along a composite data line formed with selected local bit line58, selected global bit line60, selected data line62, and associated data input line64.

Column decoders44and46and control circuitry48are configured and operable to simultaneously connect the reference input terminal of each sense amplifier50to a predesignated reference local bit line58in reference memory section40by way of (a) global bit line60, referred to as the global bit line, for reference local bit line58, (b) data line62, referred to as the reference data line, for reference global bit line60, and (c) reference input line66for that amplifier50. Consequently, the reference input terminal of each amplifier50sees a reference impedance along a composite reference line formed with reference local bit line58, reference global bit line60, reference data line62, and associated reference input line66. These four lines respectively have largely the same impedance characteristics as selected local bit line58, selected global bit line60, selected data line62, and associated data input line64of the composite data line for that amplifier50. The input terminals of each amplifier50thereby see largely equal impedances.

By arranging for each memory section40and its reference section40to be in different memory section rows, none of cells54in reference section40is accessed when selected section40is undergoing a read operation. Hence, substantially no current flows through the composite references lines to interfere with the data sensing by sense amplifiers50. Arranging for each section40and its reference section40to be in different section columns simplifies the configuration and operation of column decoders44and46and control circuitry48.

Local column decoder44contains local bit line logic68and MNQ local column switching FETs70. Each FET70is physically source-drain connected between one of global bit lines60and a corresponding different one of associated NS local bit lines58, i.e., the N pluralities of S lines58associated with that global bit line60. Local bit line logic68is connected by way of local column control lines72to the gate electrodes of FETs70for controlling their switching.

Responsive to suitable row and column address signals, local bit line logic68provides control lines72with local column control signals that cause certain of FETs70to turn on and connect R/N predesignated local bit lines58in selected memory section40respectively to their global bit lines60. The local column control signals also cause certain others of FETs70to turn on and connect R/N other predesignated local bit lines58in reference section40respectively to their global bit lines60. Each so-connected global bit line60is connected to one of the associated plurality of S local bit lines58, thereby partially implementing the column selection within selected and reference sections40.

The local column control signals provided by control logic68normally cause certain further ones of FETs70to turn on and simultaneously connect further predesignated local bit lines58in yet other memory sections40respectively to global bit lines60for those lines58. These other sections40are typical in the same two section rows as selected and reference sections40. For example, R/N predesignated local bit lines58are typically respectively connected to their global bit lines60in each of (a) half of sections40, including selected section40, along the section row for selected section40and (b) half of sections40, including reference section40, along the section row for reference section40. Global column decoder46nulls any effect that these further connections might have on the data sensing.

Global column decoder46contains global bit line logic74and R global column switching FETs76. Each FET76is physically source-drain connected between one of data lines62and one of the associated T global bit lines60. Logic74is connected by global control lines78to the gate electrodes of FETs76for controlling their switching.

Decoder46performs a selection on global bit lines60to accomplish two functions: (a) connect certain of lines60that pass through selected and reference memory sections40to data lines62and (b) null the excess connections, if any, that local column decoder44makes between local bit lines58and certain of global bit lines60. Responsive to suitable column address signals, global bit line logic74provides control lines78with global column control signals that cause certain of FETs76to turn on and connect n of global bit lines60that pass through selected section40respectively to their data lines62. The global column control signals also cause certain others of FETs76to turn on and connect n of global bit lines60that pass through reference section40respectively to their data lines62. Each so-connected data line62is connected to one of the associated plurality of T global bit lines60.

FIG. 2illustrates global column decoder46in a general manner. If any one of certain memory sections40, e.g., section40M−1,N−1, were the reference section for the diagonally opposite memory section, i.e., section400,0in this example, the global column control signals for FETs76connected to global bit lines60that pass through the first memory section column would also respectively be the global bit line control signals for FETs76connected to lines60that pass through the last section column.

The excess connections that local column decoder44makes between certain of global bit lines60and local bit lines58are nulled in global column decoder46by providing certain of the global column control signals at values that cause FETs76connected to those global bit lines60to be turned off, thereby preventing any of those lines60from being connected to any of data lines62. The control operations provided by column decoders44and46in combination with the selection of a word line56by row decoder42establishes which memory section40is selected for reading and which section40is the associated reference memory section. Accordingly, n selected bit lines58in selected section40are respectively connected through their global bit lines60to n data lines62, and n selected local bit lines58in reference section40are respectively connected through their global bit lines60to n other data lines62.

N, the number of memory section columns, is typically at least4. In that case, certain groups of data lines62are normally connected together within data line control circuitry48to form composite data lines. More particularly, data lines62are divided into groups consisting of every nth line62. One such group consists of lines620,62n, . . .62Nn−2n, and62Nn−n. Half, e.g., the lower half, of lines62in each such group are typically connected together to form one composite data line. The remaining half, i.e., the upper half in this example, of lines62in that group are likewise typically connected together to form another composite data line.

Control circuitry48contains data line control logic80and data line switching FETs82. One half of FETs82are respectively physically drain-source connected between the composite data lines, on one hand, and data input lines64to the data input terminals of sense amplifiers50, on the other hand. The remaining half of FETs82are similarly respectively physically drain-source connected between the composite data lines, on one hand, and reference input lines66to the reference input terminals of amplifiers50, on the other hand. Logic80is connected by way of data control lines84to the gate electrodes of FETs82for controlling their switching.

Responsive to suitable column address signals, data line control logic80provides control lines84with data control signals that cause certain of FETs82to turn on and respectively connect data input lines64to n composite data lines that are respectively connected to n selected local bit lines58in selected memory section40by way of (a) global bit lines60for those local bit lines58and (b) data lines62for those global bit lines60. The data control signals also cause certain others of FETs82to turn on and respectively connect reference input lines66to n composite data lines that are respectively connected to n reference local bit lines58in reference section40by way of (a) associated reference global bit lines60and (b) data lines62for those reference global bit lines60. Consequently, the connections needed for impedance-matched sensing are achieved.

A further understanding of the memory ofFIG. 2can be achieved by examiningFIG. 3which illustrates a partial implementation of the memory ofFIG. 2. The number M of memory section rows and the number N of memory section columns are both4inFIG. 3. Consequently, the implementation ofFIG. 3contains sixteen local memory sections40ranging from memory section400,0to memory section403,3.

Several simplifications have been made inFIG. 3to facilitate explaining the memory system operation. Firstly,FIG. 3only depicts one sense amplifier50and the associated circuit portions. Secondly, each memory section40inFIG. 3is provided with only one memory cell54, one associated word line56, and one associated local bit line58. Since there are four memory section rows, four word lines56are shown inFIG. 3. These lines56are respectively labeled56A,56B,56C, and56Dgoing from the first section row to the last section row.

Thirdly, only one global bit line60is provided for each memory section column inFIG. 3. Inasmuch as there are four section columns inFIG. 3, four global bit lines60are shown inFIG. 3. These lines60are respectively labeled60E,60F,60G, and60Hgoing from the first section column to the last section column. Four illustrated data lines62are similarly respectively labeled62E,62F,62G, and62H.

Logic68in local column decoder44consists of a first level of OR logic gates90, a level of AND logic gates92, and a second level of OR logic gates94. Logic74in global column decoder46consists of OR logic gates96. Logic80in control circuitry48similarly consists of OR logic gates98. Each of OR gates90,94,96, and98is typically implemented as a NOR logic gate with an output inverter. Each AND gate92is similarly typically implemented as a NAND logic gate with an output inverter.

Row address signals R0, R1, R2, and R3and column address signals C0, C1, C2, and C3are variously provided to logic gates90,92,94,96, and98. Row address signals R0–R3respectively identify the four memory section rows. Column address signals C0–C3similarly respectively identify the four memory section columns. In an implementation where each memory section40has multiple columns (and rows) of memory cells, logics68and74are provided with additional logic and with additional column control signals to select among the multiple columns in each section40.

A memory section40is selected for a read operation by placing the row and column address signals for its section row and section column at logic “1” while the remaining ones of address signals R0–R3and C0–C3are placed at logic “0”. An examination of logic68in local column decoder44ofFIG. 3shows that adjusting address signals R0–R3and C0–C3in this way causes four of FETs70to turn on. One of conducting FETs70connects one global bit line60to the memory section40intended to be selected. Another of conducting FETs70connects another line60to a section40in the same section row as selected section40. The remaining two conducting FETs70connect two remaining lines60respectively to two sections40in a section row not having selected section40.

A similar examination of logic74in global column decoder46ofFIG. 3shows that two of FETs76are turned on. One of conducting FETs76connects one data line62to global bit line60connected to local bit line58in selected memory section40. The other conducting FET76connects another data line62to global bit line60connected to local bit line58in section40of a different section row than selected section40. This establishes that other section40as the reference memory section. The remaining two FETs78are off. The connections that local column decoder44provides from the other two sections40are nulled. The net result is that column decoders44and46together cause one reference section40to be established for selected section40.

The following table identifies the reference memory section for each selected memory section in the implementation ofFIG. 3:

An examination of logic80in data line control circuitry48shows that adjusting address signals R0–R3and C0–C3in the above-mentioned way so as to select one memory section40and assign another section40as the reference section for selected section40causes two of FETs82to be turned on. One of conducting FETs82connects the data input terminal of sense amplifier50through data input line64to a data line62connected through associated global bit line60to local bit line58in selected section40. The other conducting FET82connects the reference input terminal of amplifier50through reference input line66to a data line62connected through associated global bit line60to local bit line58in reference section40. Impedance matching at the input terminals of amplifier50is thereby achieved.

FIG. 4illustrates another memory configured according to the invention for achieving impedance-matched data sensing. The memory ofFIG. 4contains local memory sections40, global row decoder42, a local column decoder100, global column decoder46, data line control circuitry48, n sense amplifiers50, n reference current sources52, and a reference local memory array102. Local column decoder100in the memory ofFIG. 4is located in the same place as local column decoder44in the memory ofFIG. 2. Although, decoder100functions differently than decoder44, decoder100selectively connects local bit lines50to global bit lines60in response to suitable address signals just as decoder44does. Subject to this difference, components40,42,46,48,50, and52in the memory ofFIG. 4are configured and operable the same as in the memory ofFIG. 2.

Reference local memory array102contains a multiplicity of largely identical reference memory cells104functionally arranged in P cell rows and n cell columns. Reference memory cells104are largely identical to storage memory cells54. Reference cells104are connected to P reference word lines106and n reference bit lines108. Each cell104is specifically connected to one line106and one line108and, for illustration simplicity, is shown inFIG. 4as being at the intersection of those two lines106and108. Cells104are internally connected so as to be permanently non-conductive. Further information on memory array102, including the internal connections of cells104, is presented inFIG. 8discussed below.

Reference bit lines108are numbered108kinFIG. 4where data bit number k runs from 0 to n−1. In addition to being electrically connected to P reference cells104, each reference bit line108is connected between a corresponding different one of reference current sources52and the reference input terminal of corresponding sense amplifier50. Reference bit lines108are basically local to reference array102. Accordingly, array102can be divided into n reference memory sections104/108, each of which contains a column of P reference cells104and one bit line108connected to those cells104. Since each cell column in each memory section40contains P memory cells54, each section104/108serves as a reference memory section for associated amplifier50.

Local column decoder100contains local bit line logic110and local column switching FETs70. Logic110differs from local bit line logic68in local column decoder44of the memory ofFIG. 2. However, the combination of logic110and FETs70is interconnected between local bit lines58and global bit lines60in the memory ofFIG. 4in the same way that the combination of logic68and FETs70is interconnected between lines58and lines60in the memory ofFIG. 2. In reading n of memory cells54along a selected word line56in a selected memory section40, connection paths from the data input terminals of sense amplifiers52to those cells54go through the same circuit elements, including FETs70,76, and82, in the memory ofFIG. 4as in the memory ofFIG. 2. The data input terminal of each amplifier52sees an input impedance along a line having three basic segments: (a) a selected data line62connected to T FETs76, (b) a selected global bit line60connected to NS FETs70, and (c) a selected local bit line58connected to P cells54.

The basic principle for achieving impedance-matched sensing in the memory ofFIG. 4is to connect the reference input terminal of each sense amplifier50to a pair of reference lines that together have largely the same impedance characteristics as a data line62, a global bit line60, and a local bit line58. In particular, one of the reference lines has the same impedance characteristics as a local bit line58. This reference line is implemented with one of reference bit lines108. The other reference line, referred to as the global bit/data reference line, is implemented with a data line62, referred to as reference data line62, and a global bit line60, referred to as reference global bit line60, connected to reference data line62with all of FETs70connected to reference global bit line60turned off to avoid having the amplifier's input terminal see impedance from any of local bit lines58connected to those FETs70.

As with local bit line logic68in the memory ofFIG. 2, local bit line logic110in the memory ofFIG. 4provides control lines72with local column control signals that cause certain of FETs70to turn on and connect R/N local bit lines58in selected memory section40respectively to their global bit lines60. Each of these so-connected global bit lines60is connected to one of the associated plurality of S local bit lines58so as to partially implement the column selection within selected memory section40.

Likewise similar to what occurs in logic68in the memory ofFIG. 2, the local column control signals provided by logic110in the memory ofFIG. 4normally cause certain further FETs70to turn on and simultaneously connect further local bit lines58in one or more memory sections40in the same section row as selected section40respectively to global bit lines60for those local bit lines58. For instance, R/N predesignated local bit lines58are typically respectively connected to their global bit lines60in each of half of sections40, including selected section40, along the section row for selected section40. Global bit line decoder46nulls any effect that these further connections might have on the data sensing.

Unlike what occurs in the memory ofFIG. 2, the local column control signals provided by logic110in the memory ofFIG. 4cause all of FETs70for local bit lines58in memory sections40along every memory section row other than the section row for selected section40to be turned off when the local column control signals cause certain of FETs70to turn on in selected section40. Consequently, none of global bit lines60is here connected to any of local bit lines58for any section40in a section row other than the section row for selected section40. Taking note of the fact that logic68in the memory ofFIG. 2establishes a place for reference memory section40in a different section row than that for selected section40, logic110in the memory ofFIG. 4does not establish such a place for reference section40.

Global column decoder46operates the same in the memory ofFIG. 4as in the memory ofFIG. 2but achieves different connections because logic110provides different connections than logic68. More particularly, decoder46in the memory ofFIG. 4performs a selection on global bit lines60to accomplish three functions: (a) connect certain global bit lines60that pass through selected memory section40to their data lines62, (b) null the excess connections, if any, that logic110makes between local bit lines58and certain other global bit lines60, and (c) establish the global bit/data reference lines for sense amplifiers50by connecting certain other data lines62to yet other global bit lines60connected to FETs70that are all turned off. Decoder46accomplishes the first two functions in the same way in the memory ofFIG. 4as in the memory ofFIG. 2.

With respect to the third function, all of FETs70in the memory ofFIG. 4are turned off in at least one memory section column due to the operation of local bit line logic110. Global bit line logic74in global column decoder46provides control lines78with global column control signals that cause certain of FETs76in one such memory section column to turn on and connect n of global bit lines60to their data lines62. These connections provide the global bit/data reference lines for sense amplifiers50. The control operations provided by column decoders44and46in combination with the selection of a local bit line56by row decoder42thus establishes which memory section40is selected for a read operation and which combinations of global bit lines60and data lines62form the global bit/data reference lines. Lines60and62of the global bit/data reference lines are the same lines that connect to reference section40in the memory ofFIG. 2.

As mentioned above, data line control circuitry48operates the same in the memory ofFIG. 4as in the memory ofFIG. 2. Hence, control circuitry48connects the n data input lines64extending from the data input terminals of sense amplifiers50respectively to n data lines62that are respectively connected through n selected global bit lines60to n selected local bit lines58of selected memory section40. Since lines60and62of the global bit/data reference lines are lines that connect to reference memory section40in the memory ofFIG. 2, control circuitry48in the memory ofFIG. 4also connects the n reference input lines66extending from the reference input terminals of amplifiers50respectively to the n global/data reference lines. Reference bit lines108are permanently connected to the reference input terminals of amplifiers50. Consequently, the configuration needed for impedance matching in the memory ofFIG. 4is established.

A further understanding of the memory ofFIG. 4can be achieved by examiningFIG. 5which illustrates a partial implementation of the memory ofFIG. 4. The embodiment ofFIG. 5implements the memory ofFIG. 4in the same way that the embodiment ofFIG. 3implements the memory ofFIG. 2. Hence, the difference betweenFIGS. 3 and 5is that (a) local column decoder46in the implementation ofFIG. 3is replaced with local column decoder100in the implementation ofFIG. 5and (b) reference current sources52are coupled through reference bit lines108and reference local memory array102to the reference input terminals of sense amplifiers50. Local bit line logic110in local column decoder100in the implementation ofFIG. 5contains OR logic gates90and AND logic gates92. OR logic gates94are absent in logic110. All of the simplifications made inFIG. 3are made inFIG. 5.

As with the implementation ofFIG. 3, one local memory section40, i.e., memory section40at the intersection of a particular memory section row and a particular memory section column, is selected for a read operation in the implementation ofFIG. 5by placing the row and column address signals for that section row and section column at logic “1” while placing the others of row address signals R0–R3and column address signals C0–C3at logic “0”. An examination of logic110in decoder100ofFIG. 5shows that adjusting address signals R0–R3and C0–C3in this way causes two of FETs70to turn on. One of conducting FETs70provides a connection from one global bit line60to a local bit line58in memory section40intended to be selected. The other conducting FET70provides a connection from another global bit line60to a global bit line58of a memory section40in the same section row as selected section40. Remaining FETs70are turned off.

An examination of global bit line logic74in global bit line decoder46ofFIG. 5shows, as inFIG. 3, that two of FETs76are turned on. One of conducting FETs76again provides a connection from one of data lines62to selected global bit line60connected to selected local bit line58in selected memory section40. The other conducting FET76provides a connection from another data line62to a global bit line60connected to FETs70that are all turned off. This connection establishes the global bit/data reference line. Since the remaining two FETs76are turned off, the connection that logic100provides for the other section40in the same section row as selected section40is nulled.

An examination of data line control logic80in data line circuitry48ofFIG. 5shows, again as inFIG. 3, that two of FETs82are turned on. One of conducting FETs82connects the data input terminal of sense amplifier50through data input line64to data line62connected through selected global bit line60to selected local bit line58in selected memory section40. The other conducting FET82connects the reference input terminal of sense amplifier50through reference input line66to lines62and60that form the global bit/data reference line. Since the amplifier's reference input terminal is already connected to reference bit line108, impedance matching at the input terminals of amplifier50is achieved.

The array formed with local memory sections40in each ofFIGS. 2–5is typically implemented in a semiconductor integrated circuit as one of a group of such memory arrays. Eight of these memory arrays are typically provided in a memory integrated circuit. Only one set of n sense amplifiers50and n reference current sources52is typically provided in an integrated circuit. In the case ofFIGS. 4 and 5, only one reference memory array102and one set of n reference bit lines108are likewise provided in such an integrated circuit. Suitable multiplexer circuitry is utilized to multiplex amplifiers50among the memory arrays.

The memories ofFIGS. 2–5are typically implemented as flash EPROMs. Each memory section40is then sometimes referred to as a sector or bank. The flash EPROM is provided with a capability for simultaneously erasing all memory cells54in any of sections40. The erasure of each section40is performed separately, and thus can be done at a different time, than the erasure of any other section40.

In one embodiment where the memory ofFIG. 4or5is implemented as a flash EPROM, the number n of sense amplifiers50(or bits in a word) is16, the number M of memory section rows is4, and the number N of memory section columns is4. In each memory section40, the number P of cell rows is512, the number Q of cell columns is1024, the number R of global bit lines60is256, the number S of local bit lines58associated with a global bit line60is4, and the number T of global bit lines60associated with a data line62is16. The memory is also typically provided with redundant word and bit lines and associated memory cells that can be wired into the memory should any of components54,56,58,104,106, and108be defective.

FIG. 6depicts a split-gate floating-gate FET120suitable for implementing each memory cell54in producing the memory of anyFIGS. 2–5as a flash EPROM. Split-gate FET120has a source122, a drain124, a floating gate126overlying the FET's channel region near source122, a control gate128overlying floating gate126, and a select gate130overlying the channel region near drain124. Select gate130and drain124are respectively connected to a word line56and a local bit line58. Source122and control gate128are respectively connected to additional lines132and134.

Appropriate voltages are variously placed on lines56,58,132, and134for programming and erasing memory cell54/split-gate FET120inFIG. 6. Programming entails introducing electrons onto floating gate126to raise the FET's threshold voltage. Erasing entails removing electrons from floating gate126to lower the threshold voltage.

The channel region of split-gate FET120is formed with the channel portion below floating gate126and the channel portion below select gate130. The two channel portions are arranged in series. Both channel portions must be electrically conductive for FET120to be turned on. FET120is turned off when at least one of the channel portions is electrically non-conductive.

A control voltage is applied between control gate128and source122of split-gate FET120via lines134and132. During read operations, the value of the control voltage lies between the high programmed value of the FET's threshold voltage and the low erased value of the threshold voltage. When FET120is in a programmed condition, the channel portion below floating gate126is thus non-conductive. Conversely, the channel portion below floating gate126is conductive when FET120is in an erased condition.

A selection voltage is applied between select gate130and source122via lines56and132. If split-gate FET120is selected to be read, the selection voltage is sufficiently high to cause the channel portion below select gate130to be conductive. When FET120is in an erased condition, both channel portions are conductive so that FET120is turned on. A logic value, typically a logic “1”, characteristic of a conductive transistor is read out of memory cell54/FET120.

When split-gate FET120is in a programmed condition, the channel portion below floating gate126remains non-conductive even though the channel portion below control gate130is conductive. As a result, FET120is turned off. A logic value, typically a logic “0”, characteristic of a non-conductive transistor is read out of memory cell54/FET120. If FET120is not selected to be read, the selection voltage applied between select gate130and source122is sufficiently low that the channel portion below select gate130is non-conductive. Hence FET120is turned off when it is not selected.

If excess electrons are removed from floating gate126during an erasure operation, the channel portion below floating gate126may invert, i.e., go into a conducting condition, even though the selection voltage applied between select gate130and source122is not at a high reading value. However, the channel portion below select gate130will still be non-conductive. Inasmuch as a conductive path from source122to drain124through the channel region will not be present, FET120will remain off. Consequently, overerasure does not cause a problem in split-gate FET120ofFIG. 6.

FIG. 7illustrates circuitry suitable for implementing reference current sources52. The illustrated circuitry includes a split-gate floating-gate FET140, a pair of largely identical p-channel FETs142A and142B, an FET144, and n FETs146that respectively implement reference sources52. FETs142A and142B are arranged in a current-mirror configuration with their sources connected to a source of a high supply voltage VDD.

P-channel FET142A is drain-drain coupled to split-gate FET140whose source is connected to a source of a low supply voltage VSS, typically ground reference. One or more FETs (not) shown may be drain-source inserted between the drains of FETs140and142A for controlling current sources52. Voltage signals VSRand VCRare respectively supplied to the select and control gates of FET140. During read operations, signals VSRand VCRare both set at VDD.

P-channel FET142B is drain-drain connected to FET144whose source is connected to the VSSsupply. Split-gate FET140, which is substantially identical to split-gate FET120inFIG. 6, is in an erased condition and thus has a low threshold voltage. With signals VSRand VCRbeing at VDDat during read operations, FET140draws a current approximately equal to2IREF. Because largely identical FETs140A and140B form a current mirror, a current approximately equal to2IREFalso flows through FET144during read operations.

The sources of FETs146are connected to the VSSsupply. Each FET146is arranged in a current-mirror configuration with FET144. However, each FET146is of approximately half the channel width of FET144. Each FET146thereby draws a current IREFso as to implement one of reference current sources52.

FIG. 8depicts how reference local memory array102is typically implemented in the memory ofFIG. 4or5when memory cells54are formed with split-gate FETs120as shown inFIG. 6. Each reference memory cell104in array102ofFIG. 8consists of a split-gate floating-gate FET150substantially identical to each FET120. Each split-gate FET150has a source152, a drain154, a floating gate156, a control gate158, and a select gate160arranged the same as elements122,124,126,128and130in each FET120. Drains154are connected to reference bit line108. FETs150are maintained in an always-off condition by providing low supply voltage VSSto sources152and gates158and160.

While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, the principles of invention can be applied to volatile memories, such as random-access memories of the static or dynamic type. In addition to EPROMs, the principles of the invention can also be applied to other non-volatile memories such as read-only memories and programmable read-only memories.

Each of memory cells54and104can be implemented with a split-gate floating-gate FET in which the select and control gates are merged together to form a composite control gate. Cells54and104can also be implemented with stacked-gate floating-gate FETs. Various modifications and applications may thus be made by those skilled in the art without departing from the true scope of the invention as defined in the appended claims.