Vertical capacitor structure having capacitor in cavity and method for manufacturing the same

A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a capacitor structure and a method, and to a vertical capacitor structure and a method for manufacturing the vertical capacitor structure.

2. Description of the Related Art

A comparative circuit may include one or more passive devices, where a passive device is a component such as a capacitor, a resistor or an inductor. To achieve microminiaturization, there is a trend to integrate passive devices into a semiconductor device. However, a plane type capacitor includes three stacked plane layers, and when integrated by disposing the capacitor on a surface of an insulating layer, the capacitor can occupy a large space. In addition, within a limited area, the capacitance of the capacitor is low.

SUMMARY

In some embodiments, a vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

In some embodiments, a capacitor component includes a first conductive layer, a first dielectric layer and a second conductive layer. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The capacitor component has at least one first portion in a truncated hollow cone shape, and a second portion in a substantially plane shape extending from a lower edge of the first portion.

In some embodiments, a method for manufacturing a vertical capacitor structure includes: (a) forming a cavity in a substrate; (b) forming at least one pillar in the cavity; (c) forming a first conductive layer covering and conformal to the cavity of the substrate and the pillar, wherein the first conductive layer is insulated from the substrate and the pillar; (d) forming a first dielectric layer covering and conformal to the first conductive layer; and (e) forming a second conductive layer covering and conformal to the first dielectric layer, wherein the first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

DETAILED DESCRIPTION

To improve the capacitance of the plane type capacitor, a vertical capacitor is provided. In a method for manufacturing an example vertical capacitor, a glass wafer (or a glass substrate) is provided, and a plurality of holes is formed thereon by, for example, drilling. Then, the capacitor is formed on the side walls of the holes. However, an aspect ratio of the holes may not be large enough, thus the capacitance of such vertical capacitor is constrained. In a method for manufacturing another example vertical capacitor, a silicon wafer is etched to form a plurality of deep holes to increase a surface area of thereof. An aspect ratio of the deep holes may be as large as about 20:1. Then, the surface of the silicon wafer is polarized by an implanter process, such that the surface of the silicon wafer is doped with N/P to form a conductive surface. A dielectric layer, a conductive layer and electrodes are then formed on the conductive surface of the silicon wafer, thus forming the vertical capacitor. However, the etching process for the deep holes and the implanter process may be difficult and expensive.

The present disclosure addresses at least the above concerns and provides for a method for an improved vertical capacitor structure, and improved techniques for manufacturing the vertical capacitor structure. The vertical capacitor may be manufactured without the need of the etching process for the deep holes and the implanter process

FIG. 1illustrates a cross-sectional view of a vertical capacitor structure1according to some embodiments of the present disclosure.FIG. 2illustrates a cross-sectional view taken along line I-I of the vertical capacitor structure1shown inFIG. 1. The vertical capacitor structure1includes a substrate2, at least one pillar3, a first conductive layer41, a first dielectric layer42, a second conductive layer43, a dielectric structure5and a circuit layer6.

The substrate2may be a substrate of any type. For example, the substrate2may be made of semiconducting material (e.g., silicon) or insulating material (e.g., glass). The substrate2has an upper surface21and defines a cavity20recessed from the upper surface21. As shown inFIG. 1, the cavity20is defined by a bottom surface201and a lateral surface202. For example, the lateral surface202extends from an edge of the bottom surface201to the upper surface21. In some embodiments, the lateral surface202may be substantially perpendicular to the bottom surface201and the upper surface21. The bottom surface201and the upper surface21may be substantially parallel to each other.

In some embodiments, the substrate2may include an insulating layer26(e.g., a barrier layer). The insulating layer26is disposed in and covers the cavity20, such as covering the bottom surface201and the lateral surface202. The insulating layer26may further cover the upper surface21of the substrate2. Due to the arrangement of the insulating layer26, the substrate2is insulated from other components disposed thereon, such as the first conductive layer41. For example, the insulating layer26may be formed by oxidizing surfaces of the substrate2(e.g., the upper surface21, and the bottom surface201and the lateral surface202of the cavity20). A material of the insulating layer26may be silicon oxide. However, the insulating layer26may be omitted if the substrate2is made of an insulating material (e.g., glass).

The pillar3is disposed in the cavity20of the substrate2.FIGS. 1 and 2show 2×2 pillars3for illustration purpose. In some embodiments, the vertical capacitor structure1may include at least about 20×20 pillars3. However, the amount and arrangement of the pillar3are not limited in the present disclosure. The pillar3has a bottom surface31, an upper surface32opposite to the bottom surface31, and a lateral surface33extending between the bottom surface31and the upper surface32. As shown inFIG. 1, the pillar3stands on the insulating layer26. The bottom surface31is disposed on and contacts the insulating layer26. That is, the bottom surface31is a boundary between the pillar3and the insulating layer26. For example, the bottom surface31is adhered to the insulating layer26. However, in other embodiments, the insulating layer26may be omitted, thus the pillar3may stand directly on the bottom surface201of the cavity20of the substrate2. That is, the bottom surface31is a boundary between the pillar3and the substrate2. In some embodiments, a height of the pillar3may be substantially equal to the depth of the cavity20of the substrate2.

As shown inFIG. 1, the pillar3tapers upward. In some embodiments, the pillar3is in a truncated cone-shape (as shown inFIG. 14). For example, the pillar3may be in a shape of a right circular cone, while a portion including an apex of the circular cone is omitted. Accordingly, an area of the bottom surface31may be greater than an area of the upper surface32. The lateral surface33is not perpendicular to the bottom surface201of the cavity20of the substrate2. For example, an angle θ between the lateral surface33of the pillar3and the bottom surface201of the cavity20of the substrate2is in a range of about 91 degrees to about 95 degrees.

The pillar3is preferably made of an insulating material. For example, the pillar3may be made of a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. In some embodiments, a material of the pillar3is different from a material of the substrate2and a material of the insulating layer26.

In some embodiments, the pillar3has a minimum diameter “D”. For example, the minimum diameter “D” may be located at or adjacent to the upper surface32of the pillar3. A pitch “P” is defined as a distance between the centers of adjacent two pillars3. The pitch “P” is substantially equal to or greater than twice the minimum diameter “D”. If the pitch “P” is too small, other components (e.g., the first conductive layer41, the first dielectric layer42and the second conductive layer43) disposed on the adjacent two pillars3may contact each other, thus forming a short circuit therebetween. On the other hand, an increased “P” may reduce the maximum amount of the pillars3disposed in the cavity20of the substrate2. For example, the minimum diameter “D” may be about 20 μm and the pitch “P” may be equal to or greater than about 40 μm.

The first conductive layer41is disposed in the cavity20of the substrate2and on the pillar3. The first conductive layer41covers and is conformal to the cavity20of the substrate2and the pillar3. For example, the first conductive layer41covers and is conformal to the upper surface32and the lateral surface33of the pillar3, and covers the insulating layer26disposed on portions of the bottom surface201of the cavity20which is not covered by the pillar3, the lateral surface202of the cavity20, and the upper surface21of the substrate2, such that the first conductive layer41is insulated from the substrate2. The first conductive layer41is further disposed on the upper surface21of the substrate2. However, in other embodiments, the first conductive layer41may directly contact and be conformal to the upper surface32and the lateral surface33of the pillar3, portions of the bottom surface201of the cavity20which is not covered by the pillar3, the lateral surface202of the cavity20, and the upper surface21of the substrate2. The first conductive layer41has a pad portion413on the upper surface21of the substrate2. The first conductive layer41may be made of a conductive material, and may be formed by physical or chemical vapor deposition. A thickness of the first conductive layer41may be about 0.5 μm to about 3 μm.

The first dielectric layer42covers and is conformal to the first conductive layer41. For example, the first dielectric layer42is disposed on and contacts the first conductive layer41. The first dielectric layer42may further be disposed on the upper surface21of the substrate2. The first dielectric layer42covers the first conductive layer41on the upper surface21of the substrate2, while the pad portion413of the first conductive layer41is exposed from the first dielectric layer42. The first dielectric layer42may be made of a dielectric material, such as Ta2O5, Al2O3, TiO2or HfO2. A relative permittivity of the first dielectric layer42may be about 8 to about 80. The first dielectric layer42may also be formed by physical or chemical vapor deposition, or by atomic layer deposition (ALD). A thickness of the first dielectric layer42may be about 10 nm to about 20 nm.

The second conductive layer43covers and is conformal to the first dielectric layer42. For example, the second conductive layer43is disposed on and contacts the first dielectric layer42. The second conductive layer43may further be disposed on the upper surface21of the substrate2. The second conductive layer43has a pad portion433on the upper surface21of the substrate2. The second conductive layer43may be made of a conductive material, and may be formed by physical or chemical vapor deposition. A thickness of the second conductive layer43may be about 0.5 μm to about 3 μm.

The first conductive layer41, the first dielectric layer42and the second conductive layer43jointly form a capacitor component4. That is, the capacitor component4may include the first conductive layer41, the first dielectric layer42, and the second conductive layer43. The capacitor component4is a vertical capacitor. A cross section of the capacitor component4, as shown inFIG. 1, is substantially in a serpentine shape or a rectangular wave shape.

The capacitor component4may have at least one first portion44, a second portion45, a third portion46and a fourth portion47. The first portion44is in a truncated hollow cone shape, and is disposed on and conformal to the pillar3. That is, the first portion44is disposed on the upper surface32and the lateral surface33of the pillar3. The first portion44may taper upward. The second portion45extends from a lower edge of the first portion44to the edge of the bottom surface201of the cavity20of the substrate2, and is disposed on a bottom surface201of the cavity20of the substrate2. The second portion45is substantially in a plane shape. The third portion46extends from an edge of the second portion45to the top edge of the cavity20of the substrate2, and is disposed on a lateral surface202of the cavity20of the substrate2. The third portion46is substantially perpendicular to the second portion45. An angle θ at an intersection of the first portion44and the second portion45is in a range between about 91 degrees to about 95 degrees. The fourth portion47extends from an upper edge of the third portion46, and is disposed on the upper surface21of the substrate2. The fourth portion47is substantially perpendicular to the third portion46.

In some embodiments, the capacitor component4has a plurality of first portions44, and the second portion45connects the first portions44. A pitch “P” between adjacent two of the first portions44is equal to or greater than twice a minimum diameter “D” of the first portions44.

The dielectric structure5is disposed on and covers the capacitor component4. The dielectric structure5is disposed in the cavity20and on the upper surface21of the substrate2. For example, the dielectric structure5fills the cavity20of the substrate2, and has an upper surface51which may substantially be planar. A material of the dielectric structure5may include an insulating material, a passivation material, a dielectric material or a solder resist material, such as, for example, a benzocyclobutene (BCB) based polymer or a polyimide (PI). As shown inFIG. 1, the dielectric structure5covers the first portion44of the capacitor component4. That is, the peripheral outer surface of the first portion44of the capacitor component4is surrounded by the dielectric structure5. The dielectric structure5defines a first opening54extending through the dielectric structure5to expose a portion of the first conductive layer41, and a second opening56extending through the dielectric structure5to expose a portion of the second conductive layer43. The first opening54and the second opening56may be located on the upper surface21of the substrate2. For example, the first opening54exposes the pad portion413of the first conductive layer41. The second opening56exposes the pad portion433of the second conductive layer43.

The circuit layer6is disposed on the upper surface51, and in the first opening54and the second opening56of the dielectric structure5. The circuit layer6may be a redistribution layer (RDL) that includes a trace63, a first terminal64and a second terminal66. The trace63is disposed on the upper surface51of the dielectric structure5. The first terminal64is disposed in the first opening54of the dielectric structure5and contacts the first conductive layer41, such as the pad portion413of the first conductive layer41. The second terminal66is disposed in the second opening56of the dielectric structure5and contacts the second conductive layer43, such as the pad portion433of the second conductive layer43. As can be seen inFIG. 1, the circuit layer6includes a seed layer61and a conductive layer62. The seed layer61may be made of copper and/or titanium, and the conductive layer62may be made of copper.

In the vertical capacitor structure1, since the capacitor component4(including the first conductive layer41, the first dielectric layer42and the second conductive layer43) is conformal to the cavity20of the substrate2and the pillar3, a total area of the capacitor component4, especially of the first dielectric layer42, is dramatically increased. Accordingly, a capacitance density of the vertical capacitor structure1(e.g., the capacitance density of the capacitor component4) is also increased.

Comparing to the exemplary vertical capacitor structure mentioned above, since the vertical capacitor structure1utilizes the pillars3, instead of deep holes, to increase the surface area of the substrate, the etching process for forming deep holes can be omitted. Besides, the implanted process is not necessary for forming the vertical capacitor structure1.

The capacitance “C” of the capacitor component4may be calculated by using the equation below, with “κ” representing a relative permittivity of the first dielectric layer42, “ε0” representing vacuum permittivity, “A” representing a total area of the first dielectric layer42, and “d” representing a thickness of the first dielectric layer42.

In some embodiments, an area of the bottom surface201may be 800 μm×800 μm, and a depth of the cavity20may be about 100 μm. The minimum diameter “D” of the pillar3may be about 20 μm, and the pitch “P” between adjacent two pillars3may be about 20 μm. The height of the pillar3is substantially equal to the depth of the cavity20. The thickness of the first dielectric layer42may be about 10 nm to about 20 nm, and the relative permittivity of the first dielectric layer42may be about 8 to about 80. The “capacitance density” may be defined as a capacitance in a predetermined area, e.g., the capacitance of the capacitor component4divided by the area of the capacitor component4on a plane of the upper surface21of the substrate2, which is approximately the area of the bottom surface201. According to the above criteria, a capacitance density of the capacitor component4may be greater than about 70 nF/mm2.

FIG. 3illustrates a cross-sectional view of a vertical capacitor structure1aaccording to some embodiments of the present disclosure. The vertical capacitor structure1ais similar to the vertical capacitor structure1shown inFIGS. 1 and 2, except for the structure of the pillar3a.

As shown inFIG. 3, the pillar3aalso has a bottom surface31a, an upper surface32aopposite to the bottom surface31a, and a lateral surface33aextending between the bottom surface31aand the upper surface32a. However, the pillar3ais substantially in a cylinder shape. That is, the lateral surface33ais substantially perpendicular to the bottom surface31aand the upper surface32a, and is substantially perpendicular to the bottom surface201of the cavity20of the substrate2. Besides, an area of the bottom surface31amay substantially be equal to the upper surface32a.

FIG. 4illustrates a cross-sectional view of a vertical capacitor structure1baccording to some embodiments of the present disclosure. The vertical capacitor structure1bis similar to the vertical capacitor structure1shown inFIGS. 1 and 2, except for the structure of the capacitor component4b, the dielectric structure5band the circuit layer6b.

As shown inFIG. 4, the capacitor component4balso includes the first conductive layer41, the first dielectric layer42and the second conductive layer43, but further includes a second dielectric layer44and a third conductive layer45. The first conductive layer41, the first dielectric layer42and the second conductive layer43of the capacitor component4bare similar to those of the capacitor component4shown inFIGS. 1 and 2.

The second dielectric layer44is similar to the first dielectric layer42. The second dielectric layer44covers and is conformal to the second conductive layer43. For example, the second dielectric layer44is disposed on and contacts the second conductive layer43. The second dielectric layer44may further be disposed on the upper surface21of the substrate2. The second dielectric layer44covers the second conductive layer43on the upper surface21of the substrate2, while the pad portion433of the second conductive layer43is exposed from the second dielectric layer44. Material, thickness and forming process of the second dielectric layer44may be the same as the first dielectric layer42.

The third conductive layer45is similar to the second conductive layer43and/or the first conductive layer41. The third conductive layer45covers and is conformal to the second dielectric layer44. For example, the third conductive layer45is disposed on and contacts the second dielectric layer44. The third conductive layer45may further be disposed on the upper surface21of the substrate2. The third conductive layer45has a pad portion453on the upper surface21of the substrate2. Material, thickness and forming process of the third conductive layer45may be the same as the second conductive layer43and/or the first conductive layer41.

Accordingly, the dielectric structure5further defines a third opening58to expose a portion of the third conductive layer45. The third opening58may be located on the upper surface21of the substrate2. For example, the third opening58exposes the pad portion453of the third conductive layer45.

In the vertical capacitor structure1b, since the capacitor component4bincludes two dielectric layers (e.g., the first dielectric layer42and the second dielectric layer44), a capacitance density thereof may be twice the capacitance density of the vertical capacitor structure1shown inFIGS. 1 and 2. For example, the capacitance density of the vertical capacitor structure1bmay be greater than about 140 NF/mm2.

FIG. 5throughFIG. 30illustrate a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a vertical capacitor structure such as the vertical capacitor structure1shown inFIGS. 1 and 2.

Referring toFIG. 5, a substrate2is provided, and a photoresist layer81is disposed thereon. The substrate2may be a substrate of any type. For example, the substrate2may be made of semiconducting material (e.g., silicon) or insulating material (e.g., glass). The substrate2has an upper surface21, and the photoresist layer81is disposed on the upper surface21.

Referring toFIG. 6, the photoresist layer81is patterned to define a through hole82. Processes for patterning the photoresist layer81may include exposure and development. For example, the photoresist layer81may be exposed to a patterned light, thus a portion of the photoresist layer is cured. Then, the photoresist layer81is developed. Another portion of the photoresist layer81which is not cured is removed during the development process.

Referring toFIG. 7, the substrate2is etched with the photoresist layer81serving as a mask, thus forming a cavity20in the substrate2corresponding to the through hole82of the photoresist layer81. The cavity20is recessed from the upper surface21of the substrate2. As shown inFIG. 7, the cavity20is defined by a bottom surface201and a lateral surface202. For example, the lateral surface202extends from an edge of the bottom surface201to the upper surface21. In some embodiments, the lateral surface202may be substantially perpendicular to the bottom surface201and the upper surface21. The bottom surface201and the upper surface21may be substantially parallel to each other.

Referring toFIG. 8, the photoresist layer81is removed, and the upper surface21of the substrate2is exposed.FIG. 9illustrates a perspective view of the substrate2. In some embodiments, an area of the bottom surface201of the cavity20may be about 800 nm×800 nm, and a depth thereof may be about 100 nm. Since the bottom surface201of the cavity20has a large area relative to the depth of the cavity20, the etching process for forming the cavity20may be easier and cheaper than the etching process for forming the deep holes in the exemplary vertical capacitor structure.

Referring toFIG. 10, an insulating layer26(e.g., a barrier layer) is formed to cover the cavity20of the substrate2such as covering the bottom surface201and the lateral surface202. The insulating layer26may further cover the upper surface21of the substrate2. Due to the arrangement of the insulating layer26, the substrate2is insulated from other components disposed thereon. For example, the insulating layer26may be formed by oxidizing surfaces of the substrate2(e.g., the upper surface21, and the bottom surface201and the lateral surface202of the cavity20). A material of the insulating layer26may be silicon oxide. However, the insulating layer26may be omitted if the substrate2is made of an insulating material (e.g., glass).

Referring toFIG. 11, a photoimageable dielectric material83is disposed in the cavity20and on the upper surface21of the substrate2. For example, the photoimageable dielectric material83is disposed on the insulating layer26. The photoimageable dielectric material83may be epoxy or polyimide (PI) including photoinitiators, and may not yet be cured. In some embodiments, the photoimageable dielectric material83may be applied in a dry film form, thus an upper surface84of the photoimageable dielectric material83may not be planar.

Referring toFIG. 12, a photomask85is disposed on the photoimageable dielectric material83. The photomask85defines at least one through hole86. Then, the photoimageable dielectric material83is exposed to a radiation source, and at least a portion of the photoimageable dielectric material83which is not covered by the photomask85is cured to form at least one pillar3in the cavity20of the substrate2. That is, the pillar3is the cured portion of the photoimageable dielectric material83. The pillar3is disposed in the cavity20of the substrate2. The pillar3has a bottom surface31, an upper surface32opposite to the bottom surface31, and a lateral surface33extending between the bottom surface31and the upper surface32. The upper surface32is a portion of the upper surface84of the photoimageable dielectric material83.

Referring toFIG. 13, the photoimageable dielectric material83is developed, and the lateral surface33of the pillar3is exposed. That is, a portion (e.g., uncured portion) of the photoimageable dielectric material83, excluding the pillar3, is removed. Thus, the pillar3stands on the insulating layer26. The bottom surface31is disposed on and contacts the insulating layer26. That is, the bottom surface31is a boundary between the pillar3and the insulating layer26. For example, the bottom surface31is adhered to the insulating layer26. In some embodiments, a height of the pillar3may be substantially equal to the depth of the cavity20of the substrate2.

As shown inFIG. 13, the pillar3tapers upward. In some embodiments, the pillar3is in a truncated cone-shape (as shown inFIG. 14). For example, the pillar3may be in a shape of a right circular cone, while a portion including an apex of the circular cone is omitted. Accordingly, an area of the bottom surface31may be greater than an area of the upper surface32. The lateral surface33is not perpendicular to the bottom surface201of the cavity20of the substrate2. For example, an angle θ between the lateral surface33of the pillar3and the bottom surface201of the cavity20of the substrate2is in a range of about 91 degrees to about 95 degrees. In some embodiments, the pillar3has a minimum diameter “D”. For example, the minimum diameter “D” may be located at or adjacent to the upper surface32of the pillar3. A pitch “P” is defined as a distance between the centers of adjacent two pillars3. For example, the minimum diameter “D” may be about μm and the pitch “P” may be equal to or greater than about 40 μm.

FIG. 14illustrates a perspective view of the structure shown inFIG. 13.FIG. 14shows 2×2 pillars3for illustration purpose. However, the amount and arrangement of the pillar3are not limited in the present disclosure. As shown inFIG. 13andFIG. 14, there is an empty space surrounding the pillars3. That is, the empty space is disposed between the lateral surfaces33of the pillars3, and between the lateral surface33of the pillar3and the lateral surface202of the cavity20of the substrate2.

Referring toFIG. 15, a first conductive layer41is formed to cover and conformal to the cavity20of the substrate2and the pillar3. For example, the first conductive layer41covers and is conformal to the upper surface32and the lateral surface33of the pillar3, portions of the bottom surface201of the cavity20which is not covered by the pillar3, and the lateral surface202of the cavity20of the substrate2. Since the angle θ between the lateral surface33of the pillar3and the bottom surface201of the cavity20of the substrate2is in a range of about 91 degrees to about 95 degrees, the first conductive layer41may be disposed on and extend smoothly along the lateral surface33of the pillar3.

The first conductive layer41is insulated from the substrate2. For example, the first conductive layer41covers the insulating layer26, such that the first conductive layer41is insulated from the substrate2. The first conductive layer41is further disposed on the upper surface21of the substrate2. The first conductive layer41may be made of a conductive material, and may be formed by physical or chemical vapor deposition.

Referring toFIG. 16, a first dielectric layer42is formed to cover and conformal to the first conductive layer41. For example, the first dielectric layer42is disposed on and contacts the first conductive layer41. The first dielectric layer42may further be disposed on the upper surface21of the substrate2. The first dielectric layer42covers the first conductive layer41on the upper surface21of the substrate2. The first dielectric layer42may be made of a dielectric material, such as Ta2O5; Al2O3, TiO2or HfO2. A relative permittivity of the first dielectric layer42may be about 8 to about 80. The first dielectric layer42may also be formed by physical or chemical vapor deposition, or by atomic layer deposition (ALD). A thickness of the first dielectric layer42may be about 10 nm to about 20 nm.

Referring toFIG. 17, a second conductive layer43is formed to cover and conformal to the first dielectric layer42. For example, the second conductive layer43is disposed on and contacts the first dielectric layer42. The second conductive layer43may further be disposed on the upper surface21of the substrate2. The second conductive layer43may be made of a conductive material, and may be formed by physical or chemical vapor deposition.

Referring toFIG. 18, a photoresist layer88is disposed on the second conductive layer43. The photoresist layer88may be applied in a dry film form, and may be laminated to the second conductive layer43. Thus, the photoresist layer88may not extend into the cavity20.

Referring toFIG. 19, the photoresist layer88is patterned to define a through hole89.

Referring toFIG. 20, the first dielectric layer42and the second conductive layer43is etched with the photoresist layer88serving as a mask to form a pad portion433of the second conductive layer43, and to expose a portion of the first conductive layer41. That is, portions of the first dielectric layer42and the second conductive layer43corresponding to the through hole89of the photoresist layer88are removed. Then, the photoresist layer88is removed.

Referring toFIG. 21, a photoresist layer90is disposed on the second conductive layer43and on the first conductive layer41. The photoresist layer90may be applied in a dry film form, and may be laminated to the second conductive layer43. Thus, the photoresist layer90may not extend into the cavity20.

Referring toFIG. 22, the photoresist layer90is patterned to define a through hole91.

Referring toFIG. 23, the first conductive layer41is etched with the photoresist layer90serving as a mask to form a pad portion413of the first conductive layer41. The pad portion413of the first conductive layer41is exposed from the first dielectric layer42and the first second conductive layer43. That is, portions of the first conductive layer41corresponding to the through hole91of the photoresist layer90are removed. Then, the photoresist layer90is removed. Accordingly, a capacitor component4is formed and includes the first conductive layer41, the first dielectric layer42, and the second conductive layer43. That is, the first conductive layer41, the first dielectric layer42and the second conductive layer43jointly form the capacitor component4. The capacitor component4is a vertical capacitor. A cross section of the capacitor component4, as shown inFIG. 23, is substantially in a serpentine shape or a rectangular wave shape.

The capacitor component4may have at least one first portion44, a second portion45, a third portion46and a fourth portion47. The first portion44is in a truncated hollow cone shape, and is disposed on and conformal to the pillar3. That is, the first portion44is disposed on the upper surface32and the lateral surface33of the pillar3. The first portion44may taper upward. The second portion45extends from a lower edge of the first portion44to the edge of the bottom surface201of the cavity20of the substrate2, and is disposed on a bottom surface201of the cavity20of the substrate2. The second portion45is substantially in a plane shape. The third portion46extends from an edge of the second portion45to the top edge of the cavity20of the substrate2, and is disposed on a lateral surface202of the cavity20of the substrate2. The third portion46is substantially perpendicular to the second portion45. An angle θ at an intersection of the first portion44and the second portion45is in a range between about 91 degrees to about 95 degrees. The fourth portion47extends from an upper edge of the third portion46, and is disposed on the upper surface21of the substrate2. The fourth portion47is substantially perpendicular to the third portion46.

Referring toFIG. 24, a dielectric structure5is formed to covers the capacitor component4. The dielectric structure5is disposed in the cavity20and on the upper surface21of the substrate2. For example, the dielectric structure5fills the cavity20of the substrate2, and has an upper surface51which may substantially be planar. A material of the dielectric structure5may include an insulating material, a passivation material, a dielectric material or a solder resist material, such as, for example, a benzocyclobutene (BCB) based polymer or a polyimide (PI). As shown inFIG. 24, the dielectric structure5covers the first portion44of the capacitor component4. That is, the peripheral outer surface of the first portion44of the capacitor component4is surrounded by the dielectric structure5.

Referring toFIG. 25, a first opening54and a second opening56are formed in and extend through the dielectric structure5. The first opening54and the second opening56may be located on the upper surface21of the substrate2. The first opening54exposes a portion of the first conductive layer41, such as the pad portion413of the first conductive layer41. The second opening56exposes a portion of the second conductive layer43, such as the pad portion433of the second conductive layer43.

Referring toFIG. 26, a seed layer61is formed in the first opening54and the second opening56, and on the upper surface51of the dielectric structure5. The seed layer61may be made of copper and/or titanium, and may be formed by sputtering.

Referring toFIG. 27, a photoresist layer92is disposed on the seed layer61. The photoresist layer92may be applied in a dry film form.

Referring toFIG. 28, the photoresist layer92is patterned to define a first through hole93on the seed layer61, a second through hole94corresponding to (or above) the first opening54of the dielectric structure5, and a third through hole95corresponding to (or above) the second opening56of the dielectric structure5.

Referring toFIG. 29, a conductive layer62is formed in the first through hole93, the second through hole94and the third through hole95of the photoresist layer92. The conductive layer62may be made of copper, and may be formed by plating. Accordingly, conductive layer62includes a trace63disposed in the first through hole93of the photoresist layer92, a first terminal64disposed in the second through hole94of the photoresist layer92and in the first opening54of the dielectric structure5, and a second terminal66disposed in the second through hole95of the photoresist layer92and in the second opening56of the dielectric structure5. That is, a metal material is disposed in the first opening54of the dielectric structure5to contact the first conductive layer41to form the first terminal64, and a metal material is disposed in the second opening56of the dielectric structure5to contact the second conductive layer43to form the second terminal66.

Referring toFIG. 30, the photoresist layer92is removed. Then, a portion of the seed layer61which is not covered by the conductive layer62is removed, thus forming the circuit layer6. The circuit layer6may be a redistribution layer (RDL) that includes the trace63, the first terminal64and the second terminal66. Then, a singulation process is conducted to form the vertical capacitor structure1as shown inFIGS. 1 and 2.