Systems and methods of RF power transmission, modulation, and amplification, including embodiments for amplifier class transitioning

Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to RF power transmission, modulation, and amplification. More particularly, the invention relates to methods and systems for vector combining power amplification.

2. Background Art

In power amplifiers, a complex tradeoff typically exists between linearity and power efficiency.

Linearity is determined by a power amplifier's operating range on a characteristic curve that relates its input to output variables—the more linear the operating range the more linear the power amplifier is said to be. Linearity is a desired characteristic of a power amplifier. In one aspect, for example, it is desired that a power amplifier uniformly amplifies signals of varying amplitude, and/or phase and/or frequency. Accordingly, linearity is an important determiner of the output signal quality of a power amplifier.

Power efficiency can be calculated using the relationship of the total power delivered to a load divided by the total power supplied to the amplifier. For an ideal amplifier, power efficiency is 100%. Typically, power amplifiers are divided into classes which determine the amplifier's maximum theoretical power efficiency. Power efficiency is clearly a desired characteristic of a power amplifier—particularly, in wireless communication systems where power consumption is significantly dominated by the power amplifier.

Unfortunately, the traditional tradeoff between linearity and efficiency in power amplifiers is such that the more linear a power amplifier is the less power efficient it is. For example, the most linear amplifier is biased for class A operation, which is the least efficient class of amplifiers. On the other hand, higher class amplifiers such as class B, C, D, E, etc, are more power efficient, but are considerably non-linear which can result in spectrally distorted output signals.

The tradeoff described above is further accentuated by typical wireless communication signals. Wireless communication signals, such as OFDM, CDMA, and W-CDMA for example, are generally characterized by their peak-to-average power ratios. The larger the signal's peak to average ratio the more non-linear distortion will be produced when non-linear amplifiers are employed.

Outphasing amplification techniques have been proposed for RF amplifier designs. In several aspects, however, existing outphasing techniques are deficient in satisfying complex signal amplification requirements, particularly as defined by wireless communication standards, for example.

In one aspect, existing outphasing techniques employ an isolating and/or a combining element when combining constant envelope constituents of a desired output signal. For example, it is commonly the case that a power combiner is used to combine the constituent signals. This combining approach, however, typically results in a degradation of output signal power due to insertion loss and limited bandwidth, and, correspondingly, a decrease in power efficiency.

In another aspect, the typically large size of combining elements precludes having them in monolithic amplifier designs.

What is needed therefore are power amplification methods and systems that solve the deficiencies of existing power amplifying techniques while maximizing power efficiency and minimizing non-linear distortion. Further, power amplification methods and systems that can be implemented without the limitations of traditional power combining circuitry and techniques are needed.

BRIEF SUMMARY OF THE INVENTION

Embodiments for vector combining power amplification are disclosed herein.

In one embodiment, a plurality of substantially constant envelope signals are individually amplified, then combined to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal.

In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of substantially constant envelope constituent signals. The constituent signals are amplified, and then re-combined to construct an amplified version of the original time-varying envelope signal.

Embodiments of the invention can be practiced with modulated carrier signals and with baseband information and clock signals. Embodiments of the invention also achieve frequency up-conversion. Accordingly, embodiments of the invention represent integrated solutions for frequency up-conversion, amplification, and modulation.

Embodiments of the invention can be implemented with analog and/or digital controls. The invention can be implemented with analog components or with a combination of analog components and digital components. In the latter embodiment, digital signal processing can be implemented in an existing baseband processor for added cost savings.

Additional features and advantages of the invention will be set forth in the description that follows. Yet further features and advantages will be apparent to a person skilled in the art based on the description set forth herein or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure and methods particularly pointed out in the written description and claims hereof as well as the appended drawings.

It is to be understood that both the foregoing summary and the following detailed description are exemplary and explanatory and are intended to provide further explanation of embodiments of the invention as claimed.

DETAILED DESCRIPTION OF THE INVENTION

Table of Contents

1. Introduction1.1. Example Generation of Time-Varying Complex Envelope Input Signals1.2. Example Generation of Time-Varying Complex Envelope Signals from Constant Envelope Signals1.3. Vector Power Amplification Overview

2. General Mathematical Overview2.1. Phasor Signal Representation2.2. Time-Varying Complex Envelope Signals2.3. Constant Envelope Decomposition of Time-Varying Envelope Signals

3. Vector Power Amplification (VPA) Methods and Systems3.1. Cartesian 4-Branch Vector Power Amplifier3.2. Cartesian-Polar-Cartesian-Polar (CPCP) 2-Branch Vector Power Amplifier3.3. Direct Cartesian 2-Branch Vector Power Amplifier3.4. I and Q Data to Vector Modulator Transfer Functions3.4.1. Cartesian 4-Branch VPA Transfer Function3.4.2. CPCP 2-Branch VPA Transfer Function3.4.3. Direct Cartesian 2-Branch VPA Transfer Function3.4.4. Magnitude to Phase Shift Transform3.4.4.1. Magnitude to Phase-Shift Transform for Sinusoidal Signals3.4.4.2. Magnitude to Phase Shift Transform for Square Wave Signals3.4.5. Waveform Distortion Compensation3.5. Output Stage3.5.1. Output Stage Embodiments3.5.2. Output Stage Current Shaping3.5.3. Output Stage Protection3.6. Harmonic Control3.7. Power Control3.8. Exemplary Vector Power Amplifier Embodiment

4. Additional Exemplary Embodiments and Implementations4.1. Overview4.1.1. Control of Output Power and Power Efficiency4.1.2. Error Compensation and/or Correction4.1.3. Multi-Band Multi-Mode Operation4.2. Digital Control Module4.3. VPA Analog Core4.3.1. VPA Analog Core Implementation A4.3.2. VPA Analog Core Implementation B4.3.3. VPA Analog Core Implementation C

5. Real-Time Amplifier Class Control of VPA Output Stage

Methods, apparatuses and systems for vector combining power amplification are disclosed herein.

Vector combining power amplification is an approach for optimizing linearity and power efficiency simultaneously. Generally speaking, and referring to flowchart502inFIG. 50, in step504a time-varying complex envelope input signal, with varying amplitude and phase, is decomposed into constant envelope constituent signals. In step506, the constant envelope constituent signals are amplified, and then in step508summed to generate an amplified version of the input complex envelope signal. Since substantially constant envelope signals may be amplified with minimal concern for non-linear distortion, the result of summing the constant envelope signals suffers minimal non-linear distortion while providing optimum efficiency.

Accordingly, vector combining power amplification allows for non-linear power amplifiers to be used to efficiently amplify complex signals whilst maintaining minimal non-linear distortion levels.

For purposes of convenience, and not limitation, methods and systems of the present invention are sometimes referred to herein as vector power amplification (VPA) methods and systems.

A high-level description of VPA methods and systems according to embodiments of the present invention is now provided. For the purpose of clarity, certain terms are first defined below. The definitions described in this section are provided for convenience purposes only, and are not limiting. The meaning of these terms will be apparent to persons skilled in the art(s) based on the entirety of the teachings provided herein. These terms may be discussed throughout the specification with additional detail.

The term signal envelope, when used herein, refers to an amplitude boundary within which a signal is contained as it fluctuates in the time domain. Quadrature-modulated signals can be described by r(t)=i(t)·cos(ωc·t)+q(t)·sin(ωc·t) where i(t) and q(t) represent in-phase and quadrature signals with the signal envelope e(t), being equal to e(t)=√{square root over (i(t)2+q(t)2)}{square root over (i(t)2+q(t)2)} and the phase angle associated with r(t) is related to arctan(q(t)/i(t).

The term constant envelope signal, when used herein, refers to in-phase and quadrature signals where e(t)=√{square root over (i(t)2+q(t)2)}{square root over (i(t)2+q(t)2)}, with e(t) having a relatively or substantially constant value.

The term time-varying envelope signal, when used herein, refers to a signal having a time-varying signal envelope. A time-varying envelope signal can be described in terms of in-phase and quadrature signals as e(t)=√{square root over (i(t)2+q(t)2)}{square root over (i(t)2+q(t)2)}, with e(t) having a time-varying value.

The term phase shifting, when used herein, refers to delaying or advancing the phase component of a time-varying or constant envelope signal relative to a reference phase.

1.1) Example Generation of Complex Envelope Time-Varying Input Signals

FIGS. 1A and 1Bare examples that illustrate the generation of time-varying envelope and phase complex input signals. InFIG. 1A, time-varying envelope carrier signals104and106are input into phase controller110. Phase controller110manipulates the phase components of signals104and106. In other words, phase controller110may phase shift signals104and106. Resulting signals108and112, accordingly, may be phased shifted relative to signals104and106. In the example ofFIG. 1A, phase controller110causes a phase reversal (180 degree phase shift)o in signals104and106at time instant to, as can be seen from signals108and112. Signals108and112represent time-varying complex carrier signals. Signals108and112have both time-varying envelopes and phase components. When summed, signals108and112result in signal114. Signal114also represents a time-varying complex signal. Signal114may be an example input signal into VPA embodiments of the present invention (for example, an example input into step504ofFIG. 50).

Time-varying complex signals may also be generated as illustrated inFIG. 1B. InFIG. 1B, signals116and118represent baseband signals. For example, signals116and118may be in-phase (I) and quadrature (Q) baseband components of a signal. In the example ofFIG. 1B, signals116and118undergo a zero crossing as they transition from +1 to −1. Signals116and118are multiplied by signal120or signal120phase shifted by 90 degrees. Signal116is multiplied by a 0 degree shifted version of signal120. Signal118is multiplied by a 90 degree shifted version of signal120. Resulting signals122and124represent time-varying complex carrier signals. Note that signals122and124have envelopes that vary according to the time-varying amplitudes of signals116and118. Further, signals122and124both undergo phase reversals at the zero crossings of signals116and118. Signals122and124are summed to result in signal126. Signal126represents a time-varying complex signal. Signal126may represent an example input signal into VPA embodiments of the present invention. Additionally, signals116and118may represent example input signals into VPA embodiments of the present invention.

1.2) Example Generation of Time-Varying Complex Envelope Signals from Constant Envelope Signals

The description in this section generally relates to the operation of step508inFIG. 50.FIG. 1Cillustrates three examples for the generation of time-varying complex signals from the sum of two or more substantially constant envelope signals. A person skilled in the art will appreciate, however, based on the teachings provided herein that the concepts illustrated in the examples ofFIG. 1Ccan be similarly extended to the case of more than two constant envelope signals.

In example 1 ofFIG. 1C, constant envelope signals132and134are input into phase controller130. Phase controller130manipulates phase components of signals132and134to generate signals136and138, respectively. Signals136and138represent substantially constant envelope signals, and are summed to generate signal140. The phasor representation inFIG. 1C, associated with example 1 illustrates signals136and138as phasors P136and P138, respectively. Signal140is illustrated as phasor P140. In example 1, P136and P138are symmetrically phase shifted by an angle φ1relative to a reference signal assumed to be aligned with the real axis of the phasor representation. Correspondingly, time domain signals136and138are phase shifted in equal amounts but opposite directions relative to the reference signal. Accordingly, P140, which is the sum of P136and P138, is in-phase with the reference signal.

In example 2 ofFIG. 1C, substantially constant envelope signals132and134are input into phase controller130. Phase controller130manipulates phase components of signals132and134to generate signals142and144, respectively. Signals142and144are substantially constant envelope signals, and are summed to generate signal150. The phasor representation associated with example 2 illustrates signals142and144as phasors P142and P144, respectively. Signal150is illustrated as phasor P150. In example 2, P142and P144are symmetrically phase shifted relative to a reference signal. Accordingly, similar to P140, P150is also in-phase with the reference signal. P142and P144, however, are phase shifted by an angle whereby φ2≠φ1relative to the reference signal. P150, as a result, has a different magnitude than P140of example 1. In the time domain representation, it is noted that signals140and150are in-phase but have different amplitudes relative to each other.

In example 3 ofFIG. 1C, substantially constant envelope signals132and134are input into phase controller130. Phase controller130manipulates phase components of signals132and134to generate signals146and148, respectively. Signals146and148are substantially constant envelope signals, and are summed to generate signal160. The phasor representation associated with example 3 illustrates signals146and148as phasors P146and P148, respectively. Signal160is illustrated as phasor P160. In example 3, P146is phased shifted by an angle φ3relative to the reference signal. P148is phase shifted by an angle φ4relative to the reference signal. φ3and φ4may or may not be equal. Accordingly, P160, which is the sum of P146and P148, is no longer in-phase with the reference signal. P160is phased shifted by an angle Θ relative to the reference signal. Similarly, P160is phase shifted by Θ relative to P140and P150of examples 1 and 2. P160may also vary in amplitude relative to P140as illustrated in example 3.

In summary, the examples ofFIG. 1Cdemonstrate that a time-varying amplitude signal can be obtained by the sum of two or more substantially constant envelope signals (Example 1). Further, the time-varying signal can have amplitude changes but no phase changes imparted thereon by equally shifting in opposite directions the two or more substantially constant envelope signals (Example 2). Equally shifting in the same direction the two or more constant envelope constituents of the signal, phase changes but no amplitude changes can be imparted on the time-varying signal. Any time-varying amplitude and phase signal can be generated using two or more substantially constant envelope signals (Example 3).

It is noted that signals in the examples ofFIG. 1Care shown as sinusoidal waveforms for purpose of illustration only. A person skilled in the art will appreciate based on the teachings herein that other types of waveforms may also have been used. It should also be noted that the examples ofFIG. 1Care provided herein for the purpose of illustration only, and may or may not correspond to a particular embodiment of the present invention.

1.3) Vector Power Amplification Overview

A high-level overview of vector power amplification is now provided.FIG. 1Dillustrates the power amplification of an exemplary time-varying complex input signal172. Signals114and126as illustrated inFIGS. 1A and 1Bmay be examples of signal172. Further, signal172may be generated by or comprised of two or more constituent signals such as104and106(FIG. 1A),108and112(FIG. 1A),116and118(FIG. 1B), and122and124(FIG. 1B).

In the example ofFIG. 1D, VPA170represents a VPA system embodiment according to the present invention. VPA170amplifies signal172to generate amplified output signal178. Output signal178is amplified efficiently with minimal distortion.

In the example ofFIG. 1D, signals172and178represent voltage signals Vin(t) and Volt(t), respectively. At any time instant, in the example ofFIG. 1D, Vin(t) and Volt(t) are related such that Volt(t)=Kevin(tat′), where K is a scale factor and t′ represents a time delay that may be present in the VPA system. For power implication,

Vout2⁡(t)Zout>Vin2⁡(t)Zin,
where output signal178is a power amplified version of input signal172.

Linear (or substantially linear) power amplification of time-varying complex signals, as illustrated inFIG. 1D, is achieved according to embodiments of the present as shown inFIG. 1E.

FIG. 1Eis an example block diagram that conceptually illustrates a vector power amplification embodiment according to embodiments of the present invention. InFIG. 1E, input signal172represents a time-varying complex signal. For example, input signal172may be generated as illustrated inFIGS. 1A and 1B. In embodiments, signal172may be a digital or an analog signal. Further, signal172may be a baseband or a carrier-based signal.

Referring toFIG. 1E, according to embodiments of the present invention, input signal172or equivalents thereof are input into VPA182. In the embodiment ofFIG. 1E, VPA182includes a state machine184and analog circuitry186. State machine184may include digital and/or analog components. Analog circuitry186includes analog components. VPA182processes input signal172to generate two or more signals188-{1, . . . ,n}, as illustrated inFIG. 1E. As described with respect to signals136,138,142,144, and146,148, inFIG. 1C, signals188-{1, . . . ,n} may or may not be phase shifted relative to each other over different periods of time. Further, VPA182generates signals188-{1, . . . ,n} such that a sum of signals188-{1, . . . ,n} results in signal194which, in certain embodiments, can be an amplified version of signal172.

Still referring toFIG. 1E, signals188-{1, . . . ,n} are substantially constant envelope signals. Accordingly, the description in the prior paragraph corresponds to step504inFIG. 50.

In the example ofFIG. 1E, generally corresponding to step506inFIG. 50, constant envelope signals188-{1, . . . ,n} are each independently amplified by a corresponding power amplifier (PA)190-{1, . . . ,n} to generate amplified signals192-{1, . . . ,n}. In embodiments, PAs190-{1, . . . ,n} amplify substantially equally respective constant envelope signals188-{1, . . . ,n}. Amplified signals192-{1, . . . ,n} are substantially constant envelope signals, and in step508are summed to generate output signal194. Note that output signal194can be a linearly (or substantially linearly) amplified version of input signal172. Output signal194may also be a frequency-upconverted version of input signal172, as described herein.

2. GENERAL MATHEMATICAL OVERVIEW

FIG. 1illustrates a phasor representation {right arrow over (R)}102of a signal r(t). A phasor representation of a signal is explicitly representative of the magnitude of the signal's envelope and of the signal's phase shift relative to a reference signal. In this document, for purposes of convenience, and not limitation, the reference signal is defined as being aligned with the real (Re) axis of the orthogonal space of the phasor representation. The invention is not, however, limited to this embodiment. The frequency information of the signal is implicit in the representation, and is given by the frequency of the reference signal. For example, referring toFIG. 1, and assuming that the real axis corresponds to a cos(ωt) reference signal, phasor {right arrow over (R)} would translate to the function r(t)=R(t)cos(ωt+φ(t)), where R is the magnitude of {right arrow over (R)}

Still referring toFIG. 1, it is noted that phasor {right arrow over (R)} can be decomposed into a real part phasor {right arrow over (I)} and an imaginary part phasor {right arrow over (I)} and {right arrow over (Q)} are said to be the in-phase and quadrature phasor components of {right arrow over (R)} with respect to the reference signal. It is further noted that the signals that correspond to {right arrow over (I)} and {right arrow over (Q)} are related to r(t) as I(t)=R(t)·cos(φ(t)) and Q(t)=R(t)·sin(φ(t)), respectively. In the time domain, signal r(t) can also be written in terms of its in-phase and quadrature components as follows:
r(t)=I(t)·cos(ωt)+Q(t)·sin(ωt)=R(t)·cos(φ(t))·cos(ωt)+R(t)·sin(φ(t))·sin(ωt)  (1)

Note that, in the example ofFIG. 1, R(t) is illustrated at a particular instant of time.

FIG. 2illustrates a phasor representation of a signal r(t) at two different instants of time t1and t2. It is noted that the magnitude of the phasor, which represents the magnitude of the signal's envelope, as well as its relative phase shift both vary from time t1to time t2. InFIG. 2, this is illustrated by the varying magnitude of phasors {right arrow over (R1)} and {right arrow over (R2)} and their corresponding phase shift angles φ1and φ2. Signal r(t), accordingly, is a time-varying complex envelope signal.

It is further noted, fromFIG. 2, that the real and imaginary phasor components of signal r(t) are also time-varying in amplitude. Accordingly, their corresponding time domain signals also have time-varying envelopes.

FIGS. 3A-3Cillustrate an example modulation to generate a time-varying complex envelope signal.FIG. 3Aillustrates a view of a signal m(t).FIG. 3Billustrates a view of a portion of a carrier signal c(t).FIG. 3Cillustrates a signal r(t) that results from the multiplication of signals m(t) and c(t).

In the example ofFIG. 3A, signal m(t) is a time-varying magnitude signal. m(t) further undergoes a zero crossing. Carrier signal c(t), in the example ofFIG. 3B, oscillates at some carrier frequency, typically higher than that of signal m(t).

FromFIG. 3C, it can be noted that the resulting signal r(t) has a time-varying envelope. Further, it is noted, fromFIG. 3C, that r(t) undergoes a reversal in phase at the moment when the modulating signal m(t) crosses zero. Having both non-constant envelope and phase, r(t) is said to be a time-varying complex envelope signal.

2.3) Constant Envelope Decomposition of Time-Varying Envelope Signals

Any phasor of time-varying magnitude and phase can be obtained by the sum of two or more constant magnitude phasors having appropriately specified phase shifts relative to a reference phasor.

FIG. 3Dillustrates a view of an example time-varying envelope and phase signal S(t). For ease of illustration, signal S(t) is assumed to be a sinusoidal signal having a maximum envelope magnitude A.FIG. 3Dfurther shows an example of how signal S(t) can be obtained, at any instant of time, by the sum of two constant envelope signals S1(t) and S2(t). Generally, S1(t)=A1sin(ωt+φ1(t)) and S1(t)=A2sin(ωt+φ2(t)).

For the purpose of illustration, three views are provided inFIG. 3Dthat illustrate how by appropriately phasing signals S1(t) and S2(t) relative to S(t), signals S1(t) and S2(t) can be summed so that S(t)=K(S1(t)+S2(t)) where K is a constant. In other words, signal S(t) can be decomposed, at any time instant, into two or more signals. FromFIG. 3D, over period T1, S1(t) and S2(t) are both in-phase relative to signal S(t), and thus sum to the maximum envelope magnitude A of signal S(t). Over period T3, however, signals S1(t) and S2(t) are 180 degree out-of-phase relative to each other, and thus sum to a minimum envelope magnitude of signal S(t).

The example ofFIG. 3Dillustrates the case of sinusoidal signals. A person skilled in the art, however, will understand that any time-varying envelope, which modulates a carrier signal that can be represented by a Fourier series or Fourier transform, can be similarly decomposed into two or more substantially constant envelope signals. Thus, by controlling the phase of a plurality of substantially constant envelope signals, any time-varying complex envelope signal can be generated.

3. VECTOR POWER AMPLIFICATION METHODS AND SYSTEMS

Vector power amplification methods and systems according to embodiments of the present invention rely on the ability to decompose any time-varying envelope signal into two or more substantially constant envelope constituent signals or to receive or generate such constituent signals, amplify the constituent signals, and then sum the amplified signals to generate an amplified version of the time-varying complex envelope signal.

In sections 3.1-3.3, vector power amplification (VPA) embodiments of the present invention are provided, including 4-branch and 2-branch embodiments. In the description, each VPA embodiment is first presented conceptually using a mathematical derivation of underlying concepts of the embodiment. An embodiment of a method of operation of the VPA embodiment is then presented, followed by various system level embodiments of the VPA embodiment.

Section 3.4 presents various embodiments of control modules according to embodiments of the present invention. Control modules according to embodiments of the present invention may be used to enable certain VPA embodiments of the present invention. In some embodiments, the control modules are intermediary between an input stage of the VPA embodiment and a subsequent vector modulation stage of the VPA embodiment.

Section 3.5 describes VPA output stage embodiments according to embodiments of the present invention. Output stage embodiments are directed to generating the output signal of a VPA embodiment.

Section 3.6 is directed to harmonic control according to embodiments of the present invention. Harmonic control may be implemented in certain embodiments of the present invention to manipulate the real and imaginary power in the harmonics of the VPA embodiment, thus increasing the power present in the fundamental frequency at the output.

Section 3.7 is directed to power control according to embodiments of the present invention. Power control may be implemented in certain embodiments of the present invention in order to satisfy power level requirements of applications where VPA embodiments of the present invention may be employed.

According to one embodiment of the invention, herein called the Cartesian 4-Branch VPA embodiment for ease of illustration and not limitation, a time-varying complex envelope signal is decomposed into 4 substantially constant envelope constituent signals. The constituent signals are equally or substantially equally amplified individually, and then summed to construct an amplified version of the original time-varying complex envelope signal.

It is noted that 4 branches are employed in this embodiment for purposes of illustration, and not limitation. The scope of the invention covers use of other numbers of branches, and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

In one embodiment, a time-varying complex envelope signal is first decomposed into its in-phase and quadrature vector components. In phasor representation, the in-phase and quadrature vector components correspond to the signal's real part and imaginary part phasors, respectively.

As described above, magnitudes of the in-phase and quadrature vector components of a signal vary proportionally to the signal's magnitude, and are thus not constant envelope when the signal is a time-varying envelope signal. Accordingly, the 4-Branch VPA embodiment further decomposes each of the in-phase and quadrature vector components of the signal into four substantially constant envelope components, two for the in-phase and two for the quadrature signal components. This concept is illustrated inFIG. 4using a phasor signal representation.

In the example ofFIG. 4, phasors {right arrow over (I1)} and {right arrow over (I2)} correspond to the real part phasors of an exemplary time-varying complex envelope signal at two instants of time t1and t2, respectively. It is noted that phasors {right arrow over (I1)} and {right arrow over (I2)} have different magnitudes.

Still referring toFIG. 4, at instant t1, phasor {right arrow over (I1)} can be obtained by the sum of upper and lower phasors {right arrow over (IU1)} and {right arrow over (IL1)}. Similarly, at instant t2, phasor {right arrow over (I2)} can be obtained by the sum of upper and lower phasors {right arrow over (IU2)} and {right arrow over (IL2)}. Note that phasors {right arrow over (IU1)} and {right arrow over (IU2)} have equal or substantially equal magnitude. Similarly, phasors {right arrow over (IL1)} and {right arrow over (IL2)} have substantially equal magnitude. Accordingly, the real part phasor of the time-varying envelope signal can be obtained at any time instant by the sum of at least two substantially constant envelope components.

The phase shifts of phasors {right arrow over (IU1)}, and {right arrow over (IL1)} relative to {right arrow over (I1)}, as well as the phase shifts of phasors {right arrow over (IU2)} and {right arrow over (IL2)} relative to {right arrow over (I2)} are set according to the desired magnitude of phasors {right arrow over (I1)} and {right arrow over (I2)} respectively. In one case, when the upper and lower phasors are selected to have equal magnitude, the upper and lower phasors are symmetrically shifted in phase relative to the phasor. This is illustrated in the example ofFIG. 4, and corresponds to {right arrow over (IU1)}, {right arrow over (IL1)}, {right arrow over (IU2)}, and {right arrow over (IL2)} all having equal magnitude. In a second case, the phase shift of the upper and lower phasors are substantially symmetrically shifted in phase relative to the phasor. Based on the description herein, anyone skilled in the art will understand that the magnitude and phase shift of the upper and lower phasors do not have to be exactly equal in value

As an example, it can be further verified that, for the case illustrated inFIG. 4, the relative phase shifts, illustrated as

ϕ12
and

ϕ22
inFIG. 4, are related to the magnitudes of normalized phasors {right arrow over (I1)} and {right arrow over (I2)} as follows:

wherein I1and I2represent the normalized magnitudes of phasors {right arrow over (I1)} and {right arrow over (I2)}, respectively, and wherein the domains of {right arrow over (I1)} and {right arrow over (I2)} are restricted appropriately according to the domain over which equation (2) and (3) are valid. It is noted that equations (2) and (3) are one representation for relating the relative phase shifts to the normalized magnitudes. Other, solutions, equivalent representations, and/or simplified representations of equations (2) and (3) may also be employed. Look up tables relating relative phase shifts to normalized magnitudes may also be used.

The concept describe above can be similarly applied to the imaginary phasor or the quadrature component part of a signal r(t) as illustrated inFIG. 4. Accordingly, at any time instant t, imaginary phasor part {right arrow over (Q)} of signal r(t) can be obtained by summing upper and lower phasor components {right arrow over (QU)} and {right arrow over (QL)} of substantially equal and constant magnitude. In this example, {right arrow over (QU)} and {right arrow over (QL)} are symmetrically shifted in phase relative to {right arrow over (Q)} by an angle set according to the magnitude of {right arrow over (Q)} at time t. The relationship of {right arrow over (QU)} and {right arrow over (QL)} to the desired phasor {right arrow over (Q)} are related as defined in equations 2 and 3 by substituting Q1and Q2for {right arrow over (I1)} and {right arrow over (I2)} respectively.

It follows from the above discussion that, in phasor representation, any phasor {right arrow over (R)} of variable magnitude and phase can be constructed by the sum of four substantially constant magnitude phasor components:
{right arrow over (R)}={right arrow over (IU)}+{right arrow over (IL)}+{right arrow over (QU)}+{right arrow over (QL)};
{right arrow over (IU)}+{right arrow over (IL)}={right arrow over (I)};
{right arrow over (QU)}+{right arrow over (QL)}={right arrow over (Q)};
IU=IL=constant;
QU=QL=constant;  (4)

Correspondingly, in the time domain, a time-varying complex envelope sinusoidal signal r(t)=R(t)cos(ωt+φ) is constructed by the sum of four constant envelope signals as follows:

r⁡(t)=⁢IU⁡(t)+IL⁡(t)+QU⁡(t)+QL⁡(t);IU⁡(t)⁢=sgn⁢(I)→×IU×cos⁡(ϕI2)×cos⁡(ω⁢⁢t)+IU×sin⁡(ϕI2)×sin⁡(ω⁢⁢t);IL⁡(t)⁢=sgn⁢(I)→×IL×cos⁡(ϕI2)×cos⁡(ω⁢⁢t)-IL×sin⁡(ϕI2)×sin⁡(ω⁢⁢t);QU⁡(t)⁢=-sgn⁢(Q)→×QU×cos⁡(ϕQ2)×sin⁡(ω⁢⁢t)+QU×sin⁡(ϕQ2)×cos⁡(ω⁢⁢t);⁢QL⁡(t)=-sgn⁢(Q)→×QL×cos⁡(ϕQ2)×sin⁡(ω⁢⁢t)-QL×sin⁡(ϕQ2)×cos⁡(ω⁢⁢t).(5)
where sgn({right arrow over (I)})=±1 depending on whether {right arrow over (I)} is in-phase or 180° degrees out-of-phase with the positive real axis. Similarly, sgn({right arrow over (Q)})=±1 depending on whether {right arrow over (Q)} is in-phase or 180° degrees out-of-phase with the imaginary axis.

ϕI2
corresponds to the phase shift of {right arrow over (IU)} and {right arrow over (IL)} relative to the real axis. Similarly,

ϕQ2
corresponds to the phase shift of {right arrow over (Q)}Uand {right arrow over (QL)} relative to the imaginary axis

ϕI2
and

ϕQ2
can be calculated using the equations given in (2) and (3).

It can be understood by a person skilled in the art that, whereas the time domain representations in equations (5) and (6) have been provided for the case of a sinusoidal waveform, equivalent representations can be developed for non-sinusoidal waveforms using appropriate basis functions. Further, as understood by a person skilled in the art based on the teachings herein, the above-describe two-dimensional decomposition into substantially constant envelope signals can be extended appropriately into a multi-dimensional decomposition.

FIG. 5is an example block diagram of the Cartesian 4-Branch VPA embodiment. An output signal r(t)578of desired power level and frequency characteristics is generated from baseband in-phase and quadrature components according to the Cartesian 4-Branch VPA embodiment.

In the example ofFIG. 5, a frequency generator such as a synthesizer510generates a reference signal A*cos(ωt)511having the same frequency as that of output signal r(t)578. It can be understood by a person skilled in the art that the choice of the reference signal is made according to the desired output signal. For example, if the desired frequency of the desired output signal is 2.4 GHz, then the frequency of the reference signal is set to be 2.4 GHz. In this manner, embodiments of the invention achieve frequency up-conversion.

Referring toFIG. 5, one or more phase splitters are used to generate signals521,531,541, and551based on the reference signal511. In the example ofFIG. 5, this is done using phase splitters512,514, and516and by applying 0° phase shifts at each of the phase splitters. A person skilled in the art will appreciate, however, that various techniques may be used for generating signals521,531,541, and551of the reference signal511. For example, a 1:4 phase splitter may be used to generate the four replicas521,531,541, and551in a single step or in the example embodiment ofFIG. 5, signal511can be directly coupled to signals521,531,541,551Depending on the embodiment, a variety of phase shifts may also be applied to result in the desired signals521,531,541, and551.

Still referring toFIG. 5, the signals521,531,541, and551are each provided to a corresponding vector modulator520,530,540, and550, respectively. Vector modulators520,530,540, and550, in conjunction with their appropriate input signals, generate four constant envelope constituents of signal r(t) according to the equations provided in (6). In the example embodiment ofFIG. 5, vector modulators520and530generate the IU(t) and IL(t) components, respectively, of signal r(t). Similarly, vector modulators540and550generate the QU(t) and QL(t) components, respectively, of signal r(t).

The actual implementation of each of vector modulators520,530,540, and550may vary. It will be understood by a person skilled in the art, for example, that various techniques exist for generating the constant envelope constituents according to the equations in (6).

In the example embodiment ofFIG. 5, each of vector modulators520,530,540,550includes an input phase splitter522,532,542,552for phasing the signals522,531,541,551. Accordingly, input phase splitters522,532,542,552are used to generate an in-phase and a quadrature components or their respective input signals.

In each vector modulator520,530,540,550, the in-phase and quadrature components are multiplied with amplitude information. InFIG. 5, for example, multiplier524multiplies the quadrature component of signal521with the quadrature amplitude information IUYof IU(t). In parallel, multiplier526multiplies the in-phase replica signal with the in-phase amplitude information sgn(I)×IUXof IU(t).

To generate the IU(t) constant envelope constituent signals525and527are summed using phase splitter528or alternate summing techniques. The resulting signal529corresponds to the IU(t) component of signal r(t).

Further, as described above, signals529,539,549, and559are characterized by having substantially equal and constant magnitude envelopes. Accordingly, when signals529,539,549, and559are input into corresponding power amplifiers (PA)562,564,566, and568, corresponding amplified signals563,565,567, and569are substantially constant envelope signals.

Power amplifiers562,564,566, and568amplify each of the signals529,539,549,559, respectively. In an embodiment, substantially equal power amplification is applied to each of the signals529,539,549, and559. In an embodiment, the power amplification level of PAs562,564,566, and568is set according to the desired power level of output signal r(t).

Still referring toFIG. 5, amplified signals563and565are summed using summer572to generate an amplified version573of the in-phase component {right arrow over (I)}(t) of signal r(t). Similarly, amplified signals567and569are summed using summer574to generate an amplified version575of the quadrature component {right arrow over (Q)}(t) of signal r(t).

Signals573and575are summed using summer576, as shown inFIG. 5, with the resulting signal corresponding to desired output signal r(t).

It must be noted that, in the example ofFIG. 5, summers572,574, and576are being used for the purpose of illustration only. Various techniques may be used to sum amplified signals563,565,567, and569. For example, amplified signals563,565,567, and569may be summed all in one step to result in signal578. In fact, according to various VPA embodiments of the present invention, it suffices that the summing is done after amplification. Certain VPA embodiments of the present invention, as will be further described below, use minimally lossy summing techniques such as direct coupling via wire. Alternatively, certain VPA embodiments use conventional power combining techniques. In other embodiments, as will be further described below, power amplifiers562,564,566, and568can be implemented as a multiple-input single-output power amplifier.

Operation of the Cartesian 4-Branch VPA embodiment shall now be further described with reference to the process flowchart ofFIG. 6. The process begins at step610, which includes receiving the baseband representation of the desired output signal. In an embodiment, this involves receiving in-phase (I) and quadrature (Q) components of the desired output signal. In another embodiment, this involves receiving magnitude and phase of the desired output signal. In an embodiment of the Cartesian 4-Branch VPA embodiment, the I and Q are baseband components. In another embodiment, the I and Q are RF components and are down-converted to baseband.

Step620includes receiving a clock signal set according to a desired output signal frequency of the desired output signal. In the example ofFIG. 5, step620is achieved by receiving reference signal511.

Step630includes processing the I component to generate first and second signals having the output signal frequency. The first and second signals have substantially constant and equal magnitude envelopes and a sum equal to the I component. The first and second signals correspond to the IU(t) and IL(t) constant envelope constituents described above. In the example ofFIG. 5, step630is achieved by vector modulators520and530, in conjunction with their appropriate input signals.

Step640includes processing the Q component to generate third and fourth signals having the output signal frequency. The third and fourth signals have substantially constant and equal magnitude envelopes and a sum equal to the Q component. The third and fourth signals correspond to the QU(t) and QL(t) constant envelope constituents described above. In the example ofFIG. 5, step630is achieved by vector modulators540and550, in conjunction with their appropriate input signals.

Step650includes individually amplifying each of the first, second, third, and fourth signals, and summing the amplified signals to generate the desired output signal. In an embodiment, the amplification of the first, second, third, and fourth signals is substantially equal and according to a desired power level of the desired output signal. In the example ofFIG. 5, step650is achieved by power amplifiers562,564,566, and568amplifying respective signals529,539,549, and559, and by summers572,574, and576summing amplified signals563,565,567, and569to generate output signal578.

FIG. 7Ais a block diagram that illustrates an exemplary embodiment of a vector power amplifier700implementing the process flowchart600ofFIG. 6. In the example ofFIG. 7A, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional.

Vector power amplifier700includes an in-phase (I) branch703and a quadrature (Q) branch705. Each of the I and Q branches further comprises a first branch and a second branch.

In-phase (I) information signal702is received by an I Data Transfer Function module710. In an embodiment, I information signal702includes a digital baseband signal. In an embodiment, I Data Transfer Function module710samples I information signal702according to a sample clock706. In another embodiment, I information signal702includes an analog baseband signal, which is converted to digital using an analog-to-digital converter (ADC) (not shown inFIG. 7A) before being input into I Data Transfer Function module710. In another embodiment, I information signal702includes an analog baseband signal which input in analog form into I Data Transfer Function module710, which also includes analog circuitry. In another embodiment, I information signal702includes a RF signal which is down-converted to baseband before being input into I Data Transfer Function module710using any of the above described embodiments.

I Data Transfer Function module710processes I information signal702, and determines in-phase and quadrature amplitude information of at least two constant envelope constituent signals of I information signal702. As described above with reference toFIG. 5, the in-phase and quadrature vector modulator input amplitude information corresponds to sgn(I)×IUXand IUY, respectively. The operation of I Data Transfer Function module710is further described below in section 3.4.

I Data Transfer Function module710outputs information signals722and724used to control the in-phase and quadrature amplitude components of vector modulators760and762. In an embodiment, signals722and724are digital signals. Accordingly, each of signals722and724is fed into a corresponding digital-to-analog converter (DAC)730and732, respectively. The resolution and sample rate of DACs730and732is selected to achieve the desired I component of the output signal782. DACs730and732are controlled by DAC clock signals723and725, respectively. DAC clock signals723and725may be derived from a same clock signal or may be independent.

In another embodiment, signals722and724are analog signals, and DACs730and732are not required.

In the exemplary embodiment ofFIG. 7A, DACs730and732convert digital information signals722and724into corresponding analog signals, and input these analog signals into optional interpolation filters731and733, respectively. Interpolation filters731and733, which also serve as anti-aliasing filters, shape the DACs outputs to produce the desired output waveform. Interpolation filters731and733generate signals740and742, respectively. Signal741represents the inverse of signal740. Signals740-742are input into vector modulators760and762.

Vector modulators760and762multiply signals740-742with appropriately phased clock signals to generate constant envelope constituents of I information signal702. The clock signals are derived from a channel clock signal708having a rate according to a desired output signal frequency. A plurality of phase splitters, such as750and752, for example, and phasors associated with the vector modulator multipliers may be used to generate the appropriately phased clock signals.

In the embodiment ofFIG. 7A, for example, vector modulator760modulates a 90° shifted channel clock signal with quadrature amplitude information signal740. In parallel, vector modulator760modulates an in-phase channel clock signal with in-phase amplitude information signal742. Vector modulator760combines the two modulated signals to generate a first modulated constant envelope constituent761of I information signal702. Similarly, vector modulator762generates a second modulated constant envelope constituent763of I information signal702, using signals741and742. Signals761and763correspond, respectively, to the IU(t) and IL(t) constant envelope components described with reference toFIG. 5.

In parallel and in similar fashion, the Q branch of vector power amplifier700generates at least two constant envelope constituent signals of quadrature (Q) information signal704.

In the embodiment ofFIG. 7A, for example, vector modulator764generates a first constant envelope constituent765of Q information signal704, using signals744and746. Similarly, vector modulator766generates a second constant envelope constituent767of Q information signal704, using signals745and746.

As described above with respect toFIG. 5, constituent signals761,763,765, and767have substantially equal and constant magnitude envelopes. In the exemplary embodiment ofFIG. 7A, signals761,763,765, and767are, respectively, input into corresponding power amplifiers (PAs)770,772,774, and776. PAs770,772,774, and776can be linear or non-linear power amplifiers. In an embodiment, PAs770,772,774, and776include switching power amplifiers.

Circuitry714and716(herein referred to as “autobias circuitry” for ease of reference, and not limitation) and in this embodiment, control the bias of PAs770,772,774, and776according to I and Q information signals702and704. In the embodiment ofFIG. 7A, autobias circuitry714and716provide, respectively, bias signals715and717to PAs770,772and PAs774,776. Autobias circuitry714and716are further described below in section 3.5. Embodiments of PAs770,772,774, and776are also discussed below in section 3.5.

In an embodiment, PAs770,772,774, and776apply substantially equal power amplification to respective substantially constant envelope signals761,763,765, and767. In other embodiments, PA drivers are additionally employed to provide additional power amplification. In the embodiment ofFIG. 7A, PA drivers794,795,796, and797are optionally added between respective vector modulators760,762,764766and respective PAs770,772,774, and776, in each branch of vector power amplifier700.

The outputs of PAs770,772,774, and776are coupled together to generate output signal782of vector power amplifier700. In an embodiment, the outputs of PAs770,772,774, and776are directly coupled together using a wire. Direct coupling in this manner means that there is minimal or no resistive, inductive, or capacitive isolation between the outputs of PAs770,772,774, and776. In other words, outputs of PAs770,772,774, and776, are coupled together without intervening components. Alternatively, in an embodiment, the outputs of PAs770,772,774, and776are coupled together indirectly through inductances and/or capacitances that result in low or minimal impedance connections, and/or connections that result in minimal isolation and minimal power loss. Alternatively, outputs of PAs770,772,774, and776are coupled using well known combining techniques, such as Wilkinson, hybrid, transformers, or known active combiners. In an embodiment, the PAs770,772,774, and776provide integrated amplification and power combining in a single operation. In an embodiment, one or more of the power amplifiers and/or drivers described herein are implemented using multiple input, single output power amplification techniques, examples of which are shown inFIGS. 7B, and51A-H.

Output signal782includes the I and Q characteristics of I and Q information signals702and704. Further, output signal782is of the same frequency as that of its constituents, and thus is of the desired up-converted output frequency. In embodiments of vector power amplifier700, a pull-up impedance780is coupled between the output of vector amplifier700and a power supply. Output stage embodiments according to power amplification methods and systems of the present invention will be further described below in section 3.5.

In other embodiments of vector power amplifier700, process detectors are employed to compensate for any process variations in circuitry of the amplifier. In the embodiment ofFIG. 7Afor example, process detectors791-793are optionally added to monitor variations in PA drivers794-797and phase splitter750. In further embodiments, frequency compensation circuitry799may be employed to compensate for frequency variations.

FIG. 7Bis a block diagram that illustrates another exemplary embodiment of vector power amplifier700. Optional components are illustrated with dashed lines, although other embodiments may have more or less optional components.

The embodiment illustrates a multiple-input single-output (MISO) implementation of the amplifier ofFIG. 7A. In the embodiment ofFIG. 7B, constant envelope signals761,763,765and767, output from vector modulators760,762,764, and766, are input into MISO PAs784and786. MISO PAs784and786are two-input single-output power amplifiers. In an embodiment, MISO PAs784and786include elements770,772,774,776,794-797as shown in the embodiment ofFIG. 7Aor functional equivalence thereof. In another embodiment, MISO PAs784and786may include other elements, such as optional pre-drivers and optional process detection circuitry. Further, MISO PAs784and786are not limited to being two-input PAs as shown inFIG. 7B. In other embodiments as will be described further below with reference toFIGS. 51A-H, PAs784and786can have any number of inputs and outputs.

FIG. 8Ais a block diagram that illustrates another exemplary embodiment800A of a vector power amplifier according to the Cartesian 4-Branch VPA method shown inFIG. 6. Optional components are illustrated with dashed lines, although other embodiments may have more or less optional components.

In the embodiment ofFIG. 8A, a DAC830of sufficient resolution and sample rate replaces DACs730,732,734, and736of the embodiment ofFIG. 7A. DAC830's sample rate is controlled by a DAC clock signal826.

DAC830receives in-phase and quadrature information signals810and820from I Data Transfer Function module710and Q Data Transfer Function module712, respectively, as described above. In an embodiment, a input selector822selects the order of signals810and820being input into DAC830.

DAC830may output a single analog signal at a time. In an embodiment, a sample and hold architecture may be used to ensure proper signal timing to the four branches of the amplifier, as shown inFIG. 8A.

DAC830sequentially outputs analog signals832,834,836,838to a first set of sample-and-hold circuits842,844,846, and848. In an embodiment, DAC830is clocked at a sufficient rate to emulate the operation of DACs730,732,734, and736of the embodiment ofFIG. 7A. An output selector824determines which of output signals832,834,836, and838should be selected for output.

DAC830's DAC clock signal826, output selector signal824, input selector822, and sample-and-hold clocks840A-D, and850are controlled by a control module that can be independent or integrated into transfer function modules710and/or712.

In an embodiment, sample-and-hold circuits (S/H)842,844,846, and848sample and hold the received analog values from DAC830according to a clock signals840A-D. Sample-and-hold circuits852,854,856, and858sample and hold the analog values from sample and hold circuits842,844,846, and848respectively. In turn, sample-and-hold circuits852,854,856, and858hold the received analog values, and simultaneously release the values to vector modulators760,762,764, and766according to a common clock signal850. In another embodiment, sample-and-hold circuits852,854,856, and858release the values to optional interpolation filters731,733,735, and737which are also anti-aliasing filters. In an embodiment, a common clock signal850is used in order to ensure that the outputs of S/H852,854,856, and858are time-aligned.

Other aspects of vector power amplifier800A substantially correspond to those described above with respect to vector power amplifier700.

FIG. 8Bis a block diagram that illustrates another exemplary embodiment800B of a vector power amplifier according to the Cartesian 4-Branch VPA method shown inFIG. 6. Optional components are illustrated with dashed lines, although other embodiments may have more or less optional components.

Embodiment800B illustrates another single DAC implementation of the vector power amplifier. However, in contrast to the embodiment ofFIG. 8A, the sample and hold architecture includes a single set of sample-and-hold (S/H) circuits. As shown inFIG. 8B, S/H842,844,846, and848receive analog values from DAC830, illustrated as signals832,834,836, and838. Each of S/H circuits842,844,846and848release its received value according to a different clock840A-D as shown. The time difference between analog samples used for to generate signals740,741,742,744,745, and746can be compensated for in transfer functions710and712. According to the embodiment ofFIG. 8B, one level of S/H circuitry can be eliminated relative to the embodiment ofFIG. 8A, thereby reducing the size and the complexity of the amplifier.

Other aspects of vector power amplifier800B substantially correspond to those described above with respect to vector power amplifiers700and800A.

FIG. 8Cis a block diagram that illustrates another exemplary embodiment800C of vector power amplifier700. Optional components are illustrated with dashed lines, although other embodiments may have more or less optional components. The embodiment ofFIG. 8Cillustrates a multiple-input single-output (MISO) implementation of the amplifier ofFIG. 8A. In the embodiment ofFIG. 8C, constant envelope signals761,763,765and767, output from vector modulators760,762,764, and766, are input into MISO PAs860and862. MISO PAs860and862are two-input single-output power amplifiers. In an embodiment, MISO PAs860and862include elements770,772,774,776,794-797as shown in the embodiment ofFIG. 7Aor functional equivalence thereof. In another embodiment, MISO PAs860and862may include other elements, such as optional pre-drivers and optional process detection circuitry. In another embodiment, MISO PAs860and862may include other elements, such as pre-drivers, not shown in the embodiment ofFIG. 7A. Further, MISO PAs860and862are not limited to being two-input PAs as shown inFIG. 8C. In other embodiments as will be described further below with reference toFIGS. 51A-H, PAs860and862can have any number of inputs and outputs.

Other aspects of vector power amplifier800C substantially correspond to those described above with respect to vector power amplifiers700and800A.

FIG. 8Dis a block diagram that illustrates another exemplary embodiment800D of vector power amplifier700. Optional components are illustrated with dashed lines, although other embodiments may have more or less optional components. The embodiment ofFIG. 8Dillustrates a multiple-input single-output (MISO) implementation of the amplifier ofFIG. 8B. In the embodiment ofFIG. 8D, constant envelope signals761,763,765and767, output from vector modulators760,762,764, and766, are input into MISO PAs870and872. MISO PAs870and872are two-input single-output power amplifiers. In an embodiment, MISO PAs870and872include elements770,772,774,776,794-797as shown in the embodiment ofFIG. 7Aor functional equivalence thereof. In another embodiment, MISO PAs870and872may include other elements, such as optional pre-drivers and optional process detection circuitry. In another embodiment, MISO PAs870and872may include other elements, such as pre-drivers, not shown in the embodiment ofFIG. 7A. Further, MISO PAs870and872are not limited to being two-input PAs as shown inFIG. 8D. In other embodiments as will be described further below with reference toFIGS. 51A-H, PAs870and872can have any number of inputs and outputs.

Other aspects of vector power amplifier800D substantially correspond to those described above with respect to vector power amplifiers700and800B.

A Cartesian-Polar-Cartesian-Polar (CPCP) 2-Branch VPA embodiment shall now be described (The name of this embodiment is provided for ease of reference, and is not limiting).

According to the Cartesian-Polar-Cartesian-Polar (CPCP) 2-Branch VPA method, a time-varying complex envelope signal is decomposed into 2 substantially constant envelope constituent signals. The constituent signals are individually amplified, and then summed to construct an amplified version of the original time-varying complex envelope signal. In addition, the phase angle of the time-varying complex envelope signal is determined and the resulting summation of the constituent signals are phase shifted by the appropriate angle.

In one embodiment of the CPCP 2-Branch VPA method, a magnitude and a phase angle of a time-varying complex envelope signal are calculated from in-phase and quadrature components of a signal. Given the magnitude information, two substantially constant envelope constituents are calculated from a normalized version of the desired time-varying envelope signal, wherein the normalization includes implementation specific manipulation of phase and/or amplitude. The two substantially constant envelope constituents are then phase shifted by an appropriate angle related to the phase shift of the desired time-varying envelope signal. The substantially constant envelope constituents are then individually amplified substantially equally, and summed to generate an amplified version of the original desired time-varying envelope signal.

FIGS. 9A and 9Bconceptually illustrate the CPCP 2-Branch VPA embodiment using a phasor signal representation. InFIG. 9A, phasor {right arrow over (Rin)}represents a time-varying complex envelope input signal r(t). At any instant of time, {right arrow over (Rin)} reflects a magnitude and a phase shift angle of signal r(t). In the example shown inFIG. 9A, {right arrow over (Rin)} is characterized by a magnitude R and a phase shift angle θ. As described above, the phase shift angle is measured relative to a reference signal.

Referring toFIG. 9A, {right arrow over (R′)} represents the relative amplitude component of {right arrow over (R)}ingenerated by {right arrow over (U)}′ and {right arrow over (L)}′.

Still referring toFIG. 9A, it is noted that, at any time instant, {right arrow over (R′)} can be obtained by the sum of an upper phasor {right arrow over (U′)} and a lower phasor {right arrow over (L′)}. Further, {right arrow over (U′)} and {right arrow over (L′)} can be maintained to have substantially constant magnitude. The phasors, {right arrow over (U′)} and {right arrow over (L′)}, accordingly, represent two substantially constant envelope signals. r′(t) can thus be obtained, at any time instant, by the sum of two substantially constant envelope signals that correspond to phasors {right arrow over (U′)} and {right arrow over (L)}′.

The phase shifts of phasors {right arrow over (U′)} and {right arrow over (L′)} relative to {right arrow over (R′)} are set according to the desired magnitude R of {right arrow over (R′)}. In the simplest case, when upper and lower phasors {right arrow over (U′)} and {right arrow over (L′)} are selected to have equal magnitude, upper and lower phasors {right arrow over (U′)} and {right arrow over (L′)} are substantially symmetrically shifted in phase relative to {right arrow over (R′)}. This is illustrated in the example ofFIG. 9A. It is noted that terms and phrases indicating or suggesting orientation, such as but not limited to “upper and lower” are used herein for ease of reference and are not functionally or structurally limiting.

It can be verified that, for the case illustrated inFIG. 9A, the phase shift of {right arrow over (U′)} and {right arrow over (L′)} relative to {right arrow over (R′)}, illustrated as angle

ϕ2
inFIG. 9A, is related to the magnitude of {right arrow over (R′)} as follows:

ϕ2=cot-1(R2⁢1-R24)(7)
where R represents a normalized magnitude of phasor {right arrow over (R′)}.

Equation (7) can further be reduced to

ϕ2=cos-1⁡(R2)(7.10)
where R represents a normalized magnitude of phasor {right arrow over (R′)}.

Alternatively, any substantially equivalent mathematical equations or other substantially equivalent mathematical techniques such as look up tables can be used.

It follows from the above discussion that, in phasor representation, any phasor {right arrow over (R′)} of variable magnitude and phase can be constructed by the sum of two constant magnitude phasor components:
{right arrow over (R′)}={right arrow over (U′)}+{right arrow over (L′)}
|{right arrow over (U)}|=|{right arrow over (L)}|=A=constant  (8)

Correspondingly, in the time domain, a time-varying envelope sinusoidal signal r′(t)=R(t)×cos(ωt) is constructed by the sum of two constant envelope signals as follows:

r′⁡(t)=⁢U′⁡(t)+L′⁡(t);U′⁡(t)=⁢A×cos⁡(ω⁢⁢t+ϕ2);L′⁡(t)=⁢A×cos⁡(ω⁢⁢t-ϕ2);(9)
where A is a constant and

ϕ2
is as shown in equation (7).

FromFIG. 9A, it can be further verified that equations (9) can be rewritten as:
r′(t)=U′(t)+L′(t);
U′(t)=Ccos(ωt)+α sin(ωt);
L′(t)=Ccos(ωt)−β sin(ωt);  (10)
where C denotes the real part component of phasors {right arrow over (U′)} and {right arrow over (L′)} and is
equal to

A×cos⁢(ϕ2).
Note that C is a common component of {right arrow over (U′)} and {right arrow over (L′)}. α and β denote the imaginary part components of phasors {right arrow over (U′)} and {right arrow over (L′)}, respectively.

r′⁡(t)=2⁢C×cos⁡(ω⁢⁢t)=2⁢A×cos⁢(ϕ2)×cos⁡(ω⁢⁢t).
As understood by a person skilled in the art based on the teachings herein, other equivalent and/or simplified representations of the above representations of the quantities A, B, and C may also be used, including look up tables, for example.

Note that {right arrow over (Rin)} is shifted by θ degrees relative to {right arrow over (R′)}. Accordingly, using equations (8), it can be deduced that:
{right arrow over (Rin)}={right arrow over (R′)}ejθ=({right arrow over (U′)}+{right arrow over (L′)})ejθ={right arrow over (U′)}ejθ={right arrow over (L′)}ejθ(11)

Equations (11) imply that a representation of {right arrow over (Rin)} can be obtained by summing phasors {right arrow over (U′)} and {right arrow over (L′)}, described above, shifted by θ degrees. Further, an amplified output version, {right arrow over (Rout)}, of {right arrow over (Rin)} can be obtained by separately amplifying substantially equally each of the 0 degrees shifted versions of phasors {right arrow over (U′)} and {right arrow over (L′)}, and summing them.FIG. 9Billustrates this concept. InFIG. 9B, phasors {right arrow over (U)} and {right arrow over (L)} represent θ degrees shifted and amplified versions of phasors {right arrow over (U′)} and {right arrow over (L′)} Note that, since {right arrow over (U′)} and {right arrow over (L′)} are constant magnitude phasors, {right arrow over (U)} and {right arrow over (L)} are also constant magnitude phasors. Phasors {right arrow over (U)} and {right arrow over (L)} sum, as shownFIG. 9B, to phasor {right arrow over (Rout)}, which is a power amplified version of input signal {right arrow over (Rin)}.

Equivalently, in the time domain, it can be shown that:
rout(t)=U(t)+L(t);
U(t)=K[Ccos(ωt+θ)+α sin(ωt+θ)];
L(t)=K[Ccos(ωt+θ)−β sin(ωt+θ)].  (12)
where rout(t) corresponds to the time domain signal represented by phasor {right arrow over (Rout)}, U(t) and L(t) correspond to the time domain signals represents by phasors {right arrow over (U)} and {right arrow over (L)}, and K is the power amplification factor.

A person skilled in the art will appreciate that, whereas the time domain representations in equations (9) and (10) have been provided for the case of a sinusoidal waveform, equivalent representations can be developed for non-sinusoidal waveforms using appropriate basis functions.

FIG. 10is a block diagram that conceptually illustrates an exemplary embodiment1000of the CPCP 2-Branch VPA embodiment. An output signal r(t) of desired power level and frequency characteristics is generated from in-phase and quadrature components according to the CPCP 2-Branch VPA embodiment.

In the example ofFIG. 10, a clock signal1010represents a reference signal for generating output signal r(t). Clock signal1010is of the same frequency as that of desired output signal r(t).

Referring toFIG. 10, an Iclk_phase signal1012and a Qclk_phase signal1014represent amplitude analog values that are multiplied by the in-phase and quadrature components of Clk signal1010and are calculated from the baseband I and Q signals.

Still referring toFIG. 10, clock signal1010is multiplied with Iclk_phase signal1012. In parallel, a 90° degrees shifted version of clock signal1010is multiplied with Qclk_phase signal1014. The two multiplied signals are combined to generate Rclk signal1016. Rclk signal1016is of the same frequency as clock signal1010. Further, Rclk signal1016is characterized by a phase shift angle according to the ratio of Q(t) and I(t). The magnitude of Rclk signal1016is such that R2clk=I2clk_phase+Q2clk_phase. Accordingly, Rclk signal1016represents a substantially constant envelope signal having the phase characteristics of the desired output signal r(t).

Still referring toFIG. 10, Rclk signal1016is input, in parallel, into two vector modulators1060and1062. Vector modulators1060and1062generate the U(t) and L(t) substantially constant envelope constituents, respectively, of the desired output signal r(t) as described in (12). In vector modulator1060, an in-phase Rclk signal1020, multiplied with Common signal1028, is combined with a 90° degree shifted version1018of Rclk signal, multiplied with first signal1026. In parallel, in vector modulator1062, an in-phase Rclk signal1022, multiplied with Common signal1028, is combined with a 90° degrees shifted version1024of Rclk signal, multiplied with second signal1030. Common signal1028, first signal1026, and second signal1030correspond, respectively, to the real part C and the imaginary parts α and β described in equation (12).

Output signals1040and1042of respective vector modulators1060and1062correspond, respectively, to the U(t) and L(t) constant envelope constituents of input signal r(t).

As described above, signals1040and1042are characterized by having substantially equal and constant magnitude envelopes. Accordingly, when signals1040and1042are input into corresponding power amplifiers (PA)1044and1046, corresponding amplified signals1048and1050are substantially constant envelope signals.

Power amplifiers1044and1046apply substantially equal power amplification to signals1040and1042, respectively. In an embodiment, the power amplification level of PAs1044and1046is set according to the desired power level of output signal r(t). Further, amplified signals1048and1050are in-phase relative to each other. Accordingly, when summed together, as shown inFIG. 10, resulting signal1052corresponds to the desired output signal r(t).

FIG. 10Ais another exemplary embodiment1000A of the CPCP 2-Branch VPA embodiment. Embodiment1000A represents a Multiple Input Single Output (MISO) implementation of embodiment1000ofFIG. 10.

In embodiment1000A, constant envelope signals1040and1042, output from vector modulators1060and1062, are input into MISO PA1054. MISO PA1054is a two-input single-output power amplifier. In an embodiment, MISO PA1054may include various elements, such as pre-drivers, drivers, power amplifiers, and process detectors (not shown inFIG. 10A), for example. Further, MISO PA1054is not limited to being a two-input PA as shown inFIG. 10A. In other embodiments, as will be described further below with reference toFIGS. 51A-H, PA1054can have any number of inputs.

Operation of the CPCP 2-Branch VPA embodiment is depicted in the process flowchart1100ofFIG. 11.

The process begins at step1110, which includes receiving a baseband representation of the desired output signal. In an embodiment, this involves receiving in-phase (I) and quadrature (Q) components of the desired output signal. In another embodiment, this involves receiving magnitude and phase of the desired output signal.

Step1120includes receiving a clock signal set according to a desired output signal frequency of the desired output signal. In the example ofFIG. 10, step1120is achieved by receiving clock signal1010.

Step1130includes processing the clock signal to generate a normalized clock signal having a phase shift angle according to the received I and Q components. In an embodiment, the normalized clock signal is a constant envelope signal having a phase shift angle according to a ratio of the I and Q components. The phase shift angle of the normalized clock is relative to the original clock signal. In the example ofFIG. 10, step1130is achieved by multiplying clock signal1010's in-phase and quadrature components with Iclk_phase1012and Qclk_phase1014signals, and then summing the multiplied signal to generate Rclk signal1016.

Step1140includes the processing of the I and Q components to generate the amplitude information required to produce first and second substantially constant envelope constituent signals.

Step1150includes processing the amplitude information of step1140and the normalized clock signal Rclk to generate the first and second constant envelope constituents of the desired output signal. In an embodiment, step1150involves phase shifting the first and second constant envelope constituents of the desired output signal by the phase shift angle of the normalized clock signal. In the example ofFIG. 10, step1150is achieved by vector modulators1060and1062modulating Rclk signal1016with first signal1026, second signal1030, and common signal1028to generate signals1040and1042.

Step1160includes individually amplifying the first and second constant envelope constituents, and summing the amplified signals to generate the desired output signal. In an embodiment, the amplification of the first and second constant envelope constituents is substantially equal and according to a desired power level of the desired output signal. In the example ofFIG. 10, step1160is achieved by PAs1044and1046amplifying signals1040and1042to generate amplified signals1048and1050.

FIG. 12is a block diagram that illustrates an exemplary embodiment of a vector power amplifier1200implementing the process flowchart1100. Optional components are illustrated with dashed lines, although in other embodiments more or less components may be optional.

Referring toFIG. 12, in-phase (I) and quadrature (Q) information signal1210is received by an I and Q Data Transfer Function module1216. In an embodiment, I and Q Data Transfer Function1216samples signal1210according to a sample clock1212. I and Q information signal1210includes baseband I and Q information of a desired output signal r(t).

In an embodiment, I and Q Data Transfer Function module1216processes information signal1210to generate information signals1220,1222,1224, and1226. The operation of I and Q Data Transfer Function module1216is further described below in section 3.4.

Referring toFIG. 12, information signal1220includes quadrature amplitude information of first and second constant envelope constituents of a baseband version of desired output signal r(t). With reference toFIG. 9A, for example, information signal1220includes the α and β quadrature components. Referring again toFIG. 12, information signal1226includes in-phase amplitude information of the first and second constant envelope constituents of the baseband version of signal r(t). With reference toFIG. 9A, for example, information signal1226includes the common C in-phase component.

Still referring toFIG. 12, information signals1222and1224include normalized in-phase Iclk_phase and quadrature Qclk_phase signals, respectively. Iclk_phase and Qclk_phase are normalized versions of the I and Q information signals included in signal1210. In an embodiment, Iclk_phase and Qclk_phase are normalized such that that (I2clk_phase+Q2clk_phase=constant). It is noted that the phase of signal1250corresponds to the phase of the desired output signal and is created from Iclk_phase and Qclk_phase. Referring toFIG. 9B, Iclk_phase and Qclk_phase are related to I and Q as follows:

where θ represents the phase of the desired output signal, represented b phasor {right arrow over (Rout)} inFIG. 9B. The sign information of the baseband I and Q information must be taken into account to calculate θ for all four quadrants.

In the exemplary embodiment ofFIG. 12, information signals1220,1222,1224, and1226are digital signals. Accordingly, each of signals1220,1222,1224, and1226is fed into a corresponding digital-to-analog converter (DAC)1230,1232,1234, and1236. The resolution and sample rate of DACs1230,1232,1234, and1236is selected according to specific signaling schemes. DACs1230,1232,1234, and1236are controlled by DAC clock signals1221,1223,1225, and1227, respectively. DAC clock signals1221,1223,1225, and1227may be derived from a same clock signal or may be independent.

In other embodiments, information signals1220,1222,1224, and1226are generated in analog format and no DACs are required.

Referring toFIG. 12, DACs1230,1232,1234, and1236convert digital information signals1220,1222,1224, and1226into corresponding analog signals, and input these analog signal into optional interpolation filters1231,1233,1235, and1237, respectively. Interpolation filters1231,1233,1235, and1237, which also serve as anti-aliasing filters, shape the DACs output signals to produce the desired output waveform. Interpolation filters1231,1233,1235, and1237generate signals1240,1244,1246, and1248, respectively. Signal1242represents the inverse of signal1240.

Still referring toFIG. 12, signals1244and1246, which include Iclk_phase and Qclk_phase information, are input into a vector modulator1238. Vector modulator1238multiplies signal1244with a channel clock signal1214. Channel clock signal1214is selected according to a desired output signal frequency. In parallel, vector modulator1238multiplies signal1246with a 90° shifted version of channel clock signal1214. In other words, vector modulator1238generates an in-phase component having amplitude of Iclk_phase and a quadrature component having amplitude of Qclk_phase.

Vector modulator1238combines the two modulated signals to generate Rclk signal1250. Rclk signal1250is a substantially constant envelope signal having the desired output frequency and a phase shift angle according to the I and Q data included in signal1210.

Still referring toFIG. 12, signals1240,1242, and1248include the U, L, and Common C amplitude components, respectively, of the complex envelope of signal r(t). Signals1240,1242, and1248along with Rclk signal1250are input into vector modulators1260and1262.

Vector modulator1260combines signal1240, multiplied with a 90° shifted version of Rclk signal1250, and signal1248, multiplied with a 0° shifted version of Rclk signal1250, to generate output signal1264. In parallel, vector modulator1262combines signal1242, multiplied with a 90° shifted version of Rclk signal1250, and signal1248, modulated with a 0° shifted version of Rclk signal1250, to generate output signal1266.

Output signals1264and1266represent substantially constant envelope signals. Further, phase shifts of output signals1264and1266relative to Rclk signal1250are determined by the angle relationships associated with the ratios α/C and β/C, respectively. In an embodiment, α=−β and therefore output signals1264and1266are symmetrically phased relative to Rclk signal1250. With reference toFIG. 9B, for example, output signals1264and1266correspond, respectively, to the {right arrow over (U)} and {right arrow over (L)} constant magnitude phasors.

A sum of output signals1264and1266results in a channel-clock-modulated signal having the I and Q characteristics of baseband signal r(t). To achieve a desired power level at the output of vector power amplifier1200, however, signals1264and1266are amplified to generate an amplified output signal. In the embodiment ofFIG. 12, signals1264and1266are, respectively, input into power amplifiers (PAs)1270and1272and amplified. In an embodiment, PAs1270and1272include switching power amplifiers. Autobias circuitry1218controls the bias of PAs1270and1272as further described below in section 3.5.2. In the embodiment ofFIG. 12, for example, autobias circuitry1218provides a bias voltage1228to PAs1270and1272.

In an embodiment, PAs1270and1272apply substantially equal power amplification to respective constant envelope signals1264-1266. In an embodiment, the power amplification is set according to the desired output power level. In other embodiments of vector power amplifier1200, PA drivers and/or pre-drivers are additionally employed to provide additional power amplification capability to the amplifier. In the embodiment ofFIG. 12, for example, PA drivers1284and1286are optionally added, respectively, between vector modulators1260and1262and subsequent PAs1270and1272.

Respective output signals1274and1276of PAs1270and1272are substantially constant envelope signals. Further, when output signals1274and1276are summed, the resulting signal has minimal non-linear distortion. In the embodiment ofFIG. 12, output signals1274and1276are coupled together to generate output signal1280of vector power amplifier1200. In an embodiment, no isolation is used in coupling the outputs of PAs1270and1272. Accordingly, minimal power loss is incurred by the coupling. In an embodiment, the outputs of PAs1270and1272are directly coupled together using a wire. Direct coupling in this manner means that there is minimal or no resistive, inductive, or capacitive isolation between the outputs of PAs1270and1272. In other words, outputs of PAs1270and1272are coupled together without intervening components. Alternatively, in an embodiment, the outputs of PAs1270and1272are coupled together indirectly through inductances and/or capacitances that result in low or minimal impedance connections, and/or connections that result in minimal isolation and minimal power loss. Alternatively, outputs of PAs1270and1272are coupled using well known combining techniques, such as Wilkinson, hybrid combiners, transformers, or known active combiners. In an embodiment, the PAs1270and1272provide integrated amplification and power combining in a single operation. In an embodiment, one or more of the power amplifiers and/or drivers described herein are implemented using multiple input, single output power amplification techniques, examples of which are shown inFIGS. 12A,12B, and51A-H.

Output signal1280represents a signal having the I and Q characteristics of baseband signal r(t) and the desired output power level and frequency. In embodiments of vector power amplifier1200, a pull-up impedance1288is coupled between the output of vector power amplifier1200and a power supply. In other embodiments, an impedance matching network1290is coupled at the output of vector power amplifier1200. Output stage embodiments according to power amplification methods and systems of the present invention will be further described below in section 3.5.

In other embodiments of vector power amplifier1200, process detectors are employed to compensate for any process variations in circuitry of the amplifier. In the exemplary embodiment ofFIG. 12, for example, process detector1282is optionally added to monitor variations in PA drivers1284and1286.

FIG. 12Ais a block diagram that illustrates another exemplary embodiment of a vector power amplifier1200A implementing the process flowchart1100. Optional components are illustrated with dashed lines, although in other embodiments more or less components may be optional.

Embodiment1200A illustrates a multiple-input single-output (MISO) implementation of embodiment1200. In embodiment1200A, constant envelope signals1261and1263, output from vector modulators1260and1262, are input into MISO PA1292. MISO PA1292is a two-input single-output power amplifier. In an embodiment, MISO PA1292includes elements1270,1272,1282,1284, and1286as shown in the embodiment ofFIG. 12. In another embodiment, MISO PA1292may include other elements, such as pre-drivers, not shown in the embodiment ofFIG. 12. Further, MISO PA1292is not limited to being a two-input PA as shown inFIG. 12A. In other embodiments as will be described further below with reference toFIGS. 51A-H, PA1292can have any number of inputs and outputs.

Still referring toFIG. 12A, embodiment1200A illustrates one implementation for delivering autobias signals to MISO PA1292. In the embodiment ofFIG. 12A, Autobias signal1228generated by Autobias circuitry1218, has one or more signals derived from it to bias different stages of MISO PA1292. As shown in the example ofFIG. 12A, three bias control signals Bias A, Bias B, and Bias C are derived from Autobias signal1228, and then input at different stages of MISO PA1292. For example, Bias C may be the bias signal to the pre-driver stage of MISO PA1292. Similarly, Bias B and Bias A may be the bias signals to the driver and PA stages of MISO PA1292.

In another implementation, shown in embodiment1200B ofFIG. 12B, Autobias circuitry1218generates separate Autobias signals1295,1296, and1295, corresponding to Bias A, Bias B, and Bias C, respectively. Signals1295,1296, and1297may or may not be generated separately within Autobias circuitry1218, but are output separately as shown. Further, signals1295,1296, and1297may or may not be related as determined by the biasing of the different stages of MISO PA1294.

Other aspects of vector power amplifiers1200A and1200B substantially correspond to those described above with respect to vector power amplifier1200.

FIG. 13is a block diagram that illustrates another exemplary embodiment1300of a vector power amplifier according to the CPCP 2-Branch VPA embodiment. Optional components are illustrated with dashed lines, although in other embodiments more or less components may be optional.

In the exemplary embodiment ofFIG. 13, a DAC of sufficient resolution and sample rate1320replaces DACs1230,1232,1234and1236of the embodiment ofFIG. 12. DAC1320is controlled by a DAC clock1324.

DAC1320receives information signal1310from I and Q Data Transfer Function module1216. Information signal1310includes identical information content to signals1220,1222,1224and1226in the embodiment ofFIG. 12.

DAC1320may output a single analog signal at a time. Accordingly, a sample-and-hold architecture may be used as shown inFIG. 13.

DAC1320sequentially outputs analog signals1332,1334,1336,1336to a first set of sample-and-hold circuits1342,1344,1346, and1348. In an embodiment, DAC1230is clocked at a sufficient rate to replace DACs1230,1232,1234, and1236of the embodiment ofFIG. 12. An output selector1322determines which of output signals1332,1334,1336, and1338should be selected for output.

DAC1320's DAC clock signal1324, output selector signal1322, and sample-and-hold clocks1340A-D and1350are controlled by a control module that can be independent or integrated into transfer function module1216.

In an embodiment, sample-and-hold circuits (S/H)1342,1344,1346, and1348hold the received analog values and, according to a clock signal1340A-D, release the values to a second set of sample-and-hold circuits1352,1354,1356, and1358. For example, S/H1342release its value to S/H1352according to a received clock signal1340A. In turn, sample-and-hold circuits1352,1354,1356, and1358hold the received analog values, and simultaneously release the values to interpolation filters1231,1233,1235, and1237according to a common clock signal1350. A common clock signal1350is used in order to ensure that the outputs of S/H1352,1354,1356, and1358are time-aligned.

In another embodiment, a single layer of S/H circuitry that includes S/H1342,1344,1346, and1348can be employed. Accordingly, S/H circuits1342,1344,1346, and1348receive analog values from DAC1320, and each releases its received value according to a clock independent of the others. For example, S/H1342is controlled by clock1340A, which may not be synchronized with clock1340B that controls S/H1344. To ensure that outputs of S/H circuits1342,1344,1346, and1348are time-aligned, delays between clocks1340A-D are pre-compensated for in prior stages of the amplifier. For example, DAC1320outputs signal1332,1334,1336, and1338with appropriately selected delays to S/H circuits1342,1344,1346, and1348in order to compensate for the time differences between clocks1340A-D.

Other aspects of vector power amplifier1300are substantially equivalent to those described above with respect to vector power amplifier1200.

FIG. 13Ais a block diagram that illustrates another exemplary embodiment1300A of a vector power amplifier according to the CPCP 2-Branch VPA embodiment. Optional components are illustrated with dashed lines, although in other embodiments more or less components may be optional. Embodiment1300A is a MISO implementation of embodiment1300ofFIG. 13.

In the embodiment ofFIG. 13A, constant envelope signals1261and1263output from vector modulators1260and1262are input into MISO PA1360. MISO PA1360is a two-input single-output power amplifier. In an embodiment, MISO PA1360includes elements1270,1272,1282,1284, and1286as shown in the embodiment ofFIG. 13. In another embodiment, MISO PA1360may include other elements, such as pre-drivers, not shown in the embodiment ofFIG. 13, or functional equivalents thereof. Further, MISO PA1360is not limited to being a two-input PA as shown inFIG. 13A. In other embodiments as will be described further below with reference toFIGS. 51A-H, PA1360can have any number of inputs.

The embodiment ofFIG. 13Afurther illustrates two different sample and hold architectures with a single or two levels of S/H circuitry as shown. The two implementations have been described above with respect toFIG. 13.

Embodiment1300A also illustrates optional bias control circuitry1218and associated bias control signal1325,1326, and1327. Signals1325,1326, and1327may be used to bias different stages of MISO PA1360in certain embodiments.

Other aspects of vector power amplifier1300A are equivalent to those described above with respect to vector power amplifiers1200and1300.

3.3) Direct Cartesian 2-Branch Vector Power Amplifier

A Direct Cartesian 2-Branch VPA embodiment shall now be described. This name is used herein for reference purposes, and is not functionally or structurally limiting.

According to the Direct Cartesian 2-Branch VPA embodiment, a time-varying envelope signal is decomposed into two constant envelope constituent signals. The constituent signals are individually amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal.

In one embodiment of the Direct Cartesian 2-Branch VPA embodiment, a magnitude and a phase angle of a time-varying envelope signal are calculated from in-phase and quadrature components of an input signal. Using the magnitude and phase information, in-phase and quadrature amplitude components are calculated for two constant envelope constituents of the time-varying envelope signal. The two constant envelope constituents are then generated, amplified equally or substantially equally, and summed to generate an amplified version of the original time-varying envelope signal Rin.

The concept of the Direct Cartesian 2-Branch VPA will now be described with reference toFIGS. 9A and 14.

As described and verified above with respect toFIG. 9A, the phasor {right arrow over (R′)} can be obtained by the sum of an upper phasor {right arrow over (U′)} and a lower phasor {right arrow over (L′)} appropriately phased to produce {right arrow over (R′)}. {right arrow over (R′)} is calculated to be proportional to the magnitude Rin. Further, {right arrow over (U′)} and {right arrow over (L′)} can be maintained to have substantially constant magnitude. In the time domain, {right arrow over (U′)} and {right arrow over (L′)} represent two substantially constant envelope signals. The time domain equivalent r′(t) of {right arrow over (R′)} can thus be obtained, at any time instant, by the sum of two substantially constant envelope signals.

For the case illustrated inFIG. 9A, the phase shift of {right arrow over (U′)} and {right arrow over (L′)} relative to {right arrow over (R′)}, illustrated as angle

ϕ2
inFIG. 9A, is related to the magnitude of {right arrow over (R′)} as follows:

ϕ2=cot-1(R2⁢1-R24)(13)
where R represents the normalized magnitude of phasor {right arrow over (R′)}.

In the time domain, it was shown that a time-varying envelope signal, r′(t)=R(t) cos(ωt) for example, can be constructed by the sum of two constant envelope signals as follows:
r′(t)=U′(t)+L′(t);
U′(t)=C×cos(ωt)+α×sin(ωt);
L′(t)=C×cos(ωt)−−β×sin(ωt).  (14)
where C denotes the in-phase amplitude component of phasors {right arrow over (U′)} and {right arrow over (L′)} and is equal or substantially equal to

A×cos⁢(ϕ2)
(A being a constant). α and β denote the quadrature amplitude components of phasors {right arrow over (U′)} and {right arrow over (L′)}, respectively.

α=β=A×sin⁢(ϕ2).
Note that equations (14) can be modified for non-sinusoidal signals by changing the basis function from sinusoidal to the desired function.

FIG. 14illustrates phasor {right arrow over (R)} and its two constant magnitude constituent phasors {right arrow over (U)} and {right arrow over (L)}. {right arrow over (R)} is shifted by θ degrees relative to {right arrow over (R′)} inFIG. 9A. Accordingly, it can be verified that:
{right arrow over (R)}={right arrow over (R′)}×ejθ=({right arrow over (U′)}+{right arrow over (L′)})×ejθ={right arrow over (U)}+{right arrow over (L)};
{right arrow over (U)}={right arrow over (U)}×ejθ;
{right arrow over (L)}={right arrow over (L)}′×ejθ(15)

where φ1(t) and φ2(t) represent an appropriately selected orthogonal basis functions.

From equations (18) and (19), it is noted that it is sufficient to calculate the values of α, β, C and sin(Θ) and cos(Θ)) in order to determine the two constant envelope constituents of a time-varying envelope signal r(t). Further, α, β and C can be entirely determined from magnitude and phase information, equivalently I and Q components, of signal r(t).

FIG. 15is a block diagram that conceptually illustrates an exemplary embodiment1500of the Direct Cartesian 2-Branch VPA embodiment. An output signal r(t) of desired power level and frequency characteristics is generated from in-phase and quadrature components according to the Direct Cartesian 2-Branch VPA embodiment.

In the example ofFIG. 15, a clock signal1510represents a reference signal for generating output signal r(t). Clock signal1510is of the same frequency as that of desired output signal r(t).

Referring toFIG. 1.5, exemplary embodiment1500includes a first branch1572and a second branch1574. The first branch1572includes a vector modulator1520and a power amplifier (PA)1550. Similarly, the second branch1574includes a vector modulator1530and a power amplifier (PA)1560.

Still referring toFIG. 15, clock signal1510is input, in parallel, into vector modulators1520and1530. In vector modulator1520, an in-phase version1522of clock signal1510, multiplied with Uxsignal1526, is summed with a 90° degrees shifted version1524of clock signal1510, multiplied with Uysignal1528. In parallel, in vector modulator1530, an in-phase version1532of clock signal1510, multiplied with Lx signal1536, is summed with a 90° degrees shifted version1534of clock signal1510, multiplied with Ly signal1538. Uxsignal1526and Uysignal1528correspond, respectively, to the in-phase and quadrature amplitude components of the U(t) constant envelope constituent of signal r(t) provided in equation (19). Similarly, Lxsignal1536, and Lysignal1538correspond, respectively, to the in-phase and quadrature amplitude components of the L(t) constant envelope constituent of signal r(t) provided in equation (19).

Accordingly, respective output signals1540and1542of vector modulators1520and1530correspond, respectively, to the U(t) and L(t) constant envelope constituents of signal r(t) as described above in equations (19). As described above, signals1540and1542are characterized by having equal and constant or substantially equal and constant magnitude envelopes.

Referring toFIG. 15, to generate the desired power level of output signal r(t), signals1540and1542are input into corresponding power amplifiers1550and1560.

In an embodiment, power amplifiers1550and1560apply equal or substantially equal power amplification to signals1540and1542, respectively. In an embodiment, the power amplification level of PAs1550and1560is set according to the desired power level of output signal r(t).

Amplified output signals1562and1564are substantially constant envelope signals. Accordingly, when summed together, as shown inFIG. 15, resulting signal1570corresponds to the desired output signal r(t).

FIG. 15Ais another exemplary embodiment1500A of the Direct Cartesian 2-Branch VPA embodiment. Embodiment1500A represents a Multiple Input Signal Output (MISO) implementation of embodiment1500ofFIG. 15.

In embodiment1500A, constant envelope signals1540and1542, output from vector modulators1520and1530, are input into MISO PA1580. MISO PA1580is a two-input single-output power amplifier. In an embodiment, MISO PA1580may include various elements, such as pre-drivers, drivers, power amplifiers, and process detectors (not shown inFIG. 15A), for example. Further, MISO PA1580is not limited to being a two-input PA as shown inFIG. 15A. In other embodiments, as will be described further below with reference toFIGS. 51A-H, PA1580can have any number of inputs.

Operation of the Direct Cartesian 2-Branch VPA embodiment is depicted in the process flowchart1600ofFIG. 16. The process begins at step1610, which includes receiving a baseband representation of a desired output signal. In an embodiment, the baseband representation includes I and Q components. In another embodiment, the I and Q components are RF components that are down-converted to baseband.

Step1620includes receiving a clock signal set according to a desired output signal frequency of the desired output signal. In the example ofFIG. 15, step1620is achieved by receiving clock signal1510.

Step1630includes processing the I and Q components to generate in-phase and quadrature amplitude information of first and second constant envelope constituent signals of the desired output signal. In the example ofFIG. 15, the in-phase and quadrature amplitude information is illustrated by Ux, Uy, Lx, and Ly.

Step1640includes processing the amplitude information and the clock signal to generate the first and second constant envelope constituent signals of the desired output signal. In an embodiment, the first and second constant envelope constituent signals are modulated according to the desired output signal frequency. In the example ofFIG. 15, step1640is achieved by vector modulators1520and1530, clock signal1510, and amplitude information signals1526,1528,1536, and1538to generate signals1540and1542.

Step1650includes amplifying the first and second constant envelope constituents, and summing the amplified signals to generate the desired output signal. In an embodiment, the amplification of the first and second constant envelope constituents is according to a desired power level of the desired output signal. In the example ofFIG. 15, step1650is achieved by PAs1550and1560amplifying respective signals1540and1542and, subsequently, by the summing of amplified signals1562and1564to generate output signal1574.

FIG. 17is a block diagram that illustrates an exemplary embodiment of a vector power amplifier1700implementing the process flowchart1600. Optional components are illustrated with dashed lines, although other embodiments may have more or less optional components.

Referring toFIG. 17, in-phase (I) and quadrature (Q) information signal1710is received by an I and Q Data Transfer Function module1716. In an embodiment, I and Q Data Transfer Function module1716samples signal1710according to a sample clock1212. I and Q information signal1710includes baseband I and Q information.

In an embodiment, I and Q Data Transfer Function module1716processes information signal1710to generate information signals1720,1722,1724, and1726. The operation of I and Q Data Transfer Function module1716is further described below in section 3.4.

Referring toFIG. 17, information signal1720includes vector modulator1750quadrature amplitude information that is processed through DAC1730to generate signal1740. Information signal1722includes vector modulator1750in-phase amplitude information that is processed through DAC1732to generate signal1742. Signals1740and1742are calculated to generate a substantially constant envelope signal1754. With reference toFIG. 14, for example, information signals1720and1722include the upper quadrature and in-phase components Uyand Ux, respectively.

Still referring toFIG. 17, information signal1726includes vector modulator1752quadrature amplitude information that is processed through DAC1736to generate signal1746. Information signal1724includes vector modulator1752in-phase amplitude information that is processed through DAC1734to generate signal1744. Signals1744and1746are calculated to generate a substantially constant envelope signal1756. With reference toFIG. 14, for example, information signals1724and1726include the lower in-phase and quadrature components Lxand Ly, respectively.

In the exemplary embodiment ofFIG. 17, information signals1720,1722,1724and1726are digital signals. Accordingly, each of signals1720,1722,1724and1726is fed into a corresponding digital-to-analog converter (DAC)1730,1732,1734, and1736. The resolution and sample rates of DACs1730,1732,1734, and1736are selected according to the specific desired signaling schemes. DACs1730,1732,1734, and1736are controlled by DAC clock signals1721,1723,1725, and1727, respectively. DAC clock signals1721,1723,1725, and1727may be derived from a same clock or may be independent of each other.

In other embodiments, information signals1720,1722,1724and1726are generated in analog format and no DACs are required.

Referring toFIG. 17, DACs1730,1732,1734, and1736convert digital information signals1720,1722,1724, and1726into corresponding analog signals, and input these analog signals into optional interpolation filters1731,1733,1735, and1737, respectively. Interpolation filters1731,1733,1735, and1737, which also serve as anti-aliasing filters, shape the DACs output signals to produce the desired output waveform. Interpolation filters1731,1733,1735, and1737generate signals1740,1742,1744, and1746, respectively.

Still referring toFIG. 17, signals1740,1742,1744, and1746are input into vector modulators1750and1752. Vector modulators1750and1752generate first and second constant envelope constituents. In the embodiment ofFIG. 17, channel clock1714is set according to a desired output signal frequency to thereby establish the frequency of the output signal1770.

Referring toFIG. 17, vector modulator1750combines signal1740, multiplied with a 90° shifted version of channel clock signal1714, and signal1742, multiplied with a 0° shifted version of channel clock signal1714, to generate output signal1754. In parallel, vector modulator1752combines signal1746, multiplied with a 90° shifted version of channel clock signal1714, and signal1744, multiplied with a 0° shifted version of channel clock signal1714, to generate output signal1756.

Output signals1754and1756represent constant envelope signals. A sum of output signals1754and1756results in a carrier signal having the I and Q characteristics of the original baseband signal. In embodiments, to generate a desired power level at the output of vector power amplifier1700, signals1754and1756are amplified and then summed. In the embodiment ofFIG. 17, for example, signals1754and1756are, respectively, input into corresponding power amplifiers (PAs)1760and1762. In an embodiment, PAs1760and1762include switching power amplifiers. Autobias circuitry1718controls the bias of PAs1760and1762. In the embodiment ofFIG. 17, for example, autobias circuitry1718provides a bias voltage1728to PAs1760and1762.

In an embodiment, PAs1760and1762apply equal or substantially equal power amplification to respective constant envelope signals1754and1756. In an embodiment, the power amplification is set according to the desired output power level. In other embodiments of vector power amplifier1700, PA drivers are additionally employed to provide additional power amplification capability to the amplifier. In the embodiment ofFIG. 17, for example, PA drivers1774and1776are optionally added, respectively, between vector modulators1750and1752and subsequent PAs1760and1762.

Respective output signals1764and1766of PAs1760and1762are substantially constant envelope signals. In the embodiment of FIG.17, output signals1764and1766are coupled together to generate output signal1770of vector power amplifier1700. In embodiments, it is noted that the outputs of PAs1760and1762are directly coupled. Direct coupling in this manner means that there is minimal or no resistive, inductive, or capacitive isolation between the outputs of PAs1760and1762. In other words, outputs of PAs1760and1762are coupled together without intervening components. Alternatively, in an embodiment, the outputs of PAs1760and1762are coupled together indirectly through inductances and/or capacitances that result in low or minimal impedance connections, and/or connections that result in minimal isolation and minimal power loss. Alternatively, outputs of PAs1760and1762are coupled using well known combining techniques, such as Wilkinson, hybrid couplers, transformers, or known active combiners. In an embodiment, the PAs1760and1762provide integrated amplification and power combining in a single operation. In an embodiment, one or more of the power amplifiers and/or drivers described herein are implemented using multiple input, single output (MISO) power amplification techniques, examples of which are shown inFIGS. 17A,17B, and51A-H.

Output signal1770represents a signal having the desired I and Q characteristics of the baseband signal and the desired output power level and frequency. In embodiments of vector power amplifier1700, a pull-up impedance1778is coupled between the output of vector power amplifier1700and a power supply. In other embodiments, an impedance matching network1780is coupled at the output of vector power amplifier1700. Output stage embodiments according to power amplification methods and systems of the present invention will be further described below in section 3.5.

In other embodiments of vector power amplifier1700, process detectors are employed to compensate for any process and/or temperature variations in circuitry of the amplifier. In the exemplary embodiment ofFIG. 17, for example, process detector1772is optionally added to monitor variations in PA drivers1774and1776.

FIG. 17Ais a block diagram that illustrates another exemplary embodiment1700A of a vector power amplifier implementing process flowchart1600. Optional components are illustrated with dashed lines, although other embodiments may have more or less optional components. Embodiment1700A illustrates a multiple-input single-output (MISO) implementation of the amplifier ofFIG. 17. In the embodiment ofFIG. 17A, constant envelope signals1754and1756, output from vector modulators1750and1760, are input into MISO PA1790. MISO PA1790is a two-input single-output power amplifier. In an embodiment, MISO PA1790include elements1760,1762,1772,1774, and1776as shown in the embodiment ofFIG. 17, or functional equivalents thereof. In another embodiment, MISO PA1790may include other elements, such as pre-drivers, not shown in the embodiment ofFIG. 17. Further, MISO PA1790is not limited to being a two-input PA as shown inFIG. 17A. In other embodiments, as will be described further below with reference toFIGS. 51A-H, PA1790can have any number of inputs.

In another embodiment of embodiment1700, shown as embodiment1700B ofFIG. 17B, optional Autobias circuitry1218generates separate bias control signals1715,1717, and1719, corresponding to Bias A, Bias B, and Bias C, respectively. Signals1715,1717, and1719may or may not be generated separately within Autobias circuitry1718, but are output separately as shown. Further, signals1715,1717, and1719may or may not be related as determined by the biasing required for the different stages of MISO PA1790.

FIG. 18is a block diagram that illustrates another exemplary embodiment1800of a vector power amplifier according to the Direct Cartesian 2-Branch VPA embodiment ofFIG. 16. Optional components are illustrated with dashed lines, although other embodiments may have more or less optional components.

In the exemplary embodiment ofFIG. 18, a DAC1820of sufficient resolution and sample rate replaces DACs1730,1732,1734, and1736of the embodiment ofFIG. 17. DAC1820is controlled by a DAC clock1814.

DAC1820receives information signal1810from I and Q Data Transfer Function module1716. Information signal1810includes identical information content to signals1720,1722,1724, and1726in the embodiment ofFIG. 17.

DAC1820may output a single analog signal at a time. Accordingly, a sample-and-hold architecture may be used as shown inFIG. 18.

In the embodiment ofFIG. 18, DAC1820sequentially outputs analog signals1822,1824,1826, and1828to sample-and-hold circuits1832,1834,1836, and1838, respectively. In an embodiment, DAC1820is of sufficient resolution and sample rate to replace DACs1720,1722,1724, and1726of the embodiment ofFIG. 17. An output selector1812determines which of output signals1822,1824,1826, and1828are selected for output.

DAC1820's DAC clock signal1814, output selector signal1812, and sample-and-hold clocks1830A-D, and1840are controlled by a control module that can be independent or integrated into transfer function module1716.

In an embodiment, sample-and-hold circuits1832,1834,1836, and1838sample and hold their respective values and, according to a clock signal1830A-D, release the values to a second set of sample-and-hold circuits1842,1844,1846, and1848. For example, S/H1832release's its value to S/H1842according to a received clock signal1830A. In turn, sample-and-hold circuits1842,1844,1846, and1848hold the received analog values, and simultaneously release the values to interpolation filters1852,1854,1856, and1858according to a common clock signal1840.

In another embodiment, a single set of S/H circuitry that includes S/H1832,1834,1836, and1838can be employed. Accordingly, S/H circuits1832,1834,1836, and1838receive analog values from DAC1820, and each samples and holds its received value according to independent clocks1830A-D. For example, S/H1832is controlled by clock1830A, which may not be synchronized with clock1830B that controls S/H1834. For example, DAC1820outputs signals1822,1824,1826, and1828with appropriately selected analog values calculated by transfer function module1716to S/H circuits1832,1834,1836, and1838in order to compensate for the time differences between clocks1830A-D.

Other aspects of vector power amplifier1800correspond substantially to those described above with respect to vector power amplifier1700.

FIG. 18Ais a block diagram that illustrates another exemplary embodiment1800A of a vector power amplifier according to the Direct Cartesian 2-Branch VPA embodiment. Optional components are illustrated with dashed lines, although in other embodiments more or less components may be optional. Embodiment1800A is a Multiple Input Single Output (MISO) implementation of embodiment1800ofFIG. 18.

In the embodiment ofFIG. 18A, constant envelope signals1754and1756, output from vector modulators1750and1752, are input into MISO PA1860. MISO PA1860is a two-input single-output power amplifier. In an embodiment, MISO PA1860includes elements1744,1746,1760,1762, and1772as shown in the embodiment ofFIG. 18, or functional equivalents thereof. In another embodiment, MISO PA1860may include other elements, such as pre-drivers, not shown in the embodiment ofFIG. 17. Further, MISO PA1860is not limited to being a two-input PA as shown inFIG. 18A. In other embodiments as will be described further below with reference toFIGS. 51A-H, PA1860can have any number of inputs.

The embodiment ofFIG. 18Afurther illustrates two different sample and hold architectures with a single or two levels of S/H circuitry as shown. The two implementations have been described above with respect toFIG. 18.

Other aspects of vector power amplifier1800A are substantially equivalent to those described above with respect to vector power amplifiers1700and1800.

3.4) I and Q Data to Vector Modulator Transfer Functions

In some of the above described embodiments, I and Q data transfer functions are provided to transform received I and Q data into amplitude information inputs for subsequent stages of vector modulation and amplification. For example, in the embodiment ofFIG. 17, I and Q Data Transfer Function module1716processes I and Q information signal1710to generate in-phase and quadrature amplitude information signals1720,1722,1724, and1726of first and second constant envelope constituents1754and1756of signal r(t). Subsequently, vector modulators1750and1752utilize the generated amplitude information signals1720,1722,1724, and1726to create the first and second constant envelope constituent signals1754and1756. Other examples include modules710,712, and1216inFIGS. 7,8,12, and13. These modules implement transfer functions to transform I and/or Q data into amplitude information inputs for subsequent stages of vector modulation and amplification.

According to the present invention, I and Q Data Transfer Function modules may be implemented using digital circuitry, analog circuitry, software, firmware or any combination thereof.

Several factors affect the actual implementation of a transfer function according to the present invention, and vary from embodiment to embodiment. In one aspect, the selected VPA embodiment governs the amplitude information output of the transfer function and associated module. It is apparent, for example, that I and Q Data Transfer Function module1216of the CPCP 2-Branch VPA embodiment1200differs in output than I and Q Data Transfer Function module1716of the Direct Cartesian 2-Branch VPA embodiment1700.

In another aspect, the complexity of the transfer function varies according to the desired modulation scheme(s) that need to be supported by the VPA implementation. For example, the sample clock, the DAC sample rate, and the DAC resolution are selected in accordance with the appropriate transfer function to construct the desired output waveform(s).

According to the present invention, transfer function embodiments may be designed to support one or more VPA embodiments with the ability to switch between the supported embodiments as desired. Further, transfer function embodiments and associated modules can be designed to accommodate a plurality of modulation schemes. A person skilled in the art will appreciate, for example, that embodiments of the present invention may be designed to support a plurality of modulation schemes (individually or in combination) including, but not limited to, BPSK, QPSK, OQPSK, DPSK, CDMA, WCDMA, W-CDMA, GSM, EDGE, MPSK, MQAM, MSK, CPSK, PM, FM, OFDM, and multi-tone signals. In an embodiment, the modulation scheme(s) may be configurable and/or programmable via the transfer function module.

FIG. 19is a process flowchart1900that illustrates an example I and Q transfer function embodiment according to the Cartesian 4-Branch VPA embodiment. The process begins at step1910, which includes receiving an in-phase data component and a quadrature data component. In the Cartesian 4-Branch VPA embodiment ofFIG. 7A, for example, this is illustrated by I Data Transfer Function module710receiving I information signal702, and Q Data Transfer Function module712receiving Q information signal704. It is noted that, in the embodiment ofFIG. 7A, I and Q Data Transfer Function modules710and712are illustrated as separate components. In implementation, however, I and Q Data Transfer Function modules710and712may be separate or combined into a single module.

Step1920includes calculating a phase shift angle between first and second substantially equal and constant envelope constituents of the I component. In parallel, step1920also includes calculating a phase shift angle between first and second substantially equal and constant envelope constituents of the Q component. As described above, the first and second constant envelope constituents of the I components are appropriately phased relative to the I component. Similarly, the first and second constant envelope constituents of the Q components are appropriately phased relative to the Q component. In the embodiment ofFIG. 7A, for example, step1920is performed by I and Q Data Transfer Function modules710and712.

Step1930includes calculating in-phase and quadrature amplitude information associated with the first and second constant envelope constituents of the I component. In parallel, step1930includes calculating in-phase and quadrature amplitude information associated with the first and second constant envelope constituents of the Q component. In the embodiment ofFIG. 7A, for example, step1930is performed by and I and Q Data Transfer Function modules710and712.

Step1940includes outputting the calculated amplitude information to a subsequent vector modulation stage. In the embodiment ofFIG. 7A, for example, I and Q Transfer Function modules710and712output amplitude information signals722,724,726, and728to vector modulators760,762,764, and766through DACs730,732,734, and736.

FIG. 20is a block diagram that illustrates an exemplary embodiment2000of a transfer function module, such as transfer function modules710and712ofFIG. 7A, implementing the process flowchart1900. In the example ofFIG. 20, transfer function module2000receives I and Q data signals2010and2012. In an embodiment, I and Q data signals2010and2012represent I and Q data components of a baseband signal, such as signals702and704inFIG. 7A.

Referring toFIG. 20, in an embodiment, transfer function module2000samples I and Q data signals2010and2012according to a sampling clock2014. Sampled I and Q data signals are received by components2020and2022, respectively, of transfer function module2000. Components2020and2022measure, respectively, the magnitudes of the sampled I and Q data signals. In an embodiment, components2020and2022are magnitude detectors.

Components2020and2022output the measured I and Q magnitude information to components2030and2032, respectively, of transfer function module2000. In an embodiment, the measured I and Q magnitude information is in the form of digital signals. Based on the I magnitude information, component2030calculates a phase shift angle φIbetween first and second equal and constant or substantially equal and constant envelope constituents of the sampled I signal. Similarly, based on the Q magnitude information, component2032calculates phase shift angle φQbetween a first and second equal and constant or substantially equal and constant envelope constituents of the sampled Q signal. This operation shall now be further described.

In the embodiment ofFIG. 20, φIand φQare illustrated as functions F(|{right arrow over (I)}|) and f(|{right arrow over (Q)}|) of the I and Q magnitude signals. In embodiments, functions f(|{right arrow over (I)}|) and f(|{right arrow over (Q)}|) are set according to the relative magnitudes of the baseband I and Q signals respectively. f(|{right arrow over (I)}|) and f(|{right arrow over (Q)}|) according to embodiments of the present invention will be further described below in section 3.4.4.

Referring toFIG. 20, components2030and2032output the calculated phase shift information to components2040and2042, respectively. Based on phase shift angle φI, component2040calculates in-phase and quadrature amplitude information of the first and second constant envelope constituents of the sampled I signal. Similarly, based on phase shift angle φQ, component2042calculates in-phase and quadrature amplitude information of the first and second constant envelope constituents of the sampled Q signal. Due to symmetry, in embodiments of the invention, calculation is required for 4 values only. In the example ofFIG. 20, the values are illustrated as sgn(I)×IUX, IUY, QUX, and sgn(Q)×QUY, as provided inFIG. 5.

Components2040and2042output the calculated amplitude information to subsequent stages of the vector power amplifier. In embodiments, each of the four calculated values is output separately to a digital-to-analog converter. As shown in the embodiment ofFIG. 7Afor example, signals722,724,726, and728are output separately to DACs730,732,734, and736, respectively. In other embodiments, signals722,724,726, and728are output into a single DAC as shown inFIGS. 800A and 800B.

FIG. 21is a process flowchart2100that illustrates an example I and Q transfer function embodiment according to the CPCP 2-Branch VPA embodiment. The process begins at step2110, which includes receiving in-phase (I) and quadrature (Q) data components of a baseband signal. In the CPCP 2-Branch VPA embodiment ofFIG. 12, for example, this is illustrated by I and Q Data Transfer Function module1216receiving I and Q information signal1210.

Step2120includes determining the magnitudes |I| and |Q| of the received I and Q data components.

Step2130includes calculating a magnitude |R| of the baseband signal based on the measured |I| and |Q| magnitudes. In an embodiment, |R| is such that |R|2=|I|2+|Q|2. In the embodiment ofFIG. 12, for example, steps2120and2130are performed by I and Q Data Transfer Function module1216based on received information signal1210.

Step2140includes normalizing the measured |I| and |Q| magnitudes. In an embodiment, |I| and |Q| are normalized to generate an Iclk_phase and Qclk_phase signals (as shown inFIG. 10) such that |Iclk_phase|2+|Qclk_phase|2=constant. In the embodiment ofFIG. 12, for example, step2140is performed by I and Q Data Transfer Function module1216based on received information signal1210.

Step2150includes calculating in-phase and quadrature amplitude information associated with first and second constant envelope constituents. In the embodiment ofFIG. 12, for example, step2150is performed by I and Q Data Transfer Function module1216based on the envelope magnitude |R|.

Step2160includes outputting the generated Iclk_phase and Qclk_phase (from step2140) and the calculated amplitude information (from step2150) to appropriate vector modulators. In the embodiment ofFIG. 12, for example, I and Q Data Transfer Function module1216output information signals1220,1222,1224, and1226to vector modulators1238,1260, and1262through DACs1230,1232,1234, and1236.

FIG. 22is a block diagram that illustrates an exemplary embodiment2200of a transfer function module (such as module1216ofFIG. 12) implementing the process flowchart2100. In the example ofFIG. 22, transfer function module2200receives I and Q data signal2210. In an embodiment, I and Q data signal2210includes I and Q components of a baseband signal, such as signal1210in the embodiment ofFIG. 12, for example.

In an embodiment, transfer function module2200samples I and Q data signal2210according to a sampling clock2212. Sampled I and Q data signals are received by component2220of transfer function module2200. Component2220measures the magnitudes |{right arrow over (I)}| and |{right arrow over (Q)}| of the sampled I and Q data signals.

Based on the measured |{right arrow over (I)}| and |{right arrow over (Q)}| magnitudes, component2230calculates the magnitude |R| of the baseband signal. In an embodiment, |{right arrow over (R)}|is such that |{right arrow over (R)}|2=|{right arrow over (I)}|2+|{right arrow over (Q)}|2.

In parallel, component2240normalizes the measured |{right arrow over (I)}| and |{right arrow over (Q)}|magnitudes. In an embodiment, |{right arrow over (I)}| and |{right arrow over (Q)}| are normalized to generate Iclk_phase and Qclk_phase signals such that |Iclk_phase|2+|Qclk_phase|2=constant, where |Iclk_phase| and |Qclk_phase| represent normalized magnitudes of |{right arrow over (I)}| and |{right arrow over (Q)}|.

Typically, given that the constant has a value A, the measured |{right arrow over (I)}| and |{right arrow over (I)}| magnitudes are both divided by the quantity

Component2250receives the calculated |{right arrow over (R)}|magnitude from component2230, and based on it calculates a phase shift angle φ between first and second constant envelope constituents. Using the calculated phase shift angle φ, component2050then calculates in-phase and quadrature amplitude information associated with the first and second constant envelope constituents.

In the embodiment ofFIG. 22, the phase shift angle φ is illustrated as a function f(|{right arrow over (R)}|) of the calculated magnitude |{right arrow over (R)}|.

Referring toFIG. 22, components2240and2250output the normalized |Iclk_phase| and |Qclk_phase| magnitude information and the calculated amplitude information to DAC's for input into the appropriate vector modulators. In embodiments, the output values are separately output to digital-to-analog converters. As shown in the embodiment ofFIG. 12, for example, signals1220,1222,1224, and1226are output separately to DACs1230,1232,1234, and1236, respectively. In other embodiments, signals1220,1222,1224, and1226are output into a single DAC as shown inFIGS. 3 and 13A.

3.4.3) Direct Cartesian 2-Branch Transfer Function

FIG. 23is a process flowchart2300that illustrates an example I and Q transfer function embodiment according to the Direct Cartesian 2-Branch VPA embodiment. The process begins at step2310, which includes receiving in-phase (I) and quadrature (Q) data components of a baseband signal. In the Direct Cartesian 2-Branch VPA embodiment ofFIG. 17, for example, this is illustrated by I and Q Data Transfer Function module1716receiving I and Q information signal1710.

Step2320includes determining the magnitudes |I| and |Q| of the received I and Q data components.

Step2330includes calculating a magnitude |R| of the baseband signal based on the measured |I| and |Q| magnitudes. In an embodiment, |R|is such that |R|2=|I|2+|Q|2. In the embodiment ofFIG. 17, for example, steps2320and2330are performed by I and Q Data Transfer Function module1716based on received information signal1710.

Step2340includes calculating a phase shift angle θ of the baseband signal based on the measured |I| and |Q| magnitudes. In an embodiment, θ is such that

θ=tan-1⁡(QI),
and wherein the sign of I and Q determine the quadrant of θ. In the embodiment ofFIG. 17, for example, step2340is performed by I and Q Data Transfer Function module1216based on I and Q data components received in information signal1210.

Step2350includes calculating in-phase and quadrature amplitude information associated with a first and second constant envelope constituents of the baseband signal. In the embodiment ofFIG. 17, for example, step2350is performed by I and Q Data Transfer Function module1716based on previously calculated magnitude |R| and phase shift angle θ.

Step2360includes outputting the calculated amplitude information to DAC's for input into the appropriate vector modulators. In the embodiment ofFIG. 17, for example, I and Q Data Transfer Function module1716output information signals1720,1722,1724, and1726to vector modulators1750and1752through DACs1730,1732,1734, and1736. In other embodiments, signals1720,1722,1724, and1726are output into a single DAC as shown inFIGS. 8 and 18A.

FIG. 24is a block diagram that illustrates an exemplary embodiment2400of a transfer function module implementing the process flowchart2300. In the example ofFIG. 24, transfer function module2400(such as transfer function module1716) receives I and Q data signal2410, such as signal1710inFIG. 17. In an embodiment, I and Q data signal2410includes I and Q data components of a baseband signal.

In an embodiment, transfer function module2400samples I and Q data signal2410according to a sampling clock2412. Sampled I and Q data signals are received by component2420of transfer function module2200. Component2420measures the magnitudes |{right arrow over (I)}| and |{right arrow over (Q)}| of the sampled I and Q data signals.

Based on the measured |{right arrow over (I)}| and |{right arrow over (Q)}| magnitudes, component2430calculates the magnitude |{right arrow over (R)}|. In an embodiment, |{right arrow over (R)}| is such that |{right arrow over (R)}|2=|{right arrow over (I)}|2+|{right arrow over (Q)}|2.

In parallel, component2240calculates the phase shift angle θ of the baseband signal. In an embodiment, θ is such that

θ=tan-1⁡(Q→I→),
where the sign of I and Q determine the quadrant of θ.

Component2450receives the calculated |{right arrow over (R)}|magnitude from component2430, and based on it calculates a phase shift angle φ between first and second constant envelope constituent signals. In the embodiment ofFIG. 24, the phase shift angle φ is illustrated as a function f3|{right arrow over (R)}|) of the calculated magnitude |{right arrow over (R)}|. This is further described in section 3.4.4.

In parallel, component2450receives the calculated phase shift angle θ from component2440. As functions of φ and θ, component2450then calculates in-phase and quadrature amplitude information for the vector modulator inputs that generate the first and second constant envelope constituents. In an embodiment, the in-phase and quadrature amplitude information supplied to the vector modulators are according to the equations provided in (18).

Component2450outputs the calculated amplitude information to subsequent stages of the vector power amplifier. In embodiments, the output values are separately output to digital-to-analog converters. As shown in the embodiment ofFIG. 17, for example, signals1720,1722,1724, and1726are output separately to DACs1730,1732,1734, and1736, respectively. In other embodiments, signals1720,1722,1724, and1726are output into a single DAC as shown inFIGS. 8 and 18A.

3.4.4) Magnitude to Phase Shift Transform

According to the present invention, any periodic waveform that can be represented by a Fourier series and a Fourier transform can be decomposed into two or more constant envelope signals.

Below are provided two examples for sinusoidal and square waveforms.

3.4.4.1) Magnitude to Phase Shift Transform for Sinusoidal Signals:

Consider a time-varying complex envelope sinusoidal signal r(t). In the time domain, it can be represented as:
r(t)=R(t)sin(ωt+δ(t))  (20)
where R(t) represents the signal's envelope magnitude at time t, δ(t) represents the signal's phase shift angle at time t, and ω represents the signal's frequency in radians per second.

It can be verified that, at any time instant t, signal r(t) can be obtained by the sum of two appropriately phased equal and constant or substantially equal and constant envelope signals. In other words, it can be shown that:
R(t)·sin(ωt+δ(t))=Asin(ωt)+Asin(ωt+φ(t))  (21)
for an appropriately chosen phase shift angle φ(t) between the two constant envelope signals. The phase shift angle φ(t) will be derived as a function of R(t) in the description below. This is equivalent to the magnitude to phase shift transform for sinusoidal signals.

Note, from equation (22), that signal r(t) is written as a sum of an in-phase component and a quadrature component. Accordingly, the envelope magnitude R(t) can be written as:
R(t)=√{square root over ((Asin(φ(t)))2+(A(1+cos(φ(t))))2)}{square root over ((Asin(φ(t)))2+(A(1+cos(φ(t))))2)};
R(t)=√{square root over (2A(A+cos(φ(t))))}.  (23)

Equation (23) relates the envelope magnitude R(t) of signal r(t) to the phase shift angle φ(t) between two constant envelope constituents of signal r(t). The constant envelope constituents have equal or substantially equal envelope magnitude A, which is typically normalized to 1.

Inversely, from equation (23), the phase shift angle φ(t) can be written as a function of R(t) as follows:

Equation (24) represents the magnitude to phase shift transform for the case of sinusoidal signals, and is illustrated inFIG. 26.

3.4.4.2) Magnitude to Phase Shift Transform for Square Wave Signals:

FIG. 28illustrates a combination of two constant envelope square wave signals according to embodiments of the present invention. InFIG. 28, signals2810and2820are constant envelope signals having a period T, a duty cycle γT (0<y<1), and envelope magnitudes A1and A2, respectively.

Signal2830results from combining signals2810and2820. According to embodiments of the present invention, signal2830will have a magnitude equal or substantially equal to a product of signals2810and2820. In other words, signal2830will have a magnitude of zero whenever either of signals2810or2820has a magnitude of zero, and a non-zero magnitude when both signals2810and2820have non-zero magnitudes.

Further, signal2830represents a pulse-width-modulated signal. In other words, the envelope magnitude of signal2830is determined according to the pulse width of signal2830over one period of the signal. More specifically, the envelope magnitude of signal2830is equal or substantially to the area under the curve of signal2830.

Referring toFIG. 28, signals2810and2820are shown time-shifted relative to each other by a time shift t′. Equivalently, signals2810and2820are phase-shifted relative to each other by a phase shift angle

Still referring toFIG. 28, note that the envelope magnitude R of signal2830, inFIG. 28, is given by:
R=A1×A2×(γT−t′)  (25)

Accordingly, it can be deduced that φ is related to R according to:

Note, from equation (26), that R is at a maximum of γA1A2when φ=0. In other words, the envelope magnitude is at a maximum when the two constant envelope signals are in-phase with each other.

In typical implementations, signals2810and2820are normalized and have equal or substantially equal envelope magnitude of 1. Further, signals2810and2820typically have a duty cycle of 0.5. Accordingly, equation (26) reduces to:

Equation (27) illustrates the magnitude to phase shift transform for the case of normalized and equal or substantially equal envelope magnitude square wave signals. Equation (27) is illustrated inFIG. 26.

3.4.5) Waveform Distortion Compensation

In certain embodiments, magnitude to phase shift transforms may not be implemented exactly as theoretically or practically desired. In fact, several factors may exist that require adjustment or tuning of the derived magnitude to phase shift transform for optimal (or at least improved) operation. In practice, phase and amplitude errors may exist in the vector modulation circuitry, gain and phase imbalances can occur in the vector power amplifier branches, and distortion may exist in the MISO amplifier itself including but not limited to errors introduced by directly combining at a single circuit node transistor outputs within the MISO amplifier described herein. Each of these factors either singularly or in combination will contribute to output waveform distortions that result in deviations from the desired output signal r(t). When output waveform distortion exceeds system design requirements, waveform distortion compensation may be required.

FIG. 25illustrates the effect of waveform distortion on a signal using phasor signal representation. InFIG. 25, {right arrow over (R)} represents a phasor representation of a desired signal r(t). In the example ofFIG. 25, waveform distortion can cause the actual output phasor to vary from r(t) anywhere within the phasor error region. An exemplary phasor error region is illustrated inFIG. 25, and is equal or substantially equal to the maximum error vector magnitude. Phasors {right arrow over (R1)} and {right arrow over (R2)} represent examples of potential output phasors that deviate from the desired r(t).

According to embodiments of the present invention, waveform distortions can be measured, calculated, or estimated during the manufacture of the system and/or in real time or non-real time operation.FIG. 54AandFIG. 55are examples of methods that can be used for phasor error measurement and correction. These waveform distortions can be compensated for or reduced at various points in the system. For example, a phase error between the branch amplifiers can be adjusted by applying an analog voltage offset to the vector modulation circuitry, within the transfer function, and/or using real time or non-real time feedback techniques as shown in the example system illustrated inFIGS. 58,59and60. Similarly, branch amplification imbalances can be adjusted by applying an analog voltage offset to the vector modulation circuitry, within the transfer function, and/or using real time or non-real time feedback techniques as shown inFIGS. 58,59and60. In the system illustrated inFIGS. 58,59and60, for example, waveform distortion adjustment is performed, as illustrated inFIG. 60, using Differential Branch Amplitude Measurement Circuitry6024and Differential Branch Phase Measurement Circuitry6026, which provide a Differential Branch Amplitude signal5950and a Differential Branch Phase signal5948, respectively. These signals are input into an A/D Converter5732by input signal selector5946, with the values generated by A/D converter5732being input into Digital Control Module5602. Digital Control Module5602uses the values generated by A/D converter5732to calculate adjusted or offset values to provide control voltages for phase adjustments to Vector modulation circuitry5922,5924,5926, and5928and control voltages for amplitude adjustments to Gain Balance control circuitry6016. InFIG. 58, these control voltages are illustrated using Gain Balance Control signal5749and Phase Balance Control signal5751. The feedback approach described above also compensates for process variations, temperature variations, IC package variations, and circuit board variations by ensuring the system amplitude and phase errors remain with a specified tolerance. Additional example feedback and feedforward error measurement and compensation techniques are further described in section 4.1.2.

In other embodiments, the measured, calculated, or estimated waveform distortions are compensated for at the transfer function stage of the power amplifier. In this approach, the transfer function is designed to factor in and correct the measured, calculated, and/or estimated waveform distortions.FIG. 78illustrates a mathematical derivation of the magnitude to phase shift transform in the presence of amplitude and phase errors in branches of the VPA. Equation (28) inFIG. 78takes into account both phase and amplitude errors in an exemplary embodiment. Note that R*sin({acute over (ω)}*t+δ) inFIG. 78can be representative of either {right arrow over (R)}1or {right arrow over (R)}2inFIG. 25, for example. Equation (28) assumes that amplitudes A1and A2of the VPA branches can be different and that each branch can contain a respective phase error φe1(t) and φe2(t). For reference purposes, in a theoretically perfect system, A1=A2and φe1(t)=φe2(t)=0.6(t) is adjusted by quadrant based on the sign value of the input vectors I(t) and Q(t). As such, with no amplitude or phase errors, the phasor corresponding to R*sin({acute over (ω)}*t+δ) is aligned with the desired phasor {right arrow over (R)} inFIG. 25.

In some embodiments, in practice, amplitude and phase components of the phasor corresponding to R*sin({acute over (ω)}*t+δ) are compared to the desired phasor {right arrow over (R)} to generate system amplitude and phase error deviations. These amplitude and phase error deviations from the desired phasor {right arrow over (R)}, as shown inFIG. 25, can be accounted for in the system transfer function. In an embodiment, A1and A2can be substantially equalized and ωe1(t) and ωe2(t) can be minimized by properly adjusting the control inputs to the vector modulation circuitry. In an embodiment, as illustrated inFIG. 57, this is performed by the digital control module, which provides, using digital-to-analog converters DAC_01, DAC_02, DAC_03, and DAC_04, control inputs to the vector modulation circuitry.

Accordingly, given the fact that equations such as equation (28) can be used to calculate the resultant phasor at any instant in time based on the values of A1and A2and φe1(t) and φe2(t), transfer function modification(s) can be made to compensate for the system errors, and such transfer function modification(s) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Exemplary methods for generating error tables and/or mathematical functions to compensate for system errors are described in Section 4.1.2. It will be apparent to persons skilled in the relevant art(s) that these waveform distortion correction and compensation techniques can be implemented in either the digital or the analog domains, and implementation of such techniques will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.

3.5) Output Stage

An aspect of embodiments of the present invention lies in summing constituent signals at the output stage of a vector power amplifier (VPA). This is shown, for example, inFIG. 7where the outputs of PAs770,772,774, and776are summed. This is similarly shown inFIGS. 8,12,13,17, and18, for example. Various embodiments for combining the outputs of VPAs are described herein. While the following is described in the context of VPAs, it should be understood that the following teachings generally apply to coupling or summing the outputs of any active devices in any application.

FIG. 29illustrates a vector power amplifier output stage embodiment2900according to an embodiment of the present invention. Output stage2900includes a plurality of vector modulator signals2910-{1, . . . ,n} being input into a plurality of corresponding power amplifiers (PAs)2920-{1, . . . ,n}. As described above, signals2910-{1, . . . ,n} represent constituent signals of a desired output signal of the vector power amplifier.

In the example ofFIG. 29, PAs2910-{1, . . . ,n} equally amplify or substantially equally amplify input signals2910-{1, . . . ,n} to generate amplified output signals2930-{1, . . . ,n}. Amplified output signals2930-{1, . . . ,n} are coupled together directly at summing node2940. According to this example embodiment of the present invention, summing node2940includes no coupling or isolating element, such as a power combiner, for example. In the embodiment ofFIG. 29, summing node2940is a zero-impedance (or near-zero impedance) conducting wire. Accordingly, unlike in conventional systems that employ combining elements, the combining of output signals according to this embodiment of the present invention incurs minimal power loss.

In another aspect, output stage embodiments of the present invention can be implemented using multiple-input single-output (MISO) power amplifiers.

In another aspect, output stage embodiments of the present invention can be controlled to increase the power efficiency of the amplifier by controlling the output stage current according to the desired output power level.

In what follows, various output stage embodiments according to VPA embodiments of the present invention are provided in section 3.5.1. In section 3.5.2, embodiments of output stage current shaping functions, for increasing the power efficiency of certain VPA embodiments of the present invention, are presented. Section 3.5.3 describes embodiments of output stage protection techniques that may be utilized for certain output stage embodiments of the present invention.

3.5.1) Output Stage Embodiments

FIG. 30is a block diagram that illustrates a power amplifier (PA) output stage embodiment3000according to an embodiment of the present invention. Output stage embodiment3000includes a plurality of PA branches3005-{1, . . . ,n}. Signals3010-{1, . . . ,n} incoming from respective vector modulators represent inputs for output stage3000. According to this embodiment of the present invention, signals3010-{1, . . . ,n} represent equal and constant or substantially equal and constant envelope constituent signals of a desired output signal of the power amplifier.

PA branches3005-{1, . . . ,n} apply equal or substantially equal power amplification to respective signals3010-{1, . . . ,n}. In an embodiment, the power amplification level through PA branches3005-{1, . . . ,n} is set according to a power level requirement of the desired output signal.

In the embodiment ofFIG. 30, PA branches3005-{1, . . . ,n} each includes a power amplifier3040-{1, . . . ,n}. In other embodiments, drivers3030-{1, . . . ,n} and pre-drivers3020-{1, . . . ,n}, as illustrated inFIG. 30, may also be added in a PA branch prior to the power amplifier element. In embodiments, drivers and pre-drivers are employed whenever a required output power level may not be achieved in a single amplifying stage.

To generate the desired output signal, outputs of PA branches3005-{1, . . . ,n} are coupled directly at summing node3050. Summing node3050provides little or no isolation between the coupled outputs. Further, summing node3050represents a relatively lossless summing node. Accordingly, minimal power loss is incurred in summing the outputs of PAs3040-{1, . . . ,n}.

Output signal3060represents the desired output signal of output stage3000. In the embodiment ofFIG. 30, output signal3060is measured across a load impedance3070.

FIG. 31is a block diagram that illustrates another power amplifier (PA) output stage embodiment3100according to the present invention. Similar to the embodiment ofFIG. 30, output stage3100includes a plurality of PA branches3105-{1, . . . ,n}. Each of PA branches3105-{1, . . . ,n} may include multiple power amplification stages represented by a pre-driver3020-{1, . . . ,n}, driver3030-{1, . . . , n}, and power amplifier3040-{1, . . . ,n}. Output stage embodiment3100further includes pull-up impedances coupled at the output of each power amplification stage to provide biasing of that stage. For example, pull-up impedances3125-{1, . . . ,n} and 3135-{1, . . . ,n}, respectively, couple the pre-driver and driver stage outputs to power supply or independent bias power supplies. Similarly, pull-up impedance3145couples the PA stage outputs to the power supply or an independent bias power supply. According to this embodiment of the present invention, pull-up impedances represent optional components that may affect the efficiency but not necessarily the operation of the output stage embodiment.

FIG. 32is a block diagram that illustrates another power amplifier (PA) output stage embodiment3200according to the present invention. Similar to the embodiment ofFIG. 30, output stage3200includes a plurality of PA branches3205-{1, . . . ,n}. Each of PA branches3205-{1, . . . ,n} may include multiple power amplification stages represented by a pre-driver3020-{1, . . . ,n}, driver3030-{1, . . . ,n}, and power amplifier3040-{1, . . . ,n}. Output stage embodiment3200also includes pull-up impedances coupled at the output of each power amplification stage to achieve a proper biasing of that stage.

Further, output stage embodiment3200includes matching impedances coupled at the outputs of each power amplification stage to maximize power transfer from that stage. For example, matching impedances3210-{1, . . . ,n} and3220-{1, . . . ,n}, are respectively coupled to the pre-driver and driver stage outputs. Similarly, matching impedance3240is coupled at the PA stage output. Note that matching impedance3240is coupled to the PA output stage subsequent to summing node3250.

In the above-described embodiments ofFIGS. 30-32, the PA stage outputs are combined by direct coupling at a summing node. For example, in the embodiment ofFIG. 30, outputs of PA branches3005-{1, . . . ,n} are coupled together at summing node3050. Summing node3050is a near zero-impedance conducting wire that provides minimal isolation between the coupled outputs. Similar output stage coupling is shown inFIGS. 31 and 32. It is noted that in certain embodiments of the present invention, output coupling, as shown in the embodiments ofFIGS. 30-32or embodiments subsequently described below, may utilize certain output stage protection measures. These protection measures may be implemented at different stages of the PA branch. Further, the type of protection measures needed may be PA implementation-specific. A further discussion of output stage protection according to an embodiment of the present invention is provided in section 3.5.3.

FIG. 33is a block diagram that illustrates another power amplifier (PA) output stage embodiment3300according to the present invention. Similar to the embodiment ofFIG. 30, output stage3300includes a plurality of PA branches3305-{1, . . . ,n}. Each of PA branches3305-{1, . . . ,n} may include multiple power amplification stages represented by a pre-driver3020-{1, . . . ,n}, driver3030-{1, . . . , n}, and power amplifier3040-{1, . . . ,n}. Output stage embodiment3300may also include pull-up impedances3125-{1, . . . ,n},3135-{1, . . . , n}, and3145coupled at the output of each power amplification stage to achieve a proper biasing of that stage. Additionally, output stage embodiment3300may include matching impedances3210-{1, . . . ,n},3220-{1, . . . ,n}, and3240coupled at the output of each power amplification stage to maximize power transfer from that stage. Further, output stage embodiment3300receives an autobias signal3310, from an Autobias module3340, coupled at the PA stage input of each PA branch3305-{1, . . . ,n}. Autobias module3340controls the bias of PAs3040-{1, . . . ,n}. In an embodiment, autobias signal3340controls the amount of current flow through the PA stage according to a desired output power level and signal envelope of the output waveform. A further description of the operation of autobias signal and the autobias module is provided below in section 3.5.2.

FIG. 34is a block diagram that illustrates another power amplifier (PA) output stage embodiment3400according to the present invention. Similar to the embodiment ofFIG. 30, output stage3400includes a plurality of PA branches3405-{1, . . . ,n}. Each of PA branches3405-{1, . . . ,n} may include multiple power amplification stages represented by a pre-driver3020-{1, . . . ,n}, driver3030-{1, . . . , n}, and power amplifier3040-{1, . . . ,n}. Output stage embodiment3400may also include pull-impedances3125-{1, . . . ,n},3135-{1, . . . ,n}, and3145coupled at the output of each power amplification stage to achieve desired biasing of that stage. Additionally, output stage embodiment3400may include matching impedances3210-{1, . . . ,n},3220-{1, . . . ,n}, and3240coupled at the output of each power amplification stage to maximize power transfer from that stage. Further, output stage embodiment3400includes a plurality of harmonic control circuit networks3410-{1, . . . ,n} coupled at the PA stage input of each PA branch {1, . . . ,n}. Harmonic control circuit networks3410-{1, . . . ,n} may include a plurality of resistance, capacitance, and/or inductive elements and/or active devices coupled in series or in parallel. According to an embodiment of the present invention, harmonic control circuit networks3410-{1, . . . ,n} provide harmonic control functions for controlling the output frequency spectrum of the power amplifier. In an embodiment, harmonic control circuit networks3410-{1, . . . ,n} are selected such that energy transfer to the fundamental harmonic in the summed output spectrum is increased while the harmonic content of the output waveform is decreased. A further description of harmonic control according to embodiments of the present invention is provided below in section 3.6.

FIG. 35is a block diagram that illustrates another power amplifier (PA) output stage embodiment3500according to the present invention. Output stage embodiment3500represents a differential output equivalent of output stage embodiment3200ofFIG. 32. In embodiment3500, PA stage outputs3510-{1, . . . ,n} are combined successively to result in two aggregate signals. The two aggregate signals are then combined across a loading impedance, thereby having the output of the power amplifier represent the difference between the two aggregate signals. Referring toFIG. 35, aggregate signals3510and3520are coupled across loading impedance3530. The output of the power amplifier is measured across the loading impedance3530as the voltage difference between nodes3540and3550. According to embodiment3500, the maximum output of the power amplifier is obtained when the two aggregate signals are 180 degrees out-of-phase relative to each other. Inversely, the minimum output power results when the two aggregate signals are in-phase relative to each other.

FIG. 36is a block diagram that illustrates another output stage embodiment3600according to the present invention. Similar to the embodiment ofFIG. 30, output stage3600includes a plurality of PA branches3605-{1, . . . ,n}. Each of PA branches {1, . . . ,n} may include multiple power amplification stages represented by a pre-driver3020-{1, . . . ,n}, a driver3030-{1, . . . ,n}, and a power amplifier (PA)3620-{1, . . . ,n}.

FIG. 37is an example (related toFIG. 36) that illustrates an output signal of the PA stage of embodiment3600in response to square wave input signals. For ease of illustration, a two-branch PA stage is considered. In the example ofFIG. 37, square wave signals3730and3740are input, respectively, into BJT elements3710and3720. Note than when either of BJT elements3710or3720turns on, summing node3750is shorted to ground. Accordingly, when either of input signals3730or3740is high, output signal3780will be zero. Further, output signal3780will be high only when both input signals3730and3740are zero. According to this arrangement, PA stage3700performs pulse-width modulation, whereby the magnitude of the output signal is a function of the phase shift angle between the input signals.

Embodiments are not limited to npn BJT implementations as described herein. A person skilled in the art will appreciate, for example, that embodiments of the present invention may be implemented using pnp BJTs, CMOS, NMOS, PMOS, or other type of transistors. Further, embodiments can be implemented using GaAs and/or SiGe transistors with the desired transistor switching speed being a factor to consider.

Referring back toFIG. 36, it is noted that while PAs3620-{1, . . . , n) are each illustrated using a single BJT notation, each PA3620-{1, . . . ,n} may include a plurality of series-coupled transistors. In embodiments, the number of transistors included within each PA is set according to a required maximum output power level of the power amplifier. In other embodiments, the number of transistors in the PA is such that the numbers of transistors in the pre-driver, driver, and PA stages conform to a geometric progression.

FIG. 38illustrates an exemplary PA embodiment3800according to an embodiment of the present invention. PA embodiment3800includes a BJT element3870, a LC network3860, and a bias impedance3850. BJT element3870includes a plurality of BJT transistors Q1, . . . , Q8coupled in series. As illustrated inFIG. 38, BJT transistors Q1, . . . , Q8are coupled together at their base, collector, and emitter terminals. Collector terminal3880of BJT element3870provides an output terminal for PA3800. Emitter terminal3890of BJT element3870may be coupled to substrate or to an emitter terminal of a preceding amplifier stage. For example, emitter terminal3890is coupled to an emitter terminal of a preceding driver stage.

Referring toFIG. 38, LC network3860is coupled between PA input terminal3810and input terminal3820of BJT element3870. LC network3860includes a plurality of capacitive and inductive elements. Optionally, a Harmonic Control Circuit network3830is also coupled at input terminal3820of BJT element3870. As described above, the HCC network3830provides a harmonic control function for controlling the output frequency spectrum of the power amplifier.

Still referring toFIG. 38, bias impedance3850couples Iref signal3840to input terminal3820of BJT element3870. Iref signal3840represents an autobias signal that controls the bias of BJT element3870according to a desired output power level and signal envelope characteristics.

It is noted that, in the embodiment ofFIG. 38, BJT element3870is illustrated to include 8 transistors. It can be appreciated by a person skilled in the art, however, that BJT element3870may include any number of transistors as required to achieve the desired output power level of the power amplifier.

In another aspect, output stage embodiments can be implemented using multiple-input single-output (MISO) power amplifiers.FIG. 51Ais a block diagram that illustrates an exemplary MISO output stage embodiment5100A. Output stage embodiment5100A includes a plurality of vector modulator signals5110-{1, . . . ,n} that are input into MISO power amplifier (PA)5120. As described above, signals5110-{1, . . . ,n} represent constant envelope constituents of output signal5130of the power amplifier. MISO PA5120is a multiple input single output power amplifier. MISO PA5120receives and amplifies signals5110-{1, . . . ,n} providing a distributed multi signal amplification process to generate output signal5130.

It is noted that MISO implementations, similar to the one shown inFIG. 51A, can be similarly extended to any of the output stage embodiments described above. More specifically, any of the output stage embodiments ofFIGS. 29-37can be implemented using a MISO approach. Additional MISO embodiments will now be provided with reference toFIGS. 51B-I. It is noted that any of the embodiments described above can be implemented using any of the MISO embodiments that will now be provided.

Referring toFIG. 51A, MISO PA5120can have any number of inputs as required by the substantially constant envelope decomposition of the complex envelope input signal. For example, in a two-dimensional decomposition, a two-input power amplifier can be used. According to embodiments of the present invention, building blocks for creating MISO PAs for any number of inputs are provided.

FIG. 51Billustrates several MISO building blocks according to an embodiment of the present invention. MISO PA5110B represents a two-input single-output PA block. In an embodiment, MISO PA5110B includes two PA branches. The PA branches of MISO PA5110B may be equivalent to any PA branches described above with reference toFIGS. 29-37, for example. MISO PA5120B represents a three-input single-output PA block. In an embodiment, MISO PA5120B includes three PA branches. The PA branches of MISO PA5120B may equivalent to any PA branches described above with reference toFIGS. 29-37, for example.

Still referring toFIG. 51B, MISO PAs5110B and5120B represent basic building blocks for any multiple-input single-output power amplifier according to embodiments of the present invention. For example, MISO PA5130B is a four-input single-output PA, which can be created by coupling together the outputs of two two-input single-output PA blocks, such as MISO PA5110B, for example. This is illustrated inFIG. 51C. Similarly, it can be verified that MISO PA5140B, an n-input single-output PA, can be created from the basic building blocks5110B and5120B.

FIG. 51Dillustrates various embodiments of the two-input single output PA building block according to embodiments of the present invention.

Embodiment5110D represents an npn implementation of the two-input single output PA building block. Embodiment5110D includes two npn transistors coupled together using a common collector node, which provides the output of the PA. A pull-up impedance (not shown) can be coupled between the common collector node and a supply node (not shown).

Embodiment5130D represents a pnp equivalent of embodiment5110D. Embodiment5130D includes two pnp transistors coupled at a common collector node, which provides the output of the PA. A pull-down impedance (not shown) can be coupled between the common collector node and a ground node (not shown).

Embodiment5140D represents a complementary npn/pnp implementation of the two-input single output PA building block. Embodiment5140D includes an npn transistor and a pnp transistor coupled at a common collector node, which provides the output of the PA.

Still referring toFIG. 51D, embodiment5120D represents a NMOS implementation of the two-input single output PA building block. Embodiment5120D includes two NMOS transistors coupled at a common drain node, which provides the output of the PA.

Embodiment5160D represents an PMOS equivalent of embodiment5120D. Embodiment5120D includes two PMOS transistors coupled at a common drain node, which provides the output of the PA.

Embodiment5150D represents a complementary MOS implementation of the two-input single-output PA building block. Embodiment5150D includes a PMOS transistor and an NMOS transistor coupled at common drain node, which provides the output of the PA.

Two-input single-output embodiments ofFIG. 51Dcan be further extended to create multiple-input single-output PA embodiments.FIG. 51Eillustrates various embodiments of multiple-input single-output PAs according to embodiments of the present invention.

Embodiment5150E represents an npn implementation of a multiple-input single-output PA. Embodiment5150E includes a plurality of npn transistors coupled together using a common collector node, which provides the output of the PA. A pull-up impedance (not shown) can be coupled between the common collector node and a supply voltage (not shown). Note that an n-input single-output PA according to embodiment5150E can be obtained by coupling additional npn transistors to the two-input single-output PA building block embodiment5110D.

Embodiment5170E represents a pnp equivalent of embodiment5150E. Embodiment5170E includes a plurality of pnp transistors coupled together using a common collector node, which provides the output of the PA. A pull-down impedance (not shown) may be coupled between the common collector node and a ground node (not shown). Note than an n-input single-output PA according to embodiment5170E can be obtained by coupling additional pnp transistors to the two-input single-output PA building block embodiment5130D.

Embodiments5110E and5130E represent complementary npn/pnp implementations of a multiple-input single-output PA. Embodiments5110E and5130E may include a plurality of npn and/or pnp transistors coupled together using a common collector node, which provides the output of the PA. Note that an n-input single-output PA according to embodiment5110E can be obtained by coupling additional npn and/or pnp transistors to the two-input single-output PA building block embodiment5140D. Similarly, an n-input single-output PA according to embodiment5130E can be obtained by coupling additional npn and/or pnp transistors to the two-input single-output PA building block embodiment5130D.

Embodiment5180E represents an PMOS implementation of a multiple-input single-output PA. Embodiment5180E includes a plurality of PMOS transistors coupled together using a common drain node, which provides the output of the PA. Note that an n-input single-output PA according to embodiment5180E can be obtained by coupling additional NMOS transistors to the two-input single-output PA building block embodiment5160D.

Embodiment5160E represents a NMOS implementation of multiple-input single-output PA. Embodiment5160E includes a plurality of NMOS transistors coupled together using a common drain node, which provides the output of the PA. Note that an n-input single-output PA according to embodiment5160E can be obtained by coupling additional PMOS transistors to the two-input single-output PA building block embodiment5120D.

Embodiments5120E and5140E complementary MOS implementations of a multiple-input single-output PA. Embodiments5120E and5140E include a plurality of npn and pnp transistors coupled together using a common drain node, which provides the output of the PA. Note that a n-input single-output PA according to embodiment5120E can be obtained by coupling additional NMOS and/or PMOS transistors to the two-input single-output PA building block5150D. Similarly, an n-input single-output PA according to embodiment5140E can be obtained by coupling additional NMOS and/or PMOS transistors to the two-input single-output PA building block5160D.

FIG. 51Fillustrates further multiple-input single-output PA embodiments according to embodiments of the present invention. Embodiment5110F represents a complementary npn/pnp implementation of a multiple-input single-output PA. Embodiment5110F can be obtained by iteratively coupling together embodiments of PA building block5140D. Similarly, embodiment5120F represents an equivalent NMOS/PMOS complementary implementation of a multiple-input single-output PA. Embodiment5120F can be obtained by iteratively coupling together embodiments of PA building block5150D.

It must be noted that the multiple-input single-output embodiments described above may each correspond to a single or multiple branches of a PA. For example, referring toFIG. 29, any of the multiple-input single-output embodiments may be used to replace a single or multiple PAs2920-{1, . . . ,n}. In other words, each of PAs2920-{1, . . . ,n} may be implemented using any of the multiple-input single-output PA embodiments described above or with a single-input single-output PA as shown inFIG. 29.

It is further noted that the transistors shown in the embodiments ofFIGS. 51D,51E, and51F may each be implemented using a series of transistors as shown in the exemplary embodiment ofFIG. 38, for example.

FIG. 51Gillustrates further embodiments of the multiple-input single-output PA building blocks. Embodiment5110G illustrates an embodiment of the two-input single-output PA building block.

Embodiment5110G includes two PA branches that can each be implemented according to single-input single-output or multiple-input single-output PA embodiments as described above. Further, embodiment5110G illustrates an optional bias control signal5112G that is coupled to the two branches of the PA embodiment. Bias control signal5112G is optionally employed in embodiment5110G based on the specific implementation of the PA branches. In certain implementations, bias control will be required for proper operation of the PA. In other implementations, bias control is not required for proper operation of the PA, but may provide improved PA power efficiency, output circuit protection, or power on current protection.

Still referring toFIG. 51G, embodiment5120G illustrates an embodiment of the three-input single-output PA building block. Embodiment5120G includes three PA branches that can each be implemented according to single-input single-output or multiple-input single-output PA embodiments as described above. Further, embodiment5120G illustrates an optional bias control signal5114G that is coupled to the branches of the PA embodiment. Bias control signal5114G is optionally employed in embodiment5120G based on the specific implementation of the PA branches. In certain implementations, bias control will be required for proper operation of the PA. In other implementations, bias control is not required for proper operation of the PA, but may provide improved PA power efficiency.

FIG. 51Hillustrates a further exemplary embodiment5100H of the two-input single-output PA building block. Embodiment5100H includes two PA branches that can each be implemented according to single-input single-output or multiple-input single-output PA embodiments as described above. Embodiment5100H further includes optional elements, illustrated using dashed lines inFIG. 51H, that can be additionally employed in embodiments of embodiment5100H. In an embodiment, PA building block5100H may include a driver stage and/or pre-driver stage in each of the PA branches as shown inFIG. 51H. Process detectors may also be optionally employed to detect process and temperature variations in the driver and/or pre-driver stages of the PA. Further, optional bias control may be provided to each of the pre-driver, driver, and/or PA stages of each branch of the PA embodiment. Bias control may be provided to one or more the stages based on the specific implementation of that stage. Further, bias control may be required for certain implementations, while it can be optionally employed in others.

FIG. 51Iillustrates a further exemplary embodiment51001of a multiple-input single-output PA. Embodiment51001includes at least two PA branches that can each be implemented according to single-input single-output or multiple-input single-output PA embodiments as described above. Embodiment51001further includes optional elements that can be additionally employed in embodiments of embodiment51001. In an embodiment, the PA may include driver and/or pre-driver stages in each of the PA branches as shown inFIG. 51I. Process detectors may also be optionally employed to detect process and temperature variations in the driver and/or pre-driver stages of the PA. Further, optional bias control may be provided to each of the pre-driver, driver, and/or PA stages of each branch of the PA embodiment. Bias control may be provided to one or more the stages based on the specific implementation of that stage. Further, bias control may be required for certain implementations, while it can be optionally employed in others.

3.5.2) Output Stage Current Control—Autobias Module

Embodiments of the output stage and optional pre-driver and driver stage bias and current control techniques according to embodiments of the present invention are described below. In certain embodiments, output stage current control functions are employed to increase the output stage efficiency of a vector power amplifier (VPA) embodiment In other embodiments, output stage current control is used to provide output stage protection from excessive voltages and currents which is further describe in section 3.5.3. In embodiments, output stage current control functions are performed using the Autobias module described above with reference toFIG. 33. A description of the operation of the Autobias module in performing these current control functions is also presented below according to an embodiment of the present invention.

According to embodiments of the present invention, power efficiency of the output stage of a VPA can be increased by controlling the output stage current of the VPA as a function of the output power and the envelope of the output waveform.

FIG. 37, illustrates a partial schematic of a Multiple Input Single Output amplifier comprised of two NPN transistors with input signals S1and S2. When S1and S2are designed to be substantially similar waveforms and substantially constant envelope signals, any time varying complex-envelope output signal can be created at circuit node3750by changing the phase relationship of S1and S2.

FIG. 39illustrates an example time varying complex-envelope output signal3910and its corresponding envelope signal3920. Note than signal3910undergoes a reversal of phase at an instant of time t0. Correspondingly, envelope signal3920undergoes a zero crossing at time t0. Output signal3910exemplifies output signals according to typical wireless signaling schemes such as W-CDMA, QPSK, and OFDM, for example.

FIG. 40illustrates example diagram FIG.37's output stage current in response to output signal3910. Ioutsignal4010represents output stage current without autobias control, and Ioutsignal4020represents output stage current with autobias control. Without autobias control, as the phase shift between S1and S2changes from 0 to 180 degrees, the output current Ioutincreases. With autobias control, the output current Ioutdecreases and can be minimized when at or near to ofFIG. 39.

Note that Ioutsignal4020varies as a function of envelope signal3920. Accordingly, Ioutsignal4020is at the maximum when a maximum output power is required, but decreases as the required output power goes down. Particularly, Ioutsignal4020approaches zero as the associated output power goes to zero. Accordingly, a person skilled in the art will appreciate that output stage current control, according to embodiments of the present invention, results in significant power savings and increases the power efficiency of the power amplifier.

According to embodiments of the present invention, output stage current control may be implemented according to a variety of functions. In an embodiment, the output stage current can be shaped to correspond to the desired output power of the amplifier. In such an embodiment, the output stage current is a function that is derived from the envelope of the desired output signal, and the power efficiency will increase.

FIG. 41illustrates exemplary autobias output stage current control functions4110and4120according to embodiments of the present invention. Function4110may represent a function of output power and signal envelope as described above. On the other hand, function4120may represent a simple shaping function that goes to a minimum value for a pre-determined amount of time when the output power is below a threshold value. Accordingly, functions4110and4120represent two cases of autobias output stage current control functions with autobias control signal4110resulting in Ioutresponse4130and autobias control signal4120resulting in loUt response4140.

The invention, however, is not limited to those two exemplary embodiments. According to embodiments of the present invention, output stage autobias current control functions may be designed and implemented to accommodate the efficiency and current consumption requirements of a particular vector power amplifier design.

In implementation, several approaches exist for performing output stage current control. In some embodiments, output stage current shaping is performed using the Autobias module. The Autobias module is illustrated as autobias circuitry714and716in the embodiments ofFIGS. 7 and 8. Similarly, the Autobias module is illustrated as autobias circuitry1218in the embodiments ofFIGS. 12 and 13, and as autobias circuitry1718in the embodiments ofFIGS. 17 and 18.

Output stage current control using Autobias is depicted in process flowchart4800of the embodiment ofFIG. 48. The process begins in step4810, which includes receiving output power and output signal envelope information of a desired output signal of a vector power amplifier (VPA). In some embodiments, implementing output stage current control using Autobias requires a priori knowledge of the desired output power of the amplifier. Output power information may be in the form of envelope and phase information. For example, in the embodiments ofFIGS. 7,8,12,13,17, and18, output power information is included in I and Q data components received by the VPA embodiment. In other embodiments, output power information may be received or calculated using other means.

Step4820includes calculating a signal according to the output power and output envelope signal information. In embodiments, an Autobias signal is calculated as a function of some measure of the desired output power. For example, the Autobias signal may be calculated as a function of the envelope magnitude of the desired output signal. Referring to the embodiments ofFIGS. 7,8,12,13,17, and18, for example, it is noted that the Autobias signal (signals715and717inFIGS. 7 and 8, signal1228inFIGS. 12 and 13, and signals1728inFIGS. 17 and 18) is calculated according to received I and Q data components of a desired output signal. In certain embodiments, such as the ones described inFIGS. 7,8,12,13,17, and18, the Autobias signal is calculated by an Autobias module being provided output power information. In other embodiments, the Autobias signal may be calculated by the I and Q Data Transfer Function module(s) of the VPA. In such embodiments, an Autobias module may not be required in implementation. In embodiments, the I and Q Data Transfer Function module calculates a signal, outputs the signal to a DAC which output signal represents the Autobias signal.

Step4830includes applying the calculated signal at an output stage of the VPA, thereby controlling a current of the output stage according to the output power of the desired output signal. In embodiments, step4830includes coupling the Autobias signal at the PA stage input of the VPA. This is illustrated, for example, in the embodiments ofFIGS. 33 and 42where Autobias signal3310is coupled at the PA stage input of the VPA embodiment. In these embodiments, Autobias signal3310controls the bias of the PA stage transistors according to the output power of the desired output signal of the VPA embodiment. For example, Autobias signal3310may cause the PA stage transistors to operate in cutoff state when the desired output power is minimal or near zero, thereby drawing little or no output stage current. Similarly, when a maximum output power is desired, Autobias signal3310may bias the PA stage transistors to operate in class C, D, E, etc. switching mode. Autobias signal3310may also cause the PA stage transistors or FETs to operate in forward or reverse biased states according to the desired output power and signal envelope characteristics.

In other embodiments, step4830includes coupling the Autobias signal using pull-up impedances at the PA stage input and optionally the inputs of the driver and pre-driver stages of the VPA.FIGS. 38 and 43illustrate such embodiments. For example, in the embodiment ofFIG. 38, bias impedance3850couples Autobias Iref signal3840to input terminal3820of BJT element3870. BJT element3870represents the PA stage of one PA branch of an exemplary VPA embodiment. Similarly, in the embodiment ofFIG. 43, Autobias signal4310is coupled to transistors Q1, . . . , Q8through corresponding bias impedances Z1, . . . , Z8. Transistors Q1, . . . , Q8represent the PA stage of one branch of an exemplary VPA embodiment.

Embodiments for implementing the Autobias circuitry described above will now be provided.FIG. 27illustrates three embodiments2700A,2700B, and2700C for implementing the Autobias circuitry. These embodiments are provided for illustrative purposes, and are not limiting. Other embodiments will be apparent to persons skilled in the art(s) based on the teachings contained herein.

In embodiment2700A, Autobias circuitry2700A includes an Autobias Transfer Function module2712, a DAC2714, and an optional interpolation filter2718. Autobias circuitry2700A receives an I and Q Data signal2710. Autobias Transfer Function module2712processes the received I and Q Data signal2710to generate an appropriate bias signal2713. Autobias Transfer Function module2712outputs bias signal2713to DAC2714. DAC2714is controlled by a DAC clock2716which may be generated in Autobias transfer module2712. DAC2714converts bias signal2713into an analog signal, and outputs the analog signal to interpolation filter2718. Interpolation filter2718, which also serves as an anti-aliasing filter, shapes the DAC's output to generate Autobias signal2720, illustrated as Bias A in embodiment5112G. Autobias signal2720may be used to bias the PA stage and/or the driver stage, and/or the pre-driver stage of the amplifier. In an embodiment, Autobias signal2720may have several other Autobias signals derived therefrom to bias different stages within the PA stage. This can be done using additional circuitry not included in embodiment2700A.

In contrast, embodiment2700B illustrates an Autobias circuitry embodiment in which multiple Autobias signals are derived within the Autobias circuitry. As shown in embodiment2700B, circuit networks2722,2726, and2730, illustrated as circuit networks A, B, and C in embodiment2700B, are used to derive Autobias signals2724and2728from Autobias signal2720. Autobias signals2720,2724, and2728are used to bias different amplification stages.

Embodiment2700C illustrates another Autobias circuitry embodiment in which multiple Autobias signals are generated independently within the Autobias Transfer Function module2712. In embodiment2700C, Autobias Transfer Function module2712generates multiple bias signals according to the received I and Q Data signal2710. The bias signals may or may not be related. Autobias Transfer Function module2712outputs the generated bias signals to subsequent DACs2732,2734, and2736. DACs2732,2734, and2736are controlled by DAC clock signals2733,2735, and2737, respectively. DACs2732,2734, and2736convert the received bias signals into analog signals, and output the analog signals to optional interpolation filters2742,2744, and2746. Interpolation filters2742,2744, and2746, which also serve as anti-aliasing filters, shape the DACs outputs to generate Autobias signals2720,2724, and2728. Similar to embodiment2700B, Autobias signals2720,2724, and2728are used to bias different amplification stages such as the pre-driver, driver, and PA.

As noted above, Autobias circuitry embodiments according to the present invention are not limited to the ones described in embodiments2700A,2700B, and2700C. A person skilled in the art will appreciate, for example, that Autobias circuitry can be extended to generate any number of bias control signals as required to control the bias of various stages of amplification, and not just three as shown in embodiments5200B and5200C, for example.

3.5.3) Output Stage Protection

As described above, output stage embodiments according to embodiments of the present invention are highly power efficient as a result of being able to directly couple outputs at the PA stage using no combining or isolating elements. Certain output stage embodiments in certain circumstances and/or applications, however, may require additional special output stage protection measures in order to withstand such direct coupling approach. This may be the case for example for output stage embodiments such as5110D,5120D,5130D,5160D,5150E,5160E,5170E, and5180E illustrated inFIGS. 51D and 51E. Note that, generally, complementary output stage embodiments, such as embodiments5140D,5150D,5110E,5120E,5130E, and5140E ofFIGS. 51D and 51E, do not require (but may optionally use) the same output stage protection measures as will be described herein in this section. Output stage protection measures and embodiments to support such measures are now provided.

In one aspect, transistors of distinct branches of a PA stage should generally not simultaneously be in opposite states of operation for extended periods of time. Following a restart or power on with no inputs being supplied to the final PA stages, transients within the PA branches may cause this mode to occur resulting in the PA stage transistors potentially damaging one another or circuit elements connected to the output. Accordingly, embodiments of the present invention further constrain the Autobias module to limit the output current in the PA stage.

In another aspect, it may be desired to ensure that the Autobias module limits the output voltages below the breakdown voltage specification of the PA stage transistors. Accordingly, in embodiments of the present invention, such as the one illustrated inFIG. 42for example, a feedback element4210is coupled between the common collector node of the PA stage and the Autobias module. Feedback element4210monitors the collector to base voltage of the PA stage transistors, and may constrain the Autobias signal as necessary to protect the transistors and/or circuit elements.

A person skilled in the art will appreciate that other output stage protection techniques may also be implemented. Furthermore, output stage protection techniques may be implementation specific. For example, depending on the type of PA stage transistors (npn, pnp, NMOS, PMOS, npn/pnp, NMOS/PMOS), different protection functions may be required.

3.6) Harmonic Control

According to embodiments of the present invention, an underlying principle for each branch PA is to maximize the transfer of power to a fundamental harmonic of the output spectrum. Typically, each branch PA may be multi-stage giving rise to a harmonically rich output spectrum. In one aspect, transfer of real power is maximized for the fundamental harmonic. In another aspect, for non-fundamental harmonics, real power transfer is minimized while imaginary power transfer may be tolerated. Harmonic control, according to embodiments of the present invention, may be performed in a variety of ways.

In one embodiment, real power transfer onto the fundamental harmonic is maximized by means of wave-shaping of the PA stage input signals. In practice, several factors play a role in determining the optimal wave shape that results in a maximum real power transfer onto the fundamental harmonic. Embodiment3400of the present invention, described above, represents one embodiment that employs waveshaping of PA stage input signals. In embodiment3400, a plurality of harmonic control circuitry (HCC) networks3410-{1, . . . ,n} are coupled at the PA stage input of each PA branch {1, . . . ,n}. HCC networks3410-{1, . . . ,n} have the effect of waveshaping the PA stage inputs, and are typically selected so as to maximize real power transfer to the fundamental harmonic of the summed output spectrum.

According to embodiments of the present invention, waveshaping can be used to generate variations of harmonically diverse waveforms. In other embodiments, as can be apparent to a person skilled in the art, waveshaping can be performed at the pre-driver and/or the driver stage.

In another embodiment, harmonic control is achieved by means of waveshaping of the PA stage output.FIG. 43illustrates an exemplary PA stage embodiment4300of the present invention. In embodiment4300, Autobias signal4310is coupled to transistors Q1, . . . , Q8through corresponding bias impedances Z1, . . . , Z8. Notice that when impedances Z1, . . . , Z8have different values, transistors Q1, . . . , Q8have different bias points and can be turned on at different times. This approach of biasing transistors Q1, . . . , Q8is referred to as staggered bias. Note that using staggered bias, the PA output waveform can be shaped in a variety of ways depending on the values assigned to bias impedances Z1, . . . , Z8.

Harmonic control using staggered bias is depicted in process flowchart4900of the embodiment ofFIG. 49. The process begins in step4910, which includes coupling an input signal at first ports of a plurality of transistors of a power amplifier (PA) switching stage. In the example embodiment ofFIG. 43, for example, step4910corresponds to coupling PA_IN signal4310at base terminals of the plurality of transistors Q1, . . . , Q8.

Step4920includes coupling a plurality of impedances between the first ports of the plurality of transistors and a bias signal. In the example embodiment ofFIG. 43, for example, step4920is achieved by coupling impedances Z1, . . . , Z8between base terminals of respective transistors Q1, . . . , Q8and Iref signal. In an embodiment, values of the plurality of impedances are selected to cause a time-staggered switching of the input signal, thereby harmonically shaping an output signal of the PA stage. In embodiments, a multi-stage staggered output may be generated by selecting multiple distinct values of the plurality of impedances. In other embodiments, switching is achieved by selecting the plurality of impedances to have equal or substantially equal value.

FIG. 44illustrates an exemplary wave-shaped PA output using a two-stage staggered bias approach. In a two-stage staggered bias approach, a first set of the PA transistors is first turned on before a second set is turned on. In other words, the bias impedances take two different values. Waveform4410represents an input waveform into the PA stage. Waveform4420represents the wave-shaped PA output according to a two-stage staggered bias. Notice that output waveform4420slopes twice as it transitions from 1 to 0, which corresponds to the first and second sets of transistors turning on successively.

According to embodiments of the present invention, a variety of multi-stage staggered bias approaches may be designed. Bias impedance values may be fixed or variable. Furthermore, bias impedance values may be equal or substantially equal, distinct, or set according to a variety of permutations. For example, referring to the example ofFIG. 43, one exemplary permutation might set Z1=Z2=Z3=Z4and Z5=Z6=Z7=Z8resulting in a two-stage staggered bias.

3.7) Power Control

Vector power amplification embodiments of the present invention intrinsically provide a mechanism for performing output power control.

FIG. 45illustrates one approach for performing power control according to an embodiment of the present invention. InFIG. 45, phasors {right arrow over (U1)} and {right arrow over (I1)} represent upper and lower constituents of a first phasor {right arrow over (R1)}. {right arrow over (U1)} and {right arrow over (L1)} are constant magnitude and are symmetrically shifted in phase relative to {right arrow over (R1)} by a phase shift angle

ϕ2.
Phasors {right arrow over (U2)} and {right arrow over (L2)} represent upper and lower constituents of a second phasor {right arrow over (R2)}. {right arrow over (U2)} and {right arrow over (L2)} are constant magnitude and are symmetrically shifted in phase relative to {right arrow over (R2)} by a phase shift angle

It is noted, fromFIG. 45, that {right arrow over (R1)} and {right arrow over (R2)} are in-phase relative to each other but only differ in magnitude. Furthermore, {right arrow over (U2)} and {right arrow over (L2)} are equally or substantially equally phased shifted relative to {right arrow over (U1)} and {right arrow over (L1)}, respectively. Accordingly, it can be inferred that, according to the present invention, a signal's magnitude can be manipulated without varying its phase shift angle by equally or substantially equally shifting symmetrically its constituent signals.

According to the above observation, output power control can be performed by imposing constraints on the phase shift angle of the constituent signals of a desired output signal. Referring toFIG. 45, for example, by constraining the range of values that phase shift angle

ϕ2
can take, magnitude constraints can be imposed on phasor {right arrow over (R1)}.

According to embodiments of the present invention, a maximum output power level can be achieved by imposing a minimum phase shift angle condition. For example, referring toFIG. 45, by setting a condition such that

ϕ2⁢>_⁢ϕff,
the magnitude of phasor {right arrow over (R1)} is constrained not to exceed a certain maximum level. Similarly, a maximum phase shift angle condition imposes a minimum magnitude level requirement.

In another aspect of power control, output power resolution is defined in terms of a minimum power increment or decrement step size. According to an embodiment of the present invention, output power resolution may be implemented by defining a minimum phase shift angle step size. Accordingly, phase shift angle values are set according to a discrete value range having a pre-determined step size.FIG. 46illustrates an exemplary phase shift angle spectrum, whereby phase shift angle

ϕ2
is set according to a pre-determined value range having a minimum step φstep.

A person skilled in the art will appreciate that a variety of power control schemes may be implemented in a fashion similar to the techniques described above. In other words, various power control algorithms can be designed, according to the present invention, by setting corresponding constraints on phase shift angle values. It is also apparent, based on the description above of data transfer functions, that power control schemes can be naturally incorporated into a transfer function implementation.

3.8) Exemplary Vector Power Amplifier Embodiment

FIG. 47illustrates an exemplary embodiment4700of a vector power amplifier according to the present invention. Embodiment4700is implemented according to the Direct Cartesian 2-Branch VPA method.

Referring toFIG. 47, signals4710and4712represent incoming signals from a transfer function stage. The transfer function stage is not shown inFIG. 47. Block4720represents a quadrature generator which may be optionally implemented according to an embodiment of the present invention. Quadrature generator4720generates clock signals4730and4732to be used by vector modulators4740and4742, respectively. Similarly, signals4710and4712are input into vector modulators4740and4742. As described above, vector modulators4740and4742generate constant envelope constituents that are, subsequently, processed by a PA stage. In embodiment4700, the PA stage is multi-stage, whereby each PA branch includes a pre-driver stage4750-4752, a driver stage4760-4762, and a power amplifier stage4770-4772.

Further illustrated inFIG. 47are Autobias signals4774and4776, and terminals4780and4782for coupling harmonic control circuitry and networks. Terminal node4780represents the output terminal of the vector power amplifier, and is obtained by direct coupling of the two PA branches' outputs.

4. ADDITIONAL EXEMPLARY EMBODIMENTS AND IMPLEMENTATIONS

Exemplary VPA implementations according to embodiments of the present invention will be provided in this section. Advantages of these VPA implementations will be appreciated by persons skilled in the art based on the teachings herein. We briefly describe below some of these advantages before presenting in more detail the exemplary VPA implementations.

4.1.1) Control of Output Power and Power Efficiency

The exemplary VPA implementations enable several layers of functionality for performing power control and/or for controlling power efficiency using circuitry within the VPA.FIG. 52illustrates this functionality at a high level using a MISO VPA embodiment5200. MISO VPA embodiment5200is a 2 input single output VPA with optional driver and pre-driver stages in each branch of the VPA. As in previously described embodiments, the input bias voltage or current to each amplification stage (e.g., pre-driver stage, driver stage, etc.) of the VPA is controlled using a bias signal (also referred to as Autobias in other embodiments). In embodiment5200, separate bias signals Bias C, Bias B, and Bias A are coupled to the pre-driver, driver, and PA stages, respectively, of the VPA. Additionally, VPA embodiment5200includes power supply signals (Pre-Driver VSUPPLY, Driver VSUPPLY, and Output Stage VSUPPLY) that are used to power respective stages of the VPA. In embodiments, these power supply signals are generated using voltage controlled power supplies and can be further used to bias their respective amplifications stages, thereby providing additional functionality for controlling the overall power efficiency of the VPA and for performing power control, as well as other functions of the VPA. For example, when controlled independently, the power supply signals and bias signals can be used to operate different amplification stages of the VPA at different power supply voltages and bias points, enabling a wide output power dynamic range for the VPA. In embodiments the voltage controlled power supplies can be implemented as continuously variable supplies such as voltage controlled switching supplies which provide variable voltage supplies to the appropriate amplification stage. In other embodiments the voltage controlled power supply can be implemented by using switches to provide different power supply voltages. For example, a VPA output stage and/or optional driver stages and/or optional pre-driver stages power supply could be switched between 3.3V, 1.8V, and 0V depending on the desired operating parameters.

The exemplary VPA implementations provide different approaches for monitoring and/or compensating for errors in the VPA. These errors may be due, among other factors, to process and/or temperature variations in the VPA, phase and amplitude errors in the vector modulation circuitry, gain and phase imbalances in branches of the VPA, and distortion in the MISO amplifier (see, for example, Section 3.4.5 above). In previously described VPA embodiments, part of this functionality was embodied in the process detector circuitry (e.g., process detector792inFIG. 7A, process detector1282inFIG. 12, process detector1772inFIG. 17). These approaches can be classified as feedforward, feedback, and hybrid feedforward/feedback techniques, and can be implemented in a variety of ways as will be further discussed in the following sections that describe the exemplary VPA implementations. A conceptual description of these error monitoring and compensation approaches will be now provided.

FIGS. 54A and 54Bare block diagrams that illustrate at a high level feedforward techniques for compensating for errors in a VPA. Feedforward techniques rely on a priori knowledge of expected errors in the VPA in order to pre-compensate for these errors within the VPA. Thus, feedforward techniques include an error measurement phase (typically performed in a test and characterization process) and a pre-compensation phase using the error measurements.

FIG. 54Aillustrates a process5400A for generating an error table or function that describes expected errors in I data and Q data at the output of the VPA (error measurement phase). Such errors are typically due to imperfections in the VPA. Process5400A is typically performed in a testing lab prior to finalizing the VPA design, and includes measuring at the output of a receiver I and Q values that correspond to a range of I and Q values at the input of the VPA. Typically, the input I and Q values are selected to generate a representative range of the 360° degrees polar space (for example, the I and Q values may be selected at a uniform spacing of 30° degrees). Subsequently, error differences between the input I and Q values and the output I and Q values are calculated. For example, after measuring I and Q at the output of the receiver for a particular set of I and Q input values, a compare circuitry calculates as Ierrorand Qerrorthe differences in I data and Q data between the input I and Q values and the receiver output I and Q values. Ierrorand Qerrorrepresent the expected errors in I and Q at the output of the VPA for the particular set of I and Q input values.

In an embodiment, the receiver is integrated with the VPA, or is provided by an external calibration and/or testing device. Alternatively, the receiver is the receiver module in the device employing the VPA (e.g., the receiver in a cellular phone). In this alternative embodiment, the VPA error table and/or feedback information can be generated by this receiver module in the device.

The calculated Ierrorand Qerrorvalues are used to generate an error table or function representative of expected I and Q errors for various I and Q input values. In embodiments, the calculated Ierrorand Qerrorvalues are further interpolated to generate error values for an augmented range of I and Q input values, based on which the error table or function is generated.

FIG. 54Billustrates feedforward error pre-compensation (pre-compensation phase) according to an embodiment of the present invention. As illustrated, I and Q input values are corrected for any expected Ierrorand Qerrorvalues as determined by an error table or function, prior to amplification by the VPA. I and Q error pre-compensation may be performed at different stages and/or at different temperatures and/or at different operating parameters within the VPA. In the embodiment ofFIG. 54B, error correction occurs prior to the amplification stage of the VPA. For example, I and Q error correction may be performed by the transfer function module of the VPA, such as transfer function modules1216and1726ofFIGS. 12 and 17, for example. Several methods exist for implementing I and Q error correction in the transfer function module of the VPA including using look up tables and/or digital logic to implement an error function. Typically, feedforward techniques require data storage such as RAM or NVRAM, for example, to store data generated in the measurement phase.

In contrast to feedforward techniques, feedback techniques do not pre-compensate for errors but perform real-time measurements inside or at the output of the VPA to detect any errors or deviations due to process or temperature variations, for example.FIG. 55is a block diagram that conceptually illustrates an exemplary Cartesian feedback error correction technique according to embodiments of the present invention. As will be further described below,FIG. 55illustrates a receiver-based feedback technique, in which the output of the VPA is received by a receiver, before being fed back to the VPA. Other feedback techniques according to embodiments of the present invention will be further described below. Feedback techniques may require additional circuitry to perform these real-time measurements, which may be made at different stages within the VPA, but require minimal or no data storage. Several implementations exist for feedback error correction as will be further described in the description of the exemplary VPA implementations below.

Hybrid feedforward/feedback techniques include both feedforward and feedback error pre-compensation and/or correction components. For example, a hybrid feedforward/feedback technique may pre-compensate for errors but may also use low rate periodical feedback mechanisms to supplement feedforward pre-compensation.

The exemplary VPA implementations provide several VPA architectures for concurrently supporting multiple frequency bands (e.g., quad band) and/or multiple technology modes (e.g., tri mode) for data transmission. Advantages of these VPA architectures will be appreciated by a person skilled in the art based on the teachings to be provided herein. In embodiments, the VPA architectures allow for using a single PA branch for supporting both TDD (Time Division Duplex) and FDD (Frequency Division Duplex) based standards. In other embodiments, the VPA architectures allow for the elimination of costly and power inefficient components at the output stage (e.g., isolators), typically required for FDD based standards. For the purpose of illustration and not limitation, frequency band allocation on lower and upper spectrum bands for various communication standards is provided inFIG. 53. Note that the DCS1800(Digital Cellular System1800) and the PCS1900(Personal Communications Service1900) bands can support different GSM-based implementations, also known as GSM-1800and GSM-1900. The 3G TDD bands are allocated for third generation time division duplex standards such as UMTS TDD (Universal Mobile Telephone System) and TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), for example. The 3G FDD bands are allocated for third generation frequency division duplex standards such as WCDMA (Wideband CDMA), for example.

As will be appreciated by persons skilled in the art based on the teachings herein, advantages enabled by the exemplary VPA implementations exist in various aspects in addition to those described above. In the following, a more detailed description of the exemplary VPA implementations will be provided. This includes a description of different implementations of the digital control circuitry of the VPA followed by a description of different implementations of the analog core of the VPA. Embodiments of the present invention are not limited to the specific implementations described herein. As will be understood by persons skilled in the art based on the teachings herein, several other VPA implementations may be obtained by combining features provided in the exemplary VPA implementations. Accordingly, the exemplary VPA implementations described below do not represent an exhaustive listing of VPA implementations according to embodiments of the present invention, and other implementations based on teachings contained herein are also within the scope of the present invention. For example, certain digital control circuitry could be integrated or combined with a baseband processor. In addition, certain analog control circuitry such as quadrature generators and vector modulators can be implemented using digital control circuitry. In an embodiment, the VPA system can be implemented in its entirety using digital circuitry and can be integrated completely with a baseband processor.

4.2) Digital Control Module

The digital control module of the VPA includes digital circuitry that is used, among other functions, for signal generation, performance monitoring, and VPA operation control. In Section 3, the signal generation functions of the digital control module (i.e., generating constant envelope signals) were described in detail with reference to the transfer function module (state machine) of the digital control module, in embodiments700,1200, and1700, for example. The performance monitoring functions of the digital control module include functions for monitoring and correcting for errors in the operation of the VPA and/or functions for controlling the bias of different stages of the VPA. The VPA operation control functions of the digital control module include a variety of control functions related to the operation of the VPA (e.g., powering up or programming VPA modules). In certain embodiments, these control functions may be optional. In other embodiments, these control functions are accessible through the digital control module to external processors connected to the VPA. In other embodiments, these functions are integrated with baseband processors or other digital circuitry. Other functions are also performed by the digital control module in addition to those described above. Digital control module functions and implementations will now be provided in further detail.

FIG. 56is a high level illustration of a digital control module embodiment5600according to an embodiment of the present invention. Digital control module embodiment5600includes an input interface5602, an output interface5604, a state machine5606, a RAM (Random Access Memory)5608, and a NVRAM (Non-Volatile RAM)5610. In embodiments, Ram5608, and/or NVRAM5610may be optional.

Input interface5602provides a plurality of buses and/or ports for inputting signals into digital control module5600. These buses and/or ports include, for example, buses and/or ports for inputting I and Q data signals, control signals provided by an external processor, and/or clock signals. In an embodiment, input interface5602includes an I/O bus. In another embodiment, input interface5602includes a data bus for receiving feedback signals from the analog core of the VPA. In another embodiment, input interface5602includes ports for reading values out of digital control module5600. In an embodiment, values are read out of digital control module5600by an external processor (e.g., a baseband processor) connected to digital control module5600.

Output interface5604provides a plurality of output buses and/or ports for outputting signals from digital control module5600. These output buses and/or ports include, for example, buses and/or ports for outputting amplitude information signals (used to generate constant envelope signals), bias control signals (Autobias signals), voltage control signals (power supply signals), and output select signals.

State machine5606performs various functions related to the signal generation and/or performance monitoring functions of digital control module5600. In an embodiment, state machine5606includes a transfer function module, as described in Section 3, for performing signal generation functions. In another embodiment, state machine5606includes modules for generating, among other types of signals, bias control signals, power control signals, gain control signals, and phase control signals. In another embodiment, state machine5606includes modules for performing error pre-compensation in a feedforward error correction system.

RAM5608and/or NVRAM5610are optional components of digital control module5600. In embodiments, RAM5608and NVRAM5610reside externally of digital control module5600and may be accessible to digital control module5600through data buses connected to digital control module5600via input interface5602, for example. RAM5608and/or NVRAM5610may or may not be needed depending on the specific VPA implementation. For example, a VPA implementation employing feedforward techniques for error pre-compensation may require RAM5608or NVRAM5610to store error tables or functions. On the other hand, a feedback technique for error correction may solely rely on digital logic modules in the state machine and may not require RAM5608or NVRAM5610storage. Similarly, the amount of RAM5608and NVRAM5610storage may depend on the specific VPA implementation. Typically, when used, NVRAM5610is used for storing data that is not generated in real time and/or that must be retained when power is turned off. This includes, for example, error tables and/or error values such as scalar values and angular values generated in the testing and characterization phase of the VPA system and/or look up tables used by transfer functions modules.

FIG. 57illustrates an exemplary digital control module implementation5700according to an embodiment of the present invention. Digital control module implementation5700illustrates in particular an exemplary input interface5602and an exemplary output interface5604of an exemplary VPA digital control module5700. As will be further described below, signals of the input and output interfaces5602and5604of VPA digital control module5700correlate directly with signals from the analog core of the VPA and/or signals to/from one or more external processors/controllers connected to the VPA. In the example embodiments described in the sections above, the analog core of the VPA was represented by analog circuitry186together with PA stage190-{1, . . . ,n} inFIG. 1E, for example. It is noted that bit widths of data buses and/or signals of the input and output interfaces inFIG. 57are provided for the purpose of illustration only and are not limiting.

The input interface5602of exemplary digital control module5700includes an A/D IN bus5702, a digital I/O bus5704, and a plurality of control signals5706-5730. In other digital control module implementations, the input interface5602may include more or less data buses, programming buses, and/or control signals.

A/D IN bus5702carries feedback information from the analog core of the VPA to the digital control module5700. Feedback information can be used, among other functions, to monitor the output power of the VPA and/or for amplitude and/or phase variations in branches of the VPA. As illustrated inFIG. 57, an A/D converter5732converts from analog to digital feedback information received from the analog core of the VPA (using A/D IN signal5736) before sending it on A/D IN bus5702to the digital control module5700. In an embodiment, the digital control module5700controls a clock signal A/D CLK5734of the A/D converter5732. In another embodiment, the digital control module5700controls an input selector to the A/D converter5732to select between multiple feedback signals at the input of the A/D converter5732. In an embodiment, this is performed using A/D Input Selector signals5738-5746.

Digital110bus5704carries data and control signals into and out of the digital control module5700from and to one or more processors or controllers that may be connected to the VPA. In an embodiment, some of control signals5706-5730are used to inform the digital control module5700of the type of information to expect on (or that is present on) digital I/O bus5704. For example, PC/(I/Q)n signal5724indicates to the digital control module5700whether power control information or I/Q data is being sent over digital I/Q bus5704. Similarly, I/Qn signal5720indicates to the digital control module5700whether I or Q data is being sent over digital I/O bus5704.

Digital Enable/Disablen signal5706controls the power-up, reset, and shut down of the VPA. Signals to power-up, reset, or shut down the VPA typically come from a processor connected to the VPA. For example, when used in a cellular phone, a baseband processor or controller of the cellular phone may shut down the VPA in receive mode and enable it in transmit mode.

PRGM/RUNn signal5708indicates to the digital control module5700whether it is in programming or in run mode. In programming mode, the digital control module5700can be programmed to enable the desired operation of the VPA. For example, memory (RAM5608, NVRAM5610) bits of the digital control module5700can be programmed to indicate the standard to be used (e.g., WCDMA, EDGE, GSM, etc.) for communication. Programming of digital control module5700is done using digital I/O bus5704.

In an embodiment, the VPA is programmed and/or re-programmed (partially or completely) after it is installed in (or integrated with) the final product or device employing the VPA. For example, when used in a cellular phone, the VPA can be programmed after the cellular phone is manufactured to provide the cellular phone with new, additional, modified or different features, such as features related to (1) supported waveforms, (2) power control, (3) enhanced efficiency, and/or (4) power-up and power-down profiles. The VPA can also be programmed to remove waveforms or other features as desired by the network provider.

Programming of the VPA may be payment based. For example, the VPA may be programmed to include features and enhancements selected and purchased by the end-user.

In an embodiment, the VPA is programmed after the device is manufactured using any well known method or technique, including but not limited to: (1) programming the VPA using the programming interface of the device employing the VPA; (2) programming the VPA by storing programming data on a memory card readable by the device (a SIM card, for example, in the case of a cellular phone); and/or (3) programming the VPA by transferring programming data to the VPA wirelessly by the network provider or other source.

READ/WRITEn signal5710indicates to the digital control module5700whether data is to be read from or written to the digital control module storage (RAM5608or NVRAM5610) via digital I/O bus5704. When data is being read out of the digital control module5700, CLK OUT signal5712indicates timing information for reading from digital I/O bus5704.

CLK_IN signal5718provides a reference clock signal to the digital control module5700. Typically, the reference clock signal is selected according to the communication standards supported by the VPA. For example, in a dual-mode WCDMA/GSM system, it is desirable that the reference clock signal be a multiple of the WCDMA chip rate (3.84 MHz) and the GSM channel raster (200 KHz), with 19.2 MHz being a popular rate as the least common multiple of both. Further, CLK_IN signal5718can be made a multiple of the reference clock signal. In an embodiment, CLK_IN×2 Enable/Disablen5714, CLK_IN×4 Enable/Disablen5716can be used to indicate to the VPA digital control module5700that a multiple of the reference clock is being provided.

TX/RXn signal5726indicates to the digital control module5700when the system (e.g., cellular phone) employing the VPA is going into transmit or receive mode. In an embodiment, the digital control module5700is notified a short amount of time prior to the system going into transmit mode in order for it to power up the VPA. In another embodiment, the digital control module5700is notified when the system is going into receive mode in order for it to enter a

SYNTH PRGM/SYNTH RUNn signal5728is used to program the synthesizer that provides the reference frequency to the VPA (such as synthesizers5918and5920shown inFIGS. 59A-D). When SYNTH PRGM5728is high, the VPA digital control module5700can expect to receive data for programming the synthesizer on digital I/O bus5704. Typically, programming of the synthesizer is needed when selecting the VPA transmission frequency. When SYNTH RUN5728goes high, the synthesizer is instructed to run. The synthesizer may be integrated with the VPA system or provided as an external component or subsystem.

OUTPUT SEL/LATCHn signal5730is used to select the VPA output to be used for transmission. This may or may not be needed depending on the number of outputs of the VPA. When OUTPUT SEL5730goes high, the digital control module5700expects to receive data for selecting the output on digital I/O bus5704. When LATCH5730goes high, the digital control module5700ensures that the VPA output used for transmission is held (cannot be changed) for the duration of the current transmit sequence.

The output interface5604of exemplary digital control module5700includes a plurality of data buses (5748,5750,5752,5754,5756,5758,5760,5762,5764, and5766), a programming bus5799, and a plurality of control signals (5768,5770,5772,5744,5776,5778,5780,5782,5784,5786,5788,5790,5792,5794,5796, and5798). In other embodiments of digital control module5700, the output interface5604may have more or less data buses, programming buses, and/or control signals.

Data buses5752,5754,5756, and5758carry digital information from the digital control module5700that is used to generate the substantially constant envelope signals in the analog core of the VPA. Note that exemplary digital control module5700may be used in a 4-Branch VPA embodiment (see Section 3.1) or a 2-Branch VPA embodiment (see Section 3.3). For example, digital information carried by data buses5752,5754,5756, and5758correspond to signals722,724,726, and728in the embodiment ofFIG. 7Aor signals1720,1722,1724, and1726in the embodiment ofFIG. 17, and may be generated by the digital control module5700according to equations (5) (for a 4-Branch VPA embodiment) and (18) (for a 2-Branch VPA embodiment). Digital information carried by data buses5752,5754,5756, and5758is converted from digital to analog using respective Digital-to-Analog Converters (DACs01-04) to generate analog signals5753,5755,5757, and5759, respectively. Analog signals5753,5755,5757, and5759are input into vector modulators in the analog core of the VPA as will be further described below with reference to the VPA analog core implementations. In an embodiment, DACs01-04are controlled and synchronized by a Vector MOD DAC CLK signal5770provided by the digital control module. Further, DACs01-04are provided the same central reference voltage VREF_D signal5743.

Data buses5760and5762carry digital information from the digital control module5700that is used to generate bias voltage signals for the PA amplification stage and the driver amplification stage of the VPA (seeFIG. 52for illustration of different amplification stages of the VPA). In another embodiments additional control functions such as pre-driver Stage Bias Control is used. Digital information carried by data bus5760is converted from digital to analog using DAC_05to generate output stage bias signal5761. Similarly, digital information carried by data bus5762is converted from digital to analog using DAC_06to generate driver stage bias signal5763. Output stage bias signal5761and driver stage bias signal5763correspond, for example, to bias signals A and B illustrated in embodiment5100H. In an embodiment, DACs05and06are controlled and synchronized using an Autobias DAC CLK signal5772, and are provided the same central reference voltage VREF_E signal5745.

Data buses5764and5766carry digital information from the digital control module5700that is used to generate voltage control signals for the output stage and the driver stage of the VPA. Digital information carried by data bus5764is converted from digital to analog using DAC-07to generate output stage voltage control signal5765. Similarly, digital information carried by data bus5766is converted from digital to analog using DAC-08to generate driver stage voltage control signal5767. Output stage voltage control signal5765and driver stage voltage control5767are used to generate supply voltages for the output stage and the driver stage, providing a further method for controlling the voltage of the output stage and driver stage of the VPA. In an embodiment, DACs07and08are controlled and synchronized using a Voltage Control DAC CLK signal5774, and are provided the same central reference voltage VREF_F signal5747.

Data buses5748and5750carry digital information from the digital control module5700that is used to generate gain and phase balance control signals. In an embodiment, the gain and phase balance control signals are generated in response to feedback gain and phase information received from the analog core of the VPA on A/D IN bus5702. Digital information carried by data bus5748is converted from digital to analog using DAC_09to generate analog gain balance control signal5749. Similarly, digital information carried by data bus5750is converted from digital to analog using DAC_10to generate analog phase balance control5751. Gain and phase balance control signals5749and5751provide one mechanism for regulating gain and phase in the analog core of the VPA. In an embodiment, DACs09and10are controlled and synchronized using a Balance DAC CLK signal5768, and are provided the same central reference voltage VREF_B5739.

Programming bus5799carries digital instructions from the digital control module5700that are used to program frequency synthesizer or synthesizers in the analog core of the VPA. In an embodiment, digital instructions carried by programming bus5799are generated according to data received on digital I/O bus5704, when SYNTH PRGM signal5728is high. Digital instructions for programming the frequency synthesizers include instructions for setting the appropriate synthesizer (HI Band or Low Band) to generate a frequency according to the selected communication standard. In an embodiment, programming bus5799is a 3-wire programming bus.

In addition to the data and programming buses described above, the output interface5604includes a plurality of control signals.

In conjunction with programming bus5799, used for programming the frequency synthesizers of the analog VPA core, HI Band Enable/Disablen and Low Band Enable/Disablen control signals5796and5798are generated to control which of a high band frequency synthesizer and a low band frequency synthesizer of the analog VPA core is enabled/disabled.

Control signals5738,5740,5742,5744, and5746control an input selector for multiplexing feedback signals from the analog core of the VPA onto A/D IN input signal5736of A/D converter5732. In an embodiment, control signals5738,5740,5744, and5746control the multiplexing of a power output feedback signal, a differential branch amplitude feedback signal, and a differential branch phase feedback signal on A/D IN signal5736. Other feedback signals may be available in other embodiments. In an embodiment, the feedback signals are multiplexed according to a pre-determined multiplexing cycle. In another embodiment, certain feedback signals are periodically carried by A/D IN signal5736, while others are requested on-demand by the digital control module.

Output select control signals5776,5778,5780,5782, and5784are generated by the digital control module5700in order to select a VPA output, when the particular VPA implementation supports a plurality of outputs for different frequency bands and/or technology modes. In an embodiment, output select control signals5776,5778,5780,5782, and5782are generated according to digital control module input signal5730. In the example implementation ofFIG. 57, the digital control module5700provides five output select control signals for selecting one of five different VPA outputs. In an embodiment, output select control signals5776,5778,5780,5782, and5784control circuitry within the analog core of the VPA in order to power up circuitry corresponding to the selected VPA output and to power off circuitry corresponding to the remaining unselected VPA outputs. In embodiments, at any time, output select control signals5776,5778,5780,5782, and5784ensure that circuitry corresponding to a single VPA output are powered up, when the VPA is in transmit mode. A different digital control module embodiment may have more or less output select control signals depending on the particular number of VPA outputs supported by the particular analog core implementation.

Vector MOD HI Band(s)/Vector MOD Low Band(s)n control signal5786is generated by the digital control module5700to indicate whether a high band frequency modulation set or a low band frequency modulation set of vector modulators is to be used in the analog core of the VPA. In an embodiment, the high band and the low band vector modulators have different characteristics, allowing each set to be more suitable for a range of modulation frequencies. Control signal5786is generated according to the selected output of the VPA. In an embodiment, control signal5786controls circuitry within the analog core of the VPA in order to ensure that the selected set of vector modulators is powered up and that the other set(s) of vector modulators are powered off. In another embodiment, control signal5786controls circuitry within the analog core of the VPA in order to couple a set of interpolation filters to the selected set of vector modulators.

3G HI Band/Normaln control signal5788is an optional control signal which may be used, if necessary, to enable the VPA to support the wide range High frequency band. In an embodiment, control signal5788may force more current through the output stage circuitry of the analog core and/or modify the output impedance characteristics of the VPA.

Filter Response 1/Filter Response 2n control signal5790is an optional control signal which may be used to dynamically change the response of interpolation filters in the analog core of the VPA. This may be needed as the interpolation filters have different optimal responses for different communication standards. For example, the optimal filter response has a 3 dB corner frequency around 5 MHz for WCDMA or EDGE, while this frequency is around 400 KHz for GSM. Accordingly, control signal5790allows for optimizing the interpolation filters according to the used communication standard.

Attenuator control signals5792and5794are optional control signals which may be used, if necessary, to provide additional output power control features and functions. For example, attenuator control signals5792and5794could be configured to enable/disable RF attenuators on the output of the VPA. These attenuators may be required based on the specific VPA implementation, which could be fabricated using Silicon, GaAs, or CMOS processes.

FIG. 58illustrates another exemplary digital control module5800according to an embodiment of the present invention. Exemplary digital control module5800is similar in many respects to digital control module5700. In particular, both embodiments5700,5800have the same input interface5602, and substantial portions of the output interface (the output interface inFIG. 58is labeled with reference number5604′). The differences between exemplary embodiments5700and5800relate to the type of feedback information being provided to the digital control module. Specifically, the two embodiments5700and5800are designed to operate with distinctly different feedback mechanisms for error correction. These mechanisms will be further described below in Section 4.3 with reference to the exemplary analog core implementations.

Exemplary implementation5800includes different input select control signals5808,5810, and5812compared to exemplary implementation5700. Input select control signals5810and5812control whether feedback information is to be received from the high band or the low band analog circuitry of the VPA, depending on which band is in use. Input select control signal I/Qn5808controls the multiplexing of I and Q feedback data from the analog core of the VPA. In an embodiment, control signal5812allows sequential switching between I data and Q data on A/D IN signal5736.

In further distinction to exemplary embodiment5700, exemplary embodiment5800include an additional data bus5802, which carries digital information from the digital control module5800used to generate an automatic gain control signal5806. Automatic gain control signal5806is used to control the gain of an amplifier circuit used in the feedback mechanism in the analog core of the VPA. Further description of this component of the feedback mechanism will be provided below. In an embodiment, digital information carried by data bus5802is converted from digital to analog by DAC_11to generate analog signal5806. DAC_11is controlled by a clock signal5804provided by the digital control module, and is provided VREF_B signal5739as a central reference voltage.

It is noted that exemplary digital control modules5700and5800illustrate some of the typical input and output digital control module signals that may be used in a digital control module implementation. More or less input and output signals may also be used, as will be appreciated by a person skilled in the art based on the teachings herein, depending on the system in which the VPA is being used and/or the specific VPA analog core to be used with the digital control module. In an embodiment, exemplary digital control module implementations5700and5800may be used in conjunction with a VPA analog core using feedback only, feedforward only, or both feedback and feedforward error correction. When used in a feedforward only approach, feedback elements and/or signals (e.g., A/D IN5702, control signals5738,5740,5742,5744,5746, gain and phase balance control signals5749and5751) may be disabled or eliminated. Accordingly, variations of exemplary digital control module implementations5700and5800are within the scope of embodiments of the present invention.

In this section, various exemplary implementations of the VPA analog core will be provided. As will be described below, the various exemplary implementations share a large number of components, circuits, and/or signals, with the main differences relating to the output stage architecture, the adopted error correction feedback mechanism, and/or the actual semiconductor material used in chip fabrication. As will be understood by a person skilled in the art based on the teachings herein, other VPA analog core implementations are also conceivable by interchanging, adding, and/or removing features among the various exemplary implementations described below. Accordingly, embodiments of the present invention are not to be limited to the exemplary implementations described herein.

4.3.1) VPA Analog Core Implementation A

FIGS. 59A-Dillustrates a VPA analog core implementation5900according to an embodiment of the present invention. In an embodiment, the input signals of analog core5900connect directly or indirectly (through DACs) to output signals from the output interface5604of digital control module5600. Similarly, feedback signals from analog core5900connect directly or indirectly (through DACs) to the input interface of the digital control module5600. For illustrative purposes, the analog core5900is shown inFIGS. 59A-Das being connected to digital control module5700, as indicated by the same numeral signals on bothFIG. 57andFIGS. 59A-D.

Analog core implementation5900is a 2-Branch VPA embodiment. This implementation5900, however, can be readily modified to a 4-Branch or a CPCP VPA embodiment, as will be apparent to persons skilled in the art based on the teachings herein.

At a high level, analog core5900includes an input stage for receiving data signals from the digital control module5700, a vector modulation stage for generating substantially constant envelope signals, and an amplification output stage for amplifying and outputting the desired VPA output signal. Additionally, analog core5900includes power supply circuitry for controlling and delivering power to the different stages of the analog core, optional output stage protection circuitry, and optional circuitry for generating and providing feedback information to the digital control module of the VPA.

The input stage of VPA analog core5900includes an optional interpolation filter bank (5910,5912,5914, and5916) and a plurality of switches5964,5966,5968, and5970. Interpolation filters5910,5912,5914, and5916, which may also serve as anti-aliasing filters, shape the analog outputs5753,5755,5757, and5759of DACs01-04to generate the desired output waveform. In an embodiment, the response of interpolation filters5910,5912,5914, and5916is dynamically changed using control signal5790from the digital control module5700. Digital control module signal5790may, for example, control switches within interpolation filters5910,5912,5914, and5916to cause a change in active circuitry (enable/disable RC circuitry) within filters5910,5912,5914, and5916. This may be needed as interpolation filters5910,5912,5914, and5916have different optimal responses for different communication standards. It should be noted that interpolation filters5910,5912,5914, and5916can be implemented using digital circuitry such as FIR filters or programmable FIR filters. When implemented digitally, these filters can be included within the VPA system or integrated with a baseband processor.

Subsequently, the outputs of interpolation filters5910,5912,5914, and5916are switched using switches5964,5966,5968, and5970to connect to either an upper band path5964or a lower band path5966of the VPA analog core5900. This determination between the upper and lower band paths is usually made by the digital control module5700based on the selected frequency range for transmission by the VPA. For example, the lower band path5966is used for GSM-900, while the upper band path5964is used for WCDMA. In an embodiment, switches5964,5966,5968, and5970are controlled by Vector MOD HI Band(s)/Vector MOD Low Band(s)n signal5786, provided by the digital control module5700. Signal5786controls the coupling of each of switches5964,5966,5968, and5970to respective first or second inputs, thereby controlling the coupling of the outputs of interpolation filters5910,5912,5914, and5916to the either the upper path5964or lower path5966of the VPA analog core5900.

The vector modulation stage of VPA analog core5900includes a plurality of vector modulators5922,5924,5926, and5928, divided between the upper band path5964and the lower band path5966of the analog core5900. Based on the selected band of operation, either the upper band path vector modulators (5922,5924) or the lower band path vector modulators (5926,5928) are active.

In an embodiment, the operation of vector modulators5922,5924or5926,5928is similar to the operation of vector modulators1750and1752in the embodiment ofFIG. 17, for example. Vector modulators5922and5924(or5926and5928) receive input signals5919,5921,5923, and5925(5927,5929,5931, and5933) from optional interpolation filters5910,5912,5914, and5916, respectively. Input signals5919,5921,5923, and5925(or5927,5929,5931, and5933) include amplitude information that is used to generate the constant envelope signals by the vector modulators. Further, vector modulators5922and5924(or5926and5928) receive a HI Band RF_CLK signal5935(LOW BAND RF_CLK signal5937) from a HI Band(s) Frequency Synthesizer5918(Low Band(s) Frequency Synthesizer5920). HI Band(s) Frequency Synthesizer5918(Low Band(s) Frequency Synthesizer5920) are optionally located externally or in the VPA analog core. In an embodiment, HI Band(s) Frequency Synthesizer5918(Low Band(s) Frequency Synthesizer5920) generates RF frequencies in the upper band range of 1.7-1.98 GHz (lower band range of 824-915 MHz). In another embodiment, HI Band(s) Frequency Synthesizer5918and Low Band(s) Frequency Synthesizer5920are controlled by digital control module signals5796and5798, respectively. Signals5796and5798, for example, power up the appropriate frequency synthesizer according to the selected transmission frequency band, and instruct the selected synthesizer to generate a RF frequency clock according to the selected transmission frequency.

Vector modulators5922and5924(or5926and5928) modulate input signals5919,5921,5923, and5925(5927,5929,5931, and5933) with HI BAND RF_CLK signal5935(LOW BAND RF_CLK signal5937). In an embodiment, vector modulators5922and5924(or5926and5928) modulate the input signals with appropriately derived and/or phase shifted versions of HI BAND RF_CLK signal5935(LOW BAND RF_CLK signal5937), and combine the generated modulated signals to generate substantially constant envelope signals5939and5941(5943and5945).

In another embodiment, vector modulators5922and5924(or5926and5928) further receive a phase balance control signal5751from the VPA digital control module. Phase balance control signal5751controls vector modulators5922and5924(or5926and5928) to cause a change in phase in constant envelope signals5939and5941(or5943and5945), in response to phase feedback information from the analog core. The amplitude and phase feedback mechanism is further discussed below. Optionally, upper band path vector modulators5922and5924also receive a 3G HI Band/Normaln signal5788from the digital control module. Signal5788can be used, if necessary, to further support driving the vector modulators at the highest frequencies of the upper band.

The output stage of VPA analog core5900includes a plurality of MISO amplifiers5930and5932, divided between the upper band path5964and the lower band path5966of the analog core5900. Based on the selected band of operation, either the upper band path MISO amplifier5930or the lower band path MISO amplifier5932is active.

In an embodiment, MISO amplifier5930(or5932) receives substantially constant envelope signals5939and5941(or5943and5945) from vector modulators5922and5924(or5926and5928). MISO amplifier5930(or5932) individually amplifies signals5939and5941(or5943and5945) to generate amplified signals, and combines the amplified signals to generate output signal5947(or5949). In an embodiment, MISO amplifier5930(or5932) combines the amplified signals via direct coupling, as described herein. Other modes of combining the amplified signals according to embodiments of the present invention have been described above in Section 3.

The output stage of VPA analog core5900is capable of supporting multi-band multi-mode VPA operation. As shown inFIGS. 59A-D, the output stage includes two MISO amplifiers5930and5932for upper band and lower band operation, respectively. In addition, the output of each of the upper band5964and the lower band5966is further switched between one or more output paths according to the selected transmission mode (e.g., GSM, WCDMA, etc.). Typically, separate output paths are needed for different transmission modes since FDD-based modes (e.g., WCDMA) require the presence of duplexers at the output, while TDD-based modes (e.g., GSM, EDGE) have T/R switched outputs.

In analog core5900, the output5947of MISO amplifier5930can be coupled to one of three output paths5954,5956, and5958, with each output path5954,5956,5958being the one that is coupled to an antenna (not shown) or connector (not shown) for a particular mode of transmission. Similarly, the output5949of MISO amplifier5932can be coupled to one of two output paths5960and5962. In an embodiment, output select signals5776,5778,5780,5782, and5784, provided by the digital control module, control switches5942and5944to couple the output of the active MISO amplifier to the appropriate output path, based on the selected transmission mode. It is noted that more or less output paths5954,5956,5958,5960, and5962may be used.

Accordingly, with only two MISO amplifiers5930and5932, analog core5900supports multiple different transmission modes. In an embodiment, analog core5900allows for using a single MISO amplifier to support GSM, EDGE, WCDMA, and CDMA2000. It is clear therefore that one of the advantages of this exemplary VPA analog core according to implementation5900is in the reduction in the number of PAs per supported output paths This directly corresponds to a reduction in required chip area for the VPA analog core5900.

In an embodiment, the output stage of analog core5900receives optional output stage autobias signal5761, driver stage autobias signal5763, and gain balance control signal5749from the digital control module. Output stage autobias signal5761and driver stage autobias signal5763may or may not be needed according to the particular type of transistors used in the actual MISO implementation. In an embodiment, output stage autobias signal5761and driver stage autobias signal5763control the bias of MISO amplification stages to cause a change in the power output and/or the power efficiency of the VPA. Similarly, gain balance control signal5749may cause a change in the gain levels of different MISO amplification stages, in response to power output feedback information received by the digital control module from the analog core. Further discussion of these optional output stage input signals will be provided below.

In an embodiment, the output stage of analog core5900provides optional feedback signals to the digital control module5700of the VPA. Typically, these feedback signals are used by the digital control module5700to correct for amplitude and phase variations in branches of the VPA and/or for controlling the output power of the VPA. In the specific implementation of analog core5900, a differential feedback approach is employed to monitor for amplitude and phase variations, using a differential branch amplitude signal5950and a differential branch phase signal5948provided by the output stage. Further, output power monitoring is provided using signals PWR Detect A5938and PWR Detect B5940, which measure the output power of MISO amplifiers5930and5932, respectively. Since only one of MISO amplifiers5930and5932can be active at any time, in an embodiment, PWR Detect A5938and PWR Detect5940are summed together using summer5942, to generate a signal that corresponds to the output power of the VPA.

In an embodiment, the feedback signals from the output stage are multiplexed using an input selector5946controlled by the digital control module5700. In another embodiment, the digital control module5700uses A/D Input Selector signals5738,5740,5742,5744, and5746to control input selector5946and select the feedback signal to be received. It is noted that monitoring of feedback signals may not need to occur in real-time rate and may only need to be performed periodically at a low rate. For example, for the purpose of branch amplitude and phase error correction, the rate at which feedback monitoring is performed depends on several factors such as the degree of feedforward correction being performed in the digital control module, process variations due to temperature, or operation changes such as changing battery or supply voltages.

Above, the tradeoffs between feedforward and feedback error compensation and/or correction techniques have been described. Accordingly, parameters governing the rates at which feedback monitoring is performed are design choices typically selected by the actual designer of the VPA. As a result, analog core implementation5900can be programmed to operate as a pure feedback implementation by disabling any feedforward correction in the digital control module, a pure feedforward implementation by disabling the monitoring of feedback signals, or as a hybrid feedforward/feedback implementation with variable feedforward/feedback utilization.

In an embodiment, the output stage of analog core5900includes optional output stage protection circuitry. InFIGS. 59A-D, this is illustrated using VSWR (Voltage-Standing-Wave-Ratio) Protect circuitry5934and5936coupled respectively to MISO amplifiers5930and5932. VSWR protection circuitry5934,5936may or may not be needed depending on the actual MISO amplifier implementation. In an embodiment, VSWR Protect circuitry5934and5936protect the output stage PAs (see PAs6030and6032inFIG. 60, for example) from going into thermal shutdown or device breakdown, when the output voltage level could cause the output stage breakdown voltage to be exceeded. In conventional systems, this is achieved by using an RF isolator at the output of the PAs, which is both expensive and lossy (typically causes around 1.5 dB in power loss). Accordingly, VSWR Protect circuitry5934,5936eliminate the need for isolators at the output stage, further reducing the cost, size, and power loss of the VPA. In an embodiment, VSWR Protect circuitry5934,5936enable an isolator-free output stage capable of supporting WCDMA. VSWR protection circuitry5934and5936also enable the VPA to operate into any VSWR level without damaging the VPA. VSWR protection circuitry can be designed to deliver the maximum output power of a particular implementation of a VPA into any VSWR level.

As described above, analog core5900includes power supply circuitry for controlling and delivering power to the different stages of the analog core5900. In one aspect, the power supply circuitry provides means for powering up active portions of the VPA analog core5900. In another aspect, the power supply circuitry provides means for controlling the power efficiency and/or the output power of the VPA.

In analog core implementation5900, the power supply circuitry includes MA Power Supply5902, Driver Stage Power Supply5904, Output Stage Power Supply5906, and Vector Mods Power Supply5908. In an embodiment, the power supply circuitry is controlled by output select signals5776,5778,5780,5782, and5784, provided by the digital control module5700.

MA Power Supply5902includes circuitry for controlling the powering up of active portions of the VPA analog core5900. In analog core5900, MA Power Supply5902has two outputs MA1VSUPPLY5903and MA2VSUPPLY5905. At any time, only one of MA1VSUPPLY5903or MA2VSUPPLY5905is active, ensuring that only the upper band5964or the lower band5966portion of the VPA analog core5900is powered up. In an embodiment, the active output of MA Power Supply5902is coupled to all active circuitry of the VPA analog core5900, with the exception of circuitry having unique power supply signals as described below. MA Power Supply5902receives output select signals from the digital control module, which enable one or the other of output signals MA1VSUPPLY5903or MA2VSUPPLY5905, based on the selected output of the VPA.

Driver Stage Power Supply5904includes circuitry for providing power to the driver stage circuitry of the MISO amplifiers5930,5932. Similar to MA Power Supply5902, Driver Stage Power Supply5904has two outputs MA1Driver VSUPPLY5907and MA2Driver VSUPPLY5909, with only one of the two outputs being active at any time. Driver Stage Power Supply5904is also controlled by output select signals5776,5778,5780,5782, and5784according to the selected output of the VPA. In addition, Driver Stage Power Supply5904receives a Driver Stage Voltage Control signal5767from the digital control module5700. In an embodiment, the outputs MA1Driver VSUPPLY5907and MA2Driver VSUPPLY5909are generated according to the received Driver Stage Voltage Control signal5767. In another embodiment, Driver Stage Voltage Control signal5767causes Driver Stage Power Supply5904to increase or decrease MA1Driver VSUPPLY5907or MA2Driver VSUPPLY5909to control the driver stage power amplification level. In another embodiment, Driver Stage Voltage Control signal5767is used by the digital control module5700to affect a change, using Driver Stage Power Supply5904, in the power supply voltage of the driver stage of the active MISO amplifier5930or5932, thereby controlling the power efficiency of the VPA.

Output Stage Power Supply5906includes circuitry for providing power to the PA stage circuitry of the MISO amplifiers5930,5932. Similar to MA Power Supply5902, Output Stage Power Supply5906has two outputs MA1Output Stage VSUPPLY5911and MA2Output Stage VSUPPLY5913, with only one of the two outputs being active at any time. Output Stage Power Supply5906is also controlled by output select signals5776,5778,5780,5782, and5784according to the selected output of the VPA. In addition, Output Stage Power Supply5906receives an Output Stage Voltage Control signal5765from the digital control module5700. In an embodiment, the outputs MA1Output Stage VSUPPLY5911and MA2Output Stage VSUPPLY5913are generated according to the received Output Stage Voltage Control signal5765. In another embodiment, Output Stage Voltage Control signal5765causes Output Stage Power Supply5906to increase or decrease MA1Output Stage VSUPPLY5911or MA2Output Stage VSUPPLY5913to control the PA stage power amplification level. In another embodiment, Output Stage Voltage Control signal5765is used by the digital control module5700to affect a change, using Output Stage Power Supply5906, in the power supply voltage of the PA stage of the active MISO amplifier5930or5932, thereby controlling the power efficiency of the VPA.

Vector Mods Power Supply5908includes circuitry for providing power to the vector modulators5922,5924,5926, and5928of the analog core5900. In analog core5900, Vector Mods Power Supply5908has two outputs5915and5917for powering up the upper band vector modulators5922and5924and the lower band vector modulators5926and5928, respectively. At any time, only one of outputs5915or5917is active, ensuring that only the upper band or the lower vector modulators of the analog core5900are powered up. Vector Mods Power Supply5908receives a vector mod select signal5786from the digital control module5700, which controls which of its two outputs5915and5917is active, according to the selected transmission frequency requirements.

In addition to the above described power supply circuitry, analog core5900may optionally include voltage reference generator circuitry. The voltage reference generator circuitry may reside externally or within the VPA analog core5900. The voltage reference generator circuitry generates reference voltages for different circuits within the VPA. In an embodiment, as illustrated inFIG. 57, the voltage reference generator circuitry provides reference voltages to DACs01-10, coupled to data outputs of the digital control module. In another embodiment, as illustrated inFIGS. 59A-D, the voltage reference generator circuitry provides reference voltages to the interpolation filters and/or the vector modulators in the VPA analog core. In an embodiment, circuits of the same branch of the VPA are provided with the same reference voltage. For example, note that DACs01and02, interpolation filters5910and5912, and vector modulators5922and5924, which represent a VPA branch or data path, all share the same reference voltage VREF_C5741. For different implementations and system performance requirements, the voltage reference signals can be provided as a single reference voltage or multiple reference voltages.

FIG. 60illustrates an output stage embodiment6000according to VPA analog core implementation5900. Output stage embodiment6000includes a MISO amplifier stage6058, an optional output switching stage (embodied by switch6044), and optional output stage protection and power detection circuitry.

MISO amplifier stage6058in embodiment6000includes a pre-driver amplification stage, embodied by Pre-Drivers6012and6014, a driver amplification stage, embodied by Drivers6018and6020, and a PA amplification stage, embodied by output stage PAs6030and6032. In an embodiment, substantially constant envelope input signals MA IN16008and MA IN26010are amplified at each stage of MISO amplifier6058, before being summed at the outputs of the PA stage.

In an embodiment, MISO amplifier stage6058is powered by power supply signals provided by voltage controlled power supply circuits. As described with reference toFIGS. 59A-D, the power supply signals are generated by power supply circuitry of the VPA analog core5900. In an embodiment, the power supply signals are used to control the power supply voltages of the different amplification stages of MISO amplifier stage6058, thereby affecting the power efficiency of the VPA under various operating conditions. In another embodiment, the power supply signals are used to control the gain of each of the different amplification stages of MISO amplifier stage6058, thereby enabling a power control mechanism. Further, the power supply signals can be controlled independently of each other, allowing for independent control of power and/or efficiency for each of the different amplification stages of MISO amplifier stage6058. This independent control allows, for example, for shutting off one or more amplification stages of MISO amplifier6058according to the desired output power of the VPA. InFIG. 60, the power supply signals are illustrated using signals6002,6004, and6006.

In an embodiment, MISO amplifier stage6058includes bias control circuitry. The bias control circuitry may be optional according to the particular MISO amplifier implementation. In an embodiment, the bias control circuitry provides a mechanism for controlling efficiency and/or power at each amplification stage of MISO amplifier6058. This mechanism is independent of the mechanism described above with reference to the power supply signals. Further, this mechanism provides for independently and individually controlling each amplification stage. InFIG. 60, the bias control circuitry is illustrated using Gain Balance Control Circuitry6016, Driver Stage Autobias Circuitry6022, and Output Stage Autobias Circuitry6028.

In an embodiment, Gain Balance Control Circuitry6016is coupled to the inputs of the pre-driver amplification stage as illustrated inFIG. 60. Gain Balance Control Circuitry6016receives a Gain Balance Control signal5749from the digital control module5700(through a DAC), and outputs input bias control signals6013and6015. Driver Stage Autobias Circuitry6022is coupled to the inputs of the driver amplification stage as illustrated inFIG. 60. Driver Stage Autobias Circuitry6022receives Driver Stage Autobias signal5763from the digital control module5700(through a DAC), and outputs input bias control signals6017and6019. Similarly, Output Stage Autobias Circuitry6028is coupled to the inputs of the PA amplification stage as illustrated inFIG. 60. Output Stage Autobias Circuitry6028receives Output Stage Autobias signal5761from the digital control module5700(through a DAC), and outputs input bias control signals6029and6031.

In an embodiment, the digital control module5700independently controls the bias of the pre-driver stage, the driver stage, and the PA stage of MISO amplifier6058using Gain Balance Control signal5749, Driver Stage Autobias signal5763, and Output Stage Autobias signal5761, respectively. In another embodiment, the digital control module5700may affect a change in the bias of the pre-driver stage, the driver stage, and/or the PA stage of MISO amplifier6058only using Gain Balance Control signal5749. As illustrated inFIG. 60, Gain Balance Control Circuitry6016is coupled to Driver Stage Autobias Circuitry6022and Output Stage Autobias Circuitry6028. In an embodiment, a change in the overall gain of the VPA is affected by digital control module5700first by controlling the bias at the pre-driver stage. If further gain change is needed, bias control is performed at the driver stage, and subsequently at the PA stage.

In an embodiment, MISO amplifier stage6058includes circuits for enabling an error correction and/or compensation feedback mechanism. In output stage embodiment6000, a differential feedback mechanism is adopted, whereby Differential Branch Amplitude Measurement Circuitry6024and Differential Branch Phase Measurement Circuitry6026respectively measure differences in amplitude and phase between branches of MISO amplifier6058. In an embodiment, Differential Branch Amplitude Measurement Circuitry6024and Differential Branch Phase Measurement Circuitry6026are coupled at the inputs of the PA stage (PAs6030and6032) of MISO amplifier6058. In other embodiments, circuitry6024and6026may be coupled at the inputs of prior stages of MISO amplifier6058. In an embodiment, Differential Branch Amplitude Measurement Circuitry6024and Differential Branch Phase Measurement Circuitry6026respectively output Differential Branch Amplitude signal5950and Differential Branch Phase signal5948, which are fed back to digital control module5700(through A/D converters). Since digital control module5700knows at any particular time the correct differences in amplitude and/or phase between the branches of MISO amplifier6058, it may determine any errors in amplitude and/or phase based on Differential Branch Amplitude signal5950and Differential Branch Phase signal5948.

Output stage embodiment6000includes optional output stage protection circuitry. The output stage protection circuitry may or may not be needed according to the particular MISO amplifier implementation. InFIG. 60, the output stage protection circuitry is illustrated using VSWR Protection Circuitry6034. In an embodiment, VSWR Protection Circuitry6034monitors the output of the PA stage, and controls the gain of MISO amplifier6058to protect PAs6030and6032. In embodiment6000, VSWR Protection Circuitry6034receives a signal6036, which is coupled either directly or indirectly to the output of the PA stage. In an embodiment, VSWR Protection Circuitry6034ensures that the voltage level at the output of the PA stage remains below a certain level, to prevent PAs6030and6032from going into thermal shutdown or experiencing device breakdown. In an embodiment, VSWR Protection Circuitry6034ensures that a breakdown voltage of PAs6030and6032is not exceeded. Accordingly, whenever the voltage level at the output of PAs6030and6032is above a pre-determined threshold, VSWR Protection Circuitry6034may cause a decrease in the gain of the MISO amplification stages. In an embodiment, VSWR Protection Circuitry6034is coupled to Balance Gain Control Circuitry6016, which in turn is coupled to both Driver Stage Autobias Circuitry6022and Output Stage Autobias Circuitry6028. In an embodiment, VSWR Protection Circuitry6034responds to a pre-determined voltage level at the output stage PAs by decreasing gain first at the pre-driver stage, then at the driver stage, and finally at the PA stage. As described above, VSWR

Protection Circuitry6034may or may not be needed according to the particular MISO amplifier implementation. For example, a GaAs (Gallium Arsenide) MISO amplifier implementation would not require VSWR Protection Circuitry, as typical breakdown voltages of GaAs transistors are too large to be exceeded in many RF scenarios.

Output stage embodiment6000includes optional power detection circuitry. In an embodiment, the power detection circuitry serves as a means for providing power level feedback to the digital control module. InFIG. 60, the power detection circuitry is illustrated using Power Detection Circuitry6038. In an embodiment, Power Detection Circuitry6038is coupled to the output of the PA stage of MISO amplifier6058. Power Detection Circuitry6038may be coupled directly or indirectly to the output of the PA stage as illustrated by signal6040inFIG. 60. In an embodiment, Power Detection Circuitry6038outputs a PWR Detect signal6023. PWR Detect signal6023may be equivalent to PWR Detect A signal5938or PWR Detect B signal5940shown inFIGS. 59A-D, which are fed back (through A/D converters) into the digital control module of the VPA. The digital control module uses PWR Detect signal6023to regulate the output power of the VPA as desired.

The optional output switching stage of output stage embodiment6000is embodied by a switch6044inFIG. 60. In an embodiment, switch6044is coupled to one of three outputs6046,6048, or6050of the VPA. As described earlier, the switch is controlled by a set of output select signals5776,5778, and5780, provided by the digital control module. Switch6044is coupled to the proper output according to the select transmission mode and/or desired output frequency requirements (e.g., GSM, WCDMA, etc.).

Accordingly, pull-up impedance coupling at the output of the VPA can be done in various ways. In an embodiment, as shown inFIG. 60, pull-up impedances6052,6054, and6056are respectively coupled between outputs6046,6048, and6050and MA Output Stage VSUPPLY6002. In another embodiment, a single pull-up impedance is used and is coupled between the output6042of the PA stage and MA Output Stage VSUPPLY6002. The advantage of the first approach lies in that, by placing the pull-impedance after the switch6044, the impedance characteristics of switch6044can be taken into account when selecting values for impedances6052,6054, and/or6056, allowing the VPA designer to exploit a further aspect to increase the efficiency of the VPA. On the other hand, the second approach requires a smaller number of pull-up impedances.

According to the particular MISO amplifier implementation, output stage embodiment6000may include more or less circuitry than to what is illustrated inFIG. 60.

According to embodiments of the present invention, output stage embodiment6000including MISO amplifier stage6058, the optional output switching stage (switch6044), and the optional output protection and power detection circuitry may be fabricated using a SiGe (Silicon-Germanium) material. In another embodiment, MISO amplifier stage6058is fabricated using SiGe, and the output switching stage is fabricated using GaAs. In another embodiment, the PA stage (PAs6030and6032) and the output switching stage are fabricated using GaAs, while other circuitry of MISO amplifier stage6058and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage, the driver stage, and the output switching stage are fabricated using GaAs, while other circuitry of MISO amplifier stage6058and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage, the driver stage, the pre-driver stage, and the output switching stage are fabricated using GaAs. In another embodiment, the VPA system may be implemented using CMOS for all circuitry except for the output stage (6030or6032) which could be implemented in SiGe or GaAs material. In another embodiment, the VPA system may be implemented in its entirety in CMOS. Other variations and/or combinations of fabrication material(s) used for circuitry of the output stage are also possible, as can be understood by a person skilled in the art, and are therefore also within the scope of embodiments of the present invention.

Accordingly, as different semiconductor materials have different costs and performance, embodiments of the present invention provide a variety of VPA designs encompassing a wide range of cost and performance options.

4.3.2) VPA Analog Core Implementation B

FIGS. 61A-Dillustrates an alternative VPA analog core implementation6100according to an embodiment of the present invention. For illustrative purposes, the VPA analog core6100is shown inFIGS. 61A-Das being connected to digital control module5700, although alternatively other digital control modules could be used. The physical connection between analog core6100and digital control module implementation5700is illustrated inFIGS. 61A-D, as indicated by the same numeral signals on bothFIG. 57andFIGS. 61A-D.

Analog core implementation6100is corresponds to a 2-Branch VPA embodiment. This implementation, however, can be readily modified to a 4-Branch or a CPCP VPA embodiment, as will be apparent to persons skilled in the art based on the teachings herein.

Analog core implementation6100has the same input stage and vector modulation stage as analog core implementation5900, described above. Accordingly, similar to analog core implementation5900, analog core6100includes an upper band path5964and a lower band path5966for upper band and lower band operation of the VPA, respectively.

One of the differences between analog core5900and analog core6100lies in the output stage of the VPA. In contrast to the output stage of analog core5900, which includes two MISO amplifiers5930and5932, the output stage of analog core6100includes five MISO amplifiers6126,6128,6130,6132, and6134, divided between the upper band path5964and the lower band path5966of the analog core. In an embodiment, the output stage includes a combination of SiGe and GaAs MISO amplifiers. In an embodiment, the upper band path5964includes three MISO amplifiers6126,6128, and6130, and the lower band path5966includes two MISO amplifiers6132and6134. Based on the selected band of operation, a single MISO amplifier, either in the upper band path5964or the lower band path5966, is active. In an embodiment, each of MISO amplifiers6126,6128,6130,6132, and6134can be dedicated to a single transmission mode (e.g., WCDMA, GSM, EDGE, etc.) of the VPA. This is in contrast to analog core5900, where each of MISO amplifiers5930and5932supports more than one transmission modes. Advantages and disadvantages of each architecture will be further discussed below.

As a result of having more than one MISO amplifiers per path, a switching stage is needed to couple the vector modulation stage to the MISO amplifiers in analog core6100. InFIGS. 61A-D, this is illustrated using switches6118,6120,6122, and6124. In an embodiment, according to the selected transmission mode, switches6118and6120couple the outputs5939and5941of vector modulators5922and5924to one of MISO amplifiers6126,6128, and6130. Similarly, switches6122and6124couples the outputs5943and5945to one of MISO amplifiers6132and6134, according to the selected transmission mode and/or frequency requirements.

In an embodiment, MISO amplifier6126(or6128,6130,6132,6134) receives constant envelope signals6119and6121(or6123and6125,6127and6129,6131and6133,6135and61137). MISO amplifier6126(or6128,6130,6132,6134) individually amplifies signals6119and6121(or6123and6125,6127and6129,6131and6133,6135and6137) to generate amplified signals, and combines the amplified signals to generate output signal6141(6144,6146,6148,6150). In an embodiment, MISO amplifier6126(or6128,6130,6132,6134) combines the amplified signals via direct coupling, as described herein. Other modes of combining the amplified signals according to embodiments of the present invention have been described above in Section 3.

The output stage of VPA analog core6100is capable of supporting multi-band multi-mode VPA operation. Further, since the output stage of analog core6100can dedicate one MISO amplifier for each supported transmission mode, the output switching stage (embodied in analog core5900by switches5942and5944) can be eliminated. This results in a more efficient output stage (no power loss due switching stage), but at the expense of a larger chip area. This summarizes the main tradeoff between the architecture of analog core5900and that of analog core6100.

In an embodiment, the output stage of analog core6100receives optional bias control signals from digital control module5700. These are output stage autobias signal5761, driver stage autobias signal5763, and gain balance control signal5749, which have been described above with reference to analog core5900.

In an embodiment, the output stage of analog core6100provides optional feedback signals to digital control module5700of the VPA. These feedback signals include Differential Branch Amplitude signal5950and Differential Branch Phase signal5948, described above with reference to analog core5900, to enable a differential feedback approach to monitor for amplitude and phase variations in branches of the VPA. Also, similar to analog core5900, output power monitoring is provided using PWR Detect signals6152,6154,6156,6158, and6160, each of which measuring one of outputs6142,6144,6146,6148, and6150of the VPA. Since only one of the VPA outputs can be active at any time, PWR Detect signals6152,6154,6156,6158, and6160are summed together, in an embodiment, using summer5952, to generate a signal that corresponds to the current output power of the VPA.

Similar to analog core5900, the feedback signals from the output stage are multiplexed using an input selector5946controlled by the digital control module. Other aspects of the multiplexing of the feedback signals are described above with reference to analog core5900.

Similar to analog core5900, analog core6100can be designed to operate as a pure feedback implementation by disabling any feedforward correction in the digital control module, a pure feedforward implementation by disabling the monitoring of feedback signals, or as a hybrid feedforward/feedback implementation with variable feedforward/feedback utilization.

In an embodiment, the output stage of analog core6100includes optional output stage protection circuitry. InFIGS. 61A-D, this is illustrated using VSWR (Voltage-Standing-Wave-Ratio) Protect circuitry6136,6138, and6140coupled respectively to MISO amplifiers6128,6130, and6134. VSWR protection circuitry may or may not be needed depending on the actual MISO amplifier implementation. For example, note that MISO amplifiers6126and6132, which are GaAs amplifiers, require no VSWR protection circuitry for many applications. Functions and advantages of VSWR Protection circuitry according to embodiments of the present invention are described above with reference to analog core5900.

Analog core6100includes power supply circuitry for controlling and delivering power to the different stages of the analog core. In one aspect, the power supply circuitry provides means for powering up active portions of the VPA analog core. In another aspect, the power supply circuitry provides means for controlling the power efficiency and/or the output power of the VPA.

The power supply circuitry of analog core6100is substantially similar to the power supply circuitry of analog core5900, with the difference being that analog core6100includes five MISO amplifiers as opposed to two in analog core5900. InFIGS. 61A-D, the power supply circuitry is embodied in GMA and MA Power Supply circuitry6102, Driver Stage Power Supply circuitry5904, Output Stage Power Supply circuitry5908, and Vector Mods Power Supply circuitry5908. Each of circuitry6102,5904, and5906has five output power supply signals, with a single one of these five output signals being active at any time, according to the active MISO amplifier of the VPA. Function and operation of the power supply circuitry of analog core6100are substantially similar to those of the power supply circuitry of analog core5900, described above.

FIG. 62illustrates an output stage embodiment6200according to VPA analog core implementation6100. Output stage embodiment6200includes a MISO amplifier stage6220and optional output stage protection and power detection circuitry.

MISO amplifiers6126,6128,6130,6132and/or6134shown inFIGS. 61A-Dcan be implemented using an amplifier such as MISO amplifier stage6220.

Output stage embodiment6200is substantially similar to output stage embodiment6000illustrated inFIG. 60, with the main difference being in the elimination of the output switching stage (embodied by switch6044inFIG. 60) in embodiment6200.

Similar to embodiment6000, MISO amplifier stage6220in embodiment6200includes a pre-driver amplification stage, embodied by Pre-Drivers6206and6208, a driver amplification stage, embodied by Drivers6210and6212, and a PA amplification stage, embodied by output stage PAs6214and6216. In an embodiment, substantially constant envelope input signals MA IN16202and MA IN6204are amplified at each stage of MISO amplifier6220, before being summed at the outputs of the PA stage. Input signals MA IN16202and MA IN6204correspond to signals6123and6125inFIGS. 61A-D, for example.

In an embodiment, MISO amplifier stage6220of output stage embodiment6200is powered by power supply signals provided by voltage controlled power supply circuits. In another embodiment, MISO amplifier stage6220includes optional bias control circuitry controllable by the digital control module. In another embodiment, MISO amplifier stage6220includes circuits for enabling an error correction and/or compensation feedback mechanism. In another embodiment, output stage embodiment6000includes optional output stage protection circuitry and power detection circuitry. These aspects (power supply, bias control, error correction, output protection, and power detection) of output stage embodiment6200are substantially similar to what have been described above with respect to output stage embodiment6000.

According to embodiments of the present invention, output stage embodiment6200may be fabricated using a SiGe (Silicon-Germanium) material including MISO amplifier stage6220and the optional output protection and power detection circuitry. In another embodiment, MISO amplifier stage6220is fabricated using SiGe in its entirety. In another embodiment, the PA stage (PAs6214and6216) of MISO amplifier stage6220is fabricated using GaAs, while other circuitry of MISO amplifier stage6220and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage and the driver stage (Drivers6210and6212) of MISO amplifier stage6220are fabricated using GaAs, while other circuitry of MISO amplifier stage6220and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage, the driver stage, and the pre-driver stage (Pre-Drivers6206and6208) are fabricated using GaAs. In another embodiment, the VPA system may be implemented using CMOS for all circuitry except for the output stage (6030or6032) which could be implemented in SiGe or GaAs material. In another embodiment, the VPA system may be implemented in its entirety in CMOS. Other variations and/or combinations of fabrication material(s) used for circuitry of the output stage are also possible, as can be understood by a person skilled in the art, and are therefore also within the scope of embodiments of the present invention. Further, output stages within the same the VPA may be fabricated using different material, as illustrated inFIGS. 61A-Dfor example, where MISO amplifiers6128,6130, and6134are SiGe amplifiers and MISO amplifiers6126and6132are GaAs amplifiers (one or more stages of their output stage are GaAs).

4.3.3) VPA Analog Core Implementation C

FIGS. 63A-Dillustrates another VPA analog core implementation6300according to an embodiment of the present invention. For illustrative purposes, example analog core6300is shown inFIGS. 63A-Das being connected to digital control module5800, although other digital control modules could alternatively be used. The physical connection between analog core6300and digital control module5800is indicated by the same numeral signals on bothFIG. 58andFIGS. 63A-D.

Analog core implementation6300corresponds to a 2-Branch VPA embodiment. This implementation, however, can be readily modified to a 4-Branch or a CPCP VPA embodiment, as will be apparent to a person skilled in the art based on the teachings herein.

Analog core implementation6300includes similar input stage, vector modulation stage, and amplification output stage as analog core5900ofFIGS. 59A-D. Function, operation and control of these stages is described above with reference toFIGS. 59A-D.

Similar to analog core5900, analog core6300includes a feedback error correction and/or compensation mechanism. In contrast to analog core5900, however, analog core6300employs a receiver-based feedback mechanism, as opposed to a differential feedback mechanism in analog core5900. A receiver-based feedback mechanism is one that is based on having a receiver that receives the active output of the VPA, generates I data and Q data from the received output, and feeds back the generated I and Q data to the digital control module. By estimating the delay between the input and the output of the VPA, the feedback I and Q signals can be properly aligned with their corresponding input I and Q signals. In another embodiment, the receiver feedback includes the complex output signal (magnitude and phase polar information) instead of Cartesian I and Q data signals.

In an embodiment, this is done by coupling a receiver (not shown) at the active output of the VPA (5947or5949). InFIGS. 63A-D, signals6302and6304respectively represent upper band and lower band RF inputs into the receiver. Only one of signals6302and6304can be active at any time, depending on whether the upper band path5964or the lower band path5966of analog core6300is being used. Similarly, the receiver-based feedback mechanism includes an upper band path and a lower band path. In an embodiment, each of the upper band and lower band feedback paths include an Automatic Gain Controller (AGC) (6306and6308), I/Q sample-and-hold (S/H) circuitry (6314,6316and6318,6320), switching circuitry (6322and6324), and optional interpolation filters (6326and6328). In an embodiment, a switch6330, controlled by the digital control module by means of input select signals5810and5812, couples either the upper band or the lower band feedback paths to the digital control module. Further, based on the coupled feedback path, digital control module I/Qn Select signal5808controls switching circuitry6322or6324to alternate the coupling of I data and Q data to the digital control module. Other implementations are also possible as can be understood by a person skilled in the art based on the teachings herein.

In an embodiment, the AGC circuitry is used to allow the receiver to feedback useful I and Q information over a wide dynamic range of VPA output power. For example, output signals5954,5956,5958,5960, and5962can vary from +35 dBm to −60 dBm in certain cell phone applications. For I and Q data to contain accurate feedback information, the I and Q output of the receiver needs to be scaled to utilize the majority of the input voltage range of the A/Dinsignal5736, independently of the output signal power. Digital Control module5800is designed to control the VPA to the required output power, which allows digital control module5800to determine an appropriate receiver gain to achieve the proper A/D input voltage which is digitized through A/D5732.

A VPA analog core with a receiver-based feedback mechanism can be implemented as a pure feedback, feedforward, or hybrid feedback/feedforward system. As described above, a pure feedback implementation requires a minimal amount of or no memory (RAM5608, NVRAM5610) in the digital control module. This may represent one advantage of an analog core implementation according to analog core6300, in addition to the elimination of differential feedback measurement circuitry from the analog core. Nonetheless, analog core6300can be programmed to operate as a pure feedback implementation by disabling any feedforward correction in digital control module5800, a pure feedforward implementation by disabling the monitoring of feedback signals, or as a hybrid feedforward/feedback implementation with variable feedforward/feedback utilization.

In an embodiment, the output stage of analog core6300includes optional output stage protection circuitry. This is not shown inFIGS. 63A-D, but has been described above with respect to analog core implementations5900and6100. Other aspects of analog core6300(bias control, power supply, etc.) are substantially similar to analog core5900, and are described above with reference toFIGS. 59A-D.

FIG. 64illustrates an output stage embodiment6400according to VPA analog core implementation6300. Output stage embodiment6400includes a MISO amplifier stage6434and an output switching stage. In an embodiment, MISO amplifier stage6434corresponds to MISO amplifier5930and/or5932, shown inFIGS. 63A-D(that is, either or both of MISO amplifiers5930,5932can be implemented using an amplifier such as MISO amplifier stage6434).

Output stage embodiment6400is substantially similar to output stage embodiment6000illustrated inFIG. 60, with the main difference being in the elimination of the differential branch measurement circuitry (6024and6026) due to the use a receiver-based feedback mechanism.

Similar to embodiment6000, MISO amplifier stage6434in embodiment6400includes a pre-driver amplification stage, embodied by Pre-Drivers6406and6408, a driver amplification stage, embodied by Drivers6410and6412, and a PA amplification stage, embodied by output stage PAs6414and6416. In an embodiment, constant envelope input signals MA IN16402and MA IN6404are amplified at each stage of MISO amplifier stage6434, before being summed at the outputs of the PA stage of MISO amplifier stage6434.

In an embodiment, MISO amplifier stage6434of output stage embodiment6400is powered by power supply signals provided by voltage controlled power supply circuits. In another embodiment, MISO amplifier stage6434includes optional bias control circuitry controllable by the digital control module. In another embodiment, output stage embodiment6400includes optional output stage protection circuitry (not shown inFIG. 64). These aspects (power supply, bias control, and output protection) of output stage embodiment6400are substantially similar to what have been described above with respect to output stage embodiment6000.

According to embodiments of the present invention, output stage embodiment6400may be fabricated using a SiGe (Silicon-Germanium) material including the MISO amplifier stage6434, the output switching stage6420, and the optional output protection circuitry. In another embodiment, MISO amplifier stage6434is fabricated using SiGe, and the output switching stage6420is fabricated using GaAs. In another embodiment, the PA stage (PAs6414and6416) of MISO amplifier stage6434and the output switching stage6420are fabricated using GaAs, while other circuitry of MISO amplifier stage6434and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage, the driver stage (Drivers6410and6412), and the output switching stage6420are fabricated using GaAs, while other circuitry of MISO amplifier stage6434and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage, the driver stage, the pre-driver stage (Pre-drivers6406and6408), and the output switching stage6420are fabricated using GaAs. In another embodiment, the VPA system may be implemented using CMOS for all circuitry except for the output stage (6030or6032) which could be implemented in SiGe or GaAs material. In another embodiment, the VPA system may be implemented in its entirety in CMOS. Other variations and/or combinations of fabrication material(s) used for circuitry of the output stage are also possible, as can be understood by a person skilled in the art, and are therefore also within the scope of embodiments of the present invention. Further, output stages within the same the VPA may be fabricated using different material, as illustrated inFIGS. 61A-Dfor example, where MISO amplifiers6128,6130, and6134are SiGe amplifiers and MISO amplifiers6126and6132are GaAs amplifiers (one or more stages of their output stage are GaAs).

5. REAL-TIME AMPLIFIER CLASS CONTROL OF VPA OUTPUT STAGE

According to embodiments of the present invention, a VPA output stage can be controlled to vary its amplifier class of operation according to changes in its output waveform trajectory. This concept is illustrated inFIG. 65with reference to an exemplary WCDMA waveform. The graph inFIG. 65illustrates a timing diagram of a WCDMA output waveform envelope versus the class of operation of the VPA output stage. Note that the output waveform envelope is directly proportional to the output power of the VPA output stage.

It is noted that the VPA output stage amplifier class traverses from a class S amplifier to a class A amplifier as the output waveform envelope decreases from its maximum value towards zero. At the zero crossing, the VPA output stage operates as a class A amplifier, before switching to higher class amplifier operation as the output waveform envelope increases.

One important problem overcome by this real-time ability to control the VPA output stage amplifier class of operation is the phase accuracy control problem. With regard to the example shown inFIG. 65, the phase accuracy control problem lies in the fact that in order to produce high quality waveforms, at any given power level, a 40 dB of output power dynamic range is desirable. However, the phase accuracy required to produce a 40 dB output power dynamic range (around 1.14 degrees or 1.5 picoseconds) is well beyond the tolerance of practical circuits in high volume applications. As will be appreciated, the specific power ranges cited in this paragraph, and elsewhere herein, are provided solely for illustrative purposes, and are not limiting.

Embodiments according to the present invention solve the phase accuracy control problem by transiting multiple classes of operation based on waveform trajectory so as to maintain the best balance of efficiency versus practical control accuracy for all waveforms. In embodiments, the output power dynamic range of the VPA output stage exceeds 90 dB.

In an embodiment, at higher instantaneous signal power levels, the amplifier class in operation (class S) is highly efficient and phase accuracy is easily achieved using phase control. At lower instantaneous signal power levels, however, phase control may not be sufficient to achieve the required waveform linearity. This is illustrated inFIG. 66, which shows a plot of the VPA output power (in dBm) versus the outphasing angle between branches of the VPA. It can be seen that at high power levels, a change in outphasing angle results in a smaller output power change than at lower power levels. Accordingly, phase control provides higher resolution power control at higher power levels than at lower power levels.

Accordingly, to support high resolution power control at lower power levels, other mechanisms of control are needed in addition to phase control.FIG. 67illustrates exemplary power control mechanisms according to embodiments of the present invention using an exemplary QPSK waveform. The QPSK constellation is imposed on a unit circle in the complex domain defined by cos(wt) and sin(wt). The constellation space is partitioned between three concentric and non-intersecting regions: an outermost “phase control only” region, a central “phase control, bias control, and amplitude control” region, and an innermost “bias control and amplitude control” region. According to embodiments of the present invention, the outermost, central, and innermost regions define the type of power control to be applied according to the power level of the output waveform. For example, referring toFIG. 67, at lower power levels (points falling in the innermost region), bias control and amplitude control are used to provide the required waveform linearity. On the other hand, at higher power levels (points falling in the outermost region), phase control (by controlling the outphasing angle) only is sufficient.

As can be understood by persons skilled in the art, the control regions illustrated inFIG. 67are provided for purposes of illustration only and are not limiting. Other control regions can be defined according to embodiments of the present invention. Typically, but not exclusively, the boundaries of the control regions are based on the Complementary Cumulative Density Function (CCDF) of the desired output waveform and the sideband performance criteria. Accordingly, the control regions' boundaries change according to the desired output waveform of the VPA.

In embodiments, the power control mechanisms defined by the different control regions enable the transition of the VPA output stage between different class amplifiers. This is shown inFIG. 68, which illustrates, side by side, the output stage amplifier class operation versus the output waveform envelope and the control regions imposed on a unit circle.FIG. 69further shows the output stage current in response to the output waveform envelope. It is noted that the output stage current closely follows the output waveform envelope. In particular, it is noted that the output stage current goes completely to zero when the output waveform envelope undergoes a zero crossing.

FIG. 70illustrates the VPA output stage theoretical efficiency versus the output stage current. Note that the output stage current waveform ofFIG. 70corresponds to the one shown inFIG. 69. In an embodiment, the VPA output stage operates at 100% theoretical efficiency for 98% (or greater) of the time. It is also noted fromFIG. 70the transition of the output stage between different amplifier classes of operation according to changes in the output stage current.

FIG. 71illustrates an exemplary VPA according to an embodiment of the present invention. For illustrative purposes, and not purposes of limitation, the exemplary embodiment ofFIG. 71will be used herein to further describe the various control mechanisms that can be used to cause the transitioning of the VPA output stage (illustrated as a MISO amplifier inFIG. 71) between different amplifier classes of operation.

The VPA embodiment ofFIG. 71includes a transfer function module, a pair of vector modulators controlled by a frequency reference synthesizer, and a MISO amplifier output stage. The transfer function module receives I and Q data and generates amplitude information that is used by the vector modulators to generate substantially constant envelope signals. The substantially constant envelope signals are amplified and summed in a single operation using the MISO amplifier output stage.

According to embodiments of the present invention, the MISO amplifier output stage can be caused to transition in real time between different amplifier classes of operation according to changes in output waveform trajectory. In an embodiment, this is achieved by controlling the phases of the constant envelope signals generated by the vector modulators. In another embodiment, amplitudes of the MISO amplifier input signals are controlled using the transfer function.

In another embodiment, the MISO amplifier inputs are biased (biasing of the MISO inputs can be done at any amplification stage within the MISO amplifier) using the transfer function to control the MISO amplifier class of operation. In other embodiments, combinations of these control mechanisms (phase, input bias and/or input amplitude) are used to enable the MISO amplifier stage to transition between different amplifier classes of operation.

FIG. 72is a process flowchart100that illustrates a method for real-time amplifier class control in a power amplifier, according to changes in output waveform trajectory, according to an embodiment of the invention. Process flowchart100begins in step110, which includes determining an instantaneous power level of a desired output waveform. In an embodiment, the instantaneous power level is determined as a function of the desired output waveform envelope.

Based on the determined instantaneous power level, step120of process flowchart100includes determining a desired amplifier class of operation, wherein said amplifier class of operation optimizes the power efficiency and linearity of the power amplifier. In an embodiment, determining the amplifier class of operation depends on the specific type of desired output waveform (e.g., CDMA, GSM, EDGE).

Step130includes controlling the power amplifier to operate according to the determined amplifier class of operation. In an embodiment, the power amplifier is controlled using phase control, bias control, and/or amplitude control methods, as described herein.

According to process flowchart100, the power amplifier is controlled such that it transitions between different amplifier classes of operation according to the instantaneous power level of the desired output waveform. In other embodiments, the power amplifier is controlled such that it transitions between different amplifier classes of operation according the average output power of the desired output waveform. In further embodiments, the power amplifier is controlled such that it transitions between different amplifier classes of operation according to both the instantaneous power level and the average output power of the desired output waveform.

According to embodiments of the present invention, the power amplifier can be controlled to transition from a class A amplifier to a class S amplifier, while passing through intermediary amplifier classes (AB, B, C, and D).

Embodiments of the invention control transitioning of the power amplifier(s) to different amplifier classes as follows:

To achieve a class A amplifier, the drive level and bias of the power amplifier are controlled so that the output current conduction angle is equal to 360 degrees. The conduction angle is defined as the angular portion of a drive cycle in which output current is flowing through the amplifier.

To achieve a class AB amplifier, the drive level and bias of the power amplifier are controlled so that the output current conduction angle is greater than 180 degrees and less than 360 degrees.

To achieve a class B amplifier, the drive level and bias of the power amplifier are controlled so that the output current conduction angle is approximately equal to 180 degrees.

To achieve a class C amplifier, the drive level and bias of the power amplifier are controlled so that the output current conduction angle is less than 180 degrees.

To achieve a class D amplifier, the drive level and bias of the power amplifier are controlled so that the amplifier is operated in switch mode (on/off).

To achieve a class S amplifier, the amplifier is controlled to generate a Pulse Width Modulated (PWM) output signal.

In an embodiment, the above described real-time amplifier class control of the VPA output stage is accompanied by a dynamic change in the transfer function being implemented in the digital control module of the VPA. This is further described below with respect toFIGS. 73-77.

FIG. 73illustrates an example VPA output stage according to an npn implementation with two branches. Each branch of the VPA output stage receives a respective substantially constant envelope signal. The substantially constant envelope signals are illustrated as IN1and IN2inFIG. 73. Transistors of the VPA output stage are coupled together by their emitter nodes to form an output node of the VPA.

When the VPA output stage operates as a class S amplifier, it effectuates Pulse Width Modulation (PWM) on the received substantially constant envelope signals IN1and IN2. A theoretical equivalent circuit of the VPA output stage in this amplifier class of operation is illustrated inFIG. 74. Note that transistors of the VPA output stage are equivalent to switching amplifiers in this class of operation. The output of the VPA as a function of the outphasing angle θ between the substantially constant envelope signals IN1and IN2(assuming that IN1and IN2have substantially equal amplitude of value A) is given by

SQ⁡(θ)=A⁢π-θ2⁢⁢π.
A plot of this function, described previously as the magnitude to phase shift transform, is illustrated inFIG. 76.

On the other hand, when the VPA output stage operates as a class A amplifier, it emulates a perfect summing node. A theoretical equivalent circuit of the VPA output stage in this amplifier class of operation is illustrated inFIG. 75. Note that transistors of the VPA output stage are equivalent to current sources in this class of operation. The output of the VPA as function of the outphasing angle θ between the substantially constant envelope signals. IN1and IN2(assuming that IN1and IN2have substantially equal amplitude of value A) is given by R(θ)=AA√{square root over (2(1+cos(θ)))}. A plot of this function, described previously as the magnitude to phase shift transform, is illustrated inFIG. 76.

According to an embodiment of the present invention, amplifier classes of operation A and S represent two extremes of the amplifier operating range of the VPA output stage. However, as described above, the VPA output stage may transition a plurality of other amplifier classes of operation including, for example, classes AAB, B, C, and D. Accordingly, the transfer function implemented by the digital control module of the VPA varies within a spectrum of magnitude to phase shift transform functions, with the transform functions illustrated inFIG. 76representing the boundaries of this spectrum. This is shown inFIG. 77, which illustrates a spectrum of magnitude to phase shift transform functions corresponding to a range of amplifier classes of operation of the VPA output stage.FIG. 77illustrates 6 functions corresponding to the six amplifier classes of operation A, AB, B, C, D, and S. In general, however, an infinite number of functions can be generated using the functions corresponding to the two extreme classes of operation A and S. In an embodiment, this is performed using a weighted sum of the two functions and is given by (1−K)×R(θ)+K×SQ(θ), with 0≦K≦1.

Mathematical basis for a new concept related to processing signals to provide power amplification and up-conversion is provided herein. These new concepts permit arbitrary waveforms to be constructed from sums of waveforms which are substantially constant envelope in nature. Desired output signals and waveforms may be constructed from substantially constant envelope constituent signals which can be created from the knowledge of the complex envelope of the desired output signal. Constituent signals are summed using new, unique, and novel techniques not available commercially, not taught or found in literature or related art. Furthermore, the blend of various techniques and circuits provided in the disclosure provide unique aspects of the invention which permits superior linearity, power added efficiency, monolithic implementation and low cost when compared to current offerings. In addition, embodiments of the invention are inherently less sensitive to process and temperature variations. Certain embodiments include the use of multiple input single output amplifiers described herein.

Embodiments of the invention can be implemented by a blend of hardware, software and firmware. Both digital and analog techniques can be used with or without microprocessors and DSP's.

Embodiments of the invention can be implemented for communications systems and electronics in general. In addition, and without limitation, mechanics, electro mechanics, electro optics, and fluid mechanics can make use of the same principles for efficiently amplifying and transducing signals.

The present invention has been described above with the aid of functional building blocks illustrating the performance of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Any such alternate boundaries are thus within the scope and spirit of the claimed invention. One skilled in the art will recognize that these functional building blocks can be implemented by discrete components, application specific integrated circuits, processors executing appropriate software and the like and combinations thereof.