Apparatus, system, and moving object

An apparatus includes a plurality of pixels, a plurality of circuits arranged correspondingly to the plurality of pixels, and an output line connected to the plurality of circuits. Each of the circuits generates a signal by converting an analog signal at a first conversion rate and a signal by converting, at a second conversion rate, the analog signal used for generating the signal converted at the first conversion rate. The circuit has a signal obtaining unit configured to obtain a difference signal corresponding to a difference between a signal converted at the first conversion rate and a signal converted at the second conversion rate.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to an apparatus, a system, and a moving object.

Description of the Related Art

A technology has been known which changes the rate of change of an electric potential of a ramp signal for use in an AD conversion based on the amplitude of a signal output from a pixel.

Japanese Patent Laid-Open No. 2014-140152 discloses a technology for correcting an error of a digital signal caused by an error between ramp signals having different rates of change of their electric potentials. The digital signal correction is performed by an output circuit to which digital signals are sequentially transferred from AD converting units of columns.

Furthermore, in recent years, increases of the number of pixels in an imaging apparatus and an increased frame rate have been demanded. A further increased number of pixels and a further increased frame rate may also increase the processing amount of signals in an output circuit to which digital signals are sequentially transferred from circuits of columns. The signal processing capability of such output circuits may possibly limit the performances of an imaging apparatus such as the number of pixels in and the frame rate of the imaging apparatus.

According to the technology disclosed in Japanese Patent Laid-Open No. 2014-140152, an output circuit to which signals are sequentially transferred from circuits of columns performs signal correction processing. This, however, may tighten the signal processing capability of the output circuit and may result in limited performances of an imaging apparatus such as the number of pixels in and the frame rate of the imaging apparatus.

SUMMARY OF THE INVENTION

According to an aspect of the embodiments, an apparatus includes a plurality of pixels, a plurality of circuits arranged correspondingly to the plurality of pixels, and an output line connected to the plurality of circuits. Each of the circuits generates a signal by converting an analog signal at a first conversion rate and a signal by converting, at a second conversion rate, the analog signal used for generating the signal converted at the first conversion rate. The circuit has a signal obtaining unit configured to obtain a difference signal corresponding to a difference between a signal converted at the first conversion rate and a signal converted at the second conversion rate.

DESCRIPTION OF THE EMBODIMENTS

Imaging apparatuses according to embodiments will be described below with reference to drawings.

FIG. 1Ais a block diagram illustrating an imaging apparatus according to a first embodiment of the present disclosure.

A pixel array102has a plurality of rows and a plurality of columns of pixels100. A vertical scanning circuit101is configured to sequentially select a predetermined row of the pixel array102and cause the pixels100of the predetermined row to output signals.

Externally to the pixel array102, a column circuit (AD converting unit150) including a comparator104is provided for each of the columns of the pixels100. An example will be described below in which one column circuit (AD converting unit150) is provided for each one column of the pixels100.

The pixels100and the corresponding AD converting unit150are connected through a vertical signal line50.

The AD converting unit150has a first selector80-1, a second selector80-2, the comparator104, a counter105, and a memory106.FIG. 1Aillustrates signals φS1, φCLMP, and clk output from a control unit (not illustrated) included in the imaging apparatus. The control unit is typically a timing generator.

The signal φS1is input to the first selector80-1. The first selector80-1receives signals output from the pixels100to the vertical signal line50and a signal Vrf. The first selector80-1selectively outputs one of the signals from the pixels100and the signal Vrf as a signal Vin_cmp to the comparator104based on whether the signal level of the signal φS1is a High level or a Low level.

The signal φS2is an output signal from the comparator104or a signal to be controlled by the control unit, not illustrated. The signal φS2is output to the second selector80-2. The second selector80-2outputs one of a ramp signal Vr1and a ramp signal Vr2output from a ramp signal supply circuit103as a signal Vr_cmp to the comparator104based on the signal level of the signal φS2.

A common counter108outputs a count signal to the memory106in the AD converting unit150for each column. The memory106receives an output signal from the comparator104. The memory106holds a signal code_N, a signal code_S, and a signal flg, which will be described below.

The counter105receives a signal clk being a clock signal and an output signal from the comparator104. The counter105holds a signal code_dif, which will be described below.

A horizontal scanning circuit107is configured to perform a control for sequentially reading digital signals from the counters105and the memories106in the AD converting units150of columns. The counters105in the AD converting units150of columns are connected to an output line160-1. The memories106of columns are connected to an output line160-2. A signal processing circuit109is configured to perform digital signal processing including correlated double sampling processing by using digital signals read out from the counters105and the memories106of columns. The signal processing circuit109outputs a signal generated by performing digital signal processing as an image signal to an apparatus external to the imaging apparatus.

FIG. 1Bis an equivalent circuit diagram of the pixel100. The pixel100has a photodiode PD which is a photoelectric converting unit. The pixel100further has a reset transistor M1, a transfer transistor M2, an amplification transistor M3, and a selection transistor M4. A signal φR, a signal φT, and a signal φSEL are output from the vertical scanning circuit101illustrated inFIG. 1A. One main node of the reset transistor M1, one main node of the transfer transistor M2, and an input node of the amplification transistor M3are connected to a floating diffusion portion FD.

FIG. 2is an equivalent circuit diagram of the comparator104illustrated inFIG. 1A. The comparator104according to this embodiment has an auto-zero clamp function. A differential amplifier has a capacitive coupling input unit. The differential amplifier has an input terminal to be reset to a common reset potential when the control unit changes the signal φCLMP to a High level. Thus, the comparator104undergoes the auto-zero clamp.

FIG. 3is a timing chart illustrating operations to be performed by the imaging apparatus illustrated inFIG. 1A.FIG. 3illustrates signals corresponding to the signals illustrated inFIGS. 1A and 1B.

According to this embodiment, a voltage change against a time of a second ramp signal Vr2is four times as large as that of the first ramp signal Vr1.

Referring toFIG. 3, a period V blank is a vertical blanking period. The vertical blanking period is a period when no signal is read from the pixel100. A period Valid 1H is a period when a signal is read from the pixel100and is one horizontal period (one row reading period). An operation in one horizontal period may be repeated a number of times equal to the number of rows in the pixel array to obtain signals for one screen, though not illustrated. When the signal φR, the signal φT, the signal φSEL and the signal φCLMP are changed to a High level, switches which receive the signals are turned on.

During the period V blank, the control unit changes the signal φS1to a High level. Thus, the first selector80-1outputs the signal Vrf as a signal Vin_cmp. At the same time, the control unit changes the signal φS2to a High level. Thus, the second selector80-2outputs the first ramp signal Vr1as a signal Vr_cmp.

The control unit changes the signal φCLMP to a High level. Thus, the comparator104undergoes auto-zero clamp. After that, the control unit changes the signal φCLMP to a Low level.

The ramp signal supply circuit103starts a change with passage of time of the electric potential of the first ramp signal Vr1. The comparator104compares the first ramp signal Vr1and the signal Vin_cmp with respect to their magnitude relationship and outputs a comparison result signal representing a result of the comparison.

Operations to be performed by the counter105will be described briefly here and will be described in detail below with reference toFIG. 4. The counter105starts counting the signal clk in response to the start of the change of the electric potential of the first ramp signal Vr1. Here, the counter105performs an up-count operation which counts the signal clk in a direction (first direction) of an increase of the count value.

In response to the change of the magnitude relationship between the first ramp signal Vr1and the signal Vin_cmp, the signal level of the comparison result signal output from the comparator104changes. In response to the change of the signal level of the comparison result signal, the counter105stops counting the signal clk. Thus, the counter105obtains a first digital signal corresponding to the signal Vrf.

Next, the control unit changes the signal level of the signal φS2to a Low level. Thus, the second selector80-2outputs the second ramp signal Vr2as a signal Vr_cmp.

The ramp signal supply circuit103starts a change with passage of time of the electric potential of the second ramp signal Vr2. The comparator104compares the second ramp signal Vr2and the signal Vin_cmp with respect to their magnitude relationship and outputs a comparison result signal representing the result of the comparison.

The counter105starts counting the signal clk in response to the start of the change of the electric potential of the second ramp signal Vr2. At this time, the counter105performs a down-count operation which counts the signal clk in a direction of a decrease of the count value (second direction opposite to the first direction) starting from a digital value of the first digital signal.

In response to the change of the magnitude relationship between the second ramp signal Vr2and the signal Vin_cmp, the signal level of the comparison result signal output from the comparator104changes. In response to the change of the signal level of the comparison result signal, the counter105stops counting the signal clk. Thus, the counter105obtains a second digital signal corresponding to the signal Vrf. The second digital signal will be called a signal code_dif. The signal code_dif is a difference signal between a digital signal corresponding to the first ramp signal Vr1and the signal Vrf and a digital signal corresponding to the second ramp signal Vr2and the signal Vrf. The signal code_dif is held in the counter105in the AD converting unit150for each column. The counter105is a signal obtaining unit configured to obtain a correction value (second digital signal) being a difference between a digital signal (first digital signal) corresponding to the signal Vrf and the first ramp signal Vr1being analog signals and a digital signal corresponding to the signal Vrf and the second ramp signal Vr2.

With reference toFIG. 4, a method for obtaining the signal code_dif through up/down-count operations performed by the counter105will be described in detail.

The count value of the counter105is set to 0. The counter105starts up-counting from start of a change of the potential of the first ramp signal Vr1. In response to the change of the comparison result signal depending on the change of the magnitude relationship between the signal Vr_cmp and the signal Vin_cmp, the counter105stops counting the signal clk. At this time, the counter105obtains the first digital signal.

Next, in response to the start of the change of the potential of the second ramp signal Vr2, the counter105starts down-counting. The counter105starts the down-counting from the first digital signal. The down-counting is performed such that the change amount of the count value per unit time period can be larger than that of the up-counting. This is because the second ramp signal Vr2has a second rate of change four times as large as the first rate of change, compared with the first ramp signal Vr1having the electric potential changing at the first rate of change. The AD conversion using the second ramp signal Vr2is a ¼ AD conversion gain of that of the AD conversion using the first ramp signal Vr1. In other words, the column circuit (AD converting unit150) has a ¼ input signal conversion rate using the second ramp signal Vr2of that using the first ramp signal Vr1. In order to reduce the difference between the AD conversion gains, the down-counting is performed such that the change amount of the count value per unit time period can be larger than that of the up-counting. The down-counting may be performed such that the change amount of the count value per unit time period can be four times as large as the change amount of the count value per unit time period when the up-counting is performed. More specifically, it may be achieved by increasing the clock frequency of the signal clk in the down-counting to four times of the clock frequency of the signal clk in the up-counting. Thus, the counter105can obtain the signal code_dif.

During the period Valid 1H, the control unit changes the signal φS1to a Low level. Thus, the first selector80-1outputs the signal to be output from the pixel100to the vertical signal line50as a signal Vin_cmp.

During the period Valid 1H, the vertical scanning circuit101reads out signals from the pixels100of a predetermined one row (hereinafter, selected row) of the pixel array102. The vertical scanning circuit101changes the signal level of the signal φSEL to be output to the pixels100of the selected row to a High level. This turns on the selection transistors M4of the pixels100of the selected row. Thus, the amplification transistors M3in the pixels100of the selected row are connected to the vertical signal line50through the selection transistors M4.

Then, the vertical scanning circuit101changes the signal level of the signal φR to be output to the pixels100of the selected row to a High level. This resets the floating diffusion portions FD in the pixels100of the selected row to a predetermined electric potential.

The vertical scanning circuit101changes the signal level of the signal φR to a Low level. A signal to be output from the amplification transistors M3to the vertical signal line50through the selection transistors M4will be called a pixel reset signal.

The control unit changes the signal level of the signal φS2to a High level. Here, the control unit causes the signal φS2to have a High level. Thus, the second selector80-2outputs the first ramp signal Vr1as a signal Vr_cmp.

The control unit changes the signal level of the signal CLMP to a High level. Thus, the comparator104undergoes auto-zero clamp. The control unit changes the signal level of the signal φCLMP to a Low level.

Next, the AD converting unit150performs an AD conversion on the pixel reset signal. Referring toFIG. 3, the period in which the AD conversion is performed is called “N AD”. Hereinafter, the period will be called “N AD”.

The ramp signal supply circuit103starts a change with passage of time of the electric potential of the first ramp signal Vr1. The comparator104compares the first ramp signal Vr1and the pixel reset signal with respect to their magnitude relationship and outputs a comparison result signal representing the result of the comparison.

The common counter108starts counting the signal clk in response to the start of the change of the electric potential of the first ramp signal Vr1. The common counter108up-counts the signal clk.

In response to a change of the magnitude relationship between the first ramp signal Vr1and the pixel reset signal, the signal level of the comparison result signal output from the comparator104changes. In response to the change of the signal level of the comparison result signal, the memory106holds the count signal output from the common counter108. Thus, the counter105obtains a third digital signal that is a digital signal corresponding to the pixel reset signal. The digital signal is called a signal code_N.

Next, the vertical scanning circuit101changes the signal level of the signal φT of the selected row to a High level and then to a Low level. Thus, the electric charges accumulated in the photodiode PD are transferred to the floating diffusion portion FD. Therefore, the amplification transistor M3outputs a signal based on the electric charges accumulated in the photodiode PD through the selection transistor M4. This signal will be called an optical signal.

The comparator104determines whether the optical signal has an amplitude higher than a threshold value level or not. The ramp signal supply circuit103sets the electric potential of the first ramp signal Vr1to the threshold value level. The control unit keeps the signal φS2at a High level. Thus, the second selector80-2outputs the threshold value level as a signal Vr_cmp. The comparator104compares the threshold value level and the optical signal. The control unit changes the control over the signal φS2from the control by the control unit to the control based on the output from the comparator104. In a case where the comparator104determines that the optical signal has an amplitude higher than the threshold value level, the signal level of the signal φS2is changed to a Low level. In a case where the comparator104determines that the optical signal has an amplitude lower than the threshold value level on the other hand, the signal level of the signal φS2is changed to a High level.

In a Case where the Optical Signal has an Amplitude Lower than the Threshold Value Level:

A determination result flag flg=0 that is a comparison result between the threshold value level and the optical signal is held in the memory106.

Next, the AD converting unit150performs an AD conversion on the optical signal. Referring toFIG. 3, the period in which the AD conversion is performed on the optical signal is called “S AD”. Hereinafter, the period will be called “S AD”.

During the period S AD, the signal level of the signal φS2is changed to a High level based on the comparison result between the threshold value level and the optical signal, as described above.

Therefore, the second selector80-2outputs the first ramp signal Vr1to the comparator104as a signal Vr_cmp. The subsequent operations are the same as the operations to be performed in the period N AD. As a result of the AD conversion, the memory106obtains a fourth digital signal that is a digital signal corresponding to the optical signal. The digital signal will be called a signal code_S.

In a Case where the Optical Signal has an Amplitude Higher than the Threshold Value Level:

A determination result flag flg=1 that is a comparison result between the threshold value level and the optical signal is held in the memory106.

Next, the AD converting unit150performs AD conversion on the optical signal.

During the period S AD, the signal level of the signal φS2is changed to a Low level based on the comparison result between the threshold value level and the optical signal, as described above.

Therefore, the second selector80-2outputs the second ramp signal Vr2to the comparator104as a signal Vr_cmp. The subsequent operations are the same as the operations to be performed in the period N AD. As a result of the AD conversion, the memory106obtains the signal code_S.

The signal processing circuit109processes digital signals output from the AD converting units150of columns. The processing includes digital correlated double sampling for obtaining a difference between the signal code_S and the signal code_N. The signal code_S obtained by using the first ramp signal Vr1and the signal code_S obtained by using the second ramp signal Vr2have an AD conversion gain difference due to a difference in rate of change between the electric potentials of the ramp signals. In order to reduce the AD conversion gain difference, the signal processing circuit109applies a four-time gain to the signal code_S obtained by using the second ramp signal Vr2. The processing is implemented by performing a bit shift which shifts the signal code_S obtained by using the second ramp signal Vr2to higher order by 2 bits. Then, the signal processing circuit109performs processing for obtaining a difference between a fifth digital signal that is a difference between the signal code_N and the signal code_dif and the signal code_S. This processing may compensate for the digital correlated double sampling processing and an error in the AD conversion due to use of two ramp signals having different rates of change in electric potential.

More specifically, the signal processing circuit109performs the digital correlated double sampling processing in the following manner.
If flg=0
code_out=code_S−code_N
If flg=1
code_out=code_S×4−(code_N−code_dif)

In this manner, the imaging apparatus according to this embodiment performs processing for compensating for the digital correlated double sampling processing and an error in the AD conversion by using two ramp signals having different electric potential rates of change. Thus, the imaging apparatus according to this embodiment can obtain a higher-quality image signal.

In the imaging apparatus according to this embodiment, the AD converting unit150of each column obtains the signal code_dif that is a correction value. This can reduce the signal processing amount of the signal processing circuit109compared with a case where the signal processing circuit109generates a correction value for the AD converting unit150of each column. Thus, improved performance such as an increased number of pixels and an increased frame rate of an imaging apparatus can be easily achieved.

According to this embodiment, one AD converting unit150is provided for pixels100of one column, for example. This embodiment is not limited thereto, but one AD converting unit150may be provided for pixels100of a plurality of columns. Alternatively, a plurality of AD converting units150may be provided for pixels100of one column.

According to this embodiment, the second ramp signal has a rate of change of the electric potential four times as large as that of the first ramp signal. This embodiment is not limited to the example but may apply other rates. For facilitating the signal processing by the signal processing circuit109, the slope ratio of the ramp signals may be raised to the nth-power of 2. The slope ratio may be raised to the nth-power of 2 so that the processing for multiplying the signal code_S by a gain to be performed by the signal processing circuit109can be implemented by bit shifting.

According to this embodiment, the ramp signals change their electric potentials in a slopewise manner, for example. This embodiment is not limited to the example, but the ramp signals may change their electric potentials in a stepwise manner. Signals having their electric potentials changing in a stepwise manner are also included in the same category as that of the ramp signals having their electric potential changing with passage of time.

According to this embodiment, the ramp signal supply circuit103provided on the semiconductor substrate having the imaging apparatus thereon generates ramp signals. A circuit which generates ramp signals having electric potentials changing with passage of time may be provided externally to the semiconductor substrate having the imaging apparatus thereon. In this case, the imaging apparatus has a ramp signal supply circuit (such as a buffer circuit) for outputting an externally input ramp signal to the AD converting unit150of each column.

According to this embodiment, the AD converting unit150for each column obtains the signal code_dif that is a correction value. In another example, the AD converting units150for a plurality of columns may operate as one block to obtain one signal code_dif. In this case, the signals code_dif generated by the AD converting units150for the plurality of columns may be averaged by the signal processing circuit109. Alternatively, a signal code_dif generated by one AD converting unit150of AD converting units150for a plurality of columns may also be used as a correction value for each of the AD converting units150for the plurality of columns. In this case, some AD converting units150of the AD converting units150for a plurality of columns may have a counter105being a signal holding unit.

According to this embodiment, in order to obtain the signal code_dif, an AD conversion using the first ramp signal Vr1is performed before an AD conversion using the second ramp signal Vr2is performed. In another example, the AD conversion using the second ramp signal Vr2may be performed before the AD conversion using the first ramp signal Vr1is performed.

According to this embodiment, a signal code_dif is obtained prior to the readout of signals from the pixels100of each column. In another example, a signal code_dif may be obtained once during the readout of signals from the pixels100of each column. The counter105may obtain the signal code_dif during a period (one frame period) from readout of signals from the pixels100of a predetermined row to the next readout of signals from the pixels100of the predetermined row. The counter105may obtain a signal code_dif when the imaging apparatus is powered on.

Other operations to be performed by the counter105for obtaining a signal code_dif will be described below.

FIG. 5illustrates a case where the counter105is a continuity counter. For measuring an error in the AD conversion using the first ramp signal Vr1and in the AD conversion using the second ramp signal Vr2, the counter105may not necessarily have a bit count for the full-scale AD conversions. The possible range of the error can be estimated by arithmetic processing if digital signals with a certain degree of accuracy are obtained.

Referring toFIG. 5, the counter105is a counter, which generates a count signal having 4 bits signals and a code indicating negative or positive. The counter105is a continuity counter which does not clip an overflow and an underflow. An equal number of rounds occur both in the up-counting and the down-counting during the periods for obtaining the first digital signal and the second digital signal as illustrated inFIG. 3. Also in this case, the difference value code_dif can be correctly obtained. With the configuration of the counter105illustrated inFIG. 5, the bit count can be reduced, compared with the configuration of the counter105which performs the operations illustrated inFIG. 4. Therefore, the circuit area of the counter105can also be reduced.

Second Embodiment

An imaging apparatus according to a second embodiment will be described mainly with respect to differences from the first embodiment.

FIG. 6Ais a block diagram illustrating a configuration of an imaging apparatus according to a second embodiment. The imaging apparatus according to this embodiment has a configuration different from the one illustrated inFIG. 1Ain that the first selector80-1is omitted and that the output from a dummy pixel100ais selectable with a signal φS1instead of the signal Vrf.

FIG. 6Bis an equivalent circuit diagram of the dummy pixel100a. The dummy pixel100ahas a reset transistor M1aand a dummy pixel transistor M3ato be controlled by a signal φRa output from the vertical scanning circuit101and a selection transistor M4ato be controlled by the signal φS1.

FIG. 7is a timing chart illustrating operations to be performed by the imaging apparatus illustrated inFIG. 6A.

The timing chart inFIG. 7is different from the timing chart illustrated inFIG. 3in that a signal φRa is further given.

During a period V blank, the signal levels of the signals φS1and φRa are a High level. A signal corresponding to a reset level is output from the dummy pixel100a. By using the signal, the AD converting unit150for each column obtains a difference signal code_dif by performing the same AD conversion operation as that of the first embodiment. The other operations are the same as those of the first embodiment.

Having described the example using a dummy pixel, an analog input signal for obtaining a difference signal code_dif for each column may be other arbitrary signals according to the present disclosure. It is not intended that the present disclosure is limited by the type of the analog input signal.

Third Embodiment

A third embodiment will be described mainly with respect to differences from the first embodiment. An imaging apparatus according to this embodiment is different from the first embodiment in that the AD converting unit150includes an infinite impulse response (IIR) filter112that is a digital low pass filter circuit and a difference memory106-1.

FIG. 8is a block diagram illustrating the AD converting unit150according to this embodiment. The IIR filter112is configured to compare a signal code_dif obtained by the counter105with the signal code_dif obtained last time. The IIR filter112filters the signal code_dif and stores the result of the filtering in the difference memory106-1.

According to this embodiment, an error due to noise occurring in a measurement of a difference value between the signals code_dif may possibly deteriorate the quality of the resulting image signal.

Even when noise is mixed to the obtained difference value and results in an error, the configuration of this embodiment can reduce an influence of the noise by performing the low pass filter processing by the IIR filter112.

Fourth Embodiment

An imaging apparatus according to a fourth embodiment will be described with respect to differences from the first embodiment. The imaging apparatus according to the first embodiment obtains a signal code_S and a signal code_N by using a count signal output from the common counter108provided commonly for the AD converting units150of a plurality of columns. The imaging apparatus according to this embodiment is different from the imaging apparatus according to the first embodiment in that the signal code_S and the signal code_N are obtained by using a count signal output from the counter105provided in the AD converting unit150for each column.

FIG. 9is a block diagram illustrating a configuration of the AD converting units150in the imaging apparatus according to this embodiment. Each of the AD converting units150has a flag memory110, a difference memory106-1, and an S-N memory106-2.

The signal code_dif can be obtained by performing the same operations as those illustrated inFIG. 3except that the count signal is output from the counter105instead of the common counter108. The difference memory106-1is configured to hold the signal code_dif.

Operations to be performed during a period Valid 1H will be described with reference toFIG. 10.

The AD converting unit150performs an AD conversion during a period N AD by using a first ramp signal Vr1. Here, the counter105counts a signal clk by performing down-counting. In response to a change of the signal level of a comparison result signal, the S-N memory106-2holds the count signal output from the counter105. Thus, the S-N memory106-2obtains a signal code_N that is a digital signal corresponding to a pixel reset signal.

After that, the comparator104compares an amplitude of the optical signal and a threshold value level. Based on the result of the comparison, one of a case indicated by the solid-line and a case indicated by the broken line illustrated inFIG. 10is selected as a subsequent process to be performed by the AD converting unit150.

In a Case where the Optical Signal has an Amplitude Lower than the Threshold Value Level:

A determination result flag that is a comparison result between the threshold value level and the optical signal is held in the flag memory110. After that, during a period S AD, the counter105up-counts the signal clk based on the change amount per unit time period of the count signal regarded as being equal to that in the period N AD. The counter105defines the initial value for starting the up-counting as the value of the signal code_N. The rest is the same as those in the period N AD. Thus, the S-N memory106-2holds the signal code_S−code_N. Therefore, a digital signal corresponding to the optical signal with a reduced noise component can be obtained.

In a Case where the Optical Signal has an Amplitude Higher than the Threshold Value Level:

A determination result flag flg=1 that is a comparison result between the threshold value level and the optical signal is held in the flag memory110. After that, during a period S AD, the counter105up-counts the signal clk based on the change amount per unit time period of the count signal regarded as being equal to four times as large as that in the period N AD. The counter105defines the initial value for starting the up-counting as the value of the signal code_N. The other points are the same as those in the period N AD. Thus, the S-N memory106-2holds the signal code_S×4−code_N in the S-N memory106-2. Therefore, a digital signal corresponding to the optical signal with a reduced noise component can be obtained. The counter105defines the change amount of the count value per unit time period four times in the period S AD as large as that in the period N AD. Thus, the AD conversion using the second ramp signal Vr2having a rate of change of electric potential four times as large as that of the first ramp signal Vr1can result in a digital signal assumed to be obtained if the first ramp signal Vr1is used. In other words, because the second ramp signal Vr2has a gradient four times as large as that of the first ramp signal Vr1, the resulting AD conversion gain is ¼ times while a four-time AD conversion gain can be obtained by a counting operation. The product of the ¼ times and the four times result in an equal AD conversion gain both in the case using the second ramp signal Vr2and in the case using the first ramp signal Vr1.

In this manner, the imaging apparatus including the counter105, instead of the common counter108, within the AD converting unit150can obtain a digital signal corresponding to the digital signal obtained according to the first embodiment. The imaging apparatus according to this embodiment also provides the same effect as that of the imaging apparatus according to the first embodiment.

Fifth Embodiment

An imaging apparatus according to a fifth embodiment will be described with respect to differences from the first embodiment. According to the first embodiment, the signal code_dif is obtained by using a count signal output from the counter105provided in the AD converting unit150. This embodiment is different from the first embodiment in that the signal code_dif is obtained by using a count signal output from the common counter108, instead of a count signal output from the counter105.

FIG. 11is a block diagram illustrating the AD converting unit150in the imaging apparatus according to this embodiment. The common counter108is commonly provided for each of the AD converting units150for a plurality of columns, like the first embodiment. Each of the AD converting units150has a flag memory110, a subtraction circuit111, and a difference memory106-1.

Referring toFIG. 3, during the period V blank, the memory106holds a first digital signal obtained by performing an AD conversion on a signal vrf by using the first ramp signal Vr1. During the period V blank, the memory106holds a digital signal (sixth digital signal) obtained by performing an AD conversion on a signal vrf by using the second ramp signal Vr2. The subtraction circuit111obtains a digital signal representing a difference between the first digital signal and the sixth digital signal. In other words, the subtraction circuit111is a computing unit configured to obtain a digital signal representing a difference between the first digital signal held in the memory106and the sixth digital signal. The digital signal is a second digital signal corresponding to the signal code_dif according to the first embodiment. The difference memory106-1holds the signal code_dif obtained by the subtraction circuit111.

The operations in the period Valid 1H are performed in the same manner as those inFIG. 3.

In a case where the AD converting unit150of each column does not have the counter105, the imaging apparatus according to this embodiment can obtain a digital signal corresponding to the digital signal obtained according to the first embodiment. Thus, the imaging apparatus according to this embodiment can provide the same effect as that of the imaging apparatus according to the first embodiment. In The imaging apparatus according to this embodiment, the counter105in the AD converting unit150of each column can be omitted. Thus, the effect of reduction of power consumption can further be obtained, compared with the imaging apparatus according to the first embodiment. In a case where the subtraction circuit111has a smaller circuit size than that of the circuit size of the counter105, the imaging apparatus according to this embodiment can provide an effect of reduction of the circuit area of the AD converting unit150, compared with the imaging apparatus according to the first embodiment.

Sixth Embodiment

FIGS. 12A and 12Bare block diagrams illustrating an imaging apparatus according to a sixth embodiment of the present disclosure. The sixth embodiment further has amplifiers110each corresponding to an amplifying unit in addition to the configuration of the first embodiment. According to the first embodiment, the rate of change of a ramp signal is changed based on the amplitude of an optical signal. According to this embodiment, a ramp signal to be used for an AD conversion of an optical signal has one rate of change. The amplifier110is configured to output an amplified signal obtained by amplifying a signal input to the amplifier110at a predetermined amplification ratio.

A column circuit170includes the amplifier110and an AD converting unit150. The amplifier110has an operational amplifier, capacitor elements Ci, Cf1, and Cf2, and switches to be controlled by signals φR_AMP and φatt. The amplifier110may have an amplification gain which can be set to a first amplification gain and a second amplification gain higher than the first amplification gain. Hereinafter, the first amplification gain and the second amplification gain will be called a low gain and a high gain, respectively. A state that the amplifier110is set to the low gain will be called a low gain state, and a state that the amplifier110is set to the high gain will be called a high gain state. The conversion rate of the column circuit is changed based on the gain of the amplifier110. The amplifier110has an input connected to a vertical signal line or a signal Vrf through a selector80-3. An output of the amplifier110and a ramp signal Vr are input to the comparator104.

A period V blank inFIG. 13is a vertical blanking period, likeFIG. 3. During a period V blank, the control unit changes the signal φS1to a High level. The amplifier110has an input Vin_amp having a value Vrf. The control unit changes signals φR_amp and φatt to a High state and resets the amplifier110. After the signals φR_amp and φatt are sequentially changed to a Low state and the amplifier110is changed to a high gain state, the signal φCLMP is changed to a High state so that the comparator104undergoes auto-zero clamp. Next, the ramp signal Vr is ramped up so that an AD conversion is performed with the amplifier110having the high gain. Next, the signal φatt is changed to a High state so that the amplifier110is changed to have a low gain state. Next, the ramp reference signal Vr is ramped up again so that am AD conversion is performed with the amplifier110at the low gain state. Thus, digital values can be obtained at the high gain state and at the low gain state. While the gain switching is performed based on the gradient of the ramp signal in the example inFIG. 3, the gain of the amplifier110is directly changed according to this embodiment. In other words, according to this embodiment, the conversion rate of the column circuit is changed based on the gain of the amplifier110.

During a period Valid 1H when a pixel signal is read out, the control unit changes the signal φS1to a low state, and the vertical signal line is connected to an input of the amplifier110. The signals φR_amp, φatt, and φCLMP are sequentially changed to a Low state, and an AD conversion is performed with the amplifier110having a high gain amplification state and with the pixel reset state. This period is called “N AD” inFIG. 13. A digital signal is obtained in response to a change of the magnitude relationship between a ramped up ramp reference signal Vr and Vin_cmp. Next, whether the optical signal has an amplitude higher than a threshold value level or not is determined. InFIG. 13, the operation is indicated by “DETERMINE LUMINANCE LEVEL”. The control unit determines the magnitude relationship between the signal Vim_cmp and the signal Vr to change the signal φatt.

In a Case where the Optical Signal has an Amplitude Lower than the Threshold Value Level:

The signals Vin_cmp and φatt are indicated by solid lines inFIG. 13. The signal φatt keeps a low state, and the amplifier110has the high gain state. By keeping the high gain state, an optical signal undergoes an AD conversion. Referring toFIG. 13, this period is called “S AD”.

In a Case where the Optical Signal has an Amplitude Higher than the Threshold Value Level:

The signals Vin_cmp and φatt are indicated by broken lines inFIG. 13. When The control unit detects that Vin_cmp is higher than the threshold value, the signal φatt is changed to a High state. This changes the amplifier110to have a low gain state. Next, an AD conversion is performed on the optical signal with the low gain state.

Also in the imaging apparatus according to this embodiment, the AD converting unit150for each column obtains a signal code_dif that is a correction value. Thus, like the imaging apparatus according to the first embodiment, the signal processing amount of the signal processing circuit109can be reduced, compared with a case where the signal processing circuit109generates a correction value for the AD converting unit150for each column. Thus, improved performance such as an increased number of pixels and an increased frame rate of an imaging apparatus can be easily achieved.

Seventh Embodiment

FIG. 14is a block diagram illustrating a configuration of an imaging system500according to a seventh embodiment. The imaging system500according to this embodiment includes a solid-state imaging apparatus200applying a configuration of any one of the imaging apparatuses according to the aforementioned embodiments. Concrete examples of the imaging system500may include a digital still camera, a digital camcorder, and a surveillance camera and so on.FIG. 14illustrates a configuration example of a digital still camera applying the imaging apparatus according to any one of the aforementioned embodiments as the solid-state imaging apparatus200.

The imaging system500illustrated inFIG. 14has the solid-state imaging apparatus200, a lens502configured to form an optical image of an object on the solid-state imaging apparatus200, a diaphragm504usable for adjusting the quantity of light to pass through the lens502, and a barrier506for protecting the lens502. The lens502and the diaphragm504form an optical system configured to gather light to the solid-state imaging apparatus200.

The imaging system500has a signal processing unit508configured to process a signal output from the solid-state imaging apparatus200. The signal processing unit508is configured to perform signal processing operations including correcting and compressing an input signal and outputting the processed signal. The signal processing unit508is capable of performing AD conversion processing on a signal output from the solid-state imaging apparatus200. In this case, the solid-state imaging apparatus200may not necessarily has an AD conversion circuit internally.

The imaging system500further includes a buffer memory unit510configured to temporarily store image data and an external interface unit (external I/F unit)512for communication with an external computer. The imaging system500further includes a recording medium514such as a semiconductor memory to and from which image data is written and read and a recording medium control interface unit (recording medium control I/F unit)516for writing and reading data to and from the recording medium514. The recording medium514may be internally provided or be detachably mounted in the imaging system500.

The imaging system500further includes an overall control/calculation unit518configured to perform different kinds of computing and generally control the imaging system500such as a digital still camera and a timing generation unit520configured to output timing signals to the solid-state imaging apparatus200and the signal processing unit508. Here, the timing signals may be externally input, and the imaging system500may only include at least the solid-state imaging apparatus200and a signal processing unit508configured to process signals output from the solid-state imaging apparatus200. The overall control/calculation unit518and the timing generation unit520may be configured to implement a part or all of control functions of the solid-state imaging apparatus200.

The solid-state imaging apparatus200is configured to output an image signal to the signal processing unit508. The signal processing unit508is configured to perform a predetermined signal process on an image signal output from the solid-state imaging apparatus200and output image data. The signal processing unit508is further configured to generate an image by using the image signal.

An imaging system applying the solid-state imaging apparatus corresponding to any one of the aforementioned embodiments can provide a higher quality image.

Eighth Embodiment

FIG. 15AandFIG. 15Billustrate configurations of an imaging system1000and a moving object according to an eighth embodiment.FIG. 15Aillustrates an example of the imaging system1000relating to a vehicle-mounted camera. The imaging system1000has an imaging apparatus1010. The imaging apparatus1010may be any one of the imaging apparatuses according to the aforementioned embodiments. The imaging system1000includes an image processing unit1030configured to perform an image process on a plurality of image data sets obtained by the imaging apparatus1010and a parallax obtaining unit1040configured to calculate a parallax (phase difference between parallax images) from the a plurality of image data pieces obtained by the imaging system1000. The imaging system1000further includes a distance obtaining unit1050configured to calculate a distance to a target object based on the calculated parallax and a collision determining unit1060configured to determine whether there is a collision possibility based on the calculated distance. Here, the parallax obtaining unit1040and the distance obtaining unit1050are examples of a distance information obtaining unit configured to obtain distance information to a target object. In other words, the distance information is information regarding a parallax, a de-focused amount, and a distance to a target object, for example. The collision determining unit1060may determine a collision possibility by using such distance information. The distance information obtaining unit may be implemented by a specifically designed hardware module or software module. The distance information obtaining unit may be implemented by an Field Programmable Gate Array (FPGA), an ASIC (Application Specific Integrated circuit) or the like or a combination thereof.

The imaging system1000is connected to a vehicle information obtaining apparatus1310and can obtain vehicle information such as a vehicle speed, a yaw rate, and a helm position. A control ECU1410is connected to the imaging system1000. The control ECU1410is a control device configured to output a control signal for causing a braking force to the vehicle based on a determination result by the collision determining unit1060. In other words, the control ECU1410is an example of a moving object control unit configured to control a moving object based on distance information. The imaging system1000is also connected to an alert apparatus1420configured to give an alert to a driver based on a determination result by the collision determining unit1060. For example, if the collision determining unit1060determines that there is a high collision possibility, the control ECU1410performs a vehicle control for avoidance of a collision or reduction of damages by braking, releasing the acceleration pedal, or suppressing an engine output, for example. The alert apparatus1420warns a user by giving an audio alert, displaying alert information on a screen of a car navigation system, or vibrating a sheet belt or a steering, for example.

According to this embodiment, the imaging system1000may be used to capture an image of surroundings of a vehicle such as its front or back.FIG. 15Billustrates the imaging system1000in a case where an image of a front (image capturing range1510) of a vehicle is to be captured. The vehicle information obtaining apparatus1310transmits an instruction to the imaging system1000to operate and capture an image. Any one of the imaging apparatuses according to the aforementioned embodiments may be used as the imaging apparatus1010so that the imaging system1000according to this embodiment can have more improved accuracy of focusing.

Having described the example of the control for prevention of collision with another vehicle, this embodiment is also applicable to a control for automatic driving by following another vehicle or a control for preventing the vehicle from crossing over a lane marking, for example. Furthermore, the imaging system is also applicable to not only vehicles such as a vehicle on which the imaging system is mounted but also moving objects (moving apparatuses) such as ships, airplanes and industrial robots. In addition, the imaging system is also applicable to not only moving objects but also apparatuses which apply object identification such as an intelligent transportation system (ITS).

Variation Examples

All of the aforementioned embodiments are merely given for illustrating concrete examples for embodying the present disclosure. The technical scope of the present disclosure should not be limitedly interpreted based on the examples. In other words, various aspects of the embodiments can be implemented without departing from its technical scope or features. Various combinations of the aforementioned embodiments may also be implemented.

According to the present disclosure, an imaging apparatus can be provided which can easily achieve improved signal output performance such as an increased number of pixels and an increased frame rate of the imaging apparatus.

This application claims the benefit of Japanese Patent Application No. 2017-072541 filed Mar. 31, 2017 which is hereby incorporated by reference herein in its entirety.