SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect

A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of semiconductor integrated circuits and, more particularly, to an improved SiGe device with SiGe-embedded dummy pattern that encircles the SiGe device, which is capable of alleviating the micro-loading effect during the epitaxial growth of SiGe.

2. Description of the Prior Art

As known in the art, stress can be introduced in the channel region of a MOS transistor to increase carrier mobility, thereby enhancing the performance of the MOS transistor. Generally, it is desirable to induce tensile stress in the channel region of an NMOS device in a source-to-drain direction, and to induce compressive stress in the channel region of a PMOS device in a source-to-drain direction. Typically, to induce compressive stress in the channel region of a PMOS transistor, epitaxially grown SiGe (also referred to as SiGe stressor) is formed in the source and drain regions of the PMOS devices. Since SiGe has a greater lattice constant than silicon, it expands after annealing and induces compressive stress to the channel region in a source-to-drain direction.

However, the conventional SiGe technology suffers from the influence of micro-loading effect, which occurs due to a difference in pattern densities on a single die. The micro-loading effect leads to variation of epitaxial growth rates between a region of a higher density and a region of a lower density. Due to the difference in growth rates, the thickness of the resulting SiGe film becomes non-uniform. In addition, the composition of the epitaxial SiGe stressor in an isolated active region usually differs from that in a densely packed active region. Such non-uniformities may alter the stress level of the epitaxial SiGe stressor and adversely affect device performance.

Accordingly, there is a strong need in this industry to provide an improved SiGe device and method for alleviating the micro-loading effect, while at the same time overcoming the deficiencies of the prior art.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide an improved SiGe device with specially designed SiGe-embedded dummy pattern that encompasses the SiGe device, which is capable of alleviating the micro-loading effect during the epitaxial growth of SiGe.

According to the claimed invention, a semiconductor device with dummy patterns for alleviating micro-loading effect comprises a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of first dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the first dummy patterns contains SiGe.

From one aspect of this invention, a semiconductor device comprises a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; a plurality of SiGe-embedded, cell-like dummy patterns provided on the semiconductor substrate within the middle annular region, wherein each of the SiGe-embedded, cell-like dummy patterns has substantially the same structure as that of the SiGe device; and a plurality of SiGe-free, cell-like dummy patterns in the outer region.

DETAILED DESCRIPTION

This invention pertains to an improved SiGe device with SiGe-embedded dummy patterns encompassing the SiGe device, which is capable of alleviating or counteracting the micro-loading effect during the epitaxial growth of SiGe. Such SiGe device may be a circuit component of mixed-signal circuits, RF circuits or analog circuits, and is usually designed as an isolated component in order to avoid coupling effect.

FIG. 1is a schematic top view showing the layout of the SiGe device and SiGe dummy pattern in accordance with the first preferred embodiment of this invention. As shown inFIG. 1, a SiGe device100is formed in an isolated region10of a substrate1. The substrate1may be a silicon substrate, silicon-on-insulator (SOI) substrate or other suitable semiconductor substrates. The SiGe device100may include but not limited to P-channel metal-oxide-semiconductor (PMOS) transistors or bipolar junction transistors. By way of example, the SiGe device100is a PMOS transistor and comprises a gate stack101, a P+source diffusion region102and a P+drain diffusion region103.

An N well12is formed in the isolated region10of a substrate1, wherein the SiGe device100is fabricated within the N well12. Both of the P+source diffusion region102and the P+drain diffusion region103contain an epitaxially grown SiGe stressor layer. Shallow trench isolation (STI)14is formed in the substrate1to electrically isolate the SiGe device100.

Typically, the steps before growing the SiGe stressor layer in the source and drain regions include forming a gate stack on a semiconductor substrate, forming spacers on sidewalls of the gate stack, and forming recesses in the silicon substrate along gate spacers. Then the SiGe stressor layer may be epitaxially grown in the recesses and annealed. The SiGe stressor layer may be formed by any suitable methods known in the art, for example, selective epitaxial growth (SEG) methods.

To effectively counteract the micro-loading effect of SiGe growth, a plurality of SiGe dummy patterns20are added to a middle annular region300. The middle annular region300is between an inner region200and an outer region400, wherein the SiGe device100is disposed within the inner region200. The SiGe dummy patterns20surround the SiGe device100. The SiGe dummy patterns20are active areas, which are defined concurrently with the active area or oxide define (OD) region of the SiGe device100. SiGe is grown in these active areas concurrently with the SiGe stressor layer grown in the P+source diffusion region102and the P+drain diffusion region103of the SiGe device100.

Please refer toFIG. 2andFIG. 3.FIG. 2is a schematic top view showing the layout of the SiGe device and SiGe-embedded dummy pattern in accordance with the second preferred embodiment of this invention, andFIG. 3is a schematic, cross-sectional diagram taken along line I-I ofFIG. 2, wherein like numeral numbers designate like regions, elements or layers.

As shown inFIG. 2andFIG. 3, likewise, a SiGe device100is formed in an N well12of a substrate1. The substrate1may be a silicon substrate, silicon-on-insulator (SOI) substrate or other suitable semiconductor substrates. According to the second preferred embodiment, the SiGe device100may include but not limited to a PMOS transistor and comprises a gate stack101, a P+source diffusion region102and a P+drain diffusion region103. A SiGe stressor layer102ais formed on the P+source diffusion region102and a SiGe stressor layer103ais formed on the P+drain diffusion region103. STI14is formed in the substrate1to electrically isolate the SiGe device100.

In this embodiment, a plurality of SiGe-embedded dummy diffusion regions32and a plurality of dummy poly-Si patterns34are provided around the SiGe device100. As best seen inFIG. 2, the SiGe-embedded dummy diffusion regions32and the dummy poly-Si patterns34, which together encompass the SiGe device100, are arranged in an alternate manner. However, any other arrangements make SiGe-embedded dummy diffusion regions32appear around the SiGe device100may also be used.

Referring toFIG. 3, to effectively counteract the micro-loading effect of SiGe growth, a dummy SiGe layer32ais grown in each of the SiGe-embedded dummy diffusion regions32. The dummy SiGe layer32ais grown concurrently with the SiGe stressor layers102aand103a. As best seen inFIG. 3, the dummy poly-Si patterns34are situated directly above the STI14and do not overlap with the SiGe-embedded dummy diffusion regions32.

As shown inFIG. 2andFIG. 3, the plurality of SiGe-embedded dummy diffusion regions32and the plurality of dummy poly-Si patterns34are disposed within a middle annular region300. The middle annular region300is between an inner region200and an outer region400, wherein the SiGe device100is disposed within the inner region200. A plurality of dummy poly-Si patterns34and a plurality of SiGe-free dummy diffusion regions36are provided in the outer region400. The term “SiGe-free” refers to not containing SiGe herein. No SiGe is grown in the SiGe-free dummy diffusion regions36. Likewise, the dummy poly-Si patterns34and the SiGe-free dummy diffusion regions36are arranged, but not limited to, in an alternate manner. Each dummy poly-Si pattern34is formed on the STI14. Analogously, the dummy poly-Si pattern34does not overlap with the SiGe-free dummy diffusion region36in the outer region400.

Please refer toFIG. 4andFIG. 5.FIG. 4is a schematic top view showing the layout of the SiGe device and SiGe-embedded dummy pattern in accordance with the third preferred embodiment of this invention, andFIG. 5is a schematic, cross-sectional diagram taken along line II-II ofFIG. 4. As shown inFIG. 4, a SiGe device100is formed in an N well12of a substrate1. The substrate1may be a silicon substrate, SOI substrate or other suitable semiconductor substrates. According to the third preferred embodiment, the SiGe device100may include but not limited to a PMOS transistor and comprises a gate stack101, a P+source diffusion region102, a P+drain diffusion region103, and a P channel between the P+source diffusion region102and the P+drain diffusion region103. SiGe stressor layers102aand103aare formed on the P+source diffusion region102and the P+drain diffusion region103, respectively. STI14is formed in the substrate1to electrically isolate the SiGe device100.

According to the third preferred embodiment, a plurality of SiGe-embedded, cell-like dummy patterns332are disposed within the middle annular region300, which is between the inner region200and the outer region400. The SiGe device100is disposed within the inner region200. A plurality of SiGe-free, cell-like dummy patterns432are disposed within the outer region400.

In this embodiment, the SiGe-embedded, cell-like dummy patterns332are fabricated concurrently with the SiGe device100. Therefore, each of the SiGe-embedded, cell-like dummy patterns332may have the same structure as that of the SiGe device100except that no contact is formed on the SiGe-embedded, cell-like dummy patterns332. That is, each of the SiGe-embedded, cell-like dummy patterns332has a dummy gate301, a dummy P+diffusion region302and a dummy P+diffusion region303. SiGe layers302aand303aare formed on the dummy P+diffusion region302and the dummy P+diffusion region303, respectively.

Each of the SiGe-free, cell-like dummy patterns432disposed within the outer region400may have the same structure as that of the SiGe device100except the contact and the SiGe layer. As best seen inFIG. 5, each of the SiGe-free, cell-like dummy patterns432has a dummy gate401, a dummy P+diffusion region402and a dummy P+diffusion region403. No SiGe layers are formed on the dummy P+diffusion region402and the dummy P+diffusion region403.

FIG. 6is a schematic top view showing the layout of the SiGe device and SiGe-embedded dummy pattern in accordance with the fourth preferred embodiment of this invention. As shown inFIG. 6, a SiGe device100ais formed in an inner region200. A plurality of SiGe-embedded, cell-like dummy patterns332aare formed in the middle annular region300that surrounds the inner region200. A plurality of SiGe-free, cell-like dummy patterns432aare formed in the outer region400.

The SiGe-embedded, cell-like dummy patterns332amay be fabricated concurrently with the SiGe device100a. Therefore, each of the SiGe-embedded, cell-like dummy patterns332amay have the same structure as that of the SiGe device100aexcept that no contact is formed on the SiGe-embedded, cell-like dummy patterns332a. Each of the SiGe-free, cell-like dummy patterns432adisposed within the outer region400may have the same structure as that of the SiGe device100aexcept the contact and the SiGe layer.

One germane feature of the fourth preferred embodiment as set forth inFIG. 6is that a plurality of poly-Si dummy patterns502are added in the middle annular region300. In this embodiment, these poly-Si dummy patterns502are disposed on the STI14and situated between the SiGe-embedded, cell-like dummy patterns332a. By adding these poly-Si dummy patterns502, the poly-Si critical dimension (CD) can be improved.