A logic circuit for quantum-resistant cryptoprocessing. The logic circuit includes a first plurality of multiplexers, a second plurality of multiplexers, a plurality of AND gates, a third plurality of multiplexers, a plurality of shift registers, a plurality of inverters, a fourth plurality of multiplexers, a plurality of adders, a plurality of XOR gates, a fifth plurality of multiplexers, and a plurality of parallel outputs.

TECHNICAL FIELD

The present disclosure generally relates to cryptoprocessing, and particularly, to binary Ring-LWE cryptoprocessing.

BACKGROUND

To implement secure channels for communications, a set of operations should be executed for cryptographic primitives such as public key encryption and decryption. Classic public key cryptosystems are computationally complex and may not be efficiently implemented on resource-constrained devices. Moreover, classic public key cryptosystems may rely on hard problems that may have polynomial time solutions using quantum search algorithm. Therefore, classic public key cryptosystems may not be quantum-resistant and may require very large keys to remain secure, which may not be practical due to hardware implementation complexity. There are alternative cryptosystems that rely on quantum-resistant hard problems. Ring learning with error (Ring-LWE) cryptosystems may rely on hardness of LWE problem. However, implementation of Ring-LWE may require some operations on ring of polynomials that may lead to high complexity. As a result, implementation of Ring-LWE on resource-constrained devices may be challenging.

There is, therefore, a need for a cryptoprocessing circuit that implements a quantum-resistant cryptoprocessing method with low complexity. There is also a need for a cryptoprocessing circuit that implements a quantum-resistant cryptoprocessing method with high speed.

SUMMARY

In one general aspect, the present disclosure describes an exemplary logic circuit for quantum-resistant cryptoprocessing. An exemplary logic circuit may include a first plurality of multiplexers, a second plurality of multiplexers, a plurality of AND gates, a third plurality of multiplexers, a plurality of shift registers, a plurality of inverters, a fourth plurality of multiplexers, a plurality of adders, a plurality of XOR gates, a fifth plurality of multiplexers, and a plurality of parallel outputs.

In an exemplary embodiment, an (n,1)thmultiplexer of the first plurality of multiplexers may be configured to route one of an ithfirst random sequence of a plurality of first random sequences and an ithprivate sequence of a plurality of private sequences to an (n,1)thoutput utilizing a first selector input. An exemplary ithfirst random sequence may include b bits where b is a positive integer. In an exemplary embodiment, each bit of the ithfirst random sequence may be equal to an ithrandom bit of a first plurality of random bits. An exemplary ithprivate sequence may include the b bits. In an exemplary embodiment, each bit of the ithprivate sequence may be equal to an ithbit of a second plurality of bits, where n∈[0,N−1], i∈[0,N−1], and N is a number of the first plurality of bits.

In an exemplary embodiment, an (n,2)thmultiplexer of the second plurality of multiplexers may be configured to route one of an nthpublic subsequence of a plurality of public subsequences, an nthpublic key sequence of a plurality of public key sequences, and an nthfirst ciphertext sequence of a plurality of first ciphertext sequences to an (n,2)thoutput utilizing a second selector input. Each exemplary public subsequence of the plurality of public subsequences may include the b bits and may represent a decimal number in a range of

In an exemplary embodiment, an nthAND gate of the plurality of AND gates may be configured to generate an nthAND gate output by performing an AND operation on the (n,1)thoutput and the (n,2)thoutput. An exemplary (n,3)thmultiplexer of the third plurality of multiplexers may be configured to route one of an nthsecond ciphertext sequence of a plurality of second ciphertext sequences, an nthtemporary sequence of a plurality of temporary sequences, the nthAND gate output, an nthsecond random sequence of a plurality of second random sequences, an nththird random sequence of a plurality of third random sequences, and an nthmessage sequence of a plurality of message sequences to an (n,3)thoutput utilizing a third selector input. An exemplary nthtemporary sequence may include the b bits. Each exemplary bit of the nthtemporary sequence may be equal to an nthbit of the first plurality of bits. An exemplary nthsecond random sequence may include the b bits. Each exemplary bit of the nthsecond random sequence may be equal to an nthrandom bit of a second plurality of random bits. An exemplary nththird random sequence may include the b bits. Each exemplary bit of the nththird random sequence may be equal to an nthrandom bit of a third plurality of random bits. An exemplary nthmessage sequence may include the b bits.

In an exemplary embodiment, an nthshift register may be configured to generate an nthshift register output by storing an nthresult sequence of a plurality of result sequences. An exemplary nthresult sequence may include the b bits. An exemplary plurality of inverters may include a zeroth inverter and a jthinverter. An exemplary zeroth inverter may be configured to generate a zeroth inverter output by bit-wise inverting an (N−1)thshift register output of the plurality of shift register outputs. An exemplary jthinverter may be configured to generate a jthinverter output by bit-wise inverting a (j−1)thshift register output of the plurality of shift register outputs where j∈[1,N−1].

In an exemplary embodiment, the fourth plurality of multiplexers may include a (0,4)thmultiplexer and a (j,4)thmultiplexer. An exemplary (0,4)thmultiplexer may be configured to route one of the zeroth inverter output and the (N−1)thshift register output to a (0,4)thoutput utilizing a fourth selector input. An exemplary (j,4)thmultiplexer may be configured to route one of the jthinverter output and the (j−1)thshift register output to a (j,4)thoutput utilizing the fourth selector input.

In an exemplary embodiment, an nthadder of the plurality of adders may be configured to generate an nthadder output by summing the (n,3)thoutput, an (n,4)thoutput, and an nthcarry input. An exemplary nthadder output may be associated with the nthresult sequence. An nthXOR gate of the plurality of XOR gates may be configured to generate an nthXOR gate output by performing an XOR operation on two most significant bits of the nthresult sequence. An exemplary (n,5)thmultiplexer of the fifth plurality of multiplexers may be configured to route one of the nthresult sequence and the nthXOR gate output to an (n,5)thoutput utilizing a fifth selector input. An exemplary nthparallel output of the plurality of parallel outputs may be connected to the (n,5)thoutput.

DETAILED DESCRIPTION

The following detailed description is presented to enable a person skilled in the art to make and use the methods and devices disclosed in exemplary embodiments of the present disclosure. For purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that these specific details are not required to practice the disclosed exemplary embodiments. Descriptions of specific exemplary embodiments are provided only as representative examples. Various modifications to the exemplary implementations will be readily apparent to one skilled in the art, and the general principles defined herein may be applied to other implementations and applications without departing from the scope of the present disclosure. The present disclosure is not intended to be limited to the implementations shown, but is to be accorded the widest possible scope consistent with the principles and features disclosed herein.

Herein is disclosed exemplary method and circuits for quantum-resistant cryptoprocessing. An exemplary method aims to provide a secure channel between two entities and is based on binary ring learning with error (LWE) hard problem. The method may include a public key generation, an encryption, and a decryption. The method may perform the public key generation, the encryption, and the decryption by a multiplication and a summation over a ring of polynomials. The ring may utilize an inverted binary ring LWE that may eliminate a reduction operation resulting in hardware implementation efficiency. The multiplication may be performed by a shift and add method that may be performed by an anti-circular rotation. A set of sequences to be multiplied may be considered as coefficients of polynomials in a ring. Therefore, the anti-circular rotation may be performed by feeding a sequence of a leading coefficient to an adder generating a constant coefficient. On the other hand, each of other sequences may be fed to an adder generating a coefficient of one higher degree.

Two exemplary cryptoprocessing logic circuits are also disclosed. A parallel cryptoprocessing logic circuit may include N shift registers and N adders, where N is a number of message bits. An exemplary parallel cryptoprocessing logic circuit may perform a multiplication and a summation in a parallel manner that may lead to a high-speed cryptoprocessing. A serial cryptoprocessing logic circuit may perform a multiplication and a summation in a serial manner. The serial cryptoprocessing logic circuit may include a single shift register and a single adder and may be optimized for resource-constrained devices.

FIG. 1Ashows a flowchart of a method for cryptoprocessing, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method100may include generating a public key (step102), generating a first ciphertext and a second ciphertext (step104), and generating a plurality of decrypted message bits (step106).FIG. 2shows a data flow diagram of a cryptoprocessing method, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, method100may facilitate establishing a secure connection between a first entity and a second entity utilizing a cryptoprocessing method. In an exemplary embodiment, a public key p may be generated in the first entity by step102. Next, an exemplary public key p may be sent to the second entity. In an exemplary embodiment, the second entity may then encrypt a message sequence by generating a first ciphertext f1and a second ciphertext c2and may send first ciphertext c1and second ciphertext c2to the first entity. Finally, the first entity may obtain a plurality of decrypted message bits m by decryption of first ciphertext c1and second ciphertext c2.

For further detail with respect to step102,FIG. 1Bshows a flowchart for generating a public key, consistent with one or more exemplary embodiments of the present disclosure. Referring toFIGS. 1B and 2, in an exemplary embodiment, generating public key p may include generating a temporary key r1and a private key r2(step108), generating a key generation product (step110), and obtaining public key p (step112). In an exemplary embodiment, temporary key r1and private key r2may be generated utilizing a processor. In an exemplary embodiment, temporary key r1may include a first plurality of bits. In an exemplary embodiment, each bit of the first plurality of bits may include a respective binary random variable. In an exemplary embodiment, private key r2may include a second plurality of bits. In an exemplary embodiment, each bit of the second plurality of bits may include a respective binary random variable. In an exemplary embodiment, a number of the second plurality of bits may be equal to a number of the first plurality of bits.

In an exemplary embodiment, the key generation product may be generated by multiplying private key r2by a public sequence a. In an exemplary embodiment, the key generation product may be generated utilizing a logic circuit. In an exemplary embodiment, public sequence a may include a plurality of public subsequences. In an exemplary embodiment, the key generation product may include a plurality of key generation sequences. In an exemplary embodiment, a number of the plurality of key generation sequences may be equal to a number of the first plurality of bits. In an exemplary embodiment, a number of the plurality of public subsequences may be equal to the number of the first plurality of bits. In an exemplary embodiment, each public subsequence of the plurality of public subsequences may include b bits and representing a decimal number in a range of

-⌊q2⌋⁢⁢and⁢⁢⌊q2⌋-1,
where q=2band b is a positive integer. In an exemplary embodiment, public key p may be obtained by subtracting the key generation product from temporary key r1. In an exemplary embodiment, public key p may be obtained utilizing the logic circuit. In an exemplary embodiment, public key p may include a plurality of public key sequences.

In further detail regarding step110,FIG. 1Cshows a first flowchart of generating a key generation product, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method110A may include a first implementation of step110.FIG. 3shows a schematic of a parallel cryptoprocessing logic circuit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, different steps of method100may be implemented utilizing a parallel cryptoprocessing logic circuit300. In an exemplary embodiment, generating the key generation product may include initializing a plurality of result sequences (step114) and generating an nthkey generation sequence of the plurality of key generation sequences (step116). In an exemplary embodiment, the plurality of result sequences may be initialized by storing a zero sequence in each of a plurality of shift registers302. In an exemplary embodiment, each shift register of a plurality of shift registers302may be associated with a respective result sequence of the plurality of result sequences. In an exemplary embodiment, each result sequence of the plurality of result sequences may be stored in a respective shift register. In an exemplary embodiment, the zero sequence may include the b bits, each bit of the zero sequence comprising a zero value.

For further detail with regards to step116, in an exemplary embodiment, the nthkey generation sequence may be generated by repeating a first iterative process for N times where N is the number of the first plurality of bits and n∈[0,N−1]. In an exemplary embodiment, the nthkey generation sequence may be obtained by multiplying public sequence a by private key r2. An exemplary nthkey generation sequence may be associated with an nthresult sequence res[n] of the plurality of result sequences. In an exemplary embodiment, nthresult sequence res[n] may include nthkey generation sequence when the first iterative process is performed. An exemplary ithiteration of the first iterative process, where 0≤i≤N−1, may include routing an ithprivate sequence r2[i] of a plurality of private sequences to an (n,1)thoutput304, routing an nthpublic subsequence a[n] of plurality of public subsequences to an (n,2)thoutput306, generating an nthAND gate output308by performing an AND operation on (n,1)thoutput304and (n,2)thoutput306, routing nthAND gate output308to an (n,3)thoutput310, generating a zeroth inverter output312by bit-wise inverting an (N−1)thresult sequence res[N−1] of the plurality of result sequences, routing zeroth inverter output312to a (0,4)thoutput314, routing a (j−1)thresult sequence res[j−1] of the plurality of result sequences to a (j,4)thoutput322, generating a zeroth adder output316by summing a (0,3)thoutput318, (0,4)thoutput314and a zeroth carry input320equal to 1, generating a jthadder output324by summing a (j,3)thoutput326, the (j,4)thoutput and a jthcarry input328equal to 0, and updating nthresult sequence res[n].

In an exemplary embodiment, the first iterative process may implement a shift and add method to obtain the nthkey generation sequence. When a modulus of a ring of polynomials is chosen to be 1+xN, the shift operation may be performed by an anti-circular rotation over a set of coefficients of polynomials. Each coefficient of polynomials in the ring may include a number in a range of

-⌊q2⌋⁢⁢and⁢⁢⌊q2⌋-1.
Therefore, the anti-circular operation may include a 2's complement of a coefficient of N−1 degree. In an exemplary embodiment, the first iterative process may perform the shift and add method for multiplying public sequence a by private key r2. In doing so, in an exemplary embodiment, a bit-wise inverted (N−1)thresult sequence res[N−1] may be fed to a zeroth adder with a carry input equal to 1 which may provide a 2's complement of an N−1 coefficient of the polynomial. Meanwhile, each result sequence of the plurality of result sequences (except (N−1)thresult sequence res[N−1]) may be fed to a next adder to complete the anti-circular rotation. Repeating this process for N times may implement the shift and add method, which provides the multiplication result.

In an exemplary embodiment, ithprivate sequence r2[i] may be routed to (n,1)thoutput304utilizing an (n,1)thmultiplexer330of a first plurality of multiplexers. In an exemplary embodiment, (n,1)thmultiplexer330may route ithprivate sequence r2[i] utilizing a first selector input331. In an exemplary embodiment, (n,1)thmultiplexer330may route ithprivate sequence r2[i] to (n,1)thoutput304responsive to a third control sequence S3loaded to first selector input331. In an exemplary embodiment, third control sequence S3may be equal to 1.

In an exemplary embodiment, ithprivate sequence r2[i] may include the b bits, each bit of ithprivate sequence r2[i] equal to an ithbit of the second plurality of bits. In an exemplary embodiment, nthpublic subsequence a[n] may be routed utilizing an (n,2)thmultiplexer332of a second plurality of multiplexers. In an exemplary embodiment, (n,2)thmultiplexer332may route nthpublic subsequence a[n] utilizing a second selector input333. In an exemplary embodiment, (n,2)thmultiplexer332may route nthpublic subsequence a[n] to (n,2)thoutput306responsive to a first control sequence S1loaded to second selector input333. In an exemplary embodiment, first control sequence S1may be equal to 00. In an exemplary embodiment, nthAND gate output308may be generated utilizing an nthAND gate334of a plurality of AND gates. In an exemplary embodiment, nthAND gate output308may be routed utilizing an (n,3)thmultiplexer336of a third plurality of multiplexers. In an exemplary embodiment, (n,3)thmultiplexer336may route nthAND gate output308utilizing a third selector input337. In an exemplary embodiment, (n,3)thmultiplexer336may route nthAND gate output308to (n,3)thoutput310responsive to a second control sequence S2loaded to third selector input337. In an exemplary embodiment, second control sequence S2may be equal to 010. In an exemplary embodiment, zeroth inverter output312may be bit-wise inverted utilizing a zeroth inverter338of a plurality of inverters. In an exemplary embodiment, zeroth inverter output312may be routed utilizing a (0,4)thmultiplexer340of a fourth plurality of multiplexers. In an exemplary embodiment, (0,4)thmultiplexer340may route zeroth inverter output312utilizing a fourth selector input341. In an exemplary embodiment, (0,4)thmultiplexer340may route zeroth inverter output312to (0,4)thoutput314responsive to a first element of a fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 0.

In an exemplary embodiment, (j−1)thresult sequence res[j−1] may be routed utilizing a (j,4)thmultiplexer342of the fourth plurality of multiplexers, where 1≤j≤N−1. In an exemplary embodiment (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] utilizing fourth selector input341. In an exemplary embodiment, (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] to (j,4)thoutput322responsive to a second element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the second element of fourth control sequence S4may be equal to 1. In an exemplary embodiment, zeroth adder output316may be generated utilizing a zeroth adder344of a plurality of adders. In an exemplary embodiment, jthadder output324may be generated utilizing a jthadder346of the plurality of adders. In an exemplary embodiment, nthresult sequence res[n] may be updated by storing an nthadder output348in an nthshift register350of plurality of shift registers302.

For further detail with regards to step112,FIG. 1Dshows a first flowchart of obtaining a public key sequence, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method112A may include a first implementation of step112. In an exemplary embodiment, different steps of method112A may be implemented utilizing parallel cryptoprocessing logic circuit300. In an exemplary embodiment, obtaining public key p may include obtaining an nthpublic key sequence p[n] of the plurality of public key sequences. In an exemplary embodiment, obtaining nthpublic key sequence p[n] may include routing an nthtemporary sequence r1[n] of a plurality of temporary sequences to (n,3)thoutput310(step118), updating zeroth inverter output312(step120), generating a jthinverter output352(step122), routing an nthinverter output354to an (n,4)thoutput356(step124), updating nthadder output348(step126), updating nthresult sequence res[n] (step128), and extracting nthpublic key sequence p[n] from nthshift register350(step130).

In an exemplary embodiment, nthtemporary sequence r1[n] may be routed to (n,3)thoutput310. In an exemplary embodiment, nthtemporary sequence r1[n] may be routed utilizing (n,3)thmultiplexer336. In an exemplary embodiment, (n,3)thmultiplexer336may route nthtemporary sequence r1[n] utilizing third selector input337. In an exemplary embodiment, (n,3)thmultiplexer336may route nthtemporary sequence r1[n] to (n,3)thoutput310responsive to a second control sequence S2loaded to third selector input337. In an exemplary embodiment, second control sequence S2may be equal to 001. An exemplary nthtemporary sequence r1[n] may include the b bits. In an exemplary embodiment, each bit of nthtemporary sequence r1[n] may be equal to an nthbit of the first plurality of bits. In an exemplary embodiment, zeroth inverter output312may be updated by bit-wise inverting (N−1)thresult sequence res[N−1]. In an exemplary embodiment, zeroth inverter output312may be bit-wise inverted utilizing zeroth inverter338. In an exemplary embodiment, jthinverter output352may be updated by bit-wise inverting (j−1)thresult sequence res[j−1]. In an exemplary embodiment, jthinverter output352may be bit-wise inverted utilizing a jthinverter358. In an exemplary embodiment, nthinverter output354may be routed utilizing an (n,4)thmultiplexer360of the fourth plurality of multiplexers. In an exemplary embodiment (n,4)thmultiplexer360may route nthinverter output354utilizing fourth selector input341. In an exemplary embodiment, (n,4)thmultiplexer360may route nthinverter output354to (n,4)thoutput356responsive to the second element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the second element of fourth control sequence S4may be equal to 1.

In an exemplary embodiment, nthadder output348may updated by summing (n,3)thoutput310, (n,4)thoutput356, and an nthcarry input362equal to 1. In an exemplary embodiment, nthadder output348may updated utilizing an nthadder364. In an exemplary embodiment, nthresult sequence res[n] may be updated by storing nthadder output348in nthshift register350. In an exemplary embodiment, nthpublic key p[n] may be extracted by routing nthresult sequence res[n] to an nthparallel output366of a plurality of parallel outputs368. In an exemplary embodiment, nthresult sequence res[n] may be routed to nthparallel output366utilizing an (n,5)thmultiplexer370of a fifth plurality of multiplexers372. In an exemplary embodiment, an (n,5)thmultiplexer370may route nthresult sequence res[n] to nthparallel output366utilizing a fifth selector input371. In an exemplary embodiment, an (n,5)thmultiplexer370may route nthresult sequence res[n] to nthparallel output366responsive to a sixth control sequence S6loaded to fifth selector input371. In an exemplary embodiment, sixth control sequence S6may be equal to 0.

FIG. 3Ashows a parallel key generation logic circuit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, a parallel key generation logic circuit300A may include a first implementation of parallel cryptoprocessing logic circuit300. In an exemplary embodiment, different steps of method102may be implemented utilizing parallel key generation logic circuit300A. In an exemplary embodiment, ithprivate sequence r2[i] may be routed to (n,1)thoutput304utilizing a direct connection. In other words, in an exemplary embodiment, ithprivate sequence r2[i] may be directly connected to (n,1)thoutput304. In an exemplary embodiment, nthpublic subsequence a[n] may be routed to (n,2)thoutput306utilizing a direct connection. In an exemplary embodiment, zeroth inverter output312may be routed to (0,4)thoutput314utilizing a direct connection. In an exemplary embodiment, nthresult sequence res[n] may be routed to nthparallel output366utilizing a direct connection.

FIG. 1Eshows a flowchart of generating a first ciphertext and a second ciphertext, consistent with one or more exemplary embodiments of the present disclosure. Referring toFIG. 2, in an exemplary embodiment, step104may include an encryption of the message sequence by the second entity. An exemplary first ciphertext c1may include a plurality of first ciphertext sequences. An exemplary second ciphertext c2may include a plurality of second ciphertext sequences. In an exemplary embodiment, generating first ciphertext c1and second ciphertext c2may include generating a first random key e1, a second random key e2, and a third random key e3(step132), generating an nthfirst ciphertext sequence c1[n] of the plurality of first ciphertext sequences (step134), and generating an nthsecond ciphertext sequence of the plurality of second ciphertext sequences (step136).

In an exemplary embodiment, step132may be performed utilizing the processor. An exemplary first random key e1may include a first plurality of random bits. An exemplary second random key e2may include a second plurality of random bits. An exemplary third random key e3may include a third plurality of random bits. In an exemplary embodiment, each random bit of the first plurality of random bits, the second plurality of random bits, and the third plurality of random bits may include a respective binary random variable. In an exemplary embodiment, a number of the first plurality of random bits, a number of the second plurality of random bits, and a number of the third plurality of random bits may be equal to N.

In further detail with regards to step134,FIG. 1Fshows a first flowchart of generating a first ciphertext sequence, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method134A may include a first implementation of step134. Referring toFIGS. 1F and 3, in an exemplary embodiment, generating nthfirst ciphertext sequence c1[n] may include initializing the plurality of result sequences (step138), generating an nthfirst encryption sequence of a plurality of first encryption sequences (step140), routing an nthsecond random sequence of a plurality of second random sequences to (n,3)thoutput310(step142), routing (N−1)thresult sequence res[N−1] to (0,4)thoutput314(step144), routing (j−1)thresult sequence res[j−1] to (j,4)thoutput322(step146), updating nthadder output348(step148), updating nthresult sequence res[n] (step150), and extracting nthfirst ciphertext sequence c1[n] from nthshift register350(step152). In an exemplary embodiment, nthfirst ciphertext sequence c1[n] may be associated with nthresult sequence res[n]. In an exemplary embodiment, nthresult sequence res[n] may include the nthfirst ciphertext sequence c1[n] after performing step134.

In an exemplary embodiment, the plurality of result sequences may be initialized by storing the zero sequence in each of the plurality of shift registers. An exemplary nthfirst encryption sequence may be associated with nthresult sequence res[n]. In an exemplary embodiment, the plurality of first encryption sequences may include a multiplication result of public sequence a and first random key e1, i.e., a first encryption product ae1. An exemplary first encryption product ae1may include the plurality of first encryption sequences. As a result, nthresult sequence res[n] may include the nthfirst encryption sequence after performing step140. In an exemplary embodiment, a number of the plurality of first encryption sequences may be equal to N.

In an exemplary embodiment, generating the nthfirst encryption sequence may include repeating a second iterative process for N times. An exemplary ithiteration of the second iterative process may include routing an ithfirst random sequence e1[i] of a plurality of first random sequences to (n,1)thoutput304, routing nthpublic subsequence a[n] to (n,2)thoutput306, updating nthAND gate output308, routing nthAND gate output308to (n,3)thoutput310, updating zeroth inverter output312, routing zeroth inverter output312to (0,4)thoutput314, routing (j−1)thresult sequence res[j−1] to (j,4)thoutput322, updating zeroth adder output316, updating jthadder output324, updating nthresult sequence res[n].

In an exemplary embodiment, ithfirst random sequence e1[i] may be routed to (n,1)thoutput304utilizing (n,1)thmultiplexer330. In an exemplary embodiment, (n,1)thmultiplexer330may route ithfirst random sequence e1[i] utilizing first selector input331. In an exemplary embodiment, (n,1)thmultiplexer330may route ithfirst random sequence e1[i] to (n,1)thoutput304responsive to third control sequence S3loaded to first selector input331. In an exemplary embodiment, third control sequence S3may be equal to 0. An exemplary ithfirst random sequence e1[i] may include the b bits. In an exemplary embodiment, each bit of ithfirst random sequence e1[i] may be equal to an ithrandom bit of the first plurality of random bits. An exemplary nthpublic subsequence a[n] may be routed to (n,2)thoutput306utilizing (n,2)thmultiplexer332. In an exemplary embodiment, (n,2)thmultiplexer332may route nthpublic subsequence a[n] utilizing second selector input333. In an exemplary embodiment, (n,2)thmultiplexer332may route nthpublic subsequence a[n] to (n,2)thoutput306responsive to a first control sequence S1loaded to second selector input333. In an exemplary embodiment, first control sequence S1may be equal to 00.

In an exemplary embodiment, nthAND gate output308may be updated by performing an AND operation on the (n,1)thoutput and the (n,2)thoutput. In an exemplary embodiment, nthAND gate output308may be updated utilizing nthAND gate334. An exemplary nthAND gate output308may be routed to (n,3)thoutput310utilizing (n,3)thmultiplexer336. In an exemplary embodiment, (n,3)thmultiplexer336may route nthAND gate output308utilizing third selector input337. In an exemplary embodiment, (n,3)thmultiplexer336may route nthAND gate output308to (n,3)thoutput310responsive to a second control sequence S2loaded to third selector input337. In an exemplary embodiment, second control sequence S2may be equal to 010. In an exemplary embodiment, zeroth inverter output312may be updated by bit-wise inverting (N−1)thresult sequence res[N−1]. In an exemplary embodiment, zeroth inverter output312may be updated utilizing zeroth inverter338.

In an exemplary embodiment, zeroth inverter output312may be routed to (0,4)thoutput314utilizing (0,4)thmultiplexer340. In an exemplary embodiment, (0,4)thmultiplexer340may route zeroth inverter output312utilizing fourth selector input341. In an exemplary embodiment, (0,4)thmultiplexer340may route zeroth inverter output312to (0,4)thoutput314responsive to the first element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 0. In an exemplary embodiment, (j−1)thresult sequence res[j−1] may be routed to (j,4)thoutput322utilizing (j,4)thmultiplexer342. In an exemplary embodiment (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] utilizing fourth selector input341. In an exemplary embodiment, (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] to (j,4)thoutput322responsive to the second element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the second element of fourth control sequence S4may be equal to 1. In an exemplary embodiment, zeroth adder output316may be updated by summing (0,3)thoutput318, (0,4)thoutput314, and zeroth carry input320equal to 1. In an exemplary embodiment, zeroth adder output316may be updated utilizing zeroth adder344. In an exemplary embodiment, jthadder output324may be updated by summing (j,3)thoutput326, (j,4)thoutput322, and jthcarry input328to 0. In an exemplary embodiment, jthadder output324may be updated utilizing jthadder346. In an exemplary embodiment, nthresult sequence res[n] may be updated by storing nthadder output348in nthshift register350.

In an exemplary embodiment, first ciphertext c1may be obtained by summing first encryption product ae1and second random key e2. In an exemplary embodiment, steps142-150of method134A may be performed to generate first ciphertext c1by summing first encryption product ae1and second random key e2. In an exemplary embodiment, nthsecond random sequence e2[n] may be routed to (n,3)thoutput310utilizing (n,3)thmultiplexer336. In an exemplary embodiment, (n,3)thmultiplexer336may route nthsecond random sequence e2[n] utilizing third selector input337. In an exemplary embodiment, (n,3)thmultiplexer336may route nthsecond random sequence e2[n] to (n,3)thoutput310responsive to a second control sequence S2loaded to third selector input337. In an exemplary embodiment, second control sequence S2may be equal to 011. In an exemplary embodiment, each second random sequence of the plurality of second random sequences may include the b bits. In an exemplary embodiment, each bit of the nthsecond random sequence may be equal to an nthbit of the second plurality of random bits.

In an exemplary embodiment, (N−1)thresult sequence res[N−1] may be routed to (0,4)thoutput314utilizing the (0,4)thmultiplexer. In an exemplary embodiment, (0,4)thmultiplexer340may route (N−1)thresult sequence res[N−1] utilizing fourth selector input341. In an exemplary embodiment, (0,4)thmultiplexer340may route (N−1)thresult sequence res[N−1] to (0,4)thoutput314responsive to the first element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1. In an exemplary embodiment, (j−1)thresult sequence res[j−1] may be routed to (j,4)thoutput322utilizing (j,4)thmultiplexer342. In an exemplary embodiment (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] utilizing fourth selector input341. In an exemplary embodiment, (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] to (j,4)thoutput322responsive to the second element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the second element of fourth control sequence S4may be equal to 1.

In an exemplary embodiment, nthadder output348may be updated by summing (n,3)thoutput310, (n,4)thoutput356, and nthcarry input362equal to 0. In an exemplary embodiment, nthadder output348may be updated utilizing nthadder364. In an exemplary embodiment, nthresult sequence res[n] may be updated by storing nthadder output348in nthshift register350. In an exemplary embodiment, nthfirst ciphertext sequence c1[n] may be extracted by routing nthresult sequence res[n] to nthparallel output366. In an exemplary embodiment, nthfirst ciphertext sequence c1[n] may be extracted utilizing an (n,5)thmultiplexer370. In an exemplary embodiment, an (n,5)thmultiplexer370may route nthresult sequence res[n] to nthparallel output366utilizing fifth selector input371. In an exemplary embodiment, an (n,5)thmultiplexer370may route nthresult sequence res[n] to nthparallel output366responsive to sixth control sequence S6loaded to fifth selector input371. In an exemplary embodiment, sixth control sequence S6may be equal to 0.

For further detail with respect to step136,FIG. 1Gshows a first flowchart of generating a second ciphertext sequence, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method136A may include a first implementation of step136. Referring toFIGS. 1G and 3, in an exemplary embodiment, generating nthsecond ciphertext sequence c2[n] may include initializing the plurality of result sequences (step154), generating an nthsecond encryption sequence of a plurality of second encryption sequences (step156), routing an nththird random sequence of a plurality of third random sequences to (n,3)thoutput310(step158), routing (N−1)thresult sequence res[N−1] to (0,4)thoutput314(step160), routing (j−1)thresult sequence res[j−1] to (j,4)thoutput322(step162), updating nthadder output348(step164), updating nthresult sequence res[n] (step166), obtaining, a plurality of message bits (step168), generating an nthmessage sequence m[n] of a plurality of message sequences (step170), routing nthmessage sequence m[n] to (n,3)thoutput310(step172), routing (N−1)thresult sequence res[N−1] to (0,4)thoutput314(step174), routing (j−1)thresult sequence res[j−1] to (j,4)thoutput322(step176), updating nthadder output348(step178), updating nthresult sequence res[n] (step180), extracting nthsecond ciphertext sequence c2[n] from nthshift register350(step182). In an exemplary embodiment, nthsecond ciphertext sequence c2[n] may be associated with nthresult sequence res[n]. In an exemplary embodiment, nthresult sequence res[n] may include nthsecond ciphertext sequence c2[n] after performing step136.

In an exemplary embodiment, the plurality of result sequences may be initialized by storing the zero sequence in each of the plurality of shift registers. An exemplary nthsecond encryption sequence may be associated with nthresult sequence res[n]. In an exemplary embodiment, the plurality of second encryption sequences may include a multiplication result of public key sequence p and first random key e1, i.e., a second encryption product pe1. An exemplary second encryption product may include the plurality of second encryption sequences. As a result, nthresult sequence res[n] may include the nthsecond encryption sequence after performing step156. In an exemplary embodiment, a number of the plurality of second encryption sequences may be equal to N.

In an exemplary embodiment, generating the nthsecond encryption sequence may include repeating a third iterative process for N times. An exemplary ithiteration of the third iterative process may include routing an ithfirst random sequence e1[i] of a plurality of first random sequences to (n,1)thoutput304, routing nthpublic key sequence p[n] to (n,2)thoutput306, updating nthAND gate output308, routing nthAND gate output308to (n,3)thoutput310, updating zeroth inverter output312, routing zeroth inverter output312to (0,4)thoutput314, routing (j−1)thresult sequence res[j−1] to (j,4)thoutput322, updating zeroth adder output316, updating jthadder output324, updating nthresult sequence res[n].

In an exemplary embodiment, ithfirst random sequence e1[i] may be routed to (n,1)thoutput304utilizing (n,1)thmultiplexer330. In an exemplary embodiment, (n,1)thmultiplexer330may route ithfirst random sequence e1[i] utilizing first selector input331. In an exemplary embodiment, (n,1)thmultiplexer330may route ithfirst random sequence e1[i] to (n,1)thoutput304responsive to third control sequence S3loaded to first selector input331. In an exemplary embodiment, third control sequence S3may be equal to 0. An exemplary ithfirst random sequence e1[i] may include the b bits. In an exemplary embodiment, each bit of ithfirst random sequence e1[i] may be equal to an ithrandom bit of the first plurality of random bits. An exemplary nthpublic key sequence p[n] may be routed to (n,2)thoutput306utilizing (n,2)thmultiplexer332. In an exemplary embodiment, (n,2)thmultiplexer332may route nthpublic key sequence p[n] utilizing second selector input333. In an exemplary embodiment, (n,2)thmultiplexer332may route nthpublic key sequence p[n] to (n,2)thoutput306responsive to first control sequence S1loaded to second selector input333. In an exemplary embodiment, first control sequence may be equal to 01.

In an exemplary embodiment, nthAND gate output308may be updated by performing an AND operation on the (n,1)thoutput and the (n,2)thoutput. In an exemplary embodiment, nthAND gate output308may be updated utilizing nthAND gate334. An exemplary nthAND gate output308may be routed to (n,3)thoutput310utilizing (n,3)thmultiplexer336. In an exemplary embodiment, (n,3)thmultiplexer336may route nthAND gate output308utilizing third selector input337. In an exemplary embodiment, (n,3)thmultiplexer336may route nthAND gate output308to (n,3)thoutput310responsive to a second control sequence S2loaded to third selector input337. In an exemplary embodiment, second control sequence S2may be equal to 010. In an exemplary embodiment, zeroth inverter output312may be updated by bit-wise inverting (N−1)thresult sequence res[N−1]. In an exemplary embodiment, zeroth inverter output312may be updated utilizing zeroth inverter338. In an exemplary embodiment, zeroth inverter output312may be routed to (0,4)thoutput314utilizing (0,4)thmultiplexer340. In an exemplary embodiment, (0,4)thmultiplexer340may route zeroth inverter output312utilizing a fourth selector input341. In an exemplary embodiment, (0,4)thmultiplexer340may route zeroth inverter output312to (0,4)thoutput314responsive to the first element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 0. In an exemplary embodiment, (j−1)thresult sequence res[j−1] may be routed to (j,4)thoutput322utilizing (j,4)thmultiplexer342. In an exemplary embodiment (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] utilizing fourth selector input341. In an exemplary embodiment, (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] to (j,4)thoutput322responsive to the second element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the second element of fourth control sequence S4may be equal to 1.

In an exemplary embodiment, zeroth adder output316may be updated by summing (0,3)thoutput318, (0,4)thoutput314, and zeroth carry input320equal to 1. In an exemplary embodiment, zeroth adder output316may be updated utilizing zeroth adder344. In an exemplary embodiment, jthadder output324may be updated by summing (j,3)thoutput326, (j,4)thoutput322, and jthcarry input328to 0. In an exemplary embodiment, jthadder output324may be updated utilizing jthadder346. In an exemplary embodiment, nthresult sequence res[n] may be updated by storing nthadder output348in nthshift register350.

Referring again toFIG. 2, in an exemplary embodiment, second ciphertext c2may be obtained by summing second encryption product pe1and third random key e3. In an exemplary embodiment, steps148-166may be performed to generate first ciphertext c2by summing second encryption product pe1and third random key e3. In an exemplary embodiment, nththird random sequence e3[n] may be routed to (n,3)thoutput310utilizing (n,3)thmultiplexer336. In an exemplary embodiment, (n,3)thmultiplexer336may route nththird random sequence e3[n] utilizing third selector input337. In an exemplary embodiment, (n,3)thmultiplexer336may route nththird random sequence e3[n] to (n,3)thoutput310responsive to a second control sequence S2loaded to third selector input337. In an exemplary embodiment, second control sequence S2may be equal to 100.

In an exemplary embodiment, each third random sequence of the plurality of third random sequences may include the b bits. In an exemplary embodiment, each bit of the nththird random sequence may be equal to an nthbit of the second plurality of random bits. In an exemplary embodiment, nthmessage sequence m[n] may be routed to (n,3)thoutput310utilizing (n,3)thmultiplexer336. In an exemplary embodiment, (n,3)thmultiplexer336may route nthmessage sequence m[n] utilizing third selector input337. In an exemplary embodiment, (n,3)thmultiplexer336may route nthmessage sequence m[n] to (n,3)thoutput310responsive to a second control sequence S2loaded to third selector input337. In an exemplary embodiment, second control sequence S2may be equal to 101.

In an exemplary embodiment, (N−1)thresult sequence res[N−1] may be routed to (0,4)thoutput314utilizing (0,4)thmultiplexer. In an exemplary embodiment, (0,4)thmultiplexer340may route (N−1)thresult sequence res[N−1] utilizing fourth selector input341. In an exemplary embodiment, (0,4)thmultiplexer340may route (N−1)thresult sequence res[N−1] to (0,4)thoutput314responsive to the first element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1. In an exemplary embodiment, (j−1)thresult sequence res[j−1] may be routed to (j,4)thoutput322utilizing (j,4)thmultiplexer342. In an exemplary embodiment (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] utilizing fourth selector input341. In an exemplary embodiment, (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] to (j,4)thoutput322responsive to the second element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the second element of fourth control sequence S4may be equal to 1. In an exemplary embodiment, nthadder output348may be updated by summing (n,3)thoutput310, (n,4)thoutput356, and nthcarry input362equal to 0. In an exemplary embodiment, nthadder output348may be updated utilizing nthadder364. In an exemplary embodiment, nthresult sequence res[n] may be updated by storing nthadder output348in nthshift register350.

In an exemplary embodiment, the plurality of message bits may be obtained utilizing the processor. In an exemplary embodiment, nthmessage sequence m[n] may be generated by the processor. In an exemplary embodiment, nthmessage sequence m[n] may include the b bits. In an exemplary embodiment, generating nthmessage sequence m[n] may include setting nthmessage sequence m[n] to a binary value of a decimal number equal to

-⌊q2⌋
responsive to an nthmessage bit of the plurality of message bits equal to 1. In an exemplary embodiment, generating nthmessage sequencem [n] may further include setting nthmessage sequencem [n] to the zero sequence responsive to the nthmessage bit equal to 0.

In an exemplary embodiment, nthsecond ciphertext sequence c2[n] may be extracted from nthshift register350by routing nthresult sequence res[n] to nthparallel output366. In an exemplary embodiment, nthresult sequence res[n] may be routed to nthparallel output366utilizing an (n,5)thmultiplexer370. In an exemplary embodiment, an (n,5)thmultiplexer370may route nthresult sequence res[n] to nthparallel output366utilizing fifth selector input371. In an exemplary embodiment, an (n,5)thmultiplexer370may route nthresult sequence res[n] to nthparallel output366responsive to sixth control sequence S6loaded to fifth selector input371. In an exemplary embodiment, sixth control sequence S6may be equal to 0.

FIG. 3Bshows a parallel encryption logic circuit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, a parallel encryption logic circuit300B may include a second implementation of parallel cryptoprocessing logic circuit300. In an exemplary embodiment, different steps of method104may be implemented utilizing parallel encryption logic circuit300B. In an exemplary embodiment, ithfirst random sequence e1[i] may be routed to (n,1)thoutput304utilizing a direct connection. In other words, in an exemplary embodiment, ithfirst random sequence e1[i] may be directly connected to (n,1)thoutput304. In an exemplary embodiment, (j−1)thresult sequence res[j−1] may be routed to (j,4)thoutput322utilizing a direct connection. In an exemplary embodiment, nthresult sequence res[n] may be routed to nthparallel output366utilizing a direct connection.

In further detail with regards to step106,FIG. 1Hshows a first flowchart of generating a plurality of decrypted message bits, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method106A may include a first implementation of step106. Referring toFIGS. 1H and 3, in an exemplary embodiment, generating a plurality of decrypted message bits may include initializing the plurality of result sequences (step184), generating an nthdecryption sequence of a plurality of decryption sequences (step186), routing nthsecond ciphertext c2[n] to (n,3)thoutput310(step188), routing (N−1)thresult sequence res[N−1] to (0,4)thoutput314(step190), routing (j−1)thresult sequence res[j−1] to (j,4)thoutput322(step192), updating nthadder output348(step194), updating nthresult sequence res[n] (step196), generating an nthXOR gate output374(step198), and extracting nthdecrypted message bit (step199).

In an exemplary embodiment, the plurality of result sequences may be initialized by storing the zero sequence in each of the plurality of shift registers. An exemplary nthdecryption sequence may be associated with nthresult sequence res[n]. In an exemplary embodiment, the plurality of decryption sequences may include a multiplication result of first ciphertext c1and private key r2, i.e., a decryption product c1r2. An exemplary decryption product c1r2may include the plurality of decryption sequences. As a result, nthresult sequence res[n] may include the nthdecryption sequence after performing step186. In an exemplary embodiment, a number of the plurality of decryption sequences may be equal to N.

In an exemplary embodiment, generating the nthdecryption sequence may include repeating a fourth iterative process for N times. An exemplary ithiteration of the fourth iterative process may include routing ithprivate sequence r2[i] to (n,1)thoutput304, routing nthfirst ciphertext sequence c1[n] to (n,2)thoutput306, updating nthAND gate output308, routing nthAND gate output308to (n,3)thoutput310, updating zeroth inverter output312, routing zeroth inverter output312to (0,4)thoutput314, routing (j−1)thresult sequence res[j−1] to (j,4)thoutput322, updating zeroth adder output316, updating jthadder output324, updating nthresult sequence res[n].

In an exemplary embodiment, ithprivate sequence r2[i] may be routed to (n,1)thoutput304utilizing (n,1)thmultiplexer330. In an exemplary embodiment, (n,1)thmultiplexer330may route ithfirst random sequence r2[i] utilizing first selector input331. In an exemplary embodiment, (n,1)thmultiplexer330may route ithprivate sequence r2[i] to (n,1)thoutput304responsive to third control sequence S3loaded to first selector input331. In an exemplary embodiment, third control sequence S3may be equal to 1. An exemplary nthfirst ciphertext sequence c1[n] may be routed to (n,2)thoutput306utilizing (n,2)thmultiplexer332. In an exemplary embodiment, (n,2)thmultiplexer332may route nthfirst ciphertext sequence c1[n] utilizing second selector input333. In an exemplary embodiment, (n,2)thmultiplexer332may route nthfirst ciphertext sequence c1[n] to (n,2)thoutput306responsive to first control sequence S1loaded to second selector input333. In an exemplary embodiment, first control sequence S1may be equal to 10.

In an exemplary embodiment, nthAND gate output308may be updated by performing an AND operation on the (n,1)thoutput and the (n,2)thoutput. In an exemplary embodiment, nthAND gate output308may be updated utilizing nthAND gate334. An exemplary nthAND gate output308may be routed to (n,3)thoutput310utilizing (n,3)thmultiplexer336. In an exemplary embodiment, (n,3)thmultiplexer336may route nthAND gate output308utilizing third selector input337. In an exemplary embodiment, (n,3)thmultiplexer336may route nthAND gate output308to (n,3)thoutput310responsive to a second control sequence S2loaded to third selector input337. In an exemplary embodiment, second control sequence S2may be equal to 010. In an exemplary embodiment, zeroth inverter output312may be updated by bit-wise inverting (N−1)thresult sequence res[N−1]. In an exemplary embodiment, zeroth inverter output312may be updated utilizing zeroth inverter338.

In an exemplary embodiment, zeroth inverter output312may be routed to (0,4)thoutput314utilizing (0,4)thmultiplexer340. In an exemplary embodiment, (0,4)thmultiplexer340may route zeroth inverter output312utilizing fourth selector input341. In an exemplary embodiment, (0,4)thmultiplexer340may route zeroth inverter output312to (0,4)thoutput314responsive to the first element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 0. In an exemplary embodiment, (j−1)thresult sequence may be routed to (j,4)thoutput322utilizing (j,4)thmultiplexer342. In an exemplary embodiment (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] utilizing fourth selector input341. In an exemplary embodiment, (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] to (j,4)thoutput322responsive to the second element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the second element of fourth control sequence S4may be equal to 1.

In an exemplary embodiment, zeroth adder output316may be updated by summing (0,3)thoutput318, (0,4)thoutput314, and zeroth carry input320equal to 1. In an exemplary embodiment, zeroth adder output316may be updated utilizing zeroth adder344. In an exemplary embodiment, jthadder output324may be updated by summing (j,3)thoutput326, (j,4)thoutput322, and jthcarry input328to 0. In an exemplary embodiment, jthadder output324may be updated utilizing jthadder346. In an exemplary embodiment, nthresult sequence res[n] may be updated by storing nthadder output348in nthshift register350.

In an exemplary embodiment, the plurality of decrypted message bits may be obtained by summing decryption product c1r2and second ciphertext c2. In an exemplary embodiment, steps188-196may be performed to generate the plurality of decrypted message bits by summing decryption product c1r2and second ciphertext c2. In an exemplary embodiment, nthsecond ciphertext sequence c2[n] may be routed to (n,3)thoutput310utilizing (n,3)thmultiplexer336. In an exemplary embodiment, (n,3)thmultiplexer336may route nthsecond ciphertext sequence c2[n] utilizing third selector input337. In an exemplary embodiment, (n,3)thmultiplexer336may route nthsecond ciphertext sequence c2[n] to (n,3)thoutput310responsive to a second control sequence S2loaded to third selector input337. In an exemplary embodiment, second control sequence S2may be equal to 000.

In an exemplary embodiment, (N−1)thresult sequence res[N−1] may be routed to (0,4)thoutput314utilizing the (0,4)thmultiplexer. In an exemplary embodiment, (0,4)thmultiplexer340may route (N−1)thresult sequence res[N−1] utilizing fourth selector input341. In an exemplary embodiment, (0,4)thmultiplexer340may route (N−1)thresult sequence res[N−1] to (0,4)thoutput314responsive to the first element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1. In an exemplary embodiment, (j−1)thresult sequence res[j−1] may be routed to (j,4)thoutput322utilizing (j,4)thmultiplexer342. In an exemplary embodiment (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] utilizing fourth selector input341. In an exemplary embodiment, (j,4)thmultiplexer342may route (j−1)thresult sequence res[j−1] to (j,4)thoutput322responsive to the second element of fourth control sequence S4loaded to fourth selector input341. In an exemplary embodiment, the second element of fourth control sequence S4may be equal to 1.

In an exemplary embodiment, nthadder output348may be updated by summing (n,3)thoutput310, (n,4)thoutput356, and nthcarry input362equal to 0. In an exemplary embodiment, nthadder output348may be updated utilizing nthadder364. In an exemplary embodiment, nthresult sequence res[n] may be updated by storing nthadder output348in nthshift register350. In an exemplary embodiment, nthXOR gate output374may be generated by performing an XOR operation on two most significant bits of nthshift register350. In an exemplary embodiment, nthXOR gate output374may be generated utilizing an nthXOR gate376of a plurality of XOR gates. In an exemplary embodiment, the nthdecrypted message bit may be extracted by routing nthXOR gate output374to nthparallel output366. In an exemplary embodiment, nthdecrypted message bit may be extracted utilizing an (n,5)thmultiplexer370. In an exemplary embodiment, an (n,5)thmultiplexer370may route nthXOR gate output374to nthparallel output366utilizing fifth selector input371. In an exemplary embodiment, an (n,5)thmultiplexer370may route nthXOR gate output374to nthparallel output366responsive to sixth control sequence S6loaded to fifth selector input371. In an exemplary embodiment, sixth control sequence S6may be equal to 1.

FIG. 3Cshows a parallel decryption logic circuit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, a parallel decryption logic circuit300C may include a third implementation of parallel cryptoprocessing logic circuit300. In an exemplary embodiment, different steps of method106may be implemented utilizing parallel decryption logic circuit300C. In an exemplary embodiment, ithprivate sequence r2[i] may be routed to (n,1)thoutput304utilizing a direct connection. In other words, in an exemplary embodiment, ithprivate sequence r2[i] may be directly connected to (n,1)thoutput304. In an exemplary embodiment, nthfirst ciphertext sequence c1[n] may be routed to (n,2)thoutput306utilizing a direct connection. In an exemplary embodiment, (j−1)thresult sequence res[j−1] may be routed to (j,4)thoutput322utilizing a direct connection. In an exemplary embodiment, nthresult sequence res[n] may be routed to nthparallel output366utilizing a direct connection.

In further details regarding to step110,FIG. 1Ishows a second flowchart of generating a key generation product, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method110B may include a second implementation of step110.FIG. 4shows a schematic of a serial cryptoprocessing logic circuit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, different steps of method100may be implemented utilizing a serial cryptoprocessing logic circuit400. In an exemplary embodiment, generating the key generation product may include initializing a serial result sequence Res (step111) and generating the nthkey generation sequence (step113). In an exemplary embodiment, serial result sequence Res may be initialized by storing the zero sequence in a serial shift register402. In an exemplary embodiment, serial shift register402may be associated with serial result sequence Res. In an exemplary embodiment, serial result sequence Res may be stored in serial shift register402.

For further details with regards to step113, in an exemplary embodiment, the nthkey generation sequence may be generated by repeating a first serial iterative process for N times. In an exemplary embodiment, the nthkey generation sequence may be obtained by multiplying public sequence a by private key r2. An exemplary nthkey generation sequence may be associated with serial result sequence Res. In an exemplary embodiment, serial result sequence Res may include nthkey generation sequence when the first serial iterative process is performed. An exemplary ithiteration of the first iterative process, where 0≤i≤N−1, may include routing an ithpublic subsequence a[i] of the plurality of public subsequences to a first public output404, generating a selector bit SL, routing first public output404to a second public output406, generating a public inverter output408by bit-wise inverting first public output404, routing public inverter output408to second public output406, routing second public output406to a first serial output410, routing ithprivate sequence r2[i] to a second serial output412, generating a serial AND gate output414, routing serial AND gate output414to a third serial output416, routing serial result sequence Res to a fourth serial output418, generating a serial adder output420, updating serial result sequence Res.

In an exemplary embodiment, ithprivate sequence r2[i] may be extracted from a private key shift register419. In an exemplary embodiment, ithpublic subsequence a[i] may be routed to first public output404utilizing a first public multiplexer422. In an exemplary embodiment, first public multiplexer422may route ithpublic subsequence a[i] to first public output404utilizing a first public selector input417. In an exemplary embodiment, first public multiplexer422may route ithpublic subsequence a[i] to first public output404responsive to a first counter output421loaded to first public selector input417. In an exemplary embodiment, first counter output421may be equal to i. In an exemplary embodiment, first counter output421may be generated by first counter423. An exemplary first counter423may count from 0 to N−1.

An exemplary selector bit SL may be generated utilizing a comparator424. An exemplary comparator424may compare first counter output421and a second counter output425. In an exemplary embodiment, second counter output425may be generated utilizing a second counter427. In an exemplary embodiment, first counter output421may be equal to i. In an exemplary embodiment, second counter output425may be equal to n. An exemplary selector bit SL may be generated by setting selector bit SL to 1 responsive to n larger than or equal to i. An exemplary selector bit SL may be generated by setting selector bit SL to 0 responsive to n smaller than i. An exemplary first public output404may be routed to second public output406utilizing a second public multiplexer426responsive to selector bit SL equal to 1. An exemplary public inverter output408may be generated utilizing a public inverter428responsive to selector bit SL equal 0. An exemplary public inverter output408may be routed to second public output406utilizing second public multiplexer426responsive to selector bit SL equal to 0.

An exemplary second public output406may be routed to first serial output410utilizing a first serial multiplexer430. In an exemplary embodiment, first serial multiplexer430may route second public output406to first serial output410responsive to first control sequence S1loaded to a first serial selector input431. In an exemplary embodiment, first control sequence S1may be equal to 00. An exemplary ithprivate sequence r2[i] may be routed to second serial output412utilizing a second serial multiplexer432. In an exemplary embodiment, second serial multiplexer432may route ithprivate sequence r2[i] to second serial output412responsive to third control sequence S3loaded to a second serial selector input433. In an exemplary embodiment, third control sequence S3may be equal to 1.

An exemplary serial AND gate output414may be generated by performing an AND operation on first serial output410and second serial output412. An exemplary serial AND gate output414may be generated utilizing a serial AND gate434. An exemplary serial AND gate output414may be routed to third serial output416utilizing a third serial multiplexer436. In an exemplary embodiment, third serial multiplexer436may route serial AND gate output414to third serial output416responsive to second control sequence S2loaded to a third serial selector input435. In an exemplary embodiment, second control sequence S2may be equal to 010. An exemplary serial result sequence Res may be routed to fourth serial output418utilizing a fourth serial multiplexer438. In an exemplary embodiment, fourth serial multiplexer438may route serial result sequence Res to fourth serial output418responsive to the first element of fourth control sequence S4loaded to fourth serial selector input439. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1.

An exemplary serial adder output420may be generated by generating a selector inverter output440and obtaining serial adder output420. An exemplary selector inverter output440may be generated by inverting selector bit SL utilizing a selector inverter442. An exemplary serial adder output420may be obtained by summing third serial output416, fourth serial output418, and selector inverter output440utilizing a serial adder444. An exemplary serial adder output420may be updated by storing serial adder output420in serial shift register402.

For further detail with regards to step112,FIG. 1Jshows a second flowchart of obtaining a public key sequence, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method112B may include a second implementation of step112. In an exemplary embodiment, different steps of method112B may be implemented utilizing serial cryptoprocessing logic circuit400. In an exemplary embodiment, obtaining public key p may include obtaining nthpublic key sequence p[n]. In an exemplary embodiment, obtaining nthpublic key sequence p[n] may include routing nthtemporary sequence r1[n] to third serial output416(step115), generating a serial inverter output446(step117), routing serial inverter output446to fourth serial output418(step119), updating serial adder output420(step121), updating the serial result sequence Res (step123), and extracting nthpublic key sequence p[n] from serial shift register402(step125).

An exemplary nthtemporary sequence r1[n] may be extracted from a temporary key shift register447. An exemplary nthtemporary sequence r1[n] may be routed to third serial output416utilizing third serial multiplexer436. In an exemplary embodiment, third serial multiplexer436may route nthtemporary sequence r1[n] to third serial output416responsive to second control sequence S2loaded to third serial selector input435. In an exemplary embodiment, second control sequence S2may be equal to 001. An exemplary serial inverter output446may be generated by bit-wise inverting serial result sequence Res. An exemplary serial inverter output446may be generated utilizing a serial inverter448. An exemplary serial inverter output446may be routed to fourth serial output418utilizing fourth serial multiplexer438. In an exemplary embodiment, fourth serial multiplexer438may route selector inverter output440to fourth serial output418responsive to the first element of fourth control sequence S4loaded to fourth serial selector input439. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 0. An exemplary serial adder output420may be updated by summing third serial output416, fourth serial output418, and a serial carry input450equal to 1.

In an exemplary embodiment, a fifth serial multiplexer451may route one of selector inverter output440and a selector control bit Sel to serial carry input450responsive to a second element of fourth control sequence S4loaded to fifth serial selector input453. In an exemplary embodiment, fifth serial multiplexer451may route selector inverter output440to serial carry input450responsive to the second element of fourth control sequence S4equal to 0. In an exemplary embodiment, fifth serial multiplexer451may route selector control bit Sel to serial carry input450responsive to the second element of fourth control sequence S4equal to 1.

FIG. 4Ashows a serial key generation logic circuit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, a serial key generation logic circuit400A may include a first implementation of serial cryptoprocessing logic circuit400. In an exemplary embodiment, parallel key generation logic circuit300A may simultaneously obtain the plurality of public key sequences. On the other hand, in an exemplary embodiment, serial key generation logic circuit400A may obtain each of the plurality of public key sequences one at a time. In an exemplary embodiment, different steps of method102may be implemented utilizing serial key generation logic circuit400A. An exemplary second public output406may be routed to first serial output410utilizing a direct connection. In other words, in an exemplary embodiment, second public output406may be directly connected to first serial output410. An exemplary ithprivate sequence r2[i] may be routed to second serial output412utilizing a direct connection. An exemplary nthpublic key sequence p[n] may be extracted from serial shift register402utilizing a direct connection.

In further detail with regards to step134,FIG. 1Kshows a second flowchart of generating a first ciphertext sequence, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method134B may include a second implementation of step134. Referring toFIGS. 1K and 3, in an exemplary embodiment, generating nthfirst ciphertext sequence c1[n] may include initializing serial result sequence Res (step127), generating the nthfirst encryption sequence (step129), routing nthsecond random sequence e2[n] to third serial output416(step131), routing serial result sequence Res to fourth serial output418(step133), updating serial adder output420(step135), updating serial result sequence Res (step137), and extracting nthfirst ciphertext sequence c1[n] from serial shift register402(step139). In an exemplary embodiment, nthsecond random sequence e2[n] may be extracted from a second random key shift register457. In an exemplary embodiment, serial result sequence Res may be initialized by storing the zero sequence in a serial shift register402. In an exemplary embodiment, serial shift register402may be associated with serial result sequence Res. In an exemplary embodiment, serial result sequence Res may be stored in serial shift register402.

For further detail with regards to step129, in an exemplary embodiment, the nthfirst encryption sequence may be generated by repeating a second serial iterative process for N times. In an exemplary embodiment, the nthfirst encryption sequence may be obtained by multiplying public sequence a by first random key e1, i.e., first encryption product ae1. An exemplary first encryption product ae1may include the plurality of first encryption sequences. An exemplary nthfirst encryption sequence may be associated with serial result sequence Res. In an exemplary embodiment, serial result sequence Res may include nthfirst encryption sequence when the second serial iterative process is performed. An exemplary ithiteration of the second iterative process may include routing ithpublic subsequence a[i] to first public output404, generating selector bit SL, routing first public output404to second public output406, generating public inverter output408by bit-wise inverting first public output404, routing public inverter output408to second public output406, routing second public output406to first serial output410, routing ithfirst random sequence e1[i] to second serial output412, updating serial AND gate output414, routing serial AND gate output414to third serial output416, routing serial result sequence Res to fourth serial output418, updating serial adder output420, updating serial result sequence Res.

In an exemplary embodiment, ithfirst random sequence e1[i] may be extracted from a first random key shift register415. In an exemplary embodiment, ithpublic subsequence a[i] may be routed to first public output404utilizing first public multiplexer422. In an exemplary embodiment, first public multiplexer422may route ithpublic subsequence a[i] to first public output404utilizing a first public selector input417. In an exemplary embodiment, first public multiplexer422may route ithpublic subsequence a[i] to first public output404responsive to first counter output421loaded to first public selector input417. In an exemplary embodiment, first counter output421may be equal to i. An exemplary selector bit SL may be generated utilizing comparator424. An exemplary selector bit SL may be generated by setting selector bit SL to 1 responsive to n larger than or equal to i. An exemplary selector bit SL may be generated by setting selector bit SL to 0 responsive to n smaller than i. An exemplary first public output404may be routed to second public output406utilizing second public multiplexer426responsive to selector bit SL equal to 1. An exemplary public inverter output408may be generated utilizing a public inverter428responsive to selector bit SL equal 0.

An exemplary public inverter output408may be routed to second public output406utilizing second public multiplexer426responsive to selector bit SL equal to 0. An exemplary second public output406may be routed to first serial output410utilizing first serial multiplexer430. In an exemplary embodiment, first serial multiplexer430may route second public output406to first serial output410responsive to first control sequence S1loaded to first serial selector input431. In an exemplary embodiment, first control sequence S1may be equal to 00. An exemplary ithfirst random sequence e1[i] may be routed to second serial output412utilizing second serial multiplexer432. In an exemplary embodiment, second serial multiplexer432may route ithfirst random sequence e1[i] to second serial output412responsive to third control sequence S3loaded to a second serial selector input433. In an exemplary embodiment, third control sequence S3may be equal to 0.

An exemplary serial AND gate output414may be generated by performing an AND operation on first serial output410and second serial output412. An exemplary serial AND gate output414may be generated utilizing serial AND gate434. An exemplary serial AND gate output414may be routed to third serial output416utilizing third serial multiplexer436. In an exemplary embodiment, third serial multiplexer436may route serial AND gate output414to third serial output416responsive to second control sequence S2loaded to third serial selector input435. In an exemplary embodiment, second control sequence S2may be equal to 010.

An exemplary serial result sequence Res may be routed to fourth serial output418utilizing fourth serial multiplexer438. In an exemplary embodiment, fourth serial multiplexer438may route serial result sequence Res to fourth serial output418responsive to the first element of fourth control sequence S4loaded to fourth serial selector input439. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1. An exemplary serial adder output420may be updated by updating selector inverter output440and obtaining serial adder output420. An exemplary selector inverter output440may be updated by inverting selector bit SL utilizing selector inverter442. An exemplary serial adder output420may be obtained by summing third serial output416, fourth serial output418, and selector inverter output440utilizing serial adder444. An exemplary serial adder output420may be updated by storing serial adder output420in serial shift register402.

In an exemplary embodiment, first ciphertext c1may be obtained by summing first encryption product ae1and second random key e2. In an exemplary embodiment, steps131-137of method134B may be performed to generate first ciphertext c1by summing first encryption product ae1and second random key e2. An exemplary nthsecond random e2[n] may be routed to third serial output416utilizing third serial multiplexer436. In an exemplary embodiment, third serial multiplexer436may route nthsecond random e2[n] to third serial output416responsive to second control sequence S2loaded to third serial selector input435. In an exemplary embodiment, second control sequence S2may be equal to 011. An exemplary serial result sequence Res may be routed to fourth serial output418utilizing fourth serial multiplexer438. In an exemplary embodiment, fourth serial multiplexer438may route serial result sequence Res to fourth serial output418responsive to the first element of fourth control sequence S4loaded to fourth serial selector input439. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1. An exemplary serial adder output420may be updated by summing third serial output416, fourth serial output418, and serial carry input450equal to 0.

For further detail with respect to step136,FIG. 1Lshows a second flowchart of generating a second ciphertext sequence, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method136B may include a second implementation of step136. Referring toFIGS. 1L and 4, in an exemplary embodiment, generating nthsecond ciphertext sequence c2[n] may include initializing serial result sequence Res (step141), generating an nthsecond encryption sequence (step143), routing nththird random sequence e3[n] to third serial output416(step145), routing serial result sequence Res to fourth serial output418(step147), updating serial adder output420(step149), updating serial result sequence Res (step151), obtaining a plurality of message bits (step153), generating an nthmessage sequence (step155), routing the nthmessage sequence to third serial output416(step157), routing serial result sequence Res to fourth serial output418(step159), updating serial adder output420(step161), updating serial result sequence Res (step163), and extracting nthsecond ciphertext sequence c2[n] from serial shift register402(step139).

In an exemplary embodiment, nththird random sequence e3[n] may be extracted from a third random key shift register459. In an exemplary embodiment, nthsecond ciphertext sequence c2[n] may be extracted from a ciphertext shift register455. In an exemplary embodiment, nthmessage sequence m[n] may be extracted from a message shift register465. In an exemplary embodiment, serial result sequence Res may be initialized by storing the zero sequence in serial shift register402. In an exemplary embodiment, serial shift register402may be associated with serial result sequence Res. In an exemplary embodiment, serial result sequence Res may be stored in serial shift register402.

An exemplary nthsecond encryption sequence may be associated with serial result sequence Res. In an exemplary embodiment, the plurality of second encryption sequences may include a multiplication result of public key sequence p and first random key e1, i.e., a second encryption product pe1. An exemplary second encryption product may include the plurality of second encryption sequences. As a result, serial result sequence Res may include the nthsecond encryption sequence after performing step143.

In further details regarding to step143, in an exemplary embodiment, the nthsecond encryption sequence may be generated by repeating a third serial iterative process for N times. An exemplary first encryption product ae1may include the plurality of first encryption sequences. An exemplary nthsecond encryption sequence may be associated with serial result sequence Res. An exemplary ithiteration of the third serial iterative process may include routing ithpublic key sequence p[i] to a first public key output456, generating selector bit SL, routing first public key output456to a second public key output458, generating a public key inverter output460by bit-wise inverting first public key output456, routing public key inverter output460to second public key output458, routing second public key output458to first serial output410, routing ithfirst random sequence e1[i] to second serial output412, updating serial AND gate output414, routing serial AND gate output414to third serial output416, routing serial result sequence Res to fourth serial output418, updating serial adder output420, updating serial result sequence Res.

In an exemplary embodiment, ithpublic key sequence p[i] may be routed to first public key output456utilizing a first public key multiplexer461. In an exemplary embodiment, first public key multiplexer461may route ithpublic key sequence p[i] to first public key output456utilizing a first public key selector input463. In an exemplary embodiment, first public key multiplexer461may route ithpublic key sequence p[i] to first public key output456responsive to first counter output421loaded to first public key selector input463. In an exemplary embodiment, first counter output421may be equal to i.

An exemplary selector bit SL may be generated utilizing comparator424. An exemplary selector bit SL may be generated by setting selector bit SL to 1 responsive to n larger than or equal to i. An exemplary selector bit SL may be generated by setting selector bit SL to 0 responsive to n smaller than i. An exemplary first public key output456may be routed to second public key output458utilizing a second public key multiplexer462responsive to selector bit SL equal to 1. An exemplary public key inverter output460may be generated utilizing a public key inverter464responsive to selector bit SL equal 0. An exemplary public key inverter output460may be routed to second public key output458utilizing second public key multiplexer462responsive to selector bit SL equal to 0. An exemplary second public key output458may be routed to first serial output410utilizing first serial multiplexer430. In an exemplary embodiment, first serial multiplexer430may route second public key output458to first serial output410responsive to first control sequence S1loaded to first serial selector input431. In an exemplary embodiment, first control sequence S1may be equal to 01.

An exemplary ithfirst random sequence e1[i] may be routed to second serial output412utilizing second serial multiplexer432. In an exemplary embodiment, second serial multiplexer432may route ithfirst random sequence e1[i] to second serial output412responsive to third control sequence S3loaded to a second serial selector input433. In an exemplary embodiment, third control sequence S3may be equal to 0. An exemplary serial AND gate output414may be generated by performing an AND operation on first serial output410and second serial output412. An exemplary serial AND gate output414may be generated utilizing serial AND gate434. An exemplary serial AND gate output414may be routed to third serial output416utilizing third serial multiplexer436. In an exemplary embodiment, third serial multiplexer436may route serial AND gate output414to third serial output416responsive to second control sequence S2loaded to third serial selector input435. In an exemplary embodiment, second control sequence S2may be equal to 010.

An exemplary serial result sequence Res may be routed to fourth serial output418utilizing fourth serial multiplexer438. In an exemplary embodiment, fourth serial multiplexer438may route serial result sequence Res to fourth serial output418responsive to the first element of fourth control sequence S4loaded to fourth serial selector input439. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1. An exemplary serial adder output420may be updated by updating selector inverter output440and obtaining serial adder output420. An exemplary selector inverter output440may be updated by inverting selector bit SL utilizing selector inverter442. An exemplary serial adder output420may be obtained by summing third serial output416, fourth serial output418, and selector inverter output440utilizing serial adder444. An exemplary serial adder output420may be updated by storing serial adder output420in serial shift register402.

In an exemplary embodiment, second ciphertext c2may be obtained by summing second encryption product pe1and third random key e3. In an exemplary embodiment, steps145-151of method136B may be performed to generate second ciphertext c1by summing second encryption product pe1and third random key e3. An exemplary nththird random sequence e3[n] may be routed to third serial output416utilizing third serial multiplexer436. In an exemplary embodiment, third serial multiplexer436may route nththird random sequence e3[n] to third serial output416responsive to second control sequence S2loaded to third serial selector input435. In an exemplary embodiment, second control sequence S2may be equal to 100.

An exemplary serial result sequence Res may be routed to fourth serial output418utilizing fourth serial multiplexer438. In an exemplary embodiment, fourth serial multiplexer438may route serial result sequence Res to fourth serial output418responsive to the first element of fourth control sequence S4loaded to fourth serial selector input439. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1. An exemplary serial adder output420may be updated by summing third serial output416, fourth serial output418, and serial carry input450equal to 0. An exemplary serial adder output420may be updated utilizing serial adder444. An exemplary serial result sequence Res may be updated by storing serial adder output420in serial shift register402.

In an exemplary embodiment, nthsecond ciphertext c1[n] may be obtained by summing serial result sequence Res and nthmessage sequence m[n]. In an exemplary embodiment, steps157-163of method136B may be performed to generate c2[n] by summing serial result sequence Res and nthmessage sequence m[n]. In an exemplary embodiment, the plurality of message bits may be obtained utilizing the processor. In an exemplary embodiment, nthmessage sequence m[n] may be generated by the processor. In an exemplary embodiment, nthmessage sequence m[n] may include the b bits. In an exemplary embodiment, generating nthmessage sequence m[n] may include setting nthmessage sequence m[n] to a binary value of a decimal number equal to

-⌊q2⌋
responsive to an nthmessage bit of the plurality of message bits equal to 1. In an exemplary embodiment, generating nthmessage sequence m[n] may further include setting nthmessage sequence m[n] to the zero sequence responsive to the nthmessage bit equal to 0. An exemplary nthmessage sequence m[n] may be routed to third serial output416utilizing third serial multiplexer436. In an exemplary embodiment, third serial multiplexer436may route nthmessage sequence m[n] to third serial output416responsive to second control sequence S2loaded to third serial selector input435. In an exemplary embodiment, second control sequence S2may be equal to 101.

An exemplary serial result sequence Res may be routed to fourth serial output418utilizing fourth serial multiplexer438. In an exemplary embodiment, fourth serial multiplexer438may route serial result sequence Res to fourth serial output418responsive to the first element of fourth control sequence S4loaded to fourth serial selector input439. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1. An exemplary serial adder output420may be updated by summing third serial output416, fourth serial output418, and serial carry input450equal to 0. An exemplary serial adder output420may be updated utilizing serial adder444. An exemplary serial result sequence Res may be updated by storing serial adder output420in serial shift register402. An exemplary nthsecond ciphertext c2[n] may be extracted by routing serial result sequence Res to serial output452. An exemplary nthsecond ciphertext Q[n] may be extracted utilizing sixth serial multiplexer454.

FIG. 4Bshows a serial encryption logic circuit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, a serial encryption logic circuit400B may include a second implementation of serial cryptoprocessing logic circuit400. In an exemplary embodiment, parallel encryption logic circuit300B may simultaneously obtain the plurality of first ciphertext sequences. On the other hand, in an exemplary embodiment, serial encryption logic circuit400B may obtain each of the plurality of first ciphertext sequences one at a time. In an exemplary embodiment, parallel encryption logic circuit300B may simultaneously obtain the plurality of second ciphertext sequences. On the other hand, serial encryption logic circuit400B may obtain each of the plurality of second ciphertext sequences one at a time. In an exemplary embodiment, different steps of method104may be implemented utilizing serial encryption logic circuit400B. An exemplary ithfirst random sequence e1[i] may be routed to second serial output412utilizing a direct connection. In other words, in an exemplary embodiments, ithfirst random sequence e1[i] may be directly connected to second serial output412. An exemplary nthfirst ciphertext sequence c1[n] may be extracted utilizing a direct connection. An exemplary nthsecond ciphertext sequence c2[n] may be extracted utilizing a direct connection.

In further detail with respect to step106,FIG. 1Mshows a second flowchart of generating a plurality of decrypted message bits, consistent with one or more exemplary embodiments of the present disclosure. An exemplary method106B may include a second implementation of step106. Referring toFIGS. 1M and 4, in an exemplary embodiment, generating a plurality of decrypted message bits may include initializing serial result sequence Res (step167), generating an nthdecryption sequence (step169), routing nthsecond ciphertext sequence c2[n] to third serial output416(step171), routing serial result sequence Res to fourth serial output418(step173), updating serial adder output420(step175), updating serial result sequence Res (step177), generating a serial XOR gate output466(step179), and extracting the nthdecrypted message bit from serial XOR gate output466(step181).

In an exemplary embodiment, serial result sequence Res may be initialized by storing the zero sequence serial shift register402. An exemplary nthdecryption sequence may be associated with serial result sequence Res. In an exemplary embodiment, the plurality of decryption sequences may include a multiplication result of first ciphertext c1and private key r2, i.e., a decryption product c1r2. An exemplary decryption product c1r2may include the plurality of decryption sequences. As a result, serial result sequence Res may include the nthdecryption sequence after performing step169.

In further detail regarding to step169, in an exemplary embodiment, the nthdecryption sequence may be generated by repeating a fourth serial iterative process for N times. An exemplary decryption product c1r2may include the plurality of decryption sequences. An exemplary nthdecryption sequence may be associated with serial result sequence Res. An exemplary ithiteration of the fourth iterative process may include routing an ithfirst ciphertext sequence c1[i] of a plurality of first ciphertext sequences to a first ciphertext output468, updating selector bit SL, routing first ciphertext output468to a second ciphertext output470, generating a ciphertext inverter output472by bit-wise inverting first ciphertext output468, routing ciphertext inverter output472to second ciphertext output470, routing second ciphertext output470to first serial output410, routing ithprivate sequence r2[i] to second serial output412, updating serial AND gate output414, routing serial AND gate output414to third serial output416, routing serial result sequence Res to fourth serial output418, updating serial adder output420, updating serial result sequence Res.

In an exemplary embodiment, ithfirst ciphertext sequence c1[i] may be routed to first ciphertext output468utilizing a first ciphertext multiplexer474. In an exemplary embodiment, first ciphertext multiplexer474may route ithfirst ciphertext sequence c1[i] to first ciphertext output468utilizing a first ciphertext selector input469. In an exemplary embodiment, first ciphertext multiplexer474may route ithfirst ciphertext sequence c1[i] to first ciphertext output468responsive to first counter output421loaded to first ciphertext selector input469. In an exemplary embodiment, first counter output421may be equal to i. An exemplary selector bit SL may be generated utilizing comparator424. An exemplary selector bit SL may be generated by setting selector bit SL to 1 responsive to n larger than or equal to i. An exemplary selector bit SL may be generated by setting selector bit SL to 0 responsive to n smaller than i. An exemplary first ciphertext output468may be routed to second ciphertext output470utilizing a second ciphertext multiplexer476responsive to selector bit SL equal to 1. An exemplary ciphertext inverter output472may be generated utilizing a ciphertext inverter477responsive to selector bit SL equal 0.

An exemplary ciphertext inverter output472may be routed to second ciphertext output470utilizing second ciphertext multiplexer476responsive to selector bit SL equal to 0. An exemplary second ciphertext output470may be routed to first serial output410utilizing first serial multiplexer430. In an exemplary embodiment, first serial multiplexer430may route second ciphertext output470to first serial output410responsive to first control sequence S1loaded to first serial selector input431. In an exemplary embodiment, first control sequence S1may be equal to 10. An exemplary ithprivate sequence r2[i] may be routed to second serial output412utilizing second serial multiplexer432. In an exemplary embodiment, second serial multiplexer432may route ithprivate sequence r2[i] to second serial output412responsive to third control sequence S3loaded to a second serial selector input433. In an exemplary embodiment, third control sequence S3may be equal to 1.

An exemplary serial AND gate output414may be generated by performing an AND operation on first serial output410and second serial output412. An exemplary serial AND gate output414may be generated utilizing serial AND gate434. An exemplary serial AND gate output414may be routed to third serial output416utilizing third serial multiplexer436. In an exemplary embodiment, third serial multiplexer436may route serial AND gate output414to third serial output416responsive to second control sequence S2loaded to third serial selector input435. In an exemplary embodiment, second control sequence S2may be equal to 010. An exemplary serial result sequence Res may be routed to fourth serial output418utilizing fourth serial multiplexer438. In an exemplary embodiment, fourth serial multiplexer438may route serial result sequence Res to fourth serial output418responsive to the first element of fourth control sequence S4loaded to fourth serial selector input439. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1.

An exemplary serial adder output420may be updated by updating selector inverter output440and obtaining serial adder output420. An exemplary selector inverter output440may be updated by inverting selector bit SL utilizing selector inverter442. An exemplary serial adder output420may be obtained by summing third serial output416, fourth serial output418, and selector inverter output440utilizing serial adder444. An exemplary serial adder output420may be updated by storing serial adder output420in serial shift register402.

In an exemplary embodiment, the plurality of decrypted message bits may be obtained by summing decryption product c1r2and second ciphertext c2. In an exemplary embodiment, steps171-177of method106B may be performed to generate the plurality of decrypted message bits by summing decryption product c1r2and second ciphertext c2. An exemplary nthsecond ciphertext sequence c2[n] may be routed to third serial output416utilizing third serial multiplexer436. In an exemplary embodiment, third serial multiplexer436may route nthsecond ciphertext sequence c2[n] to third serial output416responsive to second control sequence S2loaded to third serial selector input435. In an exemplary embodiment, second control sequence S2may be equal to 000.

An exemplary serial result sequence Res may be routed to fourth serial output418utilizing fourth serial multiplexer438. In an exemplary embodiment, fourth serial multiplexer438may route serial result sequence Res to fourth serial output418responsive to the first element of fourth control sequence S4loaded to fourth serial selector input439. In an exemplary embodiment, the first element of fourth control sequence S4may be equal to 1. An exemplary serial adder output420may be updated by summing third serial output416, fourth serial output418, and serial carry input450equal to 0. An exemplary serial adder output420may be updated utilizing serial adder444. An exemplary serial result sequence Res may be updated by storing serial adder output420in serial shift register402.

An exemplary serial XOR gate output466may be generated by performing an XOR operation on two most significant bits of serial shift register402. An exemplary serial XOR gate output466may be generated utilizing a serial XOR gate478. An exemplary nthdecrypted message bit may be extracted from serial XOR gate output466by routing serial XOR gate output466to serial output452. An exemplary serial XOR gate output466may be routed to serial output452utilizing sixth serial multiplexer454.

FIG. 4Cshows a serial decryption logic circuit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, a serial decryption logic circuit400C may include a third implementation of serial cryptoprocessing logic circuit400. In an exemplary embodiment, parallel decryption logic circuit300C may simultaneously obtain the plurality of decrypted message bits. On the other hand, in an exemplary embodiment, serial decryption logic circuit400C may obtain each of the plurality of decrypted message bits one at a time. In an exemplary embodiment, different steps of method106may be implemented utilizing serial decryption logic circuit400C. An exemplary ithprivate sequence r2[i] may be routed to second serial output412utilizing a direct connection. In other words, in an exemplary embodiments, ithprivate sequence r2[i] may be directly connected to second serial output412. An exemplary second ciphertext output470may be routed to first serial output410utilizing a direct connection. An exemplary serial XOR gate output466may be routed to serial output452utilizing a direct connection.

FIG. 5shows an example computer system500in which an embodiment of the present invention, or portions thereof, may be implemented as computer-readable code, consistent with exemplary embodiments of the present disclosure. For example, step108of flowchart102, step132of flowchart104, steps168and170of flowchart136A, and steps153and155of flowchart136B may be implemented in computer system500using hardware, software, firmware, tangible computer readable media having instructions stored thereon, or a combination thereof and may be implemented in one or more computer systems or other processing systems. Hardware, software, or any combination of such may embody any of the modules and components inFIGS. 1A-1M.

If programmable logic is used, such logic may execute on a commercially available processing platform or a special purpose device. One ordinary skill in the art may appreciate that an embodiment of the disclosed subject matter can be practiced with various computer system configurations, including multi-core multiprocessor systems, minicomputers, mainframe computers, computers linked or clustered with distributed functions, as well as pervasive or miniature computers that may be embedded into virtually any device.

For instance, a computing device having at least one processor device and a memory may be used to implement the above-described embodiments. A processor device may be a single processor, a plurality of processors, or combinations thereof. Processor devices may have one or more processor “cores.”

Processor device504may be a special purpose or a general-purpose processor device. As will be appreciated by persons skilled in the relevant art, processor device504may also be a single processor in a multi-core/multiprocessor system, such system operating alone, or in a cluster of computing devices operating in a cluster or server farm. Processor device504may be connected to a communication infrastructure506, for example, a bus, message queue, network, or multi-core message-passing scheme.

In an exemplary embodiment, computer system500may include a display interface502, for example a video connector, to transfer data to a display unit530, for example, a monitor. Computer system500may also include a main memory508, for example, random access memory (RAM), and may also include a secondary memory510. Secondary memory510may include, for example, a hard disk drive512, and a removable storage drive514. Removable storage drive514may include a floppy disk drive, a magnetic tape drive, an optical disk drive, a flash memory, or the like. Removable storage drive514may read from and/or write to a removable storage unit518in a well-known manner. Removable storage unit518may include a floppy disk, a magnetic tape, an optical disk, etc., which may be read by and written to by removable storage drive514. As will be appreciated by persons skilled in the relevant art, removable storage unit518may include a computer usable storage medium having stored therein computer software and/or data.

In alternative implementations, secondary memory510may include other similar means for allowing computer programs or other instructions to be loaded into computer system500. Such means may include, for example, a removable storage unit522and an interface520. Examples of such means may include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM, or PROM) and associated socket, and other removable storage units522and interfaces520which allow software and data to be transferred from removable storage unit522to computer system500.

Computer system500may also include a communications interface524. Communications interface524allows software and data to be transferred between computer system500and external devices. Communications interface524may include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, or the like. Software and data transferred via communications interface524may be in the form of signals, which may be electronic, electromagnetic, optical, or other signals capable of being received by communications interface524. These signals may be provided to communications interface524via a communications path526. Communications path526carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, an RF link or other communications channels.

In this document, the terms “computer program medium” and “computer usable medium” are used to generally refer to media such as removable storage unit518, removable storage unit522, and a hard disk installed in hard disk drive512. Computer program medium and computer usable medium may also refer to memories, such as main memory508and secondary memory510, which may be memory semiconductors (e.g. DRAMs, etc.).

Computer programs (also called computer control logic) are stored in main memory508and/or secondary memory510. Computer programs may also be received via communications interface524. Such computer programs, when executed, enable computer system500to implement different embodiments of the present disclosure as discussed herein. In particular, the computer programs, when executed, enable processor device504to implement the processes of the present disclosure, such as the operations in method100illustrated by flowchart102ofFIG. 1B, flowchart104ofFIG. 1E, flowchart136A ofFIG. 1G, and flowchart136B ofFIG. 1Ldiscussed above. Accordingly, such computer programs represent controllers of computer system500. Where an exemplary embodiment of method100is implemented using software, the software may be stored in a computer program product and loaded into computer system500using removable storage drive514, interface520, and hard disk drive512, or communications interface524.

Embodiments of the present disclosure also may be directed to computer program products including software stored on any computer useable medium. Such software, when executed in one or more data processing device, causes a data processing device to operate as described herein. An embodiment of the present disclosure may employ any computer useable or readable medium. Examples of computer useable mediums include, but are not limited to, primary storage devices (e.g., any type of random access memory), secondary storage devices (e.g., hard drives, floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices, and optical storage devices, MEMS, nanotechnological storage device, etc.).

In this example, a performance of a cryptoprocessing method (similar to method100) is evaluated. The method is implemented on a cryptoprocessing logic circuit (similar to parallel cryptoprocessing logic circuit300). The cryptoprocessing logic circuit is implemented on a Virtex 6 field programmable gate array (FPGA). For q=256 and N=256, the cryptoprocessing logic circuit provides 73 quantum bits and 84 classic bits of security, respectively. Moreover, a run time of cryptoprocessing for encryption and decryption are about 1.1 μs and 0.54 μs, respectively. For q=256 and N=512, the cryptoprocessing logic circuit provides 140 quantum bits and 190 classic bits of security, respectively. Moreover, a run time of cryptoprocessing for encryption and decryption are about 2.32 μs and 1.13 μs, respectively.

In this example, a performance of a cryptoprocessing method (similar to method100) is evaluated. The method is implemented on a cryptoprocessing logic circuit (similar to serial cryptoprocessing logic circuit400). The cryptoprocessing logic circuit is implemented on an application specific integrated circuit using 45 nm Nangate standard cell library. For q=256 and N=256, the cryptoprocessing logic circuit provides 84 classic bits of security. For q=256 and N=512, the cryptoprocessing logic circuit provides about 84 classic bits of security. Moreover, a run time of cryptoprocessing for encryption and decryption are about 3.8×103μs and 0.54×103μs, respectively. For q=256 and N=512, the cryptoprocessing logic circuit provides about 190 classic bits of security, respectively. Moreover, a run time of cryptoprocessing for encryption and decryption are about 15.2×103μs and 7.6×103μs, respectively.