Mobile device adapter and charger

Systems and methods are presented for an improved high power density power adapter. On one potential embodiment, an improved power adapter includes an AC input; a rectifier coupled to the AC input; a power factor correction circuit coupled to the rectifier; and a burst switch circuit coupled to the power factor correction circuit. The burst switch circuit provides power to a DC output via a set of FET drivers, a set of FETs, and a transformer and may provides power exclusively in a burst mode using a feedback input from the DC output. The transformer may be composed of windings coupled to the set of FETs, and additional windings embedded in the PCB and coupled to the first winding. Certain windings may comprise a conductive ribbon that loops around a transformer core. Additional embodiments may include monitoring circuits and multiple outputs.

BACKGROUND

The present application related to DC power supplies, and AC to DC power adapters. The present application further refers to multi-function power supplies, USB power supplies, and improved power supply efficiency, power density, and circuit protection.

With a modern proliferation of electronic devices, a wide variety of interconnects and power supplies to communicate with and power those electronic devices has emerged in a broad range of shapes, sizes, and connection formats. For many computing devices, power is provided to the device via a switching power supply that receives an AC input and provides a DC power to the electronic device. One potential interconnect is a simple DC tip input to an electronic device. Additionally, while there are various power supply connection formats from a power supply to an electronic device, a universal serial bus (USB) interface is a commonly used connecting interface.

The USB interface includes the benefit of being able to function both as an information connection and a connection for device charging. A general USB interface has pin definitions comprising a VBUS terminal, a D+ terminal, a D− terminal and a ground terminal. The VBUS terminal and the ground terminal are used to output DC power if the USB interface connects to a DC power source. The D+ and D− terminals are used to transmit data. Compared with conventional computer connecting buses, the USB interface is capable of transmitting data and providing electric power as a power supply connection in a standardized format. Because of the above-mentioned features, some portable electronic devices are designed to have USB interfaces for connecting to computers and charging the portable electronic devices from the computers. While power adapters and power supplies currently exist to support broad range of devices, there is an increasing need due to the numbers of devices in use by individual users or households that require charging. Improved mobile device adapters and chargers that can provide power adapting and charging functions for different types of devices and multiple devices simultaneously may therefore improve on the currently available device adapters and power supplies.

BRIEF SUMMARY

Various embodiments of present innovations describe an improved power adapter. Various alternative embodiments include improved power adapters and supplies with improved to DC power supply modules, improved AC to DC power modules, improved multi-function power modules and outputs, improved USB power supplies, and improved power supply efficiency, power density, and circuit protection. Additional combinations and improvements are also described such that alternate combinations of the provided examples may be apparent to one of ordinary skill in the art from the details of the provided examples.

In one particular embodiment, and improved power adapter is described that is made up of an AC input; a rectifier coupled to the AC input; a power factor correction circuit coupled to the rectifier; and a burst switch circuit coupled to the power factor correction circuit. The burst switch circuit provides power to a DC output via a set of FET drivers, a set of FETs, and a transformer, and wherein the burst switch circuit provides power exclusively in a burst mode using a feedback input from the DC output. The transformer may be composed of a first winding coupled to the set of FETs, and second, third, fourth, and fifth windings each coupled to the first winding, wherein the second winding and the third winding are embedded in a printed circuit board; and wherein the fourth and fifth winding each comprise a conductive ribbon that loops around a transformer core.

Various embodiments may also include a power adapter housing enclosing the power adapter such that the power density of the power adapter enclosed by the power adapter housing is greater than 12 W/cubic inch, providing improved power density over previously known power supplies with equivalent functionality.

Various embodiments may also include a high voltage line coupled to a bus output of the power factor correction circuit, a comparator, and a diode coupled to a transistor, where the transistor is further coupled to the high voltage line. In certain embodiments, the diode and the transistor operate at a start-up of the power adapter to create a low voltage backup that provides operating power to the set of FET drivers at the start-up of the power adapter, and the second winding may create a FET driver operating voltage that replaces the low voltage backup in providing power to the set of FET drivers when the second winding is driven by the first winding. Additionally, certain embodiments may function such that the comparator compares a first comparison voltage with the FET driver operating voltage and the output of the comparator is coupled to the transistor to maintain the low voltage backup when the FET driver operating voltage drops below a predetermined threshold set by the first comparison voltage.

In further embodiments according to the present innovations, an improved power adapter may have a USB switcher coupled to the DC output that drives a USB voltage and a USB current to a first USB output and a second USB output. Certain embodiments may include improved system monitoring with a first monitoring circuit that monitors the USB current and activates a fault input of the power factor correction circuit when the USB current exceeds a current threshold, a second monitoring circuit that monitors the USB voltage and activates the fault input of the power factor correction circuit when the USB voltage exceeds a voltage threshold; and/or a third monitoring circuit that activates the fault input of the power factor correction circuit when a DC output voltage of the DC output exceeds a DC voltage threshold.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention are directed to AC to DC adapters and chargers having a high power density. These power supplies may be used to charge portable devices with DC tip input or a universal serial bus (USB) port. The high power density enables the power adapter to be compact, and at the same time to provide charging capacity to multiple devices. Additional embodiments enable device protection measure that avoid damage conditions common in previously known power supplies.

FIGS. 1-7describe one potential embodiment of a high power density adapter.FIG. 1details a perspective view, and shows AC input22.FIGS. 2-3show side angles andFIGS. 4-5show top and bottom views. Aspects of the present innovations allow the power adapter to have a power density greater than 12 Watts/cubic inch, and additionally enable a thin profile.FIG. 6shows an end perspective that includes AC input22.FIG. 7shows an opposite end of the power adapter from the end shown inFIG. 6, and includes cover switch24, DC output29, USB port26, and mini-USB port28.FIGS. 1-7are provided for illustrative purposes, and do not limit the shape or port configurations possible under different embodiments. Alternative embodiments may include a DC tip output with two USB ports, or any combination of USB, mini-USB, or micro-USB ports. Further alternative embodiments may include three or more USB ports with additional supporting protection circuitry.

FIG. 8shows one embodiment of a simplified system diagram for a power adapter200according to the innovations herein. Power adapter100comprises AC input22, rectifier23, power factor correction circuit30, discrete second bus start up circuit20, chipset regulator40, shutdown protection circuit50, burst switcher circuit60, adapter housekeeping circuit70, synchronous rectification circuit80, primary protection circuit90, secondary protection circuit100, USB switcher110, USB protection circuit120, DC output130, first USB output140, and second USB output150

AC input22and bridge rectifier23work together to accept an AC input and deliver the AC input to power factor correction circuit30. In one potential embodiment, AC input22accepts an AC input that is between 90 V and 264 VAC. Rectifier23may be any rectifier that delivers a single polarity voltage, for example a standard bridge rectifier. The voltage output from the rectifier23is then input to power factor correction circuit30. Output power from rectifier23or AC input22may additionally be used to provide initial start up power for chipset regulator40or other components requiring initial start up power.

Power factor correction circuit30receives a rectified AC voltage input, and supplies a DC voltage output for use as a voltage and power input by burst switcher circuit60. Burst switcher circuit60drives DC output130using burst signals to FETs, drivers, and a transformer that is part of synchronous rectification circuit80. Burst switcher circuit60further relies on a feedback signal from DC output130to control an output of burst signals which initiate the adapter of power to the DC output130via the aforementioned drivers, FETs, and transformer. DC output130includes connections that further adapter power to USB switcher110. USB switcher110then enables power output at first USB output140and second USB output150.

Power adapter200additionally includes protection circuitry operating in conjunction with above described system. Primary protection circuit90senses fault signals from burst switcher circuit60, secondary protection circuit100senses current and voltage from DC output130, and USB protection circuit120senses voltage and current from USB switcher110. All three elements of primary protection circuit90, secondary protection circuit100, and USB protection circuit120provide signals through shutdown protection circuit50to enable power shutdown through power factor correction circuit30.

Power Factor Correction Circuit

Power factor correction circuit30accepts the rectified voltage input from rectifier23, and creates a DC output voltage. In several embodiments, power factor correction circuit comprises power handling electronic switches that effectively connect and disconnect energy storage inductors and capacitors to and from an input source to an output. By varying duty cycle, frequency, or phase shift, the output of power factor correction circuit may be controlled. An active power factor corrector (PFC) is a power electronic system that controls the amount of power drawn by a load in order to obtain a power factor as close as possible to unity. In most applications, the active PFC controls the input current of the load so that the current waveform is proportional to the mains voltage waveform (a sine wave). The purpose of making the power factor as close to unity (1) as possible is to make the load circuitry that is power factor corrected appear purely resistive (apparent power equal to real power). In this case, the voltage and current are in phase and the reactive power consumption is zero. This enables the most efficient delivery of electrical power. Some types of active PFC are buck, boost, and buck-boost. In the case of a switched-mode power adapter, a boost converter is inserted between the bridge rectifier and the main input capacitors. The boost converter attempts to maintain a constant DC bus voltage on its output while drawing a current that is always in phase with and at the same frequency as the line voltage. Another switchmode converter inside the power adapter produces the desired output voltage from the DC bus. This approach requires additional semiconductor switches and control electronics, but permits cheaper and smaller passive components. Due to their very wide input voltage range, many power supplies with active PFC can automatically adjust to operate on AC power supplied by power utilities in most locations. This includes inputs from about 100 V (Japan) to 230 V (Europe).

Specific detail will now be provided to describe an embodiment of a power adapter2000, with various components of power adapter2000detailed inFIGS. 9-15.

FIGS. 9A and 9Bdiscloses one potential embodiment of a power factor correction circuit that may be used as in embodiments such as power factor correction circuit that is part of power adapter2000inFIG. 8. Power factor correction circuit900comprises a buck power factor correction circuit232. The operation of a basic buck topology uses an inductor and two switches (usually a transistor and a diode) that control the inductor. It alternates between connecting the inductor to source voltage to store energy in the inductor and discharging the inductor into the load. Buck power factor correction circuit232may include variations on this bock topology, in addition to additional control circuitry.

Where a traditional adapter would create a DC output voltage for a voltage bus in the range of 360-420V, power factor correction circuit30outputs a lower DC voltage. In one potential embodiment, the DC output of power factor correction circuit30may be set to any DC voltage between 50V and 150V. In one Embodiment, the DC output of power factor correction circuit is near 84V. A setting in the 80V range allows the use of sub-100V rated capacitors for space savings, while avoiding the losses that occur in a lower voltage. For example, at a setting of 50V, the copper losses in the system become excessive, and traces and currents are required to create a functioning circuit. A setting in the sub 100 VC range also allows for a more dense design as creepage and clearances can be reduced.

Additional functionality of power factor correction circuit will be described below in conjunction with other circuits ofFIGS. 9-13.

Burst Switcher Circuit

FIGS. 10A and 10Bdescribe one potential embodiment of burst switcher circuit1000, which may be included as part of an embodiment of power adapter2000ofFIG. 8. Burst switcher circuit1000comprises burst switch chip262. Burst switch chip262comprises DC voltage input264, chipset voltage input266, high gate output269a, low gate output269b, and feedback input268. During normal operation, burst switcher circuit1000provides burst signals to that enable power to a DC output430of power adapter2000. DC output430is adapted to match the power demands of a load placed on the DC output through feedback circuitry. Because the burst switcher circuit constantly operates in a feedback mode and adapts to the output load demands, greater efficiency is achieved that in a traditional switched power adapter that does not constantly adapt to the load demands. Additional description of the functionality of burst switcher circuit1000will be described below in conjunction withFIGS. 9-13.

Synchronous Rectification and DC Output

FIGS. 11A and 11Bdescribe one potential implementation of synchronous rectification circuit1100and DC output430, both of which may be part of an implementation of power adapter2000ofFIG. 8. Synchronous rectification circuit1100comprises FET drivers382and384, FETs386and388, as well as transformer windings T1a, T1d, T1e, T1g, and T1f. When operating FET driver382receives signals from high gate output269aofFIG. 10and FET driver384receives power from low gate output269bofFIG. 10. FET drivers382and384drive FETS386AND388, which in turn drive transformer winding T1a. Transformer winding T1adrives transformer windings T1eand T1f. Transformer winding T1edrives FET Q101and transformer winding T1fdrives FET Q102. FETs Q101and Q102drive the current for DC output430of T1dand T1gare complementary planar windings. In one potential embodiment, T1dcomprises a planar winding in a circuit board consisting of two clockwise windings, and T1gcomprises a planar winding in the circuit board consisting of two counter-clockwise windings. T1dand T1gare part of the gate drive circuit used to drive FETs Q101and Q102. The main windings T1eand T1fare copper foil windings.

In addition to the use of 100V rated capacitors associated with the lower than typical DC output of power factor correction circuit30, in one potential embodiment, space may be saved and greater power density achieved through the use of surface mount component, and a mixture of planar transformer windings, triple insulated primary winding, and foil transformer windings creating a hybrid design.

For example, in one potential embodiment, transformer windings that are designed to operate below a predetermined current or power threshold may be implemented as embedded planar windings in a circuit board. Transformer windings designed to operate above the predetermined threshold may be implemented using foil windings. Use of planar windings in the circuit board may enable higher power density, and lower product thickness. Similarly, for a high power output transformer, copper foil windings may enable a more compact output transformer, and therefore a circuit board with lower height, a thinner package, and a higher overall power density. In one potential embodiment copper foil is used for all turns and legs attached to the circuit board in a 100 W output transformer.

FIGS. 14-17describe transformer T1that includes windings T1a, T1b, T1c, T1d, T1e, T1f, and T1g. Transformer T1may be used to implement the windings as shown inFIGS. 9,10, and11. T1ais a primary winding that drives power to windings T1b-fon both sides of isolation barrier3.

FIG. 15shows an embodiment of power adapter2000in which windings T1b-dand T1gare windings embedded in circular PCB section1500. In one embodiment shown inFIG. 16, T1ais a split winding, comprising both a foil winding T1a1and a wire winding T1a2.FIG. 16additionally shows the ends of secondary foil windings T1eand T1f, with a coil forming fixture1610.

FIG. 16shows coil forming fixture1610placed above circular PCB section1500, with foil windings T1a1, T1e, and T1fterminated on a PCB1700. Primary wire winding T1a2is also shown to be terminated to PCB1700. Following placement of the windings via coil forming fixture1610at circular PCB section1500, the core may be placed at attached to PCB1700. The core, such as Feroxcube™ EQ core. In alternative embodiments, the core may comprise top and bottom components that connect through an opening in circular PCB section1500. The core may be glued or otherwise attached to circular PCB section1500or affixed through some other attachment or clamp to PCB1700that positions the core within windings T1a-f.

FIG. 18shows an interleaving arrangement for windings T1aand T1ein transformer1. The interleaving arrangement allows for an efficient high power output in a small space in a synchronous transformer such as synchronous rectifier80ofFIG. 8. According to the structure ofFIGS. 14-18, one embodiment of a transformer T1as follows: secondary winding of windings T1efrom winding end811to winding end812is wound first around a fixture. Placement of secondary foil windings prior to primary foil winding may allow subsequent steps in setting the structure, such as a milling of the core that may be necessary if the primary foil winding is placed first, to be avoided. In a compact transformer, one potential core may be a Ferroxcube™ EQ25LP core as mentioned above with a gap length of approximately 0.1 mm with an AL of approximately 800 nH. The secondary windings and are wound counterclockwise. Primary winding T1ais wound over 2 layers in a counter clockwise direction after the secondary windings are complete. In one alternative embodiment, tape such as 50 um Mylar tape may be used to keep each foil winding in place after each piece of foil is wound, so secondary windings T1eand T1fmay be wound and kept in place with tape, and the primary foil winding T1a1may subsequently be wound and set in place with Mylar tape. Windings are then attached to pins in a PCB such as PCB1700ofFIG. 17to integrate the transformer windings with a circuit contained in the attached PCB.

Discrete Second Bus Start Up Circuit

FIG. 12includes discrete second bus start up circuit1200, which is one potential embodiment of discrete second bus start up circuit20. Discrete second bus start up circuit1200comprises high voltage line1210, low voltage backup line1212, first comparison voltage1214, second comparison voltage1216, comparator1220, transistor1240, diodes1242-1244, resistors1248-1258,1268, and capacitors1272-1278. High voltage line1210receives a DC voltage from a power factor correction circuit900ofFIG. 9, where high voltage line1210ofFIG. 12is connected either directly or indirectly to bus output252ofFIG. 9. Discrete second bus start up circuit1200operates to adapter and maintain power to FET drivers in power adapter2000during start up and abnormal operating conditions, as will be described just below with respect toFIGS. 9-12.

DC Output Power Adapter Operation

Start up and function of one potential implementation of power adapter2000will now be described in conjunction with discrete second bus start up circuit1200ofFIG. 12, power factor correction circuit900ofFIGS. 9A and 9B, synchronous rectification circuit1100ofFIGS. 11A and 11B, and burst switcher circuit1000ofFIGS. 10A and 10B.

When power adapter2000is enabled through connection of an AC input to an AC source, or in some embodiments, through selection of a switch, the input AC power is rectified and supplied to rectified input240ofFIG. 9

Rectified input240will initially adapter a small amount of power when an AC input of a power adapter such as AC input22ofFIG. 1is provided an AC input. The initial power from rectified input240is sufficient to activate regulator242with a secondary bus voltage level. Regulator242then supplies a chip voltage to buck power factor correction circuit232at power connection236. Further, when AC voltage is input to the power adapter associated with power factor correction circuit900, input234receives a rectified AC voltage from a rectifier such as rectifier23ofFIG. 8. When buck power factor correction circuit232is powered on with an input power at power connection236, and is receiving the AC input voltage at input234, it functions to output a DC voltage at bus output252. Power factor correction circuit900thus enables a power adapter to have a efficient and relatively high voltage DC bus from an AC input. In one exemplary embodiment, the DC voltage at bus output252is 84 V.

Bus output252then supplies a DC voltage to high voltage input1210ofFIG. 12. When high voltage input1210receives power diodes1242and1244clap at voltage settings to set the voltage levels at an input of transistor1240to a secondary bus voltage level. The voltage level at low voltage backup line1212is therefore set to the secondary bus voltage level. In one potential embodiment, the secondary bus voltage level may be 10V, and may be consistent throughout secondary power levels in power adapter2000, such as the secondary power level supplied to regulator242at startup inFIG. 9. Providing the secondary power levels provides design flexibility in device start up and normal operation through power feedback from the output transformer. In other embodiments, the adapter of secondary power levels may be provided independently at different voltage levels.

When low voltage backup line1212achieves a secondary bus voltage level, that voltage is passed to FET drivers382and384ofFIG. 11to turn the FET drivers on, and the voltage is also passed to low voltage input1010ofFIG. 10. Low voltage input1010ofFIG. 10then provides sufficient power to regulator1042with a secondary bus voltage level. Regulator1042then supplies a chip voltage to burst switch chip262at chipset voltage input236from chipset voltage connection1012. The physical connection from chipset voltage connection1012to chipset voltage input236is not shown inFIG. 10. Regulator1042further provides power to adapter feedback circuit1020with power in conjunction with feedback connection1022to provide a feedback signal from DC output430. The feedback operates by a connection from DC output430that operates through a circuit to provide a signal at feedback input268.

In one embodiment, DC output430is connected to feedback output line1310ofFIG. 13. The output voltage is sensed and compared to a reference value by a comparator1320on the secondary side, and the comparator1320output drives a digital opto-coupler1312. When the output voltage is below the regulation level, the comparator1320output is high and the opto-coupler is not driven; when the output voltage exceeds the regulation level, the comparator1320output goes low and turns on the opto-coupler1312. In this way, the output comparator1320acts like a simple ND converter. The opto-coupler1312feeds the digital feedback information to the primary side across the isolation barrier of the transformer. In normal mode, the burst switcher circuit1000monitors the feedback input268to determine the switching cycle and mark/space ratio to maintain an appropriate level of output burst signaling from high gate output269aand low gate output269bto meet power demands at DC output530. When the feedback indicates power is needed, a switching cycle is commenced to output burst power at high gate output269aand low gate output269b. Every time a switching cycle is commenced, it is completed fully, regardless of the input at feedback input268. During each current switching cycle, feedback input268is monitored to determine whether or not a subsequent switching cycle should be delivered. If feedback input268stays high, then another switching cycle is delivered contiguously. If feedback input268goes low, then switching ceases or “drops out” at the end of the current cycle. While delivering switching cycles, feedback input268is polled once every switching cycle. Once switching ceases at the end of the cycle, feedback input268is monitored while the controller waits for the next feedback input268high transition to indicate that switching should recommence.

A switching cycle delivers alternating square wave outputs from high gate output269aand low gate output269b. The output of high gate output269ais deliver to FET driver382ofFIG. 11. The output of low gate output269bis delivered to FET driver384ofFIG. 11. These FET drivers then drive FETs386and388, which in turn drive primary winding T1aofFIG. 11.

When T1ais driven by FETs386and388, it in turn drives windings T1b-g. Windings T1dand T1ethen drive FET Q101ofFIG. 11. Windings T1fand T1gdrive FET Q102ofFIG. 11. These components then drive the output power available from DC output430.

When driven by winding T1a, winding T1bofFIG. 9serves to replace rectified input240as the input power source for regulator242. Winding T1conFIG. 10similarly replaces low voltage input1010ofFIG. 12as the source of power for both regulator1042inFIG. 10and FET drivers382and384ofFIG. 11. Because FET drivers382and384are now essentially receiving their operating power and voltage from transformer1, additional protection circuitry is required to protect certain parts of the circuit in abnormal operating conditions.

When an output load is changed while the power adapter2000remains operational during the change, burst switcher circuit1000may operate for a time in some embodiments under an incorrect feedback setting, where burst switcher circuit1000operates based on an expected feedback of the original load, while comparator1320and the comparator1320output drives a digital opto-coupler1312according to a new output voltage and a new load. Under these circumstances, burst switcher circuit may cease delivering switching cycles while the new output load continues to draw power. As T1afails to be driven by signals originating from high gate output269aand low gate output269b, the power supplied to operate FET drivers382and384may fall below an operating threshold, and the FET drivers382and384may shut down without the rest of power adapter2000receiving an error or shutdown indication. In this circumstance where FET drivers382and384have shut down, the feedback input268to burst switch chip262will eventually reach a level where a switching cycle would have been requested by the old load, and output from high gate output269aand low gate output269bwill recommence. Because FET drivers382and384have shut down and no longer respond to an input from high gate output269aand low gate output269b, FETs386and388will begin to draw excess power from high voltage line1102which is connected to high voltage line1210ofFIG. 10, and across transistor1240which supplies start up operating power to FET drivers382and384. Because Transistor1240is not capable of dealing with this demand, there is a high likelihood that transistor1240will be destroyed if it operates normally without support from resistor1250, comparator1220, and the related circuitry. Resistor1250functions to prevent excessive current from flowing through transistor1240in conditions where high voltage line1210may draw power through transistor1240. Comparator1220is connected to first comparison voltage1214and second comparison voltage1216through dividing resistors as shown byFIG. 12. The configuration of comparator1220and resistors1252through1258are provided by example, and may be of any set of values that functions in the fashion described here. First comparison voltage1214is attached to the low voltage backup line1212which, as described above, provides a start up operating voltage to FET drivers382and384. Second comparison voltage1216may be attached to any stable voltage level that does not depend on power from T1to operate, such as chip voltage at power connection236from regulator242which may operate from the rectified AC input.

If comparator1220senses first comparison voltage1214is dropping from the level required to adapter adequate operating power to FET driver382and384, comparator1220output drives diode1242and transistor1240back to the voltage required. In this way, comparator1220operates to prevent shutdown of FET drivers382and384, and to prevent potential damage to transistor1240.

USB Output Operation and Protection Circuits

In addition to the functionality described above,FIGS. 13A,13B,13C, and13D, includes a description of USB outputs1360and1362that may be incorporated into various embodiments according to the present invention. In various embodiments USB outputs1360and1362may be mini, micro, or any other form factor of USB output.FIG. 13also shows USB switcher1380, which includes USB switcher power input1382. USB switcher power input1382receives power from DC output420or from a power adapter derived from or just prior to power adapter2000DC output420around FETs Q101AND Q102. USB switcher is preferably rated to adapter a combined output at USB outputs1360and1362of at least 2.5 A. In one embodiment, USB switcher is rated to provide 4 A.

Diode1330is a part of an opto-isolator comprising diode1330ofFIG. 13and transistor250ofFIG. 9. When diode1330conducts and transmits a signal across the power adapter isolation barrier to transistor250, a signal is sent from transistor250to fault input238of buck power factor correction circuit232. This causes buck power factor correction circuit232to shut down the entire power adapter, including the high voltage output and FETs that enables power at the outputs of power adapter2000. For example, when DC output420is too high, diode1332will begin to conduct, driving current through diode1330, thereby sending the signal to transistor250and fault input238of buck power factor correction circuit232. Fault input238operates without an automatic restart for power adapter2000, thereby preventing additional damage that may occur with standard switching power supplies operating with single and lower power USB outputs, where current flows under a fault condition are less likely to cause damage. Because power adapter2000operates with a high current output, faults require removal of the AC input to restart power adapter2000and to prevent damage that may be caused by automated fault recovery from overvoltage and overcurrent conditions.

Similarly, monitoring circuit1340measures a voltage across resistor1342, which carries the output current to the USB outputs1360and1362. When the USB output current, and therefore the voltage across resistor1342exceeds a predetermined value, current monitoring circuit activates diode1334which enables comparator1350to set an output that activates diode1330. Diode1332will begin to conduct, driving current through diode1330, thereby sending the signal to transistor250and fault input238of buck power factor correction circuit232.

Additionally, resistors1344and1346divide the USB output voltage supplied to USB outputs1360and1362. When the voltage exceeds an amount determined by the circuit design, diode1336is activated to enable comparator1350to set an output that activates diode1330. Diode1332will begin to conduct, driving current through diode1330, thereby sending the signal to transistor250and fault input238of buck power factor correction circuit232.

In an alternative embodiment, power adapter2000may comprise a second USB switcher similar to USB switcher1380, a second circuit similar to monitoring circuit1340, and a third and fourth USB power supplies. The second USB switcher receives input power in the same fashion as the first USB switcher, and has overcurrent monitoring and voltage monitoring through circuits that duplicate the functionality described above in parallel to the functionality of the first USB switcher1380. When the second USB switcher experiences a fault, additional comparator circuitry is disposed to turn on diode1330in the same fashion done with comparator1350, with an extra level of logic to enable comparator1350and the inputs from the second USB switcher to send a fault signal via diode1330.

In addition to the specific functioning of the elements of power adapter2000described above, the operation of power factor correction circuit30, chipset regulator40, discrete second bus start up circuit20, and USB switcher110enabled with surface mount technology and a hybrid transformer that incorporates both foil windings and planar windings embedded in a PCB creates a power adapter with a higher power density than available previously in power adapters. In one embodiment, the power supply package ofFIGS. 1-7have the dimensions approximately 5 inches (or less) long by four inches (or more) wide by 0.3 to 0.8 inches high, which in conjunction with the innovations disclosed above and standard heat dispersion technology may enable power density greater than 12 W per cubic inch.

The figures described above detail one potential embodiment of the above described power adapter. The above description including all of the various circuit descriptions of the figures and the related description is illustrative and is not restrictive, and is indented to shown example embodiments illustrating implementations of the invention. Moreover, any one or more features of any embodiment of the invention may be combined with any one or more other features of any other embodiment of the invention, without departing from the scope of the invention. Any use of “a”, “an”, or “the” is intended to mean “one or more” unless specifically indicated to the contrary.

Many variations of the invention will become apparent to those skilled in the art upon review of the disclosure. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the pending claims along with their full scope or equivalents. One or more features from any embodiment may be combined with one or more features of any other embodiment without departing from the scope of the invention. Where approximate or “about” is described for measurements, embodiments herein also contemplate the exact measurement. Where a shape is disclosed, such as a rectangular surface, embodiments herein contemplate other suitable shapes, such as multi-sided blocks or rounded surfaces.