Flash memory device

The present invention relates to a flash memory device and, more particularly, to a flash memory device which can obtain the accurate and rapid current drive ratio by storing current drive ratio for some probable cases in the memory cell in advance, and selecting and using the most proper current drive ratio as required by means of external command.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a flash memory device and, more 
particularly, to a flash memory device which can control the current drive 
ratio of a sense amplifier by external commands. 
2. Information Disclosure Statement 
In general, in sensing data of a flash EPROM cell, sensing margin is 
determined by a drive ratio of current flowing through a reference cell. 
In a conventional sense amplifier circuit, there is a disadvantage in that 
in case where the current drive ratio of sense amplifier circuit is 
incorrectly designed, the sense amplifier circuit or a MASK program 
operation must be redesigned to adjust it so that a lost in time or 
economy is caused. 
SUMMARY OF THE INVENTION 
Therefore, it is the object of the present invention to provide a flash 
memory device which can solve the above described disadvantage by storing 
the current drive ratio for some probable cases in the memory cell in 
advance, and selecting and using the most proper current drive ratio as 
required by means of external command. 
A flash memory device according to the present invention to achieve the 
above described object comprises a ratio content block for outputting a 
first to fourth control signal having different current drive ratio 
according to a plurality of control signals and a select gate input signal 
inputted from external; a main cell block which takes as inputs said first 
and second control signals, and which outputs a fifth control signal 
according to said first and second control signals; a reference cell block 
which takes as inputs said third and fourth control signals, and which 
outputs a sixth control signal according to said third and fourth control 
signals; and a sense amplifier block which takes as inputs said fifth and 
sixth control signals, and which outputs data.

Similar reference characters refer to similar parts in the several views of 
the drawings. 
DETAILED DESCRIPTION OF THE DRAWINGS 
The present invention will be described in detail with reference to the 
accompanying drawings. 
FIG. 1 is a block diagram of a flash memory device according to the present 
invention. A ratio content block 1 takes as inputs a plurality of control 
signals A0HVB, A0HV, A1HVB, A1HV and select gate input signal VSG, and 
output a first to fourth control signals A to D having different current 
drive ratio. Among the first to fourth control signals A to D, the first 
and second control signals A,B are inputted to a main cell block 2 and the 
third and fourth control signals C,D are inputted to a reference cell 
block 3. The main cell block 2 outputs a fifth control signal ARY 
according to the first and second control signals A,B. The reference cell 
block 3 outputs a sixth control signal REF according to the inputted third 
and fourth control signals C,D. The fifth control signal ARY and sixth 
control signal REF are inputted to a sense amplifier block 4. The sense 
amplifier block 4 compares the inputted fifth and sixth control signals 
ARY, REF and outputs data to an output terminal SAout. 
FIG. 2 is a detailed circuit diagram of a ratio content block of FIG. 1, 
and the operation of it is as follows. 
A plurality of control signals A0HVB, A0HV, A1HVB, A1HV inputted from 
external are inputted to a first to fourth NAND gates ND1 to ND4 
respectively. A first to fourth enable signals EN1 to EN4 which are 
outputs of the first to fourth NAND gate ND1 to ND4 are selectively 
outputed according to a first to fourth inverter I1 to I4 according to the 
inputted plurality of control signals, A0HVB, A0HV, A1HVB, A1HV. The 
selectively outputted first to fourth enable signals EN1 to EN4 are 
inputted to a first to fourth memory cell blocks 11 to 14. In addition, 
the first to fourth enable signals EN1 to EN4 are inputted to a 4-input 
NOR gate NR1. An output of the 4-input NOR gate NR1 is inputted to a 
positive charge pump circuit 5 via a fifth inverter 15. At this time, the 
positive charge pump circuit 5 outputs a program gate voltage VPG 
according to the output of the 4-input NOR gate NR1. The program gate 
voltage VPG is inputted to the first to fourth memory cell blocks 11 to 
14. Therefore, one memory cell block selected by the first to fourth 
enable signals EN1 to EN4 is programmed. 
Eventually, the first to fourth memory cell blocks 11 to 14 outputs a first 
to fourth control signals A to D having different current drive ratio 
according to the plurality of control signals A0HVB, A0HV, A1HVB, A1HV 
inputted from external. 
FIG. 3 is a detailed circuit diagram of the memory cell block of FIG. 2. 
The operation of the memory cell block is described with reference to 
FIGS. 4A and 4B. 
A program enable signal EN becomes HIGH state at the time of programming so 
that the voltage of high state 5V is supplied to a drain electrode D of a 
memory cell 6. The program gate voltage VPG is supplied to a program gate 
electrode PG of the memory cell 6 at the time of programming. Ground 
voltage 0V inputted from a source sense block 7 is supplied to a source 
electrode S from a source. In addition, the program enable signal EN and 
the program enable signal EN which passed through an inverter 16 are 
respectively inputted to a first and second PMOS transistors P2, P1 
serially connected between a power source terminal Vcc and select gate 
voltage source VSG. At this time, the first PMOS transistor P1 turns on 
and the second PMOS transistor P2 turns off. Therefore, the program select 
gate voltage VSG is supplied to a select gate electrode SG of the memory 
cell 6. That is, as shown in FIG. 4A, to the select gate electrode SG is 
supplied 2V, to the program gate electrode PG is supplied +12V, to the 
drain electrode D is supplied 5V, and to the source electrode is supplied 
0V so that the memory cell 6 is programmed. 
On the other hand, at the time of read operation, the program enable signal 
EN becomes LOW state. At this time, the first PMOS transistor P1 is turned 
off, and the second PMOS transistor P2 is turned on. Therefore, the select 
gate voltage Vcc is supplied to the select gate electrode SG of the memory 
cell 6 at the time of reading. Therefore, the data of the memory cell 6 is 
outputted to the output terminal OUT through the source sense block 7. 
That is, as shown in FIG. 4B, to the select gate electrode SG is supplied 
5V, to the program gate electrode PG is supplied 5V, to the drain 
electrode D is supplied 0V, and to the source electrode is supplied 5V so 
that the read operation of the memory cell 6 is performed. 
As described above, the present invention has an excellent effect that the 
accurate and rapid current drive ratio can be obtained by storing the 
current drive ratio for some probable cases in the memory cell in advance, 
and selecting and using the most proper current drive ratio as required by 
means of external command. 
The foregoing description, although described in its preferred embodiment 
with a certain degree of particularity, is only illustrative of the 
principles of the present invention. It is to be understood that the 
present invention is not to be limited to the preferred embodiments 
disclosed and illustrated herein. Accordingly, all expedient variations 
that may be made within the scope and spirit of the present invention are 
to be encompassed as further embodiments of the present invention.