Time delay apparatus

A time delay apparatus for generating a plurality of phase shifted signals is described comprising a phase tuner generating a phase control signal and a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by phase shifting the digital signal according to the phase control signal.

The invention relates to a time delay apparatus.

In wireless transmitter and receiver systems, beam forming or beam steering may be accomplished by switching antenna elements or by changing the relative phases of the radio frequency signals driving the antenna elements. Current beam forming or beam steering methods in the analog domain require phase shifters. An alternative is the conversion to the optical domain because of the higher resolution at optical frequencies. These methods are often bulky and not power efficient. Further, state of the art phase shifters are limited in bandwidth. Wide band phase shifters can be implemented using switches to fixed delay transmission lines such as microstrips and Monolithic Microwave Integrated Circuits (MMICs). However, this comes at the expense of size and cost.

A good beam steering performance can be achieved at the digital domain by using direct digital synthesizers (DDS) or even Digital Signal Processors (DSPs). However, this leads to a high power consumption and a high complexity and thus to high cost and is not suitable for mobile applications.

In [1], it is described to use an array of DDS coupled to an array of Digital to Analog Converters (DACs) for the generation of phase interpolated signals. Each DDS generates a digital sine wave signal representing the transmit signal. Each of the digital sine waves generated by the DDS is characterized by a frequency value and a phase value. Each of these values is independently controllable by digital control of the DDS that generates the sine wave. The phase relationship between each DDS is maintained by the use of a common clock signal. A DAC is used to generate an analog signal is responsive to the digital sine wave signal. This analog signal is operatively coupled to a corresponding radiator element. This method requires a number of N DDS and DACs for the generation of N phase interpolated signals. This results in a demand for a large chip area and high power consumption.

In [2], a method for interpolating clock signals to generate multi phase clocks for applications in microprocessors is described. Conventionally, phase lock loops (PLLs) and delay lock loops (DLLs) and clock distribution networks have been used to generate multi-phased clocks for microprocessor applications. In [2], also PLLs/DLLs with delay circuits are used to perform phase interpolation. Further, a clock generator is used for generating a clock that is synchronised with a reference clock. A control signal is generated that is responsive to the phase difference between the reference clock and the generated clock. A delay circuit is used for generating a multi-phase clock based on the clock and the control signal. The clock generator generates a signal having a frequency equal to an integral multiple of the frequency of the reference clock and outputs the signal as the clock. The delay circuit has a circuit receiving the clock and including a series of delay elements in form of a cascade each giving a delay according to the control signal. Signals output from the series of delay elements are used as signals constituting the multi-phase clock. This method requires a series of delay elements and phase interpolation to have an integer relationship with the reference clock.

A time delay apparatus for generating a plurality of phase shifted signals is provided comprising a phase tuner generating a phase control signal and a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by phase shifting the digital signal according to the phase control signal.

Further, a time delay apparatus for generating a plurality of phase shifted signals is provided comprising a comparator receiving at least one wave signal and generating at least one digital signal by shaping the at least one wave signal, a phase tuner generating a phase control signal, and a phase interpolator receiving the at least one digital signal and generating the plurality of phase shifted signals by phase shifting the digital signal according to the phase control signal.

Illustratively, the phase tuner controls a phase control signal based on which the phase interpolator phase shifts the digital signal such that a shifted signal is generated. By performing various phase shifts of the digital signal, for example by phase shifting the digital signal according to various multiples of a phase difference specified by the phase control signal, a plurality of phase shifted signals is generated.

In contrast to the system described in [2], the time delay apparatus has the flexibility of variable time delay without being tied to a reference clock. No integer relationship with a reference clock is necessary. Therefore, the time delay apparatus may be used for beam-steering applications.

In one embodiment, a programmable time delay apparatus for generating a plurality of phase interpolated signals is provided comprising an analog to digital converter for shaping a plurality of parallel signals, a parallel to serial converter for converting the plurality of parallel signals to a plurality of serial signals, at least one phase interpolator for phase shifting the plurality of serial signals in response to a phase control signal to generate a plurality of phase shifted signals, a phase tuner for generating the phase control signal, a buffer for buffering the plurality of phase shifted serial signals, a serial to parallel converter for converting the plurality of phase shifted serial signals to a plurality of phase shifted parallel signals, and an array of buffers for buffering the plurality of phase shifted parallel signals.

In one embodiment, a transmission method is provided wherein each output from the time delay apparatus described above is buffered by at least one high-speed buffer to obtain fast rise and/or fast fall times and is further pulse shaped using at least one pulse forming network.

The outputs generated in this way may be fed to an array of antenna for beamsteering. A switch may be used to select one of the outputs and to connect the selected output to one of the antennas in an antenna array for beamsteering.

In one embodiment, a transmission method is provided according to which one of the outputs of the time delay apparatus described above and an external ultrawideband pulse signal are selected and both are fed to a mixer or a multiplier to produce a correlated output for beamsteering at reception.

In another embodiment, a transmission method is provided according to which an ultrawideband signal is delayed at a certain pulse repetition interval using the time delay apparatus described above and is correlated with the input signal of the time delay apparatus for maximum energy.

Embodiments of the invention emerge from the dependent claims.

The phase tuner is for example a phase locked loop. The phase locked loop may comprise a voltage controlled oscillator and the voltage input to the voltage controlled oscillator for controlling the frequency of the oscillation output by the voltage controlled oscillator may be the phase control signal.

Alternatively, a DLL (delay locked loop) may be used as phase tuner.

In one embodiment, the voltage controlled oscillator generates a first clock signal and the phase locked loop further comprises a receiving means for receiving a second clock signal, a phase comparator for comparing the phase difference between the first clock signal and the second clock signal to produce a digital error signal, a charge pump for converting the digital error signal to an analog error signal, a low pass filter for filtering the analog error signal to produce the phase control signal, and a frequency divider for dividing the first clock signal.

The digital error signal is for example a digital error pulse signal. The analog error signal is for example an analog error current.

In one embodiment, the phase control signal specifies a phase difference and the phase difference is programmable by setting a factor by which the frequency divider divides the first clock signal.

The time delay apparatus may further comprise a buffer for buffering the plurality of phase shifted signals.

In one embodiment, the time delay apparatus further comprises a comparator receiving at least one wave signal and generating the at least one digital signal by shaping the at least one wave signal.

The comparator is for example an analog to digital converter. The phase control signal may specify a phase difference and each phase shifted signal of the plurality of phase shifted signals may be generated by the phase interpolator by phase shifting the digital signal according to multiple of the phase difference.

In one embodiment, the digital signal is random (arbitrary). It may for example be generated pseudo-randomly. Similar, the wave signal may be random (arbitrary) and may be generated pseudo-randomly.

FIG. 1shows a transmitter100according to an embodiment of the invention.

The transmitter comprises a variable time delay apparatus101which comprises a clock generator102and a phase interpolated delay element103. The clock generator102receives as input a reference clock signal104and a phase select signal105and generates a control signal106which is fed to the phase interpolated delay element103.

In addition to the control signal106, the phase interpolated delay element103receives an input pulse signal107as input which is variable (and may for example be a pseudo-random digital signal). The phase interpolated delay element103generates a plurality of phase shifted signals108which are each fed into a pulse forming network109.

The pulse forming networks109generate radio pulses which are fed to an antenna array110. Based on the generated radio pulses, beam forming and/or beam steering is performed.

The plurality of phase shifted signals108according to one embodiment of the invention is illustrated inFIG. 2.

FIG. 2shows a plurality of signals200according to an embodiment of the invention.

The plurality of signals200consists of N signals201which are denoted by F1, F2, . . . , FN. Every two of the signals201are phase shifted by a phase shift202denoted by ΔPh. This means that F2is phase shifted with respect to F1by ΔPh, F3is phase shifted with respect to F2by ΔPh and so on. FN is phase shifted with respect to FN−1 by ΔPh. This means that FN is phase shifted by N−1 times ΔPh with respect to F1.

As mentioned above, the signals201may be generated by a variable time delay apparatus101as shown inFIG. 1. In one embodiment, the variable time delay apparatus101is implemented as shown inFIG. 3.

FIG. 3shows a time delay apparatus300according to an embodiment of the invention.

The output of the time delay apparatus300is a plurality of signals301corresponding to the plurality of signals200denoted by F1to FN.

The size of the phase shift ΔPh of the plurality of signals301as explained above with reference toFIG. 2is defined by a plurality of input bits302, denoted by Y. By setting the plurality of input bits302the time delay apparatus300may be programmed such that the phase shift ΔPh has a certain value, for example to a phase shift between 100 psec and 500 psec. The plurality of input bits302may for example be a binary representation of the resulting phase shift. In this way, the time delay apparatus300is digitally programmable for a desired phase shift. The plurality of the input bits302correspond to the phase select signal105shown inFIG. 1.

The plurality of input bits302is fed into a control logic303which interprets the plurality of input bits302and provides a corresponding control signal311to a phase locked loop (PLL)304.

In addition to the control signal311, the phase locked loop receives a reference clock signal305(denoted by MCLK) as input which corresponds to the reference clock signal104shown inFIG. 1.

The phase locked loop304comprises a frequency divider306, a phase frequency detector307, a charge pump308, a low-pass filter309and a voltage controlled oscillator310. The phase locked loop304corresponds to the clock generator102shown inFIG. 1.

The frequency divider306divides the frequency of a signal output from the voltage controlled oscillator310by a number of times specified by the control signal311. The phase frequency detector307compares the phases between the output of the frequency divider306and the reference clock signal305and outputs a signal responsive to the phase difference to the charge pump308. The charge pump308converts the (digital) output signal of the phase frequency detector307to a (analog) voltage responsive to the phase difference which is fed into the low-pass filter309. The low-pass filter309outputs the low-frequency component of the input voltage to the voltage controlled oscillator310. The output of the low-pass filter309is also input as control voltage312to a phase interpolator313.

The control voltage312contains phase shift information corresponding to the result of the phase comparison performed by the phase frequency detector307. The control voltage312corresponds to the control signal106.

The time delay apparatus300further comprises a comparator314. The comparator compares a pulse signal315to a reference signal316. By comparing the pulse signal315with the reference signal316, which is in one embodiment chosen constant, the comparator generates a digital signal318(for example square-like or rectangular-like) which corresponds to the signal denoted by F1. Illustratively, the comparator shapes up the pseudo-random pulse signal315to a square wave. The pulse signal315is in one embodiment pseudo-random.

The control voltage312specifies the phase shift ΔPh. Since the phase locked loop304is a feedback system, it ensures that there is minimal drift in the generated phase shift ΔPh.

Every programming of the phase shift (by setting the plurality of input bits) requires the phase locked loop304to re-acquire lock. In one embodiment the worst case lock time for the phase locked loop304(from power up) is 50 μsecs.

Using the phase shift information embedded into the control voltage312, the phase interpolator generates the plurality of output signals301. These may be buffered by a buffer317for off-chip driving capabilities. In one embodiment, high-speed buffers are used to obtain fast rise and fall times in addition to off-chip driving capabilities. An example of a simulated system specification is summarized below.

In one embodiment, the phase interpolator313is implemented by a plurality of phase interpolators, each generating one of the output signals of the plurality of output signals by phase shifting the digital signal318.

The phase interpolator313is in one embodiment a modified version of the voltage controlled oscillator310. Illustratively, the voltage controlled oscillator310is a closed loop. The phase interpolator313gives an open loop response.

In one embodiment, the time delay system300has the following technical characteristics.

Phase tuning

With this characteristics, the time delay system300is capable of generating pulses with fast risetime and/or fast falltime for beam forming or beam steering. In particular, the plurality of signals301may be used for ultra wide band (UWB) beam forming or beam steering. UWB is typically defined as a minimum of 20% of the bandwidth or at least 500 MHz.

The application of the transmitter100shown inFIG. 1to ultra wide band is illustrated byFIG. 4.

FIG. 4shows a first pulse forming network400according to an embodiment of the invention.

The pulse forming network400corresponds to one of the pulse forming networks109shown inFIG. 1. One signal of the plurality of signals301generated by the time delay system300is used as input signal401to the first pulse forming network400.

The risetime, which is for example 60 psec, is used by the pulse forming network, which for example performs a differentiation, to produce one or more UWB pulses.

Switches with two ports may be provided between the outputs of the pulse forming networks109and the antenna array110such that only one of the UWB pulses output from a pulse forming network109is selected and connected to only one of the antenna elements of the antenna array110to form another beamsteering sub-system. A plurality of these sub-systems may be used to steer a beam using a plurality of time delays.

In ultra wideband radar operations, it is important to control the time delay of high-speed radio pulses for correlation. An example for such an application of a variable time delay system in a receiver is shown inFIG. 5.

FIG. 5shows a system processing system500according to an embodiment of the invention.

The processing system500may be part of a receiver and comprises a first time delay module501and a second time delay module502. The first time delay module501and the second time delay module502are different from the time delay apparatus300shown inFIG. 3in that they receive a signal which is delayed, i.e. phase shifted, by a time T1(first time delay module) and a time T2(second time delay module), respectively.

The first time delay module501and the second time delay module502may be programmable to set the introduced phase shifts, i.e. to set the times T1and T2, in a similar way as the time delay apparatus300.

A received signal503is divided by a divider504and fed into the first time delay module502, a first multiplier (or mixer)505, the second time delay module502and a second multiplier (or mixer)506.

The received signal is delayed by the time T1by the first time delay module501and the delayed received signal is then correlated with the (original) received signal503by the first multiplier505to maximize the correlated output energy.

Further, the received signal is delayed by the time T2by the second time delay module502and the delayed received signal is then correlated with the (original) received signal503by the second multiplier506. The time T2represents the time delay required to correlate the received signal503for maximum energy when the position of a moving target is tracked.

The output of the first multiplier505and the second multiplier506are fed into an analog or digital processing unit507.

The invention is also applicable to other types of communication or radar systems shere variable time delay operations are required.

In one embodiment, an analog to digital converter (ADC) is used instead of the comparator314to generate input digital signals. This is illustrated inFIG. 6.

FIG. 6shows a time delay system600according to an embodiment of the invention.

The time delay system600is similar to the time delay system300shown inFIG. 3. The time delay system600comprises a phase locked loop604and a control logic603with the same functionality as the phase locked loop304and the control logic303as described above with reference toFIG. 3. In particular, the phase locked loop generates a control voltage612.

Similar to the time delay system300, the time delay system600receives a pulse signal615and a reference signal616as input. However, the pulse signal615and the reference signal616are not compared, but the pulse signal615is converted from analog to digital by an analog to digital converter614. According to the conversion of the pulse signal615, the analog to digital converter614generates a plurality of digital signals618each digital signal618corresponding to one bit of the output of the analog to digital converter614.

Similar to the digital signal318shown inFIG. 3, each digital signal618is phase shifted by a phase interpolator619to generate a plurality of phase shifted output signals601.

Each plurality of phase shifted output signals601may be buffered by a corresponding buffer620.

The phase interpolators619all derive the same phase shift information from the control voltage612.

The time delay apparatus300may be modified by using a parallel-to-serial converter and/or a serial-to-parallel-converter as shown inFIG. 7.

FIG. 7shows a time delay apparatus700according to an embodiment of the invention.

The time delay system700is similar to the time delay system700shown inFIG. 6. The time delay system700comprises a phase locked loop704and a control logic703with the same functionality as the phase locked loop304and the control logic303described above with reference toFIG. 3. In particular, the phase locked loop generates a control voltage712.

As the time delay apparatus600, the time delay apparatus700comprises an analog to digital converter714adapted to convert a pulse signal715using a reference signal716. The output of the analog to digital converter714is converted by a parallel to serial converter718to a serial stream of bits which has the form of a digital signal. The serial stream of bits is phase shifted by a phase interpolator713using the control voltage712to generate a plurality of output signals701as it is done with the digital signal318by the phase interpolator713shown inFIG. 3. Similar to above, the plurality of output signals701may be buffered by a buffer717.

The output of the phase interpolator713is also converted from serial to parallel by a serial to parallel converter719. The output of the serial to parallel converter is a set of interpolated ADC outputs. These outputs may be bufferd using a buffer array720for off-chip driving capabilities.