Analog-to-digital converter and image sensor

An analog-to-digital converter has a sampler to hold a sampled signal, an input signal predictor to generate a prediction signal at predetermined timing before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal, a comparator to compare signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal lever of the sampled signal, a first counter to perform a count operation in synchronism with a first clock signal within a period from start of a comparison operation by the comparator to generation of the prediction signal, and a second counter to perform a count operation in synchronism with a second clock signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2014-1481, filed on Jan. 8, 2014, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments of the present invention relate to an integral analog-to-digital converter and an image sensor provided with the analog-to-digital converter.

BACKGROUND

An integral analog-to-digital converter (ADC) using a time-to-digital converter (TDC) has been proposed. This type of integral ADC performs fine A/D conversion using TDC in addition to coarse A/D conversion using a ramp signal to increase the resolution of A/D conversion and speed up the A/D conversion.

However, TDC requires a high-speed clock signal. Thus, if a high-speed clock signal is supplied to TDC while performing coarse A/D conversion using a ramp signal, a consumption power increases.

Moreover, different clock signals are used for coarse A/D conversion using a ramp signal and fine A/D conversion using TDC. Thus, A/D conversion performance may be lowered due to phase difference between both clock signals.

DETAILED DESCRIPTION

An analog-to-digital converter according to one embodiment has a sampler to hold a sampled signal obtained by sampling an input signal for each specific time, an input signal predictor to generate a prediction signal at predetermined timing before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal, a comparator to compare signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal lever of the sampled signal, a first counter to perform a count operation in synchronism with a first clock signal within a period from start of a comparison operation by the comparator to generation of the prediction signal, and a second counter to perform a count operation in synchronism with a second clock signal having a higher frequency than the first clock signal after the generation of the prediction signal and to increase or decrease a count value in accordance with the comparison signal.

First Embodiment

FIG. 1is a block diagram schematically showing the configuration of an analog-to-digital converter1according to a first embodiment. The analog-to-digital converter1ofFIG. 1is provided with a sampler2, a ramp signal generator3, an input signal predictor4, a comparator5, a Fine counter6, and a Coarse counter7.

The sampler2holds a sampled signal obtained by sampling an input signal per specific period of time. The ramp signal generator3generates a ramp signal. The ramp signal is a signal whose signal level monotonically increases or decreases with time. In other words, the ramp signal is a signal whose output voltage increases by Δv while a time Δt passes or a signal whose output voltage decreases by Δv while Δt passes.

The ramp signal generator3may be configured with an integrator. In the case of the integrator, Δt is one clock period and Δv represents an integrated voltage within one clock period. The ramp signal generator3starts a ramp-signal generation operation after the integrator is released from a reset operation.

The input signal predictor4generates a prediction signal at a predetermined timing before the signal level of a ramp signal crosses the signal level of a sampled signal. Generation of the prediction signal means setting the prediction signal to a specific logic. The input signal predictor4outputs the prediction signal of the specific logic when the signal level of the ramp signal becomes closer to the signal level of the sampled signal.

The comparator5compares the signal level of the ramp signal and the signal level of the sampled signal to output a signal indicating a comparison result, i.e. to output a comparison signal showing whether the ramp signal is larger than the ramp signal. The comparator5outputs, for example, 1 when the signal level of the sampled signal becomes equal to or higher than the signal level of the ramp signal.

In more detail, the comparator5performs two kinds of comparison process. In the first comparison process, the comparator5performs a comparison process between a bias signal and a sampled signal or between a bias signal and a ramp signal. In the second comparison process, the comparator5performs a comparison process between a ramp signal and a sampled signal.

The Coarse counter7performs a count operation (for example, a count-up operation) in synchronism with a first clock signal within a period from the start of a comparison operation by the comparator5to the generation of a prediction signal. The Coarse counter7starts a count operation when released from a reset mode in response to a reset signal whose logic has changed into a specific logic. The Coarse counter7stops the count operation and holds a count value counted just before the stoppage when the comparator5performs the second-time comparison process to detect signal level crossing of a ramp signal and a sampled signal. The held count value is a coarse A/D conversion value.

For example, it is supposed that the output of the Coarse counter7is ADO when the ramp signal has an inclination of Vref[V]/T[μsec] and the first clock signal has a frequency of 2N/T[μsec]. A ramp signal voltage Vramp (ADO) when the output of the Coarse counter7is ADO is expressed by the following formula (1).

After the prediction signal is generated, the Fine counter6performs a count operation in synchronism with a second clock signal having a higher frequency than the first clock signal and increases or decreases a count value in accordance with a comparison result (comparison signal) of the comparator5.

The Fine counter6has stopped a count operation until the signal level of a sampled signal becomes closer to the signal level of a ramp signal. However, the Fine counter6starts a count operation when the prediction signal is generated, indicating that the signal level of the sampled signal becomes closer to the signal level of the ramp signal.

The Fine counter6performs a count operation at a higher speed than the Coarse counter7, and hence consumes more power than the Coarse counter7. However, the Fine counter6performs a count operation for a shorter period than the Coarse counter7. Therefore, an increase in power consumed by the Fine counter6can be suppressed.

FIG. 2is a block diagram showing a detailed concrete example of the analog-to-digital converter1according to the first embodiment.FIG. 3is a chart of signal waveforms of the analog-to-digital converter1ofFIG. 2.

The analog-to-digital converter1ofFIG. 2has a bias signal generator8, a signal switch9, and a toggle circuit10, as the internal configuration of the input signal predictor4ofFIG. 1.

The bias signal generator8generates a bias signal obtained by converting the signal level of the ramp signal generated by the ramp signal generator3. The signal level conversion includes increasing and decreasing the signal level of the ramp signal by a specific level. However, in this specification, the bias signal generator8generates a bias signal obtained by increasing the signal level of the ramp signal by a specific level, as shown inFIG. 3.

As shown inFIG. 2, a reset signal is input to the ramp signal generator3and the Coarse counter7. The ramp signal generator3and the Coarse counter7are released from a reset mode at time t1ofFIG. 3. After time t1, the ramp signal generator3generates the ramp signal and the Coarse counter7starts a count operation.

Based on a signal logic held by the toggle circuit10, the signal switch9is switched to select either one of the ramp signal generated by the ramp signal generator3and the bias signal generated by the bias signal generator8and supplies the selected signal to the comparator5.

At time t1, the toggle circuit10outputs a low-level output signal, so that the signal switch9selects the bias signal and then the comparator5compares the bias signal and a sampled signal. As described above, the bias signal is obtained by raising the signal level of the ramp signal. Thus, the signal levels of the bias signal and the sampled signal cross each other at a higher timing than the signal levels of the ramp signal and the sampled signal. In other words, this means that the timing of signal level crossing of the ramp signal and the sampled signal is predicted by comparing the bias signal and the sampled signal to detect the timing of signal level crossing of the bias signal and the sampled signal. In this embodiment, at the moment when signal levels of the bias signal and the sampled signal cross each other, the input signal predictor4generates the prediction signal. This prediction signal is generated while the toggle circuit10is outputting a high-level output signal. In this way, the predetermined timing is set by the signal level of the bias signal.

The toggle circuit10inverts the initial signal and holds the inverted signal when the comparator5outputs a signal whose logic has changed into a specific logic indicating a comparison result (comparison signal), that is an output signal of the comparator5at the timing when signal levels of the bias signal and the sampled signal cross each other. The initial signal is, for example, at a low level. The toggle circuit10inverts the low-level initial signal to output a high-level signal when the comparator5outputs a signal whose logic has changed into a specific logic. The toggle circuit10may be configured with a toggle flip-flop (TFF), a D flip-flop (DFF), etc.

In the example ofFIG. 3, signal levels of the bias signal and the sampled signal cross at time t2and then the comparator5outputs a high-level signal. When the comparator5outputs a high-level signal, the toggle circuit10holds its level to output a high-level signal.

The signal held by the toggle circuit10is used as a signal for the Fine counter6to start a count operation, that is, a signal for the Fine counter6to be released from a reset mode. Therefore, the Fine counter6starts a count operation when the toggle circuit10performs a hold operation.FIG. 3shows that the Fine counter6performs a count operation at a higher cycle than the Coarse counter7after time t2.

The signal held by the toggle circuit10is also used for signal switching by the signal switch9. As shown inFIG. 3, at time t2, the signal switch9selects a ramp signal and supplies the signal to the comparator5. Therefore, after time t2, the comparator5compares the signal levels of the ramp signal and the sampled signal.

Thereafter, at time t3, the signal level of the ramp signal crosses with the signal level of the sampled signal. With this signal level crossing, as shown inFIG. 3, the output logic of the comparator5changes again to be a high level which causes the inversion of the output logic of the toggle circuit10. With the inversion of the output logic of the toggle circuit10, the Fine counter6stops a count operation and holds the count value obtained just before the stoppage.

At time t3, the signal switch9selects the bias signal again. Thus, after time t3, the comparator5compares the signal levels of the bias signal and the sampled signal. As understood fromFIG. 3, since the bias signal has a higher signal level than the sampled signal, the Coarse counter7does not perform a count operation after time t3.

As described above, the comparator5ofFIG. 2performs signal level comparison between the ramp signal and the sampled signal, and also between the bias signal and the sampled signal. The order of a comparison process is such that the comparator5compares, firstly, the signal levels of the bias signal and the sampled signal, and then the signal levels of the ramp signal and the sampled signal.

In other words, the comparator5ofFIG. 2performs signal level comparison between the bias signal and the sampled signal, which should be basically performed inside the input signal predictor4. Therefore, there is no necessity of providing a comparator inside the input signal predictor4, hence the internal configuration of the input signal predictor4can be simplified.

FIG. 4is a block diagram of an analog-to-digital converter1that is a more concrete version ofFIG. 2. InFIG. 4, a switch11and a capacitor12have the bias signal generator8ofFIG. 2. The switch11switches a bias voltage to be supplied to one end of the capacitor12or the signal switch9in accordance with the logic of a bias-voltage setting signal. To the other end of the capacitor12, the ramp signal is supplied and the signal switch9is connected.

In the initial state, the capacitor12is charged in accordance with the ramp signal. For example, when the bias-voltage setting signal becomes high, the voltage at the other end of the capacitor12has a voltage value obtained by the addition of a voltage of the ramp signal and the bias voltage, thereby the bias signal being generated.

InFIGS. 1 to 4, the bias voltage is generated by converting the signal level of the ramp signal. However, the bias voltage may also be generated by converting the signal level of a sampled signal.

FIG. 5is a block diagram of an analog-to-digital converter1according to a modified version ofFIG. 1. A bias signal generator8ofFIG. 5generates a bias voltage by converting the signal level of a sampled signal. The signal switch9is switched to select either the sampled signal sampled by the sampler2or the bias signal generated by the bias signal generator8based on a signal logic held by the toggle circuit10and supplies the selected signal to the comparator5. The comparator5compares the signal level of the sampled signal or bias signal selected by the signal switch9and the signal level of a ramp signal generated by the ramp signal generator3.

It is required for the input signal predictor4to generate a prediction signal at a predetermined timing before the signal levels of the ramp signal and the sampled signal cross each other. Thus, in the case of using a ramp signal having a tendency of monotonic increase as shown inFIG. 2, the bias signal generator8ofFIG. 5generates the bias signal that is obtained by decreasing the signal level of the sampled signal by a specific level. In this way, at the same timing asFIG. 2, the Fine counter6can start a count operation after the generation of the prediction signal.

As described above, in the first embodiment, the bias signal is generated by converting the signal level of the ramp signal or sampled signal and the prediction signal is generated by detecting the timing at which the signal level of the bias signal crosses the signal level of the sampled signal or ramp signal. Before the generation of a prediction signal, the Coarse counter7performs a coarse A/D conversion process and, after the generation of the prediction signal, the Fine counter6performs a fine A/D conversion process. Accordingly, it is possible to perform a high-resolution A/D conversion process and shorten the operation time of the Fine counter6that operates in synchronism with a high-speed second clock signal, thereby decreasing consumed power.

Second Embodiment

When the signal switch9ofFIG. 2 or 5performs switching between two input signals, the input signal level of the comparator5may temporarily fluctuate largely.FIG. 6is an equivalent circuit diagram of a signal path that connects the signal switch9and the comparator5.FIG. 7is a chart of a signal waveform along the signal path.

A wiring resistance R and an input capacitance C of the comparator5exist on the signal path that connects the signal switch9and the comparator5. When the input capacitance C of the comparator5is large, the signal level on the signal path rapidly fluctuates due to a settling operation to charge the input capacitance C. That is, when the signal switch9performs signal switching and thus the signal level of a signal supplied to the comparator5rapidly varies, the output voltage of a low-path filter having the wiring resistance R and the input capacitance C of the comparator5ofFIG. 6shows step response characteristics expressed by the following formula (2).
output voltage=difference voltage between signal levels×(1−et/CR)  (2)

where t is an elapsed time, C is the input capacitance C of the comparator5and R is the wiring resistance R. A signal waveform of the formula (2) is such as shown inFIG. 7.

As understood from the formula (2), the time constant of the low-path filter having the wiring resistance R and the input capacitance C of the comparator5is decided by CR. Thus, when both of the input capacitance C and the wiring resistance R are large, the comparator5may output an erroneous comparison result (comparison signal) at the moment at which the Fine counter6starts a count operation, which gives an adverse effect to an A/D conversion performance. A fine A/D conversion process may be performed after temporary signal drop such as shown inFIG. 7ceases, which however takes time for A/D conversion and escalates power consumption.

For the reason above, it is considered to use a 3-input comparator13into which the signal switch9and the comparator5ofFIG. 2 or 5are unified.FIG. 8is a block diagram of an analog-to-digital converter1having a 3-input comparator13in place of the signal switch9and the comparator5ofFIG. 5. To the 3-input comparator13, a sampled signal, a ramp signal and a bias signal are input, and also the output signal of the toggle circuit10is input. The 3-input comparator13selects either the sampled signal or the bias signal based on the logic of the output signal of the toggle circuit10and compares the selected signal and the ramp signal.

As to the circuit operation,FIG. 8is similar toFIG. 5. However, inFIG. 8, the input signal of the comparator5does not vary rapidly when the 3-input comparator13performs signal switching.

FIG. 9is a circuit diagram showing an example of the internal configuration of the 3-input comparator13. The 3-input comparator13has a 3-input preamplifier14and a latch15that latches the output of the preamplifier14.

The preamplifier14is a 3-input differential amplifier and has a first impedance element21connected between a power supply voltage node Vcc and a first output node OUT1, a second impedance element22connected between the power supply voltage node Vcc and a second output node OUT2, a first transistor24and a second transistor25connected in series between the first output node OUT1and one end of a current source23, a third transistor26and a fourth transistor27connected in series between the first output node OUT1and the one end of the current source23, a fifth transistor28and a sixth transistor29connected in series between the second output node OUT2and the one end of the current source23, and an inverter30that inverts the output signal of the toggle circuit10.

A sampled signal is supplied to the gate of the second transistor25, a bias signal is supplied to the gate of the fourth transistor27, and a ramp signal is supplied to the gate of the sixth transistor29. The output signal of the toggle circuit10is supplied to the gate of the first transistor24and the output signal of the inverter30is supplied to the gate of the third transistor26. The gate of the fifth transistor28is set to a power supply voltage.

In the 3-input comparator13ofFIG. 9, a current flows through either the first and second transistors24and25or the third and fourth transistors26and27, depending on the logic of the output signal of the toggle circuit10. A differential voltage in accordance with difference between the above-mentioned current and a current flowing through the fifth and sixth transistors28and29is output from the first and second output nodes OUT1and OUT2.

In the 3-input comparator13ofFIG. 9, the current flowing through the first impedance element21does not vary rapidly when the logic of the output signal of the toggle circuit10changes. It is thus considered that temporary signal drop such as shown inFIG. 7does not occur in principle.

When the 3-input comparator13ofFIG. 9is actually designed, the first and third transistors24and26may be fabricated to be smaller than the second, fourth and sixth transistors25,27and29. Since the 3-input comparator13ofFIG. 9has an offset voltage, an offset cancelling circuit may be added. In the case of adding a circuit for storing only one kind of offset voltage, the circuit may store an offset voltage for a transistor whose gate is supplied with a sampled signal or a ramp signal, but may not need to store an offset voltage for a transistor whose gate is supplied with a bias signal. The reason is that bias-signal offsetting does not affect the conversion accuracy of the analog-to-digital converter1.

As described above, in the second embodiment, signal switching and comparison are performed with the 3-input comparator13. Thus, there is no problem such that the signal level of an input signal to the comparator5varies rapidly just after signal switching, and hence stable A/D conversion process can be performed.

Third Embodiment

A third Embodiment which will be explained below has two types of comparators5.

FIG. 10is a block diagram schematically showing the configuration of an analog-to-digital converter1according to the third embodiment.FIG. 11is a chart of waveforms of the analog-to-digital converter1ofFIG. 10. The analog-to-digital converter1ofFIG. 10is provided with a first comparator5aand a second comparator5bin place of the signal switch9and the comparator5ofFIG. 1, the other configuration being the same asFIG. 1.

The first comparator5acompares the signal levels of a bias signal and a sampled signal to output a signal indicating a comparison result, i.e. to output a comparison signal showing whether the bias signal is larger than the sampled signal. The second comparator5bcompares the signal levels of a ramp signal and the sampled signal to output a signal indicating a comparison result, i.e. to output a comparison signal showing whether the ramp signal is larger than the sampled signal.

When released from a reset mode, the ramp signal generator3starts the generation of a ramp signal (time t1inFIG. 11), firstly, the first comparator5astarts a comparison process and the Coarse counter7starts a count operation. When the output signal of the first comparator5ais inverted (time t2), that is, when the signal levels of the bias signal and the sampled signal cross each other, the second comparator5bstarts a comparison process and the Fine counter6starts a count operation. Thereafter, when the output signal of the second comparator5bis inverted (time t3), the Coarse counter7and the Fine counter6both stop the count operation.

InFIG. 5, instead of the signal switch9and the comparator5, a first comparator5aand a second comparator5bsuch as shown inFIG. 10may be provided.

As described above, in the third embodiment, the first comparator5aand the second comparator5breceive different signals and perform a comparison process independently. Thus, there is no need to switch the signals to be compared like the first embodiment. Therefore, the input signals of the first comparator5aand the second comparator5bdo not vary rapidly, and hence there is no problem such that the signal indicating a comparison result (comparison signal) temporarily fluctuates largely, which is a problem in the first embodiment. Accordingly, a high-resolution A/D conversion process can be performed stably.

Fourth Embodiment

A fourth embodiment which will be explained below is to supply a minimum necessary amount of power to the second comparator5bexplained in the third embodiment

FIG. 12is a block diagram schematically showing the configuration of an analog-to-digital converter1according to the fourth embodiment. In addition to the configuration ofFIG. 10, the analog-to-digital converter1ofFIG. 12has a power switch16that is switched to supply a power to the second comparator5bor not. When the first comparator5adetects that the signal levels of the bias signal and the sampled signal cross each other and then the toggle circuit10outputs a logic-inverted signal, the power switch16supplies a power to the second comparator5b. Accordingly, the second comparator5bcompares the signal levels of the sampled signal with the ramp signal at the timing at which the Fine counter6starts a count operation.

As described above, in the fourth embodiment, a power is supplied to the second comparator5bwhile the Fine counter6is performing a count operation so that the second comparator5bconsumes a minimum amount of power. Therefore, it is possible to reduce a consumed power more than the third embodiment.

Fifth Embodiment

A fifth embodiment which will be explained below is to generate a high-speed second clock signal to be used for operating the Fine counter6, inside the analog-to-digital converter1a,

FIG. 13is a block diagram schematically showing the configuration of an analog-to-digital converter1according to the fifth embodiment. The analog-to-digital converter1ofFIG. 13has a high-speed clock generator31in addition to the configuration ofFIG. 1. The high-speed clock generator31generates a high-speed second clock signal when the input signal predictor4generates the prediction signal. In other words, the high-speed clock generator31starts the generation of the second clock signal after the signal level of the bias signal obtained by converting the signal level of the ramp signal and the signal level of the sampled signal cross each other. The Fine counter6starts a count operation in synchronism with the second clock signal generated by the high-speed clock generator31.

The second clock signal is a higher speed signal than the first clock signal that operates the Coarse counter7. It is thus conceivable, as a circuit for generating the second clock signal, to provide a multi-phase clock generator for generating multi-phase clock signals obtained by shifting a reference clock signal little by little and a decoder for sequentially selecting the multi-phase clock signals to generate the second clock signal. However, this results in a complicated circuit configuration. Therefore, this embodiment is provided with the high-speed clock generator31that generates the second clock signal with a simple circuit configuration.

FIG. 14is a circuit diagram showing an example of the internal configuration of the high-speed clock generator31. The high-speed clock generator31ofFIG. 14has plural stages of series-connected inverters32, a first switch33connected between the output node of the last-stage inverter32and the input node of the first-stage inverter32, a second switch34connected between the input node of the first-stage inverter32and a ground node, and an inverter35that inverts a control signal.

The control signal ofFIG. 14is a prediction signal generated by the input signal predictor4and is a signal that becomes a high level signal when the signal levels of the bias signal and the sampled signal cross each other, for example.

The first switch33and the second switch34are switched to be on or off exclusively by the control signal. In detail, until the signal levels of the bias signal and the sampled signal cross each other, the first switch33is off while the second switch34is on. Thus, the high-speed clock generator31is put into an operation halt state. When the signal levels of the bias signal and the sampled signal cross each other, the first switch33is turned on while the second switch34is turned off. Thus, the high-speed clock generator31becomes an oscillator having plural stages of ring inverters32, thereby performing the generation of a high-speed second clock signal.

For generation of the second clock signal with the plural stages of inverters32, it is required to connect at least three or more of an odd number of inverters32in a ring shape. The frequency of the second clock signal is decided by the signal transfer delay time of each inverter32and the number of connected stages.

When the plural stages of inverters32have a delay time td, the second clock signal has a frequency ½td. Desired A/D conversion can be performed by appropriately setting this delay amount. For example, when the Fine counter6has a resolution of M bits and one clock is expressed as Δt, a delay amount td of the plural stages of inverters32is expressed by the following formula (3).
td=Δt/2M+1(3)

As described above, in the fifth embodiment, the second clock signal for operating the Fine counter6is generated by the high-speed clock generator31inside the analog-to-digital converter1. There is thus no need to input a high-speed clock signal from outside, and hence noises and timing shift can be prevented. Moreover, by providing the high-speed clock generator31inside, the second clock signal can be generated for a minimum necessary time, thereby reducing consumed power.

Sixth Embodiment

When the delay times of plural stages of inverters32are used to generate the high-speed second clock signal, as shown inFIG. 14, the frequency may vary due to the variation in delay times of the inverters32. The variation in delay times of the inverters32may occur due to variation in production, change in environment, aging, etc. For this reason, it is preferable to provide a collector for correcting a delay time of the plural stages of inverters32.

FIG. 15is a block diagram schematically showing the configuration of an analog-to-digital converter1having a corrector (frequency adjuster)40in addition to the configuration ofFIG. 13. Similar to the high-speed clock generator31, the corrector40adjusts the frequency of a second clock signal generated by the high-speed clock generator31based on the prediction signal generated by the input signal predictor4.

FIG. 16is a block diagram showing an example of the internal configuration of the corrector40. The corrector40ofFIG. 16has an OR circuit41, a synchronous reset counter42, a digital comparator43, a determination module44, and an up/down counter45.

The OR circuit41generates a logical sum signal of a control signal corresponding to a prediction signal generated by the input signal predictor4and an correction enable signal and supplies the logical sum signal to the high-speed clock generator31. Accordingly, the high-speed clock generator31generates a second clock signal when the prediction signal is input or the correction enable signal is input.

The synchronous reset counter42continues a count-up operation in synchronism with the second clock signal generated by the high-speed clock generator31. The synchronous reset counter42is reset by a clock signal from outside (hereinafter, an external clock signal). The external clock signal has an extremely lower frequency than the second clock signal. Therefore, the synchronous reset counter42counts the cycles of the second clock signal generated by the high-speed clock generator31, within one cycle of the external clock signal.

The digital comparator43compares a count value of the synchronous reset counter42and a first set value to output 1 if both are equal to each other whereas 0 if both are not equal to each other, for example.

The up/down counter45performs a count-up operation while the digital comparator43is outputting 0 whereas performs a count-down operation while the digital comparator43is outputting 1, for example.

The determination module44counts the number of times the output of the digital comparator43has changed from 0 to 1 and outputs 1 if the count value becomes equal to a set value 2, for example. When the output of the determination module44becomes 1, the up/down counter45stops a count operation and the corrector40finishes a correction sequence.

The output of the up/down counter45is used as a control signal ofFIG. 14. In detail, when the up/down counter45starts a count-up operation, inFIG. 14, the first switch33is turned on while the second switch34is turned off so that the high-speed clock generator31raises the frequency. On the contrary, when the up/down counter45starts a count-down operation, inFIG. 14, the first switch33is turned off while the second switch34is turned on so that the high-speed clock generator31lowers the frequency.

FIG. 17is a timing chart ofFIG. 16. Hereinafter, the operation of the corrector40will be explained withFIG. 17. When a correction enable signal becomes high at time t1, the corrector40starts a correction process with the frequency of the second clock signal. In the example ofFIG. 17, the initial value of the synchronous reset counter42is set to 3.

At time t2and thereafter, the synchronous reset counter42performs a count-up operation. In the beginning, since the digital comparator43outputs 0, the up/down counter45performs a count-up operation.

At time t3, the synchronous reset counter42counts 8, and hence the output of the digital comparator43changes to be 1 (time t4), which causes the up/down counter45to perform a count-down operation. Thus, the high-speed clock generator31performs a correction process to lower the frequency of the second clock signal. The synchronous reset counter42performs a count-down operation when the frequency of the second clock signal generated by the high-speed clock generator31is lowered. Accordingly, the output of the digital comparator43is changed to be 0 again (time t5), and hence the up/down counter45performs a count-up operation.

When the synchronous reset counter42and the up/down counter45have repeated count-up and count-down operations for several times, at time t6, the output of the determination module44becomes high.

As described above, the sixth embodiment is provided with the corrector40that performs frequency adjustments of the high-speed clock generator31that generates the second clock signal for operating the Fine counter6. Therefore, even if there is variation in delay time of the inverters32in the high-speed clock generator31, the second clock signal of a desired frequency can be generated and high-resolution A/D conversion process can be performed.

In the above-mentioned first to sixth embodiments, an example of providing the ramp signal generator3inside the analog-to-digital converter1has been shown. However, the ramp signal generator3may be provided outside the analog-to-digital converter1. In this case, a ramp signal generated by an external ramp signal generator is input to the analog-to-digital converter1.

Seventh Embodiment

The analog-to-digital converters1explained in the above first to sixth embodiments can be built in an image sensor.

FIG. 18is a block diagram of schematically showing the configuration of an image sensor50having the analog-to-digital converter1of any one of the first to sixth embodiments. The image sensor50ofFIG. 18is a CMOS sensor and provided with a pixel array51, a row selector52, a reader53, a selector54, an arithmetic module55, a ramp signal generator3, and a reference clock generator56.

The pixel array51has a plurality of CMOS sensors arranged in row and column directions. From among the CMOS sensors, the row selector52selects a plurality of CMOS sensors aligned in a specific row.

The reader53has a plurality of analog-to-digital converters1for the number of CMOS sensors aligned in a column direction in the pixel array51. These analog-to-digital converters1correspond to the analog-to-digital converter1of any one of the first to sixth embodiments. The ramp signal generator3has the identical internal configuration for the analog-to-digital converters1, and hence can be used for all of the analog-to-digital converters1. Thus, the ramp signal generator3is not contained in each analog-to-digital converter1ofFIG. 18but provided separately from the reader53.

The reference clock generator56generates a first clock signal for operating the Coarse counter7in each analog-to-digital converter1. A second clock signal for operating the Fine counter6may also be generated by the reference clock generator56.

The count value of the Coarse counter7in each analog-to-digital converter1becomes an A/D conversion value. It is the arithmetic module55to obtain a final A/D conversion value by averaging or the like the count value of the Coarse counter7. The arithmetic process of the arithmetic module55is the same for all of the analog-to-digital converters1. Thus, inFIG. 18, the arithmetic module55is provided outside the analog-to-digital converters1. The selector54selects the output signal of any one of the analog-to-digital converters1and supplies the selected output signal to the arithmetic module55. The selector54selects the analog-to-digital converters1one by one, and hence the arithmetic module55obtains A/D conversion values of all of the analog-to-digital converters1one by one.

As described above, the analog-to-digital converter1of each of the first to sixth embodiments can perform an A/D conversion process at high resolution without increasing power consumption. Therefore, by applying the analog-to-digital converter1to the image sensor50having a plurality of built-in analog-to-digital converters1as shown inFIG. 18, the features of high resolution and low power consumption can be more fully utilized.

FIG. 18shows an example of CMOS sensor. However, the image sensor50in this embodiment is also applicable to CCDs (Charge Coupled Devices).FIG. 19is a plan view of an image sensor50having built-in CCDs. The image sensor50ofFIG. 19has a pixel array61of vertical transfer CCDs, a horizontal transfer CCD62, a charge-to-voltage converter63, an A/D converter1, a ramp signal generator3, a reference clock generator56, and an arithmetic module55.

The pixel array61has a photoelectric converter and transfer gate each provided per pixel, and vertical transfer CCDs provided per column.

In the image sensor50ofFIG. 19, electric signals obtained by photoelectric conversion at a plurality of photoelectric converters in each row pass through the vertical transfer CCDs and are transferred to the horizontal transfer CCD62. Thereafter, the electric signals are sequentially transferred through the horizontal transfer CCD62and subjected to A/D conversion by the A/D converter1, after converted into voltage signals by the charge-to-voltage converter63.

The image sensor50ofFIG. 18, that is a CMOS sensor, requires a plurality of A/D converters1. By contrast, the image sensor50ofFIG. 19having CCDs requires only one A/D converter1.