Data detector and multi-channel data detector

A data detector detects an identification signal of a prescribed format from N-bit wide parallel input data (where N is a natural number). The data detector includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a natural number), and a determining section. Each of the P first comparing sections compares one of first P data of continuous (P+Q) data in the parallel input data with a first pattern. Each of the Q second comparing sections compares one of Q data following the P data with a second pattern. The determining section determines whether the identification signal has been detected or not according to a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 on Japanese Patent Application No. 2004-067863 filed on Mar. 10, 2004, the entire contents of which are hereby referenced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data detector and a multi-channel data detector for extracting required data from received data.

2. Description of the Related Art

Japanese Patent Laid-Open Publication No. 60-91739 describes a data detector. As shown inFIG. 22, this data detector includes a pattern detecting means161, a synchronous detecting means162, an asynchronous detecting means163, an OR means164, and a flip-flop165. Input data which is applied to the pattern detecting means161is formed from a frame synchronization pattern and data. A frame synchronization pattern is a special pattern string which is periodically present in every frame so that data is synchronized. The pattern detecting means161detects whether or not a frame synchronization pattern is present in the received input data. The pattern detecting means161outputs a match signal if a frame synchronization pattern is present. Otherwise, the pattern detecting means161outputs a mismatch signal. The synchronous detecting means162counts the match signals from the pattern detecting means161. The asynchronous detecting means163counts the mismatch signals from the pattern detecting means161. When the match signal is output N times in a row, the synchronous detecting means162sets the flip-flop165to 1, switching the mode to a synchronous mode. At the same time, the synchronous detecting means162resets the respective counters of the synchronous detecting means162and the asynchronous detecting means163through the OR means164.

When the mismatch signal is output M times in a row in the synchronous mode, the asynchronous detecting means163resets the flip-flop165to zero, switching the mode to an asynchronous mode. At the same time, the asynchronous detecting means163resets the respective counters of the synchronous detecting means162and the asynchronous detecting means163through the OR means164.

When the mode is switched to the synchronous mode, data in the input data can be accurately detected based on the frame synchronization pattern. The frame synchronization pattern is present periodically. Therefore, the synchronous mode can be maintained as long as the pattern detecting means161detects a frame synchronization pattern after the cycle of the previous frame synchronization pattern.

SUMMARY OF THE INVENTION

The above conventional structure requires periodic detection of an identification signal (frame synchronization pattern). If there is no periodic synchronization pattern like a frame synchronization pattern, an identification signal cannot be accurately detected and therefore data cannot be accurately extracted.

Moreover, data may be subjected to bit errors or a difference in delay (skew) due to a transmission path. Such defects in the data caused by a transmission path or the like may prevent accurate detection of the data. For example, bit errors may disturb detection of an identification signal, and a skew may shift the timing of extracting the data.

The present invention is made to solve the foregoing problems, and it is an object of the present invention to provide a data detector and a multi-channel data detector which are capable of accurately detecting required data even when data has defects.

According to one aspect of the present invention, a data detector detects an identification signal of a prescribed format from N-bit wide parallel input data (where N is a natural number). The data detector includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a natural number), and a determining section. Each of the P first comparing sections compares one of first P data of continuous (P+Q) data in the parallel input data with a first pattern. Each of the Q second comparing sections compares one of Q data following the P data with a second pattern. The determining section determines whether the identification signal has been detected or not according to a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections.

In the parallel input data, a plurality of N-bit data of N-bit wide and one-bit long are continuously arranged in the lengthwise direction. The identification signal is formed from continuous (P+Q) N-bit data. Each of the first P N-bit data of the identification signal has the first pattern. Each of Q N-bit data following the P N-bit data of the identification signal has the second pattern. The determining section of the data detector determines whether the identification signal has been detected or not based on the comparison result of the plurality of comparing sections adapted to the identification signal. It is herein assumed that the P first comparing sections compare the first P N-bit data of the identification signal with the first pattern, and the Q second comparing sections compare Q N-bit data following the P N-bit data of the identification signal with the second pattern. In this case, each of the P first comparing sections determines that the received N-bit data matches the first pattern, and each of the Q second comparing sections determines that the received N-bit data matches the second pattern. The determining section determines that the identification signal has been detected when all of the P first comparing sections determine that the received N-bit data matches the first pattern and all of the Q second comparing sections determine that the received N-bit data matches the second pattern. The identification signal can thus be detected. Alternatively, the determining section may determine whether or not the number of first and second comparing sections which have determined that the received N-bit data does not match the prescribed pattern is less than a prescribed value. The first comparing sections and the second comparing sections may determine whether or not at least a prescribed number of bits of the received N-bit data match the prescribed pattern. The determining section may alternatively determine whether or not the number of first and second comparing sections which have determined that the number of matching bits is less than the prescribed value is less than a prescribed value. As a result, the identification signal can be accurately detected without using powerful error correction even when data has bit errors. For example, the identification signal can be accurately detected and the data can be accurately extracted even if bit errors are generated due to a defective transmission path.

Preferably, the above data detector further includes (P+Q) data holding sections which are connected in series. The first data holding section of the (P+Q) data holding sections receives the parallel input data in synchronization with a prescribed timing. Each of the remaining data holding sections holds data held in the previous data holding section in synchronization with the prescribed timing. Each of the P first comparing sections compares data held in a corresponding one of the first P data holding sections of the (P+Q) data holding sections with the first pattern. Each of the Q second comparing sections compares data held in a corresponding one of the remaining Q data holding sections of the (P+Q) data holding sections with the second pattern.

With the plurality of stages of data holding sections, the above data detector can sequentially receive the parallel input data N bits by N bits from the beginning of the parallel input data.

Preferably, each of the P first comparing sections determines whether or not one of the P data matches the first pattern. Each of the Q second comparing sections determines whether or not one of the Q data matches the second pattern. The determining section determines that the identification signal has been detected when a total number of the first comparing sections which have determined that one of the P data does not match the first pattern and the second comparing sections which have determined that one of the Q data does not match the second pattern is less than a prescribed value.

In the above data detector, the determining section determines that the identification signal has been detected not only when all of the first and second comparing sections have determined that the received data matches a prescribed pattern but also when the number of first and second comparing sections which have determined that the received data does not match the prescribed pattern is less than the prescribed value. In other words, the determining section determines that the identification signal has been detected as long as the number of first and second comparing sections which have determined that the received data does not match the prescribed pattern is less than the prescribed value. As a result, the identification signal can be detected even when data has bit errors.

Preferably, each of the P first comparing sections compares one of the P data with the first pattern to determine whether or not a number of matching bits is equal to or larger than a prescribed value. Each of the Q second comparing sections compares one of the Q data with the second pattern to determine whether or not a number of matching bits is equal to or larger than a prescribed value. The determining section determines that the identification signal has been detected when all of the P first comparing sections have determined that the number of matching bits is equal to or larger than the prescribed value as well as all of the Q second comparing sections have determined that the number of matching bits is equal to or larger than the prescribed value.

In the above data detector, the determining section determines that the identification signal has been detected not only when all of the first and second comparing sections have determined that the received data completely matches a prescribed pattern but also when all of the first and second comparing sections have determined that the number of matching bits is equal to or larger than the prescribed value. Since the first and second comparing sections determine whether or not at least the prescribed number of bits of the received data match the prescribed pattern, the identification signal can be detected even when data has bit errors.

Preferably, each of the P first comparing sections compares one of the P data with the first pattern to determine whether or not a number of matching bits is equal to or larger than a prescribed value. Each of the Q second comparing sections compares one of the Q data with the second pattern to determine whether or not a number of matching bits is equal to or larger than a prescribed value. The determining section determines that the identification signal has been detected when a total number of the first comparing sections which have determined that the number of matching bits is less than the prescribed value and the second comparing sections which have determined that the number of matching bits is less than the prescribed value is less than a prescribed value.

In the above data detector, the first and second comparing sections do not determine whether or not the received data completely matches the prescribed pattern. Instead, the first and second comparing sections determine whether or not at least the prescribed number of bits of the received data match the prescribed pattern. Moreover, the determining section does not determine whether or not all of the first and second comparing sections have determined that at least the prescribed number of bits of the received data match the prescribed pattern. Instead, the determining section determines whether or not at least the prescribed number of first and second comparing sections have determined that at least the prescribed number of bits of the received data match the prescribed pattern. As a result, the identification signal can be detected even when the data has bit errors.

Preferably, the determining section determines whether the identification signal has been detected or not based on comparison between a comparison result pattern (a pattern of a length (P+Q) obtained from a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections) and a third pattern.

Preferably, the above data detector further includes an error-rate detecting section. The error-rate detecting section detects an error rate of the parallel input data. The determining section changes the third pattern to be compared with the comparison result pattern, according to the error rate detected by the error-rate detecting section.

In the above data detector, the third pattern which is used by the determining section is changed according to the error rate. As a result, misdetection possibility can further be reduced.

Preferably, the above data detector further includes an error-rate detecting section. The error-rate detecting section detects an error rate of the parallel input data. The first comparing sections change the first pattern according to the error rate detected by the error-rate detecting section. The second comparing sections change the second pattern according to the error rate detected by the error-rate detecting section.

In the above data detector, the first pattern which is used by the first comparing sections and the second pattern which is used by the second comparing section are changed according to the error rate. As a result, misdetection possibility can further be reduced.

Preferably, the data detector further includes a first error correcting section and a second error correcting section. The first error correcting section compares the received parallel input data with a third pattern. The first error correcting section outputs the third pattern as the parallel input data when a number of matching bits is equal to or larger than a prescribed value, and outputs the parallel input data when the number of matching bits is less than the prescribed value. The second error correcting section compares the received parallel input data with a fourth pattern. The second error correcting section outputs the fourth pattern as the parallel input data when a number of matching bits is equal to or larger than a prescribed value, and outputs the parallel input data when the number of matching bits is less than the prescribed value. Each of the P first comparing sections compares one of the first P data of the continuous (P+Q) data in the parallel input data received through the first error correcting section with the first pattern. Each of the Q second comparing sections compares one of the Q data following the P data in the parallel input data received through the second error correcting section with the second pattern.

In the above data detector, the first error correcting section and the second error correcting section output a prescribed pattern as the parallel input data when the identification signal has bit errors. In other words, the first error correcting section and the second error correcting section correct the identification signal having bit errors to a correct identification signal. Accordingly, the identification signal can be accurately detected with a simple structure without conducting error correction using a redundant error correcting code. The determining section may determine whether or not the number of first and second comparing sections which have determined that the received data does not match the prescribed pattern is less than a prescribed value. The first comparing sections and the second comparing sections may determine whether or not at least a prescribed number of bits of the received data match the prescribed pattern. The determining section may alternatively determine whether or not the number of first and second comparing sections which have determined that the number of matching bits is less than the prescribed value is less than a prescribed value. As a result, the identification signal can be detected even if bit errors are not completely corrected by the first and second error correcting sections.

Preferably, the data detector further includes an error-rate detecting section. The error-rate detecting section detects an error rate of the parallel input data. The first error-rate detecting section and the second error-rate detecting section change the respective prescribed value according to the error rate detected by the error-rate detecting section.

In the above data detector, the respective prescribed value which is used in the first and second comparing sections is changed according to the error rate. As a result, misdetection possibility can further be reduced.

According to another aspect of the present invention, a multi-channel data detector corrects a difference in delay in K input data (where K is a natural number). Each of the K input data includes an identification signal of a prescribed format. The multi-channel data detector includes K first identification-signal detecting sections, K delaying sections, K skew correcting sections, K second identification-signal detecting sections, and a skew determining section. The K first identification-signal detecting sections correspond to the K input data. The K delaying sections correspond to the K input data. The K skew correcting sections correspond to the K input data. The K second identification-signal detecting sections correspond to the K delaying sections. Each of the K first identification-signal detecting sections detects the identification signal from corresponding input data. Each of the K delaying sections delays corresponding input data. Each of the K second identification-signal detecting sections detects the identification signal from the input data delayed by a corresponding delaying section. The skew determining section determines a difference in delay in the K input data based on a timing the K first identification-signal detecting sections and the K second identification-signal detecting sections detect the identification signal. Each of the K skew correcting sections adjusts a delay amount of corresponding input data according to the difference in delay determined by the skew determining section.

In the above multi-channel data detector, the beginning of data to be extracted from input data can be detected by detecting the identification signal. When there is a difference in delay between a plurality of input data, the timing of the beginning of data to be extracted is different between the plurality of input data. The skew determining section therefore determines the difference in delay in the K input data by determining the difference in timing of the beginning of data to be extracted. For example, if the skew determining section determines that second input data is one clock behind first input data, the skew correcting section corresponding to the first input data delays the first input data by one clock cycle. In this way, the difference in delay between channels can be corrected with a simple structure, whereby the data can be accurately extracted.

Preferably, each of the K skew correcting sections selects corresponding input data or input data delayed by a corresponding delaying section, according to the difference in delay determined by the skew determining section.

According to still another aspect of the present invention, a multi-channel data detector corrects a difference in delay in K input data (where K is a natural number). Each of the K input data includes an identification signal of a prescribed format. The multi-channel data detector includes K identification-signal detecting sections, K skew correcting sections, and a skew determining section. The K identification-signal detecting sections correspond to the K input data. The K skew correcting sections correspond to the K input data. Each of the K identification-signal detecting sections detects the identification signal from corresponding input data. The skew determining section determines a difference in delay in the K input data based on a timing the K identification-signal detecting sections detects the identification signal. Each of the K skew correcting sections adjusts a delay amount of corresponding input data according to the difference in delay determined by the skew determining section.

In the above multi-channel data detector, the beginning of data to be extracted from input data can be detected by detecting the identification signal. When there is a difference in delay between a plurality of input data, the timing of the beginning of data to be extracted is different between the plurality of input data. The skew determining section therefore determines the difference in delay in the K input data by determining the difference in timing of the beginning of data to be extracted. For example, if the skew determining section determines that second input data is one clock behind first input data, the skew correcting section corresponding to the first input data delays the first input data by one clock cycle. In this way, the difference in delay between channels can be corrected with a simple structure.

Preferably, each of the K identification-signal detecting sections outputs a data detection signal upon detection of an identification signal from corresponding input data. The skew determining section includes K delaying sections and a skew detecting section. The K delaying sections correspond to the K identification-signal detecting sections. Each of the K delaying sections delays a data detection signal from a corresponding identification-signal detecting section. The skew detecting section detects a difference in delay (skew) in the K input data based on the data detection signals from the K identification-signal detecting sections and the data detection signals from the K delaying sections. Each of the K skew correcting sections stores corresponding input data when a corresponding identification-signal detecting section detects an identification signal from the corresponding input data, and outputs the stored input data based on the difference in delay detected by the skew detecting section.

Preferably, each of the identification-signal detecting sections outputs a data detection signal upon detection of an identification signal from corresponding input data. The skew determining section includes K delaying sections and a skew detecting section. The K delaying sections correspond to the K identification-signal detecting sections. Each of the K delaying sections delays a data detection signal from a corresponding identification-signal detecting section. The skew detecting section detects a difference in delay (skew) in the K input data based on the data detection signals from the K identification-signal detecting sections and the data detection signals from the K delaying sections. Each of the K skew correcting sections includes a delaying section and a selecting section. The delaying section delays corresponding input data. The selecting section selects corresponding input data or input data delayed by the delaying section, according to the difference in delay detected by the skew detecting section.

Preferably, each of the K input data is N-bit wide parallel input data (where N is a natural number). Each of the identification-signal detecting sections includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a natural number) and a determining section. Each of the P first comparing sections compares one of first P data of continuous (P+Q) data in the input data with a first pattern. Each of the Q second comparing sections compares one of Q data following the P data with a second pattern. The determining section determines whether the identification signal has been detected or not according to a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections.

In the above multi-channel data detector, the identification signal can be detected by the determining section even when input data has bit errors. The difference in delay (skew) can therefore be corrected by using these signals.

Preferably, each of the K input data is N-bit wide parallel input data (where N is a natural number). Each of the identification-signal detecting sections includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a natural number) and a determining section. Each of the P first comparing sections compares one of first P data of continuous (P+Q) data in the input data with a first pattern. Each of the Q second comparing sections compares one of Q data following the P data with a second pattern. The determining section determines whether the identification signal has been detected or not according to a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections.

In the above multi-channel data detector, the identification signal can be detected by the determining section even when input data has bit errors. Therefore, the difference in delay (skew) can be corrected by using these signals. As a result, data can be accurately extracted.

Preferably, the above data detector further includes a first error correcting section and a second error correcting section. The first error correcting section compares the received parallel input data with the first pattern. The first error correcting section outputs the first pattern as the parallel input data when the number of matching bits is equal to or larger than a prescribed value, and outputs the parallel input data when the number of matching bits is less than the prescribed value. The second error correcting section compares the received parallel input data with the second pattern. The second error correcting section outputs the second pattern as the parallel input data when the number of matching bits is equal to or larger than a prescribed value, and outputs the parallel input data when the number of matching bits is less than the prescribed value. The first data holding section of the (P+Q) data holding sections receives the parallel input data through the first error correcting section and the second error correcting section.

In the above data detector, the first error correcting section and the second error correcting section output a prescribed pattern as the parallel input data when the identification signal has bit errors. In other words, the first error correcting section and the second error correcting section correct the identification signal having bit errors to a correct identification signal. Accordingly, the identification signal can be accurately detected with a simple structure without conducting error correction using a redundant error correcting code. The determining section may determine whether or not the number of first and second comparing sections which have determined that the received data does not match the prescribed pattern is less than a prescribed value. The first comparing sections and the second comparing sections may determine whether or not at least a prescribed number of bits of the received data match the prescribed pattern. The determining section may alternatively determine whether or not the number of first and second comparing sections which have determined that the number of matching bits is less than the prescribed value is less than a prescribed value. As a result, the identification signal can be detected even if bit errors are not completely corrected by the first and second error correcting sections.

In this way, the identification signal can be accurately detected without using powerful error correction even when data has bit errors. For example, the identification signal can be accurately detected and the data can be accurately extracted even if bit errors are generated due to a defective transmission path.

Moreover, the difference in delay (skew) between channels can be corrected with a simple structure, whereby data can be accurately extracted.

Moreover, the identification signal can be detected by the determining section even when input data has bit errors. The difference in delay (skew) can therefore be corrected by using these signals. As a result, data can be accurately extracted.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the same or corresponding portions are denoted with the same reference numerals and characters throughout the figures, and description thereof will not be repeated.

First Embodiment

FIG. 1shows the overall structure of a data detector1according to the first embodiment of the present invention. The data detector1detects an identification signal from data having an identification signal of a prescribed format added thereto (hereinafter, this data is referred to as input data Data). The data detector1includes flip-flops101ato101i, preamble <A> match detecting sections102ato102h, preamble <B> match detecting sections103a,103b, an error-pattern determining section104and an error-rate detecting section105. Each flip-flop101ato101ireceives the first ten bits of input data Data (hereinafter, the first ten bits of input data Data are referred to as input data Dx) and outputs previously stored input data Dx in response to a clock. Each preamble <A> match detecting section102ato102houtputs a match detection signal (i.e., outputs “1”) if the bit values of input data Dx from a corresponding one of the flip-flops101ato101imatch a preamble <A> match pattern stored in that preamble <A> match detecting section. Otherwise, the preamble <A> match detecting section102ato102hdoes not output a match detection signal (i.e., outputs “0”). The preamble <B> match detecting section103boutputs a match detection signal (i.e., outputs “1”) if the bit values of the first ten bits of input data Data (i.e., the bit values of input data Dx) match a preamble <B> match pattern stored in the preamble <B> match detecting section103b. Otherwise, the preamble <B> match detecting section103bdoes not output a match detection signal (i.e., outputs “0”). The preamble <B> match detecting section103aoutputs a match detection signal (i.e., outputs “1”) if the bit values of input data Dx from the flip-flop101imatch a preamble <B> match pattern stored in the preamble <B> match detecting section103a.Otherwise, the preamble <B> match detecting section103adoes not output a match detection signal (i.e., outputs “0”). The error-pattern determining section104outputs a data detection signal if a pattern of the respective output values of the preamble <A> match detecting sections102ato102hand the preamble <B> match detecting sections103a,103b, i.e., an output value pattern, matches any error pattern stored in the error-pattern determining section104. The error-rate detecting section105controls the error-pattern determining section104according to the error rate of input data Data.

[Structure of Input Data Data]

FIG. 2shows an example of input data Data which is received by the data detector1ofFIG. 1. The input data Data is 10-bit wide parallel data, and is produced by converting every ten bits of one-bit wide serial data into parallel data. Note that the data width is herein 10 bits because 8-bit data has been converted into 10-bit data by a prescribed conversion algorithm in order to stabilize serial data transmission and to facilitate reproduction of serial clocks. The input data Data is formed from an identification signal and (10×L)-bit information data Dmain (where L is a data length and a natural number). The identification signal is formed from 10-bit preambles <A> Da1to Da8and 10-bit preambles <B> Db1, Db2. After detection of the beginning of the information data Dmain, the 10-bit data is restored to 8-bit data by an inverse conversion algorithm which is not shown inFIG. 1.

An error correcting code De may be added at the end of the information data Dmain. For example, a BCH (Bose-Chaudhuri-Hochquenghem) code is known as such an error correcting code De. The error correcting code De is usually produced by performing a prescribed operation to the information data Dmain. Note that the error correction code De is added to the information data Dmain, and is not included in the preambles <A> Da1to Da8and the preambles <B> Db1, Db2. The preambles <A> Da1to Da8and the preambles <B> Db1, Db2form an identification signal for detecting the beginning of the information data Dmain, and have a fixed value.

It is herein assumed that a string of the ten bit values of a preamble <A> having no bit error (i.e., a pattern represented by a normal preamble <A>) is Pa[0:9], a string of the ten bit values of a preamble <B> having no bit error (i.e., a pattern represented by a normal preamble <B>) is Pb[0:9], and a string of the ten bit values of actually received 10-bit input data Dx (i.e., a pattern represented by the input data Dx) is Dx[0:9].

Although there are eight preambles <A> and two preambles <B> in the example ofFIG. 2, the present invention is not limited to this. There may be P preambles <A> and Q preambles <B> (where P and Q are natural numbers). The preambles <A> and <B> need not be present periodically.

A preamble <A> match pattern stored in each preamble <A> match detecting section102ato102hofFIG. 1is a pattern of a normal preamble <A>, Pa[0:9]. A preamble <B> match pattern stored in each preamble <B> match detecting section103a,103bofFIG. 1is a pattern of a normal preamble <B>, Pb[0:9].

[Error Patterns Stored in the Error-Pattern Determining Section]

FIGS. 3A and 3Bshow examples of error patterns stored in the error-pattern determining section104ofFIG. 1. Each error pattern is formed from ten bit values. These ten bit values respectively correspond to the output values of the preamble <B> match detecting section103b, the preamble <B> match detecting section103a, the preamble <A> match detecting section102h. . . and the preamble <A> match detecting section102afrom left to right. Therefore, the rightmost bit value corresponds to the output value of the preamble <A> match detecting section102a.

The error pattern group1shown inFIG. 3Ainclude an error pattern P101in which all of the ten bit values are “1”, and error patterns P102to P111in which any one of the ten bit values is “0” and the remaining nine bit values are “1”.

The error pattern group2shown inFIG. 3Binclude error patterns P201to P245in which any two of the ten bit values are “0” and the remaining eight bit values are “1”.

Hereinafter, operation of the data detector1shown inFIG. 1will be described.

First, the flip-flop101iand the preamble <B> match detecting section103breceive the first ten bits of input data Data (input data Dx1).

The preamble <B> match detecting section103bcompares bit values Dx1[0:9] of the received input data Dx1with a preamble <B> match pattern Pb[0:9] stored in the preamble <B> match detecting section103b. The preamble <B> match detecting section103boutputs “1” to the error-pattern determining section104if the bit values Dx1[0:9] match the preamble <B> match pattern Pb[0:9]. Otherwise, the preamble <B> match detecting section103boutputs “0” to the error-pattern determining section104.

The flip-flop101ithen receives the first ten bits of input data Data (input data Dx2) and outputs the previously received input data Dx1to the flip-flop101hand the preamble <B> match detecting section103ain response to a clock. The preamble <B> match detecting section103balso receives the first ten bits of the input data Data (input data Dx2), and compares bit values Dx2[0:9] of the received input data Dx2with the preamble <B> match pattern Pb[0:9] stored in the preamble <B> match detecting section103b. The preamble <B> match detecting section103boutputs “1” to the error-pattern determining section104if the bit values Dx2[0:9] match the preamble <B> match pattern Pb[0:9]. Otherwise, the preamble <B> match detecting section103boutputs “0” to the error-pattern determining section104.

The flip-flop101hreceives the input data Dx1from the flip-flop101iin response to a clock. The preamble <B> match detecting section103acompares the bit values Dx1[0:9] of the input data Dx1received from the flip-flop101iwith a preamble <B> match pattern Pb[0:9] stored in the preamble <B> match detecting section103a. The preamble <B> match detecting section103aoutputs “1” to the error-pattern determining section104if the bit values Dx1[0:9] match the preamble <B> match pattern Pb[0:9]. Otherwise, the preamble <B> match detecting section103aoutputs “0” to the error-pattern determining section104.

Each of the flip-flops101ato101ithus sequentially shifts the input data Data ten-bits by ten-bits to a flip-flop of the subsequent stage in response to every clock. As a result, the preamble <A> match detecting sections102ato102hand the preamble <B> match detecting sections103a,103bsequentially receive the input data Data ten-bits by ten-bits.

For example, an apparatus of the subsequent stage produces a data period signal which is held at “1” for the same period as the period L of the information data Dmain based on the data detection signal, as shown inFIG. 2. As a result, the period of the information data Dmain can be accurately extracted from the input data Data.

The data detector1thus extracts the information data Dmain by detecting the beginning of the information data Dmain from the input data Data.

[Operation of the Error-Pattern Determining Section104]

Hereinafter, operation of the error-pattern determining section104will be described according to the types of error pattern group stored in the error-pattern determining section104.

(i) When the error-pattern determining section104stores the error pattern group1(FIG. 3A):

When the data detector1receives input data Data having no bit error, all of the preamble <A> match detecting sections102ato102hand the preamble <B> match detecting sections103a,103boutput “1”. Since the pattern represented by these output values matches the error pattern P101of the error pattern group1, the error-pattern determining section104outputs a data detection signal.

When the data detector1receives input data Data having bit errors in any one of the preambles <A> Da1to Da8and preambles <B> Db1, Db2, one of the preamble <A> match detecting sections102ato102hand preamble <B> match detecting sections103a,103boutputs “0”, and the remaining nine match detecting sections output “1”. For example, if the input data Data has bit errors in the preamble <A> Da5, the output values will be “1111101111” in the order from the preamble <B> match detecting section103bto the preamble <A> match detecting section102a. Since the pattern represented by these output values matches the error pattern P107of the error pattern group1, the error-pattern determining section104outputs a data detection signal.

The data detector1can thus accurately detect the beginning of data even when a plurality of bit errors burst in a single preamble <A> or a single preamble <B>.

When the data detector1receives input data Data having bit errors in any two of the preambles <A> Da1to Da8and preambles <B> Db1, Db2, two of the preamble <A> match detecting sections102ato102hand preamble <B> match detecting sections103a,103boutput “0”, and the remaining eight match detecting sections output “1”. For example, if the output values are “1111111001” in the order from the preamble <B> match detecting sections103bto the preamble <A> match detecting section102a, the pattern represented by these output values matches the error pattern P202of the error pattern group2. Therefore, the error-pattern determining section104outputs a data detection signal.

The use of the error pattern groups1,2ofFIGS. 3A,3B thus enables accurate detection of an identification signal without using powerful error correction even when input data has bit errors.

Hereinafter, the possibility that the error-pattern determining section104erroneously outputs a data detection signal when the data detector1has not completely received an identification signal (preambles <A> Da1to Da8and preambles <B> Db1, Db2) will be described.

It is herein assumed that input data Data having no bit error is sequentially applied to the data detector1, and the preamble <A> match detecting sections102bto102hhave received the preambles <A> Da1to Da7, respectively, the preamble <B> match detecting section103ahas received the preamble <A> Da8, and the preamble <B> match detecting section103bhas received the preamble <B> Db1. In other words, it is assumed that the data detector1has received the preambles <A> Da1to Da8and the preamble <B> Db1, but has not received the preamble <B> Db2.

In this case, the preamble <A> match detecting section102aoutputs “0”. Since the preamble <B> match detecting section103ahas received the preamble <A> Da8, the preamble <B> match detecting section103aoutputs “0”. Since the preamble <A> match detecting sections102bto102hhave received the preambles <A> Da1to Da7, respectively, and the preamble <B> match detecting section103bhas received the preamble <B> Db1, all of the preamble <A> match detecting sections102bto102hand preamble <B> match detecting section103boutput “1”. In other words, the pattern represented by the output values (the output value pattern) is “1011111110” in the order from the preamble <B> match detecting section103bto the preamble <A> match detecting section102a.

None of the error patterns P101to P111in the error pattern group1ofFIG. 3Amatches this output value pattern, and the error pattern P216in the error pattern group2ofFIG. 3Bmatches this output value pattern. The error-pattern determining section104therefore does not output a data detection signal.

Misdetection can thus be prevented by using two kinds of match detecting sections (preamble <A> match detecting sections102ato102hand preamble <B> match detecting sections103a,103b).

[Operation of the Error-Rate Detecting Section]

Hereinafter, operation of the error-rate detecting section105ofFIG. 1will be described.

The error-rate detecting section105receives information data Dmain and an error correcting code De which have been detected by the above operation.

The error-rate detecting section105then produces data for detecting an error rate (hereinafter, referred to as error-rate detecting data Dk) by performing to the received information data Dmain the same operation as that performed to produce the error correcting code De.

The error-rate detecting section105compares the bit values of the error-rate detecting data Dk with the bit values of the error correcting code De having no bit error (i.e., the bit values of a normal error correcting code De), and detects the number of matching bit values.

If the number of matching bit values is equal to or larger than a threshold, the error-rate detecting section105outputs to the error-pattern determining section104a selection signal for selecting the error pattern group1. If the number of matching bit values is less than the threshold, the error-rate detecting section105outputs to the error-pattern determining section104a selection signal for selecting the error pattern group2.

According to the selection signal from the error-rate detecting section105, the error-pattern determining section104selects one of the error pattern groups in order to use the selected error pattern group in the above operation.

The error-rate detecting section105thus detects the error rate by comparing the bit values of the error-rate detecting data Dk with the bit values of a normal error correcting code De.

[First Modification of the Error-Rate Detecting Section]

The error-rate detecting section105may alternatively detect the error rate by using fixed data transmitted through the same transmission path as input data Data. For example, the error rate may be detected as follows:

The data detector1receives input data Data with fixed data of prescribed bit values added thereto.

The error-rate detecting section105receives the fixed data and compares the bit values of the received fixed data with the bit values of fixed data having no bit error (i.e., the bit values of normal fixed data).

If the number of matching bit values is equal to or larger than a threshold, the error-rate detecting section105outputs to the error-pattern determining section104a selection signal for selecting the error pattern group1. If the number of matching bit values is less than the threshold, the error-rate detecting section105outputs to the error-pattern determining section104a selection signal for selecting the error pattern group2.

The error-rate detecting section105thus detects the error rate by comparing the bit values of the received fixed data with the bit values of normal fixed data.

[Second Modification of the Error-Rate Detecting Section]

A section for detecting error-rate detecting data (hereinafter, referred to as data detecting section) may be connected before the error-rate detecting section105ofFIG. 1. The data detecting section has the same structure as the data detector1ofFIG. 1except that the data detecting section does not include the error-rate detecting section105. For example, the error rate may be detected as follows:

The data detecting section receives input data Data and detects an identification signal by the operation described above. Upon detection of the identification signal, the data detecting section outputs a data detection signal to the error-rate detecting section105.

The error-rate detecting section105produces a data period signal which is held at “1” for the same period as the period L of information data Dmain based on the data detection signal. The period of the information data Dmain is thus extracted from the input data Data based on the data period signal.

As described above, the error-rate detecting section105produces error-rate detecting data Dk by performing to the extracted information data Dmain the same operation as that performed to produce the error correcting code De. The error-rate detecting section105then detects the error rate by comparing the bit values of the produced error-rate detecting data Dk with the bit values of a normal error correcting code De.

As described above, the error-pattern determining section104uses a plurality of error patterns for comparison with an output value pattern of the preamble <A> detecting sections and the preamble <B> detecting sections. Accordingly, an identification signal can be accurately detected without using powerful error correction even when input data has bit errors. As a result, an apparatus of the subsequent stage can accurately extract information data Dmain.

Misdetection can be prevented by using two kinds of match detecting sections for two kinds of identification data (preambles <A> Da1to Da8and preambles <B> Db1, Db2).

Possibility of misdetection can further be reduced by selecting the error pattern group1or the error pattern group2in the error-pattern determining section104according to the error rate.

By increasing the number of error patterns, the data detector1can operate in the same manner even if any three or more of the preamble <A> match detecting sections102ato102hand preamble <B> match detecting sections103a,103boutput “0”. In this case, such error patterns are used that any three of the ten bit values are “0” and the remaining seven bit values are “1”. However, an error pattern like P216ofFIG. 3Bshould be included in order to prevent misdetection.

Second Embodiment

FIG. 4shows the overall structure of a data detector2according to the second embodiment of the present invention. The data detector2has the same structure as the data detector1ofFIG. 1except that the preamble <A> match detecting sections102ato102h, the preamble <B> match detecting sections103a,103b, the error-pattern determining section104and the error-rate detecting section105ofFIG. 1are replaced with preamble <A> detecting sections202ato202h, preamble <B> detecting sections203a,203band a determining section204. Each preamble <A> detecting section202ato202houtputs a detection signal (i.e., outputs “1”) when the bit values of received ten bits of input data (i.e., the bit values of input data Dx) match a preamble <A> similar pattern stored in that preamble <A> detecting section. Each preamble <B> detecting section203a,203boutputs a detection signal (i.e., outputs “1”) when the bit values of received ten bits of input data (i.e., the bit values of input data Dx) match a preamble <B> similar pattern stored in that preamble <B> detecting section. The determining section204outputs a data detection signal when all of the preamble <A> detecting sections202ato202hand preamble <B> detecting sections203a,203boutput “1”.

[Internal Structure of the Preamble <A> Detecting Sections]

FIG. 5Ashows the internal structure of the preamble <A> detecting sections202ato202hofFIG. 4. Since the preamble <A> detecting sections202ato202hhave the same internal structure, the internal structure of the preamble <A> detecting structure202ais shown inFIG. 5A. The preamble <A> detecting section202aincludes a comparison table211and a comparing section212. The comparison table211stores preamble <A> similar patterns A201to A210. The comparing section212outputs a detection signal (i.e., outputs “1”) when received input data Dx matches any one of the preamble <A> similar patterns A201to A210stored in the comparison table211.

[Internal Structure of the Preamble <B> Detecting Sections]

FIG. 5Bshows the internal structure of the preamble <B> detecting sections203a,203bofFIG. 4. Since the preamble <B> detecting sections203a,203bhave the same internal structure, the internal structure of the preamble <B> detecting structure203ais shown inFIG. 5B. The preamble <B> detecting section203aincludes a comparison table221and a comparing section222. The comparison table221stores preamble <B> similar patterns B201to B210. The comparing section222outputs a detection signal (i.e., outputs “1”) when received input data Dx matches any one of the preamble <B> similar patterns B201to B210stored in the comparison table221.

The preamble <A> similar patterns A201to A210stored in the comparison table211ofFIG. 5Awill now be described. Provided that the bit values Pa[0:9] of a normal preamble <A> is A0, A1, A2, . . . , A9in this order, each of the preamble <A> similar patterns A201to A210is a pattern having one of the bit values A0to A9replaced with a bit value X. The bit value X is an arbitrary bit value (the bit value X may be either “0” or “1”). For example, the preamble <A> similar pattern A203is a preamble <A> match pattern having a bit value A7replaced with a bit value X. In other words, the eighth bit value of the preamble <A> similar pattern A203is an arbitrary bit value.

The preamble <B> similar patterns B201to B210stored in the comparison table221ofFIG. 5Bwill now be described. Provided that the bit values Pb[0:9] of a normal preamble <B> is B0, B1, B2, . . . , B9in this order, each of the preamble <B> similar patterns B201to B210is a pattern having one of the bit values B0to B9replaced with a bit value X. The bit value X is an arbitrary bit value (the bit value X may be either “0” or “1”). For example, the preamble <B> similar pattern B203is a preamble <B> match pattern having a bit value B7replaced with a bit value X. In other words, the eighth bit value of the preamble <B> similar pattern B203is an arbitrary bit value.

Hereinafter, operation of the data detector2ofFIG. 4will be described.

Like the first embodiment, each of the flip-flops101ato101isequentially shifts the input data Data ten-bits by ten-bits to a flip-flop of the subsequent stage in response to every clock. As a result, the preamble <A> detecting sections202ato202hand the preamble <B> detecting sections203a,203bsequentially receive the input data Data ten-bits by ten-bits.

In each preamble <A> detecting section202ato202h, the comparing section212compares the preamble <A> similar patterns A201to A210stored in the comparison table211with received input data Dx. The comparing section212outputs a detection signal (i.e., outputs “1”) when any one of the preamble <A> similar patterns A201to A210matches the input data Dx.

In each preamble <B> detecting section203a,203b, the comparing section222compares the preamble <B> similar patterns B201to B210stored in the comparison table221with received input data Dx. The comparing section222outputs a detection signal (i.e., outputs “1”) when any one of the preamble <B> similar patterns B201to B210matches the input data Dx.

The determining section204outputs a data detection signal when all of the preamble <A> detecting sections202ato202hand the preamble <B> detecting sections203a,203boutput “1”.

For example, as shown inFIG. 2, an apparatus of the subsequent stage then produces a data period signal which is held at “1” for the same period as the period L of information data Dmain based on the data detection signal. As a result, the period of the information data Dmain can be accurately extracted from input data Data.

[Operation of the Preamble <A> Detecting Sections]

Hereinafter, operation of the preamble <A> detecting sections202ato202hwill be described. Since the preamble <A> detecting sections202ato202hoperate in the same manner, operation of the preamble <A> detecting section202awill be described.

When input data Data to the data detector2has a one-bit error in the preamble <A> Da2, the preamble <A> Da2has one wrong bit value and nine correct bit values. For example, if the eighth bit value of the preamble <A> Da2is wrong, the comparing section212determines that the preamble <A> Da2matches the preamble <A> similar pattern A203stored in the comparison table211. The comparing section212therefore outputs “1” to the determining section204.

[Operation of the Preamble <B> Detecting Sections]

Hereinafter, operation of the preamble <B> detecting sections203a,203bwill be described. Since the preamble <B> detecting sections203a,203boperate in the same manner, operation of the preamble <B> detecting section203awill be described.

When input data Data to the data detector2has a one-bit error in the preamble <B> Db1, the preamble <B> Db1has one wrong bit value and nine correct bit values. For example, if the eighth bit value of the preamble <B> Db1is wrong, the comparing section222determines that the preamble <B> Db1matches the preamble <B> similar pattern B203stored in the comparison table221. The comparing section222therefore outputs “1” to the determining section204.

[Modification of the Preamble <A> Detecting Sections]

Hereinafter, a modification of the preamble <A> detecting sections202ato202hwill be described. In this modification, the data detector2includes the error-rate detecting section105shown inFIG. 1, and the preamble <A> detecting sections202ato202hreceive a selection signal from the error-rate detecting section105. Since the preamble <A> detecting sections202ato202hhave the same internal structure, the internal structure of the preamble <A> detecting section202ais shown inFIG. 6. The preamble <A> detecting section202aincludes comparison tables211a,211band a comparing section212. The comparison table211ahas the same structure as the comparison table211ofFIG. 5A. The comparison table211bstores preamble <A> similar patterns A221to A265. Each of the preamble <A> similar patterns A221to A265is a pattern of a normal preamble <A> having two of bit values A0to A9replaced with bit values X. According to a selection signal from the error-rate detecting section105, the comparing section212selects one of the comparison tables211a,211bfor comparison with the input data Dx.

Operation of the preamble <A> detecting section202aofFIG. 6will now be described.

The error-rate detecting section105detects the error rate in the same manner as the first embodiment. When the number of matching bits is equal to or larger than a threshold, the error-rate detecting section105outputs to the comparing section212a selection signal for selecting the comparison table211a. When the number of matching bits is less than the threshold, the error-rate detecting section105outputs to the comparing section212a selection signal for selecting the comparison table211b.

According to the selection signal from the error-rate detecting section105, the comparing section212selects one of the comparison tables211a,211bfor comparison with the input data Dx.

[Modification of the Preamble <B> Detecting Sections]

A modification of the preamble <B> detecting sections203a,203bwill now be described. In this modification, the data detector2includes the error-rate detecting section105shown inFIG. 1, and the preamble <B> detecting sections203a,203breceive a selection signal from the error-rate detecting section105. Since the preamble <B> detecting sections203a,203bhave the same internal structure, the internal structure of the preamble <B> detecting section203ais shown inFIG. 7. The preamble <B> detecting section203aincludes comparison tables221a,221band a comparing section222. The comparison table221ahas the same structure as the comparison table221ofFIG. 5B. The comparison table221bstores preamble <B> similar patterns B221to B265. Each of the preamble <B> similar patterns B221to B265is a pattern of a normal preamble <B> having two of bit values B0to B9replaced with bit values X. According to a selection signal from the error-rate detecting section105, the comparing section222selects one of the comparison tables221a,221bfor comparison with the input data Dx.

Like the preamble <A> detecting section202aofFIG. 6, when each of the preamble <B> detecting sections203a,203bincludes a plurality of comparison tables (comparison tables221a,221b), the comparing section222selects one of the comparison tables221a,221bfor comparison with the input data Dx according to a selection signal from the error-rate detecting section105.

As has been described above, each of the preamble <A> detecting sections202ato202hand preamble <B> detecting sections203a,203buses a plurality of preamble <A> similar patterns or a plurality of preamble <B> similar patterns for comparison with the received input data. Therefore, an identification signal can be accurately detected even when each of the preambles <A> Da1to Da8and preambles <B> Db1, Db2has a one-bit error.

When the preamble <A> detecting sections and the preamble <B> detecting sections have the internal structure shown inFIGS. 6 and 7, misdetection possibility can further be reduced by switching the comparison tables according to the error rate.

Third Embodiment

FIG. 8shows the overall structure of a data detector3according to the third embodiment of the present invention. The-data detector3has the same structure as the data detector2ofFIG. 4except that the determining section204ofFIG. 4is replaced with the error-pattern determining section104ofFIG. 1.

Hereinafter, operation of the data detector3ofFIG. 8will be described.

Like the second embodiment, each of the flip-flops101ato101isequentially shifts the input data Data ten-bits by ten-bits to a flip-flop of the subsequent stage in response to every clock. As a result, the preamble <A> detecting sections202ato202hand the preamble <B> detecting sections203a,203bsequentially receive the preambles <A> Da1to Da8and the preambles <B> Db1, Db2. In each preamble <A> detecting section202ato202h, the comparing section212outputs a detection signal (i.e., outputs “1”) when any one of the preamble <A> similar patterns A201to A210stored in the comparison table211matches the received input data Dx. In each preamble <B> detecting section203a,203b,the comparing section222outputs a detection signal (i.e., outputs “1”) when any one of the preamble <B> similar patterns B201to B210stored in the comparison table221matches the received input data Dx.

Like the first embodiment, the error-pattern determining section104outputs a data detection signal when the pattern represented by the respective output values of the preamble <A> detecting sections202ato202hand the preamble <B> detecting sections203a,203bmatches any error pattern stored in the error-pattern determining section104.

The above operation will now be described specifically. In the example described below, the error-pattern determining section104stores the error pattern group1ofFIG. 3A.

It is herein assumed that the data detector3receives input data Data having a one-bit error in each of the preambles <A> Da1, Da3to Da8and preambles <B> Db1, Db2and a two-bit error in the preamble <A> Da2. In this case, the preamble <A> detecting sections202a,202cto202hand the preamble <B> detecting sections203a,203boutput “1”, and the preamble <A> detecting section202boutputs “0”. The pattern represented by these output values (the output value pattern) is therefore “1111111101” in the order from the preamble <B> detecting section203bto the preamble <A> detecting section202a.This output value pattern matches the error pattern P110stored in the error-pattern determining section104. The error-pattern determining section104therefore outputs a detection signal. In this way, even when each of the preambles <A> Da1to Da8and preambles <B> Db1, Db2has bit errors, one-bit errors can be corrected by the preamble <A> detecting sections202ato202hand the preamble <B> detecting sections203a,203b.Two-bit or more errors can be corrected by the error-pattern determining section104, if not 100%.

As has been described above, each of the preamble <A> detecting sections202ato202hand preamble <B> detecting sections203a,203buses a plurality of preamble <A> similar patterns or a plurality of preamble <B> similar patterns for comparison with the received input data. Moreover, the error-pattern determining section104uses a plurality of error patterns for comparison with an output value pattern of the preamble <A> detecting sections and the preamble detecting sections <B>. As a result, the capability of detecting an identification signal can be improved as compared to the second embodiment.

Note that the error pattern groups1,2ofFIGS. 3A,3B, the comparison tables211a,211bofFIG. 6, the comparison tables221a,221bofFIG. 7and the like may be optimized according to the capability of the data detector3to detect an identification signal.

It is also to be understood that misdetection possibility can further be reduced by providing a plurality of error pattern groups and a plurality of comparison tables and adaptively switching the error pattern groups and the comparison tables according to the error rate, like the error pattern groups1,2ofFIGS. 3A,3B, the comparison tables211a,211bofFIG. 6and the comparison tables221a,221bofFIG. 7.

Fourth Embodiment

FIG. 9shows the overall structure of a data detector4according to the fourth embodiment of the present invention. The data detector4includes flip-flops101ato101i,preamble <A> match detecting sections102ato102hand preamble <B> match detecting sections103a,103bas shown inFIG. 1, a determining section204as shown inFIG. 4, a preamble <A> error correcting section401, and a preamble <B> error correcting section402. The preamble <A> error correcting section401corrects the bit values of a preamble <A> having a bit error to the bit values Pa[0:9] of a normal preamble <A>. The preamble <B> error correcting section402corrects the bit values of a preamble <B> having a bit error to the bit values Pb[0:9] of a normal preamble <B>.

[Internal Structure of the Preamble <A> Error Correcting Section401]

FIG. 10shows the internal structure of the preamble <A> error correcting section401ofFIG. 9. The preamble <A> error correcting section401includes a bit-error detecting section411, a normal preamble <A> storing section412and a selecting section413. The bit-error detecting section411has the same structure as the comparing section212. The bit-error detecting section411outputs a switching signal (i.e., outputs “1”) to the selecting section413when the received 10-bit input data (input data Dx) matches one of the preamble <A> similar patterns A201to A210stored in the comparison table211. The normal preamble <A> storing section412stores the bit values of a preamble <A> having no bit error (i.e., the bit values Pa[0:9] of a normal preamble <A>). The selecting section413outputs the received input data Dx or the normal preamble <A> stored in the normal preamble <A> storing section412, according to the switching signal from the bit-error detecting section411.

[Internal Structure of the Preamble <B> Error Correcting Section402]

FIG. 10shows the internal structure of the preamble <B> error correcting section402ofFIG. 9. The preamble <B> error correcting section402includes a bit-error detecting section421, a normal preamble <B> storing section422and a selecting section423. The bit-error detecting section421has the same structure as the comparing section222. The bit-error detecting section421outputs a switching signal (i.e., outputs “1”) to the selecting section423when the received input data Dx matches one of the preamble <B> similar patterns B201to B210stored in the comparison table221. The normal preamble <B> storing section422stores the bit values of a preamble <B> having no bit error (i.e., the bit values Pb[0:9] of a normal preamble <B>). The selecting section423outputs the received input data Dx or the normal preamble <B> stored in the normal preamble <B> storing section422, according to the switching signal from the bit-error detecting section421.

It is very unlikely that a portion other than the preambles <A> is erroneously corrected to a preamble <A>. The probability that 10-bit input data Dx is erroneously corrected to a preamble <A> is 10/1024 (about 1/100). Similarly, it is also very unlikely that a portion other than the preambles <B> is erroneously corrected to a preamble <B>. Since the total number of preambles <A> and preambles <B> is ten, the probability that miscorrection occurs for all preambles is ( 1/10)20. It is therefore considered that such miscorrection hardly occurs.

Hereinafter, operation of the data detector4ofFIG. 9will be described.

The bit-error detecting section411of the preamble <A> error correcting section401receives the first ten bits of input data Data (i.e., input data Dx1), and determines whether or not the bit values Dx1[0:9] of the input data Dx1match any one of the preamble <A> similar patterns A201to A201stored in the bit-error detecting section411. The bit-error detecting section411outputs “1” to the selecting section413if the bit values Dx1[0:9] of the input data Dx1match any one of the preamble <A> similar patterns A201to A201. Otherwise, the bit-error detecting section411outputs “0” to the selecting section413.

When the bit-error detecting section411outputs “1”, the selecting section413outputs the bit values Pa[0:9] of a normal preamble <A> stored in the normal preamble <A> storing section412as input data Dx1. When the bit-error detecting section411outputs “0”, the selecting section413outputs the received input data Dx1.

The bit-error detecting section421of the preamble <B> error correcting section402receives the input data Dx1from the preamble <A> error detecting section401, and determines whether or not the bit values of the received input data Dx1match any one of the preamble <B> similar patterns B201to B210stored in the bit-error detecting section421. The bit-error detecting section421outputs “1” to the selecting section423if the bit values of the received input data Dx1match any one of the preamble <B> similar patterns B201to B210. Otherwise, the bit-error detecting section421outputs “0” to the selecting section423.

When the bit-error detecting section421outputs “1”, the selecting section423outputs the bit values Pb[0:9] of a normal preamble <B> stored in the normal preamble <B> storing section422as input data Dx1. When the bit-error detecting section421outputs “0”, the selecting section423outputs the received input data Dx1.

Like the first embodiment, each of the flip-flops101ato101isequentially shifts the input data Data ten-bits by ten-bits to a flip-flop of the subsequent stage in response to every clock. As a result, the preamble <A> match detecting sections102ato102hand the preamble <B> match detecting sections103a,103bsequentially receive the input data Data ten-bits by ten-bits.

Like the second embodiment, the determining section204outputs a data detection signal when the determining section204determines that all the output values of the preamble <A> match detecting sections102ato102hand preamble <B> match detecting sections103a,103bare “1”.

It is herein assumed that input data Data has a one-bit error in each of the preambles <A> Da1to Da8and preambles <B> Db1, Db2.

In this case, the preamble <A> error correcting section401corrects each of the preambles <A> Da1to Da8to the bit values Pa[0:9] of a normal preamble <A>. The preamble <B> error correcting section402then corrects each of the preambles <B> Db1, Db2to the bit values Pb[0:9] of a normal preamble <B>. The preamble <A> match detecting sections102ato102hand the preamble <B> match detecting sections103a,103bthen receive the preambles <A> Da1to Da8and the preambles <B> Db1, Db2. In this case, the pattern represented by the output values (i.e., the output value pattern) is “1111111111” in the order from the preamble <B> match detecting section103bto the preamble <A> match detecting section102a. As a result, the determining section204outputs a data detection signal.

As has been described above, even when each of the preambles <A> Da1to Da8and preambles <B> Db1, Db2has a one-bit error, an identification signal can be accurately detected with a simple structure without conducting error correction using a redundant error correcting code.

Fifth Embodiment

FIG. 11shows the overall structure of a data detector5according to the fifth embodiment of the present invention. The data detector5includes the flip-flops101ato101i, the preamble <A> detecting sections102ato102h, the preamble <B> detecting sections103a,103band the error-pattern determining section104as shown inFIG. 1, and the preamble <A> error correcting section401and the preamble <B> error correcting section402as shown inFIG. 9.

Hereinafter, operation of the data detector5ofFIG. 11will be described.

Like the fourth embodiment, the data detector5sequentially receives the first ten bits of input data Data.

Like the fourth embodiment, the preamble <A> error correcting section401corrects the bit values of each preamble <A> Da1to Da8to the bit values Pa[0:9] of a normal preamble <A>. The preamble <B> error correcting section402corrects the bit values of each preamble <B> Db1, Db2to the bit values Pb[0:9] of a normal preamble <B>.

Like the first embodiment, each of the flip-flops101ato101isequentially shifts the input data Data ten-bits by ten-bits to a flip-flop of the subsequent stage in response to every clock. As a result, the preamble <A> match detecting sections102ato102hand the preamble <B> match detecting sections103a,103bsequentially receive the input data Data ten-bits by ten-bits.

Like the first embodiment, each preamble <A> match detecting section102ato102hdetermines its output value by comparing the received input data with a preamble <A> match pattern stored in that preamble <A> match detecting section. Each preamble <B> match detecting section103a,103bdetermines its output value by comparing the received input data with a preamble <B> match pattern stored in that preamble <B> match detecting section.

Like the first embodiment, the error-pattern determining section104determines whether or not the pattern represented by ten output values, i.e., the pattern represented by the respective output values of the preamble <A> match detecting sections102ato102hand the preamble <B> match detecting sections103a,103b(the output value pattern), matches any error pattern stored in the error-pattern determining section104. The error-pattern determining section104outputs a data detection signal if the output value pattern matches any error pattern stored in the error-pattern determining section104. Otherwise, the error-pattern determining section104does not output a data detection signal.

It is herein assumed that the data detector5receives input data Data having a one-bit error in each of the preambles <A> Da1to Da8and preamble Db2, and a two-bit or more error in the preamble <B> Db1.

In this case, the preamble <A> error correcting section401corrects each of the preambles <A> Da1to Da8to the bit values Pa[0:9] of a normal preamble <A>. The preamble <B> error correcting section402then corrects the preamble <B> Db2to the bit values Pb[0:9] of a normal preamble <B>. The preamble <A> match detecting sections102ato102hand the preamble <B> match detecting sections103a,103bthen receive the preambles <A> Da1to Da8and the preambles <B> Db1, Db2. In this case, the pattern represented by the output values (i.e., the output value pattern) is “1011111111” in the order from the preamble <B> match detecting section103bto the preamble <A> match detecting section102a. Since this output value pattern matches the error pattern P103, the error-pattern determining section104outputs a data detection signal.

As has been described above, an identification signal can be accurately detected even when bit errors cannot be completely corrected by the preamble <A> error correcting section401and the preamble <B> error correcting section402. The fifth embodiment thus has improved capability of detecting an identification signal over the fourth embodiment.

The number of bits to be corrected by the preamble <A> error correcting section401and the preamble <B> error correcting section402and the error pattern groups to be used by the error-pattern determining section104may be optimized according to the capability of the data detector5.

Sixth Embodiment

FIG. 12shows the overall structure of a data detector6according to the sixth embodiment of the present invention. The data detector6has the same structure as the data detector2ofFIG. 4except that the data detector6further includes the preamble <A> error correcting section401and the preamble <B> error correcting section402ofFIG. 9.

Hereinafter, operation of the data detector6ofFIG. 12will be described.

Like the fourth embodiment, the data detector6sequentially receives the first ten bits of input data Data.

Like the fourth embodiment, the preamble <A> error correcting section401corrects the bit values of each preamble <A> Da1to Da8to the bit values Pa[0:9] of a normal preamble <A>. The preamble <B> error correcting section402corrects the bit values of each preamble <B> Db1, Db2to the bit values Pb[0:9] of a normal preamble <B>.

Like the second embodiment, each of the flip-flops101ato101isequentially shifts the input data Data ten-bits by ten-bits to a flip-flop of the subsequent stage in response to every clock. As a result, the preamble <A> detecting sections202ato202hand the preamble <B> detecting sections203a,203bsequentially receive the input data Data ten-bits by ten-bits.

Like the second embodiment, each preamble <A> detecting section202ato202hdetermines its output value by comparing the received input data with the preamble <A> similar patterns A221to A265stored in that preamble <A> detecting section. Each preamble <B> detecting section203a,203bdetermines its output value by comparing the received input data with the preamble <B> similar patterns B221to B265stored in that preamble <B> detecting section.

Like the second embodiment, the determining section204outputs a data detection signal when all of the ten output values from the preamble <A> detecting sections202ato202hand the preamble <B> detecting sections203a,203bare “1”.

It is herein assumed that the data detector6receives input data Data having a two-bit error in each of the preambles <A> Da1to Da8and preambles <B> Db1, Db2. In this example, the bit-error detecting section411has the internal structure ofFIG. 5A, the bit-error detecting section421has the internal structure ofFIG. 5B, each of the preamble <A> detecting sections202ato202hhas the internal structure ofFIG. 6, and each of the preamble <B> detecting sections203a,203bhas the internal structure ofFIG. 7.

In this case, the bit errors of the preambles <A> Da1to Da8and the preambles <B> Db1, Db2are not corrected in the preamble <A> error correcting section401and the preamble <B> error correcting section402. The preamble <A> detecting sections202ato202hand the preamble <B> detecting sections203a,203bthen receive the preambles <A> Da1to Da8and the preambles <B> Db1, Db2. As a result, the pattern represented by the respective output values (the output value pattern) is “1111111111” in the order from the preamble <B> detecting section203bto the preamble <A> detecting section202a.The determining section204therefore outputs a data detection signal.

As has been described above, an identification signal can be accurately detected even when bit errors cannot be completely corrected by the preamble <A> error correcting section401and the preamble <B> error correcting section402. The sixth embodiment thus has improved capability of detecting an identification signal over the fourth embodiment.

Seventh Embodiment

FIG. 13shows the overall structure of a data detector7according to the seventh embodiment of the present invention. The data detector7has the same structure as the data detector3ofFIG. 8except that the data detector7further includes the preamble <A> error correcting section401and the preamble <B> error correcting section402ofFIG. 9.

Hereinafter, operation of the data detector7ofFIG. 13will be described.

Like the fourth embodiment, the data detector7sequentially receives the first ten bits of input data Data.

Like the fourth embodiment, the preamble <A> error correcting section401corrects the bit values of each preamble <A> Da1to Da8to the bit values Pa[0:9] of a normal preamble <A>, and the preamble <B> error correcting section402corrects the bit values of each preamble <B> Db1, Db2to the bit values Pb[0:9] of a normal preamble <B>.

Like the third embodiment, each of the flip-flops101ato101isequentially shifts the input data Data ten-bits by ten-bits to a flip-flop of the subsequent stage in response to every clock. As a result, the preamble <A> detecting sections202ato202hand the preamble <B> detecting sections203a,203bsequentially receive the input data Data ten-bits by ten-bits.

Like the third embodiment, each preamble <A> detecting section202ato202hdetermines its output value by comparing the received input data with the preamble <A> similar patterns A221to A265stored in that preamble <A> detecting section. Each preamble <B> detecting section203a,203bdetermines its output value by comparing the received input data with the preamble <B> similar patterns B221to B265stored in that preamble <B> detecting section.

Like the third embodiment, the error-pattern determining section104determines whether or not the pattern represented by the ten output values from the preamble <A> detecting sections202ato202hand preamble <B> detecting sections203a,203b(the output value pattern) matches any error pattern stored in the error-pattern determining section104. The error-pattern determining section104outputs a data detection signal if the output value pattern matches any error pattern stored in the error-pattern determining section104. Otherwise, the error-pattern determining section104does not output a data detection signal.

It is herein assumed that the data detector7receives input data Data having a two-bit error in each of the preambles <A> Da1to Da8and preamble <B> Db2and a three-bit or more error in the preamble <B> Db2. In this example, the bit-error detecting section411has the internal structure ofFIG. 5A, the bit-error detecting section421has the internal structure ofFIG. 5B, each of the preamble <A> detecting sections202ato202hhas the internal structure ofFIG. 6, and each of the preamble <B> detecting sections203a,203bhas the internal structure ofFIG. 7.

In this case, the bit errors of the preambles <A> Da1to Da8and the preambles <B> Db1, Db2are not corrected in the preamble <A> error correcting section401and the preamble <B> error correcting section402. The preamble <A> detecting sections202ato202hand the preamble <B> detecting sections203a,203bthen receive the preambles <A> Da1to Da8and the preambles <B> Db1, Db2. As a result, the pattern represented by the respective output values (the output value pattern) is “1011111111” in the order from the preamble <B> detecting section203bto the preamble <A> detecting section202a.Since this output value pattern matches the error pattern P110, the error-pattern determining section104outputs a data detection signal.

As has been described above, an identification signal can be accurately detected even when bit errors cannot be completely corrected by the preamble <A> error correcting section401and the preamble <B> error correcting section402. The seventh embodiment thus has improved capability of detecting an identification signal over the fourth embodiment.

Eighth Embodiment

FIG. 14shows the overall structure of a multi-channel data detector8according to the eighth embodiment of the present invention. The data detector8receives a plurality of input data (first input data Data1and second input data Data2) transmitted through different transmission paths. The data detector8adjusts the difference in delay (skew) between the plurality of input data to zero, and detects an identification signal included in each of the plurality of input data. The data detector8includes input terminals801a,801b, flip-flops802a,802b,2-channel data detecting sections803ato803c, a skew determining section804, and selecting sections805a,805b. The input terminal801areceives the first input data Data1from the outside. The input terminal801breceives the second input data Data2from the outside. The flip-flop802adelays the first input data Data1received by the input terminal801aby one clock cycle. The flip-flop802bdelays the second input data Data2received by the input terminal801bby one clock cycle. The 2-channel data detecting section803adetermines whether or not there is a skew between the first input data Data1delayed by the flip-flop802aand the second input data Data2received by the input terminal801b. The 2-channel data detecting section803aoutputs a timing match signal S803aif there is no skew therebetween. The 2-channel data detecting section803bdetermines whether or not there is a skew between the first input data Data1received by the input terminal801aand the second input data Data2received by the input terminal801b. The 2-channel data detecting section803boutputs a timing match signal S803bif there is no skew therebetween. The 2-channel data detecting section803cdetermines whether or not there is a skew between the first input data Data1received by the input terminal801aand the second input data Data2delayed by the flip-flop802b. The 2-channel data detecting section803coutputs a timing match signal S803cif there is no skew therebetween. Based on the timing match signals S803ato S803cfrom the 2-channel data detecting sections803ato803c, the skew determining section804outputs selection signals S804a, S804bto the selecting sections805a,805b,respectively, and outputs a data extraction start signal St to an apparatus of the subsequent stage. The selection signals S804a, S804bindicate whether the input data from the input terminal or the input data from the flip-flop is to be selected. Based on the selection signal S804afrom the skew determining section804, the selecting section805aselects the first input data Data1received by the input terminal801aor the first input data Data1delayed by the flip-flop802a, and outputs the selected first input data Data1to the apparatus of the subsequent stage. Based on the selection signal S804bfrom the skew determining section804, the selecting section805bselects the second input data Data2received by the input terminal801bor the second input data Data2delayed by the flip-flop802b, and outputs the selected second input data Data2to the apparatus of the subsequent stage.

[Internal Structure of the 2-Channel Data Detecting Sections803ato803c]

Hereinafter, the internal structure of the 2-channel data detecting sections803ato803cofFIG. 14will be described. Since the 2-channel data detecting sections803ato803chave the same internal structure, the internal structure of the 2-channel data detecting section803ais shown inFIG. 15. The 2-channel data detecting section803aincludes identification-signal match detecting sections806a,806band an AND section807. The identification-signal match detecting section806areceives first input data Data1. The identification-signal match detecting section806aoutputs a data detection signal S806ato the AND section807upon detecting an identification signal (preambles <A> Da1to Da8and preambles <B> Db1, Db2) from the received input data Data1. The identification-signal match detecting section806breceives second input data Data2. The identification-signal match detecting section806boutputs a data detection signal S806bto the AND section807upon detecting an identification signal (preambles <A> Da1to Da8and preambles <B> Db1, Db2) from the received input data Data2. The AND section807outputs a timing match signal S803aupon receiving both data detection signals S806aand S806bfrom the identification-signal match detecting sections806aand806b.

[Structure of the First and Second Input Data Data1, Data2]

FIGS. 16A and 16Erespectively show the first input data Data1and the second input data Data2which are input to the multi-channel data detector8ofFIG. 14. The first input data Data1and the second input data Data2have the same structure as the input data Data ofFIG. 2. The first input data Data1has first information data Dmain1as information data Dmain. The second input data Data2has second information data Dmain2as information data Dmain. Note that the first input data Data1has the same data length as the second input data Data2.

Hereinafter, operation of the multi-channel data detector8ofFIG. 14will be described.

The input terminal801areceives the first input data Data1from the outside. The input terminal801breceives the second input data Data2from the outside.

The flip-flop802adelays the first input data Data1received by the input terminal801aby one clock cycle, and outputs the delayed first input data Data1to the 2-channel data detecting section803a. The flip-flop802bdelays the second input data Data2received by the input terminal801bby one clock cycle, and outputs the delayed second input data Data2to the 2-channel data detecting section803c.

In the 2-channel data detecting section803a, the identification-signal match detecting section806areceives the delayed first input data Data1from the flip-flop802a,and the identification-signal match detecting section806breceives the second input data Data2from the input terminal801b.

In the 2-channel data detecting section803b, the identification-signal match detecting section806areceives the first input data Data1from the input terminal801a,and the identification-signal match detecting section806breceives the second input data Data2from the input terminal801b.

In the 2-channel data detecting section803c, the identification-signal match detecting section806areceives the first input data Data1from the input terminal801a,and the identification-signal match detecting section806breceives the delayed second input data Data2from the flip-flop802b.

The identification-signal match detecting section806ain each of the 2-channel data detecting sections803ato803coutputs a data detection signal S806aupon detecting an identification signal in the received first input data Data1. For example, the identification-signal match detecting section806astores a pattern P[10:10] of an identification signal having no bit error (i.e., a pattern of a normal identification signal). The identification-signal match detecting section806aoutputs a data detection signal S806awhen the received first input data (100 bits) matches the stored pattern P[10:10] of a normal identification signal. Like the identification-signal match detecting section806a,the identification-signal match detecting section806bin each of the 2-channel data detecting sections803a,803b,803coutputs a data detection signal S806bupon detecting an identification signal in the received second input data Data2.

The AND section807in each of the 2-channel data detecting sections803a,803b,803coutputs a timing match signal S803a, S803b, S803cto the skew determining section804upon receiving both data detection signals S806aand S806bfrom the identification-signal match detecting sections806aand806b.

According to the timing match signals S803a, S803b, S803cfrom the 2-channel data detecting sections803a,803b,803c, the skew determining section804outputs a selection signal S804ato the selecting section805a, and outputs a selection signal S804bto the selecting section805b. The selection signal S804ais a signal indicating which of the first input data Data1from the input terminal801aand the first input data Data1from the flip-flop802ais to be selected. The selection signal S804bis a signal indicating which of the second input data Data2from the input terminal801band the second input data Data2from the flip-flop802bis to be selected. For example, when the 2-channel data detecting section803boutputs the timing match signal S803bto the skew determining section804, the skew determining section804outputs to the selecting section805aa selection signal S804afor selecting the first input data Data1received by the input terminal801a, and outputs to the selecting section805ba selection signal S804bfor selecting the second input data Data2received by the input terminal801b.

In addition to the selection signals S804a, S804bto the selecting sections805a,805b, the skew determining section804also outputs a data extraction start signal St to an apparatus of the subsequent stage.

The selecting section805aselects the first input data Data1from the input terminal801aor the first input data Data1from the flip-flop802aaccording to the selection signal S804afrom the skew determining section804. The selecting section805athen outputs the selected first input data Data1to the apparatus of the subsequent stage. The selecting section805bselects the second input data Data2from the input terminal801bor the second input data Data2from the flip-flop802baccording to the selection signal S804bfrom the skew determining section804. The selecting section805bthen outputs the selected second input data to the apparatus of the subsequent stage.

For example, as shown inFIG. 2, the apparatus of the subsequent stage produces a data period signal which is held at “1” for the same period as the period L of the information data Dmain based on the data extraction start signal St. The apparatus of the subsequent stage can thus accurately extract the period of the information data Dmain1, Dmain2from the input data Data1, Data2.

The above operation will now be described specifically. It is herein assumed that the second input data Data2is one clock behind the first input data Data1(FIGS. 16A,16E). In other words, there is a one-clock skew between the first input data Data1and the second input data Data2. Note that the first input data Data1and the second input data Data2have no bit error.

The flip-flop802adelays the first input data Data1received by the input terminal801aby one clock cycle (FIG. 16C). The flip-flop802bdelays the second input data Data2received by the input terminal801bby one clock cycle (FIG. 16G).

The identification-signal match detecting sections806a,806bof the 2-channel data detecting section803aoutput data detection signals S806a, S806bat the same timing (FIGS. 16D,16F). The AND section807therefore outputs a timing match signal S803ato the skew determining section804(FIG. 16I).

On the other hand, the identification-signal match detecting sections806a,806bof the 2-channel data detecting section803bdo not output data detection signals S806a,S806bat the same timing (FIGS. 16B,16F). The AND section807therefore does not output a timing match signal S803b. The identification-signal match detecting sections806a,806bof the 2-channel data detecting section803cdo not output data detection signals S806a, S806bat the same timing (FIGS. 16B,16H). The AND section807therefore does not output a timing match signal S803c.

Since the timing match signal S803ais output from the 2-channel data detecting section803a, the skew determining section804detects that the second input data is one clock behind the first input data. The skew determining section804therefore outputs to the selecting section805aa selection signal S804afor selecting the first input data Data1from the flip-flop802a, and also outputs to the selecting section805ba selection signal S804bfor selecting the second input data Data2from the input terminal801b. In addition, the skew determining section804outputs a data extraction start signal St to the apparatus of the subsequent stage.

The selecting section805aselects the first input data Data1from the flip-flop802a,i.e., the first input data Data1delayed by one clock cycle, according to the selection signal S804afrom the skew determining section804, and outputs the selected first input data Data1to the apparatus of the subsequent stage. The selecting section805bselects the second input data Data2from the input terminal801baccording to the selection signal S804bfrom the skew determining section804, and outputs the selected second input data Data2to the apparatus of the subsequent stage.

For example, the apparatus of the subsequent stage then produces a data period signal (FIG. 2) which is held at “1” for the same period as the period L of the information data Dmain based on the data extraction start signal St from the skew determining section804. As a result, the period of the information data Dmain1, Dmain2is accurately extracted from the input data Data1, Data2.

As has been described above, a skew between channels can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected with a simple structure.

The number of channels is two in the above example. However, a skew between channels can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected with a similar structure even when the number of channels is K or more (where K is a natural number).

A skew between channels is one clock in the above example. However, a skew between channels can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected with a similar structure even when a skew between channels is two clocks or more. In this case, the multi-channel data detector includes the same number of flip-flops as the number of clocks of a skew to be corrected, and the 2-channel data detecting sections detect an identification signal.

Ninth Embodiment

FIG. 17shows the overall structure of a multi-channel data detector9according to the ninth embodiment of the present invention. The data detector9includes input terminals901a,901b, identification-signal match detecting sections806a,806b, a skew determining section902, a control section903, and buffers904a,904b. The input terminal901areceives first input data Data1from the outside. The input terminal901breceives second input data Data2from the outside. The skew determining section902receives data detection signals S806a, S806bfrom the identification-signal match detecting sections806a,806b, respectively, and outputs the data detection signals S806a,S806bto the control section903. Based on the data detection signals S806a, S806b, the skew determining section902detects the timing a skew between the first input data Data1and the second input data Data2becomes zero. The skew determining section902then outputs to the control section903a timing match signal S902indicating the detected timing. The control section903outputs a write start signal Sw to each buffer904a,904baccording to the data detection signals S806a, S806bfrom the identification-signal match detecting sections806a,806b. The control section903also outputs a read start signal Sr to each buffer904a,904bas well as outputs a data extraction start signal St to an apparatus of the subsequent stage according to the timing match signal S902from the skew determining section902. The buffer904astores the first input data Data1from the input terminal901ain response to the write start signal Sw from the control section903. The buffer904aoutputs the stored first input data Data1in response to the read start signal Sr from the control section903. The buffer904bstores the second input data Data2from the input terminal901bin response to the write start signal Sw from the control section903. The buffer904boutputs the stored second input data Data2in response to the read start signal Sr from the control section903.

[Internal Structure of the Skew Determining Section902]

The skew determining section902ofFIG. 17includes flip-flops905a,905band a skew detecting section906. The flip-flop905adelays a data detection signal S806afrom the identification-signal match detecting section806aby one clock cycle, and outputs the delayed data detection signal S905a. The flip-flop905bdelays a data detection signal S806bfrom the identification-signal match detecting section806bby one clock cycle, and outputs the delayed data detection signal S905b. The skew detecting section906outputs a timing match signal S902based on the data detection signal S806afrom the identification-signal match detecting section806a, the data detection signal S905afrom the flip-flop905a, the data detection signal S806bfrom the identification-signal match detecting section806band the data detection signal S905bfrom the flip-flop905b.

Hereinafter, operation of the multi-channel data detector9ofFIG. 17will be described.

The input terminal901areceives the first input data Data1from the outside. The input terminal901breceives the second input data Data2from the outside.

The identification-signal match detecting section806aprocesses the first input data Data1from the input terminal901ain the same manner as the eighth embodiment, and outputs a data detection signal S806a. The identification-signal match detecting section806bprocesses the second input data Data2from the input terminal901bin the same manner as the eighth embodiment, and outputs a data detection signal S806b.

Upon receiving the data detection signal S806afrom the identification-signal match detecting section806athrough the skew determining section902, the control section903outputs a write start signal Sw to the buffer904a. In response to the write start signal Sw from the control section903, the buffer904astarts storing the first input data Data1from the input terminal901a. Upon receiving the data detection signal S806bfrom the identification-signal match detecting section806bthrough the skew determining section902, the control section903outputs a write start signal Sw to the buffer904b. In response to the write start signal Sw from the control section903, the buffer904bstarts storing the second input data Data2from the input terminal901b.

The flip-flop905adelays the data detection signal S806afrom the identification-signal match detection signal806aby one clock cycle, and outputs the delayed data detection signal S905ato the skew detecting section906. The flip-flop905bdelays the data detection signal S806bfrom the identification-signal match detecting section806bby one clock cycle, and outputs the delayed data detection signal S905bto the skew detecting section906.

The skew detecting section906detects a combination of data detection signals which are output at the same timing from the data detection signal S806afrom the identification-signal match detecting section806a, the data detection signal S905afrom the flip-flop905a, the data detection signal S806bfrom the identification-signal match detecting section S806band the data detection signal S905bfrom the flip-flop905b. The skew detecting section906then outputs a timing match signal S902to the control section903in synchronization with the rise of the detected data detection signals.

The control section903outputs a read start signal Sr to the buffers904a,904bas well as outputs a data extraction start signal St to the outside after a time period corresponding to L has passed since the skew detecting section906output the timing match signal S902. L is the length of the first information data Dmain1included in the first input data Data1(or the second information data Dmain2included in the second input data Data2).

The buffer904astarts outputting the stored first input data Data1to an apparatus of the subsequent stage in response to the read start signal Sr from the control section903. The buffer904bstarts outputting the stored second input data Data2to the apparatus of the subsequent stage in response to the read start signal Sr from the control section903.

For example, the apparatus of the subsequent stage obtains the first information data Dmain1from the buffer904aand the second information data Dmain2from the buffer904bin response to the data extraction start signal St from the control section903.

The above operation will now be described specifically. It is herein assumed that the second input data Data2is one clock behind the first input data Data1(FIGS. 16A,16E). In other words, there is a one-clock skew between the first input data Data1and the second input data Data2. Note that the first input data Data1and the second input data Data2have no bit error.

When the identification-signal match detecting section806aoutputs a data detection signal S806aand the control section903outputs a write start signal Sw to the buffer904a, the buffer904astarts storing the first input data Data1from the input terminal901a. More specifically, the buffer904astores the first information data Dmain1of the first input data Data1.

When the identification-signal match detecting section806boutputs a data detection signal S806band the control section903outputs a write start signal Sw to the buffer904b, the buffer904bstarts storing the second input data Data2from the input terminal901b. More specifically, the buffer904bstores the second information data Dmain2of the second input data Data2.

The data detection signals S806a, S806b, S905a, S905bfrom the identification-signal match detecting sections806a,806band the flip-flops905a,905bare as shown inFIGS. 16B,16F,16D and16H, respectively. Referring toFIGS. 16A to 16J, the timing the data detection signal S806bis output from the identification-signal match detecting section806b(FIG. 16F) is the same as the timing the data detection signal S905ais output from the flip-flop905a(FIG. 16D). No other combinations of data detection signals are output at the same timing. The skew detecting section906therefore detects that the second input data Data2is one clock behind the first input data Data1.

When the skew detecting section906outputs a timing match signal S902in synchronization with the rise of the data detection signal S806b(or the data detection signal S905a) (FIG. 16I), the control section903outputs a read start signal Sr (FIG. 16J) to each buffer904a,904bas well as outputs a data extraction start signal St to an apparatus of the subsequent stage after a time period corresponding to L has passed since the rise of the timing match signal S902. L is the length of the first information data Dmain1(or the second information data Dmain2).

The buffer904astarts outputting the stored first information data Dmain1to the apparatus of the subsequent stage in response to the read start signal Sr from the control section903. The buffer904bstarts outputting the stored second information data Dmain2to the apparatus of the subsequent stage in response to the read start signal Sr from the control section903.

As has been described above, a skew between channels can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected with a simple structure.

The number of channels is two in the above example. However, a skew between channels can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected with a similar structure even when the number of channels is K or more (where K is a natural number).

A skew between channels is one clock in the above example. However, a skew between channels can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected with a similar structure even when a skew between channels is two clocks or more. In this case, the multi-channel data detector includes the same number of flip-flops as the number of clocks of a skew to be corrected, and the skew detecting section detects a skew between channels.

Tenth Embodiment

FIG. 18shows the overall structure of a multi-channel data detector10according to the tenth embodiment of the present invention. The multi-channel data detector10has the same structure as the multi-channel data detector ofFIG. 17except that the skew determining section902, the control section903and the buffers904a,904bofFIG. 17are replaced with a skew determining section1001and delay correcting sections1002a,1002b. Based on data detection signals S806a, S806bfrom the identification-signal match detecting sections806a,806b, the skew determining section1001outputs a data extraction start signal St to an apparatus of the subsequent stage and outputs a skew correction signal Sc to each delay correcting section1002a,1002b. The skew correction signal Sc is a signal for adjusting the skew to zero. The delay correcting sections1001a,1001bcorrect the skew between the first input data Data1and the second input data Data2according to the skew correction signal Sc from the skew determining section1001.

[Internal Structure of the Skew Determining Section1001]

The skew determining section1001ofFIG. 18has the same structure as the skew determining section902ofFIG. 17except that the skew detecting section906ofFIG. 17is replaced with a skew detecting section1003. The skew detecting section1003outputs a data extraction start signal St to the apparatus of the subsequent stage as well as outputs a skew correction signal Sc to each delay correcting section1002a,1002b, based on a data detection signal S806afrom the identification-signal match detecting section806a, a data detection signal S905afrom the flip-flop905a, a data detection signal S806bfrom the identification-signal match detecting section806b, and a data detection signal S905bfrom the flip-flop905b.

[Internal Structure of the Delay Correcting Sections1002a,1002b]

The delay correcting section1002aofFIG. 18includes a flip-flop1004aand a selecting section1005a. The flip-flop1004adelays the first input data Data1received by the input terminal901aby one clock cycle. The selecting section1005aselects the first input data Data1from the input terminal901aor the delayed first input data Data1from the flip-flop1004aaccording to the skew correction signal Sc from the skew detecting section1003. The selecting section1005athen outputs the selected first input data Data1to the apparatus of the subsequent stage.

The delay correcting section1002bofFIG. 18includes a flip-flop1004band a selecting section1005b. The flip-flop1004bdelays the second input data Data2received by the input terminal901bby one clock cycle. The selecting section1005bselects the second input data Data2from the input terminal901bor the delayed second input data Data2from the flip-flop1004baccording to the skew correction signal Sc from the skew detecting section1003. The selecting section1005bthen outputs the selected second input data Data2to the apparatus of the subsequent stage.

Operation of the multi-channel data detector10ofFIG. 18is different from that of the multi-channel data detector ofFIG. 17in the processing after detection of a skew.

Like the skew detecting section906, the skew detecting section1003detects a combination of data detection signals which are output at the same timing from the data detection signal S806afrom the identification-signal match detecting section806a, the data detection signal S905afrom the flip-flop905a, the data detection signal S806bfrom the identification-signal match detecting section806band the data detection signal S905bfrom the flip-flop905b.

The flip-flop1004adelays the first input data Data1received by the input terminal901aby one clock cycle. The flip-flop1004bdelays the second input data Data2received by the input terminal901bby one clock cycle.

The skew detecting section1003outputs a data extraction start signal St to the apparatus of the subsequent stage as well as outputs a skew correction signal Sc to the delay correcting sections1002a,1002bin synchronization with the rise of the detected data detection signals. The skew correction signal Sc indicates which of the input data from the input terminal and the input data from the flip-flop is to be selected.

The selecting section1005aselects the first input data Data1from the input terminal901aor the delayed first input data Data1from the flip-flop1004aaccording to the skew correction signal Sc from the skew detecting section1003. The selecting section1005athen outputs the selected first input data Data1to the apparatus of the subsequent stage. The selecting section1005bselects the second input data Data2from the input terminal901bor the delayed second input data Data2from the flip-flop1004baccording to the skew correction signal Sc from the skew detecting section1003. The selecting section1005bthen outputs the selected second input data Data2to the apparatus of the subsequent stage.

The above operation will now be described specifically. It is herein assumed that the second input data Data2is one clock behind the first input data Data1(FIGS. 16A,16E). In other words, there is a one-clock skew between the first input data Data1and the second input data Data2. Note that the first input data Data1and the second input data Data2have no bit error.

Like the ninth embodiment, the skew detecting section1003detects that the second input data Data2is one clock behind the first input data Data1, and outputs a data extraction start signal St to the apparatus of the subsequent stage in synchronization with the rise of the data detection signal S806b(or the data detection signal S905a). At the same time, the skew detecting section1003outputs to the selecting section1005aa skew correction signal Sc for selecting the delayed first input data Data1from the flip-flop1004a, and outputs to the selecting section1005ba skew correction signal Sc for selecting the second input data Data2from the input terminal901b.

The selecting section1005aoutputs the selected first input data, i.e., the delayed first input data from the flip-flop1004a, to the apparatus of the subsequent stage according to the skew correction signal Sc from the skew detecting section1003. The selecting section1005boutputs the selected second input data, i.e., the second input data from the input terminal901b, to the apparatus of the subsequent stage according to the skew correction signal Sc from the skew detecting section1003.

As has been described above, a skew between channels can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected with a simple structure.

The number of channels is two in the above example. However, a skew between channels can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected with a similar structure even when the number of channels is K or more (where K is a natural number).

A skew between channels is one clock in the above example. However, a skew between channels can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected with a similar structure even when a skew between channels is two clocks or more. In this case, the multi-channel data detector includes the same number of flip-flops as the number of clocks of a skew to be corrected, and the skew detecting section detects a skew between channels.

Eleventh Embodiment

[Relation Between a Skew and a Bit Error]

If there is a defective transmission path, a skew is likely to be generated between a plurality of input data transmitted through different transmission paths. Moreover, input data transmitted through a defective transmission path is likely to have bit errors. Accordingly, if there is a skew between a plurality of input data, the input data is likely to have bit errors.

A multi-channel data detector according to the eleventh embodiment of the present invention has the same structure as the multi-channel detector ofFIG. 14except that the 2-channel data detecting sections803a,803b,803cofFIG. 14are replaced with 2-channel data detecting sections1101a,1101b,1101cofFIG. 19(Since the 2-channel data detecting sections1101a,1101b,1101chave the same internal structure, only the internal structure of the 2-channel data detecting section1101ais shown inFIG. 19.). The 2-channel data detecting section1101adetermines whether or not there is a skew between the first input data Data1delayed by the flip-flop802aand the second input data Data2received by the input terminal801b. The 2-channel data detecting section1101aoutputs a timing match signal S1101aif there is no skew therebetween. The 2-channel data detecting section1101bdetermines whether or not there is a skew between the first input data Data1received by the input terminal801aand the second input data Data2received by the input terminal801b. The 2-channel data detecting section1101boutputs a timing match signal S1101bif there is no skew therebetween. The 2-channel data detecting section1101cdetermines whether or not there is a skew between the first input data Data1received by the input terminal801aand the second input data Data2delayed by the flip-flop802b.The 2-channel data detecting section1101coutputs a timing match signal S1101cif there is no skew therebetween. The skew determining section804outputs selection signals S804a, S804bto the selecting sections805a,805b, respectively, as well as outputs a data extraction start signal St to an apparatus of the subsequent stage, according to the timing match signals S1101ato S1101cfrom the 2-channel data detecting sections1101ato1101c.The selection signals S804a, S804bare signals indicating which of the input data from the input terminal and the input data from the flip-flop is to be selected.

[Internal Structure of the 2-Channel Data Detecting Sections]

The 2-channel data detecting sections1101a,1101b,1101cwill now be described. Since the 2-channel data detecting sections1101a,1101b,1101chave the same internal structure, only the 2-channel data detecting section1101awill be described. The 2-channel data detecting section1101ahas the same structure as the 2-channel data detecting section803aofFIG. 15except that the identification-signal match detecting sections806a,806bare replaced with data detectors1a,1b. Each data detector1a,1bhas the same structure as the data detector1ofFIG. 1. Each data detector1a,1breceives input data Data1or Data2and outputs a data detection signal S1aor Sab.

The multi-channel data detector of the eleventh embodiment is different from the eighth embodiment in operation of the 2-channel data detecting sections1101a,1101b,1102c.

The data detector1ain each 2-channel data detecting section1101a,1101b,1101cdetects an identification signal (preambles <A> Da1to Da8and preambles <B> Db1, Db2) and outputs a data detection signal S1aby processing the first input data Data1in the same manner as the first embodiment.

The data detector1bin each 2-channel data detecting section1101a,1101b,1101cdetects an identification signal (preambles <A> Da1to Da8and preambles <B> Db1, Db2) and outputs a data detection signal S1bby processing the second input data Data2in the same manner as the first embodiment.

[Comparison to the Eighth Embodiment]

Hereinafter, operation of the eighth embodiment and the eleventh embodiment will be described. It is herein assumed that the first input data Data1and the second input data Data2have bit errors.

In the multi-channel data detector8of the eighth embodiment, the bit pattern of the received identification signal does not match the identification-signal pattern P[10:10] stored in the identification-signal match detecting sections806a,806b. The identification-signal match detecting sections806a,806btherefore do not output data detection signals S806a, S806b.

In the multi-channel data detector of the eleventh embodiment, however, the data detectors1a,1bcan detect the identification signal by respectively processing the first and second input data Data1, Data2in the same manner as the first embodiment. The data detectors1a,1btherefore output data detection signals S1a, S1b, respectively.

As has been described above, the data detection signals S1a, S1bare output even when the input data have bit errors. By using the signals S1a, S1b, a skew can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected. The eleventh embodiment thus has improved capability of detecting information data over the eighth embodiment.

In the eleventh embodiment, the data detector1ofFIG. 1is used as the data detectors1a,1b. However, the present invention is not limited to this. The data detectors2,3,4,5,6,7ofFIGS. 4,8,9,11,12,13may alternatively be used as the data detectors1a,1b.

Twelfth Embodiment

FIG. 20shows the overall structure of a multi-channel data detector12according to the twelfth embodiment of the present invention. The multi-channel data detector12has the same structure as the multi-channel data detector ofFIG. 17except that the identification-signal match detecting sections806a,806bofFIG. 17are replaced with data detectors1a,1b. Each data detector1a,1bhas the same structure as the data detector1ofFIG. 1. The data detectors1a,1breceive input data and output data detection signals S1a, S1b, respectively. The skew determining section902receives the data detection signals S1a, S1bfrom the data detectors1a,1b, respectively, and outputs the received data detection signals S1a, S1bto the control section903. Based on the data detection signals S1a, S1b, the skew determining section902detects the timing a skew between the first input data Data1and the second input data Data2becomes zero. The skew determining section902then outputs to the control section903a timing match signal S902indicating the detected timing. The control section903outputs a write start signal Sw to each buffer904a,904bbased on the data detection signals S1a, S1bfrom the data detectors1a,1b.Based on the timing match signal S902from the skew determining section902, the control section903outputs a read start signal Sr to each buffer904a,904band outputs a data extraction start signal St to an apparatus of the subsequent stage.

[Comparison to the Ninth Embodiment]

Hereinafter, operation of the ninth embodiment and the twelfth embodiment will be described. It is herein assumed that the first input data Data1and the second input data Data2have bit errors.

In the multi-channel data detector9of the ninth embodiment, the bit pattern of the received identification signal does not match the identification-signal pattern P[10:10] stored in the identification-signal match detecting sections806a,806b. The identification-signal match detecting sections806a,806btherefore do not output data detection signals S806a, S806b.

In the multi-channel data detector12of the twelfth embodiment, however, the data detectors1a,1bcan detect the identification signal by respectively processing the first and second input data Data1, Data2in the same manner as the first embodiment. The data detectors1a,1btherefore output data detection signals S1a, S1b, respectively.

As has been described above, the data detection signals S1a, S1bare output even when the input data have bit errors. By using the signals S1a, S1b, a skew can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected. The twelfth embodiment thus has improved capability of detecting information data over the ninth embodiment.

In the twelfth embodiment, the data detector1ofFIG. 1is used as the data detectors1a,1b. However, the present invention is not limited to this. The data detectors2,3,4,5,6,7ofFIGS. 4,8,9,11,12,13may alternatively be used as the data detectors1a,1b.

Thirteenth Embodiment

FIG. 21shows the overall structure of a multi-channel data detector13according to the thirteenth embodiment of the present invention. The multi-channel data detector13has the same structure as the multi-channel data detector ofFIG. 18except that the identification-signal match detecting sections806a,806bofFIG. 18are replaced with data detectors1a,1b. Each data detector1a,1bhas the same structure as the data detector1ofFIG. 1. The data detectors1a,1breceive input data and output data detection signals S1a, S1b, respectively. Based on the data detection signals S1a, S1bfrom the data detectors1a,1b, the skew determining section1001outputs a data extraction start signal St to an apparatus of the subsequent stage and outputs a skew correction signal Sc to each delay correcting section1002a,1002b. The skew correction signal Sc is a signal for adjusting the skew to zero.

[Comparison to the Tenth Embodiment]

Hereinafter, operation of the tenth embodiment and the thirteenth embodiment will be described. It is herein assumed that the first input data Data1and the second input data Data2have bit errors.

In the multi-channel data detector10of the tenth embodiment, the bit pattern of the received identification signal does not match the identification-signal pattern P[10:10] stored in the identification-signal match detecting sections806a,806b. The identification-signal match detecting sections806a,806btherefore do not output data detection signals S806a, S806b.

In the multi-channel data detector13of the thirteenth embodiment, however, the data detectors1a,1bcan detect the identification signal by respectively processing the first and second input data Data1, Data2in the same manner as the first embodiment. The data detectors1a,1btherefore output data detection signals S1a, S1b, respectively.

As has been described above, the data detection signals S1a, S1bare output even when the input data have bit errors. By using the signals S1a, S1b, a skew can be adjusted to zero and the timing of extracting information data Dmain1, Dmain2can be accurately detected. The thirteenth embodiment thus has improved capability of detecting information data over the tenth embodiment.

In the thirteenth embodiment, the data detector1ofFIG. 1is used as the data detectors1a,1b. However, the present invention is not limited to this. The data detectors2,3,4,5,6,7ofFIGS. 4,8,9,11,12,13may alternatively be used as the data detectors1a,1b.

For example, the present invention is useful for interfaces of DVD (Digital Versatile Disc) players, liquid crystal televisions and digital televisions.