Read Gate Training and Tracking

In accordance with described techniques for read gate training and tracking, a computing device includes a memory system (e.g., dynamic random access memory (DRAM)) that receives a memory read operation which includes a memory clock that correlates to a physical layer (PHY) clock. The computing device includes a PHY that receives a return data signal from the memory system, where the return data signal includes a returned data strobe that is out-of-phase with respect to the PHY clock. The computing device includes training logic that utilizes edge detection to determine an unknown clocking phase of the returned data strobe with respect to the PHY clock. The computing device also includes tracking logic that utilizes the edge detection to detect a signal drift of the delay signal with respect to the returned data strobe and compensate for the drift.

BACKGROUND

The physical memory, such as dynamic random access memory and associated memory controllers, utilized in computing systems to manage data storage, as well as how this data is made available to processing devices (e.g., a central processing unit, graphics processing unit, auxiliary processing unit, parallel accelerated processor, and so forth). As such, efficiency in data storage and access to data directly affects the operation of these devices, examples of which include processing speed, bandwidth, and power consumption. Conventional techniques for memory operations introduce latency, thereby hindering performance of the memory operations as well as device operations that rely on data that is a subject of the memory operations.

DETAILED DESCRIPTION

Efficiency of data access to and from device memory has a direct effect on efficiency of overall device operation. The data stored by a computing device in a physical memory (e.g., a dynamic random access memory (DRAM)) is subject to operation instructions communicated from a memory controller, such as for read and write memory operations. The memory controller and physical memory are communicatively coupled to a physical layer (PHY) of the device (also referred to as the PHY layer, or PHY logic). The physical layer causes the physical memory to push data subject to a memory read operation received from the memory controller to a first-in, first-out (FIFO) buffer, and the data is then output from the buffer back to the memory controller. The PHY communicatively couples the memory controller with the physical memory, and includes the FIFO buffer as a read data buffer that supports memory read operations and data communication between the physical memory and the memory controller.

In device implementation, the PHY receives a memory read operation initiated by the memory controller. The PHY signals the memory read operation to the physical memory as a read command signal and a memory clock, where the memory clock correlates to the current timing of a PHY clock. In response to the memory read operation, the PHY receives a return data signal (DQs) from the memory system, and the return data signal includes a returned data strobe (DQS). However, the PHY receives the returned data strobe which is out-of-phase with respect to the PHY clock (e.g., the returned data strobe may be delayed by several nano-seconds), such as due to a timing latency that has been introduced in returning the requested data and/or due to latency caused by the physical signal communication path. This unknown data strobe latency needs to be accounted for before any memory read transaction.

To solve the latency and phase relationship of the returned data strobe with respect to the PHY clock, aspects of the described techniques support implementations of read gate training and tracking. In one or more implementations, a read gate logic system in the PHY includes training logic and tracking logic utilized in conjunction to determine and compensate for unknown data strobe latency and phase. The training logic generates a pulse width filter signal to filter a high impedance state of the returned data strobe, which is returned from the physical memory in an unknown phase with respect to the PHY clock. This involves the training logic utilizing a phase detectors circuit and an adjustable delay line, and subsequently generating a timing mask as a delay signal to filter the high impedance state of the returned data strobe. Additionally, the tracking logic utilizes the phase detectors circuit to detect possible drift of the timing mask relative to the data strobe and further adjusts the delay line to compensate for the drift.

In device circuit implementations, the circuits are typically subject to power, voltage, and/or temperature (PVT) variation that affects signal timing and overall memory system operation performance. In aspects of this disclosure for read gate training and tracking, the tracking logic is implemented to detect the drift of the timing mask with respect to an incoming data strobe due to variations, and compensate for it by incrementing or decrementing the delay line. Accordingly, the unknown clocking phase of a returned data strobe from the physical memory is determined (e.g., by the training logic), and the determined strobe phase is maintained by monitoring and compensating for signal drift (e.g., by the tracking logic), which is a result of variation over time.

In aspects of the described techniques, read gate logic is implemented in PHY as hardware and/or software logic, such as a software implementation that initiates and controls the training logic and the tracking logic of the read gate logic. Notably, aspects of the described read gate training and tracking can be utilized with any type of CPU, APU, GPU, and/or FPGA hardware in a processing and memory system. In further aspects of the described read gate training and tracking, the tracking logic is initiated during return data signals to track the signal drift of a determined timing mask relative to the data strobe, and the training logic is also initiated during the return data signals that are communicated back from the memory system to determine the timing mask that filters the high impedance state of the returned data strobe with respect to the PHY clock. Accordingly, operational performance of the memory operations between the PHY and the physical memory is maintained by both training and the tracking logic being initiated during a return data signal communicated from the memory system.

Various aspects of the described read gate training and tracking provides a solution for memory initialization and operations so that the PHY and/or memory controller trains incoming data signals and data strobe (DQS) timing with respect to its own internal clocking, such that PHY can properly utilize the valid strobes to sample the data (DQs) and filter out a high impedance (Hi-Z) state on the line. In implementations, the training logic and the tracking logic of the PHY read gate logic utilize edge detection techniques along with cycle and sub-cycle base adjustment, to determine the assertion of DQS valid window (tDV). An intended position is at the preamble low region with a +/−2UI valid window margin (VWM) to accommodate DRAMs versus PHY timing drift due to, in particular, voltage and timing (VT) variations. In further aspects of the described techniques, the delay line is configurable to determine the assertion time of DQS valid window to filter the high impedance state, and this valid window is self-closing. The self-closing aspect is provided by having a FIFO read pointer clocked by incoming DQS to determine the de-assertion of the DQS valid window, where the clocking by the incoming DQS is subject to the drift from a DRAM is tracked accordingly. A FIFO buffer provides the programming capability to determine the number of DQS cycles need to be passed through.

In some aspects, the techniques described herein relate to a computing device comprising a memory system to receive a memory read operation that includes a memory clock which correlates to a physical layer (PHY) clock, a PHY to receive a return data signal from the memory system, the return data signal including a returned data strobe that is out-of-phase with respect to the PHY clock, and training logic configured to utilize edge detection and delay adjustment to determine an unknown clocking phase of the returned data strobe with respect to the PHY clock.

In some aspects, the techniques described herein relate to a computing device further comprising a phase detectors circuit including a first phase detector and a second phase detector implementing the edge detection.

In some aspects, the techniques described herein relate to a computing device where the training logic generates a pulse width filter signal to filter a high impedance state of the returned data strobe with respect to the PHY clock.

In some aspects, the techniques described herein relate to a computing device where the training logic determines a timing mask as a delay signal to filter a high impedance state of the returned data strobe with respect to the PHY clock.

In some aspects, the techniques described herein relate to a computing device where the delay signal is configurable with extended pulses to filter the high impedance state, and the delay signal is self-closing.

In some aspects, the techniques described herein relate to a computing device further comprising tracking logic configured to utilize the edge detection to detect a signal drift of the delay signal with respect to the returned data strobe.

In some aspects, the techniques described herein relate to a computing device where the tracking logic is configured to detect an advancing signal drift of the delay signal with respect to the returned data strobe, and the tracking logic is configured to decrement the delay signal.

In some aspects, the techniques described herein relate to a computing device where the tracking logic is configured to detect a lagging signal drift of the delay signal with respect to the returned data strobe, and the tracking logic is configured to increment the delay signal.

In some aspects, the techniques described herein relate to a computing device where the tracking logic is initiated during the return data signal being communicated to the memory system to track the signal drift of the delay signal with respect to the returned data strobe, and the training logic is initiated during the return data signal being communicated from the memory system to determine the timing mask that filters the high impedance state of the returned data strobe with respect to the PHY clock.

In some aspects, the techniques described herein relate to a computing device where operational performance of memory operations between the PHY and the memory system is maintained by the tracking logic and the training logic being initiated during the return data signal communicated from the memory system.

In some aspects, the techniques described herein relate to a device physical layer (PHY) comprising a PHY clock signaled as a memory clock to dynamic random access memory (DRAM) as part of a memory read operation, a returned data strobe signaled to the device PHY as a part of a return data signal from the DRAM, the returned data strobe being out-of-phase with respect to the PHY clock, and training logic configured to determine an unknown clocking phase of the returned data strobe with respect to the PHY clock.

In some aspects, the techniques described herein relate to a device PHY where the training logic generates a pulse width filter signal to filter a high impedance state of the returned data strobe with respect to the PHY clock.

In some aspects, the techniques described herein relate to a device PHY where the training logic determines a timing mask as a delay signal to filter a high impedance state of the returned data strobe with respect to the PHY clock.

In some aspects, the techniques described herein relate to a device PHY further comprising tracking logic configured to one of detect an advancing signal drift of the delay signal with respect to the returned data strobe, and the tracking logic is responsive to decrement the delay signal, or detect a lagging signal drift of the delay signal with respect to the returned data strobe, and the tracking logic is responsive to increment the delay signal.

In some aspects, the techniques described herein relate to a method of receiving, by a dynamic random access memory (DRAM), a memory read operation that includes a memory clock which correlates to a physical layer (PHY) clock, receiving by a PHY, a return data signal from the DRAM, the return data signal including a returned data strobe that is out-of-phase with respect to the PHY clock, and determining an unknown clocking phase of the returned data strobe with respect to the PHY clock.

In some aspects, the techniques described herein relate to a method further comprising generating a pulse width filter signal to filter a high impedance state of the returned data strobe with respect to the PHY clock.

In some aspects, the techniques described herein relate to a method further comprising determining a timing mask as a delay signal to filter a high impedance state of the returned data strobe with respect to the PHY clock.

In some aspects, the techniques described herein relate to a method further comprising utilizing edge detection to detect a signal drift of the delay signal with respect to the returned data strobe.

In some aspects, the techniques described herein relate to a method further comprising detecting an advancing signal drift of the delay signal with respect to the returned data strobe, and decrementing the delay signal.

In some aspects, the techniques described herein relate to a method further comprising detecting a lagging signal drift of the delay signal with respect to the returned data strobe, and incrementing the delay signal.

FIG.1is a block diagram of a non-limiting example system100for read gate training and tracking, as described herein. The example system100is illustrative of any type of a computing system or computing device102that includes a processing unit104with a memory controller106, a physical layer (PHY)108, and a physical memory110(e.g., volatile or nonvolatile memory) that are communicatively coupled, one to another. As referred to herein, the physical memory110is a memory system, and an example of the physical memory110is dynamic random access memory (DRAM)112. The computing device102is an example of any type computing and/or electronic device, to include without limitation, a computer, computing device, server device, mobile device (e.g., a wearable, mobile phone, tablet device, laptop), processors (e.g., graphics processing units, central processing units, and accelerators), a digital signal processor, disk array controller, hard disk drive host adapter, memory card, solid-state drive, wireless communications hardware connection, Ethernet hardware connection, a switch, a bridge, network interface controller, and/or any other type apparatus configuration. Further the computing device102is configurable as part of another device that incorporates this computational functionality (e.g., a vehicle).

In this example system100, the processing unit104executes software (e.g., an operating system114, applications116, etc.) to issue memory operations to the memory controller106. The memory operations are configurable to cause storage (e.g., data programming) of data to the physical memory110as a write operation or to read data from the physical memory110as a read operation. In device implementations, the computing device102includes a memory system, such as the physical memory110(e.g., DRAM112).

The memory controller106is communicatively coupled to the PHY108and performs operations based on a reference clock signal utilized by the processing unit104to coordinate the operations. The memory controller106initiates memory operation instructions to the physical memory110via the PHY108. The processing unit104processes and initiates the memory operation instructions for any type of software, application, procedure, device function, device component, and/or system module that initiates memory operation instructions, such as read and write memory operations. Further, the physical memory110is communicatively coupled to the PHY108, which operates based on a different clock signal than the reference clock signal utilized by the processing unit104. In device implementation, the PHY clock has a higher clock rate than the reference clock signal utilized by the processing unit104.

The PHY108supports communication between the memory controller106and the physical memory110. The PHY108includes a FIFO buffer118, which is utilized as a “read buffer” to store data obtained from the physical memory110in response to a memory read operation and output the data to the memory controller106. For example, the PHY108receives a memory operation (e.g., a memory read operation) from the memory controller106, and this operation is then communicated by the PHY108to the physical memory110. This causes the physical memory110to push data subject to the memory read operation to the FIFO buffer118, and the data is then output by the FIFO buffer118to the memory controller106.

In this example system100, the PHY108includes read gate (e.g., RDGATE) logic120, which is implemented as hardware and/or software logic, such as a software implementation that initiates and controls training logic and tracking logic of the read gate logic120. Implementation examples of the read gate logic120are further shown and described with reference toFIG.2, as well as a read gate training and tracking circuit diagram shown and described with reference toFIG.6, and a circuit diagram for phase detectors logic shown and described with reference toFIG.7. In implementations, the read gate logic120is hardware logic added to the PHY108. Although illustrated as a component or module of the PHY108, the read gate logic120is implementable as an independent component or logic, separate from the PHY layer in the computing device102. In one or more implementations, the read gate logic120is a programmable state machine. Alternatively, or in addition, the read gate logic120includes independent processing, memory, and/or logic components functioning as a computing and/or electronic device integrated with the PHY108, or with the computing device102. The read gate logic120is implementable in software, in hardware, or as a combination of software and hardware components.

In device implementation, the PHY108receives a memory read operation initiated by the memory controller106. The PHY signals the memory read operation to the physical memory110as a read command and a memory clock, where the memory clock correlates to the current timing of a PHY clock. In response to the memory read operation, the PHY108receives a return data signal from the memory system, and the return data signal includes a returned data strobe. However, the PHY108receives the returned data strobe which is now out-of-phase with respect to the PHY clock (e.g., the returned data strobe may be delayed by several nano-seconds), such as due to a timing latency that has been introduced in returning the requested data and due to latency caused by the physical signal communication path.

In aspects of the techniques for read gate training and tracking, as described herein, and to solve this memory clock latency problem, the read gate logic120in the PHY108includes training logic and tracking logic utilized in conjunction to determine and compensate for unknown memory clock latencies. The training logic generates a pulse width filter signal to filter the high impedance state of the returned data strobe, which is returned from the physical memory110out-of-phase with respect to the PHY clock. This involves the training logic utilizing phase detectors with a delay line to determine a timing mask as a delay signal to filter the high impedance state of the returned data strobe with respect to the PHY clock. Additionally, the tracking logic utilizes a phase detectors circuit for signal edge detection to detect possible signal drift of the delay signal with respect to the returned data strobe and adjust the delay signal to compensate for the drift.

Various aspects of the described read gate training and tracking provides a solution for memory initialization so that the PHY108and/or the memory controller106trains incoming data signals and data strobe (DQS) timing with respect to its own internal clocking, such that PHY108can properly utilize the valid strobes to sample the data (DQs) and filter out high impedance (Hi-Z) state signals on the line. In implementations, the training logic and the tracking logic of the PHY read gate logic120are edge detection techniques that are utilized, along with cycle and sub-cycle base adjustment, to determine the assertion of DQS (data output) valid window (tDV). An intended position is at the preamble low region with a +/−2UI valid window margin (VWM) to accommodate DRAMs versus PHY timing drift due to, in particular, voltage and timing (VT) variations.

FIG.2depicts a non-limiting example of a system200with read gate logic for operation of read gate training and tracking, as described herein. This example system200further illustrates and describes aspects of the memory controller106, the PHY108, and the physical memory110(e.g., a memory system of the computing device102) as shown and described with reference toFIG.1. The PHY108in this example receives a memory read operation202from the memory controller106, and the memory controller will also receive data204from the physical memory110via the PHY108responsive to the memory read operation202.

The PHY108generates a read command206specifying the memory read operation202, indicating addresses of corresponding data that is a subject of the memory read operation. The PHY108signals the memory read operation202to the physical memory110as the read command206and a memory clock208, where the memory clock208correlates to the current timing of a PHY clock210of the PHY108. In response to the memory read operation202, the PHY108receives a return data signal212from the physical memory110, and the return data signal includes a returned data strobe214. The returned data strobe214is like a clock signal for the data lines in which each data byte is associated with a corresponding data strobe. The read command206is driven by the PHY108to the physical memory110, and the return data signal212and the associated returned data strobe214are returned from the physical memory110to the FIFO buffer118of the PHY108in response to the read command206, which is then output as the data204to the memory controller106.

In device implementations, the PHY108receives the return data signal212and the returned data strobe214. However, the PHY108receives the returned data strobe214which is now out-of-phase with respect to the PHY clock210(e.g., the returned data strobe214may be delayed by several nano-seconds), such as due to a timing latency that has been introduced in returning the requested data and due to latency caused by the physical signal communication path. In one or more implementations, the read gate logic120in the PHY108includes the training logic216and the tracking logic218that is utilized in conjunction to determine and compensate for unknown read clock latencies (e.g., the returned data strobe214that is out-of-phase with respect to the PHY clock210).

In aspects of the described techniques for read gate training and tracking, the training logic216generates a pulse width filter signal to filter a high impedance state of the returned data strobe214, which is returned from the physical memory110out-of-phase with respect to the PHY clock210. This involves the training logic216adjusting an adjustable delay line220and generating a timing mask as a delay signal to filter the high impedance state of the returned data strobe214with respect to the PHY clock210. Additionally, the tracking logic218utilizes a phase detectors circuit222for signal edge detection to detect possible signal drift of the delay signal with respect to the returned data strobe and adjusts the adjustable delay line220to compensate for the drift. This is performable over iterations to dynamically determine and compensate for unknown memory clock latencies, and is responsive to changes in device circuit operation, such as voltage and/or temperature (VT) variances that affect signal timing and overall memory system operation performance.

FIG.3depicts a non-limiting example of a circuit diagram300as related to read gate training and tracking, as described herein. This example circuit diagram300further illustrates and describes aspects of the memory controller106, the PHY108, the read gate (RDGATE) logic120, and the memory system (e.g., the DRAM112) as shown and described with reference toFIGS.1and2. The system includes a reference clock302outputting a reference clock signal to the memory controller106(e.g., directly or indirectly through use of a phase-locked loop). The memory controller106then operates and communicates with the physical layer108based on timing of the reference clock302. A memory clock304is also utilized in this example to set a clock rate for PHY108operations. As described above, the PHY108signals a memory read operation to the memory system as the read command206and the memory clock208(e.g., READ Clk at306is MEMCLK (memory clock304)), which correlates to the current timing of the PHY clock (e.g., DfiClk308) of the PHY108. In response to the memory read operation, the PHY108receives a return data signal212from the memory system, and the return data signal includes a returned data strobe214(e.g., data strobe, DQS).

FIG.4depicts a non-limiting example of a circuit timing diagram400for read gate training and tracking, as described herein. This example circuit timing diagram400illustrates operation of the training logic216to generate a pulse width filter signal to filter the high impedance state of the returned data strobe214, which is returned from the physical memory out-of-phase with respect to the PHY clock304(e.g., PCIk402). The PHY108is operated according to the DfiClk308and the PCIk402. The signals404CK (e.g., CK_t and CK_c) are communicated from the PHY108to the DRAM112. However, the phase relationship of the returned signaling data (DQ)406and data strobe (DQS)408(e.g., DQS_t and DQS_c (truth and complement differential strobe)) is no longer valid with respect to the internal PHY108clocking (e.g., DfiClk308and the PCIk402). Notably, the clocking edge of DQS at410does not align with the internal PHY clocking402, which is shown offset at 412.

The DRAM112provides the strobe pattern (DQS), which can include assumptions for this example of the dficlk to pclk frequency ratio=1:2; the tRPRE=3*tCK (000010 pattern)=3*Pclk; the tRPST=1.5*tCK (010 pattern)=1.5*Pclk; and the Read DQS Offset=1*tCK.

The training logic216filters the signal414(e.g., as a filter or mask) with the toggling edges passing through and filter out the unknown data or high impedance state to generate the filtered signal416(e.g., DQSL/U_t_gated). The signal414“@DQS RX” is a signal being filtered. The training logic216initiates the signal418(e.g., RdGateRequest) from the state machine, and the edge line420is derived from the PCIk402as the only known timing aspect (e.g., only issued on the PCIk402rising interval). At the edge line420, the pulse is configured and issued as a two-cycle pulse based on sub-granularity within the PHY clocking (e.g., one PCIk is 2UI). The signal418goes into an adjustable delay line, which produces a delay signal422(e.g., RdGateSet) and further delay version of signals424and426(e.g., RdGateSet_dlyd1 and RdGateSet_dlyd2) for edge detection and determining the assertion time of a read gate enable signal428(e.g., RdGateEn). The phase detectors of the phase detectors circuit222can then be utilized to detect the falling edge of the signal424and signal426with respect to the rising edge of the signal414, as shown by the edge line420. A first phase detector clocked by signal424detects the level low of the rising edge of the signal414, and a second phase detector clocked by signal426detects the level high of the rising edge of the signal414. The rising edge of the read gate enable signal428(RdGateEn) is determined based on the detection edge alignment. This is the training logic216determining a timing mask as the enable signal428to filter the high impedance state of the returned data strobe with respect to the PHY clock.

In further aspects of the described techniques, the enable signal428determined by the training logic is configurable with extended pulses to filter the high impedance state, and the enable signal is self-closing (e.g., by the set/resettable flop). The set/resettable flop is not clocked by the PCIk402, but rather by the filtered signal416(e.g., DQSL/U_t_gated). In implementations, this is a credit system that allocates input signal assertion to the flop (nine credit or nine cycles of input high in this example) before the signal de-assertion goes low, and self-closing is initiated.

Additionally, the tracking logic218utilizes the phase detectors circuit222for signal edge detection to detect possible signal drift of the signal414relative signal428that has been determined by the training logic216. In aspects of the described techniques, the tracking logic218is implemented to detect an advancing signal drift, and at least one of the tracking logic or the training logic then decrements the signal422, which consequently decrements the enable signal428. Similarly, the tracking logic is implemented to detect a lagging signal drift, and at least one of the tracking logic or the training logic then increments the signal419, which consequently increments the enable signal428. Accordingly, the unknown clocking phase of a returned data strobe from the physical memory is determined (e.g., by the training logic), and the determined clocking phase is maintained by monitoring and compensating for signal drift (e.g., by the tracking logic), which ensures that performance is not being degraded by the VT variation.

In further aspects of the described read gate training and tracking, the tracking logic218is initiated to track the signal drift of a returned data strobe with respect to a delay signal, and the training logic216is initiated during the return data signals that are communicated back from the memory system to determine the timing mask that filters the high impedance state of the returned data strobe. Accordingly, operational performance of the memory operations between the PHY and the physical memory is maintained by the tracking logic being initiated during a memory read operation, and by the tracking logic and the training logic being initiated during a return data signal communicated from the memory system.

FIG.5depicts a non-limiting example of the circuit timing diagram500for read gate training and tracking, as described herein. In this example, the circuit timing diagram500is the circuit timing diagram400with training implemented from the right side of the graph for the circuit timing, as indicated by the additional dashed signal pulses.

FIG.6depicts a non-limiting example of a read gate training and tracking circuit diagram600as related to read gate training and tracking, as described herein. This example circuit diagram600illustrates an implementation of the read gate (RDGATE) logic120in the PHY108. In an implementation, an additional async set/reset flop (at602) is utilized for replicating Set to Q delay (i.e., Set to Q delay on these two FFs match). The FF (at602) has the clock also coming from RdGteSet, and when set, the output is not sticky. The component604(e.g., RDGATE+PD) is representative of the phase detectors circuit222and the clock gate, which is further shown and described with reference toFIG.7.

FIG.7depicts a non-limiting example of a circuit diagram700for phase detectors logic and the clock gate as related to read gate training and tracking, as described herein. In this example circuit diagram700, the phase detectors circuit222includes a first phase detector702and at least a second phase detector704, which implement edge detection as utilized by the training logic216and the tracking logic218. In aspects of the techniques for read gate training and tracking, as described herein, the training logic216utilizes edge detection (e.g., the phase detectors circuit222) to determine the unknown clocking phase of the returned data strobe214with respect to the PHY clock. The tracking logic218utilizes the edge detection (e.g., phase detectors circuit222) to detect a signal drift of the returned data strobe with respect to the delay signal, such as an advancing signal drift of the delay signal or a lagging signal drift of the delay signal.

FIG.8is a flow diagram depicting a procedure800in an example implementation of read gate training and tracking, as described herein. The order in which the procedure is described is not intended to be construed as a limitation, and any number or combination of the described operations are performed in any order to perform the procedure, or an alternate procedure.

In the procedure800, a memory read operation is received, where the memory read operation includes a memory clock that correlates to a physical layer (PHY) clock (at802). For example, the physical memory110(e.g., a dynamic random access memory (DRAM)) receives the memory read operation202, and the memory read operation includes the memory clock208that correlates to the physical layer (PHY) clock210.

A return data signal is received by a PHY from the memory system, where the return data signal includes a returned data strobe that is out-of-phase with respect to the PHY clock (at804). For example, the PHY108receives the return data signal212from the memory system (e.g., the physical memory110), and the return data signal includes the returned data strobe214that is out-of-phase with respect to the PHY clock210.

An unknown clocking phase of the returned data strobe is determined with respect to the PHY clock (at806). For example, the training logic216determines the unknown clocking phase of the returned data strobe214with respect to the PHY clock210.

FIG.9is a flow diagram depicting a procedure900in an example implementation of read gate training and tracking, as described herein. The order in which the procedure is described is not intended to be construed as a limitation, and any number or combination of the described operations are performed in any order to perform the procedure, or an alternate procedure.

In the procedure900, a memory read operation is received, where the memory read operation includes a memory clock that correlates to a physical layer (PHY) clock (at902). For example, the physical memory110(e.g., a dynamic random access memory (DRAM)) receives the memory read operation202, and the memory read operation includes the memory clock208that correlates to the physical layer (PHY) clock210.

A return data signal is received by a PHY from the memory system, where the return data signal includes a returned data strobe that is out-of-phase with respect to the PHY clock (at904). For example, the PHY108receives the return data signal212from the memory system (e.g., the physical memory110), and the return data signal includes the returned data strobe214that is out-of-phase with respect to the PHY clock210.

A pulse width filter signal is generated to filter a high impedance state of the returned data strobe with respect to the PHY clock (at906). For example, the training logic216generates the pulse width filter signal to filter a high impedance state of the returned data strobe214with respect to the PHY clock210.

A timing mask as a delay signal is determined to filter a high impedance state of the returned data strobe with respect to the PHY clock (at908). For example, the training logic216determines the timing mask of the delay signal to filter a high impedance state of the returned data strobe214with respect to the PHY clock210.

An advancing signal drift of the delay signal with respect to the returned data strobe is detected, and the delay signal is decremented (at910). For example, the tracking logic218detects an advancing signal drift of the delay signal with respect to the returned data strobe, and the training logic216decrements the delay signal.

A lagging signal drift of the delay signal with respect to the returned data strobe is detected, and the delay signal is incremented (at912). For example, the tracking logic218detects a lagging signal drift of the delay signal with respect to the returned data strobe, and the training logic216increments the delay signal.

The various functional units illustrated in the figures and/or described herein (including, where appropriate, the processing unit104, the memory controller106, the PHY108, the physical memory110(e.g., to include the DRAM112), and the read gate logic120are implemented in any of a variety of different forms, such as in hardware circuitry, software, and/or firmware executing on a programmable processor, or any combination thereof. The procedures provided are implementable in any of a variety of devices, such as a general-purpose computer, a processor, a processor core, and/or an in-memory processor. Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a graphics processing unit (GPU), a parallel accelerated processor, a plurality of microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) circuits, any other type of integrated circuit (IC), and/or a state machine.

Although implementations of read gate training and tracking have been described in language specific to features, elements, and/or procedures, the appended claims are not necessarily limited to the specific features, elements, or procedures described. Rather, the specific features, elements, and/or procedures are disclosed as example implementations of read gate training and tracking, and other equivalent features, elements, and procedures are intended to be within the scope of the appended claims. Further, various different examples are described herein and it is to be appreciated that many variations are possible and each described example is implementable independently or in connection with one or more other described examples.