Apparatus and method for controlling delay of signal

An apparatus, includes a counter which counts a frequency of input of a first signal, a delay controller which generates a second signal by adding a delay to the first signal, the delay corresponding to the frequency, and a control circuit which halts the counter counting the frequency, when a phase difference between the first signal and the second signal is a predetermined value.

INCORPORATION BY REFERENCE

This application is based upon and claims the benefit of priority from Japanese patent application No. 2007-071707, filed on Mar. 20, 2007, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

In recent years, a general-purpose SDRAM (Synchronous Dynamic Random Access Memory) is becoming popular that has a high-speed interface such as in a DDR2-SDRAM or a DDR3-SDRAM. Since the SDRAM is a general-purpose product, the specifications are defined such that the SDRAM has a large timing margin. On the contrary, a timing margin for a memory controller LSI (Large Scale Integrated Circuit) connecting to the SDRAM is very strict. A data strobe signal DQS is outputted in the same phase as a data signal DQn from a DDR2/DDR3-SDRAM. The data strobe signal indicates a timing for transmitting the data signal. Since the phase of the DQS and the DQn are the same, it is difficult to transmit the data signal under this condition.

In the above circumstances, an interface circuit needs to control the shifting of the phase of the data strobe signal by substantially 90°. For the substantially 90°-phase shifting control, a DLL (delay locked loop) circuit is used, for example. However, since the DLL has a large scale circuit, if many DLLs are installed, it increases an area or power consumption of the circuit.

On the other hand, a delay circuit can be provided instead of the DLL. However, it is difficult to optimize a delay amount by the delay circuit. For example, even if the amount is set to a value estimated at the designing of the circuit, the optimal setting might not be achieved due to an unevenness in quality of the interface circuit, temperature change, power voltage change or the like.

Another method generates a calibration pattern for a DDR2/DDR3-SDRAM at power-on by using the delay circuit which is able to change the delay amount, and controls the circuit by pass/fail determination for the optimized delay amount. However, the method needs a circuit for the control of the calibration pattern and the pass/fail determination. Such a circuit increases an area for the delay circuit.

Some examples of this kind of related art are disclosed in Patent Documents 1 to 3.[Patent Document 1] Japanese Patent Laid-Open No. 2005-078547[Patent Document 2] Japanese Patent Laid-Open No. 2005-276396[Patent Document 3] Japanese Patent Laid-Open No. 2006-012363

SUMMARY OF THE INVENTION

According to one exemplary aspect of the present invention, an apparatus includes: a counter which counts a frequency of input of a first signal; a delay controller which generates a second signal by adding a delay to the first signal, the delay corresponding to the frequency; a control circuit which halts the counter counting the frequency, when a phase difference between the first signal and the second signal is a predetermined value.

According to another exemplary aspect of the present invention, an apparatus, comprising: means for counting a frequency of input of a first signal; means for generating a second signal by adding a delay to the first signal, the delay corresponding to said frequency; and means for halting counting said frequency, when a phase difference between the first signal and the second signal is a predetermined value.

According to another exemplary aspect of the present invention, an apparatus which controls a strobe signal for a memory device, the strobe signal indicating a timing for transmitting data, includes: a counter which counts a frequency of input of said strobe signal; a delay controller which generates a delayed strobe signal by adding a delay to the strobe signal, the delay corresponding to the frequency; a control circuit which halts the counter counting the frequency, when a phase difference between the strobe signal and the delayed strobe signal is a predetermined value.

According to yet another exemplary aspect of the present invention, a method includes: counting a frequency of an input of a first signal; generating a second signal by adding a delay to the first signal, the delay corresponding to the frequency; halting counting the frequency, when a phase difference between the first signal and the second signal is a predetermined value.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

The present invention relates to an apparatus including a delay control circuit and a memory interface control circuit using the delay control circuit, and particularly to a delay control circuit provided between a double data rate synchronous DRAM such as a DDR (double data rate) 2/DDR3-SDRAM (synchronous dynamic random access memory) and an LSI (large scale integrated circuit).

The related arts (including the inventions disclosed in the above mentioned Patent Documents 1 to 3) have a drawback that a circuit area and the power consumption of LSI for a high-end server or a super computer increase. Because the LSI for a high-end server or a super computer has a large number of memory controllers, the circuit area and the power consumption of the LSI increase. The related arts also have a problem that it is difficult to optimize a delay amount by a delay circuit.

It is an exemplary purpose of the present invention to provide an apparatus including a delay control circuit that is able to reduce the circuit area and the power consumption and optimize the delay amount.

FIG. 1is a configuration diagram of an first exemplary embodiment of the memory interface control circuit according to the present invention. As shown inFIG. 1, the first exemplary embodiment of the memory interface control circuit according to the present invention includes an I/O buffer1, an I/O buffer2, a delay control circuit8, a FIFO (first-in first-out) circuit12and a flip-flop (F/F)13.

The I/O buffer1may be a single-end input buffer for receiving a data signal DQn read out from a DDR2/DDR3-SDRAM, for example. The I/O buffer1outputs a signal DQn0. The I/O buffer2may be a differential input buffer for receiving a data strobe signal DQS read out from a DDR2/DDR3-SDRAM and the opposite phase signal, for example. The I/O buffer2outputs a data strobe signal DQS0. The data signal DQn and the data strobe signal DQS are in the same phase.

Although the I/O buffers1and2are essentially bidirectional buffers, they are described as input buffers since the present invention is an invention for an input side. As such, the I/O buffers1and2can also be configured as bidirectional buffers.

The FIFO circuit12includes a write pointer signal generating circuit9, a flip-flop (F/F) circuit10and a selector11.

The F/F circuit10receives a data signal DQn0, a strobe signal DQS1which is delayed by a certain amount, and an output signal from the write pointer signal generating circuit9. The selector11receives respective data (FIFO(0), FIFO(1), . . . , FIFO(n) (n is a positive integer)) from the flip-flop (F/F) circuits10.

Also, the selector11receives a signal corresponding to a read pointer signal via the flip-flop (F/F)13. And, the selector11outputs data (any of FIFO(0), FIFO(1), . . . , FIFO(n)) corresponding to a read pointer signal as a signal DOUTn. The read pointer signal may be a logic signal of a memory controller LSI which includes the memory interface control circuit of the present invention.

The delay control circuit8includes a delay controller3and a delay controller4, a calculation circuit7, a flip-flop (F/F)5and a counter6.

The delay amount which is added to the strobe signal increases in stages (e.g., is larger in downstream stages) corresponding to a counter value of the counter6.

The flip-flop (F/F)5receives a signal DDQS from the delay controller3, and the strobe signal DQS0as a clock signal. The flip-flop5receives the DQS0so that the phase of DQS0is reversed. The flip-flop5captures the signal DDQS according to the phase reversed DQS0. The flip-flop5outputs the captured signal as the count-up enable signal CEN to the counter6. The count-up enable signal CEN indicates whether the counter6counts the counter value or not. The flip-flop5may be able to halt the counter6count the counter value according to the count-up enable signal CEN. In other words, the flip-flop5may be a control circuit for controlling the counting operation of the counter6.

The counter6counts a frequency of input of the strobe signal DQS0. In other words, the counter6counts the number of input(s) of the strobe signal DQS0. The counter6receives the count-up enable signal CEN from the flip-flop5. The counter6counts the frequency while the count-up enable signal CEN is asserted. The counter6sends the counter value to the delay controller3as a signal CN1, and sends the counter value to the calculation circuit7as a signal CN2. The counter6stops counting the frequency after the count-up enable signal CEN is negated.

The calculation circuit7divides the counter value sent from the counter6as the signal CN1. In this embodiment, the calculation circuit7divides the counter value by 2. However, the invention is not limited to the calculation circuit7dividing the counter value by 2. The calculation circuit7sends the divided counter value to the delay controller4as a signal CN2.

Next, an example of a configuration of the delay controllers3and4will be described, with referring toFIG. 2. Referring toFIG. 2, the exemplary configuration of the delay controllers3and4include m (m is a positive integer) delay elements (21-1to21-m) and a selector22. The respective delay elements (21-1to21-m) are connected in series. The selector22receives the signal CN1or CN2, which is sent from the delay controller3or4, as a delay select signal.

As an example, it is assumed that a delay amount of each of the delay elements (21-1to21-m) is D (sec). The selector22receives the signal indicating the delay amount D from the delay element21-1, the signal indicating the delay amount 2D from the delay element21-2, . . . , the signal indicating the delay amount mD from the delay element21-m. The selector22selects the signal from any of the delay elements (21-1to21-m) according to the counter value sent from the delay controller3as a signal CN1according to the counter value or sent from the delay controller4as a signal CN2.

Next, an operation of the first exemplary embodiment of the present invention will be described. Referring toFIG. 1, the FIFO circuit12transmits the data signals DQn according to the strobe signals DQS in the order of being captured according to the read pointer signal sent from the write pointer signal generating circuit9.

However, as discussed in the above, the strobe signals DQS are outputted from the DDR2/DDR3-SDRAM in the same phase as the data signals DQn. As such, if the FIFO circuit12receives the strobe signal DQS without the delay, the timing to receive the data signals DQn is too strict. Therefore, the FIFO circuit12receives the strobe signal DQS1to which the delay is added by the delay control circuit8. The delay is substantially 90°. However, the invention is not limited to the delay being substantially 90°.

The configuration of the first exemplary embodiment has been described in detail above. However, the configurations of the write pointer signal generating circuit9, the F/F circuits10, the selector11and the flip-flop (F/F)13for receiving a read pointer signal that constitute the FIFO circuit12are well known to those skilled in the art, and do not directly relate to the feature of the present invention. Therefore, such configurations are not further described herein.

Next, an example of an operation of the delay control circuit8will be described with referring toFIG. 3which is a timing chart. InFIG. 3, a longitudinal axis indicates the level (mV) of signals DQS0, DDQS, CEN, CN1, CN2and DQS1, and a horizontal axis indicates time (sec.).

First, an outline of the operation will be described. The flip-flop5captures the strobe signal DDQS, to which the delay is added by the delay controller3, according to the strobe signal DQS0whose phase is reversed. In other words, the strobe signal DQS0is used as the clock signal of the flip-flop5. The flip-flop5captures the strobe signal DDQS at the timing of the falling edge of the strobe signal DQS0. The flip-flop5captures the strobe signal DDQS at the timing of the rising edge of the clock signal. In this embodiment, the reversed DQS0is input to the flip-flop5as the clock signal. Therefore, the timing for capturing the strobe signal DDQS is equal to the timing of the falling edge of the not-reversed DQS0. The flip-flop5outputs the count-up enable signal CEN to the counter6. Therefore, when the phase difference between the strobe signal DQS0and the strobe signal DDQS becomes substantially 180°, the level of DDQS captured by the flip-flop5is low, and then, the count-up enable signal CEN becomes low. In other words, the delay amount which is added by the delay controller3is fixed at substantially 180°, since the counter6stops to count the frequency of input of the strobe signal DQS0after the count-up enable signal CEN is negated.

A counter value CN1of the counter6is used as the delay select signal of the delay controller3. The counter value CN2which is calculated by the calculation circuit7is used as the delay select signal of the delay controller4. In this embodiment, the counter value CN2is substantially half of the counter value CN1.

As a result, a signal DQS1being output from the delay controller4is a desired signal and is a phase shifted by substantially 90° from a data strobe signal DQS0. The timing chart inFIG. 3illustrates a state after the counter6is initialized with a counter reset signal.

Next, details of the operation will be described. InFIG. 3, it is assumed that the delay amount corresponding to each of the delay elements (21-1, . . . ,21-m) of the delay controllers3and4is D0(sec.). In the initial state, when a high-level signal (100) is inputted to the delay controller3at the timing of the first rising edge (100) of the strobe signal DQS0, the signal DDQS (101) is outputted that is delayed by D0with respect to the strobe signal DQS0.

The flip-flop (F/F)5outputs a high-level signal (103) as the count-up enable signal CEN at the timing of the first falling edge (102) of the strobe signal DQS0, since a signal level (101) of the strobe signal DDQS is a high-level. The counter6starts to count according to the high-level signal (103). The high-level signal corresponds to the count-up enable signal CEN. In the initial state, a counter value of the counter6is set to “0” (see reference numeral104inFIG. 3), a counter value “0” is outputted as a signal CN1to the delay controller3.

The counter6counts by “1” at the timing of the second rising edge (104) of the strobe signal DQS0(see reference numeral105inFIG. 3), and outputs a counter value “1” as the signal CN1to the delay controller3. At that time, a delay amount of the delay controller3is (D0+D0), i.e. D1(see reference numeral106inFIG. 3). Therefore, a signal DDQS with the delay amount D1is outputted from the delay controller3.

The flip-flop (F/F)5outputs the high-level signal (103) as the count-up enable signal CEN, since the signal level (101) of the strobe signal DQS0is still a high-level at the timing of the second falling edge (107) of DQS0.

The counter6counts by “2” at the timing of the third rising edge (108) of the strobe signal DQS0(not shown inFIG. 3), and outputs the counter value “2” as the signal CN1to the delay controller3. At that time, a delay amount of the delay controller3is (D0+D0+D0), i.e. D2(not shown). Therefore, a signal DDQS with the delay amount D2is outputted from the delay controller3.

Afterward, a similar count-up operation is repeated. When the phase difference between the strobe signal DQS0and the strobe signal DDQS becomes substantially 180° (see reference numerals109and110inFIG. 3), the flip-flop5changes a level of the output signal CEN from a high-level to a low level (112) at the timing of an (n+1)-th falling edge (109) of the strobe signal DQS0since a level of the signal DDQS has varied to a low level (111).

At the above-mentioned time, a counter value of the counter6is “n”. However, since the flip-flop5has received the count-up enable signal CEN of the low level, the count-up operation is stopped.

Since the counter6stops the count-up operation at the counter value “n”, the delay amount of the delay controller3is fixed to Dn afterward even if the following strobe signals DQS0are inputted to the delay controller3.

On the other hand, since a half value of a counter value of the counter6is inputted to the delay controller4via the calculation circuit7, a counter value inputted to the delay controller4is “n/2” (see reference numeral114inFIG. 3) when the counter value of the counter6is “n” (see reference numeral113inFIG. 3). Therefore, the delay amount of a signal DQS1outputted from the delay controller4is fixed to the half value of the delay amount of the strobe signal DDQS outputted from the delay controller3, i.e. substantially 90°.

In other words, the phase difference between a strobe signal DQS0and a strobe signal DQS1is fixed to substantially 90°. This results in the phase difference between the data signal DQn and the strobe signal DQS1being fixed to substantially 90°.

In this embodiment, a half value of the counter value CN1is inputted to the delay controller4as the signal CN2. However, a divisional ratio of the counter value CN1is not limited to 1/2, it is able to be set to any value (for example, 1/3, 1/4, etc.).

As described in the above, a first benefit of the first exemplary embodiment of the present invention is that a timing margin for reading memory data is improved. That is, an optimal delay control of the strobe signal DQS (i.e. substantially 90°-phase shift) can be accomplished.

A second benefit is that a circuit size is reduced. That is, a conventional DLL circuit or memory initializing calibration control circuit, which is configured with a large amount of circuits, is avoided.

A third benefit is that power consumption is reduced. That is, a conventional DLL circuit or memory initializing calibration control circuit, which has higher power consumption because of a large amount of circuits, is avoided.

A benefit of the first exemplary embodiment is not limited to these benefits.

FIG. 4is a configuration diagram of a second exemplary embodiment of the present invention. Similar components in the drawing to those inFIG. 1are denoted by the same reference numerals and will not be further described herein.

Referring toFIG. 4, the second exemplary embodiment does not include the calculation circuit7, and the delay controller4is replaced with a delay controller4awith a delay step D0/2. In other words, the delay amount of each of the delay elements (21-1, . . . ,21-m) of the delay controller4ais half of each of the delay elements of the delay controller4of the first exemplary embodiment. The delay controllers3and4have the same delay step of D0as in the first exemplary embodiment, while the delay controller4ahas a half delay step compared to the delay controller3in the second exemplary embodiment. As such, the second exemplary embodiment dispenses with the calculation circuit7used in the first exemplary embodiment. Therefore, the delay controller4aoutputs a half delay compared to the delay controller3.

As described above, according to the second exemplary embodiment of the present invention, the calculation circuit7is unnecessary.

FIG. 5is a configuration diagram of a third exemplary embodiment of the present invention. Similar components in the drawing to those inFIG. 1are denoted by the same reference numerals and will not be further described herein.

Referring toFIG. 5, in the third exemplary embodiment, a synchronization circuit16is added to the configuration of the first exemplary embodiment (seeFIG. 1). The synchronization circuit16includes a flip-flop (F/F)14and a flip-flop (F/F)15, in which an output signal DQS02from the synchronization circuit16is outputted to the delay controller3, the flip-flop (F/F)5and the counter6.

FIG. 6is a timing chart showing an operation of the third exemplary embodiment of the delay control circuit8. InFIG. 6, a signal CLK represents a clock signal inputted to the flip-flops (F/F)13-15, and a signal DQS02represents an output signal from the flip-flop (F/F)15. The other signals are similar to those inFIG. 3.

The strobe signal DQS may be an LSI external signal transmitted from a DDR2/DDR3-SDRAM, including a problem of being sensitive to a noise and jittery compared to a clock signal CLK inside the LSI.

Therefore, when the duty ratio or a cross-point of the strobe signal DQS temporally degrades due to a noise, a rising edge of the strobe signal DDQS exceeds a falling edge of the strobe signal DQS0in the state of being smaller than the delay amount originally detected, thereby holding the counter6. Therefore, when the duty ratio or a cross-point of the strobe signal DQS temporally degrades due to a noise, the flip-flop5detects that the level of the strobe signal DDQS is low at the timing of the falling edge of the strobe signal DQS0, before the delay amount added to the DDQS reaches a preferable delay amount. Then, the counter6is held.

Therefore, the synchronization circuit16synchronizes the strobe signal DQS0with the clock signal CLK, which is an internal clock signal of the memory controller LSI and which has lower jitter than the strobe signal DQS, and the output signal DQSO2is used as a clock input of the delay controller3, the flip-flop (F/F)5and the counter6. By deleting rising and falling edges of a signal DQS affected by a noise, a stable operation is performed.

FIG. 7is a timing chart showing an exemplary operation of the synchronization circuit16when the strobe signal DQS0is affected by noise. InFIG. 7, the longitudinal axis represents the level (mV) of a signal CLK, a signal DQS0, a signal DQSO1and a signal DQSO2, while the horizontal axis represents time (sec.).

A signal CLK represents a clock inputted to the flip-flops (F/F)13-15, a signal DQS0represents the strobe signal, a signal DQSO1represents an output signal from the flip-flop (F/F)14, and a signal DQSO2represents an output signal from the flip-flop (F/F)15.

As shown inFIG. 7, when the duty ratio of a signal DQS0temporally degrades due to a noise, the flip-flops (F/F)14and15in the synchronization circuit16delete a component (edge) of a signal DQSO2corresponding to a component affected by the noise of the signal DQS0.

FIG. 5illustrates the configuration of the delay control circuit8similar to the first exemplary embodiment. However, the delay control circuit8can be configured similarly to the delay control circuit8of the second exemplary embodiment. InFIG. 5, the synchronization circuit16includes a typical configuration in that the flip-flops (F/F) are arranged in two stages in series. However, a three-stage configuration also is possible to reduce the probability of synchronization mistakes. Moreover, it is possible to configure the number of the flip-flop (F/F) stages to one stage, if the phase difference between the strobe signal DQS0and the clock signal CLK is able to be correctly estimated and a meta-stable state is not apparently achieved.

As described above, according to the third exemplary embodiment of the present invention, it is possible to prevent a change of rising timing of the signal DDQS due to the strobe signal DQS being affected by a noise and hence jittery.

While this invention has been described in conjunction with the exemplary embodiments described above, it will now be possible for those skilled in the art to put this invention into practice in various other manners.

A delay control circuit according to the present invention may be a delay control circuit for delaying and outputting binary signals by a pre-determined time, which may include: a counter for counting the binary signals; first and second delay elements to which the binary signals are inputted in which the delay amount increases in stages depending on the counter value by the counter; and a counting controller for monitoring phases of the binary signals and a signal outputted from the first delay element, and for stopping the counting by the counter when the phase difference is substantially 180 degrees, wherein the delay amount by the second delay element is a value produced by dividing the delay amount by the first delay element by an integer.

A memory interface control circuit according to the present invention may be a memory interface control circuit provided between a memory and an integrated circuit, which may include: a counter for counting binary signals read out from the memory; first and second delay element to which the binary signals are inputted in which the delay amount increases in stages depending on the counter value by the counter; and a counting controller for monitoring phases of the binary signals and a signal outputted from the first delay element, and for stopping the counting by the counter when the phase difference is substantially 180 degrees, wherein the delay amount by the second delay element is a value produced by dividing the delay amount by the first delay element by an integer.

Next, an exemplary operation of the present invention will be discussed. Referring toFIG. 1, the delay control circuit8according to the present invention includes delay controllers3and4in which the delay amount increases in stages (e.g., step-wise) depending on the counter value by the counter6. the data signal DQn and the strobe signal DQS are in the same phase.

To the delay controller3, the strobe signal DQS0is inputted. Each time the strobe signal DQS0is inputted, the counter6performs a count-up (e.g., a counter value is incremented). When the phase difference between the strobe signal DQS0and the signal DDQS outputted from the delay controller3is substantially 180°, counter6stops the count-up.

Meanwhile, the strobe signal DQS0is also inputted to the delay controller4. However, the delay controller4is configured to receive an input of a half value of the counter value by the counter6by the calculation circuit7.

A signal outputted from the delay controller4is denoted by DQS1. When the phase difference between the strobe signal DQS0and the signal DDQS is substantially 180°, the phase difference between the strobe signal DQS0and the signal DQS1is substantially 90°. The signal DQS1with the phase difference substantially 90° is inputted to the FIFO circuit12.

According to the present invention, the above configuration is included so that a circuit area and the power consumption can be reduced and the delay amount by the delay controller can be optimized.

It is noted that applicant's intent is to obtain all equivalents.