Tensile and compressive fins for vertical field effect transistors

Various embodiments disclose a method for fabricating one or more vertical fin field-effect-transistors. In one embodiment, a spacer layer is formed in contact with at least one fin structure. The at least one fin structure contacts a source/drain layer formed on a substrate and includes a channel material. A high-k dielectric layer is formed in contact with the spacer layer and the at least one fin structure. A work function metal layer is formed in contact with and conforms to the high-k dielectric layer. A metal gate layer is formed in contact with the work function metal layer. The metal gate layer includes an intrinsic stress inducing a stress on the at least one fin structure.

BACKGROUND OF THE INVENTION

The present disclosure generally relates to the field of semiconductors, and more particularly relates to vertical field-effect-transistors.

Vertical transistors are a promising option for technology scaling for 5 nm and beyond. However, in many instances such as when generating channel stress, conventional fabrication processes are not applicable to vertical transistors.

SUMMARY OF THE INVENTION

In one embodiment, a method for one or more vertical fin field-effect-transistors is disclosed. The method comprises forming a spacer layer in contact with at least one fin structure. The at least one fin structure contacts a source/drain layer formed on a substrate and comprises a channel material. A high-k dielectric layer is formed in contact with the spacer layer and the at least one fin structure. A work function metal layer is formed in contact with and conforms to the high-k dielectric layer. A metal gate layer is formed in contact with the work function metal layer. The metal gate layer comprises an intrinsic stress inducing a stress on the at least one fin structure.

In another embodiment, a vertical field-effect transistor is disclosed. The vertical field-effect transistor comprises a substrate and a source/drain layer formed on the substrate. At least one fin structure is formed in on the source/drain layer. A spacer layer is formed in contact with the least one fin structure. A high-k dielectric layer is formed in contact with the spacer layer and the at least one fin structure. A work function metal layer is formed in contact with and conforming to the high-k dielectric layer. A metal gate layer is formed in contact with the work function metal layer. The metal gate layer comprises an intrinsic stress of a first type, where the at least one fin structure comprises an induced stress of a second type.

In a further embodiment, a semiconductor structure is disclosed. The semiconductor structure comprises a plurality of vertical field-effect transistors. Each vertical field-effect transistor in the plurality of vertical field-effect transistors comprises a substrate and a source/drain layer formed on the substrate. At least one fin structure is formed in on the source/drain layer. A spacer layer is formed in contact with the least one fin structure. A high-k dielectric layer is formed in contact with the spacer layer and the at least one fin structure. A work function metal layer is formed in contact with and conforming to the high-k dielectric layer. A metal gate layer is formed in contact with the work function metal layer. The metal gate layer comprises an intrinsic stress of a first type, where the at least one fin structure comprises an induced stress of a second type.

DETAILED DESCRIPTION

It is to be understood that the present disclosure will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present disclosure.

Referring now to the drawings in which like numerals represent the same of similar elements,FIGS. 1-17illustrate various processes for fabricating tensile and compressive fins for vertical field-effect-transistors (FETs).FIG. 1shows a partially fabricated semiconductor device100comprising a substrate102, a doped source/drain layer104, and a channel layer106. The thickness of the substrate102can be, for example, from 50 microns to 1,000 microns, although lesser and greater thicknesses can be employed as well. The substrate102can be single crystalline and or a bulk substrate, a semiconductor-on-insulator (SOI) substrate, or a hybrid substrate. An insulator layer (not shown) comprising a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof can be formed on an in contact with the substrate102.

The substrate102can be appropriately doped either with p-type dopant atoms and/or with n-type dopant atoms, or the material can be substantially undoped (intrinsic). The dopant concentration of the substrate102can be from 1.0×1015/cm3to 1.0×1019/cm3and in one embodiment, is from 1.0×1016cm3to 3.0×1018/cm3, although lesser and greater dopant concentrations are applicable as well. An optional counter-doped layer (not shown) can be formed on and in contact with the substrate102(or buried insulator layer if formed). The counter-doped layer, in one embodiment, is formed by an epitaxial growth of a semiconductor material. The counter-doped layer may be implanted with dopants and annealed using, for example, rapid thermal anneal. Alternatively, the counter-doped layer can be doped in-situ during the epitaxial growth. The purpose of the counter-doped layer is to provide isolation between one transistor and the next transistor.

The source/drain layer104is formed on and in contact with the substrate102(or counter-doped layer if formed). The source/drain layer104can be, for example, an n++ doped region or a p++ doped region of the substrate102and can have a thickness in a range of, for example, about 10 nm to about 200 nm. However, other thicknesses are applicable as well. The source/drain region can be formed by epitaxial growth. In one embodiment, the channel layer106comprises a channel material. The channel material can be formed using an epitaxy process that grows a material up from the source/drain layer104. The channel material can be undoped or doped with either p-type or n-type dopants through ion implantation, plasma doping, or gas phase doping. P-type transistors are produced by doping the channel material with elements from group III of the periodic table (e.g., boron, aluminum, gallium, or indium). As an example, the dopant can be boron in a concentration ranging from 1×10E17 atoms/cm3 to 1×10E22 atoms/cm3. N-type transistors are produced by doping the channel material with elements from group V of the periodic table (e.g., phosphorus, antimony, or arsenic). As an example, the dopant can be phosphorus in a concentration ranging from 1×10E14 atoms/cm3 to 1×10E20 atoms/cm3.

FIG. 2shows the semiconductor device100after fin structures202,204,206,208have been formed in the channel layer106. The fins202,204,206,208are formed, in one embodiment, by forming an etch-stop capping layer210onto the channel material through, for example, deposition. The etch-stop capping layer210, in one embodiment, may be made of silicon-nitride although other material suitable in providing etch-stop function may be used as well. One or more fin structures202,204,206,208are subsequently formed or etched out of the channel material to be on top of and in contact with the source/drain layer104through a process involving masking, using industry-standard lithographic techniques, and directionally etching the etch-stop capping layer and underneath channel material. The directional etching process, for example a reactive-ion-etching (RIE) process, stops on the source/drain layer104. In one embodiment, the fins have a thickness of, for example, 20 nm to 100 nm. After the RIE etching process, the photo-resist mask used in the lithographic etching process can be removed.

After the fins202,204,206,208have been formed, bottom spacers302are formed in contact with each of the fins fin202,204,206,208, as shown inFIG. 3. Each bottom spacer302contacts a top surface304of the source/drain layer106and sidewalls306,308,310,312of at least one fin202,204,206,208. In one embodiment, the bottom spacers302comprise an insulating material (such as silicon oxide, silicon nitride, silicon oxynitride, or a combination of these) and can be formed using any conventional deposition process such as, for example, chemical vapor deposition (CVD) and subsequent etching techniques. The deposited spacer material is then subsequently etched to form the final spacer structures. In one embodiment, the spacers have a thickness of, for example, 3 nm to 30 nm.

The various device regions402,404within the structure100are then isolated from each other. For example,FIG. 4shows that a flowable oxide406is deposited over the structure100and then a hard mask408,410is formed over an nFinFet region402and a pFinFet region404. The hard masks408,410can be formed by, for example, depositing, and a suitable hard mask material, such as silicon nitride, onto the flowable oxide406and then patterned using standard lithography and etching techniques. Trenches502,504,506are then formed within the exposed oxide406down to the substrate102, as shown inFIG. 5. The trenches502,504,506expose a top surface508of the substrate102, sidewalls510,512of the source/drain layer106, and sidewalls514,516of a portion of the spacer layer302. Shallow trench isolation (STI) oxide is then deposited within the deep trenches regions forming STI regions602,604,606, as shown inFIG. 6. The masks408,410, flowable oxide406, and excess STI oxide are removed via chemical-mechanical polishing (CMP), selective etching, and/or the like. The resulting STI regions602,604,606comprise a top surface608that is co-planar with a top surface610,612,614,616of the fins202,204,206,208or their hard masks210(if present).

A dummy gate702is then formed over the structure100, as shown inFIG. 7. The dummy gate702is formed in contact with sidewalls of the STI regions602604,606; a top surface704of the spacers302; and sidewalls of the fins202,204,206,208. The dummy gate702also fills gate regions706to716. In one embodiment, the dummy gate702comprises polysilicon, amorphous silicon, nitride, or a combination thereof, and can be formed by CVD processes, thermal oxidation, or wet chemical oxidation. It should be noted that in some embodiments, a separate dummy gate is not required and the flowable oxide406can be maintained and acts as the dummy gate. Once the dummy gate702has been formed, exposed portions of the dummy gate702within the first region402of the structure100are the selectively removed, as shown inFIG. 8. For example, a hard mask (not shown) is formed over and in contact with the portion of the dummy gate702in the second region404using industry-standard patterning and lithographic techniques, and then dummy gate702within the first region402of the structure100is removed.

The hard mask is then removed and a high-k dielectric material is then blanket deposited over the entire structure100, for example by CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), or ALD (Atomic layer deposition). The high-k gate material forms a high-k gate dielectric layer902, as shown inFIG. 9. This layer902is formed on, in contact with, and conforming to a top surface608of one or more of the STI regions602,604,608; a top surface904of the fin hard masks210within the first region402; sidewalls of the STI regions602,604within the first region402; sidewalls of the fins202,204within the first region402; a top surface704of the spacers302within the first region402; and the portion of the dummy gate702within the second region404. In one embodiment, the high-k dielectric layer902forms a “U” shape” within the gate regions706,708,710of the first region402. The high-k gate dielectric layer902can have a thickness, for example, between 0.1 nm and 3 nm.

Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k layer902may further include dopants such as lanthanum or aluminum.

A conformal work function metal layer906is then subsequently formed over, in contact with, and conforming to the high-k gate dielectric layer902employing CVD, sputtering, or plating. The work function metal layer906includes one or more metals having a function suitable to tune the work function of nFinFETs in the nFinFET region402. Exemplary metals that can be employed in the work function metal layer include, but are not limited to titanium, titanium nitride, titanium carbide, titanium aluminum nitride, rubidium, platinum, molybdenum, cobalt, and alloys and combinations. The thickness of the first work function metal layer can be from 3 nm to 15 nm, although lesser and greater thicknesses can also be employed.

A tensile metal gate material1002is then deposited over the structure100, as shown inFIG. 10. In one embodiment, the tensile metal gate material1002comprises tungsten with an intrinsic tensile stress ranging from, for example, 0.2 GPa to 2 GPa. The tensile metal gate material1002is deposited utilizing, for example, a PVD process such as magnetron sputtering.FIG. 10shows that the tensile metal gate material1002contacts the entire top surface1004of the work function metal layer906at least within the first region402of the structure100, and is fills the gate regions706,708,710within the first region402of the structure100. The tensile metal gate material1002wraps around the fins202,204within the first region402and induces a compressive stress1006,1008along the vertical fin channel within the first region402. For example, if the tensile metal gate material1002comprises an intrinsic tensile stress 0.2 GPa to 2 GPa the vertical fin channels comprise an inducted compressive stress of 0.1 GPa to 1 GPa.

The tensile metal gate material1002, the remaining dummy gate702, the high-k dielectric layer902, and work function metal layer906are then polished using, for example, CMP. This results in the high-k dielectric layer902, work function metal layer906, and tensile metal gate material1002being co-planar with the top surface608of the STI regions602,604,606, as shown inFIG. 11. A hard mask1202is then formed over the first region402of the structure100, and the portion of the dummy gate702remaining in the second region404is removed, as shown inFIG. 12. The hard mask can be formed using industry-standard patterning and lithographic techniques. Removal of the dummy gate702exposes the gate regions712,714,716within the second region404of the structure100.

A high-k dielectric material is then blanket deposited over the entire structure100, for example by CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), or ALD (Atomic layer deposition). The high-k gate material forms a high-k gate dielectric layer1302, as shown inFIG. 13. This layer1302is formed on, in contact with, and conforming to a top surface608of one or more of the STI regions602,604,608; a top surface1304of the fin hard masks210within the second region404; sidewalls of the STI regions604,606within the second region404; sidewalls of the fins206,208within the second region404; and a top surface704of the spacers302within the second region404. In one embodiment, the high-k dielectric layer1302forms a “U” shape” within the gate regions712,714,716of the second region404. The high-k gate dielectric layer1302can have a thickness, for example, between 0.1 nm and 3 nm.

Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k layer1302may further include dopants such as lanthanum or aluminum.

A conformal work function metal layer1306is then subsequently formed over, in contact with, and conforming to the high-k gate dielectric layer1302employing CVD, sputtering, or plating. The work function metal layer1306includes one or more metals having a function suitable to tune the work function of pFinFETs in the pFinFET region404. Exemplary metals that can be employed in the work function metal layer include, but are not limited to titanium, titanium nitride, titanium carbide, titanium aluminum nitride, rubidium, platinum, molybdenum, cobalt, and alloys and combinations. The thickness of the first work function metal layer can be from 3 nm to 15 nm, although lesser and greater thicknesses can also be employed.

A compressive metal gate material1402is then deposited over the structure100and polished back, as shown inFIG. 14. In one embodiment, the compressive metal gate material1402comprises tungsten with an intrinsic compressive stress ranging from 0.2 GPa-2 GPa, and is deposited utilizing, for example, a PVD process such as magnetron sputtering.FIG. 14shows that the compressive metal gate material1402fills the gate regions712,714,716within the second region404and contacts the work function metal layer1306within the second region404. The compressive metal gate material1402wraps around the fins206,208within the second region404and induces a tensile stress1406,1408along the vertical fin channels within the second region404. For example, if the compressive metal gate material1402comprises an intrinsic compressive stress of 0.2 GPa to 2 GPa the vertical fin channels comprise an inducted tensile stress of 0.1 GPa to 1 GPa.

The compressive metal gate material1402, extraneous high-k dielectric and work function materials1302,1306are then polished using, for example, CMP. This results in the second region high-k dielectric layer1302, second region work function metal layer1304, and compressive metal gate material1402being co-planar with the top surfaces of the STI regions602,604,606; the first region high-k dielectric layer902; the first region work function metal layer906; and the tensile metal gate material1002. The hard mask1202can also be removed as part of the CMP process as well.

It should be noted that in one or more of the embodiments discussed above, the first region high-k dielectric layer902and the second region high-k dielectric layer1302comprise different materials, and the first region work function metal layer906and second region work function metal layer1306comprise different materials. However, in some embodiments the high-k dielectric layers902,1302comprise the same material and the work function metal layers906,1306comprise the same material. In these embodiments, the high-k dielectric layers902,1302and the work function metal layers906,1306are formed prior to forming the dummy gate702. For example, after the flowable oxide306is removed inFIG. 6a single continuous high-k dielectric layer can be deposited conforming to and in contact with the gate regions706to716. Then, a single continuous work function metal layer can be formed in contact with and conforming to the high-k dielectric layer. Once the high-k dielectric and work function metal layers have been deposited, the dummy gate is formed over the structure and within the gate regions of the structure. The portion of the dummy gate within the first region is removed and the tensile metal gate material is deposited within the gate regions of the first region. The remaining portion of the dummy gate within the second region is then removed and the compressive metal gate material is deposited within the gate regions of the second region.

Once the tensile metal gate material902and the compressive metal gate material1402have been deposited and polished

FIG. 15shows that the tensile and compressive metal gate materials1002,1402; high-k dielectric layers902,1302; and work function metal layers906,1306are then recessed using one or more etching processes resulting in separate tensile gate materials1002, compressive metal gate materials1402; high-k dielectric layers902,1302; and work function metal layers906,1306in each of the gate regions706to716. In one embodiment, the recess depth is, for example, 20 nm to 100 nm so that the height of the remaining tensile and compressive metal gate materials1002,1402is, for example, 10 nm to 50 nm.

FIG. 16shows that the fin hard masks210are then removed via selective etching and top spacers1602,1604are formed within each of the first and second regions402,404on and in contact with the top surface of the high-k gate dielectric layers902,1302; the top surface of the work function metal layers906,1306; the top surface of the tensile metal gate material1002; and the top surface of the compressive metal gate material1402. The top spacers1602,1604also contact a portion of the sidewalls of the fins202,204,206,208, and comprise a top surface1606that is co-planar with a top surface1608of each fin202,204,206,208.

Once the second spacers1602have been formed a doped source/drain layer1702,1704is formed within each of the first and second regions402,404of the structure100as shown in FIG.17. The source/drain layers1702,1704are formed on and in contact with the top surface1606of the top spacer1602,1604and the top surface1608of the fins202,204,206,208. Each source/drain layer1702,1704also contacts a portion of the sidewalls of the STI regions602,604,606and comprises a top surface1706that is co-planar with a top surface608of the STI regions602,604,606. The source/drain layers1702,1704can have a thickness in a range of, for example, about 10 nm to about 200 nm. However, other thicknesses are applicable as well. The source/drain layers1702,1704can be formed using an epitaxy process. For example, epitaxy that is selective with respect to the materials of the top spacers1602,1604and fins202,204,206,208is used grow material to form the source/drain layers1702,1704. The source/drain layers1702,1704comprise in-situ doping (boron, in one embodiment for pFET and phosphorus, in one embodiment, for nFET). It should be noted that, according to one embodiment, the source/drain layers1702,1704may not contain any doping. In the present embodiment, the doping can be performed using any standard approach such as ion implantation. Conventional fabrication processes can then be performed to complete the device(s).

FIG. 18is an operational flow diagram illustrating one process for fabricating one or more vertical fin field-effect-transistors. It should be noted that each of the steps shown inFIG. 18has been discussed in greater detail above with respect toFIGS. 1-17. A spacer layer302, at step1802, is formed in contact with at least one fin structure1102. The at least one fin structure1102is in contact with a source/drain layer104formed on a substrate104and comprises a channel material. A high-k dielectric layer702, at step1804, is formed in contact with the spacer layer302and the at least one fin structure1102. A work function metal layer802, at step1806, is formed in contact with and conforming to the high-k dielectric layer702. A metal gate layer1002, at step1808, is formed in contact with the work function metal layer802. The metal gate layer1002comprises an intrinsic stress that induces a stress on the at least one fin structure1102.

Although specific embodiments of the disclosure have been disclosed, those having ordinary skill in the art will understand that changes can be made to the specific embodiments without departing from the spirit and scope of the disclosure. The scope of the disclosure is not to be restricted, therefore, to the specific embodiments, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present disclosure.

It should be noted that some features of the present disclosure may be used in one embodiment thereof without use of other features of the present disclosure. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples, and exemplary embodiments of the present disclosure, and not a limitation thereof.

Also, these embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed disclosures. Moreover, some statements may apply to some inventive features but not to others.