Substrate panel structure and manufacturing process

A substrate panel structure includes a plurality of sub-panels and a dielectric portion. Each of the sub-panels includes a plurality of substrate units. The dielectric portion is disposed between the sub-panels.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a substrate panel structure and a manufacturing process, and more particularly to a substrate panel structure including a plurality of sub-panels, and a manufacturing process thereof.

2. Description of the Related Art

In an electronic device, functionality improvement and size reduction can be achieved by changing the materials thereof, or by changing the structural design thereof. When the materials of the electronic device are changed, the settings or parameters of production equipment and the manufacturing methods should be modified accordingly, which is rather complicated and expensive than simply adjusting the structural design thereof. Recently, one of the most efficient ways for improving functionality and reducing size of the electronic device is achieved by the structural design with reduced line width/line space (L/S).

SUMMARY

In some embodiments, according to an aspect, a substrate panel structure includes a plurality of sub-panels and a dielectric portion. Each of the sub-panels includes a plurality of substrate units. The dielectric portion is disposed between the sub-panels.

In some embodiments, according to another aspect, a manufacturing process includes: (a) providing a plurality of intermediate panels each including a circuit structure, wherein each of the intermediate panels includes a plurality of panel units, and the intermediate panels are separate and spaced from each other; (b) providing a dielectric material to form a plurality of first dielectric layer and a dielectric portion, wherein each of the first dielectric layers are disposed on respective one of the intermediate panels, and the dielectric portion is disposed between and connects the dielectric layers; and (c) forming a plurality of redistribution layers on the first dielectric layers, wherein each of the redistribution layer connects to respective one of the circuit structures of the intermediate panels.

DETAILED DESCRIPTION

In the semiconductor-associated industry, since the line width/line space (L/S) of the substrate panel gradually decreases, the accuracy of the substrate panel product is thus challenged. Manufacturing tolerances, including warpage due to the material differences and errors caused by the manufacturing machine, generally occur in every single layer of the substrate panel. For example, when the substrate panel includes three layers, the total tolerance would be the sum of the tolerances in the first layer, the second layer and the third layer. That is, the total tolerance of the substrate panel accumulates when the amount of layers (including protection layers) of the substrate panel increases.

It is noteworthy that in a same layer of the substrate panel, the tolerance, which may be expressed as the value of pattern shift, differs among different locations. The value of pattern shift may be defined as a distance between the actual position of the pattern and the predetermined position of the pattern. Generally, the value of pattern shift would be relatively small at a location near the center (e.g., center of mass) of the substrate panel, and would be relatively great at a location away from the center. The value of pattern shift at a particular location is proportional to the distance between the particular location and the center. Hence, the maximum value of pattern shift occurs at the edge of the substrate panel, and may increase with the size of the substrate panel. For example, in a comparative substrate panel with an area of 450 mm*450 mm and having a single circuit layer with an L/S of 2 μm/2 μm, the value of pattern shift measured at the edge of the substrate panel is at least 3 μm to 5 μm. In addition to the pattern shift amount, the warpage of the substrate panel also increases when the size of the substrate panel increases. Due to the pattern shift and warpage of the substrate panel, semiconductor dice cannot be mounted to the substrate panel accurately.

To address at least the above concerns, an embodiment of the present disclosure provides a substrate panel structure including a plurality of sub-panels. At least a portion of each of the sub-panels may be formed separately and then combined into the substrate panel structure. For example, one or more circuits of the sub-panels may be formed separately under a relative small scale, thus a maximum value of pattern shift of the substrate panel structure can be reduced.

FIG. 1illustrates a top view of an example of a substrate panel structure1′ according to some embodiments of the present disclosure. The substrate panel structure1′ includes a plurality of sub-panels2′ and a dielectric portion14′ disposed between the sub-panels2′. Each of the sub-panels2′ includes a plurality of substrate units20′. The sub-panels2′ are arranged in an “m*n” manner, and “m” and “n” are integers equal to or greater than two. For example, as shown inFIG. 1, the substrate panel structure1′ includes 2*2 sub-panels2′. However, an amount of the sub-panels2′ in the substrate panel1′ may be greater than 2*2, and the “m” and “n” may not equal to each other. Similarly, the substrate units20′ of the sub-panels2′ may be arranged in an “o*p” manner, with “o” and “p” being integers, and at least one of “o” and “p” being greater than one. For example, as shown inFIG. 1, each of the sub-panels2′ includes 5*5 substrate units20′. In some embodiments, a dimension of each of the sub-panels2′ is less than 500 mm*500 mm. That is, a length of each side edge of the sub-panel2′ may be shorter than 500 mm, such as shorter than 400 mm, shorter than 300 mm or shorter than 200 mm. In some embodiments, all the sub-panels2′ are known good sub-panels.

FIG. 2illustrates a top view of an example of a substrate panel structure1according to some embodiments of the present disclosure.FIG. 3illustrates a cross-sectional view taken along line3-3of the substrate panel structure1shown inFIG. 2. Similar to the substrate panel structure1′ shown inFIG. 1, the substrate panel structure1also includes a plurality of sub-panels2and a dielectric portion14. The dielectric portion14is disposed between the sub-panels2and may surround the sub-panels2. Each of the sub-panels2includes a plurality of substrate units20. Each of the substrate units20corresponds to a package unit, such as the package unit7shown inFIG. 12. However, each of the sub-panels2shown inFIGS. 2 and 3includes 2*2 substrate units20instead of the5*5substrate units20′ shown inFIG. 1for simple and clear explanation.

The sub-panels2may include a first sub-panel2aand a second sub-panel2b, and a gap “g” is formed between adjacent two of the sub-panels2(e.g., the first sub-panel2aand the second sub-panel2b). As can be seen inFIG. 2, the two adjacent sub-panels2(e.g., the first sub-panel2aand the second sub-panel2b) may not be aligned with each other, or may not be parallel to each other. Hence, the gap “g” therebetween may have a non-consistent width. However, in other embodiments, adjacent two of the sub-panels2may be substantially parallel to each other, and the gap “g” therebetween may have a consistent width.

The substrate units20in each of the sub-panels2are close to each other. For example, adjacent two of the substrate units20in the first sub-panel2amay physically connect with each other, or may be spaced by a cutting line or a sawing street. That is, the substrate units20in the first sub-panel2amay be defined by the cutting lines or the sawing streets. After a plurality of semiconductor dice are mounted to each of the sub-panels2and/or an encapsulant is formed on each of the sub-panels2, these substrate units20may be separated by a singulating process along the cutting lines or the saw streets to form a plurality of package units (e.g., the package unit7shown inFIG. 12). As shown inFIGS. 2 and 3, since adjacent two of the sub-panels2(e.g., the first sub-panel2aand the second sub-panel2b) are spaced by the gap “g”, a pitch P1between adjacent two of the substrate units20in the first sub-panel2ais less than a pitch P2between the closest one of the substrate units20of the first sub-panel2aand one of the substrate units20of the second sub-panel2b. The “pitch” between two substrate units20may refer to a distance between a center of one of the substrate units20and a center of the other one of the substrate units20.

Referring toFIG. 3, each of the sub-panels2has a first surface21, a second surface22opposite to the first surface21, and a lateral surface23extending between the first surface21and the second surface22. In some embodiments, at least a portion of the lateral surface23is an imaginary surface or an imaginary plane. The lateral surface23may be a cutting line or a saw street for separating the sub-panels2from the substrate panel structure1. As shown inFIG. 3, the first surface21is an upper surface, and the second surface22is a lower surface. Each of the sub-panels2includes a first dielectric layer3, a redistribution layer4, a protection layer25, at least one solder connecter26, a circuit structure5and a second dielectric layer6. Similarly, each of the substrate units20may include at least a portion of the first dielectric layer3, at least a portion of the redistribution layer4, at least a portion of the protection layer25, at least one solder connecter26, at least a portion of the circuit structure5and at least a portion of the second dielectric layer6. For illustration purposes, elements of the substrate units20are not shown inFIG. 2.

FIG. 3shows the first sub-panel2aand the second sub-panel2bwhich are substantially the same with each other. However, the first sub-panel2aand the second sub-panel2bmay be different from each other. For example, the components, arrangements, materials, size, and position relative to the dielectric portion14of the first sub-panel2amay differ from those of the second sub-panel2b.

The first dielectric layer3includes a first surface31and a second surface32opposite to the first surface31. As shown inFIG. 3, the first surface31is an upper surface, and the second surface32is a lower surface. The first dielectric layer3may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the first dielectric layer3may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. The first dielectric layer3defines at least one through hole30extending through the first dielectric layer3and between the first surface31and the second surface32. In some embodiments, a thickness of the first dielectric layer3may be about 3 μm to about 20 μm, preferably about 3 μm to about 15 μm. The material of the first dielectric layer3in the first sub-panel2amay be substantially the same as the material of the dielectric layer3in the second sub-panel2b. However, a thickness of the first dielectric layer3in the first sub-panel2amay be substantially the same as or slightly different from a thickness of the dielectric layer3in the second sub-panel2b.

The redistribution layer4is disposed on the first dielectric layer3. The redistribution layer4may be disposed on the second surface32of the first dielectric layer3and in the through hole30. The redistribution layer4may include a seed layer41disposed on the first dielectric layer3, and a conductive layer42disposed on the seed layer41. A material of the seed layer41may be, for example, titanium or copper. In some embodiments, the seed layer41may include a titanium layer and a copper layer. A material of the conductive layer42may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer41may be omitted, and the conductive layer42may directly contact the first dielectric layer3. The redistribution layer4may include at least one conductive via43disposed in the through hole30of the first dielectric layer3, and at least one conductive pad44disposed on the second surface32of the first dielectric layer3. In some embodiments, the redistribution layer4may further include at least one trace (not shown). In some embodiments, a line width/line space (L/S) of the redistribution layer4may be equal to or greater than 10 μm/10 μm. The materials and L/S of the redistribution layer4in the first sub-panel2amay be substantially the same as the materials and L/S of the redistribution layer4in the second sub-panel2b.

The protection layer25is disposed on the second surface32of the first dielectric layer3and on the redistribution layer4. The protection layer25has a first surface251and a second surface252opposite to the first surface251. The first surface251contacts the lower surface (e.g., the second surface32) of the first dielectric layer3. The second surface252may be a portion of the lower surface (e.g., the second surface22) of each of the sub-panels2. In some embodiments, the protection layer25further includes a portion254extending into the gap “g” between the sub-panels2and disposed on the dielectric portion14. The protection layer25may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators, or a solder resist layer. The protection layer25covers the redistribution layer4, and at least a portion of the redistribution layer4, such as the conductive pad44, is exposed from the protection layer25for external connection. In some embodiments, a thickness of the protection layer25may be about 10 μm to about 30 μm. The material of the protection layer25in the first sub-panel2amay be substantially the same as the material of the protection layer25in the second sub-panel2b. However, a thickness of the protection layer25in the first sub-panel2amay be substantially the same as or slightly different from a thickness of the protection layer25in the second sub-panel2b.

The solder connector26is disposed on the exposed portion of the redistribution layer4, such as the conductive pad44of the redistribution layer4. A material of the solder connector26may be a conductive metal, such as tin, or another metal or combination of metals.

The circuit structure5is disposed adjacent to the first surface31of the first dielectric layer3. For example, as shown inFIG. 3, the circuit structure5is embedded in the first dielectric layer3and exposed from the first surface31of the first dielectric layer3. The circuit structure5may include a seed layer51and a conductive layer52. The seed layer51is exposed from the first surface31of the first dielectric layer3. A material of the seed layer51may be, for example, titanium or copper. In some embodiments, the seed layer51may include a titanium layer and a copper layer. The conductive layer52covers the seed layer51. A material of the conductive layer52may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer51may be omitted, and the conductive layer52may be exposed from the first surface31of the first dielectric layer3. The circuit structure5includes at least one conductive pad53, at least one conductive via54and at least one trace55. The conductive pad53, the conductive via54and the trace55may be formed integrally and concurrently. In some embodiments, the conductive via54is disposed on and formed integrally with the conductive pad53. The conductive via54protrudes from the first dielectric layer3. The conductive via54may be adapted for connection with a semiconductor die (e.g., as shown inFIG. 12). The conductive via54has an upper surface541, which is at a level higher than the upper surface (e.g., the first surface31) of the first dielectric layer3. The trace55has an upper surface551, which is substantially coplanar with the upper surface31of the first dielectric layer3. In some embodiments, an L/S of the circuit structure5may be equal to or less than 2 μm/2 μm. The redistribution layer4is electrically connected to the circuit structure5. For example, a portion of the redistribution layer4(e.g., the conductive via43) is embedded in the first dielectric layer3, and contacts and electrically connects the circuit structure5. For example, the conductive via43extends through the first dielectric layer3to contact the circuit structure5. The materials and L/S of the circuit structure5in the first sub-panel2amay be the same as or different from the materials and L/S of the circuit structure5of in the second sub-panel2b.

The second dielectric layer6is disposed on the first dielectric layer3. The second dielectric layer6has a first surface61, a second surface62opposite to the first surface61, and a lateral surface63extending between the first surface61and the second surface62. As shown inFIG. 3, the first surface61is an upper surface, and the second surface62is a lower surface. The first surface61of the dielectric layer6is a portion of the upper surface (e.g., the first surface21) of the sub-panel2. The lateral surface63is a portion of the lateral surface23of the sub-panel2. The second dielectric layer6may be disposed on the first surface31of the first dielectric layer3and on the circuit structure5. The lower surface (e.g., the second surface62) of the second dielectric layer6may contact the upper surface (e.g., the first surface31) of the first dielectric layer3. As shown inFIG. 3, the seed layer51of the circuit structure5is located between the conductive layer52of the circuit structure5and the second dielectric layer6. The upper surface551of the trace55of the circuit structure5contacts the lower surface (e.g., the second surface62) of the second dielectric layer6. The second dielectric layer6may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the second dielectric layer6may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. The material of the second dielectric layer6may be the same as or different from the material of the first dielectric layer3. A thickness of the second dielectric layer6may be 5 μm to 20 μm. The material and thickness of the second dielectric layer6in the first sub-panel2amay be the same as or different from those of the second sub-panel2b.

The conductive via54of the circuit structure5may be embedded in and exposed from the second dielectric layer6. For example, the second dielectric layer6may define at least one through hole60extending through the second dielectric layer6and between the first surface61and the second surface62. The conductive via54of the circuit structure5may be disposed in the through hole60of the second dielectric layer6and exposed from the first surface61of the second dielectric layer6. The seed layer51of the conductive via54of the circuits structure5is disposed in the through hole60of the second dielectric layer6and between the conductive layer52and the second dielectric layer6. In some embodiments, a portion of the seed layer51of the conductive via54of the circuit structure5adjacent to the first surface61of the second dielectric layer6is omitted, and the conductive layer52of the conductive via54of the circuit structure5is exposed from the first surface61of the second dielectric layer6. Accordingly, the upper surface541of the conductive via54is recessed from the upper surface (e.g., the first surface61) of the second dielectric layer6. As shown inFIG. 3, the second dielectric layers6of the sub-panels2are not connected with each other, and the materials and structures of the second dielectric layers6may be different among the sub-panels2.

The dielectric portion14is disposed between the sub-panels2. For example, the dielectric portion14is filled in the gap “g” formed between adjacent two of the sub-panels2(e.g., the first sub-panel2aand the second sub-panel2b). The dielectric portion14has an upper surface141, a lower surface142and at least one lateral surface143extending between the upper surface141and the lower surface142. At least a portion of the lateral surface143is an imaginary surface or an imaginary plane. As shown inFIG. 3, the dielectric portion14has at least one lateral surface143corresponding to each of the sub-panels2.

In some embodiments, the dielectric portion14covers and contacts at least a portion of a lateral surface23of each of the sub-panels2. For example, the lateral surface143of the dielectric portion14contacts and is substantially coplanar with the lateral surface63of the second dielectric layer6of each of the sub-panels2. In some embodiments, the first dielectric layer3of each of the sub-panels2and the dielectric portion14are formed integrally and concurrently. For example, the dielectric layers3of the sub-panels2and the dielectric portion14may be integrally and concurrently formed as a monolithic structure. That is, there is no boundary or interface between the dielectric portion14and the first dielectric layers3of the sub-panels2.

In some embodiments, as shown inFIG. 3, the upper surface141of the dielectric portion14is at a level higher than the upper surface (e.g., the first surface21) of each of the sub-panels2and/or the first surface61of the second dielectric layer6. Hence, the dielectric portion14has an inner surface145to define a cavity140above the upper surface (e.g., the first surface21) of each of the sub-panels2. The cavity140completely exposes the second dielectric layer6, such as the first surface61of the second dielectric layer6, of each of the sub-panels2. The upper surface541of the conductive via54is exposed in the cavity140. The inner surface145may be a portion of the lateral surface143of the dielectric portion14. The lateral surface63of the second dielectric layer6is substantially coplanar with the inner surface145of the cavity140.

The dielectric portion14may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the dielectric portion14may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. The material of the dielectric portion14may be the same as the material of the first dielectric layer3of each of the sub-panels2. In some embodiments, a thickness of the dielectric portion14may be about 100 μm to about 300 As shown inFIG. 3, the thickness of the first dielectric layer3is less than the thickness of the dielectric portion14. However, in other embodiments, the thickness of the first dielectric layer3may be substantially equal to or greater than the thickness of the dielectric portion14.

In the substrate panel structure1, layers with smaller L/S (e.g., the circuit structure5and the second dielectric layer6) are separately formed in each of the sub-panels2, while layers with larger L/S (e.g., the redistribution layer4and the first dielectric layer3) are concurrently formed across the entire substrate panel structure1. The layers with smaller L/S are much more sensitive to pattern shift than the layers with larger L/S. Since the layers with smaller L/S are formed separately under a smaller scale (e.g., each of the sub-panels2has a smaller size or area), a maximum value of pattern shift, such as of each of the circuit structures5, is rather small. The effect of pattern shift on the layers with smaller L/S can thus be reduced. Besides, warpage of the second dielectric layer6is also reduced. On the other hand, the layers with larger L/S, which are more tolerant to pattern shift, can be formed concurrently under a larger scale to reduce time and cost of production. The larger pattern shift of the layers with larger L/S does not affect the layers with smaller L/S. Hence, the substrate panel structure1, formed from the sub-panels2, has the maximum value of pattern shift as same as the sub-panels2.

For example, in the sub-panel2having an area of 300 mm*300 mm, the value of pattern shift measured at the edge thereof may be about 1 μm to 2 μm. The substrate panel structure1, including at least 2*2 of such sub-panels2, is thus provided with a maximum value of pattern shift of about 1 μm to 2 μm. That is, the values of pattern shift of the sub-panels2will not accumulate. Thus, even though the substrate panel structure1according to the present disclosure has an area greater than 600 mm*600 mm, the maximum value of pattern shift thereof (e.g., about 1 μm to 2 μm) is significantly less than that of a comparative substrate panel with an area of 450 mm*450 mm (e.g., at least 3 μm to 5 μm). Since the maximum value of pattern shift and warpage are both reduced, semiconductor dice can be mounted to predetermined positions on the sub-panels2(e.g., on the circuit structures5) accurately.

FIG. 4illustrates a cross-sectional view of an example of a substrate panel structure1aaccording to some embodiments of the present disclosure. The substrate panel structure1aalso includes a plurality of sub-panels2(including a first sub-panel2aand a second sub-panel2b), and a dielectric portion14disposed between the sub-panels2. Each of the sub-panels2includes a plurality of substrate units20. Components and arrangements of the substrate panel structure1a, including the sub-panels2and the substrate units20, are similar to the substrate panel structure1shown inFIGS. 2 and 3, except for the dielectric portion14, as describe below.

As shown inFIG. 4, the upper surface141of the dielectric portion14is at a level lower than the upper surface (e.g., the first surface21) of each of the sub-panels2. The cavity140of the substrate panel structure1shown inFIGS. 2 and 3is omitted. The upper surface141of the dielectric portion14is substantially coplanar with the upper surface (e.g., the first surface31) of the first dielectric layer3and/or the lower surface (e.g., the second surface62) of the second dielectric layer6of each of the sub-panels2. The lateral surface63of the second dielectric layer6is not covered by the dielectric portion14, thus is exposed and is a free surface.

FIG. 5illustrates a cross-sectional view of an example of a substrate panel structure1baccording to some embodiments of the present disclosure. The substrate panel structure1bincludes a plurality of sub-panels2c, and a dielectric portion14disposed between the sub-panels2c. Each of the sub-panels2cincludes a plurality of substrate units20c. The substrate panel structure1bis similar to the substrate panel structure1shown inFIGS. 2 and 3, except for the follows.

As shown inFIG. 5, the second dielectric layer6shown inFIGS. 2 and 3is omitted. Besides, the conductive via54of the circuit structure5is also omitted. Accordingly, a first surface57of the circuit structure5, which is an upper surface as shown inFIG. 5, is completely exposed, such as exposed in the cavity140defined by the dielectric portion14. The entire upper surface (e.g., first surface57) of the circuit structure5may be substantially coplanar with the upper surface (e.g., the first surface31) of the first dielectric layer3. Accordingly, the conductive pad53and the trace55are exposed in the cavity140. The conductive pad53may be adapted for connection with a semiconductor die.FIG. 5shows the circuit structure5with one layer (e.g., a conductive layer) without seed layer. However, the circuit structure5may also include one or more than one seed layers.

FIG. 6illustrates a cross-sectional view of an example of a substrate panel structure1caccording to some embodiments of the present disclosure. The substrate panel structure1calso includes a plurality of sub-panels2c, and a dielectric portion14disposed between the sub-panels2c. Each of the sub-panels2cincludes a plurality of substrate units20c. Components and arrangements of the substrate panel structure1c, including the sub-panels2cand the substrate units20c, are similar to the substrate panel structure1bshown inFIG. 5, except for the dielectric portion14as describe below.

As shown inFIG. 6, the upper surface141of the dielectric portion14is substantially coplanar with the upper surface (e.g., the first surface21) of each of the sub-panels2c. The cavity140of the substrate panel structure1bshown inFIG. 5is omitted. The upper surface141of the dielectric portion14is substantially coplanar with the upper surface (e.g., the first surface31) of the first dielectric layer3and/or the upper surface (e.g., first surface57) of the circuit structure5of each of the sub-panels2c.

FIG. 7illustrates a cross-sectional view of an example of a substrate panel structure1daccording to some embodiments of the present disclosure. The substrate panel structure1dalso includes a plurality of sub-panels2d, and a dielectric portion14disposed between the sub-panels2d. Each of the sub-panels2dincludes a plurality of substrate units20d. The substrate panel structure1dis similar to the substrate panel structure1cshown inFIG. 6, except for the follows.

As shown inFIG. 7, the circuit structure5is not embedded in the first dielectric layer3. The circuit structure5protrudes from the first dielectric layer3. For example, the circuit structure5is disposed on the upper surface (e.g., the first surface31) of the first dielectric layer3. The first surface57, which is a lower surface as shown inFIG. 7, contacts and is substantially coplanar with the upper surface (e.g., the first surface31) of the first dielectric layer3.

FIG. 8illustrates a cross-sectional view of an example of a substrate panel structure1eaccording to some embodiments of the present disclosure. The substrate panel structure1ealso includes a plurality of sub-panels2e, and a dielectric portion14disposed between the sub-panels2e. Each of the sub-panels2eincludes a plurality of substrate units20e. The substrate panel structure1eis similar to the substrate panel structure1shown inFIGS. 2 and 3, but further includes an additional dielectric layer3eand an additional redistribution layer4e.

Structures, configurations, materials and relative positions of the first dielectric layers3, the redistribution layers4, the circuit structures5, the second dielectric layers6and the dielectric portion14in the substrate panel structure1eshown inFIG. 8are similar to those of the first dielectric layers3, the redistribution layers4, the circuit structures5, the second dielectric layers6and the dielectric portion14in the substrate panel structure1shown inFIGS. 2 and 3, thus are not described redundantly.

The additional dielectric layer3eis disposed on the first dielectric layer3and covers the redistribution layer4. The additional layer3emay further include a portion34eextending into the gap “g” between the sub-panels2eand disposed on the dielectric portion14. The additional dielectric layer3emay be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the additional dielectric layer3emay include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. The material of the additional dielectric layer3emay be the same as or different from the material of the first dielectric layer3. The material of the additional dielectric layers3ein each of the sub-panels2emay be the same, and may be formed integrally and concurrently. The additional dielectric portion3eof the sub-panels2emay be connected with each other through the extending portion34e. The additional dielectric layer3edefines at least one through hole30eto expose at least a portion of the redistribution layer4, such as the conductive pad44of the redistribution layer4.

The additional redistribution layer4eis disposed on the additional dielectric layer3e, and in the through hole30e. The additional redistribution layer4emay also include a seed layer41edisposed on the additional dielectric layer3e, and a conductive layer42edisposed on the seed layer41e. Materials of the seed layer41eand the conductive layer42eof the additional redistribution layer4emay be the same as the materials of the seed layer41and the conductive layer42of the redistribution layer4. The additional redistribution layer4emay include at least one conductive via43edisposed in the through hole30eof the additional dielectric layer3e, and at least one conductive pad44edisposed on the additional dielectric layer3e. The additional redistribution layer4eis electrically connected to the redistribution layer4, such as through the conductive via43e. In some embodiments, the additional redistribution layer4emay further include at least one trace (not shown). An L/S of the additional redistribution layer4emay be substantially equal to or greater than 10 μm/10 μm. The L/S of the additional redistribution layer4emay be substantially the same as the L/S of the redistribution layer4. The material and L/S of the additional redistribution layer4ein each of the sub-panels2emay be the same, and may be formed integrally and concurrently.

The protection layer25is disposed on the additional dielectric layer3eand the additional redistribution layer4e. The protection layer25has a first surface251and a second surface252opposite to the first surface251. The first surface251contacts the additional dielectric layer3e. The second surface252may be a portion of the lower surface (e.g., the second surface22) of each of the sub-panels2e. The second surface252may be a portion of the lower surface (e.g., the second surface22) of each of the sub-panels2e. In some embodiments, the protection layer25further includes a portion254extending into a gap “g” defined between adjacent two of the sub-panels2eand disposed on the extending portion34eof the additional dielectric layer3e. The protection layer25may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators, or a solder resist layer. The protection layer25covers the additional redistribution layer4e. At least a portion of the additional redistribution layer4e, such as the conductive pad44e, is exposed from the protection layer25for external connection. The solder connector26is disposed on the exposed portion of the additional redistribution layer4e, such as the conductive pad44eof the additional redistribution layer4e. In some embodiments, the panel structure1emay include more than one of the additional dielectric layer3eand more than one of the additional redistribution layer4e.

FIG. 9illustrates a cross-sectional view of an example of a substrate panel structure1faccording to some embodiments of the present disclosure. The substrate panel structure1falso includes a plurality of sub-panels2f, and a dielectric portion14disposed between the sub-panels2f. Each of the sub-panels2fincludes a plurality of substrate units20f.

Referring toFIG. 9, each of the sub-panels2fhas a first surface21, a second surface22opposite to the first surface21, and a lateral surface23extending between the first surface21and the second surface22. In some embodiments, at least a portion of the lateral surface23is an imaginary surface or an imaginary plane. As shown inFIG. 9, the first surface21is an upper surface, and the second surface22is a lower surface. Each of the sub-panels2fincludes a first dielectric layer3, a circuit layer27, a redistribution layer4, a second dielectric layer6, a circuit structure5, a protection layer25, and at least one solder connecter26. Similarly, each of the substrate units20fmay include at least a portion of the first dielectric layer3, at least a portion of the circuit layer27, at least a portion of the redistribution layer4, at least a portion of the second dielectric layer6, at least a portion of the circuit structure5, at least a portion of the protection layer25, and at least one solder connecter26.

The first dielectric layer3includes a first surface31and a second surface32opposite to the first surface31. As shown inFIG. 9, the first surface31is an upper surface, and the second surface32is a lower surface. The first surface31of the first dielectric layer3may be a portion of the upper surface (e.g., the first surface21) of each of the sub-panels2f. The first dielectric layer3may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the first dielectric layer3may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators.

The circuit layer27is disposed adjacent to the second surface32of the first dielectric layer3. The circuit layer27may be embedded in the first dielectric layer3and exposed from the second surface32of the first dielectric layer3. The circuit layer27may include a seed layer271and a conductive layer272. The seed layer271is disposed between the conductive layer272and the first dielectric layer3. A material of the seed layer271may be, for example, titanium or copper. In some embodiments, the seed layer271may include a titanium layer and a copper layer. A material of the conductive layer272may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer271may be omitted, and the conductive layer272may directly contact the first dielectric layer3. The circuit layer27may include at least one conductive pad274, and may further include at least one trace (not shown). The circuit layer27, including the conductive pad274and the trace, may be formed by patterning a metal layer.

The first dielectric layer3may further define a through hole30exposing a portion of the circuit layer27, such as the conductive pad274of the circuit layer27. The redistribution layer4is disposed on the first dielectric layer3and in the through hole30. The redistribution layer4may include a seed layer41and a conductive layer42. The seed layer41is disposed between the conductive layer42and the first dielectric layer3. A material of the seed layer41may be, for example, titanium or copper. In some embodiments, the seed layer41may include a titanium layer and a copper layer. A material of the conductive layer42may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer41may be omitted, and the conductive layer42may directly contact the first dielectric layer3. The redistribution layer4may include at least one conductive via43, and may further include at least one trace (not shown). The conductive via43is disposed in the through hole30, and contacts and electrically connects the circuit layer27. A solder material77is disposed on the conductive via43of the redistribution layer4for external connection. The solder material77may be made of tin, or another metal or combination of metals.

The second dielectric layer6is disposed on the second surface32of the first dielectric layer3and covers the circuit layer27. The second dielectric layer6has a first surface61, a second surface62opposite to the first surface61and a lateral surface63extending between the first surface61and the second surface62. As shown inFIG. 9, the first surface61is an upper surface, and the second surface62is a lower surface. The first surface61of the second dielectric layer6contacts the first dielectric layer3and the circuit layer27. The lateral surface63of the second dielectric layer6is a portion of the lateral surface23of each of the sub-panels2f. The second dielectric layer6may define at least one through hole60to expose a portion of the circuit layer27, such as the conductive pad274of the circuit layer27. The second dielectric layer6may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the second dielectric layer6may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators.

The circuit structure5is disposed on the second surface62of the second dielectric layer6and in the through hole60of the second dielectric layer6. The circuit structure5may include a seed layer51and a conductive layer52. The seed layer51is disposed on the second dielectric layer6, in the through hole60of the second dielectric layer6and on the redistribution layer4. The conductive layer52is disposed on the seed layer51. A material of the seed layer51may be, for example, titanium or copper. In some embodiments, the seed layer51may include a titanium layer and a copper layer. A material of the conductive layer52may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer51may be omitted, and the conductive layer52may directly contact the second dielectric layer6and/or the redistribution layer4. The circuit structure5includes at least one conductive pad53, at least one conductive via54and at least one trace55. The conductive pad53, the conductive via54and the trace55may be formed integrally and concurrently. In some embodiments, the conductive via54is disposed on and formed integrally with the conductive pad53. The conductive via54is disposed in the through hole60of the second dielectric layer6to contact and electrically connect the circuit layer27embedded in the first dielectric layer3. Accordingly, the redistribution layer4is electrically connected to the circuit structure5through the circuit layers27. That is, each of the redistribution layers4is electrically connected to the respective one of the circuit structures5through respective one of the circuit layers27. In some embodiments, an L/S of the circuit structure5may be equal to or less than 2 μm/2 μm.

The protection layer25is disposed on the second dielectric layer6and covers the circuit structure5. That is, the second dielectric layer6is sandwiched between the first dielectric layer3and the protection layer25. The protection layer25has a first surface251and a second surface252opposite to the first surface251. The first surface251contacts the lower surface (e.g., the second surface62) of the second dielectric layer6. The second surface252may be a portion of the lower surface (e.g., the second surface22) of each of the sub-panels2f. In some embodiments, the protection layer25further includes a portion254extending into the gap “g” between the sub-panels2fand disposed on the dielectric portion14. The extending portion254of the protection layer25may contact a portion of the lateral surface63of the second dielectric layer6. The protection layer25exposes a portion of the circuit structure5, such as the conductive pad53of the circuit structure5, for external connection. The protection layer25may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators, or a solder resist layer.

The solder connector26is disposed on the exposed portion of the circuit structure5, such as the conductive pad53of the circuit structure5. A material of the solder connector26may be a conductive metal, such as tin, or another metal or combination of metals.

The dielectric portion14is disposed between the sub-panels2fFor example, the dielectric portion14is disposed in the gap “g” between the sub-panels2fThe dielectric portion14has an upper surface141, a lower surface142and at least one lateral surface143extending between the upper surface141and the lower surface142. At least a portion of the lateral surface143is an imaginary surface or an imaginary plane. As shown inFIG. 9, the upper surface141of the dielectric portion14is substantially coplanar with the upper surface (e.g., the first surface21) of each of the sub-panels2fand/or the upper surface (e.g., the first surface31) of the first dielectric layer3. The lower surface142of the dielectric portion14is at a level lower than the lower surface (e.g., the second surface32) of the first dielectric layer37and the upper surface (e.g., the first surface61) of the second dielectric layer6, while higher than the lower surface (e.g., the second surface62) of the second dielectric layer6. However, in other embodiments, The lower surface142of the dielectric portion14may be substantially coplanar with the lower surface (e.g., the second surface32) of the first dielectric layer3and the upper surface (e.g., the first surface61) of the second dielectric layer6, or may be substantially coplanar with the lower surface (e.g., the second surface62) of the second dielectric layer6.

In some embodiments, the dielectric portion14covers and contacts at least a portion of a lateral surface23of each of the sub-panels2f. For example, the lateral surface143of the dielectric portion14contacts and is substantially coplanar with the lateral surface63of the second dielectric layer6of each of the sub-panels2fIn some embodiments, the first dielectric layer3of each of the sub-panels2fis formed integrally and concurrently with the dielectric portion14. For example, the dielectric layers3of the sub-panels2fand the dielectric portion14may be integrally and concurrently formed as a monolithic structure. That is, there is no boundary or interface between the dielectric portion14and the first dielectric layers3of the sub-panels2f.

The dielectric portion14may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the dielectric portion14may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. The material of the dielectric portion14may be the same as the material of the first dielectric layer3of each of the sub-panels2f. As shown inFIG. 9, a thickness of the first dielectric layer3is less than a thickness of the dielectric portion14. However, in other embodiments, the thickness of the first dielectric layer3may be substantially the same as or greater than a thickness of the dielectric portion14.

FIG. 10illustrates a cross-sectional view of an example of a substrate panel structure1gaccording to some embodiments of the present disclosure. The substrate panel structure1galso includes a plurality of sub-panels2g, and a dielectric portion14disposed between the sub-panels2g. Each of the sub-panels2gincludes a plurality of substrate units20g.

Referring toFIG. 10, each of the sub-panels2ghas a first surface21, a second surface22opposite to the first surface21, and a lateral surface23extending between the first surface21and the second surface22. In some embodiments, at least a portion of the lateral surface23is an imaginary surface or an imaginary plane. As shown inFIG. 10, the first surface21is an upper surface, and the second surface22is a lower surface. Each of the sub-panels2gincludes a first dielectric layer3, a circuit structure5, a redistribution layer4, and at least one solder connecter26. Similarly, each of the substrate units20gmay include at least a portion of the first dielectric layer3, at least a portion of the circuit structure5, at least a portion of the redistribution layer4, and at least one solder connecter26.

The first dielectric layer3includes a first surface31, a second surface32opposite to the first surface31, and a lateral surface33extending between the first surface31and the second surface32. As shown inFIG. 10, the first surface31is an upper surface, and the second surface32is a lower surface. The first surface31of the first dielectric layer3may be a portion of the upper surface (e.g., the first surface21) of each of the sub-panels2g, the second surface32of the dielectric layer3may be a portion of the lower surface (e.g., the second surface22) of each of the sub-panels2g, and the lateral surface33of the first dielectric layer3may be a portion of the lateral surface23of the sub-panels2g. The first dielectric layer3may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the first dielectric layer3may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators.

The circuit structure5is disposed adjacent to the first surface31of the first dielectric layer3. For example, as shown inFIG. 10, the circuit structure5is embedded in the first dielectric layer3and exposed from the first surface31of the first dielectric layer3. A material of the circuit structure5may be, for example, a conductive metal, such as copper, or another metal or combination of metals.FIG. 10shows the circuit structure5composed of a single layer. However, in some embodiments, the circuit structure5may also include other layers, such as one or more seed layers. The circuit structure5includes at least one conductive pad53and at least one trace55. The conductive pad53and the trace55may be formed integrally and concurrently. The trace55has an upper surface551, which is at a level lower than the upper surface31of the first dielectric layer3. In some embodiments, an L/S of the circuit structure5may be equal to or less than 2 μm/2 μm.

The first dielectric layer3may further define at least one through hole30, such that a portion of the circuit structure5, such as the conductive pad53of the circuit structure5, can be exposed in the through hole30and from the second surface32of the dielectric layer3.

The redistribution layer4is electrically connected to the circuit structure5. For example, the redistribution layer4includes at least one conductive via43disposed in the through hole30of the first dielectric layer3and embedded in the first dielectric layer3. The conductive via43extends through the first dielectric layer3to contact and electrically connect the circuit structure5, such as the conductive pad53of the circuit structure5. In some embodiments, the redistribution layer4may further include at least one trace (not shown). A material of the redistribution layer4may be, for example, a conductive metal, such as copper, or another metal or combination of metals. In some embodiments, one or more seed layers may be disposed between the redistribution layer4and the first dielectric layer3. In some embodiments, a line width/line space (L/S) of the redistribution layer4may be equal to or greater than 10 μm/10 μm.

The solder connector26is disposed on and electrically connected to the conductive via43of the redistribution layer4. A material of the solder connector26may be a conductive metal, such as tin, or another metal or combination of metals. An under bump metallization (UBM)46may be disposed between the conductive via43and the solder connector26.

The dielectric portion14is disposed between the sub-panels2g. For example, a gap “g” is defined between adjacent two of the sub-panels2g, and the dielectric portion14is disposed in the gap “g”. The dielectric portion14has an upper surface141, a lower surface142and at least one lateral surface143extending between the upper surface141and the lower surface142. At least a portion of the lateral surface143is an imaginary surface or an imaginary plane. As shown inFIG. 10, the dielectric portion14has at least one lateral surface143corresponding to each of the sub-panels2g. The upper surface141of the dielectric portion14is at a level lower than the upper surface (e.g., the first surface21) of each of the sub-panels2gand/or the upper surface (e.g., the first surface31) of the first dielectric layer3. The lower surface142of the dielectric portion14is substantially coplanar with the lower surface (e.g., the second surface22) of each of the sub-panels2gand/or the lower surface (e.g., the second surface32) of the first dielectric layer3.

In some embodiments, the dielectric portion14covers and contacts at least a portion of a lateral surface23of each of the sub-panels2g. For example, the lateral surface143of the dielectric portion14contacts and is substantially coplanar with the lateral surface23of the first dielectric layer3of each of the sub-panels2gand/or the lateral surface33of the first dielectric layer3. In some embodiments, the first dielectric layer3of each of the sub-panels2gis formed integrally and concurrently with the dielectric portion14. For example, the dielectric layers3of the sub-panels2gand the dielectric portion14may be integrally and concurrently formed as a monolithic structure. That is, there is no boundary or interface between the dielectric portion14and the first dielectric layers3of the sub-panels2g.

The dielectric portion14may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the dielectric portion14may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. The material of the dielectric portion14may be the same as the material of the first dielectric layer3of each of the sub-panels2g. A thickness of the first dielectric layer3may be greater than a thickness of the dielectric portion14.

As shown inFIG. 10, at least one semiconductor die74is connected to each of the substrate units20g. That is, a plurality of semiconductor dice74is connected to each of the sub-panels2g. The semiconductor die74may include a bump75and an UBM76. The bump75is disposed on a lower surface741of the semiconductor die74, and the UBM76is disposed on the bump75. A material of the bump75may be copper. The UBM76may include a first layer761, a second layer762and a third layer763sequentially disposed on the bump75. For example, a material of the first layer761may be nickel, a material of the second layer762may be palladium, and a material of the third layer763may be gold, but not limited thereto. The UBM76of the semiconductor die74may be electrically connected to the conductive pad53of the circuit structure5through a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals.

An encapsulant78is disposed on and covers the substrate panel structure1g. For example, the encapsulant78is disposed on the first dielectric layer3of each of the sub-panels2g, and covers and encapsulates the semiconductor dice74. The encapsulant78may further include a portion784disposed in the gap “g” between the sub-panels2gand on the dielectric portion14. The portion784of the encapsulant78contacts the lateral surface33of the first dielectric layer3. The encapsulant78may be a molding compound. The substrate panel structure1gand the encapsulant78may be separated by a singulation process into a plurality of package units, such as the package unit7gshown inFIG. 16.

FIG. 11illustrates a cross-sectional view of an example of a substrate panel structure1haccording to some embodiments of the present disclosure. The substrate panel structure1halso includes a plurality of sub-panels2h, and a dielectric portion14disposed between the sub-panels2h. Each of the sub-panels2hincludes a plurality of substrate units20h.

Referring toFIG. 11, each of the sub-panels2hhas a first surface21, a second surface22opposite to the first surface21, and a lateral surface23extending between the first surface21and the second surface22. In some embodiments, at least a portion of the lateral surface23is an imaginary surface or an imaginary plane. As shown inFIG. 11, the first surface21is an upper surface, and the second surface22is a lower surface. Each of the sub-panels2hincludes a second dielectric layer6, a plurality of conductive pillars28, a circuit structure5, a first dielectric layer3, a redistribution layer4, and at least one solder connecter26. Similarly, each of the substrate units20hmay include at least a portion of the second dielectric layer6, a plurality of conductive pillars28, at least a portion of the circuit structure5, at least a portion of the first dielectric layer3, at least a portion of the redistribution layer4, and at least one solder connecter26.

The second dielectric layer6has a first surface61, a second surface62opposite to the first surface61, and a lateral surface63extending between the first surface61and the second surface62. As shown inFIG. 11, the first surface61is an upper surface, and the second surface62is a lower surface. The first surface61of the dielectric layer6is a portion of the upper surface (e.g., first surface21) of the sub-panel2h. The lateral surface63is a portion of the lateral surface23of the sub-panel2h. The second dielectric layer6defines a plurality of through holes60extending through the second dielectric layer6and between the first surface61and the second surface62. The second dielectric layer6may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the second dielectric layer6may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators.

The conductive pillars28are disposed in the through holes60of the second dielectric layer6, and two ends of each of the conductive pillars28are exposed from the second dielectric layer6. A material of the conductive pillars28may be, for example, a conductive metal, such as copper, or another metal or combination of metals.

The circuit structure5is disposed adjacent to the first surface61of the second dielectric layer6and electrically connected to the conductive pillars28. For example, as shown inFIG. 11, the circuit structure5is disposed on the first surface61of the second dielectric layer6, and portions of the circuit structure5may extend into the through holes60to contact the conductive pillars28. The circuit structure5may include a seed layer51and a conductive layer52. The seed layer51is disposed between the conductive layer52and the second dielectric layer6, and between the conductive layer52and the conductive pillars28. A material of the seed layer51may be, for example, titanium or copper. In some embodiments, the seed layer51may include a titanium layer and a copper layer. A material of the conductive layer52may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer51may be omitted, and the conductive layer52may directly contact the second dielectric layer6and the conductive pillars28. The circuit structure5includes at least one conductive pad53and at least one trace55. The conductive pad53and the trace55may be formed integrally and concurrently. In some embodiments, an L/S of the circuit structure5may be equal to or less than 2 μm/2 μm.

The redistribution layer4is disposed adjacent to the second surface62of the second dielectric layer6. For example, as shown inFIG. 11, the redistribution layer4is disposed on the second surface62of the second dielectric layer6, and portions of the redistribution layer4may extend into the through holes60to contact the conductive pillars28. The redistribution layer4is electrically connected to the circuit structure5through the conductive pillars28. The redistribution layer4may include a seed layer41and a conductive layer42. The seed layer41is disposed between the conductive layer42and the second dielectric layer6, and between the conductive layer42and the conductive pillars28. A material of the seed layer41may be, for example, titanium or copper. In some embodiments, the seed layer41may include a titanium layer and a copper layer. A material of the conductive layer42may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer41may be omitted, and the conductive layer42may directly contact the second dielectric layer6and the conductive pillars28. The redistribution layer4may include at least one conductive pad44and at least one trace45. In some embodiments, a line width/line space (L/S) of the redistribution layer4may be equal to or greater than 10 μm/10 μm.

The first dielectric layer3is disposed on the second surface62of the second dielectric layer6and covers the redistribution layer4. The first dielectric layer3includes a first surface31and a second surface32opposite to the first surface31. As shown inFIG. 11, the first surface31is an upper surface, and the second surface32is a lower surface. The upper surface (e.g., the first surface31) of the first dielectric layer3may contact the lower surface (e.g., the second surface62) of the second dielectric layer6.

The first dielectric layer3may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the first dielectric layer3may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. The first dielectric layer3defines at least one through hole30to expose at least a portion of the redistribution layer4, such as the conductive pad44of the redistribution layer4.

The solder connector26is disposed in the through hole30of the first dielectric layer3, and is on and electrically connected to the exposed portion of the redistribution layer4, such as the conductive pad44. A material of the solder connector26may be a conductive metal, such as tin, or another metal or combination of metals. A barrier layer47and a wetting layer48may be disposed between the conductive pad44and the solder connector26. A material of the barrier layer47may be nickel, and a material of the wetting layer may be gold.

The dielectric portion14is disposed between the sub-panels2h. For example, a gap “g” is defined between adjacent two of the sub-panels2h, and the dielectric portion14is disposed in the gap “g”. The dielectric portion14has an upper surface141, a lower surface142and at least one lateral surface143extending between the upper surface141and the lower surface142. At least a portion of the lateral surface143is an imaginary surface or an imaginary plane. As shown inFIG. 11, the upper surface141of the dielectric portion14is substantially coplanar with the upper surface (e.g., the first surface31) of the first dielectric layer3and the lower surface (e.g., the second surface62) of the second dielectric layer6of each of the sub-panels2h, and is lower than the upper surface (e.g., the first surface21) of each of the sub-panels2h. The lower surface142of the dielectric portion14is substantially coplanar with the lower surface (e.g., the second surface22) of each of the sub-panels2hand/or the lower surface (e.g., the second surface32) of the first dielectric layer3. The lateral surface143of the dielectric portion14is substantially coplanar with the lateral surface63of the second dielectric layer6of each of the sub-panels2h.

In some embodiments, the dielectric portion14covers and contacts at least a portion of a lateral surface23of each of the sub-panels2. In some embodiments, the first dielectric layer3of each of the sub-panels2his formed integrally and concurrently with the dielectric portion14. For example, the dielectric layers3of the sub-panels2hand the dielectric portion14may be integrally and concurrently formed as a monolithic structure. That is, there is no boundary or interface between the dielectric portion14and the first dielectric layers3of the sub-panels2h.

As shown inFIG. 11, at least one semiconductor die74is connected to each of the substrate units20h. That is, a plurality of semiconductor dice74is connected to each of the sub-panels2h. The semiconductor die74may include a bump75and an UBM76. The bump75is disposed on a lower surface741of the semiconductor die74, and the UBM76is disposed on the bump75. A material of the bump75may be copper. The UBM76may include a first layer761and second layer762sequentially disposed on the bump75. For example, a material of the first layer761may be nickel, and a material of the second layer762may be palladium, but not limited thereto. In some embodiments, the UBM76may include three layers made of nickel, palladium and gold. The UBM76of the semiconductor die74may be electrically connected to the conductive pad53of the circuit structure5through a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals.

An encapsulant78is disposed on and covers the substrate panel structure1h. For example, the encapsulant78is disposed on the second dielectric layer6of each of the sub-panels2h, and covers and encapsulates the semiconductor dice74. The encapsulant78includes a portion784disposed in the gap “g” formed between two adjacent sub-panels2hand on the dielectric portion14. The encapsulant78may contact and cover the lateral surface63of the second dielectric layer6. The encapsulant78may be a molding compound. The substrate panel structure1hand the encapsulant78may be separated by a singulation process into a plurality of package units, such as the package unit7hshown inFIG. 17.

FIG. 12illustrates a cross-sectional view of an example of a package unit7according to some embodiments of the present disclosure. The package unit7corresponds to each of the substrate units20shown inFIG. 3orFIG. 4. That is, the package unit7includes the substrate unit20, and further includes a semiconductor die74and an encapsulant78.

The semiconductor die74is connected to the substrate unit20. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74. The bump75of the semiconductor die74is electrically connected to the conductive via54of the circuit structure5of the substrate unit20through a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals.

The encapsulant78is disposed on the substrate unit20, and covers at least a portion of the substrate unit20and/or the semiconductor die74. For example, the encapsulant78is disposed between the second dielectric layer6of the substrate unit20and the semiconductor die74, and encapsulates the bump75and the solder material77. The encapsulant78may be an underfill or a molding compound.

FIG. 13illustrates a cross-sectional view of an example of a package unit7caccording to some embodiments of the present disclosure. The package unit7ccorresponds to each of the substrate units20cshown inFIG. 5orFIG. 6. That is, the package unit7cincludes the substrate unit20c, and further includes a semiconductor die74and an encapsulant78.

The semiconductor die74is connected to the substrate unit20c. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74. The bump75of the semiconductor die74is electrically connected to the conductive pad53of the circuit structure5of the substrate unit20cthrough a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals.

The encapsulant78is disposed on the substrate unit20c, and covers at least a portion of the substrate unit20cand/or the semiconductor die74. For example, the encapsulant78is disposed between the first dielectric layer3of the substrate unit20cand the semiconductor die74, and encapsulates the bump75, the solder material77and a portion of the circuit structure5. The encapsulant78may be an underfill or a molding compound.

FIG. 14illustrates a cross-sectional view of an example of a package unit7daccording to some embodiments of the present disclosure. The package unit7dcorresponds to each of the substrate units20dshown inFIG. 7. That is, the package unit7dincludes the substrate unit20d, and further includes a semiconductor die74and an encapsulant78.

The semiconductor die74is connected to the substrate unit20d. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74. The bump75of the semiconductor die74is electrically connected to the conductive pad53of the circuit structure5of the substrate unit20dthrough a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals.

The encapsulant78is disposed on the substrate unit20d, and covers at least a portion of the substrate unit20dand/or the semiconductor die74. For example, the encapsulant78is disposed between the first dielectric layer3of the substrate unit20dand the semiconductor die74, and encapsulates the bump75, the solder material77and a portion of the circuit structure5. The encapsulant78may be an underfill or a molding compound.

FIG. 15illustrates a cross-sectional view of an example of a package unit7faccording to some embodiments of the present disclosure. The package unit7fcorresponds to each of the substrate units20fshown inFIG. 9. That is, the package unit7fincludes the substrate unit20f, and further includes a semiconductor die74and an encapsulant78.

The semiconductor die74is connected to the substrate unit20fThe semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74, and an UBM76disposed on the bump75. The UBM76may include a first layer761and second layer762sequentially disposed on the bump75. For example, a material of the first layer761may be nickel, and a material of the second layer762may be palladium, but not limited thereto. In some embodiments, the UBM76may include three layers made of nickel, palladium and gold. The UBM76of the semiconductor die74is connected through the solder material77to the redistribution layer4of the substrate unit20f, such as the conductive via43of the redistribution layer4.

The encapsulant78is disposed on the substrate unit20f, and covers at least a portion of the substrate unit20fand/or the semiconductor die74. For example, the encapsulant78is disposed on the first dielectric layer3of the substrate unit20f, and covers and encapsulates the semiconductor die74, the bump75and the UBM76of the semiconductor die74, the solder material77, and the redistribution layer4of the substrate unit20f. The encapsulant78may be an underfill or a molding compound.

FIG. 16illustrates a cross-sectional view of an example of a package unit7gaccording to some embodiments of the present disclosure. The package unit7gcorresponds to each of the substrate units20gshown inFIG. 10. That is, the package unit7gincludes the substrate unit20g, and further includes the semiconductor die74and the encapsulant78. The semiconductor74and the encapsulant78are the same as those described inFIG. 10, thus are not repeated redundantly here.

FIG. 17illustrates a cross-sectional view of an example of a package unit7haccording to some embodiments of the present disclosure. The package unit7hcorresponds to each of the substrate units20hshown inFIG. 11. That is, the package unit7hincludes the substrate unit20h, and further includes the semiconductor die74and the encapsulant78. The semiconductor74and the encapsulant78are the same as those described inFIG. 11, thus are not repeated redundantly here.

FIG. 18illustrates a cross-sectional view of an example of a package unit7kaccording to some embodiments of the present disclosure. The package unit7kcorresponds to each of the substrate units20shown inFIG. 3orFIG. 4. That is, the package unit7includes the substrate unit20, and further includes a semiconductor die74and an encapsulant78. The package unit7kis similar to the package unit7shown inFIG. 12, except that the encapsulant78of the package unit7kcompletely covers the semiconductor die74.

FIGS. 19 to 26illustrate a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure such as the substrate panel structure1shown inFIGS. 2 and 3, and/or the package unit such as the package unit7shown inFIG. 12.

Referring toFIG. 19, an intermediate carrier81is provided. The intermediate carrier81may include a releasing film82disposed thereon. A seed layer is formed or disposed on the intermediate carrier81, by, for example, sputtering. As shown inFIG. 19, the seed layer includes a titanium layer83and a copper layer84sequentially disposed on the releasing film82of the intermediate carrier81.

Referring toFIG. 20, a second dielectric layer6is formed on the seed layer (e.g., the copper layer84). The second dielectric layer6has a first surface61, a second surface62opposite to the first surface61, and a lateral surface63extending between the first surface61and the second surface62. As shown inFIG. 20, the first surface61is an upper surface, and the second surface62is a lower surface. The first surface61contacts the seed layer (e.g., the copper layer84). The second dielectric layer6defines at least one through hole60extending through the second dielectric layer6and between the first surface61and the second surface62to expose a portion of the seed layer (e.g., the copper layer84). Then, a circuit structure5is formed on the second surface62of the second dielectric layer6and in the through hole60of the second dielectric layer6. The circuit structure5includes a seed layer51and a conductive layer52. The seed layer51is disposed between the conductive layer52and the second dielectric layer6, and between the conductive layer52and the seed layer (e.g., the copper layer84) in the through hole60. For example, the seed layer51may be formed by sputtering, and the conductive layer52may be formed by plating. A material of the seed layer51may be, for example, titanium or copper. In some embodiments, the seed layer51may include a titanium layer and a copper layer. A material of the conductive layer52may be, for example, a conductive metal, such as copper, or another metal or combination of metals. The circuit structure5includes at least one conductive pad53, at least one conductive via54and at least one trace55. The conductive pad53, the conductive via54and the trace55may be formed integrally and concurrently. In some embodiments, the conductive via54is disposed on and formed integrally with the conductive pad53. The conductive via54of the circuit structure5may be disposed in the through hole60of the second dielectric layer6. That is, each of the circuit structures5includes at least one conductive via54disposed in the through hole60of respective one of the second dielectric layers6. The trace55has an upper surface551, which contacts and is substantially coplanar with the lower surface62of the second dielectric layer6. In some embodiments, an L/S of the circuit structure5may be equal to or less than 2 μm/2 μm. Accordingly, an intermediate panel8is formed. The intermediate panel8includes a plurality of panel units80connected with each other. Each of the panel units80corresponds to a package unit, such as the package unit7shown inFIG. 12.

For illustration purpose,FIGS. 19 and 20shows one intermediate panel8. However, a plurality of intermediate panels8may be provided or formed through the aforementioned process. Each of the intermediate panels8includes one circuit structure5, and these intermediate panels8are separated from each other. That is, a plurality of intermediate carriers81may be provided, and the second dielectric layer6may be formed on each of the intermediate carriers81. Similarly, the circuit structure5may be formed on each of the intermediate carriers81, such as formed on the second dielectric layer6, thus forming each intermediate panel8. Since the intermediate panels8can be separately formed, materials and structures of each of the intermediate panels8may be different from others.

Referring toFIG. 21, a main carrier91is provided. The main carrier91includes a soft releasing film92disposed thereon. The intermediate panels8are disposed on the main carrier91and are partially embedded in the soft releasing film92. The intermediate carriers81are located between the main carrier91and the circuit structures5. A lower surface921of the soft releasing film92is at a level higher than the upper surface (e.g., the first surface61) of the second dielectric layer6. The intermediate panels8are spaced from each other, and a gap “g” is defined between adjacent two of the intermediate panels8. For illustration purpose,FIG. 21shows two intermediate panels8. However, an amount of the intermediate panels8may be more than two.

Referring toFIG. 22, a dielectric material is provided on the main carrier91to form a plurality of first dielectric layer3and a dielectric portion14. The dielectric material covers the intermediate panels8and the soft releasing film92. Each of the first dielectric layers3is disposed on respective one of the intermediate panels8. The dielectric portion14is disposed in the gap “g” between two adjacent intermediate panels8and on the soft releasing film92. The dielectric portion14is disposed between and connects the first dielectric layers3. The first dielectric layers3and the dielectric portion14are formed concurrently and integrally as a monolithic structure. That is, there is no boundary or interface between the dielectric portion14and the first dielectric layers3. The dielectric material may be an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the dielectric material may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. Accordingly, the first dielectric layers3and the dielectric portion14may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP), or may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators.

The first dielectric layer3includes a first surface31and a second surface32opposite to the first surface31. As shown inFIG. 22, the first surface31is an upper surface, and the second surface32is a lower surface. The upper surface (e.g., the first surface31) of the first dielectric layer3contacts the lower surface (e.g., the second surface62) of the second dielectric layer6, thus is substantially coplanar with the upper surface551of the trace55of the circuit structure5. In some embodiments, a thickness of the first dielectric layer3may be about 3 μm to about 20 preferably about 3 μm to about 15 μm.

The dielectric portion14has an upper surface141, a lower surface142and at least one lateral surface143extending between the upper surface141and the lower surface142. The upper surface141contacts the lower surface921of the soft releasing film92, thus is at a level higher than the upper surface (e.g., the first surface61) of the second dielectric layer6. At least a portion of the lateral surface143is an imaginary surface or an imaginary plane. The lateral surface143may contact and be substantially coplanar with the lateral surface63of the second dielectric layer6, and may further contact the releasing film82and the intermediate carrier81.

Referring toFIG. 23, at least one through hole30is formed through each of the first dielectric layers3by, for example, lithography or drilling. The through hole30exposes a portion of the circuit structure5, such as the conductive pad53of the circuit structure5. Then, a plurality of redistribution layers4are formed on the first dielectric layers3, and each of the redistribution layers4is electrically connected to respective one of the circuit structures5of the intermediate panels8. The redistribution layer4is disposed on the second surface32of the first dielectric layer3and in the through hole30. The redistribution layer4may include a seed layer41disposed on the first dielectric layer3, and a conductive layer42disposed on the seed layer41. A material of the seed layer41may be, for example, titanium or copper. In some embodiments, the seed layer41may include a titanium layer and a copper layer. For example, the seed layer41may be formed by sputtering, and the conductive layer42may be formed by plating. A material of the conductive layer42may be, for example, a conductive metal, such as copper, or another metal or combination of metals. The redistribution layer4may include at least one conductive via43disposed in the through hole30of the first dielectric layer3, and at least one conductive pad44disposed on the second surface32of the first dielectric layer3. The redistribution layer4is electrically connected to the circuit structure5through the conductive via43. In some embodiments, the redistribution layer4may further include at least one trace (not shown). In some embodiments, a line width/line space (L/S) of the redistribution layer4may be equal to or greater than 10 μm/10 μm.

Referring toFIG. 24, a protection layer25is formed on the first dielectric layers3and covers the redistribution layers4. The protection layer25has a first surface251and a second surface252opposite to the first surface251. The first surface251contacts the second surface32of the first dielectric layer3. In some embodiments, the protection layer25further includes a portion254extending into the gap “g” between the intermediate panels8and disposed on the dielectric portion14. The protection layer25may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators, or a solder resist layer. The protection layer25covers the redistribution layer4, and at least a portion of the redistribution layer4, such as the conductive pad44, is exposed from the protection layer25for external connection. In some embodiments, a thickness of the protection layer25may be about 10 μm to about 30 At least one solder connectors26is then formed on the exposed portion of the redistribution layer4, such as the conductive pad44of the redistribution layer4. A material of the solder connector26may be a conductive metal, such as tin, or another metal or combination of metals.

Referring toFIG. 25, the main carrier91, including the soft releasing layer92, is removed. Then, the intermediate carriers81, including the releasing films82, are removed, such that the seed layer (e.g., the titanium layer83) is exposed. Then, the seed layer (e.g., the titanium layer83and the copper layer84) are removed by, for example, etching, thus forming the substrate panel structure1shown inFIGS. 2 and 3. Each of the intermediate panels8corresponds to respective one of the sub-panels2. During the etching process, a portion of the seed layer51of the circuit structure5adjacent to the first surface61of the second dielectric layer6may also be removed, thus the conductive layer52of the conductive via54is exposed from the first surface61of the second dielectric layer6. Accordingly, the upper surface541of the conductive via54is recessed from the upper surface (e.g., the first surface61) of the second dielectric layer6.

Referring toFIG. 26, a plurality of semiconductor dice74are then connected or mounted to the circuit structure5of each of the intermediate panels8(e.g., the sub-panels2in the substrate panel structure1). For example, at least one semiconductor die74is connected to each of the substrate units20. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74. The bump75of the semiconductor die74is electrically connected to the conductive via54of the circuit structure5of the substrate unit20through a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals. A plurality of encapsulants78are then formed on each of the substrate units20to cover respective one of the semiconductor dice74. For example, the encapsulant78is disposed between the second dielectric layer6and the semiconductor die74, and encapsulates the bump75and the solder material77. Then, each of the sub-panels2is singulated. That is, each of the intermediate panels8(e.g., including the second dielectric layer6and the circuit structure5), each of the first dielectric layers3and each of the redistribution layers4are singulated, forming a plurality of package units, such as the package unit7shown inFIG. 12. For example, the edge of each sub-panel2may be cut along the lateral surface23, such that the dielectric portion14and the portion254of the protection layer25are removed during the singulation process.

In a comparative manufacturing process (e.g., a reconstitution process), an intermediate panel is first cut into a plurality of panel units separated from each other. The panel units are then picked up and placed on a main carrier. Then, other layers, such as a dielectric layer and a redistribution layer, are formed on main carriers, and a plurality of semiconductor dice are then connected to the panel units. The reason for cutting the intermediate panel into the panel units lies in that the intermediate panel is usually a wafer of a round shape, thus the cutting process may effectively decrease the waste area of the wafer. However, these panel units are placed on the main carrier by a machine, which may cause about 1 μm to 3 μm position shift of these units. That is, pitches of these panel units are not consistent, thus the semiconductor dice cannot be bond accurately to the panel units.

In comparison, since the intermediate panel8in the aforementioned manufacturing process of the present disclosure includes a plurality of panel units80which are connected to each other, pitches therebetween are not affected by pick and place process. That is, pitches between the panel units in the same intermediate panel are substantially consistent, thus the semiconductor dice can be mounted accurately to the panel units.

FIG. 27illustrates a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is also for manufacturing a substrate panel structure such as the substrate panel structure1shown inFIGS. 2 and 3, and/or the package unit such as the package unit7shown inFIG. 12. The initial stages of the illustrated process are the same as, or similar to, the stages illustrated inFIG. 19throughFIG. 20.FIG. 27depicts a stage subsequent to that depicted inFIG. 20.

The stage shown inFIG. 27is similar to that shown inFIG. 21, except for the follows. As shown inFIG. 27, the main carrier91includes a hard releasing film92ainstead of the soft releasing film92shown inFIG. 21. Accordingly, the intermediate panels8are disposed on the hard releasing film92a, instead of being embedded therein. A gap “g” is defined between adjacent two of the intermediate panels8. A resin material93, such as a photoresist, is applied in the gap “g” defined between adjacent two of the intermediate panels8. The resin material93may be applied on the hard releasing film92abefore the intermediate panels8are disposed, such that the intermediate panels8may be embedded in the resin material93. Alternatively, the resin material93may be applied in the in the gap “g” after the intermediate panels8are disposed. A lower surface931of the resin material93is at a level higher than the upper surface (e.g., the first surface61) of the second dielectric layer6. In a subsequent stage similar to the stage shown inFIG. 22, the lower surface931of the resin material93contacts the upper surface141of the dielectric portion14. That is, the thickness of the dielectric portion14can be adjusted by varying the thickness of the resin material93. A position of the upper surface141of the dielectric portion14can be adjusted by varying a position of the lower surface931of the resin material93.

The stages subsequent to that shown inFIG. 27of the illustrated process are similar to the stages illustrated inFIG. 22throughFIG. 25, thus forming the substrate panel structure1shown inFIGS. 2 and 3. Further stages, such as the stage shown inFIG. 26, may then be conducted to the substrate panel structure1shown inFIGS. 2 and 3to form a plurality of package units, such as the package unit7shown inFIG. 12.

FIGS. 28 and 29illustrate a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure such as the substrate panel structure1ashown inFIG. 4, and/or the package unit such as the package unit7shown inFIG. 12. The initial stages of the illustrated process are the same as, or similar to, the stages illustrated inFIG. 19throughFIG. 20.FIG. 28depicts a stage subsequent to that depicted inFIG. 20.

The stage shown inFIG. 28is similar to that shown inFIG. 21, except for the follows. As shown inFIG. 28, the main carrier91includes a soft releasing film92bhaving a thickness greater than that of the soft releasing film92shown inFIG. 21. A lower surface921bof the soft releasing film92bis substantially coplanar with the lower surface (e.g., the second surface62) of the second dielectric layer6. In a subsequent stage similar to the stage shown inFIG. 22, the lower surface921bof the soft releasing film92bcontacts the upper surface141of the dielectric portion14. Accordingly, the upper surface141of the dielectric portion14is substantially coplanar with the lower surface (e.g., the second surface62) of the second dielectric layer6, as shown inFIG. 4.

The stages subsequent to that shown inFIG. 28of the illustrated process are similar to the stages illustrated inFIG. 22throughFIG. 25, thus forming the substrate panel structure1ashown inFIG. 4. Each of the intermediate panels8corresponds to respective one of the sub-panels2.

Referring toFIG. 29, a plurality of semiconductor dice74are then connected or mounted to the circuit structure5of each of the intermediate panels8(e.g., the sub-panels2in the substrate panel structure1). For example, at least one semiconductor die74is connected to each of the substrate units20. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74. The bump75of the semiconductor die74is electrically connected to the conductive via54of the circuit structure5of the substrate unit20through a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals. A plurality of encapsulants78are then formed on each of the substrate units20to cover respective one of the semiconductor dice74. For example, the encapsulant78is disposed between the second dielectric layer6and the semiconductor die74, and encapsulates the bump75and the solder material77. Then, each of the sub-panels2is singulated. That is, each of the intermediate panels8(e.g., including the second dielectric layer6and the circuit structure5), each of the first dielectric layers3and each of the redistribution layers4are singulated, forming a plurality of package units, such as the package unit7shown inFIG. 12. For example, the edge of each sub-panel2may be cut along the lateral surface23, such that the dielectric portion14and the portion254of the protection layer25are removed during the singulation process.

FIG. 30illustrates a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is also for manufacturing a substrate panel structure such as the substrate panel structure1ashown inFIG. 4, and/or the package unit such as the package unit7shown inFIG. 12. The initial stages of the illustrated process are the same as, or similar to, the stages illustrated inFIG. 19throughFIG. 20.FIG. 27depicts a stage subsequent to that depicted inFIG. 20.

The stage shown inFIG. 30is similar to that shown inFIG. 28, except for the follows. As shown inFIG. 30, the main carrier91includes a hard releasing film92ainstead of the soft releasing film92bshown inFIG. 28. Accordingly, the intermediate panels8are disposed on the hard releasing film92a, instead of being embedded therein. A gap “g” is defined between adjacent two of the intermediate panels8. A resin material93a, such as a photoresist, is applied in the gap “g” defined between adjacent two of the intermediate panels8. The resin material93amay be applied on the hard releasing film92abefore the intermediate panels8are disposed, such that the intermediate panels8may be embedded in the resin material93a. Alternatively, the resin material93amay be applied in the in the gap “g” after the intermediate panels8are disposed. A lower surface931aof the resin material93ais substantially coplanar with the lower surface (e.g., the second surface62) of the second dielectric layer6. In a subsequent stage similar to the stage shown inFIG. 22, the lower surface931aof the resin material93acontacts the upper surface141of the dielectric portion14. Accordingly, the upper surface141of the dielectric portion14is substantially coplanar with the lower surface (e.g., the second surface62) of the second dielectric layer6, as shown inFIG. 4.

The stages subsequent to that shown inFIG. 30of the illustrated process are similar to the stages illustrated inFIG. 22throughFIG. 25, thus forming the substrate panel structure1ashown inFIG. 4. Further stages, such as the stage shown inFIG. 29, may then be conducted to the substrate panel structure1ashown inFIG. 4to form a plurality of package units, such as the package unit7shown inFIG. 12.

FIGS. 31 to 33illustrate a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure such as the substrate panel structure1bshown inFIG. 5, and/or the package unit such as the package unit7cshown inFIG. 13. The initial stages of the illustrated process are the same as, or similar to, the stage illustrated inFIG. 19.FIG. 31depicts a stage subsequent to that depicted inFIG. 19.

Referring toFIG. 31, a circuit structure5is formed on the seed layer (e.g., the copper layer84). A first surface57of the circuit structure5contacts the seed layer (e.g., the copper layer84). A material of the circuit structure5may be, for example, a conductive metal, such as copper, or another metal or combination of metals. The circuit structure5includes at least one conductive pad53and at least one trace55. The conductive pad53and the trace55may be formed integrally and concurrently. In some embodiments, an L/S of the circuit structure5may be equal to or less than 2 μm/2 μm. Accordingly, an intermediate panel8cis formed. The intermediate panel8cincludes a plurality of panel units80cconnected with each other. Each of the panel units80ccorresponds to a package unit, such as the package unit7cshown inFIG. 13.

Referring toFIG. 32, a main carrier91is provided. The main carrier91includes a soft releasing film92disposed thereon. The intermediate panels8care disposed on the main carrier91and are partially embedded in the soft releasing film92. A lower surface921of the soft releasing film92is at a level higher than the first surface57of the circuit structure5. As shown inFIG. 32, the first surface57of the circuit structure5is an upper surface. The intermediate panels are spaced8cfrom each other, and a gap “g” is defined between adjacent two of the intermediate panels8c. As shown inFIG. 32, the intermediate carriers81are located between the main carrier91and the circuit structures5. In a subsequent stage similar to the stage shown inFIG. 22, the lower surface921of the soft releasing film92contacts the upper surface141of the dielectric portion14. Accordingly, the upper surface141of the dielectric portion14is at a level higher than the upper surface (e.g., the first surface57) of the circuit structure5, as shown inFIG. 5. Besides, the first dielectric layer3formed on each of the intermediate panels8ccontacts the seed layer (e.g., the copper layer84), thus the upper surface (e.g., the first surface31) of the first dielectric layer3is substantially coplanar with the upper surface (e.g., the first surface57) of the circuit structure5, as shown inFIG. 5.

The stages subsequent to that shown inFIG. 32of the illustrated process are similar to the stages illustrated inFIG. 22throughFIG. 25, thus forming the substrate panel structure1bshown inFIG. 5. Each of the intermediate panels8ccorresponds to respective one of the sub-panels2c.

Referring toFIG. 33, a plurality of semiconductor dice74are then connected or mounted to the circuit structure5of each of the intermediate panels8c(e.g., the sub-panels2cin the substrate panel structure1b). For example, at least one semiconductor die74is connected to each of the substrate units20c. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74. The bump75of the semiconductor die74is electrically connected to the conductive pad53of the circuit structure5of the substrate unit20cthrough a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals. A plurality of encapsulants78are then formed on each of the substrate units20cto cover respective one of the semiconductor dice74. For example, the encapsulant78is disposed between the first dielectric layer3and the semiconductor die74, and covers and encapsulates the bump75, the solder material77and a portion of the circuit structure5. Then, each of the sub-panels2cis singulated. That is, each of the intermediate panels8c(e.g., including the circuit structure5), each of the first dielectric layers3and each of the redistribution layers4are singulated, forming a plurality of package units, such as the package unit7cshown inFIG. 13. For example, the edge of each sub-panel2cmay be cut along the lateral surface23, such that the dielectric portion14and the portion254of the protection layer25are removed during the singulation process.

FIG. 34illustrates a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is also for manufacturing a substrate panel structure such as the substrate panel structure1bshown inFIG. 5, and/or the package unit such as the package unit7cshown inFIG. 13. The initial stages of the illustrated process are the same as, or similar to, the stages illustrated inFIGS. 19 and 31.FIG. 34depicts a stage subsequent to that depicted inFIG. 31.

The stage shown inFIG. 34is similar to that shown inFIG. 32, except for the follows. As shown inFIG. 34, the main carrier91includes a hard releasing film92ainstead of the soft releasing film92shown inFIG. 32. Accordingly, the intermediate panels8care disposed on the hard releasing film92a, instead of being embedded therein. A gap “g” is defined between adjacent two of the intermediate panels8c. A resin material93, such as a photoresist, is applied in the gap “g” defined between adjacent two of the intermediate panels8c. The resin material93may be applied on the hard releasing film92abefore the intermediate panels8care disposed, such that the intermediate panels8cmay be embedded in the resin material93. Alternatively, the resin material93may be applied in the in the gap “g” after the intermediate panels8care disposed. A lower surface931of the resin material93is at a level higher than the upper surface e.g., the first surface57) of the circuit structure5. In a subsequent stage similar to the stage shown inFIG. 22, the lower surface931of the resin material93contacts the upper surface141of the dielectric portion14. Accordingly, the upper surface141of the dielectric portion14is at a level higher than the upper surface (e.g., the first surface57) of the circuit structure5, as shown inFIG. 5. Besides, the first dielectric layer3formed on each of the intermediate panels8ccontacts the seed layer (e.g., the copper layer84), thus the upper surface (e.g., the first surface31) of the first dielectric layer3is substantially coplanar with the upper surface (e.g., the first surface57) of the circuit structure5, as shown inFIG. 5.

The stages subsequent to that shown inFIG. 34of the illustrated process are similar to the stages illustrated inFIG. 22throughFIG. 25, thus forming the substrate panel structure1bshown inFIG. 5. Further stages, such as the stage shown inFIG. 33, may then be conducted to the substrate panel structure1bshown inFIG. 5to form a plurality of package units, such as the package unit7cshown inFIG. 13.

FIGS. 35 and 36illustrate a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure such as the substrate panel structure1cshown inFIG. 6, and/or the package unit such as the package unit7cshown inFIG. 13. The initial stages of the illustrated process are the same as, or similar to, the stages illustrated inFIGS. 19 and 31.FIG. 35depicts a stage subsequent to that depicted inFIG. 31.

The stage shown inFIG. 35is similar to that shown inFIG. 32, except for the follows. As shown inFIG. 35, the main carrier91includes a soft releasing film92bhaving a thickness greater than that of the soft releasing film92shown inFIG. 32. A lower surface921bof the soft releasing film92bis substantially coplanar with the upper surface (e.g., the first surface57) of the circuit structure5. In a subsequent stage similar to the stage shown inFIG. 22, the lower surface921bof the soft releasing film92bcontacts the upper surface141of the dielectric portion14. Accordingly, the upper surface141of the dielectric portion14is substantially coplanar with the upper surface (e.g., the first surface57) of the circuit structure5, as shown inFIG. 6. Besides, the first dielectric layer3formed on each of the intermediate panels8ccontacts the seed layer (e.g., the copper layer84), thus the upper surface (e.g., the first surface31) of the first dielectric layer3is substantially coplanar with the upper surface (e.g., the first surface57) of the circuit structure5and the upper surface141of the dielectric portion14, as shown inFIG. 6.

The stages subsequent to that shown inFIG. 35of the illustrated process are similar to the stages illustrated inFIG. 22throughFIG. 25, thus forming the substrate panel structure1cshown inFIG. 6. Each of the intermediate panels8ccorresponds to respective one of the sub-panels2c.

Referring toFIG. 36, a plurality of semiconductor dice74are then connected or mounted to the circuit structure5of each of the intermediate panels8c(e.g., the sub-panels2cin the substrate panel structure1c). For example, at least one semiconductor die74is connected to each of the substrate units20c. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74. The bump75of the semiconductor die74is electrically connected to the conductive pad53of the circuit structure5of the substrate unit20cthrough a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals. A plurality of encapsulants78are then formed on each of the substrate units20cto cover respective one of the semiconductor dice74. For example, the encapsulant78is disposed between the first dielectric layer3and the semiconductor die74, and covers and encapsulates the bump75, the solder material77and a portion of the circuit structure5. Then, each of the sub-panels2cis singulated. That is, each of the intermediate panels8c(e.g., including the circuit structure5), each of the first dielectric layers3and each of the redistribution layers4are singulated, forming a plurality of package units, such as the package unit7cshown inFIG. 13. For example, the edge of each sub-panel2cmay be cut along the lateral surface23, such that the dielectric portion14and the portion254of the protection layer25are removed during the singulation process.

FIG. 37illustrates a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is also for manufacturing a substrate panel structure such as the substrate panel structure1cshown inFIG. 6, and/or the package unit such as the package unit7cshown inFIG. 13. The initial stages of the illustrated process are the same as, or similar to, the stages illustrated inFIGS. 19 and 31.FIG. 27depicts a stage subsequent to that depicted inFIG. 31.

The stage shown inFIG. 37is similar to that shown inFIG. 35, except for the follows. As shown inFIG. 37, the main carrier91includes a hard releasing film92ainstead of the soft releasing film92bshown inFIG. 35. Accordingly, the intermediate panels8care disposed on the hard releasing film92a, instead of being embedded therein. A gap “g” is defined between adjacent two of the intermediate panels8c. A resin material93a, such as a photoresist, is applied in the gap “g” defined between adjacent two of the intermediate panels8c. The resin material93amay be applied on the hard releasing film92abefore the intermediate panels8care disposed, such that the intermediate panels8cmay be embedded in the resin material93a. Alternatively, the resin material93amay be applied in the in the gap “g” after the intermediate panels8care disposed. A lower surface931aof the resin material93ais substantially coplanar with the upper surface (e.g., the first surface57) of the circuit structure5. In a subsequent stage similar to the stage shown inFIG. 22, the lower surface931aof the resin material93acontacts the upper surface141of the dielectric portion14. Accordingly, the upper surface141of the dielectric portion14is substantially coplanar with the upper surface (e.g., the first surface57) of the circuit structure5, as shown inFIG. 6. Besides, the first dielectric layer3formed on each of the intermediate panels8ccontacts the seed layer (e.g., the copper layer84), thus the upper surface (e.g., the first surface31) of the first dielectric layer3is substantially coplanar with the upper surface (e.g., the first surface57) of the circuit structure5and the upper surface141of the dielectric portion14, as shown inFIG. 6.

The stages subsequent to that shown inFIG. 37of the illustrated process are similar to the stages illustrated inFIG. 22throughFIG. 25, thus forming the substrate panel structure1cshown inFIG. 6. Further stages, such as the stage shown inFIG. 36, may then be conducted to the substrate panel structure1cshown inFIG. 6to form a plurality of package units, such as the package unit7cshown inFIG. 13.

FIGS. 38 to 41illustrate a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure such as the substrate panel structure1dshown inFIG. 7, and/or the package unit such as the package unit7dshown inFIG. 14. The initial stages of the illustrated process are the same as, or similar to, the stage illustrated inFIGS. 19 and 31.FIG. 38depicts a stage subsequent to that depicted inFIG. 31.

Referring toFIG. 38, a main carrier91is provided. The main carrier91includes a soft releasing film92disposed thereon. The intermediate panels8dare disposed on the main carrier91and are partially embedded in the soft releasing film92. The intermediate panel8dincludes a plurality of panel units80dconnected with each other. Each of the panel units80dcorresponds to a package unit, such as the package unit7dshown inFIG. 14. The formation of the intermediate panels8dmay be same as, or similar to, the formation of the intermediate panel8cshown inFIG. 31. The circuit structures5of the intermediate panels8dare located between the main carrier91and the intermediate carriers81. The circuit structure5is embedded in the soft releasing film92. The first surface57of the circuit structure5is a lower surface, as shown inFIG. 38. A lower surface921of the soft releasing film92is substantially coplanar with the lower surface (e.g., the first surface57) of the circuit structure5. The intermediate panels8dare spaced from each other, and a gap “g” is defined between adjacent two of the intermediate panels8d. In an alternative manufacturing process, the soft releasing film92may be replaced by a hard releasing film92aand a resin material93, such as those shown inFIG. 27.

Referring toFIG. 39, the intermediate carriers81, including the releasing films82, are removed, such that the seed layer (e.g., the titanium layer83and the copper layer84) is exposed.

Referring toFIG. 40, the seed layer (e.g., the titanium layer83and the copper layer84) may be removed by, for example, etching. Then, a dielectric material may be provided on the main carrier91to form a plurality of first dielectric layer3and a dielectric portion14. The formation of the first dielectric layer3and a dielectric portion14may be similar to those shown inFIG. 22. Each of the first dielectric layers3is disposed on respective one of the intermediate panels8dand contacts the soft releasing film92. An upper surface (e.g., the first surface31) of the first dielectric layer3is thus substantially coplanar with the lower surface (e.g., the first surface57) of the circuit structure5. The dielectric portion14is disposed in the gap “g” between two adjacent intermediate panels8dand on the soft releasing film92. An upper surface141of the dielectric portion14is thus substantially coplanar with the lower surface (e.g., the first surface57) of the circuit structure5and/or the upper surface (e.g., the first surface31) of the first dielectric layer3.

Then, at least one through hole30is formed through each of the first dielectric layers3by, for example, lithography or drilling. The through hole30exposes a portion of the circuit structure5, such as the conductive pad53of the circuit structure5. Then, a plurality of redistribution layers4are formed on the first dielectric layers3, and each of the redistribution layers4is electrically connected to respective one of the circuit structures5of the intermediate panels8d. The formation of the through hole30of the first dielectric layer3and the redistribution layer4may be similar to those shown inFIG. 23. The redistribution layer4is disposed on the second surface32of the first dielectric layer3and in the through hole30. The redistribution layer4may include at least one conductive via43disposed in the through hole30of the first dielectric layer3, and at least one conductive pad44disposed on the second surface32of the first dielectric layer3. The redistribution layer4is electrically connected to the circuit structure5through the conductive via43.

Then, a protection layer25is formed on the first dielectric layers3and covers the redistribution layers4. The formation of the protection layer25may be similar to that shown inFIG. 24. The protection layer25has a first surface251and a second surface252opposite to the first surface251. The first surface251contacts the second surface32of the first dielectric layer3. In some embodiments, the protection layer25further includes a portion254extending into the gap “g” between the intermediate panels8dand disposed on the dielectric portion14. The protection layer25covers the redistribution layer4, and at least a portion of the redistribution layer4, such as the conductive pad44, is exposed from the protection layer25for external connection. Then, at least one solder connector26may be formed on the exposed portion of the redistribution layer4, such as the conductive pad44of the redistribution layer4. The formation of the protection layer25and the solder connector26may be similar to those shown inFIG. 24.

Then, the main carrier91, including the soft releasing layer92, is removed, forming the substrate panel structure2dshown inFIG. 7. Each of the intermediate panels8dcorresponds to respective one of the sub-panels2d. In an alternative manufacturing process, the main carrier91may be removed before the solder connector26is formed, thus forming the structure shown inFIG. 40. The structure shown inFIG. 40includes sub-panels2d′ similar to the sub-panels2dshown inFIG. 7, but without the solder connectors26. The structure shown inFIG. 40may also be utilized as a substrate panel structure.

Referring toFIG. 41, a plurality of semiconductor dice74are then connected or mounted to the circuit structure5of each of the intermediate panels8d(e.g., the sub-panels2din the substrate panel structure1d). For example, at least one semiconductor die74is connected to each of the substrate units20d. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74. The bump75of the semiconductor die74is electrically connected to the conductive via54of the circuit structure5of the substrate unit20dthrough a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals. An encapsulant78is then formed on and covers each of the first dielectric layers3and the dielectric portion14, and covers the semiconductor dice74. The encapsulant78covers and encapsulates the bump75, the solder material77and a portion of the circuit structure5. Then, each of the sub-panels2dis singulated. That is, each of the intermediate panels8d(e.g., including the circuit structure5), each of the first dielectric layers3, each of the redistribution layers4and the encapsulant7are singulated, forming a plurality of package units, such as the package unit7dshown inFIG. 14. For example, the edge of each sub-panel2dmay be cut along the lateral surface23, such that the dielectric portion14and the portion254of the protection layer25are removed during the singulation process.

Similarly, the above stages (e.g., the stages referring toFIG. 41) may also be conducted to the structure shown inFIG. 40to form the package unit7dshown inFIG. 14. In some embodiments, the solder connector26may be formed after formation of the encapsulant78.

FIGS. 42 to 48illustrate a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure such as the substrate panel structure2fshown inFIG. 9, and/or the package unit such as the package unit7fshown inFIG. 15.

Referring toFIG. 42, an intermediate carrier81is provided. The intermediate carrier81may include a releasing film82disposed thereon. A metal layer85is formed or disposed on the intermediate carrier81. As shown inFIG. 42, the metal layer85may include a seed layer851and a conductive layer852sequentially disposed on the releasing film82of the intermediate carrier81. For example, the seed layer851may be formed by sputtering, and the conductive layer852may be formed by plating. A material of the seed layer851may be, for example, titanium or copper. In some embodiments, the seed layer851may include a titanium layer and a copper layer. A material of the conductive layer852may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in other embodiments the metal layer85may be a metal foil pressed and attached to the releasing film82.

Referring toFIG. 43, a second dielectric layer6is formed on the metal layer85, such as formed on the conductive layer852of the metal layer85. The second dielectric layer6has a first surface61, a second surface62opposite to the first surface61, and a lateral surface63extending between the first surface61and the second surface62. The first surface61contacts the conductive layer852of the metal layer85. The second dielectric layer6defines at least one through hole60extending through the second dielectric layer6and between the first surface61and the second surface62to expose a portion of the conductive layer852of the metal layer85. Then, a circuit structure5is formed on the second surface62of the second dielectric layer6and in the through hole60of the second dielectric layer6. The circuit structure5includes a seed layer51and a conductive layer52. The seed layer51is disposed between the conductive layer52and the second dielectric layer6, and between the conductive layer52and the conductive layer852of the metal layer85in the through hole60. A material of the seed layer51may be, for example, titanium or copper. In some embodiments, the seed layer51may include a titanium layer and a copper layer. A material of the conductive layer52may be, for example, a conductive metal, such as copper, or another metal or combination of metals. The circuit structure5includes at least one conductive pad53, at least one conductive via54and at least one trace55. The conductive pad53, the conductive via54and the trace55may be formed integrally and concurrently. In some embodiments, the conductive via54is disposed on and formed integrally with the conductive pad53. The conductive via54of the circuit structure5may be disposed in the through hole60of the second dielectric layer6to connect the metal layer85. That is, each of the circuit structures5includes at least one conductive via54disposed in the through hole60of respective one of the second dielectric layers6. In some embodiments, an L/S of the circuit structure5may be equal to or less than 2 μm/2 μm. Accordingly, an intermediate panel8fis formed. The intermediate panel8fincludes a plurality of panel units80fconnected with each other. Each of the panel units80fcorresponds to a package unit, such as the package unit7fshown inFIG. 15.

Referring toFIG. 44, a main carrier91is provided. The main carrier91includes a soft releasing film92disposed thereon. The intermediate panels8fare disposed on the main carrier91and are partially embedded in the soft releasing film92. The circuit structures5of the intermediate panels8fare located between the main carrier91and the intermediate carriers81. The circuit structure5and the second dielectric layer6are embedded in the soft releasing film92. An upper surface921of the soft releasing film92is at a level lower than the upper surface (e.g., the first surface61) of the second dielectric layer6, while higher than the lower surface (e.g., the second surface62) of the second dielectric layer6. The intermediate panels8fare spaced from each other, and a gap “g” is defined between adjacent two of the intermediate panels8f. In an alternative manufacturing process, the soft releasing film92may be replaced by a hard releasing film92aand a resin material93, such as those shown inFIG. 27.

Referring toFIG. 45, the intermediate carriers81, including the releasing films82, are removed, such that the metal layer85is exposed. Then, the metal layer85is pattern to form a circuit layer27on the first surface61of the second dielectric layer6. The circuit layer27may include a seed layer271form of the seed layer851of the metal layer85, and a conductive layer272formed of the conductive layer852of the metal layer85. The circuit layer27may include at least one conductive pad274, and may further include at least one trace (not shown). The conductive via54of the circuit structure5contacts and electrically connects the circuit layer27.

Referring toFIG. 46, a dielectric material is provided on the main carrier91to form a plurality of first dielectric layer3and a dielectric portion14. The dielectric material covers the intermediate panels8fand the soft releasing film92. Each of the first dielectric layers3is disposed on respective one of the intermediate panels8f. The dielectric portion14is disposed in the gap “g” between two adjacent intermediate panels8fand on the soft releasing film92. The dielectric portion14is disposed between and connects the first dielectric layers3. The first dielectric layers3and the dielectric portion14are formed concurrently and integrally as a monolithic structure. That is, there is no boundary or interface between the dielectric portion14and the first dielectric layers3. The dielectric material may be an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the dielectric material may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. Accordingly, the first dielectric layers3and the dielectric portion14may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP), or may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators.

The first dielectric layer3includes a first surface31and a second surface32opposite to the first surface31. As shown inFIG. 46, the first surface31is an upper surface, and the second surface32is a lower surface. The first dielectric layer3is disposed on the second dielectric layer6and covers the circuit layer27. The lower surface (e.g., the second surface32) of the first dielectric layer3contacts the upper surface (e.g., the first surface61) of the second dielectric layer6.

The dielectric portion14has an upper surface141, a lower surface142and at least one lateral surface143extending between the upper surface141and the lower surface142. The lower surface142contacts the upper surface921of the soft releasing film92, thus is at a level lower than the lower surface (e.g., the second surface32) of the first dielectric layer37and the upper surface (e.g., the first surface61) of the second dielectric layer6, while higher than the lower surface (e.g., the second surface62) of the second dielectric layer6. At least a portion of the lateral surface143is an imaginary surface or an imaginary plane. The lateral surface143may contact and be substantially coplanar with the lateral surface63of the second dielectric layer6.

Referring toFIG. 47, at least one through hole30is formed through each of the first dielectric layers3by, for example, lithography or drilling. The through hole30exposes a portion of the circuit layer27, such as the conductive pad274of the circuit layer27. Then, a plurality of redistribution layers4are formed on the first dielectric layers3, and each of the redistribution layers4is electrically connected to respective one of the circuit structures5through respective one of the circuit layers27of the intermediate panels8fThe redistribution layer4is disposed on the first dielectric layer3and in the through hole30. The redistribution layer4may include a seed layer41and a conductive layer42. The seed layer41is disposed between the conductive layer42and the first dielectric layer3. A material of the seed layer41may be, for example, titanium or copper. In some embodiments, the seed layer41may include a titanium layer and a copper layer. A material of the conductive layer42may be, for example, a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer41may be omitted. The redistribution layer4may include at least one conductive via43, and may further include at least one trace (not shown). The conductive via43is disposed in the through hole30, and contacts and electrically connects the circuit layer27. A solder material77is formed or disposed on the conductive via43of the redistribution layer4for external connection. The solder material77may be made of tin, or another metal or combination of metals.

Then, the main carrier91, including the soft releasing layer92, is removed. A protection layer25is formed on the second dielectric layer6and covers the circuit structure5. The protection layer25has a first surface251and a second surface252opposite to the first surface251. The protection layer25exposes a portion of the circuit structure5, such as the conductive pad53of the circuit structure5for external connection. The protection layer25may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators, or a solder resist layer. At least one solder connectors26is then formed on the exposed portion of the circuit structure5, such as the conductive pad53of the circuit structure5. A material of the solder connector26may be a conductive metal, such as tin, or another metal or combination of metals. Accordingly, the substrate panel structure1fas shown inFIG. 9is formed. Each of the intermediate panels8fcorresponds to respective one of the sub-panels2f.

Referring toFIG. 48, a plurality of semiconductor dice74are then connected or mounted to the redistribution layer4of each of the intermediate panels8f(e.g., the sub-panels2fin the substrate panel structure1f). For example, at least one semiconductor die74is connected to each of the substrate units20f. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74, and an UBM76disposed on the bump75. The UBM76may include a first layer761and second layer762sequentially disposed on the bump75. For example, a material of the first layer761may be nickel, and a material of the second layer762may be palladium, but not limited thereto. The UBM76of the semiconductor die74is connected through the solder material77to the redistribution layer4of the substrate unit20f, such as the conductive via43of the redistribution layer4. An encapsulant78is then formed on and covers each of the first dielectric layers3and the dielectric portion14, and covers the semiconductor dice74. For example, the encapsulant78is disposed on the first dielectric layer3of the substrate unit20f, and covers and encapsulates the semiconductor die74, the bump75and the UBM76of the semiconductor die74, the solder material77, and the redistribution layer4of the substrate unit20fThe encapsulant78may be an underfill or a molding compound. Then, each of the sub-panels2fis singulated. That is, each of the intermediate panels8f(e.g., including the circuit layer27, the second dielectric layer6and the circuit structure5), each of the first dielectric layers3, each of the redistribution layers4and the encapsulant78are singulated, forming a plurality of package units, such as the package unit7fshown inFIG. 15. For example, the edge of each sub-panel2fmay be cut along the lateral surface23, such that the dielectric portion14and the portion254of the protection layer25are removed during the singulation process.

In an alternative manufacturing process, the main carrier91may be removed after the semiconductor dice74are connected to the circuit structures5, and the encapsulant78are formed. Then, the protection layer25and the solder connector26may be formed after the encapsulant78is formed and the main carrier91is removed.

FIGS. 49 to 54illustrate a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure such as the substrate panel structure1gshown inFIG. 10, and/or the package unit such as the package unit7gshown inFIG. 16. The initial stages of the illustrated process are the same as, or similar to, the stage illustrated inFIG. 19.FIG. 49depicts a stage subsequent to that depicted inFIG. 19.

Referring toFIG. 49, a patterned photoresist86is formed or disposed on the seed layer (e.g., the copper layer84). The patterned photoresist86has an upper surface861, and defines a plurality of openings860. Then, a circuit structure5is formed in the openings860of the patterned photoresist86and on the seed layer (e.g., the copper layer84). A material of the circuit structure5may be, for example, a conductive metal, such as copper, or another metal or combination of metals. The circuit structure5includes at least one conductive pad53and at least one trace55. The conductive pad53and the trace55may be formed integrally and concurrently. The trace55has an upper surface551, which is at a level lower than the upper surface861of the patterned photoresist86. In some embodiments, an L/S of the circuit structure5may be equal to or less than 2 μm/2 μm. Accordingly, an intermediate panel8gis formed. The intermediate panel8gincludes a plurality of panel units80gconnected with each other. Each of the panel units80gcorresponds to a package unit, such as the package unit7gshown inFIG. 16.

Referring toFIG. 50, a main carrier91is provided. The main carrier91includes a soft releasing film92disposed thereon. The intermediate panels8gare disposed on the main carrier91and are partially embedded in the soft releasing film92. As shown inFIG. 50, the intermediate carriers81are located between the main carrier91and the circuit structures5. An upper surface921of the soft releasing film92is at a level lower than the upper surface86of the patterned photoresist86. The intermediate panels8gare spaced from each other, and a gap “g” is defined between adjacent two of the intermediate panels8g.

Referring toFIG. 51, a plurality of semiconductor dice74are then connected or mounted to the circuit structure5of each of the intermediate panels8g. For example, at least one semiconductor die74is connected to each panel unit80g. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74, and an UBM76disposed on the bump75. A material of the bump75may be copper. The UBM76may include a first layer761, a second layer762and a third layer763sequentially disposed on the bump75. For example, a material of the first layer761may be nickel, a material of the second layer762may be palladium, and a material of the third layer763may be gold, but not limited thereto. The UBM76of the semiconductor die74may be electrically connected to the conductive pad53of the circuit structure5through a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals. An encapsulant78is then formed on the patterned photoresist85, and covers and encapsulates the semiconductor dice74on each of the intermediate panels8g. A first lower surface781of the encapsulant is substantially coplanar with the upper surface861of the patterned photoresist86. The encapsulant78may further include a portion784disposed in the gap “g” between the intermediate panels8gand contacts the upper surface921of the soft releasing film92. A second lower surface782of the portion784in the gap “g” is substantially coplanar with the upper surface921of the soft releasing film92. The second lower surface782is at a level lower than the first lower surface781. The encapsulant78may be a molding compound.

Referring toFIG. 52, the main carrier91, including the soft releasing layer92, is removed. Then, the intermediate carriers81, including the releasing films82, are removed, such that the seed layer (e.g., the titanium layer83) and the second lower surface782of the encapsulant78are exposed.

Referring toFIG. 53, the seed layer (e.g., the titanium layer83and the copper layer84) is removed by, for example, etching. Then, the patterned photoresist86is removed by, for example, stripping. The first lower surface781of the encapsulant78and the circuit structure5are thus exposed.

Referring toFIG. 54, a dielectric material is provided on the encapsulant78and the intermediate panels8g(e.g., the circuit structure5) to form a plurality of first dielectric layer3and a dielectric portion14. The dielectric material covers the intermediate panels8g(e.g., the circuit structure5). Each of the first dielectric layers3corresponds to respective one of the intermediate panels8g. The dielectric portion14is disposed in the gap “g” between two adjacent intermediate panels8and on the portion784of the encapsulant78in the gap “g”. The dielectric portion14is disposed between and connects the first dielectric layers3. The first dielectric layers3and the dielectric portion14are formed concurrently and integrally as a monolithic structure. That is, there is no boundary or interface between the dielectric portion14and the first dielectric layers3. The dielectric material may be an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the dielectric material may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. Accordingly, the first dielectric layers3and the dielectric portion14may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP), or may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators.

The first dielectric layer3includes a first surface31, a second surface32opposite to the first surface31, and a lateral surface33extending between the first surface31and the second surface32. As shown inFIG. 54, the first surface31is an upper surface, and the second surface32is a lower surface. The upper surface (e.g., the first surface31) of the first dielectric layer3contacts and is substantially coplanar with the first lower surface781of the encapsulant78, thus is at a level higher than the upper surface551of the trace55of the circuit structure5. The lateral surface33contacts the portion784of the encapsulant78.

The dielectric portion14has an upper surface141, a lower surface142and at least one lateral surface143extending between the upper surface141and the lower surface142. At least a portion of the lateral surface143is an imaginary surface or an imaginary plane. The upper surface141of the dielectric portion14contacts and is substantially coplanar with the second lower surface782of the portion784of the encapsulant78, thus is at a level lower than the upper surface (e.g., the first surface31) of the first dielectric layer3. The lower surface142of the dielectric portion14is substantially coplanar with the lower surface (e.g., the second surface32) of the first dielectric layer3.

Then, at least one through hole30is form through the first dielectric layer3, such that a portion of the circuit structure5, such as the conductive pad53of the circuit structure5, is exposed in the through hole30and from the second surface32of the dielectric layer3. A redistribution layer4is then formed electrically connected to the circuit structure5. For example, the redistribution layer4includes at least one conductive via43disposed in the through hole30of the first dielectric layer3and embedded in the first dielectric layer3. The conductive via43extends through the first dielectric layer3to contact and electrically connect the circuit structure5, such as the conductive pad53of the circuit structure5. In some embodiments, the redistribution layer4may further include at least one trace (not shown). A material of the redistribution layer4may be, for example, a conductive metal, such as copper, or another metal or combination of metals. In some embodiments, a line width/line space (L/S) of the redistribution layer4may be equal to or greater than 10 μm/10 μm.

Then, at least one solder material26ais formed or disposed on and electrically connected to the conductive via43of the redistribution layer4. The solder material26may be a conductive metal, such as tin, or another metal or combination of metals. An UBM46may be disposed between the conductive via43and the solder connector26. A reflow process may then be conducted to form the solder material26ainto a solder connector26, thus forming the substrate panel structure1gshown inFIG. 10. Each of the intermediate panels8gcorresponds to respective one of the sub-panels2g. Then, each of the sub-panels2gis singulated. That is, each of the intermediate panels8g(e.g., the circuit structure5), each of the first dielectric layers3, each of the redistribution layers4and the encapsulant78are singulated, forming a plurality of package units, such as the package unit7gshown inFIG. 16. For example, the edge of each sub-panel2gmay be cut along the lateral surface23, such that the dielectric portion14and the portion784of the encapsulant78in the gap “g” are removed during the singulation process.

FIGS. 55 to 60illustrate a manufacturing process according to some embodiments of the present disclosure. In some embodiments, the manufacturing process is for manufacturing a substrate panel structure such as the substrate panel structure1hshown inFIG. 11, and/or the package unit such as the package unit7hshown inFIG. 17. The initial stages of the illustrated process are the same as, or similar to, the stage illustrated inFIG. 19.FIG. 55depicts a stage subsequent to that depicted inFIG. 19.

Referring toFIG. 55, a second dielectric layer6is formed on the seed layer (e.g., the copper layer84). The second dielectric layer6has a first surface61, a second surface62opposite to the first surface61, and a lateral surface63extending between the first surface61and the second surface62. As shown inFIG. 55, the first surface61is an upper surface, and the second surface62is a lower surface. The second surface62contacts the seed layer (e.g., the copper layer84). The second dielectric layer6may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the second dielectric layer6may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. Then, a plurality of through holes60ais formed extending through the second dielectric layer6and between the first surface61and the second surface62. A plurality of conductive pillars28are then formed in the through holes60aof the second dielectric layer6by, for example, plating. A material of the conductive pillars28may be, for example, a conductive metal, such as copper, or another metal or combination of metals. Accordingly, an intermediate panel8his formed. The intermediate panel8hincludes a plurality of panel units80hconnected with each other. Each of the panel units80hcorresponds to a package unit, such as the package unit7hshown inFIG. 17.

Referring toFIG. 56, a circuit structure5is formed adjacent to the first surface61of the second dielectric layer6and electrically connected to the conductive pillars28. For example, as shown inFIG. 56, the circuit structure5is disposed on the first surface61of the second dielectric layer6, and portions of the circuit structure5may extend into the through holes60ato contact the conductive pillars28. The circuit structure5may include a seed layer51and a conductive layer52. The seed layer51is disposed between the conductive layer52and the second dielectric layer6, and between the conductive layer52and the conductive pillars28. A material of the seed layer51may be, for example, titanium or copper. In some embodiments, the seed layer51may include a titanium layer and a copper layer. A material of the conductive layer52may be, for example, a conductive metal, such as copper, or another metal or combination of metals. The circuit structure5includes at least one conductive pad53and at least one trace55. The conductive pad53and the trace55are formed integrally and concurrently. In some embodiments, an L/S of the circuit structure5may be equal to or less than 2 μm/2 μm. Forming the circuit layer5may include forming a pattern photoresist on the second dielectric layer6, and forming the circuit layer5in the pattern photoresist and on the second dielectric layer6. It is noted that the pattern photoresist may be removed in the stage shown inFIG. 56, or may alternatively be removed after the intermediate panel8his disposed on a main carrier, such as the stage shown inFIG. 57.

Referring toFIG. 57, a main carrier91is provided. The main carrier91includes a soft releasing film92disposed thereon. The intermediate panels8hare disposed on the main carrier91and are partially embedded in the soft releasing film92. The intermediate carriers81are located between the main carrier91and the circuit structures5. An upper surface921of the soft releasing film92is substantially coplanar with the lower surface (e.g., the second surface62) of the second dielectric layer6. The intermediate panels8hare spaced from each other, and a gap “g” is defined between adjacent two of the intermediate panels8h.

Referring toFIG. 58, a plurality of semiconductor dice74are then connected or mounted to the circuit structure5of each of the intermediate panels8h. For example, at least one semiconductor die74is connected to each panel unit80h. The semiconductor die74may include a bump75disposed on a lower surface741of the semiconductor die74, and an UBM76disposed on the bump75. A material of the bump75may be copper. The UBM76may include a first layer761and second layer762sequentially disposed on the bump75. For example, a material of the first layer761may be nickel, and a material of the second layer762may be palladium, but not limited thereto. The UBM76of the semiconductor die74may be electrically connected to the conductive pad53of the circuit structure5through a solder material77disposed therebetween. The solder material77may be made of tin, or another metal or combination of metals.

An encapsulant78is then formed on the second dielectric layer6, and covers and encapsulates the semiconductor dice74on each of the intermediate panels8h. The encapsulant78includes a portion784disposed in the gap “g” between two adjacent sub-panels2hand on the soft releasing film92. A lower surface782of the portion784of the encapsulant78contacts and is substantially coplanar with the upper surface921of the soft releasing film92, thus is also substantially coplanar with the lower surface (e.g., the second surface62) of the second dielectric layer6. The encapsulant78may contact and cover the lateral surface63of the second dielectric layer6. The encapsulant78may be a molding compound.

Referring toFIG. 59, the main carrier91, including the soft releasing layer92, is removed, such that the surface782of the portion784of the encapsulant78is exposed. Then, the intermediate carriers81, including the releasing films82, are removed, such that the seed layer (e.g., the titanium layer83) is exposed. Then, the seed layer (e.g., the titanium layer83and the copper layer84) are removed by, for example, etching. A laser drilling process may be conducted to enlarge a portion of the through hole60a, forming the shape of the through hole60as shown inFIG. 59. A redistribution layer4is then formed adjacent to the second surface62of the second dielectric layer6. For example, as shown inFIG. 59, the redistribution layer4is disposed on the second surface62of the second dielectric layer6, and portions of the redistribution layer4may extend into the through holes60to contact the conductive pillars28. The redistribution layer4is electrically connected to the circuit structure5through the conductive pillars28. The redistribution layer4may include a seed layer41and a conductive layer42. The seed layer41is disposed between the conductive layer42and the second dielectric layer6, and between the conductive layer42and the conductive pillars28. A material of the seed layer41may be, for example, titanium or copper. In some embodiments, the seed layer41may include a titanium layer and a copper layer. A material of the conductive layer42may be, for example, a conductive metal, such as copper, or another metal or combination of metals. The redistribution layer4may include at least one conductive pad44and at least one trace45. In some embodiments, a line width/line space (L/S) of the redistribution layer4may be equal to or greater than 10 μm/10 μm.

Referring toFIG. 60, a dielectric material is provided on the encapsulant78and the intermediate panels8h(e.g., the second dielectric layers6) to form a plurality of first dielectric layer3and a dielectric portion14. The dielectric material covers the redistribution layer4. Each of the first dielectric layers3is disposed on respective one of the intermediate panels8h. The dielectric portion14is disposed in the gap “g” between two adjacent intermediate panels8hand on the portion784of the encapsulant4. The dielectric portion14is disposed between and connects the first dielectric layers3. The first dielectric layers3and the dielectric portion14are formed concurrently and integrally as a monolithic structure. That is, there is no boundary or interface between the dielectric portion14and the first dielectric layers3. The dielectric material may be an insulating material or a dielectric material, such as, for example, polypropylene (PP). It is noted that the dielectric material may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. Accordingly, the first dielectric layers3and the dielectric portion14may be made of an insulating material or a dielectric material, such as, for example, polypropylene (PP), or may include, or be formed from, a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators.

The first dielectric layer3includes a first surface31and a second surface32opposite to the first surface31. As shown inFIG. 60, the first surface31is an upper surface, and the second surface32is a lower surface. The upper surface (e.g., the first surface31) of the first dielectric layer3contacts the lower surface (e.g., the second surface62) of the second dielectric layer6.

The dielectric portion14has an upper surface141, a lower surface142and at least one lateral surface143extending between the upper surface141and the lower surface142. The upper surface141contacts the surface782of the portion784of the encapsulant78, thus is substantially coplanar with the lower surface (e.g., the second surface62) of the second dielectric layer6and/or the upper surface (e.g., the first surface31) of the dielectric layer3. At least a portion of the lateral surface143is an imaginary surface or an imaginary plane. The lateral surface143may be substantially coplanar with the lateral surface63of the second dielectric layer6.

Then, at least one through hole30is formed extending through the first dielectric layer3to expose at least a portion of the redistribution layer4, such as the conductive pad44of the redistribution layer4. At least one solder connector26is formed in the through hole30of the first dielectric layer3, and is on and electrically connected to the exposed portion of the redistribution layer4, such as the conductive pad44. A material of the solder connector26may be a conductive metal, such as tin, or another metal or combination of metals. A barrier layer47and a wetting layer48may be disposed between the conductive pad44and the solder connector26. A material of the barrier layer47may be nickel, and a material of the wetting layer may be gold. Accordingly, the substrate panel1hshown inFIG. 11is formed. Each of the intermediate panels8hcorresponds to respective one of the sub-panels2h.

Then, each of the sub-panels2his singulated. That is, each of the intermediate panels8h(e.g., including the second dielectric layer6and the circuit structure5), each of the first dielectric layers3, each of the redistribution layers4and the encapsulant78are singulated, forming a plurality of package units, such as the package unit7hshown inFIG. 17. For example, the edge of each sub-panel2hmay be cut along the lateral surface23, such that the dielectric portion14and the portion784of the encapsulant78are removed during the singulation process.