Stackable semiconductor package having semiconductor chip within central through hole of substrate

A stackable semiconductor package includes a substrate having a first surface, an opposite second surface, and through hole. Circuit patterns on the first and second surfaces of the substrate include lands, and the circuit patterns of the second surface also include bond fingers. A semiconductor chip is in the throughhole. The semiconductor chip has bond pads, which are oriented in a same direction as the second surface of the substrate. Wires electrically connect the bond pads to the bond fingers. An encapsulant fills the through hole and covers the semiconductor chip, the wires and the bond fingers, without covering the lands. Conductive balls are fused to the lands of the first surface of the substrate. A second semiconductor package may be stacked on the second surface of the substrate, and conductive balls of the second semiconductor package may be fused to the lands of the second surface.

BACKGROUND OF THE INVENTION

I. Field of the Invention

The present invention relates to a semiconductor package and a method for fabricating the semiconductor package.

II. Description of the Prior Art

Recently, semiconductor devices have been developed to have a thinner and more miniature structure. For such semiconductor devices, there are ball grid array (BGA) semiconductor packages, chip scale semiconductor packages, and micro BGA semiconductor packages.

Also, semiconductor chips, which are mounted on semiconductor packages as mentioned above, have been developed toward a high performance of electric power circuits, an increase in operating frequency, and an expansion of circuit functions, in pace with the development of integration techniques and manufacturing equipment. For this reason, an increase in heat occurs inevitably during the operation of such a semiconductor chip.

Referring toFIG. 10, a typical BGA semiconductor package having a conventional structure involving the above mentioned problem is illustrated.

As shown inFIG. 10, the BGA semiconductor package, which is denoted by the reference numeral100′, includes a semiconductor chip1′ arranged at a central portion of the semiconductor package100′. The semiconductor chip1′ is provided with a plurality of integrated electronic circuits. A plurality of input/output pads2′ are provided at an upper surface of the semiconductor chip1′. A circuit board10′ is bonded at a central portion thereof to a lower surface of the semiconductor chip1′ by means of an adhesive3′.

The circuit board10′ includes a resin substrate15′. A circuit pattern12′ provided with bond fingers11′ is formed on an upper surface of the resin substrate15′ around the semiconductor chip1′. Another circuit pattern provided with a plurality of ball lands13′ is formed on a lower surface of the resin substrate15′. Each of the circuit patterns is comprised of a thin film made of a conductive material such as copper (Cu). These circuit patterns are interconnected together by via holes14′. The exposed surface portions of the circuit patterns not covered with the bond fingers11′ and ball lands13′ are coated with cover coats16′, respectively, so that those circuit patterns are protected from the external environment.

The input/output pads2′ of the semiconductor chip1′ are connected to the bond fingers11′ on the upper surface of the circuit board10′ by means of conductive wires4′, respectively. In order to protect the conductive wires4′ from the external environment, the upper surface of the circuit board10′ is encapsulated by a resin encapsulate20′.

The circuit board10′ is mounted on a mother board (not shown) in a state in which a plurality of conductive balls40′ are fused on the ball lands13′, respectively, so that it serves as a medium for electrical signals between the semiconductor chip1′ and mother board.

In the BGA semiconductor package100′ having the above mentioned configuration, the semiconductor chip1′ thereof exchanges electrical signals with the mother board via the input/output pads2′, conductive wires4′, bond fingers11′, via holes14′, ball lands13′, and conductive balls40′, respectively.

However, the above mentioned conventional BGA semiconductor package is problematic in that it has an increased thickness because the semiconductor chip is bonded to the upper surface of the circuit board having a relatively large thickness. This is contrary to the recent trend toward a miniaturization and thinness. As a result, the above mentioned semiconductor package is problematic in that it cannot be applied to a variety of miniature electronic appliances such as portable phones, cellular phones, pagers, and notebooks.

Furthermore, in spite of the increasing heat generated at the semiconductor chip, as mentioned above, there is no appropriate heat discharge means in the conventional semiconductor package. As a result, the conventional semiconductor package is implicated in a heat-related degradation in the electrical performance and other functions of the semiconductor chip. In severe cases, the semiconductor package and the electronic appliance using it may be so damaged as not to be inoperable.

Although a semiconductor package has been proposed, which is provided with a heat discharge plate or heat sink for easily discharging heat generated from the semiconductor chip, the provision of such a heat discharge plate causes another problem because it serves to further increase the thickness of the semiconductor package while increasing the manufacturing costs.

SUMMARY OF THE INVENTION

Therefore, the present invention has been made in view of the above mentioned problems involved in the prior art, and an object of the invention is to provide a semiconductor package having a super-thin structure and a method for fabricating the semiconductor package.

Another object of the invention is to provide a semiconductor package having a structure capable of easily discharging heat from a semiconductor chip included therein, and a method for fabricating the semiconductor package.

In accordance with one aspect, the present invention provides a semiconductor package comprising: a semiconductor chip having a first major surface and a second major surface, the semiconductor chip being provided at the second major surface with a plurality of input/output pads; a circuit board including a resin substrate having a first major surface and a second major surface, a first circuit pattern formed at the first major surface and provided with a plurality of ball lands, a second circuit pattern formed at the second major surface and provided with a plurality of bond fingers connected with the ball lands by conductive via holes, cover coats respectively coating the first and second circuit patterns while allowing the bond fingers and the ball lands to be open, and a central through hole adapted to receive the semiconductor chip therein; electrical connection means for electrically connecting the input/output pads of the semiconductor chip with the bond fingers of the circuit board, respectively; a resin encapsulate for encapsulating the semiconductor chip, the electrical connection means, and the circuit board; and a plurality of conductive balls fused on the ball lands of the circuit board, respectively.

The semiconductor chip may be arranged in such a fashion that it is oriented, at the second major surface thereof, in the same direction as the second major surface of the circuit board provided with the bond fingers while being flush, at the first major surface thereof, with the first major surface of the circuit board provided with the ball lands and one surface of the resin encapsulate.

The resin encapsulate may be formed to completely or partially encapsulate the second major surface of the circuit board provided with the bond fingers.

The second major surface of the circuit board provided with the bond fingers may be further provided with a plurality of ball lands.

A plurality of conductive balls may be fused on the ball lands provided at the second major surface of the circuit board, respectively.

The semiconductor package may further comprises a closure member attached to the first major surface of the semiconductor chip and adapted to cover the through hole of the circuit board.

Preferably, each of the closure members comprises an insulating tape or a copper layer.

In accordance with another aspect, the present invention provides a method for fabricating semiconductor packages comprising the steps of: preparing a circuit board strip including a plurality of unit circuit boards, the circuit board strip having a plurality of ball lands formed at a first major surface thereof, a plurality of bond fingers formed at a second major surface thereof and respectively connected with the ball lands by conductive via holes, and a plurality of through holes respectively associated with the unit circuit boards; receiving, in the through holes, semiconductor chips each having a first major surface and a second major surface provided with a plurality of input/output pads, respectively; electrically connecting the input/output pads of the semiconductor chips with associated ones of the bond fingers of the circuit board strip using connection means, respectively; encapsulating the semiconductor chips, the connection means, and the through holes of the circuit board strip using an encapsulating material; fusing conductive balls on the ball lands of the circuit board strip; and singulating the circuit board strip into semiconductor packages respectively corresponding to the unit circuit boards.

The circuit board strip prepared at the circuit board strip preparing step may comprise: a main strip including a resin substrate having a substantially rectangular strip shape provided with a first major surface and a second major surface; a plurality of main slots extending to a desired length in a direction transverse to a longitudinal direction of the main strip while being uniformly spaced apart from one another in the longitudinal direction of the main strip, thereby dividing the main strip into a plurality of sub-strips aligned together in the longitudinal direction of the main strip; a plurality of sub slots extending to a desired length and serving to divide each of the sub-strips into a plurality of strip portions arranged in a matrix array, each of the strip portions corresponding to one of the unit circuit boards while having one of the through holes; a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the ball lands; a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be externally open.

Alternatively, the circuit board strip prepared at the circuit board strip preparing step may comprise: a resin substrate having a substantially rectangular strip shape provided with a first major surface and a second major surface; a plurality of slots extending to a desired length and serving to divide each of the resin substrate into a plurality of substrate portions arranged in a matrix array, each of the substrate portions corresponding to one of the unit circuit boards while having one of the through holes; a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the ball lands; a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be externally open.

The method may further comprise the step of attaching a plurality of closure members to the first major surface of the circuit board strip in such a fashion that each of the closure members covers an associated one of the through holes, prior to the step of receiving the semiconductor chips in the through holes.

The method may further comprise the step of attaching a plurality of closure members to the first major surface of the main strip in such a fashion that each of the closure members covers an associated one of the through holes, prior to the step of receiving the semiconductor chips in the through holes.

The closure member attaching step may comprise the steps of preparing closure member strips each having closure members for an associated one of the sub-strips, and individually attaching the closure member strips to the sub-strips, respectively, in such a fashion that each of the closure member strips is arranged to cover the main slot formed at one side of an associated one of the sub-strips.

Alternatively, the closure member attaching step may comprise the steps of preparing a single closure member strip having closure members for all sub-strips of the circuit board strip while having small singulation apertures at a region corresponding to each of the main slots, and attaching the closure member strip to the main strip in such a fashion that the closure member strip is arranged to allow each of the small singulation apertures to be aligned with an associated one of the main slots.

The closure members are removed after the encapsulating step, e.g., before or after the conductive ball fusing step, or after the singulation step.

The closure members may be removed by inserting a planar bar into each of the main slots in a direction from the second major surface of the circuit board strip to the first major surface of the second board strip, thereby detaching an associated one of the closure members from the circuit board strip at one side of the associated closure member.

Each of the closure members may comprise an insulating tape, an ultraviolet tape, or a copper layer.

The encapsulating step may be carried out to form an encapsulate completely encapsulating the second major surface of the circuit board strip.

The singulation step may be carried out in such a fashion that the encapsulate and the circuit board strip are simultaneously singulated.

The encapsulating step may comprise the steps of interposing the circuit board strip between a pair of molds, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated one of the cavities while facing an associated one of the gates at a central portion thereof, and injecting the encapsulating material into each of the cavities through an associated one of the gates in such a fashion that it flows outwardly from the central portion of the second major surface of the associated semiconductor chip along the second major surface.

The circuit board strip prepared at the circuit board strip preparing step may be further provided with a plurality of ball lands at the second major surface thereof having the bond fingers. In this case, the conductive ball fusing step further comprises the step of fusing a plurality of conductive balls on the ball lands provided at the second major surface of the circuit board strip having the bond fingers.

In accordance with the present invention, a circuit board is used which has a through hole of a desired size adapted to receive a semiconductor chip, thereby allowing the thickness of the semiconductor chip to be offset by the thickness of the circuit board. Accordingly, it is possible to fabricate semiconductor packages having a super-thin structure.

In accordance with the present invention, the semiconductor chip is outwardly exposed at one major surface thereof without being encapsulated by an encapsulate. Accordingly, heat generated from the semiconductor chip can be easily discharged into the atmosphere. This results in an improvement in the thermal and electrical performance of the semiconductor chip.

In accordance with the present invention, the circuit board may be completely encapsulated at one major surface thereof by an encapsulate. In this case, it is possible to effectively prevent a bending phenomenon of the circuit board.

In addition, the use of closure members during the fabrication of semiconductor packages according to the present invention achieves an easy encapsulating process. For such closure members, closure member strips may be used, each of which has closure members for one sub strip of a circuit board strip. In this case, the closure member strips are individually attached to the sub-strips of the circuit board strip. Alternatively, a single closure member strip may be used which has closure members for all sub-strips of the circuit board strip while having small singulation apertures or slits. By virtue of such a single closure member strip or closure member strips, an easy removal of closure members is achieved.

Also, the encapsulating process involved in the fabrication of semiconductor packages is conducted in such a fashion that it proceeds from the second major surface of each semiconductor chip in accordance with the present invention. Accordingly, it is possible to achieve a uniform encapsulation while suppressing the occurrence of a wire sweeping phenomenon.

DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Referring toFIGS. 1 to 5, semiconductor packages according to various embodiments of the present invention are illustrated, respectively.

In accordance with the embodiment of the present invention illustrated inFIG. 1, the semiconductor package, which is denoted by the reference numeral101, includes a semiconductor chip30having a first major surface30a(a lower surface inFIG. 1) and a second major surface30b(an upper surface inFIG. 1). A plurality of input/output pads31are formed at the second major surface30bof the semiconductor chip30.

The semiconductor chip30is arranged in such a fashion that it is received in a through hole12formed through a circuit board10to have a desired size. The through hole12has a size larger than the area of the first or second surface30aor30bof the semiconductor chip30. The circuit board10includes a resin substrate17having a first major surface11a(a lower surface inFIG. 1) and a second major surface11b(an upper surface inFIG. 1). The through hole12is centrally formed through the resin substrate17. The resin substrate17is provided at the first major surface11athereof with a conductive circuit pattern18having a plurality of ball lands18b. The conductive circuit pattern18is arranged around the through hole12. The resin substrate17is also provided at the second major surface11bthereof with another conductive circuit pattern18having a plurality of bond fingers18a. The conductive circuit patterns18on the first and second major surfaces of the circuit board10are electrically connected to each other by conductive via holes20.

Each of the bond fingers18ais plated with gold (Au) or silver (Ag) in order to allow an easy bonding of a conductive connecting means40(e.g., a bond wire) thereto. Each of the ball lands18bis plated with gold (Au), silver (Ag), nickel (Ni), or palladium (Pd) in order to allow an easy bonding of a conductive ball60thereto. Preferably, the resin substrate17is made of a bismaleimide triazine (BT) epoxy resin exhibiting a hardness. Of course, the resin substrate17is not limited to the above mentioned material.

The conductive circuit patterns18are coated with cover coats19in such a fashion that the bond fingers18aand ball lands18bare externally open through the cover coats19, respectively, so that they are protected from physical, chemical, electrical, and mechanical damage externally applied thereto.

The input/output pads31of the semiconductor chip30are electrically interconnected with the bond fingers18aon the circuit board10via the conductive connecting means40, respectively. The conductive connecting means40may comprise conductive wires, such as gold (Au) wires or aluminum (Al) wires, or leads extending from respective bond fingers18a.

Meanwhile, the semiconductor chip30and conductive connecting means40are encapsulated by a resin encapsulate50so that they are protected from external physical, chemical, and mechanical damage. The resin encapsulate50may be formed in such a fashion that it completely encapsulates the entire upper surface of the circuit board10, as shown inFIG. 1. Where the resin encapsulate50completely encapsulates the entire upper surface of the circuit board10, there is an advantage in that it is possible to prevent the circuit board10from being bent. Alternatively, the resin encapsulate50may be formed in such a fashion that it partially encapsulates the upper surface of the circuit board10at a region where the semiconductor chip30, connecting means40, and bond fingers18aare arranged, as shown inFIG. 2. The resin encapsulate50may be formed using an epoxy molding compound so that it is molded using a mold. The use of such a molding compound may be implemented in the case ofFIG. 1or2. On the other hand, a liquid encapsulating resin may be used to form the resin encapsulate50. In this case, the encapsulation process may be carried out using a dispenser. The use of such a liquid encapsulating resin may be implemented in the case ofFIG. 3. Where the liquid encapsulating resin is used, a dam25may be formed on the upper surface of the circuit board10, as shown inFIG. 3, in order to prevent the liquid encapsulating resin from flowing beyond a desired encapsulating region. In the case ofFIG. 1or2, the liquid encapsulating resin may also be used. In other words, the present invention is not limited by the material of the resin encapsulate. Semiconductor packages ofFIGS. 2 and 3are denoted by the reference numerals102and103, respectively.

In either case ofFIG. 1,2or3, the semiconductor package is formed in such a fashion that the second major surface30bof the semiconductor chip30and the circuit board surface formed with the bond fingers18a, that is, the second major surface11bof the circuit board10, are oriented in the same direction. Also, the first major surface30aof the semiconductor chip30, the circuit board surface formed with the ball lands18b, that is, the first major surface11aof the circuit board10, and the lower surface of the resin encapsulate50are flush with one another. Accordingly, the semiconductor package has a thin structure. In addition, the first major surface30aof the semiconductor chip30is exposed without being covered with the resin encapsulate50, so that it can easily discharge heat generated therefrom.

Although not shown, an insulating tape or a copper layer may be attached, as a closure means, to the first major surface30aof the semiconductor chip30in such a fashion that it covers the through hole12of the circuit board10. Where the insulating tape is used as the closure means, it is adapted to protect the first major surface30aof the semiconductor chip30from external damage. On the other hand, where the copper layer is used as the closure means, it is adapted to improve the heat discharge performance of the semiconductor chip30.

A plurality of conductive balls60made of tin (Sn), lead (Pb), or an alloy thereof are fused on the ball lands18bprovided at the first major surface11aof the resin substrate17, respectively, in order to allow the semiconductor package to be subsequently mounted on a mother board (not shown).

The circuit pattern18formed on the second major surface11bof the resin substrate17may also be provided with a plurality of ball lands18b, as in a semiconductor package104illustrated inFIG. 4. As shown inFIG. 4, the ball lands18bformed on the second major surface11bof the resin substrate17are not covered with the cover coat19covering the associated circuit pattern18in such a fashion that they are open. This means that a plurality of semiconductor packages having the above mentioned structure can be laminated together. That is, the lamination of a number of semiconductor packages can be achieved under the condition in which a plurality of conductive balls60are additionally fused on the ball lands18bformed at the second major surface11bof the resin substrate17in the semiconductor package105ofFIG. 5. An exemplary stack1040of such laminated (i.e., stacked) semiconductor packages104is illustratedFIG. 5A.

FIGS. 6A and 6Bare a top view and a bottom view respectively illustrating a circuit board strip used in the fabrication of the semiconductor package according to the present invention. Now, the structure of the circuit board strip will be described in brief, with reference toFIGS. 6A and 6B. InFIGS. 6A and 6B, elements respectively corresponding to those inFIGS. 1 to 5are denoted by the same reference numerals.

As shown inFIGS. 6A and 6B, the circuit board strip, which is denoted by the reference numeral10-1, includes a main strip16comprising a resin substrate17, circuit patterns18, and cover coats19. The resin substrate17has a substantially rectangular plate structure having a first major surface11a(FIG. 6B) and a second major surface11b(FIG. 6A). The main strip16is divided into a plurality of sub-strips14aligned together in the longitudinal direction of the main strip16by a plurality of main slots15. Main slots15extend through resin substrate17at a side of each sub-strip14. Sub-strips14extend to a desired length in a direction transverse to the longitudinal direction of the main strip16while being uniformly spaced apart from one another in the longitudinal direction of the main strip16. A plurality of through holes12, which are adapted to receive semiconductor chips (not shown) therein, respectively, are formed at each sub strip14in such a fashion that they are arranged in the form of a matrix array. Each sub strip14is divided by sub slots13having a desired length into a rectangular matrix of strip portions, each of which corresponds to a unit circuit board10ofFIGS. 1–5. Each unit circuit board10in each sub strip14includes an associated one of the through holes12provided at the sub strip14.

The sub slots13and main slots15are formed through the resin substrate17.

In each unit circuit board10of circuit board strip10-1, the circuit patterns18are formed on the first and second major surfaces11aand11bof the resin substrate17between the through hole12and the sub slots13. The circuit patterns18are typically comprised of a copper thin film.

In each unit circuit board10, the cover coats19are coated over the exposed surfaces of the circuit patterns18and resin substrate17in order to protect the circuit patterns18from the external environment. The cover coats19are typically made of a polymeric resin.

One circuit pattern18of each unit circuit board is provided with a plurality of bond fingers18ato be subsequently connected with a semiconductor chip whereas the other circuit pattern18of the unit circuit board is provided with a plurality of ball lands18bon which conductive balls are to be subsequently fused, respectively. The bond fingers18aand ball lands18bare externally open through the associated cover coats19, respectively.

As shown inFIG. 6A, the circuit pattern18formed on the second major surface lib of the resin substrate17may have both the bond fingers18aand the ball lands18b. Alternatively, the ball lands18bmay be provided only at the first major surface11aof the resin substrate17, as shown inFIG. 6B. Each bond finger18ais electrically connected with a ball land18bby conductive via (not shown) through resin substrate17. Although the ball lands18bhave been illustrated as being arranged along two lines, as shown inFIGS. 6A and 6B, they may be arranged along three through five lines. It will be appreciated by those persons skilled in the art that such an arrangement is optional. In other words, the present invention is not limited by the number of lines on which the ball lands18bare arranged.

FIGS. 7A to 7Fillustrate a semiconductor package fabricating method according to the present invention. Now, the fabrication method will be described with reference toFIGS. 7A to 7F.

In accordance with the semiconductor package fabricating method of the present invention, a circuit board strip, which may have the structure ofFIG. 6Aor6B, is used in order to achieve a simultaneous fabrication of a number of semiconductor packages. The following description will be made in conjunction with the case in which the circuit board strip ofFIG. 6Aor6B is used. For the simplicity of description, the illustration of the sub slots13that are along the four edges of each rectangular unit circuit board10of strip10-1are omitted.

In accordance with the fabricating method of the present invention, a circuit board strip, which is the circuit board strip10ofFIG. 6Aor6B, is first prepared, as shown inFIG. 7A.

Thereafter, a semiconductor chip30is inserted into each of the through holes12of the circuit board strip10, respectively, in such a fashion that the input/output pads31of each semiconductor chip30are oriented in the same direction as the bond fingers18aformed on the circuit board strip10.

Prior to the insertion of the semiconductor chips30, closure members70are attached to the lower surface of the circuit board strip10in such a fashion that each of them covers an associated one of the through holes12, as shown inFIG. 7B. In this case, each semiconductor chip30, which is subsequently received in an associated one of the through holes12, is seated on an associated one of the closure members70at the first major surface30athereof.

For the closure members70, insulating tapes may be used. Ultraviolet tapes may be used which can be easily peeled using ultraviolet rays. Alternatively, heat sensitive tapes may be used. For the closure members70, copper layers exhibiting a superior heat discharge property also may be attached to the circuit board strip10. In such a case, the closure members70are not removed after the completion of the package fabrication.

Alternatively, the closure members70may be attached to the circuit board strip10-1in such a fashion that they cover the entire lower surface of the circuit board strip10-1. This will be described in more detail, in conjunction withFIGS. 8A and 8B.

In order to electrically connect the input/output pads31of each semiconductor chip30with the associated bond fingers18aof the circuit board strip10, conductive wires, such as gold wires or aluminum wires, or leads extending from respective bond fingers18aare then electrically connected, as connection means40, between the input/output pads31and the associated bond fingers18a, respectively, as shown inFIG. 7C.

Subsequently, a resin encapsulate50is formed using an encapsulating resin, such as an epoxy molding compound or a liquid encapsulating resin, in such a fashion that it encapsulates the entire upper surface of each semiconductor chip30, the entire upper surface of the circuit board strip10, and the connection means40, as shown inFIG. 7D. Alternatively, the resin encapsulate50may be formed in such a fashion that it partially encapsulates desired upper surface portions of the circuit board strip10while completely encapsulating the upper surface of each semiconductor chip30and the connection means40. The encapsulating extent of the resin encapsulate50is optional.

The encapsulating process will be described in more detail, in conjunction withFIG. 9.

Thereafter, a plurality of conductive balls60are fused on the ball lands18bprovided at the lower surface of the circuit board strip10in order to allow each unit circuit board of the circuit board strip10to be mounted to a mother board in a subsequent process, as shown inFIG. 7E.

In the case in which the circuit board strip10is provided with ball lands18bnot only at the lower surface thereof, but also at the upper surface thereof formed with the bond fingers18a, conductive balls60are also fused on the ball lands18bof that upper surface. In this case, a plurality of semiconductor packages can be laminated together in a subsequent process.

The fusing of the conductive balls60may be achieved using a variety of appropriate methods. For example, a screen printing method may be used. In accordance with this screen printing method, a sticky flux exhibiting a high viscosity is first applied, in the shape of dots, to the ball lands18b. Conductive balls60are then temporarily bonded to the flux dots, respectively. The resultant circuit board strip10is subsequently put into a furnace so that the conductive balls60are fused on the associated ball lands18b, respectively.

Finally, the circuit board strip10is then singulated into individual semiconductor packages, each corresponding to one unit circuit board, using a desired singulation tool80, as shown inFIG. 7F.

In the singulation process, the singulation tool80(e.g., a saw) passes through regions defined between adjacent sub slots (not shown).

Removal of the closure members70may be conducted, to externally expose respective first major surfaces30aof the semiconductor chips30, before or after a formation of input/output terminals achieved by the fusing of the conductive balls on the ball lands18b, or after the singulation process. It is also possible to deliver the semiconductor packages in a state in which the closure members70are not removed, for example, where the closure member is made of a copper layer.

Where the resin encapsulate50is formed to completely encapsulate the entire upper surface of the circuit board strip10, the singulation processes for the resin encapsulate50and the circuit board strip10are simultaneously conducted. In this case, semiconductor packages having a structure shown inFIG. 1are produced.

FIGS. 8A and 8Bare bottom views each illustrating another attaching method for the closure members usable in the semiconductor package fabricating method according to the present invention.

In accordance with the attaching method ofFIG. 8A, a plurality of closure member strips are used, each of which provides in interconnected form the closure member70for each unit circuit board10of one sub strip14of the circuit board strip10-1. That is, the closure member strips are individually attached to the sub-strips14of the circuit board strip10-1. In this case, it is preferred that each closure member strip be arranged in such a fashion that it covers the main slot15formed at one side of the sub strip covered therewith.

The reason why each closure member strip has the above mentioned arrangement is to achieve an easy removal of the closure members70. That is, the closure members70of each closure member strip can be easily detached from the associated sub strip14of the circuit board strip10-1by inserting a planar bar (not shown) into the main slot15formed at one side of the sub strip14, thereby pushing the closure member strip in such a fashion that it is detached from the sub strip14. At this time, the planar bar moves in a direction from the second major surface11bof the circuit board strip10-1to the first major surface11a.

In accordance with the attaching method ofFIG. 8B, a single closure member strip is used which provides in interconnected form a closure member70for each unit circuit board10of all sub-strips14of the circuit board strip10-1having small singulation apertures or slits71at a region corresponding to each main slot15of the circuit board strip10-1. In this case, the closure members70for all sub-strips14are simultaneously attached to those sub-strips14.

Similar to the case ofFIG. 8A, the reason why the closure member strip has the above mentioned arrangement in the case ofFIG. 8Bis to achieve an easy removal of the closure members70. That is, the closure members70of the closure member strip can be easily detached from the circuit board strip10by inserting a planar bar (not shown) into each main slot15of the circuit board strip10, thereby pushing the closure member strip, in particular, the portion thereof formed with the singulation apertures71, in such a fashion that it is detached from the circuit board strip10. In this case, the closure member strip utilizes an easy singulation configuration, applied to the technical field of postage-stamps, using small singulation apertures.

FIG. 9illustrates an encapsulating method usable in the semiconductor package fabricating method according to the present invention.

In accordance with the encapsulating method shown inFIG. 9, a mold is used which includes an upper mold91having cavities93and gates94, and a lower mold92. First, the circuit board strip10is interposed between the upper and lower molds91and92in such a fashion that the second major surface30aof each semiconductor chip30faces an associated one of the cavities93while facing an associated one of the gates94at the central portion thereof.

An encapsulating resin is then injected into each cavity93of the upper mold91through an associated one of the gates94in such a fashion that it flows outwardly from the central portion of the second major surface30aof each semiconductor chip30along the second major surface30a. Thus, each semiconductor chip30is encapsulated. In accordance with this encapsulating method, it is possible to minimize a wire sweeping phenomenon occurring during the encapsulating process, as compared to conventional encapsulating methods in which the encapsulation proceeds from one side of the circuit board. The reason why a minimized wire sweeping phenomenon occurs in accordance with the present invention is because a maximum pressure of the encapsulating resin is applied to the central portion of the second major surface of each semiconductor chip while being gradually reduced toward the peripheral portion of the second major surface where wires are arranged.

As apparent from the above description, in accordance with the present invention, a circuit board is used which has a through hole of a desired size adapted to receive a semiconductor chip, thereby allowing the thickness of the semiconductor chip to be offset by the thickness of the circuit board. Accordingly, it is possible to fabricate semiconductor packages having a super-thin structure.

In accordance with the present invention, the semiconductor chip is outwardly exposed at one major surface thereof without being encapsulated by an encapsulate. Accordingly, heat generated from the semiconductor chip can be easily discharged into the atmosphere. This results in an improvement in the thermal and electrical performance of the semiconductor chip.

In accordance with the present invention, the circuit board may be completely encapsulated at one major surface thereof by an encapsulate. In this case, it is possible to effectively prevent a bending phenomenon of the circuit board.

In addition, the use of closure members during the fabrication of semiconductor packages according to the present invention achieves an easy encapsulating process. For such closure members, closure member strips may be used, each of which has closure members for one sub strip of a circuit board strip. In this case, the closure member strips are individually attached to the sub-strips of the circuit board strip. Alternatively, a single closure member strip may be used which has closure members for all sub-strips of the circuit board strip while having small singulation apertures or slits. By virtue of such a single closure member strip or closure member strips, an easy removal of closure members is achieved.

Also, the encapsulating process involved in the fabrication of semiconductor packages is conducted in such a fashion that it proceeds from the second major surface of each semiconductor chip in accordance with the present invention. Accordingly, it is possible to achieve a uniform encapsulation while suppressing the occurrence of a wire sweeping phenomenon.

Other embodiments of semiconductor packages and method of making them are disclosed in U.S. patent application Ser. No. 09/566,069, which was filed with the U.S. Patent and Trademark Office on May 5, 2000 and issued as U.S. Pat. No. 6,515,356 on Feb. 4, 2003, and in U.S. patent application Ser. No. 09/574,006, which was filed on May 19, 2000, and issued as U.S. Pat. No. 6,501,184 on Dec. 31, 2002. Both of these applications are incorporated herein by reference in their entireties.