Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods

Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

BACKGROUND

I. Field of the Disclosure

The field of the disclosure relates to integrated circuit (IC) packages, and more particularly to providing decoupling capacitance in a power distribution network (PDN) of the IC package for reducing current-resistance (IR) drop and voltage droop.

Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are typically packaged in an IC package, also called a “semiconductor package” or “chip package.” The IC package includes a package substrate and one or more IC chips or other electronic modules mounted to the package substrate to provide electrical connectivity to the IC chips. For example, an IC chip in an IC package may be a system-on-a chip (SoC). The IC chips are electrically coupled to other IC chips and/or to other components in the IC package through electrical coupling to metal lines in the package substrate. The IC chips can also be electrically coupled to other circuits outside the IC package through electrical connections of external metal interconnects (e.g., solder bumps) of the IC package.

High-performance compute chips in IC packages require effective power distribution networks (PDN) to distribute power to the circuits and other components in the IC chip efficiently. For example, an IC package may include a separate power management chip (PMC) that includes voltage regulator circuitry configured to distribute voltage to other IC chips in the IC package. Noise can occur in the PDN due to current-resistance (IR) drop between the PMC and a powered IC chip due to the series resistance and inductance in the PDN. Change in current draw from a powered IC chip to the PDN can induce noise in the PDN. If the magnitude of noise in the PDN exceeds a certain threshold, it alters the voltages delivered to the IC chips and its circuits below the acceptable values, which can cause malfunction of circuits. Even if a PDN supplies a voltage to the IC chips within tolerance, the PDN noise may still cause other problems. It can cause or appear as crosstalk on signal lines. Further, as PDN interconnects typically carry higher currents, high-frequency PDN noise has the potential of creating electromagnetic radiation interference, possibly causing other failures.

Thus, it is important to control noise in a PDN. In this regard, decoupling capacitors are employed to shunt PDN noise in the PDN to reduce its effect on the IC chips powered by the PDN. A decoupling capacitor can be mounted on a package substrate or embedded within a package substrate of an IC package to provide decoupling capacitance between the power source and IC chips. However, the electrical path connection between the decoupling capacitor and the IC chips has a parasitic inductance that can contribute to IR drop and PDN noise in an undesired manner.

SUMMARY OF THE DISCLOSURE

Aspects disclosed herein include integrated circuit (IC) packages employing an embedded-capacitor, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate. A RDL substrate is a substrate that includes a RDL layer that includes one or more metal redistribution lines supporting fan-out of metal interconnects. The embedded capacitor(s) can provide a decoupling capacitance for a power distribution network (PDN) in the IC package to reduce current-resistance (IR) drop as an example. Related fabrication methods are also disclosed. The IC package includes a package substrate and one or more IC chips electrically coupled to the package substrate. The package substrate includes one or more substrate layers with metal traces or lines embedded therein to provide electrical signal routing to and from the IC chip(s). The package substrate supports a PDN that carries electrical power signals at a given voltage for distribution to the IC chip(s) for operation. In exemplary aspects, the RDL substrate that supports the embedded capacitor is disposed between the IC chip(s) and the package substrate to minimize the distance between the embedded capacitor(s) and the IC chip(s). This can reduce the parasitic inductance in the power distribution lines between the embedded capacitor(s) and the IC chip(s) to reduces the IR drop in the PDN, which in turn reduces PDN noise. However, with the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections for an electrical interface between the package substrate and the IC chip(s). The IC chip(s) may have a high density of die interconnects that need to be electrically coupled to the package substrate. In this regard, the RDL substrate is provided to include a first outer RDL layer adjacent to the IC chip(s). The first outer RDL layer, being formed from a RDL process, allows the first outer RDL layer to support small pitch metal interconnects as well as provide fan-out capability. This allows the RDL substrate to provide enhanced connectivity compatibility with higher-density die interconnect IC chips while at the same time supporting an embedded capacitor closely located to the IC chip to minimize IR drop.

In an exemplary aspect, the RDL substrate can also include a second outer RDL layer that is adjacent to the package substrate. The metal interconnects of the second outer RDL layer can be formed with a different pitch from the metal interconnects of the first outer RDL layer for greater flexibility in providing a compatible package substrate in the IC package. For example, the die interconnect pitch of the IC chip may be much tighter (i.e., smaller) than the metal interconnect pitch of the package substrate. In this regard, the RDL layer can facilitate electrical coupling between the IC chip and a package substrate that have metal interconnects of different pitches for enhanced compatibility and ease in package fabrication processes. This can also provide a greater flexibility in choice of package substrates employed in the IC package to achieve pitch compatibility between the IC chip(s) and the package substrate for reduced cost, and/or ease in manufacturability, as examples.

In another exemplary aspect, the embedded capacitor can be included in a capacitor package that is embedded in the RDL substrate. In another exemplary aspect, to minimize the vertical interconnection path disturbance between the IC chip(s) and the package substrate in the vertical path of the embedded capacitor, through-silica-vertical interconnect accesses (vias) (TSVs) can be employed. The TSVs are disposed through the packaging dielectric of the embedded capacitor package to provide electrical through-connections between the IC chip(s) and the package substrate and/or to the embedded capacitor(s). In this manner, the RDL substrate is not limited to supporting vertical interconnects between the IC chip(s) and the package substrate only outside the area of the embedded capacitor package. In another exemplary aspect, the IC package also includes through-interconnects, such as through-mold-vias (TMV), that extend through the RDL substrate outside of the embedded capacitor package. These other through-interconnects provide pass-through electrical connections (e.g., input/output (I/O) connections) between the IC chip(s) and the package substrate. The RDL substrate can also more easily facilitate through-interconnects of a larger diameter and/or a higher aspect ratio that may be required due the increased distance between the package substrate and IC chip(s) due to the RDL substrate disposed therebetween.

In this regard, in one exemplary aspect, an integrated circuit (IC) package is provided. The IC package comprises a package substrate comprising a plurality of package substrate interconnects. The IC package also comprises an IC chip comprising a plurality of die interconnects. The IC package also comprises a RDL substrate disposed between the package substrate and the IC chip. The RDL substrates comprises a RDL layer comprising a plurality of redistribution metal lines each comprising a RDL interconnect coupled to a die interconnect among the plurality of die interconnects. The RDL substrate also comprises a substrate layer comprising a plurality of substrate interconnects. The RDL substrate also comprises a capacitor disposed between the RDL layer and the substrate layer. The IC package also comprises at least one via electrically coupled to a die interconnect among the plurality of die interconnects and the capacitor.

In another exemplary aspect, a method of fabricating an IC package is provided. The method comprises forming a package substrate comprising a plurality of package substrate interconnects. The method also comprises forming a RDL substrate on the package substrate, comprising forming a RDL layer comprising a plurality of redistribution metal lines each comprising a RDL interconnect, forming a substrate layer comprising a plurality of substrate interconnects, and disposing a capacitor between the RDL layer and the substrate layer. The method also comprises forming at least one via electrically coupled to the capacitor and configured to be electrically coupled to at least one die interconnect among a plurality of die interconnects of an IC chip. The method also comprises coupling at least one die interconnect among a plurality of die interconnects of the IC chip to at least one RDL interconnect among the plurality of redistribution metal lines.

In another exemplary aspect, RDL substrate is provided. The RDL substrate comprises a RDL layer comprising a plurality of redistribution metal lines each comprising a RDL interconnect. The RDL substrate also comprises a substrate layer comprising a plurality of substrate interconnects. The RDL substrate also comprises a dielectric layer comprising a dielectric material disposed between the RDL layer and the substrate layer. The RDL substrate also comprises a capacitor package embedded in the dielectric layer, the capacitor package comprising a capacitor. The RDL substrate also comprises a plurality of TSVs disposed through the capacitor package and electrically coupled to RDL interconnect among a plurality of RDL interconnects.

DETAILED DESCRIPTION

Aspects disclosed herein include integrated circuit (IC) packages employing an embedded-capacitor, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate. A RDL substrate is a substate that includes a RDL layer that includes one or more metal redistribution lines supporting fan-out of metal interconnects. The embedded capacitor(s) can provide a decoupling capacitance for a power distribution network (PDN) in the IC package to reduce current-resistance (IR) drop as an example. Related fabrication methods are also disclosed. The IC package includes a package substrate and one or more IC chips electrically coupled to the package substrate. The package substrate includes one or more substrate layers with metal traces or lines embedded therein to provide electrical signal routing to and from the IC chip(s). The package substrate supports a power distribution network (PDN) that carries electrical power signals at a given voltage for distribution to the IC chip(s) for operation. In exemplary aspects, the RDL substrate that supports the embedded capacitor is disposed between the IC chip(s) and the package substrate to minimize the distance between the embedded capacitor(s) and the IC chip(s). This can reduce the parasitic inductance in the power distribution lines between the embedded capacitor(s) and the IC chip(s) to reduces the IR drop in the PDN, which in turn reduce PDN noise. However, with the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections for an electrical interface between the package substrate and the IC chip(s). The IC chip(s) may have a high density of die interconnects that need to be electrically coupled to the package substrate. In this regard, the RDL substrate is provided to includes an outer RDL layer adjacent to the IC chip(s). The outer RDL layer, being formed from a RDL process, allows outer RDL layer to supports small pitch metal interconnects as well as provide fan-out capability. This allows the RDL substrate to provide enhanced connectivity compatibility with higher-density die interconnect IC chips while at the same time supporting an embedded capacitor closely located to the IC chip to minimize IR drop.

In this regard,FIG.1is a side view of an exemplary IC system100that includes an IC package102mounted to a printed circuit board (PCB)104. The IC package102includes an IC chip106supported by a package substrate108. The IC chip106and package substrate108are encapsulated by an over-molding material112in this example. The IC chip106can include circuitry for a specific type of application, such as a radio frequency (RF) transceiver or a computer-based system-on-a-chip (SoC) as non-limiting examples. The package substrate108supports the IC chip106of the IC package102and includes one or more metal layers of metal lines to provide electrical coupling paths between the IC chip106and the PCB104to support signaling between the IC chip106and other circuits external to the IC package102. The package substrate108can be formed from layers of organic material laminates with metal traces formed therein that are then laminated together as one example. The package substrate108can also include a RDL layer to support fan-out of electrical connections as another example. The IC chip106is electrically coupled to other external circuits through external package interconnects114, also referred to as “interconnect bumps,” formed on a bottom surface115of the package substrate108and electrically coupled to metal lines therein that are electrically coupled to the IC chip106.

As discussed in more detail below, the IC package102includes a capacitor-embedded, RDL substrate116(also referred to as “RDL substrate”) that is disposed between the IC chip106and the package substrate108. As discussed below, the RDL substrate116is a substrate that includes a RDL layer that includes one or more metal redistribution lines supporting fan-out of metal interconnects. The RDL substrate116includes one or more capacitors118. The capacitor(s)118can provide a decoupling capacitance for a PDN in the IC package102to reduce IR drop as an example. For example, a ground power conductor of the IC chip106may be coupled through one of its die interconnects120to a capacitor(s)118through the RDL substrate116to provide a decoupling capacitance for a power signal (e.g., a voltage signal) to ground. The RDL substrate116supports the embedded capacitor(s)118to be disposed between the IC chip106and the package substrate108to minimize the distance D1between the embedded capacitor(s)118and the IC chip106. Distance D1is shown inFIG.1as the distance between an outer surface122of the package substrate108and an active surface124of the IC chip106. For example, distance D1may be at least two (2) micrometers (μm). This can reduce the parasitic inductance in power distribution lines of a PDN between the embedded capacitor(s)118and the IC chip106to reduces the IR drop in the PDN, which in turn reduce PDN noise.

However, with the RDL substrate116disposed between the package substrate108and the IC chip106, the RDL substrate116needs to support through-interconnections for an electrical interface between the package substrate108and the IC chip106. The IC chip106may have a high density of die interconnects120that need to be electrically coupled to the package substrate108. In this regard, as shown inFIG.2illustrating a more detailed side view of the RDL substrate116ofFIG.1, the RDL substrate116is provided to include an outer RDL layer126. As shown inFIG.1, the outer RDL layer126is adjacent to the active surface124of the IC chip106. The outer RDL layer126, being formed from a RDL process in one example, includes a plurality of redistribution metal lines200each comprising a respective RDL interconnect202that can be coupled to a die interconnect120of the IC chip106when the IC chip106is disposed on the RDL substrate116. A solder bump can be formed and coupled to a RDL interconnect220to be coupled to a die interconnect120as an example. In this manner, the outer RDL layer126of the RDL substrate116can support small, high-density pitch die interconnects120of the IC chip106as well as provide fan-out capability between the die interconnects120and RDL substrate116. This in turn allows the RDL substrate116to provide enhanced connectivity compatibility with higher-density die interconnect IC chips, such as IC chip106, while at the same time supporting an embedded capacitor, such as capacitors118, more closely located to the IC chip106to minimize IR drop when coupled to a PDN in the IC package102.

With reference toFIG.2, the RDL substrate116includes the outer RDL layer126(shown as a top layer inFIG.2in the Z-axis direction) that includes redistribution metal lines200that can include a respective RDL interconnect202that can be coupled to a respective die interconnect120of the IC chip106(shown inFIG.1). With reference back toFIG.1, the package substrate108includes a plurality of package substrate interconnects128in a package substrate layer130that can be electrically coupled to the RDL substrate116to provide an electrical interface between the package substrate108and the IC chip106through the RDL substrate116. With reference back toFIG.2, the RDL substrate116also includes a substrate layer204that is a bottom layer located beneath the RDL layer126. The substrate layer204includes the substrate interconnects206that are configured to be coupled to respective package substrate interconnects128in a top, adjacent package substrate layer130of the package substrate108as shown inFIG.1. This provides an electrical interface between the package substrate108and the RDL substrate116. An electrical interface is provided in the RDL substrate116by an electrical coupling between RDL interconnects202in the RDL layer126and substrate interconnects206in the substrate layer204through respective vias208that extend through a dielectric layer210between the RDL layer126and the substrate layer204. In this regard, the vias208can be considered through-mold vias (TMVs) that extend through the dielectric layer210. For example, the vias208may be copper pillars. The vias208extend through the dielectric layer210of the RDL substrate116outside the area of a capacitor package212. The substrate interconnects206can be coupled to a respective package substrate interconnect128of the package substrate108as shown inFIG.1. The external package interconnects114can be electrically coupled to package substrate interconnects128in the package substate layer130of the package substrate108.

In this manner, an electrical interface is provided in the IC package102inFIG.1to the IC chip106. The electrical interface includes the external package interconnects114and their electrical coupling to package substrate interconnects128, substrate interconnects206of the RDL substrate116, vias208and RDL interconnects202of the RDL substrate116, and to the die interconnects120of the IC chip106(inFIG.1).

In this example of the RDL substrate116inFIG.2, the capacitors118are included in the capacitor package212. The capacitor package212includes a dielectric layer214comprising a dielectric material disposed between the RDL layer126and the substrate layer204. The capacitors118are embedded in the dielectric layer214of the capacitor package212. The capacitor package212is embedded in the dielectric layer210of the RDL substrate116. The capacitor package212can be formed as a separate package, such as a chiplet, as will be discussed in more detail below. In this example RDL substrate116inFIG.2, to provide an electrical interface between the IC chip106and the capacitors118in the capacitor package212, the RDL layer126of the package substrate108also includes redistribution metal lines216that can include respective RDL interconnects218that can be coupled to a respective die interconnect120of the IC chip106(seeFIG.1). However, in this example, the RDL interconnects218are coupled to the capacitors118through vias220. For example, the vias220can be through-silicon-vias (TSVs)222that extend through the dielectric layer214of the capacitor package212. In this manner, the redistribution metal lines216and their respective RDL interconnects218of the RDL layer126of the RDL substrate116provide an interface between the capacitors118and the IC chip106to, for example, provide a decoupling capacitance to the PDN in the IC chip106. For example, the capacitors118may be coupled to a ground node in the PDN in the IC chip106coupled to the die interconnects120that are coupled to the RDL interconnects218(see alsoFIG.1).

Also, with reference toFIG.2, note that the substrate layer204of the RDL substrate116inFIG.2can also be provided as a second RDL layer224. The second RDL layer224can be being formed from a RDL process in one example. The second RDL layer224can include a plurality of redistribution metal lines226each comprising a respective RDL interconnect228that can be coupled to a package substrate interconnect128of the package substrate108when the RDL substrate116is disposed on the package substrate108. The vias208,220can be coupled to a second RDL interconnect228in the second RDL layer224through a RDL deposition and under bump metallization (UBM) formation as one example. A solder bump can be formed and coupled to a second RDL interconnect228to couple a corresponding via208,220to a second RDL interconnect228in the second RDL layer224. The vias208,220could also be copper pillars that are formed in direct contact with the second RDL layer228as another alternative. This allows the second RDL layer224of the RDL substrate116to support fan-out connections to the package substrate interconnect128of the package substrate108. This may allow the RDL substrate116to provide further enhanced connectivity compatibility with different package substrates108, while at the same time supporting an embedded capacitor, such as capacitors118, more closely located to the IC chip106to minimize IR drop when coupled to a PDN in the IC package102. For example, package substrates that are less costly to manufacture may only support substrate interconnects that have a larger pitch. As alternative, note that substrate layer204of the RDL substrate116inFIG.2can also be provided as a laminate substrate comprising a laminate layer of organic material that does not include RDLs.

FIG.3is a side view of another RDL substrate316that can be provided as the RDL substrate116in the IC package102inFIGS.1and2. The RDL substrate316includes additional exemplary features that will now be discussed. Common elements between the RDL substrate316inFIG.3and the RDL substrate116inFIGS.1and2are shown with common element numbers.

As shown inFIG.3, a passivation layer302can be provided in the RDL substrate316and disposed between the capacitor package212and the RDL layer126of the RDL substrate316. Providing the passivation layer302of dielectric material may provide for enhanced alignment between top surfaces304of the TSVs222and the redistribution metal lines216for reduced resistance and thus reduced IR drop through the capacitors118. The passivation layer302can be patterned and opened to allow the redistribution metal lines216to be formed in the openings for enhanced alignment between the TSVs222and the redistribution metal lines216, as will be later described in more detail. In this example, the TSVs222extend through the passivation layer302to be in contact with the redistribution metal lines216of the RDL layer126.

With continued reference toFIG.3, note that the vias220can be employed to provide connectivity to the capacitors118in the capacitor package212and the RDL interconnects218in the RDL layer126. Also note that the vias220may also be fabricated to pass through the capacitor package212and its dielectric layer214as through-vias to be coupled to a substrate interconnect206to provide coupling to the package substrate108inFIG.1. In this regard, the vias220can be provided as TSVs222as previously discussed to extend through the capacitor package212. This allows the vertical path space in the Z-axis direction in the path of the capacitor package212to allow connectivity between the RDL layer126and the substrate layer204to minimize the capacitor package's212vertical path interconnection disturbance in the RDL substrate116. Providing the vias220as TSVs222may allow a greater height H1to width W1aspect ratio to allow the RDL substrate316to support a greater density of vias220to provide connectivity between the IC chip106, the RDL substrate316, and the package substrate108. This may be particularly advantageous since the RDL substrate316is provided with its RDL layer126to support a fan-out of the RDL interconnects202,218, which in turn may support interconnection compatibility with an IC chip106having a higher density of die interconnects120. Also, the overall height width H2of the RDL substrate316to support the capacitor package212and the embedded capacitors118may require a certain desired height H1-to-width W1aspect ratio of the TSVs222to support the density of interconnections provided in the RDL substate316. For example, the aspect ratio of height H1to width W1of the TSVs222may be at least 2.0. Also, the vias208may also be provided as TSVs, and may also include a higher H1-to-width W2aspect ratio of at least 1.0 for the same reasons as discussed above for the TSVs222.

As discussed above, providing the RDL substrates116,316with a RDL layer126allows fan-out of the redistribution metal lines200,216to support a higher density of their respective RDL interconnects202,218. For example, as shown inFIGS.2and3in the RDL substrates116,316, the redistribution metal lines200are fanned-out outside a vertical path V1of their respective RDL interconnects202. Similarly, as shown inFIGS.2and3in the RDL substrates116,316, the redistribution metal lines216are fanned-out outside a vertical path V2of their respective RDL interconnect218. This allows the die interconnects120in the IC chip106inFIG.1to have a tighter (i.e., smaller) pitch P1than a pitch P2of the substrate interconnects206in the substrate layer204. The pitch P3of the RDL interconnects202of the RDL layer126of the RDL substrates116,316may be the same as a pitch P4of the of the package substrate interconnects128of the package substate108. The pitch P2of the substrate interconnects206of the substrate layer204of the RDL substrates116,316may be configured to be compatible with the pitch P4of the package substrate interconnects128of the package substate108as previously discussed. The pitch P2of the substrate interconnects206of the substrate layer204of the RDL substrates116,316may be the same as the pitch P4of the of the package substrate interconnects128of the package substate108.

Also, note that the RDL substrates116,316could also be configured to act as a interposer between two or more IC chips, like the IC chip106, that are provided in an IC package, like the IC package102inFIG.2. Additional IC chips could be provided in the IC package102that include components like the IC chip106described above. The RDL substrate116,316would be disposed between the package substrate108and the additional IC chip(s). The RDL substrates116,316could further include additional, second redistribution metal lines each including additional, second RDL interconnects coupled to a die interconnect of an additional IC chip(s). One or more of the additional, second redistribution metal lines could be coupled to one or more of the redistribution metal lines200in the RDL substrate116to electrically the IC chip106to another IC chip(s).

FIG.4is a flowchart illustrating an exemplary process400of fabricating an IC package that includes a capacitor-embedded, RDL substrate disposed between an IC chip(s) and package substrate, including, but not limited to, the IC package102inFIG.1and its RDL substrate inFIGS.1-3. The exemplary process400will be referenced inFIG.2with reference to the IC package102inFIG.2, and the RDL substrates116,316inFIGS.2and3.

In this regard, a first step in the fabrication process400to fabricate the IC package102can be forming a package substrate108comprising a plurality of package substrate interconnects128(block402inFIG.4). A next step in the fabrication process400to fabricate the IC package102can be forming a RDL substrate116,316on the package substrate108(block404inFIG.4). The process of forming the RDL substate116,316, can include forming a RDL layer126comprising a plurality of redistribution metal lines200,216each comprising a RDL interconnect202,218(block406inFIG.4). The process of forming the RDL substate116,316, can also include forming a substrate layer204comprising a plurality of substrate interconnects206(block408FIG.4). The process of forming the RDL substate116,316, can also include disposing a capacitor118between the RDL layer126and the substrate layer204(block410inFIG.4). A next step in the fabrication process400to fabricate the IC package102can be forming at least one via220,222electrically coupled to the capacitor118and configured to be electrically coupled to at least one die interconnect120among a plurality of die interconnects120of the IC chip106(block412inFIG.4). A next step in the fabrication process400to fabricate the IC package102can be coupling at least one die interconnect120among the plurality of die interconnects120of the IC chip106to at least one RDL interconnect202,218among the plurality of redistribution metal lines200,216(block414inFIG.4).

An IC package that includes a capacitor-embedded, RDL substrate disposed between an IC chip(s) and package substrate, including, but not limited to, the IC package102inFIG.1and its RDL substrate inFIGS.1-3, can be fabricated in other fabrication processes. For example,FIGS.5A-5Gillustrate exemplary fabrication stages500A-500G of another exemplary process600inFIGS.6A-6Dof fabricating an IC package that includes a capacitor-embedded, RDL substrate disposed between an IC chip(s) and package substrate, including, but not limited to, the IC packages and RDL substrates inFIGS.1-3.FIGS.6A-6Dare a flowchart illustrating the exemplary process600of fabricating the IC package that includes a capacitor-embedded, RDL substrate disposed between an IC chip(s) and package substrate according to the exemplary fabrication stages500A-500G inFIGS.5A-5G. In the exemplary process600inFIGS.6A-6Dand according to the exemplary fabrication stages500A-500G inFIGS.5A-5G, as discussed below, a RDL layer of the RDL substrate of the IC package is formed before a capacitor package is embedded in the RDL substrate. The exemplary process600inFIGS.6A-6Dis discussed below with reference to the fabrication stages500A-500G inFIGS.5A-5G. The exemplary process600inFIGS.6A-6Dis also discussed with reference to the IC package102inFIG.1and the RDL substrates116,316inFIGS.2and3, as examples.

In this regard,FIG.5Aillustrates a first fabrication stage500A of the IC package102inFIG.1. In this fabrication stage500A, a carrier502is provided. The RDL layer224is formed on the carrier502to be provided in an eventually formed RDL substrate116,316(block602inFIG.6A). The carrier502is used to allow the RDL layer224and RDL substrate116,316of the IC package102to be formed before the capacitor package212is embedded in the RDL substrate116,316.FIG.5Billustrates a next fabrication stage500B of the IC package102inFIG.1. As shown in the next fabrication stage500B inFIG.5B, the vias208, which may be TMVs and that are outside of an area504where the capacitor package212will be disposed, are formed on the RDL layer224and in electrical contact with the redistribution metal lines226of the RDL layer224(block604inFIG.6A).

As shown in a next fabrication stage500C inFIG.5C, the capacitor package212is disposed on the RDL layer224to prepare the capacitor package212to be embedded in the eventually formed RDL substrate116,316that includes the RDL layer224(block606inFIG.6B). Note that the TSVs222are exposed through the passivation layer302through a separate process to fabricate the capacitor package212that is described with reference toFIGS.7A-8below. As shown in a next fabrication stage500D inFIG.5D, the dielectric layer210is then disposed over the vias208, the capacitor package212, and the exposed TSVs222as part of forming the RDL substrate (block608inFIG.6B). As shown in a next fabrication stage500E inFIG.5E, the dielectric layer210is ground down to a top surface505to expose top surfaces506,508of the vias208and the TSVs222to prepare these vias208and TSVs222for connection to the RDL layer126to be formed for the RDL substrate116,316(block610inFIG.6C). As shown in a next fabrication stage500F inFIG.5F, the RDL layer126is formed on the top surface505of the dielectric layer210that was ground down to form the RDL substrate116,316. The redistribution metal lines200,216are electrically coupled to the respective top surfaces506,508of the vias208and TSVs222as part of forming the RDL layer126(block612inFIG.6C). As shown in a next fabrication stage500G inFIG.5G, the IC chip106is then coupled to the RDL layer126of the RDL substrate116,316to form the IC package102(block614inFIG.6D).

FIGS.7A-7Cillustrate exemplary fabrication stages700A-700C of an exemplary process of fabricating the capacitor package212that can be embedded in the RDL substrate of an IC package, including, but not limited to, the IC packages102and RDL substrates116,316inFIGS.1-3and5G.FIG.8is a flowchart illustrating an exemplary process800of fabricating the capacitor package212according to the exemplary fabrication stages700A-700C inFIGS.7A-7C.FIGS.7A-7CandFIG.8will be discussed on conjunction.

In this regard, as shown in a fabrication stage700A inFIG.7A, the capacitors118and TSVs222are formed with the dielectric layer214disposed over the capacitors118and TSVs222(block802inFIG.8). As shown in a next fabrication stage700B inFIG.7B, the dielectric layer214is ground down to a top surface702to expose top surfaces704of the TSVs222. Then, a passivation layer302is disposed over the top surface702of the dielectric layer214and the TSVs222(block804inFIG.8). As shown in a next fabrication stage700C inFIG.7C, the passivation layer302is etched to expose the top surfaces704of the TSVs222to prepare same for electrical connection to the redistribution metal lines216of the RDL layer126of the RDL substrate116,316(block806inFIG.8).

FIGS.9A-9Hillustrate exemplary fabrication stages900A-900H of another exemplary process1000inFIGS.10A-10Dof fabricating an IC package that includes a capacitor-embedded, RDL substrate disposed between an IC chip(s) and package substrate, including, but not limited to, the IC packages and RDL substrates inFIGS.1-3.FIGS.10A-10Darea flowchart illustrating the exemplary process1000of fabricating the IC package that includes a capacitor-embedded, RDL substrate disposed between an IC chip(s) and package substrate according to the exemplary fabrication stages900A-900H inFIGS.9A-9H. In the exemplary process1000inFIGS.10A-10Dand according to the exemplary fabrication stages900A-900H inFIGS.9A-9H, as discussed below, a RDL layer of the RDL substrate of the IC package is formed before a capacitor package is embedded in the RDL substrate like in the process800inFIGS.8A-8Ddiscussed above. However, the passivation layer302is not included in the capacitor package312in the process1000inFIGS.10A-10D. The exemplary process1000FIGS.10A-10Dis discussed below with reference to the fabrication stages900A-900H inFIGS.9A-9H. The exemplary process1000FIGS.10A-10Dis also discussed with reference to the IC package102inFIG.1and the RDL substrates116,316inFIGS.2and3, as examples.

In this regard,FIG.9Aillustrates a first fabrication stage900A of the IC package102inFIG.1according to an alternative fabrication process. In this fabrication stage900A, a carrier902is provided. The RDL layer224is formed on the carrier902to be provided in an eventually formed RDL substrate116,316(block1002inFIG.10A). The carrier902is used to allow the RDL layer224and RDL substrate116,316of the IC package102to be formed before the capacitor package212is embedded in the RDL substrate116,316.FIG.9Billustrates a next fabrication stage900B of the IC package102inFIG.1. As shown in the next fabrication stage900B inFIG.9B, the vias208, which may be TMVs and that are outside of an area904where the capacitor package212will be disposed, are formed on the RDL layer224and in electrical contact with the redistribution metal lines226of the RDL layer224(block1004inFIG.10A). As shown in a next fabrication stage900C inFIG.9C, the capacitor package212is disposed on the RDL layer224to prepare the capacitor package212to be embedded in the eventually formed RDL substrate116,316that includes the RDL layer224(block1006inFIG.10A). Note that there is no passivation layer302included in the capacitor package212as described in the process above inFIGS.5A-8.

As shown in a next fabrication stage900D inFIG.9D, the dielectric layer210is then disposed over the vias208and the capacitor package212as part of forming the RDL substrate (block1008inFIG.10B). As shown in a next fabrication stage900E inFIG.9E, the dielectric layer210is ground down to a top surface906to expose top surfaces908,910of the vias208and the TSVs222to prepare these vias208and TSVs222for connection to the RDL layer126to be formed for the RDL substrate116,316(block1010inFIG.10B). As shown in a next fabrication stage900F inFIG.9F, the RDL layer126is formed on the top surface906of the dielectric layer210that was ground down to form the RDL substrate116,316. The redistribution metal lines200,216are electrically coupled to the respective top surfaces908,910of the vias208and TSVs222as part of forming the RDL layer126(block1012inFIG.10C).

As shown in a next fabrication stage900G inFIG.9G, the RDL substrate116,316disposed on the carrier902is flipped to prepare the carrier902to be removed (block1014inFIG.10D). As shown in a next fabrication stage900H inFIG.9H, the IC chip106is then coupled to the RDL layer126of the RDL substrate116,316to form the IC package102(block1016inFIG.10D).

FIGS.11A-11Lillustrate exemplary fabrication stages1100A-1100L of another exemplary process1200inFIGS.12A-12Fof fabricating an IC package that includes a capacitor-embedded, RDL substrate disposed between an IC chip(s) and package substrate, including, but not limited to, the IC packages and RDL substrates inFIGS.1-3.FIGS.12A-112Fare a flowchart illustrating the exemplary process1200of fabricating the IC package that includes a capacitor-embedded, RDL substrate disposed between an IC chip(s) and package substrate according to the exemplary fabrication stages1100A-1100L inFIGS.11A-11L. In the exemplary process1200inFIGS.12A-12Fand according to the exemplary fabrication stages1100A-1100L inFIGS.11A-11L, as discussed below, a RDL layer of the RDL substrate of the IC package is formed after a capacitor package is embedded in the RDL substrate. The exemplary process1200FIGS.12A-12Fis discussed below with reference to the fabrication stages1100A-1100L inFIGS.11A-11L. The exemplary process1200FIGS.12A-12Fis also discussed with reference to the IC package102inFIG.1and the RDL substrates116,316inFIGS.2and3, as examples.

As shown in a fabrication stage1100A inFIG.11A, the package substrate108of a carrier1102is started to be prepared. A carrier1102is provided, such as a laminate substrate, and a coating is disposed on the carrier1002through a light-to-heat conversion (LTHC) release layer1104(block1202inFIG.12A). As shown in a next fabrication stage1100B inFIG.11B, a laminated polyimide layer1106is disposed on the LTHC release layer1104(block1204inFIG.12A). As shown in a next fabrication stage1100C inFIG.11C, a seed layer1108(e.g., a TiCu layer) is disposed on the laminated polyimide layer1106to prepare for forming the vias208(block1206inFIG.12A). As shown in a next fabrication stage1100D inFIG.11D, a photoresist layer1110is disposed on the seed layer1108to prepare for the photoresist layer1110to be patterned to form openings1112as shown to form the vias208(block1208inFIG.12B). As shown in a next fabrication stage1100E inFIG.11E, the vias208are formed in the openings1112(block1210inFIG.12B). For example, the vias208can be copper pillars.

As shown in a next fabrication stage1100F inFIG.11F, the capacitor package212is then disposed in the area1114between the vias208to eventually become part of a fabricated RDL substrate116,316(block1212inFIG.12C). As shown in a next fabrication stage1100G inFIG.11G, a dielectric layer210is disposed on the vias208and capacitor package212(block1214inFIG.12D). As shown in a next fabrication stage1100H inFIG.11H, the dielectric layer210is ground down to a top surface1116to expose the top surfaces1118,1120of the vias208and the TSVs222of the capacitor package212(block1216inFIG.12D). As shown in a next fabrication stage1100I inFIG.11I, the RDL layer126is formed on the top surface1116of the dielectric layer210to form a portion of the RDL substrate116,316(block1218inFIG.12E). As shown in a next fabrication stage1100J inFIG.11J, the carrier1102is flipped and removed with the dielectric layer210with embedded capacitor package212and RDL layer126separated to prepare to form the second RDL layer224of the RDL substrate116,316(block1220inFIG.12E).

As shown in a next fabrication stage1100K inFIG.11K, the second RDL layer224of the RDL substrate116,316is formed to form the RDL substrate116,316(block1222inFIG.12E). As shown in a next fabrication stage11L inFIG.1L, the IC chip106is then coupled to the RDL layer126of the RDL substrate116,316to form the IC package102(block1224inFIG.12F).

It should be understood that that the terms “top,” “above,” “bottom,” below,” where used herein, are relative terms and are not meant to limit or imply a strict orientation. A “top” referenced element does not always be oriented to be above a “bottom” referenced element with respect to ground, and vice versa. An element referenced as “top” or “bottom” may be on top or bottom relative to that example only and the particular illustrated example. An element referenced as “above” or “below” another element does not have to be with respect to ground, and vice versa. An element referenced as “above” or “below” may be on above or below and to such other referenced element, relative to that example only and the particular illustrated example.

IC packages that include a RDL substrate with an embedded capacitor(s) disposed between an IC chip(s) and package substrate, including, but not limited to, the IC packages inFIGS.1-3,5G,9H, and11L, and according to any aspects disclosed herein, may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

FIG.13illustrates an exemplary wireless communications device1300that includes electrical components formed from one or more ICs1302, wherein any of the ICs1302can be included in an IC package1303. The IC package1303can include IC packages that include a RDL substrate with an embedded capacitor(s) disposed between an IC chip(s) and package substrate, including, but not limited to, the IC packages inFIGS.1-3,5G,9H, and11L, and according to any aspects disclosed herein.

The wireless communications device1300may include or be provided in any of the above referenced devices, as examples. As shown inFIG.13, the wireless communications device1300includes a transceiver1304and a data processor1306. The data processor1306may include a memory to store data and program codes. The transceiver1304includes a transmitter1308and a receiver1310that support bi-directional communications. In general, the wireless communications device1300may include any number of transmitters1308and/or receivers1310for any number of communication systems and frequency bands. All or a portion of the transceiver1304may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

The transmitter1308or the receiver1310may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for the receiver1310. In the direct-conversion architecture, a signal is frequency-converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the wireless communications device1300inFIG.13, the transmitter1308and the receiver1310are implemented with the direct-conversion architecture.

In the transmit path, the data processor1306processes data to be transmitted and provides I and Q analog output signals to the transmitter1308. In the exemplary wireless communications device1300, the data processor1306includes digital-to-analog converters (DACs)1312(1),1312(2) for converting digital signals generated by the data processor1306into the I and Q analog output signals, e.g., I and Q output currents, for further processing.

Within the transmitter1308, lowpass filters1314(1),1314(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the prior digital-to-analog conversion. Amplifiers (AMPs)1316(1),1316(2) amplify the signals from the lowpass filters1314(1),1314(2), respectively, and provide I and Q baseband signals. An upconverter1318upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals through mixers1320(1),1320(2) from a TX LO signal generator1322to provide an upconverted signal1324. A filter1326filters the upconverted signal1324to remove undesired signals caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA)1328amplifies the upconverted signal1324from the filter1326to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch1330and transmitted via an antenna1332.

In the receive path, the antenna1332receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch1330and provided to a low noise amplifier (LNA)1334. The duplexer or switch1330is designed to operate with a specific receive (RX)-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by the LNA1334and filtered by a filter1336to obtain a desired RF input signal. Downconversion mixers1338(1),1338(2) mix the output of the filter1336with I and Q RX LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator1340to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs1342(1),1342(2) and further filtered by lowpass filters1344(1),1344(2) to obtain I and Q analog input signals, which are provided to the data processor1306. In this example, the data processor1306includes analog-to-digital converters (ADCs)1346(1),1346(2) for converting the analog input signals into digital signals to be further processed by the data processor1306.

In the wireless communications device1300ofFIG.13, the TX LO signal generator1322generates the I and Q TX LO signals used for frequency upconversion, while the RX LO signal generator1340generates the I and Q RX LO signals used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A TX phase-locked loop (PLL) circuit1348receives timing information from the data processor1306and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from the TX LO signal generator1322. Similarly, an RX PLL circuit1350receives timing information from the data processor1306and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from the RX LO signal generator1340.

Implementation examples are also described in the following numbered clauses:1. An integrated circuit (IC) package, comprising.a package substrate comprising a plurality of package substrate interconnects;an IC chip comprising a plurality of die interconnects;a redistribution layer (RDL) substrate disposed between the package substrate and the IC chip, the RDL substrate comprising:a RDL layer comprising a plurality of redistribution metal lines each comprising a RDL interconnect coupled to a die interconnect among the plurality of die interconnects;a substrate layer comprising a plurality of substrate interconnects; anda capacitor disposed between the RDL layer and the substrate layer; andat least one vertical interconnect access (via) electrically coupled to a dieinterconnect among the plurality of die interconnects and the capacitor.2. The IC package according to clause 1, wherein the substrate layer comprises a second RDL layer comprising a plurality of second redistribution metal lines each comprising a second RDL interconnect.3. The IC package according to clause 2, further comprising at the least one second via coupled to a die interconnect among the plurality of die interconnects and at least one substrate interconnect among the plurality of substrate interconnects in the substrate layer.4. The IC package according to any of clauses 1 to 3, further comprising a passivation layer disposed between the capacitor and the RDL layer.5. The IC package according to any of clauses 1 to 4, wherein the at least one via comprises at least one through-silicon-via (TSV) disposed through the RDL substrate and electrically coupled to a redistribution metal line among the plurality of redistribution metal lines coupled to the die interconnect.6. The IC package according to clause 5, wherein the aspect ratio of height to width of the at least one TSV is at least 2.0.7. The IC package according to any of clauses 1 to 6, further comprising a plurality of second vias disposed through the RDL substrate and electrically coupled to a RDL interconnect among a plurality of RDL interconnects in the RDL layer and a substrate interconnect among the plurality of substrate interconnects in the substrate layer.8. The IC package according to clause 7, wherein the aspect ratio of height to width of the plurality of second vias is at least 1.0.9. The IC package according to any of clauses 1 to 8, further comprising:a dielectric layer comprising a dielectric material disposed between the RDL layer and the substrate layer; anda capacitor package embedded in the dielectric layer, the capacitor package comprising the capacitor.10. The IC package according to clause 9, wherein the at least one via comprises at least one through-silicon-via (TSV) disposed through the capacitor package and electrically coupled to a redistribution metal line among the plurality of redistribution metal lines coupled to the die interconnect.11. The IC package according to clause 9, further comprising a plurality of second vias disposed through the RDL substrate and electrically coupled to a RDL interconnect among a plurality of RDL interconnects in the RDL layer and a substrate interconnect among the plurality of substrate interconnects in the substrate layer;wherein the plurality of second vias are disposed through the dielectric layer of the RDL substrate outside of the capacitor package.12. The IC package according to any of clauses 1 to 11, wherein at least one redistribution metal line among the plurality of redistribution metal lines is fanned-out outside a vertical path of its respective RDL interconnect.13. The IC package according to clause of any of clauses 1 to 12, wherein:the plurality of die interconnects have a first pitch;the plurality of substrate interconnects in the substrate layer have a second pitch greater than the first pitch; andthe plurality of package substrates interconnects have the second pitch.14. The IC package according to clause 13, further comprising a plurality of second vias disposed through the RDL substrate and electrically coupled to a RDL interconnect among a plurality of RDL interconnects in the RDL layer and a substrate interconnect among the plurality of substrate interconnects in the substrate layer coupled to a package substrate interconnect among the plurality of package substrate interconnects.15. The IC package according to any of clauses 1 to 14, wherein:the package substrate further comprises a first outer surface, the plurality of package substrate interconnects disposed through the first outer surface;the IC chip further comprises an active surface, the plurality of die interconnects disposed through the active surface; anda distance between the first outer surface and the active surface is at least two (2) micrometers (μm).16. The IC package according to any of clauses 1 to 15 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer, a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.17. A method of fabricating an IC package, comprising:forming a package substrate comprising a plurality of package substrate interconnects;forming a redistribution layer (RDL) substrate on the package substrate, comprising:forming a RDL layer comprising a plurality of redistribution metal lines each comprising a RDL interconnect;forming a substrate layer comprising a plurality of substrate interconnects; anddisposing a capacitor between the RDL layer and the substrate layer;forming at least one vertical interconnect access (via) electrically coupled to the capacitor and configured to be electrically coupled to at least one die interconnect among a plurality of die interconnects of the IC chip; andcoupling at least one die interconnect among a plurality of die interconnects of an IC chip to at least one RDL interconnect among the plurality of redistribution metal lines.18. The method according to clause 17, wherein forming the substrate layer comprises forming a second RDL layer comprising a plurality of second redistribution metal lines each comprising a second RDL interconnect; andfurther comprising:coupling at least one package substrate interconnect among the plurality of package substrate interconnects to at least one second RDL interconnect among a plurality of second RDL interconnects; anddisposing the capacitor between the RDL layer and the substrate layer comprises disposing the capacitor between the RDL layer and the second RDL layer.19. The method according to any of clauses 17 to 18, further comprising forming at least one second via electrically coupled to at least one die interconnect among the plurality of die interconnects and at least one substrate interconnect among the plurality of substrate interconnects.20. The method according to clause 19, wherein forming the at least one second via further comprises forming the least one second via outside a vertical path of the capacitor.21. The method according to any of clauses 17 and 19-20, wherein forming the substrate layer comprises forming a second RDL layer on the package substrate comprising a plurality of second redistribution metal lines each comprising a second RDL interconnect, to electrically couple the second RDL interconnect among the plurality of second redistribution metal lines to at least one second RDL interconnect among the second RDL interconnects.22. The method according to clause 21, further comprising forming a passivation layer above a first side of the capacitor opposite a second side of the capacitor adjacent to the second RDL layer.23. The method according to any of clauses 19 to 22, further comprising forming a dielectric layer comprising a dielectric material over the at least one via, the at least one second via, and the capacitor.24. The method according to clause 23, further comprising grinding down a surface of the dielectric layer to expose a top surface of each of the at least one via from the dielectric layer.25. The method according to clause 24, further comprising forming the RDL layer above the dielectric layer on a first side of the dielectric layer opposite the second RDL layer to electrically couple the at least one via to at least one RDL interconnect among the plurality of redistribution metal lines.26. The method according to any of clauses 17 to 25, further comprising:providing a carrier; andforming a plurality of second vias on the carrier.27. A redistribution layer (RDL) substrate, comprising:a RDL layer comprising a plurality of redistribution metal lines each comprising a RDL interconnect;a substrate layer comprising a plurality of substrate interconnects,a dielectric layer comprising a dielectric material disposed between the RDL layer and the substrate layer;a capacitor package embedded in the dielectric layer, the capacitor package comprising a capacitor; anda plurality of through-silicon-vertical interconnect accesses (vias) (TSVs) disposed through the capacitor package and electrically coupled to RDL interconnect among a plurality of RDL interconnects.28. The RDL substrate according to clause 27, wherein:the capacitor package further comprises a metal layer comprising at least one metal line coupled to the capacitor; andat least one TSV among the plurality of TSVs is coupled to the at least one metal line coupled to the capacitor.29. The RDL substrate according to clause 27, wherein at least one TSV among the plurality of TSVs is coupled to at least one substrate interconnect among the plurality of substrate interconnects in the substrate layer.30. The RDL substrate according to any of clauses 27 to 29, wherein the substrate layer comprises a second RDL layer comprising a plurality of second redistribution metal lines each comprising a second RDL interconnect.31. The RDL substrate according to any of clauses 27 to 30, wherein the RDL layer comprises an outer surface and the RDL interconnects of the plurality of redistributed metal lines are disposed through the outer surface.32. The RDL substrate according to any of clauses 27 to 31, further comprising a passivation layer disposed between the capacitor package and the RDL layer.33. The RDL substrate according to clause 32, wherein the plurality of TSVs extend through the passivation layer.34. The RDL substrate according to any of clauses 27 to 33, wherein the aspect ratio of height to width of the plurality of TSVs is at least two (2) micrometers (μm).35. The RDL substrate according to any of clauses 27 to 34, further comprising a plurality of vias disposed through the dielectric layer and electrically coupled to a RDL interconnect among a plurality of RDL interconnects and a substrate interconnect among the plurality of substrate interconnects.36. The RDL substrate according to any of clauses 27 to 35, further comprising a plurality of second vias disposed through the dielectric layer of the RDL substrate and electrically coupled to a RDL interconnect among a plurality of RDL interconnects in the RDL layer and a substrate interconnect among the plurality of substrate interconnects in the substrate layer.37. The RDL substrate according to clause 36, wherein the aspect ratio of height to width of the plurality of second vias is at least 1.0.38. The IC package according to any of clauses 36 to 37, wherein the plurality of second vias are disposed through the dielectric layer of the RDL substrate outside of the capacitor package.39. The RDL substrate according to any of clauses 27 to 38, wherein the capacitor package comprises the dielectric layer comprising the dielectric material, wherein the capacitor is embedded in the dielectric layer.