Resistive memory device and manufacturing method thereof

A resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode disposed on the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode disposed on the second bottom electrode, and a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer for increasing the number of switchable resistance states of the resistive memory device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a resistive memory device and a manufacturing method thereof, and more particularly, to a resistive memory device including variable resistance layers with different thicknesses and a manufacturing method thereof.

2. Description of the Prior Art

Semiconductor memory devices are used in computer and electronics industries as a means for retaining digital information or data. Typically, the semiconductor memory devices are divided into volatile and non-volatile memory devices. The volatile memory device is a computer memory that loses its stored data when power to the operation is interrupted. Comparatively, in the non-volatile memory device, the stored data will not be lost when the power supply is interrupted. The resistive random access memory (RRAM) is a kind of non-volatile memory technology having the characteristics of low operating voltage, low power consumption, and high writing speed and is regarded as a memory structure that can be applied to many electronic devices.

SUMMARY OF THE INVENTION

A resistive memory device and a manufacturing method thereof are provided in the present invention. Variable resistance layers with different thicknesses are used to increase the number of switchable resistance states of the resistive memory device, and the resistive memory device with multiple resistance states may be realized accordingly.

According to an embodiment of the present invention, a resistive memory device is provided. The resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode, and a first variable resistance layer. The first top electrode is disposed on the first bottom electrode, and the first variable resistance layer is disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode, and a second variable resistance layer. The second top electrode is disposed on the second bottom electrode, and the second variable resistance layer is disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer.

According to an embodiment of the present invention, a manufacturing method of a resistive memory device is provided. The manufacturing method includes the following steps. A first stacked structure and a second stacked structure are formed on a dielectric layer. The first stacked structure includes a first bottom electrode, a first top electrode, and a first variable resistance layer. The first top electrode is disposed on the first bottom electrode, and the first variable resistance layer is disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode, and a second variable resistance layer. The second top electrode is disposed on the second bottom electrode, and the second variable resistance layer is disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer.

DETAILED DESCRIPTION

The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein below are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present invention.

Before the further description of the preferred embodiment, the specific terms used throughout the text will be described below.

The ordinal numbers, such as “first”, “second”, etc., used in the description and the claims are used to modify the elements in the claims and do not themselves imply and represent that the claim has any previous ordinal number, do not represent the sequence of some claimed element and another claimed element, and do not represent the sequence of the manufacturing methods, unless an addition description is accompanied. The use of these ordinal numbers is only used to make a claimed element with a certain name clear from another claimed element with the same name.

The term “forming” or the term “disposing” are used hereinafter to describe the behavior of applying a layer of material to the substrate. Such terms are intended to describe any possible layer forming techniques including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer toFIG. 1.FIG. 1is a schematic drawing illustrating a resistive memory device101according to a first embodiment of the present invention. As shown inFIG. 1, the resistive memory device101includes a first stacked structure ST1and a second stacked structure ST2. The first stacked structure ST1includes a first bottom electrode BE1, a first top electrode TE1, and a first variable resistance layer RL1. The first top electrode TE1is disposed on the first bottom electrode BE1, and the first variable resistance layer RL1is disposed between the first bottom electrode BE1and the first top electrode TE1in a vertical direction (such as a first direction D1 shown inFIG. 1). The second stacked structure ST2includes a second bottom electrode BE2, a second top electrode TE2, and a second variable resistance layer RL2. The second top electrode TE2is disposed on the second bottom electrode BE2, and the second variable resistance layer RL2is disposed between the second bottom electrode BE2and the second top electrode TE2in the first direction D1. A thickness TK1of the first variable resistance layer RL1in the first direction D1 is less than a thickness TK2of the second variable resistance layer RL2in the first direction D1.

In some embodiments, the first stacked structure ST1and the second stacked structure ST2may be regarded as resistive memory sub units including variable resistance material layers with different thicknesses, and each variable resistance material layer may be regarded as a switching medium in the resistive memory sub unit. The resistance of the resistive memory sub unit may be changed by applying suitable voltage to the top electrode and the bottom electrode in the stacked structure, and the resistive memory sub unit may switch to high resistance state (HRS) or low resistance state (LRS) for realizing the operation mode of the memory device, such as storing data, reading data, and resetting. Additionally, the operation voltage and/or the operation current for switching between the HRS and the LRS in the resistive memory sub unit and the resistance of the resistive memory sub unit in the HRS and the LRS may be changed by adjusting the thickness of the variable resistance material layer in the resistive memory sub unit, and multiple resistance states may be realized in the resistive memory device101accordingly.

For example, in some embodiments, the setting voltage (VSET) for switching the first stacked structure ST1including the relatively thinner first variable resistance layer RL1to LRS from FIRS may be lower than the setting voltage for switching the second stacked structure ST2including the relatively thicker second variable resistance layer RL2to LRS from HRS. For instance, the setting voltage for switching the first stacked structure ST1including the relatively thinner first variable resistance layer RL1to LRS from FIRS may be about 0.5 volt, and the setting voltage for switching the second stacked structure ST2including the relatively thicker second variable resistance layer RL2to LRS from HRS may be about 1 volt, but not limited thereto. Therefore, by controlling the voltage applied to the first stacked structure ST1and the second stacked structure ST2respectively, both the first stacked structure ST1and the second stacked structure ST2may be kept in HRS, both the first stacked structure ST1and the second stacked structure ST2may be kept in LRS, or the first stacked structure ST1may switch to LRS from HRS while the second stacked structure ST2may be kept in HRS still. In other words, compared with the resistive memory sub units including the variable resistance material layers with the same thickness, the first stacked structure ST1and the second stacked structure ST2in this embodiment may be used to provide at least three different resistance states (both in HRS, both in LRS, and partly in HRS and partly in LRS), the multiple resistance states may be realized, and the data storage capacity of the resistive memory device101may be enhanced accordingly.

In some embodiments, the first stacked structure ST1may be electrically connected with the second stacked structure ST2. For example, the first stacked structure ST1may be electrically connected with the second stacked structure ST2in parallel, but not limited thereto. In some embodiments, the first bottom BE1of the first stacked structure ST1may be electrically connected to the second bottom electrode BE2of the second stacked structure ST2via an electrically conductive structure (such as an electrically conductive layer12and connection plugs18shown inFIG. 1, but not limited thereto) disposed in a single dielectric layer or multiple dielectric layers (such as a dielectric layer10, a dielectric layer14, and a dielectric layer16shown inFIG. 1, but not limited thereto), and the first top TE1of the first stacked structure ST1may be electrically connected to the second top electrode TE2of the second stacked structure ST2via an electrically conductive structure (such as an electrically conductive layer46and connection plugs44shown inFIG. 1, but not limited thereto) disposed in a single dielectric layer or multiple dielectric layers (such as a dielectric layer40and a dielectric layer42shown inFIG. 1, but not limited thereto). In some embodiments, the first bottom electrode BE1may be electrically connected with the second bottom electrode BE2via an approach different from the approach described above, the first top electrode TE1may be electrically connected with the second top electrode TE2via an approach different from the approach described above, and the first stacked structure ST1may be electrically connected with the second stacked structure ST2via an approach different from the approach described above also according to some design considerations.

In some embodiments, the dielectric layer10, the dielectric layer14, the dielectric layer16, the electrically conductive layer12, and the connection plugs18may be disposed under the first stacked structure ST1and the second stacked structure ST2; the dielectric layer40, the dielectric layer42, the connection plugs44, and the electrically conductive layer46may be disposed above the first stacked structure ST1and the second stacked structure ST2; and the first stacked structure ST1and the second stacked structure ST2may be disposed in a dielectric layer34located between the dielectric layer16and the dielectric layer40in the first direction D1, but not limited thereto. In other words, the resistive memory device101may further include the dielectric layer10, the dielectric layer14, the dielectric layer16, the dielectric layer34, the dielectric layer40, the dielectric layer42, the electrically conductive layer12, the connection plugs18, the connection plugs44, and the electrically conductive layer46described above, but not limited thereto. Additionally, in some embodiments, the resistive memory device101may further include a first spacer32A and a second spacer32B disposed in the dielectric layer34and surrounding the first stacked structure ST1and the second stacked structure ST2in a horizontal direction (such as a second direction D2 shown inFIG. 1, but not limited thereto) respectively for protecting the first variable resistance layer RL1and the second variable resistance layer RL2and keeping material (such as oxygen) from entering the first variable resistance layer RL1and the second variable resistance layer RL2via the sidewalls of the first stacked structure ST1and the second stacked structure ST2and influencing the material characteristics of the first variable resistance layer RL1and the second variable resistance layer RL2.

In some embodiments, the dielectric layer10may be disposed on a substrate (not shown), and the substrate may include a semiconductor substrate, such as a silicon substrate, a silicon germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a substrate made of other suitable materials, but not limited thereto. In addition, before the step of forming the dielectric layer10, other units (such as transistors) and/or other circuits (not shown) may be formed on the substrate described above, and the electrically conductive layer12may be electrically connected downwardly with the units and/or the circuits on the substrate, but not limited thereto. In some embodiments, the manufacturing method of the resistive memory device101may be integrated with the back end of line (BEOL) process in the semiconductor manufacturing process. The dielectric layer10, the dielectric layer14, the dielectric layer16, the dielectric layer34, the dielectric layer40, and the dielectric layer42described above may be regarded as interlayer dielectric formed in the BEOL process, and the electrically conductive layer12, the connection plugs18, the connection plugs44, and the electrically conductive layer46described above may be regarded as a portion of an interconnection structure formed in the BEOL process, but not limited thereto.

In some embodiments, the first direction D1 described above may be regarded as a thickness direction of the dielectric layer10, and a horizontal direction (such as the second direction D2) substantially orthogonal to the first direction D1 may be parallel with a surface of the dielectric layer10, but not limited thereto. Additionally, in this description, a distance between the dielectric layer10and a relatively higher location and/or a relatively higher part in the first direction D1 is greater than a distance between the dielectric layer10and a relatively lower location and/or a relatively lower part in the first direction D1. The bottom of each part may be closer to the dielectric layer10in the first direction D1 than the top of this part. Another part disposed above a specific part may be regarded as being relatively far from the dielectric layer10in the first direction D1, and another part disposed under a specific part may be regarded as being relatively closer to the dielectric layer10in the first direction D1.

In some embodiments, the materials of the first variable resistance layer RL1and the second variable resistance layer RL2may respectively include metal oxide such as transition metal oxide, perovskite oxide, or other suitable variable resistance materials. The metal oxide described above may include nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, zinc oxide, tungsten oxide, cobalt oxide, copper oxide, niobium oxide, molybdenum oxide, tantalum oxide, ferric oxide, manganese oxide, a mixture of the above-mentioned materials, or other suitable metal oxide materials. The perovskite oxide described above may include strontium titanate (SrTiO3), barium titanate (BaTiO3), lead titanate (PbTiO3), or other suitable perovskite oxide materials. In some embodiments, the material composition of the first variable resistance layer RL1may be identical to or different from the material composition of the second variable resistance layer RL2according to some design considerations. For example, in some embodiments, the second variable resistance layer RL2may include a first layer RL21and a second layer RL22stacked in the first direction D1, and the second layer RL22may be disposed on the first layer RL21in the first direction D1. In some embodiments, the material composition of the first variable resistance layer RL1may be identical to a material composition of at least one of the first layer RL21or the second layer RL22.

In some embodiments, the first layer RL21of the second variable resistance layer RL2, the second layer RL22of the second variable resistance layer RL2, and the first variable resistance layer RL1may be formed of the same material and have the same material composition accordingly. In some embodiments, the material composition of the first layer RL21of the second variable resistance layer RL2may be different from the material composition of the second layer RL22of the second variable resistance layer RL2. The first variable resistance layer RL1and the first layer RL21or the first variable resistance layer RL1and the second layer RL22may be formed of the same material and have the same material composition and substantially the same thickness, and the first layer RL21or the second layer RL22including a material different from the material of the first variable resistance layer RL1may be used to increase the total thickness of the second variable resistance layer RL2, but not limited thereto. For example, in some embodiments, the first layer RL21of the second variable resistance layer RL2may be formed by patterning a first resistance material layer26, and the first variable resistance layer RL1and the second layer RL22of the second variable resistance layer RL2may be formed by patterning a second resistance material layer28, but not limited thereto. It is worth noting that, in some embodiments, when the thickness of the first resistance material layer26is equal to the thickness of the second resistance material layer28, the voltage for switching the first resistance material layer26to LRS from FIRS may be higher than the voltage for switching the second resistance material layer28to LRS from FIRS by adjusting the material compositions of the first resistance material layer26and the second resistance material layer28. Accordingly, the difference between the voltage for switching the first stacked structure ST1to LRS from HRS and the voltage for switching the second stacked structure ST2to LRS from HRS may be further increased, and that will be beneficial to the operation of the resistive memory device101, but not limited thereto.

In some embodiments, the first stacked structure ST1may further include a first intermediate electrode ME1and a first diode layer22A, and the second stacked structure ST2may further include a second intermediate electrode ME2and a second diode layer22B. The first intermediate electrode ME1may be disposed between the first bottom electrode BE1and the first top electrode TE1in the first direction D1, the first variable resistance layer RL1may be disposed between the first intermediate electrode ME1and the first top electrode TE1in the first direction D1, and the first diode layer22A may be disposed between the first intermediate electrode ME1and the first bottom electrode BE1in the first direction D1. The second intermediate electrode ME2may be disposed between the second bottom electrode BE2and the second top electrode TE2in the first direction D1, the second variable resistance layer RL2may be disposed between the second intermediate electrode ME2and the second top electrode TE2in the first direction D1, and the second diode layer22B may be disposed between the second intermediate electrode ME2and the second bottom electrode BE2in the first direction D1. In other words, the first bottom electrode BE1, the first diode layer22A, the first intermediate electrode ME1, the first variable resistance layer RL1, and the first top electrode TE1in the first stacked structure ST1may be sequentially stacked and disposed from the bottom of the first stacked structure ST1to the top of the first stacked structure ST1in the first direction D1, and the second bottom electrode BE2, the second diode layer22B, the second intermediate electrode ME2, the second variable resistance layer RL2, and the second top electrode TE2in the second stacked structure ST2may be sequentially stacked and disposed from the bottom of the second stacked structure ST2to the top of the second stacked structure ST2in the first direction D1

In some embodiments, the first variable resistance layer RL1may directly contact the first intermediate electrode ME1and the first top electrode TE1, and the second variable resistance layer RL2may directly contact the second intermediate electrode ME2and the second top electrode TE2. In this situation, a distance DS1between the first top electrode TE1and the first intermediate electrode ME1in the first direction D1 may be substantially equal to the thickness TK1of the first variable resistance layer RL1, a distance DS2between the second top electrode TE2and the second intermediate electrode ME2in the first direction D1 may be substantially equal to the thickness TK2of the second variable resistance layer RL2, and the distance DS1between the first top electrode TE1and the first intermediate electrode ME1in the first direction D1 may be less than the distance DS2between the second top electrode TE2and the second intermediate electrode ME2in the first direction D1 accordingly, but not limited thereto. Additionally, in some embodiments, a top surface S12of the first top electrode TE1and a top surface S22of the second top electrode TE2may be substantially coplanar, and a bottom surface S11of the first top electrode TE1may be lower than a bottom surface S21of the second top electrode TE2in the first direction D1. In some embodiments, the top surface S12and the top surface S22may be regarded as the topmost surface of the first top electrode TE1and the topmost surface of the second top electrode TE2in the first direction D1 respectively, the bottom surface S11and the bottom surface S21may be regarded as the bottommost surface of the first top electrode TE1and the bottommost surface of the second top electrode TE2in the first direction D1 respectively, and the thickness of the first top electrode TE1in the first direction D1 may be greater than the thickness of the second top electrode TE2in the first direction D1, but not limited thereto.

In some embodiments, the first intermediate electrode MEL the second intermediate electrode ME2, the first diode layer22A, and the second diode layer22B described above may be omitted and not disposed in the resistive memory device according to some design considerations, the first variable resistance layer RL1may directly contact the first bottom electrode BE1and the first top electrode TE1, and the second variable resistance layer RL2may directly contact the second bottom electrode BE2and the second top electrode TE2, but not limited thereto. No matter whether the first intermediate electrode MEL the second intermediate electrode ME2, the first diode layer22A, and the second diode layer22B are disposed in the resistive memory device or not, the distance between the first top electrode TE1and the first bottom electrode BE1in the first direction D1 may be less than the distance between the second top electrode TE2and the second bottom electrode BE2in the first direction D1.

In some embodiments, the materials of the first bottom electrode BE1, the second bottom electrode BE2, the first intermediate electrode ME1, the second intermediate electrode ME2, the first top electrode TE1, and the second top electrode TE2may respectively include aluminum, platinum, ruthenium, iridium, nickel, cobalt, chromium, tungsten, copper, hafnium, zirconium, zinc, gold, titanium, an alloy of the material described above, a mixture of the material described above, or other suitable metallic electrically conductive materials or non-metallic electrically conductive materials. In some embodiments, the first diode layer22A and the second diode layer22B may respectively include a p-type semiconductor layer and an n-type semiconductor layer (not shown) stacked in the first direction D1 for forming a diode structure between the first intermediate electrode ME1and the first bottom electrode BE1and forming a diode structure between the second intermediate electrode ME2and the second bottom electrode BE2, respectively, but not limited thereto. In some embodiments, the first diode layer22A and the second diode layer22B may include other suitable diode structures, respectively. In addition, the p-type semiconductor layer described above may include a p-type silicon semiconductor layer, a p-type cupric oxide (CuO) semiconductor layer, or other suitable p-type semiconductor materials, and the n-type semiconductor layer described above may include an n-type silicon semiconductor layer, an n-type indium zinc oxide (InZnO) semiconductor layer, or other suitable n-type semiconductor materials. Additionally, the p-type semiconductor layer in the first diode layer22A and the p-type semiconductor layer in the second diode layer22B may be disposed between the n-type semiconductor layer and the bottom electrode in the first direction D1 respectively for controlling the current direction in the first stacked structure ST1and the second stacked structure ST2under the structures shown inFIG. 1, but not limited thereto.

Please refer toFIGS. 1-8.FIGS. 2-8are schematic drawings illustrating a manufacturing method of a resistive memory device according to an embodiment of the present invention, whereinFIG. 3is a schematic drawing in a step subsequent toFIG. 2,FIG. 4is a schematic drawing in a step subsequent toFIG. 3,FIG. 5is a schematic drawing in a step subsequent toFIG. 4,FIG. 6is a schematic drawing in a step subsequent toFIG. 5,FIG. 7is a schematic drawing in a step subsequent toFIG. 6, andFIG. 8is a schematic drawing in a step subsequent toFIG. 7. In some embodiments,FIG. 1may be regarded as a schematic drawing in a step subsequent toFIG. 8, but not limited thereto. As shown inFIG. 1, a manufacturing method of the resistive memory device101may include the following steps. Firstly, the first stacked structure ST1and the second stacked structure ST2are formed on the dielectric layer10. The first stacked structure ST1includes the first bottom electrode BE1, the first top electrode TE1, and the first variable resistance layer RL1. The first top electrode TE1is disposed on the first bottom electrode BE1, and the first variable resistance layer RL1is disposed between the first bottom electrode BE1and the first top electrode TE1in the first direction D1. The second stacked structure ST2includes the second bottom electrode BE2, the second top electrode TE2, and the second variable resistance layer RL2. The second top electrode TE2is disposed on the second bottom electrode BE2, and the second variable resistance layer RL2is disposed between the second bottom electrode BE2and the second top electrode TE2in the first direction D1. The thickness TK1of the first variable resistance layer RL1is less than the thickness TK2of the second variable resistance layer RL2.

Specifically, the manufacturing method in this embodiment may include but is not limited to the following steps. Firstly, as shown inFIG. 2, the electrically conductive layer12may be formed in the dielectric layer10. The dielectric layer14and the dielectric layer16may be formed on the dielectric layer10and the electrically conductive layer12, and the connection plugs18may penetrate through the dielectric layer16and the dielectric layer14in the first direction D1 for contacting and being electrically connected with the electrically conductive layer12. Subsequently, a first electrically conductive layer20, a diode material layer22, a second electrically conductive layer24, and the first resistance material layer26may be sequentially formed on the dielectric layer16and the connection plugs18. In some embodiments, a first region R1and a second region R2may be defined on the dielectric layer10, and the first region R1may be disposed adjacent to the second region R2. The first region R1may be a region where the first stacked structure ST1shown inFIG. 1is going to be formed, and the second region R2may be a region where the second stacked structure ST2shown inFIG. 1is going to be formed. In other words, the first region R1and the second region R2may be regarded as regions corresponding to different resistive memory sub units, but not limited thereto. The first electrically conductive layer20, the diode material layer22, the second electrically conductive layer24, and the first resistance material layer26may be formed on the first region R1and the second region R2.

As shown inFIG. 3, the first resistance material layer26on the first region R1is then removed, and a part of the first resistance material layer26remains on the second region R2after the step of removing the first resistance material layer26on the first region R1. Subsequently, as shown inFIG. 4, a second resistance material layer28is formed on the first region R1and the second region R2, and a mask layer30is formed on the second resistance material layer28. A part of the second resistance material layer28may be formed on the part of the first resistance material layer26remaining on the second region R2. The mask layer30may include polysilicon or other suitable materials without negative influence on the second resistance material layer28. As shown inFIG. 4andFIG. 5, after the step of forming the mask layer, a patterning process91may be performed to the second resistance material layer28and the part of the first resistance material layer26remaining on the second region R2for forming the first variable resistance layer RL1on the first region R1and the second variable resistance layer RL2on the second region R2. In other words, the mask layer30may be formed before the patterning process91, but not limited thereto. In some embodiments, the manufacturing method may not include the step of forming the mask layer30described above according to some design considerations. In some embodiments, a patterned photoresist (not shown) may be formed on the mask layer30in the patterning process91and be used as an etching mask in an etching process, the patterning process91may include one or more etching steps for etching the mask layer30, the second resistance material layer28, the first resistance material layer26, the second electrically conductive layer24, the diode material layer22, and the first electrically conductive layer20respectively, and the patterned photoresist may be removed in the etching steps or after the patterning process91, but not limited thereto.

In other words, the first electrically conductive layer20may be patterned to be the first bottom electrode BE1on the first region R1and the second bottom electrode BE2on the second region R2by the patterning process91, and the first bottom electrode BE1and the second bottom electrode BE2are separated from each other. The diode material layer22may be patterned to be the first diode layer22A on the first region R1and the second diode layer22B on the second region R2by the patterning process91, and the first diode layer22A and the second diode layer22B are separated from each other. The second electrically conductive layer24may be patterned to be the first intermediate electrode ME1on the first region R1and the second intermediate electrode ME2on the second region R2by the patterning process91, and the first intermediate electrode ME1and the second intermediate electrode ME2are separated from each other. The part of the first resistance material layer26remaining on the second region R2may be patterned to be the first layer RL21of the second variable resistance layer RL2on the second region R2by the patterning process91. The second resistance material layer28may be pattered to be the first variable resistance layer RL1on the first region R1and the second layer RL22of the second variable resistance layer RL2on the second region R2by the patterning process91, and the first variable resistance layer RL1is separated from the second layer RL22of the second variable resistance layer RL2. Additionally, in some embodiments, the mask layer30may be patterned to be a first mask pattern30A on the first variable resistance layer RL1and a second mask pattern30B on the second variable resistance layer RL2by the patterning process91, and the first mask pattern30A and the second mask pattern30B are separated from each other, but not limited thereto.

It is worth noting that, the method of forming the first variable resistance layer RL1and the second variable resistance layer RL2in this embodiment is not limited to the approach shown inFIGS. 2-5described above, and other suitable approaches may be used to form the first variable resistance layer RL1and the second variable resistance layer RL2according to some design considerations. Additionally, in some embodiments, a projection area of the first bottom electrode BE1in the first direction D1, a projection area of the first diode layer22A in the first direction D1, a projection area of the first intermediate electrode ME1in the first direction D1, a projection area of the first variable resistance layer RL1in the first direction D1, and a projection area of the first mask pattern30A in the first direction D1 may be substantially equal to one another; and a projection area of the second bottom electrode BE2in the first direction D1, a projection area of the second diode layer22B in the first direction D1, a projection area of the second intermediate electrode ME2in the first direction D1, a projection area of the second variable resistance layer RL2in the first direction D1, and a projection area of the second mask pattern30B in the first direction D1 may be substantially equal to one another because the first bottom electrode BE1, the second bottom electrode BE2, the first diode layer22A, the second diode layer22B, the first intermediate electrode ME1, the second intermediate electrode ME2, the first variable resistance layer RL1, the second variable resistance layer RL2, the first mask pattern30A, and the second mask pattern30B may be formed by one patterning process, but not limited thereto. In some embodiments, the first bottom electrode BE1, the second bottom electrode BE2, the first diode layer22A, the second diode layer22B, the first intermediate electrode ME1, the second intermediate electrode ME2, the first variable resistance layer RL1, the second variable resistance layer RL2, the first mask pattern30A, and the second mask pattern30B may be formed respectively by different patterning processes according to some design considerations, and the projection areas of at least some of the parts described above in the first direction D1 may be different from one another accordingly.

Subsequently, as shown inFIG. 6, the first spacer32A may be formed on sidewalls of the first bottom electrode BE1, sidewalls of the first diode layer22A, sidewalls of the first intermediate electrode ME1, sidewalls of the first variable resistance layer RL1, and sidewalls of the first mask pattern30A, and the second spacer32B may be formed on sidewalls of the second bottom electrode BE2, sidewalls of the second diode layer22B, sidewalls of the second intermediate electrode ME2, sidewalls of the second variable resistance layer RL2, and sidewalls of the second mask pattern30B. The first spacer32A may surround the first bottom electrode BE1, the first diode layer22A, the first intermediate electrode ME1, the first variable resistance layer RL1, and the first mask pattern30A in the horizontal direction, and the second spacer32B may surround the second bottom electrode BE2, the second diode layer22B, the second intermediate electrode ME2, the second variable resistance layer RL2, and the second mask pattern30B in the horizontal direction. The dielectric layer34may then be formed, and the top surface of the first mask pattern30A, the top surface of the second mask pattern30B, the top surface of the first spacer32A, the top surface of the second spacer32B, and the top surface of the dielectric layer34may be substantially coplanar by performing a planarization process (such as a chemical mechanical polishing process, but not limited thereto), but not limited thereto.

As shown inFIGS. 6-8, the first mask pattern30A may then be replaced with the first top electrode TE1, and the second mask pattern30B may then be replaced with the second top electrode TE2. For example, the first mask pattern30A and the second mask pattern30B may be removed for forming a first trench TR1surrounded by the first spacer32A and located above the first variable resistance layer RL1and forming a second trench TR2surrounded by the second spacer32B and located above the second variable resistance layer RL2. Subsequently, a third electrically conductive layer36may be formed, and the first trench TR1and the second trench TR2may be filled with the third electrically conductive layer36. The third electrically conductive layer36located outside the first trench TR1and the second trench TR2may be removed by performing a planarization process (such as a chemical mechanical polishing process, but not limited thereto) for forming the first top electrode TE1in the first trench TR1and forming the second top electrode TE2in the second trench TR2respectively, and the first stacked structure ST1and the second stacked structure ST2may be formed accordingly. As shown inFIG. 1, the dielectric layer40, the dielectric layer42, the connection plugs44, and the electrically conductive layer46described above may then be formed on the first stacked structure ST1and the second stacked structure ST2, and the resistive memory device101shown inFIG. 1may be formed accordingly.

The first variable resistance layer RL1and the second variable resistance layer RL2with different thicknesses may be formed by the manufacturing method described above, the etching damage to the variable resistance layer when a part of the variable resistance layer is thinned directly by an etching back approach may be avoided, and that will be beneficial to the electrical performance of the resistive memory device.

The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.

Please refer toFIG. 9.FIG. 9is a schematic drawing illustrating a resistive memory device102according to a second embodiment of the present invention. As shown inFIG. 9, the difference between the resistive memory device102and the resistive memory device in the first embodiment described above is that, in a cross-sectional view of the second variable resistance layer RL2(such asFIG. 9), the second layer RL22of the second variable resistance layer RL2in the resistive memory device102may include a U-shaped structure surrounding the second top electrode TE2in a horizontal direction (such as the second direction D2). In this embodiment, the thickness TK2of the second variable resistance layer RL2may be regarded as a thickness of the second variable resistance layer RL2located between the second top electrode TE2and the second intermediate electrode ME2in the first direction D1, and the distance DS2between the second top electrode TE2and the second intermediate electrode ME2in the first direction D1 may be substantially equal to the thickness TK2of the second variable resistance layer RL2, but not limited thereto. In some embodiments, a top surface S33of the second variable resistance layer RL2located between the second top electrode TE2and the second intermediate electrode ME2in the first direction D1 may be lower than a top surface S32of the second layer RL22of the second variable resistance layer RL2in the first direction D1, and the top surface S32of the second layer RL22of the second variable resistance layer RL2and the top surface S22of the second top electrode TE2may be substantially coplanar, but not limited thereto.

Additionally, in some embodiments, the first variable resistance layer RL1and the first layer RL21of the second variable resistance layer RL2may be formed of the same material layer (such as the first resistance material layer26), the second layer RL22of the second variable resistance layer RL2may be formed of another material layer (such as the second resistance material layer28), and the material composition of the second layer RL22of the second variable resistance layer RL2may be different from the material composition of the first variable resistance layer RL1accordingly, but not limited thereto. It is worth noting that, in some embodiments, when the thickness of the first resistance material layer26is equal to the thickness of the second resistance material layer28, the voltage for switching the second resistance material layer28to LRS from HRS may be higher than the voltage for switching the first resistance material layer26to LRS from HRS by adjusting the material compositions of the first resistance material layer26and the second resistance material layer28. Accordingly, the difference between the voltage for switching the first stacked structure ST1to LRS from HRS and the voltage for switching the second stacked structure ST2to LRS from HRS in this embodiment may be further increased, and that will be beneficial to the operation of the resistive memory device102, but not limited thereto.

Please refer toFIGS. 9-15.FIGS. 10-15are schematic drawings illustrating a manufacturing method of a resistive memory device according to another embodiment of the present invention, whereinFIG. 11is a schematic drawing in a step subsequent toFIG. 10,FIG. 12is a schematic drawing in a step subsequent toFIG. 11,FIG. 13is a schematic drawing in a step subsequent toFIG. 12FIG. 14is a schematic drawing in a step subsequent toFIG. 13, andFIG. 15is a schematic drawing in a step subsequent toFIG. 14. In some embodiments,FIG. 9may be regarded as a schematic drawing in a step subsequent toFIG. 15, but not limited thereto. Firstly, as shown inFIG. 10, the first electrically conductive layer20, the diode material layer22, the second electrically conductive layer24, the first resistance material layer26, and the mask layer30may be sequentially formed on the dielectric layer16and the connection plugs18. The first electrically conductive layer20, the diode material layer22, the second electrically conductive layer24, the first resistance material layer26, and the mask layer30may be formed on the first region R1and the second region R2. Subsequently, as shown inFIG. 10andFIG. 11, a patterning process92may be performed to the first resistance material layer26for forming the first variable resistance layer RL1on the first region R1and forming the first layer RL21on the second region R2.

In other words, the mask layer30may be formed before the patterning process92, but not limited thereto. In some embodiments, the manufacturing method may not include the step of forming the mask layer30described above according to some design considerations. In some embodiments, a patterned photoresist (not shown) may be formed on the mask layer30in the patterning process92and be used as an etching mask in an etching process, the patterning process92may include one or more etching steps for etching the mask layer30, the first resistance material layer26, the second electrically conductive layer24, the diode material layer22, and the first electrically conductive layer20respectively, and the patterned photoresist may be removed in the etching steps or after the patterning process92, but not limited thereto. Therefore, the first electrically conductive layer20may be patterned to be the first bottom electrode BE1and the second bottom electrode BE2by the patterning process92; the diode material layer22may be patterned to be the first diode layer22A and the second diode layer22B by the patterning process92; the second electrically conductive layer24may be patterned to be the first intermediate electrode ME1and the second intermediate electrode ME2by the patterning process92; and the first resistance material layer26may be patterned to be the first variable resistance layer RL1on the first region R1and the first layer RL21on the second region R2by the patterning process92. In this embodiment, the first variable resistance layer RL1is separated from the first layer RL21, and the second layer of the second variable resistance layer may be formed on the first layer RL21after the patterning process92. Additionally, in some embodiments, the mask layer30may be patterned to be the first mask pattern30A on the first variable resistance layer RL1and the second mask pattern30B on the first layer RL21by the patterning process92, but not limited thereto.

Subsequently, as shown inFIG. 11andFIG. 12, a patterned mask layer82may be formed covering the first region R1and exposing the second mask pattern30B, and the second mask pattern30B may be removed by an etching process accordingly for forming a third trench TR3surrounded by the second spacer32B and located above the first layer RL21. As shown inFIGS. 11-13, after the step of removing the second mask pattern30B, the patterned mask layer82is removed, the second layer RL22is formed on the first layer RL21, and the second top electrode TE2is formed on the second layer RL22. In some embodiments, the second resistance material layer28may be formed after the step of removing the second mask pattern30B, and the third electrically conductive layer36may be formed on the second resistance material layer28. The third trench TR3may be filled with the second resistance material layer28and the third electrically conductive layer36. The second resistance material layer28and the third electrically conductive layer36located outside the third trench TR3may be removed by performing a planarization process (such as a chemical mechanical polishing process, but not limited thereto) for forming the second layer RL22of the second variable resistance layer RL2and the second top electrode TE2in the third trench TR3, and the second stacked structure ST2may be formed accordingly.

Subsequently, as shown inFIGS. 13-15, after the step of forming the second top electrode TE2, the first mask pattern30A may be replaced with the first top electrode TE1for forming the first stacked structure ST1described above. In some embodiments, a patterned mask layer84may be formed covering the second region R2and exposing the first mask pattern30A, and the first mask pattern30A may be removed by an etching process accordingly for forming the first trench TR1. The patterned mask layer84may be removed after the step of removing the first mask pattern30A, a fourth electrically conductive layer38may be formed, and the first trench TR1may be filled with the fourth electrically conductive layer38. The fourth electrically conductive layer38located outside the first trench TR1may be removed by performing a planarization process (such as a chemical mechanical polishing process, but not limited thereto) for forming the first top electrode TE1in the first trench TR1, and the first stacked structure ST1described above may be formed accordingly. As shown inFIG. 9, the dielectric layer40, the dielectric layer42, the connection plugs44, and the electrically conductive layer46may then be formed on the first stacked structure ST1and the second stacked structure ST2, and the resistive memory device102shown inFIG. 9may be formed accordingly.

It is worth noting that, the method of forming the first variable resistance layer RL1and the second variable resistance layer RL2in this embodiment is not limited to the approach shown inFIGS. 10-13described above, and other suitable approaches may be used to form the first variable resistance layer RL1and the second variable resistance layer RL2shown inFIG. 9according to some design considerations. Additionally, in this embodiment, the material composition of the first top electrode TE1may be different from the material composition of the second top electrode TE2because the first top electrode TE1and the second top electrode TE2may be formed by different process steps, but not limited thereto. In addition, the etching damage to the second top electrode TE2and/or the second layer RL22of the second variable resistance layer RL2in the patterning process may be avoided because the second top electrode TE2and the second layer RL22of the second variable resistance layer RL2may be formed after the patterning process, and that will be beneficial to the electrical performance of the resistive memory device102.

To summarize the above descriptions, in the resistive memory device and the manufacturing method thereof according to the present invention, the variable resistance layers with different thicknesses may be used to increase the number of switchable resistance states of the resistive memory device, and the resistive memory device with multiple resistance states may be realized accordingly. In addition, the variable resistance layers with different thicknesses may be formed and the etching damage to the variable resistance layers may be reduced by the manufacturing method of the present invention, and the overall electrical performance of the resistive memory device may be improved accordingly.