SEMICONDUCTOR DEVICE

A semiconductor device that has both low power consumption and high performance is provided. The semiconductor device includes a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer over the first semiconductor layer, a third conductive layer over the second insulating layer, and a first insulating layer sandwiched between the first conductive layer and the second conductive layer. The first insulating layer includes a first opening reaching the first conductive layer. The second conductive layer includes a second opening. The first opening and the second opening overlap with each other in a plan view. In the first opening, the first semiconductor layer is in contact with the top surface of the first conductive layer and the side surface of the first insulating layer. In the second opening, the first semiconductor layer is in contact with the side surface of the second conductive layer. The first semiconductor layer includes a region overlapping with the third conductive layer with the second insulating layer therebetween. The side surface of the first insulating layer in the first opening includes a region forming an angle of greater than or equal to 10° and less than 55° with the top surface of the first conductive layer.

TECHNICAL FIELD

One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. One embodiment of the present invention relates to a transistor and a manufacturing method thereof. One embodiment of the present invention relates to a display device including a semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting apparatus, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input/output device (e.g., a touch panel), a method for driving any of them, and a method for manufacturing any of them.

Note that in this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, and means a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like), a device including the circuit, and the like. The semiconductor device also means all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component including a chip in a package are examples of the semiconductor device. Moreover, a memory device, a display device, a light-emitting apparatus, a lighting device, and an electronic device themselves are semiconductor devices and each of them includes a semiconductor device in some cases.

BACKGROUND ART

Semiconductor devices that include transistors are applied to a wide range of electronic devices. In a display device, for example, when the area occupied by transistors is reduced, the pixel size can be reduced and the definition can be increased. Therefore, minute transistors have been required.

As devices requiring high-definition display devices, for example, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR) have been actively developed.

As the display device, a light-emitting apparatus including an organic EL (Electro Luminescence) element or a light-emitting diode (LED) has been developed.

Patent Document 1 discloses a high-definition display device using an organic EL element.

REFERENCE

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

An object of one embodiment of the present invention is to provide a semiconductor device including a transistor having a minute size. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with a high on-state current. Another object is to provide a semiconductor device including a transistor with high reliability. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device including transistors with different channel lengths. Another object is to provide a semiconductor device that occupies a small area. Another object is to provide a high-performance semiconductor device. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with high productivity. Another object is to provide a novel semiconductor device.

Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not necessarily need to achieve all of these objects. Other objects can be derived from the description of the specification, the drawings, and the claims.

Means for Solving the Problems

One embodiment of the present invention is a semiconductor device including a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer over the first semiconductor layer, a third conductive layer over the second insulating layer, and a first insulating layer sandwiched between the first conductive layer and the second conductive layer. The first insulating layer includes a first opening reaching the first conductive layer. The second conductive layer includes a second opening. The first opening and the second opening overlap with each other in a plan view. In the first opening, the first semiconductor layer is in contact with a top surface of the first conductive layer and a side surface of the first insulating layer. In the second opening, the first semiconductor layer is in contact with a side surface of the second conductive layer. The first semiconductor layer includes a region overlapping with the third conductive layer with the second insulating layer therebetween. The side surface of the first insulating layer in the first opening includes a region forming an angle of greater than or equal to 10° and less than 55° with the top surface of the first conductive layer.

In the above structure, a thickness of the first insulating layer is preferably greater than or equal to 10 nm and less than 3 μm.

In the above structure, the first semiconductor layer preferably contains a metal oxide.

Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer over the first semiconductor layer, and a third conductive layer over the second insulating layer. The second transistor includes a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, the second insulating layer over the second semiconductor layer, and a sixth conductive layer over the second insulating layer. The first insulating layer includes a region sandwiched between the first conductive layer and the second conductive layer and a region sandwiched between the fourth conductive layer and the fifth conductive layer. The first insulating layer includes a first opening reaching the first conductive layer and a second opening reaching the fourth conductive layer. A side surface of the first insulating layer in the first opening includes a region forming an angle of greater than or equal to 10° and less than 55° with a top surface of the first conductive layer. A side surface of the first insulating layer in the second opening includes a region forming an angle of greater than or equal to 55° and less than or equal to 90° with a top surface of the fourth conductive layer. The second conductive layer includes a third opening. The first opening and the third opening overlap with each other in a plan view. The fifth conductive layer includes a fourth opening. The second opening and the fourth opening overlap with each other in a plan view. In the first opening, the first semiconductor layer is in contact with the top surface of the first conductive layer and the side surface of the first insulating layer. In the third opening, the first semiconductor layer is in contact with a side surface of the second conductive layer. The first semiconductor layer overlaps with the third conductive layer with the second insulating layer therebetween. In the second opening, the second semiconductor layer is in contact with the top surface of the fourth conductive layer and the side surface of the first insulating layer. In the fourth opening, the second semiconductor layer is in contact with a side surface of the fifth conductive layer. The second semiconductor layer overlaps with the sixth conductive layer with the second insulating layer therebetween.

In the above structure, the second insulating layer preferably includes a first region covering the side surface of the first insulating layer in the first opening with the first semiconductor layer therebetween, a second region covering a top surface of the second conductive layer with the first semiconductor layer therebetween, a third region covering the side surface of the first insulating layer in the second opening with the second semiconductor layer therebetween, and a fourth region covering a top surface of the fifth conductive layer with the second semiconductor layer therebetween. A thickness of the first region is preferably greater than 0.85 times and less than 1.2 times a thickness of the second region. A thickness of the third region is preferably greater than or equal to 0.4 times and less than or equal to 0.85 times a thickness of the fourth region.

In the above structure, the thickness of the second region is preferably greater than or equal to 10 nm and less than or equal to 200 nm, and the thickness of the fourth region is preferably greater than or equal to 10 nm and less than or equal to 200 nm.

In the above structure, the second insulating layer preferably includes a first region covering the side surface of the first insulating layer in the first opening with the first semiconductor layer therebetween, a second region covering the top surface of the first conductive layer with the first semiconductor layer therebetween, a third region covering the side surface of the first insulating layer in the second opening with the second semiconductor layer therebetween, and a fourth region covering a top surface of the fourth conductive layer with the second semiconductor layer therebetween. A thickness of the first region is preferably greater than 0.85 times and less than 1.2 times a thickness of the second region. A thickness of the third region is preferably greater than or equal to 0.4 times and less than or equal to 0.85 times a thickness of the fourth region.

In the above structure, the thickness of the second region is preferably greater than or equal to 10 nm and less than or equal to 200 nm. The thickness of the fourth region is preferably greater than or equal to 10 nm and less than or equal to 200 nm.

In the above structure, a thickness of the first semiconductor layer in a region in contact with the side surface of the first insulating layer in the first opening is preferably greater than 0.85 times and less than 1.2 times a thickness of the first semiconductor layer in a region in contact with a top surface of the second conductive layer. A thickness of the second semiconductor layer in a region in contact with the side surface of the first insulating layer in the second opening is preferably greater than or equal to 0.4 times and less than or equal to 0.85 times a thickness of the second semiconductor layer in a region in contact with a top surface of the fifth conductive layer.

In the above structure, the thickness of the first semiconductor layer in the region in contact with the top surface of the second conductive layer is preferably greater than or equal to 1 nm and less than or equal to 200 nm. The thickness of the second semiconductor layer in the region in contact with the top surface of the fifth conductive layer is preferably greater than or equal to 1 nm and less than or equal to 200 nm.

In the above structure, a thickness of the first semiconductor layer in a region in contact with the side surface of the first insulating layer in the first opening is preferably greater than 0.85 times and less than 1.2 times a thickness of the first semiconductor layer in a region in contact with the top surface of the first conductive layer. A thickness of the second semiconductor layer in a region in contact with the side surface of the first insulating layer in the second opening is preferably greater than or equal to 0.4 times and less than or equal to 0.85 times a thickness of the second semiconductor layer in a region in contact with the top surface of the fourth conductive layer.

In the above structure, the thickness of the first semiconductor layer in the region in contact with the top surface of the first conductive layer is preferably greater than or equal to 1 nm and less than or equal to 200 nm. The thickness of the second semiconductor layer in the region in contact with the top surface of the fourth conductive layer is preferably greater than or equal to 1 nm and less than or equal to 200 nm.

Effect of the Invention

One embodiment of the present invention can provide a semiconductor device including a transistor having a minute size. A semiconductor device including a transistor with a short channel length can be provided. A semiconductor device including a transistor with a high on-state current can be provided. A semiconductor device including a transistor with high reliability can be provided. A semiconductor device including a transistor with favorable electrical characteristics can be provided. A semiconductor device including transistors with different channel lengths can be provided. A semiconductor device that occupies a small area can be provided. A high-performance semiconductor device can be provided. A semiconductor device with low power consumption can be provided. A highly reliable semiconductor device can be provided. A semiconductor device with high productivity can be provided. A novel semiconductor device can be provided.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Other effects can be derived from the description of the specification, the drawings, and the claims.

MODE FOR CARRYING OUT THE INVENTION

The position, size, range, and the like of each component illustrated in drawings do not represent the actual position, size, range, and the like in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, and the like disclosed in the drawings.

Note that in this specification and the like, ordinal numbers such as “first” and “second” are used for convenience and do not limit the number of components or the order of components (e.g., the order of steps or the stacking order of layers). An ordinal number used for a component in a certain part in this specification is not the same as an ordinal number used for the component in another part in this specification or the scope of claims in some cases.

Note that the term “film” and the term “layer” can be used interchangeably depending on the case or the circumstances. For example, the term “conductive layer” can be replaced with the term “conductive film”. As another example, the term “insulating film” can be replaced with the term “insulating layer”.

A transistor is a kind of semiconductor elements and can achieve a function of amplifying current or voltage, a switching operation for controlling conduction or non-conduction, and the like. An IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT) are in the category of a transistor in this specification.

In this specification and the like, expressions “one of a source and a drain” (or a first electrode or a first terminal) and “the other of the source and the drain” (or a second electrode or a second terminal) are used in the description of the connection relation of a transistor. This is because the source and the drain of the transistor change depending on the structure, operating conditions, or the like of the transistor. Note that the source or the drain of the transistor can also be referred to as a source (drain) terminal, a source (drain) electrode, or the like as appropriate depending on the situation.

In this specification and the like, the term “electrode” or “wiring” does not limit the function of the component. For example, an “electrode” is used as part of a “wiring” in some cases, and vice versa. Furthermore, the term “electrode” or “wiring” also includes the case where a plurality of “electrodes” or “wirings” are formed in an integrated manner, for example.

In this specification and the like, “electrically connected” includes the case where connection is made through an “object having any electric function”. Here, there is no particular limitation on the “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object. Examples of the “object having any electric function” include a switching element such as a transistor, a resistor, a coil, a capacitor, and other elements with a variety of functions as well as an electrode and a wiring.

Unless otherwise specified, off-state current in this specification and the like refers to leakage current between a source and a drain of a transistor in an off state (also referred to as a non-conduction state or a cutoff state). Unless otherwise specified, an off state refers to, in an n-channel transistor, a state where a voltage Vgs between its gate and source is lower than a threshold voltage Vth (in a p-channel transistor, higher than Vth).

In this specification and the like, the expression “having substantially the same top-view shapes” means that at least outlines of stacked layers partly overlap with each other. For example, the case of processing the upper layer and the lower layer with use of the same mask pattern or mask patterns that are partly the same is included. However, in some cases, the outlines do not completely overlap with each other and the upper layer is positioned on an inner side of the lower layer or the upper layer is positioned on an outer side of the lower layer; such a case is also represented by the expression “top-view shapes are substantially the same”. In the case where top-view shapes are the same or substantially the same, it can be said that end portions are aligned with each other or substantially aligned with each other”.

In this specification and the like, a tapered shape refers to such a shape that at least part of a side surface of a structure is inclined with respect to a substrate surface or a formation surface. For example, the tapered shape preferably includes a region where the angle formed by the inclined side surface and the substrate surface or the formation surface (such an angle is also referred to as a taper angle) is less than 90°. Note that the side surface, the substrate surface, and the formation surface of the structure are not necessarily completely flat and may be substantially flat with a slight curvature or substantially flat with slight unevenness.

In this specification and the like, a device manufactured using a metal mask or an FMM (fine metal mask, high-definition metal mask) is sometimes referred to as a device having an MM (metal mask) structure. In this specification and the like, a device manufactured without using a metal mask or an FMM is sometimes referred to as a device having an MML (metal maskless) structure.

In this specification and the like, a structure in which light-emitting layers of light-emitting elements (also referred to as light-emitting devices) having different emission wavelengths are separately formed is sometimes referred to as an SBS (Side By Side) structure. The SBS structure can optimize materials and structures of light-emitting elements and thus can increase the degree of freedom in selecting materials and structures, so that the luminance and the reliability can be easily improved.

In this specification and the like, a hole or an electron is sometimes referred to as a “carrier”. Specifically, a hole-injection layer or an electron-injection layer may be referred to as a “carrier-injection layer”, a hole-transport layer or an electron-transport layer may be referred to as a “carrier-transport layer”, and a hole-blocking layer or an electron-blocking layer may be referred to as a “carrier-blocking layer”. Note that the above-described carrier-injection layer, carrier-transport layer, and carrier-blocking layer cannot be clearly distinguished from each other on the basis of the cross-sectional shape, properties, or the like in some cases. One layer may have two or three functions of the carrier-injection layer, the carrier-transport layer, and the carrier-blocking layer in some cases.

In this specification and the like, the light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, examples of a layer included in the EL layer (also referred to as a functional layer) include a light-emitting layer, carrier-injection layers (a hole-injection layer and an electron-injection layer), carrier-transport layers (a hole-transport layer and an electron-transport layer), and carrier-blocking layers (a hole-blocking layer and an electron-blocking layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) includes at least an active layer functioning as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode and the other may be referred to as a common electrode.

In this specification and the like, a sacrificial layer (may be referred to as a mask layer) is positioned above at least a light-emitting layer (specifically, a layer processed into an island shape among layers included in an EL layer) and has a function of protecting the light-emitting layer in the manufacturing process.

In this specification and the like, step disconnection refers to a phenomenon in which a layer, a film, or an electrode is split because of the shape of the formation surface (e.g., a step).

In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 1 to FIG. 26.

Structure Example 1

The semiconductor device of one embodiment of the present invention will be described. FIG. 1A is a top view (also referred to as a plan view) of a semiconductor device 10. FIG. 1B is a cross-sectional view of a cross section along the dashed-dotted line A1-A2 in FIG. 1A, FIG. 2A is a cross-sectional view of a cross section along the dashed-dotted line B1-B2 in FIG. 1A, and FIG. 2B is a cross-sectional view of a cross section along the dashed-dotted line B3-B4 in FIG. 1A. Note that in FIG. 1A, some components (e.g., an insulating layer) of the semiconductor device 10 are not illustrated. Some components are not illustrated in top views of semiconductor devices in the following drawings, as in FIG. 1A.

The semiconductor device 10 includes a transistor 100 and a transistor 200. FIG. 2C and FIG. 2D are a perspective view of the transistor 100 and a perspective view of the transistor 200 included in the semiconductor device 10, respectively. In FIG. 2C and FIG. 2D, some components such as a substrate and an insulating layer are omitted.

The shape of the opening portion or the like where the semiconductor layer is embedded in the transistor 100 is different from that in the transistor 200. When the shapes of the opening portions are different from each other, the channel lengths of the transistor 100 and the transistor 200 can be different from each other. The thickness of the gate insulating layer can be different between the transistor 100 and the transistor 200. Moreover, the thickness of the semiconductor layer can be different between transistor 100 and the transistor 200. The transistor 100 includes a conductive layer 112a, a semiconductor layer 108, a conductive layer 112b, an insulating layer 106, and a conductive layer 104. The layers included in the transistor 100 may each have a single-layer structure or a stacked-layer structure.

The conductive layer 112a is provided over a substrate 102. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100.

An insulating layer 110 is positioned over the conductive layer 112a. The insulating layer 110 is provided so as to cover the top surface and a side surface of the conductive layer 112a.

The insulating layer 110 preferably has a stacked-layer structure. FIG. 1B and the like illustrate an example in which the insulating layer 110 has a stacked-layer structure of an insulating layer 110a, an insulating layer 110b over the insulating layer 110a, and an insulating layer 110c over the insulating layer 110b.

The insulating layer 110a is positioned over the conductive layer 112a. The insulating layer 110a is provided so as to cover the top surface and the side surface of the conductive layer 112a.

The insulating layer 110b is provided over the insulating layer 110a, and the insulating layer 110c is provided over the insulating layer 110b. An opening 141 reaching the conductive layer 112a is provided in the insulating layer 110.

The conductive layer 112b is positioned over the insulating layer 110. The conductive layer 112b includes an opening 143 overlapping with the opening 141. The conductive layer 112b functions as the other of the source electrode and the drain electrode of the transistor 100. The conductive layer 112b includes a region overlapping with the conductive layer 112a with the insulating layer 110 therebetween. The insulating layer 110 includes a region sandwiched between the conductive layer 112a and the conductive layer 112b. As described later, the insulating layer 110 includes a region sandwiched between two conductive layers (a conductive layer 212a and a conductive layer 212b) included in the transistor 200.

The semiconductor layer 108 is in contact with the top surface of the conductive layer 112a, a side surface of the insulating layer 110, and the top surface and a side surface of the conductive layer 112b. The semiconductor layer 108 is provided to cover the opening 141 and the opening 143. The semiconductor layer 108 is provided in contact with a side surface of the insulating layer 110 on the opening 141 side and an end portion of the conductive layer 112b on the opening 143 side (which can also be referred to as part of the top surface of the conductive layer 112b and a side surface of the conductive layer 112b on the opening 143 side). The semiconductor layer 108 is in contact with the conductive layer 112a through the opening 141 and the opening 143.

The insulating layer 106 is positioned over the semiconductor layer 108 and the conductive layer 112b. The insulating layer 106 is provided to cover the opening 141 and the opening 143 through the semiconductor layer 108. Part of the insulating layer 106 functions as a gate insulating layer of the transistor 100. Another part of the insulating layer 106 functions as a gate insulating layer of the transistor 200.

The conductive layer 104 is positioned over the insulating layer 106. The conductive layer 104 overlaps with the semiconductor layer 108 with the insulating layer 106 therebetween. The conductive layer 104 functions as a gate electrode of the transistor.

FIG. 5A is an enlarged view of the transistor 100 illustrated in FIG. 1A and FIG. 5B is an enlarged view of the transistor 100 illustrated in FIGS. 1B and 1s a cross-sectional view of a cross section along the dashed-dotted line A1-A3 in FIG. 5A. FIG. 5C is an enlarged view of a region 41 illustrated in FIG. 5B. Note that in the cross-sectional views illustrated in FIG. 1B and the like, the thicknesses of components are sometimes drawn to be larger for easy viewing. Thus, in the enlarged views illustrated in FIG. 5B, FIG. 5C, and the like, the thicknesses of the components are sometimes drawn to be smaller than those in a drawing that is not enlarged.

An angle th1 is an angle between the side surface of the insulating layer 110 on the opening 141 side and the formation surface of the insulating layer 110 (which is the top surface of the conductive layer 112a here). The angle th1 is preferably larger than an angle th2 described later (an angle formed by a side surface of the insulating layer 110 on an opening 241 side and the formation surface of the insulating layer 110 in the transistor 200).

The transistor 200 includes the conductive layer 212a, a semiconductor layer 208, the conductive layer 212b, the insulating layer 106, and a conductive layer 204. The layers included in the transistor 200 may each have a single-layer structure or a stacked-layer structure. The conductive layer 212a, the semiconductor layer 208, the conductive layer 212b, and the conductive layer 204 can be formed using the same materials as the materials that can be used for the conductive layer 112a, the semiconductor layer 108, the conductive layer 112b, and the conductive layer 104.

The conductive layer 212a is provided over the substrate 102. The conductive layer 212a functions as one of a source electrode and a drain electrode of the transistor 200.

The conductive layer 212a and the conductive layer 112a can be formed by processing the same conductive film.

The insulating layer 110 is positioned over the conductive layer 212a. The insulating layer 110 is provided so as to cover the top surface and the side surface of the conductive layer 112a.

The insulating layer 110a is positioned over the conductive layer 212a. The insulating layer 110a is provided so as to cover the top surface and a side surface of the conductive layer 212a.

The insulating layer 110b is provided over the insulating layer 110a, and the insulating layer 110c is provided over the insulating layer 110b. The opening 241 reaching the conductive layer 212a is provided in the insulating layer 110.

FIG. 6A is an enlarged view of the transistor 200 illustrated in FIG. 1A. FIG. 6B is an enlarged view of the transistor 200 illustrated in FIGS. 1B and 1s a cross-sectional view of a cross section along the dashed-dotted line A4-A2 in FIG. 6A. FIG. 7 is an enlarged view of a region 42 illustrated in FIG. 6B.

The angle th2 is an angle formed by the side surface of the insulating layer 110 on the opening 241 side and the formation surface of the insulating layer 110 (which is the top surface of the conductive layer 212a here).

The angle th2 is preferably smaller than the angle th1. A channel length L1 of the transistor 100 corresponds to the length of the side surface of the insulating layer 110 in the opening 141 in a cross-sectional view. A channel length L2 of the transistor 200 corresponds to the length of the side surface of the insulating layer 110 in the opening 241 in the cross-sectional view. When the angle th2 is smaller than the angle th1, the length of the side surface of the insulating layer 110 in the opening 241 can be longer than the length of the side surface of the insulating layer 110 in the opening 141. Thus, the channel length L2 of the transistor 200 can be longer than the channel length L1 of the transistor 100.

The conductive layer 212b is positioned over the insulating layer 110. The conductive layer 212b includes an opening 243 overlapping with the opening 241. The conductive layer 212b functions as the other of the source electrode and the drain electrode of the transistor 200. The conductive layer 212b includes a region overlapping with the conductive layer 212a with the insulating layer 110 therebetween.

The insulating layer 110 includes a region sandwiched between the conductive layer 112a and the conductive layer 112b and a region sandwiched between the conductive layer 212a and the conductive layer 212b.

The conductive layer 212b and the conductive layer 112b can be formed by processing the same conductive film.

The semiconductor layer 208 is in contact with the top surface of the conductive layer 212a, the side surface of the insulating layer 110, and the top surface and a side surface of the conductive layer 212b. The semiconductor layer 208 is provided to cover the opening 241 and the opening 243. The semiconductor layer 208 is provided in contact with the side surface of the insulating layer 110 on the opening 241 side and an end portion of the conductive layer 212b on the opening 143 side (which can also be referred to as part of the top surface of the conductive layer 212b and a side surface of the conductive layer 212b on the opening 243 side). The semiconductor layer 208 is in contact with the conductive layer 212a through the opening 241 and the opening 243.

The semiconductor layer 208 and the semiconductor layer 108 can be formed by processing the same semiconductor film.

In the case where a film is formed to cover a sidewall of the opening portion, the coverage with the film can be improved when the sidewall has a tapered shape and the angle between the sidewall and the formation surface is made small. Meanwhile, when the sidewall is steep, the coverage is reduced and the thickness is reduced in some cases. Thus, in the case where the angle th1 is larger than the angle th2 and a sidewall of the opening 141 is steeper than that of the opening 241, the semiconductor layer 108 is sometimes thinner than the semiconductor layer 208.

The insulating layer 106 is positioned over the semiconductor layer 208 and the conductive layer 212b. The insulating layer 106 is provided to cover the opening 241 and the opening 243 through the semiconductor layer 208. As described above, one part of the insulating layer 106 functions as the gate insulating layer of the transistor 100 and another part of the insulating layer 106 functions as the gate insulating layer of the transistor 200.

Note that the thickness of the insulating layer 106 in a region covering the sidewall of the opening 141 is different from the thickness of the insulating layer 106 in a region covering the sidewall of the opening 241 in some cases. Specifically, for example, the sidewall of the opening 141 is steeper than that of the opening 241, so that the insulating layer 106 covering the sidewall of the opening 141 is thinner than that of the opening 241 in some cases.

The conductive layer 204 is positioned over the insulating layer 106. The conductive layer 204 overlaps with the semiconductor layer 208 with the insulating layer 106 therebetween. The conductive layer 204 functions as a gate electrode of the transistor.

The conductive layer 204 and the conductive layer 104 can be formed by processing the same conductive film.

The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can function as wirings, and the transistor 100 can be provided in a region where these wirings overlap with each other. The conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can function as wirings, and the transistor 200 can be provided in a region where these wirings overlap with each other. That is, the areas occupied by the transistor 100, the transistor 200, and the wirings can be reduced in the circuit including the transistor 100, the transistor 200, and the wirings. Accordingly, the area occupied by the circuit can be reduced, which makes it possible to provide a small semiconductor device.

When the semiconductor device of one embodiment of the present invention is used for a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced and a high-definition display device can be provided, for example. When the semiconductor device of one embodiment of the present invention is used for a driver circuit (e.g., one or both of a gate line driver circuit and a source line driver circuit) of a display device, the area occupied by the driver circuit can be reduced and the display device can have a narrow bezel, for example.

There is no particular limitation on the top-view shapes of the opening 141, the opening 143, the opening 241, and the opening 243. The top-view shapes of the opening 141, the opening 143, the opening 241, and the opening 243 can be polygons such as a circle, an ellipse, a triangle, a tetragon (including a rectangle, a rhombus, and a square), and a pentagon; and polygons with rounded corners, for example. Note that the polygon may be a concave polygon (a polygon at least one of the interior angles of which is greater than 180°) or a convex polygon (a polygon all the interior angles of which are less than or equal to 180°). The top-view shapes of the opening 141, the opening 143, the opening 241, and the opening 243 are preferably circles as illustrated in FIG. 1A and the like. When the top-view shapes of the openings are circles, processing accuracy at the time of formation of the openings can be high, whereby the openings can be formed to have minute sizes. Note that in this specification and the like, a circular shape is not necessarily a perfect circular shape.

In this specification and the like, a top-view shape refers to a shape in a plan view. For example, in the structure illustrated in FIG. 1B or the like, the shape of the end portion of the top surface of the insulating layer (here, the insulating layer 110) sandwiched between the conductive layer 112a and the conductive layer 112b on the opening 141 side can be the top-view shape of the opening 141. Alternatively, for example, the shape of the end portion of the bottom surface of the insulating layer sandwiched between the conductive layer 112a and the conductive layer 112b on the opening 141 side can be the top-view shape of the opening 141.

In FIG. 1A, the shape of an end portion of the top surface of the insulating layer 110 on the opening 141 side is denoted as a shape 141t. The shape of an end portion of the bottom surface of the conductive layer 112b on the opening 143 side is denoted as a shape 143b. The shape of an end portion of the top surface of the insulating layer 110 on the opening 241 side is denoted as a shape 241t. The shape of an end portion of the bottom surface of the conductive layer 212b on the opening 243 side is denoted as a shape 243b.

As illustrated in FIG. 1A, the shape 141t and the shape 143b can be the same or substantially the same. In that case, it is preferable that the end portion of the bottom surface of the conductive layer 112b on the opening 143 side be aligned with or substantially aligned with the end portion of the top surface of the insulating layer 110 on the opening 141 side as illustrated in FIG. 1B and the like. The bottom surface of the conductive layer 112b refers to the surface thereof on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface thereof on the conductive layer 112b side.

Note that the shape 141t and the shape 143b are not necessarily the same. In the case where the top-view shapes of the opening 141 and the opening 143 are circular, the opening 141 and the opening 143 may be concentrically arranged, but not necessarily concentrically arranged.

As illustrated in FIG. 1A, the shape 241t and the shape 243b can be the same or substantially the same. In that case, it is preferable that the end portion of the bottom surface of the conductive layer 212b on the opening 243 side be aligned with or substantially aligned with the end portion of the top surface of the insulating layer 110 on the opening 241 side as illustrated in FIG. 1B and the like. The bottom surface of the conductive layer 212b refers to the surface thereof on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface thereof on the conductive layer 212b side.

The shape 241t and the shape 243b are not necessarily the same. In the case where the top-view shapes of the opening 241 and the opening 243 are circular, the opening 241 and the opening 243 may be concentrically arranged, but not necessarily concentrically arranged.

The size of the opening 241 is greatly different between the shape of the end portion of the top surface of the insulating layer 110 on the opening 241 side and the shape of an end portion of the bottom surface of the insulating layer 110 on the opening 241 side. In FIG. 1A, the shape of the end portion of the bottom surface of the insulating layer 110 on the opening 241 side in the opening 241 is denoted by a shape 241b.

Each of the transistor 100 and the transistor 200 is what is called a top-gate transistor including the gate electrode above the semiconductor layer. Furthermore, since the bottom surface of the semiconductor layer is in contact with the source electrode and the drain electrode, the each of the transistors can be referred to as a TGBC (Top Gate Bottom Contact) transistor. In each of the transistor 100 and the transistor 200, the source electrode and the drain electrode are positioned at different levels with respect to a surface of the substrate 102 where each of the transistors is formed, and drain current flows in a direction perpendicular or substantially perpendicular to the surface of the substrate 102. In the transistor 100 and the transistor 200, drain current can also be regarded as flowing in the vertical direction or the substantially vertical direction. Accordingly, the transistor 100 can be referred to as a vertical-channel transistor or a VFET (Vertical Field Effect Transistor).

The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 and the angle between the sidewall of the opening 141 provided in the insulating layer 110 and the formation surface. The channel length of the transistor 200 can be controlled by the thickness of the insulating layer 110 and the angle between the sidewall of the opening 241 provided in the insulating layer 110 and the formation surface. Thus, as each of the transistor 100 and the transistor 200, a transistor having a channel length shorter than the resolution limit of a light-exposure apparatus used for manufacturing the transistor can be manufactured with high accuracy. Specifically, a transistor with an extremely short channel length that could not be achieved with a conventional light-exposure apparatus for mass production of flat panel displays (the minimum line width: approximately 2 μm or approximately 1.5 μm, for example) can be achieved. Moreover, it is also possible to obtain a transistor with a channel length shorter than 10 nm without using an extremely expensive light-exposure apparatus used in the latest LSI technology. Furthermore, variations in characteristics between a plurality of transistors 100 or between a plurality of transistors 200 are also reduced. Accordingly, the operation of the semiconductor device including the transistor 100 and the transistor 200 can be stabilized and the reliability thereof can be improved. When the variations in characteristics are reduced, the circuit design flexibility is increased and the operation voltage of the semiconductor device can be reduced. Thus, the power consumption of the semiconductor device can be reduced.

The reduction in the channel length can increase the on-state current of the transistor. With the use of the transistor, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a semiconductor device with a small size can be obtained. The application of the semiconductor device of one embodiment of the present invention to a large display device or a high-definition display device can reduce signal delay in wirings and reduce display unevenness even if the number of wirings is increased, for example. In addition, since the area occupied by the circuit can be reduced, the bezel of the display device can be narrowed.

In each of the transistor 100 and the transistor 200, the source electrode, the semiconductor layer, and the drain electrode can be provided to overlap with each other; thus, the area occupied by the transistor can be significantly smaller than the area occupied by a so-called planar transistor in which a planar semiconductor layer is placed.

Although FIG. 1B and the like illustrate an example in which an end portion of the semiconductor layer 108 is positioned over the conductive layer 112b and the semiconductor layer 108 includes a region in contact with the top surface of the conductive layer 112b, the present invention is not limited thereto. The semiconductor layer 108 may cover the end portion of the conductive layer 112b, the end portion of the semiconductor layer 108 may be positioned outward from the end portion of the conductive layer 112b, and the semiconductor layer 108 may include a region in contact with the top surface of the insulating layer 110. Similarly, FIG. 1B and the like illustrate an example in which an end portion of the semiconductor layer 208 is positioned over the conductive layer 212b and the semiconductor layer 208 includes a region in contact with the top surface of the conductive layer 212b; alternatively, the semiconductor layer 208 may cover the end portion of the conductive layer 212b, the end portion of the semiconductor layer 208 may be positioned outward from the end portion of the conductive layer 212b, and the semiconductor layer 208 may be in contact with the top surface of the insulating layer 110.

Although the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the opening 141 and the opening 143 in FIG. 1B and the like, one embodiment of the present invention is not limited thereto. A step may be formed between the conductive layer 112a and each of the insulating layer 110 and the conductive layer 112b, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 may be provided along the step. In the same manner, a step may be formed between the conductive layer 212a and each of the insulating layer 110 and the conductive layer 212b, and the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 may be provided along the step.

In the semiconductor device of one embodiment of the present invention, the transistor 100 with a short channel length and the transistor 200 with a long channel length can be separately formed. For example, the transistor 100 is used as a transistor required to have a high on-state current and the transistor 200 is used as a transistor required to have favorable saturation characteristics, thereby providing a high-performance semiconductor device.

In the semiconductor device of one embodiment of the present invention, the thickness of the gate insulating layer of the transistor 100 can be smaller than that of the gate insulating layer of the transistor 200. When the thickness of the gate insulating layer is reduced, the on-state current and the operation speed of the transistor can be increased. In addition, in the transistor 100, the gate insulating layer can be thinner and the channel length can be shorter, so that the on-state current and the operation speed of the transistor 100 can be further increased. The thickness of the gate insulating layer of the transistor 200 can be larger than that of the gate insulating layer of the transistor 100; thus, the gate breakdown voltage of the transistor 200 can be higher than that of the transistor 100. For example, when the transistor 200 is used as a transistor to which high voltages are applied and the transistor 100 is used as a transistor requiring high speed operation, a semiconductor device achieving both high speed operation and high reliability can be provided.

In the semiconductor device of one embodiment of the present invention, the thickness of the semiconductor layer 108 can be smaller than that of the semiconductor layer 208. When the thickness of the semiconductor layer is reduced, the diameter of the opening 141 can be reduced and the area occupied by the transistor 100 can be reduced, for example.

An insulating layer 195 is provided to cover the transistor 100 and the transistor 200. The insulating layer 195 functions as a protective layer for the transistor 100 and the transistor 200.

The detailed structures of the transistor 100 and the transistor 200 are described.

First, the detailed structure of the transistor 100 is described with reference to FIG. 5A and FIG. 5B.

In the semiconductor layer 108, a region in contact with the conductive layer 112a functions as one of the source region and the drain region, a region in contact with the conductive layer 112b functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

The channel length of the transistor 100 is a distance between the source region and the drain region. In FIG. 5B, the channel length L1 of the transistor 100 is indicated by a dashed double-headed arrow. It can be said that in a cross-sectional view, the channel length L1 is the shortest distance between a region of the semiconductor layer 108 that is in contact with the conductive layer 112a and a region of the semiconductor layer 108 that is in contact with the conductive layer 112b.

The channel length L1 of the transistor 100 corresponds to the length of the side surface of the insulating layer sandwiched between the conductive layer 112a and the conductive layer 112b on the opening 141 side in a cross-sectional view. That is, the channel length L1 is determined by a thickness T1 of the insulating layer sandwiched between the conductive layer 112a and the conductive layer 112b (here, the thickness of the insulating layer 110) and the angle th1 of the angle formed by the side surface of the insulating layer on the opening 141 side and the formation surface (here, the top surface of the conductive layer 112a).

In FIG. 5A and FIG. 5B, a width D143b of the shape 143b is denoted by a dashed double-dotted double-headed arrow as the width of the opening 143. FIG. 5A illustrates an example in which the top-view shapes of the opening 141 and the opening 143 are circular, and the width D143b corresponds to the diameter of the circle. A channel width W1 of the transistor 100 is the length of the circumference of this circle. That is, the channel width W1 is π×D143b. In the case where the opening 141 and the opening 143 have circular top-view shapes as described above, the channel width of the transistor can be smaller than in the case where the opening 141 and the opening 143 have any other shape such as a polygonal shape, for example. When the shape of the opening is a desired shape such as a circular shape or a polygonal shape in this manner, the channel width can be changed even when the diameter of the transistor is not greatly changed.

Note that the opening 141 and the opening 143 sometimes have different diameters.

Next, a detailed structure of the transistor 200 is described with reference to FIG. 6A, FIG. 6B, and FIG. 7.

In the semiconductor layer 208, a region in contact with the conductive layer 212a functions as one of the source region and the drain region, a region in contact with the conductive layer 212b functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

The channel length of the transistor 200 is a distance between the source region and the drain region. In FIG. 6B, the channel length L2 of the transistor 200 is indicated by a dashed double-headed arrow. It can be said that in a cross-sectional view, the channel length L2 is the shortest distance between a region of the semiconductor layer 208 that is in contact with the conductive layer 212a and a region of the semiconductor layer 208 that is in contact with the conductive layer 212b.

The channel length L2 of the transistor 200 corresponds to the length of the side surface of the insulating layer sandwiched between the conductive layer 212a and the conductive layer 212b on the opening 241 side in a cross-sectional view. That is, the channel length L2 is determined by the thickness T1 of the insulating layer sandwiched between the conductive layer 212a and the conductive layer 212b (here, the thickness of the insulating layer 110) and the angle th2 of the angle formed by the side surface of the insulating layer on the opening 241 side and the formation surface (here, the top surface of the conductive layer 212a).

In FIG. 6A and FIG. 6B, a width D243b of the shape 243b is denoted by a dashed double-dotted double-headed arrow as the width of the opening 243. FIG. 6A illustrates an example where the top-view shape of each of the opening 241 and the opening 243 is a circle.

Note that the opening 241 and the opening 243 sometimes have different diameters.

The diameter of the opening 141, the diameter of the opening 143, the diameter of the opening 241, and the diameter of the opening 243 sometimes varies from position to position in the depth direction. In particular, since the angle th2 is small in the transistor 200, a change in the depth direction in each of the diameter of the opening 241 and the diameter of the opening 243 is more significant in some cases. As the diameter of the opening, for example, the average value of the following three diameters can be used: the diameter at the highest level of the insulating layer 110 in a cross-sectional view, the diameter at the lowest level of the insulating layer 110 in a cross-sectional view, and the diameter at the midpoint between these levels. For another example, any of the diameter at the highest level of the insulating layer 110 in a cross-sectional view, the diameter at the lowest level of the insulating layer 110 in a cross-sectional view, and the diameter at the midpoint between these levels can be used as the diameter of the opening. As the width of the opening 241, FIG. 6A illustrates a width D241t at the highest position of the insulating layer 110 in a cross-sectional view and a width D241b at the lowest position of the insulating layer 110 in a cross-sectional view. The width D241t is larger than the width D241b.

In FIG. 6A, the top-view shape of the lower edge of the opening 243 is circular, and the width D243b corresponds to the diameter of the circle. The length of the circumference of the circle can be, for example, the channel width of the transistor 200 (hereinafter referred to as a channel width W2). The channel width W2 is π×D243b.

Alternatively, the channel width of the transistor 200 may be calculated using the length of the circumference of the lower edge of the opening 241. The top-view shape of the lower edge of the opening 241 is circular, and the width D241b corresponds to the diameter of the circle. The length of the circumference of the circle can be, for example, the channel width of the transistor 200 (hereinafter referred to as a channel width W2b). The channel width W2b is π×D241b.

Alternatively, the average value of the channel width W2 and the channel width W2b may be the channel width of the transistor 200.

In the case where the opening 241 and the opening 243 have circular top-view shapes, the channel width of the transistor can be smaller than in the case where the opening 241 and the opening 243 have any other shape.

In the structure illustrated in FIG. 6A and FIG. 6B, the width D243b is the same as the width D241t.

FIG. 8A illustrates an example in which an end portion of the insulating layer 110 on the semiconductor layer 208 side is positioned inward from an end portion of the conductive layer 212b on the semiconductor layer 208 side. In the structure illustrated in FIG. 8A, the width D241t is narrower than the width D243b. In the structure illustrated in FIG. 8A, the diameter of the end portion of the top surface of the insulating layer 110 on the opening 241 side is narrower than the diameter of the end portion of the bottom surface of the conductive layer 212b on the opening 243 side.

FIG. 8B illustrates an example in which the end portion of the conductive layer 212b on the semiconductor layer 208 side is positioned inward from the end portion of the insulating layer 110 on the semiconductor layer 208 side. In the structure illustrated in FIG. 8B, the width D241t is wider than the width D243b. In the structure illustrated in FIG. 8B, the diameter of the end portion of the top surface of the insulating layer 110 on the opening 241 side is wider than the diameter of the end portion of the bottom surface of the conductive layer 212b on the opening 243 side.

Although FIG. 5B and the like illustrate the structure in which the side surface of the insulating layer 110 on the opening 141 side is linear in the cross-sectional view, one embodiment of the present invention is not limited thereto. In the cross-sectional view, the side surface of the insulating layer 110 on the opening 141 side may be curved, or the side surface may include both a linear region and a curved region. Similarly, although FIG. 6B and the like illustrate the structure in which the side surface of the insulating layer 110 on the opening 241 side is linear in the cross-sectional view, one embodiment of the present invention is not limited thereto. In the cross-sectional view, the side surface of the insulating layer 110 on the opening 241 side may be curved, or the side surface may include both a linear region and a curved region. A curved region can include a variety of curves such as a convex curve and a concave curve. The side surface may include two or more linear regions. The side surface may include two or more curved regions.

FIG. 9A and FIG. 10A each illustrate an example in which the side surface of the insulating layer 110 on the opening 241 side has a curved region in a cross-sectional view of the transistor 200. FIG. 9B is an enlarged view of a region 43 illustrated in FIG. 9A, and FIG. 10B is an enlarged view of a region 44 illustrated in FIG. 10A.

FIG. 9A illustrates an example in which the side surface of the insulating layer 110 on the opening 241 side includes a region that is convexly curved outwardly from the insulating layer 110 in the cross-sectional view of the transistor 200. The angle th2 can be calculated as the angle between a tangent drawn to a line along the shape of the side surface of the insulating layer 110 and the formation surface (here, the top surface of the conductive layer 212a), for example. FIG. 9C illustrates an example in which the angle th2 is calculated by drawing a tangent to a region where the side surface of the insulating layer 110 is in contact with the top surface of the conductive layer 212a. FIG. 9D illustrates an example in which the angle th2 is calculated by drawing a tangent to a region of the insulating layer 110 in the vicinity of the midpoint in depth, and is smaller than the angle th2 in FIG. 9C.

FIG. 10A illustrates an example in which the side surface of the insulating layer 110 on the opening 241 side includes a region that is convexly curved inwardly from the insulating layer 110 (concavely curved outwardly from the insulating layer) in the cross-sectional view of the transistor 200. FIG. 10C illustrates an example in which the angle th2 is calculated by drawing a tangent to a region where the side surface of the insulating layer 110 is in contact with the top surface of the conductive layer 212a. FIG. 10D illustrates an example in which the angle th2 is calculated by drawing a tangent to a region of the insulating layer 110 in the vicinity of the midpoint in depth, and is larger than the angle th2 in FIG. 10C.

In the cross-sectional view of the transistor 200, an angle between a straight line connecting the end portions of top and bottom surfaces of the insulating layer 110 in the opening 241 and the top surface of the conductive layer 212a may be the angle th2.

The channel length L1 can be, for example, greater than or equal to 5 nm, greater than or equal to 7 nm, or greater than or equal to 10 nm and less than 3 μm, less than or equal to 2.5 μm, less than or equal to 2 μm, less than or equal to 1.5 μm, less than or equal to 1.2 μm, less than or equal to 1 μm, less than or equal to 500 nm, less than or equal to 300 nm, less than or equal to 200 nm, less than or equal to 100 nm, less than or equal to 50 nm, less than or equal to 30 nm, or less than or equal to 20 nm. For example, the channel length L1 can be greater than or equal to 100 nm and less than or equal to 1 μm.

By adjusting the thickness T1 and the angle th1, the channel length L1 can be controlled. The ratio between the channel length L2 and the channel length L1 can be controlled by adjusting the relation between the angle th1 and the angle th2. Note that in FIG. 5B and FIG. 6B, the thickness T1 is indicated by a dashed-dotted double-headed arrow.

The thickness T1 can be, for example, greater than or equal to 10 nm, greater than or equal to 50 nm, greater than or equal to 100 nm, greater than or equal to 150 nm, greater than or equal to 200 nm, greater than or equal to 300 nm, greater than or equal to 400 nm, or greater than or equal to 500 nm and less than 3.0 μm, less than or equal to 2.5 μm, less than or equal to 2.0 μm, less than or equal to 1.5 μm, less than or equal to 1.2 μm, or less than or equal to 1.0 μm.

The angle th1 is preferably 90° or a value in the vicinity thereof. Alternatively, the angle th1 is preferably greater than or equal to 55°, further preferably greater than or equal to 60°, still further preferably greater than or equal to 65°, yet still further preferably greater than or equal to 70°, yet still further preferably less than or equal to 90°. Alternatively, the angle th1 may be less than 90°, less than or equal to 85°, less than or equal to 80°, or less than or equal to 75°.

The angle th2 is preferably greater than 0° and less than the angle th1. The angle th2 is further preferably less than 55°, still further preferably less than or equal to 50°, yet still further preferably less than or equal to 45°, yet still further preferably less than or equal to 40°. The angle th2 may be greater than or equal to 10°, greater than or equal to 15°, or greater than or equal to 20°, for example.

The channel length L2 is, for example, greater than 1.2 times, greater than 1.3 times, greater than 1.4 times, or greater than 1.5 times the channel length L1.

The channel length L2 is, for example, less than or equal to 6 times, less than or equal to 4 times, or less than or equal to 3 times the channel length L1.

In the case where the opening 143 and the opening 243 are formed by a photolithography method, the width D143b of the opening 143 and the width D243b of the opening 243 are each larger than or equal to the resolution limit of a light-exposure apparatus. The width D143b can be, for example, greater than or equal to 20 nm, greater than or equal to 30 nm, greater than or equal to 50 nm, greater than or equal to 100 nm, greater than or equal to 200 nm, greater than or equal to 300 nm, greater than or equal to 400 nm, or greater than or equal to 500 nm and less than 5.0 μm, less than or equal to 4.5 μm, less than or equal to 4.0 μm, less than or equal to 3.5 μm, less than or equal to 3.0 μm, less than or equal to 2.5 μm, less than or equal to 2.0 μm, less than or equal to 1.5 μm, or less than or equal to 1.0 μm. The width D243b can be, for example, greater than or equal to 30 nm, greater than or equal to 50 nm, greater than or equal to 100 nm, greater than or equal to 200 nm, greater than or equal to 300 nm, greater than or equal to 400 nm, or greater than or equal to 500 nm and less than 5.0 μm, less than or equal to 4.5 μm, less than or equal to 4.0 μm, less than or equal to 3.5 μm, less than or equal to 3.0 μm, less than or equal to 2.5 μm, less than or equal to 2.0 μm, less than or equal to 1.5 μm, or less than or equal to 1.0 μm.

Although FIG. 1A, FIG. 1B, and the like illustrate an example in which the width D243b is larger than the width D143b, a structure in which the width D243b is substantially the same as the width D143b as illustrated in FIG. 3 may be employed. Alternatively, a structure in which the width D243b is smaller than the width D143b may be employed.

Next, the thickness of the gate insulating layer of the transistor 100 is described with reference to FIG. 5B. The insulating layer 106 sandwiched between the conductive layer 104 functioning as a gate electrode and the semiconductor layer 108 functions as a gate insulating layer. The thickness of the gate insulating layer is the shortest distance between the conductive layer 104 and the semiconductor layer 108 in a cross-sectional view.

The thickness of the gate insulating layer differs depending on the angle th1, the angle th2, and the formation method of the insulating layer 106 in some cases.

FIG. 11A is a diagram illustrating the thickness of the semiconductor layer of the transistor 100 and the thickness of the gate insulating layer of the transistor 100.

The thicknesses of the semiconductor layer 108 on the top surface of the conductive layer 112b, the side surface of the insulating layer 110 in the opening 141, and the top surface of the conductive layer 112a are a thickness B1, a thickness B2, and a thickness B3, respectively. The thickness B2 is sometimes smaller than the thickness B1. The thickness B2 is, for example, greater than or equal to 0.4 times and less than or equal to 0.85 times the thickness B1. The thickness B2 is sometimes smaller than the thickness B3. The thickness B2 is, for example, greater than or equal to 0.4 times and less than or equal to 0.85 times the thickness B3.

The thickness of the insulating layer 106 in the top surface of the conductive layer 112b, the side surface of the insulating layer 110 in the opening 141, and the top surface of the conductive layer 112a is a thickness A1, a thickness A2, and a thickness A3, respectively. The thickness A2 is sometimes smaller than the thickness A1. The thickness A2 is, for example, greater than or equal to 0.4 times and less than or equal to 0.85 times the thickness A1. The thickness A2 is sometimes smaller than the thickness A3. The thickness A2 is, for example, greater than or equal to 0.4 times and less than or equal to 0.85 times the thickness A3.

FIG. 11B is a diagram illustrating the thickness of the semiconductor layer of the transistor 200 and the thickness of the gate insulating layer of the transistor 200.

The thickness of the semiconductor layer 208 on the top surface of the conductive layer 212b, the side surface of the insulating layer 110 in the opening 241, and the top surface of the conductive layer 212a is a thickness B11, a thickness B12, and a thickness B13, respectively. The thickness B12 is, for example, greater than 0.85 times and less than 1.2 times the thickness B11. The thickness B12 is, for example, greater than 0.85 times and less than 1.2 times the thickness B13.

The thicknesses of the insulating layer 106 on the top surface of the conductive layer 212b, the side surface of the insulating layer 110 in the opening 241, and the top surface of the conductive layer 212a is a thickness A11, a thickness A12, and a thickness A13, respectively. The thickness A12 is, for example, greater than 0.85 times and less than 1.2 times the thickness A11. The thickness A12 is, for example, greater than 0.85 times and less than 1.2 times the thickness A3.

Components included in the semiconductor device of this embodiment will be described below.

There is no particular limitation on the semiconductor material used for each of the semiconductor layer 108 and the semiconductor layer 208. For example, a single-element semiconductor or a compound semiconductor can be used. Examples of the single-element semiconductor include silicon and germanium. Examples of the compound semiconductor include gallium arsenide and silicon germanium. Other examples of the compound semiconductor include an organic semiconductor, a nitride semiconductor, and an oxide semiconductor. These semiconductor materials may contain an impurity as a dopant.

There is no particular limitation on the crystallinity of the semiconductor material used for each of the semiconductor layer 108 and the semiconductor layer 208, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having other crystallinity than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor partly including crystal regions) may be used. A single crystal semiconductor or a semiconductor having crystallinity is preferably used, in which case deterioration of the transistor characteristics can be inhibited.

Each of the semiconductor layer 108 and the semiconductor layer 208 preferably includes a metal oxide exhibiting semiconductor characteristics (also referred to as an oxide semiconductor).

The band gap of a metal oxide used for each of the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, further preferably 2.5 eV or more.

Examples of the metal oxide that can be used for each of the semiconductor layer 108 and the semiconductor layer 208 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains two or three selected from indium, an element M, and zinc. The element M is a metal element or metalloid element that has a high bonding energy with oxygen, such as a metal element or metalloid element whose bonding energy with oxygen is higher than that of indium, for example. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M included in the metal oxide is preferably one or more kinds of the above elements, further preferably one or more kinds selected from aluminum, gallium, tin, and yttrium, and still further preferably gallium. In this specification and the like, a metal element and a metalloid element may be collectively referred to as a “metal element” and a “metal element” in this specification and the like may refer to a metalloid element.

For example, the semiconductor layer 108 and the semiconductor layer 208 can be formed using indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (also referred to as Ga—Zn oxide or GZO), aluminum zinc oxide (also referred to as Al—Zn oxide or AZO), indium aluminum zinc oxide (also referred to as In—Al—Zn oxide or IAZO), indium tin zinc oxide (also referred to as In—Sn—Zn oxide or ITZO (registered trademark)), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (also referred to as In—Ga—Zn oxide or IGZO), indium gallium tin zinc oxide (also referred to as In—Ga—Sn—Zn oxide or IGZTO), or indium gallium aluminum zinc oxide (also referred to as In—Ga—Al—Zn oxide, IGAZO, IGZAO, or IAGZO). Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like can be used.

When the proportion of the number of indium atoms in the total number of atoms of all the metal elements contained in the metal oxide is increased, the field-effect mobility of the transistor can be increased. In addition, the transistor can have a high on-state current.

Instead of indium or in addition to indium, the metal oxide may contain one or more kinds of metal elements with larger period numbers. The larger the overlap between orbits of metal elements is, the more likely it is that the metal oxide will have high carrier conductivity. Thus, when the transistor includes metal elements with larger period numbers, the field-effect mobility of the transistor can be increased in some cases. As examples of the metal element with a large period number, the metal elements belonging to Period 5 and those belonging to Period 6 are given. Specific examples of the metal element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare-earth elements.

The metal oxide may contain one or more kinds of nonmetallic elements. By containing a non-metallic element, the metal oxide sometimes has an increased carrier concentration, a reduced band gap, or the like, in which case the transistor can have increased field-effect mobility. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

By increasing the proportion of the number of zinc atoms in the total number of atoms of all the metal elements contained in the metal oxide, the metal oxide has high crystallinity, so that diffusion of impurities in the metal oxide can be inhibited. Consequently, a change in electrical characteristics of the transistor is suppressed and the transistor can have high reliability.

By increasing the proportion of the number of element M atoms in the total number of atoms of all the metal elements contained in the metal oxide, oxygen vacancies can be inhibited from being formed in the metal oxide. Accordingly, generation of carriers due to oxygen vacancies is inhibited, which makes the off-state current of the transistor low. Furthermore, a change in electrical characteristics of the transistor can be reduced to improve the reliability of the transistor.

Electrical characteristics and reliability of a transistor depend on the composition of the metal oxide used for each of the semiconductor layer 108 and the semiconductor layer 208. Therefore, by determining the composition of the metal oxide in accordance with the electrical characteristics and reliability required for the transistor, the semiconductor device can have both excellent electrical characteristics and high reliability.

A composition of a metal oxide can be analyzed by energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES), for example. Alternatively, such kinds of analysis methods may be performed in combination. Note that as for an element whose content percentage is low, the actual content percentage may be different from the content percentage obtained by analysis because of the influence of the analysis accuracy. In the case where the content percentage of the element Mis low, for example, the content percentage of the element M obtained by analysis may be lower than the actual content percentage.

When the metal oxide is an In-M-Zn oxide, the proportion of the number of In atoms is preferably higher than or equal to that of the number of M atoms in the In-M-Zn oxide. Examples of the atomic ratio of the metal elements of such an In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5 and a composition in the neighborhood of any of the above atomic ratios. Note that a composition in the neighborhood of an atomic ratio includes ±30% of an intended atomic ratio. By increasing the proportion of the number of indium atoms in the metal oxide, the on-state current, field-effect mobility, or the like of the transistor can be improved.

The proportion of the number of In atoms may be less than that of the number of M atoms in the In-M-Zn oxide. Examples of the atomic ratio of the metal elements of such an In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, and In:M:Zn=1:3:4 and a composition in the neighborhood of any of these atomic ratios. By increasing the proportion of the number of M atoms in the metal oxide, generation of oxygen vacancies can be suppressed.

In the case where a plurality of metal elements are contained as the element M, the sum of the proportions of the numbers of atoms of these metal elements can be used as the proportion of the number of element M atoms.

In this specification and the like, the proportion of the number of indium atoms in the total number of atoms of all the metal elements contained is sometimes referred to as indium content percentage. The same applies to other metal elements.

A sputtering method or an atomic layer deposition (ALD) method can be suitably used for forming a film of the metal oxide. Note that in the case where the metal oxide is formed by a sputtering method, the composition of the deposited metal oxide may be different from the composition of a target. In particular, the content of the zinc in the deposited metal oxide may be reduced to approximately 50% of that of the target.

The semiconductor layer 108 and the semiconductor layer 208 may each have a stacked-layer structure of two or more metal oxide layers. The two or more metal oxide layers included in each of the semiconductor layer 108 and the semiconductor layer 208 may have the same composition or substantially the same compositions. Employing a stacked-layer structure of metal oxide layers having the same composition can reduce the manufacturing cost because the metal oxide layers can be formed using the same sputtering target.

The two or more metal oxide layers included in each of the semiconductor layer 108 and the semiconductor layer 208 may have different compositions. For example, a stacked-layer structure of a first metal oxide layer having In:M:Zn=1:3:4 [atomic ratio] or a composition in the neighborhood thereof and a second metal oxide layer having In:M:Zn=1:1:1 [atomic ratio] or a composition in the neighborhood thereof and being formed over the first metal oxide layer can be suitably employed. In particular, gallium, aluminum, or tin is preferably used as the element M. A stacked-layer structure of one selected from indium oxide, indium gallium oxide, and IGZO, and one selected from IAZO, IAGZO, and ITZO (registered trademark) may be employed, for example.

The semiconductor layer 108 and the semiconductor layer 208 may each have a stacked-layer structure of two or more layers. The stacked-layer structure can be, for example, a three-layer structure in which the first layer is a semiconductor layer in which the atomic ratio of metal elements is In:Ga:Zn=1:1:1, the second layer is a semiconductor layer in which the atomic ratio of metal elements is In:Zn=4:1, and the third layer is a semiconductor layer in which the atomic ratio of metal elements is In:Ga:Zn=1:1:1. Note that the band gaps of the first-layer and third-layer semiconductor layers are preferably larger than the band gap of the second-layer semiconductor layer. With this structure, the main current path can be the second-layer semiconductor layer, so that what is called a buried channel structure can be obtained.

It is preferable that the semiconductor layer 108 and the semiconductor layer 208 each include a metal oxide layer having crystallinity. Examples of the structure of a metal oxide having crystallinity include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nano-crystal (nc) structure. By using a metal oxide layer having crystallinity as the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, which enables the semiconductor device to have high reliability.

The higher the crystallinity of the metal oxide layer used for each of the semiconductor layer 108 and the semiconductor layer 208 is, the lower the density of defect states in the semiconductor layer 108 can be. By contrast, the use of a metal oxide layer having low crystallinity enables a transistor to flow a large amount of current.

In the case where the metal oxide layer is formed by a sputtering method, the higher the substrate temperature (the stage temperature) in the formation is, the higher the crystallinity of the metal oxide layer can be. Furthermore, the higher the proportion of a flow rate of an oxygen gas in the whole deposition gas (also referred to as an oxygen flow rate ratio) used in the formation is, the higher the crystallinity of the metal oxide layer can be.

The semiconductor layer 108 and the semiconductor layer 208 may each have a stacked-layer structure of two or more metal oxide layers having different crystallinities. For example, a stacked-layer structure of a first metal oxide layer and a second metal oxide layer provided over the first metal oxide layer can be employed; the second metal oxide layer can include a region having higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer can include a region having lower crystallinity than the first metal oxide layer. In that case, the composition of the first metal oxide layer may be different from, the same as, or substantially the same as that of the second metal oxide layer.

The thickness of each of the semiconductor layer 108 and the semiconductor layer 208 is preferably greater than or equal to 1 nm and less than or equal to 200 nm, further preferably greater than or equal to 3 nm and less than or equal to 100 nm, still further preferably greater than or equal to 5 nm and less than or equal to 100 nm, yet still further preferably greater than or equal to 10 nm and less than or equal to 100 nm, yet still further preferably greater than or equal to 10 nm and less than or equal to 70 nm, yet still further preferably greater than or equal to 15 nm and less than or equal to 70 nm, yet still further preferably greater than or equal to 15 nm and less than or equal to 50 nm, yet still further preferably greater than or equal to 20 nm and less than or equal to 50 nm. The thicknesses of the semiconductor layer 108 and the semiconductor layer 208 may be the same or different from each other.

Note that the thickness of each of the semiconductor layer 108 and the semiconductor layer 208 may vary from region to region. In some cases, the thickness of each of the semiconductor layer 108 and the semiconductor layer 208 is greater than or equal to 0.4 times and less than 1.2 times the above-described thickness range, depending on the region, for example.

In the case where the semiconductor layer 108 and the semiconductor layer 208 are formed using an oxide semiconductor, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus sometimes forms an oxygen vacancy (VO) in the oxide semiconductor. In some cases, a defect that is an oxygen vacancy into which hydrogen enters (hereinafter referred to as VOH) functions as a donor and generates an electron serving as a carrier. In other cases, bonding of part of hydrogen to oxygen bonded to a metal atom generates electrons serving as carriers. Thus, a transistor including an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics. Moreover, hydrogen in an oxide semiconductor is easily transferred by a stress such as heat or an electric field; thus, a large amount of hydrogen in an oxide semiconductor might reduce the reliability of a transistor.

In the case where an oxide semiconductor is used for each of the semiconductor layer 108 and the semiconductor layer 208, the amount of VOH in each of the semiconductor layer 108 and the semiconductor layer 208 are preferably reduced as much as possible so that the semiconductor layer 108 and the semiconductor layer 208 become a highly purified intrinsic or substantially highly purified intrinsic semiconductor layer. In order to obtain such an oxide semiconductor with sufficiently reduced VOH, it is important to remove impurities such as water and hydrogen in the oxide semiconductor (which is sometimes described as dehydration or dehydrogenation treatment) and to repair oxygen vacancies by supplying oxygen to the oxide semiconductor. When an oxide semiconductor with a sufficiently reduced amount of impurities such as VOH is used for the channel formation region of the transistor, the transistor can have stable electrical characteristics. Note that repairing oxygen vacancies by supplying oxygen to an oxide semiconductor is sometimes referred to as oxygen adding treatment.

When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, the carrier concentration of the oxide semiconductor in the region functioning as the channel formation region is preferably lower than or equal to 1×1018 cm−3, further preferably lower than 1×1017 cm−3, still further preferably lower than 1×1016 cm−3, yet still further preferably lower than 1×1013 cm−3, yet still further preferably lower than 1×1012 cm−3. Note that the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as the channel formation region is not particularly limited and can be, for example, 1× 10−9 cm−3.

A transistor including an oxide semiconductor (hereinafter referred to as an OS transistor) has much higher field-effect mobility than a transistor including amorphous silicon. In addition, the OS transistor has an extremely low off-state current, and charge accumulated in a capacitor that is connected in series to the transistor can be held for a long period. Furthermore, a semiconductor device can have lower power consumption by including the OS transistor.

A change in electrical characteristics of an OS transistor due to irradiation with radiation is small, i.e., an OS transistor has high resistance to radiation; thus, an OS transistor can be suitably used even in an environment where radiation might enter. It can also be said that an OS transistor has high reliability against radiation. For example, an OS transistor can be suitably used for a pixel circuit of an X-ray flat panel detector. Moreover, an OS transistor can be suitably used for a semiconductor device used in space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, a proton beam, and a neutron beam).

Examples of silicon that can be used for each of the semiconductor layer 108 and the semiconductor layer 208 include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

The transistor using amorphous silicon for each of the semiconductor layer 108 and the semiconductor layer 208 can be formed over a large glass substrate, and can be manufactured at low cost. The transistor including polycrystalline silicon in each of the semiconductor layer 108 and the semiconductor layer 208 has high field-effect mobility and enables high-speed operation. The transistor including microcrystalline silicon in each of the semiconductor layer 108 and the semiconductor layer 208 has higher field-effect mobility and enables higher speed operation than the transistor including amorphous silicon.

The semiconductor layer 108 and the semiconductor layer 208 may each contain a layered material functioning as a semiconductor. The layered material generally refers to a group of materials having a layered crystal structure. In the layered crystal structure, layers formed by covalent bonding or ionic bonding are stacked with bonding such as the van der Waals binding, which is weaker than covalent bonding or ionic bonding. The layered material has high electrical conductivity in a unit layer, that is, high two-dimensional electrical conductivity. When a material that functions as a semiconductor and has high two-dimensional electrical conductivity is used for a channel formation region, a transistor having a high on-state current can be provided.

Examples of the layered material include graphene, silicene, and chalcogenide. Chalcogenide is a compound containing chalcogen (an element belonging to Group 16). Examples of chalcogenide include transition metal chalcogenide and chalcogenide of Group 13 elements. Specific examples of the transition metal chalcogenide which can be used for a semiconductor layer of a transistor include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

The semiconductor layer 108 is preferably formed in the same step as the semiconductor layer 208. Therefore, the same material is preferably used for the semiconductor layer 108 and the semiconductor layer 208.

Alternatively, the semiconductor layer 108 and the semiconductor layer 208 may be formed in different steps. In that case, the material used for the semiconductor layer 108 can be different from that used for the semiconductor layer 208.

The layers constituting the insulating layer 110 are preferably formed using inorganic insulating films. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film.

Note that in this specification and the like, an oxynitride refers to a material that contains more oxygen than nitrogen in its composition. A nitride oxide refers to a material that contains more nitrogen than oxygen in its composition. For example, silicon oxynitride refers to a material that contains more oxygen than nitrogen in its composition, and silicon nitride oxide refers to a material that contains more nitrogen than oxygen in its composition.

A composition can be analyzed by secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), auger electron spectroscopy (AES), or energy dispersive X-ray spectroscopy (EDX), for example. When the content percentage of a target element is high (e.g., higher than or equal to 0.5 atomic %, or higher than or equal to 1 atomic %), XPS can be suitably used, for example. In contrast, when the content percentage of a target element is low (e.g., lower than or equal to 0.5 atomic %, or lower than or equal to 1 atomic %), SIMS can be suitably used. For analysis of a composition, a plurality of analysis methods are preferably used. For example, it is further preferable to perform a combined analysis of SIMS and XPS.

The insulating layer 110 includes a portion that is in contact with the semiconductor layer 108. In the case where the semiconductor layer 108 is formed using an oxide semiconductor, at least part of the portion of the insulating layer 110 that is in contact with the semiconductor layer 108 is preferably formed using an oxide to improve the characteristics of the interface between the semiconductor layer 108 and the insulating layer 110. Specifically, the portion of the insulating layer 110 that is in contact with a channel formation region of the semiconductor layer 108 is preferably formed using an oxide. The channel formation region is a high-resistance region having a low carrier concentration. The channel formation region can be regarded as being i-type (intrinsic) or substantially i-type.

As the insulating layer 110b, a layer containing oxygen is preferably used. It is preferable that the insulating layer 110b include a region having a higher oxygen content than at least one of the insulating layer 110a and the insulating layer 110c. It is particularly preferable that the insulating layer 110b include a region having a higher oxygen content than each of the insulating layer 110a and the insulating layer 110c.

The insulating layer 110b is preferably formed using any one or more of the oxide insulating films and oxynitride insulating films described above. Specifically, the insulating layer 110b is preferably formed using one or both of a silicon oxide film and a silicon oxynitride film. By having a high oxygen content, the insulating layer 110b can facilitate formation of an i-type region in the region of the semiconductor layer 108 that is in contact with the insulating layer 110b and the vicinity of this region.

It is further preferable that a film from which oxygen is released by heating be used as the insulating layer 110b. When the insulating layer 110b releases oxygen by being heated during the manufacturing process of the transistor 100, the oxygen can be supplied to the semiconductor layer 108. The oxygen supply from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region of the semiconductor layer 108, reduces the amount of oxygen vacancies (VO) and VOH in the semiconductor layer 108, so that the transistor can have favorable electrical characteristics and high reliability.

For example, the insulating layer 110b can be supplied with oxygen when heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere is performed. Alternatively, an oxide film may be formed over the top surface of the insulating layer 110b by a sputtering method in an oxygen atmosphere to supply oxygen. After that, the oxide film may be removed.

The insulating layer 110b is preferably formed by a film formation method such as a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, a film is formed by a sputtering method as a film formation method that does not use a hydrogen gas for a film formation gas, so that a film with an extremely low hydrogen content can be formed. In that case, supply of hydrogen to the semiconductor layer 108 is inhibited and the electrical characteristics of the transistor 100 can be stabilized.

As described above, the channel length L1 of the transistor 100 can be extremely short. Particularly in the case where the channel length L1 is short, oxygen vacancy (VO) and VOH in the channel formation region greatly affect electrical characteristics and reliability. However, supply of oxygen from the insulating layer 110b to the semiconductor layer 108 can inhibit an increase in the amount of oxygen vacancies (VO) and VOH at least in the region of the semiconductor layer 108 in contact with the insulating layer 110b. Thus, the transistor with a short channel length can have favorable electrical characteristics and high reliability.

As each of the insulating layer 110a and the insulating layer 110c, a film through which oxygen hardly diffuses is preferably used. Accordingly, it is possible to prevent oxygen included in the insulating layer 110b from being transmitted toward the substrate 102 side through the insulating layer 110a and being transmitted toward the insulating layer 106 side through the insulating layer 110c due to heating. In other words, when the upper and lower sides of the insulating layer 110b are sandwiched between the insulating layer 110a and the insulating layer 110c, which do not easily allow diffusion of oxygen, oxygen included in the insulating layer 110b can be enclosed. Accordingly, oxygen can be effectively supplied to the semiconductor layer 108.

As each of the insulating layer 110a and the insulating layer 110c, a film through which hydrogen hardly diffuses is preferably used. In that case, hydrogen can be inhibited from diffusing from outside the transistor to the semiconductor layer 108 through the insulating layer 110a or the insulating layer 110c.

As each of the insulating layer 110a and the insulating layer 110c, any one or more of the oxide insulating film, nitride insulating film, oxynitride insulating film, and nitride oxide insulating film described above is preferably used and any one or more of a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, an aluminum nitride film, a hafnium oxide film, and a hafnium aluminate film is preferably used. Specifically, a silicon nitride film and a silicon nitride oxide film can be suitably used as each of the insulating layer 110a and the insulating layer 110c because the amount of impurities (e.g., water and hydrogen) released from a silicon nitride film and a silicon nitride oxide film themselves is small and a silicon nitride film and a silicon nitride oxide film have a feature that oxygen and hydrogen are less likely to be transmitted. For the insulating layer 110a and the insulating layer 110c, the same material or different materials may be used.

Here, the conductive layer 112a and the conductive layer 112b are oxidized by oxygen included in the insulating layer 110b and have high resistance in some cases. Providing the insulating layer 110a between the insulating layer 110b and the conductive layer 112a can inhibit the conductive layer 112a from being oxidized and having high resistance. In addition, providing the insulating layer 110c between the insulating layer 110b and the conductive layer 112b can inhibit the conductive layer 112b from being oxidized and having high resistance. Accordingly, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 is increased, whereby the amount of oxygen vacancy in the semiconductor layer 108 can be reduced.

The thickness of each of the insulating layer 110a and the insulating layer 110c is preferably greater than or equal to 5 nm and less than or equal to 150 nm, further preferably greater than or equal to 5 nm and less than or equal to 100 nm, still further preferably greater than or equal to 5 nm and less than or equal to 70 nm, yet still further preferably greater than or equal to 10 nm and less than or equal to 70 nm, yet still further preferably greater than or equal to 10 nm and less than or equal to 50 nm, yet still further preferably greater than or equal to 20 nm and less than or equal to 50 nm. When the thickness of each of the insulating layer 110a and the insulating layer 110c is in the above-described range, the amount of oxygen vacancies in the semiconductor layer 108, or specifically the channel formation region, can be reduced.

It is preferable that, for example, the insulating layer 110a and the insulating layer 110c be formed using silicon nitride films and the insulating layer 110a be formed using a silicon oxynitride film.

Note that although a structure where the insulating layer 110 has a three-layer structure is described in this embodiment, one embodiment of the present invention is not limited to this. The insulating layer 110 may have a single-layer structure or a stacked-layer structure of two or four or more layers. The insulating layer 110 preferably includes at least the insulating layer 110b.

A film from which hydrogen is released by heating may be used as the insulating layer 110c. When the insulating layer 110c releases hydrogen by being heated during the manufacturing process of the transistor 100, the hydrogen can be supplied to the semiconductor layer 108 and the semiconductor layer 208. Thus, a low-resistance region can be formed in each of the vicinity of a region of the semiconductor layer 108 that is in contact with the conductive layer 112b in the transistor 100 and the vicinity of a region of the semiconductor layer 208 that is in contact with the conductive layer 212b in the transistor 200.

Similarly, when a film from which hydrogen is released by heating is used as the insulating layer 110a, a low-resistance region can be formed in each of the vicinity of a region of the semiconductor layer 108 that is in contact with the conductive layer 112a in the transistor 100 and the vicinity of a region of the semiconductor layer 208 that is in contact with the conductive layer 212a in the transistor 200.

As the insulating layer 110b, a film with a low hydrogen content is preferably used. When the insulating layer 110b is a film with a low hydrogen content, diffusion of hydrogen into a region of the semiconductor layer 108 where a gate electric field is sufficiently applied (a region that is intended to be of an i-type) can be inhibited, so that the channel formation region can be an i-type region.

FIG. 12A is an enlarged view of the region 41 illustrated in FIG. 5B, and FIG. 12B is an enlarged view of the region 42 illustrated in FIG. 6B. FIG. 12A and FIG. 12B illustrate an example of the case where a film from which hydrogen is released by heating is used as each of the insulating layer 110a and the insulating layer 110c.

As illustrated in FIG. 12A, in the semiconductor layer 108 of the transistor 100, the resistance of each of the region in contact with the insulating layer 110a and the region in contact with the insulating layer 110c is reduced and each of the regions does not serve as a channel formation region, so that the channel formation region is shorter than that in FIG. 5C. As illustrated in FIG. 12B, in the semiconductor layer 208 of the transistor 200, the resistance of each of the region in contact with the insulating layer 110a and the region in contact with the insulating layer 110c is reduced and each of the regions does not serve as a channel formation region, so that the channel formation region is shorter than that in FIG. 7.

In the structure example of the transistor 100 illustrated in FIG. 12A, in the case where the conductive layer 112a functions as a drain electrode, the semiconductor layer 108 can be regarded as including a low-resistance region between a region in contact with the drain electrode and the channel formation region. Owing to this structure, a high electric field is not easily generated in the vicinity of a drain region, and generation of hot carriers and degradation of the transistor can be inhibited. In addition, in the case where the conductive layer 112b functions as a drain electrode, the semiconductor layer 108 can be regarded as including a low-resistance region between a region in contact with the drain electrode and the channel formation region. Owing to this structure, a high electric field is not easily generated in the vicinity of the drain region, and generation of hot carriers and degradation of the transistor can be inhibited. The transistor 100 can have high reliability irrespective of whether the conductive layer 112a or the conductive layer 112b is the drain electrode. Accordingly, the design flexibility of the semiconductor device can be increased.

In the structure example of the transistor 200 illustrated in FIG. 12B, in the case where the conductive layer 212a functions as a drain electrode, the semiconductor layer 208 can be regarded as including a low-resistance region between a region in contact with the drain electrode and the channel formation region. Owing to this structure, a high electric field is not easily generated in the vicinity of the drain region, and generation of hot carriers and degradation of the transistor can be inhibited. In the case where the conductive layer 212b functions as a drain electrode, the semiconductor layer 208 can be regarded as including the low-resistance region between a region in contact with the drain electrode and the channel formation region. Owing to this structure, a high electric field is not easily generated in the vicinity of the drain region, and generation of hot carriers and degradation of the transistor can be inhibited. The transistor 200 can have high reliability irrespective of whether the conductive layer 212a or the conductive layer 212b is the drain electrode. Accordingly, the design flexibility of the semiconductor device can be increased.

The insulating layer 110c can also have a stacked-layer structure of two or more layers. For example, the insulating layer 110c can have a stacked-layer structure including two layers of an insulating layer 110cl and an insulating layer 110c2 over the insulating layer 110c1.

The insulating layer 110a can also have a stacked-layer structure of two or more layers. For example, the insulating layer 110a can have a stacked-layer structure including two layers of an insulating layer 110al and an insulating layer 110a2 over the insulating layer 110al.

FIG. 13A is an enlarged view of the region 41 illustrated in FIG. 5B. FIG. 13B is an enlarged view of the region 42 illustrated in FIG. 6B. FIG. 13A and FIG. 13B each illustrate an example of a case where the insulating layer 110a has a stacked-layer structure including two layers of the insulating layer 110al and the insulating layer 110a2 over the insulating layer 110a1 and the insulating layer 110c has a stacked-layer structure including two layers of the insulating layer 110c1 and the insulating layer 110c2 over the insulating layer 110c1.

A film from which hydrogen is released by heating is preferably used as the insulating layer 110c2. Accordingly, a low-resistance region can be formed in each of the vicinity of the semiconductor layer 108 in contact with the conductive layer 112b in the transistor 100 and the vicinity of a region of the semiconductor layer 208 in contact with the conductive layer 212b in the transistor 200. In the case where the conductive layer 112b and the conductive layer 212b are used as the drain electrode of the transistor 100 and the drain electrode of the transistor 200, respectively, generation of hot carriers can be inhibited.

The insulating layer 110cl preferably includes a region having a lower hydrogen content than the insulating layer 110c2. Accordingly, diffusion of hydrogen from the insulating layer 110c2 to a region where a gate electric field is sufficiently applied (a region that is intended to be of an i-type) in the insulating layer 110b and the semiconductor layer of the transistor (the semiconductor layer 108 of the transistor 100 or the semiconductor layer 208 of the transistor 200) can be inhibited.

A film from which hydrogen is released by heating is preferably used as the insulating layer 110a1. Accordingly, a low-resistance region can be formed in each of the vicinity of the semiconductor layer 108 in contact with the conductive layer 112a in the transistor 100 and the vicinity of the region of the semiconductor layer 208 in contact with the conductive layer 212a in the transistor 200; in the case where the conductive layer 112a and the conductive layer 212a are used as the drain electrode of the transistor 100 and the drain electrode of the transistor 200, respectively, generation of hot carriers can be inhibited.

The insulating layer 110a2 preferably includes a region having a lower hydrogen content than the insulating layer 110al. Accordingly, diffusion of hydrogen from the insulating layer 110al to a region where a gate electric field is sufficiently applied (a region that is intended to be of an i-type) in the insulating layer 110b and the semiconductor layer of the transistor (the semiconductor layer 108 of the transistor 100 or the semiconductor layer 208 of the transistor 200) can be inhibited.

As the film from which hydrogen is released by heating, any one or more of the oxide insulating film, nitride insulating film, oxynitride insulating film, and nitride oxide insulating film described above can be used, and any one or more of a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, an aluminum nitride film, a hafnium oxide film, and a hafnium aluminate film can be used.

As the film from which hydrogen is released by heating, any one or more of a nitride insulating film and a nitride oxide insulating film is preferably used. Specifically, one or both of a silicon nitride film and a silicon nitride oxide film is preferably used.

Note that when deposition conditions (e.g., a deposition gas and power at the time of deposition) and the like are changed, the silicon nitride film and the silicon nitride oxide film can be films from which a large amount of hydrogen is released. Moreover, by changing the deposition conditions and the like, the silicon nitride film and the silicon nitride oxide film can be films where the amount of impurities (e.g., water and hydrogen) released from themselves is small and oxygen and hydrogen are less likely to be transmitted.

Thus, in the case where the silicon nitride film and the silicon nitride oxide film are used as the insulating layer 110al and the insulating layer 110c2, a film from which a large amount of hydrogen is released may be used. In the case where the silicon nitride film and the silicon nitride oxide film are used as the insulating layer 110a2 and the insulating layer 110c1, a film from which the amount of impurities (e.g., water and hydrogen) released from themselves is small and oxygen and hydrogen are less likely to be transmitted may be used.

The hydrogen content of the insulating layer is lower than the content of each of the main components constituting the insulating layer (e.g., nitrogen and silicon in a silicon nitride layer); thus, the hydrogen content of the layers constituting the insulating layer 110 is preferably compared through SIMS analysis.

Furthermore, even when the layers constituting the insulating layer 110 are layers having the same main component (e.g., a silicon nitride layer), two layers can be distinguished from each other in some cases by a difference in brightness or the like by cross-sectional observation using a scanning transmission electron microscopy (STEM) or the like. For example, in a transmitted electron (TE) image, a silicon nitride film (or a silicon nitride oxide film) that releases a large amount of hydrogen is sometimes observed to have higher brightness than a silicon nitride film (or a silicon nitride oxide film) that releases fewer impurities (e.g., water and hydrogen) from itself and is less likely to transmit oxygen and hydrogen.

The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may each have a single-layer structure or a stacked-layer structure of two or more layers. As a material that can be used for each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, ruthenium, and niobium, or an alloy containing one or more of these metals as its components can be given. For each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, a conductive material with low resistance that contains one or more of copper, silver, gold, and aluminum can be suitably used. Copper or aluminum is particularly preferable because of its high mass-productivity.

For each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, a conductive metal oxide (also referred to as an oxide conductor) can be used. Examples of an oxide conductor (OC) include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon or ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. A conductive oxide containing indium is particularly preferable because of its high conductivity.

When an oxygen vacancy is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen vacancy, a donor level is formed in the vicinity of the conduction band. As a result, the conductivity of the metal oxide is increased, and thus, the metal oxide becomes a conductor. The metal oxide having become a conductor can be referred to as an oxide conductor.

The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may each have a stacked-layer structure of a conductive film containing the above-described oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. The use of the conductive film containing a metal or an alloy can reduce the wiring resistance.

A Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b. The use of a Cu—X alloy film can reduce the manufacturing cost because a wet etching method can be used in the processing.

Note that all of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may be formed using the same material or at least one of them may be formed using a different material.

Note that in this specification and the like, different materials mean materials having different constituent elements or materials having the same constituent element and different compositions.

Each of the conductive layer 112a and the conductive layer 112b has a region that is in contact with the semiconductor layer 108. Each of the conductive layer 212a and the conductive layer 212b has a region that is in contact with the semiconductor layer 208. In the case where the semiconductor layer 108 is formed using an oxide semiconductor, when the conductive layer 112a or the conductive layer 112b is formed using a metal that is likely to be oxidized (e.g., aluminum), an insulating oxide (e.g., aluminum oxide) is formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, which might prevent electrical continuity between the conductive layer 112a or a conductive layer 112b and the semiconductor layer 108. Therefore, the conductive layer 112a and the conductive layer 112b are preferably formed using a conductive material that is less likely to be oxidized or a conductive material that maintains low electric resistance even after being oxidized. In the case where the semiconductor layer 208 is formed using an oxide semiconductor, the same applies to the conductive layer 212a and the conductive layer 212b, and each of the conductive layer 212a and the conductive layer 212b is preferably formed using a conductive material that is less likely to be oxidized or a conductive material that maintains low electric resistance even after being oxidized.

For each of the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b, for example, one or more of titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel is preferably used. These materials are preferable because they are conductive materials that are less likely to be oxidized or conductive materials that maintain low electric resistance even after being oxidized.

The conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b can each be formed using any of the above-described oxide conductors. Specifically, one or more of indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide to which gallium is added can be used.

A nitride conductor may be used for each of the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b. For example, one or more of tantalum nitride and titanium nitride can be used.

The conductive layer 112a and the conductive layer 112b may each have a stacked-layer structure. In the case of the stacked-layer structure, at least a layer on the side that is in contact with the semiconductor layer 108 is preferably formed using a conductive material that is less likely to be oxidized or a conductive material that maintains low electric resistance even after being oxidized. For example, the conductive layer 112a can have a stacked-layer structure of an aluminum film and a titanium film over the aluminum film. The titanium film includes a region in contact with the semiconductor layer 108. The conductive layer 112a can have a stacked-layer structure of a first titanium film, an aluminum film over the first titanium film, and a second titanium film over the aluminum film. The second titanium film includes a region in contact with the semiconductor layer 108.

The conductive layer 212a and the conductive layer 212b may each have a stacked-layer structure. In the case of the stacked-layer structure, at least a layer on the side that is in contact with the semiconductor layer 208 is preferably formed using a conductive material that is less likely to be oxidized or a conductive material that maintains low electric resistance even after being oxidized. For example, the conductive layer 212a can have a stacked-layer structure of an aluminum film and a titanium film over the aluminum film. The titanium film includes a region in contact with the semiconductor layer 208. The conductive layer 212a can have a stacked-layer structure of a first titanium film, an aluminum film over the first titanium film, and a second titanium film over the aluminum film. The second titanium film includes a region in contact with the semiconductor layer 208.

The insulating layer 106 may have a single-layer structure or a stacked-layer structure of two or more layers. The insulating layer 106 preferably includes one or more inorganic insulating films. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. And for the insulating layer 106, the material that can be used for the insulating layer 110 can be used.

The insulating layer 106 includes a region that is in contact with the semiconductor layer 108 and the semiconductor layer 208. In the case where the semiconductor layer 108 and the semiconductor layer 208 are formed using an oxide semiconductor, at least the film of the insulating layer 106 that is in contact with the semiconductor layer 108 or the semiconductor layer 208 is preferably any of the above-described oxide insulating films and oxynitride insulating films. A film from which oxygen is released by heating is further preferably used as the insulating layer 106.

Specifically, in the case where the insulating layer 106 has a single-layer structure, the insulating layer 106 is preferably formed using a silicon oxide film or a silicon oxynitride film.

The insulating layer 106 can have a stacked-layer structure of an oxide insulating film or an oxynitride insulating film on the side that is in contact with the semiconductor layer 108 and a nitride insulating film or a nitride oxide insulating film on the side that is in contact with the conductive layer 104 and the conductive layer 204. As the oxide insulating film or the oxynitride insulating film, for example, a silicon oxide film or a silicon oxynitride film is preferably used. As the nitride insulating film or the nitride oxide insulating film, a silicon nitride film or a silicon nitride oxide film is preferably used.

A silicon nitride film and a silicon nitride oxide film can be suitably used as the insulating layer 106 because the amount of impurities (e.g., water and hydrogen) released from the silicon nitride film and the silicon nitride oxide film themselves is small and have a feature that oxygen and hydrogen are less likely to be transmitted. Diffusion of impurities from the insulating layer 106 to the semiconductor layer 108 and the semiconductor layer 208 is inhibited, whereby the transistor can have favorable electrical characteristics and high reliability.

A miniaturized transistor including a thin gate insulating layer may have a high leakage current. When a high dielectric constant material (also referred to as a high-k material) is used for the gate insulating layer, the voltage at the time of operation of the transistor can be reduced while the physical thickness is maintained. Examples of the high-k material usable for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

It is preferable to use a material that does not easily allow diffusion of impurities for the insulating layer 195 functioning as a protective layer of the transistor 100 and the transistor 200. Providing the insulating layer 195 can effectively inhibit diffusion of impurities into the transistors from the outside and increase the reliability of the display device. Examples of the impurities include water and hydrogen.

The insulating layer 195 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as an oxide, an oxynitride, a nitride oxide, or a nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. As the organic material, for example, one or more of an acrylic resin and a polyimide resin can be used. As the organic material, a photosensitive material may be used. A stack including two or more of the above insulating films may also be used. The insulating layer 195 may have a stacked-layer structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

Although there is no great limitation on a material of the substrate 102, it is necessary that the substrate have heat resistance high enough to withstand at least heat treatment performed later. For example, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate of silicon or silicon carbide, a compound semiconductor substrate of silicon germanium or the like, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102. The substrate 102 may be provided with a semiconductor element. Note that the shape of the semiconductor substrate and an insulating substrate may be circular or square.

A flexible substrate may be used as the substrate 102, and the transistor 100, the transistor 200, and the like may be formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and each of the transistor 100 and the transistor 200, for example. With the separation layer, part or the whole of a semiconductor device completed thereover can be separated from the substrate 102 and transferred onto another substrate. In such a case, the transistor 100, the transistor 200, and the like can be transferred onto a substrate having low heat resistance or a flexible substrate as well.

Structure Example 2

FIG. 4A is a top view of the semiconductor device 10 of one embodiment of the present invention. FIG. 4B is a cross-sectional view of a cross section along the dashed-dotted line A1-A2 in FIG. 4A.

The semiconductor device 10 illustrated in FIG. 4A and FIG. 4B includes the transistor 100 and the transistor 200. The semiconductor device 10 is different from the semiconductor device 10 illustrated in FIG. 1A, FIG. 1B, and the like mainly in including a conductive layer 103, a conductive layer 203, and an insulating layer 107.

The transistor 100 illustrated in FIG. 4A and FIG. 4B includes the conductive layer 103 and the insulating layer 107 between the conductive layer 112a and the insulating layer 110. The transistor 200 illustrated in FIG. 4A and FIG. 4B includes the conductive layer 203 and the insulating layer 107 between the conductive layer 212a and the insulating layer 110.

The insulating layer 107 includes a region positioned over the conductive layer 112a and a region positioned over the conductive layer 212a. The insulating layer 107 includes a region provided to cover the top surface and the side surface of the conductive layer 112a and a region provided to cover the top surface and the side surface of the conductive layer 212a.

The conductive layer 103 is positioned over the insulating layer 107. The conductive layer 112a and the conductive layer 103 are electrically insulated from each other by the insulating layer 107. In the conductive layer 103, an opening 148 reaching the insulating layer 107 is provided in a region overlapping with the conductive layer 112a.

The conductive layer 203 is positioned over the insulating layer 107. The conductive layer 212a and the conductive layer 203 are electrically insulated from each other by the insulating layer 107. In the conductive layer 203, an opening 248 reaching the insulating layer 107 is provided in a region overlapping with the conductive layer 212a.

The insulating layer 110 is provided over the insulating layer 107, the conductive layer 103, and the conductive layer 203. The insulating layer 110 is provided so as to cover the top surface and a side surface of the conductive layer 103, the top surface and a side surface of the conductive layer 203, and the top surface of the insulating layer 107. The opening 141 reaching the conductive layer 112a is provided in each of the insulating layer 110 and the insulating layer 107 in a region overlapping with the conductive layer 112a. In the insulating layer 110 and the insulating layer 107, the opening 241 reaching the conductive layer 212a is provided in each of the insulating layer 110 and the insulating layer 107 in a region overlapping with the conductive layer 212a.

The insulating layer 110a is positioned over the insulating layer 107, the conductive layer 103, and the conductive layer 203. The insulating layer 110a includes a region provided to cover the top surface and the side surface of the conductive layer 103 and a region provided to cover the top surface and the side surface of the conductive layer 203. The insulating layer 110a is provided to cover part of the opening 148. The insulating layer 110a is in contact with the insulating layer 107 through the opening 148. The insulating layer 110a is provided to cover part of the opening 248. The insulating layer 110a is in contact with the insulating layer 107 through the opening 248.

There is no particular limitation on the top-view shape of each of the opening 148 and the opening 248. As the top-view shape of the opening 148, the shapes that can be used for the opening 141 and the opening 143 can be employed. The top-view shapes of the opening 141, the opening 143, and the opening 148 are each preferably circular as illustrated in FIG. 4A. When the top-view shapes of the openings are circular, the top-view shape of the opening 248 can be a shape that can be used for each of the opening 241 and the opening 243. The top-view shapes of the opening 241, the opening 243, and the opening 248 are each preferably circular as illustrated in FIG. 4A. When the top-view shapes of the openings are circular, processing accuracy at the time of formation of the openings can be high, whereby the openings can be formed to have minute sizes.

In this specification and the like, the top-view shape of the opening 148 refers to the shape of an end portion of the top surface or the shape of an end portion of the bottom surface of the conductive layer 103 on the opening 148 side. FIG. 4A illustrates a shape 148t of the end portion of the top surface of the conductive layer 103 on the opening 148 side. In this specification and the like, the top-view shape of the opening 248 refers to the shape of an end portion of the top surface or the shape of an end portion of the bottom surface of the conductive layer 103 on the opening 248 side. FIG. 4A illustrates a shape 248t of the end portion of the top surface of the conductive layer 203 on the opening 248 side.

When the top-view shape of each of the opening 141 and the opening 148 is circular, the opening 141 and the opening 148 are preferably concentrically arranged. In that case, the shortest distances between the semiconductor layer 108 and the conductive layer 103 on the left and right sides of the opening 141 can be the same in the cross-sectional view. The opening 141 and the opening 148 are not concentrically arranged in some cases. When the top-view shape of each of the opening 241 and the opening 248 is circular, the opening 241 and the opening 248 are preferably concentrically arranged. In that case, the shortest distances between the semiconductor layer 208 and the conductive layer 203 on the left and right sides of the opening 241 can be the same in the cross-sectional view. The opening 241 and the opening 248 are not concentrically arranged in some cases.

In the semiconductor layer 108 of the transistor 100, a region overlapping with the conductive layer 104 with the insulating layer 106 therebetween and overlapping with the conductive layer 103 with part (specifically, the insulating layer 110a and the insulating layer 110b) of the insulating layer 110 therebetween. In other words, in the semiconductor layer 108, a region sandwiched between the conductive layer 104 and the conductive layer 103 is included, the insulating layer 106 is sandwiched between the region and the conductive layer 104, and part (specifically, the insulating layer 110a and the insulating layer 110b) of the insulating layer 110 is sandwiched between the region and the conductive layer 103.

The conductive layer 103 functions as a back gate electrode of the transistor 100. Part of the insulating layer 110 functions as a back gate insulating layer of the transistor 100.

In the semiconductor layer 208 of the transistor 200, a region overlapping with the conductive layer 204 with the insulating layer 106 therebetween and overlapping with the conductive layer 203 with part (specifically, the insulating layer 110a and the insulating layer 110b) of the insulating layer 110 therebetween. In other words, in the semiconductor layer 208, a region sandwiched between the conductive layer 204 and the conductive layer 203 is included, the insulating layer 106 is sandwiched between the region and the conductive layer 204, and part (specifically, the insulating layer 110a and the insulating layer 110b) of the insulating layer 110 is sandwiched between the region and the conductive layer 203.

The conductive layer 203 functions as a back gate electrode of the transistor 200. Part of the insulating layer 110 functions as a back gate insulating layer of the transistor 200.

For the conductive layer 103 and the conductive layer 203, any of the materials that can be used for the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, the conductive layer 212b, the conductive layer 104, and the conductive layer 204 can be used.

Since the back gate electrode is provided in the transistor 100, the potential of the semiconductor layer on the back channel side can be fixed, so that the saturation characteristics of the Id-Vd characteristics of the transistor 100 can be improved. The potential of the semiconductor layer 108 on the back channel side is fixed, whereby a shift in the threshold voltage can be inhibited. When the shift in the threshold voltage of the transistor 100 is inhibited, a transistor with a low cut-off current can be obtained.

In this specification and the like, the state where the change in current is small in the saturation region of the Id-Vd characteristics of a transistor is sometimes described using the expression “favorable saturation characteristics” or “having favorable saturation characteristics”, for example.

For the insulating layer 107, the material that can be used for the insulating layer 110 can be used. As the insulating layer 107, an insulating layer containing nitrogen is preferably used. For the insulating layer 107, a material that can be used for the insulating layer 110a and the insulating layer 110c can be suitably used. For example, silicon nitride can be suitably used for the insulating layer 107. Although the insulating layer 107 has a single-layer structure in this embodiment, one embodiment of the present invention is not limited thereto. The insulating layer 107 may have a stacked-layer structure of two or more layers.

In each of the transistor 100 and the transistor 200, the back gate electrode can be electrically connected to the source electrode or the drain electrode. The back gate electrode is electrically connected to the source electrode, whereby a shift in the threshold voltage of the transistor can be inhibited. The reliability of the transistors can be increased.

In each of the transistor 100 and the transistor 200, the back gate electrode can be electrically connected to the gate electrode. Electrical connection between the back gate electrode and the gate electrode can increase the on-state current of each of the transistors.

When an opening is provided in a region of the insulating layer 107 that overlaps with the conductive layer 112a and the conductive layer 103 is provided to cover the opening, the conductive layer 103 and the conductive layer 112a can be in contact with each other.

When an opening is provided in a region of the insulating layer 110 that overlaps with the conductive layer 103 and the conductive layer 112b is provided to cover the opening, the conductive layer 103 and the conductive layer 112b can be in contact with each other.

When an opening is provided in a region of the insulating layer 106 and the insulating layer 110 that overlaps with the conductive layer 103 and the conductive layer 104 is provided to cover the opening, the conductive layer 103 and the conductive layer 104 can be in contact with each other.

When an opening is provided in a region of the insulating layer 107 that overlaps with the conductive layer 212a and the conductive layer 203 is provided to cover the opening, the conductive layer 203 and the conductive layer 212a can be in contact with each other.

When an opening is provided in a region of the insulating layer 110 that overlaps with the conductive layer 203 and the conductive layer 212b is provided to cover the opening, the conductive layer 203 and the conductive layer 212b can be in contact with each other.

When an opening is provided in a region of the insulating layer 106 and the insulating layer 110 that overlaps with the conductive layer 203 and the conductive layer 204 is provided to cover the opening, the conductive layer 203 and the conductive layer 204 can be in contact with each other.

The thickness of the conductive layer 103 is preferably greater than or equal to 0.5 times, further preferably greater than or equal to 1.0 times, still further preferably greater than 1.0 times the channel length L1, and preferably less than or equal to 2.0 times, further preferably less than or equal to 1.5 times, still further preferably less than or equal to 1.2 times the channel length L1. In that case, a region of the semiconductor layer 108 that overlaps with the conductive layer 104 with the insulating layer 106 therebetween and overlaps with the conductive layer 103 with the insulating layer 110 therebetween can be sufficiently widely. As a result, the potential of the semiconductor layer 108 on the back channel side can be more surely controlled.

The thickness of the conductive layer 103 may be larger than that of the insulating layer 110. Accordingly, the potential of the semiconductor layer 108 on the back channel side can be fixed in a wide range between the source region and the drain region of the semiconductor layer 108.

The transistor 100 illustrated in FIG. 4A and FIG. 4B includes a region where the conductive layer 103, the insulating layer 110, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are stacked in this order in one direction with no any other layer included between these layers. The one direction can be perpendicular to the channel length L1 direction. When the above region is wide, the potential of the semiconductor layer 108 on the back channel side can be more surely controlled.

The thickness of the conductive layer 103 can be larger than the sum of the thickness of a portion of the semiconductor layer 108 in contact with the conductive layer 112a inside the opening 141 and the thickness of the insulating layer 106 in contact with the portion.

The thickness of the conductive layer 203 is preferably greater than or equal to 0.5 times, further preferably greater than or equal to 1.0 times, still further preferably greater than 1.0 times the channel length L2, and preferably less than or equal to 2.0 times, further preferably less than or equal to 1.5 times, still further preferably less than or equal to 1.2 times the channel length L2. In that case, a region of the semiconductor layer 208 that overlaps with the conductive layer 204 with the insulating layer 106 therebetween and overlaps with the conductive layer 203 with the insulating layer 110 therebetween can be sufficiently widely. As a result, the potential of the semiconductor layer 208 on the back channel side can be more surely controlled.

The thickness of the conductive layer 203 may be larger than that of the insulating layer 110. Accordingly, the potential of the semiconductor layer 208 on the back channel side can be fixed in a wide range between the source region and the drain region of the semiconductor layer 208.

The transistor 200 illustrated in FIG. 4A and FIG. 4B includes a region where the conductive layer 203, the insulating layer 110, the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 are stacked in this order in one direction with no any other layer included between these layers. The one direction can be perpendicular to the channel length L2 direction. When the above region is wide, the potential of the semiconductor layer 208 on the back channel side can be more surely controlled.

The thickness of the conductive layer 203 can be larger than the sum of the thickness of a portion of the semiconductor layer 208 in contact with the conductive layer 212a inside the opening 241 and the thickness of the insulating layer 106 in contact with the portion.

Here, the conductive layer 103 is oxidized by oxygen contained in the insulating layer 110b and has high resistance in some cases. Providing the insulating layer 110a between the insulating layer 110b and the conductive layer 103 can inhibit the conductive layer 103 from being oxidized and having high resistance. In addition, providing the insulating layer 110c between the insulating layer 110b and the conductive layer 112b can inhibit the conductive layer 112b from being oxidized and having high resistance. Accordingly, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 is increased, whereby the amount of oxygen vacancy in the semiconductor layer 108 can be reduced.

Structure Example 3

FIG. 14A is a cross-sectional view of a structure including a transistor 200(1) and a transistor 200(2).

The above-described transistor 200 can be referred to for each of the transistor 200(1) and the transistor 200(2); the transistor 200(1) and the transistor 200(2) are different from the transistor 200 in that a conductive layer 212b_A shared by the two transistors is provided instead of the conductive layer 212b in each transistor and a conductive layer 204_A shared by the two transistors is provided instead of the conductive layer 204 in each transistor.

In FIG. 14A, part of the conductive layer 212b_A functions as one of a source electrode and a drain electrode of the transistor 200(1), and another part of the conductive layer 212b_A functions as one of a source electrode and a drain electrode of the transistor 200(2).

In FIG. 14A, part of the conductive layer 204_A functions as a gate electrode of the transistor 200(1), and another part of the conductive layer 204_A functions as a gate electrode of the transistor 200(2).

It can be said that the transistor 200(1) and the transistor 200(2) are connected in series because they share the gate electrode and the one of the source electrode and the drain electrode of the transistor 200(1) is electrically connected to the one of the source electrode and the drain electrode of the transistor 200(2). FIG. 14C illustrates an example of a circuit diagram corresponding to the transistor 200(1) and the transistor 200(2) connected in series. P is a wiring corresponding to the conductive layer 212a included in the transistor 200(1), Q is a wiring corresponding to the conductive layer 212a included in the transistor 200(2), and G is a wiring corresponding to the conductive layer 204_A.

The two transistors connected in series as illustrated in FIG. 14C can be regarded as one transistor 200A as illustrated in FIG. 14D. In the case where the channel length and the channel width of each of the two transistors are respectively represented by L and W, the transistor 200A can be regarded to have a channel length of 2×L and a channel width of W.

FIG. 14B illustrates a structure where the transistor 200(1) and the transistor 200(2) are included. The above-described transistor 200 can be referred to for each of the transistor 200(1) and the transistor 200(2); the transistor 200(1) and the transistor 200(2) are different from the transistor 200 in that a conductive layer 212a_A shared by the two transistors is provided instead of the conductive layer 212a in each transistor and the conductive layer 204_A shared by the two transistors is provided instead of the conductive layer 204 in each transistor.

In FIG. 14C, when P is a wiring corresponding to the conductive layer 212b included in the transistor 200(1), Q is a wiring corresponding to the conductive layer 212b included in the transistor 200(2), and G is a wiring corresponding to the conductive layer 204_A, the structure illustrated in FIG. 14C can also be employed for the structure illustrated in FIG. 14B.

This embodiment can be combined with the other embodiments as appropriate. In this specification, in the case where a plurality of structure examples are shown in one embodiment, the structure examples can be combined as appropriate.

In this embodiment, a method for manufacturing the semiconductor device of one embodiment of the present invention will be described with reference to FIG. 15 to FIG. 17. Note that as for a material and a formation method of each component, portions similar to those described in Embodiment 1 are not described in some cases.

Thin films included in the semiconductor device (e.g., insulating films, semiconductor films, and conductive films) can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, or the like. Examples of a CVD method include a PECVD method and a thermal CVD method. An example of a thermal CVD method is a metal organic chemical vapor deposition (MOCVD: Metal Organic CVD) method.

Thin films included in the semiconductor device (e.g., insulating films, semiconductor films, and conductive films) can be formed by a wet film formation method such as spin coating, dipping, spray coating, ink-jetting, dispensing, screen printing, offset printing, a doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

In processing thin films included in the semiconductor device, a photolithography method or the like can be employed. Alternatively, the thin films may be processed by a nanoimprinting method, a sandblasting method, a lift-off method, or the like. Alternatively, island-shaped thin films may be directly formed by a film formation method using a shielding mask such as a metal mask.

There are the following two typical examples of a photolithography method. In one of the methods, a resist mask is formed over a thin film to be processed, the thin film is processed by etching or the like, and then the resist mask is removed. In the other method, a photosensitive thin film is formed and then the thin film is processed into a desired shape by light exposure and development.

As the light used for light exposure in the photolithography method, it is possible to use light with the i-line (wavelength: 365 nm), light with the g-line (wavelength: 436 nm), light with the h-line (wavelength: 405 nm), or light in which the i-line, the g-line, and the h-line are mixed. Alternatively, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. In addition, light exposure may be performed by liquid immersion exposure technique. As the light used for light exposure, extreme ultraviolet (EUV) light or X-rays may also be used. Furthermore, instead of the light used for the exposure, an electron beam can also be used. EUV light, X-rays, or an electron beam is preferably used to enable extremely minute processing. Note that a photomask is not needed when light exposure is performed by scanning with a beam such as an electron beam.

For etching of thin films, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

Manufacturing Method Example 1

The manufacturing method is described below taking the semiconductor device 10 illustrated in FIG. 1B or the like as an example.

Each of FIG. 15A to FIG. 17C is a diagram illustrating the method for manufacturing the semiconductor device 10. Each diagram is a cross-sectional view taken along the dashed-dotted line A1-A2.

First, the conductive layer 112a and the conductive layer 212a are formed over the substrate 102, and an insulating film 110af to be the insulating layer 110a and an insulating film 110bf to be the insulating layer 110b are formed over the conductive layer 112a and the conductive layer 212a.

For the formation of a conductive film to be the conductive layer 112a and the conductive layer 212a, a sputtering method can be suitably used, for example. The conductive layer 112a and the conductive layer 212a can be formed in the following manner: a resist mask is formed over the conductive film by a photolithography process and then, the conductive film is processed.

For the formation of the insulating film 110af and the insulating film 110bf, a sputtering method or a PECVD method can be suitably used, for example. It is preferable that the insulating film 110bf be formed in a vacuum successively after the formation of the insulating film 110af, without exposure of a surface of the insulating film 110af to the air. By forming the insulating film 110af and the insulating film 110bf successively, attachment of impurities derived from the air to the surface of the insulating film 110af can be inhibited. Examples of the impurities include water and organic substances.

The substrate temperature at the time of forming the insulating film 110af and the insulating film 110bf is preferably higher than or equal to 180° C. and lower than or equal to 450° C., further preferably higher than or equal to 200° C. and lower than or equal to 450° C., still further preferably higher than or equal to 250° C. and lower than or equal to 450° C., yet still further preferably higher than or equal to 300° C. and lower than or equal to 450° C., yet still further preferably higher than or equal to 300° C. and lower than or equal to 400° C., yet still further preferably higher than or equal to 350° C. and lower than or equal to 400° C. When the substrate temperature at the time of forming the insulating film 110af and the insulating film 110bf is in the above range, the amount of impurities (e.g., water and hydrogen) released from the insulating films themselves can be reduced, which inhibits the diffusion of the impurities to the semiconductor layer 108. Consequently, a transistor with favorable electrical characteristics and high reliability can be obtained.

After the insulating film 110bf is formed, oxygen may be supplied to the insulating film 110bf. As a method for supplying oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or plasma treatment can be used, for example. For the plasma treatment, an apparatus in which an oxygen gas is made to be plasma by high-frequency power can be suitably used. Examples of the apparatus in which a gas is made to be plasma by high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, dinitrogen monoxide (N2O), nitrogen dioxide (NO2), carbon monoxide, and carbon dioxide.

Note that the plasma treatment may be successively performed in a vacuum without exposure of a surface of the insulating film 110bf to the air. For example, in the case where a PECVD apparatus is used to form the insulating film 110bf, the plasma treatment is preferably performed with the PECVD apparatus. Accordingly, the productivity can be increased.

A metal oxide layer may be formed after the formation of the insulating film 110bf. The formation of the metal oxide layer enables oxygen supply to the insulating film 110bf.

There is no limitation on the conductivity of the metal oxide layer. As the metal oxide layer, at least one type of an insulating film, a semiconductor film, and a conductive film can be used. For the metal oxide layer, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can be used, for example.

For the metal oxide layer, an oxide material containing one or more elements that are the same as those of the semiconductor layer 108 and the semiconductor layer 208 is preferably used. It is particularly preferable to use an oxide semiconductor material that can be used for each of the semiconductor layer 108 and the semiconductor layer 208.

At the time of forming the metal oxide layer, a larger amount of oxygen can be supplied into the insulating film 110af with a higher proportion of the oxygen flow rate to the total flow rate of the film formation gas introduced into a treatment chamber of a film formation apparatus (i.e., with a higher oxygen flow rate ratio), or with a higher oxygen partial pressure in the treatment chamber. The oxygen flow rate ratio or the oxygen partial pressure is, for example, higher than or equal to 50% and lower than or equal to 100%, preferably higher than or equal to 65% and lower than or equal to 100%, further preferably higher than or equal to 80% and lower than or equal to 100%, still further preferably higher than or equal to 90% and lower than or equal to 100%. It is particularly preferred that the oxygen flow rate ratio be 100% and the oxygen partial pressure be as close to 100% as possible.

When the metal oxide layer is formed by a sputtering method in an oxygen-containing atmosphere in the above manner, oxygen can be supplied to the insulating film 110bf and release of oxygen from the insulating film 110bf can be prevented during the formation of the metal oxide layer. As a result, a large amount of oxygen can be enclosed in the insulating film 110bf. Moreover, a large amount of oxygen can be supplied to the semiconductor layer 108 by heat treatment performed later. Consequently, the amounts of oxygen vacancies and VOH in the semiconductor layer 108 can be reduced, whereby a transistor with favorable electrical characteristics and high reliability can be obtained.

After the metal oxide layer is formed, heat treatment may be performed. By the heat treatment performed after the formation of the metal oxide layer, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110bf.

The heat treatment temperature is preferably higher than or equal to 150° C. and lower than the strain point of the substrate, further preferably higher than or equal to 200° C. and lower than or equal to 450° C., still further preferably higher than or equal to 250° C. and lower than or equal to 450° C., yet still further preferably higher than or equal to 300° C. and lower than or equal to 450° C., yet still further preferably higher than or equal to 300° C. and lower than or equal to 400° C., yet still further preferably higher than or equal to 350° C. and lower than or equal to 400° C. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, and oxygen. As a nitrogen-containing atmosphere or an oxygen-containing atmosphere, clean dry air (CDA) may be used. Note that the content of hydrogen, water, or the like in the atmosphere is preferably as low as possible. As the atmosphere, a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower is preferably used. With the use of an atmosphere where the content of hydrogen, water, or the like is as low as possible, entry of hydrogen, water, or the like into the insulating film 110bf can be prevented as much as possible. An oven, a rapid thermal annealing (RTA) apparatus, or the like can be used for the heat treatment. With the RTA apparatus, the heat treatment time can be shortened.

After the formation of the metal oxide layer or after the above-described heat treatment, oxygen may be further supplied to the insulating film 110bf through the metal oxide layer. As a method for supplying oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or plasma treatment can be used, for example. The above description can be referred to for the plasma treatment; thus, the detailed description thereof is omitted.

The metal oxide layer is removed after the formation, after the heat treatment, or after the supply of oxygen. There is no particular limitation on a method for removing the metal oxide layer, and a wet etching method can be suitably used. With use of a wet etching method, the insulating film 110bf can be inhibited from being etched during the removal of the metal oxide layer. This can inhibit a reduction in the thickness of the insulating film 110bf and the thickness of the insulating layer 110b can be uniform.

The treatment for supplying oxygen to the insulating film 110bf is not necessarily performed in the above-described manner. An oxygen radical, an oxygen atom, an oxygen atomic ion, an oxygen molecular ion, or the like is supplied to the insulating film 110bf by an ion doping method, an ion implantation method, plasma treatment, or the like. Alternatively, a film that inhibits oxygen release may be formed over the insulating film 110bf, and then oxygen may be supplied to the insulating film 110bf through the film. It is preferable to remove the film after supply of oxygen. As the above film that inhibits oxygen release, a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

Next, an insulating film 110cf to be the insulating layer 110c is formed over the insulating film 110bf.

For the formation of the insulating film 110cf, a sputtering method or a PECVD method can be suitably used, for example.

Then, a conductive film to be the conductive layer 112b and the conductive layer 212b is formed over the insulating film 110cf. A sputtering method can be suitably used for forming the conductive film, for example.

Next, the conductive film is processed to form a conductive layer 112b_e and a conductive layer 212b_e (FIG. 15A). The conductive layer 112b_e is to be the conductive layer 112b later, and the conductive layer 212b_e is to be the conductive layer 212b later. For example, a wet etching method can be suitably used for formation of the conductive layer 112b_e and the conductive layer 212b_e. A dry etching method may also be used.

Subsequently, a resist mask 190A is formed over the conductive layer 112b_e, the conductive layer 212b_e, and the insulating film 110cf (FIG. 15A).

Then, part of the conductive layer 112b_e is removed using the resist mask 190A, so that the conductive layer 112b including the opening 143 is formed. A wet etching method can be suitably used to form the conductive layer 112b. A dry etching method may also be used.

Next, part of the insulating film 110cf, part of the insulating film 110bf, and part of the insulating film 110af are removed to form the opening 141 (FIG. 15B). The insulating film 110cf, the insulating film 110bf, and the insulating film 110af after the formation of the opening 141 are referred to as an insulating layer 110cg, an insulating layer 110bg, and an insulating layer 110ag, respectively. The opening 141 is provided in a region overlapping with the opening 143. The conductive layer 112a is exposed by the formation of the opening 141. For the formation of the insulating layer 110cg, the insulating layer 110bg, and the insulating layer 110ag, a dry etching method can be suitably used.

The opening 141 can be formed using the resist mask 190A, for example. The opening 141 may be formed using a resist mask that is different from the resist mask 190A.

The resist mask 190A can be removed after formation of the opening 141, for example. Alternatively, the resist mask 190A may be removed after the opening 143 is provided and before formation of the insulating layer 110cg, before formation of the insulating layer 110bg, or before formation of the insulating layer 110ag.

Note that in the formation of the opening 141 or after the formation of the opening 141, part of the conductive layer 112a in a region overlapping with the opening 141 may be removed. When the thickness of the region of the conductive layer 112a that is in contact with the bottom surface of the semiconductor layer 108 is smaller than the thickness of the region of the conductive layer 112a that is not in contact with the semiconductor layer 108, the electric field of the gate electrode applied to the channel formation region in the vicinity of the conductive layer 112a can be increased and the on-state current of the transistor can be increased.

Next, a resist mask 190B is formed over the conductive layer 112b, the conductive layer 212b_e, and the insulating layer 110cg (FIG. 15C).

Then, part of the conductive layer 212b_e is removed using the resist mask 190B, and an opening is provided in the conductive layer 212b_e. For the formation of the opening, a wet etching method can be suitably used. Alternatively, a dry etching method may be used for the formation of the opening. Here, the opening provided in the conductive layer 212b_e can be an opening smaller than the opening 243, for example, and the end portion of the opening can be made to recede to be the opening 243 in a later-described formation process of the insulating layer 110.

Next, part of the insulating layer 110cg, part of the insulating layer 110bg, and part of the insulating layer 110ag are removed to form the insulating layer 110 including the opening 241 (FIG. 15D). The opening 241 is provided in a region overlapping with the opening provided in the conductive layer 212b_e. The conductive layer 212a is exposed by the formation of the opening 241. A dry etching method can be suitably used for the formation of the insulating layer 110.

The opening 241 can be formed using the resist mask 190B, for example. The opening 241 may be formed using a resist mask different from the resist mask 190B.

The resist mask 190B can be removed after the formation of the opening 241, for example. Alternatively, the resist mask 190B may be removed after the opening 243 is provided and before the formation of the insulating layer 110c, before the formation of the insulating layer 110b, or before the formation of the insulating layer 110a.

At the time of forming the insulating layer 110, processing is preferably performed such that the side surface of the insulating layer 110 in the opening 241 has a tapered shape. Processing is preferably performed such that an angle formed by the side surface of the insulating layer 110 in the opening 241 and the formation surface is small. In the case where a resist mask is used to form the opening 241, the insulating layer 110 is processed under the conditions where the resist mask is easily recessed (reduced in size), whereby an angle formed by the side surface of the insulating layer 110 and the formation surface can be small.

In the formation of the insulating layer 110, when the resist mask is recessed, the opening provided in the conductive layer 212b_e can also be etched to be recessed. Here, in the case where the conductive layer 212b_e does not recede or has a small recession amount, for example, the end portion of the conductive layer 212b in the opening 243 is positioned outward from the end portion of the insulating layer 110 in the opening 241 in some cases as illustrated in FIG. 8B. Meanwhile, in the case where the recession amount of the conductive layer 212b_e is large, for example, the end portion of the conductive layer 212b in the opening 243 is positioned inward from the end portion of the insulating layer 110 in the opening 241 in some cases as illustrated in FIG. 8A.

Note that the method for manufacturing the conductive layer 212b is not limited to the method for making an end portion of the opening provided in the conductive layer 212b_e recede at the time of forming the insulating layer 110. For example, the conductive layer 212b including the opening 243 may be provided in advance before the formation of the insulating layer 110. Alternatively, the opening provided in the conductive layer 212b_e may be recessed after the formation of the insulating layer 110.

For example, instead of the steps in FIG. 15C to FIG. 15D, the conductive layer 212b and the insulating layer 110 may be formed using the steps in FIG. 16A to FIG. 16D shown below. The steps in FIG. 15C to FIG. 15D illustrate an example in which the opening of the conductive layer 212b is formed in accordance with the recession of the resist mask 190B at the time of forming the insulating layer 110; however, the steps in FIG. 16A to FIG. 16D illustrate an example in which the insulating layer 110 is formed after an opening with a desired size is provided in advance in the conductive layer 212b.

First, a resist mask 190C is formed over the conductive layer 112b, the conductive layer 212b_e, and the insulating layer 110cg (FIG. 16A).

Next, part of the conductive layer 212b_e is removed using the resist mask 190C, so that the conductive layer 212b including the opening 243 is formed (FIG. 16B).

Then, a resist mask 190D is formed over the conductive layer 112b, the conductive layer 212b, and the insulating layer 110cg (FIG. 16C). Here, an end portion of the opening in the resist mask 190D is provided inward from an end portion of the opening 243 in the conductive layer 212b.

Subsequently, part of the insulating layer 110cg, part of the insulating layer 110bg, and part of the insulating layer 110ag are removed using the resist mask 190D, so that the insulating layer 110 including the opening 241 is formed (FIG. 16D). In the formation of the insulating layer 110, processing is preferably performed to make the resist mask 190D recede. Note that the end portion of the opening in the resist mask 190D is provided inward from the end portion of the opening 243 in the conductive layer 212b; thus, when the recession amount of the resist mask 190D is small enough not to expose the top surface and the side surface of the conductive layer 212b, the top surface and the side surface of the conductive layer 212b can be kept covered with the resist mask 190D.

Note that the side surface of the conductive layer 212b or the like is sometimes exposed in the middle of a step of making the resist mask 190D recede at the time of forming the insulating layer 110. In such a case, the end portion of the opening 243 in the conductive layer 212b recedes, so that the opening is increased in some cases. That is, the size of the opening in the conductive layer 212b in FIG. 16D is larger than the size of the opening in the conductive layer 212b in FIG. 16B in some cases.

In the case where the etching condition at the time of forming the insulating layer 110 is a condition where the conductive layer 212b is unlikely to recede, a display device of one embodiment of the present invention can be suitably manufactured with the use of the manufacturing method illustrated in FIG. 16A to FIG. 16D.

Note that FIG. 16D illustrates, as an example, a structure in which the end portion of the bottom surface of the conductive layer 212b in the opening 243 is positioned inward from the end portion of the top surface of the insulating layer 110 in the opening 241; however, by adjusting the pattern of the resist mask 190C, the pattern of the resist mask 190D, the etching condition of the conductive layer 212b_e, and the etching conditions of the insulating layer 110cg, the insulating layer 110bg, and the insulating layer 110ag, a structure in which the end portion of the bottom surface of the conductive layer 212b in the opening 243 is positioned outward from the end portion of the top surface of the insulating layer 110 in the opening 241, a structure in which the end portion of the bottom surface of the conductive layer 212b in the opening 243 and the end portion of the top surface of the insulating layer 110 in the opening 241 are substantially aligned with each other, or the like can be suitably manufactured.

As described above, the conductive layer 212b including the opening 243 and the insulating layer 110 including the opening 241 can be formed by the method illustrated in FIG. 15C to FIG. 15D or FIG. 16A to FIG. 16D.

Next, a metal oxide film 108f to be the semiconductor layer 108 and the semiconductor layer 208 is formed to cover the opening 141, the opening 143, the opening 241, and the opening 243 (FIG. 17A). The metal oxide film 108f is provided in contact with the top surface and the side surface of the conductive layer 112b, the top surface and the side surface of the conductive layer 212b, the top surface and the side surface of the insulating layer 110, the top surface of the conductive layer 112a, and the top surface of the conductive layer 212a.

Subsequently, part of the metal oxide film 108f is removed using a resist mask or the like, so that the semiconductor layer 108 and the semiconductor layer 208 are formed. For the formation of each of the semiconductor layer 108 and the semiconductor layer 208, a wet etching method can be suitably used.

The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. The metal oxide film 108f is preferably formed by an ALD method.

The metal oxide film 108f is preferably a dense film with as few defects as possible. The metal oxide film 108f is preferably a highly purified film in which impurities containing hydrogen elements are reduced as much as possible. It is particularly preferable to use a metal oxide film having crystallinity as the metal oxide film 108f.

In forming the metal oxide film 108f, an oxygen gas is preferably used. In the case of using an oxygen gas at the time of forming the metal oxide film 108f, oxygen can be suitably supplied into the insulating layer 110. For example, in the case where an oxide is used for the insulating layer 110b, oxygen can be suitably supplied into the insulating layer 110b.

By the supply of oxygen to the insulating layer 110b, oxygen is supplied to the semiconductor layer 108 and the semiconductor layer 208 in a later step, so that the amounts of oxygen vacancy and VOH in the semiconductor layer 108 and the semiconductor layer 208 can be reduced.

In forming the metal oxide film 108f, an oxygen gas and an inert gas (e.g., a helium gas, an argon gas, or a xenon gas) may be mixed. Note that when the proportion of an oxygen gas in the whole deposition gas (an oxygen flow rate ratio) at the time of forming the metal oxide film is higher, the crystallinity of the metal oxide film can be higher and a transistor with higher reliability can be obtained. By contrast, when the oxygen flow rate ratio is lower, the crystallinity of the metal oxide film is lower and a transistor with a higher on-state current can be obtained. For example, with use of different oxygen flow rate ratios, a stacked-layer structure of two or more metal oxide layers having different crystallinities can be formed.

In forming the metal oxide film, as the substrate temperature is higher, a denser metal oxide film having higher crystallinity can be formed. On the other hand, as the substrate temperature is lower, the metal oxide film having lower crystallinity and higher electric conductivity can be formed.

The substrate temperature during the formation of the metal oxide film 108f is preferably higher than or equal to room temperature and lower than or equal to 250° C., further preferably higher than or equal to room temperature and lower than or equal to 200° C., still further preferably higher than or equal to room temperature and lower than or equal to 140° C. For example, the substrate temperature is preferably higher than or equal to room temperature and lower than or equal to 140° C., in which case productivity is increased. Furthermore, when the metal oxide film is formed with the substrate temperature set at room temperature or without heating the substrate, the crystallinity can be made low.

In the case of employing an ALD method for forming the metal oxide film 108f, a film formation method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method is preferably employed. The thermal ALD method is preferable because of its capability of forming a film with extremely high step coverage. The PEALD method is preferable because of its capability of forming a film at low temperatures, in addition to its capability of forming a film with high step coverage.

The metal oxide film can be formed by an ALD method using an oxidizing agent and a precursor containing a constituent metal element, for example.

For example, in the case where In—Ga—Zn oxide is formed, three precursors of a precursor containing indium, a precursor containing gallium, and a precursor containing zinc can be used. Alternatively, two precursors of a precursor containing indium and a precursor containing gallium and zinc may be used.

As examples of the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionato)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium can be given.

As examples of the precursor containing zinc, dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionato) zinc, and zinc chloride can be given.

As examples of the oxidizing agent, ozone, oxygen, and water can be given.

As an example of a method for controlling the composition of a film to be formed, adjusting one or more of the kinds of source gases, the flow rate ratio of source gases, flowing time of source gases, and flowing order of source gases is given. By adjusting such conditions, a film whose composition is continuously changed can be formed. Furthermore, films having different compositions can be formed successively.

In the case where the metal oxide film 108f has a stacked-layer structure, an upper metal oxide film is preferably formed successively after the formation of a lower metal oxide film without exposure of a surface of the lower metal oxide film to the air.

Before the formation of the metal oxide film 108f, at least one of treatment for desorbing water, hydrogen, an organic substance, and the like adsorbed on a surface of the insulating layer 110, and treatment for supplying oxygen into the insulating layer 110 is preferably performed. For example, heat treatment can be performed at a temperature higher than or equal to 70° C. and lower than or equal to 200° C. in a reduced-pressure atmosphere. Alternatively, plasma treatment in an oxygen-containing atmosphere may be performed. Alternatively, oxygen may be supplied to the insulating layer 110 by performing plasma treatment in an atmosphere containing an oxidizing gas such as dinitrogen monoxide (N2O). When plasma treatment is performed using a dinitrogen monoxide gas, an organic substance on the surface of the insulating layer 110 can be suitably removed and oxygen can be supplied to the insulating layer 110. The metal oxide film 108f is preferably formed successively after such treatment without exposure of the surface of the insulating layer 110 to the air.

It is preferable that heat treatment be performed after the metal oxide film 108f is formed or the metal oxide film 108f is processed into the semiconductor layer 108 and the semiconductor layer 208. By the heat treatment, hydrogen or water contained in the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 or adsorbed on a surface of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 can be removed. Furthermore, the film quality of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 is improved (e.g., the number of defects is reduced or the crystallinity is increased) by the heat treatment in some cases.

Oxygen can be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 by heat treatment. In this case, it is further preferable that the heat treatment be performed after forming the metal oxide film 108f and before processing into the semiconductor layer 108 and the semiconductor layer 208. For the heat treatment, the above description can be referred to.

Note that the heat treatment is not necessarily performed. The heat treatment is not necessarily performed in this step, and heat treatment performed in a later step may also serve as the heat treatment in this step. In some cases, treatment at a high temperature (e.g., film formation step) in a later step can serve as the heat treatment in this step.

Then, the insulating layer 106 is formed to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112b, the conductive layer 212b, and the insulating layer 110 (FIG. 17B). For the formation of the insulating layer 106, for example, a PECVD method or an ALD method can be suitably used.

In the case where the semiconductor layer 108 and the semiconductor layer 208 are formed using an oxide semiconductor, the insulating layer 106 preferably functions as a barrier film that inhibits diffusion of oxygen. The insulating layer 106 having a function of inhibiting diffusion of oxygen inhibits diffusion of oxygen to the conductive layer 104 and the conductive layer 204 from above the insulating layer 106 and thus can inhibit oxidation of the conductive layer 104 and the conductive layer 204. Consequently, a transistor with favorable electrical characteristics and high reliability can be obtained.

Note that in this specification and the like, a barrier film refers to a film having a barrier property. For example, an insulating layer having a barrier property can be referred to as a barrier insulating layer. In this specification and the like, a barrier property means one or both of a function of inhibiting diffusion of a particular substance (or low permeability) and a function of capturing or fixing (also referred to as gettering) a particular substance.

When the temperature at the time of forming the insulating layer 106 to be the insulating layer 106 functioning as a gate insulating layer is increased, an insulating layer with few defects can be obtained. However, the high temperature at the time of forming the insulating layer 106 sometimes allows release of oxygen from the semiconductor layer 108 and the semiconductor layer 208, which increases the amounts of oxygen vacancies and VOH in the semiconductor layer 108 and the semiconductor layer 208. The substrate temperature at the time of forming the insulating layer 106 is preferably higher than or equal to 180° C. and lower than or equal to 450° C., further preferably higher than or equal to 200° C. and lower than or equal to 450° C., still further preferably higher than or equal to 250° C. and lower than or equal to 450° C., yet still further preferably higher than or equal to 300° C. and lower than or equal to 450° C., yet still further preferably higher than or equal to 300° C. and lower than or equal to 400° C. When the substrate temperature at the time of forming the insulating layer 106 is in the above range, release of oxygen from the semiconductor layer 108 and the semiconductor layer 208 can be inhibited while the defects in the insulating layer 106 can be reduced. Consequently, a transistor with favorable electrical characteristics and high reliability can be obtained.

Before the formation of the insulating layer 106, a surface and a side surface of each of the semiconductor layer 108 and the semiconductor layer 208 may be subjected to plasma treatment. By the plasma treatment, impurities such as water adsorbed on the surface and the side surface of each of the semiconductor layer 108 and the semiconductor layer 208 can be reduced. Accordingly, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 and the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, enabling formation of a highly reliable transistor. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, dinitrogen monoxide, argon, or the like. The plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

Next, a conductive film to be the conductive layer 104 and the conductive layer 204 is formed over the insulating layer 106, and the conductive film is processed to form the conductive layer 104 and the conductive layer 204.

Subsequently, the insulating layer 195 is formed to cover the conductive layer 104, the conductive layer 204, and the insulating layer 106 (FIG. 17C). For the formation of the insulating layer 195, a PECVD method can be suitably used.

Through the above process, the semiconductor device 10 can be manufactured.

In this embodiment, display devices for which the semiconductor device of one embodiment of the present invention can be used will be described with reference to FIG. 18 to FIG. 28.

The display device in this embodiment can be a high-resolution display device or a large-sized display device. Accordingly, the display device in this embodiment can be used for display portions of electronic devices such as a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, and an audio reproducing device, in addition to display portions of electronic devices with a relatively large screen, such as a television device, a desktop or notebook personal computer, a monitor of a computer or the like, digital signage, and a large game machine such as a pachinko machine.

The display device in this embodiment can be a high-definition display device. Accordingly, the display device in this embodiment can be used for display portions of information terminals (wearable devices) such as watch-type and bracelet-type information terminals and display portions of wearable devices capable of being worn on a head, such as a VR device like a head-mounted display (HMD) and a glasses-type AR device.

The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device are a module in which a connector such as a flexible printed circuit board (hereinafter referred to as an FPC) or a TCP (Tape Carrier Package) is attached to the display device, a module in which the display device is mounted with an integrated circuit (IC) by a COG (Chip On Glass) method, a COF (Chip On Film) method, or the like.

FIG. 18A illustrates a perspective view of a display device 50A.

In the display device 50A, a substrate 152 and a substrate 151 are bonded to each other. In FIG. 18A, the substrate 152 is indicated by a dashed line.

The display device 50A includes a display portion 162, a connection portion 140, a peripheral circuit portion 164, a wiring 165, and the like. FIG. 18A illustrates an example where an FPC 172 is implemented onto the display device 50A.

The connection portion 140 is provided outside the display portion 162. The connection portion 140 can be provided along one or more sides of the display portion 162. The number of connection portions 140 may be one or more. FIG. 18A illustrates an example where the connection portion 140 is provided to surround the four sides of the display portion. In the connection portion 140, a common electrode of a display element is electrically connected to a conductive layer so that a potential can be supplied to the common electrode.

The peripheral circuit portion 164 includes a scan line driver circuit (also referred to as a gate driver), for example. The peripheral circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

The wiring 165 has a function of supplying a signal and power to the display portion 162 and the peripheral circuit portion 164. The signal and power are input to the wiring 165 from the outside through the FPC 172.

As illustrated in FIG. 19, an IC 173 may be mounted on the display device 50A in addition to the FPC 172.

In the structure illustrated in FIG. 19, a signal and power supplied to the display portion 162 and the peripheral circuit portion 164 are input to the wiring 165 through the IC 173. Thus, the structure illustrated in FIG. 18A and FIG. 18B can be regarded as a display module including the display device, the FPC, and the like.

FIG. 18A illustrates an example where the IC 173 is provided on the substrate 151 by a COG method, a COF method, or the like. An IC including one or both of a scan line driver circuit and a signal line driver circuit can be used as the IC 173, for example. The IC may be mounted on the FPC by a COF method or the like.

The semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 162 and the peripheral circuit portion 164 of the display device 50A, for example.

The display portion 162 of the display device 50A is a region where an image is to be displayed, and includes a plurality of pixels 210 that are periodically arranged. FIG. 18A illustrates an enlarged view of one of the pixels 210.

There is no particular limitation on the arrangement of the pixels in the display device of this embodiment, and any of a variety of methods can be employed. Examples of the arrangement of the pixels include stripe arrangement, S-stripe arrangement, matrix arrangement, delta arrangement, Bayer arrangement, and PenTile arrangement.

The pixel 210 illustrated in FIG. 18A includes a pixel 230R that emits red light, a pixel 230G that emits green light, and a pixel 230B that emits blue light. The pixel 230R, the pixel 230G, and the pixel 230B function as subpixels.

The pixel 230R, the pixel 230G, and the pixel 230B each include a display element and a circuit for controlling the driving of the display element.

Any of a variety of elements can be used as the display element, and a liquid crystal element or a light-emitting element can be used, for example. Alternatively, a MEMS (Micro Electro Mechanical Systems) shutter element, an optical interference type MEMS element, or a display element using a microcapsule method, an electrophoretic method, an electrowetting method, an Electronic Liquid Powder (registered trademark) method, or the like can be used. Alternatively, a QLED (Quantum-dot LED) employing a light source and color conversion technology using quantum dot materials may be used.

As examples of a display device that includes a liquid crystal element, a transmissive liquid crystal display device, a reflective liquid crystal display device, and a transflective liquid crystal display device can be given.

Examples of the light-emitting element include self-luminous light-emitting elements such as an LED (Light Emitting Diode), an OLED (Organic LED), and a semiconductor laser. Examples of the LED include a mini LED and a micro LED.

Examples of a light-emitting substance contained in the light-emitting element include a substance that emits fluorescent light (a fluorescent material), a substance that emits phosphorescent light (a phosphorescent material), a substance that exhibits thermally activated delayed fluorescence (a thermally activated delayed fluorescent (TADF) material), and an inorganic compound (e.g., a quantum dot material).

The emission color of the light-emitting element can be infrared, red, green, blue, cyan, magenta, yellow, or white, for example. When the light-emitting element has a microcavity structure, higher color purity can be achieved.

One of a pair of electrodes of the light-emitting element functions as an anode, and the other electrode functions as a cathode.

In this embodiment, the case where a light-emitting element is used as the display element is mainly described as an example.

Any of a variety of logic circuits can be used in the circuit included in the display device of one embodiment of the present invention. Examples of the logic circuit include a combination circuit such as an OR circuit, an AND circuit, a NAND circuit, and a NOR circuit; a sequential circuit such as a flip-flop circuit, a latch circuit, a counter circuit, a register circuit, and a shift register circuit; and a buffer circuit.

FIG. 18B is a block diagram illustrating the display device 50A. The display device 50A includes the display portion 162 and the peripheral circuit portion 164. The display portion 162 includes a plurality of pixels 230 arranged periodically (the pixel 230[1,1] to the pixel 230[m,n], where m and n are each independently an integer greater than or equal to 2). In FIG. 18B, the pixel 230 in the first row and the n-th column is denoted as the pixel 230[1,n], the pixel 230 in the m-th row and the first column is denoted as the pixel 230[m,1], and the pixel 230 in the m-th row and the n-th column is denoted as the pixel 230[m,n]. The peripheral circuit portion includes a first driver circuit portion 231 and a second driver circuit portion 232.

A circuit included in the first driver circuit portion 231 functions as, for example, a scan line driver circuit. A circuit included in the second driver circuit portion 232 functions as, for example, a signal line driver circuit. Some sort of circuit may be provided to face the first driver circuit portion 231 with the display portion 162 placed therebetween. Some sort of circuit may be provided to face the second driver circuit portion 232 with the display portion 162 placed therebetween.

Any of various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, and a demultiplexer circuit can be used for the peripheral circuit portion 164. In the peripheral circuit portion 164, a transistor, a capacitor, and the like can be used. The transistor of one embodiment of the present invention can be used in the peripheral circuit portion 164 and the pixel 230.

The scan line driver circuit includes at least a shift register, for example. The signal line driver circuit can be formed using a shift register, a digital-analog converter circuit, a latch circuit, and the like.

The display device 50A includes wirings 236 which are arranged substantially parallel to each other and whose potentials are controlled by the circuits included in the first driver circuit portion 231, and wirings 238 which are arranged substantially parallel to each other and whose potentials are controlled by the circuits included in the second driver circuit portion 232. FIG. 18B illustrates an example in which the wiring 236 and the wiring 238 are connected to the pixel 230. Note that the wiring 236 and the wiring 238 are examples, and the wirings connected to the pixel 230 are not limited to the wiring 236 and the wiring 238.

<Structure Example of Peripheral Driver Circuit>

A structure example of a circuit that can be used for a peripheral driver circuit is described below.

FIG. 20A is a circuit diagram illustrating a structure example of a latch circuit LAT. The latch circuit LAT illustrated in FIG. 20A includes a transistor Tr31, a transistor Tr33, a transistor Tr35, a transistor Tr36, a capacitor C31, and an inverter circuit INV. In FIG. 20A, a node that is electrically connected to one of a source and a drain of the transistor Tr33, a gate of the transistor Tr35, and one electrode of the capacitor C31 is referred to as a node N.

In the latch circuit LAT illustrated in FIG. 20A, when a high-potential signal is input to a terminal SMP, the transistor Tr33 is turned on. Thus, the potential of the node N becomes a potential corresponding to the potential of a terminal ROUT, and data corresponding to a signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. After data is written to the latch circuit LAT, the potential of the terminal SMP is set to a low potential, so that the transistor Tr33 is turned off. Thus, the potential of the node N is held and the data written to the latch circuit LAT is held. Specifically, when the potential of the node N is a low potential, data “O” is held in the latch circuit LAT and when the potential of the node N is a high potential, data “1” is held in the latch circuit LAT, for example.

A transistor with a low off-state current is preferably used as the transistor Tr33. An OS transistor can be suitably used as the transistor Tr33. Thus, the latch circuit LAT can hold data for a long period. Thus, the frequency of rewriting data in the latch circuit LAT can be lowered.

In this specification and the like, data that allows a signal input from a terminal SP2 to be output to a terminal LLIN is written to the latch circuit LAT, which is referred to simply as “writing data to the latch circuit LAT” in some cases. That is, for example, data “1” is written to the latch circuit LAT, which is referred to simply as “writing data to the latch circuit LAT” in some cases.

The semiconductor device of one embodiment of the present invention can be suitably used for the latch circuit LAT. For example, the transistor 100 or the transistor 200 illustrated in FIG. 1B or the like can be used as each of the transistor Tr31, the transistor Tr33, the transistor Tr35, and the transistor Tr36.

FIG. 20B illustrates a structure example of the inverter circuit INV. The inverter circuit INV includes a transistor Tr41, a transistor Tr43, a transistor Tr45, a transistor Tr47, and a capacitor C41.

The latch circuit LAT has the structure illustrated in FIG. 20A and the inverter circuit INV has the structure illustrated in FIG. 20B, in which case all the transistors included in the latch circuit LAT can be transistors having the same polarity, for example, n-channel transistors. Thus, the transistor Tr31, the transistor Tr35, the transistor Tr36, the transistor Tr41, the transistor Tr43, the transistor Tr45, and the transistor Tr47 as well as the transistor Tr33 can be OS transistors, for example. Accordingly, all the transistors included in the latch circuit LAT can be formed in the same step.

The semiconductor device of one embodiment of the present invention can be suitably used for the inverter circuit INV. For example, the transistor 100 or the transistor 200 illustrated in FIG. 1B or the like can be used as one or more of the transistor Tr41, the transistor Tr43, the transistor Tr45, and the transistor Tr47.

FIG. 21 illustrates a structure example of a sequential circuit 20. The sequential circuit 20 includes a circuit 11 and a circuit 12. The circuit 11 and the circuit 12 are electrically connected to each other through a wiring 15a and a wiring 15b. When a plurality of stages of the structure illustrated in FIG. 21 are connected to each other, a circuit such as a shift register can be formed in some cases.

The circuit 12 has a function of outputting a first signal to the wiring 15a and outputting a second signal to the wiring 15b in accordance with the potential of a signal LIN and the potential of a signal RIN. Here, the second signal is a signal obtained by inverting the first signal. That is, in the case where the first signal and the second signal are each a signal having two kinds of potentials, a high potential and a low potential, the circuit 12 outputs a low potential to the wiring 15b when outputting a high potential to the wiring 15a, and the circuit 12 outputs a high potential to the wiring 15b when outputting a low potential to the wiring 15a.

The circuit 11 includes a transistor 21, a transistor 22, and a capacitor C1. The transistor 21 and the transistor 22 are n-channel transistors. For a semiconductor where a channel is formed in each of the transistor 21 and the transistor 22, a metal oxide (hereinafter also referred to as an oxide semiconductor) exhibiting semiconductor characteristics can be suitably used. Note that the semiconductor is not limited to an oxide semiconductor; a semiconductor such as silicon (single crystal silicon, polycrystalline silicon, or amorphous silicon) or germanium or a compound semiconductor may be used.

The transistor of one embodiment of the present invention can be suitably used as each of the transistor 21 and the transistor 22. For example, the transistor 100 or the transistor 200 illustrated in FIG. 1B or the like can be suitably used as the transistor 21. The transistor 21 preferably includes a back gate. Thus, the transistor 100 or the transistor 200 illustrated in FIG. 4B or the like can be suitably used as the transistor 21, for example.

The transistor 21 includes a pair of gates (hereinafter referred to as a first gate and a second gate). In the transistor 21, the first gate is electrically connected to the wiring 15b, the second gate is electrically connected to one of a source and a drain of the transistor 21 and a wiring supplied with a potential VSS (also referred to as a first potential), and the other of the source and the drain thereof is electrically connected to one of a source and a drain of the transistor 22. In the transistor 22, a gate is electrically connected to the wiring 15a, and the other of the source and the drain thereof is electrically connected to a wiring supplied with a signal CLK. The capacitor C1 has a pair of electrodes, one of which is electrically connected to the one of the source and the drain of the transistor 22 and the other of the source and the drain of the transistor 21, and the other of which is electrically connected to a gate of the transistor 22 and the wiring 15a. The other of the source and the drain of the transistor 21, the one of the source and the drain of the transistor 22, and the one electrode of the capacitor C1 are electrically connected to an output terminal OUT. Note that the output terminal OUT is a portion supplied with an output potential from the circuit 11, and may be part of a wiring or part of an electrode.

The other of the source and the drain of the transistor 22 is supplied with a second potential and a third potential alternately as the signal CLK. The second potential can be a potential (e.g., a potential VDD) higher than the potential VSS. The third potential can be a potential lower than the second potential. As the third potential, the potential VSS can be suitably used. Note that the other of the source and the drain of the transistor 22 may be supplied with the potential VDD instead of the signal CLK.

When the wiring 15a and the wiring 15b are supplied with a high potential and a low potential, respectively, the transistor 22 is turned on and the transistor 21 is turned off. At this time, electrical continuity is established between the output terminal OUT and the wiring supplied with the signal CLK.

In the circuit 11, the output terminal OUT and the gate of the transistor 22 are electrically connected to each other through the capacitor C1; thus, an increase in the potential of the output terminal OUT is accompanied by an increase in the potential of the gate of the transistor 22 owing to a bootstrap effect. Here, in the case of the absence of the capacitor C1, using the same potential (assumed to be the potential VDD) as the second potential of the signal CLK and a high potential applied to the wiring 15a would cause the potential of the output terminal OUT to decrease from the potential VDD by the threshold voltage of the transistor 22. By contrast, in the presence of the capacitor C1, the potential of the gate of the transistor 22 increases to a potential almost twice as high as the potential VDD (specifically, a potential almost twice as high as the difference between the potential VDD and the potential VSS, or a potential almost twice as high as the difference between the potential VDD and the third potential), so that the potential VDD can be output to the output terminal OUT without being affected by the threshold voltage of the transistor 22. Accordingly, the sequential circuit 20 with high output performance can be obtained without increasing the number of kinds of power supply potentials.

Conversely, when the wiring 15a and the wiring 15b are supplied with a low potential and a high potential, respectively, the transistor 22 is turned off and the transistor 21 is turned on. At this time, electrical continuity is established between the output terminal OUT and the wiring supplied with the potential VSS, and the potential VSS is output to the output terminal OUT.

Here, the sequential circuit 20 can be used as a driver circuit of a display device. In particular, the sequential circuit 20 can be suitably used as a scan line driver circuit. At this time, in the case where a scanning line connected to a plurality of pixels of the display device is connected to the output terminal OUT, the duty ratio of an output signal output from the sequential circuit 20 to the output terminal OUT is much lower than that of the signal CLK or the like. In this case, the period for which the transistor 21 is on is much longer than the period for which the transistor 21 is off. That is, the period for which the first gate of the transistor 21 is supplied with a high potential is much longer than the period for which the first gate of the transistor 21 is supplied with a low potential. The use of the transistor of one embodiment of the present invention as the transistor 21 can inhibit degradation of the transistor characteristics in a state where a high potential is supplied to the first gate.

The use of the transistor of one embodiment of the present invention as the transistor 21 suitably prevents the threshold voltage from having a negative value, which enables the transistor 21 to easily have normally-off characteristics. In the case of the transistor 21 having normally-on characteristics, a leakage current occurs between the source and the drain when the voltage between the other gate of the transistor 21 and the source thereof is 0 V, preventing the potential of the output terminal OUT from being maintained. Therefore, to turn off the transistor 21, the other gate of the transistor 21 needs to be supplied with a potential lower than the potential VSS, which necessitates a plurality of power supplies. When the transistor of one embodiment of the present invention is used as the transistor 21, the sequential circuit 20 with high output performance can be obtained without increasing the number of kinds of power supply potentials.

With the use of the transistor of one embodiment of the present invention as the transistor 21, the saturation characteristics of the transistor 21 can be improved. This facilitates designing of the circuit 11 and enables the circuit 11 to operate stably.

With the use of the transistor 100, the occupied area can be reduced, so that a display device with a narrow bezel can be provided. The transistor 100 can be suitably used as a transistor required to have a high on-state current. Furthermore, the transistor 200 can be suitably used as a transistor required to have favorable saturation characteristics. Accordingly, the display device can have high performance.

<Structure Example of Pixel Circuit>

FIG. 22A illustrates a structure example of the pixel 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61.

The pixel circuit 51 illustrated in FIG. 22A is a 2Tr1C-type pixel circuit including a transistor 52A, a transistor 52B, and a capacitor 53.

One of a source and a drain of the transistor 52A is electrically connected to a gate of the transistor 52B and one terminal of the capacitor 53, and the other of the source electrode and the drain electrode of the transistor 52A is electrically connected to a wiring SL. A gate of the transistor 52A is electrically connected to a wiring GL. One of a source electrode and a drain electrode of the transistor 52B and the other terminal of the capacitor 53 are electrically connected to an anode of the light-emitting device 61. The other of the source electrode and the drain electrode of the transistor 52B is electrically connected to a wiring ANO. A cathode of the light-emitting device 61 is electrically connected to a wiring VCOM.

The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring that supplies a potential for supplying current to the light-emitting device 61. The transistor 52A has a function of controlling the conduction state and the non-conduction state between the wiring SL and the gate of the transistor 52B in accordance with the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

The transistor 52B has a function of controlling the amount of current flowing through the light-emitting device 61. The capacitor 53 has a function of holding a gate potential of the transistor 52B. The intensity of light emitted by the light-emitting device 61 can be controlled in accordance with an image signal supplied to the gate of the transistor 52B.

Some or all of the transistors included in the pixel circuit 51 may be provided with a back gate electrode. In the pixel circuit 51 illustrated in FIG. 22A, the transistor 52B includes a back gate electrode, and the back gate electrode is electrically connected to the one of the source electrode and the drain electrode of the transistor 52B. Note that the back gate electrode of the transistor 52B may be electrically connected to a gate electrode of the transistor 52B.

The above-described semiconductor device can be suitably used for the pixel circuit 51. For example, the transistor 100 illustrated in FIG. 1B or the like can be used as the transistor 52A, and the transistor 200 can be used as the transistor 52B.

FIG. 22B illustrates a structure example different from that of the pixel 230 illustrated in FIG. 22A. The pixel 230 includes a pixel circuit 51A and the light-emitting device 61.

The pixel circuit 51A illustrated in FIG. 22B is different from the pixel circuit 51 illustrated in FIG. 22A mainly in including a transistor 52C. The pixel circuit 51A is a 3Tr1C-type pixel circuit including the transistor 52A, the transistor 52B, the transistor 52C, and the capacitor 53.

One of a source electrode and a drain electrode of the transistor 52C is electrically connected to one of a source electrode and a drain electrode of the transistor 52B. The other of the source electrode and the drain electrode of the transistor 52C is electrically connected to a wiring V0. For example, a reference potential is supplied to the wiring V0.

The transistor 52C has a function of controlling the conduction state and the non-conduction state between the wiring V0 and the one of the source electrode and the drain electrode of the transistor 52B in accordance with the potential of the wiring GL. Variations in the gate-source potential of the transistor 52B can be inhibited by the reference potential of the wiring V0 supplied through the transistor 52C.

A current value that can be used for setting pixel parameters can be obtained with use of the wiring V0. Specifically, the wiring V0 can function as a monitor line for outputting current flowing through the transistor 52B or current flowing through the light-emitting device 61 to the outside. Current output to the wiring V0 is converted into a voltage by a source follower circuit and can be output to the outside. For another example, the current is converted into a digital signal by an A/D converter, and can be output to the outside.

The transistor 52B functioning as a driving transistor that controls current flowing through the light-emitting device 61 preferably has more favorable saturation characteristics than the transistor 52A functioning as a selection transistor for controlling a selection state of the pixel 230. The use of the transistor 200 with a long channel length as the transistor 52B enables the display device to have high reliability. Furthermore, when the transistor 100 is used as each of the transistor 52A and the transistor 52C, the area occupied by the pixel circuit 51A can be reduced, so that a high-definition display device can be obtained.

Note that the transistor 100 may also be used as the transistor 52B. The use of the transistor 100 having a short channel length as the transistor 52B enables the display device to have high luminance. Furthermore, the area occupied by the pixel circuit 51A can be reduced, so that a high-definition display device can be obtained.

The above-described semiconductor device can be suitably used for the pixel circuit 51A. For example, the transistor 100 illustrated in FIG. 1B or the like can be used as each of the transistor 52A and the transistor 52C, and the transistor 200 illustrated in FIG. 4B or the like can be used as the transistor 52B.

Note that there is no particular limitation on the pixel circuit that can be used for the display device of one embodiment of the present invention.

FIG. 23A illustrates a structure example of the display device of one embodiment of the present invention. FIG. 23A is a cross-sectional view of the peripheral circuit portion 164 and the display portion 162.

In the display portion 162, the transistor 100 and the transistor 200 are provided over the substrate 102. The transistor 100 and the transistor 200 provided in the display portion can each be used as a transistor included in the pixel circuit. The display portion can have a structure including only the transistor 100 or a structure including only the transistor 200. When the transistor 200 having favorable saturation characteristics is included in the display portion, a highly reliable display device with high display quality and multiple grayscale levels can be obtained, for example.

FIG. 23A illustrates one transistor 100 included in the peripheral circuit portion 164. Note that the peripheral circuit portion 164 preferably includes one or more transistors 100. Although not illustrated in FIG. 23A or the like, the peripheral circuit portion 164 may include the transistor 200.

FIG. 23A illustrates one transistor 100 and one transistor 200 included in the pixel circuit of the display portion 162, and illustrates an example where the transistor 100 is used as the transistor 52A of the pixel circuit 51 and the transistor 200 is used as the transistor 52B of the pixel circuit 51. Note that the electrical connection between the transistor 100 and the transistor 200 is omitted in FIG. 23A. For example, a first opening reaching the conductive layer 112b and a second opening reaching the conductive layer 204 are provided in the insulating layer 195. A first wiring is provided over the insulating layer 195 to cover the first opening and the second opening, whereby the conductive layer 112b and the conductive layer 204 can be electrically connected to each other through the first wiring.

In FIG. 23A, a capacitor included in the pixel circuit is omitted.

The insulating layer 195 is provided to cover the transistor 100 and the transistor 200, and an insulating layer 235 is provided to cover the insulating layer 195. The light-emitting device 61 can be provided over the insulating layer 235. FIG. 23A illustrates a pixel electrode 111 functioning as one electrode of the light-emitting device 61. The pixel electrode 111 is electrically connected to the conductive layer 212a through an opening 135 provided in the insulating layer 110, the insulating layer 106, the insulating layer 195, and the insulating layer 235. The insulating layer 235 has a function of reducing unevenness due to the transistor and making the formation surface of the light-emitting device 61 flatter. Note that in this specification and the like, the insulating layer 235 is referred to as a planarization layer in some cases.

An organic insulating film is suitable as the insulating layer 235. Examples of materials that can be used for the organic insulating film include an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimide-amide resin, a siloxane resin, a benzocyclobutene-based resin, a phenol resin, and precursors of these resins. Alternatively, the insulating layer 235 may have a stacked-layer structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably has a function of an etching protective layer. In that case, the formation of a depressed portion in the insulating layer 235 can be inhibited at the time of forming the pixel electrode 111. Alternatively, a depressed portion may be formed in the insulating layer 235 at the time of forming the pixel electrode 111.

The insulating layer 235 may have a stacked-layer structure of an organic insulating layer and an inorganic insulating layer. For example, the insulating layer 235 can have a stacked-layer structure of an organic insulating layer and an inorganic insulating layer over the organic insulating layer. An inorganic insulating layer provided as the outermost surface of the insulating layer 235 can function as an etching protective layer. This can inhibit a decrease in the planarity of the insulating layer 235, which is caused by etching of part of the insulating layer 235 in the formation of the pixel electrode 111.

As illustrated in FIG. 23B, the transistor 200 can be used as each of the transistor 52A and the transistor 52B.

Note that in the transistor 200 used as the transistor 52B, instead of the conductive layer 212a, the conductive layer 212b may be connected to the pixel electrode 111 as illustrated in FIG. 23C. The pixel electrode 111 illustrated in FIG. 23C is electrically connected to the conductive layer 212b through an opening 136 provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235.

The display device of one embodiment of the present invention can have any of the following structures: a top-emission structure in which light is emitted in a direction opposite to the substrate where the light-emitting device is formed, a bottom-emission structure in which light is emitted toward the substrate where the light-emitting device is formed, and a dual-emission structure in which light is emitted toward both surfaces.

Structure Example 1 of Display Device

FIG. 24A illustrates an example of cross sections of part of a region including the FPC 172, part of the peripheral circuit portion 164, part of the display portion 162, part of the connection portion 140, and part of a region including an end portion of the display device 50A.

The display device 50A illustrated in FIG. 24A includes transistors 205D, 205R, 205G, and 205B, a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, and the like between the substrate 151 and the substrate 152. The light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B are display elements included in the pixel 230R that emits red light, the pixel 230G that emits green light, and the pixel 230B that emits blue light, respectively.

The display device 50A employs an SBS structure. The SBS structure can optimize materials and structures of light-emitting elements and thus can extend freedom of choice of materials and structures, whereby the luminance and the reliability can be easily improved.

The display device 50A has a top-emission structure. The aperture ratio of pixels in a top-emission structure can be higher than that of pixels in a bottom-emission structure because a transistor and the like can be provided so as to overlap with a light-emitting region of a light-emitting element in the top-emission structure.

All of the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are formed over the substrate 151. These transistors can be manufactured using the same material through the same process.

Any one or more kinds of the above-described transistor 100 and transistor 200 can be used as at least one or more of the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B. For example, in the display portion 162, the transistor 200 having favorable saturation characteristics can be suitably used as each of the transistor 205R, the transistor 205G, and the transistor 205B which function as driver circuits of the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B, respectively. Thus, a display device with high reliability can be obtained. When the transistor 100 to the transistor 100 are used in the peripheral circuit portion 164, a display device that operates at high speed can be obtained. Furthermore, the area occupied by the peripheral circuit portion 164 can be reduced and a narrower bezel can be achieved.

The transistor provided in the peripheral circuit portion 164 is sometimes required to have a higher on-state current than the transistor provided in the display portion 162. The peripheral circuit portion 164 preferably employs a transistor with a short channel length. For example, the transistor 100 can be suitably used for the peripheral circuit portion 164. When the transistor 100 is used in the peripheral circuit portion 164, the occupation area can be reduced, so that a display device with a narrow bezel can be obtained. The transistor 200 can be suitably used as the transistor provided in the display portion 162. FIG. 24A illustrates a structure in which the transistor 100 is used as the transistor 205D and the transistor 200 is used as each of the transistor 205R, the transistor 205G, and the transistor 205B. Note that the transistor 100 may be used in the display portion 162, and the transistor 200 may be used in the peripheral circuit portion 164.

Note that the transistor included in the display device of this embodiment is not limited to the transistor included in the semiconductor device of one embodiment of the present invention. For example, the display device of this embodiment may include the transistor included in the semiconductor device of one embodiment of the present invention and a transistor having another structure in combination. The display device of this embodiment may include one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor, for example. A transistor included in the display device of this embodiment may have a top-gate structure or a bottom-gate structure. Gates may be provided above and below a semiconductor layer where a channel is formed.

The OS transistor can be suitably used as each of the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B.

A transistor including silicon in its channel formation region (a Si transistor) may be included in the display device of this embodiment. Examples of silicon include single crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, a transistor including LTPS in a semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used. The LTPS transistor has high field-effect mobility and favorable frequency characteristics.

To increase the emission luminance of the light-emitting element included in the pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. For this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher breakdown voltage between the source and the drain than a Si transistor, a high voltage can be applied between the source and the drain of the OS transistor. Thus, with the use of an OS transistor as a driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting element can be increased, resulting in an increase in emission luminance of the light-emitting element.

When transistors operate in a saturation region, a change in source-drain current relative to a change in gate-source voltage can be smaller in an OS transistor than in a Si transistor. Accordingly, when an OS transistor is used as the driving transistor included in the pixel circuit, current flowing between the source and the drain can be set minutely by a change in gate-source voltage; hence, the amount of current flowing through the light-emitting element can be controlled. Therefore, the number of gray levels in the pixel circuit can be increased.

Regarding saturation characteristics of current flowing when a transistor operates in a saturation region, current (saturation current) can flow more stably in an OS transistor than in a Si transistor even when the source-drain voltage gradually increases. Thus, with the use of an OS transistor as a driving transistor, current can be made to flow stably through the light-emitting element, for example, even when a variation in current-voltage characteristics of the EL element occurs. In other words, when the OS transistor operates in the saturation region, the source-drain current hardly changes with a change in the source-drain voltage; hence, the emission luminance of the light-emitting element can be stable.

The transistor included in the peripheral circuit portion 164 and the transistor included in the display portion 162 may have the same structure or different structures. The same structure or two or more kinds of structures may be employed for a plurality of transistors included in the peripheral circuit portion 164. Similarly, the same structure or two or more kinds of structures may be employed for a plurality of transistors included in the display portion 162.

All of the transistors included in the display portion 162 may be OS transistors or all of the transistors included in the display portion 162 may be Si transistors; alternatively, some of the transistors included in the display portion 162 may be OS transistors and the others may be Si transistors.

For example, when both an LTPS transistor and an OS transistor are used in the display portion 162, the display device can have low power consumption and high drive capability. Note that a structure in which an LTPS transistor and an OS transistor are used in combination is referred to as LTPO in some cases. Similarly, all of the transistors included in the peripheral circuit portion 164 may be OS transistors or all of the transistors included in the peripheral circuit portion 164 may be Si transistors; alternatively, some of the transistors included in the peripheral circuit portion 164 may be OS transistors and the others may be Si transistors.

The insulating layer 195 is provided to cover the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B and the insulating layer 235 is provided over the insulating layer 195.

The light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B are provided over the insulating layer 235.

The light-emitting element 130R includes a pixel electrode 111R over the insulating layer 235, an EL layer 113R over the pixel electrode 111R, and a common electrode 115 over the EL layer 113R. The light-emitting element 130R illustrated in FIG. 24A emits red light (R). The EL layer 113R includes a light-emitting layer that emits red light.

The light-emitting element 130G includes a pixel electrode 111G over the insulating layer 235, an EL layer 113G over the pixel electrode 111G, and the common electrode 115 over the EL layer 113G. The light-emitting element 130G illustrated in FIG. 24A emits green light (G). The EL layer 113G includes a light-emitting layer that emits green light.

The light-emitting element 130B includes a pixel electrode 111B over the insulating layer 235, an EL layer 113B over the pixel electrode 111B, and the common electrode 115 over the EL layer 113B. The light-emitting element 130B illustrated in FIG. 24A emits blue light (B). The EL layer 113B includes a light-emitting layer that emits blue light.

Although the EL layers 113R, 113G, and 113B have the same thickness in FIG. 24A, the present invention is not limited thereto. The EL layers 113R, 113G, and 113B may have different thicknesses. For example, the thicknesses of the EL layers 113R, 113G, and 113B are preferably set to match an optical path length that intensifies light emitted from each layer. In that case, a microcavity structure is obtained, and the color purity of light emitted from each light-emitting element can be improved.

The pixel electrode 111R is electrically connected to the conductive layer 112b included in the transistor 205R through an opening provided in the insulating layer 195 and the insulating layer 235. In a similar manner, the pixel electrode 111G is electrically connected to the conductive layer 112b included in the transistor 205G and the pixel electrode 111B is electrically connected to the conductive layer 112b included in the transistor 205B.

End portions of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition (also referred to as an embankment, a bank, or a spacer). The insulating layer 237 can have a single-layer structure or a stacked-layer structure including one or both of an inorganic insulating material and an organic insulating material. A material that can be used for the insulating layer 235 can be used for the insulating layer 237, for example. The insulating layer 237 can electrically isolate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically isolate light-emitting elements adjacent to each other.

The common electrode 115 is one continuous film shared by the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is electrically connected to a conductive layer 123 provided in the connection portion 140. The conductive layer 123 is preferably formed using a conductive layer formed using the same material through the same process as the pixel electrodes 111R, 111G, and 111B.

In the display device of one embodiment of the present invention, a conductive film that transmits visible light is used for the electrode through which light is extracted, which is either the pixel electrode or the common electrode. A conductive film reflecting visible light is preferably used for the electrode through which light is not extracted.

A conductive film that transmits visible light may be used also for the electrode through which light is not extracted. In that case, this electrode is preferably provided between a reflective layer and the EL layer. In other words, light emitted by the EL layer may be reflected by the reflective layer to be extracted from the display device.

As a material of the pair of electrodes of the light-emitting element, a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like can be used as appropriate. Specific examples of the material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and an alloy containing any of these metals in appropriate combination. Other examples of the material include indium tin oxide (also referred to as In—Sn oxide or ITO), In—Si—Sn oxide (also referred to as ITSO), indium zinc oxide (In—Zn oxide), and In—W—Zn oxide. Other examples of the material include an alloy containing aluminum (aluminum alloy), such as an alloy of aluminum, nickel, and lanthanum (Al—Ni—La), and an alloy containing silver, such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (also referred to as Ag—Pd—Cu or APC). Other examples of the material include an element belonging to Group 1 or Group 2 of the periodic table that is not described above (e.g., lithium, cesium, calcium, or strontium), a rare earth metal such as europium or ytterbium, an alloy containing an appropriate combination of any of these elements, and graphene.

The light-emitting element preferably employs a microcavity structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode having properties of transmitting and reflecting visible light (a transflective electrode), and the other is preferably an electrode having a property of reflecting visible light (a reflective electrode). When the light-emitting element has a microcavity structure, light obtained from the light-emitting layer can be resonated between the electrodes, whereby light emitted from the light-emitting element can be intensified.

The transparent electrode has a light transmittance higher than or equal to 40%. For example, an electrode having a visible light (light with wavelengths greater than or equal to 400 nm and less than 750 nm) transmittance higher than or equal to 40% is preferably used as the transparent electrode of the light-emitting element. The transflective electrode has a visible light reflectance higher than or equal to 10% and lower than or equal to 95%, preferably higher than or equal to 30% and lower than or equal to 80%. The reflective electrode has a visible light reflectance higher than or equal to 40% and lower than or equal to 100%, preferably higher than or equal to 70% and lower than or equal to 100%. These electrodes preferably have a resistivity lower than or equal to 1×10−2 Ωcm.

The EL layers 113R, 113G, and 113B are each provided to have an island shape. In FIG. 24A, an end portion of the EL layer 113R and an end portion of the EL layer 113G that are adjacent to each other overlap with each other, the end portion of the EL layer 113G and an end portion of the EL layer 113B that are adjacent to each other overlap with each other, and the end portion of the EL layer 113R and the end portion of the EL layer 113B that are adjacent to each other overlap with each other. When island-shaped EL layers are formed using a fine metal mask, end portions of the EL layers adjacent to each other may overlap with each other as illustrated in FIG. 24A; however, the present invention is not limited thereto. That is, it is also possible that the EL layers adjacent to each other do not overlap with each other and are apart from each other. It is also possible that the display device includes both a portion where the EL layers adjacent to each other overlap with each other and a portion where the EL layers adjacent to each other do not overlap with each other and are apart from each other.

Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer contains one or more kinds of light-emitting substances. As the light-emitting substance, a substance whose emission color is blue, violet, bluish violet, green, yellowish green, yellow, orange, red, or the like is appropriately used. Alternatively, as the light-emitting substance, a substance that emits near-infrared light can be used.

Examples of the light-emitting substance include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

The light-emitting layer may contain one or more kinds of organic compounds (e.g., a host material or an assist material) in addition to the light-emitting substance (a guest material). As one or more kinds of organic compounds, one or both of a substance with a high hole-transport property (a hole-transport material) and a substance with a high electron-transport property (an electron-transport material) can be used. As the one or more kinds of organic compounds, a substance with a bipolar property (also referred to as a substance with a high electron-transport property and a high hole-transport property) or a TADF material may be used.

The light-emitting layer preferably contains a phosphorescent material and a combination of a hole-transport material and an electron-transport material that easily forms an exciplex, for example. With such a structure, light emission can be efficiently obtained by ExTET (exciplex-triplet energy transfer), which is energy transfer from the exciplex to the light-emitting substance (the phosphorescent material). When a combination of materials is selected so as to form an exciplex that emits light whose wavelength overlaps with the wavelength of a lowest-energy-side absorption band of the light-emitting substance, energy can be transferred smoothly and light emission can be obtained efficiently. With this structure, high efficiency, low-voltage driving, and a long lifetime of the light-emitting element can be achieved at the same time.

In addition to the light-emitting layer, the EL layer can include one or more of a layer containing a substance having a high hole-injection property (a hole-injection layer), a layer containing a hole-transport material (a hole-transport layer), a layer containing a substance having a high electron-blocking property (an electron-blocking layer), a layer containing a substance having a high electron-injection property (an electron-injection layer), a layer containing an electron-transport material (an electron-transport layer), and a layer containing a substance having a high hole-blocking property (a hole-blocking layer). The EL layer may further include one or both of a bipolar material and a TADF material.

Either a low molecular compound or a high molecular compound can be used in the light-emitting element, and an inorganic compound may also be included. Each layer included in the light-emitting element can be formed by an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

The light-emitting element may employ a single structure (a structure including only one light-emitting unit) or a tandem structure (a structure including a plurality of light-emitting units). The light-emitting unit includes at least one light-emitting layer. In a tandem structure, a plurality of light-emitting units are connected in series with a charge-generation layer therebetween. The charge-generation layer has a function of injecting electrons into one of two light-emitting units and injecting holes to the other when a voltage is applied between the pair of electrodes. A tandem structure enables a light-emitting element capable of emitting light with high luminance. Furthermore, a tandem structure allows the amount of current needed for obtaining the same luminance to be reduced as compared to the case of using a single structure; thus, the display device can have higher reliability. A tandem structure may be referred to as a stack structure.

In the case of using a tandem light-emitting element in FIG. 24A, the EL layer 113R preferably includes a plurality of light-emitting units that emit red light, the EL layer 113G preferably includes a plurality of light-emitting units that emit green light, and the EL layer 113B preferably includes a plurality of light-emitting units that emit blue light.

A protective layer 131 is provided over the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded to each other with an adhesive layer 142. The substrate 152 is provided with a light-blocking layer 117. For example, a solid sealing structure or a hollow sealing structure can be employed to seal the light-emitting elements. In FIG. 24A, a solid sealing structure is employed, in which a space between the substrate 152 and the substrate 151 is filled with the adhesive layer 142. Alternatively, a hollow sealing structure may be employed, in which the space is filled with an inert gas (e.g., nitrogen or argon). In that case, the adhesive layer 142 may be provided not to overlap with the light-emitting element. Alternatively, the space may be filled with a resin other than the frame-shaped adhesive layer 142.

The protective layer 131 is provided at least in the display portion 162, and preferably provided to cover the entire display portion 162. The protective layer 131 is preferably provided to cover not only the display portion 162 but also the connection portion 140 and the peripheral circuit portion 164. It is further preferable that the protective layer 131 be provided to extend to the end portion of the display device 50A. Meanwhile, a connection portion 168 has a portion not provided with the protective layer 131 so that the FPC 172 and a conductive layer 166 are electrically connected to each other.

By providing the protective layer 131 over the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B, the reliability of the light-emitting elements can be increased.

The protective layer 131 may have a single-layer structure or a stacked-layer structure of two or more layers. There is no limitation on the conductivity of the protective layer 131. As the protective layer 131, at least one kind of insulating films, semiconductor films, and conductive films can be used.

The protective layer 131 including an inorganic film can inhibit deterioration of the light-emitting elements by preventing oxidation of the common electrode 115 and inhibiting entry of impurities (e.g., moisture and oxygen) into the light-emitting elements, for example; thus, the reliability of the display device can be improved.

As the protective layer 131, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used, for example. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably includes a nitride insulating film or a nitride oxide insulating film, and further preferably includes a nitride insulating film.

An inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, A1-Zn oxide, IGZO, or the like can be used as the protective layer 131. The inorganic film preferably has high resistance, specifically, higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

When light emitted from the light-emitting element is extracted through the protective layer 131, the protective layer 131 preferably has a high visible-light-transmitting property. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials having a high visible-light-transmitting property.

The protective layer 131 can have, for example, a stacked-layer structure of an aluminum oxide film and a silicon nitride film over the aluminum oxide film or a stacked-layer structure of an aluminum oxide film and an IGZO film over the aluminum oxide film. Such a stacked-layer structure can inhibit entry of impurities (e.g., water and oxygen) into the EL layer.

Furthermore, the protective layer 131 may include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film. Examples of an organic film that can be used as the protective layer 131 include organic insulating films that can be used as the insulating layer 235.

The connection portion 168 is provided in the substrate 151 in a region that does not overlap with the substrate 152. In the connection portion 168, the wiring 165 is electrically connected to the FPC 172 through the conductive layer 166 and a connection layer 242. An example in which the conductive layer 166 has a single-layer structure of a conductive layer obtained by processing the same conductive film as the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B is shown. The conductive layer 166 is exposed from the top surface of the connection portion 168. Thus, the connection portion 168 and the FPC 172 can be electrically connected to each other through the connection layer 242.

The wiring 165 is electrically connected to the transistor included in the peripheral circuit portion 164. FIG. 24A illustrates a structure in which the conductive layer 112b included in the transistor 205D extends and functions as the wiring 165. Note that the structure of the wiring 165 is not limited thereto.

The display device 50A has a top-emission structure. Light emitted from the light-emitting element is emitted toward the substrate 152 side. For the substrate 152, a material having a high visible-light-transmitting property is preferably used. The pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B contain a material that reflects visible light, and the counter electrode (the common electrode 115) contains a material that transmits visible light.

The light-blocking layer 117 is preferably provided on the surface of the substrate 152 on the substrate 151 side. The light-blocking layer 117 can be provided between adjacent light-emitting elements and in positions overlapping with the connection portion 140, the peripheral circuit portion 164, and the like.

A coloring layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or over the protective layer 131. When the color filter is provided so as to overlap with the light-emitting element, the color purity of light emitted from the pixel can be increased.

Moreover, a variety of optical members can be provided on the outer surface of the substrate 152 (the surface opposite to the substrate 151). Examples of the optical members include a polarizing plate, a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflective layer, and a light-condensing film. Furthermore, an antistatic film inhibiting the attachment of dust, a water repellent film inhibiting the attachment of stain, a hard coat film inhibiting generation of a scratch caused by the use, an impact-absorbing layer, or the like may be provided as a surface protective layer on the outer surface of the substrate 152. For example, a glass layer or a silica layer (SiOx layer) is preferably provided as the surface protective layer to inhibit the surface contamination and damage. The surface protective layer may be formed using DLC (diamond-like carbon), aluminum oxide (AlOx), a polyester-based material, a polycarbonate-based material, or the like. For the surface protective layer, a material having a high visible light transmittance is preferably used. The surface protective layer is preferably formed using a material with high hardness.

For each of the substrate 151 and the substrate 152, glass, quartz, ceramic, sapphire, a resin, a metal, an alloy, a semiconductor, or the like can be used. The substrate on the side from which light from the light-emitting element is extracted is formed using a material that transmits the light. When a flexible material is used for the substrate 151 and the substrate 152, the display device can have increased flexibility and a flexible display can be obtained. Furthermore, a polarizing plate may be used as at least one of the substrate 151 and the substrate 152.

For each of the substrate 151 and the substrate 152, any of the following can be used, for example: polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), a polyacrylonitrile resin, an acrylic resin, a polyimide resin, a polymethyl methacrylate resin, a polycarbonate (PC) resin, a polyethersulfone (PES) resin, polyamide resins (e.g., nylon and aramid), a polysiloxane resin, a cycloolefin resin, a polystyrene resin, a polyamide-imide resin, a polyurethane resin, a polyvinyl chloride resin, a polyvinylidene chloride resin, a polypropylene resin, a polytetrafluoroethylene (PTFE) resin, an ABS resin, and cellulose nanofiber. Glass that is thin enough to have flexibility may be used for at least one of the substrate 151 and the substrate 152.

In the case where a circularly polarizing plate overlaps with the display device, a highly optically isotropic substrate is preferably used as the substrate included in the display device. A highly optically isotropic substrate has a low birefringence (in other words, a small amount of birefringence). Examples of the film having high optical isotropy include a triacetyl cellulose (TAC, also referred to as cellulose triacetate) film, a cycloolefin polymer (COP) film, a cycloolefin copolymer (COC) film, and an acrylic film.

The adhesive layer 142 can be formed using any of a variety of curable adhesives, e.g., a reactive curable adhesive, a thermosetting curable adhesive, an anaerobic adhesive, or a photocurable adhesive such as an ultraviolet curable adhesive. Examples of these adhesives include an epoxy resin, an acrylic resin, a silicone resin, a phenol resin, a polyimide resin, an imide resin, a PVC (polyvinyl chloride) resin, a PVB (polyvinyl butyral) resin, and an EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as an epoxy resin, is preferred. A two-component-mixture-type resin may be used. An adhesive sheet or the like may be used.

As the connection layer 242, an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like can be used.

Structure Example 2 of Display Device

A display device 50B illustrated in FIG. 24B is different from the display device 50A mainly in that the subpixels of different colors include respective coloring layers (color filters or the like) and the light-emitting elements that include the common EL layer 113. Note that in the following description of display devices, the description of portions similar to those of the above-described display device may be omitted.

The display device 50B illustrated in FIG. 24B is different from the display device 50A illustrated in FIG. 24A in that the transistors 205D, 205R, 205G, and 205B, the light-emitting elements 130R, 130G, and 130B, a coloring layer 132R transmitting red light, a coloring layer 132G transmitting green light, a coloring layer 132B transmitting blue light, and the like are included between the substrate 151 and the substrate 152. Note that FIG. 24B selectively illustrates the difference from FIG. 24A. The structure illustrated in FIG. 24B can be combined with the structure of the region including the FPC 172, the peripheral circuit portion 164, the stacked-layer structure from the substrate 151 to the insulating layer 235 in the display portion 162, the connection portion 140, and the end portion, which is illustrated in FIG. 24A.

The light-emitting element 130R includes the pixel electrode 111R, the EL layer 113 over the pixel electrode 111R, and the common electrode 115 over the EL layer 113. Light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50B through the coloring layer 132R.

The light-emitting element 130G includes the pixel electrode 111G, the EL layer 113 over the pixel electrode 111G, and the common electrode 115 over the EL layer 113. Light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50B through the coloring layer 132G.

The light-emitting element 130B includes the pixel electrode 111B, the EL layer 113 over the pixel electrode 111B, and the common electrode 115 over the EL layer 113. Light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50B through the coloring layer 132B.

The EL layer 113 and the common electrode 115 are shared between the light-emitting elements 130R, 130G, and 130B. The number of manufacturing steps can be smaller in the case where the EL layer 113 is shared between the subpixels of different colors than the case where the subpixels of different colors include different EL layers.

The light-emitting elements 130R, 130G, and 130B illustrated in FIG. 24B emit white light, for example. When white light emitted from the light-emitting elements 130R, 130G, and 130B passes through the coloring layers 132R, 132G, and 132B, light of desired colors can be obtained.

In the light-emitting element that emits white light, two or more light-emitting layers are preferably included. In the case where two light-emitting layers are used to obtain white light emission, the two light-emitting layers are selected so that emission colors of the two light-emitting layers have a relationship of complementary colors. For example, when an emission color of a first light-emitting layer and an emission color of a second light-emitting layer are complementary colors, the light-emitting element can be configured to emit white light as a whole. In the case where three or more light-emitting layers are used to obtain white light, the light-emitting element is configured to emit white light as a whole by combining emission colors of the three or more light-emitting layers.

For example, the EL layer 113 preferably includes a light-emitting layer containing a light-emitting substance that emits blue light and a light-emitting layer containing a light-emitting substance that emits visible light having a longer wavelength than blue light. The EL layer 113 preferably includes a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light, for example. Alternatively, the EL layer 113 preferably includes a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light, for example.

A light-emitting element that emits white light preferably has a tandem structure. Specific examples include a two-unit tandem structure including a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light; a two-unit tandem structure including a light-emitting unit that emits red light and green light and a light-emitting unit that emits blue light; a three-unit tandem structure in which a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light are stacked in this order; and a three-unit tandem structure in which a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and red light, and a light-emitting unit that emits blue light are stacked in this order. Examples of the number of stacked light-emitting units and the order of colors from the anode side include a two-unit structure of B and Y; a two-unit structure of B and a light-emitting unit X; a three-unit structure of B, Y, and B; and a three-unit structure of B, X, and B. Examples of the number of light-emitting layers stacked in the light-emitting unit X and the order of colors from an anode side include a two-layer structure of R and Y; a two-layer structure of R and G; a two-layer structure of G and R; a three-layer structure of G, R, and G; and a three-layer structure of R, G, and R. Another layer may be provided between two light-emitting layers.

Alternatively, the light-emitting elements 130R, 130G, and 130B illustrated in FIG. 24B emit blue light, for example. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In the pixel 230B that emits blue light, blue light emitted from the light-emitting element 130B can be extracted. In each of the pixel 230R that emits red light and the pixel 230G that emits green light, a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152 so that blue light emitted from the light-emitting element 130R or 130G is converted into light with a longer wavelength, whereby red light or green light can be extracted. Furthermore, it is preferable that over the light-emitting element 130R, the coloring layer 132R be provided between the color conversion layer and the substrate 152 and over the light-emitting element 130G, the coloring layer 132G be provided between the color conversion layer and the substrate 152. In some cases, part of light emitted from the light-emitting element is transmitted through the color conversion layer without being converted. When light transmitted through the color conversion layer is extracted through the coloring layer, light other than light of the desired color can be absorbed by the coloring layer, and color purity of light exhibited by a subpixel can be improved.

Structure Example 3 of Display Device

A display device 50C illustrated in FIG. 25 is different from the display device 50B mainly in having a bottom-emission structure.

Light emitted from the light-emitting element is emitted toward the substrate 151 side. For the substrate 151, a material having a high visible-light-transmitting property is preferably used. By contrast, there is no limitation on the light-transmitting property of a material used for the substrate 152.

The light-blocking layer 117 is preferably formed between the substrate 151 and the transistor. FIG. 25 illustrates an example where the light-blocking layers 117 are provided over the substrate 151, an insulating layer 153 is provided over the light-blocking layers 117, and the transistor 205D, the transistor 205R (not illustrated), the transistor 205G, the transistor 205B, and the like are provided over the insulating layer 153. In addition, the coloring layer 132R, the coloring layer 132G, and the coloring layer 132B are provided over the insulating layer 195 and the insulating layer 235 is provided over the coloring layer 132R, the coloring layer 132G, and the coloring layer 132B.

The light-emitting element 130G overlapping with the coloring layer 132G includes the pixel electrode 111G, the EL layer 113, and the common electrode 115.

The light-emitting element 130B overlapping with the coloring layer 132B includes the pixel electrode 111B, the EL layer 113, and the common electrode 115.

A material having a high visible-light-transmitting property is used for each of the pixel electrodes 111G and 111B. A material that reflects visible light is preferably used for the common electrode 115. In the display device having a bottom-emission structure, a metal or the like having low resistance can be used for the common electrode 115; thus, a voltage drop due to the resistance of the common electrode 115 can be suppressed and the display quality can be high.

Structure Example 4 of Display Device

A display device 50D illustrated in FIG. 26A is different from the display device 50A mainly in including a light-receiving element 130S.

The display device 50D includes light-emitting elements and a light-receiving element in a pixel. In the display device 50D, organic EL elements are preferably used as the light-emitting elements and an organic photodiode is preferably used as the light-receiving element. The organic EL elements and the organic photodiode can be formed over the same substrate. Thus, the organic photodiode can be incorporated in a display device including the organic EL elements.

The display device 50D can detect the touch or approach of an object while displaying an image because the pixel includes the light-emitting elements and the light-receiving element and thus has a light-receiving function. Accordingly, the display portion 162 has one or both of an image capturing function and a sensing function in addition to a function of displaying an image. For example, all the subpixels included in the display device 50D can display an image; alternatively, some of the subpixels can emit light as a light source, some of the rest of the subpixels can detect light, and the other subpixels can display an image.

Accordingly, a light-receiving portion and a light source do not need to be provided separately from the display device 50D; hence, the number of components of an electronic device can be reduced. For example, a biometric authentication device provided in the electronic device or a capacitive touch panel for scroll operation or the like is not necessarily provided separately. Thus, with the use of the display device 50D, the electronic device can be provided at lower manufacturing costs.

When the light-receiving elements are used as an image sensor, the display device 50D can capture an image using the light-receiving elements. For example, image capturing for personal authentication with the use of a fingerprint, a palm print, the iris, the shape of a blood vessel (including the shape of a vein and the shape of an artery), a face, or the like is possible by using the image sensor.

Moreover, the light-receiving element can be used in a touch sensor (also referred to as a direct touch sensor), a contactless sensor (also referred to as a hover sensor, a hover touch sensor, or a touchless sensor), or the like. The touch sensor can detect an object (e.g., a finger, a hand, or a pen) when the display device and the object come in direct contact with each other. Furthermore, the contactless sensor can detect the object even when the object is not in contact with the display device.

The light-receiving element 130S includes a pixel electrode 111S over the insulating layer 235, a functional layer 113S over the pixel electrode 111S, and the common electrode 115 over the functional layer 113S. Light Ln enters the functional layer 113S from the outside of the display device 50D.

The pixel electrode 111S is electrically connected to the conductive layer 112b included in a transistor 205S through an opening provided in the insulating layer 195 and the insulating layer 235.

An end portion of the pixel electrode 111S is covered with the insulating layer 237.

The common electrode 115 is one continuous film provided to be shared by the light-receiving element 130S, the light-emitting element 130R (not illustrated), the light-emitting element 130G, and the light-emitting element 130B. The common electrode 115 shared by the light-emitting elements and the light-receiving element is electrically connected to the conductive layer 123 provided in the connection portion 140.

The functional layer 113S includes at least an active layer (also referred to as a photoelectric conversion layer). The active layer includes a semiconductor. Examples of the semiconductor include an inorganic semiconductor such as silicon and an organic semiconductor including an organic compound. This embodiment illustrates an example where an organic semiconductor is used as the semiconductor included in the active layer. An organic semiconductor is preferably used, in which case the light-emitting layer and the active layer can be formed by the same method (e.g., a vacuum evaporation method) and thus the same manufacturing apparatus can be used.

In addition to the active layer, the functional layer 113S may further include a layer containing a substance having a high hole-transport property, a substance having a high electron-transport property, a substance having a bipolar property (a substance having a high electron-transport property and a high hole-transport property), or the like. Without limitation to the above, the functional layer 113S may further include a layer containing a substance having a high hole-injection property, a hole-blocking material, a substance having a high electron-injection property, an electron-blocking material, or the like. Layers other than the active layer included in the light-receiving element can be formed using a material that can be used for the light-emitting element.

Either a low molecular compound or a high molecular compound can be used in the light-receiving element, and an inorganic compound may also be included. Each layer included in the light-receiving element can be formed by an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

When part of the peripheral region of the functional layer 113S of the light-receiving element is covered with the light-blocking layer 117, the range where light is detected by the light-receiving element can be controlled. The light-blocking layer 117 has openings in a region overlapping with the EL layer of the light-emitting element and a region overlapping with the functional layer 113S. FIG. 26A illustrates an example in which a width Ws of the opening overlapping with the functional layer 113S is smaller than a width We of the opening overlapping with the EL layer. When the width Ws is narrowed, for example, the resolution of the light-receiving element is increased in some cases.

The display device 50D illustrated in FIG. 26B and FIG. 26C includes, between the substrate 151 and the substrate 152, a layer 353 including a light-receiving element, a circuit layer 355, and a layer 357 including a light-emitting element.

The layer 353 includes the light-receiving element 130S, for example. The layer 357 includes the light-emitting elements 130R, 130G, and 130B, for example.

The circuit layer 355 includes a circuit for driving a light-receiving element and a circuit for driving a light-emitting element. The circuit layer 355 includes the transistors 205R, 205G, and 205B, for example. The circuit layer 355 can further include one or more of a switch, a capacitor, a resistor, a wiring, a terminal, and the like.

FIG. 26B illustrates an example where the light-receiving element 130S is used as a touch sensor. Light emitted from the light-emitting element in the layer 357 is reflected by a finger 352 that touches the display device 50D as illustrated in FIG. 26B; then, the light-receiving element in the layer 353 detects the reflected light. Thus, the touch of the finger 352 on the display device 50D can be detected.

FIG. 26C illustrates an example where the light-receiving element 130S is used as a contactless sensor. Light emitted from the light-emitting element in the layer 357 is reflected by the finger 352 that is close to (i.e., that does not touch) the display device 50D as illustrated in FIG. 26C; then, the light-receiving element in the layer 353 detects the reflected light.

Structure Example 5 of Display Device

A display device 50E illustrated in FIG. 27A is an example of a display device where a device having an MML (metal maskless) structure is employed. In other words, the display device 50E includes a light-emitting element that is formed without using a fine metal mask. The stacked-layer structure from the substrate 151 to the insulating layer 235 and the stacked-layer structure from the protective layer 131 to the substrate 152 are similar to those in the display device 50A; therefore, description thereof is omitted.

In FIG. 27A, the light-emitting elements 130R, 130G, and 130B are provided over the insulating layer 235.

The light-emitting element 130R includes a conductive layer 124R over the insulating layer 235, a conductive layer 126R over the conductive layer 124R, a layer 133R over the conductive layer 126R, a common layer 114 over the layer 133R, and the common electrode 115 over the common layer 114. The light-emitting element 130R illustrated in FIG. 27A emits red light (R). The layer 133R includes a light-emitting layer that emits red light. In the light-emitting element 130R, the layer 133R and the common layer 114 can be collectively referred to as an EL layer. One or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.

The light-emitting element 130G includes a conductive layer 124G over the insulating layer 235, a conductive layer 126G over the conductive layer 124G, a layer 133G over the conductive layer 126G, the common layer 114 over the layer 133G, and the common electrode 115 over the common layer 114. The light-emitting element 130G illustrated in FIG. 27A emits green light (G). The layer 133G includes a light-emitting layer that emits green light. In the light-emitting element 130G, the layer 133G and the common layer 114 can be collectively referred to as an EL layer. One or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.

The light-emitting element 130B includes a conductive layer 124B over the insulating layer 235, a conductive layer 126B over the conductive layer 124B, a layer 133B over the conductive layer 126B, the common layer 114 over the layer 133B, and the common electrode 115 over the common layer 114. The light-emitting element 130B illustrated in FIG. 27A emits blue light (B). The layer 133B includes a light-emitting layer that emits blue light. In the light-emitting element 130B, the layer 133B and the common layer 114 can be collectively referred to as an EL layer. One or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.

In this specification and the like, in the EL layers included in the light-emitting elements, the island-shaped layer provided in each light-emitting element is referred to as the layer 133B, the layer 133G, or the layer 133R, and the layer shared by the plurality of light-emitting elements is referred to as the common layer 114. Note that in this specification and the like, the layer 133R, the layer 133G, and the layer 133B are sometimes referred to as island-shaped EL layers, EL layers formed in an island shape, or the like, in which case the common layer 114 is not included.

The layers 133R, 133G, and 133B are isolated from each other. When the EL layer is provided to have an island shape for each light-emitting element, a leakage current between adjacent light-emitting elements can be inhibited. This can prevent unintended light emission due to crosstalk, so that a display device with extremely high contrast can be obtained.

Although the layers 133R, 133G, and 133B have the same thickness in FIG. 27A, the present invention is not limited thereto. The layers 133R, 133G, and 133B may have different thicknesses.

The conductive layer 124R is electrically connected to the conductive layer 112b included in the transistor 205R through an opening provided in the insulating layer 195 and the insulating layer 235. In a similar manner, the conductive layer 124G is electrically connected to the conductive layer 112b included in the transistor 205G and the conductive layer 124B is electrically connected to the conductive layer 112b included in the transistor 205B.

The conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235. A layer 128 is embedded in each of the depressed portions of the conductive layers 124R, 124G, and 124B.

The layer 128 has a function of filling the depressed portions of the conductive layers 124R, 124G, and 124B. The conductive layers 126R, 126G, and 126B electrically connected to the conductive layers 124R, 124G, and 124B, respectively, are provided over the conductive layers 124R, 124G, and 124B and the layer 128. Thus, regions overlapping with the depressed portions of the conductive layers 124R, 124G, and 124B can also be used as the light-emitting regions, increasing the aperture ratio of the pixels. A conductive layer functioning as a reflective electrode is preferably used as each of the conductive layer 124R and the conductive layer 126R.

The layer 128 may be an insulating layer or a conductive layer. Any of a variety of inorganic insulating materials, organic insulating materials, and conductive materials can be used for the layer 128 as appropriate. Specifically, the layer 128 is preferably formed using an insulating material and is particularly preferably formed using an organic insulating material. For the layer 128, an organic insulating material that can be used for the insulating layer 237 can be used, for example.

Although FIG. 27A illustrates an example where the top surface of the layer 128 includes a flat portion, the shape of the layer 128 is not particularly limited. The top surface of the layer 128 may include at least one of a convex surface, a concave surface, and a flat surface.

The level of the top surface of the layer 128 and the level of the top surface of the conductive layer 124R may be the same or substantially the same, or may be different from each other. For example, the level of the top surface of the layer 128 may be either lower or higher than the level of the top surface of the conductive layer 124R.

An end portion of the conductive layer 126R may be aligned with an end portion of the conductive layer 124R or may cover a side surface of the end portion of the conductive layer 124R. The end portions of the conductive layer 124R and the conductive layer 126R each preferably have a tapered shape. Specifically, the end portions of the conductive layer 124R and the conductive layer 126R each preferably have a tapered shape with a taper angle less than 90°. In the case where the end portion of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. When the side surface of the pixel electrode has a tapered shape, coverage with an EL layer provided along the side surface of the pixel electrode can be improved.

Since the conductive layers 124G and 126G and the conductive layers 124B and 126B are similar to the conductive layers 124R and 126R, the detailed description thereof is omitted.

The top surface and a side surface of the conductive layer 126R are covered with the layer 133R. Similarly, the top surface and a side surface of the conductive layer 126G are covered with the layer 133G, and the top surface and a side surface of the conductive layer 126B are covered with the layer 133B. Accordingly, regions provided with the conductive layers 126R, 126G, and 126B can be entirely used as the light-emitting regions of the light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixels.

A side surface and part of the top surface of each of the layers 133R, 133G, and 133B are covered with insulating layers 125 and 127. The common layer 114 is provided over the layers 133R, 133G, and 133B and the insulating layers 125 and 127, and the common electrode 115 is provided over the common layer 114. The common layer 114 and the common electrode 115 are each one continuous film shared by a plurality of light-emitting elements.

In FIG. 27A, the insulating layer 237 illustrated in FIG. 24A or the like is not provided between the conductive layer 126R and the layer 133R. That is, an insulating layer (also referred to as a partition, a bank, a spacer, or the like) in contact with the pixel electrode and covering an end portion of the top surface of the pixel electrode is not provided in the display device 50E. Thus, the interval between adjacent light-emitting elements can be extremely shortened. Accordingly, the display device can have high definition or high resolution. In addition, a mask for forming the insulating layer is not needed, which leads to a reduction in manufacturing cost of the display device.

As described above, the layers 133R, 133G, and 133B each include the light-emitting layer. The layers 133R, 133G, and 133B each preferably include the light-emitting layer and a carrier-transport layer (an electron-transport layer or a hole-transport layer) over the light-emitting layer. Alternatively, the layers 133R, 133G, and 133B each preferably include the light-emitting layer and a carrier-blocking layer (a hole-blocking layer or an electron-blocking layer) over the light-emitting layer. Alternatively, the layers 133R, 133G, and 133B each preferably include the light-emitting layer, a carrier-blocking layer over the light-emitting layer, and a carrier-transport layer over the carrier-blocking layer. Since surfaces of the layers 133R, 133G, and 133B are exposed in the manufacturing process of the display device, providing one or both of the carrier-transport layer and the carrier-blocking layer over the light-emitting layer inhibits the light-emitting layer from being exposed on the outermost surface, so that damage to the light-emitting layer can be reduced. Thus, the reliability of the light-emitting elements can be increased.

The common layer 114 includes, for example, an electron-injection layer or a hole-injection layer. Alternatively, the common layer 114 may be a stack of an electron-transport layer and an electron-injection layer, or may be a stack of a hole-transport layer and a hole-injection layer. The common layer 114 is shared by the light-emitting elements 130R, 130G, and 130B.

The side surfaces of the layer 133R, the layer 133G, and the layer 133B are each covered with the insulating layer 125. The insulating layer 127 covers the side surfaces of the layer 133R, the layer 133G, and the layer 133B with the insulating layer 125 therebetween.

The side surfaces (and part of the top surfaces) of the layer 133R, the layer 133G, and the layer 133B are covered with at least one of the insulating layer 125 and the insulating layer 127, so that the common layer 114 (or the common electrode 115) can be inhibited from being in contact with the side surfaces of the pixel electrodes and the layers 133R, 133G, and 133B, leading to inhibition of a short circuit of the light-emitting elements. Thus, the reliability of the light-emitting elements can be increased.

The insulating layer 125 is preferably in contact with the side surfaces of the layer 133R, the layer 133G, and the layer 133B. The insulating layer 125 in contact with the layer 133R, the layer 133G, and the layer 133B can prevent film separation of the layer 133R, the layer 133G, and the layer 133B, whereby the reliability of the light-emitting elements can be increased.

The insulating layer 127 is provided over the insulating layer 125 to fill a depressed portion of the insulating layer 125. The insulating layer 127 preferably covers at least part of a side surface of the insulating layer 125.

The insulating layer 125 and the insulating layer 127 can fill a gap between adjacent island-shaped layers, whereby unevenness with a large level difference on the formation surface of layers (e.g., a carrier-injection layer and the common electrode) provided over the island-shaped layers can be reduced and the formation surface can be flatter. Consequently, coverage with the carrier-injection layer, the common electrode, and the like can be improved.

The common layer 114 and the common electrode 115 are provided over the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, there is a step due to a region where the pixel electrode and the island-shaped EL layer are provided and a region where neither the pixel electrode nor the island-shaped EL layer is provided (a region between the light-emitting elements). In the display device of one embodiment of the present invention, the step can be reduced with the insulating layer 125 and the insulating layer 127, and the coverage with the common layer 114 and the common electrode 115 can be improved. Thus, connection defects caused by step disconnection can be inhibited. In addition, an increase in electric resistance, which is caused by local thinning of the common electrode 115 due to the step, can be inhibited.

The top surface of the insulating layer 127 preferably has a shape with higher flatness. The top surface of the insulating layer 127 may include at least one of a flat surface, a convex surface, and a concave surface. For example, the top surface of the insulating layer 127 preferably has a convex shape with high flatness.

The insulating layer 125 can be an insulating layer containing an inorganic material. As the insulating layer 125, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used, for example. Specific examples of these inorganic insulating films are as described above. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. In particular, aluminum oxide is preferable because it has high selectivity with respect to the EL layer in etching and has a function of protecting the EL layer in forming the insulating layer 127 which is to be described later. In particular, when an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method is used as the insulating layer 125, the insulating layer 125 having few pinholes and an excellent function of protecting the EL layer can be formed. The insulating layer 125 may have a stacked-layer structure of a film formed by an ALD method and a film formed by a sputtering method. The insulating layer 125 may have a stacked-layer structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method, for example.

The insulating layer 125 preferably has a function of a barrier insulating layer against at least one of water and oxygen. The insulating layer 125 preferably has a function of inhibiting diffusion of at least one of water and oxygen. Alternatively, the insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) at least one of water and oxygen.

When the insulating layer 125 has a function of the barrier insulating layer or a gettering function, entry of impurities (typically, at least one of water and oxygen) that would be diffused into the light-emitting elements from the outside can be inhibited. With this structure, a highly reliable light-emitting element and a highly reliable display device can be provided.

The insulating layer 125 preferably has a low impurity concentration. Accordingly, degradation of the EL layer, which is caused by entry of impurities into the EL layer from the insulating layer 125, can be inhibited. In addition, when the impurity concentration is reduced in the insulating layer 125, a barrier property against at least one of water and oxygen can be increased. For example, the insulating layer 125 preferably has one of a sufficiently low hydrogen concentration and a sufficiently low carbon concentration, desirably has both of them.

The insulating layer 127 provided over the insulating layer 125 has a function of filling unevenness with a large level difference on the insulating layer 125, which is formed between the adjacent light-emitting elements. In other words, the insulating layer 127 has an effect of improving the planarity of the formation surface of the common electrode 115.

As the insulating layer 127, an insulating layer containing an organic material can be suitably used. As the organic material, a photosensitive organic resin is preferably used, and for example, a photosensitive resin composite containing an acrylic resin is preferably used. Note that in this specification and the like, an acrylic resin refers to not only a polymethacrylic acid ester or a methacrylic resin, but also all the acrylic polymer in a broad sense in some cases.

Alternatively, the insulating layer 127 may be formed using an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimide-amide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenol resin, precursors of these resins, or the like. The insulating layer 127 may be formed using an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. A photoresist may be used as the photosensitive resin. As the photosensitive organic resin, either a positive-type material or a negative-type material may be used.

The insulating layer 127 may be formed using a material absorbing visible light. When the insulating layer 127 absorbs light emitted from the light-emitting element, light leakage (stray light) from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 can be suppressed. Thus, the display quality of the display device can be improved. Since no polarizing plate is required to improve the display quality of the display device, a lightweight and thin display device can be achieved.

Examples of the material absorbing visible light include a material containing a pigment of black or the like, a material containing a dye, a light-absorbing resin material (e.g., polyimide), and a resin material that can be used for color filters (a color filter material). Using a resin material obtained by stacking or mixing color filter materials of two or three or more colors is particularly preferred to enhance the effect of blocking visible light. In particular, mixing color filter materials of three or more colors enables the formation of a black or nearly black resin layer.

Structure Example 6 of Display Device

A display device 50F illustrated in FIG. 27B is different from the display device 50E mainly in that the light-emitting elements including the layers 133 and coloring layers (color filters or the like) are used for the subpixels of different colors.

The structure illustrated in FIG. 27B can be combined with the structure of the region including the FPC 172, the peripheral circuit portion 164, the stacked-layer structure from the substrate 151 to the insulating layer 235 in the display portion 162, the connection portion 140, and the end portion, which is illustrated in FIG. 27A.

The display device 50F illustrated in FIG. 27B includes, the light-emitting elements 130R, 130G, and 130B, the coloring layer 132R transmitting red light, the coloring layer 132G transmitting green light, the coloring layer 132B transmitting blue light, and the like.

Light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50F through the coloring layer 132R. Similarly, light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50F through the coloring layer 132G. Light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50F through the coloring layer 132B.

The light-emitting elements 130R, 130G, and 130B each include the layer 133. The three layers 133 are formed using the same process and the same material. The three layers 133 are isolated from each other. When the EL layer is provided to have an island shape for each light-emitting element, a leakage current between adjacent light-emitting elements can be inhibited. This can prevent unintended light emission due to crosstalk, so that a display device with extremely high contrast can be obtained.

The light-emitting elements 130R, 130G, and 130B illustrated in FIG. 27B emit white light, for example. When white light emitted from the light-emitting elements 130R, 130G, and 130B passes through the coloring layers 132R, 132G, and 132B, light of desired colors can be obtained.

Alternatively, the light-emitting elements 130R, 130G, and 130B illustrated in FIG. 27B emit blue light, for example. In this case, the layer 133 includes one or more light-emitting layers that emit blue light. In the subpixel that emits blue light, blue light emitted from the light-emitting element 130B can be extracted. In each of the subpixel that emits red light and the subpixel that emits green light, a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152 so that blue light emitted from the light-emitting element 130R or 130G is converted into light with a longer wavelength, whereby red light or green light can be extracted. Furthermore, it is preferable that over the light-emitting element 130R, the coloring layer 132R be provided between the color conversion layer and the substrate 152 and over the light-emitting element 130G, the coloring layer 132G be provided between the color conversion layer and the substrate 152. When light transmitted through the color conversion layer is extracted through the coloring layer, light other than light of the desired color can be absorbed by the coloring layer, and color purity of light exhibited by a subpixel can be improved.

Note that the structure of the light-emitting element 130 illustrated in the display device 50E and the display device 50F can be employed for the bottom-emission display device illustrated as the display device 50C. In that case, a material having a high visible-light-transmitting property is used for each of the pixel electrodes 111 of the light-emitting elements 130, and a material reflecting visible light is used for the common electrode 115.

<Manufacturing Method Example of Display Device>

A method for manufacturing a display device where a device having an MML (metal maskless) structure is employed will be described below with reference to FIG. 28. Here, steps of manufacturing light-emitting elements without using a fine metal mask will be described in detail. FIG. 28 illustrates a cross-sectional view of three light-emitting elements included in the display portion 162 and the connection portion 140 in the steps.

For manufacture of the light-emitting elements, a vacuum process such as an evaporation method and a solution process such as a spin coating method or an inkjet method can be used. Examples of an evaporation method include physical vapor deposition methods (PVD methods) such as a sputtering method, an ion plating method, an ion beam evaporation method, a molecular beam evaporation method, and a vacuum evaporation method, and a chemical vapor deposition method (CVD method). Specifically, functional layers (e.g., a hole-injection layer, a hole-transport layer, a hole-blocking layer, a light-emitting layer, an electron-blocking layer, an electron-transport layer, an electron-injection layer, and a charge-generation layer) included in the EL layer can be formed by an evaporation method (e.g., a vacuum evaporation method), a coating method (e.g., a dip coating method, a die coating method, a bar coating method, a spin coating method, or a spray coating method), a printing method (e.g., inkjet method, a screen printing (stencil) method, an offset printing (planography) method, a flexography (relief printing) method, a gravure printing method, or a micro-contact printing method), or the like.

In the method described below for manufacturing the display device, the island-shaped layer (the layer including the light-emitting layer) is formed not by using a fine metal mask but by forming a light-emitting layer on the entire surface and processing the light-emitting layer by a photolithography method. Accordingly, a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve, can be manufactured. Moreover, light-emitting layers can be formed separately for the respective colors, enabling the display device to perform extremely clear display with high contrast and high display quality. Moreover, providing a sacrificial layer over the light-emitting layer can reduce damage to the light-emitting layer in the manufacturing process of the display device, resulting in an increase in reliability of the light-emitting element.

For example, in the case where the display device includes three kinds of light-emitting elements, which are a light-emitting element that emits blue light, a light-emitting element that emits green light, and a light-emitting element that emits red light, three kinds of island-shaped light-emitting layers can be formed by repeating formation of a light-emitting layer and processing by photolithography three times.

First, the pixel electrodes 111R, 111G, and 111B and the conductive layer 123 are formed over the substrate 151 provided with the transistors 205R, 205G, and 205B and the like (not illustrated) (FIG. 28A).

A conductive film to be the pixel electrodes can be formed by a sputtering method or a vacuum evaporation method, for example. A resist mask is formed over the conductive film by a photolithography process, and then the conductive film is processed, whereby the pixel electrodes 111R, 111G, and 111B and the conductive layer 123 can be formed. The conductive film can be processed by either one or both of a wet etching method and a dry etching method.

Next, a film 133Bf to be the layer 133B later is formed over the pixel electrodes 111R, 111G, and 111B (FIG. 28A). The film 133Bf (to be the layer 133B later) includes a light-emitting layer that emits blue light.

In an example described in this embodiment, an island-shaped EL layer included in the light-emitting element that emits blue light is formed first, and then island-shaped EL layers included in the light-emitting elements that emit light of the other colors are formed.

In the formation process of the island-shaped EL layers, the pixel electrode of the light-emitting element of the color formed second or later is sometimes damaged by the preceding step. In this case, the driving voltage of the light-emitting element of the color formed second or later might be high.

In view of this, in manufacture of the display device of one embodiment of the present invention, it is preferable that an island-shaped EL layer of a light-emitting element that emits light with the shortest wavelength (e.g., the blue-light-emitting element) be formed first. For example, it is preferable that the island-shaped EL layers be formed in the order of blue, green, and red or in the order of blue, red, and green.

This enables the blue-light-emitting element to keep the favorable state of the interface between the pixel electrode and the EL layer and to be inhibited from having an increased driving voltage. In addition, the blue-light-emitting element can have a longer lifetime and higher reliability. Note that the red-light-emitting element and the green-light-emitting element have a smaller increase in driving voltage or the like than the blue-light-emitting element, resulting in a lower driving voltage and higher reliability of the whole display device.

Note that the formation order of the island-shaped EL layers is not limited to the above; for example, the island-shaped EL layers may be formed in the order of red, green, and blue.

As illustrated in FIG. 28A, the film 133Bf is not formed over the conductive layer 123. The film 133Bf can be formed only in a desired region using an area mask, for example. Employing a film formation step using an area mask and a processing step using a resist mask enables a light-emitting element to be manufactured by a relatively easy process.

The heat resistance temperature of the compounds contained in the film 133Bf is preferably higher than or equal to 100° C. and lower than or equal to 180° C., further preferably higher than or equal to 120° C. and lower than or equal to 180° C., still further preferably higher than or equal to 140° C. and lower than or equal to 180° C. Thus, the reliability of the light-emitting element can be increased. In addition, the upper limit of the temperature that can be applied in the manufacturing process of the display device can be increased. Therefore, the range of choices of the materials and the formation method of the display device can be widened, thereby improving the yield and the reliability.

Examples of the heat resistance temperature include the glass transition point, the softening point, the melting point, the thermal decomposition temperature, and the 5% weight loss temperature, and the lowest one among the temperatures is preferable.

The film 133Bf can be formed by an evaporation method, specifically a vacuum evaporation method, for example. The film 133Bf may be formed by a transfer method, a printing method, an inkjet method, a coating method, or the like.

Next, a sacrificial layer 118B is formed over the film 133Bf and the conductive layer 123 (FIG. 28A). A resist mask is formed over a film to be the sacrificial layer 118B by a photolithography process, and then the film is processed, whereby the sacrificial layer 118B can be formed.

Providing the sacrificial layer 118B over the film 133Bf can reduce damage to the film 133Bf in the manufacturing process of the display device, resulting in an increase in reliability of the light-emitting element.

The sacrificial layer 118B is preferably provided to cover the end portions of the pixel electrodes 111R, 111G, and 111B. Accordingly, an end portion of the layer 133B formed in a later step is positioned outward from the end portion of the pixel electrode 111B. The entire top surface of the pixel electrode 111B can be used as a light-emitting region, so that the aperture ratio of the pixel can be increased. The end portion of the layer 133B might be damaged in a step after the formation of the layer 133B, and thus is preferably positioned outward from the end portion of the pixel electrode 111B, i.e., not used as the light-emitting region. This can suppress a variation in the characteristics of the light-emitting elements and can improve reliability.

When the layer 133B covers the top surface and a side surface of the pixel electrode 111B, the steps after the formation of the layer 133B can be performed without exposing the pixel electrode 111B. When the end portion of the pixel electrode 111B is exposed, corrosion might occur in the etching step or the like. When corrosion of the pixel electrode 111B is inhibited, the yield and characteristics of the light-emitting element can be improved.

The sacrificial layer 118B is preferably provided also at a position overlapping with the conductive layer 123. This can inhibit the conductive layer 123 from being damaged during the manufacturing process of the display device.

As the sacrificial layer 118B, a film that is highly resistant to the process conditions for the film 133Bf, specifically, a film having high etching selectivity with respect to the film 133Bf is used.

The sacrificial layer 118B is formed at a temperature lower than the heat resistance temperature of each compound included in the film 133Bf. The typical substrate temperature in the formation of the sacrificial layer 118B is lower than or equal to 200° C., preferably lower than or equal to 150° C., further preferably lower than or equal to 120° C., still further preferably lower than or equal to 100° C., yet still further preferably lower than or equal to 80° C.

The heat resistance temperature of the compound included in the film 133Bf is preferably high, in which case the film formation temperature of the sacrificial layer 118B can be high. For example, the substrate temperature in formation of the sacrificial layer 118B can be higher than or equal to 100° C., higher than or equal to 120° C., or higher than or equal to 140° C. An inorganic insulating film formed at a higher temperature can be denser and have a better barrier property. Therefore, forming the sacrificial layer at such a temperature can further reduce damage to the film 133Bf and improve the reliability of the light-emitting element.

Note that the same can be applied to the film formation temperature of another layer formed over the film 133Bf (e.g., an insulating film 125f).

The sacrificial layer 118B can be formed by a sputtering method, an ALD method (including a thermal ALD method and a PEALD method), a CVD method, or a vacuum evaporation method, for example. Alternatively, the above-described wet film formation method may be used for the formation.

The sacrificial layer 118B (or a layer that is in contact with the film 133Bf in the case where the sacrificial layer 118B has a stacked-layer structure) is preferably formed by a formation method that causes less damage to the film 133Bf. For example, the sacrificial layer 118B is preferably formed by an ALD method or a vacuum evaporation method rather than a sputtering method.

The sacrificial layer 118B can be processed by a wet etching method or a dry etching method. The sacrificial layer 118B is preferably processed by anisotropic etching.

In the case of employing a wet etching method, damage to the film 133Bf in processing of the sacrificial layer 118B can be reduced as compared to the case of employing a dry etching method. In the case of employing a wet etching method, it is preferable to use a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of these acids, for example. In the case of employing a wet etching method, a mixed acid chemical solution containing water, phosphoric acid, diluted hydrofluoric acid, and nitric acid may be used. A chemical solution used for the wet etching treatment may be alkaline or acid.

As the sacrificial layer 118B, one or more kinds of a metal film, an alloy film, a metal oxide film, a semiconductor film, an inorganic insulating film, and an organic insulating film can be used, for example.

For the sacrificial layer 118B, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, or tantalum or an alloy material containing the metal material can be used, for example.

For example, a semiconductor material such as silicon or germanium can be used as a material with excellent compatibility with the semiconductor manufacturing process. Alternatively, an oxide or a nitride of the semiconductor material can be used. Alternatively, a non-metallic material such as carbon or a compound thereof can be used. Alternatively, a metal such as titanium, tantalum, tungsten, chromium, or aluminum, or an alloy containing one or more of them can be given. Alternatively, an oxide containing the above-described metal, such as titanium oxide or chromium oxide, or a nitride such as titanium nitride, chromium nitride, or tantalum nitride can be used.

As the sacrificial layer 118B, any of a variety of inorganic insulating films that can be used as the protective layer 131 can be used. In particular, an oxide insulating film is preferable because its adhesion to the film 133Bf is higher than that of a nitride insulating film. For example, an inorganic insulating material such as aluminum oxide, hafnium oxide, or silicon oxide can be used for the sacrificial layer 118B. As the sacrificial layer 118B, an aluminum oxide film can be formed by an ALD method, for example. An ALD method is preferably used, in which case damage to a base (in particular, the film 133Bf) can be reduced.

For example, a stacked-layer structure of an inorganic insulating film (e.g., an aluminum oxide film) formed by an ALD method and an inorganic film (e.g., an In—Ga—Zn oxide film, a silicon film, or a tungsten film) formed by a sputtering method can be employed for the sacrificial layer 118B.

Note that the same inorganic insulating film can be used for both the sacrificial layer 118B and the insulating layer 125 that is to be formed later. For example, an aluminum oxide film formed by an ALD method can be used as both the sacrificial layer 118B and the insulating layer 125. Here, for the sacrificial layer 118B and the insulating layer 125, the same film formation condition may be used or different film formation conditions may be used. For example, when the sacrificial layer 118B is formed under conditions similar to those of the insulating layer 125, the sacrificial layer 118B can be an insulating layer having a high barrier property against at least one of water and oxygen. Meanwhile, the sacrificial layer 118B is a layer a large part or the whole of which is to be removed in a later step, and thus is preferably easy to process. Therefore, the sacrificial layer 118B is preferably formed with a substrate temperature lower than that for formation of the insulating layer 125.

An organic material may be used for the sacrificial layer 118B. For example, as the organic material, a material that can be dissolved in a solvent chemically stable with respect to at least the uppermost film of the film 133Bf may be used. Specifically, a material that is dissolved in water or alcohol can be suitably used. In forming a film of such a material, it is preferable to apply the material dissolved in a solvent such as water or alcohol by a wet process and then perform heat treatment for evaporating the solvent. At this time, the heat treatment is preferably performed under a reduced-pressure atmosphere, in which case the solvent can be removed at a low temperature in a short time and thermal damage to the film 133Bf can be accordingly reduced.

The sacrificial layer 118B may be formed using an organic resin such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, an alcohol-soluble polyamide resin, or a fluororesin like perfluoropolymer.

For example, a stacked-layer structure of an organic film (e.g., a PVA film) formed by an evaporation method or the above wet film formation method and an inorganic film (e.g., a silicon nitride film) formed by a sputtering method can be employed for the sacrificial layer 118B.

Note that in the display device of one embodiment of the present invention, part of the sacrificial film remains as the sacrificial layer in some cases.

Then, the film 133Bf is processed using the sacrificial layer 118B as a hard mask, so that the layer 133B is formed (FIG. 28B).

Accordingly, as illustrated in FIG. 28B, the stacked-layer structure of the layer 133B and the sacrificial layer 118B remains over the pixel electrode 111B. In addition, the pixel electrode 111R and the pixel electrode 111G are exposed. In a region corresponding to the connection portion 140, the sacrificial layer 118B remains over the conductive layer 123.

The film 133Bf is preferably processed by anisotropic etching. Anisotropic dry etching is particularly preferable. Alternatively, wet etching may be employed.

After that, steps similar to the formation step of the film 133Bf, the formation step of the sacrificial layer 118B, and the formation step of the layer 133B are repeated twice under the condition where at least light-emitting materials are changed, whereby a stacked-layer structure of the layer 133R and a sacrificial layer 118R is formed over the pixel electrode 111R and a stacked-layer structure of the layer 133G and a sacrificial layer 118G is formed over the pixel electrode 111G (FIG. 28C). Specifically, the layer 133R and the layer 133G are formed to include a light-emitting layer that emits red light and a light-emitting layer that emits green light, respectively. The sacrificial layers 118R and 118G can be formed using a material that can be used for the sacrificial layer 118B, and the sacrificial layers 118R and 118G may be formed using the same material or different materials.

Note that the side surfaces of the layer 133B, the layer 133G, and the layer 133R are preferably perpendicular or substantially perpendicular to their formation surfaces. For example, the angle formed by the formation surfaces and these side surfaces is preferably greater than or equal to 60° and less than or equal to 90°.

As described above, the distance between two adjacent layers among the layer 133B, the layer 133G, and the layer 133R formed by a photolithography method can be shortened to less than or equal to 8 μm, less than or equal to 5 μm, less than or equal to 3 μm, less than or equal to 2 μm, or less than or equal to 1 μm. Here, the distance can be determined by, for example, the distance between opposite end portions of two adjacent layers among the layer 133B, the layer 133G, and the layer 133R. When the distance between the island-shaped EL layers is shortened in this manner, a high-definition display device with a high aperture ratio can be provided. Next, the insulating film 125f to be the insulating layer 125 later is formed to cover the pixel electrodes, the layer 133B, the layer 133G, the layer 133R, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R, and then the insulating layer 127 is formed over the insulating film 125f (FIG. 28D).

As the insulating film 125f, an insulating film is preferably formed to have a thickness greater than or equal to 3 nm, greater than or equal to 5 nm, or greater than or equal to 10 nm and less than or equal to 200 nm, less than or equal to 150 nm, less than or equal to 100 nm, or less than or equal to 50 nm.

The insulating film 125f is preferably formed by an ALD method, for example. An ALD method is preferably used, in which case damage during film formation is reduced and a film with good coverage can be formed. As the insulating film 125f, an aluminum oxide film is preferably formed by an ALD method, for example.

Alternatively, the insulating film 125f may be formed by a sputtering method, a CVD method, or a PECVD method that provides a higher film formation rate than an ALD method. In this case, a highly reliable display device can be manufactured with high productivity.

For example, an insulating film to be the insulating layer 127 is preferably formed by the above-described wet film formation method (e.g., spin coating) using a photosensitive resin composite containing an acrylic resin. After the formation, heat treatment (also referred to as pre-baking) is preferably performed to eliminate a solvent contained in the insulating film. Next, part of the insulating film is exposed to light by irradiation with visible light or ultraviolet rays. Next, the region of the insulating film exposed to light is removed by development. Then, heat treatment (also referred to as post-baking) is performed. Accordingly, the insulating layer 127 illustrated in FIG. 28D can be formed. Note that the shape of the insulating layer 127 is not limited to the shape illustrated in FIG. 28D. For example, the top surface of the insulating layer 127 can include one or more of a convex surface, a concave surface, and a flat surface. The insulating layer 127 may cover the side surface of an end portion of at least one of the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R.

Next, as illustrated in FIG. 28E, etching treatment is performed using the insulating layer 127 as a mask to remove part of the insulating film 125f and part of the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R. Consequently, openings are formed in the sacrificial layers 118B, 118G, and 118R, and the top surfaces of the layer 133B, the layer 133G, the layer 133R, and the conductive layer 123 are exposed. Note that part of the sacrificial layers 118B, 118G, and 118R may remain in positions overlapping with the insulating layer 127 and the insulating layer 125 (see a sacrificial layer 119B, a sacrificial layer 119G, and a sacrificial layer 119R).

The etching treatment can be performed by dry etching or wet etching. Note that the insulating film 125f is preferably formed using a material similar to that for the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R, in which case etching treatment can be performed collectively.

As described above, providing the insulating layer 127, the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R can inhibit the common layer 114 and the common electrode 115 between the light-emitting elements from having connection defects due to a disconnected portion and an increase in electric resistance due to a locally thinned portion. Thus, the display device of one embodiment of the present invention can have improved display quality.

Next, the common layer 114 and the common electrode 115 are formed in this order over the insulating layer 127, the layer 133B, the layer 133G, and the layer 133R (FIG. 28F).

The common layer 114 can be formed by an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

The common electrode 115 can be formed by a sputtering method or a vacuum evaporation method, for example. Alternatively, a film formed by an evaporation method and a film formed by a sputtering method may be stacked.

As described above, in the method for manufacturing the display device of one embodiment of the present invention, the island-shaped layer 133B, the island-shaped layer 133G, and the island-shaped layer 133R are formed not by using a fine metal mask but by forming a film on the entire surface and processing the film; thus, the island-shaped layers can be formed to have a uniform thickness. Consequently, a high-definition display device or a display device with a high aperture ratio can be obtained. Furthermore, even when the definition or the aperture ratio is high and the distance between the subpixels is extremely short, the layer 133R, the layer 133G, and the layer 133B can be inhibited from being in contact with each other in the adjacent subpixels. As a result, generation of a leakage current between the subpixels can be inhibited. This can prevent unintended light emission due to crosstalk, so that a display device with extremely high contrast can be obtained.

The insulating layer 127 having a tapered end portion and being provided between adjacent island-shaped EL layers can inhibit formation of step disconnection and prevent formation of a locally thinned portion to be formed in the common electrode 115 at the time of forming the common electrode 115. Thus, a connection defect due to a disconnection portion and an increase in electric resistance due to a locally thinned portion can be inhibited from occurring in the common layer 114 and the common electrode 115. Hence, the display device of one embodiment of the present invention achieves both high definition and high display quality.

In this embodiment, electronic devices of embodiments of the present invention will be described with reference to FIG. 29 to FIG. 31.

Electronic devices in this embodiment are each provided with the display device of one embodiment of the present invention in a display portion. The display device of one embodiment of the present invention can be easily increased in definition and resolution. Thus, the display device of one embodiment of the present invention can be used for display portions of a variety of electronic devices.

Examples of the electronic devices include a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, and an audio reproducing device, in addition to electronic devices with a relatively large screen, such as a television device, desktop and notebook personal computers, a monitor of a computer and the like, digital signage, and a large game machine such as a pachinko machine.

In particular, the display device of one embodiment of the present invention can have a high definition, and thus can be suitably used for an electronic device having a relatively small display portion. Examples of such an electronic device include watch-type and bracelet-type information terminal devices (wearable devices) and wearable devices capable of being worn on a head, such as a VR device like a head-mounted display, a glasses-type AR device, and an MR device.

The resolution of the display device of one embodiment of the present invention is preferably as high as HD (number of pixels: 1280×720), FHD (number of pixels: 1920×1080), WQHD (number of pixels: 2560×1440), WQXGA (number of pixels: 2560×1600), 4K (number of pixels: 3840×2160), or 8K (number of pixels: 7680×4320). In particular, a resolution of 4K, 8K, or higher is preferable. The pixel density (definition) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, further preferably 300 ppi or higher, still further preferably 500 ppi or higher, yet still further preferably 1000 ppi or higher, yet still further preferably 2000 ppi or higher, yet still further preferably 3000 ppi or higher, yet still further preferably 5000 ppi or higher, yet still further preferably 7000 ppi or higher. The use of the display device having one or both of such high resolution and high definition can further increase realistic sensation, sense of depth, and the like. There is no particular limitation on the screen ratio (aspect ratio) of the display device of one embodiment of the present invention. For example, the display device is compatible with a variety of screen ratios such as 1:1 (a square), 4:3, 16:9, and 16:10.

Examples of head-mounted wearable devices will be described with reference to FIG. 29A to FIG. 29D. The wearable devices have at least one of a function of displaying AR contents, a function of displaying VR contents, a function of displaying SR contents, and a function of displaying MR contents. The electronic device having a function of displaying contents of at least one of AR, VR, SR, MR, and the like enables the user to feel a higher level of immersion.

An electronic device 700A illustrated in FIG. 29A and an electronic device 700B illustrated in FIG. 29B each include a pair of display panels 751, a pair of housings 721, a communication portion (not illustrated), a pair of wearing portions 723, a control portion (not illustrated), an image capturing portion (not illustrated), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

The display device of one embodiment of the present invention can be used for the display panels 751. Thus, the electronic devices are capable of performing ultrahigh-definition display.

The electronic device 700A and the electronic device 700B can each project images displayed on the display panels 751 onto display regions 756 of the optical members 753. Since the optical members 753 have a light-transmitting property, the user can see images displayed on the display regions, which are superimposed on transmission images seen through the optical members 753. Accordingly, the electronic device 700A and the electronic device 700B are electronic devices capable of AR display.

In the electronic device 700A and the electronic device 700B, a camera capable of capturing images of the front side may be provided as the image capturing portion. Furthermore, when the electronic device 700A and the electronic device 700B are provided with an acceleration sensor such as a gyroscope sensor, the orientation of the user's head can be sensed and an image corresponding to the orientation can be displayed on the display regions 756.

The communication portion includes a wireless communication device, and a video signal and the like can be supplied by the wireless communication device. Instead of or in addition to the wireless communication device, a connector that can be connected to a cable for supplying a video signal and a power supply potential may be provided.

The electronic device 700A and the electronic device 700B are each provided with a battery so that they can be charged wirelessly and/or by wire.

A touch sensor module may be provided in the housing 721. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. Detecting a tap operation, a slide operation, or the like by the user with the touch sensor module enables various types of processing. For example, a video can be paused or restarted by a tap operation, and can be fast-forwarded or fast-reversed by a slide operation. When the touch sensor module is provided in each of the two housings 721, the range of the operation can be increased.

Various touch sensors can be applied to the touch sensor module. For example, any of touch sensors of various types such as a capacitive type, a resistive type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, a capacitive sensor or an optical sensor is preferably used for the touch sensor module.

In the case of using an optical touch sensor, a photoelectric conversion element can be used as a light-receiving element. One or both of an inorganic semiconductor and an organic semiconductor can be used for an active layer of the photoelectric conversion element.

An electronic device 800A illustrated in FIG. 29C and an electronic device 800B illustrated in FIG. 29D each include a pair of display portions 820, a housing 821, a communication portion 822, a pair of wearing portions 823, a control portion 824, a pair of image capturing portions 825, and a pair of lenses 832.

The display device of one embodiment of the present invention can be used in the display portions 820. Thus, the electronic devices are capable of performing ultrahigh-definition display. This enables a user to feel a high sense of immersion.

The display portions 820 are positioned inside the housing 821 so as to be seen through the lenses 832. When the pair of display portions 820 display different images, three-dimensional display using parallax can be performed.

The electronic device 800A and the electronic device 800B can be regarded as electronic devices for VR. The user who wears the electronic device 800A or the electronic device 800B can see images displayed on the display portions 820 through the lenses 832.

The electronic device 800A and the electronic device 800B preferably include a mechanism for adjusting the lateral positions of the lenses 832 and the display portions 820 so that the lenses 832 and the display portions 820 are positioned optimally in accordance with the positions of the user's eyes. Moreover, the electronic device 800A and the electronic device 800B preferably include a mechanism for adjusting focus by changing the distance between the lenses 832 and the display portions 820.

The electronic device 800A or the electronic device 800B can be mounted on the user's head with the wearing portions 823. FIG. 29C and the like illustrate examples where the wearing portion 823 has a shape like a temple (also referred to as a joint) of glasses; however, one embodiment of the present invention is not limited thereto. The wearing portion 823 may have any shape with which the user can wear the electronic device, such as a shape of a helmet or a band.

The image capturing portion 825 has a function of obtaining information on the external environment. Data obtained by the image capturing portion 825 can be output to the display portion 820. An image sensor can be used for the image capturing portion 825. Moreover, a plurality of cameras may be provided so as to cover a plurality of fields of view, such as a telescope field of view and a wide field of view.

Although an example where the image capturing portion 825 is provided is shown here, a range sensor (hereinafter also referred to as a sensing portion) capable of measuring a distance between the user and an object just needs to be provided. In other words, the image capturing portion 825 is one embodiment of the sensing portion. As the sensing portion, an image sensor or a range image sensor such as LIDAR (Light Detection and Ranging) can be used, for example. By using images obtained by the camera and images obtained by the range image sensor, more information can be obtained and a gesture operation with higher accuracy is possible.

The electronic device 800A may include a vibration mechanism that functions as a bone-conduction earphone. For example, a structure including the vibration mechanism can be employed for any one or more of the display portions 820, the housing 821, and the wearing portions 823. Thus, without additionally requiring an audio device such as headphones, earphones, or a speaker, the user can enjoy videos and sound only by wearing the electronic device 800A.

The electronic device 800A and the electronic device 800B may each include an input terminal. To the input terminal, a cable for supplying a video signal from a video output device or the like, power for charging the battery provided in the electronic device, and the like can be connected.

The electronic device of one embodiment of the present invention may have a function of performing wireless communication with earphones 750. The earphones 750 include a communication portion (not illustrated) and have a wireless communication function. The earphones 750 can receive information (e.g., audio data) from the electronic device with the wireless communication function. For example, the electronic device 700A in FIG. 29A has a function of transmitting information to the earphones 750 with the wireless communication function. As another example, the electronic device 800A in FIG. 29C has a function of transmitting information to the earphones 750 with the wireless communication function.

The electronic device may include an earphone portion. The electronic device 700B in FIG. 29B includes earphone portions 727. For example, the earphone portion 727 can be connected to the control portion by wire. Part of a wiring that connects the earphone portion 727 and the control portion may be positioned inside the housing 721 or the wearing portion 723.

Similarly, the electronic device 800B in FIG. 29D includes earphone portions 827. For example, the earphone portion 827 can be connected to the control portion 824 by wire. Part of a wiring that connects the earphone portion 827 and the control portion 824 may be positioned inside the housing 821 or the wearing portion 823. Alternatively, the earphone portions 827 and the wearing portions 823 may include magnets. This is preferable because the earphone portions 827 can be fixed to the wearing portions 823 with magnetic force and thus can be easily housed.

The electronic device may include an audio output terminal to which earphones, headphones, or the like can be connected. The electronic device may include one or both of an audio input terminal and an audio input mechanism. As the audio input mechanism, a sound collecting device such as a microphone can be used, for example. The electronic device may have a function of what is called a headset by including the audio input mechanism.

As described above, both the glasses-type device (e.g., the electronic device 700A and the electronic device 700B) and the goggles-type device (e.g., the electronic device 800A and the electronic device 800B) are preferable as the electronic device of one embodiment of the present invention.

The electronic device of one embodiment of the present invention can transmit information to earphones by wire or wirelessly.

An electronic device 6500 illustrated in FIG. 30A is a portable information terminal that can be used as a smartphone.

The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, buttons 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

The display device of one embodiment of the present invention can be used in the display portion 6502.

FIG. 30B is a schematic cross-sectional view including an end portion of the housing 6501 on the microphone 6506 side.

A protection member 6510 having a light-transmitting property is provided on the display surface side of the housing 6501. A display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, and the like are provided in a space surrounded by the housing 6501 and the protection member 6510.

The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protection member 6510 with an adhesive layer (not illustrated).

Part of the display panel 6511 is folded back in a region outside the display portion 6502, and an FPC 6515 is connected to the part that is folded back. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on the printed circuit board 6517.

A flexible display of one embodiment of the present invention can be used as the display panel 6511. In that case, an extremely lightweight electronic device can be obtained. Since the display panel 6511 is extremely thin, the battery 6518 with high capacity can be mounted without an increase in the thickness of the electronic device. Moreover, part of the display panel 6511 is folded back so that a connection portion with the FPC 6515 is provided on the back side of the pixel portion, whereby an electronic device with a narrow bezel can be obtained.

FIG. 30C illustrates an example of a television device. In a television device 7100, a display portion 7000 is incorporated in a housing 7101. Here, the housing 7101 is supported by a stand 7103.

The display device of one embodiment of the present invention can be used for the display portion 7000.

Operation of the television device 7100 illustrated in FIG. 30C can be performed with an operation switch provided in the housing 7101 and a separate remote controller 7111. Alternatively, the display portion 7000 may include a touch sensor, and the television device 7100 may be operated by touch on the display portion 7000 with a finger or the like. The remote controller 7111 may be provided with a display portion for displaying information output from the remote controller 7111. With operation keys or a touch panel provided in the remote controller 7111, channels and volume can be controlled and videos displayed on the display portion 7000 can be controlled.

Note that the television device 7100 includes a receiver, a modem, and the like. A general television broadcast can be received with the receiver. When the television device is connected to a communication network by wire or wirelessly via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver or between receivers, for example) data communication can be performed.

FIG. 30D illustrates an example of a notebook personal computer. The notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. The display portion 7000 is incorporated in the housing 7211.

The display device of one embodiment of the present invention can be used in the display portion 7000.

Digital signage 7300 illustrated in FIG. 30E includes a housing 7301, the display portion 7000, a speaker 7303, and the like. The digital signage 7300 can also include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, a variety of sensors, a microphone, and the like.

FIG. 30F illustrates digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 includes the display portion 7000 provided along a curved surface of the pillar 7401.

The display device of one embodiment of the present invention can be used in the display portion 7000 illustrated in each of FIG. 30E and FIG. 30F.

A larger area of the display portion 7000 can increase the amount of information that can be provided at a time. The larger display portion 7000 attracts more attention, so that the effectiveness of the advertisement can be increased, for example.

A touch panel is preferably used in the display portion 7000, in which case intuitive operation by a user is possible in addition to display of an image or a moving image on the display portion 7000. Moreover, for an application for providing information such as route information or traffic information, usability can be enhanced by intuitive operation.

As illustrated in FIG. 30E and FIG. 30F, it is preferable that the digital signage 7300 or the digital signage 7400 can work with an information terminal 7311 or an information terminal 7411, such as a smartphone that a user has, through wireless communication. For example, information of an advertisement displayed on the display portion 7000 can be displayed on a screen of the information terminal 7311 or the information terminal 7411. By operation of the information terminal 7311 or the information terminal 7411, display on the display portion 7000 can be switched.

It is possible to make the digital signage 7300 or the digital signage 7400 execute a game with use of the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). Thus, an unspecified number of users can join in and enjoy the game concurrently.

In FIG. 31A to FIG. 31G, the display device of one embodiment of the present invention can be used in the display portion 9001.

The electronic devices illustrated in FIG. 31A to FIG. 31G have a variety of functions. For example, the electronic devices can have a function of displaying a variety of information (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of controlling processing with the use of a variety of software (programs), a wireless communication function, and a function of reading out and processing a program or data stored in a recording medium. Note that the functions of the electronic devices are not limited thereto, and the electronic devices can have a variety of functions. The electronic devices may include a plurality of display portions. The electronic devices may be provided with a camera or the like and have a function of capturing a still image or a moving image, a function of storing the captured image in a storage medium (an external storage medium or a storage medium incorporated in the camera), a function of displaying the captured image on the display portion, and the like.

The electronic devices illustrated in FIG. 31A to FIG. 31G will be described in detail below.

FIG. 31A is a perspective view of a portable information terminal 9101. The portable information terminal 9101 can be used as a smartphone, for example. The portable information terminal 9101 may include the speaker 9003, the connection terminal 9006, the sensor 9007, or the like. The portable information terminal 9101 can display text and image information on its plurality of surfaces. FIG. 31A illustrates an example where three icons 9050 are displayed. Furthermore, information 9051 indicated by dashed rectangles can be displayed on another surface of the display portion 9001. Examples of the information 9051 include notification of reception of an e-mail, an SNS message, or an incoming call, the title and sender of an e-mail, an SNS message, or the like, the date, the time, remaining battery, and the radio field intensity. Alternatively, the icon 9050 or the like may be displayed at the position where the information 9051 is displayed.

FIG. 31B is a perspective view of a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example in which information 9052, information 9053, and information 9054 are displayed on different surfaces is illustrated. For example, the user of the portable information terminal 9102 can check the information 9053 displayed such that it can be seen from above the portable information terminal 9102, with the portable information terminal 9102 put in a breast pocket of his/her clothes. The user can see the display without taking out the portable information terminal 9102 from the pocket and decide whether to answer the call, for example.

FIG. 31C is a perspective view of a tablet terminal 9103. The tablet terminal 9103 is capable of executing a variety of applications such as mobile phone calls, e-mailing, viewing and editing texts, music reproduction, Internet communication, and a computer game, for example. The tablet terminal 9103 includes the display portion 9001, the camera 9002, the microphone 9008, and the speaker 9003 on the front surface of the housing 9000; the operation keys 9005 as buttons for operation on the left side surface of the housing 9000; and the connection terminal 9006 on the bottom surface of the housing 9000.

FIG. 31D is a perspective view of a watch-type portable information terminal 9200. The portable information terminal 9200 can be used as a Smartwatch (registered trademark), for example. The display surface of the display portion 9001 is curved, and an image can be displayed on the curved display surface. Furthermore, for example, mutual communication between the portable information terminal 9200 and a headset capable of wireless communication can be performed, and thus hands-free calling is possible. With the connection terminal 9006, the portable information terminal 9200 can perform mutual data transmission with another information terminal and charging. Note that the charging operation may be performed by wireless power feeding.

FIG. 31E to FIG. 31G are perspective views of a foldable portable information terminal 9201. FIG. 31E is a perspective view of an opened state of the portable information terminal 9201, FIG. 31G is a perspective view of a folded state thereof, and FIG. 31F is a perspective view of a state in the middle of change from one of FIG. 31E and FIG. 31G to the other. The portable information terminal 9201 is highly portable in the folded state and is highly browsable in the opened state because of a seamless large display region. The display portion 9001 of the portable information terminal 9201 is supported by three housings 9000 joined together by hinges 9055. The display portion 9001 can be folded with a radius of curvature greater than or equal to 0.1 mm and less than or equal to 150 mm, for example.

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