Deserialized dual-loop clock radio and data recovery circuit

A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a deserialized dual-loop clock and data recovery circuit.

BACKGROUND OF THE INVENTION

Data transmission over cables and wires has enabled much of the economic and technological development over the last few decades. From early electrical telegraph lines by Samuel Morse, to copper cable lines distributing news, entertainment, and high speed internet. Today, the cutting edge of data transmission is in fiber optic communication. Optical fiber is used by many telecommunications companies to transmit telephone, internet, and television signals. Optical communication technology is also commonly used in private and corporate networks, home and commercial theater technology, as well as myriad other sectors.

Due to lower attenuation and interference, optical fiber has large advantages over existing copper wire in long-distance and high-speed applications. However, many challenges still exist in maximizing the data transfer rate over fiber optics. To receive optical data, a clock and data recovery (CDR) circuit is required to reconstruct separate clock and data signals from a single serial data signal.

Many prior art CDR circuits include logic that must run at the same frequency as the received data signal, which makes low-cost and high-speed fiber optic receivers difficult to produce. An incoming optical signal is converted to a corresponding electrical signal using a photodiode. On-off keying (OOK) or amplitude shift keying (ASK) are commonly used to encode data on a carrier wave, but other signal types are used as well.

The electrical signal is converted to binary data by sampling the electrical signal between transitions of the data signal, and the signal is also sampled at the data transitions. The data samples that occur between data transitions are in-phase (I) samples, and the data samples that occur at the transitions are quadrature (Q) samples. In-phase, or data, samples and quadrature, or edge, samples are compared to identify whether a quadrature sample occurred before or after an actual transition of the incoming data signal. The sample clock is adjusted accordingly to stay synchronized with the incoming data signal.

A half-rate phase interpolator (PI) CDR uses multiple samplers and multiple evenly spaced sampling clocks to reduce the clock frequency of CDR logic. However, prior art half-rate CDRs require an external reference clock input which can reduce jitter tolerance when the reference clock input is at an offset frequency compared to the clock signal of the received data signal. The frequency offset can be overcome by adjusting the external reference clock frequency, but then a separate reference clock is required for each CDR receiving data at a different data rate. Even if a group of CDRs is receiving data at the same rate, clock distribution and buffering will use a significant amount of power.

SUMMARY OF THE INVENTION

A need exists for a clock and data recovery (CDR) circuit that operates at a reduced clock frequency, does not require an external reference clock source, and allows for adjustment of the timing of in-phase versus quadrature sampling. Accordingly, in one embodiment, the present invention is a clock and data recovery circuit (CDR) including a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO.

In another embodiment, the present invention is a CDR comprising a clock generator. A data sampler is coupled to receive a clock signal from the clock generator. A deserializer is coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the clock generator. A second phase detector is coupled between a second output of the deserializer and a second input of the clock generator.

In another embodiment, the present invention is a CDR comprising a data sampler. A deserializer is coupled to an output of the data sampler. A first phase detector is coupled to receive a first set of data from the deserializer. A second phase detector is coupled to receive a second set of data from the deserializer.

In another embodiment, the present invention is a method of making a CDR comprising the steps of providing a data sampler, coupling a deserializer to an output of the data sampler, coupling a first phase detector to receive a first set of data from the deserializer, and coupling a second phase detector to receive a second set of data from the deserializer.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1illustrates a block diagram of a clock and data recovery (CDR) circuit10. CDR10is used in a semiconductor device to receive a serial data signal via an optical or electrical signal. The semiconductor device is a board including semiconductor packages mounted to the board, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or another type of device in various embodiments. An optical signal is received via a fiber optic cable in one embodiment. An electrical signal is received via a copper coax cable or a twisted pair in another embodiment. CDR10includes a clock generation block12which outputs one or more in-phase clock signals14, e.g., W in-phase clock signals, and one or more quadrature clock signals16, e.g., W quadrature clock signals, to data sampler block20. Data sampler block20samples input serial data22using each in-phase clock14and each quadrature clock16. Data sampler block20outputs W center data samples24, W edge samples26, and clock28to deserializer30. Deserializer30outputs K center data samples34, K edge samples36, and clock38to proportional feedback path40. Proportional feedback path40outputs a phase error signal42to clock generation block12. Deserializer30also outputs N center data samples44, M edge samples46, and clock48to integral feedback path50. Integral feedback path50outputs a frequency error signal52to clock generation block12. Clock generation block12also receives a reference clock signal58from a source external CDR10.

Input serial data22is a serial data signal with data bits being received at a baud rate. Baud rate is the rate at which information is transferred over a communication channel. For instance, a 9600 baud serial communication link is capable of transmitting 9600 bits of information every second. If input serial data22at 9600 baud changed value from a binary one to a binary zero every bit, the signal would look like a clock signal operating at 9600 hertz (Hz). In practice, input serial data22received by CDR10is generally operating in the gigahertz range or faster.

In one embodiment, CDR10is a half-rate CDR. Half-rate means that data sampler block20includes two center data samplers and two edge samplers which each operates at half the frequency that a single data sampler in a full-rate CDR would have to run at. A full-rate CDR requires a sampler operating at a frequency equivalent to the baud rate of an incoming serial signal. A half-rate CDR includes duplicate data sampling circuitry, each operating at half the baud rate frequency, which alternate to each sample every other incoming data bit. In some embodiments, CDR10is a quarter-rate CDR which uses four data sampling circuits operating in parallel, each operating at one quarter of the input serial data22baud rate and each being used to sample one out of every four data bits of input serial data22. In other embodiments, data sampler block20uses any number of data samplers, e.g., W data samplers, operating in parallel to reduce the operating frequency of each data sampler by a factor of W.

The letter W represents the number of data samplers used in parallel by data sampler block20. For a half-rate CDR10, W is equal to 2. For a quarter-rate CDR10, W is equal to 4. For a full-rate CDR10, W is equal to 1. CDR10could be a full-rate CDR, half-rate CDR, quarter-rate CDR, or W could be equal to any other number in other embodiments. For each data sampler of data sampler block20, clock generation block12creates an in-phase clock signal14and a quadrature clock signal16. Therefore, clock generation block12generates W in-phase clock signals14and W quadrature clock signals16, and each of the 2W total clock signals14-16is routed to data sampler block20. For a half-rate CDR10, W is equal to 2. Clock generation block12generates two in-phase clock signals14, referred to hereinafter as clocks14[0] and14[1], and two quadrature clock signals16, referred to hereinafter as clocks16[0] and16[1].

A clock signal is a signal that oscillates between two values, referred to as a binary one value and a binary zero value, at a generally static frequency and generally with an approximately fifty percent duty cycle. The binary one is usually manifested as a positive voltage on the clock signal line, and the binary zero is usually a voltage at approximately ground potential. A clock period includes a rising edge or transition, and a falling transition. When the clock signal transitions from a binary zero value to a binary one value, the transition is known as a rising transition. When the clock signal transitions from a binary one value to a binary zero value, the transition is known as a falling transition. Sequential logic circuits, e.g., flip-flops, generally operate on the rising transition of each clock cycle, which is assumed to be the case hereinafter. However, the disclosed circuits operate on the falling edge, or on both the falling and rising edges, in other embodiments.

Each of the W in-phase clocks14includes a rising transition of the in-phase clock occurring near a center of a serial data bit of input serial data22when CDR10is locked onto the data rate of the input serial data. When W is equal to two, each of the two individual in-phase clocks14includes a rising edge near the middle of alternating data bits of input serial data22. A first in-phase clock14[0] is used by data sampler block20to sample a first data bit of input serial data22, and then a second in-phase clock14[1] is used to sample a second data bit of the input serial data. Next, clock signal14[0] is used again to sample a third data bit, clock signal14[1] is used to sample a fourth data bit, and so on. Each individual in-phase clock14operates at half the baud rate of input serial data22, and each in-phase clock is used to sample every other bit received. The in-phase clocks14alternate sampling phases so that each bit of input serial data22is sampled using one of the in-phase clocks. With W equal to four, four in-phase clocks14are provided, each at one quarter of the baud rate of input serial data22, and each in-phase clock triggering an individual sampler of data sampler block20repeatedly in order, i.e., every fourth bit of input serial data22.

Each of the quadrature clocks16nominally includes a rising transition of the quadrature clock occurring on an edge between two adjacent data bits of input serial data22when CDR10is locked into the frequency of the input serial data. When W is equal to two, each of the two individual quadrature clocks16includes a rising transition near alternating edges of input serial data22. A first quadrature clock16[0] is used by data sampler20to sample a first edge of input serial data22after in-phase clock14[0] samples the center of the previous data bit. A second quadrature clock16[1] is used by data sampler20to sample a second edge of input serial data22after in-phase clock14[1] samples the center of the previous data bit. Clock signal16[0] is then used to sample a third edge of input serial data22, clock signal16[1] is used to sample a fourth edge of the input serial data, and so on. Quadrature clocks16are each used by data sampler block20to sample every second data edge, and the quadrature clocks are out of phase such that each quadrature clock16triggers a sample on the edges of input serial data22that the other quadrature clock misses. With W equal to four, four quadrature clocks16are provided, with each quadrature clock running at one quarter of the input serial data22baud rate. Each of the quadrature clocks16is used to sample one out of every four edges of input serial data22. Quadrature clocks16include phases designed so that each input serial data edge is sampled using one of the four quadrature clocks, which alternate in order.

Together, in-phase clocks14include a single rising transition of one of the in-phase clocks occurring approximately at the center of each data bit of input serial data22, and quadrature clocks16include a single rising transition of one of the quadrature clocks occurring approximately at the edge between every two adjacent data bits. Data sampler block20samples input serial data22using each in-phase clock14and each quadrature clock16. Data sampler block20provides deserializer30with W in-phase, or center, samples24of input serial data22taken using the W in-phase clocks14. Data sampler block20also provides deserializer30with W quadrature, or edge, samples26of input serial data22taken using the W quadrature clocks16.

Data sampler block20provides a clock signal28which operates at the baud rate of input serial data22divided by W. For W equal to two, clock28operates at half the baud rate of input serial data22. For W equal to four, clock28operates at one quarter of the baud rate of input serial data22. Clock28runs at approximately the same frequency as each of the individual in-phase clocks14and quadrature clocks16, and triggers deserializer30to act on the samples24and26. When deserializer30receives a positive transition of clock signal28, the transition indicates to the deserializer that a sample of input serial data22has been taken with each of the in-phase clocks14and quadrature clocks16. Deserializer30caches, or otherwise acts on, the W center data samples24and the W edge samples26at each positive transition of clock signal28before data sampler20resamples input serial data22using the next positive transition of each in-phase clock14and quadrature clock16.

Proportional feedback path40receives a data bus of K center data samples34and K edge samples36from deserializer30. Deserializer30generates a clock38which has a frequency equivalent to the baud rate of input serial data22divided by K. After deserializer30populates data buses34-36with K center data samples and K edge samples by concatenating multiple W center data samples24and W edge samples26in parallel, the deserializer generates a rising or positive transition of clock38to trigger proportional feedback path40to act on the data samples34-36.

The number K represents the number of samples transferred from deserializer30to proportional feedback path40at one time. K can be the same number as W, or K can be a larger number than W. When K is equivalent to W, deserializer30simply forwards data bus24to proportional feedback path40as center data samples34, data bus26as edge samples36, and clock28as clock38. In cases where K is larger than W, deserializer30caches center data samples24and edge samples26upon a positive transition of clock28. Deserializer30then generates a transition of clock signal38when the cached samples add up to K. In some embodiments, K is a smaller number than W. K is a smaller number than W in embodiments where W is large and not all of the W samples24and W samples26are required or desired to be used for proportional feedback path40to generate phase error signal42. With K smaller than W, clock38operates at the same rate as clock28, and deserializer only forwards a subset of samples24and26to proportional feedback path40.

As an example, with W equal to two and K equal to four, deserializer30stores a first set of samples24-26in a cache on a first positive transition of clock signal28. Upon a second positive transition of clock signal28, deserializer30generates a positive transition of clock signal38and forwards the cached first set of samples concatenated with a second set of samples24-26as center data samples34and edge samples36to proportional feedback path40. The positive edge of clock38causes proportional feedback path40to calculate phase error signal42before a third positive transition of clock28, when deserializer30caches a third set of samples24-26which overwrites the cached first set of samples. A fourth positive transition of clock28results in deserializer30generating a second positive transition of clock signal38and proportional feedback path40acts on third and fourth samples24-26received via data buses34-36.

Proportional feedback path40generates phase error signal42which signifies whether the most recent samples of data sampler block20occurred early or late relative to the signal of input serial data22. Edge samples26should ideally be taken at exactly the edge between two data bits of input serial data22. Proportional feedback path40analyzes the K center data samples34and K edge samples36to determine whether the edge samples are occurring early or late. If a value of an edge sample is different than the value of an immediately previous center data sample, the edge sample occurred after the actual edge of input serial data22, and was thus late. If a value of a center data sample is different than the value of an immediately previous edge sample, that previous edge sample occurred before a corresponding edge of input serial data22, and thus was early.

In one embodiment, phase error signal42is a two-bit bus, with one bit an early indicator and one bit a late indicator. For every positive transition of clock signal38, proportional feedback path40evaluates the K center data samples34and K edge samples36and generates a pulse on either the down bit or up bit of phase error signal42. Proportional feedback path40generates a pulse of the down bit of phase error signal42if the K center data samples34and K edge samples36as a whole indicate clocks14-16are early relative to input serial data22. Proportional feedback path40generates a pulse of the up bit of phase error signal42if the K center data samples34and K edge samples36as a whole indicate clocks14-16are late relative to input serial data22. Proportional feedback path40may not generate any pulse of phase error signal42if no transitions of input serial data22between binary values occurred during the time period when samples34-36were taken by data sampler block20.

Deserializer30caches the W center data samples24and W edge samples26into N parallel center data samples44and M parallel edge samples46which are routed to integral feedback path50. Deserializer30also generates a clock signal48which is equivalent to the baud rate of input serial data22divided by N. Deserializer30caches the W center data samples24and W edge samples26at each rising transition of clock signal28to form the N center data samples44and M edge samples46, similar to how samples34-36are formed. After enough samples24-26are received by deserializer30to form samples44-46, the deserializer30generates a rising transition of clock signal48to trigger integral feedback path50to act on the samples44-46.

In addition, the N data samples44and clock signal48are routed as outputs of the circuit module of CDR10. An engineer designing a board or chip utilizing CDR10routes center data samples44to a FIFO, cache, or other memory element, and clock signal48is routed to control the storage of data samples44into the memory element. Data samples44represent the actual data content received at input serial data22. The memory element external to CDR10stores data samples44at each positive transition of clock48for further use by a digital processor, ASIC, FPGA, or other circuit module that needs to receive data via an optical signal.

Integral feedback path50generates frequency error signal52using a digital accumulator to track the early and late samples of input serial data22over time. Frequency error signal52is a digital integral value that rises and falls as clocks14and16drift relative to input serial data22. In some embodiments, frequency error signal52is output as a reflected binary code, or Gray code. A Gray code is a binary numeral system where two successive values differ by only one bit. If the N center data samples44and M edge samples46as a whole indicate that the edges of clocks14-16are early relative to input serial data22, the value of the accumulator in integral feedback path50is reduced. If the N center data samples44and M edge samples46as a whole indicate that the edges of clocks14-16are late relative to input serial data22, the value of the accumulator in integral feedback path50is increased. In some embodiments, late samples reduce the accumulator value while early samples increase the accumulator value. The bit width of the accumulator in integral feedback path, and thus the bit width of frequency error signal52, is different in various embodiments. The bit width of frequency error signal52may be set based on a desired resolution, or step size, of integral feedback path50.

Various methods are used to determine the number that is added to or subtracted from the accumulator in integral feedback path50. Integral feedback path50subtracts the number of early edge samples from the number of late edge samples and adds the result to the accumulator. If the samples indicate an early sampling, the result is negative and the accumulator value is reduced. In one embodiment, the result of the comparison between early samples and late samples is reduced by a factor of 1, 2, 4, 8, 16, or any other number. Reducing the result by a factor which is a power of two provides the simplest implementation, but the result can be reduced by a factor that is not a power of two. In other embodiments, a majority vote is used among the samples. If more samples indicate that clocks14-16are early, the accumulator is reduced by a fixed amount. If more samples indicate that clocks14-16are late, the accumulator is increased by a fixed amount.

Clock generation block12receives phase error signal42, a two-bit signal comprising a down bit and an up bit, and frequency error signal52, a multiple bit signal representing a binary integer value. Clock generation block12modifies the phasing or frequency of in-phase clocks14and quadrature clocks16as necessary to improve the synchronization between clocks14-16and input serial data22.

Reference clock58is routed to clock generation block12. Reference clock58is at a known integer ratio of the input serial data22baud rate, i.e., a frequency near an integer sub-harmonic of the expected baud rate of input serial data22. Clock generation block12uses reference clock58during calibration to quickly sync clock signals14-16as a whole to near the baud rate of input serial data22. After calibration is complete, and during data transfer, reference clock58is not required or used. Clock generation block12syncs to input serial data22without reference clock58. Reference clock58is optional, and clock generation block12syncs to input serial data22without the reference clock. However, reference clock58allows quicker frequency lock.

CDR10reduces the cost of receiving high frequency serial data because proportional feedback path40and integral feedback path50operate on parallelized data. Deserializer30allows the circuitry of feedback paths40and50to operate at significantly reduced clock frequencies relative to input serial data22. In particular, operating the adders and accumulator of integral feedback path50at a clock rate reduced by a factor of N eases design constraints of the circuits. The lower operating frequency of proportional feedback path40and integral feedback path50allows CDR10to be fabricated using methods that reduce costs. Moreover, clock generation block12is able to shift in-phase clocks14relative to quadrature clocks16. Shifting in-phase clocks14allows data sampler20to sample input serial data22at the highest margin location between two edges of the input serial data while still sampling with the quadrature clock at or near the edges of the input serial data.

FIG. 2aillustrates detail of clock generation block12. Frequency error signal52is input to oscillator frequency control80from integral feedback path50. Oscillator frequency control80outputs a frequency control signal82to digitally controlled oscillator (DCO)84. DCO84receives phase error signal42from proportional feedback path40. DCO84returns a calibration clock86to oscillator frequency control80, and also generates 2W clock signals88to optional clock divider91. Clock divider91reduces the frequency of clock signals88as required or desired in some embodiments, and outputs 2W clock signals92to phase interpolator block94. Phase interpolator block94outputs W in-phase clocks14and W quadrature clocks16. Calibration and adaption block96outputs a control signal98used to shift the quadrature clocks16relative to the in-phase clocks14using various methods to be explained below.

Oscillator frequency control80modifies the frequency of clock signals88using frequency control signal82. Control signal82is a data bus with multiple binary digits that each control a switchable capacitive element within DCO84to tune an oscillator within the DCO. In one embodiment, control signal82is simply a binary numeral that is used by DCO84to tune itself through any number of varactors and switched capacitors. In other embodiments, a voltage controlled oscillator (VCO) is used instead of DCO84, and control signal82is an analog voltage that controls the frequency of clock signals88. One embodiment of DCO84uses a ring-oscillator core. Another embodiment of DCO84uses an inductor-capacitor (LC) based VCO.

During calibration, oscillator frequency control80compares the frequency of reference clock58to calibration clock86from DCO84to generate control signal82. Clock generation block12synchronizes the frequency of clock signals14-16to reference clock58during calibration, then uses frequency error signal52to synchronize clocks14-16with input serial data22during normal operation. After calibration, reference clock signal58and calibration clock86are generally not used unless recalibration is required.

DCO84includes a single oscillator to generate 2W clock signals88. A frequency of the oscillator in DCO84is controlled by control signal82from oscillator frequency control80. Delay logic within DCO84is used to output 2W clock signals88at different phases. In other embodiments, clock signals88are output in phase, and phase interpolator block94is relied upon to introduce the entire delay between each of the in-phase clocks14and quadrature clocks16. The delay logic is further controlled based upon phase error signal42to introduce or remove delay from each clock88in unison. Clock divider91is optionally used to reduce the frequency of clock signals14-16for use with an input serial data22having a different data rate.

Phase interpolator block94accepts 2W clocks92as inputs and generates W in-phase clocks14and W quadrature clocks16as outputs. Phase interpolator block94outputs each in-phase clock signal14to be halfway between two adjacent quadrature clock signals16. Phase interpolator block94also outputs each quadrature clock signal16to be halfway between two adjacent in-phase clock signals14. In some embodiments, calibration and adaptation block96uses interpolator control signal98to shift quadrature clocks16relative to in-phase clocks14so that data sampler block20takes center data samples near the optimal time in the eye pattern of input serial data22.

In-phase clocks14and quadrature clocks16include phases that are evenly spaced throughout one period of the clocks such that one in-phase clock and one quadrature clock have rising transitions for each bit period of input serial data22. If the period of clocks14-16is considered to be 360 degrees, and W is equal to two, then the two in-phase clocks14have rising transitions at 0 degrees and 180 degrees while the two quadrature clocks have rising edges at 90 degrees and 270 degrees. With W equal to four, one individual in-phase clock14has a rising transition at each of 0, 90, 180, and 270 degrees. The individual quadrature clocks have rising transitions at 45, 135, 225, and 315 degrees with W equal to four. Calibration and adaptation block96causes a shift in the in-phase clocks14relative to quadrature clocks16using signal98. For W equal to two, rising transitions of in-phase clocks14are shifted away from occurring at 0 and 180 degrees in cases where input serial data22has a higher margin earlier or later in the eye pattern of the serial data. Quadrature clocks16remain at approximately 90 and 270 degrees because the cycle is defined relative to edges of input serial data22, and quadrature clocks16should always occur near the edges between subsequent data bits of the input serial data.

FIG. 2billustrates one embodiment of phase interpolator block94when W is equal to two. W clock signals92from DCO84are routed to mini phase interpolator100and mini phase interpolator102. Mini phase interpolators are used for interpolators100and102which only include an adjustment range of +/−90 degrees, but include a reduced circuit footprint relative to 360 degree adjustable phase interpolators. In some embodiments, full sized and full range phase interpolators are used. Phase interpolator100generates two in-phase clock signals14. Phase interpolator102generates two quadrature clock signals16. In embodiments where W is equal to four, four phase interpolators are used. Each phase interpolator receives four of the eight total clock signals92and outputs two clock signals14or two clock signals16. Two of the four phase interpolators each outputs two of the four total in-phase clocks14. The two other phase interpolators each outputs two of the four total quadrature clocks16.

Calibration and adaptation block96controls delay of the mini phase interpolators100and102to adjust where the in-phase clocks14occur relative to quadrature clocks16. In one embodiment, calibration and adaptation block96is simply an IQ detector that receives clocks14-16and adjusts phase interpolators100-102until each clock is spread out evenly across a full clock cycle. In other embodiments, an eye monitor is used that observes input serial data22and shifts in-phase clocks14to maximize the margin of samples taken by data sampler block20.

In some embodiments, CDR10calibrates phase interpolators100-102by providing input serial data22as a square wave at a frequency slightly offset from the frequency of DCO84. During the calibration process, the data samples24and edge samples26are expected to be high, or binary one, half of the time, and therefore low, or binary zero, half the time. The numbers of high versus low samples are analyzed to sense the relative spacing of in-phase clocks14and quadrature clocks16, and determine a better setting for the mini phase interpolators100-102. Calibrating phase interpolators100-102in the above manner compensates for mismatches between samplers in data sampler block20using in-phase clocks14and samplers using quadrature clocks16.

FIG. 2cillustrates a timing diagram of clocks14-16and input serial data22when W is equal to 2. The two in-phase clocks14are designated as clock14[0] and clock14[1]. The two quadrature clocks16are designated as clock16[0] and clock16[1]. In-phase clock14[0] has a rising transition at 0 degrees. The rising transition of clock14[0] triggers data sampler block20to sample a first data bit (D0) of input serial data22. Clock16[0] has a rising transition at 90 degrees that triggers data sampler block20to sample an edge of input serial data22between D0and a second data bit (D1).

Input serial data22is illustrated as a series of eye patterns with edges at 90, 270, and 450 degrees. Each of the illustrated data bits D0-D3could potentially be a binary zero or a binary one. If D0is a binary zero, and D1is a binary one, then the data edge at 90 degrees is a rising transition. If D0is a binary one, and D1is a binary zero, then the data edge at 90 degrees is a falling transition. If both D0and D1are the same value, either binary one or binary zero, then no transition is observed at 90 degrees. Input serial data22remains a straight line from zero degrees until the next potential transition at 270 degrees.

If D0is different than D1, the sample taken with clock16[0] at 90 degrees will indicate the timing, either early or late, of clock16[0]. If clock16[0] is early, the sample taken by data sampler block20using clock16[0] will be the same as D0. If clock16[0] is late, the sample using clock16[0] will be the same as D1. If D0is the same value as D1, then no actual transition is observed in input serial data22, and the early or late status of clock signal16[0] cannot be discerned. Clock14[1] causes data sampler block20to sample D1at 180 degrees, and clock16[1] samples an edge of the input serial data between D1and a third data bit (D2) at 270 degrees. Then data sampler block20generates a rising transition of clock signal28to indicate to deserializer30that all W center data samples24and W edge samples26have been taken. In one embodiment, clock16[1] is used to generate clock28because clock16[1] is the last of clocks14-16to transition. The cycle starts over again with clock14[0] having another rising transition at 360 degrees, i.e., 0 degrees of the next cycle.

FIG. 2dillustrates eye monitor106of calibration and adaption block96which is used to adjust the relative phases of in-phase clocks14and quadrature clocks16in some embodiments. A full range phase interpolator104receives the 2W clock phases92from DCO84and outputs 2W evenly spaced clock signals105to eye monitor106. Eye monitor106monitors input serial data22and uses control signal107to adjust the quadrature clocks of clock signals105relative to the in-phase clocks of clock signals105. As the phases of clocks105are adjusted, eye monitor106observes the difference between the power level of a binary zero and a binary one on input serial data22. Eye monitor106adjusts the relative phases of in-phase and quadrature clocks of clock signals105until a maximum margin between binary input values is observed. Eye monitor106then uses phase interpolator signal98to adjust phase interpolators100and102of phase interpolator94accordingly.

In one embodiment, CDR10initially calibrates phase interpolators100and102by providing input serial data22as a clock signal and comparing low and high samples of center data44. CDR10then continues adjusting or adapting phase interpolators100and102using eye monitor106as data is received. Various factors, including intersymbol interference and channel noise, affect the actual rise or fall trajectory of input serial data22. Eye patterns of input serial data22may change over time, and eye monitor106periodically adjusts phase interpolator94as changes are detected by phase interpolator104and eye monitor106.

The eye pattern of a serial data signal represents how the signal looks on an oscilloscope display. An eye pattern shows multiple superimposed transitions, so that an observer gets a picture of the average positive and negative transition paths.FIG. 2eillustrates eye pattern108. Eye pattern108includes edge E0at 90 degrees and edge E1at 270 degrees. By default, data sampler block20takes a center data sample (C1) at 180 degrees, i.e., halfway between edges E0and E1. However, eye pattern108is vertically widest at 150 degrees. The difference between the power levels of a binary zero value and a binary one value of input serial data22is greatest at 150 degrees. Using eye monitor106to adjust in-phase clocks14to occur earlier in the data cycle increases the likelihood that data sampler block20will be able to accurately discern binary one values from binary zero values of input serial data22.FIG. 2fillustrates eye pattern109. Eye pattern109is similar to eye pattern108, but includes an optimal sample time at 225 degrees. Eye monitor106adjusts clocks105to discover the optimal center data sample time relative to the signal edges, and uses phase interpolator adjust signal98to adjust phase interpolators100and102accordingly.

FIG. 3illustrates data sampler block20of CDR10with W equal to two. Data sampler block20receives two in-phase clocks,14[0] and14[1], as well as two quadrature clocks,16[0] and16[1]. Input serial data22is routed to data sampler block20from a transmit source. In one embodiment, an optical signal from a transmit source is routed to a photo diode, which generates a corresponding electrical signal that is routed to data sampler block20as input serial data22. Flip-flops110-116sample input serial data22based on clocks14-16to generate data samples24-26. Inverters118and120introduce a delay between clock16[1] and clock28to ensure that the output of flip-flop116is setup before clock28is received by deserializer30. In some embodiments, data sampler block20includes a decision feedback equalizer (DFE) to reduce the effects of intersymbol interference on data samples.

Each of flip-flops110-116receives a digital input signal at data input terminals marked with the letter D inFIG. 3, and an input clock signal at clock input terminals marked with a triangle. At every rising transition of the input clock signal, a binary value at the data input is transferred and stored to a data output of the flip-flop, marked with the letter Q. The data output of the flip-flop is held static until a subsequent rising transition of the clock signal results in another transfer and storage of another input data bit (D) to the output data terminal (Q).

Flip-flop110copies input serial data22to in-phase sample24[0] at each rising transition of in-phase clock14[0]. Flip-flop110stores the value of in-phase sample24[0] until a subsequent rising transition of in-phase clock14[0] causes flip-flop110to store a new sample of input serial data22. The new sample could be the same binary value as the old sample, in which case no transition is observed at sample output24[0]. Flip-flop112copies a value from input serial data22to quadrature sample26[0] at every rising transition of quadrature clock16[0]. Flip-flop114copies a value from input serial data22to in-phase sample24[1] at every rising transition of in-phase clock14[1]. Flip-flop116copies a value from input serial data22to quadrature sample26[1] at every rising transition of quadrature clock16[1].

With W equal to four, data sampler block20uses four flip-flops to create center data samples24[0],24[1],24[2], and24[3] based on in-phase clocks14[0]-14[3], and four flip-flops to create edge samples26[0]-26[3] based on quadrature clocks16[0]-16[3]. In general, data sampler block20uses 2W flip-flops to create W center data samples24and W edge samples26based on W in-phase clocks14and W quadrature clocks16.

Inverters or buffers118and120introduce a delay between quadrature clock16[1] and clock signal28. The delay of inverters118and120is provided so that the value of input serial data22at the data input of flip-flop116has time to propagate through to edge sample26[1] before deserializer30receives the rising transition of clock signal28. A different number of inverters is used in some embodiments depending on the propagation timing of flip-flop116. In other embodiments, different methods of generating clock signal28are used.

FIG. 4illustrates an embodiment of deserializer30with K and W both equal to two, and N and M each equal to eight. Center data samples24are routed to proportional feedback path40as center data samples34. Edge samples26are routed to proportional feedback path40as edge samples36. Clock28is routed to proportional feedback path40as clock38. Because the width of data used by proportional feedback path40, K, is equal to W, proportional feedback path40is capable of using center data samples24, edge samples26, and clock28without further deserialization. The clock speed of proportional feedback path40is the same as each individual flip-flop of data sampler block20. More generally, the clock frequency of clock signal38used by proportional feedback path40is the frequency of clock signal28multiplied by W/K when K is greater than W.

On the other hand, the embodiment ofFIG. 4has both N and M equal to eight. That is, integral feedback path50operates on eight center data samples44and eight edge samples46at a time. In other embodiments, N and M are greater than eight, e.g., sixteen, twenty, thirty-two, or sixty-four. Clock signal48used by the circuitry of integral feedback path50operates at one quarter of the frequency of each individual sampler because N is four times W. More generally, the clock frequency of clock signal48used by integral feedback path50is the frequency of clock signal28multiplied by W/N.

Shift register130is used by deserializer30to generate the eight-bit wide center data samples44from the two-bit wide center data samples24. Shift register130includes four pairs of bits132-138, which are each capable of storing one set of center data samples24. The pairs of bits132-138are output in parallel to integral feedback path50as center data samples44. Shift register140is used by deserializer30to generate the eight-bit wide edge samples46from the two-bit wide edge samples26. Shift register140includes four pairs of bits142-148, which are each capable of storing one set of edge samples26. The pairs of bits142-148are output in parallel to integral feedback path50as edge samples46. Clock divider150is a 1:4 divider that generates clock48at one quarter of the clock frequency of clock28.

Shift register130receives and operates based on clock28. At each rising transition of clock signal28, the two bits of center data samples24are stored into bits132of shift register130. The two bits previously stored in bits132are shifted to bits134. The two bits previously stored in bits134are shifted to bits136. The two bits previously stored in bits136are shifted to bits138. The two bits that were previously stored in bits138are discarded. Every four clock cycles of clock28, four new sets of center data samples24have been stored in shift register130. Clock divider150generates a rising transition of clock48to trigger integral feedback path50to operate on the eight center data samples44. Then, over the next four clock cycles of clock28, the old samples are shifted out of shift register130and eight new bits of center data samples24are stored in bit pairs132-138.

Shift register140operates similarly to shift register130. Edge samples26are shifted into bit pair142to bit pair144, bit pair146, and bit pair148. Four new sets of edge samples26are stored at the same time as four new center data samples24are stored in shift register130, so the same transition of clock48triggers integral feedback path50to operate on both center data samples44and edge samples46.

In some embodiments, the bit-width of edge samples46, M, is less than the bit-width of center data samples44, N. M is a lower number than N in embodiments where only a subset of edge samples are used by integral feedback path50to update frequency error signal52. Only the edge samples needed to perform the calculation are sent to integral feedback path50. Each sampled data bit is generally part of center data samples44because the N center data samples are stored in memory as the received data for use by the operating system or other software or hardware applications of a system including CDR10. In embodiments where the bit-width of edge samples46, M, is lower than the bit-width, N, of center data samples44, an optional edge mute control signal is utilized to prevent operation of shift register140for some positive transitions of clock signal28.

FIG. 5aillustrates proportional feedback path40in an embodiment with K equal to 2. Center data samples34[0] and34[1] can be the same signal as any two center data samples24. Edge samples36[0] and36[1] can be the same as any two edge samples26. The four clock signals14-16are used because proportional feedback path40operates at the same speed as data sampler block20. In some embodiments, where deserialized data is used for proportional feedback path40, clock dividers are used to reduce the operating speed of the clocks. In other embodiments, proportional feedback path40operates using a single clock signal.

XOR gate160includes center data sample34[0] and edge sample36[0] as inputs, and generates an output to flip-flop162. Flip-flop162samples the output of XOR gate160using in-phase clock signal14[0] and outputs an up signal164. XOR gate170includes center data sample34[1] and edge sample36[1] as inputs, and generates an output to flip-flop172. Flip-flop172samples the output of XOR gate170using in-phase clock signal14[1] and outputs an up signal174. OR gate176outputs a binary one value on phase error signal42[0] if either up signal164or up signal174is a binary one value. Up signals164and174include a binary one value if clocks16are late relative to the edges of input serial data22. Up signals164and174include a binary zero value if clocks16are not late relative to the edges of input serial data22.

XOR gate181includes edge sample36[0] and center data sample34[1] as inputs, and generates an output to flip-flop182. Flip-flop182samples the output of XOR gate181using quadrature clock signal16[0] and outputs a down signal184. XOR gate190includes edge sample36[1] and center data sample34[0] as inputs, and generates an output to flip-flop192. Flip-flop192samples the output of XOR gate190using quadrature clock signal16[1] and outputs a down signal194. OR gate196outputs a binary one value on phase error signal42[1] if either down signal184or down signal194is a binary one value. Down signals184and194include a binary one value if clocks16are early relative to the edges of input serial data22. Down signals184and194include a binary zero value if clocks16are not early relative to the edges of input serial data22. Phase error signal bits42[0] and42[1] are routed to clock generation block12. Clock generation block12uses the up and down pulses of phase error signal42to adjust a delay in generating in-phase clocks14and quadrature clocks16.

A two-input XOR gate, e.g., XOR gates160,170,181, and190, outputs a binary one value if the two inputs to the XOR gate are at different binary values. If a two-input XOR gate has both inputs at a binary one value, or both inputs at a binary zero value, the XOR gate outputs a binary zero value. Therefore, XOR gates160,170,181, and190are used to determine if their respective inputs are the same or different binary values.

In particular, XOR gate160determines whether center data sample34[0] is the same binary value as edge sample36[0]. If the binary value of input serial data22changed between when data sampler block20took center data sample34[0], and when the data sampler block took edge sample36[0], then clock signal16[0] is late. The transition of input serial data22occurred before the transition of quadrature clock signal16[0], which is the clock signal used to take edge sample36[0]. A rising transition of clock signal14[0] causes the binary one value output by XOR gate160to be latched by flip-flop162. Therefore, up signal164and phase error signal42[0] will include a binary one value at least until the next positive transition of clock signal14[0]. XOR gate170operates similarly to XOR gate160, except that XOR gate170operates on center data sample34[1] and36[1]. XOR gate170determines the timing of quadrature clock16[1] relative to the edge of input serial data22immediately after the edge analyzed by XOR gate160.

XOR gate181determines whether edge sample36[0] is the same as or different than center data sample34[1]. If the binary value of input serial data22changed between when data sampler block20took edge sample36[0] and when the data sampler block took center data sample34[1], then clock signal16[0] is early. The transition of input serial data22occurred after the transition of quadrature clock signal16[0], which is the clock signal used to take edge sample36[0]. A rising edge of clock signal16[0] causes the binary one value output by XOR gate181to be latched by flip-flop182. Therefore, down signal184and phase error signal42[1] will include a binary one value at least until the next positive transition of clock signal16[0]. XOR gate190operates similarly to XOR gate181, except that XOR gate190compares edge sample36[1] and center data sample34[0]. XOR gate190determines the timing of quadrature clock16[1] relative to the edge of input serial data22immediately after the edge analyzed by XOR gate181.

In summary, flip-flop162generates a positive up signal164if quadrature clock16[0] is late, while flip-flop182generates a positive down signal184if quadrature clock16[0] is early. Flip-flop172generates a positive up signal174if quadrature clock16[1] is late, while flip-flop192generates a positive down signal194if quadrature clock16[1] is early. Up signals164and174are combined by OR gate176into a single up signal on phase error signal bit42[0]. Down signals184and194are combined by OR gate196to create a down signal on phase error signal bit42[1]. Phase error bits42[0] and42[1] are routed to DCO84in clock generation block12and control a delay in the generation of clock signals14-16.

FIGS. 5b-5gillustrate example transitions between D0and D1of input serial data22. In each of theFIGS. 5b-5g, a center data sample34[0] is taken near the center of D0, an edge sample36[0] is taken near the transition between D0and D1, and a second center data sample34[1] is taken near the center of D1. Proportional feedback path40compares the samples34[0],36[0], and34[1] to determine whether the edge sample36[0] was taken early or late compared to an actual transition between D0and D1.

Input serial data22inFIGS. 5b-5hutilizes OOK or ASK encoding of data. Line198inFIGS. 5b-5gdelineates between a binary zero value and a binary one value of input serial data22. The power level of input serial data22is illustrated on the vertical axes ofFIGS. 5b-5g. When the power level of input serial data22is above line198, data sampler block20samples the input serial data as a binary one. When the power level of input serial data22is below line198, data sampler block20samples the input serial data as a binary zero. In other embodiments, other encoding schemes besides on-off keying or amplitude-shift keying are used.

FIGS. 5band 5cillustrate a rising transition of input serial data22, with D0a binary zero value and D1a binary one. InFIG. 5b, sample36[0] is taken early, i.e., before input serial data22has changed from a binary zero to a binary one. Samples34[0] and36[0] are taken by data sampler block20as binary zeros, while sample34[1] is taken as a binary one. Applying the example ofFIG. 5bto the circuit ofFIG. 5a, XOR gate160compares sample34[0] and sample36[0], which are both binary zero, and outputs a binary zero value. Flip-flop162latches in a binary zero on the next rising transition of clock signal14[0]. A binary zero output by flip-flop162at output164indicates a lack of an up pulse. Assuming up signal174is a binary zero as well, both inputs to OR gate176remain binary zero, and no up pulse is generated on phase error signal42[0] to DCO84. On the other hand, sample36[0] is a binary zero while sample34[1] is a binary one. XOR gate181outputs a binary one value because the values of the XOR gate inputs are different. Flip-flop182latches in the binary one value from XOR gate181at the next rising edge of clock signal16[0] to generate a binary one at signal184. OR gate196outputs a binary one at phase error signal bit42[1]. DCO84receives phase error signal up bit42[0] as a binary zero and down bit42[1] as a binary one, and adds slightly to the delay used in generating clocks14-16.

FIG. 5cis similar toFIG. 5bexcept that sample36[0] is taken slightly after input serial data22transitions to a binary one value. InFIG. 5c, samples36[0] and34[1] are the same value, while sample34[0] is a different value. XOR gate160outputs a binary one value due to the differing values of samples34[0] and36[0]. Flip-flop162latches the binary one from XOR gate160and generates a binary one value on signals164and42[0]. XOR gate181outputs a binary zero value because samples36[0] and34[1] are the same binary value. Flip-flop182latches in the binary zero value, and signal184is a binary zero. Assuming output194of flip-flop192is a binary zero, phase error signal bit42[1] to DCO84is a zero. DCO84receives up bit42[0] as a binary one and down bit42[1] as a binary zero, and slightly reduces the delay used in generating clocks14-16.

FIGS. 5dand 5eillustrate a falling transition of input serial data22, with D0a binary one value and D1a binary zero. InFIG. 5d, sample36[0] is taken early, i.e., while input serial data22is still a binary one value. Samples34[0] and36[0] are taken by data sampler block20as binary ones, while sample34[1] is taken as a binary zero. Applying the example ofFIG. 5dto the circuit ofFIG. 5a, XOR gate160compares sample34[0] and sample36[0], which are both binary one, and outputs a binary zero value. Flip-flop162latches in a binary zero on the next rising transition of clock signal14[0]. No up pulse is generated by flip-flop162at output164. Assuming up signal174is a binary zero as well, both inputs to OR gate176remain binary zero, and no up pulse is generated on phase error signal42[0] to DCO84. On the other hand, sample36[0] is a binary one while sample34[1] is a binary zero. XOR gate181outputs a binary one value because the values of the XOR gate inputs are different. Flip-flop182latches in the binary one value from XOR gate181at the next rising edge of clock signal16[0] to generate a binary one at signal184. OR gate196outputs a binary one at phase error signal bit42[1]. DCO84receives up bit42[0] as a binary zero and down bit42[1] as a binary one, and adds slightly to the delay used in generating clocks14-16.

FIG. 5eis similar toFIG. 5dexcept that sample36[0] is taken slightly after input serial data22transitions to a binary zero value. InFIG. 5e, samples36[0] and34[1] are the same value, while sample34[0] is a different value. XOR gate160outputs a binary one value due to the differing values of samples34[0] and36[0]. Flip-flop162latches the binary one from XOR gate160and generates a binary one value on signals164and42[0]. XOR gate181outputs a binary zero value because samples36[0] and34[1] are the same binary value. Flip-flop182latches in the binary zero value, and signal184is a binary zero. Assuming output194of flip-flop192is a binary zero, phase error signal bit42[1] to DCO84is a zero. DCO84receives up bit42[0] as a binary one and down bit42[1] as a binary zero, and slightly reduces the delay used in generating clocks14-16.

FIGS. 5fand 5gillustrate examples with D0and D1of input serial data22being the same binary value. InFIG. 5f, samples34[0],36[0], and34[1] are all binary zero values. InFIG. 5g, samples34[0],36[0], and34[1] are all binary one values. In either case, all three samples have the same binary value, and therefore both XOR gates160and181output binary zero values. Assuming that signals174and194are binary zero, both phase error bits42remain binary zero and DCO84makes no adjustment to the delay used in generating clocks14-16.

FIGS. 5hand 5iare timing diagrams of proportional feedback path40over multiple data bits, D0-D3, of input serial data22with W equal to 2.FIG. 5hillustrates proportional feedback path40comparing edge sample36[0] against previous center data sample34[0] to potentially generate an up signal164. Sample34[0] begins in the graph at a value of CX, which was taken from a previous bit of input serial data22. Sample36[0] begins at a value of EX, which was taken at an edge between two previous data bits of input serial data22.

A rising edge of clock signal14[0] occurs at time0, and triggers flip-flop162to latch in the value of CXXOR EXfrom XOR gate160to flip-flop output164. The rising edge of clock14[0] also causes data sampler block20to take a new center data sample, C0, and overwrite the value CXin sample bit34[0] with the new center data sample value. Circuit delays allow flip-flop162to latch in a value based on CXprior to CXbeing overwritten by C0. C0is equal to the value of D0, either a binary zero or binary one. A rising edge of clock16[0] occurs at time90and causes data sampler block20to take a new edge sample, E0, and overwrite the value EXin sampler36[0] with the new value.

At time360, a second rising transition of in-phase clock14[0] causes flip-flop162to latch in a new value from XOR gate160, i.e., C0XOR E0, to flip-flop output164. Clock14[0] also causes data sampler block20to take a new center data sample C2, at time360. The center data sample C2is stored in sample bit34[0], overwriting C0. Clock16[0] has a rising transition at time450that causes data sampler block20to overwrite the value E0stored in sample bit36[0] with the new edge sample value E2.

Clock16[0] and sample36[0] are the same inFIG. 5ias inFIG. 5h. Rising edges of clock signal16[0] cause flip-flop182to latch in a value of E0at time90and E2at time450.FIG. 5iillustrates edge sample36[0] being compared against the next center data sample,34[1], to potentially generate a down pulse on phase error signal bit42[1]. Sample34[1] begins at a value CY, which was sampled from the data bit on input serial data22before D0. The rising edge of clock16[0] at time90causes flip-flop182to latch in the value EXXOR CYbefore also causing a new value E0to overwrite the value EXin sample36[0]. At time180, clock signal14[1] has a rising transition which causes data sampler20to store the value D1of input serial data22to sample34[1] as C1.

At time450, the rising edge of clock16[0] causes flip-flop182to latch in a new value from XOR gate181, this time E0XOR C1. The rising transition of clock16[0] at time450also causes a new sample value, E2, to be stored in edge sample bit36[0]. E2is a sample taken near the edge between D2and D3of input serial data22. At time540, a rising transition of in-phase clock14[1] causes the value D3from input serial data22to be stored in sample bit34[1] as value C3. The rising transition of in-phase clock14[1] also causes an XOR comparison of the value C1with an edge value from sample36[1] to be latched into flip-flop172, which is not illustrated inFIG. 5i.

FIG. 6aillustrates integral feedback path50of CDR10. Integral feedback path50receives N parallel center data samples44and M parallel edge samples46. Center data samples44and edge samples46are routed to a parallel phase detector210. Parallel phase detector210generates M up pulses212and M down pulses214to adder216. Adder216uses up pulses212and down pulses214to create a single signed integer sum218representative of the early or late status of edge samples36as a whole. Sum218is routed to decimator220where the integer value is reduced if desired. Decimator220outputs a signed integer value222to accumulator224. Accumulator224adds signed integer222to the already existing signed integer value being output as frequency error signal52.

In embodiments where M is smaller than N, i.e., parallel phase detector210does not operate on all edge samples26, only the M edge samples to be analyzed are routed to integral feedback path50. In some embodiments, all N center data samples are still routed to parallel phase detector210. In other embodiments, less than every center data sample44is routed to parallel phase detector210. Only the center data samples44required to determine whether the specific M edge samples46were taken early or late are routed to parallel phase detector210even though all N center data samples44are still output to another module external to CDR10as the received data.

Parallel phase detector210operates similarly to proportional feedback path40inFIGS. 5a-5i. However, parallel phase detector210operates on all M edge samples46at once. Parallel phase detector210compares each edge sample46to respective immediately preceding and subsequent center data samples44, similar to as shown inFIGS. 5b-5gfor an individual edge sample, to determine whether each edge sample46was early or late. The determination occurs as explained with regard to proportional feedback path40. If an edge sample46is a different value than an immediately preceding center data sample44, then that edge sample46was late and the value of input serial data22changed before the quadrature clock16triggered the edge sample. If an edge sample46is a different value than an immediately subsequent center data sample44, then that edge sample46was early and the value of input serial data22had not changed yet when quadrature clock16triggered the edge sample.

Parallel phase detector210outputs an M-wide bus of up pulses212and an M-wide bus of down pulses214. Each individual bit of bus212is similar to phase error signal42[0], and includes a binary one value if the particular edge associated with the bit was determined to be late. Each individual bit of bus214is similar to phase error signal42[1], and includes a binary one value if the particular edge associated with the bit was determined to be early. Parallel phase detector210includes M parallel bang-bang phase detectors in one embodiment.

Adder216generates a signed integer representative of the total number of up pulses212and down pulses214that contain a binary one value. In one embodiment, adder216subtracts the total number of binary one bits of down pulses214from the total number of binary one bits of up pulses212and outputs the result as a signed integer. Sum218represents the net value of the up and down decisions made by parallel phase detector210and output at signals212-214.

Decimator220reduces the value of sum218using an algorithm modifiable according to a decimation setting. In one embodiment, decimator220operates in either a proportional scaling mode or a majority vote mode. In proportional scaling mode, the output222of decimator220is proportional to the input218. The scaling factor applied by decimator220in the proportional scaling mode can be adjusted so that sum218is divided by 1, 2, 4, 8, or 16. In other embodiments, other scaling factors are used. Proportional scaling mode is generally used to speed up locking time, and the scaling factor can be progressively modified in a form of gear-shifting of integral feedback path50. Majority vote decimation is generally used when CDR10is locked to input serial data22and only small adjustments are required to clock generation block12. When in majority vote mode, decimator220outputs a fixed positive or negative number depending on whether the M edge samples46as a whole were early or late.

Accumulator224outputs a signed integer on frequency error signal52, which generally begins at, or has a reset value of, zero. For each clock cycle of clock48, i.e., for each new set of N center data samples44and M edge samples46, accumulator224adds output222of decimator220to the frequency error signal52. If sum218is a positive number, accumulator224increases the value of frequency error signal52. If sum218is a negative number, accumulator224decreases the value of frequency error signal52. The magnitude of change in frequency error signal52depends on the number of binary one up pulses212relative to the number of down pulses214, and also the decimation algorithm used by decimator220. Oscillator frequency control block80receives frequency error signal52and modifies the frequency of clocks88from DCO84accordingly.

In one embodiment, integral feedback path50utilizes delta-sigma modulation to dither between two neighboring values of frequency error signal52at pseudorandom times. Delta-sigma modulation in integral feedback path50increases the capability of CDR10to handle consecutive identical digits (CIDs) received on input serial data22. When a string of consecutive identical digits is received, there are no edges of input serial data22that cross over between a binary one and binary zero value, and parallel phase detector210is unable to detect whether any of the edge samples46are early or late. Without delta-sigma modulation, frequency error signal52generally does not update while receiving consecutive identical digits. The DCO84is unlikely to match the frequency of input serial data22exactly, and any error during consecutive identical digits will compound and potentially result in data errors. Increasing the resolution of frequency error signal52helps CDR10receive increased consecutive identical digits because the frequency error of DCO84can be reduced. Sigma-delta modulation helps by allowing the value of frequency error signal52to fluctuate between values rather than stay on a static value during consecutive identical digits.

FIG. 6billustrates an alternative embodiment of integral feedback path50with the addition of an optional lock or loss-of-lock detection block230. Lock detection block230monitors the integer of frequency error signal52and determines a rate of change of the frequency error signal. Lock detection block230determines lock or loss-of-lock by comparing the rate of change of frequency error signal52to a configurable threshold. If the rate of change of frequency error signal52exceeds the threshold, lock detection block230considers the frequency lock of CDR10to be lost, and uses lock status signal232to notify relevant blocks of the CDR. When the rate of change of frequency error signal52is under the threshold, lock detection block230outputs the status as locked at lock status signal232. In one embodiment, lock status signal232is a binary value, with a binary zero indicating a frequency lock and a binary one indicating a loss of frequency lock, although the opposite is also possible. In other embodiments, lock detection block230outputs the rate of change of frequency error signal52, which can then be interpreted by other blocks of CDR10.

Lock or loss-of-lock status signal232is used for various purposes in different embodiments. In one embodiment, a loss-of-lock indication triggers CDR10to run a calibration subroutine or reload calibration values from a previously executed calibration process. In some embodiments, DCO84is recentered to allow CDR10to relock.

FIGS. 7aand 7billustrate alternative embodiments of deserializer30, with W still equal to two. InFIG. 7a, K is equal to four, meaning proportional feedback path40operates on four center data samples34and four edge samples36at a time. N is equal to 8 while M is equal to four, which means that integral feedback path50calculates the early/late status of four edge samples46out of every eight edge samples26that are actually taken from input serial data22.

Shift register250receives center data samples24, and deserializes the two center data samples24to four center data samples34using bit pairs252and254. Bit pairs252and254output the two most recent sets of center data samples24in parallel as the four center data samples34. Clock divider256creates clock signal38at half the frequency of clock signal28, so that clock signal38includes a rising transition every time two new pairs of samples are available in shift register250. Center data samples34are routed not only to proportional feedback path40, but also to shift register260for further deserialization. Shift register260uses clock38to store four center data samples34in set of four bits262and shift the data existing in bits262to a second set of four bits264. Shift register260outputs sets of bits262and264in parallel as an eight bit wide data bus of center data samples44to integral feedback path50. Shift registers250and260operate as two deserializers connected in serial.

Clock divider266creates clock signal48at half the frequency of clock signal38, so that clock48includes a rising edge every time a new set of eight center data samples44is ready to be read from shift register260. In some embodiments, clock dividers256and266are formed from a single counter running off of clock28, with clocks38and48tapped off of two different bits of the counter.

Shift register271operates similarly to shift register250, but receives edge samples26rather than center data samples24. Shift register271outputs the two most recent sets of W edge samples26in parallel as edge samples36to proportional feedback path40. The most recent set of bits26is stored in bits272, and the data in bits272is shifted to bits274, every rising transition of clock28. The output36of shift register271is connected as an input to shift register280, similar to how center data samples34are routed from shift register250to shift register260. However, M is only equal to four, meaning that only four edge samples26are used by integral feedback path50for every N, or eight in the illustrate embodiment, center data samples24received. Only one bit of each set of two bits272and274is connected as an input to shift register280. The second bit of each set of bits272and274is routed to proportional feedback path40but not to shift register280. The number of edge samples from a first deserializer, shift register271, to a second deserializer, shift register280, can be any value less than or equal to the total number of edge samples in shift register271. Generally, H edge samples from shift register271are routed to be stored in shift register280.

With only one out of every two bits routed from shift register271to shift register280, shift register280only stores a sample of every other edge of input serial data22. Every rising transition of clock signal38, shift register280stores two of the four most recent edge samples26to bits282, and shifts the data existing in bits282to bits284. Bits282and284are output by shift register280in parallel as four-bit wide edge samples46to integral feedback path50. In one embodiment, proportional feedback path40calculates phase error signal42based on one or more bits from shift registers250and271and one or more bits from center data samples24and edge samples26.

In some embodiments, the bit-width of each deserializer output34,36,44, and46is configurable. A control signal is received that reconfigures shift register260to utilize an additional eight bits that are available. The control signal also updates clock divider266so that clock divider266generates clock signal48at one fourth of the clock frequency of clock signal38. N is equal to 16. Shift register260outputs the sixteen most recent center data samples24, with sixteen new samples available every rising transition of clock48. M could remain at four, in which case an edge mute signal would be used to block certain edge samples36from being stored in shift register280. Only four edge samples26out of every sixteen edge samples26is stored as edge samples46and analyzed by integral feedback path50. M could instead be increased to eight by assigning four additional bits to shift register280. Each of the shift registers250,260,271, and280can be grown or shrunk independently as desired by configuring CDR10.

WhileFIG. 7aillustrates two sets of shift registers, i.e., two deserializers, connected in serial,FIG. 7bshows shift registers operating in parallel. Shift register300inFIG. 7boperates similarly to shift register250inFIG. 7a. Shift register300stores the two most recent sets of center data samples24in bit pairs302and304, and outputs the bits in parallel as center data samples34to proportional feedback path40. Shift register310inFIG. 7boperates similarly to shift register271inFIG. 7a. Shift register310stores the two most recent sets of edge samples26in bit pairs312and314, and outputs the bits in parallel as edge samples36to proportional feedback path40. In some embodiments, proportional feedback path40calculates phase error signal42based on one or more bits from shift registers300and310and one or more bits from center data samples24and edge samples26.

Shift register320inFIG. 7bgenerates the N-wide center data samples44, as does shift register260inFIG. 7a. However, shift register320receives the W center data samples24from data sampler block20in parallel with shift register300rather than the K center data samples34output by shift register300. Shift register320stores two new bits from center data samples24in bits322every time clock28has a rising transition, and shifts bits322to bits324, bits324to bits326, and bits326to bits328. Every four clock cycles of clock28, shift register320contains eight new center data samples44.

Shift register330inFIG. 7bgenerates edge samples46from edge samples26in parallel with shift register310generating edge samples36from edge samples26. InFIG. 7b, M is equal to two. For every eight (N) center data samples of input serial data22, two edge samples of the input serial data are considered by integral feedback path50. Only one bit of the W edge samples26is connected as an input to shift register330. Therefore, integral feedback path50is only capable of receiving one out of every two edge samples when W is equal to two, or one out of every four edge samples when W is equal to four. In other embodiments, any combination of edge samples, including every edge sample26, can be received by shift register330.

Edge mute signal336is used to control which samples26[0] to store in shift register330. For every new set of eight center data bits44, only two edge samples can be stored in shift register330to be sent to integral feedback path50as edge samples46. Edge mute signal336is held low in one embodiment, which causes shift register330to store every new edge sample26[0] in bit332while shifting bit332to bit334. In the embodiment where edge mute signal336is held low, integral feedback path50will always receive the last two edge samples26[0] for a given set of center data samples44. In other embodiments, a clock signal or other square wave is used for edge mute signal336to cause alternating edge samples26[0] to be stored in shift register330. Edge mute signal336is used to store any arbitrary edge samples26[0] in shift register330. In one embodiment, edge mute signal336disables a portion of the edge samplers in data sampler block20, and also reduces the number of edges considered by proportional feedback path40.

Clock divider340is similar to clock divider266inFIG. 7a. Clock divider342is similar to clock divider256inFIG. 7a. Like clock dividers256and266, clock dividers340and342are implemented as a counter in some embodiments, with clock signals38and48being drawn from different bits depending on the configuration of the values of K and N.

Shift register320could be made any arbitrary size whileFIG. 7bremains the same in other respects. If N were equal to 32, for instance if the device using CDR10used a 32-bit data bus and stored data samples44in a 32-bit FIFO, shift register320would store 16 new pairs of center data samples24for each cycle of clock48. For each 32 bits of data received on input serial data22, stored in parallel in shift register320, two of the edge samples would be stored in shift register330for analysis by integral feedback path50. The number of edge samples46, i.e., the size of shift register330, per N center data samples44could also be increased or decreased as desired. Edge mute signal336controls which edge samples are stored in shift register330. For example, with M equal to two and N equal to thirty-two, shift register330could store the first and 16th edge sample of the group of thirty-two edge samples26taken during the period of clock signal48.

CDR10with deserializer30uses two separate phase detectors, one for proportional feedback path40and one for integral feedback path50. The separate phase detectors work on deserialized, or parallelized, samples of input serial data22. Deserializing input serial data22allows proportional feedback path40and integral feedback path50to operate at slower clock speeds than the baud rate of input serial data22. Slower clock rates of the logic of CDR10eases manufacturing constraints and allows for simpler designs. The clock speed of proportional feedback path40is reduced by a factor of K, while the clock speed of integral feedback path50is reduced by a factor of N. The reduced clock rate of integral feedback path50allows implementation using place-and-route layout with standard digital libraries. Edge mute signal336saves power by reducing the number of edge samples considered by integral feedback path50.

Using DCO84allows CDR10to frequency lock to input serial data without the need for a reference clock. Therefore, multiple CDR10circuits are usable in a single device, and each can frequency lock to a different input serial data22even when the baud rates of the input serial data signals are different. Phase interpolator94is used to allow CDR10to shift the center data sample location within an eye pattern of input serial data22, while maintaining edge samples26near the edges of the input serial data. Miniature phase interpolators are used to save real estate on the device.