Electronic circuit for decoding a read signal from an optical storage medium

The invention relates to an electronic circuit for decoding a read signal from an optical storage medium, the electronic circuit comprising a limit equalizer for amplification of high frequency read signal components without substantially increasing inter-symbol interference, a Viterbi detector being coupled to an output of the limit equalizer for providing the decoded read signal, a coefficient adaptation circuit for tuning the limit equalizer to a partial response target.

FIELD OF THE INVENTION

The present invention relates to the field of reading and decoding of optical storage media, and more particularly to

BACKGROUND OF THE INVENTION

There's a variety of optical storage media with different data capacities, such as CDs and DVDs. In order to increase the capacity of a disc with a certain fixed diameter, the track pitch and the channel bit length have to be reduced, which requires a reduction of the laser spot size, i.e. a reduction of the used laser wave length. Currently, disc recording systems are under development which use blue laser diodes with a wave length of 405 nm.

For example, there is an emerging standard for a high capacity optical disc recording format which utilises blue-violet laser light and which is called ‘blu-ray disc’, or “BD” disc. A copy of the blue-ray disc standard can be obtained from Royal Phillips Electronics, Intellectual Property and Standards, Eindhoven, The Netherlands.

In order to increase the storage density further, the channel bit length is reduced to a higher degree than the gain in spot size reduction due to the shorter wave length, i.e. the ratio between the spot size and the channel bit length, which is known as the “information density”, is increasing.

In fact, the optical channel behaves like a lowpass filter and the transfer function is known as the “modulation transfer function”, or shortly MTF, in the literature.

For high data storage densities on optical discs, the modulation transfer function drops very steeply, i.e. the high frequency components of the analog read signal are attenuated considerably compared to the low frequency components. For example for a BD disc with a storage capacity of 25 GBytes, the shortest run-length components (2T) are attenuated by a factor of more than 20 dB compared to the longest run-lengths of 8T. This results in a large amount of inter-symbol interference (ISI), which is the reason that the eye-pattern, i.e. the HF signal obtained by summing the currents of the four elements of the photo detector (“Read channel1, RDCH1”), is nearly closed, even without noise.

In order to recover the user data stored on a high density optical disc, a Partial-Response Maximum-Likelihood (PRML) detection scheme is typically used. In a standard Partial-Response Maximum-Likelihood (PRML) detection system, a FIR filter with for example 7 taps is used for the equalization of the incoming signal to the selected partial-response target. If the equalization is made adaptively in order to further improve the data detection reliability, for example with a hardware implementation of the LMS (least-mean-square) algorithm, a relatively high implementation effort is necessary.

On the other hand, the re-shaping of the incoming waveform to a simple partial-response target like PR(1,2,1) with a memory length of 2 delivers only non-optimum results, since the modulation transfer function (MTF) for a high-density optical disc is too different compared to PR(1,2,1), requiring a high gain boost of the higher frequency components of the signal. This has the drawback that the noise is also attenuated considerably.

The other possibility is to use a more complicated partial-response target with a memory length of 3, i.e. PR(1,2,2,1), or even more. This has the advantage that the partial-response target frequency response is much more similar to the MTF of the optical channel and hence only a moderate amplification of the high frequency signal components is necessary. But the serious drawback is the high implementation effort needed (chip area) and that high processing speeds could not been achieved due to the complicated Viterbi detector.

For the jitter measurement, the blu-ray disc standard (BD) defines in its Annex 12.8 the so-called limit equalizer.

For example, a limit equalizer has a first stage with a conventional linear equalizer in order to reduce inter-symbol interference and boost the high frequency signal components. The limit equalisation is done after the linear equalisation. Before limiting the signal, the sampled data are interpolated. The configuration of the limit equalizer is almost the same as that of the FIR filter-type linear equalizer but the limiter limits the reproduced signal level except for the centre tap signal. The FIR filter acts as a high boost equalizer and its gain depends on the choice of a high boost coefficient. If the high boost coefficient becomes large then the gain of the FIR filter is high.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide for an improved electronic circuit and electronic device for reading of optical storage media, in particular for blu-ray discs, as well as a corresponding method and computer program product.

The present invention provides for an electronic circuit for decoding a read signal from a high density optical storage medium, such as a blu-ray disc (BD), where a limit equalizer is used as a partial-response equalizer for a succeeding Viterbi detector. This way highly reliable data detection can be achieved at a moderate hardware effort. In particular, a simpler partial response target and a simpler Viterbi detector can be used due to the combination of the limit equalizer and partial-response maximum-likelihood (PRML) detection.

In accordance with a further preferred embodiment of the invention, the high boost coefficient of the limit equalizer is adjustable and is controlled based on the outputs of the Viterbi detector, the envelope of the equalized read signal and timing information derived from the equalized read signal.

Further preferred embodiments of the invention are set forth in the dependant claims.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1shows a block diagram of electronic circuit100for decoding a read signal obtained from a high density optical disc. The electronic circuit100has analogue to digital converter (ADC)102for converting the analogue read signal to a digital signal. The digital output of ADC102is coupled to pre-equalizer104which has its output coupled to slicer106. Slicer106serves for defining a reference level and for removing of certain signal asymmetries.

The output of slicer106is coupled to limit equalizer108. Limit equalizer108has a high boost coefficient “m” which determines the gain for the amplification of the high frequency read signal components. Limit equalizer108is used as a partial-response equalizer with maximum-likelihood detection which is necessary for the succeeding Viterbi detector110. Viterbi detector110outputs the decoded read signal in the NRZ signal format.

Further electronic circuit100has phase locked loop (PLL)112for providing a bit clock signal. Envelope detector114and coefficient adaptation module116form a control system for adapting the high boost coefficient “m” of the limit equalizer108as it will be explained in more detail in the following.

In contrast to the BD standard, the analog read channel1eye-pattern is not sampled in the middle of the channel bit position but at the zero-cross position, which results in non-zero samples at the output of the equalizer, which is the input for the PLL.FIG. 2shows the waveform at the output of the limit equalizer.

This phase shift could be achieved either by an adequate PLL circuit, an additional FIR-Filter with an even number of coefficients (e.g. 2 coefficients 0.5+0.5D) between the limit equalizer and the PLL, or any other conceivable means.

FIG. 3shows the output of the equalizer measured with a DSO in persistence mode. By modification of the high-boost coefficient “m”, the smaller signal levels of the equalizer output signal can be raised or lowered.

FIG. 4shows the target waveform for the partial-response PR(1,2,1). This is how the input signal for the Viterbi detector should look like. It has four distinct signal levels: maximum amplitude (+1), half amplitude (+0.5), negative half amplitude (−0.5) and negative maximum amplitude (−1). The amplitude signal for the coefficient adaptation is derived with an envelope detector. This amplitude signal is also used as the reference level for the branch metric calculation inside the Viterbi detector, i.e. the branch metric calculation follows gain variations of the incoming signal.

By tuning of the high-boost coefficient “m” of the limit equalizer, a close merging of the two waveforms can be achieved. This is the task of the block coefficient adaptation module116inFIG. 1, which is shown in detail inFIG. 5:

The coefficient adaptation module has an input500for inputting of equalized read channel1which is the output of limit equalizer108(cf.FIG. 1). The equalized read channel1signal is delayed to take the corresponding delay of Viterbi detector110into account. This is done by means of delay block502which provides a delay of “n×T” which is the same delay as the delay of Viterbi detector110.

Further the amplitude of the equalized read channel one signal is applied at input504. The amplitude signal is provided by envelope detector114(cf.FIG. 1). The amplitude is divided by two by means of amplifier506to provide the half amplitude signal level. The delayed equalized read channel one and the half amplitude signal level are subtracted by means of subtractor508to provide the deviation signal “delta”.

By means of the gain factor510the signal “delta” is attenuated, for example by some powers of 2. This could be achieved by right-shifting the signal or feeding it to the less significant bits of the adder520. The amplified “delta” signal is inputted into an integrator filter512. The integrator filter512has module514which serves to limit the range of the resulting high boost coefficient “m” to for example +/−1. Further the integration filter512has multiplexer (MUX)516which receives the signal “update” as timing information. The output of MUX516is coupled to register518which stores the actual high boost coefficient value “m”. The output of register518is fed back to adder520. Adder520adds the amplified delta signal and the high boost coefficient value “m”. The result of the addition is inputted into module514.

Further there is half amplitude detector522which serves to detect points of time when the equalized read channel1signal is at +0.5 amplitude level. This detection is performed based on the NRZ format signal outputted by Viterbi detector110(cf.FIG. 1).

Half amplitude detector522provides the signal “half amplitude detected” which is inputted into AND gate524as well as the sign bit of the delayed equalizer read channel1signal. This way AND gate524provides the signal “update” which is at logical “1” when the equalized read channel1signal is at the half amplitude signal level. At these points of time the integrator filter512becomes operative and the high boost coefficient value “m” is updated in register518.

The NRZ output data stream from the Viterbi detector is used to find the position where a half amplitude level should be. The half amplitude detector522delivers a “1” for each detected intermediate level according to partial-response PR(1,2,1). The equalized read channel1signal is delayed for an appropriate number of bit clocks, i.e. that it coincides with the position signal “Half amplitude detected”. The “Update” signal is derived by adding the inverted sign bit, such that the adaptation circuit is only enabled for reference levels of +0.5 (circles inFIG. 2). The difference between the delayed equalized read channel1signal and the half amplitude is multiplied with a gain factor of for example 2^(−8) and added to the old coefficient value in order to form the new coefficient value whenever the update signal is high. Otherwise the register value is left unchanged.

The half amplitude detector522is explained in more detail inFIG. 6.

Half amplitude detector522has a chain of shift registers comprising D-Flip-Flops600,602and604. The NRZ-format signal provided by Viterbi detector110(cf.FIG. 1) is applied to the input of D-Flip-Flop600. The output of D-Flip-Flop is denoted A, output of D-Flip-Flop602is denoted B and output of D-Flip-Flop604is denoted C. The outputs A, B, and C are inputted into module606which implements look-up table608.

Module606outputs the signal “half amplitude detected” which is at logical “1” when the equalizer read channel one signal is at half amplitude level. For example if A=0, B=0 and C=0 the “half amplitude detected” signal is also logical “0” and if A=1, B=0 and C=0 the “half amplitude detected” signal is at logical “1”.

FIG. 7is illustrative of a corresponding flow chart. In step700the digital read signal obtained from the optical disk is inputted into a limit equalizer to provide an equalized read signal. In step702the required half amplitude level of the equalized read signal is determined by detecting the amplitude of the equalized read signal by means of an envelope detector (cf. envelope detector114ofFIG. 1). In step704the equalized read signal of step700is delayed by the delay of the Viterbi detector coupled to the limit equalizer (cf. Viterbi detector110ofFIG. 1). The required half amplitude signal level and the delayed equalized read signals are subtracted in step708to provide a deviation signal. In step706the point of time when the equalized read signal has its half amplitude signal level are detected. At these points of time, an integration of the deviation obtained in step708is performed in step710in order to provide an adapted high boost coefficient “m”.