Apparatus that prevent a malfunction of the circuit and reduce power consumption

An interface circuit provided with a first input/output unit and a second input/output unit which respectively access external apparatuses to which electric power is supplied from power sources via different electric power supply lines includes an acquisition unit configured to acquire information whether electric power is supplied to the respective external apparatuses based on a command from the outside; a selection circuit configured to select an input/output unit corresponding to an external apparatus to which electric power is supplied, from the first input/output unit and the second input/output unit based on the information acquired by the acquisition unit; and a control circuit configured to output an instruction corresponding to the command, to the external apparatus to which electric power is supplied, via the input/output unit selected by the selection circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an interface circuit, an integrated circuit apparatus including the interface circuit, and an electronic apparatus including the interface circuit.

2. Description of the Related Art

In recent years, along with a reduction in size and thickness of an electronic apparatus, a circuit board to control the electronic apparatus has been miniaturized. A method for realizing miniaturization of such circuit board includes a system-on-chip technology to mount a number of functions on a single integrated circuit apparatus. In particular, the system-on-chip technology is frequently used in an application specific integrated circuit (ASIC). Functions incorporated into an integrated circuit by the system-on-chip technology include, for example, analog to digital conversion, specific logic operation, communication control, sequence control by a central processing unit (CPU) or the like. As a result of such increased integration of various functions, the size of the ASIC is also increasing. To address a problem, as ASIC is designed which enables using of a circuit having specific functions in the ASIC for a plurality of applications.

In particular, in a case where the ASIC is configured to communicate with a plurality of elements (for example, memory such as electrically erasable programmable read-only memory (EEPROM)), a method of communicating with a plurality of elements using one communication data generation circuit inside the ASIC has been conventionally considered.

For example, there is a method for disposing communication signal lines connecting a plurality of elements in parallel to each other on a circuit board so that a target element for communication can be selected by controlling a chip select signal. However, a problem arises when each of a plurality of elements receives electric power (supplied by different electric power system) having a different voltage for its operation.

The problem is that a communication signal to be input to an element which is supplied with electric power is input to an element which is not supplied with electric power. The input of this signal may result in a failure or a malfunction of the element receiving no electric power supply.

To address this problem, there is a conventional technology that connects a diode or the like to a communication signal line on a circuit board.

FIG. 5is a circuit diagram discussed in Japanese Patent Application Laid-Open No. 2-242313. A main apparatus11is connected with peripheral apparatuses21and22arranged in parallel to each other. The peripheral apparatuses21and22are supplied with different voltages, that is, VCC1and VCC2respectively.

Each input terminal of the peripheral apparatuses21and22is pulled up by each voltage. The No. 2-242313 discusses that even if the voltages VCC1and VCC2are different, when a transistor11ais turned off, the come-around of a voltage signal can be prevented by a diode41or42.

FIG. 6is a circuit diagram discussed in Japanese Patent Application Laid-Open No. 2002-132401. A microprocessor unit (MPU)30and a data processing random access memory (DPRAM)40are respectively run by different power source systems MVCC and SVCC. A diode D1and a diode D2are connected to one another with reverse polarity. For example, when the power source system SVCC is disconnected, signal lines S1, S2, and S3are pulled up by the power source system MVCC. However, the come-around of a voltage signal to the power source system SVCC side can be prevented by addition of the diode D2.

However, in the conventional circuits discussed in Japanese Patent Application Laid-Open No. 2-242313 and Japanese Patent Application Laid-Open No. 2002-132401, it is required to mount an additional component (diode) on a circuit board. This results in the increase of component count and manufacturing cost. Further, the increase of component count restricts pattern design of circuit wiring and interferes with miniaturization of an electronic circuit board.

To avoid additional components, there is a method for supplying electric power to all elements connected in parallel when executing communication with an element. In this method, electric power is supplied to all elements including an element that does not obtain access.

For example, in an electronic apparatus, to reduce electric power consumption during standby, electric power is supplied only just before and after an access is obtained. However, in the above-described method for supplying electric power to all elements, electric power is supplied and terminated although an element is not accessed, thus the frequency of supply and suspension of electric power is increased. Such increased frequency can reduce the life of elements.

Further, in the method of supplying electric power to all elements, elements cannot be protected when a failure of an electric power supply system occurs.

SUMMARY OF THE INVENTION

The present invention is directed to an interface circuit and an integrated circuit apparatus that prevent a failure or a malfunction of an element and reduce power consumption.

According to an aspect of the present invention, an interface circuit provided with a first input/output unit and a second input/output unit which respectively access external apparatuses to which electric power is supplied from power sources via different electric power supply lines includes an acquisition unit configured to acquire information whether electric power is supplied to the respective external apparatuses based on a command from the outside; a selection circuit configured to select an input/output unit corresponding to an external apparatus to which electric power is supplied from the first input/output unit and the second input/output unit based on the information acquired by the acquisition unit; and a control circuit configured to output an instruction corresponding to the command to the external apparatus to which electric power is supplied, via the input/output unit selected by the selection circuit.

According to another aspect of the present invention, an integrated circuit apparatus provided with a first input/output unit and a second input/output unit which respectively access elements to which electric power is supplied from power sources via different electric power supply lines includes an acquisition unit configured to acquire information whether electric power is supplied to the respective elements based on a command from the outside; a generation circuit configured to generate at least one of a command or data based on the command from the outside; a selection circuit configured to select an input/output unit corresponding to an element to which electric power is supplied from the first input/output unit and the second input/output unit based on the information acquired by the acquisition unit; and a control circuit configured to output the command and the data generated by the generation circuit to the element to which electric power is supplied, via the input/output unit selected by the selection circuit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

First Exemplary Embodiment

FIG. 1is a diagram illustrating an integrated circuit including a terminal control circuit according to an exemplary embodiment of the present invention. An ASIC101includes a terminal control circuit103. Elements108aand108bare connected with a terminal1via a common signal line. Elements109aand109bare connected with a terminal2via a common signal line. Thus, the ASIC (integrated circuit)101includes a plurality of input/output units which is the terminal (terminal group)1and the terminal (terminal group)2. In the present embodiment, data is transferred in a serial format.

The respective terminals1and2include a plurality (four) of terminals. The terminal1includes a terminal that outputs a clock signal, a terminal that inputs and outputs data, a terminal that outputs a flash signal, and a terminal that outputs a chip select signal. Here, in order to simplify description, only the terminal that inputs and outputs data is identified with a numeral104. The terminal2also includes a terminal that outputs a clock signal, a terminal that inputs and outputs data, and a terminal that outputs a chip select signal. Only the terminal that inputs and outputs data is identified with a numeral105.

Each of the above elements108a,108b,109a, and109bis connected with the ASIC101on a circuit board via the terminals1and2of the ASIC101. The elements108aand108b, and the elements109aand109bare connected to different power sources. That is, the elements108aand108b, and the elements109aand109bare connected to different power supply lines (power source system).

The elements108aand108bare supplied with a voltage VDD1(for example, 3.3 volts), and the elements109aand109bare supplied with a voltage VDD2(for example, 3.3 volts). The elements108aand108bare, for example, an EEPROM (memory). The ASIC101is connected to respective elements via a plurality of signal lines (for example, clock signal line, data line). The ASIC101outputs a chip select (CS) signal corresponding to the respective elements in order to selectively have access.

The ASIC101includes a terminal3(107) other than the terminals1and2. A signal input from the terminal107is connected to the terminal control circuit103. The terminal control circuit103is connected to a communication data generation circuit102, a configuration register106, terminals104and105other than the terminal107.

The communication data generation circuit102generates commands and data for communicating with the elements108a,108b,109a, and109b. The communication data generation circuit102includes a buffer (reception buffer) for holding data received from respective elements, and a buffer (transmission buffer) for holding commands and data which are transmitted to respective elements.

The terminal control circuit103further makes enable/disable setting of the terminals104and105, and input/output setting of the terminals104and105with the communication data generation circuit102based on information set by the configuration register106and information input from the terminals104,105and107. Furthermore, the terminal control circuit103sets an output level when a terminal is used as an output terminal.

As an example, a case will be described in which information (commands or instructions) input from the terminal107indicates that the voltage VDD1is supplied and the voltage VDD2is not supplied. In this case, the terminal control circuit103executes control so that the elements108aand108bto which the voltage VDD1is supplied are accessed.

On the other hand, a case will be described in which information (commands or instructions) input from the terminal107indicates that the voltage VDD2is supplied and the voltage VDD1is not supplied. The terminal control circuit103executes control so that the elements109aand109bto which the voltage VDD2is supplied are accessed. Thus, the terminal control circuit103acquires information from the outside via the terminal107and operates based on the acquired information.

FIG. 2is a diagram illustrating the internal configuration of the terminal control circuit (interface circuit)103included in the ASIC101and its connection with the outside.

The terminal control circuit103includes a plurality of selectors (selection circuits)202,203,204,205and206, and a control logic circuit208. The control logic circuit208operates based on the input212of the terminal107and the input211of the configuration register106. The control logic circuit208controls changeover of the selector202, the selector203, the selector204, the selector205, and the selector206.

The selector203and the selector204are connected to a terminal209(terminal104inFIG. 1). Similarly, the selector205and the selector206are connected to a terminal210(terminal105inFIG. 1).

The control logic circuit208controls changeover of the selectors202,203,204,205and206based on a signal input211, a signal input212, an input from the terminals209and210, or the combination thereof.

A signal output from the communication data generation circuit102is input to the selectors203and206.

The selectors203and206respectively switches an output state by a selection signal from the control logic circuit208. That is, the selectors203and206select the contents of output when in the state of output. The selectors203and206select any of a high level, a low level and an output based on data. For example, if the selector203selects a high level, a state of the terminal209becomes a high level. If the selector203selects a low level, a state of the terminal209becomes a low level. If the selector203selects an output based on data, a state of the terminal209(state of high level and state of low level) is changed based on the data and commands generated by the communication data generation circuit102. The function of the selector206is similar and an output state of the terminal210can be selected.

The selectors204and205switches input and output of the terminals209and210. The selectors204and205select an output state or an input state based on a selection signal from the control logic circuit208. Each selection signal from the control logic circuit208can be associated with each other or individually set. The settings are made by a signal211. The signal211is a signal corresponding to an output value of the configuration register106inFIG. 1.

When data is input from the terminal209, the data is transferred to the communication data generation circuit102via the selector202and stored in a reception buffer provided on the communication data generation circuit102. Similarly, when the data is input from the terminal210, the data is transferred to the communication data generation circuit102via the selector202.

Second Exemplary Embodiment

Next, a second exemplary embodiment will be described with reference toFIG. 3.

An ASIC301includes a terminal control circuit303, a communication data generation circuit302, a power source control circuit312, a configuration register306, and terminals304(terminal1),305(terminal2),307(terminal3),315(terminal4) and316(terminal5). Electric power source circuits313and314are connected to the ASIC301. The power source control circuit312instructs output/suspension of electric power supply to elements308a,308b,309a, and309b.310and311are lines for control signal. That is, the power source control circuit312is an electric power supply instruction circuit. In other words, the power source control circuit312instructs permission/prohibition of electric power supply to elements. Thus, the ASIC301is configured to independently control output of the voltage VDD1and the voltage VDD2.

The instruction of output/suspension of electric power supply is output to the electric power source circuit313via the terminal315and output to the electric power source circuit314via the terminal316. The contents of the instruction are transmitted to the terminal control circuit303. The terminal control circuit303makes a setting to the internal selectors and the communication data generation circuit302based on the instruction. The electric power source circuit313supplies the voltage VDD1to the elements308aand308b. The electric power source circuit314supplies the voltage VDD2to the elements309aand309b.

For example, if information input from the configuration register306is an instruction to access the element308a, the power source control circuit312instructs the electric power source circuit313to supply electric power. Thereafter, the terminal control circuit303makes a setting with respect to the terminal304so that the element308ais accessed. In this case, since the terminal control circuit303does not have an access to the terminal305, the terminal control circuit303makes a setting to the terminal305so that the terminal305is in an input state. Further, if information input from the configuration register306is an instruction to access the element309a, the power source control circuit312issues an instruction for power supply to the electric power source circuit314. Thereafter, the terminal control circuit103executes control so that the element309ais accessed.

Thus, the power source control circuit312makes a setting to enable a terminal corresponding to an element performing communication, to execute communication and further executes control so that electric power is supplied to the element.

Thus, the power source control circuit312notifies the terminal control circuit303that electric power supply has been executed. The terminal control circuit303sets a terminal which does not perform communication, to be in an input state.

By executing such control, an unnecessary signal is not transmitted to an element that does not perform communication, and a failure or a malfunction of an element is prevented.

Third Exemplary Embodiment

Next, a third exemplary embodiment of the present invention will be described. In the third exemplary embodiment, the terminal control circuit303(FIG. 3) determines whether electric power is supplied to an element based on a state input from a terminal.

For example, the terminal control circuit303detects the level of voltage of a communication signal from the terminal304(FIG. 3) and determines whether the voltage VDD1is supplied. That is, a level determination circuit provided on the terminal control circuit303is used. In this case, the terminal control circuit303determines whether electric power is supplied. If electric power is not supplied, the terminal control circuit303waits until electric power is supplied and then executes control to perform communication with the element308aor308b. As to the terminal305, the similar processing may be executed.

With reference toFIG. 4, the description made so far is put in order.FIG. 4illustrates one example of a signal input to the terminal control circuit303, and a state of the terminal304(terminal1) and the terminal305(terminal2) that the terminal control circuit303sets with the input signal. Information about the configuration register306is not described inFIG. 4.

A pattern1is a case in which the element308aor308bis used. In order to use the element308aor308b, the terminal control circuit303causes the power source control circuit312to make the signal310enable (permission). The terminal control circuit303connects the terminal304with the communication data generation circuit302. On the other hand, since the elements309aand309bare not used, the terminal control circuit303causes the power source control circuit312to make the signal311disenable (prohibition). The terminal control circuit303sets the terminal305to be in an input state. A failure or a malfunction of elements can be prevented by such a setting. A pattern3is a case in which the element309aor309bis used. That is, the pattern3is a case opposite to the pattern1. Thus, its processing is inverse.

A pattern2is a case in which the element308aor308bis used. However, the terminal control circuit303monitors a state of the terminal1(electric potential of VDD1) and has determined that the terminal1is not at a desired electric potential. It can be considered from this state that, for example, the element308aor308bdoes not work. Accordingly, the terminal control circuit303sets the terminal1to be in an input state.

A pattern4is a case in which the element309aor309bis used. However, the terminal control circuit303has determined that the terminal2(electric potential of VDD2) is not at a desired potential. It can be considered from this state that, for example, the element309aor309bdoes not work. Accordingly, the terminal control circuit303sets the terminal2to be in an input state.

A pattern5is a case in which the element308aor308bis used. In this case, the terminal control circuit303monitors a state of the terminal1. If the terminal control circuit303can determine that electric power is supplied to the element308aor308b, the terminal control circuit303connects the terminal1with the communication data generation circuit302.

A pattern6monitors states of the terminal1and the terminal2. If the terminal control circuit303determines that electric power is not supplied either to the elements308aand308b, or to the elements309aand309b, the terminal control circuit303sets the terminal1and the terminal2to be in an input state.

A pattern7is a case in which the element309aor309bis used. In this case, the terminal control circuit303monitors a state of the terminal2. If the terminal control circuit303can determine that electric power is supplied to the element309aor309b, the terminal control circuit303connects the terminal2with the communication data generation circuit302.

Fourth Exemplary Embodiment

FIG. 7is a perspective view illustrating a recording apparatus as an electronic apparatus to which an ASIC according to the above-described exemplary embodiment is applied.

InFIG. 7, a recording head704mounted on a carriage701includes discharge ports capable of discharging ink and an ink tank which contains ink. The discharge ports of the recording head704are mounted on the carriage701that faces downwardly to discharge ink and record an image onto a recording medium705located below. The recording head704is provided with an EEPROM (not shown).

The carriage701is movably supported along the axis direction by two guide axes702and703. The carriage701reciprocally scans a scan area including a recording area along a direction indicated by arrows Q1and Q2driven by a carriage motor (not shown). The direction of arrows Q1and Q2is a main scanning direction. After one main scanning is completed by the carriage701, a conveyance roller706conveys the recording medium705by a certain amount (distance corresponding to recording width of the recording head704) in a sub-scanning direction. The sub-scanning direction is a direction of an arrow P. Thus, recording of one page is executed by repeating the scan (operation) with the recording head704and the conveyance (operation) of the recording medium705. A platen707is shown inFIG. 7.

FIG. 8is a control block diagram illustrating the recording apparatus described inFIG. 7. A circuit block800includes the recording apparatus and a recording head. A CPU801controls operation of the recording apparatus. An ASIC802includes a block which generates a control signal for driving the recording head mounted on the recording apparatus and a control signal for driving a motor. For example, in the first exemplary embodiment, the CPU801outputs commands or instructions to the terminal3(numeral107). Alternatively, for example, the CPU801writes (store) commands or instructions to the configuration register106. These commands are a read command to read data stored in an EEPROM as described below or a write command to store (write) data in the EEPROM.

The recording apparatus includes EEPROMs803aand803b, and EEPROMs804aand804b. The recording apparatus also includes a carriage motor808, a conveyance motor809, and an alternating current/direct current (AC/DC) power source806for generating voltage from a commercial power source. A direct current to direct current (DC/DC) converter805receives electric power supply from the AC/DC power source806to generate a logic voltage.

The DC/DC converter805also includes a drive block for driving a motor which drives the carriage motor808and the conveyance motor809.

A drive circuit807drives a recording element mounted on the recording head. The EEPROMs803aand803b, and the drive circuit807are circuits which are mounted on the recording head.

When the recording apparatus is, for example, in an operable mode, the recording apparatus executes recording operation in parallel to an operation mode based on a predetermined event (commands and data are received from host apparatus or an operation is carried out in an operation panel mounted on recording apparatus). After the recording operation is completed, the recording apparatus proceeds to the operable mode.

For example, when the recording operation is not executed for a predetermined period (that is, if the recording apparatus is in the operable mode), the recording apparatus proceeds from the operable mode (operable state) to a standby mode (standby state). In this case, the DC/DC converter805suspends electric power supply to the EEPROMs804aand804b. The recording apparatus can reduce electric power consumption by executing such control.

In the standby mode, when the predetermined event takes place again (a predetermined phenomenon occurs), the recording apparatus proceeds to the operable mode (operable state). In the operable mode, the DC/DC converter805executes electric power supply to the EEPROMs804aand804b. Thus, the recording apparatus prepares for the recording operation.

Other Exemplary Embodiments

Elements to be connected to an ASIC may be a clock integrated circuit (IC) (real time clock).

Further, a format used for transferring data to elements which are connected to an ASIC is not limited to a serial format but may be data transfer using a parallel format.

InFIG. 1, a voltage to be supplied to the elements108aand108b, and a voltage to be supplied to the elements109aand109bare 3.3 volts respectively but may be a different voltage. For example, a voltage to be supplied to the elements108aand108bmay be 3.3 volts and a voltage to be supplied to the elements109aand109bmay be 5 volts.

Furthermore, a voltage value is not limited to the above voltages but may be, for example, 1.8 volts or 9 volts.

Further, proceeding from a standby mode to an operable mode is not limited to the above described condition.

Further, while as an electronic apparatus, a recording apparatus is described in the present exemplary embodiments, the present invention can be applied to an image reading apparatus or a portable terminal.

This application claims priority from Japanese Patent Application No. 2007-213827 filed Aug. 20, 2007, which is hereby incorporated by reference herein in its entirety.