DISPLAY APPARATUS

Provided is a display apparatus capable of stably applying an electrical signal to a gate electrode. The display apparatus includes substrate, an oxide semiconductor layer above the substrate, and including a first channel area, and a second channel area spaced from the first channel area, a first conductive layer between the substrate and the oxide semiconductor layer, and including a first gate electrode overlapping the first channel area, and a second conductive layer above the oxide semiconductor layer, and including a shielding layer overlapping the first channel area, and a second gate electrode overlapping the second channel area.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority, to and the benefit of, Korean Patent Application No. 10-2022-0024572, filed on Feb. 24, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

One or more embodiments relate to a display apparatus capable of stably applying an electrical signal to a gate electrode.

2. Description of the Related Art

Display apparatuses visually display data. Display apparatuses are used as displays of small products, such as mobile phones, or as displays of large products, such as televisions.

A display apparatus includes a display element and a pixel circuit including a transistor and a storage capacitor, and the display element is driven by the pixel circuit.

SUMMARY

A conventional display apparatus may have a problem in that a voltage that is different from a preset voltage is applied to a gate electrode due to a parasitic capacitance, or in that the voltage that is applied to the gate electrode may not be constantly maintained due to a parasitic capacitance.

One or more embodiments include a display apparatus capable of stably applying an electrical signal to a gate electrode. However, aspects of embodiments according to the disclosure are not limited thereto, and the above characteristics do not limit the scope of embodiments according to the disclosure.

Additional aspects will be set forth in portion in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

According to one or more embodiments, a display apparatus includes a substrate, an oxide semiconductor layer above the substrate, and including a first channel area, and a second channel area spaced from the first channel area, a first conductive layer between the substrate and the oxide semiconductor layer, and including a first gate electrode overlapping the first channel area, and a second conductive layer above the oxide semiconductor layer, and including a shielding layer overlapping the first channel area, and a second gate electrode overlapping the second channel area.

The shielding layer and the second gate electrode may include a same material and may have a same layer structure.

The display apparatus may further include a first insulating layer covering the first conductive layer, and between the first conductive layer and the oxide semiconductor layer, and a second insulating layer covering the oxide semiconductor layer, and between the oxide semiconductor layer and the second conductive layer, wherein the oxide semiconductor layer further includes a first connection area contacting the first channel area, and at least partially having different electrical properties from electrical properties of the first channel area, and a second connection area contacting the second channel area, and at least partially having different electrical properties from electrical properties of the second channel area, and wherein the second conductive layer further includes a first connection electrode electrically connected to the first connection area via a first contact hole defined by the second insulating layer, and a second connection electrode spaced from the first connection electrode, and electrically connected to the second connection area via a second contact hole defined by the first insulating layer and the second insulating layer.

The first insulating layer may cover the first conductive layer to correspond to an entire surface of the substrate, wherein the second insulating layer is between the first insulating layer and the second conductive layer outside the oxide semiconductor layer.

The second insulating layer may be below the second conductive layer.

The first connection electrode may be integrally formed with the shielding layer.

The first conductive layer may further include a scan line extending in a first direction.

The second conductive layer may further include a data line extending in a second direction crossing the first direction.

The first conductive layer may further include a connection line for electrically connecting the data line and the second connection electrode.

The first conductive layer may include a first capacitor electrode, wherein the oxide semiconductor layer includes a second capacitor electrode overlapping the first capacitor electrode, and wherein the second capacitor electrode has different electrical properties from electrical properties of the first channel area.

The display apparatus may further include a display element electrically connected to the second capacitor electrode, and including a pixel electrode, an emission layer, and an opposite electrode.

The second capacitor electrode may be directly in contact with the pixel electrode.

According to one or more embodiments, a display apparatus includes a substrate, an oxide semiconductor layer above the substrate, and including a first channel area, and a second channel area spaced from the first channel area, a first conductive layer between the substrate and the oxide semiconductor layer, and including a first gate electrode overlapping the first channel area, and a second gate electrode overlapping the second channel area, and a second conductive layer above the oxide semiconductor layer, and including a shielding layer overlapping the first channel area.

The first gate electrode and the second gate electrode may include a same material and have a same layer structure.

The display apparatus may further include a first insulating layer covering the first conductive layer, and between the first conductive layer and the oxide semiconductor layer, and a second insulating layer covering the oxide semiconductor layer, and between the oxide semiconductor layer and the second conductive layer, wherein the oxide semiconductor layer further includes a first connection area contacting the first channel area, and a second connection area contacting the second channel area, and wherein the second conductive layer further includes a first connection electrode electrically connected to the first connection area via a first contact hole defined by the second insulating layer, and a second connection electrode spaced from the first connection electrode, and electrically connected to the second connection area via a second contact hole defined by the second insulating layer.

The first connection electrode may be integrally formed with the shielding layer.

The second conductive layer may further include a scan line extending in a first direction.

The first conductive layer may further include a data line extending in a second direction crossing the first direction.

The second conductive layer may further include a connection line integrally formed with the second connection electrode, and electrically connected to the data line.

The display apparatus may further include a first connection metal layer above the first connection area, and corresponding to the first connection area, and a second connection metal layer above the second connection area, and corresponding to the second connection area.

The first conductive layer may include a first capacitor electrode, wherein the oxide semiconductor layer includes a second capacitor electrode overlapping the first capacitor electrode, and wherein the display apparatus further includes a capacitor metal layer above the second capacitor electrode, and corresponding to the second capacitor electrode.

The display apparatus may further include a display element electrically connected to the second capacitor electrode, and including a pixel electrode, an emission layer, and an opposite electrode.

The capacitor metal layer may be directly in contact with the pixel electrode.

These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, the claims, and the accompanying drawings.

DETAILED DESCRIPTION

Aspects of some embodiments of the present disclosure and methods of accomplishing the same may be understood more readily by reference to the detailed description of embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The described embodiments, however, may have various modifications and may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art, and it should be understood that the present disclosure covers all the modifications, equivalents, and replacements within the idea and technical scope of the present disclosure. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects of the present disclosure may not be described.

Unless otherwise noted, like reference numerals, characters, or combinations thereof denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof will not be repeated. Further, parts that are not related to, or that are irrelevant to, the description of the embodiments might not be shown to make the description clear.

Thus, the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. Additionally, as those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

It will be understood that when an element, layer, region, or component is referred to as being “formed on,” “on,” “connected to,” or “coupled to” another element, layer, region, or component, it can be directly formed on, on, connected to, or coupled to the other element, layer, region, or component, or indirectly formed on, on, connected to, or coupled to the other element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. In addition, this may collectively mean a direct or indirect coupling or connection and an integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being “electrically connected” or “electrically coupled” to another layer, region, or component, it can be directly electrically connected or coupled to the other layer, region, and/or component or intervening layers, regions, or components may be present. However, “directly connected/directly coupled,” or “directly on,” refers to one component directly connecting or coupling another component, or being on another component, without an intermediate component. Meanwhile, other expressions describing relationships between components, such as “between,” “immediately between” or “adjacent to” and “directly adjacent to” may be construed similarly. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure. The description of an element as a “first” element may not require or imply the presence of a second element or other elements. The terms “first”, “second”, etc. may also be used herein to differentiate different categories or sets of elements. For conciseness, the terms “first”, “second”, etc. may represent “first-category (or first-set)”, “second-category (or second-set)”, etc., respectively.

FIG.1is a schematic plan view of a portion of a display apparatus1according to one or more embodiments, andFIG.2is a schematic cross-sectional view of a portion of the display apparatus1according to one or more embodiments.

As shown inFIG.1, the display apparatus1may include a display area DA in which a plurality of pixels P are arranged, and a peripheral area PA located outside the display area DA. The peripheral area PA may entirely surround the display area DA.

The display area DA may have the shape of a polygon including a quadrangle, as shown inFIG.1. For example, the display area DA may have a rectangular shape in which a horizontal length is greater than a vertical length, a rectangular shape in which a horizontal length is less than a vertical length, or a square shape. Alternatively, the display area DA may have any of various shapes, such as an oval or a circle.

As shown inFIG.2, the display apparatus1may include a light-emitting panel10and a filter panel20stacked on each other. The light-emitting panel10may include a plurality of display elements DPE, and each of the display elements DPE is electrically connected to a circuit PC (hereinafter, referred to as a pixel circuit PC). The display elements DPE and the pixel circuits PC may be arranged in the display area DA.

The display area DA may provide an image (e.g., predetermined image) by using light of the display elements DPE. For example, blue light LB emitted by the display elements DPE may be converted into red light LR and green light LG while passing through the filter panel20, or may pass through the filter panel20without being converted. The display apparatus1may provide an image (e.g., predetermined image) by using light that is converted by the filter panel20or that is transmitted by the filter panel20without being converted, for example, the red light LR, the green light LG, and the blue light LB.

The peripheral area PA is a non-display area that provides no images, and may surround the entirety of the display area DA. A driver or a main power line for providing an electrical signal or power to the pixel circuits PC may be arranged in the peripheral area PA. The peripheral area PA may include a pad that is an area capable of being electrically connected to an electronic device or a printed circuit board (PCB).

FIG.3is an equivalent circuit diagram illustrating a display element DPE included in a light-emitting panel and a pixel circuit PC connected to the display element DPE, according to one or more embodiments. As shown inFIG.3, the display element DPE, for example, an organic light-emitting diode OLED, may be electrically connected to the pixel circuit PC. In detail, a pixel electrode of the organic light-emitting diode OLED may be electrically connected to the pixel circuit PC, and an opposite electrode of the organic light-emitting diode OLED may be electrically connected to a common voltage line VSL providing a common power supply voltage ELVSS. The organic light-emitting diode OLED may emit light with a brightness corresponding to a current amount provided by the pixel circuit PC.

The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. Each of the first transistor T1, the second transistor T2, and the third transistor T3may be an oxide semiconductor thin-film transistor including a semiconductor layer formed of an oxide semiconductor, or may be a silicon semiconductor thin-film transistor including a semiconductor layer formed of polysilicon.

The first transistor T1may be a driving transistor. One connection electrode of the first transistor T1may be electrically connected to the pixel electrode of the organic light-emitting diode OLED, and the other connection electrode of the first transistor T1may be electrically connected to a driving voltage line VDL that supplies a driving power supply voltage ELVDD. A first gate electrode of the first transistor T1may be electrically connected to a first node N1. The first transistor T1may control a current amount flowing through the organic light-emitting diode OLED from the driving power supply voltage ELVDD in accordance with a voltage of the first node N1.

The second transistor T2may be a switching transistor. One connection electrode of the second transistor T2may be electrically connected to a data line DL, and the other connection electrode of the second transistor T2may be electrically connected to the first node N1. A second gate electrode of the second transistor T2may be electrically connected to a scan line SL. The second transistor T2may be turned on when a scan signal is supplied to the scan line SL, and may electrically connect the data line DL to the first node N1.

The third transistor T3may be an initialization transistor and/or a sensing transistor. One connection electrode of the third transistor T3may be electrically connected to an initialization-sensing line ISL, and the other connection electrode of the third transistor T3may be electrically connected to a second node N2. A third gate electrode of the third transistor T3may be electrically connected to a control line CL.

The third transistor T3may be turned on when a control signal is supplied to the control line CL, and may electrically connect the initialization-sensing line ISL to the second node N2. According to some embodiments, the third transistor T3may be turned on according to a signal received through the control line CL to initialize the pixel electrode of the organic light-emitting diode OLED by using an initializing voltage from the initialization-sensing line ISL. According to some embodiments, the third transistor T3may be turned on when the control signal is supplied to the control line CL, and may sense property information, or characteristic information, of the organic light-emitting diode OLED. The third transistor T3may function both as the above-described initialization transistor, and as the above-described sensing transistor, or may include one of the two functions. According to some embodiments, when the third transistor T3includes the function as the initialization transistor, the initialization-sensing line ISL may be referred to as an initializing voltage line, and, when the third transistor T3includes the function as the sensing transistor, the initialization-sensing line ISL may be referred to as a sensing line. An initialization operation and a sensing operation of the third transistor T3may be individually conducted or may be concurrently or substantially simultaneously conducted. In other words, the third transistor T3may be an initialization transistor and/or a sensing transistor. For convenience of description, a case where the third transistor T3has both the function of the initialization transistor and the function of the sensing transistor will be described in detail.

The storage capacitor Cst may be connected between the first node N1and the second node N2. For example, one capacitor electrode of the storage capacitor Cst may be electrically connected to the first gate electrode of the first transistor T1, and the other capacitor electrode of the storage capacitor Cst may be electrically connected to the pixel electrode of the organic light-emitting diode OLED.

InFIG.3, the pixel circuit PC includes three transistors and one storage capacitor. However, according to one or more other embodiments, the number of transistors or the number of storage capacitors may vary according to a design of the pixel circuit PC.

Although the display element DPE includes the organic light-emitting diode OLED including an organic material inFIG.3, embodiments are not limited thereto. According to one or more other embodiments, the display element DPE may be an inorganic light-emitting diode including an inorganic material. The inorganic light-emitting diode may include a PN diode including materials based on an inorganic material semiconductor. When a voltage is applied to the PN junction diode in a forward direction, holes and electrons are injected, and energy generated by recombination of the holes and the electrons is converted into light energy to thereby emit light of a color (e.g., predetermined color). The aforementioned inorganic light-emitting diode may have a width of several to several hundreds of micrometers. According to some embodiments, the aforementioned inorganic light-emitting diode may be referred to as a micro LED.

FIG.4is a schematic layout diagram illustrating respective locations of the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst in pixels included in the display apparatus1according to one or more embodiments, andFIGS.5through8are schematic layout diagrams illustrating respective components of the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst for each layer of the display apparatus1ofFIG.4.FIG.9Ais a schematic cross-sectional view illustrating a cross-section taken along the line I-I′ of the display apparatus1ofFIG.4, andFIG.10is a schematic cross-sectional view illustrating a cross-section taken along the line II-II′ of the display apparatus1ofFIG.4.

As shown in these drawings, the display apparatus1may include a first pixel, a second pixel, and a third pixel adjacent to one another. Thus, the first pixel may include a first pixel circuit PC1, the second pixel may include a second pixel circuit PC2, and the third pixel may include a third pixel circuit PC3. As shown inFIG.4, the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3may be located adjacent to one another. The light-emitting panel10of the display apparatus1may include pixel circuits PC (such as, the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3), the scan line SL, the control line CL, the data line DL, the initialization-sensing line ISL, the driving voltage line VDL, and the common voltage line VSL.

As described above, the first pixel may include the first pixel circuit PC1, the second pixel may include the second pixel circuit PC2, and the third pixel may include the third pixel circuit PC3. In other words the first pixel circuit PC1may drive a first display element DPE1of the first pixel, the second pixel circuit PC2may drive a second display element of the second pixel, and the third pixel circuit PC3may drive a third display element of the third pixel.

Each of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3may include three transistors and one storage capacitor. In detail, the first pixel circuit PC1may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. Because the second pixel circuit PC2and the third pixel circuit PC3are similar to the first pixel circuit PC1, the first pixel circuit PC1will now be focused on and described in detail for convenience of explanation.

A buffer layer including silicon oxide, silicon nitride, or silicon oxynitride may be positioned on a substrate100. The buffer layer may function to increase the smoothness of an upper surface of the substrate100, and the buffer layer may reduce or prevent diffusion of metal atoms or impurities from the substrate100to an oxide semiconductor layer300(seeFIG.6) located on the metal atoms or the impurities. The buffer layer may be a single layer or multi-layer including silicon oxide, silicon nitride, or silicon oxynitride.

A first conductive layer200shown inFIG.5may be located on the substrate100. The first conductive layer200may include the scan line SL and the control line CL each extending in a first direction (for example, an x-axis direction). Because the scan line SL may be electrically connected to a second gate electrode GE2(seeFIG.7), an electrical signal may be applied to the second gate electrode GE2via the scan line SL. The first conductive layer200may include a connection line CNL extending in the first direction (for example, the x-axis direction), and the connection line CNL may be electrically connected to the data line DL (seeFIG.7).

The first conductive layer200may further include a first gate electrode GE1and a first capacitor electrode CE1. The first gate electrode GE1and the first capacitor electrode CE1may be integrated. In other words, the first gate electrode GE1and the first capacitor electrode CE1may be integrally formed with each other through the same process. Thus, the first gate electrode GE1may include the same material as the first capacitor electrode CE1. The first gate electrode GE1may have the same layer structure as the first capacitor electrode CE1. For example, when the first gate electrode GE1has a double-layer structure, the first capacitor electrode CE1may also have a double-layer structure formed of the same material as that used to form the first gate electrode GE1. Although the first gate electrode GE1and the first capacitor electrode CE1are integrated inFIG.5, embodiments are not limited thereto. For example, the first capacitor electrode CE1may be arranged apart from the first gate electrode GE1.

The first conductive layer200may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first conductive layer200may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first conductive layer200may have a multi-layered structure. For example, the first conductive layer200may have a double-layer structure of Mo/Al or a three-layered structure of Mo/Al/Mo.

A first insulating layer110ofFIG.9Amay cover the first conductive layer200and may be located on (e.g., above) the substrate100. The first insulating layer110may include an insulating material. For example, the first insulating layer110may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

The oxide semiconductor layer300shown inFIG.6may be located on the first insulating layer110. The oxide semiconductor layer300may include a first semiconductor pattern SP1and a second semiconductor pattern SP2. The first semiconductor pattern SP1may include a first channel area CHA1, a third channel area CHA3, and a second capacitor electrode CE2, and the second semiconductor pattern SP2may include a second channel area CHA2. The first channel area CHA1may overlap the first gate electrode GE1.

In detail, the first semiconductor pattern SP1may further include a first-first connection area CNA1-1and a second-first connection area CNA1-2, and the first channel area CHA1may be between the first-first connection area CNA1-1and the second-first connection area CNA1-2. For example, the first-first connection area CNA1-1may contact one side of the first channel area CHA1, the second-first connection area CNA1-2may contact the other side of the first channel area CHA1, and the first channel area CHA1may be integrated with the first-first connection area CNA1-1and the second-first connection area CNA1-2.

The first-first connection area CNA1-1and the second-first connection area CNA1-2have different electrical properties from those of the first channel area CHA1, and thus may respectively correspond to a source region and a drain region. In detail the first channel area CHA1may allow a current to flow only when a voltage is applied to a conductive layer located above or below the first channel area CHA1. However, even when a voltage is not applied to conductive layers located above or below the first-first connection area CNA1-1and the second-first connection area CNA1-2, a current may flow in the first-first connection area CNA1-1and the second-first connection area CNA1-2. In other words, a resistance of the first-first connection area CNA1-1and a resistance of the second-first connection area CNA1-2, when no voltages are applied to the conductive layers located above or below the first-first connection area CNA1-1and the second-first connection area CNA1-2, may be less than a resistance of the first channel area CHA1when no voltages are applied to the conductive layer located above or below the first channel area CHA1.

The first semiconductor pattern SP1may further include a third connection area CNA3, and the third channel area CHA3may be located adjacent to the third connection area CNA3. For example, the third channel area CHA3may be integrated with the third connection area CNA3. The third connection area CNA3has different electrical properties from those of the third channel area CHA3, and may correspond to a source region or a drain region. In detail, the third channel area CHA3may allow a current to flow when a voltage is applied to a conductive layer located above or below the third channel area CHA3. However, the third connection area CNA3may allow a current to flow even when no voltages are applied to a conductive layer located above or below the third connection area CNA3. In other words, a resistance of the third connection area CNA3, when no voltages are applied to the conductive layer located above or below the third connection area CNA3, may be less than a resistance of the third channel area CHA3when no voltages are applied to the conductive layer located above or below the third channel area CHA3.

The second capacitor electrode CE2may be arranged between the first-first connection area CNA1-1and the third channel area CHA3. For example, the first-first connection area CNA1-1may contact one side of the second capacitor electrode CE2, the third channel area CHA3may contact the other side of the second capacitor electrode CE2, and the second capacitor electrode CE2may be integrated with the first-first connection area CNA1-1and the third channel area CHA3. The first-first connection area CNA1-1may correspond to a portion of the second capacitor electrode CE2. In other words, a portion of a portion of the second capacitor electrode CE2that does not overlap the first capacitor electrode CE1may correspond to the first-first connection area CNA1-1of the first transistor T1. The second capacitor electrode CE2may have different electrical properties from electrical properties of the first channel area CHA1. In contrast with the electrical properties of the first channel area CHA1, the second capacitor electrode CE2may allow a current to flow even when no voltages are applied to a conductive layer located above or below the second capacitor electrode CE2. In other words, a resistance of the second capacitor electrode CE2, when no voltages are applied to the conductive layer located above or below the second capacitor electrode CE2, may be less than the resistance of the first channel area CHA1when no voltages are applied to the conductive layer located above or below the first channel area CHA1. Thus, the second capacitor electrode CE2may function as one electrode of the storage capacitor Cst.

The second semiconductor pattern SP2may further include a first-second connection area CNA2-1and a second-second connection area CNA2-2, and the second channel area CHA2may be between the first-second connection area CNA2-1and the second-second connection area CNA2-2. For example, the first-second connection area CNA2-1may contact one side of the second channel area CHA2, the second-second connection area CNA2-2may contact the other side of the second channel area CHA2, and the second channel area CHA2may be integrated with the first-second connection area CNA2-1and the second connection area CNA2-2.

The first-second connection area CNA2-1and the second-second connection area CNA2-2have different electrical properties from those of the second channel area CHA2, and thus may respectively correspond to a source region and a drain region. In detail, the second channel area CHA2may allow a current to flow only when a voltage is applied to a conductive layer located above or below the second channel area CHA2. However, even when a voltage is not applied to conductive layers located above or below the first-second connection area CNA2-1and the second-second connection area CNA2-2, a current may flow in the first-second connection area CNA2-1and the second-second connection area CNA2-2. In other words, a resistance of the first-second connection area CNA2-1and a resistance of the second-second connection area CNA2-2, when no voltages are applied to the conductive layers located above or below the first-second connection area CNA2-1and the second-second connection area CNA2-2, may be less than a resistance of the second channel area CHA2when no voltages are applied to the conductive layer located above or below the second channel area CHA2.

The oxide semiconductor layer300may include an oxide semiconductor. For example, the oxide semiconductor may include Zn oxide, In—Zn oxide, or Ga—In—Zn oxide, as a Zn oxide-based material. Alternatively, the oxide semiconductor may include an In-Ga—Zn-O (IGZO), In—Sn—Zn—O (ITZO), or In—Ga—Sn—Zn—O (IGTZO) containing metals, such as In, Ga, and Sn, in ZnO.

The first-first connection area CNA1-1, the second-first connection area CNA1-2, the first-second connection area CNA2-1, the second-second connection area CNA2-2, the third connection area CNA3, and the second capacitor electrode CE2may be areas in which impurities are added to a layer formed of an oxide semiconductor. In other words, the first-first connection area CNA1-1, the second-first connection area CNA1-2, the first-second connection area CNA2-1, the second-second connection area CNA2-2, the third connection area CNA3, and the second capacitor electrode CE2may be doped areas. Thus, the first-first connection area CNA1-1, the second-first connection area CNA1-2, the first-second connection area CNA2-1, the second-second connection area CNA2-2, the third connection area CNA3, and the second capacitor electrode CE2may have different electrical properties from electrical properties of an undoped oxide semiconductor, for example, the first channel area CHA1, the second channel area CHA2, and the third channel area CHA3. In other words, a resistance of a doped area of the oxide semiconductor layer300, when no voltages are applied to a conductive layer located above or below the doped area of the oxide semiconductor layer300, may be less than a resistance of an undoped area of the oxide semiconductor layer300when no voltages are applied to the conductive layer located above or below the undoped area of the oxide semiconductor layer300.

A second insulating layer120ofFIG.9Amay cover the oxide semiconductor layer300and may be located on the first insulating layer110. The second insulating layer120may include an insulating material. The second insulating layer120may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

A second conductive layer400shown inFIG.7may be located on the second insulating layer120. The second conductive layer400may include the data line DL, the initialization-sensing line ISL, the driving voltage line VDL, and the common voltage line VSL. The data line DL, the initialization-sensing line ISL, the driving voltage line VDL, and the common voltage line VSL may each extend in a second direction (for example, a y-axis direction) intersecting the first direction. The data line DL may include a first data line DL1, a second data line DL2, and a third data line DL3. The first data line DL1, the second data line DL2, and the third data line DL3may supply a data signal to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3, respectively.

The second conductive layer400may further include a gate wire GL, the second gate electrode GE2, and a third gate electrode GE3. The gate wire GL may be electrically connected to the scan line SL included in the first conductive layer200. In detail, the gate wire GL may be electrically connected to the scan line SL through a scan line contact hole H-SL formed in the first insulating layer110and the second insulating layer120.

The second gate electrode GE2may overlap the second channel area CHA2. The second gate electrode GE2may correspond to a portion of the gate wire GL. In other words, portions of the gate wire GL that overlap the oxide semiconductor layer300may correspond to respective gate electrodes of the respective second transistors T2of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3, respectively. The third gate electrode GE3may overlap the third channel area CHA3. The third gate electrode GE3may correspond to a portion of the gate wire GL. The portions of the gate wire GL that overlap the oxide semiconductor layer300may correspond to respective gate electrodes of the respective third transistors T3of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3, respectively. The gate wire GL may extend from the second direction (for example, the y-axis direction) between the driving voltage line VDL and the data line DL.

The second conductive layer400may further include a shielding layer SDL, a first-first connection electrode CNE1-1, a second-first connection electrode CNE1-2, a first-second connection electrode CNE2-1, a second-second connection electrode CNE2-2, and a third connection electrode CNE3. The shielding layer SDL may have a shape corresponding to the first channel area CHA1of the first transistor T1to protect the first channel area CHA1overlapping the shielding layer SDL.

In detail, the first transistor T1may have a bottom gate structure in which the first gate electrode GE1is located below the first channel area CHA1. During a metallization process of the display apparatus1to be described later, the second gate electrode GE2located above the second channel area CHA2may function as a mask that covers the second channel area CHA2such that the second channel area CHA2is not metalized, and the third gate electrode GE3located above the third channel area CHA3may function as a mask that covers the third channel area CHA3such that the third channel area CHA3is not metalized. However, the first gate electrode GE1may not function as a mask because the first gate electrode GE1is located below the first channel area CHA1, and the shielding layer SDL located above the first channel area CHA1may function as a mask that covers the first channel area CHA1such that the first channel area CHA1is not metalized. In other words, the shielding layer SDL may protect the first channel area CHA1. As used herein, “X is metalized” means that X including an oxide semiconductor has different electrical properties through plasma treatment. In other words, “X is metalized” means that the resistance of X after plasma treatment is lower than that of X before plasma treatment.

The first-first connection electrode CNE1-1may be connected to the first-first connection area CNA1-1of the first transistor T1through a first-first contact hole H1-1formed in the second insulating layer120. The first-first connection electrode CNE1-1may be integrated with the shielding layer SDL. Thus, the shielding layer SDL may be connected to the first-first connection electrode CNE1-1, and accordingly the first transistor T1may have a source-sink structure. In other words, a source voltage may be applied to the shielding layer SDL located above the first channel area CHA1of the first transistor T1.

Although the first-first connection electrode CNE1-1is integrated with the shielding layer SDL inFIG.7, embodiments are not limited thereto. The second-first connection electrode CNE1-2may be connected to the second-first connection area CNA1-2of the first transistor T1through a second-first contact hole H1-2formed in the second insulating layer120. The second-first connection electrode CNE1-2may correspond to a portion of the driving voltage line VDL.

The first-second connection electrode CNE2-1may be connected to the first-second connection area CNA2-1of the second transistor T2through a first-second contact hole H2-1formed in the first insulating layer110and the second insulating layer120. The second-second connection electrode CNE2-2may be connected to the second-second connection area CNA2-2of the second transistor T2through a second-second contact hole H2-2formed in the first insulating layer110and the second insulating layer120. The third connection electrode CNE3may be connected to the third connection area CNA3of the third transistor T3through a third contact hole H3formed in the second insulating layer120.

The second conductive layer400may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second conductive layer400may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second conductive layer400may have a multi-layered structure. For example, the second conductive layer400may have a double-layer structure of Mo/Al or a three-layered structure of Mo/Al/Mo.

A third insulating layer130ofFIG.9Amay cover the second conductive layer400and may be located on (e.g., above) the second insulating layer120. The third insulating layer130may include an insulating material. The third insulating layer130may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. A fourth insulating layer140ofFIG.9Amay be located on the third insulating layer130to cover the third insulating layer130. The fourth insulating layer140may include an organic insulating material. For example, the fourth insulating layer140may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, a polymer derivative having a phenol-based group, an acryl-based polymer, an imide-based polymer, an acryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

The first display element DPE1ofFIG.9A, for example, an organic light-emitting diode OLED, may be located on the fourth insulating layer140. The first display element DPE1may include a pixel electrode510ofFIG.9A, an intermediate layer520ofFIG.9Aincluding an emission layer, and an opposite electrode530ofFIG.9A.

A pixel electrode510as shown inFIG.8may be located on or above the fourth insulating layer140. The pixel electrode510may be electrically connected to the second capacitor electrode CE2through a capacitor electrode contact hole H-CE formed in the third insulating layer130and the fourth insulating layer140. Because the first display element DPE1includes the pixel electrode510, the first display element DPE1may be electrically connected to the second capacitor electrode CE2included in the oxide semiconductor layer300.

A pixel defining layer may be arranged on the fourth insulating layer140. The pixel defining layer may reduce or prevent the likelihood of an electric arc or the like occurring on an edge of the pixel electrode510by increasing a distance between the edge of the pixel electrode510and an opposite electrode530over the pixel electrode510. The pixel defining layer may be formed of at least one organic insulating material from among polyimide, polyamide, acryl resin, benzocyclobutene, and a phenolic resin, by using a method, such as spin coating.

At least a portion of the intermediate layer520of the first display element DPE1may be located within an opening formed by the pixel defining layer. An emission region of the first display element DPE1may be defined by the opening.

The intermediate layer520may include the emission layer. The emission layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emission layer may include a low molecular organic material or a high molecular organic material, and one or more functional layers, such as a hole transport layer (HTL), an hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL), may be further arranged below and above the emission layer.

The emission layer may have a shape patterned in correspondence with each pixel electrode510. Various modifications may be made to the emission layer. For example, a layer other than the emission layer included in the intermediate layer520may be integrated to cover a plurality of pixel electrodes510.

The opposite electrode530may be a light-transmissive electrode or a reflective electrode. For example, the opposite electrode530may be a transparent or semi-transparent electrode, and may include a metal thin film having a small work function, including Li, Ca, LiF, Al, Ag, Mg, or a combination thereof. The opposite electrode530may further include a transparent conductive oxide (TCO) layer of, for example, ITO, IZO, ZnO, or In2O3, located on the metal thin film. The opposite electrode530may be integrated to cover the entire surface of the display area DA, and may be located over the intermediate layer520and the pixel defining layer.

FIG.9Ais a schematic cross-sectional view taken along the line I-I′ of the display apparatus1ofFIG.4. As shown inFIG.9A, the first gate electrode GE1may be located below the oxide semiconductor layer300. In other words, the first transistor T1may have a bottom gate structure. Accordingly, the first insulating layer110may cover the first gate electrode GE1.

When a driving transistor has a top gate structure in which a gate electrode is located above a semiconductor layer, a pixel of a display apparatus may include an unwanted parasitic capacitance. As in the second pixel circuit PC2of the second pixel ofFIG.4, a portion of a pixel electrode of another pixel of a display apparatus may be located on a pixel circuit of one pixel of the display apparatus. When a driving transistor has a top gate structure, a portion of a pixel electrode of another pixel may be located on a gate electrode of a driving transistor of one pixel. In this case, a parasitic capacitance may be formed between the gate electrode of the driving transistor of the one pixel and the pixel electrode of the other pixel. The parasitic capacitance may affect a voltage of the gate electrode of the one pixel. In other words, even when a voltage different from a preset voltage is applied to the gate electrode of the driving transistor of the one pixel or the preset voltage is applied, the voltage of the gate electrode of the driving transistor may not be maintained constant. Accordingly, the organic light-emitting diode OLED may emit light of unintended brightness, and thus may not display a high-quality image.

However, in the case of the display apparatus1according to one or more embodiments, the driving transistor, for example, the first gate electrode GE1, may be located below the oxide semiconductor layer300, and the first insulating layer110may cover the first gate electrode GE1. Thus, even when the pixel electrode510of the other pixel is located on the pixel circuit PC of the one pixel of the display apparatus1, a parasitic capacitance may not be formed between the first gate electrode GE1of the first transistor T1of the one pixel and the pixel electrode510of the other pixel. Thus, a voltage of the first gate electrode GE1may not be affected by the parasitic capacitance, or an influence of the parasitic capacitance upon the voltage of the first gate electrode GE1may be reduced or minimized. In other words, an electrical signal may be stably applied to the first gate electrode GE1. Thus, brightness of the organic light-emitting diode OLED may be appropriately controlled.

A reason why a cross-section as shown inFIG.9Ais obtained will be described with reference toFIGS.9B,9C, and9D.FIGS.9B,9C, and9Dare schematic cross-sectional views of a process of manufacturing a portion of the display apparatus1ofFIG.4.

First, as shown inFIG.9B, the first conductive layer200including the first gate electrode GE1and the first capacitor electrode CE1may be formed above the substrate100, and the first insulating layer110may be formed to cover the first conductive layer200. Because the first insulating layer110covers the first conductive layer200to correspond to the entire surface of the substrate100, the first insulating layer110may cover the first gate electrode GE1and the first capacitor electrode CE1included in the first conductive layer200. The first semiconductor pattern SP1including the first channel area CHA1, the first-first connection area CNA1-1, and the second-first connection area CNA1-2may be formed above the first insulating layer110. The second insulating layer120may be formed above the first semiconductor pattern SP1. Thereafter, as shown inFIG.9B, the first-first contact hole H1-1and the second-first contact hole H1-2penetrating through the second insulating layer120may be formed. The first-first contact hole H1-1may be formed to overlap the first-first connection area CNA1-1in a plan view, and the second-first contact hole H1-2may be formed to overlap the second-first connection area CNA1-2in a plan view.

Then, as shown inFIG.9C, after a preliminary second conductive layer may be formed on the second insulating layer120to cover the second insulating layer120, the second conductive layer400may be patterned. Thus, the second conductive layer400including the first-first connection electrode CNE1-1and the second-first connection electrode CNE1-2may be formed. In this case, the first-first contact hole H1-1and the second-first contact hole H1-2penetrating through the second insulating layer120may be filled with a portion of the second conductive layer400. Thus, the first-first connection electrode CNE1-1may be electrically connected to the first-first connection area CNA1-1via the first-first contact hole H1-1, and the second-first connection electrode CNE1-2may be electrically connected to the second-first connection area CNA1-2via the second-first contact hole H1-2.

Then, as shown inFIG.9D, a portion of the second insulating layer120that includes no second conductive layers400formed thereon may be removed. In other words, the second insulating layer120may be located only below the second conductive layer400. Thus, the second insulating layer120may exist below the shielding layer SDL, the first-first connection electrode CNE1-1, and the second-first connection electrode CNE1-2, and there may be no second insulating layers120existing below the outside of the first-first connection electrode CNE1-1and the outside of the second-first connection electrode CNE1-2.

Thus,FIGS.9B and9Cillustrate the first-first contact hole H1-1and the second-first contact hole H1-2in shapes, such as holes in a plan view. However, inFIG.9D, portions of the second insulating layer120on the outside of the first-first connection electrode CNE1-1and the outside of the second-first connection electrode CNE1-2are removed, and thus the first-first contact hole H1-1and the second-first contact hole H1-2do not appear in shapes, such as holes in a plan view. Accordingly, the display apparatus1according to one or more embodiments may have a cross-section as inFIG.9A.

FIG.10is a schematic cross-sectional view taken along the line II-II′ of the display apparatus1ofFIG.4. As shown inFIG.10, the first-second connection electrode CNE2-1of the second transistor T2may be electrically connected to the first-second connection area CNA2-1of the second transistor T2. The first-second connection electrode CNE2-1of the second transistor T2may be electrically connected to the connection line CNL.

In detail, the first-second connection electrode CNE2-1may be connected to the connection line CNL through the first-second contact hole H2-1formed in the first insulating layer110and the second insulating layer120. Because the first-second connection electrode CNE2-1may be connected to the first-second connection area CNA2-1, the first-second connection area CNA2-1and the connection line CNL may be connected to each other via the first-second connection electrode CNE2-1. In other words, the first-second connection electrode CNE2-1may serve as a bridge that connects the first-second connection area CNA2-1to the connection line CNL. Because the connection line CNL is electrically connected to the first data line DL1via a data line contact hole H-DL, the first-second connection electrode CNE2-1of the second transistor T2may be electrically connected to the first data line DL1.

FIGS.11through14are schematic cross-sectional views illustrating a process of manufacturing a portion of the display apparatus1ofFIG.4. In detail,FIGS.11through14are schematic cross-sectional views illustrating a process of manufacturing the connection line CNL, the first-second connection area CNA2-1, and the first-second connection electrode CNE2-1of the display apparatus1ofFIG.1.

First, as shown inFIG.11, the connection line CNL and the first capacitor electrode CE1may be formed above the substrate100, and the first insulating layer110may be formed to cover the connection line CNL and the first capacitor electrode CE1. Because the first insulating layer110covers the first conductive layer200to correspond to the entire surface of the substrate100, the first insulating layer110may cover the connection line CNL and the first capacitor electrode CE1included in the first conductive layer200. The second semiconductor pattern SP2including the second channel area CHA2, the first-second connection area CNA2-1, and the second-second connection area CNA2-2may be formed above the first insulating layer110. The second insulating layer120may be formed above the second semiconductor pattern SP2.

Then, as shown inFIG.12, the first-second contact hole H2-1, the second-second contact hole H2-2, and the data line-contact hole H-DL penetrating through the first insulating layer110and the second insulating layer120may be formed. The first-second contact hole H2-1may be formed to overlap the first-second connection area CNA2-1and the connection line CNL in a plan view. In detail, a portion of the first-second contact hole H2-1may overlap the first-second connection area CNA2-1in a plan view, and the entirety of the first-second contact hole H2-1may overlap the connection line CNL in a plan view. The second-second contact hole H2-2may be formed to overlap the second-second connection area CNA2-2and the first capacitor electrode CE1in a plan view. The data line-contact hole H-DL may be formed to overlap the connection line CNL in a plan view.

The first-second connection area CNA2-1may include the first area A1and the second area A2, the first area A1may be a portion of the first-second connection area CNA2-1exposed by the first-second contact hole H2-1, and the second area A2may be a portion of the first-second connection area CNA2-1not exposed by the first-second contact hole H2-1. The first area A1exposed by the first-second contact hole H2-1may be metalized via plasma processing or the like. In detail, the first-second contact hole H2-1may be formed by using plasma, and the first area A1of the first-second connection area CNA2-1may be plasma-processed during formation of the first-second contact hole H2-1.

For example, plasma processing may be chemically or materially modifying the surface of a material due to collision of high energy particles placed in a plasma state with the surface of the material. In the plasma processing, at least one gas selected from the group consisting of hydrogen gas, argon gas, helium gas, xenon gas, nitrogen gas, nitrogen oxide gas, oxygen gas, and a mixed gas thereof may be used.

When an oxide semiconductor is plasma-processed, the oxide semiconductor is reduced, and thus oxygen defects included in the oxide semiconductor may be induced and oxygen vacancy may increase. In an oxide semiconductor having an increased oxygen vacancy, the concentration of carriers is increased, and as a result, the concentration of a threshold voltage, which is a voltage through which electricity is passed from among semiconductor characteristics, may shift in a negative direction. This may mean that the oxide semiconductor is metalized to conduct electricity well. In other words, electrical characteristics of the oxide semiconductor before plasma processing may be different from those of the oxide semiconductor after plasma processing. For example, the resistance of the oxide semiconductor after plasma processing may be lower than the resistance of the oxide semiconductor before plasma processing. Thus, because the first-second contact hole H2-1is formed by using plasma, the first area A1of the first-second connection area CNA2-1exposed by the first-second contact hole H2-1may be plasma-processed. Accordingly, the first area A1may be metalized.

Then, as shown inFIG.13, the second gate electrode GE2, the first-second connection electrode CNE2-1, the second-second connection electrode CNE2-2, the initialization-sensing line ISL, and the data line DL may be formed on the second insulating layer120. In detail, a portion of the first-second connection electrode CNE2-1may contact the first area A1of the first-second connection area CNA2-1, and a portion of the first-second connection electrode CNE2-1may contact the connection line CNL. Accordingly, as described above, the first-second connection electrode CNE2-1may serve as a bridge that connects the first-second connection area CNA2-1to the connection line CNL. The first-second connection electrode CNE2-1may not overlap the second area A2of the first-second connection area CNA2-1in a plan view.

The above-described shielding layer SDL may be formed through the same process as the second gate electrode GE2. Thus, the shielding layer SDL may include the same material as the second gate electrode GE2. The shielding layer SDL may have the same layer structure as the second gate electrode GE2. For example, when the second gate electrode GE2has a double-layer structure, the shielding layer SDL may also have a double-layer structure formed of the same material as that used to form the second gate electrode GE2.

Then, as shown inFIG.14, a portion of the second insulating layer120having no second conductive layers400formed thereabove may be removed. In other words, the second insulating layer120may be located only below the second conductive layer400(e.g., after other portions thereof are removed). Thus, the second insulating layer120may exist below the second gate electrode GE2, the first-second connection electrode CNE2-1, and the second-second connection electrode CNE2-2, but the second insulating layer120may not exist on the second area A2of the first-second connection area CNA2-1. Outside the first-second connection area CNA2-1, the second insulating layer120may exist below the second gate electrode GE2, the first-second connection electrode CNE2-1, the second-second connection electrode CNE2-2, the initialization-sensing line ISL, and the data line DL. In other words, outside the first-second connection area CNA2-1, the second insulating layer120may be interposed between the first insulating layer110and the second conductive layer400.

A portion of the second insulating layer120having no second conductive layers400formed thereabove may be removed using plasma. Thus, a portion of the oxide semiconductor layer300existing below the removed portion of the second insulating layer120, for example, the second area A2of the first-second connection area CNA2-1, may be metalized by plasma processing. Thus, the first-second connection area CNA2-1including the first area A1and the second area A2may be metalized. In other words, electrical properties of the first-second connection area CNA2-1may be different from electrical properties of the second channel area CHA2.

FIG.15is a schematic layout diagram illustrating respective locations of a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst in pixels included in a display apparatus2according to one or more other embodiments, andFIGS.16through19are schematic layout diagrams illustrating respective components of the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst for each layer of the display apparatus2ofFIG.15.FIG.20is a schematic cross-sectional view illustrating a cross-section taken along the line III-III′ of the display apparatus2ofFIG.15, andFIG.21is a schematic cross-sectional view illustrating a cross-section taken along the line IV-IV′ of the display apparatus2ofFIG.15. Because the display apparatus2according to one or more embodiments is similar to the display apparatus1described above with reference toFIGS.1through14, a difference of the display apparatus2from the display apparatus1described above with reference toFIGS.1through14will now be focused on and described.

A first conductive layer200shown inFIG.16may be located on a substrate100. The first conductive layer200included in the display apparatus1according to the embodiments described above with reference toFIG.5and the like include the control line CL, the scan line SL, the connection line CNL, the first gate electrode GE1, and the first capacitor electrode CE1. The first conductive layer200included in the display apparatus2according to one or more embodiments may also include the first gate electrode GE1and the first capacitor electrode CE1. However, in the display apparatus2according to one or more embodiments, the first conductive layer200does not include a control line CL, a scan line SL, and a connection line CNL, whereas the first conductive layer200may include a data line DL, an initialization-sensing line ISL, a driving voltage line VDL, a common voltage line VSL, and a gate wire GL.

The data line DL, the initialization-sensing line ISL, the driving voltage line VDL, and the common voltage line VSL may each extend in the second direction (for example, the y-axis direction). The data line DL may include a first data line DL1, a second data line DL2, and a third data line DL3. The first data line DL1, the second data line DL2, and the third data line DL3may supply a data signal to a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3, respectively. The gate wire GL may be electrically connected to a scan line SL included in a second conductive layer400. In detail, the gate wire GL may be electrically connected to the scan line SL through a scan line contact hole H-SL ofFIG.18formed in a first insulating layer110ofFIG.20and a second insulating layer120ofFIG.20.

The first conductive layer200may further include the first gate electrode GE1, the first capacitor electrode CE1, the gate wire GL, a second gate electrode GE2, and a third gate electrode GE3. The first insulating layer110may cover the first conductive layer200and may be located on the substrate100.

An oxide semiconductor layer300as shown inFIG.17may be located on the first insulating layer110. The oxide semiconductor layer300may include a first channel area CHA1, a second channel area CHA2, a third channel area CHA3, and a second capacitor electrode CE2. The first channel area CHA1may overlap the first gate electrode GE1, the second channel area CHA2may overlap the second gate electrode GE2, and the third channel area CHA3may overlap the third gate electrode GE3.

Compared with the above-described display apparatus1, a first-first connection area CNA1-1, a second-first connection area CNA1-2, a first-second connection area CNA2-1, a second-second connection area CNA2-2, a third connection area CNA3, and the second capacitor electrode CE2according to one or more embodiments may be a layer formed of a non-metalized oxide semiconductor. Connection metal layers may be located on the first-first connection area CNA1-1, the second-first connection area CNA1-2, the first-second connection area CNA2-1, the second-second connection area CNA2-2, and/or the third connection area CNA3, respectively. A capacitor metal layer may be located on the second capacitor electrode CE2.

In detail, the connection metal layer corresponding to the first-first connection area CNA1-1may be located on the first-first connection area CNA1-1, and the connection metal layer corresponding to the second-first connection area CNA1-2may be located on the second-first connection area CNA1-2. The connection metal layer corresponding to the first-second connection area CNA2-1may be located on the first-second connection area CNA2-1, and the connection metal layer corresponding to the second-second connection area CNA2-2may be located on the second-second connection area CNA2-2. The connection metal layer corresponding to the third connection area CNA3may be located on the third connection area CNA3. A capacitor metal layer corresponding to the second capacitor electrode CE2may be located on the second capacitor electrode CE2.

The connection metal layer and/or the capacitor metal layer may be a metal layer including a metal, such as titanium (Ti), molybdenum (Mo), or tungsten (W). The connection metal layer and/or the capacitor metal layer may have a single-layered or multi-layered structure including the aforementioned metal. For example, the connection metal layer and/or the capacitor metal layer may have a single layered structure, such as a titanium layer, a molybdenum layer, or a tungsten layer. Alternatively, the connection metal layer and/or the capacitor metal layer may have a multi-layered structure in which the aforementioned layers are stacked. The second insulating layer120may cover the oxide semiconductor layer300and the connection metal layer and/or the capacitor metal layer, and may be located on the first insulating layer110.

During the above-described metallization process of the display apparatus1, the second gate electrode GE2located above the second channel area CHA2may function as a mask that covers the second channel area CHA2such that the second channel area CHA2is not metalized, and the third gate electrode GE3located above the third channel area CHA3may function as a mask that covers the third channel area CHA3such that the third channel area CHA3is not metalized. However, the display apparatus2according to one or more embodiments, the second gate electrode GE2may not function as a mask because the second gate electrode GE2is located below the second channel area CHA2, and the third gate electrode GE3may not function as a mask either because the third gate electrode GE3is located below the third channel area CHA3. Thus, connection metal layers are located on the non-metalized first-first connection area CNA1-1, the non-metalized second-first connection area CNA1-2, the non-metalized first-second connection area CNA2-1, the non-metalized second-second connection area CNA2-2, and/or the non-metalized third connection area CNA3, respectively, so that there may be generated the same effect as when the first-first connection area CNA1-1, the second-first connection area CNA1-2, the first-second connection area CNA2-1, the second-second connection area CNA2-2, and/or the third connection area CNA3are metalized. Even when the capacitor metal layer corresponding to the second capacitor electrode CE2is located on the second capacitor electrode CE2, the same effect as when the second capacitor electrode CE2is metalized may be generated.

A second conductive layer400as shown inFIG.18may be located on the second insulating layer120. The second conductive layer400included in the display apparatus1according to the embodiments described above with reference toFIG.5and others include the data line DL, the initialization-sensing line ISL, the driving voltage line VDL, the common voltage line VSL, the gate wire GL, the shielding layer SDL, the first-first connection electrode CNE1-1, the second-first connection electrode CNE1-2, the first-second connection electrode CNE2-1, the second-second connection electrode CNE2-2, and the third connection electrode CNE3. The second conductive layer400included in the display apparatus2according to one or more embodiments also includes the shielding layer SDL, the first-first connection electrode CNE1-1, the second-first connection electrode CNE1-2, the first-second connection electrode CNE2-1, the second-second connection electrode CNE2-2, and the third connection electrode CNE3. However, in the display apparatus2according to one or more embodiments, the second conductive layer400may not include the data line DL, the initialization-sensing line ISL, the driving voltage line VDL, the common voltage line VSL, and the gate wire GL, whereas the second conductive layer400may include the control line CL, the scan line SL, and the connection line CNL.

The second conductive layer400may include the scan line SL and the control line CL each extending in the first direction (for example, the x-axis direction). The second conductive layer400may include the connection line CNL extending in the first direction (for example, the x-axis direction).

The first-second connection electrode CNE2-1and the connection line CNL may be integrated. In other words, the first-second connection electrode CNE2-1and the connection line CNL may be integrally formed with each other through the same process. For example, the first-second connection electrode CNE2-1may be a portion of the connection line CNL. Thus, the first-second connection electrode CNE2-1may include the same material as the connection line CNL. The first-second connection electrode CNE2-1may have the same layer structure as the connection line CNL. For example, when the first-second connection electrode CNE2-1has a double-layer structure, the connection line CNL may also have a double-layer structure formed of the same material as that used to form the first-second connection electrode CNE2-1.

A third insulating layer130ofFIG.20may cover the second conductive layer400and may be located on the second insulating layer120. A fourth insulating layer140ofFIG.20may be located on the third insulating layer130to cover the third insulating layer130. A first display element DPE1may be located on the fourth insulating layer140. The first display element DPE1may include a pixel electrode510, an intermediate layer520including an emission layer, and an opposite electrode530, and the pixel electrode510ofFIG.19may be located on the fourth insulating layer140.

FIG.20is a schematic cross-sectional view taken along the line III-III′ of the display apparatus2ofFIG.15. Similar to the above-described display apparatus1, the first gate electrode GE1of the display apparatus2may also be located below the oxide semiconductor layer300. In other words, the first transistor T1of the display apparatus2may have a bottom gate structure. Accordingly, the first insulating layer110may cover the first gate electrode GE1. An effect generated due to a location of the first gate electrode GE1below the oxide semiconductor layer300and due to covering of the first gate electrode GE1by the first insulating layer110may also occur in the case of the display apparatus2. Thus, a description of an effect generated due to a location of the first gate electrode GE1of the display apparatus2below the oxide semiconductor layer300and due to covering of the first gate electrode GE1by the first insulating layer110, which is the same as given above, will not be repeated herein. A first-first connection metal layer CNA1-1amay be located on the first-first connection area CNA1-1, a second-first connection metal layer CNA1-2amay be located on the second-first connection area CNA1-2, and a second capacitor metal layer CE2amay be located on the second capacitor electrode CE2.

FIG.21is a schematic cross-sectional view taken along the line IV-IV′ of the display apparatus2ofFIG.15. As shown inFIG.21, the first-second connection electrode CNE2-1of the second transistor T2may be electrically connected to a connection metal layer on the first-second connection area CNA2-1of the second transistor T2. Accordingly, the first-second connection electrode CNE2-1of the second transistor T2may be electrically connected to the first-second connection area CNA2-1of the second transistor T2. The first-second connection electrode CNE2-1of the second transistor T2may be integrated with the connection line CNL. Because the connection line CNL is electrically connected to the first data line DL1, the first-second connection electrode CNE2-1of the second transistor T2may be electrically connected to the first data line DL1.

FIGS.22through24are schematic cross-sectional views illustrating a process of manufacturing a portion of the display apparatus2ofFIG.15. In detail,FIGS.22through24are schematic cross-sectional views illustrating a process of manufacturing the connection line CNL, the first-second connection area CNA2-1, the connection metal layer on the first-second connection area CNA2-1, and the first-second connection electrode CNE2-1of the display apparatus2ofFIG.15.

First, as shown inFIG.22, the first capacitor electrode CE1, the second gate electrode GE2, the initialization-sensing line ISL, and the data line DL may be formed above the substrate100, and the first insulating layer110may be formed to cover the first capacitor electrode CE1, the second gate electrode GE2, the initialization-sensing line ISL, and the data line DL. Because the first insulating layer110covers the first conductive layer200to correspond to the entire surface of the substrate100, the first insulating layer110may cover the first capacitor electrode CE1, the second gate electrode GE2, the initialization-sensing line ISL, and the data line DL included in the first conductive layer200.

The above-described first gate electrode GE1may be formed through the same process as the second gate electrode GE2. Thus, the first gate electrode GE1may include the same material as the second gate electrode GE2. The first gate electrode GE1may have the same layer structure as the second gate electrode GE2. For example, when the second gate electrode GE2has a double-layer structure, the first gate electrode GE1may also have a double-layer structure formed of the same material as that used to form the second gate electrode GE2.

A second semiconductor pattern SP2may be formed above the first insulating layer110. A first-second connection metal layer CNA2-1acorresponding to the first-second connection area CNA2-1may be formed on the first-second connection area CNA2-1, and a second-second connection metal layer CNA2-2acorresponding to the second-second connection area CNA2-2may be formed on the second-second connection area CNA2-2. To this end, after a preliminary oxide semiconductor layer is formed on the first insulating layer110and a preliminary connection metal layer is formed on the preliminary oxide semiconductor layer, the preliminary oxide semiconductor layer and the preliminary connection metal layer may be concurrently or substantially simultaneously patterned using a photoresist. In detail, during exposure of the photoresist, the preliminary oxide semiconductor layer and the preliminary connection metal layer may be concurrently or substantially simultaneously patterned by using a halftone mask.

Then, as shown inFIG.23, the second insulating layer120may be formed above the second semiconductor pattern SP2, and a first-second contact hole H2-1penetrating through the second insulating layer120may be formed. The first-second contact hole H2-1may be formed to overlap the first-second connection area CNA2-1in a plan view. A data line contact hole H-DL penetrating through the first insulating layer110and the second insulating layer120may be formed, and the data line contact hole H-DL may overlap the first data line DL1in a plan view.

Then, as shown inFIG.24, the first-second connection electrode CNE2-1and the connection line CNL may be formed on the second insulating layer120. In detail, the first-second connection electrode CNE2-1and the connection line CNL may be integrally formed with each other through the same process.

According to one or more embodiments as described above, a display apparatus capable of stably applying an electrical signal to a gate electrode may be realized. Of course, the scope of the disclosure is not limited thereto.