DIGITAL ISOLATOR ARCHITECTURE FOR HYBRID CAPACITOR AND INDUCTOR

In general, one aspect disclosed features an apparatus comprising: a receiver comprising a receiver inductor-capacitor (LC) tank; a transmitter comprising an oscillator; and a capacitive isolation barrier electrically coupled between an output of the transmitter and an input of the receiver.

DESCRIPTION OF RELATED ART

The disclosed technology relates generally to electronic data communications, and more particularly some embodiments are related to electronic data communications across a galvanic isolation barrier.

SUMMARY

In general, one aspect disclosed features an apparatus comprising: a receiver comprising a receiver inductor-capacitor (LC) tank; a transmitter comprising an oscillator; and a capacitive isolation barrier electrically coupled between an output of the transmitter and an input of the receiver.

Embodiments of the apparatus may include one or more of the following features. In some embodiments, the oscillator is tuned to a resonant frequency of the LC tank. In some embodiments, the receiver LC tank comprises: a receiver coupled inductor pair with a center tap. In some embodiments, the inductor pair is implemented using standard CMOS processes. In some embodiments, the transmitter transmits a signal of interest; and the receiver coupled inductor pair with a center tap is configured to cancel any common mode signal without attenuating the signal of interest.

In some embodiments, the receiver comprises a differential receive amplifier. In some embodiments, the receiver coupled inductor pair with the center tap is electrically coupled between differential inputs of the differential receive amplifier. In some embodiments, the capacitive isolation barrier comprises: a first capacitor electrically coupled to a first input of the differential receive amplifier; and a second capacitor electrically coupled to a second input of the differential receive amplifier. Some embodiments comprise a first tunable capacitor coupled to a first differential input of the differential receive amplifier; and a second tunable capacitor coupled to a second differential input of the differential receive amplifier

In some embodiments, the transmitter comprises a differential transmit driver. In some embodiments, the oscillator is electrically coupled between an input of the transmitter and inputs of the differential transmit driver. In some embodiments, the oscillator is electrically coupled to a first input of the differential transmit driver by a first capacitor; and the oscillator is electrically coupled to a second input of the differential transmit driver by a second capacitor. In some embodiments, the capacitive isolation barrier comprises: a first capacitor electrically coupled to a first output of the differential transmit driver; and a second capacitor electrically coupled to a second output of the differential transmit driver

In some embodiments, the transmitter further comprises a transmitter LC tank, wherein the transmitter LC tank is tuned to the resonant frequency of the receiver LC tank. In some embodiments, the transmitter LC tank comprises a transmitter coupled inductor pair with a second center tap separate from the receiver LC tank. In some embodiments, the inductor pair is implemented using standard CMOS processes. In some embodiments, the transmitter comprises a differential transmit driver; and the transmitter coupled inductor pair with the second center tap is electrically coupled between differential outputs of the differential transmit driver. In some embodiments, a first tunable capacitor coupled to a first differential output of the differential transmit driver; and a second tunable capacitor coupled to a second differential output of the differential transmit driver.

In some embodiments, the transmitter and receiver employ on-off keying communications by modulating a carrier available at the transmitter. Some embodiments comprise a second receiver comprising a second receiver LC tank; a second transmitter comprising a second oscillator, wherein the second oscillator is tuned to a resonant frequency of the second receiver LC tank, and wherein the resonant frequency of the second receiver LC tank is different from the resonant frequency of the transmitter LC tank; and a second capacitive isolation barrier electrically coupled between an output of the second transmitter and an input of the second receiver.

DETAILED DESCRIPTION

In many applications such as industrial, automotive, renewable energy, and medical equipment, there is a need to provide galvanic isolation between two electrical domains while exchanging information between the electrical domains. These approaches generally employ on-off keying (OOK) of a carrier signal to exchange the information across a galvanic isolation barrier. OOK signals are illustrated inFIG.1, where an input signal TX IN and the corresponding output signal RX OUT are square waves. The input signal TX IN OOK modulates a carrier signal CS for transmission across the galvanic isolation barrier. The presence of the carrier signal CS indicates the “off” state of the OOK signal, while the absence of the carrier signal CS indicates the “on” state. The carrier signal CS is then OOK demodulated on the other side of the galvanic isolation barrier to produce the output signal RX OUT.

In one approach, optocouplers have been used to achieve such isolation where a signal is generated by modulating a light emitting transmitter on one side of the galvanic barrier, and receiving the signal in the form of light using a photo receiver on the other side of the galvanic barrier.

In recent years these devices have been replaced by silicon based isolators that use a transmitter device and a receiver device implemented on two separate silicon chips that are galvanically isolated. One of the key requirements of these solutions is to tolerate large DC and transient voltage differences between the transmitter and receiver chips. In particular, even if there is a large common mode voltage change between the two chips (transmitter and receiver), on the order of 10 KV/us to 100 KV/us, no signal corruption should occur. This is a key metric for digital isolators, and is commonly referred to as “Common Mode Transient Immunity” (CMTI). There are currently two main methods of achieving signal transmission across the galvanic barrier: inductive and capacitive.

FIG.2. illustrates an inductive approach for transmitting signals across the galvanic barrier. Referring toFIG.2, the primary side of a transformer202is connected to a transmitter204, while the secondary side of the transformer202is connected to a receiver206. The coupling between the transformer primary and secondary is used to sense the primary signal on the secondary side and thus achieve signal communication.

However, this implementation is area and power intensive due to the requirements of implementing and driving the transformer202on silicon. This method also requires specialized processing and assembly to achieve good performance. Such solutions have primarily been adopted by silicon vendors with their own captive foundry and assembly operations.

FIG.3. illustrates a capacitive approach for transmitting signals across the galvanic barrier. Referring toFIG.3, a capacitive isolation barrier302is connected in series between a transmitter304and a receiver306. This is currently the most common implementation of silicon based isolators, but has several drawbacks. This implementation is sensitive to parasitic capacitance to ground on both the receiver chip and the transmitter chip. CMTI performance is limited by the ratio of coupling capacitance to parasitic capacitance.

The capacitive coupling between transmitter304and receiver306attenuates the signal of interest and the common mode noise signal by the same factor. Since the common mode signal during a CMTI event is of the order of 10 KV to 100 KV and the signal of interest of the order of 1V, this further limits the CMTI performance of such solutions.

Robust signal detection requires modulation of the signal at the transmit side and demodulation of the signal at the receive side. To avoid the signal of interest being corrupted by the much larger common mode signal during a-common mode transient event, the demodulation requires more time and sometimes additional circuits to reject the common mode signal. This increases signal latency and is a still further limitation on performance.

FIG.4. is a circuit block diagram of a hybrid capacitor and inductor based digital isolator circuit400according to some embodiments of the disclosed technologies. Referring toFIG.4, the circuit400includes a capacitive isolation barrier402connected in series between a transmitter404and a receiver406. The transmitter404may include a tunable oscillator408and a transmit (TX) driver410, both coupled to an input signal TX IN. The transmit driver410may be differential, and the oscillator408may be coupled to differential inputs of the differential TX driver410, for example by capacitors C7and C8. The transmitter404may include output capacitors C1and C2.

The receiver406may include an LC tank410and a receive (RX) amplifier412that provides an output signal RX OUT. The receiver406may include input capacitors C3and C4. The receive amplifier412may be differential. The LC tank410may include an inductor L1coupled between the differential inputs of the receive amplifier412. The inductor L1may be a paired inductor with a center tap CT. The LC tank410may include two tunable capacitors C5and C6, each coupled to one of the differential inputs of the receiver amplifier412.

The oscillator408may be factory tuned to the resonant frequency of the LC tank410. The differential signal of interest may be amplified by the LC tank410. The paired inductors in the LC tank410may be coupled in a way that cancels the common mode signal passing through them without attenuating the differential mode signal of interest. This results in an attenuation of the undesirable common mode transient signal compared to the differential signal of interest. The combination of these features may fundamentally improve the signal to noise ratio between the differential signal of interest and the common mode signal to be rejected, thus fundamentally improving achievable CMTI. For perfect coupling of the inductors, the common mode signal will be reduced to zero without any impact on the differential signal. Because the circuit400cancels the common mode transient signal, there is no need to allocate additional time or circuits to reject the common mode signal. This improves latency. The inductors L1are not very sensitive to losses and can be implemented using standard CMOS processes. This allows the use of commercially available third party silicon foundry processes and standard assembly techniques to implement such chips. The hybrid capacitor and inductor based digital isolator circuit400ofFIG.4achieves both a high CMTI and low latency at the same time.

In some embodiments, an additional LC tank may be implemented in the transmitter404.FIG.5is a circuit block diagram of a hybrid capacitor and inductor based digital isolator circuit500having LC tanks in both the transmitter and the receiver according to some embodiments of the disclosed technologies. Referring toFIG.5, the circuit500is similar to the circuit400, but with the addition of an LC tank510to the transmitter404. The LC tank510may include an inductor L2coupled between the differential outputs of the transmit driver410. The inductor L2may be a paired inductor with a center tap CT. The LC tank410may include two tunable capacitors C9and C10, each coupled to one of the differential outputs of the transmit driver410. The second LC tank510may be tuned to the resonant frequency of the first LC tank410. This arrangement may further improve CMTI by another factor of two.

In some embodiments, a multi-channel hybrid capacitor and inductor based digital isolator circuit includes a plurality of the disclosed hybrid capacitor and inductor based digital isolator circuits.FIG.6depicts one such circuit600according to some embodiments of the disclosed technologies. Referring toFIG.6, the circuit600includes N isolator circuits400A-400N. Each of the isolator circuits400A-400N may implemented as described with reference toFIG.4. In some embodiments, each of the isolator circuits400A-400N may implemented as described with reference toFIG.5. Each of the isolator circuits400A-400N may be tuned to a different frequency to increase immunity from crosstalk between the channels. In some embodiments, one or more of the isolator circuits400A-400N may share an oscillator.

FIG.7illustrates a paired inductor with a center tap according to some embodiments of the disclosed technologies. Referring toFIG.7, the inductor may include two traces that connect a pair of inputs P and N to a common tap CT. Each trace may include top metal layers706, and top-1 metal layers708. The top metal layers706in a trace may be connected to the top-1 layers708in that trace by a plurality of vias702. The inductor may be surrounded by metal structures704that reduce the magnetic coupling of the inductor to adjacent electrical structures.

As used herein, a circuit might be implemented utilizing any form of hardware, or a combination of hardware and software. For example, one or more processors, controllers, ASICs, PLAS, PALs, CPLDs, FPGAs, logical components, software routines or other mechanisms might be implemented to make up a circuit. In implementation, the various circuits described herein might be implemented as discrete circuits or the functions and features described can be shared in part or in total among one or more circuits. Even though various features or elements of functionality may be individually described or claimed as separate circuits, these features and functionality can be shared among one or more common circuits, and such description shall not require or imply that separate circuits are required to implement such features or functionality.

The foregoing description of the present disclosure has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments. Many modifications and variations will be apparent to the practitioner skilled in the art. The modifications and variations include any relevant combination of the disclosed features. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the disclosure be defined by the following claims and their equivalence.