Method of improving refresh time in DRAM products

An improved and new method for forming a metal conductor interconnection structure on a semiconductor substrate containing DRAM devices has been developed. The method utilizes a thermal anneal in a flowing gas mixture of nitrogen and hydrogen following patterning of the metal conductor interconnection structure and results in DRAM devices having improved mean refresh time (time between refresh cycles).

BACKGROUND OF THE INVENTION 
(1) Field of the Invention 
This invention relates to a method of fabrication used for semiconductor 
circuit devices, and more specifically to an improved method of forming 
the metallization interconnection layers in DRAM (Dynamic Random Access 
Memory) products. 
(2) Description of Related Art 
DRAM (Dynamic Random Access Memory) products make use of very low leakage 
associated with gate circuits and junctions of MOS devices. Usually the 
leakage currents are small enough to permit the circuit's parasitic 
capacitances to exhibit time constants of many milliseconds. And, long 
time constants may be used to provide temporary storage, which may be made 
permanent by appropriate cyling or refresh operations. It is, therefore, 
desirable that the refresh time (time between refresh cycles) be as long 
as possible in order to minimize the necessity to periodically restore 
charge storage in the memory cells. More advanced DRAM products require 
longer and longer refresh times to ensure quality and advanced memory 
functionality. 
In current DRAM products, such as 16M DRAM, it is desirable that the mean 
refresh time be greater than 1200 milliseconds. However, using current 
fabrication processing technologies, the typical refresh time is about 
400-600 milliseconds. This results in refresh time test failure and 
becomes a major yield detractor when manufacturing advanced DRAM products 
such as 16M DRAM, 64M DRAM and 256M DRAM. Improvements to DRAM 
manufacturing processes which can increase the refresh time are, 
therefore, desirable. Such process improvements should, also, not 
adversely impact overall process yield and cost. 
U.S. Pat. No. 5,420,070 entitled "Manufacturing Method of Interconnection 
Structure of Semiconductor Device" granted May 30, 1995 to Megumi Matsuura 
et al describes a semiconductor manufacturing process in which a thermal 
treatment is made to a tungsten-titanium interface to cause reaction of 
the tungsten and the titanium layers. The result is an improved 
metallization structure having stable resistance at contacts and high 
process yield. 
SUMMARY OF THE INVENTION 
One object of the present invention is to provide an improved method of 
fabricating a metal conductor interconnection structure on a semiconductor 
substrate containing DRAM devices, which results in DRAM devices having 
improved refresh time (time between refresh cycles). 
Another object of the present invention is to provide a new and improved 
process for fabricating a metal conductor interconnection structure on a 
semiconductor substrate containing DRAM devices, which results in DRAM 
devices having mean refresh times of at least 1200 milliseconds. 
A further object of the present invention is to provide a new and improved 
process for fabricating a metal conductor interconnection structure on a 
semiconductor substrate containing DRAM devices, which results in DRAM 
devices having improved refresh time; the overall process having high 
manufacturing yield and low cost. 
In accordance with the present invention, the above and other objectives 
are realized by using a method of forming a metal conductor 
interconnection structure on a semiconductor substrate containing DRAM 
devices, comprising the steps of: providing said semiconductor substrate 
containing DRAM devices; forming an insulating layer on the semiconductor 
substrate; forming contact holes in the insulating layer, exposing a 
plurality of underlying regions of the DRAM devices; depositing a metal 
conductor layer on the insulating layer and the underlying regions to 
substantially cover the insulating layer and the underlying regions; 
forming an interconnection structure pattern in the metal conductor layer; 
and applying a thermal process in a flowing gas mixture of nitrogen and 
hydrogen.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The new and improved method for fabricating a metal conductor 
interconnection structure on a semiconductor substrate containing DRAM 
devices, which results in DRAM devices having improved mean refresh time 
(time between refresh cycles), will now be described in detail. 
Referring to FIG. 1, DRAM cell 11 is formed on silicon semiconductor 
substrate 10. DRAM cell 11 is formed of an element separator oxide layer 
12, a transfer gate electrode 13, an impurity diffusion layer 14, a word 
line 15, a memory node 16, a capacitor insulating layer 17, a cell plate 
18 and a dielectric layer 19. The DRAM cell 11 is formed by conventional 
semiconductor circuit manufacturing processes. 
Referring to FIG. 2, insulating layer 20 is formed on the entire surface of 
the silicon semiconductor substrate 10 on which DRAM cell 11 is formed. 
The insulating layer 20 may be silicon oxide deposited by LPCVD (Low 
Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical 
Vapor Deposition), at a temperature between about 300 to 1000.degree. C., 
to a thickness between about 2000 and 10,000 Angstroms, using TEOS 
(tetraethylorthosilicate) gas at a flow between about 0.1 and 2 slm. 
Contact holes 21 are formed in the insulating layer 20 using conventional 
lithographic and plasma etching techniques. Metal conductor layer 22 is 
deposited by conventional methods and etched to form a metal conductor 
interconnection structure pattern, as shown. The metal conductor layer 22 
may be tungsten deposited by a CVD process, at a temperature between about 
300 and 500.degree. C., to a thickness between about 2000 and 8000 
Angstroms, using WF.sub.6 gas at a flow between about 5 and 200 sccm. 
Formation of the tungsten interconnection structure is by conventional 
lithographic techniques and plasma etching in a conventional metal etcher 
apparatus using SF.sub.6 and N.sub.2 gases. Alternately, the metal 
conductor layer 22 may be aluminum deposited to a thickness between about 
2000 and 10,000 Angstroms. Formation of the aluminum interconnection 
structure is by conventional lithographic techniques and plasma etching in 
a conventional metal etcher apparatus using Cl.sub.2 and BCl.sub.3 gases. 
Following formation of the metal conductor interconnection structure 
pattern, the semiconductor substrate is annealed in a flowing gas mixture 
of nitrogen and hydrogen. The annealing process comprises the step of 
heating at a temperature between about 400 and 500.degree. C. for a time 
between about 30 and 90 min. It is important that the temperature of the 
anneal step be between about 400 and 500.degree. C. for a time greater 
than about 20 to 30 min. A flowing gas mixture of nitrogen and hydrogen is 
present during the anneal step and the gas mixture has a flow rate of 
nitrogen between about 5 and 30 slm (standard liters per min) and a flow 
rate of hydrogen between about 0.5 and 5 slm (standard liters per min). 
The ratio of the flow rate of the nitrogen to the flow rate of the 
hydrogen is not critical, but may be between about 2 to 1 and 15 to 1. 
The anneal of the metal conductor interconnection structure pattern in the 
flowing gas mixture of nitrogen and hydrogen results in a significant 
improvement in mean refresh time for DRAM products formed with a metal 
conductor interconnection structure pattern. TABLE 1 shows the mean 
refresh time in milliseconds for DRAM devices formed with a tungsten 
interconnection structure pattern as a function of anneal treatment in a 
mixture of nitrogen and hydrogen. 
TABLE 1 
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Anneal History Mean Refresh Time 
______________________________________ 
No anneal 700 ms 
N.sub.2 /H.sub.2 anneal at 450.degree. C. 
1400 ms 
No anneal 600 ms 
30 min anneal, N.sub.2 /H.sub.2, 450.degree. C. 
1200 ms 
60 min anneal, N.sub.2 /H.sub.2, 450.degree. C. 
1200 ms 
90 min anneal, N.sub.2 /H.sub.2, 450.degree. C. 
1200 ms 
No anneal 650 ms 
N.sub.2 /H.sub.2 anneal at 450.degree. C. 
1300 ms 
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The increased mean refresh time, which results when the intreconnection 
structure pattern is annealed in a gas mixture of nitrogen and hydrogen, 
results in improved DRAM cell functionality. The anneal step should be at 
a temperature of at least 400.degree. C., and may be at a temperature 
between about 400 and 500.degree. C. The anneal time is not critical. A 
time of 30 min or longer results in longer mean refresh time. The anneal 
step is easily implemented, at low cost, in the fabrication process flow 
and does not negatively impact DRAM device parameters. FIG. 3 is a flow 
chart of the improved process. 
Following the anneal step in the flowing gas mixture of nitrogen and 
hydrogen, a cleaning step may be applied to the semiconductor substrate. 
The cleaning may be performed in an ultrasonic bath, as is conventional to 
semiconductor integrated circuit manufacturing processes. 
While the invention has been particularly shown and described with 
reference to the preferred embodiments thereof, it will be understood by 
those skilled in the art that various changes in form and details may be 
made without departing from the spirit and scope of the invention.