System and method to reduce noise in a substrate

Certain embodiments of the invention may be found in, for example, a system that reduces noise in a substrate of a chip and may comprise a substrate and a first well disposed on top of the substrate. The first well may be a deep well. Notwithstanding, a second well and a third are both disposed within the first well and a first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor and a second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor and a body of the first transistor may be resistively coupled to the second well.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to integrated circuit (IC) designs. More specifically, certain embodiments of the invention relate to a system for reducing noise in a substrate of an integrated circuit.

BACKGROUND OF THE INVENTION

As more and more functional blocks are added, for example, to a chip, an integrated circuit (IC) or an integrated system or device, the risk for the generation and propagation of noise between the different functional blocks or within a functional block may become quite substantial.

An exemplary conventional complementary metal oxide semiconductor (CMOS) transistor arrangement is illustrated in FIG.1. As shown inFIG. 1, the conventional CMOS transistor arrangement10includes an n-channel MOS (NMOS) transistor30and a p-channel MOS (PMOS) transistor40. The conventional CMOS arrangement10also includes a p-substrate20(e.g., a p−-substrate). The NMOS transistor30is disposed in the p-substrate20. The NMOS transistor30includes a p+-body (B), an n+-source (S) and an n+-drain (D) disposed in the p-substrate20. A voltage source VSS7having a ground is coupled to the p+-body (B) and the n+-source (S) of NMOS transistor30. An input line5is coupled to a gate (G) of the NMOS transistor30. An output line15is coupled to the n+-drain (D) of the NMOS transistor30. The PMOS transistor40includes an n-well50that is disposed in the p-substrate20. The PMOS transistor40also includes an n+-body (B), a p+-source (S) and a p+-drain (D) disposed in the n-well50. A voltage source VDD17is coupled to the p+-source (S) and the n+-body (B) of PMOS transistor50. The input line5is also coupled to a gate of the PMOS transistor40. The output line15is also coupled to the p+-drain (D) of the PMOS transistor40.

During normal operation of the conventional CMOS transistor arrangement10, the voltage sources VSS7, VDD17may be noisy. For example, the noise may be caused by other circuitry found on or coupled to the chip that may directly or indirectly affect the voltage sources VSS7, VDD17. High swing or high power devices such as, data drivers in a wire line communication system or transmitters in wireless communications systems, may be sources of noise. The noise may also be caused, for example, by the driving of active circuits. In one example, the voltage sources may be coupled to active circuitry (e.g., active portions of an inverter circuit) which may cause transient currents to flow during signal transitions from a high level to a low level or from a low level to a high level. In another example, noise may be caused by transitions in a signal propagated or generated by the chip.

In the NMOS transistor30, if the voltage source VSS7is noisy, then the noise may propagate to the p-substrate20via, for example, at least through the resistive coupling9between the p+-body (B) and the p-substrate20. In the PMOS transistor40, if the voltage source VDD17is noisy, then the noise may propagate to the n-well50via the n+-body (B) of the PMOS transistor40via a resistive coupling19. The noise in the n-well50may propagate to the p-substrate20via, for example, at least the capacitive coupling29between the n-well50and the p-substrate20. If the noise is able to propagate to the p-substrate20, then noise may propagate to or otherwise affect other circuits on or off the chip that may be coupled to the p-substrate20.

FIG. 1Ashows another conventional CMOS arrangement10, which is similar to the conventional CMOS arrangement10shown inFIG. 1, except that a quieter voltage source VSS3is coupled to the p+-body (B) of the NMOS transistor30and a noisy voltage source VSS7is coupled to the n+-source (S) of the NMOS transistor30. Thus, less noise is resistively coupled from the p+-body (B) to the p-substrate20. To a lesser extent, noise may be capacitively coupled between the n+-source and the p-substrate20. Noise may be coupled from the PMOS transistor40to the p-substrate20as described above with respect to the conventional CMOS arrangement10as shown in FIG.1. In the CMOS arrangement ofFIG. 1A, noise may substantially propagate to the p-substrate20. Accordingly, there is a need to mitigate noise in the substrate of a chip.

BRIEF SUMMARY OF THE INVENTION

Certain embodiments of the invention may be found in, for example, a system that reduces noise in a substrate of a chip. Aspects of the system may comprise a substrate and a first well disposed on top of the substrate. The first well may be a deep well. A second well and a third are both disposed within the first well and a first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor and a second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor and a body of the first transistor may be resistively coupled to the second well.

The system may further comprise a noisy voltage source, and a body and a source of the second transistor may both be coupled to the noisy voltage source. The body of the second transistor may be capacitively coupled to the substrate. The substrate and the third well may be doped with a first dopant and the first and the second well may be doped with a second dopant.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIGS. 1 and 1Ashows embodiments of conventional complementary metal oxide semiconductor (CMOS) transistor arrangements.

FIG. 2shows an embodiment of a CMOS transistor arrangement according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2shows an embodiment of a complementary metal oxide semiconductor (CMOS) transistor arrangement60in accordance with the present invention. The CMOS transistor arrangement60may include a p-substrate70, a deep n-well80, an n-channel MOS (NMOS) transistor90and a p-channel MOS (PMOS) transistor100. The NMOS transistor90may include, for example, a p+-body (B), an n+-source (S) and an n+-drain (D) which may be disposed in a p-well110. The p-well110may be an isolated p-well since, for example, it may be disposed between two n-wells120and the deep n-well80. A voltage source VSS170having an electrical ground, may be coupled to the p+-body (B) and the n+-source (S) of the NMOS transistor90. An input signal line150may be coupled to a gate of the NMOS transistor90. An output signal line160may be coupled to the n+-drain of the NMOS transistor90.

The PMOS transistor100may include, for example, an n+-body (B), a p+-source (S) and a p+-drain (D), which may be disposed in an n-well120. A first voltage source VDD130may be coupled to the p+-source (S) and a second voltage source VDD140may be coupled to the n+-body (B) of the PMOS transistor100. In one embodiment, the second voltage source VDD140is less noisy than the first voltage source VDD130. In this regard, VDD140may be a quieter voltage source in comparison to the voltage source VDD130. The input signal line150may be coupled to a gate of the PMOS transistor100. The output signal line160may be coupled to the p+-drain (D) of the PMOS transistor100.

The voltage source VDD130and the quieter voltage source VDD140may be different voltage sources. The quieter voltage source VDD140may be a dedicated voltage source that is not coupled to some sources of noise. For example, it can be an active component of a transistor. The quieter voltage source VDD140may be dedicated, for example, to a guard bar for well taps or substrate taps. Alternatively, the voltage source VDD130and the quieter voltage source VDD140may be coupled to the same voltage source. However, the quieter voltage source VDD140may be isolated or separated from the voltage source VDD130so that less noise may be carried by the quieter voltage source VDD140.

In operation, the voltage source VSS170and the voltage source VDD130may be noisy due to a number of factors, some of which are described herein. For example, the noise may be caused by other circuitry found on or coupled to the chip that may directly or indirectly affect the voltage sources VSS170, VDD130. High swing or high power devices such as, data drivers in a wire line communication system or transmitters in wireless communications systems, may be sources of noise. The noise may also be caused, for example, by the driving of active circuits. In one example, the voltage sources may be coupled to active circuitry (e.g., active portions of an inverter circuit) which may cause transient currents to flow during signal transitions from a high level to a low level or from a low level to a high level. In another example, noise may be caused by transitions in a signal propagated or generated by the chip and/or any associated circuitry.

In accordance with the inventive CMOS transistor arrangement60, one source of noise is that the voltage sources VSS170, VDD130may be coupled to the sources of the NMOS transistor90and the PMOS transistor100. Thus, for example, when the circuit is in a transitional state such as during a signal transition from a high level to a low level or from a low level to a high level, a transient current may flow between the voltage sources VSS170and VDD130. Notably, if other devices (e.g., other CMOS transistor arrangements) are sharing the voltage sources VSS170, VDD130, then the noise generated by the transient current flows may be substantial.

The noise in the voltage source VSS170may flow into the body (B) and the source (S) of the NMOS transistor90. The body (B) of the NMOS transistor90may be resistively coupled180to the p-well110and the source (S) of the NMOS transistor90may be capacitively coupled190to the p-well110. The resistive coupling180may be much more substantial than the capacitive coupling190. Accordingly, most of the noise in the p-well110may be associated with the p+-body of the NMOS transistor90. For the noise in the p-well110to reach the p-substrate70, the noise may need to pass through two capacitive couplings: a capacitive coupling200between the p-well110and the deep n-well80and a capacitive coupling210between the deep n-well80and the p-substrate70. Importantly, the capacitive coupling is generally fairly weak, but the capacitive coupling is even weaker when the couplings are placed in series. Thus, in this embodiment of the present invention, the resistive couplings180,200and210between the p+-body (B) of the NMOS transistor90through to the p-substrate70may be replaced with a much weaker capacitive coupling.

The noise in the voltage source VDD130may flow into the p+-source (S) of the PMOS transistor100. In this embodiment, the present invention may employ a quieter voltage source VDD140which may be coupled to the n+-body (B) of the PMOS transistor100. The p+-source (S) of the PMOS transistor100may be capacitively coupled220to the n-well120and the n+-body (B) of the PMOS transistor100may be resistively coupled230to the n-well120. Since the resistive coupling230may be more substantial than the capacitive coupling, the noise in the n-well120may be mostly from the quieter voltage source VDD140. Advantageously, the noise in the n-well120may be substantially reduced by connecting the quieter voltage source VDD140to the n+-body (B) of the PMOS transistor100. The n-well120and the deep n-well80may be resistively coupled240. Notably, the deep n-well80may provide a substantial amount of resistance to the noise, thereby further reducing any noise propagating through PMOS resistor100and reaching substrate70. The deep n-well80and the p-substrate70may be capacitively coupled, which may offer the noise only a weak coupling.

Although illustrated in use with a CMOS transistor arrangement, the present invention need not be so limited. The present invention may also be applicable for use with other types of transistors or other types of transistor arrangements. Notably, in a an embodiment of the invention, the quiet Vddmay be used to replace a conventional Vsswithout an area penalty. In this regard, the area used by the Vddmay replace the area used by the Vss, in for example, a block or standard resistor/transistor logic (RTL) arrangement. The present invention may also be applicable for use with other electrical, magnetic or electromagnetic components or circuits. Furthermore, although one or more of the embodiments described above may employ semiconductor materials (e.g., semiconductor material, compound semiconductor material, etc.), the present invention may also contemplate using other materials (e.g., ceramics, metals, alloys, superconductors, etc.) or combinations thereof. In addition, the present invention may also contemplate using different dopant types, dopant schemes or dopant concentrations other than or in addition to the above-described dopant types, dopant schemes or dopant concentrations.