Magnetic tunnel junction element

Devices and methods for forming a device are disclosed. A substrate having circuit component formed on a substrate surface is provided. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A pair of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. Each of the MTJ stack includes a fixed layer, a tunneling barrier layer and a free layer. The fixed layer has a first width. The tunneling barrier layer is formed on the fixed layer. The free layer is formed on the tunneling barrier layer. The free layer has a second width. The first width is wider than the second width.

BACKGROUND

There are two important requirements for a high density memory cell application, namely the intrinsic critical current (Ic) and thermal stability factor (A). However, satisfying the two important requirements remains a huge challenge due to the trade-off relation of the intrinsic critical current and thermal stability factor.

For example, thermal stability factor of a memory cell improves with increased volume of the memory cell. Such improvement of the thermal stability factor enhances the data retention time of the memory cell. However, an increase in the volume of the memory cell adversely results in an increase in the intrinsic critical current, which is undesirable for high density memory cell application.

Therefore, it is desirable to provide reliable memory devices having a reduced volume so as to achieve critical current scaling for high density memory cell application without sacrificing the thermal stability factor.

SUMMARY

Embodiments of the present disclosure generally relate to semiconductor devices and methods for forming a semiconductor device. In one embodiment, a method for forming a device is disclosed. The method includes providing a substrate having circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. The method also includes forming a pair of magnetic tunneling junction (MTJ) stacks in between adjacent ILD levels of the upper ILD layer. Each of the MTJ stack includes a fixed layer, a tunneling barrier layer and a free layer. The fixed layer has a first width. The tunneling barrier layer is formed on the fixed layer. The free layer is formed on the tunneling barrier layer. The free layer has a second width. The first width is wider than the second width.

In one embodiment, a device is disclosed. The device includes a substrate having circuit component formed on a substrate surface. An upper inter level dielectric (ILD) layer is disposed over the substrate. The upper ILD layer includes a plurality of ILD levels. The device also includes a pair of magnetic tunneling junction (MTJ) stacks disposed in between adjacent ILD levels of the upper ILD layer. Each of the MTJ stack includes a fixed layer, a tunneling barrier layer and a free layer. The fixed layer has a first width. The tunneling barrier layer is formed on the fixed layer. The free layer is formed on the tunneling barrier layer. The free layer has a second width. The first width is wider than the second width.

DETAILED DESCRIPTION

Embodiments of the present disclosure generally relate to memory cells or devices. In one embodiment, the memory cells are magnetoresistive memory cells. For example, the memory devices may be spin transfer torque magnetoresistive random access memory (STT-MRAM) devices. Magnetoresistive memory cells include magnetic tunneling junction (MTJ) elements. Other suitable types of memory cells may also be useful. Such memory devices, for example, may be incorporated into standalone memory devices including, but not limited to, USB or other types of portable storage units, or integrated circuits (ICs), such as microcontrollers or system on chips (SoCs). The devices or ICs may be incorporated into or used with, for example, consumer electronic products, or relate to other types of devices.

FIGS. 1aand 1bshow simplified cross-sectional views of a memory element100along the bitline (BL) direction and wordline (WL) direction, respectively. The memory element100, in one embodiment, includes a magnetic tunnel junction (MTJ) stack sandwiched between a pair of electrodes. The memory element100, for example, is a magnetoresistive memory cell. The magnetoresistive memory cell may be a Spin Transfer Torque-Magnetoresistive Random Access Memory (STT-MRAM) cell. The electrode pair which includes first and second electrodes (not shown) are provided to the MTJ stack. The first electrode, for example, may be a bottom electrode while the second electrode may be a top electrode. The top and bottom electrodes may be formed of Ta. Other suitable types of electrodes may also be useful. For example, Ti, TaN, TiN or a combination of different electrode materials, including Ta, may also be useful. The MTJ stack is disposed in between the top and bottom electrodes. For example, the bottommost layer of the MTJ stack is disposed on the bottom electrode, while the top electrode is disposed on the uppermost layer of the MTJ stack. Other configurations of electrodes may also be useful.

The MTJ stack100is a stack of layers which includes a magnetically fixed (pinned) layer111, a tunneling barrier layer113, a free layer115and cap layer116. The MTJ stack100may also include a seed layer (not shown) and a bias layer (not shown). The seed layer may be disposed on the bottom electrode and the bias layer may be disposed on the seed layer. The seed layer may be a nickel-based alloy, for example, NiFe or NiCr. Other suitable alloys, apart from nickel-based alloys, may also be useful. The seed layer, for example, enables a smooth growth of the subsequently formed layers in a desired crystallinity. The bias layer may be an antiferromagnetic (AFM) layer. For example, the AFM layer may be metal alloys, such as Pt—Mn or Ir—Mn.

The fixed (pinned) layer111is disposed on the bias layer. The fixed (pinned) layer111may be a synthetic antiferromagnetic (SAF) layer. The SAF layer may include a first magnetic layer111a, a second magnetic layer111band a coupling layer111c. The first and second magnetic layers have opposite magnetizations and are separated by the coupling layer111c. The first magnetic layer111ais coupled to the bias layer. The coupling layer111cis disposed on the first magnetic layer111aand the second magnetic layer111bis disposed on the coupling layer111c. Since the magnetic layers are antiparallel coupled, a closure of the magnetic flux is formed within. As a result, stray magnetic field influences on the free layer115is minimized.

The magnetizations of the first and second magnetic layers are “pinned” via a direct exchange-bias coupling to the bias layer, so that the magnetization of the first and second magnetic layers does not flip (rotate) in the presence of an applied magnetic field. The magnetization or magnetic orientation in the second magnetic layer proximate to the free layer115acts as a fixed reference to the free layer115.

The first and second magnetic layers of the fixed layer111may be an alloy magnetic layer or a multilayer. For example, the magnetic layers may be a cobalt-iron-boron (CoFeB) alloy or a cobalt-iron (CoFe) alloy, or a multilayer of cobalt/platinum (Co/Pt), cobalt/palladium (Co/Pd) or cobalt/nickel (Co/Ni). The first magnetic layer may be thicker than the second magnetic layer to cancel the stray field acted upon the free layer. For example, the first magnetic layer may include n layer of Co/Pt, Co/Pd or Co/Ni, and the second magnetic layer may include m layer of Co/Pt, Co/Pd or Co/Ni, where n is an integer larger than m. In one embodiment, n and m may be less than 20 layers.

The coupling layer111cmay be a non-magnetic conductor. For example, the coupling layer111cmay be a ruthenium (Ru) layer. The Ru layer may be sufficiently thin. The thickness of the Ru layer may be chosen so that there is enough AFM exchange bias existing between the first and second magnetic layers. As a result, the magnetic moment orientation is stabilized in opposite direction.

The tunneling barrier layer113is disposed on the fixed (pinned) layer111. The tunneling barrier layer is a non-magnetic and electrically insulating layer. The tunneling barrier layer may be metal oxides, for example, MgO or Al2O3. Other metal oxides suitable for used in the MTJ element may also be useful.

The magnetically free layer115is disposed on the tunneling barrier layer113. The magnetic free layer115may be a CoFeB layer or a composite layer including CoFeB. The composite layer115may include a mono coupling stack or a dual coupling stack. The mono coupling stack includes a coupling layer sandwiched between two magnetic layers, i.e., magnetic layer/coupling layer/magnetic layer configuration. The dual coupling stack includes two mono coupling stacks with a shared magnetic layer in between, i.e., magnetic layer/coupling layer/magnetic layer/coupling layer/magnetic layer configuration. The magnetic layer may be CoFeB and the coupling layer maybe Ru. The thickness of the magnetic layers in the mono coupling stack and dual coupling stack may be substantially the same, whereas the coupling layer may be a thin layer suffices for coupling the magnetic layers.

The cap layer116is disposed on the free layer115. The cap layer116may be made of tantalum (Ta). The cap layer116protects the underlying free layer115.

Although the MTJ stack100is illustrated as having the various layers as shown inFIGS. 1a-1b, it is to be understood that the MTJ stack may include additional or lesser layers. Other suitable configurations or materials of the MTJ stack may also be useful.

As shown inFIG. 1a, the width w of the various layers of the MTJ element100is substantially the same along the bitline (BL) direction. Similarly, the length l of the various layers of the MTJ stack100along the wordline (WL) direction is also substantially the same, as shown inFIG. 1b.

There are two important requirements for a high density memory cell application, namely the intrinsic critical current (Ic) and thermal stability factor (A). The intrinsic critical current (Ic) of the MTJ element100is as follows:

Ic≈αP⁢4⁢⁢π·eℏ⁢Ms2·V(1)
where α denotes the damping constant, P denotes polarization, e denotes the magnitude of electron charge, ℏ denotes the Dirac constant, MSdenotes the saturation magnetization and V denotes the volume of the free layer. The intrinsic critical current (Ic) decreases proportionally with decreasing volume of the free layer, as shown in equation (1). Therefore, a reduction in the volume of the free layer allows for a smaller cell size to be formed and also reduces the intrinsic critical current.

The data retention time of a memory cell defines how long data can be properly kept in the memory cell and it depends significantly on the thermal stability of the MTJ. The thermal stability factor (Δ) of the MTJ is expressed as follows:

Δ=HK⁢Ms⁢V2⁢kB⁢T⁢∼⁢t⁡(1w-1l)⁢V⁢Ms2kB⁢T(2)
where HKdenotes uni-axial anisotropy, MSis the saturation magnetization, kBis the Boltzmann constant, V denotes the volume of the free layer, T denotes the absolute temperature, t, w and 1 respectively denote the thickness, width and length of the free layer. According to equation (2), the thermal stability factor (Δ) increases linearly with increasing volume of the free layer. However, an increase of the volume of the free layer results in an increase in the intrinsic critical current Ic, as shown in equation (1). Therefore, satisfying the two important requirements remains a huge challenge due to the trade-off relation of the intrinsic critical current and thermal stability factor.

FIGS. 2aand 2bshow a simplified cross-sectional view and a simplified front view of a single (individual) stack memory element200along the wordline (WL) direction and bitline (BL) direction, respectively. The memory element200, in one embodiment, includes a magnetic tunnel junction (MTJ) stack sandwiched between bottom and top electrodes. The memory element200, for example, is a magnetoresistive memory cell. The magnetoresistive memory cell may be a Spin Transfer Torque-Magnetoresistive Random Access Memory (STT-MRAM) cell. The memory element200, for example, is similar to that described inFIGS. 1a-1b. As such, common elements may not be described or described in detail. As shown inFIGS. 2aand 2b, the memory element200includes a bottom electrode220, a magnetically fixed (pinned) layer211, a tunneling barrier layer213, a hard mask layer214, a free layer215and a top electrode230.

Referring toFIG. 2a, the fixed layer211is disposed on the bottom electrode220. The tunneling barrier layer213is disposed on the fixed layer. In one embodiment, the tunneling barrier layer213is a thin layer. For example, the thickness of the tunneling barrier layer213may be about 1 nm to 3 nm. Other thickness of the tunneling barrier layer may also be useful. The hard mask layer214and free layer215are disposed on the tunneling barrier layer213. The hard mask layer214may be a dielectric layer, for example, a silicon nitride (SiN) layer. Other suitable dielectric layer may also be used as the hard mask layer. The hard mask layer214has a first side and an opposing second side. The free layer215has a first side and an opposing second side. The hard mask layer214and free layer215are abutting each other on one side, for example, a first side of the hard mask layer214is abutting a second side of the free layer215. The hard mask layer214has a first width w1and a first thickness t1. The first width w1of the hard mask layer214may be about 50 nm to 70 nm and the first thickness t1may be about 10 nm to 20 nm. The free layer215has a second width w2and a second thickness t2. The second width w2of the free layer215may be about 5 nm to 10 nm and the second thickness t2may be about 15 nm to 20 nm. Other thicknesses and widths of the hard mask layer214and free layer215may also be useful. In one embodiment, the first width w1of the hard mask layer214is wider than the second width w2of the free layer215. The first thickness t1of the hard mask layer214, in one embodiment, is less than the second thickness t2of the free layer215, such that the first side of the hard mask layer214abuts a lower portion of the second side of the free layer215. A top surface of the free layer215is higher than a top surface of the hard mask layer214.

The fixed layer211has a third width w3and a third thickness t3. The third width w3of the fixed layer211may be about 50 nm to 70 nm and the third thickness t3may be about 20 nm to 30 nm. Other thickness and width of the fixed layer211may also be useful. The third width w3of the fixed layer211defines the width w of the memory element200. The third width w3, i.e., the width of the memory element, is wider than the second width w2of the free layer215and the first width w1of the hard mask layer214. In one embodiment, the third width w3of the fixed layer is wider than the sum of the widths of the free layer215and hard mask layer214. The third thickness t3of the fixed layer211, in one embodiment, is more than the second thickness t2of the free layer215.

The top electrode230is disposed on the hard mask layer214. The top electrode230has a first side and an opposing second side. The top electrode230partially abuts the free layer215on one side. For example, a lower part of the first side of the top electrode230abuts an upper part of the second side of the free layer215. A top surface of the free layer215is lower than a top surface of the top electrode230. The top electrode230has a width that is substantially the same as the first width w1of the hard mask layer214.

As shown in the front view (FIG. 2b) of the memory element200, the tunneling barrier213is disposed on the fixed layer211and the free layer215is disposed on the tunneling barrier layer213. The free layer215has a second length l2that is less than the length l of the memory cell200, which is defined by the length of the fixed layer. In one embodiment, the second length l2may be about 50 nm to 70 nm and the length l of the memory cell may be about 50 nm to 70 nm. Other lengths of the free layer215and memory cell may also be useful. In one embodiment, the top electrode230has a length that is substantially the same as the length l2of the free layer215.

In conventional scaling to obtain a lower intrinsic critical current, the volume of the free layer is laterally reduced (i.e., a reduction in the width and length), while maintaining the thickness. However, due to the reciprocal of the width and length according to equation (2), a lateral reduction of the volume results in a reduced thermal stability factor, which is undesirable. The free layer215of the memory cell200has a reduced width, while maintaining the length. As a result, the thermal stability factor increases due to the reciprocal of the width. The configuration of the free layer215as described, i.e., reducing the width while maintaining the length, ensures that the volume is reduced for obtaining a lower intrinsic critical current. Furthermore, the configuration of the free layer as described also has less impact on the thermal stability as compared by the conventional scaling which reduces both the width and length. As a result, thermal stability degradation as commonly observed by the conventional free layer scaling can be mitigated.

In one embodiment, an adjacent memory element is configured as a mirror image of the memory element200.FIG. 3shows a simplified cross-sectional view of a memory element pair305along the wordline (WL) direction. The memory element pair includes a first single stack memory element200and a second single stack memory element300. The first memory element200, for example, is similar to that described inFIGS. 2a-2b. The second memory element300is the mirror image of the first element200. As such, common elements may not be described or described in detail.

In one embodiment, the memory element pair305is disposed in an interlevel dielectric (ILD) level (or layer) over a substrate (not shown). The ILD level is one of ILD levels of a device having a plurality of ILD levels. The number of the ILD levels may depend on, for example, design requirements or the logic process involved. All ILD level includes a metal level and a contact (or via) level. In one embodiment, the memory element pair305is disposed in a contact (or via) level of an ILD level. For example, the memory element pair305is disposed in the contact level Vx-1between metal levels Mx-1and Mx. The metal level Mxand contact level Vx-1, in one embodiment, may be the uppermost ILD level. The contact level includes a storage dielectric layer (not shown). The storage dielectric layer may be a dedicated storage dielectric layer disposed over dielectric layer335and is not part of an interconnect level. Other configurations of storage dielectric layer may also be useful. The bottom electrode320is coupled to a drain of a select transistor (not shown). For example, the bottom electrode320is coupled to a contact pad in the M1level and a via contact in the CA level (i.e., the first contact level of the first ILD level). Other configurations of coupling the bottom electrode may also be useful. The top electrode330is coupled to a bitline (BL). For example, the top electrode is coupled to the BL disposed in M2level. The BL is along a bitline direction. As for the source of the select transistor, it is coupled to a source line (SL). For example, a via contact in CA is provided to couple the source to SL in M1. Providing SL and BL in other suitable metal levels and providing the memory element pair in between any suitable adjacent metal levels may also be useful.

FIGS. 4aand 4bshow a simplified cross-sectional view and a simplified front view of another embodiment of a single (individual) stack single memory element400along the wordline (WL) direction and bitline (BL) direction, respectively. The memory element400, in one embodiment, includes a magnetic tunnel junction (MTJ) stack sandwiched between bottom and top electrodes. The memory element400, for example, is a magnetoresistive memory cell. The magnetoresistive memory cell may be a Spin Transfer Torque-Magnetoresistive Random Access Memory (STT-MRAM) cell. The memory element400, for example, is similar to that described inFIGS. 1a-1b. As such, common elements may not be described or described in detail. As shown inFIGS. 4aand 4b, the memory element400includes a bottom electrode420, a magnetically fixed (pinned) layer411, a tunneling barrier layer413, a hard mask layer414, a free layer415and a top electrode430.

Referring toFIG. 4a, the fixed layer411is disposed on the bottom electrode420. The tunneling barrier layer413is disposed on the fixed layer411. The tunneling barrier layer413and hard mask layer414are disposed on the fixed layer411. The hard mask layer414may be a dielectric layer, for example, a silicon nitride (SiN) layer. Other suitable dielectric layer may also be used as the hard mask layer. The hard mask layer414has a first side and an opposing second side. The tunneling barrier layer413is a horizontally flipped L-shape structure having a vertical portion and a left-extending horizontal portion. The vertical portion has an outer side and an inner side. The left-extending horizontal portion has an upper side and a lower side. The lower side of the left-extending horizontal portion abuts the fixed layer411. The hard mask layer414and tunneling barrier layer413are abutting each other on one side. For example, the first side of the hard mask layer414is abutting the outer side of the vertical portion of the tunneling barrier layer413.

The free layer415has a first side and an opposing second side. The free layer415is disposed on the tunneling barrier layer413. In one embodiment, the free layer415is disposed on the left-extending horizontal portion. The second side of the free layer415abuts the inner side of the vertical portion of the tunneling barrier layer413.

The hard mask layer414has a first width w1and a first thickness t1. The first width w1of the hard mask layer414may be about 50 nm to 80 nm and the first t1thickness a may be about 10 nm to 20 nm. The free layer415has a second width w2and a second thickness t2. The second width w2of the free layer415may be about 5 nm to 10 nm and the second thickness t2may be about 15 nm to 20 nm. Other thicknesses and widths of the hard mask layer414and free layer415may also be useful. In one embodiment, the first width w1of the hard mask layer414is wider than the second width w2of the free layer415. The second thickness t2of the free layer415is less than the first thickness a of the hard mask layer414due to the presence of the tunneling barrier layer413underneath the free layer415. In one embodiment, the tunneling barrier layer413has a uniform thickness. For example, the vertical portion has the same thickness as the left-extending horizontal portion. The thickness of the tunneling barrier layer413may be about 1 nm to 3 nm. Other thickness of the tunneling barrier layer may also be useful.

The fixed layer411has a third width w3and a third thickness t3. The third width w3of the fixed layer411may be about 50 nm to 70 nm and the third thickness t3may be about 20 nm to 30 nm. Other thickness and width of the fixed layer411may also be useful. The third width w3defines the width of the memory element400. The third width w3of the fixed layer411is wider than the second width w2of the free layer415and the first width w1of the hard mask layer414. In one embodiment, the third width w3of the fixed layer is wider than the sum of the widths of the free layer415and hard mask layer414. The third thickness t3of the fixed layer411is more than the second thickness t2of the free layer415.

In one embodiment, the tunneling barrier layer413, hard mask layer414and free layer415have a coplanar top surface. The top electrode430is disposed on the coplanar top surface of the tunneling barrier layer413, hard mask layer414and free layer415. The top electrode430has a width that is substantially the same as the third width w3of the fixed layer411.

As shown in the front view (FIG. 4b) of the memory element400, the tunneling barrier413is disposed on the fixed layer411and the free layer415is disposed on the tunneling barrier layer413. The free layer415has a second length l2that is less than the length l of the memory cell400, which is defined by the length of the fixed layer. In one embodiment, the second length l2may be about 50 nm to 70 nm and the length l of the memory cell may be about 50 nm to 70 nm. Other lengths of the free layer415and memory cell may also be useful. In one embodiment, the top electrode430has a length that is substantially the same as the length l2of the free layer415.

In conventional scaling to obtain a lower intrinsic critical current, the volume of the free layer is laterally reduced (i.e., a reduction in the width and length), while maintaining the thickness. However, due to the reciprocal of the width and length according to equation (2), a lateral reduction of the volume results in a reduced thermal stability factor, which is undesirable. The free layer415of the memory cell400has a reduced width, while maintaining the length. As a result, the thermal stability factor increases due to the reciprocal of the width. The configuration of the free layer415as described, i.e., reducing the width while maintaining the length, ensures that the volume is reduced for obtaining a lower intrinsic critical current. Furthermore, the configuration of the free layer as described also has less impact on the thermal stability as compared by the conventional scaling which reduces both the width and length. As a result, thermal stability degradation as commonly observed by the conventional free layer scaling can be mitigated.

In one embodiment, an adjacent memory element is configured as a mirror image of the memory element400.FIG. 5shows a simplified cross-sectional view of a memory element pair505along the wordline (WL) direction. The memory element pair includes a first single stack memory element400and a second single stack memory element500. The first memory element400, for example, is similar to that described inFIGS. 4a-4b. The second memory element500is the mirror image of the first element400. As such, common elements may not be described or described in detail.

Referring toFIG. 5, the tunneling barrier layer513and hard mask layer514are disposed on the fixed layer411. The hard mask layer514has a first sidewall and an opposing second sidewall. The tunneling barrier layer513is a L-shape structure having a vertical portion and a right-extending horizontal portion. The vertical portion has an outer side and an inner side. The right-extending horizontal portion has an upper side and a lower side. The lower side of the right-extending horizontal portion abuts the fixed layer411. The hard mask layer514and tunneling barrier layer513are abutting each other on one side. For example, the second sidewall of the hard mask layer514is abutting the outer side of the vertical portion of the tunneling barrier layer513.

The free layer515has a first side and an opposing second side. The free layer515is disposed on the tunneling barrier layer513. In one embodiment, the free layer515is disposed on the right-extending horizontal portion. The first side of the free layer515abuts the inner side of the vertical portion of the tunneling barrier layer513. Similar to the memory element400, the top electrode430is disposed on the planar top surface of the hard mask layer514, tunneling barrier layer513and free layer515.

In one embodiment, the memory element pair505is disposed in an interlevel dielectric (ILD) level (or layer) of a substrate (not shown). The ILD level is one of ILD levels of a device having a plurality of ILD levels. The number of the ILD levels may depend on, for example, design requirements or the logic process involved. All ILD level includes a metal level and a contact (or via) level. In one embodiment, the memory element pair505is disposed in a contact (or via) level of an ILD level. For example, the memory element pair505is disposed in the contact level Vx-1between metal levels Mx-1and Mx. The metal level Mxand contact level Vx-1, in one embodiment, is the uppermost ILD level. The contact level includes a storage dielectric layer. The storage dielectric layer may be a dedicated storage dielectric layer disposed over dielectric layer535and is not part of an interconnect level. Other configurations of storage dielectric layer may also be useful. The bottom electrode420is coupled to a drain of a select transistor (not shown). For example, the bottom electrode420is coupled to a contact pad in the M1level and a via contact in the CA level (i.e., the first contact level of the first ILD level). Other configurations of coupling the bottom electrode may also be useful. The top electrode430is coupled to a bitline (BL). For example, the top electrode is coupled to the BL disposed in M2level. The BL is along a bitline direction. As for the source of the select transistor, it is coupled to a source line (SL). For example, a via contact in CA is provided to couple the source to SL in M1. Providing SL and BL in other suitable metal levels and providing the memory element pair in between any suitable adjacent metal levels may also be useful.

FIG. 6shows a simplified cross-sectional view of a single stack dual memory element600along the wordline (WL) direction. The single stack dual memory element600includes two memory elements. Each of the memory elements, in one embodiment, includes a magnetic tunnel junction (MTJ) sandwiched between a pair of electrodes. The memory element, for example, is a magnetoresistive memory cell. The magnetoresistive memory cell may be a Spin Transfer Torque-Magnetoresistive Random Access Memory (STT-MRAM) cell. The continual memory element600, for example, is similar to the memory element pair505described inFIG. 5. As such, common elements may not be described or described in detail.

As shown inFIG. 6, the single stack dual memory element600includes a first memory element600aand a second memory element600b. The first memory element600ais similar to the memory element400and the second memory element is similar to the memory element500. The first memory element600aincludes a first bottom electrode620a, a first fixed layer611a, a first tunneling barrier layer613a, a first free layer615aand a first top electrode630a. The second element600bincludes a second bottom electrode620b, a second fixed layer611b, a second tunneling barrier layer613b, a second free layer615band a second top electrode630b. The first and second elements, for example, share a common hard mask layer614.

Referring toFIG. 6, the first fixed layer611aand second fixed layer611bare separated by a first gap670. In one embodiment, the gap670follows the BEOL minimum design rules. For example, the gap is about 40 nm for a metal or via minimum distance of 60 nm to 80 nm. The hard mask layer614is disposed over the first fixed layer611aand second fixed layer611b. The hard mask614includes a first sidewall and an opposing second sidewall. The hard mask layer614, in one embodiment, is a continuous layer. For example, the first sidewall of the hard mask layer abuts the outer side of the vertical portion of the first tunneling barrier layer613aand the second sidewall abuts the outer side of the vertical portion of the second tunneling barrier layer613b. The continuous hard mask layer614bridges the first gap670between the first fixed layer611aand second fixed layer611b. For example, a middle portion of the hard mark layer614fills the first gap670between the first fixed layer611aand second fixed layer611b. The hard mask layer614, being a dielectric layer (e.g., a silicon nitride layer), isolates the first memory element600aand second memory element600b. In one embodiment, the width of the hard mask layer may be about 150 nm to 250 nm. Other suitable width of the hard mask layer may also be useful.

In one embodiment, the first tunneling barrier layer613a, second tunneling barrier layer613b, hard mask layer614, first free layer615aand second free layer615bhave a coplanar top surface. The first top electrode630aand second top electrode630bare disposed on the coplanar top surface. The first top electrode630aand second top electrode630bare separated by a second gap680. The second gap680, in one embodiment, is aligned with the first gap670separating the first and second fixed layers611aand611b. The first top electrode630ais aligned with the first fixed layer611a, while the second top electrode630bis aligned with the second fixed layer611b.

In one embodiment, the single stack dual memory element600is disposed in an interlevel dielectric (ILD) level (or layer) of a substrate (not shown). The ILD level is one of ILD levels of a device having a plurality of ILD levels. The number of the ILD levels may depend on, for example, design requirements or the logic process involved. All ILD level includes a metal level and a contact (or via) level. In one embodiment, the single stack dual memory element600is disposed in a contact (or via) level of an ILD level. For example, the single stack dual memory element600is disposed in the contact level Vx-1between metal levels Mx-1and Mx. The metal level Mxand contact level Vx-1, in one embodiment, correspond to the uppermost ILD level. The contact level includes a storage dielectric layer. The storage dielectric layer may be a dedicated storage dielectric layer disposed over dielectric layer635and is not part of an interconnect level. Other configurations of storage dielectric layer may also be useful. The bottom electrode620is coupled to a drain of a select transistor (not shown). For example, the bottom electrode620is coupled to a contact pad in the M1level and a via contact in the CA level (i.e., the first contact level of the first ILD level). Other configurations of coupling the bottom electrode may also be useful. The top electrode630is coupled to a bitline (BL). For example, the top electrode is coupled to the BL disposed in M2level. The BL is along a bitline direction. As for the source of the select transistor, it is coupled to a source line (SL). For example, a via contact in CA is provided to couple the source to SL in M1. Providing SL and BL in other suitable metal levels and providing the memory element pair in between any suitable adjacent metal levels may also be useful.

In conventional scaling to obtain a lower intrinsic critical current, the volume of the free layer is laterally reduced (i.e., a reduction in the width and length), while maintaining the thickness. However, due to the reciprocal of the width and length according to equation (2), a lateral reduction of the volume results in a reduced thermal stability factor, which is undesirable. The free layers of the single stack dual memory element600have a reduced width, while maintaining the length. As a result, the thermal stability factor increases due to the reciprocal of the width. The configuration of the free layers as described, i.e., reducing the width while maintaining the length, ensures that the volume is reduced for obtaining a lower intrinsic critical current. Furthermore, the configuration of the free layer as described also has less impact on the thermal stability as compared by the conventional scaling which reduces both the width and length. As a result, thermal stability degradation as commonly observed by the conventional free layer scaling can be mitigated.

FIGS. 7a-7oshow simplified cross-sectional views of a process700of forming an embodiment of a memory device along the wordline (WL) direction. The device formed by process700includes a memory element pair. The memory element pair includes a first single stack memory element and a second single stack memory element. The memory element pair, for example, is similar to that described inFIG. 3. Common elements may not be described or described in detail. Each of the memory element, in one embodiment, includes a magnetic tunnel junction (MTJ) stack sandwiched between bottom and top electrodes. The memory element, for example, is a magnetoresistive memory cell. The magnetoresistive memory cell may be a Spin Transfer Torque-Magnetoresistive Random Access Memory (STT-MRAM) cell.

Although the cross-sectional views show two memory elements, it is understood that the device includes a plurality of memory elements of, for example, a memory array. In addition, the memory elements can be formed simultaneously with CMOS logic devices on the same substrate.

The simplified cross-sectional views illustrate an ILD level790. For example, a substrate (not shown) has been processed with FEOL and BEOL processing to include the ILD level. FEOL processing, for example, forms transistors, including a select transistor of the memory cell. Other types of devices may also be formed on the same substrate. BEOL processing forms interconnects in ILD levels. The FEOL and part of the BEOL processing will not be illustrated. The substrate (not shown), for example, is processed up to the stage where an ILD level790which includes a via level792and a metal level794is formed. For example, the ILD level790includes V4and M5. The via level V4includes via contacts793. The metal level, as shown, includes interconnects. For example, an interconnect795ais a cell contact pad for coupling to a memory element and an interconnect795bfor coupling to a pad interconnect. The interconnects, for example, are copper interconnects. Other suitable types of interconnects may also be useful.

Referring toFIG. 7a, a dielectric liner758, in one embodiment, is disposed above the metal level M5. The dielectric liner, for example, serves as an etch stop layer. The dielectric liner may be a low k dielectric liner. For example, the dielectric liner may be nBLOK. Other types of dielectric materials for the dielectric liner may also be useful. The dielectric liner, for example, is formed by CVD. Other suitable techniques for forming the dielectric liner may also be useful.

The process continues to form a dielectric layer760. As shown inFIG. 7b, a dielectric layer760is formed on the ILD level790. For example, the dielectric layer is formed on the dielectric liner758. The dielectric layer, for example, may be formed by CVD. Other suitable forming techniques or suitable thicknesses for the dielectric layer may also be useful.

InFIG. 7c, the dielectric layer is patterned to form memory element opening764. The memory element opening764, for example, is a via opening for accommodating a lower portion of a subsequently formed memory element stack. The memory element opening exposes a cell contact pad795ain the metal level below. The opening may be formed by mask and etch techniques. For example, a patterned photoresist mask may be formed over the dielectric layer, serving as an etch mask. An etch, such as RIE, may be performed to pattern the dielectric layer using the patterned resist etch mask. In one embodiment, the etch transfers the pattern of the mask to the dielectric layer, including the dielectric liner to expose the cell contact pad below.

Referring toFIG. 7d, the process continues to form memory element stacks. The memory element stacks may be magnetic storage stacks. The magnetic storage stacks are, for example, the MTJ stacks, similar to that describe inFIG. 3. Each of the MTJ stack may include various layers configured as a top-pinned or bottom-pinned MTJ stack. Each of the MTJ stack forms a storage unit of a MRAM cell.

The MTJ stack, for example, is disposed between top and bottom electrodes. The bottom electrode is coupled to a contact pad in the metal level below. For example, the bottom electrode is coupled to the contact pad795ain M5. This provides connections of the MTJ stack to a first S/D region of a cell select transistor. As for the top electrode, it is exposed over the top surface of the MTJ stack.

The various layers of the MTJ stack are formed on the substrate. For example, the various layers of the MTJ stack are sequentially formed over the dielectric layer and filling the openings. After the openings764are formed, a bottom electrode layer720, such as Ta or TaN is deposited over the dielectric layer and fills the openings as shown inFIG. 7d. A chemical mechanical polishing (CMP) process is applied to form an embedded bottom electrode in the opening764and remove excess bottom electrode layer in other areas. Other suitable bottom electrode materials and techniques may be employed. The bottom electrode320fills the opening and the surface is flat as shown inFIG. 7e.

As shown inFIG. 7f, a fixed layer711and a tunneling barrier layer713are sequentially formed on the uppermost dielectric layer. For example, the fixed layer711is formed on the dielectric layer760and the tunneling barrier layer713is subsequently formed on the fixed layer711. The layers may be formed by physical vapor deposition (PVD) process.

InFIG. 7g, the layers are patterned by mask and etch techniques to form two stacks of fixed layer311and tunneling barrier layer313. For example, a first lithography mask may be used to pattern a photoresist layer that is formed over the tunneling barrier layer713. The patterned photoresist layer serves as an etch mask. An etch, such as RIE, may be performed to pattern the layers using the patterned resist as an etch mask. The first stack of patterned fixed layer311and tunneling barrier layer313is separated from the second stack of patterned fixed layer311and tunneling barrier layer313by a first gap740.

As shown inFIG. 7h, a hard mask layer714is formed over the dielectric layer760, covering the patterned fixed layer311and tunneling barrier layer313. The hard mask layer714fills the gaps740between the two stacks of patterned fixed layer and tunneling barrier layer. A top electrode layer730is subsequently formed on the hard mask layer714. The layers may be formed by PVD process.

The layers are patterned by mask and etch technique to form a hard mask layer314and a top electrode330as shown inFIG. 7i. For example, a second lithography mask may be used to pattern a photoresist layer that is formed over the top electrode layer730. The patterned photoresist layer serves as an etch mask. An etch, such as RIE, may be performed to pattern the layers using the patterned resist. The patterned layers have sidewalls that are displaced from the sidewalls of the patterned fixed layer311and tunneling barrier layer313, such that the outer portions of the tunneling barrier layer313of the first and second stacks are exposed. The patterned layers also bridge the two stacks, such that the first gap740remains filled by the hard mask layer.

A conformal free layer is formed over the patterned layers. The conformal free layer is formed by a PVD process. The conformal free layer is subsequently patterned to form free layer315in the form of spacer on the sidewalls of the hard mask layer314and top electrode330, as well as on a portion of the outer portions of the tunneling barrier layer313. An anisotropic etch, such as RIE, may be used to remove horizontal portions of the conformal free layer, leaving free layer315in the form of spacer on the sidewalls of the hard mask layer314and top electrode layer330. In one embodiment, the top surface of the free layer315is below the top surface of the top electrode330but above the upper surface of the hard mask layer314, as shown inFIG. 7j. A corresponding top view of the partially processed device is shown inFIG. 7k. For the purpose of illustration, the substrate is omitted. As shown, the free layer315surrounds the perimeter of the patterned stack which includes the hard mask layer314and top electrode layer330, leaving outer edges of the tunneling barrier layer313exposed.

As shown inFIG. 7l, the layers, except the fixed layer311and tunneling barrier layer313, are further patterned to form individual memory elements. The layers are patterned by mask and etch techniques to form a first memory element200and a second memory element300. For example, a third lithography mask may be used to pattern a photoresist layer that is formed over the layers of the memory elements. The patterned photoresist layer serves as an etch mask. An etch, such as RIE, may be performed to pattern the layers using the patterned resist etch mask. The first memory element200, for example, is similar to that described inFIGS. 2a-2b. The second memory element300, for example, is the mirror image of the first memory element200. A corresponding top view of the partially processed device is shown inFIG. 7m. For the purpose of illustration, the substrate is omitted. As shown, the first and second memory elements are separated by a second gap743which is substantially the same as the first gap740and the patterned free layers315of the individual memory elements are in the form of spacers disposed on a sidewall of the hard mask layer314.

A dielectric layer750is formed on the substrate, as shown inFIG. 7n. The dielectric layer750is formed over the dielectric layer760and sufficiently covers the memory elements. The dielectric layer750, for example, is silicon oxide. Other types of dielectric layers may also be useful. The dielectric layer may be formed by CVD. Other techniques for forming the dielectric layer may also be useful. The dielectric layer750and dielectric layer760correspond to a storage dielectric layer.

A planarizing process is performed on the substrate, planarizing the dielectric layer750. The planarizing process, for example, is a CMP process. The CMP produces a planar top surface between the top of the memory elements and dielectric layer750.

The dielectric layers and the dielectric liner are patterned to form a via opening776at the logic region. The via opening is patterned by mask and etch techniques. The via opening penetrates through the various dielectric layers. This exposes the interconnect795bin the lower metal level. After forming the via opening, the mask layer is removed. For example, the mask and ARC layers are removed.

Referring toFIG. 7o, a conductive layer is formed on the substrate. The conductive layer covers the dielectric layer and MTJ stacks as well as filling the via opening. In one embodiment, the conductive layer is a copper layer. For example, the copper layer is used to form metal line and/or interconnect pads. Other suitable types of conductive layers may also be useful. The conductive layer may be formed by, for example, sputtering. Other suitable techniques for forming the conductive layer may also be useful.

The conductive layer is patterned to form metal lines768and interconnect762. Patterning the conductive layer to form the metal lines and interconnect may be achieved by mask and etch techniques. For example, a patterned photoresist mask may be formed over the conductive layer. An etch, such as RIE, may be used to pattern the conductive layer with a patterned resist mask. In one embodiment, the interconnect762includes a via contact764in the via opening and a contact pad766. The metal line768, for example, serves as the bitline BL. After patterning the conductive layer, the mask layer is removed. For example, the mask and ARC layers are removed.

Additional processes may be performed to complete forming the device. For example, the processes may include forming additional ILD levels, pad level, passivation level, pad opening, dicing, assembly and testing. Other types of processes may also be performed.

FIGS. 8a-8ishow simplified cross-sectional views of a process800of forming an embodiment of a memory device along the wordline (WL) direction. The device formed by process800includes a single stack dual memory element. The single stack dual memory element includes a first memory element600aand a second memory element600b, similar to those described inFIG. 6. Common elements may not be described or described in detail. The process may contain similar elements or process steps as the process700described inFIGS. 7a-7o. As such, the common elements or process steps may not be described or described in detail.

Each of the memory element, in one embodiment, includes a magnetic tunnel junction (MTJ) stack sandwiched between bottom and top electrodes. The memory element, for example, is a magnetoresistive memory cell. The magnetoresistive memory cell may be a Spin Transfer Torque-Magnetoresistive Random Access Memory (STT-MRAM) cell.

Although the cross-sectional views show two memory elements, it is understood that the device includes a plurality of memory elements of, for example, a memory array. In addition, the memory elements can be formed simultaneously with CMOS logic devices on the same substrate.

Referring toFIG. 8a, a partially processed device is provided. The device, as shown, is at the stage of processing as described inFIG. 7e. For example, a bottom electrode320fills the opening and the surface is flat.

As shown inFIG. 8b, a fixed layer811is formed on the uppermost dielectric layer. For example, the fixed layer811is formed on the dielectric layer760. The layer may be formed by physical vapor deposition (PVD) process.

InFIG. 8c, the fixed layer811is patterned by mask and etch techniques to form two stacks of fixed layer611. For example, a first lithography mask may be used to pattern a photoresist layer that is formed over the fixed layer811. The patterned photoresist layer serves as an etch mask. An etch, such as RIE, may be performed to pattern the layer using the patterned resist etch mask. The first stack of patterned fixed layer611is separated from the second stack of patterned fixed layer611by a gap740.

As shown inFIG. 8d, a hard mask layer is formed over the dielectric layer760, covering the patterned fixed layer611. The hard mask layer may be formed by PVD process. The hard mask layer fills the gap740between the two stacks of patterned fixed layer611. The hard mask layer is patterned by mask and etch to form a patterned hard mask layer614. The sidewalls of the patterned hard mask layer614are displaced from the sidewalls of the patterned fixed layer611, such that outer portions of the patterned fixed layers are exposed. For example, a second lithography mask may be used to pattern a photoresist layer that is formed over the hard mask layer. The patterned photoresist layer serves as an etch mask. An etch, such as RIE, may be performed to pattern the hard mask layer using the patterned resist mask.

A tunneling barrier layer is formed on the dielectric layer760. For example, the tunneling barrier layer is formed on the dielectric layer760, covering the patterned fixed layer611and patterned hard mask layer614. The layer may be formed by PVD process. In one embodiment, the tunneling barrier layer is a conformal layer. The thickness of the conformal tunneling barrier layer is uniform over vertical and horizontal surfaces. A conformal free layer is subsequently formed on the tunneling barrier layer, for example, by PVD. An anisotropic etch, such as RIE, may be used to remove the free layer and tunneling barrier layer, forming an L-shaped tunneling barrier layer and a free layer in the form of spacer615on the sidewalls of the L-shaped tunneling barrier layer. Due to the presence of the free layer spacer615, the patterned tunneling barrier layer613resembles an L-shape structure on one side of the hard mask layer614and a horizontally flipped L-shape structure on the opposing side of the hard mask layer614, as shown inFIG. 8e.

A corresponding top view of the partially processed device is shown inFIG. 8f. As shown, the tunneling barrier layer613surrounds the perimeter of the hard mask layer614, while the free layer615surrounds the perimeter of the tunneling barrier layer613, leaving the fixed layer611exposed.

In one embodiment, the layers are subsequently patterned by mask and etch techniques to form a memory element pattern. The top view of the memory element pattern is shown inFIG. 8g. For example, a third lithography mask may be used to pattern a photoresist layer that is formed over the top surfaces of the layers. The patterned photoresist layer serves as an etch mask. An etch, such as RIE, may be performed to pattern the layer using the patterned resist mask and the patterned free layers615are in the form of spacers disposed adjacent to the L-shaped tunneling barrier layer.

InFIG. 8h, a dielectric layer750is formed on the substrate. The dielectric layer750is formed over the dielectric layer760and sufficiently covers the memory element. The dielectric layer, for example, is silicon oxide. Other types of dielectric layers may also be useful. The dielectric layer may be formed by CVD. Other techniques for forming the dielectric layer may also be useful. The dielectric layer750and dielectric layer760correspond to a storage dielectric layer.

A planarizing process is performed on the substrate, planarizing the dielectric layer750. The planarizing process, for example, is a CMP process. The CMP produces a planar top surface between the top of the memory elements and dielectric layer750.

In another embodiment, the portion of the hard mask layer which fills the gap740and the portion above the gap740is removed, leaving a gap in between. Subsequently, the gap is filled by the dielectric layer750. For example, a dielectric layer is formed in the gap and subsequently the dielectric layer750is formed on the substrate in a process step as illustrated inFIG. 8h. Such processing results in the configuration of memory element pair505as shown inFIG. 5.

Referring toFIG. 8i, a top electrode layer is subsequently formed on the planar top surface. The top electrode layer is patterned by a mask and etch to form individual top electrodes630. For example, the first lithography mask may be used to pattern a photoresist layer that is formed on the top electrode layer. The patterned photoresist serves as an etch mask. An etch, such as RIE, may be performed to pattern the layer using the patterned resist mask.

The forming of the individual top electrodes630completes the formation of the single stack dual memory element600ofFIG. 6. The single stack dual memory element includes a first memory element600aand a second memory element600bseparated by a gap743.

Additional processes may be performed to complete forming the device. For example, the processes may include the processes illustrated inFIGS. 7n-7o, as wells as forming additional ILD levels, pad level, passivation level, pad opening, dicing, assembly and testing. Other types of processes may also be performed.

The process as described inFIGS. 7a-7oandFIGS. 8a-8iresult in advantages. The process700or800as described is highly compatible with logic processing or technology. This avoids the investment of new tools and the process enables MTJ elements with reduced intrinsic critical current Ic without compromising thermal stability factor to be formed.