Data serialization circuit

The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

BACKGROUND

Field of the Invention

The invention is directed to a data serialization circuit and more particularly, to the data serialization circuit with lower jitter re-sampling scheme.

Description of Related Art

In conventional art, a plurality of clock trees are necessary for an integrated circuit (IC). The clock trees are used to provide a plurality of clock signals to a core circuit of the IC. The core circuit can sample data by using the clock signals. Under a noisy power and/or ground environment, jitter of each of the clock signals increases according to number of delay stages of the clock tree for generating each of the clock signals. As a result, size of a window of an eye diagram corresponding to data sampled by the clock signal with higher jitter is reduced. Quality of the sampled data declines correspondingly.

SUMMARY

The invention provides a plurality of data serialization circuits for lower jitter of sampled data.

The invention is directed to the data serialization circuit including a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit includes a plurality of delay stages, receives an input clock signal and generates a plurality of delayed clock signals. The delay stages include a first delay stage and a second delayed stage prior to the first delay stage. The delayed clock signals include a first delayed clock signal generated by the first delay stage and a second delayed clock signal generated by the second delay stage. The data serializer is coupled to the delay circuit. The data serializer is receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. The first data sampler and a second data sampler are coupled in series, and are coupled to the delay circuit and the data serializer. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

The invention is also directed to another data serialization circuit including a delay circuit, a data serializer, a plurality of data samplers and an output decision circuit. The delay circuit includes a plurality of delay stages, receives an input clock signal and generates a plurality of delayed clock signals. The delay stages include a first delay stage and a second delayed stage prior to the first delay stage. The delayed clock signals include a first delayed clock signal generated by the first delay stage and a second delayed clock signal generated by the second delay stage. The data serializer is coupled to the delay circuit, receives parallel data and the first delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the first delayed clock signal. The data samplers are coupled to the delay circuit, wherein, the data samplers respectively sample input serial data to generate a plurality of sampled serial data according to a plurality of sampling clock signals. The output decision circuit is coupled to the data samplers, receives the plurality of sampled serial data and selects one of the plurality of sampled serial data to be an output serial data according to the plurality of sampled serial data.

In an embodiment of the invention, wherein the output decision circuit includes a transition detection circuit, a voting circuit, a clock selection circuit and a selector. The transition detection circuit is coupled to the data samplers, receives the plurality of sampled serial data and determines which one of the sampling clock signals hits transition regions of the serial data by monitoring the plurality of sampled serial data to generate detection information. The voting circuit is coupled to the transition detection circuit, receives a plurality of the detection information and determines a majority of the plurality of the detection information to generate a voting result. The clock selection circuit is coupled to the voting circuit, and generates a selecting signal according to the voting result. The selector is coupled to the clock selection circuit and the data samplers, and selects one of the plurality of sampled serial data to be as the output serial data according to the selecting signal.

To sum up, the invention provides a plurality of data samplers for re-sampling the serial data to generate the output serial data. The serial data is generated according to a delayed clock signal, and the data samplers re-sample the serial data according to another delayed clock signal(s) prior to the delayed clock signal. Such as that, jitter of the output serial data can be reduced, and quality of the output serial data can be improved.

DESCRIPTION OF EMBODIMENTS

Please refer toFIG. 1, which illustrates a schematic diagram of a data serialization circuit100according to an embodiment of present disclosure. The data serialization circuit100includes a delay circuit110, a data serializer120and data samplers130-132. The delay circuit110receives an input clock signal CK0and generates a plurality of delayed clock signals dCK2-dCK0by delaying the input clock signal CK0sequentially. The delay circuit110includes a plurality of delay stages, such as three delay stages111-113as an example shown inFIG. 1. Wherein, the delay stages111-113are coupled in series, and respectively generate the delayed clock signals dCK2-dCK0. In this embodiment, the delayed clock signals dCK2is prior to the delayed clock signals dCK1, and the delayed clock signals dCK1is prior to the delayed clock signals dCK0. The delay stage113is a final delay stage and the delayed clock signal dCK0is a final stage delayed clock signal.

It can be seen, since the delayed clock signals dCK2is prior to the delayed clock signals dCK1and the delayed clock signals dCK1is prior to the delayed clock signals dCK0, jitter of the delayed clock signals dCK2is less than jitter of the delayed clock signals dCK1, and jitter of the delayed clock signals dCK1is less than jitter of the delayed clock signals dCK0.

Each of the delay stages111-113can be implemented by one or more logic buffers. Or, in some embodiments, each of the delay stages111-113can be implemented by any other component which can delay a periodic signal.

The data serializer120is coupled to the delay circuit110, and receives the delayed clock signals dCK0generated by the delay stage113which is a final stage of the delay stages111-113. The data serializer120also receives parallel data PDATA and converts the parallel data PDATA into serial data SDATA according to the final stage delayed clock signal (i.e., the delayed clock signals dCK0).

The data serializer120can be implemented by any parallel signal to serial signal converting circuit well known by a person skilled in the art. For example, the data serializer120may pre-store the parallel data PDATA into a shift register, and shift out the parallel data PDATA in the shift register to generate the serial data SDATA according to the delayed clock signals dCK0.

The data samplers130-132are coupled to the data serializer120in series. The data sampler130receives the serial data SDATA from the data serializer120, and receives the delayed clock signals dCK0. The data sampler130samples the serial data SDATA according to the delayed clock signal dCK0to generate an output serial data OSDATA0. The data sampler131is coupled to the data sampler130, and receives the output serial data OSDATA0and the delayed clock signal dCK1. The data sampler131samples the output serial data OSDATA0according to the delayed clock signal dCK1to generate an output serial data OSDATA1. Further, the data sampler132is coupled to the data sampler131, and receives the output serial data OSDATA1and the delayed clock signal dCK2. The data sampler132samples the output serial data OSDATA1according to the delayed clock signal dCK2to generate an output serial data OSDATA2.

In the present embodiment, the data serialization circuit100samples the serial data SDATA by the data samplers130-132according to the delayed clock signals dCK0-dCK2in sequence. As can be seen from a prior delay stage to a later delay stage, the jitter of the delayed clock signals increases gradually. On the other side, as seen from the later delay stage to the prior delay stage, the jitter of the delayed clock signals are regarded as decreasing gradually. Since jitter of the delayed clock signal dCK1generated by the relatively prior delay stage112is smaller than jitter of the final stage delayed clock signal dCK0generated by the final delay stage113, jitter of the output serial data OSDATA1may be smaller than jitter of the output serial data OSDATA0generated by using the final stage delayed clock signal dCK0having large jitter. Similarly, since jitter of the delayed clock signal dCK2generated by the relatively prior delay stage111is smaller than jitter of the delayed clock signal dCK1generated by the relatively later delay stage112, jitter of the output serial data OSDATA2may be even smaller than the jitter of the output serial data OSDATA1. In other words, the jitter of the output serial data OSDATA0-OSDATA2can decrease gradually by using the delayed clock signals which have gradually smaller jitter to do sampling.

Please refer toFIG. 2, which illustrates a relationship diagram between the delayed clock signals and the data samplers according to an embodiment of present disclosure. InFIG. 2, delayed clock signals dCK(m−1), dCK(m−2) and dCK(m−3) are respectively generated by different middle delay stages of the delay circuit110which has a plurality of delay stages, and a delayed clock signal dCK0is a final stage delayed clock signal generated by the final delay stage of the delay circuit110, wherein m is an integer larger than 3. A middle delay stage, as it is called, is not the final delay stage of the delay circuit110. InFIG. 2, the data samplers130-132may be implemented by D-type flip-flops (DFF). The data samplers130-132may sample received serial data according to the delayed clock signals dCK(m−3), dCK(m−2) and dCK(m−1), respectively.FIG. 2illustrates an embodiment that the serial data is sampled by using delayed clock signals not including the final stage delayed clock signal. From a prior delay stage to a later delay stage, the jitter of the delayed clock signals increases gradually. That is, as seen from the later delay stage to the prior delay stage, the jitter of the delayed clock signals decreases gradually. Such as that, the jitter of the sampled serial data generated by the data samplers130-132decreases gradually as a result of using the delayed clock signals which have gradually smaller jitter to do sampling. In another embodiment, the data sampler130may firstly sample the serial data SDATA according to the final stage delayed clock signal dCK0and subsequently sample the serial data according to middle stage delayed clock signals (such as the example inFIG. 1).

Please refer toFIG. 3, which illustrates a waveform diagram of the delayed clock signals and the serial data according to an embodiment of present disclosure. A relationship of timing parameters between the data sampler130and the data sampler131ofFIG. 1can be shown as formula (1) shown as below:
T−(td_ck+td_ck2q)−Tjitter>Tset(1)

Wherein, T is a period of the delayed clock signal dCK1, td_ck is a delay between the delayed clock signal dCK1and the delayed clock signal dCK0, td_ck2qis a gate delay of the data sampler130, Tjitteris a timing range of accumulated jitter, and Tsetis a setup time of the data sampler131. Another two middle stage delayed clock signals such as dCK(m−2) and dCK(m−3) shown inFIG. 2may be presented in the same waveforms as the waveforms of the delayed clock signals dCK1and dCK0inFIG. 3, and the relationship of timing parameters is similar.

Please refer toFIG. 4, which illustrates a schematic diagram of a data serialization circuit according to another embodiment of present disclosure. The data serialization circuit400includes a delay circuit410, a data serializer420, data samplers (implemented as D flip-flops, DFF)431-433, an output decision circuit440and a phase generation circuit450. The delay circuit410includes a plurality of delay stages411-41N, receives an input clock signal CK0and delays the input clock signal CK0to generate a plurality of delayed clock signals, including a middle stage delayed clock signal dCKn and a final stage delayed clock signal dCK0. The delayed clock signals dCK0is transported to the data serilaizer420, and the data serilaizer420converts received parallel data PDATA to serial data SDATA according to the delayed clock signals dCK0. The delayed clock signal dCKn is generated by one of middle stages of the delay stage411-41N, and may be transported to the phase generation circuit450. The phase generation circuit450may generate sampling clock signals SCK1-SCK3according to the delayed clock signal dCKn. The sampling clock signals SCK1-SCK3generated by the phase generation circuit450have the same period but different phases, the sampling clock signal SCK2lags behind the sampling clock signal SCK1, and the sampling clock signal SCK3lags behind the sampling clock signal SCK2.

It should be noted here, in some embodiment, the phase generation circuit450is not necessary. The sampling clock signals SCK1-SCK3may be obtained by selecting three of the middle stage delayed clock signals generated by the delay circuit410. The sampling clock signal SCK2lags behind the sampling clock signal SCK1, and the sampling clock signal SCK3lags behind the sampling clock signal SCK2. A delay between the sampling clock signals SCK1and SCK2, and a delay between the sampling clock signals SCK2and SCK3can be determined according to a data transmission rate of the serial data SDATA. A relationship between the delay between two sampling clock signals used by two neighboring data samplers and the data transmission rate can be referred to formula (1). In some embodiments, the sampling clock signals SCK1-SCK3may be selected from three consecutively neighboring middle delay stages of the delay circuit410.

The data samplers431-433are respectively formed by three D-type flip-flops (DFF). The data samplers431-433receive the serial data SDATA commonly, sample the serial data SDATA according to the sampling clock signals SCK1-SCK3respectively, and generate sampled serial data DA, DB and DC, respectively. The output decision circuit440receives the sampled serial data DA, DB and DC and selects one of the plurality of sampled serial data DA, DB and DC to be an output serial data OSDATA according to the sampled serial data DA, DB and DC.

In one embodiment, the data samplers431-433do not directly receive the serial data SDATA outputted from the data serializer420but receive a sampled serial data, as referred toFIG. 7.FIG. 7illustrates a schematic diagram of a scheme for generating a serial data to be sampled by the data samplers according to an embodiment of present disclosure. InFIG. 7, the serial data SDATA that the data serializer420generates is not directly sent to the data samplers431-433. The data serializer420sends the serial data SDATA to an initial stage data sampler710. The initial stage data sampler710samples the serial data SDATA initially to generate an input serial data SDATA1according to the delayed clock signal dCK0(which may be the final stage delayed clock signal generated by the final delay stage of the delay circuit410). The input serial data SDATA1is fed to the data samplers431-433. A relationship between timing parameters of the initial stage data sampler710and the plurality of data samplers431-433can be referred to formula (1). Besides, the initial stage data sampler710may be a D-type flip-flop.

In detail operation of the output decision circuit440, the output decision circuit440may select one of the plurality of sampled serial data DA, DB and DC to be as the output serial data OSDATA according to logic states of the plurality of sampled serial data DA, DB and DC. Please refer toFIG. 5, which illustrates a schematic diagram of the output decision circuit according to an embodiment of present disclosure. InFIG. 5, the output decision circuit440includes a transition detection circuit510, a voting circuit520, a clock selection circuit530and a selector540. The transition detection circuit510is coupled to the data samplers431-433, receives the sampled serial data DA, DB and DC and determines which one of the sampling clock signals SCK1-SCK3hits transition regions of the serial data SDATA by monitoring the plurality of sampled serial data DA, DB and DC to generate detection information DI. By referring toFIG. 6, which illustrates a waveform diagram of the transition detection circuit according to an embodiment of present disclosure. The serial data SDATA is respectively sampled at transition edges (rising edges and/or falling edges) of the sampling clock signals SCK1-SCK3, and three (or more) sampled serial data DA, DB and DC can be obtained. Take the sampling clock signal SCK1for example. If the sampling clock signal SCK1hit a logic high region of the serial data SDATA, the sampled serial data DA with logic “1” can be obtained, and if the sampling clock signal SCK1hit a logic low region of the serial data SDATA, the sampled serial data DA with logic “0” can be obtained.

It can be seen, when logic levels of the first, second, and third sampled serial data DA, DB and DC are the same, the detection information DI indicates a first event; when the logic level of the first sampled serial data DA is different from the logic levels of the second sampled serial data DB and the third sampled serial data DC, the detection information DI indicates a second event; and, when the logic level of the third sampled serial data DC is different from the logic levels of the first sampled serial data DA and the second sampled serial data DB, the detection information DI indicates a third event. Wherein, the first event indicates the transition region of the serial data SDATA is not hit by any of the sampling clock signals SCK1-SCK3, the second event indicates to the transition region is hit by the first sampling clock signal SCK1, and the third event indicates the transition region is hit by the third sampling clock signal SCK3.

That is, the transition detection circuit510may generate the detection information DI according to the sampled serial data DA, DB and DC by reference to a Table 1 shown as below. In Table 1, “No transition” is the first event, “SCK1hits data transition” is the second event, and “SCK3hits data transition” is the third event.

Please be noted here, in the Table 1, some unreasonable sampled serial data set with (DA, DB, DC)=(1, 0, 1) and (0, 1, 0) may be found. It means that operation of the transition detection circuit510at that time is abnormal. Such as that, the detection information DI is set to be “Don't care” by the transition detection circuit510corresponding to the abnormal status.

The voting circuit520is coupled to the transition detection circuit510, and receives a plurality of the detection information DI during a predetermined time period for a majority voting operation. The voting circuit520is used to determine a majority of the plurality of the detection information to generate a voting result VR.

In detail, during the time period of the majority voting operation, the voting circuit520may accumulate a first value in response to the detection information indicating the first event (“No transition”), accumulate a second value in response to the detection information indicating the second event (“SCK1hits data transition”), and accumulate a third value in response to the detection information indicating the third event (“SCK3hits data transition”), according to the plurality of detection information DI. After the majority voting operation is completed, the first value indicates the number of times that the first event occurs, the second value indicates the number of times that the second event occurs, and the third value indicating the number of times that the third event occurs. The voting circuit520may determine, among the three events, an event that occurs the maximum number of times according to the first to the third values, after the majority voting operation. The voting result VR indicates the determined event that occurs the maximum number of times during the majority voting operation. In other words, the voting circuit520may generate the voting result VR based on one of the first to third values which is corresponding to the event that occurs the maximum number of times.

The clock selection circuit530is coupled to the voting circuit520and the selector540. The clock selection circuit530receives the voting result VR, generates a selecting signal SS according to the voting result VR, and outputs the selecting signal SS to control the selector540to selectively outputs one of the sampled serial data DA, DB and DC to be as the output serial data OSDATA. The selecting signal SS may have three different values respectively corresponding to the voting result VR indicating the first event, the second event and the third event. In detail, if the voting result VR indicates the first event (“No transition”), the selecting signal SS may control the selector540to output the sampled serial data DB that is sampled by using the sampling clock signal SCK2to be as the output serial data OSDATA; if the voting result VR indicates the second event (“SCK1hits data transition”), the selecting signal SS may control the selector540to output the sampled serial data DC that is sampled by using the sampling clock signal SCK3to be as the output serial data OSDATA; and, if the voting result VR indicates the third event (“SCK3hits data transition”), the selecting signal SS may control the selector540to output the sampled serial data DA that is sampled by using the sampling clock signal SCK1to be as the output serial data OSDATA.

The transition detection circuit510, the clock selection circuit530, and the selector540may be implemented by a plurality of logic gates. A design of the logic gates can be implemented according to a truth table built based on the Table 1. The voting circuit520may include counters, and the counters respectively correspond to the events, and each of the counters is used to accumulate the value according to the corresponding detection information DI. The voting circuit520may further include a comparator to decide the maximum one of the values for generating the voting result VR.

To conclusion, the present disclosure provides a plurality of data samplers for re-sampling the serial data to generate the output serial data. The serial data is generated according to a delayed clock signal, and the data samplers re-sample the serial data according to another delayed clock signal(s) prior to the delayed clock signal. By selecting proper delayed clock signals, jitter of the output serial data can reduce, and quality of the output serial data can be improved.