Via construction for structural support

An integrated circuit having electrically conductive vias with a diameter of between about one micron and about fifty microns. Prior art vias have a diameter of between no less than 0.3 microns to no more than 0.8 microns. In this manner, stresses such as those that press down upon the top surface of the integrated circuit can be absorbed by the large vias and transferred past fragile layers, such as low k layers, so that the fragile layers are not damaged by the stresses.

FIELD

This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to designing integrated circuits so as to provide stress protection to layers and structures within the integrated circuit, such as low k material layers.

BACKGROUND

As integrated circuits have become increasingly smaller, electrically conductive structures within the integrated circuits are placed increasingly closer together. This situation tends to enhance the inherent problem of parasitic capacitance between adjacent electrically conductive structures. Thus, new electrically insulating materials have been devised for use between electrically conductive structures, to reduce such capacitance problems. The new electrically insulating materials typically have lower dielectric constants, and thus are generally referred to as low k materials. While low k materials help to resolve the capacitance problems described above, they unfortunately tend to introduce new challenges.

Low k materials are typically filled with small voids that help reduce the material's effective dielectric constant. Thus, there is less of the material itself within a given volume, which tends to reduce the structural strength of the material. The resulting porous and brittle nature of such low k materials presents new challenges in both the fabrication and packaging processes. Unless special precautions are taken, the robustness and reliability of an integrated circuit that is fabricated with low k materials may be reduced from that of an integrated circuit that is fabricated with traditional materials, because low k materials differ from traditional materials in properties such as thermal coefficient of expansion, moisture absorption, adhesion to adjacent layers, mechanical strength, and thermal conductivity.

Concerning the problem of thermal coefficient of expansion, when adjacent layers having different thermal coefficients of expansion are heated and cooled, such as occurs during the normal operation of an integrated circuit, the layers tend to expand and contract at different rates and to different degrees. These forces induce strains in the adjacent and proximal layers. Low k materials tend to have thermal coefficients of expansion that are sufficiently different from those of the other materials used to fabricate integrated circuits, that such strains create problems, which may be both physical and electrical, in the integrated circuit.

As to the problem of moisture absorption, the porosity of low k materials makes them susceptible to absorbing the moisture that typically tends to diffuse into the packaged integrated circuit. As the low k material absorbs such moisture, the properties of the low k material changes. For example, the dielectric constant of the material changes, because the voids tend to fill with water or water vapor. The moisture in the voids may rapidly expand during subsequent heating operations such as baking or solder ball reflow, causing the layers of the integrated circuit to burst apart, resulting in dramatic device failure. The moisture absorbed by the low k material also tends to cause other problems, some of which are described in more detail below.

Integrated circuits containing low k materials are inherently more prone to delamination, either between the various layers of the integrated circuit itself, or between the integrated circuit and packaging materials, such as underfill and mold compound, or other materials which are in intimate contact with the integrated circuit. There are several probable causes for such delamination, including a reduction in the adhesion of a low k layer due to absorption of moisture, as described above. In addition, because the low k material tends to be very porous by nature, there is physically less material available to form adhesive bonds with adjacent layers. Further, the strains induced by differing thermal coefficients of expansion also tend to shear the low k layer from adjacent layers, which again tends to enhance the occurrence of delamination.

As to mechanical strength, low k materials are typically more brittle and have a lower breaking point than other materials. One reason for this is, again, the porosity of the low k material, where a significant percentage of its physical volume is filled with voids. Thus, integrated circuits containing low k materials are inherently more prone to breaking or cracking during processes where physical contact is made with the integrated circuit surface, such as wire bonding and electrical probing, or processes that cause bending stresses such as mold curing, underfill curing, solder ball reflow, or temperature cycling.

Finally, because of their porosity and other properties, low k materials tend to be very poor thermal conductors, typically much less than half a watt per meter-Kelvin (W/mK). This contrasts significantly with the thermal conductivity of traditional integrated circuit and packaging materials such as silicon (60-90 W/mK), copper 380-390 W/mK), mold compound (0.7-2 W/mK), or die attach material (2-4 W/mK). Thus, the thermal energy created during the normal operation of the integrated circuit tends to not be dissipated well by low k materials. Therefore, thermal energy tends to build up within the integrated circuit, and is expressed as localized areas of increased temperature, or hot spots.

There is a need, therefore, for new structures, processes, and materials for use in integrated circuit fabrication, which help to alleviate one or more of the challenges that are enhanced by the use of low k materials.

SUMMARY

Some of the above and other needs are met by an integrated circuit having electrically conductive vias with a diameter of between about one micron and about fifty microns. Prior art vias have a diameter of between no less than 0.3 microns to no more than 0.8 microns. In this manner, stresses such as those that press down upon the top surface of the integrated circuit can be absorbed by the large vias and transferred past fragile layers, such as low k layers, so that the fragile layers are not damaged by the stresses.

In various preferred embodiments, the electrically conductive vias are disposed in one or more of a seal ring of the integrated circuit, active portions of the integrated circuit, and via arrays in corner portions of the integrated circuit. The electrically conductive vias may alternately be either electrically active or electrically inactive. In one embodiment, sets of the electrically conductive vias are disposed in vertical alignment one to another from a top surface of the integrated circuit to a substrate layer of the integrated circuit, thereby transferring loads from the top surface to the substrate without substantially loading any intervening layers.

In an alternate embodiment, the sets of the electrically conductive vias are disposed in an offset alignment one to another from a top surface of the integrated circuit to a substrate layer of the integrated circuit, thereby distributing loads from the top surface either between the substrate and selected intervening layers or to a selected intervening layer. Preferably the electrically conductive vias are formed of metal, and most preferably are formed of copper. In one embodiment all of the vias in the integrated circuit are the large electrically conductive vias. The larger vias are most beneficial when the integrated circuit is a flip chip and is at least about ten millimeters square in size.

Also described herein is a packaged integrated circuit, where the improvement is the integrated circuit having the large vias as described above. Additionally described is an integrated circuit having a die seal ring formed of continuous electrically conductive via rings that extend completely around a peripheral portion of the integrated circuit. Preferably the continuous electrically conductive via rings are disposed in vertical alignment one to another from a top surface of the integrated circuit to a substrate layer of the integrated circuit, thereby transferring loads from the top surface to the substrate without substantially loading any intervening layers. Alternately, the continuous electrically conductive via rings are disposed in an offset alignment one to another from a top surface of the integrated circuit to a substrate layer of the integrated circuit, thereby distributing loads from the top surface between the substrate and selected intervening layers. The continuous electrically conductive via rings may also be interdisposed with separate electrically conductive vias on different layers of the integrated circuit.

A packaged integrated circuit is also described, where the packaged integrated circuit includes a flip chip monolithic integrated circuit that is at least about ten millimeters square in size. Electrically conductive, electrically active vias are disposed in the monolithic circuit, where the electrically conductive vias have a diameter of between about one micron and about fifty microns. The electrically conductive vias are disposed in a seal ring and in via arrays in corner portions of the integrated circuit. Sets of the electrically conductive vias are disposed in vertical alignment one to another from a top surface of the integrated circuit to a substrate layer of the integrated circuit, thereby transferring loads from the top surface to the substrate without substantially loading any intervening layers.

DETAILED DESCRIPTION

With reference now toFIG. 1, there is depicted a top plan view of an integrated circuit10depicting electrically conductive vias12according to the present invention. The electrically conductive vias12of the present invention are larger than prior art vias, which typically range in diameter from no less than 0.3 microns to no more than 0.8 microns. By contrast, the electrically conductive vias12of the present invention have a diameter of no less than about one micron and no more than about fifty microns, and thus are substantially larger than prior art vias. Thus, the electrically conductive vias12of the present invention are able to bear and distribute stresses, such as those produced externally to the integrated circuit10and which press down upon the upper surface of the integrated circuit10.

The electrically conductive vias12are preferably formed of metal, and are most preferably formed of copper. The electrically conductive vias12may be either electrically active, meaning that they are used to conductive signals, power, or ground through the integrated circuit10, or electrically inactive, meaning that they are not used to conductive signals, power, or ground through the integrated circuit10. The electrically conductive vias12may be disposed in an interior portion22of the integrated circuit10, and may be paired with traditional vias24. In such a configuration, the electrically conductive vias12may provide structural support alone, redundant electrically active operation in addition to the traditional vias24, or primary electrically active operation to the integrated circuit10.

The electrically conductive vias12may also be placed in specially designed arrays18, such as in the corner portions20of the integrated circuit10, where stresses tend to be the greatest on a packaged integrated circuit10. Such stresses are especially prevalent on relatively larger integrated circuits10, such as those that are at least about ten millimeters square in size. The electrically conductive vias12may also be placed in a die seal ring14near the peripheral edges16of the integrated circuit10. In this manner, the via density in the die seal ring14is increased, due to the larger size of the electrically conductive vias12, which tends to improve the transfer of stress from the surface of the integrated circuit10to layers within the integrated circuit10that are more able to bear the stress, and away from layers that are less able to bear the stress, such as low k layers.

FIG. 2depicts an integrated circuit10where the electrically conductive via12in the die seal ring14has the form of a continuous ring, rather than a plurality of separate vias. It is appreciated that some of the electrically conductive vias12may be in the form of a ring via12in the die seal ring14, and others of the electrically conductive vias12may be in the separate via form as depicted in the interior22of the integrated circuit10and in the arrays18in the corners20of the integrated circuit10. It is further appreciated that some of the electrically conductive vias12may be electrically active and others of the electrically conductive vias12may be electrically inactive.

With reference now toFIG. 3, there is depicted a cross sectional view of a portion of a packaged integrated circuit34, including a package substrate28, electrical connection26between the package substrate28and an electrical contact30on the surface32of the integrated circuit10, and a stack of electrically conductive vias12formed between electrically conductive traces36. In the embodiment depicted inFIG. 3, the via stack is formed in a vertical alignment from the contact30to the substrate40of the integrated circuit10, and is formed through a variety of different layers38, which are not separately distinguished inFIG. 3. Acasing42is disposed against the backside of the integrated circuit10.

In the embodiment depicted inFIG. 3, the vertical alignment of the via stack tends to transfer loads from the upper surface32of the integrated circuit10directly to the substrate40on which the electrically conductive vias12are based. Thus, the via stack acts like a structural pillar support, and any intervening layers, such as low k layers, are not unduly loaded from stresses placed on the upper surface32of the integrated circuit10.

FIG. 4depicts an alternate embodiment where the via stack is disposed in an offset alignment, and the stresses are transferred to one or more intervening layers38, either in place of or in addition to transferring the load to either the substrate40or an overlying oxide layer44. It is appreciated that the load could be transferred to an oxide or other base layer44in the embodiment ofFIG. 3as well, instead of directly to the substrate40, and the load could be at least partially transferred directly to the substrate40in the embodiment of FIG.4. The offset alignment of the via stack as depicted inFIG. 4allows the load to be either evenly distributed throughout the layers38, and thus ensuring that no one layer has too much of a load, or distributed to a selected subset of the layers38and not to the other layers, and thereby ensuring that the other layers, such as weaker low k layers, are not burdened with too much of a load.

It is further appreciated that a combination of the continuous via rings as depicted in the FIG.2and the separate vias as depicted inFIG. 1can be used on the different layers down through the integrated circuit10. Additionally, either a greater number of smaller vias12or a smaller number of larger vias12may be used to provide the desired support. In addition, the via stacks as depicted inFIGS. 3 and 4need not be connected to the package substrate28by electrical connections26, such as the solder bump depicted. In such an embodiment, the volume that is taken with the electrical connection26will instead be filled with an underfill or other potting material, which also produces stress against the top surface32of the integrated circuit10.