A semiconductor device includes a semiconductor substrate of a first conductivity type, a RESURF layer of a second conductivity type, a buried layer of the second conductivity type formed in the bottom portion of a high-side circuit, and a MOSFET having the RESURF layer serving as a drift layer, in which the MOSFET includes a first semiconductor layer of the second conductivity type serving as a drain layer, an end portion of the first semiconductor layer is located on a low-side circuit side more than an end portion of the buried layer is, and a curvature center of a curved portion of the first semiconductor layer is located closer to a high-side circuit than a curved portion of the buried layer is, and the curvature of the curved portion of the first semiconductor layer is smaller than that of the curved portion of the buried layer.

FIELD OF THE INVENTION

The present disclosure relates to a semiconductor device including a Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) and a method of manufacturing the semiconductor device.

DESCRIPTION OF THE BACKGROUND ART

A power control IC (Integrated Circuit), which is mainly used to drive the gate of a power semiconductor device, outputs a drive signal according to the input signal from the input terminal, from an output terminal thereof, which drives the gate of a power switching element by turning on and off. A power control IC typically has a low-side circuit that operates with the ground (GND) potential as a reference potential, a high-side circuit that operates with a potential different from the GND potential as a reference potential, and a level shift circuit that performs signal transmission between the low-side circuit and the high-side circuit.

In particular, the power control IC requires a power source to drive both the low-side and high-side circuits. A technique of using a MOSFET formed in a RESURF layer as a high-voltage element in a bootstrap circuit with the bootstrap circuit for generating the power source for the high-side circuit within the IC is known.

In a semiconductor device with such a RESURF layer, the impurity concentration of the RESURF layer is limited because the RESURF layer is required to be fully depleted to maintain a high breakdown voltage during the breakdown voltage is maintained, which is a state from when an electric field is generated by applying a high voltage between the source and the drain when the MOSFET is turned off to when the avalanche starts. On the other hand, limiting the impurity concentration of the RESURF layer prevents reduction in the on-resistance of the MOSFET formed in the RESURF layer. For example, increasing the length of the RESURF layer forming the MOSFET in the direction along the substrate plane improves the breakdown voltage property of the MOSFET, but causes an increase in the on-resistance of the MOSFET. In other words, in the MOSFET formed in the RESURF layer, improvement in breakdown voltage property and reduction in on-resistance are in a trade-off relationship.

Therefore, techniques for improving the trade-off between the improvement in breakdown voltage property and the reduction in on-resistance are being studied. For example, in Japanese Patent Application Laid-Open No. 2021-103731, the trade-off between the improvement in the breakdown voltage property and the reduction in on-resistance in the MOSFET formed in the RESURF layer is improved with the structure in which an N-type buried diffusion layer and an N-type diffusion layer are provided, and the position of the end portion on the outer side (low side circuit side) of the N-type diffusion layer is laid closer to the low-side circuit than the end portion of the position of the outer side of the N-type buried diffusion layer is.

According to the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2021-103731, by extending the N-type diffusion layer toward the low-side circuit side more than the N-type buried diffusion layer is extended, the trade-off between the improvement in breakdown voltage property and the reduction in on-resistance is improved. On the other hand, in the N-type diffusion layer having a straight line region and a corner region in plan view, there has been a problem in that, when the extension of the N-type diffusion layer in the straight line region is similarly applied to the corner region, the electric field concentrates in the corner region and the breakdown voltage property reduces.

SUMMARY

An object of the present disclosure is to provide a semiconductor device with a reduction in breakdown voltage property.

According to a first aspect of the present disclosure, a semiconductor device includes a semiconductor substrate of a first conductivity type, a RESURF layer of a second conductivity type formed in a surface portion of the semiconductor substrate and separating a high-side circuit and a low-side circuit, a buried layer provided between the semiconductor substrate and the RESURF layer, formed at a bottom of the high-side circuit and having an impurity concentration higher than that of the RESURF layer, and a MOSFET having the RESURF layer serving as a drift layer. The MOSFET includes a first semiconductor layer of the second conductivity type formed in a surface portion of the RESURF layer having an impurity concentration higher than that of the RESURF layer, and serving as a drift layer, a second semiconductor layer of the first conductivity type provided on a side away from the high-side circuit further than the first semiconductor layer is, and a third semiconductor layer of the second conductivity type formed in a surface portion of the second semiconductor layer, and serving as a source layer. An end portion of the first semiconductor layer is located at a position further away from the high-side circuit than an end portion of the buried layer is. The end portion of the buried layer has a first straight portion, a second straight portion, and a curved portion whose ends are connected to the first straight portion and the second straight portion, respectively, in plan view. The end portion of the first semiconductor layer has a third straight portion, a fourth straight portion, and a curved portion whose ends are connected to the third straight portion and the fourth straight portion, respectively, in plan view. A position of a curvature center of the curved portion of the first semiconductor layer is closer to the high-side circuit than the curved portion of the buried layer is. A curvature of the curved portion of the first semiconductor layer is smaller than the curved portion of the buried layer.

According to a second aspect of the present disclosure, a semiconductor device includes a semiconductor substrate of a first conductivity type, a RESURF layer of a second conductivity type formed in a surface portion of the semiconductor substrate and separating a high-side circuit and a low-side circuit, a buried layer provided between the semiconductor substrate and the RESURF layer, formed at a bottom of the high-side circuit and having an impurity concentration higher than that of the RESURF layer, and a MOSFET having the RESURF layer serving as a drift layer. The MOSFET includes a first semiconductor layer of the second conductivity type formed in a surface portion of the RESURF layer having an impurity concentration higher than that of the RESURF layer, and serving as a drift layer, a second semiconductor layer of the first conductivity type provided on a side away from the high-side circuit further than the first semiconductor layer is, and a third semiconductor layer of the second conductivity type formed in a surface portion of the second semiconductor layer, and serving as a source layer. An end portion of the first semiconductor layer is located at a position further away from the high-side circuit than an end portion of the buried layer is. The end portion of the first semiconductor layer has a first straight portion, a second straight portion, and a portion whose ends are connected to the first straight portion and the second straight portion, respectively, in plan view. The portion has a third straight portion connected to the first straight portion at an obtuse angle and a fourth straight portion connected to the second straight portion at an obtuse angle, respectively, in plan view. The end portion of the buried layer has a fifth straight portion, a sixth straight portion, and a curved portion whose ends are connected to the fifth straight portion and the sixth straight portion, respectively, in plan view.

According to a third aspect of the present disclosure, a semiconductor device includes a semiconductor substrate of a first conductivity type, a RESURF layer of a second conductivity type formed in a surface portion of the semiconductor substrate and separating a high-side circuit and a low-side circuit, a buried layer provided between the semiconductor substrate and the RESURF layer, formed at a bottom of the high-side circuit and having an impurity concentration higher than that of the RESURF layer, and a MOSFET having the RESURF layer serving as a drift layer. The MOSFET includes a first semiconductor layer of the second conductivity type formed in a surface portion of the RESURF layer having an impurity concentration higher than that of the RESURF layer, and serving as a drift layer, a second semiconductor layer of the first conductivity type provided on a side away from the high-side circuit further than the first semiconductor layer is, and a third semiconductor layer of the second conductivity type formed in a surface portion of the second semiconductor layer, and serving as a source layer. An end portion of the first semiconductor layer is located at a position further away from the high-side circuit than an end portion of the buried layer is. The end portion of the buried layer has a first straight portion, a second straight portion, and a curved portion whose ends are connected to the first straight portion and the second straight portion, respectively, in plan view. The end portion of the first semiconductor layer has a third straight portion, a fourth straight portion, and a curved portion whose ends are connected to the third straight portion and the fourth straight portion, respectively, in plan view. An impurity concentration of a portion of the first semiconductor layer located on an inner side than the second curved portion including the second curved portion is lower than an impurity concentration of the first semiconductor layer.

According to the present disclosure, a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device that includes a semiconductor substrate of a first conductivity type, a RESURF layer of a second conductivity type formed in a surface portion of the semiconductor substrate and separating a high-side circuit and a low-side circuit, a buried layer provided between the semiconductor substrate and the RESURF layer, formed at a bottom of the high-side circuit and having an impurity concentration higher than that of the RESURF layer, and a MOSFET having the RESURF layer serving as a drift layer. The MOSFET includes a first semiconductor layer of the second conductivity type formed in a surface portion of the RESURF layer having an impurity concentration higher than that of the RESURF layer, and serving as a drift layer, a second semiconductor layer of the first conductivity type provided on a side away from the high-side circuit further than the first semiconductor layer is, and a third semiconductor layer of the second conductivity type formed in a surface portion of the second semiconductor layer, and serving as a source layer. An end portion of the first semiconductor layer is located at a position further away from the high-side circuit than an end portion of the buried layer is. The end portion of the buried layer has a first straight portion, a second straight portion, and a curved portion whose ends are connected to the first straight portion and the second straight portion, respectively, in plan view. The end portion of the first semiconductor layer has a third straight portion, a fourth straight portion, and a curved portion whose ends are connected to the third straight portion and the fourth straight portion, respectively, in plan view. In the method of manufacturing the semiconductor device, a step of forming the first semiconductor layer includes a step of forming a mask material having a first impurity implantation opening, a plurality of second impurity implantation openings, and a blocking portion defining the first impurity implantation opening and the plurality of second impurity implantation openings on a base material, a step of introducing impurities into the base material from the first impurity implantation opening and the plurality of second impurity implantation openings by irradiating with the impurities, a step of removing the mask material from the base material, and a step of subjecting the base material into which the impurities have been introduced to heat treatment. The plurality of second impurity implantation openings are provided in a region corresponding to a portion of the first semiconductor layer located on an inner side than the second curved portion including the second curved portion in the mask material in plan view.

According to the present disclosure, a reduction in breakdown voltage property is prevented.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

InFIGS.1,6,9and14, the direction to the left is referred to as “inner side” for convenience, and the direction to the right is referred to as “outer side” for convenience. Also, inFIGS.3,4,7,8,10to13, and15to19, the left and downward directions are referred to as “inner side” and the right and upward directions are referred to as “outer side”.

As will be understood from the description below, the inner side in each drawing corresponds to a side closer to a high-side circuit, and the outer side corresponds to a side away from the high-side circuit.

First Embodiment

A semiconductor device1001according to a first embodiment will be described with reference toFIGS.1to6.

FIG.1is a cross-sectional view illustrating a structure of a semiconductor device1001according to a first embodiment, and corresponds to a cross-section taken along line A-A inFIG.2described later. The semiconductor device1001includes a MOSFET formed in a RESURF layer2. Hereinafter, the MOSFET refers to a lateral N-channel MOSFET formed in the RESURF layer2. In the following, P-type represents the first conductivity type, N-type represents the second conductivity type, and the semiconductor layer of the first conductivity type is referred to as “P-type semiconductor layer”, and the semiconductor layer of the second conductivity type is referred to as “N-type semiconductor layer”. However, the first conductivity type may be N-type, and the second conductivity type may be P-type.

The semiconductor device1001includes a semiconductor layer100. The semiconductor layer100includes a P-type semiconductor substrate1, a RESURF layer2, which is an N-type semiconductor layer formed in the surface portion of the semiconductor substrate, and a buried layer3, which is provided between the semiconductor substrate1and the RESURF layer2and formed at the bottom of a high-side circuit to be described later, having an impurity concentration higher than that of the RESURF layer2. The semiconductor layer100includes an N-type semiconductor layer4formed in the surface portion of the RESURF layer2and having an impurity concentration higher than that of the RESURF layer2, and an N-type semiconductor layer5formed in the surface portion of the N-type semiconductor layer4and having an impurity concentration higher than that of the N-type semiconductor layer4. The semiconductor layer100includes a P-type semiconductor layer6formed on the outer side than the N-type semiconductor layer4is, an N-type semiconductor layer7formed in the surface portion of the P-type semiconductor layer6, and a P-type semiconductor layer8provided in the surface portion of the P-type semiconductor layer6and having an impurity concentration higher than that of the P-type semiconductor layer6. The semiconductor layer100further includes a P-type semiconductor layer16being on the outer side than the RESURF layer2is and formed in the surface portion of the semiconductor substrate1so as to be in contact with the RESURF layer2, and a P-type semiconductor layer17formed in the surface portion of P-type semiconductor layer16and having an impurity concentration higher than that of P-type semiconductor layer16.

The impurity concentrations of N-type semiconductor layers increase in the order of the RESURF layer2, the N-type semiconductor layer4, the buried layer3, and the N-type semiconductor layer5, and the impurity concentration of the N-type semiconductor layer7is equal to that of the N-type semiconductor layer5.

The semiconductor device1001includes an insulating film12provided on the semiconductor layer100and a field oxide film9provided, in a position between the N-type semiconductor layer5and the N-type semiconductor layer7, in a position inner side than the N-type semiconductor layer5is, in a position between the P-type semiconductor layer8and the P-type semiconductor layer17, and in a position outer side than the P-type semiconductor layer17is, on the surface of the semiconductor layer100so as to be covered with the insulating film12. The semiconductor device1001includes a polysilicon10provided so as to cover the end portion on the inner side of the field oxide film9between the N-type semiconductor layer5and the N-type semiconductor layer7, and a polysilicon11provided so as to cover the end portion on the outer side of the field oxide film9between the N-type semiconductor layer5and the N-type semiconductor layer7. The semiconductor device1001further includes a drain electrode12connected to the N-type semiconductor layer5, a source electrode14connected to the N-type semiconductor layer7and the P-type semiconductor layer8, and an electrode for fixing reference potential15connected to the P-type semiconductor layer17, each of which is formed so as to be buried in the insulating film12. The polysilicon10is buried in the insulating film12and used as a mask material56at a moment of implantation at which the N-type semiconductor layer5is formed. The polysilicon11is buried in the insulating film12and used as the gate electrode of the MOSFET.

The semiconductor device1001constitutes a high-voltage integrated circuit, or an HVIC, and includes a high-side circuit and low-side circuit. Both of the high-side circuit and the low-side circuit are configured in N-type semiconductor layers and P-type semiconductor layers that are not illustrated inFIG.1in the semiconductor layer100. The high-side circuit, which includes a digital circuit and an analog circuit, generates a signal that drives a power semiconductor element to supply thereof to the high-side power semiconductor element. The low-side circuit, which includes a digital circuit and an analog circuit, generates a signal that drives a power semiconductor element to supply thereof to the low-side power semiconductor element. The power semiconductor element is, for example, a MOSFET or an (Insulated Gate Bipolar Transistor (IGBT), and is provided outside the semiconductor device1001.

The semiconductor substrate1and the semiconductor layer100include a semiconductor material such as silicon (Si) or silicon carbide (SiC). In particular, the semiconductor device1001using silicon carbide or the like, which has a wider bandgap than silicon, is superior in operation at high voltage and high temperature to conventional semiconductor device1001using silicon.

The RESURF layer2separates the high-side circuit and the low-side circuit. In addition to this, the RESURF layer2serves as a drift layer of the MOSFET.

The buried layer3illustrates the effect of suppressing the vertical parasitic operation of the element in the high-side circuit, and the effect of preventing the damage from being inflicted on the operation of the elements within the high-side circuit with the depletion layer of the RESURF layer2expanding into the high-side circuit when the breakdown voltage is maintained.

The N-type semiconductor layer4has a structure in which the position of the end portion on the outer side of the N-type semiconductor layer4is away from the high-side circuit than the position of the end portion on the outer side of the buried layer3is, and this illustrates the effect of reducing the on-resistance and the effect of preventing field inversion of the MOSFET. In addition, the N-type semiconductor layer4and the N-type semiconductor layer5serve as drain layers of the MOSFET, and the N-type semiconductor layer5serves to electrically connect the N-type semiconductor layer4and a drain electrode13. Although the buried layer3and the N-type semiconductor layer4are spaced apart in the first embodiment, they may be in contact with each other.

The P-type semiconductor layer6serves as a back gate layer of the MOSFET, the N-type semiconductor layer7serves as a source layer of the MOSFET, and the P-type semiconductor layer8serves to electrically connect the P-type semiconductor layer6and a source electrode14, a substitute for a back gate electrode.

The P-type semiconductor layer16, which is the outer end portion of the semiconductor device1001, serves to fix the potential of the semiconductor substrate1to a reference potential. The P-type semiconductor layer17serves to electrically connect the P-type semiconductor layer16and the electrode for fixing reference potential15.

FIG.2is a plan view illustrating a semiconductor device1001of the first embodiment.

InFIG.2, the outermost edge is represented by the outer edge of the semiconductor substrate1, that is, the outer edge of the semiconductor device1001. A semiconductor device1001includes a level shift circuit50that transmits signals between the high-side circuit and the low-side circuit.

The N-type semiconductor layer4illustrated inFIG.2is a portion that does not overlap the buried layer3in plan view, and the non-overlapping portion is formed in a ring with the level shift circuit50interposed therebetween. The RESURF layer2illustrated inFIG.2is a portion that does not overlap the buried layer3, the N-type semiconductor layer4, and the N-type semiconductor layer5in plan view, and the non-overlapping portion is also formed in a ring with the level shift circuit50interposed therebetween.

The outer edges of each layer of the RESURF layer2, the N-type semiconductor layer4, and the buried layer3forms a substantially rectangular shape with four corners. Each corner has a curved portion each of whose ends is connected to a straight portion. These two straight portions correspond to two adjacent sides of the substantially rectangular shape. In each layer of the RESURF layer2, the N-type semiconductor layer4, and the buried layer3, a corner area represents the area of the inner side of the curved portion including the curved portion, and a straight area represents the area of the inner side of the straight portion including the straight portion of each side. InFIG.2, a corner area51represents one of four corner areas, and two straight areas each represent two straight areas adjacent to the corner area51.

The high-side circuitry is arranged within the buried layer3inFIG.2. The low-side circuit is arranged aligned with the high-side circuit with the RESURF layer2and the level shift circuit50interposed therebetween, specifically, the low-side circuit is arranged above the RESURF layer2and the level shift circuit50(not illustrated).

The MOSFET according to the first embodiment, which is provided in the RESURF layer2(shaded portion inFIG.2) and surrounding the high-side circuit, is an element constituting the bootstrap circuit, and is used instead of the bootstrap diode. A bootstrap circuit is a circuit that generates an operating power source for a high-side circuit, and includes, in addition to a MOSFET, a capacitor connected to the MOSFET.

FIG.3is a plan view illustrating part of the corner area51and the straight areas52of the first embodiment.

FIG.3is an enlarged view of the buried layer3and the N-type semiconductor layer4in the corner area51illustrated inFIG.2.

Solid lines represent contour lines that are the respective end portions of the buried layer3and the N-type semiconductor layer4. The end portion of the N-type semiconductor layer4is defined by a straight portion41included in one straight area52, a straight portion42included in an other straight area52, and a curved portion40whose ends are connected to the straight portion41and the straight portion42, respectively. The straight portion41and the straight portion42are orthogonal to each other in their extension lines. The end portion of the buried layer3is also defined by a straight portion31included in one straight area52, a straight portion32included in an other straight area52, and a curved portion30whose ends are connected to the straight portion31and the straight portion32, respectively. The straight portion31and the straight portion32are orthogonal to each other in their extension lines. Therefore, the straight portion41and the straight portion31are parallel, and the straight portion42and the straight portion31are also parallel.

The curvature center O of the curved portion30of the buried layer3and the curvature center O′ of the curved portion40of the N-type semiconductor layer4are located at different positions, and the curvatures of the two are also different. The distance between the contour line of the buried layer3and the contour line of the N-type semiconductor layer4is not the same value in the corner area51and the straight area52.

Meanwhile, the dotted line represents the contour line of the outer edge of an N-type semiconductor layer4A as a comparative example. The end portion of the N-type semiconductor layer4A is defined by a straight portion41A included in one straight area52, a straight portion42A included in an other straight area52, and a curved portion40A whose ends are connected to the straight portion41A and the straight portion42A, respectively. The straight portion41A and the straight portion42A are orthogonal to each other in their extension lines. The curvature center of the curved portion40A of the N-type semiconductor layer4A and the curvature center O of the curved portion30of the buried layer3are located at the same positions, and the curvatures of the two are also different. The distance between the contour line of the buried layer3and the contour line of the N-type semiconductor layer4A is the same value in the corner area51and the straight area52.

The distance between a point on the contour line of the buried layer3and the contour line of the N-type semiconductor layer4is represented by the distance from the point to a point on the contour line of the N-type semiconductor layer4where a line orthogonal to the tangent line at the point intersects.

As illustrated inFIG.3, the curvature of the curved portion40of the N-type semiconductor layer4is smaller than the curvature of the curved portion30of the buried layer3, and the curvature center O′ of the curved portion40of the N-type semiconductor layer4is receded toward the inner side in comparison with the curvature center O of the curved portion30of the buried layer3.

Further, a distance L′ between an intersection point N′ between the curved portion40and the straight portion42of the N-type semiconductor layer4and an intersection point M′ between the straight line drawn in the horizontal direction from the intersection point N′ and the contour line of the embedded layer3, is made greater by the elongation value S illustrated inFIG.3, than a distance L between an intersection point N between the curved portion40A and the straight portion42A of the N-type semiconductor layer4and an intersection point M between the straight line drawn in the horizontal direction from the intersection point N. Specifically, as illustrated inFIG.4, a line segment AB is elongated by the elongation value S, in which an intersection point A represents an intersection point of between a straight line passing through the curvature center O and the curvature center O′ and the curved portion40A of the N-type semiconductor layer4A, and an intersection point B represents an intersection point of between a straight line passing through the curvature center O and the curvature center O′ and the curved portion40B of the N-type semiconductor layer4B. Here, the elongation value S refers to the horizontal distance between the intersection point N and the intersection point N′ between the corner area51and the straight area52of the N-type semiconductor layer4.

FIG.3particularly illustrates the case where, in the corner area51, at a point, which is a point on the contour line of the N-type semiconductor layer4at which the distance between the curvature center O and the point becomes shortest, the contour line of the N-type semiconductor layer4and the contour line of the N-type semiconductor layer4A are in contact with each other.

Although the corner area51has been described, the same configuration as inFIG.3is applicable to the shapes of the other three corner areas.

FIG.4is a plan view in which an N-type semiconductor layer4B is superimposed onFIG.3as another comparative example. A dashed line indicates the N-type semiconductor layer4B, and the distance L from the buried layer3is extended by the elongation value S. However, unlike the N-type semiconductor layer4A, the curvature center thereof remains at the same position as the curvature center of the curved portion40A of the N-type semiconductor layer4A, and the distance L is extended by the elongation value S, as illustrated inFIG.4.

Therefore, the corner area51of the N-type semiconductor layer4B is elongated more, by the elongation value S, than that of the N-type semiconductor layer4A as a whole, similarly to the straight areas52.

Effects of the semiconductor device1001according to a first embodiment will be described.

In the semiconductor device1001according to the first embodiment, when the breakdown voltage is maintained, while at least the portion of the RESURF layer2on the outer side the N-type semiconductor layer4is fully depleted so that a high breakdown voltage of the MOSFET is realized, the buried layer3prevents the damage from being inflicted on the operation of the elements within the high-side circuit with the depletion layer generated from a PN junction between the semiconductor substrate1and the RESURF layer2expanding into the high-side circuit. The buried layer3also serves to suppress the operation of vertical parasitic PNP transistors in the high-side circuit. Also, by providing the N-type semiconductor layer4having the impurity concentration higher than that of the RESURF layer2, which serves as a drift layer, in the surface portion of the RESURF layer2, the surface concentration is improved and the on-resistance of the MOSFET is reduced.

Furthermore, both the buried layer3and the N-type semiconductor layer4being formed within the RESURF layer2does not allow the full depletion of the buried layer3when the breakdown voltage is maintained; therefore, the concentration of electric field that occurs in the buried layer3is dispersed by the buried layer3and the N-type semiconductor layer4, improving the breakdown voltage property of the MOSFET.

These effects are exhibited also in the semiconductor device having the N-type semiconductor layer4A according to the comparative example. Here, assume that the N-type semiconductor layer4A is elongated to become the N-type semiconductor layer4B in order to further reduce the on-resistance of the MOSFET. Then, not only the straight areas52but also the corner area51of the N-type semiconductor layer4B are elongated more by the elongation value S than the N-type semiconductor layer4A as a whole. Accordingly, although the on-resistance is reduced more as compared with the case of the N-type semiconductor layer4A, the electric field tends to be concentrated in the corner area51of the N-type semiconductor layer4B, deteriorating the breakdown voltage property.

Meanwhile, also in the present embodiment, the N-type semiconductor layer4A is elongated to become the N-type semiconductor layer4, that is, the on-resistance of the MOSFET is reduced because the distance L of the N-type semiconductor layer4A is increased by the elongation value S in the straight area52.

In the first embodiment, the line segment AZ is smaller than the line segment AB when the intersection point of the straight line passing through the curvature center O and the curvature center O′ and the curved portion40of the N-type semiconductor layer4is the intersection point Z; therefore, a concentration of electric field in the corner area51of the N-type semiconductor layer4is suppressed and a reduction in breakdown voltage property is prevented as compared with the N-type semiconductor layer4B. Also, in the N-type semiconductor layer4as in the first embodiment, in comparison with the N-type semiconductor layer4A, the curvature of the N-type semiconductor layer4in the corner region51is small so that the on-resistance can be reduced and the concentration of electric field of the N-type semiconductor layer4in the corner area51can also be suppressed.

FIG.5is a graph illustrating the relationship between the change in the elongation value S of the N-type semiconductor layer and the breakdown voltage between the source and the drain in the MOSFET of a comparative example and the MOSFET according to the first embodiment.

InFIG.5, the solid line graph indicates a change in breakdown voltage when the elongation value S of the N-type semiconductor layer4B of the comparative example is changed. The dashed line graph indicates a change in the breakdown voltage when the elongation value S is changed in a state where the curvature center O′ of the curved portion40of the N-type semiconductor layer4of the first embodiment is displaced leftward and downward by10pin inFIG.4. The dotted line graph indicates a change in the breakdown voltage when the elongation value S is changed in a state where the curvature center O′ of the curved portion40of the N-type semiconductor layer4of the first embodiment is displaced leftward and downward by 20 μm inFIG.4. The one dot chain line graph indicates a change in the breakdown voltage when the elongation value S is changed in a state where the curvature center O′ of the curved portion40of the N-type semiconductor layer4of the first embodiment is displaced leftward and downward by 30 μm inFIG.4. The evaluation was taken place with the distance L in the N-type semiconductor layer4A serving as a reference being 21 μm.

As illustrated inFIG.5, the peak value of the breakdown voltage of the MOSFET of the first embodiment is higher than that of the MOSFET of the comparative example, illustrating improvement in the breakdown voltage property of the MOSFET of the first embodiment in comparison with the MOSFET of the comparative example.

Furthermore, the elongation value S at the peak value of the breakdown voltage is 19 μm for the MOSFET of the comparative example, whereas the same are 23 μm, 24 μm, and 25 μm for the three examples of the MOSFET of the first embodiment. Therefore, the elongation value of the N-type semiconductor layer4of the MOSFET of the first embodiment can be increased compared with the MOSFET of the comparative example from which a reduction in on-resistance can also be expected.

In other words, in the MOSFET of the first embodiment, the trade-off between the improvement in breakdown voltage property and the reduction in on-resistance is improved in comparison with the conventional MOSFET.

In the first embodiment, although the example has been illustrated that the back gate layer of the MOSFET is composed of the P-type semiconductor layer6, and the source electrode14substitutes for the back gate electrode, as illustrated inFIG.6, the back gate layer may be formed with a P-type semiconductor layer16, and the electrode for fixing reference potential15may substitute for the back gate electrode. At this time, an N-type semiconductor layer18is provided in the surface portion of the P-type semiconductor layer16, and an N-type semiconductor layer19connected to the source electrode14is provided in the surface portion of the N-type semiconductor layer18. The N-type semiconductor layer18and the N-type semiconductor layer19become source layers of the MOSFET. The impurity concentrations of the N-type semiconductor layer18and the N-type semiconductor layer19are the same as those of the N-type semiconductor layers4and5, respectively.

Second Embodiment

FIG.7is a plan view illustrating part of a corner area51and linear areas52of the second embodiment.

In the first embodiment, the configuration has been described, in which, the curvature of the curved portion40of the N-type semiconductor layer4is smaller than the curvature of the curved portion30of the buried layer3, and the curvature center O′ of the curved portion40of the N-type semiconductor layer4is receded toward the inner side in comparison with the curvature center O of the curved portion30of the buried layer3, meanwhile, the corner area51of the N-type semiconductor layer4C has a shape in which the curved portion40B of the N-type semiconductor layer4B is chamfered, which is a different respect from the first embodiment. The rest of the configuration is the same as in the first embodiment, and the same reference numerals are given to the same or corresponding parts as in the first embodiment.

FIG.7is an enlarged view of the buried layer3and the N-type semiconductor layer4in the corner area51illustrated inFIG.2.

The N-type semiconductor layer4C indicated by a solid line represents a contour line of a shape obtained by chamfering the curved portion40B of the N-type semiconductor layer4B at the intersection point A. Although, the surface formed by chamfering the curved portion40B of the N-type semiconductor layer4B is in contact with the contour line of the curved portion40A of the N-type semiconductor layer4A, the surface may not be in contact therewith.

FIG.8is a plan view illustrating an other example of part of the corner area51and the linear areas52of the second embodiment. As in an N-type semiconductor layer4D illustrated inFIG.8, the shape takes a form that is chamfered the curved portion40B of the N-type semiconductor layer4B with a portion of the contour line of the curved portion40A of the N-type semiconductor layer4A left such that a surface formed by chamfering the curved portion40B of the N-type semiconductor layer4B overlaps the contour line of the curved portion40A of the N-type semiconductor layer4A.

Although bothFIGS.7and8illustrate the shapes chamfered the curved portion40B of the N-type semiconductor layer4B, the curved portion40of the N-type semiconductor layer4may be chamfered to form the N-type semiconductor layer4C.

According to the second embodiment, in plan view, the N-type semiconductor layer has end portions that are a straight portion41C or41D, a straight portion42C or42D, and a portion each of both ends connect to the straight portion41C or41D and the straight portion42C or42D, in which the portion has a straight portion43C or43D connected to the straight portion41C or41D at an obtuse angle, and a straight portion44C or44D connected to the straight portion42C or42D.

InFIG.7, one straight line is formed with the straight portion43C and the straight portion44C. The straight portion41C and the straight portion42C are in a relationship where they are orthogonal to each other on their extension lines, the straight portion43C intersects the straight portion41C at an angle of 135 degrees, and the straight portion44C intersects the straight portion42C at an angle of 135 degrees.

InFIG.8, the portion further has a curved portion40D each of both ends is connected to the straight portion43D and the straight portion44D. The straight portion41D and the straight portion42D are in a relationship where they are orthogonal to each other on their extension lines, the straight portion43D intersects the straight portion41D at an angle of 135 degrees, and the straight portion44D intersects the straight portion42D at an angle of 135 degrees.

In a semiconductor device1002of the second embodiment, when the N-type semiconductor layer4A is elongated to become the N-type semiconductor layer4C, the distance L of the N-type semiconductor layer4A is increased by the elongation value S, so that the on-resistance is reduced. Further, the line segment AC is smaller than the line segment AB when the intersection point of the straight line passing through the curvature center O and the curvature center O′ and the contour line of the curved portion40C of the N-type semiconductor layer4C is the intersection point C; therefore, a concentration of electric field in the corner area51of the N-type semiconductor layer4is suppressed and a reduction in breakdown voltage property is prevented as compared with the N-type semiconductor layer4B.

Although the corner area51has been described in the N-type semiconductor layer illustrated inFIGS.7and8, the same configuration as inFIG.7or8is applicable to the shapes of the other three corner areas.

Also, the back gate layer and the source layer of the second embodiment may be configured like the P-type semiconductor layer16and the N-type semiconductor layers18and19inFIG.6.

Although the straight portion43C is directly connected to the straight portion41C inFIG.7, a curved portion may be interposed between the straight portions43C and41C. Therefore, “a certain straight portion is connected to another straight portion at an obtuse angle” encompasses the case where two straight portions, whose extension lines intersect at an obtuse angle, are connected to each other via a curved portion. For example, the same applies between the straight portion44C and the straight portion42C inFIG.7, between the straight portion43D and the straight portion41D and between the straight portion44D and the straight portion42D inFIG.8.

Third Embodiment

FIG.9is a cross-sectional view illustrating a structure of a semiconductor device1003according to a third embodiment, and corresponds to a cross-section taken along line A-A inFIG.2.FIGS.10,11, and12are plan views illustrating part of a corner area51and straight areas52of the third embodiment.

In the first embodiment, the configuration has been described, in which As illustrated inFIG.3, the curvature of the curved portion40of the N-type semiconductor layer4is smaller than the curvature of the curved portion30of the buried layer3, and the curvature center O′ of the curved portion40of the N-type semiconductor layer4is receded toward the inner side in comparison with the curvature center O of the curved portion30of the buried layer3, meanwhile, in the third embodiment, the curvature of the curved portion40of the N-type semiconductor layer4is smaller than the curvature of the curved portion30of the buried layer3, and the curvature center O′ of the curved portion of the N-type semiconductor layer4is the same position as the curvature center O of the curved portion30of the buried layer3, which is a different respect from the first embodiment, and the impurity concentration of a part of the N-type semiconductor layer4including the curved portion40is different from that of the first embodiment. The rest of the configuration is the same as in the first embodiment, and the same reference numerals are given to the same or corresponding parts as in the first embodiment.

As illustrated inFIG.9, an N-type semiconductor layer4E includes two regions E1and E2with different impurity concentrations from each other. The region E1is located at the end portion of the N-type semiconductor layer4E, and the region E2is located on the inner side than the region E1is. The impurity concentration of the region E1is lower than that of the region E2.

FIGS.10,11, and12are diagrams according to the third embodiment, in each of which an enlarged view of the buried layer3and the N-type semiconductor layer4E in the corner region51illustrated inFIG.2is superimposed with a mask material54having a first impurity implantation opening53, a plurality of second impurity implantation openings54, and a blocking portion55.

The one dot chain line represents a contour line that is the end portion of the N-type semiconductor layer4E. The end portion of the N-type semiconductor layer4E is defined by a straight portion41E included in one straight area52, a straight portion42E included in an other straight area52, and a curved portion40E whose ends are connected to the straight portion41E and the straight portion42E, respectively. The contour line of the N-type semiconductor layer4E substantially matches that of the N-type semiconductor layer4B. The region E1corresponds to a region including the curved portion40E and located on the inner side of the curved portion40E.

The solid lines represent the contour lines of the first impurity implantation opening53and the second impurity implantations openings54. The blocking portion55of the mask material56is formed by removing the first impurity implantation opening53and the second impurity implantation openings54indicated by the solid lines from the N-type semiconductor layer4E indicated by the one dot chain line.

The first impurity implantation opening53indicates the opening pattern of the mask material56for forming the region E2of the N-type semiconductor layer4E, and the shape of the first impurity implantation opening53substantially matches the shape of the N-type semiconductor layer4C.

The second impurity implantation openings54indicate the opening pattern of the mask material56for forming the region E1of the N-type semiconductor layer4E. The second impurity implantation openings54are arranged in a region having a shape substantially matching the region obtained by removing the N-type semiconductor layer4C from the N-type semiconductor layer4E.

The boundary between the regions E1and E2, which is respectively formed by the mask material56in each ofFIGS.10to12, is defined by a straight portion43E connected to the straight portion41E at an obtuse angle and a straight portion44E connected to the straight portion42E at an obtuse angle in plan view. The straight portion43E and the straight portion44E form one straight line.

InFIG.10, the plurality of second impurity implantation openings54having a trapezoidal shape with a pattern width W are arranged in the region E1along the tangential direction of the intersection point A at regular intervals of a pattern interval I.

InFIG.11, a plurality of square dot-shaped second impurity implantation openings54are arranged in the region E1. Although an example in which the shape of the second impurity implantation openings54is a square dot shape is illustrated, as long as the shape takes a dot shape, any shape such as a chain dot shape, a round dot shape, may be adoptable.

InFIG.12, the plurality of second impurity implantation openings54having a rectangular shape with a pattern width W are arranged in the region E1along the horizontal direction at regular intervals of a pattern interval I.

Next, a method of manufacturing the semiconductor device1003, in particular, a forming step of the N-type semiconductor layer4E will be described with reference toFIG.13. First, the mask material56provided with the first impurity implantation opening53, the plurality of second implantation openings54, and the blocking portion55defining those openings, illustrated in any ofFIGS.10to12, is formed on a base material57, in a region E1′ in the base material57corresponding to the region E1, and a region E2′ in the base material corresponding to the region E2in the corner area51. The first impurity implantation opening53and the plurality of second impurity implantation openings54open the surface of the base material57. Next, the base material57is irradiated with impurities. Impurities are introduced into the base material57through the first impurity implantation opening53and the plurality of second impurity implantation openings54, and the introduction of the impurities is blocked by the blocking portion55. After that, the base material57into which the impurities have been introduced is subjected to heat treatment. The heat treatment allows the impurities to be diffused in the direction in which the concentration becomes uniform, and the N-type semiconductor layer4E illustrated inFIG.9is formed. The mask material56having the opening pattern of the second impurity implantation openings54in the region E1′ partially blocks the impurities to diffuse; therefore, as illustrated inFIG.9, the region E1having an impurity concentration lower than that of the region E2is formed. Although the mask material56is removed after the impurities are introduced and before the heat treatment, the mask material56may be removed after the heat treatment.

In a semiconductor device1003of the second embodiment, when the N-type semiconductor layer4A is elongated to become the N-type semiconductor layer4E, the distance L of the N-type semiconductor layer4A is increased by the elongation value S, so that the on-resistance is reduced. Further, by arranging the second impurity implantation openings54in the region E1and making the impurity concentration lower than that in the region E2, the concentration of electric field in the corner area51of the N-type semiconductor layer4E is suppressed and a reduction in breakdown voltage property is prevented as compared with the N-type semiconductor layer4B.

Although the example in which the second impurity implantation openings54are arranged in the region E1is illustrated in the third embodiment, as illustrated inFIG.14the second impurity implantation openings54may be arranged along the curvature of the curved portion40A of the N-type semiconductor layer4A at equal intervals at the pattern interval I. Also in the N-type semiconductor layer4E formed using the mask material56ofFIG.14, the two regions E1and E2with different impurity concentrations are formed.

The difference among the N-type semiconductor layers4E formed using the mask material56inFIGS.10to12is the shape of the region E2.

The contour line of the N-type semiconductor layer4E substantially matches that of the N-type semiconductor layer4B in plan view, and the region E1corresponds to the region formed by removing the N-type semiconductor layer4D from the N-type semiconductor layer4B. The region E2corresponds to a region formed by removing the region E1from the N-type semiconductor layer4E. Therefore, the boundary between the region E1and the region E2is, in plan view, is defined by the straight portion43E connected to the straight portion41E at an obtuse angle, the straight portion44E connected to the straight portion42E at an obtuse angle, and a curved portion45E each of both ends is connected to the straight portion43E and the straight portion44E. The impurity concentration of the region E1is higher than that of the region E2.

Further, in the third embodiment, an example in which the shape of the second impurity implantation openings54is trapezoidal, dot-shaped, or rectangular has been illustrated, however, the shape, dimensions, and arrangement intervals of the second impurity implantation openings54are not limited thereto.

Although the corner area51has been described inFIGS.10,11,12, and14, the same configuration as any ofFIGS.10,11,12, and14is applicable to the shapes of the other three corner areas.

Also, the back gate layer and the source layer of the second embodiment may be configured like the P-type semiconductor layer16and the N-type semiconductor layers18and19inFIG.6.

Fourth Embodiment

FIG.15is a cross-sectional view illustrating a structure of a semiconductor device1004according to a fourth embodiment, and corresponds to the cross-section taken along line A-A inFIG.2.FIGS.16,17,18,19, and20are plan views illustrating part of a corner area51and straight areas52of the fourth embodiment.

In the third embodiment, the configuration in which the impurity concentration is higher in the region E2than in the region E1has been described. The fourth embodiment differs from the third embodiment in that the impurity concentration is higher in a region F2than in that in a region F1, which are described later, and a concentration gradient is given to the impurity concentration of the region F1. The rest of the configuration is the same as in the third embodiment, and the same reference numerals are given to the same or corresponding parts as in the third embodiment.

As illustrated inFIG.15, the N-type semiconductor layer4F includes the two regions F1and F2with different impurity concentrations from each other. The region F1is located at the end portion of the N-type semiconductor layer4F, and the region F2is located on the inner side than the region F1is. The impurity concentration of the region F1is lower than that of the region F2.

FIG.16is diagram according to the fourth embodiment, in which an enlarged view of the buried layer3and the N-type semiconductor layer4F in the corner region51illustrated inFIG.2is superimposed with a mask material54having a first impurity implantation opening53, a plurality of second impurity implantation openings54, and a blocking portion55.

The one dot chain line represents a contour line that of the N-type semiconductor layer4F. The end portion of the N-type semiconductor layer4F is defined by a straight portion41F included in one straight area52, a straight portion42F included in an other straight area52, and a curved portion40F whose ends are connected to the straight portion41F and the straight portion42F, respectively. The contour line of the N-type semiconductor layer4F substantially matches that of the N-type semiconductor layer4B. The region F1corresponds to a region including the curved portion40F and located on the inner side of the curved portion40F.

The solid lines represent the contour lines of the first impurity implantation opening53and the second impurity implantations openings54. The blocking portion55of the mask material56is formed by removing the first impurity implantation opening53and the second impurity implantation openings54indicated by the solid lines from the N-type semiconductor layer4F indicated by the one dot chain line.

The first impurity implantation opening53indicates the opening pattern of the mask material56for forming the region F2of the N-type semiconductor layer4F, and the shape of the first impurity implantation opening53substantially matches the shape of the N-type semiconductor layer4C.

The second impurity implantation openings54indicate the opening pattern of the mask material56for forming the region F1of the N-type semiconductor layer4F. The second impurity implantation openings54are arranged in a region having a shape substantially matching the region obtained by removing the N-type semiconductor layer4C from the N-type semiconductor layer4F.

The boundary between the regions F1and F2, which is respectively formed by the mask material56inFIG.16is defined by a straight portion43F connected to the straight portion41F at an obtuse angle and a straight portion44F connected to the straight portion42F at an obtuse angle in plan view. The straight portion43F and the straight portion44F form one straight line.

FIG.16illustrates the arrangement of the second impurity implantation openings54, in a manner where each of the second implantation openings54has the pattern width W which is narrower than the next one and each pattern interval I is formed which is wider than the next one in the direction toward a portion corresponding to the curved portion40F, that is, the closer the second implantation opening54formed to the outer side of the semiconductor device1004is, the narrower the pattern width W the second implantation opening54has so as to establish W1>W2 . . . >Wn, and the wider each pattern interval I is formed so as to establish I1<I2 . . . <In.

In a semiconductor device1004of the second embodiment, when the N-type semiconductor layer4A is elongated to become the N-type semiconductor layer4F, the distance L of the N-type semiconductor layer4A is increased by the elongation value S, so that the on-resistance is reduced. Further, by arranging the second impurity implantation openings54in the region F1and making the impurity concentration lower than that in the region F2, and the impurity concentration of the region F1lowers toward the outer side of semiconductor device1004, the concentration of electric field in the corner area51of the N-type semiconductor layer4F is suppressed and a reduction in breakdown voltage property is prevented as compared with the N-type semiconductor layer4B.

It should be noted that, although in the fourth embodiment, an example of the arrangement of the second impurity implantation openings54has been described, as being in a manner where each of the second implantation openings54has the pattern width W which is narrower than the next one and each pattern interval I is formed which is wider than the next one, and the closer the second implantation opening54formed to the outer side of the semiconductor device1004is, the narrower the pattern width W the second implantation opening54has so as to establish W1>W2 . . . >Wn, and the wider each pattern interval I is formed so as to establish I1<I2 . . . <In, however, not both of the pattern widths W and the pattern intervals I of the second implantation openings54are required to be changed in widths and intervals thereof as they are provided closer to the outer side of the semiconductor device1004, either ones of the pattern widths W or the pattern intervals I may have a fixed width or a fixed interval.

The N-type semiconductor layer4F illustrated inFIGS.17and18is configured with the two regions F1and F2with different impurity concentrations. The contour line of the N-type semiconductor layer4F substantially matches that of the N-type semiconductor layer4B in plan view, and the region F1corresponds to the region formed by removing the N-type semiconductor layer4D from the N-type semiconductor layer4B. The region F2corresponds to a region formed by removing the region F1from the N-type semiconductor layer4F. Therefore, the boundary between the region F1and the region F2is, in plan view, is defined by the straight portion43F connected to the straight portion41F at an obtuse angle, the straight portion44F connected to the straight portion42F at an obtuse angle, and a curved portion45F each of both ends is connected to the straight portion43F and the straight portion44F. The impurity concentration is higher in the region F2than in the region F1, and the impurity concentration in the region F1lowers toward the outer side of the semiconductor device1004.

For forming the N-type semiconductor layer4F, an arrangement may also be adopted in which, the second impurity implantation openings54are in a manner where each of the second implantation openings54has the pattern width W which is narrower than the next one and each pattern interval I is formed which is wider than the next one, and the closer the second implantation opening54formed to the outer side of the semiconductor device1004is, the narrower the pattern width W the second implantation opening54has so as to establish W1>W2 . . . >Wn, and the wider each pattern interval I is formed so as to establish I1<I2 . . . <In, in the region F1corresponding to the region formed by removing the N-type semiconductor layer4D from the N-type semiconductor layer4B, as illustrated inFIGS.17and18. InFIG.17, the second impurity implantation openings54having a strip-shape are aligned, and inFIG.18, the second impurity implantation openings54having a dot-shape are arranged radially.

Further, although in the fourth embodiment, an example is illustrated in which the pattern widths W and the pattern intervals I of the second impurity implantation openings54are gradually changed as they are provided closer to the outer side of the semiconductor device1004so that the impurity concentration of the region F1lowers toward the outer side of the semiconductor device1004, as illustrated inFIGS.19and20, the second impurity implantation openings54may simply be arranged radially with the pattern widths W being constant.FIG.19illustrates the second impurity implantation openings54having a rectangular shape, andFIG.20illustrates the second impurity implantation openings54having a dot-shape. In bothFIGS.19and20, every interval between the second impurity implantation openings54adjacent each other in the direction along the curved portion increases in the radial direction.

Although inFIGS.16to20, the corner area51has been described, the same configuration as inFIGS.16to20is applicable to the shapes of the other three corner areas.

Also, the back gate layer and the source layer of the second embodiment may be configured like the P-type semiconductor layer16and the N-type semiconductor layers18and19inFIG.6.

In addition to the above, the embodiments can be combined, components of the embodiments can appropriately be modified, or components of embodiments can appropriately be omitted.

While the disclosure has been illustrated and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.