Complex region detection for display stream compression

A method and apparatus for detecting a complex region of an image are disclosed. In one example, the method may involve calculating complexity values for a current block, a next block, and a previous block. The method may involve: (i) detecting that the previous complexity value is less than a first threshold value, and that the next complexity value is greater than a second threshold value; and (ii) determining that neither a transition to the current block nor a transition to the previous block is a flat-to-complex region transition. The method may involve detecting a flat-to-complex region transition when transitioning to the next block in response to (i) and (ii).

TECHNICAL FIELD

This disclosure relates to the field of video coding and compression, and particularly, to video compression for transmission over display links, such as display stream compression (DSC).

BACKGROUND

Digital video capabilities can be incorporated into a wide range of displays, including digital televisions, personal digital assistants (PDAs), laptop computers, desktop monitors, digital cameras, digital recording devices, digital media players, video gaming devices, video game consoles, cellular or satellite radio telephones, video teleconferencing devices, and the like. Display links are used to connect displays to appropriate source devices. The bandwidth requirements of display links are proportional to the resolution of the displays, and thus, high-resolution displays require large bandwidth display links. Some display links do not have the bandwidth to support high resolution displays. Video compression can be used to reduce the bandwidth requirements such that lower bandwidth display links can be used to provide digital video to high resolution displays.

Others have tried to utilize image compression on the pixel data. However, such schemes are sometimes not visually lossless or can be difficult and expensive to implement in conventional display devices.

The Video Electronics Standards Association (VESA) has developed display stream compression (DSC) as a standard for display link video compression. The display link video compression technique, such as DSC, should provide, among other things, picture quality that is visually lossless (i.e., pictures having a level of quality such that users cannot tell the compression is active). The display link video compression technique should also provide a scheme that is easy and inexpensive to implement in real-time with conventional hardware.

SUMMARY

In one aspect, there is provided a method for detecting a complex region of an image, wherein a slice of the image includes a current block, a next block, and a previous block. The method may involve calculating a current complexity value for the current block, a next complexity value for the next block, and a previous complexity value for the previous block. The method may involve: detecting that the previous complexity value is less than a first threshold value, and that the next complexity value is greater than a second threshold value, wherein the second threshold value is greater than the first threshold value; and determining that neither a transition to the current block nor a transition to the previous block is a flat-to-complex region transition. The method may involve detecting a flat-to-complex region transition when transitioning to the next block in response to (i) detecting that the previous complexity value is less than the first threshold value, and that the next complexity value is greater than the second threshold value, and (ii) determining that neither the transition to the current block nor the transition to the previous block is a flat-to-complex region transition.

In another aspect, calculating the current complexity value for the current block, the next complexity value for the next block, and the previous complexity value for the previous block may involve, for each block among the current, next, and previous blocks, (i) applying a transformation (e.g., a discrete cosine transform (DCT) or a Hadamard transform) to determine transform coefficients and (ii) determining a defined absolute sum of the transform coefficients. In yet another aspect, the method may further involve adjusting a quantization parameter (QP) in response to detecting a flat-to-complex region transition.

In still another aspect, there is provided a device for detecting a complex region of an image, wherein a slice of the image includes a current block, a next block, and a previous block. The device may include a memory configured to store video information relating to the image. The device may include at least one processor (e.g., part of an integrated circuit (IC) and/or graphics processing unit (GPU)) coupled to the memory and configured to: calculate a current complexity value for the current block, a next complexity value for the next block, and a previous complexity value for the previous block; detect that the previous complexity value is less than a first threshold value, and that the next complexity value is greater than a second threshold value, wherein the second threshold value is greater than the first threshold value; determine that neither a transition to the current block nor a transition to the previous block is a flat-to-complex region transition; and detect a flat-to-complex region transition when transitioning to the next block in response to (i) detecting that the previous complexity value is less than the first threshold value, and that the next complexity value is greater than the second threshold value, and (ii) determining that neither the transition to the current block nor the transition to the previous block is a flat-to-complex region transition.

DETAILED DESCRIPTION

In general, the present disclosure relates to techniques of improving video compression techniques such as display stream compression (DSC). More specifically, this disclosure relates to systems and methods for detecting a transition from a flat or smooth region to a complex region of an image to be coded. Described herein are techniques for complex region detection in video data in the context of video compression techniques, such as, for example, DSC. Aspects of this disclosure relate to ensuring that underflow or overflow of the rate buffer during coding is avoided.

While certain embodiments are described herein in the context of the DSC standard, one having ordinary skill in the art would appreciate that systems and methods disclosed herein may be applicable to any suitable video coding standard. For example, embodiments disclosed herein may be applicable to one or more of the following standards: International Telecommunication Union (ITU) Telecommunication Standardization Sector (ITU-T) H.261, International Organization for Standardization/International Electrotechnical Commission (ISO/IEC) Moving Picture Experts Group-1 (MPEG-1) Visual, ITU-T H.262 or ISO/IEC MPEG-2 Visual, ITU-T H.263, ISO/IEC MPEG-4 Visual, ITU-T H.264 (also known as ISO/IEC MPEG-4 AVC), High Efficiency Video Coding (HEVC), and any extensions to such standards. The techniques described herein may be particularly applicable to standards which incorporate a constant bit rate (CBR) buffer model. Also, the techniques described in this disclosure may become part of standards developed in the future. In other words, the techniques described in this disclosure may be applicable to previously developed video coding standards, video coding standards currently under development, and forthcoming video coding standards.

The concepts of this disclosure may be integrated in or a be part of a codec (e.g., DSC) that includes several elements and/or modes aimed at encoding/decoding various types of content with substantially visually lossless performance. This disclosure provides a complex region detection algorithm that detects the transition from a smooth/flat region (e.g., a region that is easy to code) to a complex region (e.g., a region that is relatively difficult to code or requires a higher number of bits to code). When such a transition is detected, the quantization parameter (QP) used in the codec is increased to a high value in order to reduce the expected rate required to code the current block. This is desirable as the complexity of visual information in the complex region may mask artifacts more so than would occur for a smooth/flat region. In addition, the low rate is desirable to prevent the coder from spending too many bits on a complex block (e.g., well in excess of the target bitrate).

Video Coding Standards

A digital image, such as a video image, a TV image, a still image or an image generated by a video recorder or a computer, may include pixels or samples arranged in horizontal and vertical lines. The number of pixels in a single image is typically in the tens of thousands. Each pixel typically contains luminance and chrominance information. Without compression, the sheer quantity of information to be conveyed from an image encoder to an image decoder would render real-time image transmission impractical. To reduce the amount of information to be transmitted, a number of different compression methods, such as JPEG, MPEG and H.263 standards, have been developed.

In addition, a video coding standard, namely DSC, has been developed by VESA. The DSC standard is a video compression standard which can compress video for transmission over display links. As the resolution of displays increases, the bandwidth of the video data required to drive the displays increases correspondingly. Some display links may not have the bandwidth to transmit all of the video data to the display for such resolutions. Accordingly, the DSC standard specifies a compression standard for interoperable, visually lossless compression over display links.

The DSC standard is different from other video coding standards, such as H.264 and HEVC. DSC includes intra-frame compression, but does not include inter-frame compression, meaning that temporal information may not be used by the DSC standard in coding the video data. In contrast, other video coding standards may employ inter-frame compression in their video coding techniques.

Video Coding System

The attached drawings illustrate examples. Elements indicated by reference numbers in the attached drawings correspond to elements indicated by like reference numbers in the following description. In this disclosure, elements having names that start with ordinal words (e.g., “first,” “second,” “third,” and so on) do not necessarily imply that the elements have a particular order. Rather, such ordinal words are merely used to refer to different elements of a same or similar type.

FIG. 1Ais a block diagram that illustrates an example video coding system10that may utilize techniques in accordance with aspects described in this disclosure. As used described herein, the term “video coder” or “coder” refers generically to both video encoders and video decoders. In this disclosure, the terms “video coding” or “coding” may refer generically to video encoding and video decoding. In addition to video encoders and video decoders, the aspects described in the present application may be extended to other related devices such as transcoders (e.g., devices that can decode a bitstream and re-encode another bitstream) and middleboxes (e.g., devices that can modify, transform, and/or otherwise manipulate a bitstream).

As shown inFIG. 1A, video coding system10includes a source device12that generates encoded video data to be decoded at a later time by a destination device14. In the example ofFIG. 1A, the source device12and destination device14constitute separate devices. It is noted, however, that the source device12and destination device14may be on or part of the same device, as shown in the example ofFIG. 1B.

With reference once again, toFIG. 1A, the source device12and the destination device14may respectively comprise any of a wide range of devices, including desktop computers, notebook (e.g., laptop) computers, tablet computers, set-top boxes, telephone handsets such as so-called “smart” phones, so-called “smart” pads, televisions, cameras, display devices, digital media players, video gaming consoles, in-car computers, video streaming devices, devices that are wearable (or removeably attachable) by (to) an entity (e.g., a human, an animal, and/or another controlled device) such as eyewear and/or a wearable computer, devices or apparatus that can be consumed, ingested, or placed within an entity, and/or the like. In various embodiments, the source device12and the destination device14may be equipped for wireless communication.

The destination device14may receive, via link16, the encoded video data to be decoded. The link16may comprise any type of medium or device capable of moving the encoded video data from the source device12to the destination device14. In the example ofFIG. 1A, the link16may comprise a communication medium to enable the source device12to transmit encoded video data to the destination device14in real-time. The encoded video data may be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to the destination device14. The communication medium may comprise any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide-area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment that may be useful to facilitate communication from the source device12to the destination device14.

In the example ofFIG. 1A, the source device12includes a video source18, video encoder20and the output interface22. In some cases, the output interface22may include a modulator/demodulator (modem) and/or a transmitter. In the source device12, the video source18may include a source such as a video capture device, e.g., a video camera, a video archive containing previously captured video, a video feed interface to receive video from a video content provider, and/or a computer graphics system for generating computer graphics data as the source video, or a combination of such sources. As one example, if the video source18is a video camera, the source device12and the destination device14may form so-called “camera phones” or “video phones”, as illustrated in the example ofFIG. 1B. However, the techniques described in this disclosure may be applicable to video coding in general, and may be applied to wireless and/or wired applications.

The captured, pre-captured, or computer-generated video may be encoded by the video encoder20. The encoded video data may be transmitted to the destination device14via the output interface22of the source device12. The encoded video data may also (or alternatively) be stored onto the storage device31for later access by the destination device14or other devices, for decoding and/or playback. The video encoder20illustrated inFIGS. 1A and 1Bmay comprise the video encoder20illustratedFIG. 2Aor any other video encoder described herein.

In the example ofFIG. 1A, the destination device14includes the input interface28, a video decoder30, and a display device32. In some cases, the input interface28may include a receiver and/or a modem. The input interface28of the destination device14may receive the encoded video data over the link16and/or from the storage device31. The encoded video data communicated over the link16, or provided on the storage device31, may include a variety of syntax elements generated by the video encoder20for use by a video decoder, such as the video decoder30, in decoding the video data. Such syntax elements may be included with the encoded video data transmitted on a communication medium, stored on a storage medium, or stored a file server. The video decoder30illustrated inFIGS. 1A and 1Bmay comprise the video decoder30illustrated inFIG. 2Bor any other video decoder described herein.

The display device32may be integrated with, or external to, the destination device14. In some examples, the destination device14may include an integrated display device and also be configured to interface with an external display device. In other examples, the destination device14may be a display device. In general, the display device32displays the decoded video data to a user, and may comprise any of a variety of display devices such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

In related aspects,FIG. 1Bshows an example video coding system10′ wherein the source device12and the destination device14are on or part of a device11. The device11may be a telephone handset, such as a “smart” phone or the like. The device11may include a processor/controller device13(optionally present) in operative communication with the source device12and the destination device14. The video coding system10′ ofFIG. 1B, and components thereof, are otherwise similar to the video coding system10ofFIG. 1A, and components thereof.

The video encoder20and the video decoder30may operate according to a video compression standard, such as DSC. Alternatively, the video encoder20and the video decoder30may operate according to other proprietary or industry standards, such as the ITU-T H.264 standard, alternatively referred to as MPEG-4, Part 10, AVC, HEVC or extensions of such standards. The techniques of this disclosure, however, are not limited to any particular coding standard. Other examples of video compression standards include MPEG-2 and ITU-T H.263.

Video Coding Process

As mentioned briefly above, the video encoder20encodes video data. The video data may comprise one or more pictures. Each of the pictures is a still image forming part of a video. In some instances, a picture may be referred to as a video “frame.” When the video encoder20encodes the video data, the video encoder20may generate a bitstream. The bitstream may include a sequence of bits that form a coded representation of the video data. The bitstream may include coded pictures and associated data. A coded picture is a coded representation of a picture.

To generate the bitstream, the video encoder20may perform encoding operations on each picture in the video data. When the video encoder20performs encoding operations on the pictures, the video encoder20may generate a series of coded pictures and associated data. The associated data may include a set of coding parameters such as a QP. To generate a coded picture, the video encoder20may partition a picture into equally-sized video blocks. A video block may be a two-dimensional array of samples. The coding parameters may define a coding option (e.g., a coding mode) for every block of the video data. The coding option may be selected in order to achieve a desired rate-distortion performance.

In some examples, the video encoder20may partition a picture into a plurality of slices. Each of the slices may include a spatially distinct region in an image (e.g., a frame) that can be decoded independently without information from the rest of the regions in the image or frame. Each image or video frame may be encoded in a single slice or each image or video frame may be encoded in several slices. In DSC, the target bits allocated to encode each slice may be substantially constant. As part of performing an encoding operation on a picture, the video encoder20may perform encoding operations on each slice of the picture. When the video encoder20performs an encoding operation on a slice, the video encoder20may generate encoded data associated with the slice. The encoded data associated with the slice may be referred to as a “coded slice.”

DSC Video Encoder

FIG. 2Ais a block diagram illustrating an example of the video encoder20that may implement techniques in accordance with aspects described in this disclosure. The video encoder20may be configured to perform some or all of the techniques of this disclosure. In some examples, the techniques described in this disclosure may be shared among the various components of the video encoder20. In some examples, additionally or alternatively, a processor (not shown) may be configured to perform some or all of the techniques described in this disclosure.

For purposes of explanation, this disclosure describes the video encoder20in the context of DSC coding. However, the techniques of this disclosure may be applicable to other coding standards or methods.

In the example ofFIG. 2A, the video encoder20includes a plurality of functional components. The functional components of the video encoder20include a color-space converter105, a buffer,110, a flatness detector115, a rate controller120, a predictor, quantizer, and reconstructor component125, a line buffer130, an indexed color history135, an entropy encoder140, a substream multiplexor145, and a rate buffer150. In other examples, the video encoder20may include more, fewer, or different functional components.

The color-space converter105may convert an input color-space to the color-space used in the coding implementation. For example, in one exemplary embodiment, the color-space of the input video data is in the red, green, and blue (RGB) color-space and the coding is implemented in the luminance Y, chrominance green Cg, and chrominance orange Co (YCoCg) color-space. The color-space conversion may be performed by method(s) including shifts and additions to the video data. It is noted that input video data in other color-spaces may be processed and conversions to other color-spaces may also be performed.

In related aspects, the video encoder20may include the buffer110, the line buffer130, and/or the rate buffer150. For example, the buffer110may hold the color-space converted video data prior to its use by other portions of the video encoder20. In another example, the video data may be stored in the RGB color-space and color-space conversion may be performed as needed, since the color-space converted data may require more bits.

The rate buffer150may function as part of the rate control mechanism in the video encoder20, which will be described in greater detail below in connection with rate controller120. The bits spent on encoding each block can vary highly substantially based on the nature of the block. The rate buffer150can smooth the rate variations in the compressed video. In some embodiments, a CBR buffer model is employed in which bits are taken out from the buffer at a constant bit rate. In the CBR buffer model, if the video encoder20adds too many bits to the bitstream, the rate buffer150may overflow. On the other hand, the video encoder20must add enough bits in order to prevent underflow of the rate buffer150.

On the video decoder side, the bits may be added to rate buffer155of the video decoder30(seeFIG. 2Bwhich is described in further detail below) at a constant bit rate, and the video decoder30may remove variable numbers of bits for each block. To ensure proper decoding, the rate buffer155of the video decoder30should not “underflow” or “overflow” during the decoding of the compressed bit stream.

In some embodiments, the buffer fullness (BF) can be defined based on the values BufferCurrentSize representing the number of bits currently in the buffer and BufferMaxSize representing the size of the rate buffer150, i.e., the maximum number of bits that can be stored in the rate buffer150at any point in time. The BF may be calculated as:
BF=((BufferCurrentSize*100)/BufferMaxSize)

It is noted that the above approach to calculating BF is merely exemplary, and that the BF may be calculated in any number of different ways, depending on the particular implementation or context.

The flatness detector115can detect changes from complex (i.e., non-flat) areas in the video data to flat (i.e., simple or uniform) areas in the video data, and/or vice versa. The terms “complex” and “flat” will be used herein to generally refer to the difficulty for the video encoder20to encode the respective regions of the video data. Thus, the term complex as used herein generally describes a region of the video data as being complex for the video encoder20to encode and may, for example, include textured video data, high spatial frequency, and/or other features which are complex to encode. The term flat as used herein generally describes a region of the video data as being simple for the video encoder20to encoder and may, for example, include a smooth gradient in the video data, low spatial frequency, and/or other features which are simple to encode. The transitions from complex to flat regions may be used by the video encoder20to reduce quantization artifacts in the encoded video data. Specifically, the rate controller120and the predictor, quantizer, and reconstructor component125can reduce such quantization artifacts when the transitions from complex to flat regions are identified. Similarly, transitions from flat to complex regions may be used by the video encoder20to increase the QP in order to reduce the expected rate required to code a current block.

The rate controller120determines a set of coding parameters, e.g., a QP. The QP may be adjusted by the rate controller120based on the buffer fullness of the rate buffer150and image activity of the video data (e.g., a transition from complex to flat regions or vice versa) in order to maximize picture quality for a target bitrate which ensures that the rate buffer150does not overflow or underflow. The rate controller120also selects a particular coding option (e.g., a particular mode) for each block of the video data in order to achieve the optimal rate-distortion performance. The rate controller120minimizes the distortion of the reconstructed images such that it satisfies the bit-rate constraint, i.e., the overall actual coding rate fits within the target bit rate. Thus, one purpose of the rate controller120is to determine a set of coding parameters, such as QP(s), coding mode(s), etc., to satisfy instantaneous and average constraints on rate while maximizing rate-distortion performance.

The predictor, quantizer, and reconstructor component125may perform at least three encoding operations of the video encoder20. The predictor, quantizer, and reconstructor component125may perform prediction in a number of different modes. One example predication mode is a modified version of median-adaptive prediction. Median-adaptive prediction may be implemented by the lossless JPEG standard (JPEG-LS). The modified version of median-adaptive prediction which may be performed by the predictor, quantizer, and reconstructor component125may allow for parallel prediction of three consecutive sample values. Another example prediction mode is block prediction. In block prediction, samples are predicted from previously reconstructed pixels in the line above or to the left in the same line. In some embodiments, the video encoder20and the video decoder30may both perform an identical search on reconstructed pixels to determine the block prediction usages, and thus, no bits need to be sent in the block prediction mode. In other embodiments, the video encoder20may perform the search and signal block prediction vectors in the bitstream, such that the video decoder30need not perform a separate search. A midpoint prediction mode may also be implemented in which samples are predicted using the midpoint of the component range. The midpoint prediction mode may enable bounding of the number of bits required for the compressed video in even the worst-case sample.

The predictor, quantizer, and reconstructor component125also performs quantization. For example, quantization may be performed via a power-of-2 quantizer which may be implemented using a shifter. It is noted that other quantization techniques may be implemented in lieu of the power-of-2 quantizer. The quantization performed by the predictor, quantizer, and reconstructor component125may be based on the QP determined by the rate controller120. Finally, the predictor, quantizer, and reconstructor component125also performs reconstruction which includes adding the inverse quantized residual to the predicted value and ensuring that the result does not fall outside of the valid range of sample values.

It is noted that the above-described example approaches to prediction, quantization, and reconstruction performed by the predictor, quantizer, and reconstructor component125are merely illustrative and that other approaches may be implemented. It is also noted that the predictor, quantizer, and reconstructor component125may include subcomponent(s) for performing the prediction, the quantization, and/or the reconstruction. It is further noted that the prediction, the quantization, and/or the reconstruction may be performed by several separate encoder components in lieu of the predictor, quantizer, and reconstructor component125.

The line buffer130holds the output from the predictor, quantizer, and reconstructor component125so that the predictor, quantizer, and reconstructor component125and the indexed color history135can use the buffered video data. The indexed color history135stores recently used pixel values. These recently used pixel values can be referenced directly by the video encoder20via a dedicated syntax.

The entropy encoder140encodes the prediction residuals and any other data (e.g., indices identified by the predictor, quantizer, and reconstructor component125) received from the predictor, quantizer, and reconstructor component125based on the indexed color history135and the flatness transitions identified by the flatness detector115. In some examples, the entropy encoder140may encode three samples per clock per substream encoder. The substream multiplexor145may multiplex the bitstream based on a headerless packet multiplexing scheme. This allows the video decoder30to run three entropy decoders in parallel, facilitating the decoding of three pixels per clock. The substream multiplexor145may optimize the packet order so that the packets can be efficiently decoded by the video decoder30. It is noted that different approaches to entropy coding may be implemented, which may facilitate the decoding of power-of-2 pixels per clock (e.g., 2 pixels/clock or 4 pixels/clock).

DSC Video Decoder

FIG. 2Bis a block diagram illustrating an example of the video decoder30that may implement techniques in accordance with aspects described in this disclosure. The video decoder30may be configured to perform some or all of the techniques of this disclosure. In some examples, the techniques described in this disclosure may be shared among the various components of the video decoder30. In some examples, additionally or alternatively, a processor (not shown) may be configured to perform some or all of the techniques described in this disclosure.

For purposes of explanation, this disclosure describes the video decoder30in the context of DSC coding. However, the techniques of this disclosure may be applicable to other coding standards or methods.

In the example ofFIG. 2B, the video decoder30includes a plurality of functional components. The functional components of the video decoder30include a rate buffer155, a substream demultiplexor160, an entropy decoder165, a rate controller170, a predictor, quantizer, and reconstructor component175, an indexed color history180, a line buffer185, and a color-space converter190. The illustrated components of the video decoder30are analogous to the corresponding components described above in connection with the video encoder20inFIG. 2A. As such, each of the components of the video decoder30may operate in a similar fashion to the corresponding components of the video encoder20as described above.

QP Calculation

In one approach, the QP for the current block (denoted as currQP) may be derived or calculated based on the following equation:
currQP=prevQ+QpAdj*(diffBits>0?1:−1),

where prevQP is the QP associated with the previous block, diffBits represents the difference between the previousBlockBits and targetBits, QpAdj is the QP offset value (e.g., QP adjustment value) that is calculated based on the magnitude of diffBits, previousBlockBits represents the number of bits used to code the previous block, and targetBits represents a target number of bits in which to code the current block. When previousBlockBits>targetBits, diffBits is positive, and the current block QP may be derived by adding the offset value QpAdj to the prevQP value. In other words, the QP value does not decrease in value from the prevQP value when diffBits is positive. When previousBlockBits≤targetBits, diffBits is negative or zero, and currQP does not increase from the prevQP value. It is noted that the offset value QpAdj may be calculated, for example, as a function of diffBits in such a way that QpAdj monotonically increases as the magnitude of diffBits increases.

One technique, referred to herein as a default technique, for calculating the QP adjustment value QpAdj will now be described with reference toFIG. 3.FIG. 3provides a graph300including an axis on which values of diffBits starting a zero are plotted. In the default technique, when diffBits>0, diffBits may be classified into K+1 ranges using K threshold values. These threshold values are illustrated by the labels Threshold1, Threshold2, Threshold3, . . . , and Threshold K and the ranges are illustrated by the labels Range1, Range2, Range3, . . . , and Range K+1. In the default technique ofFIG. 3, there is shown one approach to segmenting diffBits into K+1 ranges using K threshold values. Each range may be associated with a specific QpAdj value, where the QpAdj value increases as the range index increases. When diffBits≤0, the absolute value of diffBits may be classified into J+1 ranges using J threshold values (not illustrated), and there may be a specific QpAdj value assigned for each of the J+1 ranges.

In other aspects, the currQP value may be adjusted based on the fullness of the buffer (which may be represented in terms of buffer fullness BF), in order to prevent underflow and/or overflow of the buffer. In particular, when BF exceeds a certain threshold (e.g., P1), currQP may be incremented by a fixed offset value (e.g., p1). For example, currQP may be adjusted as follows: currQP+=p1. Further, when BF falls below a certain threshold (e.g., Q1), currQP may be decremented by q1, e.g., currQP−=q1. In certain aspect, a plurality of thresholds may be employed, and for each threshold there may be a corresponding offset value to adjust currQP.

When a transition from a complex region to a flat region is identified or when a flat region is identified, the currQP may be set to a low value (e.g., a value below a defined currQP value), as described in further detail below.

Detecting Transition from Flat to Complex Regions

With reference toFIG. 4, one or more techniques may be utilized to detect a transition from a flat/smooth region to a complex region.FIG. 4illustrates an example region of interest400which may be a frame or portion thereof, such as, for example, a slice of the frame. The region400may include and three successive blocks405,410, and415. In this example, block405corresponds to a flat region/portion of the region400, block410corresponds to a transition region/portion of the region400, and block415corresponds to a complex region/portion of the region400. As shown, the content of block405is flat, smooth, or uniform. The content of block415is textured and exhibits patterns that are not uniform throughout. The block410includes a transition from uniform to non-uniform content. As described below, a complexity calculation made be performed for each of the blocks405,410, and415.

As used herein, a flat block may refer to a block which has a complexity value that is lower than a complexity threshold. The threshold at which a block is determined to be flat may be set based on various design criteria such as the number of bits required to code the block. Similarly, a non-flat or complex block may refer to a block which is not flat, e.g., has a complexity value which is greater than or equal to the complexity threshold. Various other categorizations of blocks may be employed based on the associated complexities of the blocks, and such categorizations may be ranges defined by thresholds in the complexity values of the blocks.

The terms flat and complex may also apply to regions other than blocks. In this case, although the regions may not be the same size as a block, e.g., the regions may not be a size which is discretely encoded/decoded, regions may also be categorized as flat or complex based on a complexity of the region. For example, a region may be referred to as a flat region if each block within that region is a flat block. However, a flat region may not have the same boundary as the block contained therein, and may the complexity of the region may be calculated over the entire region. Complex regions may be defined similarly. Thus, a region may be categorized as flat or complex by comparing a complexity value for the region to a complexity threshold, which may be different from the complexity threshold for blocks. Further, since regions may be divided into blocks for coding, the term region may be used herein conceptually to facilitate the understanding of various aspects of this disclosure.

As described above, in order to categorize a block as flat or complex, a complexity value for the block may be determined. The complexity value for a block may be determined according to various techniques, as long as the complexity value is representative of the difficulty of encoding the block, e.g., the number of bits that may be required to code the block without introducing visible artifacts.

The framework of the proposed flatness detection technique is shown in an example complexity detection system500ofFIG. 5. The system500may receive as input the blocks405,410, and415ofFIG. 4, or information regarding such blocks. In one implementation, the system500may perform a complexity calculation for each of the blocks405,410, and415to calculate per-block complexity values denoted as Ccur, Cnext, and Cprev. For example, the system500may include complexity calculation units505,510, and515corresponding to each of the blocks405,410, and415, respectively, and may output calculate complexity values Cprev, Ccur, and Cnext, respectively, to a detector520. In another implementation, fewer than three complexity values may be calculated for each block. For example, the encoder may buffer or store the “current” and “next” block complexity values at a given time block which will become the “previous” and “current” complexity values, respectively, for the next block time. In this way, only the “next” block complexity value will need to be calculated for the next time block. Stated differently, the encoder may buffer or store the “current” and “next” block complexity values at a first time block which will become the “previous” and “current” complexity values, respectively, at a second block time, such that only the “next” block complexity value is calculated at the second time block.

In related aspects, the complexity calculation units505,510, and515, and/or the detector520, may be separate components, part of the same component or processor of a codec, or software modules that be performed by one or more processors. The features of the system500may be may be implemented in hardware, software, firmware, or any combination thereof. In further related aspects, the system500may receive information regarding or relating to any number of successive blocks for an image or region of interest (e.g., four successive blocks in a slice) and may perform complexity calculations for each of the successive blocks.

In one aspect, the complexity of a block may be calculated by taking a frequency transform (e.g., a discrete cosine transform (DCT), Hadamard transform, etc.) of the pixels in the block. The frequency transform may result in a number of frequency coefficients which may be summed to generate the complexity value. In another aspect, the direct current (DC or zero-frequency) coefficient and/or one or more low frequency coefficients may not be included in the sum. Various other techniques for determining the complexity value, such as applying a color transformation before the frequency transform, may also be implemented.

In related aspects, the absolute value or absolute square value of the transform coefficients may be summed to calculate the complexity value for a block. In further related aspects, the luma channel may be used to calculate the complexity value, or both the luma/chroma channels may be used to calculate the complexity value.

In yet further related aspects, a subset of the transform coefficients may be considered while calculating the absolute sum or absolute square sum, i.e., less than all of the transform coefficients in the block may be considered in some example approaches.

In still further aspects, each transform coefficient may be multiplied with a weight, where the weight applied to each coefficient may vary or be constant. Then, the absolute value or absolute square value of the weighted coefficients may be calculated.

With reference once again to the example ofFIG. 5, the detector500may determine, based on Cprev, Ccur, and Cnext, whether blocks405,410, and415include a transition from a flat region to a complex region. For example, the output of the detector500may be a binary result, such as 0 to indicate that there is not a flat-to-complex region transition, and 1 to indicate that there is a flat-to-complex region transition.

The determination of whether there is transition from a flat region to a complex region may be performed by checking one or more conditions based on the complexity values of the successive blocks (e.g., blocks405,410, and415) in a region of interest (e.g., region400). In one embodiment, the determination of whether there is a flat-to-complex region transition is performed via checking the following Condition 1 and Condition 2.
(Cprev<T0)&&(Cnext>T1)  Condition 1:

Regarding Condition 1, the thresholds T0and T1may be tuned based on the parameters of the codec. Preferably, the ordering T0<T1should be followed. In related aspects, detecting that there is transition from a flat region to a complex region may include determining that (i) a complexity value for the previous block405is less than (or less than or equal to) a first threshold (e.g., T0), which is indicative of the previous block405corresponding to a flat region, and that (ii) a complexity value for the next block415is greater than (or greater than or equal to) a second threshold (e.g., T1), which is indicative of the next block415corresponding to a complex region. Here, the indications that the previous block corresponds to a flat region and that the next block415corresponds to a complex region further indicate that there is transition from a flat region to a complex region in the current block410, i.e., that the current block410is a transition block.
(C0=false,C1=false  Condition 2:

Regarding Condition 2, the values C0and C1in Condition 2 are Boolean in nature and represent the previous history of flat-to-complex region detection, as shown inFIG. 6. For example, the values C0and C1for previous block times, as well as C2for a current block time, may be stored in a memory storage unit600. In one aspect, at each block time, the complexity values are shifted left by one. In another aspect, the previous history of flat-to-complex region detection—namely, the values C0and C1for previous block times—are used to check Condition 2 above. In yet another aspect, if both parts of Condition 1 are met, then the value C2inFIG. 6will be set to true. Even when a flat-to-complex region transition is detected, the QP used may be increased (compared to the previous flat block) at the transition block or the next block after the transition block in order to reduce the expected rate required to code the current/next block. It is noted, however, that the QP value at the transition block cannot be too high (e.g., exceeding a defined QP value), as the transition block contains both partially flat information and partially complex information. For example, when the QP value for a transition block exceeds a defined QP value, artifacts may be generated in the flat potion of the block which may be noticeable within an image reconstructed from the transition block.

As such, it may be desirable to delay increasing the QP until after the transition block. For example, the QP may be increased for the block immediately following the detected transition block (e.g., for block415which follows block410). If the QP is high for the first entirely complex block (e.g., block415), then the complexity may mask the presence of artifacts.

Accordingly, the next decision of whether the QP should be adjusted for the current block depends on the Boolean value of C1. If C1is true, then the QP for the current block should be increased to a high value.

At the encoder side, at the beginning of processing each new block, the history of detection results is updated. That is, C1→C0, C2→C1, C2=false. This is done prior to computing the detection result for the current block. Essentially, this adds an offset of one block between detecting a flat-to-complex transition and adjusting the QP. As discussed above, this ensures that the QP will remain at a low value for the transition block. In addition, this ensures that multiple blocks in a row cannot be detected as flat-to-complex transitions.

In another example, the comparison operators in Condition 1 may be replaced with different comparison operators. For example, instead of Cprev<T0, instead Cprev≤Tc, may be used instead.

One advantage of the above embodiment is that the detection of flat-to-complex region transitions allows the encoder to increase the QP for complex regions. This will decrease the expected rate required to code the block, and the artifacts which result will be masked by the complexity of the region. Also, the result of the flat-to-complex transition detection can be signaled explicitly to the decoder in the encoded bitstream using one bit/block. This allows the decoder to adjust the QP without having to compute complexity values as is done in the encoder. Furthermore, the complexity calculations and look-ahead data utilized in the present technique for detecting flat-to-complex region transitions may also be utilized for detecting complex-to-flat region transitions, thereby realizing efficiencies for a fixed rate codec, such as DSC or the like. In one embodiment, there is provided a technique that may involve signaling a flat-to-complex transition using one bit. In related aspects, flat-to-complex is one of a set of possible flatness detections or classifications, which can be grouped together. For example, if there are four classes of flatness (e.g., flat-to-complex, complex-to-flat, somewhat flat, and very flat), then the result may be signaled with one of a set of 2-bit codes.

In one embodiment, when a flat-to-complex transition is identified, the QP value of the block may be set to a predefined value (e.g., a fixed high value) or the QP may be increased by a predefined increment or value (e.g. a fixed adjustment value).

Example Flowcharts for Detecting a Complex Region of an Image

With reference toFIG. 7, an example procedure for detecting a transition from a flat region to a complex region of an image will be described. A slice of the image may include a current block, a next block, and a previous block.

FIG. 7is a flowchart illustrating a method700for coding video data, according to an embodiment of the present disclosure. The steps illustrated inFIG. 7may be performed by a video encoder (e.g., the video encoder20inFIG. 2A), a video decoder (e.g., the video decoder30inFIG. 2B), or component(s) thereof, such as for example, the flatness detector115, the rate controller120, the predictor, quantizer, and reconstructor component125, the entropy encoder140, and the rate buffer150. For convenience, method700is described as performed by a video coder (also simply referred to as coder), which may be the video encoder20, the video decoder30, or another component.

The coder or component(s) thereof may be implemented on device that includes an integrated global memory shared by a plurality of programmable compute units that includes a buffer, wherein the buffer may include a first-in-first-out (FIFO) buffer. The device may further include an integrated circuit (IC) that may include at least one processor or processor circuit (e.g., a central processing unit (CPU)) and/or a graphics processing unit (GPU), wherein the GPU may include one or more programmable compute units.

The method700begins at block710. At block710, the coder calculates a current complexity value for the current block, a next complexity value for the next block, and a previous complexity value for the previous block. Block710may involve the coder, for each block among the current, next, and previous blocks, (i) applying a transformation to determine transform coefficients and (ii) determining a defined absolute sum of the transform coefficients. Applying the transformation may involve applying one of a DCT and a Hadamard transform. Determining the defined absolute sum may involve determining one of an absolute sum and an absolute square sum of the transform coefficients.

At block720, the coder detects that the previous complexity value is less than a first threshold value, and that the next complexity value is greater than a second threshold value, wherein the second threshold value is greater than the first threshold value.

At block730, the coder determines that neither a transition to the current block nor a transition to the previous block is a flat-to-complex region transition. Wherein the coder performs block730based on the complexity values of the current, next, and previous blocks at a current block time, and/or complexity values of the current, next, and previous blocks at one or more previous block times.

At block740, the coder detects a flat-to-complex region transition when transitioning to the next block in response to (i) detecting that the previous complexity value is less than the first threshold value, and that the next complexity value is greater than the second threshold value, and (ii) determining that neither the transition to the current block nor the transition to the previous block is a flat-to-complex region transition.

At block750, the coder may optionally adjust a QP in response to detecting a flat-to-complex region transition, and/or signal an indication of the transition from an encoder to a decoder of a codec in response to detecting a flat-to-complex region transition when transitioning to the next block. The method700may end at block740or at block750.

OTHER CONSIDERATIONS

It should be noted that aspects of this disclosure have been described from the perspective of an encoder, such as the video encoder20inFIG. 2A. However, those skilled in the art will appreciate that the reverse operations to those described above may be applied to decode the generated bitstream by, for example, the video decoder30inFIG. 2B.

Although the foregoing has been described in connection with various different embodiments, features or elements from one embodiment may be combined with other embodiments without departing from the teachings of this disclosure. However, the combinations of features between the respective embodiments are not necessarily limited thereto. Various embodiments of the disclosure have been described. These and other embodiments are within the scope of the following claims.