Level shifter

A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.

BACKGROUND

The present disclosure relates generally to electronic circuits, and, more particularly, to a level shifter.

Some integrated circuits typically include various voltage domains. When functional circuits associated with one voltage domain generate signals that are to be utilized by functional circuits associated with a different voltage domain, voltage translation of the signals may be required. To implement the voltage translation between the voltage domains, level shifters are utilized in the integrated circuits. A level shifter receives a signal that is associated with one voltage domain and outputs another signal that is associated with a different voltage domain. In other words, the outputted signal is a level-shifted version of the received signal. Some types of level shifters utilize an amplification circuit and a series of buffers. Such a level shifter, however, distorts a duty cycle of the outputted signal.

SUMMARY

In an embodiment of the present disclosure, a circuit is disclosed. The circuit may include a level shifter. The level shifter may include a control circuit and a bias circuit that may be coupled with the control circuit. The control circuit may be configured to receive a bias voltage, a first signal associated with a first voltage domain, and a first supply voltage and a second supply voltage that are associated with a second voltage domain, and output a second signal associated with the second voltage domain. The bias circuit may be configured to generate the bias voltage that is indicative of a duty cycle of the second signal, and provide the bias voltage to the control circuit. The duty cycle of the second signal is controlled based on the bias voltage such that a difference between a duty cycle of the first signal and an inverse of a duty cycle of the second signal is less than a first tolerance limit associated with the level shifter.

In another embodiment of the present disclosure, a level shifting method is disclosed. The level shifting method may include receiving a bias voltage, a first signal associated with a first voltage domain, and first and second supply voltages associated with a second voltage domain by a control circuit of a level shifter. The level shifting method may further include outputting a second signal associated with the second voltage domain by the control circuit. The second signal may be outputted based on the bias voltage, the first signal, and the first and second supply voltages. Further, the level shifting method may include generating the bias voltage by a bias circuit of the level shifter. The bias voltage may be indicative of a duty cycle of the second signal. The level shifting method may further include providing, by the bias circuit, the bias voltage to the control circuit. The duty cycle of the second signal may be controlled based on the bias voltage such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a first tolerance limit associated with the level shifter.

In some embodiments, the control circuit acts as a current-controlled inverter such that a current associated with the control circuit is controlled based on the bias voltage. The control circuit acts as a current-controlled inverter when a difference between the first supply voltage and the bias voltage is greater than or equal to a first threshold value and when a difference between the bias voltage and the second supply voltage is greater than or equal to a second threshold value. When the control circuit acts as the current-controlled inverter, the control circuit outputs the second signal as an inverted level-shifted version of the first signal. Further, the first supply voltage is greater than the second supply voltage.

In some embodiments, the bias circuit may include an integrator that may be configured to integrate a third signal and generate the bias voltage such that the bias voltage is an integrated version of the third signal. The third signal is derived from the second signal.

In some embodiments, the circuit may further include a first functional circuit that may be coupled with the control circuit. The first functional circuit may be configured to receive a third supply voltage and a fourth supply voltage associated with the first voltage domain, and generate the first signal. The first functional circuit may further be configured to provide the first signal to the control circuit.

In some embodiments, the level shifter may further include a set of inverters that may be coupled with the control circuit and the bias circuit. The set of inverters may be configured to receive the second signal, output a third signal such that a voltage range of the third signal is equal to a voltage range of the second signal, and provide the third signal to the bias circuit. The bias circuit generates the bias voltage that is indicative of a duty cycle of the third signal.

In some embodiments, the second signal is an inverted version of the first signal and the third signal has a same logic state as that of the second signal. A difference between the duty cycle of the third signal and the duty cycle of the second signal is less than a second tolerance limit associated with the level shifter.

In some embodiments, the level shifter may further include an inverter that may be coupled with the set of inverters. The inverter may be configured to receive the third signal and output a fourth signal that is an inverted version of the third signal. A voltage range of the fourth signal is equal to the voltage range of the third signal. A difference between a duty cycle of the fourth signal and an inverse of the duty cycle of the third signal is less than a third tolerance limit associated with the level shifter.

In some embodiments, the circuit may further include a second functional circuit that may be coupled with the inverter. The second functional circuit may be configured to receive the fourth signal and the first and second supply voltages and perform a set of functional operations associated therewith.

In some embodiments, the bias circuit may include a resistor and a capacitor that may be configured to integrate a third signal and generate the bias voltage such that the bias voltage is an integrated version of the third signal. The third signal is derived from the second signal. The bias circuit may further include a switch that may be configured to receive a fourth signal. The switch may be activated and deactivated based on activation and deactivation of the fourth signal, respectively. When the switch is activated, the bias circuit provides the bias voltage to the control circuit.

In some embodiments, the switch may be coupled between the resistor and the capacitor.

In some embodiments, the switch may be coupled between the capacitor and the control circuit.

In some embodiments, the control circuit may include a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor has a first terminal, a second terminal, and a third terminal. The first terminal of the first transistor may be configured to receive the first supply voltage. The second terminal of the first transistor may be coupled with the bias circuit. The second terminal of the first transistor may be configured to receive the bias voltage from the bias circuit. The second transistor has a first terminal that may be coupled with the third terminal of the first transistor and a second terminal that may be configured to receive the first signal. Further, the second transistor has a third terminal that may be configured to output the second signal. The third transistor has a first terminal, a second terminal, and a third terminal. The second terminal of the third transistor may be coupled with the second terminal of the first transistor, and the third terminal of the third transistor may be coupled with the third terminal of the second transistor. The fourth transistor has a first terminal that may be configured to receive the second supply voltage and a second terminal that may be coupled with the second terminal of the second transistor. Further, the fourth transistor has a third terminal that may be coupled with the first terminal of the third transistor. The first supply voltage is greater than the second supply voltage.

In some embodiments, the first transistor is deactivated when the bias voltage is equal to the first supply voltage, and the first transistor is activated when the difference between the first supply voltage and the bias voltage is greater than or equal to a first threshold value. The third transistor is deactivated when the bias voltage is equal to the second supply voltage, and the third transistor is activated when the difference between the bias voltage and the second supply voltage is greater than or equal to a second threshold value.

In some embodiments, when the first and third transistors are activated, a drive strength of the first transistor and a drive strength of the third transistor are controlled based on the bias voltage such that the difference between the duty cycle of the first signal and the inverse of the duty cycle of the second signal is less than the first tolerance limit.

In some embodiments, the level shifter may further include a fifth transistor that has a first terminal configured to receive the first supply voltage and a second terminal configured to receive a third signal. An operation of the level shifter is controlled based on the third signal. The fifth transistor further has a third terminal that may be coupled with the bias circuit and the second terminals of the first and third transistors. The fifth transistor is activated and deactivated based on deactivation and activation of the third signal, respectively.

In some embodiments, when the fifth transistor is activated, the bias voltage is equal to the first supply voltage, the first transistor is deactivated, and the third transistor is activated. When the fifth transistor is deactivated, the bias voltage reduces such that the first transistor is activated when the difference between the first supply voltage and the bias voltage is greater than or equal to a first threshold value. When the first and third transistors are activated, the control circuit acts as a current-controlled inverter and outputs the second signal as an inverted level-shifted version of the first signal.

In some embodiments, when the fifth transistor is activated, the bias voltage is equal to the first supply voltage, the first transistor is deactivated, and the third transistor is activated. When the fifth transistor is deactivated, the bias voltage is equal to the second supply voltage, the third transistor is deactivated, and the first transistor is activated. When the fifth transistor remains deactivated, the bias voltage increases such that the third transistor is activated when the difference between the bias voltage and the second supply voltage is greater than or equal to a second threshold value. When the first and third transistors are activated, the control circuit acts as a current-controlled inverter and outputs the second signal as an inverted level-shifted version of the first signal.

In some embodiments, the level shifter may further include a sixth transistor that has a first terminal configured to receive the second supply voltage and a second terminal configured to receive a fourth signal that is an inverted version of the third signal. The sixth transistor further has a third terminal that may be coupled with the third terminal of the second transistor. The third terminal of the sixth transistor may be configured to receive the second signal from the third terminal of the second transistor. Based on activation of the fourth signal, the sixth transistor is activated and the second signal is pulled down to the second supply voltage. Further, based on deactivation of the fourth signal, the sixth transistor is deactivated.

Various embodiments of the present disclosure disclose a level shifter. The level shifter may include a control circuit, a set of inverters, a bias circuit, and another inverter. The control circuit receives a bias voltage, a first signal that is associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal. The second signal is an inverted level-shifted version of the first signal. A difference between a duty cycle of the first signal and an inverse of a duty cycle of the second signal is less than a first tolerance limit associated with the level shifter.

The set of inverters receives the second signal and outputs a third signal. A voltage range of the third signal is equal to a voltage range of the second signal. Further, the third signal has a same logic state as that of the second signal. A difference between the duty cycle of the second signal and a duty cycle of the third signal is less than a second tolerance limit associated with the level shifter. The bias circuit receives the third signal, generates the bias voltage that is indicative of the duty cycle of the third signal, and provides the bias voltage to the control circuit such that the duty cycle of the second signal is controlled based on the bias voltage. Further, the inverter receives the third signal and outputs a fourth signal that is an inverted version of the third signal. A difference between a duty cycle of the fourth signal and an inverse of the duty cycle of the third signal is less than a third tolerance limit associated with the level shifter. A voltage range of the fourth signal is equal to the voltage range of the third signal. The fourth signal is provided to a functional circuit associated with the second voltage domain. The functional circuit performs various functional operations based on the fourth signal.

Thus, the level shifter translates the first signal to the fourth signal such that the fourth signal is the level-shifted version of the first signal, and has a same logic state as that of the first signal. In the level shifter of the present disclosure, the control circuit is biased based on the bias voltage such that a difference between the duty cycle of the first signal and the duty cycle of the fourth signal is less than a fourth tolerance limit, i.e., a sum of the first through third tolerance limits. Thus, the distortion of the duty cycle of the fourth signal is reduced. A conventional level shifter that reduces duty cycle distortion consumes a significant current, and in turn, a significant power. In the level shifter of the present disclosure, the bias voltage controls the control circuit such that the creation of a direct current path between a power supply and a ground terminal is prevented. Hence, a current in the level shifter of the present disclosure is significantly less than that in the conventional level shifter. Consequently, a power consumed by the level shifter of the present disclosure is significantly less than a power consumed by the conventional level shifter.

DETAILED DESCRIPTION

The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the present disclosure, and is not intended to represent the only form in which the present disclosure may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present disclosure.

FIG.1illustrates a schematic block diagram of an integrated circuit (IC)100in accordance with an embodiment of the present disclosure. The IC100may include a first power supply102that may be configured to generate a first supply voltage VDD1and a second supply voltage VSS1. The first supply voltage VDD1and the second supply voltage VSS1are associated with a first voltage domain. The first supply voltage VDD1is greater than the second supply voltage VSS1. Further, the IC100may include a second power supply104that may be configured to generate a third supply voltage VDD2and a fourth supply voltage VSS2. The third supply voltage VDD2and the fourth supply voltage VSS2are associated with a second voltage domain. The third supply voltage VDD2is greater than the fourth supply voltage VSS2.

AlthoughFIG.1illustrates that the IC100may include the first and second power supplies102and104, the scope of the present disclosure is not limited to it. In an alternate embodiment, the first and second power supplies102and104may be external to the IC100, without deviating from the scope of the present disclosure.

A voltage range of the first voltage domain (i.e., a difference between the first and second supply voltages VDD1and VSS1) is different than a voltage range of the second voltage domain (i.e., a difference between the third and fourth supply voltages VDD2and VSS2). In an embodiment, the voltage range of the first voltage domain is less than the voltage range of the second voltage domain. In another embodiment, the voltage range of the first voltage domain is greater than the voltage range of the second voltage domain. Further, the second and fourth supply voltages VSS1and VSS2may be equal to a ground voltage (i.e., 0 volts). However, the scope of the present disclosure is not limited to the second and fourth supply voltages VSS1and VSS2being equal to the ground voltage. In various other embodiments, one or both of the second and fourth supply voltages VSS1and VSS2may be less than the ground voltage (e.g., −1 volt), without deviating from the scope of the present disclosure. The IC100may further include a first functional circuit106, a second functional circuit108, and a level shifter110.

The first functional circuit106may be coupled with the first power supply102, and the second functional circuit108may be coupled with the second power supply104. The first and second functional circuits106and108are thus associated with the first and second voltage domains, respectively. In other words, the first and second functional circuits106and108operate in the first and second voltage domains, respectively.

The first and second functional circuits106and108include suitable circuitry configured to perform one or more operations. For example, the first functional circuit106may be configured to receive the first and second supply voltages VDD1and VSS1from the first power supply102. Similarly, the second functional circuit108may be configured to receive the third and fourth supply voltages VDD2and VSS2from the second power supply104. Based on the first and second supply voltages VDD1and VSS1, the first functional circuit106may be further configured to generate a first signal CS1having a first duty cycle. The first signal CS1is hereinafter referred to as a “first control signal CS1”. The second functional circuit108may be configured to receive a second signal CS2that is a level-shifted version of the first control signal CS1(i.e., associated with the second voltage domain). The second signal CS2is hereinafter referred to as a “second control signal CS2”. In such a scenario, the second control signal CS2has a second duty cycle.

A difference between the first duty cycle (i.e., a duty cycle of the first control signal CS1) and the second duty cycle (i.e., a duty cycle of the second control signal CS2) is less than a first tolerance limit associated with the level shifter110. In an example, the first tolerance limit is equal to 5 percent. However, the first tolerance limit may have other values in other embodiments. Based on the second control signal CS2and the third and fourth supply voltages VDD2and VSS2, the second functional circuit108may be further configured to perform a set of functional operations associated therewith. Examples of the first and second functional circuits106and108may include oscillators, analog-to-digital converters, processors, digital logic circuits, or the like.

The level shifter110may be coupled between the first functional circuit106and the second functional circuit108. Further, the level shifter110may be coupled with the second power supply104. The level shifter110may be configured to receive the first control signal CS1from the first functional circuit106and the third and fourth supply voltages VDD2and VSS2from the second power supply104. Based on the first control signal CS1and the third and fourth supply voltages VDD2and VSS2, the level shifter110may be further configured to output the second control signal CS2. The second control signal CS2is thus associated with the second voltage domain. In other words, the second control signal CS2is the level-shifted version of the first control signal CS1. In an embodiment, a voltage range of the first control signal CS1is less than a voltage range of the second control signal CS2. In another embodiment, the voltage range of the first control signal CS1is greater than the voltage range of the second control signal CS2. For the sake of ongoing discussion, it is assumed that the voltage range of the first control signal CS1is less than the voltage range of the second control signal CS2. Further, the difference between the first and second duty cycles is less than the first tolerance limit. Additionally, a logic state of the first control signal CS1is same as that of the second control signal CS2(i.e., the first and second control signals CS1and CS2are in phase with each other).

The level shifter110may be further configured to receive a third signal EB1and a fourth signal EB2. The third signal EB1is hereinafter referred to as a “first enable signal EB1” and the fourth signal EB2is hereinafter referred to as a “second enable signal EB2”. An operation of the level shifter110is controlled based on the first enable signal EB1. Further, the second enable signal EB2is an inverted version of the first enable signal EB1. When the first enable signal EB1is deactivated (e.g., is at a logic low state) and the second enable signal EB2is activated (e.g., is at a logic high state), the level shifter110is deactivated (i.e., the level shifter110is non-operational). When the first enable signal EB1is activated (e.g., is at a logic high state) and the second enable signal EB2is deactivated (e.g., is at a logic low state), the level shifter110is activated (i.e., the level shifter110is operational). When the level shifter110is operational, the second control signal CS2is the level-shifted version of the first control signal CS1. The level shifter110is explained in detail in conjunction withFIGS.2-7.

The IC100may further include an enabling circuit112and a first inverter114. The enabling circuit112may be coupled with the level shifter110. The enabling circuit112may include suitable circuitry that may be configured to perform one or more operations. For example, the enabling circuit112may be configured to generate the first enable signal EB1and provide the first enable signal EB1to the level shifter110to control the operation of the level shifter110. The first inverter114may be coupled between the enabling circuit112and the level shifter110. The first inverter114may be configured to receive the first enable signal EB1from the enabling circuit112and output the second enable signal EB2such that the second enable signal EB2is the inverted version of the first enable signal EB1. Further, the first inverter114may be configured to provide the second enable signal EB2to the level shifter110.

FIG.2illustrates a schematic circuit diagram of the level shifter110in accordance with an embodiment of the present disclosure. The level shifter110may include a control circuit202, a set of inverters204, a second inverter206, and a bias circuit208.

The control circuit202may be coupled with the second power supply104, the bias circuit208, and the first functional circuit106that is associated with the first voltage domain. The control circuit202may be configured to receive the first control signal CS1from the first functional circuit106. In other words, the first functional circuit106may be configured to provide the first control signal CS1to the control circuit202. The first control signal CS1has the first duty cycle and is associated with the first voltage domain. Further, the control circuit202may be configured to receive a bias voltage VB from the bias circuit208, and the third and fourth supply voltages VDD2and VSS2from the second power supply104. Based on the first control signal CS1, the bias voltage VB, and the third and fourth supply voltages VDD2and VSS2, the control circuit202may be further configured to output a fifth signal CS3. The fifth signal CS3is hereinafter referred to as a “third control signal CS3”.

The third control signal CS3has a third duty cycle and is an inverted version of the first control signal CS1. Further, a difference between the first duty cycle and an inverse of the third duty cycle (i.e., a duty cycle of the third control signal CS3) is less than a second tolerance limit associated with the level shifter110. In an example, the second tolerance limit is equal to 4.95 percent. However, the second tolerance limit may have other values in other embodiments. Additionally, a voltage range of the third control signal CS3is different than the voltage range of the first control signal CS1. In an embodiment, the voltage range of the first control signal CS1is less than the voltage range of the third control signal CS3. In another embodiment, the voltage range of the first control signal CS1is greater than the voltage range of the third control signal CS3. For the sake of ongoing discussion, it is assumed that the voltage range of the first control signal CS1is less than the voltage range of the third control signal CS3. Thus, the third control signal CS3is the inverted level-shifted version of the first control signal CS1.

The control circuit202may include a first transistor210, a second transistor212, a third transistor214, and a fourth transistor216. The first transistor210has a first terminal, a second terminal, and a third terminal. The first terminal of the first transistor210may be coupled with the second power supply104and the second terminal of the first transistor210may be coupled with the bias circuit208. The first terminal of the first transistor210may be configured to receive the third supply voltage VDD2from the second power supply104. Further, the second terminal of the first transistor210may be configured to receive the bias voltage VB from the bias circuit208. In an embodiment, the first transistor210is a p-channel metal-oxide semiconductor (PMOS) transistor, and the first through third terminals of the first transistor210correspond to source, gate, and drain terminals, respectively.

The second transistor212has a first terminal, a second terminal, and a third terminal. The first terminal of the second transistor212may be coupled with the third terminal of the first transistor210. The second terminal of the second transistor212may be coupled with the first functional circuit106. The second terminal of the second transistor212may be configured to receive the first control signal CS1from the first functional circuit106. Further, the third terminal of the second transistor212may be configured to output the third control signal CS3. In an embodiment, the second transistor212is a PMOS transistor, and the first through third terminals of the second transistor212correspond to source, gate, and drain terminals, respectively.

The first transistor210is thus deactivated when the bias voltage VB is equal to the third supply voltage VDD2. Conversely, the first transistor210is activated when the difference between the third supply voltage VDD2and the bias voltage VB is greater than or equal to a first threshold value. In an example, the first threshold value is equal to a threshold voltage of the first transistor210. However, the first threshold value may have other values in other embodiments. Further, the second transistor212is activated when the first control signal CS1is deactivated (e.g., is at a logic low state). The second transistor212remains activated when the first control signal CS1is activated (e.g., is at a logic high state) until a difference between a voltage level of the first control signal CS1and a drain voltage (i.e., a voltage level at the third terminal) of the first transistor210is greater than or equal to a second threshold value. Further, the second transistor212is deactivated when the difference between the voltage level of the first control signal CS1and the drain voltage of the first transistor210is less than the second threshold value. In an example, the second threshold value is equal to a threshold voltage of the second transistor212. However, the second threshold value may have other values in other embodiments.

The third transistor214has a first terminal, a second terminal, and a third terminal. The second terminal of the third transistor214may be coupled with the second terminal of the first transistor210and the bias circuit208. Thus, the second terminal of the third transistor214may be configured to receive the bias voltage VB. Further, the third terminal of the third transistor214may be coupled with the third terminal of the second transistor212to output the third control signal CS3. In an embodiment, the third transistor214is an n-channel metal-oxide semiconductor (NMOS) transistor, and the first through third terminals of the third transistor214correspond to source, gate, and drain terminals, respectively.

The fourth transistor216has a first terminal, a second terminal, and a third terminal. The first terminal of the fourth transistor216may be coupled with the second power supply104. The first terminal of the fourth transistor216may be configured to receive the fourth supply voltage VSS2. The second terminal of the fourth transistor216may be coupled with the second terminal of the second transistor212and the first functional circuit106. Thus, the second terminal of the fourth transistor216may be configured to receive the first control signal CS1. Further, the third terminal of the fourth transistor216may be coupled with the first terminal of the third transistor214. In an embodiment, the fourth transistor216is an NMOS transistor, and the first through third terminals of the fourth transistor216correspond to source, gate, and drain terminals, respectively.

The third transistor214is thus activated when a difference between the bias voltage VB and the fourth supply voltage VSS2is greater than or equal to a third threshold value. Conversely, the third transistor214is deactivated when the difference between the bias voltage VB and the fourth supply voltage VSS2is less than the third threshold value. In an example, the third threshold value is equal to a sum of a threshold voltage of the third transistor214and a voltage drop across the fourth transistor216. However, the third threshold value may have other values in other embodiments. Further, the fourth transistor216is activated when the first control signal CS1is activated (e.g., is at a logic high state). Conversely, the fourth transistor216is deactivated when the first control signal CS1is deactivated (e.g., is at a logic low state).

Thus, when the bias voltage VB is equal to the third supply voltage VDD2, the first transistor210is deactivated, and when the bias voltage VB is equal to the fourth supply voltage VSS2, the third transistor214is deactivated. The bias voltage VB thus controls the first and third transistors210and214. When the bias voltage VB is at such a voltage level that a difference between the third supply voltage VDD2and the bias voltage VB is greater than or equal to the first threshold value and a difference between the bias voltage VB and the fourth supply voltage VSS2is greater than or equal to the third threshold value, both the first and third transistors210and214are activated. Upon activation, the drive strengths of the first and third transistors210and214are controlled based on the bias voltage VB. The bias voltage VB thus controls a current associated with the control circuit202(i.e., a current passing through the first through fourth transistors210-218). In other words, the control circuit202acts as a current-controlled inverter when the first and third transistors210and214are activated.

The scope of the present disclosure is not limited to the control circuit202as illustrated inFIG.2(i.e., including the first through fourth transistors210-216arranged as illustrated inFIG.2). In various other embodiments, more than or less than four transistors arranged in various other configurations may be implemented as the control circuit202, without deviating from the scope of the present disclosure.

The set of inverters204may be coupled with the control circuit202(i.e., the third terminals of the second and third transistors212and214). The set of inverters204may be configured to receive the third control signal CS3from the control circuit202(i.e., the third terminals of the second and third transistors212and214), and output a sixth signal CS4. The sixth signal CS4is hereinafter referred to as a “fourth control signal CS4”. As shown inFIG.2, the set of inverters204may include a third inverter218, a fourth inverter220, a fifth inverter222, and a sixth inverter224(i.e., an even number of inverters) that may be coupled in series with each other. Thus, the fourth control signal CS4has a same logic state as that of the third control signal CS3. Further, the fourth control signal CS4has a fourth duty cycle. In other words, the fourth control signal CS4is derived from the third control signal CS3.

Although it is described that the set of inverters204may include an even number of inverters that may be coupled in series with each other, the scope of the present disclosure is not limited to it. In an alternate embodiment, the set of inverters204may include an odd number of inverters that may be coupled in series with each other, without deviating from the scope of the present disclosure.

A difference between the fourth duty cycle (i.e., a duty cycle of the fourth control signal CS4) and the third duty cycle is less than a third tolerance limit associated with the level shifter110. In an example, the third tolerance limit is equal to 0.04 percent. However, the third tolerance limit may have other values in other embodiments. Additionally, a voltage range of the fourth control signal CS4is equal to the voltage range of the third control signal CS3.

Although not illustrated inFIG.2. the third, fourth, fifth, and sixth inverters218,220,222, and224may further be configured to receive the third and fourth supply voltages VDD2and VSS2at supply terminals thereof for performing the corresponding inverting operations.

The second inverter206may be coupled with the set of inverters204(i.e., the sixth inverter224) and the second functional circuit108that is associated with the second voltage domain. The second inverter206may be configured to receive the fourth control signal CS4from the set of inverters204(i.e., the sixth inverter224), and output the second control signal CS2. The second control signal CS2is an inverted version of the fourth control signal CS4and has a same voltage range as that of the fourth control signal CS4. A difference between the second duty cycle and an inverse of the fourth duty cycle is less than a fourth tolerance limit associated with the level shifter110. In an example, the fourth tolerance limit is equal to 0.01 percent. However, the fourth tolerance limit may have other values in other embodiments. The second inverter206may be further configured to provide the second control signal CS2to the second functional circuit108.

Although not illustrated inFIG.2, the second inverter206may be further configured to receive the third and fourth supply voltages VDD2and VSS2at supply terminals thereof for performing the corresponding inverting operation.

The second control signal CS2is an inverted version of the fourth control signal CS4and has a same voltage range as that of the fourth control signal CS4. The fourth control signal CS4has a same logic state and a same voltage range as that of the third control signal CS3. Further, the third control signal CS3is the inverted level-shifted version of the first control signal CS1. Hence, the second control signal CS2has a same logic state as that of the first control signal CS1and is the level-shifted version of the first control signal CS1.

The difference between the second duty cycle and the inverse of the fourth duty cycle is less than the fourth tolerance limit. The difference between the third and fourth duty cycles is less than the third tolerance limit. In other words, the difference between the inverse of the third duty cycle and the inverse of the fourth duty cycle is less than the third tolerance limit. Further, the difference between the first duty cycle and the inverse of the third duty cycle is less than the second tolerance limit. Thus, the difference between the first duty cycle and the second duty cycle is less than the first tolerance limit, where the first tolerance limit is equal to a sum of the second, third, and fourth tolerance limits (e.g., 4.95 percent+0.04 percent+0.01 percent=5 percent).

AlthoughFIG.2illustrates that the level shifter110may include the second inverter206for outputting the second control signal CS2that has a same logic state as that of the first control signal CS1, the scope of the present disclosure is not limited to it. In various other embodiments, the level shifter110may include an even number of inverters instead of the second inverter206to output the second control signal CS2such that the second control signal CS2is the inverted version of the first control signal CS1, without deviating from the scope of the present disclosure. Alternatively, the second inverter206may be omitted from the level shifter110and the fourth control signal CS4outputted by the set of inverters204may be provided to the second functional circuit108, without deviating from the scope of the present disclosure.

The bias circuit208may be coupled with the second power supply104, the enabling circuit112, the first inverter114, the set of inverters204(i.e., the sixth inverter224), and the control circuit202(i.e., the second terminals of the first and third transistors210and214). The bias circuit208may be configured to receive the third supply voltage VDD2and the fourth control signal CS4from the second power supply104and the set of inverters204(i.e., the sixth inverter224), respectively. Further, the bias circuit208may be configured to receive the first and second enable signals EB1and EB2from the enabling circuit112and the first inverter114, respectively. Based on the first and second enable signals EB1and EB2, the third supply voltage VDD2, and the fourth control signal CS4, the bias circuit208may be further configured to generate the bias voltage VB. The bias voltage VB is indicative of the fourth duty cycle of the fourth control signal CS4, and in turn, of the third duty cycle of the third control signal CS3. Further, the bias circuit208may be configured to provide the bias voltage VB to the control circuit202(i.e., the second terminals of the first and third transistors210and214). The bias voltage VB controls the operation of the control circuit202. In other words, the third duty cycle of the third control signal CS3is controlled based on the bias voltage VB such that the difference between the first duty cycle and the inverse of the third duty cycle is less than the second tolerance limit.

The bias circuit208may include a switch226, a resistor228, and a capacitor230. As shown inFIG.2, the switch226corresponds to a transmission gate. However, various other circuits (e.g., a transistor) may be implemented as the switch226in other embodiments. The switch226has a first data terminal that may be coupled with the resistor228and a second data terminal that may be coupled with the capacitor230. In other words, the switch226may be coupled between the resistor228and the capacitor230. Further, the switch226has a first control terminal that may be coupled with the enabling circuit112and a second control terminal that may be coupled with the first inverter114. The first and second control terminals of the switch226may be configured to receive the first and second enable signals EB1and EB2from the enabling circuit112and the first inverter114, respectively. In an embodiment, the switch226is deactivated (i.e., open) when the first enable signal EB1is deactivated (e.g., is at a logic low state). Conversely, the switch226is activated (i.e., closed) when the first enable signal EB1is activated (e.g., is at a logic high state). In other words, the switch226is activated and deactivated based on the activation and deactivation of the first enable signal EB1, respectively.

The resistor228has a first terminal that may be coupled with the set of inverters204(i.e., the sixth inverter224). The first terminal of the resistor228may be configured to receive the fourth control signal CS4. The resistor228further has a second terminal that may be coupled with the first data terminal of the switch226. The capacitor230has a first terminal that may be coupled with the second power supply104. The first terminal of the capacitor230may be configured to receive the third supply voltage VDD2from the second power supply104. The capacitor230further has a second terminal that may be coupled with the control circuit202(i.e., the second terminals of the first and third transistors210and214) and the second data terminal of the switch226. When the switch226is activated, the resistor228and the capacitor230may be configured to integrate the fourth control signal CS4and generate the bias voltage VB. In other words, when the switch226is activated, the resistor228and the capacitor230act as an integrator232. The integrator232may thus include the resistor228and the capacitor230. Further, the integrator232may be configured to integrate the fourth control signal CS4, when the switch226is activated, based on the third supply voltage VDD2and generate the bias voltage VB. The bias voltage VB is an integrated version of the fourth control signal CS4. In other words, the bias voltage VB is a product of the third supply voltage VDD2and the fourth duty cycle of the fourth control signal CS4. The bias circuit208further provides the bias voltage VB to the control circuit202(i.e., the second terminals of the first and third transistors210and214) by way of the second terminal of the capacitor230.

It will be apparent to a person skilled in the art that the scope of the disclosure is not limited to the integrator232being implemented by way of the resistor228and the capacitor230as illustrated inFIG.2. In various other embodiments, the integrator232may be implemented by way of various other circuits, without deviating from the scope of the present disclosure.

AlthoughFIG.2illustrates that the first terminal of the capacitor230receives the third supply voltage VDD2from the second power supply104, the scope of the present disclosure is not limited to it. In various other embodiments, the first terminal of the capacitor230may alternatively receive the fourth supply voltage VSS2from the second power supply104, without deviating from the scope of the present disclosure. Further, it will be apparent to a person skilled in the art that the scope of the present disclosure is not limited to the switch226being coupled between the capacitor230and the resistor228. In an alternate embodiment, the switch226may be coupled between the resistor228and the set of inverters204, without deviating from the scope of the present disclosure. In such a scenario, the operations of the bias circuit208remain same as described above.

The level shifter110may further include a fifth transistor234that has a first terminal, a second terminal, and a third terminal. The first terminal of the fifth transistor234may be coupled with the second power supply104and the second terminal of the fifth transistor234may be coupled with the enabling circuit112. The first terminal of the fifth transistor234may be configured to receive the third supply voltage VDD2from the second power supply104. The second terminal of the fifth transistor234may be configured to receive the first enable signal EB1from the enabling circuit112. Further, the third terminal of the fifth transistor234may be coupled with the control circuit202(i.e., the second terminals of the first and third transistors210and214) and the bias circuit208(i.e., the second terminal of the capacitor230). In an embodiment, the fifth transistor234is a PMOS transistor, and the first through third terminals of the fifth transistor234correspond to source, gate, and drain terminals, respectively. The fifth transistor234is thus deactivated and activated when the first enable signal EB1is activated (e.g., is at a logic high state) and deactivated (e.g., is at a logic low state), respectively. In other words, the fifth transistor234is activated and deactivated based on the deactivation and activation of the first enable signal EB1, respectively. When the fifth transistor234is activated, the bias voltage VB is equal to the third supply voltage VDD2.

The level shifter110may further include a sixth transistor236that has a first terminal, a second terminal, and a third terminal. The first terminal of the sixth transistor236may be coupled with the second power supply104and the second terminal of the sixth transistor236may be coupled with the first inverter114. Thus, the first terminal of the sixth transistor236may be configured to receive the fourth supply voltage VSS2from the second power supply104, and the second terminal of the sixth transistor236may be configured to receive the second enable signal EB2from the first inverter114. Further, the third terminal of the sixth transistor236may be coupled with the third terminal of the second transistor212. The third terminal of the sixth transistor236may be configured to receive the third control signal CS3from the third terminal of the second transistor212. In an embodiment, the sixth transistor236is an NMOS transistor, and the first through third terminals of the sixth transistor236correspond to source, gate, and drain terminals, respectively. Thus, when the second enable signal EB2is deactivated (e.g., is at a logic low state), the sixth transistor236is deactivated. Further, when the second enable signal EB2is activated (e.g., is at a logic high state), the sixth transistor236is activated. In other words, the sixth transistor236is activated and deactivated based on the activation and deactivation of the second enable signal EB2, respectively. When the sixth transistor236is activated, the third control signal CS3is pulled down to the fourth supply voltage VSS2.

In operation, when the first enable signal EB1is deactivated (e.g., is at a logic low state), the fifth and sixth transistors234and236are activated and the switch226is deactivated. Thus, the third control signal CS3is pulled down to the fourth supply voltage VSS2and the level shifter110is deactivated. In an embodiment, when the level shifter110is deactivated, the second functional circuit108discards the received second control signal CS2(i.e., the second control signal CS2is not utilized for performing the set of functional operations). Further, as the fifth transistor234is activated, the bias voltage VB is equal to the third supply voltage VDD2and the capacitor230is charged to the third supply voltage VDD2. Hence, the first transistor210is deactivated and the third transistor214is activated.

When the first enable signal EB1transitions from the deactivated state to an activated state (e.g., from a logic low state to a logic high state), the fifth and sixth transistors234and236are deactivated and the switch226is activated. The bias voltage VB remains equal to the third supply voltage VDD2due to the charged capacitor230. As the bias voltage VB is equal to the third supply voltage VDD2, the first transistor210remains deactivated and the third transistor214remains activated. In such a scenario, when the first control signal CS1is both deactivated (e.g., is at a logic low state) and activated (e.g., is at a logic high state), the third control signal CS3remains deactivated (e.g., remains at a logic low state). Further, the set of inverters204output the fourth control signal CS4having a same logic state as that of the third control signal CS3. Thus, the fourth control signal CS4is deactivated (e.g., is at a logic low state).

When the fourth control signal CS4is deactivated, the bias voltage VB drains by way of the switch226, the resistor228, and the sixth inverter224. As a result, the bias voltage VB reduces, thereby increasing a magnitude of a gate-to-source voltage of the first transistor210(i.e., increasing the drive strength of the first transistor210). The bias voltage VB reduces with each cycle associated with the first control signal CS1. The first transistor210is thus activated when the difference between the bias voltage VB and the third supply voltage VDD2is equal to the first threshold value (e.g., the threshold voltage of the first transistor210). The third transistor214remains activated at such a time instance.

When the first and third transistors210and214are activated, the control circuit202acts as a current-controlled inverter such that the current associated with the control circuit202is controlled based on the bias voltage VB. When the control circuit202acts as the current-controlled inverter, the control circuit202outputs the third control signal CS3as the inverted level-shifted version of the first control signal CS1. The bias voltage VB further reduces (i.e., the difference between the bias voltage VB and the third supply voltage VDD2is greater than the first threshold value) before settling to within a voltage range that ensures the difference between the first duty cycle and the inverse of the third duty cycle is less than the second tolerance limit. In other words, the bias voltage VB and a negative feedback configuration of the control circuit202, the set of inverters204, and the bias circuit208thus ensure that the difference between the first duty cycle and the second duty cycle is less than the first tolerance limit. In an example, the first duty cycle and the second duty cycle are equal. Further, the second inverter206outputs and provides the second control signal CS2to the second functional circuit108. In such a scenario, the third duty cycle, and in turn, the second duty cycle, is controlled by way of the bias voltage VB.

The negative feedback configuration of the control circuit202, the set of inverters204, and the bias circuit208further track process-voltage-temperature (PVT) variations associated with the IC100and the variations in the first control signal CS1. The variations in the first control signal CS1may include variations in a frequency of the first control signal CS1, the first duty cycle, or the like.

The bias voltage VB is modified based on the PVT variations and the variations in the first control signal CS1. For example, if the first duty cycle increases, the third duty cycle decreases, thereby leading to a decrease in the bias voltage VB. As a result, the drive strength of the first transistor210increases and the drive strength of the third transistor214decreases which in turn lead to an increase in the third duty cycle. The afore-mentioned operations continue for various cycles of the first control signal CS1before the bias voltage VB settles to within a voltage range that ensures the difference between the first duty cycle and the inverse of the third duty cycle is less than the second tolerance limit. Conversely, if the first duty cycle decreases, the third duty cycle increases, thereby leading to an increase in the bias voltage VB. As a result, the drive strength of the first transistor210decreases and the drive strength of the third transistor214increases which in turn lead to a decrease in the third duty cycle. The afore-mentioned operations continue for various cycles of the first control signal CS1before the bias voltage VB settles to within a voltage range that ensures the difference between the first duty cycle and the inverse of the third duty cycle is less than the second tolerance limit. The bias voltage VB may similarly be modified based on the PVT variations in the first control signal CS1. This ensures that the PVT variations associated with the IC100and the variations in the first control signal CS1do not distort the third duty cycle of the third control signal CS3, and in turn, the second duty cycle of the second control signal CS2.

The supply noise associated with the second power supply104is regulated by way of the capacitor230. For example, when the third supply voltage VDD2increases, the capacitor230couples the second terminal of the first transistor210to the first terminal of the first transistor210, thereby ensuring that the drive strength of the first transistor210remains unchanged. Thus, the capacitor230ensures that the supply noise associated with the second power supply104does not distort the second duty cycle of the second control signal CS2.

The bias voltage VB ensures that a drive strength of the first transistor210is less than that when the second terminal of the first transistor210is at the fourth supply voltage VSS2. Further, when the first control signal CS1is activated (e.g., is at a logic high state), the third terminal (i.e., the drain terminal) of the first transistor210is at such a voltage level that the drive strength of the first transistor210further decreases, thereby leading to the deactivation of the first transistor210. Additionally, the fourth transistor216is deactivated when the first control signal CS1is deactivated (e.g., is at a logic low state). Thus, the creation of a direct current path between two terminals of the second power supply104that provide the third and fourth supply voltages VDD2and VSS2, respectively, is prevented.

FIG.3represents a timing diagram300that illustrates an operation of the level shifter110in accordance with an embodiment of the present disclosure. The level shifter110receives the first and second enable signals EB1and EB2from the enabling circuit112and the first inverter114, respectively. Further, the level shifter110receives the first control signal CS1and the third supply voltage VDD2from the first functional circuit106and the second power supply104, respectively.

During a time period T0-T1, the first enable signal EB1is at a logic low state. As the first enable signal EB1is at a logic low state, the fifth and sixth transistors234and236are activated and the switch226is deactivated. Thus, the bias voltage VB is equal to the third supply voltage VDD2, and the third control signal CS3is at a logic low state (i.e., is pulled down to the fourth supply voltage VSS2). The first control signal CS1toggles between a logic low state and a logic high state during the time period T0-T1. Alternatively, the first control signal CS1may gradually increase during the time period T0-T1.

At time instance T1, the first enable signal EB1transitions from a logic low state to a logic high state. Thus, the fifth and sixth transistors234and236are deactivated and the switch226is activated. At the time instance T1, the bias voltage VB remains equal to the third supply voltage VDD2. Hence, the first transistor210remains deactivated and the third control signal CS3remains at a logic low state. The first control signal CS1continues toggling, and transitions from a logic low state to a logic high state at the time instance T1.

During a time period T1-T2, the first enable signal EB1remains at a logic high state. Thus, the fifth and sixth transistors234and236remain deactivated and the switch226remains activated. The bias voltage VB reduces as the bias voltage VB drains by way of the switch226, the resistor228, and the sixth inverter224. During the time period T1-T2, the first transistor210is partially activated (i.e., a leakage current is outputted by the first transistor210). Hence, the third control signal CS3experiences a spike during the time period T1-T2.

At time instance T2, the first control signal CS1transitions from a logic high state to a logic low state. Further, the bias voltage VB reduces such that the difference between the bias voltage VB and the third supply voltage VDD2is equal to the first threshold value. Thus, the first transistor210is activated. Hence, the third control signal CS3is the inverted version of the first control signal CS1. In other words, the third control signal CS3transitions from a logic low state to a logic high state. Additionally, the third control signal CS3is the level-shifted version of the first control signal CS1. For example, as shown inFIG.3, the voltage range of the third control signal CS3is greater than the voltage range of the first control signal CS1. Further, the first enable signal EB1remains at a logic high state.

During a time period T2-T3, the first enable signal EB1remains at a logic high state. Thus, the fifth and sixth transistors234and236remain deactivated and the switch226remains activated. The bias voltage VB further reduces with each cycle associated with the first control signal CS1before settling to within a voltage range that ensures the difference between the first duty cycle and the second duty cycle is less than the first tolerance limit. Further, the first and third control signals CS1and CS3toggle between a logic low state and a logic high state such that the third control signal CS3is the inverted version of the first control signal CS1.

FIG.4illustrates a schematic circuit diagram of the level shifter110in accordance with another embodiment of the present disclosure. The level shifter110may include the control circuit202, the set of inverters204, the second inverter206, the bias circuit208, the fifth transistor234, and the sixth transistor236. The bias circuit208may include the switch226, the resistor228, and the capacitor230.

The structure of the control circuit202, the set of inverters204, the second inverter206, the fifth transistor234, and the sixth transistor236remain same as described inFIG.2. The difference between the level shifter ofFIG.2and the level shifter ofFIG.4is the structure and the functionality of the bias circuit208. In the bias circuit208ofFIG.4, the switch226may be coupled between the control circuit202and the capacitor230. The change in the structure of the bias circuit208further leads to a change in the operation of the level shifter110illustrated inFIG.4.

The resistor228has a first terminal that may be coupled with the set of inverters204(i.e., the sixth inverter224). The first terminal of the resistor228may be configured to receive the fourth control signal CS4from the set of inverters204(i.e., the sixth inverter224). The resistor228further has a second terminal that may be coupled with the first data terminal of the switch226. The capacitor230has a first terminal that may be coupled with the second power supply104. The first terminal of the capacitor230may be configured to receive the third supply voltage VDD2from the second power supply104. The capacitor230further has a second terminal that may be coupled with the second terminal of the resistor228and the first data terminal of the switch226. The resistor228and the capacitor230may be configured to integrate the fourth control signal CS4and generate the bias voltage VB. In other words, the resistor228and the capacitor230act as the integrator232. Thus, the integrator232may include the resistor228and the capacitor230. Further, the integrator232may be configured to integrate the fourth control signal CS4based on the third supply voltage VDD2and generate the bias voltage VB. The bias voltage VB is the integrated version of the fourth control signal CS4. In other words, the bias voltage VB is a product of the third supply voltage VDD2and the fourth duty cycle of the fourth control signal CS4.

It will be apparent to a person skilled in the art that the scope of the disclosure is not limited to the integrator232being implemented by way of the resistor228and the capacitor230as illustrated inFIG.4. In various other embodiments, the integrator232may be implemented by way of various other circuits, without deviating from the scope of the present disclosure.

AlthoughFIG.4illustrates that the first terminal of the capacitor230receives the third supply voltage VDD2from the second power supply104, the scope of the present disclosure is not limited to it. In various other embodiments, the first terminal of the capacitor230may alternatively receive the fourth supply voltage VSS2from the second power supply104, without deviating from the scope of the present disclosure.

As shown inFIG.4, the switch226corresponds to a transmission gate. However, various other circuits (e.g., a transistor) may be implemented as the switch226in other embodiments. The switch226has a first data terminal that may be coupled with the second terminals of the resistor228and the capacitor230. The first data terminal of the switch226may be configured to receive the bias voltage VB from the second terminals of the resistor228and the capacitor230. The switch226further has a second data terminal that may be coupled with the control circuit202(i.e., the second terminals of the first and third transistors210and214). The switch226may thus be coupled between the integrator232(i.e., the capacitor230) and the control circuit202. Further, the switch226has a first control terminal that may be coupled with the enabling circuit112and a second control terminal that may be coupled with the first inverter114. The first and second control terminals of the switch226may be configured to receive the first and second enable signals EB1and EB2from the enabling circuit112and the first inverter114, respectively. When the switch226is activated, the second data terminal of the switch226may be configured to provide the bias voltage VB to the control circuit202(i.e., the second terminals of the first and third transistors210and214). In other words, the bias circuit208provides the bias voltage VB to the control circuit202(i.e., the second terminals of the first and third transistors210and214) by way of the second data terminal of the switch226.

In operation, when the first enable signal EB1is deactivated (e.g., is at a logic low state), the fifth and sixth transistors234and236are activated and the switch226is deactivated. Thus, the third control signal CS3is pulled down to the fourth supply voltage VSS2and the level shifter110is deactivated. In an embodiment, when the level shifter110is deactivated, the second functional circuit108discards the received second control signal CS2(i.e., the second control signal CS2is not utilized for performing the set of functional operations). Further, as the fifth transistor234is activated, the bias voltage VB is equal to the third supply voltage VDD2. Hence, the first transistor210is deactivated and the third transistor214is activated. Further, as the switch226is deactivated, the capacitor230is not charged to the third supply voltage VDD2.

When the first enable signal EB1transitions from the deactivated state to the activated state (e.g., from a logic low state to a logic high state), the fifth and sixth transistors234and236are deactivated and the switch226is activated. When the switch226is activated, the bias voltage VB is pulled down to the fourth supply voltage VSS2by way of the switch226, the resistor228, and the sixth inverter224. Thus, the first transistor210is activated and the third transistor214is deactivated. As the bias voltage VB is equal to the fourth supply voltage VSS2, the drain voltage of the first transistor210is equal to the third supply voltage VDD2. For the sake of ongoing discussion, it is assumed that the voltage range of the first control signal CS1is significantly less than that of the second voltage domain. Thus, a difference between the voltage level of the first control signal CS1and the drain voltage of the first transistor210is greater than the second threshold value. Hence, the third control signal CS3is activated (e.g., is at a logic high state) even when the first control signal CS1is activated (e.g., is at a logic high state). The third control signal CS3is also activated when the first control signal CS1is deactivated (e.g., is at a logic low state). In other words, the second transistor212is activated for both the activation and deactivation of the first control signal CS1. Further, the set of inverters204output the fourth control signal CS4having a same logic state as that of the third control signal CS3. Thus, the fourth control signal CS4is activated (e.g., is at a logic high state).

As the fourth control signal CS4remains activated (i.e., as the fifth transistor234remains deactivated), the bias voltage VB increases, thereby increasing the magnitude of the gate-to-source voltage of the third transistor214(i.e., increasing the drive strength of the third transistor214). The bias voltage VB increases with each cycle associated with the first control signal CS1. The third transistor214is thus activated when the difference between the bias voltage VB and the fourth supply voltage VSS2is equal to the third threshold value. The first transistor210remains activated at such a time instance.

When the first and third transistors210and214are activated, the control circuit202acts as a current-controlled inverter such that the current associated with the control circuit202is controlled based on the bias voltage VB. When the control circuit202acts as the current-controlled inverter, the control circuit202outputs the third control signal CS3as the inverted level-shifted version of the first control signal CS1. The bias voltage VB further increases (i.e., the difference between the bias voltage VB and the fourth supply voltage VSS2is greater than the third threshold value) before settling to within a voltage range that ensures the difference between the first duty cycle and the inverse of the third duty cycle is less than the second tolerance limit.

FIG.5represents a timing diagram500that illustrates the operation of the level shifter110in accordance with another embodiment of the present disclosure. The level shifter110receives the first and second enable signals EB1and EB2from the enabling circuit112and the first inverter114, respectively. Further, the level shifter110receives the first control signal CS1from the first functional circuit106and the third and fourth supply voltages VDD2and VSS2from the second power supply104.

During a time period T0-T1, the first enable signal EB1is at a logic low state. As the first enable signal EB1is at a logic low state, the fifth and sixth transistors234and236are activated and the switch226is deactivated. Thus, the bias voltage VB is equal to the third supply voltage VDD2, and the third control signal CS3is at a logic low state (i.e., is pulled down to the fourth supply voltage VSS2). The first control signal CS1toggles between a logic low state and a logic high state during the time period T0-T1. Alternatively, the first control signal CS1may gradually increase during the time period T0-T1.

At time instance T1, the first enable signal EB1transitions from a logic low state to a logic high state. Thus, the fifth and sixth transistors234and236are deactivated and the switch226is activated. At the time instance T1, the bias voltage VB is pulled down to the fourth supply voltage VSS2by way of the switch226, the resistor228, and the sixth inverter224. Hence, the first transistor210is activated and the third transistor214is deactivated. As the first transistor210is activated, the first terminal (i.e., the source terminal) of the second transistor212is at a voltage level that is equal to the third supply voltage VDD2. For the sake of ongoing discussion, it is assumed that a voltage range of the first control signal CS1is significantly less than that of the second domain. Thus, the second transistor212is activated for both the activation and deactivation of the first control signal CS1. Hence, the third control signal CS3transitions from a logic low state to a logic high state. The first control signal CS1continues toggling, and transitions from a logic high state to a low state at the time instance T1.

During a time period T1-T2, the first enable signal EB1remains at a logic high state. Thus, the fifth and sixth transistors234and236remain deactivated and the switch226remains activated. The bias voltage VB increases as the capacitor230is charged by way of the resistor228and the sixth inverter224. During the time period T1-T2, the third transistor214is partially activated (i.e., a leakage current is outputted by the third transistor214). Hence, the third control signal CS3experiences a spike during the time period T1-T2.

At time instance T2, the first control signal CS1transitions from a logic low state to a logic high state. Further, the bias voltage VB increases such that the difference between the bias voltage VB and the fourth supply voltage VSS2is equal to the third threshold value. Thus, the third transistor214is activated. Hence, the third control signal CS3is the inverted version of the first control signal CS1. In other words, the third control signal CS3transitions from a logic high state to a logic low state. Additionally, the third control signal CS3is the level-shifted version of the first control signal CS1. For example, as shown inFIG.5, the voltage range of the third control signal CS3is greater than the voltage range of the first control signal CS1. Further, the first enable signal EB1remains at a logic high state.

During a time period T2-T3, the first enable signal EB1remains at a logic high state. Thus, the fifth and sixth transistors234and236remain deactivated and the switch226remains activated. The bias voltage VB further increases (i.e., the third transistor214remains activated) with each cycle associated with the first control signal CS1before settling to within a voltage range that ensures the difference between the first duty cycle and the second duty cycle is less than the first tolerance limit. Further, the first and third control signals CS1and CS3toggle between a logic low state and a logic high state such that the third control signal CS3is the inverted version of the first control signal CS1.

FIGS.6and7, collectively, represent a flowchart600that illustrates a level shifting method in accordance with an embodiment of the present disclosure. Referring now toFIG.6, at step602, the control circuit202receives the first control signal CS1from the first functional circuit106, the bias voltage VB from the bias circuit208, and the third and fourth supply voltages VDD2and VSS2from the second power supply104. At step604, the control circuit202outputs the third control signal CS3associated with the second voltage domain, and provides the third control signal CS3to set of inverters204. The third control signal CS3is outputted based on the first control signal CS1, the bias voltage VB, and the third and fourth supply voltages VDD2and VSS2. The third control signal CS3is the inverted level-shifted version of the first control signal CS1. Further, a difference between the first duty cycle and the inverse of the third duty cycle is less than the second tolerance limit. At step606, the set of inverters204outputs and provides, based on the third control signal CS3, the fourth control signal CS4to the bias circuit208and the second inverter206. The fourth control signal CS4has a same voltage range and a same logic state as that of the third control signal CS3. Further, a difference between the third duty cycle and the fourth duty cycle is less than the third tolerance limit.

At step608, the second inverter206outputs and provides, based on the fourth control signal CS4, the second control signal CS2to the second functional circuit108. The second control signal CS2is an inverted version of the fourth control signal CS4and has a same voltage range as that of the fourth control signal CS4. Further, a difference between the second duty cycle and the inverse of the fourth duty cycle is less than the fourth tolerance limit. Thus, the second control signal CS2is a level-shifted version of the first control signal CS1and has a same logic state as that of the first control signal CS1. Further, a difference between the first and second duty cycles is less than the first tolerance limit. At step610, the bias circuit208generates the bias voltage VB.

Referring now toFIG.7, at step610a, the switch226receives the first enable signal EB1. At step610b, the integrator232(i.e., the capacitor230and the resistor228) receives the third supply voltage VDD2and the fourth control signal CS4. At step610c, the integrator232integrates the fourth control signal CS4to generate the bias voltage VB. The bias voltage VB is an integrated version of the fourth control signal CS4.

Referring back toFIG.6, at step612, the bias circuit208provides the bias voltage VB to the control circuit202. At step614, it is determined whether the difference between the first and second duty cycles is less than the first tolerance limit. If at step614, it is determined that the difference between the first and second duty cycles is greater than or equal to the first tolerance limit, steps604-614are repeated.

Thus, the level shifter110translates the first control signal CS1that is associated with the first voltage domain to the second control signal CS2that is associated with the second voltage domain. In the level shifter110of the present disclosure, the control circuit202is biased based on the bias voltage VB such that the difference between the first duty cycle of the first control signal CS1and the second duty cycle of the second control signal CS2is less than the first tolerance limit. In other words, duty cycle distortion of the second control signal CS2is reduced.

A conventional level shifter includes a bias circuit having a diode-connected transistor that is coupled with a power supply and another transistor that is coupled between the diode-connected transistor and a ground terminal for reducing duty cycle distortion. The utilization of the diode-connected transistor results in a direct current path between the power supply and the ground terminal when the other transistor is activated. As a result, a current in the conventional level shifter significantly increases, thereby increasing a power consumed by the conventional level shifter.

In the level shifter110of the present disclosure, the bias voltage VB controls the first and third transistors210and214such that when the bias voltage VB is equal to the third supply voltage VDD2, the first transistor210is deactivated, and when the bias voltage VB is equal to the fourth supply voltage VSS2, the third transistor214is deactivated. Further, when the bias voltage VB is greater than the third and fourth supply voltages VDD2and VSS2by at least the first and third threshold values, respectively, the first transistor210is deactivated when the first control signal CS1is activated and the fourth transistor216is deactivated when the first control signal CS1is deactivated. Thus, the creation of a direct current path between the two terminals of the second power supply104that provide the third and fourth supply voltages VDD2and VSS2, respectively, is prevented in the level shifter110of the present disclosure. Hence, a current in the level shifter110of the present disclosure is significantly less than that in the conventional level shifter. Consequently, a power consumed by the level shifter110of the present disclosure is significantly less than a power consumed by the conventional level shifter. Thus, the level shifter110of the present disclosure is more efficient as compared to the conventional level shifter.

While various embodiments of the present disclosure have been illustrated and described, it will be clear that the present disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present disclosure, as described in the claims. Further, unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.