Self-synchronous FIFO memory device

A self-synchronous FIFO memory device (100) has a structure in which n self-synchronous data transmission lines (111-11n) are arrayed in parallel. An input control section (101) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a first transfer request signal, a first acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a preceding-stage section. Further, an output control section (102) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a second transfer request signal, a second acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a succeeding-stage section.

This nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No(s). 2002-231787 filed in JAPAN on Aug. 8, 2002, which is (are) herein incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates to self-synchronous FIFO (First-In First-Out) memory devices and, in particular, to a self-synchronous FIFO memory device equipped with a control circuit for transmitting an input signal or output signal of a self-synchronous signal control circuit that controls a FIFO memory device.

Logic circuits that perform pipeline data processing in synchronization with a clock are, normally, implemented as logic LSIs. These logic LSIs have been under year-by-year developments to high speed, larger scale, and further microfabrication, with elongation of wiring length and reduction in spacing between wirings, so that series resistance of wirings and parallel capacitance between other wirings have been increasing more and more.

For this reason, signal delay and waveform rounding have been becoming larger, the influence of which would vary depending on the length of wirings, i.e. interconnect lines. Unfortunately, however, it is difficult to uniformize the lengths of interconnect lines to all flip-flops arranged randomly on the overall chip, making it harder and harder to achieve the distribution of an in-phase single clock.

Avoiding this problem would involve, for example, generating a clock tree in which buffers are arranged in a multi-stage tree structure for implementing a constant delay for the overall chip, which would lead to an increase in cost. Therefore, under discussions are logic circuits having a self-synchronous pipeline that allows local synchronization between neighboring pipeline registers to be maintained and that eliminates the need for an in-phase single clock.

In this self-synchronous pipeline, when data transfer is temporarily halted at an output end of the pipeline for the reason that succeeding-stage device is in a state of being unable to receive output data from the pipeline or another reason, data transfer is forced to be halted chainedly toward an input end of the pipeline, followed by a standby state lasting until data transfer at the output end of the pipeline is enabled again.

During this process, data within the pipeline flowing normally at some intervals are brought more compact in their intervals, thus the pipeline showing an autonomous buffer capacity. However, when the case is beyond the buffer capacity, there would occur a state that data reception at the input end of the pipeline is temporarily disabled. In this case, it is desirable that a FIFO memory device be inserted into the pipeline to reinforce the buffer capacity.

FIG. 8shows an example of a FIFO memory device utilizing autonomous buffer capacity of such a self-synchronous pipeline. InFIG. 8, a FIFO memory device800includes three self-synchronous data transmission lines811,812,813, and these self-synchronous data transmission lines811,812,813include pipeline registers801,802,803, respectively. As a result of this, the FIFO memory device800is enabled to hold a maximum of three pieces of data.

Also, the three self-synchronous data transmission lines811,812,813of the FIFO memory device800include self-synchronous signal control circuits804,805,806, respectively. These three self-synchronous signal control circuits804,805,806, while handshaking each other, feed clocks to the pipeline registers801,802,803.

As shown above, the self-synchronous data transmission lines811,812,813are each made up of a set of one self-synchronous signal control circuit804,805,806and one pipeline register801,802,803which operates with a clock that the self-synchronous signal control circuit804,805,806feeds. As shown inFIG. 8, the self-synchronous data transmission lines811,812,813are connected in series, by which the FIFO memory device800is implemented.

Next,FIG. 9shows one configuration example of one of the self-synchronous signal control circuits804,805,806in the FIFO memory device800ofFIG. 8. As shown inFIG. 9, the self-synchronous signal control circuit includes a CI signal terminal901, an RO signal terminal902, a CP output terminal903, a CO output terminal904and an RI input terminal905, and further includes an RS flip-flops906,908and a four-input NAND gate907which is a logic circuit.

A transfer request signal of the preceding stage is inputted to the CI signal terminal901, and the RO signal terminal902returns to the preceding stage an acknowledge signal showing the reception of the transfer request signal from the CI signal terminal901. Also, the CP signal terminal903transmits clock pulses to the pipeline registers801to803according to the transfer request signal from the CI signal terminal901.

The CO output terminal904transfers the transfer request signal from the preceding stage to the succeeding stage. Also, to the RI signal terminal905is returned an acknowledge signal showing that the transfer request from the CO signal terminal904has been received by the succeeding stage. Further, the RS flip-flop906holds a transfer request acceptance state, while the RS flip-flop908holds a transfer request state for the succeeding stage. Further, the four-input NAND gate907maintains synchronization of the RS flip-flop906and the RS flip-flop908.

Next, a timing chart ofFIG. 10shows an example of the signal for activating a self-synchronous pipeline partly composed of the FIFO memory device800ofFIG. 8. A pulse of a transfer request signal804CI is inputted to a CI signal terminal CI of the self-synchronous signal control circuit804forming the first stage of the pipeline in the FIFO memory device800ofFIG. 8. Similarly, processing data801D is inputted to a data terminal D of the first-stage pipeline register801.

As a result, the RS flip-flop906for holding the transfer request acceptance state in the self-synchronous signal control circuit804is set, and an acknowledge signal804RO is returned to the Self-synchronous signal control circuit of the preceding-stage FIFO memory device from an RO signal terminal RO of the self-synchronous signal control circuit804. As a result of this, the transfer request signal804CI returns to the H (High) level while a signal804NAND goes L (Low) level, so that the RS flip-flop908for holding a transfer request to the succeeding stage is set and the RS flip-flop906is cleared.

Next, a clock804CP for the pipeline register801goes H level, by which data is latched to the pipeline register801and this data is outputted to a terminal Q of the pipeline register801. Also, a transfer request pulse804CO for the succeeding stage is outputted from a terminal CO of the self-synchronous signal control circuit804. This transfer request pulse804CO is inputted to the self-synchronous signal control circuit805forming the second-stage self-synchronous data transmission line812composing the pipeline ofFIG. 8. Likewise, a signal804RI, a signal805NAND, a signal805CP and a signal805CO are generated, and a signal801Q is latched by the second-stage pipeline register802and outputted to the terminal Q.

Similar operations are performed between the self-synchronous signal control circuit805and the self-synchronous signal control circuit806, by which a data signal802Q is latched by the third-stage pipeline register803and outputted from the terminal Q of the pipeline register803to the data path output.

Meanwhile, a FIFO memory device intended for insertion into a self-synchronous pipeline has to be capable of processing asynchronous two requests of data write and read in parallel and moreover capable of processing at the same speed as the other parts of the self-synchronous pipeline.

Also, in the case where data is held in this FIFO memory device, a control mechanism for spontaneously generating a data transfer request is indispensable. Further, the FIFO memory device is expected to substantially increase the physical storage capacity without increasing the delay time that is simply proportional to the depth of the pipeline. Furthermore, in order to implement an optimum FIFO memory device for pipeline processing, it is desirable that the FIFO memory device can change the storage capacity dynamically and statically.

The above FIFO memory device800of the related art, in which the self-synchronous data transmission lines811,812,813are connected to one another in cascade, is capable of processing two asynchronous requests of write and read in parallel, while the cascade-connection structure of the self-synchronous data transmission lines811-813deepens the pipeline so that the delay time would be increased in simple proportion to the depth of the pipeline.

In this connection, although intended for use other than the insertion into a self-synchronous pipeline to reinforce the buffer capacity, there has been disclosed, as a similar technique, an asynchronous FIFO memory device (Japanese Patent Laid-Open Publication 2000-11636). This asynchronous FIFO memory device is a FIFO memory device for performing data input and output asynchronously with external devices.

However, this related-art asynchronous FIFO memory device, which is placed intermediate between external write processor and read processor, is purposed to passively respond to write requests or read requests transmitted from those active processors. As a result of this, the asynchronous FIFO memory device is incapable of spontaneously generating a transfer request delay time simply proportional to the depth of the pipeline, is incapable of processing asynchronous requests of write and read in parallel while ensuring normal operations in a critical state in the case where the FIFO memory device is emptied or where there is no empty space left or other cases. Furthermore, in this related art technique, the asynchronous FIFO memory device will not execute data output until it receives an output request from an external processor, so that the FIFO memory device is incapable of spontaneously generating a data transfer request. From these and other constraints, it is difficult to insert the asynchronous FIFO memory device into a self-synchronous pipeline.

SUMMARY OF THE INVENTION

Accordingly, a feature of the present invention is to provide a self-synchronous FIFO memory device which is capable of substantially increasing the physical storage capacity without increasing the delay time and moreover capable of processing two asynchronous requests of write and read in parallel.

In order to achieve the above feature, the self-synchronous FIFO memory device of the present invention has a plurality of self-synchronous data transmission lines each composed of a self-synchronous signal control circuit and a data hold circuit. The plurality of self-synchronous data transmission lines are connected in parallel, forming a parallel structure. The FIFO memory device further has an input control section and an output control section. The input control section selects one of the self-synchronous data transmission lines contained in the parallel structure, then outputs to the selected self-synchronous data transmission line a first transfer request signal inputted from a preceding-stage section, and outputs to the preceding-stage section a first acknowledge signal outputted from the selected self-synchronous data transmission line, and further, given a state that data transfer toward the selected self-synchronous data transmission line is enabled, outputs, to the selected self-synchronous data transmission line, input data inputted from the preceding-stage section.

Also, the output control section selects one of the self-synchronous data transmission lines contained in the parallel structure and then outputs to a succeeding-stage section a second transfer request signal outputted from the selected self-synchronous data transmission line, and outputs to the selected self-synchronous data transmission line a second acknowledge signal inputted from the succeeding-stage section, and further, given a state that data transfer toward the succeeding-stage section is enabled, outputs, to the succeeding-stage section, output data outputted from the selected self-synchronous data transmission line.

The FIFO memory device of this invention has a structure that a plurality of self-synchronous data transmission lines are arrayed in parallel. This plurality of self-synchronous data transmission lines are used as element devices for data transmission and data hold.

Also, immediately before the parallelly-provided self-synchronous data transmission lines, the FIFO memory device has an input control section. This input control section selects one of the parallelly-provided self-synchronous data transmission lines, and mediates the reception and delivery of a transfer request signal, a transfer instruction signal (acknowledge signal) and data between the selected self-synchronous data transmission line and the self-synchronous data transmission line of the preceding-stage section. Further, immediately after the parallelly-provided self-synchronous data transmission lines, the FIFO memory device has an output control section. This output control section selects one of the parallelly-provided self-synchronous data transmission lines, and mediates the reception and delivery of a transfer request signal, a transfer instruction signal (acknowledge signal) and data between the selected self-synchronous data transmission line and the self-synchronous data transmission line of the succeeding-stage section.

Thus, according to the FIFO memory device of this invention, there can be implemented a FIFO memory device which has the same functions as that of the related art even without any data path of cascade passage through self-synchronous data transmission lines, as compared with the self-synchronous FIFO memory device shown in the related art in which data transmission lines are connected in series.

Consequently, in this invention, since the self-synchronous data transmission lines are arranged in parallel, it becomes implementable to perform data input or output by one-time data transfer for an arbitrary self-synchronous data transmission line. Therefore, in this invention, unlike the related-art FIFO memory device in which self-synchronous data transmission lines are arrayed in series, it never occurs that the delay time increases in simple proportion to the maximum storage capacity. Therefore, according to this invention, the physical storage capacity can be substantially increased without increasing the delay time, and moreover, two asynchronous requests of write and read can be processed in parallel.

In the FIFO memory device of one embodiment, the input control section has a sequencer. This sequencer selects a transmission path for the first transfer request signal toward the self-synchronous data transmission lines forming the parallel structure as well as a transmission path for the first acknowledge signal derived from the self-synchronous data transmission lines forming the parallel structure, and further distributes the input data to the self-synchronous data transmission lines forming the parallel structure. In this embodiment, the input control section can be implemented with a simple circuit construction by virtue of the input control section having the sequencer.

In this embodiment, which is selected out of the parallelly-provided self-synchronous data transmission lines is determined by the sequencer provided inside the input control section. The sequencer is driven by a signal inputted from the self-synchronous data transmission line of the preceding-stage section, independently of the internal state of the FIFO memory device.

Also, in the FIFO memory device of one embodiment, the input control section further includes at an input stage a self-synchronous data transmission line composed of a self-synchronous signal control circuit and a data hold circuit. The self-synchronous data transmission line transfers the first transfer request signal and the first acknowledge signal between the preceding-stage section outer than the input control section and an internal circuit containing the sequencer of the input control section.

In this embodiment, since the input control section includes the self-synchronous data transmission line, more reliable data transmission can be fulfilled without decreasing the data transfer rate.

Also, in the FIFO memory device of one embodiment, the output control section has a sequencer. This sequencer selects a transmission path for the second transfer request signal derived from the self-synchronous data transmission line forming the parallel structure as well as a transmission path for the second acknowledge signal toward the self-synchronous data transmission lines forming the parallel structure and further selects output data outputted from the self-synchronous data transmission lines forming the parallel structure. According to this embodiment, the output control section can be implemented with a simple circuit construction by virtue of the output control section having the sequencer.

In this embodiment, which is selected out of the parallelly-connected self-synchronous data transmission lines is determined by the sequencer provided inside the output control section. The sequencer is driven by a signal inputted from the self-synchronous data transmission line of the succeeding-stage section, independently of the internal state of the FIFO memory device.

It is noted that whereas the sequencer inside the input control section and the sequencer inside the output control section operate independently of each other, the order in which the parallelly-connected self-synchronous data transmission lines are selected on and on is desirably made identical for both sequencers. As a result of this, it becomes implementable to substantially increase the physical storage capacity with the number of stages dynamically variable and without increasing the delay time that is simply proportional to the depth of the pipeline.

Also, in the FIFO memory device of one embodiment, the output control section further includes at an output stage a self-synchronous data transmission line composed of a self-synchronous signal control circuit and a data hold circuit. Then, the self-synchronous data transmission line transfers the second transfer request signal and the second acknowledge signal between the succeeding-stage section outer than the output control section and an internal circuit containing the sequencer of the output control section.

In this embodiment, since the output control section includes the self-synchronous data transmission line, more reliable data transmission can be fulfilled without decreasing the data transfer rate.

Also, the FIFO memory device of one embodiment has an input terminal to which a storage capacity control signal for changing storable data amount is inputted.

In the invention of this embodiment, since the FIFO memory device has an input terminal to which a storage capacity control signal for changing the storable data amount is inputted, the number of stages of the FIFO memory device can be made statically variable. That is, the dynamically variable number of stages of the FIFO memory device (i.e., maximum storage capacity of FIFO memory device) is determined with the use of this storage capacity control signal.

From the standpoint of buffer function, the upper limit of the dynamically variable number of stages is desirably as large as possible. However, it may be still desirable, on the other hand, that the storage capacity of the FIFO memory device is not excessive for cases where the input to the pipeline should favorably be halted under stagnated output of the pipeline.

That is, in the self-synchronous pipeline, when the output of the pipeline is stagnated, data transfer is autonomously halted on and on from outlet toward inlet of the pipeline, so that the acknowledge signal is finally fixed to L level at the inlet of the pipeline, thus making it possible for the preceding-stage section to find that the pipeline is saturated. For such a purpose, it is desirable that the maximum storage capacity of the FIFO memory device is properly restricted.

Also, in the FIFO memory device of one embodiment, the input control section has a sequencer, and this sequencer selects a transmission path for the first transfer request signal as well as a transmission path for the first acknowledge signal and further distributes input data. Also, the sequencer has an input terminal for the storage capacity control signal.

In this embodiment, out of the parallelly-provided self-synchronous data transmission lines, only self-synchronous data transmission lines of a number designated by the storage capacity control signal are targeted for the selection by the sequencer provided inside the input control section.

Also, in the FIFO memory device of one embodiment, the output control section has a sequencer for selecting a transmission path for the second transfer request signal as well as a transmission path for the second acknowledge signal and further for selecting the output data, and this sequencer has an input terminal for the storage capacity control signal.

In this embodiment, out of the parallelly-provided self-synchronous data transmission lines, only self-synchronous data transmission lines of a number designated by the storage capacity control signal are targeted for the selection by the sequencer provided inside the output control section.

It is noted that, for the input of the storage capacity control signal to the input control section and the output control section, the selection-targeted set of self-synchronous data transmission line, as well as the order of selection thereamong, are made identical for both the sequencer inside the input control section and the sequencer inside the output control section. As a result of this, it becomes implementable to properly restrict the maximum storage capacity of the FIFO memory device according to its application without adding any complex mechanism.

With the above-described means, there can be implemented a FIFO memory device the number of stages of which is dynamically and statically variable, making it possible to obtain a FIFO memory device which can be easily inserted into a self-synchronous pipeline and which is best suited for application systems and internal pipeline processing of the present invention. That is, there can be implemented a FIFO memory device capable of substantially increasing the physical storage capacity without increasing the delay time that is simply proportional to the depth of the pipeline.

DETAILED DESCRIPTION

Hereinbelow, the present invention is described in detail by embodiments thereof illustrated in the accompanying drawings.

First Embodiment

FIG. 1shows block configuration of a self-synchronous FIFO memory device as a first embodiment of the present invention.

The self-synchronous FIFO memory device100of this first embodiment has input terminals RST0, CI0, RI0and D0as well as output terminals CO0, RO0, Q0. This FIFO memory device100also includes an input control section101and an output control section102, as well as n self-synchronous data transmission lines111-11nconnected in parallel between the input control section101and the output control section102. Each of these self-synchronous data transmission lines111-11nis composed of a self-synchronous signal control circuit and a data hold circuit. This self-synchronous signal control circuit is similar in construction to the self-synchronous signal control circuit804ofFIG. 8, and the data hold circuit is similar in construction to the pipeline register801ofFIG. 8.

As shown inFIG. 1, all of these n self-synchronous data transmission lines111,112, . . .11nare arranged in parallel between the input control section101and the output control section102. Also, in this FIFO memory device100, a preceding-stage section is connected to the input side of the input control section101, while a succeeding-stage section is connected to the output side of the output control section102. These preceding-stage section and succeeding-stage section are given by, for example, self-synchronous data transmission lines711and712, respectively, such as shown inFIG. 7. Otherwise, the preceding-stage section and the succeeding-stage section may also be given, for example, by a construction similar to that of this FIFO memory device100.

The input control section101has an input terminal CI1to which a first transfer request signal inputted from the preceding-stage section is inputted, as well as an output terminal RO1for outputting to the preceding-stage section a first acknowledge signal derived from the self-synchronous data transmission lines111-11n, and a data input terminal D1to which data from the preceding-stage section is inputted. These input terminal CI1, output terminal RO1and data input terminal D1are connected to the input terminal CI0, output terminal RO0and data input terminal D0, respectively, of the FIFO memory device100.

Further, the input control section101has n output terminals CO1-COn for outputting a transfer request signal, n input terminals RI1-RIn to each of which an acknowledge signal is inputted, and n data output terminals Q1-Qn for outputting data. These n output terminals CO1-COn of the input control section101are connected to input terminals CI11-CI1n, respectively, of the n self-synchronous data transmission lines111-11n. Also, the n input terminals RI1-RIn of the input control section101are connected to n output terminals RO11-RO1n, respectively, of the n self-synchronous data transmission lines111-11n. Also, the n data output terminals Q1-Qn of the input control section101are connected to data input terminals D11-D1n, respectively, of the n self-synchronous data transmission lines111-11n.

Further, the input control section101has an input terminal RST1to which an initialization signal is inputted, and the input terminal RST1is connected to the input terminal RST0of the FIFO memory device100.

(Operation of Input Control Section101)

When an initialization signal is inputted to the input terminal RST0, causing the input terminal RST1of the input control section101to come to H level, the input control section101makes the input terminal CI1and the output terminal CO1connect to each other, the output terminal RO1and the input terminal RI1connect to each other, and the data input terminal D1and the data output terminal Q1connect to each other, thus being initialized.

Then, after the initialization on, during the input terminal RST1keeps L level, the input control section101switches the internal connection between the input terminal CI1and the output terminals CO1-COn each time the input terminal CI1changes from L level to H level. That is, upon each level change, the input control section101sequentially selects the output terminals CO2, . . . , COn, CO1, CO2, . . . cyclically and connects them to the input terminal CI1.

Likewise, after the initialization on, during the input terminal RST1keeps L level, the input control section101switches the internal connection between the output terminal RO1and the input terminals RI1-RIn each time the input terminal CI1changes from L level to H level. That is, upon each level change, the input control section101sequentially selects the input terminals RI2, . . . , RIn, RI1, RI2, . . . cyclically and connects them to the output terminal RO1.

Likewise, after the initialization on, during the input terminal RST1keeps L level, the input control section101switches the internal connection between the data input terminal D1and data output terminals Q1-Qn each time the input terminal CI1changes from L level to H level. That is, upon each level change, the input control section101sequentially selects the data output terminals Q2, . . . , Qn, Q1, Q2, . . . cyclically and connects them to the data input terminal D1.

(Operation of Output Control Section102)

The output control section102has n input terminals CI1-CIn to which second transfer request signals from the n self-synchronous data transmission lines111-11nare inputted, respectively, and n output terminals RO1-ROn for outputting a second acknowledge signal derived from the succeeding-stage section. Also, the output control section102has n data input terminals D1-Dn to which data derived from the n self-synchronous data transmission lines111-11nare inputted, respectively.

These n data input terminals D1-Dn are connected to data output terminals Q11-Q1nof the n self-synchronous data transmission lines111-11n, respectively. Also, the n output terminals RO1-ROn are connected to input terminals RI11-RI1n, respectively, of the n self-synchronous data transmission lines111-11n. Further, the n input terminals CI1-CIn are connected to output terminals CO11-CO1n, respectively, of the n self-synchronous data transmission lines111-11n.

Further, the output control section102has an output terminal CO2for outputting a second transfer request signal to the succeeding-stage section, an input terminal RI2to which a second acknowledge signal inputted from the succeeding-stage section is inputted, and a data output terminal Q2. These output terminal CO2, input terminal RI2and data output terminal Q2are connected to the output terminal CO0, input terminal RI0and data output terminal Q0, respectively, of the FIFO memory device100. Also, the output control section102has an input terminal RST2to which an initialization signal is inputted, and this input terminal RST2is connected to the input terminal RST0of the FIFO memory device100.

In this output control section102, when an initialization signal is inputted from the input terminal RST0, causing the input terminal RST2to come to H level, the output control section102is initialized. That is, the output control section102makes the input terminal CI1connect to the output terminal CO2, the input terminal RI2connect to the output terminal RO1, and the data input terminal D1connect to the data output terminal Q2.

After this initialization on, during the reset input terminal RST2keeps L level, the output control section102switches the internal connection between the output terminal CO2and the n input terminals CI1-CIn each time the input terminal RI2changes from L level to H level. That is, upon each level change, the output control section102sequentially selects the input terminals CI2, . . . , CIn, CI1, CI2, . . . cyclically and connects them to the output terminal CO2.

Likewise, during the reset input terminal RST2keeps L level, the output control section102switches the internal connection between the input terminal RI2and the n output terminals RO1-ROn each time the input terminal RI2changes from L level to H level. That is, upon each level change, the output control section102sequentially selects the output terminals RO2, . . . , ROn, RO1, RO2, . . . cyclically and connects them to the input terminal RI2. Likewise, upon each level change, the output control section102sequentially selects the data input terminal D2, . . . , Dn, D1, D2, . . . cyclically and connects them to the data output terminal Q2.

(Internal Structure of Input Control Section101)

Next, internal structure of the input control section101is described with reference to the block diagram ofFIG. 2. This input control section101has a self-synchronous data transmission line201, a sequencer202, a distribution control circuit203and a data distribution circuit204.

As described above, this input control section101has an input terminal RST1for the initialization signal, a data input terminal D1for data derived from the preceding-stage section, an input terminal CI1for the first transfer request signal derived from the preceding-stage section, and input terminals RI1-RIn for the first acknowledge signals derived from the n self-synchronous data transmission lines111-11n. Further, the input control section101has data output terminals Q1-Qn for the self-synchronous data transmission lines111-11n, output terminals CO1-COn for the first transfer request signals directed toward the self-synchronous data transmission lines111-11n, and an output terminal RO1for the first acknowledge signal directed toward the preceding-stage section.

The sequencer202has an input terminal RST22for a reset signal, an input terminal CLK22for a clock signal, and an output terminal SEQ22for a distribution instruction signal. The input terminal CLK22is connected to an output terminal CO21of the self-synchronous data transmission line201. Also, the input terminal RST22of the sequencer202is connected to the input terminal RST1of the input control section101.

When the input terminal RST22has come to H level, this sequencer202is initialized so that the value of the output terminal SEQ22is set to “1.” After this initialization on, during the input terminal RST22keeps L level, the sequencer202changes the value of the output terminal SEQ22in an order of “2,” . . . , “n,” “1,” “2,” . . . cyclically each time the clock-signal input terminal CLK22changes from L level to H level.

Also, the distribution control circuit203has an input terminal CI23to which the first transfer request signal is inputted, output terminals CO13-COn3for outputting the first transfer request signal, input terminals RI13-RIn3to which the first acknowledge signal (transfer instruction signal) is inputted, an output terminal RO23for outputting the first acknowledge signal (transfer instruction signal), and an input terminal SEL23to which the distribution instruction signal is inputted. The input terminal CI23is connected to the output terminal CO21of the self-synchronous data transmission line201, and the output terminal RO23is connected to an input terminal RI21of the self-synchronous data transmission line201.

It is noted that in the case where the self-synchronous data transmission line201is not provided, the input terminal CI23and output terminal RO23of the distribution control circuit203may be connected directly to the input terminal CI1and output terminal RO1, respectively, of the input control section101. Likewise, in the case where the self-synchronous data transmission line201is not provided, the input terminal CLK22of the sequencer202may be connected directly to the input terminal CI1of the input control section101. Also, the input terminal SEL23of this distribution control circuit203is connected to the output terminal SEQ22of the sequencer202.

Further, the n output terminals CO13-COn3of this distribution control circuit203are connected to the n output terminals CO1-COn, respectively, of the input control section101. Also, the n input terminals RI13-RIn3of this distribution control circuit203are connected to the n input terminals RI1-RIn, respectively, of the input control section101.

This distribution control circuit203transfers a signal inputted to the input terminal CI23to one of the n output terminals CO13-COn3according to a signal value of the distribution instruction signal inputted from the output terminal SEQ22of the sequencer202to the input terminal SEL23. Also likewise, this distribution control circuit203transfers a signal of one of the n input terminals RI13-RIn3to the output terminal RO23according to the value of the input terminal SEL23.

Also, the data distribution circuit204has a data input terminal D24, data output terminals Q14-Qn4, and an input terminal SEL24for the distribution instruction signal. This data input terminal D24is connected to a data output terminal Q21of the self-synchronous data transmission line201.

It is noted that in the case where the self-synchronous data transmission line201is not provided, the data input terminal D24of the data distribution circuit204may be connected directly to the data input terminal D1of the input control section101. Also, the input terminal SEL24of this data distribution circuit204is connected to the terminal SEQ22of the sequencer202.

Also, the n data output terminals Q14-Qn4of this data distribution circuit204are connected to the n data output terminals Q1-Qn, respectively, of the input control section101. This data distribution circuit204transfers a signal value inputted to the data input terminal D24to one of the n data output terminals Q14-Qn4according to a signal value of the distribution instruction signal inputted from the terminal SEQ22of the sequencer202to the input terminal SEL24. For example, the data distribution circuit204transfers a signal value inputted to the data input terminal D24to the data output terminals Q14, Q24-Qn4in correspondence to the values “1,” “2,” . . . “n” of the distribution instruction signal.

In order that the values (voltages) of the n output terminals CO1-COn in this input control section101will not become unstable, it has to be ensured that a change in the value (voltage) of the input terminal SEL23of the distribution control circuit203is effected during the input terminal CI23of the distribution control circuit203keeps H level. This is ensured, in this input control section101, by feeding identical input signals from the output terminal CO21of the self-synchronous data transmission line201to the input terminal CLK22of the sequencer202and the input terminal CI23of the distribution control circuit203.

That is, a certain time period is required after the input terminal CLK22of the sequencer202has changed to H level until the value of the input terminal SEL23of the distribution control circuit203changes. Therefore, it is ensured that the output terminal CO21of the self-synchronous data transmission line201has already been stabilized at H level at the time when the value of the input terminal SEL23of the distribution control circuit203changes.

Also, the structure of a self-synchronous signal control circuit (not shown) provided inside the self-synchronous data transmission line201ensures a sufficient shortness of the time required after the clock-signal input terminal CLK22of the sequencer202has changed to H level until the value of the input terminal SEL23of the distribution control circuit203changes, as compared with the time required after the input terminal CI23of the distribution control circuit203has changed to H level until its changing again to L level.

As far as the relationship between the value (voltage) of the input terminal SEL23and the value (voltage) of the input terminal CI23in the distribution control circuit203is ensured, a transfer control signal outputted by an output terminal RO21of the self-synchronous data transmission line201(or a self-synchronous signal control circuit provided inside the self-synchronous data transmission line201) may also be used as an input for the input terminal CLK22of the sequencer202.

It is noted that the self-synchronous data transmission line201in this input control section101is not essential for the function of the input control section in the present invention. However, without the provision of the self-synchronous data transmission line201, it would take time to distribute input data for the data input terminal D1of the input control section101to the data output terminals Q1-Qn. Therefore, providing the self-synchronous data transmission line201has an advantage of enabling more reliable data transmission without decreasing the data transfer rate.

(Internal Structure of Output Control Section102)

Next, internal structure of the output control section102inFIG. 1is described with reference to the block diagram ofFIG. 3. This output control section102has a self-synchronous data transmission line301, a sequencer302, a selection control circuit303and a data selection circuit304.

Also, this output control section102has an input terminal RST2, n input terminals D1-Dn, n input terminals CI1-CIn, and an input terminal RI2. Further, this output control section102has an output terminal Q2, an output terminal CO2and n output terminals RO1-ROn.

The sequencer302has a reset-signal input terminal RST32, a clock-signal input terminal CLK32and a selection-instruction-signal output terminal SEQ32. This clock-signal input terminal CLK32is connected to an output terminal RO31of the self-synchronous data transmission line301. Also, the input terminal RST32is connected to the input terminal RST2of the output control section102.

When the input terminal RST32has come to H level, this sequencer302is initialized so that the value of the output terminal SEQ32is set to “1.” After the initialization on, during the input terminal RST32keeps L level, the sequencer302changes the value of the output terminal SEQ32in an order of “2,” “n,” “1,” “2,” . . . cyclically each time the clock-signal input terminal CLK32changes from L level to H level.

Also, the selection control circuit303has n input terminals CI13-CIn3to which the second transfer request signal is inputted, an output terminal CO33for outputting the transfer request signal, an input terminal RI33to which the second acknowledge signal (transfer instruction signal) derived from the succeeding-stage section is inputted, n output terminals RO13-ROn3for outputting the second acknowledge signal (transfer instruction signal), and an input terminal SEL33to which the selection instruction signal derived from the sequencer302is inputted. Also, the output terminal CO33of this selection control circuit303is connected to an input terminal CI31of the self-synchronous data transmission line301, and the input terminal RI33is connected to the output terminal RO31of the data transmission line301.

It is noted that in the case where the self-synchronous data transmission line301is not provided, the output terminal CO33and input terminal RI33of the selection control circuit303may be connected directly to the output terminal CO2and input terminal RI2, respectively, of the output control section102. Likewise, in the case where the self-synchronous data transmission line301is not provided, the input terminal CLK32of the sequencer302may be connected directly to the input terminal RI2of the output control section102.

Also, the input terminal SEL33of the selection control circuit303is connected to the output terminal SEQ32of the sequencer302. The n input terminals CI13-CIn3of the selection control circuit303are connected to the n input terminals CI1-CIn of the output control section102. The n output terminals RO13-ROn3of this selection control circuit303are connected to the n output terminals RO1-ROn, respectively, of the output control section102.

This selection control circuit303selects a signal of one terminal out of the input terminals CI13-CIn3according to the value of the input terminal SEL33to which the selection instruction signal derived from the sequencer302is inputted, and then transfers the signal to the output terminal CO33. Also likewise, the selection control circuit303selects one terminal out of the output terminals RO13-ROn3according to the value of the input terminal SEL33, and then transfers to this selected terminal the second acknowledge signal derived from the input terminal RI33.

Also, the data selection circuit304has n input terminals D14-Dn4to which data is inputted, an output terminal Q34for outputting data, and an input terminal SEL34to which the selection instruction signal derived from the sequencer302is inputted. This output terminal Q34is connected to a data input terminal D31of the self-synchronous data transmission line301.

It is noted that in the case where the self-synchronous data transmission line301is not provided, the output terminal Q34of the data selection circuit304may be connected directly to the data output terminal Q2of the output control section102.

Also, the input terminal SEL34of this data selection circuit304is connected to the output terminal SEQ32of the sequencer302. Also, the n data input terminals D14-Dn4of the data selection circuit304are connected to the n data input terminals D1-Dn, respectively, of the output control section102.

Also, the data selection circuit304selects a value of one terminal out of the input terminals D14-Dn4according to the value of the input terminal SEL34to which the selection instruction signal derived from the sequencer302is inputted, and then transfers the value to the output terminal Q34.

In order that the values of the output terminals RO1-ROn of the output control section102will not become unstable, it has to be ensured that a change in the value of the input terminal SEL33of the selection control circuit303is effected during the input terminal RI33of the selection control circuit303keeps H level. This is ensured, in the output control section102ofFIG. 3, by feeding identical input signals (second acknowledge signals) from the output terminal RO31of the self-synchronous data transmission line301to the input terminal CLK32of the sequencer302and the input terminal RI33of the selection control circuit303.

That is, in this output control section102, a certain time period is required after the input terminal CLK32of the sequencer302has changed to H level until the value of the input terminal SEL33of the selection control circuit303changes. Therefore, it is ensured that the input terminal RI33of the selection control circuit303has already been stabilized at H level at the time when the value of the input terminal SEL33of the selection control circuit303changes.

Also, the structure of the self-synchronous signal control circuit included in the self-synchronous data transmission line301ensures a sufficient shortness of the time required after the input terminal CLK32of the sequencer302has changed to H level until the value of the input terminal SEL33of the selection control circuit303changes, as compared with the time required after the input terminal RI33of the selection control circuit303has changed to H level until its changing again to L level. As far as the relationship between the value of the input terminal SEL33and the value of the input terminal RI33in the selection control circuit303is ensured, a transfer control signal outputted by a self-synchronous signal control circuit (not shown) provided inside the self-synchronous data transmission line301may also be used as an input for the input terminal CLK32of the sequencer302.

It is noted that the self-synchronous data transmission line301provided in this output control section102is not essential for the function of the output control section in this embodiment. However, without the provision of the self-synchronous data transmission line301, it would take time to select one out of data inputted to the data input terminals D1-Dn, and then transfer the data to the data output terminal Q2. In consideration of this, it is desirable to provide this self-synchronous data transmission line301with a view to fulfilling more reliable data transmission without decreasing the data transfer rate.

In the FIFO memory device100of this first embodiment, the input control section101selects one out of the parallel-connected self-synchronous data transmission lines111-11n, and transfers to this one selected self-synchronous data transmission line a first transfer request signal inputted from the preceding-stage section. Also, the input control section101transfers to the preceding-stage section a first acknowledge signal outputted from the selected self-synchronous data transmission line. Further, based on the first transfer request signal and the first acknowledge signal, the input control section101decides whether or not data transfer to the selected self-synchronous data transmission line is enabled. If the data transfer to the selected self-synchronous data transmission line is enabled, then the input control section101outputs input data, which is inputted from the preceding-stage section, to the selected self-synchronous data transmission line.

Also, the output control section102selects one out of the parallel-connected self-synchronous data transmission lines111-11n, and outputs a second transfer request signal, which is outputted from the selected self-synchronous data transmission line, to the succeeding-stage section. Also, the output control section102outputs a second acknowledge signal, which is inputted from the succeeding-stage section, to the selected self-synchronous data transmission line. Further, based on the second transfer request signal and the second acknowledge signal, the output control section102decides whether or not data transfer to the succeeding-stage section is enabled. If the data transfer to the succeeding-stage section is enabled, then the output control section102outputs output data, which is outputted from the selected self-synchronous data transmission line, to the succeeding-stage section.

The FIFO memory device of this first embodiment has a structure that n self-synchronous data transmission lines111-11nare arrayed in parallel, and these n self-synchronous data transmission lines111-11nare used as element devices for data transfer and data hold.

The input control section101selects one out of the parallelly-provided self-synchronous data transmission lines111-11n, and mediates the reception and delivery of the first transfer request signal, the first acknowledge signal (transfer instruction signal) and data between the selected one self-synchronous data transmission line and the self-synchronous data transmission line contained in the preceding-stage section. Further, the output control section102selects one out of the parallelly-provided n self-synchronous data transmission lines111-11n, and mediates the reception and delivery of the second transfer request signal, the second acknowledge signal (transfer instruction signal) and data between the selected one self-synchronous data transmission line and the self-synchronous data transmission line contained in the succeeding-stage section.

In the self-synchronous FIFO memory device100of this first embodiment, since the n self-synchronous data transmission lines111-11nare arranged in parallel unlike the conventional self-synchronous FIFO memory device in which data transmission lines are connected in series, it becomes implementable to perform data input or output by one-time data transfer for an arbitrary self-synchronous data transmission line. Therefore, in this first embodiment, unlike the conventional FIFO memory device in which self-synchronous data transmission lines are connected in series, it never occurs that the delay time increases in simple proportion to the maximum storage capacity. Accordingly, the physical storage capacity can be substantially increased without increasing the delay time, and moreover, two asynchronous requests of write and read can be processed in parallel.

Also, in the self-synchronous FIFO memory device100of this first embodiment, the input control section101has the sequencer202. This sequencer202inputs a distribution instruction signal to the distribution control circuit203, thereby making the distribution control circuit203select a transmission path of the first transfer request signal toward one of the parallelly-connected n self-synchronous data transmission lines111-11n. Also, this sequencer202inputs the distribution instruction signal to the distribution control circuit203, thereby making the distribution control circuit203select a transmission path of the first acknowledge signal from the parallelly-connected n self-synchronous data transmission lines111-11n. Further, the sequencer202inputs the distribution instruction signal to the data distribution circuit204, thereby making the data distribution circuit204distribute the input data to one of the n self-synchronous data transmission lines111-11n.

As shown above, in this first embodiment, which is selected out of the parallelly-provided n self-synchronous data transmission lines111-11nis determined by the sequencer202provided inside the input control section101. The sequencer202is driven by propagation of the transfer request signal inputted from the self-synchronous data transmission line contained in the preceding-stage section, independently of the internal state of the FIFO memory device100. In this first embodiment, the input control section101can be implemented with a simple circuit construction by virtue of the input control section101having the sequencer202.

Further, in the self-synchronous FIFO memory device100of this first embodiment, the output control section102has the sequencer302. This sequencer302inputs a selection instruction signal to the selection control circuit303to control the selection control circuit303so that the selection control circuit303selects a transmission path of the second transfer request signal out of the n self-synchronous data transmission lines111-11n. Also, the sequencer302inputs a selection instruction signal to the selection control circuit303, thereby making the selection control circuit303select a transmission path of the second acknowledge signal toward the n self-synchronous data transmission lines111-11n. Further, the sequencer302inputs the selection instruction signal to the data selection circuit304, thereby making the data selection circuit304select one out of output data outputted from the n self-synchronous data transmission lines111-11n.

As shown above, in this first embodiment, which is selected out of the parallelly-provided n self-synchronous data transmission lines111-11nis determined by the sequencer302provided inside the output control section102. The sequencer302is driven by propagation of the acknowledge signal (transfer instruction signal) inputted from the self-synchronous data transmission line contained in the succeeding-stage section, independently of the internal state of the FIFO memory device100. In this first embodiment, the output control section102can be implemented with a simple circuit construction by virtue of the output control section102having the sequencer302.

It is noted that the sequencer202inside the input control section101and the sequencer302inside the output control section102operate independently of each other, whereas the order in which the parallelly-provided n self-synchronous data transmission lines111-11nare selected on and on is desirably set to the same one for both sequencers202,302. As a result, it becomes implementable to substantially increase the physical storage capacity with the number of stages dynamically variable and without increasing the delay time.

Second Embodiment

Next,FIG. 4shows a self-synchronous FIFO memory device400as a second embodiment of the present invention. This self-synchronous FIFO memory device400includes an input control section401and an output control section402for handling a data-storage capacity control signal, as well as n self-synchronous data transmission lines411-41n. These n self-synchronous data transmission lines411-41nare connected in parallel between the input control section401and the output control section402.

This self-synchronous FIFO memory device400has an input terminal RST0, an input terminal EN0, an input terminal CI0, an input terminal R10and an input terminal D0. Further, this FIFO memory device400has an output terminal CO0, an output terminal RO0and an output terminal Q0.

This second embodiment differs from the connection structure of the self-synchronous FIFO memory device100of the first embodiment shown inFIG. 1only in that the input terminal EN0, to which the storage capacity control signal is inputted, is connected to an input terminal EN1of the input control section401and an input terminal EN2of the output control section402.

In this second embodiment, in the case where the input terminal EN0of the FIFO memory device400shows a value of “n”, the input control section401operates in the same manner as the input control section101of the first embodiment, and the output control section402operates in the same manner as the output control section102of the first embodiment.

Meanwhile, in the case where the input terminal EN0shows a value of “1,” the input control section401operates in such a manner as to maintain internal connection only with a self-synchronous data transmission line411at all times. Similarly, in the case where the input terminal EN0shows a value of “1,” the output control section402operates in such a manner as to maintain internal connection only with the self-synchronous data transmission line411at all times. Accordingly, the storage capacity control signal inputted to the input terminal EN0is a signal directing to select any one of integer values “1” to “n” as the number of data pieces that can be stored between the input control section401and the output control section402.

Next,FIG. 5is a block diagram showing the configuration of the input control section401ofFIG. 4. This input control section401includes a self-synchronous data transmission line501, a sequencer502, a distribution control circuit503and a data distribution circuit504.

This input control section401has input terminals RST1, EN1, D1, CI1, and n input terminals RI1-RIn. Further, this input control section401has n output terminals Q1-Qn, n output terminals CO1-COn, and one output terminal RO1.

This input control section401differs from the connection structure of the input control section101shown inFIG. 2only in that the input terminal EN1, to which the storage capacity control signal is inputted, is connected to an input terminal EN52of the sequencer502.

In this input control section401, the sequencer502differs from the sequencer202of the first embodiment ofFIG. 2only in that if the input terminal EN1shows a value of i that falls within a range of 1 to n, then the value of an output terminal SEQ52of the sequencer502is limited to within a range of 1 to i. That is, if the value i of the input terminal EN1of the input control section401is i=n, then this sequencer502operates entirely in the same manner as the sequencer202ofFIG. 2. Meanwhile, the value i of the input terminal EN1of the input control section401is i=1, then the sequencer502outputs a “1” as the value of the output terminal SEQ52at all times. As a result of this, the data distribution circuit504and the distribution control circuit503select a transmission line in conjunction with the self-synchronous data transmission line411.

Next,FIG. 6is a block diagram showing the configuration of an output control section402of this second embodiment. This output control section402includes a self-synchronous data transmission line601, a sequencer602, a selection control circuit603, and a data selection circuit604. Also, this output control section402includes an input terminals RST2, an input terminal EN2, n input terminals D1-Dn, n input terminals CI1-CIn, and an input terminal RI2.

Further, this output control section402includes an output terminal Q2, an output terminal CO2and n output terminals ROI-ROn. This output control section402differs from the connection structure of the output control section102of the first embodiment shown inFIG. 3only in that the input terminal EN2, to which the storage capacity control signal is inputted, is connected to an input terminal EN62of the sequencer602.

In this output control section402, the sequencer602differs from the sequencer302of the first embodiment ofFIG. 3only in that if the input terminal EN2shows a value of i that falls within a range of 1 to n, then the value of an output terminal SEQ62of the sequencer602is limited to within a range of 1 to i. That is, in this output control section402, if the value i of the input terminal EN2is i=n, then the sequencer602operates entirely in the same manner as the sequencer302ofFIG. 3. Meanwhile, the value i of the input terminal EN2is i=1, then the sequencer602outputs a “1” as the value of the output terminal SEQ62at all times. As a result of this, the data distribution circuit604and the selection control circuit603select a transmission line in conjunction with the self-synchronous data transmission line411.

Thus, according to this second embodiment, by virtue of the inclusion of input terminals EN0, EN1, EN2for the storage capacity control signal serving for changing the storable data amount, the number of stages of the FIFO memory device400can be made statically variable. That is, the dynamically variable number of stages of the FIFO memory device (i.e., maximum storage capacity of the FIFO memory device) can be determined by this storage capacity control signal.

From the standpoint of buffer function, the upper limit of the dynamically variable number of stages is desirably as large as possible. However, it may be still desirable, on the other hand, that the storage capacity of the FIFO memory device is not excessive for cases where the input to the pipeline should favorably be halted under stagnated output of the pipeline. That is, in the self-synchronous pipeline, when the output of the pipeline is stagnated, data transfer is autonomously halted on and on from outlet toward inlet of the pipeline, so that the acknowledge signal is finally fixed to L level at the inlet of the pipeline, thus making it possible for the preceding-stage section to find that the pipeline is saturated. For such a purpose, it is desirable that the maximum storage capacity of the FIFO memory device is properly restricted.

Also, in this second embodiment, the input control section401has the sequencer502, the output control section402has the sequencer602, and these sequencers502,602have the input terminals EN52, EN62, respectively, for the storage capacity control signal. Then, for the input of the storage capacity control signal to the input control section401and the output control section402, the selection-targeted set out of n self-synchronous data transmission line411-41n, as well as the order of selection thereamong, are made identical for both the sequencer502inside the input control section401and the sequencer602inside the output control section402. As a result of this, it becomes implementable to properly restrict the maximum storage capacity of the FIFO memory device according to its application without adding any complex mechanism.

Next,FIG. 7shows a self-synchronous pipeline system equipped with the self-synchronous FIFO memory device100of the first embodiment. In this self-synchronous pipeline system, the self-synchronous FIFO memory device100is connected between self-synchronous data transmission lines711and712. In this self-synchronous pipeline system, the self-synchronous data transmission line711, the self-synchronous FIFO memory device100and the self-synchronous data transmission line712are connected in cascade.

In this self-synchronous pipeline system, a combinational circuit721is connected between the self-synchronous data transmission line711and the self-synchronous FIFO memory device100. Also, a combinational circuit722is connected between the self-synchronous FIFO memory device100and the self-synchronous data transmission line712.

The self-synchronous data transmission line711includes an input terminal CI for the transfer request signal, an output terminal CO for the first transfer request signal, an input terminal RI for the first acknowledge signal (transfer instruction signal), an output terminal RO for the acknowledge signal (transfer instruction signal), a data input terminal D, and a data output terminal Q. Also, the self-synchronous data transmission line712includes an input terminal CI for the second transfer request signal, an output terminal CO for the transfer request signal, an input terminal RI for the acknowledge signal (transfer instruction signal), an output terminal RO for the second acknowledge signal (transfer instruction signal), a data input terminal D, and a data output terminal Q.

In this self-synchronous pipeline system, data is inputted to the data input terminal D of the self-synchronous data transmission line711. Then, data outputted from the data output terminal Q of the self-synchronous data transmission line711is inputted to a data input terminal D0of the FIFO memory device100via the combinational circuit721.

Then, data outputted from the data output terminal Q0of the FIFO memory device100is inputted to the data input terminal D of the self-synchronous data transmission line712via the combinational circuit722. Further, this self-synchronous data transmission line712outputs data from the data output terminal Q.

In this self-synchronous pipeline system as an application system, the self-synchronous data transmission lines711,712and the self-synchronous FIFO memory device100have structures that allow alternative use for each other, except for the difference in their internal physical storage capacity.

As an example of more specific application systems of this self-synchronous pipeline system, a self-synchronous arithmetic pipeline is conceivable. In this arithmetic pipeline, the self-synchronous data transmission line711is disposed on the input side of the combinational circuit721, while the self-synchronous data transmission line712is disposed on the output side of the combinational circuit722. As a result of this, the combinational circuits721and722implement a pipelined arithmetic unit, the combinational circuit721implements an arithmetic unit for processing the first half of an operation, and the combinational circuit722implements an arithmetic unit for processing the second half of the operation.

In this arithmetic pipeline, in a case where the arithmetic processing time at the combinational circuit722can be longer than the processing time at the combinational circuit721depending on the contents of arithmetic operation, the self-synchronous data transmission line712exercises control so that the timing at which the output terminal RO of the self-synchronous data transmission line712rises from L level to H level is temporarily delayed. This makes it possible to ensure enough arithmetic processing time of the combinational circuit722.

In this case, if the self-synchronous FIFO memory device100is not provided, the self-synchronous data transmission line711could not hold new data until the processing by the combinational circuit722is ended. This would result in lowered throughput of the whole arithmetic pipeline.

In contrast to this, in the case where the self-synchronous FIFO memory device100is provided, the combinational circuit721can carry on arithmetic operation with the succeeding data train even while the output terminal RO of the self-synchronous data transmission line712keeps fixed at L level, as far as the self-synchronous FIFO memory device100is not saturated.

Thereafter, when the output terminal RO of the self-synchronous data transmission line712has come to H level, the data train stored within the self-synchronous FIFO memory device100can be fed to the combinational circuit722at the shortest possible intervals.

As shown above, the self-synchronous FIFO memory device100of the first embodiment can be easily inserted at an arbitrary site in an arithmetic pipeline system including the self-synchronous data transmission lines711,712and the combinational circuits721,722. This makes it possible to maintain high arithmetic throughput of the arithmetic pipeline system.