Semiconductor arrangement and method of manufacture

A semiconductor arrangement includes a semiconductor layer having a source/drain region and a first epitaxial layer over the semiconductor layer. The semiconductor arrangement includes a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer define a contact structure for the source/drain region.

BACKGROUND

In semiconductor technology Group III-V (or III-V) semiconductor compounds, such as InGaAs, are used to form various integrated circuit devices, such as high power field-effect transistors, high frequency transistors, high electron mobility transistors (HEMTs), etc. A HEMT is a field effect transistor incorporating a junction between two materials with different band gaps to form the channel. Such a junction is sometimes referred to as a heterojunction. HEMTs have a number of attractive properties including, for example, high electron mobility, the ability to transmit signals at high frequencies, etc.

DETAILED DESCRIPTION

One or more techniques for fabricating a semiconductor arrangement are provided herein. In some embodiments, the semiconductor arrangement comprises a contact structure for a source/drain region of a HEMT.

Turning toFIG. 1, a plurality of layers used in the formation of a semiconductor arrangement are illustrated, in accordance with some embodiments. In some embodiments, the semiconductor arrangement comprises an ohmic contact in a HEMT. The plurality of layers are formed over a substrate102. In some embodiments, the substrate102comprises at least one of an epitaxial layer, a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, and InP, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the substrate102comprises one of any Group III-V or Group II-VI semiconductor. In some embodiments, the substrate102comprises crystalline silicon.

In some embodiments, a first semiconductor layer104is formed over the substrate102. In some embodiments, the first semiconductor layer104is an InGaAs channel layer. According to some embodiments, the first semiconductor layer104is formed by at least one of chemical vapor deposition (CVD), metal-organic CVD (MOCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), pulsed laser deposition, sputtering, evaporative deposition, vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other applicable techniques. In some embodiments, one or more buffer layers (not shown) are formed between the substrate102and the first semiconductor layer104to relax a lattice mismatch between the first semiconductor layer104and the substrate102. In some embodiments, the first semiconductor layer104is the substrate102or is part of the substrate102. If the first semiconductor layer104is the substrate102or is part of the substrate102, the substrate102is treated to have at least some of the aforementioned characteristics of the first semiconductor layer104.

In some embodiments, a barrier layer106is formed over the first semiconductor layer104by at least one of CVD, MOCVD, LPCVD, PECVD, UHVCVD, RPCVD, ALD, PVD, pulsed laser deposition, sputtering, evaporative deposition, VPE, MBE, LPE, or other applicable techniques. In some embodiments, the barrier layer106is formed to a thickness of at least 5 nm to reduce leakage current and decrease parasitic capacitance. In some embodiments, the barrier layer106is formed of a semiconductor doped with a dopant to supply free carriers to the first semiconductor layer104by at least one of an in-situ deposition method or other applicable techniques. In some embodiments, the barrier layer106is an AlGaAs layer. In some embodiments, the barrier layer106is formed to be in direct contact with the first semiconductor layer104or is formed to be in direct contact with the substrate102in embodiments where the first semiconductor layer104is part of the substrate102.

In some embodiments, a high-k dielectric layer108is formed over the barrier layer106. As used herein, the term “high-k dielectric layer” refers to a material having a dielectric constant, k, greater than about 3.9, which is the k value of SiO2. The material of the high-k dielectric layer may be any suitable material. Examples of the material of the high-k dielectric layer include but are not limited to Ga2O3, GdGaO, Al2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, Al2OxNy, HfOxNy, ZrOxNy, La2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, or other suitable materials. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2. The high-k dielectric layer108is formed over the barrier layer106by at least one of CVD, MOCVD, LPCVD, RPCVD, PECVD, ALD, PVD, pulsed laser deposition, sputtering, evaporative deposition, VPE, MBE, ALD and LPE, or other applicable techniques. In some embodiments, the high-k dielectric layer108is formed to be in direct contact with the barrier layer106.

In some embodiments, a gate metallization layer110is formed over the high-k dielectric layer108. In some embodiments, the gate metallization layer110comprises at least one of a conductive metallic layer or an electrically conducting layer. In some embodiments, the gate metallization layer110comprises at least one of Co, Ni, W, Ti, Ta, Cu, Al, Mo, TiN, TaN, WSi, Ni—Si, Co—Si, WN, TiAlN, TaCN, TaC, TaSiN, metal alloys such as Ti—Al alloy, Al—Cu alloy, or other suitable materials. In some embodiments, the gate metallization layer110is formed by at least one of PVD, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, VPE, MBE, LPE, or other applicable techniques. In some embodiments, the gate metallization layer110is subjected to chemical mechanical polishing (CMP). In some embodiments, the gate metallization layer110is formed to be in direct contact with the high-k dielectric layer108.

According to some embodiments, a photoresist layer111is formed over the gate metallization layer110. In some embodiments, the photoresist layer111is formed by at least one of spinning, spray coating, or other applicable techniques. The photoresist layer111comprises a light sensitive material such that properties, such as solubility, of the photoresist layer111are affected by light. The photoresist layer111is either a negative photoresist or a positive photoresist. With respect to a negative photoresist, regions of the negative photoresist become insoluble when illuminated by a light source such that application of a solvent to the negative photoresist during a subsequent development stage removes non-illuminated regions of the negative photoresist. A pattern formed in the negative photoresist is thus a negative of a pattern defined by opaque regions of a template between the light source and the negative photoresist. In a positive photoresist, illuminated regions of the positive photoresist become soluble and are removed via application of a solvent during development. Thus, a pattern formed in the positive photoresist is a positive image of opaque regions of the template between the light source and the positive photoresist. In some embodiments, the photoresist layer111is formed to be in direct contact with the gate metallization layer110.

As illustrated inFIG. 1, the photoresist layer111is patterned to expose a portion of the gate metallization layer110, according to some embodiments. Referring toFIG. 2, a portion of the gate metallization layer110not underlying, and thus not protected by, the patterned photoresist layer111is removed by an etching process. For example, in the illustrated embodiment, a portion of the gate metallization layer110is removed to expose a first portion of the high-k dielectric layer108. In some embodiments, the etching process is at least one of a plasma etching process, a reactive ion etching (RIE) process, a wet etching process, or other applicable techniques. The patterned photoresist layer111is then removed to expose the gate metallization layer110, and a second photoresist layer112is formed over the gate metallization layer110and the first portion of the high-k dielectric layer108. In some embodiments, the second photoresist layer112is formed to be in direct contact with the gate metallization layer110and the high-k dielectric layer108.

In some embodiments, the second photoresist layer112is formed by at least one of spinning, spray coating, or other applicable techniques. The second photoresist layer112comprises a light sensitive material such that properties, such as solubility, of the second photoresist layer112are affected by light. The second photoresist layer112is either a negative photoresist or a positive photoresist.

Still referring toFIG. 2, the second photoresist layer112is patterned to expose a second portion of the high-k dielectric layer108, according to some embodiments. Referring toFIG. 3, portions of one or more layers not underlying, and thus not protected by, the patterned second photoresist layer112are removed by an etching process. For example, in the illustrated embodiment, a portion of the high-k dielectric layer108and a portion of the barrier layer106are removed to expose the first semiconductor layer104. In some embodiments, the etching process is at least one of a plasma etching process, an RIE process, a wet etching process, or other applicable techniques. The patterned second photoresist layer112is then removed to expose the gate metallization layer110and the first portion of the high-k dielectric layer108.

Referring toFIG. 4, in some embodiments, a first epitaxial layer114is formed over the first semiconductor layer104. In some embodiments, the first epitaxial layer114fills a portion of a recess115created by the removal of the portion of the barrier layer106and the portion of the high-k dielectric layer108. According to some embodiments, the first epitaxial layer114is selectively grown on the first semiconductor layer104in a conformal manner in the recess115. In some embodiments, due to the selective, conformal growth of the first epitaxial layer114in the recess115, the first epitaxial layer114abuts a sidewall of the barrier layer106and there is little to no gap between the first epitaxial layer114and the sidewall of the barrier layer106. According to some embodiments, due to the selective, conformal growth of the first epitaxial layer114in the recess115, the first epitaxial layer114abuts a sidewall of the high-k dielectric layer108and there is little to no gap between the first epitaxial layer114and the sidewall of the high-k dielectric layer108. According to some embodiments, the first epitaxial layer114is formed to be in direct contact with the first semiconductor layer104.

In some embodiments, the first epitaxial layer114comprises germanium. In some embodiments, the first epitaxial layer114is doped by n-type dopants to increase a free charge carrier concentration of electrons in the first epitaxial layer114. In some embodiments, the first epitaxial layer114is a phosphorus doped germanium (Ge:P) layer. According to some embodiments, the first epitaxial layer114is formed by at least one at least one of CVD, LPCVD, PECVD, UHVCVD, RPCVD, ALD, physical vapor deposition, PLD, sputtering, evaporative deposition, VPE, MBE, LPE, or other applicable techniques. In some embodiments, the first epitaxial layer114is formed using Ge2H6(1% in H2) with a level of phosphorus doping of 5-15% PH3in He. In some embodiments, GeH4is used as a precursor for forming the first epitaxial layer114. In some embodiments, conditions for selectively grown epitaxial Ge:P using GeH4as a precursor flowing at 50-800 sccm are a temperature of 450-500 degrees Celsius and a pressure of 10-100 Torr. In some embodiments, conditions for selectively grown epitaxial Ge:P using Ge2H6as a precursor flowing at 50-800 sccm are a temperature of 350-500 degrees Celsius and a pressure of 10-100 Torr. In some embodiments, an n-type doping source is PH3with a dilution in H2—He at 3-30 slm. In some embodiments, at least one of source or injection rates of the n-type doping source PH3are 30-400 sccm.

Referring toFIG. 5, in some embodiments, a second epitaxial layer116is formed over the first epitaxial layer114. In some embodiments, the second epitaxial layer116is selectively grown on the first epitaxial layer114in a conformal manner in the recess115. In some embodiments, due to the selective, conformal growth of the second epitaxial layer116in the recess115, the second epitaxial layer116abuts a sidewall of the high-k dielectric layer108and there is little to no gap between the second epitaxial layer116and the sidewall of the high-k dielectric layer108. According to some embodiments, the second epitaxial layer116is formed to be in contact with the first epitaxial layer114.

In some embodiments, the second epitaxial layer116comprises SixGe1-x, where x<1. In some embodiments, the second epitaxial layer116is an n-type SiGe layer. In some embodiments, the second epitaxial layer116comprises a graded composition. That is, a concentration of a material in the second epitaxial layer116changes (increases or decreases) in a direction moving from the first semiconductor layer104toward a top surface of the second epitaxial layer116. In some embodiments, an n-type dopant in the second epitaxial layer116is phosphorus. According to some embodiments, the second epitaxial layer116is formed by at least one of CVD, LPCVD, PECVD, UHVCVD, RPCVD, ALD, physical vapor deposition, PLD, sputtering, evaporative deposition, VPE, MBE, LPE, or other applicable techniques.

According to some embodiments, the second epitaxial layer116is formed using Ge2H6(1% in H2) at a flow rate of 50-800 sccm and at a temperature of 350-500 degrees Celsius at a pressure of 10-200 Torr. According to some embodiments, Si2H6is a second precursor to the formation of the second epitaxial layer116, with a flow rate of 20-300 sccm at a pressure of 10-200 Torr and a temperature of 350-550 degrees Celsius. An n-type doping source, according to some embodiments, is PH3diluted in H2—He at 3-30 slm, injected into a reactor at 30-400 sccm. In some embodiments, the second epitaxial layer116is formed by a GeH4precursor at a flow rate of 50-800 sccm, a pressure of 10-200 Torr and at a temperature of 450-500 degrees Celsius. In some embodiments, SiH4is a second precursor to the formation of the second epitaxial layer116, with a flow rate of 20-300 sccm, a pressure of 10-200 Torr and a temperature of 450-550 degrees Celsius. In some embodiments, an atomic percentage of germanium in the second epitaxial layer116is in the range of 30-80%.

Referring toFIG. 6, in some embodiments, a third epitaxial layer118is formed over the second epitaxial layer116. In some embodiments, the third epitaxial layer118is selectively grown on a top surface of the second epitaxial layer116and conformally fills the recess115to contact a sidewall of the high-k dielectric layer108. In some embodiments, the second epitaxial layer116is not present and the third epitaxial layer118is selectively grown on a top surface of the first epitaxial layer114conformally fills the recess115to contact a sidewall of the high-k dielectric layer108.

In some embodiments, the third epitaxial layer118comprises silicon. In some embodiments, the third epitaxial layer118is doped by n-type dopants to increase a free charge carrier concentration of electrons in the third epitaxial layer118. In some embodiments, the third epitaxial layer118is a phosphorus doped silicon (Si:P) layer. According to some embodiments, the third epitaxial layer118is formed by at least one of CVD, LPCVD, PECVD, UHVCVD, RPCVD, ALD, PVD, PLD, sputtering, evaporative deposition, VPE, MBE, LPE, or other applicable techniques.

In some embodiments, the third epitaxial layer118undergoes selective epitaxial growth (SEG) over the first epitaxial layer114or the second epitaxial layer116using dichlorosilane (DCS) as a precursor with a flow rate between 70-300 sccm, at a temperature between 650-800 degrees Celsius and at a pressure of 20-200 Torr. In some embodiments, the third epitaxial layer118is non-selectively grown over first epitaxial layer114or the second epitaxial layer116with a precursor comprising Si3H8, at a flow rate of 20-300 mg/min at a temperature of 400-550 degrees Celsius at a pressure of 20-200 Torr. In some embodiments, at least one of Si2H4or Si4H10are used as precursors in non-selective growth of the third epitaxial layer118. In some embodiments, a phosphorus source for growing the third epitaxial layer118, either selectively or non-selectively, is PH3with a source and injection rate of 300-900 sccm. In some embodiments, the PH3source is not diluted in H2—He. In some embodiments, a source for phosphorus to dope the third epitaxial layer118is PH3diluted in He, where the concentration of PH3is in a range of 5%-15% by volume percentage.

Referring toFIG. 7, in some embodiments, a contact layer120is formed over the third epitaxial layer118. In some embodiments, the contact layer120is formed of at least one of a conductive metallic layer or an electrically conducting layer. In some embodiments, the contact layer120comprises at least one of Co, Ni, W, Ti, Ta, Cu, Al, Mo, TiN, TaN, WSi, Ni—Si, Co—Si, WN, TiAlN, TaCN, TaC, TaSiN, metal alloys such as Ti—Al alloy, Al—Cu alloy, or other suitable materials. In some embodiments, the contact layer120is formed by at least one of PVD, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, MBE, or other applicable techniques. In some embodiments, the contact layer120is subjected to chemical mechanical polishing (CMP), etching, or the like. In some embodiments, the contact layer120is formed to be in direct contact with the third epitaxial layer118.

FIG. 8illustrates a zoomed out view of a semiconductor arrangement100resulting from the aforementioned method, according to some embodiments. It may be appreciated that whileFIGS. 1-7illustrate a formation process for one-half of the semiconductor arrangement100, the same or a similar process may be performed to form the other half of the semiconductor arrangement. The semiconductor arrangement100comprises a transistor, a first contact122for providing electrical conductivity to a first source/drain region underlying the first contact122and within at least one of the substrate102or the first semiconductor layer104, and a second contact124for providing electrical conductivity to a second source/drain region underlying the second contact124and within at least one of the substrate102or the first semiconductor layer104. In some embodiments, the first contact122comprises a first instance of the first epitaxial layer114, a first instance of the second epitaxial layer116, a first instance of the third epitaxial layer118, and a first instance of the contact layer120. In some embodiments where the second epitaxial layer116is not present, the first contact122comprises the first instance of the first epitaxial layer114, the first instance of the third epitaxial layer118, and the first instance of the contact layer120. In some embodiments, the second contact124comprises a second instance of the first epitaxial layer114, a second instance of the second epitaxial layer116, a second instance of the third epitaxial layer118, and a second instance of the contact layer120. In some embodiments where the second epitaxial layer116is not present, the second contact124comprises the second instance of the first epitaxial layer114, the second instance of the third epitaxial layer118, and the second instance of the contact layer120.

A gate structure of the transistor is disposed between the first contact122and the second contact124. The gate structure comprises, among other things, the barrier layer106, the high-k dielectric layer108, and the gate metallization layer110. A channel of the transistor underlies the gate structure. In some embodiments, the transistor is a HEMT.

Turning toFIG. 9, a plurality of layers used in the formation of a semiconductor arrangement are illustrated, in accordance with some embodiments. In some embodiments, at least some of the layers, features, formation techniques, etc. discussed with respect toFIGS. 9-18mimic at least some of the layers, features, formation techniques, etc. discussed with respect toFIGS. 1-7and thus are not described in detail so as to limit redundancy. In some embodiments, the semiconductor arrangement comprises an ohmic contact in a HEMT. The plurality of layers are formed over a substrate902. In some embodiments, the substrate902comprises at least one of an epitaxial layer, a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, and InP, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the substrate102comprises one of any Group III-V or Group II-VI semiconductor. In some embodiments, the substrate102comprises crystalline silicon.

In some embodiments, a first semiconductor layer904is formed over the substrate902. In some embodiments, the first semiconductor layer904is an InGaAs layer. According to some embodiments, the first semiconductor layer904is formed by at least one of CVD, MOCVD, LPCVD, PECVD, UHVCVD, RPCVD, ALD, physical vapor deposition, pulsed laser deposition, sputtering, evaporative deposition, VPE, MBE, LPE, or other applicable techniques. In some embodiments, one or more buffer layers (not shown) are formed between the substrate902and the first semiconductor layer904to relax a lattice mismatch between the first semiconductor layer904and the substrate902. In some embodiments, the first semiconductor layer904is the substrate902or is part of the substrate902. If the first semiconductor layer904is the substrate902or is part of the substrate902, the substrate902is treated to have at least some of the aforementioned characteristics of the first semiconductor layer904.

In some embodiments, a barrier layer906is formed over the first semiconductor layer904by at least one of CVD, LPCVD, PECVD, UHVCVD, RPCVD, ALD, PVD, pulsed laser deposition, sputtering, evaporative deposition, VPE, MBE, LPE, or other applicable techniques. In some embodiments, the barrier layer906is formed to a thickness of at least 5 nm to reduce leakage current and decrease parasitic capacitance. In some embodiments, the barrier layer906is formed of a semiconductor doped with a dopant to supply free carriers to the first semiconductor layer904by an in-situ deposition method or other applicable techniques. In some embodiments, the barrier layer906is an AlGaAs layer. In some embodiments, the barrier layer906is formed to be in direct contact with the first semiconductor layer904or is formed to be in direct contact with the substrate902in embodiments where the first semiconductor layer904is part of the substrate902.

In some embodiments, a high-k dielectric layer908is formed over the barrier layer906. The high-k dielectric layer908is formed over the over the barrier layer906by at least one of CVD, LPCVD, PECVD, ALD, PVD, pulsed laser deposition, sputtering, evaporative deposition, VPE, MBE, ALD, LPE, or other applicable techniques. In some embodiments, the high-k dielectric layer908is formed to be in direct contact with the barrier layer906.

In some embodiments, a gate metallization layer910is formed over the high-k dielectric layer908. In some embodiments, the gate metallization layer910comprises at least one of a conductive metallic layer or an electrically conducting layer. In some embodiments, the gate metallization layer910comprises at least one of Co, Ni, W, Ti, Ta, Cu, Al, Mo, TiN, TaN, WSi, Ni—Si, Co—Si, WN, TiAlN, TaCN, TaC, TaSiN, metal alloys such as Ti—Al alloy, Al—Cu alloy, or other suitable materials. In some embodiments, the gate metallization layer910is formed by at least one of PVD, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, VPE, LPE, MBE, or other applicable techniques. In some embodiments, the gate metallization layer910is subjected to CMP. In some embodiments, the gate metallization layer910is formed to be in direct contact with the high-k dielectric layer908.

According to some embodiments, a photoresist layer911is formed over the gate metallization layer910. In some embodiments, the photoresist layer911is formed by at least one of spinning, spray coating, or other applicable techniques. The photoresist layer911comprises a light sensitive material such that properties, such as solubility, of the photoresist layer911are affected by light. The photoresist layer911is either a negative photoresist or a positive photoresist. In some embodiments, the photoresist layer911is formed to be in direct contact with the gate metallization layer910.

As illustrated inFIG. 9, the photoresist layer911is patterned to expose a portion of the gate metallization layer910, according to some embodiments. Referring toFIG. 10, a portion of the gate metallization layer910not underlying, and thus not protected by, the patterned photoresist layer911is removed by an etching process. For example, in the illustrated embodiment, a portion of the gate metallization layer910is removed to expose a first portion of the high-k dielectric layer908. In some embodiments, the etching process is at least one of a plasma etching process, an RIE process, a wet etching process, or other applicable techniques. The patterned photoresist layer911is then removed to expose the gate metallization layer910, and a second photoresist layer912is formed over the gate metallization layer910and the first portion of the high-k dielectric layer908. In some embodiments, the second photoresist layer912is formed to be in direct contact with the gate metallization layer910and the high-k dielectric layer908.

In some embodiments, the second photoresist layer912is formed by at least one of spinning, spray coating, or other applicable techniques. The second photoresist layer912comprises a light sensitive material such that properties, such as solubility, of the second photoresist layer912are affected by light. The second photoresist layer912is either a negative photoresist or a positive photoresist.

Still referring toFIG. 10, the second photoresist layer912is patterned to expose a second portion of the high-k dielectric layer908, according to some embodiments. Referring toFIG. 11, portions of one or more layers not underlying, and thus not protected by, the patterned second photoresist layer912are removed by an etching process. For example, in the illustrated embodiment, a portion of the high-k dielectric layer908and a portion of the barrier layer906are removed to expose the first semiconductor layer904. In some embodiments, the etching process is at least one of a plasma etching process, an RIE process, a wet etching process, or other applicable techniques. The patterned second photoresist layer912is then removed to expose the gate metallization layer910and the first portion of the high-k dielectric layer908.

Referring toFIG. 12, in some embodiments, a first epitaxial layer914is formed over the first semiconductor layer904. In some embodiments, the first epitaxial layer914fills a portion of a recess915created by the removal of the portion of the barrier layer906and the portion of the high-k dielectric layer908. According to some embodiments, the first epitaxial layer914is selectively grown on the first semiconductor layer904in a conformal manner in the recess915. In some embodiments, due to the selective, conformal growth of the first epitaxial layer914in the recess915, the first epitaxial layer914abuts a sidewall of the barrier layer906and there is little to no gap between the first epitaxial layer914and the sidewall of the barrier layer906. According to some embodiments, due to the selective, conformal growth of the first epitaxial layer114in the recess115, the first epitaxial layer914abuts a sidewall of the high-k dielectric layer908and there is little to no gap between the first epitaxial layer914and the sidewall of the high-k dielectric layer908. According to some embodiments, the first epitaxial layer914is formed to be in direct contact with the first semiconductor layer904.

In some embodiments, the first epitaxial layer914comprises germanium. In some embodiments, the first epitaxial layer914is doped by n-type dopants to increase a free charge carrier concentration of electrons in the first epitaxial layer914. In some embodiments, the first epitaxial layer914is a phosphorus doped germanium (Ge:P) layer. According to some embodiments, the first epitaxial layer914is formed by at least one at least one of CVD, LPCVD, PECVD, UHVCVD, RPCVD, ALD, PVD, PLD, sputtering, evaporative deposition, VPE, MBE, LPE, or other applicable techniques. In some embodiments, the first epitaxial layer914is formed using Ge2H6(1% in H2) with a level of phosphorus doping of 5-15% PH3in He. In some embodiments, GeH4is used as a precursor for forming the first epitaxial layer914. In some embodiments, conditions for selectively grown epitaxial Ge:P using GeH4as a precursor flowing at 50-800 sccm are a temperature of 450-500 degrees Celsius and a pressure of 10-100 Torr. In some embodiments, conditions for selectively grown epitaxial Ge:P using Ge2H6as a precursor flowing at 50-800 sccm are a temperature of 350-500 degrees Celsius and a pressure of 10-100 Torr. In some embodiments, an n-type doping source is PH3with a dilution in H2—He at 3-30 slm. In some embodiments, at least one of source or injection rates of the n-type doping source PH3are 30-400 sccm.

Referring toFIG. 13, in some embodiments, a second epitaxial layer916is formed over the first epitaxial layer914. In some embodiments, the second epitaxial layer916is selectively grown on the first epitaxial layer914in a conformal manner in the recess915. In some embodiments, due to the selective, conformal growth of the second epitaxial layer916in the recess915, such that the second epitaxial layer916abuts a sidewall of the high-k dielectric layer908and there is little to no gap between the second epitaxial layer916and the sidewall of the high-k dielectric layer908. According to some embodiments, the second epitaxial layer916is formed to be in contact with the first epitaxial layer914.

In some embodiments, the second epitaxial layer916comprises SixGe1-x, where x<1. In some embodiments, the second epitaxial layer916is an n-type SiGe layer. In some embodiments, the second epitaxial layer916comprises a graded composition. That is, a concentration of material in the second epitaxial layer916changes (increases or decreases) in a direction moving from the first semiconductor layer904toward a top surface of the second epitaxial layer916. In some embodiments, an n-type dopant in the second epitaxial layer916is phosphorus. According to some embodiments, the second epitaxial layer916is formed by at least one of CVD, LPCVD, PECVD, UHVCVD, RPCVD, ALD, PVD, PLD, sputtering, evaporative deposition, VPE, MBE, LPE, or other applicable techniques.

According to some embodiments, the second epitaxial layer916is formed using Ge2H6(1% in H2) at a flow rate of 50-800 sccm and at a temperature of 350-500 degrees Celsius at a pressure of 10-200 Torr. According to some embodiments, Si2H6is a second precursor to the formation of the second epitaxial layer916, with a flow rate of 20-300 sccm at a pressure of 10-200 Torr and a temperature of 350-550 degrees Celsius. An n-type doping source, according to some embodiments, is PH3diluted in H2—He at 3-30 slm, injected into a reactor at 30-400 sccm. In some embodiments, the second epitaxial layer916is formed by a GeH4precursor at a flow rate of 50-800 sccm, a pressure of 10-200 Torr and at a temperature of 450-500 degrees Celsius. In some embodiments, SiH4is a second precursor to the formation of the second epitaxial layer916, with a flow rate of 20-300 sccm, a pressure of 10-200 Torr and a temperature of 450-550 degrees Celsius. In some embodiments, an atomic percentage of germanium in the second epitaxial layer is in the range of 30-80%

Referring toFIG. 14, an oxide mask layer918is formed over the gate metallization layer910and the second epitaxial layer916or the first epitaxial layer914when the second epitaxial layer916is not present. In some embodiments, the oxide mask layer918comprises SiO2or other dielectric material. In some embodiments, the oxide mask layer918is formed by at least one of CVD, LPCVD, PECVD, UHVCVD, RPCVD, ALD, PVD, PLD, evaporative deposition, VPE, MBE, LPE, or other applicable techniques. In some embodiments, the oxide mask layer918is formed to contact a top surface of the gate metallization layer910, a top surface of the high-k dielectric layer908, a top surface of the second epitaxial layer916, and at least one of a sidewall of the high-k dielectric layer908or a sidewall of the gate metallization layer910. In some embodiments where the second epitaxial layer916is not present, the oxide mask layer918is formed to contact a top surface of the gate metallization layer910, a top surface of the high-k dielectric layer, a top surface of the first epitaxial layer914, and at least one of a sidewall of the high-k dielectric layer908or a sidewall of the gate metallization layer910.

Referring toFIG. 15, the oxide mask layer918is patterned to form an opening920that exposes a portion of the second epitaxial layer916or a portion of the first epitaxial layer914when the second epitaxial layer916is not present, in accordance with some embodiments. In some embodiments, the oxide mask layer918is patterned using an etching process and a photoresist (not shown). In some embodiments, the etching process is at least one of a plasma etching process, a reactive ion etching (RIE) process, a wet etching process, or other applicable techniques.

Referring toFIG. 16, a third epitaxial layer922is formed over the oxide mask layer918and in the opening920. In some embodiments, the third epitaxial layer922is non-selectively grown over the oxide mask layer918and over the second epitaxial layer916such that the third epitaxial layer922contacts a top surface of the second epitaxial layer916, sidewalls of the oxide mask layer918that defines the opening920, and a top surface of the oxide mask layer918. In some embodiments where the second epitaxial layer916is not present, the third epitaxial layer922is non-selectively grown over the oxide mask layer918and over the first epitaxial layer914such that the third epitaxial layer922contacts a top surface of the first epitaxial layer914, sidewalls of the oxide mask layer918that defines the opening920, and a top surface of the oxide mask layer918.

In some embodiments, the third epitaxial layer922is grown conformally, allowing the third epitaxial layer922to grow on sidewalls of the oxide mask layer918that define the opening920and on a top surface of the oxide mask layer918. In some embodiments, the third epitaxial layer922is grown non-selectively at a temperature of 450-500 degrees Celsius. In some embodiments, a second opening924is defined by sidewalls of the third epitaxial layer922.

Referring toFIG. 17, a contact layer926is formed in the second opening924over the third epitaxial layer922. In some embodiments, the contact layer926is formed of at least one of a conductive metallic layer or an electrically conducting layer. In some embodiments, the contact layer926comprises at least one of Co, Ni, W, Ti, Ta, Cu, Al, Mo, TiN, TaN, WSi, Ni—Si, Co—Si, WN, TiAlN, TaCN, TaC, TaSiN, metal alloys such as Ti—Al alloy, Al—Cu alloy, or other suitable materials. In some embodiments, the contact layer926is formed by at least one of PVD, CVD, LPCVD, ALCVD, ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), MBE, or other applicable techniques. In some embodiments, the contact layer926is formed to be in direct contact with the third epitaxial layer922. In some embodiments, at least a portion of the contact layer926is grown, such as in the second opening924.

Referring toFIG. 18, at least one of the contact layer926or the third epitaxial layer922are planarized by chemical mechanical polishing to expose the oxide mask layer918. It is to be appreciated that whileFIGS. 17 and 18illustrate the contact layer926as being formed before chemical mechanical polishing of the third epitaxial layer922, in some embodiments the third epitaxial layer922is polished to expose the oxide mask layer918prior to the contact layer926being formed. In such embodiments, a top surface of the contact layer926may extend above a top surface of at least one of the third epitaxial layer922or the oxide mask layer918

FIG. 19illustrates a zoomed out view of a semiconductor arrangement900resulting from the aforementioned method, according to some embodiments. It may be appreciated that whileFIGS. 9-17illustrate a formation process for one-half of the semiconductor arrangement900, the same or a similar process may be performed to form the other after of the semiconductor arrangement. The semiconductor arrangement900comprises a transistor, a first contact928for providing electrical conductivity to a first source/drain region underlying the first contact928and within at least one of the substrate902or the first semiconductor layer904, and a second contact930for providing electrical conductivity to a second source/drain region underlying the second contact930and within at least one of the substrate902or the first semiconductor layer904. In some embodiments, the first contact928comprises a first instance the first epitaxial layer914, a first instance of the second epitaxial layer916, a first instance of the third epitaxial layer922, and a first instance of the contact layer926. In some embodiments where the second epitaxial layer916is not present, the first contact928comprises the first instance of the first epitaxial layer914, the first instance of the third epitaxial layer922, and the first instance of the contact layer926. In some embodiments, the second contact930comprises a second instance of the first epitaxial layer914, a second instance of the second epitaxial layer916, a second instance of the third epitaxial layer922, and a second instance of the contact layer926. In some embodiments where the second epitaxial layer916is not present, the second contact930comprises the second instance of the first epitaxial layer914, the second instance of the third epitaxial layer922, and the second instance of the contact layer926.

A gate structure of the transistor is disposed between the first contact928and the second contact930. The gate structure comprises, among other things, the barrier layer906, the high-k dielectric layer908, and the gate metallization layer910. A channel of the transistor underlies the gate structure. In some embodiments, the transistor is a HEMT.

According to some embodiments, a contact structure of a semiconductor arrangement is formed at temperatures that are lower than temperature at which other materials or interfaces of the semiconductor arrangement melt or are otherwise adversely affected. In this way, an interface between the high-k dielectric layer108/808and the barrier layer106/806, which typically degrades at a temperature far lower than other epitaxial layers, is prevented from degradation or degradation is minimized. Components of the contact structure are epitaxial layers that are grown, rather than layers that formed in other manners that require higher temperatures, such as 600 degrees Celsius or greater, than temperatures used in growing the epitaxial contact layers, which are generally between 350 degrees Celsius and 550 degrees Celsius as described above. The contact structure provides electrical connectivity to a source/drain region of a HEMT in some embodiments, where temperatures used to form the contact structure do not exceed temperatures used in forming the HEMT. According to some embodiments, the contact structure provides electrical connectivity to a source/drain region of a compound semiconductor heterojunction device. In some embodiments, a compound semiconductor heterojunction device includes any device formed from any Group III-V or Group II-VI semiconductor.

Moreover, the formation of the contact structure according to the aforementioned techniques reduce or minimize the amount of metal alloys present in the contact structure, which tend to degrade over time. Further, the formation of the contact structure against the barrier layer and the high-k dielectric layer reduces, minimizes, or eliminates gaps present between the contact structure and barrier layer and between the contact structure and the high-k dielectric layer, which mitigates channel surface depletion that can cause the contact structure to degrade.

In some embodiments, a method of forming a semiconductor arrangement includes forming a semiconductor layer, wherein the semiconductor layer comprises a source/drain region. In some embodiments, the method includes selectively growing a first epitaxial layer conformally over the semiconductor layer. In some embodiments, the method includes forming a second epitaxial layer over the first epitaxial layer. In some embodiments, the method includes forming a contact layer over the second epitaxial layer, wherein the first epitaxial layer, the second epitaxial layer, and the contact layer define a contact structure for the source/drain region.

In some embodiments, a semiconductor arrangement includes a semiconductor layer having a source/drain region, a barrier layer over the semiconductor layer, a high-k dielectric layer over the barrier layer, and a first epitaxial layer over the semiconductor layer. In some embodiments, a sidewall of the first epitaxial layer contacts the barrier layer and the high-k dielectric layer. In some embodiments, the semiconductor arrangement includes a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer define a contact structure for the source/drain region.

In some embodiments, a high electron mobility transistor (HEMT) includes an InGaAs layer having a source/drain region and a channel region. In some embodiments, the semiconductor arrangement includes a first epitaxial layer over the source/drain region. In some embodiments, the semiconductor arrangement includes a high-k dielectric layer over the channel region, wherein a sidewall of the high-k dielectric layer contacts a sidewall of the first epitaxial layer.

The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand various aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of various embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers, regions, features, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques, growth techniques, or deposition techniques such as CVD, for example.