Horizontal memory array structure with scavenger layer

Various embodiments of the present disclosure are directed towards a resistive random access memory (RRAM) device including a scavenger layer. A bit line overlying a semiconductor substrate. A data storage layer around outer sidewalls and a top surface of the bit line. A word line overlying the data storage layer. A scavenger layer between the word line and the bit line such that a bottom surface of the scavenger layer is aligned with a bottom surface of the bit line. A lateral thickness of the scavenger layer is less than a vertical thickness of the scavenger layer.

BACKGROUND

Many modern electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data only while it is powered, while non-volatile memory is able to keep data when power is removed. Resistive random access memory (RRAM) is one promising candidate for next generation non-volatile memory technology due to its simple structure and CMOS logic compatible process technology that is involved. An RRAM cell includes a dielectric data storage layer having a variable resistance, which is placed between two conductive wires.

DETAILED DESCRIPTION

Resistive random access memory (RRAM) cells may be disposed in a horizontal memory array. In a horizontal memory array, a first bit line overlies a second bit line respectively extending along in a first direction. The first bit line is separated from the second bit line by an isolation layer. A data storage layer overlies and surrounds the first bit line and the second bit line. A word line is disposed over the data storage layer along a second direction (where the first direction is orthogonal to the second direction) and extend downward along opposite sides of the first and second bit lines. Thus, the word line is separated from the first and second bit lines by the data storage layer. Thus, a first RRAM cell is defined by the first bit line, the data storage layer, and the word line. Additionally, a second RRAM cell is defined by the second bit line, the data storage layer, and the word line.

Depending on a voltage applied to the first bit line and the word line, a portion of the dielectric data storage layer (sandwiched between the first bit line and the word line) will undergo a reversible change (e.g., form or remove a conductive filament in the data storage layer). The reversible change may be between a high resistance state associated with a first data state (e.g., a ‘0’ or ‘RESET’) and a low resistance state associated with a second data state (e.g., a ‘1’ or ‘SET’). Once a resistance state is set, the first RRAM cell will retain the resistive state until another voltage is applied to induce a RESET operation (resulting in a high resistance state) or a SET operation (resulting in a low resistance state). A same operation may be carried out between the second bit line and the word line, thereby changing a resistance state of the second RRAM cell. Due to the straight outer sidewalls of the pillar structure and the rectangular shape of the first and second bit lines, an electric field between the first bit line and the word line is substantially uniform over the entirety of the outer sidewalls. The substantially uniform electric field makes the location of the conductive filament variable and/or unpredictable for different write operations, thereby reducing distinct data states, stability, and/or reliability of the memory device.

In some embodiments of the present disclosure, to eliminate the uniform electric field between the first bit line and the world line, a conductive scavenger layer may be formed between the first bit line and the word line. The conductive scavenger layer is configured to direct the electric field to an upper region (e.g., an upper corner) between a top surface of the first bit line and the word line, thereby distorting the uniformity of the electric field and facilitating a maximum magnitude of the electric field in the upper region (thereby confining the conductive filament to the upper region). This, in part, makes the location, conductivity, and/or predictability of the conductive filament more consistent, thereby increasing distinct data states, stability, and reliability of the memory device. Further, the conductive scavenger layer comprises a scavenger material (e.g., titanium nitride) configured to “scavenge” (i.e., collect, absorb, and/or store) a reactive species (e.g., oxygen) from the data storage layer. This, in part, further improves formation and/or conductivity of the conductive filament, thereby further increasing distinct data states, stability, and reliability of the memory device.

Referring toFIG. 1A, a cross-sectional view of a memory device100including memory cells120a-din accordance with some embodiments is provided.

The memory device100includes four bit lines104a-d, such that a first bit line104aunderlies a second bit line104b, and a third bit line104cunderlies a fourth bit line104d. The first and second bit lines104a-b, and the third and fourth bit lines104c-dare respectively separated from one another by lower isolation structures112. Upper isolation structures114isolate the second and fourth bit lines104b,104dfrom an overlying first word line116a. The bit lines104a-dand the first word line116adefine a first column124aof the memory device100. The bit lines104a-drespectively extend in a first direction (e.g., into the page along the z-axis), the first word line116aextends in a second direction (e.g., along the x-axis), such that the first direction is orthogonal to the second direction. The bit lines104a-doverlie an interconnect dielectric structure102. In some embodiments, the bit lines104a-doverlie and are electrically coupled to semiconductor devices (e.g., transistors) disposed on an underlying semiconductor substrate (not shown). A scavenger layer106extends in the first direction along sidewalls and an upper surface of each bit line104a-d. A data storage layer108continuously extends around the bit lines104a-dand the scavenger layer106, such that the scavenger layer106and the data storage layer108are sandwiched between each bit line104a-dand the first word line116a.

In some embodiments, the first column124aof the memory device100includes memory cells120a-drespectively configured as resistive random-access memory (RRAM) cells. Each memory cell120a-dis defined by a bit line (e.g., one of the bit lines104a-d), the scavenger layer106, the data storage layer108, and the first word line116a. For example, a first memory cell120ais defined by the first bit line104a, the first word line116a, and the layers (the scavenger layer106and the data storage layer108) disposed between the first bit and word lines104a,116a. A second memory cell120bis defined by the second bit line104b, the first word line116a, and the layers (the scavenger layer106and the data storage layer108) disposed between the aforementioned lines. A third memory cell120cis defined by the third bit line104c, the first word line116a, and the layers (the scavenger layer106and the data storage layer108) disposed between the aforementioned lines. A fourth memory cell120dis defined by the fourth bit line104d, the first word line116a, and the layers (the scavenger layer106and the data storage layer108) disposed between the aforementioned lines.

In some embodiments, the bit lines104a-dand first word line116aare electrically coupled to support circuitry (e.g., transistors, diodes, microcontrollers, any combination of the aforementioned, etc.) configured to selectively apply formation, read, and/or write signals. The first word line116adefines the first column124aand each bit line104a-ddefines a separate row in a memory array. Consequently, by providing suitable bias conditions to the first word line116aand the first bit line104aan electrical resistance of the data storage layer108between the first bit and word lines104a,116amay be switched. Thus, the first memory cell120amay be switched between a first state with low resistance (a conductive filament is made in the data storage layer108between the first bit and word lines104a,116a) and a second state with a high resistance (at least a portion of the conductive filament is unmade in the data storage layer108), or vice versa to store data. The memory cells120b-dmay each be switched between the first and second states as described above.

During operation of the memory device100, the scavenger layer106is configured to manipulate a strength of an electrical field due to the bias conditions. A lateral thickness Tlof the scavenger layer106is less than a vertical thickness Tvof the scavenger layer106. This, in part, directs a maximum strength of the electric field around the first bit line104aand the scavenger layer106to an upper region120urof the first memory cell120a. Thus, during a formation and/or write operation, the conductive filament in the data storage layer forms in the upper region120ur, thereby increasing stability, reliability, and distinct data states in each memory cell120a-dof the memory device100. In some embodiments, the conductive filament is confined to the upper region120ur, such that the conductive filament does not form along outer sidewalls of the scavenger layer106.

In some embodiments, the lateral thickness T1is, for example, within a range of about 3 to 5 nanometers. The vertical thickness Tvis, for example, within a range of about 5 to 8 nanometers. The vertical thickness Tvis, for example, approximately 1.2 to 1.6 times greater than the lateral thickness T1. For example, the vertical thickness Tvmay be 1.2 times greater than the lateral thickness T1. In some embodiments, if the vertical thickness Tvis 1.2 times or greater than the lateral thickness T1, then the maximum strength of the electric field is directed to the upper region120ur. In further embodiments, if the vertical thickness Tvis 1.6 times or less than the lateral thickness T1, then the maximum strength of the electric field is directed to the upper region120urwithout electrically shorting the first bit line104ato the second bit line104b.

In some embodiments, the data storage layer108may have any composition suitable for the data storage layer of an RRAM cell. A material suitable for the data storage layer of an RRAM cell is one that can be induced to undergo a reversible phase change between a high resistance state and a low resistance state. In some embodiments, the change is between an amorphous state (i.e., no presence of a conductive filament in the data storage layer108) and a metallic state (i.e., presence of a conductive filament in the data storage layer108). The phase change can be accompanied by or associated with a change in molecular structure. For example, an amorphous metal oxide may lose oxygen as it undergoes a phase change to a metallic state (thereby forming the conductive filament). The oxygen may be stored in a portion of the data storage layer108that remains in the amorphous state or in an adjacent layer (e.g., the scavenger layer106). Although described as a dielectric, only the low resistance state need be a dielectric. In most embodiments, the data storage layer108is a high-k dielectric while in the low resistance state. In some embodiments, the data storage layer108is a transitional metal oxide. Examples of materials that can be suitable for data storage layer108include nitric oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zirconium oxide, and/or aluminum oxide.

In some embodiments, the bit lines104a-dand/or the first word line116amay, for example, be or comprise titanium, tantalum, titanium nitride, tantalum nitride, tungsten, ruthenium, zirconium, platinum, aluminum nickel, or the like. In some embodiments, the bit lines104a-dmay respectively comprise a first material different than a second material the first word line116ais comprise of. Further, the scavenger layer106may, for example, be or comprise titanium nitride, tantalum nitride, titanium, tantalum, or the like. The data storage layer108may, for example, be or comprise gold and/or hafnium oxide, copper and hafnium oxide, aluminum and hafnium oxide, arsenic and hafnium oxide, gold tellurium and hafnium oxide, silicon oxide, titanium oxide, aluminum oxide (e.g., Al2O3), tantalum oxide, zirconium oxide, or the like. Therefore, the scavenger layer106comprises a conductive material different than the bit lines104a-dand/or the first word line116a. Further, by virtue of the conductive material (of the scavenger layer106), the scavenger layer106is configured to “scavenge” (i.e., collect, absorb, and/or store) a reactive species (e.g., oxygen) from the data storage layer108. This, in part, enhances formation of the filament in the data storage layer108, thereby further increasing stability, reliability, and distinct data states in each memory cell120a-dof the memory device100.

Referring toFIG. 1B, a top view corresponding to some embodiments of the memory device100ofFIG. 1A, as indicated by the cut-away lines shown inFIGS. 1A-1Bis provided.

The second and fourth bit lines104b,104d, the scavenger layers106, and the data storage layers108respectively extend in the first direction (e.g., along the z-axis). The first word line116aand a second word line116brespectively extend in the second direction (e.g., the x-axis), such that the first direction is orthogonal to the second direction. In some embodiments, the second and fourth bit lines104b,104d, the scavenger layers106, the data storage layers108, and the first and second word lines116a-brespectively have a bottom surface that is parallel to a top surface of an underlying semiconductor substrate (not shown). The second and fourth bit lines104b,104d, underlying first and third bit lines (104a,104cofFIG. 1A), and the second word line116bdefine a second column124bof the memory device100. The first column124acomprises four memory cells (120a-dofFIG. 1A) and the second column124bcomprises four memory cells (not shown), such that the memory device100comprises a total of eight memory cells. The memory cells within the second column124bare respectively configured as the first memory cell (120aofFIG. 1A). The first and second word lines116a,116bare laterally separated from one another by an upper inter-metal dielectric (IMD) structure126. The second and fourth bit lines104b,104dare laterally separated from one another by the upper IMD structure126.

AlthoughFIGS. 1A-1Bdescribe the memory cells (e.g., memory cells120a-dofFIG. 1A) in the memory device100as being resistive random access memory (RRAM) cells, it will be appreciated that the memory cells (e.g., memory cells120a-dofFIG. 1A) are not limited to such devices. Rather, in alternative embodiments, the memory cells (e.g., memory cells120a-dofFIG. 1A) may comprise phase-change random-access memory (PCRAM) cells, magnetoresistive random-access memory (MRAM) cells, conductive bridging random access memory (CBRAM) cells, or the like. In such embodiments, the memory cells can be formed to direct a maximum strength of the electric field around the bit line to an upper region located at top corners of the bit line.

In some embodiments, if the memory cells are respectively MRAM cells, then each MRAM cell may comprise a free layer, a tunneling barrier layer, a reference layer, and/or a fixed layer. In the aforementioned embodiment, the free layer may, for example, be or comprise cobalt iron, cobalt iron boron, cobalt iron tantalum, cobalt iron boron tantalum, tungsten, ruthenium, or the like. The tunneling barrier layer may, for example, be or comprise magnesium oxide, aluminum oxide, or the like. The reference layer may, for example, be or comprise cobalt iron, cobalt iron boron, cobalt iron tantalum, cobalt iron boron tantalum, tungsten, ruthenium, or the like. The fixed layer may, for example, be or comprise cobalt platinum ruthenium, cobalt platinum iridium, or the like.

In some embodiments, if the memory cells are respectively CBRAM cells, then the first word line116amay, for example, be or comprise gold, copper, gold tellurium, copper tellurium, or the like. In the aforementioned embodiments, the data storage layer108may, for example, be or comprise hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium zirconium oxide, hafnium titanium oxide, or the like. In further embodiments, if the memory cells are respectively PCRAM cells, then the bit lines104a-dand/or the first word line116amay respectively, for example, be or comprise titanium, tantalum, titanium nitride, tantalum nitride, tungsten, carbon, or the like. In the aforementioned embodiment, the data storage layer108may, for example, be or comprise germanium antimony tellurium, germanium tellurium, germanium antimony, antimony tellurium, or the like.

Referring toFIG. 2A, a cross-sectional view of a memory device200acorresponding to some alternative embodiments of the memory device100ofFIG. 1Ais provided.

The memory device200aincludes a selector layer202disposed between the data storage layer108and the first word line116a, such that the first memory cell120aincludes the first bit line104a, the first word line116a, and the layers (the scavenger layer106, the data storage layer108, and the selector layer202) sandwiched between the first bit and word lines104a,116a. The memory cells120b-dare respectively configured as the first memory cell120a. The selector layer202is configured to switch between a low resistance state and a high resistance state depending on whether a voltage applied across the selector layer202is greater than a threshold voltage. For example, the selector layer202may have a high resistance state if a voltage cross the selector layer202is less than the threshold voltage, and the selector layer202may have a low resistance state if a voltage across the selector layer202is greater than the threshold voltage. In some embodiments, the threshold voltage may, for example, be within a range of about 0.1 to 0.6 volts (V). In some embodiments, an operational voltage (i.e., a voltage that may be applied to form the conductive filament in the data storage layer108) of the data storage layer108may, for example, be within a range of about 0.5 to 2 V. The threshold voltage of the selector layer202may, for example, be less than the operational voltage of the data storage layer108. In some embodiments, the memory device200ais a part of a cross-point memory array, such that the memory cells120a-dare respectively configured as one-resistor one-selector (IRIS) cells.

Referring toFIG. 2B, a top view corresponding to some embodiments of the memory device200aofFIG. 2A, as indicated by the cut-away lines shown inFIGS. 2A-2Bis provided.

The selector layer202extends in the first direction (e.g., along the z-axis) orthogonal to the second direction (e.g., along the x-axis). In some embodiments, a bottom surface of the selector layer202is parallel to a top surface of an underlying semiconductor substrate (not shown).

Referring toFIG. 2C, a cross-sectional view of a memory device200ccorresponding to some alternative embodiments of the memory device200aofFIG. 2Ais provided. The scavenger layer106is sandwiched between the data storage layer108and the selector layer202. The data storage layer108directly contacts and extends along outer sidewalls of the first bit line104aand a top surface of the first bit line104a. In some embodiments, the scavenger layer106is configured to confine a formation and/or removal of a conductive filament in the data storage layer108within the upper region120ur. A thickness Tslof the selector layer202is greater than a thickness Tdsof the data storage layer108. In some embodiments, a maximum value of the thickness Tslis at least two times greater than a maximum value of the thickness Tds.

Referring toFIG. 2D, a cross-sectional view of a memory device200dcorresponding to some alternative embodiments of the memory device200aofFIG. 2Ais provided.

An outer scavenger layer204is disposed between the data storage layer108and the selector layer202. In some embodiments, the outer scavenger layer204comprises a same material as the scavenger layer106. The outer scavenger layer204is configured to “scavenge” (i.e., collect, absorb, and/or store) oxygen from the data storage layer108, thereby further increasing stability, reliability, and distinct data states in each memory cell120a-dof the memory device100. Further, the outer scavenger layer204enhances direction of the electric field to the upper region120ur, thereby further increasing stability, reliability, and distinct data states in each memory cell120a-dof the memory device100.

Referring toFIG. 3A, a cross-sectional view of a memory device300acorresponding to some alternative embodiments of the memory device200aofFIG. 2Ais provided. The selector layer202directly contacts the bit lines104a-d, the lower isolation structure112, and the upper isolation structure114. The scavenger layer106directly contacts the selector layer202and is disposed between the selector layer202and the data storage layer108. The data storage layer108directly contacts the first word line116a.

Referring toFIG. 3B, a cross-sectional view of a memory device300bcorresponding to some alternative embodiments of the memory device300aofFIG. 3Ais provided, in which an outer scavenger layer204is disposed between the data storage layer108and the first word line116a.

Referring toFIG. 4, a cross-sectional view of a memory device400is provided, in which memory cells410are respectively configured as the first memory cell120aofFIG. 2D. The memory device400comprises twelve bit lines104and twelve memory cells410. The upper isolation structure114may, for example, comprise silicon nitride, silicon carbide, or the like. In some embodiments, the upper isolation structure114comprises a dielectric material different than the lower isolation structure112. The interconnect dielectric structure102comprises a metal etch stop layer404overlying an inter-level dielectric (ILD) layer402.

Referring toFIG. 5, a perspective view with some portions cut-away of a memory device500including thirty-six memory cells410is provided, in which the memory cells410are respectively configured as the first memory cell120aofFIG. 2C. The memory device500includes twelve rows (corresponding to the twelve bit lines104) and three columns124a-c(corresponding to the three word lines116a-c). In some embodiments, twelve bit lines104extend along a first direction and three word lines116a-cextend along a second direction, such that the first direction is orthogonal to the second direction. Portions of the second word line124band the leftmost rows have been cut-away to better illustrate some underling features of the device.

FIGS. 6-19illustrate cross-sectional views600-1900of some embodiments of a method of forming a memory device including memory cells according to the present disclosure. Although the cross-sectional views600-1900shown inFIGS. 6-19are described with reference to a method, it will be appreciated that the structures shown inFIGS. 6-19are not limited to the method but rather may stand alone separate of the method. AlthoughFIGS. 6-19are described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

As shown in cross-sectional view600ofFIG. 6, a metal etch stop layer404is formed over an inter-level dielectric (ILD) layer402. In some embodiments, the ILD layer402is a part of an interconnect structure comprising multiple layers of metal lines with conductive vias disposed between the multiple layers of metal lines (not shown). In some embodiments, the ILD layer402overlies a semiconductor substrate comprising a plurality of semiconductor devices (e.g., transistors) disposed over the semiconductor substrate (not shown). A lower bit line layer602is formed over the metal etch stop layer404. A lower isolation layer604is formed over the lower bit line layer602. An upper bit line layer606is formed over the lower isolation layer604. A first upper isolation layer608is formed over the upper bit line layer606. A second upper isolation layer610is formed over the first upper isolation layer608. A plurality of pad layers612a-care formed over the second upper isolation layer610. A masking layer614is formed over the plurality of pad layers612a-c. An upper surface of a third pad layer612cis left exposed in a plurality of sacrificial regions616, laterally offset segments of the masking layer614. In some embodiments, the above layers may be formed using a deposition process such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), some other suitable deposition process(es), or any combination of the foregoing.

In some embodiments, the ILD layer402may, for example, be or comprise an oxide, silicon oxide, a low-k dielectric, or the like. As used herein, a low-k dielectric is a dielectric material with a dielectric constant less than 3.9. The metal etch stop layer404may, for example, be or comprise silicon carbide, silicon nitride, or the like. The lower bit line layer602may, for example, be or comprise tungsten. The lower isolation layer604may, for example, be or comprise an oxide, silicon oxide, a low-k dielectric, or the like. The upper bit line layer606may, for example, be or comprise tungsten. In some embodiments, the lower bit line layer602is a same material (e.g., tungsten) as the upper bit line layer606. The first upper isolation layer608may, for example, be or comprise silicon oxide, silicon nitride, aluminum oxide, or the like. The second upper isolation layer610may, for example, be or comprise an oxide, silicon oxide, a low-k dielectric, or the like. A first pad layer612amay, for example, be or comprise nitride, silicon nitride, or the like. A second pad layer612bmay, for example, be or comprise an oxide, silicon oxide, or the like. The third pad layer612cmay, for example, be or comprise a nitride, silicon nitride, or the like. The masking layer614may, for example, be or comprise a hard mask layer, silicon oxide, silicon oxynitride, or the like.

As shown in cross-sectional view700ofFIG. 7, an etching process is performed to etch the third pad layer612cand layers underlying the third pad layer612c, defining 6 pillar structures702. The etching process is performed by exposing the layers underlying the third pad layer612cwithin the sacrificial regions (616ofFIG. 6) to one or more etchants. The etching process may, for example, be performed by a photolithography/etching process and/or some other suitable patterning process(es). In various embodiments, the etching process may comprise a single etch (i.e., a continuous etch that etches the plurality of pad layers612a-c, the first and second upper isolation layers (608,610ofFIG. 6), the upper bit line layer (606ofFIG. 6), the lower isolation layer (604ofFIG. 6), and the lower bit line layer (602ofFIG. 6)) or multiple etches performed in-situ. Etching the first and second upper isolation layers (608,610ofFIG. 6), the upper bit line layer (606ofFIG. 6), the lower isolation layer (604ofFIG. 6), and the lower bit line layer (602ofFIG. 6) define first and second isolation layers114a,114b, bit lines104, and a lower isolation structure112. In some embodiments, the etching process defines twelve bit lines104. In yet further embodiments, the pillar structures702are separated from one another by a lateral distance dps. The lateral distance dpsmay, for example, be within a range of about 40 to 100 nanometers.

As shown in cross-sectional view800ofFIG. 8, a removal process is performed to remove the first second and third pad layers (612b,612cofFIG. 7). In some embodiments, the removal process may comprise a photolithography/etching process and/or a planarization process (e.g., a chemical mechanical planarization (CMP) process) to expose an upper surface of the first pad layer612a.

As shown in cross-sectional view900ofFIG. 9, a lateral etch process is performed to reduce a width of the first and second upper isolation layers114a,114band the lower isolation structure112. In some embodiments, the lateral etch process reduces a width wiof the first and second upper isolation layers114a,114band the lower isolation structure112by approximately 5 to 40 nanometers. The lateral etch process may, for example, comprise a wet etch process.

As shown in cross-sectional view1000ofFIG. 10, conductive scavenger layers106a-care deposited on the bit lines104and the first pad layer612a. The conductive scavenger layers106a-cmay, for example, respectively be or comprise titanium nitride, or the like. The deposition process may, for example, comprise a physical vapor deposition (PVD) process of a conductive scavenger material1004(e.g., titanium nitride) at an angle α. The angle α is defined from a substantially straight vertical line1002, such that the vertical line1002is perpendicular to a top surface of the metal etch stop layer404and/or perpendicular to a top surface of an underlying semiconductor substrate (not shown). In some embodiments, the angle α is within a range of about −45 to −10 degrees and/or 10 to 45 degrees. The angle α is configured to mitigate formation of the conductive scavenger material1004on a bottom surface of each bit line104, such that the bottom surface of each bit line104is shielded from the deposition of the conductive scavenger material1004.

As shown in cross-sectional view1100ofFIG. 11, an etching process is performed to remove a portion of the conductive scavenger layers106a-c, thereby defining a scavenger layer106over and around each bit line104. In some embodiments, the etching process is a directional dry etching process. The etching process may, for example, be configured to electrically isolate a bottommost layer of bit lines104botfrom one another by removing a portion of a bottommost conductive scavenger layer (106aofFIG. 10) between the bit lines104in the bottommost layer of bit lines104bot.

As shown in cross-sectional view1200ofFIG. 12, a data storage layer108is formed over the scavenger layer106, the metal etch stop layer404, the lower isolation structure112, and the first and second upper isolation layers114a,114b. In some embodiments, the data storage layer108is formed by atomic layer deposition (ALD). The data storage layer108may, for example, be or comprise an oxide (such as titanium oxide, tantalum oxide, etc.), a high-k dielectric, or the like. As used herein, a high-k dielectric is a dielectric material with a dielectric constant greater than 3.9.

As shown in cross-sectional view1300ofFIG. 13, an outer scavenger layer204is formed over and around the data storage layer108. In some embodiments, the outer scavenger layer204may, for example, be or comprise titanium nitride, or the like. The outer scavenger layer204may, for example, be formed with a same or similar process as described inFIGS. 10 and 11, such that the outer scavenger layer204is formed in a similar manner as the scavenger layer106.

As shown in cross-sectional view1400ofFIG. 14, a selector layer202is formed over the outer scavenger layer204and the data storage layer108. The selector layer202may, for example, be or comprise a binary material such as silicon tellurium, germanium tellurium, carbon tellurium, boron tellurium, zinc tellurium, aluminum tellurium, germanium selenide, germanium antimony, selenium antimony, silicon arsenide, germanium arsenide, arsenic tellurium, boron carbide, or the like and/or may comprise N-doping, and O-doping. In further embodiments, the selector layer202may, for example, be or comprise a ternary compound such as germanium selenium arsenide, germanium selenium antimony, germanium antimony tellurium, germanium silicon arsenide, germanium arsenic antimony, selenium antimony tellurium, silicon tellurium selenium, or the like and/or may comprise N-doping, O-doping, and C-doping. In yet further embodiments, the selector layer202may, for example, be or comprise a quadruple compound such as germanium selenium arsenic tellurium, germanium selenium tellurium silicon, germanium selenium tellurium arsenide, germanium selenium arsenic antimony, germanium selenium antimony silicon, or the like and/or may comprise N-doping, O-doping, and C-doping. The selector layer202may, for example, comprise a compound with five elements. In some embodiments, the selector layer202comprises a dielectric material different than the data storage layer108. An upper inter-metal dielectric (IMD) structure126is formed over the selector layer202. The upper IMD structure126may, for example, be or comprise silicon oxide, a low-k dielectric, or the like. In some embodiments, the selector layer202and the upper IMD structure126may, for example, be formed by an ALD process.

As shown in cross-sectional view1500ofFIG. 15, a planarization process is performed on the structure ofFIG. 14until a top surface of the first pad layer612ais exposed. The planarization process may, for example, be a CMP process.

As shown in cross-sectional view1600ofFIG. 16, an etching process is performed on the structure ofFIG. 15until a top surface of the second upper isolation layer (114bofFIG. 15) is exposed, thereby defining an upper isolation structure114. The etching process removes a portion of the upper IMD structure (126ofFIG. 15), thereby exposing an upper surface of the selector layer202. The etching process may, for example, be a wet etch process.

As shown in cross-sectional view1700ofFIG. 17, a word line layer1702is formed over the selector layer202and the upper isolation structure114. The word line layer1702may, for example, be or comprise tungsten, or the like. In some embodiments, a process for forming the word line layer1702may, for example, include forming a conductive material (e.g., tungsten) over the selector layer202and the upper isolation structure114, then subsequently performing a planarization process (e.g., a CMP process) into the conductive material until reaching a top surface of the selector layer202.

As shown in cross-sectional view1800ofFIG. 18, conductive word line material (e.g., tungsten) is formed over the structure ofFIG. 17, thereby forming a first word line116a. This, in part, defines a first column124aof a memory device400and twelve memory cells410.

Referring toFIG. 19, a top view corresponding to some embodiments of the cross-sectional view1800ofFIG. 18, as indicated by the cut-away lines shown inFIGS. 18-19is provided. In some embodiments, during a formation of the first column124a, a second column124bmay be formed concurrently. The second column124bmay, for example, be formed with a same process flow as described in the formation of the first column124a. The bit lines104respectively extend in a first direction (e.g., along the z-axis), the first word line116aand a second word line116brespectively extend in a second direction (e.g., along the x-axis). In some embodiments, the first direction is orthogonal to the second direction. The first and second word lines116a,116bare laterally separated from one another by the upper IMD structure126.

At act2002, a stack of layers is formed over a substrate. The stack of layers include a lower isolation layer overlying a lower bit line layer, an upper bit line layer overlying the lower isolation layer, an upper isolation layer overlying the upper bit line layer, and a masking layer overlying the upper isolation layer.FIG. 6illustrates a cross-sectional view600corresponding to some embodiments of act2002.

At act2004, an etching process is performed according to the masking layer, thereby defining a plurality of bit lines, an upper bit line layer is separated from a lower bit line layer by the lower isolation layer.FIG. 7illustrates a cross-sectional view700corresponding to some embodiments of act2004.

At act2006, a lateral etch process is performed to reduce a width of the upper and lower isolation layers.FIG. 9illustrates a cross-sectional view900corresponding to some embodiments of act2006.

At act2008, scavenger layers are formed over a top surface and outer sidewalls of each bit line.FIGS. 10 and 11illustrate cross-sectional views1000and1100corresponding to some embodiments of act2008.

At act2010, a data storage layer is formed over the scavenger layers and the bit lines.FIG. 12illustrates a cross-sectional view1200corresponding to some embodiments of act2010.

At act2012, outer scavenger layers are formed over the data storage layer and each bit line.FIG. 13illustrates a cross-sectional view1300corresponding to some embodiments of act2012.

At act2014, a selector layer is formed over the outer scavenger layers and the data storage layer.FIG. 14illustrates a cross-sectional view1400corresponding to some embodiments of act2014.

At act2016, an inter-metal dielectric (IMD) structure is formed laterally between the bit lines.FIG. 14illustrates a cross-sectional view1400corresponding to some embodiments of act2016.

At act2018, an etching process is performed to remove a portion of the IMD structure.FIG. 16illustrates a cross-sectional view1600corresponding to some embodiments of act2018.

At act2020, a word line is formed over the plurality of bit lines, thereby defining a plurality of memory cells.FIGS. 17 and 18illustrate cross-sectional views1700and1800corresponding to some embodiments of act2020.

Accordingly, in some embodiments, the present disclosure relates to a horizontal memory array including a scavenger layer around an upper surface and sidewalls of a bit line configured to “scavenge” (i.e., collect, absorb, and/or store) oxygen from an adjacent data storage layer and direct an electric field around the bit line.

In some embodiments, the present application provides a resistive random access memory (RRAM) device including a bit line overlying a semiconductor substrate; a data storage layer around outer sidewalls and a top surface of the bit line; a word line overlying the data storage layer; and a scavenger layer between the word line and the bit line, wherein a bottom surface of the scavenger layer is aligned with a bottom surface of the bit line, wherein a lateral thickness of the scavenger layer is less than a vertical thickness of the scavenger layer.

In some embodiments, the present application provides a memory device including a bit line overlying a substrate; a word line overlying the bit line; a data storage layer between the word line and the bit line, wherein a conductive filament is selectively formable within the data storage layer between the bit line and the word line; and a scavenger layer between the word line and the bit line, wherein the scavenger layer is configured to confine the conductive filament to an upper region of the data storage layer such that the upper region is above a top surface of the bit line, wherein a vertical thickness of the scavenger layer is greater than a lateral thickness of the scavenger layer, and wherein the vertical thickness is defined above a top surface of the bit line.

In some embodiments, the present application provides a method for manufacturing a memory device, including depositing an upper bit line over a lower bit line, wherein a lower isolation structure is formed directly between the upper and lower bit lines; depositing scavenger layers around and over the upper bit line and the lower bit line; depositing a data storage layer over the upper bit line, the lower bit line, and the lower isolation layer; depositing an inter-metal dielectric (IMD) structure around the upper and lower bit lines; patterning a portion of the IMD structure; and depositing a word line over the upper bit line such that a bottom surface of the word line is below a top surface of the lower bit line.