Multichannel, self-calibrating, analog input/output apparatus for generating and measuring DC stimuli

Analog input/output apparatus includes a plurality of digital to analog converters (18, 20, 22, 24, 26) and a plurality of interfacing means (4, 6, 8, 10, 12, 14, 16) for interfacing the converters with a central processing unit (2). A plurality of current and voltage sources (28, 30, 32, 34, 36, 38, 40, 42) are connected to the converters for providing a plurality of voltage and current stimuli signals and monitor signals. A signal measurement channel (44, 46, 48, 52) is responsive to the monitor signals and is controlled by the interfacing means (4-16), and multiplexers (44, 46) are wrapped around the measurement channel to provide a self-calibration channel (50). The central processing unit is responsive to the self-calibration channel output for determining the correction to be applied to the stimuli signals.

BACKGROUND OF THE INVENTION 
Automatic test equipment such as used, for example, in testing aircraft 
engine and/or flight parameters uses DC stimuli signals which must be 
generated with a high degree of accuracy. Accordingly, apparatus for 
generating said stimuli signals should include signal measurement and 
self-calibration features. 
Prior to the present invention, calibration means for apparatus of the type 
described required precision analog to digital converters for these 
purposes and a correction was applied by measuring a reference voltage 
error and offset. This arrangement has, among others, the disadvantage of 
not correcting for output non-linearity. The present invention overcomes 
the disadvantages of the prior art by amplifying existing errors and 
measuring the errors using conventional analog to digital converters. The 
measured errors are reduced via a least square error reduction 
arrangement, based on a minimum number of error measurements to accomplish 
the required calibration. A central processing unit (CPU) determines the 
offset and gain correction to be applied. 
SUMMARY OF THE INVENTION 
This invention contemplates apparatus including a plurality of channels for 
precisely generating and measuring DC current and voltage stimuli signals 
and includes a calibration arrangement based on least square error 
reduction principles. 
The generated signals are measured either single ended or differentially 
with a high degree of accuracy. The plurality of signal generating 
channels are dual range; have high and low power capabilities; are 
bi-directional; and are ground referenced. The signal generating channels 
are wrapped around a measurement channel to impart a built-in test 
capability to the apparatus. The accuracy of the signal generating 
channels is enchanced by a high gain measurement arrangement whereby 
signal errors are amplified for calibration via a central processing unit.

DETAILED DESCRIPTION OF THE INVENTION 
With reference to FIG. 1, a central processing unit (CPU) 2 is connected 
via an input/output bus 4 to digital circuitry 8. Digital circuitry 8 
provides a controlling output for controlling a select logic device 6, 
which provides logic outputs S.sub.0, S.sub.1, S.sub.2, S.sub.3 and 
S.sub.4. 
Digital circuitry 8 provides a sixteen bit controlling output, eight bits 
of which control programmable peripheral input/output interfaces 10, 12, 
14, and 16. Interface 10 provides eight bit outputs 10A, 10B, and 10C; 
interface 12 provides eight bit outputs 12A, 12B and 12C; interface 14 
provides eight bit outputs 14A, 14B and 14C; and interface 16 provides 
eight bit outputs 16A, 16B and 16C. 
A digital to analog converter 18 is connected to a positive (+) 10 volt 
reference source and receives logic signals S.sub.1, S.sub.2, S.sub.3 and 
S.sub.4 from select logic device 6. The logic signals are at a logic "low" 
level so as to enable digital to analog converter 18. Digital to analog 
converter 18 is controlled by twelve bits of the sixteen bit output from 
digital circuitry 8. 
A digital to analog converter 20 receives signals 10A and 12A (sixteen 
bits) from the respective interfaces 10 and 12; a digital to analog 
converter 22 receives signals 10B and 12B (sixteen bits) from the 
respective interfaces 10 and 12; a digital to analog converter 24 receives 
signals 14A and 16A (sixteen bits) from the respective interfaces 14 and 
16; and a digital to analog converter 26 receives signals 14B and 16B 
(sixteen bits) from the respective interfaces 14 and 16. 
Digital to analog converter 20 is connected to a voltage to current 
converter 28, and digital to analog converter 18 is connected to a voltage 
to current converter 30 and is connected to a voltage to current converter 
32. Digital to analog converter 18 is further connected to a power 
amplifier 34 and to a power amplifier 36. Digital to analog converter 22 
is connected to a power amplifier 38; digital to analog converter 24 is 
connected to a power amplifier 40; and digital to analog converter 26 is 
connected to a power amplifier 42. In this connection it will be 
understood that voltage to current converter or current source 28 is a 
sixteen bit device; voltage to current converters or current sources 30 
and 32 are twelve bit devices; and amplifiers or voltage sources 34 and 36 
are twelve bit devices; and amplifiers or voltage sources 38, 40 and 42 
are sixteen bit devices. 
Current sources 28, 30 and 32 and voltage sources 34, 36, 38, 40 and 42 
receive inputs from programmable peripheral interface 10 and digital 
circuitry 8. As heretofore noted, each of the signals 10A, 10B and 10C 
provided by interface 10 is an eight bit signal. Each of the current and 
voltage sources receives one of the eight bits of signal 10C provided by 
interface 10. Thus, current sources 28, 30 and 32 receive bits 10C.sub.0, 
10C.sub.1, and 10C.sub.2, respectively, and voltage sources 34, 36, 38, 40 
and 42 receive bits 10C.sub.3, 10C.sub.4, 10C.sub.5, 10C.sub.6 and 
10C.sub.7, respectively. 
It should be noted that current sources 28, 30 and 32 are devices of the 
type having (+) or (-) 25 volts compliance and are dual range; i.e., 
.+-.50 milliamperes and .+-.2 milliamperes. The current sources can drive 
ground reference loads and open circit compliance is clamped to 30.5 volts 
maximum. Voltage sources 34, 36, 38, 40 and 42 are dual range; i.e., 
.+-.30 volts and .+-.10 volts, at a 50 milliampere output range. 
It will now be understood with reference to FIG. 1 that current sources 28, 
30, and 32 and voltage sources 34, 36, 38, 40 and 42 are interfaced to the 
digital world through digital to analog converters 18, 20, 22, 24, and 26. 
Interfacing to bus 4 is achieved through programmable peripheral 
interfaces 10, 12, 14, and 16, select logic device 6 and digital circuitry 
8. 
In accordance with the above, current sources 28, 30 and 32 provide DC 
current stimuli signals I.sub.0 (28), I.sub.0 (30) and I.sub.0 (32), 
respectively, and provide DC current monitor signals I.sub.m (28), I.sub.m 
(30) and I.sub.m (32), respectively. Voltage sources 34, 36, 38, 40 and 42 
provide DC voltage stimuli signals E.sub.0 (34), E.sub.0 (36), E.sub.0 
(38), E.sub.0 (40) and E.sub.0 (42), respectively, and provide DC voltage 
monitor signals E.sub.M (34), E.sub.M (36), E.sub.M (38), E.sub.M (40), 
E.sub.M (42), respectively. 
With reference to FIG. 2, a twelve bit signal measurement channel with a 
gain of 1 and 500 includes multiplexers 44 and 46, an amplifier 48 and an 
analog to digital converter 50. Self-test channels are wrapped around the 
measurement channel, using multiplexers 44 and 46 as will be hereinafter 
explained. 
Thus, multplexer 44 is connected to programmable peripheral interface 14 
and receives four of the bits of eight bit output 14C therefrom. 
Multiplexer 14 receives output bits 14C.sub.0, 14C.sub.1, 14C.sub.2 and 
14C.sub.6. Multiplexer 44 is connected to a positive (+) 10 volt reference 
source and to a negative (-) 10 volt reference source; and is connected to 
a pair of external measurement inputs, namely input (+) and input return 
(-), as indicated in the Figure. Multiplexer 44 receives monitor signals 
I.sub.m (28), I.sub.m (30), I.sub.m (32) and E.sub.m (34). 
Multiplexer 46 is connected to programmable peripheral interface 14 and 
receives the remaining four bits of signal 14C therefrom. Multiplexer 46 
receives bits 14C.sub.3, 14C.sub.4, 14C.sub.5 and 14C.sub.7. Multiplexer 
46 is connected to a positive (+) 10 volt reference source and to a 
negative 10 (-) volt reference source; and is connected to a pair of 
external measurement negative inputs, namely input (-) and input return 
(+), as indicated in the Figure. Multiplexer 48 receives monitor signals 
E.sub.m (36), E.sub.m (38) E.sub.m (40) and E.sub.m (42). 
Multiplexer 44 is connected to the non-inverting input terminal (+) of 
amplifier 48 and multiplexer 46 is connected to the inverting input 
terminal (-) of the amplifier. Amplifier 48 is connected to analog to 
digital converter 50 which receives signal S.sub.0 at a logic "high" level 
from select logic device 6. 
An analog relay designated generally by the numeral 52 is responsive to bit 
16C.sub.0 of output signal 16C from programmable peripheral interface 16 
so as to selectively switch a pair of gain selection resistors 54 and 56, 
into the amplifier input to provide the aforenoted gain of 1 and 500, 
respectively, as the case may be. 
Thus, single ended or differential measurements with a gain of 1 and 500 
are made through amplifier 48 and multiplexers 44 and 46. The gain of 500 
is used to amplify errors for calibration purposes. 
All voltage and current stimuli signals are thus monitored through 
multiplexers 44 and 46. Programmable peripheral interface 14 controls the 
operation and range selection of voltage to current converters 28, 30 and 
32 and power amplifiers 34, 36, 38, 40 and 42. All outputs are wrapped 
around the measurement channel through multiplexers 44 and 46 to provide a 
built-in test capability. Converter 50 provides a twelve bit measurement 
signal D.sub.m having bits D.sub.0 and D.sub.11 and provides a signal 
D.sub.c which is applied to digital circuitry 8 (FIG. 1) and therefrom to 
CPU 2 via bus 4 which calculates an appropriate correction. 
As further illustrated in FIG. 2, error measurements are made at positive 
full scale (+10) negative full scale (-10) and zero output voltages by the 
twelve bit measurement channel after error amplification by a factor of 
500. Based on these measurements CPU 2 (FIG. 1) calculates two constants, 
K.sub.g and K.sub.o, where K.sub.g is a gain constant and K.sub.o is an 
offset constant. The correction to be applied is given by the following 
equation: 
EQU .delta..sub..eta. =K.sub.o +K.sub.g x. 
With reference to FIG. 3, input/output combinations at which error 
measurements are made are tabulated as follows: 
______________________________________ 
.eta. -10 V 0 V +10 V. 
______________________________________ 
y y.sub.1 y.sub.2 
y.sub.3 
______________________________________ 
The least square error (best fit output) line is given as: 
EQU y=a+b(.eta.-.eta.), 
and, since .eta.=0, 
EQU y=a+b.eta., 
where: 
EQU a=y=(y.sub.1 +y.sub.2 +y.sub.3)/3; (1) 
and: 
##EQU1## 
Let x' be the correction for x as shown in FIG. 3. Note that the (-y) 
values are the same for both the best fit output line and the ideal output 
line, i.e., y=.eta. and y=a+b.eta.. Hence: 
EQU a+b.eta.'=x; 
and 
EQU x'=(.eta.-a)1/b, 
where a and b are given by equations (1) and (2). 
Let error measurements be y.sub.1 ', y.sub.2 ' and y.sub.3 ', corresponding 
to output y.sub.1, y.sub.2, and y.sub.3. Since the error measurements are 
made with respect to -10 volts, zero volts and +10 volts for y.sub.1 ', 
y.sub.2 ', and y.sub.3 ', respectively, and since the error measurements 
are amplified by gain G of amplifier 48 (FIG. 2): 
EQU y.sub.1 '=(y.sub.1 +10)G; y.sub.1 =y.sub.1 '/G-10, (3) 
EQU y.sub.2 '=y.sub.2 G; y.sub.2 =y.sub.2 '/G; and (4) 
EQU y.sub.3 '=(y.sub.3 -10)G; y.sub.3 =y.sub.3 '/G+10. (5) 
Substituting for a and b, using equations (1), (2), (3), (4) and (5) gives 
the correction to be subtracted from each input code: 
##EQU2## 
With the aforegoing description of the invention in mind, reference is made 
to the claims appended hereto for a definition of the scope of the 
invention.