BIT-LINE RESISTANCE REDUCTION

The present disclosure relates integrated chip structure. The integrated chip structure includes a memory array having a plurality of memory devices arranged in a plurality of rows and a plurality of columns. A word-line is coupled to a first set of the plurality of memory devices disposed within a first row of the plurality of rows. A bit-line is coupled to a second set of the plurality of memory devices disposed within a first column of the plurality of columns. A local interconnect extends in parallel to the bit-line and is coupled to the bit-line and two or more of the second set of the plurality of memory devices. The local interconnect is coupled to the bit-line by a plurality of interconnect vias that are between the local interconnect and the bit-line.

BACKGROUND

Many modern day electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data when it is powered, while non-volatile memory is able to store data when power is removed. Magneto-resistive random-access memory (MRAM) is one promising candidate for a next generation non-volatile memory technology.

DETAILED DESCRIPTION

Magneto-resistive random-access memory (MRAM) cells comprise a magnetic tunnel junction (MTJ) arranged between conductive electrodes. The MTJ comprises a pinned layer separated from a free layer by a tunnel barrier layer. The magnetic orientation of the pinned layer is static (i.e., fixed), while the magnetic orientation of the free layer is capable of switching between a parallel configuration and an anti-parallel configuration with respect to that of the pinned layer. The parallel configuration provides for a low resistance state that digitally stores data as a first bit value (e.g., a logical “1”). The anti-parallel configuration provides for a high resistance state that digitally stores data as a second bit value (e.g., a logical “0”).

MRAM devices may be arranged on an integrated chip structure in an array comprising rows and columns. MRAM devices within a row are operably coupled to a word-line that is further coupled to a word-line decoder. MRAM devices within a column are operably coupled to bit-lines that are further coupled to a bit-line decoder. During operation, the word-line decoder and the bit-line decoder are configured to selectively apply signals to the word-lines and bit-lines. By selectively applying signals to the word-lines and bit-lines, data can be written to and/or read from different ones of the MRAM devices within an array.

As a functionality of integrated chips has increased, the need for more memory has also increased, causing integrated chip designers and manufacturers to increase the amount of available memory. To reach this goal, a size of memory arrays may be increased, thereby increasing a length of word-lines and/or bit-lines within an array. Furthermore, a size of memory array components may also be decreased, thereby decreasing a size (e.g., a width and/or height) of the word-lines and bit-lines. However, increasing a length of the word-lines and bit-lines and/or reducing a size of the word-lines and bit-lines causes a resistance of the word-lines and bit-lines to increase (since R=ρ*L/A, where R is resistance, ρ is resistivity, L is a length, and A is a cross-sectional area). Increasing the resistance of the word-lines and/or bit-lines can decrease performance of a memory array. For example, increasing a resistance of a bit-line may increase a variation in read signals received from different parts of an array and/or driving signals provided to different parts of the array. The increased variations may reduce a memory window (e.g., a difference between signals output from an MRAM device in a low resistance state and a high resistance state) of a memory array and ultimately lead to errors in reading and/or writing data.

The present disclosure relates to an integrated chip structure comprising a memory array having a local interconnect that is configured to reduce a resistance of a bit-line within the memory array. In some embodiments, the integrated chip structure may comprise a memory array having a plurality of memory devices. The plurality of memory devices are arranged in a plurality of rows and a plurality of columns. A word-line is operably coupled to a first set of the plurality of memory devices disposed within a first row of the plurality of rows. A bit-line is operably coupled to a second set of the plurality of memory devices disposed within a first column of the plurality of columns. A local interconnect extends in parallel to the bit-line and is coupled between the bit-line and two or more of the second set of the plurality of memory devices. Because the local interconnect is coupled to and extends in parallel to the bit-line, the local interconnect is able to reduce a resistance of first bit-line. By reducing a resistance of the bit-line, the local interconnect is able to improve a performance of the integrated chip structure.

FIG.1Aillustrates a schematic diagram100of some embodiments of an integrated chip structure comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line.

As shown in the schematic diagram100, the integrated chip structure comprises a memory array102including a plurality of memory cells103arranged within rows and/or columns. The plurality of memory cells103comprise memory devices104and access devices106configured to control access to the memory devices104. A first set of the plurality of memory devices104within a row respectively have access devices106that are operably coupled to a word-line108. A second set of the plurality of memory devices104within a column are operably coupled to a bit-line110. In some embodiments, the second set of the plurality of memory devices104within the column may have access devices106that are further coupled to a source-line112. The word-line108and the bit-line110are coupled to control circuitry114, which is configured to selectively apply signals to the word-line108and/or the bit-line110to access (e.g., write data to and/or read data from) one or more of the plurality of memory devices104.

A local interconnect116extends in parallel to the bit-line110. The local interconnect116is coupled between the bit-line110and two or more of the second set of the plurality of memory devices104within the column of the memory array102. Because the local interconnect116is coupled to and extends in parallel to the bit-line110, the local interconnect116is able to provide an alternative path for signals that are applied to the bit-line110by way of the control circuitry114. By providing an alternative path for signals that are applied to the bit-line110, the local interconnect116is able to reduce a resistance of the bit-line110. By reducing a resistance of the bit-line110, the local interconnect116is able to improve a performance (e.g., a memory window) of the memory array102.

FIG.1Billustrates a cross-sectional view120of some embodiments of an integrated chip structure corresponding to section118of the schematic diagram100shown inFIG.1A.

As shown in cross-sectional view120, the integrated chip structure comprises an embedded memory region124and a peripheral region136(e.g. a logical region comprising one or more transistor devices configured to perform logical functions). A memory array102is disposed within the embedded memory region124. The memory array102comprises a plurality of memory devices104disposed within a dielectric structure126over a substrate122. The plurality of memory devices104respectively comprise a data storage structure104bdisposed been a bottom electrode104aand a top electrode104c. In some embodiments, the dielectric structure126comprises a lower inter-level dielectric (ILD) structure126L and an upper ILD structure126U over the lower ILD structure126L.

In some embodiments, a plurality of access devices106are disposed within the embedded memory region124. In some embodiments, the plurality of access devices106are coupled to the plurality of memory devices104by way of a plurality of lower interconnects128within the lower ILD structure126L. In some additional embodiments, one or more transistor devices138are disposed within the peripheral region136. The one or more transistor devices138may be part of a control circuitry114configured to selectively apply signals to the one or more memory devices104.

A local interconnect116is arranged within the upper ILD structure126U and extends in parallel to the bit-line110. The local interconnect116is coupled to the plurality of memory devices104. The local interconnect116is further coupled to an overlying bit-line110by way of a plurality of interconnect vias130that are directly between the local interconnect116and the bit-line110. In some embodiments, the local interconnect116has a first length132(e.g., measured along a longest dimension of the local interconnect116) and the bit-line110has a second length134(e.g., measured along a longest dimension of the bit-line110) that is greater than the first length132. In some embodiments, the bit-line110extends past one end of the local interconnect116. In some additional embodiments, the bit-line110extends past opposing ends of the local interconnect116.

The bit-line110extends from within the embedded memory region124to within the peripheral region136. The bit-line110is coupled to the control circuitry114, by way of one or more peripheral interconnects140. In some embodiments, the one or more peripheral interconnects140may comprise an interconnect via and/or an interconnect wire. In some alternative embodiments (not shown), the bit-line110may be coupled to a voltage source that is disposed within the dielectric structure126over the bit-line110. In some embodiments, the bit-line110extends to within the peripheral region136of the substrate122and the local interconnect116is confined within the embedded memory region124of the substrate122. Confining the local interconnect116within the embedded memory region124provides space within the peripheral region136for other interconnect routing.

During operation, the control circuitry114is configured to perform an access operation (e.g., a read operation or a write operation) on one of the plurality of memory devices104by selectively applying a signal142(e.g., a read current, a driving current, or the like) to the bit-line110. Typically, a resistance of the bit-line110will be proportional to the second length134of the bit-line110divided by a cross-sectional area of the bit-line110(since R=ρ*L/A). However, because the local interconnect116is coupled to the bit-line110by way of the plurality of interconnect vias130, the signal132has multiple parallel paths between the control circuitry114and the plurality of memory devices104. The multiple parallel paths provide for a larger cumulative cross-sectional area for a signal142to travel through, thereby reducing a resistance of the bit-line110. By reducing a resistance of the bit-line110, a performance (e.g., a memory window) of the integrated chip structure can be improved.

FIG.2illustrates a cross-sectional view of some additional embodiments of an integrated chip structure200comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line.

The integrated chip structure200comprises an embedded memory region124and a peripheral region136. A memory array102is disposed within the embedded memory region124. The memory array102comprises a plurality of memory devices104disposed within a dielectric structure126over a substrate122. The plurality of memory devices104respectively comprise a data storage structure104bdisposed between a bottom electrode104aand a top electrode104c. In some embodiments, the bottom electrode104aand the top electrode104cmay comprise a metal, such as tantalum, titanium, tantalum nitride, titanium nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, or the like.

In some embodiments, the dielectric structure126comprises a lower ILD structure126L and an upper ILD structure126U. The lower ILD structure laterally surrounds a plurality of lower interconnects128. In some embodiments, the plurality of lower interconnects128may comprise conductive contacts, interconnect wires, and/or interconnect vias including one or more of copper, aluminum, tungsten, ruthenium, or the like. The upper ILD structure126U laterally surrounds the plurality of memory devices104. In some embodiments, the lower ILD structure126L and/or the upper ILD structure126U may comprise one or more of silicon dioxide, carbon doped silicon oxide (SiCOH), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), borosilicate glass (BSG), fluorosilicate glass (FSG), undoped silicate glass (USG), or the like.

In some embodiments, a plurality of access devices106are disposed within the embedded memory region124and are coupled to the plurality of memory devices104by way of the plurality of lower interconnects128. In some embodiments, the plurality of access devices106may respectively comprise a MOSFET device having a gate structure106cthat is laterally arranged between a source region106aand a drain region106b. In some embodiments, the gate structure106cmay comprise a gate electrode that is separated from the substrate122by a gate dielectric. In some embodiments, the source region106ais coupled to a source-line112and the gate structure106cis coupled to a word-line108. In various embodiments, the MOSFET device may comprise a planar FET, a FinFET, a gate-all-around (GAA) device, or the like. In other embodiments, the access device106may comprise a HEMT (high-electron-mobility transistor), a BJT (bipolar junction transistor), a JFET (junction-gate field-effect transistor), or the like.

In some embodiments, the lower ILD structure126L is separated from the upper ILD structure126U by way of a lower insulating structure202. A bottom electrode via204extends through the lower insulating structure202to couple the plurality of memory devices104to the plurality of lower interconnects128. In some embodiments, the lower insulating structure202may comprise one or more dielectric layers stacked onto one another. In various embodiments, the one or more dielectric layers may comprise one or more of silicon rich oxide, silicon carbide, silicon dioxide, silicon nitride, or the like.

A local interconnect116is arranged within the upper ILD structure126U and is coupled to the plurality of memory devices104. The local interconnect116is further coupled to an overlying bit-line110by way of a plurality of interconnect vias130. The local interconnect116extends in parallel to the bit-line110and is coupled between the bit-line110and the plurality of memory devices104. In some embodiments, the local interconnect116continuously extends laterally past the plurality of memory devices104and the plurality of interconnect vias130. In some embodiments, the bit-line110comprises a bottom surface that continuously extends laterally past both the plurality of interconnect vias130and the local interconnect116. In some embodiments, the plurality of interconnect vias130are arranged in an array that laterally extends past two or more of the plurality of memory devices104, so that the plurality of interconnect vias130laterally extend past the two or more of the plurality of memory devices104. In some embodiments (not shown), the memory array102comprises one or more additional memory devices that are laterally outside of the local interconnect116and directly below the bit-line110. In such embodiments, the memory array102extends laterally past one or more outer edges of the local interconnect116.

In some embodiments, the plurality of interconnect vias130have bottom surfaces that physically contact the local interconnect116and top surfaces that physically contact the bit-line110. In some such embodiments, the local interconnect116and the bit-line110may be disposed on neighboring interconnect wire layers of a back-end-of-the-line (BEOL) stack. For example, the local interconnect116may be disposed on a sixth interconnect wire layer (e.g., an interconnect wire layer that is a sixth interconnect wire layer above the substrate122), while the bit-line110may be disposed on a seventh interconnect wire layer (e.g., an interconnect wire layer that is a seven interconnect wire layer above the substrate122).

FIG.3illustrates a cross-sectional view of some additional embodiments of an integrated chip structure300comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line.

The integrated chip structure300comprises an embedded memory region124and a peripheral region136. A memory array102is disposed within the embedded memory region124. The memory array102comprises a plurality of memory devices104disposed within a dielectric structure126over a substrate122. A local interconnect116is arranged within the dielectric structure126directly over the plurality of memory devices104. The local interconnect116is coupled to the plurality of memory devices104. The local interconnect116is further coupled to an overlying bit-line110by way of a plurality of interconnect vias130, a plurality of interconnect islands304, and a plurality of additional upper interconnect vias306.

The plurality of interconnect vias130have bottom surfaces that physically contact the local interconnect116and top surfaces that physically contact the plurality of interconnect islands304. The plurality of additional upper interconnect vias306have bottom surfaces that physically contact the plurality of interconnect islands304and top surfaces that physically contact the bit-line110. The plurality of interconnect islands304have bottom surfaces that laterally extend past one or more outer edges of the plurality of interconnect vias130, and top surfaces that laterally extend past one or more outer edges of the plurality of additional upper interconnect vias306. In some embodiments, the plurality of interconnect islands304have outer edges that are directly over a top surface of the local interconnect116and that are separated from one another by one or more non-zero distances308that are over the top surface of the local interconnect116.

By having the plurality of interconnect islands304disposed between the local interconnect116and the bit-line110, a distance between the local interconnect116and the bit-line110is increased thereby reducing a capacitance on the bit-line110and improving a performance of the integrated chip structure300. Furthermore, the plurality of interconnect islands304allow for the bit-line110to be formed on a relatively large interconnect wire layer (e.g., comprising a greater height and/or width than the bit-line110shown inFIG.2). Forming the bit-line110on a relatively large interconnect wire layer will give the bit-line110a relatively low resistance that will further improve the performance of the integrated chip structure300.

FIG.4illustrates a schematic diagram400of some additional embodiments of an integrated chip structure comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line.

As shown in the schematic diagram400, the integrated chip structure comprises a memory array102including a plurality of memory cells103arranged within rows and/or columns. The plurality of memory cells103comprise a plurality of memory devices104and a plurality of access devices106configured to control access to the plurality of memory devices104. A first set of the plurality of memory devices104within a row respectively have access devices106that are operably coupled to one of a plurality of word-lines108a-108n. A second set of the plurality of memory devices104within a column are operably coupled to one of a plurality of bit-lines110a-110n. In some embodiments, the plurality of memory devices104within the column comprise access devices106that are further coupled to one of a plurality of source-lines112a-112n.

A plurality of local interconnects116a-116nextends in parallel to the plurality of bit-lines110a-110n. The plurality of local interconnects116a-116nare coupled between one of the plurality of bit-lines110a-110nand two or more of plurality of memory devices104within the column of the memory array102. The plurality of word-lines108a-108n, the plurality of bit-lines110a-110n, and/or the plurality of source-lines112a-112nare further coupled to control circuitry114. In some embodiments, the control circuitry114comprises a word-line decoder402coupled to the plurality of word-lines108a-108n, a bit-line decoder404coupled to the plurality of bit-lines110a-110n, and/or a source-line decoder406coupled to the plurality of source-lines112a-112n. In some embodiments, the control circuitry114further comprises a control unit410coupled to the word-line decoder402, the bit-line decoder404, and/or the source-line decoder406.

During operation, the control circuitry114is configured to provide address information SADRto the word-line decoder402, the bit-line decoder404, and/or the source-line decoder406. Based on the address information SADR, the word-line decoder402is configured to selectively apply a bias voltage to one of the plurality of word-lines108a-108n. Concurrently, the bit-line decoder404is configured to selectively apply a bias voltage to one of the plurality of bit-lines110a-110nand/or the source-line decoder406is configured to selectively apply a bias voltage to one of the plurality of source-lines112a-112n. By applying bias voltages to selective ones of the plurality of word-lines108a-108n, the plurality of bit-lines110a-110n, and/or the plurality of source-lines112a-112n, the control circuitry114can be operated to write different data states to and/or read data states from the plurality of memory cells103.

In some embodiments, the control circuitry114further comprises a sense amplifier408coupled to the plurality of bit-lines110a-110n. During a read operation, the plurality of bit-lines110a-110nare configured to provide a read signal (e.g., a read current and/or voltage) to the sense amplifier408. The sense amplifier408is configured to compare the read signal to a reference signal to determine a data state within an accessed memory device. Because the plurality of local interconnects116a-116nare coupled in parallel to the plurality of bit-lines110a-110n, the plurality of bit-lines110a-110nwill have a lower resistance that mitigates degradation of the read signal.

FIG.5illustrates a cross-sectional view of some additional embodiments of an integrated chip structure500comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line.

The integrated chip structure500comprises an embedded memory region124and a peripheral region136. A memory array102is disposed within the embedded memory region124. The memory array102comprises a plurality of memory devices104disposed within a dielectric structure126over a substrate122. In some embodiments, the dielectric structure126comprises a lower ILD structure126L separated from an upper ILD structure126U by a lower insulating structure202. The lower ILD structure126L surrounds a plurality of lower interconnects128. In some embodiments, the plurality of memory devices104may be disposed over the lower insulating structure202and be surrounded by the upper ILD structure126U. In some embodiments, the upper ILD structure126U may comprise a plurality of upper ILD layers126U1-126U3stacked onto one another.

In some embodiments, the lower insulating structure202comprises a first lower insulating layer501arranged within the embedded memory region124and the peripheral region136. The lower insulating structure202may further comprise a second lower insulating layer502disposed over the first lower insulating layer501and a third lower insulating layer504disposed over the second lower insulating layer502. In some embodiments, the second lower insulating layer502and the third lower insulating layer504are confined within the embedded memory region124.

A bottom electrode via204extends through the lower insulating structure202between the plurality of lower interconnects128and the plurality of memory devices104. In some embodiments, the bottom electrode via204may comprise a diffusion barrier layer514and a conductive core512surrounded by the diffusion barrier layer514. In some embodiments, the diffusion barrier layer514may comprise one or more of titanium, titanium nitride, tantalum, tantalum nitride, or the like. In some embodiments, the conductive core512may comprise one or more of aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, or the like.

In some embodiments, the plurality of memory devices104respectively comprise a data storage structure104bdisposed been a bottom electrode104aand a top electrode104c. In some embodiments, the data storage structure104bmay comprise a magnetic tunnel junction (MTJ). In such embodiments, the data storage structure104bmay comprise a pinned layer516separated from a free layer520by a dielectric tunnel barrier518. The pinned layer516has a magnetization that is fixed, while the free layer520has a magnetization that can be changed during operation (through the tunnel magnetoresistance (TMR) effect) to be either parallel (i.e., a ‘P’ state) or anti-parallel (i.e., an ‘AP’ state) with respect to the magnetization of the pinned layer516. A relationship between the magnetizations of the pinned layer516and the free layer520define a resistive state of the MTJ and thereby enables the MTJ to store a data state.

Sidewall spacers505may be disposed along sidewalls of the lower insulating structure202and the plurality of memory devices104. In some embodiments, the sidewall spacers505may comprise a first sidewall spacer layer506and a second sidewall spacer layer508over the first sidewall spacer layer506. In some embodiments, the top electrode104cprotrudes outward from a top of the sidewall spacers505. In some embodiments, the first sidewall spacer layer506and/or the second sidewall spacer layer508may comprise an oxide (e.g., silicon rich oxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. A dielectric encapsulation structure510is disposed on the sidewall spacers505and a first upper ILD layer126U1is arranged on and around the dielectric encapsulation structure510.

An upper-level etch stop dielectric layer524is arranged over the first upper ILD layer126U1. In various embodiments, the upper-level etch stop dielectric layer524comprises silicon nitride, silicon carbide, silicon nitride carbide, aluminum nitride, a metal oxide (such as aluminum oxide, titanium oxide, tantalum oxide, etc.), or the like. In some embodiments, the upper-level etch stop dielectric layer524physically contacts a top surface of the first upper ILD layer126U1. In various embodiments, the upper-level etch stop dielectric layer524may have a thickness525that is in a range of between approximately 4 nanometers (nm) and approximately 20 nm, between approximately 10 nm and approximately 15 nm, approximately 12.5 nm, or other similar values.

A first dielectric matrix layer526is disposed over the upper-level etch stop dielectric layer524and a second dielectric matrix layer528is disposed over the first dielectric matrix layer526. In some embodiments, the first dielectric matrix layer526may include, for example, silicon nitride, silicon carbide, silicon nitride carbide, aluminum nitride, a metal oxide (such as aluminum oxide, titanium oxide, tantalum oxide, etc.), or the like. In some embodiments, the second dielectric matrix layer528may include, for example, Tetraethyl orthosilicate (TEOS), USG, BPSG, FSG, PSG, BSG, or the like. In some embodiments, a cumulative thickness of the first dielectric matrix layer526and the second dielectric matrix layer528may be in a range of between approximately 15 nm and approximately 60 nm, between approximately 20 nm and approximately 40 nm, or other similar values. In some embodiments, the first dielectric matrix layer526may have a thickness527that is in a range of between approximately 4 nm and approximately 8 nm, approximately 6 nm, or other similar values. In some embodiments, the second dielectric matrix layer528may have a thickness529that is in a range of between approximately 10 nm and approximately 20 nm, approximately 16 nm, or other similar values.

A common electrode522is disposed within the upper-level etch stop dielectric layer524and the at least one dielectric matrix layer526-528. The common electrode522continuously extends over the plurality of memory device104. In some embodiments, the common electrode522continuously extends past outermost edges of the plurality of memory devices104. In some embodiments, the common electrode522directly physically contacts the top electrodes104cof the plurality of memory devices104.

A cap-level etch stop dielectric layer530is arranged over the least one dielectric matrix layer526-528and the common electrode522. In some embodiments, the cap-level etch stop dielectric layer530includes silicon nitride, silicon carbide, silicon nitride carbide, aluminum nitride, a metal oxide (such as aluminum oxide, titanium oxide, tantalum oxide, etc.), or the like. In some embodiments, the cap-level etch stop dielectric layer530may physically contact a top surface of the at least one dielectric matrix layer526-528. In some embodiments, the cap-level etch stop dielectric layer530may have a thickness531that is in a range of between approximately 4 nm and approximately 20 nm, between approximately 10 nm and approximately 15 nm, approximately 12.5 nm, or other similar values.

An upper-level dielectric layer532is disposed on the cap-level etch stop dielectric layer530. The upper-level dielectric layer532may include TEOS, USG, BPSG, FSG, PSG, BSG, or the like. In some embodiments, a thickness533of the upper-level dielectric layer532may be in a range of between approximately 5 nm and approximately 20 nm, between approximately 8 nm and approximately 12 nm, approximately 10 nm, or other similar values. A plurality of local interconnect vias534are disposed within the cap-level etch stop dielectric layer530and the upper-level dielectric layer532. The plurality of local interconnect vias534contact a top of the common electrode522.

A second upper ILD layer126U2is arranged on the upper-level dielectric layer532. A local interconnect116is disposed within the second upper ILD layer126U2. A plurality of interconnect vias130are disposed on the local interconnect116and are surrounded by a third upper ILD layer126U3. The plurality of interconnect vias130couple the local interconnect116to a bit-line110that is within the third upper ILD layer126U3. In various embodiments, the second upper ILD layer126U2and/or the third upper ILD layer126U3may comprise USG, BPSG, FSG, PSG, BSG, or the like. In various embodiments, the local interconnect116, the plurality of interconnect vias130, and/or the bit-line110may comprise aluminum, copper, tungsten, and/or the like.

In some embodiments, a peripheral interconnect via536is arranged within the peripheral region136of the substrate122. The peripheral interconnect via536is disposed within the dielectric structure126outside of the memory array102. The peripheral interconnect via536vertically extends past at least a part of the common electrode522and the plurality of local interconnect vias534.

FIG.6Aillustrates a cross-sectional view of some additional embodiments of an integrated chip structure600comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line.

The integrated chip structure600comprises an embedded memory region124and a peripheral region136. A memory array102is disposed within the embedded memory region124. The memory array102comprises a plurality of memory devices104disposed within a first upper ILD layer126U1of a dielectric structure126over a substrate122. A local interconnect116is arranged within a second upper ILD layer126U2and is coupled to the plurality of memory devices104by way of a common electrode522and a plurality of local interconnect vias534. The local interconnect116continuously extends laterally past the plurality of memory devices104.

The local interconnect116is coupled to an overlying bit-line110by way of a plurality of interconnect vias130, a plurality of interconnect islands304, and a plurality of additional upper interconnect vias306. The plurality of interconnect vias130physically contact the local interconnect116and the plurality of interconnect islands304. The plurality of additional upper interconnect vias306physically contact the plurality of interconnect islands304and the bit-line110. In some embodiments, the plurality of interconnect vias130and the plurality of interconnect islands304are disposed within a third upper ILD layer126U3, while the plurality of additional upper interconnect vias306and the bit-line110are disposed within a fourth upper ILD layer126U4.

In some embodiments, the plurality of interconnect vias130may have a first height125that is in a range of between approximately 25 nm and approximately 100 nm, between approximately 50 nm and approximately 90 nm, or other similar values. In some embodiments, the plurality of interconnect islands304may have a second height305that is in a range of between approximately 25 nm and approximately 100 nm, between approximately 50 nm and approximately 90 nm, or other similar values. In some embodiments, the plurality of additional upper interconnect vias306may have a third height307that is in a range of between approximately 40 nm and approximately 130 nm, between approximately 50 nm and approximately 120 nm, or other similar values. In some embodiments, the bit-line110may have a fourth height111that is in a range of between approximately 40 nm and approximately 130 nm, between approximately 50 nm and approximately 120 nm, or other similar values.

FIG.6Billustrates a top-view602of some additional embodiments of the integrated chip structure600taken along cross-sectional line A-A′ ofFIG.6A.

As shown in top-view602, the plurality of interconnect vias130are disposed within a boundary of the plurality of interconnect islands304. In some embodiments, the plurality of interconnect vias130may be set back from the boundary along a first direction604and/or along a second direction606that is perpendicular to the first direction604. In some embodiments, the plurality of interconnect islands304may be square shaped. In other embodiments, the plurality of interconnect islands304may be rectangular shaped, or other similar shapes.

In some embodiments, the plurality of interconnect islands304may be separated from one another by a first distance608along the first direction604and by a second distance610along the second direction606. In some embodiments, the first distance608and/or the second distance610may be in a range of between approximately 10 nm and approximately 100 nm, between approximately 20 nm and approximately 80 nm, or other similar values. In some embodiments, the plurality of interconnect islands304may have a width614that is in a range of between approximately 10 nm and approximately 70 nm, between approximately 20 nm and approximately 50 nm, or other similar values.

In some embodiments, the plurality of interconnect vias130may have a circular shape. In other embodiments, the plurality of interconnect vias130may have a square shape, a rectangular shape, or other similar shapes. In some embodiments, the plurality of interconnect vias130may have a width612that is in a range of between approximately 10 nm and approximately 100 nm, between approximately 20 nm and approximately 80 nm, or other similar values.

FIG.6Cillustrates a top-view616of some additional embodiments of the integrated chip structure600taken along cross-sectional line B-B′ ofFIG.6A.

As shown in top-view616, the bit-line110continuously extends past the plurality of additional upper interconnect vias306along the first direction604along the second direction606. In some embodiments, the bit-line110may have a width620that is in a range of between approximately 10 nm and approximately 200 nm, between approximately 20 nm and approximately 160 nm, or other similar values. In some embodiments, the bit-line110may be separated from an additional bit-line624by a third distance622along the second direction606. In some embodiments, the third distance622may be in a range of between approximately 10 nm and approximately 200 nm, between approximately 20 nm and approximately 160 nm, or other similar values.

In some embodiments, the plurality of additional upper interconnect vias306may have a circular shape. In other embodiments, the plurality of additional upper interconnect vias306may have a square shape, a rectangular shape, or other similar shapes. In some embodiments, the plurality of additional upper interconnect vias306may have a width618that is in a range of between approximately 10 nm and approximately 100 nm, between approximately 20 nm and approximately 80 nm, or other similar values.

FIG.7illustrates a cross-sectional view of some additional embodiments of an integrated chip structure700comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line.

The integrated chip structure700comprises an embedded memory region124and a peripheral region136. A memory array102, comprising a plurality of memory devices104, is disposed within a dielectric structure126within the embedded memory region124. A local interconnect116is arranged within the dielectric structure126and is coupled to the plurality of memory devices104. The local interconnect116is arranged vertically between the plurality of memory devices104and the bit-line110. The local interconnect116comprises a bottom surface that continuously extends laterally past the plurality of memory devices104.

The local interconnect116is coupled to an overlying bit-line110by way of a plurality of interconnect vias130. The plurality of interconnect vias130have bottom surfaces that physically contact the local interconnect116and top surfaces that physically contact the bit-line110. In some embodiments, the local interconnect116continuously extends from within the embedded memory region124to within the peripheral region136. In some such embodiments, plurality of interconnect vias130may also extend from within the embedded memory region124to a non-zero distance702within the peripheral region136. By extending to the non-zero distance702within the embedded memory region124, the local interconnect116is able to further reduce a resistance of the bit-line110.

FIG.8illustrates a cross-sectional view of some additional embodiments of an integrated chip structure800comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line.

The integrated chip structure800comprises an embedded memory region124and a peripheral region136. A memory array102is disposed within the embedded memory region124. The memory array102comprises a plurality of memory devices104disposed within a dielectric structure126over a substrate122. A local interconnect116is arranged within the dielectric structure126and is coupled to the plurality of memory devices104. The local interconnect116is arranged vertically between the substrate122and the bit-line110.

The local interconnect116is coupled to an overlying bit-line110by way of a plurality of interconnect vias130, an additional interconnect wire802, and a plurality of additional upper interconnect vias306. The additional interconnect wire802is coupled to and extends in parallel to both the local interconnect116and the bit-line110. The plurality of interconnect vias130have bottom surfaces that physically contact the local interconnect116. The additional interconnect wire802has a bottom surface that physically contacts top surfaces of the plurality of interconnect vias130and a top surface that physically contacts the plurality of additional upper interconnect vias306. The plurality of additional upper interconnect vias306couple the additional interconnect wire802to the bit-line110.

FIG.9Aillustrates a schematic diagram900of some embodiments of an integrated chip structure comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line.

As shown in the schematic diagram900, the integrated chip structure comprises a memory array102including a plurality of memory cells103arranged within rows and/or columns. The plurality of memory cells103comprise a plurality of memory devices104and a plurality of access devices106configured to control access to the plurality of memory devices104. A first set of the plurality of memory devices104within a row respectively have access devices106that are operably coupled to one of a plurality of word-lines108a-108n. A second set of the plurality of memory devices104within a column are operably coupled to one of a plurality of bit-lines110a-110n. A third set of the plurality of memory devices104within the column are operably coupled to one of a plurality of additional bit-lines902a-902n. In some embodiments, the plurality of memory devices104within a column are further coupled to one of a plurality of source-lines112a-112n.

A plurality of local interconnects116a-116nare respectively coupled to the plurality of bit-lines110a-110nand to the second set of the plurality of memory devices104within the column of the memory array102. The plurality of local interconnects116a-116nextends in parallel to the plurality of bit-lines110a-110n. An additional plurality of local interconnects904a-904nare also respectively coupled to the plurality of additional bit-lines902a-902nand to the third set of the plurality of memory devices104within the column of the memory array102.

The plurality of word-lines108a-108n, the plurality of bit-lines110a-110n, and the plurality of additional bit-lines902a-902nare coupled to control circuitry114. In some embodiments, the control circuitry114comprises a word-line decoder402coupled to the plurality of word-lines108a-108n, a bit-line decoder404coupled to the plurality of bit-lines110a-110n, and an additional bit-line decoder906coupled to the plurality of additional bit-line902a-902n. In some such embodiments, the bit-line decoder404is configured to provide a signal to the plurality of bit-lines110a-110nduring an access operation and the additional bit-line decoder906is configured to provide an additional signal to the plurality of additional bit-line902a-902nduring an additional access operation. In some alternative embodiments (not shown), the control circuitry114may comprise a bit-line decoder404coupled to both the plurality of bit-lines110a-110nand the plurality of additional bit-line902a-902n. In some such embodiments, the bit-line decoder404is configured to provide signals to both the plurality of bit-lines110a-110nand the plurality of additional bit-line902a-902nduring an access operation.

By having the plurality of memory devices104within a column of the memory array102coupled to both the bit-line110aand the additional bit-line902a, a distance that the bit-line110aand the additional bit-line902aspan can be reduced thereby reducing a resistance of the bit-line110aand the additional bit-line902a. Furthermore, by having the bit-line110aand the additional bit-line902arespectively coupled to the local interconnect116aand the additional local interconnect904a, a resistance of the bit-line110aand the additional bit-line902acan be further reduced.

FIG.9Billustrates a cross-sectional view of some additional embodiments of an integrated chip structure910corresponding to section908of the schematic diagram900shown inFIG.9A.

The integrated chip structure910comprises an embedded memory region124and a peripheral region136. A memory array102is disposed within the embedded memory region124. The memory array102comprises a plurality of memory devices104disposed within a dielectric structure126over a substrate122.

A local interconnect116is arranged within the dielectric structure126and is coupled to a second set of the plurality of memory devices104. The local interconnect116is arranged vertically between the second set of the plurality of memory devices104and a bit-line110. The local interconnect116comprises a bottom surface that continuously extends laterally past the second set of the plurality of memory devices104. An additional local interconnect904is arranged within the dielectric structure126and is coupled to a third set of the plurality of memory devices104. The additional local interconnect904is arranged vertically between the third set of the plurality of memory devices104and an additional bit-line902. The additional local interconnect904comprises a bottom surface that continuously extends laterally past the third set of the plurality of memory devices104.

In some embodiments, the additional local interconnect904is coupled to an additional common electrode916by way of a plurality of additional local interconnect vias918. In some embodiments, the additional common electrode916physically contacts the third set of the plurality of memory devices104. The additional local interconnect904is further coupled to the additional bit-line902by way of a plurality of additional interconnect vias920, a plurality of additional interconnect islands922that are on the plurality of additional interconnect vias920, and a second plurality of additional upper interconnect vias924that are on the plurality of additional interconnect islands922.

The local interconnect116comprises an end that is laterally separated from an end of the additional local interconnect904by a first non-zero distance912that is laterally between the second set of the plurality of memory devices104and the third set of the plurality of memory devices104. The bit-line110also comprises an end that is laterally separated from an end of the additional bit-line902by a second non-zero distance914. In some embodiments, the first non-zero distance912may be approximately equal to the second non-zero distance914. In other embodiments, the first non-zero distance912and second non-zero distance914may be different. The separation between the local interconnects and the bit-lines reduces a length of the local interconnects and the bit-lines, thereby reducing a resistance of the bit-lines and further improving a performance of the integrated chip structure910.

FIGS.10-29illustrate cross-sectional views1000-2900showing some embodiments of a method of forming an integrated chip structure comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line. AlthoughFIGS.10-29are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.10-29are not limited to such a method, but instead may stand alone as structures independent of the method.

As shown in cross-sectional view1000ofFIG.10, a substrate122is provided. In various embodiments, the substrate122may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers, associated therewith. In some embodiments, the substrate122may comprise one or more dielectric layers, one or more inter-level dielectric (ILD) layers, and/or one or more interconnect layers disposed over a semiconductor body. In some embodiments, the substrate122may comprise an embedded memory region124and a peripheral region136.

In some embodiments, an access device106is formed on the substrate122and within the embedded memory region124. In some embodiments, a transistor device138is formed on the substrate122and within the peripheral region136. In some embodiments, the access device106may comprise a gate structure106cformed over the substrate122. In such embodiments, the gate structure106cmay be formed by depositing a gate dielectric over the substrate122and depositing a gate electrode over the gate dielectric. The gate electrode and the gate dielectric are subsequently patterned to form the gate structure106c. A source region106aand a drain region106bmay be formed within the substrate122on opposing sides of the gate structure106cby an implantation process. In some embodiments, the access device106may be formed within an active area defined by one or more isolation structures (e.g., shallow trench isolation (STI) structures) disposed within the substrate122.

As shown in cross-sectional view1100ofFIG.11, a plurality of lower interconnects128are formed within a lower ILD structure126L formed on the substrate122. In some embodiments, the plurality of lower interconnects128may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by forming an ILD layer over the substrate122, etching the ILD layer to form a via hole and/or a trench, and filling the via hole and/or trench with a conductive material. In some embodiments, the ILD layer may comprise USG, BPSG, FSG, PSG, BSG, or the like, formed by a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.), In some embodiments, the conductive material may comprise tungsten, copper, aluminum, copper, or the like, formed using a deposition process and/or a plating process (e.g., electroplating, electro-less plating, etc.).

An intermediate lower insulating structure1102is formed over the one or more lower interconnects128and/or the lower ILD structure126L. In some embodiments, the intermediate lower insulating structure1102comprises one or more of silicon rich oxide, silicon carbide, silicon nitride, and/or the like. In some embodiments, the intermediate lower insulating structure1102may be formed by one or more deposition processes (e.g., a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PE-CVD) process, or the like).

As shown in cross-sectional view1200ofFIG.12, a bottom electrode via204is formed within the intermediate lower insulating structure1102. In some embodiments, the bottom electrode via204may be formed by selectively etching the intermediate lower insulating structure1102to form an opening1202that extends through the intermediate lower insulating structure1102to expose an upper surface of the one or more lower interconnects128. In some embodiments, the opening1202may be subsequently filled with a conductive material to form a bottom electrode via204that extends through the intermediate lower insulating structure1102.

In some embodiments, the bottom electrode via204may comprise a diffusion barrier layer514and a conductive core512formed over the diffusion barrier layer514. In some embodiments, the diffusion barrier layer514may comprise one or more of a metal, a metal nitride, and/or the like. In some embodiments, the conductive core512may comprise tungsten, tantalum nitride, titanium nitride, ruthenium, platinum, iridium, or the like. In some embodiments, the diffusion barrier layer514and the conductive core512may be formed by deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). In some embodiments, a planarization process1204(e.g., a chemical mechanical planarization (CMP) process) be performed to remove excess of the diffusion barrier layer514and the conductive core512from over the intermediate lower insulating structure1102.

As shown in cross-sectional view1300ofFIG.13, a bottom electrode structure1302is formed over the intermediate lower insulating structure1102and a memory device stack1303is formed over the bottom electrode structure1302. In some embodiments, the bottom electrode structure1302may comprise a metal, such as tantalum, titanium, tantalum nitride, titanium nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, or the like. In some embodiments, the memory device stack1303may comprise a pinned layer1304formed over the bottom electrode structure1302, a dielectric barrier tunnel layer1306formed over the pinned layer1304, and a free layer1308formed over the dielectric barrier tunnel layer1306. In other embodiments (not shown), the free layer1308may be formed over the bottom electrode structure1302, the dielectric barrier tunnel layer1306formed over the free layer1308, and the pinned layer1304may be formed over the dielectric barrier tunnel layer1306.

As shown in cross-sectional view1400ofFIG.14, a top electrode structure1402is formed over the memory device stack1303. In some embodiments, the top electrode structure1402may comprise a metal, such as tantalum, titanium, tantalum nitride, titanium nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, or the like. In some embodiments, the top electrode structure1402may be formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like).

As shown in cross-sectional view1500ofFIG.15, the top electrode structure (e.g.,1402ofFIG.14) is selectively patterned to define a top electrode104c. In some embodiments, the top electrode structure may be selectively patterned by exposing the top electrode structure to an etchant1502according to a mask layer1504(e.g., silicon nitride, silicon carbide, or the like).

As shown in cross-sectional view1600ofFIG.16, the memory device stack (e.g.,1303ofFIG.15) and the bottom electrode structure (e.g.,1302ofFIG.15) are selectively patterned to define a memory device104having data storage structure104bdisposed between a bottom electrode104aand the top electrode104c. In some embodiments, the memory device stack may be selectively etched according to the mask layer (1504ofFIG.15) and/or the top electrode104cto define the data storage structure104band the bottom electrode104a.

In some embodiments, the intermediate lower insulating structure (1102ofFIG.15) may also be etched to define a lower insulating structure202. The lower insulating structure202comprises a first lower insulating layer501, a second lower insulating layer502over the first lower insulating layer, and a third lower insulating layer504over the second lower insulating layer. In some embodiments, the second lower insulating layer502and the third lower insulating layer504may be confined within the embedded memory region124.

As shown in cross-sectional view1700ofFIG.17, a first sidewall spacer layer506is formed along sidewalls of the memory device104. In some embodiments, the first sidewall spacer layer506may comprise a first dielectric material such as silicon nitride, silicon oxide, or the like. In some embodiments, the first dielectric material may be deposited using a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). An etch process (e.g., an anisotropic etch process) may be subsequently performed to remove horizontal portions of the first dielectric material. The first dielectric material may be formed to a thickness that is in a range of between approximately 2 nm and approximately 20 nm, between approximately 4 nm and approximately 10 nm, or other similar values.

As shown in cross-sectional view1800ofFIG.18, an intermediate second sidewall spacer layer1802is on the first sidewall spacer layer506and the top electrode104c. In some embodiments, the intermediate second sidewall spacer layer1802may comprise a second dielectric material such as a dielectric metal oxide such as aluminum oxide, hafnium oxide, lanthanum oxide, or yttrium oxide. In some embodiments, the second dielectric material may be deposited using a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). The second dielectric material may be formed to a thickness that is in a range of between approximately 2 nm and approximately 20 nm, between approximately 4 nm and approximately 10 nm, or other similar values. In one embodiment, the second dielectric material may be deposited directly on sidewalls of the top electrode104c.

As shown in cross-sectional view1900ofFIG.19, a dielectric encapsulation structure510is formed over the intermediate second sidewall spacer layer1802. In some embodiments, the dielectric encapsulation structure510may comprise silicon oxide, silicon nitride, or a dielectric metal oxide. In some embodiments, the dielectric encapsulation structure510may be formed by depositing a dielectric encapsulation material (e.g., by a conformal deposition process such as an atomic layer deposition process or a chemical vapor deposition process), and subsequently etching (e.g., anisotropically etching) the dielectric encapsulation material to remove the dielectric encapsulation material from the peripheral region136. In one embodiment, a top surface of the dielectric encapsulation structure510may be located above a top of the top electrode104c.

As shown in cross-sectional view2000ofFIG.20, a first upper ILD layer126U1is formed over the dielectric encapsulation structure510. In some embodiments, the first upper ILD layer126U1may comprise USG, BPSG, FSG, PSG, BSG, or the like. In some embodiments, the first upper ILD layer126U1may be formed by way of a deposition process (e.g., PVD, CVE, PE-CVD, ALD, or the like).

As shown in cross-sectional view2100ofFIG.21, one or more peripheral interconnects140are formed within the peripheral region136. In some embodiments, the one or more peripheral interconnects140may be formed by way of a damascene process and/or a dual damascene process. In some such embodiments, the first upper ILD layer126U1is etched to form holes and/or trenches, which are subsequently filled with a conductive material (e.g., tungsten, copper, and/or aluminum). A planarization process2102(e.g., a CMP process) is subsequently performed to remove excess of the conductive material from over the first upper ILD layer126U1.

As shown in cross-sectional view2200ofFIG.22, a first dielectric stack2201is formed over the first upper ILD layer126U1. In some embodiments, the first dielectric stack2201may comprise an intermediate upper-level etch stop dielectric layer2202formed over the first upper ILD layer126U1, an intermediate first dielectric matrix layer2204formed over the intermediate upper-level etch stop dielectric layer2202, and an intermediate second dielectric matrix layer2206formed over the intermediate first dielectric matrix layer2204. In some embodiments, the intermediate upper-level etch stop dielectric layer2202may comprise silicon nitride, silicon carbide, silicon nitride carbide, aluminum nitride, a metal oxide (such as aluminum oxide, titanium oxide, tantalum oxide, etc.), or the like, formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). In some embodiments, the intermediate first dielectric matrix layer2204may comprise silicon nitride, silicon carbide, silicon nitride carbide, aluminum nitride, a metal oxide (such as aluminum oxide, titanium oxide, tantalum oxide, etc.), or the like, formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). In some embodiments, the intermediate second dielectric matrix layer2206may comprise TEOS, USG, BPSG, FSG, PSG, BSG, or the like, formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like).

As shown in cross-sectional view2300ofFIG.23, the intermediate upper-level etch stop dielectric layer (2202ofFIG.22), the intermediate first dielectric matrix layer (2204ofFIG.22), and the intermediate second dielectric matrix layer (2206ofFIG.22) are selectively patterned to form an upper-level etch stop dielectric layer524, a first dielectric matrix layer526, and a second dielectric matrix layer528. The upper-level etch stop dielectric layer524, the first dielectric matrix layer526, and the second dielectric matrix layer528respectively have sidewalls that define a common electrode opening2302that exposes upper surfaces of the top electrode104cwithin the plurality of memory devices104.

As shown in cross-sectional view2400ofFIG.24, a common electrode522is formed within the common electrode opening2302. In some embodiments, the common electrode522may be formed by depositing a conductive material (e.g., tungsten, copper, and/or aluminum) within the common electrode opening2302. A planarization process2102(e.g., a chemical CMP process) is subsequently performed to remove excess of the conductive material from over the second dielectric matrix layer528.

As shown in cross-sectional view2500ofFIG.25, a cap-level etch stop dielectric layer530is formed over the common electrode522and an upper-level dielectric layer532is formed over the cap-level etch stop dielectric layer530. In some embodiments, the cap-level etch stop dielectric layer530may comprise silicon nitride, silicon carbide, silicon nitride carbide, aluminum nitride, a metal oxide (such as aluminum oxide, titanium oxide, tantalum oxide, etc.), or the like, formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). In some embodiments, the upper-level dielectric layer532may comprise TEOS, USG, BPSG, FSG, PSG, BSG, or the like, formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). In some embodiments, the cap-level etch stop dielectric layer530and the upper-level dielectric layer532may be formed to continuously extend from over the common electrode522to within the peripheral region136.

As shown in cross-sectional view2600ofFIG.26, a second upper ILD layer126U2is formed over the upper-level dielectric layer532. In some embodiments, the second upper ILD layer126U2may comprise TEOS, USG, BPSG, FSG, PSG, BSG, or the like, formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like).

The cap-level etch stop dielectric layer530, the upper-level dielectric layer532, and the second upper ILD layer126U2are selectively patterned to form a plurality of interconnect via openings2602and a local interconnect opening2604that expose an upper surface of common electrode522. The plurality of local interconnect via openings2602are defined by sidewalls of the cap-level etch stop dielectric layer530and the upper-level dielectric layer532, while the local interconnect opening2604is defined by sidewalls of the second upper ILD layer126U2. The local interconnect opening2604extends laterally past plurality of interconnect via openings2602and past opposing edges of the plurality of memory devices104.

As shown in cross-sectional view2700ofFIG.27, a plurality of local interconnect vias534are formed within the plurality of local interconnect via openings2602and a local interconnect116is formed within the local interconnect opening2604. In some embodiments, the plurality of local interconnect vias534and/or the local interconnect116may be formed by depositing a conductive material (e.g., tungsten, copper, and/or aluminum) within the plurality of local interconnect via openings2602and the local interconnect opening2604. A planarization process2702(e.g., a CMP process) is subsequently performed to remove excess of the conductive material from over the second upper ILD layer126U2.

As shown in cross-sectional view2800ofFIG.28, a third upper ILD layer126U3is formed over the second upper ILD layer126U2. In some embodiments, the third upper ILD layer126U3may comprise TEOS, USG, BPSG, FSG, PSG, BSG, or the like, formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). The third upper ILD layer126U3is selectively patterned to form a plurality of interconnect via openings2802and a bit-line opening2804that expose an upper surface of local interconnect116. The plurality of interconnect via openings2802and the bit-line opening2804are defined by sidewalls of the third upper ILD layer126U3.

As shown in cross-sectional view2900ofFIG.29, a plurality of interconnect vias130are formed within the plurality of interconnect via openings2802and a bit-line110is formed within the bit-line opening2804. In some embodiments, the plurality of interconnect vias130and/or the bit-line110may be formed by depositing a conductive material (e.g., tungsten, copper, and/or aluminum) within the plurality of interconnect via openings2802and the bit-line opening2804. A planarization process2902(e.g., a CMP process) is subsequently performed to remove excess of the conductive material from over the third upper ILD layer126U3.

FIG.30illustrates a flow diagram of some embodiments of a method3000of forming an integrated chip structure comprising a memory array having a local interconnect configured to reduce a resistance of a bit-line.

At act3002, a plurality memory devices are formed within a memory array disposed over a substrate.FIGS.13-21illustrate cross-sectional views1300-2100of some embodiments corresponding to act3002.

At act3004, a common electrode is formed onto the plurality of memory devices.FIGS.22-24illustrate cross-sectional views2200-2400of some embodiments corresponding to act3004.

At act3006, a plurality of local interconnect vias are formed onto the common electrode.FIGS.25-27illustrate cross-sectional views2500-2700of some embodiments corresponding to act3006.

At act3008, a local interconnect is formed onto the plurality of local interconnect vias.FIGS.25-27illustrate cross-sectional views2500-2700of some embodiments corresponding to act3008.

At act3010, a plurality of interconnect vias are formed onto the local interconnect.FIGS.28-29illustrate cross-sectional views2800-2900of some embodiments corresponding to act3010.

At act3012, a bit-line, which laterally extends past opposing ends of the local interconnect, is formed over and in electrical contact with plurality of interconnect vias.FIGS.28-29illustrate cross-sectional views2800-2900of some embodiments corresponding to act3012.

Accordingly, in some embodiments, the present disclosure relates to an integrated chip structure comprising a memory array having a local interconnect that is configured to reduce a resistance of a bit-line within the memory array.

In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a memory array having a plurality of memory devices arranged in a plurality of rows and a plurality of columns; a word-line coupled to a first set of the plurality of memory devices disposed within a first row of the plurality of rows; a bit-line coupled to a second set of the plurality of memory devices disposed within a first column of the plurality of columns; and a local interconnect extending in parallel to the bit-line and coupled to the bit-line and two or more of the second set of the plurality of memory devices, the local interconnect being coupled to the bit-line by a plurality of interconnect vias that are between the local interconnect and the bit-line. In some embodiments, the local interconnect is vertically between the two or more of the second set of the plurality of memory devices and the bit-line. In some embodiments, the local interconnect continuously extends laterally past outermost edges of the two or more of the second set of the plurality of memory devices. In some embodiments, the local interconnect continuously extends laterally past the plurality of interconnect vias. In some embodiments, the bit-line laterally extends past opposing ends of the local interconnect. In some embodiments, the integrated chip structure further includes a bit-line decoder coupled to the bit-line and configured to selectively apply a signal to the bit-line during an access operation. In some embodiments, the integrated chip structure further includes an additional bit-line coupled to a third set of the plurality of memory devices disposed within the first column of the plurality of columns, an end of the bit-line being separated from an end of the additional bit-line by a non-zero distance; and an additional local interconnect extending in parallel to the additional bit-line, the additional local interconnect being coupled between the additional bit-line and two or more of the third set of the plurality of memory devices. In some embodiments, the integrated chip structure further includes a bit-line decoder coupled to the bit-line, the bit-line decoder being configured to selectively apply a signal to the bit-line during an access operation; and an additional bit-line decoder coupled to the additional bit-line, the additional bit-line decoder being configured to selectively apply an additional signal to the additional bit-line during an additional access operation. In some embodiments, the integrated chip structure further includes a common electrode disposed between the local interconnect and the two or more of the second set of the plurality of memory devices, the local interconnect being coupled to the common electrode by way of a plurality of local interconnect vias.

In other embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a memory array having a plurality of memory devices arranged within a dielectric structure disposed over a substrate as viewed in a cross-sectional view; a bit-line disposed over the plurality of memory devices; a local interconnect extending in parallel to the bit-line and coupled to the plurality of memory devices, the bit-line extending laterally past opposing ends of the local interconnect; and the local interconnect being coupled to the bit-line by a plurality of interconnect vias that are disposed between a top of the local interconnect and a bottom of the bit-line. In some embodiments, the plurality of interconnect vias laterally extend past two or more of the plurality of memory devices. In some embodiments, the integrated chip structure further includes a common electrode disposed between the local interconnect and the plurality of memory devices and continuously extending past outermost edges of the plurality of memory devices, the local interconnect being coupled to the common electrode by way of a plurality of local interconnect vias. In some embodiments, the local interconnect laterally extends past opposing ends of the common electrode. In some embodiments, the integrated chip structure further includes an upper ILD structure laterally surrounding the bit-line; and a peripheral interconnect via vertically extending through the upper ILD structure outside of the memory array, the peripheral interconnect via vertically extending past the common electrode and the plurality of local interconnect vias. In some embodiments, the plurality of memory devices respectively include a magnetic tunnel junction (MTJ) disposed between a bottom electrode and a top electrode. In some embodiments, the integrated chip structure further includes a plurality interconnect islands contacting upper surfaces of the plurality of interconnect vias; and a plurality of additional upper interconnect vias contacting upper surfaces of the plurality of interconnect islands and a lower surface of the bit-line. In some embodiments, the memory array includes one or more additional memory devices disposed laterally outside of the local interconnect, as viewed in the cross-sectional view. In some embodiments, the integrated chip structure further includes a transistor device disposed within a peripheral region of the substrate that surrounds an embedded memory region of the substrate comprising the plurality of memory devices, the bit-line extending to within the peripheral region of the substrate and the local interconnect being confined within the embedded memory region of the substrate.

In yet other embodiments, the present disclosure relates to a method for forming an integrated chip structure. The method includes forming a plurality of memory devices over a substrate; forming a first upper inter-level dielectric (ILD) layer over the plurality of memory devices; patterning a first upper ILD layer to form a local interconnect opening that extends laterally past opposing edges of the plurality of memory devices; forming a local interconnect within the local interconnect opening; forming a plurality of interconnect vias within a second upper ILD layer that is over the first upper ILD layer; and forming a bit-line over the plurality of interconnect vias, the plurality of interconnect vias coupling the local interconnect to the bit-line. In some embodiments, the method further includes forming a first dielectric stack over the plurality of memory devices; patterning the first dielectric stack to form a common electrode opening that exposes tops of the plurality of memory devices; and forming a common electrode within the local interconnect opening.