Self monitoring and self repairing ECC

Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.

FIELD OF THE INVENTION

The present invention relates generally to the design of memory and more specifically to the design of Error Correcting Code.

BACKGROUND

Error Correcting Code (ECC) is a technique that is commonly used to correct errors in semiconductor memory but may be used elsewhere. ECC is used with all forms of semiconductor memory but is especially beneficial in dynamic memory (DRAM) memories and to a lesser extent in static memory (SRAMs). DRAMs are more susceptible than SRAMs to soft errors (transitory) and hard errors (permanent) caused by a variety of sources, including energetic particles, electrical noise, microwaves, age, and high temperatures. An energetic particle (often a proton produced by a decayed cosmic ray neutron) can discharge small capacitors that store bits in a DRAM and can, in some cases, permanently damage semiconductor circuits. Airborne system designers pay particular heed to a risk from energetic particles whose prevalence increases greatly with altitude. A common form of ECC used with semiconductor memories is Single Error Correction Double Error Detection (SEC-DED) which can, as the name implies, detect and correct a single bit error and detect a double bit error. Usually a system is unaware of an occurrence of a single bit error but may try to clear a double bit error by retrying an access. If a double bit error cannot be cleared, an operating system is often notified by way of a machine check, which may then take an appropriate action. Many systems cannot recover from a double bit error in critical code, e.g., the kernel of an operating system. Some systems scrub memory by periodically reading and writing data to clean single bit soft errors from memory to reduce the likelihood that ECC will detect a double bit error.

When data is written to an ECC enabled memory, ECC logic examines a block of data bits, commonly 64-bits, and generates a block of bits based on the data bits, called check bits, that are stored with the data. A check bit is a parity bit generated on a combination of data bits, and each check bit is generated from a specific combination of data bits that is unique to each check bit. SEC-DED requires 8 check bits to be generated from and stored with a 64-bit block of data, therefore storing 72-bits. When the data is read, the check bits are read with the data and are processed by ECC logic to generate an error indicator, called a syndrome. A syndrome points to a flipped bit (in the data or check bits) if there is one, or may indicate that two erroneous bits exist somewhere in the 72-bits read. In an unlikely event that three or more bits are in error, an erroneous syndrome is generated that may erroneously indicate that a correct bit is incorrect or that the data is correct.

Double Error Correction (DEC) techniques exist but require 14 check bits to be generated and stored with 64-bits of data. Double Error Correction Triple Error Detection (DEC-TED) requires 15 check bits to be generated and stored with 64-bits of data. DEC or DEC-TED is used in situations that require extreme reliability and/or operation in hazardous environments, e.g., spacecraft exposed to radiation or in hardened weapons systems.

Byte correction codes are a type of ECC that is are often employed in memory systems with a memory organization that includes memory chips that provide byte accesses. In this case, a failed memory chip causes an entire byte of information to be incorrect. Byte-oriented error correction codes have been developed that provide single byte error correction and double byte error detection (SBC-DBD) to enable a system to continue operation with a failed memory chip. Other byte-oriented ECC techniques are possible.

SUMMARY

Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.

DETAILED DESCRIPTION

FIG. 1depicts a computer system100in which a processor complex101is connected to a memory system102via a data bus104. Processor complex101stores and retrieves data from memory system102as needed. Memory system102incorporates an Error Correcting Code (ECC) system103that can correct a single bit in data read from memory and can detect a double bit error in data read from memory. An ability to correct a single bit error and detect a double bit error is termed Single Error Correction Double Error Detection or SEC-DED. In an exemplary embodiment, ECC system103incorporates two ECC modules, ECC module A201and ECC module B202, shown inFIG. 2, that can each independently perform SECDED with ECC logic217and ECC logic218respectively. In this embodiment, ECC module A201and ECC module B202are identical in design, but ECC module A201and ECC module B202may differ in design in other embodiments.

In an exemplary embodiment, ECC module A201operates until ECC module A201fails as determined by a loop-back test that is run on ECC logic217in ECC module A201. If ECC module A201fails, ECC system control logic207causes ECC module B202to perform a loop-back test, and if ECC module B202passes the loop-back test, ECC module B202assumes operation. If ECC module B202fails a loop-back test, ECC system control logic207generates a machine check interrupt that notifies an operating system that ECC system103has failed.

A test pattern used by a check bit test contains a correct check bit pattern for a data bit pattern that the check bit pattern is coupled with in the test pattern. The check bit pattern is a check bit pattern that a correctly functioning ECC logic would generate to be stored in memory with the data in the data bit pattern. A test pattern used by an error detection and correction test contains an incorrect check bit pattern coupled with a data bit pattern in the test pattern. Incorrect check bits associated with a data bit pattern cause a correctly functioning ECC logic to detect a single bit error in a specific bit position or a double bit error in the data bit pattern, depending on a pattern of bits in the incorrect check bit pattern used. By varying an incorrect check bit pattern used in each of a plurality of tests, ECC logic that participates in detecting and correcting an error in each bit position in a data and check bits that are processed by an ECC module is tested for correct function. ECC logic that detects an existence of two erroneous bits in all possible bit position combinations is also tested.

FIG. 3is a block diagram that depicts a flow of information in a check bit test in ECC module A201. Test pattern302is read from test pattern table215. ECC logic217generates check bits307from data bit pattern304which are compared with correct check bit pattern303in comparator308. If the generated check bits307match correct check bit pattern303, ECC logic217operated correctly and passed the check bit test.

FIG. 4depicts a flow diagram of a check bit test that may use one or more test patterns in a check bit test of ECC logic217. In step401a test pattern is read from test pattern table215. In step402, check bits are generated from a data bit pattern in the test pattern. In step403, the generated check bits are compared with a check bit pattern in the test pattern. If the generated check bits do not match the check bit pattern in the test pattern, ECC logic217fails the check bit test and the check bit test fails in step406, otherwise, the check bit test continues until ECC logic217has passed a test with each test pattern in the check bit test, determined in step404, and passes the check bit test in step405or until ECC logic217fails a test and the check bit test fails in step406.

FIG. 5is a block diagram that depicts an example of a flow of information in an error detection and correction test in ECC module A201. Test pattern502is read from test pattern table215. ECC logic217processes check bit pattern503and data bit pattern504as if data bit pattern504and check bit pattern503had been read from memory. Since check bit pattern503is incorrect, ECC logic217should detect and correct a single bit error507or detect a double bit error508, depending on a function of ECC logic217that check bit pattern503is intended to test.

FIG. 6depicts an exemplary flow diagram of an error detection and correction test that may use one or more test patterns to test ECC logic217. In step601, a test pattern is read from test pattern table215. In step602, ECC logic217processes a check bit pattern (that is incorrect) and a data bit pattern in the test pattern as if the data bit pattern and the check bit pattern had been read from memory. In step603, an error that ECC logic217may have detected and/or corrected is checked for correctness. If ECC logic217generates an incorrect result, ECC logic217fails606the error detection and correction test, otherwise, the error detection and correction test continues until ECC logic217has passed a test with each test pattern in the error detection and correction test, as determined in step604, and passes the error detection and correction test in step605, or until ECC logic217fails a test and fails the error detection and correction test in step606.

ECC system103may employ the function of ECC module201or the function of ECC module202as controlled by ECC system control207. When ECC system103is employing the function of ECC module201, multiplexers203,204,205and206, are conditioned by control lines221,222,223, and220respectively, to select inputs210,212,213, and209respectively as an output. When ECC system103is using the function of ECC module202, multiplexers203,204,205and206, are conditioned by control lines221,222,223, and220respectively, to select inputs210,224,223, and209respectively as an output.

ECC system control207conditions multiplexers203,204,205and206with control lines221,222,223, and220respectively during a loop-back test to cause an output of an ECC module to be routed to an input of the ECC module. To perform a loop-back test on ECC module A201, ECC system control207uses control bus210to initiate a loop-back test on ECC logic217in ECC module A201. Test patterns in test pattern table215are output on bus213and input to multiplexer205. ECC system control207, via control line219, selects multiplexer input213for output on signal bus208, which is an input to multiplexer206. ECC control system207conditions multiplexer via control line220to select input signal lines208to be output on signal lines214. ECC module201then reads an input on signal lines214as if the input was from memory and performs a check bit test or an error detection and correction test.

In an exemplary embodiment, test patterns in test pattern table215are used in a loop-back test on ECC logic217and test patterns in test pattern table216are used in a loop-back test on ECC logic218. However, in other embodiments, test patterns in test pattern table215may be used in a loop-back test on ECC logic218and test patterns in test pattern table216may be used in a loop-back test on ECC logic217. In this case, ECC system control207would condition multiplexers203,204,205and206with control lines221,222,223, and220respectively to route a test pattern in an ECC module to a different ECC module, doubling a number of test patterns that may be used in a loop-back test.

FIG. 7is a flow diagram of an operation of ECC system103. ECC module A201is operating in computer system100soon after computer system100is powered on and if no ECC system103errors have yet occurred after computer system100is running. Single bit errors (SBE) that ECC module A201has detected and corrected is counted by counter225in step701, and double bit errors (DBE) are detected. If the number of SBEs does not exceed a specified limit and no DBEs have been detected, ECC system103continues operation by continuing to count SBEs and detecting DBEs. In decision step702a determination is made if the number of SBEs has exceeded a specified limit or a DBE has been detected. If the number of SBEs has exceeded a specified limit or a DBE has been detected ECC system103runs a loop-back check on ECC module201in step703. In decision step704a determination is made if ECC module201passed or failed the loop-back test. If ECC module201passes the loop-back test and a DBE had been detected in step702, as determined in step705, a machine check is asserted in step707. If ECC module201fails the loop-back check, as determined in step704and a DBE was not detected in step702, as determined in step705, an event that a specified number of SBEs is exceeded is logged in step708, SBE counter225is reset to zero in step709, and ECC module A201continues to operate with next step701.

If in decision step704ECC module A201is found to be defective because ECC module A201failed the loop-back test, a loop-back test is run on ECC module B202in step710in preparation for ECC module B202to replace ECC module A201. A determination is made in step710as to whether ECC module B passed or failed a loop-back test in step706. If ECC module B failed a loop-back test in step706, a machine check is asserted in step707as ECC system103has failed. If ECC module B passed a loop-back test in step706, ECC system control207replaces a function of ECC module A201with a function of ECC module202in step711. A fact that ECC system103is operating on a backup ECC module202and that ECC system103needs to be replaced is logged in step712.

If ECC module B202is operating in ECC system103, ECC module A201is inoperative. A flow diagram inFIG. 8depicts the operation of ECC system103when ECC module B202is operating after replacing ECC module A201. Single bit errors are detected and corrected and counted by counter226, and double bit errors are detected in step801. Decision step802determines if a specified number of SBEs is exceeded or a DBE has been detected in ECC module202, if not, operation continues with step801. If a specified number of SBEs is exceeded or a DBE is detected in ECC module202, a loop-back test is run in step803. A determination is made in step804as to whether ECC module202passed or failed the loop-back test. If ECC module202failed the loop-back test, ECC system103has failed and a machine check is asserted. If ECC module202passed the loop-back test a determination is made in step805as to whether or not a DBE was detected in step802. If a DBE was detected in step802, an uncorrectable memory error has occurred and a machine check is asserted. If no DBE was detected in step802, the fact that a specified limit of SBEs has been exceeded is logged in step807, SBE counter226is reset to zero in step808, and ECC module B202continues to operate with a next step801.

The forgoing description is an example embodiment only, and those skilled in the art understand that the number of ECC modules in an ECC system can vary, that a number of bits involved in correctable and uncorrectable errors can vary depending on a type of ECC employed, and that tests that are included in a loop-back test can vary in number and nature. In the forgoing embodiment a single bit correction, double bit detection code is assumed, however other embodiments may employ a byte-oriented ECC, e.g., a Single Byte Correction, Double Byte Detection code (SBC-DBD). Byte-oriented ECC is often employed in memory systems that may employ memory components that provide a byte access. A failure of a memory component providing a byte access results in an entire byte of data being in error. Employing SBC-DBD for example, enables a system to continue operation with a failed memory component that has byte access.

FIG. 9depicts a block diagram of components of computer system900in accordance with an illustrative embodiment of the present invention. Computer system900may incorporate computer system100. It should be appreciated thatFIG. 9provides only an illustration of one implementation and does not imply any limitations with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made.

Computer system900includes communications fabric902, which provides communications between computer processor(s)904, memory906, persistent storage908, communications unit910, and input/output (I/O) interface(s)912. Communications fabric902can be implemented with any architecture designed for passing data and/or control information between processors (such as microprocessors, communications and network processors, etc.), system memory, peripheral devices, and any other hardware components within a system. For example, communications fabric902can be implemented with one or more buses.

Communications unit910, in these examples, provides for communications with other data processing systems or devices. In these examples, communications unit910includes one or more network interface cards. Communications unit910may provide communications through the use of either or both physical and wireless communications links.

I/O interface(s)912allows for input and output of data with other devices that may be connected to computer system100. For example, I/O interface912may provide a connection to external devices918such as a keyboard, keypad, a touch screen, and/or some other suitable input device. External devices918can also include portable computer-readable storage media such as, for example, thumb drives, portable optical or magnetic disks, and memory cards. Software and data used to practice embodiments of the present invention, e.g., ECC system103can be stored on such portable computer-readable storage media and can be loaded onto persistent storage908via I/O interface(s)912. I/O interface(s)912also connects to display920.