CMOS N-well bias generator and gating system

A system for preventing forward biasing of the bit line junctions formed between the N-well and bit lines of a CMOS memory. The system includes a gating system for maintaining the bit line voltage at V.sub.CC /2 whenever the well voltage is less than V.sub.CC. A well regulator and well pump maintain the well voltage at a selected multiple of V.sub.CC.

BACKGROUND OF THE INVENTION 
The invention relates generally to biasing a region in a semiconductor 
integrated circuit to a selected voltage level and, more particularly, to 
a system for preventing undesired charge injection for bipolar latchup in 
a CMOS integrated circuit. 
Recent advances in CMOS technology have allowed memory circuit designers to 
realize the power reduction inherent in CMOS design while achieving high 
density. However, as memory cell size decreases to allow for high density 
arrays, the susceptibility of alpha particle induced soft errors in the 
array increases. A CMOS DRAM utilizing PMOS memory cells disposed in an 
N-well formed in P substrate significantly reduces this soft error 
susceptibility. 
The N-well must be biased to a higher voltage level than the PMOS transfer 
gates in the memory cells and the P channel bit line connections to 
reverse bias the semiconductor junctions formed between these PMOS 
elements and the N-well. If these junctions are forward biased, then 
undesired charge injection takes place between the PMOS memory cells and 
the bit line connections in the N-well, thereby destroying the information 
stored in the memory. Additionally, the various P type and N type regions 
in a CMOS array form bipolar transistors. If the above-described junctions 
are forward biased then the transistors may form a feedback current loop 
to allow high substrate current. This phenomenon is termed bipolar latch 
up. 
The active cycle of the memory is initiated by clocking a control signal 
received at a control input of the memory. During the active cycle, 
selected word lines are clocked to couple selected storage cells to the 
bit lines. The voltage level on half the bit lines in the array are pulled 
to the power supply level, V.sub.CC, by the sense amps. 
The N-well may be biased to a multiple of V.sub.CC, e.g., 1.5 V.sub.CC, to 
prevent forward biasing during the active cycle. A CMOS memory having an 
N-well biased at 1.5 V.sub.CC is described in an article by Shimohigashi, 
et al. entitled "An N-Well CMOS Dynamic RAM," IEEE Journal of Solid State 
Circuits, Vol. SC-17, No. 2, April, 1982, pp. 344-348. 
However, during initial power-up, or during an excursion in the value of 
the power supply voltage (V.sub.CC bump), the bit line voltage may exceed 
the N-well bias voltage and forward bias the semiconductor junction. The 
large capacitance of the N-well causes the rate of change of the N-well 
bias voltage level to be slower than the rate of change of the bit line 
voltage level. Thus, the bit line voltage may exceed the N-well voltage 
for a short time. During this time the above-described problems of charge 
injection and bipolar latchup will be present if the memory is in the 
active cycle. 
Accordingly, a system for preventing the forward biasing of the junctions 
between the bit lines and the N-well during the active cycle of the memory 
is greatly needed in the industry. This system must protect the memory 
during initial power-up and during a V.sub.CC bump. Additionally, the 
system must consume low power so as not to degrade the low power 
dissipation inherent in CMOS technology. 
SUMMARY OF THE INVENTION 
The present invention is a system for preventing forward biasing of the bit 
line junctions and memory cell junctions formed between the N-well and bit 
line terminals and memory cells, respectively. The system is for use with 
a memory array where the bit lines are precharged to a fraction of 
V.sub.CC, e.g., V.sub.CC /2. 
The invention includes a gating system for forcing the array into precharge 
during a critical time period when V.sub.W is less than V.sub.CC. The 
gating system overrides the external control signal during the critical 
period. Thus, the bit line is held at V.sub.CC /2 until V.sub.W is greater 
than V.sub.CC. 
According to a further aspect of the invention, a well regulator and charge 
pump maintain V.sub.W at a multiple of V.sub.CC, e.g., 1.5 V.sub.CC. 
However, during initial powerup or a V.sub.CC bump V.sub.W rises more 
slowly than V.sub.CC because of the large capacitance of the well. 
Accordingly, V.sub.W will be less than V.sub.CC during a critical time 
period. 
If the array were driven into the active cycle during this critical time 
period, then half the bit lines would be pulled to V.sub.CC. Because 
V.sub.W is less than V.sub.CC, the junctions between these bit lines and 
the N-well would be forward biased, thereby causing charge injection and 
bipolar latchup. 
The gating system prevents forward biasing during the critical period by 
holding the array in precharge to maintain the bit line voltage at 
V.sub.CC /2. Once V.sub.W is greater than V.sub.CC the gating system 
releases the array to the control of the external control signal. 
In a preferred embodiment, the gate control signal is clocked by a CMOS 
differential amplifier having its inverting input coupled to V.sub.CC and 
its non-inverting input coupled to V.sub.W. 
According to a further aspect of the invention, a well enabling circuit 
clocks a well enabling signal to disable the differential amplifier when 
V.sub.W is greater than V.sub.CC +V.sub.T, where V.sub.T is the threshold 
of a MOS transistor. 
According to a further aspect of the invention, a holding transistor holds 
the gate control signal at V.sub.CC when the well detector is disabled. 
The differential amplifier consumes power when in operation. By disabling 
the differential amplifier subsequent to termination of the critical time 
period, power dissipation of the system is reduced. 
Other aspects and advantages will become apparent by reference to the 
drawings and the detailed description which follow.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The present invention is a system for preventing charge injection from the 
bit lines to the N-well and for preventing bipolar latchup during the 
active cycle of a CMOS memory array. The system is for use in a memory 
scheme where the bit lines are biased to V.sub.CC /2 during the precharge 
cycle of the memory. A biasing system suitable for use with the present 
invention is disclosed in the copending, commonly assigned, patent 
application entitled "CMOS DRAM MEMORY ARRAY BIAS SCHEME," by Chuang, et 
al. There, an externally clocked signal, RAS, is received at the control 
input of the memory. When RAS is high the chip is in the precharge state 
and the bit lines are coupled to each other and to a V.sub.CC /2 bias 
voltage generator. When RAS is clocked low, bit lines are isolated from 
each other and from the V.sub.CC /2 bias voltage generator. 
During the active cycle, half of the bit lines in the array are pulled to 
V.sub.CC and half are pulled to ground by the sense amplifiers. When RAS 
is clocked high again, the bit lines are again coupled to each other and 
to the V.sub.CC /2 bias voltage generator to rapidly return the bit lines 
to V.sub.CC /2. 
In the description that follows, various control signals are switched 
between low and high voltage states in response to specified circuit 
conditions. Generally, the magnitude of the high voltage state is equal to 
about V.sub.CC and the magnitude of the low voltage state is equal to 
about ground. 
The operation of the circuit will be generally described with reference to 
FIGS. 1-3, which are a block diagram and timing diagrams, respectively. 
Specific circuitry for implementing the functions described in the block 
diagram will be presented with reference to FIGS. 4, 5, and 6. 
Referring now to FIG. 1, the memory array 10 includes an N-well 12 and DRAM 
memory logic circuitry 14. The N-well is coupled to the output of a well 
pump 16. The well pump has an input for receiving a well pump enable 
signal .phi..sub.WPE, clocked by a well regulator 18. 
The well regulator 18 has an input coupled to the N-well for monitoring the 
N-well bias level, V.sub.W. The well pump enable signal .phi..sub.WPE, is 
directed to the input of a well detector enable circuit 20. 
A well detector enable circuit 20 clocks a well detector enable signal, 
.phi..sub.WDE. The well detector enable circuit includes a first input 
coupled to .phi..sub.WPE and a second input coupled to V.sub.W. 
This well detector enable signal, .phi..sub.WDE, is directed to a first 
input of a well detector circuit 22. A second input of the well detector 
circuit 22 is coupled to the N-well 12 and monitors V.sub.W. The well 
detector 22 clocks a gate control signal, V.sub.WH. 
A NAND gate 24 receives the gate control signal, V.sub.WH, at a first input 
and receives the external control signal, RAS at a second inverting input. 
The NAND gate 24 clocks the internal control signal, RAS (INT), which is 
coupled to the control input 26 of the DRAM memory logic circuitry 14. 
The operation of the circuit depicted in FIG. 1 will now be described with 
reference to FIG. 2. FIG. 2 is a timing diagram depicting the voltage 
levels, V.sub.CC and V.sub.W, as a function of time. Additionally, the 
states of the gate control signal, V.sub.WH, the internal control signal, 
RAS, the well detector enable signal, .phi..sub.WDE, and the well pump 
enable signal, .phi..sub.WPE are depicted. 
Referring now to FIG. 2, at time T.sub.0 the external power supply is 
turned on and the external power supply voltage level begins to increase. 
At time T.sub.1 the external voltage supply level is equal to the full 
value V.sub.CC. Note that the bias voltage level of the N-well 12 
increases more slowly than the external power supply voltage. The well 
regulator clocks .phi..sub.WPE high whenever V well is less than a 
reference voltage equal to 1.5 V.sub.CC. When .phi..sub.WPE is clocked 
high the well pump is enabled and transfers charge to the N-well to 
increase the bias voltage level, V.sub.W, of the well. The quantity 
V.sub.W increases more slowly than the external power supply voltage level 
because the capacitance of the N-well is high and a substantial amount of 
charge must be pumped in the N-well to increase V.sub.W to 1.5 V.sub.CC. 
At time T.sub.4, V.sub.W is equal to 1.5 V.sub.CC and .phi..sub.WPE is 
clocked low by the voltage regulator 18. If V well is above 1.5 V.sub.CC 
then charge will be transferred from the well to the ground tunnel of the 
external power supply via the well regulator 18. Note that the well 
regulator 18, well pump 16, and N-well 12 are coupled to form a feedback 
loop to maintain the value of V.sub.W at 1.5 V.sub.CC. 
The well detector enable circuit 20 clocks .phi..sub.WDE high when 
.phi..sub.WPE is high and V.sub.W is less than V.sub.CC +V.sub.T, where 
V.sub.T is the threshold voltage of a PMOS transistor. When .phi..sub.WDE 
is clocked high, the well detector circuit 22 is enabled. The signal 
.phi..sub.WDE is clocked low when V.sub.W is greater than V.sub.CC 
+V.sub.T. The well detector 22 is disabled when .phi..sub.WDE is clocked 
low. In FIG. 2 .phi..sub.WDE is clocked low at time T.sub.3. 
The well detector 22 clocks V.sub.WH to the low voltage state when V.sub.W 
is less than V.sub.CC and clocks V.sub.WH to the high voltage state at 
time T.sub.2 when V.sub.W is greater than V.sub.CC. 
The function of the gate control signal, V.sub.WH, will now be described. 
Table 1 is a truth table for the NAND gate 24 with the inverting input. 
When V.sub.WH is low the external control signal, RAS (INT), is high 
regardless of the state of the external control signal, RAS. Thus, when 
V.sub.W is less than V.sub.CC, RAS (INT) is always in the high voltage 
state and the chip is always in the precharge state. As described above, 
during the precharge state the bit lines are biased to V.sub.CC /2. 
TABLE 1 
______________________________________ 
V.sub.WH RAS 
##STR1## 
______________________________________ 
L H H 
L L H 
H H H 
H L L 
______________________________________ 
If the external control signal, RAS, were directly connected to the memory 
array control input 26, then the active state of the memory array 10 could 
be initiated during the period T.sub.0 to T.sub.2. If the active state 
were initiated during this time, the sense amps would pull half of the bit 
lines to V.sub.CC and the junction between those bit lines and the N-well 
would be forward biased, thereby inducing charge injection and bipolar 
latchup. Thus, when V.sub.W is less than the gate 24 prevents the external 
control signal, RAS, from affecting the value of RAS (INT) received at the 
control input 26. The voltage levels on the bit lines are maintained at 
V.sub.CC /2. 
When the well bias level, V.sub.W, increases to V.sub.CC, then V.sub.WH is 
clocked low to release the chip from the well detector 22 and make the 
gate 24 transparent to the RAS signal. Referring back to Table 1, when 
V.sub.WH is high, RAS (INT) is equal to RAS. 
As will be described more fully below, the well detector is a CMOS 
differential amplifier with the inverting input coupled to V.sub.CC and 
the non-inverting input coupled to V.sub.W. This amplifier draws current 
and dissipates power. The well detector 22 performs no useful function 
once V.sub.W is greater than V.sub.CC. Accordingly, the well detector 
enable circuit 20 clocks .phi..sub.WPE low at time T.sub.2 when V.sub.W is 
equal to about V.sub.CC +V.sub.T. Thus the power dissipation of the system 
is minimized to preserve the inherent low power features of CMOS 
technology. 
The functioning of the system during a V.sub.CC bump will now be described 
with reference to the timing diagram of FIG. 3. In FIG. 3, V.sub.CC bumps 
from four volts to seven volt between time X.sub.1 and time X.sub.4. 
At time X.sub.1, V.sub.W is equal to 1.5 V.sub.CC, V.sub.WH is low, the 
NAND gate 24 is transparent, and the state of RAS (INT) is equal to the 
state of RAS. Thus, the chip is under the control of the external control 
signal, RAS. At time X.sub.2 .phi..sub.WPE is clocked high because V.sub.W 
is less than 1.5 V.sub.CC. Clocking .phi..sub.WPE high enables the well 
pump 16. The well pump 16 begins transferring charge to the N-well to 
increase V.sub.W. As described above, the rate of increase of V.sub.W is 
less than the rate of increase of V.sub.CC due to N-well capacitance. 
At time X.sub.3, V.sub.CC is greater than V.sub.W, and V.sub.WH is clocked 
low to set RAS (INT) high and force the chip into the precharge state. At 
this point, the external control signal, RAS, has no effect on the state 
of the memory array. 
The magnitude of V.sub.W continues to increase due to the action of the 
charge pump and, at time X.sub.5, V.sub.W is equal to V.sub.CC and the 
well detector clock V.sub.WH high to release the chip and restore control 
of the chip to the external control signal, RAS. 
At time X.sub.6, the well detector enable circuit clocks .phi..sub.WDE low 
to disable the well detector and conserve power. At time X.sub.7, V.sub.W 
is again equal to 1.5 V.sub.CC and .phi..sub.WPE is clocked low to disable 
the well pump 16. 
FIG. 4 is a circuit diagram of the well regulator 18. The well regulator 
includes a biasing circuit 29 comprising first and second PMOS biasing 
transistors 30 and 31. The source terminal of the first biasing transistor 
30 is coupled to a V.sub.W input 33, the gate is coupled to V.sub.CC, and 
the drain terminal is coupled to a biasing node 34. The source terminal of 
the second biasing transistor 31 is coupled to the biasing node 34, the 
gate is coupled to ground, and the drain terminal is coupled to ground 35. 
The CMOS comparator 36 is formed by a first series circuit including a 
first input transistor 37 and NMOS transistor 38, and by a second series 
circuit including second input transistor 39 and NMOS transistor 40. The 
first input transistor 37 has its source terminal coupled to V.sub.CC, its 
gate coupled to the biasing node 34, and its drain terminal coupled to an 
output node 41. NMOS transistor 38 has its drain terminal coupled to 
output node 41 and its source terminal coupled to ground. The second input 
transistor 39 has its source terminal coupled to V.sub.CC, and its drain 
terminal coupled to circuit node 42. The gates of NMOS transistors 38 and 
40 are coupled to circuit node 42. 
A reference circuit 43 includes PMOS transistor 44, having its source 
terminal coupled to V.sub.CC and its drain terminal and gate coupled to 
reference node 45 and PMOS transistor 46, having its source terminal 
coupled to reference node 45 and its drain terminal and gate coupled to 
ground. 
The output node 41 is coupled to a .phi..sub.WPE terminal 47 by inverters 
48a and b. 
The operation of the circuit depicted in FIG. 4 will now be described. The 
(W/L) ratios of transistors 44 and 46 in the reference circuit 43 are 
equal so that the voltage level at the reference node 45 is V.sub.CC /2. 
Accordingly, the input voltage, V.sub.2, at the gate of the second input 
transistor 39 of the CMOS comparator 36 is set at V.sub.CC /2. 
The transistors 30 and 31 of the biasing circuit 29 each have the same 
(W/L) ratio. The voltage level at the biasing node 34 is greater than 
V.sub.CC /2 if V.sub.WELL is greater than 1.5 V.sub.CC and less than 
V.sub.CC /2, if V.sub.WELL is less than 1.5 V.sub.CC. The input voltage, 
V.sub.1, at the gate of the first transistor 37 of the CMOS comparator 36 
is coupled to the biasing node. 34 Accordingly, V.sub.1 is greater than 
V.sub.2 if V.sub.WELL is greater than 1.5 V.sub.CC and V.sub.1 is less 
than V.sub.2 if V.sub.WELL is less than 1.5 V.sub.CC. 
If V.sub.1 is greater than V.sub.2 then the voltage level on the output 
node 41 is low and if V.sub.1 is less than V.sub.2 then the voltage level 
on the output node 41 is high. The voltage level on .phi..sub.WPE terminal 
47 is the same as the voltage level on the output node 41. Accordingly, 
the well regulator circuit 18 clocks .phi..sub.WPE high when V.sub.WELL 
is less than 1.5 V.sub.CC and clocks .phi..sub.WPE low when V.sub.WELL is 
greater than 1.5 V.sub.CC. 
A circuit diagram of the charge pump 16 is depicted in FIGS. 5A and 5B. 
FIG. 5C is a phase diagram of the clock signals utilizing the circuit 
pump. Referring now to FIG. 5A, a NAND gate 48 has a first input coupled 
to the .phi..sub.WPE terminal 47. The output of the NAND gate 48 is 
coupled to the input of the delay 49 with the output of the delay 49 
coupled to a second input of NAND gate 48. The output of the delay 49 is 
coupled to the input of a clock generator 50. Clock generator 50 provides 
clock outputs .phi..sub.WP1, .phi..sub.WP2B and .phi..sub.WP2 at clock 
outputs 51, 52, 53, respectively. 
Clock generator output 53 is coupled to a first circuit node 54 by 
depletion device 55, clock generator output terminal 52 is coupled to a 
second circuit node 56 via capacitor 57, and clock generator terminal 51 
is coupled to a third circuit node 58 by capacitor 60. The voltage level 
on the first circuit node 54 is designated V.sub.A, on the second circuit 
node 56 V.sub.B, and on the third circuit node 58 V.sub.C. 
The first circuit node 54 is coupled to a V.sub.WELL output terminal 62 by 
NMOS transistor 64. The first terminal 54 is coupled to the second 
terminal 56 by NMOS transistor 66. The first circuit node 54 is coupled to 
V.sub.CC by NMOS transistor 68. The gates of transistors 66 and 68 are 
coupled to the third circuit node 58. The gate of transistor 64 is coupled 
to the second circuit node 56. 
NMOS transistor 70 has one terminal coupled to the third node 58, a second 
terminal coupled to V.sub.CC, and its gate coupled to V.sub.CC. Transistor 
72 has a first terminal coupled to the third node 58 and a second terminal 
coupled to node 74. Node 74 is coupled to the first terminal of transistor 
76 and to the gate of transistor 76. A second terminal of transistor 76 is 
coupled to circuit node 78. Circuit node 78 is coupled to a first terminal 
of transistor 80 and to the gate of transistor 80. The second terminal of 
transistor 80 is coupled to V.sub.CC. The gate of transistor 72 is coupled 
to the third node 58 and to V.sub.CC by NMOS transistor 82. 
NMOS Transistor 84 has one terminal coupled to the V.sub.WELL terminal 62 
and a second terminal coupled to circuit node 86 and has its gate also 
coupled to circuit node 86. NMOS transistor 88 has a first terminal 
coupled to node 86, a second terminal coupled to node 90 and has its gate 
also being coupled to node 90. NMOS transistor 92 has a first terminal 
connected to node 90, a second terminal connected to node 94. Node 94 is 
coupled to the gates of transistors 82 and 92 and also to the second 
circuit node 56. The V.sub.WELL terminal 62 is coupled to V.sub.CC by NMOS 
transistor 96. The gate of transistor 96 is also coupled to V.sub.CC. 
FIG. 5B is a timing diagram of the output signals from the clock generator 
50. The operation of the charge pump will now be described with reference 
to FIG. 5B. During time period I the first circuit node 54 is coupled to 
the V.sub.WELL output terminal 62 because .phi..sub.WP2B is high and 
transistor 64 is conducting. The first circuit node is isolated from the 
V.sub.CC terminal because .phi..sub.WP1 is low and transistor 68 is not 
conducting. 
During time period II the first circuit node 54 is isolated from the 
V.sub.WELL terminal 62 because .phi..sub.WP2B is clocked low and 
transistor 64 is off. The voltage level V.sub.C, on the third node 58, is 
clocked from the low state to the high state by .phi..sub.WP1. 
Accordingly, transistors 66 and 68 are switched on and the first and 
second nodes 54 and 56 are charged to V.sub.CC. 
During time period III, .phi..sub.WP1 is clocked low to switch off 
transistors 66 and 68 and isolate the first and second circuit nodes 54 
and 56 from V.sub.CC. .phi..sub.WP2 is clocked high and, because V.sub.A 
has been precharged to V.sub.CC during time period II, V.sub.A is boosted 
to about 10 volts. Additionally, .phi..sub.WP2B is also clocked high and 
the voltage level V.sub.B is boosted to about 10 volts. Because the second 
node is high, transistor 64 is switched on and the first node is coupled 
to the V.sub.WELL terminal 62. The excess charge pumped into the first 
circuit node 54 by the .phi..sub.WP2 signal is transferred to the well to 
increase V.sub.WELL. This pumping continues until .phi..sub.WPE is clocked 
low by the well detector. Accordingly, the charge pump increases 
V.sub.WELL to 1.5 V.sub.CC. 
FIG. 6 is a circuit diagram depicting circuitry for the well detector 22 
and the well detector enabling circuit 20. The well detector 22 includes a 
CMOS differential amplifier 50 having its inverting input coupled to 
V.sub.CC terminal 40 and its non-inverting input coupled to V.sub.W 
terminal 34. The differential amplifier 150 is coupled to the ground 
terminal 40 of the power supply via NMOS disabling transistor 152. The 
gate of the disabling transistor 152 receives the .phi..sub.WDE signal. 
The output of the differential amplifier 150 is coupled to a holding node 
154. A PMOS holding transistor 156 has its source terminal coupled to 
V.sub.CC terminal 44, its gate coupled to .phi..sub.WDE, and its drain 
terminal coupled to a holding node 154. Inverter 158 has its input coupled 
to holding node 154 and its output coupled to circuit node 160. Circuit 
node 160 is coupled to the V.sub.CC terminal 44 by capacitor 162. Inverter 
164 has its input coupled to circuit node 160 and its output coupled to a 
well detector output terminal 166. 
The well detector enabling circuit 20 includes a detection circuit 170, 
including a first PMOS detection transistor 172, having its source 
terminal coupled to the V.sub.W terminal 34, its drain terminal coupled to 
a circuit node 176, and its gate coupled to circuit node 176. Second 
detection transistor 178 has its source terminal coupled to node 176, its 
drain terminal coupled to circuit node 180, and its gate coupled to 
circuit node 180. Circuit node 180 is coupled to a CMOS current source 
182. The current source 182 is coupled to the ground terminal 40 by NMOS 
transistor 184. NMOS transistor 184 has its gate coupled to the 
.phi..sub.WPE signal. 
A PMOS output transistor 186 has its source terminal connected to the 
V.sub.CC terminal 44, its drain terminal coupled to an output node 188, 
and its gate coupled to circuit node 180. The output node 188 is coupled 
to the ground terminal 40 by a CMOS current source 190. 
Output terminal 188 is coupled to a first input of a well detector NAND 
gate 192 via inverter 194. The second input of the NAND gate 192 is 
coupled to the output terminal 166 of the well detector 22. The output of 
NAND gate 192 is coupled to the gate of the disabling transistor 152 and 
provides the .phi..sub.WDE signal. 
The detection circuit 170 is activated when .phi..sub.WDE is clocked high 
and NMOS transistor 184 conducts. Circuit node 180 is pulled low, thereby 
creating a negative potential at the gate of the second detection 
transistor 178. The second detection transistor 178 is connected in the 
diode configuration, i.e., the gate is coupled to the drain. When V.sub.GS 
of transistor 178 is equal to -V.sub.T, transistor 178 conducts and pulls 
node 176 low. Similarly, when node 176 is pulled low the first detection 
transistor 172 begins to conduct. Because both the detection transistors 
172 and 178 are coupled in the diode configuration the voltage level at 
node 176 is equal to V.sub.W -V.sub.T and the voltage level at node 180 is 
equal to V.sub.W -2V.sub.T. Because the gate of the output transistor 186 
is coupled to node 180, V.sub.G of transistor 186 is equal to V.sub.W 
-2V.sub.T. Thus, output transistor 186 conducts when V.sub.GS is equal to 
-V.sub.T or when V.sub.W is less than or equal to V.sub.CC +V.sub.T. When 
the output transistor 186 conducts output node 188 is charged to V.sub.CC. 
In summary, with .phi..sub.WPE clocked high, the voltage level at the 
output node 188 is low when V.sub.W is greater than V.sub.CC +V.sub.T and 
is high when V.sub.W is less than V.sub.CC +V.sub.T. Table 2 is a truth 
table for the well detector enable NAND gate 192, where V.sub.0 is the 
voltage level at the output node 188. 
TABLE 2 
______________________________________ 
V.sub.WH V.sub.0 
##STR2## 
______________________________________ 
L H H 
L L H 
H H H 
H L L 
______________________________________ 
From Table 2 it is apparent that V.sub.WH acts as a gate control signal for 
the well detector enable NAND gate 192. When V.sub.WH is low, i.e., when 
the array is forced into precharge, .phi..sub.WDE is always high and the 
well detector 22 is always enabled. However, when V.sub.WH is high, i.e., 
the array is released, the state .phi..sub.WDE is the same as the state of 
V.sub.0. 
The voltage state of the .phi..sub.WDE signal be analyzed for the case of a 
voltaqe bump as illustrated in FIG. 3. At time X.sub.1, V.sub.WH is high 
and V.sub.0 is low because V.sub.W is greater than V.sub.CC +V.sub.T. 
Accordingly, from Table 1, .phi..sub.WDE is low, the disabling transistor 
152 is off, and the differential amplifier 150 is disabled. Thus, when the 
N-well is properly biased with respect to V.sub.CC, the differential 
amplifier 150 is disabled to conserve power. 
At time X.sub.2, V.sub.W is less than 1.5 V.sub.CC, and .phi..sub.WPE is 
clocked high by the well regulator. Accordingly, the detection circuit 170 
of the well detector enable circuit 20 is activated by transistor 184. The 
signal V.sub.0 is clocked high because V.sub.W is less than V.sub.CC 
+V.sub.T and the output transistor 186 conducts to charge the output node 
188. V.sub.WH is still high because node 154 is coupled to node V.sub.CC 
by the PMOS transistor 156. Thus, from the Table 2, with V.sub.0 high and 
V.sub.WH high, .phi..sub.WDE is clocked high and the disabling transistor 
152 conducts to enable the difference amplifier 150. Additionally, when 
.phi..sub.WDE is clocked high, the holding transistor 156 is deactivated 
to decouple the holding node 154 from the V.sub.CC terminal. The output of 
the difference amplifier 150 is high because V.sub.W is greater than 
V.sub.CC at time X.sub.2. Accordingly, V.sub.WH remains high. 
At time X.sub.3 the output of the differential amplifier 150 goes low 
because V.sub.W is less than V.sub.CC. Accordingly, V.sub.WH is clocked 
low and RAS (INT) is held high to force the array into the precharge 
state. From Table 2, .phi..sub.WDE remains high and the differential 
amplifier 150 remains enabled. 
During the period from X.sub.4 to X.sub.5, V.sub.W is less than V.sub.CC, 
so that the output of the difference amplifier 150 is low and V.sub.WH 
remains low. Additionally, V.sub.0 is high because V.sub.W is less than 
V.sub.CC +V.sub.T. From Table 2, .phi..sub.WDE remains high and the 
differential amplifier 150 continues to be enabled and hold V.sub.WH low. 
Between X.sub.5 and X.sub.6, V.sub.W is greater than V.sub.CC but less than 
V.sub.CC +V.sub.T. V.sub.WH is clocked high by the difference amplifier 
150 because V.sub.W is greater than V.sub.CC. V.sub.0 still remains low 
because V.sub.W is less than V.sub.CC +V.sub.T. Accordingly, V.sub.WDE is 
still high and the differential amplifier 150 remains enabled during this 
short time period to charge the holding capacitor 162 to hold V.sub.WH 
high during the transition period when the difference amplifier 150 is 
disabled. 
At time X.sub.6, V.sub.W is greater than V.sub.CC +V.sub.T, the output 
transistor 186 is deactivated, and the output node 188 is discharged via 
the current source 190. Accordingly, V.sub.0 goes low. From Table 2, with 
V.sub.0 low and V.sub.WH high, .phi..sub.WDE is clocked low to turn off 
the disabling transistor 152 and disable the differential amplifier 150. 
The V.sub.WH signal is held high by capacitor 162 while the .phi..sub.WDE 
signal activates holding transistor 156 to charge the holding node 154 
high and hold V.sub.WH at the high voltage level. 
FIG. 7 is a circuit diagram of CMOS differential amplifier 150. In FIG. 7, 
the + input is + node 200 of input circuit 202. The - input is - node 204 
of reference circuit 206. 
A CMOS comparator 208 provides a high output at output node 154 when 
V.sub.+ &gt;V.sub.- and a low output when V.sub.+ &lt;V.sub.-. 
The voltage level at - node 204 is set at V.sub.CC /2 by reference circuit 
206 The voltage level at + node 200 is set at V.sub.WELL /2, by input 
circuit 202. 
Accordingly voltage level, V.sub.WH, at output node 154 is high when 
V.sub.W &gt;V.sub.CC and low when V.sub.W &lt;V.sub.CC. 
The present invention thus prevents forward biasing of junctions between 
the bit lines and transfer gates and N-well to prevent charge injection or 
bipolar latchup during the active cycle of the memory. The well detector 
enabling circuit reduces power dissipation by disabling the well detector 
when it is not needed. 
The invention has been explained with reference to specific embodiments. 
Other embodiments will now be apparent to those of ordinary skill in the 
art. In particular, the invention may be utilized in a memory array having 
NMOS bit line connections and transfer gates disposed in a P-type well. 
Additionally, other gating configurations than those described above may 
be utilized to attain the equivalent logical functions described herein. 
Further, the states of the various signals set forth above may be varied 
by utilizing inverters. The techniques described for controlling the 
states of the well pump enabling signal, well detector enabling signal, 
and gate control signals may be utilized in other technologies, such as 
NMOS, PMOS, or bipolar. Accordingly, it is therefore not intend that the 
invention be limited except as indicated by the appended claims.