MULTI-LAYER CAPACITORS FOR THREE-DIMENSIONAL MEMORY SYSTEMS

Methods, systems, and devices for multi-layer capacitors for three-dimensional memory systems are described. Memory cells of a memory system may include capacitors having dielectric material between multiple interfaces (e.g., concentric interfaces) of a bottom electrode and a top electrode. A bottom electrode may include a first portion wrapping around a portion of a semiconductor material that is contiguous with a channel of a transistor, and a top electrode may include a first portion wrapping around the first portion of the bottom electrode. The bottom electrode may also include a second portion wrapping around the first portion of the top electrode, and the top electrode may also include a second portion wrapping around the second portion of the bottom electrode. The dielectric material may include respective portions between each interface of the bottom electrode and top electrode which, in some examples, may be a contiguous implementation of the dielectric material.

TECHNICAL FIELD

The following relates to one or more systems for memory, including multi-layer capacitors for three-dimensional memory systems.

BACKGROUND

Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells.

DETAILED DESCRIPTION

Some memory devices may include one or more three-dimensional arrays of memory cells formed over a substrate. For example, a memory device may include multiple levels of memory cells, where a level may refer to a dimension above the substrate (e.g., a level along one or more horizontal directions above a substrate). In some implementations, a memory cell may include a capacitor operable to store a charge indicative of logic state and a switching component (e.g., a cell selection component, a transistor) operable to couple the capacitor with an access line such that the logic state may be written to, or read from, or both from the capacitor, among other operations.

Reducing the physical size of memory cells may support increased array density, and thus an increased storage capacity of a memory device for a given size, among other benefits. However, reducing the physical size of memory cells may include reducing one or more dimensions of capacitors of the memory cells which, for some capacitor architectures, may reduce a capacity of the memory cells to store a charge that corresponds to a given logic state. The reduced capacity to store charge may be associated with relatively small read margins, relatively high refresh rates, or relatively complex access circuitry, among other accompanying characteristics.

In accordance with the examples described herein, a memory device may include memory cells having capacitors that support a capacitance with a relatively compact arrangement of material portions. For example, a capacitor of a memory cell may include multiple portions (e.g., layers) of dielectric material between portions, such as concentric portions, of a first electrode (e.g., a bottom plate) and a second electrode (e.g., a top plate). The first electrode may include a first portion that wraps around or is otherwise coupled with a portion of a semiconductor material that is contiguous with a channel of a transistor (e.g., a cell selection transistor), and the second electrode may include a first portion that wraps around the first portion of the first electrode (e.g., separated by a first portion of the dielectric material between the first portion of the first electrode and the first portion of the second electrode). The first electrode may also include a second portion that wraps around the first portion of the second electrode (e.g., separated by a second portion of the dielectric material between the first portion of the second electrode and the second portion of the first electrode), and the second electrode may include a second portion that wraps around the second portion of the first electrode (e.g., separated by a third portion of the dielectric material between the first portion of the first electrode and the first portion of the second electrode). Thus, the capacitor may include three interfaces (e.g., concentric interfaces, interfaces at different relative radial positions from an axis of the capacitor) between material portions of the first electrode and the second electrode, each across a respective portion of the dielectric material, which may support a relatively high capacitance in a relatively small volume. Such techniques may support a relatively dense array architecture, including for three-dimensional arrays of memory cells, which may support relatively high storage capacity, relatively low fabrication cost, or relatively low operational latency, among other benefits.

Features of the disclosure are initially described in the context of a memory device with reference toFIG.1. Features of the disclosure are described in the context of an array architecture and fabrication operations as described with reference toFIGS.2through14B. These and other features of the disclosure are described in the context of a flowchart that relates to multi-layer capacitors for three-dimensional memory systems with reference toFIG.15.

FIG.1shows an example of a memory device100that supports multi-layer capacitors for three-dimensional memory systems in accordance with examples as disclosed herein. The memory device100may be referred to as a memory die or an electronic memory apparatus. The memory device100may include memory cells105that are programmable to store different logic states. In some cases, a memory cell105may be programmable to store two logic states, denoted a logic 0 and a logic 1. In some cases, a memory cell105may be programmable to store more than two logic states (e.g., as a multi-level cell). The memory cells105may be part of an array110(e.g., a memory array) of the memory device100, where, in some examples, an array110may refer to a contiguous set of memory cells105(e.g., a contiguous set of elements of a semiconductor chip).

In some examples, a memory cell105may store an electric charge representative of the programmable logic states in a storage component (e.g., a capacitor, a capacitive memory element, a capacitive storage element). In some examples, a charged and uncharged capacitor may represent two logic states, respectively. In some other examples, a positively charged (e.g., a first polarity, a positive polarity) and negatively charged (e.g., a second polarity, a negative polarity) capacitor may represent two logic states, respectively. DRAM or FeRAM architectures may use such designs, and the capacitor employed may include a dielectric material with linear or para-electric polarization properties as an insulator. In some examples, different levels of charge of a capacitor may represent different logic states, which, in some examples, may support more than two logic states in a respective memory cell105. In some examples, such as FeRAM architectures, a memory cell105may include a ferroelectric capacitor having a ferroelectric material as an insulating (e.g., non-conductive) layer between terminals of the capacitor. Different levels or polarities of polarization of a ferroelectric capacitor may represent different logic states (e.g., supporting two or more logic states in a respective memory cell105).

In the example of memory device100, each row of memory cells105may be coupled with one or more word lines120(e.g., WL1through WLM), and each column of memory cells105may be coupled with one or more digit lines130(e.g., DL1through DLN). Each of the word lines120and digit lines130may be an example of an access line of the memory device100. In general, one memory cell105may be located at the intersection of (e.g., coupled with, coupled between) a word line120and a digit line130. This intersection may be referred to as an address of a memory cell105. A target (e.g., selected) memory cell105may be a memory cell105located at the intersection of an activated or otherwise selected word line120and an activated or otherwise selected digit line130.

In some architectures, a storage component of a memory cell105may be electrically isolated from a digit line130by a cell selection component, which, in some examples, may be referred to as a switching component or a selector device of or otherwise associated with the memory cell105. A word line120may be coupled with the cell selection component (e.g., via a control node of the cell selection component), and may control the cell selection component of the memory cell105. For example, the cell selection component may be a transistor and the word line120may be coupled with or be a portion of a gate of the transistor (e.g., where a gate node of the transistor may be a control node of the transistor). Activating a word line120may result in an electrical connection (e.g., a closed circuit) between a respective storage component of one or more memory cells105and one or more corresponding digit lines130, which may be referred to as activating the one or more memory cells105or coupling the one or more memory cells105with a respective one or more digit lines130. A digit line130may then be accessed to write to or read from the respective memory cell105.

In some examples, memory cells105may also be coupled with one or more plate lines140(e.g., PL1through PLN). In some examples, each of the plate lines140may be independently addressable (e.g., supporting individual selection or biasing). In some examples, the plurality of plate lines140may represent or be otherwise functionally equivalent with a common plate, or other common node (e.g., a plate node common to each of the memory cells105in the array110). For implementations in which a memory cell105employs a capacitor for storing a logic state, a digit line130may provide access to a first terminal (e.g., a first plate) of the capacitor, and a plate line140may provide access to a second terminal (e.g., a second plate) of the capacitor. Although the plurality of plate lines140of the memory device100are shown as being parallel with the plurality of digit lines130, in other examples, a plurality of plate lines140may be parallel with the plurality of word lines120, or in any other configuration (e.g., a common planar conductor, a common plate layer, a common plate node).

Access operations such as reading, writing, rewriting, and refreshing may be performed on a memory cell105by activating (e.g., selecting) a word line120, a digit line130, or a plate line140coupled with the memory cell105, which may include applying a voltage, a charge, or a current to the respective access line. After selecting a memory cell105(e.g., in a read operation), a resulting signal may be used to determine the logic state stored by the memory cell105. For example, a memory cell105with a capacitive memory element storing a logic state may be selected, and the resulting flow of charge via an access line or resulting voltage of an access line may be detected to determine the programmed logic state stored by the memory cell105.

Accessing memory cells105may be controlled using a row component125(e.g., a row decoder), a column component135(e.g., a column decoder), or a plate component145(e.g., a plate decoder), or a combination thereof. For example, a row component125may receive a row address from the memory controller170and activate a corresponding word line120based on the received row address. Similarly, a column component135may receive a column address from the memory controller170and activate a corresponding digit line130. In some examples, such access operations may be accompanied by a plate component145biasing one or more of the plate lines140(e.g., biasing one of the plate lines140, biasing some or all of the plate lines140, biasing a common plate).

In some examples, the memory controller170may control operations (e.g., read operations, write operations, rewrite operations, refresh operations) of memory cells105using one or more components (e.g., row component125, column component135, plate component145, sense component150). In some cases, one or more of the row component125, the column component135, the plate component145, and the sense component150may be co-located with or otherwise included as part of the memory controller170. The memory controller170may generate row and column address signals to activate a desired word line120and digit line130. The memory controller170may also generate or control various voltages or currents used during the operation of memory device100.

A memory cell105may be written (e.g., programmed, set) by activating the relevant word line120, digit line130, or plate line140(e.g., via a memory controller170). In other words, a logic state may be stored in a memory cell105. A row component125, column component135, or plate component145may accept data, for example, via input/output component160, to be written to the memory cells105. In some examples, a write operation may be performed at least in part by a sense component150, or a write operation may be configured to bypass a sense component150.

In the case of a capacitive memory element, a memory cell105may be written by applying a voltage to (e.g., across) a capacitor, and then isolating the capacitor (e.g., isolating the capacitor from a voltage source used to write the memory cell105, floating the capacitor) to store a charge in the capacitor associated with a desired logic state. In the case of ferroelectric memory, a ferroelectric memory element (e.g., a ferroelectric capacitor) of a memory cell105may be written by applying a voltage with a magnitude high enough to polarize the ferroelectric memory element (e.g., applying a saturation voltage) with a polarization associated with a desired logic state, and the ferroelectric memory element may be isolated (e.g., floating), or a zero net voltage may be applied across the ferroelectric memory element (e.g., grounding, virtually grounding, or equalizing a voltage across the ferroelectric memory element).

A memory cell105may be read (e.g., sensed) by a sense component150when the memory cell105is accessed (e.g., in cooperation with the memory controller170) to determine a logic state written to or stored by the memory cell105. For example, the sense component150may be configured to evaluate a current or charge transfer through or from the memory cell105, or a voltage resulting from coupling the memory cell105with the sense component150, responsive to a read operation. The sense component150may provide an output signal indicative of the logic state read from the memory cell105to one or more components (e.g., to the column component135, the input/output component160, to the memory controller170).

A sense component150may include various circuitry (e.g., switching components, selection components, transistors, amplifiers, capacitors, resistors, voltage sources) configured to detect or amplify a difference in sensing signals (e.g., a difference between a read voltage and a reference voltage, a difference between a read current and a reference current, a difference between a read charge and a reference charge), which, in some examples, may be referred to as latching. In some examples, a sense component150may include a collection of circuit elements that are repeated for each of a set or subset of digit lines130coupled with the sense component150. For example, a sense component150may include a separate sensing circuit (e.g., a separate or duplicated sense amplifier, a separate or duplicated signal development component) for each of a set of digit lines130coupled with the sense component150, such that a logic state may be separately detected for a respective memory cell105coupled with a respective one of the set of digit lines130.

In some implementations, the memory device100may include one or more three-dimensional arrays of memory cells105formed over a substrate. For example, one or more arrays110may be formed above a substrate with word lines120arranged at different levels along a direction from a substrate and digit lines130arranged at different positions along a direction above a substrate (e.g., with each digit line130extending along the direction from the substrate and each word line120extending along the direction above the substrate). Additionally, or alternatively, one or more arrays110may be formed above a substrate with digit lines130arranged at different levels along a direction from a substrate and word lines120arranged at different positions along a direction above a substrate. Reducing the physical size of memory cells105may support increased density of such arrays110, and thus an increased storage capacity for a given size of the arrays110, among other benefits. However, reducing the physical size of memory cells105may include reducing one or more dimensions of capacitors of the memory cells which, for some capacitor architectures, may reduce a capacity of the memory cells105to store a charge that corresponds to a given logic state. The reduced capacity to store charge may be associated with relatively small read margins, relatively high refresh rates, or relatively complex access circuitry, among other accompanying characteristics of the memory device100.

In accordance with the examples described herein, a memory device100may include memory cells105having capacitors that support a capacitance with a relatively compact arrangement of material portions. For example, a capacitor of a memory cell105may include multiple portions (e.g., layers) of dielectric material between portions, such as concentric portions of a first electrode (e.g., a bottom plate) and a second electrode (e.g., a top plate). The first electrode may include a first portion that wraps around or is otherwise coupled with a portion of a semiconductor material that is contiguous with a channel of a transistor (e.g., a cell selection transistor), and the second electrode may include a first portion that wraps around the first portion of the first electrode (e.g., separated by a first portion of the dielectric material between the first portion of the first electrode and the first portion of the second electrode). The first electrode may also include a second portion that wraps around the first portion of the second electrode (e.g., separated by a second portion of the dielectric material between the first portion of the second electrode and the second portion of the first electrode), and the second electrode may include a second portion that wraps around the second portion of the first electrode (e.g., separated by a third portion of the dielectric material between the first portion of the first electrode and the first portion of the second electrode). Thus, the capacitor may include three interfaces (e.g., concentric interfaces, interfaces at different relative positions relative to an axis or center portion of the capacitor) between material portions of the first electrode and the second electrode, each across a respective portion of the dielectric material, which may support a relatively high capacitance in a relatively small volume. Such techniques may support a relatively dense architecture for arrays110, including for three-dimensional arrays of memory cells105, which may support relatively high storage capacity, relatively low fabrication cost, or relatively low operational latency of the memory device100, among other benefits.

In addition to applicability in memory systems as described herein, techniques for manufacturing multi-layer capacitors for three-dimensional memory systems may be generally implemented to improve the performance (including gaming) of various electronic devices and systems. Some electronic device applications, including gaming and other high-performance applications, may be associated with relatively high processing characteristics while also benefitting from relatively quick response times to improve user experience. As such, increasing processing speed, decreasing response times, or otherwise improving the performance electronic devices may be desirable. Implementing the techniques described herein may improve the performance of electronic devices by increasing the capacitance of three-dimensional arrays of volatile memory cells (e.g., DRAM cells, FeRAM cells), which may improve memory access speeds, decrease processing times, decrease latency times, improve response times, or otherwise improve user experience, among other benefits.

FIG.2shows an example of an array architecture200that supports multi-layer capacitors for three-dimensional memory systems in accordance with examples as disclosed herein. The array architecture200may illustrate an example for implementing aspects of an array110in a memory device100, which may include features formed above a substrate (not shown), such as features formed above a crystalline semiconductor wafer. For example, the array architecture200may illustrate an architecture of memory cells105, which may be implemented in a three-dimensional array110. Aspects of the array architecture200may be described with reference to an x-direction, a y-direction, and a z-direction, with the example ofFIG.2providing an illustrative cross-sectional view of features of the array architecture200in a yz-plane. In some implementations, the x-direction may be a direction over (e.g., parallel to, above) the substrate, the y-direction may be another direction over (e.g., parallel to, above) the substrate, and the z-direction may be a direction away from the substrate (e.g., perpendicular to or otherwise away from a surface of the substrate, a height direction, a thickness direction). In some other implementations, the x-direction may be a direction away from a substrate, the y-direction may be a direction over the substrate, and the z-direction may be another direction over the substrate. Aspects of the array architecture200may be repeated in various quantities and arrangements along the x-direction, the y-direction, and the z-direction to support various three-dimensional configurations of memory cells105.

In the example of array architecture200, each memory cell105includes a respective capacitor250and a respective transistor260(e.g., a cell selection transistor). Each memory cell105(e.g., of a column of memory cells105along the z-direction) may also be associated with a digit line130(e.g., digit line130-aassociated with memory cells105-aand105-b, extending along the z-direction) and a respective word line120(e.g., word line120-aassociated with memory cell105-a, word line120-bassociated with memory cell105-b, each extending along the x-direction). The word lines120may act as a gate of or be otherwise coupled with a gate of the transistors260, and biasing a word line120(e.g., with an activation bias, with a selection bias) may be operable to couple the capacitor250of a memory cell105with a digit line130(e.g., based on activating a channel of the respective transistor260). The array architecture200also includes a plate line140-acoupled with the capacitors250and extending along at least the z-direction. In some examples, the plate line140-amay be associated with a column of memory cells105that include the memory cells105-aand105-b. In some examples, the plate line140-amay also extend along the x-direction, which may include being coupled with additional memory cells105along the x-direction (e.g., as a common plate for multiple columns of memory cells105arranged along the x-direction.

Each of the memory cells105may be associated with a respective semiconductor portion205that extends along the y-direction (e.g., from the digit line130-a). At least a portion of the semiconductor portion205associated with a memory cell105may support a channel of the transistor260associated with the memory cell105. For example, the word line120-a, operating as a gate of the transistor260-a, may be operable to modulate a conductivity of a channel portion of the semiconductor portion205-a. In some examples, word lines120may be associated with one or more conductors that extend along the x-direction adjacent to the semiconductor portions205(e.g., in a pass-by gate configuration). In some examples, the word lines120may be associated with conductor portions that wrap around the semiconductor portions205(e.g., in an all-around gate configuration, where semiconductor portions205extend through openings in word lines120).

The semiconductor portions205may include various semiconductor materials, such as silicon (e.g., crystalline silicon, epitaxial silicon, polysilicon), and portions of the semiconductor portions205associated with the transistors260may be doped to support the channel characteristics of the transistors260. For example, to support an n-type transistor configuration for the transistors260, the semiconductor portions205may include n-type doping, or a portion with p-type doping between portions with n-type doping (e.g., along the y-direction), among other doping configurations. The semiconductor portions205may be formed with various cross-sectional shapes (e.g., in an xz-plane), such as with a circular cross-section, an oval cross-section, a square cross-section, a rectangular cross-section, a polygonal cross-section, and others. In some examples, the semiconductor portions205may referred to as a stud of a capacitor250or of a memory cell105.

Each capacitor250may be associated with an electrode210(e.g., a bottom electrode) coupled with a transistor260, an electrode215(e.g., a top electrode) coupled with the plate line140-a, and a dielectric material (not shown) between the electrode210and the electrode215. For example, the capacitor250-amay be associated with an electrode210-aand an electrode215-a, and so on. In various examples, the electrodes215may be formed with a same material (e.g., a contiguous material) as the plate line140-a, or may be formed with a different material than the plate line140-a, or may be otherwise electrically coupled with the plate line140-a. In some examples, at least a portion of (e.g., an outer portion of) an electrode215may be shared between capacitors250of adjacent memory cells105in an array110, which may provide a shielding effect between electrodes210of adjacent memory cells105, which may reduce disturbance effects between the adjacent memory cells105. In some examples, at least a portion of electrodes210may be formed in contact with (e.g., around an end of, in contact with an end of) respective semiconductor portions205, or may be otherwise coupled with a channel of a respective transistor260. The electrodes210and electrodes215may be formed from various materials such as titanium nitride or other conductive materials, and electrodes215may be formed with a same material as electrodes210or with a different material than electrodes210.

The electrodes210and electrodes215may include various material portions that are formed around (e.g., in a concentric manner) a respective axis255(e.g., axes along the y-direction, an axis through a respective semiconductor portion205-a, an axis along a direction of a channel of a transistor260), where such portions may be formed around an end of a respective semiconductor portion205(e.g., an end along the y-direction). For example, the electrode210-amay include a portion220-a, which may be in contact with and wrap around the semiconductor portion205-a, and a portion220-b, which may wrap around the portion220-a. In some examples, the portion220-aand the portion220-bmay be formed with a contiguous material, which may include a portion220-cthat extends at least in part along one or more radial directions (e.g., directions radial to the axis255-a) between the portion220-aand the portion220-b. Accordingly, the electrode210may be configured in a toroidal shape (e.g., a cupped shape) having a cavity (e.g., a depression, a well) on an end of the electrode210between the portion220-aand the portion220-b, as illustrated inFIG.2. Although the semiconductor portion205-ais illustrated as extending through the portion220-a, in some other examples, the portion220-amay be contiguous over (e.g., may cover) the end of the semiconductor portion205-a.

The electrode215-amay include a portion225-aand a portion225-b. The portion225-amay be arranged between the portion220-aand the portion220-b, and may wrap around the portion220-a. In some examples, the portion225-amay be contiguous over (e.g., may cover) an end of the portion220-a, an end of the portion of the semiconductor portion205-a, or both. The portion225-bmay wrap around the portion220-b, such that the portion220-bis positioned between the portion225-aand the portion225-b. In some examples, the portion225-aand the portion225-bmay be formed with a contiguous material, which may include a portion225-cthat extends at least in part along one or more radial directions (e.g., directions radial to the axis255-a) between the portion225-aand the portion225-b. In some cases, the portion225-bmay have a greater extent (e.g., along the negative y-direction) than the portion225-a. For example, the portion225-bmay extend to or beyond an end of the electrode210, as illustrated inFIG.2. Such an extension may enhance an ability of the portion225-bto act as a barrier (e.g., a shield) between adjacent memory cells105(e.g., between adjacent electrodes210), which may mitigate disturbance effects between adjacent memory cells105(e.g., disturbances associated with access operations on one or both of adjacent memory cells105).

A dielectric material between the electrode210and the electrode215may support a capacitance between the electrode210and the electrode215, with which a charge indicative of a logic state may be stored in a memory cell105. In some examples, such a dielectric material may include one or more materials that support a linear capacitance (e.g., for operating memory cells105in accordance with a DRAM architecture). In some examples, such a dielectric material may include one or more materials that support a ferroelectric capacitance (e.g., a polarization, for operating memory cells105in accordance with an FeRAM architecture).

A dielectric material may contiguously extend between portions220of the electrode210and portions225of the electrode215. For example, for the capacitor250-a, a dielectric material may include a first portion arranged between the portion220-aand the portion225-athat wraps around the portion220-a, a second portion arranged between the portion225-aand the portion220-bthat wraps around the portion225-a, and a third portion arranged between the portion220-band the portion225-bthat wraps around the portion220-b. In some cases, the dielectric material may be contiguous between the portions (e.g., with one or more portions that extend along one or more directions radial to the axis255-a). For example, the first portion of the dielectric material may be contiguous with the second portion over an end of portion225-a, and the second portion may be contiguous with the third portion over an end of the portions220-b. In such cases, the portion220-amay be contiguous with the portion220-bover an end of the first portion and the second portion, and the portion225-amay be contiguous with the portion225-bover an end of the second portion, an end of the portion220-b, and an end of the third portion. Because the dielectric material may be implemented with three concentric interfaces between an electrode210and an electrode215for each capacitor250(e.g., interfaces at different positions or layers radially from a respective axis255), the capacitors250may be referred to as three-sided stud capacitors, which may provide a relatively large capacitance in a relatively small volume.

FIGS.3through13illustrate examples of fabrication operations that support multi-layer capacitors for three-dimensional memory systems in accordance with examples as disclosed herein. For example,FIGS.3through13may illustrate operations for fabricating aspects of a material arrangement300, which may be a portion of a memory device (e.g., a portion of a memory device100), and may include aspects of the array architecture200. Each ofFIGS.3through13may illustrate aspects of the material arrangement300after different subsets of the fabrication operations for forming the material arrangement300(e.g., illustrated as a material arrangement300-aafter a first set of one or more fabrication operations, as a material arrangement300-bafter a second set of one or more fabrication operations, and so on). Each view ofFIGS.3through13may be described with reference to an x-direction, a y-direction, and a z-direction, as illustrated, which may correspond to the respective directions described with reference to the array architecture200. Aspects of the material arrangement300may be illustrated in accordance with cut planes (e.g., along xz-planes, along yz-planes) to show various embedded features of the material arrangement300.

Operations illustrated in and described with reference toFIGS.3through13may be performed by a manufacturing system, such as a semiconductor fabrication system configured to perform additive operations (e.g., deposition, epitaxy, bonding), subtractive operations (e.g., etching, trenching, planarizing, polishing), modifying operations (e.g., oxidizing, doping, reacting, converting), and supporting operations (e.g., masking, patterning, photolithography, aligning), among other operations that support the described techniques for formation of the features of the material arrangement300. In some examples, operations performed by such a manufacturing system may be supported by a process controller or its components as described herein.

Although aspects of the material arrangement300illustrate examples of relative dimensions and quantities of various features, aspects of the material arrangement300may be implemented with other relative dimensions or quantities of such features in accordance with examples as disclosed herein. Moreover, aspects of the material arrangement300may be repeated in various manners (e.g., along the x-direction, along the y-direction, along the z-direction) to support a three-dimensional architecture of memory cells105. In the following description of the material arrangement300, some methods, techniques, processes, and operations may be performed in different orders, or at different times, or otherwise modified. Further, some operations for fabricating a material arrangement300(e.g., for fabrication in accordance with an array architecture200) may be omitted from the described fabrication operations, or other operations may be added to the described fabrication operations.

FIG.3illustrates the material arrangement300(e.g., as a material arrangement300-a) after a first set of one or more fabrication operations. The first set of operations may include forming an access region320of a memory device. For example, the first set of operations may include forming one or more digit lines130-cextending along the z-direction (e.g., away from a substrate305), one or more word lines120-cextending along the x-direction (e.g., over the substrate305), and a material315, such as an oxide material, which may provide an electrical isolation between features of the access region320.

Forming the access region320may also include forming transistors260-c, which may include channels formed from portions of semiconductor material portions310. The semiconductor material portions310may be arranged in a two-dimensional array along the x-direction and the z-direction (e.g., an array in an xz-plane). Each semiconductor material portion310may extend along the y-direction (e.g., over the substrate305), and may include a channel region of a respective transistor260-cthrough, between, or adjacent to corresponding word lines120-c(e.g., operating as a gate of the respective transistor260-a). The semiconductor material portions310may extend away from the access region along the y-direction, and may be associated with exposed studs of the semiconductor material (e.g., unsupported studs).

In some examples, forming the semiconductor material portions310may implement epitaxial formation techniques (e.g., epitaxial deposition). For example, the substrate305may have a crystalline atomic arrangement, and the crystalline arrangement of the substrate305may be translated through (e.g., contiguous through) alternating portions (e.g., layers, levels) of the semiconductor material (e.g., of the semiconductor material portions310) and another material (e.g., a sacrificial material). To support such techniques, the semiconductor material and the other material may be selected to support translation of the crystalline arrangement from the substrate305as the portions are formed (e.g., deposited) along the z-direction (e.g., across boundaries between and through the semiconductor material and the other material). In some examples, the substrate305may be the same semiconductor material as the semiconductor material portions310(e.g., silicon or other semiconductor), and the other material may be a compound of the semiconductor material or another material that is otherwise compatible for translating the atomic arrangement of the substrate305. For example, the semiconductor material may be silicon (e.g., epitaxial silicon) and the other material may be silicon germanium (e.g., epitaxial silicon germanium). In some examples, the semiconductor material and the other material may also be selected to support differential processing techniques, such as selecting the other material to support being preferentially removed while maintaining portions of the semiconductor material for forming the semiconductor material portions310. In some examples, the other material may be removed (e.g., exhumed) and replaced with the material315, or another material, or various combinations thereof. Some other examples may implement other techniques for forming the semiconductor material portions310with a crystalline atomic arrangement or a polycrystalline atomic arrangement.

In some cases, the first set of operations may include doping the semiconductor material portions310. For example, for transistors260-chaving an n-type configuration, the first set of operations may include doping ends of the semiconductor material portions310, including exposed studs, with an n-type doping material (e.g., using a gas phase doping operation, using diffusion doping from a sacrificial material, or a combination thereof). Doping the ends of the semiconductor material portion310may form a concentration of an n-type dopant (e.g., a concentration greater than 1e18 per cubic centimeter (cm), a concentration greater than 1e20 per cubic cm, a concentration greater than 1e21 per cubic cm). In some examples, the first set of operations may also include doping portions of the semiconductor material portions (e.g., in the channel regions of the transistors260-c, between n-type doped portions) with a p-type doping material (e.g., to provide an npn transistor junction).

FIG.4illustrates the material arrangement300(e.g., as a material arrangement300-b) after a second set of one or more fabrication operations. The second set of operations may include operations that support forming a material405(e.g., an insulating material, such as a nitride) around ends of the semiconductor material portions310. For example, the second set of operations may include depositing the material405on exposed portions of the access region (e.g., the exposed portions of the material315) and on the exposed portions of the semiconductor material portions310.

In some examples, the second set of operations may also include forming a material410(e.g., a liner material, such as an oxide material) on at least the semiconductor material portions310(e.g., prior to forming the material405). For example, the second set of operations may include depositing the material410and subsequently depositing the material405. In some cases, the material410may be the same material as the material315(e.g., may be the same oxide material).

FIG.5illustrates the material arrangement300(e.g., as a material arrangement300-c) after a third set of one or more fabrication operations. The third set of operations may include operations that support forming a material505(e.g., an insulating material, such as an oxide) over (e.g., around) the material405. For example, the third set of operations may include depositing the material505on sidewalls of the material405. In some cases, depositing the material505may fill spaces between adjacent semiconductor material portions310and deposited material405, as illustrated inFIG.5. In some cases, the material505may be the same material as the material315, the material410, or both (e.g., may be the same oxide material).

FIG.6illustrates the material arrangement300(e.g., as a material arrangement300-d) after a fourth set of one or more fabrication operations. The fourth set of operations may include operations that support removing portions of the material505. For example, the fourth set of operations may include a recess operation configured to remove a portion of the material505while leaving other material, such as the material405, and some other portions of the material505, intact. Accordingly, removing the portions of the material505may expose at least a first portion of the material405, while leaving a second portion of the material405covered by the remaining material505.

FIG.7illustrates the material arrangement300(e.g., as a material arrangement300-c) after a fifth set of one or more fabrication operations. The fifth set of operations may include operations that support removing portions of the material405to form cavities705. For example, the fourth set of operations may include a recess operation configured to remove at least a portion of the material405while leaving other material, such as the material505, the semiconductor material portions310, or both intact. Accordingly, removing the portions of the material405may expose sidewalls around the semiconductor material portions310, and may expose sidewalls of the material505around the semiconductor material portions310. In some cases, where applicable, the fifth set of operations may include removing at least a portion of the material410, which may expose the ends of semiconductor material portions310.

In some examples, removing the portions of the material405may form one or more structures710from the remaining portions of the material405. A structure710may include a cavity (e.g., a depression, a well) in which another material, such as the material505, may be arranged. In some examples, structures710may provide mechanical support for subsequent features of the material arrangement300. In some examples, a presence of structures710may be indicative that aspects of the operations described herein have been performed to form the material arrangement300.

FIG.8illustrates the material arrangement300(e.g., as a material arrangement300-f) after a sixth set of one or more fabrication operations. The sixth set of operations may include operations that support forming a material805(e.g., a conductive material, such as titanium nitride) on exposed portions of the material arrangement300. For example, the sixth set of operations may include depositing the material805within each of the cavities705to cover exposed sidewalls of the material505within the cavities705, as well as depositing the material805to cover the semiconductor material portions310within the cavities705.

The material805within each cavity705may form the electrode210as described with reference toFIG.2. For example, the material805deposited on the semiconductor material portions310may form the portion220-aof the electrode210, and the material805deposited on the sidewalls of the material505within the cavities705may form the portion220-bof the electrode210.

FIG.9illustrates the material arrangement300(e.g., as a material arrangement300-g) after a seventh set of one or more fabrication operations. The seventh set of operations may include operations that support forming a material905(e.g., a placeholder material, a sacrificial material) to fill the cavities705. For example, the seventh set of operations may include depositing the material905to cover exposed portions of the material arrangement300, which may fill the cavities705with the material905, or cover an outer sidewall910of the material805(e.g., a sidewall exterior to the cavities705), or both. In some cases, the seventh set of operations may include removing a portion of the material905, for example using a recess operation, to recess the material905into the cavities705and to expose the outer sidewall910of the material805.

FIG.10illustrates the material arrangement300(e.g., as a material arrangement300-h) after a eighth set of one or more fabrication operations. The eighth set of operations may include operations that support removing the outer sidewall910of the material805to separate the material805within each cavity705from the material805within a different cavity705(e.g., to separate electrodes210of adjacent capacitors250). For example, the eighth set of operations may include a recess operation to remove the outer sidewall910of the material805to expose the material505.

FIG.11illustrates the material arrangement300(e.g., as a material arrangement300-i) after a ninth set of one or more fabrication operations. The ninth set of operations may include operations that support removing the remaining portions of the material905to expose the material805within each cavity705. For example, the ninth set of operations may include an etching procedure to remove the material905, which may expose the material805(e.g., corresponding to portions220-aand portions220-bof electrodes210).

FIG.12illustrates the material arrangement300(e.g., as a material arrangement300-j) after a tenth set of one or more fabrication operations. The tenth set of operations may include operations that support removing the remaining portions of the material505to expose portions of the material805(e.g., to expose electrodes210). For example, the tenth set of operations may include a material removal procedure, such as a stop on film process, to remove remaining exposed portions of the material505. In some examples, removing the material505may expose sidewalls of the material805(e.g., outer sidewalls of the portions220-b).

FIG.13illustrates the material arrangement300(e.g., as a material arrangement300-k) after an eleventh set of one or more fabrication operations. The eleventh set of operations may include operations that support forming electrodes215and dielectric material between the electrodes215and the electrodes210. For example, the eleventh set of operations may include depositing a material1305on the exposed portions of the material805(e.g., on the exposed portions of the electrode210). Additionally, the eleventh set of operations may include depositing a material1310on the material1305.

The material1305may be an example of a dielectric material, which may have a relatively high dielectric constant (e.g., a relative to other insulating materials of the material arrangement300, such as the material405, the material505, or both), and may accordingly be referred to as a high-k material. In some examples, the material1305may have ferroelectric properties, which may support operation in accordance with a ferroelectric capacitance. The material1310may be an example of a conductive material such as titanium nitride, and may act as an electrode for memory cells105-c(e.g., electrodes215). Accordingly, the eleventh set of operations may form capacitors250of the memory cells105-c, for which the material805may support first plates (e.g., electrodes210) of the capacitors250, the material1310may support second plates (e.g., electrodes215) of the capacitor250, and the material1305may support a dielectric film between the first plates and the second plates.

In some cases, the eleventh set of operations may include forming a plate line140-b(e.g., a conductive plate) extending along the z-direction, and a contact1315arranged above (e.g., in the z-direction, on top of the plate line140-b). For example, eleventh set of operations may include depositing a conductive material to contact the material1310, which may form the plate line140-b, and depositing a second conducive material to form the contact1315. In some cases, the conductive material of the plate line140-bmay be different than the conductive material of the electrode210, the electrode215, or both. For example, the conductive material of the plate line140-bmay include boron, silicon, germanium, or a combination thereof, such as a boron silicon germanium alloy.

Because the material1305may have a relatively high dielectric property, the material1305may provide a similarly high capacitance for the capacitor of the memory cells105-c. Additionally, the layered arrangement (e.g., three concentric layers) of the material1305may support a relatively high surface area of the material1305for the capacitors250(e.g., relative to an arrangement having fewer layers), which may support relatively high capacitance in a relatively small volume.

FIGS.14A and14Bshows an example of the material arrangement300(e.g., as the material arrangement300-k) in a cross-sectional view in a yz-plane and in a cross-sectional view in an xz-plane, respectively. For example,FIGS.14A and14Bmay illustrate aspects of a three-dimensional array of memory cells105-cwith word lines120-cextending along the x-direction, digit lines130-cextending along the z-direction, and plate line140-bextending along the x-direction and along the z-direction.

The memory cells105-cmay each include a capacitor250having an electrode1405(e.g., a bottom electrode), an electrode1410(e.g., a top electrode) coupled with the plate line140-b, and a dielectric material1415between the electrode1405and the electrode1410. The electrode1405may extend around a central axis extending along the y-direction and through the portion of the semiconductor material1425.

Each electrode1405may include one or more portions220, such as a portion1405-a, which may be in contact with the portion of the semiconductor material1425and may wrap around (e.g., be concentric with) the central axis (e.g., around the semiconductor material1425), and a portion1405-bwhich may wrap around the portion1405-aand may be contiguous with the portion1405-a. As shown, the portion1405-amay wrap around an end of the semiconductor material1425. Alternatively, the portion1405-amay form a lumen with an open end around the semiconductor material1425.

The electrode1410may include a second conductive material, which may be a same material as the electrode1405, or may be a different conductive material. The electrode1410may wrap around the central axis, and may include one or more portions225, such as a portion1410-aand a portion1410-b. The portion1410-amay be arranged between the portion1405-aand the portion1405-b, and may wrap around the portion1405-a. Additionally, the portion1410-bmay wrap around the portion1405-b. In some cases, the portion1410-bmay have a greater length (e.g., in the y-direction) than the portion1410-a. For example, the portion1410-bmay extend to or beyond an end of the electrode1405. Such an extension may allow the portion1410-bto act as a barrier (e.g., a shield) between adjacent memory cells105-c, which may mitigate disturb effects between adjacent memory cells105-c. In some examples, the portion1410-amay be contiguous over an end of the portion1405-aand over an end of the portion of the semiconductor material1425.

The dielectric material1415may contiguously extend between portions of the electrode1405and portions of the electrode1410. For example, the dielectric material1415may include a portion1415-aarranged between the portion1405-aand the portion1410-awhich wraps around the portion1405-a, a portion1415-barranged between the portion1410-aand the portion1405-bwhich wraps around the portion1410-a, and a portion1415-carranged between the portion1405-band the portion1410-bwhich wraps around the portion1405-b.

In some cases, the dielectric material1415may be contiguous between the portions thereof. For example, the portion1415-amay be contiguous with the portion1415-bover an end of portion1410-a, and the portion1415-bmay be contiguous with the portion1415-cover an end of the portions1410-b. In such cases, the portion1405-amay be contiguous with the portion1405-bover an end of the first portion and the second portion, and the portion225-amay be contiguous with the portion1410-bover an end of the portion1415-b, an end of the portion1405-b, and an end of the portion1415-c.

FIG.15shows a flowchart illustrating a method1500that supports multi-layer capacitors for three-dimensional memory systems in accordance with examples as disclosed herein. The operations of method1500may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally, or alternatively, one or more controllers may perform aspects of the described functions using special-purpose hardware.

At1505, the method may include forming a cell selection transistor (e.g., a transistor260) of a memory cell, the cell selection transistor including a channel portion of a semiconductor material (e.g., a semiconductor material portion310) extending along a first direction (e.g., a y-direction) over a substrate (e.g., a substrate305).

At1510, the method may include forming a first material (e.g., a material405) around an end (e.g., about the x-direction) of the semiconductor material along the first direction.

At1515, the method may include forming a second material (e.g., a material505) around the first material.

At1520, the method may include forming a cavity (e.g., a cavity705) based at least in part on removing a portion of the first material, the cavity exposing a sidewall around the semiconductor material and exposing a sidewall of the second material around the semiconductor material.

At1525, the method may include forming a first electrode (e.g., an electrode210) of a capacitor of the memory cell based at least in part on forming a first conductive material (e.g., a material805) in the cavity, the first conductive material including a first portion (e.g., a portion220-a) along the sidewall around the semiconductor material, a second portion (e.g., a portion220-b) along the sidewall of the second material and around the first portion, and a third portion (e.g., a portion220-c) coupling the first portion with the second portion along one or more directions radial from (e.g., radially from the x-direction) the first portion.

At1530, the method may include forming a dielectric material (e.g., a material1305) over the first electrode and at least partially within the cavity.

At1535, the method may include forming a second electrode (e.g., an electrode215) of the capacitor of the memory cell over the dielectric material based at least in part on forming a second conductive material (e.g., a material1310) at least partially within the cavity.

In some examples, an apparatus (e.g., a manufacturing system) as described herein may perform a method or methods, such as the method1500. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof for performing the following aspects of the present disclosure:Aspect 1: A method or apparatus including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming a cell selection transistor of a memory cell, the cell selection transistor including a channel portion of a semiconductor material extending along a first direction over a substrate; forming a first material around an end of the semiconductor material along the first direction; forming a second material around the first material; forming a cavity based at least in part on removing a portion of the first material, the cavity exposing a sidewall around the semiconductor material and exposing a sidewall of the second material around the semiconductor material; forming a first electrode of a capacitor of the memory cell based at least in part on forming a first conductive material in the cavity, the first conductive material including a first portion along the sidewall around the semiconductor material, a second portion along the sidewall of the second material and around the first portion, and a third portion coupling the first portion with the second portion along one or more directions radial from the first portion; forming a dielectric material over the first electrode and at least partially within the cavity; and forming a second electrode of the capacitor of the memory cell over the dielectric material based at least in part on forming a second conductive material at least partially within the cavity.Aspect 2: The method or apparatus of aspect 1, where the second conductive material includes a fourth portion between the first portion of the first conductive material and the second portion of the first conductive material, a fifth portion around the second portion of the first conductive material, and a sixth portion coupling the fourth portion with the fifth portion along one or more directions radial from the fourth portion.Aspect 3: The method or apparatus of any of aspects 1 through 2, where the first conductive material is formed over the end (e.g., along the x-direction) of the semiconductor material.Aspect 4: The method or apparatus of any of aspects 1 through 3, where forming the cavity exposes a portion of the first material at an end of the cavity (e.g., along the x-direction) that extends between semiconductor material and the sidewall of the second material.Aspect 5: The method or apparatus of any of aspects 1 through 4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming a third material in the cavity after forming the first conductive material; removing a portion of the first conductive material external to the cavity after forming the third material; and removing the third material from the cavity after removing the portion of the first conductive material external to the cavity, where forming the dielectric material is performed after removing the third material.Aspect 6: The method or apparatus of any of aspects 1 through 5, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for removing the second material, where forming the dielectric material is performed after removing the second material.Aspect 7: The method or apparatus of any of aspects 1 through 6, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming a conductive plate extending along a second direction away from the substrate and along a third direction over the substrate, the conductive plate in contact with a portion of the second conductive material.Aspect 8: The method or apparatus of any of aspects 1 through 7, where the first material includes a nitride material and the second material includes an oxide material.

It should be noted that the methods described herein are possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:Aspect 9: An apparatus, including: a cell selection transistor of a memory cell (e.g., a memory cell105), the cell selection transistor including a channel extending along a first direction (e.g., a y-direction) over a substrate (e.g., a substrate305); and a capacitor of the memory cell coupled with the channel of the cell selection transistor and associated with an axis along the first direction over the substrate, the capacitor including: a first portion of a first electrode of the capacitor aligned along the axis; a first portion of a dielectric of the capacitor around the first portion of the first electrode about the axis; a first portion of a second electrode of the capacitor around the first portion of the dielectric about the axis; a second portion of the dielectric around the first portion of the second electrode about the axis; a second portion of the first electrode around the second portion of the dielectric about the axis; a third portion of the dielectric around the second portion of the first electrode about the axis; and a second portion of the second electrode around the third portion of the dielectric about the axis.Aspect 10: The apparatus of aspect 9, further including: a semiconductor material portion, a first portion of the semiconductor material portion including the channel of the cell selection transistor, and the first portion of the first electrode around a second portion of the semiconductor material portion about the axis.Aspect 11: The apparatus of aspect 10, where the first portion of the first electrode is in contact with the second portion of the semiconductor material portion.Aspect 12: The apparatus of any of aspects 10 through 11, where the first portion of the first electrode is contiguous over an end of the second portion of the semiconductor material portion.Aspect 13: The apparatus of any of aspects 9 through 12, where the first portion of the dielectric is contiguous with the second portion of the dielectric over an end of the first portion of the second electrode along the first direction.Aspect 14: The apparatus of any of aspects 9 through 13, where the second portion of the dielectric is contiguous with the third portion of the dielectric over an end of the second portion of the first electrode along the first direction.Aspect 15: The apparatus of any of aspects 9 through 14, where the first portion of the first electrode is contiguous with the second portion of the first electrode over an end of the first portion of the dielectric along the first direction and over an end of the second portion of the dielectric along the first direction.Aspect 16: The apparatus of aspect 15, where the first portion of the second electrode is contiguous over an end of the first portion of the dielectric along the first direction and contiguous over an end of the first portion of the first electrode along the first direction.Aspect 17: The apparatus of any of aspects 9 through 16, where the first portion of the second electrode is contiguous with the second portion of the second electrode over an end of the second portion of the dielectric and over an end of the third portion of the dielectric.Aspect 18: The apparatus of any of aspects 9 through 17, where the cell selection transistor further includes a gate including a first access line extending along a second direction over the substrate, and the cell selection transistor is coupled with a second access line extending along a third direction away from the substrate.Aspect 19: The apparatus of any of aspects 9 through 18, where the cell selection transistor further includes a gate including a first access line extending along a second direction away from the substrate, and the cell selection transistor is coupled with a second access line extending along a third direction over the substrate.Aspect 20: The apparatus of any of aspects 9 through 19, further including: a conductive plate in contact with the second electrode and extending along a second direction away from the substrate and a third direction over the substrate.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:Aspect 21: An apparatus formed by a process including: forming a cell selection transistor of a memory cell, the cell selection transistor including a channel portion of a semiconductor material extending along a first direction over a substrate; forming a first material around an end of the semiconductor material along the first direction; forming a second material around the first material; forming a cavity based at least in part on removing a portion of the first material, the cavity exposing a sidewall around the semiconductor material and exposing a sidewall of the second material around the semiconductor material; forming a first electrode of a capacitor of the memory cell based at least in part on forming a first conductive material in the cavity, the first conductive material including a first portion along the sidewall around the semiconductor material, a second portion along the sidewall of the second material and around the first portion, and a third portion coupling the first portion with the second portion along one or more directions radial from the first portion; forming a dielectric material over the first electrode and at least partially within the cavity; and forming a second electrode of the capacitor of the memory cell over the dielectric material based at least in part on forming a second conductive material at least partially within the cavity.Aspect 22: The apparatus of aspect 21, where the second conductive material includes a fourth portion between the first portion of the first conductive material and the second portion of the first conductive material, a fifth portion around the second portion of the first conductive material, and a sixth portion coupling the fourth portion with the fifth portion along one or more directions radial from the fourth portion.Aspect 23: The apparatus of any of aspects 21 through 22, where the first conductive material is formed over the end of the semiconductor material.Aspect 24: The apparatus of aspect 23, formed by the process further including: removing the second material, where forming the dielectric material is performed after removing the second material.Aspect 25: The apparatus of any of aspects 21 through 24, formed by the process further including: forming a conductive plate extending along a second direction away from the substrate and along a third direction over the substrate, the conductive plate in contact with a portion of the second conductive material.