Serial advanced technology attachment (SATA) switch that toggles with power control to hard disk drive while avolding interruption to system

An embodiment of the present invention includes a switch employed in a system having two hosts and a device and for coupling two or more host ports to a device. The switch includes a power signal control circuit generating a power signal for use by the device in receiving power for operability thereto, the power signal control circuit responsive to detection of inoperability of the device and in response thereto, toggling the power signal to the device while avoiding interruption to the system.

FIELD OF THE INVENTION

The present invention relates generally to Serial Advanced Technology Attachment ATA (SATA) switches and, in particular, to switches having two host ports and one device port allowing for access by both host ports, the device port being coupled to a storage device, such as a hard disk drive, the switch further having the capability to control power to the storage device.

BACKGROUND OF THE INVENTION

As discussed in prior related patent applications/patents, referenced hereinabove, as listed hereinabove and incorporated herein by reference, a switch or multiplexer (Mux) is used to couple two or more host ports to a target device. A simple failover switch or Active Passive Mux (APMux) allows two different hosts to connect to the same device, however, when one host is connected to the device, the other host can not access the device. An Active switch or Active Active Mux (AAMux) allows concurrent access by both hosts to the device. “Switch or Mux”, as used herein below, refers to either an Active Switch (AAMux) or a Simple Failover Switch (APMux).

Now, briefly problems associated with current apparatus and method are discussed.

In the case where a target device is a storage device, such as a hard disk drive (HDD), is used, power control becomes an issue in today's technology. More specifically, HDDs are commonly known to hang-up or become nonoperational for a variety of reasons, which are well known in the industry. Upon the occurrence of a hang-up, error recovery is performed in an attempt to render the HDD and the system in which the HDD is being utilized operational. In the event of the error recovery failing, as a last step, recovery of the HDD is performed, requiring turning the power to the HDD ‘off’ and then ‘on’ while the rest of the system in which the HDD is being utilized remains operational.

In light of the foregoing, it is desirable to interrupt power to a HDD without interrupting power to the rest of the system in which the HDD resides, the system including a switch coupling at least two host ports to a target (or storage) device, such as the HDD, and the interruption of power to the HDD being the last step in an error recovery process, initiated from the HDD becoming inoperational.

The SATA and SAS use the same connector, to allow use of either a SATA or SAS device in the same system. SATA uses only one link of the connector whereas SAS uses both links on the connector. That is, when disk drives are used in different settings, the use of a mux may or may not be necessary. A specific example is in the context or application of what is commonly known as “Just a Bunch of Disks” (JBOD), or Disk Arrays which is essentially a large number of removable disks (disk array) or HDDs that are in the same enclosure, connected to a backplane and coupled to a common system interface. In JBODs, using SATA or SAS HDDs interchangeably is desirably. Such JBODs will be referred to as SAS/SATA JBODs. Yet another problem associated with the use of SATA switches on the backplane of SAS/SATA JBOD is the need to bypass the switch on the backplane when a SAS HDD is used.

other systems in a variety of different ways. One way is using the disk array in SATA, another is using the disk array in SAS.

Currently, a disk array JBOD requiring SATA coupling as well as SAS coupling needs two different connections therefor, one for the SATA coupling and another for the SAS coupling. Specifically, SATA uses one link of a connector, whereas, SAS uses both links of a connector and SATA requires a mux, whereas, SAS does not.

Therefore, the need arises for an apparatus and method of bypassing an active switch so as to allow using the same connection to connect two or more host ports on one side of a JBOD to either of the SATA and the SAS target device.

SUMMARY OF THE INVENTION

Briefly, an embodiment of the present invention includes a switch employed in a system having two hosts and a device and for coupling two or more host ports to a device. The switch includes a power signal control circuit generating a power signal for use by the device in receiving power for operability thereto, the power signal control circuit responsive to detection of inoperability of the device and in response thereto, toggling the power signal to the device while avoiding interruption to the system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1shows a system60utilizing the switch64in accordance with an embodiment of the present invention. The switch may be SATA or ATA. Further discussions and figures relating to the switch and some of the remaining structures ofFIG. 1, such as the ports64aand64band the host bus adapters11aand12aare included in U.S. patent application Ser. No. 10/775,521, entitled “Switching Serial Advanced Technology Attachment (SATA)”, filed on Feb. 9, 2004 by Siamack Nemazie, the contents of which are incorporated herein as though set forth in full.

The switch64may be an active active mux (AAMux). The switch64comprises of a SATA port64acoupled to a host11, a SATA port64bcoupled to a host12and a SATA port64ccoupled to a storage unit66, which may be a SATA HDD. In system60, the storage unit66has a SATA link and the SATA port64cis coupled to a storage unit66via a SATA link66a. However, the storage unit66may have a ATA link such that the port64cis a ATA port and the link66ais a ATA link.

In the embodiment ofFIG. 1, the hosts11and host12access the storage unit66through the switch64. The host11accesses the switch64through the host bus adapter11aand the host12accesses the switch64through the host bus adapter12a. Thus, the switch64allows for access by the hosts11and host12to the target device, i.e. the storage unit66, wherein concurrent access is allowed from two or more host ports to a single-ported storage unit connected to the device port of a switch via a SATA link or an ATA link.

“Host”, as used herein below, refers to either the host II or host12ofFIG. 1.

InFIG. 1, the switch64is shown to include an out of band (OOB) detector200, shown coupled to a power circuit202, through the power control circuit203and power control signal206. The power circuit202is shown coupled to the storage unit66, through a power connection204which is part of the SATA link66a. The OOB detector200presents one of the ways of toggling power to the storage unit66, through the power connection204, as will be clear shortly. As the OOB detector200is an existing circuit within the system60, there is no need for additional circuitry or even software to effectuate the toggling process. This clearly saves costs in allowing an already existing system to be used for a purpose not currently used, i.e. toggling power.

The storage unit66, as stated previously, may be an HDD, which is prone to hang-ups or times of inoperation due to a wide variety of reasons well-known in industry. Upon recovery from a hang-up situation, error recovery is performed and if the latter process fails, the HDD is preferably turned ‘off’ and ‘on’ (toggled) without interruption of power to the rest of the system60, e.g. operation of the rest of the system60. This is important in that normal operation continues without any disruption to the operation of the rest of the system60even though power to the storage unit66is interrupted.

A condition used to detect a hang-up of the storage unit66is detection of an issued, yet incompletely processed command within a predetermined time period and detection of a failed ‘soft’ reset or ‘hard’ reset as well as failed link re-initialization. A ‘soft’ reset is initiated via setting a control bit in the task file while a ‘hard’ reset is initiated by asserting signals or sequences. Failure to reset or link re-initialize refers to failure to properly recover from a hang-up situation.

Once the foregoing condition is detected, one of the methods of the present invention is used to toggle (or turn ‘off’ or turn ‘on’) power to the storage unit66. One method is to utilize the Port Select OOB (PS OOB) sequence, which is clearly already in existence, as is the OOB detector200, to toggle the power control signal206, which ultimately results in toggling the signal carried on the power connection204, to the storage unit66. The PS OOB sequence is effectively used to select the ‘active’ port when using an APMux and to toggle power to the storage unit66when using an AAMux. The PS OOB sequence consists of two sequences of two COMRESET intervals comprising a total of five COMRESET bursts with four inter-burst delays.FIG. 7ashows the PS OOB sequence400comprising two sequences of two COMRESET intervals consisting of T1interval401, and T2interval402. where delay T1is nominally 2 ms and in the range of 1.6 to 2.4 ms and where delay T2is nominally 8 ms and in the range of 7.6 to 8.4 ms

Another method to toggle power is to use a sequence of COMRESET bursts to turn “off” power and another sequence of COMMREST bursts to turn “on” power. Such sequence must not occur during normal operation. One such sequence is to use two back to back PS OOB with two delays between the two PS OOB sequences. If the delay is between a first range then the sequence is designated to turn “off” power and if the delay is between a second range the sequence is designated to turn power “on”.

FIG. 2ashows further details of the switch64ofFIG. 1in accordance with an embodiment of the present invention. InFIG. 2a, a power control circuit203ais shown to be coupled to the OOB detector200, OOB detector201and the power control circuit202. The power control circuit203ais shown, inFIG. 2a, to include a T type flip flop240, coupled to the host port select signal208and host port select signal209and generating a power control signal206. The T flip flop240is held in reset condition when power on reset signal211is asserted (active low) or when active active mode select signal210is deasserted (low). In operation when a PS OOB is detected the corresponding host port select signal208, or209is asserted which will cause the state of power control circuit203ato toggle. The active active mode select210configures the operation of switch64as APMux or AAMux. When active active mode select210is asserted then switch64is configured for AAMux operation, else if deasserted configured for APMux operation.

Power control circuit is shown to include a RS flip flop230. When active active mode select210is asserted and power on reset211is deasserted and power control signal206is deasserted then if a PS OOB is detected the corresponding host port select signal208, or209is asserted which will cause corresponding host power off signal219, or223to be asserted which will cause the state of power control signal206to toggle (to asserted state). The host power off signals219and223are logically ORed by OR gate226to generate the set signal227of RS flip flop230. When active active mode select210is asserted and power on reset211is deasserted and power control signal206is asserted then if a PS OOB is detected the corresponding host port select signal208, or209is asserted which will cause corresponding host power on signal221, or225to be asserted which will cause the state of power control signal206to toggle (to deasserted state). The host power on signals221and225are logically ORed by OR gate228to generate the reset signal229of RS flip flop230.

FIG. 2cshows another embodiment of present invention. InFIG. 2c, a power control circuit203cis shown to be coupled to the OOB detector200, OOB detector201and the power control circuit202. The power control circuit203cinFIG. 2cis shown to include a RS type flip flop260generating a power control signal206, The set signal257of RS flip flop is coupled to the host port off signal252and254, the reset signal259of RS flip flop260is coupled to host power on signal253and255. The RS flip flop260is held in reset condition when power on reset signal211is asserted (active low) or when active active mode select signal210is deasserted (low). The power control circuit203cis shown to include a host power on/off circuit251coupled to host port select signal209and generating host power off signal252and host power on signal253. The power control circuit203cis shown to include a host power on/off circuit250coupled to host port select signal208and generating host power off signal254and host power on signal255. The host power on signals253and255are logically ORed by OR gate258to generate the reset signal259of RS flip flop260. The host power off signals252and254are logically ORed by OR gate256to generate the set signal257of RS flip flop260. The host power on/off circuit250is responsive to predefined sequences of OOB signals to generate host power on signal253and host power off signal252. One such sequences, shown inFIG. 7bandFIG. 7c, use two back to back PS OOB sequences with two delays between the two PS OOB sequence. If the delay is between a first range then the sequence is designated to turn power “off” and if the delay is between a second range the sequence is designated to turn power “on”. The power on sequence, shown inFIG. 7buse two back to back PS OOB sequences with delay T3403between the two PS OOB sequences, where delay T3is nominally 10 ms and in the range of 9 to 11 ms. The power off sequence, shown inFIG. 7cuse two back to back PS OOB sequences with delay T4404between the two PS OOB sequences, where delay T4is nominally 14 ms and in the range of 13 to 15 ms

It is obvious to one skilled in the art to devise other OOB sequences to turn power “on” or “off”. By way of example, a sequence of COMRESET signal to turn power “on” or “off” is shown inFIGS. 7dand7erespectively.FIG. 7dshows a sequence to turn power “on” comprising two sequences of two COMRESET intervals consisting of T11interval411, and T12interval412followed by another COMRESET burst with inter-burst delay T13413, comprising a total of six COMRESET bursts with five inter-burst delays,FIG. 7eshows a sequence to turn power “off” comprising two sequences of two COMRESET intervals consisting of T11interval411, and T12interval412followed by another COMRESET bust with inter-bust delay T14414, a comprising a total of six COMRESET bursts with five inter-burst delays. It should be noted that such sequence is unique for both AAMux and APMux. It is obvious to one skilled in the art to modify the circuits and methods of present invention for use with such sequences. It is therefore intended that any sequence of OOB signals used in conjunction with circuits and methods for turning power “on” and “off” for AAMux or APMux to fall within scope of the present invention

Yet another method is to use a sequence of COMRESET to request/initiate an atomic power cycle operation. An atomic power cycle operation comprises of turning power off then waiting for a first predetermined time interval and then turning power on, and the host should wait for a second predetermined time before issuing any commands. When an atomic power cycle is in progress any command received from the other host is returned with error.

FIG. 2dshows further details of an embodiment of present invention with atomic power cycle operation. InFIG. 2da power control circuit203dis shown to be coupled to a SATA port64a, a SATA port64band the power control circuit202. The power control circuit203dis shown to include a RS flip flop270and a power off/on circuit271. The RS flip flop270generating a power control signal206, the set signal267and rest signal269of RS flip flop270is coupled to the power off/on circuit271. The RS flip flop270is held in reset condition when power on reset signal211is asserted (active low). The power control circuit203dis shown to include a power off/on circuit271coupled to SATA port64avia control bus261and power status263, to SATA port64bvia control bus262and power status263, and power control signal206. The power off/on circuit271generates power off signals267, and power on signals269. The power off/on circuit271further includes a sequencer271aand a timer271b. The control bus261includes a power cycle request signal261rindicating a request by the host11to initiate a power cycle. The control bus262includes a power cycle request signal262rindicating a request by the host12to initiate a power cycle. The said power cycle request signals,261rand262rare generated by any method of present invention. In response to power cycle request signals261ror262rthe sequencer271astarts, first the sequencer271aasserts power off signal267to cause power circuit202to turn power off, next the sequence271astarts timer271bby asserting timer start signal271s, and waits for the timer271bto time out, when timer271bexpires a time out signal271tis generated and in response the sequencer271adeasserts timer start signal271s, deasserts power off267and assert power on signal269which will cause power circuit202to turn power on.

In general either hosts can initiate a power “off”/“on” cycle. Uncoordinated power “off”/“on” by host11and host12may lead to problems. For example during error recovery host11completes power “off”/“on” and then issues commands, and shortly after host12performing error recovery may initiate a power “off”/“on” cycle followed by issuing commands, the power “off”/“on” cycle by host12will cause command issued by host11to be aborted and host11may initiate another error recovery causing commands issued by host12to be aborted. This situation may lead to a condition that either host may incorrectly conclude that the drive is dead since power “off”/“on” cycle did not bring drive to an operational state. In practice either an in-band coordination via AAMux or out-of-band coordination via other communication paths between the hosts is required to perform power “off”/“on” cycle. An embodiment with in-band coordination via AAMux will be discussed later.

An improvement of embodiment ofFIG. 2dto avoid coordination between hosts for power cycle follows next. The operation of power on/off circuit271inFIG. 2d, is modified to ignore a request by a host for atomic power cycle when an atomic power cycle is in progress or completed in response to an earlier power cycle request by the other host. The power cycle request will be ignored until the host issues a command after atomic power cycle request by the other host is completed.

Yet Another method to toggle power is to use a vendor unique command to turn power ‘off’ and ‘on’ (toggle).FIG. 8ashows an exemplary host to device register FIS data structure501in accordance with an embodiment of the present invention. The value of FIS type510afor host to device register FIS501is 27h(the subscript h indicates the number is in hexadecimal). A host to device register FIS501with C-bit510bset indicates command from host and is called a “command FIS”. The commands includes vendor unique commands (VUC) that is not generally supported by all devices but unique for each vendor, and hence the name “vendor unique commands”. The VUC is targeted at the device66and not the AAMux64. The method of present invention uses a predefined setting for combination of other fields of a command FIS that does not occur in standard command FIS to send VUC specifically to the AAMux (AAMux VUC). Upon receipt of such AAMux VUC, the AAMux will not forward the command FIS to device66and will provide the response directly to host. The VUC command codes include 80h-86h, 88h-8Fh, C1h-C3h, F0h, F7h, FAh-FFh. In particular the method of present invention uses the VUC code FFh, along with a predefined setting of FFhfor Dev/Head register511d, along with value of Ah, for the upper nibble (bits7-4) of control register513dto indicate an AAMux VUC. It is obvious to one skilled in the art to devise other combinations of settings to specify a AAMux VUC. For a AAMux VUC the features register510dincludes sub-command codes that define the operation or service requested by the AAMux VUCs.

The contents of host to device register FIS for AAMux VUC are shown below:

FIG. 8bshows an exemplary device to host register FIS data structure502in accordance with an embodiment of the present invention. The value of FIS type520afor host to device register FIS502is 34h (hexadecimal). The device to host register FIS502is used to provide response to host including response for AAMux VUCs. In particular the status register520cincludes the status.

The contents of device to host register FIS502for response to AAMux VUC are shown below:

Communication between hosts via a mailbox is well known in the art and will not be discussed here. In the embodiment ofFIG. 1, SATA port64ais shown to include mailbox A61a, and SATA port64bis shown to include mailbox B61b. In this embodiment the mailbox A61aand mailbox B61bcomprise of four general purpose registers. The unique aspect of present invention is providing access to mailboxes via AAMux. Host11and host12can write to mailbox A and mailbox B registers via AAMux VUC 01h. Host11or host12can read mailbox A or mailbox via AAMux VUC 03h and 04h. The 4-byte mail box contents is returned via device to host register FIS in Sector Count513a, Sector Number511a, Cy1Low511b, Cy1High511crespectively. It should be noted that host11or host12can read individual registers of mailbox A or mailbox via AAMux VUC 0.

Communication path between the hosts via mailbox and AAMux VUC to access the mailboxes provides an in-band coordination between host11and host12.

By way of vendor unique commands a variety of operations can be performed by the AAMux. Such operations include the following:

AAMuxVUCcodedescription00hNOP.In response to NOP, the AAMux 64 will send device to hostregister FIS 502. NOP provides a way to obtain status withoutrequesting any operation01hWrite AAMux internal register.Register Address is in “Sector Count” 513aData is in “”Cyl Low” 511bData Mask is in “Cyl High” 511c. Data Mask specifiesregister bits that should be written (and bits that are notaffected)02hRead AAMux internal registerRegister Address is in “Sector Count” 513a.Contents of register is returned in “”Cyl Low” 511b viadevice to host register FIS 50203hRead internal mailbox A 61a04hRead internal mailbox B 61b05hPower OFF06hPower ON07hAtomic Power CycleThe timer 271b timeout value is programmable. Cyl high 511cis concatenated with Cyl low 511b to form a 16-bit timeoutvalue for timer 271b.08hChange timeout value of timerThe timer 271b timeout value is set to 16-bit value formed byconcatenating Cyl high 511c and Cyl low 511b09h~FFhReserved

Next, another embodiment of the present invention is shown in relation to the use of Just a Bunch of Disks (JBOD), which as previously explained, is basically a disk array or array of HDDs.

The SATA and SAS use the same connector, to allow use of either a SATA or SAS device in the same system. The SATA will use only one link of the connector whereas the SAS will use both links on the connector. A specific example is in the context or application of what is commonly known as “Just a Bunch of Disks” (JBOD), or Disk Arrays which is essentially a large number of removable HDDs that are in the same enclosure, connected to a backplane and coupled to a common system interface. In JBODs using SATA or SAS HDDs it is desirable to use either SATA or SAS HDDs interchangeably. Such JBODs will be referred to as SAS/SATA JBODs. Yet another problem associated with the use of SATA switches on the backplane of SAS/SATA JBOD is the need to bypass the switch on the backplane when a SAS HDD is used.

Currently, a JBOD requiring SATA coupling as well as SAS coupling needs two different connections therefor, one for the SATA coupling and another for the SAS coupling. Specifically, SATA uses one link of a connector, whereas, SAS uses both links of a connector and SATA requires a switch, whereas, SAS does not.

In accordance with an embodiment of the present invention,FIG. 3shows a JBOD system300to include a JBOD302, a one or more connection circuit307coupled thereto or physically residing therein, a host304coupled to the JBOD302, through the link312, a host306, coupled to the JBOD302, through the link314, a host controller303coupled to link312and generating one or more links322for connection to HDDs and host controller305coupled to link314and generating one or more links324for connection to HDDs. The connection circuit307is shown to generate a D1output318and a D2output320in response to inputs322and324. While prior art techniques use two connectors to couple the links322and324to the outputs318and320, respectively, as shown inFIG. 3, an embodiment of the present invention uses only one connector, which is included in the connection circuit307and shown in greater detail in other figures to be discussed shortly.

Perhaps, at this time, a brief discussion for the purpose of using two connectors by prior art systems is in order. The need for the use of two different connectors arises, in large part, due the use of SATA as well as SAS HDDs. To this end, SATA uses one link of a connector, whereas, SAS uses two links of a connector, accordingly, SATA requires the use of a switch, whereas, SAS does not. Thus, the embodiment of the present invention, shown inFIGS. 3-5employs a combination of switch and connector within the connection circuit307to alleviate the need for two connectors, yet, operate with SATA and SAS HDDs.

Referring now toFIG. 4, further details of the connection circuit307are shown to include a switch316responsive to the links322and324and a connector308coupled to receive the mux output313and the link314and to generate the D1output318and the D2output320.

The switch316is also shown to receive a bypass control signal311, which is essentially indicative of a SAS HDD where the switching function of switch316is bypassed and the links322is coupled to output link313, and links313and324ultimately generating the D1output318and the D2output320, respectively. This is further clear with respect toFIG. 5where a functional representation of the relationship between the links322and324and the D1output318and the D2output320, respectively, is shown.

InFIG. 5, a functional relationship, as that described above is shown. That is, when the bypass control signal311indicates a SAS HDD, the link322essentially generates the D1output and the link324essentially generates the D2output320. However, when the bypass control signal311indicates a SATA HDD, the links322and324are selectively caused to generate the D1output318, i.e. the links312and314are each inputs of the switch316and are then multiplexed to generate the D1output318, and the D2output320remains unused. In this manner, only one connector is utilized to accommodate both SATA and SAS HDDs.

In yet another embodiment of the switch shown inFIG. 6a, the switch336has an additional device port, that is the switch336has a first host port331, a second host port332, a first device port341, a second device port342, and a bypass control signal311. When the bypass control signal311indicates a bypass mode (used with SAS HDD) the first host port331is coupled to first device port341and the second host port332is coupled to second device port342. When the bypass control signal311indicates a non-bypass mode (used with SATA HDD), the second device port342is disabled and the switch operates in normal mode wherein the first host port331and second host port332are multiplexed on the first device port341.

Referring now toFIG. 6b, further details of the connection circuit307are shown to include a switch336responsive to the links322and324and a connector308coupled to receive the outputs341and342of switch336and to generate the D1output318and the D2output320.”

Although the present invention has been described in terms of specific embodiments it is anticipated that alterations and modifications thereof will no doubt become apparent to those skilled in the art. It is therefore intended that the following claims be interpreted as covering all such alterations and modifications as fall within the true spirit and scope of the invention. It is obvious to an expert in the art to combine the present invention with prior art to develop devices and methods that perform multiple functions including the teachings of this invention. Such devices and methods fall within the scope of present invention.