Array substrate and display device

Embodiments of the present application provide an array substrate and a display device. The array substrate includes a plurality of sub-pixel units arranged in an array, each sub-pixel unit includes a base substrate, a thin film transistor, a pixel electrode and a common electrode, the common electrode is on a side of the base substrate, the thin film transistor and the pixel electrode are between the base substrate and the common electrode, the thin film transistor includes a control terminal, a first electrode and a second electrode, the pixel electrode is connected to the second electrode, and the control terminal is in a continuous sheet shape, an orthographic projection of a boundary of the control terminal on the base substrate is within an orthographic projection of the common electrode on the base substrate.

RELATED APPLICATION

The present application claims the benefit of Chinese Patent Application No. 202110281696X, filed on Mar. 16, 2021, the entire disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the field of display technology, in particular to an array substrate and a display device.

BACKGROUND

With the advancement of technology, liquid crystal displays are widely used in electronic products such as TVs, computers, and mobile phones due to their small size, thin thickness, light weight and low power consumption. Liquid crystal displays cannot self-illuminate and require additional backlighting. In the dark state, the liquid crystals at certain positions are deflected due to the influence of the irregular electric field, so that the backlight passes through the deflected liquid crystals to be received by the human eyes, which causes the brightness of the dark state to increase and affects the viewing effect.

SUMMARY

As a first aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides an array substrate comprising a plurality of sub-pixel units arranged in an array, each sub-pixel unit comprising a base substrate, a thin film transistor, a pixel electrode and a common electrode, the common electrode being on a side of the base substrate, the thin film transistor and the pixel electrode being between the base substrate and the common electrode, the thin film transistor comprising a control terminal, a first electrode and a second electrode, the pixel electrode being connected to the second electrode, and the control terminal being in a continuous sheet shape, an orthographic projection of a boundary of the control terminal on the base substrate being within an orthographic projection of the common electrode on the base substrate.

In some implementations, an orthographic projection of the control terminal on the base substrate and the orthographic projection of the common electrode on the base substrate have a first overlap area, and the first overlap area extends from the boundary of the control terminal toward a middle part of the control terminal.

In some implementations, a part of the orthographic projection of the control terminal on the base substrate is in the first overlap area, and a range of a width d of the first overlap area satisfies 0<d<s/2, s is a width of the control terminal, and measurement directions of d and s are same.

In some implementations, the orthographic projection of the control terminal on the base substrate is completely in the first overlap area, and a width of the first overlap area is equal to a width of the control terminal.

In some implementations, the thin film transistor further comprises an active layer, the array substrate further comprises a first insulating layer, the control terminal is on a side of the base substrate, the first insulating layer is on a side of the control terminal away from the base substrate, the active layer is on a side of the first insulating layer away from the base substrate, and the first electrode and the second electrode are on a side of the active layer away from the base substrate, an orthographic projection of the first electrode on the base substrate is within an orthographic projection of the control terminal on the base substrate.

In some implementations, the array substrate further comprises a second insulating layer, the second insulating layer is on a side of the second electrode away from the base substrate, the common electrode is on a side of the second insulating layer away from the base substrate, and the pixel electrode is between the active layer and the second electrode.

In some implementations, the array substrate further comprises a second insulating layer, the second insulating layer is on a side of the second electrode away from the base substrate, the common electrode is on a side of the second insulating layer away from the base substrate, and the pixel electrode is between the second electrode and the second insulating layer.

In some implementations, the thin film transistor further comprises an active layer, the active layer is on a side of the base substrate, the array substrate further comprises a first insulating layer, a second insulating layer and a third insulating layer, the first insulating layer is on a side of the active layer away from the base substrate, the control terminal is on a side of the first insulating layer away from the base substrate, the second insulating layer is on a side of the control terminal away from the base substrate, the third insulating layer is on a side of the second insulating layer away from the base substrate, the first electrode, the second electrode, and the pixel electrode are between the second insulating layer and the third insulating layer, and the common electrode is on a side of the third insulating layer away from the base substrate.

In some implementations, an orthographic projection of the first electrode on the base substrate and the orthographic projection of the common electrode on the base substrate have a second overlap area, and the second overlap area extends from an outer boundary of the first electrode toward a middle part of the control terminal.

In some implementations, the common electrode comprises a plurality of first strip-shaped sub-electrodes arranged at intervals in the sub-pixel unit.

In some implementations, the array substrate further comprises a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines define the plurality of sub-pixel units, and an extending direction of the first strip-shaped sub-electrodes is consistent with an extending direction of the data lines.

In some implementations, the common electrode further comprises second strip-shaped sub-electrodes, an extending direction of the second strip-shaped sub-electrodes is consistent with the extending direction of the data lines, and an orthographic projection of the data lines on the base substrate is within an orthographic projection of the second strip-shaped sub-electrodes on the base substrate.

In some implementations, the common electrode further comprises a connecting portion, and each of the first strip-shaped sub-electrodes and each of the second strip-shaped sub-electrodes are connected to each other through the connecting portion.

As a second aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a display device, which comprises a first substrate and a second substrate disposed oppositely, and a liquid crystal layer between the first substrate and the second substrate, the first substrate adopting the array substrate in any embodiment of the present disclosure, the common electrode facing the liquid crystal layer.

In some implementations, an orthographic projection of the control terminal on the base substrate and the orthographic projection of the common electrode on the base substrate have a first overlap area, and the first overlap area extends from the boundary of the control terminal toward a middle part of the control terminal.

In some implementations, a part of the orthographic projection of the control terminal on the base substrate is in the first overlap area, and a range of a width d of the first overlap area satisfies 0<d<s/2, s is a width of the control terminal, and measurement directions of d and s are same.

In some implementations, the orthographic projection of the control terminal on the base substrate is completely in the first overlap area, and a width of the first overlap area is equal to a width of the control terminal.

In some implementations, an orthographic projection of the first electrode on the base substrate and the orthographic projection of the common electrode on the base substrate have a second overlap area, and the second overlap area extends from an outer boundary of the first electrode toward a middle part of the control terminal.

In some implementations, the thin film transistor further comprises an active layer, the array substrate further comprises a first insulating layer, the control terminal is on a side of the base substrate, the first insulating layer is on a side of the control terminal away from the base substrate, the active layer is on a side of the first insulating layer away from the base substrate, and the first electrode and the second electrode are on a side of the active layer away from the base substrate, an orthographic projection of the first electrode on the base substrate is within an orthographic projection of the control terminal on the base substrate.

In some implementations, the thin film transistor further comprises an active layer, the active layer is on a side of the base substrate, the array substrate further comprises a first insulating layer, a second insulating layer and a third insulating layer, the first insulating layer is on a side of the active layer away from the base substrate, the control terminal is on a side of the first insulating layer away from the base substrate, the second insulating layer is on a side of the control terminal away from the base substrate, the third insulating layer is on a side of the second insulating layer away from the base substrate, the first electrode, the second electrode, and the pixel electrode are between the second insulating layer and the third insulating layer, and the common electrode is on a side of the third insulating layer away from the base substrate.

The above summary is only for illustrative purposes and is not intended to be limiting in any way. In addition to the exemplary aspects, embodiments and features described above, by referring to the accompanying drawings and the following detailed description, further aspects, embodiments and features of the present disclosure will be easy to appreciate.

DETAILED DESCRIPTION OF THE DISCLOSURE

Only some exemplary embodiments are briefly described below. As those skilled in the art can realize, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and description are regarded to be illustrative essentially but not restrictive.

FIG.1is a schematic diagram of light leakage of a liquid crystal display device in a dark state in the related art. It can be seen fromFIG.1that in the dark state, the display device has light leakage, which causes the brightness of the dark state to increase, which affects the viewing effect.

There are a variety of metal traces in a substrate such as an array substrate. The relative positions of the metal traces make the distribution of electric field in the array substrate disorder and cannot be effectively controlled, resulting in liquid crystal deflection in partial areas which leads to light leakage. In the related art, the technical solution to avoid light leakage is to use a black matrix for shielding. However, the black matrix can only block light leakage at a positive viewing angle. To ensure that the black matrix can block light leakage at an oblique viewing angle, the size of the black matrix needs to be increased, which will reduce the aperture ratio of the display device.

In addition, the liquid crystal material in the display device is anisotropic. The anisotropic liquid crystal material has light transmission properties. A small amount of light in the light leakage area will be transmitted to the pixel area. Although there is no obvious light leakage visually, it affects the contrast of the product.

For a liquid crystal display device in fringe field switching (FFS) mode, in the dark state, the voltages of the pixel electrode and the common electrode are both 0 V, and the voltage of the source electrode is within the range of 0˜±Vop, and the voltage of the gate electrode is usually −8V or 18V. Therefore, in the dark state, there is a voltage difference between the gate electrode and the pixel electrode or the common electrode to generate an electric field, and there is a voltage difference between the source electrode and the pixel electrode or the common electrode to generate an electric field. These electric fields will cause the liquid crystals in the corresponding positions to deflect, leading to light leakage. Although a black matrix is used for light leakage shielding, when the size of the black matrix is certain, the black matrix cannot shield the light leakage from the oblique viewing angle, which causes the display device to have high brightness in the dark state, resulting in lower contrast. In addition, the alignment of the black matrix and the array substrate will have a deviation, which is greatly affected by the process stability, resulting in large fluctuations in the brightness in the dark state, and the macroscopic performance is large fluctuations in contrast, which is difficult to meet the customer's requirements for contrast.

In order to solve the problem of light leakage in the display device, an embodiment of the present disclosure provides an array substrate.

FIG.2ais a schematic plan view of the array substrate in an embodiment of the present disclosure.FIG.3is a schematic diagram of the A-A cross-sectional structure inFIG.2a.FIG.2ashows a sub-pixel unit in the array substrate, in which the active layer31is not shown for clarity. As shown inFIG.2aandFIG.3, the array substrate may include a plurality of gate lines11and a plurality of data lines51, and the plurality of gate lines11and the plurality of data lines51define a plurality of sub-pixel units arranged in an array. Each sub-pixel unit may include a base substrate10, a thin film transistor, a pixel electrode41and a common electrode71. The common electrode71is on a side of the base substrate10, and the thin film transistor and the pixel electrode41are between the base substrate10and the common electrode71. The thin film transistor includes a control terminal12, an active layer31, a first electrode52and a second electrode53. The pixel electrode41is connected to the second electrode53of the thin film transistor. The control terminal12of the thin film transistor is in a continuous sheet shape, and an orthographic projection of a boundary of the control terminal12of the thin film transistor on the base substrate10being within an orthographic projection of the common electrode71on the base substrate10.

Exemplarily, the control terminal may be a gate electrode, one of the first electrode52and the second electrode53may be a source electrode, and the other may be a drain electrode. For example, the first electrode52may be a source electrode, and the second electrode53may be a drain electrode.

In the array substrate of the embodiment of the present disclosure, the thin film transistor and the pixel electrode41are between the base substrate10and the common electrode71, the control terminal12of the thin film transistor is in a continuous sheet shape, and the orthographic projection of the boundary of the control terminal12of the thin film transistor on the base substrate10is within the orthographic projection of the common electrode71on the base substrate10. Thus, the orthographic projection of the control terminal12of the thin film transistor on the base substrate10and the orthographic projection of the common electrode71on the base substrate10have a first overlap area110. The portion of the common electrode71corresponding to the first overlap area110is in a continuous sheet shape. Therefore, the common electrode71can completely shield the electric field in the first overlap area110.

It can be understood that in the dark state, the voltages of the pixel electrode and the common electrode are both 0V, and the voltage of the gate electrode is usually −8V or 18V. In the array substrate according to the embodiment of the present disclosure, the orthographic projection of the boundary of the control terminal12of the thin film transistor on the base substrate10is within the orthographic projection of the common electrode71on the base substrate10. Therefore, in the dark state (LO state), the electric field generated by the boundary of the control terminal12and the pixel electrode41, and the electric field generated by the boundary of the control terminal12and the common electrode71can both be shielded by the common electrode71with a common voltage to avoid the electric field enters the liquid crystal layer to cause the liquid crystal to deflect. Therefore, the light leakage resulted from the liquid crystal deflection caused by the irregular electric field is avoided, the brightness of the display device in the dark state is reduced, and the contrast of the product is improved.

In an embodiment, the first overlap area110extends from the boundary of the control terminal12toward the middle part of the control terminal12. It can be understood that the material of the control terminal12can be light-shielding metal. The control terminal12can prevent light from passing through the middle part of the control terminal12due to the light-shielding property, so light leakage usually occurs at the boundary position of the control terminal12. The first overlap area110is set to extend from the boundary of the control terminal12toward the middle part of the control terminal12, the electric field generated by the boundary of the control terminal12and the position close to the boundary and the pixel electrode41, the electric field generated by the boundary of the control terminal12and the position close to the boundary and the common electrode71can both be shielded by the common electrode71with a common voltage to avoid the deflection of the liquid crystal near the boundary of the control terminal12, thereby avoiding light leakage at the boundary of the control terminal12.

In an embodiment, as shown inFIG.2a,FIG.2bandFIG.2c, the portion of the common electrode71corresponding to the control terminal includes an opening710, and a part of the orthographic projection of the control terminal12on the base substrate10is in the first overlap area110, and a range of a width d of the first overlap area110satisfies 0<d<s/2, s is a width of the control terminal, and the measurement directions of d and s are the same. The width of the first overlap area110is the size of the first overlap area110in the direction perpendicular to the direction in which it extends. For example, as shown inFIG.2c, for the portion of the first overlap area110extending in the vertical direction, the width of the first overlap area110is the dimension along the horizontal direction, and for the portion of the first overlap area110extending in the horizontal direction, the width of the first overlap area110is the dimension along the vertical direction, as indicated by d inFIG.2c.

In an embodiment, the part of the common electrode corresponding to the control terminal is in a continuous sheet shape, and the orthographic projection of the control terminal on the base substrate is completely covered by the orthographic projection of the common electrode on the base substrate, that is, the orthographic projection of the control terminal on the base substrate is completely in the first overlap area. In this case, the width of the first overlap area is equal to the width of the control terminal.

As shown inFIG.2aandFIG.3, the array substrate may further include a first insulating layer21, and the thin film transistor may also include an active layer31. The control terminal12is on a side of the base substrate10, the first insulating layer21is on a side of the control terminal12away from the base substrate10, and the active layer31is on a side of the first insulating layer21away from the base substrate10. The first electrode52and the second electrode53are on a side of the active layer31away from the base substrate10. In an embodiment, an orthographic projection of the first electrode52on the base substrate10is within the orthographic projection of the control terminal12on the base substrate10.

It can be understood that, in the liquid crystal display device, the backlight can be arranged on a side of the base substrate10away from the thin film transistor, so that the control terminal12can block the first electrode52from the backlight side. When the liquid crystal is deflected by the electric field generated between the first electrode52and the common electrode41, since the control terminal12blocks the light, there will be no light leakage due to the liquid crystal deflection.

In an embodiment, as shown inFIG.2d, the orthographic projection of the first electrode52on the base substrate10and the orthographic projection of the common electrode71on the base substrate10have a second overlap area120, and the second overlap area120extends from the outer boundary of the first electrode52toward the middle part of the control terminal12. With this arrangement, the common electrode71with a common voltage can shield the electric field generated at the outer boundary of the first electrode52, and prevent the electric field at the outer boundary of the first electrode52from causing the liquid crystal to deflect and then leading to leak light.

In the embodiment shown inFIG.2aandFIG.2d, the first electrode52has a “U”-shaped groove shape, and the second electrode53is inserted in the groove of the first electrode52. It can be understood that the specific shape of the first electrode52can be set according to actual needs, and is not limited to the shape inFIG.2aandFIG.2d. It should be noted that “the outer boundary of the first electrode” refers to the outer edge of the boundary of the first electrode facing the control terminal in a plane parallel to the base substrate. For example, the outer boundary of the first electrode52inFIG.2ais the edge of the outer contour of the “U”-shaped groove.

In an embodiment, as shown inFIG.3, the array substrate may further include a second insulating layer61, the second insulating layer61is on a side of the second electrode53away from the base substrate10, and the common electrode71is on a side of the second insulating layer61away from the base substrate. Exemplarily, the pixel electrode41may be between the active layer31and the second electrode53, as shown inFIG.3. Alternatively, the pixel electrode may be between the second electrode and the second insulating layer, and the pixel electrode is connected to the second electrode.

The thin film transistors shown inFIG.2aandFIG.3are bottom gate thin film transistors, and the technical solutions of the present disclosure are also applicable to top gate thin film transistors.

FIG.4is a schematic diagram of a cross-sectional structure of an array substrate according to another embodiment of the present disclosure. As shown inFIG.4, the thin film transistor includes a control terminal12, a first electrode52, a second electrode53and an active layer31. The array substrate further includes a first insulating layer21, a second insulating layer61, and a third insulating layer81. The active layer31is on a side of the base substrate10, the first insulating layer21is on a side of the active layer31away from the base substrate10, the control terminal12is on a side of the first insulating layer21away from the base substrate10, the second insulating layer61is on a side of the control terminal12away from the base substrate10, and the third insulating layer81is on a side of the second insulating layer61away from the base substrate10. The first electrode52, the second electrode53and the pixel electrode41are all between the second insulating layer61and the third insulating layer81, and the pixel electrode41is connected to the second electrode53. The first electrode52is connected to the active layer31through a via hole that penetrates the second insulating layer61and the first insulating layer21, and the second electrode53is connected to the active layer31through a via hole that penetrates the second insulating layer61and the first insulating layer21. Exemplarily, the pixel electrode41is on the side of the second insulating layer61away from the base substrate10, and the first electrode52and the second electrode53are on the side of the pixel electrode41away from the base substrate10. The common electrode71is on the side of the third insulating layer81away from the base substrate10.

It can be understood that in the top gate thin film transistor, the orthographic projection of the outer boundary of the first electrode52on the base substrate10may be outside the orthographic projection of the active layer31on the base substrate, then the active layer31can not shield the boundary of the first electrode52, which causes light leakage at the boundary of the first electrode52. In an embodiment, as shown inFIG.2d, the orthographic projection of the first electrode52on the base substrate and the orthographic projection of the common electrode71on the base substrate have a second overlap area120, and the second overlap area120extends from the outer boundary of the first electrode52toward the middle part of the control terminal12. Therefore, when an electric field is generated between the first electrode52and the common electrode, the portion of the common electrode corresponding to the second overlap area120can shield the electric field at the boundary of the first electrode52, and avoid the liquid crystal corresponding to the boundary of the first electrode52to deflect, thereby avoiding light leakage caused by liquid crystal deflection.

Exemplarily, as shown inFIG.4, the array substrate may further include a light-shielding layer91and a fourth insulating layer92. The light-shielding layer91is on a side of the base substrate10facing the active layer31, and the fourth insulating layer92is on a side of the light-shielding layer91away from the base substrate10, the active layer31is on a side of the fourth insulating layer92away from the base substrate10. The orthographic projection of the active layer31on the base substrate10may be within the orthographic projection of the light shielding layer91on the base substrate10. The light-shielding layer91can shield the light from the lower side of the base substrate10to avoid affecting the working performance of the thin film transistor. The material of the light-shielding layer91may include an opaque metal, such as at least one of tantalum (Ta), molybdenum (Mo), tungsten (W), aluminum (Al), and the like.

The shape of the first electrode52shown inFIG.4may be the same as or different from the shape of the first electrode52inFIG.2aandFIG.2d.

FIG.5is a schematic diagram of the B-B cross-sectional structure inFIG.2a. In an embodiment, the array substrate may include a plurality of gate lines11and a plurality of data lines51, and the plurality of gate lines11and the plurality of data lines51define a plurality of sub-pixel units arranged in an array. The gate lines11may extend in a first direction D1, and the data lines51may extend in a second direction D2, which is perpendicular to the first direction D1. As shown inFIG.2a,FIG.3, andFIG.5, the pixel electrode41is in the sub-pixel unit, and the pixel electrode41may have a sheet structure. The common electrode71may include a plurality of first strip-shaped sub-electrodes711arranged at intervals in the sub-pixel unit, and the extending direction of the first strip-shaped sub-electrodes711may be consistent with the extending direction of the data lines51. The first strip-shaped sub-electrodes711and the pixel electrode41in the sub-pixel unit can form an FFS mode electric field, which can drive the liquid crystal display device to work.

The common electrode71may also include second strip-shaped sub-electrodes712. The extending direction of the second strip-shaped sub-electrodes712is consistent with the extending direction of the data lines51. The orthographic projection of the data lines51on the base substrate10is within the orthographic projection of the second strip-shaped sub-electrodes712on the base substrate10. Therefore, the second strip-shaped sub-electrodes712can form a shielding effect on the data lines51, and prevent the data line51and other electrodes from generating an electric field to cause liquid crystal deflection and light leakage.

As shown inFIG.2aandFIG.2b, the common electrode may further include a connecting portion713, which may extend along the first direction D1, and the connecting portion may be connected to the ends of the first strip-shaped sub-electrodes and the ends of the second strip-shaped sub-electrodes, thereby each of the first strip-shaped electrodes and each of the second strip-shaped electrodes may be connected to each other through the connection portion713.

The technical solution of the embodiments of the present disclosure will be described in detail below through the preparation process of the array substrate in an embodiment of the present disclosure. It can be understood that, for the term “patterning” mentioned herein, when the patterned material is inorganic material or metal, “patterning” includes coating photoresist, mask exposure, development, etching, stripping photoresist and other processes, and when the patterned material is organic material, “patterning” includes mask exposure, development and other processes. The process of evaporation, deposition, and coating mentioned herein are all mature preparation process in related art.

The preparation process of the array substrate may include the following steps.

The first patterning process: a gate metal layer is formed on the base substrate10. The gate metal layer includes a control terminal12and a gate line11, as shown inFIG.6aandFIG.6b.FIG.6ais a schematic plan view of an array substrate after a gate metal layer is formed according to an embodiment of the disclosure.FIG.6bis a schematic diagram of the A-A cross-sectional structure inFIG.6a.

Exemplarily, a gate metal film may be deposited on the base substrate10, and the gate metal film may be patterned to form the control terminal12and the gate line11. The control terminal12may be a continuous sheet, and the gate line11is connected to the control terminal12. The gate line11may extend in the first direction, and the gate line11may be connected to the control terminals12in the plurality of sub-pixel units. The material of the gate metal film may include an opaque metal, such as at least one of tantalum (Ta), molybdenum (Mo), tungsten (W), aluminum (Al), and the like.

The second patterning process: forming a first insulating layer21on a side of the gate metal layer away from the base substrate10, forming an active film on a side of the first insulating layer21away from the base substrate10, and patterning the active film to form the active layer31, as shown inFIG.7aandFIG.7b.FIG.7ais a schematic plan view of an array substrate after an active layer is formed according to an embodiment of the disclosure.FIG.7bis a schematic diagram of the A-A cross-sectional structure inFIG.7a. The material of the active layer can be a semiconductor material.

The third patterning process: forming a pixel electrode41on a side of the active layer31away from the base substrate10, as shown inFIG.8aandFIG.8b.FIG.8ais a schematic plan view of an array substrate after pixel electrodes is formed according to an embodiment of the disclosure.FIG.8bis a schematic diagram of the A-A cross-sectional structure inFIG.8a.

Exemplarily, a transparent electrode film may be deposited on a side of the active layer31away from the base substrate10, and the transparent electrode film may be patterned to form the pixel electrode41in the sub-pixel unit, and the pixel electrode41has a sheet structure. The material of the pixel electrode may include at least one of indium tin oxide (ITO) and indium zinc oxide (IZO).

The fourth patterning process: forming a source-drain metal layer on a side of the pixel electrode41away from the base substrate10. The source-drain metal layer includes a first electrode52, a second electrode53, and a data line51, as shown inFIG.9aandFIG.9b.FIG.9ais a schematic plan view of an array substrate after a source and drain metal layer is formed according to an embodiment of the disclosure.FIG.9bis a schematic diagram of the A-A cross-sectional structure inFIG.9a. The active layer is not shown inFIG.9afor clarity.

Exemplarily, a source-drain metal film is deposited on the side of the pixel electrode41away from the base substrate10, and the source-drain metal film is patterned to form a first electrode52, a second electrode53and a data line51, and the data line51extend along the second direction. The data line51is connected to the first electrode52, and the second electrode53is connected to the pixel electrode41. The orthographic projection of the second electrode52on the base substrate10is within the orthographic projection of the control terminal12on the base substrate10. The first electrode52may have a “U”-shaped groove shape, and the second electrode53is inserted into the groove of the first electrode52. It can be understood that the specific shape of the first electrode52can be set according to actual needs, and is not limited to the shape inFIG.9a. The material of the source-drain metal film may include opaque metals, such as at least one of tantalum (Ta), molybdenum (Mo), tungsten (W), aluminum (Al), and the like.

The fifth patterning process: forming a second insulating layer61on a side of the second electrode53away from the base substrate10, and forming a common electrode71on a side of the second insulating layer61away from the base substrate10, as shown inFIG.2aandFIG.3.

It can be known from the preparation process of the array substrate that the array substrate of the embodiment of the present disclosure does not increase the number of masks and the process steps.

Based on the inventive concept of the foregoing embodiments, an embodiment of the present disclosure further provides a display device, which includes a first substrate and a second substrate disposed oppositely, and a liquid crystal layer between the first substrate and the second substrate. The first substrate adopts the array substrate in any embodiment of the present disclosure, and the common electrode faces the liquid crystal layer. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.

The display device in the embodiments of the present disclosure can eliminate the light leakage in the dark state of the display device, reduce the light leakage phenomenon in the thin film transistor area. Even if there is an alignment deviation of the black matrix, it can also block the light leakage at an oblique viewing angle, and improve the contrast and process stability of the product.

Through experimental simulations, for the display device of an embodiment of the present disclosure, in the dark state, each sub-pixel unit has no light leakage, the brightness is reduced in the dark state, and the contrast is increased from 900:1 in the prior art to 1000:1, and the contrast is greatly improved.

In the description of this specification, it should be understood that the orientations or positional relations indicated by the terms such as “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “upper”, “lower”, “front”, “rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, and the like are based on the orientations or positional relations shown in the drawings, which are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply an indicated device or element must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present disclosure.

In addition, the terms “first” and “second” are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present disclosure, “plurality” means two or more, unless specifically defined otherwise.

In the present disclosure, unless expressly specified and defined otherwise, the terms such as “installation”, “connected”, “connection”, “fixation”, etc. should be understood broadly, for example, they can be fixed connection, detachable connection or integral connection; they can be mechanical connection, electrical connection or communication; they can be direct connection or indirect connection via an intermediate medium, or communication between two elements or interaction between two elements. Those ordinarily skilled in the art may understand the specific meanings of the above terms in the present disclosure based on specific situations.

In the present disclosure, unless expressly specified and defined otherwise, the first feature being “on” or “under” the second feature may include the first feature being in direct contact with the second feature, and may also include the first feature and the second feature being not in direct contact but in contact with each other via another feature therebetween. Moreover, the first feature being “on”, “above” and “over” the second feature includes the first feature being directly above and diagonally above the second feature, or it simply means that the level height of the first feature is larger than that of the second feature. The first feature being “under”, “below” and “beneath” the second feature includes the first feature being directly below and diagonally below the second feature, or it simply means that the level height of the first feature is smaller than that of the second feature.

The above disclosure provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the present disclosure, components and settings of specific examples are described above. Of course, they are only examples, and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numerals and/or reference letters in different examples, and this repetition is for the purpose of simplification and clarity and does not itself indicate the relationships between the various embodiments and/or settings discussed.

What have been described are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not so limited. Any variations or substitutions that can be easily conceived by a skilled person familiar with this technical field shall be encompassed within the protection scope of the present disclosure. Thus, the protection scope of the present disclosure shall be based on that of the claims.