Comb filter that utilizes host memory

A comb filter system that utilizes host memory is disclosed. The comb filter system that utilizes host memory may include a comb filter. The comb filter system that utilizes host memory may include an allocated host memory. The comb filter system that utilizes host memory may include an interface in signal communication with the comb filter and allocated host memory.

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to video decoders, and in particular to video decoder having a comb filter system that utilizes host memory.

2. Related Art

The complexity and flexibility of electronic processing devices such as personal computers (“PCs”), personal digital assistants (“PDAs”), two-way set top boxes (both for cable and satellite), personal video recorders (“PVRs”), cellular telephones, two-way pagers, and other host devices capable of processing information are growing a rapid pace. As such, these types of devices have become common place in today's society.

With the growth, improvement, and general acceptance of the Internet, more information is becoming accessible to these types of devices in varying forms of content leading to a fusion between these types of devices and various types of multimedia content. As an example, the growth of both cable and satellite type television systems has resulted in cable ready televisions, two-way set top boxes (the devices that interface between the cable or satellite systems and the television monitor generally known as “STBs”), digital cable, cable modems to access the Internet, Internet based web-TV, digital telephone over cable, on-demand video services, etc. Additionally, devices such as cable ready televisions, web-TVs, Internet capable video games, and PCs are increasing being connected to either cable or satellite type broadband systems to enable broadband connectivity with the Internet.

As an example, as PCs become more multimedia type devices, video and audio content are becoming important for PC users. Radio and television tuner add-on devices from numerous vendors are common place. Generally, these radio and/or television tuner add-on devices are peripheral devices that include an audio, video, or both, decoder (i.e., an audio/video decoder—also know generically as a “A/V decoder” and/or “video decoder”) that is capable of receiving a broadcast composite video signal (i.e., having luminance and chrominance spectra components, also known as channels) that is transmitted in one of the world's three television transmission formats (i.e., either NTSC, PAL, or SEACAM) and converts it to a digital data stream component video signal (i.e., having red, green, and blue “RGB” or “Y PbPr”) that has a format that is readable to the particular type of PC. Luminance (“Y”) describes a black and white image in full detail and chrominance (“C” also referred to as “UV”) describes coloration of the image. These types of video decoders may vary in the way they separate luminance and chrominance spectra in the composite video signal and generally include either a notch filter or comb filter.

In the case of video decoders utilizing a comb filter, the comb filter separates the composite video signal into both Y and C channels to reduce both cross-luma (i.e., cross-luminance) and cross-chroma (i.e., cross-chrominance) artifacts. The comb filter is utilized so that the resulting video images show fine picture detail from standard broadcasts, Laserdisk, and other composite sources. Video decoders utilizing a comb filters also reduce discolorations in fine picture detail and provide purer color overall.

In general, known video decoders utilize three-line (“3-line”) adaptive comb filters (also known as three-line two-dimensional “3-line 2D” comb filters) or higher quality three-dimensional (“3D”) comb filters (also know as “3D Y/C filter,” “3D digital comb filter,” or “motion adaptive” comb filters). As far as 3D comb filters, in addition to separating the Y and C channels of a composite video signal, a 3D comb filter also performs two additional functions. While comparing three consecutive horizontal scan lines within a single video frame, the 3D comb filter also analyzes each frame for improved image quality.

Unfortunately, known approaches to 3D comb filtering of composite video typically requires local memory frame buffers (on the video decoder) to hold the previous frames of video for use in the 3D comb filter. As a result, currently known peripheral devices utilizing 3D comb filters (such as, for example, PC TV 3D comb filter cards) have an additional standalone integrated circuit (“IC”) along with a dedicated dynamic read access memory (“DRAM”) to provide frame buffer storage of previous video fields required for the 3D comb filter. This additional hardware adds significant cost and complexity to the peripheral device and as peripheral devices move towards dual-tuner use, board space for all of the required additional components on the peripheral device also becomes an issue.

Therefore, there is a need for a new comb filter system on a peripheral device that does not require the utilization of dedicated DRAM on the peripheral device.

SUMMARY

A comb filter system that utilizes host memory (“CFSHM”) is disclosed. The CFSHM may include a comb filter, an allocated host memory, and an interface in signal communication with the comb filter and allocated host memory. The comb filter is located on a peripheral device and the allocated host memory is located within the host memory, wherein the host memory is located on a host device. Additionally, the interface is configured to allow the comb filter utilization of the allocated host memory.

In an example of operation, the CFSHM may allocate a portion of the host memory for allocated host memory and then utilize the allocated host memory with the comb filter.

DETAILED DESCRIPTION

In the following description of the preferred and various alternative embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the spirit and scope of this invention.

The invention is described with reference to various functional block diagrams, which illustrate possible applications of and embodiments of the invention from a functional perspective. These functional block diagrams should not be interpreted to imply or otherwise require a particular physical architecture in accordance with the partitioning of the functionality depicted therein. Instead, it will be appreciated by one of ordinary skill in the art that various alternative physical architectures (whether hardware, software or a combination thereof) can be used to implement the described functionality. For example, the invention can be implemented using various hardware and software components, including, for example, using a semiconductor integrated circuit (e.g., a chip) or a combination of semiconductor integrated circuits (e.g., a chipset or multi-chip module), or in associated circuitry, or in the software, firmware, protocol stacks, libraries, algorithms or other processes operating thereon (or in any configuration of one or more of the foregoing). The chip or chipset implementation may include an integrated circuit, including, for example, any of the following alone or in combination: an application specific integrated circuit (“ASIC”), a digital signal processor (“DSP”), or another general-purpose or specific-purpose processor, and associated circuitry (e.g., memory, co-processors, busses, etc.).

In general, a comb filter system that utilizes host memory (“CFSHM”) is disclosed. The CFSHM may include a comb filter, an allocated host memory, and an interface in signal communication with the comb filter and allocated host memory. The comb filter is located on a peripheral device and the allocated host memory is located within the host memory, wherein the host memory is located on a host device. Additionally, the interface is configured to allow the comb filter utilization of the allocated host memory.

Turning toFIG. 1, a functional block diagram of an example of an implementation of a comb filter system that utilizes host memory (“CFSHM”)100is shown. The CFSHM100may include a comb filter102, an allocated host memory104, and an interface106in signal communication with the comb filter102and allocated host memory104. The comb filter102is located on a peripheral device108and the allocated host memory104is located within the host memory110, wherein the host memory110is located on a host device112. The CFSHM100may also include a peripheral controller114located within the peripheral device108that is in signal communication with the interface106. The peripheral controller114may include peripheral controller software116. The host device112may also include a host controller118, in signal communication with the interface106, which includes host device software120.

As an example, the comb filter102is a device that receives a composite video input signal122and separates the Luminance (“Y”) channel124(which describes a black and white image in full detail) and chrominance (“C”) channel126(which describes coloration of the image). It is appreciated by those skilled in the art that comb filters are well known in the art.

The comb filter102may be a three-line (“3-line”) adaptive comb filter (also known as three-line two-dimensional “3-line 2D” comb filter) or a higher quality three-dimensional (“3D”) comb filter (also know as “3D Y/C filter,” “3D digital comb filter,” or “motion adaptive” comb filters). If the comb filter102is a 3D comb filter, in addition to separating the Y and C channels of a composite video input signal122, the 3D comb filter may also performs two additional functions. While comparing three consecutive horizontal scan lines within a single video frame, the 3D comb filter may also analyze each frame for improved image quality. Additionally, based on design criteria, a 3D comb filter system may be a hybrid device that includes notch filters, 2D comb filters, and 3D comb filters.

InFIG. 2, a functional block diagram of an example of an implementation of a 3D comb filter system200is shown. The 3D comb filter system200may include a notch filter202, 2D comb filter204, 3D comb filter206, motion detection module208, first frame storage module210, second frame storage module212, and blending module214. In general, the first frame storage module210and second frame storage module212are modules, circuitry, or devices that provide memory to store complete frames of data from an composite video input signal216. The motion detection module208is a module, circuitry, or device that detects inter-frame motion from the composite video input signal216. The blending module214is a module, circuitry, or device that includes blend logic configured to average the results of each filter (i.e., notch filter202, 2D comb filter204, or 3D comb filter206) with each other, according to the control provided by the motion detection module208.

In operation, the composite video input signal216is received by the 3D comb filter system200. The composite video input signal216is passed to both the first frame module210and the motion detection module208. The output signal218of the first frame module210is a one frame delayed version of the composite video input signal216. The output218of the first frame storage module210is then passed to the motion detection module208, second frame storage module212, the notch filter202, 2D comb filter204, and 3D comb filter206. The output signal220of the second frame module212is a one frame delayed version of the output signal218of the first frame module210, or in other words, an output signal220is two frame delayed version of the composite video input signal216. The output220of the second frame storage module212is then passed to the motion detection module208and 3D comb filter206. The motion detection module208then detects inter-frame motion from the composite video signal216and in response produces a number of control signals222,224,226,228that are passed to the filters (i.e., notch filter202, 2D comb filter204, or 3D comb filter206) and blending module214. As an example, the first control signal222of the motion detection module208is passed to the 3D comb filter206, the second control signal224of the motion detection module208is passed to the 2D comb filter204, and the third control signal226of the motion detection module208is passed to the notch filter202. The control signals222,224, and226are control signal that configure each respective filter, where each filter may be configured differently depending on the image content and the detection of motion within the image being transmitted by the composite video input signal216. The motion detection module208also outputs a blending control signal228that is passed to the blending module214. The blending control signal228controls how the outputs of each filter are blended together, if at all, to create a final output.

The blending module214then receives the blending control signal228from the motion detection module208, the separated luma channel230and chroma channel232from the 3D comb filter206, the separated luma channel234and chroma channel236from the 2D comb filter204, and the separated luma channel238and chroma channel240from the notch filter202. The blending module214then combines all the inputs utilizing the blending logic of the blending module214to produce a combined luma channel (“Y”)242and combined chroma channel (“C”)244based on the blending control signal228.

Returning toFIG. 1, allocated host memory104may be any portion of memory from the host memory110that is allocated to comb filter102. As an example, the host memory110may be DRAM system memory on personal computer (“PC”). In the case of the host device112being a PC, host memory110may be system DRAM memory and the host controller118may be a central processing unit (“CPU”) that runs operating system software for the host device software120. Examples of the host controller118include Intel® type processors, AMD® type processors, IBM® type processors, Motorola® power PC type processors, RISC processors, or any similar type microprocessor. Example of the host device software120may include Microsoft® Windows based operating systems (“OSs”), the as of yet not release Longhorn OS from Microsoft®, Apple® based operating systems, Linux based operating systems, IBM® OS-2 based OS, or other similar type OS.

The peripheral controller114may be a microcontroller, processor, microprocessor, ASIC, or DSP capable of controlling the operation of the peripheral device108. The peripheral controller software116may be any software capable of running on the peripheral controller114and controlling the peripheral device108.

The interface106is a high bandwidth interface bus capable of allowing the comb filter102to utilize the allocated host memory104without delays. The interface106may be a Peripheral Component Interface (“PCI”) type of interface that is compliant with PCI Express® interface architecture.

In an example of operation, the CFSHM100may allocate a portion of the host memory110for the allocated host memory104and then utilize the allocated host memory104with the comb filter102. Generally, the peripheral controller software116establishes communication with the host device software120on the host controller118and requests direct access to a portion of host memory110. The host device software120responds but allocating a portion of the host memory110into the allocated host memory104that the peripheral controller software116may access utilizing varying communication protocols such as, for example, utilizing Direct Memory Access (“DMA”) to access the allocated host memory104.

The allocated host memory104is dedicated to the comb filter in a way that provides dedicated, guaranteed bandwidth, minimal latency, non-local frame buffer memory for the comb filter102. In general, the allocated host memory104is allocated by the host device software120as non-snooped uncached memory in response to requests from a video capture driver (not shown) in the peripheral controller software116at driver initialization time. Once allocated, the allocated host memory104is allocated for exclusive use by the peripheral device108. Typically, the scatter gather virtual-to-physical address mapping information for the allocated host memory104is provided to the peripheral device108by the device driver in the peripheral controller software116, and after the comb filter102is enabled, neither the device driver nor the host controller118accesses the allocated host memory104. As a result, the comb filter102utilizes the allocated host memory104as a “true non-local storage”, and accesses the allocated host memory104as needed. In the case of the interface106having a PCI Express® interface architecture, the comb filter102utilizes an isochronous PCI Express® virtual channel enabled by the root complex, either through BIOS of the host device112or by other means allowed by the host controller118and host device software120.

InFIG. 3, a functional block diagram of an example of another implementation of CFSHM300is shown utilizing a video decoder302with a 3D comb filer in the peripheral device304, PC as a host device306, and a PCI Express® interface architecture for the interface308. The host device306may include allocated host memory310and a CPU312. Similar toFIG. 1, the allocated host memory310may be a portion of host memory (not shown) and may be, for example, DRAM system memory. The CPU312is the host controller and may run an OS such as, for example, Microsoft® Windows based OS or Apple® based OS. Both the allocated host memory310and CPU312are in signal communication with the interface308. In this example, the interface308utilizes PCI Express® interface architecture such that it is appreciated by those skilled in the art that the interface includes a PCI Express® root complex module314and PCI Express® end point module316.

The peripheral device304may be a multimedia system on a chip such as television and/or video capture card. The peripheral device304may include the video decoder302with a 3D comb filter, a configurable depth FIFO module318, and a DMA controller320.

In an example of operation, once the CFSHM300has allocated a portion of the host memory (not shown) for the allocated host memory310, the 3D comb filter of the video decoder302utilizes the allocated host memory310in a dedicated manner via the DMA controller320. The configurable depth FIFO module318is a module that assures that any data to and from the video decoder302to the allocated host memory310is synchronized in that that the data that is first to go in to the configurable depth FIFO module318is the first to go out.

InFIG. 4, a flowchart diagram400of an example of operation of the CFSHM is shown. The process begins in step402and the system powers up404. The interface and peripheral device negotiate a communication link in step406. As an example, if the interface utilizes a PCI Express® chipset, the PCI Express® chipset and peripheral device may negotiate a 2.5 gigabit x1 PCI Express® Link. In the example of the interface utilizing a PCI Express® chipset, the host device BIOS may scan the PCI® device tree to find the peripheral device and then adds the peripheral device to device tree in step408. The OS loads and finds peripheral device in BIOS device tree in step410. The OS then assigns a physical and virtual memory base address and interrupt resources to the peripheral device in step412. The OS, based on the PCI Express® configuration space device ID values, finds and loads the peripheral device driver in step414. The device driver reads the OS registry and determines that 3D comb feature is requested in step416. The device driver then allocates guaranteed physical resident and contiguous memory to hold the comb filter's raw sample frame buffers (such as, for example, two full frames plus two lines) in step418. The device driver then requests from OS the virtual to physical memory address mapping for allocated memory in step420. The device driver then generates looped hardware DMA read program for frame N-2starting at beginning of allocated memory in step422and the device driver generates looped hardware DMA read program for frame N-1starting in middle of allocated memory in step424. The device driver then generates looped hardware DMA write program for frame N starting at beginning of allocated memory in step426. The device driver then configures internal SRAM FIFOs (not shown) for expected PCI Express® DMA latency protection in step428. The application then starts the process of video capture in step430and the 3D comb parameters in the video digitizer hardware (such as video decoder302) is initialized in step432. In step434, with the 3D comb DMA engines started, the 3D comb processes the video data with no interaction from the OS.

In decision step436, an error condition is tested. If a DMA FIFO overflow or underflow event occurs due to excessive PCI Express® bus latency during reading or writing to host memory, the process continues to step438. If no overflow or underflow event occurs, the process returns to step430and the application continued to video capture and process loops through steps430to436.

In step438, the peripheral device generates an interrupt in response to the error condition in decision step436. As a result, the peripheral device driver receives an interrupt function call from OS in step440and the device driver reads the hardware status registers and determines that a FIFO underflow or overflow event occurred in step442. The device driver logs event and time of occurrence in step444and the process continues to decision step446.

In decision step446, a second error condition is tested. If an additional overflow or underflow events occur in a short period of time, the process continues to decision step448. If no overflow or under flow events occur, the process returns to step430and the application continued to video capture and process loops through steps430to436.

In decision step448, if additional SRAM FIFO space available in device, the device driver stops the 3D comb filter and increases the FIFO size for additional latency protection in step450. The process then returns to step428and the process loops through steps428to436. If the no additional SRAM FIFO space is available in device, the device driver disables the 3D comb filter feature by turning off the DMA and reprogramming the video decoder settings in step452. The application then stops video capture in step454and the device driver stops the 3D comb filter DMAs in step456. The OS requests that device driver be unloaded in step458. In response, the device driver releases allocated comb filter frame buffer memory back to the OS in step460and the process ends462. It is appreciated that while this example of a process has been described utilizing a PCI Express® chipset, any high bandwidth interface may be utilized in a similar way without departing from the sprit of the invention.

Persons skilled in the art will understand and appreciate that one or more processes, sub-processes, or process steps described inFIG. 4may be performed by hardware and/or software. Additionally, the CFSHM may be implemented completely in software that would be executed within a microprocessor, general purpose processor, combination of processors, digital signal processor (“DSP”), and/or application specific integrated circuit (“ASIC”). If the process is performed by software, the software may reside in software memory in the controller. The software in software memory may include an ordered listing of executable instructions for implementing logical functions (i.e., “logic” that may be implemented either in digital form such as digital circuitry or source code or in analog form such as analog circuitry or an analog source such as an analog electrical, sound or video signal), and may selectively be embodied in any computer-readable (or signal-bearing) medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that may selectively fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “computer-readable medium” and/or “signal-bearing medium” is any means that may contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer readable medium may selectively be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples, but nonetheless a non-exhaustive list, of computer-readable media would include the following: an electrical connection (electronic) having one or more wires; a portable computer diskette (magnetic); a RAM (electronic); a read-only memory “ROM” (electronic); an erasable programmable read-only memory (EPROM or Flash memory) (electronic); an optical fiber (optical); and a portable compact disc read-only memory “CDROM” (optical). Note that the computer-readable medium may even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

While various preferred and alternative embodiments of the present intention are described herein, it will be apparent to one of ordinary skill in the art after reading this description that there are various modifications and extensions of the above described technology that may be implemented using these teachings without departing from the spirit and scope of the present invention, the breadth and scope of which shall be defined by following claims.