Method and device for measuring the capacitance of a capacitive component

A method of measuring the capacitance of a capacitive component (21), whereby a digital bridge with two measuring branches generates a first signal (B1) defined by a train of measuring pulses (M) having a frequency (f1) related to the unknown capacitance being measured, and a second signal (B2) defined by a train of reference pulses (L) having a frequency (f2) related to a reference capacitance (CREF) of known value. The time difference (ΔT) between the times (T1, T2) taken by the two measuring branches of the digital bridge to generate an equal number of pulses (Th1, Th2) is calculated. The capacitance difference (ΔC) between the unknown capacitance and the reference capacitance (CREF) is determined as a function of the time difference (ΔT). The unknown capacitance of the capacitive component (21) is calculated on the basis of the reference capacitance (CREF) and the capacitance difference (ΔC).

BACKGROUND OF THE INVENTION

The present invention relates to a method and device for measuring the capacitance of a capacitive component.

More specifically, the present invention relates to a method and device for accurately determining the capacitance of a capacitive component varying as a function of a physical quantity, such as the amount of liquid in a vessel; to which the following description refers purely by way of example.

As is known, some electronic devices currently used to determine the amount of liquid in a vessel or the pressing of a key employ a capacitive component varying in capacitance as a function of the quantity to be determined; and a measuring device connected to the capacitive component to measure its capacitance and provide a quantitative indication of the physical quantity causing the variation in capacitance.

Some measuring devices used for the above purposes are of digital circuit architecture, wherein a multivibrator stage is connected to the capacitive component to oscillate and generate a train of pulses frequency-related to the capacitance of the capacitive component. The multivibrator stage is also connected to a counter stage, which counts the pulses generated by the multivibrator stage and supplies an interrupt signal when the pulse count, as of a start instant in which a reset signal is received, reaches a predetermined count threshold.

The reset signal and interrupt signal are generated/received by a microprocessor with an internal clock for measuring the time interval between the instant the reset signal is generated and the instant the interrupt signal is received, and on the basis of which the capacitance of the capacitive component is determined.

By way of a non-limiting example,FIG. 1shows a measuring device1of digital architecture as described above, and for measuring the capacitance of a capacitive component4defined, for example, by a capacitor. The capacitor comprises a first plate, and a second plate polarized to a ground potential VGND; and the first and second plate respectively define a measuring electrode4aand a reference electrode4bof measuring device1, which are typically located in a vessel to determine a liquid level.

More specifically, measuring device1substantially comprises a microprocessor processing unit2, which generates a reset signal R synchronized with the instant an internal clock2ais activated, and which receives an interrupt signal I to stop the clock; and a pulse generating circuit3, in turn comprising a multivibrator stage5and a counter stage6.

More specifically, multivibrator stage5has a terminal5areceiving reset signal R; a terminal5bconnected to measuring electrode4a; a terminal5cconnected to reference electrode4b; and an output5dwhich generates a switching signal B defined by a train of rectangular pulses D frequency-related to the capacitance of capacitive component4, as shown inFIG. 2.

More specifically, multivibrator stage5is typically defined by a Schmitt trigger, and counter stage6has a terminal6awhich receives reset signal R to start the count of pulses D; a terminal6bwhich receives the train of pulses D; and a terminal6cwhich generates interrupt signal I when the number of pulses D reaches a predetermined trigger threshold Th.

With reference toFIG. 2, the capacitance of capacitor4is measured by measuring device1at predetermined time intervals TI, each started by the microprocessor generating reset signal R.

During each time interval TI, microprocessor2activates the clock and, at the same time, supplies reset signal R to multivibrator stage5and counter stage6.

More specifically, reset signal R is received as a trigger pulse by multivibrator stage5, which switches from a rest condition to an oscillating condition (point P inFIG. 2) in which multivibrator stage5generates pulses D with a frequency proportional to the capacitance of capacitive component4.

Reset signal R also starts the count of pulses D by counter stage6.

As long as the pulse D count is below predetermined trigger threshold Th, interrupt signal I switches to a first, e.g. high, logic level. Conversely, when the pulse D count equals predetermined trigger threshold Th (point E inFIG. 2), interrupt signal I switches to a second—in this case, low—logic level to stop the pulse count. At this point, microprocessor2determines the time interval TA between the start and end of the pulse D count, and accordingly calculates the capacitance value.

BRIEF SUMMARY

Measuring devices of the above type perform particularly well when measuring large variations in capacitance, but not so well in the case of small variations.

It is an object of the present invention to provide a device and method for measuring the capacitance of a capacitive component to a greater degree of precision than that of known devices.

According to the present invention, there are provided a device and method for measuring the capacitance of a capacitive component, as defined in the accompanying Claims.

DETAILED DESCRIPTION

The present invention is substantially based on the principle of:generating, by means of a digital bridge with two measuring branches, a first signal defined by a train of pulses frequency-related to the unknown capacitance to be determined, and a second signal defined by a train of pulses frequency-related to a reference capacitance of known value;calculating the difference in the times taken by the two measuring branches of the digital bridge to generate an equal number of pulses:determining the difference between the unknown capacitance and the reference capacitance as a function of the difference in the times taken by the two measuring branches of the digital bridge to generate an equal number of pulses; andcalculating the unknown capacitance on the basis of the reference capacitance and the above calculated difference.

FIG. 3shows a block diagram of a measuring device20for measuring the capacitance of a capacitive component in accordance with the present invention.

More specifically, in theFIG. 3embodiment, the capacitive component21has a first plate, and a second plate polarized to a reference potential, preferably but not necessarily a ground potential VGND; and the first and second plate respectively define a measuring electrode21aand a reference electrode21bof measuring device20.

Measuring device20substantially comprises a pulse generating circuit23, to which is connected the capacitive component21whose capacitance is to be determined; a pulse generating circuit24, to which is connected a reference capacitive component25, e.g. a capacitor having a reference capacitance CREFof known constant value; a logic circuit26for generating a logic signal, which assumes a logic level for a time related, in particular, proportional, to the difference ΔC between reference capacitance CREFand the unknown capacitance being measured, as described in detail below; and a processing unit22configured to determine the unknown capacitance being measured, as a function of difference ΔC and the value of reference capacitance CREF.

More specifically, in theFIG. 3example, pulse generating circuits23and24are both of the same digital architecture as pulse generating circuit3inFIG. 1, i.e. each comprise a multivibrator stage and a counter stage.

More specifically, pulse generating circuit23comprises a multivibrator stage23a, preferably, though not necessarily, defined by a Schmitt trigger or any other similar multivibrator circuit, e.g. bistable multivibrator, which has an input terminal27receiving a reset signal R; a first and second input terminal28,29connected respectively to measuring electrode21aand reference electrode21bof capacitive component21; and an output terminal30which supplies a switching signal B1defined by a train of measuring pulses M having a frequency f1related to the capacitance of capacitive component21.

Pulse generating circuit23also comprises a counter stage23b, in turn comprising an input terminal31receiving reset signal R, which also starts the count of measuring pulses M by counter stage23b; an input terminal32receiving switching signal B1; and an output terminal33supplying an interrupt signal I1.

As long as the measuring pulse M count is below a predetermined first trigger threshold Th1, counter stage23bswitches interrupt signal I1to a first, e.g. high, logic level. Conversely, when the measuring pulse M count equals predetermined trigger threshold Th1(point F inFIG. 4), counter stage23bswitches interrupt signal I1to a second—in this case, low—logic level to stop the measuring pulse M count.

Pulse generating circuit24comprises a multivibrator stage24a, preferably, though not necessarily, defined by a Schmitt trigger or any other similar multivibrator circuit, e.g. bistable multivibrator, which has an input terminal35receiving a reset signal R; a first and second input terminal36,37connected respectively to a first and second terminal of reference capacitive component25; and an output terminal38which supplies a switching signal B2defined by a train of reference pulses L having a frequency f2related to the reference capacitance CREFof reference capacitive component25.

Pulse generating circuit24also comprises a counter stage24b, in turn comprising an input terminal39receiving reset signal R, which also starts the count of reference pulses L by counter stage24b; an input terminal40receiving switching signal B2; and an output terminal41supplying an interrupt signal I2.

As long as the reference pulse L count is below a predetermined second trigger threshold Th2(e.g. Th2=Th1), counter stage24bswitches interrupt signal I2to a first, e.g. high, logic level. Conversely, when the reference pulse L count equals predetermined trigger threshold Th2(point U inFIG. 4), counter stage24bswitches interrupt signal I2to a second—in this case, low—logic level to stop the reference pulse L count.

Logic circuit26comprises a first and second input terminal42,43receiving interrupt signals I1, I2respectively; and an output terminal44generating the logic signal ST, which assumes a first, e.g. low, logic level when both interrupt signals I1and I2are at the same logic level, and, conversely, assumes a second, e.g. high, logic level when interrupt signals I1and I2are at different logic levels.

More specifically, logic circuit26may comprise an XOR gate or any similar circuit.

Processing unit22, for example, is a microprocessor type, and comprises an output generating reset signal R to synchronize oscillation and the pulse count of the two pulse generating circuits23and24; and an input receiving logic signal ST.

From the duration of a logic level of signal ST, processing unit22is able to determine the time difference ΔT between the times T1and T2taken by the two pulse generating circuits23and24of measuring device20to generate an equal number of pulses.

On the basis of time difference ΔT, processing unit22is also able to determine the difference in capacitance ΔC between reference capacitive component25and capacitive component21, and so calculate the capacitance of capacitive component21as a function of capacitance difference ΔC and reference capacitance CREF.

The operating method of measuring device20will now be described with reference toFIG. 4, and assuming trigger thresholds Th1and Th2equal a number n of 256 pulses, and that reference capacitance CREFdiffers from the unknown capacitance being measured, and is such that frequency f2of reference pulses L generated by pulse generating circuit24substantially equals frequency f1of measuring pulses M generated by pulse generating circuit23.

Firstly, processing unit22generates reset signal R, which, on the one hand, acts as a trigger to activate oscillation of multivibrator stages23aand24a, and, on the other, starts the pulse count by counter stages23band24b.

More specifically, multivibrator stage23agenerates the pulse signal B1containing the train of measuring pulses M of frequency f1, and, at the same time, multivibrator24agenerates the pulse signal B2containing reference pulses L of frequency f2.

At this step, counter stages23band24bcount measuring pulses M and reference pulses L respectively.

When the measuring pulse M count reaches trigger threshold Th1, counter stage23bswitches interrupt signal I1from the high to low logic level; and, at the same time, when the reference pulse L count reaches trigger threshold Th2, counter stage24bswitches interrupt signal I2from the high to low logic level.

The unknown capacitance and the reference capacitance being different, interrupt signals I1and I2switch at different instants.

More specifically, in theFIG. 4example, interrupt signal I1switches before interrupt signal I2. In the interval between the two switching, interrupt signals I1and I2are therefore at different logic levels, so logic circuit26switches signal ST from a low to high logic level throughout the time interval ΔT this condition persists, and which ends the instant interrupt signal I2switches.

Time interval ΔT therefore represents the difference between time T1proportional to the unknown capacitance value, and time T2proportional to the reference capacitance CREFvalue.

Signal ST therefore contains a square pulse of a duration corresponding to time interval ΔT, and which is supplied to processing unit22.

At this point, processing unit22determines the capacitance difference ΔC between reference capacitance CREFand the unknown capacitance being measured, as a function of time interval ΔT and according to the equation:
ΔC=f(ΔT)=ΔT/(R*K)
in which R is the resistance of a resistor in the Schmitt trigger; K is a constant.

At this point, processing unit22determines the unknown capacitance of capacitive component21on the basis of the reference capacitance CREFvalue and capacitance difference ΔC.

With reference toFIG. 3, to make measuring device20particularly insensitive to external electromagnetic noise, a compensating electrode45can be connected to input terminal36of multivibrator stage24ato supply multivibrator stage24awith electromagnetic noise identical to that supplied to multivibrator stage23aby measuring electrode21a.

Any variations produced by external electromagnetic noise in interrupt signals I1and I2are thus identical, on account of the two pulse generating circuits23,24having the same circuit configuration and receiving the same noise signals.

More specifically, being identical, noise-induced variations have absolutely no effect on the capacitance measurement, and, in fact, are reduced by logic circuit26determining the difference in the instants interrupt signals I1and I2switch.

It should also be pointed out that, for particularly effective noise compensation, multivibrator stage24amust be defined by a circuit identical to the electronic circuit of multivibrator stage23a, and, at the same time, counter stage23bmust be defined by a circuit identical to the electronic circuit of counter stage24b.

In connection with the above, it should be pointed out that, in an embodiment not shown, measuring device20is connectable by a switching circuit (e.g. a multiplexer) to a number of capacitive components for measurement. By appropriately synchronizing switching of the switching circuit, measuring device20can therefore measure the capacitances of a large number of capacitive components21.

FIG. 5shows one possible application of measuring device20, in an apparatus50for measuring the level of a liquid L in a vessel51.

More specifically, in theFIG. 5example, capacitive component21being measured has measuring electrode21aand reference electrode21bfitted to the inside or outside of vessel51. For example, measuring electrode21aand reference electrode21bmay be positioned facing each other and parallel to the inside or outside walls of vessel51, and may be fitted to or incorporated in vessel51.

Measuring apparatus50also preferably comprises compensating electrode45, which is fitted to vessel51, next to measuring electrode21a, so as to receive the same noise signals and supply them to pulse generating circuit24to which it is connected.

A variation in the amount of liquid L in vessel51produces a corresponding variation in the capacitance of capacitive component21, which is measured by measuring device20; and processing unit22determines, as a function of the capacitance measurement, the corresponding amount of liquid L in vessel51.

In addition to being straightforward and cheap to produce, measuring device20described above has the major advantage of accurately measuring both large and small variations in capacitance.

Moreover, using compensating electrode45, measuring device20compensates for any input noise, particularly at the measuring electrode, and is therefore highly resistant to electromagnetic noise.

Clearly, changes may be made to the device and method as described herein without, however, departing from the scope of the present invention, as defined in the accompanying Claims.