Method for selective growth of highly doped group IV—Sn semiconductor materials

Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to European Patent Application Serial No. EP 12176741.2 filed Jul. 17, 2012, the contents of which are hereby incorporated by reference.

BACKGROUND

In some applications, it may be desirable to selectively provide a highly doped Group IV-Sn semiconductor material, such as, for example, SiSn, SiGeSn or GeSn, on semiconductor surfaces without providing the same on insulating surfaces. For example, complementary metal-oxide-semiconductor (CMOS) transistors may be fabricated using methods that provide mono-crystalline semiconductor films only on the active areas of the transistors (e.g., source/drain structures). Other examples are possible as well.

Typically, the dopants in the group IV-Sn semiconductor material are provided by means of implantation of the dopants in this material. For example, Boron implantation in GeSn is described by B. Vincent et al. in “Characterization of GeSn materials for future Ge pMOSFETs source/drain stressors,” Microelectronic Engineering 88 (2011) 342-346. This approach, however, is difficult for shallow junctions. Moreover, after implantation, an anneal step is required to activate the dopants. For GeSn, the thermal budget of this anneal step is limited to temperatures below 600° C. in order to avoid Sn precipitation. This low temperature thermal budget then limits the Boron activation.

SUMMARY

Disclosed are methods for the selective deposition of doped Group IV-Sn semiconductor materials. In some embodiments, the methods may be directed to the deposition of highly doped Group IV-Sn semiconductor materials. The (highly) doped Group IV-Sn semiconductor materials deposited using the disclosed methods may be used at low processing temperatures, e.g., below 650° C., below 550° C., or below 500° C., below 400° C., or even below 350° C.

Disclosed are methods for providing selective deposition of a doped Group IV-Sn material on a first semiconductor material. The method includes providing a patterned substrate comprising at least a first region and a second region, where the first region comprises an exposed first semiconductor material and the second region comprises an exposed insulator material. The method further includes depositing the doped Group IV-Sn layer by providing a precursor of the group IV semiconductor material, SnCl4acting at the same time as a Sn precursor and a selective growth regulator, a dopant precursor, and optionally, depending on the deposition process, a carrier gas. The method further includes thereafter etching back the deposited doped group IV-Sn layer using an etch gas until the layer is substantially completely removed from the second region, thereby compensating a loss in selectivity of the depositing step due to the interaction between the selective growth regulator and the dopant precursor. The depositing and etching steps may be repeated in a grow-etch cyclic process.

During deposition, monocrystalline doped group IV-Sn material may be grown on the first region and polycrystalline doped group IV-Sn material may be grown on the second region. During the etch step, the polycrystalline doped group IV-Sn material may be removed more quickly than the monocrystalline doped group IV-Sn material, thereby leaving some monocrystalline doped group IV-Sn material on the first region while removing substantially all the polycrystalline doped group IV-Sn material from the second region.

In some embodiments, providing the patterned substrate may include loading the patterned substrate into a chemical vapor deposition chamber.

In some embodiments, the doped Group IV-Sn layer may be deposited a temperature lower than 650° C., lower than 500° C., or even lower than 350° C. Thus, the disclosed methods allow for the deposition of doped Group IV-Sn layers at low processing temperatures.

In some embodiments, the doped Group IV-Sn layer may be a GeSn:B layer having a dopant concentration of, for example, at least about 1·1018at·cm−3.

In some embodiments, the Group IV precursor may be a germanium precursor. Further, in some embodiments, the Group IV precursor may be Ge2H6or a higher order germanes. In some embodiments, the Group IV precursor may be provided at a partial pressure higher than 10 mTorr.

In some embodiments, the dopant precursor may be B2H6. In these embodiments, a dopant concentration of at least about 1·1018at·cm-3 may be obtained.

In some embodiments, the doped Group IV-Sn layer may have a Sn concentration of at least about 5 at %.

In some embodiments, the insulator material may be selected from the group consisting of an oxide of a group IV element, a nitride of a group IV element, and any combination thereof.

In some embodiments, the first region may comprise silicon, germanium, or silicon germanium. Alternatively, in some embodiments the first region may comprise a binary or a tertiary III-V compound such as a III-V compound selected from a group consisting of III-antimonides, III-arsenides, III-phosphides, and any combination thereof.

For purposes of summarizing the disclosure and the advantages achieved over the prior art, certain objects and advantages of the disclosure have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosure. Thus, for example, those skilled in the art will recognize that the disclosure may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

The above and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

It will be understood that the drawings are merely illustrative and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the disclosure.

DETAILED DESCRIPTION

The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims.

It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the disclosure with which that terminology is associated.

In the context of the present disclosure, a precursor is a product, element or compound that participates in a chemical reaction that produces another product, element or compound, whereby at least part of the precursor after reaction forms part of the another product, element or compound. In particular in the context of the present disclosure, the referenced chemical reaction is a deposition reaction for depositing a semiconductor material film or layer.

In the context of the present disclosure, a single source precursor is a precursor where all the elements required into the other compound are provided in that single precursor.

In the context of the present disclosure, a carrier gas is a gas stream that brings a precursor of semiconductor material and tin-tetrachloride (SnCl4) into the chemical vapor deposition (CVD) chamber. The carrier gas can be any inert gas (i.e., a gas that is non-reactive with other components in the CVD chamber). The inert gas may be elemental, such as, for example, in the case of noble gases, or may be a compound gas. In some embodiments, the inert gases may be specifically selected for the particular operational settings of the CVD chamber for which they are functionally inert. In other embodiments, no carrier gas may be used (e.g., an ultra-high vacuum chemical vapor deposition (UHVCVD) process does not require a carrier gas).

The tin-tetrachloride carrier gas may be added at the same time as a Sn precursor and as a source of etchant material (Cl) to regulate selective growth.

It has been found that for Boron-doped GeSn growth, the selectivity of the growth is reduced or even partially lost irrespective the carrier flow used. The addition of B2H6in the gas phase reaction forms B2Cl6by-products with SnCl4and reduces selectivity. To regain selectivity, Clxproducts may be added in the reaction. For example, by adding HCl and/or using higher SnCl4flows, the selectivity may be regained. Other examples are possible as well. However, such addition of HCl and/or use of higher SnCl4flows may result in a very limited Boron incorporation due mainly to the formation of B2Cl6by-products. Thus, adding HCl and/or using higher SnCl4flows is not conducive to the selective deposition of doped Group IV-Sn material at certain dopant concentrations (e.g., with a dopant concentration of 1×1019at·cm−3or above), such as GeSn:B layers with high Boron concentrations (e.g., 2×1020at·cm−3).

The disclosed methods begin with providing a substrate. The patterned substrate may, for example, be similar to the example patterned substrate100illustrated inFIG. 1. The patterned substrate100may be formed of a semiconductor material, such as, for example, silicon, germanium, silicon-germanium, III/V compound substrates, or another material compatible with the semiconductor manufacturing such as glass, quartz. The patterned substrate100may further take the form of a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate. In some embodiments, the patterned substrate100may be a silicon wafer. Other patterned substrates are possible as well.

As shown, the patterned substrate100includes a first region102and a second region104. The first region102may include an exposed first semiconductor material. The first semiconductor material may be the semiconductor material of the patterned substrate100, as shown, or may be a layer of another semiconductor material grown epitaxially on the patterned substrate100, such as, for example, silicon, germanium, silicon germanium, or a binary or a tertiary III-V compound (e.g., III-antimonides, III-arsenides, III-phosphides and any combination thereof). Other first semiconductor material are possible as well.

The second region104may include an exposed insulator material. The insulator material may be, for example, an oxide or a nitride of a Group IV element or any combination thereof. In some embodiments, the insulator material may further comprise a second Group IV element, such as Carbon (C). The insulator material may, for example, be silicon oxide, silicon nitride, or any combination thereof. Other insulator materials are possible as well.

The disclosed methods may further include loading the patterned substrate100into a CVD chamber. A doped Group IV-Sn material may then be selectively deposited on the exposed first semiconductor material in the first region102. The group IV-Sn semiconductor material may comprise one or more Group IV elements. In some embodiments, the Group IV-Sn semiconductor material may be selected from the group consisting of Sn alloyed Si, Ge or SiGe and any combination thereof. Other Group IV-Sn semiconductor materials are possible as well. The deposition conditions of the group IV-Sn semiconductor material may be such that mono-crystalline material is deposited.

To this end, a cyclic deposition-etch process may be used. In such process, a non-selective deposition is alternated with an etch in the CVD chamber; hence the supplies of etchant gas and dopant elements are both interrupted and alternated.

Such a cyclic deposition-etch process may allow for the selective deposition of a doped Group IV-Sn material on the exposed first semiconductor material in the first region102. The doped Group IV-Sn material may be, for example, SiGeSn:B or GeSn:B. Other Group IV-Sn materials are possible as well.

In some embodiments, the doped Group IV-Sn material may be a highly doped (e.g., may have a concentration of at least 5 at %). In embodiments where the doped Group IV-Sn material is SiGeSn:B or GeSn:B, the doped Group IV-Sn material may have a high concentration of both Sn and B. For example, the doped Group IV-Sn material may have a concentration of Sn of at least about 5 at %, and may have a concentration of B of about 1·1018at·cm−3or higher, of about 1·1019at·cm−3or higher, or even of about 2·1020at·cm−3or higher.

During the deposition step, a monocrystalline doped Group IV-Sn material (e.g., monocrystalline GeSn:B) may be grown in the first region102, while a polycrystalline doped Group IV-Sn material (e.g., polycrystalline GeSn:B) may be deposited in the second region104. Hereto a precursor of the Group IV semiconductor material may be provided, and SnCl4 may be provided as a Sn precursor. SnCl4is a stable precursor, suitable for low temperature deposition processes. The Group IV precursor may be, for example, a gas comprising the Group IV element. Further, the Group IV precursor may be, for example, a single-source precursor (e.g., SixH2x+2, GexH2x+2, SiClxH4−x, SiH3—CH3, or combined SixGeyH2(x+y)+2precursors) or a mixture of two or more precursors (e.g., SixH2x+2or GexH2x+2). In some embodiments, the SnCl4may be provided to the deposition chamber diluted in a carrier gas, such as N2or H2or an inert gas.

Further, a dopant precursor may be provided, and optionally, depending on the deposition process, a carrier gas may be provided. By adding a dopant precursor, the Group IV-Sn semiconductor material may further comprise n-type (e.g., P, As) or p-type (e.g., B) dopants. The carrier gas may be, for example, N2, H2or a noble gas (He, Ar). For example, because a UHVCVD process runs without a carrier gas, in embodiments where UHVCVD is used, no carrier gas may be provided. For example, in embodiments where GeSn:B is to be grown, Ge2H6may be provided as the Group IV semiconductor material precursor, SnCl4may be provided as the Sn precursor, B2H6may be provided as the dopant precursor, and H2or N2may be provided as the carrier gas. Other examples are possible as well.

Thereafter, during the etching step, the polycrystalline doped Group IV-Sn material (e.g., polycrystalline GeSn:B) may be removed by the etch step more quickly (e.g., at a higher etch rate) than the monocrystalline doped Group IV-Sn material (e.g., monocrystalline GeSn:B). Hereto, an etchant gas such as HCl or Cl2may be provided in the CVD chamber. During the etching step, the deposited doped Group IV-Sn layer may be etched back using an etch gas until the layer is substantially completely removed from the second region104comprising the exposed insulator material, thereby compensating a loss in selectivity of the depositing step due to the interaction between the selective growth regulator and the dopant precursor, as described above.

The cycle of deposition and etching is repeated until a desired, predetermined doped Group IV-Sn (e.g., polycrystalline GeSn:B) material thickness is obtained.

In particular embodiments, the same temperature and pressure may be kept for both the growth and etch steps.

In some embodiments, it may be desirable to provide the dopant precursor and the etchant gas serially, rather than simultaneously, in the CVD chamber. For example, in embodiments where GeSn:B is to be selectively grown, providing B2H6and HCl or Cl2simultaneously in the CVD chamber may result in the generation of B2Cl6byproducts, which severely reduce the dopant incorporation in the semiconductor material formed. Hence, with such simultaneous provision high dopant concentrations (e.g., 1·1018at·cm−3or higher, or 1·1019at·cm−3or higher, or even 2×1020at·cm−3) could not be obtained. This may be addressed by carrying out a cyclic process, as described above, in which steps where dopants are present in the CVD chamber alternate with steps where etchant gas is present in the CVD chamber.

FIG. 2shows a schematic representation of the growth-etch cyclic process, in accordance with some embodiments. This process includes growth steps indicated (1), in which growth of the Group IV-Sn material takes place by supplying a Group IV semiconductor precursor (e.g. Ge2H6), a Sn precursor (e.g., SnCl4), a dopant precursor (e.g., B2H6), and a carrier gas (e.g., H2or N2); and etch steps indicated (2), in which an etchant gas (e.g., HCl or Cl2or any other etch gas known in the art) is supplied in the CVD chamber. In the context of the present disclosure, SnCl4is not used as an etch gas but as an Sn precursor. In some embodiments, such as that shown, the etch rate may be much lower than the growth rate, with the result that the etch steps may be substantially longer than the growth steps. For example, in embodiments where HCl is used as etchant, the etch rate may be about 0.7 nl/min (as shown inFIG. 3and described below), which is about 10 times lower than the growth rate. As a result, the etch time (e.g., t2, t4, t6, . . . , ti+1) will be about ten times longer than the growth time (e.g., t1, t3, t5, . . . , ti). For example, the etch time may be approximately 10 minutes, while the growth time may be approximately 1 minute. Other examples are possible as well. In other embodiments, not illustrated, such as those where Cl2is used as etchant, the etch rate may be higher.

FIG. 3illustrates the etch rate of polycrystalline GeSn etched at 320° C. at an atmospheric pressure for 200, 1000, and 2000 sscm of HCl. However, specific values of growth time and etch time depend on the overall pressure in the reactor, the partial pressures of the different precursors, the precursor choice and the process temperature.

The disclosed methods allow for the selective deposition of Group IV-Sn material at a temperature lower than 650° C., or even lower than 400° C. Thus, the disclosed methods may be used for low temperature selective deposition.

Deposition of the Group IV-Sn semiconductor material may be suitably conducted according to any of the various CVD methods known to those skilled in the art, including, but not limited to, e.g., atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), and ultra high vacuum CVD (UHVCVD). While typical CVD deposition temperatures range from about 200° C. to about 800° C., in some embodiments the disclosed methods may allow for deposition at temperatures below 650° C., below 500° C., or even below 350° C.

In some embodiments, the Group IV semiconductor material to be selectively deposited may be GeSn. In these embodiments, the patterned substrate may include first regions of germanium and second regions of silicon oxide. The Group IV precursor may be a germanium precursor, such as, for example, germane, digermane, trigermane and higher order germanes, such as neo-pentagermane.

In these embodiments, digermane can be used at temperatures below 500° C. in combination with SnCl4and the growth-etch cyclic process described above to provide selective deposition of GeSn. Both precursors are widely available and do not impose safety constraints at this manufacturing step. This represents a clear advantage of the method in contrast with solutions known to present serious safety risks.

Therefore, the disclosed methods may be suitable for epitaxially growing GeSn for different applications, such as, for example, elevated source/drain applications. Other Group IV semiconductor materials and other applications are possible as well.

While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The foregoing description details certain embodiments of the disclosure. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the disclosure may be practiced in many ways. The disclosure is not limited to the disclosed embodiments.