Image sensor and imaging apparatus

An image sensor includes a unit pixel that includes a photoelectric converter configured to accumulate electric charges generated based on incident light, and an electric charger configured to store the electric charges transferred from the photoelectric converter, and a corrector configured to correct a signal corresponding to the electric charges output from the electric charger based on a transfer condition when the electric charges are transferred from the photoelectric converter to the electric charger.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an image sensor and an imaging apparatus.

Description of the Related Art

A recent digital single-lens reflex camera and a video camera often use a CMOS image sensor. The CMOS image sensor has been developed and required for many pixels, fast imaging, and high ISO speed. Most of recent CMOS image sensors have more than ten million pixels.

The CMOS image sensor has a photodiode (“PD” hereinafter) for each pixel, and the electric charges stored in the PD are transferred to an electric charger and sequentially read via an output line from the electric charger. When the electric charges are transferred to the electric charger from the PD, the incomplete transfer that cannot transfer all the electric charges is likely to occur. An optimization of the manufacturing condition, such as a concentration of a charge transfer path, is necessary for the complete transfer. However, as the pixel pitch reduces due to the increased pixel number, the optimization control becomes very difficult and the incomplete transfer of some electrons may occur due to slight errors. The incomplete transfer deteriorates the output value characteristic (linearity) that should originally be proportional to the incident light quantity.

Japanese Patent No. 4,678,824 discloses an imaging apparatus that adds an offset correction amount for correcting a charge loss caused by the incomplete transfer to an electric signal generated from the image sensor. Japanese Patent Laid-Open No. 2002-27326 discloses a digital camera that enables a captured state to be live-view confirmed by repeating the transfer from the PD to the electric charger and a nondestructive readout from the electric charger.

The imaging apparatus disclosed in Japanese Patent No. 4,678,824 changes an offset correction value in accordance with the imaging sensitivity considering the influence of the incomplete transfer different from the imaging sensitivity. Since the influence of the incomplete transfer is different according to the voltage value in the transfer, the transfer pulse slope, and the temperature in imaging, it is insufficient to change the offset correction value based only on the imaging sensitivity.

In the digital camera disclosed in Japanese Patent Laid-Open No. 2002-27326, a plurality of charge transfers from the PD increase the influence of the incomplete transfer in comparison with a single charge transfer. For example, the charge remaining amount associated with two charge transfers is twice as large as that with the single charge transfer. As a result, the increased transfer number deteriorates the obtained image quality.

SUMMARY OF THE INVENTION

The present invention provides an image sensor and an imaging apparatus, which can restrain the image quality from degrading.

An image sensor according to one aspect of the present invention includes a unit pixel that includes a photoelectric converter configured to accumulate electric charges generated based on incident light, and an electric charger configured to store the electric charges transferred from the photoelectric converter, and a corrector configured to correct a signal corresponding to the electric charges output from the electric charger based on a transfer condition when the electric charges are transferred from the photoelectric converter to the electric charger.

DESCRIPTION OF THE EMBODIMENTS

Referring now to the accompanying drawings, a detailed description will be given of embodiments of the present invention. Corresponding elements will be designated by the same reference numerals, and a duplicate description thereof will be omitted.

FIG. 1is a block diagram of an imaging apparatus100according to this embodiment of the present invention. The imaging apparatus100includes an imaging lens101and a diaphragm (aperture stop)102in an imaging optical system. The light that has passed the imaging lens101and the diaphragm102forms an image near a focal position of the imaging lens101. The imaging lens101is illustrated as a single lens but may actually include a plurality of lenses. The imaging optical system may be fixed onto the imaging apparatus100but may be detached from and attached to it.

An image sensor103is a CMOS image sensor that converts an object image formed by the imaging lens101into an electric signal and a processable image signal in accordance with the light quantity. A signal processing circuit104performs a variety of corrections, such as a signal amplification and a reference level adjustment, and data sorting for an image signal output from the image sensor103. A timing generating circuit105outputs a drive timing signal to the image sensor103and the signal processing circuit104.

An overall controlling/calculating circuit106integrally drives and controls the entire imaging apparatus100that includes the image sensor103and the signal processing circuit104. The overall controlling/calculating circuit106performs predetermined image processing and a defect correction for the image signal output from the signal processing circuit104. A memory circuit107and a recording circuit108include a nonvolatile memory or a recording medium, such as a memory card, for storing the image signal etc. output from the overall controlling/calculating circuit106. An operating circuit109accepts a signal from an operating member provided to the imaging apparatus100and reflects a command by a user on the overall controlling/calculating circuit106. The display circuit110displays a captured image, a live-view image, and a variety of setup screens, etc.

FIG. 2is a block diagram of the image sensor103. The image sensor103has a plurality of unit pixels200arranged in a matrix shape.FIG. 2illustrates 4×4 or 16 unit pixels200, but millions of unit pixels200are actually arranged. The unit pixels200include color filters of R (red), G (green), and B (blue) in the Bayer array. A letter and numeral in the unit pixel200represent a color and address of the pixel. For example, G01represents a G (green) pixel at the 0throw and 1stthe column. The unit pixel200outputs an image signal to a column output line201. The column output line201is connected to a current source202.

A read circuit203has a plurality of column circuits211. The column circuits211performs an analog-to-digital conversion (AD conversion) for an image signal input from the column output line201. A slope voltage generating circuit204generates a slope voltage in which the potential varies at a constant variation rate over time used for the AD conversion in a column circuit211.

The signal AD-converted by the column circuit211is sequentially output to the outside of the image sensor103via a horizontal output line209and a digital output processing circuit210as the horizontal scanning circuit205is driven. A vertical scanning circuit206selects a row and drives the unit pixel200via a signal line207connected for each row of the unit pixel200. InFIG. 2, the signal line207is connected only to the unit pixel200at the 0throw but is actually wired to each row. A timing generator (TG)208sends a signal to and controls driving of a variety of circuits, such as the read circuit203, the slope voltage generating circuit204, the horizontal scanning circuit205, the vertical scanning circuit206, and the digital output processing circuit210.

First Embodiment

FIG. 3illustrates an illustrative circuit structure of the unit pixels200in the image sensor103. A photodiode (photoelectric converter or “PD” hereinafter)301generates the electric charges based on incident light, and accumulates the generated electric charges. According to this embodiment, the PD301generates the electric charges in response to the object image formed by the imaging lens101and accumulates the generated electric charges. The electric charges accumulated by the PD301are transferred to a floating diffusion part (“FD” hereinafter)304as the electric charger via a transfer MOS transistor (“transfer switch” hereinafter)302. When a selection switch306turns on, a voltage signal (pixel signal) representing the voltage corresponding to the electric charges transferred to the FD304is output to the column output line201via an amplification MOS transistor (“SF” hereinafter)305forming a source follower amplifier. The selection switch306is controlled every row in the unit pixel200, and the pixel signals at the selected row are collectively output to the column output line201for each column. The reset MOS transistor (“reset switch” hereinafter)303resets the potential in the FD304and the potential in the PD301via the transfer switch302to VDD.

The electric charges transferred to the FD304are stored by the FD304unless it is reset by the reset switch303. When the electric charges accumulated by the PD301are transferred to the FD304that has already stored the electric charges, the electric charges transferred to the PD301are superimposed on or added to the electric charges that have already stored by the FD304.

The transfer switch302, the reset switch303, and the selection switch306are controlled by control signals PTX, PRES, and PSEL via the signal line207connected to the vertical scanning circuit206.

Referring now toFIG. 4, a description will be given of the column circuit211that constitutes the read circuit203.FIG. 4illustrates an illustrative stmcture of the column circuit211.

An amplifier401amplifies the pixel signal input from the column output line201. A capacitor403is used to store the signal voltage. Writing in the capacitor403is controlled when a control signal PSH turns on and off a switch402.

A slope voltage (Vslope) as a reference voltage supplied from the slope voltage generating circuit204is input to one input terminal in a comparator404. An output of the amplifier401written in the capacitor403is input to the other input terminal in the comparator404. The comparator404compares the output of the amplifier401and the slope voltage Vslope with each other, and outputs one of two values (binary), i.e., a IOW level and a high level, depending on the comparison result. More specifically, the comparator404outputs the low level when the slope voltage Vslope is smaller than the output of the amplifier401, and outputs the high level when the slope voltage Vslope is larger than the output of the amplifier401. When the slope voltage Vslope starts transferring, a clock (“CLK” hereinafter) starts. A counter405counts up the count value in response to the CLK when an output COMP of the comparator404has a high level, and stops an operation as soon as the output COMP of the comparator404inverts to the low level (as soon as the comparison result inverts).

An N memory406holds a digital signal made by AD-converting the reset level signal (“N signal” hereinafter) of the FD304. An S memory407holds a digital signal made by AD-converting the signal (“S signal” hereinafter) in which the signal of PD301is superimposed on the N signal of the FD304.

The N signal and the S signal are output to the digital output processing circuit210via horizontal output lines40land409by the control signal from the horizontal scanning circuit205. The digital output processing circuit210outputs a differential signal (light component) in which the N signal (the reset noise component in the FD304) that causes noises is removed from the S signal.

A description will now be given of the charge read operation from the unit pixel200for one row in the image sensor103. The image sensor103according to this embodiment has a single transfer mode for reading the signal after the electric charges are transferred from the PD301to the FD304once, and a multiple transfers mode for reading the signal after the electric charges are transferred a plurality of times.

FIG. 5is a timing chart of the illustrative charge read operation in the single transfer mode. The timing of each control signal, the slope voltage Vslope, CLK, and the horizontal scanning signal are schematically illustrated. The voltage V1in the vertical output line output from the amplifier401and the output COMP from the comparator404are also illustrated at each timing.

At time t500, prior to the reading of the signal from the PD301, the control signal PRES for the reset switch303is set to a high level. Thereby, a gate of the SF305is reset by the rest power voltage.

At time t501, the control signal PSEL for the selection switch306is set to a high level, and the SF305is activated.

At time t502, the control signal PRES is set to a low level, and the FD304is released from being reset. The voltage signal output from the FD304is read as the N signal to the column output line201and input to the column circuit211.

At time t503and time t504, the control signal PSH is sequentially set to a high level and a low level so as to turn on and off the switch402. Thereby, the N signal that is gain-amplified by the amplifier401is stored by the capacitor403. The signal value of the N signal stored by the capacitor403is input to the one input terminal of the comparator404.

From time t505to time t507, the slope voltage generating circuit204decreases the slope voltage Vslope from an initial value over time. At time t505, when the slope voltage Vslope starts transferring, CLK is supplied to the counter405. The count value in the counter405increases in accordance with the number of CLKs. At time t506, when the slope voltage Vslope input to the comparator404has the same value as the signal value of the N signal, the output COMP of the comparator404has a low level and the counter405stops operating. The count value when the counter405stops operating, the N signal has an AD converted value and is stored in the N memory406.

At time t507and time t508, the control signal PTX is sequentially set to a high level and a low level so as to transfer the electric charges accumulated in the PD301to the FD304. The voltage signal output from the FD304that changes according to a charge amount is read out as the S signal to the column output line201and input to the column circuit211.

At time t509and time t510, the control signal PSH is sequentially set to a high level and a low level so as to turn on and off the switch402. Thereby, the capacitor403stores the S signal gain-amplified by the amplifier401. The signal value of the S signal stored in the capacitor403is input to one input terminal in the comparator404.

From time t511to time t513, the slope voltage generating circuit204decreases the slope voltage Vslope from the initial value over time. At time t511, when the slope voltage Vslope starts transferring, CLK is supplied to the counter405. The counter value of the counter405increases in accordance with the number of CLKs. At time t512, when the slope voltage Vslope input to the comparator404has the same value as the signal value of the S signal, the output COMP of the comparator404has a low level and the counter405stops operating. The counter value when the counter405stops operating is the AD-converted value of the S signal and stored in the S memory407.

Following time t513, the horizontal scanning circuit205sequentially operates the column circuit211and the signals stored in the N memory406and the S memory407are output to the digital output processing circuit210via the horizontal output lines408and409. The digital output processing circuit210outputs the calculated differential signal to the outside of the image sensor103after calculating the differential signal by subtracting the N signal from the S signal.

FIG. 6is a timing chart of an illustrative charge read operation in the multiple transfers mode. The operation from time t600to time t608is similar to that from time t500to t508inFIG. 5, and a description thereof will be omitted.

At time t609and time t610, the control signal PTX is again sequentially set to a high level and a low level so as to transfer the electric charges accumulated in PD301to the FD304from time t608to time t610. The control signal PRES is maintained to be a low level in the first charge transfer from time t607to time t608and the second charge transfer from time t609to time t610and no resets are performed. Hence, the second transferred electric charges are superimposed on the electric charges first transferred and stored in the FD304. The voltage signal output from the FD304that changes with the charge amount is read as the S signal to the column output line201and input to the column circuit211.

At time t611and rime612, the control signal PSH is sequentially set to a high level and a low level so as to turn on and off the switch402. Thereby, the S signal gain-amplified by the amplifier401is stored in the capacitor403. The signal value of the S signal stored in the capacitor403is input to the one input terminal in the comparator404.

The operation from time t613to time t615is similar to that from time t511to time t513inFIG. 5and the AD-converted value of the S signal is stored in the S memory407.

The charge read operation in the multiple transfers mode according to this embodiment reads the S signal only after the second charge transfer but may read it after the first charge transfer. Since the multiple transfers and read operation are repeated for each row, the one-frame read time becomes long. The charge accumulating time to the PD301between the first transfer and the second transfer cannot be longer. Hence, the image sensor103may include a read circuit for each pixel rather than a read circuit for each column described inFIG. 2. After the electric charges are transferred, the next charge transfer may be performed at the read time.

FIG. 7schematically illustrates a driving operation example in the multiple transfers. The abscissa axis denotes time, and the ordinate axis denotes a row position in the image sensor103.

As the image capture starts, the vertical scanning circuit206sequentially sends the control signals PRES and PTX to all rows and performs pixel reset operation. After the reset operation, the accumulation operation starts. After the first accumulation operation (after the accumulation time T1passes), the control of the control signal PTX provides the first charge transfer from PD301to FD304. Moreover, the second charge transfer and the S signal read operation are performed after the second accumulation operation (after the accumulation time T2passes).

However, this driving operation cannot read the N signal before the S signal is read. Accordingly, the N signal data is previously stored so as to remove noises and a difference between the obtained S signal and the stored N signal may be calculated. In this driving operation, it is a long time for the FD304to store the electric charges and thus the FD304may be shielded from light.

As illustrated inFIG. 7, the first charge transfer is previously executed and the second charge transfer and the S signal read operation are executed. Thereby, the multiple transfers can be executed without influencing the one-frame ead time. This embodiment describes two transfers but may increase the number of transfers by repeating the similar operation.

The multiple transfers are very effective to a large exposure amount in a pixel structure in which the PD301has a small area and the FD304has a large capacitance. Even when the generated charge amount reaches the storable charge amount in the PD301, the PD301can transfer the accumulated charges to the FD304and again accumulate the electric charges so as to expand the detectable exposure amount (dynamic range).

As described above, the multiple transfers are effective in expanding the dynamic range. On the other hand, the charge transfer from the PD301to the FD304has an incomplete transfer, and the influence increases as the transfer number increases.

FIG. 8Ais a graph of an illustrative output characteristic to the exposure amount for each transfer number. The abscissa axis denotes an exposure amount, and the ordinate axis denotes an output value. As illustrated by a straight line, it is ideal that the output line is proportional to the exposure amount. However, actually, the output value is smaller than the ideal value under the condition having a small exposure amount due to the influence of the electric charge return caused by the incomplete transfer. This influence increases as the transfer number increases. The output characteristic deterioration to the exposure amount can be corrected to the ideal line by the corrective processing. For example, the corrected output value y (=αx+β) may be calculated for the acquired output value x by using a correction coefficient (a gain value α used for the gain correction and an offset value β used for the offset correction). The gain value α and the offset value β are coefficients arbitrarily set based on the characteristic of the image sensor.

The digital output processing circuit210according to the present invention changes the correction amount to the acquired output value in accordance with the transfer number by considering the output characteristic that changes according to the transfer number. In this embodiment, the digital output processing circuit210changes the correction coefficient in accordance with the transfer number. More specifically, the digital output processing circuit210corrects the offset β so that the offset β for two transfers is larger than that for a single transfer.FIG. 8Bis a graph of the corrected output value to the acquired output value. In order to change the correction coefficient in accordance with the transfer number, the corrected output value is different according to the transfer number even when the output value is the same. This correction can acquire the output value to the exposure amount close to the ideal value illustrated inFIG. 8A.

This embodiment instructs the digital output processing circuit210to provide this correction but may use the signal processing circuit104in the imaging apparatus100for the corrector.

The incomplete transfer characteristic also depends on the layout in the image sensor103, and is different according to areas on the same imaging plane of the image sensor103. Accordingly, the correction coefficient may be variable in accordance with areas on the imaging plane. For example, the correction coefficient is previously stored for each of the transfer number and area and may be changed in accordance with the driving condition of the read signal and the pixel address.

Since the transfer characteristic changes according to the temperature in imaging, the voltage in a transfer, the transfer time, and the transfer pulse slope, the correction coefficient may be changed according to the above condition. In other words, even in the single transfer mode, the correction coefficient may be changed according to the temperature in imaging, the voltage in the transfer, and the transfer pulse slope. Since the influence of the incomplete transfer depends on the exposure amount as illustrated inFIGS. 8A and 8B, the operation may be actively performed for the imaging condition in a scene with a high ISO speed and a small exposure amount.

As described above, a high-quality image can be obtained by changing the correction coefficient for the obtained signal in accordance with the transfer condition such as a charge transfer number from the PD301to the FD304as the electric charger.

Second Embodiment

The imaging apparatus according to this embodiment has a similar structure as that of the imaging apparatus100according to the first embodiment. This embodiment is different from the first embodiment in pixel structure. A unit pixel900according to this embodiment includes a pixel memory (memory part) as an electric charger between the photodiode and the floating diffusion part. The pixel memory enables the global shutter driving and smooth multiple transfers.

FIG. 9illustrates one illustrative circuit configuration of the unit pixel900. A photodiode (photoelectric converter, “PD” hereinafter)901receives an object image formed by the imaging lens101, generates the electric charges, and accumulates the generated electric charges. A reset switch902resets the PD901. The electric charges accumulated by the PD901are transferred to a pixel memory904as the electric charger via a transfer switch903. The electric charges stored in the pixel memory904are transferred to a floating diffusion part (“FD” hereinafter)906via a transfer switch905. When a selection switch909turns on, the voltage signal (pixel signal) representing the voltage corresponding to the electric charges transferred to the FD906is output to the column output line201via an SF908. The selection switch909is controlled in a row unit of the unit pixel900, and the pixel signals at the selected row are simultaneously output to the column output line201of each column. A reset MOS transistor (“reset switch” hereinafter)908resets the potential of the FD906and the potential of the pixel memory904via the transfer switch905to VDD. When the transfer switch903simultaneously turns on, the electric charges of the PD901can be reset, but when the reset switch902is turned on, the electric charges of the PD901can be reset while the pixel memory904stores the electric charges.

The transfer switch905, the reset switch907, and the selection switch909are controlled by the control signals PTX, PRES, and PSEL via the signal line207connected to the vertical scanning circuit206. The reset switch902and the transfer switch903are controlled by the control signals PRES1and PTX1, respectively.

FIG. 10schematically one illustrative driving operation of the multiple transfers in the image sensor103according to this embodiment. The abscissa axis denotes time, and the ordinate axis denotes the row position in the image sensor103.

At time t1000, the vertical scanning circuit206sends the control signals PRES1and PTX1to all rows when the image capture starts, and the pixels are reset. The vertical scanning circuit206simultaneously sends the control signals PRES and PTX to all rows to reset the image memory904and the FD906.

At time t1001, the first accumulation operation starts for all rows simultaneously.

After the first accumulation operation (after the accumulation time T1passes), the control by the control signal PTX1from the time t1002to time t1003performs the first charge transfer to all rows simultaneously from the PD901to the pixel memory904.

At time t1003, the second accumulation operation starts for all rows simultaneously.

After the second accumulation operation (after the accumulation time T2passes), the control by the control signal PTX1from the time t1004to time t1005performs the second charge transfer.

After time t1005, the read operation is sequentially performed. The electric charge stored in the pixel memory904can be read in accordance with the timing chart inFIG. 5. This embodiment transfers the electric charges from the pixel memory904to the FD906rather than the charge transfer from the PD301to the FD304.

This embodiment describes two transfers but may perform reading after the first charge transfer in the single transfer mode or may increase the transfer number.

The unit pixel900according to this embodiment includes the pixel memory904and performs the global shutter driving that provides simultaneous accumulations for all rows and sequential reading. This embodiment stores the electric charges in the pixel memory904and then reads them from the FD906. Thereby, prior to reading the S signal, the N signal of the FD906can be read out. The noises can be accurately removed and a high-quality image can be acquired.

The structure of this embodiment suffers from the incomplete transfer in the charge transfer from the PD901to the pixel memory904, and the influence increases as the transfer number increases. Hence, this embodiment executes the correction processing described with reference toFIGS. 8A to 8B. The output value can be corrected suitable for each transfer characteristic by changing the correction coefficient in accordance with the transfer number from the PD901to the pixel memory904, and a high-quality image can be acquired.

Since the transfer characteristic changes according to the voltage in the transfer and the transfer pulse slope in this embodiment, the correction coefficient may be changed according to the above condition.

As described above, the high-quality image can be obtained by changing the correction coefficient to the signal obtained according to the transfer condition, such as the electric charge transfer number from the PD901to the pixel memory904as the electric charger.

FIG. 11illustrates an illustrative circuit configuration of a unit pixel1100in the image sensor103according to a variation of the second embodiment. The unit pixel1100includes two pixel memories for one PD.

A photodiode (photoelectric converters, “PD” hereinafter)1101receives an object image formed by the imaging lens101, generates the electric charges, and accumulates the generated electric charges. A reset switch1102resets the PD1101. The electric charges accumulated in the PD1101are transferred to pixel memories1104aand1104bas electric chargers via transfer switches1103aand1103b. The unit pixel1100includes a transfer switch1105a, an FD1106a, a reset switch1107a, an SF1108a, and a selection switch1109acorresponding to the pixel memory1104a. The voltage signal representing the voltage corresponding to the electric charges transferred to the FD1106aare output to the column output line201a. The unit pixel1100includes a transfer switch1105b, an FD1106b, a reset switch1107b, an SF1108b, and a selection switch1109bcorresponding to the pixel memory1104b. The voltage signal representing the voltage corresponding to the electric charges transferred to the FD1106bare output to the column output line201b.

The control signal PTX1for controlling the transfer switches1105aand1105bcan determine which of the pixel memories1104-1and1104-2the electric charges are transferred to. The control signals PRES, PSEL, and PTX also control reading of the electric charges.

The unit pixel1100that includes two pixel memories for one PD provides a variety of global shutter drives to the image sensor103.

FIG. 12is a schematic view of an illustrative charge accumulating operation of the PD1101. After the electric charge accumulating operation starts, the PD1101repeats a short accumulation and a long accumulation. The electric charges accumulated in the short accumulation are transferred to one pixel memory, such as the pixel memory1104a, and sequentially read out. The electric charges accumulated in the long accumulation are transferred to the other pixel memory, such as the pixel memory1104b. In this case, the transferred electric charges may be read out after the single transfer or multiple transfers. The example inFIG. 12provides an image corresponding to the accumulation time T1+T2by reading the electric charges after the two transfers. The above operation enables the images of both the short accumulation and the long accumulation to be acquired.

The structure according to this embodiment provides a high-quality image in accordance with the transfer condition by the correction processing described with reference toFIGS. 8A and 8Bin the first embodiment. The correction coefficient may be changed for each transfer switch in addition to the transfer number.

As described above, the high-quality image can be obtained by changing the correction coefficient for the signal obtained according to the transfer condition of the electric charge transfer from the PD901to the pixel memories1104aand1104bas the electric chargers.

This application claims the benefit of Japanese Patent Application No. 2017-142106, filed on Jul. 21, 2017, which is hereby incorporated by reference herein in its entirety.