Polysilicon structure including protective layer

A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers.

BACKGROUND

In some applications, a logic circuit, static random access memory (SRAM), and one-time-programmable (OTP) memory of an integrated circuit are fabricated on the same substrate. In some applications, when performing a self-aligned silicide (salicide) process to form electrical contacts on the logic or SRAM part, the OTP part of the integrated circuit is protected by a protective layer. The performance of the logic circuit, the SRAM, and the OTP memory is affected by the thickness of the protective layer in the OTP part and residue of materials used to form the protective layer in the SRAM part.

DETAILED DESCRIPTION

By forming a layer of protective material that is sufficiently thick and yet conformal to a contour of a polysilicon structure and corresponding spacers of an integrated circuit, a process window of a subsequent removal process is enlarged compared to a non-conformal layer of protective material. As a result, the integrated circuit has a better silicide formation in the logic or SRAM part and better leakage prevention in the OTP part. In some embodiments, the disclosed embodiments are suitable to be used in a Bipolar-CMOS-DMOS (BCD) process. Bipolar stands for bipolar junction transistors, CMOS stands for complementary metal-oxide-semiconductor transistors, and DMOS stands for double-diffused metal-oxide-semiconductor transistors.

FIG. 1is a cross-sectional view of an integrated circuit100in accordance with some embodiments. In some embodiments, integrated circuit100depicted inFIG. 1is an intermediate product, which will be further processed by one or more manufacturing processes in order to form a functional integrated circuit. Other active electrical components and passive electrical components of the integrated circuit100are not shown inFIG. 1.

Integrated circuit100has a substrate110, a first polysilicon structure122, a second polysilicon structure124, a first set of spacers132, a second set of spacers134, and a protective layer142.

In some embodiments, substrate110includes: an elementary semiconductor such as silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In at least one embodiment, substrate110is an alloy semiconductor substrate having a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. In another embodiment, the alloy SiGe is formed over a silicon substrate. In yet another embodiment, a SiGe substrate is strained. In some further embodiments, substrate110is a semiconductor on insulator. In some examples, substrate110includes an epitaxial layer or a buried layer. In other examples, substrate110includes a multilayer compound semiconductor structure.

In some embodiments, substrate110generally exhibits a conductive characteristic similar to that of an intrinsic semiconductor material or a semiconductor material having a predetermined doping type. In some embodiments, the predetermined doping type is a P-type doping.

Substrate110has a first portion112and a second portion114. In some embodiments, two or more of a logic circuit, a static random access memory (SRAM), or a one-time-programmable (OTP) memory are fabricated on substrate110, where the OTP memory is formed on first portion112of substrate110, and the logic circuit and/or the SRAM are formed on second portion114of substrate110.FIG. 5includes an integrated circuit500including an SRAM520on second portion114of substrate110; and an OTP memory510on first portion112of substrate110. In some embodiments, the logic circuits, SRAM, and OTP memory are fabricated using a bipolar-CMOS-DMOS (BCD) process. In other words, in some embodiments, at least one bipolar junction transistor (BJT) device, at least one complementary metal-oxide-semiconductor (CMOS) device, and at least one double-diffused metal-oxide-semiconductor (DMOS) device are formed on substrate110.

First polysilicon structure122is over first portion112of substrate110. First set of spacers132includes two spacers on opposite sidewalls of first polysilicon structure122. Spacers132are L-shaped spacers. In some embodiments, spacers132have a shape other than an L-shape. In some embodiments, spacers132have a material including silicon nitride. In some embodiments, spacers132have a multi-layer structure. In some embodiments, integrated circuit100has a one-time-programmable (OTP) device that includes first polysilicon structure122and spacers132. In some embodiments, a gate dielectric (not shown) is formed between polysilicon structure122and substrate110. In some embodiments, one or more layers of other materials are formed between polysilicon structure122and substrate110.

Second polysilicon structure124is over second portion114of substrate110. Second set of spacers134includes two spacers on opposite sidewalls of second polysilicon structure124. Spacers134are L-shaped spacers. In some embodiments, spacers134have a shape other than an L-shape. In some embodiments, spacers134have a material including silicon nitride. In some embodiments, spacers134have a multi-layer structure. In some embodiments, integrated circuit100has a logic circuit or an SRAM that includes second polysilicon structure124and spacers134. In some embodiments, a gate dielectric (not shown) is formed between polysilicon structure124and substrate110. In some embodiments, one or more layers of other materials are formed between polysilicon structure124and substrate110.

In some embodiments, first and second polysilicon structure122and124are concurrently formed and include similar materials. In some embodiments, first and second set of spacers132and134are concurrently formed and include similar configuration and materials.

Protective layer142covers first portion112of substrate110, first polysilicon structure122, and first set of spacers132. Protective layer142is free from covering second portion114of substrate110, second polysilicon structure124, and second set of spacers134. A thickness of protective layer142is measureable as a distance between an upper surface142aand a lower surface142bof protective layer142along a normal direction of the lower surface142bof protective layer142. Protective layer142having a thickness H1over first polysilicon structure122, and the thickness H1is equal to or greater than 500 Å. In some embodiments, thickness H1represents the maximum thickness of protective layer142directly over first polysilicon structure122. Protective layer142having a thickness H2over spacers132, and the thickness H2is equal to or less than 110% of the first thickness H1. In some embodiments, thickness H2represents the maximum thickness of protective layer142directly over spacers132. In some embodiments, the maximum thickness of protective layer142over spacers132occurs at about a corner portion132aof the spacers132.

Protective layer142thus provides sufficient protection to first polysilicon structure122while second polysilicon structure124is being processed by a silicide process. Also, the difference between thickness H2and thickness H1is small enough (equal to or less than 10% of thickness H1) that eases a requirement for the processing window for a subsequent protective layer removal process.

FIG. 2is a flow chart of a method200of fabricating an integrated circuit100in accordance with some embodiments.FIGS. 3A to 3Care cross-sectional views of integrated circuit100at various manufacturing stages in accordance with some embodiments. Components inFIGS. 2 and 3A to 3Cthat are the same or similar to those inFIG. 1are given the same reference numbers, and detailed description thereof is omitted. It is understood that additional operations may be performed before, during, and/or after the method200depicted inFIG. 2, and that some other processes may only be briefly described herein.

As depicted inFIG. 2andFIG. 1, the process200begins at operation210, where first polysilicon structure122is formed over first portion112of substrate110and second polysilicon structure124is formed over second portion114of substrate110. In some embodiments, operation210includes forming a layer of polysilicon material over substrate110and then patterning the layer of polysilicon material into first and second polysilicon structures122and124by performing a lithographic process followed by a removal process.

The process200proceeds to operation220, where first set of spacers132and second set of spacers134are formed on sidewalls of polysilicon structure122and124. In some embodiments, operation220includes forming a layer of spacer material over first and second polysilicon structures122and124and substrate110and then patterning the layer of spacer material into first and second sets of spacers132and134by performing a removal process. In some embodiments, the layer of spacer material includes silicon nitride. In some embodiments, the removal process includes an anisotropic etch process.

As depicted inFIG. 2andFIG. 1, the process200proceeds to operation230, where one or more other electrical components are also formed on substrate110. In some embodiments, integrated circuit100is fabricated by a BCD process, and operation230, in conjunction with operations210and/or220, are usable to form at least one bipolar junction transistor (BJT), at least one complementary metal-oxide-semiconductor (CMOS) device, and at least one double-diffused metal-oxide-semiconductor (DMOS) device on substrate110. In some embodiments, operation230is performed before, after, or concurrently with operations210and220. In some embodiments, operation230is omitted.

The process200proceeds to operation240, where a layer of protective material is formed over substrate110. In some embodiments, the layer of protective material includes silicon oxide, and operation240includes performing an ozone-tetraethyl orthosilicate (TEOS) high aspect ratio process (HARP) or an atomic layer deposition (ALD) process. In some embodiments, the ozone-TEOS HARP process or the ALD process is suable to form a layer of protective material that is conformal to a contour of polysilicon structure122and124and corresponding spacers132and134of an integrated circuit100, even when the thickness of the layer of protective material over polysilicon structure122and124is equal to or greater than 500 Å.

FIG. 3Bis a cross-sectional view of integrated circuit100after operation240. A layer of protective material140covers the first and second polysilicon structures122and132and first and second sets of spacers132and134.

The layer of protective material140has a thickness H1over first polysilicon structure122, and the thickness H1is equal to or greater than 500 Å. In some embodiments, thickness H1represents the maximum thickness of the layer of protective material140over first polysilicon structure122. The layer of protective material140having a thickness H2over spacers132, and the thickness H2is equal to or less than 110% of the first thickness H1. In some embodiments, thickness H2represents the maximum thickness of the layer of protective material140over spacers132.

Also, the layer of protective material140has a maximum thickness H3over second polysilicon structure124, and the maximum thickness H3is equal to or greater than 500 Å. The layer of protective material140having a maximum thickness H4over spacers134, and the thickness H4is equal to or less than 110% of the thickness H3. In some embodiments, the difference between thickness H4and thickness H3is small enough (e.g., equal to or less than 10% of thickness H3) that eases a requirement for the processing window for one or more subsequent protective layer removal processes.

As depicted inFIG. 2andFIG. 1, the process200proceeds to operation250, where a patterned photo resist layer is formed over a portion of the layer of protective material140and the first portion of substrate112.

FIG. 3Cis a cross-sectional view of integrated circuit100after operation250. A patterned photo resist layer310is formed to cover a first portion142of the layer of protective material140that covers the first portion112of the substrate110and to expose a second portion144of the layer of protective material140that covers the second portion114of the substrate110.

As depicted inFIG. 2,FIG. 1, andFIG. 3C, the process200proceeds to operation260, where the second portion144of the layer of protective material140is removed. In some embodiments, operation260includes performing a dry etch process or a wet etch process, or a combination thereof. In some embodiments, operation260includes performing a dry etch process and then performing a wet etch process after the performing the dry etch process. After operation260, patterned photo resist layer310is removed by an ashing process.

Because the layer of protective material140is conformally formed along a contour of polysilicon structure124and spacers134, the process window for the dry etch process is sufficient large for yield control, and the process window for the wet etch process is sufficient large for protective layer peeling prevention.

As depicted inFIG. 2, the process200proceeds to operation270, where a self-aligned silicide (salicide) process is performed on the second portion114of the substrate110while the first portion112of the substrate110is covered by the first portion142of the layer of protective material. The process200then proceeds to operation280, where a logic circuit or an SRAM cell is formed based on the second polysilicon structure124and spacers134, and an OTP device is formed based on first polysilicon structure122and spacers132. In some embodiments, operation280is omitted, and polysilicon structures122and124are used to form other types of electrical components.

FIG. 4is a cross-sectional view of an integrated circuit400that is fabricated by a process different from that depicted inFIG. 2in accordance with some embodiments. Components inFIG. 4that are the same or similar to those inFIG. 1are given the same reference numbers, and detailed description thereof is omitted.

Integrated circuit400includes a protective layer412over first polysilicon structure122, first set of spacers132, and first portion112of substrate110. Integrated circuit400further includes residue protective materials414near the corner portion134aof second set of spacers134of and extending to an upper surface of second portion114of substrate110.

Compared with integrated circuit100, a processing operation comparable to operation240for manufacturing integrated circuit400is performed by a Plasma-enhanced chemical vapor deposition (PECVD) process. The PECVD process causes accumulation of protective materials at corner portions132aand134a. As a result, when a thickness H5of protective layer412over first polysilicon structure122is equal to or greater than 500 Å, a thickness H6of protective layer412around corner portion132aof first set of spacers132is greater than 110% of thickness H5. In some embodiments, thickness H6of protective layer412is greater than 120% of thickness H5.

At a stage comparable toFIG. 3C, second polysilicon structure122of integrated circuit400is covered by a layer of protective material in a manner similar to protective layer412over first silicon structure122. The difference between thickness H6and thickness H5is too large (greater than 10% of thickness H5) that renders a requirement for the processing window for a subsequent protective layer removal process more stringent than that of operation260or technically infeasible. As a result, residue protective materials414near the corner portion134aof second set of spacers134are not fully removed.

In some embodiments, residue protective materials414hinder a subsequent salicidation process comparable to operation270. In some embodiments, in order to reduce or eliminate residue protective materials414, protective layer412becomes too thin to effectively protect polysilicon structure122from the subsequent salicidation process intended for polysilicon structure124and/or second portion of substrate114.FIG. 6is a cross-sectional view of integrated circuit400′ according to some embodiments. In comparison with integrated circuit400, integrated circuit400′ does not include residue protective materials414.

An aspect of this description relates to a manufacture. The manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers. In some embodiments, the two spacers are L-shaped spacers. In some embodiments, the manufacture further includes a static random access memory (SRAM) cell comprising the second polysilicon structure and the two spacers. In some embodiments, the manufacture further includes a one-time-programmable (OTP) device comprising the first polysilicon structure. In some embodiments, the protective layer comprises silicon oxide. In some embodiments, the manufacture further includes another two spacers on opposite sidewalls of the first polysilicon structure. In some embodiments, the protective layer has a second maximum thickness over the another two spacers, and the second maximum thickness is equal to or less than 110% of the first maximum thickness. In some embodiments, the manufacture further includes at least one bipolar junction transistor (BJT) device on the substrate; at least one complementary metal-oxide-semiconductor (CMOS) device on the substrate; and at least one double-diffused metal-oxide-semiconductor (DMOS) device on the substrate.

An aspect of this description relates to a semiconductor device. The semiconductor device includes a substrate and a first polysilicon structure over a first portion of the substrate. The semiconductor device further includes a first spacer on a sidewall of the first polysilicon structure, wherein the first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device further includes a second polysilicon structure over a second portion of the substrate. The semiconductor device further includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein a thickness of the protective layer over the concave corner region is at least 110% of a thickness of the protective layer over the first polysilicon structure, and the protective layer exposes the second polysilicon structure. In some embodiments, the protective layer partially covers the second spacer. In some embodiments, the thickness of the protective layer over the first polysilicon structure is at least 500 angstroms. In some embodiments, the thickness of the protective layer over the concave corner region is at least 120% of the thickness of the protective layer over the first polysilicon structure. In some embodiments, at least one of the first spacer or the second spacer is a multi-layer structure. In some embodiments, a material of the first spacer is a same material as the second spacer.

An aspect of this description relates to a semiconductor device. In some embodiments, a substrate and a first polysilicon structure over a first portion of the substrate. The semiconductor device further includes a first spacer on a sidewall of the first polysilicon structure. The semiconductor device further includes a second polysilicon structure over a second portion of the substrate. The semiconductor device further includes a second spacer on a sidewall of the second polysilicon structure wherein the second spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer at least partially exposes the upper portion of the second spacer. In some embodiments, a thickness of the protective layer over the concave corner region is at least 110% of a thickness of the protective layer over the first polysilicon structure. In some embodiments, a difference between a thickness of the protective layer over the concave corner region and a thickness of the protective layer over the first polysilicon structure is equal to or less than 10% of the thickness of the protective layer over the first polysilicon structure. In some embodiments, the semiconductor device further includes a static random access memory (SRAM) cell, wherein the second polysilicon structure is part of the SRAM cell. In some embodiments, the semiconductor device further includes a one-time-programmable (OTP) device, wherein the first polysilicon structure is part of the OTP device. In some embodiments, the protective layer exposes an entirety of the second spacer.