Clock generator

A clock generator has a ring oscillator which has odd-numbered inverters connected in series, wherein an output of the inverter at a final stage is inputted into the inverter at a first stage to generate and output a clock signal, a frequency divider which receives the clock signal outputted from the ring oscillator, and divides frequency thereof for output, and a heater which is on-off controlled based on the output of the frequency divider and heats the ring oscillator when turned on.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the Japanese Patent Application No. 2007-304711, filed on Nov. 26, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a clock generator.

It has been known that a clock signal or a data signal changing synchronously with the clock signal generates electromagnetic interference, hereinafter referred to as “EMI”. In recent years, the required frequency of a clock signal becomes higher and measures against EMI are in demand.

To suppress EMI noise, there has been proposed a spread spectrum clock generator (SSCG) which gives minute oscillations to the clock frequency relative to a clock signal resulting in noise and reduce the strength (amplitude) of a noise spectrum by means of a smoothing action with the oscillations.

However, the conventional SSCG uses a PLL circuit, which causes a function of SSCG to come into no action until the PLL circuit has stabilized and is unsuitable to a system which frequently switches turning on and off a power supply. There is also a problem of a cost increase due to use of a PLL circuit.

As a SSCG having no PLL circuit, there has been proposed an apparatus which gives oscillations to a reference frequency by inputting an input pulse (a clock signal of the reference frequency) into a delay circuit including a plurality of delay buffers connected in series and outputting an output of the delay buffer selected by switching as needed as an output pulse.

It has been known that what has a large effect in EMI noise reduction is the one that gives periodical waveform fluctuations to a reference clock, such as Hershey Kiss waveform. The apparatus described above has a reference frequency as an output pulse during a period except instantaneous switching period of a delay time (selected delay buffer) and therefore an EMI reduction effect is small.

Accordingly, there has been requested a clock generator which has a simple circuit configuration without PLL circuit and can generate a clock signal having a steadily oscillating frequency.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided a clock generator comprising:

a ring oscillator which has odd-numbered inverters connected in series, wherein an output of the inverter at a final stage is inputted into the inverter at a first stage to generate and output a clock signal;

a frequency divider which receives the clock signal outputted from the ring oscillator, and divides frequency thereof for output; and

a heater which is on-off controlled based on the output of the frequency divider and heats the ring oscillator when turned on.

According to one aspect of the present invention, there is provided a clock generator comprising:

a ring oscillator which has odd-numbered inverters connected in series, wherein an output of the inverter at a final stage is inputted into the inverter at a first stage to generate and output a clock signal;

a dummy circuit which is formed adjacent to the ring oscillator and changes heating value based on a frequency of a drive signal; and

a temperature control circuit which receives the clock signal outputted from the ring oscillator and generates and outputs the drive signal based on the clock signal.

DESCRIPTION OF THE EMBODIMENTS

Referring now to the accompanying drawings, description will be made on a clock generator according to embodiments of the present invention.

First Embodiment

FIG. 1is a schematic configurational view of a clock generator according to a first embodiment of the present invention. The clock generator includes a ring oscillator11, a frequency divider12, a NAND gate13and a heater14.

The ring oscillator11has inverters inv1to invN the quantity of which is N (N: Odd number). Outputs of the respective inverters are inputted into the next stage of inverter and an output of the final stage of inverter invN is inputted into the first stage of inverter inv1, and a ring configuration is formed as a whole.

An inverter chain having inverters the number of which is N becomes a logical NOT of an input as a whole. The inverters have a delay time, respectively, and at a predetermined delay time after an input into the first stage of inverter inv1, the final stage of inverter invN outputs a logical NOT of the first stage of input and the logical NOT is inputted into the first stage of inverter inv1again. By repeating this process, oscillation is made. If a delay time per one stage of inverter is taken as τ, an oscillation frequency f becomes f=1/(2×N×τ).

An output of the ring oscillator11is inputted into the frequency divider12. Of outputs of the frequency divider12, a first-most significant bit Qn and a second-most significant bit Qn-1are given to the NAND gate13. The heater14is on-off controlled based on an output value of the NAND gate13. For example, when an output value of the NAND gate13is 0, the heater14is turned on and, when an output value thereof is 1, the heater14is turned off.

The heater14heats the ring oscillator11. As illustrated inFIG. 2, there is the characteristic that the delay time of the inverters inv1to invn included in the ring oscillator11changes with temperature. The delay time of the respective inverters, if a delay time of +25° C. is 100%, changes within the range of 81% to 118% between −40° C. to +80° C. and therefore oscillation frequency as well changes at the rate.

Accordingly, the heater14turn on and, after heating, the delay time of the ring oscillator11increases and oscillation frequency lowers. On the contrary, the heater14turns off and the temperature of the ring oscillator11lowers, the oscillation frequency increases.

For example, if a change of −100 kHz to +100 kHz is given to a reference clock of 100 MHz, an EMI spectrum can be reduced significantly and therefore it is sufficient to give a temperature bias of approximately 0.7° C. to the ring oscillator11by performing heating with the heater14. A preferable period is such that a frequency change makes one vertical movement during 33 μs and therefore it is preferable that a temperature bias of approximately 0.7° C. is given at a period of 33 μs. Accordingly, preferably, the frequency divider12divides an output signal of the ring oscillator11into approximately 30 kHz.

FIG. 3is a timing chart of each of output of the frequency divider12, output value of the NAND gate13, turning-on/off of the heater14, temperature of the ring oscillator11and oscillation frequency (pulse waveform).

While the heater14is on, a pulse duration gradually becomes wider and oscillation frequency lowers. While the heater14is off, pulse duration gradually becomes narrower, and the oscillation frequency becomes higher.

Using the most-significant 2 bits Qn, Qn-1of outputs of the frequency divider12, on-off control of the heater14is performed and therefore on-period of the heater14is ¼. This is because it takes more time to perform cooling than heating the ring oscillator11. The on-period of the heater14can be determined by the characteristics of the heater14or the ring oscillator11. For example, using the most-significant 3 bits Qn, Qn-1, Qn-2of outputs of the frequency divider12, the on-period of the heater14can be reduced to ⅛.

The clock generator according to the present embodiment changes a temperature of the ring oscillator11by turning on and off the heater14to change oscillation frequency, thus generating a clock signal having steady oscillations in the frequency.

For the heater14, for example, a heater with polysilicon may be used.FIG. 4illustrates an example of a layout with CMOS semiconductor of a ring oscillator formed with a polysilicon heater. In addition,FIG. 4illustrates a part of the ring oscillator and the heater. By repeatedly using this layout, the ring oscillator and the heater are constructed.

A source region42and a drain region43of a P-channel FET (Field Effect Transistor) and a source region44and a drain region45of an N-channel FET are generated at a surface portion of a semiconductor substrate. A gate electrode41is formed, through a gate oxide film, on a semiconductor substrate between the source region42and the drain region43of the P-channel FET and between the source region44and the drain region45of the N-channel FET.

The source region42of the P-channel FET is connected with a power supply potential line VDD. The source region44of the N-channel FET is connected with a ground potential line VSS.

The gate electrode41is a polysilicon layer and a polysilicon heater46is processed according to the same process as the gate electrode41.

One end of the heater46is connected with the power supply potential line VDD and the other end thereof is connected with a heater control line47. The heater control line47is connected with an output terminal of the NAND gate13inFIG. 1. When a potential difference occurs between the power supply potential line VDD and the heater control line47, an electric current flows through the polysilicon heater46to generate heat. This allows heating of a transistor (an inverter constructing the ring oscillator) formed below the polysilicon heater46.

The polysilicon heater46can be structured to have a desired heating capacity by changing a length according to heating watt capacity thereof.

The polysilicon heater46is formed flush with the gate electrode41when viewed from the semiconductor substrate. Accordingly, a distance to a diffusion layer (source regions42,44, drain regions43,45) can be reduced, heat transfer can be quickened and heating period (heater on-period) can be shortened.

For the heater14, an aluminum wiring may be used in place of polysilicon.FIG. 5illustrates an example of a layout with CMOS semiconductor of a ring oscillator formed with an aluminum wiring heater. Components except an aluminum wiring heater51are the same as inFIG. 4and therefore the same reference numerals/characters are allocated and description thereof will not be repeated.

One end of the aluminum wiring heater51is connected with the power supply potential line VDD and the other end thereof is connected with a heater control line (not illustrated). However, inFIG. 5, no contact points are illustrated between the power supply potential line VDD, the heater control line and the aluminum wiring heater51. The aluminum wiring heater51is formed at a higher position than the polysilicon heater46illustrated inFIG. 4, when viewed from the semiconductor substrate. Accordingly, the aluminum wiring heater51can uniformly heat a transistor (source regions42,44and drain regions43,45) constructing the ring oscillator.

As described above, the clock generator according to the present embodiment can produce a clock signal having a large EMI noise reduction effect by turning on and off the heater to change the temperature of the ring oscillator and give steady oscillations to oscillation frequency. Use of the ring oscillator having odd-numbered inverters connected in series in place of a PLL circuit facilitates a circuit configuration, thus attaining cost reduction.

Second Embodiment

FIG. 6is a schematic configurational view of a clock generator according to a second embodiment of the present invention. The clock generator includes a ring oscillator61, a temperature control circuit62and a dummy circuit63. The ring oscillator61has a configuration with odd-numbered inverters connected in a chain form in the same way as the ring oscillator11according to the first embodiment. The temperature control circuit62receives an oscillation clock signal outputted from the ring oscillator61and outputs a drive signal to the dummy circuit63.

The dummy circuit63has inverters connected in series in the same way as the ring oscillator61. The inverters of the dummy circuit63and the inverters of the ring oscillator61are alternately formed on the semiconductor substrate.

As illustrated in the first embodiment, the ring oscillator61changes oscillation frequency by heating (temperature changes). The clock generator according to the embodiment controls heating of the ring oscillator61by arranging dummy circuits63to be skewered inside the ring oscillator61and controlling fluctuations in heat generated by the operation.

FIG. 7(a) illustrates an example of a layout with CMOS semiconductors of the ring oscillator and the dummy circuit. In addition,FIG. 7(a) illustrates a part of the ring oscillator and the dummy circuit. By repeatedly using this layout, the ring oscillator and the dummy circuit are constructed.

Source regions72a,72band drain regions73a,73bof a P-channel FET and source regions74a,74band drain regions75a,75bof an N-channel FET are formed on a surface portion of a semiconductor substrate.

A gate electrode71ais formed, through a gate oxide film, on a semiconductor substrate between the source region72aand the drain region73aof the P-channel FET and between a source region74aand a drain region75aof the N-channel FET.

A gate electrode71bis formed, through a gate oxide film, on the semiconductor substrate between the source region72band the drain region73bof the P-channel FET and between a source region74band a drain region75bof the N-channel FET.

The source regions72a,72bof the P-channel FET is connected with a power supply potential line VDD. In addition, the source regions74a,74bof the N-channel FET are connected with a ground potential line VSS.

An inverter including a PMOS transistor having the gate electrode71aand diffusion layers (source-drain region)72a,73aand an NMOS transistor having the gate electrode71aand the diffusion layers (source-drain region)74a,75ais an inverter included in the ring oscillator61.

An inverter including a PMOS transistor having the gate electrode71band diffusion layers (source-drain region)72b,73band an NMOS transistor having the gate electrode71band the diffusion layers (source-drain region)74b,75bis an inverter included in the dummy circuit63.

By repeatedly using such a layout, a configuration in which an inverter of the ring oscillator61and an inverter of a dummy circuit63are alternately formed for every two-stage can be implemented, as illustrated inFIG. 7(b).

The dummy circuit63operates on a drive signal outputted from the temperature control circuit62. The inverter of the dummy circuit63generates heat with the operation of the dummy circuit63, thus heating the inverter of the adjacent ring oscillator61by thermal diffusion. That is, the dummy circuit63serves as a heater.

FIG. 8illustrates a schematic configuration of the temperature control circuit62. The temperature control circuit62includes a frequency divider81, a 5/8 pulse generator82, a 6/8 pulse generator83and a multiplexer84.

The frequency divider81receives an oscillation clock signal outputted from a ring oscillator (not illustrated), performs frequency division and outputs most significant 7 bits Qn to Qn-6.FIG. 9illustrates timing charts of most significant 7 bits Qn to Qn-6. During a certain time T when Qn-3bit generates by one pulse, Qn-4bit generates by two pulses, Qn-5bit generates by four pulses and Qn-6bit generates by eight pulses.

The 5/8 pulse generator82receives Qn-3to Qn-6bits from a frequency divider81, and outputs a signal of generating five pulses during a certain time T.FIG. 10illustrates a schematic configurational view of 5/8 pulse generator82. Qn-5bit and Qn-4bit are given to an AND gate101. The output of the AND gate101and Qn-3bit are given to OR gate102.

The output of the OR gate102and Qn-6bit are given to an AND gate103. As illustrated inFIG. 11, a signal of generating five pulses during a certain time T is outputted from the AND gate103.

A 6/8 pulse generator83receives Qn-3bit, Qn-4bit and Qn-6bit from the frequency divider81and outputs a signal of generating six pulses during a certain time T.FIG. 12illustrates a schematic configurational view of 6/8 pulse generator83. Qn-3bit and Qn-4bit are given to the OR gate121.

The output of the OR gate121and Qn-6bit are given to the AND gate122. As illustrated inFIG. 13, a signal of generating six pulses during a certain time T is outputted from the AND gate122.

As illustrated inFIG. 8, Qn-5bit, an output of the 5/8 pulse generator82, an output of the 6/8 pulse generator83, Qn-6bit, an output of the 6/8 pulse generator83, an output of 5/8 pulse generator82and Qn-4bit are given to input terminals X0to X7of the multiplexer84, respectively.

The multiplexer84sequentially selects one of the input terminals X0to X7for each section of the time divided into 8 portions using Qn to Qn-2 bits outputted from the frequency divider81and outputs a signal given from the input terminal as a drive signal. Accordingly, the operating frequency of an output signal of the multiplexer84changes for each section of the time divided into 8 portions.

FIG. 14illustrates a frequency progress of an output signal of the multiplexer84. At a time (section) t1, a signal (Qn-5bit signal) given from the input terminal X0is outputted. Thereafter, signals from the input terminals X1at a time t2, X2at a time t3, X3at a time t4, X4at a time t5, X5at a time t6, X6at a time t7and X7at a time t8are outputted, respectively.

Specifically, if a frequency of an output signal at a time t8is taken as 2 m, frequencies of output signals at t1and t7, t2and t6, t3and t5, and t4are 4 m, 5 m, 6 m and 8 m, respectively.

Accordingly, as seen fromFIG. 14, the frequency of a signal outputted from the multiplexer84repeatedly increases and decreases, and during a period from an increase to a decrease and during a period from a decrease to an increase, a variation in the frequency becomes larger. Preferably, an increase or decrease in the frequency is made once per 33 μs in the same way as the first embodiment. Specifically, it is preferable that the frequency increases or decreases at a period of approximately 30 kHz.

The heating value of the dummy circuit63is proportional to the frequency of a signal (drive signal) outputted from the multiplexer84and therefore a variation in the heating value of the dummy circuit63is also as illustrated inFIG. 14. Accordingly, the temperature (and temperature-dependent oscillation frequency) of the ring oscillator61also repeatedly increases or decreases in the same way, and during a period from an increase to a decrease and during a period from a decrease to an increase, a variation becomes larger. Such a change in the frequency performs a behavior next to a so-called Hershey Kiss waveform, thus increasing an effect of EMI spectrum reduction.

As described above, the clock generator according to the embodiment is configured so that an inverter constructing a ring oscillator and an inverter constructing a dummy circuit are alternately formed to heat the ring oscillator by the heat generated by driving the dummy circuit and give oscillation to oscillation frequency, thus reducing EMI noise. In addition, by periodically changing the frequency of a drive signal of the dummy circuit, heating value is changed to generate a clock signal having steady oscillation.

In the present embodiment, the temperature control circuit62divides time into eight portions to change the frequency of a drive signal to be outputted between respective sections, but the time may be divided into 16 or more portions. In addition, as the drive signal to be outputted, a signal of generating two to eight pulses during a certain time T is selected, but the signal may be selected from signals generating 2 to 64 pulses. Thus, the heating value (ring oscillator temperature) of the dummy circuit can be further controlled with high accuracy.

In the foregoing embodiment, a portion which requires no wiring above the heater may be filled with aluminum. Aluminum, having high heat conductivity, enables highly efficient cooling when the heater is off. Accordingly, balancing between heating time and cooling time becomes better, thus further increasing EMI spectrum reduction.