Bottom electrode mask design for ultra-thin interlayer dielectric approach in MRAM device fabrication

A bottom electrode (BE) layout is disclosed that has four distinct sections repeated in a plurality of device blocks and is used to pattern a BE layer in a MRAM. A device section includes BE shapes and dummy BE shapes with essentially the same shape and size and covering a substantial portion of substrate. There is a via in a plurality of dummy BE shapes where each via will be aligned over a WL pad. A second bonding pad section comprises an opaque region having a plurality of vias. The remaining two sections relate to open field regions in the MRAM. The third section has a plurality of dummy BE shapes with a first area size. The fourth section has a plurality of dummy BE shapes with a second area size greater than the first area size to provide more complete BE coverage of an underlying etch stop ILD layer.

RELATED PATENT APPLICATION

This application is related to the following: Ser. No. 11/724,435, filing date Mar. 15, 2007; assigned to a common assignee and herein incorporated by reference in its entirety.

FIELD OF THE INVENTION

The invention relates to an improved bottom electrode mask layout to achieve more uniform interlayer dielectric (ILD) layer thickness and reduce ILD delamination during an MRAM device fabrication.

BACKGROUND OF THE INVENTION

Magnetic random access memory (MRAM) that incorporates a magnetic tunnel junction (MTJ) as a memory storage device is a strong candidate to provide a high density, fast (1-30 ns read/write speed), low power, and non-volatile solution for future memory applications. The architecture for MRAM devices is composed of an array of memory cells generally arranged in rows and columns. Each memory cell is comprised of a memory element (MTJ) that is in electrical communication with a transistor through an interconnect stack. The memory elements are programmed by a magnetic field created from pulse current carrying conductors such as copper lines. Typically, two arrays of current carrying conductors that may be called “word lines” and “bit lines” are arranged in a cross point matrix. Normally, the word lines are formed under the MTJs and are isolated from the memory elements by one or more layers such as an etch stop layer and an interdielectric (ILD) layer. The bit lines contact the top portion of the MTJs and are electrically connected to a conductive cap layer. Additionally, there is a bottom electrode (BE) that contacts the bottom of each MTJ and electrically connects the MTJ with an underlying transistor.

The MTJ consists of a stack of layers with a configuration in which two ferromagnetic layers are separated by a thin insulating layer such as AlOXthat is called a tunnel barrier layer. One of the ferromagnetic layers is a pinned layer in which the magnetization (magnetic moment) direction is more or less uniform along a preset direction and is fixed by exchange coupling with an adjacent anti-ferromagnetic (AFM) pinning layer. The second ferromagnetic layer is a free layer in which the magnetization direction can be changed by external magnetic fields. The magnetization direction of the free layer may change in response to external magnetic fields which can be generated by passing currents through a bit line and word line in a write operation. When the magnetization direction of the free layer is parallel to that of the pinned layer, there is a lower resistance for tunneling current across the insulating layer (tunnel barrier) than when the magnetization directions of the free and pinned layers are anti-parallel. The MTJ stores digital information (“0” and “1”) as a result of having one of two different magnetic states.

In a read operation, the information is read by sensing the magnetic state (resistance level) of the MTJ through a sensing current flowing through the MTJ, typically in a current perpendicular to plane (CPP) configuration. During a write operation, the information is written to the MTJ by changing the magnetic state to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents. Cells which are selectively written to are subject to magnetic fields from both a bit line and word line while adjacent cells (half-selected cells) are only exposed to a bit line or a word line field.

As the MTJ size from a top-down view shrinks relative to the easy axis and hard axis directions (x,y plane), and from a cross-sectional perspective is reduced in thickness (perpendicular to the x,y plane) in order to satisfy higher performance MRAM requirements, the interconnects within the MRAM structure also decrease in size to conform to electrical requirements and space restrictions for high density designs. There is also a greater demand on reliability of the MRAM device since reduced MTJ sizes usually lead to a greater chance of device failure at contact points between adjacent metal layers and tend to cause delamination of the one or more interlevel dielectric (ILD) layers that separate the bit line and word line during CMP processing. In particular, the ILD layer above the word line and below the MTJ tends to delaminate during CMP processes to planarize the MTJ and bit line (BIT).

In order to maximize word line and bit line writing efficiency in an MRAM device, one needs to minimize both the distance from the bit line (BIT) to the MTJ free layer and the distance from the word line (WL) to the MTJ free layer. In related patent application Ser. No. 11/724,435, a MTJ mask layout was described that enables a reduction in the BIT-MTJ distance. In state of the art MRAM designs, there are only BE and ILD layers separating the WL and MTJ. The BE thickness is normally thin so the best approach to minimize the WL-MTJ distance is to reduce the ILD thickness. However, there are some major obstacles in this approach. First, there is a lack of high etch selectivity between BE films and ILD films. Secondly, an over-etch non-uniformity across a substrate due to etch tool hardware limitations and an etch micro-loading effect between dense and isolated features prevents a smooth and thin ILD layer. Moreover, as an ILD layer becomes thinner, it is more susceptible to delamination during chemical mechanical polish (CMP) processes. In addition, as an ILD layer becomes thinner, the risk of etch chemical leakage through pinholes and attacking the WL increases. Therefore, an improved BE mask layout is required to enable thinner ILD layers without suffering from the aforementioned drawbacks.

A routine search of the prior art revealed the following reference. In U.S. Pat. No. 6,358,755, a dummy bottom electrode may be formed in addition to a bottom electrode in a memory cell where a metal plug and bottom electrode form an electrical connection between a ferroelectric capacitor and an integrated circuit transistor. However, the circuit does not include a MTJ as required for a MRAM device fabrication.

SUMMARY OF THE INVENTION

One objective of the present invention is to provide a BE pattern layout in a MRAM device that minimizes delamination of dielectric layers between the word line and MTJ especially during CMP processing of various dielectric layers.

A second objective of the present invention is to provide a BE pattern layout according to the first objective that also provides improved etch thickness uniformity with fewer defects in the ILD layer contacting the word line thereby minimizing WL corrosion.

According to the present invention, these objectives are achieved by providing a substructure for a MRAM array that includes metal layers, insulating layers, and transistors arranged in a conventional configuration on a semiconductor substrate. In the exemplary embodiment, the substructure includes a word line metal layer comprised of a plurality of word line pads (WLP), word line contacts (WLC), and word lines (WL) which may be made of Cu and is coplanar with a WL ILD layer. A first etch stop layer (etch stop ILD) such as SiNx or the like is deposited on the WL ILD layer and WL metal layer. The etch stop ILD layer may be patterned and etched to form openings over certain portions of the underlying layers.

In one embodiment, a bottom electrode (BE) layer is deposited on the etch stop ILD layer. A BE mask with a unique design (pattern layout) is used to pattern the BE layer in a subsequent lithography step. The BE mask is comprised of a clear quartz substrate covered on one of its two large surfaces with an array of opaque features having the same shape and pattern as the intended array of BE elements in the final device. Clear regions between the opaque features will be transferred into the BE layer by a sequence involving photolithography and etching steps. A photoresist film is coated on the BE layer and is exposed by one or more wavelengths of light through the clear regions in the BE mask. Following exposure, the exposed regions of the photoresist film are removed by an aqueous base developer. Subsequently, a reactive ion etch (RIE) may be employed to transfer the openings in the photoresist film through underlying regions in the BE layer and stopping on the etch stop ILD layer. After the RIE step is complete, the remaining photoresist film is removed to afford a patterned BE layer having a plurality of BE elements.

A key feature of the present invention is the BE layout or array of opaque features on the BE mask that will be employed to form BE elements in a MRAM array on a substrate. The BE mask layout is comprised of opaque chrome features on a clear quartz substrate and includes at least four sections that are repeated a plurality of times across the BE mask. In a first section called the device area, there is a plurality of opaque features that will become active BE elements in the patterned BE layer of the MRAM cell. For example, there are 4 million active BE elements (and the same number of active MTJ elements) in each device block in a 4 Mb MRAM. A plurality of dummy BE shapes is positioned to cover a substantial portion of the clear quartz regions between active BE shapes in adjoining device blocks. In one embodiment, the shapes of the active BE and dummy BE features are essentially equivalent and the space between any two adjacent BE features in the BE array is maintained at a constant value across the device area. In one aspect, each clear space between adjacent BE features has a dimension “s” that is substantially less than the length of an adjoining side of a neighboring BE shape which is a rectangle in the exemplary embodiment. A certain number of the dummy BE shapes have a via opening formed therein to enable BIT line contact to WL pad in a subsequent MRAM fabrication step.

In a second section of the BE mask called the bond pads area, the opaque covering on the mask is essentially continuous except for a plurality of small via openings that enable a BIT line contact to bonding pad in a subsequent MRAM fabrication step.

There is a third BE mask section that is an open field area which is not overlaid on a WL metal pattern. This open field area is comprised of an array of opaque features such as rectangles each having a length “b” and a width “c” and separated by clear regions with a dimension “a” between opaque rectangles. Preferably, a>c but “a” may also be equal to or less than “c”. The opaque features will be transferred into the BE layer to become dummy BE elements to assist in achieving improved BE ILD uniformity in a subsequent CMP process. In one aspect, the density of the dummy BE elements is essentially the same as the density of the dummy MTJ elements to be formed in a MTJ patterning sequence during a later stage of MRAM fabrication.

A fourth section of the BE mask is an open field area that will be overlaid above a WL metal pattern. In one embodiment, this section has an array of opaque rectangles similar to the third section except the rectangles are larger and cover a majority of the clear substrate. The opaque shapes in the fourth section will be transformed by a photolithography and etching process into dummy BE elements in the MRAM device. Preferably, the clear opening between short sides of adjacent rectangles and between long sides of adjacent rectangles is essentially the same as dimension “s” in the first BE mask section. In one aspect, a column of opaque rectangles is overlaid on a first WL in the semiconductor substrate and a second column of opaque rectangles is overlaid on a second WL parallel to the first WL. During the MTJ patterning sequence, a dummy MTJ having a first area size may be formed above each dummy BE with a second area size where the second area size is substantially greater than the first area size.

The BE mask may be fabricated by a conventional method that involves patterning a continuous opaque film such as chrome on a clear quartz substrate.

After the BE ILD is deposited on the etch stop ILD to fill openings between BE elements, a second patterning and etch sequence is performed as described previously to simultaneously form dummy MTJ devices above a certain number of dummy BE elements and active MTJ elements above active BE elements. Thereafter, a MTJ ILD layer is deposited on the dummy MTJ arrays and active MTJ arrays and is followed by a CMP process that stops on the hard mask layer. Next, a second etch stop layer and a BIT ILD layer are sequentially deposited on the MTJ ILD and hard mask. A third patterning and etch sequence is employed to form trenches in the BIT ILD which stop on the second etch stop layer. Then another patterning and etch process is used to form vias in the aforementioned trenches that extend through the underlying MTJ ILD and etch stop ILD to uncover portions of the WL pad and WLC layer. The trenches and vias are filled with a metal such as Cu to form interconnects between the BIT line metal in the trenches and the WL pads and WLC. The final step in the process flow involves a third CMP step to planarize the BIL line and the BIT ILD layer. As a result of the improved BE layout, delamination of the etch stop ILD is minimized and improved planarization of the BE ILD is achieved because of the additional dummy BE features that enable more uniform etching across the wafer.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is a novel BE layout (mask) used to pattern a BE layer formed in a MRAM device. The present invention also encompasses a MRAM structure and a method for forming the same that minimizes delamination of interlevel dielectric (ILD) layers formed between a word line (WL) layer and a bit line (BIT) layer, improves ILD layer thickness uniformity, and reduces pinholes in an etch stop ILD layer that can lead to WL corrosion. Although the exemplary embodiment depicts a MRAM device with a 1T1MTJ architecture, the present invention may also apply to other magnetic memory devices known in the art that include a BE layer and an array of MTJ devices. Drawings are provided by way of example and are not intended to limit the scope of the invention. The MTJ devices may have a top spin valve, bottom spin valve, or multi-layer spin valve configuration as appreciated by those skilled in the art. Two layers are said to be coplanar when a top surface of each layer lies in the same plane.

Referring toFIG. 1a, the exemplary embodiment depicts a 1T1MTJ architecture wherein a bit line48a-48cis the top conductor line in each MRAM cell and a bottom electrode (BE)22ais a patterned conductor pad connected to an underlying selection transistor (not shown). Word line15is separated by ILD layers11,17from other conductive elements and is aligned below a BE22aand a MTJ23a. The cross-sectional view illustrates only one MRAM cell in a device area (block)9that includes 4 million cells in a 4 Mb MRAM and 16 million devices in a 16 Mb MRAM, for example. There are also open field regions (not shown) between device blocks that do not contain active devices.

A method of forming a MRAM structure similar to that depicted inFIG. 1awas previously disclosed by the inventors in U.S. Pat. No. 7,122,386 and is herein incorporated by reference in its entirety. In view of issues related to an etch stop ILD layer contacting the word line such as ILD peeling during subsequent CMP processes and corrosion in word line and word line pads caused by pinholes in the thin etch stop ILD layer, we were motivated to further improve the MRAM structure by modifying the BE layer pattern (layout) by adding dummy BE elements to provide additional coverage of etch stop ILD layer for increased protection and reliability. The improved MRAM structure shown inFIG. 1ahaving etch stop ILD layer17, WL15, and WLP14will be described in detail and then a description of the BE mask comprised of a novel BE layout that is employed to pattern the BE layer and form BE elements including active BE elements22aand dummy BE elements22d1,22d2will be provided in a later section.

Substructure10is comprised of metal layers, insulating layers, transistors, and other devices not shown in order to simplify the drawing. There is a first ILD layer11formed on the substructure10. In one embodiment, the first ILD layer11is made of fluorosilicate glass (FSG) and is disposed on a substructure10that has an exposed third metal level (M3) formed therein. There are vias (V3)12formed in the first ILD layer11that connect the M3 layer to overlying WL pads14a,14cand to word line contact (WLC)16. According to one embodiment, a WL ILD layer13is deposited on the first ILD layer11and vias12. The WL ILD layer13and subsequent ILD layers described herein may be comprised of silicon oxide or another insulator such as a low k dielectric material used in the art. Elements10-13are fabricated by standard processes that are not described herein. Likewise, a conventional patterning, etching, metal deposition, and planarization sequence may be employed to form WL pads (WLP)14a,14c, WL15, and WLC16in the ILD layer13. Typically, the word line metal is Cu and a CMP process is needed to make the WLP14a,14c, WL15, and WLC16coplanar with the WL ILD layer13.

Referring toFIG. 1b, a top-down view of the layout depicted inFIG. 1ais provided. Note that the cross-sectional view inFIG. 1amay be obtained along the plane8-8. In the exemplary embodiment, active device area (block)9has a rectangular shape. When all levels are removed above the WL metal layer, active device area9comprises a plurality of word lines15, and adjacent regions6and7include a plurality of WL pads14aand14c, respectively. InFIG. 1a, WL pad14ais formed in a bonding pad region6of the device where WL pad14ais connected to an overlying BIT line48afor probing the device to obtain electrical measurements. A second type of WL pad14cin region7becomes connected in the final device to an active BIT line48cin an open field area. As appreciated by those skilled in the art, other designs comprising a plurality of WL pads arranged around an active device area may be employed to replace the one depicted inFIG. 1b.

An ILD layer17that also serves as an etch stop layer and is preferably silicon nitride (SiNX) is deposited on the WL ILD layer13, WLP14a,14c, WL15, and WLC16by a chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. Alternatively, the ILD layer17may be silicon oxynitride or another etch stop material known to those skilled in the art. The ILD layer17is typically thin with a 100 to 300 Angstrom thickness. A standard photoresist patterning and etch sequence is used to form an opening19in ILD layer17to expose the WLC16in each MRAM cell.

In one embodiment, a BE layer is deposited on the ILD layer17and is patterned to form BE elements22aand dummy BE elements22d1,22d2prior to depositing a MTJ stack of layers and forming MTJ elements. Preferably, a sputter deposition system such as an Anelva 7100 system is used to deposit the BE layer. The present invention encompasses a variety of materials and configurations for the BE layer. In one aspect, the BE layer may be comprised of a plurality of layers including metals, metal alloys, and metal nitrides such as TaN. A photolithography process comprising a BE mask according to the present invention is preferably used to pattern the BE layer to form BE elements22aand dummy BE elements22d1,22d2. The BE patterning step involves coating a photoresist layer (not shown) on the BE layer and then patternwise exposing the photoresist layer through the BE layout on the BE mask. Regions of the photoresist layer that are exposed through clear regions in the BE mask are then developed away with an aqueous base solution. Thus, the BE layout on the BE mask is transferred into the photoresist film as a BE pattern. In the following step, a RIE process transfers the openings in the photoresist pattern through underlying regions in the BE layer and stops on ILD layer17. The remaining photoresist film is removed to leave a plurality of BE elements22aas well as a plurality of dummy BE elements22d1,22d2. A more detailed description of the BE elements22a,22d1,22d2will be provided in a later section.

Referring toFIG. 2, the patterned BE layer comprises a via opening70in dummy BE element22d1above WLP14a, openings71,72which separate BE element22afrom dummy BE elements22d1,22d2, and a via opening73in dummy BE element22d2above WLP14c. The dummy BE elements22d1,22d2are advantageously used to allow a more uniform RIE etch across the substrate during subsequent planarization of a BE ILD layer. It should be understood that there are a plurality of vias70,73and a plurality of openings71,72but only one of each is depicted in the cross-sectional view to simplify the drawing.

Referring toFIG. 3, a BE ILD layer20is deposited to fill the openings70-73and cover the BE elements22a,22d1,22d2. In one embodiment, a two step planarization process is used to achieve coplanarity of the BE ILD layer20and BE elements22a,22d1,22d2. First, a CMP step removes a substantial portion of the BE ILD layer above BE elements22a,22d1,22d2. Then a RIE removes the remaining BE ILD layer and stops on the top surfaces of BE elements22a,22d1,22d2. In an alternative embodiment, the CMP step is employed to perform the complete planarization process and the RIE step is omitted. The presence of BE dummy elements22d1,22d2fill a majority of open space between adjoining device blocks of BE elements22athereby enabling a more uniform BE ILD20thickness and also serve to cover ILD layer17in spaces between BE elements22ato prevent RIE or CMP processes from thinning or delaminating the ILD17in these regions. As a result, pinholes in the ILD layer17that could allow chemical etchants to attack underlying WLP14a,14cin prior art designs are greatly reduced because of the new BE layout. Previously, we have practiced a method with no dummy BE elements in the device area (FIG. 4a) which leads to non-uniform RIE etching of a BE ILD layer since large open areas containing no BE metal are etched at a faster rate than small spaces between adjacent BE elements.

In the next step of MRAM fabrication, a MTJ stack of layers and overlying hardmask are deposited on the BE ILD20and BE elements22a,22d1,22d2by a sputter deposition process. In one embodiment, the hard mask24is a Ta layer having a thickness of about 200 to 1500 Angstroms. Optionally, a hard mask spacer may be inserted between the uppermost MTJ layer and the hard mask24to assist with a subsequent etching process. The MTJ stack of layers and hardmask are patterned by a process similar to the BE patterning process except that a different mask comprising a unique MTJ layout such as the design disclosed in related patent application Ser. No. 11/724,435 is preferably used. An active MTJ element23awith overlying hardmask24is formed above a WL15in each MRAM cell. Dummy MTJ elements are typically included in the MTJ layout to assist in improving CMP uniformity but are not shown in this drawing. A MTJ ILD layer30is then deposited on the hard mask24and on exposed regions of BE22a,22d1,22d2and on BE ILD20. A CMP process may be employed to make the MTJ ILD layer30coplanar with hard mask24.

The present invention also anticipates alternative methods of patterning the MTJ and BE elements. For example, as described in patent application Ser. No. 11/724,435, the BE layer, MTJ stack, and hard mask may be sequentially laid down before the MTJ and hard mask are patterned. Thereafter, the BE layer may be patterned to form BE elements. The BE mask layout disclosed herein could also be implemented in this alternative fabrication scheme. However, those skilled in the art will appreciate that the fabrication method will be altered somewhat to align the BE mask to the MTJ pattern instead of aligning to the underlying WL pattern as in the exemplary embodiment.

Returning toFIG. 1a, a second etch stop layer31and BIT ILD layer32are sequentially formed by conventional methods on the MTJ ILD layer30and hard mask24. The second etch stop layer31is formed by a CVD or PVD method, for example, and may be comprised of SiNx or the like. The thickness of the second etch stop layer31may be in the range of 100 to 500 Angstroms. Thereafter, a BIT line ILD layer hereafter referred to as BIT ILD layer32having a thickness of about 1000 to 10000 Angstroms is deposited on the second etch stop layer31. The BIT ILD layer32may have the same composition as the dielectric material in the MTJ ILD layer30, BE ILD layer20, and in WL ILD layer13.

A dual damascene process is then performed in which a first patterning and etch sequence is used to form trenches in the BIT ILD layer32that uncover portions of the MTJ ILD layer30. A second photoresist patterning and etch sequence is followed to form vias also known as contact holes below the trench openings and through the MTJ ILD layer30, and ILD layer17below vias70,73thereby uncovering portions of the WLP14a,14cbelow the vias and trench openings. Once the second photoresist layer is removed, the vias and trenches are filled with metal such as Cu. Thus, a bit line contact48ais formed that connects to WLP14a, and a bit line contact48cis formed that contacts WLP14c. In addition, bit line48bis formed on hard mask24above MTJ23aand WL15. A CMP process is performed to achieve planarization of BIT48bwith BIT contacts48a,48c.

According to the present invention, the BE layout comprises at least four distinct mask sections that may be referred to as (1) an active device area which will be used to form active BE elements in MRAM cells, (2) a bond pads area, (3) an open field area that will be aligned above a region in the substrate without WL metal under the etch stop ILD, and (4) an open field area that will be aligned over a region in the substrate with WL metal under the etch stop ILD. These four sections are repeated in a plurality of locations across the BE mask. The actual position and area occupied by each section on the BE mask varies with respect to the design of the MRAM array. Each of the BE layout sections may abut one or more of the other BE layout sections.

Referring toFIG. 4a, a prior art BE design employed by the inventors includes a device area100ahaving portions of two adjacent device blocks300,301on the BE mask. Dashed line104denotes the boundary between device blocks300,301. Opaque BE shapes110in device area100aare superimposed over word lines15a-15dand a plurality of WLP14cin a substrate to indicate the alignment that is required when transferring the features on the BE mask including those in device area100ainto a photoresist layer coated on the substrate above WL15a-15dand WLP14c. Note that a stack comprised of a lower etch stop ILD layer, middle unpatterned BE layer, and upper photoresist layer are not shown above the WL15a-15dand WLP14cin order to simplify the drawing and emphasize the alignment of device area100ato the word line metal layer. The regions101in device area100anot covered by BE shapes110are clear quartz (mask substrate). There are no dummy BE shapes between BE shapes110in adjacent device blocks. It should be understood that there are 1 million BE shapes110in each device block300,301in a 1 Mb MRAM device, for example.

InFIG. 4b, a portion of a prior art BE layout is shown that is a bond pads area100b. There are no opaque features on this section of the BE mask. Therefore, in an embodiment where the boundary of the bond pads area is indicated by the shape140, the region101inside the bond pads area is clear quartz. Optionally, shape140may be polygonal or another shape that conforms to the BE layout. The region102outside the bond pads area may have a combination of clear regions and opaque shapes (not shown). As a result, all of the photoresist layer on the substrate which is exposed through region101will be removed in the photoresist development process. During the subsequent etch process, all of the BE layer on the substrate which was uncovered by the removal of the photoresist layer during the patterning process will be removed to expose an underlying etch stop layer (not shown). This method can easily lead to defect issues as the etch process has a tendency to thin the large open regions of underlying etch stop ILD layer to yield pinholes and give a greater susceptibility to delamination which increases as ILD thickness decreases.

Referring toFIG. 4c, an open field area100cof a prior art BE layout that is not overlaid on a WL metal region in the substrate is depicted. Opaque BE dummy shapes160are formed on a clear quartz substrate101in the BE mask and may be formed in a plurality of rows and columns. Typically, the dummy BE elements160have the same shape and density as the overlying dummy MTJ elements that will be formed in a later step of the MRAM fabrication process using a MTJ mask.

Referring toFIG. 4d, an open field area100dof a prior art BE layout is overlaid on a portion of the substrate with word lines15e,15fformed therein. A plurality of opaque BE dummy shapes160is formed on a clear quartz substrate101and have a shape and density similar to the dummy BE shapes in open field area100c.

According to the present invention, a new BE layout has been discovered that affords improved MRAM performance by minimizing defects arising from undesired thinning, delamination, and pinhole defect formation in the etch stop ILD layer. Three of the four BE layout sections mentioned previously with respect toFIGS. 4a-4dhave been modified. Only the third section involving BE dummy shapes formed over a substrate region with no underlying WL metal remains essentially the same as in the prior art design.

Referring toFIG. 5a, one important feature of the present invention is the new BE layout section200afor the device area which is depicted with two device block sections400,401that are separated by dashed line204. Only portions of two device blocks are shown to simplify the drawing. Each device block comprises a device region and open field regions between active devices. The actual number of device blocks depends on the type and size of MRAM cell to be fabricated. Unlike the prior art design that has no dummy BE features, layout section200acomprises a plurality of dummy BE shapes203formed between BE shapes202. In one embodiment, both the BE shapes202used to make active BE elements and the dummy BE shapes203have a rectangular shape with a length d and a width w that are generally less than 1 micron in size. Optionally, the BE features202,203may have other shapes including polygons or circles as appreciated by those skilled in the art. It should be understood that the photoresist patterning process does not perfectly transfer a shape on the BE mask into the photoresist layer. Thus, a rectangular shape on the BE mask may print as an oval in the photoresist film. In general, sharp corners on mask features that are sub-micron in size become rounded corners in the imaged photoresist film. Moreover, most exposure systems involve a 4× or 5× reduction in image size which means a feature with a 1 micron dimension on the BE mask is transferred into the photoresist film as a feature with a 0.25 micron dimension for a 4× optical reduction process. Thus, any two sides of BE features202,203that face each other are separated by a distance of about 0.5 to 1.0 microns for a 5× optical reduction mask design and a distance of about 0.4 to 0.8 microns for a 4× optical reduction mask design.

The space s which separates the long sides or short sides of any two adjacent BE features202,203is preferably between 0.4 and 1.0 microns in order to print an actual space of 0.1 to 0.2 microns between adjacent BE22afeatures in a MRAM device. In one embodiment, the space s is kept constant across the mask layout. The space s is sufficiently large to avoid two adjacent WL/BIT shorts in the final device (FIG. 1) even though there may be a defect related short between a BE element22aand WL15through the etch stop ILD17in one MRAM cell. Note that BE shape202becomes BE element22aand dummy BE shape203becomes BE dummy22d1in a MRAM cell in the final device. Alternatively, the dimension s may vary slightly across the BE layout section200a. The important aspect is that the dummy BE features203are used to cover a majority of the clear quartz regions201between adjacent BE features202on BE layout200a.

In yet another embodiment (not shown), a plurality of dummy BE features203may be joined together to form one larger BE dummy feature in BE layout section200a. For example, four adjacent dummy BE features203arranged in a 2×2 array may be joined together to form one larger BE dummy feature having a length (2d+s) and a width (2w+s). Thus, there may be a plurality of dummy features203with size (w×d) in the same device block and one or more dummy features having a size [(2w+s)×(2d+s)]. Preferably, the distance between a side of the large dummy feature and a side of a smaller dummy feature203is the dimension s.

Note that the BE layout200ais overlaid on the substrate such that each of the BE shapes202is aligned above one WL. In the exemplary embodiment, only WL15a-15dare depicted but it should be understood that there is a plurality of WL in the substrate. Another important feature is that a plurality of dummy BE shapes203which are disposed above a WLP14chave a via210formed therein. In one embodiment, each via210has a square shape with a dimension k where k<w and exposes a clear quartz region201in the BE mask. Optionally, other via shapes may be employed. The vias210enable an opening to be formed in the BE dummy elements in the partially completed MRAM cell so that a subsequent process step may be used to form a BIT contact to the WLP14cthrough the opening70(FIG. 2).

Referring toFIG. 5b, a section200bof the new BE layout is depicted that represents a bond pads area. Unlike a prior art design (FIG. 4b) that has no opaque features, the bond pads section disclosed herein has a majority of the clear quartz substrate covered by opaque material205such as chrome. There is a plurality of openings (vias214) where the clear quartz substrate201is uncovered. The vias214are employed to eventually form openings in the BE layer which will be subsequently filled with metal to allow BIT contact48cto connect with WLP14c. As a result of BE pattern transfer into the BE layer, the opaque region205becomes unpatterned BE layer that remains in the device to protect underlying etch stop ILD layer17from delamination and exposure to etchants that could form pinholes. Incorporation of BE layout section200bprovides an extra measure of protection to etch stop ILD layer17to improve MRAM performance. Opaque region205becomes BE dummy element22d2when the BE layer is patterned during MRAM fabrication (FIG. 1).

Referring toFIG. 5c, the BE layout section200crelates to a BE open field area without underlying WL metal in the MRAM cell. Similar to the design inFIG. 4c, there is a plurality of opaque features such as rectangular shapes220formed on a clear quartz substrate201. In one embodiment, each of the rectangular opaque shapes220has a length b and a width c. Preferably, the distance a between adjacent shapes220is greater than c. In an alternative embodiment, c≧a. The dummy BE shapes220will become dummy BE elements in the BE layer of the MRAM cell following pattern transfer. The density of dummy BE shapes220is kept essentially the same as the MTJ dummy density in a corresponding open field area section of the MTJ layout as appreciated by those skilled in the art.

InFIG. 5d, a BE layout section200dis illustrated that relates to a BE open field area that is aligned above WL metal in a device during the BE patterning process. In the exemplary embodiment, there is a plurality of opaque dummy BE features230arranged in rows and columns, for example, that are aligned above a WL metal array including WL15e,15f. Each dummy BE shape230has a length x and a width y such that a substantial portion of clear quartz substrate201is covered by the opaque features. Preferably, the distance between two adjacent dummy BE features230is approximately the dimension s. Again, the addition of more opaque coverage on the BE mask in layout section200dcompared with dummy BE160density inFIG. 4dmeans that there will be more dummy BE coverage of etch stop ILD layer17in the final MRAM device according to the present invention. Dummy BE shapes230may have shapes other than rectangles and may be formed in arrays other than rows and columns.

It is important to increase the size of BE dummy features230in section200drelative to BE dummy features220in section200csince an etch stop ILD layer is subject to additional strain in regions above or proximate to WL metal. For example, thermal expansion and contraction from WL metal places additional stress on an overlying etch stop ILD layer that can lead to delamination in prior art designs. However, according to the present invention, etch stop ILD layer17is covered by dummy BE elements (not shown) fabricated from dummy BE shapes230that provide additional support and protection from strain in open areas near WL metal.

Referring toFIG. 6, the overlay of opaque MTJ dummy shapes560on dummy BE features220dformed in an open field area of in the BE layer in a MRAM device is depicted to show that the MTJ dummy density and shape may be similar to that in the underlying BE dummy elements220d. Note that BE dummy elements220dare formed as a result of the BE layer patterning process using BE layout section220cwith opaque BE dummy shapes220. Although this drawing represents a MRAM fabrication sequence where the MTJ stack of layers is patterned after the BE layer is patterned, the present invention also encompasses a process flow where the BE layer is patterned following the formation of MTJ elements as mentioned previously. In the latter case, the BE layout200cwould be overlaid on the MTJ array but the density and shapes of the BE dummy features and MTJ dummy features would preferably remain the same.

Referring toFIG. 7, the overlay of opaque MTJ dummy shapes510on dummy BE features230dformed in an open field area in the BE layer with underlying WL metal is illustrated to show that the MTJ dummy density may be the same as the underlying BE dummy density230din this part of the MRAM device. BE dummy elements230dare formed as a result of the BE layer patterning process using BE layout section220dwith opaque BE dummy shapes230. However, the size of the MTJ dummy features510is preferably kept about the same as the size of the MTJ dummy features560in an open field area without underlying WL metal. Thus, the size of the BE dummy features230dmay be considerably larger than the size of overlying MTJ dummy features (not shown) resulting from patterning of the MTJ layer in open field areas with underlying WL metal.

By implementing the novel BE layout comprised of at least four separate sections as described herein, a significant improvement in etch stop ILD reliability and MRAM performance is realized. The additional dummy BE coverage of etch stop ILD layer proximate to underlying WL metal offers additional protection to minimize delamination of thin etch stop ILD layers. The dummy BE coverage allows etch stop ILD layers to be thinned to a greater extent than before without encountering device failure issues due to ILD peeling. Moreover, the additional dummy BE coverage in device areas enables a more uniform etch stop ILD layer across the substrate thereby minimizing defects such as pinholes that form when the etch stop ILD layer is thinned uncontrollably from etching processes in large open areas. Overall improvement in reliability and performance is expected to allow a higher density MRAM device to be fabricated to meet the demands of advanced technologies.