Nonvolatile memory cell with improved isolation structures

An array of floating gate transistors of a non-volatile memory, NVM, cell includes floating gate transistors separated from one another by high-concentration dopant impurity regions and without using shallow trench isolation (STI) or field oxide (FOX) isolation structures. The array is formed over a substrate portion that includes a continuous and planar upper surface. The high-concentration dopant impurity regions are formed in a P-field region and are formed of the same dopant impurity species as the P-field region but of a higher concentration. The floating gate transistors are split-gate floating gate transistors in some embodiments.

TECHNICAL FIELD

The disclosure relates, most generally, to semiconductor devices and methods for manufacturing the same. More particularly, the disclosure is related to non-volatile memory cells with improved isolation structures, and methods for manufacturing the same.

BACKGROUND

Non-volatile memory (NVM) devices are commonly used in the electronics world and provides computer memory that can retrieve stored information even when not powered. Non-volatile memory cells include floating gate transistors and in some cases, split-gate floating gate transistors. Non-volatile memory cells typically include an array of floating gate transistors and some adjacent floating gate transistors are isolated and separated from one another using thick oxide structures. The thick oxide structures include shallow trench isolation (STI) devices formed in trenches and filled with dielectric materials, and also thick field oxide, FOX, structures disposed between the transistors.

The STI or FOX structures used to separate and isolate adjacent floating gate transistors from one another generally include upper surfaces that extend above the substrate surface and which form sharp interfaces with the substrate surface. This topography can cause several problems including the undesirable retention of charge at undesired locations. The etching processes used to form trenches within which the STI structures are formed, create undesirable crystal defects in the sidewalls of the trenches. The STI or FOX structures have been found to be the source of stress defects, electrical defects and poor topography that causes degradation of NVM performance. It would be desirable to produce NVM cells without the above-identified problems.

DETAILED DESCRIPTION

The disclosure, in various embodiments, provides for an array of floating gate transistors of a non-volatile memory, NVM, cell. The floating gate transistors are separated from one another by high-concentration dopant impurity regions. The array is formed over a substrate portion that includes a continuous and planar upper surface. The continuous and planar upper surface is achievable because the high-concentration dopant impurity regions are formed in a P-field region and each extend downwardly from the continuous and planar upper surface of the substrate over which the array is formed. Shallow trench isolation (STI) and field oxide (FOX) isolation structures are not used in the array area and the disclosure provides the advantage that problems associated with the topography of STI and FOX isolation structures is avoided. The problems associated with the crystal defects formed the sidewalls of the trenches due to the etching processes used to form trenches for the STI structures, are also avoided. In some embodiments, the floating gate transistors are split-gate floating gate transistors in which the control gate or word line extends only partially over the subjacent floating gate. The smooth upper surfaces and lack of crystal defects associated with sidewalls, alleviates unwanted sharp edges on the substrate surface and enables the formation of structures over the substrate surface without sharp edges. The absence of sharp edges reduces power consumption of non-volatile memory, NVM cells, enhances the endurance of floating gate transistors, prolongs data retention of floating gate transistors, and improves the disturb characteristics of the floating gate transistors because the sharp edges are prone to high current concentrations. The use of an implant instead of deposited or grown oxide structures enables the size reduction of the unit cell size of an array of floating gate transistors that form an NVM cell because implantation regions can be made to smaller controlled dimensions than STI structures or grown oxides.

FIG. 1Ais a plan view showing a portion of an array of floating gate transistors according to some embodiments of the disclosure.FIGS. 1B, 1C and 1Dare each cross-sectional views taken along the indicated line shown inFIG. 1A. The following description refers to each ofFIGS. 1A, 1B, 1C and 1D. The floating gate transistors of the array will be described in terms of N-type floating gate transistors, i.e., floating gate transistors with N-type source and drain regions formed over a P-type channel region. In various other embodiments, however, the non-volatile memory cell includes P-type floating gate transistors in which the dopant types are reversed with respect to the following description.

According to the N-type floating gate transistor embodiment, a P-field region is formed within the substrate. The substrate is a silicon or other suitable substrate used in the semiconductor manufacturing industry. P-field region12is shown most clearly inFIGS. 1B, 1C and 1D, but is essentially obscured inFIG. 1A. The array of floating gate transistors shown inFIG. 1Ais formed over or on a P-field region of a substrate. P-field region12is formed by ion implantation or diffusion of impurities into the substrate, in various embodiments of the disclosure and may be formed of boron or other suitable P-type dopant impurities in various embodiments. In some embodiments, P-field region12includes a dopant concentration in the range of about 1e15 atoms/cm3 to about 5e17 atoms/cm3and has a dopant concentration of about 1e16 atoms/cm3 to 1e17 atoms/cm3in some embodiments. P-field region12has a dopant concentration of around 1e17 atoms/cm3in some embodiments, but other dopant impurity concentrations suitable for use as transistor channels, are used in other embodiments. The P-field region12includes various dimensions in various embodiments. The NVM array ofFIG. 1Aincludes an array of floating gate transistors, associated with a corresponding floating gate structure8and although sixteen such structures are represented inFIG. 1A, the NVM arrays include various numbers of floating gate transistors in various embodiments.

Channel direction15is the direction along which current flows from source to drain in an operating floating gate transistor. Along the direction orthogonal to channel direction15, i.e. along orthogonal direction25, the respective transistors represented by the respective floating gate structures8, are separated from one another by spaced apart high concentration dopant impurity regions13. According to one description, along orthogonal direction25are alternating regions of P-field region12and high concentration dopant impurity regions13. High concentration dopant impurity regions13are P+ regions within the P-field region12and include higher concentrations of the same dopant impurity species, than the P-field region12. High concentration dopant impurity regions13are rectangular in shape in the plan view ofFIG. 1Aenabling the formation of an array of linearly arranged transistors, but take on other shapes in other embodiments. The rectangular shape includes a lesser lateral dimension of about 0.4 microns in some embodiments, as will be shown inFIG. 1D. High concentration dopant impurity regions13are formed by introducing dopant impurity species into already formed P-filed region12using ion implantation or diffusion or other suitable methods for introducing dopant impurities into a substrate material in some embodiments. In some embodiments, high concentration dopant impurity regions13include the same dopant species as P-field region12and in other embodiments, high concentration dopant impurity regions13and P-field regions12are formed of the same dopant impurity type (i.e. “N” or “P”) but different dopant species.

Now referring to features most clearly shown inFIGS. 1A and 1B, source regions2are formed within P-field region12and take on the structure of source lines in the embodiment shown inFIG. 1A. Source regions2are N+regions and are formed by ion implantation or other suitable methods of introducing N-type dopant impurities such as phosphorus or other suitable N-type dopants, into P-field regions12. N+drain regions16are also formed within P-field12. N+drain regions16are formed by ion implantation or other suitable means for introducing dopant impurities into a substrate. The N+regions, i.e. source regions2and N+drain regions16are formed of phosphorus, arsenic or other suitable N-type dopant impurities in various embodiments. The N+regions, i.e. source regions2and N+drain regions16, include various dopant concentrations in various embodiments, but the “N+” designation is used in the semiconductor manufacturing industry to signify a relatively high dopant concentration compared to other N-type dopant concentrations. In some embodiments, either or both of the N+regions include phosphorus having a dopant concentration in the range of about 1e20 atoms/cm3to 1e21 atoms/cm3and in some embodiments, either or both of the N+regions include arsenic at a concentration in the range of about 1e20 atoms/cm3to 1e21 atoms/cm3but other N+dopant impurities and other concentrations sufficient for use as source/drain regions, are used in other embodiments.

FIG. 1Bmost clearly shows the P-field regions12, source regions2and N+drain regions16are formed within and extend downwardly from substrate surface7. P-field regions12, source regions2and N+drain regions16do not extend above substrate surface7. Substrate surface7is a continuous and planar surface throughout the array. Each floating gate transistor includes a floating gate structure8that includes floating gate electrode10and inter-gate oxide30formed over gate dielectric17. Inter-gate oxide30is bi-convex in shape inFIG. 1Bbut has other configurations in other embodiments. Floating gate electrode10includes various dimensions in various embodiments and is formed of polysilicon in some embodiments and other suitable conductive or semiconductive gate materials in other embodiments. Word line4serves as a control gate that extends partially but not completely over floating gate structure8in the split-gate embodiment shown inFIG. 1B, but other arrangements are used in other embodiments. Word line4is formed of polysilicon or other suitable gate materials in various embodiments and is separated from floating gate structure8by dielectric liner36which is also an inter-gate dielectric. In some embodiments, word line4has a top surface that includes a silicide material. In addition to oxide, various other suitable dielectrics are used for dielectric liner36in various embodiments. Channel direction15is the direction along which charge flows between source regions2and N+drain structure16. Channel direction15also indicates the channel, i.e., the uppermost portion of P-field12region between source regions2and N+drain regions16which provides the path along which charge flows between source regions2and N+drain structure16.

The floating gate transistor structure8shown inFIG. 1B, is separated from further floating gate transistors that are adjacent floating gate transistor structure8along the direction in and out of the plane of the drawing figure, i.e., adjacent along orthogonal direction25orthogonal to the channel direction. This is shown inFIG. 1A. InFIG. 1A, each floating gate transistor structure includes floating gate structure8which includes floating gate electrode10and inter-gate oxide30. Channel direction15is shown inFIG. 1Awhich also shows that the floating gate structure8is partially overlapped by word line4that serves a control gate and the channel27includes charge moving from source regions2to N+drain regions16for the respective transistors.

Along the direction orthogonal to channel direction15, i.e. along orthogonal direction25, the respective transistors associated with respective floating gate structures8, are separated from one another by high concentration dopant impurity regions13. According to the N-type floating gate transistor embodiment, high concentration dopant impurity regions13are P+dopant impurity regions and in various embodiments, the high concentration dopant impurity regions13are deep P-well dopant impurity regions designated DW regions. In some embodiments, high concentration dopant impurity regions13are doped with boron and include a dopant impurity concentration greater than the dopant impurity concentration in P-field of region12. In some embodiments, high concentration dopant impurity regions13are doped with boron and in some embodiments, high concentration dopant impurity regions13are doped at a concentration range of about 1e15-1e19 atoms/cm3 which provides a dopant concentration sufficient to isolate the devices formed in P-field regions12such as floating gate or other transistors formed between and isolated by the high concentration dopant impurity regions13. The dopant concentration is also chosen to avoid breakdowns at any P-N junctions that may form between high concentration dopant impurity regions13and source regions2and N+ drain structure16. Other dopant impurity species and other dopant impurity concentrations are used in other embodiments.

FIG. 1Cshows high concentration dopant impurity regions13spaced apart along orthogonal direction25which is the direction orthogonal to channel direction15. The floating gate transistor structures are formed in P-field regions12and between the respective high concentration dopant impurity regions13. The current or charge that flows in channel direction15(seeFIG. 1B), flows in the direction orthogonal to the plane of the drawing figure for the drawing ofFIG. 1Cfor the operating transistor. InFIG. 1C, N+drain structure16, to which the current of the floating gate transistors flows, is disposed above P-field region12in the area between high concentration dopant impurity regions13. Contact26provides contact to N+drain structure16and includes silicide region34formed on substrate surface7of N+drain structure16in some embodiments. Still referring toFIG. 1C, high concentration dopant impurity regions13include depth14of about 1.5 microns or within the range of about 1-2 μm in some embodiments but other suitable depths that are deep enough to isolate P-field regions12from one another, are used in other embodiments.

FIG. 1Dis also taken along orthogonal direction25.FIG. 1Dshows two floating gate structures8, each including floating gate electrode10and inter-gate oxide30adjacent one another along the direction, orthogonal direction25, orthogonal to a channel direction of the transistor. The adjacent transistors shown inFIG. 1D, are separated by high concentration dopant impurity region13and formed over P-field region12. Word line4which serves as a control gate, couples the two adjacent transistors shown inFIG. 1D, but in other embodiments, other arrangements are used. Word line4is separated from the respective floating gate electrodes10by dielectric liners36and also inter-gate oxide30. In some embodiments, high concentration dopant impurity regions13include a width40that ranges from about 0.2 to 0.6 microns and may be 0.4 microns, along orthogonal direction25, but other widths are used in other embodiments. It is desirable to provide feature sizes as small as possible to increase integration levels and such widths are achievable using the patterning and implanting methods used to form dopant impurity regions13. In some embodiments, the array includes features and spacings that are essentially the same throughout the array, for example, high concentration dopant impurity regions13include the same width and depth throughout the array but in other embodiments, the array may include different dimensions.

As shown inFIGS. 1B, 1C and 1D, substrate surface7is continuous and planar within the array region. For example, inFIG. 1D, the intersection21between high concentration dopant impurity regions13and P-field region12along surface7is smooth and there are no divots at intersection21. This smooth surface enables floating gate electrode10to have smooth bottom edges23, again free of divots or sharp points that cause the problems associated with high current concentration as described above. This, in turn, enables the formation of superjacent materials such as the word line, without sharp edges or divots. This alleviates any potential problems that could be caused by topography issues created by the use of STI or FOX structures instead of high concentration dopant impurity regions13. STI and FOX structures are not present in the NVM array, in various embodiments.

The disclosed NVM cell structure provides for lower power consumption due to the absence of stress and divots at corners of STI structures as in other structures. Disturbed characteristics and data retention properties are improved and the avoidance of STI structures enables for greater integration levels as the high concentration dopant impurity regions13of the disclosed NVM can be formed to smaller dimensions than STI structures and avoid the crystal defects associated with forming the trenches used for the STI structures.

In various embodiments, an array of floating gate transistors is provided. The array comprises: a plurality of floating gate transistors, each formed over a corresponding channel region of a substrate, each channel region being of a first impurity type and laterally bounded in a first lateral direction by source/drain regions of a second impurity type, wherein the floating gate transistors that are adjacent one another in a direction orthogonal to the first lateral direction, are separated from one another by respective high-concentration impurity regions of the first impurity type formed in the substrate. The high-concentration impurity regions have dopant concentrations greater than dopant concentrations of the channel regions.

In some embodiments, the array of floating gate transistors includes the corresponding channel regions formed in a P-field region that includes boron as a dopant impurity therein, and wherein the floating gate transistors that are adjacent one another along the channel direction are formed over a common P-field region.

Also provided is an array of floating gate transistors formed over a substrate region that includes alternating regions of heavily doped impurity regions of a first impurity type and lesser doped impurity regions of the first impurity type and no oxide isolation structures formed in the substrate in the substrate region, wherein each floating gate transistor is formed in the lesser doped impurity regions.

Also provided is a method for forming a non-volatile memory cell. The method comprises: forming a P-field region in a semiconductor substrate, the P-field region having a first impurity concentration; forming a plurality of spaced apart high concentration P+ regions within the P-field region, the high concentration P+ regions each having a higher concentration than the first impurity concentration; and forming a plurality of floating gate transistors in the P-field region between the high concentration P+ regions.