Partial-rate transfer mode for fixed-clock-rate interface

Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.

BACKGROUND

This disclosure generally relates to transmitter and receiver systems. In particular, this disclosure relates to systems that facilitate a partial-rate data transfer mode using fixed-clock-rate interfaces.

Present computing and communication systems require progressively higher off-chip communications bandwidth, and multi-Gb/s serial links for chip-to-chip interconnects are becoming ubiquitous. Meanwhile, power consumption is becoming an increasingly important design metric, especially for mobile applications. System designers often face the challenge of providing high bandwidth, low power consumption, and minimal latency at the same time.

TABLE 1 presents a set of exemplary power-consumption values and the amount of time for transitions between different modes in a 6.25 Gb/s system which can operate in a partial-rate transfer mode but configured to operate in conventional modes, in accordance with one embodiment of the present invention.

TABLE 2 presents a set of exemplary power-consumption values and the amount of time for transitions between modes in a 6.25 Gb/s system configured to operate in a partial-rate transfer mode in accordance with one embodiment of the present invention.

In the drawings, the same reference numbers identify identical or substantially similar elements or acts. The most significant digit or digits in a reference number refer to the figure number in which that element is first introduced. For example, element102is first introduced in and discussed in conjunction withFIG. 1.

DETAILED DESCRIPTION

Overview

Embodiments of the present invention provide a novel system that facilitates a partial-rate transfer mode for fixed-clock-rate transmission/receiving interfaces. In one embodiment, the transmitter-receiver pair operates in three modes: a standby mode, a partial-rate mode, and an active mode. During the standby mode, most of the receiver circuitry is turned off. A global clock signal is continuously delivered to the receiver, and a global phase-locking mechanism on the receiver remains operative to provide a clock signal with a deterministic phase.

In the partial-rate mode, the receiver activates its local phase-adjusting circuitry to generate the sampling signals that are to be used for sampling data during the active mode. Meanwhile, the transmitter can emulate a partial-rate transmission by transmitting each data bit two or more times at full data rate. As a result, the receiver can use the global clock signal without any phase adjustment to receive the data. Note that this partial-rate data transfer can be performed with the normal clock rate. Hence, embodiments of the present invention can benefit systems with a fixed clock rate. This partial-rate transfer mode allows data transfer during the transition from the standby mode to the active mode. Consequently, the system can reduce data-transfer latency and increase the effective bandwidth.

Multi-Mode Operation without Partial-Rate Data Transfer

FIG. 1illustrates a transmitter-receiver pair capable of operating in a partial-rate transfer mode but configured to operate in conventional power-down, standby, and active modes and an exemplary power-consumption vs. time diagram for different modes, in accordance with one embodiment of the present invention. (Note that, in some embodiments, a transmitter or receiver system is capable of operating in the novel partial-rate transfer mode as well as the conventional power-saving modes.) System102includes four transmitters112,118,122, and128, and four receivers114,120,124, and130. System102also includes a global phase-locking mechanism104, which is coupled to a global clock distribution mechanism184and produces a local clock signal for the transmitters and receivers in system102. Also included in system102are four local phase-adjusting mechanisms116,121,126, and132, which are coupled to receivers114,120,124, and130, respectively. Note that global clock distribution mechanism184can be a stand-alone mechanism outside of system102or142, or can be included in one of the systems. For example, system102can be a memory controller which includes a global clock generation or distribution mechanism, and system142can be a memory module.

Similarly, system142includes four transmitters156,162,168, and174, and four receivers152,158,164, and170. System142also includes a global phase-locking mechanism144, which is coupled to global clock distribution mechanism184and produces a local clock signal for the transmitters and receivers in system142. Also included in system142are four local phase adjusting mechanisms154,160,166, and172, which are coupled to receivers152,158,164, and170, respectively.

Transmitters112,118,122, and128are coupled to receivers152,158,164, and170, respectively. Similarly, transmitters156,162,168, and174are coupled to receivers114,120,124, and130, respectively. Global phase-locking mechanisms104and144lock into the frequency of the global clock signal with a deterministic phase in their respective outputs. These output clock signals are then respectively distributed through out systems102and142. Global phase-locking mechanisms104and144include phase-locking loops (PLLs). These PLLs lock into the frequency of the global clock signal. These PLLs provide only limited phase-adjusting capabilities with respect to their output signals. That is, the output of these PLLs only needs to be frequency-locked, but not phase-locked, to the global clock signal. Note that these PLLs still need to produce a signal with a substantially deterministic phase. In other words, the phase of the output of global phase-locking mechanism104or144does not vary quickly over time.

Since systems102and142are substantially similar, the following description, although directed to system102, is also applicable to system142. The output of global phase-locking mechanism104is a signal with the same frequency as the global clock signal and is distributed to the transmitters and receivers in system102. Note that this global clock signal typically exhibits an arbitrary (but fixed) phase relative to the incoming data signals, and therefore cannot be directly used for data-receiving purposes. Hence, a respective receiver is equipped with a phase-adjusting mechanism to fine-tune the phase of the global clock signal, so that transitions of the phase-adjusted global clock signal (i.e., sampling edges) are aligned with desired sampling points in the incoming data signals, and thereby provide sufficient signal-detection margin. For example, receiver114is equipped with a phase-locking loop116to generate a phase-adjusted local clock signal having an arbitrary phase offset relative to the global clock signal, and thereby provide receiver114with a phase-adjusted local clock signal having sampling edges in a desired alignment with the incoming data signal. For instance, the data-sampling edge used by receiver114may fall approximately in the center of a data eye (i.e., interval over which data is valid and may be sampled), which gives receiver114sufficient margin for data detection.

Phase-locking mechanism104differs from PLL116and other receiver-specific PLLs in that phase-locking mechanism104does not provide arbitrary phase-adjustment capability with respect to its output signal. As a result, PLL104is typically less complex and consumes less power. Phase-locking mechanism104performs only frequency-locking, but not phase-locking, to the global clock signal. In particular, phase-locking mechanism104does not need to provide a phase vector which is typically used to interpolate and adjust the phase of the output signal to a specific position relative to the global clock signal.

Although capable of operating in the novel partial-rate mode, in this example, systems102is configured to operate in three modes: power-down, standby, and active. In the power-down mode, at least some components of system102, including phase-locking mechanism104, are disabled or otherwise turned off (i.e., the supplied power is removed), so that little or negligible power is consumed.

In the standby mode, receivers114,120,124, and130, and transmitters112,118,122, and128are turned off (i.e., the power to these components is removed). However, phase-locking mechanism104and phase-adjusting mechanisms116,121,126, and132remain powered on, operational, and locked in, thus resulting in reduced, but non-negligible power consumption.

In the active mode, all the receivers114,120,124, and130, transmitters112,118,122, and128, phase-adjusting mechanisms116,121,126, and132, and the phase-locking mechanism104are powered on and operate at the full data rate.

TABLE 1 presents a set of exemplary power-consumption values and the amount of time for transitions between different modes in a 6.25 Gb/s system capable of operating in a partial-rate transfer mode but configured to operate in the conventional modes, in accordance with one embodiment of the present invention.

TABLE 1SymbolDescriptionValuepPPower consumption during power-down~0mWmodepSPower consumption during standby mode~20mWpAPower consumption during active mode~110mWpPAPower consumption during transition from~40mWpower-down mode to active modepSAPower consumption during transition from~40mWstandby mode to active modetBITActive-mode bit time~160pstPATransition time from power-down mode to~500 ns, oractive mode3000 tBITtSATransition time from standby mode to~15 ns, oractive mode100 tBIT

As shown in TABLE 1, although the standby-to-active transition is relatively short, the standby power consumption is approximately one sixth of the active power consumption. Hence, if the system remains in the standby mode for too long, the standby power consumption can quickly offset the power savings. On the other hand, although the power-down mode consumes a negligible amount of power, the power-down-to-active transition takes a long time and can consume a significant amount of power. Since the system cannot transmit or receive data during the transition period, if the system switches between power-down and active modes frequently, the system would lose the power-saving benefits and suffer from increased data-transfer latency.

The problem described above is more clearly illustrated in the exemplary power-consumption vs. time diagram for different modes inFIG. 1. As illustrated in this example, the system enters the standby mode after the first active period. Since this standby period is significantly longer than the first active period, the total power consumption in the standby period actually surpasses the power consumed during the first active period.

After the second active period, the system enters the power-down mode. After being in the power-down mode for a short time, the system needs to enter the active mode for data transfer. However, the system cannot quickly switch to the active mode, because the receiver and phase-adjusting circuitry have been turned off in the power-down mode. Consequently, the system spends tPA amount of time in transition, when the phase-locking and phase-adjusting mechanisms prepare the proper clock signals, before it can commence data transfer.

As illustrated in the example inFIG. 1, if the system experiences many short bursts of data transfers followed by periods of inactivity, the system would be switching between different modes frequently. Over time, the power savings could only be marginal due to the higher power consumption in the standby mode and power-down-to-active transitions.

Partial-Rate Transfer Mode

In one embodiment, a receiver system, with collaboration from a transmitter system, is configured to operate in three modes: standby, partial-rate, and active. In the standby mode, at least some components of the receiver circuit, except for the global phase-locking mechanism, are turned off (i.e., with power removed). In the partial-rate mode, the local, receiver-specific phase-adjusting mechanisms are powered on to lock into the respective phase for optimal data reception at a respective receiver. Meanwhile, the receivers are also powered on to receive data by using the global clock signal provided by the global phase-locking mechanism without any phase adjustment. Each data bit is transmitted multiple times at the full data rate by the transmitter. In this way, the system can reliably receive the payload data at an effective partial data rate without using the local fine-tuned, phase-adjusted sampling edges. Furthermore, the partial-rate transfer mode does not require a slower clock speed, which allows systems with fixed-clock-rate interfaces to benefit from the power savings.

FIG. 2illustrates a number of transmitter-receiver pairs configured to operate in standby, partial-rate, and active modes and an exemplary power-consumption vs. time diagram for different modes in accordance with one embodiment of the present invention. System202includes a global phase-locking mechanism204, a number of transmitters such as transmitter212, receivers such as receiver214, and phase-adjusting mechanisms such as phase-adjusting mechanism216. Similarly, system242includes a global phase-locking mechanism244, a number of transmitters such as transmitter256, receivers such as receiver252, and phase-adjusting mechanisms such as phase-adjusting mechanism254.

A respective transmitter in system202is coupled to a receiver in system242, and a respective receiver in system202is also coupled to a transmitter in system242. There are four bi-directional data transfer channels between systems202and242. Although the description below is directed to system202, the same description also applies to system242.

In the standby mode, at least part of system202is turned off. However, global phase-locking mechanism204remains operational in the standby mode, so that the global clock signal remains locked in and distributed to the transmitters and receivers. In one embodiment, global phase-locking mechanism204is a phase-locking loop which is capable of locking to the global clock signal's frequency and producing a clock signal with a deterministic phase. In the following description, this phase-locked global signal is indicated by the suffix “_G.” For example, (clkP_G, clkN_G) denotes a pair of complementary, phase-locked global clock signals. Furthermore, the phase-adjusted, receiver-specific clock signals are indicated by the suffix “_L.” Note that the power consumed by PLL204is relatively low compared with the power consumption of phase-adjusting mechanism216, which includes circuitry for arbitrary phase adjustments.

In the partial-rate mode, the phase-adjusting mechanisms in system202are turned on. Referring to phase-adjusting mechanism216for example, in the partial-rate mode, phase-adjusting mechanism216adjusts the phase of the locked global clock signal provided by PLL204, and optimizes the sampling edges to be used during the active mode. Meanwhile, the receivers in system202are also turned on to receive data at a partial data rate using the global clock signal provided by PLL204without any phase adjustments. Note that the eight transmitter/receiver pairs inFIG. 2are just for illustration purposes. In practice, different channels in a system can operate in partial-rate mode independently or jointly. For example, one transmitter-receiver pair can operate in the partial-rate mode while one or more other pairs are in standby and/or active modes.

During the partial-rate mode, the transmitter (for example transmitter256) transmits each data bit multiple times. In other words, one data bit is extended to occupy multiple unit intervals. For example, one data bit can occupy 2, 3, 4, or other number of unit intervals. As a result, receiver214does not need fine-tuned sampling edges to reliably detect such data bits. Instead, receiver214can use the rising or falling edge of the global clock to sample the incoming data bits, since each data bit is extended over multiple unit intervals. Note that a unit interval refers to the minimum time interval between condition changes of a data transmission signal, and may correspond to half a clock cycle in a double-date-rate (DDR) configuration or one clock cycle in a single-data-rate (SDR) configuration. A unit interval may also correspond to other fractional values of a clock cycle in other data-rate schemes. Although the examples presented in this disclosure are based on DDR operation, embodiments of the present invention can also be applied to systems with an SDR configuration.

After local phase-adjusting mechanisms, such as PLL216, have locked into a substantially optimal phase with respect to the incoming data, system202enters the active mode. In the active mode, the receivers and transmitters operate at the full data rate. The receivers detect incoming bits using the phase-adjusted local clock signals provided by the local, receiver-specific PLLs.

Note that in one embodiment, system202can be a memory module, and system242can be a memory controller.

TABLE 2 presents a set of exemplary power-consumption values and the amount of time for transitions between modes in a 6.25 Gb/s system configured to operate in a partial-rate transfer mode in accordance with on embodiment of the present invention.

As shown in TABLE 2, the power consumption in the standby mode is very low (about 2-4 mW), which means that the system can remain in the standby mode for a long time without consuming too much power. By contrast, the exemplary system shown inFIG. 1, while in standby mode, could consume 5-10 times the power (about 20 mW, see TABLE 1). In one embodiment, the system can perform data transfer at half or quarter rate while in the partial-rate mode. Further, because the global phase-locking mechanism is operational and remains locked-in, the system may commence data transfer quickly (e.g., after 15 ns) after the payload data is ready, which significantly reduces the data-transfer latency. Note that, because of the reduced effective data rate, the receiver circuits may still receive data even though the local, receiver-specific PLLs are not phase-locked relative to the data bits. That is, the reduced effective data rate allows the receivers to reliably sample the data bits within a substantially larger time window, which spans over two or more unit intervals, than during full data-rate operation. This enlarged time window extends sufficiently to accommodate the arbitrary phase of the global clock signal which is directly used to sample the data bits during the partial-rate mode.

The power-consumption vs. time diagram inFIG. 2illustrates the power savings due to the partial-rate transfer mode. Assume that after the first idle period, the transmitter system has data to transfer to the receiver system. In response, the receiver system transitions from the standby mode to the partial-rate mode. The time for this transition is tSR, which is approximately 15 ns, equivalent to 100 active-mode bit times. After the receiver system enters partial-rate mode, the transmitter system can start transferring data at half or quarter the normal data rate by transmitting each bit twice or four times. While data is being received at a reduced effective data rate in the partial-rate mode, the local, receiver-specific phase-adjusting mechanisms in the receiver system adjust the phase of their respective clock signals in preparation for the full-rate data transfer in the active mode. That is, data is received during the transition from partial-rate mode to full-rate active mode. After these phase-adjusting mechanisms lock into their respective clock signals, the receiver system enters the full-rate active mode, and the transmitter system starts transmitting data bits at the full rate.

It should be noted that the ability to receive at least some data prior to entering full data-rate active mode can be extremely helpful in certain types of systems, even though data is transferred between transmitter and receiver at a reduced effective data rate during partial-rate mode. For example, in a memory system, the first transmission after awaking from a reduced-power mode (which in one embodiment is the standby mode) is the communication of a fairly brief read command (or read request) from the memory controller to one or more memory devices. Thereafter, the memory devices typically perform a relatively long-latency core access operation (e.g., 40-100 nanoseconds (nS) in a dynamic random access memory device (DRAM)). Hence, the ability to transfer the memory read request during partial-rate mode may substantially reduce the data access latency. That is, a substantial portion of the system wake-up time (i.e., time to transition from reduced-power mode to full-rate active mode) may overlap with the core access time, since the system wake-up and core-access may be performed in parallel (concurrently) instead of sequentially.

Comparing the power-consumption diagram inFIG. 2with the one inFIG. 1, one can observe that the new standby mode replaces the previous power-down mode, and the partial-rate mode replaces the previous standby mode. The new standby mode's power consumption is just slightly higher than the near-zero power consumption in the previous power-down mode. The power consumption in the partial-rate mode is comparable to the power consumption incurred by the power-down-to-active transition in the system shown inFIG. 1. Furthermore, the system can now transfer data in the partial-rate mode, which effectively speeds up data transfer.

FIG. 3presents an exemplary timing diagram of a data signal and a set of data and edge sampling signals used in a double-data-rate (DDR) configuration in accordance with one embodiment of the present invention. In the active mode, two data bits are transferred in one clock cycle. Typically, the phase-adjusting mechanism at a receiver provides four sampling edges, a data clock signal (dclkP), an inversed data clock signal (dclkN), an edge clock signal (eclkP), and an inversed edge clock signal (eclkN). The phase-adjusting mechanisms continuously monitors the phase of these four clock signals, so their respective rising (or falling) edge is placed at the center of a data eye or at the transition edge between two data bits to provide reliable sampling. Note that, in all instances and embodiments herein, phase-adjusting mechanisms may be based on phase-locking loops or delay-locking loops. Other phase-adjusting mechanisms can also be used.

As illustrated inFIG. 3, during normal full-rate operation, each data bit occupies one unit interval, which is half of a clock cycle. The rising edges of dclkP and dclkN are placed in the middle of two consecutive data bits. For example, edges302and304sample data bits “A” and “B,” respectively. Edges310and312sample data bits “C” and “D,” respectively. As a result, data clock signals dclkP and dclkN can be used to sample two consecutive bits d0and d1.

The associated edge clock signals, eclkP and eclkN, sample the transition edge between two consecutive data bits. The edge value or edge sample is used by the phase-adjusting mechanism in conjunction with the values of the data bits (i.e., the data samples) captured immediately before and after the edge to determine whether the edge clock signals and, correspondingly, the data clock signals, are early or late. For example, rising edge306is used to sample the transition edge between data bits “A” and “B,” and rising edge308is used to sample the transition edge between data bits “C” and “D.” If the value sampled by edge306(i.e., edge value) is the same as preceding data the value sampled by edge302, but different from the succeeding data value (sampled by edge304), the sampling clocks are deemed to be early. Conversely, if the edge value matches the succeeding data value but not the preceding data value, the clocks are deemed to be late. The phase-adjusting mechanism continuously monitors the edge and data values, and adjusts the phase of the four clock signals to ensure that the data sampling edges remain at the center of a data eye.

Quarter-Rate Transfer Mode

In one embodiment, the transmitter system transmits each data bit consecutively four times during the partial-rate mode, thus effecting a quarter-rate transfer mode or quarter-rate mode. The effective data rate of the transfer is therefore a quarter of the normal rate.FIG. 4presents an exemplary timing diagram of a data signal and a pair of global clock signals used in a quarter-rate transfer mode in accordance with one embodiment of the present invention.

As illustrated inFIG. 4, a data bit is transmitted consecutively four times, over four unit intervals. Hence, the transmitter can emulate a transmission at one-fourth the full data rate. In the following description, an “interval” refers to one unit interval. For example, intervals “ABCD” carry the value of one data bit, and intervals “EFGH” carry the value of another data bit.

On the receiver side, the receiver uses the phase-locked (but not necessarily phase-adjusted) global signal and its complement as the data sampling signals. For example, global clock signal dclkP_G provides rising edges402and406, which are used to sample values at intervals “A” and “C.” Similarly, inverted global clock signal dclkN_G provides rising edges404and408, which are used to sample values at bit positions “B” and “D.” Collectively, these four rising edges, denoted as d00, d01, d10, and d11, provide four consecutive samples during the time occupied by one data bit, which extends over four intervals. The values detected by these two clock signals are denoted as “d0” and “d1,” as illustrated inFIG. 4. The value of d0corresponds to the values of intervals A, C, E, G, and so forth. The value of d1corresponds to the values of intervals B, D, F, H, and so forth.

In general, the receiver system samples four times a data bit which extends over four intervals, that is, twice with two consecutive rising edges of dclkP_G, and twice with two consecutive rising edges of dclkN_G. These four samples, when interleaved, provide four consecutive samples of a data bit. Note that the system does not need to adjust the phase of these sampling signals, since at least one sampling edge would fall substantially in the middle of a four-interval-long data bit. Typically, every data bit is sampled four times and the system can select the second or third sample as the main sampling point for a data bit. In the most extreme scenario, five or three sampling edges may fall within the same data bit due to signal drift or jitter. In such cases, the system can select the sampling edge in the middle (e.g., the second sampling edge if three sampling edges fall within one data bit, or the third sampling edge if five sampling edges fall within one data bit) as the main sampling point. This way, the system can ensure the best signal-detection margin both before and after that sampling point. Further details of the calibration process and how to select the sampling edge are provided in the description in conjunction withFIG. 6.

FIG. 5presents an exemplary block diagram for a receiver capable of operating in a quarter-rate transfer mode in accordance with one embodiment of the present invention. A receiver system can include a receive port502, an amplification circuit504, a group of samplers506,508,510, and512, a deserializer-clock generation module (DesClk)520, and two 2-to-16 deserializer518and522. DesClk520provides two sets of clock signals519and521to deserializers518and522, respectively. Also included in the receiver system are a phase-locking loop528, a 4×2 multiplexer530, and a partial-rate data processing module540.

During the active mode, receive port502receives a data stream at the normal data rate. The received data stream is then amplified by amplification circuit504, and is sampled by four samplers506,508,510, and512. In one embodiment, a respective sampler is a flip-flop triggered by a sampling edge. In this example, data samplers506and508are triggered by data sampling signals (dclkp, dclkN), which correspond to the sampling signals dclkP and dclkN inFIG. 3. Ideally, data sampling signals (dclkp, dclkN) are phase-adjusted to the data-eye midpoints of incoming data bits, and samplers506and508take samples at the center of two consecutive data eyes to produce two consecutive data bits, d0and d1. Similarly, edge samplers510and512are triggered by edge sampling signals (eclkP_L, eclkN_L), which correspond to the sampling signals eclkP and eclkN inFIG. 3.

In one embodiment, PLL528generates phase-adjusted local clock signals, which include two local data clocks (dclkP_L, dclkN_L), and two local edge clocks (eclkP_L, eclkN_L). PLL528generates these local clock signals based on a pair of global clock signals (clkP_G, clkN_G), which correspond to the output of the phase-locking mechanism204in system202as illustrated inFIG. 2. Note that, during the active mode, PLL528may continuously adjust the phase of the four local clock signals based on a phase control signal, which can be derived from the relative phase information of the data and edge samples.

4×2 multiplexer530, which is controlled by a partial-rate enable signal532, selects between the global clock signals (clkP_G, clkN_G) and the local data clock signals (dclkP_L, dclkN_L). When partial-rate enable signal532is set, multiplexer530selects the global clock signals (clkP_G, clkN_G) as the data sampling signals (dclkp, dclkN), which are used to trigger flip-flops506and508. During the active mode, partial-rate enable signal532is unset and multiplexer530selects the local data clock signals (dclkP_L, dclkN_L) as the data sampling signals (dclkp, dclkN).

The outputs of data samplers506and508are coupled to 2-to-16 deserializer518. Virtually any circuit for reorganizing an incoming sequence of 2-bit values to an outgoing sequence of m-bit values (m=16 in this example) may be used to implement deserializer518. For example, in one embodiment, deserializer518is based on a tree of 1:2 demultiplexers clocked by a set of divider-chain clock signals519(dclkp, dclkP/2, dclkP/4, dclkP/8), wherein dclkP/n denotes a clock signal the frequency of which is equal to the frequency of dclkP divided by n. DesClk520derives clock signals519based on dclkP and/or dclkN.

Note that in the active mode, DesClk520derives clock signals519based on the local data clock signals (dclkP_L, dclkN_L), which are the outputs of 4×2 multiplexer530when partial-rate enable signal532is unset (i.e., deasserted). In the partial-rate mode, DesClk520derives clock signals519based on the global clock signals (clkP_G, clkN_G), which are the outputs of 4×2 multiplexer530when the partial-rate enable signal532is set (i.e., asserted). In this example, the output of deserializer518is a 16-bit wide data stream, rxdat[15:0]. DesClk520also generates a receiver clock signal rxclk which can be used to sample the deserialized data rxdat[15:0].

DesClk520further generates a set of divider-chain clock signals521to clock deserializer522, which converts the two edge bits e0and e1from edge samplers510and512into a 16-bit wide edge data stream edat[15:0].

In partial-rate mode, the operation of the edge samplers510and512, and deserializer522are the same as in the active mode, since they are clocked by the same local edge clock signals (eclkP_L, eclkN_L). The data samplers506and508, and deserializer518are clocked by the global clocks (clkP_G, clkN_G). Meanwhile, PLL528continuously adjusts the phase of (dclkP_L, dclkN_L) and (eclkP_L, eclkN_L) in preparation of the active mode. Although data samplers506and508, deserializer518, and part of DesClk520are shared between the partial-rate mode and active mode in this embodiment, it is also possible to provide a separate set of samplers in similar configuration for the partial-rate operation.

Note that in the partial-rate mode, each bit is transmitted four times in the data stream received at receive port502. Hence, the deserialized data output rxdat[15:0] typically contains 3, 4, or 5 identical bits which are adjacent to each other, depending on the phase of global clocks (clkP_G, clkN_G) relative to the phase of the serial bits in the incoming data stream. For example, rxdat[2]-rxdat[5] can be identical and carry the same data bit which is transmitted four times. In other words, the 16-bit wide data output rxdat[15:0] only carries four bits of useful information. Therefore, partial-rate data processing module540selects four bits out of the 16 bits of rxdat[15:0] as the received data bits during the partial-rate mode. Note that partial-rate processing module540is controlled by partial-rate enable signal532. In the active mode when partial-rate enable signal532is unset, partial-rate data processing module540allows the entire 16-bit-wide rxdat[15:0] to pass through as received data.

In one embodiment, the receiver system performs a calibration process before commencing payload data transfer. This calibration process allows the system to determine the amount of logical shift to apply to rxdat[15:0], so that the received words are aligned with the transmitted words.FIG. 6illustrates an exemplary calibration process in a quarter-rate transfer mode in accordance with an embodiment of the present invention. During the calibration process, the transmitter typically transmits a unique pattern, which in this example is a 16-bit long stream “0000001111000000.” Assume that the transmission channel introduces an arbitrary shift to the received stream. For illustration purposes, the received 16-bit wide parallel word rxdat[15:0] could be “0000000000011110.”

The system then selects the second “1,” which corresponds to position rxdat[3] and is indicated by a bold font, as the reference sampling point. The system further applies a logical five-bit left shift to rxdat[15:0] and generates a shifted 16-bit-wide word rxshift[15:0]. As a result, the received second “1” is at position rxshift[8] and is aligned with the position of the second “1” in the transmitted pattern. Note that, after the five-bit left shift, the system uses bit positions rxshift[14], rxshift[10], rxshift[6], and rxshift[2] as the four sampling points, since every 16-bit word contains four meaningful bits in the quarter-rate mode.

The example below is provided to illustrate how the five-bit left shift allows the system to align its received words with the transmitted words. Assume that the transmitter is to transmit a payload data stream “ABCDEFGH.” The actual transmitted 16-bit words in the quarter-rate mode are “AAAABBBBCCCCDDDD” and “EEEEFFFFGGGGHHHH,” since every bit is transmitted four times. Before the five-bit shift, the received parallel words rxdat[15:0] are “00000AAAABBBBCCC,” “CDDDDEEEEFFFFGGG,” and “GHHHH00000000000.” The system then applies a five-bit left shift to rxdat[15:0], which results in two words in rxshift[15:0]: “AAAABBBBCCCCDDDD” and “EEEEFFFFGGGGHHHH.” Note that the system selects the second bit of every four-bit group, which is underlined, as the sampling point for each data bit. This calibration process allows the receiver system to recover the original word “ABCDEFGH.”

The above calibration process allows a drift of up to six unit intervals in either direction (early or late) to be detected and compensated for with a shifter block which uses rxdat[15:0] as the input and produces rxshift[15:0] as the output. The bits in rxshift[15:0] that are shifted out are to be merged into the previous or next rxshift[15:0] word. Furthermore, the above calibration process can be performed by partial-rate data processing module540.

FIG. 7presents an exemplary block diagram for a transmitter capable of operating in a partial-rate transfer mode in accordance with one embodiment of the present invention. Transmitter700typically includes a 16-to-2 serializer702, a serializer clock generator (SerClk)720, a 2×1 multiplexer, and a transmission driver604. During operation, transmitter700receives the payload data txdat[15:0] in parallel format. Serializer702converts the 16-bit-wide parallel data into two serial streams, d0and d1. In one embodiment, serializer702includes a tree of 2×1 multiplexers and is clocked by a set of divider-chain clock signals generated by SerClk720. 2×1 multiplexer704, which is clocked by a pair of clocks (clkP, clkN), further multiplexes d0and d1in a DDR fashion. Transmission driver604then transmits the output of 2×1 multiplexer704, which is a serial bit stream, onto a transmission medium.

During the partial-rate mode, each 16-bit-wide word txdat[15:0] contains four meaningful bits, wherein each meaningful bit is transmitted four times. For example, txdat[15:12], txdat[11:8], txdat[7:4], and txdat[3:0] each contains four identical bits.

Half-Rate Transfer Mode

In one embodiment, the transmitter system transmits each data bit consecutively twice during the partial-rate mode, thus effecting a half-rate transfer mode or half-rate mode, in which the effective data rate of the transfer is half of the full data rate.FIG. 8presents an exemplary timing diagram of a data signal and a set of quadrature global clock signals used in a half-rate transfer mode in accordance with one embodiment of the present invention.

As illustrated inFIG. 8, a data bit is transmitted consecutively twice, over two unit intervals. Hence, the transmitter can emulate a transmission at half the full data rate. For example, intervals “AB” carry the value of one data bit, and intervals “CD” carry the value of another data bit. On the receiver side, the receiver uses a set of phase-locked (but not necessarily phase-adjusted) global quadrature clock signals as the data and edge sampling signals. These quadrature clock signals are separated by 90° in phase. For example, global clock signals dclkP_G and eclkP_G provide two rising edges802and804, which can be used to sample twice the value at interval “A.” Similarly, global clock signals dclkN_G and eclkN_G provide two rising edges806and808, which can be used to sample twice the value at interval “B.” Collectively, these four rising edges provide four consecutive samples during the time occupied by one data bit, which extends over two intervals. Note that in some embodiment the receiver system is only provided with a pair global clock signals (dclkP_G, dclkN_G). A quadrature clock-generation mechanism can be used to generate the complete set of quadrature clock signals by using, for example, delay-locking loops (DLLs).

The values detected by these four clock signals are denoted as “d0,” “e0,” “d1,” and “e1,” as illustrated inFIG. 8. The value of d0corresponds to the values of intervals A, C, E, G, and so forth. The value of e0corresponds to the values detected substantially between intervals A and B, C and D, E and F, G and H, and so forth. The value of d1corresponds to the values of intervals B, D, F, H, and so forth. The value of e1corresponds to the values detected substantially between intervals B and C, D and E, F and G, and so forth.

In general, during the half-rate mode, the receiver system samples four times a data bit which extends over two intervals with the four global clock signals (dclkP_G, dclkN_G, eclkP_G, eclkN_G). These four samples, when interleaved, provide four consecutive samples of a data bit. Note that the system does not need to adjust the phase of these sampling signals, since at least one sampling edge would fall substantially in the middle of a two-interval-long data bit.

Typically, every data bit is sampled four times by the quadrature global clocks, and the system can select the second or third sample as the main sampling point for a data bit. In the most extreme scenario, five or three sampling edges may fall within the same data bit due to signal drift or jitter. In such cases, the system can select the sampling edge in the middle (e.g., the second sampling edge if three sampling edges fall within one data bit, or the third sampling edge if five sampling edges fall within one data bit) as the main sampling point. This way, the system can ensure the best signal-detection margin both before and after that sampling point. Further details of the calibration process and how to select the sampling point are provided in the description in conjunction withFIG. 10.

FIG. 9presents an exemplary block diagram of a receiver capable of operating in a half-rate transfer mode in accordance with one embodiment of the present invention. A receiver system can include a receive port902, an amplification circuit504, a group of samplers906,908,910, and912, a deserializer-clock generation module (DesClk)920, and two 2-to-16 deserializers918and922. DesClk920provides two sets of clock signals919and921to deserializers918and922, respectively. Also included in the receiver system are a phase-locking loop928, an 8×4 multiplexer930, and a partial-rate data processing module940.

During the active mode, receive port902receives a data stream at the normal data rate. The received data stream is then amplified by amplification circuit904, and is sampled by four samplers906,908,910, and912. In one embodiment, a respective sampler is a flip-flop triggered by a sampling edge. In this example, data samplers906and908are triggered by data sampling signals (dclkp, dclkN), which correspond to the sampling signals dclkP and dclkN inFIG. 3. Ideally, data sampling signals (dclkp, dclkN) are phase-adjusted to the data-eye midpoints of incoming data bits, and samplers906and908take samples at the center of two consecutive data eyes to produce two consecutive data bits, d0and d1. Similarly, edge samplers910and912are triggered by edge sampling signals (eclkp, eclkN), which correspond to the sampling signals eclkP and eclkN inFIG. 3. Ideally, edge sampling signals (eclkp, eclkN) are phase-adjusted to the incoming data bits, and samplers910and912take samples at the transition edges between two consecutive data bits.

In one embodiment, PLL928generates phase-adjusted local clock signals, which include the two local data clocks (dclkP_L, dclkN_L), and two local edge clocks (eclkP_L, eclkN_L). PLL928generates these local clock signals based on a pair of global clock signals (clkP_G, clkN_G), which correspond to the output of the phase-locking mechanism204in system202as illustrated inFIG. 2. Note that, during the active mode, PLL928may continuously adjust the phase of these four local clock signals based on a phase control signal, which can be derived from the relative phase information of the data and edge samples.

8×4 multiplexer530, which is controlled by a partial-rate enable signal932, selects between the global clock signals (dclkP_G, dclkN_G, eclkP_G, eclkN_G) and the local clock signals (dclkP_L, dclkN_L, eclkP_L, eclkN_L). When partial-rate enable signal932is set, multiplexer930selects the global clock signals (dclkP_G, dclkN_G, eclkP_G, eclkN_G) as the data and edge sampling signals for samplers906,908,910, and912. During the active mode, partial-rate enable signal932is unset, and multiplexer930selects the local clock signals (dclkP_L, dclkN_L, eclkP_L, eclkN_L) as the sampling signals.

Note that the global clock signals (clkP_G, clkN_G) are used as the data sampling signals during the partial-rate mode. A pair of corresponding global edge clock signals (eclkP_G, eclkN_G) are used for edge detection by samplers910and912. Global edge clock signals (eclkP_G, eclkN_G) can be locally generated based on (clkP_G, clkN_G) with, for example, a DLL or an equivalent phase-shifting circuit with zero standby power consumption and a quick turn-on time in the partial-rate mode.

The outputs of data samplers906and908are coupled to 2-to-16 deserializer918. Virtually any circuit for reorganizing an incoming sequence of 2 bit values to an outgoing sequence of m-bit values (m=16 in this example) may be used to implement deserializer918. For example, in one embodiment, deserializer918is based on a tree of 1:2 demultiplexers clocked by a set of divider-chain clock signals919(dclkp, dclkP/2, dclkP/4, dclkP/8), wherein dclkP/n denotes a clock signal the frequency of which is equal to the frequency of dclkP divided by n. DesClk920derives clock signals919based on dclkP and/or dclkN.

Note that in the active mode, DesClk920derives clock signals919based on the local clock signals (dclkP_L, dclkN_L, eclkP_L, eclkN_L), which are the outputs of 8×4 multiplexer930when partial-rate enable signal932is unset (i.e., deasserted). In the partial-rate mode, DesClk920derives clock signals919based on the global clock signals (dclkP_G, dclkN_G, eclkP_G, eclkN_G), which are the outputs of 8×4 multiplexer930when the partial-rate enable signal932is set (i.e., asserted). In this example, the output of deserializer918is a 16-bit wide data stream, rxdat[15:0]. DesClk920also generates a receiver clock signal rxclk which can be used to sample the deserialized data rxdat[15:0].

DesClk920further generates a set of divider-chain clock signals921to clock deserializer922, which converts the two edge bits e0and e1from edge samplers910and912into a 16-bit wide edge data stream edat[15:0]. Note that, in partial-rate mode, the system uses both rxdat[15:0] and edat[15:0] to determine a reliable sampling point for a data bit which extends over two unit intervals.

In the embodiment illustrated inFIG. 9, the samplers906,908,910, and912, data deserializer918, edge deserializer922, and DesClk920are shared between the active mode and partial-rate mode. It is also possible to provide a separate set of samplers in similar configuration for the partial-rate operation.

Note that in the partial-rate mode, each bit is transmitted twice in the data stream received at receive port902. Hence, the deserialized data output rxdat[15:0] typically contains 1, 2, or 3 identical bits which are adjacent to each other, depending on the phase of global clocks (clkP_G, clkN_G) relative to the phase of the serial bits in the incoming data stream. For example, rxdat[2]-rxdat[3] can be identical and carry the same data bit which is transmitted twice. Similarly, edat[15:0] can contain 1, 2, or 3 identical bits which correspond to the same duplicated data bit. In other words, the 16-bit wide data output rxdat[15:0] and edge output edat[15:0] only carry eight bits of useful information. Therefore, partial-rate data processing module940selects four bits out of the 32 bits of rxdat[15:0] and edat[15:0] as the received data bits during the partial-rate mode. Note that partial-rate processing module940is controlled by partial-rate enable signal932. In the active mode when partial-rate enable signal932is unset, partial-rate data processing module940allows the entire 16-bit-wide rxdat[15:0] to pass through as received data.

In one embodiment, the receiver system performs a calibration process before commencing payload data transfer. This calibration process allows the system to determine the amount of logical shift to apply to rxdat[15:0] or edat[15:0], so that the received words are aligned with the transmitted words.FIG. 10illustrates an exemplary calibration process in a quarter-rate transfer mode in accordance with an embodiment of the present invention. During the calibration process, the transmitter typically transmits a unique pattern, which in this example is a 16-bit long stream “0000000110000000.” Assume that the transmission channel introduces an arbitrary shift to the received stream. For illustration purposes, the received 16-bit wide parallel word rxdat[15:0] could be “0000110000000000,” and edat[15:0] could be “0001100000000000.”

The system then interleaves rxdat[15:0] and edat[15:0], and determines to use the second “1” in edat[15:0], which is at position edat[11], as the sampling point, since it is the third sample in the four continuous samples of “1.” The system further applies a logical four-bit right shift to edat[15:0] and generates a shifted 16-bit-wide word rxshift[15:0]. As a result, the received second “1” is at position rxshift[7] and is aligned with the position of the second “1” in the transmitted pattern. After the four-bit right shift, the system uses bit positions rxshift[15], rxshift [13], rxshift[11], rxshift[9], rxshift[7], rxshift[5], rxshift[3], and rxshift[1] as the eight sampling points, since every 16-bit word contains eight meaningful bits in the half-rate mode.

The example below is provided to illustrate how the four-bit right shift allows the system to align its received words with the transmitted words. Assume that the transmitter is to transmit a payload data stream “ABCDEFGH.” The actual transmitted 16-bit word in the half-rate mode is “AABBCCDDEEFFGGHH,” since every bit is transmitted twice. Before the four-bit right shift, the received parallel words edat[15:0] are “000000000000AABB” and “CCDDEEFFGGHH0000.” The system then applies a four-bit right shift to edat[15:0], which results in one word in rxshift[15:0]: “AABBCCDDEEFFGGHH.” Note that the system selects the first bit of every two-bit group, which is underlined, as the sampling point for each data bit. This calibration process allows the receiver system to recover the original word “ABCDEFGH.”

The above calibration process allows a drift of up to eight bit times in either direction (early or late) to be detected and compensated for with a shifter block which uses rxdat[15:0] or edat[15:0] as the input and produces rxshift[15:0] as the output. The bits in rxshift[15:0] that are shifted out are to be merged into the previous or next rxshift[15:0] word. Furthermore, the above calibration process can be performed by partial-rate data processing module940.

Partial-Rate Operation with Multiplicated Global Clock Signals

Embodiments of the present invention can be used in transmitter or receiver systems with multiplicated global clock signals.FIG. 11illustrates a number of transmitter-receiver pairs with a resonant clock-distribution network capable of operating in a partial-rate transfer mode in accordance with one embodiment of the present invention. A global clock-distribution mechanism1184distributes a low-frequency global clock signal to both systems1102and1142. System1102includes a phase-locking and frequency-multiplication mechanism1104, a set of inductors1138,1134, and1136, transmitters1112,1118,1122, and1128, receivers1114,1120,1124, and1130, and local, receiver-specific phase-adjusting mechanisms1116,1121,1126, and1132. Similarly, system1142includes a phase-locking and frequency-multiplication mechanism1144, a set of inductors1182,1178, and1180, transmitters1156,1162,1168, and1174, receivers1152,1158,1164, and1174, and local, receiver-specific phase-adjusting mechanisms1154,1160,1166, and1172. The transmitters in system1102are coupled to the receivers in system1142, and vice versa.

Since the configurations of system1142is substantially similar to that of system1102, the following description is directed to system1102and applies also to system1142. During operation, global clock-distribution mechanism1184delivers a low-frequency clock signal to system1102. This low-frequency clock signal is received by phase-locking and frequency-multiplication mechanism1104. In one embodiment, phase-locking and frequency-multiplication mechanism1104includes a PLL with frequency-multiplication capability. For example, PLL1104can be configured to lock into a frequency that is eight times the frequency of the received global signal. If the low-frequency global clock signal is at 400 MHz, the output of PLL1104can be at 3.2 GHz.

The output of PLL1104is then distributed to the transmitters and receivers through a resonant clock-distribution network, which includes inductors1134,1136, and1138. The inductance of these three inductors are chosen to match with the inherent impedance of the clock-distribution network, so that the entire clock-distribution network exhibits a resonant frequency that is substantially the same as the frequency of the output of PLL1104. This way, system1104can transmit and receive data at a much higher data rate while the global clock distribution mechanism1102can operate at a low frequency.

Systems1102can operate in three modes: standby, partial-rate, and active. In the standby mode, transmitters1112,1118,1122, and1128, receivers1114,1120,1124, and1130, and local receiver-specific phase-adjusting mechanisms1116,1121,1126, and1132are turned off. However, clock-multiplication PLL1104remains operational, and the multiplied global clock signal is continuously distributed through the resonant clock-distribution network in system1102.

In the partial-rate mode, the transmitters, receivers, and local receiver-specific phase-adjusting mechanism are turned on. The transmitters and receivers operate at a partial data rate, as described previously in conjunction withFIG. 5andFIG. 10. Meanwhile, each local receiver-specific phase-adjusting mechanism adjusts the phase of a set of quadrature clock signals in preparation for the active-mode data transfer which is at the full data rate.

After the local, receiver-specific phase-adjusting mechanisms have locked the local quadrature clock signals into the optimal phase, system1102enters the active mode and begins data transfer at the full data rate.

The partial-rate mode is particularly useful for system1102, because the global clock signal has a fixed frequency. In system1102, it is difficult to obtain a slower clock for power-saving purposes, because the intra-system clock distribution system is tuned to a particular frequency. By transferring data at a partial data rate, system1102can reduce the inter-mode switching overhead and reduce data-transfer latency.

Although the partial-rate operation is described in the context of DDR communication channels, the partial-rate data transfer mechanism can also be used for single data-rate (SDR) communication channels where a period of the clock signal corresponds to one unit interval.

The components of the partial-rate data transfer mechanism described above can include any collection of computing components and devices operating together. The components of the partial-rate data transfer mechanism can also be components or subsystems in a larger computer system or network. Components of a partial-rate data transfer mechanism can also be coupled among any number of components (not shown), for example, buses, controllers, memory devices, and data input/output (I/O) devices, in any number of combinations. Many of these system components may be situated on a common printed circuit board or integrated circuit, or may be integrated in a system that includes several printed circuit boards or ICs that are coupled together in a system, for example, using connector and socket interfaces such as those employed by personal computer motherboards and dual inline memory modules (“DIMM”). In other examples, complete systems may be integrated in a single package housing using a system in package (“SIP”) type of approach. Integrated circuit devices may be stacked on top of one another and utilize wire bond connections to effectuate communication between devices or may be integrated on a single planar substrate in the package housing.

Further, functions of the partial-rate data transfer mechanism can be distributed among any number/combination of other processor-based components. The partial-rate data transfer mechanism described above can include, for example, various DRAM systems. As examples, the DRAM memory systems can include DDR systems like DDR SDRAM, as well as DDR2 SDRAM, DDR3 SDRAM, and other DDR SDRAM variants, such as Graphics DDR (“GDDR”) and further generations of these memory technologies, including GDDR2 and GDDR3, but are not limited to these memory systems.

It should be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and HLDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media).