Deep trench isolation structures resistant to cracking

A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

BACKGROUND

Semiconductor image sensors are operated to sense light. Typically, the semiconductor image sensors include Complementary Metal-Oxide-Semiconductor (CMOS) Image Sensors (CIS) and Charge-Coupled Device (CCD) sensors, which are widely used in various applications such as Digital Still Camera (DSC), mobile phone camera, Digital Video (DV) and Digital Video Recorder (DVR) applications. These semiconductor image sensors utilize an array of image sensor elements, with each image sensor element including a photodiode and other elements, to absorb light and convert the sensed light into digital data or electrical signals.

Front Side Illumination (FSI) CMOS image sensors and Backside Illumination (BSI) CMOS image sensors are two types of CMOS image sensors. The FSI CMOS image sensors are operable to detect light projected from their front side while the BSI CMOS image sensors are operable to detect light projected from their backside. When light projected into the FSI CMOS image sensors or the BSI CMOS image sensors, photoelectrons are generated and then are sensed by light-sensing devices in pixels of the image sensors. The more the photoelectrons are generated, the more superior quantum efficiency (QE) the image sensor has, thus improving the image quality of the CMOS image sensors.

However, while CMOS image sensor technologies are rapidly developed, CMOS image sensors with higher Quantum Efficiency (QE) are desired.

DETAILED DESCRIPTION

A Deep Trench Isolation (DTI) structure in a semiconductor substrate and the method of forming the same are provided in accordance with various embodiments. The intermediate stages of forming the D/TI structure are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In accordance with some embodiments of the present disclosure, the DTI structure forms a grid, and includes a high-reflectivity metallic material and a void in the high-reflectivity metallic material. Accordingly, with the use of the high-reflectivity metallic material, the quantum efficiency of the image sensors is improved. On the other hand, with the void being formed, buffers are provided to absorb the stress generated in thermal cycles, which stress is due to the significant difference between the high-reflectivity metallic material and the semiconductor substrate. Accordingly, the possibility of cracking is reduced. The DTI structure may be used for Backside Illumination (BSI) Complementary Metal-Oxide-Semiconductor (CMOS) image sensors or Front Side Illumination (FSI) CMOS image sensors, and may be used in other application in which deep trench isolation regions are used.

FIGS. 1 through 12illustrate the cross-sectional views of intermediate stages in the formation of a DTI structure in accordance with some embodiments of the present disclosure. The steps shown inFIGS. 1 through 12are also reflected schematically in the process flow200as shown inFIG. 18. The DTI regions may be used in image sensor chips (such as FSI image sensor chips or BSI image sensor chips) in accordance with some embodiments of the present disclosure.

FIG. 1illustrates the formation of an initial structure of image sensor chip20, which may be a part of wafer22that includes a plurality of image sensor chips20therein. The respective process is illustrated as process202in the process flow shown inFIG. 18. Image sensor chip20includes semiconductor substrate24. In accordance with some embodiments of the present disclosure, semiconductor substrate24is a crystalline silicon substrate. In accordance with other embodiments of the present disclosure, semiconductor substrate24includes an elementary semiconductor such as germanium; a compound semiconductor including silicon carbon, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates such as multi-layered or gradient substrates may also be used. Throughout the description, major surface24A of substrate24is referred to as a front surface of semiconductor substrate24, and surface24B is referred to as a back surface of semiconductor substrate24. Surfaces24A and24B may be on (100) or (001) surface planes.

Isolation regions32, which are alternatively referred to as Shallow Trench Isolation (STI) regions32, are formed to extend into semiconductor substrate24to define active regions for circuits. In accordance with some embodiments of the present disclosure, as shown in the top view inFIG. 14, STI regions32may form a grid including horizontal strip portions and vertical strip portions crossing each other.

Referring back toFIG. 1, image sensors26are formed extending from front surface24A into semiconductor substrate24. The formation of image sensors26may include implantations. Image sensors26are configured to convert light signals (photons) to electrical signals. Image sensors26may be photo-sensitive Metal-Oxide-Semiconductor (MOS) transistors, photo-sensitive diodes, or the like. Throughout the description, Image sensors26are alternatively referred to as photo diodes26, although they may be other types of image sensors. In accordance with some embodiments of the present disclosure, photo diodes26form an image sensor array.

FIG. 1also illustrates pixel units30, which may include at least portions in the active regions defined by STI regions32.FIG. 13illustrates a circuit diagram of an example of pixel unit30. In accordance with some embodiments of the present disclosure, pixel unit30includes photo diode26, which has an anode coupled to the electrical ground GND, and a cathode coupled to a source of transfer gate transistor134. The drain of transfer gate transistor134may be coupled to a drain of reset transistor138and a gate of source follower142. Reset transistor138has a gate coupled to a reset line RST. A source of reset transistor138may be coupled to pixel power supply voltage VDD. Floating diffusion capacitor140may be coupled between the source/drain of transfer gate transistor134and the gate of source follower142. Reset transistor138is used to preset the voltage at floating diffusion capacitor140to VDD. A drain of source follower142is coupled to a power supply voltage VDD. A source of source follower142is coupled to row selector144. Source follower142provides a high-impedance output for pixel unit30. The row selector144functions as the select transistor of the respective pixel unit30, and the gate of the row selector144is coupled to select line SEL.

Referring back toFIG. 1, a transistor is illustrated as an example of the devices (such as134,138,142, and144inFIG. 13) in pixel unit30. For example, transfer gate transistor134is illustrated inFIG. 1. In accordance with some embodiments of the present disclosure, each of photo diodes26is electrically coupled to a first source/drain region of transfer gate transistor134, which includes gate28and gate dielectric31. Gate dielectric31is in contact with front surface24A of substrate24. The first source/drain region of transfer gate transistor134may be shared by the corresponding connecting photo diode26. Floating diffusion capacitor140is formed in substrate24, for example, through implanting into substrate24to form a p-n junction, which acts as floating diffusion capacitor140. Floating diffusion capacitor140may be formed in a second source/drain region of transfer gate transistor134, and hence one of the capacitor plates of floating diffusion capacitor140is electrically coupled to the second source/drain region of transfer gate transistor134. Photo diodes26and the respective transfer gate transistors134and floating diffusion capacitors140in the same active region form pixel units30as also marked inFIG. 1.

Contact Etch Stop Layer (CESL)40is formed on substrate24and transistors such as transfer gate transistors134. Inter-Layer dielectric (ILD)42is formed over CESL40. CESL40may be formed of silicon oxide, silicon nitride, silicon carbo-nitride, or the like, or the multi-layers thereof. CESL40may be formed using a conformal deposition method such as Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD), for example. ILD42may include a dielectric material formed using, for example, Flowable Chemical Vapor Deposition (FCVD), spin-on coating, CVD, or another deposition method. ILD42may also be formed of an oxygen-containing dielectric material, which may be an oxide such as Tetra Ethyl Ortho Silicate (TEOS) oxide, a Plasma-Enhanced CVD (PECVD) oxide (such as SiO2), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), or the like.

Front-side interconnect structure44is formed over semiconductor substrate24. Front-side interconnect structure44is used to electrically interconnect the devices in image sensor chip20. Front-side interconnect structure44includes dielectric layers46, and metal lines48and vias50in dielectric layers46. Throughout the description, the metal lines48in a same dielectric layer46are collectively referred to as being a metal layer. Front-side interconnect structure44may include a plurality of metal layers. In accordance with some embodiments of the present disclosure, dielectric layers46include low-k dielectric layers. The low-k dielectric layers have low k values, for example, lower than about 3.0. One or more passivation layer52is formed over dielectric layers46. Passivation layers52may be formed of non-low-k dielectric materials having k values equal to or greater than about 3.8. In accordance with some embodiments of the present disclosure, passivation layers52include a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.

Referring toFIG. 2, wafer22is flipped upside down. A backside grinding is performed to grind back surface24B (FIG. 1) to thin semiconductor substrate24. The resulting back surface is referred to as24B′ inFIG. 2. The thickness of substrate24may be reduced to smaller than about 10 μm, or smaller than about 5 μm, for example. With semiconductor substrate24having a small thickness, light can penetrate from back surface24B′ into semiconductor substrate24, and reach photo diodes26.

In accordance with some embodiments of the present disclosure, etching mask54is formed on the back surface24B′ of semiconductor substrate24. The respective process is illustrated as process204in the process flow shown inFIG. 18. In accordance with some embodiments of the present disclosure, etching mask54includes a hard mask, which may be formed of silicon nitride, titanium nitride, or the like. A pad layer (not shown) may also be formed underlying the hard mask. The pad layer may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process or a deposition process such as Chemical Vapor Deposition (CVD). The pad layer may buffer the stress of the hard mask. In accordance with some embodiments of the present disclosure, hard mask54is formed of silicon nitride, for example, using Low-Pressure Chemical Vapor Deposition (LPCVD). In accordance with other embodiments, hard mask54is formed using thermal nitridation of silicon, Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like. A photo resist (not shown) may be formed on hard mask54and then patterned, and hard mask54is patterned using the photo resist as an etching mask. In a top view of the structure shown inFIG. 2, the patterned etching mask54may include a plurality of discrete blocks arranged as an array, and the spaces between the discrete blocks form a grid.

Next, an etching process is performed to form the structure shown inFIG. 3. The respective process is illustrated as process206in the process flow shown in FIG.18. The etching process may include a wet etching process, which may be performed using KOH, Tetra Methyl Ammonium Hydroxide (TMAH), or the like as an etchant. Since the etching rates of semiconductor substrate24on different surface planes are different from each other, slant straight surfaces56A are formed, for example, on (111) surface planes, which have tilt angle β equal to about 54.7 degrees. Recesses58are formed to extend into semiconductor substrate24.

With the proceeding of the etching of semiconductor substrate24, straight surfaces56A are recessed, and opposite surfaces56A facing the same recess58eventually meet with each other to have a V-shape. In accordance with some embodiments of the present disclosure, etching mask54is removed after recesses58start extending directly underlying etching mask54, followed by another wet etching to further extend recesses58down until the top portions of semiconductor substrate24form pyramids. In accordance with other embodiments, etching mask54is consumed during the wet etching so that a single wet etching process may result in the structure as shown inFIG. 3. In accordance with some embodiments of the present disclosure, etching mask54is removed when recesses58start extending directly underlying etching mask54, and no more etching of substrate24is performed after etching mask54is removed.

After the etching, pyramids56are formed, with each of pyramids including four sides. Each of the four sides has a triangular shape. In accordance with other embodiments, instead of having pyramid shapes, pseudo pyramids are formed, which include small planar platforms at the top, which planar platforms are formed since the portions of substrate24directly underlying etching mask54are not fully etched. Accordingly, the resulting structure will have a trapezoidal cross-sectional view shape. In subsequent discussion, pyramids are used as examples, and other shapes of the top portions of substrate24are contemplated. When viewed from top, pyramids (or pseudo pyramids) may form an array.

Next, an etching process is performed to form trenches60. The respective process is illustrated as process208in the process flow shown inFIG. 18. The etching is performed through an anisotropic etching process, so that the sidewalls of trenches60are straight and vertical, wherein the sidewalls are perpendicular to major surface24A of substrate24. Trenches60may also be slightly tapered, and hence the sidewalls of trench60are substantially perpendicular to (and slightly tilted) major surface24A of substrate24. For example, the angle α may be greater than about 88 degrees and smaller than 90 degrees. In accordance with some embodiments of the present disclosure, the etching is performed through a dry etching method including, and not limited to, Inductively Coupled Plasma (ICP), Transformer Coupled Plasma (TCP), Electron Cyclotron Resonance (ECR), Reactive Ion Etch (RIE), and the like. The process gases include, for example, fluorine-containing gases (such as SF6, CF4, CHF3, NF3), Chlorine-containing gases (such as Cl2), Br2, HBr, BCl3, and/or the like. When viewed from top of wafer22, trenches60form a grid. Furthermore, trenches60may overlap STI regions32, which also form a grid. Trenches60may be spaced apart from the respective underlying STI regions32by a small distance, for example, smaller than about 0.5 μm.

In accordance with some embodiments of the present disclosure, depth D1of trenches60is in the range between about 1 μm and about 10 μm. Width W1of trenches60may be in the range between about 0.1 μm and about 0.3 μm. Aspect ratio D1/W1of trench60may be greater than about 5, or greater than about 10 or higher, for example, between about 10 and 20. In accordance with some embodiments of the present disclosure, the bottom surfaces of trenches60are rounded and have a U-shape or a V-shape in the cross-sectional view.

FIG. 5illustrates the formation of dielectric layer62. The respective process is illustrated as process210in the process flow shown inFIG. 18. In accordance with some embodiments of the present disclosure, dielectric layer62comprises silicon oxide. The formation of dielectric layer62may be achieved through a non-conformal and none bottom-up deposition method, so that recesses58(FIG. 4) are fully filled. Voids (air gaps)64are formed in trenches60, and are sealed by dielectric layer62. For example, dielectric layer62may be formed using High-Density Plasma (HDP) Chemical Vapor Deposition (CVD). The top ends of voids64may be higher than the top ends of pyramids56in accordance with some embodiments. The thickness T1of the sidewall portions of dielectric layer62in trenches60may be in the range between about 10 Å and about 200 Å, wherein thickness T1may be measured at a level in the middle between the bottom of trenches60and the top of pyramids56. In accordance with some embodiments of the present disclosure, a planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process is performed. In accordance with alternative embodiments of the present disclosure, no planarization process is performed on dielectric layer62.

FIG. 6illustrates the opening of dielectric layer62in order to expose voids64. The respective process is illustrated as process212in the process flow shown inFIG. 18. In accordance with some embodiments of the present disclosure, the opening process includes a dry etch or a wet etch process. For example, when dry etch is used, a mixed gas of NF3and NH3or a mixed gas of HF and NH3may be used. When wet etch is used, an HF solution may be used. The etch may be performed without any hard mask, and all top surfaces of dielectric layer62are exposed to the etchant. Since the portions of dielectric layer62directly overlying voids64are thinner than the portions directly over pyramids56, although the etching is performed without an etching mask, voids64are exposed, while some other portions of dielectric layer62remain to cover pyramids56. In accordance with some embodiments of the present disclosure, voids64have curved edges at top, wherein dashed lines65are drawn to show the possible shapes. The subsequently formed layers66and68thus will follow the profile of dashed lines65. In accordance with alternative embodiments of the present disclosure, an etching mask (not shown) such as a patterned photo resist is used, wherein the patterned etching mask have some portions overlapping pyramids56, and have openings overlapping voids64. Dielectric layer62is etched using the etching mask to open voids64.

FIG. 7illustrates the formation of diffusion barrier layer66. The respective process is illustrated as process214in the process flow shown inFIG. 18. In accordance with some embodiments of the present disclosure, diffusion barrier layer66is formed of a material that can effectively prevent the subsequently deposited high-reflectivity layer68(FIG. 9) from diffusing into substrate24. Furthermore, diffusion barrier layer66may also be formed of a high-k dielectric layer because some of the high-k dielectric materials have advantageously optical properties (such as good reflection property). Non-high-k materials with good optical properties are also contemplated by the embodiments. In accordance with some embodiments of the present disclosure, diffusion barrier layer66is formed of aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), or the like, or a composite layer including more than one of these layers. The formation of diffusion barrier layer66may be achieved using a conformal deposition method such as Atomic Layer Deposition (ALD), CVD, or the like. The thickness of diffusion barrier layer66is high enough to prevent the subsequently deposited high-reflectivity layer68(FIG. 9) from diffusing into substrate24, yet small enough to leave enough space for high-reflectivity layer68and voids64. For example, thickness T2of diffusion barrier layer66is greater than about 30 Å because if thickness T2is smaller, the diffusion-preventing ability of diffusion barrier layer66is inadequate. On the other hand, thickness T2may be smaller than about 10 percent of width W1of trenches60. Otherwise, the remaining voids64will be too small and will not have enough height. The thickness T2of diffusion barrier layer66may be in the range between about 30 Å and about 100 Å. Thickness T2may also be measured at a level in the middle between the bottom of trenches6oand the top of pyramids56.

FIG. 8illustrates the formation of high-reflectivity layer68. The respective process is illustrated as process216in the process flow shown inFIG. 18. In accordance with some embodiments of the present disclosure, the formation method includes forming a seed layer (for example, using PVD), and plating high-reflectivity layer68. The seed layer may be formed of copper. The material of high-reflectivity layer68includes a material that has a high reflectivity, for example, higher than about 90 percent at a wavelength greater than about 600 nm.FIG. 16illustrates the reflectivity values of several metal-containing materials (with thicknesses being 5 kÅ) as a function of wavelengths. As is shown inFIG. 16, copper and aluminum copper (AlCu) have high reflectivity values, and can be used to form high-reflectivity layer68. As a comparison, tungsten and titanium nitride have low reflectivity values, and will not be used. Also,FIG. 17illustrates the absorption index k and reflective index n of copper as functions of the thicknesses of copper in accordance with some embodiments. The results shown inFIG. 17were obtained using the light with wavelength of 940 nm.FIG. 17illustrates that when the thickness of copper layer is about 15 nm (150 Å) or greater, the absorption index k is high, for example, with values being about 5.0 or higher. The absorption index k also becomes stably high when the thicknesses of copper are greater than about 150 Å. High absorption index means that the light goes into copper is absorbed more, and will not penetrate through copper to go into neighboring image sensor cells, and will not adversely affect the neighboring image sensor cells.FIG. 17also illustrates that when the thickness of copper layer is about 150 Å or greater, the reflective index n is low. The reflective index n also becomes stably low with thicknesses of copper being greater than about 150 Å. Low reflective index n means that light-reflection at the surface of copper is better. Also, when the thickness of copper is increased to about 300 Å or greater, the absorption index k and reflective index n of copper are satisfactory for all wavelengths.

Based on the results shown inFIG. 17, the thickness of high-reflectivity layer68is greater than about 150 Å, and may be greater than about 300 Å for performance demanding devices. The thickness of high-reflectivity layer68is also small enough so that the remaining voids64are large enough, and the top ends of voids64can be at least level with or higher than the top ends of substrate24, so that the ability of voids64for absorbing stress is not compromised. In accordance with some embodiments of the present disclosure, thickness T3of high-reflectivity layer68(FIG. 8) may be in the range between about 150 Å and about 500 Å, and may be in the range between about 300 Å and about 500 Å. Thickness T3may also be measured at a level in the middle between the bottom of trenches60and the top of pyramids56. Also, all portions of high-reflectivity layer68may have thicknesses greater than about 150 Å or greater than about 300 Å.

In order to form high-reflectivity layer68while leaving voids64not fully filled, a method capable of increasing the overhang of high-reflectivity layer68is used, wherein the overhang portions are the portions that are directly over some portions of voids64. The overhangs of high-reflectivity layer68grow toward each other, and eventually seal voids64therein. In accordance with some embodiments of the present disclosure, high-reflectivity layer68is plated, with the plating including two stages. The first stage is performed using a first plating current small enough so that the respective plated first layer of high-reflectivity layer68is substantially conformal. Accordingly, the plated first layer has a good coverage. When the thickness of the first layer of high-reflectivity layer68is greater than about 150 Å (for example, for copper), the second stage is performed, and a second plating current higher than the first plating current is used to increase the deposition rate and to form a second layer on the first layer. The deposition rate in the second stage is high so that the top portions of metal layer68, especially the portions outside and around the top ends of trenches60are grown much faster than the portions inside trenches60. Accordingly, voids64are sealed. In accordance with some embodiments of the present disclosure, the first plating current of the first plating stage has a first current in the range between about 0.5 amps and about 5 amps, and the second plating current has a second current in the range between about 10 amps and about 40 amps. It is appreciated that the plating currents are related to the total area to be plated. In accordance with some embodiments of the present disclosure, the ratio of the second current to the first current (and the corresponding current densities) is greater than 1.0, greater than about 2.0, and may be in the range between about 2 and about 80.

Referring toFIG. 9, a planarization process such as a CMP process or a mechanical grinding process is performed to remove excess portions of layers62,66, and68, forming Deep Trench Isolations (DTIs)70. The respective process is illustrated as process218in the process flow shown inFIG. 18. The remaining voids64in DTI regions70have top ends level with or higher than the bottoms of pyramids56, for example, at the level between the top ends and the bottoms of pyramids56in order to effectively absorb stress. The top ends of voids64may also be higher than the top ends of pyramids56to have further improved ability in absorbing the stress. Furthermore, DTI regions70include portions70A higher than the top ends of pyramids56. Portions70A do not have void therein. The portions of metal layer68in portions70A also form a grid when viewing from the top of wafer22. These portions of metal layer68thus act as a metal grid. In accordance with some embodiments of the present disclosure, height H2of portions70A is greater than about 0.5 μm to effectively confine incoming light between the grids.

FIG. 10illustrates the deposition of diffusion barrier layer72. The respective process is illustrated as process220in the process flow shown inFIG. 18. In accordance with some embodiments of the present disclosure, diffusion barrier layer72comprises silicon nitride or the like. Diffusion barrier layer72prevents the material (such as copper) in DTI regions70from being diffused upwardly.

FIG. 14illustrates a top view of DTI regions70. In accordance with some embodiments of the present disclosure, a plurality of DTI regions70are formed simultaneously, each having the structure shown inFIG. 10. The plurality of DTI regions70form a plurality of strips as shown inFIG. 14, which include a first plurality of strips70extending in the X-direction, and a second plurality of strips70extending in the Y-direction, which is perpendicular to the X-direction. Hence, the first plurality of DTI regions70and the second plurality of DTI regions70form a grid pattern, with a plurality of portions of semiconductor substrate24separated from each other, and defined by, the grid. The grid of DTI regions70overlap the grid formed of STI regions32.

Voids64, as also illustrated inFIG. 14, may include portions extending in the X-direction and portions extending in the Y-direction. The portions of voids64extending in the X-direction and the Y-direction are also interconnected to form an integrated void, which has the shape of a grid when viewed from top.

In subsequent process steps, as shown inFIG. 11, additional components such as color filters74are formed. The respective process is illustrated as process222in the process flow shown inFIG. 18. Micro lenses76are then formed, as shown inFIG. 12. The respective process is illustrated as process224in the process flow shown inFIG. 18. Each of image sensors26is aligned to one of color filters74and one of micro-lenses76. Image sensor chip20(and corresponding wafer22) is thus formed.

The image sensor chip20as shown inFIG. 12is a BSI image sensor chip, and incoming light78is projected from the backside of substrate24onto image sensors26. The light78may be scattered by slanted surfaces56A, so that the light becomes more tilted inside substrate24. The tilted light is more likely to be reflected (rather than penetrating through substrate24). Also, by forming high-reflectivity layer68using a high-reflectivity material, the light is more likely to be reflected than absorbed by DTIs70. These factors increase the light-traveling paths in substrate24(and in image sensors26), and the light has more chance to be absorbed by image sensors26. The light-conversion efficiency (the quantum efficiency) is thus improved.

The DTI regions70formed in accordance with some embodiments of the present disclosure may also be used in other structures such as in Front Side Illumination (FSI) image sensor chips.FIG. 15illustrates an embodiment in which DTI regions70are formed in FSI image sensor chip20′. Referring toFIG. 15, FSI image sensor chip20′ includes DTI regions70, which form a grid similar to what is shown inFIG. 14. Pixel units30have portions formed in the regions defined by DTI regions70. In accordance with some embodiments of the present disclosure, STI regions are no longer formed to define active regions since DTI regions70include dielectric layers that may also act as (electrical) isolation regions. Each of the pixel units30may include photo diode26, transfer gate transistor134, and additional components (not shown inFIG. 15, refer toFIG. 13). DTI regions70extend from the major surface24A (which is the front surface) of semiconductor substrate24into an intermediate level of semiconductor substrate24. Interconnect structure44may be formed over pixel units30and DTI regions70, and includes a plurality of metal lines and vias in a plurality of dielectric layers. Color filters74and micro lenses76are formed over interconnect structure44, and are aligned to pixel units30. In the FSI image sensor chip20′, light78is projected to photo diodes26from the front surface of chip20′.

A plurality of group of samples are made on semiconductor wafers to compare the results. The first group of samples is formed to have air gaps (which are not filled) as DTI regions. The second group of samples is formed to have tungsten in DTI regions. The third group of samples is formed according to some embodiments of the present disclosure, in which copper is used. The first, the second, and the third groups have the same number of pixels. After the formation, the three groups of samples are measured to determine the number of defective pixels and the quantum efficiency of the image sensors. The number of Dark Current (DC) pixels in the first, second, and the third groups of sample pixels are 17, 44, and 18, respectively. This indicates the number of DC pixels in accordance with some embodiments of the present disclosure (the third group) is much better than that of the second group, and is substantially the same as that of the first group. The number of White Pixels (WP) in the first, second, and the third groups of sample pixels are 522, 1145, and 438, respectively, indicating the number of DC pixels formed in accordance with some embodiments of the present disclosure (the third group) is much better than that of both the first and the second groups. In addition, the quantum efficiency of the samples formed in accordance with some embodiments of the present disclosure (the third group) is 19 percent, which is slightly lower than the 24 percent quantum efficiency of the first group of samples, and much higher than the 5 percent quantum efficiency of the second group of samples. Accordingly, the samples formed in accordance with some embodiments of the present disclosure have the best overall performance.

The embodiments of the present disclosure have some advantageous features. By using a high-reflectivity metallic material such as copper to form DTI regions, the quantum efficiency of image sensors is improved. The high-reflectivity metallic material, however, may have a Coefficient of Thermal Expansion (CTE) around 16 to 16.7, which is much greater than the CTE (about 3 to 5) of the substrate. The significant difference in the CTEs causes cracks to be formed between the DTI regions and the substrate. This problem is solved by forming voids (air gaps) in the DTI regions. The voids act as the buffer for the increased volume of copper under elevated temperatures, and absorb the stress generated due to thermal cycles. Accordingly, the performance of the image sensors is improved without sacrificing the reliability.

In accordance with some embodiments of the present disclosure, a method includes etching a semiconductor substrate to form a trench; filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer; etching the dielectric layer to reveal the void; forming a diffusion barrier layer on the dielectric layer; and forming a high-reflectivity metal layer on the diffusion barrier layer, wherein the high-reflectivity metal layer comprises a portion extending into the trench, and a remaining portion of the void is enclosed by the high-reflectivity metal layer. In an embodiment, the forming the high-reflectivity metal layer comprises: forming a seed layer extending into the trench; plating a first copper-containing metal layer to a thickness greater than about 150 Å on the seed layer, wherein the first copper-containing metal layer is plated using a first plating current; and depositing a second copper-containing metal layer on the first copper-containing metal layer, wherein the second copper-containing metal layer is plated using a second plating current greater than the first plating current. In an embodiment, the forming the diffusion barrier layer comprises depositing a conformal high-k dielectric layer. In an embodiment, the method further includes, before the semiconductor substrate is etched to form the trench, etching the semiconductor substrate to form an array of pyramids, with the pyramids formed of portions of the semiconductor substrate. In an embodiment, the method further includes planarizing the high-reflectivity metal layer, the diffusion barrier layer, and the dielectric layer to form a DTI region, wherein after the high-reflectivity metal layer is planarized, the void is sealed in the high-reflectivity metal layer. In an embodiment, the DTI region forms a grid, and the method further comprises: forming pixel units, with portions of the pixel units in the grid; and forming color filters and micro lenses overlapping the grid. In an embodiment, a portion of the void extends beyond the semiconductor substrate. In an embodiment, the forming the diffusion barrier layer comprises depositing hafnium oxide or aluminum oxide.

In accordance with some embodiments of the present disclosure, a method includes forming STI regions extending from a first surface of a semiconductor substrate into the semiconductor substrate; forming pixel units between the STI regions; forming DTI regions extending from a second surface of a semiconductor substrate toward the STI regions, wherein the forming the DTI regions comprises: etching the semiconductor substrate to form trenches extending from the second surface of the semiconductor substrate into the semiconductor substrate; forming a dielectric layer extending into the trenches; filling a high-reflectivity metal layer extending into the trenches and over the dielectric layer, wherein the high-reflectivity metal layer encloses a void therein; and planarizing the high-reflectivity metal layer and the dielectric layer to form the DTI regions; and forming micro lenses aligned to the pixel units. In an embodiment, the DTI regions comprise portions extending beyond the second surface of the semiconductor substrate, with the portions of the DTI regions being located between the semiconductor substrate and the micro lenses. In an embodiment, the method further includes, before the etching the semiconductor substrate to form the trenches, etching the semiconductor substrate from the second surface to form pyramids. In an embodiment, the dielectric layer further comprises a portion between the semiconductor substrate and the micro lenses. In an embodiment, the method further includes forming a first diffusion barrier layer between the dielectric layer and the high-reflectivity metal layer; and forming a second diffusion barrier layer between the semiconductor substrate and the micro lenses. In an embodiment, the filling the high-reflectivity metal layer comprises: plating using a first plating current to form a substantially conformal layer; and plating using a second plating current greater than the first plating current to seal the void.

In accordance with some embodiments of the present disclosure, a structure includes a DTI region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the DTI region comprises a dielectric layer extending into the semiconductor substrate; and a high-reflectivity metal layer between opposite portions of the dielectric layer, wherein the high-reflectivity metal layer encloses a void therein; a diffusion barrier layer over the DTI regions and the semiconductor substrate; pixel units with portions in the semiconductor substrate; color filters overlapping the pixel units; and micro lenses overlapping the color filters. In an embodiment, the structure further comprises a Shallow Trench Isolation (STI) region extending from a bottom surface of the semiconductor substrate into the semiconductor substrate, wherein the DTI region overlaps the STI region. In an embodiment, the structure further comprises a diffusion barrier layer between the semiconductor substrate and the color filters, wherein the dielectric layer comprises a portion overlapping the semiconductor substrate, with the portion of the dielectric layer having opposite surfaces contacting the semiconductor substrate and the diffusion barrier layer. In an embodiment, the structure further comprises an additional diffusion barrier layer between the dielectric layer and the high-reflectivity metal layer, wherein the additional diffusion barrier layer is in the semiconductor substrate. In an embodiment, the high-reflectivity metal layer has a reflectivity higher than about 90 percent. In an embodiment, all portions of the high-reflectivity metal layer in the DTI region have thicknesses greater than about 150 Å.