Low noise and low distortion test method and system for analog-to-digital converters

Disclosed examples include a method and automated test system for testing an ADC. The method includes computing an ADC noise value based on a first set of data values sampled while the ADC input terminals are shorted, computing a first system noise value based on a second set of data values sampled while a test circuit signal source applies zero volts to the ADC through a signal chain, computing a signal chain noise value based on the first system noise value and the ADC noise value, computing a measured SNR value based on a third set of data values sampled while the test circuit signal source applies a non-zero source voltage signal to the signal chain, computing a second system noise value based on the measured SNR value, and computing an ADC SNR value based on the second system noise value and the signal chain noise value.

BACKGROUND

Analog-to-digital converters (ADC) are used in many modern electrical systems to provide a digital value representing a sampled input signal. During manufacturing, ADCs are tested to evaluate noise performance in terms of signal-to-noise ratio (SNR), as well as to characterize integral non-linearity (INL) to ensure that the ADC will operate properly. INL performance is related to settling time of a test system, and there is a trade-off between fast settling time and low noise for the test system. Current systems used two separate circuits for testing high-performance ADC noise and integral non-linearity. This increases the testing time for a given manufactured ADC, because each part requires two insertions of the ADC. First insertion into a low noise test circuit to evaluate SNR performance, and a second insertion into a fast settling-time test circuit to evaluate INL performance.

SUMMARY

Disclosed examples provide simplified techniques for testing ADC noise performance. Systems and methods for testing ADCs are presented using an approach with three modes. In certain examples, the method includes receiving a first set of data values sampled when first and second ADC input terminals are connected to one another. The method further includes receiving a second set of data values sampled by the ADC while the ADC input terminals are connected to a test circuit signal chain of a test circuit and a test circuit signal source applies a zero volt source voltage signal to the test circuit signal chain. The method further includes receiving a third set of data values sampled by the ADC while the first and second ADC input terminals are connected to the test circuit signal chain and the test circuit signal source applies a full scale source voltage signal to the test circuit signal chain. The method further includes computing an ADC SNR value that represents a noise performance of the ADC based on the first, second, and third sets of data values.

In some examples, the method further includes actuating the test circuit to connect the first and second ADC input terminals to one another. In some examples, the method further includes actuating the ADC to sample the input signal while the first and second ADC input terminals are connected to one another, and receiving the first set of data values from the ADC. In some examples, the method further includes computing an ADC noise value based on the first set of data values. In some examples, the method further includes actuating the test circuit to connect the ADC input to a test circuit signal chain of the test circuit, and setting the test circuit signal source to apply the zero volt source voltage signal to the signal chain. In some examples, the method further includes actuating the ADC to sample the input signal while the test circuit signal source applies zero volts to the signal chain, and receiving the second set of data values from the ADC. In some examples, the method further includes computing the first system noise value based on the second set of data values. In some examples, the method further includes computing a signal chain noise value based on the first system noise value and the ADC noise value. In some examples, the method further includes actuating the test circuit signal source to apply the non-zero full scale source voltage signal to the signal chain while the first and second ADC input terminals are connected to the signal chain. In some examples, the method further includes actuating the ADC to sample the input signal while the test circuit signal source applies the non-zero full scale source voltage signal to the signal chain, and receiving the third set of data values from the ADC. In some examples, the method further includes computing a measured SNR value based on the third set of data values. In some examples, the method further includes computing a second system noise value based on the measured SNR value. In some examples, the method further includes computing the ADC SNR value based on the second system noise value and the signal chain noise value.

In some examples, the method further includes that the ADC noise value is computed as a standard deviation of the first set of data values; and that the first system noise value is computed as a standard deviation of the second set of data values. In some examples, the method further includes that the second system noise value is computed based on using an ADC code range. In some examples, the method further includes that the ADC SNR value is computed based on a square root of a difference between a square of the signal chain noise value and a square of the second system noise value. In some examples, the method further includes that the measured SNR value includes performing a Fast Fourier Transform on the third set of data values. In some examples, the method further includes that the signal chain noise value is computed as a square root of a difference between a square of the ADC noise value and a square of the first system noise value.

An automated test system for testing a connected ADC is also provided, the ADC including an input with a first ADC input terminal and a second ADC input terminal to receive an input signal. The system includes a test circuit. The test circuit includes a test circuit signal source, including first and second signal source outputs to provide a source voltage signal according to a signal source control signal. The test circuit further includes a signal chain circuit. The signal chain includes a signal chain input to receive the source voltage signal from the test circuit signal source, the signal chain input including a first signal chain input node connected to the first signal source output, and a second signal chain input node connected to the second signal source output. The signal chain further includes a signal chain output to provide a signal chain output signal, the signal chain output including a first signal chain output node. The test circuit further includes a second signal chain output node. The test circuit further includes a switch circuit coupled with the signal chain output and with the input of the ADC, the switch circuit operative in a first state to connect the first and second ADC input terminals to one another, and in a second state to connect the signal chain output to the input of the ADC to provide the signal chain output signal to the first and second ADC input terminals. In certain implementations, the system further includes a host system. The host system includes a processor configured to, in a first test mode, provide a switch control signal to place the switch circuit in the first state, provide a convert control signal to cause the ADC to sample and convert the input signal while the switch circuit is in the first state, receive a corresponding first set of data values from the ADC, and compute an ADC noise value based on the first set of data values. In certain implementations, the processor is further configured to, in a second test mode, provide the switch control signal to place the switch circuit in the second state, provide the signal source control signal to cause the test circuit signal source to provide the source voltage signal to the signal chain circuit at zero volts, provide the convert control signal to cause the ADC to sample and convert the input signal while the test circuit signal source provides the source voltage signal to the signal chain circuit at zero volts, receive a corresponding second set of data values from the ADC, and compute a first system noise value based on the second set of data values. In certain implementations, the processor is further configured to compute a signal chain noise value based on the first system noise value and the ADC noise value. In certain implementations, the processor is further configured to in a third test mode, provide the source control signal to cause the test circuit signal source to provide the source voltage signal to the signal chain circuit as a non-zero full scale sine wave voltage signal while the switch circuit is in the second state, provide the convert control signal to cause the ADC to sample and convert the input signal while the test circuit signal source provides the source voltage signal to the signal chain circuit as the non-zero full scale sine wave voltage signal, receive a corresponding third set of data values from the ADC, and compute a measured signal to noise ratio value based on the third set of data values. In certain implementations, the processor is further configured to compute a second system noise value based on the measured SNR value. In certain implementations, the processor is further configured to compute an ADC SNR value that represents a noise performance of the ADC based on the second system noise value and the signal chain noise value.

In some examples, the processor computes the ADC noise value as a standard deviation of the first set of data values. In some examples, the processor computes the first system noise value as a standard deviation of the second set of data values. In some examples, the processor computes the second system noise value based on using an ADC code range. In some examples, the processor computes the ADC SNR value based on a square root of a difference between a square of the signal chain noise value and a square of the second system noise value. In some examples, the measured SNR value includes performing a Fast Fourier Transform on the third set of data values. In some examples, the signal chain noise value is computed as a square root of a difference between a square of the ADC noise value and a square of the first system noise value.

In another embodiment, a method of individually testing ADCs is provided. The ADCs include a input with a first ADC input terminal, and a second ADC input terminal to receive an input signal. The method includes, for a plurality of ADCs, connecting the first and second ADC input terminals to one another. The method includes computing an ADC noise value based on a first set of data values corresponding to the ADC sampling the input signal while the first and second ADC input terminals are connected to one another. The method includes connecting the first and second ADC input terminals to a test circuit signal chain, and setting a test circuit signal source to apply a zero volt source voltage signal to the signal chain. The method includes computing, by the processor, a first system noise value based on a second set of data values corresponding to the ADC sampling the input signal while the test circuit signal source applies the zero volt source voltage signal to the signal chain. The method includes computing, by the processor, a signal chain noise value based on the first system noise value and the ADC noise value. The method includes setting the test circuit signal source to apply a non-zero voltage signal to the signal chain. The method includes computing, by the processor, a measured signal to noise ratio (SNR) value based on a third set of data values corresponding to the ADC sampling the input signal while the test circuit signal source applies the non-zero voltage signal to the signal chain. The method includes computing, by the processor, a second system noise value based on the measured SNR value. The method includes using the processor, computing an ADC SNR value that represents a noise performance of the ADC based on the second system noise value and the signal chain noise value. In some examples, the method includes, for the plurality of ADCs, using the processor, setting the test circuit signal source to apply a non-zero full scale sine wave voltage signal to the signal chain while the first and second ADC input terminals are connected to the signal chain, and includes that the third set of data values corresponds to a sample and conversion of the input signal done while the test circuit signal source applies the full scale sine wave voltage signal to the signal chain.

In some examples, the method includes, for the plurality of ADCs, that the ADC noise value is computed as a standard deviation of the first set of data values; and that the first system noise value is computed as a standard deviation of the second set of data values. In some examples, the method includes, for the plurality of ADCs, that the second system noise value is computed based on using an ADC code range. In some examples, the method includes, for the plurality of ADCs, that the ADC SNR value is computed based on a square root of a difference between a square of the signal chain noise value and a square of the second system noise value. In some examples, the method includes, for the plurality of ADCs, that the measured SNR value includes performing a Fast Fourier Transform on the third set of data values. In some examples, the method includes, for the plurality of ADCs, that the signal chain noise value is computed as a square root of a difference between a square of the ADC noise value and a square of the first system noise value.

DETAILED DESCRIPTION

In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are intended to be inclusive in a manner similar to the term “comprising”, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the terms “couple”, “coupled” or “couples” is intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections.

Referring initially toFIGS. 1 and 2,FIG. 1illustrates a non-limiting example method100of testing an ADC that can be implemented by a processor204in an automated test system200ofFIG. 2. The ADC260includes an input. The ADC input in one example is a differential input. In other examples, the ADC input is a pseudo-differential input or a single ended input. The ADC input includes a first ADC input terminal272and a second ADC input terminal274to receive an input signal, such as a differential input signal INP, INM. In other examples, the ADC input receives a single-ended or pseudo-differential input signal. In various configurations of the test system200, the input signal is provided to the ADC input from a test circuit signal source250though signal chain253.FIG. 2shows a differential signal chain circuit253. In other examples, the signal chain circuit253is a single ended circuit (not shown), and the circuit can include ground or reference node connections for the second ADC input. The system200ofFIG. 2can be used to test a variety of different types and forms of ADC, for example, a 20-bit successive approximation register (SAR) ADC. The method100in one example is implemented by a processor204of a host system202by exchanging signals with a currently tested ADC260and a test circuit251. The example method100includes a first test mode (e.g., at104,106and108inFIG. 1), a second test mode (e.g.,110,112and114), and a third test mode (118,120and122). Based on measurements taken during these three test modes, the method100provides a computed ADC signal-to-noise ratio value SNRADCrepresenting noise performance of the ADC260device under test (DUT). The method100, including the three test modes, is then repeated for a subsequently tested ADC260.

FIG. 2shows an automated test system200for testing the ADC260. The ADC260is connectable to test circuit251through the first ADC input terminal272and the second ADC input terminal274. In this example, the first ADC input terminal272is connectable to a first signal chain output node276, and the second ADC input terminal274is connectable to a second signal chain output node280. A switch connecting node278connects the test circuit251to the ADC260. The automated test system200ofFIG. 2includes a host system202with a processor204and an associated memory206. In one example, the processor204implements or executes a control program to a weight stored in the memory206, including obtaining and computing one or more data values210stored in the memory206. The host system202includes a data input connection212to receive converted data values or signals (DATA) from a tested ADC260. In one example, the data input connection212is a single electrical connection to provide serial transfer of the data signal DATA from the tested ADC converter260. In another non-limiting example, the data input connection212includes multiple connections to provide parallel data transfer from a tested ADC260to the host system202. The host system202also includes a conversion control output connection214to provide a convert control signal CON CONTROL to the tested ADC260, as well as a test circuit control output connection216to provide a switch control signal SWC CONTROL to a switch circuit269of the test circuit251. The switch269may be placed in the first state, which is used for a first test mode. In the first state, the switch269connects the first and second ADC input terminals272,274to one another (e.g., shorts the first and second ADC input terminals272,274). The switch269may also be placed in the second state, which is used for second and third test modes. In the second state, the switch269connects the first and second ADC input terminals272,274to the test circuit signal chain253of the test circuit251.

The host system202also includes an output connection218to provide a signal source control signal SOURCE CONTROL to a test circuit signal source250of the test circuit251. The host system202provides a signal PASS/FAIL via an output220to indicate whether the ADC260under test has an acceptable noise performance, and also provides an ADC SNR signal at an output222to indicate the measured SNR performance of the ADC260under test. The host system202in various examples can provide the outputs220,222and the associated signals PASS/FAIL, ADC SNR as communications messaging to another computer system (not shown), or can provide the signals or values to a user interface or any other suitable external system by which a given device under test can be deemed as acceptable or not, and a specific performance parameter of the tested device can be provided.

The host system202and the device under test interface with the test circuit251to implement multi-mode testing of a connected ADC260. The test circuit251includes the switch circuit269operating according to the switch control signal from the host circuit output216in order to selectively connect the ADC input terminals to272,274of the connected ADC260to one another, or to connect the ADC input to receive a differential signal from a signal chain circuit253. The signal chain circuit253includes a differential input with first and second signal chain input nodes255and257that receive a differential source voltage signal VS from the test circuit signal source250.

The source250provides the differential source voltage signal VS according to the SOURCE CONTROL signal from the host circuit output218. The host system processor204, in some implementations, executes program instructions208in the memory206to perform the method100ofFIG. 1. In operation, the host system202provides the convert control signal CON CONTROL214to the ADC260to cause the ADC260to sample and convert the differential, single-ended or pseudo-differential input signal INP, INM. The ADC260provides the resulting converted data values DATA via the host system connection212to the host system202for use by the host processor204to compute noise values and SNR values. The host processor204also provides the switch control signal SWC CONTROL at the output216to control the switch circuit269in different states according to a test mode. The host processor204indicates a pass/fail of the ADC260with pass/fail signal PASS/FAIL via an output220, and also indicates SNR values by providing the ADC SNR signal at the output222.

The first signal chain input node255is connected through an upper first resistor252(R1) to an inverting (+) input of an upper amplifier262, and an upper feedback resistor256(RF) is connected between the inverting input (−) of the amplifier262and an output of the amplifier262. A non-inverting input of the upper amplifier262is connected to a common or reference node263. The second signal chain input node257is similarly coupled through a lower first resistor254(R1) to a non-inverting input (+) of a lower amplifier264, and a lower feedback resistor258(RF) is connected between the lower amplifier non-inverting input and an output of the amplifier264. The inverting (−) input of the lower amplifier264is connected to the non-inverting input of the upper amplifier262at the reference node263. The upper and lower amplifier outputs are coupled through respective upper and lower resistors (R)266and268to corresponding signal chain output nodes276and280. A test circuit output capacitor270is connected between the circuit nodes276and280. With the switch circuit269in the second state, the signal chain253provides the voltage signal VS from the test circuit signal source250to the first and second ADC input terminals272,274. As discussed below in connection withFIG. 3, however, the signal chain253has noise. The presently disclosed concepts account for the signal chain noise when testing the ADC260. In some implementations, the differential source voltage signal VS is sent from the test circuit signal source250to the first and second signal source outputs255,257(also referred to as the first and second signal chain input nodes255,257). In the implementation ofFIG. 2, the signal chain253includes first through sixth resistors252,254,256,258,266and268, as well as first and second operational amplifiers (op-amps)262and264and a capacitor270(C).

The circuit node276in this example is connected to the first ADC input terminal272by the system socket connection for the tested ADC260. The lower circuit node280is connected to the switching circuit269, which selectively connects the second ADC input terminal274to either the first ADC input terminal272or to the signal chain output node280. In this configuration, a first switching state of the switching circuit269shorts the ADC input terminals272,274together, and a second switching state of the circuit269connects the ADC input terminals272,274to receive a differential, single-ended or pseudo-differential input signal INP, INM from the signal chain circuit253.

The example test method100ofFIG. 1begins at102, where an ADC260is inserted into the test system200ofFIG. 2, for example, by insertion of the currently tested ADC260into a test fixture or socket having electrical connections for the ADC input terminals to272,274, connections for interfacing a data output of the tested ADC260with the host system202, connections for a conversion control input signal from the host system202, as well as connections to provide power to the ADC260. In the example ofFIG. 2, the test fixture includes socket connections to connect the first and second ADC input terminals272,274to the test circuit251, as well as a single socket connection to connect a serial ADC output terminal to the host processor204. At104, the processor204actuates (e.g., enables or otherwise causes) the test circuit251to connect the first and second ADC input terminals272,274to one another. At106, the processor204actuates the ADC260to sample and convert the differential, single-ended or pseudo-differential input signal INP, INM while the first and second ADC input terminals272,274are connected to one another, and receives a corresponding first set of data values from the ADC260. At108, the processor204computes an ADC noise value (σADC) based on the first set of data values. At110, the processor204actuates the test circuit251to connect the first and second ADC input terminals272,274to a test circuit signal chain253of the test circuit251, and sets the test circuit signal source250to apply a zero volt source signal to the signal chain253. The applied zero volt source signal is an output corresponding to a zero voltage command input to the signal source250, which may but need not be actually zero. At112, the processor204actuates (e.g., enables or otherwise causes) the ADC260to sample and convert the differential, single-ended or pseudo-differential input signal INP, INM while the test circuit signal source250applies zero volts to the signal chain253, and receives a corresponding second set of data values from the ADC260. At114, the processor204computes a first system noise value (σSYS-0V) based on the second set of data values. At116, the processor204computes a signal chain noise value (σSIGNAL-CHAIN) based on the first system noise value (σSYS-0V) and the ADC noise value (σADC). At118, the processor204sets the test circuit signal source250to apply a non-zero full scale voltage signal to the signal chain253while the first and second ADC input terminals272,274are connected to the signal chain253. In some implementations, the applied non-zero signal is a sine wave. In other implementations, the applied non-zero signal is a non-sinusoidal alternating waveform. In some examples the non-zero signal is a full scale alternating signal. At120, the processor204actuates the ADC260to sample and convert the differential, single-ended or pseudo-differential input signal INP, INM while the test circuit signal source250applies the full scale wave voltage signal to the signal chain253, and receives a corresponding third set of data values from the ADC260. At122, the processor204computes a measured signal to noise ratio (SNR) value (SNRMEASURED) based on the third set of data values. At124, the processor204computes a second system noise value (σSYS-FS) based on the measured SNR value (SNRMEASURED). At126, the processor204computes an ADC SNR value (SNRADC) that represents a noise performance of the ADC (260) based on the second system noise value (σSYS-FS) and the signal chain noise value (σSIGNAL-CHAIN).

Referring also toFIG. 3, as mentioned above, the signal chain circuit253has noise sources, and the process100accounts for these noise source when testing the ADC260.FIG. 3is a schematic diagram of the automated test system200including an illustrative example of the signal chain noise components or sources. In certain implementations, many of the components of the system200will have an associated noise. The example ofFIG. 3shows first resistor noise representation302, second resistor noise representation304, third resistor noise representation306, first op-amp noise representation308, common mode noise representation310, second op-amp noise representation312, fourth resistor noise representation314, and ADC noise representation316.

The illustrated system200measures ‘device limited’ SNR and linearity of ADC260. In one example, a pass/fail criterion for a given tested ADC260is expressed in terms of signal-to-noise ratio and integral non-linearity (e.g., an expected device performance of 105 dB SNR and +/−1 ppm integral non linearity (INL)). To accurately verify whether or not a given ADC260meets this example performance, the test system must have greater than 22 bit linearity and greater than 120 dB SNR. In such a system, the measured ADC performance will accurately reflect the capabilities of the tested ADC260. For an example 105 dB device SNR, the voltage noise density of the signal chain253should be less than 1 nV/√Hz over a bandwidth of 5 MHz. As discussed above, however, it is not practical to achieve a 22 bit linear source with less than 1 nV/√Hz noise in a single test circuit, and the maximum measurable test circuit SNR is limited by the driving op-amps.

DC input applications for ADCs260often require maximum SNR from device. For AC input applications, distortion is an important performance criteria. The illustrated method100and the example test system200facilitate use of a single test circuit to accurately characterize ADC SNR and INL in a single insertion. Compared with prior techniques, this advantageously reduces test time and cost for producing ADCs260. Moreover, the illustrated techniques and systems accommodate the inherent trade-off between SNR and linearity, while facilitating accurate characterization of both SNR and INL in a single test insertion. The ADC260has an input sample and hold circuit (not shown). After conversion, a charged capacitor in the hold circuit of the ADC260, is connected to the differently charged capacitor270. This causes a ‘kick-back’ effect which is partly absorbed by the capacitor270. Remaining charge is provided by a driving amplifier and the inputs ideally settle within the acquisition phase for high bandwidth performance. Noise from the op-amps262,264and the test circuit signal source250will integrate over this high bandwidth, and accordingly there is a trade-off between faster settling (e.g., low INL) and low noise (SNR). The signal chain bandwidth has an impact on the type of performance parameter being tested. Specifically, a low bandwidth test circuit is preferred for testing ADC noise (SNR), whereas a high signal chain bandwidth is beneficial for testing the INL of the ADC260. For noise measurements, op-amp white noise (voltage noise and current noise) integrates over the bandwidth of the driver amplifier stage. Also, the total input referred noise of the op-amps, which are capable of driving a switched capacitor load such as the ADC260, is typically 5 nV/√Hz, and the SNR is inversely proportional to system bandwidth. The total integrated RMS noise of the signal chain is given by: Total input referred noise x√{square root over (bandwidth VRMS)}.

Conversely, a high signal chain bandwidth is beneficial for ‘kick-back’ settling (fast settling time), and hence for properly characterizing the INL of the ADC260. The kick-back caused by the input sampling capacitor of the ADC260(not shown inFIG. 2) must be settled within the acquisition time for good INL testing, as the settling time is inversely proportional to the driver stage bandwidth and higher bandwidth corresponds to a lower (i.e., faster) settling time. For instance, for 20 bit settling, 14 time-constants are required for a sine input. For an example amplified bandwidth of 5 MHz, one time constant is 20 ns and the total settling time is 14×20 ns=280 ns. Hence, settling (in effect distortion) of the system is directly proportional to system bandwidth.

As mentioned above, prior systems had the drawback that two insertions of an ADC were required. The first insertion was to a circuit with a low noise topology. In this topology, a high input common mode variation resulted in distortion limited by the common-mode rejection ratio (CMRR) of the op-amp. This test circuit topology had a poor INL, and a high SNR. The second insertion had a linear topology (rather than a low noise topology). This topology, had no common mode variation, which ensured lowest possible distortion on account of op-amps. This test circuit had poor SNR because the op-amp noise is multiplied by a non-inverting gain.

In contrast, the example systems200and methods100advantageously allow for a single insertion solution, for example, by using a high bandwidth signal chain and calibrating system noise in accordance with the multiple test modes described herein. In operation, the host system202provides the SWC CONTROL216to place the switch269in a state according to a current test mode. In the example ofFIG. 4, the switch is in the first state and the system200is in the first test mode. In certain implementations, the use of the two switch states and multiple test modes advantageously allows an ADC260to be successfully tested with only one insertion.

Referring also to a graph500inFIG. 5, the total noise seen in the output codes of the ADC260is root-sum-square of individual noise sources. Common mode noise is rejected by the CMRR of the ADC260. Among all the mentioned noise sources, only VnoiseADCis of interest in characterizing ADCs260in a manufacturing test application. The process or method100inFIG. 1accurately computes the device SNR value and VnoiseADCby effectively calibrating the test circuit noise sources using the ADC260currently connected to the test system200.FIG. 5shows noise profile vs. input voltage (e.g. shows standard deviation of ADC output codes (LSB) vs. differential voltage). The graph500ofFIG. 5includes an ADC noise curve502and an op-amp noise curve504, shown as a function of differential input voltage. In this example, the ADC noise502increases as the differential input voltage tends towards full scale voltage. Conversely, the op-amp noise504is independent of the applied input voltage. If the op-amp noise504is known at any DC voltage, it can be used to calibrate a noise floor of the ADC260at any input voltage. At 0V input, the ADC260has no dependence on reference voltage, and hence reference artifacts are not calibrated out. InFIG. 5, point506illustrates the ADC noise at 0V (e.g., measured in the first mode of the method100at104-108), and point508illustrates the op-amp noise at 0V (e.g., measured in the second test mode at110-114inFIG. 1).

In this example, because ADC noise is a function of the applied input voltage, the two measurements for σADCand σSYSare done under the same differential input voltage (e.g., at 0V). As σADCvaries with input, σADCcannot be directly used for computing the SNR of the ADC260. Accordingly, the method100computes the system noise σsignal-chainindependent of applied input voltage. The illustrated method100subtracts this noise source from the SNRMEASUREDnoise floor to compute the value SNRADC. The resulting computed value SNRADChas all the information regarding ADC260noise variation with input to correctly characterize the performance of the ADC260under test.

In the first test mode, the system measures the noise of the ADC260.FIG. 4illustrates an example of the system configuration in the first test mode. In one implementation of the first test mode, all noise sources external to ADC are attenuated by the CMRR of the ADC260. In this configuration, the processor204captures the data from the ADC260and computes its standard deviation σADC(e.g.,106,108inFIG. 1). The converted codes of ADC260correspond to 0 V differential input (e.g., because the switch269is shorting the first and second ADC input terminals272and274). These codes have a code spread caused by the intrinsic noise of the ADC260under test (e.g., quantization and thermal).

In the second test mode, the processor204measures the system noise.FIG. 6shows the system200with the switch circuit269in the second state, corresponding to the system operation in the second or third test modes. In one example, the system200applies a 0 V differential input from the test circuit signal source250through the input signal chain253(e.g.,110inFIG. 1). The host system202captures data from the ADC260in this configuration, and computes the data's standard deviation σSYS(e.g.,112,114inFIG. 1). The converted codes of ADC260correspond to 0 V differential input, with a code spread caused by noise from the ADC260and from the test circuit signal chain noise sources illustrated inFIG. 3.

The signal chain noise σsignal-chaincan be computed by subtracting the ADC noise σADC, from the system noise σSYSas follows:
σsignal-chain=√{square root over (σSYS2−σADC2,)}
σsignal-chain=√{square root over (σSYS2+σop-amp2+σop-amp2+σsource2−σADC2)}, and
σsignal-chain=√{square root over (σop-amp2+σop-amp2+σsource2)}.

In the third test mode, the switch269is still in the second state. In one implementation, the host system202causes the test circuit signal source250to apply a full scale sine wave to the input of the ADC260through the signal chain circuit253, and the host system202computes the SNRMEASURED(e.g.,118,120,122inFIG. 1) from the captured data. The captured data includes all noise sources (e.g., σSYS). The host system202then computes a second system noise value σSYS-FS, in one implementation, by solving the following equation:

The host system202removes the signal chain noise (as demonstrated in the equation below), and computes SNRADCby solving the following equation.

The above-described implementation reports true ADCSNRwithout system limitations in a signal path optimized for linearity (i.e., high bandwidth). In one example, the ADCcode-rangeis a fixed value (e.g. 220). To illustrate the effectiveness of the above-described procedure, 30 ADC devices were tested under the following conditions: (i) High bandwidth: Signal chain optimized for distortion; no noise calibration, (ii) Limited bandwidth: Signal chain optimized for noise; no noise calibration, and (iii) High bandwidth with calibration: Signal chain optimized for distortion; noise calibration implemented.

The results were as follows.

As this shows, the example implementation described above allows to test the ADC260for linearity while still measuring true device SNR.

Also advantageously, certain implementations do not require high precision equipment. In some implementations, higher end equipment is not required, even for higher resolutions ADCs.

The above-described methods also improve quality of measurement, as parameters truly reflect device performance. It should also be noted that the ADC260is able to achieve simulation numbers using the above-described methods. The illustrated methods may be implemented in hardware, processor-executed software or processor-executed firmware, programmable logic, etc. or combinations thereof, and various embodiments or implementations include non-transitory computer readable mediums having computer-executable instructions for performing the illustrated and described methods. For example, an electronic memory (e.g.,206inFIG. 2) can be used to store computer executable instructions (program208) that are executed by the host processor204or more than one processor to implement the method ofFIG. 1. The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.