A voltage-controlled oscillator, including a voltage-controlled LC resonator including at least one first output node; an amplifier including at least one first dual-gate MOS transistor including first and second gates, coupling the first output node to a second node of application of a reference potential; and a regulation circuit capable of applying to the second gate of the first transistor a bias voltage variable according to the amplitude of the oscillations of a signal delivered on the first output node of the oscillator.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of French patent application number 16/51873, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

BACKGROUND

The present disclosure relates to voltage-controlled oscillators, and more particularly to oscillators with an LC resonator. More specifically, the present disclosure aims at so-called class-C oscillators with an LC resonator.

DISCUSSION OF THE RELATED ART

Voltage-controlled oscillators are used in many applications, particularly to generate radio frequency signals or RF signals (that is, signals having a frequency in the range from 3 kHz to 300 GHz) in wire or wireless communication systems.

Oscillators with an LC resonator, that is, comprising an LC resonant circuit (or LC resonator) having a resonance frequency varying according to a voltage applied to a circuit control node and an amplifier circuit comprising at least one MOS transistor coupled with the LC resonator, are here more particularly considered.

More specifically, so-called class-C oscillators with an LC resonator, that is, where the gates of the MOS transistor(s) of the amplifier circuit are biased to a DC voltage smaller than the threshold voltage of the transistors so that the transistors behave as class-C amplifiers, are here considered.

SUMMARY

An embodiment provides a voltage-controlled oscillator, comprising a voltage-controlled LC resonator comprising at least one first output node; an amplifier comprising at least one first dual-gate MOS transistor comprising first and second gates, coupling the first output node to a second node of application of a reference potential; and a regulation circuit capable of applying to the second gate of the first transistor a bias voltage variable according to the amplitude of the oscillations of a signal delivered on the first output node of the oscillator.

According to an embodiment, the oscillator further comprises a circuit of application of a fixed bias voltage to the first gate of the first transistor.

According to an embodiment, the fixed and variable bias voltages are such that the amplifier has a class-A, -B, or -AB biasing during a start-up phase of the oscillator, and has a class-C biasing in steady state.

According to an embodiment, the first transistor is a transistor having a negative threshold voltage variation; and the variable bias voltage decreases as the amplitude of the oscillations increases.

According to an embodiment, the fixed bias voltage is greater than or equal to the minimum threshold voltage of the first transistor, and is smaller than the maximum threshold voltage of the first transistor.

According to an embodiment, the regulation circuit comprises a first circuit capable of supplying a first voltage representative of the envelope of the oscillations, and a second circuit capable of generating the variable bias voltage from the first voltage.

According to an embodiment, the first circuit comprises a second diode-assembled MOS transistor in series with a first capacitive element between the first output node and the second node.

According to an embodiment, the second circuit comprises first and second resistors series-connected between first and second electrodes of the first capacitive element, and a third resistor series-connected with a third MOS transistor between a third node of application of a power supply voltage and the second node, the gate of the third transistor being coupled to the junction point of the first and second resistors, and the junction point of the third resistor and of the third transistor being coupled to the second gate of the first transistor.

According to an embodiment, the resonator comprises an inductance and a series association of first and second variable-capacitance capacitive elements.

According to an embodiment, the LC resonator is a differential resonator further comprising a fourth output node; the amplifier comprises at least one fourth dual-gate MOS transistor comprising first and second gates, coupling the fourth output node to the second node; and the regulation circuit is capable of applying said variable bias voltage to the second gate of the second transistor.

According to an embodiment, the amplifier comprises second and third capacitive elements respectively coupling the first gate of the first transistor to the fourth output node and the first gate of the fourth transistor to the first output node.

DETAILED DESCRIPTION OF THE PRESENT EMBODIMENTS

The same elements have been designated with the same reference numerals in the different drawings. In the present description, term “connected” is used to designate a direct electric connection, with no intermediate electronic component, for example, by means of one or a plurality of conductive tracks, and term “coupled” or term “linked” is used to designate either a direct electric connection (then meaning “connected”) or a connection via one or a plurality of intermediate components (resistor, capacitor, transistor, etc.). Unless otherwise specified, expressions “approximately”, “substantially”, and “in the order of” mean to within 10%, preferably to within 5%.

FIG. 1is an electric diagram of an example of an oscillator with a parallel LC resonator.

The oscillator ofFIG. 1comprises a parallel LC resonator101coupled between two output nodes Vout1and Vout2of the oscillator. Resonator101comprises an inductance L1having a first end coupled (connected in the shown example) to node Vout1and having its second end coupled (connected in the shown example) to node Vout2, the midpoint of inductance L1being coupled to a node VDDof application of a fixed (DC) power supply voltage. Resonator101further comprises, in parallel with inductance L1, two variable-capacitance capacitive elements CV1and CV2, for example, series-coupled variable-capacitance capacitors. More particularly, in the shown example, capacitive element CV1has a first electrode connected to the first end of inductance L1and a second electrode connected to a first electrode of capacitive element CV2, and capacitive element CV2has a second electrode connected to the second end of inductance L1. The values of the capacitances of elements CV1and CV2vary according to a control voltage applied to a control node Vctrlof the resonator, in the shown example, the junction point of elements CV1and CV2. In this example, the DC power supply voltage applied to node VDDand the control voltage applied to node Vctrlare referenced to a node GND of application of a reference potential of the oscillator, for example, the ground.

The oscillator ofFIG. 1further comprises an amplifier circuit103coupled in parallel with the LC resonator. Circuit103comprises a pair of MOS transistors T1and T2, in the shown example, N-channel transistors. Transistors T1and T2are for example identical to each other, to within manufacturing dispersions. Transistor T1couples node Vout1to node GND via its conduction nodes (drain and source), and transistor T2couples node Vout2to node GND via its conduction nodes. More particularly, in the shown example, the drain of transistor T1is connected to node Vout1, the drain of transistor T2is connected to node Vout2, and the sources of transistors T1and T2are connected to a same node S coupled to node GND. In this example, node S is coupled to node GND on the one hand by a current source I, and on the other hand by a capacitive element CT, for example, a capacitor, connected in parallel with current source I. Transistors T1and T2form a crossed differential pair, that is, the gate (g) of transistor T1is coupled (in this example, connected) to the drain of transistor T2, and the gate (g) of transistor T2is coupled (in this example, connected) to the drain of transistor T1.

The oscillator ofFIG. 1operates as follows. Amplifier circuit103behaves as a negative resistor coupled in parallel with resonator101, supplying power to resonator101to compensate for the inner resistance thereof. In steady state, amplifier circuit103ensures the holding of the oscillations of resonator101, output nodes Vout1and Vout2supplying two AC voltages substantially of same frequency (equal to the resonance frequency of resonator101) and of same amplitude, but in phase opposition. Calling L the total inductance of resonator101and C the total capacitance of resonator101, oscillation frequency f of circuit101can be expressed as follows: f=½π√{square root over (LC)}. This output frequency is voltage-controllable via node Vctrl.

The architecture ofFIG. 1has the advantage of having a robust start-up and of being simple to implement.

FIG. 2is an electric diagram of an example of a class-C oscillator with a parallel LC resonator.

The oscillator ofFIG. 2comprises a parallel LC resonator201coupled between two output nodes Vout1and Vout2of the oscillator.

Resonator201is for example identical to resonator101described in relation withFIG. 1.

The oscillator ofFIG. 2further comprises an amplifier circuit203coupled in parallel with the LC resonator. In this example, amplifier circuit203comprises the same elements as amplifier circuit103ofFIG. 1, arranged substantially in the same way, but differs from circuit103in that the gates (g) of transistors T1and T2are not directly connected to the drains of transistors T1and T2. Circuit203indeed comprises a capacitive decoupling element C1, for example, a capacitor, coupling the gate of transistor T1to the drain of transistor T2, and a capacitive decoupling element C2, for example, identical to element C1to within manufacturing dispersions, coupling the gate of transistor T2to the drain of transistor T1. Circuit203further comprises a circuit of application of a DC bias voltage to the gates of transistors T1and T2. More particularly, in this example, the gate of transistor T1is coupled to a node Vgbiasof application of a DC bias voltage via a resistor R1, and the gate of transistor T2is coupled to node Vgbiasvia a resistor R2, for example, identical to resistor R1to within manufacturing dispersions. Capacitive elements C1and C2are capable of preventing the transmission, onto output nodes Vout1and Vout2of the oscillator, of the DC bias voltage applied to node Vgbias, while transmitting onto the gates of transistors T1and T2the AC voltage delivered to output nodes Vout1and Vout2of the oscillator.

The operation of the oscillator ofFIG. 2is similar to that of the oscillator ofFIG. 1, to within the fact that, in the example ofFIG. 2, a DC bias voltage Vgbiassmaller than threshold voltage Vthof transistors T1and T2is applied to the gates of transistors T1and T2(via node Vgbias), so that transistors T1and T2behave as class-C amplifiers, that is, they have a conduction angle smaller than 180° of the phase of the amplifier signal (that is, the output oscillating signal of resonator LC).

The class-C biasing of amplifier circuit203enables to decrease both the phase noise and the power consumption of the oscillator as compared with architectures having a class-A operation of the type described in relation withFIG. 1.

The gain in terms of phase noise and of power consumption is all the higher as the bias voltage applied to the gates of transistors T1and T2is low. However, the application of too low a bias voltage to the gates of transistors T1and T2may prevent the starting of the oscillator.

The solutions described in these publications have the common point of applying to the gates of the MOS transistors of the amplifier circuit a first bias voltage for the start-up phase, and a second bias voltage smaller than the first voltage for the operation in steady state. The provided architectures are however complex. In particular, solutions providing a dynamic adjustment of the bias voltage applied to the gates of the MOS transistors of the amplifier circuit have the disadvantage of being invasive, since the gates of the MOS transistors of the amplifier circuit also receive the oscillating AC signal to be amplified. Thus, a malfunction of the circuits for controlling the bias voltage of the MOS transistors may cause a stopping of the oscillations and make the circuit unusable. Further, in the solutions described in the above-mentioned publications, to take into account, in particular, manufacturing and temperature dispersions, a security margin should be taken in the selection of the transistor bias point, to avoid risking an unwanted stopping of the oscillations. As a result, the optimal bias point in terms of phase noise and of power consumption cannot be reached.

FIG. 3is a simplified electric diagram illustrating an embodiment of a class-C oscillator with a parallel LC resonator.

The oscillator ofFIG. 3comprises a parallel LC resonator301coupled between output nodes Vout1and Vout2of the oscillator. Resonator301is for example identical to resonator201of the oscillator ofFIG. 2.

The oscillator ofFIG. 3further comprises an amplifier circuit303, coupled in parallel with resonator301. Amplifier circuit303ofFIG. 3is identical or similar to amplifier circuit203ofFIG. 2, to within the fact that, in circuit303ofFIG. 3, MOS transistors T1and T2are dual-gate MOS transistors.

Dual-gate MOS transistor here means a transistor comprising a channel-forming region laterally bordered, on the one hand, with a source region and, on the other hand, with a drain region, and further comprising a first control gate or front gate (fg), arranged above the channel-forming region and insulated from the channel-forming region by a dielectric layer, and a second control gate or back gate (bg), arranged under the channel-forming region. In such a transistor, the current flowing between the drain and the source of the transistor is a function not only of the potential applied to the front gate of the transistor, but also of the potential applied to the back gate thereof. In particular, the threshold voltage of the transistor, that is, the minimum voltage to be applied between the front gate and the source of the transistor to turn on the transistor, depends on the potential applied to the back gate of the transistor.

Transistors T1and T2are for example SOI-type (“semiconductor on insulator”) transistors, the back gate being then insulated from the channel-forming region by a dielectric layer. Preferably, transistors T1and T2are FDSOI-type (“Fully Depleted Semiconductor On Insulator”) transistors, that is, SOI transistors where the channel-forming region is fully depleted when the transistor is not biased. Indeed, in a FDSOI transistor, the variations of the control potential applied to the back gate of the transistor cause significant variations of the transistor threshold voltage, which is particularly adapted to the implementation of the embodiments which will be described, as will more clearly appear from the following description. The described embodiments are however not limited to the case where transistors T1and T2are of SOI or FDSOI type. More generally, the described embodiments apply to any types of MOS transistors with two control gates respectively arranged on the front side and on the back side of the channel-forming region of the transistor. As an example, the described embodiments are compatible with “bulk”-type MOS transistors, comprising a semiconductor bulk region arranged under the channel-forming region, having its upper surface in contact with the lower surface of the channel-forming region. In this case, the back gate is formed by the transistor bulk region, and is not insulated from the channel-forming region. As a variation, transistors T1and T2may be FinFET-type transistors.

The assembly of transistors T1and T2ofFIG. 3is similar to what has been described in relation withFIG. 2, the gates (g) of transistors T1and T2of the circuit ofFIG. 2being replaced with the front gates (fg) of transistors T1and T2in the circuit ofFIG. 3.

The oscillator ofFIG. 3further comprises a regulation circuit305coupled, on the one hand, to output nodes Vout1and Vout2of the oscillator and, on the other hand, to the back gates (bg) of transistors T1and T2. Circuit305is capable of applying to the back gates (bg) of transistors T1and T2a DC bias voltage Vbgwhich is a function of the amplitude of the oscillations of the output signal of the oscillator. More particularly, in this example, dual-gate transistors T1and T2are transistors having a negative threshold voltage variation, that is, the higher the bias voltage applied to their back gate, the lower their threshold voltage. In this case, circuit305is configured to apply to the back gates of transistors T1and T2a bias voltage Vbgwhich decreases as the oscillation amplitude increases. As an example, circuit305is configured to apply to the back gates of transistors T1and T2a voltage Vbgwhich continuously decreases according to the oscillation amplitude, between a maximum value Vbgmaxwhen the oscillation amplitude is zero, and a minimum value Vbgminwhen the oscillation amplitude reaches its maximum value. Value Vbgmaxis smaller than or equal to the maximum nominal back side bias voltage that transistors T1and T2can withstand, and value Vbgminis smaller than value Vbgmaxand greater than or equal to 0 V.

In operation, a fixed DC bias voltage is applied to the front gates of transistors T1and T2, via node Vgbias. Voltage Vgbiasis preferably selected to be greater than or equal to minimum threshold voltage Vthminof transistors T1and T2, that is, the threshold voltage of transistors T1and T2when their back gates are biased to voltage Vbgmax. Thereby, transistors T1and T2have a class-B, -AB, or -A biasing at the starting of the oscillator, that is, when the amplitude of the oscillations of the output signal is zero. This guarantees a robust start-up of the oscillator.

When the oscillator starts, an oscillating signal appears on its output nodes Vout1, Vout2. Circuit305then continuously modifies the bias voltage Vbgapplied to the back gates of transistors T1and T2according to the amplitude of the oscillations of the signal delivered to nodes Vout1, Vout2. In steady state, voltage Vbgreaches its minimum value Vbgmin, and the threshold voltage of transistors T1and T2accordingly reaches its maximum value Vthmax. The fixed bias voltage Vgbiasapplied to the front gates (fg) of transistors T1and T2is selected to be smaller than maximum threshold voltage Vthmaxof transistors T1and T2, to obtain a class-C biasing of transistors T1and T2in steady state.

In the shown example, circuit305comprises a first sub-circuit3051connected, on the one hand, to node Vout1and, on the other hand, to the back gate (bg) of transistor T1, and a second sub-circuit3052connected, on the one hand, to node Vout2and, on the other hand, to the back gate (bg) of transistor T2. In this example, sub-circuit3051comprises a rectifying and filtering circuit3071, or envelope detection circuit, connected to node Vout1and capable of delivering, on an output node N1, a voltage representative of the envelope of the oscillating signal present on node Vout1. Sub-circuit3051further comprises a shaping circuit3091connected to node N1and capable of applying, to the back gate (bg) of transistor T1, a bias voltage which is a function of the amplitude of the envelope signal delivered by envelope detector3071to node N1. Similarly, sub-circuit3052comprises a rectifying and filtering circuit3072, or envelope detection circuit, connected to node Vout2and capable of delivering, on an output node N2, a voltage representative of the envelope of the oscillating signal present on node Vout2. Sub-circuit3052further comprises a shaping circuit3092connected to node N2and capable of applying, to the back gate (bg) of transistor T2, a bias voltage which is a function of the amplitude of the envelope signal delivered by envelope detector3072to node N2. Sub-circuits3051and3052are for example identical, to within manufacturing dispersions. In practice, the bias voltage applied to the back gate (bg) of transistor T1is substantially identical to the bias voltage applied to the back gate (bg) of transistor T2. As a variation, only one of the two sub-circuits3051and3052may be provided, and the output of this sub-circuit may be connected both to the back gate (bg) of transistor T1and to the back gate (bg) of transistor T2. The arrangement shown inFIG. 3comprising two separate identical sub-circuits3051and3052for the biasing of transistors T1and T2is however preferably since it enables to symmetrize the load seen by output nodes Vout1and Vout2of the resonator.

FIG. 4is an electric diagram shown in further detail an example of implementation of the oscillator ofFIG. 3. More particularly,FIG. 4shows in further detail an embodiment of regulation circuit305of the oscillator ofFIG. 3.

In this example, envelope detection circuit3071of sub-circuit3051comprises a diode-assembled MOS transistor M11, which couples node Vout1to node N1. In this example, transistor M11is an N-channel transistor, having its conduction nodes respectively connected to node Vout1and to node N1, and having its gate connected to node Vout1. Transistor M11may be a single-gate or a dual-gate transistor. In the shown example, transistor M11is a dual-gate transistor having its back gate connected to ground (node GND) and having its front gate connected to node Vout1. Envelope detection circuit3071further comprises a capacitive element C11, for example, a capacitor, connected between node N1and node GND.

Shaping circuit3091comprises two resistors R11and R12series-connected between node N1and node GND, in parallel with capacitive element C11of circuit3071. Resistors R11and R12form a first voltage dividing bridge lowering the level of the envelope voltage delivered by circuit3071on node N1. Circuit3091further comprises a resistor R13series-connected with a MOS transistor M12between nodes VDD and GND. More particularly, in the shown example, transistor M12is an N-channel transistor having its drain coupled to node VDD via resistor R13and having its source connected to node GND. The gate of transistor M12is coupled to the output node of the voltage dividing bridge formed by resistors R11and R12, that is, to the junction point of resistors R11and R12. Transistor M12may be a single-gate transistor or a dual-gate transistor. In the shown example, transistor M12is a dual-gate transistor having its back gate connected to ground (node GND) and having its front gate connected to the junction point of resistors R11and R12. Resistor R13and transistor M12form together a second resistive voltage dividing bridge delivering a voltage having a level which is all the lower as the resistance of transistor M12is low, that is, as the voltage level on node N1is high. The output node of the voltage dividing bridge formed by resistor R13and transistor M12, that is, the junction point of resistor R13and of transistor M12, is connected to the back gate (bg) of transistor T1.

Similarly, envelope detection circuit3072of sub-circuit3052comprises a diode-assembled MOS transistor M21, coupling node Vout1to node N2, and a capacitive element C21connected between node N2and node GND. Further, shaping circuit3092comprises two resistors R21and R22series-connected between node N2and node GND, in parallel with capacitive element C21. Circuit3092further comprises a resistor R23series-connected with a MOS transistor M22between nodes VDD and GND, the gate of transistor M22being coupled to the junction point of resistors R21and R22, and the junction point of resistor R23and of transistor M22being coupled to the back gate (bg) of transistor T2.

An advantage of the embodiments described in relation withFIGS. 3 and 4is the self-regulation of the bias point of transistors T1and T2. Indeed, circuit305automatically places the bias point of transistors T1and T2at an optimal level in terms of power consumption, while preventing any risk of interrupting the oscillations. In particular, when the bias voltage Vbgapplied by circuit305to the back gate of transistors T1and T2becomes too low, the amplitude of the oscillations of the output signal of resonator301starts decreasing, which results in increasing back voltage Vbgand thus in restoring the amplitude of the oscillations. Thus, in steady state, bias voltage Vbgautomatically settles at an optimal level in terms of power consumption and of phase noise. This is a noticeable difference with respect to the above-mentioned publications where a security margin has to be provided in the selection of the class-C bias point of transistors, to take into account possible manufacturing and/or temperature dispersions.

Another advantage of the described embodiments is that the dynamic adjustment of the bias point of transistors T1and T2in order to, in a first phase, satisfy the oscillator start-up conditions and, in a second phase, obtain a class-C operation providing a good performance in terms of phase noise and of power consumption, is performed via the back gates of transistors T1and T2. Thus, regulation circuit305is non-invasive, since the bias voltage dynamically modified by circuit305is not superimposed to the high-frequency oscillating signal to be amplified. Bias voltage Vgbiasapplied to the front gate of transistors T1and T2remains constant during the oscillator operation.

Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, the described embodiments are not limited to the example of parallel LC resonators301shown inFIGS. 3 and 4. More generally, the described embodiments are compatible with any other parallel LC resonator architecture having a voltage-controlled resonance frequency.

Further, the described embodiments are not limited to the specific example of layout of amplifier circuit303shown inFIGS. 3 and 4. More generally, the embodiments are compatible with other architectures of an amplifier circuit comprising a crossed differential pair of dual-gate MOS transistors.

Further, the described embodiments are not limited to the specific examples of implementation of regulation circuit305described in relation withFIGS. 3 and 4. More generally, other regulation circuits capable of implementing the desired operation may be provided.

Further, the described embodiments may be adapted to the case where transistors T1and T2are transistors having a positive threshold voltage variation.

Further, embodiments of oscillators with a differential LC resonator have been described hereabove. The above-described embodiments may however be adapted to oscillators having a non-differential LC resonator, that is, where the output oscillating signal of the oscillator is referenced to ground.

FIG. 5is an electric diagram illustrating an embodiment of a class-C oscillator with a non-differential LC resonator.

The oscillator ofFIG. 5comprises an LC resonator501comprising an inductance L1having a first end coupled to a node VDDof application of a fixed (DC) power supply voltage and having its second end coupled to an output node Vout1of the oscillator. Resonator501further comprises two variable-capacitance capacitive elements CV1and CV2, for example, series-coupled variable-capacitance capacitors. More particularly, in the shown example, capacitive element CV1has a first electrode coupled to node Vout1and a second electrode connected to a first electrode of capacitive element CV2, and capacitive element CV2has a second electrode coupled to a node GND of application of a reference potential of the oscillator, for example, the ground. The values of the capacitances of elements CV1and CV2vary according to a control voltage applied to a control node Vctr1of the resonator, in the shown example, the junction point of elements CV1and CV2.

The oscillator ofFIG. 5further comprises an amplifier circuit503coupled to the LC resonator. Circuit503comprises a MOS transistor T1, in the shown example, an N-channel transistor. Transistor T1couples node Vout1to node GND via its conduction nodes. More particularly, in the shown example, the drain of transistor T1is connected to node Vout1and the source of transistor T1is coupled to node GND by a current source i. In the same way as in the examples ofFIGS. 3 and 4, transistor T1is a dual-gate transistor. The front gate (fg) of transistor T1is coupled to a node Vgbiasof application of a DC bias voltage.

The oscillator ofFIG. 5further comprises a regulation circuit505coupled, on the one hand, to output node Vout1of the oscillator and, on the other hand, to the back gate (bg) of transistors T1. As circuit305ofFIGS. 3 and 4, circuit505is capable of applying to the back gate (bg) of transistor T1a DC bias voltage Vbgwhich is a function of the amplitude of the oscillations of the output signal of the oscillator. In the shown example, sub-circuit505comprises a rectifying and filtering circuit507, connected to node Vout1and capable of delivering, on an output node N, a voltage representative of the envelope of the oscillating signal present on node Vout1. Circuit507is for example identical or similar to circuit3071described in relation withFIGS. 3 and 4. Circuit505further comprises a shaping circuit509connected to node N and capable of applying, to the back gate (bg) of transistor T1, a bias voltage which is a function of the amplitude of the envelope signal delivered by envelope detector507on node N. Circuit509is for example identical or similar to circuit3091described in relation withFIGS. 3 and 4.

The operation of the oscillator ofFIG. 5is similar to the above-described operation of the differential oscillators. Amplifier circuit503behaves as a negative resistor coupled with resonator501, supplying power to resonator501to compensate for the inner resistance thereof. In steady state, amplifier circuit503ensures the holding of the oscillations of resonator501, output node Vout1delivering an AC voltage referenced to ground, having a frequency equal to the resonance frequency of resonator501. A DC bias voltage Vgbiasis applied to the gate of transistor T1(via node Vgbias). Voltage Vgbiasis preferably selected to be greater than or equal to minimum threshold voltage Vthminof transistor T1, so that transistor T1has a class-B, -AB, or -A biasing at the starting of the oscillator. When the oscillator starts, an oscillating signal appears on its output node Vout1. Circuit505then continuously modifies the bias voltage Vbgapplied to the back gate of transistor T1according to the oscillation amplitude. In steady state, voltage Vbgreaches its minimum value Vbgmin, and the threshold voltage of transistor T1accordingly reaches its maximum value Vthmax. The fixed bias voltage Vgbiasapplied to the front gate of transistor T1is selected to be smaller than maximum threshold voltage Vthmaxof transistor T1, to obtain a class-C biasing of transistor T1in steady state.