Semiconductor device assembly having a stress-relieving buffer layer

Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface material is used in conjunction with a semiconductor device assembly of a chip carrier substrate, a heat spreader for attaching to the substrate, a semiconductor device mounted on the substrate and underneath the heat spreader and the multilayer thermal interface material interposed between the heat spreader and the semiconductor device. The heat spreader has a first coefficient of thermal expansion (CTE), CTE1, the buffer layer has a second CTE, CTE2, and the semiconductor device has a third CTE, CTE3, wherein CTE1>CTE2>CTE3.

BACKGROUND OF THE INVENTION

The present invention relates to a thermal interface material and package thermal design for a semiconductor device which includes a stress-relieving buffer layer.

A flip chip package, more specifically an organic flip chip package, including a flip chip on a multi-layer carrier, inherently warps within a predetermined temperature range because of the coefficient of thermal expansion (CTE) mismatch between the flip chip and the multi-layer carrier. For example, a chip may have a CTE of 3 ppm/° C. while an organic chip carrier may have a CTE of 17-24 ppm/° C. Such a CTE mismatch can lead to bending of the carrier. If a heat spreader or lid is attached to the back surface of a chip with a thermal interface material, such as a thermally conductive grease, an uneven grease-filled gap can result between the chip and the heat spreader or lid. The thermal interface material can also be stretched as a result of the bending of the carrier which can impact thermal performance adversely. In a severe situation, cracking or debonding of the thermal interface material can occur.

BRIEF SUMMARY OF THE INVENTION

The various advantages and purposes of the present invention as described above and hereafter are achieved by providing, according to a first aspect of the invention, a heat spreader assembly comprising:

a heat spreader for a chip carrier substrate, the heat spreader having a first coefficient of thermal expansion, CTE1;

a multilayer thermal interface material in contact with the heat spreader, the thermal interface material comprising a first layer of metallic thermal interface material in contact with the heat spreader and a buffer layer in contact with the first layer of metallic thermal interface material, the buffer layer having a second coefficient of thermal expansion CTE2 wherein CTE1>CTE2.

According to a second aspect of the invention, there is provided a semiconductor device assembly comprising:

a chip carrier substrate;

a heat spreader for attaching to the substrate, the heat spreader having a first coefficient of thermal expansion, CTE1;

a semiconductor device mounted on the substrate and underneath the heat spreader, the semiconductor device having a third coefficient of thermal expansion, CTE3;

a multilayer thermal interface material interposed between the heat spreader and the semiconductor device, the thermal interface material comprising a first layer of metallic thermal interface material in contact with the heat spreader and a buffer layer in contact with the first layer of metallic thermal interface material, the buffer layer having a second coefficient of thermal expansion, CTE2 wherein CTE1>CTE2>CTE3.

According to a third aspect of the present invention, there is provided a semiconductor device assembly comprising:

a chip carrier substrate;

a semiconductor device mounted on the substrate, the semiconductor device having a first coefficient of thermal expansion, CTE1;

a multilayer thermal interface material on the semiconductor device, the thermal interface material comprising a first layer of metallic thermal interface material and a buffer layer in contact with the first layer of metallic thermal interface material, the buffer layer having a second coefficient of thermal expansion, CTE2 wherein CTE1>CTE2 and a layer of thermal interface material in contact with the buffer layer and the semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

Referring to the Figures in more detail, and particularly referring toFIG. 1, there is shown a side view of a prior art semiconductor device assembly10. The semiconductor device assembly10includes a chip carrier substrate12, such as an organic chip carrier, upon which a chip14, hereafter referred to as a semiconductor device, is mounted in the so-called flip chip position. By flip chip, it is meant that the semiconductor device14is mounted active side down and the semiconductor device14makes connections to the substrate12through solder balls16or other well-known electrical connections. There may also be a conventional underfill material18. The semiconductor device assembly10may also include a lid or heat spreader20(hereafter collectively referred to as just “heat spreader”) which removes heat generated by the semiconductor device14. The heat spreader20may be supported by legs22which are firmly attached to the substrate12by adhesive24. Lastly, in order to have good thermal contact between the semiconductor device14and the heat spreader20, there is also a conventional thermal interface material26. The conventional thermal interface material26may comprise a nonmetallic thermal grease, paste or gel.

In practice, the coefficient of thermal expansion (CTE) mismatch between the semiconductor device14and the substrate12can lead to bending of the substrate12and the device14and thus stretching of the thermal interface material26which can lead to cracking or debonding of the thermal interface material26from the semiconductor device14. This cracking or debonding of the thermal interface material26can occur at the interface28(shown inFIG. 1) between the thermal interface material26and the semiconductor device14or at the interface29between the thermal interface material26and the heat spreader20.

Referring now toFIG. 2, there is shown a side view of a semiconductor assembly according to the present invention. There is shown a semiconductor device assembly110comprising a semiconductor device114mounted on a chip carrier substrate112. The semiconductor device114makes electrical connection with the substrate112through solder balls116or other electrical connection devices known to those skilled in the art. The semiconductor device114may have an underfill material118around and underneath the semiconductor device114. The semiconductor device assembly110further comprises a heat spreader120which may have legs122which are fixed to the substrate112by adhesive124. In order to remove heat from the semiconductor device114, the present invention further comprises a multilayer thermal interface material, generally indicated by126.

The multilayer thermal interface material126includes a first layer128of metallic thermal interface material in contact with the heat spreader120. Suitable materials for the first layer128of metallic thermal interface material include indium (by itself as elemental indium) and low melt solder alloys such as 97% indium/3% silver and 58% bismuth/42% tin (by weight percent). The material should be such that it is capable of reflowing at a low temperature to fuse to the heat spreader120if desired.

The multilayer thermal interface material126further includes a buffer layer130in contact with the first layer128of metallic thermal interface material. The purpose of the buffer layer130is as follows. The heat spreader120has a CTE of about 17 ppm/° C. (similar to that of the chip carrier substrate112) while the semiconductor device114has a CTE of about 3 ppm/° C. This large mismatch in CTE between the heat spreader120and semiconductor device114can lead to stresses in the thermal interface material126. To relieve those stresses, buffer layer130having an intermediate CTE value is inserted between the first layer128of metallic thermal interface material and the semiconductor device114. In other words, where the CTE of heat spreader120is CTE1, the CTE of buffer layer130is CTE2 and the CTE of semiconductor device114is CTE3, then CTE1>CTE2>CTE3. More precisely, buffer layer130should be chosen from a material having the following properties:

a CTE between that of the semiconductor device and the heat spreader, and preferably closer to the semiconductor device than the heat spreader;

thermal conductivity between that of the heat spreader120and first layer128of the thermal interface material126;

readily manufacturable into a thin, flat plate;

should be available in thin sheets in the range of hundreds of microns; and

competitive in cost with a thermal interface material consisting entirely of first layer128.

Some materials meeting these requirements include alloys of aluminum/silicon/carbon (AlSiC), tungsten and copper (W/Cu), and molybdenum and copper (MoCu) and laminates of copper, molybdenum and copper (Cu/Mo/Cu).

As can be seen fromFIGS. 2 and 3, the first layer128of metallic thermal interface material and buffer layer130extend beyond the dimensions of the semiconductor device114.

FIGS. 2 and 3also illustrate two other preferred features of the present invention. One of these preferred features is standoffs134in the first layer128of metallic thermal interface material. The standoffs134ensure consistent thermal interface material thickness between the heat spreader120and buffer layer130. Moreover, the standoffs134can act as crack stops. As best shown inFIG. 3, the standoffs134can be only segments (FIG. 3B) or may circle the entire chip circumference (FIG. 3D).

Another of the preferred features is for the buffer layer120to have perforations136, as best shown inFIGS. 3C and 3D. The perforations eliminate any additional thermal resistance due to the presence of the buffer layer120, especially over hot spot regions. The perforations136may be used without standoffs as shown inFIG. 3Cor with standoffs134as shown inFIG. 3D. The perforations136may take on any shape that allows for the reduction of thermal resistance. The flexibility provided by this invention to use rounded corners for the first metallic layer128of the thermal interface material126also helps reduce the high stress concentrations caused by sharp corners in conventional designs.

In one preferred embodiment, there is an additional layer132of thermal interface material in contact with the buffer layer130. Referring again toFIG. 2, the additional layer132of thermal interface material is placed between the buffer layer130and the semiconductor device114. In one preferred embodiment, the additional layer132of thermal interface material may be made of a metallic material similar to first layer128of metallic thermal interface material. Again, suitable materials include indium (by itself as elemental indium) and low melt solder alloys such as 97% indium/3% silver and 58% bismuth/42% tin (by weight percent). While the additional layer132of thermal interface material and the first layer128of metallic thermal interface material may be made of the same material, this is not required and they may be made of different metallic materials so long as they are both made from the suitable materials mentioned above.

In one preferred embodiment, the additional layer132of thermal interface material may alternatively be made of a nonmetallic material such as a thermal gel, paste or grease. These are conventional materials which are classified as nonmetallic materials although they may contain metallic or nonmetallic high conductivity particles for thermal conductivity.

FIG. 5is an enlarged side view of the multilayer thermal interface material126showing the first layer128of metallic thermal interface material, buffer layer130, additional layer132of thermal interface material, optional standoffs134and optional perforation136.

FIGS. 4A and 4Billustrate two methodologies for assembling the semiconductor device assembly110according to the present invention. Turning first toFIG. 4A, the multilayer thermal interface material126comprising first layer128of metallic thermal interface material, buffer layer130and a second layer132of metallic thermal interface material is assembled and then placed on the semiconductor device114. It may be desirable to metalize the surface140of semiconductor device114with, for example, nickel or gold, prior to placing the multilayer thermal interface material126on the semiconductor device114. Thereafter, heat spreader120is placed on the multilayer thermal interface material126and then the entire assembly is heated to a predetermined temperature to reflow the first layer128of metallic thermal interface material and the second metallic layer of thermal interface material132.

FIG. 4Billustrates the second methodology for forming the semiconductor device assembly110according to the present invention. The first layer128of metallic thermal interface material and buffer layer130are placed against the heat spreader120. The first layer128of metallic thermal interface material should be in direct contact with the heat spreader120. This subassembly is heated to a predetermined temperature to reflow the first layer128of metallic thermal interface material. Thereafter, a second layer132of thermal interface material is placed on semiconductor device114followed by the first layer128of metallic thermal interface material, buffer layer130and heat spreader120. Second layer132of thermal interface material may be metallic (for example, indium or low melt solder alloy) or nonmetallic (thermal gel, paste or grease). If the second layer132of thermal interface material is metallic, then surface140of semiconductor device114may need to be metalized.

The advantages of the present invention include reducing stress raisers at semiconductor device corners, thus reducing cracking tendency of the thermal interface material126(either cohesively or adhesively at either of the interface with the heat spreader120or the semiconductor device114) and eliminating stress raisers between the buffer layer130and the heat spreader120, thus reducing cracking tendency.