Microelectronic devices and electronic systems

A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Microelectronic devices, electronic systems, and additional methods are also described.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 17/364,281, filed Jun. 30, 2021, listing Fatma Arzum Simsek-Ege, Kunal R. Parekh, Terrence B. McDaniel, and Beau D. Barry as inventors, for “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS.” This application is also related to U.S. patent application Ser. No. 17/364,377, filed Jun. 30, 2021, listing Fatma Arzum Simsek-Ege and Kunal R. Parekh as inventors, for “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS.” This application is also related to U.S. patent application Ser. No. 17/364,429, filed Jun. 30, 2021, listing Fatma Arzum Simsek-Ege as inventor, for “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS.” This application is also related to U.S. patent application Ser. No. 17/364,476, filed Jun. 30, 2021, listing Fatma Arzum Simsek-Ege and Kunal R. Parekh as inventors, for “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS.” This application is also related to U.S. patent application Ser. No. 17/364,379, filed Jun. 30, 2021, listing Fatma Arzum Simsek-Ege as inventor, for “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS.” The disclosure of each of the foregoing documents is hereby incorporated herein in its entirety by reference.

TECHNICAL FIELD

The disclosure, in various embodiments, relates generally to the field of microelectronic device design and fabrication. More specifically, the disclosure relates to methods of forming microelectronic devices and memory devices, and to related microelectronic devices, memory devices, and electronic systems.

BACKGROUND

Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, microelectronic device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified, easier and less expensive to fabricate designs.

One example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory devices including, but not limited to, volatile memory devices. One type of volatile memory device is a dynamic random access memory (DRAM) device. A DRAM device may include a memory array including DRAM cells arranged rows extending in a first horizontal direction and columns extending in a second horizontal direction. In one design configuration, an individual DRAM cell includes an access device (e.g., a transistor) and a storage node device (e.g., a capacitor) electrically connected to the access device. The DRAM cells of a DRAM device are electrically accessible through digit lines and word lines arranged along the rows and columns of the memory array and in electrical communication with control logic devices within a base control logic structure of the DRAM device.

Control logic devices within a base control logic structure underlying a memory, array of a DRAM device have been used to control operations on the DRAM cells of the DRAM device. Control logic devices of the base control logic structure can be provided in electrical communication with digit lines and word lines coupled to the DRAM cells by way of routing and contact structures. Unfortunately, processing conditions (e.g., temperatures, pressures, materials) for the formation of the memory array over the base control logic structure can limit the configurations and performance of the control logic devices within the base control logic structure. In addition, the quantities, dimensions, and arrangements of the different control logic devices employed within the base control logic structure can also undesirably impede reductions to the size (e.g., horizontal footprint) of a memory device, and/or improvements in the performance (e.g., faster memory cell ON/OFF speed, lower threshold switching voltage requirements, faster data transfer rates, lower power consumption) of the DRAM device.

DETAILED DESCRIPTION

The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art would understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device). The structures described below do not form a complete microelectronic device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form a complete microelectronic device from the structures may be performed by conventional fabrication techniques.

As used herein, a “memory device” means and includes microelectronic devices exhibiting memory functionality, but not necessarily limited to memory functionality. Stated another way, and by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory; conventional non-volatile memory), but also includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device combining logic and memory, and a graphics processing unit (GPU) incorporating memory.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the figures, a “horizontal” or “lateral” direction may be perpendicular to an indicated “Z” axis, and may be parallel to an indicated “X” axis and/or parallel to an indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, features (e.g., regions, structures, devices) described as “neighboring” one another means and includes features of the disclosed identity (or identities) that are located most proximate (e.g., closest to) one another. Additional features (e.g., additional regions, additional structures, additional devices) not matching the disclosed identity (or identities) of the “neighboring” features may be disposed between the “neighboring” features. Put another way, the “neighboring” features may be positioned directly adjacent one another, such that no other feature intervenes between the “neighboring” features; or the “neighboring” features may be positioned indirectly adjacent one another, such that at least one feature having an identity other than that associated with at least one the “neighboring” features is positioned between the “neighboring” features. Accordingly, features described as “vertically neighboring” one another means and includes features of the disclosed identity (or identities) that are located most vertically proximate (e.g., vertically closest to) one another. Moreover, features described as “horizontally neighboring” one another means and includes features of the disclosed identity (or identities) that are located most horizontally proximate (e.g., horizontally closest to) one another.

As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct Ohmic connection or through an indirect connection (e.g., by way of another structure).

As used herein, “insulative material” means and includes electrically insulative material, such one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiOxCy)), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiCxOyHz)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)). Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxCy, SiCxOyHz, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including insulative material.

As used herein, the term “homogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) do not vary throughout different portions (e.g., different horizontal portions, different vertical portions) of the feature. Conversely, as used herein, the term “heterogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) vary throughout different portions of the feature. If a feature is heterogeneous, amounts of one or more elements included in the feature may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the feature. The feature may, for example, be formed of and include a stack of at least two different materials.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. In addition, unless the context indicates otherwise, removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical-mechanical planarization (CMP)), or other known methods.

FIGS.1through12are various views (described in further detail below) illustrating different processing stages of a method of forming a microelectronic device (e.g., a memory device, such as a DRAM device), in accordance with embodiments of the disclosure. With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods described herein may be used for forming various devices. In other words, the methods of the disclosure may be used whenever it is desired to form a microelectronic device. With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods and structures described herein may be used to form various devices and electronic systems.

FIG.1shows a simplified plan view of a first microelectronic device structure100(e.g., a first wafer) at an early processing stage of a method of forming a microelectronic device (e.g., a memory device, such as a DRAM device), in accordance with embodiments of the disclosure. As shown inFIG.1, the first microelectronic device structure100may be formed to include array regions102, digit line exit regions104(also referred to as “digit line contact socket regions”) interposed between pairs of the array regions102horizontally neighboring one another in a first horizontal direction (e.g., the Y-direction), word line exit regions106(also referred to as “word line contact socket regions”) interposed between additional pairs of the array regions102horizontally neighboring one another in a second horizontal direction (e.g., the X-direction) orthogonal to the first horizontal direction, and one or more socket regions108(also referred to as “back end of line (BEOL) contact socket regions”) horizontally neighboring some of the array regions102in one or more of the first horizontal direction and the second horizontal direction. The array regions102, the digit line exit regions104, the word line exit regions106, and the socket regions108are each described in further detail below.

The array regions102of the first microelectronic device structure100may comprise horizontal areas of the first microelectronic device structure100configured and positioned to have arrays of memory cells (e.g., arrays of DRAM cells) subsequently formed within horizontal boundaries thereof, as described in further detail below. In addition, the array regions102may also be configured and positioned to have desirable arrangements of control logic devices subsequently formed within horizontal boundaries thereof, as also described in further detail below. The control logic devices to be formed within the horizontal boundaries of the array regions102may be formed to be vertically offset (e.g., in the Z-direction) from the memory cells to be formed within the horizontal boundaries of the array regions102.

The first microelectronic device structure100may be formed to include a desired quantity of the array regions102. For clarity and ease of understanding of the drawings and related description,FIG.1depicts the first microelectronic device structure100as being formed to include four (4) array regions102: a first array region102A, a second array region102B, a third array region102C, and a fourth array region102D. As shown inFIG.1, the second array region102B may horizontally neighbor the first array region102A in the Y-direction, and may horizontally neighbor the fourth array region102D in the X-direction; the third array region102C may horizontally neighbor the first array region102A in the X-direction, and may horizontally neighbor the fourth array region102D in the Y-direction; and the fourth array region102D may horizontally neighbor the third array region102C in the Y-direction, and may horizontally neighboring the second array region102B in the Y-direction. In additional embodiments, the first microelectronic device structure100is formed to include a different number of array regions102. For example, the first microelectronic device structure100may be formed to include greater than four (4) array regions102, such as greater than or equal to eight (8) array regions102, greater than or equal to sixteen (16) array regions102, greater than or equal to thirty-two (32) array regions102, greater than or equal to sixty-four (64) array regions102, greater than or equal to one hundred twenty eight (128) array regions102, greater than or equal to two hundred fifty six (256) array regions102, greater than or equal to five hundred twelve (512) array regions102, or greater than or equal to one thousand twenty-four (1024) array regions102.

In addition, the first microelectronic device structure100may be formed to include a desired distribution of the array regions102. As shown inFIG.1, in some embodiments, the first microelectronic device structure100is formed to include rows103of the array regions102extending in the X-direction, and columns105of the array regions102extending in the Y-direction. The rows103of the array regions102may, for example, include a first row including the first array region102A and the third array region102C, and a second row including the second array region102B and the fourth array region102D. The columns105of the array regions102may, for example, include a first column including the first array region102A and the second array region102B, and a second column including the third array region102C and the fourth array region102D.

With continued reference toFIG.1, the digit line exit regions104of the first microelectronic device structure100may comprise horizontal areas of the first microelectronic device structure100configured and positioned to have at least some subsequently formed digit lines (e.g., bit lines, data lines) horizontally terminate therein. For an individual digit line exit region104, at least some subsequently formed digit lines operatively associated with the array regions102flanking (e.g., at opposing boundaries in the Y-direction) the digit line exit region104may have ends within the horizontal boundaries of the digit line exit region104. In addition, the digit line exit regions104may also be configured and positioned to include contact structures and routing structures with the horizontal boundaries thereof that are operatively associated with at least some of the subsequently formed digit lines. As described in further detail below, some of the contact structures to be formed within the digit line exit regions104may couple the subsequently formed digit lines to control logic circuitry of control logic devices (e.g., sense amplifier (SA) devices) to subsequently be formed within the array regions102. As shown inFIG.1, in some embodiments, the digit line exit regions104horizontally extend in the X-direction, and are horizontally interposed between horizontally neighboring rows of the array regions102in the Y-direction. The digit line exit regions104may, for example, horizontally alternate with the rows of the array regions102in the Y-direction.

An individual digit line exit region104may be divided into multiple subregions. For example, as shown inFIG.1, an individual digit line exit region104may include first digit line exit subregions104A and second digit line exit subregions104B. In some embodiments, the first digit line exit subregions104A horizontally alternate with the second digit line exit subregions104B in the X-direction. A pair (e.g., two (2)) of horizontally neighboring array regions102within an individual column of the array regions102may include one (1) of the first digit line exit subregions104A and one (1) of the second digit line exit subregions104B positioned horizontally therebetween in the Y-direction. By way of non-limiting example, the first array region102A and the second array region102B of a first column of the array regions102may include one (1) of the first digit line exit subregions104A and one (1) of the second digit line exit subregions104B positioned therebetween in the Y-direction. The one (1) of the first digit line exit subregions104A and the one (1) of the second digit line exit subregions104B may be at least partially (e.g., substantially) confined with horizontal boundaries in the X-direction of the first array region102A and the second array region102B.

As described in further detail below, an individual first digit line exit subregion104A may be configured and positioned to facilitate electrical connections between a group of digit lines (e.g., odd digit lines or even digit lines) and a group of control logic devices (e.g., odd SA devices or even SA devices) operatively associated with a portion (e.g., a half portion in the X-direction) of one (1) array region102(e.g., the first array region102A) of a pair of horizontally neighboring array regions102, and to also facilitate electrical connections between a group of additional digit lines (e.g., additional odd digit lines or additional even digit lines) and a group of additional control logic devices (e.g., additional odd SA devices or additional even SA devices) operatively associated with a corresponding portion (e.g., a corresponding half portion in the X-direction) of an additional array region102(e.g., the second array region102B) of the pair of horizontally neighboring array regions102. In addition, as also described in further detail below, an individual second digit line exit subregion104B may be configured and positioned to facilitate electrical connections between a group of further digit lines and a group of further control logic devices operatively associated with another portion (e.g., another half portion in the X-direction) of the one (1) array region102(e.g., the first array region102A), and to also facilitate electrical connections between a group of yet further digit lines and a group of yet further control logic devices operatively associated with a corresponding another portion (e.g., a corresponding another half portion in the X-direction) of the additional array region102(e.g., the second array region102B).

Still referring toFIG.1, the word line exit regions106of the first microelectronic device structure100may comprise horizontal areas of the first microelectronic device structure100configured and positioned to have at least some subsequently formed word lines (e.g., access lines) horizontally terminate therein. For an individual word line exit region106, at least some subsequently formed word lines operatively associated with the array regions102flanking (e.g., at opposing boundaries in the X-direction) the word line exit region106may have ends within the horizontal boundaries of the word line exit region106. In addition, the word line exit regions106may also be configured and positioned to include contact structures and routing structures within the horizontal boundaries thereof that are operatively associated with the subsequently formed word lines. As described in further detail below, some of the contact structures to be formed within the word line exit regions106may couple the subsequently formed word lines to control logic circuitry of additional control logic devices (e.g., sub-word line driver (SWD) devices) to subsequently be formed within the array regions102. As shown inFIG.1, in some embodiments, the word line exit regions106horizontally extend in the Y-direction, and are horizontally interposed between horizontally neighboring columns of the array regions102in the X-direction. The word line exit regions106may, for example, horizontally alternate with the columns of the array regions102in the X-direction.

An individual word line exit region106may be divided into multiple subregions. For example, as shown inFIG.1, an individual word line exit region106may include first word line exit subregions106A and second word line exit subregions106B. In some embodiments, the first word line exit subregions106A horizontally alternate with the second word line exit subregions106B in the Y-direction. A pair (e.g., two (2)) of horizontally neighboring array regions102within an individual row of the array regions102may include one (1) of the first word line exit subregions106A and one (1) of the second word line exit subregions106B positioned horizontally therebetween in the X-direction. By way of non-limiting example, the first array region102A and the third array region102C of a first row of the array regions102may include one (1) of the first word line exit subregions106A and one (1) of the second word line exit subregions106B positioned therebetween in the X-direction. The one (1) of the first word line exit subregions106A and the one (1) of the second word line exit subregions106B may be at least partially (e.g., substantially) confined with horizontal boundaries in the Y-direction of the first array region102A and the third array region102C.

As described in further detail below, an individual first word line exit subregion106A may be configured and positioned to facilitate electrical connections between a group of word lines (e.g., odd word lines or even word lines) and a group of control logic devices (e.g., odd SWD devices or even SWD devices) operatively associated with a portion (e.g., a half portion in the Y-direction) of one (1) array region102(e.g., the first array region102A) of a pair of horizontally neighboring array regions102, and to also facilitate electrical connections between a group of additional word lines (e.g., additional odd word lines or additional even word lines) and a group of additional control logic devices (e.g., additional odd SWD devices or additional even SWD devices) operatively associated with a corresponding portion (e.g., a corresponding half portion in the Y-direction) of a further array region102(e.g., the third array region102C) of the pair of horizontally neighboring array regions102. In addition, as also described in further detail below, an individual second word line exit subregion106B may be configured and positioned to facilitate electrical connections between a group of further word lines and a group of further control logic devices operatively associated with another portion (e.g., another half portion in the Y-direction) of the one (1) array region102(e.g., the first array region102A), and to also facilitate electrical connections between a group of yet further word lines and a group of yet further control logic devices operatively associated with a corresponding another portion (e.g., a corresponding another half portion in the Y-direction) of the further array region102(e.g., the third array region102C).

With continued reference toFIG.1, the socket regions108of the first microelectronic device structure100may comprise horizontal areas of the first microelectronic device structure100configured and positioned to facilitate electrical connections (e.g., by way of contact structures and routing structures formed within horizontal boundaries thereof) between subsequently formed control logic circuitry and additional subsequently formed structures (e.g., BEOL structures), as described in further detail below. The socket regions108may horizontally neighbor one or more peripheral horizontal boundaries (e.g., in the Y-direction, in the X-direction) of one or more groups of the array regions102. For clarity and ease of understanding of the drawings and related description,FIG.1depicts the first microelectronic device structure100as being formed to include one (1) socket region108horizontally neighboring a shared horizontal boundary of the second array region102B and the fourth array region102D. However, the first microelectronic device structure100may be formed to include one or more of a different quantity and a different horizontal position of socket region(s)108. As a non-limiting example, the socket region108may horizontally neighbor a shared horizontal boundary of a different group of the array regions102(e.g., a shared horizontal boundary of the third array region102C and the fourth array region102D, a shared horizontal boundary of the first array region102A and the third array region102C, a shared horizontal boundary of the first array region102A and the second array region102B). As another non-limiting example, the first microelectronic device structure100may be formed to include multiple (e.g., a plurality of, more than one) socket regions108horizontally neighboring different groups of the array regions102than one another. In some embodiments, multiple socket regions108collectively substantially horizontally surround (e.g., substantially horizontally circumscribe) the array regions102.

FIGS.2A through2Dillustrate simplified, partial longitudinal cross-sectional views of different regions of the first microelectronic device structure100previously described with reference toFIG.1.FIG.2Aillustrates a simplified, partial longitudinal cross-sectional view from the perspective of the Y-direction (so as to depict an XZ-plane) of one of the array regions102(e.g., the first array region102A) of the first microelectronic device structure100shown inFIG.1.FIG.2Billustrates a simplified, partial longitudinal cross-sectional view from the perspective of the Y-direction (so as to depict an XZ-plane) of one of the digit line exit regions104of the first microelectronic device structure100shown inFIG.1.FIG.2Cillustrates a simplified, partial longitudinal cross-sectional view from the perspective of the X-direction (so as to depict a YZ-plane) of one of the word line exit regions106of the first microelectronic device structure100shown inFIG.1.FIG.2Dillustrates a simplified, partial longitudinal cross-sectional view from the perspective of the X-direction (so as to depict a YZ-plane) of one of socket regions108of the first microelectronic device structure100shown inFIG.1.

Referring collectively toFIGS.2A through2D, the first microelectronic device structure100may be formed to include a first base semiconductor structure110, filled trenches112, transistors114(FIGS.2A and2D), a first isolation material116, first contact structures118(FIGS.2A and2D), second contact structures120(FIGS.2A and2D), third contact structures122(FIG.2D), and at least one first routing tier124including first routing structures126. The filled trenches112vertically extend (e.g., in the Z-direction) into the first base semiconductor structure110. The transistors114at least partially vertically overlie the first base semiconductor structure110and the filled trenches112. The first contact structures118and second contact structures120contact the transistors114. The third contact structures122vertically extend through the filled trenches112within the digit line exit regions104(FIG.2B), the word line exit regions106(FIG.2C), and socket regions108(FIG.2D) and contact the first base semiconductor structure110. Some of the first routing structures126contact some of the first contact structures118(FIGS.2A and2D), some other of the first routing structures126contact some of the second contact structures120(FIGS.2A and2D), and yet some other of the first routing structures126contact some of the third contact structures122(FIGS.2B,2C, and2D). The first isolation material116may substantially cover and surround the first base semiconductor structure110, the transistors114, the first contact structures118, the second contact structures120, the third contact structures122, and the first routing structures126.

The first base semiconductor structure110comprises a base material or construction upon which additional features (e.g., materials, structures, devices) of the first microelectronic device structure100are formed. The first base semiconductor structure110may comprise a semiconductor structure (e.g., a semiconductor wafer), or a base semiconductor material on a supporting structure. For example, the first base semiconductor structure110may comprise a conventional silicon substrate (e.g., a conventional silicon wafer), or another bulk substrate comprising a semiconductor material. In some embodiments, the first base semiconductor structure110comprises a silicon wafer. The first base semiconductor structure110may include one or more layers, structures, and/or regions formed therein and/or thereon.

The filled trenches112may comprise trenches (e.g., openings, vias, apertures) within the first base semiconductor structure110that are at least partially (e.g., substantially) filled with the first isolation material116. The filled trenches112may, for example, be employed as shallow trench isolation (STI) structures within the first base semiconductor structure110. The filled trenches112may be formed to vertically extend partially (e.g., less than completely) through the first base semiconductor structure110. Each of the filled trenches112may be formed to exhibit substantially the same dimensions and shape as each other of the filled trenches112, or at least one of the filled trenches112may be formed to exhibit one or more of different dimensions and a different shape than at least one other of the filled trenches112. As a non-limiting example, each of the filled trenches112may be formed to exhibit substantially the same vertical dimension(s) and substantially the same vertical cross-sectional shape(s) as each other of the filled trenches112; or at least one of the filled trenches112may be formed to exhibit one or more of different vertical dimension(s) and different vertical cross-sectional shape(s) than at least one other of the filled trenches112. In some embodiments, the filled trenches112are all formed to vertically extend to and terminate at substantially the same depth within the first base semiconductor structure110. In additional embodiments, at least one of the filled trenches112is formed to vertically extend to and terminate at a relatively deeper depth within the first base semiconductor structure110than at least one other of the filled trenches112. As another non-limiting example, each of the filled trenches112may be formed to exhibit substantially the same horizontal dimension(s) and substantially the same horizontal cross-sectional shape(s) as each other of the filled trenches112; or at least one of the filled trenches112may be formed to exhibit one or more of different horizontal dimension(s) (e.g., relatively larger horizontal dimension(s), relatively smaller horizontal dimension(s)) and different horizontal cross-sectional shape(s) than at least one other of the filled trenches112. In some embodiments, at least one of the filled trenches112is formed to have one or more different horizontal dimensions (e.g., in the X-direction and/or in the Y-direction) than at least one other of the filled trenches112.

Referring collectively toFIGS.2A and2D, the transistors114may individually be formed to include conductively doped regions128, a channel region130, a gate structure132, and a gate dielectric material134. For a transistor114, the conductively doped regions128may be formed within the first base semiconductor structure110(e.g., within an relatively elevated portion of the formed within portions (e.g., relatively elevated portions) of the first base semiconductor structure110horizontally neighboring at least one of the filled trenches112; the channel region130may be within the first base semiconductor structure110and may be horizontally interposed between the conductively doped regions128thereof; the gate structure132may vertically overlie the channel region130; and the gate dielectric material134(e.g., a dielectric oxide) may be vertically interposed (e.g., in the Z-direction) between the gate structure132and the channel region130. The conductively doped regions128of an individual transistor114may include a source region128A and a drain region128B.

Referring collectively toFIGS.2A and2D, for an individual transistor114, the conductively doped regions128thereof may comprise semiconductor material of the first base semiconductor structure110doped with one or more desired conductivity-enhancing dopants. In some embodiments, the conductively doped regions128of the transistor114comprise semiconductor material (e.g., silicon) doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In some of such embodiments, the channel region130of the transistor114comprises the semiconductor material doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some other of such embodiments, the channel region130of the transistor114comprises substantially undoped semiconductor material (e.g., substantially undoped silicon). In additional embodiments, for an individual transistor114, the conductively doped regions128thereof comprise semiconductor material (e.g., silicon) doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some of such additional embodiments, the channel region130of the transistor114comprises the semiconductor material doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In some other of such additional embodiments, the channel region130of the transistor114comprised substantially undoped semiconductor material (e.g., substantially undoped silicon).

Still referring collectively toFIGS.2A and2D, the gate structures132(e.g., gate electrodes) may individually horizontally extend (e.g., in the X-direction) between and be employed by multiple transistors114. The gate structures132may be formed of and include conductive material. The gate structures132may individually be substantially homogeneous, or the gate structures132may individually be heterogeneous. In some embodiments, the gate structures132are each substantially homogeneous. In additional embodiments, the gate structures132are each heterogeneous. Individual gate structures132may, for example, be formed of and include a stack of at least two different conductive materials.

Still referring toFIGS.2A and2D, the first contact structures118may individually be formed to vertically extend between and couple the gate structures132(and, hence, the transistors114) to one or more of the first routing structures126of the first routing tier124. The first contact structures118may individually be formed of and include conductive material. By way of non-limiting example, the first contact structures118may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the first contact structures118are formed of and include W. In additional embodiments, the first contact structures118are formed of and include Cu.

As also shown inFIGS.2A and2D, the second contact structures120may be formed to vertically extend between and couple the conductively doped regions128(e.g., the source region128A, the drain region128B) of the transistors114to some of the first routing structures126of the first routing tier124. The second contact structures120may individually be formed of and include conductive material. By way of non-limiting example, the second contact structures120may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). A material composition of the second contact structures120may be substantially the same as a material composition of the first contact structures118, or the material composition of one or more of the second contact structures120may be different than the material composition of one or more of the first contact structures118. In some embodiments, the second contact structures120are formed of and include W. In additional embodiments, the second contact structures120are formed of and include Cu.

Referring collectively toFIGS.2B through2D, at least some of the third contact structures122may vertically extend (e.g., in the Z-direction) between some other of the first routing structures126and other portions (e.g., relatively vertically recessed portions) of the first base semiconductor structure110within (e.g., inside of) the horizontal boundaries (e.g., in the X-direction and the Y-direction) of some of the filled trenches112, such as some of the filled trenches112within the digit line exit regions104(FIG.2B), the word line exit regions106(FIG.2C), and the socket regions108(FIG.2D) of the first microelectronic device structure100. As shown inFIGS.2B through2D, in some embodiments, at least some of the third contact structures122vertically extend from the first routing structures126, through one or more of the filled trenches112, and to one or more vertically lower surfaces of the first base semiconductor structure110within horizontal boundaries of the one or more of the filled trenches112. As described in further detail below, at least some of the third contact structures122may be employed to facilitate electrical connection between some of the first routing structures126and one or more features (e.g., structures, materials, devices) to be formed at an opposing side (e.g., a back side, a bottom side) of the first base semiconductor structure110following subsequent processing (e.g., subsequent thinning) of the first base semiconductor structure110. The third contact structures122may each individually be formed of and include conductive material. By way of non-limiting example, the third contact structures122be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the third contact structures122are formed of and include W. In additional embodiments, the third contact structures122are formed of and include Cu.

Referring collectively toFIGS.2A through2D, the first routing structures126of the first routing tier124may be formed of and include conductive material. By way of non-limiting example, the first routing structures126may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the first routing structures126are formed of and include W. In additional embodiments, the first routing structures126are formed of and include Cu. At least some of the first routing structures126may be employed as local routing structures of a microelectronic device (e.g., a memory device, such as a DRAM device) of the disclosure.

WhileFIGS.2A through2Ddepict the first microelectronic device structure100as being formed to include a single (e.g., only one) first routing tier124including first routing structures126, the first microelectronic device structure100may be formed to include multiple (e.g., more than one) first routing tiers124each individually including a desired arrangement (e.g., pattern) of first routing structures126. By of non-limiting example, the first microelectronic device structure100may be formed to include two or more (e.g., three or more) of the first routing tiers124, wherein different first routing tiers124are vertically offset from one another and each individually include a desired arrangement of first routing structures126therein. At least some of the first routing structures126within at least one of the first routing tiers124may be coupled to at least some of the first routing structures126within at least one other of the first routing tiers124by way of conductive interconnect structures.

With continued collective reference toFIGS.2Athough2D, the transistors114, the first contact structures118, the second contact structures120, and the first routing structures126may form control logic circuitry of various control logic devices136(FIGS.2A and2D) configured to control various operations of various features (e.g., the memory cells) of a microelectronic device (e.g., a memory device, such as a DRAM device) to be formed through the methods of disclosure. In some embodiments, the control logic devices136comprise CMOS circuitry. As a non-limiting example, the control logic devices136may include one or more (e.g., each) of charge pumps (e.g., VCCPcharge pumps, VNEGWLcharge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuitry (e.g., ring oscillators), Vddregulators, drivers (e.g., main word line drivers, sub word line drivers (SWD)), page buffers, decoders (e.g., local deck decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), repair circuitry (e.g., column repair circuitry, row repair circuitry), I/O devices (e.g., local I/O devices), memory test devices, array multiplexers (MUX), error checking and correction (ECC) devices, self-refresh/wear leveling devices, and other chip/deck control circuitry. Different regions (e.g., the array region102(FIG.2A), the socket region108(FIG.2D)) may have different control logic devices136formed within horizontal boundaries thereof.

Still referring to collectively toFIGS.2A through2D, the first isolation material116may be formed on or over surfaces of the first base semiconductor structure110inside and outside of the horizontal boundaries of the filled trenches112. In addition, the first isolation material116may be formed on or over surfaces of the transistors114, the first contact structures118(FIGS.2A and2D), the second contact structures120(FIGS.2A and2D), the third contact structures122(FIGS.2B through2D), and the first routing structures126. An uppermost vertical boundary (e.g., an uppermost surface) of the first isolation material116may vertically overlie uppermost vertical boundaries (e.g., uppermost surfaces) of the first routing structures126. As described in further detail below, the first isolation material116may be employed to attach (e.g., bond) the first microelectronic device structure100to a second microelectronic device structure (e.g., a second wafer). The first isolation material116may be formed of and include at least one insulative material. By way of non-limiting example, the first isolation material116may be formed of and include one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, and TiOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric carboxynitride material (e.g., SiOxCzNy), and amorphous carbon. In some embodiments, the first isolation material116is formed of and includes SiOx(e.g., SiO2). The first isolation material116may be substantially homogeneous, or the first isolation material116may be heterogeneous. In some embodiments, the first isolation material116is substantially homogeneous. In additional embodiments, the first isolation material116is heterogeneous. The first isolation material116may, for example, be formed of and include a stack of at least two different dielectric materials.

Referring next toFIG.3, illustrated is simplified, partial longitudinal cross-sectional view from the perspective of the Y-direction (so as to depict an XZ-plane) of a second microelectronic device structure138(e.g., a second wafer) may be formed to include a second base semiconductor structure140and a second isolation material142formed on, over, or within the second base semiconductor structure140. The second microelectronic device structure138may be formed separate from the first microelectronic device structure100(FIGS.1and2A through2D). Following separate formation, the second microelectronic device structure138may be attached to the first microelectronic device structure100(FIGS.1and2A through2D), as described in further detail below with reference toFIGS.4A through4D.

The second base semiconductor structure140of the second microelectronic device structure138comprises a base material or construction upon which additional features (e.g., materials, structures, devices) of the formed. In some embodiments, the second base semiconductor structure140comprises a wafer. The second base semiconductor structure140may be formed of and include a semiconductor material (e.g., one or more of a silicon material, such monocrystalline silicon or polycrystalline silicon; silicon-germanium; germanium; gallium arsenide; a gallium nitride; gallium phosphide; indium phosphide; indium gallium nitride; and aluminum gallium nitride). By way of non-limiting example, the second base semiconductor structure140may comprise a semiconductor wafer (e.g., a silicon wafer). The second base semiconductor structure140may include one or more layers, structures, and/or regions formed therein and/or thereon.

As shown inFIG.3, optionally, the second base semiconductor structure140may include at least one detachment region144therein configured to promote or facilitate detachment of a portion140A of the second base semiconductor structure140proximate (e.g., adjacent) the second isolation material142from an additional portion140B of the second base semiconductor structure140relatively more distal from the second isolation material142. By way of non-limiting example, the detachment region144may include one more of dopants (e.g., hydrogen), void spaces, and/or structural features (e.g., defects, damage) promoting or facilitating subsequent detachment of the portion140A from the additional portion140B, as described in further detail below. A vertical depth Di (e.g., in the Z-direction) of the detachment region144within the second base semiconductor structure140may correspond to desired vertical height of the portion140A of the second base semiconductor structure140. The vertical height of the portion140A may be selected at least partially based on desired configuration of additional features (e.g., structures, materials, devices) to be formed using the portion140A of the second base semiconductor structure140following the detachment thereof from the additional portion140B of the second base semiconductor structure140. In some embodiments, the vertical depth Di of the detachment region144(and, hence, the vertical height of the portion140A of the second base semiconductor structure140) is within a range of from about 400 nanometers (nm) to about 800 nm. In additional embodiments, the detachment region144is absent from the second base semiconductor structure140. In some of such embodiments, the additional portion140B of the second base semiconductor structure140may subsequently be removed relative to the portion140A of the second base semiconductor structure140through a different process (e.g., a non-detachment-based process, such as a conventional grinding process).

The second isolation material142of the second microelectronic device structure138may be formed of and include at least one insulative material. A material composition of the second isolation material142of the second microelectronic device structure138may be substantially the same as a material composition of the first isolation material116(FIGS.2A through2D) of the first microelectronic device structure100(FIGS.1and2A through2D); or the material composition of the second isolation material142may be different than the material composition of the first isolation material116(FIGS.2A through2D). In some embodiments, the second isolation material142is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The second isolation material142may be substantially homogeneous, or the second isolation material142may be heterogeneous. In some embodiments, the second isolation material142is substantially homogeneous. In additional embodiments, the second isolation material142is heterogeneous. The second isolation material142may, for example, be formed of and include a stack of at least two different dielectric materials.

Referring next toFIGS.4A through4D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.4A), the digit line exit region104(FIG.4B), the word line exit region106(FIG.4C), and the socket region108(FIG.4D) previously described with reference toFIGS.2A through2Dat a processing stage of the method of forming the microelectronic device following the processing stages previously described with reference toFIGS.1,2A through2D, and3. While the different regions shown inFIGS.4A through4Dwere previously described as different regions of the first microelectronic device structure100, it will be understood that these regions are not limited to the features (e.g., structures, materials, devices) and/or portions of features of the first microelectronic device structure100previously described with reference toFIGS.1and2A through2D. Instead, these regions may evolve to encompass and include additional features (e.g., additional structures, additional materials, additional devices), portions of additional features, and/or modified features provided within horizontal boundaries thereof as a result of additional processing stages of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.1and2A through2D. These regions, as evolved through the method of forming the microelectronic device of the disclosure, become portions of a microelectronic device of the disclosure.

As depicted inFIGS.4A through4D, the second microelectronic device structure138may be vertically inverted (e.g., flipped upside down in the Z-direction) and the second isolation material142thereof may be attached (e.g., bonded, such as through oxide-oxide bonding) to the first isolation material116of the first microelectronic device structure100to form a microelectronic device structure assembly146. Attaching (e.g., bonding) the second isolation material142of the second microelectronic device structure138to the first isolation material116of the first microelectronic device structure100may form a first connected isolation structure148of the microelectronic device structure assembly146. Alternatively, the first microelectronic device structure100may be vertically inverted (e.g., flipped upside down in the Z-direction) and attached to the second microelectronic device structure138to form the microelectronic device structure assembly146.

To form the first connected isolation structure148of the microelectronic device structure assembly146, after physically contacting the first isolation material116of the first microelectronic device structure100with the second isolation material142of the second microelectronic device structure138, the first microelectronic device structure100and the second microelectronic device structure138may be exposed to annealing conditions to form bonds (e.g., oxide-to-oxide bonds) between the first isolation material116and the second isolation material142. By way of non-limiting example, the first isolation material116and the second isolation material142may be exposed to a temperature greater than or equal to about 400° C. (e.g., within a range of from about 400° C. to about 800° C., greater than about 800° C.) to form oxide-to-oxide bonds between the first isolation material116and the second isolation material142. In some embodiments, the first isolation material116and the second isolation material142are exposed to at least one temperature greater than about 800° C. to form oxide-to-oxide bonds between first isolation material116and the second isolation material142and attach the first microelectronic device structure100to the second microelectronic device structure138.

While the first isolation material116and the second isolation material142of the first connected isolation structure148of the microelectronic device structure assembly146are distinguished from one another inFIGS.4A through4Dby way of a dashed line, the first isolation material116and the second isolation material142may be integral and continuous with one another. Put another way, the first connected isolation structure148may be a substantially monolithic structure including the first isolation material116as a first region (e.g., a vertically lower region) thereof, and the second isolation material142as a second region (e.g., a vertically upper region) thereof. For the first connected isolation structure148, the first isolation material116thereof may be attached to the second isolation material142thereof without a bond line.

Still referring toFIGS.4A through4D, attaching the second microelectronic device structure138to the first microelectronic device structure100to form the microelectronic device structure assembly146in the manner described above may facilitate forming individual socket regions108(FIG.4D) to have a relatively reduced horizontal area as compared to conventional microelectronic device configurations. For example, by attaching the second microelectronic device structure138to the first microelectronic device structure100prior to forming various devices (e.g., access devices, storage node device) and associated additional interconnect features (e.g., contact structures, routing structures) of a microelectronic device of the disclosure, various alignment considerations may be alleviated and the horizontal footprint that would otherwise be needed to account for such alignment considerations may be reduced. The horizontal area of an individual socket region108(FIG.4D) may, for example, be from about 40 percent to about 60 percent smaller than the horizontal area of a conventional socket region of a conventional microelectronic device configuration. Such socket region size reduction may facilitate relatively enhanced areal density for sub-20 nanometer (nm) technology nodes.

Referring next toFIGS.5A through5D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.5A), the digit line exit region104(FIG.5B), the word line exit region106(FIG.5C), and the socket region108(FIG.5D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.4A through4D. As depicted inFIGS.5A through5D, the additional portion140B (FIGS.4A through4D) of the second base semiconductor structure140(FIGS.4A through4D) is removed while at least partially maintaining the portion140A (FIGS.4A through4D) of the second base semiconductor structure140(FIGS.4A through4D), and then the at least partially maintained portion140A (FIGS.4A through4D) may be patterned to form a first semiconductor tier150including first semiconductor structures152. The first semiconductor structures152may be employed to subsequently form additional features (e.g., structures; devices, such as transistors), as described in further detail below. In addition, a third isolation material154may be formed horizontally adjacent the first semiconductor structures152of the first semiconductor tier150.

The additional portion140B (FIGS.4A through4D) of the second base semiconductor structure140(FIGS.4A through4D) may be removed using conventional processes (e.g., a detachment process; a wafer thinning process, such as a grinding processes) and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, in some embodiments wherein the second base semiconductor structure140(FIGS.4A through4D) includes the detachment region144(FIGS.4A through4D) including one more of dopants (e.g., hydrogen), void spaces, and/or structural features (e.g., defects, damage) promoting or facilitating subsequent detachment of the portion140A (FIGS.4A through4D) from the additional portion140B (FIGS.4A through4D), the second base semiconductor structure140(FIGS.4A through4D) may be acted upon to effectuate such detachment at or proximate the detachment region144(FIGS.4A through4D). In addition, parts of the portion140A (FIGS.4A through4D) of the second base semiconductor structure140(FIGS.4A through4D) maintained following the removal of the additional portion140B (FIGS.4A through4D) of the second base semiconductor structure140(FIGS.4A through4D) may be further processed (e.g., polished, patterned) to form the first semiconductor structures152of the first semiconductor tier150using conventional processes (e.g., conventional CMP processes, conventional masking processes, conventional etching processes) and conventional processing equipment, which are also not described in detail herein. A vertical height (e.g., in the Z-direction) of the first semiconductor structures152may be less than or equal to the vertical height of the portion140A (FIGS.4A through4D) of the second base semiconductor structure140(FIGS.4A through4D). In some embodiments, the vertical height of the first semiconductor structures152is formed to be less than the vertical height of the portion140A (FIGS.4A through4D) of the second base semiconductor structure140(FIGS.4Athrough4D). For example, the vertical height of the first semiconductor structures152may be formed to be within a range of from about 100 nm to about 300 nm, such as from about 150 nm to about 250 nm, or about 200 nm.

As collectively depicted inFIGS.5A through5D, following the processing of the additional portion140B (FIGS.4A through4D) of the second base semiconductor structure140(FIGS.4A through4D), some of the regions (e.g., the array region102shown inFIG.5A, the socket region108shown inFIG.5D) include the resulting first semiconductor structures152, and some other of the regions (e.g., the digit line exit region104shown inFIG.5B, the word line exit region106shown inFIG.5C) are substantially free of the resulting first semiconductor structures152. For example, the array region102shown inFIG.5Amay include some of the first semiconductor structures152, wherein horizontally neighboring first semiconductor structures152are separated from one another by the third isolation material154. As another example, each of the digit line exit region104shown inFIG.5Band the word line exit region106shown inFIG.5Cmay be substantially free of the first semiconductor structures152. As collectively illustrated inFIGS.5A through5D, in some embodiments, an upper surface of the third isolation material154is formed to be substantially coplanar with upper surfaces of the first semiconductor structures152of the first semiconductor tier150.

The third isolation material154may be formed of and include at least one insulative material. A material composition of the third isolation material154may be substantially the same as a material composition of the first connected isolation structure148, or the material composition of the fourth isolation material170may be different than the material composition of the first connected isolation structure148. In some embodiments, the third isolation material154is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The third isolation material154may be substantially homogeneous, or the third isolation material154may be heterogeneous. In some embodiments, the third isolation material154is substantially homogeneous. In additional embodiments, the third isolation material154is heterogeneous. The third isolation material154may, for example, be formed of and include a stack of at least two different dielectric materials.

Referring next toFIGS.6A through6D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.6A), the digit line exit region104(FIG.6B), the word line exit region106(FIG.6C), and the socket region108(FIG.6D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.5A through5D. As collectively depicted inFIGS.6A through6D, access devices156(FIG.6A) (e.g., access transistors) may be formed within the array region102(FIG.6A). In addition, digit lines158(FIGS.6A and6B) (e.g., data lines, bit lines) may be formed to be coupled to the access devices156(FIG.6A) and to horizontally extend in the Y-direction through the array region102(FIG.6A). At least some of the digit lines158(FIGS.6A and6B) may terminate (e.g., end) within the digit line exit region104(FIG.6B). Furthermore, word lines160(e.g., access lines) may be formed to be coupled to the access devices156(FIG.6A) and to horizontally extend in the X-direction through the array region102(FIG.6A). At least some of the word lines160(FIGS.6A and6C) may terminate within the word line exit region106(FIG.6C).

Referring toFIG.6A, the access devices156formed within the array region102may be employed as components of memory cells (e.g., DRAM cells) to be formed within the array region102. By way of non-limiting example, each access device156may individually be formed to include a channel region comprising a portion of one of the first semiconductor structures152; a source region and a drain region each individually comprising one or more of at least one conductively doped portion of the one first semiconductor structures152and/or at least one conductive structure formed in, on, or over the one of the first semiconductor structures152; and at least one gate structure comprising a portion of at least one of the word lines160. Each access device156may also include a gate dielectric material (e.g., a dielectric oxide material) formed to be interposed between the channel region thereof and the gate structure thereof.

The digit lines158may exhibit horizontally elongate shapes extending in parallel in the Y-direction; and the word lines160may exhibit horizontally elongate shapes extending in parallel in the X-direction orthogonal to the Y-direction. As used herein, the term “parallel” means substantially parallel. The digit lines158and the word lines160may each individually be formed of and include conductive material. By way of non-limiting example, the digit lines158and the word lines160may each individually be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the digit lines158and the word lines160are each individually formed of and include one or more of W, Ru, Mo, and titanium nitride (TiNy). Each of the digit lines158and each of the word lines160may individually be substantially homogeneous, or one or more of the digit lines158and/or one or more of the word lines160may individually be substantially heterogeneous. In some embodiments, each of the digit lines158and each of the word lines160are formed to be substantially homogeneous.

Still referring toFIG.6A, within the array region102, additional features (e.g., structures, materials) are also formed on, over, and/or between the access devices156, the digit lines158, and the word lines160. For example, as shown inFIG.6A, fourth contact structures162(e.g., digit line contact structures, also referred to as so-called “bitcon” structures) may be formed to vertically extend between and couple the access devices156to the digit lines158; fifth contact structures164(e.g., cell contact structures, also referred to as so-called “cellcon” structures) may be formed in contact with the access devices156and may configured and positioned to couple the access devices156to subsequently formed storage node devices (e.g., capacitors); dielectric cap structures166may be formed on or over the digit lines158; and additional dielectric cap structures168may be formed on or over the word lines160. The fourth contact structures162and the fifth contact structures164may individually be formed of and include at least one conductive material. In some embodiments, the fourth contact structures162and the fifth contact structures164are individually formed of and include one or more of at least one metal (e.g., W), at least one alloy, at least one conductive metal silicide (e.g., one or more of titanium silicide (TiSix), cobalt silicide (CoSix), tungsten silicide (WSix), tantalum silicide (TaSix), molybdenum silicide (MoSix), and nickel silicide (NiSix)), and at least one conductive metal nitride (e.g., one or more of titanium nitride (TiNy), tungsten nitride (WNy), tantalum nitride (TaNy), cobalt nitride (CoNy), molybdenum nitride (MoNy), and nickel nitride (NiNy)). In addition, the dielectric cap structures166and the additional dielectric cap structures168may individually be formed of and include at least one insulative material. In some embodiments, the dielectric cap structures166and the additional dielectric cap structures168are individually formed of and include a dielectric nitride material (e.g., SiNy, such as Si3N4).

Referring toFIG.6B, within the digit line exit region104, at least some of the digit lines158may horizontally terminate (e.g., end) in the Y-direction. Each of the digit lines158horizontally extending through the array region102(FIG.6A) and horizontally terminating within the digit line exit region104may be formed to terminate at substantially the same horizontal position in the Y-direction; or at least one of the digit lines158horizontally terminating within the digit line exit region104may be formed to terminate at a different horizontal position in the Y-direction within the digit line exit region104than at least one other of the digit lines158horizontally terminating within the digit line exit region104. In some embodiments, at least some digit lines158horizontally neighboring one another in the X-direction have terminal ends (e.g., terminal surfaces) horizontally offset from one another in the Y-direction. Horizontally offsetting the terminal ends of some of the digit lines158from the terminal ends of some other of the digit lines158within the digit line exit region104may, for example, promote or facilitate desirable contact structure arrangements within the digit line exit region104.

Referring next toFIG.6C, within the word line exit region106, at least some of the word lines160may horizontally terminate (e.g., end) in the X-direction. Each of the word lines160horizontally extending through the array region102(FIG.6A) and horizontally terminating within the word line exit region106may be formed to terminate at substantially the same horizontal position in the X-direction; or at least one of the word lines160horizontally terminating within the word line exit region106may be formed to terminate at a different horizontal position in the X-direction within the word line exit region106than at least one other of the word lines160horizontally terminating within the word line exit region106. In some embodiments, at least some word lines160horizontally neighboring one another in the Y-direction have terminal ends (e.g., terminal surfaces) horizontally offset from one another in the X-direction. Horizontally offsetting the terminal ends of some of the word lines160from the terminal ends of some other of the word lines160within the word line exit region106may, for example, promote or facilitate desirable contact structure arrangements within the word line exit region106.

Referring collectively toFIGS.6A through6D, a fourth isolation material170may be formed on or over portions of at least the access devices156(FIG.6A), the digit lines158(FIGS.6A and6B), the word lines160(FIGS.6A and6C), the fifth contact structures164, and the third isolation material154. The fourth isolation material170may be formed of and include at least one insulative material. A material composition of fourth isolation material170may be substantially the same as a material composition of the third isolation material154, or the material composition of the fourth isolation material170may be different than the material composition of the third isolation material154. In some embodiments, the fourth isolation material170is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The fourth isolation material170may be substantially homogeneous, or the fourth isolation material170may be heterogeneous. In some embodiments, the fourth isolation material170is substantially homogeneous. In additional embodiments, the fourth isolation material170is heterogeneous. The fourth isolation material170may, for example, be formed of and include a stack of at least two different dielectric materials.

Referring next toFIGS.7A through7D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.7A), the digit line exit region104(FIG.7B), the word line exit region106(FIG.7C), and the socket region108(FIG.7D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.6A through6D. As collectively depicted inFIGS.7A through7D, sixth contact structures172may be formed within each of the digit line exit region104(FIG.7B), the word line exit region106(FIG.7C), and the socket region108(FIG.7D). The sixth contact structures172may be formed to vertically extend (e.g., in the Z-direction) to and contact the first routing structures126of the first routing tier124. In addition, as described in further detail below, some of the sixth contact structures172may be formed to be contact to portions of the digit lines158(FIG.7B) within the digit line exit region104(FIG.7B), and some other of the sixth contact structures172may be formed to be contact to portions of the word lines160(FIG.7C) within the word line exit region106(FIG.7C).

Referring toFIG.7B, within the digit line exit region104, a first group172A of the sixth contact structures172may be formed to contact at least some of the digit lines158horizontally extending (e.g., in the Y-direction) into the digit line exit region104. Each sixth contact structure172of the first group172A of sixth contact structures172may be considered to be a digit line contact structure (e.g., a so-called “edge of array” digit line contact structure). As shown inFIG.7B, each sixth contact structure172of the first group172A of sixth contact structures172may be formed to physically contact and vertically extend completely through an individual digit line158. For example, within the digit line exit region104, each sixth contact structure172of the first group172A may be formed to physically contact and vertically extend through each of the fourth isolation material170, one of the digit lines158, the third isolation material154, and the first connected isolation structure148. Outer sidewalls of each sixth contact structure172of the first group172A of the sixth contact structures172may physically contact inner sidewalls of an individual digit line158. In addition, each sixth contact structure172of the first group172A may be formed to vertically terminate on or within one of the first routing structures126located within the digit line exit region104. Accordingly, each sixth contact structure172of the first group172A may be formed to be coupled to one of the digit lines158and to one of the first routing structures126.

Referring next toFIG.7C, within the word line exit region106, a second group172B of the sixth contact structures172may be formed to contact at least some of the word lines160horizontally extending (e.g., in the X-direction) into the word line exit region106. Each sixth contact structure172of the second group172B of sixth contact structures172may be considered to be a word line contact structure (e.g., a so-called “edge of array” word line contact structure). As shown inFIG.7C, each sixth contact structure172of the second group172B of sixth contact structures172may be formed to physically contact and vertically extend completely through an individual word line160. For example, within the word line exit region106, each sixth contact structure172of the second group172B may be formed to physically contact and vertically extend through each of the fourth isolation material170, one of the word lines160, the third isolation material154, and the first connected isolation structure148. Outer sidewalls of each sixth contact structure172of the second group172B of the sixth contact structures172may physically contact inner sidewalls of an individual word line160. In addition, each sixth contact structure172of the second group172B may be formed to vertically terminate on or within one of the first routing structures126located within the word line exit region106. Accordingly, each sixth contact structure172of the second group172B may be formed to be coupled to one of the word lines160and to one of the first routing structures126.

Referring next toFIG.7D, within the socket region108, a third group172C of the sixth contact structures172may be formed to vertically extend to the first routing structures126located within the socket region108. Each sixth contact structure172of the third group172C of sixth contact structures172may be considered to be a deep contact structure (e.g., a deep contact structure to be electrically connected to one or more BEOL structures to subsequently be formed). Within the socket region108, each sixth contact structure172of the third group172C may be formed to physically contact and vertically extend through each of the fourth isolation material170, the third isolation material154, and the first connected isolation structure148; and may vertically terminate on or within one of the first routing structures126located within the socket region108.

Collectively referring again toFIGS.7A through7D, the sixth contact structures172, including the first group172A (FIG.7B), the second group172B (FIG.7C), and the third group172C (FIG.7D) thereof, may be formed of and include conductive material. By way of non-limiting example, the sixth contact structures172may each individually be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the sixth contact structures172are each individually formed of and include W. Each of the sixth contact structures172may be substantially homogeneous, or one or more of the sixth contact structures172may individually be heterogeneous. In some embodiments, each of the sixth contact structures172is substantially homogeneous. In additional embodiments, each of the sixth contact structures172is heterogeneous. Each sixth contact structure172may, for example, be formed of and include a stack of at least two different conductive materials.

Referring next toFIGS.8A through8D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.8A), the digit line exit region104(FIG.8B), the word line exit region106(FIG.8C), and the socket region108(FIG.8D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.7A through7D. As collectively depicted inFIGS.8A through8D, at least one second routing tier174including second routing structures176may be formed over the access devices156(FIG.8A) and the sixth contact structures172(FIGS.8B through8D); storage node devices178(e.g., capacitors) may be formed over and in electrical communication with at least some of the second routing structures176within the array region102(FIG.8A); seventh contact structures180may be formed over and in electrical communication with at least some of the second routing structures176within the socket region108(FIG.8D); and at least one third routing tier182including third routing structures184may be formed over the storage node devices178and the seventh contact structures180.

With continued collective reference toFIGS.8A through8D, the second routing structures176of the second routing tier174may be employed to facilitate electrical communication between additional features (e.g., structures, materials, devices) coupled thereto. The second routing structures176may each individually be formed of and include conductive material. By way of non-limiting example, the second routing structures176may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the second routing structures176are formed of and include W.

Referring toFIG.8A, within the array region102, at least some of the second routing structures176may be formed and configured to couple the access devices156to the storage node devices178(e.g., capacitors) to form memory cells186(e.g., DRAM cells) within the array region102. Each memory cell186may individually include one of the access devices156; one of the storage node devices178; one of the fifth contact structures164interposed between the access device156and the storage node device178; and one of the second routing structures176interposed between the fifth contact structure164and the storage node device178. At least some of the second routing structures176within the array region102may, for example, be configured and employed as redistribution material (RDM) structures (also referred to as “redistribution layer” (RDL) structures) to effectively shift (e.g., stagger, adjust, modify) lateral positions of semiconductor pillars of the access devices156to accommodate a desired arrangement (e.g., a hexagonal close packed arrangement) of the storage node devices178vertically over and in electrical communication with the access devices156.

WhileFIGS.8A through8Dshow the formation of a single (e.g., only one) second routing tier174including second routing structures176, multiple (e.g., more than one) second routing tiers174each individually including a desired arrangement (e.g., pattern) of second routing structures176may be formed. By of non-limiting example, two or more (e.g., three or more) of the second routing tiers174may be formed, wherein different second routing tiers174are vertically offset from one another and each individually include a desired arrangement of second routing structures176therein. At least some of the second routing structures176within at least one of the second routing tiers174may be coupled to at least some of the second routing structures176within at least one other of the second routing tiers174by way of conductive interconnect structures.

Referring to again toFIG.8A, within the array region102, the storage node devices178may individually be formed and configured to store a charge representative of a programmable logic state of the memory cell186including the storage node device178. In some embodiments, the storage node devices178comprise capacitors. During use and operation, a charged capacitor may represent a first logic state, such as a logic 1; and an uncharged capacitor may represent a second logic state, such as a logic 0. Each of the storage node devices178may, for example, be formed to include a first electrode (e.g., a bottom electrode), a second electrode (e.g., a top electrode), and a dielectric material between the first electrode and the second electrode.

Referring to next toFIG.8D, within the socket region108, at least some of the seventh contact structures180may be formed to contact at least some of the sixth contact structures172within the third group172C of the sixth contact structures172. For example, one or more the seventh contact structures180may be formed to vertically extend to and terminate on or within one or more of the sixth contact structures172located within the socket region108. The seventh contact structures180may individually be formed of and include conductive material. By way of non-limiting example, the seventh contact structures180may each individually be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, each of the seventh contact structures180is formed of and includes W. Each of the seventh contact structures180may be substantially homogeneous, or one or more of the seventh contact structures180may individually be heterogeneous. In some embodiments, each of the seventh contact structures180is substantially homogeneous. In additional embodiments, each of the seventh contact structures180is heterogeneous. Each seventh contact structure180may, for example, be formed of and include a stack of at least two different conductive materials.

As shown inFIG.8D, within the socket region108, one or more groups of storage node devices178(e.g., capacitors) may, optionally, also be formed. If formed within the socket region108, the storage node devices178may be coupled to at least some of the third routing structures184positioned within the socket region108. If formed, the storage node devices178may be employed to enhance the performance of a microelectronic device formed through the methods of the disclosure. The storage node devices178may, for example, subsequently (e.g., following completion of additional processing stages of the method of forming the microelectronic device) be coupled to and employed to power additional devices (e.g., control logic devices, access devices) of a microelectronic device of the disclosure. In some embodiments, the storage node devices178are subsequently coupled to and employed to power at least some of the control logic devices136. The storage node devices178formed within socket region108may be coupled to (e.g., by way of one or more of the third routing structures184, one or more of the seventh contact structures180, one or more of the sixth contact structures172, one or more of the first routing structures126, and one or more of the third contact structures122) to BEOL structures to subsequently be formed, as also described in further detail below.

Referring collectively toFIGS.8A through8D, the third routing structures184of the third routing tier182may be employed to facilitate electrical communication between additional features (e.g., structures, materials, devices) coupled thereto. In some embodiments, one or more of the third routing structures184are formed to horizontally extend between and couple at least some of the storage node devices178(and, hence, the memory cells186) (FIG.8A) within the array region102(FIG.8A) to one or more of the seventh contact structures180(FIG.8D) within the socket region108(FIG.8D). The third routing structures184may each be formed of and include conductive material. By way of non-limiting example, the third routing structures184may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, each of the third routing structures184of the third routing tier182is formed of and includes W.

With continued reference toFIGS.8A through8D, a fifth isolation material188may be formed on or over portions of at least the fourth isolation material170, the second routing structures176(FIG.8A), the storage node devices178(FIGS.8A and8D), the seventh contact structures180(FIG.8D), and the third routing structures184. The fifth isolation material188may be formed of and include at least one insulative material. A material composition of the fifth isolation material188may be substantially the same as a material composition of the fourth isolation material170, or the material composition of the fifth isolation material188may be different than the material composition of the fourth isolation material170. In some embodiments, the fifth isolation material188is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The fifth isolation material188may be substantially homogeneous, or the fifth isolation material188may be heterogeneous. In some embodiments, the fifth isolation material188is substantially homogeneous. In additional embodiments, the fifth isolation material188is heterogeneous. The fifth isolation material188may, for example, be formed of and include a stack of at least two different dielectric materials.

Referring next toFIGS.9A through9D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.9A), the digit line exit region104(FIG.9B), the word line exit region106(FIG.9C), and the socket region108(FIG.9D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.8A through8D. As collectively depicted inFIGS.9A through9D, a third microelectronic device structure190(e.g., a third wafer) including a base structure192and a sixth isolation material194may be vertically inverted (e.g., flipped upside down in the Z-direction), and the sixth isolation material194thereof may be attached (e.g., bonded, such as through oxide-oxide bonding) to the fifth isolation material188to form an additional microelectronic device structure assembly196. Attaching (e.g., bonding) the sixth isolation material194to the fifth isolation material188may form a second connected isolation structure198.

The base structure192of the third microelectronic device structure190comprises a base material or construction upon which additional features (e.g., materials, structures, devices) of the formed. In some embodiments, the base structure192comprises a wafer. The base structure192may be formed of and include one or more of semiconductor material (e.g., one or more of a silicon material, such monocrystalline silicon or polycrystalline silicon (also referred to herein as “polysilicon”); silicon-germanium; germanium; gallium arsenide; a gallium nitride; gallium phosphide; indium phosphide; indium gallium nitride; and aluminum gallium nitride), a base semiconductor material on a supporting structure, glass material (e.g., one or more of borosilicate glass (BSP), phosphosilicate glass (PSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), aluminosilicate glass, an alkaline earth boro-aluminosilicate glass, quartz, titania silicate glass, and soda-lime glass), and ceramic material (e.g., one or more of poly-aluminum nitride (p-AlN), silicon on poly-aluminum nitride (SOPAN), aluminum nitride (AlN), aluminum oxide (e.g., sapphire; α-Al2O3), and silicon carbide). By way of non-limiting example, the base structure192may comprise a semiconductor wafer (e.g., a silicon wafer), a glass wafer, or a ceramic wafer. The base structure192may include one or more layers, structures, and/or regions formed therein and/or thereon.

The sixth isolation material194of the third microelectronic device structure190may be formed of and include at least one insulative material. A material composition of the sixth isolation material194may be substantially the same as a material composition of the fifth isolation material188; or the material composition of the sixth isolation material194may be different than the material composition of the fifth isolation material188. In some embodiments, the sixth isolation material194is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The sixth isolation material194may be substantially homogeneous, or the sixth isolation material194may be heterogeneous. In some embodiments, the sixth isolation material1948 is substantially homogeneous. In additional embodiments, the sixth isolation material194is heterogeneous. The sixth isolation material194may, for example, be formed of and include a stack of at least two different dielectric materials.

To form second connected isolation structure198of the additional microelectronic device structure assembly196, after physically contacting the fifth isolation material188with the sixth isolation material194, the fifth isolation material188and the sixth isolation material194may be exposed to annealing conditions to form bonds (e.g., oxide-to-oxide bonds) between the fifth isolation material188and the sixth isolation material194. By way of non-limiting example, the fifth isolation material188and the sixth isolation material194may be exposed to a temperature greater than or equal to about 400° C. (e.g., within a range of from about 400° C. to about 800° C., greater than about 800° C.) to form oxide-to-oxide bonds between the fifth isolation material188and the sixth isolation material194. In some embodiments, the fifth isolation material188and the sixth isolation material194are exposed to at least one temperature greater than about 800° C. to form oxide-to-oxide bonds between the fifth isolation material188and the sixth isolation material194.

While inFIGS.9A through9D, the fifth isolation material188and the sixth isolation material194of the second connected isolation structure198are distinguished from one another by way of a dashed line, the fifth isolation material188and the sixth isolation material194may be integral and continuous with one another. Put another way, the second connected isolation structure198may be a substantially monolithic structure including the fifth isolation material188as a first region (e.g., a vertically lower region) thereof, and the sixth isolation material194as a second region (e.g., a vertically upper region) thereof. For the second connected isolation structure198, the sixth isolation material194thereof may be attached to the fifth isolation material188thereof without a bond line.

Referring next toFIGS.10A through10D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.10A), the digit line exit region104(FIG.10B), the word line exit region106(FIG.10C), and the socket region108(FIG.10D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.9A through9D. As collectively depicted inFIGS.10A through10D, the additional microelectronic device structure assembly196may be vertically inverted (e.g., flipped upside down in the Z-direction), and then an upper portion of the first base semiconductor structure110(FIGS.9A through9D) may be removed to expose (e.g., uncover) the first isolation material116within the filled trenches112(FIGS.9A through9D) and form a second semiconductor tier200including second semiconductor structures202. The second semiconductor structures202may be separated from one another by remaining portions of the first isolation material116.

The upper portion of the first base semiconductor structure110(FIGS.9A through9D) vertically overlying the filled trenches112(FIGS.9A through9D) following the vertical inversion of the additional microelectronic device structure assembly196may be removed using at least one conventional wafer thinning process (e.g., a conventional chemical-mechanical planarization (CMP) process; a conventional etching process, such as a conventional dry etching process, or a conventional wet etching process). The second semiconductor structures202may be formed to exhibit a desired vertical height (e.g., in the Z-direction) through the material removal process. The material removal process may also remove portions (e.g., upper portions following the vertical inversion of the additional microelectronic device structure assembly196) of the first isolation material116. As shown inFIG.10D, within the socket region108, the material removal process may partially expose the third contact structures122. The material removal process may also remove portions (e.g., upper portions following the vertical inversion of the additional microelectronic device structure assembly196) of the third contact structures122.

Referring next toFIGS.11A through11D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.11A), the digit line exit region104(FIG.11B), the word line exit region106(FIG.11C), and the socket region108(FIG.11D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.10A through10D. As collectively depicted inFIGS.11A through11D, at least one fourth routing tier204including fourth routing structures206may be formed over the first isolation material116, the second semiconductor structures202(FIG.11A), the transistors114(and, hence, the control logic devices136), and the third contact structures122(FIGS.11B through11D); and BEOL structures may be formed over the fourth routing tier204. The BEOL structures may, for example, be formed to include at least one fifth routing tier208including fifth routing structures210over the fourth routing tier204; and at least one sixth routing tier212including sixth routing structures214over the fifth routing tier208. One or more of the fourth routing structures206of the fourth routing tier204may be coupled to one or more of the third contact structures122(e.g., within the socket region108(FIG.11D)) by way of one of more eighth contact structures215(FIG.11D). In addition, one or more of the fifth routing structures210of the fifth routing tier208may be coupled to one or more of the third contact structures122(e.g., within the socket region108(FIG.11D)) by way of one or more ninth contact structures216(FIG.11D). Furthermore, one or more of the sixth routing structures214(e.g., one or more conductive pad structures) of the sixth routing tier212may be coupled to one or more of the fifth routing structures210of the fifth routing tier208by way of tenth contact structures218(FIG.11D). In further embodiments, at least some (e.g., all) of the tenth contact structures218(FIG.11D) are omitted (e.g., are not formed), and one or more of the sixth routing structures214of the sixth routing tier212are formed to directly physically contact one or more of the fifth routing structures210of the fifth routing tier208.

The fourth routing structures206and the eighth contact structures215(FIG.11D) may each be formed of and include conductive material. By way of non-limiting example, the fourth routing structures206and the eighth contact structures215(FIG.11D) may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the fourth routing structures206and the eighth contact structures215(FIG.11D) are formed of and include W. At least some of the fourth routing structures206may be employed as local routing structures of a microelectronic device (e.g., a memory device, such as a DRAM device).

WhileFIGS.11A through11Dshow the formation of a single (e.g., only one) fourth routing tier204including fourth routing structures206, multiple (e.g., more than one) fourth routing tiers204each individually including a desired arrangement (e.g., pattern) of fourth routing structures206may be formed. By of non-limiting example, two or more (e.g., three or more) of the fourth routing tiers204may be formed, wherein different fourth routing tiers204are vertically offset from one another and each individually include a desired arrangement of fourth routing structures206therein. At least some of the fourth routing structures206within at least one of the fourth routing tiers204may be coupled to at least some of the fourth routing structures206within at least one other of the fourth routing tiers204by way of conductive interconnect structures.

Still referring collectively toFIGS.11A through11D, the fifth routing structures210, the sixth routing structures214, the ninth contact structures216(FIG.11D), and the tenth contact structures218(FIG.11D) (if any) may each be formed of and include conductive material. By way of non-limiting example, the fifth routing structures210, the sixth routing structures214, the ninth contact structures216(FIG.11D), and the tenth contact structures218(FIG.11D) may individually be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the fifth routing structures210are each formed of and include Cu; the sixth routing structures214are each formed of and include Al; and the ninth contact structures216(FIG.11D) and the tenth contact structures218(FIG.11D) are each formed of and include W.

WhileFIGS.12A through12Dshow the formation of a single (e.g., only one) fifth routing tier208including fifth routing structures210, multiple (e.g., more than one) fifth routing tiers208each individually including a desired arrangement (e.g., pattern) of fifth routing structures210may be formed. In addition, whileFIGS.11A through11Dshow the formation of a single (e.g., only one) sixth routing tier212including sixth routing structures214, multiple (e.g., more than one) sixth routing tiers212each individually including a desired arrangement (e.g., pattern) of sixth routing structures214may be formed. By of non-limiting example, two or more (e.g., three or more) of the fifth routing tier208may be formed, wherein different fifth routing tier208are vertically offset from one another and each individually include a desired arrangement of fifth routing structures210therein. At least some of the fifth routing structures210within at least one of the fifth routing tiers208may be coupled to at least some of the fifth routing structures210within at least one other of the fifth routing tiers208by way of conductive interconnect structures.

Referring toFIG.11D, in some embodiments, at least some of the fifth routing structures210and the sixth routing structures214are formed to be in electrical communication with at least some of the third routing structures184coupled to the memory cells186(FIG.11A) within the array region102(FIG.11A) by way of at least one deep contact assembly extending between the at least some of the fifth routing structures210and at least some of the third routing structures184within the socket region108. As shown inFIG.11D, the deep contact assembly may include some of the contact structures (e.g., at least one of the tenth contact structures218(if any), at least one of the ninth contact structures216, at least one of the third contact structures122, at least one of the sixth contact structures172, and at least one of the seventh contact structures180) located within the socket region108, as well the routing structures within the socket region108coupled to the some of the contact structures.

Still referring to collectively toFIGS.11A through11D, a seventh isolation material220may be formed on or over portions of at least the fourth routing structures206, the fifth routing structures210, the sixth routing structures214, the eighth contact structures215(FIG.11D), the ninth contact structures216(FIG.11D), and the tenth contact structures218(FIG.11D) (if any). The seventh isolation material220may be formed of and include at least one insulative material. A material composition of the seventh isolation material220may be substantially the same as a material composition of the first isolation material116, or the material composition of the seventh isolation material220may be different than the material composition of the first isolation material116. In some embodiments, the seventh isolation material220is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The seventh isolation material220may be substantially homogeneous, or the seventh isolation material220may be heterogeneous. In some embodiments, the seventh isolation material220is substantially homogeneous. In additional embodiments, the seventh isolation material220is heterogeneous. The seventh isolation material220may, for example, be formed of and include a stack of at least two different dielectric materials. In addition, as shown inFIG.11D, one or more openings222may be formed within the seventh isolation material220(e.g., within a portion of the seventh isolation material220within the socket region108(FIG.11D)) to expose (and, hence, facilitate access to) one or more portions of one or more of the sixth routing structures214(e.g., one or more conductive pad structures) of the sixth routing tier212.

As shown inFIGS.11A through11D, the method described above with reference toFIGS.1through11Dmay effectuate the formation of a microelectronic device224(e.g., a memory device, such as a DRAM device) including the features (e.g., structures, materials, devices) previously described herein. In some embodiments, at least some of the fifth routing structures210and the sixth routing structures214are employed as global routing structures for the microelectronic device224. The fifth routing structures210and the sixth routing structures214may, for example, be configured to receive global signals from an external bus, and to relay the global signals to other features (e.g., structures, devices) of the microelectronic device224.

Thus, in accordance with embodiments of the disclosure, a method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure.

Furthermore, in accordance with additional embodiments of the disclosure, a method of forming a microelectronic device comprises forming a first wafer comprising a semiconductor material, control logic devices including comprising portions of the semiconductor material, and oxide dielectric material covering the semiconductor material and the control logic devices. A second wafer comprising additional semiconductor material and additional oxide dielectric material over the additional semiconductor material is formed. The second wafer is attached to the semiconductor wafer to using oxide-oxide bonding between the additional oxide dielectric material and the oxide dielectric material. Access devices are formed using portions of the additional semiconductor material. Word lines and digit lines operatively associated with the access devices are formed. Contact structures are formed to penetrate the word lines and the digit lines, the contact structures formed to be in electrical communication with the control logic devices. Capacitors are formed over and in electrical communication with the access devices to form memory cells. Routing structures are formed over the capacitors, the routing structures formed to be in electrical communication with the memory cells and the control logic devices.

Referring next toFIG.12, depicted is a simplified plan view of the microelectronic device224illustrating an arrangement of different control logic sections (described in further detail below) within individual different regions (e.g., the array regions102, such as the first array region102A, the second array region102B, the third array region102C, and the fourth array region102D; the socket regions108) of the microelectronic device224, as well as routing arrangements to different control logic devices (e.g., corresponding to the control logic devices207(FIG.11A)) within the different control logic sections, in accordance with embodiments of the disclosure. The different control logic devices of the different control logic sections may be positioned vertically above (e.g., in the Z-direction) the memory cells186(FIG.11A) of the microelectronic device224. At least some of the different control logic devices may be coupled to the memory cells186(FIG.11A) in the manner previously described with reference toFIGS.11A through11D. For clarity and ease of understanding the description, not all features (e.g., structures, materials, devices) of the microelectronic device224previously described with reference toFIGS.11A through11Dare illustrated inFIG.12.

As shown inFIG.12, within a horizontal area of each array region102, the microelectronic device224may be formed to include a desired arrangement of sense amplifier (SA) sections226and sub-word line driver (SWD) sections228. The SA sections226may include SA devices coupled to the digit lines158of the microelectronic device224, as described in further detail below. The digit lines158may vertically underlie (e.g., in the Z-direction) the SA devices of the SA sections226within the microelectronic device224. The SWD sections228may include SWD devices coupled to the word lines160of the microelectronic device224, as also described in further detail below. The word lines160may vertically underlie (e.g., in the Z-direction) the SWD devices of the SWD sections228within the microelectronic device224.

The SA sections226within a horizontal area an individual array region102(e.g., the first array region102A, the second array region102B, the third array region102C, or the fourth array region102D) may include a first SA section226A and a second SA section226B. For an individual array region102, the first SA section226A and the second SA section226B may be positioned at or proximate opposite corners (e.g., diagonally opposite corners) of the array region102than one another. For example, as shown inFIG.12, for an individual array region102, the first SA section226A may be positioned at or proximate a first corner234A of the array region102, and the second SA section226B may be positioned at or proximate a second corner234B of the array region102located diagonally opposite (e.g., kitty-corner) the first corner234A.

For each SA section226(e.g., the first SA section226A, the second SA section226B) within an individual array region102, the SA devices of the SA section226may be coupled to a group of the digit lines158horizontally extending (e.g., in the Y-direction) through the array region102by way of digit line routing and contact structures236. The digit line routing and contact structures236may, for example, correspond to some of the routing structures (e.g., some of the first routing structures126(FIGS.11A and11B); some of the fourth routing structures206(FIGS.11A and11B)) and some of the contact structures (e.g., some of the first group172A (FIG.11B) of the sixth contact structures172(FIG.11B); some of the third contact structures122(FIG.11B); some of the eighth contact structures215(FIG.11D)) previously described herein.

The SA devices of the SA sections226of array regions102horizontally neighboring one another in the Y-direction (e.g., the first array region102A and the second array region102B; the third array region102C and the fourth array region102D) may be coupled to different groups of digit lines158than one another. For example, each of the SA sections226(e.g., each of the first SA section226A and the second SA section226B) of the first array region102A may include so-called “even” SA devices coupled to even digit lines158B of the microelectronic device224by way of the digit line routing and contact structures236associated with the SA sections226; and each of the SA sections226(e.g., each of the first SA section226A and the second SA section226B) of the second array region102B may include so-called “odd” SA devices coupled to odd digit lines158A of the microelectronic device224by way of the digit line routing and contact structures236associated with the SA sections226; or vice versa. The even digit lines158B of the microelectronic device224may horizontally alternate with the odd digit lines158A of the microelectronic device224in the X-direction. The SA devices of each of the SA sections226of the first array region102A may not be coupled to any odd digit lines158A; and the SA devices of each of the SA sections226of the second array region102B may not be coupled to any even digit lines158B; or vice versa. Similarly, each of the SA sections226(e.g., each of the first SA section226A and the second SA section226B) of the third array region102C horizontally neighboring the first array region102A in the X-direction may include additional even SA devices coupled to additional even digit lines158B of the microelectronic device224by way of the digit line routing and contact structures236associated with the SA sections226; and each of the SA sections226(e.g., each of the first SA section226A and the second SA section226B) of the fourth array region102D horizontally neighboring the second array region102B in the X-direction may include additional odd SA devices coupled to additional odd digit lines158A of the microelectronic device224by way of the digit line routing and contact structures236associated with the SA sections226; or vice versa.

As shown inFIG.12, the SA devices (e.g., odd SA devices or even SA devices) within an individual SA section226of an individual array region102may be coupled to digit lines (e.g., odd digit lines158A or even digit lines158B) horizontally extending through the array region102, and may also be coupled to additional digit lines (e.g., additional odd digit lines158A or additional even digit lines158B) horizontally extending through another array region102horizontally neighboring the array region102in the Y-direction. For example, some odd SA devices within the first SA section226A of the second array region102B may be coupled to odd digit lines158A horizontally extending through the second array region102B by way of some digit line routing and contact structures236extending to and through the first digit line exit subregion104A horizontally neighboring the second array region102B in the Y-direction; and some additional odd SA devices within the first SA section226A of the second array region102B may be coupled to additional odd digit lines158A horizontally extending through the first array region102A by way of some additional digit line routing and contact structures236extending to and through the first digit line exit subregion104A. As another example, some even SA devices within the second SA section226B of the first array region102A may be coupled to even digit lines158B horizontally extending through the first array region102A by way of some digit line routing and contact structures236extending to and through the second digit line exit subregion104B horizontally neighboring the first array region102A in the Y-direction; and some additional even SA devices within the second SA section226B of the first array region102A may be coupled to additional even digit lines158B horizontally extending through the second array region102B by way of some additional digit line routing and contact structures236extending to and through the second digit line exit subregion104B.

With maintained reference toFIG.12, the SWD sections228within a horizontal area an individual array region102(e.g., the first array region102A, the second array region102B, the third array region102C, or the fourth array region102D) may include a first SWD section228A and a second SWD section228B. For an individual array region102, the first SWD section228A and the second SWD section228B may be positioned at or proximate different corners than the first SA section226A and a second SA section226B. In addition, the corner of the array region102associated with first SWD section228A may oppose (e.g., diagonally oppose) the corner of the array region102associated with second SWD section228B. For example, as shown inFIG.12, for an individual array region102, the first SWD section228A may be positioned at or proximate a third corner234C of the array region102, and the second SWD section228B may be positioned at or proximate a fourth corner234D of the array region102located diagonally opposite (e.g., kitty-corner) the third corner234C.

For each SWD section228(e.g., the first SWD section228A, the second SWD section228B) within an individual array region102, the SWD devices of the SWD section228may be coupled to a group of the word lines160horizontally extending (e.g., in the X-direction) the array region102by way of word line routing and contact structures238. The word line routing and contact structures238may, for example, correspond to some of the routing structures (e.g., some of the first routing structures126(FIGS.11A and11B); some of the fourth routing structures206(FIGS.11A and11B)) and some of the contact structures (e.g., some of the second group172B (FIG.11C) of the sixth contact structures172(FIG.11C); some of the third contact structures122(FIG.11C); some of the eighth contact structures215(FIG.11D)) previously described herein.

The SWD devices of the SWD sections228of array regions102horizontally neighboring one another in the X-direction (e.g., the first array region102A and the third array region102C; the second array region102B and the fourth array region102D) may be coupled to different groups of word lines160than one another. For example, each of the SWD sections228(e.g., each of the first SWD section228A and the second SWD section228B) of the first array region102A may include so-called “even” SWD devices coupled to even word lines160B of the microelectronic device224by way of the word line routing and contact structures238associated with the SWD sections228; and each of the SWD sections228(e.g., each of the first SWD section228A and the second SWD section228B) of the third array region102C may include so-called “odd” SWD devices coupled to odd word lines160A of the microelectronic device224by way of the word line routing and contact structures238associated with the SWD sections228; or vice versa. The even word lines160B of the microelectronic device224may horizontally alternate with the odd word lines160A of the microelectronic device224in the Y-direction. The SWD devices of each of the SWD sections228of the first array region102A may not be coupled to any odd word lines160A; and the SWD devices of each of the SWD sections228of the third array region102C may not be coupled to any even word lines160B; or vice versa. Similarly, each of the SWD sections228(e.g., each of the first SWD section228A and the second SWD section228B) of the second array region102B horizontally neighboring the first array region102A in the Y-direction may include additional even SWD devices coupled to additional even word lines160B of the microelectronic device224by way of the word line routing and contact structures238associated with the SWD sections228; and each of the SWD sections228(e.g., each of the first SWD section228A and the second SWD section228B) of the fourth array region102D horizontally neighboring the third array region102C in the Y-direction may include additional odd SWD devices coupled to additional odd word lines160A of the microelectronic device224by way of the word line routing and contact structures238associated with the SWD sections228; or vice versa.

As shown inFIG.12, the SWD devices (e.g., odd SWD devices or even SWD devices) within an individual SWD section228of an individual array region102may be coupled to word lines (e.g., odd word lines160A or even word lines160B) horizontally extending through the array region102, and may also be coupled to additional word lines (e.g., additional odd word lines160A or additional even word lines160B) horizontally extending through another array region102horizontally neighboring the array region102in the X-direction. For example, some odd SWD devices within the first SWD section228A of the third array region102C may be coupled to odd word lines160A horizontally extending through the third array region102C by way of some word line routing and contact structures238extending to and through the second word line exit subregion106B horizontally neighboring the third array region102C in the X-direction; and some additional odd SWD devices within the first SWD section228A of the third array region102C may be coupled to additional odd word lines160A horizontally extending through the first array region102A by way of some additional word line routing and contact structures238extending to and through the second word line exit subregion106B. As another example, some even SWD devices within the second SWD section228B of the first array region102A may be coupled to even word lines160B horizontally extending through the first array region102A by way of some word line routing and contact structures238extending to and through the first word line exit subregion106A horizontally neighboring the first array region102A in the X-direction; and some additional even SWD devices within the second SWD section228B of the first array region102A may be coupled to additional even word lines160B horizontally extending through the third array region102C by way of some additional word line routing and contact structures238extending to and through the first word line exit subregion106A.

With maintained reference toFIG.12, within a horizontal area of each array region102, the microelectronic device224may include additional control logic sections individually including additional control logic devices (e.g., control logic devices other than SA devices and SWD devices). For example, for each array region102, additional control logic sections240may be positioned horizontally between (e.g., at relatively more horizontally central positions within the array region102) the SA sections226and the SWD sections228. The additional control logic sections240may include, but are not limited to, column decoder device sections including column decoder device, and main word line (MWD) sections including MWD devices.

Still referring toFIG.12, within a horizontal area of each socket region108, the microelectronic device224may include further control logic sections242individually including further control logic devices (e.g., control logic devices in addition to those located within the horizontal areas of the array regions102). For example, for each socket region108, one or more further control logic sections242may be positioned horizontally between deep contact structures assemblies (e.g., vertically extending from one or more of the fifth routing structures210(FIG.11D) to one or more of the third routing structures184(FIG.11D)) within the socket region108and the array regions102horizontally neighboring the socket region108. At least some of the further control logic devices within the further control logic sections242may have different configurations and different operational functions than the control logic devices located within the horizontal areas of the array regions102. By way of non-limiting example, the further control logic sections242may include bank logic sections including bank logic devices.

Thus, in accordance with embodiments of the disclosure, a microelectronic device comprises array regions, digit line exit regions, and word line exit regions. The array regions individually comprise memory cells, digit lines, word lines, and control logic devices. The memory cells comprise capacitors, and access devices vertically overlying and in electrical communication with the capacitors. The digit lines are operably associated with the memory cells and horizontally extend in a first direction. The word lines are operably associated with the memory cells and horizontally extend in a second direction orthogonal to the first direction. The control logic devices vertically overlie and are in electrical communication with the memory cells. The control logic devices comprise transistors including gate electrodes vertically underlying channels. The digit line exit regions horizontally alternate with rows of the array regions in the first direction. The digit line exit regions individually comprise portions of the digit lines horizontally extending beyond boundaries of the rows of the array regions horizontally adjacent thereto, digit line contact structures physically contacting and vertically extending completely through at least some of the portions of the digit lines, and routing structures coupled to the digit line contact structures. The word line exit regions horizontally alternate with columns of the array regions in the second direction. The word line exit regions individually comprise portions of the word lines horizontally extending beyond boundaries of the columns of the array regions horizontally adjacent thereto, word line contact structures physically contacting and vertically extending completely through at least some of the portions of the word lines, and additional routing structures coupled to the word line contact structures.

Microelectronic devices (e.g., the microelectronic device224(FIGS.11A through11D)) in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG.13is a block diagram illustrating an electronic system300according to embodiments of disclosure. The electronic system300may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPAD® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system300includes at least one memory device302. The memory device302may comprise, for example, a microelectronic device (e.g., the microelectronic device224(FIGS.11A through11D)) previously described herein. The electronic system300may further include at least one electronic signal processor device304(often referred to as a “microprocessor”). The electronic signal processor device304may, optionally, comprise a microelectronic device (e.g., the microelectronic device224(FIGS.11A through11D)) previously described herein. While the memory device302and the electronic signal processor device304are depicted as two (2) separate devices inFIG.13, in additional embodiments, a single (e.g., only one) memory/processor device having the functionalities of the memory device302and the electronic signal processor device304is included in the electronic system300. In such embodiments, the memory/processor device may include a microelectronic device (e.g., the microelectronic device224(FIGS.11A through11D)) previously described herein. The electronic system300may further include one or more input devices306for inputting information into the electronic system300by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system300may further include one or more output devices308for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device306and the output device308comprise a single touchscreen device that can be used both to input information to the electronic system300and to output visual information to a user. The input device306and the output device308may communicate electrically with one or more of the memory device302and the electronic signal processor device304.

Thus, in accordance with embodiments of the disclosure, an electronic system comprises an input device, an output device, a processor device operably connected to the input device and the output device, and a memory device operably connected to the processor device. The memory device comprises memory array regions, a digit line contact region horizontally interposed between two of the memory array regions horizontally neighboring one another in a first direction, and a word line contact region horizontally interposed between two other of the memory array regions horizontally neighboring one another in a second direction perpendicular to the first direction. The memory array regions each comprise dynamic random access memory (DRAM) cells, digit lines coupled to the DRAM cells, word lines coupled to the DRAM cells, and control logic circuitry overlying and in electrical communication with the DRAM cells. The control logic circuitry comprises transistors including gate structures vertically underlying channel structures. The digit line contact region comprises end portions of some of the digit lines extending past horizontal boundaries of the two of the memory array regions, digit line contacts coupled to and extending completely through the end portions of the some of the digit lines, and routing structures coupled to the digit line contacts. The word line contact region comprises end portions of some of the word lines extending past horizontal boundaries of the two other of the memory array regions, word line contacts coupled to and extending completely through the end portions of the some of the word lines, and additional routing structures coupled to the word line contacts.

The structures, devices, and methods of the disclosure advantageously facilitate one or more of improved microelectronic device performance, reduced costs (e.g., manufacturing costs, material costs), increased miniaturization of components, and greater packaging density as compared to conventional structures, conventional devices, and conventional methods. The structures, devices, and methods of the disclosure may also improve scalability, efficiency, and simplicity as compared to conventional structures, conventional devices, and conventional methods.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalent. For example, elements and features disclosed in relation to one embodiment may be combined with elements and features disclosed in relation to other embodiments of the disclosure.