Circuit simulation device, circuit simulation method, and circuit simulation program

A circuit simulation device includes a measurement unit, a calculation unit, and a processing unit. The measurement unit measures first spaces between adjacent contacts of a plurality of first contacts provided on a source diffusion layer in a line in a direction along which a gate electrode of a transistor extends and also a space between adjacent contacts of a plurality of second contacts provided on a drain diffusion layer in a line in the direction, based on layout design data, and second spaces between the first contacts and the gate electrode and spaces between the second contacts and the gate electrode. The calculation unit calculates a fringe capacitance between the gate electrode, the source diffusion layer, and the drain diffusion layer of the transistor, based on the first and second spaces. The processing unit executes layout simulation based on the fringe capacitance of the transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2015-005958 filed on Jan. 15, 2015 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

The present disclosure relates to a circuit simulation device, a circuit simulation method, and a circuit simulation program, and, more particularly, to a circuit simulation device, a circuit simulation method, and a circuit simulation program, for a semiconductor device including transistors.

BACKGROUND

Circuit simulation for semiconductor devices has increasingly gained importance in recent years.

In this respect, in the semiconductor devices in the related art, the gate capacitance and the wiring capacitance of a MOS-FET transistor have great effect, while the capacitance near the MOS-FET transistor has only negligible effect.

As the miniaturization advances, it causes a problem that measured values of the circuit simulation and the silicon device do not match each other. For example, a simulation error at a frequency more than 10% occurs in a ring oscillator of a digital circuit with 40 nm technology.

The major cause thereof is an error of the simulation accuracy of the capacitance near the MOS-FET transistor.

The characteristics of the capacitance near the MOS-FET transistor are relatively large, and the effect on the circuit frequency becomes large. Particularly, the significant characteristics in circuit design are a gate fringe capacitance, a gate overlap capacitance, and a gate contact plug capacitance, included in the capacitance near the MOS-FET transistor.

At this point, Japanese Unexamined Patent Publication No. 2011-129615 discloses a technique for extracting the gate overlap capacitance as a capacitance of an overlapped part of the gate, the source, and the drain.

A fixed value is generally used for the gate fringe capacitance as one capacitance near the MOS-FET transistor. It does not guarantee circuit simulation with high accuracy.

SUMMARY

The present disclosure has been made to solve the above problem. It is accordingly an object thereof to provide a circuit simulation device, a circuit simulation method, and a circuit simulation program, capable of performing circuit simulation with high accuracy.

Other objects and new features thereof will be apparent from the following description made in connection with the accompanying drawings.

According to an embodiment, a circuit simulation device includes a measurement unit, a calculation unit, and a processing unit. The measurement unit measures, as first spaces, a space between adjacent contacts of a plurality of first contacts provided on a source diffusion layer in a line in a direction along which a gate electrode of a transistor extends and also a space between adjacent contacts of a plurality of second contacts provided on a drain diffusion layer in a line in the direction, based on layout design data. The measurement unit measures, as second spaces, spaces between the first contacts and the gate electrode and spaces between the second contacts and the gate electrode. The calculation unit calculates a fringe capacitance between the gate electrode, the source diffusion layer, and the drain diffusion layer of the transistor, based on the first and second spaces measured by the measurement unit. The processing unit executes layout simulation based on the fringe capacitance of the transistor which is calculated by the calculation unit.

According to an embodiment, a circuit simulation device is possible to execute circuit simulation with high accuracy.

DETAILED DESCRIPTION

Descriptions will now specifically be made to an embodiment with reference to the accompanying drawings. The same and corresponding elements are identified with the same reference numerals, and thus will not repeatedly be described.

Accordingly, the present disclosure has been made specifically based on the embodiment. The present disclosure is not limited to the embodiment, and various changes may possibly be made thereto without departing from the scope thereof.

FIG. 1is a diagram for explaining a circuit simulation device1based on the embodiment.

As illustrated inFIG. 1, the circuit simulation device1is a SPICE (Simulation Program with Integrated Circuit Emphasis) simulation device, and includes a circuit verification unit10which executes simulation at the level of circuit based on the inputs of circuit design data and a simulation model file SM. Obtained are various parameters PD of circuit constituent elements (devices) for use in layout design as simulation results of the circuit verification unit10.

The circuit simulation device1includes a layout design unit12, an LPE (Layout Parasitic Extraction) unit14, and a layout verification unit20.

The layout design unit12generates layout design data LD in accordance with the corresponding parameter PD.

The LPE unit14includes a layout dimension measurement unit16and a parasitic RC characteristic calculation unit18.

The layout dimension measurement unit16measures (calculates) various layout dimensions in accordance with the layout design data LD.

The parasitic RC characteristic calculation unit18calculates the parasitic resistance (R) and the parasitic capacitance (C) of the MOS-FET transistor (hereinafter simply referred to as a transistor), in accordance with the measured layout dimensions. The unit18outputs a net list NR with the parasitic RC in consideration of the parasitic resistance and the parasitic capacitance.

The layout verification unit20outputs a simulation result SD, based on the net list NR with the parasitic RC and the simulation model file SM.

FIG. 2is a diagram for explaining an example of a ring oscillator circuit based on the embodiment.

As illustrated inFIG. 2, a plurality of inverters IV are coupled in series, and are configured to be coupled in a ring-like form. The inverter IV includes a P-channel MOS transistor and an N-channel MOS transistor.

The circuit verification unit10executes circuit simulation based on a circuit diagram of the ring oscillator circuit as an example of the circuit design data and the simulation model file. By this circuit simulation, verification is made as to whether the output of the designed ring oscillator circuit has desired characteristics (for example, frequency characteristics). When the desired characteristics are not output, various parameters PD are adjusted again to output the desired characteristics.

The layout design unit12designs the layout design data LD in accordance with the parameters PD obtained as the verification result of the ring oscillator circuit, with the desired characteristics by the circuit simulation of the circuit verification unit10. Specifically, it designs a mask layout pattern for forming the ring oscillator circuit.

FIG. 3is a diagram for explaining a layout configuration of the inverter IV based on the embodiment.

As illustrated inFIG. 3, the layout configuration is a part of the layout design data LD.

The inverter IV has a P-channel MOS transistor and an N-channel MOS transistor. The source diffusion layer of the P-channel MOS transistor is coupled to a source line VDD, through contact plugs CPs arranged at spaces CTS of contact plugs. The drain diffusion layer is coupled to a signal line OUT for outputting an output signal through the contact plugs CPs arranged at the spaces CTS of contact plugs.

The gate is coupled to a signal line IN for inputting an input signal.

Similarly, the source diffusion layer of the N-channel MOS transistor is coupled to a grounding line VSS through contact plugs CP arranged at the spaces CTS of contact plugs. The drain diffusion layer is coupled to a signal line OUT for outputting an output signal through the contact plugs CP arranged at the spaces CTS of contact plugs.

The layout design unit12designs a net list for use in simulation, as layout design data LD.

FIG. 4is a diagram for explaining an example of a net list based on the embodiment.

FIG. 4illustrates examples of a gate length L and a gate width W of a metal wiring layer (M1) as one layer for forming the gate of the N-channel MOS transistor of the inverter IV with the layout configuration ofFIG. 3. Any other layout configurations are explained similarly in the form of a net list.

The LPE unit14calculates the parasitic RC characteristics based on the layout design data LD designed by the layout design unit12.

FIG. 5is a diagram for explaining the parasitic resistance (R) and the parasitic capacitance (C) of a transistor.

FIG. 5illustrates a state in which various parasitic resistance (R) and the parasitic capacitance (C) having an effect on the circuit simulation are added to one transistor.

The layout dimension measurement unit16of the LPE unit14measures various layout dimensions necessary for calculating the parasitic RC characteristics in accordance with the layout design data LD.

The parasitic RC characteristic calculation unit18calculates each of the parasitic resistance (R) and the parasitic capacitance (C) of the transistor in accordance with the measured layout dimensions.

In this embodiment, the fringe capacitance will mainly be described as a parasitic capacitance. It calculates the overlap capacitance and the contact plug capacitance in addition to the fringe capacitance, and obtains the parasitic capacitance.

FIG. 6is a diagram for explaining an example of a net list NR with the parasitic RC.

FIG. 6explains information regarding the parasitic RC characteristic of the parasitic resistance (R) and the parasitic capacitance (C) of an N-channel MOS transistor of an inverter IV, in addition to the net list ofFIG. 4.

There are explained also information about the layout dimensions measured by the layout dimension measurement unit16. For example, a length SA of the source diffusion layer and a length SB of the drain diffusion layer of the transistor are explained.

The layout verification unit20executes layout simulation based on the net list NR with the parasitic RC and the simulation model file SM. By the layout simulation, verification is made as to whether the output of the designed ring oscillator circuit has desired characteristics (for example, frequency characteristic). When the desired characteristics are not output, the layout design data is adjusted again to output the desired characteristics.

FIG. 7is a diagram for explaining the fringe capacitance of the transistor based on the embodiment.

FIG. 7illustrates a cross sectional configuration of the transistor.

Specifically, the transistor includes a drain diffusion layer32, a source diffusion layer36, a gate34, and a contact plug30.

Illustrated are a gate overlap capacitance Cov and a contact plug capacitance Cct. The gate overlap capacitance is a capacitance of an overlapped part of the gate34, the source diffusion layer36, and the drain diffusion layer32. The contact plug capacitance Cct intervenes between the gate34and the contact plug30.

Illustrated is also a fringe capacitance Cf between the gate34, the source diffusion layer36, and the drain diffusion layer32.

Conventionally, a fixed value is set at the fringe capacitance Cf between the gate34, the source diffusion layer36, and the drain diffusion layer32, regardless of the arrangement of the contact plug coupled to the source diffusion layer36and the drain diffusion layer32.

In fact, if the contact plug30is arranged, a line of electric force for the source diffusion layer36and the drain diffusion layer32is partially shielded, and there occurs a physical phenomenon in which the fringe capacitance Cf decreases.

In this embodiment, descriptions will be made thereto, as a fringe capacitance component Cf1(a first capacitance characteristic parameter) fixed regardless of the arrangement of the contact plug30and also fringe capacitance components Cf2and Cf3(second capacitance characteristic parameters) with characteristics varying depending on the arrangement of the contact plug.

If the contact plug30is arranged, the fringe capacitance component Cf2varies in accordance with the arrangement, based on a physical principle that the line of electric force is not physically coupled to the source diffusion layer36and the drain diffusion layer32.

If the contact plug30is arranged, the fringe capacitance component Cf3varies in accordance with the arrangement, based on a physical principle that the line of electric force is not physically coupled onto the diffusion layer from the contact plug30to the gate direction backward part.

As the miniaturization advances, the dimension between the gate and the contact plug decreases. Thus, the percentages of the fringe capacitance components Cf2and Cf3to vary are relatively greater than the fringe capacitance component Cf1.

Thus, there is a considerable divergence between the fringe capacitance for use in the simulation in the related art and the fringe capacitance of the measured value.

The line of electric force is shielded in accordance with the arrangement of the contact plug, and there occurs a physical phenomenon in which the fringe capacitance coupled to the source and drain diffusion layers decreases. Therefore, it is necessary to obtain the fringe capacitance Cfdel (Cf2+Cf3) which varies based on dimensions dc and dpc in accordance with the arrangement of the contact plug.

In this case, the dimension dc is a dimension (a first space) between adjacent contact plugs. If a contact plug is provided at the end, the dimension is between the end of the diffusion layer and this contact plug. The dimension dpc is a dimension (a second space) between the gate and the contact plug.

FIG. 8is a flow diagram for explaining a process of the LPE unit14.

As illustrated inFIG. 8, a process for measuring the dimensions dc and dpc based on the layout design data is executed (Step S2).

The fringe capacitance Cfdel is calculated based on the measured dimensions dc and dpc (Step S4).

There is executed a process for adding the fixed fringe capacitance Cf1and the fringe capacitance Cfdel to vary into the net list with the parasitic RC (Step S6).

Then, the process ends (END).

FIG. 9is a diagram for explaining that the layout dimension measurement unit16measures the dimensions dc and dpc in accordance with the arrangement of the contact plug based on the layout design data.

As illustrated inFIG. 9, the source diffusion layer has two contact plugs CP1and CP2arranged thereon in a line in a direction along which the gate electrode extends. The drain diffusion layer includes two contact plugs CP3and CP4arranged in a line in a direction along which the gate electrode extends.

The dimension dpc between a contact plug CP1and the gate is measured (calculated) as dpc1.

The dimension dc between the contact plug CP1and the end of the diffusion layer is measured (calculated) as dc1.

The dimension dpc between a contact plug CP2and the gate is measured (calculated) as dpc2.

The dimension dc between the contact plugs CP1and CP2is measured (calculated) as dc2.

The dimension dc between the contact plug CP2and the end of the diffusion layer is measured (calculated) as dc3.

The dimension dpc between a contact plug CP3and the gate is measured (calculated) as dpc3.

The dimension dc between the contact plug CP3and the end of the diffusion layer is measured (calculated) as dc3.

The dimension dpc between a contact plug CP4and the gate is measured (calculated) as dpc4.

The dimension dc between the contact plugs CP3and CP4is measured (calculated) as dc4.

The dimension dc between the contact plug4and the end of the diffusion layer is measured (calculated) as dc5.

FIG. 10is a table for calculating the fringe capacitance Cfdel based on the embodiment.

FIG. 10illustrates characteristic lines of the fringe capacitance Cfdel which oaring in accordance with the dimensions dc and dpc. This table explains the characteristic lines which can be obtained through some experiment based on the dimensions measured in advance.

This table may be kept by the LPE unit14, or may be acquired from a non-illustrative memory unit.

The parasitic RC characteristic calculation unit18calculates the fringe capacitance using the corresponding table based on the dimension measured by the layout dimension measurement unit16.

Provided are the characteristic lines of the fringe capacitance corresponding respectively to the dimensions dc1, dc2, dc3(dc>dc2>dc3), by way of example. In this case, the characteristic lines of a cfdel function involving the dimensions dpc and dc as parameters are illustrated.

This fringe capacitance is a fringe capacitance per unit length.

Thus, the fringe capacitance Cfdel on the side of the source can be calculated by “cfdel (dpc1, dc1)*w1+(cfdel (dpc2, dc2)*w2/2+cfel (dpc2, dc2)*w2/2+cfel (dpc2, dc3)*w3”.

Similarly, the fringe capacitance Cfdel on the side of the drain can be calculated by “cfdel (dpc3, dc3)*w4+cfdel (dpc3, dc4)*w5/2+cfdel (dpc4, dc4)*w5/2+cfdel (dpc4, dc5)*w6”.

It is possible to calculate the fringe capacitance Cf based on the corresponding fringe capacitance Cfdel and the fixed fringe capacitance Cf1.

This information is added to the net list with the parasitic RC, and the layout verification unit20executes the layout simulation, thereby enabling to perform simulation with high accuracy.

As a program according to this embodiment, the process explained inFIG. 8may be provided in the form of the application which can be executed by personal computers. At this time, the program according to this embodiment may be embedded as a part of functions of various applications executed on the personal computers.