Semiconductor device and method for fabricating the same

A semiconductor device includes a substrate including an active region and a dummy active region that are spaced apart by an isolation layer, a buried word line extending from the active region to the dummy active region, and a contact plug coupled to an edge portion of the buried word line, wherein an upper surface of the active region is positioned at a higher level than an upper surface of the buried word line, and an upper surface of the dummy active region is positioned at a lower level than the upper surface of the buried word line.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean Patent Application No. 10-2020-0039204, filed on Mar. 31, 2020, which is incorporated herein by reference in its entirety.

BACKGROUND

Various embodiments of the present invention relate to a semiconductor device and, more particularly, to a semiconductor device including a buried word line, and a method for fabricating the semiconductor device.

2. Description of the Related Art

Generally, the use of a buried word line for improving the characteristics of a transistor in a semiconductor device is well known. However, significant research and product development efforts are focused in developing new improved structures that exhibit improved performance characteristics.

SUMMARY

Embodiments of the present invention are directed to a semiconductor device including a buried word line which exhibits significantly improved reliability, and a method for fabricating the same.

In accordance with an embodiment of the present invention, a semiconductor device includes: a substrate including an active region and a dummy active region that are spaced apart by an isolation layer; a buried word line extending from the active region to the dummy active region; and a contact plug coupled to an edge portion of the buried word line, wherein an upper surface of the active region is positioned at a higher level than an upper surface of the buried word line, and an upper surface of the dummy active region is positioned at a lower level than the upper surface of the buried word line.

In accordance with another embodiment of the present invention, a semiconductor device includes: a substrate including a plurality of active regions and a plurality of dummy active regions that are spaced apart by an isolation layer; a plurality of buried word lines that are buried in the substrate and extend from the active regions to the dummy active regions; a capping layer that covers an edge portion of each of the buried word lines; and a contact plug coupled to the edge portion of each of the buried word lines, wherein the edge portion of each of the buried word lines includes a buried portion buried in the dummy active regions; and a protruding portion formed over the buried portion and having a higher level than an upper surface of a dummy active region.

In accordance with yet another embodiment of the present invention, a method for fabricating a semiconductor device includes: forming an active region and a dummy active region in the substrate; forming a buried word line that is buried in the substrate and extends from the active region to the dummy active region; recessing the dummy active region lower than an upper surface of an edge portion of the buried word line; forming a capping layer over the recessed dummy active region; and forming a contact plug that penetrates the capping layer and is coupled to the edge portion of the buried word line.

In accordance with another embodiment of the present invention, a semiconductor device includes: an active region and a dummy active region separated by an isolation layer, the dummy active region having an upper surface that is positioned lower than an upper surface of the active region; and a buried word line extending from the active region to the dummy active region, wherein the buried word line is fully buried within the active region and only partially buried in the dummy active region.

These and other features and advantages of the present invention will be better understood from the following detailed description of specific embodiments of the invention in conjunction with the following drawings.

DETAILED DESCRIPTION

Various embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. Various embodiments of the present invention will be described in greater detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the described embodiments should not be construed as being limited to the particular configurations and shapes illustrated herein but may include deviations in configurations and shapes which do not depart from the spirit and scope of the present invention as defined in the appended claims.

It will be further understood that when an element is referred to as being “connected to”, or “coupled to” another element, it may be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. Furthermore, the connection/coupling may not be limited to a physical connection but may also include a non-physical connection, e.g., a wireless connection.

In addition, it will also be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or one or more intervening elements may also be present.

When a first element is referred to as being “over” a second element, it not only refers to a case where the first element is formed directly on the second element but also a case where a third element exists between the first element and the second element.

It should be understood that the drawings are simplified schematic illustrations of the described devices and may not include well known details for avoiding obscuring the features of the invention.

It should also be noted that features present in one embodiment may be used with one or more features of another embodiment without departing from the scope of the invention.

FIG. 1is a plan view illustrating a semiconductor device100in accordance with an embodiment of the present invention.FIG. 2Ais an enlarged view illustrating a portion100A ofFIG. 1.FIG. 2Bpresents cross-sectional views taken along a line A-A′ and a line B-B′ shown inFIG. 2A.

Referring toFIGS. 1, 2A, and 2B, the semiconductor device100may include a substrate101provided with a plurality of active regions103and a plurality of dummy active regions103D that are spaced apart from each other by an isolation layer102. The semiconductor100device may further include a buried word line104that is buried in the substrate101and extends from the active regions103to the dummy active regions103D, and a contact plug110that is coupled to an edge portion104D of the buried word line104. The buried word line104is fully buried within the active region103and only partially buried in the dummy active region103D.

The active regions103may all have the same shape. From the perspective of a top view, the individual active regions103may have an island-shape. The individual active regions103may extend in the A-A′ direction. The individual active regions103may have a long axis and a short axis, and the length of the long axis may be greater than the length of the short axis. The dummy active regions103D may have the same length or different lengths. The individual dummy active regions103D may extend along the B-B′ direction. The B-B′ direction may be the same as the A-A′ direction. The individual dummy active regions103may have a long axis and a short axis, and the length of the long axis may be greater than the length of the short axis. The individual dummy active regions103D may be greater than the individual active regions103. For example, the individual dummy active regions103D and the individual active regions103may extend with the same directionality, but the individual dummy active regions103D may extend longer than the individual active regions103. As described above, the dummy active regions103D may have a line shape that is elongated along the B-B′ direction. The active regions103may also have a line shape that is elongated along the A-A′ direction. The dummy active regions103D may have a line shape that is significantly longer than the line shape of the active regions103. The line shape of the active regions may also be referred to hereinafter as a short island shape. The individual active regions103may have a size that is sufficiently large so that two buried word lines104are placed therein, and the individual dummy active regions103D may have a size that is sufficiently large so that at least three or more buried word lines104are placed therein. In some embodiments of the present invention, two word lines may be disposed in each dummy active region103D, but in this case, too, the individual dummy active regions103D may be greater than the individual active regions103. The individual active regions103may have a first length D1, and the individual dummy active regions103D may have a second length D2. The second length D2may be greater than the first length D1.

The upper surface T1of an active region103may be positioned at a higher level than the upper surface T2of a dummy active region103D. The upper surface T1of the active region103may be positioned at a higher level than the upper surface L1of the buried word line104. The upper surface T2of the dummy active region103D may be positioned at a lower level than the upper surface L2of the edge portion104D of the buried word line104. The upper surface L2of the edge portion104D of the buried word line104may be positioned at a lower level than the upper surface T1of the active region103.

The edge portion104D of the buried word line104may include a buried portion BP buried in the dummy active region103D, and a protruding portion PP formed over the buried portion BP. The upper surface L2of the edge portion104D of the buried word line104may be provided by the upper surface of the protruding portion PP. The upper surface L2of the protruding portion PP may be positioned at a higher level than the upper surface T2of the dummy active region103D. The upper surface L2of the protruding portion PP may be positioned at a lower level than the upper surface T1of the active region103. The upper surface of the buried portion BP and the upper surface T2of the dummy active region103D may be positioned at the same level. The height of the protruding portion PP may be greater than the height of the buried portion BP. The protruding portion PP may include sidewalls and the upper surface L2.

The sidewalls and the upper surface L2of the protruding portion PP may be covered by a capping layer107. The bottom surface and the sidewalls of the buried portion BP may be covered by a gate dielectric layer106. The gate dielectric layer106may extend to cover the sidewalls of the protruding portion PP. The capping layer107may cover sidewalls of the protruding portion PP over the gate dielectric layer106. The capping layer107may extend to cover the upper surface of the isolation layer102. The capping layer107may cover the upper portion of the buried word line104, but may be buried in the substrate101and extend from the active regions103to the dummy active regions103D.

An inter-layer dielectric layer109may be formed over the capping layer107. The contact plug110may penetrate the inter-layer dielectric layer109and the capping layer107to be coupled to the edge portion104D of the buried word line104. The contact plug110may be coupled to the protruding portion PP of the edge portion104D of the buried word line104. A metal wire111may be formed over the contact plug110. The metal wire111may be formed to be in direct contact with the contact plug110.

Neighboring contact plugs110may be disposed on the same axis or different axes. For example, referring back toFIG. 1, the contact plugs110may be disposed in a zigzag arrangement.

According to the above-described embodiment of the present invention, bending of the word line104may be suppressed by forming the dummy active regions103D longer than the active regions103.

Since the upper surface T2of the dummy active region103D is lower than the upper surface L2of the edge portion104D of the buried word line104, the physical distance between the contact plug110and the dummy active region103D may increase. This may prevent a short circuit between the contact plug110and the dummy active region103D. Since the capping layer107between the edge portions104D of the buried word lines104is gap-filled, a short circuit between the contact plug110and the dummy active region103D may be further prevented. Since the capping layer107is gap-filled between the edge portions104D of the neighboring buried word lines104, widening of the bottom portion of the contact plug110may also be suppressed.

Referring back toFIG. 2B, the buried word line104may include a metal-based material such as a metal nitride, metal, a doped semiconductor material such as, for example, doped polysilicon or a combination thereof. Examples of suitable metals may include tungsten, copper, aluminum, titanium, tantalum and the like. Examples of suitable metal nitrides may include titanium nitride, tungsten nitride, tantalum nitride and the like. For example, the buried word line104and the edge portion104D of the buried word line104may all include a metal-based material. Herein, the edge portion104D of the buried word line may have a lower surface than the buried word line104.

FIG. 3is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. The semiconductor device ofFIG. 3may include some similar elements to the semiconductor device shown inFIG. 2B. Hereinafter, a detailed description of any overlapping constituent elements may be omitted.

Referring toFIG. 3, a buried word line104′ crossing the active region103may include a stack of a metal-based material104A and a semiconductor material104B. The edge portion104D′ of the buried word line104′ may also include the metal-based material104A. The buried portion BP and the protruding portion PP, which form the edge portion104D′ of the buried word line104′ crossing the dummy active region103D, may be all formed of a metal-based material104A.

The upper surface T1of the active region103may be positioned at a higher level than the upper surface T2of the dummy active region103D. The upper surface T1of the active region103may be positioned at a higher level than the upper surface L1′ of the buried word line104′. The upper surface T2of the dummy active region103D may be positioned at a lower level than the upper surface L2of the edge portion104D′ of the buried word line104′. The upper surface L2of the edge portion104D′ of the buried word line104′ may be positioned at a lower level than the upper surface T1of the active region103.

The edge portion104D′ of the buried word line104′ may include a buried portion BP buried in the dummy active region103D and a protruding portion PP positioned over the buried portion BP. The upper surface L2of the edge portion104D′ of the buried word line104′ may be provided by the upper surface of the protruding portion PP. The upper surface L2of the protruding portion PP may be positioned at a higher level than the upper surface T2of the dummy active region103D. The upper surface L2of the protruding portion PP may be positioned at a lower level than the upper surface T1of the active region103. The upper surface of the buried portion BP and the upper surface T2of the dummy active region103D may be positioned at the same level. The height of the protruding portion PP may be greater than the height of the buried portion BP. The protruding portion PP may include sidewalls and the upper surface L2. The upper surface L2of the protruding portion PP may be lower than the upper surface L1′ of the semiconductor material104B.

The upper surface L2of the protruding portion PP may be covered by a capping layer107. The bottom surface and the sidewalls of the buried portion BP may be covered by a gate dielectric layer106. The gate dielectric layer106may extend to cover the sidewalls of the protruding portion PP as shown inFIG. 3. The capping layer107may cover the gate dielectric layer106which is over the sidewalls of the protruding portion PP. The buried word line104′ is fully buried within the active region103and only partially buried in the dummy active region103D.

FIG. 4is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. The semiconductor device ofFIG. 4may include some similar elements to the semiconductor device shown inFIG. 3. Hereinafter, a detailed description of any overlapping constituent elements may be omitted.

Referring toFIG. 4, a buried word line104′ crossing the active region103may include a stack of a metal-based material104A and a semiconductor material104B. An edge portion104D′ of the buried word line104′ may also include the metal-based material104A. The buried portion BP and the protruding portion PP, which form the edge portion104D′ of the buried word line104′ crossing the dummy active region103D, may be formed of the metal-based material104A. A contact plug110′ may be coupled to the edge portion104D′ of the buried word line104′ and, more specifically, to the protruding portion PP of the edge portion104D′. The width W1of the contact plug110′ may be greater than the width W2of the edge portion104D′ of the buried word line104′.

The bottom portion of the contact plug110′ may include a first portion CB1overlapping with the edge portion104D′ of the buried word line104′ and a second portion CB2overlapping with the capping layer107. For example, the first portion CB1of the contact plug110′ may overlap and be in direct contact with the upper surface protruding portion PP of the edge portion104D′ of the buried word line104′, and the second portion CB2of the contact plug110′ may overlap and be in direct contact with the capping layer107. The buried word line104′ is fully buried within the active region103and only partially buried in the dummy active region103D.

FIG. 5is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. The semiconductor device ofFIG. 5may include some similar elements to the semiconductor devices illustrated inFIGS. 3 and 4. Hereinafter, a detailed description of any overlapping constituent elements may be omitted.

Referring toFIG. 5, a buried word line104′ crossing the active region103may include a stack of a metal-based material104A and a semiconductor material104B. An edge portion104D′ of the buried word line104′ may also include the metal-based material104A. The buried portion BP and the protruding portion PP, which form the edge portion104D′ of the buried word line104′ crossing the dummy active region103D′ may be all formed of the metal-based material104A.

A contact plug110″ may be coupled to the edge portion104D′ of the buried word line104′. The width W1of the contact plug110″ may be greater than the width W2of the edge portion104D′ of the buried word line104′.

The bottom portion of the contact plug110″ may include a first portion CB1overlapping with the edge portion104D′ of the buried word line104′ and a second portion CB2′ overlapping with the capping layer107. The second portion CB2′ of the contact plug110″ may overlap with one sidewall of the protruding portion PP. The contact plug110″ may be in direct contact with the upper surface of the protruding portion PP of the edge portion104D′ and may also be in direct contact with an upper part of the gate dielectric layer106that covers an upper part of one of the sidewalls of the protruding portion PP of the edge part104D′. The buried word line104′ is fully buried within the active region103and only partially buried in the dummy active region103D.

FIGS. 6A to 6Hare cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with an embodiment of the present invention.FIGS. 6A to 6Hillustrate an example of a method for fabricating the semiconductor device shown inFIG. 3.

Referring toFIG. 6A, an isolation layer12may be formed in a substrate11. A plurality of active regions1may be defined by the isolation layer12. The isolation layer12may be formed by a Shallow Trench Isolation (STI) process. For example, the substrate11may be etched to form an isolation trench (not shown). The isolation trench may be filled with a dielectric material to form the isolation layer12. The isolation layer12may include silicon oxide, silicon nitride, or a combination thereof. A Chemical Vapor Deposition (CVD) process or other deposition processes may be used to fill the isolation trench with a dielectric material. A planarization process such as chemical-mechanical polishing (CMP) may additionally be used. Each of the active regions13may have the same shape. From the perspective of a top view, the individual active regions13may have an island-shape surrounded by the isolation layer12. The individual active regions13may extend in a diagonal direction. The individual active regions13may have a long axis and a short axis. The length of the long axis may be greater than the length of the short axis.

The substrate11may include a first region R1and a second region R2. The active regions13may be formed in the first region R1. A plurality of dummy active regions13D may be formed in the second region R2. The dummy active regions13D and the active regions13may have different sizes. The dummy active regions13D may have the same length or different lengths. The individual dummy active regions13D may have a line shape extending along a diagonal direction. The individual dummy active regions13D may be greater than the individual active regions13. For example, the individual dummy active regions13D and the individual active regions13may extend in the same direction, but the individual dummy active regions13D may extend longer than the individual active regions13. As described above, the dummy active regions13D may have a line shape that is a longer elongated shape (relative to the active regions13), while the active regions13may have a shorter elongated shape (relative to the dummy active regions13D) referred to as an island shape. As will be described later, the individual active regions13may have a size that is sufficiently large that two word lines are placed therein, and the individual dummy active regions13D may have a size that is sufficiently large that at least three word lines are placed therein. In some embodiments, two word lines may be disposed in the individual dummy active regions13D, but in this case, too, the individual dummy active regions13D may be greater than the individual active regions13.

Referring toFIG. 6B, a plurality of trenches15may be formed in the substrate11. The trenches15may be formed in a line shape traversing the active region13and the isolation layer12. The trenches15may be formed by an etching process of the substrate11using the hard mask layer14as an etching mask. The hard mask layer14may be formed over the substrate11and may have a plurality of line-shaped openings. The hard mask layer14may be formed of a material having an etch selectivity with respect to the substrate11. For example, the hard mask layer14may be of silicon oxide such as Ultra Low Temperature Oxide (ULTO) or Tetra-Ethyl-Ortho-Silicate (TEOS). The trenches15may be formed to have a depth that is shallower than the bottom surface of the isolation layer12. The trenches15may have a depth sufficient to increase the average cross-sectional area of the word line which is to be formed subsequently. As a result, the resistance of the word line may be reduced. The bottom edge of the trenches15as shown inFIG. 6Bare flat. However, the bottom edge of the trenches15according to another embodiment of the present invention (not shown) may have a curvature. The neighboring trenches15may be parallel to each other by being spaced apart from each other.

Although not illustrated, a fin region (not shown) may be formed after the trenches15are formed. In order to form the fin region, the isolation layer12below the trenches15may be selectively recessed. As a result, the active region13below the trenches15may include a fin region that is positioned at a higher level than the recessed isolation layer12.

The trenches15may be formed in the first region R1. The trenches15may each include a trench edge portion15D positioned in the second region R2. The trench edge portion15D may be formed by etching the dummy active regions13D and the isolation layer12.

The trenches15positioned in the isolation layer12may be deeper than the trenches15positioned in the active region13and the dummy active region13D. The trench edge portion15D may have an elongated shape extending in a direction crossing the dummy active regions13D.

Referring toFIG. 6C, a gate dielectric layer16may be formed on the surface of the trenches15. Before the gate dielectric layer16is formed, etch damage on the surface of the trenches15may be cured. For example, after a sacrificial oxide is formed by a thermal oxidation treatment, the sacrificial oxide may be removed. For example, the gate dielectric layer16may include silicon oxide.

The gate dielectric layer16may be formed, for example, by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The gate dielectric layer16formed by the deposition method may include, for example, a high-k material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The high-k material may include, for example, a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or combinations thereof. As for the high-k material, other known high-k materials may be selectively used. The gate dielectric layer16may include a stack of silicon oxide and a high-k material, where the high-k material may include a material having a higher oxygen atom surface density than silicon oxide.

According to another embodiment of the present invention, the gate dielectric layer16may be formed by a thermal oxidation process.

According to another embodiment of the present invention, the gate dielectric layer16may be formed by sequentially performing an ULTO deposition process and a high temperature oxidation process. The ULTO deposition process may refer to the deposition of an ultra low temperature silicon oxide. The ultra low temperature silicon oxide (ULTO) may be deposited at a temperature of approximately 400° C. The high temperature oxidation process may be an oxidation process performed at a temperature of approximately 1050° C. after the deposition of the ultra low temperature silicon oxide (ULTO). As described above, a decrease in the critical dimension of the active region13may be suppressed by the combination of the ULTO deposition process and the high temperature oxidation process.

Referring toFIG. 6D, a word line17may be formed. The word line17may partially fill a trench15over the gate dielectric layer16. The word line17may be referred to as a buried word line. The word line17may include a lower gate layer18and an upper gate layer19. The upper gate layer19may be formed over the lower gate layer18. The upper surface of the upper gate layer19may be positioned at a lower level than the upper surface of the hard mask layer14.

The lower gate layer18may fill the bottom portion of the trench15over the gate dielectric layer16. The lower gate layer18may include a low-resistance metal material. The lower gate layer18may include, for example, tungsten. The lower gate layer18may be formed, for example, by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. According to another embodiment of the present invention, the lower gate layer18may include a high work function material. For example, the lower gate layer18may include a high work function metal or a high work function polysilicon. The high work function polysilicon may include, for example, P-type polysilicon. The high work function metal may include, for example, nitrogen-rich titanium nitride (TiN). To form the lower gate layer18, a recessing process of a lower gate material may be performed after the trench15is gap-filled with the lower gate material (not shown). The recessing process may be performed by a dry etching process, for example, an etch-back process. The etch-back process may be performed using plasma. The lower gate layer18may be formed by an etch-back process of the lower gate material. According to another embodiment of the present invention, the recessing process may be performed by performing a planarization process first to expose the upper surface of the hard mask layer14and then performing an etch-back process subsequently. The upper surface of the lower gate layer18may be recessed to be lower than the upper surface of the active region13.

In order to form the upper gate layer19, after an upper gate material (not shown) is deposited to fill the trench15over the lower gate layer18, a recessing process of the upper gate material may be performed. The upper gate material may be formed, for example, by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The recessing process of the upper gate material may be performed by a dry etching process, for example, an etch-back process. The upper gate layer19may be formed by an etch-back process of the upper gate material. According to another embodiment of the present invention, the recessing process of the upper gate material may be performed by performing a planarization process to expose the upper surface of the hard mask layer14and then performing an etch-back process subsequently. The upper surface of the upper gate layer19may be positioned at a lower level than the upper surface of the active region13.

The upper gate layer19may have a lower work function than the lower gate layer18. The upper gate layer19may have a smaller work function than a mid-gap work function of silicon. The upper gate layer19may be referred to as a low work function gate layer. The upper gate layer19may include a low work function metal or a low work function polysilicon. The low work function polysilicon may include, for example, N-type polysilicon. The low work function metal may include, for example, titanium-rich titanium nitride (TiN). In this embodiment of the present invention, the upper gate layer19may be polysilicon doped with an N-type impurity.

The word line17formed in the first region R1may extend to be positioned in the second region R2. The word line17may include a word line edge portion17D positioned in the second region R2. The word line edge portion17D may partially fill the trench edge portion15D over the gate dielectric layer edge portion16D. The word line edge portion17D and the word line17may be formed at the same time. The word line edge portion17D and the word line17may be made of the same material. The word line edge portion17D and the word line17may have the same height. The word line edge portion17D may include a lower gate layer edge portion18D and an upper gate layer edge portion19D positioned over the lower gate layer edge portion18D. The lower gate layer edge portion18D may be a portion of the lower gate layer18and may refer to the lower gate layer18positioned in the second region R2. The upper gate layer edge portion19D may be a portion of the upper gate layer19and may refer to the upper gate layer19positioned in the second region R2. The word line edge portion17D may correspond to the edge portions104D and104D′ of the buried word line104shown inFIGS. 1 to 5.

The word line17positioned in the isolation layer12may be deeper than the word line17positioned in the active region13and the dummy active region13D. The word line edge portion17D may have an elongated shape extending in a direction crossing the dummy active regions13D.

Referring toFIG. 6E, a mask layer20may be formed. The mask layer20may be formed in the first region R1. The mask layer20may include a photoresist pattern or a hard mask material. The second region R2may be exposed by the mask layer20. The mask layer20may expose an etch target portion22of the second region R2. The etch target portion22may refer to a structure having a higher level than the bottom surface of the lower gate layer edge portion18D.

An etching process using the mask layer20may be performed, and the etch target portion22may be removed by the etching process. For example, the hard mask layer14, the upper gate layer edge portion19D, a portion of the gate dielectric layer edge portion16D, and a portion of the isolation layer12may be etched. Through the etching process of the etch target portion22, an isolation layer12′ with a lowered height and a gate dielectric layer edge portion16D′ with a lowered height may be formed in the second region R2. As the upper gate layer edge portion19D is removed, the lower gate layer edge portion18D may remain in the second region R2. The lower gate layer edge portion18D may fill the trench edge portion15D′ with a lowered height.

Additionally, the etching process using the mask layer20may etch a portion of the dummy active region13D. As a result, a dummy active region13D′ with a lowered height may be formed. The dummy active region13D′ with a lowered height may be simply referred to as a recessed dummy active region13D′.

The upper surface21of the recessed dummy active region13D′ may be positioned at a lower level than the upper surface L1of the lower gate layer edge portion18D, and the upper surface21of the recessed dummy active region13D′ may be positioned at a higher level than the bottom surface L2of the lower gate layer edge portion18D. The gate dielectric layer edge portion16D′ may cover the bottom surface and the sidewalls of the lower gate layer edge portion18D. The upper surface of the gate dielectric layer edge portion16D′ and the upper surface of the lower gate layer edge portion18D may be positioned at the same level.

As described above, in order to recess the dummy active region13D′, the dummy active region13D′ may be selectively etched with respect to the lower gate layer edge portion18D.

Referring toFIG. 6F, after the mask layer20is removed, a capping layer23may be formed. The capping layer23may include a dielectric material. For example, the capping layer23may include silicon nitride. In an embodiment, the capping layer23may have an oxide-nitride-oxide (ONO) structure.

The capping layer23may be formed in both the first region R1and the second region R2. The capping layer23formed in the second region R2may be simply referred to as a capping layer edge portion23D. The capping layer edge portion23D may cover the upper surface of the recessed dummy active region13D′. The capping layer edge portion23D may cover the upper surface of the lower gate layer edge portion18D. The capping layer edge portion23D may cover a portion of the sidewalls of the gate dielectric layer edge portion16D′. The capping layer edge portion23D may cover the upper surface and a portion of the sidewalls of the isolation layer12′.

The capping layer23formed in the first region R1may directly contact the upper gate layer19. The capping layer edge portion23D formed in the second region R2may directly contact the lower gate layer edge portion18D.

As described above, the capping layer edge portion23D may be filled in the second region R2between the neighboring lower gate layer edge portions18D.

Referring toFIG. 6G, an inter-layer dielectric layer24may be formed over the capping layer23. For example, the inter-layer dielectric layer24may include silicon oxide.

Subsequently, one or more contact holes25A and25B may be formed by etching the inter-layer dielectric layer24and the capping layer edge portion23D. The contact holes25A and25B may be formed in the second region R2. The contact holes25A and25B may land on the upper surface of the lower gate layer edge portion18D. The contact hole25A may land on the upper surface of the lower gate layer edge portion18D crossing the recessed dummy active region13D′. The contact hole25B may land on the upper surface of the lower gate layer edge portion18D buried in the isolation layer12′.

Referring toFIG. 6H, a metal wire27may be formed which is coupled to the lower gate layer edge portion18D through the contact holes25A and25B. The metal wire27may be electrically connected to the lower gate layer edge portion18D through the contact plug26. The contact plug26may fill the contact holes25A and25B.

According to the above-described embodiment of the present invention, by forming the dummy active region13D′ long, bending of the word line17may be suppressed.

Since the height of the dummy active region13D′ is lowered by using the mask layer20, the physical distance between the contact holes25A and25B and the dummy active region13D′ may be increased. Accordingly, a short circuit between the contact holes25A and25B and the dummy active region13D′ may be prevented. Since the capping layer edge portion23D between the lower gate layer edge portions18D is gap-filled the space, short circuits between the contact holes25A and256and the dummy active region13D′ may be further prevented. Since the capping layer edge portion23D between the neighboring lower gate layer edge portions18D is gap-filled, widening of the contact holes25A and25B may also be suppressed.

As a comparative example, when the dummy active regions13and13D′ are omitted, only the isolation layer12may be formed in the second region R2. Accordingly, bending of the edge portion of the word line17to which the contact plug26is coupled may be caused by the stress induced from the isolation layer12. The bending of the word line may result in a short circuit between the neighboring word lines. In contrast, in this embodiment of the present invention, even though the word line edge portion17D′ is subjected to the stress induced from the isolation layer12, the dummy active region13D′ may be able to support the word line edge portion17D′ so as to suppress the bending of the word line edge portion17D′.

As a comparative example, when the capping layer edge portion23D is not gap-filled between the neighboring lower gate layer edge portion18D, a short circuit between the contact holes25A and25B and the neighboring word line edge portion17D may occur. In contrast, in this embodiment of the present invention, the capping layer edge portion23D between the neighboring lower gate layer edge portions18D is gap-filled. Therefore, even though the critical dimensions of the bottom portions of the contact holes25A and25B increase, a short circuit with the neighboring word line edge portion17D′ may be suppressed.

FIGS. 7A to 7Eare cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention.

First, the gate dielectric layer16may be formed by a series of the processes illustrated inFIGS. 6A to 6C.

Subsequently, as shown inFIG. 7A, a word line27may be formed. The word line27may partially fill the trench15over the gate dielectric layer16. The word line27may be referred to as a buried word line. The word line27may include a single gate layer. The upper surface of the word line27may be positioned at a lower level than the upper surface of the hard mask layer14.

The word line27may include a low-resistance metal material. The word line27may include, for example, tungsten. The word line27may include a high work function material. The word line27may include a high work function metal or a high work function polysilicon. The high work function polysilicon may include, for example, a P-type polysilicon. The high work function metal may include, for example, nitrogen-rich titanium nitride (TiN). To form the word line27the trench15may be gap-filled with a gate material (not shown) and then the gate material may be recessed. The recessing process may be performed by a dry etching process, for example, an etch-back process. The etch-back process may be performed using plasma. The word line27may be formed by an etch-back process of the gate material. According to another embodiment of the present invention, the recessing may be performed by performing a planarization process to expose the upper surface of the hard mask layer14and then performing an etch-back process. The upper surface of the word line27may be recessed to a level that is lower than the upper surface of the active region13. In this embodiment of the present invention, the word line27may include a TiN/W stack.

The word line27formed in the first region R1may extend to be positioned in the second region R2. The word line27may include a word line edge portion27D positioned in the second region R2. The word line edge portion27D may partially fill the trench edge portion15D over the gate dielectric layer edge portion16D. The word line edge portion27D and the word line27may be formed at the same time. The word line edge portion27D and the word line27may be made of the same material. The word line edge portion27D and the word line27may have the same height.

The word line27positioned in the isolation layer12may be deeper than the word line27positioned in the active region13and the dummy active region13D. The word line edge portion27D may have an elongated shape extending in a direction crossing the dummy active regions13D.

Referring toFIG. 7B, a mask layer20may be formed. The mask layer20may be formed in the first region R1. The mask layer20may include a photoresist pattern or a hard mask material. The second region R2may be exposed by the mask layer20. The mask layer20may expose the etch target portion22of the second region R2. The etch target portion22may refer to a structure positioned at a higher level than the upper surface of the word line edge portion27D.

An etching process using the mask layer20may be performed, and the etch target portion22may be removed by the etching process. For example, the hard mask layer14, a portion of the word line edge portion27D, a portion of the gate dielectric layer edge portion16D, and a portion of the isolation layer12may be etched. Through the etching process of the etch target portion22, an isolation layer12′ with a lowered height and a gate dielectric layer edge portion16D′ with a lowered height may be formed in the second region R2. The word line edge portion27D′ with a lowered height may remain in the second region R2, as a portion of the word line edge portion27D is removed. The word line edge portion27D′ may fill the trench edge portion15D′ with a lowered height.

Additionally, the etching process using the mask layer20may etch a portion of the dummy active region13D. As a result, a dummy active region13D′ with a lowered height may be formed. The dummy active region13D′ with a lowered height may be simply referred to as a recessed dummy active region13D′.

The upper surface21of the recessed dummy active region13D′ may be positioned at a lower level than the upper surface L1of the word line edge portion27D′, and the upper surface21of the recessed dummy active region13D′ may be positioned at a higher level than the bottom surface L2of the word line edge portion27D′. The gate dielectric layer edge portion16D′ may cover the bottom surface and the sidewalls of the word line edge portion27D′. The upper surface of the gate dielectric layer edge portion16D′ and the upper surface of the word line edge portion27D′ may be positioned at the same level.

The word line edge portion27D′ may have a lower upper surface than the word line27.

Referring toFIG. 7C, after the mask layer20is removed, a capping layer23may be formed. The capping layer23may include a dielectric material. The capping layer23may include silicon nitride. The capping layer23may have an oxide-nitride-oxide (ONO) structure.

The capping layer23may be formed in both of the first region R1and the second region R2. The capping layer23formed in the second region R2may be simply referred to as a capping layer edge portion23D. The capping layer edge portion23D may cover the upper surface of the recessed dummy active region13D′. The capping layer edge portion23D may cover the upper surface of the word line edge portion27D′. The capping layer edge portion23D may cover a portion of the sidewalls of the gate dielectric layer edge portion16D′. The capping layer edge portion23D may cover the upper surface and a portion of the sidewalls of the isolation layer12′.

The capping layer23formed in the first region R1may directly contact the word line27. The capping layer edge portion23D formed in the second region R2may directly contact the word line edge portion27D′.

As described above, in the second region R2, the capping layer edge portion23D between the neighboring word line edge portions27D′ may be filled.

Referring toFIG. 7D, an inter-layer dielectric layer24may be formed over the capping layer23. The inter-layer dielectric layer24may include silicon oxide.

Subsequently, one or more contact holes25A and25B may be formed by etching the inter-layer dielectric layer24and the capping layer edge portion23D. The contact holes25A and25B may be formed in the second region R2. The contact holes25A and25B may land on the upper surface of the word line edge portion27D′. The contact hole25A may land on the upper surface of the word line edge portion27D′ crossing the recessed dummy active region13D′. The contact hole25B may land on the upper surface of the word line edge portion27D′ buried in the isolation layer12′.

Referring toFIG. 7E, a metal wire27may be formed which is coupled to the word line edge portion27D′ through the contact holes25A and25B. The metal wire27may be electrically connected to the word line edge portion27D′ through the contact plug26. The contact plug26may fill the contact holes25A and256.

FIG. 8is a cross-sectional view of a semiconductor device200in accordance with another embodiment of the present invention.

Referring toFIG. 8, the semiconductor device200may be a portion of a memory cell, and the memory cell may include a DRAM memory cell.

The semiconductor device200may include a bit line structure BL that is positioned at a higher level than the buried word line104. The bit line structure BL may be oriented at a direction crossing the orientation of the buried word line104(not shown), and a capacitor CAP that is positioned at a higher level than the bit line structure BL while being coupled to a portion of the active region103. The capacitor CAP may be coupled to a portion of the active region103through a storage node contact plug (SNC). The bit line structure BL may be coupled to another portion of the active region103through a bit line contact plug BLC.

The buried word line104may correspond to the word lines104,17and27according to the above-described embodiments of the present invention. Therefore, the buried word line104may include the word line edge portion104D.

According to the embodiments of the present invention, it is possible to suppress the bending of a word line by forming a dummy active region long.

According to the embodiments of the present invention, since the height of a dummy active region is lowered, a short circuit between a contact hole and a dummy active region may be prevented.

According to the embodiments of the present invention, since a capping layer edge portion between the word line edge portions is gap-filled, a short circuit between the contact hole and the dummy active region may be further prevented.

According to the embodiments of the present invention, since the capping layer edge portion is between the neighboring word line edge portions, widening of the contact hole may be suppressed.

According to the embodiments of the present invention, the connection between a word line contact plug and a word line may be improved, and accordingly, electrical characteristics and reliability of the semiconductor device may be improved.