Methods to form memory devices having a capacitor with a recessed electrode

Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

FIELD OF THE PRESENT DISCLOSURE

The disclosed embodiments of the present disclosure relate generally to metal-insulator-metal (MIM) capacitors, and relate more particularly to techniques suitable for manufacturing such capacitors in embedded technologies.

BACKGROUND OF THE PRESENT DISCLOSURE

Memory access time is a significant factor affecting the performance of computer systems. System performance can typically be enhanced by placing the memory on the same die or in the same package as the processor, and embedded dynamic random access memory (embedded DRAM, or eDRAM) is an example of such on-die or on-package memory technology. Because capacitors are the data storage element of eDRAM, the fabrication of eDRAM involves the manufacture of embedded capacitors—a process that includes subtractive metal patterning. Traditionally, subtractive metal patterning has been done with numerous processing operations including plasma etching. Plasma etches are highly anisotropic, making it very difficult to cleanly remove metal from a surface oriented orthogonally to the wafer surface and plasma field.

DETAILED DESCRIPTION OF THE DRAWINGS

In one embodiment of the present disclosure, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom of the excavated feature and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes. The described method may be used to produce a MIM capacitor suitable for an eDRAM device.

In certain embodiments, a method of fabricating a MIM capacitor includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. A first electrically conductive layer is then deposited on the excavated feature with a resputter ratio that causes beveling of upper corners of the excavated feature in order to form a recessed lower electrode layer within the excavated feature. Next, the method includes depositing an electrically insulating layer on the first electrically conductive layer and depositing a second electrically conductive layer (e.g., upper electrode) on the first electrically insulating layer. At least a portion of the beveled upper corners of the excavated feature includes no first electrical conductive layer. This technique performs selective deposition by sputtering high energy metal or Argon ions to provide isolation between the capacitor electrodes.

It was mentioned above that eDRAM capacitors are manufactured using a subtractive metal patterning process. Traditionally, subtractive metal patterning has been done by plasma etching. Plasma etches are highly anisotropic, making it very difficult to cleanly remove metal from a surface oriented orthogonally to the wafer surface and plasma field. Additionally, subtractive metal patterning requires a large number of processing operations. One approach deposits a lower electrode layer in a dielectric feature, fills the feature with a spin-on film, plasma etches a top portion of the film, wet etches an exposed portion of the lower electrode layer, removes the film, deposits a dielectric layer, deposits the upper electrode, and then planarizes the MIM capacitor. This approach suffers from pattern-dependent lower electrode height variation, which causes significant capacitance variation for the MIM capacitor.

Embodiments of the present disclosure overcome these problems by using selective etch techniques and chemicals to recess one of the electrodes after the planarization of the MIM capacitor, thus enabling the efficient manufacture of eDRAM capacitors. Other embodiments of the present disclosure overcome these problems by using a selective deposition of the lower electrode to form a recessed lower electrode. The recessed electrode techniques of the present disclosure require fewer process operations, do not suffer from pattern-dependent electrode height, and do not have to account for polish variation when determining how to recess one of the electrodes. The reduced electrode height variation provides a higher recessed electrode height, which provides more capacitance.

The recessed electrode techniques of the present disclosure provide a sequential deposition of a lower electrode layer, high-k dielectric layer, and upper electrode layer without intervening wet processing operations. As used herein, the phrase “high-k” refers to materials having a dielectric constant, k, greater than that of silicon dioxide, that is, greater than about 4. In an embodiment, a selective etch recesses one of the electrodes after planarization of the MIM capacitor. A subsequent filling of an electrode recess with a CVD dielectric provides robust isolation between upper and lower electrodes. The resulting capacitor has fewer defects and higher surface area, resulting in a better yield and performance, respectively.

FIG. 1is a flowchart illustrating a method100of forming an embedded MIM capacitor according to an embodiment of the present disclosure. As an example, method100may result in the formation of a structure in which an embedded memory device may be constructed. The method100includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature at block102. In one embodiment, the upper portion includes dielectric material (e.g., sidewalls of the feature) and the lower portion includes an electrically conductive layer that at least partially defines the bottom of the feature at block102. Next, the method100includes depositing a first electrically conductive layer in the feature at block104. Then, the method100includes depositing an electrically insulating layer on the first electrically conductive layer at block106. The method100further includes depositing a second electrically conductive layer on the electrically insulating layer at block108. Then, a conductive material is deposited on the second electrically conductive layer at block110. The conductive material fills the feature.

In one embodiment, the first electrically conductive layer forms a bottom electrode of the capacitor. The second electrically conductive layer and conductive material in combination form a top electrode of the capacitor. Then, an upper portion of the MIM capacitor is removed to expose an upper surface of the first and second electrically conductive layers at block112. In one embodiment, the upper portion of the capacitor is removed using standard semiconductor processing operations such as etching. For example, a chemical-mechanical planarization (CMP) process or plasma etch process may perform the etch. The etch may be stopped upon reaching an upper portion of the dielectric material. The method100further includes selectively etching the first or second electrically conductive layer to recess the first or second electrically conductive layer, respectively at block114.

In an embodiment, the selective etch includes a selective wet etch that recesses the first electrically conductive layer (e.g., bottom electrode) without substantially etching exposed portions of the electrically insulating layer nor the second electrically conductive layer (e.g., top electrode). In another embodiment, the selective wet etch recesses the second electrically conductive layer without substantially etching exposed portions of the electrically insulating layer nor the first electrically conductive layer.

FIG. 2is a cross-sectional view of an excavated feature230of an embedded memory device200, such as an eDRAM or the like, according to an embodiment of the present disclosure. As illustrated inFIG. 2A, embedded memory device200comprises an electrically conductive layer210, an electrically insulating layer212, an electrically insulating layer214, and etch stop layers216and218. An excavated feature230is an opening or recess defined by a lower portion (e.g.,210,212) and an upper portion (e.g.,214,216,218).

FIG. 3Ais a cross-sectional view of a MIM capacitor272formed in the excavated feature230of the embedded memory device200, according to an embodiment of the present disclosure. The MIM capacitor272includes an electrically conductive layer240located in excavated feature230adjacent to and electrically connected to electrically conductive layer210, an electrically insulating layer250located in excavated feature230deposited on electrically conductive layer240, and an electrically conductive layer260located in excavated feature230and deposited on electrically insulating layer250. The MIM capacitor272may also include a conductive material270deposited on the layer260. The material270fills a recess of the MIM capacitor272. In one embodiment, the layers240and260may be formed of Tantalum (Ta), Tantalum Nitride (TaN), or Titanium Nitride (TiN) using sputter, physical vapor deposition (PVD), or atomic layer deposition (ALD) processing.

As an example, electrically conductive layer210can be a metal line made of copper or the like. As another example, electrically conductive layer270can be a plug made of copper or another metal. In one embodiment, the metal of electrically conductive layer210and the metal of electrically conductive layer270are the same (e.g., copper). As another example, etch stop layers can be a CVD dielectric (e.g., Silicon Carbide (SiC)). As another example, electrically insulating layer250can be a conformal dielectric film, which in one embodiment comprises a high-k metal oxide or other high-k material. The layer250may be formed of Hafnium Oxide (HfO2), Zirconium Oxide (ZrO2), Tantalum Oxide (Ta2O5), Barium Strontium Titanate (e.g., BaSrTiO3), Aluminum Oxide (Al2O3), or combinations of these materials (e.g., ZrO2/Al2O3/ZrO2) using ALD or other semiconductor processing technology.

FIG. 3Bis a cross-sectional view of embedded memory device200at a different particular point in its manufacturing process according to an embodiment of the present disclosure. As illustrated inFIG. 3B, an upper portion of capacitor272has been removed such that the remaining device is planarized. In one embodiment, the portion of the capacitor272that is removed is etched away using a plasma etch or CMP operation or a combination of these operations. The etch may be stopped upon reaching an upper portion of the dielectric layer214. At this point in the process, the electrode layers240and260are merely separated by the thickness of the dielectric layer250. In order to ensure that a current leakage path is not created across the top of the dielectric layer250, the present design of the embedded memory device increases the distance between the electrode layers240and260by recessing one of the electrode layers240or260.

FIG. 3Cis a cross-sectional view of embedded memory device200after a selective etch recesses a conductive electrode layer240of the MIM capacitor according to an embodiment of the present disclosure. The selective etch can selectively etch the electrically conductive layer240or layer260to recess one of these layers. In an embodiment, the selective etch includes a selective wet etch that recesses the electrically conductive layer240(e.g., bottom or lower electrode) without substantially etching exposed portions of the electrically insulating layer250nor the electrically conductive layer260(e.g., top or upper electrode). For this embodiment, the layer240may include TiN and the layer260may include Ta or TaN.

In another embodiment, the selective wet etch recesses the layer260without substantially etching exposed portions of the electrically insulating layer250nor the layer240. For this embodiment, the layer260may include TiN and the layer240may include Ta or TaN.

In some embodiments, the selective wet etch includes hydrogen peroxide chemistries (acidic or alkali) in order to etch titanium alloys and ceramics with high selectivity against etching of high-k dielectrics and copper. In one embodiment, the selective wet etch includes approximately 15% weight hydrogen peroxide with pH adjusted to approximately 8 at a temperature of approximately 50 C. This etch chemistry etches TiN with greater than 40:1 selectivity to HfO2, Ta, TaN, Cu, and interlayer dielectric layer (e.g.,214). The amount of electrode removed varies dependent on a given capacitor application. This amount of removed electrode can vary from 10-20 Angstroms (A) up to 500-600A or possibly a greater amount.

FIG. 3Dis a cross-sectional view of embedded memory device200after formation of a via to the MIM capacitor according to an embodiment of the present disclosure. An etchstop layer219and interlayer dielectric layer280have been deposited on the device. The via connection290to the upper electrode (e.g., material270and layer260) is patterned, etched, and filled. These operations can be accomplished using conventional via patterning techniques.

In certain embodiments, a MIM capacitor having a recessed electrode can be formed with a selective deposition of the recessed electrode.FIG. 4is a flowchart illustrating a method400of forming a MIM capacitor with a recessed electrode according to an embodiment of the present disclosure. As an example, method400may result in the formation of a structure in which an embedded memory device may be constructed. The method400includes forming an excavated feature defined by a lower portion that forms a bottom of the excavated feature and an upper portion that forms sidewalls of the excavated feature at block402. The method optionally includes a sputtering operation to fabricate a beveled region of the upper corners of the excavating feature at block404. This sputtering operation is optionally performed prior to the deposition of the first electrical conductive layer, which occurs at block406. The first electrically conductive layer is deposited with a resputter ratio that causes beveling of upper corners of the excavated feature in order to form a recessed lower electrode layer within the excavated feature at block406. At least a portion of the beveled upper corners of the excavated feature includes no first electrical conductive layer as described in more detail below and illustrated inFIGS. 5A-5D. If operation404is performed, then operation406may be more effective in selectively depositing the first electrically conductive layer on the lower portion (e.g., bottom) and the upper portion (e.g., sidewalls) of the excavated feature that is below the beveled region, which is completely or at least partially without the first conductive layer.

The method400includes depositing an electrically insulating layer on the first electrically conductive layer at block408. The method400includes depositing a second electrically conductive layer on the first electrically insulating layer at block410. The method400includes depositing a conductive material on the second electrically conductive layer in order to fill the MIM capacitor at block412. The method400includes removing an upper portion of the MIM capacitor to form a planarized MIM capacitor at block414. The planarized MIM capacitor has the lower electrode layer recessed with respect to an upper electrode layer formed of the remaining second electrically conductive layer and conductive material.

FIG. 5Ais a cross-sectional view of an excavated feature530of an embedded memory device500, such as an eDRAM or the like, according to an embodiment of the present disclosure. As illustrated inFIG. 5A, embedded memory device500comprises an electrically conductive layer510, an electrically insulating layer512, an electrically insulating layer514, and etch stop layers516and518. An excavated feature530is an opening or recess defined by a lower portion (e.g.,510,512) and an upper portion (e.g.,514,516,518). A metal-insulator-metal (MIM) capacitor is deposited on the excavated feature530as illustrated inFIGS. 5A-5D.FIG. 5Aillustrates a first electrically conductive layer (e.g.,540,541) deposited with a resputter ratio that causes beveling of upper corners (e.g., beveled regions542) of the excavated feature530. The first electrically conductive layer includes an upper portion541and a lower portion540that is a recessed lower electrode layer of a MIM capacitor deposited on the excavated feature. At least a portion of the beveled regions542of the excavated feature includes no first electrical conductive layer. The upper portion541and lower portion540are separated and electrically insulated from each other. In an embodiment, the resputter ratio is greater than 1. In another embodiment, the resputter ratio is approximately 1.4 to 1.6.

FIG. 5Bis a cross-sectional view of the formation of a MIM capacitor in the excavated feature530of the embedded memory device500in a different point of fabrication, according to an embodiment of the present disclosure. An electrically insulating layer550is deposited on the electrically conductive layer (e.g.,540,541).

FIG. 5Cis a cross-sectional view of the formation of a MIM capacitor572in the excavated feature530of the embedded memory device500in a different point of fabrication, according to an embodiment of the present disclosure. An electrically conductive layer560is deposited on the electrically insulating layer550. A conductive material570fills the MIM capacitor572. The MIM capacitor572includes the lower electrode540, insulating layer550, conductive layer560(e.g., upper electrode), and material570.

In an embodiment, upper corners of the excavating feature530include a beveled region542that is caused by a sputtering operation (e.g., metal ions, Argon). This sputter operation can be performed prior to the deposition of the electrical conductive layer (e.g.,540,541).

FIG. 5Dis a cross-sectional view of the formation of a MIM capacitor572in the excavated feature530of the embedded memory device500in a different point of fabrication, according to an embodiment of the present disclosure.FIG. 5Dillustrates the removal of an upper portion of the MIM capacitor572to form a planarized MIM capacitor having the lower electrode layer540recessed with respect to an upper electrode layer560formed of the remaining second electrically conductive layer. In one embodiment, the conductive layer (e.g.,540,541) may be formed of Ta, TaN, Ti, or TiN using a sputter processing. The layer560may be formed of Ta, TaN, Ti, or TiN using sputter, physical vapor deposition (PVD), or atomic layer deposition (ALD) processing.

In some embodiments, the bottom electrode540can be recessed during the deposition process by the following processes alone or in combination.

1. deposit Ti, Ta, TiN, or TaN by using sputtering to bevel the top corners of the excavated feature530prior to and/or during the bottom electrode metal deposition. Deposition is done in a regime where there is a “net etch” at the top corners. The “net etch” condition results in the bottom plate being recessed.

2. flaring out the etch during the capacitor patterning, so that sputtering is more effective at depositing the electrode metal on the bottom and sidewalls while leaving the top corners metal free.

In one specific embodiment, one such stack and etch combination is as follows. The bottom electrode plate540is formed with Ta with a high resputter rate. The PVD High-k dielectric includes HfO2 using ALD processing. The top electrode includes Ta (or TaN) using sputter, PVD, or ALD deposition. The conductive material570is formed with copper.

As an example, electrically conductive layer510can be a metal line made of copper or the like. As another example, electrically conductive layer570can be a plug made of copper or another metal. In one embodiment, the metal of electrically conductive layer510and the metal of electrically conductive layer570are the same (as in the case where both are copper). As another example, etch stop layers can be a CVD dielectric (e.g., SiC). As another example, electrically insulating layer550can be a conformal dielectric film, which in one embodiment comprises a high-k metal oxide or other high-k material. The layer550may be formed of HfO2, ZrO2, Ta2O5, BaSrTiO3, Al2O3, or combinations of these materials (e.g., ZrO2/Al2O3/ZrO2) using ALD or other semiconductor processing technology.

As illustrated inFIG. 5D, an upper portion of capacitor572has been removed such that the remaining device is planarized. In one embodiment, the portion of the capacitor572that is removed is etched away using a plasma etch or CMP operation or a combination of these operations. The etch may be stopped upon reaching an upper portion of the dielectric layer541. Next, an etchstop layer519and interlayer dielectric layer580have been deposited on the device. The via connection590to the upper electrode (e.g., material570and layer560) is patterned, etched, and filled. These operations can be accomplished using conventional via patterning techniques.

FIG. 6Ais a cross-sectional view of a portion of an excavated feature630after deposition of a lower electrode layer on the feature according to an embodiment of the present disclosure. A dielectric region610forms a sidewall of the excavated feature630with a lower electrode layer640and upper conductive portion641being deposited on the excavated feature during a sputtering operation having a high resputtering ratio. A copper layer620is formed after the sputtering operation that depositions layer640and portion641. The excavated feature630has a beveled region642.

FIG. 6Bis an exploded view of the beveled region642according to an embodiment of the present disclosure. The beveled region642does not contain lower electrode layer640nor upper conductive portion641, which are selectively deposited with physical vapor deposition (PVD) on the dielectric region610.

The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the present disclosure described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of operations, the order of such operations as presented herein is not necessarily the only order in which such operations may be performed, and certain of the stated operations may possibly be omitted and/or certain other operations not described herein may possibly be added to the method. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Although the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made without departing from the spirit or scope of the present disclosure. Accordingly, the disclosure of embodiments of the present disclosure is intended to be illustrative of the scope of the present disclosure and is not intended to be limiting. It is intended that the scope of the present disclosure shall be limited only to the extent required by the appended claims. For example, to one of ordinary skill in the art, it will be readily apparent that the embedded memory device and the related structures and methods discussed herein may be implemented in a variety of embodiments, and that the foregoing discussion of certain of these embodiments does not necessarily represent a complete description of all possible embodiments.