SEMICONDUCTOR STRUCTURE INCLUDING LINES OF DIFFERENT HEIGHT

A method for manufacturing a semiconductor structure includes: forming a patterned first layer which is made of a first electrically conductive material, and which includes first lines, second lines, and a connection portion disposed on a part of one of the first lines, the first lines having a height lower than a height of the second lines; forming a first via which is connected to an upper surface of the connection portion, the first via having a height above the connection portion; and forming a second via which is connected to an upper surface of one of the second lines, the second via having a height that is the same as the height of the first via above the connection portion.

BACKGROUND

As scaling down of semiconductor device continues in the IC industry, there is an urgent need to enhance interconnect structures, so as to improve performance thereof. For instance, there is research focusing on RC delay of interconnect structures to achieve a reduction in resistance and/or capacitance of interconnect structures.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “on,” “above,” “top,” “bottom,” “bottommost,” “upper,” “uppermost.” “lower,” “lowermost,” “over,” “beneath,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

For the purposes of this specification and appended claims, unless otherwise indicated, all numbers expressing amounts, sizes, dimensions, proportions, shapes, formulations, parameters, percentages, quantities, characteristics, or other numerical values used in the specification and claims, are to be understood as being modified in all instances by the term “about” even if the term “about” is not explicitly recited with the values, amounts or ranges. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and appended claims are not and need not be exact, but may be approximations and/or larger or smaller than specified as desired, may encompass tolerances, conversion factors, rounding off, measurement error, and other factors known to those of skill in the art depending on the desired properties sought to be obtained by the presently disclosed subject matter. For example, the term “about,” when used with a value, can capture variations of, in some aspects±10%, in some aspects ±5%, in some aspects±2.5%, in some aspects±1%, in some aspects±0.5%, and in some aspects±0.1% from the specified amount, as such variations are appropriate to perform the disclosed methods or employ the disclosed compositions.

By adopting different materials (e.g., metals and low-k materials) in interconnect structures, overall resistance and capacitance of the interconnect structures may be reduced, so that the interconnect structures are capable of fulfilling increasing demand with excellent performance. To achieve further enhancement, in some cases, low resistance, or low capacitance interconnect structures may be desired so as to satisfy different final product specifications. In view of this, new interconnect structures with lower capacitance and/or resistance are in urgent need.

The present disclosure is directed to a semiconductor structure including lines formed with different heights, and a method for manufacturing the same. Referring toFIG.24, the semiconductor structure includes a plurality of interconnect level structures, such as a first interconnect level structure60and a second interconnect level structure68. The first interconnect level structure60includes a first region41, a second region42and dielectric units29. The first region41includes a plurality of first lines232having a first height (H1), and a connection portion233(may be referred to as a semi via) formed on a part of a predetermined one of the first lines232. The second region42includes a plurality of second lines234that have a second height (H2) greater than the first height (H1). That is, at the first interconnect level structure60, the first region41, including the relatively shorter first lines232, may be considered as a relatively low capacitance region; and the second region42, including the relatively higher second lines234, may be considered as a relatively low resistance region. The first and second lines232,234are spaced apart from each other by the dielectric units29. In some embodiments, the connection portion233is formed on the part of the predetermined one of the first lines232between two adjacent ones of the dielectric units29in a self-aligned manner since the connection portion233and the predetermined one of the first lines232are integrally formed by patterning lines231as illustrated inFIGS.14to17. The second interconnect level structure61is formed on the first interconnect level structure60, and includes a third line62, and a first via63connected to an upper surface of the connection portion233of the first interconnect level structure60, so as to permit the predetermined one of the first lines232to be connected to the third line62through the first via63and the connection portion233. That is, the first via63and the connection portion233cooperatively form a via feature70that interconnects the third line61in the second interconnect level structure61, and the predetermined one of the first lines232in the first interconnect level structure60. In the case that the first and second lines232,234have the same height (not shown in figures), if a via (not shown), which is formed on one of the first lines232, is accidentally shifted toward an adjacent one of the dielectric units29, a minimal distance between the via and the corresponding adjacent one of the first lines232will be reduced, which undesirably affects time-dependent dielectric breakdown (TDDB) in the one of the dielectric units29. In this disclosure, the first lines232have a reduced height relative to the second lines234, and the connection portion233is formed in the self-aligned manner to compensate the reduced height, resulting in a minimal distance between the via and an adjacent one of the dielectric units being comparatively greater, and thus, even if the first via63is accidentally shifted toward one of the dielectric units29, time-dependent dielectric breakdown (TDDB) in the one of the dielectric units29is larger and more acceptable. In addition, although the first lines and second lines232,234are formed with different heights, the connection portion233facilitates depth loading issue in formation of the first via63over the relatively lower first lines232and compensates for the height difference of first and second lines232,234. Moreover, the first region41with a relatively low capacitance is substantially free of high-k material (e.g., etch stop layer material) or has the high-k material with a relatively smaller occupied area, which favors further reduction in capacitance of the first interconnect level structure60.

FIG.1is a flow diagram illustrating a method for manufacturing the semiconductor structure (for example, the semiconductor structure shown inFIG.24) in accordance with some embodiments.FIGS.2to26illustrate schematic views of intermediate stages of the method in accordance with some embodiments. Some repeating structures are omitted inFIGS.2to26for the sake of brevity. Additional steps can be provided before, after or during the method, and some of the steps described herein may be replaced by other steps or be eliminated.

Referring toFIG.1and the example illustrated inFIG.7, the method begins at step101, where a first layer23and dielectric units29are formed on a base structure. Step101may include sub-steps illustrated inFIGS.2to7in accordance with some embodiments.

Referring toFIG.2, a stack may include a substrate10, a front-end-of-line (FEOL) part (not shown), an interlayer dielectric (ILD) layer21, a glue layer22, and a first interconnect material layer23A that are sequentially formed on the substrate10. The stack may further include any other suitable components based on practical requirements and final product specification. For example, one or more interconnect structures (not shown), which may be considered as a portion of a back-end-of-line (BEOL) part, may be formed between the FEOL part and the ILD layer21.

The substrate10may be made of elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. The material for forming the substrate10may be doped with p-type impurities or n-type impurities, or undoped. In addition, the substrate10may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. Other suitable materials for the substrate10are within the contemplated scope of disclosure.

The FEOL part may include any suitable elements such as active devices (for example, transistors such as fin-type field-effect transistors (FinFET), nanosheet semiconductor devices, e.g. gate-all-around-field-effect transistors (GAAFET), forksheet-based devices, complementary transistors (CFET), or the like), passive devices (for example, capacitors, resistors, or the like), decoders, amplifiers, other suitable devices, and combinations thereof. Other suitable elements for the FEOL part are within the contemplated scope of disclosure.

The ILD layer21may include a low-k material, carbon-doped hydrogenated silicon oxide (SiOxCyHz), silicon oxide (SiOx), silicon carbon nitride (SiCN), oxygen-doped carbide (ODC), nitrogen-doped carbide (NDC), tetraethyl orthosilicate (TEOS), silicon nitride (SiNx), or the like, or combinations thereof. The ILD layer21may have a single-layer structure, or a multi-layered structure. The ILD layer21may be formed by one or more deposition processes (such as chemical vapour deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof. Other suitable materials, and/or configuration, and/or method for forming the ILD layer21are within the contemplated scope of disclosure.

The glue layer22may serve as a conduction layer and/or an adhesion layer between the ILD layer21and the first interconnect material layer23A. The glue layer22may include an electrically conducting material, or an adhesive material, such as tantalum (Ta), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), self-assembled monolayer (SAM), manganese nitride (MnNx), aluminum (Al), molybdenum (Mo), iridium (Ir), rhodium (Rh), graphene, or the like, or combinations thereof, but are not limited thereto. The glue layer22may be formed by one or more deposition processes (such as chemical vapour deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof. Other suitable materials and/or method for forming the glue layer22are within the contemplated scope of disclosure.

The first interconnect material layer23A may include a first electrically conductive material, and may be formed into conductive lines in subsequent steps. In some embodiments, the first interconnect material layer23A may include copper (Cu), ruthenium (Ru), tungsten (W), titanium (Ti), aluminum (Al), cobalt (Co), molybdenum (Mo), iridium (Ir), rhodium (Rh), or the like, or combinations thereof. The first interconnect material layer23A may be formed by one or more deposition processes (such as chemical vapour deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof. Other suitable materials for the first interconnect material layer23A are within the contemplated scope of disclosure.

Other elements and/or configuration of the stack are within the contemplated scope of the present disclosure.

Please note that inFIG.3and subsequent figures, the substrate10is not shown for the sake of brevity.

Referring toFIG.3, the first interconnect material layer23A (seeFIG.2) is formed into a plurality of lines231(which are formed into first and second lines232,234as shown inFIG.25), thereby forming the first layer23. The lines231are each elongated in an X direction, and spaced apart from each other in a Y direction transverse (e.g., perpendicular to) to the X direction. In some embodiments, the lines231may have a pitch ranging from about 12 nm to about 25 nm, but are not limited thereto. Each of the lines231may be formed with the second height (H2) along a Z direction transverse (e.g., perpendicular to) to the X direction and the Y direction. In some embodiments, the second height (H2) ranges from about 120 Å to about 300 Å, but is not limited thereto. Other ranges for the second height (H2) are within the contemplated scope of the present disclosure. In some embodiments, the lines231(formed from the first interconnect material layer23A) are made of a metallic material, and may be referred as metal lines or the conductive lines. Other materials for forming the lines231are within the contemplated scope of the present disclosure.

The lines231are spaced from each other by trenches241. The lines231and the trenches241may be formed by the following: forming a patterned mask (not shown, which may be a patterned hard mask or a patterned photoresist) over the first interconnect material layer23A; patterning the first interconnect material layer23A through the patterned mask using a suitable etching process; and removing the patterned mask. In some embodiments, formation of the patterned photoresist may involve coating a photoresist, exposing the photoresist through a photomask, developing the photoresist to form a patterned photoresist, and/or other suitable processes, but are not limited thereto. In some embodiments, portions of the glue layer22may also be removed during the patterning process so as to expose portions of the ILD layer21underneath. Other methods for forming the lines231and the trenches241are within the contemplated scope of the present disclosure.

Referring toFIG.4, a liner material layer25A is formed over the lines231, and in the trenches241over the exposed portions of the ILD layer21. In some embodiments, the liner material layer25A may include oxygen-doped carbide (ODC), a dielectric oxide (e.g., a metal oxide or silicon oxide), silicon nitride (SiNx), graphene, or the like, or combinations thereof, but are not limited thereto. In some embodiments, the liner material layer25A is formed in a conformal manner using one or more deposition processes (such as chemical vapour deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof). That is, the liner material layer25A may be conformally formed over top surfaces and side surfaces of the lines231, and over the exposed portions of the ILD layer21. Other materials, and/or methods for forming the liner material layer25A are within the contemplated scope of the present disclosure.

Referring toFIG.5, sacrificial elements26are formed on the liner material layer25A at bottoms of the trenches241. The sacrificial elements26will be removed to leave air gaps at bottoms of the trenches241in subsequent sub-step. In some embodiments, the sacrificial elements26may include a polymer. The polymer may be a hydrocarbon-based polymer, but is not limited thereto. In other embodiments, the sacrificial elements26may include polyurea, polylactic acid, polycaprolactone, poly(ethylene oxide), polyacrylate, polyvinyl alcohol, or the like, or combinations thereof. In some embodiments, the sacrificial elements26are formed by (i) spin coating the material(s) for forming the sacrificial elements26over the liner material layer25A to fill the trenches241at room temperature, (ii) performing a curing process to cure the material for forming the sacrificial elements26(e.g., at about 100° C. to about 250° C., but not limited thereto), and (iii) recessing the cured material to form the sacrificial elements26in the trenches241. The sacrificial elements26may be formed with a predetermined height according to practical needs. Other materials, and/or processes, and/or conditions suitable for forming the sacrificial elements26are within the contemplated scope of the present disclosure.

Referring toFIG.6, dielectric elements27are formed on the sacrificial elements26to fill the trenches241. Possible materials of the dielectric elements27may be similar to that of the ILD layer21, and thus are not described for the sake of brevity. In some embodiments, the dielectric elements27may be made of a material same as or different from that of the ILD layer21. The dielectric elements27may each have a single-layer structure, or a multi-layered structure. In certain embodiments, upper surfaces of the dielectric elements27may be flush with upper surfaces of the lines231. The dielectric elements27may be formed by depositing the material(s) for forming the dielectric elements27over the structure shown inFIG.5using one or more deposition processes (such as chemical vapour deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof), followed by removing excesses of the material(s) using one or more planarization processes such as chemical-mechanical planarization process (CMP), but is not limited thereto, so as to expose the lines231. After the one or more planarization processes, the dielectric elements27are respectively formed in the trenches241and the liner material layer25A shown inFIG.5is formed into a plurality of liners25which are respectively formed along trench defining walls of the trenches241. Other suitable materials, and/or configurations, and/or methods for forming the dielectric elements27and/or the liners25are within the contemplated scope of disclosure.

Referring toFIG.7, the sacrificial elements26(seeFIG.6) formed at the bottoms of the trenches241are removed to form air gaps242. As such, the dielectric units29are formed, each of which includes one dielectric element27, one liner25and one air gap242. The air gap242and the dielectric element27are separated from adjacent ones of the lines231by the liner25. Two adjacent ones of the first lines232and the second lines231are spaced apart from each other by a corresponding one of the dielectric units29. Each of the dielectric units29has an upper surface at a level which is the same as that of an upper surface of each of the lines231. In some embodiments, the sacrificial elements26are removed by, for example, a thermal treatment, but is not limited thereto. In other embodiments, the sacrificial elements26may merely be partially removed to respectively remain parts of which at the bottom of the trenches241. Other suitable materials, and/or configurations, and/or methods for forming the dielectric units29are within the contemplated scope of disclosure.

In some embodiments, the formation of the air gaps242is omitted, and sub-steps described with reference toFIGS.5to7may be modified by directly forming the dielectric elements27filling the entire trenches241.

By completing the sub-step described with reference toFIG.7, the first layer23and the dielectric units29are formed on the base structure. The first layer23includes a plurality of the lines231that are spaced apart from each other by the dielectric units29. The first layer23, and any other elements formed thereon opposite to the ILD layer21, may be considered as another portion of the back-end-of-line (BEOL) part. The first layer23will be formed into a patterned first layer23′ (seeFIG.24) in subsequent steps, in which the patterned first layer23′ is equivalent to a metal portion of the first interconnect level structure60described, or may be referred as a critical interconnect layer Mx. The base structure includes the substrate10(seeFIG.2), and the FEOL part (not shown), the ILD layer21, the patterned glue layer22(seeFIG.7).

The first layer23may include additional elements according to practical needs. Other materials, and/or methods, and/or configurations for forming the first layer23are within the contemplated scope of the present disclosure.

Referring toFIG.1and the example illustrated inFIG.9, the method proceeds to step102, where an etch stop layer28is formed over the first layer23and the dielectric units29, and a patterned first mask33is formed over the etch stop layer23. The patterned first mask33exposes a first portion of the etch stop layer28, and covers a second portion of the etch stop layer28. The first and second portions of the etch stop layer28respectively correspond in position to the first region41(which may be known as a relatively low capacitance region) and a second region42(which may be known as a relatively low resistance region) of the patterned first layer23′ (i.e., the metal portion of the first interconnect level structure60, seeFIG.24) formed in subsequent step. In some embodiments, the second lines234may each have a width wider than a width of each of the first lines232in the Y direction.

Step102may include sub-steps illustrated inFIGS.8to9in accordance with some embodiments.

Referring toFIG.8, the etch stop layer28, a first mask layer31, and a first photoresist layer32are sequentially formed over the first layer23. The etch stop layer28includes a high k material, silicon carbon nitride (SiCN), carbon-doped hydrogenated silicon oxide (SiOxCyHz), silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxynitride (AlOxNy), a metal oxide (e.g., aluminum oxide (AlOx), carbon-doped aluminum oxide (C:AlO) zirconium oxide (ZrOx)), oxygen-doped carbide (ODC), nitrogen-doped carbide (NDC), tetraethyl orthosilicate (TEOS), or the like, or combinations thereof.

The etch stop layer28may have a single-layer structure, or a multi-layered structure. The etch stop layer28may be formed by one or more deposition processes (such as chemical vapour deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof. Other suitable materials, and/or configuration, and/or method for forming the etch stop layer28are within the contemplated scope of disclosure.

The first mask layer31may include dielectric materials, such as silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, or the likes, or combinations thereof, but are not limited thereto, and may be formed by one or more deposition processes (such as chemical vapour deposition (CVD), atomic layer deposition (ALD), other suitable processes, or combinations thereof. The first photoresist layer32may include any suitable light-sensitive material and may be formed using spin coating or other suitable processes. One may decide to adopt a positive photoresist or a negative photoresist material according to practical needs. In some embodiments, the first photoresist layer32may have a single-layer structure. In other embodiments, the first photoresist layer32may have a multi-layered structure. As the first photoresist layer32is formed into a patterned first photoresist34(seeFIG.9), and an underlying element is patterned through the patterned photoresist34, such multi-layered structure helps controls profile (e.g. critical dimension) of opening(s) formed in the underlying element.

Referring toFIG.9, in some embodiments, the first photoresist layer32(seeFIG.8) is exposed through a photomask (not shown), and is then developed to form a patterned first photoresist34. The first mask layer31(seeFIG.8) is patterned through the patterned first photoresist34to form the patterned first mask33with an opening that exposes the first portion of the etch stop layer28. The patterned first mask33covers the second portion of the etch stop layer28. Other suitable materials, and/or configurations, and/or methods for forming the patterned first mask33are within the contemplated scope of disclosure.

After formation of the patterned first mask33, the patterned first photoresist34may be removed by any suitable methods, such as one or more stripping and/or ashing processes, but are not limited thereto.

Referring toFIG.1and the examples illustrated inFIGS.14and15, the method proceeds to step103, where a patterned second mask35is formed on the first portion of the etch stop layer28, and is in position corresponding to predetermined ones of the lines231at the first region41.FIG.14illustrates a cross-sectional view of the structure along a Y-Z plane at which the patterned second mask35is formed in accordance with some embodiments, andFIG.15illustrates another cross-sectional view of the structure along another Y-Z plane at which the patterned second mask35is absent in accordance with some embodiments.

Each of the lines231at the first region41may have a bottom segment232A and an upper segment. For each of the predetermined ones of the lines231, the upper segment includes a first part233A (seeFIG.14) that is covered by the patterned second mask35and a second part233B (seeFIG.15) that is not covered by the patterned second mask35. For each remaining line231, the upper segment includes a second part233B only (i.e., each remaining line231is not covered by the patterned second mask35). The first parts233A of the predetermined ones of the lines231may later serve as the connection portions233(seeFIG.24) formed in subsequent step. The connection portions233each contributes to a part of a corresponding via feature that interconnects different interconnect level structures (e.g., first and second interconnect level structures60,61as shown inFIG.24). As exemplarily shown inFIG.14, at the first region41, the two rightmost lines231serve as the predetermined ones of lines231. In other embodiments, positions of the predetermined ones of the lines231, and/or positions of the first parts233A, and/or positions of the second parts233B may be varied based on practical needs. The second parts233B of the lines231at the first region41are removed in subsequent step.

In some embodiments, step103may include sub-steps illustrated inFIGS.10to15in accordance with some embodiments.

Referring toFIG.10, a second mask layer35A and a second photoresist layer36A are sequentially formed over the patterned first mask33and the etch stop layer28. The second mask layer35A may fill the opening of the patterned first mask33. In some embodiments, possible processes and materials for forming the second mask layer35A are similar to those for the first mask layer31, and thus are not described for the sake of brevity. In some embodiments, possible processes and materials for forming the second photoresist layer36A are similar to those for the first photoresist layer32described with reference toFIG.8, and the details thereof are omitted for the sake of brevity. Other suitable materials, and/or configuration, and/or method for forming the second mask layer35A and the second photoresist layer36A are within the contemplated scope of disclosure.

Referring toFIGS.11to13, the second photoresist layer36A (seeFIG.10) is formed into a patterned second photoresist36. Specifically, the patterned second photoresist36includes a plurality of sections361that are in positions corresponding to the first parts233A of the predetermined ones of the lines231.FIG.11shows a top view of the structure after formation of the patterned second photoresist36.FIG.12is a cross-sectional view of the structure along a line A-A shown inFIG.11, showing the sections361of the patterned second photoresist36formed in positions corresponding to the first parts233A.FIG.13is a cross-sectional view of the structure along a line B-B shown inFIG.11, illustrating a place where the patterned second photoresist36is absent.

In some embodiments, formation of the patterned second photoresist36may be a photolithography process, but is not limited thereto. For instance, the second photoresist layer36A (seeFIG.10) may be exposed through a photomask (not shown), and then developed and formed into the patterned second photoresist36. In other embodiments, the second photoresist layer36A may be patterned into a patterned layer (not shown) with openings in positions corresponding to the sections361, and then a masking material may be filled in the openings, followed by removing the patterned layer so as to obtain masking sections which can also be represented by the sections361shown inFIG.12. . . . Other suitable methods for forming the patterned second photoresist36are within the contemplated scope of the present disclosure.

Referring toFIGS.14and15, the second mask layer35A (seeFIGS.12and13), is patterned into a patterned second mask35through the patterned second photoresist36. The patterned second photoresist36may serve as a cover mask in formation of the patterned second mask35. Similar to the patterned second photoresist36, the patterned second mask35includes a plurality of sections351that are in positions corresponding to the first parts233A of the predetermined ones of the lines231.

FIG.14illustrates the cross-sectional view of the structure subsequent to that shown inFIG.12(i.e., along the line A-A shown inFIG.11), showing the sections351of the patterned second mask35formed in positions corresponding to the first parts233A in accordance with some embodiments.FIG.15illustrates the cross-sectional view of the structure subsequent to that shown inFIG.13(i.e., along the line B-B shown inFIG.11), illustrating a place where the patterned second mask35is absent in accordance with some embodiments.

In some embodiments, during patterning of the second mask layer35A into the patterned second mask35, the etch stop layer28exposed from the patterned first mask33and the patterned second mask35is partially etched. As shown inFIGS.14and15, after step103, parts of the etch stop layer28that are not covered by the patterned first mask33and that are not covered by the patterned second mask35have a reduced height along the Z direction when comparing with the structure shown inFIGS.12and13.

The patterning process may be any suitable process, such as etching (e.g., dry etching, wet etching, anisotropic etching, other suitable techniques, or combinations thereof), but is not limited thereto. Other suitable methods for forming the patterned second mask35are within the contemplated scope of the present disclosure.

In certain embodiments, the sections351may each have a first width (CD1), and the first parts233A of the predetermined ones of the lines231underneath the sections351may each have a second width (CD2) smaller than the first width (CD1). As such, even in case that any one of the sections351is in slight misalignment with a corresponding one of the first parts233A, the section(s)351could still cover the corresponding first part(s)233A as much as possible (i.e., overlay window is improved), the first parts233A are less likely to be etched during removal of the second parts233B, and thus uniformity of a width of the connection portions233(seeFIG.25) formed form the first parts233A is improved (i.e., improved critical dimension uniformity). In some embodiments, portions of the etch stop layer28covered by the sections351may each have a width same as that of the sections351.

Please note that the number of the sections361and the number of the sections351formed are determined according to the amount of the connection portions233desired. In some embodiments, as shown inFIG.24, there are two connection portions233, and thus two sections361are formed as shown inFIGS.11and12, and two sections351are formed as shown inFIG.14. In other embodiments, there may be only one, or more than two of the connection portions233. In some embodiments, as shown inFIGS.11and12, the sections361are each formed in a pillar shape (with a circular cross-section along a X-Y plane), as well as the sections351(seeFIG.14), but are not limited thereto. In other embodiments, the sections361may each be formed into different shapes according to practical needs or final product specification, as well as the sections351. Other suitable configurations for the patterned second photoresist36and the patterned second mask35are within the contemplated scope of the present disclosure.

By completing steps102and103, the obtained patterned first and second masks33,35cooperatively form a patterned masking unit in positions corresponding to the lines231at the second region42, and the first parts233A of the predetermined ones of the lines231at the first region41. The remaining parts of the lines231that are not covered by the patterned mask unit. e.g., the second parts233B of the lines231at the first region41, are to be recessed in subsequent step.

Referring toFIG.1and the examples illustrated inFIGS.14to15and16to17, the method proceeds to step104, where the first layer23is patterned to form a patterned first layer23′.FIG.16illustrates the cross-sectional view of the structure subsequent to that shown inFIG.14in accordance with some embodiments.FIG.17illustrates the cross-sectional view of the structure subsequent to that shown inFIG.15in accordance with some embodiments.

Referring toFIGS.14and15, before a patterning process for forming first lines232and second lines234in step104, the first parts233A of the predetermined ones of the lines231are respectively covered by the sections351of the patterned second mask35; the second parts233B of the lines231at the first region41are exposed from the patterned second mask35; and the lines231at the second region42are covered by the patterned first mask33. Each of the first and second parts233A,233B may have a third height (H3). The lower segment232A of each of the lines231at the first region41for forming the first lines232may have a first height (H1). The line231may have a second height (H2), which is equivalent to a sum of the third height (H3) and the first height (H1). Each of the first, second, and third heights (H1, H2, H3) may be determined according to practical needs.

In step104, the first layer23is subjected to the patterning process to form the patterned first layer23′, such that the lines231are selectively recessed through the patterned first and second masks33,35. At the first region41, the second parts233B of the lines231are removed, while the first parts233A (seeFIGS.14and15) of the predetermined ones of the lines231are protected by the patterned second mask35and remain as the connection portions233(seeFIGS.16and17) having the third height (H3). In some embodiments, the third height (H3) may be greater than about 30 Å, and may range from about 30 Å to about 60 Å, from about 60 Å to about 90 Å, from about 90 Å to about 120 Å, or from about 120 Å to about 150 Å, but is not limited thereto. The lower segments232A of the lines231at the first region41remain and serve as the first lines232having the first height (H1). As such, the connection portions233, in combination with parts of predetermined first lines232(formed from the predetermined ones of the lines231) disposed underneath serve as a non-recessed portion having the second height (H2), while the remaining parts of the predetermined first lines232, and other first lines232(on which the connection portions233are not disposed thereon), serve as a recessed portion. At the second region42, the lines231(seeFIGS.14and15) are protected by the patterned first mask33, and thus are not recessed, such that the lines231serve as the second lines234(seeFIGS.12and13) having the second height (H2), or known as another non-recessed portion in the patterning process. The patterning process may be performed by any suitable etching process, such as dry etching, wet etching, anisotropic etching, other suitable techniques, or combinations thereof, but are not limited thereto. In some embodiments, a reagent used in the patterning process has different selectivity toward the materials of the lines231and the materials of the dielectric units29, such that the dielectric units29substantially intact.

By completing step104, the patterned first layer23′ including the relatively lower first lines232, the relatively higher second lines234, and the connection portions233respectively disposed on parts of predetermined ones of the first lines232is obtained. The first region41having such relatively lower first lines232may then serve as a relatively low capacitance region, while the second region42having such relatively higher second lines234may serve as a relatively low resistance region, which is conducive to achieving different product specification by varying configuration and/or height of first and second lines232,234. Each of the connection portions233and a corresponding one of the predetermined ones of the first lines232are integrally formed by patterning a corresponding one of the predetermined ones of lines231(seeFIGS.14to17). The first interconnect level structure60is obtained after obtaining the patterned first layer23′. The first interconnect level structure60includes the patterned first layer23′ serving as the metal portion, and the dielectric units29. Each of the first and second lines232,234are separated from each other by the dielectric units29, and the connection portions233are respectively disposed on parts of predetermined ones of the first lines232. The connection portions233are formed in a self-aligned manner along the Y direction and each uses two adjacent ones of the dielectric units29as the spacers.

In some embodiments, prior to patterning the first layer23, the etch stop layer28may be patterned first, such that portions thereof exposed from the patterned first and second masks33,35are removed so as to expose the lines231underneath. Specifically, as shown inFIGS.16and17, after step104, the patterned etch stop layer28A is obtained, which includes first sections281covering the connection portions233at the first region41, and second sections282covering the second lines234at the second region42. That is, parts of the first lines232, that are not covered by the connection portions233, are exposed from the patterned etch stop layer28A (which is made of a high-k material), so as to further lower capacitance of the first interconnect level structure60.

In some embodiments, after patterning the etch stop layer28and the first layer23in step104, the patterned first and second masks33,35are removed using any suitable methods.

Other suitable methods for forming the patterned first layer23′ and/or the first interconnect level structure60are within the contemplated scope of the present disclosure.

Referring toFIG.1and the example illustrated inFIGS.22and23, the method proceeds to step105, where a patterned dielectric layer51is formed over the patterned etch stop layer28A and the first interconnect level structure60.FIG.22illustrates the cross-sectional view of the structure, at which the connection portions233are formed in accordance with some embodiments.FIG.23illustrates the cross-sectional view of the structure, at which the connection portions233are absent in accordance with some embodiments.

In some embodiments, step105may include sub-steps illustrated inFIGS.18to23in accordance with some embodiments.

Referring toFIGS.18and19, a dielectric material layer including a lower dielectric511A and an upper dielectric512A is formed over the patterned etch stop layer28A and the first interconnect level structure60.FIG.18illustrates the cross-sectional view of the structure at which the connection portions233are formed subsequent to that shown inFIG.16.FIG.19illustrates the cross-sectional view of the structure at which the connection portions233are absent subsequent to that shown inFIG.17.

Possible materials and configuration for the dielectric layer may be similar to those of the ILD layer21, and thus are omitted for the sake of brevity. In some embodiments, the lower and upper dielectrics511A,512A may be made of the same material, and may be formed by one or more deposition processes (such as CVD, ALD, the likes, other suitable processes, or combinations thereof, but are not limited thereto). In some embodiments, the lower and upper dielectrics511A,512A may be sequentially formed over the patterned etch stop layer28A and the first interconnect level structure60. The lower dielectric511A fills spaces between sections281,282of patterned etch stop layer28A, and spaces between adjacent ones of dielectric units29and above the recessed portion.

Referring toFIGS.20and21, the upper dielectric512A is patterned to form a patterned upper dielectric512that has upper cavities621,641,661exposing portions of the lower dielectric511A.FIG.20illustrates the cross-sectional view of the structure at which the connection portions233are formed subsequent to that shown inFIG.18in accordance with some embodiments.FIG.21illustrates the cross-sectional view of the structure at which the connection portions233are absent subsequent to that shown inFIG.19in accordance with some embodiments. The patterning process may involve one or more etching processes (for example, but not limited to, a dry etching process, a wet etching process, or the likes, or combinations thereof) through a patterned mask (not shown).

Referring toFIGS.22and23, the lower dielectric511A is patterned through the upper cavities621,641,661to form a patterned lower dielectric511that has lower cavities631,651,671exposing portions of the first level interconnect structure60.FIG.22illustrates the cross-sectional view of the structure at which the connection portions233are formed subsequent to that shown inFIG.20in accordance with some embodiments.FIG.23illustrates the cross-sectional view of the structure at which the connection portions233are absent subsequent to that shown inFIG.21in accordance with some embodiments. The patterning process may involve one or more etching processes (for example, but not limited to, a dry etching process, a wet etching process, or the likes, or combinations thereof) through a patterned mask (not shown).

Exemplarily shown inFIGS.22and23, the lower cavities631respectively expose the connection portions233, the lower cavity651exposes the leftmost second line234, and the lower cavity671exposes the rightmost second line234. The lower cavities631are in spatial communication with the upper cavity621. The lower cavity651is in spatial communication with the upper cavity641. The lower cavity671is in spatial communication with the upper cavity661. Please note that amount and/or configuration of the upper and/or lower cavities621,641,661,631,651,671may be adjusted according to practical needs. Referring toFIG.22, there are two lower cavities631formed, which are formed to accommodate first vias63formed in subsequent step. Each of the lower cavities631extend from an upper surface of the patterned second dielectric51to a bottom surface of the patterned second dielectric51. The right lower cavity631aligns with the connection portion233underneath by exposing the entire upper surface of the connection portion233underneath. The left lower cavity631exposes a portion of an upper surface of the connection portion233underneath, and a portion of an upper surface of an adjacent one of the dielectric unit29, and such left lower cavity631is in slight misalignment with the connection portion233underneath, and in some embodiments, may be considered as an overlay error.

In some embodiments, in formation of the lower cavities631,651,671, the first sections281of the patterned etch stop layer28A may be patterned into first portions283so as to expose the connection portions233underneath, while the second sections282are patterned into second portions284, so as to expose the second lines234underneath.

Step105including the sub-steps shown inFIGS.18to23may be known as a dual damascene process. In other embodiments, step105may also be performed using two single damascene processes, or any other suitable processes to achieve the structure shown inFIGS.22and23.

Referring toFIG.1and the example illustrated inFIGS.24and25, the method proceeds to step106, where a second layer61is formed over the patterned dielectric layer51, so as to permit the second layer61to be connected to the metal portion of the first interconnect level structure60.FIG.24illustrates the cross-sectional view of the structure, at which the connection portions233are formed, subsequent to that shown inFIG.22in accordance with some embodiments.FIG.25illustrates the cross-sectional view of the structure, at which the connection portions233are absent, subsequent to that shown inFIG.23in accordance with some embodiments.

The second layer61includes a second electrically conductive material, which may be same as or different that of the first electrically conductive material, and thus details thereof may be omitted for the sake of brevity. The second layer61may be formed by performing one or more deposition processes, such as CVD, ALD, the likes, other suitable processes, or combinations thereof for depositing the second electrically conductive material, followed by one or more planarization processes (such as, CMP, and/or other suitable processes) may be used, but not limited thereto. Other materials and/or method for forming the second layer61are within the contemplated scope of the present disclosure.

The second layer61may serve as a metal portion of a second interconnect level structure68, and includes first vias63, a third line62connected to the first vias63, a second via65, a fourth line64connected to the second via65, a third via67, and a fifth line66connected to the third via67. The patterned dielectric layer51serves as a dielectric portion of the second interconnect level structure68.

Specifically, as exemplarily shown inFIGS.24and25, the first vias63are respectively connected to the first lines232of the first interconnect level structure60through the connection portions233, while the second and third vias65,67are directly connected to the second lines234, respectively. In some embodiments, the first via63and the second via65are simultaneously formed in the patterned dielectric layer51.

Referring toFIG.24, each of the first via63, and a corresponding one of the connection portions233together serves as a via feature70that interconnects the first line62with the predetermined ones of the first lines232. As shown inFIG.24, two via features70are formed. The right via feature70shows that the right first via63and the right connection portion233that are aligned to each other in a manner that a bottom surface of the right first via63fully covers an upper surface of the right connection portion233. A corresponding one of the first portions283is disposed around the right first via63. It is noted that for the left via feature70, a bottom surface of the left first via63is connected to a portion of the upper surface of the left connection portion233underneath, and a portion of an upper surface of a left adjacent one of the dielectric units29, or, in other words, the upper surface of the left connection portion233is connected to both the left first via63and a corresponding one of the first portions283of the patterned etch stop layer28A. That is, the left first via63is in slight misalignment with the left connection portion233underneath, and is shifted toward the left adjacent one of the dielectric units29(see the horizontal arrow shown inFIG.24, indicating the shift of the left first via63from its original position). In such overlay condition, a minimal distance between the overlaid first via63and an adjacent one of the first lines232is indicated by the inclined arrow shown inFIG.24. Since the first lines232are formed relatively lower, resulting in that the minimal distance is comparatively greater than the case that the first lines formed relatively higher (e.g., same as that of the second lines234).

The first vias63formed on the connection portions233have a height (H4) which is same as that of the second vias65,67formed on the second lines234. The connection portions233(with the height (H3)) compensate the reduced height of the first lines232(with the first height (H1)) compared to the second lines234(with the second height (H2), which is equivalent to a sum of H1 and H3). As such, patterning loading in formation of the lower cavities631is relatively easy as the lower cavities631merely extends through the patterned lower dielectric511with the height (H4), so that the first vias63formed in the lower cavities631are respectively connected to the first lines232through the connection portions233. In the case that the connection portions233are omitted, lower cavities (not shown) would have to be formed with a height equivalent to a sum of H4 and H3 so that first vias (not shown) can be connected to the first lines232, which may be considered as a relatively heavy patterning loading.

In some embodiments, additional elements such as barrier layers (not shown) and/or etch stop layers (not shown) may be included in the second interconnect level structure68based on practical needs.

FIG.26is similar toFIG.24, except that the dielectric units29are formed with different shapes. For the dielectric units29shown inFIG.24, each of which is in a substantially rectangular shape, while for those shown inFIG.26, each of which is in a substantially trapezium shape. Other suitable configurations for the dielectric units29are within the contemplated scope of the present disclosure.

FIG.28is a cross-sectional view of the structure taken along a line A′-A′ shown in FIG.FIG.27, andFIGS.29to33illustrate cross-sectional views of the structure subsequent to that shown inFIG.27.FIGS.27to33are respectively similar toFIGS.11,12,14,16,18,22and24, illustrating different stages of the method to acquire the semiconductor structure having an overlay condition of the right first via63(seeFIG.33) different from that shown inFIG.24. Please note that only the cross-sectional views at which the connection portions233are formed is shown, and the cross-sectional views at which the connection portions233are absent, are not described (e.g., the fifth line55and the third via67shown inFIG.25are not described in the followings).

Referring toFIGS.27and28, in this case, the right section361formed in step103is not completely in alignment with the corresponding predetermined one of the lines231underneath, but is shifted to the right, i.e., a projection of the right section361in the Z direction on the first interconnect level structure60may be shifted to cover a portion of the corresponding line231and a portion of a right adjacent ones of the dielectric units29, compared to the structure shown inFIG.12. As a result, the sections361shown inFIGS.27and28have a larger spaced-apart distance. Referring toFIG.29, the right section351formed in step103through the patterned second photoresist36accordingly has an overlay condition similar to that of the right section361and is also shifted to the right. Referring toFIG.30, in step104, after patterning through the etch stop layer28. the right predetermined one of the lines231is not entirely protected by the right section351due to the overlay, and has a small portion exposed from the patterned etch stop layer28. As such, the exposed right predetermined one of the lines231is also subjected to the patterning process in step104, resulting in a small recess formed in the right connection portion233, as shown inFIG.30. Referring toFIG.31, in step105, the lower dielectric511A formed over the patterned etch stop layer28A fills the small recess in the right connection portion233. Referring toFIG.32, in forming the lower cavity631on the right in the patterned dielectric layer51in step105, the dielectric material filling the small recess in the right connection portion233is also removed, leaving the recess empty. Referring toFIG.33, in step106for forming the second layer61, the second electrically conductive material is filled into the lower cavities631(seeFIG.32) and the recess in the right connection portion233, thereby forming the first vias63. The resultant right first via63has a tiger tooth portion632-aportion extending downwardly to be connected to a side surface of the right connection portion233.

In some embodiments, a photomask used in formation of the patterned second photoresist36(seeFIG.28) may also be used in formation of the lower cavities631,651(seeFIG.32). In such case, a patterned photoresist (not shown), which is formed on and exposes portions of the lower dielectric511A (see alsoFIG.20) and which is used for forming the lower cavities631,651, is made of a photoresist material that is opposite in type to the photoresist material for forming the patterned second photoresist36. That is, if the not-shown patterned photoresist is a positive photoresist, the patterned second photoresist36is a negative photoresist, and vice versa. As such, referring toFIGS.27and28, the patterned second photoresist36further includes a dummy section362located at the second region42, and referring toFIG.29, the patterned second mask35, which is formed through the patterned second photoresist36, similarly also includes a dummy section352located at the second region42. Such dummy sections352,362correspond in position to the second via65(seeFIG.33) and do not serve any specific function in terms of patterning the first layer23and will be removed together with the sections351,361, respectively.

FIGS.34to36illustrate a possible modification to the abovementioned method regarding formation of the patterned first and second masks33,35in steps102and103described with reference toFIGS.9to14. From the example illustrated inFIGS.9to14, the patterned first mask33is formed to define the first region41(including the lines231that are exposed and recessed to form the first lines232in subsequent step) and the second region42(including lines231that are covered and not-recessed to serve as the second lines234), and the patterned second mask35is formed to define and cover the first parts233A of the predetermined ones of the lines231at the first region41, so as to form the connection portions233on the predetermined ones of the first lines232. That is, two different masks are formed separately to facilitate patterning of the first layer23. In the example illustrated inFIGS.34to36, one single mask, namely a patterned mask unit37, is formed over the etch stop layer28prior to patterning the first layer23.FIG.34illustrates a top view of the patterned mask unit37(the etch stop layer28, and elements underneath are not shown in this figure).FIG.35is a cross-sectional view of the structure taken along line A″-A″ ofFIG.34, at which the first parts233A are present, in accordance with some embodiments.FIG.36illustrates another cross-sectional view of the structure taken along line B″-B″ ofFIG.34, at which the second parts233B are present, in accordance with some embodiments. The patterned mask unit37includes first sections373covering the first parts233A of the predetermined ones of the lines231at the first region41, and second sections374covering the second region42. That is, the first sections373of the patterned mask unit37are similar to the second patterned mask35illustrated inFIG.14, while the second sections374of the patterned mask unit37are similar to the patterned first mask33illustrated inFIGS.9to15. The second parts233B of the predetermined one of the lines231are exposed from the patterned mask unit37, so as to be removed in patterning of the first layer231performed in step104.

Each of the first and second sections373,374of the patterned mask unit37may include a hard mask layer371formed on the etch stop layer28, and a photoresist372formed on the hard mask layer371opposite to the etch stop layer28. Possible materials and processes for forming the hard mask layer371may be similar to those for forming the patterned first mask33described inFIG.9, and possible materials and processes for forming the photoresist372may be similar to those for forming the patterned first photoresist34described inFIG.9, and thus details thereof are omitted for the sake of brevity. By forming the patterned mask unit37, the structure shown inFIGS.34to36may be ready to proceed to step104for patterning the first layer23.

The embodiments of the present disclosure have the following advantageous features. The first and second lines at the first interconnect level structure60are formed with different height, so that the first interconnect level structure60achieves different capacitance and resistance. To compensate the reduced height of the first lines232compared to that of the second lines234, the connection portions233are formed on the predetermined ones of the first lines232, so that in formation of the lower cavities631for accommodating the first vias63that interconnect the metal portions of the first and second interconnect level structures60,68, the lower cavities631can be formed with less patterning loading. In addition, such connection portions233are formed in a self-aligned manner on account of the connection portions233are formed between the dielectric units29and the connection portions233are integrally formed with the first lines232. In the event of slight misalignment between one of the first vias63and a corresponding one of the connection portions233, a distance between such first via63and an adjacent one of the comparatively lower first lines232is greater compared with when the adjacent one of the first lines (not shown) is comparatively higher (i.e., not reduced in height), which results in the first interconnect level structure60having a larger TDDB window. Furthermore, a majority of the first region41is exposed from the patterned etch stop layer28A, which is conducive for further reducing the capacitance of the first interconnect level structure60.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes: forming a first layer on a base structure, the first layer being made of a first electrically conductive material, and having a first region and a second region displaced from the first region, each of the first region and the second region including a conductive line; patterning the first layer such that the conductive line at the first region is selectively recessed to have a recessed portion which has a first height and a non-recessed portion which has a second height that is greater than the first height and that is the same as a height of the conductive line at the second region; forming a patterned dielectric layer over the patterned first layer such that the non-recessed portion is exposed from the patterned dielectric layer; and forming a second layer over the patterned dielectric layer so as to permit the second layer to be connected to the non-recessed portion, the second layer being made of a second electrically conductive material.

In accordance with some embodiments of the present disclosure, patterning the first layer includes: forming a patterned masking unit to cover the conductive line at the second region and the non-recessed portion of the conductive line at the first region; and patterning the first layer through the patterned masking unit such that a portion of the conductive line at the first region, which is exposed from the patterned masking unit, is recessed to form the recessed portion.

In accordance with some embodiments of the present disclosure, the patterned masking unit includes a section covering the non-recessed portion, a width of the section being greater than a width of the non-recessed portion.

In accordance with some embodiments of the present disclosure, forming the patterned masking unit includes: forming a patterned first mask over the first layer to expose the first region; and forming a patterned second mask to cover the non-recessed portion of the conductive line at the first region, the patterned second mask being made of a material different from that of the patterned first mask.

In accordance with some embodiments of the present disclosure, forming the patterned second mask includes: forming a second mask layer over the patterned first mask and the first layer; forming a protection mask layer over the second mask layer, the protection mask layer being made of a material different from that of the second mask layer; patterning the protection mask layer to form a cover mask that corresponds in position to the non-recessed portion of the conductive line at the first region; and patterning the second mask layer (through the cover mask, such that the patterned second mask covers the non-recessed portion of the conductive line at the first region.

In accordance with some embodiments of the present disclosure, the patterned second mask includes a section covering the non-recessed portion, a width of the section being greater than a width of the non-recessed portion.

In accordance with some embodiments of the present disclosure, the method further includes forming an etch stop layer over the first layer, prior to patterning the first layer, the etch stop layer being patterned to expose a portion of the conductive line at the first region, in patterning the first layer, the portion of the conductive line at the first region is recessed to form the recessed portion, and in forming the patterned dielectric layer, the patterned dielectric layer being formed over the patterned etch stop layer and the patterned first layer.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes: forming a patterned first layer which is made of a first electrically conductive material, and which includes first lines, second lines, and a connection portion disposed on a part of one of the first lines, the first lines having a height lower than a height of the second lines; forming a first via which is connected to an upper surface of the connection portion, the first via having a height above the connection portion; and forming a second via which is connected to an upper surface of one of the second lines, the second via having a height that is the same as the height of the first via above the connection portion.

In accordance with some embodiments of the present disclosure, the method further includes, prior to forming the first via and the second via, forming a patterned dielectric layer over the patterned first layer.

In accordance with some embodiments of the present disclosure, the first via and the second via are simultaneously formed in the patterned dielectric layer, and are made of a second electrically conductive material.

In accordance with some embodiments of the present disclosure, the first via has a portion extending downwardly to be connected to a side surface of the connection portion.

In accordance with some embodiments of the present disclosure, the method further includes forming a patterned etch stop layer on the patterned first layer, the patterned etch stop layer having a first portion which is formed around the first via, and a second portion which is disposed on the second lines.

In accordance with some embodiments of the present disclosure, the upper surface of the connection portion is connected to both the first via and the first portion of the patterned etch stop layer.

In accordance with some embodiments of the present disclosure, the method further includes forming a plurality of dielectric units such that two adjacent ones of the first lines and the second lines are spaced apart from each other by a corresponding one of the dielectric units.

In accordance with some embodiments of the present disclosure, each of the dielectric units has an upper surface at a level which is the same as that of an upper surface of each of the second lines.

In accordance with some embodiments of the present disclosure, the method further includes, prior to forming the patterned dielectric layer, forming a patterned etch stop layer on the patterned first layer, the patterned etch stop layer having a first portion which is formed around the first via, and a second portion which is disposed on the second lines, such that after forming the patterned dielectric layer, the first lines are in direct contact with the patterned dielectric layer.

In accordance with some embodiments of the present disclosure, each of the dielectric units includes an air gap therein.

In accordance with some embodiments of the present disclosure, a semiconductor structure includes: a base structure; a first interconnect level structure; and a second interconnect level structure. The first interconnect level structure is formed over the base structure, and includes a first region and a second region. The first region includes a plurality of first lines, and a connection portion formed on a part of one of the first lines. The first lines are each elongated in an X direction, and spaced apart from each other in a Y direction transverse to the X direction. The first lines have a first height. The second region includes a plurality of second lines that have a second height which is greater than the first height. An upper surface of each of the second lines is at a level same as an upper surface of the connection portion. The second lines are elongated in the X direction, and spaced apart from each other in the Y direction. The second interconnect level structure is formed on the first interconnect level structure, and includes a third line elongated in the Y direction, and a first via connected to an upper surface of the connection portion so as to permit the one of the first lines to be connected to the third line through the first via and the connection portion.

In accordance with some embodiments of the present disclosure, the second interconnect level structure further includes a patterned dielectric layer formed between the first interconnect level structure and the third line of the second interconnect level structure. The first via is formed to extend through the patterned dielectric layer so as to connect the third line to the connection portion.

In accordance with some embodiments of the present disclosure, the semiconductor structure further includes a patterned etch stop layer disposed between the first interconnect level structure and the patterned dielectric layer. The patterned etch stop layer includes a first portion which is formed around the first via, and a second portion disposed on the second lines.