Systems and methods for temperature-based performance optimization of memory devices

In accordance with embodiments of the present disclosure, a memory system may include one or more memory modules and a memory controller communicatively coupled to one or more memory modules. The memory controller may be configured to determine a temperature associated with the memory system and determine if the temperature is below a minimum threshold temperature, wherein the minimum threshold temperature is a predetermined margin greater than a critical temperature below which one or more timing parameters of the memory system are of greater durations than they are when the temperature is above the critical temperature, and further wherein the predetermined margin is zero or greater. The memory controller may also be configured to initiate one or more remedial actions to increase the temperature above the minimum threshold temperature if the temperature is below the minimum threshold temperature.

TECHNICAL FIELD

The present disclosure relates in general to information handling systems, and more particularly to systems and methods for temperature-based performance optimization of memory devices.

BACKGROUND

Information handling systems often use memories to store data, either temporarily in volatile memory or in a quasi-permanent basis in non-volatile memory. A type of memory often used is dynamic random access memory (DRAM). DRAM includes a number of memory cells each configured to store one bit of data. One crucial timing parameter of a DRAM is the write recovery parameter, which defines a minimum time required to ensure that a DRAM cell has been written to its full charge. As DRAM technology has scaled to smaller and smaller physical sizes, suppliers of DRAMs have indicated a desire to increase the write recovery parameters of their DRAMs, and have pursued relaxation of the write recovery parameter with the Joint Electron Device Engineering Council (JEDEC), the computing industry's memory standards-setting organization. Without this timing relaxation, the DRAM bit error rate due to write failures may become so high as to make DRAM chips non-manufacturable at an acceptable yield. Such increases in the write recovery parameters and other timing parameters of DRAM may significantly reduce bandwidth of memory devices.

In addition, in many DRAMs, the write time of a memory cell may increase as the ambient temperature of the memory cell falls, further degrading memory performance as temperature decreases. In fact, many in the relevant industry have proposed that for future memory implementations, DRAM timing parameters such as the write recovery parameter be a function of operating temperature. For example, in future DRAM devices, a write recovery parameter may have a value of 60 nanoseconds for temperatures below 45 degrees Celsius and a value of 30 nanoseconds for temperatures above 45 degrees Celsius. Such DRAM devices may also be enabled such that a memory controller of a DRAM device may be notified of such changes in temperature and modify timing parameters in accordance with such temperature.

Because an increase in write recovery time increases overall DRAM write latency and read-after-write latency to the same DRAM rank, maximum memory bandwidth may decrease due to a drop in temperature. Thus, with the industry-proposed changes to move towards temperature-based timing parameters, when a temperature falls below a certain level, write latency may triple and write bandwidth would fall by up to two-thirds when writes are issued to the same DRAM rank and bank. Another disadvantage is that variable memory latency which varies with temperature may create undesirable effects in application programs which are sensitive to timing variation, either with the same rank or different ranks.

SUMMARY

In accordance with the teachings of the present disclosure, the disadvantages and problems associated with optimizing memory performance in an information handling system may be reduced or eliminated.

In accordance with embodiments of the present disclosure, an information handling system may include a processor and a memory system communicatively coupled to the processor. The memory system may be configured to, alone or in concert with the processor determine a temperature associated with the memory system and determine if the temperature is below a minimum threshold temperature, wherein the minimum threshold temperature is a predetermined margin greater than a critical temperature below which one or more timing parameters of the memory system are of greater durations than they are when the temperature is above the critical temperature, and further wherein the predetermined margin is zero or greater. The memory system may further be configured to initiate one or more remedial actions to increase the temperature above the minimum threshold temperature if the temperature is below the minimum threshold temperature.

In accordance with these and other embodiments of the present disclosure, a method may include determining a temperature associated with a memory system. The method may also include determining if the temperature is below a minimum threshold temperature, wherein the minimum threshold temperature is a predetermined margin greater than a critical temperature below which one or more timing parameters of the memory system are of greater durations than they are when the temperature is above the critical temperature, and further wherein the predetermined margin is zero or greater. The method may additionally include initiating one or more remedial actions to increase the temperature above the minimum threshold temperature if the temperature is below the minimum threshold temperature.

In accordance with these and other embodiments of the present disclosure, a memory system may include one or more memory modules and a memory controller communicatively coupled to one or more memory modules. The memory controller may be configured to determine a temperature associated with the memory system and determine if the temperature is below a minimum threshold temperature, wherein the minimum threshold temperature is a predetermined margin greater than a critical temperature below which one or more timing parameters of the memory system are of greater durations than they are when the temperature is above the critical temperature, and further wherein the predetermined margin is zero or greater. The memory controller may also be configured to initiate one or more remedial actions to increase the temperature above the minimum threshold temperature if the temperature is below the minimum threshold temperature.

DETAILED DESCRIPTION

Preferred embodiments and their advantages are best understood by reference toFIGS. 1 through 3, wherein like numbers are used to indicate like and corresponding parts.

FIG. 1illustrates a block diagram of an example information handling system102in accordance with certain embodiments of the present disclosure. In certain embodiments, information handling system102may comprise a computer chassis or enclosure (e.g., a server chassis holding one or more server blades). In other embodiments, information handling system102may be a personal computer (e.g., a desktop computer or a portable computer). As depicted inFIG. 1, information handling system102may include a processor103, a memory system104communicatively coupled to processor103, a storage medium106communicatively coupled to processor103, and a cooling system122communicatively coupled to processor103.

Memory system104may be communicatively coupled to processor103and may comprise any system, device, or apparatus operable to retain program instructions or data for a period of time (e.g., computer-readable media). Memory system104may comprise random access memory (RAM), electrically erasable programmable read-only memory (EEPROM), a PCMCIA card, flash memory, magnetic storage, opto-magnetic storage, or any suitable selection and/or array of volatile or non-volatile memory that retains data after power to information handling system102is turned off. In particular embodiments, memory system104may comprise dynamic random access memory (DRAM).

As shown inFIG. 1, memory system104may include memory controller108, one or more memory modules116a-116ncommunicatively coupled to memory controller108, status registers112communicatively coupled to memory controller108, a temperature sensor124, and a self-heating system128. Memory controller108may be any system, device, or apparatus configured to manage and/or control memory system104. For example, memory controller108may be configured to read data from and/or write data to memory modules116comprising memory system104. Additionally or alternatively, memory controller108may be configured to refresh memory modules116and/or memory chips110thereof in embodiments in which memory system104comprises DRAM. Although memory controller108is shown inFIG. 1as an integral component of memory system104, memory controller108may be separate from memory system104and/or may be an integral portion of another component of information handling system102(e.g., memory controller108may be integrated into processor103).

Each memory module116may include any system, device or apparatus configured to retain program instructions and/or data for a period of time (e.g., computer-readable media). A memory module116may comprise a dual in-line package (DIP) memory, a dual-inline memory module (DIMM), a Single In-line Pin Package (SIPP) memory, a Single Inline Memory Module (SIMM), a Ball Grid Array (BGA), or any other suitable memory module.

As depicted inFIG. 1, each memory module116may include one or more ranks118a-118m. Each memory rank118within a memory module116may be a block or area of data created using some or all of the memory capacity of the memory module116. In some embodiments, each rank118may be a rank as such term in defined by the JEDEC Standard for memory devices.

As shown inFIG. 1, each rank118may include a plurality of memory chips110. Each memory chip110may include a packaged integrated circuit configured to comprise a plurality of memory cells110for storing data. In some embodiments, a memory chip110may include dynamic random access memory (DRAM). Selected components of a memory chip110are illustrated in greater detail inFIG. 2below.

As shown inFIG. 1, a memory module116may include a temperature sensor126and a self-heating system130. Temperature sensor126may comprise any system, device, or apparatus (e.g., a thermometer, thermistor, etc.) configured to communicate a signal to memory controller108and/or control logic internal to the memory module116indicative of a temperature within memory module116. In some embodiments, such temperature sensors126may already be required within a memory module116to provide thermal feedback to memory controller108or processor103to allow for closed-loop thermal management of memory module116and/or enable other thermal or power management features of a memory module116.

Self-heating system130may comprise any system, device, or apparatus for generating heat and communicating such generated heat to components throughout a memory module116(e.g., to memory chips110integral to such memory module116). For example, self-heating element130may comprise programmable heating elements (e.g., electrically resistive loads) under the control of memory controller108, processor103, logic internal to memory module116, or another information handling resource of information handling system102. In some embodiments, such control may be implemented as a closed-loop thermal control based on active monitoring of temperature sensor126. In other embodiments, such control may be implemented as an open-loop thermal control (e.g., by passive monitoring of a memory module116and/or temperature of air ambient to such memory module116). To communicate heat generated by such heating element to memory chips110, self-heating system130may include one or more heat pipes, heat spreaders, or other thermally-conductive components coupling memory chips110to such heating element.

Status registers112may include one or more configuration variables and/or parameters associated with memory system104. When reading, writing, refreshing, and/or performing other operations associated with memory system104, memory controller108may carry out such operations based at least in part on configuration parameters and/or variables stored in status registers112. In some embodiments, status registers112may include registers similar to mode registers220.

Temperature sensor124may comprise any system, device, or apparatus (e.g., a thermometer, thermistor, etc.) configured to communicate a signal to memory controller108indicative of a temperature within memory system104. In some embodiments, a temperature sensor124may detect a temperature associated with memory system104at large. In these and other embodiments, memory system104may comprise a plurality of temperature sensors124, wherein each temperature sensor124may detect a temperature near a particular component and/or location within memory system104. For example, where memory system104comprises memory modules116comprise DIMMs, one or more DIMMs may be monitored by a respective temperature sensor124.

Self-heating system128may comprise any system, device, or apparatus for generating heat and communicating such generated heat to components (e.g., memory modules116) of memory system104. For example, self-heating system128may have one or more programmable heating elements (e.g., electrically resistive loads) under the control of memory controller108, processor103, or another information handling resource of information handling system102. In some embodiments, such control may be implemented as a closed-loop thermal control based on active monitoring of temperature sensor124. In other embodiments, such control may be implemented as an open-loop thermal control (e.g., by passive monitoring of memory system104and/or temperature of air ambient to memory system104). To communicate heat generated by such heating element to memory modules116, self-heating system128may include one or more heat pipes, heat spreaders, or other thermally-conductive components coupling memory modules116to such heating element.

Storage medium106may be communicatively coupled to processor104. Storage medium106may include any system, device, or apparatus operable to store information processed by processor103. Storage medium106may include, for example, network attached storage, one or more direct access storage devices (e.g., hard disk drives), and/or one or more sequential access storage devices (e.g., tape drives). As shown inFIG. 1, storage medium106may have stored thereon an operating system (OS)114. OS114may be any program of executable instructions, or aggregation of programs of executable instructions, configured to manage and/or control the allocation and usage of hardware resources such as memory, CPU time, disk space, and input and output devices, and provide an interface between such hardware resources and application programs hosted by OS114. Active portions of OS114may be transferred to memory104for execution by processor103.

Cooling system122may include any mechanical or electro-mechanical system, apparatus, or device operable to move coolant (e.g., air, other gasses, liquids) throughout a chassis or enclosure of information handling system102. In some embodiments, cooling system122may comprise a fan (e.g., a rotating arrangement of vanes or blades which act on a gaseous coolant such as air). In other embodiments, cooling system122may comprise a blower (e.g., a centrifugal fan that employs rotating impellers to accelerate gaseous cooling received at its intake and change the direction of the airflow). In operation, in the case of a cooling system122including an air mover (e.g., fan or blower), the air mover may cool information handling resources of information handling system102by drawing cool air into an enclosure housing the information handling resources from the outside of the housing, expel warm air from inside the enclosure to the outside of such enclosure, and/or move air across one or more heatsinks (not explicitly shown) internal to the enclosure to cool one or more information handling resources. Although not explicitly depicted inFIG. 1, cooling system122may also include one or more heating elements in air flow paths which may be enabled to pre-heat air before it is delivered to an information handling resource (e.g., memory system104or a portion thereof) in order to provide heat to such information handling resource. In these and other embodiments, cooling system122may include one or more air deflection structures, such as, for example, static or dynamically adjustable air ducts and/or plenums, to steer air flow towards or away from particular information handling resources as desired. Parameters for controlling air flow (e.g., air mover speed, positions of air deflection structures, etc.) and/or heat of air (e.g., heating elements within the air flow) may be managed and controlled by a thermal management system of cooling system122.

In other embodiments, cooling system122may comprise mechanisms other than a blower for moving coolant, including liquid pumps, jets, and/or free convection enclosures. In these and other embodiments, rotating and other components for moving coolant by cooling system122may be driven by a motor or other mechanical device.

In addition to processor103, memory104, storage medium106, and cooling system122, information handling system102may include one or more other information handling resources.

FIG. 2illustrates a block diagram of an example memory chip in accordance with embodiments of the present disclosure. A memory chip110may include mode registers220and one or more memory banks210. Each memory bank210may be a logical unit of storage within memory chip110.

Mode registers220may include one or more configuration variables and/or parameters associated with memory chip110. When reading, writing, refreshing, and/or performing other operations associated with memory system104, a memory module116may carry out such operations based at least in part on configuration parameters and/or variables stored in mode registers220. In some embodiments, mode registers220may be defined by a JEDEC standard for memory devices.

As shown inFIG. 2, a memory chip110may include a temperature sensor226and a self-heating element230. Temperature sensor226may comprise any system, device, or apparatus (e.g., a thermometer, thermistor, etc.) configured to communicate a signal to memory controller108and/or control logic internal to the memory chip110indicative of a temperature within the memory chip110. In some embodiments, such temperature sensors226may already be required within a memory chip110to implement temperature compensated self-refresh rate features and/or other features of a memory chip110.

Self-heating element130may comprise any system, device, or apparatus for generating heat and communicating such generated heat throughout a memory chip110(e.g., throughout an integrated circuit die comprising such memory chip110). For example, self-heating element230may comprise a programmable heating elements (e.g., electrically resistive loads) under the control of memory controller108, processor103, logic internal to memory module116, logic internal to memory chip110, or another information handling resource of information handling system102. In some embodiments, such control may be implemented as a closed-loop thermal control based on active monitoring of temperature sensor226. In some embodiments, mode registers220may be employed to store parameters such that memory controller108, processor103, logic internal to memory module116, logic internal to memory chip110, or another information handling resource of information handling system102may control self-heating elements230on a memory chip110-by-memory chip110basis.

In operation, one or more of cooling system122and memory system104is configured to regulate a temperature associated with memory system104(e.g., one or more temperatures detected by one or more of temperature sensor124, temperature sensors126, and/or temperature sensors226) in order to optimize timing parameters of memory system104. For example, as a temperature associated with memory system104cools down towards a temperature threshold whereby memory system104would switch to lower-performance memory timing parameters (e.g., an increased write recovery parameter for all or a portion of memory system104), one or more of cooling system122and memory system104would take one or more remedial actions to maintain the temperature associated with memory system104to remain above the temperature threshold. Such remedial actions may include, without limitation:reducing air flow from cooling system122to all or a part of memory system104(e.g., reducing air flow to memory modules116having higher temperatures);increasing air temperature of air flow of cooling system122to all or a part of memory system104(e.g., activating heating elements of cooling system122within the air flow path of memory modules116having higher temperatures);activating self-heating system128to maintain or increase a temperature associated with memory system104(e.g., a temperature sensed by temperature sensor124);activating a self-heating system130of a memory module116to maintain or increase a temperature associated with memory system104(e.g., a temperature sensed by temperature sensor126of such memory module116); andactivating a self-heating element230of a memory chip110to maintain or increase a temperature associated with memory system104(e.g., a temperature sensed by temperature sensor226of such memory chip110); andissuance within a memory chip110of an internal non-destructive memory cycle or “dummy cycle” to consume power and thus increase or maintain temperature within the memory chip110.

In the case of issuance of an internal non-destructive memory cycle, a memory chip110may execute such a memory cycle when it is not activated to maintain or increase a temperature. Such cycle may include an activate, precharge, read, refresh, or any other non-destructive memory cycle that will complete before the memory chip110must be ready to accept a new memory command. For example, so as to always be ready to accept memory commands from processor103, the dummy cycles would be issued to internal ranks118or banks210coherently with “real” memory cycles in order to ensure that the dummy cycles do not collude with the real cycles.

In some embodiments, a memory chip110may maintain a suite of dummy command cycles each with a known activation energy through table, characterization, measurement or other means. The memory module116may then choose the optimal dummy command cycle that best provides the optimal amount of power (heat) dissipation. For example, when a temperature associated with a memory module116is near the lower bound of a temperature threshold, dummy cycles with higher power may be utilized, whereas when the temperature is higher, dummy cycles with less power dissipation would be chosen.

In these and other embodiments, a memory module116may also queue up of a range of “dummy” command cycles to multiple ranks118, banks210, sub-banks, etc. so that when an opportunistic dummy command slot is available, one or more cycles may be run in parallel.

In these and other embodiments, a memory module116may also make available to processor103readings from temperature sensor126and/or temperature sensor226(e.g., via the Multi-Purpose Register (MPR) read method, an out of band method such as System Management Bus or Inter-Integrated Circuit, or an in-band double data rate command response method), and thus also report (e.g., to a management tool of operating system114) any number of statistics on how often self-heating system128, self-heating system130, and/or self-heating elements230have been enabled within a certain period of time. These statistics could be used advantageously in a higher-level thermal management algorithm to maximize overall system performance and power, by adjusting and/or combining the amount of memory module116self-heating with other heating options described below.

In some embodiments, a memory module may suspend self-heating while in specific low-power power management modes such as self-refresh, or clock enable (CKE) power down. Various tradeoffs between power and performance may be made available to processor103, memory controller108, or another component of information handling system102by employing programmable MPRs.

In some embodiments, a memory module116may self-throttle the self-heating command cycles and/or resistive load elements to ensure that the operating currents of the various memory modules116do not exceed system current limits.

FIG. 3illustrates a flow chart of an example method300for temperature-based optimization for memory devices, in accordance with embodiments of the present disclosure. According to some embodiments, method300may begin at step302. As noted above, teachings of the present disclosure may be implemented in a variety of configurations of information handling system102. As such, the preferred initialization point for method300and the order of the steps comprising method300may depend on the implementation chosen.

At step302, one or more temperature sensors (e.g., temperature sensors124,126, and/or226) may determine a temperature associated with memory system104and communicate such temperature to a processing device (e.g., memory controller108, processor103, logic internal to a memory module116, logic internal to a memory chip110). At step304, the processing device may determine if whether the temperature is above a maximum threshold temperature. Such maximum threshold temperature may define a maximum temperature at which memory system104or a component thereof may operate at a desired or optimum level of performance. If the measured temperature exceeds the maximum threshold temperature, method300may proceed to step312. Otherwise, method300may proceed to step306.

At step306, the processing device may determine whether the measured temperature is below a minimum threshold temperature. Such minimum threshold temperature may define a minimum temperature (or such minimum temperature plus a “safety” margin above such minimum temperature) for which timing parameters (e.g., a write recovery parameter) of memory system104or its components may have optimum values, wherein at temperatures below the minimum threshold temperature, such timing parameters may be suboptimal. If the measured temperature is above the minimum threshold temperature, method300may proceed to step308. Otherwise, method300may proceed to step310.

At step308, in response to determining that the measured temperature is above the minimum threshold temperature, memory system104, alone or in concert with the processing device, may utilize moderate remedial actions in order to maintain the temperature associated with memory system104above the minimum threshold temperature. For example, such remedial action may include issuing non-destructive dummy commands to ranks118and/or banks210of memory system104. After completion of step308, method300may proceed again to step302.

At step310, in response to determining that the measured temperature is below the minimum threshold temperature, memory system104, alone or in concert with the processing device, may utilize aggressive remedial actions in order to raise the temperature associated with memory system104above the minimum threshold temperature. For example, such remedial action may include activating self-heating system128, self-heating system130, and/or self-heating elements230. After completion of step308, method300may proceed again to step302.

At step312, in response to determining that the measured temperature is above the maximum threshold temperature, remedial action may be taken to reduce the temperature associated with memory system104. For example, such remedial action may include increasing airflow or cooling via cooling system122and/or disabling or reducing the heat generated by heating systems128,130, and230. After completion of step308, method300may proceed again to step302.

AlthoughFIG. 3discloses a particular number of steps to be taken with respect to method300, method300may be executed with greater or fewer steps than those depicted inFIG. 3. In addition, althoughFIG. 3discloses a certain order of steps to be taken with respect to method300, the steps comprising method300may be completed in any suitable order.

Method300may be implemented using processor103, memory controller108, and/or any other system operable to implement method300. In certain embodiments, method300may be implemented partially or fully in software and/or firmware embodied in computer-readable media.

Thus, consistent with the methods and systems disclosed herein, a memory system may be configured to, alone or in concert with a processor to which it is coupled, determine a temperature associated with the memory system and determine if the temperature is below a minimum threshold temperature, wherein the minimum threshold temperature is a predetermined margin greater than a critical temperature below which one or more timing parameters of the memory system are of greater durations than they are when the temperature is above the critical temperature, and further wherein the predetermined margin is zero or greater. If the temperature is below the minimum threshold temperature, memory system104may alone or in concert with the processor, initiate one or more remedial actions to increase the temperature above the minimum threshold temperature.

In addition, in some embodiments, the memory system may be further configured to, alone or in combination with the processor, determine if the temperature is above the minimum threshold temperature and below a maximum threshold temperature, and if the temperature is above the minimum threshold temperature and below a maximum threshold temperature, initiate one or more remedial actions to maintain the temperature above the minimum threshold temperature.