Vertical field-effect transistor having a high breakdown voltage and a small on-resistance

A vertical MOSFET includes a base region formed on the surface of a drain region, a source region provided in the base region, a first semiconductor region provided on the surface of the drain region between portions of the base region, the first semiconductor region having the same conductivity type as the drain region and an impurity concentration higher than that of the drain region, a second semiconductor region of the opposite conductivity type provided in the first semiconductor region, a gate electrode provided on the base region surrounded by the source region and the first semiconductor region, and an insulating film provided on the second semiconductor region.

BACKGROUND OF THE INVENTION 
1 Field of the Invention 
The present invention relates to a field effect transistor, and more 
particularly, to improvements of breakdown voltage and on-resistance of a 
vertical field effect transistor. 
2 Description of the Related Art 
A conventional vertical field effect transistor is disclosed in Japanese 
Patent Laid-Open No. 53-135284 and U.S. Pat. No. 4,593,302 and has an 
n.sup.- -type active layer on an n.sup.+ -type substrate serving as a 
drain, a p-type base region formed in a surface area of the n.sup.- -type 
layer, an n.sup.+ -type source region formed in the p-type base region, a 
gate electrode positioned, through an insulating film, on the p-type base 
region between the n.sup.+ -type source region and the n.sup.- -type layer 
to extend over the n.sup.- -type layer, and an n.sup.+ -type layer formed 
in the surface area of the n.sup.- -type layer adjacent to the p-type base 
region. In such vertical field effect transistor, the electrons flowing 
from the n.sup.+ -type source region to the n.sup.+ -type drain region 
flow through a channel region induced at a surface of the p-type base 
region under the gate electrode. In this electron flow-path, since the 
n.sup.+ -type layer is formed on the surface of the n.sup.- -type layer 
adjacent to the p-type base region, the on-resistance of this field effect 
transistor decreases. With the n.sup.+ -type layer being provided on the 
surface of the n.sup.- -type in contact with the p-type base region, 
however, the breakdown voltage between the drain region and the base 
region decreases. 
SUMMARY OF THE INVENTION 
It is, therefore, an object of the present invention to provide a vertical 
field effect transistor which is so constructed as to decrease the 
on-resistance without lowering the breakdown voltage. 
The field effect transistor in accordance with the present invention 
includes a first semiconductor region formed on a main surface of a 
semiconductor substrate of one conductivity type except for a 
predetermined portion of the substrate, the first semiconductor region 
being of the other conductivity type, a second semiconductor region formed 
on the main surface of the semiconductor substrate uncovered by the first 
semiconductor region, the second semiconductor region having the one 
conductivity type with an impurity concentration higher than the 
semiconductor substrate and being in contact with first semiconductor 
region, a third semiconductor region of the other conductivity type formed 
in the second semiconductor region, a fourth semiconductor region formed 
on a surface of the first semiconductor region, the fourth semiconductor 
region being separated from the second semiconductor region and being of 
the one conductivity type, a gate electrode formed on the first 
semiconductor region between the second semiconductor region and the 
fourth semiconductor region, an insulating film provided on the second 
semiconductor region and on the third semiconductor region, a first 
electrode electrically connected to the fourth semiconductor region and a 
second electrode electrically connected to the other main surface of the 
semiconductor substrate. 
Since the second semiconductor region having the same conductivity type as 
the semiconductor substrate is formed on the main surface of the 
semiconductor substrate to have an impurity concentration higher than that 
of the semiconductor substrate, the field effect transistor according to 
the present invention has a small on-resistance. Furthermore, since the 
third semiconductor region of the other conductivity type is formed in the 
second semiconductor region together with the insulating film covering the 
second and third semiconductor regions, the third semiconductor region is 
under the floating condition to act just like a field ring to relax the 
concentration of electric field, resulting in keeping a high breakdown 
voltage. According to the present invention, therefore, there is obtained 
a field effect transistor having a decreased on-resistance with high 
breakdown voltage. 
The third semiconductor region is preferably shallower than the second 
semiconductor region, because, if the third semiconductor region becomes 
deeper than the second semiconductor region, the current path becomes 
narrow to increase the on-resistance.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 is a sectional view of a preferred embodiment in which the present 
invention is adapted to an n-channel insulated-gate vertical field effect 
transistor. On an n.sup.+ -type Sb doped silicon substrate 1 having an 
impurity concentration of 3.0 .times. 10.sup.18 atoms/cm.sup.3, is formed 
an n.sup.- -type epitaxially grown layer 2 having an impurity 
concentration of 6.4 .times. 10.sup.14 atoms/cm.sup.3 and a film thickness 
of 30 .mu.m. A p.sup.- -type base region 3 having a depth of 4 .mu.m and 
an impurity concentration of 2.5 .times. 10.sup.17 atoms/cm.sup.3 is 
provided in the surface region of the n.sup.- -type epitaxially grown 
layer 2. An n.sup.+-type source region 4 having a depth of 1.0 .mu.m and 
an impurity concentration of 2.0 .times. 10.sup.20 atoms/ cm.sup.3 is 
formed in a central surface portion of the p.sup.- -type base region 3. At 
a central portion of the n.sup.+ -type source region 4, is provided a 
p.sup.+ -type region 7 having an impurity concentration of 2.0 .times. 
10.sup.18 atoms/cm.sup.3 from the surface thereof to reach the p.sup.- 
-type base region 3. At a surface portion of the n.sup.- -type epitaxially 
grown layer 2 which is adjacent to the p.sup.- -type base region 3, is 
provided an n.sup.+ -type region 5 having a depth of 2.0 .mu.m and an 
impurity concentration of 1.0 .times. 10.sup.15 atoms/cm.sup.3, and, at 
the central portion of the n.sup.+ -type region 5, is provided a p.sup.+ 
-type region 8 having an impurity concentration of 2.0 .times. 10.sup.18 
atoms/cm.sup.3 and a depth of 1.5 .mu.m. A gate electrode 6 of 
polycrystalline silicon is formed on the p.sup.- -type base region 3 
between the n.sup.+ -type source region 4 and the n.sup.+ -type region 5 
through a gate insulating film. An, oxide film 29 having a thickness of 
6000 .ANG. is formed on the n.sup.+ -type region 5 and on the p.sup.+ 
-type region 8 between the gate electrodes 6. A source electrode 10 is 
provided being commonly connected to the n.sup.+ -type source region 4 and 
to the p.sup.+ -type region 3, and a drain electrode 11 is provided on the 
back surface of the n.sup.+ -type silicon substrate 1. 
A method for manufacturing the vertical field effect transistor will now be 
described in conjunction with FIGS. 2(a) to 2(d). 
As shown in FIG. 2(a), first, an n.sup.- -type epitaxial layer 2 is grown 
on the n-type semiconductor substrate 1, and p-type impurities are 
implanted by using an oxide film 9 as a mask to form a p.sup.- -type 
region 3. Next, using the same mask, n-type impurities are implanted at a 
high concentration in order to form an n.sup.+ -type source region 4. 
Next, as shown in FIG. 2(b), n-type impurities are implanted at a high 
concentration in the surface layer of the drain region 5 by using another 
oxide film 21 as a mask. 
Referring to FIG. 2(c), p-type impurities are implanted at a high 
concentration using a polycrystalline silicon layer 6 as a mask in order 
to form p.sup.+ -type layers 7 and 8. 
Then, as shown in FIG. 2(d), ions are implanted and diffused to a suitable 
depth, followed by forming an oxide film 29 on the drain region, forming a 
source electrode 10 thereon, and forming a drain electrode 11 on the back 
surface of the substrate 1. 
FIG. 3 shows a flow of electrons and the expansion of the depletion layer, 
when the insulated gate field effect transistor of this embodiment is in 
operation. Electrons flowing out from the n.sup.+ -type source region 4 
pass through the channel 12 and the surface layer of the drain region 5 to 
arrive at the drain electrode 11. 
The drain region 5 is formed by implanting impurity ions at a high 
concentration after the p.sup.- -type region 3 has been formed. A 
relationship of dosage is p.sup.+ -type layer 8 (5 .times. 10.sup.14 
/cm.sup.2 to 5 .times. 10.sup.16 /cm.sup.2) &gt; drain region 5 (2 .times. 
10.sup.11 /cm.sup.2 to 5 .times. 10.sup.14 /cm.sup.2) &gt; p.sup.- -type 
region 3. Due to the drive-in diffusion, therefore, the drain region 5 
diffuses in the lateral direction toward the p.sup.- -type region 3 to 
shorten the channel 12. Moreover, since the surface of the drain region 5 
has a high concentration, the on-resistance decreases. 
The p.sup.+ -type layer 8 in the drain region is under the floated 
condition, the depletion layer is expanded like the field ring, and 
concentration of electric field is relaxed under the gate electrode 6. 
Therefore, the breakdown voltage is prevented from decreasing. 
Though the foregoing embodiment has dealt with the n-channel field effect 
transistor, the same effects are also obtained even with the p-channel 
field-effect transistor in which the types of conduction are reversed.