Spark ignition systems for internal combustion engines

An internal combustion engine spark ignition system includes two inductors and a circuit for transferring energy from the inductors to a common spark circuit when current flow through the inductors is interrupted. Two transistors control current flow in the respective inductors and these are controlled by a control circuit which turns on and then off just one of the transistors when a normal spark is required, and which turns on both transistors and then turns these alternately on and off when an extended spark is required.

This invention relates to spark ignition systems for internal combustion 
engines and has as an object to provide such a system in a convenient 
form. 
A spark ignition system in accordance with the invention comprises a pair 
of inductors, means for transferring energy stored in each inductor, when 
current flowing therethrough is interrupted, to a common spark circuit, a 
pair of semiconductor switch devices associated with the inductors 
respectively and controlling current flow therethrough and a control 
circuit for said switch devices such that when a normal spark is required 
one of said switch devices is switched on and then off, whereas when a 
prolonged sparking period is required both switch devices are switched on 
and then repeatedly switched on and off alternately for as long as the 
spark is required. 
Preferably, the control circuit is such that when a prolonged sparking 
period is required a delay is introduced between switching on said one of 
said switch devices and the other of said switch devices, said one of said 
switch devices being switched off when the sparking period is required to 
start and the other switch device being switched off when said one switch 
device is switched on again.

The system includes two conventional ignition transformers 10, 11, which 
have their primary windings 10a, 11a, connected between a supply rail 12 
and the collectors of a pair of n-p-n power transistors 13, 14 
respectively. The emitters of the transistors 13, 14 are earthed and their 
bases are connected by resistors 15, 16 to earth. The bases of the 
transistors, 13, 14 are also connected by resistors 17, 18 to output 
terminals X, Y of a signal generator circuit 19 for controlling the 
transistors. 
Two further n-p-n transistors 20, 21 have their bases connected by 
resistors 22, 23 to terminals X' and Y' of the circuit 19. These further 
transistors 20 and 21 have their collectors connected to the bases of the 
transistors 13, 14 respectively and their emitters earthed. The bases of 
the transistors 20, 21 are connected by resistors 24, 25 to earth. 
The signal generator 19 is controlled by a computer 26 itself having 
control inputs from a plurality of engine parameter transducers, such as 
transducers sensitive to engine speed, engine crank angle, throttle angle, 
manifold depression, temperature etc. The computer determines the instants 
at which the sparks are to be generated and also provides signals to 
indicate when current flow in the windings 10a, and 11a should commence 
and when, in certain engine conditions the sparking periods should be 
prolonged. 
In normal operation only the transformer 10 and the transistor 13 are used. 
In this mode of operation the transistor 13 is switched on and off at the 
beginning and end respectively of each pulse at terminal X of the circuit 
19. This is shown in FIG. 3a. 
When a prolonged sparking period is required, on the other hand, both 
transistors 13 and 14 are switched on (but switching on of transistor 14 
is delayed slightly) to enable energy to be built up in the transformers. 
At the instant when a spark is required, a pulse generator included in the 
circuit 19 switches on transistor 20 thereby switching off transistor 13. 
After a short interval transistor 20 is switched off again but transistor 
21 is switched on. Such alternate switching on and off of the transistors 
20 and 21 by pulses at the terminals X', Y' continues until the signals at 
the terminals X,Y terminate. 
The circuit of the signal generating circuit 19 is shown in more detail in 
FIG. 2. The circuit has two inputs from the computer 26 marked CON and 
EXT. As shown in FIGS. 3(a) and 3(b) the signal at the CON terminal is 
normally low but goes high when coil current is required to start and 
reverts to low when the spark is required. At the EXT terminal, the signal 
is normally low but goes high, if an extended sparking period is required, 
shortly after the signal at the CON terminal goes high and goes low again 
at the end of the required extended discharge period. 
The X output of the circuit 19 is derived from an OR gate 31 (e.g. 1/4 of 
an RCA CD 4071B CMOS integrated circuit) with its two input terminals 
connected respectively to the CON and EXT terminals and its output 
terminal connected to the X terminal. 
The Y output is derived from the EXT input terminal via a monostable 
circuit 32 (CD 4047A) with a pulse duration of about 300 uS and a flip 
flop 33 (1/2CD 4027B). The monostable circuit 32 has its input (pin 8) 
connected to the terminal EXT, its timing pins (1, 2, 3) interconnected by 
a resistor 34 and a capacitor 35, and its Q output (pin 11) connected to 
the CLOCK terminal of the flip-flop 33. The J input terminal of the 
flip-flop 33 (pin 6) is connected to the EXT terminal and the R input 
terminal (pin 4) is connected via an inverter 36 (1/6 CD 4049A) to the EXT 
terminal. The Q output terminal of the flip-flop 33 is connected to the Y 
terminal. These connections ensure that there is a delay between the 
signal on the EXT terminal going high and that on the Y terminal going 
high, such delay being desirable to ensure that when both transistors 13 
and 14 are in use, both turn on for approximately the same duration. The 
inverter 36 resets the flip-flop 33 when the signal at the EXT terminal 
goes low. 
The X' signal is derived from a CMOS oscillator gated by the signals from 
the CON and EXT terminals. This oscillator is constituted by a CMOS NAND 
gate 37 (1/3 CD 4023A) with one input terminal connected to the EXT 
terminal, a second input terminal connected by an inverter 38 (1/6 CD 
4049A) to the CON terminal and its third input terminal connected to 
receive positive feedback as will become apparent. The output terminal of 
the NAND gate 37 is connected to the input terminal of an inverter 46 (1/6 
CD 4049A) which has its output terminal connected to the X' terminal. A 
capacitor 39 and resistor 40 in series connect the output terminal of the 
inverter 46 to the third input terminal of the NAND gate 37 and a resistor 
41 is connected between the output terminal of the NAND gate 37 and the 
junction of the capacitor 39 with the resistor 40. The resistors 40, 41 
provide negative feedback around the NAND gate 37 so that it tends to 
operate in the linear mode when the signals at its first and second input 
terminals are high (i.e. when the CON signal is low and the EXT signal is 
high). The positive feedback via the capacitor 39 from the inverter 46 
output, however, converts the arrangement into a square wave oscillator, 
with the X' output going high as soon as the CON input goes low whilst the 
EXT input remains high. 
The Y' output signal is required to be the logical inverse of X' signal 
whenever the EXT signal is high and the oscillator 37, 46 is running. To 
this end, the Y' output is derived from an AND gate 42 (1/4 CD 4081B), 
which has one input terminal connected via an inverter 43 (1/6 CD 4049A) 
to the X' output terminal and its other input terminal connected to the 
output terminal of a NOR gate 44 (1/4 CD 4001A). This NOR gate 44 is cross 
connected with another NOR gate 45 (1/4 CD 4001A) as an R-S flip-flop, 
with the NOR gate 45 having an input from from the inverter 46 and the NOR 
gate 44 having an input from the inverter 36 for setting and resetting the 
flip-flop formed by the NOR gates 44, 45. Thus the flip-flop 44, 45 is set 
by the first high at terminal X' after the EXT signal goes high, 
thereafter allowing gate 42 to pass the inverted X' signals until the 
flip-flop 44, 45 is reset by the EXT signal going low. 
The secondary windings of the transformers 10, 11 are connected by diodes 
27, 28 to the common terminal of the ignition distributor 29 which 
connects the spark plugs 30 to the ignition circuit. 
It is to be understood that since the voltage required to maintain an 
established spark discharge is less than that required to initiate the 
spark, the coil 11 may be of less substantial construction than the coil 
10 and the associated semiconductor components may have lesser voltage, 
current and/or power ratings. The mark/space ratio of the oscillator (37, 
46) may be less than unity. 
It is also to be understood that instead of a single prolonged spark being 
produced when required a series of discrete sparks may be produced. The 
effect of this is to prolong the sparking period.