Remote tuner clock distribution using serializer/deserializer technology

A communication system includes a first radio module and a second radio module. The first radio module includes a tuner communicatively coupled to a reference signal generator that is configured to generate a first reference signal for the tuner. The first radio module further includes a serializer configured to serialize a signal output by the tuner. The second radio module includes a deserializer configured to receive a serialized version of the signal from the serializer of the first radio module and deserialize the serialized version of the signal. The second radio module further includes a second tuner that is communicatively coupled to a clock recovery circuit. The clock recovery circuit is configured to generate a second reference signal for the second tuner based on a deserialized version of the first signal, where the second reference signal is frequency and phase locked to the first reference signal.

BACKGROUND

Communication systems can employ diversity reception schemes to improve signal reliability by utilizing multiple communication channels having different respective channel characteristics. Examples of channel diversity include, but are not limited to, time diversity, frequency diversity, space diversity, polarization diversity, multi-user diversity, cooperative diversity, combinations thereof, and so forth. Diversity reception is often performed by two or more tuners that are co-located so that they can run off the same frequency reference. For example, FM diversity solutions have tuners and baseband demodulators located within a head unit (e.g., a vehicular head unit) or in a remote radio module (e.g., a radio module located near a respective antenna or set of antennas). Tuners may be located near their respective antennas to reduce signal loss when the signal is transmitted from the antennas to the tuners and/or to reduce the number or length of cables needed to for connections between the tuners and their respective antennas. However, in diversity reception schemes it may be desirable to locate antennas at different positions to provide space diversity and/or prevent interference amongst the antennas. In these situations, disposing the tuners near their respective antennas requires each radio module for each antenna or set of antennas to have its own frequency reference (e.g., its own clock signal). Diversity reception using separate frequency references (e.g., separate clocks) for each radio module can be unreliable due to crystal frequency errors, and digital feedback techniques for clock synchronization are complicated and prone to start-up issues. Consequently, there is a need for diversity reception schemes that can operate multiple radio modules at a same or substantially same frequency reference (e.g., using a same or substantially same clock signal).

DETAILED DESCRIPTION

Overview

Diversity reception schemes are employed in communication systems to improve signal reliability. For example, diversity reception schemes can be implemented in communication systems, including, but not limited to, radio communication systems, telecommunication systems, security systems, sound systems, television broadcasting systems, internet broadcasting systems, sensor systems, control systems, power distribution networks, and the like. Diversity reception schemes improve signal reliability by employing multiple communication channels having different respective channel characteristics. Examples of channel diversity include, but are not limited to, time diversity, frequency diversity, space diversity, polarization diversity, multi-user diversity, cooperative diversity, combinations thereof, and so forth.

Diversity reception schemes often employ multiple antennas, wherein a signal from each antenna is buffered and sent over a respective cable (e.g., coaxial cable) to a head unit where at least one tuner receives the signal from the antenna. Tuners may be located near their respective antennas to reduce signal loss when the signal is transmitted from the antennas to the tuners and/or to reduce the number or length of cables needed to for connections between the tuners and their respective antennas. However, as discussed above, diversity reception schemes often employ antennas at different positions (e.g., to provide space diversity and/or prevent interference amongst the antennas). Disposing the tuners near their respective antennas requires each radio module to have its own frequency reference (e.g., its own reference signal generator). However, diversity reception schemes that employ separate frequency references (e.g., separate reference signal generators) for each radio module can be unreliable due to crystal frequency errors.

A diversity reception scheme for a communication system is disclosed. In an implementation, the communication system includes two or more radio modules (e.g., at least a first radio module and a second radio module) that may be physically separate and/or remotely located from one another. The first radio module includes at least one tuner communicatively coupled to a reference signal generator that is configured to generate a first reference signal for the tuner. The first radio module further includes a serializer configured to serialize a signal output by the tuner. The second radio module includes a deserializer configured to receive a serialized version of the signal from the serializer of the first radio module and deserialize the serialized version of the signal. The second radio module further includes at least one (second) tuner that is communicatively coupled to a clock recovery circuit. The clock recovery circuit is configured to generate a second reference signal for the second tuner based on a deserialized version of the first signal, where the second reference signal is frequency and phase locked to the first reference signal. The deserializer provides a low-jitter output that can be processed by the clock recovery circuit to generate a second reference signal for the second radio module. In this manner, the system can provide robust diversity reception by providing a frequency reference (e.g., the second reference signal) for one or more tuners in the second radio module that is frequency and phase locked to the frequency reference (e.g., crystal or other reference signal generator) of the first radio module.

Example Implementations

FIG. 1is a block diagram illustrating a communication system100in accordance with an example embodiment of this disclosure. In embodiments, the communication system100includes, but is not limited to, radio communication systems, telecommunication systems, security systems, sound systems, television broadcasting systems, internet broadcasting systems, sensor systems, control systems, power distribution networks, or the like. The communication system100includes at least two radio modules (e.g., at least a first radio module102and a second radio module118) that may be physically separate and/or remotely located from one another. For example, the first radio module102and the second radio module118can have respective enclosures (e.g., enclosure103and enclosure119) that define a physical boundary for some or all of the respective components of the first radio module102and the second radio module118. The first radio module102and the second radio module118are configured to provide multiple communication channels for a diversity reception scheme. Examples of channel diversity implemented by the first radio module102and the second radio module118can include, but are not limited to, time diversity (e.g., where multiple versions of a signal are transmitted at different time instants), frequency diversity (e.g., where a signal is transmitted at several broadcast frequencies), space diversity (e.g., where a signal is transmitted over several propagation paths), polarization diversity (e.g., where multiple versions of a signal are transmitted with antennas having different respective polarization characteristics), multi-user diversity, cooperative diversity, combinations thereof, and so forth.

The communication channels implemented by the first radio module102and the second radio module118include a plurality of broadcast channels received by respective antennas of the first radio module102and the second radio module118. In some embodiments, the plurality of broadcast channels include a plurality of different broadcast channels. For example, the plurality of different broadcast channels can include different terrestrial broadcast channels, different geo-positioning signals, different satellite broadcast channels, or the like. The plurality of different broadcast channels may include a combination of different channel types. For example, the plurality of different broadcast channels can include a combination of a terrestrial broadcast channel and a geo-positioning signal, a combination of a terrestrial broadcast channel and a satellite broadcast channel, a combination of a satellite broadcast channel and a geo-positioning signal, a terrestrial broadcast channel, a combination of a satellite broadcast channel and a geo-positioning signal, or any other combination of different channel types. Examples of broadcast channels received by the respective antennas of the first radio module102and the second radio module118can include, but are not limited to, amplitude modulation (AM) channels, frequency modulation (FM) channels, digital audio broadcasting (DAB) channels, satellite radio channels, digital television (DTV) broadcasting channels, satellite television channels, global navigation satellite system (GNSS) signals, radio frequency (RF) communication signals, optical communication signals, cellular tower signals, microwave communication signals, and combinations thereof.

The first radio module102includes at least one tuner106having a respective antenna108communicatively coupled to the tuner106. In some embodiments, the first radio module102also includes at least one additional tuner110that can also have respective antenna112communicatively coupled to the tuner110. In some embodiments, two or more tuners (e.g., tuner106and tuner110) can be communicatively coupled to a shared antenna (e.g., a shared multi-band antenna). The tuner106may be communicatively coupled to a reference signal generator104(e.g., a crystal oscillator (XO), temperature compensated crystal oscillator (TCXO), or the like). The reference signal generator104can generate a first reference signal (fREF) for the tuner106and any other tuners (e.g., tuner110) or other components (e.g., serializer114) of the first radio module102. The tuner106may communicate fREFto the tuner110via a communication link111(e.g., one or more wires, traces, etc.). In some embodiments, the communication link111is coupled to an output buffer of the tuner106that relays fREFor a buffered version of fREF. In some embodiments, the tuner106outputs a clock signal (PCLK) based on the first reference signal for other tuners (e.g., tuner110) or other components (e.g., serializer114) of the first radio module102. For example, tuner106may communicate PCLK to the tuner110and the serializer114via a communication link105(e.g., one or more wires, traces, etc.). The tuner106can also be configured to communicate a word select (WS) signal to the tuner110and the serializer114via a communication link107(e.g., one or more wires, traces, etc.). The WS signal may include a signal that toggles from a first state (e.g., high or “1”) to a second state (e.g., low or “0”), or vice versa, to indicate transmission of a next data segment (e.g., next word) in a series of data segments having a transmission rate controlled according to fREFand/or PCLK. The tuners (e.g., tuner106and tuner110) can also be configured to communicate data signals (e.g., broadcast signals) to the serializer114via data lines109and113. In some embodiments, tuner106has at least two respective data lines109, and tuner110has at least two respective data lines113. However, in other embodiments, each of the tuners can have one respective data line, or any number of respective data lines.

The serializer114of the first radio module102is configured to serialize signals output by the one or more tuners (e.g., tuners106and/or110) of the first radio module102. In an embodiment, the serializer114is configured to serialize a first signal output by the tuner106. It is noted that any reference to a “first” or “second” component or signal does not indicate any order unless otherwise stated. These terms are used herein to distinguish components, signals, and the like. The serializer114output is communicatively coupled to a cable116(e.g., a coaxial cable, a twisted pair cable, or the like). In some embodiments, the cable116includes a single cable (e.g., a single coaxial cable, a single twisted pair cable, or the like), where the serializer114is configured to serialize signals from one tuner (e.g., tuner106or tuner110) or a plurality of tuners (e.g., tuner106and tuner110) prior to transmission of the signals via cable116. In some embodiments, the serializer114is configured to serialize a plurality of digitized channels from the plurality of tuners (e.g., tuner106and tuner110) onto a single output for transmission via cable116. The serializer114is configured to transmit a serialized version of the first signal to the second radio module118. For example, the serializer114can be configured to transmit the serialized version of the first signal via cable116.

The second radio module118includes a deserializer120that is configured to receive the serialized versions of the signals transmitted by the serializer114from tuners (e.g., tuner106and/or tuner110) in the first radio module102. For example, the deserializer120is configured to receive a serialized version of the first signal from the serializer114. In an embodiment, the deserializer120is configured to receive the serialized version of the first signal from serializer114via cable116. The deserializer120is configured to deserialize the serialized version of the first signal. In some embodiments, the first signal includes a serialized version of PCLK. For example, the deserializer120outputs a deserialized version of PCLK that can be communicated to various components (e.g., clock recovery circuit122, tuner124, tuner128, serializer132, etc.) of the second radio module128via a communications link125(e.g., one or more wires, traces, etc.). The deserializer120can also be configured to communicate a deserialized version of the WS signal to various components (e.g., clock recovery circuit122, tuner124, tuner128, serializer132, etc.) of the second radio module128via a communications link127(e.g., one or more wires, traces, etc.). The deserializer120can also be configured to communicate deserialized data signals (e.g., broadcast signals) from the first radio module102to a serializer132of the second radio module118via one or more data lines129. In some embodiments, deserializer120has at least four respective data lines129. However, in other embodiments, the deserializer120may have one respective data line, or any number of respective data lines.

The second radio module118includes a clock recovery circuit122communicatively coupled to the deserializer120via communication link125. In some embodiments, the clock recovery circuit122includes a phase-locked loop (PLL)121and an oscillator123(e.g., a voltage-controlled oscillator (VCO), voltage-controlled crystal oscillator (VCXO), digitally controlled crystal oscillator (DCXO), or the like). Some or all of the components of the clock recovery circuit122may be realized as an integral part of the deserializer120, and as a result a separate clock recovery circuit may not be required in all cases. The clock recovery circuit122is configured to generate a second reference signal (fREF2) for the second radio module118based on a deserialized version of the first signal (e.g., based on the deserialized version of PCLK). fREF2is frequency and phase locked fREF(i.e., the reference signal output by the reference signal generator104of the first radio module102). For example, fREF2may identical or nearly identical to fREF. Some examples of clock recovery schemes that use serializer/deserializer (SerDes) devices are described in U.S. Pat. No. 8,780,939, U.S. Pat. No. 8,368,436, U.S. Pat. No. 6,081,572, U.S. Pat. No. 8,488,657, and U.S. Pat. No. 9,077,348, all of which are incorporated herein by reference. The clock recovery circuit122can be configured to implement any such clock recovery scheme, or the like. Generally, a SerDes interface can include any interface where data from a wide bus is combined to generate data for a narrow bus. For example, a SerDes interface can include clocked interfaces (e.g., SPI, I2S, etc.) or systems that utilize embedded clocks and data packets (e.g., Ethernet, JESD204b, etc.). A SerDes interface may also implement synchronization methodology whereby a clock signal, or a coding scheme that realizes and embedded clock, is used to synchronize the tuners. The clock may be an external clock or an integral part of the interface. Examples of SerDes interfaces can include, but are not limited to, serializer/deserializer pairs, High-Definition Multimedia Interface (HDMI) devices, Digital Visual Interface (DVI) devices, Peripheral Component Interconnect Express (PCIe) devices, Inter-IC Sound (I2S) devices, Serial Peripheral Interface (SPI) devices, JESD204b interface devices, Ethernet devices, FDP-link devices, Gigabit Multimedia Serial Link (GMSL) devices, and the like.

The second radio module118also includes at least one tuner124having a respective antenna126communicatively coupled to the tuner124. In some embodiments, the second radio module118further includes at least one additional tuner128that can also have respective antenna130communicatively coupled to the tuner128. In some embodiments, two or more tuners (e.g., tuner124and tuner128) can be communicatively coupled to a shared antenna (e.g., a shared multi-band antenna). The tuner(s) (e.g., tuner124and/or tuner128) are communicatively coupled to the clock recovery circuit122. As described above, the clock recovery circuit122is configured to generate fREF2as a reference signal (that is frequency and phase locked to fREF) for the tuner124and any other tuners (e.g., tuner128) or other components (e.g., serializer132) of the second radio module118. In this manner, multiple radio modules (e.g., radio modules102and118) that are physically separate and/or remotely located from one another can still operate at the same reference frequency and phase. In some embodiments, the tuner124is communicatively coupled to the clock recovery circuit122via communication link141(e.g., one or more wires, traces, etc.) and configured to receive fREF2from the clock recovery circuit122. The tuner124may communicate fREF2to the tuner128via a communication link143(e.g., one or more wires, traces, etc.). In some embodiments, the communication link143is coupled to an output buffer of the tuner124that relays fREF2or a buffered version of fREF2. The tuners (e.g., tuner124and tuner128) can also be configured to communicate data signals (e.g., broadcast signals) to the serializer132via data lines131and133. In some embodiments, tuner106has at least two respective data lines131, and tuner133has at least two respective data lines113. However, in other embodiments, each of the tuners can have one respective data line, or any number of respective data lines.

The communication system100can include a baseband processor138configured to receive signals from the tuners (e.g., tuner106, tuner110, tuner124, and/or tuner128). The baseband processor138can be configured to perform a diversity reception algorithm utilizing the signals. In embodiments, the baseband processor138can include a processor coupled to a memory. The processor may include any number of microprocessors, digital signal processors, micro-controllers, circuitry, field programmable gate array (FPGA) or other processing systems, and resident or external memory for storing data, executable code, and other information accessed or generated by the communication system100. The processor can execute one or more software programs embodied in a non-transitory computer readable medium that implement techniques described herein. The processor is not limited by the materials from which it is formed or the processing mechanisms employed therein and, as such, can be implemented via semiconductor(s) and/or transistors (e.g., using electronic integrated circuit (IC) components), and so forth.

The memory of the baseband processor138can be a tangible, computer-readable storage medium that provides storage functionality to store various data and or program code associated with operation of the communication system100, such as software programs and/or code segments, or other data to instruct the processor, and possibly other components of the communication system100, to perform the functionality described herein. Thus, the memory can store data, such as a program of instructions for operating the communication system100(including its components), and so forth. It should be noted that while a single memory is described, a wide variety of types and combinations of memory (e.g., tangible, non-transitory memory) can be employed. The memory can be integral with the processor, can comprise stand-alone memory, or can be a combination of both. Some examples of the memory can include removable and/or non-removable memory components, such as random-access memory (RAM), read-only memory (ROM), flash memory (e.g., a secure digital (SD) memory card, a mini-SD memory card, and/or a micro-SD memory card), magnetic memory, optical memory, universal serial bus (USB) memory devices, hard disk memory, external memory, and so forth. In implementations, the memory can include removable integrated circuit card (ICC) memory, such as memory provided by a subscriber identity module (SIM) card, a universal subscriber identity module (USIM) card, a universal integrated circuit card (UICC), and so on.

The baseband processor138is in communication with the first radio module102and the second radio module118. The baseband processor138may be located remotely (e.g., may be disposed physically separate) from the first radio module102and/or the second radio module118. In some embodiments, the baseband processor138can be disposed in a head unit136having an enclosure137that physically separates some or all of the components of the head unit136from the first radio module102and the second radio module118. In other embodiments, the baseband processor138can be disposed in one of the radio modules (e.g., in the second radio module118). It is noted that any number of radio modules can be linked together in the manner shown inFIG. 1, wherein the first radio module102includes a reference signal generator104and additional radio modules in between the first radio module and the baseband processor138each include a clock recovery circuit122configured to generate a respective clock signal having the same or substantially same phase and frequency characteristics as the first reference signal that is output by the reference signal generator104.

In embodiments where the baseband processor138is located in a head unit136separate from the radio modules102and118(e.g., as shown inFIG. 1), the second radio module118can include a serializer132that is configured to serialize signals output by the one or more tuners (e.g., tuners124and/or128) of the second radio module118. The serializer132can also be configured to reserialize signals from the first radio module118. For example, the serializer132may be configured to reserialize the first signal after the first signal has been serialized at the first radio module102and deserialized at the second radio module118. The serializer132output can be communicatively coupled to a cable134(e.g., a coaxial cable, a twisted pair cable, or the like). In some embodiments, the cable134includes a single cable (e.g., a single coaxial cable, a single twisted pair cable, or the like), where the serializer132is configured to serialize signals from at least one tuner (e.g., tuner124and/or128) of the second radio module118, or reserialize signals from at least one tuner (e.g., tuner106and/or tuner110) of the first radio module102onto one output (i.e., the serializer132output) for transmission via cable134. The serializer132can be configured to transmit serialized versions of signals from at least one tuner of the first radio module102and/or at least one tuner of the second radio module118to the head unit136for further processing (e.g., demodulation and/or diversity reception processing) by the baseband processor138. For example, the serializer132can be configured to transmit the serialized versions of the signals via cable134. The head unit136can include a deserializer140configured to receive serialized versions of the signals from the tuner(s). For example the deserializer140can be configured to receive the serialized versions of the signals via cable134. The deserializer140can be further configured to deserialize the serialized versions of the signals and transmit deserialized versions of the signals to the baseband processor138. In an embodiment, the deserializer140transmits the deserialized versions of the signals to the baseband processor138via communication link145. For example, communication link145can include a plurality of data lines, a PCLK signal line, WS signal line, and so forth.

It is noted that the one or more tuners (e.g., tuner106and/or tuner110) of the first radio module102do not need to be active in order to receive signals with the one or more tuners (e.g., tuner122and/or tuner124) of the second radio module118. Similarly, the tuners of the second radio module118do not need to be active to receive signals with the tuners of the first radio module102. Both of the first radio module102and the second radio module118may be active when a diversity reception scheme is employed. For example, the baseband processor138may be configured to receive similar (e.g., same signal type or frequency band) or different signals from a tuner (e.g., tuner106and/or tuner110) of the first radio module102and from a tuner (e.g., tuner122and/or tuner124) of the second radio module118. The baseband processor138may be configured to combine or select from these signals to leverage the different tuner characteristics and/or their respective antenna positions. The baseband processor138can be configured to perform a diversity reception algorithm utilizing the signals. For example, in an embodiment, the baseband processor138is configured to select a strongest signal (e.g., from among multiple received signals). In another embodiment, the baseband processor138is configured to average or combine multiple signals to improve signal performance.

In embodiments, the tuners (tuner106, tuner110, tuner122, and/or tuner124) are configured to output a digital data stream. In some embodiments, the digital data stream output by a tuner includes a reference signal (e.g., first reference signal or second reference signal) either as a unique signal or combined with other data in the digital data stream. An example format for the digital data stream is an I2S format, which includes a clock signal, word-frame signal, in-phase data (I-data) components, and quadrature data components (Q-data). The serializer (e.g., serializer114or serializer132) can be configured to use the clock signal as a master clock signal with the other lines used as general inputs. In some embodiments, the serializer (e.g., serializer114or serializer132) is configured to accept multiple lines (e.g., up to 14 or more) such that many tuners can be located in a radio module (e.g., in radio module102or radio module118). In embodiments, the clock signal may be generated by the tuner (e.g., tuner106) with a fractional relationship to the reference signal generated by the reference signal generator104. In other embodiments, the clock signal is the same or substantially the same as the reference signal. In other embodiments, the clock signal is based on the reference signal and generated by circuitry between the tuner106and the reference signal generator104.

In some embodiments, the communication system100employs power-over-coax to furnish power (e.g., via cables116and/or134) to the serializer/deserializer (SerDes) devices (e.g., serializer114, deserializer120, serializer132, and/or deserializer140). The communication system100may also employ power-over-coax to furnish power to the tuners (e.g., tuner106, tuner110, tuner126, and/or tuner130). In some embodiments, a control channel within a respective one of the SerDes devices (e.g., serializer114, deserializer120, serializer132, and/or deserializer140) can be used to program the tuners (e.g., tuner106, tuner110, tuner126, and/or tuner130) via I2C formatted commands. Employing SerDes devices for communications via cables116and134can eliminate the need for active antenna buffers (e.g., low-noise amplifiers (LNAs)), separate power cables, and separate control lines. In addition, placing the tuners (e.g., tuner106, tuner110, tuner126, and/or tuner130) in radio modules (e.g., radio module102and/or radio module118) instead of placing the tuners in the head unit136can reduce design complexity by eliminating or reducing the presence of noise sensitive analog signals in the head unit136. Power dissipation in the head unit136may also be reduced when the tuners (e.g., tuner106, tuner110, tuner126, and/or tuner130) are included in radio modules (e.g., radio module102and/or radio module118) that are separate from the head unit136.

Example Process

FIG. 2illustrates an example process200for providing a reference signal for a second radio module that is physically separate from a first radio module in a communication system that employs a diversity reception scheme, such as the communication system100shown inFIG. 1. In general, operations of disclosed processes (e.g., process200) may be performed in an arbitrary order, unless otherwise provided in the claims.

The process200includes generating a first reference signal at a first radio module102(block202). For example, the reference signal generator104can generate a first reference signal (e.g., fREF) for the tuner106and other components (e.g., tuner110, serializer114, etc.) of the first radio module102. At least one tuner (e.g., tuner106) can be synchronized to the first reference signal (block204). For example, the tuner106can be communicatively coupled to the reference signal generator104and configured to receive the first reference signal as an input to the tuner106. In some implementations, the tuner106generates a clock signal (PCLK) for the other components (and possibly for itself) based on the reference signal from the reference signal generator104. In this regard, the other components can be indirectly synchronized to the first reference signal based on the clock signal.

At least one signal output by a tuner (e.g., tuner106) of the first radio module102is serialized at the first radio module102(block206). For example, the serializer114can serialize a signal (e.g., PCLK) output by tuner106. A serialized version of the signal is then transmitted (e.g., via cable116) from the first radio module102to a second radio module118(block208). In some implementations, several serialized versions of signals from tuners of the first radio module102can be transmitted via a single coaxial cable.

The serialized version of the signal is deserialized at the second radio module118(block210). For example, the deserializer120of the second radio module118can receive the serialized version of the signal (e.g., via cable116) and can deserialize the serialized version of the signal. A second reference signal (e.g., fREF2) is then generated based on a deserialized version of the signal (block212). For example, the deserializer120can transmit the deserialized version of the signal (e.g., PCLK) to the clock recovery circuit122, and the clock recovery circuit122can generate the second reference signal (e.g., fREF2) for at least one tuner (e.g., tuner126and/or128) and other components (e.g., serializer132) of the second radio module118. In this manner, the second radio module118is provided with a reference signal (e.g., fREF2) that is frequency and phase locked to the first reference signal generated by the reference signals generator104of the first radio module102.

Generally, any of the functions described herein can be implemented using hardware (e.g., fixed logic circuitry such as integrated circuits), software, firmware, manual processing, or a combination thereof. Thus, the blocks discussed in the above disclosure generally represent hardware (e.g., fixed logic circuitry such as integrated circuits), software, firmware, or a combination thereof. In the instance of a hardware configuration, the various blocks discussed in the above disclosure may be implemented as integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system, or circuit, or a portion of the functions of the block, system, or circuit. Further, elements of the blocks, systems, or circuits may be implemented across multiple integrated circuits. Such integrated circuits may comprise various integrated circuits, including, but not necessarily limited to: a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. In the instance of a software implementation, the various blocks discussed in the above disclosure represent executable instructions (e.g., program code) that perform specified tasks when executed on a processor. These executable instructions can be stored in one or more tangible computer readable media. In some such instances, the entire system, block, or circuit may be implemented using its software or firmware equivalent. In other instances, one part of a given system, block, or circuit may be implemented in software or firmware, while other parts are implemented in hardware.

It is to be understood that the present application is defined by the appended claims. Although embodiments of the present application have been illustrated and described herein, it is apparent that various modifications may be made by those skilled in the art without departing from the scope and spirit of this disclosure.