Phase change memory device and method of forming the same

A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes a plurality of overlapping film patterns, each of which having a respective first portion proximal to the conductive element and a second portion proximal to the phase change material. The second portions are configured and dimensioned to have higher resistance than the first portions.

BACKGROUND OF THE INVENTION

1. Technical Field

The present disclosure relates to a memory device and, more specifically, to a phase change memory device and method of forming the same.

2. Discussion of the Related Art

A phase change memory device is a type of non-volatile computer memory where data is stored by changing a chalcogenide material between an amorphous state and a crystalline state. Phase change memory devices such as PRAM (phase change random access memory) have demonstrated remarkable potential to be competitive with the ubiquitous Flash memory.

The PRAM device includes an array of memory cells. Each cell includes a layer of chalcogenide phase change material with a top electrode above the chalcogenide layer and a resistive heater element below the chalcogenide layer.

FIG. 1is a schematic of a PRAM cell structure. The PRAM cell1000includes a chalcogenide layer1100covered with a top electrode1200. The chalcogenide layer1100can include an alloy of a group V or VI element such as Tellurium (Te) Selenium (Se) or Antimony (Sb). One example of a suitable chalcogenide includes Ge2Sb2Te5. A resistive heating element1300is below the chalcogenide layer1100. A programming current may be applied to the top electrode1200by a bit line1400. A single bit line1400may connect an entire column of PRAM cells1000within a cell matrix. The resistive heating element (heater)1300is below the chalcogenide layer1100. The heater1300is connected to a transistor1500that is in turn connected to ground1700. The transistor1500controls the flow of current through the PRAM cell1000depending on a signal received from a word line1600. A single word line may connect an entire row of PRAM cells.

To program a cell, current is passed from the top electrode through the resistive heater. By varying the level of current, the heat of the chalcogenide layer may be changed between an amorphous state and a crystalline state. As used herein, the crystalline state may refer to a polycrystalline state where multiple crystals are formed within the same chalcogenide layer.

In its amorphous state, the chalcogenide has a relatively high resistivity. In its crystalline state, the chalcogenide has a relatively low resistivity. The difference in resistivity between the amorphous and crystalline states may vary by two or more orders of magnitude. This sharp difference in resistivity facilitates the reading of the PRAM cell by application of a read voltage Vr and measuring the resultant current. A low resultant current indicates a high resistivity corresponding to the amorphous state while a high resultant current indicates a low resistivity corresponding to the crystalline state. Each state may be assigned a particular logical value. For example, the crystalline state may correspond to a logical “0” while the amorphous state may correspond to a logical “1.”

As discussed above, phase change may be controlled by varying the level of current through the resistive heater and thus changing the temperature of the chalcogenide.FIG. 2shows temperature curves for eliciting an amorphous state and a crystalline state for a given chalcogenide. An amorphous state is achieved by heating the chalcogenide to a temperature above the melting temperature Tmof the particular chalcogenide used and then allowing the chalcogenide to quickly cool to below the crystallization temperature Tcover a time T1. This temperature curve is shown as2100. Because the temperature of the chalcogenide quickly cools to below a crystallization temperature Tcfor the particular chalcogenide used, the chalcogenide is not given an opportunity to crystallize and thus remains in an amorphous state. A crystalline state is elicited by heating the chalcogenide to a temperature above the crystallization temperature Tcbut below the melting temperature Tm. The temperature remains above the crystallization temperature Tcover a slow cooling time T2. This temperature curve is shown as2200. Because the temperature of the chalcogenide remains above the crystallization temperature but below the melting temperature for a sustained period of time, the chalcogenide is allowed to crystallize.

A single heater element may be used to produce each of the desired temperature curves. The heater element generates the desired heat by resisting the flow of current and converting electrical energy into heat. Accordingly, higher temperatures may be achieved by increased current. Similarly, a short time T1is achieved by using a short pulse while a slow cooling time is achieved by using a long pulse.

FIGS. 3 to 6show a fabrication process for manufacturing a conventional PRAM device. As seen inFIG. 3, an isolation layer5is formed on a semiconductor substrate1using an isolation process. The isolation layer5includes an oxide that functions as a mask during a doping process. The doping process defines an active region within the substrate1not covered by the isolation layer5. Gate structures25are formed on the active region of the substrate1. Each gate structure25includes a gale oxide layer pattern10, a gate electrode15and a gate spacer20. The gate electrode15is formed using a doped polysilicon or a metal. The gate spacer20is formed using silicon nitrite. A source region30and a drain region35are formed at portions of the active region adjacent to the gate structure25by an ion implantation process. A first insulating interlayer40is formed on the substrate1having the source30and the drain35regions to cover the gate structures25. The first insulating interlayer40is generally formed using a silicon oxide.

As seen inFIG. 4, contact holes (not shown) are formed through the first insulating interlayer40by partially etching the first insulating interlayer40. The contact holes expose the source30and drain35regions, respectively. Each of the contact holes has an upper portion and a lower portion, with the upper portion being wider than the lower portion.

A conductive layer (not shown) is formed on the source region30, drain region35and the insulating interlayer40. The conductive layer fills the contact holes. The conductive layer includes a doped poly silicon or a metal. The conductive layer is then removed exposing the first insulating interlayer40. A first contact45and a second contact50may then be formed in the contact holes. The first contact45is formed on the source region30and the second contact50is formed on the drain region35. A second insulating interlayer55is formed on the first insulating layer40and covers the first contact45and the second contact50. The second insulating interlayer55is partially etched and an opening60is formed that exposes the first contact45. The second insulating interlayer55is generally formed using silicon oxide.

As seen inFIG. 5, an insulation layer (not shown) is formed at the bottom of the opening60(FIG. 4), a sidewall of the opening60and on the second insulating interlayer55. The insulation layer is etched and a spacer70is formed on the sidewall of the opening60. The spacer70is formed using silicon nitride. A lower electrode layer is formed on the exposed first contact45and the second insulating interlayer55. The lower electrode layer is then removed by a chemical-mechanical planarization (CMP) process until the second insulating interlayer55is exposed. A lower electrode65is thereby formed in the opening60. The lower electrode65is formed using a metal or metal nitride. A phase-change material layer75and an upper electrode layer80are successively formed on the lower electrode65and the second insulating interlayer55. The phase-change material layer75is formed using chalcogenide. The upper electrode layer80is formed using a metal or metal nitride.

As seen inFIG. 6, the upper electrode layer80and the phase-change material layer75are patterned and a phase-change material layer pattern85and an upper electrode90are formed on the lower electrode65and the second insulating interlayer55. A third insulating interlayer95is formed on the second insulating interlayer55to cover the upper electrode90. The third insulating interlayer95is formed using silicon oxide.

As PRAM devices must have a high density of memory cells to be commercially viable, the total energy dissipated by the set of resistive heater elements can be substantial. In addition to relatively high power consumption, the substantial level of heat generated may be detrimental to the PRAM device and its surrounding components. Moreover, the relatively high power consumption and the substantial level of generated beat can impose limiting design constraints on PRAM devices.

SUMMARY OF THE INVENTION

A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes a plurality of film patterns. Each of the plurality of film patterns has a respective first portion proximal to the conductive element and a second portion proximal to the phase change material. The plurality of film patterns overlap with each other. Accordingly, there are multiple film patterns, the multiple film patterns overlap one another, and each of the overlapping film patterns has a first portion and a second portion. Each of the second portions are configured and dimensioned to have a higher resistance than the first portions.

The first portions may lie in a plane that is coplanar with the electrically conductive element and orthogonal with the second portions. The ends of the second portions may contact the phase change material. The area of the first portions may be larger than the area of the ends of the second portions contacting the phase change material. The area of the first portion of each film pattern may be about two to about twenty times the area of its second portions contacting the phase change material. The plurality of film patterns may include two to ten film patterns. The plurality of film patterns may include at least two film patterns having different resistivity. The different resistivity may be derived from different content of metals in the film patterns. The film patterns may include one of WNx, AlNx, TiNx, TaNx, MoNx, NbNx, TiSiNx, TiAlNx, TiBNx, ZrSiNx, WSiNx, WBNx, ZrAlNx, MoSiNx, MoAlNx, TaSiNx, or TaAlNx, and the amount of metal may be varied to vary the resistivity. The amount of metal may be gradually increased in each film pattern in the direction from the overlapped film pattern toward the overlapping film pattern. The amount of metal may be gradually decreased in each film pattern in the direction from the overlapped film pattern toward the overlapping film pattern. The amount of metal may be varied in each film pattern in the direction from the overlapped film pattern toward the overlapping film pattern. The current restrictive element may be bounded by a spacer and the space within the spacer is tilled by the plurality of film patterns. The current restrictive element may be bounded by a spacer and the space within the spacer is filled by the plurality of film patterns and a filling member disposed about the middle portion of the space. The filling member may include one of USG, SOG, FOX, BPSG, PSG, TEOS, PE-TEOS and HDP-CVD oxide, or nitride.

A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes a plurality of film patterns. Each of the film patterns extends from the electrically conductive element to the phase change material. At least two of the film patterns are made of a different material.

The plurality of the film patterns may include one of WNx, AlNx, TiNx, TaNx, MoNx, NbNx, TiSiNx, TiAlNx, TiBNx, ZrSiNx, WSiNx, WBNx, ZrAlNx, MoSiNx, MoAlNx, TaSiNx and TaAlNx. Another film pattern may include poly silicon or tungsten nitride. The resistivity of a film pattern may be varied by varying the content of metal.

A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes concentric shell layers including an inner-most layer having a first footprint and an outer-most layer having a second footprint. The second footprint is larger than the first footprint.

One or more of the concentric shell layers may be narrower at an end proximate to the phase change material than at an end proximate to the electrically conductive material. The inner-most layer may have a higher resistance and/or resistivity than the outer-most layer.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention provide for phase change memory devices having a high density of memory cells while minimizing the total level of dissipated heat and energy consumed. According to some exemplary embodiments, the total level of dissipated heat and consumed energy can be minimized by using a resistive heater element, in the form of a lower electrode that focuses heat towards a phase change material while minimizing the overall level of heat dissipation and energy consumption. The focused resistive element is able to direct sufficient heat to the phase change material to affect a desired phase change while minimizing the amount of heat that is dissipated in directions other than towards the phase change material.

Resistive heating elements according to exemplary embodiments of the present invention may be able to focus dissipated heat towards the phase change material in a variety of ways. For example, the resistive heating element may comprise a plurality of layers that form a set of concentric shell layers including an inner-most layer having a smallest footprint and an outer-most layer having a largest footprint.

FIG. 7is a perspective cutaway view of a resistive heating element according to an exemplary embodiment of the present invention. As can be seen inFIG. 7, the resistive heating element7000comprises a plurality of layers7100-7400that form a set of concentric shell layers including an inner-most layer7400having a smallest footprint and an outer-most layer7100having a largest footprint. There may be any number of intermediate layers, however, inFIG. 7, only two such layers7200and7300are shown for illustrative purposes. The total number of layers used may depend on the desired electrical characteristics of the phase change material used. While the concentric shell layers7100-7400ofFIG. 7each have a rectangular footprint, the footprint may be of any geometric shape, such as circular or polygonal. Each layer may have a similar thickness.

FIG. 8is a perspective cutaway view of a resistive heating element according to an exemplary embodiment of the present invention. As can be seen inFIG. 8, the resistive heating element8000comprises a plurality of concentric shell layers8100-8400each having a circular footprint.

The plurality of concentric shell layers may each have a narrowing width such that the width of each layer is narrower towards the top than at the bottom. The extent to which the width of each layer narrows may depend on the desired electrical characteristics of the phase change material used.FIG. 9is a cross-sectional view of a resistive heating element according to an exemplary embodiment of the present invention. In the resistive heating element9000, the narrowing width of each layer9100-9400provides an increased resistance towards the top of the resistive heating element and a decreased resistance towards the bottom of the resistive heating element. The resistive heating element may then be formed such that the top section of the resistive heating element is proximate to the phase change material. This geometry may provide a resistive gradient along the length of the resistive heating element such that the resistance towards the top of the resistive heating element is greater than the resistance towards the bottom of the resistive heating element. This resistive gradient may further focus dissipated heat towards the phase change material. WhileFIG. 9shows a cross sectional view of a plurality of concentric shell layers having a rectangular footprint, this geometry may be applied to circular or polygonal footprints as well.

According to one exemplary embodiment, each of the plurality of concentric shell layers of the resistive heating element may comprise the same material and have the same resistivity. Alternatively, various layers may be made of different materials and/or different concentrations of the same material resulting in each layer having a different resistivity. For example,FIG. 10shows a cross-sectional view of resistive heating element according to an exemplary embodiment of the present invention. The resistive heating element10000comprises a plurality of concentric shell layers10100-10500. The innermost layer10500may have a resistivity of R1. The next layer10400may have a resistivity of R2. The next layer10300may have a resistivity of R3. The next layer10200may have a resistivity of R4. The next layer10100may have a resistivity of R5. The set of resistivities may be represented by the equation R1>R2>R3>R4>R5, such that resistivity increases as layers are closer to the top and center of the resistive heating element, may be represented by the equation R1<R2<R3<R4<R5such that resistivity decreases as layers are closer to the top and center of the resistive heating element, or the set of resistivities may not conform to any regular pattern. However, as described herein, for the purposes of illustration, the example of increasing resistivity will be used. This pattern of increasing resistivity towards the top and center may be implemented for any resistive heater element geometry, including those discussed above. This formation may provide a resistive gradient along the length and width of the resistive heating element such that the resistance towards the top and center of the resistive heating element is greater than the resistance towards the bottom and outer sides of the resistive heating element. This resistive pattern may further focus dissipated heat towards the phase change material.

According to an exemplary embodiment of the present invention, a filling member may be used to further focus dissipated heat towards the phase change material. As seen inFIG. 11, a heating element11000comprises multiple concentric shell layers11100-11300. A filler member11400may be included in the top-center of the heating element1100. The filling member11400may be formed of a material having thermal properties that are suitable for focusing dissipated heat towards the phase change material. Examples of suitable filling member materials include USG, SOG, FOX, BPSG, PSG, TEOS, PE-TEOS, HDP-CVD oxide and/or nitride such as silicon nitride. The filling member11400may have a footprint that is smaller than the smallest layer11300. However, the filling member11400may also have a thickness that is larger than the thickness of the layers11100-11300.

According to an exemplary embodiment of the present invention, rather than having concentric shell members, the heater element may include a number of pillar layers as shown inFIG. 12AandFIG. 12B.FIG. 12Ais a perspective view of a heater element12000having three substantially parallel pillar layers12100-12300, however. any number of pillar layers may be used. The pillar structure ofFIG. 12Ais interposed between the electrically conductive element and the phase change material.

The pillar layer12200may include one of WNx, AlNx, TiNx, TaNx, MoNx, NbNx, TiSiNx, TiAlNx, TiBNx, ZrSiNx, WSiNx, WBNx, ZrAlNx, MoSiNx, MoAlNx, TaSiNx, or TaAlNx. The resistivity of a pillar layer may be varied by varying the content of metal. Alternatively, at least two of the pillars are made of a different material. For example, outer pillars (here,12100and12300) may be made of a first material while an inner pillar (here12200) may be made of a filling material. Examples of suitable filling materials include USG, SOG, FOX, BPSG, PSG, TEOS, PE-TEOS, HDP-CVD oxide and/or nitride such as silicon nitride. According to one exemplary embodiment of the present invention, each of the outside layers12100and12300may be formed of polisilicon or tungsten nitride while the inside layer12200may be formed of titanium aluminum nitride (TiAlN).

Each layer may have a rectangular footprint, as shown inFIG. 12A. However, other shapes are possible. For example, each layer may have a substantially triangular footprint.FIG. 12Bis a perspective view of a heater element13000having 6 parallel pillar layers13100-13600, with each pillar layer having a substantially triangular footprint. The pillar layers may be interconnected according to their geometry as is seen in bothFIG. 12AandFIG. 12B. Each parallel pillar layer may narrow towards the phase change layer as discussed above.

Accordingly, it is to be understood that any of the features discussed above and referenced inFIGS. 7 to 12Bmay be interchanged and the characteristics of any one exemplary embodiment may be modified to allow for further interchange of features from one exemplary embodiment to the next.

Exemplary embodiments of the present invention provide phase change memory devices, for example, phase change memory devices employing a heating element as discussed above with reference toFIGS. 7 to 12B. For example,FIG. 13shows a cross-sectional view of a phase change memory device according to an exemplary embodiment of the present invention. The phase change memory device may include a substrate150. A first insulating interlayer155may be formed on the substrate150. The first insulating interlayer155may be patterned and etched to form a via opening within which a conductive plug160may be formed. The plug160may be in electrical contact with a lower structure, which may include, for example, a connection to a word line (not shown).

A second insulating interlayer165may be formed on top of the first insulation interlayer155and the plug160. The second insulating interlayer may be patterned and etched to form a via opening within which a pad170may be formed. The pad170may be in electrical contact with the plug160. The pad170may have an area substantially wider than an area of the plug160. The pad170may be electrically conductive and may comprise, for example, polysilicon, metal, and/or conductive metal nitride.

An insulation structure175may be formed on the second insulation interlayer165and the pad170. The insulation structure175may serve to prevent dissipated heat from dissipating laterally. The insulation structure175may be patterned and etched to form a via opening. A first spacer180and a second spacer185may be formed within the via opening of the insulation structure175. The first and second spacer180and185may include materials having different etching selectivities. The first and second spacers180and185may he found on one or more sidewalls of the via opening of the insulation structure175. Alternatively, one or both of the spacers180and185may be omitted.

A resistive heating element may be formed within the via opening of the insulation structure175. The resistive heating element may have any of the configurations and/or geometries discussed above with respect toFIGS. 7 to 12B. The resistive heating element may comprise a lower electrode195. The lower electrode195may comprise a set of concentric shell-shaped electrode film patterns including a first lower electrode film pattern187, which is an outermost film pattern. The lower electrode195may also include a second lower electrode film pattern188, a third lower electrode film pattern189, a forth lower electrode film pattern190, a fifth lower electrode film pattern191, a sixth lower electrode film pattern192, and a seventh lower electrode film pattern193. However, the lower electrode may include any number of lower electrode film patterns. The number of lower electrode film patterns may depend on the required electrical characteristics of the phase change memory unit.

A phase change material layer may be formed over the lower electrode195. A top electrode layer may be formed over the phase change material layer. The phase change material layer and the top electrode layer may be patterned and etched into a phase change material structure196and a top electrode199, respectively. The top electrode199may comprise a first upper electrode197that may, for example, be a metal, and a second upper electrode198that may, for example, be a conductive metal nitride. The second upper electrode198may have a thickness substantially greater than a thickness of the first upper electrode197.

Each of the lower electrode film patterns187-193may have an upper portion having an upper width and a lower portion having a lower width. For each lower electrode film pattern, the upper width of the upper portion may be substantially narrower than the lower with of the lower portion. Accordingly, resistance of the entire lower electrode195may be relatively low while the resistance of the lower electrode195at the vicinity of the phase-change material may be substantially increased.

Moreover, each of the first through seventh lower electrode film patterns187-193may have a different resistance that either increases or decreases from one film pattern to the next. For example, each electrode film pattern may have a resistance within the range of about 500 μΩ·cm to about 7000 μΩ·cm.

Accordingly, the lower electrode195may be able to focus sufficient heat to obtain a desired phase change of the phase-change material layer pattern while maintaining a relatively low total set resistance of the lower electrode195. Overall heat dissipation and electrical power use may be minimized.

As discussed above, the resistance of the lower electrode195may vary from the bottom of the lower electrode195in close proximity to the pad170to the top of the lower electrode195in close proximity to the phase change structure196. This variation in resistance may occur smoothly, in discrete steps, or may otherwise be irregular. The first through seventh lower electrode film patterns187-193may each vary in composition such that the resistances of each layer may be different, for example, in the manner discussed above. For example, when each of the first through seventh lower electrode film patterns187-193include titanium aluminum nitride, the aluminum content may be gradually increased from one layer to the next to achieve the desired resistive gradient.

The phase change structure196may be comprised of, for example, a germanium-antimony-tellurium (GST) compound, for example, a GST compound doped with carbon nitrogen and/or a metal.

FIG. 14is a cross-sectional view of another phase-change memory device according to an exemplary embodiment of the present invention. Many of the features of this exemplary embodiment are similar to features of the exemplary embodiment discussed above with reference toFIG. 13. In particular, the phase-change memory device has a substrate200corresponding to the substrate150ofFIG. 13, a first insulating interlayer205corresponding to the first insulating interlayer155ofFIG. 13, a plug210corresponding to the plug160ofFIG. 13, a second insulating interlayer215corresponding to the second insulating interlayer165ofFIG. 13, a pad220corresponding to the pad170ofFIG. 13, an insulation structure225corresponding to the insulation structure175ofFIG. 13, optional first and second spacers230and235corresponding to the first and second spacers180and185ofFIG. 13, a phase change material structure252corresponding to the phase change material structure196ofFIG. 13, a top electrode255comprising a first upper electrode253and a second upper electrode254corresponding to the top electrode199comprising a first upper electrode197and a second upper electrode198ofFIG. 13.

The phase-change memory device ofFIG. 14also includes a lower electrode245that may be substantially similar to the lower electrode195ofFIG. 13but may include fewer lower electrode film patterns. For example, the lower electrode245may include a first lower electrode film pattern240, a second lower electrode film pattern241, a third lower electrode film pattern242, and a fourth lower electrode film pattern243. A filling member250may then be formed on top of the final lower electrode film pattern, here being the fourth lower electrode film pattern243. The filling member250may fill the via hole of the insulation structure225not occupied by the lower electrode film patterns240-243or the spacers230and235. The filling member may be comprised of USG, SOG, FOX, BPSG, PSG, TEOS, PE-TEOS, HDP-CVD oxide and/or nitride such as silicon nitride.

FIGS. 15 to 19show a method for fabricating the phase-change memory device ofFIG. 13. As seen inFIG. 15, a first insulating interlayer275is formed on a substrate270. A plug280is formed on the substrate270, for example, by etching an opening within the first insulating interlayer275and forming the plug280within the opening. A second insulating interlayer285is formed on the surface of the first insulating interlayer275and the plug280. A contact hole290is formed within the second insulating interlayer285exposing the plug280.

As seen inFIG. 16, a pad295is formed in the contact hole290. Then, a third insulating interlayer300and a sacrificial layer305are formed over the second insulating interlayer285and the pad295. In forming the third insulating interlayer300and a sacrificial layer305, the third insulating interlayer300may be formed first and then the sacrificial layer305may be formed on top of the third insulating interlayer300. The sacrificial layer305and the third insulating interlayer300may be etched to form an opening306. The opening306may expose the pad295.

As seen inFIG. 17, a first preliminary spacer315may be formed on one or more sidewalls of the opening306. A second preliminary spacer320may be formed on the first preliminary spacer315. A lower electrode340may be formed within the opening306. The lower electrode340may comprise a set of lower electrode films331-337. For example, an outer-most lower electrode film331may be formed over the second preliminary spacer320. Additional lower electrode films332-337may be sequentially formed over the outer-most lower electrode film331. Here, the lower electrode film337represents an innermost electrode film, however, there may be any number of lower electrode films, as discussed above. The lower electrode films may have one or more of the properties discussed above. For example, each of the lower electrode films may have a lower portion substantially wider than an upper portion thereof.

As seen inFIG. 18, a first chemical-mechanical planarization (CMP) process may be used to reduce the sacrificial layer305to a reduced sacrificial layer308, to reduce the lower electrode340and its constituent lower electrode films331-337to a reduced lower electrode350and constituent reduced lower electrode films341-347, and to reduce the first and second preliminary spacers315and320to reduced first and second preliminary spacers317and322.

As seen inFIG. 19, the reduced sacrificial layer308may be removed, for example, by a wet etching process or a dry etching process. Following the removal of the reduced sacrificial layer308, the reduced lower electrode films341-347of the reduced lower electrode350along with the reduced first and second preliminary spacers315and320may protrude above the surface of the third insulating interlayer300. A second CMP process may then be performed to planarize the surface of the third insulating interlayer300, the first and second preliminary spacers317and322and the reduced lower electrode350and constituent reduced lower electrode films341-347. From these planarized surfaces, first and second spacers319and324and a lower electrode370with constituent lower electrode layers361-367are formed.

FIGS. 20 to 23show a method for fabricating the phase-change memory device ofFIG. 14according to an exemplary embodiment of the present invention. As seen inFIG. 20, a first insulating interlayer405is formed on a substrate400. A plug410is formed on the substrate, for example, by etching an opening within the first insulating interlayer405and forming the plug410within the opening. A second insulating interlayer415is formed on the surface of the first insulating interlayer405and the plug410. A contact hole is formed within the second insulating interlayer415exposing the plug410and a pad420is formed within the contact hole contacting the plug410. A third insulating interlayer425is formed on top of the second insulating interlayer415and the pad420. A sacrificial layer430is formed on top of the third insulating interlayer425.

As seen inFIG. 21, an opening may be formed through the sacrificial layer430and the third insulating interlayer425exposing the pad420. A first preliminary spacer435and a second preliminary spacer440may be formed within the opening of the sacrificial layer430and the third insulating interlayer425. A lower electrode450may be formed within the opening. The lower electrode450may comprise a set of lower electrode films445-448. For example, an outer-most lower electrode film445may be formed over the second preliminary spacer440. Additional lower electrode films446-448may be sequentially formed over the outer-most lower electrode film445. Here, the lower electrode film448represents an innermost electrode film, however, there may be any number of lower electrode films, as discussed above. The lower electrode films may have one or more of the properties discussed above. For example, each of the lower electrode films may have a lower portion substantially wider than an upper portion thereof. A filling layer445may be formed over the lower electrode450. The filling layer445may include, for example, silicon nitride or silicon oxynitride.

As seen inFIG. 22, a first CMP process may be used to reduce the sacrificial layer430to a reduced sacrificial layer433, to reduce the lower electrode450and its constituent lower electrode films445-448to a reduced lower electrode470and constituent reduced lower electrode films466-469, to reduce the first and second preliminary spacers435and440to reduced first and second preliminary spacers460and465, and to reduce the filling layer455to a reduced filling layer475.

As seen inFIG. 23, the reduced sacrificial layer433may be removed, for example, by a wet etching process or a dry etching process. Following the removal of the reduced sacrificial layer433, the reduced lower electrode films466-469of the reduced lower electrode470along with the reduced first and second preliminary spacers460and465and the reduced filling layer474may protrude above the surface of the third insulating interlayer425. A second CMP process may then be performed to planarize the surface of the third insulating interlayer425, the first and second preliminary spacers,460and465, the reduced lower electrode470and constituent reduced lower electrode films466-469and the reduced filling layer455. From these planarized surfaces, first and second spacers480and485, a lower electrode490with constituent lower electrode layers486-489, and a filling member495are formed.

According to exemplary embodiments of the present invention, lower electrode layers may be formed by an atomic layer deposition (ALD) process.FIG. 24shows a method for forming lower electrode layers according to an ALD process according to an exemplary embodiment of the present invention. First, a substrate is loaded into a reaction chamber (Step S24100). Next, a titanium source gas is applied to the substrate to form a first chemisorption layer (Step S24200). The titanium source gas may, for example, include titanium tetrachloride TiCl4. The titanium source gas may be applied, for example, under process conditions such as about 400° C. to about 600° C., about 0.5 Torr to about 5.0 Torr, and/or at a flow rate of titanium source gas of about 20 sccm/sec. The titanium source gas may be provided onto the substrate together with a carrier gas, for example, argon (Ar) or helium (He). The reaction chamber may then be purged of the carrier gas (Step S24300), for example, by evacuation and/or by the introduction of additional argon (Ar) or helium (He). Then, a first nitrogen source gas is applied to the first chemisorption layer thereby forming a first composite layer from the first chemisorption layer (Step S24400). In this step, the titanium of the first chemisorption layer may react with the nitrogen of the nitrogen source gas. The first nitrogen source gas may include ammonia (NH3) gas, a nitric oxide (NO) gas, a nitrous oxide (N2O) gas, and/or a nitrogen (N2) gas. The nitrogen source gas may be applied, for example, under process conditions such as about 400° C. to about 600° C., about 0.5 Torr to about 5.0 Torr, and/or at a flow rate of titanium source gas of about 425 sccm/sec. The first nitrogen source gas may then be purged (Step S24500), for example, in the manner discussed above. Next, an aluminum source gas is applied to the first composite layer so that a second chemisorption layer including aluminum is formed on the first composite layer (Step S24600). The aluminum source gas may include, for example, trimethylaluminum (Al(CH3)3). The aluminum source gas may then be purged (Step S24700), for example, in the manner discussed above. A second nitrogen source gas is then applied to the second chemisorption layer so that a second composite layer including aluminum nitride is formed on the second chemisorption layer (Step S24800). A titanium aluminum nitride layer may thereby be formed. The second nitrogen source gas may include an ammonia gas, a nitric oxide gas, a nitrous oxide gas, and/or a nitrogen gas. The second nitrogen source gas may be applied, for example, under process conditions such as about 400° C. to about 600° C., about 0.5 Torr to about 5.0 Torr, and/or at a flow rate of titanium source gas of about 300 sccm/sec to about 500 sccm/sec for about 1.0 sec to about 2.0 sec. Thereafter, the second nitrogen source gas may be purged (Step S24900), for example, in the manner discussed above.

The above steps may be repeated to form each lower electrode layer. The resistivity of each lower electrode layer may be controlled by varying the chemical composition/concentration of each source gas step and/or by varying the processing conditions. For example, a prolonged exposure to and/or an increased concentration/pressure of the aluminum source gas may result in a lower electrode layer with an increased aluminum concentration and a reduced resistance.FIG. 25shows this dependency by plotting the resistance of a resulting lower electrode layer as a function of the aluminum content of the layer it. In this figure, line “I” represents the content of aluminum in the titanium aluminum nitride layers and the line “II” represents a variation of the resistance of the titanium aluminum nitride layers.

After the formation of the lower electrode, for example, in accordance with one or more of the exemplary embodiments described above, the composition of the lower electrode may vary as a function of depth.FIG. 26is a graph showing an example composition of the lower electrode as a function of depth according to an exemplary embodiment of the present invention. The vertical axis represents the concentration of a particular element by percentage while the horizontal axis represents the depth (thickness) where the particular concentration may be found. The vertical axis, representing a percentage, ranges from 0 to 100 while the horizontal axis, representing a distance from the center of the lower electrode to the outer surface ranges from 0 Å to 700 Å. Each curve represents a particular element. For example, curve “IX” represents silicon, “X” represents nitrogen, “XI” and “XIV” represent oxygen, and “XIII” represents aluminum. Using this chart, the composition of a lower electrode according to an exemplary embodiment of the present invention may be analyzed. For example, as can be seen from the curve XIII, the aluminum content is highest (about 55%) at the center of the lower electrode (0 Å) and is lowest at the periphery of the lower electrode, approaching 0% at approximately 500 Å away from the center of the lower electrode.

Exemplary embodiments of the present invention may achieve desirable reset currents at desirable set resistances.FIG. 27is a graph showing reset currents and set resistances of lower electrodes of phase-change memory units relative to specific resistances of the lower electrodes. In this graph, the vertical axis represents reset current in milliamps and the horizontal axis represents set resistance in Ohms. The diamond-shaped plots “♦” represent the reset current and set resistance of a phase-change memory unit including a lower electrode having a specific resistance of about 500 μΩ·cm. The square-shaped plots “▪” represent the reset current and set resistance of a phase-change memory unit including a lower electrode having a specific resistance of about 2000 μΩ·cm. The triangle-shaped plots “▴” represent the reset current and set resistance of a phase-change memory unit including a lower electrode having a specific resistance of about 3000 μΩ·cm. The “x” shaped plots represent the resent current and set resistance of a phase-change memory unit including a lower electrode having a specific resistance of about 5000 μΩ·cm. The circle-shaped plots “●” represent the reset current and the set resistance of a lower electrode having a specific resistance that varies within the range of about 1000 μΩ·cm to about 5000 μΩ·cm in accordance with an exemplary embodiment of the present invention.

The above specific embodiments are illustrative, and many variations can be introduced on these embodiments without departing from the spirit of the disclosure or from the scope of the appended claims. For example, elements and/or features of different exemplary embodiments may be combined with each other and/or substituted for each other within the scope of this disclosure and appended claims.