Method of fabricating array substrate for IPS-mode LCD device has a shorter processing time and low error rate without an increase in fabrication and production costs

Provided is an array substrate for an IPS-mode LCD device and method of fabricating the same that prevents a problem referred to as wavy noise. The IPS-mode LCD device and method have a shorter processing time and low error rate without an increase in fabrication and production costs.

The present application claims the benefit of Korean Patent Application No. 2005-0133525 filed in Korea on Dec. 29, 2005, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to an array substrate for an in-plane switching mode (IPS-mode) LCD device that prevents wavy noise and a method of fabricating the same.

2. Discussion of the Related Art

A related art liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite alignment direction as a result of their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal molecules. In other words, as the intensity or direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light is refracted based on the orientation of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules, images can be displayed by controlling light transmissivity.

Recently, since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images, the AM-LCD device has been widely used.

The AM-LCD device includes an array substrate, a color filter substrate and a liquid crystal layer interposed therebetween. The array substrate may include a pixel electrode and the TFT, and the color filter substrate may include a color filter layer and a common electrode. The AM-LCD device is driven by an electric field between the pixel electrode and the common electrode. However, since the AM-LCD device uses a vertical electric field, the AM-LCD device has a bad viewing angle.

An IPS-mode LCD device may be used to resolve the above-mentioned problem.FIG. 1is a cross-sectional view of a related art IPS-mode LCD device. As shown inFIG. 1, the array substrate and the color filter substrate are separated and face each other. The array substrate includes a first substrate10, a common electrode17and a pixel electrode30. Though not shown, the array substrate may include a TFT, a gate line and a data line. The color filter substrate includes a second substrate9, a color filter layer (not shown), and so on. A liquid crystal layer11is interposed between the first substrate10and the second substrate9. Since the common electrode17and the pixel electrode30are formed on the first substrate10on a same level, a horizontal electric field “L” between the common and pixel electrodes17and30is formed.

FIGS. 2A and 2Bare cross-sectional views showing turned on/off conditions of the related art IPS-mode LCD device. As shown inFIG. 2A, when the voltage is applied to the IPS-mode LCD device, liquid crystal molecules11aabove the common electrode17and the pixel electrode30are unchanged. But, liquid crystal molecules11bbetween the common electrode17and the pixel electrode30are horizontally arranged due to the horizontal electric field “L”. Since the liquid crystal molecules are arranged by a horizontal electric field, the IPS-mode LCD device has a characteristic of a wide viewing angle.FIG. 2Bshows a condition when the voltage is not applied to the IPS-mode LCD device. Because a electric field is not formed between the common and pixel electrodes17and30, the arrangement of liquid crystal molecules11is not changed.

FIG. 3is a plan view of an array substrate of the IPS-mode LCD device according to the related art. As shown inFIG. 3, the array substrate includes a substrate (not shown), a gate line43, a data line60, and a common line47. The gate line43is formed along a first direction of the substrate on the substrate. The data line60crosses the gate line43such that the gate and data lines43and60define a pixel region “P” on the substrate. The common line47is parallel to the gate line43. The common line47also crosses the data line60.

A TFT “Tr”, a switching element, is formed at a crossing portion of the gate and data lines43and60. The TFT “Tr” includes a gate electrode45, a semiconductor layer51, and source and drain electrodes53and55. The gate electrode45extends from the gate line43into the pixel region “P”. The source electrode53extends from the data line60, and the source and drain electrodes53and55are separated from each other on the semiconductor layer51. Moreover, a plurality of pixel electrodes70and a plurality of common electrodes49are formed on the substrate in the pixel region “P”. The plurality of pixel electrodes70extend from a pixel connection line68, which contacts the drain electrode55through a drain contact hole66. The plurality of common electrodes49extend from the common line47and are alternately arranged with the plurality of pixel electrodes70. Ends of each pixel electrode are connected to each other such that the connected portion is defined as a second storage electrode69. The second storage electrode69overlaps the common line47, and a portion of the common line47overlapped with the second storage electrode69is defined as a first storage electrode48. The first electrode69and second storage electrode48compose a storage capacitor StgC.

FIG. 4is cross-sectional view of a portion taken along the line IV-IV ofFIG. 3. As shown inFIG. 4, the array substrate for the IPS-mode LCD device according to the related art includes the substrate40, the gate electrode45, the semiconductor layer51, the source and drain electrodes53and55, the plurality of pixel electrodes70, and the plurality of common electrodes49. The array substrate is fabricated through the following steps. The gate line43(ofFIG. 3), the gate electrode45, the common line47(ofFIG. 3) and the plurality of common electrodes49are formed on the substrate40by depositing and patterning a first metal material through a first mask process. Next, a gate insulating layer50is formed on the substrate40including the gate line43(ofFIG. 3), the gate electrode45, the common line47(ofFIG. 3) and the plurality of common electrodes49. Then, the semiconductor layer51, which includes an intrinsic amorphous silicon layer51aand an impurity-doped amorphous silicon layer51b, is formed on the gate insulating layer50by depositing and patterning intrinsic amorphous silicon and impurity-doped amorphous silicon through a second mask process.

And the data line60(ofFIG. 3), the source electrode53and the drain electrode55are formed on the semiconductor layer51and the gate insulating layer50by depositing and patterning a second metal material through a third mask process. As mentioned above, the source electrode53extends from the data line60, and the source and drain electrodes53and55are separated from each other.

Next, a passivation layer63including a drain contact hole66is formed on the source and drain electrodes53and55and the gate insulating layer50by depositing and patterning an insulating material through a fourth mask process. As mentioned above, the drain contact hole66exposes the drain electrode55.

Finally, the pixel connection line68and the plurality of pixel electrodes70are formed on the passivation layer63by depositing and patterning a transparent conductive material through a fifth mask process. The pixel connection line68contacts the drain electrode55through the drain contact hole66such that the plurality of pixel electrodes70are electrically connected to the drain electrode55. The plurality of pixel electrodes70are alternately arranged with the plurality of common electrodes49.

As discussed above, the array substrate for the IPS-mode LCD device according to the related art is fabricated through five mask processes. Accordingly, a processing time, an error rate and production costs are increased, and a production yield is decreased.

To resolve these problems, a fabricating process using four mask processes is suggested. However, since the source and drain electrodes do not cover both ends of the semiconductor layer, a problem, referred to as wavy noise, is caused. The wavy noise means that when the IPS-mode LCD device is turned on or off, a wave pattern appears on a liquid crystal panel.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an array substrate for an IPS-mode LCD device and a method of fabricating the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.

An advantage of the present invention is to provide an array substrate for an IPS-mode LCD device and a method of fabricating the same that have a short processing time and low error rate without an increase in a fabrication process and a production cost.

Another advantage of the present invention is to provide an array substrate for an IPS-mode LCD device and a method of fabricating the same that prevents a problem referred to as wavy noise.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, an array substrate for an IPS-mode LCD device comprises a substrate having a switching region and a pixel region; a gate line on the substrate; a gate electrode formed in the switching region and extending from the gate line; a common line substantially parallel to the gate line and separated from the gate line; first and second common electrodes extending from the common line into the pixel region and separated from each other; a gate insulating layer on the gate line, the common line and the first and second common electrodes, wherein the gate insulating layer has a common line contact hole exposing the common line; a data line crossing the gate line to define the pixel region on the gate insulating layer; a semiconductor layer corresponding to the gate electrode on the gate insulating layer; a source electrode and a drain electrode separated from each other on the semiconductor layer, wherein the source electrode extends from the data line; a plurality of pixel electrodes between the first and second common electrodes, wherein the plurality of pixel electrodes are separated from each other and substantially parallel to the first and second common electrodes, and each of the plurality of pixel electrodes extends from the drain electrode; and a plurality of third common electrodes formed on the gate insulating layer, wherein the plurality of third common electrodes are connected to the common line through the common line contact hole and alternately arranged with the plurality of pixel electrodes, wherein the data line, the plurality of pixel electrodes and the plurality of third common electrodes are formed on a same layer and with a same material as one another.

In another aspect of the present invention, a method of fabricating an array substrate for an IPS-mode LCD device comprises forming a gate line, a gate electrode, a first common line, and first and second common electrodes on a substrate having a switching region and a pixel region using a first mask process, wherein the gate electrode extends from the gate line and is formed in the switching region, the first common line is substantially parallel to the gate line, and the first and second common electrodes extend from the first common line into the pixel region; sequentially forming a gate insulating layer, an intrinsic amorphous silicon layer and an impurity-doped amorphous silicon layer on the gate line, the gate electrode, and the first and second common electrodes; forming a common line contact hole in the gate insulating layer, an active layer and an impurity-doped amorphous silicon pattern by patterning the gate insulating layer, the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer using a second mask process, wherein the common line contact hole exposes the first common line, the active layer corresponds to the gate electrode on the gate insulating layer and the impurity-doped amorphous silicon pattern has a same shape as the active layer on the active layer; and forming a data line, a source electrode, a drain electrode, a plurality of pixel electrodes and a plurality of third common electrodes on the gate insulating layer, the active layer and the impurity-doped amorphous silicon pattern using a third mask process, wherein the data line crosses the gate line to define the pixel region, the source electrode extends from the data line and contacts the impurity-doped amorphous silicon pattern, and the drain electrode is separated from the source electrode and contacts the impurity-doped amorphous silicon pattern, wherein the plurality of pixel electrodes are separated each other and substantially parallel to the first and second common electrodes, and each of the plurality of electrodes extends from the drain electrode, and wherein the plurality of third common electrodes contact the first common line through the common line contact hole and are alternately arranged with the plurality of pixel electrodes.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

FIG. 5is a plan view showing a pixel region of an array substrate for an IPS-mode LCD device according to the present invention. As shown inFIG. 5, the array substrate includes a substrate (not shown), a gate line113, a data line146, a pixel electrode160, first and second common lines118and121, first, second and third common electrodes124,127and165and a TFT “Tr”. The gate line113is formed along a first direction of the substrate on the substrate. The data line146crosses the gate line113such that a pixel region “P” is defined on the substrate. The data line146has a substantially zigzag shape in an exemplary embodiment, but the data line146may have a substantially linear shape and so on. A gate pad electrode129, which connects the gate line113and an external gate driving circuit (not shown), is formed at an end of the gate line113in a gate pad region “GPA”, and a data pad electrode130, which connects the data line146and an external data driving circuit (not shown), is formed at an end of the data line146in a data pad region “DPA”. The data line146is connected to the data pad electrode130through a data link line123and a data link line contact hole171. It is characteristic that the gate pad electrode129and the data pad electrode130are formed on a same layer as each other with a same material as each other.

The first and second common lines118and121are formed on the substrate. The first and second common lines118and121are separated from each other and substantially parallel to each other. The first and second common lines118and121with the first and second common electrodes124and127surround an edge of the pixel region “P”. One end of the first and second common electrodes124and127are connected to the first common line118, and the other end of the first and second common electrodes124and127are connected to the second common line121. In other words, the first and second common lines118and121are disposed in upper and lower sides of the pixel region “P”, and the first and second common electrodes124and127are disposed in right and left sides of the pixel region “P” substantially parallel to the data line146. In addition, since a common connection line125connects the first and second common lines118and121, two to five common line pad electrodes131, which is less than a number of the first and second common lines118and121are formed between the gate pad electrodes129or of only two portions adjacent to the first and second gate pad electrodes129to apply a common voltage to the first and second common line118and121formed on an entire substrate.

The TFT “Tr” is formed at a switching region (not shown), that is a crossing portion of the gate and data lines113and146. The TFT “Tr” includes the gate electrode115, the semiconductor layer145the source electrode150and the drain electrode153. In an exemplary embodiment according to the present invention, the source electrode150has a “U” shape, and the drain electrode153is inserted into the mouth of the “U” shape of the source electrode150with the drain electrode153separated from the drain electrode150. However, in other embodiments of the present invention, the source and drain electrodes150and153may have other shapes.

The pixel electrode160including a first pixel electrode160aand a second pixel electrode160bis electrically connected to the drain electrode153. The pixel electrode160extends from the drain electrode153into the pixel region “P” and is substantially parallel to the first and second common electrodes124and127. The third common electrode165is formed between the first and second pixel electrodes160aand160band is connected to the first common line118through a common line contact hole139. The common line contact hole139may have first and second common line contact holes139aand139b. The third common electrode165is formed on a same layer as the first and second pixel electrodes160aand160bwith a same material as the first and second pixel electrodes160aand160b. A common pad contact hole136is formed at one end of the first common line118. In an exemplary embodiment of the present invention, the pixel electrode160has two pixel electrodes, that is the first and second pixel electrodes160aand160b. However, in another embodiment, the pixel electrode160may have multiple pixel electrodes, and then the third common electrode165also has several third common electrodes. When the third common electrode165includes the several third common electrodes, the several third common electrodes are alternately arranged with the multiple pixel electrodes. A horizontal electric field is generated between the first common electrode124and the first pixel electrode160a, between the pixel electrode160and the third common electrode165, and between the second pixel electrode160band the second common electrode127.

A portion connecting the pixel electrode160and the drain electrode153overlaps the second common line121. The second common line121overlapped with the portion is defined as a first storage electrode122, and the portion is defined as a second storage electrode156. The first storage electrode122, the second storage electrode156and a gate insulating layer (not shown) interposed between the first and second storage electrodes122and156compose a storage capacitor (not shown).

FIG. 6is a cross-sectional view taken along the line VI-VI ofFIG. 5,FIG. 7is a cross-sectional view taken along the line VII-VII ofFIG. 5,FIG. 8is a cross-sectional view taken along the line VIII-VIII ofFIG. 5, andFIG. 9is a cross-sectional view taken along the line IX-IX ofFIG. 5. The switching region “TrA”, in which the TFT “Tr” is formed, a storage region “StgA”, in which the storage capacitor “StgC” are defined in the pixel region. And the gate pad region “GPA” (ofFIG. 5) and the data pad region “DPA” are defined at a periphery of the pixel region “P”.

As shown inFIGS. 6 to 9, the gate line113is formed on the substrate110. The gate line113in the switching region “TrA” functions as the gate electrode115in an exemplary embodiment of the present invention, but the gate electrode115may be formed to extend from the gate line113into the pixel region “P”. The first and second common lines118and121, which are substantially parallel to each other, are formed on the substrate110and are substantially parallel to the gate line113. The gate pad electrode129(ofFIG. 5) is formed at the end of the gate line113in the gate pad region “GPA” (ofFIG. 5). The data pad electrode130is formed in the data pad region “DPA” and has a same shape as the gate pad electrode129(ofFIG. 5). And a data link line123(ofFIG. 5) contacts the data pad electrode130through a data pad contact hole137and extends to an end of the data line146.

In the pixel region “P”, the first and second common electrodes124and127extend from the first and second common lines118and121. One end of the first and second common electrodes124and127is connected to the first common line118, and the other end of the first and second common electrodes124and127is connected to the second common line121. The first and second common lines118and121, and the first and second common electrodes124and127surround an edge of the pixel region “P”. In the storage region “StgA”, the second common line121functions as the first storage electrode122.

The gate line113, the first and second common lines118and121, the first and second common electrodes124and127, the gate pad electrode129(ofFIG. 5), and the data pad electrode130may have a double-layered structure or a triple-layered structure. More particularly, the gate line113, the first and second common lines118and121, the first and second common electrodes124and127, the gate pad electrode129(ofFIG. 5), and the data pad electrode130include a first metal layer113a,118a,121a,124a,127aand130a, respectively, and a transparent conductive layer113b,118b,121b,124b,127band130bon the corresponding first metal layer113a,118a,121a,124a,127aand130a. The first metal layer113a,118a,121a,124a,127aand130ais formed of a first metal that has low resistance properties, and the transparent conductive layer113b,118b,121b,124b,127band130bis formed of a transparent conductive metal that has anti-rust properties. The first metal may include, for example, aluminum, aluminum alloy, copper, chrome and molybdenum. The transparent conductive metal may include, for example, indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). Moreover, a second metal layer (not shown) may be formed of a second metal between the first metal layer113a,118a,121a,124a,127aand130aand the transparent conductive layer113b,118b,121b,124b,127band130bsuch that the gate line113, the first and second common lines118and121, the first and second common electrodes124and127, the gate pad electrode129(ofFIG. 5), and the data pad electrode130have the triple-layered structure. When the first metal is aluminum or aluminum ally, the second metal may be molybdenum.

The gate insulating layer135is formed on the gate line113, the first and second common lines118and121, and the first and second common electrodes124and127. The gate insulating layer135includes the common line contact hole139, the data link line contact hole171(ofFIG. 5), a gate pad contact hole138(ofFIG. 5) and a data pad contact hole137. The common line contact hole139, which has a first and second common line contact holes139aand139b, exposes the first common line118, and the data link line contact hole exposes the data link line123(ofFIG. 5). The gate pad contact hole138(ofFIG. 5) and the data pad contact hole137expose the gate pad electrode129(ofFIG. 5) and the data pad electrode130, respectively. In an exemplary embodiment of the present invention, the common line contact hole139has two common line contact holes, but the common line contact hole139may have one or more than two common line contact holes. The semiconductor layer145includes an active layer141, a first ohmic contact layer144aand a second ohmic contact layer144b. The active layer141is made of an intrinsic amorphous silicon, and the first and second ohmic contact layers144aand144bare made of an impurity-doped amorphous silicon. The first and second ohmic contact layers144aand144bare disposed on the active layer141and separated from each other.

On the gate insulating layer135and the semiconductor layer145, the data line146, the source electrode150and the drain electrode153are formed. The data line146crosses the gate line113such that the pixel region “P” is defined on the substrate110. The source electrode150extends from the data line146and is disposed on the first ohmic contact layer144a. The drain electrode153is separated from the source electrode150and disposed on the second ohmic contact layer144b. The drain electrode153extends into the storage area “StgA”. The source electrode150covers one end of the first ohmic contact layer144aand the active layer141, and the drain electrode153covers an end of the second ohmic contact layer144band the other end of the active layer141.

Though not shown, the data line146is connected to the data pad electrode130in the data pad region “DPA” through the data link line123(ofFIG. 5), the data link line contact hole171(ofFIG. 5) and the data pad contact hole137. InFIG. 7, the second storage electrode156in the storage region “StgA” extends from the drain electrode153and overlaps the first storage electrode122. The first storage electrode122, the second storage electrode156and the gate insulating layer135compose the storage capacitor “StgC” in the storage region “StgA”.

The pixel electrode160including the first and second pixel electrodes160aand160bis formed on the gate insulating layer135. The pixel electrode160extends from the second storage electrode156into the pixel region “P” such that the pixel electrode160is electrically connected to the drain electrode153. The first and second pixel electrodes160aand160bare separated from each other and substantially parallel to the first and second common electrodes124and127, respectively. The third common electrode165is formed between the first and second pixel electrodes160aand160band connected to the first common line118through the first and second contact holes139aand139b.

Sine the above-mentioned array substrate for the IPS-mode LCD device is fabricated through three mask processes, a process time and a production cost decreases. Moreover, since the source and drain electrodes150and153cover both ends of the semiconductor layer145, the array substrate does not have a problem of wavy noise.

FIGS. 10A to 10Hare cross-sectional views showing processes of fabricating a portion taken along the line VI-VI ofFIG. 5,FIGS. 11A to 11Hare cross-sectional views showing processes of fabricating a portion taken along the line VII-VII ofFIG. 5,FIGS. 12A to 12Hare cross-sectional views showing processes of fabricating a portion taken along the line VIII-VIII ofFIG. 5, andFIGS. 13A to 13Hare cross-sectional views showing processes of fabricating a portion taken along the line IX-IX ofFIG. 5.

FIGS. 10A,11A,12A and13A describe a first mask process. As shown inFIGS. 10A,11A,12A and13A, the first and second common electrodes124and127, the gate line113, the first and second common lines118and121, and the data pad electrode130are formed on the substrate110by depositing and patterning the first metal and the transparent conductive metal through the first mask process. The first and second common electrodes124and127, the gate line113, and the first and second common lines118and121are formed along a side of the pixel region “P”, and the data pad electrode130is formed in the data pad region “DPA”. At the same time, the gate pad electrode129(ofFIG. 5) is formed in the gate pad region “GPA”, and the data link line123(ofFIG. 5), which is connected to the data pad electrode130and the data line146, is formed in the data pad region “DPA”. The first and second common electrodes124and127, the gate line113, the first and second common lines118and121, the data pad electrode130, and the gate pad electrode129(ofFIG. 5) have a double-layered structure. The first and second common electrodes124and127extend from the first and second common lines118and121into the pixel region “P”, and the first and second common electrodes124and127, and the first and second common lines118and121surround the pixel region “P”. The gate line113is formed along a side of the pixel region “P” and functions as the gate electrode115in the switching region “TrA”. The second common line121functions as the first storage electrode122in the storage region “StgA”. The gate pad electrode129(ofFIG. 5) is formed at the end of the gate line113in the gate pad region “GPA” (ofFIG. 5), and the data pad electrode130is formed in the data pad region “DPA” with connected to the data line146(ofFIG. 5).

In particular, the first common electrode124has a first metal layer124aand the transparent conductive layer124b, and the second common electrode127has a first metal layer127aand a transparent conductive layer127b. The gate line113has the first metal layer113aand the transparent conductive layer113b. The first common line118has the first metal layer118aand the transparent conductive layer118b, and the second common line121has the first metal layer121aand the transparent conductive layer121b. The data pad electrode130has the first metal layer130aand the transparent conductive layer130b, and the gate pad electrode129(ofFIG. 5) also has the first metal layer (not shown) and the transparent conductive layer (not shown). As mentioned above, the first metal may include aluminum, aluminum alloy, copper, chrome and molybdenum, and the transparent conductive metal may include indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). The first metal has the low resistance, and the transparent conductive metal has anti-rust properties. The second metal layer (not shown) may be further formed between the first metal layer113a,118a,121a,124a,127aand130aand the transparent conductive layer113b,118b,121b,124b,127band130bsuch that the gate line113, the first and second common lines118and121, the data pad electrode130, and the gate pad electrode129(ofFIG. 5) have the triple-layered structure. The second metal layer (not shown) may be made of molybdenum.

As shown inFIGS. 10B,11B,12B and13B, the gate insulating layer135is formed on the substrate110including the gate line113, the first and second common lines118and121, the data pad electrode130, and the gate pad electrode129(ofFIG. 5) by depositing an inorganic insulating material. The inorganic insulating material may be silicon oxide (SiO2) or silicon nitride (SiNx). The intrinsic amorphous silicon layer140and the impurity-doped amorphous silicon layer143are formed on the gate insulating layer135by sequentially depositing the intrinsic amorphous silicon and the impurity-doped amorphous silicon. Then, a photoresist (PR) layer181is formed on the impurity-doped amorphous silicon layer143by depositing photoresist. In this exemplary embodiment, the photoresist is a positive type that a portion irradiated is removed. However, photoresist of a negative type may be used.

A mask191is disposed over the PR layer181. As illustrated inFIGS. 11B and 12B, the mask191has a transmissive area “TA”, a blocking area “BA”, and a half-transmissive area “HTA”. The half-transmissive area “HTA” has a transmittance that is smaller than that of the transmissive area “TA” and greater than that of the blocking area “BA”. The transmissive area “TA” may have a transmittance of about 100 percentage, and the blocking area “BA” may have a transmittance of about 0 percentage. PR patterns having various heights can be obtained by using the above-mentioned mask. The transmissive area “TA” corresponds to a symmetric portion from the center of the first common line118shown inFIG. 12Band a center of the data pad electrode130inFIG. 13B. The first and second common line contact holes139aand139b(ofFIG. 5) are formed in the symmetric portions, and the data pad contact hole137(ofFIG. 5) is to be formed in the center of the data pad electrode130. The blocking area “BA” corresponds to the switching area “TrA”, and the half-transmissive area “HTA” corresponds to other portions. The semiconductor layer145is to be formed in a portion corresponding to the blocking area “BA”. Though not shown, the transmissive area “TA” corresponds to a center of the gate pad electrode, in which the gate pad contact hole is to be formed.

As show inFIGS. 10C,11C,12C and13C, a first PR pattern181aand a second PR pattern181bare formed on the impurity-doped amorphous silicon layer143by exposing and developing the PR layer181using the mask191. The first PR pattern181acorresponding to the blocking area “BA” has a first height, and the second PR pattern181bcorresponding to the half-transmissive area “HTA” has a second height smaller than the first height of the BA. The impurity-doped amorphous silicon layer143corresponding to the transmissive area “TA” is exposed between the second PR patterns181b.

Next, as shown inFIGS. 10D,11D,12D and13D, the first and second common line contact hole139aand139bin the first common line118, the gate pad contact hole138(ofFIG. 5) in the gate pad electrode129(ofFIG. 5), and the data pad contact hole137in the data pad electrode130are formed by sequentially removing the impurity-doped amorphous silicon layer143exposed between the second PR patterns181b, the intrinsic amorphous silicon layer140and the gate insulating layer135. Though not shown, at the same time, the data link line contact hole171(ofFIG. 5) is formed at an end of the data link line123(ofFIG. 5). The first and second common line contact holes139aand139bexpose the first common line118, respectively, and the gate pad contact hole138(ofFIG. 5) exposes the gate pad electrode129(ofFIG. 5). The data pad contact hole137exposes the data pad electrode130, and the data link line contact hole171(ofFIG. 5) exposes the data link line123(ofFIG. 5).

Since the gate pad electrode129(ofFIG. 5), the data pad electrode130, the first common line118, and the data link line123(ofFIG. 5) have an uppermost layer of the transparent conductive metal, there is no problem of rust. Moreover, since the first and second common line contact holes139aand139bare covered with the liquid crystal molecules, the problem of rust does not occur.

As shown inFIGS. 10E,11E,12E and13E, the second PR pattern181b(ofFIGS. 10D,11D,12D and13D) is removed by ashing the first and second PR patterns181aand181b, thereby exposing the impurity-doped amorphous silicon layer143below the second PR pattern181b. The first PR pattern181in the switching region “TrA” has a smaller height than the first height.

As shown inFIGS. 10F,11F,12F and13F, the impurity-doped amorphous silicon layer143exposed by ashing and the intrinsic amorphous silicon layer140are sequentially removed by dry etching such that the gate insulating layer135, which corresponds to the intrinsic amorphous silicon layer140removed by dry etching, is exposed. Accordingly, the impurity-doped amorphous silicon layer143exposed by ashing and the intrinsic amorphous silicon layer140remain in the switching region “TrA”, and thereby being the ohmic contact layer144and the active layer141, respectively. Then, the first PR pattern181ais removed from the ohmic contact layer144.

As shown inFIGS. 10G,11G,12G and13G, the data line146on the gate insulating layer135, the source electrode150on the ohmic contact layer144and the drain electrode153on the ohmic contact layer144are formed by depositing and patterning a metal layer (not shown) through a third mask process. The metal layer (not shown) may be made of molybdenum. The data line146crosses the gate line113such that the pixel region “P” is defined. The data line146contacts the data link line123(ofFIG. 5) through the link line contact hole171(ofFIG. 5). The source electrode150extends from the data line146into the switching region “TrA”, and the drain electrode153is separated from the source electrode150such that the ohmic contact layer144is exposed between the source and drain electrodes150and153. The drain electrode153extends into the storage region “StgA” such that the drain electrode153overlaps the first storage electrode122, thereby functioning as the second storage electrode156. The first storage electrode122, the second storage electrode156and the gate insulating layer135interposed between the first storage electrode122and the second storage electrode156compose the storage capacitor “StgC”.

At the same time, the pixel electrode160including the first pixel electrode160aand the second pixel electrode160bis formed in the pixel region “P”. The first and second pixel electrodes160aand160bextend from the second storage electrode156such that the first and second pixel electrodes160aand160belectrically contact the drain electrode153. The first and second pixel electrodes160aand160bare substantially parallel to the first and second common electrodes124and127, respectively. Furthermore, the third common electrode165is formed in the pixel region “P”. The third common electrode165between the first and second pixel electrodes160aand160bcontacts the first common line118through the first and second common line contact holes139aand139band is substantially parallel to the first and second pixel electrodes160aand160b.

As shown inFIGS. 10H,11H,12H and13H, the first ohmic contact layer144aand second ohmic contact layer144bare formed by removing the ohmic contact layer144(ofFIG. 11G) exposed between the source and drain electrodes150and153, and thereby exposing the active layer141. Then, a silicon oxide layer (not shown) may be formed on the active layer141exposed between the first and second ohmic contact layers144aand144bby plasma process under an ambient of oxygen. The silicon oxide layer (not shown) protects the active layer141. A step of forming the silicon oxide layer (not shown) is not essential for the array substrate.

In a method of fabricating the array substrate for the IPS-mode LCD device according to the present invention, the pixel electrode160, the third common electrode165and the data line146are formed on a same layer as each other with a same material as each other. Since the source and drain electrodes150and153covers both ends of the semiconductor layer145, respectively, the problem of wavy noise does not occur. Also, the data pad electrode130is formed on a same layer as the gate pad electrode129with a same material as the gate pad electrode129. The first and second pixel electrodes160aand160b, and the first, second and third common electrodes124,127and165have bending shapes, thereby forming multi-domains.

The above-mentioned array substrate does not include a passivation layer. However, since a first alignment layer (not shown) is formed on the pixel electrode160, the data line146and the third common line165, a problem that the pixel electrode160, the data line146and the third common line165become rusty does not occur. Also, the first alignment layer covers the data pad electrode130, the gate pad electrode129, the data link line123.

The array substrate is combined with the color filter substrate (not shown) including the color filter layer (not shown) and a second alignment layer (not shown). And the liquid crystal layer (not shown) is interposed between the array substrate and the color filter substrate.

FIG. 14is a cross sectional-view of a portion taken along the line XIV-XIV ofFIG. 5and shows the data link line123and the data link line contact hole171. As shown inFIG. 14, the data link line123includes the first metal layer123aand the transparent conductive layer124bis formed on the substrate110. The data link line123contacts the data pad electrode130(ofFIG. 5) through the data pad contact hole137(ofFIG. 5). The gate insulating layer135is formed on the data link line123. The gate insulating layer135has the data link line contact hole171exposing the data link line123. The data line146is formed on the gate insulating layer135and contacts the data link line123through the data link line contact hole171. InFIG. 14, the data link line123has a double-layered structure. Alternatively, the data link line may have a triple-layered structure as mentioned above.