Memory controller, method of operating, and apparatus including same

A method of operating a memory controller includes; counting a number of read operations directed to a page-group of data stored in a block and generating a first read count number, then comparing the first read count number with a first reference count threshold among a first set of reference count thresholds associated with the page-group, and upon determining that the first read count number exceeds the first reference count threshold, performing a copy-back operation of the page-group data from the block to another block.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(a) from Korean Patent Application No. 10-2013-0075394 filed on Jun. 28, 2013, the subject matter of which is hereby incorporated by reference.

BACKGROUND

The inventive concept relates generally to memory controllers, methods of operating memory controllers, and apparatuses incorporating memory controllers. More particularly, the inventive concept relates to memory controller operating methods capable of copying back page-group data from one memory block to another memory block during a read refresh operation.

Flash memory devices include a vast number of individual memory cells that operate under various conditions related to both the memory cells themselves and the flash memory device as a whole. For example, it is well understood that each flash memory cell will gradually ‘fatigue’ (or wear-out) over its operational life. Additionally, the quality (or reliability) of the data stored by a memory cell at any given point in time will be affected by certain eternal (e.g., noise, environmental, and/or operating voltage-related) factors. That is, the actual threshold voltage exhibited by a programmed flash memory cell relative to a set of defined threshold voltage distributions is a function of many factors. Accordingly, memory system designers seek to account for these many factors in order to provide data having the highest data reliability that may be reasonably expected for a memory device, given its age, use, and overall functionality.

SUMMARY

According to an aspect of the inventive concept, there is provided a method of operating a memory controller comprising; counting a first number of read operations directed to a first page-group of data stored in a first block of the memory device to generate a first read count number, and counting a second number of read operations directed to a second page-group of data stored in the first block of the memory device to generate a second read count number, comparing the first read count number with a first reference count threshold among a first set of reference count thresholds associated with the first page-group and upon determining that the first read count number exceeds the first reference count threshold, performing a copy-back operation of the first page-group data from the first block to a second block of the memory device different from the first block.

According to another aspect of the inventive concept, there is provided a memory controller for controlling a memory device and comprising; a counting module that generates a first read count number for a first page-group of data stored in a first block of a flash memory device, and a second count number for a second page-group of data stored in the first block of the memory device to generate a second read count number, and a copy-back page-group determination module that compares the first read count number with a first reference count threshold among a first set of reference count thresholds associated with the first page-group, and upon determining that the first read count number exceeds the first reference count threshold, performs a copy-back operation of the first page-group data from the first block to a second block of the flash memory device different from the first block.

DETAILED DESCRIPTION OF EMBODIMENTS

Certain embodiments of the inventive concepts will now be described in some additional detail with reference to the accompanying drawings. This inventive concept may, however, be embodied in many different forms and should not be construed as being limited to only the illustrated embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Throughout the written description and drawings, like reference numbers and levels are used to denote like or similar elements.

The term “module” is used hereafter to denote a variety of related hardware, firmware and/or software components that cooperate to provide certain functionality to memory controllers and apparatuses according to embodiments of the inventive concept. Those skilled in the art will recognize that many different specific configurations of software, firmware and/or hardware may be provide equivalent functionality. Thus, the term “module” may read on, in part, one or more logical unit(s); programming code; and/or hardware resource(s) that when interoperated are capable of performing the described functionality.

FIG. 1is a block diagram illustrating an electronic system1according to an embodiment of the inventive concept, andFIG. 2is a block diagram further illustrating the memory controller100ofFIG. 1. Referring toFIG. 1, the electronic system1generally includes a host10and a memory system20.

The memory system20is connected with the host10and includes the memory controller100and a non-volatile memory device200. The memory controller100may control data exchange between the host10and the non-volatile memory device200. In certain embodiments, the memory controller100may be used to control the execution of read operations directed to “read data” stored in the non-volatile memory device200and/or write operations related to “write data” to be written to the non-volatile memory device200in response to a request received from the host10.

In addition to controlling the execution of read/write operations, the memory controller100may also be used to monitor and control certain “internal operations” that contribute to the successful overall operation of the non-volatile memory device200. Such internal operations (e.g., garbage collection, wear-levelling, read refresh, etc.) may be thought of as housekeeping, background, or management operations that are necessary to the proper and efficient operation of the non-volatile memory device200. In this context, it is assumed that consistent with conventional usages, the non-volatile memory device200may be used to store various types of data, such as data defining programming code as well as payload (e.g., user-defined files) data.

According to various embodiments of the inventive concept, the non-volatile memory device200may be implemented using one or more flash memory device(s), an embedded multimedia card (eMMC), a universal flash storage (UFS), a solid state drive (SSD), or a redundant array of independent disks (or a redundant array of inexpensive disks) (RAID). Alternately, according to other embodiments of the inventive concept, the non-volatile memory device200may be implemented using one or more non-volatile memory-based storage device(s) other than flash memory-based storage device(s). Examples of the non-volatile memory-based storage device include electrically erasable programmable read-only memory (EEPROM), magnetic RAM (MRAM), spin-transfer torque (MRAM), conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM (RRAM), polymer RAM (PoRAM), nano floating gate memory (NFGM), holographic memory, molecular electronics memory device, and insulator resistance change memory.

Those skilled in the art will understand that various embodiments of the inventive concept such as memory system20may further include components such as a read only memory (ROM) capable of storing programming code executed when the memory system20is powered-up, a clock module capable of generating one or more clock signal(s), and/or a timer.

Referring toFIG. 2, the memory controller100may include a buffer memory110, a central processing unit (CPU)120, a host interface130, a non-volatile memory interface140, an error correction code (ECC) block150, and a bus160. The buffer memory110may be implemented by using volatile memory, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM).

The buffer memory110may be used to temporarily store write data to be written to the non-volatile memory device200and/or read data retrieved from the non-volatile memory device200. In the illustrated embodiment ofFIG. 2, the buffer memory110is internally implemented within the memory controller100, but this need not be the case in other embodiments.

The CPU120may be used to control the overall operation of the memory controller100. That is, the CPU120may be used to control data exchange(s) between the buffer memory110, the host interface130, the non-volatile memory interface140, and the ECC block150via the bus160. The CPU120may also be used to drive the execution of a flash translation layer (FTL) associated with the non-volatile memory device200.

The host interface130may be used to control the communication of data and/or information with the host10using one or more interface protocol(s), such as an UHS (e.g., UHS-I or UHS-II), a peripheral component interconnect-express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), or the like. In certain embodiments of the inventive concept, the interface protocol may be a universal serial bus (USB), a multi-media card (MMC), an enhanced small disk interface (ESDI), or integrated drive electronics (IDE), but is not limited thereto.

In similar manner, the non-volatile memory interface140may be used to interface data exchanges between the non-volatile memory device200and the memory controller100. The ECC block150may detect and correct an error included in data that is to be stored in the non-volatile memory device200or in data read from the non-volatile memory device200, by using an ECC.

FIG. 3is a conceptual diagram of an exemplary, hierarchical structure of hardware/software components that may form in one embodiment (1A) the electronic system ofFIG. 1. Referring toFIGS. 1, 2 and 3, the electronic system1A generally comprises a host10A and a memory system20A.

The host10A is assumed to operate in response to one or more operating system(s) (OS) and one or more applications (e.g., application1through application N) that make use of certain resources and capabilities provided by the host OS. The memory system20A is assumed to include a flash controller100A and a flash memory device200A. The flash controller100A is further assumed to include an FTL170and an interface layer140A.

The interface layer140A provides a flash interface so that the flash controller100A may access the flash memory device200A. The interface layer140A may correspond to the whole or a part of the non-volatile memory interface140ofFIG. 2.

The FTL170is a specialized software layer capable of managing at least the allocation of physical memory space within the memory device200A. The FTL170is functionally disposed between the host10A and the interface layer140A so that the flash memory device200A may be used without an additional requirement of modifying the file system used by the flash memory device200A to match the file system used by the host10A.

In its functional operation, the FTL170ofFIG. 3is assumed to include a logical-to-physical address mapping module172, a garbage collection module174, a wear-levelling module176, and a read refresh control module178. The logical-to-physical address mapping module172, garbage collection module174, wear-levelling module176, and read refresh control module178may be variously provided either functionally or logically, and may share one or more common hardware/software resources.

The logical-to-physical address mapping module172may be used to map certain logical address(es) defined by the file system of the host10A onto the physical address(es) provided by the flash memory device200A using, for example, one or more address mapping table(s).

The garbage collection module174may be used to control execution of a garbage collection operation that manages the provision of valid page(s) within defined block(s) of the flash memory device200A. In certain embodiments, the garbage collection operation may copy a valid page existing in an “old block” of the flash memory device200A to a “new block”, and then erase the old block to generate a new “free block” that may be used during subsequent read/write operations.

The wear-levelling module176may be used to control the execution of a wear-levelling operation capable of extending the useful lifespan of flash memory cells in the flash memory device200A. In certain embodiments, the wear-levelling operation manages the distribution of write (or program) operations and/or erase operations across a number of defined memory blocks in order to prevent uneven wearing of the constituent flash memory cells.

The read refresh control module178may be used to control the flash memory device200A in order to copy-back data from an “impaired memory block” having diminished data reliability due to read disturbance experienced by the flash memory device200A to a “normal memory block” having acceptable data reliability. This type of specialized copy-back operation is termed “a read refresh operation” in the context of the inventive concept.

The term “read disturbance” should be broadly understood to denote an electrical disturbance or interference effect upon a first memory cell connected to a word line that is generated as the result of a read operation being directed to a second memory cell connected to an adjacent word line. The read disturbance may essentially cause an inadvertent (re-)programming of the first memory cell.

In the context of certain embodiments of the inventive concept, the read refresh control module178will perform a read refresh operation (i.e., the specialized copy-back operation) according to “page-groups” of data. That is, a particular read refresh operation may be directed to identified “page-group data”, wherein the page-group data includes data from two or more pages.

Exemplary structure, operation and/or functionality for the read refresh control module178ofFIG. 3will be further described in the context of embodiments illustrated inFIGS. 4, 5, 6, 7, 8 and 9that follow.

FIG. 4is a general block diagram of the read refresh control module178ofFIG. 3, andFIG. 5is a flowchart summarizing in one example a method of operating a memory controller according to certain embodiments of the inventive concept. Referring toFIGS. 3, 4 and 5, the read refresh control module178comprises a counting module178-1and a copy-back page-group determination module178-2.

The counting module178-1may be used to track a “read count number” for each memory block of the flash memory device200A. That is, the counting module178-1will count for each block a number of executed read operations directed to constituent memory cells of each block. The counting module178-1may then be used to communicate a particular read count number, or a plurality of read count numbers to the copy-back page-group determination module178-2. This communication of one or more read count numbers may be done in response to request made to the counting module178-1, or as part of a cyclically performed update function.

This control information provided by embodiments of the inventive concept recognizes that each defined page-group included in each block of a non-volatile memory will have at any given time a particular data reliability expectation, and that different page-groups will have different data reliability expectations. Further, the data reliability expectation for each page-group will be a function of read disturbance(s) that may have occurred over a given time horizon. The concept of variable data reliability expectations for different page-groups will be described hereafter in relation toFIGS. 6 and 7.

Thus, according to certain embodiments of the inventive concept, the copy-back page-group determination module178-2may include a storage device (e.g., memory or register) capable of storing a field of read count numbers that respectively serve as a criterion for a read refresh operation directed to a corresponding page-group. For example, the field of read count numbers may be stored in the storage device in the form of a read refresh table that tracks different read count numbers for each page-group. One possible embodiment for the read refresh table is illustrated inFIG. 8.

Referring toFIG. 5, it is assumed that the copy-back page-group determination module178-2compares one or more read count number(s) provided by the counting module178-1with each one of a plurality of reference count numbers (S10). Here, each reference count number may be determined in accordance with the page-groups included in a given memory block, and in accordance with a number (or a range) of program/erase (P/E) cycle executed by the flash memory device200A over a given time period. Thus, as shown for example inFIG. 8, a plurality of reference count numbers may be respectively associated with a plurality of page-groups included in a memory block in accordance with a plurality of P/E cycle ranges for the flash memory device200A.

Then, the copy-back page-group determination module178-2may control the flash memory device200A to execute a copy-back operation directed to data in a page-group when the page-group has a current read count number that exceeds a relevant reference count number (S20). In other words, the copy-back page-group determination module178-2may control the execution of a copy-back operation that copies the data of a page-group from a first block determined to have impaired data reliability to a second block deemed to have normal data reliability.

FIG. 6is a conceptual diagram further describing a data reliability expectation difference between page-groups that may be caused by read disturbance. Referring toFIG. 6, possible threshold voltage distributions for a 2-bit multi-level flash memory cell (MLC) are shown. Possible states for the MLC include an erase state E and three (3) program states P1, P2and P3, wherein it is assumed that states E, P1, P2and P3respectively correspond to data values of ‘11’, ‘10’, ‘00’, and ‘01’. In this example, the first bit of each data value is the least significant bit (LSB) and the second bit is the most significant bit (MSB).

As illustrated inFIG. 6, it is assumed that the lowest threshold voltage distribution corresponding to the erase state E is relatively more affected by read disturbance than the program states P1, P2and P3. Thus, the desired or intended threshold voltage distribution for the erase state E may actually be more like erase state E′ due to the read disturbance. Under these assumed conditions, the data reliability expectation for MSB data is relatively low, as it will be difficult to distinguish the erase state E′ from the first program state P1. Thus, the data reliability expectation of the LSB page—assuming that the LSB is stored differently from the MSB page—will be different from the data reliability expectation for the MSB page. In other words, a MSB page-group storing the MSB page of the 2-bit MLC will have a lower data reliability expectation than a corresponding LSB page-group.

FIG. 7is another conceptual diagram further describing data reliability expectation differences between various page-groups caused by read disturbance. Referring toFIG. 7, threshold voltage distributions for a 3-bit MLC are shown. Possible states for the 3-bit MLC include an erase state E and seven (7) program states P1, P2, P3, P4, P5, P6and P7, respectively corresponding to data values ‘111’, ‘011’, ‘001’, ‘000’, ‘010’, ‘110’, ‘100’, and ‘101’. Here, a first bit of each data value is said to be the LSB, the second bit is a center significant bit (CSB), and the third bit is the MSB.

Similar toFIG. 6, a threshold voltage distribution of the erase state E is more affected by read disturbance than the other states P1through P7. The erase state E may be worse like an erase state E′ due to read disturbance. In this case, the reliability of the LSB distinguished by the erase state E and the first program state P1may be lower than the reliability of the CSB and that of the MSB.

Thus, the reliabilities of an LSB page, a CSB page, and an MSB page that store the LSB, the CBS, and the MSB, respectively, are different. In other words, an LSB page-group including the MSB page in the multi-level cell of 3 bits may have lower reliability than a CSB page-group including the CSB page and an MSB page-group including the MSB page.

The read refresh table ofFIG. 8has been reference above, and may be used during a copy-back operation controlled by the read refresh control module178ofFIG. 3. Referring toFIGS. 3, 6, and 8, the read refresh table may include read count number information that may be used to initiate a read refresh operation. However, a given read count number may be variously interpreted in relation to one or more reference read count numbers based on different ranges of P/E cycles executed by the flash memory device200A.

In this manner certain embodiments of the inventive concept recognize that the overall data reliability of a flash memory device will generally decrease as the number of P/E cycles executed by the flash memory device increases. Hence, reference count numbers (or reference count thresholds) may be differently applied during a comparison of a given read count number according to the number of P/E cycle previously executed by the flash memory device. For example as illustrated inFIG. 8, if a “current number of executed P/E cycles” falls within a first range of between zero and 100, then a given read count number received from the counting module178-1will be compared with a first reference count threshold (e.g., RC1-1). In contrast, if a current number of executed P/E cycles falls within a second range of between 101 and 500, then a given read count number will be compared with a second reference count threshold (e.g., RC1-2), and if a current number of executed P/E cycles falls within a third range of between 501 and 3000, then a given read count number will be compared with a third reference count threshold (e.g., RC1-3). In the illustrated example ofFIG. 8. it is assumed that the second reference count threshold RC1-2is less than the first reference count threshold RC1-1, and the third reference count threshold RC1-3is less than the second reference count threshold RC1-2. Of additional note, the foregoing P/E cycle ranges and first set of reference count thresholds (RC1-1, RC1-2and RC1-3) are associated in the read refresh table ofFIG. 8with a first page-group (PAGE-GROUP1), whereas a second set of reference count thresholds (RC2-1, RC2-2and RC2-3) are associated in the read refresh table ofFIG. 8with a second page-group (PAGE-GROUP2). Those skilled in the art will understand that many more reference count thresholds (and corresponding executed P/E cycle ranges) may be used in various embodiments of the inventive concept, and may be variously associated with a great number of defined page-groups.

Thus, even under the same general operating conditions (e.g., a current range of executed P/E cycles), a first reference count threshold associated with a first page-group may be different (or the same) as a second reference count threshold associated with a second page-group. As a result, the granularity (and resulting volume) of the information stored read refresh table ofFIG. 8may be controlled in certain embodiments of the inventive concept by the particular definition of the page-groups within one or more block(s).

According to certain embodiments of the inventive concept, the first page-group ofFIG. 8may be a MSB page-group including MSB pages, while the second page-group may be a LSB page-group including LSB pages. Continuing with the assumptions described above with respect toFIGS. 6 and 7, the first page-group may have lower data reliability expectation than the second page-group. Thus, the first set of reference count thresholds may more strict (i.e., lower) than the second set of reference count thresholds.

According to other embodiments of the inventive concept, a competent read refresh table may include information related to different reference count thresholds (and executed P/E cycle ranges or other memory system condition indicator(s)) for three (3) or more page-groups of data per memory cell (e.g., an MSB page-group; a CSB page-group; and a LSB page-group, where the LSB page-group may have lower data reliability expectation than the MSB page-group and/or the CSB page-group).

FIG. 9is a conceptual diagram illustrating a copy-back operation that may be executed under the control of the read refresh control module178ofFIG. 3. Referring toFIGS. 3 and 9, the flash controller100A may be used to control the flash memory device200A to copy-back data stored in a first page-group including PAGE1, PAGE3, PAGE5, and PAGE7. Here, the first page-group data is copied back from an old block (BLOCK1) to a new block (BLOCK2). It is assumed that consistent with the foregoing, the first page-group ofFIG. 9is subjected to the copy-back operation because a current read count number for the first page-group data exceeds a reference count threshold associated with a current number of executed P/E cycles for the flash memory device.

FIG. 10is a block diagram of an electronic system400according to another embodiment of the inventive concept, which includes the memory controller100and the non-volatile memory device200ofFIG. 1. Referring toFIGS. 1 and 10, the electronic system400may be implemented by using a cellular phone, a smart phone, a personal digital assistant (PDA), mobile internet device (MID), a wearable computer, a wireless communication device, or the like.

The electronic system400may include the non-volatile memory device200, the memory controller100capable of controlling an operation of the non-volatile memory device200, a processor410, a display420, a radio transceiver430, and an input device440.

The memory controller100may control a data access operation of the non-volatile memory device200, for example, a program operation, an erase operation, or a read operation, under the control of the processor410. The data programmed in the non-volatile memory device200may be displayed via the display420under the control of the processor410and/or the memory controller100.

The processor410may control an operation of the display420so that data output by the memory controller100, data output by the radio transceiver430, or data output by the input device440may be displayed via the display420.

The radio transceiver430may transmit or receive a radio signal via an antenna ANT. For example, the radio transceiver430may transform the radio signal received via the ANT into a signal that can be processed by the processor410. Thus, the processor410may process the signal output by the radio transceiver430and may transmit a signal obtained by the processing to the memory controller100or the display420.

The radio transceiver430may also change the signal output by the processor410to a radio signal and may output the radio signal to an external device via the ANT.

The input device440is capable of inputting a control signal for controlling an operation of the processor410or data to be processed by the processor410, and may be implemented by using a pointing device, such as a touch pad or a computer mouse, a keypad, a keyboard, or the like. According to an embodiment, the memory controller100capable of controlling the operation of the non-volatile memory device200may be implemented by using a part of the processor410and may also be implemented by using a special chip separate from the processor410.

FIG. 11is a block diagram of an electronic system500according to another embodiment of the inventive concept, which includes the memory controller100and the non-volatile memory device200illustrated inFIG. 1. Referring toFIGS. 1 and 11, the electronic system500may be implemented by using a memory card, a smart card, or the like.

The electronic system500includes the memory controller100, the non-volatile memory device200, and a card interface520. The memory controller100may control data exchange between the non-volatile memory device200and the card interface520.

The card interface520may interface data exchange between a host530and the memory controller100according to a protocol of the host530. According to an embodiment, the card interface520may be a secure digital (SD) card interface or an MMC interface, but is not limited thereto.

According to another embodiment, the card interface520may support a USB protocol and an interchip (IC)-USB protocol. Herein, the card interface520may denote hardware capable of supporting the protocol used by the host530, software mounted in the hardware, or a signal transmission method.

The host530may be implemented by using a PC, a tablet PC, a digital camera, a digital audio player, a mobile telephone, console video game hardware, a digital set-top box, or the like.

When the electronic system500contacts a host interface550of the host530, the host interface550may perform data communication with the non-volatile memory device200via the card interface520and the memory controller100under the control of a microprocessor540.

FIG. 12is a block diagram of an electronic system600according to another embodiment of the inventive concept, which includes the memory controller100and the non-volatile memory device200illustrated inFIG. 1. Referring toFIGS. 1 and 12, the electronic system600may be implemented by using an SSD.

The electronic system600may include the memory controller100, a plurality of non-volatile memory devices200, a buffer manager620, a volatile memory device630, and a host640. The memory controller100may control a data processing operation of each of the non-volatile memory devices200.

The buffer manager620may control the volatile memory device630to store data that is exchanged between the memory controller100and the host640. The volatile memory device630may buffer the data exchanged between the memory controller100and the host640. According to an embodiment, the volatile memory device630may be implemented by using a DRAM.

FIG. 13is a block diagram of an electronic system700according to another embodiment of the inventive concept, which includes the memory system20illustrated inFIG. 1. Referring toFIGS. 1 and 13, the electronic system700may be implemented by using a redundant array of independent disks (RAID) system and may include a RAID controller710and a plurality of memory systems700-1through700-n(where n is a natural number).

Each of the memory systems700-1through700-nmay be the memory system20illustrated inFIG. 1. The memory systems700-1through700-nmay constitute a RAID array. According to an embodiment, electronic system700may be implemented by using a PC or an SSD.

While a program operation is being performed, the RAID controller710may transmit program data output by a host according to a program command output by the host, to at least one of the memory systems700-1thorough700-naccording to a RAID level.

While a read operation is being performed, the RAID controller710may transmit, to the host, data red from at least one of the memory systems700-1thorough700-naccording to a read command output by the host.

The host ofFIG. 13may denote the host10ofFIG. 1.

FIG. 14is a block diagram of an electronic system1000according to another embodiment of the inventive concept. Referring toFIGS. 1 and 14, the electronic system1ofFIG. 1may be implemented by using the electronic system1000ofFIG. 14. The electronic system1000may be implemented by using a data processing device capable of using or supporting a mobile industry processor interface (MIPI). Examples of the data processing device include a PDA, a portable multimedia player (PMP), an internet protocol television (IPTV), and a smart phone.

A camera serial interface (CSI) host1012implemented in an application processor1010may serially communicate with a CSI device1041of an image sensor1040via a CSI. For example, the CSI host1012may include a deserializer (DES), and the CSI device1041may include a serializer (SER).

A display serial interface (DSI) host1011implemented in the application processor1010may serially communicate with a DSI device1051of a display1050via a DSI. For example, the DSI host1011may include an SER, and the DSI device1051may include a DES.

According to an embodiment, the electronic system1000may further include a RF chip1060capable of communicating with the application processor1010. A PHYsical layer (PHY)1013included in the application processor1010and a PHY1061included in the RF chip1060may exchange data with each other according to a MIPI digRF.

According to an embodiment, the electronic system1000may further include a global positioning system (GPS) receiver1020, a storage1070, a microphone (MIC)1080, a DRAM1085, and a speaker1090.

The host10ofFIG. 1may be implemented by using the application processor1010ofFIG. 14, and the memory system20ofFIG. 1may be implemented by using the storage1070ofFIG. 14.

The electronic system1000may communicate by using a world interoperability for microwave access (WIMAX) module1030, a wireless local area network (WLAN) module1100, and/or an ultra wideband (UWB) module1110.

Various memory controller operating methods, memory controllers and apparatuses incorporating same according to embodiments of the inventive concept will be capable of executing a read refresh operation on a page-group by page-group basis. Thus, page-group data having understood characteristics (i.e., a number of read operation directed thereto) in the context of current flash memory device characteristics (i.e., a current number of executed P/E cycles) may be appropriately managed in memory to ensure acceptable data reliability expectations, thereby improving over reliability and performance of the memory system.