System and method for filtering field programmable gate array input/output

Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a “black box” regarding FPGA I/O during the occurrence of the catastrophic events within the system.

BACKGROUND

1. Technical Field

The present disclosure relates to filtering the input/output (I/O) of a Field Programmable Gate Array (FPGA), and more specifically to adding a logic layer between the FPGA I/O and the core logics of the FPGA.

FPGAs are integrated circuits which can be configured by users after manufacturing. Each FPGA contains I/O (generally in the form of pins), programmable logic blocks, and programmable routing which connects the logic blocks to one another and the I/O. Users develop FPGA logic programming codes using a Hardware Description Language, such as VHDL or Verilog, use EDA (Electronic Design Automation) tools to compile and synthesize the codes into FPGA programming specific to an FPGA, and then upload that program into the FPGA for implementation. To verify the FPGA codes are operating correctly, users apply known inputs to the appropriate pins of the FPGA and compare resulting outputs to desired outputs, either in a simulation environment or in a live system.

SUMMARY

Disclosed are systems, methods, and non-transitory computer-readable storage media for adding a logic layer between the FPGA I/O and the core logic of the FPGA. With the extra logic layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA.

To take advantage of the FPGA I/O connected to the filtering layer, a digital oscilloscope can be implemented. The digital oscilloscope can have options to select trigger signals, signal acquisition rate, triggering position, triggering polarity, and the ability to acquire and store all I/O connected to the filtering layer inside the FPGA blockRam. The acquired signals can then be fetched and viewed by users accessing the stored I/O from the FPGA using a CPU and bus connected to the FPGA.

When the digital oscilloscope is in place, a special operation mode can be implemented, where predefined events can trigger the digital oscilloscope to acquire the I/O signals, store the I/O signals in the FPGA blockRAM, generate a timestamp for the I/O collected, and send an interrupt signal to the CPU. After detecting the interrupt signal, the CPU can transfer the acquired signal samples to a non-volatile media, using the FPGA timestamp to tag the event with the CPU's epoch time. Thus all signals leading to catastrophic failure can be acquired and saved in a non-volatile medium, performing a function similar to the “blackbox” of an airplane.

Consider the following example. An FPGA can be loaded using a logic codes bitstream by a CPU, or loaded from a PROM (Programmable Read Only Memory), where the FPGA logic segments the FPGA into: a core logic layer and a filtering layer, wherein the filtering layer: receives Input/Output (I/O) associated with the core logic layer, and is configurable by the CPU to modify the I/O associated with the core logic layer.

The FPGA can receive the instructions for the I/O filtering layer logic via a bus (such as an I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), or other bus format) from the CPU. Users can then verify that the core logic is receiving and outputting correct data.

DETAILED DESCRIPTION

A system, method and computer-readable media are disclosed which allows users to filter, monitor, and otherwise modify inputs and outputs to and from the core logic of an FPGA. This is achieved by programming the FPGA to have multiple logic layers. As data is received, a filtering layer within the FPGA can (1) receive the inputs to the pins of the FPGA, (2) modify/replace the inputs according to logic within the filtering layer, (3) communicate the FPGA inputs, or the filtered outputs of the filtering layer, to a core logic layer within the FPGA, (4) output the FPGA inputs and/or the outputs of the filtering layer to other connected devices. The core logic layer within the FPGA can receive the filtered outputs of the filtering layer, perform programmed logic functions using those outputs, and produce corresponding outputs. The outputs of the core logic layer can either pass through the filtering layer to FPGA pins without any change, or can be modified by the filtering layer prior to arriving at the FPGA pins.

Various embodiments of the disclosure are described in detail below. While specific implementations are described, it should be understood that this is done for illustration purposes only. Other components and configurations may be used without parting from the spirit and scope of the disclosure.

The disclosed systems and concepts provide improvement over industry standards such as JTAG (Joint Test Action Group), which can be used to test and debug FPGAs. Specifically, the hardware validation concepts disclosed herein can improve automation of hardware validation tests, introduce additional simulation/verification coverage, and create test cases for ILOM (Integrated Lights Out Manager).

Conventional JTAG interfaces with FPGAs have certain limitations the concepts disclosed herein improve upon. For example, JTAG only works with cells, whereas systems configured as disclosed herein communicate with I/O cells as well as internal registers which directly map to any I/O interfaces, such as serialized general I/O interfaces. Furthermore, the I/O filtering disclosed herein can load static and/or predefined signal patterns (such as a positive pulse or a negative pulse), whereas the JTAG is only capable of loading static values to the I/O of the FPGA. In addition, the I/O filtering disclosed herein can load I/O cell output, read I/O cell input, and/or replace I/O cell input. As yet another improvement, JTAG uses a TAP (Test Access Port) controller, while the I/O filtering disclosed herein can adapt to any host.

In addition, the digital scope implementation within the filter layer has certain advantage over other implementations. For example, in Xilinx® ChipScope™, the numbers of channels and how deep the acquisition channels can be are limited by the device resources. By contrast, embodiments configured as disclosed herein can capture over 400 channels simultaneously, where each channel has 2048 sampling points. In addition, the digital scope implementation disclosed herein can use any I/O signals received, as well as internal registers, as a digital scope trigger, with the additional flexibility that a user can choose a trigger in real-time, without any need to re-compile the FPGA design. Such digital scope features require no extra hardware components to set up the digital scope and/or read back the captured signals, making such filtering layers suited for use as an engineering tool in the laboratory as well as a service tool in the field.

By setting the digital oscilloscope to be triggered for certain events, including catastrophic events, systems configured according to this disclosure effectively implement a “black box,” for the FPGA. Some of the advantages of a black box implementation can include: improving failure analysis by using hardware parameters captured prior to hardware failure; allowing failure analysis engineers to replay the hardware event without recreating the failure itself; and storing multiple sets of parameters and hardware failures with which a unified timeline of the system can be created, and which can be used for identifying failure correlations.

Having discussed some non-limiting, exemplary advantages of how the disclosed concepts improve on the art, the disclosure turns to discussing exemplary embodiments and configurations of systems and methods. These variations shall be described herein as the various embodiments are set forth. The disclosure now turns toFIG. 1.

FIG. 1illustrates an example100of FPGA I/O filters104being implemented on an FPGA102. FPGAs, like other integrated circuits, have physical pins connecting the device to other devices on a board. The physical pins of the example FPGA102are elements120,118, with possible connections to Serial I/O112, Mbus (Similar to Serial I/O, but with frame CRC (Cyclic Redundancy Check) protection) I/O110, Parallel/Serial I/O122, or other I/O resources124. The FPGA102can likewise be in communication with a Service Processor (SP)108via an I2C bus. Between the physical I/O120,118,124of the FPGA and core logic I/O114,116, a layer of filtering logic104is implemented.

In other words, as the FPGA is being programmed, the bit-stream/FPGA images used to program the FPGA can partition the FPGA into distinct sections: a filtering layer104and a core logic layer106, where the core logic layer106performs the main calculations and computations required by the FPGA device, and a filtering layer104which “filters” the inputs and outputs both of the FPGA102and the core logic layer106.

The filtering layer104can load input being provided to the FPGA by the FPGA pins, thereby “intercepting” it before the input is provided to the core logic. The filtering layer104can then pass the input on to the core logic106, or modify and/or replace the input before sending it to the core logic106, based on user configuration for each input. The filtering layer104can also pass the input from the core logic106to the FPGA output, or modify and/or replace the input before sending it to the FPGA102output. Such logic blocks within the filtering layer can be referred to as “filtering logic.”

The filtering layer104can also act as a non-intrusive digital scope, outputting data which is being received/output by the FPGA102, and/or outputting data from the core logic106. For example, the outputs from the filtering layer104can be sampled and stored inside the FPGA blockRAM, then users can read the captured signal sampling points one signal a time by selecting the signal through the primary I2C device.

The digital oscilloscope features provide the user the capability to capture all the listed I/O signals, where each signal is captured in a predetermined number of points with sampling rate selectable from multiple sampling rates. For example, sampling rates can include 25 Mhz, 12.5 Mhz, 6.25 Mhz, 2.5 Mhz, 100 Khz, 10 Khz, 1 khz and 100 hz. This gives the user the capability to capture a chain of event of approximately 20 seconds when the predetermined number of points is 2048, with the understanding that this amount of time is directly related to the amount of data being captured.

The digital scope also enables the user to select any listed I/O signals as the triggering signals, or use I2C access to a specific register as the trigger event. Users can interact with the FPGA via the I2C bus connected SP (service processor)108, thereby allowing the user to view inputs/outputs to the FPGA, as well as reset, program, and debug the FPGA. A user can specify when the FPGA begins to capture the I/O signal by specifying the trigger position within the 2048 sampling points. For example if the trigger position is 0, that shows the trigger is at the very beginning of the captured series of points, if trigger position is 2047, it means the trigger point is at the very end of the captured series of points.

To use the digital scope feature it is not required to set a global I/O filtering enable bit because the digital scope feature is a non-intrusive feature. However, a user can combine the digital scope feature with the I/O modification feature whenever the user thinks it is beneficial to his task.

The filtering can load static logic values and/or pre-defined signal patterns into/out of the core logic I/O. Examples of static logic values can include high or low voltages corresponding to a “1” or a “0”. Examples of pre-defined signal patterns can include a positive pulse, a negative pulse, etc.

It can be desirable to verify how an FPGA will react in particular circumstances. With the filtering layer104, users can provide specific inputs and test the FPGA logic to ensure it will react correctly when those inputs are received. For example, a user testing an FPGA on board could use the filtering layer to enter specific inputs indicating a hardware failure on the board, then view how the FPGA reacts based on that input. Non-limiting exemplary error conditions which an FPGA could receive include a host power fault, a power supply unit oversubscription, and a thermal trip event.

FIG. 2illustrates functionality of FPGA I/O filters208,220. The left example202represents filtering of I/O input206via a filter layer208prior to the core logic210receiving the I/O input. The right-side example214represents filtering of I/O output222via a filter layer220after the core logic218has received and processed input data. The export filter layer220can have the same structure as the import filter layer208. For resource sharing all I/O filtering can share one same stimulus library. For example, service processor SP108can configure I/O filter controls204,216for both filter examples202,214according user instructions. In addition, the filtering layer can either pass data through the filtering layer or can replace/modify the data. For example, the output from the I/O filter208,220can be the same as the input206, or218(i.e, the data can be passed through the filtering layer), or the output can be replaced by the chosen signal from the stimulus library212,224.

FIG. 3illustrates I2C devices for I/O filtering a the digital oscilloscope implementation. By using an indirect access approach, a primary I2C device302inside a I/O filtering module can access an array of control and status registers for all the I/O signals. The primary I2C device302can also control other functions for this module. Consider the following example of how the registers on the primary I2C device can be configured.

IO Filtering module, Primary I2C device, Register 0x00DefaultBitsFieldRulesDescription07:0Signal#[7:0]RWLower 8 bits of the IO signal #field of 12 bits

IO Filtering module, Primary I2C device, Register 0x02DefaultBitsFieldRulesDescription03:0StimulusRWSelect which waveform to replace the selected signal.SourceFirst release will only enable logic high and low:Stimulus SourceWaveform00112200 ns of logic low,then restored to the originalsignal.3200 ns of logic high,then restored to the originalsignal.OthersReserved04Original SignalROThe logic level of the original signal05Modified SignalROThe logic level of the modified signal06ReservedROReserved07Enable IORWSet this bit to 1 is to enable to replace the originalFilteringsignal with the selected stimulus waveform.

IO Filtering module, Primary I2C device, Register 0x03DefaultBitsFieldRulesDescription06:0ReservedROReserved17Write/RWWhen write 0 to this bit, it triggersReadthe transferring the configurationdefined by 0x02 to the signalsselected by registers 0x00 and 0x01.When write 1 to this bit, it triggersthe configuration and status readof the IO signals selected by registers0x00 and 0x01 to register 0x02

IO Filtering module, Primary I2C device, Register 0x04DefaultBitsFieldRulesDescription06:0ReservedROReserved07IO FilteringROWhen this bit is set to 1, the IOGlobal Enablefiltering can be activated foreach IO signals.User needs to write specialcodes to register 0xF0 to 0xF7 toset this bit.

IO Filtering module, Primary I2C device, Register 0x05DefaultBitsFieldRulesDescription06:0ReservedROReserved07IO latch TriggerWOWrite 1 to this bit, will latchall IO signals into another setof registers at the same timeto be shifted out by readingthe second I2C device

IO Filtering module, Primary I2C device, Register 0xF0-0xF7DefaultBitsFieldRulesDescription007:0ReservedWOUser writes special codes to these8 registers to set the global IOfiltering enable. When user writes 0to register 0xF0, the global enableis disabled. When read these registersthey always return 0.

As illustrated inFIG. 2, the primary I2C device controls the filtering of the I/O to and from the core logic. InFIG. 3, this is further illustrated by both filtering the inputs to the FPGA304and filtering the outputs of the FPGA316. With regard to filtering the inputs to the FPGA, this is done by a set of control signals from306from the primary device302which controls the filtering310for input signal #0, resulting in output sent to the core logic312. With regard to filtering the outputs of the FPGA, this is done by a set of control signals from318from the primary device302for output signal #M, which instructs the filtering regarding the output of the core logic320, resulting in filtered I/O output324.

To facilitate easy verifying of the I/O values, a second I2C device314can be created. The second I2C device314is created to dump the I/O logic level (status). To dump the I/O logic level, the second device314is expected to latch the I/O signals at the same time they are produced, such that a cause-effect analysis can be done to debug problems. The I/O signal latch enable is done through the primary I2C device302. Similarly, a third I2C device326can be created, where the third I2C device dumps the I/O filtering enable bits for all I/O signals.

Because all I/O goes through the filtering, a digital scope328can be implemented to monitor all I/O signals. The digital scope328can include of a digital scope control332, digital scope memory array340, and digital scope channel read device344. Under scoping conditions, consider the following example, with the primary I2C device302at address 0x60, the second I2C device314at address 0x62, and the third I2C device326at address 0x64. The digital scope can store all I/O signals in the internal memory array340. In order to read a specific channel through device 0x66, a user first selects the channel through device 0x60, register 0x19 (see below), and 0x1A (see below); then read the data from device 0x66, where in the readback I2C data each bit represents one acquired data point.

To set up the digital scope, a user writes specific parameters for a set of control registers in I/O filtering primary I2C device302with address 0x60. The following registers show relevant registers in device 0x60 in details:

I/O Filtering module, Primary I2C device, Register0x10, Digital Scope, Local Trigger Selector #0DefaultBitsFieldRulesDescription007:0TriggerRWSelected local trigger signal #0,Signallower 8 bits. Combined with lower 2#0bits from register 0x11 to produce thefull 10 bits of signal #0 as the digitalscope trigger when scope trigger sourceis selected as a local signal.

I/O Filtering module, Primary I2C device, Register0x11, Digital Scope, Local Trigger Selector #1DefaultBitsFieldRulesDescription001:0TriggerRWSelected local trigger signal #1,Signalhigher 2 bits. Combined with lower 8#1bits from register 0x10 to produce thefull 10 bits of signal #1 as the digitalscope trigger when scope triggersource is selected as a local signal.007:2ReservedROReserved

I/O Filtering module, Primary I2C device, Register 0x12, Digital Scope Trigger ControlDefaultBitsFieldRulesDescription001:0Digital ScopeRWOnly applicable when local trigger is selected:Trigger Edge2′B00: Positive edge;Selector2′B01: Negative edge;2′B10: Both positive and negative edges;2′B11: Reserved.113:2Digital ScopeRWSelect which source to use for the digital scope:Trigger Source2′B00: Use the selected local trigger;Selector2′B01: Use the SP accessing the specific I2C register asthe trigger,2′B10: Use the trigger pulse from the Mbus as thelocal FPGA digital scope trigger. For SMOD, thetriggers are the pulses generated any selectedCMODs; while for CMODs, the trigger is from thepulse generated by SMOD.3′B11: “Flight Black Box Mode”. Once this mode isselected a pre-determined a set of events will be usedfor controlling the digital scope. More details in the“Flight Black Box Mode” sections.14Relay theRWIf this is set to 1 in SMOD FPGA, the SMOD will relayTrigger Eventthe trigger pulse to all CMODs; while if it is set to 1 inCMOD FPGA, will relay the trigger pulse to SMODwhen only the trigger source are local, by SP or in“Flight Black Box Mode” to break endless trigger loop.0007:5ReservedROReserved

I/O Filtering module, Primary I2C device, Register0x13, Digital Scope, Trigger Position Register #0DefaultBitsFieldRulesDescription007:0TriggerRWThe Digital scope has an exemplaryPositiondepth of 2048 points, this registerRegistercombined with register 0x14 forms#0the 11-bit position of the triggerin digital scope channels. These arethe 8 lower bits.

I/O Filtering module, Primary I2C device, Register0x14, Digital Scope, Trigger Position Register #1DefaultBitsFieldRulesDescription1112:0TriggerRWThe Digital scope has depth of 2048Positionpoints, this register combined withRegisterregister 0x13 forms the 11-bit#1position of the trigger in digitalscope channels. These are the higher3 bits.007:3ReservedROReserved

I/O Filtering module, Primary I2C device, Register0x18, Digital Scope, Acquisition StatusDefaultBitsFieldRulesDescription001:0DigitalROIndicating which state the digitalScopescope is at:Acqui-00: Digital scope is at idle state;sition01: Digital scope is at armed state-StatusThe digital scope is always runningand acquiring data, but it is notbeing triggered yet;10: Digital scope is at runningstate- The digital scope has alreadybeen triggered, and it is stillacquiring data to fill in the memoryarray;11: Digital scope is at finished state.The digital scope has finished theacquisition successfully.007:2ReservedROReserved

I/O Filtering module, Primary I2C device, Register0x19, Digital Scope, Read Channel Selector #0DefaultBitsFieldRulesDescription007:0ReadRWThe Digital scope acquires samples forChannelall listed signals. To get the storedRegistersamples out of the FPGA, user has to#0select which signal to be fetched, afterthat user can read the data from I2Cdevice 0x66. These bits are the 8 lowerbits for the signal #.

I/O Filtering module, Primary I2C device, Register0x1A, Digital Scope, Read Channel Selector #1DefaultBitsFieldRulesDescription001:0ReadRWThe Digital scope acquires samplesChannelfor all listed signals. To get the storedRegistersamples out of the FPGA, user has to#1select which signal to be fetched,after that user can read the data fromI2C device 0x66. These bits are the2 high bits for the signal #.007:2ReservedROReserved

The primary I2C device302inside the I/O filtering holds the Control and Status Registers (CSR) for the digital scope operation. These include:a. Local Trigger Selector, 10-bit;b. Digital Scope Trigger Control, 8-bit;c. Trigger Position Register, 11-bit;d. Sampling Rate Selector, 4-bit;e. Run Button, 1-bit;f. Stop Button, 1-bit;g. Acquisition Status, 2-bit;h. Read Channel Selector, 10-bit.

Regarding the digital scope control block332: this functional block takes the control signals from the primary I2C device302, generates the digital scope memory write enable334, write address336, the starting address for the channel read338, and the digital scope acquisition status.

Regarding the digital scope memory array340: the memory arrays are created by utilizing the FPGA block-RAM. First a macro with 32-bit wide write/read data bus, 11-bit wide address bus, dual-port RAM can be created by a Xilinx Core Generator. Then multiple dual-port RAM macros can be connected to the digital scope control block332and digital scope channel read I2C device344. Each I/O signal is connected to each of the write data bus bit, and each read data bus bit is connected to the N:1 multiplexer342that is controlled by the CSR “Read Channel Selector”338. The output of the multiplexer346is then connected to the digital scope channel read I2C device344.

Regarding the digital scope channel read I2C device344. This functional block responds to the I2C access from the system, generates the digital scope memory array read address348, and re-arrange the read-back data order suited for I2C access.

When the digital scope functions are in place, systems can be further configured to operate in a “Blackbox” mode, where predetermined system events of significance trigger recording of events for failure analysis. This is accomplished by the FPGA being hard-coded to use these pre-determined events as the digital scope triggers, to either record events proceeding the trigger or initiate recording of events

Once the digital scope is set in this “Blackbox Mode”, and is started by system software, the digital scope can run the following steps (the times, sample rates, and other values provided herein are exemplary only and are non-limiting):(1) The digital scope starts to record all listed signals on every 10 us, with total sampling number of 2048 for each signal,(2) When the these blackbox trigger events occurs,(3) The digital scope latches the information to identify which blackbox trigger is fired,(4) The digital scope latches the current FPGA timestamp,(5) The digital scope keeps recording for another 256 samples, then stops recording;(6) Then the digital scope generates an interrupt to the system software and indicates that the digital scope is successfully concluded.

After system software receives the blackbox interrupt, system software can transfer all the recorded signal samplings to a non-volatile storage for further failure analyzing. When system software reads back the latched blackbox timestamp, it can use this timestamp to correlate the blackbox samplings to other system events, and put them into a unified consistent system timeline. The captured hardware parameters are therefore securely stored in non-volatile media.

The blackbox feature is a special application case out of the FPGA digital scope. But there are a few extra CSR that are only applicable to the blackbox mode. The following CSR descriptions show what they are:

I/O Filtering module, Primary I2C device, Register0x1C, Digital Scope, Trigger Time Stamp Reg #0DefaultBitsFieldRulesDescription007:0Latched timeROThe Event log time stamp at thestamp formoment of the digital scopeDigital scopetrigger, bit 7 to 0. The combinedtrigger, #0latched event log time stamp [10:0]is in the unit of second.

I/O Filtering module, Primary I2C device, Register0x1D, Digital Scope, Trigger Time Stamp Reg #1DefaultBitsFieldRulesDescription002:0Latched timeROThe Event log time stamp at thestamp formoment of the digital scopeDigital scopetrigger, bit 10 to 8. The combinedtrigger, #1latched event log time stamp [10:0]is in the unit of second.007:3ReservedROReserved

I/O Filtering module, Primary I2C device, Register0x1E, Digital Scope, Blackbox trigger sourceDefaultBitsFieldRulesDescription00HostROA logic high indicates the host powerPowerfailure event triggers the blackbox.Fault01PSUROA logic high indicates the PSU over-oversub-subscription event triggers thescriptionblackbox.02ThermalROA logic high indicates the systemtripthermal trip interrupt to SP triggerseventthe blackbox.to SP03FanROA logic high indicates the system fanBlastblasting event triggers the blackbox.04MbusROA logic high indicates the Mbusfailurefailure (CRC error) event triggersthe blackbox.05CPUROA logic high indicates the host CPUProcproc_hot_L event triggers theHotblackbox.06CPUROA logic high indicates the host CPUThermalthermal_L event triggers thetripblackbox.07CPUROA logic high indicates the hostCATERRCPU CATERROR_L oror CPUCPU_ERROR2_L event triggersERR2the blackbox.assertion

An 11-bit timestamp count inside the blackbox can increment in any desired time increments (for example, one second increments). When the timestamp count reaches full it can wrap around to zero, while at the same time the FPGA can generate an interrupt to the CPU. This allows the CPU to collaborate the timestamp zero with the CPU Epoch time (i.e., the timestamp is calibrated periodically to keep sync with CPU Epoch time). This allows the system to correctly keep track of time elapsed between consecutive events that are separated by one or more wraparounds of the 11-bit timestamp counter.

FIG. 4illustrates a general-purpose system or computing device400capable of performing the concepts disclosed herein, including a processing unit (CPU or processor)410and a system bus405that couples various system components including the system memory415such as read only memory (ROM)420and random access memory (RAM)425to the processor410. The system400can include a cache412of high speed memory connected directly with, in close proximity to, or integrated as part of the processor410. The system400copies data from the memory415and/or the storage device430to the cache412for quick access by the processor410. In this way, the cache provides a performance boost that avoids processor410delays while waiting for data. These and other modules can control or be configured to control the processor410to perform various actions. Other system memory415may be available for use as well. The memory415can include multiple different types of memory with different performance characteristics. It can be appreciated that the disclosure may operate on a computing device400with more than one processor410or on a group or cluster of computing devices networked together to provide greater processing capability. The processor410can include any general purpose processor and a hardware module or software module, such as module1432, module2434, and module3436stored in storage device430, configured to control the processor410as well as a special-purpose processor where software instructions are incorporated into the actual processor design. The processor410may essentially be a completely self-contained computing system, containing multiple cores or processors, a bus, memory controller, cache, etc. A multi-core processor may be symmetric or asymmetric.

The system bus405may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. A basic input/output (BIOS) stored in ROM420or the like, may provide the basic routine that helps to transfer information between elements within the computing device400, such as during start-up. The computing device400further includes storage devices430such as a hard disk drive, a magnetic disk drive, an optical disk drive, tape drive or the like. The storage device430can include software modules432,434,436for controlling the processor410. Other hardware or software modules are contemplated. The storage device430is connected to the system bus405by a drive interface. The drives and the associated computer-readable storage media provide nonvolatile storage of computer-readable instructions, data structures, program modules and other data for the computing device400. In one aspect, a hardware module that performs a particular function includes the software component stored in a tangible computer-readable storage medium in connection with the necessary hardware components, such as the processor410, bus405, display435, and so forth, to carry out the function. In another aspect, the system can use a processor and computer-readable storage medium to store instructions which, when executed by the processor, cause the processor to perform a method or other specific actions. The basic components and appropriate variations are contemplated depending on the type of device, such as whether the device400is a small, handheld computing device, a desktop computer, or a computer server.

Although the exemplary embodiment described herein employs a hard disk, other types of computer-readable media which can store data that are accessible by a computer, such as magnetic cassettes, flash memory cards, digital versatile disks, cartridges, random access memories (RAMs)425, and read only memory (ROM)420, may also be used in the exemplary operating environment. Tangible computer-readable storage media, computer-readable storage devices, or computer-readable memory devices, expressly exclude media such as transitory waves, energy, carrier signals, electromagnetic waves, and signals per se.

To enable user interaction with the computing device400, an input device445represents any number of input mechanisms, such as a microphone for speech, a touch-sensitive screen for gesture or graphical input, keyboard, mouse, motion input, speech and so forth. An output device435can also be one or more of a number of output mechanisms known to those of skill in the art. In some instances, multimodal systems enable a user to provide multiple types of input to communicate with the computing device400. The communications interface440generally governs and manages the user input and system output. There is no restriction on operating on any particular hardware arrangement and therefore the basic features here may easily be substituted for improved hardware or firmware arrangements as they are developed.

The logical operations of the various embodiments are implemented as: (1) a sequence of computer implemented steps, operations, or procedures running on a programmable circuit within a general use computer, (2) a sequence of computer implemented steps, operations, or procedures running on a specific-use programmable circuit; and/or (3) interconnected machine modules or program engines within the programmable circuits. The system400shown inFIG. 4can practice all or part of the recited methods, can be a part of the recited systems, and/or can operate according to instructions in the recited tangible computer-readable storage media. Such logical operations can be implemented as modules configured to control the processor410to perform particular functions according to the programming of the module. For example,FIG. 4illustrates three modules Mod1432, Mod2434and Mod3436which are modules configured to control the processor410. These modules may be stored on the storage device130and loaded into RAM425or memory415at runtime or may be stored in other computer-readable memory locations.

FIG. 5illustrates an exemplary FPGA environment500, where a CPU516interacts with an FPGA502via an I2C bus510. The processing unit516interacts with components such as DDR DRAM514, boot flash520to store the BIOS and firmware, NAND flash518as a non-volatile storage medium, a Gigabit Ethernet port522to a network (thereby allowing users to login to the system). The embedded CPU516may also include a JTAG interface508which can directly load an FPGA image to the FPGA502, or alternatively, can load the FPGA image to a flash PROM504and subsequently load the FPGA502via a serial interface506. The I2C bus510between the CPU516and FPGA502can provide the CPU516a configuration path for FPGA I/O filtering CRS, where the FPGA502can also generate various interrupts512to the CPU516upon detection of certain events.

The disclosure now turns to the exemplary method embodiment shown inFIG. 6. For the sake of clarity, the method is described in terms of an exemplary system400as shown inFIG. 4configured to practice the method. The steps outlined herein are exemplary and can be implemented in any combination thereof, including combinations that exclude, add, or modify certain steps.

The system400receives, at a processor, a Field Programmable Gate Array (FPGA) program bitstream (502), to yield FPGA programming logic segments. The system400loads the FPGA programming logic segments into an FPGA, such that the FPGA is modified to comprise (604): a core logic layer (606); and a filtering layer, wherein the filtering layer (608): receives Input/Output (I/O) associated with the core logic layer (610); and is programmable to modify the I/O associated with the core logic layer (612).

The I/O can, for example, include signals associated with pins of the FPGA, signals embedded inside a serial GPIO interface, and/or signals of or any other buses. The system400can pass data through the filtering layer and/or modify the data coming through the filtering layer. For example, the system400can replace the I/O with a set of pre-defined signal patterns.

The system400can act as a digital oscilloscope or a “black box.” For example, the system400can enable a user selectable trigger, and, upon detecting an occurrence of the user selectable trigger, sample the I/O and store the sampled I/O into a FPGA blockRAM.

Such digital oscilloscope/blackbox embodiments can be triggered upon detecting specific conditions, conditions which can be selected/set by a user. For example, the user selectable trigger can be an error condition. In addition, storing the sampled I/O can further include receiving a timestamp from the FPGA associated with the sampled I/O; receiving, at the processor and from the FPGA, an interrupt signal; and after receiving the interrupt signal, correlating the sampled I/O and the timestamp with an Epoch time of the processor. Such timestamps can be generated and calibrated by the processor periodically.

The various embodiments described above are provided by way of illustration only and should not be construed to limit the scope of the disclosure. For example, the principles herein apply FPGAs, but can also be applied to other field-programmable integrated circuits. Various modifications and changes may be made to the principles described herein without following the example embodiments and applications illustrated and described herein, and without departing from the spirit and scope of the disclosure.