A physical layer device for a network interface includes a reconciliation device that includes a first interface that outputs data. A physical coding sublayer (PCS) device communicates with the first interface and includes an encoder that encodes the data to produce an encoded data block including an offset portion and n data blocks, each including at least one of data portions and control code portions. The encoder is capable of locating the control code portions within any of the n data blocks based on the offset portion.

FIELD OF THE INVENTION

The present invention relates to networks, and more particularly to data coding in physical coding sublayers of physical layer devices in Ethernet network devices.

BACKGROUND OF THE INVENTION

Ethernet network devices include physical layer devices that transmit and receive data over a medium. In a Gigabit (Gb) network device, the physical layer device includes a Physical Coding Sublayer (PCS), which acts as an interface between a Gigabit Media Independent Interface (GMII) or extended GMII (XGMII) and a Physical Medium Attachment (PMA) layer.

The PCS typically includes an encoder/decoder. The PCS may also include other components such as a scrambler and a gearbox in certain circumstances. The gearbox is not necessary when an analog circuit in the PMA can be designed to run in multiples of a reference clock or multiples of bus widths, both of which are not easy to implement. In essence, the gearbox is a digital solution that is used to overcome analog circuit limitations. The encoder provides data formatting and organizes the data into data blocks (such as bytes) and control codes. The scrambler performs line balancing and ensures sufficient transition density. The function of the gearbox is application specific. The gearbox may include a buffer that is used to adjust for input/output speed differences and/or to format data width for a Serializer/Deserializer (SERDES).

In one approach, the PCS is implemented based on the 10GBASE-R standard in IEEE section 802.3, which is hereby incorporated by reference. The 10GBASE-R standard implements 64/66 bit encoding, which has low overhead. The 10GBASE-R standard restricts the placement of control codes within a data block during block encoding. When multiple independent communications channels are aggregated to provide high-speed link, control codes may need to appear in any byte position of a data block after the channels are combined. Therefore, the 10GBASE-R standard may pose problems for aggregated communications channels.

SUMMARY OF THE INVENTION

A physical layer device for a network interface includes a reconciliation device that includes a first interface that outputs data. A physical coding sublayer (PCS) device communicates with the first interface and includes an encoder that encodes the data to produce an encoded data block including an offset portion and n data blocks, each including at least one of data portions and control code portions. The encoder is capable of locating the control code portions within any of the n data blocks based on the offset portion.

In other features the offset portion includes at least one offset count. The offset portion includes a bit map that represents the data portions and control code portions included in the n data blocks. The offset portion indicates a quantity of the control code portions. The offset portion includes a data format that is based on a quantity of the control code portions. In other features the physical layer device includes a multiplexer that aggregates data, which includes at least one of data portions and control portions, from m data streams received from the reconciliation device into a multiplexed data block. The first interface is at least one of XGMII compliant and GMII compliant. The physical layer device includes a scrambler that communicates with the encoder and that scrambles the encoded data block to produce a scrambled data block, and a sync adder that adds a sync header to the scrambled data block. The sync header has a first state when the scrambled data block only includes the data portions. The sync header has a second state when the scrambled data block includes at least one of the control code portions. The physical layer device includes a serializer/deserializer (SERDES) that communicates with the scrambler. The PCS module implements 64/66 bit encoding. The PCS device is otherwise compliant with the 10GBASE-R section of the Institute of Electrical and Electronics Engineers (IEEE) 802.3 specification. A network transmitter includes the physical layer device.

A physical layer device of an Ethernet network device includes a serializer/deserializer that has an input and an output that outputs an encoded data block. A physical coding sublayer (PCS) device communicates with the output and includes a decoder that decodes the encoded data block. The encoded data block includes an offset portion and n data blocks, each including at least one of data portions and control code portions. The control code portions can be located within any of the n data blocks.

In other features the decoder reads the offset portion of the encoded data block. The decoder determines a quantity of the control code portions based on the offset portion.

In other features the physical layer device includes a reconciliation device that includes a first interface that receives decoded data from the decoder. The first interface is at least one of XGMII compliant and GMII compliant. The encoded data block from the serializer/deserializer is scrambled and includes a sync header. The physical layer device includes a descrambler that descrambles the encoded data block for the decoder. The sync header has a first state when the n data blocks only include the data portions. The sync header has a second state when the n data blocks include at least one of the control code portions. The decoder decodes the encoded data block based on the sync header and the offset portion. The PCS device implements 64/66 bit decoding. A network receiver includes the physical layer device.

A method of operating a physical layer device for a network interface includes receiving data from a first interface of a reconciliation device; and encoding the data to produce an encoded data block. The encoded data block includes an offset portion and n data blocks, each including at least one of data portions and control code portions. The control code portions can be located within any of the n data blocks based on the offset portion.

In other features the offset portion includes at least one offset count. The offset portion includes a bit map that represents the data portions and control code portions included in the n data blocks. The offset portion indicates a quantity of the control code portions. The offset portion includes a data format that is based on a quantity of the control code portions.

In other features the method includes aggregating data, which includes at least one of data portions and control portions, from m data streams received from the reconciliation device into a multiplexed data block. The first interface is at least one of XGMII compliant and GMII compliant. The method includes scrambling the encoded data block to produce a scrambled data block and adding a sync header to the scrambled data block. The sync header has a first state when the scrambled data block only includes the data portions. The sync header has a second state when the scrambled data block includes at least one of the control code portions. The method includes serializing the scrambled data block. The encoding step is otherwise compliant with the 10GBASE-R section of the Institute of Electrical and Electronics Engineers (IEEE) 802.3 specification.

A method of operating a physical layer device of an Ethernet network device includes converting serialized data into an encoded data block and decoding the encoded data block. The encoded data block includes an offset portion and n data blocks, each including at least one of data portions and control code portions. The control code portions can be located within any of the n data blocks.

In other features the decoding step includes reading the offset portion of the encoded data block. The method includes comprising determining a quantity of the control code portions based on the offset portion. The method includes communicating decoded data from the decoding step to a first interface of a reconciliation device. The encoded data block is scrambled and includes a sync header. The method includes descrambling the encoded data block prior to the decoding step. The sync header has a first state when the n data blocks only include the data portions. The sync header has a second state when the n data blocks include at least one of the control code portions. The decoding step decodes the encoded data block based on the sync header and the offset portion.

A computer program executed by a processor for operating a physical layer device of an Ethernet network device includes converting serialized data into an encoded data block and decoding the encoded data block. The encoded data block includes an offset portion and n data blocks, each including at least one of data portions and control code portions. The control code portions can be located within any of the n data blocks.

In other features the decoding step includes reading the offset portion of the encoded data block. The computer program includes determining a quantity of the control code portions based on the offset portion. The computer program includes communicating decoded data from the decoding step to a first interface of a reconciliation device. The encoded data block is scrambled and includes a sync header. The computer program includes descrambling the encoded data block prior to the decoding step. The sync header has a first state when the n data blocks only include the data portions. The sync header has a second state when the n data blocks include at least one of the control code portions. The decoding step decodes the encoded data block based on the sync header and the offset portion.

A computer program executed by a processor for operating a physical layer device for a network interface includes receiving data from a first interface of a reconciliation device; and encoding the data to produce an encoded data block. The encoded data block includes an offset portion and n data blocks, each including at least one of data portions and control code portions. The control code portions can be located within any of the n data blocks based on the offset portion.

In other features the offset portion includes at least one offset count. The offset portion includes a bit map that represents the data portions and control code portions included in the n data blocks. The offset portion indicates a quantity of the control code portions. The offset portion includes a data format that is based on a quantity of the control code portions.

In other features the computer program includes aggregating data, which includes at least one of data portions and control portions, from m data streams received from the reconciliation device into a multiplexed data block. The first interface is at least one of XGMII compliant and GMII compliant. The computer program includes scrambling the encoded data block to produce a scrambled data block and adding a sync header to the scrambled data block. The sync header has a first state when the scrambled data block only includes the data portions. The sync header has a second state when the scrambled data block includes at least one of the control code portions. The computer program includes serializing the scrambled data block. The encoding step is otherwise compliant with the 10GBASE-R section of the Institute of Electrical and Electronics Engineers (IEEE) 802.3 specification.

A physical layer device for a network interface includes reconciliation means for generating data at a first interface thereof. The physical layer device also includes physical coding sublayer (PCS) means for communicating with the first interface and including encoding means for encoding the data to produce an encoded data block including an offset portion and n data blocks, each including at least one of data portions and control code portions. The encoding means is capable of locating the control code portions within any of the n data blocks based on the offset portion.

In other features the offset portion includes at least one offset count. The offset portion includes a bit map that represents the data portions and control code portions included in the n data blocks. The offset portion indicates a quantity of the control code portions. The offset portion includes a data format that is based on a quantity of the control code portions.

In other features the physical layer device includes multiplexing means for aggregating data, which includes at least one of data portions and control portions, from m data streams received from the reconciliation means into a multiplexed data block. The first interface is at least one of XGMII compliant and GMII compliant. The physical layer device includes scrambler means for communicating with the encoding means and scrambling the encoded data block to produce a scrambled data block. The physical layer device includes sync adder means for adding a sync header to the scrambled data block. The sync header has a first state when the scrambled data block only includes the data portions. The sync header has a second state when the scrambled data block includes at least one of the control code portions. The physical layer device includes serializer/deserializer (SERDES) means for communicating with the scrambler means. The PCS means implements 64/66 bit encoding. The PCS means is otherwise compliant with the 10GBASE-R section of the Institute of Electrical and Electronics Engineers (IEEE) 802.3 specification.

A physical layer device of an Ethernet network device includes a serializer/deserializer means for outputting an encoded data block from an output thereof. The physical layer device also includes physical coding sublayer (PCS) means for communicating with the output including decoding means for decoding the encoded data block. The encoded data block includes an offset portion and n data blocks, each including at least one of data portions and control code portions. The control code portions can be located within any of the n data blocks.

In other features the decoding means reads the offset portion of the encoded data block. The decoding means determines a quantity of the control code portions based on the offset portion.

In other features the physical layer device includes reconciliation means for receiving decoded data from the decoding means at a first interface thereof. The first interface is at least one of XGMII compliant and GMII compliant. The encoded data block from the serializer/deserializer is scrambled and includes a sync header. The physical layer device further comprises descrambler means for descrambling the encoded data block for the decoding means. The sync header has a first state when the n data blocks only include the data portions. The sync header has a second state when the n data blocks include at least one of the control code portions. The decoding means decodes the encoded data block based on the sync header and the offset portion. The PCS means implements 64/66 bit decoding.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term device refers to an application specific integrated circuit, an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software programs, a combinational logic circuit, or other suitable components that provide the described functionality.

Referring toFIG. 1, the OSI Reference Model10defines a network device with a physical layer device12that transmits and receives data to/from a medium. The physical layer device12is further divided into a group of sublayer devices14.FIG. 1illustrates the group of sublayer devices14for Ten Gigabit Ethernet applications. The group of sublayer devices14includes a Ten Gigabit Ethernet reconciliation sublayer16, a XGMII18, a PCS20, a PMA22, a Physical Medium Dependant (PMD) sublayer24, and a Medium Dependant Interface (MDI)26. The medium is identified at28. The PCS20encodes/decodes data to/from the XGMII18and transfers encoded data to/from the PMA22.

Referring now toFIG. 2, the PCS20includes a transmitter36and a receiver38. The transmitter36includes an encoder40, which assembles data blocks that include data bytes and/or control codes for transmission. The control codes include identification of the start and/or end of a packet and/or other data. The data blocks are transmitted from the encoder40to a scrambler42. The scrambler42prepares the data blocks for transmission and ensures sufficient transition density. Data from the scrambler42is transmitted to a gearbox44. The gearbox44formats data for a particular SERDES45. The gearbox44may include a FIFO buffer, which is used to convert from one speed to another and/or to modify the width of a bit pattern. The receiver includes a gearbox46, a descrambler48, and a decoder50, which implement the reverse of the transmit process.

For each data block transmitted, it is desirable to allow for 256 combinations of data and a limited number of control codes. For example, in 1000BASE-X 8 bit to 10 bit encoding, there are 256 possible data combinations and 12 possible control code combinations. Since there are 256+12=268 total combinations, 9 bits of data are required to encode all valid data blocks. The overhead is high because an additional bit is used to generate only 12 more combinations. When 8 bit to 10 bit encoding is implemented, 10 bits are used instead of 9, which produces an even larger overhead. However, 10 bits are used in 1000BASE-X to preserve DC balance and to ensure that sufficient transitions exist through redundant bits.

A 64/66 bit block coding concept is implemented by IEEE 802.3 in the 10GBASE-R PCS. 10GBASE-R reduces overhead and achieves DC balance through scrambling and guaranteed periodic transitions with a sync header. The additional coding complexity on the digital side increases latency in the system. Since the circuit can be run at a lower rate, power is saved.

Referring now toFIG. 3, a block encoding scheme58for 10GBASE-R is shown. The block encoding scheme58is set forth in IEEE 802.3, which is hereby incorporated by reference in its entirety. A 2-bit sync header60is followed by a 64-bit block of data62. Each 64-bit block of data62includes 8 bytes that may be data bytes64and/or control codes66. Bytes labeled with a C, O, S, or T represent control codes66. Bytes labeled with a D represent data bytes64. A sync header60with a value of 01 indicates that the entire 64-bit block of data62is made up of data bytes64. When the sync header60has a value of 10, at least one of the control codes66exists among the 64-bit block of data62.

FIG. 3shows that there are a limited number of permutations for the control codes66and data bytes64. Many combinations are not possible. For example, the combination C0, D1, C2, C3, D4, C5, D6, C7is not possible. This limitation creates a problem when control codes66need to be placed within any byte in a 64-bit block of data62. For example, when multiple independent data streams are aggregated into a high-speed link, control codes66need to appear in any location of a 64-bit block of data62. Aggregation is very useful in reducing the pin count of devices. Therefore, the 10GBASE-R PCS cannot be used as currently designed when multiple independent data streams need to be aggregated.

Referring now toFIG. 4, a transmitter36for a PCS device20according to the present invention is illustrated. Four independent data streams74-1,74-2,74-3, and74-4are combined by a multiplexer76into an 8-byte data block78. The encoder40outputs an encoded data block80as well as the 2 bit sync header60. The encoded data block80is transmitted to the scrambler42. The sync header60is used by a receiver to lock onto a data block. The sync header60bypasses the scrambler42. Both a scrambled data block and the sync header60are input to the gearbox44. Data from the gearbox44is transmitted to a SERDES45. The scrambler42and the gearbox44operate according to the 10GBASE-R standard. However, the coding scheme implemented by the encoder40is different than the coding performed in 10GBASE-R.

Referring now toFIGS. 5A-5C, the coding according to the present invention provides for data62to include between one and eight control codes66. Each control code66is four-bits wide. The remainder of data62includes data bytes64and/or “don't care” data. The sync header60is set to “10” to indicate that data62includes the control codes66. Two more bits immediately follow the sync header60and indicate whether data62includes one, two, or between three and eight control codes66.

Referring now toFIG. 5A, an example is shown of data62that includes one control code66. A “0” immediately follows the sync header60. The “0” is part of an offset portion of the data62and indicates that data62includes only one control code66. A 3-bit field154follows the “0” and includes an offset to a location of the control code66. The offset is between zero and seven and referenced to locations Data0in data62. The offset is an unsigned binary number written with the LSB on the left. In the depicted example the reverse-ordered offset is “100”, which is equal to decimal “1”. The control code66is therefore stored in location Data1.

Referring now toFIG. 5B, an example is shown of data62that includes two control codes66-1and66-2. A two-bit field160includes a bit pattern “10” and immediately follows the sync header60. The “10” bit pattern in field160is part of the offset portion of data62and indicates that data62includes only two control codes66. Two 3-bit fields154-1and154-2follow field160and include offsets of respective control codes66-1and66-2in the data62. In the depicted example, the first field154-1includes the reverse-ordered offset “010”, which is equal to decimal “2”. The first control code66-1is therefore stored in location Data2. The second field154-2includes the reverse-ordered offset “011”, which is equal to decimal “6”. The second control code66-2is therefore stored in location Data6.

Referring now toFIG. 5C, several examples are shown of data62that includes between three and eight control codes66-1, . . . ,66-8. A four-bit pattern170of “11XX” immediately follows the sync header60. The “11XX” is included in the offset portion of data62and indicates that data62includes between three and eight control codes66. An eight-bit field172follows the “11 XX” and includes bit-mapped offsets of each control code66. Each bit in the field172represents a corresponding data byte64(if the bit is equal to zero) or a corresponding control code66(if the bit is equal to one.) The LSB of the bit map is on the left and represents the Data0position in data62. In the examples ofFIG. 5Cthe order of the bit map is always given from Data0to Data7and don't care data (X's) are always inserted at the end of data62. It is possible to rearrange the order of data62or place the don't care data in different positions without a loss of generality.

In a first example150-1, the field172includes ones in the locations of bit1, bit2, and bit7. The control codes66are therefore located in the Data1, Data2, and Data7locations. In a second example150-2, the field172includes ones in the locations of bit0, bit1, bit2, bit4, and bit6positions. The control codes66are therefore located in the Data0, Data1, Data2, Data4, and Data6locations.

The remaining examples ofFIG. 5Cinclude other bit patterns in field172and corresponding control codes66. It should be appreciated that still other bit patterns can be used to indicate still other combinations of control code66locations.

Referring now toFIG. 6, a decoding algorithm200according to the present invention is shown. Algorithm200can be executed in a decoder50for a PCS device20. Algorithm200can be used to decode data62that is encoded according to the patterns described inFIGS. 5A-5C. Control begins in step202. Control immediately proceeds to block204and determines whether data62is being received. If it is not, control waits for data62by re-entering decision block204. Control proceeds to decision block206upon receiving data62. In decision block206, control examines the sync header60to determine whether data62includes any control codes66. If data62does not contain any control codes66then control branches to block208and reads data bytes64from all eight bytes of data62. Control then returns to decision block204.

On the other hand if control determines, in decision block206, that data62includes control codes66, then control branches to decision block210. In decision block210control determines whether the bit following the sync header60is equal to zero. If it is, then data62includes a single control code66and control branches to block212to read the offset from field154and locate the control code66accordingly. Control then returns to decision block204.

On the other hand if control determines, in decision block210, that data62includes more than one control code66, then control branches to decision block214. In decision block214control determines whether the two bits following the sync header60are equal to “10” and. If they are, the data62includes two control codes66and control branches to block216to read the offsets from locations154and locate the corresponding control codes66accordingly. Control then returns to decision block204. On the other hand, if control determines, in decision block214, that data62includes more than two control codes66, then control branches to block218. In block218control uses the bit-mapped offsets in location170to locate the control codes66.

Referring now toFIGS. 7A-7D, various exemplary implementations of the present invention are shown. Referring now toFIG. 7A, the present invention can be implemented in a high definition television (HDTV)420. The present invention may implement and/or be implemented in either or both signal processing and/or control circuits, which are generally identified inFIG. 7Aat422. The HDTV420receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display426. In some implementations, signal processing circuit and/or control circuit422and/or other circuits (not shown) of the HDTV420may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.

The HDTV420may communicate with mass data storage427that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. The mass data storage427may include at one HDD and/or at least one DVD player/recorder. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The HDTV420may be connected to memory428such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The HDTV420also may support connections with a WLAN via a WLAN network interface429. The HDTV420may also include a power supply423.

Referring now toFIG. 7B, the present invention may implement and/or be implemented in a control system of a vehicle430. In some implementations, the present invention implement a powertrain control system432that receives inputs from one or more sensors such as temperature sensors, pressure sensors, rotational sensors, airflow sensors and/or any other suitable sensors and/or that generates one or more output control signals such as engine operating parameters, transmission operating parameters, and/or other control signals.

The present invention may also be implemented in other control systems440of the vehicle430. The control system440may likewise receive signals from input sensors442and/or output control signals to one or more output devices444. In some implementations, the control system440may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc and the like. Still other implementations are contemplated.

The powertrain control system432may communicate with mass data storage446that stores data in a nonvolatile manner. The mass data storage446may include at one HDD and/or at least one DVD player/recorder. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The powertrain control system432may be connected to memory447such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The powertrain control system432also may support connections with a WLAN via a WLAN network interface448. The control system440may also include mass data storage, memory and/or a WLAN interface (all not shown). The vehicle430may include a power supply433.

Referring now toFIG. 7C, the present invention can be implemented in a set top box480. The present invention may implement and/or be implemented in either or both signal processing and/or control circuits, which are generally identified inFIG. 7Cat484. The set top box480receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display488such as a television and/or monitor and/or other video and/or audio output devices. The signal processing and/or control circuits484and/or other circuits (not shown) of the set top box480may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.

The set top box480may communicate with mass data storage490that stores data in a nonvolatile manner. The mass data storage490may include at one HDD and/or at least one DVD player/recorder. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The set top box480may be connected to memory494such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The set top box480also may support connections with a WLAN via a WLAN network interface496. The set top box480may include a power supply483.

Referring now toFIG. 7D, the present invention can be implemented in a media player500. The present invention may implement and/or be implemented in either or both signal processing and/or control circuits, which are generally identified inFIG. 7Dat504. In some implementations, the media player500includes a display507and/or a user input508such as a keypad, touchpad and the like. In some implementations, the media player500may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons and/or a point-and-click interface via the display507and/or user input508. The media player500further includes an audio output509such as a speaker and/or audio output jack. The signal processing and/or control circuits504and/or other circuits (not shown) of the media player500may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.

The media player500may communicate with mass data storage510that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage510may include at one HDD and/or at least one DVD player/recorder. The HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The media player500may be connected to memory514such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The media player500also may support connections with a WLAN via a WLAN network interface516. The media player500may also include a power supply503. Still other implementations in addition to those described above are contemplated.