Low power content addressable memory system

A content addressable memory (CAM) system includes one or more CAM cells, each including a bit cell to store a bit and a complementary bit, and a compare circuit to compare a reference input to the stored bit and to the stored complementary bit. The compare circuit may be implemented to compare a single-ended reference input to each of the stored bit and the complementary bit. The compare circuit may include a pass circuit to selectively provide the reference input to an output under control of the stored bit and the stored complementary bit, a pull-up circuit to selectively pull-up the output under control of the reference input and the stored complementary bit, and a pull-down circuit to selectively pull-down the output under control of the reference input and the stored bit. The reference input may be provided to multiple CAM cells, which may share compare circuitry.

BACKGROUND

In a random access memory (RAM) system, a memory address and read controls are applied to the RAM system to retrieve or read contents of the memory address.

In a content addressable memory (CAM) system, a data word is provided to the CAM system, and a search for the data word is performed across bits cells of the CAM. If the data word is found, the CAM system indicates a match and returns a list of one or more storage addresses where the word was found. The CAM system may also return the data word or other associated information. A CAM system may be viewed as a hardware embodiment of a software-based associative array.

A CAM system may include an array of CAM cells, each including a storage or bit cell and a compare circuit to compare contents of the bit cell with a reference bit. Conventional CAM compare circuits are implemented with complementary or differential reference bit lines, which increase routing complexity and space requirements. The compare circuits may include a separate pass circuit for each of the differential reference bit lines. Switching delays in the CAM cell can cause unwanted current contention between the separate pass circuits, which manifests itself as a crowbar current that wastes power and slows down CAM speed.

In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.

DETAILED DESCRIPTION

FIG. 1is a block diagram of a content addressable (CAM) system100, including multiple CAM cells <0> through <n>

CAM cell <0> is described below. CAM cells <1> through <n> may be implemented similar to CAM cell <0>.

CAM cell <0> includes a bit cell106to store a bit BIT and a corresponding complementary hit BITX at corresponding nodes of bit cell106.

CAM cell <0> further includes a compare circuit108to compare a reference input107to the stored bit (BIT) and to the stored complementary bit (BITX), and to provide an indication at an output110based on the comparison.

CAM system100may include a driver circuit104to provide reference input107to CAM cells <0> through <n>. In the example ofFIG. 1, driver circuit104is illustrated as an inverter to receive a reference bit109, illustrated here as Camdata (CD), and to provide a corresponding inverted reference bit, Camdatax (CDX), as reference input107.

Compare circuit108may include logic to compare CDX to BIT and to BITX, and to output a match indication at output110when CDX differs from BIT and matches BITX, which is equivalent to CD matching BIT and differing from BITX.

Alternatively, reference bit CD may be provided directly to reference input107, and compare circuit108may include logic to compare CD to BIT and to BITX, and to output a match indication at output110when CD matches BIT and differs from BITX.

In the example ofFIG. 1, compare circuit108includes complementary inputs130and132, also referred to herein as differential inputs, to receive BIT and BITX.

Reference input107may include a differential input or a single-ended input.

Compare circuit108may include logic to perform one of the following based on logic states of reference input107, BIT, and BITX:provide reference input107to output110;pull-up output110; andpull-down output110.

The term pull-up, as used herein, refers to a switch device and/or circuit to couple a node to an operating voltage, Vcc. The term pull-down, as used herein, refers to a switch device and/or circuit to couple a node to a voltage reference, Vss, which may correspond to ground.

For illustrative purposes, a logic state of 1 corresponds to Vcc, and a logic state of 0 corresponds to Vss. Methods and systems disclosed herein are not, however, limited to these relative examples.

Compare circuit108may be implemented to perform an XOR operation with respect to reference input107, BIT, and BITX.

FIG. 2is a circuit diagram of a CAM cell202and a driver circuit204, which may represent CAM cell <0> and driver circuit104ofFIG. 1.

CAM cell202includes a bit cell206and a compare circuit208, which may represent embodiments of bit cell106and compare circuit108ofFIG. 1.

Bit cell206is illustrated as a contention-based bit cell having cross-coupled inverters to store BIT and BITX, and dual write gates NX1 and NX2, controllable by a write wordline WRWL, to write values from write bit lines WRBL and WRBLX to corresponding nodes of the cross-coupled inverters.

In the example ofFIG. 2, pass circuit212is on when BIT is at logic state 0 and BITX is at logic state 1. Pass circuit212is off when BIT is at logic state 1 and BITX is at logic state 0.

When pass circuit212is on, reference input207is provided output210through pass circuit212. Specifically, when BIT is at logic state 0 and CDX is at logic state 0 (i.e., CD is at logic state 1), the CDX logic state 0 is provided to output210to indicate that CD does not match BIT. Conversely, when CDX is at logic state 1 (i.e., CD is at logic state 0), the CDX logic state 1 is provided to output210to indicate that CD matches BIT.

When pass circuit212is off, output210is driven by one of pull-up214and pull down216.

Pull-up circuit214includes a P-type device PD2 controllable as a switch by reference input207, and a P-type device PPX2 controllable as a switch by BITX. When reference input207is at logic state 0, PD2 turns on to couple a node215to Vcc. When BITX is at logic state 0, PPX2 turns on to couple output210to node215. Thus, when CDX and BITX are at logic state 0 (i.e., CD and BIT are at logic state 1), output210is pulled-up to Vcc, or logic state 1, to indicate that CD matches BIT.

Pull-down circuit216includes an N-type device ND2 controllable as a switch by reference input207, and an N-type device NP2 controllable as a switch by BIT. When reference input207is at logic state 1, ND2 turns on turns on to couple a node217to Vss. When BIT is at logic state 1, NP2 turns on to couple output210to node217. Thus, when CDX and BIT are at logic state 1 (i.e., CD is at logic state 0), output210is pulled-down to Vss, or logic state 0, to indicate that CD does not match BIT.

Pull-up circuit214and pull-down circuit216may be referred to together as an output switch stack.

The example ofFIG. 2includes a single driver circuit204, and compare circuit208compares reference input207to each of BIT and BITX. Compare circuit208may thus be referred to as a single-ended reference input embodiment, as opposed to differential reference input embodiment.

A differential reference input embodiment may include a first driver to provide a reference input, a second driver to provide corresponding complementary reference, and a differential-input compare circuit to compare the reference input and the complementary reference input to BIT and BITX.

A single-ended reference input embodiment, as illustrated inFIG. 2, may provide reduced routing complexity, area consumption, line driver power requirements, and/or capacitive switching.

A single driver circuit, such as driver circuit204, may be implemented with a larger scale fabrication technology (i.e., wider channels, longer channels, and/or larger feature sizes), relative to driver circuits of a differential reference input embodiment, to drive a larger gate load. Nevertheless, a single-ended reference input embodiment may reduce overall area and/or power requirements.

A CAM system may be implemented to provide a reference input to multiple CAM cells, as illustrated inFIG. 1, and may include circuitry that is shared amongst the multiple CAM cells, such as described below with reference toFIG. 3.

FIG. 3is a circuit diagram of a CAM system300, including multiple CAM cells302-1through302-n, and a driver circuit304to provide a reference input307to each of CAM cells302. CAM cell302-1is described below. Remaining ones of CAM cells302may be implemented similar to CAM cell302-1.

CAM cell302-1includes a bit cell306, which may be implemented as described in one or more examples herein.

CAM cell302-1further includes a compare circuit308, including a pass circuit312to selectively provide reference input307to an output310under control of BIT and BITX, such as described above with reference to pass circuit212inFIG. 2.

CAM cell302-1further includes pull-up circuitry to selectively pull-up output310under control of reference input307and BITX, and pull-down circuitry to selectively pull-down output310under control of reference input307and BIT. The pull-up circuitry includes PD2 and PPX2, and the pull-down circuitry includes ND2 and NP2, as described above with reference toFIG. 2.

InFIG. 3, pull-up device PD2 and pull-down device ND2 is shared amongst compare circuits308-1through308-nof CAM cells302-1through302-n. Specifically, device PD2 includes a terminal322coupled to a terminal324of device PPX2 of compare circuit308-1, and to a terminal326of a corresponding device328of compare circuit308-n. Similarly, device ND2 includes a terminal330coupled to a terminal332of device NP2 of compare circuit308-1, and to a terminal334of a corresponding device336of compare circuit308-n. Sharing of PD2 and/or ND2 may further reduce area and/or power consumption.

A CAM system as disclosed herein may be implemented to search an array of CAM cells for a reference word that includes multiple reference bits.

FIG. 4is a block diagram of an example in by in array400of CAM cells, which may be implemented as described in one or more examples herein. Array400may be arranged as in rows of m-bit words. Array400may represent, for example, a 48×48 array.

Methods and systems disclosed herein may be implemented with respect to one or more of a variety of systems, such as described below with reference toFIG. 5. Methods and systems disclosed herein are not, however, limited to the examples ofFIG. 5.

FIG. 5is a block diagram of a system500including a CAM system502, which may be implemented as described in one or more examples herein.

System500may further include a processor504to access CAM system502, such as to store data and/or to search for reference words, CAM system502may be implemented as part of a memory system to support operation of processor504, and may represent, for example, a cache or an associative memory. CAM system502may be coupled to or integrated within processor504.

System500may include a communication system506to interface with a communication network. Communication system506may include a wired and/or wireless communication transceiver.

System500or portions thereof may be implemented within one or more integrated circuit dies, and may be implemented as a system-on-a-chip (SoC).

System500may further include a user interface system510.

User interface system510may include a monitor or display532to display information from processor504and/or communication system506.

User interface system510may include a human interface device (MD)534to provide user input to processor504and/or communication system506. HID534may include, for example and without limitation, one or more of a key hoard, a cursor device, a touch-sensitive device, and or a motion and/or image sensor. HID534may include a physical device and/or a virtual device, such as a monitor-displayed or virtual keyboard.

User interface system510may include an audio system536to receive and/or output audible sound.

System500may correspond to, for example, a computer system, a personal communication device, and/or a television set-top box.

System500may include a housing, and one or more of communication system506, digital processor system504user interface system510, or portions thereof may be positioned within the housing. The housing may include, without limitation, a rack-mountable housing, a desk-top housing, a lap-top housing, a notebook housing, a net-book housing, a set-top box housing, a portable housing, and/or other conventional electronic housing and/or future-developed housing.

As disclosed herein, a content addressable memory (CAM) apparatus may include a first CAM cell. The first CAM cell may include a first bit cell to store a bit and a corresponding complementary bit. The first CAM cell may further include a first compare circuit to compare a reference input to the stored bit and to the corresponding stored complementary bit, and to provide an indication based on the comparison.

The reference input may include a single-ended reference input, and the first compare circuit may include logic to compare the single-ended reference input to each of the stored bit and the corresponding stored complementary bit.

The first compare circuit may include logic to output a match indication when a reference bit matches the stored bit and differs from corresponding stored complementary bit. The CAM apparatus may include an inverter to invert the reference bit and to provide the inverted reference bit as the input reference, and the first compare circuit may include logic to output a match indication when the inverted reference bit differs from the stored bit and matches the corresponding stored complementary bit.

The first compare circuit may include logic to perform one of the following based on logic states of the reference input, the stored bit, and the stored complementary bit:provide the reference input to an output;pull-up the output; andpull-down the output,

The first compare circuit may include:a pass circuit to selectively provide the reference input to an output under control of the stored bit and the stored complementary bit;a pull-up circuit to selectively pull-up the output under control of the reference input and the stored complementary bit; anda pull-down circuit to selectively pull-down the output under control of the reference input and the stored bit.

As further disclosed herein, the CAM apparatus may include a second CAM cell, including a second bit cell and a second compare circuit to receive the same reference input as the first CAM cell, and to compare the reference input to a bit and complementary bit stored in the second bit cell.

The first and second compare circuits may include corresponding first and second pull-up circuits. The first and second pull-up circuits may each include a corresponding first switch device controllable by the respective stored complementary bit. The first and second pull-up circuits may further include a shared second switch device controllable by the reference input, where the shared second switch device includes a terminal coupled to a terminal of each of the first switch devices.

The first and second compare circuits may include corresponding first and second pull-down circuits. The first and second pull-down circuits may each include a corresponding first switch device controllable by the respective stored bit. The first and second pull-down circuits may further include a shared second switch device controllable by the reference input, where the shared second switch device includes a terminal coupled to a terminal of each of the first switch devices.

As further disclosed herein, a processor-based system may include an array of content addressable memory (CAM) cells, each including a bit cell and a compare circuit as described in one or more examples herein.

The processor-based system may include a processor to search the array of CAM cells for a reference word of multiple reference bits.

The processor-based system may include a communication system to communicate with a network. The communication system may include a wireless communication system.

The processor-based system may include communication infrastructure to communicate amongst the processor, the communication system, and a user interface system.

The processor-based system may include a housing.

The processor-based system may include a battery.

The processor, the communication system, the battery, and at least a portion of the user interface system may be positioned within the housing.

Methods and systems are disclosed herein with the aid of functional building blocks illustrating functions, features, and relationships thereof. At least some of the boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.

While various embodiments are disclosed herein, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail may be made therein without departing from the spirit and scope of the methods and systems disclosed herein. Thus, the breadth and scope of the claims should not be limited by any of the example embodiments disclosed herein.