Bimodal memory controller

A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two different formats. Each of the alternative interface circuits is electrically coupled to a corresponding signal connector, and only one of these signal connectors, in turn, is electrically coupled to the external path via an I/O pin or printed-circuit board connection (depending upon implementation). The remaining signal connector may be left electrically uncoupled from the external, wired electrical path, and, if desired, the corresponding remaining interface circuit may be left unused during operation of the memory controller.

TECHNICAL FIELD

The present embodiments relate to memory controllers. More specifically, the present embodiments relate to memory controllers that support communication with memory devices having different communication formats.

BACKGROUND

Different types of digital systems may employ different communication formats. For example, high-speed memory systems may utilize different signaling rates, voltages, impedances, common-mode signaling levels, termination structures (such as ground-referenced common-mode signaling levels) and communication formats than other memory systems. The nature of different communication formats makes it difficult to support support multiple formats on a single interface circuit, particularly where the formats in question diverge in driving voltage, currents and signaling rates. Furthermore, as digital components continue to decrease in die size, there is a trend to simplify pin counts and the number of input and output signals. Consequently, designers tend to design digital components (especially microprocessors and controllers and the like) in a manner dedicated to a single communications format.

Hence, there is a need to reduce costs and otherwise improve the marketability of digital components by enabling them to adapt to multiple communication formats without substantially increasing pin count, and without requiring platform-specific designs. This need also exists in the field of memory, where it is desired to produce memory components that can support communication parameters for diverse systems.

Note that like reference numerals refer to corresponding parts throughout the drawings.

DETAILED DESCRIPTION

FIG. 1Apresents a block diagram illustrating an embodiment of a memory system100. In this memory system, memory controller110-1includes separate interface circuits112-1and112-2, which are, respectively, electrically coupled to connectors114-1and114-2, and which are electrically isolated from one another. A given interface circuit, such as interface circuit112-1, can communicate information (such as commands, addresses, and/or data) from a communication path108(which is internal to memory controller110-1) to memory device130via an external, electrical path128(such as at least a portion of a memory-system bus), which may be wired or wireless, using a signal format (or, more generally, a communication format) that is different than the signal format of the other interface circuit. By electrically coupling only one of connectors114-1or114-2to corresponding connectors116-1during assembly of memory system100(for example, using solder balls and/or bonding wires), one of the interface circuits112can communicate the information to memory device130during operation of the memory controller110-1, while the other one of the connectors114remains electrically uncoupled to connectors116-1. In particular, connectors114-1and116-1or connectors114-2and116-1can be electrically coupled based on communication characteristics associated with memory device130. If desired, the interface circuit associated with the uncoupled connectors114may remain unused during the operation of the memory controller110-1.

Note that memory controller110-1includes two connectors (i.e., in connectors114-1and114-2) for each connector (e.g., as represented in a package or a printed circuit board). A number of different embodiments may be used to selectively connect one of the memory-controller connectors114-1or114-2to the connectors116-1. For example, as described below with reference toFIG. 2A, a single memory controller and a single printed circuit board may be combined with one of two alternative packages to electrically couple an associated one of connectors114-1and116-1or connectors114-2and116-1during assembly of memory system100(e.g., based solely on the choice of the alternative package). Alternatively, as described below with reference toFIG. 2B, a single memory controller and a single package may be combined with one of two alternative printed circuit boards to electrically couple connectors114-1and116-1or connectors114-2and116-1during assembly of memory system100(for example, the printed circuit board may have reciprocal connectors corresponding to alternative connectors114-1or114-2, but connect the external electrical path128to only one set of reciprocal connectors). Other specific embodiments are also presented below.

The principles introduced above may allow a single memory controller to support different communication formats, such as those associated with different memory devices or applications (such as extreme data rate and double data rate), without compromising the performance associated with either communication format. In particular, these principles may provide additional degrees of design freedom by not sharing a single interface circuit for the different communication formats. Thus, relative to each other, the interface circuits112may have: different voltage swings, different transistor sizes, different parasitic capacitance, different breakdown voltages, different electrostatic-discharge protection circuits, and/or different data rates. Therefore, these principles can increase the level of system integration and reduce the expense of components in memory system100. As mentioned above, note that in the embodiment shown inFIG. 1A, one interface circuit112-1or112-2may be left electrically isolated and not connected to connectors116-1(and to the associated external electrical path128). This design choice may be advantageous as, for some communication formats, the components needed to support one format may create parasitic effects that would unacceptably interfere with communications using a different format (e.g., parasitic capacitance for an unused driver could degrade the data eye associated with a higher speed communication format). By leaving one interface circuit electrically isolated from the external electrical path128, the embodiment shown inFIG. 1Amay be used to support diverse multiple formats while minimizing electrical degradation introduced by unused interface circuits.

These integrated circuits and techniques may be used in a wide variety of systems, including with a wide variety of memory systems and memory devices, including: volatile memory, non-volatile memory, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash, solid-state memory, and/or other types of memory. Moreover, for a given type of memory, these techniques may be used in different memory technologies or technology generations (which may use different power supply voltages or signaling rates). For example, these techniques may be used in extreme data rate (XDR), double-data rate (DDR), graphics double-data rate (GDDR) and/or synchronous DRAM, such as: DDR2, DDR3, DDRx, GDDR1, GDDR3, GDDR5, and/or mobile DDR.

Additionally, integrated circuits and/or memory components (such as a memory controller, a memory device, a memory module, and/or a memory system) that use these techniques may be included in a wide variety of applications, such as: desktop or laptop computers, computer systems, hand-held or portable devices (such as personal digital assistants and/or cellular telephones), set-top boxes, home networks, and/or video-game devices. For example, a storage device (such as the memory module) may be included in computer main memory. Moreover, one or more of these embodiments may be included in a communication channel, such as: serial or parallel links, metropolitan area networks, local area networks (LANs), and/or personal area networks (PANs).

Embodiments of a bimodal memory controller are now further described. Continuing the discussion ofFIG. 1A, one of the challenges associated with separate interface circuits112is presented by the general trend to minimize pin count and the number of input/output signals. In particular, for a given die, chip size or configuration, there may be limits on the number of bonding wires that can be used to connect to the die or chip. For example, for a given perimeter of a die, constraints on the bonding-wire pitch typically limit the maximum number of connections that can be made, for example, by bonding wires. Similarly, for implementations which rely on solder ball attachment, there are often limits on the number of solder balls that can carry signals.

As described further below, in some embodiments memory controller110-1may address the packaging and electrical constraints by positioning connectors114-1and114-2in physically separate (as opposed to interdigited) but adjacent groups of connectors that are parallel to the periphery of the die. Connectors in these groups may have the same pitch118. For example, the connectors may be bonding pads, which can be relatively small compared to bonding wire size for a conventional package that is used to mount an integrated circuit. These bonding pads may be positioned next to each other in a conventional profile such that the package may be electrically coupled to bonding pads in only one of the groups of the connectors, i.e., the pitch118may accommodate a single bonding wire. In this way, the memory controller110-1can accommodate two configurations (which are associated with a particular one of interface circuits112and connectors114) without using twice as many bonding wires or requiring an increase in the size of the chip or its periphery. Moreover, this configuration, in which one of multiple pads can be electrically coupled to a bonding wire, facilitates communication using alternate communication formats without introducing impedance problems that would occur if both of the bonding pads were electrically coupled to each other and the memory device130.

While the preceding example uses bonding pads as illustration, connectors114-1,114-2and116-1should be understood to include metal contacts, pads and other forms of electrical coupling of an integrated circuit to the outside world (such as pads for solder balls). Thus, these connectors should be understood to include any type of connector that would be suitable for this purpose.

Signal lines, links or wires that are coupled to one of the connectors114-1or114-2may be passed through a wired, routing channel120-1to external electrical path128. Moreover, the active one of the interface circuits112may communicate information on a single line or multiple lines in external electrical path128(such as those in a data bus, an address bus, or some other specific-purpose bus). For example, the active one of the interface circuits112may communicate information on a set of pins, for example, all data bus, data-bus and address, or any other set or subset of lines in a bus between memory controller110-1and memory device130. In some embodiments, signals are communicated via the external electrical path128using serial and/or parallel communication. Moreover, at least some of the signal lines, links or wires in the external electrical path128may be capable of bidirectional communication (such as half-duplex or full-duplex communication).

In some embodiments, memory controller110-1includes an optional state-specifying component122that specifies, based on the communication characteristics associated with memory device130, which of the interface circuits112is used during operation of the memory controller110-1. For example, the state-specifying device may include: a mode register that stores a state setting that indicates which of the interface circuits112is used; a fuse, whose state (open or closed) indicates which of the interface circuits112is used; a connector that receives a voltage (such as high or low) that indicates which of the interface circuits112is used; and/or a node electrically coupled to an optional initialization bus124, which receives state-specifying information that indicates which of the interface circuits112is used. Other forms of specifying the connection state between memory controller110-1and memory device130will also occur to those having familiarity with systems logic design.

Alternatively, memory controller110-1may include optional control logic126to determine whether connectors114-1or114-2are electrically coupled, respectively, to connectors116-1(and thus, to memory device130). Based on this determination, optional control logic126may activate the corresponding one of the interface circuits112, and, if desired, may deactivate the unused one of the interface circuits112.

In some embodiments, connectors114-1and116-3, as well as connectors114-2and116-2, are electrically coupled, but only one of these pairs, such as connectors114-1and116-3, is electrically coupled to memory device130. This is shown inFIG. 1B, which presents a block diagram of memory system150. In this system, only one of connectors116in an application-specific package160are electrically coupled by wired, routing channel120-1to connectors162-1, which, in turn, are electrically coupled to connectors162-2, and ultimately, to memory device130.

FIG. 2Ashows a side-view of an embodiment of a memory system200in which multiple alternative connectors are passed from memory controller210-1through to package208-1, and where the package208-1is relied upon to couple one alternative set of interface circuits to the external signal path128. In particular, the package208-1may be coupled to a die by a number of solder ball, such as solder ball214-1, where both sets of interface circuit are electrically coupled, via connectors212-1and212-2, to reciprocal pads or connectors216-1and216-3on the package208-1, but where the package208-1electrically couples only one set of these connectors to a printed circuit board220-1. In particular, a number of connectors212-1and212-2are each associated with one of at least two separate interface circuits. Each group of connectors212-1or212-2may be alternatively used to communicate information (using different communication formats) between a chip (such as a memory controller210-1) and external electrical path128in printed circuit board220-1via package208-1. Connectors212-1and212-2are electrically coupled to solder balls214(such as C4 balls), which are electrically coupled to reciprocal connectors216-1and216-3on package208-1. However, only one of these groups of reciprocal connectors (such as connectors216-1) are electrically coupled to connectors216-2, for example by the wired, routing channel120-1(which may run along a surface of package208-1and/or which may include vias in package208-1). In turn, connectors216-2are electrically coupled to connectors222-1by solder balls218(such as a ball grid array).

In another version of package208-1, connectors216-3(instead of connectors216-1) may be electrically coupled by the wired, routing channel120-1to connectors216-2, and thus, to the memory device (not shown). Consequently, memory systems150(FIG. 1B) and 200illustrates a configuration in which the same memory controller210-1and printed circuit board220-1support different memory devices and/or applications, which have different communication protocols, using an appropriate one of two alternative versions of package208-1.

In some embodiments, rather than selectively electrically coupling connectors216-1or connectors216-3to connectors216-2via wired, routing channel120-1, either connectors216-1or connectors216-3are electrically coupled to corresponding connectors212-2or connectors212-1, respectively. For example, in one embodiment, a solder ball may be deliberately omitted between some of these pairs of connectors in order to isolate an interface circuit in the controller. Alternatively, this approach may be implemented between some of connectors216-2and connectors222-1.

In yet another variation on this technique, the selective electrical coupling may be implemented in the printed circuit board (as opposed to the package). Thus, the same memory controller and package may be used with an appropriate one of two versions of the printed circuit board (depending on the communication format of the memory device). This is shown inFIG. 2B, which presents a block diagram illustrating an embodiment of a memory system250. In this system, package208-3is common to both communication formats (or applications), but only a subset of connectors216-2(which are electrically coupled to one of the two interface circuits in memory controller210-1, and which are electrically coupled to connectors222-1by solder balls218) are uniquely electrically coupled to the memory device (not shown). In particular, only a subset of the connectors222-1are electrically coupled to the external electrical path128.

While the preceding memory systems inFIGS. 2A-2Billustrate configurations where there are multiple versions of a package or a printed circuit board depending on the communication characteristics associated with the memory device, in other embodiments the package (inFIG. 2A) or the printed circuit board (inFIG. 2B) may also be common for different memory devices or applications having different communication formats. For example, this common component may have two orientations. In a first orientation, connectors may electrically couple one of the interface circuits in the memory controller to the memory device. And in a second orientation (such as one obtained by rotating the common component, in the plane of the connectors, by 180°), additional connectors may electrically couple the other of the interface circuits in the memory controller to the memory device. For example, by presenting an even number of mounting pads on the die-receiving side of a package, in a symmetrical arrangement, with every other pad coupled through-package to the printed circuit board, it might be possible to use one package configuration to support alternative connection schemes (e.g., by rotating the package through its direction of symmetry).

As noted previously, in some embodiments the selective electrical coupling is implemented using wire bonding. This is shown inFIG. 3A, which presents a block diagram illustrating an embodiment of a memory system300. In particular, bonding wire310-1may electrically couple only one of bonding-pad connectors312-1and312-5(in this example, bonding-pad connector312-1) on memory controller210-2(which is associated with one of the interface circuits) to bonding-pad connector312-2on circuit board220-2. (In contrast withFIG. 3A,FIG. 3Billustrates a memory system300in which bonding-pad connector312-5is electrically coupled to bonding-pad connector312-2by bonding wire310-1.) Bonding-pad connector312-2is electrically coupled to connector314-1, which is electrically coupled to connector314-2on printed circuit board220-3by solder ball218-2(such as a C4 ball or a ball in a ball grid array). In turn, connector314-2is electrically coupled to bonding-pad connector312-3, which is electrically coupled by bonding wire310-2to bonding-pad connector312-4on memory device316. In some embodiments, there may be additional instances of memory devices in a die stack that are, respectively, electrically coupled to one of two or more alternative interface circuits on memory controller210-2via a similar electrical path.

Note that using one bonding wire, such as bonding wire310-1, to electrically couple to only one of bonding-pad connectors312-1and312-5allows memory controller210-2to accommodate multiple communication formats without increasing the number of bonding wires electrically coupled to this memory controller (and, thus, without impacting the periphery requirement or cooling requirements of memory controller210-2).

In some embodiments, the alternative bonding-pad connectors may include single-ended and differential configurations. This is shown inFIG. 3C, which presents a block diagram illustrating an embodiment of a memory controller350. In particular, the wired pairs of pads on the left-hand side are, respectively, associated with differential output paths0and1for data (DQ) interface A. In contrast, the wired pads on the right-hand side inFIG. 3D, which presents a block diagram illustrating an embodiment of a memory controller370, show alternative single-ended output paths0-3for DQ interface B.

Another example of the alternative interface circuits and their associated bonding-pad connectors is shown inFIG. 3Epresents a block diagram illustrating an embodiment of a memory controller390. Note that these alternative interface circuits share a common multiplexer, as well as additional logic functions in memory controller390. Consequently, proximate bonding-pad connectors, associated with alternative interface circuits, allows these memory controllers to support multiple communication formats even when the bonding-wire connector pitch is sufficient to accommodate a single bonding wire. Moreover, by selectively electrically coupling only one set of the two or more alternative bonding-wire connectors to a memory device (and leaving the remaining bonding-wire connectors open), this approach permits the active one of the interface circuits to be used without having its performance affected by the impedance associated with the other interface circuits.

Embodiments of a given interface circuit in the memory controller (such as one of the memory controllers110inFIGS. 1A and 1B) are now described.FIG. 4presents a block diagram illustrating an embodiment400of an interface circuit410. Data412(and/or addresses and commands) to be transmitted by interface circuit410to a memory device is temporarily stored in memory buffer414-1. Then, the data412is forwarded to driver circuits (Tx)416, and is transmitted as (analog or digital) signals418onto wired, wireless, and/or optical links in a memory-system bus.

Similarly, signals426may be received from the memory device using receiver circuits (Rx)428, which include detection circuits (such as slicer circuits) to determine data432(and/or addresses and commands) from the signals426. (As noted previously, signals418and426may be electrically coupled to one group of alternative connectors, such as those in a package, and ultimately to an external path. In some embodiments, signals418and426are communicated via a bidirectional bus.) This data432may be temporarily stored in memory buffer414-2.

In interface circuit410, timing of the forwarding, driving, and/or receiving may be gated by one or more timing signals provided by clock distribution424. Consequently, signals418may be transmitted (or driven) and/or signals426may be received based on either or both edges in the one or more timing signals. Moreover, in some embodiments, transmitting and receiving may be synchronous and/or asynchronous.

These timing signals may be generated based on one or more clock signals422, which may be generated off-chip or on-chip (for example, using a phase-locked loop and one or more reference signals provided by a frequency reference, and which are communicated using a dedicated clock-forwarding link or by recovering an embedded clock signal). Moreover, voltage levels and/or a voltage swing of the signals418may be based on voltages420provided by a power supply (not shown), and logic levels of the data432may be based on voltages430provided by the power supply. These voltages may be fixed or may be adjustable.

As noted previously, the different interface circuits in the memory controller may correspond to different communication formats. Thus, driver and receiver circuits in one of the interface circuits may have a lower voltage swing, less input/output (I/O) capacitance, and/or a larger data rate than driver and receiver circuits in the other of the interface circuits. Consequently, to avoid the impedance associated with the other of the interface circuits impacting the one of the interface circuits, only the one of the interface circuits is electrically coupled to the external path. Moreover, the driver and receiver circuits in the two separate interface circuits may have different breakdown voltages and/or different electrostatic-discharge protection circuits.

The driver circuits in a first interface circuit may support a lower data rate, while a second interface circuit may support a higher data rate. Moreover, the first interface circuit may include: single-ended drivers, series-source termination, current-mode signaling, and/or strobed clocking. Additionally, the second interface circuit may include: differential drivers, parallel termination, voltage-mode signaling, and/or an adjustable transmit/receive clock signal.

Memory systems100(FIG. 1A),150(FIG. 1B),200(FIG. 2A),250(FIG. 2B),300(FIG. 3A),330(FIG. 3B),350(FIG. 3C),370(FIG. 3D),390(FIG. 3E), and/or interface circuit410may include fewer components or additional components. Moreover, two or more components may be combined into a single component and/or the position of one or more components may be changed.

Components and/or functionality illustrated in these embodiments may be implemented using analog circuits and/or digital circuits. Furthermore, the components and/or the functionality may be implemented using hardware and/or software. For example, memory controllers110(FIGS. 1A and 1B) may be included in a processor or a processor core.

In an exemplary embodiment, the first interface circuit in the memory controller supports up to 20 unidirectional single-ended links that operate at 0.4 Gb/s and 40 bidirectional single-ended links that operate at 0.8 Gb/s using a low-power DDR2 communication format. This is shown inFIG. 5Apresents a block diagram illustrating an embodiment of a memory system500. The communication format in memory system500may include: a low voltage of approximately 0.2 V, a high voltage of approximately 1.0 V, a VDDQ of approximately 1.2 V, an input capacitance of approximately 5 pF, and a signaling rate of up to 0.8 Gb/s.

The second interface circuit may support up to 24 differential links that operate at 3.2 Gb/s using an XDR communication format. This is shown inFIG. 5Bpresents a block diagram illustrating an embodiment of a memory system530. The communication format in memory system550may include: a low voltage of approximately 0.0.05 V, a high voltage of approximately 0.15 V, a VDDQ of approximately 0.2 V, an input capacitance of approximately 0.75 pF, and a signaling rate of up to 3.2 Gb/s.

Note that the bimodal memory controller that includes both of these interface circuits may use 3% more of the available die area than a unimodal memory controller, and the perimeter of the die may be unchanged.

Embodiments of processes for assembling a memory system and for operating a memory controller are now described.FIG. 6Apresents a flow chart illustrating an embodiment of a process600for assembling a memory system. During this method, a first set of signal connectors and corresponding first interface circuits to electrically couple at least part of a memory-controller I/O bus in a memory controller to at least part of an external, memory-system I/O bus is provided (610). Then, a second, alternative set of signal connectors and corresponding second interface circuits to electrically couple at least the part of the memory-controller I/O bus in a memory controller to at least the part of the external, memory-system I/O bus is provided (612). Next, the memory-controller I/O bus is selectively electrically coupled with the external, memory-system I/O bus using either the first set of signal connectors or the second set of signal connectors based on communication characteristics of the memory system (614), where a remaining set of signal connectors, which can be either the first set of signal connectors or the second set of signal connectors, remains selectively electrically uncoupled from the external, memory-system I/O bus.

FIG. 6Bpresents a flow chart illustrating an embodiment of a process650for operating a memory controller. During this method, which one of a first interface circuit and a second interface circuit to use to communicate signals via an external, electrical path is identified (660). Note that the first interface circuit communicates first signals having a first communication format and the second interface circuit communicates second signals having a second communication format. Moreover, the signals are communicated with the external electrical path using the identified interface circuit (662).

In some embodiments of the processes600(FIG. 6A) and/or650, there are fewer or additional operations. Moreover, two or more operations may be combined into a single operation and/or a position of one or more operations may be changed.

Devices and circuits described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. These software descriptions may be: behavioral, register transfer, logic component, transistor and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3½ inch floppy media, CDs, DVDs, and so on.

FIG. 7presents a block diagram illustrating an embodiment of a system700that stores such computer-readable files. This system may include at least one data processor or central processing unit (CPU)710, machine-readable storage medium724and one or more signal lines or communication buses722for coupling these components to one another. Machine-readable storage medium724may include high-speed random access memory and/or non-volatile memory, such as: ROM, RAM, EPROM, EEPROM, flash, one or more smart cards, one or more magnetic disc storage devices, and/or one or more optical storage devices.

Machine-readable storage medium724may store a circuit compiler726and circuit descriptions728. Circuit descriptions728may include descriptions of the circuits, or a subset of the circuits discussed above with respect toFIGS. 1A-5. In particular, circuit descriptions728may include circuit descriptions of: one or more memory controllers730, optional processors732, one or more memory devices734, one or more interface circuits736, one or more driver circuits738, one or more receiver circuits740, one or more packages742, one or more circuit boards744, optional control logic746, optional state-specifying components748, and/or one or more buses750.

In some embodiments, system700includes fewer or additional components. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed.