Semiconductor device and formation method thereof

A method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions.

BACKGROUND

DETAILED DESCRIPTION

In operation, current may not flow through the channel, and source/drain-to-substrate leakage may occur. Some existing transistor comes in forming silicon oxide materials at the source/drain region to prevent such leakage. However, silicon oxide materials have poor thermal conductivity. It may be difficult for heat generated by the source-to-drain current to dissipate into the substrate via the silicon oxide materials, resulting heat flowing towards channel, which has an effect on the performance and reliability of the transistor. In some cases, one or more anneal processes may be performed on the source/drain features to activate the dopants therein, which generates heat. The heat cannot dissipate into the substrate via the silicon oxide materials efficiently, leading to poor heat dissipation issues as well.

Therefore, embodiments of this disclosure provide a transistor having a thermal conductive layer at a source/drain region of the transistor. Heat generated by the source-to-drain current and/or the anneal process can be dissipated toward the substrate efficiently.

FIG.1is a perspective view of the semiconductor device100having a substrate100at one of various stages of fabrication according to an embodiment. In one embodiment, the substrate100includes a crystalline silicon substrate (e.g., wafer). In some alternative embodiments, the substrate100may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Further, the substrate100may include an epitaxial layer (epi-layer), may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure.

In some embodiments, the substrate100includes various doped regions. The substrate100may include a well region depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the well region may be doped with p-type or n-type dopants. For example, the well region may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The well region may be configured for an n-type fin field effect transistor (FinFET), or alternatively configured for a p-type FinFET. For an n-type filed effect (NFET) transistor, the well region should be doped with p-type dopants to form PN junctions. For a p-type filed effect (PFET) transistor, the well region should be doped with n-type dopants.

In one embodiment, a pad layer PD and a mask layer MK are formed on the substrate100. The pad layer PD may be a thin film including silicon oxide formed, for example, using a thermal oxidation process. The pad layer PD may act as an adhesion layer between the substrate100and the mask layer MK. The pad layer PD may also act as an etch stop layer for etching the mask layer MK. In at least one embodiment, the mask layer MK is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer MK is used as a hard mask during subsequent photolithography processes. A photo-sensitive layer PR0is formed on the mask layer MK and is then patterned, forming openings116in the photo-sensitive layer PR0.

The mask layer MK and the pad layer PD are etched through the openings116to expose the underlying substrate100. The exposed substrate100is then etched to form trenches TR in the substrate100, as illustrated inFIGS.2A-2C. Portions of the substrate100between the trenches TR form strips120. The trenches TR may be strips (viewed from in the top of the semiconductor device100) parallel to each other, and closely spaced with respect to each other. The photo-sensitive layer PR0is then removed, such as by an acceptable asking process. Next, a cleaning may be performed to remove a native oxide of the substrate100. The cleaning may be performed using diluted hydrofluoric (DHF) acid.FIG.2Afurther illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of the strip120, which corresponds toFIG.2B. Cross-section B-B′ is perpendicular to cross-section A-A′ and extends through a subsequently formed epitaxial source/drain regions of the FinFET, which corresponds toFIG.2C.

Liner oxide (not shown) is then optionally formed in the trenches TR. In an embodiment, liner oxide may be a thermal oxide. In some embodiments, liner oxide may be formed using in-situ steam generation (ISSG) and the like. The formation of liner oxide rounds corners of the trenches TR, which reduces the electrical fields, and hence improves the performance of the resulting integrated circuit.

The trenches TR are filled with a dielectric material. A chemical mechanical polish (CMP) is then performed, followed by the removal of the mask layer MK and the pad layer PD. The dielectric material is recessed by an etching step, resulting in recesses124. The remaining portions of the dielectric material in the trenches TR are hereinafter referred to as shallow trench insulation (STI) regions103. The resulting structure is shown inFIGS.3A-3C. The dielectric material may include silicon oxide, and hence is also referred to as oxide in the present disclosure. In some embodiments, other dielectric materials, such as silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or a low-K dielectric material, may also be used. In an embodiment, the oxide may be formed using a high-density-plasma (HDP) chemical vapor deposition (CVD) process, using silane (SiH4) and oxygen (O2) as reacting precursors. In other embodiments, the oxide may be formed using a sub-atmospheric CVD (SACVD) process or high aspect-ratio process (HARP), wherein process gases may comprise tetraethylorthosilicate (TEOS) and/or ozone (O3). In yet other embodiments, the oxide may be formed using a spin-on-dielectric (SOD) process, such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ).

In one embodiment, the etching step may be performed using a wet etching process, for example, by dipping the substrate100in hydrofluoric acid (HF). In another embodiment, the etching step may be performed using a dry etching process, for example, the dry etching process may be performed using CHF3or BF3as etching gases. Throughout the description, a portion of the strip120higher than a top surface of the STI regions126is referred to as a fin (or protruding fin)102. A portion of the strip lower than the fin102is referred to as punch-through stopper101. It is noted that the reference numerals101and102are omitted in perspective views throughout the description for clarity.

A dummy gate stack104is formed across the fin102and extends over the STI regions103, as shown inFIGS.4A-4C. The dummy gate stack104includes sacrificial material and optionally one or more additional layers. The additional layers may include interfacial layers, etch stop layers, and/or dielectric layers. The sacrificial material may be polysilicon. It is noted that the fin102has a portion covered by and below the dummy gate stack104and is referred to as a channel portion hereafter.

Next, referring toFIGS.5A-5B, after the dummy gate stack104is formed, a spacer layer105′ is formed as a blanket layer to cover the structure shown inFIGS.4A-4Cby conformally depositing, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. In some embodiments, the spacer layer105′ is made of one or more layers of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or other applicable dielectric materials. The spacer layer105′ is subsequently anisotropically etched to form gate spacers105along opposing sidewalls of the dummy gate stack104.

An etching step (referred to as source/drain recessing hereinafter) is then performed to etch the portions of the protruding fins102that are not covered by the dummy gate stack104and the gate spacers105, resulting in the structure shown inFIGS.6A-6C. The recessing may be anisotropic, and hence the portions of protruding fins102directly underlying the dummy gate stack104and the gate spacers105are protected, and are not etched. Top surfaces120A of the recessed strips120may be lower than the top surfaces103A of the STI regions103in accordance with some embodiments. Recesses40are accordingly formed between the STI regions103. The recesses40are located on opposite sides of the dummy gate stack104.

FIGS.7A-7Cillustrate formation of a mask layer106and a patterned photoresist PR1. The mask layer106is used as a hard mask during subsequent photolithography process. The mask layer106is filled into the recesses40(seeFIGS.6A-6C). The mask layer106may be formed of silicon nitride or the like using, for example, flowable CVD (FCVD), spin-on coating, CVD, or other deposition methods. A planarization step such as chemical mechanical polish (CMP) or mechanical grinding may be performed to level top surfaces of the mask layer106, the dummy gate stack104and the gate spacers105with each other. A photo-sensitive layer PR1is formed on the mask layer106and is then patterned, forming openings in the photo-sensitive layer PR1.

The mask layer106is etched through the openings to expose the underlying STI region103and the punch-through stopper101of the substrate100. Recesses42are accordingly formed in the STI regions103and are at opposite sides of the dummy gate stack104. The photo-sensitive layer PR1is then removed, such as by an acceptable ashing process, and then the mask layer106is removed by an etch process. The resulting structure is shown inFIGS.8A-8C. The substrate100(e.g., punch-through stopper101) is exposed.

Referring toFIGS.9A-9C. A thermal conductive layer108is formed to cover the structure shown inFIGS.8A-8C. The thermal conductive layer108fills into the recesses42(seeFIGS.8A-8C). The thermal conductive layer108has a high thermal conductivity, for example, greater than 1.4 W/m·K, which is the thermal conductivity of silicon oxide. If the thermal conductivity of the thermal conductive layer is less than 1.4 W/m·K, heat generated by the source-to-drain current may not be dissipated into the substrate100efficiently, leading to unwanted heat flowing toward the channel.

In some embodiments, the thermal conductive layer108is a dielectric layer, such as BeO, AlN, or chemical vapor deposited diamond. The thermal conductive layer108has an ability to tolerate high temperature. In some embodiments where the thermal conductive layer108includes BeO, the thermal conductive layer108can tolerate a temperature from 550° C. to 650° C. for 2 to 4 minutes, for example, of about 600° C. for 3 minutes. The thermal conductive layer108may be formed using ALD. In the ALD process, alternating cycles are performed. In one cycle, a precursor gas is turned on. In another cycle, an oxidant gas is turned on. These cycles are repeated for a number of times, which can be precisely controlled to grow a desired material with a desired thickness. In one embodiment, the precursor gas includes beryllium chloride (BeCl2), beryllium acetylacetonate (Be(acac), in which “acac” refers to CH3COCHCOCH3), dimethylberyllium (Be(CH3)2), or diethylberyllium (Be(C2H5)2). In some embodiments, the oxidant gas includes water (H2O), oxygen, or ozone. In this embodiment, the process temperature is in a range from 200° C. to 250° C.

In some embodiments where the thermal conductive layer108includes AlN, the thermal conductive layer108can tolerate a temperature from 600° C. to 700° C. for to 35 minutes, for example, of about 650° C. for 30 minutes. The thermal conductive layer108may be formed using ALD. In the ALD process, alternating cycles are performed. In one cycle, a precursor gas is turned on. In another cycle, a nitridant gas is turned on. These cycles are repeated for a number of times, which can be precisely controlled to grow a desired material with a desired thickness. In one embodiment, the precursor gas includes AlCl3, Trimethylaluminium (TMA) or triethylaluminum (TEA). In some embodiments, the nitridant gas includes NH3/Ar/H2gas mixture, N2H2, or N2H4. In this embodiment, the process temperature is in a range from 300° C. to 400° C., such as about 350° C.

InFIGS.10A-10C, the thermal conductive layer108is recessed in an etching step(s), so that recesses44are formed. The etching step(s) may include an anisotropic dry etch. For example, the etching step(s) may include a dry etch process using reaction gas(es) that selectively etch the thermal conductive layer108without etching the dummy gate stack104and the gate spacers105. The channel of the fin102is exposed by the thermal conductive layer108.

A photo-sensitive layer PR2is formed on the thermal conductive layer108and is then patterned, forming openings in the photo-sensitive layer PR2, as shown inFIGS.11A-11C.

Next, the thermal conductive layer108is patterned using a lithography process. For example, inFIGS.12A-12C, the thermal conductive layer108is etched through the openings. A recess46is formed in the thermal conductive layer108. The photo-sensitive layer PR2is then removed, such as by an acceptable ashing process. The thermal conductive layer108has a U-shaped profile when viewed in cross-section A-A′. The thermal conductive layer108still covers the punch-through stopper101of the substrate100after the lithography process in one example.

In some other embodiments, a portion of the thermal conductive layer108athat covers the punch-through stopper101of the substrate100is removed, as shown inFIG.12D. The punch-through stopper101is exposed by the thermal conductive layer108a. In some other embodiments, portions of the thermal conductive layer108bover the STI regions103are removed by the lithography process, so that the STI regions103are exposed, as shown inFIG.12E.

Epitaxial regions (source/drain regions)109are formed by selectively growing a semiconductor material in the recesses46, resulting in the structure inFIGS.13A-13C. In accordance with some exemplary embodiments, the epitaxy regions109include silicon germanium or silicon. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p-type or an n-type impurity may be in-situ doped with the proceeding of the epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorous (SiP) or silicon carbon phosphorous (SiCP) may be grown. In accordance with alternative embodiments of the present disclosure, the epitaxy regions109is formed of a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multi-layers thereof. After epitaxy regions109fully fill recesses46, epitaxy regions109start expanding horizontally, and facets may be formed.

After the epitaxy step, the epitaxy regions109may be further implanted with a p-type or an n-type impurity to form source and drain regions, which are also denoted using reference numeral109. In accordance with alternative embodiments of the present disclosure, the implantation step is skipped when the epitaxy regions109are in-situ doped with the p-type or n-type impurity during the epitaxy. The epitaxy regions109include lower portions109B that are formed in the STI regions103, and upper portions109A that are formed over the top surfaces103A of the STI regions103.

InFIGS.14A-14C, a thermal conductive layer119is formed on the structure inFIGS.13A-13C. A planarization step such as chemical vapor deposition (CMP) or mechanical grinding may be performed to level top surfaces of the thermal conductive layer119, the gate spacers105and the dummy gate stack104. The thermal conductive layer119has a similar material and formation method to the material and formation method of the thermal conductive layer108, so that the description thereof is not repeated herein.

Because the thermal conductive layers108,119have a high thermal conductivity, the heat generated by the source-to-drain current and/or the anneal process of forming the epitaxy regions109can be dissipated into the substrate100via the thermal conductive layers108,119efficiently. As a result, the performance and reliability of the semiconductor device10can be ensured.

The thermal conductive layer119surrounds the upper portion109A of the epitaxy region109. In this example, the thermal conductive layer108and the thermal conductive layer119collectively surround the epitaxy regions109. As a result, the thermal conductive layers108,119can enhance heat dissipation into the substrate100.

In some embodiments, the thermal conductive layer108has a thickness t1in a vertical direction from a bottom surface of the thermal conductive layer108to a bottom surface of the epitaxy regions109.

In some embodiment, the thickness t1is from 0 to 200 nm. In an example, the epitaxy regions109and the thermal conductive layer119are formed on the structure inFIG.12D, in which the resulting structure is shown inFIG.14D. InFIG.14D, the thickness t1equals 0 nm. The epitaxy regions109are in contact with the substrate100(e.g., the punch-through stopper101). Referring back toFIG.14C, the thermal conductive layers108,119collectively have a thickness t2in a vertical direction from a top surface of the STI regions103to the top surface of the thermal conductive layer119. The thickness t2is in a range from 0 nm to 200 nm. In an example, the epitaxy regions109are formed on the structure inFIG.12E, in which the resulting structure is shown inFIG.14E. InFIG.14E, the thickness t2equals 0 nm. That is, no thermal conductive layer is formed after the formation of the epitaxy regions109. The STI region103and the thermal conductive layer108bare substantially coplanar. Referring back toFIG.14C, in some embodiments, the thermal conductive layer108has a lateral thickness t3, which extends in a direction parallel to the dummy gate stack104, from 1 nm to 200 nm.

Next, the dummy gate stack104is replaced with a replacement gate stack layers which include an interfacial layer (IL)110, a high-k gate dielectric layer111and a metal gate112. The metal gate112is formed by depositing the IL110, the high-k gate dielectric layer111and the metal gate112followed by a planarization step such as CMP or mechanical grinding, so that the portions of IL110, the high-k gate dielectric layer111, and the metal gate112over the thermal conductive layer119are removed. As a result, the replacement gate stack113is formed. As shown inFIGS.15A-15C, top surfaces of the replacement gate stack113, the gate spacers105, and the thermal conductive layer119may be substantially coplanar at this time. The thermal conductive layer119laterally surrounds the replacement gate stack113.

The IL110is extends into the trenches. The IL110extends on the top surface of the fin102and along sidewalls of the gate spacers105. In accordance with some embodiments, the IL110includes an oxide layer such as a silicon oxide layer, which is formed through chemical vapor oxidation process, or a deposition process. The high-k gate dielectric layer111is formed overlying the IL110and includes a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k-value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0. The high-k gate dielectric layer111is in contact with the IL110and is formed as a conformal layer. In accordance with some embodiments, the high-k gate dielectric layer111is formed using ALD or CVD. In an example, the metal gate112may include tungsten. In some other embodiments, the metal gate112includes stacked layers including a diffusion barrier layer, one (or more) work-function layer over the diffusion barrier layer, and a fill metal layer over the work-function layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work-function layer determines the work function of the metal gate112, and includes at least one layer, or a plurality of layers formed of different materials. The specific material of the work-function layer is selected according to whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work-function layer may include a TaN layer and a titanium aluminum (TiAl) layer over the TaN layer. When the FinFET is a p-type FinFET, the work-function layer may include a TaN layer, a TiN layer over the TaN layer, and a TiAl layer over the TiN layer. After the deposition of the work-function layer(s), another barrier layer, which may be another TiN layer, is formed. The fill metal layer may be formed of cobalt (Co), or tungsten (W), for example.

FIGS.16A-17Billustrate the formation of source/drain contact plugs and gate contact plug. Referring toFIGS.16A-16B, an etch stop layer114is formed, followed by the formation of an interlayer dielectric layer (ILD)115. Throughout the description, the ILD layer115is alternately referred to as ILD1. The etch stop layer114may be formed of silicon carbide, silicon oxynitride, silicon carbo-nitride, combinations thereof, or composite layers thereof. The etch stop layer114may be formed using a deposition method such as CVD, Plasma Enhanced Chemical Vapor Deposition (PECVD), ALD, or the like. The ILD layer115may include a material selected from PSG, BSG, BPSG, Fluorine-doped Silicon Glass (FSG), TEOS, or other non-porous low-k dielectric materials. The ILD layer115may be formed using spin coating, FCVD, or the like, or formed using a deposition method such as CVD, PECVD, Low Pressure Chemical Vapor Deposition (LPCVD), or the like. Openings116are formed through the ILD layer115, the etch stop layer114and the thermal conductive layer119, such that the source/drain regions and the replacement gate stack are exposed to the openings.

Referring toFIGS.17A-17B, a contact metal layer is deposited in the openings116to form a gate contact117and source/drain contacts118extending down to the replacement gate stack113and the epitaxy regions109, respectively. The contact metal layer may include copper (Cu), aluminum (Al), tungsten (W), copper or copper alloy, such as copper magnesium (CuMn), copper aluminum (CuAl) or copper silicon (CuSi), or other suitable conductive material. The contact metal layer may be deposited by physical vapor deposition (PVD), CVD, metal-organic chemical vapor deposition (MOCVD), or plating. Additionally, a CMP is performed to etch back the excessive contact metal layer to provide a substantially planar surface.

FIGS.18-28show cross-sectional representations of various stages of forming an integrated circuit structure20in accordance with some embodiments of the disclosure. Referring toFIG.18, the integrated circuit structure20has a substrate204having a front-side204A and a back-side204B opposite to each other. The integrated circuit structure20includes a front-end-of line stack203and a back-end-of-line stack202, which are both formed on the front-side204A of the substrate204. The front-end-of-line stack203includes one or more semiconductor devices10a. Each of the semiconductor devices10ais similar to the semiconductor device10inFIGS.17A-17B, and the description thereof is omitted.

The back-end-of-line stack202may include interconnect structures electrically connected to conductive features (e.g., gate contacts117and source/drain contacts118) of the semiconductor devices10a. The interconnect structure includes conductive features202a, such as conductive lines, vias, and at least one conductive pad205, formed in an insulating material2026. As shown inFIG.18, devices, such as the semiconductor devices10aincluding a metal gate112, are formed in the front-side204A of the substrate204while no devices are formed in the back-side204B of substrate204. The metal routings of the conductive features202ashown inFIG.18are merely examples. Alternatively, other designs of metal routings of conductive features202amay be used according to actual application.

As shown inFIG.18, the integrated circuit structure20is turned upside down and bonded to a carrier substrate200through an adhesive layer201, in accordance with some embodiments. As a result, the front-side204A of the substrate204faces the carrier substrate170. In some embodiments, the carrier substrate200is used as a temporary substrate. The temporary substrate provides mechanical and structural support during a subsequent thinning process, which will be described in more detail later. In this example, the carrier substrate100is silicon. In some other embodiments, the carrier substrate200is made of glass material, semiconductor material, ceramic material, polymer material, metal material, another suitable material, or a combination thereof.

In some embodiments, the adhesive layer201is used as a temporary adhesive layer. The adhesive layer201may be made of glue, or may be a lamination material, such as a foil. In some embodiments, the adhesive layer201is photosensitive and is easily detached from the carrier substrate200by light irradiation. For example, shining ultra-violet (UV) light or laser light on the carrier substrate200is used to detach the adhesive layer201. In some embodiments, the adhesive layer201is a light-to-heat-conversion (LTHC) coating. In some other embodiments, the adhesive layer201is heat-sensitive and is easily detached from the carrier substrate200when it is exposed to heat.

Afterwards, a mask layer206is formed on the substrate204. In at least one embodiment, the mask layer206is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer206is used as a hard mask during subsequent photolithography processes. A photo-sensitive layer207is formed on the mask layer206and is then patterned, forming an opening214in the photo-sensitive layer207. The mask layer206is etched through the opening214to expose the underlying substrate204. The exposed substrate204is then etched to form a through substrate via (TSV) opening215. The resulting structure is shown inFIG.20. A top portion of the back-end-of-line stack202is removed. The TSV opening215exposes sidewalls of the substrate204and a top of the back-end-of-line stack202. In one example, the conductive features202aare exposed by the TSV opening215.

Next, the photo-sensitive layer114is then removed, such by an acceptable ashing process. The mask layer206is then removed by etch, as shown inFIG.21. Reference is made toFIG.21. A dielectric layer208is formed as a blanket layer to cover a surface and the sidewalls of the substrate204and the top of the back-end-of-line stack202. In some embodiments, the dielectric layer208includes silicon oxide and can be formed by atomic layer deposition.

Referring toFIG.22, an etch stop layer209is formed over the dielectric layer208using a non-conformal deposition method, for example, plasma enhanced chemical vapor deposition. The etch stop layer209and the dielectric layer208have different materials. In one example, the etch stop layer209can include silicon nitride. The etch stop layer209acts to stop a subsequent etch process at a desired interface.

InFIG.23, the dielectric layer208at the bottom of the TSV opening215is removed using an etch process to expose the top of back-end-of-line stack202. One of the semiconductor devices10aclosest to the TSV opening215has an edge10aeopposite to an edge215eof the TSV opening215. In an example, the edge10aerefers to an edge of the epitaxy region109. In some embodiments, a lateral distance d1between the edges215e,10aeis from 0.1 μm to 100 μm, such as 1 μm. The distance d1is controlled to ensure a sufficient space for a desired number of semiconductor devices be placed and avoid an unwanted stress applied to the semiconductor devices10a. If the lateral distance d1is lower than 0.1 μm, a subsequently formed TSV may affect device performance. If the lateral distance d1is greater than 100 μm, the device density will decrease.

InFIG.24, a diffusion barrier layer210is formed on sidewalls of the TSV opening215to act as an isolation layer, such that subsequently formed conductive materials of TSV and the substrate204do not directly contact with each other. The diffusion barrier layer208is conformally formed on the etch stop layer209, the dielectric layer208and the top of the back-end-of-line stack202(e.g., on the bottom of the TSV opening215). The diffusion barrier layer210is used to prevent conductive materials of the TSV, which will be formed later, from migrating to device regions (e.g., the front-end-of-line stack203and the back-end-of-line stack202). After the diffusion barrier layer210is formed, a copper seed layer211is formed lining the diffusion barrier layer210. In some embodiments, the diffusion barrier layer210is made of Ta, TaN, Ti, TiN or CoW. In some embodiments, diffusion barrier layer210is formed by a physically vapor deposition (PVD) process. In some embodiments, diffusion barrier layer210is formed by plating.

InFIG.25, a conductive material212is formed to fill into the TSV opening215(seeFIG.24) using an electroplating process, such as an electrochemical deposition (ECD) process, or the like. In some embodiments, the conductive material212is made of copper, copper alloy, aluminum, aluminum alloys, or combinations thereof. Alternatively, other applicable materials may be used. The conductive material212can help heat generated by the source-to-drain current dissipate into the substrate204. As mentioned above, the thermal conductive layers108,119can help dissipate heat as well. As a result, the performance and reliability of integrated circuit structure20can be ensured.

Afterwards, the excess diffusion barrier layer210, seed layer211and conductive material212are removed by a planarization process, such as a chemical mechanical polishing (CMP) process, until the etch stop layer209is exposed. The resulting structure is shown inFIG.26. The diffusion barrier layer210, the seed layer211and the conductive material212collectively refer to a through substrate via (TSV)216. The TSV216can help heat generated by the source-to-drain current dissipate into the substrate204. As mentioned above, the thermal conductive layers108,119can help dissipate heat as well. As a result, the performance and reliability of the integrated circuit structure20can be ensured.

Referring toFIG.27, subsequently, a redistribution layer (RDL)213is formed over the TSV216, in accordance with some embodiments.

In some embodiments, the RDL213includes copper. Examples of the material of the RDL213include Cu, Al, W, titanium (Ti), tantalum (Ta), another suitable material, or a combination thereof. In some embodiments, the RDL213are formed by an electroplating process, an electroless plating process, a sputtering process, a CVD process, or another applicable process. In some other embodiments, the RDL213may include one or more passivation layers and one or more conductive layers. The RDL213may have solder balls (not shown) placed on to be electrically connect to external contact pads.

Afterwards, the carrier substrate200and the adhesive layer201are removed. Suitable light may be provided to remove the adhesive layer201so as to lift off the carrier substrate200as well. The resulting structure is shown inFIG.28. The conductive pad205is exposed. The resulting integrated circuit structure20may then be bonded to other package component via the conductive pad205.

Based on the above discussions, it can be seen that the present disclosure in various embodiments offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that by using the thermal conductive layer, the heat generated by the source-to-drain current and/or the anneal process of forming the epitaxy regions can be dissipated into the substrate via the thermal conductive layer efficiently. Another advantage is that the thermal conductive layers can collectively surround the epitaxy regions to enhance heat dissipation into the substrate.

In some embodiments, a method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions. In some embodiments, the first thermal conductive layer is made of BeO, AlN, or chemical vapor deposited diamond. In some embodiments, the first thermal conductive layer has a thermal conductivity of greater than 1.4 W/m·K. In some embodiments, forming the first thermal conductive layer comprises depositing a first thermal conductive material filling into the recess in the STI regions and etching back the first thermal conductive material. In some embodiments, forming the first thermal conductive layer further comprises forming a patterned photoresist over the etched back first thermal conductive material and etching the first thermal conductive material using the patterned photoresist as a mask. In some embodiments, the method further includes forming a second thermal conductive layer covering the source/drain epitaxy structure. In some embodiments, the second thermal conductive layer and the first thermal conductive layer collectively surround the source/drain epitaxy structure. In some embodiments, the second thermal conductive layer includes BeO, AlN, or chemical vapor deposited diamond.

In some embodiments, a method of forming a semiconductor device includes forming a semiconductor strip extending above a front-side of a semiconductor substrate, wherein the semiconductor substrate has a back-side opposite to the front-side, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, forming a dielectric layer on the recessed portion of the semiconductor strip, forming a source/drain epitaxy structure on dielectric layer, wherein the source/drain epitaxy structure is in contact with the dielectric layer, and forming a gate stack across the semiconductor strip and extending over the STI regions. In some embodiments, the dielectric layer has a thermal conductivity greater than a thermal conductivity of silicon oxide. In some embodiments, the recessed portion of the semiconductor strip is separated with the source/drain epitaxy structure by the dielectric layer. In some embodiments, the dielectric layer has a U-shaped profile when viewed from cross-section. In some embodiments, the method further includes after recessing a portion of the semiconductor strip, forming a mask layer on the STI regions, forming a patterned photoresist over the mask layer, and etching the STI regions using the mask layer and the patterned photoresist as an etch mask to form a recess in the STI regions. In some embodiments, forming the dielectric layer is performed using atomic layer deposition, chemical vapor deposition, or physical vapor deposition. In some embodiments, the method further includes forming a back-end-of-line (BEOL) stack on the front-side of the semiconductor substrate, wherein the BEOL stack is electrically connected to the gate stack or the source/drain epitaxy structure, and forming a through substrate via (TSV) penetrating from the back-side of the semiconductor substrate into the semiconductor substrate, wherein the TSV is electrically connected to the BEOL stack.

In some embodiments, a semiconductor device includes a semiconductor strip on a front-side of a semiconductor substrate, shallow trench isolation (STI) regions on the semiconductor substrate, a gate crossing the semiconductor strip, source/drain epitaxy structures on opposite sides of the gate, and a thermal conductive layer at least laterally surrounding a bottom of the source/drain epitaxy structure, wherein the thermal conductive layer has a thermal conductivity greater than 1.4 W/m·K. In some embodiments, the thermal conductive layer has a portion between the semiconductor strip and the source/drain epitaxy structures in a vertical direction. In some embodiments, the thermal conductive layer covers a top of the source/drain epitaxy structures. In some embodiments, the thermal conductive layer is BeO, AlN, or chemical vapor deposited diamond. In some embodiments, the semiconductor device further includes a back-end-of-line (BEOL) stack on a front-side of the semiconductor substrate and being electrically connected to the gate or the source/drain epitaxy structures, and a through-substrate via (TSV) penetrating through a back-side of the semiconductor substrate opposite to the front-side, wherein the TSV has a first edge opposite to a second edge of the source/drain epitaxy structures, and the first edge and the second edge have a lateral distance in a range from 0.1 μm to 100 μm.