THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

BACKGROUND

The present disclosure relates to three-dimensional (3D) memory devices and fabrication methods thereof.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

SUMMARY

In one aspect, a method for forming a 3D memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

In some implementations, dummy channel structures extending through the first dielectric layers and the second dielectric layers in the second region of the stack structure are formed in a same process of forming the channel structures.

In some implementations, to replace, a slit extending through the first dielectric layers and the second dielectric layers and across the first region and the second region of the stack structure is formed before forming the word line pick-up structures.

In some implementations, to replace, the slit in the second region of the stack structure is covered, all the second dielectric layers in the first region of the stack structure in the first region of the stack structure are removed through the slit, the slit in the second region of the stack structure is opened, the parts of the second dielectric layers in the second region of the stack structure are removed through the slit in the second region of the stack structure, and the conductive layers are deposited through the slit in the first region and the second region of the stack structure.

In some implementations, to replace, the slit in the first region of the stack structure is covered, the parts of the second dielectric layers in the second region of the stack structure in the second region of the stack structure are removed through the slit, the slit in the first region of the stack structure is opened, the slit in the second region of the stack structure is covered, all the second dielectric layers in the first region of the stack structure are removed through the slit in the first region of the stack structure, the slit in the second region of the stack structure is opened, and the conductive layers are deposited through the slit in the first region and the second region of the stack structure.

In some implementations, a first spacer is formed in the slit before forming the word line pick-up structures.

In some implementations, to form the word line pick-up structures, word line pick-up openings extending through the first dielectric layers and the remainders of the second dielectric layers in the second region of the stack structure are formed at different depths to expose the remainders of the second dielectric layers in the second regions of the stack structure, respectively, parts of the remainders of the second dielectric layers in the second region of the stack structure are replaced, through the word line pick-up openings, with interconnect lines, respectively, such that the interconnect lines are in contact with the conductive layers, respectively, in the second region of the stack structure, and vertical contacts in the word line pick-up openings are formed in contact with the interconnect lines, respectively.

In some implementations, to form the word line pick-up structures, a second spacer is formed on sidewalls and a bottom of each of the word line pick-up openings, the second spacer on the bottom of the word line pick-up opening is removed to expose the respective part of the remainder of the second dielectric layer, and a filler is formed in the word line pick-up opening after forming the respective vertical contact.

In some implementations, to replace the parts of the second dielectric layers with the interconnect lines, the exposed part of the remainder of the second dielectric layer is etched through the word line pick-up opening to expose the respective conductive layer in the second region of the stack structure, and the respective interconnect line is deposited through the word line pick-up opening to be in contact with the exposed respective conductive layer in the second region of the stack structure.

In some implementations, to replace all the second dielectric layers and the parts of the second dielectric layers with the conductive layers, high dielectric constant (high-k) gate dielectric layers are deposited, such that the conductive layers are surrounded by the high-k gate dielectric layers, respectively. In some implementations, to replace the parts of the second dielectric layers with the interconnect lines, the exposed part of the remainder of the second dielectric layer is etched to expose the respective high-k gate dielectric layer, the exposed high-k gate dielectric layer is etched to expose the respective conductive layer, and the respective interconnect line is deposited to be in contact with the exposed respective conductive layer.

In another aspect, a 3D memory device includes a first stack structure including interleaved conductive layers and first dielectric layers, a second stack structure including interleaved second dielectric layers and the first dielectric layers, dummy channel structures extending through the first stack structure, and word line pick-up structures extending into the second stack structure at different depths. Each of the word line pick-up structures includes a vertical contact, and an interconnect line in contact with the vertical contact and a respective one of the conductive layers in the first stack structure.

In some implementations, dummy channel structures extending through the first dielectric layers and the second dielectric layers in the second region of the stack structure are formed in a same process of forming the channel structures.

In some implementations, to form the word line pick-up structures, word line pick-up openings extending through the first dielectric layers and the second dielectric layers in the second region of the stack structure are formed at different depths to expose the second dielectric layers in the second regions of the stack structure, respectively, parts of the second dielectric layers in the second region of the stack structure are replaced, through the word line pick-up openings, with interconnect lines, respectively, and vertical contacts in the word line pick-up openings are formed in contact with the interconnect lines, respectively.

In some implementations, to form the word line pick-up structures, a second spacer is formed on sidewalls and a bottom of each of the word line pick-up openings, the second spacer on the bottom of the word line pick-up opening is removed to expose the respective part of the second dielectric layer, and a filler is formed in the word line pick-up opening after forming the respective vertical contact.

In some implementations, to replace the parts of the second dielectric layers with the interconnect lines, the exposed part of the remainder of the second dielectric layer is etched through the word line pick-up opening, and the respective interconnect line is deposited through the word line pick-up opening.

In some implementations, to replace all the second dielectric layers and the parts of the second dielectric layers with the conductive layers, a slit extending through the first dielectric layers and the second dielectric layers and across the first region and the second region of the stack structure is formed after forming the word line pick-up structures.

In some implementations, to replace all the second dielectric layers and the parts of the second dielectric layers with the conductive layers, the slit in the second region of the stack structure is covered, all the second dielectric layers in the first region of the stack structure in the first region of the stack structure are removed through the slit, the slit in the second region of the stack structure is opened, the parts of the second dielectric layers in the second region of the stack structure are removed through the slit in the second region of the stack structure to expose the interconnect lines of the word line pick-up structures, and the conductive layers are deposited through the slit in the first region and the second region of the stack structure to be in contact with the interconnect lines of the word line pick-up structures, respectively, in the second region of the stack structure.

In some implementations, to replace all the second dielectric layers and the parts of the second dielectric layers with the conductive layers, the slit in the first region of the stack structure is covered, the parts the second dielectric layers in the second region of the stack structure in the second region of the stack structure are removed through the slit to expose the interconnect lines of the word line pick-up structures, the slit in the first region of the stack structure is opened, the slit in the second region of the stack structure is covered, all the second dielectric layers in the first region of the stack structure are removed through the slit in the first region of the stack structure, the slit in the second region of the stack structure is opened, and the conductive layers are deposited through the slit in the first region and the second region of the stack structure to be in contact with the interconnect lines of the word line pick-up structures, respectively, in the second region of the stack structure.

In some implementations, a first spacer is formed in the slit before forming the word line pick-up structures.

In some implementations, to form the channel structures, a high-k gate dielectric layer, a memory layer, and a channel layer are sequentially formed.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In some 3D memory devices, such as 3D NAND memory devices, memory cells for storing data are vertically stacked through a stack structure (e.g., a memory stack) in vertical channel structures. 3D memory devices usually include staircase structures formed on one or more sides (edges), or at the center, of the stacked storage structure for purposes such as word line pick-up/fan-out using word line contacts landed onto different steps/levels of a staircase structure. Dummy channel structures are usually formed through the memory stack in regions outside of the core array region in which the channel structures of 3D NAND memory devices are formed, such as staircase regions having the staircase structures, to provide mechanical support to the stack structure, in particular, during the gate replacement process that temporarily removes some layers of the stack structure through slit openings across the core array region and staircase regions of the stack structure.

The integration of the various structures, such as dummy channel structures, word lien contacts, staircase structures, slit openings, etc., from both the device design perspective and the fabrication process perspective, has become more and more challenging as the memory cell density of the 3D NAND memory devices continues increasing.

To address one or more of the aforementioned issues, the present disclosure introduces a solution that achieves the word line pick-up/fan-out functions without using staircase structures and word line contacts. The present disclosure can use a relatively simple single process of making word line pickup structures to replace the relatively complicated multiple processes of making staircase structures and word line contacts. That is, the two structures-staircase structure and word line contact, as well as their separate processes, can be merged into a single word line pick-structure in one process, thereby reducing the manufacturing cost and simplifying the process. Moreover, by replacing staircase structures and word line contacts with word line pick-structures, the scope of the gate replacement process can be reduced, such that at least some of the dummy channel structures can be eliminated as well to further reduce the cost and simplify the process.

FIG.1illustrates a plan view of a 3D memory device100having word line pick-up structures106, according to some aspects of the present disclosure. In some implementations, 3D memory device100is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. It is noted that x and y axes are included inFIG.1to illustrate two orthogonal (perpendicular) directions in the wafer plane. The x-direction is the word line direction of 3D memory device100, and the y-direction is the bit line direction of 3D memory device100.

As shown inFIG.1, 3D memory device100can include one or more blocks102arranged in the y-direction (the bit line direction) separated by parallel slit structures108, such as gate line slits (GLSs). In some implementations in which 3D memory device100is a NAND Flash memory device, each block102is the smallest erasable unit of the NAND Flash memory device. Each block102can further include multiple fingers104in the y-direction separated by some of slit structures108with “H” cuts109.

As shown inFIG.1, 3D memory device100can be divided into at least a core array region101in which an array of channel structures110are formed, as well as a word line pick-up region103in which word line pick-up structures106are formed. Core array region101and word line pick-up region103are arranged in the x-direction (the word line direction), according to some implementations. It is understood that although one core array region101and one word line pick-up region103are illustrated inFIG.1, multiple core array regions101and/or multiple word line pick-up regions103may be included in 3D memory device100, for example, one word line pick-up region103between two core array regions101in the x-direction, in other examples. It is also understood thatFIG.1only illustrates portions of core array region101that are adjacent to word line pick-up region103.

As described below in detail, word line pick-up region103can include conductive portions105and dielectric portions107arranged in they-direction. As shown inFIG.1, word line pick-up structures106are disposed in dielectric portion107, while dummy channel structures112are disposed in conductive portion105of word line pick-up region103to provide mechanical support and/or load balancing, according to some implementations. In some implementations (e.g., as shown inFIG.1), dummy channel structures112are disposed in dielectric portion107of word line pick-up region103as well, for example, between word line pick-up structures106in the x-direction. In some implementations, dummy channel structures112are not disposed in dielectric portion107of word line pick-up region103, i.e., only in conductive portion105of word line pick-up region103. As shown inFIG.1, each finger104of 3D memory device100can include one row of word line pick-up structures106disposed in dielectric portion107of word line pick-up region103. It is understood that the layout and arrangement of word line pick-up structures106, as well as the shape of each word line pick-up structure106, may vary in different examples.

FIG.2illustrates a top perspective view of 3D memory device100having word line pick-up structures106, according to some aspects of the present disclosure.FIG.3illustrates an enlarged top perspective view of 3D memory device100having word line pick-up structures106, according to some aspects of the present disclosure. As shown inFIGS.2and3, a stack structure201can be formed on a substrate203, which can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials. In some implementations, substrate203includes single crystalline silicon, which is part of the wafer on which 3D memory device100is fabricated, either in its native thickness or being thinned. In some implementations, substrate203includes, for example, polysilicon, which is a semiconductor layer replacing the part of wafer on which 3D memory device100is fabricated. It is noted that x, y, and z axes are included inFIGS.2and3to further illustrate the spatial relationship of the components in 3D memory device100. Substrate203of 3D memory device100includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer on which stack structure201can be formed, and a bottom surface on the backside opposite to the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or a device) is “on,” “above,” or “below” another component (e.g., a layer or a device) of 3D memory device100is determined relative to substrate203of 3D memory device100in the z-direction (the vertical direction perpendicular to the x-y plane) when substrate203is positioned in the lowest plane of 3D memory device100in the z-direction. The same notion for describing the spatial relationship is applied throughout the present disclosure.

As shown inFIG.3, stack structure201can include vertically interleaved first material layers302and second material layers304that are different from first material layers302. First material layers302and second material layers304can alternate in the vertical direction (the z-direction). In some implementations, stack structure201can include a plurality of material layer pairs stacked vertically in the z-direction, each of which includes first material layer302and second material layer304. The number of the material layer pairs in stack structure201can determine the number of memory cells in 3D memory device100.

In some implementations, 3D memory device100is a NAND Flash memory device, and stack structure201is a stacked storage structure through which NAND memory strings are formed. As shown inFIG.3, second material layers304can have different materials in different regions/portions of 3D memory device100. Thus, stack structure201may be viewed as having a number of stack structures with different materials of second material layers304for ease of description in the present disclosure. In some implementations, core array region101and conductive portion105of word line pick-up region103include a conductive stack structure having interleaved conductive layers and first dielectric layers. That is, second material layers304of stack structure201may be conductive layers in core array region101and conductive portion105of word line pick-up region103. In some implementations, dielectric portion107of word line pick-up region103includes a dielectric stack structure having interleaved second dielectric layers and the first dielectric layers. That is, second material layers304of stack structure201may be the second dielectric layers in dielectric portion107of word line pick-up region103. First material layers302of stack structure may be the same—the first dielectric layers—in the conductive stack structure and the dielectric stack structure across core array region101and word line pick-up region103. As described below in detail with respect to the fabrication process, the formation of stack structure201with different materials of second material layer304in different regions/portions can be achieved by controlling the different degrees and scopes of the gate replacement process in different regions/portions. For example, stack structure201may have undergone a complete gate replacement process in core array region101to replace all the second dielectric layers with the conductive layers, but a partial gate replacement process in word line pick-up region103to replace some of the second dielectric layers with the conductive layers in conductive portion105, leaving the remainders of the second dielectric layers in dielectric portion107.

In some implementations, each conductive layer in the conductive stack structure in core array region101and conductive portion105of word line pick-up region103functions as a gate line of the NAND memory strings (in the forms of channel structures110) in core array region101, as well as a word line extending laterally from the gate line and ending in conductive portion105of word line pick-up region103for word line pick-up/fan-out through word line pick-up structures106. The word lines (i.e., the conductive layers) at different depths/level of the conductive stack structure each extends laterally in core array region101and conductive portion105of word line pick-up region103, but are discontinuous (e.g., being replaced by the second dielectric layers) in dielectric portion107of word line pick-up region103, according to some implementations.

The conductive layers can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon (polysilicon), doped silicon, silicides, or any combination thereof. The dielectric layers can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The first dielectric layers and the second dielectric layers can have different dielectric materials, such as silicon oxide and silicon nitride. In some implementations, the conductive layers include metals, such as tungsten, the first dielectric layers include silicon oxide, and the second dielectric layers include silicon nitride. For example, first material layers302of stack structure201may include silicon oxide across core array region101and word line pick-up region103, and second material layers304of stack structure201may include tungsten in core array region101and conductive portion105of word line pick-up region103and silicon nitride in dielectric portion107of word line pick-up region103.

As shown inFIGS.2and3, the heights of stack structure201(e.g., the conductive stack structure and the dielectric stack structure) are uniform in core array region101and in word line pick-up region103, according to some implementations. Different from some 3D memory devices that include one or more staircase structures in a staircase region (corresponding to word line pick-up region103for word line pick-up/fan-out), which has uniform heights of the stack structure in the staircase region, 3D memory device100can eliminate the staircase structures while still achieving the word line pick-up/fan-out function using word line pick-up structures106, as described below in detail.

FIG.4illustrates a cross-sectional side view of 3D memory device100having word line pick-up structures106, according to some aspects of the present disclosure. The cross-section may be along the AA direction in dielectric portion107of word line pick-up region103inFIG.1. As shown inFIG.4, word line pick-up structures106extend vertically into stack structure201(the dielectric stack structure in dielectric portion107of word line pick-up region103) at different depths in the z-direction, according to some implementations. The top surfaces of different word line pick-up structures106can be flush with one another, while the bottom surfaces of different word line pick-up structures106can extend to different levels, for example, different second material layers304of stack structure201.

In some implementations, word line pick-up structure106includes a vertical contact202, a contact spacer204circumscribing vertical contact202, and an interconnect line206below and in contact with vertical contact202. Vertical contact202and interconnect line206can include conductive materials including, but not limited to, W, Co, Cu, Al, TiN, polysilicon, doped silicon, silicides, or any combination thereof. Contact spacer204can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some implementations, vertical contact202and interconnect line206include TiN/W, and contact spacer204includes silicon oxide.

FIG.5illustrates cross-sectional side views of 3D memory device100having word line pick-up structures106, according to some aspects of the present disclosure. One cross-section may be along the BB direction in core array region101inFIG.1, and another cross-section may be along the CC direction in word line pick-up region103inFIG.1. As shown inFIG.5, 3D memory device100can include channel structures110in core array region101. Each channel structure110can extend vertically through interleaved conductive layers502(word lines, e.g., tungsten) and first dielectric layers503(e.g., silicon oxide) of the conductive stack structure of stack structure201into substrate203. 3D memory device100can also include dummy channel structures112in conductive portion105of word line pick-up region103. Each dummy channel structure112can extend vertically through interleaved conductive layers502and first dielectric layers503of the conductive stack structure of stack structure201into substrate203. 3D memory device100can further include slit structures108across core array region101and core array region101. Each slit structure108can extend vertically through interleaved conductive layers502and first dielectric layers503of the conductive stack structure of stack structure201into substrate203as well.

As shown inFIG.5, slit structure108can include a slit spacer509that separate conductive layers502(word lines) between different blocks102. In some implementations, slit structure108is an insulating structure that does not include any contact therein (i.e., not functioning as the source contact) and thus, does not introduce parasitic capacitance and leakage current with conductive layers502(word lines). In some implementations, slit structure108is a front-side source contact further including a conductive portion (e.g., including W, polysilicon, and/or TiN) circumscribed by slit spacer509. As described below in detail, during the gate replacement process, the slit in which slit structure108is formed can serve as the passageway and starting point for forming conductive layers502. As a result, slit structure108is surrounded by conductive layers502in either core array region101or conductive portion105of word line pick-up region103.

As shown inFIG.5, in some implementations, 3D memory device300further includes a plurality of drain select gate (DSG) channel structures507above and in contact with the upper ends of channel structures110, respectively. 3D memory device300can further includes a DSG layer504including a semiconductor layer (e.g., polysilicon layer) on stack structure201in core array region101, but not in word line pick-up region105, for example, as shown inFIG.5. Each DSG channel structure507can extend vertically through DSG layer504to be in contact with the upper end of a corresponding channel structure110. In some implementations, 3D memory device300further includes a stop layer511(e.g., silicon nitride layer) on DSG layer504. DSG channel structure507can include a semiconductor layer (e.g., polysilicon) and a spacer surrounding the semiconductor layer. In some implementations, 3D memory device300includes a DSG stack including one or more DSG layers and one or more dielectric layers (e.g., silicon oxide layers) interleaved stacked above stack structure201.

As shown inFIG.5, 3D memory device100can further include a local contact layer above stop layer511and stack structure201. In some implementations, the local contact layer includes various local contacts, such as channel contacts506(a.k.a. bit line contacts) above and in contact with DSG structures507in core array region101. The local contact layer can further include one or more interlayer dielectric (ILD) layers (also known as “intermetal dielectric (IMD) layers”) in which the local contacts can form. Channel contacts506in the local contact layer can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers the in local contact layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

Instead of having staircase structures and word line contacts landed on different levels/stairs of the staircase structures, 3D memory device100can include stack structure201with uniform heights and word line pick-up structures106in dielectric portion107of word line pick-up region103for word line pick-up/fan-out. As shown inFIG.5, interconnect line206of each word line pick-up structure106in dielectric portion107can extend laterally in they-direction (the bit line direction) to be in contact with a corresponding conductive layer502(word line) in conductive portion105at the same level of stack structure201. Since interconnect line206is in contact with vertical contact202of word line pick-up structure106, each word line pick-up structure106is electrically connected to corresponding conductive layer502(word line) across conductive portion105in word line pick-up region103and core array region101, according to some implementations. In other words, word line pick-up structures106can extend vertically through stack structure201at different depths to be electrically connected to the word lines at different levels, respectively, to achieve word line pick-up/fan-out.

As described below in detail, during the gate replacement process, some of second dielectric layers505(e.g., silicon nitride) remain intact, thereby forming the dielectric stack structure of stack structure201in dielectric portion107of word line pick-up region103, and word line pick-up structure106is formed by etching first and second dielectric layers503and505in dielectric portion107of word line pick-up region103. As a result, word line pick-up structures106extend into interleaved first and second dielectric layers503and505of the dielectric stack structure and are surrounded by first and second dielectric layers503and505in dielectric portion107of word line pick-up region103. The bottom of each word line pick-up region103can be aligned with a corresponding second dielectric layer505, as opposed to first dielectric layer503, and the corresponding second dielectric layer505can be partially replaced with interconnect line206to form the electrical connection between vertical contact202of word line pick-up region103and the corresponding conductive layer502(word line). Thus, in some implementations, interconnect line206is sandwiched between two first dielectric layers503, as opposed to two second dielectric layers505, in the dielectric stack structure in dielectric portion107of word line pick-up region103.

In some implementations as shown inFIG.5, due to the relatively large critical dimension compared with the word line contacts in some 3D memory devices caused by its fabrication process as described below in detail, word line pick-up structure106further includes a filler508circumscribed by vertical contact202. That is, the word line pick-up opening may not be fully filled with contact spacer204and vertical contact202, and the remaining space of the word line pick-up opening may be filled with dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof, as filler508.

As shown in the enlarged view ofFIG.6A, in some implementations, channel structure110includes a channel hole filled with a semiconductor layer (e.g., as a channel layer604) and a composite dielectric layer (e.g., as a memory layer602). In some implementations, channel layer604includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. For example, channel layer604may include polysilicon. In some implementations, memory layer602is a composite layer including a tunneling layer610, a storage layer608(also known as a “charge trap layer”), and a blocking layer606. The remaining space of the channel hole can be partially or fully filled with a filler including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure110can have a cylinder shape (e.g., a pillar shape). The filler, channel layer604, tunneling layer610, storage layer608, and blocking layer606of memory layer602are arranged radially from the center toward the outer surface of the pillar in this order, according to some implementations. Tunneling layer610can include silicon oxide, silicon oxynitride, or any combination thereof. Storage layer608can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Blocking layer606can include silicon oxide, silicon oxynitride, or any combination thereof. In one example, memory layer602can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

As shown inFIG.6A, 3D memory device100can further include high dielectric constant (high-k) gate dielectric layers612each sandwiched between adjacent conductive layer502and first dielectric layer503in the conductive stack structure in core array region101and conductive portion105of word line pick-up region103. As described below in detail with respect to the fabrication process, high-k gate dielectric layers612may be formed prior to the formation of conductive layers502, such that conductive layers502may be formed surrounded by high-k gate dielectric layers612. Parts of high-k gate dielectric layers612that are laterally between memory layer602of channel structure110and conductive layers502can serve as the gate dielectrics of the memory cells. High-k gate dielectric layers612can include high-k dielectric materials, such as aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), or any combinations thereof.

As shown inFIG.6A, compared with other high-k gate dielectric layers612, part of high-k gate dielectric layer612surrounding conductive layer502(part of word line) that is in contact with interconnect line206of word line pick-up structure106is removed to expose conductive layer502such that interconnect line206can be electrically connected to conductive layer502.

It is understood that high-k gate dielectric layers612may be formed in different locations in 3D memory device100, for example, as shown inFIG.6B. As shown in the enlarged view ofFIG.6B, in some implementations, channel structure110includes a channel hole filled with a semiconductor layer (e.g., as channel layer604) and a composite dielectric layer (e.g., as memory layer602and high-k gate dielectric layer612). In some implementations, channel layer604includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. For example, channel layer604may include polysilicon. In some implementations, memory layer602is a composite layer including a tunneling layer610, a storage layer608(also known as a “charge trap layer”), and a blocking layer606. Different from the example inFIG.6A, channel structure110inFIG.6Bcan further include high-k gate dielectric layer612laterally between blocking layer606of memory layer602and the conductive stack structure of stack structure201. The remaining space of channel structure110can be partially or fully filled with a filler including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure110can have a cylinder shape (e.g., a pillar shape). The filler, channel layer604, tunneling layer610, storage layer608, and blocking layer606of memory layer602, and high-k gate dielectric layers612are arranged radially from the center toward the outer surface of the pillar in this order, according to some implementations. Tunneling layer610can include silicon oxide, silicon oxynitride, or any combination thereof. Storage layer608can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Blocking layer606can include silicon oxide, silicon oxynitride, or any combination thereof. In one example, memory layer602may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). high-k gate dielectric layer612can include aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), or any combinations thereof. In one example, high-k gate dielectric layer612may include AlO.

As shown inFIG.6B, different from the example inFIG.6A, high-k gate dielectric layers612are disposed only surrounding memory layer602of channel structures110, but not being sandwiched between adjacent conductive layer502and first dielectric layer503in the conductive stack structure in core array region101and conductive portion105of word line pick-up region103. As described below in detail with respect to the fabrication process, high-k gate dielectric layers612may be formed prior to the formation of memory layer602, as opposed to conductive layers502, such that memory layer602, instead of conductive layers502, may be formed surrounded by high-k gate dielectric layers612.

In some implementations, dummy channel structure112has the same structure as channel structure110, as described above with respect toFIGS.6A and6B, because they are formed in the same fabrication process. Dummy channel structure112, however, cannot perform the same memory functions as channel structure110at least because dummy channel structures112are not in contact with any DSG channel structures507or any local contacts (e.g., channel contacts506) in the local contact layer to pick-up/fan-out dummy channel structures112, as shown inFIG.5, according to some implementations. It is understood that in some examples, dummy channel structures112and channel structure110may have different structures and may be formed in different fabrication processes. For example, dummy channel structures112may be filled with dielectric material(s) without semiconductor materials (as channel layer604). Nevertheless, both dummy channel structures112and channel structures110can perform the mechanical supporting functions to stack structure201, in particular, during the gate replacement process, as described below in detail with respect to the fabrication processes.

FIG.13illustrates a block diagram of an exemplary system1300having a 3D memory device, according to some aspects of the present disclosure. System1300can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown inFIG.13, system1300can include a host1308and a memory system1302having one or more 3D memory devices1304and a memory controller1306. Host1308can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host1308can be configured to send or receive data to or from 3D memory devices1304.

3D memory device1304can be any 3D memory device disclosed herein, such as 3D memory device100depicted inFIGS.1-5,6A, and6B. In some implementations, each 3D memory device1304includes a NAND Flash memory. Consistent with the scope of the present disclosure, word line pick-up structures can replace the staircase structures and word line contacts to achieve word line pick-up/fan-out functions, thereby reducing the manufacturing cost and simplifying the fabrication process.

Memory controller1306(a.k.a., a controller circuit) is coupled to 3D memory device1304and host1308and is configured to control 3D memory device1304, according to some implementations. For example, memory controller1306may be configured to operate the plurality of channel structures via the word lines. Memory controller1306can manage the data stored in 3D memory device1304and communicate with host1308. In some implementations, memory controller1306is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller1306is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller1306can be configured to control operations of 3D memory device1304, such as read, erase, and program operations. Memory controller1306can also be configured to manage various functions with respect to the data stored or to be stored in 3D memory device1304including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller1306is further configured to process error correction codes (ECCs) with respect to the data read from or written to 3D memory device1304. Any other suitable functions may be performed by memory controller1306as well, for example, formatting 3D memory device1304. Memory controller1306can communicate with an external device (e.g., host1308) according to a particular communication protocol. For example, memory controller1306may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

Memory controller1306and one or more 3D memory devices1304can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system1302can be implemented and packaged into different types of end electronic products. In one example as shown inFIG.14A, memory controller1306and a single 3D memory device1304may be integrated into a memory card1402. Memory card1402can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. Memory card1402can further include a memory card connector1404electrically coupling memory card1402with a host (e.g., host1308inFIG.13). In another example as shown inFIG.14B, memory controller1306and multiple 3D memory devices1304may be integrated into an SSD1406. SSD1406can further include an SSD connector1408electrically coupling SSD1406with a host (e.g., host1308inFIG.13). In some implementations, the storage capacity and/or the operation speed of SSD1406is greater than those of memory card1402.

FIGS.7A-7Pillustrate a fabrication process for forming a 3D memory device having word line pick-up structures, according to some aspects of the present disclosure. FIGS.8A-8C illustrate a fabrication process for forming another 3D memory device having word line pick-up structures, according to some aspects of the present disclosure.FIG.9illustrates a flowchart of a method900for forming an exemplary 3D memory device having word line pick-up structures, according to some implementations of the present disclosure. Examples of the 3D memory device depicted inFIGS.7A-7P,8A-8C, and9include 3D memory devices100depicted inFIGS.1-5,6A, and6B.FIGS.7A-7P,8A-8C, and9will be described together. It is understood that the operations shown in method900are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG.9.

Referring toFIG.9, method900starts at operation902, in which a stack structure including interleaved first dielectric layers and second dielectric layers is formed. The first dielectric layers can include silicon oxide, and the second dielectric layers can include silicon nitride. In some implementations, to form the stack structure, the first dielectric layers and the second dielectric layers are alternatingly deposited above a substrate. The substrate can be a silicon substrate.

As illustrated inFIG.7A, a stack structure704including multiple pairs of a first dielectric layer706and a second dielectric layer708(a.k.a., a stack sacrificial layer) is formed above a silicon substrate702. Stack structure704includes vertically interleaved first dielectric layers706and second dielectric layers708, according to some implementations. First and second dielectric layers706and708can be alternatingly deposited above silicon substrate702to form stack structure704. In some implementations, each first dielectric layer706includes a layer of silicon oxide, and each second dielectric layer708includes a layer of silicon nitride. Stack structure704can be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

Method900proceeds to operation904, as illustrated inFIG.9, in which channel structures extending through the first dielectric layers and the second dielectric layers are formed in a first region of the stack structure. In some implementations, to form the channel structure, a channel hole extending vertically through the stack structure is formed, and a memory layer and a channel layer are sequentially formed over sidewalls of the channel hole. In some implementations, to form the channel structure, a channel hole extending vertically through the stack structure is formed, and a high-k gate dielectric layer, a memory layer, and a channel layer are sequentially formed over sidewalls of the channel hole. In some implementations, dummy channel structures extending through the first dielectric layers and the second dielectric layers are formed in the second region of the stack structure in the same process of forming the channel structures. That is, channel structures and dummy channel structures can be simultaneously formed through the first dielectric layers and the second dielectric layers in the first region and the second region of the stack structure, respectively.

As illustrated inFIG.7B, channel structures714can be formed in a core array region701of stack structure704, for example, corresponding to core array region101of stack structure201inFIGS.1-3. To form each channel structure714, as illustrated inFIG.7A, a channel hole710, which is an opening extending vertically through stack structure704, can be formed first in core array region701. In some implementations, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structure714in the later process. In some implementations, fabrication processes for forming channel hole710of channel structure714include wet etching and/or dry etching, such as deep-ion reactive etching (DRIE).

As illustrated inFIG.7B, a memory layer (including a blocking layer, a storage layer, and a tunneling layer) and a channel layer are sequentially formed in this order along sidewalls and the bottom surface of channel hole710, for example, corresponding to the example shown inFIG.6A. In some implementations, the memory layer is first deposited along the sidewalls and bottom surface of channel hole710, and the semiconductor channel is then deposited over the memory layer. The blocking layer, storage layer, and tunneling layer can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form the memory layer. The channel layer can then be formed by depositing a semiconductor material, such as polysilicon, over the tunneling layer of the memory layer using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are subsequently deposited to form the memory layer and the channel layer of channel structure714.

In some implementations, a high-k gate dielectric layer is formed before the formation of the memory layer. That is, the high-k gate dielectric layer, memory layer (including the blocking layer, storage layer, and tunneling layer), and the channel layer can be sequentially formed in this order along sidewalls and the bottom surface of channel hole710, for example, corresponding to the example shown inFIG.6B. In some implementations, the high-k gate dielectric layer is first deposited along the sidewalls and bottom surfaces of channel hole710, the memory layer is then deposited over the high-k gate dielectric layer, and the semiconductor channel is then deposited over the memory layer. The high-k gate dielectric layer can be formed by depositing high-k dielectric materials, such as aluminum oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. The blocking layer, storage layer, and tunneling layer can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, over the high-k gate dielectric layer to form the memory layer. The channel layer can then be formed by depositing a semiconductor material, such as polysilicon, over the tunneling layer of the memory layer using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, an aluminum oxide layer, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are subsequently deposited to form the high-k gate dielectric layer, the memory layer, and the channel layer of channel structure714.

In some implementations, as illustrated inFIG.7B, dummy channel structures716can be formed in a word line pick-up region703of stack structure704, for example, corresponding to word line pick-up region103of stack structure201inFIGS.1-3, in the same process of forming channel structures714. To form each dummy channel structure716, as illustrated inFIG.7A, a dummy channel hole712, which is another opening extending vertically through stack structure704, can be formed in word line pick-up region703simultaneously as channel hole710by the same wet etching and/or dry etching, such as DRIE. As illustrated inFIG.7B, dummy channel structure716can then be formed simultaneously as channel structure714by the same thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof that deposit a memory layer (including a blocking layer, a storage layer, and a tunneling layer) and a channel layer, or a high-k gate dielectric layer, a memory layer (including a blocking layer, a storage layer, and a tunneling layer), and a channel layer. It is understood that in some examples, dummy channel structures716may be formed in a separate process from channel structures714.

As illustrated inFIG.7C, a DSG layer718and a stop layer721are formed on core array region701of stack structure704. DSG layer718can include a semiconductor layer, such as a polysilicon layer, and stop layer721can include a silicon nitride layer. DSG layer718and stop layer721can be sequentially deposited on core array region701, but not on word line pick-up region703, of stack structure704using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. DSG channel structures719can be formed extending vertically through DSG layer718and stop layer721to be in contact with the upper ends of channel structures714, but not dummy channel structures716, as shown inFIG.7C. To form DSG channel structures719, DSG holes can be etched through DSG layer718and stop layer721to expose the upper ends of channel structures714, respectively, and a spacer (e.g., having silicon oxide) and a semiconductor layer (e.g., having polysilicon) can be sequentially deposited into the DSG holes using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, to fill the DSG holes.

Method900proceeds to operation906, as illustrated inFIG.9, in which all the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers, for example, by a gate replacement process. The conductive layer can include a metal.FIG.10Ais a flowchart of method906for a gate replacement, according to some aspects of the present disclosure. At operation1002, a slit extending through the first dielectric layers and the second dielectric layers and across the first region and the second region of the stack structure is formed. In some implementations, the slit extends vertically through the local contact layer as well.

As illustrated inFIG.7D, a slit720is an opening that extends vertically through stop layer721, DSG layer718, and first dielectric layers706and second dielectric layers708(a.k.a., stack sacrificial layers) of stack structure704until silicon substrate702. Slit720can also extend laterally across core array region701and word line pick-up region703in the x-direction (the word line direction), for example, corresponding to slit structure108inFIG.1. In some implementations, fabrication processes for forming slit720include wet etching and/or dry etching, such as DRIE, of first dielectric layers706and second dielectric layers708. The etching process through stack structure704may not stop at the top surface of silicon substrate702and may continue to etch part of silicon substrate702to ensure that slit720extends vertically all the way through all first dielectric layers706and second dielectric layers708of stack structure704.

At operation1004, the slit in the first region of the stack structure is covered. As illustrated inFIG.7E, the part of slit720in core array region701is covered by a sacrificial layer724. In some implementations, sacrificial layer724that is different from first dielectric layers706and second dielectric layers708, such as a polysilicon layer or a carbon layer, is deposited into slit720using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, to at least partially fill slit720(covering the exposed first dielectric layers706and second dielectric layers708in slit720). Sacrificial layer724can then be patterned using lithography and wet etching and/or dry etching to remove the part of sacrificial layer724in word line pick-up region703, leaving only the part of sacrificial layer724in core array region701to cover only the part of slit720in core array region701.

At operation1006, the parts of the second dielectric layers in the second region of the stack structure are removed through the slit in the second region of the stack structure. As illustrated inFIG.7E, parts of second dielectric layers708in a conductive portion729of word line pick-up region703are removed by wet etching to form lateral recesses726, leaving the remainders of second dielectric layers708in a dielectric portion727of word line pick-up region703intact. In some implementations, the parts of second dielectric layers708are wet etched by applying a wet etchant through the part of slit720in word line pick-up region703that is uncovered by sacrificial layer724, creating lateral recesses726interleaved between first dielectric layers706. The wet etchant can include phosphoric acid for etching second dielectric layers708including silicon nitride. In some implementations, the etching rate and/or etching time are controlled to remove only the parts of second dielectric layers708in conductive portion729, leaving the remainders of second dielectric layers708intact in dielectric portion727. By controlling the etching time, the wet etchant does not travel all the way to completely remove second dielectric layers708in word line pick-up region703, thereby defining two portions in word line pick-up region703-dielectric portion709in which second dielectric layers708are removed, and dielectric portion727in which second dielectric layers708remain. As illustrated inFIG.7E, since the part of slit720in core array region701is covered by sacrificial layer724that is resistant to the etchant for removing second dielectric layers708, all second dielectric layers708remain intact in core array region701at operation1006.

At operation1008, the slit in the first region of the stack structure is opened. As illustrated inFIG.7F, the part of slit720in core array region701is re-opened by removing sacrificial layer724(shown inFIG.7E) to expose first dielectric layers706and second dielectric layers708(shown inFIG.7E). In some implementations, sacrificial layer724is selectively etched away from the part of slit720in core array region701, for example, using potassium hydroxide (KOH) for etching sacrificial layer724having polysilicon, to open the part of slit720in core array region701.

At operation1010, the slit in the second region of the stack structure is covered. As illustrated inFIG.7F, lateral recesses726(shown inFIG.7E) and the part of slit720in word line pick-up region703are covered by a sacrificial layer728. In some implementations, sacrificial layer728that is different from first dielectric layers706and second dielectric layers708, such as a polysilicon layer or a carbon layer, is deposited into lateral recesses726and slit720using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, to at least partially fill slit720(covering the exposed first dielectric layers706and second dielectric layers708). Sacrificial layer728can then be patterned using lithography and wet etching and/or dry etching to remove the part of sacrificial layer728in core array region701, leaving only the part of sacrificial layer728in word line pick-up region703to cover only lateral recesses726and the part of slit720in word line pick-up region703, but not in core array region701. It is understood that lateral recesses726may be considered as parts of slit720in word line pick-up region703. Thus, even if only lateral recesses726are fully or partially filled by sacrificial layer728(e.g., as shown inFIG.7F), the part of slit720in word line pick-up region703may still be considered as being covered.

At operation1012, all the second dielectric layers in the first region of the stack structure are removed through the slit in the first region of the stack structure. As illustrated inFIG.7F, all second dielectric layers708(as shown inFIG.7E) in core array region701are fully removed by wet etching to form lateral recesses730. In some implementations, second dielectric layers708are wet etched by applying a wet etchant through the part of slit720in core array region701that is uncovered by sacrificial layer728, creating lateral recesses730interleaved between first dielectric layers706. The wet etchant can include phosphoric acid for etching second dielectric layers708including silicon nitride. In some implementations, the etching rate and/or etching time are controlled to ensure that all second dielectric layers708in core array region701are completely etched away. As illustrated inFIG.7F, since the part of slit720in word line pick-up region703is covered by sacrificial layer728that is resistant to the etchant for removing second dielectric layers708, the remainders of second dielectric layers708in dielectric portion727of word line pick-up region703remain intact at operation1012.

At operation1014, the slit in the second region of the stack structure is opened. As illustrated inFIG.7G, the part of slit720in word line pick-up region703is re-opened by removing sacrificial layer728(shown inFIG.7F) to expose first dielectric layers706and the remainders of second dielectric layers708in word line pick-up region703. In some implementations, sacrificial layer728is selectively etched away from the part of slit720in word line pick-up region703, for example, using KOH for etching sacrificial layer728having polysilicon, to open the part of slit720(and lateral recesses726) in word line pick-up region703.

At operation1016, the conductive layers are deposited through the slit in the first region and the second region of the stack structure. As illustrated inFIG.7H, conductive layers732are deposited into lateral recesses730and726(shown inFIG.7G) in core array region701and conductive portion729of word line pick-up region703through slit720. In some implementations in which high-k gate dielectric layers are not formed in channel structures714, high-k gate dielectric layers733are deposited into lateral recesses726and730prior to conductive layers732, such that conductive layers732are deposited on and surrounded by high-k gate dielectric layers733, for example, corresponding to the example shown inFIG.6A. In some implementations in which high-k gate dielectric layers are formed in channel structures714, high-k gate dielectric layers are not deposited into lateral recesses726and730prior to conductive layers732, such that conductive layers732are deposited on and surrounded by first dielectric layers706, for example, corresponding to the example shown inFIG.6B. Conductive layers732, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As described above, the removal of second dielectric layers708(stack sacrificial layers, e.g., having silicon nitride) can be performed separately in core array region101and word line pick-up region103by partially covering slit720in core array region101or word line pick-up region103to allow second dielectric layers708to be removed at different scopes (e.g., fully removal in core array region101and partial removal in word line pick-up region103). In the gate replacement process described above with respect toFIG.10A, the removal of second dielectric layers708is performed first in word line pick-up region703, and then in core array region701. It is understood that in another gate replace process, the removal of second dielectric layers708may be performed first in core array region701, and then in word line pick-up region703, for example, as shown inFIGS.8A-8C and10B.FIG.10Bis a flowchart of method906for another gate replacement, according to some aspects of the present disclosure. At operation1002, a slit extending through the first dielectric layers and the second dielectric layers and across the first region and the second region of the stack structure is formed. In some implementations, the slit extends vertically through the local contact layer as well.

As illustrated inFIG.7D, a slit720is an opening that extends vertically through stop layer721, DSG layer718, and first dielectric layers706and second dielectric layers708of stack structure704until silicon substrate702. Slit720can also extend laterally across core array region701and word line pick-up region703in the x-direction (the word line direction), for example, corresponding to slit structure108inFIG.1. In some implementations, fabrication processes for forming slit720include wet etching and/or dry etching, such as DRIE, of first dielectric layers706and second dielectric layers708. The etching process through stack structure704may not stop at the top surface of silicon substrate702and may continue to etch part of silicon substrate702to ensure that slit720extends vertically all the way through all first dielectric layers706and second dielectric layers708of stack structure704.

At operation1005, the slit in the second region of the stack structure is covered. As illustrated inFIG.8A, the part of slit720in word line pick-up region703is covered by a sacrificial layer802. In some implementations, sacrificial layer802that is different from first dielectric layers706and second dielectric layers708, such as a polysilicon layer or a carbon layer, is deposited into slit720using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, to at least partially fill slit720(covering the exposed first dielectric layers706and second dielectric layers708in slit720). Sacrificial layer802can then be patterned using lithography and wet etching and/or dry etching to remove the part of sacrificial layer802in core array region701, leaving only the part of sacrificial layer802in word line pick-up region703to cover only the part of slit720in word line pick-up region703.

At operation1007, all the second dielectric layers in the first region of the stack structure are removed through the slit in the first region of the stack structure. As illustrated inFIG.8B, all second dielectric layers708(as shown inFIG.8A) in core array region701are fully removed by wet etching to form lateral recesses730. In some implementations, second dielectric layers708are wet etched by applying a wet etchant through the part of slit720in core array region701that is uncovered by sacrificial layer802, creating lateral recesses730interleaved between first dielectric layers706. The wet etchant can include phosphoric acid for etching second dielectric layers708including silicon nitride. In some implementations, the etching rate and/or etching time are controlled to ensure that all second dielectric layers708in core array region701are completely etched away. As illustrated inFIG.8B, since the part of slit720in word line pick-up region703is covered by sacrificial layer802that is resistant to the etchant for removing second dielectric layers708, second dielectric layers708in word line pick-up region703remain intact at operation1007.

At operation1009, the slit in the second region of the stack structure is opened. As illustrated inFIG.8C, the part of slit720in word line pick-up region703is re-opened by removing sacrificial layer802(shown inFIG.8B) to expose first dielectric layers706and second dielectric layers708in word line pick-up region703. In some implementations, sacrificial layer802is selectively etched away from the part of slit720in word line pick-up region703, for example, using KOH for etching sacrificial layer802having polysilicon, to open the part of slit720in word line pick-up region703.

At operation1013, the parts of the second dielectric layers in the second region of the stack structure are removed through the slit in the second region of the stack structure. As illustrated inFIG.8C, parts of second dielectric layers708in conductive portion729of word line pick-up region703are removed by wet etching to form lateral recesses726, leaving the remainders of second dielectric layers708in dielectric portion727of word line pick-up region703intact. In some implementations, the parts of second dielectric layers708are wet etched by applying a wet etchant through the part of slit720in word line pick-up region703, creating lateral recesses726interleaved between first dielectric layers706. The wet etchant can include phosphoric acid for etching second dielectric layers708including silicon nitride. In some implementations, the etching rate and/or etching time are controlled to remove only the parts of second dielectric layers708in conductive portion729, leaving the remainders of second dielectric layers708intact in dielectric portion727. By controlling the etching time, the wet etchant does not travel all the way to completely remove second dielectric layers708in word line pick-up region703, thereby defining two portions in word line pick-up region703-conductive portion729in which second dielectric layers708are removed, and dielectric portion727in which second dielectric layers708remain. As illustrated inFIG.8C, since all second dielectric layers708in core array region701have already been removed at operation1007, the part of slit720in core array region701may not need to be covered at operation1013.

At operation1016, the conductive layers are deposited through the slit in the first region and the second region of the stack structure. As illustrated inFIG.7H, conductive layers732are deposited into lateral recesses730and726(shown inFIG.8C) in core array region701and conductive portion729of word line pick-up region703through slit720. In some implementations in which high-k gate dielectric layers are not formed in channel structures714, high-k gate dielectric layers733are deposited into lateral recesses726and730prior to conductive layers732, such that conductive layers732are deposited on and surrounded by high-k gate dielectric layers733, for example, corresponding to the example shown inFIG.6A. In some implementations in which high-k gate dielectric layers are formed in channel structures714, high-k gate dielectric layers are not deposited into lateral recesses726and730prior to conductive layers732, such that conductive layers732are deposited on and surrounded by first dielectric layers706, for example, corresponding to the example shown inFIG.6B. Conductive layers732, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

After the gate replacement processes described above with respect toFIGS.10A and10B, stack structure704can be redefined into two stack structures—a conductive stack structure including interleaved conductive layers732and first dielectric layers706in core array region701as well as in conductive portion729of word line pick-up region703, and a dielectric stack structure including interleaved first dielectric layers706and the remainders of second dielectric layers708in dielectric portion727of word line pick-up region703. That is, all second dielectric layers708in core array region701and parts of second dielectric layers708in word line pick-up region703of stack structure704are replaced with conductive layers732, according to some implementations. Moreover, in some examples, since the dielectric stack structure in dielectric portion727of word line pick-up region703remains intact during the gate replacement process (without removal of the remainders of second dielectric layers708therein), dummy channel structures716may not need to be formed in dielectric portion727of word line pick-up region703to provide mechanical support when removing second dielectric layer708.

Referring back toFIG.9, method900proceeds to operation908, as illustrated inFIG.9, in which word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

In some implementations, before forming the word line pick-up structures, a first spacer is formed in the slit. As illustrated inFIG.7I, a slit spacer737is formed in slit720(shown inFIG.7H) to form a slit structure734extending vertically through interleaved conductive layers732and first dielectric layers706of stack structure704and laterally across core array region701and conductive portion729of word line pick-up region703. Slit spacer737can be formed by depositing dielectrics into slit720using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, conductive materials (e.g., as a source contact) are deposited into slit720after slit spacer737as part of slit structure734.

In some implementations, to form the word line pick-up structures, word line pick-up openings extending through the first dielectric layers and the remainders of the second dielectric layers in the second region of the stack structure are formed at different depths to expose the remainders of the second dielectric layers in the second regions of the stack structure, respectively. As illustrated inFIG.7J, an opening736extends vertically through a number of pairs of first and second dielectric layers706and708of the dielectric stack structure in dielectric portion727of word line pick-up region703. In some implementations, a plurality of openings736are formed extending through different numbers of pairs of first and second dielectric layers706and708in dielectric portion727, stopping at different depths, for example, corresponding to the examples shown inFIG.4. Openings736can be formed using a chopping process. As used herein, a “chopping” process is a process that increases the depth of one or more openings extending through a dielectric stack structure including interleaved first and second dielectric layers by a plurality of etching cycles. Each etch cycle can include one or more dry etch and/or wet etch processes that etch one pair of first and second dielectric layers, i.e., reducing the depth by one dielectric layer pair. The purpose of the chopping process is to make multiple openings736at different depths. Accordingly, depending on the number of openings736, a certain number of chopping processes, along with a number of chopping masks, may be needed. It is understood that the number of chopping masks, the sequence of the chopping masks, the design (e.g., the number and pattern of openings) of each chopping mask, and/or the reduced depth by each chopping process (e.g., the number of etching cycles) may affect the specific depth of each opening736after the chopping process. A detailed description of the chopping process can be referenced in U.S. patent application Ser. No. 16/881,168, filed on May 22, 2022, and U.S. patent application Ser. No. 16/881,339, filed on May 22, 2022, both of which are incorporated by reference in their entireties herein.

It is understood that the chopping process can be more easily performed through a dielectric stack structure including interleaved first and second dielectric layers (e.g., silicon oxide and silicon nitride), as opposed to a conductive stack structure including interleaved conductive layers and dielectric layers (e.g., metal and silicon oxide) due to the etching properties of the different materials. Thus, the dielectric stack structure remains after the gate replacement process in dielectric portion727of word line pick-up region703is suitable for forming openings736for word line pick-up structures at different depths using the chopping process, according to some implementations.

In some implementations, to form the word line pick-up structures, a second spacer is formed on sidewalls and a bottom of each of the word line pick-up openings. As illustrated inFIG.7K, a contact spacer738is formed on the sidewalls and the bottom surface of opening736, thereby covering first dielectric layers706and second dielectric layers708exposed from the sidewalls of opening736. In some implementations, contact spacer738is formed by depositing dielectric materials, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, over the sidewalls and the bottom surface of opening736.

In some implementations, to form the word line pick-up structures, the second spacer on the bottom of the word line pick-up opening is removed to expose the respective part of the remainder of the second dielectric layer. As illustrated inFIG.7L, the part of contact spacer738on the bottom surface of opening736is removed, for example, by dry etching, to expose part of second dielectric layer708in dielectric portion727of word line pick-up region703. In some implementations, the etching rate, direction, and/or duration of RIE are controlled to etch only the part of contact spacer738on the bottom surface, but not on the sidewalls, of opening736, i.e., “punching” through contact spacer738in the z-direction to expose only a corresponding second dielectric layer708from the bottom, but not other second dielectric layers708from the sidewalls.

In some implementations, to form the word line pick-up structures, parts of the remainders of the second dielectric layers in the second region of the stack structure are replaced with interconnect lines, respectively, through the word line pick-up openings, such that the interconnect lines are in contact with the conductive layers, respectively, in the second region of the stack structure. In some implementations, to replace the parts of the second dielectric layers with the interconnect lines, the exposed part of the remainder of the second dielectric layer is etched through the word line pick-up opening to expose the respective conductive layer in the second region of the stack structure, and the respective interconnect line is deposited through the word line pick-up opening to be in contact with the exposed respective conductive layer in the second region of the stack structure.

As illustrated inFIG.7M, part of second dielectric layer708exposed from the bottom of opening736is removed by wet etching to form a lateral recess740, leaving the remainder of second dielectric layer708at the same level, as well as other second dielectric layers708at other levels, in dielectric portion727of word line pick-up region703intact. Lateral recess740can expose a corresponding conductive layer732at the same level in conductive portion729of word line pick-up region703. In some implementations, the part of second dielectric layer708is wet etched by applying a wet etchant through opening736, creating lateral recess740sandwiched between two first dielectric layers706. The wet etchant can include phosphoric acid for etching second dielectric layer708including silicon nitride. In some implementations, the etching rate and/or etching time are controlled to remove only part of second dielectric layer708that is enough to expose corresponding conductive layer732at the same level in conductive portion729. By controlling the etching time, the wet etchant does not travel all the way to completely remove second dielectric layer708in dielectric portion727. As a result, dummy channel structures716may not need to be formed in dielectric portion727of word line pick-up region703to provide mechanical support when removing second dielectric layer708. As illustrated inFIG.7M, since the sidewalls of opening736are still covered by contact spacer738(e.g., silicon oxide) that is resistant to the etchant for removing second dielectric layers708(e.g., silicon nitride), second dielectric layers708at other levels remain intact in dielectric portion727.

In some implementations in which high-k gate dielectric layers733are formed surrounding conductive layers732, as opposed to in channel structures714, as illustrated inFIG.7N, once the exposed part of second dielectric layer708is etched from opening736, the corresponding high-k gate dielectric layer733surrounding the corresponding conductive layer732at the same level is exposed. The exposed part of the corresponding high-k gate dielectric layer733can then be etched, for example, using wet etching, to expose the corresponding conductive layer732at the same level. It is understood that in some examples in which high-k gate dielectric layers733are formed in channel structures714, as opposed to surrounding conductive layers732, the etching of high-k gate dielectric layer733may be skipped as the etching of second dielectric layer708may expose the corresponding conductive layer732at the same level directly.

As illustrated inFIG.7O, an interconnect line743is formed by depositing a conductive layer through opening736to fill lateral recess740. The conductive layer, such as a metal layer, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. The deposition rate and/or duration may be controlled to ensure that interconnect line743can be in contact with the exposed corresponding conductive layer732at the same level as lateral recess740. In other words, second dielectric layer708exposed from the bottom of the corresponding opening736can be partially replaced with a corresponding interconnect line743in dielectric portion727of word line pick-up region703, while other second dielectric layers708at other levels in dielectric portion727remain intact.

In some implementations, to form the word line pick-up structures, vertical contacts are formed in the word line pick-up openings in contact with the interconnect lines, respectively. As illustrated inFIG.7O, a vertical contact742is formed on the sidewalls of opening736and is in contact with interconnect line743. vertical contact742can be formed in the same process of forming interconnect line743by depositing the conductive layer not only into lateral recess740, but also on the sidewalls and the bottom surface of opening736, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

In some implementations, to form the word line pick-up structures, a filler is formed in the word line pick-up opening after forming the respective vertical contact. As illustrated inFIG.7P, a filler744is formed in opening736(shown inFIG.7O) to fully or partially fill opening736. Filler744, such as a dielectric layer, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. The excess portions of the conductive layer and dielectric layer for forming vertical contact742and filler744can be removed by using chemical mechanical polishing (CMP).

As described above, the fabrication processes for forming 3D memory devices having word line pick-up structures involve two major processes-gate replacement and word line pick-up structure formation. In method900, the gate replacement process is performed before the word line pick-up structure formation process. It is understood that in other examples, the gate replacement process may be performed after the word line pick-up structure formation process. For example,FIGS.11A-11Lillustrate another fabrication process for forming a 3D memory device having word line pick-up structures, according to some aspects of the present disclosure.FIG.12illustrates a flowchart of another method1200for forming an exemplary 3D memory device having word line pick-up structures, according to some implementations of the present disclosure. Examples of the 3D memory device depicted in11A-11L and12include 3D memory devices100depicted inFIGS.1-5,6A, and6B.FIGS.11A-11L and12will be described together. It is understood that the operations shown in method1200are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG.12.

Referring toFIG.12, method1200starts at operation1202, in which a stack structure including interleaved first dielectric layers and second dielectric layers is formed. The first dielectric layers can include silicon oxide, and the second dielectric layers can include silicon nitride. In some implementations, to form the stack structure, the first dielectric layers and the second dielectric layers are alternatingly deposited above a substrate. The substrate can be a silicon substrate.

As illustrated inFIG.11A, a stack structure704including multiple pairs of first dielectric layer706and second dielectric layer708(a.k.a., a stack sacrificial layer) is formed above silicon substrate702. Stack structure704includes vertically interleaved first dielectric layers706and second dielectric layers708, according to some implementations. First and second dielectric layers706and708can be alternatingly deposited above silicon substrate702to form stack structure704. In some implementations, each first dielectric layer706includes a layer of silicon oxide, and each second dielectric layer708includes a layer of silicon nitride. Stack structure704can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

Method1200proceeds to operation1204, as illustrated inFIG.12, in which channel structures extending through the first dielectric layers and the second dielectric layers are formed in a first region of the stack structure. In some implementations, to form the channel structure, a channel hole extending vertically through the stack structure is formed, and a high-k gate dielectric layer, a memory layer, and a channel layer are sequentially formed over sidewalls of the channel hole. In some implementations, dummy channel structures extending through the first dielectric layers and the second dielectric layers are formed in the second region of the stack structure in the same process of forming the channel structures. That is, channel structures and dummy channel structures can be simultaneously formed through the first dielectric layers and the second dielectric layers in the first region and the second region of the stack structure, respectively.

As illustrated inFIG.11A, channel structures1102can be formed in core array region701of stack structure704, for example, corresponding to core array region101of stack structure201inFIGS.1-3. To form each channel structure1102, a channel hole, which is an opening extending vertically through stack structure704, can be formed first in core array region701. In some implementations, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structure1102in the later process. In some implementations, fabrication processes for forming the channel hole of channel structure1102include wet etching and/or dry etching, such as DRIE.

As illustrated inFIG.11A, a high-k gate dielectric layer, a memory layer (including a blocking layer, a storage layer, and a tunneling layer), and a channel layer can be sequentially formed in this order along sidewalls and the bottom surface of the channel hole, for example, corresponding to the example shown inFIG.6B. In some implementations, the high-k gate dielectric layer is first deposited along the sidewalls and bottom surfaces of the channel hole, the memory layer is then deposited over the high-k gate dielectric layer, and the semiconductor channel is then deposited over the memory layer. The high-k gate dielectric layer can be formed by depositing high-k dielectric materials, such as aluminum oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. The blocking layer, storage layer, and tunneling layer can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, over the high-k gate dielectric layer to form the memory layer. The channel layer can then be formed by depositing a semiconductor material, such as polysilicon, over the tunneling layer of the memory layer using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, an aluminum oxide layer, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are subsequently deposited to form the high-k gate dielectric layer, the memory layer, and the channel layer of channel structure1102.

In some implementations, as illustrated inFIG.11A, dummy channel structures1104can be formed in word line pick-up region703of stack structure704, for example, corresponding to word line pick-up region103of stack structure201inFIGS.1-3, in the same process of forming channel structures1102. To form each dummy channel structure1104, a dummy channel hole, which is another opening extending vertically through stack structure704, can be formed in word line pick-up region703simultaneously as the channel hole for channel structure1102by the same wet etching and/or dry etching, such as DRIE. As illustrated inFIG.11A, dummy channel structure1104can then be formed simultaneously as channel structure1102by the same thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof that deposit a high-k gate dielectric layer, a memory layer (including a blocking layer, a storage layer, and a tunneling layer), and a channel layer. It is understood that in some examples, dummy channel structures1104may be formed in a separate process from channel structures1102.

As illustrated inFIG.11A, DSG layer718and stop layer721are formed on core array region701of stack structure704. DSG layer718can include a semiconductor layer, such as a polysilicon layer, and stop layer721can include a silicon nitride layer. DSG layer718and stop layer721can be sequentially deposited on core array region701, but not on word line pick-up region703, of stack structure704using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. DSG channel structures719can be formed extending vertically through DSG layer718and stop layer721to be in contact with the upper ends of channel structures1102, but not dummy channel structures1104, as shown inFIG.11A. To form DSG channel structures719, DSG holes can be etched through DSG layer718and stop layer721to expose the upper ends of channel structures1102, respectively, and a spacer (e.g., having silicon oxide) and a semiconductor layer (e.g., having polysilicon) can be sequentially deposited into the DSG holes using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, to fill the DSG holes.

Method1200proceeds to operation1206, as illustrated inFIG.12, in which word line pick-up structures extending through the first dielectric layers and the second dielectric layers in a second region of the stack structure are formed at different depths.

In some implementations, to form the word line pick-up structures, word line pick-up openings extending through the first dielectric layers and the second dielectric layers in the second region of the stack structure are formed at different depths to expose the second dielectric layers in the second regions of the stack structure, respectively. As illustrated inFIG.11B, an opening1106extends vertically through a number of pairs of first and second dielectric layers706and708of stack structure704in word line pick-up region703. In some implementations, a plurality of openings1106are formed extending through different numbers of pairs of first and second dielectric layers706and708in word line pick-up region703, stopping at different depths, for example, corresponding to the examples shown inFIG.4. Openings1106can be formed using the same chopping process as described above in detail with respect to openings736.

In some implementations, to form the word line pick-up structures, a second spacer is formed on sidewalls and a bottom of each of the word line pick-up openings. As illustrated inFIG.11C, a contact spacer1108is formed on the sidewalls and the bottom surface of opening1106, thereby covering first dielectric layers706and second dielectric layers708exposed from the sidewalls of opening1106. In some implementations, contact spacer1108is formed by depositing dielectric materials, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, over the sidewalls and the bottom surface of opening1106.

In some implementations, to form the word line pick-up structures, the second spacer on the bottom of the word line pick-up opening is removed to expose the respective part of the second dielectric layer. As illustrated inFIG.11D, the part of contact spacer1108on the bottom surface of opening1106is removed, for example, by dry etching, to expose part of second dielectric layer708in word line pick-up region703. In some implementations, the etching rate, direction, and/or duration of RIE are controlled to etch only the part of contact spacer1108on the bottom surface, but not on the sidewalls, of opening1106, i.e., “punching” through contact spacer1108in the z-direction to expose only a corresponding second dielectric layer708from the bottom, but not other second dielectric layers708from the sidewalls.

In some implementations, to form the word line pick-up structures, parts of the second dielectric layers in the second region of the stack structure are replaced with interconnect lines, respectively, through the word line pick-up openings. In some implementations, to replace the parts of the second dielectric layers with the interconnect lines, the exposed part of the remainder of the second dielectric layer is etched through the word line pick-up opening, and the respective interconnect line is deposited through the word line pick-up opening.

As illustrated inFIG.11E, part of second dielectric layer708exposed from the bottom of opening1106is removed by wet etching to form a lateral recess1110, leaving the remainder of second dielectric layer708at the same level, as well as other second dielectric layers708at other levels, in word line pick-up region703intact. In some implementations, the part of second dielectric layer708is wet etched by applying a wet etchant through opening1106, creating lateral recess1110sandwiched between two first dielectric layers706. The wet etchant can include phosphoric acid for etching second dielectric layer708including silicon nitride. In some implementations, the etching rate and/or etching time are controlled to remove only part of second dielectric layer708. By controlling the etching time, the wet etchant does not travel all the way to completely remove second dielectric layer708in word line pick-up region703. As illustrated inFIG.11E, since the sidewalls of opening1106are still covered by contact spacer1108(e.g., silicon oxide) that is resistant to the etchant for removing second dielectric layers708(e.g., silicon nitride), second dielectric layers708at other levels remain intact.

As illustrated inFIG.11F, an interconnect line1113is formed by depositing a conductive layer through opening736to fill lateral recess740. The conductive layer, such as a metal layer, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In other words, second dielectric layer708exposed from the bottom of the corresponding opening1106can be partially replaced with a corresponding interconnect line1113in word line pick-up region703, while other second dielectric layers708at other levels remain intact.

In some implementations, to form the word line pick-up structures, vertical contacts are formed in the word line pick-up openings in contact with the interconnect lines, respectively. As illustrated inFIG.11F, a vertical contact1112is formed on the sidewalls of opening1106and is in contact with interconnect line1113. Vertical contact1112can be formed in the same process of forming interconnect line1113by depositing the conductive layer not only into lateral recess1110, but also on the sidewalls and the bottom surface of opening1106, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

In some implementations, to form the word line pick-up structures, a filler is formed in the word line pick-up opening after forming the respective vertical contact. As illustrated inFIG.11G, a filler1114is formed in opening1106(shown inFIG.11F) to fully or partially fill opening1106. Filler1114, such as a dielectric layer, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. The excess portions of the conductive layer and dielectric layer for forming vertical contact1112and filler1114can be removed by using CMP.

Method1200proceeds to operation1208, as illustrated inFIG.12, in which all the second dielectric layers in the first region and parts of the second dielectric layers in the second region of the stack structure are replaced with conductive layers, for example, by a gate replacement process, such that the conductive layers are electrically connected to the word line pick-up structures, respectively, in the second region of the stack structure. The conductive layer can include a metal.

In some implantations, to perform the gate replacement process, a slit extending through the first dielectric layers and the second dielectric layers and across the first region and the second region of the stack structure is formed after forming the word line pick-up structures. In some implementations, the slit extends vertically through the local contact layer as well. As illustrated inFIG.11H, a slit1116is an opening that extends vertically through stop layer721, DSG layer718, and first dielectric layers706and second dielectric layers708of stack structure704until silicon substrate702. Slit1116can also extend laterally across core array region701and word line pick-up region703in the x-direction (the word line direction), for example, corresponding to slit structure108inFIG.1. In some implementations, fabrication processes for forming slit1116include wet etching and/or dry etching, such as DRIE, of first dielectric layers706and second dielectric layers708. The etching process through stack structure704may not stop at the top surface of silicon substrate702and may continue to etch part of silicon substrate702to ensure that slit1116extends vertically all the way through all first dielectric layers706and second dielectric layers708of stack structure704.

In some implantations, to perform the gate replacement process, the slit in the second region of the stack structure is covered. As illustrated inFIG.11I, the part of slit1116in word line pick-up region703is covered by a sacrificial layer1120. In some implementations, sacrificial layer1120that is different from first dielectric layers706and second dielectric layers708, such as a polysilicon layer or a carbon layer, is deposited into slit1116using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, to at least partially fill slit1116(covering the exposed first dielectric layers706and second dielectric layers708in slit1116). Sacrificial layer1120can then be patterned using lithography and wet etching and/or dry etching to remove the part of sacrificial layer1120in core array region701, leaving only the part of sacrificial layer1120in word line pick-up region703to cover only the part of slit1116in word line pick-up region703.

In some implantations, to perform the gate replacement process, all the second dielectric layers in the first region of the stack structure are removed through the slit in the first region of the stack structure. As illustrated inFIG.11I, all second dielectric layers708(as shown inFIG.11H) in core array region701are fully removed by wet etching to form lateral recesses1122. In some implementations, second dielectric layers708are wet etched by applying a wet etchant through the part of slit1116in core array region701that is uncovered by sacrificial layer1120, creating lateral recesses1122interleaved between first dielectric layers706. The wet etchant can include phosphoric acid for etching second dielectric layers708including silicon nitride. In some implementations, the etching rate and/or etching time are controlled to ensure that all second dielectric layers708in core array region701are completely etched away. As illustrated in FIG.11I, since the part of slit1116in word line pick-up region703is covered by sacrificial layer1120that is resistant to the etchant for removing second dielectric layers708, second dielectric layers708in word line pick-up region703remain intact.

In some implantations, to perform the gate replacement process, the slit in the second region of the stack structure is opened. As illustrated inFIG.11J, the part of slit1116in word line pick-up region703is re-opened by removing sacrificial layer1120(shown inFIG.11I) to expose first dielectric layers706and second dielectric layers708in word line pick-up region703. In some implementations, sacrificial layer1120is selectively etched away from the part of slit1116in word line pick-up region703, for example, using KOH for etching sacrificial layer1120having polysilicon, to open the part of slit1116in word line pick-up region703.

In some implantations, to perform the gate replacement process, the parts of the second dielectric layers in the second region of the stack structure are removed through the slit in the second region of the stack structure to expose the interconnect lines of the word line pick-up structures. As illustrated inFIG.11J, parts of second dielectric layers708in conductive portion729of word line pick-up region703are removed by wet etching to form lateral recesses1124, leaving the remainders of second dielectric layers708in dielectric portion727of word line pick-up region703intact. In some implementations, the parts of second dielectric layers708are wet etched by applying a wet etchant through the part of1116in word line pick-up region703, creating lateral recesses1124interleaved between first dielectric layers706. The wet etchant can include phosphoric acid for etching second dielectric layers708including silicon nitride. In some implementations, the etching rate and/or etching time are controlled to remove only the parts of second dielectric layers708in conductive portion729, leaving the remainders of second dielectric layers708intact in dielectric portion727. By controlling the etching time, the wet etchant does not travel all the way to completely remove second dielectric layers708in word line pick-up region703, thereby defining two portions in word line pick-up region703-conductive portion729in which second dielectric layers708are removed, and dielectric portion727in which second dielectric layers708remain. On the other hand, the etching rate and/or etching time are controlled to also ensure that interconnect line1113is exposed by a corresponding lateral recess1124at the same level. That is, the remainder of second dielectric layer708at the same level as interconnect line1113may be removed enough to expose interconnect line1113from corresponding lateral recess1124and slit1116. As illustrated inFIG.11J, since all second dielectric layers708in core array region701have already been removed, the part of slit1116in core array region701may not need to be covered when removing parts of second dielectric layers708in word line pick-up region703.

In some implantations, to perform the gate replacement process, the conductive layers are deposited through the slit in the first region and the second region of the stack structure to be in contact with the interconnect lines of the word line pick-up structures, respectively, in the second region of the stack structure. As illustrated inFIG.11K, conductive layers1126are deposited into lateral recesses1122and1124(shown inFIG.11J) in core array region701and conductive portion729of word line pick-up region703through slit1116. It is understood that the high-k gate dielectric layers have already been formed in channel structures1102, and may not be deposited into lateral recesses1122and1124prior to conductive layers1126, such that conductive layers1126are deposited on and surrounded by first dielectric layers706, for example, corresponding to the example shown inFIG.6B. Conductive layers1126, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. The deposition rate and/or duration can be controlled to ensure that conductive layer1126at the same level as interconnect line1113is in contact with interconnect line1113in word line pick-up region703.

After the gate replacement processes described above, stack structure704can be redefined into two stack structures—a conductive stack structure including interleaved conductive layers732and first dielectric layers706in core array region701as well as in conductive portion729of word line pick-up region703, and a dielectric stack structure including interleaved first dielectric layers706and the remainders of second dielectric layers708in dielectric portion727of word line pick-up region703. That is, all second dielectric layers708in core array region701and parts of second dielectric layers708in word line pick-up region703of stack structure704are replaced with conductive layers732, according to some implementations. Moreover, in some examples, since the dielectric stack structure in dielectric portion727of word line pick-up region703remains intact during the gate replacement process (without removal of the remainders of second dielectric layers708therein), dummy channel structures716may not need to be formed in dielectric portion727of word line pick-up region703to provide mechanical support when removing second dielectric layer708.

In some implementations, after forming the word line pick-up structures and the gate replacement process, a first spacer is formed in the slit. As illustrated inFIG.11L, a slit spacer1127is formed in slit1116(shown inFIG.11K) to form a slit structure1128extending vertically through interleaved conductive layers732and first dielectric layers706of stack structure704and laterally across core array region701and conductive portion729of word line pick-up region703. Slit spacer1127can be formed by depositing dielectrics into slit1116using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, conductive materials (e.g., as a source contact) are deposited into slit1116after slit spacer1127as part of slit structure1128.

As described above with respect toFIGS.10A and10B, during the gate replacement process, the removal of second dielectric layers708may be performed first in core array region701, and then in word line pick-up region703(e.g., shown inFIGS.11I and11J), or vice versa. Thus, the operations described with respect toFIGS.11I and11Jmay be replaced with similar operations described with respect toFIGS.7E-7G, such that the gate replacement process may be performed after the word line pick-up structure formation process, and during the gate replacement process, the removal of second dielectric layers708may be performed first in word line pick-up region703, and then in core array region701. In some implementations, to perform the gate replacement process, the slit in the first region of the stack structure is covered, the parts of the second dielectric layers in the second region of the stack structure in the second region of the stack structure are removed through the slit, the slit in the first region of the stack structure is opened, the slit in the second region of the stack structure is covered, all the second dielectric layers in the first region of the stack structure are removed through the slit in the first region of the stack structure, the slit in the second region of the stack structure is opened, and the conductive layers are deposited through the slit in the first region and the second region of the stack structure.