Method and apparatus for generating corrected quadrature phase signal pairs in a communication device

A method and an apparatus (300) for generating corrected quadrature phase signal pairs in a communication device are provided. The apparatus (300) includes a quadrature phase generator (310), programmable delay elements (320, 330) and a control circuit (360). The programmable delay elements (320, 330) receive a quadrature phase signal pair (signals I 312 and Q 314) from the quadrature phase generator (310). The control circuit (360) generates a control signal (362) based on outputs (325, 335) of the programmable delay elements (320, 330). The control signal (362) configures the programmable delay elements (320, 330). The programmable delay elements (320, 330) are configured to adjust delay between the signals I (312) and Q (314). The programmable delay elements (320, 330) are also used to adjust duty cycle for the quadrature phase signal pair to provide the corrected quadrature phase signal pair.

FIELD OF THE INVENTION

The present invention generally relates to quadrature phase signal generation and more specifically, to a method and apparatus for correcting quadrature phase signal pairs in communication devices.

BACKGROUND

Quadrature phase generators are widely used for a variety of modulation and demodulation schemes in various wireless communication devices. Some of these schemes include Quadrature Phase Shift Keying (QPSK) and Quadrature Amplitude Modulation (QAM) and the like. The quadrature phase generator takes a local oscillator (LO) signal and generates a pair of quadrature phase signals typically referred to as in-phase signal I and quadrature phase signal Q. The signals I and Q have frequency related to the LO frequency and have a phase difference of 90 degrees.

The design and topology of quadrature phase generators, along with the transmitter and receiver architectures within which they are used, vary for different communication devices. Several designs, such as divide-by-N flip flop circuits (where N is an even integer) and polyphase filters, exist. However, due to internal integrated circuit design and device tolerances, signal paths for the I and Q signals may have different propagation delays. As a result, the I and Q signals do not have an ideal quadrature phase difference of 90 degrees at the outputs of the quadrature phase generator. Any variation from the ideal quadrature phase difference of 90 degrees at the outputs of the quadrature phase generator is defined as a relative phase error between the I and Q signals.

FIG. 1is an example illustrating error prone quadrature phase signal pairs ([I, Q] and [Ix, Qx]) generated by a typical quadrature phase generator. For the illustrated example, two error prone quadrature signal pairs should ideally be differentially related, i.e. in-phase signals I (0 degrees)110and Ix (180 degrees)130, and the quadrature phase signals Q (90 degrees)120and Qx (270 degrees)140should have a phase difference of 180 degrees. However, due to the different propagation delays, the in-phase signals I110and Ix130have phase of 2 degrees and 179 degrees, and the quadrature phase signals Q120and Qx140have phase of 88 degrees and 271 degrees. Hence, the signals I110and Q120have a phase difference of 86 degrees (a relative phase error of −4 degrees) and the signals Ix130and Qx140have a phase difference of 92 degrees (a relative phase error of 2 degrees). The relative phase error for quadrature phase signal pairs subsequently results in errors in transmitting and receiving signals in a communication device.

FIG. 2is a block diagram illustrating a prior art communication device200utilizing quadrature phase generators220,270for a transmitter210and a receiver260. The transmitter210utilizes transmitter (TX) quadrature phase generator220for modulating data231,233to be transmitted. The receiver260utilizes receiver (RX) quadrature phase generator270for demodulating a received signal, for instance, a prefiltered signal285.

In the transmitter210, pre-amplifiers230,232amplify the data231and233respectively to provide amplified signals241,243. Subsequently, TX filters240,242pre-filter the amplified signals241,243to provide bandlimited I/Q baseband signals251,253to mixers250,252respectively. The TX quadrature phase generator220takes LO signal205and provides I signal221and Q signal223. The LO I signal221is provided to mixer250while the LO Q signal223is provided to mixer252. Mixer250up-converts the bandlimited I signal251with the LO I signal221to provide RF signals255. Mixer252up-converts the bandlimited Q signal253with the LO Q signal223to provide RF signal257. Ideally, RF signals255,257are phase shifted 90 degrees, but in reality these signals are prone to error. A combiner254combines the RF signals255,257to provide a modulated signal259to a TX antenna (not shown) for transmission.

In the receiver260, a RX antenna (not shown) receives a signal281or283. A switch282switches between the signals281,283based on a desired band for demodulation. A pre-filter280filters a signal (281or283) from the switch282to provide a prefiltered signal285to a pre-amplifier286. The pre-amplifier286subsequently amplifies the prefiltered signal285to provide signals287,289to mixers290,292respectively. The RX quadrature phase generator270takes the LO input205and provides I signal271and Q signal273which are respectively provided to mixers290,292. Mixer290down converts signal287with I signal271, while mixer292down converts signal289with Q signal273. Ideally, the mixers290and292generate baseband signals291,293with a phase difference of90degrees, but in reality these signals are prone to error. RX filters298,299filter the baseband signals291,293to provide demodulated baseband signals I295and Q297.

Due to the relative phase error between the signal I221and the signal Q223, the modulated signal259generated by the transmitter210contains an undesirable sideband image. Similarly, the relative phase error between the signal I271and the signal Q273results in an undesirable sideband image in the demodulated baseband signals295,297generated by the receiver260. Subsequently, the undesirable sideband images for the receiver and the transmitter may result in severe errors in detection of data during digital demodulation (receiver) or modulation (transmitter).

Common approaches for avoiding the problems associated with the relative phase error include modifying the phase for the baseband signals (data231,233) to be transmitted to match the phase difference between the signals I221and Q223. Similarly, the received signal285is down-converted to the demodulated baseband signals295,297to detect relative phase error. The phase for signals295,297are adjusted based on the detected relative phase error. However, as the baseband signals for the transmitted and received signals have different relative phase errors, a separate quadrature phase generator is required for the transmitter210and the receiver260. Circuit complexity, parts count, board area, power consumption, controller and logic complexity, and cost are major challenges for the communication devices using the aforementioned approaches.

Other approaches for addressing the problem of relative phase error in quadrature phase generators have been suggested. Approaches require a phase detector and several additional components such as filters, and operational amplifiers, and integrators in a feedback path to provide a phase adjustment signal for adjusting the phase of the I and Q signals. Again, circuit complexity and parts count are major concerns for such approaches. Furthermore, these approaches require a separate phase adjustment signal for each signal generated by the quadrature phase generator which adds to the complexity of the control circuitry used in the quadrature phase generator.

Accordingly, it would be desirable to have a method and apparatus capable of generating I and Q signals without the aforementioned issues.

DETAILED DESCRIPTION

Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the embodiments reside primarily in an apparatus and a method for generating a corrected quadrature phase signal pair. The apparatus of the present invention provides corrected in-phase and quadrature phase signals which may be utilized in a communication device using modulation schemes such as Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (QAM) and the like. Accordingly, the system and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

Briefly, in accordance with the present invention, there is provided herein a method and an apparatus for generating corrected quadrature phase signal pairs in a communication device. The apparatus formed in accordance with the present invention includes a quadrature phase generator, programmable delay elements and a control circuit. The programmable delay elements are coupled to the outputs of the quadrature phase generator. The control circuit is used to generate control signal(s) based on the outputs of the programmable delay elements. The control signal(s) are used for configuring the programmable delay elements. The programmable delay elements are configured to adjust the delay between an in-phase signal and a quadrature phase signal produced by the quadrature phase generator. The programmable delay elements are also used to adjust the duty cycle for the quadrature phase signal pairs.

FIG. 3is a block diagram illustrating an apparatus300for generating a corrected quadrature phase signal pair in accordance with some embodiments of the invention. The apparatus300is preferably incorporated as a signal generator within a communication device (shown later) for modulating and demodulating data using an in-phase signal and a quadrature phase signal. Apparatus300includes a Local Oscillator (LO)302providing a LO input signal305to a quadrature phase generator310having programmable delay elements320,330,340,350coupled thereto. In accordance with the illustrated embodiment, corrected quadrature phase signal pair(s) (corrected in-phase and quadrature phase signal(s)) are generated as outputs325,335,345,355of the programmable delay elements320,330,340,350.

The apparatus300comprises a quadrature phase generator310, programmable delay elements320,330and a control circuit360. LO302provides the LO input signal305to the quadrature phase generator310. The quadrature phase generator310provides a quadrature phase signal pair312,314comprising a first quadrature phase signal, hereafter referred to as an in-phase signal I312, and a second quadrature phase signal, hereafter referred to as a quadrature phase signal Q314. The programmable delay elements320,330form a programmable delay element pair370to receive the quadrature phase signal pair312,314. The programmable delay element pair370comprises a first programmable delay element320for receiving the signal I312and a second programmable delay element330for receiving the signal Q314. The control circuit360generates a control signal362based on the outputs325,335of the programmable delay element pair370. The control signal362may be a binary control signal, one shot logic signal, hex signal or any other suitable control signal. For the purposes of this application the control signal362will be described as a binary control signal. The programmable delay element pair370is configured by the binary control signal362to thereby provide the corrected quadrature phase signal pair as the outputs325,335of the programmable delay element pair370.

In accordance with some embodiments, the apparatus300may further comprise a tuning delay element395coupled to one of the programmable delay elements320,330. Furthermore, in some embodiments the quadrature phase generator310may generate an additional quadrature phase signal pair illustrated here as quadrature phase signal pair316,318comprising a third quadrature phase signal, hereafter referred to as an additional in-phase signal Ix316, and a fourth quadrature phase signal, hereafter referred to as an additional quadrature phase signal Qx318.

In accordance with the illustrated embodiment, the apparatus300may further comprise an additional programmable delay element pair380. The additional programmable delay element pair380includes the programmable delay elements340,350, for receiving the signals Ix316and Qx318. The control circuit360may generate an additional binary control signal364in response to outputs345,355of the additional programmable delay element pair380. Furthermore, the additional programmable delay element pair380may be configured by the additional binary control signal364to thereby provide the corrected quadrature phase signal pair as the outputs345,355of the additional programmable delay element pair380.

The apparatus300may further comprise a weighted inverter390to provide an inverted binary control signal366to one of the programmable delay elements, for instance to the programmable delay element330, of the programmable delay element pair370. Similarly, the apparatus300of the illustrated embodiment may further comprise an additional binary weighted inverter392to provide an inverted additional binary control signal368to one of the programmable delay elements, for instance to the programmable delay element350, of the additional programmable delay element pair380.

The quadrature phase generator310is designed to generate at least one quadrature phase signal pair. Each generated quadrature phase signal pair should ideally have a phase difference of 90 degrees between the in-phase signal (I or Ix) and the quadrature phase signal (Q or Qx). However, due to the aforementioned problems, signal path for signals I312, Ix316, Q314, and Qx318may have different propagation delays resulting in phase errors as illustrated inFIG. 1. Hence, the phase difference between the in-phase signal and the quadrature phase signal may not be 90 degrees. Variation from the ideal phase difference of 90 degrees is defined as a relative phase error.

The control circuit360is designed to receive signals327,337,347,357derived from outputs325,335,345,355of the programmable delay element pair370and the additional programmable delay element pair380. Furthermore, the control circuit360is designed to provide at least one control signal comprising a plurality of bits (BIT1, BIT2, . . . , BIT N) for configuring programmable delay element pair(s). For instance, the control circuit360generates the binary control signal362and the additional binary control signal364, for configuring the programmable delay element pair370and the additional programmable delay element pair380respectively.

FIG. 3also illustrates the first programmable delay element320in accordance with some embodiments of the invention. The programmable delay element320may comprise a plurality of binary weighted voltage-controlled delays322. In accordance with some embodiments, the plurality of binary weighted voltage-controlled delays322of the programmable delay element320are connected in series. The plurality of binary weighted voltage-controlled delays322are designed to be operable using a binary signal, for instance the binary control signal362. In accordance with the illustrated embodiment, each voltage-controlled delay322may be enabled or disabled by a bit (BIT1, BIT2. . . , BIT N) or an inverted bit of the plurality of bits of the binary signal.

When enabled, each voltage-controlled delay322delays an input signal, for instance the signal I312, by a predetermined time period. In accordance with some embodiments, each voltage-controlled delay322may delay the input signal by the predetermined time period which is a binary weighted multiple (1×, 2×, 4×, 8×, etc) of a constant time period. In accordance with some other embodiments, each voltage-controlled delay322may delay the input signal by the predetermined time period which is the constant time period. The programmable delay element320may further comprise an inverter324for driving current for the voltage-controlled delays322.

Operationally, the quadrature phase generator310of the illustrated embodiment, generates the signals I312and Q314in response to the LO input signal(s)305. The control circuit360generates the binary control signal362based on the outputs325,335. In accordance with some embodiments, the binary control signal362is generated by detecting the relative phase error for the signals327,337derived from the outputs325,335.

Operationally, the programmable delay elements may initially be preconfigured to enable some of the plurality of binary weighted voltage-controlled delays. Thus, the programmable delay elements may initially be preconfigured to delay the signals I312, Q314, Ix316and Qx318by a preconfigured time period. The programmable delay elements, when configured by the binary control signal362and the additional binary control signal364, varies (increases or decreases) amount of delay from the preconfigured time period. A range between maximum and minimum amount of delay for the programmable delay element is referred to as a tuning range for the programmable delay element.

In accordance with some embodiments, the first programmable delay element320and the second programmable delay element330are preconfigured for the preconfigured time period which is approximately at middle of the tuning range. The first programmable delay element320, receiving the signal I312is configured by the binary control signal362, and the second programmable delay element330, receiving the signal Q314, is configured by the inverted binary control signal366. Hence, the first programmable delay element320and the second programmable delay element330are oppositely configured resulting in opposite delays. The delay is adjusted for rising edge and falling edge of the quadrature phase signal pair312,314to simultaneously adjust the duty cycle of the quadrature phase signal pair312,314.

Thus, the binary control signal362configures the programmable delay element pair370to adjust the delay for the signals I312and Q314. The programmable delay element pair370thereby adjusts the delay (relative phase error) between the signals I312and Q314and the duty cycle of the signals I312and Q314to thereby provide the corrected signals I and Q as the outputs325,335.

Operationally, the quadrature phase generator310of the illustrated embodiment, may further generate the signals Ix316and Qx318in response to the LO input signal(s)305. The control circuit360may also generate the additional binary control signal364in response to the outputs345,355. In accordance with some embodiments, the additional binary control signal364is generated by detecting the relative phase error for the signals347,357derived from the outputs345,355. The delay between the signals Ix316and Qx318, and the duty cycle of the additional quadrature signal pair316,318may be adjusted in a similar fashion as the delay between the signals I312and Q314.

Thus, the additional binary control signal364configures the additional programmable delay element pair380to adjust the delay for the signals Ix316and Qx318. Hence, the additional programmable delay element pair380thereby adjusts the delay (relative phase) between the signals Ix316and Qx318and the duty cycle of the signals Ix316and Qx318to thereby provide the corrected signals Ix and Qx as the outputs345,355of the additional programmable delay element pair.

Furthermore, the tuning delay element395, when added, additionally delays the output325of the programmable delay element pair370. Hence, the tuning delay element395adjusts the tuning range of the programmable delay elements320,330to overcome problems caused by the variations due to the semiconductor manufacturing technologies. Similarly, the apparatus300may further comprise a tuning delay element396coupled to one of the programmable delay elements340,350.

In accordance with some embodiments, the quadrature phase generator310of the apparatus300may be implemented with a divide-by-N flip flop circuit, a polyphase filter, or the like. Furthermore, the quadrature phase generator310may generate other signals as required by the apparatus300. Accordingly, the apparatus300may include other programmable delay elements to receive other signals generated by the quadrature phase generator310.

In accordance with some embodiments, the control circuit360of the apparatus300may be a digital signal processor (DSP), an application specific integrated circuit (ASIC), or the like. The control circuit360may be configured to receive the signals, for instance the signals327,337derived from the outputs325,335of the programmable delay element pair(s). In accordance with some embodiments, the signals derived from outputs of the programmable delay element pair(s) may be down converted baseband signals derived by demodulating received data using the outputs of programmable delay element pair(s). In accordance with some other embodiments, the signals derived from outputs of programmable delay element pair(s) may be Radio Frequency (RF) signals derived by modulating data using the outputs of programmable delay element pair(s). In accordance with yet other embodiments, the control circuit360may be configured to receive the outputs of programmable delay element pair(s). Thus, the apparatus300may be used to generate corrected quadrature phase signal pair(s) for a transmitter and a receiver.

In accordance with some other embodiments, the control circuit360of the apparatus300may generate binary signal(s) by using techniques such as user controlled feedback, DSP demodulation and quadrature phase determination, spectrum analysis, time sampled phase error detection, etc. In accordance with other embodiments, the control circuit360may generate binary control signal(s) based on a lookup table with entries for a relative phase error between the in-phase signals and quadrature signals and a corresponding binary control signal value. Furthermore, while the control circuit360of the illustrated embodiment generates binary control signal(s) for each programmable delay element pair, in accordance with other embodiments, the control circuit360may generate other binary control signals for other programmable delay element pairs as required. In accordance with yet other embodiments, the control circuit360may provide a separate binary control signal for each programmable delay element. In accordance with other embodiments, the control circuit may generate other control signal(s) such as hexadecimal, one shot logic, etc.

Programmable delay element320may be implemented in a variety of ways. The programmable delay element320can be implemented, for example, utilizing electrical and/or mechanical technology, such as transistors, inductors, capacitors, and/or MEMS devices to name a few. Any means of creating a signal delay or signal advancement to vary drive strength can be used. In accordance with the illustrated embodiment, a plurality of binary weighted voltage controlled delays322may be circuits utilizing voltage-controlled capacitors, inductors or metal oxide semiconductor (MOS) transistor devices, inverters or combination of these. In accordance with some other embodiment the programmable delay element may further comprise an inverter, for instance the inverter324, configured to provide a variable drive strength in response to the control signal. In accordance with other embodiments, the programmable delay element may be designed to be operable using other control signal(s) such as hexadecimal, one shot logic, or the like. Furthermore, illustrated architecture of the programmable delay element320may be used for other programmable delay elements of the apparatus300, for instance the programmable delay elements330,340,350.

FIG. 4is an exemplary schematic diagram illustrating an apparatus400for generating corrected quadrature phase signal pairs in accordance with some embodiments of the invention. The apparatus400comprises four D-type flip-flops410, programmable delay elements420,430,440,450and a control circuit460. A quadrature phase generator of the illustrated embodiment is implemented using a divide-by-N flip flop circuit comprising the D-type flip-flops410. The divide-by-N flip flop circuit receives an LO input signal405as an input for CLK node of the D-type flip flops410and produces signals I412, Q414, Ix416, and Qx418. The signals412,414,416,418are provided to the programmable delay elements420,430,440,450. In the illustrated embodiment, the apparatus400thereby generates corrected in-phase (I, Ix) and quadrature phase signals (Q, Qx) as outputs I425, Q435, Ix445, Qx455of the programmable delay elements420,430,440,450.

The quadrature phase generator is similar to the quadrature phase generator310described above. The divide-by-N flip flop circuit generates a first quadrature phase signal pair comprising a first quadrature phase signal, referred to as the signal I412and a second quadrature phase signal, referred to as the signal Q414. The divide-by-N flip flop circuit also generates a second quadrature phase signal pair comprising a third quadrature phase signal, referred to as the signal Ix416and a fourth quadrature phase signal, referred to as the signal Qx418. As mentioned with reference toFIG. 3, the signals I412and Q414, ideally have phase difference of 90 degrees. Similarly, the signals Ix416and Qx418ideally have phase difference of 90 degrees. However, due to the aforementioned problems, the signals I412and Q414, and the signals Ix416and Qx418may have relative phase errors.

The programmable delay elements420,430form a first programmable delay element pair to receive the first quadrature phase signal pair412,414. Similarly, the programmable delay elements440,450form a second programmable delay element pair to receive the second quadrature phase signal pair416,418.

The control circuit460generates a first control signal462, for example a binary control signal, in response to the outputs425,435of the first programmable delay element pair. The control circuit460also generates a second control signal464, for example another binary control signal, in response to the outputs445,455of the second programmable delay element pair. The control circuit460provides the first binary control signal462to the first programmable delay element pair. The control circuit460provides the second binary control signal464to the second programmable delay element pair.

The first programmable delay element pair is configured by the first binary control signal462to thereby provide corrected first quadrature phase signal pair as the outputs425,435of the first programmable delay element pair. Similarly, the second programmable delay element pair is configured by the second binary control signal464to thereby provide corrected second quadrature phase signal pair as the outputs445,455of the second programmable delay element pair.

In accordance with the illustrated embodiment, each of the first binary control signal462and the second binary control signal464comprise four bits (BIT1, . . . , BIT4). Each programmable delay element420,430,440,450, may comprise a plurality of voltage-controlled N-type metal oxide semiconductor (NMOS) transistor devices422,432,442,452. The plurality of voltage-controlled N-type metal oxide semiconductor (NMOS) transistor devices are connected in series. In accordance with the illustrated embodiment, each programmable delay element420,430,440,450comprises four NMOS transistor devices, for instance four NMOS transistor devices422for the programmable delay element420, connected in series.

Each NMOS transistor device comprises a drain and a source node coupled together. Furthermore, each NMOS transistor device422,432comprises a gate node for receiving a bit (BIT1, . . . , BIT4) and an inverted bit of the first binary control signal462respectively. Similarly, each NMOS transistor device442,452comprises a gate node for receiving a bit (BIT1, . . . , BIT4) and an inverted bit of the second binary control signal464respectively. Each voltage-controlled NMOS transistor device is enabled or disabled in response to the bit (BIT1, BIT2, BIT3, or BIT4), of a binary signal. Thus, each voltage-controlled NMOS transistor device, when enabled, introduces delay to an input signal.

Furthermore, each NMOS transistor device, for instance the NMOS transistor devices422, is designed to have a different aspect ratio. For the illustrated embodiment, the aspect ratio of the four NMOS transistor devices is 1×, 2×, 4×, and 8× of a predefined aspect ratio. The predefined aspect ratio is determined based on the smallest amount of delay, also the constant time period as described earlier, that may be introduced by the programmable delay element. The smallest amount of delay that may be introduced by the programmable delay element is determined based on delay introduced by smallest NMOS transistor device and is also known as resolution of the programmable delay element. Furthermore, the tuning range of the programmable delay elements420,430,440,450ranges from 0× to 15× of the constant time period.

In the illustrated embodiment, each programmable delay element further comprises a driving inverter, for instance inverter424, for driving the plurality of voltage-controlled NMOS transistor devices. Furthermore, the programmable delay elements further comprise a plurality of driving inverters, for instance inverters426, to drive the gate nodes of the voltage-controlled NMOS transistor devices.

The apparatus400further comprises a first binary weighted inverter490for providing the bits of the first binary control signal462to the programmable delay element420. The apparatus400further comprises a second binary weighted inverter492for providing the bits of the second binary control signal464to the programmable delay element440.

Operationally, the quadrature phase generator generates the first quadrature signal pair412,414and the second quadrature signal pair416,418. Initially, the outputs425,435of the first programmable delay element pair are the first quadrature phase signal pair412,414delayed by a preconfigured time period. Similarly, the outputs445,455of the second programmable delay element pair are the second quadrature phase signal pair416,418delayed by the preconfigured time period. For the illustrated embodiment, the signals I412, Q414, Ix416, and Qx418are delayed by the preconfigured time period which is at the middle of the tuning range, in this case8x of the predefined time period. The control circuit460generates the first binary control signal462and the second binary control signal464in response to the outputs425,435and the outputs445,455respectively. The first binary control signal462is used to configure the first programmable delay element pair. The second binary control signal464is used to configure the second programmable delay element pair.

The first programmable delay element pair adjusts a delay between the signal I412and the signal Q414to thereby provide a corrected first quadrature phase signal pair as the outputs425,435. In accordance with the illustrated embodiments, the delay of the signals I412and Q414, is oppositely adjusted from the preconfigured time period. The delay is adjusted for rising edge and falling edge of the signals I412and Q414. The first programmable delay element pair, thereby, adjusts the duty cycle of the first quadrature phase signal pair412,414. The second programmable delay element also adjusts a delay between the signal Ix416and the signal Qx418to thereby provide a corrected second quadrature phase signal pair as the outputs445,455. Similarly, the second programmable delay element pair also adjusts duty cycle of the second quadrature phase signal pair416,418.

FIG. 5is an example of a graph illustrating adjusting the delay between quadrature phase signal pairs in accordance with some embodiments of the invention. The graph500illustrates signals I512, Q514, Ix516and Qx518generated by the quadrature phase generator. The graph500also illustrates waveforms for outputs525,535,545,555of the programmable delay elements configured as described earlier. Dotted lines510,520, . . . ,590represent ideal phase for rising or falling edge of the signals I512, Q514, Ix516and Qx518.

In accordance with some embodiments, a delay501between rising edges of the signals I512and Q514is adjusted. As illustrated, the delay501between the signals I512and Q514is adjusted in opposite directions511,521to result in delay502between rising edges of the outputs525,535. Similarly, a delay503between falling edges of the signals I512and Q514is oppositely adjusted533,543for to result in a delay504between falling edges of the outputs525,535. Adjusting delays between the rising and falling edges of the signals I512and Q514results in simultaneous adjustment of duty cycle for the outputs525,535. Thus, corrected in-phase I and quadrature phase Q signals are thereby provided as the outputs525,535.

Similarly, delay505between rising edges of the signals Ix516and Qx518is adjusted. As illustrated, the delay505between the rising edges of the signal Ix516and Qx518is adjusted in opposite directions531,541to result in delay506between rising edges of the outputs545,555. Furthermore, as illustrated, delay507between falling edges of the signal Ix516and Qx518is similarly adjusted553,563to result in delay508between falling edges of the outputs545,555. Adjusting delays between the rising and falling edges of the signals Ix516and Qx518results in simultaneous adjustment of duty cycle for the outputs545,555. Thus, corrected in-phase Ix and quadrature phase Qx signals are thereby provided as the outputs545,555.

Graph500is shown only for illustrative purposes and several other variants may exist. In accordance with some other embodiments, delay for the falling edges and the rising edges of one of the signals I512and Q514or the signals Ix516and Qx518may be adjusted.

FIG. 6is a flow chart illustrating a method600of generating a corrected quadrature phase signal pair in accordance with some embodiments of the invention. The method600starts at605by generating a local oscillator signal at610. Subsequently, a quadrature phase signal pair, the in-phase signal I and the quadrature phase signal Q, is generated in response to the LO signal in step620. The generated quadrature phase signal pair, the signals I and Q, are as described earlier.

The method600continues with step630by generating a control signal, shown here as a binary control signal, in response to the corrected quadrature phase signal pair. In accordance with some embodiments, the method600may further include delaying the quadrature phase signal pair by a preconfigured time period to provide the corrected quadrature phase signal pair before generating the binary control signal. In accordance with some embodiments, the binary control signal is generated in response to the signals derived from the corrected quadrature phase signal pair.

Subsequent to step of generating the binary control signal, the method600performs the step640of adjusting delay between the quadrature phase signal pair, the signals I and Q, responsive to the binary control signal. In accordance with some embodiments, the step640may comprise adjusting the delay between the falling and rising edges of the signals I and Q. Simultaneous to the step640, method600also performs step650of adjusting duty cycle of the quadrature phase signal pair responsive to the generated binary control signal. As a result of the steps640and650, the corrected quadrature phase signal pair is generated. Furthermore, the method600may continue by repeating the steps of generating the binary control signal through adjusting the duty cycle by continuously adjusting the delay to provide the corrected quadrature phase signal pair.

Additionally, while the steps of method600describe generating the corrected quadrature phase signal pair, the method600may generate additional quadrature phase signal pair(s). Furthermore, the method600may generate additional binary control signal(s) for adjusting delay between the additional quadrature phase signal pair(s). The method600may also adjust duty cycle for the additional quadrature phase signal pair(s) to generate additional corrected quadrature phase signal pair(s).

FIG. 7is a block diagram illustrating an exemplary communication device700utilizing the apparatus300for generating corrected quadrature phase signal pairs in accordance with some embodiments of the invention. The communication device700includes antennas701,703, the apparatus300hereafter referred as a apparatus705, a receiver740, and a transmitter750. In the illustrated embodiment, the apparatus705generates a corrected quadrature phase signal pair775comprising a corrected in-phase signal725and a corrected quadrature phase signal735to be utilized in the communication device700.

In the illustrated embodiment, the receiver740and the transmitter750require a quadrature phase signal pair for demodulating and modulating data. The receiver740and the transmitter750use the corrected quadrature phase signal pair775generated by the apparatus705. In this embodiment, the receiver740uses the corrected quadrature phase signal pair775for demodulating a received signal745. The receiver740thereby provides a demodulated signal pair747comprising an in-phase and a quadrature phase demodulated signals. Similarly, the transmitter750of the communication device700uses the corrected quadrature phase signal pair775for modulating data755. The transmitter750thereby provides a modulated signal pair757comprising an in-phase and a quadrature phase modulated signal.

As illustrated, the apparatus705comprises a quadrature phase generator710, programmable delay elements720,730, and a control circuit760. The programmable delay elements720,730form a programmable delay element pair770. The quadrature phase generator710generates an in-phase signal I712and a quadrature phase signal Q714. The signals I712and Q714are provided to the programmable delay element pair770. The control circuit760generates a control signal762for the programmable delay element pair770. The control signal762is generated in response to the demodulated signal pair747or the modulated signal pair757. The apparatus705also includes a binary weighted inverter790for providing an inverted binary control signal764for configuring the programmable delay element730. Thus, the programmable delay element pair770provides the corrected quadrature phase signal pair775as outputs of the programmable delay element pair770. The corrected quadrature phase signal pair775may be utilized by the receiver740or the transmitter750of the communication device700.

Operationally, the communication device700uses the corrected quadrature phase signal pair775for the receiver740and the transmitter750. The antenna701provides the received signal745to the receiver740. The receiver740also receives the corrected quadrature phase signal pair775from the apparatus705to thereby provide the demodulated signal pair747. In the illustrated embodiment, the apparatus705operates as described earlier. The control circuit760may use the demodulated signal pair747to generate the control signal762. The control signal762and the inverted binary control signal764configure the programmable delay element pair770. Hence, the corrected quadrature phase signal pair775is provided as the outputs of the programmable delay element pair770for use in the receiver740.

The transmitter750receives data755to be transmitted and the corrected quadrature phase signal pair775from the apparatus705to thereby provide the modulated signal pair757. The apparatus705operates as described earlier. The control circuit760may use the modulated signal pair757to generate the control signal762. The control signal762and the inverted binary control signal764configure the programmable delay element pair770. Hence, the corrected quadrature phase signal pair775is provided as the outputs of the programmable delay element pair770for use in the transmitter750. The modulated signal pair757is transmitted by the antenna703.

In accordance with some other embodiments, the communication device700may operate as a multiband communication device. In such a scenario, the apparatus705may generate multiple corrected quadrature phase signals of different frequencies to receive or transmit plurality of signals. In accordance with other embodiments, the apparatus705may generate multiple corrected quadrature phase signal pairs of different phases based on the modulation/demodulation scheme used by the communication device700. Further, the receiver740, the transmitter750and the antennas701,703may be combined to form a transceiver or may operate independently. Furthermore, the apparatus705may have different architecture based on use of different modulation/demodulation schemes.

Thus, the communication device700utilizes a single apparatus705for generating multiple quadrature phase signal pairs to achieve a compact and robust design for the communication device700. The compact design for the communication device700facilitates the ability to provide multiband functionality in portable communication devices. Additionally, the robust design for the apparatus705reduces the complexity of the control circuitry required for error correction. Thus, the area requirement for the communication device700is further reduced.

Hence, there has been provided a method and an apparatus for generating corrected quadrature phase signal pairs. The method and apparatus of the present invention avoids the use of modulated or demodulated baseband signals for error correction in a communication device. The apparatus generating the corrected quadrature phase signal pair allows a designer to remove some of the design restrictions for high precision quadrature phase generator. Thus, the problems such as circuit complexity, parts count, board area, power consumption, controller and logic complexity, and cost are greatly reduced. By utilizing programmable delay elements in the apparatus, the relative phase error for the quadrature signal pairs is reduced.

Additionally, the apparatus is particularly useful in the communication devices using quadrature phase signal pairs. The communication devices using the apparatus of the present inventions avoid problems, such as the sideband images, associated with the relative phase error. Furthermore, the apparatus eliminates the need for separate quadrature phase generators for the receiver and the transmitter of the communication device. Hence, the apparatus and the method achieve a compact and robust design for the communication device.