System control device

A system control device comprises a system LSI section having a plurality of functional blocks, a system control microcomputer section for controlling the control register of each of the functional blocks, an address decoding section for decoding an access address to a predetermined byte in a control register which the system control microcomputer section attempts to access, and issuing an access control signal to the whole of a single control register including the predetermined byte, an access control section for changing the access control signal to the whole of the single control register to an access control signal to the predetermined bytes of the plurality of control registers included in the system LSI section, with respect to access to an address to the predetermined byte, and an access mode control register for indicating whether or not the changing by the access control section is to be performed.

CROSS REFERENCE TO RELATED APPLICATIONS

This Non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2006-279177 filed in Japan on Oct. 12, 2006, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a system control device which controls a system LSI having a plurality of functional blocks integrated on a single chip.

2. Description of the Related Art

System control devices generally comprise a system control microcomputer section and a system LSI section which has a plurality of functional blocks integrated on a single chip. Each functional block comprises a control register. Portions of an address space which can be accessed by the system control microcomputer section are assigned to these control registers. The system control microcomputer section controls the system LSI section having the functional blocks by accessing the control registers. For example, a system control device which accesses a plurality of control registers is disclosed in Japanese Unexamined Patent Application Publication No. 2005-327078.

FIG. 9is a block diagram showing a whole configuration of a conventional system control device and a schematic diagram showing an operation of the system control device.

InFIG. 9, the system control device900comprises a system control microcomputer section910, an address decoding section911, and a system LSI section920which has four Direct Memory Access (DMA) controllers921,922,923and924which are integrated on a single chip. The four DMA controllers921to924are controlled by control registers925,926,927and928which are provided therein. The control registers925to928are accessed and controlled by the system control microcomputer section910. For the access, the address decoding section911decodes an access address to a control register which the system control microcomputer section910attempts to access, into an address assigned to the control register.

Here, the system control device900uses the four DMA controllers921to924to transfer four pieces of image data PA, PB, PC and PD stored in different address areas931,932,933and934of a main memory930to four buffer areas941,942,943and944of a buffer940. The image data PA to PD transferred to the buffer940are combined by an image combining block950to generate combined image data ABCD.

The image data PA to PD stored in the address areas931to934of the main memory930are updated by access from the outside of the system control device900a predetermined period of time after being transferred to the buffer940by the DMA controllers921to924. After being updated, the updated image data PA to PD are transferred again to the buffer areas941to944of the buffer940, respectively, using the DMA controllers921to924. The image data PA to PD transferred to the buffer940are combined into combined image data ABCD.

Regarding hardware design for system control devices, when a plurality of DMA controllers having the same function are mounted on hardware, it is often that DMA controllers having the same design data are mounted in parallel, so that the control registers of the DMA controllers have a common address or bit position in the DMA controllers. Specifically, when an address of 1000 of the DMA controller921is assigned to the address of the control register925in the DMA controller921, addresses of 1000 of the DMA controllers922to924are also assigned to the addresses of the control registers926to928in the DMA controllers922to924, respectively.

FIG. 10is a schematic diagram showing access to the control registers925to928in the conventional system control device900.

InFIG. 10, the control registers925to928are provided in the DMA controllers921to924, respectively. The control registers925to928each have 32 bits (four bytes). The Least Significant Bytes (LSBs) of the control registers925to928include startup bits which are used to start up the respective DMA controllers921to924.

The system control microcomputer section910is a 32-bit microcomputer. A register access bus (host bus) via which the control registers925to928are accessed has a width of 32 bits.

In the system control device900, when the image data PA is transferred to the buffer area941in the buffer940, the system control microcomputer section910accesses the LSB of the control register925. In this case, the address decoding section911receives an access address to the LSB of the control register925from the system control microcomputer section910, and issues an access control signal for the whole control register925. In other words, when the LSB of the control register925is accessed, the access control signal is issued for the whole 32-bit control register925.

When the system control device900is used to transfer the four pieces of image data PA to PD from the main memory930to the buffer940, four access control signals are sequentially issued to the respective control registers925to928to access the LSBs of the control registers925to928, thereby starting up the DMA controllers921to924, which in turn perform the transfer.

SUMMARY OF THE INVENTION

However, in the conventional system control device900ofFIG. 9, when the four pieces of image data PA to PD are transferred, access control signals are sequentially issued to the respective 32-bit control registers925to928. Therefore, the system control microcomputer section910needs to access the control registers925to928a total of four times. Therefore, if there are a number of control registers to be accessed, it disadvantageously takes a long time to access all the control registers.

Also, as shown inFIG. 11, in the system control microcomputer section910, parameters, such as a transfer source address, a transfer destination address and the like, are set for each of the DMA controllers921to924(step S1100), and thereafter, a startup process and a startup completion confirming process may be performed for each of the DMA controllers921to924(step S1101), and the startup process and startup completion confirming process of step S1101may be repeatedly performed until all data processes are completed in step S1102. When such an application is executed, the load of a software process of accessing the control registers of the DMA controllers921to924is significantly large in the system control microcomputer section910.

The present invention has been achieved in view of the above-described problems. An object of the present invention is to provide a system control device in which a system control microcomputer section, when accessing control registers, can simultaneously access predetermined bytes of the control registers.

To achieve the object, according to the present invention, not only the whole of a single control register can be specified by performing register access once, but also a plurality of control registers can be simultaneously specified.

Specifically, a system control device according to a first embodiment of the present invention comprises a system LSI section having a plurality of functional blocks integrated on a single chip, each functional block having a control register, a system control microcomputer section for controlling the control register of each of the plurality of functional blocks, an address decoding section for decoding an access address to a predetermined byte in a control register which the system control microcomputer section attempts to access, and issuing an access control signal to the whole of a single control register including the predetermined byte, an access control section for changing the access control signal to the whole of the single control register to an access control signal to the predetermined bytes of the plurality of control registers included in the system LSI section, with respect to access to an address to the predetermined byte, and an access mode control register for indicating whether or not the changing of the access control signal by the access control section is to be performed.

A system control device according to a second embodiment of the present invention comprises a system LSI section having a plurality of functional blocks integrated on a single chip, each functional block having a control register, a system control microcomputer section for controlling the control register of each of the plurality of functional blocks, an address decoding section for decoding an access address which the system control microcomputer section attempts to access, and an access control section for selecting and issuing either an access control signal to the whole of a single control register included in the system LSI section or an access control signal to predetermined bytes of the plurality of control registers included in the system LSI section, based on the address decoded by the address decoding section.

A system control device according to a third embodiment of the present invention comprises a system LSI section having a plurality of functional blocks integrated on a single chip, each functional block having a control register, a system control microcomputer section for controlling the control register of each of the plurality of functional blocks, an address decoding section for decoding an access address which the system control microcomputer section attempts to access, and an access control section for selecting and issuing either an access control signal to the whole of a single control register included in the system LSI section or an access control signal to all bytes of a plurality of predetermined control registers of the plurality of control registers included in the system LSI section, based on the address decoded by the address decoding section.

In the system control devices of the first and second embodiments of the present invention, an access control signal to the whole of a predetermined control register in a system LSI section is changed to an access control signal to a predetermined byte of each of a plurality of control registers, or an access address for access to a predetermined byte of each of a plurality of control registers is additionally provided. Thereby, predetermined bytes of a plurality of control registers can be simultaneously accessed.

In the system control device of the third embodiment of the present invention, access addresses for access to all bytes of a plurality of control registers included in a system LSI section are additionally provided, thereby making it possible to simultaneously access all bytes of control registers in a plurality of functional blocks.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, system control devices according to embodiments of the present invention will be described with reference to the accompanying drawings.

First Embodiment

FIG. 1is a block diagram showing a whole configuration of a system control device according to a first embodiment of the present invention and a schematic diagram showing access to control registers by the system control device.

InFIG. 1, the system control device100comprises a CPU (system control microcomputer section)110, an address decoding section111, an access control section115, an access mode control register116, and a system LSI section120which has four DMA controllers (functional blocks)121,122,123and124integrated on a single chip. The four DMA controllers121to124comprise control registers125,126,127and128, respectively, thereinside. Here, the control registers125to128each have 32 bits (4 bytes). LSBs125a,126a,127aand128aof the control registers125to128include startup bits which are used to start up the DMA controllers121to124, respectively.

The CPU110is a 32-bit microcomputer. A register access bus (host bus) for accessing the control registers125to128has a width of 32 bits.

In the system control device100, in order to start up all the four DMA controllers121to124in the system LSI section120, the CPU110initially rewrites a value of the access mode control register116so that a register access mode is switched from an access mode in which the whole 32 bits of one control register are accessed to an access mode in which the LSBs125ato128aof the four control registers125to128are simultaneously accessed. Thereafter, the CPU110accesses the LSB125aof the control register125. Thereafter, the address decoding section111decodes an access address to the LSB125aof the control register125which the CPU110attempts to access, and issues an access control signal to the whole 32 bits of the control register125. The access control section115reads the value of the access mode control register116, and changes the access control signal to the whole 32 bits of the control register125to an access control signal to the LSBs125ato128aof the four control registers125to128included in the system LSI section120. By changing the access control signal, the CPU110simultaneously accesses the LSBs125ato128ato simultaneously start up the four DMA controllers121to124. Here, the access mode control register116indicates whether or not the access control section115changes the access control signal to change combination of control registers. The access mode control register116is controlled by the CPU110.

As described above, in this embodiment, the access control section115changes the access control signal to the whole control register125of the system LSI section120to the access control signal to the LSBs125ato128aof the four control registers125to128in the system LSI section120. Therefore, all the four DMA controllers121to124in the system LSI section120can be started up by performing register access once, as compared to four times in the conventional art. Thereby, the reduction of the number of times of register access makes it possible to increase the efficiency of software and reduce the processing time of software.

Although a write process is performed by accessing the startup bits of the LSBs125ato128aof the control registers125to128in this embodiment, a read process can also be performed with respect to the LSBs125ato128aof the control registers125to128. For example, the LSBs125ato128amay include status bits of the DMA controllers121to124, respectively. The status bits may indicate whether the DMA controllers121to124are performing transfer, have completed transfer, or are waiting for startup or may indicate various errors. In this case, the statuses of the four DMA controllers121to124in the system LSI section120can be simultaneously read and confirmed.

Also, although it has been described in this embodiment that register access is performed with respect to control registers in a DMA controller, register access may be performed with respect to control registers in another functional block.

Second Embodiment

FIG. 2is a block diagram showing a whole configuration of a system control device according to a second embodiment of the present invention and a schematic diagram showing access to control registers in the system control device.

The system control device200of this embodiment is different from the system control device100of the first embodiment ofFIG. 1in that the system control device200comprises a byte position control section201for changing a position to which an access control signal is to be issued and a byte position control register202for storing information about the byte position changed by the byte position control section201. The other parts are similar to those of the first embodiment and will not be described below.

The byte position control section201receives an access control signal whose register access mode has been changed by the access control section115and the byte position information of the byte position control register202, and changes a byte position to which an access control signal is to be issued. For example, when the byte position control register202stores information indicating the third byte, the byte position control section201receives an access control signal to the LSBs125ato128aof the four control registers125to128in the system LSI section120and changes the access control signal into an access control signal which is to be issued to the byte position to third bytes125cto128cof the control registers125to128. Here, the byte position information stored in the byte position control register202is accessed and controlled by the CPU110.

In the system control device200, for example, the LSBs125ato128aof the control registers125to128may each include a startup bit and the third bytes125cto128cof the control registers125to128may each include a status bit. In this case, as shown inFIG. 3, initially, the CPU110sets parameters, such as transfer source addresses, transfer destination addresses and the like of the four DMA controllers121to124in the system LSI section120(step S300), and thereafter, the access mode control register116is set so that the access control section115changes the register access mode (step S301). Thereafter, the byte position information of the byte position control register202is set to be the first byte, and the LSBs125ato128aof the control registers125to128are simultaneously accessed to perform a startup process (write process) with respect to the four DMA controllers121to124simultaneously, i.e., in parallel (step S302). Thereafter, the byte position information of the byte position control register202is set to be the third byte, and the third bytes125cto128cof the control registers125to128are simultaneously accessed to perform a startup completion confirming process (read process) with respect to the four DMA controllers121to124simultaneously, i.e., in parallel (step S302).

As described above, in this embodiment, even when bytes which are frequently accessed extend over the four control registers125to128in the system LSI section120, and none of the bytes are present in the LSBs125ato128aof the control registers125to128, the third bytes125cto128cof the control registers125to128can be simultaneously accessed. Therefore, the number of times of register access can be further reduced, so that the processing time of software can be further reduced, as compared to register access in the conventional system control device900ofFIG. 11. In addition, the degree of freedom and efficiency of software design can be improved.

Third Embodiment

FIG. 4is a block diagram showing a whole configuration of a system control device according to a third embodiment of the present invention and a schematic diagram showing access to control registers in the system control device.

The system control device400of this embodiment is different from the system control device200of the second embodiment ofFIG. 2in that the system control device400comprises an access mask control register (access mask control register section)401for masking an access control signal to the control registers125to128in units of bits, and an AND circuit group (access mask control register section)402including128AND circuits connected thereto. The other parts are similar to those of the second embodiment and will not be described below. Note that, inFIG. 4, only four AND circuits are shown in the AND circuit group402.

The access mask control register401performs a mask control in units of bits with respect to an access control signal issued by the byte position control section201so that bits of the control registers125to128whose current values are not desired to be changed or bits which must not be accessed due to a limitation on hardware are not affected by the access control signal. The AND circuit group402is used for the mask control. The AND circuit group402includes128AND circuits corresponding to a total of 4×32 bits of the four control registers125to128. The bits which are specified to be subjected to the mask control by the access mask control register401are accessed and controlled by the CPU110.

As described above, in this embodiment, when an access control signal is issued even to a control register or a byte which includes a bit whose current value is not desired to be changed, a mask control is performed with respect to the bit which is not desired to be accessed, thereby making it unnecessary to read, modify, or write the bit. Therefore, only a bit(s) which is desired to be accessed can be subjected to a control using an access control signal, resulting in a further increase in efficiency of software.

Fourth Embodiment

FIG. 5is a block diagram showing a whole configuration of a system control device according to a fourth embodiment of the present invention and a schematic diagram showing access to control registers in the system control device.

InFIG. 5, the system control device500comprises a CPU (system control microcomputer section)510, an address decoding section511, an access control section515, and a system LSI section520which has four DMA controllers (functional blocks)521,522,523and524integrated on a single chip. The four DMA controllers521to524comprise control registers525,526,527and528, respectively, thereinside.

In the system control device500, in addition to addresses for access to the control registers525to528, addresses for access to predetermined bytes of the control registers525to528are provided. Specifically, addresses for simultaneous access to the LSBs525a,526a,527aand528aof the control registers525to528, addresses for simultaneous access to the second bytes525b,526b,527band528bof the control registers525to528, addresses for simultaneous access to the third bytes525c,526c,527cand528cof the control registers525to528, and addresses for simultaneous access to the fourth bytes525d,526d,527dand528dof the control registers525to528are additionally provided.

When the LSBs525ato528aof the control registers525to528are simultaneously accessed, the addresses for simultaneous access to the LSBs525ato528aare accessed from the CPU510. Thereafter, the address decoding section511decodes the access addresses to the LSBs525ato528awhich the CPU510attempts to access. Thereafter, the access control section515selects and issues an access control signal to the LSBs525ato528aof the control registers525to528based on the addresses decoded by the address decoding section511to simultaneously access the LSBs525ato528a.

Also, when the whole control register525is accessed, the addresses for access to the whole control register525are accessed from the CPU510, the access addresses are decoded by the address decoding section511, and based on the decoded addresses, the access control section515selects and issues an access control signal to the whole control register525.

As described above, in this embodiment, addresses for simultaneous access to predetermined bytes of the control registers525to528are additionally provided, and the addresses are accessed from the CPU510, thereby making it possible to simultaneously access predetermined bytes of the control registers525to528by performing register access once. Therefore, the reduction of the number of times of register access can make it possible to increase the efficiency of software.

Also, as is different from the above-described first and second embodiments, it is not necessary to provide the access mode control register116, the byte position control section201, or the byte position control register202, resulting in a reduction in hardware scale.

Fifth Embodiment

FIG. 6is a block diagram showing a whole configuration of a system control device according to a fifth embodiment of the present invention and a schematic diagram showing access to control registers in the system control device.

The system control device600of this embodiment is different from the system control device500of the fourth embodiment ofFIG. 5in that the system control device600comprises an access mask control register (access mask control register section)601which masks an access control signal to the control registers525to528in units of bits, and an AND circuit group (access mask control register section)602which comprises128AND circuits connected thereto. The other parts are similar to those of the fourth embodiment and will not be described below. Note that, inFIG. 6, only four AND circuits are shown in the AND circuit group602.

The access mask control register601performs a mask control in units of bits with respect to an access control signal issued by the access control section515so that bits of the control registers525to528whose current values are not desired to be changed or bits which must not be accessed due to a limitation on hardware are not affected by the access control signal. The AND circuit group602is used for the mask control. The AND circuit group602includes128AND circuits corresponding to a total of 4×32 bits of the four control registers525to528. The bits which are specified to be subjected to the mask control by the access mask control register601are accessed and controlled by the CPU510.

As described above, in this embodiment, when an access control signal is issued even to a control register or a byte which includes a bit whose current value is not desired to be changed, a mask control is performed with respect to the bit which is not desired to be accessed, thereby making it unnecessary to read, modify, or write the bit. Therefore, only a bit(s) which is desired to be accessed can be subjected to a control using an access control signal, resulting in a further increase in efficiency of software.

Sixth Embodiment

FIG. 7is a block diagram showing a whole configuration of a system control device according to a sixth embodiment of the present invention and a schematic diagram showing access to control registers in the system control device.

InFIG. 7, the system control device700comprises a CPU (system control microcomputer section)710, an address decoding section711, an access control section715, and a system LSI section720which has four DMA controllers (functional blocks)721,722,723and724integrated on a single chip. The four DMA controllers721to724comprise control registers725,726,727and728, respectively.

In the system control device700, in addition to addresses for access to the control registers725to728, addresses for access to all bits of a plurality of predetermined control registers of all control registers provided in the system LSI section720are additionally provided. Specifically, addresses for access to all bits of the four control registers725to728of the system LSI section720or addresses for access to all bits of the two control registers725and726in the system LSI section720are additionally provided.

When all the bits of the four control registers725to728provided in the system LSI section720are simultaneously accessed, the addresses for access to all the bits of the four control registers725to728are accessed from the CPU710. Thereafter, the address decoding section711decodes the access addresses to all the bits of the four control registers725to728which the CPU710attempts to access. Thereafter, the access control section715selects and issues an access control signal to all the bits of the four control registers725to728based on the addresses decoded by the address decoding section711to access all the bits of the four control registers725to728simultaneously.

Here, access to all bits of a plurality of predetermined control registers of all the control registers provided in the system LSI section720is performed only for write processes, and a value which is written into a bit is common to bits in each control register to be accessed. The common value is written in units of control registers, so that a value output via a host bus from the CPU710has 32 bits. Therefore, bits exceeding the bit width of the host bus can be simultaneously accessed to set new values thereinto.

Also, when the whole control register728is accessed, addresses for simultaneous access to the whole control register728are accessed from the CPU710, the access addresses are decoded by the address decoding section711, and based on the decoded addresses, the access control section715selects and issues an access control signal to the whole control register728.

As described above, in this embodiment, addresses for simultaneous access to all bits of a plurality of predetermined control registers of all the control registers725to728provided in the system LSI section720are additionally provided and are accessed from the CPU710, thereby making it possible to access control registers exceeding the bit width of the host bus of the CPU710by performing register access once. Therefore, the reduction of the number of times of register access makes it possible to increase the efficiency of a software process. Thereby, for example, when all interrupt processes remaining after the previous operation are cleared before starting up a plurality of DMA controllers provided in a system LSI section, when a plurality of DMA controllers having a common DMA transfer mode or an operation mode (addressing, a factor to initiate startup, etc.) is started up, or the like, a common value can be set in units of registers by performing register access once.

Although addresses for access to all bits of the four control registers725to728or addresses for access to all bits of the two control registers725and726are provided in this embodiment, the number of control registers to be accessed is not particularly limited.

Seventh Embodiment

FIG. 8is a block diagram showing a whole configuration of a system control device according to a seventh embodiment of the present invention and a schematic diagram showing access to control registers in the system control device.

The system control device800of this embodiment is different from the system control device700of the sixth embodiment ofFIG. 7in that the system control device800comprises an access mask control register (access mask control register section)801which masks an access control signal to the control registers725to728in units of bits, and an AND circuit group (access mask control register section)802which comprises 128 AND circuits connected thereto. The other parts are similar to those of the sixth embodiment and will not be described below. Note that, inFIG. 8, only 16 AND circuits are shown in the AND circuit group802.

The access mask control register801performs a mask control in units of bits with respect to an access control signal issued by the access control section715so that bits of the control registers725to728whose current values are not desired to be changed or bits which must not be accessed due to a limitation on hardware are not affected by the access control signal. The AND circuit group802is used for the mask control. The AND circuit group802includes 128 AND circuits corresponding to a total of 4×32 bits of the four control registers725to728. The bits which are specified to be subjected to the mask control by the access mask control register801are accessed and controlled by the CPU710.

As described above, in this embodiment, a mask control is performed with respect to the bit which is not desired to be accessed, thereby making it unnecessary to read, modify, or write the bit. Therefore, only a bit(s) which is desired to be accessed can be subjected to a control using an access control signal, resulting in a further increase in efficiency of software.

Also, when a transfer destination address or a transfer source address is set for a plurality of DMA controllers, a memory area which is used by each DMA controller is divided, and only set values of lower addresses can be simultaneously changed without changing set values of upper addresses which are first once set. Therefore, it is possible to further reduce the software process.

Further, at the stage of hardware design, a position or a polarity of a control bit which is frequently accessed may be implemented as appropriate with respect to a relationship between a mask signal for registers which are simultaneously accessed and set data for simultaneous access, thereby making it possible to expect a significant reduction in software process. For example, when a plurality of DMA controllers are implemented on hardware, the DMA controllers are designed so that some of the DMA controllers having control registers which have startup bits located at the same position and have the same polarity (e.g., control registers which are started up when the startup bits are “0”) can be simultaneously accessed, thereby making it possible to effectively reflect a change in set value by performing register access once on a plurality of control registers. Also, by assigning a bit position “0” to a startup-related register and bit positions “16 to 31” to status-related registers, control registers in different functional blocks (e.g., a startup register in a DMA controller and a startup register in an AV decoder) can be easily simultaneously controlled, thereby making it possible to expect a further reduction in the software process.

As described above, according to the present invention, when access to control registers is performed from a system control microcomputer section, predetermined bytes of a plurality of control registers can be simultaneously accessed. Therefore, the present invention is useful as a digital AV apparatus, such as a DTV (Digital Television), a DVD (Digital Versatile Disc), a DSC (Digital Still Camera), or the like.