Semiconductor device structure and manufacturing method thereof

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device including receiving a FinFET precursor including a fin structure formed between isolation regions, and a gate structure formed over a portion of the fin structure such that a sidewall of the fin structure is in contact with a gate spacer of the gate structure; patterning the fin structure to comprise a pattern of at least one upward step rising from the isolation region; forming a capping layer over the fin structure, the isolation region, and the gate structure; performing an annealing process on the FinFET precursor to form at least two dislocations along the upward step; and removing the capping layer.

BACKGROUND

A fin-like field effect transistor (FinFET) is fabricated with a thin “fin” (or fin structure) extending from a substrate. A channel of the FET is formed in this fin. A gate (or gate structure) is provided over the fin. The gate controls the channel in the fin.

To enhance a performance of the FinFET, stress is introduced into the channel regions to improve carrier mobility. Generally, a tensile stress is induced in the channel region of an n-type FinFET, and a compressive stress is induced in the channel region of a p-type FinFET.

DETAILED DESCRIPTION

A Fin Field-Effect Transistor (FinFET) with a dislocation therein and a method of forming the same are provided in accordance with various embodiments. Some intermediate operations of forming the FinFET are illustrated. Some variations of the embodiments are discussed. Throughout some various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIGS. 3, 9, and 12are some diagrammatic perspective views of a FinFET precursor100according to some embodiments of the present disclosure.FIGS. 3X, 3Y, 3Z, 4X, 4Y, 4Z, 5Y, 6Y, 7X, 7Y, 8X, 8Y, 9X, 9Y, 10X, 10Y, 11X, 11Y, 12X, 12Y, and12Z are some cross-sectional views of a FinFET precursor100according to some embodiments of the present disclosure.FIGS. 14Y, 15X, 15Y, 16X, 16Y, 17X, 17Y, 18X, 18Y, and 19Yare some cross-sectional views of a FinFET precursor100according to some other embodiments of the present disclosure. The method400and the FinFET precursor100are collectively described with reference toFIG. 3throughFIG. 12. The method401and the FinFET precursor100are collectively described with reference toFIG. 14YthroughFIG. 19Y. It is understood that additional operations can be provided before, during, and after the method400and401, and some of the operations described can be repeated, replaced or eliminated for some other embodiments of the methods.

FIG. 1illustrates a diagrammatic perspective view of a semiconductor device200. The semiconductor device200is a FinFET structure. A coordinate system with arrows pointing in three directions X, Y, and Z is illustrated. Direction X, direction Y, and direction Z are orthogonal to each other. Direction X is in a gate-length and a fin-width direction. Direction Y is in a gate-width direction. Direction Z is a direction for a top viewing. Unless specified otherwise, throughout the description, the cross-sectional views inFIGS. 3X, 4X, 5X, 6X, 7X, 8X, 9X, 10X, 11X, 12X, 15X, 16X, 17X, 18X and 19Xare obtained from a view looking in a direction X, whose figure numbers include a letter “X”. Unless specified otherwise, throughout the description, the cross-sectional views inFIGS. 3Y, 4Y, 5Y, 6Y, 7Y, 8Y, 9Y, 10Y, 11Y, 12Y, 14Y, 15Y, 16Y, 17Y, 18Y, and19Y are obtained from a view looking in a direction Y, whose figure numbers include a letter “Y”. Unless specified otherwise, throughout the description, the cross-sectional views inFIGS. 3Z, 4Z, 10Z and 12Zare obtained from a view looking in a direction Z, whose figure numbers include a letter “Z”.

InFIG. 1, semiconductor device200includes a fin structure11, an isolation region10, a gate structure14, a gate spacer15, a gate electrode layer16, a gate dielectric layer17, an interfacial layer18, some epitaxy regions13, and some dislocations12.

Isolation region10is under gate structure14, and is next to a lower portion of fin structure11.

Exemplary isolation region10utilizes an isolation technology, such as shallow trench isolation (STI), to define and electrically isolate various regions such as fin structure11. The isolation region10is composed of silicon oxide, silicon nitride, silicon oxynitride, an air gap, other suitable materials, or combinations thereof.

Fin structure11is between isolation regions10. Fin structure11is elongated to include a first longitudinal axis, which is in a same direction as direction X. A portion of fin structure11is above isolation region10. Fin structure11is continuous on either side of gate structure14. A portion111of fin structure11is covered by gate structure14and in contact with gate spacer15. In some embodiments, the portion111is a channel region of a FinFET. A lower portion of dislocation12is in fin structure11.

Fin structure11is made of any suitable material including silicon and silicon germanium. The fin structure204includes various doped regions. For example, the doped regions include a lightly doped source/drain (LDD) region (not shown) and a source/drain (S/D) region (not shown). The S/D regions are doped with a p-type dopant, an n-type dopant, and/or combinations thereof. The p-type dopants include boron or BF2; n-type dopants include phosphorus or arsenic. Doping specie is selected based on a type of device, such as an n-type FinFET device or a p-type FinFET device. The S/D regions can include various doping profiles.

Gate structure14is overlying on top of isolation region10and fin structure11. Gate structure14is elongated to include a second longitudinal axis, which is in a same direction as direction Y. Gate structure14is over the portion111of the fin structure11. Portion111is illustrated using dashed lines since portion111is inside gate structure14. A top side and sidewalls SW of portion111are in contact with gate structure14. Portion111of the fin structure11is in contact with a gate spacer15. A portion of gate structure14is in contact with epitaxy region13proximate to the portion111of the fin structure11. Gate structure14is continuous on either side of fin structure11. Some lower portions of dislocations12are in the portion111of the fin structure11and some portions of fin structure11between isolation regions10. Gate structure14includes interfacial layer18at a bottom, gate dielectric layer17on top of interfacial layer18, gate electrode layer16on top of gate dielectric layer17, and some gate spacer15at either side of gate structure14. A gate stack includes interfacial layer18, gate dielectric layer17, and gate electrode layer16.

The epitaxy region13is covering on top of fin structure11. Epitaxy region13is discontinuous on either side of gate structure14. Epitaxy region13is elongated in a same direction as direction X. A plurality of dislocations12is inside epitaxy region13. Epitaxy region13includes a surface in a polygonal shape. The surface is orthogonal to direction X. A portion of the surface is in contact with gate spacer15on either side of gate structure14.

The epitaxy region13is made of some semiconductor materials with a lattice constant different from that of the fin structure11. Dislocations12in epitaxy region13provide a tensile strain or a compressive strain in epitaxy region13and to the portion111of fin structure11. For the n-type FinFET, or an n-type metal-oxide-semiconductor (NMOS) device, adding SiC in epitaxy region13provides a tensile strain. For the p-type FinFET, or a p-type metal-oxide-semiconductor (PMOS) device, adding SiGe in epitaxy region13provides a compressive strain. In some embodiments, desired impurities are in epitaxy region13.

A plurality of dislocations12is within the epitaxy region13and within the fin structure11. Dislocation12extends continuously from the epitaxy region13to the fin structure11in the portion111and in between isolation regions10. Dislocations12at one side of the gate structure14are nearly parallel with each other. For example, most of dislocations12include a lower portion slanting towards the gate structure14in a uniform fashion. In some embodiments, spacing between each dislocation12is about the same. Dislocation12includes a plane region, resulting from a lattice mismatch in the plane region. The plane region includes a lower edge L parallel to the second longitudinal axis, which is in direction Y. Dislocations12at both sides of the gate structure14are nearly symmetrical with respect to the gate structure14.

FIG. 2Billustrates a process flow for patterning fin structure11in operation420. Operation420includes some sub operations such as operation421, operation422, operation423, and operation430. Operation421forms a photoresist20on the fin structure11. Some exemplary embodiments for operation421are illustrated inFIGS. 4X, 4Y, and 4Z. Operation422etches the fin structure11. Some exemplary embodiments for operation422are illustrated in5X and5Y. Operation423removes the photoresist20. Some exemplary embodiments for operation423are illustrated in6X and6Y. Operation430determines whether to form another upward step22. To form another upward step22, operation421through operation423are repeated. To stop forming another upward step22, operation430is followed to form a capping layer21on the FinFET precursor100.

Fin structure11includes sidewall SW in contact with gate structure14. Fin structure11is between isolation regions10. A height H1of a top portion of fin structure11is from a surface S3of isolation region10to top surface TS of the top portion of fin structure11. The top portion of fin structure11is a portion of fin structure11above surface S3. The height H1is approximately the same for fin structure11on either side of gate structure14as well as for the portion111. InFIG. 3Z, fin structure11is elongated to include a first longitudinal axis, which is in a same direction as direction X. Gate structure14is elongated to include a second longitudinal axis, which is in a same direction as direction Y. The first longitudinal axis is orthogonal to the second longitudinal axis. The portion111of fin structure11is at an intersection region of gate structure14and fin structure11. The portion111includes sidewall SW in contact with gate spacer15and the gate stack.

Isolation region10is formed by any suitable process including a photolithography process, etching a trench in a substrate (not shown) by using a dry etching and/or wet etching, and filling the trench by using a chemical vapor deposition (CVD) with one or more dielectric materials. The trenches are filled to form fin structure11between isolation regions10.

Referring toFIGS. 4Y, 4X, and 4Z, a photoresist20is formed on the fin structure11. The respective operation is shown as operation420inFIG. 2Aand operation421inFIG. 2B.

InFIG. 4Y, photoresist20is formed. Photoresist20is patterned by any suitable method in a lithography process. The lithography process can be a photolithography process includes forming a photoresist20overlying fin structure11, isolation region10, and gate structure14, exposing photoresist20to a pattern, performing a post-exposure bake process, and developing the photoresist20to form a masking element including the photoresist20. The pattern covers the top portion of fin structure11nearby gate structure14.

InFIG. 4XandFIG. 4Z, some surfaces S are exposed and not covered by the masking element. The surfaces S are symmetric with respect to gate structure14. The surface S includes a length L1in direction X. InFIG. 4Y, Surface S is on the top portion of fin structure11, a length L1is shown to indicate a length of surface S.

Etching process30is performed on fin structure11along direction Z. The top portion of fin structure11not covered by photoresist20are recessed by etching process30. The masking element is used to etch the fin structure11into a shape of upward steps22by recessing the top portion. A top edge of upward step22is illustrated using a dashed line since the top edge of upward step22is covered by photoresist20. The top portion is etched using reactive ion etching (RIE) processes and/or other suitable processes. In an example, upward steps22are formed by patterning and etching a portion of the fin structure11. Some portions of fin structure11are recessed by a distance D in direction Z to form an upward step22. Height H1minus height H2equals to distance D. First corner1C is distanced from gate spacer15by a length L2horizontally in direction X. Length L2is about a distance covered by a surface of photoresist20measured from gate spacer15.

In some embodiments, etching process30is a selective etching. The selective etching can use some fluorine-containing gas, HBr and/or Cl2 as etch gases. In some embodiments, a bias voltage used in the etching process30can be adjusted to allow better control of an etching direction to be isotropic or anisotropic. In some embodiments, an etching process30can include selective etching with slower etching rate for material in photoresist20than for materials such as silicon in fin structure11. In some embodiments, a recessing process can be performed by one or plurality of etching processes30. Different etchant can be used for etching different compositions of materials.

Referring toFIGS. 6X and 6Y, photoresist20is removed. The respective operation is shown as operation420inFIG. 2Aand operation423inFIG. 2B. Photoresist20is removed by any suitable method such as etching, etch back, or planarization. Two upward steps22are formed. Upward step22closest to a top surface of gate structure14is a top step. Upward step22closest to isolation region10is a bottom step. Upward step22is raised from surface S3of isolation region10by a level H2. The upward steps22are symmetrical on either side of gate structure14. Upward step22includes a first corner1C and a second corner2C. A height of the upward step22is measured vertically from a first corner1C to a second corner2C. A length of the upward step22is measured horizontally from a first corner1C to a second corner2C.

In some embodiments, a plurality of upward steps22is formed between the top step and the bottom step with plurality of first corners1C and second corners2C. First corner1C is concave inward. Second corner2C is convex outward at nearly a right angle. The plurality of upward steps22is formed via operation420inFIG. 2B. Performing an iteration including operation421, operation422, operation423, and operation430can form one upward step22on either side of gate structure14. The bottom step is formed in a first iteration and the top step is formed in a last iteration. For each iteration, a photoresist20in operation421is formed smaller compare to a photoresist20formed in a previous iteration to make shorter length L2for each upward step22formed consecutively. For each iteration, a distance D in operation422is etched shorter relative to a distance D etched in a previous iteration to form higher level H2for each upward step22formed consecutively.

Alternatively, in some other embodiments, the lithography process is implemented or replaced by a maskless photolithography, electron-beam writing, and ion-beam writing. In another alternative, the lithography process could implement nanoimprint technology. For using the maskless photolithography, operation421and operation423are skipped inFIG. 2B.

As an alternative to traditional photolithography, upward steps22can be formed by a double-patterning lithography (DPL) process. DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. Various DPL methodologies include double exposure (e. g., using two mask sets), forming some spacers adjacent features and removing the features to provide a pattern of the spacers, photoresist20freezing, and/or other suitable processes. It is understood that upward steps22can be formed in a similar manner.

Referring toFIGS. 7X and 7Y, a capping layer21is formed on the FinFET precursor100. The respective operation is shown as operation430inFIG. 2A.

Capping layer21is blanket covering to top of fin structure11and some portion of gate structure14. Capping layer21is overlying comformally following a contour33of upward steps22on either side of gate structure14. Contour33is illustrated using dashed line since upward step22is covered by capping layer21. Capping layer21is grown from a sidewall SW and a top portion of fin structures11. Some materials of capping layer21include silicon nitride, titanium nitride, oxynitride, oxide, SiGe, SiC, SiON, and/or combinations thereof. Capping layer21include an inherent tensile stress or compressive stress. For a FinFET precursor100to be a p-type FinFET, capping layer21includes an inherent compressive stress. Conversely, for a FinFET precursor100to be an n-type FinFET, capping layer21includes an inherent tensile stress. A formation process of capping layer21is adjusted to tune a stress to a desirable value. In some embodiments, capping layer21is a single layer. In other embodiments, capping layer21is a plurality of sub layers. Some formation methods include atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), or the like. The capping layer21including a silicon nitride is formed by a low pressure CVD (LPCVD). The capping layer21including a silicon nitride is formed by plasma enhanced CVD (PECVD). The capping layer21including a tetraethyl orthosilicate is formed by a CVD process. The capping layer21including a silicon oxide is formed by a high aspect ratio process (HARP).

Referring toFIGS. 8Y and 8X, a pre-amorphization implantation (PAI)31is performed on the FinFET precursor100. The respective operation is shown as operation440inFIG. 2A. In some embodiments, the PAI31is performed using germanium, silicon, or the like. A dosage and a temperature of the PAI31process are controlled for various design purposes. In some embodiments, the PAI31is performed at a low implantation temperature or at room temperatures. The FinFET precursor100undergoes the PAI31. The PAI31injects some doping species into fin structures11and disrupts a semiconductor lattice therein. By introducing some doping species such as Si, Ge, Ar, Xe, BF2, As, and/or In into fin structures11, a molecular lattice of fin structure11is damaged. This creates an amorphous region (not shown) within the semiconductor material of capping layer21and fin structure11. The amorphous region includes amorphous silicon, and some polysilicon grains. Portions111are illustrated using dash lines since they are behind capping layer21inFIGS. 7X and 8X. The portion111of fin structure11under gate structure14is protected from the PAI31, and remains to have a crystalline structure. In some embodiments, fin structure11undergoes multiple implantations utilizing a variety of energies, doping species, angles and dosages. In some embodiments, a patterned photoresist layer (not shown) is used to define the amorphous region and to protect other regions of the FinFET precursor100from implantation damage. For example, the patterned photoresist layer exposes the fin structures11to the PAI31while gate structure14is protected from the PAI31. In some embodiments, a patterned hard mask layer, such as a SiN or SiON layer is used to define the amorphous region.

In some embodiments, operation440is skipped such that a thermal anneal is performed on the FinFET precursor100after a formation of capping layer21. InFIG. 2Athe operation450performs the thermal anneal on the FinFET precursor100. The thermal anneal is performed to form defects in the amorphized regions. The thermal anneal is performed using a Rapid Thermal Anneal (RTA), laser anneal, or other anneal methods. In some embodiment, the thermal anneal is performed using a spike RTA. The thermal anneal can include a long range pre-heat.

As a result of the thermal anneal, fin structure11is recrystallized with a memorized stress obtained from capping layer21. The capping layer21is removed by any suitable process including a wet etching or a dry etching process. In one example, capping layer21composed of a silicon nitride is removed by an etching operation involving phosphoric acid. In another example, capping layer21composed of a silicon oxide is removed by an etching operation involving a hydrofluoric acid (HP) or a buffered HF. In another example, capping layer21is removed by a Chemical-Mechanical Planarization (CMP) process. The capping layer21is removed, yet fin structures11retain a stress effect. Retaining the stress effect is through operation430,440, and450, and is referred to as a stress-memorization technique (SMT).

Referring toFIGS. 9, 9Y and 9X, dislocations12are formed. Dislocation12is formed proximate to first corner1C and second corner2C. Dislocations12are formed at either side of gate structure14such that the dislocations12are nearly symmetric on either side of the gate structure14. At one side of the gate structure14, dislocations12are nearly parallel. The lower portions of dislocations12are slanting towards the gate structure14in a uniform fashion. Dislocation12includes a plane region, resulting from a lattice mismatch near the plane region. Some re-crystallized region contains some irregularities near dislocation12. For example, a locally uniform region above the plane region is misaligning with other regions below the plane region. This form of misalignment results in dislocations12. The plane region includes a lower edge L parallel to direction Y. The lower portion of dislocation12and the lower edge L are in a lower portion of fin structure11. A total number of dislocations12in FinFET precursor100is approximately a total number of first corners1C plus a total number of second corners2C. A plurality of dislocations12is within fin structure11. Dislocation12extends continuously from first corner1C and second corner2C to the portion111and in between isolation regions10. In some embodiments, at one side of gate structure14, spacing between each dislocation12is about the same. InFIG. 9X, dislocation12includes a plane region.FIG. 9illustrates a diagrammatic perspective view of a FinFET precursor100with two upward steps22and some dislocations12formed therein.

Referring toFIGS. 10Y, 10X, and 10Z, some top portions of the fin structures11are removed. The respective operation is shown as operation460inFIG. 2A.

A photoresist20is covered on top of gate structure14. Etching process30recesses the top portions of the fin structure11. The portion111of fin structure11is remained and protected by gate structure14. Removing the top portions of the fin structure11by a lithography process including forming a photoresist20over the FinFET precursor100, patterning the photoresist20to have some openings that expose the fin structure11at either side of gate structure14, and etching the fin structure11. Forming the photoresist20involves photoresist coating (e.g., spin-on coating), soft baking, mask aligning. Patterning the photoresist20involves exposure, post-exposure baking, developing a photoresist layer, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof.

The etching process30is a dry etching process. The dry etching process can be implemented in an etching chamber. The dry etching process can implement an oxygen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), bromine-containing gas (e.g., HBr, He and/or CHBR3), iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. In some embodiments, the dry etching process utilizes an O2 plasma treatment and/or an O2/N2 plasma treatment. Further, the dry etching process can be performed for a suitable duration. Some process parameters such as etching durations and/or etch rate are adjustable to control how much material is removed from fin structure11.

Alternatively, in some other embodiments, the etching process30is a wet etching process, or a combination of a dry and wet etching process. Some process parameters such as a concentration of some acid bath, a temperature of a chemical bath, an agitation of a solution bath, and/or the etching duration are adjustable to control how much the top portion is removed from fin structure11.

Alternatively, the lithography process is implemented or replaced by other methods, such as maskless photolithography, electron-beam writing, and ion-beam writing. In another alternative, the lithography process could implement nanoimprint technology.

Referring toFIGS. 11Y and 11X, some remaining portions of fin structure11is left. A remaining portion of fin structure11has a surface S2. The surface S2of the remaining portions is higher than a surface S3of the isolation region10. With the top portion of fin structure11removed, the portion111is exposed inFIG. 11X. The dry etching process can be a physical etch for an anisotropic etch to obtain the portion111with substantially vertical sides facing direction X.

A lower portion of the plurality of dislocations12is within the remaining portion of fin structure11. Dislocation12is left in the fin structure11in the portion111and in between isolation regions10. Dislocation12is shortened by the etching process30inFIG. 10X. Level of surface S2is determined by some process parameters in etching process30. Surface S2can be above a surface S3of isolation region10, at a same level with surface S3, or below surface S3. Surface S2and surface S3are substantially flat.

Referring toFIGS. 12, 12Y, 12X, and 12Z, some epitaxy regions13are formed on surface S2, on top of the remaining portion of fin structures11. The respective operation is shown as operation470inFIG. 2A.

Epitaxy region13is formed by one or more epitaxy or epitaxial (epi) processes, such that Si features, SiGe features, and/or other suitable features are formed in a crystalline state on the remaining portion of fin structures11. The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (V PE), ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process uses gaseous and/or liquid precursors, which interact with a composition of fin structure11. Thus, dislocation12is growing from the portion111into epitaxy region13. In some embodiments, epitaxy region13is in-situ doped. Some doping species include p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. In some embodiments, epitaxy region13is not in-situ doped. Dislocation12caused by the stress-memory technique SMT propagates to epitaxy region13. Epitaxy region13possesses the stress effects caused by dislocations12.

A plurality of dislocations12is within the epitaxy region13and within the fin structure11. Dislocation12from the remaining portion of fin structure11and in the portion111forms continuously to the epitaxy region13as epitaxy region13grows on top of the fin structure11. InFIG. 12X, epitaxy region13grows to form a surface in a polygonal shape. A plane covered by dislocation12is within the surface.

FIG. 13illustrates a process flow for forming semiconductor device200from FinFET precursor100. Operation410receives a FinFET precursor100. Operation421removes a top portion of a fin structure11. Operation431grows a semiconductive layer19on top of a remaining portion of the fin structure11. Operation441forming a capping layer21on the semiconductive layer19. Operation451performs a thermal anneal on the semiconductive layer19. Operation461forms some epitaxy regions13on top of a remaining portion of the fin structure11.

Referring toFIG. 14Y, removing a top portion of a fin structure11is performed. The respective operation is shown as operation421inFIG. 13.

Removing the top portion is performed by any suitable process such as etching process30. Photoresist20is covering gate structure14with fin structure11exposed to etching. In one example, a layer of photoresist20is formed over gate structure14by a suitable process, such as spin-on coating, and patterned to form a photoresist feature by a proper photolithography patterning method. A pattern on the photoresist20can then be transferred by an etching process30to underlying fin structure11.

Referring toFIGS. 15Y and 15X, the top portion of a fin structure11is removed. The photoresist20is stripped thereafter. A remaining portion of fin structure11includes a lower portion between isolation region10and the portion111of fin structure11. The lower portion includes a surface S4at a top. Surface S4can be above surface S3of isolation10, at a same level with surface S3, or below surface S3.

Referring toFIGS. 16Y and 16X, growing a semiconductive layer19on top of surface S4on the fin structure11is performed. The respective operation is shown as operation431inFIG. 13.

Semiconductive layer19is overlying on top of the remaining portion of fin structure11to form a horizontal portion of semiconductive layer19with a thickness TH2. A portion of a layer of semiconductive layer19is lining to the portion111to form a vertical portion of semiconductive layer19with a thickness TH1. A plurality of corners is formed along the horizontal portion and vertical portion of semiconductive layer19over fin structure11. A first corner1C is located at a junction of the horizontal portion and the vertical portion of semiconductive layer19. A second corner2C is located proximate to a top of the vertical portion of semiconductive layer19. The vertical portion of semiconductive layer19is lower than portion111as illustrated in16X.

Growing semiconductive layer19is by any suitable method such as some epitaxial growth. Some epitaxial growth including some processes such as vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), Liquid Phase Epitaxy (LPE), and/or molecular-beam epitaxy (MBE). Some gas sources for some epitaxy reaction are a hydrogen reduction of silicon tetrachloride, silane, dichlorosilane, or tricholorsilane. Thicknesses TH1and TH2of semiconductive layer19are controlled by duration of the epitaxial growth.

Other epitaxial growth includes some processes such as solid-phase epitaxy (SPE) or selective epitaxy growth (SEG). The SPE process converts an amorphous region of semiconductor material to crystalline structure to form semiconductive layer19. The semiconductive layer19includes silicon. The selective epitaxy growth (SEG) process involves growth and etch co-exist. In different epitaxy stages of SEG, some growth rates are greater than or smaller than some etching rates, and hence a corresponding net effect is growth or etching, respectively. SEG is performed using low pressure chemical vapor deposition (LPCVD) in a chamber.

The thicknesses TH1and TH2of semiconductive layer19are adjustable by controlling some etch to growth ratios throughout SEG process. Some process conditions including a type of process gases and a flow rate for a growth/etching process. The flow rate of the process gas is adjusted to control thicknesses TH1and TH2of semiconductive layer19.

The LPCVD includes exposing surface S4to a high vacuum. A gaseous flux including the process gas is directed onto surface S4to deposit the process gas on the surface S4. The process gas is deposited with coverage of at least approximately one monolayer. In some embodiments, a material, such as Si, deposited on surface S4is same with a material in fin structure11to form a homoepitaxy structure.

Liquid Phase Epitaxy (LPE) involves a precipitation of a crystalline film from a supersaturated melt on to surface S4. A temperature is increased until a phase transition occurs and then reduced for precipitation. By controlling some cooling rates, a rate of growth for semiconductive layer19is controlled. The cooling rates can be continuous or in a discrete increment level.

In some other embodiments, the epitaxial growth involves depositing a layer of some crystallizable elemental materials of semiconductive layer19on a lattice-mismatched target of surface S4to produce a multi-atomic-layer on fin structures11. Defects arise in some efforts to epitaxially grow one kind of crystalline material in semiconductive layer19on a different kind of material in fin structure11. A crystalline lattice size of a material in semiconductive layer19can be different from that of a material in fin structure11. This lattice mismatch between a starting fin structure11and subsequent layer(s) of semiconductive layer19creates stress during material deposition that generates defects in semiconductive layer19.

The capping layer is blanket formed on top of semiconductive layer19and some portions of gate structure14. The capping layer is overlying comformally following a contour of semiconductive layer19and of gate structure14. Some materials of the capping layer include silicon nitride, titanium nitride, oxynitride, oxide, SiGe, SiC, SiON, and/or combinations thereof. The capping layer includes an inherent tensile stress or compressive stress. For a FinFET precursor100to be a p-type FinFET, the capping layer includes an inherent compressive stress. Conversely, for a FinFET precursor100to be an n-type FinFET, the capping layer includes an inherent tensile stress. A formation process of the capping layer is adjusted to tune a stress to a desirable value. The formation process is any suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), or the like. The capping layer including a silicon nitride is formed by a low pressure CVD (LPCVD), a silicon nitride is formed by plasma enhanced CVD (PECVD), a tetraethyl orthosilicate is formed by a CVD process, a silicon oxide is formed by a high aspect ratio process (HARP).

In some embodiments, the PAI (not shown) is performed on the FinFET precursor100to create an amorphous region (not shown) within the capping layer and semiconductive layer19. The amorphous region includes amorphous silicon, and some polysilicon grains. The portion111of fin structure11under gate structures14is protected from the PAI, and remains to have a crystalline structure. Portion111is illustrated inFIG. 16Xsince the top portion of fin structure11is removed.

In some embodiments, the PAI process is skipped such that a thermal anneal is performed on the FinFET precursor100after forming of the capping layer as illustrated in operation441to operation451inFIG. 13. InFIG. 13the operation451performs the thermal anneal on the FinFET precursor100. The thermal anneal is performed to form dislocation12near first corner1C and second corner2C. The thermal anneal is performed using Rapid Thermal Anneal (RTA), laser anneal, or other anneal methods. In some embodiment, the thermal anneal is performed using spike RTA. The thermal anneal can include a long range pre-heat.

As a result of the thermal anneal, semiconductive layer19is recrystallized with a memorized stress obtained from the capping layer. The capping layer is removed by any suitable process including a wet etching or a dry etching process. In another example, the capping layer is removed by a CMP process. The capping layer is removed with fin structures11retaining a stress effect. Retaining the stress effect is through operation431,441, and451inFIG. 13.

InFIGS. 17Y and 17X, dislocation12extends from the first corner1C and the second corner2C downward towards gate structure14. Dislocation12reaches the portion111and the remaining portion of fin structure11below surface S3of isolation region10.

Removing the capping layer after dislocation12is formed. Dislocations12are formed within semiconductive layer19proximate to the first corner1C and the second corner2C. Dislocations12are nearly symmetrical on either side of the gate structure14. Semiconductive layer19is removed with dislocation12remained in the portion111and the remaining portion of fin structure11below surface S3of isolation region10. Semiconductive layer19is removed by any suitable process including the lithography process and the etching process.

InFIGS. 18Y and 18X, some remaining portions of fin structure11are left. A surface S4of the remaining portion can be above a surface S3of isolation region10, at a same level with surface S3, or below surface S3. Surface S4and surface S3are substantially flat. The portion111is exposed inFIG. 18X.

A lower edge L of dislocations12are under surface S4of the remaining portion of fin structure11. Dislocation12is left in the fin structure11in the portion111. Dislocation12is shortened by the etching process as a plane formed by dislocation12is reduced in size. A level of surface S4is determined by some process parameters in the etching process. Surface S4can be above a surface S3of isolation region10, at a same level with surface S3, or below surface S3. Surface S4and surface S3are substantially flat.

A lower portion of dislocation12remains in fin structure11. The lower portion is in a plane form and includes a lower edge L. The lower edge L is parallel to the second longitudinal axis, which is in direction Y. Dislocations12at both sides of the gate structure14are nearly symmetrical with respect to the gate structure14. In some embodiments, a portion of semiconductive layer19is removed with a remaining portion (not shown) of semiconductive layer19on top of fin structure11.

InFIGS. 19Y, 19X and 19, epitaxy region13is grown on top of the remaining portion of fin structure11and continues dislocation12into epitaxy region13. Dislocation12formed inside epitaxy region13is parallel with dislocation12within fin structure11.

Growing epitaxy region13is by any suitable method such as some epitaxy processes. The epitaxy process includes a process such as chemical vapor deposition CVD deposition techniques (e.g., vapor-phase epitaxy (VPE), metalorganic chemical vapor deposition CVD (MOCVD), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular-beam epitaxy (MBE), solid-phase epitaxy (SPE), liquid-phase epitaxy (LPE), selective epitaxy growth (SEG), and/or other suitable processes. The epitaxy process uses a process gas and/or liquid, which interacts with a composition of fin structure11. Dislocation12is replicated from fin structure11into epitaxy region13. In some embodiments, epitaxy region13is in-situ doped. Some doping species include p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. In some other embodiments, epitaxy region13is not in-situ doped.

The SPE process converts an amorphous region of a semiconductor material to crystalline structure to form epitaxy region13. The SEG process involves growth and etch co-exist. SEG is performed using low pressure chemical vapor deposition (LPCVD) in a chamber. The LPCVD includes exposing surface S4to a high vacuum. A gaseous flux including the process gas is directed onto surface S4to deposit the process gas on the surface S4.

A crystalline lattice size of a material in epitaxy layer13can be different from that a material in fin structure11. This lattice mismatch between a starting fin structure11and subsequent layer(s) of epitaxy layer13creates stress during material deposition that propagates defects at dislocation12from fin structure11to epitaxy layer13.

In efforts to epitaxially grow one kind of crystalline material on a surface of a different kind of material with dislocation12, different crystalline lattice sizes of the two materials results to a lattice mismatch proximate to dislocation12. This lattice mismatch between a starting surface such as surface S4, and subsequent layer such as epitaxy layer13, creates stress during material deposition that replicates dislocation12into epitaxy layer13.

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device including receiving a FinFET precursor including a fin structure formed between isolation regions, and a gate structure formed over a portion of the fin structure such that a sidewall of the fin structure is in contact with a gate spacer of the gate structure; patterning the fin structure to comprise at least one upward step rising from the isolation region; forming a capping layer over the fin structure, the isolation region, and the gate structure; performing an annealing process on the FinFET precursor to form at least two dislocations along the upward step; and removing the capping layer.

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device including receiving a FinFET precursor including a fin structure formed between some isolation regions, and a gate structure formed over a portion of the fin structure; removing a top portion of the fin structure on either side of the gate structure; growing a semiconductive layer on top of a remaining portion of the fin structure such that a plurality of corners is formed over the fin structure; forming a capping layer over the semiconductive layer; performing an annealing process on the FinFET precursor to form a plurality of dislocations proximate to the corners; and removing the capping layer.

Some embodiments of the present disclosure provide a semiconductor device including a fin structure between isolation regions. The fin structure includes a first longitudinal axis. A gate structure over a portion of the fin structure. The portion of the fin structure is in contact with a gate spacer. At least one epitaxy region disposed on top of the fin structure and in contact with the gate structure. A plurality of dislocations is formed within the epitaxy region and within the fin structure.