Semiconductor device and control method thereof for processing

According to an embodiment, a reconfigurable device 1 includes a configuration information storage memory 12, a state transition management unit 11, and a data path unit 13. When a failure is not detected in either of tiles T1 and T2 provided in the data path unit 13, the state transition management unit 11 selects the configuration information item so that a first processing circuit is configured using the tiles T1 and T2, while when a failure is detected in the tile T2, the state transition management unit 11 selects the configuration information item so that after a first intermediate processing circuit is configured using the tile T1 in which no failure is detected, a second intermediate processing circuit is configured again using the tile T1 in order to achieve the first processing circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese patent application No. 2015-123432, filed on Jun. 19, 2015, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The present invention relates to a semiconductor device and a control method thereof, and to, for example, a semiconductor device and a control method thereof that are suitable for executing desired processing without skipping low-priority processing.

Published Japanese Translation of PCT International Publication for Patent Application, No. 2009-542098 discloses an element controller for a resilient integrated circuit architecture. This integrated circuit includes a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element includes a selected circuit element which may vary by element interface and element type, and which may be configurable. The state machine element assigns various functions based on an element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element reassigns the first configuration to another composite circuit element and creates a second data link for continuing the same functioning. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the integrated circuit to continue the same functioning despite defects which may arise during operation.

SUMMARY

However, with the configuration disclosed in Published Japanese Translation of PCT International Publication for Patent Application, No. 2009-542098, when a failure is detected in any one of the composite circuit elements, although high priority processing can be executed using other composite circuit elements in which no failure is detected, low-priority processing needs to be excluded. Therefore, the present inventor has found a problem that with the configuration disclosed in Published Japanese Translation of PCT International Publication for Patent Application, No. 2009-542098, desired processing cannot be executed. Other problems of the related art and new features of the present invention will become apparent from the following descriptions of the specification and attached drawings.

In an aspect of the present invention, in a semiconductor device, when a failure is not detected in any one of a plurality of logic circuit groups provided in a data path unit, a state transition management unit selects a configuration information item so that a first processing circuit is configured using some or all of the plurality of logic circuit groups, and when a failure is detected in any one of the plurality of logic circuit groups, the state transition management unit selects the configuration information item so that a first intermediate processing circuit is configured using some or all of logical circuit groups in which no failure is detected from among the plurality of logic circuit groups, and then a second intermediate processing circuit is configured using some or all of the logical circuit groups in which no failure is detected from among the plurality of logic circuit groups, in order to achieve the first processing circuit.

In another aspect of the present invention, in a semiconductor device, when a failure is not detected in any one of a plurality of logic circuits provided in a data path unit, a state transition management unit selects a configuration information item so that a first processing circuit is configured using some of the plurality of logic circuits, and when a failure is detected in any one of the plurality of logic circuit, the state transition management unit selects the configuration information item so that a plurality of the first processing circuits are configured using some or all of the plurality of logical circuits, and a result of processing by the first processing circuit is determined according to results of processing by the plurality of respective first processing circuits.

In another aspect of the present invention, a control method of a semiconductor device includes: selecting, when a failure is not detected in any one of a plurality of logic circuit groups provided in the data path unit, a configuration information item so that a first processing circuit is configured using some or all of the plurality of logic circuit groups; and selecting, when a failure is detected in any one of the plurality of logic circuit groups, the configuration information item so that a first intermediate processing circuit is configured using some or all of logic circuit groups in which no failure is detected from among the plurality of logic circuit groups, and then a second intermediate processing circuit is configured using some or all of the logic circuit groups in which no failure is detected from among the plurality of logic circuit groups, in order to achieve the first processing circuit.

In another aspect of the present invention, a control method of a semiconductor device includes: selecting, when a failure is not detected in any one of a plurality of logic circuits provided in a data path unit, a configuration information item so that a first processing circuit is configured using some of the plurality of logic circuits; selecting, when a failure is detected in any one of the plurality of logic circuits, the configuration information item so that a plurality of the first processing circuits are configured using some or all of the plurality of logic circuits; and determining a result of processing by the first processing circuit according to results of processing by the plurality of respective first processing circuits.

According to the above aspects, it is possible to provide a semiconductor device and a control method thereof that can execute desired processing without skipping low-priority processing even when a failure is detected.

DETAILED DESCRIPTION

Hereinafter, embodiments will be described with reference to the drawings. The drawings are in a simplified form, and the technical scope of the embodiments should not be interpreted to be limited to the drawings. The same elements are denoted by the same reference signs, and repeated descriptions are omitted.

The invention will be described by dividing it into a plurality of sections or embodiments whenever circumstances require it for convenience in the following embodiments. However, unless otherwise particularly specified, these sections or embodiments are not irrelevant to one another. One section or embodiment is related to modifications, applications, details, supplementary explanations, and the like of some or all of the other ones. When reference is made to the number of elements or the like (including the number of pieces, numerical values, quantity, range, etc.) in the following embodiments, the number thereof is not limited to a specific number and may be greater than or less than or equal to the specific number unless otherwise particularly specified and definitely limited to the specific number in principle.

Further, in the following embodiments, components (including operation steps, etc.) are not always essential unless otherwise particularly specified and considered to be definitely essential in principle. Similarly, when reference is made to the shapes, positional relations, and the like of the components or the like in the following embodiments, they will include ones, for example, substantially approximate or similar in their shapes or the like unless otherwise particularly specified and considered not to be definitely so in principle. This is similarly applied even to the above-described number or the like (including the number of pieces, numerical values, quantity, range, etc.).

First Embodiment

FIG. 1is a block diagram showing a configuration example of a reconfigurable device (a semiconductor device)1according to a first embodiment. In the reconfigurable device1according to this embodiment, when a failure is detected in any one of a plurality of logic circuit groups provided in a dynamically reconfigurable data path unit, a first intermediate processing circuit is configured using a logic circuit group in which no failure is detected, and then a second intermediate processing circuit is configured again using the logic circuit group in which no failure is detected, in order to achieve a desired first processing circuit. Thus, the reconfigurable device1according to this embodiment can execute desired processing without skipping low-priority processing even when a failure is detected. Hereinafter, the reconfigurable device1will be described in detail.

As shown inFIG. 1, the reconfigurable device1includes a state transition management unit11, a configuration information storage memory12, and a data path unit13. Further, an error path16and an event path17are provided between the data path unit13and the state transition management unit11. An address path14is provided between the state transition management unit11and the configuration information storage memory12. A configuration information path15is provided between the configuration information storage memory12and the data path unit13.

The data path unit13is a data processing unit that can dynamically reconfigure a circuit(s) according to a configuration information item(s) supplied from outside, performs processing using the reconfigured circuit on input data Din, and outputs obtained output data Dout.

Further, the data path unit13activates a process completion signal (e.g., switches the process completion signal from an L level to an H level) when the process is completed, and activates a failure detection signal (e.g., switches the failure detection signal from an L level to an H level) when a failure is detected. Note that a failure in the data path unit13may be detected by performing a test such as a scan test or may be detected in real time by a parity bit or the like.

The process completion signal output from the data path unit13is supplied to the state transition management unit11through the event path17. The failure detection signal output from the data path unit13is supplied to the state transition management unit11through the error path16.

The state transition management unit11selects a configuration information item to be output to the data path unit13from among a plurality of configuration information items stored in the configuration information storage memory12. For example, the state transition management unit11selects any one of the configuration information items stored in the configuration information storage memory12according to the process completion signal and the failure detection signal from the data path unit13.

More specifically, the state transition management unit11outputs an address signal corresponding to the process completion signal and the failure detection signal from the data path unit13. This address signal is supplied to the configuration information storage memory12through the address path14. The configuration information item stored in a storage region at an address specified by the address signal is read out from the configuration information storage memory12.

Note that the configuration information storage memory12stores at least one or a plurality of configuration information items that are selected when a failure is not detected in the data path unit13(hereinafter referred to as a normal mode) and a plurality of configuration information items that are selected when a failure is detected in the data path unit13(hereinafter referred to as a safe mode).

The configuration information item read out from the configuration information storage memory12(i.e., the configuration information item selected by the state transition management unit11) is supplied to the data path unit13through the configuration information path15. Next, the data path unit13dynamically reconfigures a circuit according to the configuration information item supplied from the configuration information storage memory12, performs processing on the input data Din using the reconfigured circuit, and outputs the obtained output data Dout.

(Specific Configuration Example of the Data Path Unit13)

FIG. 2is a block diagram showing a reconfigurable device1awhich is a specific configuration example of the reconfigurable device1. InFIG. 2, a specific configuration example of the data path unit13is a data path unit13a.

As shown inFIG. 2, the data path unit13aincludes tiles T1to Tn (n is an integer greater than or equal to two) and selectors SEL1to SELn.

Each of the tiles T1to Tn includes a logic circuit group.

Referring toFIG. 3, each of the tiles T1to Tn includes, for example, an operator131, a memory132, a register133, and a wire connection circuit134, and processing performed by the operator131, wire connection performed by the wire connection circuit134, data initial values and the like are determined according to the configuration information items from outside. Note that a configuration of each of the tiles T1to Tn is not limited to a configuration including all of the operator131, the memory132, the register133, and the wire connection circuit134, and a configuration including some of them or a configuration including a plurality of sets of some or all of them may be incorporated.

The tile T1performs the processing on the input data Din and output obtained data. The tiles T2to Tn perform the processing on outputs of selectors SEL1to SEL(n−1), respectively, and outputs obtained data. The tiles T1to Tn activate process completion signals EVF1to EVFn, respectively, when they complete processing, and activate failure detection signals ERF1to ERFn when a failure is detected.

The process completion signals EVF1to EVFn that are output from the tiles T1to Tn are supplied to the state transition management unit11through event paths171to17n, respectively, that constitute the event path17. Moreover, the failure detection signals ERF1to ERFn output from the tiles T1to Tn are supplied to the state transition management unit11through error paths161to16n, respectively, that constitute the error path16.

Each of the selectors SEL1to SELn selects any one of all outputs of the tiles in the previous stage(s) and the input data Din according to the configuration information item from outside. More specifically, the selector SELi (i is any one of 1 to n) selects and outputs any one of the output(s) of the tiles T1to Ti (when i=1, only the output of the tile T1) in the previous stage(s) and the input data Din according to the configuration information item from outside. The output of the selector SELn is output outside as the output data Dout of the data path unit13a.

FIG. 4is a block diagram showing a reconfigurable device1bwhich is the reconfigurable device1ahaving two tiles (n=2).

As shown inFIG. 4, the reconfigurable device1bincludes a configuration information storage memory12bas the configuration information storage memory12and a data path unit13bas the data path unit13.

In the configuration information storage memory12b, for example, a configuration information item in the normal mode is stored in a storage region at an address0, configuration information items of pre-processing and post-processing in a first safe mode are stored in storage regions at addresses1and2, respectively, and configuration information items of pre-processing and post-processing in a second safe mode are stored in storage regions at addresses3and4, respectively.

FIG. 5is a flowchart showing an operation of the reconfigurable device1b.

In an example ofFIG. 5, the reconfigurable device1bperforms the pre-processing on the input data Din (step S101), performs the post-processing on the input data Din (step S102), and then consequently, executes desired processing on the input data Din (step S100).

FIG. 6is a state transition diagram of the reconfigurable device1b. Details of the state transition diagram will be described later together with a description of an operation of the reconfigurable device1b.

(Operation in Normal Mode)

Firstly, an operation in the normal mode of the reconfigurable device1bwill be described.FIG. 7is a block diagram for explaining the operation in the normal mode of the reconfigurable device1b.

As shown inFIG. 7, when no failure is detected in the data path unit13b, that is, when both of the failure detection signals ERF1and ERF2output from the tiles T1and T2are inactive, the state transition management unit11outputs the address signal indicating an address0(ST10inFIG. 6). Next, the configuration information item stored in the storage region at the address0is read out from the configuration information storage memory12band then supplied to the data path unit13b. Thus, a first intermediate processing circuit that executes the pre-processing is configured by the tile T1, and a second intermediate processing circuit that executes the post-processing is configured by the tile T2. Moreover, the selector SEL1is configured to select and output an output result of the tile T1, and the selector SEL2is configured to select and output an output result of the tile T2. As a result, in the data path unit13b, processing can be executed by a desired processing circuit.

In this state, the input data Din is supplied to the data path unit13b. The first intermediate processing circuit configured using the tile T1performs the pre-processing on the input data Din. After that, the second intermediate processing circuit configured using the tile T2performs the post-processing on the output result of the tile T1. Then, the output result of the tile T2is output outside as the output data Dout of the data path unit13b. In this way, in the data path unit13b, a process is executed by a desired processing circuit.

FIG. 8is a timing chart showing an operation in the normal mode of the reconfigurable device1b. Referring toFIG. 8, after the pre-processing and the post-processing are performed on the input data Din in a certain cycle, the processing result is output as the output data Dout in the next cycle. That is, the pre-processing and the post-processing are executed in a total of one cycle. Note that in an example ofFIG. 8, the input data Din in each cycle is distinguished and represented by input data inA to inH, and output data Dout corresponding to the input data inA to inH is distinguished and represented by output data outA to outH.

(Operation in First Safe Mode)

Next, an operation in a first safe mode of the reconfigurable device1bwill be described.FIGS. 9 and 10are block diagrams for explaining an operation in the first safe mode of the reconfigurable device1b.

As shown inFIG. 9, when a failure is detected in the tile T2that is provided in the data path unit13b, that is, when the failure detection signal ERF2output from the tile T2becomes active, firstly the state transition management unit11outputs the address signal indicating an address1(ST11inFIG. 6). Next, the configuration information item stored in the storage region at the address1is read out from the configuration information storage memory12band then supplied to the data path unit13b. Thus, the first intermediate processing circuit that executes the pre-processing is configured by the tile T1.

In this state, the input data Din is supplied to the data path unit13b. The first intermediate processing circuit configured using the tile T1performs the pre-processing on the input data Din, and when the pre-processing is completed, the first intermediate processing circuit switches the process completion signal EVF1from inactive to active.

As shown inFIG. 10, when the process completion signal EVF1becomes active, the state transition management unit11switches the address signal to indicate an address2from the address signal that indicates the address1and then outputs the switched address signal (ST12inFIG. 6). Next, the configuration information item stored in the storage region at the address2is read out from the configuration information storage memory12band then supplied to the data path unit13b. Thus, the second intermediate processing circuit that executes the post-processing is configured by the tile T1. At this time, the selector SEL2is configured to select and output the output result of the tile T1.

In this state, a result of the pre-processing by the tile T1is supplied to the second intermediate processing circuit configured using the tile T1. Note that in an example ofFIG. 10, a feedback path is not shown. The second intermediate processing circuit configured using the tile T1performs the post-processing on a result of the pre-processing. Then, the output result of the tile T1is output outside as the output data Dout of the data path unit13b. As a result, in the data path unit13b, a process is executed by a desired processing circuit.

FIG. 11is a timing chart showing an operation in the first safe mode of the reconfigurable device1b. Referring toFIG. 11, the pre-processing is performed on the input data Din in a certain cycle, the post-processing is performed on the input data Din in the next cycle, and then the input data Din is output as the output data Dout in the next cycle. That is, the pre-processing and the post-processing are executed in a total of two cycles. Note that in an example ofFIG. 11, the input data Din in each cycle is distinguished and represented by input data inA to inD, and output data Dout corresponding to the input data inA to inD is distinguished and represented by output data outA to outD.

As described above, even when a failure is detected in the tile T2of the data path unit13b, the reconfigurable device1bexecutes the pre-processing and the post-processing in a time-sharing manner using the tile T1in which no failure is detected, so that a process can be executed by a desired processing circuit without skipping low-priority processing.

(Operation in Second Safe Mode)

Next, an operation in the second safe mode of the reconfigurable device1bwill be described.FIGS. 12 and 13are block diagrams for explaining an operation in the second safe mode of the reconfigurable device1b.

As shown inFIG. 12, when a failure is detected in the tile T1provided in the data path unit13b, that is, when the failure detection signal ERF1output from the tile T1becomes active, firstly the state transition management unit11outputs the address signal indicating an address3(ST13inFIG. 6). Next, the configuration information item stored in the storage region at the address3is read out from the configuration information storage memory12band then supplied to the data path unit13b. Thus, the first intermediate processing circuit that executes the pre-processing is configured by the tile T2. At this time, the selector SEL1is configured to select and output the input data Din.

In this state, the input data Din is supplied to the data path unit13b. The first intermediate processing circuit configured using the tile T2performs the pre-processing on the input data Din, and when the pre-processing is completed, the first intermediate processing circuit switches the process completion signal EVF2from inactive to active.

As shown inFIG. 13, when the process completion signal EVF2becomes active, the state transition management unit11switches the address signal to indicate an address4from the address signal that indicates the address3and then outputs the switched address signal (ST14inFIG. 6). Next, the configuration information item stored in the storage region at the address4is read out from the configuration information storage memory12band then supplied to the data path unit13b. At this time, the selector SEL2is configured to select and output an output result of the tile T2.

In this state, a result of the pre-processing by the tile T2is supplied to the second intermediate processing circuit configured using the tile T2. Note that in an example ofFIG. 13, a feedback path is not shown. The second intermediate processing circuit configured using the tile T2performs the post-processing on the result of the pre-processing. Then, an output result of the tile T2is output outside as the output data Dout of the data path unit13b. As a result, in the data path unit13b, a process is executed by a desired processing circuit.

As a timing chart showing an operation in the second safe mode of the reconfigurable device1bis basically the same as the timing chart showing the operation in the first safe mode of the reconfigurable device1b, a description of the timing chart showing the operation in the second safe mode of the reconfigurable1bwill be omitted.

As described above, even when a failure is detected in the tile T1of the data path unit13b, the reconfigurable device1bexecutes the pre-processing and the post-processing in a time-sharing manner using the tile T2in which no failure is detected, so that a process can be executed by a desired processing circuit without skipping low-priority processing.

(Operation of the Reconfigurable Device1aHaving Three Tiles)

FIG. 14is a block diagram showing a reconfigurable device1cwhich is the reconfigurable device1ahaving three tiles (n=3).

As shown inFIG. 14, the reconfigurable device1cincludes a configuration information storage memory12cas the configuration information storage memory12and a data path unit13cas the data path unit13.

In the configuration information storage memory12c, for example, a configuration information item in the normal mode is stored in a storage region at an address0, and configuration information items in the safe mode of the first to third processing are stored in storage regions at addresses1to3, respectively.

(Operation in Normal Mode)

An operation in the normal mode of the reconfigurable device1cwill be described first.FIG. 15is a block diagram for explaining the operation in the normal mode of the reconfigurable device1c.

As shown inFIG. 15, when no failure is detected in the data path unit13c, that is, when the failure detection signals ERF1to ERF3output from the tiles T1to T3, respectively, are all inactive, the state transition management unit11outputs the address signal indicating an address0. Next, the configuration information item stored in the storage region at the address0is read out from the configuration information storage memory12cand then supplied to the data path unit13c. Thus, a first intermediate processing circuit that executes first processing is configured by the tile T1, a second intermediate processing circuit that executes second processing is configured by the tile T2, and a third intermediate processing circuit that executes third processing is configured by the tile T3. The selector SEL1is configured to select and output an output result of the tile T1, the selector SEL2is configured to select and output an output result of the tile T2, and the selector SEL3is configured to select and output an output result of the tile T3. As a result, in the data path unit13c, a process can be executed by a desired processing circuit.

In this state, the input data Din is supplied to the data path unit13c. The first intermediate processing circuit configured using the tile T1performs the first processing on the input data Din. After that, the second intermediate processing circuit configured using the tile T2performs the second processing on the output result of the tile T1. Then, the third intermediate processing circuit configured using the tile T3performs the third processing on the output result of the tile T2. Thus, the output result of the tile T3is output outside as the output data Dout of the data path unit13c. As described above, in the data path unit13c, a process is executed by a desired processing circuit.

FIG. 16is a timing chart showing an operation in the normal mode of the reconfigurable device1c. Referring toFIG. 16, the first to third processing are performed on the input data Din in a certain cycle, and then the processing result is output as the output data Dout in the next cycle. That is, the first to third processing are executed in a total of one cycle. Note that in an example ofFIG. 16, the input data Din in each cycle is distinguished and represented by input data inA to inH, and output data Dout corresponding to the input data inA to inH is distinguished and represented by output data outA to outH.

(Operation in Safe Mode)

Next, an operation in one safe mode of the reconfigurable device1cwill be described.FIGS. 17 to 19are block diagrams for explaining the operation in the safe mode of the reconfigurable device1c.

As shown inFIG. 17, when failures are detected in the tiles T2and T3provided in the data path unit13c, that is, when the failure detection signals ERF2and ERF3output respectively from the tiles T2and T3become active, firstly the state transition management unit11outputs the address signal indicating an address1. Next, the configuration information item stored in the storage region at the address1is read out from the configuration information storage memory12cand then supplied to the data path unit13c. Thus, the first intermediate processing circuit that executes the first processing is configured by the tile T1.

In this state, the input data Din is supplied to the data path unit13c. The first intermediate processing circuit configured using the tile T1performs the first processing on the input data Din, and when the first processing is completed, the first intermediate processing circuit switches the process completion signal EVF1from inactive to active.

As shown inFIG. 18, when the process completion signal EVF1becomes active, the state transition management unit11switches the address signal to indicate an address2from the address signal that indicates the address1and then outputs the switched address signal. Next, the configuration information item stored in the storage region at the address2is read out from the configuration information storage memory12cand then supplied to the data path unit13c. Thus, the second intermediate processing circuit that executes the second processing is configured by the tile T1.

In this state, a result of the first processing by the tile T1is supplied to the second intermediate processing circuit configured using the tile T1. Note that in an example ofFIG. 18, a feedback path is not shown. The second intermediate processing circuit configured using the tile T1performs the second processing on the result of the first processing, and when the second processing is completed, the second intermediate processing circuit switches the process completion signal EVF1from inactive to active.

As shown inFIG. 19, when the process completion signal EVF1becomes active, the state transition management unit11switches the address signal to indicate an address3from the address signal that indicates the address2and then outputs the switched address signal. Next, the configuration information item stored in the storage region at the address3is read out from the configuration information storage memory12cand then supplied to the data path unit13c. Thus, the third intermediate processing circuit that executes the third processing is configured by the tile T1. At this time, the selector SEL3is configured to select and output the output result of the tile T1.

In this state, a result of the second processing by the tile T1is supplied to the third intermediate processing circuit configured using the tile T1. Note that in an example ofFIG. 19, a feedback path is not shown. The third intermediate processing circuit configured using the tile T1performs the third processing on the result of the second processing. Then, the output result of the tile T1is output outside as the output data Dout of the data path unit13c. As a result, in the data path unit13c, a process is executed by a desired processing circuit.

FIG. 20is a timing chart showing an operation in the safe mode of the reconfigurable device1c. Referring toFIG. 20, the first processing is performed on the input data Din in a certain cycle, the second processing is performed on the input data Din in the next cycle, the third processing is performed on the input data Din in the next cycle, and then the input data Din is output as the output data Dout in the next cycle. That is, the first to third processing are executed in a total of three cycles. Note that in an example ofFIG. 20, the input data Din in each cycle is distinguished and represented by input data inA to inC, and output data Dout corresponding to the input data inA to inC is distinguished and represented by output data outA to outC.

As described above, even when failures are detected in the tiles T2and T3of the data path unit13c, the reconfigurable device1cexecutes the first to third processing in a time-sharing manner using the tile T1in which no failure is detected, so that a process can be executed by a desired processing circuit without skipping low-priority processing.

Although an example in which the tiles T2and T3fail has been described, it is not limited to this. More specifically, when the tiles T1and T2fail, or when the tiles T1and T3fail, a process can be executed by a desired processing circuit. Note that when the tiles T1and T3fail, the first to third processing are executed in a time-sharing manner using the tile T2in which no failure is detected. When the tiles T1and T2fail, the first to third processing are executed in a time-sharing manner using the tile T3in which no failure is detected.

Although an example in which two tiles from among the three tiles T1to T3fail has been described, it is not limited to this. More specifically, when any one of the three tiles T1to T3fails, a process can be executed by a desired processing circuit. In this case, the first to third processing are executed in a time-sharing manner using one or two tiles in which no failure is detected.

Moreover, although examples in which two or three tiles are provided have been described in the above embodiments, it is not limited to this, and four or more tiles may be provided.

In the reconfigurable device according to this embodiment, when a failure is detected in any one of a plurality of tiles provided in a dynamically reconfigurable data path unit, the first intermediate processing circuit is configured using the tile in which no failure is detected, and then the second intermediate processing circuit is configured again using the tile in which no failure is detected, in order to achieve a desired first processing circuit. Thus, the reconfigurable device according to this embodiment can execute desired processing without skipping low-priority processing even when a failure is detected.

Second Embodiment

FIG. 21is a block diagram showing a configuration example of a reconfigurable device (a semiconductor device)2according to a second embodiment. In the reconfigurable device2according to this embodiment, when a failure is detected in any one of a plurality of logic circuits provided in a dynamically reconfigurable data path unit, a plurality of first processing circuits are configured using some or all of the plurality of logic circuits, and a final result of processing by the first processing circuits is determined according to results of processing by the respective plurality of first processing circuits. Thus, the reconfigurable device2according to this embodiment can output the result of processing highly accurately even when a failure is detected. Moreover, in a manner similar to that of the reconfigurable device1, the reconfigurable device2according to this embodiment can execute desired processing without skipping low-priority processing even when a failure is detected. Hereinafter, the reconfigurable device2will be described in detail.

As shown inFIG. 21, the reconfigurable device2includes a state transition management unit21, a configuration information storage memory22, a data path unit23, a majority vote circuit28, and a selector29. Further, an error path26is provided between the data path unit23and the state transition management unit21. An address path24is provided between the state transition management unit21and the configuration information storage memory22. A configuration information path25is provided between the configuration information storage memory22and the data path unit23.

Note that the state transition management unit21, the configuration information storage memory22, the data path unit23, the address path24, the configuration information path25, and the error path26respectively correspond to the state transition management unit11, the configuration information storage memory12, the data path unit13, the address path14, the configuration information path15, and the error path16. Different configurations and operations from those explained in the first embodiment will be mainly described in this embodiment.

In the configuration information storage memory22, for example, a configuration information item in the normal mode is stored in a storage region at an address0, and a configuration information item in the failure mode is stored in a storage region at an address1.

FIG. 22is a state transition diagram of the reconfigurable device2. Details of the state transition diagram will be described later together with a description of an operation of the reconfigurable device2.

(Operation in Normal Mode)

An operation in the normal mode of the reconfigurable device2will be described first.FIG. 23is a block diagram for explaining the operation in the normal mode of the reconfigurable device2.

As shown inFIG. 23, when a failure is not detected in any one of the plurality of logic circuits provided in the data path unit23, that is, when the failure detection signal ERF1output from the data path unit23is inactive, the state transition management unit21outputs the address signal indicating an address0(ST21inFIG. 22). Next, the configuration information item stored in the storage region at the address0is read out from the configuration information storage memory22and then supplied to the data path unit23. Then, a first processing circuit231is configured by some of the plurality of logic circuits provided in the data path unit23.

In this state, the input data Din is supplied to the data path unit23. The first processing circuit231configured using some of the plurality of logic circuits provided in the data path unit23performs predetermined processing on the input data Din. A result of processing by the first processing circuit231is output outside the data path unit23. At this time, the selector29selects the result of processing by the first processing circuit231and outputs it as the output data Dout.

(Operation in Failure Mode)

Next, an operation in the failure mode of the reconfigurable device2will be described.FIG. 24is a block diagram for explaining an operation in the failure mode of the reconfigurable device2.

As shown inFIG. 24, when a failure is detected in any one of the plurality of logic circuits provided in the data path unit23, that is, when the failure detection signal ERF1output from the data path unit23becomes active, the state transition management unit21outputs the address signal indicating an address1(ST22inFIG. 22). Next, the configuration information item stored in the storage region at the address1is read out from the configuration information storage memory22and then supplied to the data path unit23. Thus, three first processing circuits232to234having the same configuration are configured by some or all of the plurality of logic circuits provided in the data path unit23.

In this state, the input data Din is supplied to the data path unit23. Each of the first processing circuits232to234configured by some or all of the plurality of logic circuits provided in the data path unit23performs processing on the input data Din in parallel. Results of the processing by the first processing circuits232to234are output outside the data path unit23.

The majority vote circuit28outputs the result of processing of a logical value that accounts for a majority of the results of the processing by the first processing circuits232to234. The selector29selects an output result of the majority vote circuit28and output it as the output data Dout. That is, the result of processing of the logical value that accounts for a majority of the results of the processing by the first processing circuits232to234is used as the result of processing by the first processing circuit231.

As described above, in the reconfigurable device2, when a failure is detected in any one of the plurality of logic circuits provided in the data path unit23, three first processing circuits232to234having the same configuration are configured using some or all of the plurality of logic circuits, and the result of the processing of the logical value that accounts for a majority of the results of the processing by the respective first processing circuits232to234is output as the result of the processing by the first processing circuit231. Thus, the reconfigurable device2according to this embodiment can output the result of processing highly accurately even when a failure is detected. Moreover, in a manner similar to that of the reconfigurable device1, the reconfigurable device2according to this embodiment can execute desired processing without skipping low-priority processing even when a failure is detected.

Further, in the reconfigurable device2, when a failure is not detected in any one of the plurality of logic circuits provided in the data path unit23, a single first processing circuit231is configured using some of the plurality of logic circuits. By doing so, the reconfigurable device2can configure other processing circuits using remaining logic circuits (hardware resources).

Moreover, as it is not necessary to divide a circuit into a plurality of tiles, it is easy to incorporate the reconfigurable device2.

In this embodiment, although an example in which three first processing circuits232to234are configured when a failure is detected in the data path unit23has been described, it is not limited to this. More specifically, four or more first processing circuits may be configured in order to further improve the accuracy.

In addition, in this embodiment, although an example in which the majority vote circuit28and the selector29are provided has been described, it is not limited to this. The majority vote circuit28and the selector29may be configured using some of the plurality of logic circuits provided in the data path unit23.

Although the invention carried out by the present inventor has been described in detail based on the embodiments, it is obvious that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

For example, in the semiconductor device according to the above embodiments, a conductivity type (p-type or n-type) of a semiconductor substrate, a semiconductor layer, and a diffusion layer (a diffusion region) may be inverted. Therefore, when one of the conductivity types, which are an n-type and p-type, is considered to be a first conductivity type, and the other one of the conductivity types is considered to be a second conductivity type, the first conductivity type may be a p-type and the second conductivity type may be an n-type. Conversely, the first conductivity type may be an n-type, and the second conductivity type may be a p-type.

The first and second embodiments can be combined as desirable by one of ordinary skill in the art.