Circuit with reset noise cancellation

A circuit primarily for use in conjunction with focal plane arrays which rejects input reset noise without adding power and complexity to the circuit. The circuit includes a preamplifier having input and output terminals, a first capacitor coupled between the input terminal and a source of reference potential, a second capacitor coupled between the output terminal and the source of reference potential, a switch coupled between the output terminal and the second capacitor coupling the output terminal to the second capacitor in response to a first predetermined signal, a third capacitor coupled between the junction of the switch and the second capacitor and a circuit output terminal and a plurality of fourth capacitors, each of the fourth capacitors coupled to a photodetector and having a switch responsive to a second predetermined signal controlling coupling of the fourth capacitor in parallel with the first capacitor. The values of the first, second, third and fourth capacitors are substantially in accordance with the relation C.sub.p /(C.sub.p +C.sub.DN)=C.sub.X /(C.sub.X +C.sub.c), where C.sub.P is the first capacitor, C.sub.X is the second capacitor, C.sub.C is the third capacitor and C.sub.DN is the fourth capacitor.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates to a circuit for cancellation of reset noise and, 
more specifically, to such a circuit, generally in conjunction with a 
focal plane array (FPA). 
2. Background and Brief Description of the Prior Art 
Staring focal plane arrays are composed of many detectors which detect a 
particular portion of a scene and which must be read out in some ordered 
manner. This read out generally is accomplished by multiplexing the 
outputs of several detectors into a single preamplifier. In order to 
obtain accurate reading of the detector outputs at the preamplifier input, 
it is necessary that, between the serial readings of the detector outputs, 
the preamplifier input be cleansed of the total signal from the prior 
sample video, this generally being accomplished by resetting the 
preamplifier input to a predetermined DC voltage. The reset operation 
gives rise to a noise term at the preamplifier input generally known as 
KTC noise which is V.sub.n =(KT/C.sub.p).sup.1/2, where V.sub.n is the 
noise voltage, K is Boltzmann's constant, T is the temperature in degrees 
Kelvin and C.sub.p is the input capacitance of the preamplifier in farads 
and is the sum of all capacitances on the input node, preamplifier 
capacitance, read line capacitance and stray capacitance. This noise term 
can be substantial compared to the signals produced by the detectors of 
the array and thereby introduce significant error in the output. 
Accordingly, this noise must be cancelled out to fully realize the 
performance potential of the focal plane array. 
The above described reset noise remains correlated from the reset time to 
the read time for the next detector and can be removed by a correlated 
double sampling. However, the magnitude of the noise term changes when the 
detector is addressed. This is better understood with reference to FIGS. 1 
and 2. When the preamplifier input is reset as shown in FIG. 2 for timing 
signal .phi..sub.R, switch S.sub.R closes, switches S.sub.1 through 
S.sub.N, which represent the detector addresses, being open at this time. 
This closing and opening of switch S.sub.R provides the undesirable KTC 
noise. The detectors are schematically represented in all figures herein 
as capacitors C.sub.D1 to C.sub.DN charged to voltages representing the 
video information detected by the associated detector. The noise created 
by the reset is stored on the clamp capacitor C.sub.c before the detectors 
are addressed. The switch S.sub.c is then closed as shown in FIG. 2 for 
timing signal .phi..sub.c to discharge capacitor C.sub.c and store the KTC 
noise value thereon. The switch S.sub.N is then closed as shown in FIG. 2 
for timing signal .phi..sub.DN to transfer the charge on capacitor 
C.sub.DN to capacitor C.sub.p. The signal voltage is amplified by the 
preamplifier and is coupled through the capacitor C.sub.c. The signal is 
transferred to capacitor C.sub.s at time .phi..sub.s. (The gain of the 
preamplifier is assumed to be unity for ease of explanation. Also DC terms 
are not carried through for the same reason.) 
When switch S.sub.N closed, a charge representing the video from the 
detector and stored on the capacitor C.sub.DN is stored onto capacitor 
C.sub.p along with the noise term thereat. The result with regard to the 
noise is that the noise on the capacitor at the preamplifier input drops 
to: 
EQU V.sub.n '=[C.sub.p /(C.sub.p +C.sub.DN)](KT/C.sub.p).sup.1/2 
The noise that appears on the sample (i.e., the capacitor C.sub.s when 
O.sub.s is closed) is: 
EQU V.sub.n.sup.o =V.sub.n '-V.sub.n =(KT/C.sub.p).sup.1/2 [C.sub.p /(C.sub.p 
+C.sub.DN)-1] 
It is readily apparent that except where C.sub.p is much greater than 
C.sub.D, the cancellation scheme is not effective. 
The same problem has been solved in barium strontium titanate (BST) focal 
plane arrays by using paralleled amplifiers to drive the correlated double 
sampler (CDS) clamp capacitor C.sub.c. The gains were scaled such that the 
difference in gains matched the capacitive divider and rejection was 
achieved. Another prior art scheme changes the gain of the preamplifier 
from clamp to sample time in order to track the capacitive divider at the 
input. 
Some problems with these solutions are: 
1. For parallel amplifiers, additional power dissipation is required 
whereas space for the additional circuitry is at a premium for IR focal 
plane arrays (FPAs). Also, 1/F noise from the parallel amplifiers does not 
tend to cancel and, in fact, may be additive. 
2. Sequential gain changing is time consuming and provides a technical 
challenge to maintain tracking from channel to channel. The more complex 
circuits consume additional power. DC shifts in the preamplifier output 
also corrupt the signal from clamp to sample time. 
SUMMARY OF THE INVENTION 
In accordance with the present invention, the above described deficiencies 
of the prior art are minimized and there is provided a circuit which 
rejects noise, particularly, but not limited to staring IR focal plane 
array without adding power and complexity to the silicon IC processor. 
This noise improvement reduces processor noise by nearly the square root 
of two for most designs and makes the focal plane arrays less susceptible 
to picking up extraneous system noise, thereby providing high performance 
more simply than in the prior art. In addition, the yields provided in 
processing should increase substantially. This invention may also be used 
on other focal plane arrays and systems, such as, for example, 
pyroelectric focal plane arrays, arrays of particle detectors, analog 
memory readouts and solid state imaging arrays with photocapacitor and 
photodiode architectures for visible application. 
More specifically, an additional switch S.sub.x is added in series with the 
output of the preamplifier and a capacitor C.sub.x to ground is added at 
the output of the preamplifier after the added switch in accordance with 
the present invention. The result of the circuit addition is shown as 
follows: 
As before the terms for noise are: 
EQU V.sub.n =(KT/C.sub.p).sup.1/2, and 
EQU V.sub.n '=C.sub.p /(C.sub.p +C.sub.DN) [KT/C.sub.p ].sup.1/2 
However, the noise stored on the clamp capacitor C.sub.c is: 
EQU V.sub.o =C.sub.x /(C.sub.x +C.sub.c) [KT/C.sub.p ].sup.1/2 
Note that the activator of the signal closing the switch S.sub.x during the 
on time of the reset signal resets old KT/C.sub.p noise from the clamp 
capacitor and the voltage stored on the samples is: 
EQU V.sub.n ={[(C.sub.p /(C.sub.p +C.sub.DN)]-[C.sub.x /(C.sub.x 
+C.sub.c)]}(KT/C.sub.p).sup.1/2 
It is now readily apparent that C.sub.x and C.sub.c can be chosen such 
that: 
EQU C.sub.p /(C.sub.p +C.sub.DN)=C.sub.x /(C.sub.x +C.sub.c) 
whereby V.sub.n would then be zero, thereby eliminating all noise, assuming 
a perfect match. 
The above described technique is superior to the prior art systems because: 
1. it cancels out KTC or (KT/C.sub.p).sup.1/2 noise. 
2. it cancels out any aliased terms of system noise sampled by the reset 
operation of the preamplifier input. 
3. it still provides rejection of preamplifier 1/F noise. 
4. it adds virtually no power to the architecture. 
An alternate embodiment would not require the output sample circuits 
S.sub.s and C.sub.s. 
The preamplifier will generally have sufficient gain to raise the video 
signals above the system noise floor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring now to FIGS. 3 and 4, there is shown a circuit and timing diagram 
therefor in accordance with a first embodiment of the present invention. 
The circuit is identical to that of FIG. 1 except for the addition of 
switch S.sub.X and capacitor C.sub.X. The circuit includes a plurality of 
capacitors C.sub.D1 to C.sub.DN which represent the video information 
thereon received from detectors. The output of each of the capacitors 
C.sub.D1 to C.sub.DN is controlled by an associated switch S.sub.1 to 
S.sub.N respectively and is fed to capacitor C.sub.p at the input of 
preamplifier 1. The capacitor C.sub.p is discharged to ground by closure 
of switch S.sub.R. The output of the preamplifier 1 is fed through switch 
S.sub.X to a capacitor C.sub.X which is coupled between the preamplifier 
output and after switch S.sub.X and ground or reference voltage. A series 
clamp capacitor C.sub.C is coupled between the switch S.sub.x and an 
amplifier 3 with a switch S.sub.C coupled between the input of amplifier 3 
and ground. The output of amplifier 3 passes through a switch S.sub.s to a 
capacitor C.sub.s which is the circuit output. In order to eliminate the 
KTC noise, the value of the capacitor C.sub.X is set to be equal to 
(C.sub.c C.sub.p)/C.sub.D) where C.sub.D is the capacitance of a capacitor 
which represents the video information received from an associated 
detector, these capacitors being shown in FIG. 3 as C.sub.D1 . . . 
C.sub.DN. 
In operation, when the preamplifier input is reset at as shown in FIG. 4 
for timing signal .phi..sub.R, switch S.sub.R closes and switches S.sub.1 
through S.sub.N, which represent the detector addresses, are open. The 
closing and opening of switch S.sub.R both provide the undesirable KTC 
noise, the closing also discharging or resetting capacitor C.sub.p. The 
detectors, which are schematically represented as capacitors C.sub.D1 to 
C.sub.DN, are at this time charged to voltages representing the video 
information detected by the associated detector. The noise created by the 
reset switch closing and opening is stored on capacitor C.sub.p. The 
switches S.sub.X and S.sub.c are first closed during reset to discharge 
capacitor C.sub.c and close the path from capacitor C.sub.p through 
preamplifier 1 to capacitor C.sub.X to charge that capacitor with the 
noise signal on capacitor C.sub.p. After the termination of reset, the 
switch S.sub.X is again momentarily closed to direct any further noise to 
capacitors C.sub.X and C.sub.c with the switch S.sub.c then being closed 
to again discharge any noise signal from the capacitors C.sub.X and 
C.sub.c. One of the switches S.sub.N is then closed as shown in FIG. 4 for 
timing signal .phi..sub.CDN to transfer the charge on the associated 
capacitor C.sub.DN to capacitor C.sub.p and through the preamplifier to 
capacitors C.sub.X and C.sub. c where it is stored and transferred to 
capacitor C.sub.s with the simultaneous closing of switch S.sub.s. (The 
gain of the preamplifier is assumed to be unity for ease of explanation. 
Also DC terms are not carried through for the same reason.) In accordance 
with the present invention, the KTC noise has been essentially removed by 
setting the values of capacitors C.sub.x and C.sub.c such that C.sub.p 
/(C.sub.p +C.sub.DN)=C.sub.X /(C.sub.X +C.sub.c). 
As a second embodiment of the invention, the embodiment of FIGS. 5 and 6 is 
provided except that the sample circuit composed of switch S.sub.s and 
capacitor C.sub.s has been omitted. For this embodiment, the sample 
operation takes place when the 0dn switch is closed by closing the 0sx 
switch. The signal is held by the capacitance at node X, being the sum of 
Cx and the series combination of Cc and the input capacitance of the 
buffer amplifier. The sum is denominated by Cx. This embodiment is 
advantageous because it requires fewer parts and can fit into a more 
compact circuit layout while providing the same performance advantages as 
the embodiment of FIG. 2. 
Though the invention has been described with respect to specific preferred 
embodiments thereof, many variations and modifications will immediately 
become apparent to those skilled in the art. It is therefore the intention 
that the appended claims be interpreted as broadly as possible in view of 
the prior art to include all such variations and modifications.