Delay compensation systems and methods for DC to DC converters

A control system for a DC to DC converter includes a predicted state generator module, a voltage estimation module, an error module, and a pulse width modulation (PWM) module. During a prior sampling period, the predicted state generator module generates a predicted capacitor voltage and a predicted capacitor current for a current sampling period. The voltage estimation module generates an estimated value of an output voltage of the DC to DC converter during the current sampling period based on the predicted capacitor current, the predicted capacitor voltage, a delay value, and a duty cycle value for the prior sampling period. The error module generates a voltage error value based on difference between a measured value of the output voltage and the estimated value. The PWM module controls the duty cycle of the DC to DC converter based on the voltage error value.

FIELD

The present disclosure relates to control systems for power supplies and more particularly to systems and methods for direct current (DC) to DC buck converters.

BACKGROUND

A power supply outputs a predetermined voltage that may be used to power one or more components. For example, the predetermined voltage may power one or more components of an integrated circuit (IC). In some situations, however, a voltage that is less than the predetermined voltage may be sufficient. The lower voltage may be obtained from the predetermined voltage using a voltage divider circuit. Voltage divider circuits, however, are inefficient and inaccurate.

A step-down (“buck”) converter may be implemented to provide the lower voltage. Under a given set of conditions, a buck converter is generally more efficient and more accurate than a voltage divider circuit. A buck converter may include an inductor, a capacitor, and two switches. The buck converter alternates between charging the inductor by connecting the inductor to the predetermined voltage and discharging the inductor to a load.

SUMMARY

A control system for a DC to DC converter includes a predicted state generator module, a voltage estimation module, an error module, and a pulse width modulation (PWM) module. During a prior sampling period, the predicted state generator module generates a predicted capacitor voltage and a predicted capacitor current for a current sampling period. The voltage estimation module generates an estimated value of an output voltage of the DC to DC converter during the current sampling period based on the predicted capacitor current, the predicted capacitor voltage, and a duty cycle value for the prior sampling period. The error module generates a voltage error value based on difference between a measured value of the output voltage and the estimated value. The PWM module controls the duty cycle of the DC to DC converter based on the voltage error value.

A control method for a DC to DC converter, includes: during a prior sampling period, generating a predicted capacitor voltage and a predicted capacitor current for a current sampling period; generating an estimated value of an output voltage of the DC to DC converter during the current sampling period based on the predicted capacitor current, the predicted capacitor voltage, and a duty cycle value for the prior sampling period; generating a voltage error value based on difference between a measured value of the output voltage and the estimated value; and controlling the duty cycle of the DC to DC converter based on the voltage error value.

DETAILED DESCRIPTION

A direct current (DC) to DC buck (or step-down) converter receives an input voltage and generates an output voltage that is less than the input voltage. A converter control module controls switching of one or more switches of the buck converter based on a difference between a measured value of the output voltage at a sampling time and an estimated value of the output voltage for the sampling time. The converter control module generates the estimated value for the sampling time based on a predicted capacitor current for the sampling time and a predicted capacitor voltage for the sampling time.

Some amount of delay is typically associated with a given buck converter. For example only, a first delay may be attributable to a period between measuring the output voltage and generating the measured value, a second delay may be attributable to determining how to control the switching, and a third delay may be attributable to transitioning a switch from on to off or vice versa.

A converter control module of the present disclosure generates the estimated value of the output voltage for a given sampling time (n) based on a delay parameter. The delay parameter is set based on the second and third delays. Generating the estimated value based on the delay parameter reduces the period between when a change in load occurs and when the output voltage returns to a desired or commanded voltage.

Referring now toFIG. 1, a diagram of an example implementation of a direct current (DC) to DC buck converter system100is shown. A DC power source104inputs DC power to a DC to DC buck converter108. A voltage input to the buck converter108will be referred to as an input voltage (VIN)112. The buck converter108may include a switching module116, a first resistor (RL)120, an inductor (L)124, a second resistor (RC)128, and a capacitor (C)132. The buck converter108outputs DC power to a load136. The voltage output by the buck converter108may be provided as a feedback voltage (VFB)140. The current through the load136will be referred to as a load current (ILOAD))144. In various implementations, a DC to DC buck converter (not shown) may include one or more buck converters, such as the buck converter108, connected in parallel to collectively output DC power to the load136.

The switching module116includes a first switch148and a second switch152. For example only, the first and second switches148and152may be field effect transistors (FETs) as shown in the example ofFIG. 1. In various implementations, such as in the example ofFIG. 1, the first and second switches148and152may be p-type, enhancement FETs. The first and/or the second switch148and152may be another suitable type of switch.

In the example ofFIG. 1, a source terminal of the first switch148is connected to the input voltage112, and a drain terminal of the first switch148is connected to a source terminal of the second switch152. The drain terminal of the second switch152is connected to ground. A first end of the first resistor120is connected to a first end of the inductor124, and a second end of the first resistor120is connected to a node156between the drain terminal of the first switch148and the source terminal of the second switch152. A voltage at the node156will be referred to as a switching voltage (VSW). A second end of the inductor124is connected to a first end of the second resistor128, and a second end of the second resistor128may be connected to an anode of the capacitor132. A cathode of the capacitor132may be connected to ground.

The feedback voltage140may be measured at a node between the inductor124and the second resistor128. The switching module116controls connection and disconnection of the inductor124and the input voltage112. Gate terminals of the first and second switches148and152are connected to a converter control module180. In various implementations, such as implementations where the load current is less than a predetermined current (e.g., 5 amps), the converter control module180and the buck converter108may be implemented on one chip. In other implementations, such as in implementations where the load current is greater than the predetermined current, the buck converter108may be implemented independently of the converter control module180.

The converter control module180controls operation of the first and second switches148and152. The converter control module180controls first and second switches148and152using pulse width modulation (PWM). More specifically, the converter control module180generates first and second PWM signals184and188(S1and S2) that are applied to the gate terminals of the first and second switches148and152, respectively.

The converter control module180varies the duty cycle of the first and second PWM signals184and188to control the output of the buck converter108. The duty cycle of a signal may refer to a percentage of a predetermined period (e.g., a control loop) during which the signal is in an active state.

The converter control module180may generate the first and second PWM signals184and188such that the first and second PWM signals184and188are substantially complementary. In other words, the first PWM signal184applied to the gate terminal of the first switch148is generally opposite in polarity to the second PWM signal188provided to the second switch152. A short circuit condition may occur when both of the first and second switches148are on. For example only, a short circuit condition may occur when one of the first and second switches148and152is switched on before the other of the first and second switches148and152is switched off. To avoid a short circuit condition, the first and second switches148and152may both be turned off during a deadtime period before one of the first and second switches148and152is turned on. Therefore, two signals being substantially complementary may mean that the two signals are opposite in polarity most of the time during switching. However, around transitions, the first and second PWM signals184and188may be in the same state for a short period.

When the first switch148is on and the second switch152is off, the inductor124is connected to the input voltage112, thereby charging the inductor124and the capacitor132. When the first switch148is off and the second switch152is on, the inductor124is disconnected from the input voltage112, and the inductor124and the capacitor132discharge energy. The converter control module180may control the first and second PWM signals184and188to maintain the feedback voltage140at approximately a predetermined (e.g., commanded or desired) voltage. The predetermined voltage is less than the input voltage112.

Generally, for every circuit that generates an output based on an input, a delay period exists between a time that a change in the input is made and a time that the output reflects the change in the input. For the buck converter system100, for example, there is a delay period between a time that the converter control module180changes the duty cycle and a time that the output of the buck converter108reflects the change in the duty cycle. For example only, in the buck converter system100, the delay period may include: a first delay period associated with measuring the feedback voltage140and generating a discrete value based on the feedback voltage140; a second delay period associated with determining and outputting the duty cycle; and a third delay period associated with transitioning a switch from on to off or vice versa. The first delay period will be referred to as an analog to digital conversion (ADC) delay, the second delay period will be referred to as a computation delay, and the third delay period will be referred to as a switching delay.

The converter control module180samples the feedback voltage140at sampling times that are each separated by a predetermined period. In other words, the converter control module180samples the feedback voltage140at predetermined intervals. The converter control module180also generates estimates of the feedback voltage140at the sampling times, respectively. The converter control module180controls the duty cycle in closed-loop based on the feedback voltage140and the estimate of the feedback voltage140at a given sampling time (n).

A change (i.e., decrease or increase) in the load current144may cause a change in the feedback voltage140. The converter control module180may change the duty cycle in response to the change in the feedback voltage140. However, the computation and switching delays may prevent the converter control module180from responding to the change in the feedback voltage140in a timely manner.

The converter control module180of the present disclosure generates the estimates of the feedback voltage140based on the computation and switching delays. Estimating the feedback voltage140based on the computation and switching delays improves the ability of the converter control module180to respond to changes in the load current144and the feedback voltage140without the need to add hardware (e.g., a capacitor) and/or substantially increasing the computational intensity of generating the estimates.

Referring now toFIG. 2, a functional block diagram of an example implementation of the converter control module180is presented. The converter control module180may include an analog to digital converter (ADC)304, an error module308, a feedback voltage estimation module312, delay modules316and320, and a predicted state generator module324. The converter control module180may also include an estimator gain application module328, a current state generator module332, a duty cycle setting module336, and a digital PWM (DPWM) module340.

The ADC304samples the feedback voltage140at a predetermined sampling rate (i.e., at predetermined intervals). For a given sampling time (n), the ADC304generates a feedback voltage value VFBbased on the feedback voltage140.

Based on the buck converter108, the following linear (continuous) equations can be derived:

L⁢ⅆi⁡(t)ⅆt=vSW⁡(t)-RL⁢i⁡(t)-vFB⁡(t);C⁢ⅆv⁡(t)ⅆt=i⁡(t)-iLOAD⁡(t);andvFB⁡(t)=v⁡(t)+RC⁡(i⁡(t)-iLOAD⁡(t)),
where L is the inductance of the inductor124, vSW(t) is the switching voltage at the node156at a given time (t), RLis the resistance of the first resistor120, C is the capacitance of the capacitor132, i(t) is the current through the inductor124at the given time (t), vFB(t) is the feedback voltage140at the given time (t), v(t) is the capacitor voltage at the given time (t), iLOAD(t) is the load current144at the given time (t), and RCis the resistance of the second resistor128.

The linear equations can be re-written in matrix form as:

ⅆⅆt⁡[v⁡(t)i⁡(t)]=[01C-1L-(Rc+RL)L]⁡[v⁡(t)i⁡(t)]+[0-1C1LRCL]⁡[vSW⁡(t)ILOAD⁡(t)]=Ac⁢x⁡(t)+Bc⁢u⁡(t);⁢and⁢vFB⁡(t)=[1RC]⁢x⁡(t)=Cc⁢x⁡(t),
where AC, BC, and Ccare continuous matrices, and u(t) corresponds to the duty cycle of the first PWM signal184at the given time (t). For example only,

Ac=[01C-1L-RtL];Bc=[11L];andCc=[1Rc],
where Rc is the equivalent series resistance (ESR) of the capacitor132, and Rt is equal to the sum of RFETand Rc. RFETis the total RDS(on) of the first and second switches148and152.

The matrix form equations can be re-written in continuous state space form for a given time (t) as:

The continuous state space equations can be re-written for a given sampling time (n) in the discrete domain as:
XP(n+1)=Ad·XC(n)+Bd·u(n); and
vFB(n)=Cd·XC(n),
where XC(n) is a 2×1 matrix with entries representing current (i.e., present) values of the capacitor voltage and the capacitor current at the given sampling time (n), XP(n+1) is a 2×1 matrix with entries representing predicted values of the capacitor voltage and the capacitor current at a next sampling time (n+1) after the given sampling time (n), and u(n) corresponds to the duty cycle of the first PWM signal184at the given sampling time (n). Ad, Bd, and Cdare discrete matrices corresponding to the continuous matrices Ac, Bc, and Cc, respectively. For example only, Ad, Bd, and Cdcan be represented by:

Ad=[1wnts-wnts1];Bd=[wnts22wnts];andCd=[1Rc],
where Rc is the equivalent series resistance (ESR) of the capacitor132, and:

wnts=TsLC.
Tsis the sampling time of the converter control module180, L is the inductance of the inductor124, and C is the capacitance of the capacitor132.

The error module308generates a voltage error value (VERROR) for the given sampling time (n) based on the feedback voltage value for the given sampling time (n) and an estimated value (VEST) of the feedback voltage value for the given sampling time (n). For example only, the error module308may set the voltage error value equal to the feedback voltage value minus the estimated value. The voltage error value is used to control the duty cycle of the first and second PWM signals184and188in closed loop operation.

The feedback voltage estimation module312generates the estimated value for the given sampling time (n) based on a predicted state of the output of the buck converter108at the given sampling time (XP(n)), the duty cycle for the last sampling time before the given sampling time (u(n−1)), and a delay parameter (KDLY). The last sampling time before the given sampling time (n) may be represented as n−1.

For example only, the feedback voltage estimation module312may generate the estimated value for the given sampling time (n) using the equation:
VEST(n)=Cd·XP(n)+KDLY·u(n−1),
where VEST(n) is the estimated value for the given sampling time (n), Cdis the 1×2 matrix for the discrete domain, XP(n) is a 2×1 matrix representing the predicted state of the output of the buck converter108at the given sampling time (n), KDLYis the delay parameter, and u(n−1) is the duty cycle at the last sampling time (n−1). The entries of the 2×1 matrix representing the predicted state of the output of the buck converter108at the given sampling time (n) may include an entry for the capacitor voltage and an entry for the capacitor current. The delay parameter may be a predetermined value set based on the computation and switching delays. In various implementations, such as for adaptive systems, the delay parameter may be variable.

In various implementations, the feedback voltage estimation module312may generate the estimated value for the given sampling time (n) using the equation:
VEST(n)=Ce·XP(n)+KDLY·u(n−1),
where Ceis another 1×2 matrix for the discrete domain and corresponds to Cd. For example only, Cemay be represented by:

Cecan also be represented as:
Ce=Cce−TdAd,
where Tdcorresponds to the sum of the switching and computation delays. But,

For example only, the delay parameter (KDLY) can be represented as:

ⅇ-Td⁢Ad=[1wntd-wntd1],⁢andCc=[1yrc].
Therefore, the delay parameter KDLYcan be represented by:

KDLY=-[1yrc]⁡[1wntd-wntd1]⁡[wntd2wntd].
This equation for the delay parameter KDLYreduces to:

KDLY=[1yrc]⁡[wntd2-wntd2wntd32+wntd],
which further reduces to:

KDLY=wntd22-wntd2+yrc*wntd+yrc*wntd32,
which can be simplified to:
KDLY=yrc*wntd−wntd2.

Accordingly, the feedback voltage estimation module312may generate the estimated value for the given sampling time (n) using the equation:

The delay module316provides the duty cycle at the last sampling time (u(n−1)) to the feedback voltage estimation module312. The delay module320provides the predicted state of the output of the buck converter108at the given sampling time (XP(n)) to the feedback voltage estimation module312. The delay modules316and320may each include one unit (i.e., one sampling period) delay buffers. More specifically, the delay module316receives the duty cycle for the present sampling time (u(n)) and delays outputting that duty cycle for one sampling period. The delay module320receives the predicted state of the output of the buck converter108at a next sampling time (XP(n+1)) after the given sampling time(n) and delays outputting that predicted state for one sampling period.

The predicted state generator module324generates the predicted state of the output of the buck converter108at the next sample time XP(n+1) and outputs the predicted state at the next sample time to the delay module320. The predicted state generator module324may generate the predicted state at the next sample time based on the current state of the output of the buck converter108at the given sample time (XC(n)) and the duty cycle for the given sample time (u(n)). For example only, the predicted state generator module324may generate the predicted state at the next sample time (XP(n+1)) using the equation:

XP⁡(n+1)=Ad·Xc⁡(n)+Bd·u⁡(n),⁢orXP⁡(n+1)=Ae·Xc⁡(n)+Be·u⁢(n),⁢whereAe=[1wnte-wnte1],⁢andBe=[wnte22wnte],⁢wherewnte=TeLC.
Teis the sampling rate of the predicted state generator module324.

The estimator gain application module328receives the voltage error value for the given sampling time (n) from the error module308. The estimator gain application module328applies an estimator gain (KLC) to the voltage error value and outputs the result for the given sampling time (n) to the current state generator module332. The estimator gain may be set to adjust the voltage error value based on inaccuracy of the feedback voltage estimation module312. The estimator gain may be a 2×1 matrix such that the result of:
KLC*VERROR
is a 2×1 matrix like the predicted state of the output of the buck converter108at the given sampling time (XP(n)). One entry of the 2×1 matrix may be a predetermined value for the capacitor voltage and the other entry may be a predetermined value for the capacitor current. The result of the application of the estimator gain to the voltage error value for the given sampling time (n) will be referred to as the adjusted voltage error value (VERR-ADJ(n)).

The current state generator module332determines the current (i.e., present) state of the output of the buck converter108for the given sampling time (XC(n)) based on the predicted state of the output of the buck converter108at the given sampling time (XP(n)) and the adjusted voltage error value for the given sampling time (VERR-ADJ). For example only, the current state generator module332may set the current state of the output of the buck converter108for the given sampling time (n) equal to the sum of the predicted state of the output and the adjusted voltage error value.

The duty cycle setting module336sets the duty cycle for the given sampling time (u(n)) based on the current state of the output of the buck converter108(XC(n)) and a feedback gain (KFB). For example only, the duty cycle setting module336may set the duty cycle using the equation:
u(n)=KFB*XC(n),
where KFBis a 2×1 matrix. In various implementations, one entry of the 2×1 matrix may be a predetermined value for the capacitor voltage and the other entry may be a predetermined value for the capacitor current.

The DPWM module340generates the first and second PWM signals184and188based on the duty cycle. In various implementations, the duty cycle may be a value corresponding to a percentage between 0 percent and 100 percent. For example only, the DPWM module340may set the duty cycle of the first PWM signal184equal to or based on the duty cycle. The DPWM module340may set the duty cycle of the second PWM signal188to be substantially complementary to the first PWM signal184.

Referring now toFIG. 3, a flowchart depicting an example method400of estimating the feedback voltage140of the buck converter108is presented. At404, control generates the predicted state of output of the buck converter108at the next sampling time (XP(n+1)) based on the current state of the output of the buck converter108at the present sampling time (XC(n)) and the duty cycle at the present sampling time (u(n)). For example only, control may set the predicted state of the output of the buck converter at the next sampling time using the equation:
XP(n+1)=Ad·XC(n)+Bd·u(n)
where XC(n) is a 2×1 matrix with entries representing the values of the capacitor voltage and the capacitor current at the present sampling time, XP(n+1) is a 2×1 matrix with entries representing predicted values of the capacitor voltage and the capacitor current at the next sampling time (n+1), u(n) corresponds to the duty cycle of the first PWM signal184at the present sampling time, Adis a 2×2 matrix for discrete domain, and Bdis a 2×1 matrix for the discrete domain.

Control delays the use of the predicted state of output of the buck converter108by one sampling period at408. Control receives the predicted state of the output of the buck converter108at the present sampling time (XP(n)) at412(generated as XP(n+1) at the last sampling time). Control also receives the feedback voltage value at the present sampling time (VFB(n)) at416.

Control generates the estimated value of the feedback voltage value at420based on the predicted state of the output of the buck converter108at the present sampling time (XP(n)) and the duty cycle at the last sampling time (u(n−1)). For example only, control may generate the estimated value of the feedback voltage using the equation:
VEST(n)=Ce·XP(n)+KDLY·u(n−1).

Control generates the voltage error value for the present sampling time (VERROR(n)) at424based on the feedback voltage value for the present sampling time (VFB(n)) and the estimated value of the feedback voltage value for the present sampling time (VEST(n)). For example only, control may set the voltage error value equal to the feedback voltage value minus the estimated value.

Control generates the current state of the output of the buck converter108at the present sampling time (XC(n)) at428based on the voltage error value (VERROR(n)) and predicted state of the output of the buck converter108at the present sampling time (XP(n)). For example only, control may apply the estimator gain (KLC) to the voltage error value to generate the adjusted voltage error value and set the current state of the output equal to the sum of the predicted state of the output and the adjusted voltage error value. The estimator gain may be a 2×1 matrix, and the current state of the output of the buck converter108may be a 2×1 matrix.

Control generates the duty cycle for the present sampling time (u(n)) at432based on the current state of the output of the buck converter108at the present sampling time (XC(n)). For example only, control may generate the duty cycle using the equation:
u(n)=KFB*XC(n),
where KFBis a 2×1 matrix. Control delays use of the duty cycle for the present sampling time at436by one predetermined time interval. In this manner, at the next sampling time, control will generate the estimated value of the feedback voltage based on the duty cycle for the present sampling time.

Referring now toFIG. 4, an example graph of the feedback voltage140as a function of time is presented. A change in the load136occurs at approximately time zero. Example trace504tracks the feedback voltage140in an implementation where the converter control module180does not generate the estimated value of the feedback voltage value at a given sample time based on the computation and switching delays. Example trace508tracks the feedback voltage140in an implementation where the converter control module180generates the estimated value of the feedback voltage value based on the computation and switching delays. Line512corresponds to an example desired value of the feedback voltage140. As illustrated in the example ofFIG. 4, generating the estimated value of the feedback voltage based on the computation and switching delays enables the converter control module180to return the feedback voltage140to the desired or commanded value quickly after a change in the load136while minimizing over and undershoot.

Referring now toFIG. 5, an example Bode plot is presented. Example trace604tracks the feedback voltage140in an implementation where the converter control module180does not generate the estimated value of the feedback voltage value at a given sample time based on the computation and switching delays. Example trace608tracks the feedback voltage140in an implementation where the converter control module180generates the estimated value of the feedback voltage value based on computation and switching delays. AsFIG. 6illustrates, generating the estimated value of the feedback voltage based on the computation and switching delays provides increased phase margin (PM) and a decreased bandwidth. Generating the estimated value of the feedback voltage based on the computation and switching delays may provide an increased PM relative at a given bandwidth relative to generating the estimated value of the feedback voltage independent of the computation and switching delays.

Referring now toFIGS. 6A-6B, example graphs of the feedback voltage140as functions of time are presented. Example traces704track the magnitude of the load136. A change in the load occurs at approximately times708. Example trace712tracks the feedback voltage140in an implementation where the converter control module180does not generate the estimated value of the feedback voltage value at a given sample time based on the computation and switching delays. Example trace716tracks the feedback voltage140in an implementation where the converter control module180generates the estimated value of the feedback voltage value based on the computation and switching delays. As illustrated in the example ofFIGS. 6A-6B, generating the estimated value of the feedback voltage based on the computation and switching delays enables the converter control module180to return the feedback voltage140to the desired value as fast as possible and with as little over and undershoot as possible after a change in the load136occurs.