Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device

A semiconductor substrate comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; and semiconductor layers of mutually different film thicknesses formed on the dielectric layers.

TECHNICAL FIELD

The present invention relates to semiconductor substrates, semiconductor devices, methods for manufacturing semiconductor substrates, and methods for manufacturing semiconductor devices, and it is particularly suitable for application to field effect transistors formed on a SOI (Silicon On Insulator) substrate.

BACKGROUND OF THE TECHNOLOGY

The utilities of field effect transistors formed on a SOI substrate are attracting attention because of their readiness of element isolation, latch-up free characteristics, small source/drain junction capacitances and the like.

Also, for example, Japanese Laid-open Patent Application HEI 7-211917 (JP '917) describes a method of forming high breakdown voltage field effect transistors having a drain breakdown voltage of about several hundred V on a SOI substrate. Also, Japanese Laid-open Patent Application 2003-158091 (JP '091) describes a method of forming field effect transistors that are miniaturized on the other of submicron on a SOI substrate.

It is noted here that optimum film thicknesses of SOI layers and BOX layers differ for semiconductor elements of different usages. In other words, for a high breakdown voltage field effect transistor having a drain breakdown voltage of about several hundred V, its BOX layer needs to have a larger film thickness in order to secure the breakdown strength of the BOX layer and the back-channel threshold breakdown strength, and the film thickness of the BOX layer amounts to the order of μm. For example, in the case of a high breakdown voltage field effect transistor having a drain breakdown voltage of about 50V, the film thickness of the BOX layer needs to be about several hundred nm, and in the case of a high breakdown voltage field effect transistor having a drain breakdown voltage of about 500V, the film thickness of the BOX layer needs to be about several μm.

On the other hand, for a field effect transistor that is miniaturized on the order of submicron, its BOX layer needs to have a smaller film thickness in order to suppress reduction of threshold values by short-channel effects, and thus the film thickness of the BOX layer becomes to be on the order of several hundred angstrom. For example, when the effective channel length becomes 0.1 μm or less, the film thickness of the SOI layer needs to be set to 50 nm or less, and the film thickness of the BOX layer needs to be set to 50-100 nm.

In the meantime, accompanied by the advent of ubiquitous societies, the SOC (System On Chip) technology that enables mix-mounting of devices of various breakdown voltages and digital and analog devices on a single chip is attracting attention, for further promotion of miniaturization of information portable devices, reduction of power consumption, greater multiple functions, and greater capacities.

Also, Japanese Laid-open Patent Application 2002-299591 (JP '591) describes a method of forming semiconductor elements for different usages in active layers having thicknesses suitable for the respective usages by embedding dielectric films at different depths from a main surface of a semiconductor substrate, in order to realize the SOC on a SOI substrate.

However, according to the methods described in JP '917, JP '091, and JP '591, the film thickness of the BOX layer is maintained at constant by the SOI substrate. For this reason, for forming semiconductor elements for different usages on a SOI substrate, the semiconductor elements need to be independently formed on different SOI substrates for the respective usages, which causes a problem that presents an obstruction to realization of the SOC.

Also, according to the method described in JP '591, in order to embed dielectric films at different depths from the main surface of the semiconductor substrate, oxygen ions are injected in a silicon substrate with different energies. For this reason, physical damages are generated in the silicon substrate, and the crystallinity and purity of the SOI layer deteriorate, thereby causing a problem in that, when semiconductor elements are formed in the SOI layer, their characteristics deteriorate due to PN junction leakages or the like. In particular, according to the method described in JP '591, the amount of injecting oxygen ions needs to be increased in order to increase the film thickness of the BOX layer, such that damages at the time of ion injection and stresses caused by expansion of oxygen films increase. For this reason, there are problems in that crystal defects occur in the SOI layers, and the reliability of the semiconductor device deteriorates.

Furthermore, when a method in which two wafers are bonded together to increase the film thickness of the BOX layer is used, one of the wafers needs to be removed almost entirely, which causes a problem in that the resources are wasted. Also, in the method of bonding two wafers, differences in film thicknesses of SOI layers become greater, and BOX layers of different film thicknesses cannot be formed on a common SOI substrate, which causes a problem that presents an obstruction to realization of the SOC. Also, when a SOI layer is formed on BOX layers of different film thicknesses, step differences are generated in the surface of the SOI layer, which causes a problem in that processing accuracy of the semiconductor manufacturing process deteriorates.

Accordingly, it is an object of at least one embodiment of the present invention to provide semiconductor substrates, semiconductor devices, a method for manufacturing semiconductor substrates, and a method for manufacturing semiconductor devices, which can improve flatness of surfaces of semiconductor layers, and are capable of making film thicknesses of dielectric layers and semiconductor layers different from one another.

SUMMARY OF THE INVENTION

To solve the problems described above, a semiconductor substrate in accordance with an embodiment of the present invention is characterized in comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; and semiconductor layers of mutually different film thicknesses formed on the dielectric layers.

By this, the film thicknesses of the dielectric layers and semiconductor layers can be set so as to match with the respective usages of semiconductor elements, and semiconductor elements for mutually different usages can be formed on a common SOI substrate. For this reason, while short-channel effects can be suppressed, field effect transistors can be further miniaturized, and while breakdown strength of dielectric layers and PN junction breakdown strength can be secured, high breakdown voltage field effect transistors can be formed on a common SOI substrate. For this reason, a System-On-Chip can be realized on a common SOI substrate, and miniaturization, lower power consumption, greater multiple functions and greater capacities of semiconductor devices can be promoted.

Also, a semiconductor substrate in accordance with an embodiment of the present invention is characterized in comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; semiconductor layers of mutually different film thicknesses formed on the dielectric layers; and semiconductor elements for mutually different usages formed on the semiconductor layers.

By this, semiconductor elements do not need to be formed separately on independent SOI substrates for different usages, and semiconductor elements for different usages in which the film thickness of each dielectric layer and semiconductor layer is optimized can be formed on a common SOI substrate, such that greater performance of a system-on-chip can be achieved.

Also, a semiconductor device in accordance with an embodiment of the present invention is characterized in comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; semiconductor layers of mutually different film thicknesses formed on the dielectric layers; and semiconductor elements for mutually different usages formed on the semiconductor base and the semiconductor layers.

Further, a method for manufacturing a semiconductor substrate in accordance with an embodiment of the present invention is characterized in comprising: a step of forming, on a semiconductor base, a plurality of laminated layered structures, each composed of a second semiconductor layer having a smaller selection ratio at etching than a first semiconductor layer, laminated on the first semiconductor layer; a step of forming a first groove that penetrates the first semiconductor layers and the second semiconductor layers and exposes the semiconductor base; a step of forming a supporting body for supporting the second semiconductor layers on the semiconductor base on side walls of the first semiconductor layers and the second semiconductor layers in the first groove; a step of forming a second groove that exposes at least a part of the first semiconductor layers with the supporting body formed on the sidewall through the second semiconductor layers; a step of selectively etching the first semiconductor layers through the second groove to form a void section in a position where the first semiconductor layers existed; and a step of completely thermally oxidizing the second semiconductor layers for at least one layer through the void section to form a dielectric layer disposed below the second semiconductor layer at an uppermost layer.

By this, the second semiconductor layers can be supported on the semiconductor base through the supporting body formed in the first groove, and etching gas or etching liquid can be brought in contact with the first semiconductor layers through the second groove. For this reason, while the second semiconductor layers can be stably supported on the semiconductor base, the first semiconductor layers below the second semiconductor layers can be removed, and while physical damages that may be inflicted on the second semiconductor layers can be suppressed, a dielectric layer can be formed below the second semiconductor layer at the uppermost layer. As a result, by appropriately setting the number of layers of the first semiconductor layers that are exposed through the second semiconductor layers, and the film thicknesses of the first and second semiconductor layers, the film thicknesses of both of the dielectric layers and the semiconductor layers thereon can be made different from one another, the crystallinity and purity of the semiconductor layers disposed on the dielectric layers can be improved, and the reliability of the system-on-chip can be improved.

Also, a method for manufacturing a semiconductor substrate in accordance with an embodiment of the present invention is characterized in that the second semiconductor layer and the supporting body consist of single crystal Si, and the first semiconductor layer consists of single crystal SiGe.

By this, lattice matching among the second semiconductor layers, the supporting body and the first semiconductor layers can be made, and the selection ratio at the time of etching the first semiconductor layers can be made greater than that of the second semiconductor layers and the supporting body. For this reason, the second semiconductor layers of good crystal quality can be formed on the first semiconductor layers, the supporting body can be stably formed in the first groove, and the film thicknesses of both of the dielectric layers and semiconductor layers thereon can be made different from one another without damaging the quality of the second semiconductor layers.

Also, a method for manufacturing a semiconductor substrate in accordance with an embodiment of the present invention is characterized in that the first groove and the second groove are disposed in element isolation regions.

By this, element isolation of the second semiconductor layers in a transverse direction and a longitudinal direction can be conducted in a batch, and grooves for removing the first semiconductor layers under the second semiconductor layers do not need to be provided in element forming regions. For this reason, while an increase in the number of steps can be suppressed, SOI transistors can be formed, and an increase in the chip size can be suppressed, such that the cost of SOI transistors can be reduced.

Also, a method for manufacturing a semiconductor substrate in accordance with an embodiment of the present invention is characterized in that the second semiconductor layer at the uppermost layer has a greater film thickness compared to the second semiconductor layers at lower layers.

By this, even when at least one layer of the second semiconductor layers is completely thermally oxidized, the second semiconductor layer at the topmost layer can be prevented from completely disappearing, and the second semiconductor layer can be disposed on the dielectric layer.

Further, a method for manufacturing a semiconductor substrate in accordance with an embodiment of the present invention is characterized in further comprising the step of forming an oxidation prevention film on the second semiconductor layer at the uppermost layer, before thermal oxidation of the second semiconductor layers is conducted.

By this, even when at least one layer of the second semiconductor layers is completely thermally oxidized, the surface of the second semiconductor layer at the uppermost layer can be prevented from being thermally oxidized, and the second semiconductor layer at the uppermost layer can be prevented from completely disappearing.

Also, a method for manufacturing a semiconductor substrate in accordance with an embodiment of the present invention is characterized in that all of the second semiconductor layers below the second semiconductor layer at the uppermost layer are completely thermally oxidized.

By this, the film thickness of the dielectric layer below the second semiconductor layer at the uppermost layer can be increased by increasing the number of layers of the second semiconductor layers. For this reason, while suppressing deterioration of the crystallinity and purity of the second semiconductor layers, the breakdown strength of the BOX layers and the back-channel threshold breakdown strength can be secured, and higher breakdown voltages of field effect transistors can be achieved.

Also, a method for manufacturing a semiconductor substrate in accordance with an embodiment of the present invention is characterized in that the first semiconductor layer has a film thickness that is substantially equal to the sum of a downwardly increased portion of film thickness of the second semiconductor layer immediately above the first semiconductor layer caused by thermal oxidation and an upwardly increased portion of film thickness of the second semiconductor layer immediately below the first semiconductor layer caused by thermal oxidation.

By this, an increase in the film thickness of the second semiconductor layer by thermal oxidation can be absorbed by a gap of the void section, and the void section can be completely closed with the dielectric layer. For this reason, stress on the dielectric layer can be suppressed, an increase in the thermal resistance can be suppressed, deterioration of the crystallinity of the second semiconductor layer on the dielectric layer can be suppressed, and the heat dissipation property of the second semiconductor layer can be improved.

Moreover, a method for manufacturing a semiconductor substrate in accordance with an embodiment of the present invention is characterized in that the first semiconductor layer has a film thickness that is smaller than the sum of a downwardly increased portion of film thickness of the second semiconductor layer immediately above the first semiconductor layer caused by thermal oxidation and an upwardly increased portion of film thickness of the second semiconductor layer immediately below the first semiconductor layer caused by thermal oxidation.

By this, an increase in the film thickness of the semiconductor layer by thermal oxidation can be made greater than a gap of the void section, such that the second semiconductor layer at an upper layer can be lifted up at the time of thermal oxidation of the second semiconductor layer at a lower layer. For this reason, the height of the second semiconductor layer can be adjusted, and the flatness of the second semiconductor layer can be improved.

Furthermore, a method for manufacturing a semiconductor substrate in accordance with an embodiment of the present invention is characterized in that the first semiconductor layer has a film thickness that is greater than the sum of a downwardly increased portion of film thickness of the second semiconductor layer immediately above the first semiconductor layer caused by thermal oxidation and an upwardly increased portion of film thickness of the second semiconductor layer immediately below the first semiconductor layer caused by thermal oxidation.

By this, an increase in the film thickness of the second semiconductor layer by thermal oxidation can be absorbed by a gap of the void section. For this reason, stress on the dielectric layer can be suppressed, and deterioration of the crystallinity of the second semiconductor layer on the dielectric layer can be suppressed.

Also, a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention is characterized in comprising: a step of forming, on a semiconductor substrate, a first laminated layered structure composed of a second semiconductor layer having a smaller selection ratio at etching than a first semiconductor layer, laminated on the first semiconductor layer; a step of forming a step difference in a part of an area of the first laminated layered structure by selectively half-etching the second semiconductor layer at the uppermost layer; a step of forming, in a portion at the step difference of the first laminated layered structure, a second laminated layered structure composed of a fourth semiconductor layer having a smaller selection ratio at etching than a third semiconductor layer, laminated on the third semiconductor layer, in a manner that the third semiconductor layer is set to have a film thickness equal to a film thickness of the first semiconductor layer; a step of forming a first groove that penetrates the first semiconductor layer through the fourth semiconductor layer and exposes the semiconductor base; a step of forming a supporting body for supporting the second and fourth semiconductor layers on the semiconductor base on side walls of the first semiconductor layer through the fourth semiconductor layer in the first groove; a step of forming, in a first area divided by the first groove, a second groove that exposes at least a part of the first semiconductor layer through the second semiconductor layer; a step of forming, in a second area divided by the first groove, a third groove that exposes at least a part of the third semiconductor layer through the fourth semiconductor layer; a step of forming void sections under the second and fourth semiconductor layers by selectively etching the first and third semiconductor layers through the second groove and the third groove; a step of forming dielectric layers disposed below the second and fourth semiconductor layers by thermally oxidizing the second and fourth semiconductor layers through the void sections; and a step of forming semiconductor elements for mutually different usages at the second and fourth semiconductor layers, respectively.

By this, the second and fourth semiconductor layers can be supported on the semiconductor base through the supporting body formed in the first groove, the heights of the first and third semiconductor layers that are exposed through the second and fourth semiconductor layers, respectively, can be made different from each other in the first area and the second area, and etching gas or etching liquid can be brought in contact with the first and third semiconductor layers through the second groove and the third groove.

For this reason, the second and fourth semiconductor layers can be stably supported on the semiconductor base, the first and third semiconductor layers disposed below the second and fourth semiconductor layers, respectively, can be removed, and the heights of the first and third semiconductor layers that are removed from below the second and fourth semiconductor layers, respectively, can be made different from each other in the first area and the second area. Also, by setting the film thickness of the third semiconductor layer to be equal to the film thickness of the first semiconductor layer, increases in the heights in the first area and the second area can be made coincide with each other, even when the film thickness of the second and fourth semiconductor layers increases by thermal oxidation.

As a result, the heights of dielectric layers to be formed by thermal oxidation after the first and third semiconductor layers are removed can be made different in the first area and the second area, and the film thicknesses of the semiconductor layers in the first area and the second area can be made mutually different, and the flatness of the surface between the second and fourth semiconductor layers can be improved.

Also, a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention is characterized in comprising: a step of forming, on a semiconductor substrate, a first laminated layered structure composed of a second semiconductor layer having a smaller selection ratio at etching than a first semiconductor layer, laminated on the first semiconductor layer; a step of forming, in a portion of an area of the first laminated layered structure, a second laminated layered structure composed of a fourth semiconductor layer having a smaller selection ratio at etching than a third semiconductor layer, laminated on the third semiconductor layer, in a manner that the third semiconductor layer is set to have a film thickness greater than a film thickness of the first semiconductor layer; a step of forming a first groove that penetrates the first semiconductor layer through the fourth semiconductor layer and exposes the semiconductor base; a step of forming a supporting body for supporting the second and fourth semiconductor layers on the semiconductor base on side walls of the first semiconductor layer through the fourth semiconductor layer in the first groove; a step of forming, in a first area divided by the first groove, a second groove that exposes at least a part of the first semiconductor layer through the second semiconductor layer; a step of forming, in a second area divided by the first groove, a third groove that exposes at least a part of the third semiconductor layer through the fourth semiconductor layer; a step of forming void sections under the second and fourth semiconductor layers by selectively etching the first and third semiconductor layers through the second groove and the third groove; a step of forming dielectric layers disposed below the second and fourth semiconductor layers by thermally oxidizing the second and fourth semiconductor layers through the void sections; and a step of forming semiconductor elements for mutually different usages at the second and fourth semiconductor layers, respectively.

By this, while leaving the first semiconductor layer remained in the second area, the first semiconductor layer in the first area can be removed, and the third semiconductor layer in the second area can be removed. For this reason, by appropriately adjusting the film thicknesses and the number of layers of the first and third semiconductor layers, the film thicknesses of the dielectric layers below the second semiconductor layer and the fourth semiconductor layer can be made different from one another. Also, by making the film thicknesses of the second semiconductor layer and the fourth semiconductor layer different from each other, the film thicknesses of the semiconductor layers on the dielectric layers can be made different from each other. Further, by setting the film thickness of the third semiconductor layer to be greater than the film thickness of the first semiconductor layer, the height of the first area can be made elevated compared to the second area, based on increases in the film thickness of the second and fourth semiconductor layers. For this reason, the flatness of the surface of the semiconductor layer can be improved, and the film thicknesses of both of the dielectric layers and the semiconductor layers can be made different from one another.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A semiconductor device and a method for manufacturing the same in accordance with embodiments of the present invention are described below with reference to the accompanying drawings.

FIG. 1-FIG.8are plan views and cross-sectional views showing a method for manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Referring toFIGS. 1(a)-1(c), first single crystal semiconductor layers12a-12cand second single crystal semiconductor layers13a-13care alternately laminated on a semiconductor substrate11. It is noted that, for example, Si, Ge, SiGe, GaAs, InP, GaP, GaN, SiC and the like can be used as materials for the semiconductor substrate11, the first single crystal semiconductor layers12a-12c, and the second single crystal semiconductor layers13a-13c.

It is noted here that the first single crystal semiconductor layers12a-12ccan use materials having a selection ratio at etching greater than that of the semiconductor substrate11and the second single crystal semiconductor layers13a-13c. In particular, when the semiconductor substrate11consists of Si, SiGe may preferably be used as the first single crystal semiconductor layers12a-12c, and Si for the second single crystal semiconductor layers12a-13c. By this, lattice matching can be achieved among the first single crystal semiconductor layers12a-12cand the second single crystal semiconductor layers13a-13c, and selection ratios can be secured among the first single crystal semiconductor layers12a-12cand the second single crystal semiconductor layers13a-13c.

Then, the second single crystal semiconductor layer13cis thermally oxidized to thereby form a sacrificial oxide film14on a surface of the second single crystal semiconductor layer13c. Then, an oxidation prevention film15is formed on the entire surface of the sacrificial oxide film14by a CVD method or the like. It is noted that, for example, a silicon nitride film can be used as the oxidation prevention film15.

Next, as shown inFIGS. 2(a)-2(c), by using a photolithography technique and an etching technique, the oxidation prevention film15, the sacrificial oxide film14, the first single crystal semiconductor layers12a-12cand the second single crystal semiconductor layers13a-13care patterned, to thereby form grooves M1that expose the semiconductor substrate11in a predetermined direction.

It is noted that, when the semiconductor substrate11is exposed, etching may be stopped at the surface of the semiconductor substrate11, or recessed portions may be formed in the semiconductor substrate11by over-etching the semiconductor substrate11. Also, arrangement positions of the grooves M1may be made to correspond to a part of element isolation regions.

Next, as shown inFIGS. 3(a)-3(b).3, supporting bodies16, that are formed in films on side walls of the first single crystal semiconductor layers12a-12cand the second single crystal semiconductor layers13a-13c, and supports the second single crystal semiconductor layers13a-13con the semiconductor substrate11, are formed in the grooves M1. It is noted that, when forming the supporting body16in a film on the side walls of the first single crystal semiconductor layers12a-12cand the second single crystal semiconductor layers13a-13c, epitaxial growth of semiconductor can be used. It is noted here that, by using the epitaxial growth of semiconductor, the supporting body16can be selectively formed on the side surfaces of the first single crystal semiconductor layers12a-12cand the second single crystal semiconductor layers13a-13cand the surface of the semiconductor substrate11. It is noted that, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe or the like can be used as a material for the supporting body16. In particular, when the semiconductor substrate11and the second single crystal semiconductor layers13a-13cconsist of Si, and the first single crystal semiconductor layers12a-12cconsist of SiGe, Si may preferably be used as a material of the supporting body16.

By this, lattice matching can be made among the supporting body16and the first single crystal semiconductor layers12a-12c, and selection ratios can be secured among the supporting body16and the first single crystal semiconductor layers12a-12c. Also, by using semiconductor such as Si as a material of the supporting body16, the three-dimensional cubic structure by the semiconductor can be maintained, even when the first single crystal semiconductor layers12a-12care removed. For this reason, the chemical resistance property and mechanical stress resistance property can be improved, such that a stable element isolation process with good reproducibility can be realized. It is noted that, besides semiconductors, a dielectric such as a silicon oxide film may be used as the material of the supporting body16.

Next, as shown inFIGS. 4(a)-4(c), the oxidation prevention film15, the sacrificial oxide film14, the first single crystal semiconductor layers12a-12cand the second single crystal semiconductor layers13a-13care patterned by using a photolithography technique and an etching technique, whereby grooves M2that expose the semiconductor substrate11are formed along a direction orthogonal to the grooves M1. It is noted that, when the semiconductor substrate11is exposed, etching may be stopped at the surface of the semiconductor substrate11, or recessed sections may be formed in the semiconductor substrate11by over-etching the semiconductor substrate11. Also, arrangement positions of the grooves M2may be made to correspond to the element isolation regions.

Next, as shown inFIGS. 5(a)-5(c), etching gas or etching liquid is brought in contact with the first single crystal semiconductor layers12a-12cthrough the grooves M2, whereby the first single crystal semiconductor layers12a-12care removed by etching. Then, void sections17are formed between the semiconductor substrate11and the second single crystal semiconductor layer13a, and between the second single crystal semiconductor layers13aand13b, and13band13c.

It is noted here that, by providing the supporting bodies16in the grooves M1, the second single crystal semiconductor layers13a-13ccan be supported on the semiconductor substrate11even when the first single crystal semiconductor layers12a-12care removed; and by providing the grooves M2independently of the grooves M1, etching gas or etching liquid can be brought in contact with the first single crystal semiconductor layers12a-12cdisposed under the second single crystal semiconductor layers13a-13c, respectively. For this reason, the void sections17can be formed between the semiconductor substrate11and the second single crystal semiconductor layer13a, and among the second single crystal semiconductor layers13athrough13c, without damaging the crystal quality of the second single crystal semiconductor layers13a-13c.

It is noted that, when the semiconductor substrate11, the second single crystal semiconductor layers13a-13cand the supporting body16consist of Si, and the first single crystal semiconductor layers12a-12cconsist of SiGe, it is desirable to use nitric-hydrofluoric acid as an etching liquid for the first single crystal semiconductor layers12a-12c. By this, a selection ratio between Si and SiGe that ranges from about 1:1000 to 1:10000 can be obtained, such that the first single crystal semiconductor layers12a-12ccan be removed while suppressing over-etching of the semiconductor substrate11, the second single crystal semiconductor layers13a-13cand the supporting body16.

Next, as shown inFIGS. 6(a)-6(c), the semiconductor substrate11, the second single crystal semiconductor layers13a-13cand the supporting body16are thermally oxidized until the second single crystal semiconductor layers13aand13bdisappear, thereby forming dielectric layers18under the second single crystal semiconductor layer13c. It is noted here that, by having the second single crystal semiconductor layers13aand13bdisappear, gaps between the second single crystal semiconductor layer13cand the semiconductor substrate11can be completely embedded with the dielectric layers18.

Then, by appropriately adjusting the film thickness and/or the number of layers of the first single crystal semiconductor layers12a-12cand the second single crystal semiconductor layers13a-13c, the film thicknesses of the second single crystal semiconductor layer13cand the dielectric layer18can be adjusted.

However, as shown inFIGS. 7(a)-7(b), the film thickness T3of the first single crystal semiconductor layer12bbetween the second single crystal semiconductor layers13aand13bthat are set to film thicknesses T1and T2, respectively, may preferably be set to a value of about ΔT1/2+ΔT2/2, where ΔT1/2 and ΔT2/2 are increases in the film thickness of the second single crystal semiconductor layers13aand13b, respectively. By this, a gap of the void section17that is created when the first single crystal semiconductor layer12bis removed can be made to correspond to increases in the film thickness due to oxidation of the second single crystal semiconductor layers13aand13b. For this reason, stress on the dielectric layer18can be suppressed, the void section17can be completely filled with the dielectric layer18, and the dielectric layer18can be prevented from bulging due to oxidation of the second single crystal semiconductor layers13aand13b. For this reason, while an increase in the thermal resistance can be suppressed, deterioration of the crystallinity of the second single crystal semiconductor layer13con the dielectric layer18can be suppressed, and the flatness of the second single crystal semiconductor layer13ccan be maintained. Also, the width of each of the grooves M1and M2may preferably be set to be greater than expansions by thermal oxidation from two sides in a transverse direction of the second single crystal semiconductor layers13a-13c.

Also, the film thickness of the second single crystal semiconductor layer13cafter element isolation can be defined by the film thickness of the second single crystal semiconductor layer13cat the time of epitaxial growth and the film thickness of the dielectric layer18formed at the time of thermal oxidation of the second single crystal semiconductor layers13a-13c. For this reason, the film thickness of the second single crystal semiconductor layer13ccan be accurately controlled, differences in the film thickness of the second single crystal semiconductor layer13ccan be reduced, and the film thickness of the second single crystal semiconductor layer13ccan be made smaller. Also, by providing the oxidation prevention film15over the second single crystal semiconductor layer13c, the surface of the second single crystal semiconductor layer13ccan be prevented from being thermally oxidized, and the dielectric layer18can be formed under the second single crystal semiconductor layer13c.

Also, instead of providing the oxidation prevention film15on the second single crystal semiconductor layer13c, the film thickness of the second single crystal semiconductor layer13cmay be set greater than the film thickness of the second single crystal semiconductor layers13aand13b. By this, even when the second single crystal semiconductor layers13aand13bare completely thermally oxidized, the second single crystal semiconductor layer13cat the uppermost layer can be prevented from completely disappearing by thermal oxidation, and the second single crystal semiconductor layer13ccan be disposed on the dielectric layer18.

After the dielectric layer18is formed, high-temperature annealing is conducted. By this, the dielectric layer18can be re-flowed, stress on the dielectric layer18can be alleviated, and the interface state can be reduced.

Next, as shown inFIGS. 8(a)-8(c), by using a CVD method or the like, a dielectric layer is deposited on the second single crystal semiconductor layer in a manner that the grooves M1and M2with the dielectric layer18formed on their side walls are embedded. Then, by using a CMP (chemical mechanical polishing) method or the like, the dielectric layer is planarized, thereby exposing the surface of the second single crystal semiconductor layer, and forming embedded dielectric layers10in the grooves M1and M2. It is noted that, for example, SiO2or Si3N4 may be used as the embedded dielectric layers19. Then, field effect transistors may be formed in the second single crystal semiconductor layer13c. By this, PN junction leakage at the field effect transistors can be suppressed, element isolation around and bottom surfaces of the field effect transistors can be achieved, characteristics of the field effect transistors can be improved, and the reliability of the field effect transistors can be improved.

FIG. 9-FIG.22are plan views and cross-sectional views showing a method for manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

Referring toFIGS. 9(a)-9(b) andFIGS. 10(a)-10(b), first single crystal semiconductor layers32a-32cand second single crystal semiconductor layers33a-33care alternately laminated on a semiconductor substrate31. It is noted here that the first single crystal semiconductor layers32a-32ccan use materials having a selection ratio at etching greater than that of the semiconductor substrate31and the second single crystal semiconductor layers33a-33c. In particular, when the semiconductor substrate31consists of Si, SiGe may preferably be used as the first single crystal semiconductor layers32a-32c, and Si for the second single crystal semiconductor layers33a-33c.

It is noted that a thick film semiconductor region R1and a thin film semiconductor region R2can be provided in the semiconductor substrate31. Then, a partially depleted type field effect transistor may be formed in the thick film semiconductor region R1, and a completely depleted type field effect transistor can be formed in the thin film semiconductor region R2.

Then, the second single crystal semiconductor layer33cis thermally oxidized to thereby form a sacrificial oxide film34on a surface of the second single crystal semiconductor layer33c. Then, an oxidation prevention film35is formed on the entire surface of the sacrificial oxide film34by a CVD method of the like. It is noted that, for example, a silicon nitride film can be used as the oxidation prevention film35. Then, by using a photolithography technique and an etching technique, the sacrificial oxide film34and the oxidation prevention film35are patterned, to thereby remove the sacrificial oxide film34and the oxidation prevention film35in the thin film semiconductor region R2, and expose the second single crystal semiconductor layer33cin the thin film semiconductor region R2. Further, by using the sacrificial oxide film34and the oxidation prevention film35as a mask, the second single crystal semiconductor layer33cis half-etched to form a step difference D in the second single crystal semiconductor layer33c, such that the second single crystal semiconductor layer33cin the thick film semiconductor region R1becomes higher by the step difference D than the height of the second single crystal semiconductor layer33cin the thin film semiconductor region R2.

Then, by using the sacrificial oxide film34and the oxidation prevention film35as a mask, epitaxial growth is conducted, whereby a first single crystal semiconductor layer32dand a second single crystal semiconductor layer33dare selectively formed on the second single crystal semiconductor layer33cin the thin film semiconductor region R2. It is noted here that the first single crystal semiconductor layer32dcan use a material having a selection ratio at etching greater than that of the second single crystal semiconductor layer33d. In particular, when the semiconductor substrate31consists of Si, SiGe may preferably be used as the first single crystal semiconductor layer32d, and Si for the second single crystal semiconductor layer33d.

Next, as shown inFIGS. 11(a)-11(b) andFIGS. 12(a)-12(b), the sacrificial oxide film34and the oxidation prevention film35in the thick film semiconductor region R1are removed. Then by using a photolithography technique and an etching technique, the first single crystal semiconductor layers32a-32dand the second single crystal semiconductor layers33a-33dare patterned, thereby forming grooves M11that expose the semiconductor substrate31along a predetermined direction.

It is noted that, when the semiconductor substrate31is exposed, etching may be stopped at the surface of the semiconductor substrate31, or recessed sections may be formed in the semiconductor substrate31by over-etching the semiconductor substrate31. Also, arrangement positions of the grooves M11may be made to correspond to a part of element isolation regions that isolate the thick film semiconductor region R1and the thin film semiconductor region R2from each other.

Next, as shown inFIGS. 13(a)-13(b) andFIGS. 14(a)-14(b), a supporting body36, that is formed in a film on side walls of the first single crystal semiconductor layers32a-32dand the second single crystal semiconductor layers33a-33d, and supports the second single crystal semiconductor layers33a-33don the semiconductor substrate31, is formed in the grooves M1. It is noted that, when forming the supporting body16in a film on the side walls of the first single crystal semiconductor layers32a-32dand the second single crystal semiconductor layers33a-33d, epitaxial growth of semiconductor can be used. It is noted that, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe or the like can be used as a material for the supporting body36. In particular, when the semiconductor substrate31and the second single crystal semiconductor layers33a-33dconsist of Si, and the first single crystal semiconductor layers32a-32dconsist of SiGe, Si may preferably be used as a material of the supporting body36.

Next, as shown inFIGS. 15(a)-15(b) andFIGS. 16(a)-16(b), by using a photolithography technique and an etching technique, the first single crystal semiconductor layers32a-32c, the second single crystal semiconductor layers33a-33cand the supporting body36are patterned, thereby forming grooves M12that expose the semiconductor substrate31along a direction orthogonal to the grooves M11in the thick film semiconductor region R1. It is noted that, when the semiconductor substrate31is exposed, etching may be stopped at the surface of the semiconductor substrate31, or recessed portions may be formed in the semiconductor substrate31by over-etching the semiconductor substrate31. Also, arrangement positions of the grooves M12may be made to correspond to element isolation regions of the single crystal semiconductor layer33c.

Next, as shown inFIGS. 17(a)-17(b) andFIGS. 18(a)-18(b), by using a photolithography technique and an etching technique, the first single crystal semiconductor layer32d, the second single crystal semiconductor layer33dand the supporting body36are patterned, thereby forming grooves M13that expose the second single crystal semiconductor layer33calong a direction orthogonal to the grooves M11in the thin film semiconductor region R2. It is noted that, when the second single crystal semiconductor layer33cis exposed, etching may be stopped at the surface of the second single crystal semiconductor layer33c, or recessed portions may be formed in the second single crystal semiconductor layer33cby over-etching the second single crystal semiconductor layer33c. Also, arrangement positions of the grooves M13may be made to correspond to element isolation regions of the single crystal semiconductor layer33c.

Also, instead of exposing the surface of the second single crystal semiconductor layer33c, etching may be stopped at the surface of the first single crystal semiconductor layer32d; or the first single crystal semiconductor layer32dmay be over-etched and etching may be conducted halfway through the first single crystal semiconductor layer32d. It is noted that, by stopping the etching of the first single crystal semiconductor layer32dhalfway through, the surface of the second single crystal semiconductor layer32din the grooves M13can be prevented from being exposed. For this reason, when the first single crystal semiconductor layer32dis removed by etching, the time during which the second single crystal semiconductor layer33cwithin the grooves M3is exposed to etching liquid or etching gas can be reduced, such that over-etching of the second single crystal semiconductor layer33cwithin the grooves M3can be suppressed.

Next, as shown inFIGS. 19(a)-19(b) andFIGS. 20(a)-20(b), etching gas or etching liquid is brought in contact with the first single crystal semiconductor layers32a-32cthrough the grooves M12, and etching gas or etching liquid is brought in contact with the first single crystal semiconductor layer32dthrough the grooves M13, whereby the first single crystal semiconductor layers32a-32cin the thick film semiconductor region R1are removed by etching, and the first single crystal semiconductor layer32din the thin film semiconductor region R2is removed by etching.

Further, in the thick film semiconductor region R1, void sections37are formed between the semiconductor substrate31and the second single crystal semiconductor layer33a, and between the second single crystal semiconductor layers33aand33b, and33band33c; and in the thin film semiconductor region R2, void sections37are formed between the second single crystal semiconductor layers33cand33d.

It is noted here that, in the thin film semiconductor region R2, the depth of the grooves M13may be set such that the second single crystal semiconductor layer33cremains on the first single crystal semiconductor layer32c, whereby the first single crystal semiconductor layers32a-32cin the thick film semiconductor region R1can be removed, while leaving the first single crystal semiconductor layers32a-32cremained in the thin film semiconductor region R2. For this reason, in the thick film semiconductor region R1, the second single crystal semiconductor layers33aand33bamong the first single crystal semiconductor layers32athrough32ccan be thermally oxidized; and in the thin film semiconductor region R2, the second single crystal semiconductor layers33aand33bamong the first single crystal semiconductor layers32athrough32ccan be prevented from being oxidized, and the second single crystal semiconductor layer33ddisposed in a layer above the second single crystal semiconductor layer33bcan be thermally oxidized. As a result, the height of a dielectric layer38that is formed by thermal oxidation of the second single crystal semiconductor layers33a-33dcan be made different in the thick film semiconductor region R1and the thin film semiconductor region R2, and the number of layers of the second single crystal semiconductor layers33a-33dthat are thermally oxidized can be made different in the thick film semiconductor region R1and the thin film semiconductor region R2. Accordingly, in the thick film semiconductor region R1and the thin film semiconductor region R2, the film thickness of the second single crystal semiconductor layers33cand33dat the uppermost layer can be made different, and the film thickness of the dielectric layer38disposed immediately below the second single crystal semiconductor layers33cand33dat the uppermost layer can be made different.

Next, as shown inFIGS. 21(a)-21(b) andFIGS. 22(a)-22(b), the semiconductor substrate31, the second single crystal semiconductor layers33a-33dand the supporting body36are thermally oxidized until the second single crystal semiconductor layers33aand33bin the thick film semiconductor region R1disappear, thereby forming dielectric layers38under the second single crystal semiconductor layer33cin the thick film semiconductor region R1and under the second single crystal semiconductor layer33din the thin film semiconductor region R2. It is noted here that, by completely thermally oxidizing the second single crystal semiconductor layers33aand33bin the thick film semiconductor region R1, the film thickness of the dielectric layer38below the second single crystal semiconductor layer33cin the thick film semiconductor region R1can be increased. For example, by setting the film thickness of each of the second single crystal semiconductor layers33aand33bto be at 45 nm, and by conducting an oxidation process such that the second single crystal semiconductor layers33aand33bbecome to be 50 nm on one side, the second single crystal semiconductor layers33aand33bcan be completely thermally oxidized, and an oxide film of 100 nm thick can be formed with the second single crystal semiconductor layers33aand33bon both sides. For this reason, deterioration of the crystallinity and purity of the second single crystal semiconductor layer33ccan be suppressed, the breakdown strength and back-channel threshold breakdown strength of the dielectric layer38in the thick film semiconductor region R1can be secured, and higher breakdown voltages of field effect transistors to be formed in the thick film semiconductor region R1can be achieved.

Further, the film thickness and the number of layers of the first single crystal semiconductor layers32a-32cand the second single crystal semiconductor layers33aand33bcan be set such that increases in the film thickness of the second single crystal semiconductor layers33aand33bare absorbed by the void sections37, when the second single crystal semiconductor layers33aand33bare completely thermally oxidized. By this, deterioration of the crystallinity of the second single crystal semiconductor layer33con the dielectric layer38can be suppressed, and the heights of the surfaces of the second single crystal semiconductor layer33cin the thick film semiconductor region R1and the second single crystal semiconductor layer33din the thin film semiconductor region R2can be matched with each other, and the flatness in the surface between the second single crystal semiconductor layer33cin the thick film semiconductor region R1and the second single crystal semiconductor layer33din the thin film semiconductor region R2can be improved.

For example, let us assume that film thicknesses TA1-TA4of the first single crystal semiconductor layers32a-32dare set to the same value of 55 nm, film thicknesses TB1and TB2of the second single crystal semiconductor layers33aand33bare set to the same value of 45 nm, and an oxidation processing is conducted such that the film thickness of an oxide film on one side of the second single crystal semiconductor layers33aand33bbecomes to be 50 nm. In this case, in the thick film semiconductor region R1, the film thickness of the dielectric layer38under the second single crystal semiconductor layer33cin the thick film semiconductor region R1can be made to 300 nm, and the film thickness of the dielectric layer38under the second single crystal semiconductor layer33din the thin film semiconductor region R2can be made to 100 nm.

Also, by setting the film thickness TB3of the second single crystal semiconductor layer33cat 345 nm, and the film thickness TB4of the second single crystal semiconductor layer33dat 75 nm, the film thickness of the second single crystal semiconductor layer33con the dielectric layer38can be set to 300 nm in the thick film semiconductor region R1, and the film thickness of the second single crystal semiconductor layer33don the dielectric layer38can be set to 30 nm in the thin film semiconductor region R2.

In this manner, by appropriately adjusting the film thickness and the number of layers of the first single crystal semiconductor layers32a-32dand the second single crystal semiconductor layers33a-33d, the flatness of their surface can be secured, and various combinations of semiconductor layers and BOX layers in various film thicknesses can be realized.

It is noted here that, in the thin film semiconductor region R2, by disposing the second single crystal semiconductor layer33don the dielectric layer38, when the effective channel length of a high-speed/lower power semiconductor element is 0.1 μm or less, the film thickness of the second single crystal semiconductor layer33dcan be made to 50 nm or less, whereby a completely depleted type SOI transistor in which the short-channel effect is suppressed can be formed.

Also, in the thick film semiconductor region R1, by disposing the second single crystal semiconductor layer33con the dielectric layer38, the film thickness of the second single crystal semiconductor layer33con the dielectric layer38can be increased. For this reason, a partially depleted type SOI transistor can be formed, while a high junction breakdown strength and a large current capacity can be secured.

FIG. 23-FIG.37are plan views and cross-sectional views showing a method for manufacturing a semiconductor device in accordance with a third embodiment of the present invention.

Referring toFIGS. 23(a)-23(b) andFIGS. 24(a)-24(b), first single crystal semiconductor layers52a-52cand second single crystal semiconductor layers53a-53care alternately laminated on a semiconductor substrate51. It is noted here that the first single crystal semiconductor layers52a-52ccan use materials having a selection ratio at etching greater than that of the semiconductor substrate51and the second single crystal semiconductor layers53a-53c. In particular, when the semiconductor substrate51consists of Si, SiGe may preferably be used as the first single crystal semiconductor layers52a-52c, and Si for the second single crystal semiconductor layers53a-53c.

It is noted that a thick film semiconductor region R11and a thin film semiconductor region R12can be provided in the semiconductor substrate51. Then, a partially depleted type field effect transistor may be formed in the thick film semiconductor region R11, and a completely depleted type field effect transistor can be formed in the thin film semiconductor region R12.

Then, the second single crystal semiconductor layer53cis thermally oxidized to thereby form a sacrificial oxide film54on a surface of the second single crystal semiconductor layer53c. Then, an oxidation prevention film55is formed on the entire surface of the sacrificial oxide film54by a CVD method of the like. Then, by using a photolithography technique and an etching technique, the sacrificial oxide film54and the oxidation prevention film55are patterned, to thereby remove the sacrificial oxide film54and the oxidation prevention film55in the thin film semiconductor region R12, and expose the second single crystal semiconductor layer53cin the thin film semiconductor region R12.

Then, by using the sacrificial oxide film54and the oxidation prevention film55as a mask, epitaxial growth is conducted, whereby a first single crystal semiconductor layer52dand a second single crystal semiconductor layer53dare selectively formed on the second single crystal semiconductor layer53cin the thin film semiconductor region R12. It is noted here that the first single crystal semiconductor layer52dcan use a material having a selection ratio at etching greater than that of the second single crystal semiconductor layer53d. In particular, when the semiconductor substrate51consists of Si, SiGe may preferably be used as the first single crystal semiconductor layer52d, and Si for the second single crystal semiconductor layer53d.

Next, as shown inFIGS. 25(a)-25(b) andFIGS. 26(a)-26(b), the sacrificial oxide film54and the oxidation prevention film55in the thick film semiconductor region R1are removed. Then by using a photolithography technique and an etching technique, the first single crystal semiconductor layers52a-52dand the second single crystal semiconductor layers53a-53dare patterned, thereby forming grooves M21that expose the semiconductor substrate51along a predetermined direction.

Next, as shown inFIGS. 27(a)-27(b) andFIGS. 28(a)-28(b), a supporting body56, that is formed in a film on side walls of the first single crystal semiconductor layers52a-52dand the second single crystal semiconductor layers53a-53d, and supports the second single crystal semiconductor layers53a-53don the semiconductor substrate51, is formed in the grooves M21. It is noted that, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe or the like can be used as a material for the supporting body56. In particular, when the semiconductor substrate51and the second single crystal semiconductor layers53a-53dconsist of Si, and the first single crystal semiconductor layers52a-52dconsist of SiGe, Si may preferably be used as a material of the supporting body56.

Next, as shown inFIGS. 29(a)-29(b) andFIGS. 30(a)-30(b), by using a photolithography technique and an etching technique, the first single crystal semiconductor layers52a-52c, the second single crystal semiconductor layers53a-53cand the supporting body56are patterned, thereby forming grooves M22that expose the semiconductor substrate51along a direction orthogonal to the grooves M21in the thick film semiconductor region R11.

Next, as shown inFIGS. 31(a)-31(b) andFIGS. 32(a)-32(b), by using a photolithography technique and an etching technique, the first single crystal semiconductor layers52d, the second single crystal semiconductor layer53dand the supporting body56are patterned, thereby forming grooves M23that expose the second single crystal semiconductor layer53calong a direction orthogonal to the grooves M21in the thin film semiconductor region R12.

Next, as shown inFIGS. 33(a)-33(b) andFIGS. 34(a)-34(b), etching gas or etching liquid is brought in contact with the first single crystal semiconductor layers52a-52cthrough the grooves M22, and etching gas or etching liquid is brought in contact with the first single crystal semiconductor layer52dthrough the grooves M23, whereby the first single crystal semiconductor layers52a-52cin the thick film semiconductor region R11are removed by etching, and the first single crystal semiconductor layer52din the thin film semiconductor region R12is removed by etching. Further, in the thick film semiconductor region R11, void sections57are formed between the semiconductor substrate51and the second single crystal semiconductor layer53a, and between the second single crystal semiconductor layers53aand53b, and53band53c; and in the thin film semiconductor region R12, void sections57are formed between the second single crystal semiconductor layers53cand53d.

It is noted here that, in the thin film semiconductor region R12, the depth of the grooves M23may be set such that the second single crystal semiconductor layer53cremains on the first single crystal semiconductor layer52c, whereby the first single crystal semiconductor layers52a-52cin the thick film semiconductor region R11can be removed, while leaving the first single crystal semiconductor layers52a-52cremained in the thin film semiconductor region R12. For this reason, in the thick film semiconductor region R11, the second single crystal semiconductor layers53aand53bamong the first single crystal semiconductor layers52athrough52ccan be thermally oxidized; and in the thin film semiconductor region R12, the second single crystal semiconductor layers53aand53bamong the first single crystal semiconductor layers52athrough52ccan be prevented from being oxidized, and the second single crystal semiconductor layer53ddisposed in a layer above the second single crystal semiconductor layer53bcan be thermally oxidized. As a result, the height of a dielectric layer58that is formed by thermal oxidation of the second single crystal semiconductor layers53a-53dcan be made different in the thick film semiconductor region R11and the thin film semiconductor region R12, and the number of layers of the second single crystal semiconductor layers53a-53dthat are thermally oxidized can be made different in the thick film semiconductor region R11and the thin film semiconductor region R12. Accordingly, in the thick film semiconductor region R11and the thin film semiconductor region R12, the film thickness of the second single crystal semiconductor layers53cand53dat the uppermost layer can be made different, and the film thickness of the dielectric layer58disposed immediately below the second single crystal semiconductor layers53cand53dat the uppermost layer can be made different.

Next, as shown inFIGS. 35(a)-35(b) andFIGS. 36(a)-36(b), the semiconductor substrate51, the second single crystal semiconductor layers53a-53dand the supporting body56are thermally oxidized until the second single crystal semiconductor layers53aand53bin the thick film semiconductor region R11disappear, thereby forming dielectric layers58under the second single crystal semiconductor layer53cin the thick film semiconductor region R11and under the second single crystal semiconductor layer53din the thin film semiconductor region R12. It is noted here that, by completely thermally oxidizing the second single crystal semiconductor layers53aand53bin the thick film semiconductor region R11, the film thickness of the dielectric layer58below the second single crystal semiconductor layer53cin the thick film semiconductor region R11can be increased. For this reason, deterioration of the crystallinity and purity of the second single crystal semiconductor layer53ccan be suppressed, the breakdown strength and back-channel threshold breakdown strength of the dielectric layer58in the thick film semiconductor region R1can be secured, and higher breakdown voltages of field effect transistors to be formed in the thick film semiconductor region R11can be achieved.

Also, the film thickness and the number of layers of the first single crystal semiconductor layers52a-52cand the second single crystal semiconductor layers53aand53bcan be set such that increases in the film thickness of the second single crystal semiconductor layers53aand53bbecome greater than the void sections57, when the second single crystal semiconductor layers53aand53bare completely thermally oxidized. By this, by forming the dielectric layer58below the second single crystal semiconductor layer53c, the second single crystal semiconductor layer53cin the thick film semiconductor region R11can be lifted up. For this reason, the heights of the surfaces of the second single crystal semiconductor layer53cin the thick film semiconductor region R11and the second single crystal semiconductor layer53din the thin film semiconductor region R12can be matched with each other, and the flatness in the surface between the second single crystal semiconductor layer53cin the thick film semiconductor region R11and the second single crystal semiconductor layer53din the thin film semiconductor region R12can be improved.

For example, by setting the film thickness TA4of the first single crystal semiconductor layer52dto 55 nm, and the film thickness TB4of the second single crystal semiconductor layer53dto 75 nm, the film thickness of the second single crystal semiconductor layer53don the dielectric layer58can be set to 30 nm, and the film thickness of the dielectric layer58under the second single crystal semiconductor layer53dcan be set to 100 nm, as shown inFIG. 37(a), in the thin film semiconductor region R12. It is noted here that the height of the surface of the second single crystal semiconductor layer53dcan be made higher than the surface of the semiconductor substrate51before thermal oxidation by (TA1+TB1+TA2+TB2+TA3+TB3+85 nm).

On the other hand, in the thick film semiconductor region R11, an increase in the film thickness by thermal oxidation of the second single crystal semiconductor layers53a-53cequals to, as shown inFIG. 37(b), the sum of an amount of an increase (55 nm) in the film thickness between an upper surface of the semiconductor substrate51and a lower surface of the second single crystal semiconductor layer53aminus the film thickness of the first single crystal semiconductor layer52a(55 nm-TA1), an amount of an increase (55 nm) in the film thickness between an upper surface of the second single crystal semiconductor layer53aand a lower surface of the second single crystal semiconductor layer53bminus the film thickness of the first single crystal semiconductor layer52b(55 nm-TA2), an amount of an increase (55 nm) in the film thickness between an upper surface of the second single crystal semiconductor layer53band a lower surface of the second single crystal semiconductor layer53cminus the film thickness of the first single crystal semiconductor layer52c(55 nm-TA3), and an amount of a decrease (−22.5 nm) in the film thickness of the semiconductor layer by surface oxidation of the second single crystal semiconductor layer53c.

In this manner, by appropriately adjusting the film thickness and the number of layers of the first single crystal semiconductor layers52a-52dand the second single crystal semiconductor layers53a-53d, the flatness of their surface can be secured, and various combinations of semiconductor layers and BOX layers in various film thicknesses can be realized.