Metal-oxide-metal (MOM) capacitor with enhanced capacitance

A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure.

The present disclosure is generally related to metal-oxide-metal (MOM) capacitors in semiconductor devices.

II. DESCRIPTION OF RELATED ART

Advances in technology have resulted in smaller and more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular telephones and internet protocol (IP) telephones, can communicate voice and data packets over wireless networks. Also, such wireless telephones include electronic devices, such as a processor that can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these wireless telephones can include significant computing capabilities.

Electronic devices may include passive components, such as inductors, resistors, and capacitors, that are widely used in tuning, filtering, impedance matching, and gain control of integrated circuits (IC). Among various types of capacitors, metal-oxide-metal (MOM) capacitors are used in analog tuning circuits, switched capacitor circuits, filters, resonators, up-conversion and down-conversion mixers, and analog/digital (A/D) converters. A challenge of capacitors in such applications includes having the MOM capacitors provide a large capacitance value or maintain a level of capacitance while taking up a small surface area of the IC.

In a conventional metal-oxide-metal (MOM) capacitor formed using a complementary metal-oxide-semiconductor (CMOS) fabrication process, electrodes may include multiple metal layers formed on a substrate. A capacitance of the conventional MOM capacitor may be based on a capacitance of an adjacent pair of electrodes that includes capacitances between each metal layer of the adjacent pair of electrodes. One way to increase the capacitance of the conventional MOM capacitor without increasing a surface area (i.e., a “footprint”) of the conventional MOM capacitor is by including conductive gate material or contact metal in the electrodes. For example, by including the conductive gate material, an additional capacitance may be formed between the conductive gate material and a conductive gate material of an adjacent electrode. An additional capacitance may be similarly formed between two contact metal portions of adjacent electrodes. To further increase the capacitance of the conventional MOM capacitor, additional electrodes may be added. However, the surface area of the conventional MOM capacitor may be constrained by design rules associated with the CMOS fabrication process, which may prevent the conventional MOM capacitor from achieving a particular capacitance without an undesired increase in surface area.

A MOM capacitor formed in accordance with the present disclosure includes electrode pairs connected to a substrate to enable an enhanced capacitance, as compared to the conventional MOM capacitor. For example, a first electrode pair may include a first electrode and a second electrode both connected to (e.g., in contact with or “extending” to) the substrate, thus forming an additional capacitance as compared to MOM capacitors that include electrodes not “extending” to a substrate.

Further, materials of the first electrode and the second electrode may be selected so that a distance between the first electrode and the second electrode is substantially equal to a “minimum” permitted distance defined by one or more fabrication design rules (e.g., CMOS fabrication design rules). For example, according to design rules, a permitted distance between a conductive gate material and a contact metal may be less than a permitted distance between two adjacent contact metals or two adjacent conductive gate materials. Therefore, by including conductive gate material in the first electrode and including contact metal in the second electrode, the distance between the first electrode and the second electrode may be reduced, thus enabling higher density of electrode pairs of the MOM capacitor. Accordingly, reducing the distance between the first electrode and the second electrode may increase a capacitance of the MOM capacitor and enable reduced surface area of the MOM capacitor, which may enable a high capacitance of the MOM capacitor exceeding a particular surface area specified by a design of the MOM capacitor.

In a particular embodiment, a MOM capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure. The first metal structure is coupled to a first higher metal structure by use of a via structure.

In another particular embodiment, a method of forming a MOM capacitor device includes forming a first electrode. The first electrode includes a conductive gate material. The method further includes forming a second electrode. The second electrode includes a contact metal. The second electrode is proximate to the first electrode.

In another particular embodiment, a MOM capacitor device includes first means for enabling charge accumulation coupled to a substrate. The first means for enabling charge accumulation includes a conductive gate material. The MOM capacitor device further includes second means for enabling charge accumulation coupled to the substrate. The second means for enabling charge accumulation includes a contact metal. The second means for enabling charge accumulation are proximate to the first means for enabling charge accumulation.

In another particular embodiment, a non-transitory computer-readable medium includes processor-executable instructions that, when executed by a processor, cause the processor to initiate fabrication of a MOM capacitor device. The MOM capacitor device is fabricated by forming a first electrode. The first electrode includes a conductive gate material. The MOM capacitor device is further fabricated by forming a second electrode. The second electrode includes a contact metal. The second electrode is proximate to the first electrode.

One particular advantage provided by at least one of the disclosed embodiments is enhanced capacitance of a MOM capacitor as compared to a conventional MOM capacitor. For example, by including both conductive gate materials and contact metals in electrodes of the MOM capacitor, the capacitance of the MOM capacitor may be increased (e.g., a capacitance of the MOM capacitor includes a capacitance between the conductive gate materials and the contact metals). Further, because a distance between the conductive gate material and the contact metal (e.g., a gate-to-contact “pitch”) is less than a distance between two adjacent conductive gate materials (e.g., a gate-to-gate pitch) or a distance between two adjacent contact metals (e.g., a contact-to-contact pitch), alternating disposition of conductive gate materials and contact metals enables a reduced surface area of the MOM capacitor as compared to other configurations of conductive gate materials and contact metals. Additionally, the capacitance of the MOM capacitor is further enhanced based on the distance between the electrodes (e.g., the gate-to-contact pitch).

DETAILED DESCRIPTION

Referring toFIG. 1, a particular embodiment of a metal-oxide-metal (MOM) capacitor is depicted and generally designated100. The MOM capacitor100includes a first electrode140and a second electrode142, that are formed on a substrate102.

The first electrode140includes a conductive gate material104that is coupled to the substrate102. For example, the conductive gate material104may be coupled to the substrate102via an intervening gate dielectric layer103as depicted inFIG. 1. The first electrode140further includes a first metal structure106that includes the conductive gate material104. For example, the first metal structure106may be entirely formed of the conductive gate material104, or a lower portion of the first metal structure106may include the conductive gate material104while an upper portion of the first metal structure106(e.g., a “metal 0” layer local connection associated with a complementary metal-oxide-semiconductor (CMOS) design) may be formed of a different metal or material than the lower portion. The first metal structure106is coupled to a first higher metal structure110(e.g., a “metal 1” layer structure) through a first via structure108. To illustrate, the first higher metal structure110may include one or more metal lines in one or more upper metal layers of a semiconductor device.

The second electrode142includes a second metal structure112that is coupled to the substrate102. For example, as shown inFIG. 1, the second metal structure112includes a contact metal120that is coupled to the substrate102. The contact metal120may include a metal that is appropriate for use as a contact of a transistor, such as for a source contact or a drain contact of a transistor. In a particular embodiment, the conductive gate material104and the contact metal120are different materials. For example, the conductive gate material104may be a metal gate titanium nitride (TiN) film and the contact metal120may be tungsten. Using tungsten for the contact metal120may reduce copper diffusion into the substrate102. The second metal structure112may be formed entirely of the contact metal120or may have a lower portion formed of the contact metal120and an upper portion formed (e.g., a “metal 0” layer local connection) of another conductive material, such as copper. The second metal structure112is coupled to a second higher metal structure116(e.g., a “metal 1” layer structure) through a second via structure114. To illustrate, the second higher metal structure116may include one or more metal lines in one or more upper metal layers of the semiconductor device.

During operation, the first electrode140and the second electrode142may each be biased according to a corresponding voltage, and the first electrode140may conduct charge (e.g., the first electrode140and the second electrode142may correspond to conductive plates in a plate capacitor). A capacitance may exist between the first electrode140and the second electrode142. For example, the capacitance may include a capacitance C1based on a first capacitance between the first higher metal structure110and the second higher metal structure116, a second capacitance between the first via structure108and the second via structure114, and a third capacitance between at least a portion of the first metal structure106and at least a portion of the second metal structure112. The capacitance C1may correspond to a capacitance of a conventional MOM capacitor that does not include electrodes extending to the substrate102(e.g., electrodes including conductive gate material coupled to the substrate102or including contact metal coupled to the substrate102). The capacitance of the MOM capacitor100also includes a capacitance C2between the portion of the first metal structure106including the conductive gate material104and the portion of the second metal structure112including the contact metal120. Thus, because the first electrode140and the second electrode142are extended to the substrate102, the capacitance (e.g., C1and C2) of the MOM capacitor100is increased without increasing a footprint (e.g., a surface area) of the MOM capacitor100on the substrate102.

Further, because the first electrode140includes the conductive gate material104and the second electrode142includes the contact metal120, the MOM capacitor100has increased capacitance as compared to configurations where two adjacent electrodes each include conductive gate material or where two adjacent electrodes each include contact metal. To illustrate, the first metal structure106including the conductive gate material104and the second metal structure112including the contact metal120may be formed in accordance with conventional transistor fabrication processing. For example, the conductive gate material104and/or the gate dielectric layer103may be formed according to a conventional transistor gate formation process, and the contact metal120may be formed in accordance with a conventional transistor source and/or drain contact metal deposition and formation. For example, the conductive gate material104and the contact metal120may be deposited and patterned in accordance with a CMOS fabrication process (e.g., during a CMOS fabrication process used to form other components of the semiconductor device).

In addition, by including the conductive gate material104in the first electrode140and by including the contact metal120in the second electrode142, a distance between the first electrode140and the second electrode142may be substantially equal to a “minimum” permitted gate-to-contact pitch130. The minimum gate-to-contact pitch130may be defined by one or more fabrication design rules, such as design rules specified by an industry standard or by a particular fabrication facility, to be smaller than a minimum permitted contact-to-contact pitch134or a minimum permitted gate-to-gate pitch132. For example, the minimum permitted contact-to-contact pitch134may be associated with a pitch between the contact metal120and a third electrode138that includes a contact metal. The minimum permitted gate-to-gate pitch132may be associated with a pitch between the conductive gate material104and a fourth electrode136that includes a conductive gate material. As a result, a distance between the first electrode140and the second electrode142may be smaller than would be possible in other configurations where adjacent electrodes include the contact metal120(and are limited by the minimum permitted contact-to-contact pitch134) or configurations where adjacent electrodes include the conductive gate material104(and are limited by the minimum permitted gate-to-gate pitch132) based on the design rules.

As will be appreciated, by including the conductive gate material104in the first electrode140and including the contact metal120in the second electrode142, the MOM capacitor100advantageously may be configured according to the smallest permitted distance between electrodes available according to design rules. By having a reduced distance between the first electrode140and the second electrode142, a capacitance between the electrodes140and142(e.g., C1+C2) may be increased based on the reduced distance. Further, by having a reduced distance between the first electrode140and the second electrode142, the footprint (e.g., the surface area) of the MOM capacitor100may be reduced as compared to the other configurations (e.g., adjacent electrodes each including the conductive gate material104or each including the contact metal120).

FIG. 2is a perspective diagram showing a particular embodiment of a metal-oxide-metal (MOM) capacitor200disposed on a substrate211. The MOM capacitor200may be the MOM capacitor100ofFIG. 1. The MOM capacitor200includes a first layer (the first layer on the substrate211) that includes first electrode portions207, gate structures208, spacer structures209, and first dielectric portions210(depicted as transparent portions between the first electrode portions207and the spacer structures209). The first electrode portions207may be the contact portion of the second metal structure112including the contact metal120and the gate structures208may be the portion of the first metal structure106including the conductive gate material104, respectively, ofFIG. 1. The MOM capacitor200includes a second layer (e.g., a metal 0″ layer local connection disposed on the first layer) that includes second electrode portions205and second dielectric portions206(depicted as transparent portions between the second electrode portions205). The second electrode portions205may be the upper portion of the first metal structure106and the upper portion of the second metal structure112ofFIG. 1. The MOM capacitor200includes a connection layer a “via 0” layer disposed on the second layer) that includes conductive connection portions203and dielectric connection portions204(depicted as transparent portions between the conductive connection portions203). The conductive connection portions203may be the first via structure108and the second via structure114ofFIG. 1. The MOM capacitor200includes a third layer (e.g., a “metal 1” layer disposed on the connection layer) that includes third electrode portions201and third dielectric portions202(depicted as transparent areas between the third electrode portions201). The third electrode portions201may be the first higher metal structure110and the second higher metal structure116ofFIG. 1. The MOM capacitor200may be formed on a shallow trench isolation (STI) layer of the substrate211. Conductive structures extending (in a direction perpendicular to the substrate211) from the first layer to the third layer may form electrodes140,142, and212-214. The number of the electrodes140,142, and212-214shown inFIG. 2is illustrative; additional electrodes or fewer electrodes may be used.

In the first layer, the first electrode portions207and the gate structures208may be disposed on the substrate211alternately in parallel and spaced at a substantially equal distance. The distance between the first electrode portions207and the gate structures208may correspond to the minimum permitted gate-to-contact pitch130ofFIG. 1, and may be based on a design rule. The first dielectric portions210may include dielectric materials disposed between the first electrode portions207and the gate structures208. In the second layer, the second electrode portions205may be disposed in parallel and spaced at a substantially equal distance. The second dielectric portions206may include dielectric materials disposed between the second electrode portions205. The second electrode portions205may be disposed on the first electrode portions207and the gate structures208. By use of the gate structures208and the first electrode portions207, the MOM capacitor200may be extended to the substrate211.

In the third layer, the third electrode portions201may be disposed in parallel and spaced at a substantially equal distance. The third dielectric portions202may include dielectric materials disposed between the third electrode portions201. The conductive connection portions203may be disposed on the second electrode portions205and between the second electrode portions205and the third electrode portions201. The conductive connection portions203may include via structures such as trench vias that have a width and length that are less than or equal to a width and length of the corresponding third electrode portions201.

The substrate211may include a substantially non-conductive material portion, such as a shallow trench isolation (STI)-type material portion. In a particular embodiment, the substrate211may include an oxide material. The first layer of the MOM capacitor200(including the gate structures208) may be disposed over the STI-type material portion.

The electrodes140,142, and212-214may be alternately interconnected to form a first set of electrodes connected by a first electrode connector and a second set electrodes connected by a second electrode connector, as described further with reference toFIG. 3. The first electrode connector may be coupled to receive a first signal source and the second electrode connector may be coupled to receive a second signal source. Such a construction may form a MOM capacitor with capacitors wired in parallel (e.g., a first capacitor plate formed by the electrodes142and212,214and a second capacitor plate formed by the electrodes140and213), as further described below.

During operation, the first signal source and the second signal source may cause a voltage difference to occur between the first electrode connector and the second electrode connector. For example, the voltage difference may occur between the electrode140and the electrode142. The voltage difference may cause the electrode140and the electrode142to act as a plate capacitor. Each set of electrodes of the electrodes140,142, and212-214may act as a capacitor plate based on the voltage difference.

A capacitance of the MOM capacitor200may be based on several components. For example, a first component of the capacitance may be a first capacitance between the first electrode portions207and the gate structures208. A second component of the capacitance may be a second capacitance between the second electrode portions205. A third component of the capacitance may be a third capacitance between the third electrode portions201. The capacitance may include additional components similar to the first capacitance, the second capacitance, and the third capacitance, based on each set of the electrodes (e.g., each set of the gate structures208and the first electrode portions207) disposed alternately within the MOM capacitor200.

By extending the electrodes140,142, and212-214to the substrate211(e.g., including the first electrode portions207in the electrode142and including the gate structures208in the electrode140), a capacitance of the MOM capacitor200may be increased as compared to a conventional MOM capacitor that does not extend electrodes to the substrate211. For example, in a particular embodiment, the first component of the capacitance formed by the first electrode portions207and the gate structures208may increase the capacitance of the MOM capacitor200by approximately 18% using a same surface area (“footprint”) of the substrate211as compared to the conventional MOM capacitor that does not extend electrodes to the substrate211(e, the conventional MOM capacitor that does not include the gate structures208and the first electrode portions207).

In another particular embodiment, the first component of the capacitance formed by the first electrode portions207and the gate structures208may enable a footprint (e.g., a surface area) of the MOM capacitor200to be approximately 18% smaller than a footprint of the conventional MOM capacitor (e.g., the conventional MOM capacitor does not dispose the gate structures208and the first electrode portions207alternately and in parallel) while providing substantially similar capacitance. For example, the smaller footprint of the MOM capacitor200may be based on the minimum permitted gate-to-contact pitch between the gate structures208and the first electrode portions207. By reducing a distance between the gate structures208and the first electrode portions207to the minimum permitted gate-to-contact pitch, the capacitance of the MOM capacitor200may be further increased based on the reduced distance.

Referring toFIG. 3, a perspective diagram shows a particular embodiment of a MOM capacitor300disposed on a semiconductor substrate, such as a silicon portion of a substrate302. The MOM capacitor300includes the first electrode portions207(e.g., the contact portions), the gate structures208, the spacer structures209, the first dielectric portions210, the second electrode portions205(e.g., the “metal 0” layer local connections), the second dielectric portions206, the conductive connection portions203(e.g., the “via 0” layer), the dielectric connection portions204, the third electrode portions201(e.g., the “metal 1” layer structures), and the third dielectric portions202ofFIG. 2. The gate structures208may be isolated from the silicon portion of the substrate302via an electrically insulating layer, such as a high dielectric constant (e.g., a high-K) material layer or a gate oxide layer301. The MOM capacitor300may also include the electrodes140,142, and212-214ofFIG. 2, and the electrodes140,142, and212-214may be connected to a first electrode connector and a second electrode connector, as described with reference toFIG. 2.

During operation, a first signal source applied to the first electrode connector and a second signal source applied to the second electrode connector may cause a voltage difference to occur between the first electrode connector and the second electrode connector. The voltage difference may cause the MOM capacitor300to conduct charge (e.g., act as a plate capacitor) and thereby induce a capacitance in the MOM capacitor300. The capacitance of the MOM capacitor300may be based on several components, such as a first capacitance, a second capacitance, and a third capacitance as described with reference toFIG. 2. The capacitance may include additional components similar to the first capacitance, the second capacitance, and the third capacitance, based on each set of the electrodes140,142, and212-214(e.g., each set of the gate structures208and the first electrode portions207) disposed alternately within the MOM capacitor300.

The capacitance of the MOM capacitor300may further include additional components based on formation of the MOM capacitor300on the silicon portion of the substrate302. For example, a metal-oxide-silicon (MOS) gate structure within the silicon portion of the substrate302may result in a first additional gate capacitance (Cg) across the gate oxide layer301and a second additional junction capacitance (Cj) between the gate oxide layer301and the first electrode portions207due to charge accumulation. In a particular embodiment, the gate structures208may be a same type of material as a substrate well and a junction of a MOS structure (e.g., the MOM capacitor300). In the particular embodiment, the gate structures208are sufficiently biased such that the MOM capacitor300operates in an accumulation mode, thereby adding the gate capacitance (Cg) without adding the junction capacitance (0).

As illustrated inFIG. 3, the MOM capacitor300is deposited on a silicon portion of the substrate302rather than on the STI portion of the substrate211. In addition, the gate oxide layer301is deposited between the silicon portion of the substrate302and the gate structures208. Such construction may provide additional capacitance for the MOM capacitor300. The additional capacitance may be based on capacitors formed by the gate structures208acting as first electrodes and the first electrode portions207acting as second electrodes. In a particular embodiment, the gate oxide layer301and the silicon portion of the substrate302may act as dielectric media between the first electrodes and the second electrodes. The MOM capacitor300may provide a larger capacitance (e.g., a capacitance including Cg) than the MOM capacitor200ofFIG. 2, while the MOM capacitor200ofFIG. 2may provide enhanced high-frequency characteristics as compared to the MOM capacitor300ofFIG. 3. For example, disposing the MOM capacitor200on the STI-type material portion of the substrate211may reduce high frequency (e.g., greater than 1 GHz) signal degradation or high frequency signal loss via the MOM capacitor200.

Referring toFIG. 4, a diagram showing a top view of a MOM capacitor is depicted and generally designated400. The MOM capacitor400may include the MOM capacitor200ofFIG. 2or the MOM capacitor300ofFIG. 3. The MOM capacitor400includes electrodes140,142, and212-214, a first electrode connector401, and a second electrode connector402. The electrodes140,142, and212-214may be the electrodes140,142, and212-214ofFIG. 2or the electrodes140,142, and212-214ofFIG. 3.

The first electrode connector401may couple the electrodes212,142, and214to a first signal source. The second electrode connector402may couple the electrodes213and140to a second signal source. Such connections may form a MOM capacitor, such as the MOM capacitor400, with multiple parallel capacitor connections. For example, the first signal source and the second signal source may cause a voltage difference to occur between the electrode140and the electrode142. The voltage difference may cause the electrode140and the electrode142to conduct charge (e.g., act as capacitor plates of a plate capacitor). Each set of electrodes of the electrodes140,142, and212-214(e.g., the electrodes212and140, the electrodes140and142, the electrodes142and213, and the electrodes213and214) may act as a conventional capacitor based on the voltage difference.

Referring toFIG. 5, a flow chart of a first illustrative embodiment of a method of forming a MOM capacitor is depicted and generally designated500. The MOM capacitor may include the MOM capacitor100ofFIG. 1, the MOM capacitor200ofFIG. 2, the MOM capacitor300ofFIG. 3, or the MOM capacitor400ofFIG. 4. One or more operations of the method500may be initiated by a processor integrated into an electronic device, as described further with reference toFIG. 10.

The method500includes forming a first electrode at502. The first electrode includes a conductive gate material. The conductive gate material may be the conductive gate material104ofFIG. 1, the gate structures208ofFIG. 2, or the gate structures208ofFIG. 3. In a particular embodiment, the first electrode may be disposed on a substrate. The substrate may be the substrate102ofFIG. 1, the STI portion of the substrate211ofFIG. 2, or the silicon portion of the substrate302ofFIG. 3. The first electrode may be formed by depositing the conductive gate material on the substrate. The conductive gate material may be deposited using a film deposition process, such as a chemical vapor deposition (CVD) process, a spin-on process, a plasma-enhanced chemical vapor deposition (PECVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process, followed by a chemical-mechanical planarization (CMP) process. An additional upper portion of the first electrode may be formed using a similar process with a different material.

At504, a second electrode is formed. The second electrode includes a contact metal. The contact metal may be the portion of the second metal structure112including the contact metal120ofFIG. 1, the first electrode portions207ofFIG. 2, or the first electrode portions207ofFIG. 3. The first electrode is proximate to the second electrode. The contact metal may be formed by depositing the contact metal using a film deposition process followed by a CMP process. An additional upper portion of the second electrode may be formed using a similar process with a same or different material.

By including the conductive gate material in the first electrode and including the contact metal in the second electrode, the MOM capacitor formed by the method500advantageously may be configured according to the smallest permitted distance between electrodes available according to design rules. By having a reduced distance between the first electrode and the second electrode, a capacitance between the first electrode and the second electrode may be increased based on the reduced distance. Further, by having a reduced distance between the first electrode and the second electrode, the footprint (e.g., the surface area) of the MOM capacitor may be reduced as compared to the other configurations (e.g., adjacent electrodes each including the conductive gate material or each including the contact metal).

Referring toFIG. 6, a flow chart of a second illustrative embodiment of a method of forming a MOM capacitor is depicted and generally designated600. The MOM capacitor may include the MOM capacitor100ofFIG. 1, the MOM capacitor200ofFIG. 2, the MOM capacitor300ofFIG. 3, or the MOM capacitor400ofFIG. 4.

The method600includes forming a shallow trench isolation (STI) portion of an insulating substrate (e.g., a silicon wafer) and starting fabrication of the MOM capacitor from the STI portion, at601. The insulating substrate may be the substrate102ofFIG. 1or the STI portion of the substrate211ofFIG. 2. The STI portion may be formed by etching a trench and performing a film deposition process, such as a chemical vapor deposition (CVD) process, a spin-on process, a plasma-enhanced chemical vapor deposition (PECVD) process, or a high density plasma chemical vapor deposition (HDPCVD) process, followed by a chemical-mechanical planarization (CMP) process.

At602, a high-K dielectric layer and a dummy gate layer are formed on the STI portion of the substrate. The high-K dielectric layer may be an oxide layer, such as the gate oxide layer301ofFIG. 3, or the intervening gate dielectric layer103ofFIG. 1. In a particular embodiment, the dummy gate layer may include agate material used during CMOS transistor fabrication, such as a polysilicon film. The dummy gate layer may be formed by a film deposition process, such as a CVD process or a PECVD process, followed by a CMP process.

At603, dummy gates are patterned, such as for an array of transistor-type devices, from the dummy gate layer. In a particular embodiment, a photolithography and etch process may be used to pattern (e.g., form) the dummy gates. The dummy gates are patterned based on a shape and a size of gate structures used in the MOM capacitor. For example, the dummy gates may be patterned based on the first metal structure106(e.g., the conductive gate material104) ofFIG. 1, the gate structures208ofFIG. 2, or the gate structures208ofFIG. 3. A width of the dummy gates may be associated with the gate structures. For example, the width may be associated with the first metal structure106(e.g., the conductive gate material104) ofFIG. 1, the gate structures208and the spacer structures209ofFIG. 2, or the gate structures208and the spacer structures209ofFIG. 3. In a particular embodiment, the width of the dummy gates is approximately 20 nm.

At604, a spacer layer is deposited and etched back to form spacer structures. The spacer structures may be the spacer structures209ofFIG. 2or the spacer structures209ofFIG. 3. The spacer layer may be composed of any suitable material with a high dielectric constant to increase capacitance, such as silicon nitride (SiN). The spacer layer may be formed by a film deposition process, such as a CVD process or a PECVD process. After the spacer layer is deposited, a thickness of the spacer layer may be comparable to the thickness of the dummy gate layer. The spacer layer may be etched back (e.g., by plasma dry etching) to form the spacer structures. The spacer structures may be formed in accordance with gate spacer structure processing for transistors in another portion of the silicon wafer.

At605, a first dielectric layer is deposited and a CMP process is performed. The first dielectric portion may be deposited on the STI portion of the substrate. The first dielectric layer deposited may be the first dielectric portions210ofFIG. 2or the first dielectric portions210ofFIG. 3. In a particular embodiment, the first dielectric layer may be composed of silicon oxide based materials, such as undoped silicate glass (USG), fluorinated silicate glass (FSG), plasma-enhanced chemical vapor deposition (PECVD) silicon oxide, or oxide/nitride/oxide. In another particular embodiment, the first dielectric layer may be composed of dielectric materials with a high dielectric constant, such as tantalum oxide (Ta2O5), hafnium oxide (HfO2), hafnium oxynitride (MON), barium strontium titanate (BazSr(1-z)TiO3(BST)), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), lead titanium oxide (PbTiO3), lead zirconate titanate (Pb(Zr,Ti)O3[PZT]), lead lanthanum zirconate titanate ((Pb, La)(Zr, Ti)O3[PLZT], lead lanthanum titanate (Pb, La)TiO3[PLT], tantalum oxide (Ta2O5), potassium nitrate (KNO3), aluminum oxide (Al2O3), or lithium niobium oxide (LiNbO3). A thickness of the first dielectric layer may be comparable to the thickness of the dummy gate layer after a CMP process is performed on the dummy gates, the spacer layer, and the first dielectric layer. In a particular embodiment, the CMP process may be performed on the first dielectric layer, the spacer layer, the dummy gates, or a combination thereof, to smooth a surface and to even out irregular topography.

At606, the dummy gates are removed, metal is deposited to form gate structures, and a CMP process is performed. For example, the dummy gates may be removed to form recesses via application of a wet etch process or a plasma etching process. The metal may be deposited in the recesses to form the gate structures. The gate structures may be the first metal structure106(e.g., the conductive gate material104) ofFIG. 1, the gate structures208ofFIG. 2or the gate structures208ofFIG. 3. The gate structures may be composed of metals or metal alloys, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), aluminum (Al), aluminum-copper alloy (Al—Cu), aluminum-neodymium (Al—Nd), or aluminum-tantalum (Al—Ta). In a particular embodiment, the gate structures may be formed by a film deposition process, such as an ALD process, a CVD process, a sputtering process, or an electroplating process. The CMP process may be performed on the gate structures to remove extra gate material, smooth a surface, even out irregular topography, or a combination thereof.

At607, an etch stop layer is deposited. The etch stop layer may be composed of silicon carbide (SiC) (optionally doped with carbon) or silicon nitride (SiN) (optionally doped with nitrogen). The etch stop layer may be formed by a film deposition process, such as a CVD process, a PECVD process, or a PVD process.

At608, openings are patterned in the etch stop layer, metal is deposited in the openings to form first electrode portions, and a CMP process is performed. The first electrode portions may be the second metal structure112(e.g., the contact metal120) ofFIG. 1, the first electrode portions207ofFIG. 2or the first electrode portions ofFIG. 3. In a particular embodiment, the first electrode portions may be formed via, a single damascene process (e.g., a process to pattern an opening in a material, deposit metal into the opening, and remove excess metal via a CMP process). For example, a photolithography and etch process may be performed to pattern the openings corresponding to the first electrode portions. The metal deposited in the openings may be metal or metal alloy such as copper (Cu), aluminum-copper alloy (Ala), tantalum (Ta), titanium (TO, tungsten (W), or silver (AO. The first electrode portions may be formed by a film deposition process, such as a PVD process, a sputtering process, or an electroplating process.

At609, a second dielectric layer is deposited, first electrode trenches are patterned in the second dielectric layer, metal is deposited in the first electrode trenches to form second electrode portions, and a CMP process is performed. The second dielectric layer may be deposited on the gate structures, the first electrode portions, the first dielectric layer, or a combination thereof. The second electrode portions may be the second electrode portions205ofFIG. 2or the second electrode portions205ofFIG. 3. The second dielectric layer may be the second dielectric portions206ofFIG. 2or the second dielectric portions206ofFIG. 3. In a particular embodiment, the second dielectric layer may be composed of silicon oxide based materials, such as undoped silicate glass (USG), fluorinated silicate glass (TSG), plasma-enhanced chemical vapor deposition (PECVD) silicon oxide, or oxide/nitride/oxide. In another particular embodiment, the second dielectric layer may be composed of dielectric materials with a high dielectric constant, such as tantalum oxide (Ta2O5), hafnium oxide (HfO2), hafnium oxynitride (HfON), barium strontium titanate (BazSr(1-z)TiO3(BST)), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), lead titanium oxide (PbTiO3), lead zirconate titanate (Pb(Zr,Ti)O3[PZT]), lead lanthanum zirconate titanate ((Pb, La)(Zr, Ti)O3[PLZT], lead lanthanum titanate ((Pb, La)TiO3[PLT], tantalum oxide (Ta2O5), potassium nitrate (KNO3), aluminum oxide (Al2O3), or lithium niobium oxide (LiNbO3). The second dielectric layer may be formed by a film deposition process, such as a CVD process, a spin-on process, a PECVD process, or a HDPCVD process, followed by a CMP process. In a particular embodiment, the second dielectric layer and the first dielectric layer may be composed of the same material. In an alternate embodiment, the second dielectric layer and the first dielectric layer may be composed of different materials.

In a particular embodiment, the second electrode portions may be formed via a single damascene process. For example, a photolithography and etch process may be performed to pattern the first electrode trenches, and the metal may be deposited into the first electrode trenches to form the second electrode portions. The CMP process may be performed to remove extra metal material and smooth a surface of the second electrode portions and to even out irregular topography. The second electrode portions may be disposed on the first electrode portions and on the gate structures. The metal deposited in the first electrode trenches may be a metal or metal alloy, such as copper (Cu), aluminum-copper alloy (AlCu), tantalum (Ta), titanium (Ti), tungsten (W), or silver (Ag). The second electrode portions may be deposited by a film deposition process, such as a PVD process, a sputtering process, or an electroplating process. In a particular embodiment, the second electrode portions and the first electrode portions may be composed of the same material. In an alternate embodiment, the second electrode portions and the first electrode portions may be composed of different materials.

At610, a third dielectric layer is deposited and patterned to form via trenches and second electrode trenches. In a particular embodiment, the third dielectric layer may be composed of silicon oxide based materials, such as undoped silicate glass (USG), fluorinated silicate glass (FSG), plasma-enhanced chemical vapor deposition (PECVD) silicon oxide, or oxide/nitride/oxide. In another particular embodiment, the third dielectric layer may be composed of dielectric materials with a high dielectric constant, such as tantalum oxide (Ta2O5), hafnium oxide (HfO2), hafnium oxynitride (WON), barium strontium titanate (BazSr(1-z)TiO3(BST)), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), lead titanium oxide (PbTiO3), lead zirconate titanate (Pb(Zr,Ti)O3[PZT], lead lanthanum zirconate titanate ((Pb, La)(Zr, Ti)O3[PLZT], lead lanthanum titanate ((Pb, La)TiO3[PLT], tantalum oxide (Ta2O5), potassium nitrate (KNO3), aluminum oxide (Al2O3), or lithium niobium oxide (LiNbO3The third dielectric layer may be formed by a film deposition process, such as a CVD process, a spin-on process, a PECVD process, or a HDPCVD process, and followed by a CMP process. In a particular embodiment, the first dielectric layer, the second dielectric layer, and the third dielectric layer may be composed of the same material. In an alternative embodiment, the first dielectric layer, the second dielectric layer, and the third dielectric layer may be composed of different materials.

In a particular embodiment, the via trenches and the second electrode trenches may be formed during a dual damascene process. For example, a photolithography and etch process may be applied to the third dielectric layer to pattern the via trenches and the second electrode trenches. The second electrode trenches may include electrode trenches for first electrode connectors and second electrode connectors, such as the first electrode connectors401and the second electrode connectors402ofFIG. 4. In an alternate embodiment, the dual damascene process may be replaced by two single damascene processes.

At611, metal is deposited into the second electrode trenches and the via trenches, a CMP process is performed on the metal to form via structures and third electrode portions, and a cap film layer is deposited. The third electrode portions may be the first higher metal structure110and the second higher metal structure116ofFIG. 1, the third electrode portions201ofFIG. 2or the third electrode portions201ofFIG. 3. The via structures may be the first via structure108and the second via structure114ofFIG. 1, the conductive connection structures203ofFIG. 2or the conductive connection structures203ofFIG. 3. In a particular embodiment, the via structures may be trench-shape vias. In alternate embodiments, the via, structures may be in any suitable shape, such as rod-shape vias.

In a particular embodiment, the via structures and the third electrode portions may be formed during the dual damascene process. The CMP process may be performed to remove extra metal, smooth the surface of the third electrode portions, even out irregular topography, or a combination thereof. In a particular embodiment, a width of the via structures may be less than a width of the third electrode portions. The metal deposited in the second electrode trenches and via structures may be a metal or metal alloy, such as copper (Cu), aluminum-copper alloy (AlCu), tantalum (Ta), titanium (Ti), tungsten (W), or silver (Ag). In a particular embodiment, the via, structures, the third electrode portions, the second electrode portions, and the first electrode portions may be composed of the same material. In an alternate embodiment, the via structures, the third electrode portions, the second electrode portions, and the first electrode portions may be composed of different materials. Although a damascene process has been described, one of ordinary skill in the art will appreciate that the technique used to form the gate structures, the first electrode portions, the second electrode portions, and the third electrode portions may not be a damascene process; an alternative technique may be adopted depending on the materials to be used or other criteria.

The via structures may be vertically disposed substantially on the second electrode portions, and the third electrode portions may be vertically disposed substantially on the via structures. The third electrode portions and the via structures may be formed by a film deposition process, such as a PVD process, a sputtering process, or an electroplating process. In a particular embodiment, the third electrode portions (and corresponding second electrode portions and corresponding gate structures or corresponding first electrode portions) may be alternately interconnected by the first electrode connector (to form a first set of electrode portions) and by the second electrode connector (to form a second set of electrode portions). Such alternating interconnection of the sets of the electrode portions forms a MOM capacitor with capacitors connected in parallel, as described above with reference toFIG. 4.

After forming the third electrode portions and the via structures, the cap film layer may be deposited. The cap film layer (e.g., an insulation layer) may be deposited to insulate the MOM capacitor from other circuitry and devices. The cap film layer may be formed by a film deposition process, such as a CVD process, a spin-on process, a PECVD process, or a HDPCVD process, followed by a CMP process.

Although not shown inFIG. 6, additional dielectric layers, additional electrode portions, and additional via structures may be formed in the MOM capacitor. The additional dielectric layers, the additional electrode portions, and the additional via structures may be formed via iteration(s) of610and611, after deposit of the cap film layer.

By having the gate structures and the first electrode portions disposed alternately and in parallel, the MOM capacitor formed by the method600may be configured according to the smallest permitted distance between electrodes available according to design rules. By having a reduced distance between the gate structures and the first electrode portions, a capacitance between the gate structures and the first electrode portions may be increased based on the reduced distance. Further, by having a reduced distance between the gate structures and the first electrode portions, a footprint (e.g., a surface area) of the MOM capacitor may be reduced as compared to the other configurations (e.g., configurations with adjacent gate structures or adjacent first electrode portions).

Referring toFIG. 7, a flow chart of a third illustrative embodiment of a method of forming a MOM capacitor is depicted and generally designated700. The MOM capacitor may include the MOM capacitor100ofFIG. 1, the MOM capacitor200ofFIG. 2, the MOM capacitor300ofFIG. 3, or the MOM capacitor400ofFIG. 4.

The method700includes forming a silicon portion of an insulation substrate (e.g., a silicon wafer) and starting fabrication of the MOM capacitor from the silicon portion, at701. The insulating substrate may be the substrate102ofFIG. 1or the silicon portion of substrate302ofFIG. 3. A dielectric material layer may be formed on the silicon portion of the substrate. In a particular embodiment, the dielectric material layer may include a high-k dielectric film (e.g., hafnium oxide (HfOx) or hafnium oxynitride (HfOxN)), and source and drain active areas (e.g., active areas excluding gate areas) may include silicon germanium (SiGe) or silicon carbide (SiC). In another particular embodiment, the dielectric material layer may be an oxide layer, such as the gate oxide layer301ofFIG. 3, or the intervening dielectric layer103ofFIG. 1. The dielectric material layer may be formed by a film deposition process, such as a thermal growth process, a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, or an atomic layer deposit (ALD) process, followed by a chemical-mechanical planarization (CMP) process. The method700further includes602-611, as described with reference toFIG. 6.

By having the gate structures and the first electrode portions disposed alternately and in parallel, the MOM capacitor formed by the method700may be configured according to the smallest permitted distance between electrodes available according to design rules. By having a reduced distance between the gate structures and the first electrode portions, a capacitance between the gate structures and the first electrode portions may be increased based on the reduced distance. Further, by having a reduced distance between the gate structures and the first electrode portions, a footprint (e.g., a surface area) of the MOM capacitor may be reduced as compared to the other configurations (e.g., configurations with adjacent gate structures or adjacent first electrode portions). Further, the MOM capacitor formed by the method700may provide additional capacitance as compared to the MOM capacitor formed by the method600. For example, by disposing the MOM capacitor on the silicon portion of the substrate, the MOM capacitor formed by the method700may provide a first additional gate capacitance (Cg) across the dielectric material layer and a second additional junction capacitance (Cj) between the dielectric material layer and the first electrode portions due to a PN junction. In a particular embodiment, a material type (e.g., a type of metal) of the gate structures and source and drain doping types are the same as a doping type of the substrate. In the particular embodiment, when a channel of the MOM capacitor is operating in an accumulation mode, the MOM capacitor provides only the first additional gate capacitance (Cg) (e.g., the second additional junction capacitance (Cj) is not provided by the MOM capacitor).

Referring toFIG. 8, a flow chart of a fourth illustrative embodiment of a method of forming a MOM capacitor is depicted and generally designated800. The MOM capacitor may include the MOM capacitor100ofFIG. 1, the MOM capacitor200ofFIG. 2, the MOM capacitor300ofFIG. 3, or the MOM capacitor400ofFIG. 4.

The method includes forming a shallow trench isolation (STI) layer on an insulating substrate and starting from the STI layer, at601, as described with reference toFIG. 6. The insulating substrate may be the substrate102ofFIG. 1or the STI portion of the substrate211ofFIG. 2.

At802, a high-K dielectric layer and a gate layer are formed or grown. The high-K dielectric layer may be an oxide layer, such as the gate oxide layer301ofFIG. 3, or the intervening dielectric layer103ofFIG. 1. A thickness of the high-K dielectric layer or the oxide layer and the gate layer may be any suitable thickness and may accommodate design and functioning criteria of the MOM capacitor. At803, gates are patterned, such as for an array of transistor-type devices, from the gate layer. In a particular embodiment, a photolithography and etch process may be used to pattern (e.g., form) the gates. A width of the gates may be any suitable width and may accommodate design and functioning criteria of the MOM capacitor. In a particular embodiment, the width of the gates is approximately 20 nm. The method800further includes604-605and607-611as described with reference toFIG. 6.

FIG. 8illustrates an alternate embodiment toFIG. 6. InFIG. 6, dummy gates are formed at603and later removed and replaced with metal at606. InFIG. 8, gates are formed at802, and the deposited gate material may remain without being later replaced. For example, a metal film may be deposited and patterned at802-803and may not be later removed (e.g.,606is omitted).

By having the gate structures and the first electrode portions disposed alternately and in parallel, the MOM capacitor formed by the method800may be configured according to the smallest permitted distance between electrodes available according to design rules. By having a reduced distance between the gate structures and the first electrode portions, a capacitance between the gate structures and the first electrode portions may be increased based on the reduced distance. Further, by having a reduced distance between the gate structures and the first electrode portions, a footprint (e.g., a surface area) of the MOM capacitor may be reduced as compared to the other configurations (e.g., configurations with adjacent gate structures or adjacent first electrode portions). Further, the MOM capacitor formed by the method800may provide enhanced high-frequency characteristics. For example, by disposing the MOM capacitor on the STI portion of the substrate, the MOM capacitor formed by the method800may reduce high frequency greater than 1 GHz) signal degradation via the MOM capacitor.

Referring toFIG. 9, a flow chart of a fifth illustrative embodiment of a method of forming a MOM capacitor is depicted and generally designated900. The MOM capacitor may include the MOM capacitor100ofFIG. 1, the MOM capacitor200ofFIG. 2, the MOM capacitor300ofFIG. 3, or the MOM capacitor400ofFIG. 4.

The method900includes forming a shallow trench isolation (STI) layer on a silicon substrate (e.g., a silicon wafer) and starting from a silicon layer, at701. The silicon substrate may be the substrate102ofFIG. 1or the silicon portion of the substrate302ofFIG. 3. An insulating material layer may be formed on the silicon substrate. In a particular embodiment, the insulating material layer may be an oxide layer, such as the gate oxide layer301ofFIG. 3, or the intervening dielectric layer103ofFIG. 1. A thickness of the insulating material layer may be any suitable thickness and may accommodate design and functioning criteria of the MOM capacitor. The method900further includes802-803,604,805-809, and611, as described above with reference toFIG. 8.

FIG. 9illustrates an alternate embodiment toFIG. 7. InFIG. 7, dummy gates are formed at603and later removed and replaced with metal at606. InFIG. 9, gates are formed at802, and the deposited gate material may remain without being later replaced. For example, a metal film may be deposited and patterned at802-803and may not be later removed (e.g.,606is omitted).

By having the gate structures and the first electrode portions disposed alternately and in parallel, the MOM capacitor formed by the method900may be configured according to the smallest permitted distance between electrodes available according to design rules. By having a reduced distance between the gate structures and the first electrode portions, a capacitance between the gate structures and the first electrode portions may be increased based on the reduced distance. Further, by having a reduced distance between the gate structures and the first electrode portions, a footprint (e.g., a surface area of the MOM capacitor may be reduced as compared to the other configurations (e.g., configurations with adjacent gate structures or adjacent first electrode portions). Further, the MOM capacitor formed by the method900may provide additional capacitance as compared to the MOM capacitors formed by the methods600and800. For example, by disposing the MOM capacitor on the silicon portion of the substrate, the MOM capacitor formed by the method900may provide a first additional capacitance (Cg) across the dielectric material layer and a second additional capacitance (Cj) between the dielectric material layer and the first electrode portions due to a PN junction. In a particular embodiment, a material type (e.g., a type of metal) of the gate structures and source and drain doping types are the same as a doping type of the substrate. In the particular embodiment, when a channel of the MOM capacitor is operating in an accumulation mode, the MOM capacitor provides only the first additional gate capacitance (Cg) (e.g., the second additional junction capacitance (Cj) is not provided by the MOM capacitor).

One or more of the operations described with reference to the methods500-900ofFIGS. 5-9, respectively, may be initiated by a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit such as a central processing unit (CPU), a digital signal processor (DSP), a controller, another hardware device, a firmware device, or any combination thereof. As an example, the methods500-900ofFIGS. 5-9, respectively, may be initiated by a processor that executes instructions stored at a memory (e.g., a non-transitory computer-readable medium) integrated within equipment of a semiconductor fabrication plant (e.g., a “fab”), as described further with reference toFIG. 11.

Referring toFIG. 10, a block diagram of a particular illustrative embodiment of a mobile device is depicted and generally designated1000. For example, the mobile device1000may include a processor1010, such as a digital signal processor (DSP). The processor1010may include a MOM capacitor1064, such as the MOM capacitor100ofFIG. 1, the MOM capacitor200ofFIG. 2, the MOM capacitor300ofFIG. 3, or the MOM capacitor400ofFIG. 4formed according to the methods of any ofFIGS. 5-9. Although the MOM capacitor1064is shown as being included in the processor1010, in alternate embodiments, the MOM capacitor1064may be included in other components of the mobile device1000. The processor1010may be coupled to a memory1032, such as random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROW, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), a non-transitory computer-readable medium, or any other form of non-transient storage medium known in the art, that stores instructions executable by the processor1010.

FIG. 10also shows a display controller1026that is coupled to the processor1010and to a display1028. A coder/decoder (CODEC)1034can also be coupled to the processor1010. A speaker1036and a microphone1038can be coupled to the CODEC1034.FIG. 10also indicates that a wireless controller1040can be coupled to the processor1010and to an antenna1042.

In a particular embodiment, the processor1010, the display controller1026, the memory1032, the CODEC1034, and the wireless controller1040are included in a system-in-package or system-on-chip device1022. An input device1030and a power supply1044may be coupled to the system-on-chip device1022. Moreover, in a particular embodiment, as illustrated inFIG. 10, the display1028, the input device1030, the speaker1036, the microphone1038, the antenna1042, and the power supply1044are external to the system-on-chip device1022. However, each of the display1028, the input device1030, the speaker1036, the microphone1038, the antenna.1042, and the power supply1044can be coupled to a component of the system-on-chip device1022, such as an interface or a controller.FIG. 10also depicts that the system-on-chip device1022may include the semiconductor device including the MOM capacitor1064. According to various embodiments, the semiconductor device including the MOM capacitor1064may be coupled to (or integrated within) one or more of the components of the mobile device1000, depending on the particular application.

The foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc) stored on computer readable media. Some or all such files may be provided to fabrication handlers to fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor dies and packaged into semiconductor chips. The semiconductor chips are then employed in electronic devices.FIG. 11depicts a particular illustrative embodiment of an electronic device manufacturing process1100.

Physical device information1102is received at the manufacturing process1100, such as at a research computer1106. The physical device information1102may include design information representing at least one physical property of a semiconductor device. For example, the physical device information1102may include physical parameters, material characteristics, and structure information that is entered via a user interface1104coupled to the research computer1106. The research computer1106includes a processor1108, such as one or more processing cores, coupled to a computer-readable medium such as a memory1110. The memory1110may store computer-readable instructions that are executable to cause the processor1108to transform the physical device information1102to comply with a file format and to generate a library file1112.

In a particular embodiment, the library file1112includes at least one data file including the transformed design information. For example, the library file1112may include a library of semiconductor devices, including a semiconductor device including the MOM capacitor100ofFIG. 1, the MOM capacitor200ofFIG. 2, the MOM capacitor300ofFIG. 3, or the MOM capacitor400ofFIG. 4, formed according to the methods of any ofFIGS. 5-9, provided for use with an electronic design automation (EDA) tool1120.

The library file1112may be used in conjunction with the FDA tool1120at a design computer1114including a processor1116, such as one or more processing cores, coupled to a memory1118. The EDA tool1120may be stored as processor executable instructions at the memory1118to enable a user of the design computer1114to design a circuit including the MOM capacitor using the library file1112. For example, a user of the design computer1114may enter circuit design information1122via a user interface1124coupled to the design computer1114. The circuit design information1122may include design information representing at least one physical property of a semiconductor device, such as a semiconductor device including the MOM capacitor. To illustrate, the circuit design property may include identification of particular circuits and relationships to other elements in a circuit design, positioning information, feature size information, interconnection information, or other information representing a physical property of a semiconductor device.

The design computer1114may be configured to transform the design information, including the circuit design information1122, to comply with a file format. To illustrate, the file formation may include a database binary file format representing planar geometric shapes, text labels, and other information about a circuit layout in a hierarchical format, such as a Graphic Data System (GDSII) file format. The design computer1114may be configured to generate a data file including the transformed design information, such as a GOSH file1126that includes information describing a semiconductor device including the MOM capacitor, in addition to other circuits or information. To illustrate, the data file may include information corresponding to a system-on-chip (SOC) that includes a semiconductor device including the MOM capacitor and that also includes additional electronic circuits and components within the SOC.

The GDSII file1126may be received at a fabrication process1128to manufacture a semiconductor device including the MOM capacitor and according to transformed information in the GDSII file1126. For example, a device manufacture process may include providing the GDSII file1126to a mask manufacturer1130to create one or more masks, such as masks to be used with photolithography processing, illustrated inFIG. 11as a representative mask1132. The mask1132may be used during the fabrication process to generate one or more wafers1134, which may be tested and separated into dies, such as a representative die1136. The die1136includes a circuit including a semiconductor device including the MOM capacitor.

The die1136may be provided to a packaging process1138where the die1136is incorporated into a representative package1140. For example, the package1140may include the single die1136or multiple dies, such as a system-in-package (SiP) arrangement. The package1140may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards.

Information regarding the package1140may be distributed to various product designers, such as via a component library stored at a computer1146. The computer1146may include a processor1148, such as one or more processing cores, coupled to a memory1150. A printed circuit board (PCB) tool may be stored as processor executable instructions at the memory1150to process PCB design information1142received from a user of the computer1146via a user interface1144. The PCB design information1142may include physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device corresponding to the package1140including a semiconductor device including the MOM capacitor.

The computer1146may be configured to transform the PCB design information1142to generate a data file, such as a GERBER file1152with data that includes physical positioning information of a packaged semiconductor device on a circuit hoard, as well as layout of electrical connections such as traces and vias, where the packaged semiconductor device corresponds to the package1140including a semiconductor device including the MOM capacitor. In other embodiments, the data file generated by the transformed PCB design information may have a format other than a GERBER format.

The GERBER file1152, may be received at a board assembly process1154and used to create PCBs, such as a representative PCB1156, manufactured in accordance with the design information stored within the GERBER file1152. For example, the GERBER file1152may be uploaded to one or more machines to perform various steps of a PCB production process. The PCB1156may be populated with electronic components including the package1140to form a representative printed circuit assembly (PCA)1158.

The PCA1158may be received at a product manufacture process1160and integrated into one or more electronic devices, such as a first representative electronic device1162and a second representative electronic device1164. As an illustrative, non-limiting example, the first representative electronic device1162, the second representative electronic device1164, or both, may be selected from the group of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which a semiconductor device including the MOM capacitor is integrated. As another illustrative, non-limiting example, one or more of the representative electronic devices1162and1164may be remote units such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter, reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. AlthoughFIG. 11illustrates remote units according to teachings of the disclosure, the disclosure is not limited to these illustrated units. Embodiments of the disclosure may be suitably employed in any device which includes active integrated circuitry including memory and on-chip circuitry.

A device that includes a semiconductor device including the MOM capacitor may be fabricated, processed, and incorporated into an electronic device, as described in the illustrative process1100. One or more aspects of the embodiments disclosed with respect toFIGS. 1-11may be included at various processing stages, such as within the library file1112, the GDSII file1126, and the GERBER file1152, as well as stored at the memory1110of the research computer1106, the memory1118of the design computer1114, the memory1150of the computer1146, the memory of one or more other computers or processors (not shown) used at the various stages, such as at the board assembly process1154, and also incorporated into one or more other physical embodiments such as the mask1132, the die1136, the package1140, the PCA1158, other products such as prototype circuits or devices (not shown), or any combination thereof. Although various representative stages are depicted with reference toFIGS. 1-11, in other embodiments fewer stages may be used or additional stages may be included. Similarly, the process1100ofFIG. 11may be performed by a single entity or by one or more entities performing various stages of the process1100.

In conjunction with the described embodiments, an apparatus is disclosed that includes a MOM capacitor device. The MOM capacitor device includes first means for conducting charge coupled to a substrate. The first means for conducting charge may be the first metal structure106or the first electrode140ofFIG. 1, the electrode140ofFIG. 2, the electrode140ofFIG. 3, or the electrode140ofFIG. 4. The substrate may be the substrate102ofFIG. 1, the STI portion of the substrate211ofFIG. 2, or the silicon portion of the substrate302ofFIG. 3. The first means for conducting charge may correspond to a first capacitor plate of a plate capacitor. The first means for conducting charge includes a conductive gate material. The conductive gate material may be the conductive gate material104ofFIG. 1, the gate structures208ofFIG. 2or the gate structures208ofFIG. 3.

The MOM capacitor device further includes second means for conducting charge coupled to the substrate. The second means for conducting charge may correspond to a second capacitor plate of the plate capacitor. The second means for conducting charge may be the second metal structure112or the second electrode142ofFIG. 1, the electrode142ofFIG. 2, the electrode142ofFIG. 3, or the electrode142ofFIG. 4. The second means for conducting charge includes a contact metal. The contact metal may be the contact metal120ofFIG. 1, the first electrode portions207ofFIG. 2, or the first electrode portions207ofFIG. 3. The first means for conducting charge is proximate to the second means for conducting charge.

In a particular embodiment, the first means for conducting charge and the second means for conducting charge may be connected to a first signal source and a second signal source, respectively, and may conduct charge based on a voltage difference between the first signal source and the second signal source. For example, the first means for conducting charge and the second means for conducting charge may operate in a manner similar to the first capacitor plate and the second capacitor plate of a plate capacitor, or similar to any of the electrodes140,142, and212-214ofFIGS. 2-4. The MOM capacitor device may be integrated within an electronic device, such as the first representative electronic device1162, the second representative electronic device1164, or a combination thereof.

In conjunction with the described embodiments, a non-transitory computer-readable medium stores instructions executable by a computer to initiate fabrication of a MOM capacitor device. For example, the non-transitory computer readable medium may store instructions executable by the computer to initiate fabrication of the MOM capacitor device based on any of the methods500-900. The MOM capacitor device may be the MOM capacitor100ofFIG. 1, the MOM capacitor200ofFIG. 2, the MOM capacitor300ofFIG. 3, or the MOM capacitor400ofFIG. 4.

The fabrication of the MOM capacitor device includes forming a first electrode. The first electrode may include a conductive gate material. The conductive gate material may be the conductive gate material104ofFIG. 1, the gate structures208ofFIG. 2, or the gate structures208ofFIG. 3.

The fabrication of the MOM capacitor device further includes forming a second electrode. The second electrode may include a contact metal. The contact metal may be the contact metal120ofFIG. 1, the first electrode portions207ofFIG. 2, or the first electrode portions207ofFIG. 3. The first electrode is proximate to the second electrode. The processor and the memory may be integrated within an electronic device, such as equipment of a semiconductor fabrication plant.