Package component, semiconductor package and manufacturing method thereof

A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes an insulating layer, a functional circuit structure embedded in the insulating layer within a functional circuit region, and a seal ring structure embedded in the insulating layer within the seal ring region surrounding the functional circuit region. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure. The seal ring structure includes a stack of alternating interconnect layers and via patterns, and the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the seal ring region.

BACKGROUND

With the advancement of modem technologies, integrated circuits having more functions and greater performance are increasingly demanded. In the packaging of integrated circuits, semiconductor dies are packaged onto package components, which include the circuitry used to route electrical signals. The package components may use organic materials such as materials that can be easily laminated. However, the materials are prone to the warpage caused by the elevated temperatures during a reflow process. Due to the warpage in the package components, crack or delamination may occur, and the yield of the packaging process is adversely affected. Therefore, there is the need for more creative packaging techniques.

DETAILED DESCRIPTION

Embodiments of the present disclosure are discussed in the context of semiconductor manufacturing, and in particular, in the context of forming a semiconductor package including a package component having a seal ring structure. The seal ring structure surrounds the functional circuit structure and includes via features arranged in a discontinuous manner. In this manner, the package component may achieve high connection reliability without generating void and/or crack therein. Some variations of embodiments are discussed and the intermediate stages of forming the semiconductor package are illustrated in accordance with some embodiments. It should be appreciated that the illustration throughout the drawings are schematic and not in scale.

FIGS. 1A-1Jare schematic cross-sectional views of various stages of manufacturing a semiconductor package in accordance with some embodiments,FIG. 2is a schematic top view ofFIG. 1Din accordance with some embodiments, andFIG. 3is a schematic perspective view of a seal ring structure in the dashed area A shown inFIG. 1Ein accordance with some embodiments.

Referring toFIG. 1A, a dielectric material layer110A is formed over a temporary carrier TC. For example, the material of the temporary carrier TC includes glass, silicon (e.g., bulk silicon), metal (e.g., steel), ceramic, a combination thereof, multi-layers thereof, or the like. The temporary carrier TC may be in a wafer form or in a panel form. Although any suitable shape of the temporary carrier TC may be provided. In some embodiments, the temporary carrier TC is provided with a release layer (not shown) formed thereon to facilitate de-bonding the temporary carrier TC from the structure formed thereon in the subsequent process. For example, the release layer includes a layer of light-to-heat-conversion (LTHC) release coating and a layer of associated adhesive (e.g. a ultra-violet curable adhesive or a heat curable adhesive layer), or the like. Alternatively, the release layer is omitted.

In some embodiments, the dielectric material layer110A may be a polymer layer. The dielectric material layer110A may be or may include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like. Other suitable dielectric material (e.g., solder resist, or Ajinomoto build-up film (ABF), etc.) may be used. In some embodiments in which the temporary carrier TC is provided with the release layer, the dielectric material layer110A is formed on the release layer. The dielectric material layer110A may be formed by using any suitable method, such as a spin coating process, a deposition process, and/or the like.

Referring toFIG. 1B, a first interconnect layer121A and a second interconnect layer131A is formed on the dielectric material layer110A. In some embodiments, the first interconnect layer121A includes contact pads for the subsequently formed structure landing thereon. The first interconnect layer121A may also include metal lines (not shown) connected to the contact pads, depending on the circuit design. For example, the second interconnect layer131A is not in contact with the first interconnect layer121A. The second interconnect layer131A may be isolated from the first interconnect layer121A. In some embodiments, the first interconnect layer121A is formed in a functional circuit region CR and the second interconnect layer131A is formed in a seal ring region SR encompassing the functional circuit region CR.

In some embodiments, a buffer region BR is between the functional circuit region CR and the seal ring region SR and encircles the functional circuit region CR. The second interconnect layer131A may be separated from the first interconnect layer121A by the buffer region BR. The buffer region BR may span a lateral dimension, and the lateral dimension may be non-zero. It is noted that the lateral dimension may be designed depending on the process requirements and construe no limitation in the disclosure. By the configuration of the buffer region BR, the risk of damage to the first interconnect layer121A and the structure form thereon may be reduced. The buffer region BR may be adjacent to the functional circuit region CR and the seal ring region SR within a device area. It is appreciated that numerous sets of the functional circuit regions CR, the buffer regions BR, and the seal ring regions SR may be defined on a given temporary carrier TC. For illustration, only one set of the regions is shown inFIGS. 1A-1J.

In some embodiments, the formation of the first interconnect layer121A includes at least the following steps. For example, a seed material layer (not shown) is formed on the dielectric material layer110A using suitable process such as sputtering, evaporation, or deposition processes, depending upon the desired materials. The seed material layer may be made of material (s) that aids in the formation of a thicker layer during subsequent processing steps. For example, the seed material layer is a metal layer, which may be a single layer (e.g., copper or copper alloys) or a composite layer including sub-layers formed of different materials (e.g., titanium and copper). Next, a photoresist having openings (also not shown) may be formed to partially cover the seed material layer using a spin coating process, lithography and etching process, or other suitable techniques. The conductive material (e.g., copper, titanium, tungsten, aluminum, another metal, the like, or a combination thereof, etc.) may be formed on the seed material layer and in the openings of the photoresist using electroplating or electroless-plating, or other suitable deposition process. Subsequently, the photoresist is removed through a suitable removal process such as ashing or chemical stripping. Those portions of the seed material layer that were covered by the photoresist may be removed by etching or other suitable process. The conductive material may serve as an etch mask when removing those portions of the seed material layer. The remaining portions of the seed material layer and conductive material thereon collectively form the first interconnect layer121A.

In some embodiments, the first interconnect layer121A and the second interconnect layer131A are formed by the same materials, at the same time, and by the same processes. For example, the remaining portions of the seed material layer and conductive material thereon within the functional circuit region CR are referred to the first interconnect layer121A, and the remaining portions of the seed material layer and conductive material thereon within the seal ring region SR are referred to the second interconnect layer131A.

Referring toFIG. 1C, a second via pattern132A is formed on the second interconnect layer131A. In some embodiments, a first via pattern122A (shown inFIG. 2) are formed on the first interconnect layer121A, but may not be seen in the illustrative cross-sectional view. In some embodiments, the second via pattern132A includes a plurality of features1321(labeled inFIG. 2) that may be offset or spaced apart from one another, as will be described in further detail below. The second via pattern132A may be formed by lithography, etching, and plating processes, or other suitable techniques. A material of the second via pattern132A may be or may include copper, aluminum, tungsten, silver, metal alloy, combinations thereof, or the like. In some embodiments, the first via pattern122A formed on the first interconnect layer121A is formed by the same materials, at the same time, and by the same processes as the second interconnect layer131A. The first via pattern122A may be isolated from the second via pattern132A. In some embodiments, the second via pattern132A and the first via pattern122A have rectangular shaped cross-sectional profiles. It is appreciated that other cross-sectional profiles may be used, such as a trapezoidal shape or the like.

Referring toFIG. 1DandFIG. 2, an insulating layer140A is formed on the dielectric material layer110A to cover the first interconnect layer121A, the first via pattern122A, the second interconnect layer131A, and the second via pattern132A. The insulating layer140A may also cover the first via pattern122A that is formed on the first interconnect layer121A in the functional circuit region CR. The second via pattern132A and the first via pattern122A formed on the first interconnect layer121A may be accessibly revealed by the insulating layer140A for further connection.

The insulating layer140A may be or may include a lamination film. For example, a material of the insulating layer140includes ABF, die attach film (DAF), prepreg, resin coated copper (RCC), a polymer material (e.g., PBO, PI, BCB), a molding compound, and/or the like. The insulating layer140A may have a Young's modulus ranging from about 3 GPa to about 20 GPa. In some embodiments in which the insulating layer140A is formed of ABF, the ABF is laminated on the structure shown inFIG. 1C, and external energy (e.g., heat and/or pressure) may be applied to soften the ABF, so that a flat-top surface is formed. In some embodiments, applying the external energy helps the insulating layer140A to fill into the spaces between the first interconnect layer121A and the second interconnect layer131A. Other technique (e.g., spin-coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), the like, a combination thereof, etc.) may be used to form the insulating layer140A. A planarization process is optionally performed to level the insulating layer140A, the second via pattern132A, and the first via pattern122A. For example, the top surface132tof the second via pattern132A and the top surface122tof the first via pattern122A are substantially leveled with the top surface140tof the insulating layer140A. In some embodiments, the top surface140tof the insulating layer140A is higher than the top surface132tof the second via pattern132A and the top surface122tof the first via pattern122A, relative to the top surface of the dielectric material layer110A. For example, the difference between the top surface140tof the insulating layer140A and the top surface132tof the second via pattern132A (or the top surface122tof the first via pattern122A) is about 2 μm.

Continue toFIG. 2, a plurality of device areas (DA1, DA2, DA3, DA4, and DA5) may be distributed in rows and columns over the temporary carrier TC in the top view. In some embodiments, the periphery of each device area (DA1, DA2, DA3, DA4, and DA5) is square or rectangular in shape. Other shapes (circle, ellipse, polygon, etc.) may be possible in accordance with other embodiments. In some embodiments, the device areas (DA1, DA2, DA3, DA4, and DA5) are spaced from one another by a scribe area SL. For example, the semiconductor structure is separated by cutting in the scribe area SL between and circumscribing device areas (DA1, DA2, DA3, DA4, and DA5) during a singulation process. It is noted that the first via pattern122A shown inFIG. 2is illustrated in a schematic and simplified manner, and the first via pattern122A may include various route features combined in various ways depending on circuit design.

In some embodiments, the second via pattern132A of each device area (DA1, DA2, DA3, DA4, or DA5) may include the features1321arranged in a discontinuous manner along at least a portion of the perimeter of the corresponding functional circuit region CR. In some embodiments, as shown inFIG. 2, the device areas (DA1, DA2, DA4, and DA5) are arranged at the periphery of the array, and the device area DA3arranged in the middle of the array. The second via patterns132A of the device areas (DA1, DA2, DA4, and DA5) may be formed at two neighboring corners that are close to the device area DA3. In some embodiments, the features1321of the second via pattern132A of the device area DA3are formed at each corner of the functional circuit region CR. In some embodiments, each of the device areas (DA1, DA2, DA3, DA4, and DA5) includes the second via pattern132A formed at each corner of the corresponding functional circuit region CR.

In some embodiments, the features1321of the second via pattern132A in each device area may be arranged in an end-to-end manner in the top view. The ends of the features1321may be spaced apart from one another by the pitch1321g. The insulating layer140A is formed between the ends of the features1321to isolate the features1321from one another. For example, the pitch1321gbetween the adjacent features1321is non-zero. The pitch1321gmay be less than a length of the corresponding side120aof the functional circuit region CR. In some embodiments, the pitch1321gis about 29 μm. The pitch1321gmay be greater than 29 μm in accordance with some other embodiments. It is noted that the pitch1321gmay vary and scale with device size, process technology, and manufacturer, and the pitch is not restricted. In some embodiments, each feature1321has a generally rectangular shape along its length in the top view. In some embodiments, the feature1321formed at each corner of the seal ring region SR in an L-shape includes the length1321L extending along a first direction and the length1321L′ extending along a second direction. The first direction and the second direction may be substantially perpendicular to each other. The lengths (1321L and1321L′) of the respective feature1321may be substantially the same. Alternatively, the lengths (1321L and1321L′) of the respective feature1321are different, so that the feature1321may have a long side and a short side connected to the long side. The features1321of the second via pattern132A may be formed in any suitable shape, such as a rectangular shape, a T-shape, an octagon-shape, a right triangle-shape, a cross-shape, combinations thereof, etc. The various dimensions of the feature1321, such as the length, width, and distance of the gap, may include any suitable value, and these values may depend on process and/or product requirements.

Referring toFIG. 1EandFIG. 3, additional interconnect layers, additional via patterns, and additional insulating layers may then be formed over the insulating layer140A, the first via pattern122A, and the second via pattern122A. For example, the first interconnect layer121B is formed on the insulating layer140A and the first via pattern122A (labeled inFIG. 2) corresponding to the functional circuit region CR. The first interconnect layer121B may be in physical and electrical contact with the first via pattern122A. The second interconnect layer131B may be formed on the insulating layer140A and the second via pattern122A corresponding to the seal ring region SR to be in physical and electrical contact with the second via pattern122A. The first interconnect layer121B and the second interconnect layer131B at the second level may include the same or similar material as the interconnect layers at the first level. For example, the second interconnect layer131B is formed simultaneously as, and may be formed of a same material as, the first interconnect layer121B.

Next, the second via pattern132B including a plurality of features1322may be formed on the second interconnect layer131B within the seal ring region SR. The first via pattern (not shown) may be formed on the first interconnect layer121B in the functional circuit region CR by a same material, at a same time, and by a same process as the second via pattern132B. The first via pattern and the second via pattern132B at the second level may include the same or similar materials as the underlying interconnect layers. Subsequently, the insulating layer140B may be formed on the insulating layer140A to cover the first interconnect layer121B, the first via pattern (not shown), the second interconnect layer131B, and the second via pattern132B. The forming process and the material of the insulating layer140B may the same or similar as the underlying insulating layer140A, so the detailed descriptions are not repeated for simplicity.

In some embodiments, the sequence of these process steps is repeated several times with simultaneous processes performed for the circuits (e.g., first interconnect layers (121C,121D, and121E) and first via pattern vertically connecting adjacent first interconnect layers) and the seal ring structures (e.g., second interconnect layer (131C,131D, and131E) and the second via pattern (132C and132D) vertically connecting adjacent second interconnect layers) covered by the insulating layers (140C and140D). Although four of the insulating layers and the interconnect layers and five of the via patterns are illustrated inFIG. 1E, any number of the insulating layers, the interconnect layers, and the via patterns may be formed over the temporary carrier TC. The second interconnect layers (131A-131E) and the second via patterns (132A-132D) formed in the seal ring region SR may be viewed as a seal ring structure130. The first interconnect layers (121A-121E) and the first via patterns (not shown) formed in the functional circuit region CR may be viewed as a functional circuit structure120.

Continue toFIG. 3, it is noted that the second interconnect layer131E of the seal ring structure130and the insulating layers (140A-140D) covering the seal ring structure130are not shown for clarity. The features1322of the second via pattern132B at the second level may be formed in an L-shape. In some embodiments, the features (1323and1324) of the second via pattern (132C and132D) are also formed in an L-shape. It is noted that the configurations of the features (1321-1324) of the second via pattern (132A-132D) may be replaced with any configuration of the second via pattern described elsewhere herein, and variations thereof may be carried out while still remaining within the disclosure.

In some embodiments, at least two adjacent levels of the second via patterns are misaligned from one another. For example, the features1322of the second via pattern132B at the second level is laterally offset relative to the features1321of the second via pattern132A at the first level in the cross section. The features1322of the second via pattern132B formed on the second interconnect layer131B and the features1321of the second via pattern132A formed on the second interconnect layer131A may be staggered. In some embodiments, in the cross-sectional view, a vertical centerline VL2of the feature1322of the second via pattern132B at the second level is offset from a vertical centerline VL1of the feature1321of the second via pattern132A at the first level. In some embodiments, in the cross-sectional view, the features (1321and1323) at the first and third levels are substantially aligned, the features (1322and1324) at the second and fourth levels are substantially aligned, and the feature1321at the first level may be misaligned with the feature1322at the second level. In some embodiments, the second via pattern at each level is staggered from one level of the second via patterns, in the cross-sectional view. Alternatively, the second via patterns (132A-132D) may be aligned or may be slightly misaligned with one another due to formation and/or alignment process variations.

Turning back toFIG. 1E, a dielectric layer151A may be formed on the first interconnect layer121E and the second interconnect layer131E. In some embodiments, the dielectric layer151A is formed differently from the underlying insulating layers (140A-140D). For example, the insulating layers (140A-140D) may be formed of a material such as ABF, while the dielectric layer151A may be formed from a different material and/or a different thickness, such as by being formed of polymer material (e.g., PBO, PI, BCB, etc.). In some embodiments, the Young's modulus of the dielectric layer151A may be less than that of one of the underlying insulating layers (140A-140D). For example, the dielectric layer151A serves as stress buffer layer. However, any combination of materials may be utilized. In some embodiments, a dielectric material is formed by a suitable process, such as spin-on coating, CVD, PVD, and/or the like, and then the dielectric material is patterned to form the dielectric layer151A having openings that expose at least portions of underlying conductive features (e.g., the first interconnect layer121E and the second interconnect layer131E).

The seal ring structure130may further include the patterned conductive layer133A, and the functional circuit structure120may further include the patterned conductive layer123A. For example, the patterned conductive layers123A and133A may be respectively formed on the dielectric layer151A and into the openings of the dielectric layer151A to be in physical contact with the underlying conductive features (e.g., first interconnect layer121E and the second interconnect layer131E). For example, the patterned conductive layer123A is formed within the functional circuit region CR to be electrically connected to the first interconnect layer121E at the topmost level of the functional circuit stack, and the patterned conductive layer133A is formed within the seal ring region SR at the topmost level of the seal ring stack. The patterned conductive layer123A may be formed by a same material, at a same time, and by a same process as the patterned conductive layer133A. In some embodiments, the via portions of the patterned conductive layers123A and133A laterally covered by the dielectric layer151A have tapered profiles. Alternatively, the sidewalls of the via portions of the patterned conductive layers123A and133A are substantially vertical. In some embodiments, the patterned conductive layer133A is omitted.

The dielectric layer151B and the patterned conductive layer123B are optionally formed on the dielectric layer151A. For example, the dielectric layer151B having openings is formed on the dielectric layer151A to cover the patterned conductive layers123A and133A, and then the patterned conductive layer123B is formed on the dielectric layer151B and extends into the openings of the dielectric layer151B to be in physical and electrical contact with the patterned conductive layer123A. In some embodiments, only patterned conductive layer123A is accessibly revealed by the openings of the dielectric layer151B, and the patterned conductive layer123B is buried in the dielectric layer151B. Alternatively, at least a portion of the patterned conductive layer123B is accessibly revealed by the dielectric layer151B for further connection.

In some embodiments, the patterned conductive layer123B and the underlying patterned conductive layer123A are formed within the functional circuit region CR. The functional circuit structure120may further include the patterned conductive layer123B. In some embodiments, the patterned conductive layer123B includes under-bump metallization (UBM) pads formed on the patterned conductive layer123A. For example, the UBM pad may include multi-layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Although other arrangements of conductive materials (e.g., copper/nickel/gold or the like) and layers may be used. In some embodiments, the dielectric layer151B and the patterned conductive layer123B are omitted, and the patterned conductive layer123A includes UBM pads for further electrical connection.

Referring toFIG. 1F, a first semiconductor device200is placed on the patterned conductive layer123B. In some embodiments, each of the device areas (shown inFIG. 2) includes at least one first semiconductor devices200mounted thereon. In some embodiments, a plurality of first semiconductor devices200is mounted within the device area. For example, conductive terminals210of the first semiconductor device200are substantially coupled to the respective UBM pad of the patterned conductive layer123B by a bonding process (e.g., a reflow process). The conductive terminals210may be or may include ball grid array (BGA), controlled collapse chip connection (C4) bumps, solder balls, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, and/or the like. In some embodiments, the first semiconductor device200has the conductive terminals210distributed at one side, and contact pads220distributed at the opposing side for further electrical connection. Alternatively, the contact pads220are omitted.

The first semiconductor device200may be or may include one or more semiconductor dies, such as a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof. In some embodiments, the first semiconductor device200includes more than one of the same types of die, or may include different types of dies. The above examples are provided for illustrative purposes only, and other embodiments may utilize additional elements for a given application.

Referring toFIG. 1G, an insulating encapsulation300is formed on the dielectric layer151B to cover the first semiconductor device200. The insulating encapsulation300may extend along the sidewalls200sof the first semiconductor device200and may be in contact with (or surround) the conductive terminals210and the patterned conductive layer123B. In some embodiments, the insulating encapsulation300includes molding compound, epoxy, or the like, and may be formed by compression molding, transfer molding, or the like. In some embodiments, the insulating encapsulation300includes a molding underfill. In some embodiments, a release film RF is attached to the first semiconductor device200and covers the contact pads220, and then the insulating material is laterally dispensed and flows through the gaps between the first semiconductor device200and the dielectric layer151B. A curing process may be performed to solidify the insulating material, and then the release film RF is removed to accessibly reveal the contact pads220. It is noted that the release film RF is illustrated in phantom to show it may not be present after the formation of the insulating encapsulation. In some embodiments in which a plurality of first semiconductor devices200mounted on the device areas, the insulating encapsulation300overlying the dielectric layer151B laterally covers each of the first semiconductor devices200for protection. In some other embodiments, the first semiconductor devices200are buried in the insulating encapsulation300.

Referring toFIG. 1Hand also with reference toFIG. 1G, the temporary carrier TC is removed to expose the dielectric material layer110A. The resulting structure shown inFIG. 1Gmay be turned upside down and placed on a tape frame TF for further processing. In some embodiments, the temporary carrier TC is released from the dielectric material layer110A using a thermal process to alter the adhesive properties of the release layer (not shown) disposed between the dielectric material layer110A and the temporary carrier TC. Other processes (e.g., grinding, mechanical peeling, etching, combinations thereof, or the like) may be used. In some embodiments, after de-bonding the temporary carrier TC, the resulting structure may be flipped over to be attached to the tape frame. In some other embodiments, the step of flipping is performed prior to the de-bonding process.

After the dielectric material layer110A is exposed, a portion of the dielectric material layer110A may be removed to form the dielectric layer110having openings110p. For example, the dielectric layer110is formed by lithography and etching, laser drilling, or other suitable patterning process. The openings110pof the dielectric layer110may accessibly reveal at least a portion of the first interconnect layer121A in the functional circuit region CR for further electrical connection. For example, the contact pads of the first interconnect layer121A are accessibly revealed by the openings110pof the dielectric layer110for the subsequently formed structure landing thereon. In some embodiments, the inner sidewalls of the dielectric layer110that define the openings110pare inclined. For example, the openings110pof the dielectric layer110have tapered profiles. In some embodiments, the openings110pof the dielectric layer110are tapered toward the first interconnect layer121A. The openings110pof the dielectric layer110and the via portions of the patterned conductive layer123A may be tapered toward the opposing directions.

Referring toFIG. 1Iand also with reference toFIG. 1H, a singulation process is performed and a second semiconductor device400may be placed on the dielectric layer110and electrically coupled to the first interconnect layer121A. For example, a pre-soldering process is optionally performed on the exposed surfaces of the first interconnect layer121A within the openings110pof the dielectric layer110. Next, the singulation process is performed to separate the resulting structure into a plurality of semiconductor structures. The singulation process may be performed using any suitable dicing tool (e.g., a blade, a saw, a laser drill, an etching process, and the like, or combinations thereof) to cut through materials of the different layers along the scribe area (shown inFIG. 2). For example, the dicing tool cuts through the dielectric layer110, the underlying insulating layers (140A,140B,140C, and140D), the underlying dielectric layers (151A and151B), and the underlying insulating encapsulation300. After the singulation process, the dielectric layer110, the underlying insulating layers (140A,140B,140C, and140D), the underlying dielectric layers (151A and151B), and the underlying insulating encapsulation300may have substantially coterminous sidewalls100s. In some embodiments, the dielectric layer110, the underlying insulating layers (140A,140B,140C, and140D), the metal structure (e.g., including the functional circuit structure120and the seal ring structure130) in the insulating layers (140A,140B,140C, and140D), the underlying dielectric layers (151A and151B), the patterned conductive layers (123A,123B, and133A) are collectively viewed as a package component100. In some embodiments, the package component100is referred to as the package substrate.

In some embodiments, the semiconductor structures are removed from the tape frame TF after the singulation process. Next, the second semiconductor device400is disposed on the dielectric layer110after removing the tape frame TF. In some other embodiments, placing the second semiconductor device400is performed prior to removing the tape frame TF. For example, contact bumps410of the second semiconductor device400extend into the openings110pof the dielectric layer110and mounted on the first interconnect layer121A. The contact bumps410of the second semiconductor device400may be or may include solder balls, although any suitable types of electrical connectors may be utilized. In some embodiments, the contact bumps410of the second semiconductor device400are in contact with the pre-solder layer (not shown), a reflow process may be performed to bond the contact bumps410of the second semiconductor device400to the first interconnect layer121A. After the reflow process, the contact bumps410may fill the openings110pof the dielectric layer110. Other bonding techniques (e.g., thermos-compression bonding, hybrid bonding, metal-to-metal bonding, or the like) may be used to couple the second semiconductor device400to the first interconnect layer121A.

The second semiconductor device400may be or may include one or more semiconductor dies, such as a logic die (e.g., CPU, GPU, SoC, microcontroller, etc.), a memory die (e.g., DRAM die, SRAM die, etc.), a power management die (e.g., PMIC die), a RF die, a sensor die, a MEMS die, a signal processing die (e.g., DSP die), a front-end die (e.g., AFE dies), the like, or combinations thereof. In some embodiments, the second semiconductor device400includes more than one of the same types of die, or may include different types of dies. In some embodiments, the second semiconductor device400performs the same function as the first semiconductor device200. Alternatively, the second semiconductor device400and the first semiconductor device200perform different functions. The above examples are provided for illustrative purposes only, and other embodiments may use additional elements for a given application.

In some embodiments, after the second semiconductor device400is coupled to the first interconnect layer121A, an underfill layer500is formed on the dielectric layer110. In some embodiments, after removing the tape frame TF, the second semiconductor device400is disposed over the package component100, and then the underfill layer500is formed. In some other embodiments, forming the underfill layer500is performed prior to removing the tape frame TF. For example, the underfill layer500fills the gap between the dielectric layer110and the second semiconductor device400to surround the contact bumps410for protection. The underfill layer500may extend along the sidewalls400sof the second semiconductor device400. The underfill layer500may include a liquid epoxy that is dispensed between the second semiconductor device400and the dielectric layer110and then cured to harden. The underfill layer500may be formed by a capillary flow process after the second semiconductor device400is attached, or may be formed by a suitable deposition method before the second semiconductor device400is attached. In other embodiments, no underfill is uses. The underfill layer500may be replaced with a molding compound formed by a molding process.

Referring toFIG. 1J, a retaining ring600may be attached to the dielectric layer110and surround the second semiconductor device400. In some embodiments, after forming the underfill layer500, the retaining ring600is placed on the dielectric layer110. In some other embodiments, placing the retaining ring600is performed prior to removing the tape frame TF. The retaining ring600may be used to protect the second semiconductor device400, to add stability to the resulting structure, to dissipate heat from the second semiconductor device400, and/or to provide a distributed heat transfer from the underlying metal structure to the environment. A material of the retaining ring600may be or may include steel, stainless steel, copper, aluminum, gold, metal alloy, ceramic, combinations thereof, or the like. An adhesive layer (not shown) is optionally disposed between the retaining ring600and the dielectric layer110to secure the retaining ring600to the dielectric layer110. In some embodiments, the adhesive layer includes a thermal interface material (TIM) layer. The height of the retaining ring600may be greater than the thickness of the second semiconductor device400. In other embodiments, the height of the retaining ring600is less than the thickness of the second semiconductor device400. In some embodiments, the outer sidewall600S of the retaining ring600is not aligned with the coterminous sidewalls100of the package component100. For example, the difference D between the outer sidewall600S of the retaining ring600and the coterminous sidewalls10sis about 10 μm. It is noted that the difference D may vary depending on product and process requirements. Alternatively, the retaining ring600and the adhesive layer attached to the retaining ring600are omitted.

In some embodiments, a plurality of external connectors700is formed on the contact pads220of the first semiconductor device200for further electrical connection after placing the retaining ring600. The external connectors700may be formed as any suitable connector (e.g., BGAs, C4 bumps, solder balls, or the like). In some embodiments, the external connectors700are formed by a ball mounting process on the exposed portions of the contact pads220to be electrically coupled to the first semiconductor device200. In some embodiments in which the first semiconductor device200does not include the contact pads220, the external connectors700are omitted. Up to here, manufacturing a semiconductor package10is substantially complete.

In some embodiments, the semiconductor package10includes the insulating encapsulation300laterally covering the first semiconductor device200, and the underfill layer500disposed between the second semiconductor device400and the package component100for protection. The semiconductor package10optionally includes the retaining ring600surrounding the second semiconductor device400for protection and stability improvements. In some other embodiments, the seal ring structure130of the package component100is thermally coupled to the retaining ring600for thermal dissipation. The first semiconductor device200and the second semiconductor device400may be located at two opposite sides of the package component100and electrically connected to the functional circuit structure120of the package component100.

The package component100of the semiconductor package10includes the seal ring structure130located within the seal ring region SR, and the functional circuit structure120located within the functional circuit region CR. The seal ring structure130is electrically isolated from the functional circuit structure120and may be electrically floating in the package component100. Since the seal ring structure130is arranged to at least partially surround the functional circuit structure120at each level, the seal ring structure130may provide protection to the functional circuit structure120from the crack propagation during the processes (e.g., de-bonding the temporary carrier TC or tape frame TH, singulation, laser drilling, etc.).

The second via patterns (e.g.,132A,132B,132C,132D) of the seal ring structure130at each level in the package component100may surround at least two adjacent corners of the functional circuit region CR as a non-continuous line. By such configuration, voids formed in the package component100during the lamination process or reliability testing may also be eliminated. If the second via pattern is formed as a closed-loop ring, voids generating in the respective level of the package component100will be retained in the area confined by the second via pattern. The presence of the voids in the package component may deleteriously affect performance of the package component. For example, when the warpage issue arises, cracks may develop and/or propagate due to the presence of the voids. Experience has shown that for the device areas arranged in the array as shown inFIG. 2, corner regions CC are the areas where potential cracking would be concentrated. Thus, the second via patterns of the seal ring structure130disposed on these corner regions CC and arranged in a discontinuous manner may provide protection to the functional circuit structure120in the functional circuit region CR from cracking and also ensure a void-free environment of the package component100. It is understood that additional features can be added in the seal ring structure130, and some features of the second via pattern described herein may be replaced or eliminated for additional embodiments of the seal ring structure.

FIG. 4Ais a schematic top view of a package component having a seal ring structure in accordance with some embodiments, andFIG. 4Bis a schematic perspective view of a seal ring structure B shown inFIG. 4Ain accordance with some embodiments. Unless specified otherwise, the materials and the formation methods of the components are essentially the same as the like components, which are denoted by like reference numerals shown inFIGS. 1A-3. It is noted that the insulating layer covering the functional circuit structure and the seal ring structure is omitted for ease of illustration. It is also noted that two-layered seal ring structure is shown for illustrative only, and the seal ring structure is not limited to any specific number of layers in the disclosure.

Referring toFIGS. 4A-4B, the seal ring structure230located within the seal ring region SR at least includes the second interconnect layers (231A and231B) and the second via patterns (232A and232B). The second via pattern232A may connect adjacent second interconnect layers (231A and231B), and the second via pattern232B may be disposed on the second interconnect layer231B. The functional circuit structure120including the first via patterns (e.g.,122B) and the first interconnect layers (not shown) is formed in the functional circuit region CR and may be surrounded by the seal ring region SR. The second via patterns and the second interconnect layers located within the seal ring region SR may be formed simultaneously with the equivalent metal levels of the functional circuit structure120located within the functional circuit region CR. The seal ring structure230may be spaced apart from the functional circuit structure120by the buffer region BR. The buffer region BR may be interposed between the seal ring region SR and the functional circuit region CR to prevent damage to the functional circuit structure120in the functional circuit region CR.

In some embodiments, the second via pattern232B of the seal ring structure230includes a plurality of features2322spaced apart from one another. At least one of the features2322may be formed in an L-shape. For example, each feature (e.g.,2322V,2322X,2322Y,2322Z) includes a first side2322aand a second side2322bconnected to the first side2322a. The first side2322aof the respective feature2322may extend along a first side120aof the functional circuit region CR, and the second side2322bof the respective feature2322may extend along a second side120bof the functional circuit region CR that is connected to the first side120a. The first side120aand the second side120bmay be substantially perpendicular to each other. For example, the first side2322aand the second side2322bform a right angle therebetween. Alternatively, the first side2322aand the second side2322bmay not be perpendicular to each other. For example, an acute angle or an obtuse angle may be formed between the first side2322aand the second side2322b. In some embodiments, a length2322L of the first side2322ais greater than a length2322L′ of the second side2322b. Under this scenario, the first side2322ais referred to as the long side of the respective feature2322and the second side2322bis referred to as the short side of the feature2322. In some embodiments, a width2322W of the first side2322aof the respective feature2322is substantially the same as a width2322W′ of the second side2322bof the respective feature2322V. Alternatively, the widths (2322W and2322W′) may be different.

In some embodiments, the features2322are all formed in the L-shape. For example, each feature (e.g.,2322V,2322X,2322Y, and2322Z) has substantially the same width and length. In some other embodiments, the length and/or width of the features2322may be different. Alternatively, the features2322disposed at corners may be formed in different shapes. In some embodiments, the features2322located within the seal ring region SR may be flipped vertically, flipped horizontally, rotated 90 degrees, rotated 180 degrees, or combinations thereof, in the top view. For example, the first feature2322V is disposed in proximity to the first side120aof the functional circuit region CR and has the first side2322a(e.g., the long side) extending parallel to the first side120a. The first side2322aof the first feature2322V may be longer than the first side120aof the functional circuit region CR, and the second side2322bof the first feature2322V may be shorter than the second side120bof the function circuit region CR. Alternatively, the first side2322aof the first feature2322V may be shorter than the first side120aof the functional circuit region CR. In some embodiments, the corner of the first feature2322V may substantially correspond to the corner of the function circuit region CR.

The second feature2322X may be, relative to the first feature2322V, rotated 90 degrees in the clockwise direction. For example, the long side of the second feature2322X extends parallel to the second side120bof the functional circuit region CR, and the short side of the second feature2322X extends along the third side120cof the functional circuit region CR. In some embodiments, the first feature2322V and the second feature2322X may be spatially separated from each other through the insulating layer (not shown). For example, the first side2322a′ of the second feature2322X and the second side2322bof the first feature2322V may be offset lengthwise relative to each other to overlap therewith along their length, and be spaced apart therefrom widthwise. The second side2322bof the first feature2322V may be interposed between the functional circuit structure120and the first side2322a′ of the second feature2322X. In some embodiments, the end of the first side2322a′ of the second feature2322X and the end of the second side2322bof the first feature2322V are offset by a lateral distance OD1. The lateral distance OD1may be non-zero. It is appreciated that the lateral distance OD1may depend on the product and process requirements and is not limited to any specific value in the disclosure.

In some embodiments, the functional circuit region CR has a generally rectangular shape in the top view, and the features2322are arranged along the four sides (e.g.,120a,120b,120c, and120d) of the functional circuit region CR. The features2322of the second via pattern232B may be arranged separately from one another and along the perimeter of the functional circuit region CR. For example, the arrangement of the third feature2322Y and the fourth feature2322Z is similar to the arrangement of the first feature2322V and the second feature2322X, but turns 180 degrees in the clockwise direction. The third feature2322Y may have the first side2322a″ extending along the third side120cof the functional circuit region CR, and the second side2322b″ connected to the first side2322″ and extending along the fourth side120dof the functional circuit region CR. The first side2322a″ may be the long side of the L-shape and the second side2322b″ may be the short side of the L-shape. In some embodiments, the third feature2322Y may be rotated 90 degrees in the clockwise direction, relative to the second feature2322X. In some embodiments, the third feature2322Y is offset and spatially separated from the second feature2322X. For example, the end of the first side2322a″ of the third feature2322Y is staggered lengthwise relative to the end of the second side2322b′ of the second feature2322X to overlap therewith along their length, and be spaced apart therefrom widthwise.

The fourth feature2322Z may be similar to the third feature2322Y, but rotated 90 degrees in the clockwise direction relative to the third feature2322Y. The first side2322a′″ (e.g., the long side) of the fourth feature2322Z may extend along the fourth side120dof the functional circuit region CR, and the second side2322b′″ (e.g., the short side) of the fourth feature2322Z connected to the first side2322a′″ may extend along the first side120aof the functional circuit region CR. The third feature2322Y, the fourth feature2322Z, and the first feature2322V may be staggered and spatially separated from one another. For example, the end of the first side2322a′″ of the fourth feature2322Z is staggered lengthwise relative to the end of the second side2322b″ of the third feature2322Y to overlap therewith along their length, and be spaced apart therefrom widthwise. The second side2322b″ of the third feature2322Y may be interposed between the functional circuit structure120and the first side2322a′″ of the fourth feature2322Z. The end of the second side2322b′″ of the fourth feature2322Z is staggered lengthwise relative to the end of the first side2322aof the first feature2322V to overlap therewith along their length, and be spaced apart therefrom widthwise. The first side2322aof the first feature2322V may be interposed between the functional circuit structure120and the second side2322b′″ of the fourth feature2322Z.

Continue toFIG. 4B, the arrangement of the features2322of the second via pattern232B formed on the second interconnect layer231B and the arrangement of the features2321of the second via pattern232A formed on the second interconnect layer231A may be similar. In some embodiments, the arrangements of the second via pattern232B and the second via pattern232A are staggered in a cross section. For example, in the cross-sectional view, a vertical centerline VL2′ of the first side2322aof the first feature2322V is laterally offset from a vertical centerline VL1′ of the first side2321aof the first feature2321V. In some embodiments, a vertical centerline VL2′ of the second side2322bof the first feature2322V at the second level is laterally offset from a vertical centerline VL1′ of the second side2321bof the first feature2321V at the first level. In some other embodiments, the first sides (2321aand2322a) of the first features (2321V and2322V) at adjacent levels are substantially aligned, while the second sides (2321band2322b) of the first features (2321V and2322V) at adjacent levels are staggered. Alternatively, the first sides (2321aand2322a) of the first features (2321V and2322V) at adjacent levels are substantially staggered, while the second sides (2321band2322b) of the first features (2321V and2322V) at adjacent levels are substantially aligned. The first side2321aof the first feature2321V at the first level may be completely offset from or partially overlap the first side2322aof the first feature2322V at the second level, in the top-down view. Alternatively, the first side2321aof the first feature2321V at the first level may be substantially aligned with the first side2322aof the first feature2322V at the second level, in the top-down view. In some embodiments, the features2322are formed in a T-shape or other suitable shape(s).

In some embodiments, the second via pattern (232A or232B) of the seal ring structure230is replaced with the second via pattern described elsewhere herein, and variations thereof may be carried out while still remaining within the disclosure. It is noted that the arrangement shown inFIG. 4Bis for illustrative purposes only, and the second via patterns of the seal ring structure230may have different shapes in the top view. It is appreciated that the seal ring structure may include additional features or fewer features at different levels for eliminating voids and preventing cracking.

FIG. 5Ais a schematic top view of a package component having a seal ring structure in accordance with some embodiments, andFIG. 5Bis a schematic perspective view of a seal ring structure C shown inFIG. 5Ain accordance with some embodiments. Unless specified otherwise, the materials and the formation methods of the components are essentially the same as the like components, which are denoted by like reference numerals shown inFIGS. 1A-3. It is noted that the insulating layer covering the functional circuit structure and the seal ring structure is omitted for ease of illustration. It is also noted that two-layered seal ring structure is shown for illustrative only, and the seal ring structure is not limited to any specific number of layers in the disclosure.

Referring toFIGS. 5A-5Band also with reference toFIG. 4A, the difference between the structure shown inFIG. 5Aand the structure shown inFIG. 4Alies in the arrangement of the seal ring structure330. For example, the seal ring structure330located within the seal ring region SR at least includes the second interconnect layers (331A and331B) and the second via patterns (332A and332B). The second via pattern332A may connect adjacent second interconnect layers (331A and331B) and the second via pattern332B is disposed on the second interconnect layer331B. The second via pattern332B may include a plurality of features3322arranged as parallel and non-continuous lines along the perimeter of the functional circuit region CR. The features3322may be spaced apart from one another.

For example, the second via pattern332B includes a first portion33220of the features (e.g.,3322a,3322b,3322c, and3322d) arranged along the outer path SR2of the seal ring region SR, and a second portion33221of the features (e.g.,3322e,3322f, and3322g) arranged along the inner path SR1of the seal ring region SR. The inner path SR1of the seal ring region SR may be in proximity to the functional circuit region CR, and the outer path SR2of the seal ring region SR may be away from the functional circuit region CR relative to the inner path SR1. In other words, the inner path SR1is between the functional circuit region CR and the outer path SR2. The inner path SR1and the outer path SR2may follow the boundary of the functional circuit region CR. For example, the inner path SR1and the outer path SR2are substantially rectangular in shape although, in other embodiments, the inner path SR1and the outer path SR2may be irregular or may have a different shape in the top view.

For example, the second portion33221of the features3322may be arranged along the inner path SR1to surround the four sides of the functional circuit region CR, and the first portion33220of the features3322may be arranged along the outer path SR2to surround the second portion33221. In some embodiments, the first portion33220of the features (e.g.,3322a,3322b,3322c, and3322d) is arranged end to end. For example, the feature3322ahas a rectangular shape along its length3322L as well as a rectangular cross section. It is appreciated that other cross sectional profiles (e.g., trapezoid, inverted trapezoid, or the like) may be used. In some embodiments, the rest of the features3322are formed in the same (or similar) shapes and dimensions as the feature3322a. It is noted that the features3322of the second via pattern332B may take on any shape and be strategically placed within the seal ring region SR.

The adjacent features arranged along the outer path SR2or the inner path SR1may be spaced apart from one another with a gap SP1. The neighboring features arranged along the outer path SR2may be spaced apart from each other with a substantially uniform gap SP1. In other embodiments, the features arranged along the outer path SR2may be separated by different distances. Alternatively, one or more features arranged along the outer path SR2may be spaced apart by the same distance, while others are separated by different distances. The various dimensions of the feature, such as the length, width, and distance of the gap, may include any suitable value. The features arranged along the inner path SR1may have the same or similar arrangement as the features arranged along the outer path SR2. It is also noted that the number of the features3322disposed along the outer path SR2and the inner path SR1shown inFIG. 5Ais for illustrative purposes only, other numbers and arrangements are possible.

The features arranged along the inner path SR1and the features arranged along the outer path SR2may be offset lengthwise relative to one another to overlap therewith along their length, and be spaced apart therefrom widthwise. For example, the second portion33221of the features3322arranged along the inner path SR1and the first portion33220of the features3322arranged along the outer path SR2are spaced apart transversely by a pitch SP. In some embodiments, each feature (e.g.,3322e,3322f, and3322g) arranged along the inner path SR1may correspond to one of the gaps SP between the features (e.g.,3322a,3322b,3322c, and3322d) arranged along the outer path SR2. The insulating layer (not shown) may be located in the gaps SP between the ends of the features3322along the outer path SR2and the inner path SR1to isolate the features3322from one another, and the insulating layer may also be located in the pitch SP1between the inner path SR1and the outer path SR2.

In some embodiments, the features (e.g.,3322e,3322f, and3322g) arranged along the inner path SR1are longitudinally offset from the associated features (e.g.,3322a,3322b,3322c, and3322d) arranged along the outer path SR2. For example, each feature3322includes a first end SE1and a second end SE2opposite to each other, and a longitudinal distance OD2between the ends of the associated features (e.g., the second end SE2of the feature3322aand the first end SE1of the feature3322e) disposed in proximity to each other is non-zero. In some embodiments, a longitudinal distance OD2′ between the ends of the associated features (e.g., the first end SE1of the feature3322band the second end SE2of the feature3322e) in proximity to each other may also be non-zero. In some embodiments, the longitudinal distances OD2and OD2′ are substantially equal to each other. For example, the longitudinal distance(s) OD2and/or OD2′ is about 50 μm. Alternatively, the longitudinal distances OD2and OD2′ are different. It is noted that the longitudinal distances (OD2and OD2′) may be adjusted depending on the process and product requirements and construe no limitation in the disclosure.

Continue toFIG. 5B, the arrangement of the features3322at the second level may be the same or similar to the arrangement of the features3321at the first level. In some embodiments, for the first level, the first portion3321O of the features (e.g.,3321b) is arranged along the outer path SR2of the seal ring region SR, and the second portion3321I of the features (e.g.,3321e) is arranged along the inner path SR1of the seal ring region SR. The features3322of the second via pattern332B disposed on the second interconnect layer331B may be aligned with, or offset relative to, the features3321of the second via pattern332A disposed on the second interconnect layer331A. For example, the vertical centerline VL1″ of the feature3321eat the first level and the vertical centerline VL2″ of the feature3322eat the second level are substantially aligned. In some embodiments, the ends of the feature3321eat the first level and the feature3322eat the second level may be staggered by an offset OF in a cross-sectional view. The offset OF may be non-zero. Alternatively, the offset OF is zero. In other words, the position of the feature3321eat the first level may be substantially the same as the position of the feature3322eat the second level. In some other embodiments, the vertical centerline VL1″ of the feature3321eis offset from the vertical centerline VL2″ of the feature3322e, while the offset OF therebetween is non-zero. Alternatively, the vertical centerline VL1″ of the feature3321eand the vertical centerline VL2″ of the feature3322eare transversely offset, but the ends of the features (3321eand3322e) are substantially aligned. The rest of the features3321at the first level and the rest of the features3322of the second level may have the same arrangement as the features (3321eand3322e).

It is noted that different arrangements of the features at different levels may be used. In some embodiments, the second via pattern (332A or332B) is replaced with the second via pattern described elsewhere herein, and variations thereof may be carried out while still remaining within the disclosure. It is noted that the arrangements shown inFIGS. 5A-5Bare for illustrative purposes only, the second via patterns of the seal ring structure330may have different shapes in the top view, and may include more features or fewer features at different levels as long as voids induced during processing or testing can be released by the suitable arrangement of the seal ring structure330.

FIG. 6Ais a schematic top view of a package component having a seal ring structure in accordance with some embodiments, andFIG. 6Bis a schematic perspective view of a seal ring structure shown inFIG. 6Ain accordance with some embodiments. Unless specified otherwise, the materials and the formation methods of the components are essentially the same as the like components, which are denoted by like reference numerals shown inFIGS. 1A-3. It is noted that the insulating layer covering the functional circuit structure and the seal ring structure is omitted for ease of illustration. It is also noted that two-layered seal ring structure is shown for illustrative only, and the seal ring structure is not limited to any specific number of layers in the disclosure.

Referring toFIGS. 6A-6Band also with reference toFIG. 4A, the difference between the structure shown inFIG. 6Aand the structure shown inFIG. 5Alies in the arrangement of the seal ring structure430. For example, the seal ring structure430located within the seal ring region SR at least includes the second interconnect layers (431A and431B) and the second via patterns (432A and432B). The second via pattern432A may be connected to adjacent second interconnect layers (431A and431B), and the second via pattern432B is disposed on the second interconnect layer431B. The second via pattern432B may include a plurality of first features43221spaced apart from one another and arranged along the inner path SR1′ of the seal ring region SR. The shape of the inner path SR1′ may follow the sides (or perimeter) of the functional circuit region CR. In some embodiments, the second via pattern432B includes a plurality of second features43220spaced apart from one another and arranged along the outer path SR2′ of the seal ring region SR, where the outer path SR2′ may surround the inner path SR1′. In some embodiments, the inner path SR1′ and the outer path SR2′ are substantially rectangular in shape although, in other embodiments, the inner path SR1and the outer path SR2may have different shapes in the top view.

In some embodiments, each of the first features43221has a rectangular shape along its length4322L as well as a rectangular cross-sectional profile. In some embodiments, each of the first features43221is disposed parallel to one side of the functional circuit region CR in a non-continuous manner. For example, a gap4322gis between two adjacent first features43221. The first features43221may have substantially the same dimensions. In some embodiments, the length4322L of the respective first feature43221is greater than the length of the corresponding side of the functional circuit region CR. In some embodiments, the first features43221are of different dimensions. For example, some of the first features43221extend longer than the length of the corresponding side of the functional circuit region CR, while other first features43221are shorter than the corresponding side of the functional circuit region CR. Alternatively, the length4322L of the respective first features43221is less than that of the corresponding side of the functional circuit region CR. In other embodiments, the first features43221are replaced with the second portion33221of the features shown inFIG. 5B. It is also noted that the number of the first features43221shown inFIG. 6Ais for illustrative purposes only and construe no limitation in the disclosure.

In some embodiments, the second features43220are arranged corresponding to the gaps4322gbetween the first features43221. For example, the respective second feature43220is offset lengthwise relative to the neighboring first features43221to overlap the gap4322gbetween the neighboring first features43221. The respective second feature43220may be spaced apart from the neighboring first features43221in the direction of the width. For example, the second features43220are formed in an L-shape. The second features43220may be arranged at each corner of the seal ring region SR along the outer path SR2′. For example, each of the second features43220includes a first side4322aand a second side4322bconnected to the first side4322a. The first side4322amay be longer than the second side4322b. In such embodiments, the first side4322ais referred to as the long side, and the second side4322bis referred to as the short side. In other embodiments, the lengths of the first side4322aand the second side4322bis substantially equal to each other. In some embodiments, the first side4322aof the respective second feature43220corresponds to the gap4322gbetween the neighboring first features43221. The first features43221and the second features43220may include any suitable shape, such as a T-shape, a rectangular shape, a polygonal shape, a cross-shape, and/or combinations thereof, etc. It is appreciated that any suitable shapes and/or cross-sectional profiles of the first features43221and the second features43220may be used to achieve the same result.

The second features43220may be flipped vertically, flipped horizontally, rotated 90 degrees, or rotated 180 degrees relative to one another, in the top view. For example, the first side4322aof the second feature4322V is substantially parallel to the second side120bof the function circuit region CR, and the second side4322bof the second feature4322V is substantially parallel to the first side120aof the function circuit region CR. The second feature4322X may be, relative to the second feature4322V, flipped horizontally to be arranged at the corner of the seal ring region SR. The second feature4322Y may be, relative to the second feature4322X, flipped vertically to be arranged at the corner of the seal ring region SR. The second feature4322Z may be, relative to the second feature4322Y, flipped horizontally to be arranged at the corner of the seal ring region SR. In some embodiments, two neighboring second features43220are separated by a pitch SP′, and the first feature43221is arranged corresponding to the pitch SP′. The pitch SP′ between two neighboring second features43220may be less than the length4322L of the corresponding first feature43221. For example, the first feature43221is offset lengthwise relative to the neighboring second features43220to overlap therewith along their length, and be spaced apart therefrom widthwise.

Continue toFIG. 6B, the arrangement of the second via pattern432B at the second level may be the same or similar to the arrangement of the second via pattern432A at the first level. In some embodiments, the second features43210are arranged along the outer path SR2″ of the seal ring region SR, and the first features43211are arranged along the inner path SR1″ of the seal ring region SR. The second via pattern432B disposed on the second interconnect layer431B may be aligned with, or offset relative to, the second via pattern432A disposed on the second interconnect layer431A. In some other embodiments, the second via pattern (432A or432B) is replaced with the second via pattern described elsewhere herein, and variations thereof may be carried out while still remaining within the disclosure. It is noted that the arrangements shown inFIGS. 6A-6Bare for illustrative purposes only, the second via patterns of the seal ring structure430may have different shapes in the top view, and other arrangements of the second via pattern at different levels are possible.

FIG. 7Ais a schematic top view of a package component having a seal ring structure in accordance with some embodiments, andFIG. 7Bis a schematic perspective view of a seal ring structure E shown inFIG. 7Ain accordance with some embodiments. Unless specified otherwise, the materials and the formation methods of the components are essentially the same as the like components, which are denoted by like reference numerals shown inFIGS. 1A-3. It is noted that the insulating layer covering the functional circuit structure and the seal ring structure is omitted for ease of illustration. It is also noted that two-layered seal ring structure is shown for illustrative only, and the seal ring structure is not limited to any specific number of layers in the disclosure.

Referring toFIGS. 7A-7Band also with reference toFIG. 6A, the difference between the structure shown inFIG. 7Aand the structure shown inFIG. 6Alies in the arrangement of the seal ring structure530. For example, the seal ring structure530located within the seal ring region SR at least include the second interconnect layers (531A and531B) and the second via patterns (532A and532B), where the second via pattern532A connects adjacent second interconnect layers (531A and531B) and the second via pattern532B is disposed on the second interconnect layer531B. The second via pattern532B may include a plurality of first features53221spaced apart from one another and arranged along the inner path SR1″ of the seal ring region SR. The shape of the inner path SR1″ may follow the sides (or perimeter) of the functional circuit region CR. In some embodiments, the second via pattern532B includes a plurality of second features53220spaced apart from one another and arranged along the outer path SR2″ of the seal ring region SR, where the outer path SR2″ surround the inner path SR1″. In some embodiments, the inner path SR1″ and the outer path SR2″ are substantially rectangular in shape although, in other embodiments, the inner path SR1and the outer path SR2may have different shapes in the top view.

In some embodiments, each of the second features53220has a rectangular shape along its length5322L as well as a rectangular cross-sectional profile. In some embodiments, each of the second features53220is disposed parallel to one side of the functional circuit region CR in a discrete manner. The second features53220arranged along the outer path SR2″ may have substantially the same dimensions. In some embodiments, the second features53220are of different dimensions. The length5322L of the respective second feature53220may be greater than the length of the corresponding side of the functional circuit region CR. Alternatively, the length5322L of the respective second feature53220is less than the length of the corresponding side of the functional circuit region CR. In other embodiments, the second features53220are replaced with the second portion33221of the features3322shown inFIG. 5B. It is also noted that the number of the second features53220shown inFIG. 7Ais for illustrative purposes only and construe no limitation in the disclosure.

In some embodiments, the first features53221are formed in an L-shape and arranged at each corner of the seal ring region SR along the inner path SR1″. For example, each of the first features53221includes a first side and a second side connected to the first side. In some embodiments, the first side is longer than the second side. In some other embodiments, the lengths of the first side and the second side are substantially equal. The first features53221disposed along the inner path SR1″ may be flipped vertically, flipped horizontally, rotated 90 degrees, or rotated 180 degrees, or combinations thereof, in the top view. For example, the first feature5322V is disposed corresponding to one corner of the functional circuit region CR. The first feature5322X arranged along the inner path SR1″ may be, relative to the first feature5322V, rotated 90 degrees in the clockwise direction, and may be disposed corresponding to another corner of the functional circuit region CR. In some embodiments, the first features (5322V and5322X) may be spatially separated from each other by a pitch SP″. For example, one of the second features53220overlaps lengthwise relative to the pitch SP″ of the first features (5322V and5322X) along their length, and the one of the second features53220is spaced apart from the first features (5322V and5322X) in the direction of the width. The pitch SP″ may be non-zero. The length5322L of the respective second feature53220may be greater than the pitch SP″ between the first features (5322V and5322X). Alternatively, the length5322L of the second feature53220may be substantially equal to the pitch SP″ between the first features (5322V and5322X). It is appreciated that the pitch SP″ and the length5322L may depend on the product and process requirements and are not limited to any specific value in the disclosure.

In some embodiments, the first features (5322Y and5322Z) arranged along the inner path SR1″ may be flipped vertically relative to the first features (5322V and5322X), and may be disposed corresponding to the other two corners of the functional circuit region CR. In some embodiments, the first features (5322Y and5322Z) may be separated from the first features (5322V and5322X) by the pitch SP″. In some other embodiments, the first features (5322Y and5322Z) and the first features (5322V and5322X) may be spaced apart by different amounts of pitches which may depend on the area defined by the functional circuit region CR. Alternatively, the first features53221and the second features53220may include a rectangular shape, an L-shape, a T-shape, a polygonal shape, a cross-shape, combinations thereof, or any suitable shapes that may be used to achieve the same result.

Continue toFIG. 7B, the arrangement of the second via pattern532B at the second level may be the same or similar to the arrangement of the second via pattern532A at the first level. In some embodiments, the second features53210are arranged along the outer path SR2″ of the seal ring region SR, and the first features53211are arranged along the inner path SR1″ of the seal ring region SR. The second via pattern532B disposed on the second interconnect layer531B may be aligned with, or offset relative to, the second via pattern532A disposed on the second interconnect layer531A. In some other embodiments, the second via pattern (532A or532B) is replaced with the second via pattern described elsewhere herein, and variations thereof may be carried out while still remaining within the disclosure. It is noted that the arrangements shown inFIGS. 7A-7Bare for illustrative purposes only, the second via patterns of the seal ring structure530may have different shapes in the top view, and other arrangements of the second via pattern at different levels are possible.

The second via pattern of the seal ring structure described herein may take on any shape and be strategically placed within the seal ring region SR to effectively release voids induced during processing and/or reliability testing. By the configuration of the seal ring structure in the discontinuous manner, cracking at the corner of the package component can be reduced. Moreover, sine the seal ring structure is formed at the same time and by the same process as the functional circuit structure, the seal ring structure may be fabricated without affecting other processes required to manufacture the package component. The manufacturing time and cost may be easily controlled without requiring any additional expenses.

According to some embodiments, a package component for electrically coupling a semiconductor die is provided. The package component includes an insulating layer, a functional circuit structure, and a seal ring structure. The insulating layer includes a functional circuit region and a seal ring region surrounding the functional circuit region. The functional circuit structure is embedded in the insulating layer within the functional circuit region, where the semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is embedded in the insulating layer within the seal ring region and electrically isolated from the functional circuit structure. The seal ring structure includes a stack of alternating interconnect layers and via patterns, and the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the seal ring region.

According to some alternative embodiments, a semiconductor package includes a package component and a semiconductor die. The package component includes a functional circuit structure and a seal ring structure surrounding the functional circuit structure, the seal ring structure is electrically floating in the package component, the seal ring structure includes an interconnect layer and a via pattern disposed on the interconnect layer, and the via pattern includes a plurality of first features arranged in a discrete manner along a perimeter of the functional circuit structure. The semiconductor die is disposed on the package component and electrically coupled to the functional circuit structure of the package component.

According to some alternative embodiments, a manufacturing method of a semiconductor package includes at least the following steps. A package component is formed by at least the following steps. A first via pattern is formed on a first interconnect layer within a functional circuit region and a second via pattern is formed on a second interconnect layer within a seal ring region, where the functional circuit region is encircled by the seal ring region, and the second via pattern includes a plurality of features isolated from one another. An insulating layer is laminated to cover the first via pattern, the first interconnect layer, the second via pattern, and the second interconnect layer, where the first via pattern and the first interconnect layer are isolated from the second via pattern and the second interconnect layer by the insulating layer. A first semiconductor die is coupled to the package component.