Memory device and method of manufacturing the same

A memory device is provided. A first conductive layer, a first diffusion barrier layer, a phase change layer, a second diffusion barrier layer and a second conductive layer are disposed on a first electrode layer in sequence to form a stacking structure. A dielectric layer is disposed on the first electrode layer and covers a sidewall of the stacking structure and part of a top surface of the second conductive layer. A second electrode layer is disposed on the dielectric layer and the second conductive layer. Barrier enhancing components are provided between a bottom surface of the first diffusion barrier layer and a top surface of the second diffusion barrier layer. Further, a method of manufacturing a memory device is provided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a memory device and a method of manufacturing the same.

2. Description of Related Art

With the continuous progressing and evolution of the semiconductor technology, the manufacturing process of memory devices also strides forward. Due to the advantages of small volume, low power consumption, high read/write speed and high capacity density, a phase change memory device is considered as one of the memory devices that are developed with great efforts currently.

Generally, the phase change memory device includes conductive layers which directly contact the phase change material, and metals (such as tungsten) in the conductive layers may be diffused into the phase change material. At this time, the reliability of the phase change memory device might be seriously affected. Therefore, how to improve the reliability of the phase change memory device, caused by the unexpected metal diffusion into the phase change material, is an important issue that needs to be overcome.

SUMMARY OF THE INVENTION

The invention provides a memory device, wherein diffusion barrier layers with barrier enhancing components are disposed between the conductive layers and the phase change layer to effectively prevent the unexpected metal diffusion from the conductive layers into the phase change material, thereby enhancing the reliability of the memory device.

The invention provides a memory device that includes the following. A first conductive layer, a first diffusion barrier layer, a phase change layer, a second diffusion barrier layer and a second conductive layer are disposed on a first electrode layer in sequence to form a stacking structure. A dielectric layer is disposed on the first electrode layer and covering a sidewall of the stacking structure and part of a top surface of the second conductive layer. A second electrode layer is disposed on the dielectric layer and the second conductive layer. Barrier enhancing components are provided between a bottom surface of the first diffusion barrier layer and a top surface of the second diffusion barrier layer.

In an embodiment of the invention, the barrier enhancing components are different from constituent elements of the first diffusion barrier layer and the second diffusion barrier layer.

In an embodiment of the invention, the barrier enhancing components include oxygen element, nitrogen element, helium element or hydrogen element.

In an embodiment of the invention, the barrier enhancing components are provided on grain boundaries of the first diffusion barrier layer, grain boundaries of the second diffusion barrier layer, the bottom surface of the first diffusion barrier layer, a top surface of the first diffusion barrier layer, a bottom surface of the second diffusion barrier layer, the top surface of the second diffusion barrier layer or a combination thereof.

In an embodiment of the invention, the barrier enhancing components are contained in a barrier enhancing layer on the bottom surface of the first diffusion barrier layer, a top surface of the first diffusion barrier layer, a bottom surface of the second diffusion barrier layer, the top surface of the second diffusion barrier layer or a combination thereof.

In an embodiment of the invention, the barrier enhancing layer includes oxygen element, nitrogen element, helium element or hydrogen element.

In an embodiment of the invention, the first diffusion barrier layer and the second diffusion barrier layer respectively include Ti, Ta, TiN, TaN or a combination thereof.

In an embodiment of the invention, the memory device further includes an insulation layer disposed on the first diffusion barrier layer. An opening is in the insulation layer, and the phase change layer covers the insulation layer and fills the opening.

The invention further provides a method of manufacturing a memory device that includes the following. A first conductive layer, a first diffusion barrier layer, a phase change layer, a second diffusion barrier layer and a second conductive layer are formed in sequence on a first electrode layer to form a stacking structure. Barrier enhancing components are provided to the stacking structure, so that the barrier enhancing components are provided between a bottom surface of the first diffusion barrier layer and a top surface of the second diffusion barrier layer. A dielectric layer is formed on the first electrode layer. The dielectric layer covers a sidewall of the stacking structure and part of a top surface of the second conductive layer. A second electrode layer is formed on the dielectric layer and the second conductive layer.

In an embodiment of the invention, the barrier enhancing components are different from constituent elements of the first diffusion barrier layer and the second diffusion barrier layer.

In an embodiment of the invention, the barrier enhancing components include oxygen element, nitrogen element, helium element or hydrogen element.

In an embodiment of the invention, the barrier enhancing components are provided on grain boundaries of the first diffusion barrier layer, grain boundaries of the second diffusion barrier layer, the bottom surface of the first diffusion barrier layer, a top surface of the first diffusion barrier layer, a bottom surface of the second diffusion barrier layer, the top surface of the second diffusion barrier layer or a combination thereof.

In an embodiment of the invention, the barrier enhancing components are contained in a barrier enhancing layer on the bottom surface of the first diffusion barrier layer, a top surface of the first diffusion barrier layer, a bottom surface of the second diffusion barrier layer, the top surface of the second diffusion barrier layer or a combination thereof.

In an embodiment of the invention, the first diffusion barrier layer and the second diffusion barrier layer are formed and the barrier enhancing components are provided in an in-situ manner.

In an embodiment of the invention, the first diffusion barrier layer and the second diffusion barrier layer are formed and the barrier enhancing components are provided in an ex-situ manner.

In an embodiment of the invention, the barrier enhancing components are provided by performing a rapid thermal oxidation process, an oxygen plasma process, or a furnace oxidation process.

In an embodiment of the invention, the first diffusion barrier layer and the second diffusion barrier layer respectively include Ti, Ta, TiN, TaN or a combination thereof.

In an embodiment of the invention, the method of manufacturing the memory device further includes forming an insulation layer on the first diffusion barrier layer. An opening is formed in the insulation layer, and the phase change layer covers the insulation layer and fills the opening.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1AtoFIG. 1Jare schematic cross-sectional views illustrating a manufacturing process of a memory device according to an embodiment of the invention.

With reference toFIG. 1A, an electrode layer12is provided. A material of the electrode layer12is metal material, such as tungsten, aluminium, copper or platinum. A method of forming the electrode layer12includes atomic layer deposition (ALD), for example. In an embodiment of the invention, a thickness of the electrode layer12may be 25 angstrom to 10000 angstrom. Then, a conductive material layer22is formed on the electrode layer12. A material of the conductive material layer22is W, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, W, Mo, Ta, TiSi, TaSi, TiW or WON, for example. A method of forming the conductive material layer22includes chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD) or ALD, for example. In an embodiment of the invention, a thickness of the conductive material layer22may be 25 angstrom to 10000 angstrom.

With reference toFIG. 1B, a diffusion barrier material layer24is formed on the conductive material layer22. A material of the diffusion barrier material layer24is Ti, Ta, TiN, TaN or a combination thereof, for example. A method of forming the diffusion barrier material layer24includes CVD, MOCVD, PVD or ALD, for example. In an embodiment of the invention, a thickness of the diffusion barrier material layer24may be 25 angstrom to 2000 angstrom.

With reference toFIG. 1B, barrier enhancing components27are provided to the diffusion barrier material layer24. The barrier enhancing components27are different from constituent elements of the diffusion barrier material layer24. The barrier enhancing components27may include oxygen element, nitrogen element, helium element or hydrogen element. In an embodiment, the barrier enhancing components27are provided into grain boundaries of the diffusion barrier material layer24. In another embodiment, the barrier enhancing components27may be provided on a bottom surface of the diffusion barrier material layer24, on a top surface of the diffusion barrier material layer24or a combination thereof. The barrier enhancing components27in the grain boundaries of the diffusion barrier material layer24inFIG. 1Bare shown for illustrative purpose, but the invention is not limited thereto. In another embodiment, the barrier enhancing components27are provided and react with the diffusion barrier material layer24to form a barrier enhancing layer (not illustrated) on the bottom surface of the diffusion barrier material layer24, on the top surface of the diffusion barrier material layer24or a combination thereof. In other words, the barrier enhancing components27may be contained in the barrier enhancing layer on the bottom surface of the diffusion barrier material layer24, on the top surface of the diffusion barrier material layer24or a combination thereof. The barrier enhancing layer may include oxygen element, nitrogen element, helium element or hydrogen element. A method of providing the barrier enhancing components27may be a rapid thermal oxidation process (RTP), an oxygen plasma process, or a furnace oxidation process. The barrier enhancing components27may be provided using an oxygen-based gas. The oxygen-based gas is an O2gas, an N2O gas, an H2O gas, an O3gas or a mixture of an O2gas and an H2gas, for example. It is worth noting that the diffusion barrier material layer24may be formed and the barrier enhancing components27may be provided in an in-situ manner (performed in the same chamber) or an ex-situ manner. The barrier enhancing components27are able to enhance the barrier ability of the diffusion barrier material layer24.

With reference toFIG. 1C, an insulation material layer30is formed on the diffusion barrier material layer24. A material of the insulation material layer30is silicon oxide, phosphosilicate glass, borophosphosilicate glass or a combination thereof, for example. A method of forming the insulation material layer30includes CVD, for example. In an embodiment of the invention, a thickness of the insulation material layer30is 500 angstrom to 20000 angstrom.

With reference toFIG. 1CandFIG. 1D, an opening31is formed in the insulation material layer30, and a portion of the diffusion barrier material layer24is exposed by the opening31. As a result, a patterned insulation material layer30ais formed. The process of forming the opening31is, for example, forming a patterned mask layer (not illustrated) on the insulation material layer30first. Afterwards, etching the insulation material layer30by using the patterned mask layer as an etching mask, so as to form the opening31. This etching process may be an anisotropic etching process, such as a dry etching process. The dry etching process is a plasma etching process, for example.

With reference toFIG. 1DandFIG. 1E, a phase change material layer25is formed to cover the patterned insulation material layer30a, and fill the opening31. A material of the phase change material layer25is chalcogenide, for example. In addition, the phase change material layer25may be a binary material layer, a ternary material layer, or a multi-element material layer. A material of the binary material layer is, for example, InSb, GaSb, InSe, Sb2Te3, or GeTe. A material of the ternary material layer is, for example, Ge2Sb2Te5, InSbTe, GaSbTe, SnSbTe4, or InSbGe. A material of the multi-element material layer is, for example, AgInSbTe, GeSbTe, SnSbTe, GeSb(SeTe), or Te81Ge15Sb2S2. A method of forming the phase change material layer25is PVD, for example. In an embodiment of the invention, a thickness of the phase change material layer25is 25 angstrom to 10000 angstrom.

With reference toFIG. 1F, a diffusion barrier material layer26is formed on the phase change material layer25. A material of the diffusion barrier material layer26is Ti, Ta, TiN, TaN or a combination thereof, for example. A method of forming the diffusion barrier material layer26includes CVD, MOCVD, PVD or ALD, for example. In an embodiment of the invention, a thickness of the diffusion barrier material layer26may be 25 angstrom to 2000 angstrom.

Similar to the diffusion barrier material layer24, barrier enhancing components27are provided to the diffusion barrier material layer26. Thus, the detailed description of the barrier enhancing components27is omitted here. The barrier enhancing components27are different from constituent elements of the diffusion barrier material layer26. In an embodiment, the barrier enhancing components27are provided into grain boundaries of the diffusion barrier material layer26. In another embodiment, the barrier enhancing components27may be provided on a bottom surface of the diffusion barrier material layer26, on a top surface of the diffusion barrier material layer26or a combination thereof. The barrier enhancing components27in the grain boundaries of the diffusion barrier material layer26inFIG. 1Fare shown for illustrative purpose, but the invention is not limited thereto. In another embodiment, the barrier enhancing components are provided and react with the diffusion barrier material layer26to form a barrier enhancing layer (not illustrated) on the bottom surface of the diffusion barrier material layer26, on the top surface of the diffusion barrier material layer26or a combination thereof. In other words, the barrier enhancing components27may be on the bottom surface of the diffusion barrier material layer26, on the top surface of the diffusion barrier material layer26or a combination thereof. The barrier enhancing layer may include oxygen element, nitrogen element, helium element or hydrogen element. It is worth noting that the diffusion barrier material layer26may be formed and the barrier enhancing components27may be provided in an in-situ manner (performed in the same chamber) or an ex-situ manner. The barrier enhancing components27are able to enhance the barrier ability of the diffusion barrier material layer26.

A conductive material layer28is formed on the diffusion barrier material layer26. A material of the conductive material layer28is W, TiN, TaN, WN, MoN, NbN, TaSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, Ti, W, Mo, Ta, TiSi, TaSi, TiW or WON, for example. A method of forming the conductive material layer28includes chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD) or ALD, for example. In an embodiment of the invention, a thickness of the conductive material layer28may be 25 angstrom to 10000 angstrom.

With reference toFIG. 1FandFIG. 1G, a patterned mask layer (not illustrated) is formed on the conductive material layer28first. Afterwards, the conductive material layers28and22, the diffusion barrier material layers26and24, the phase change material layer25, and the patterned insulation material layer30anot covered by the patterned mask layer are etched, so as to form a stacking structure20. This etching process may be an anisotropic etching process, such as a dry etching process. The dry etching process is a plasma etching process, for example. The stacking structure20comprises conductive layer28aand22a, diffusion barrier layers26aand24a, a phase change layer25a, and an insulation layer30b.

With reference toFIG. 1H, a dielectric material layer32covering the stacking structure20is formed on the electrode layer12. A material of the dielectric material layer32is silicon oxide, phosphosilicate glass, borophosphosilicate glass, or a combination thereof, for example. A method of forming the dielectric material layer32includes CVD, for example.

With reference toFIG. 1HandFIG. 1I, an opening39is formed in the dielectric material layer32, and a portion of the conductive layer28ais exposed by the opening39. As a result, a dielectric layer32ais formed. The process of forming the opening39is, for example, forming a patterned mask layer (not illustrated) on the dielectric material layer32first. Afterwards, etching the dielectric material layer32by using the patterned mask layer as an etching mask, so as to form the opening39. This etching process may be an anisotropic etching process, such as a dry etching process. The dry etching process is a plasma etching process, for example. The dielectric layer32acovers side walls of the stacking structure20and a portion of a top surface of the conductive layer28a.

With reference toFIG. 1J, an electrode layer14is formed to cover the dielectric layer32a, and fill the opening39. The electrode layer14is fabricated by metal material, such as tungsten, aluminium, copper or platinum. A method of forming the electrode layer14includes atomic layer deposition (ALD), for example. In an embodiment of the invention, a thickness of the electrode layer14is 25 angstrom to 10000 angstrom.

Further, with reference toFIG. 1J, the structure of the memory device according to an embodiment of the invention includes the electrode layers12and14, the stacking structure20, and the dielectric layer32a. The stacking structure20is disposed on the electrode layer12. More particularly, the stacking structure20comprises the conductive layer22aand28a, the diffusion barrier layers24aand26a, the phase change layer25a, the insulation layer30b, and barrier enhancing components27provided between a bottom surface of the diffusion barrier layer24aand a top surface of the diffusion barrier layer26a. In an embodiment, the barrier enhancing components27are provided on grain boundaries of the diffusion barrier layer24aand grain boundaries of the diffusion barrier layer26a. In another embodiment, the barrier enhancing components27are provided on a bottom surface of the diffusion barrier layer24a, a top surface of the diffusion barrier layer24a, a bottom surface of the diffusion barrier layer26a, a top surface of the diffusion barrier layer26aor a combination thereof. In another embodiment, the barrier enhancing components27may be contained in the barrier enhancing layer (not illustrated) on the bottom surface of the diffusion barrier layer24a, a top surface of the diffusion barrier layer24a, a bottom surface of the diffusion barrier layer26a, the top surface of the diffusion barrier layer26aor a combination thereof. Besides, the barrier enhancing components27are different from constituent elements of the diffusion barrier layers26aand24a. The barrier enhancing components27include oxygen element, nitrogen element, helium element or hydrogen element, for example. The dielectric layer32ais disposed on the electrode layer12. In addition, the dielectric layers32acovers side walls of the stacking structure20and a portion of the top surface of the conductive layer28a. The electrode layer14covers the dielectric layer32a, and a portion of the top surface of the conductive layer28a. In other words, the stacking structure20and the dielectric layer32aare located between the electrode layers12and14.

To conclude the above, the manufacturing method of the memory device provided by the invention includes providing barrier enhancing components to the diffusion barrier layers between the conductive layers and the phase change layer to improve the barrier ability, so as to effectively prevent the unexpected metal diffusion from the conductive layers into the phase change layer, thereby improving the reliability of the memory device.