Multi-semiconductor layer photodetector and related method

A structure includes a photodetector including alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other in a stack. Each semiconductor layer includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers. The extensions provide an area for operative coupling to a contact. The extensions can be arranged in a cascading, staircase arrangement, or may extend from n-type semiconductor layers on one side of the stack and from p-type semiconductor layers on another side of the stack. The photodetector can be on a substrate in a first region, and a complementary metal-oxide semiconductor (CMOS) device may be on the substrate on a second region separated from the first region by a trench isolation. The photodetector is capable of detecting and converting near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.

BACKGROUND

The present disclosure relates to photodetectors, and more specifically, to a photodetector with multiple semiconductor layers capable of near-infrared detection.

Photonics integrated circuits include photodetectors to convert optical signals to electrical signals. Certain long wavelengths of light, such as near-infrared light, are difficult to detect in an efficient manner without complex PN junction structures. The PN structures may require complicated implanting processes to form, for example, deep PN junctions or double PN junctions.

SUMMARY

An aspect of the disclosure is directed to a structure, comprising: a substrate including a first region including a photodetector including: a stack including alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other, wherein a plurality of the semiconductor layers includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers; and a contact operatively coupled to each extension.

Another aspect of the disclosure includes a structure, comprising: a substrate including a first region adjacent a second region; a photodetector in the first region, the photodetector including: a stack of alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other, wherein a plurality of the semiconductor layers includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers, and a contact operatively coupled to each extension; a complementary metal-oxide semiconductor (CMOS) device in the second region; and a trench isolation separating the first region and the second region.

An aspect of the disclosure related to a method, comprising: forming alternating p-type semiconductor layers and n-type semiconductor layers in a stack over a first region of a substrate with each semiconductor layer including an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers, each extension having the same doping type as the semiconductor layer adjacent thereto; and forming a contact operatively coupled to each extension.

The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.

DETAILED DESCRIPTION

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

Embodiments of the disclosure provide a structure including a photodetector (e.g., a photodiode) including a stack including alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other. Each semiconductor layer includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers. The extensions provide an area for operative coupling to a contact. The extensions can be arranged in a cascading, staircase arrangement, or may extend from n-type semiconductor layers on one side of the stack and from p-type semiconductor layers on another side of the stack. The photodetector can be on a substrate in a first region, and a complementary metal-oxide semiconductor (CMOS) device may be on the substrate in a second region separated from the first region by a trench isolation. The photodetector is simpler than conventional photodetectors to form, and is capable of detecting and converting near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.

FIG.1shows a cross-sectional view andFIG.2shows a top-down view of a structure100, according to embodiments of the disclosure. Structure100may include a substrate102including a first region104and a second region106. One of the regions,104as shown, includes a photodetector110. The other region,106as shown, may include a complementary metal-oxide semiconductor (CMOS) device(s)112. Substrate102, and any other semiconductor material described herein, may include any now known or later developed semiconductor material appropriate for photonics integrated circuits (PICs), e.g., silicon, silicon germanium, among others. Regions104,106may be electrically isolated by a trench isolation (TI)108, which may extend to at least the depth of photodetector110. CMOS device(s)112may include any now known or later developed active devices, e.g., transistors. CMOS device(s)112may be electrically isolated by trench isolation(s) (TI(s))114. TI108and TI(s)114may be formed by creating a trench to a desired depth and width and may include any appropriate dielectric for trench isolations such as but not limited to silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, and/or an amorphous poly/oxide combination, filling the trench.

Photodetector110may include a stack124of alternating p-type semiconductor layers120and n-type semiconductor layers122in contact with each other. Any number of each layer120,122can be provided so long as stack124includes at least three semiconductor layers, e.g., one p-type semiconductor layer120and two n-type semiconductor layers122, or two p-type semiconductor layers120and one n-type semiconductor layer122. In the non-limiting examples shown in the drawings, typically five layers are shown with three p-type semiconductor layers120and two n-type semiconductor layers122. P-type semiconductor layers120(hereinafter, where appropriate, “p-type layers120”) and n-type semiconductor layers122(hereinafter, where appropriate, “n-type layers122”) are in direct contact with one another. That is, there is no intervening material between the layers.

A plurality of semiconductor layers120,122of stack124may include an extension130,132extending beyond an end134,135of an adjacent semiconductor layer122,120of alternating p-type layers120and n-type layers122, respectively. That is, extensions130of p-type layers120extend beyond ends134of adjacent n-type layers122thereover; and extensions132of n-type layers122extend beyond ends135of adjacent p-type layers120thereover. InFIG.1, each semiconductor layer120,122in stack124, except an uppermost layer136, includes an extension130,132. More particularly, p-type layers120include extensions130, and n-type layers122include extensions132. InFIGS.1,2and4, extensions130,132are in a cascading, staircase arrangement on a selected side (right side, as shown) of stack124. In this manner, each layer120,122with its respective extension130,132may be longer than an adjacent layer thereover. While the opposing side of layers120,122is shown in a vertically aligned manner, this is not necessary in all cases.

A dielectric138(not shown inFIG.2) fills the space over extensions130,132. Dielectric138may include any now known or later developed interlayer dielectric material such as but not limited to silicon oxide. In this embodiment, each p-type layer120and each n-type layer122and respective extensions130,132thereof includes monocrystalline semiconductor (e.g., silicon), doped with an appropriate dopant. In non-limiting examples, n-type dopants may include but are not limited to: phosphorous (P), arsenic (As), antimony (Sb); and p-type dopants may include but are not limited to: boron (B), indium (In) and gallium (Ga). As will be described further herein, each n-type layer122may include an n-type doped epitaxial semiconductor layer, and each p-type layer120may include a p-type doped epitaxial semiconductor layer.

Extensions130,132provide landing locations for contacts140. Hence, photodetector110of structure100also includes a contact140operatively coupled to each extension130,132. As illustrated, contact(s)140are operatively coupled to each extension130,132. That is, contact140lands at least partially on an upper surface of a respective stair (extension130,132) of the cascading, staircase arrangement. Contact(s)140can take any now known or later developed form, e.g., conductor within a refractory metal liner within dielectrics138and142(dashed box). Contact(s)140and/or conductive wires (not shown) coupled thereto may be routed in any manner to direct the electrical signal generated by photodetector110as required. Contact(s)140can be routed individually or combined at some location within structure100.

FIG.3shows a schematic cross-sectional view a structure200, according to other embodiments of the disclosure. Structure200may include substrate102including first region104and second region106. One of the regions, first region104as shown, includes a photodetector210. The other region, second region106as shown, may include CMOS device(s)112, as previously described. Substrate102, TI108, CMOS device(s)112and TI(s)114may be arranged as described relative toFIGS.1-2.

Photodetector210may include a stack224including alternating p-type semiconductor layers220and n-type semiconductor layers222in contact with each other. Any number of each layer220,222can be provided, so long as stack224includes at least three semiconductor layers, e.g., one p-type semiconductor layer220and two n-type semiconductor layers222, or two p-type semiconductor layers220and one n-type semiconductor layer222. As noted, typically five layers are shown with three p-type semiconductor layers220and two n-type semiconductor layers222. P-type semiconductor layers220(hereinafter, where appropriate, “p-type layers220”) and n-type semiconductor layers222(hereinafter, where appropriate, “n-type layers222”) are in direct contact with one another. That is, there is no intervening material between the layers.

As shown inFIG.3, in this embodiment, extensions230of p-type layers220extend beyond ends234of n-type layers222on a first side280(e.g., left side as shown) of stack224, and extensions232of n-type layers222extend beyond ends235of p-type layers220on a second side284(e.g., right side as shown) of stack224. That is, each extension230of a p-type layer220extends beyond end234of an adjacent n-type layer222on first side280of stack224. Similarly, each extension232of an n-type layer222extends beyond end235of an adjacent p-type layer220on second side284of stack224. The first and second sides280,284of stack224are shown as opposing sides for illustration purposes, but the sides can be any two different sides of stack224. A lowermost layer236(shown as p-type layer222) may include a non-discernible extension230M, which is monocrystalline semiconductor of the same doping type as the semiconductor layer, i.e., it can just be the layer.

A dielectric250is positioned between p-type extensions230and a dielectric252is positioned between n-type extensions232. Dielectrics250,252may include but are not limited to silicon oxide, or other ILD material. Dielectrics250,252need not be the same material. While shown between extensions230,232, dielectrics250,252may also extend over and/or about sides of extensions230,232, e.g., where the latter are arranged as discrete fingers extending from layers220,222. As will be described further herein, each n-type layer222may include an n-type doped epitaxial semiconductor layer, and each p-type layer220may include a p-type doped epitaxial semiconductor layer. Layers220,222are monocrystalline semiconductor, e.g., silicon, doped with the appropriate dopant. In contrast toFIGS.1-2, extensions230,232of p-type layers220and n-type layers222, respectively, include polycrystalline semiconductor (e.g., polysilicon), doped with an appropriate dopant. The dopants may be selected from the groups previously described herein.

As shown inFIG.3, as with theFIGS.1-2embodiments, substrate102may include second region106adjacent first region104, and second region106is isolated from first region104by TI108. Second region106may include CMOS device(s)112therein, as previously described.

FIG.4shows a cross-sectional view of a structure300that is identical to structure100inFIG.1, except alternating p-type and n-type layers166,168are also present in CMOS region106. The underlying layers166,168are under CMOS devices112, which are built in/on an undoped semiconductor layer158over the alternating layers166,168, as will be described further herein.

In operation, as shown inFIGS.1,3and4, light148may enter photodetector110,210and be converted to an electrical signal transmitted through contacts140,240,242. Light can be delivered to photodetectors110,210using any now known or later developed optical waveguide. Stack124allows light to penetrate deeper into photodetectors110,210allowing longer wavelength light to penetrate deeper semiconductor layers120,122,220,222, and providing improved detection and flexibility. Photodetector110,210can detect and converting near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.

FIGS.5-16show cross-sectional views of a method according to embodiments of the disclosure.FIGS.5-16show embodiments of forming alternating p-type layers120and n-type layers122in stack124over first region104of substrate102. Each semiconductor layer120,122includes an extension130,132extending beyond end134,135of an adjacent semiconductor layer122,120of the alternating p-type layers120and n-type layers122. Each extension130,132has the same doping type as the semiconductor layer120,122adjacent thereto. The method may include forming extensions130,132in a cascading, staircase arrangement on a selected side (e.g., right side) of stack124, and forming contact140to each extension130,132, e.g., by landing a contact at least partially on an upper surface of each respective stair (i.e., extension130,132) of the cascading, staircase arrangement.

There are several ways to form alternating p-type and n-type layers120,122over substrate102. For theFIG.1embodiment, as shown inFIGS.5-8, forming stack124of alternating p-type and n-type layers120,122may include, sequentially, for each respective semiconductor layer: epitaxially forming a semiconductor layer150over substrate102; forming a mask152over (CMOS) region106of semiconductor layer150, leaving the other (photodetector) region104of semiconductor layer exposed150; doping the exposed region104; removing mask152; and repeating the process for as many layers as desired. The process includes alternatingly doping region104of semiconductor layer150with one of a p-type dopants to form p-type layer120(FIG.5) and an n-type dopant to form n-type layer122(FIG.6). Mask152may include any now known or later developed mask material, e.g., a photoresist or a silicon nitride hard mask. Doping may include any appropriate doping process such as ion implanting, among others. After doping, mask152may be removed using any appropriate process, e.g., a wet etch for a nitride mask or an ashing process for a resist-based mask. After mask152removal, the process repeats for any desired next layer120,122. As shown inFIGS.7-8, the layer formation process can repeat for as many layers as desired in photodetector110(FIG.1). Once the stack is complete, as shown by a dashed box inFIG.8for clarity, TI108(and perhaps TI(s)114(not shown)) can be formed in any now known or later developed manner, and may include any appropriate dielectric, e.g., silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), and/or porous SiCOH.

For theFIG.4embodiment, as shown inFIGS.9-10, forming stack124of alternating p-type and n-type layers120,122may include epitaxially forming a plurality of semiconductor layers120,122on substrate102while in-situ doping alternating semiconductor layers of the plurality of semiconductor layers with a p-type dopant to form a p-type layer120and an n-type dopant to form an n-type layer122. As shown inFIGS.9-10, the layer formation process can repeat for as many layers as desired in photodetector110(FIG.1) (second p-type layer122and second n-type layer122formation shown in dashed lines inFIG.9). Once stack124is complete, as shown inFIG.10, a hard mask157may be formed over stack124in region104, and another (undoped) semiconductor layer158may be epitaxially formed over region106(for CMOS devices112(FIG.4)) adjacent mask157over region104of substrate102. At this stage, as shown by a dashed box inFIG.10for clarity, TI108(and perhaps TI(s)114(not shown)) can be formed in any now known or later developed manner, and may include any appropriate dielectric, e.g., silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), and/or porous SiCOH. Mask157may then be removed using any appropriate removal process for the masking material employed, e.g., a wet etch for a hard mask material such as a nitride.

At this stage, as shown inFIG.11for theFIG.8embodiment and inFIG.12for theFIG.10embodiment, the method may optionally include forming CMOS device(s)112in region106of substrate102adjacent (photodetector) region104. CMOS device(s)112can be formed using any now known or later developed semiconductor fabrication techniques. As shown inFIG.11, if not already completed, TI108(and TI(s)114) may also be formed in substrate102to isolate regions104from region106, e.g., prior to device112formation. TI108and TI(s)114can be formed in any now known or later developed manner, and may include any appropriate dielectric, e.g., silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated silicon oxycarbide (SiCOH), and/or porous SiCOH. InFIG.12, TI108separates semiconductor layers120,122between regions104,106, creating p-type layers166and n-type layers168in CMOS region106.

There are several ways to form extensions130,132in the cascading, staircase arrangement ofFIGS.1,2and4.FIGS.13-16show cross-sectional views of one illustrative process of forming extensions130,132in the cascading, staircase arrangement. The process may include forming a mask160(FIGS.11and12) covering stack124of alternating p-type layers120and n-type layers122over substrate102. Mask160may include any appropriate masking material, e.g., a resist. Mask160may also cover (CMOS) region106to protect any structure therein, e.g., CMOS devices112if already formed. As shown inFIGS.13-16, the process may include, sequentially, from an uppermost semiconductor layer162(p-type layer120as shown) in stack124of alternating p-type and n-type layers120,122toward a lowermost semiconductor layer164(p-type layer120as shown) thereof and excepting lowermost semiconductor layer164thereof: Trimming mask160covering stack124to expose an upper surface of an end portion170(dashed boxes) of a respective semiconductor layer120,122and an end portion172of any semiconductor layer122,120thereabove on the selected side of stack124, and etching to remove end portion170(dashed box) of the respective semiconductor layer and end portion172of any semiconductor layer thereabove. The process can repeat as many times as there are layers. The sequential and progressive etching result in the cascading and staircase arrangement (seeFIGS.1,2, and4). The etching can include any chemistry appropriate for the materials to be removed, e.g., a reactive ion etch, among other possibilities. Once complete, a remaining portion174(FIG.16) of mask160can be removed using any appropriate removal process, e.g., an ashing process for a resist-based mask.

FIG.1shows structure100as completed from theFIG.11embodiment, andFIG.4shows structure300as completed from theFIG.12embodiment, i.e., in the latter case, with layers166,168in CMOS region106. As shown inFIGS.1and4, dielectric138may be formed over the cascading, staircase arrangement on the selected side of stack124in any known fashion. If not already formed, at this stage, the method may optionally include forming CMOS device(s)112in region106of substrate102adjacent (photodetector) region104. For example, TI108and TI(s)114may be formed, as previously described. CMOS device(s)112can be formed using any now known or later developed semiconductor fabrication techniques. In any event, dielectric142may be deposited, and contacts140,144may be formed in any known fashion to photodetector110and CMOS device(s)112, respectively. A contact140is operatively coupled to each extension130,132, as described herein.

FIGS.17-19show cross-sectional views of forming structure200inFIG.3, according to other embodiments of the disclosure. In this case, forming alternating p-type layers220and n-type layers222over substrate102may include starting with forming either p-type layer220(shown inFIG.17) or n-type layer222, then sequentially repeating the steps until as many of each layer220,222as desired is formed. As shown inFIG.17, forming p-type semiconductor layer220may include: epitaxially forming a p-type semiconductor where the epitaxially forming creates a p-type semiconductor layer220over any semiconductor material thereunder (substrate102inFIG.17). The step may also form a p-type polycrystalline extension230M adjacent p-type layer220at a first end280of stack124(FIG.4) (or the semiconductor layers (just222at this stage)) and over any dielectric thereunder (none present inFIG.17, seeFIG.19). Note, for a lowermost layer236, as shown inFIG.17, extension230M of lowermost layer236is not discernible from the rest of semiconductor layer (p-type layer222in this example), regardless of the doping type of the layer. Similarly, what will eventually be first end280of semiconductor layers220,222above lowermost layer236is not discernible.

Doping may occur in any now known or later developed fashion, e.g., in-situ doping, ion implanting, among others.FIG.17also shows forming dielectric252adjacent to p-type semiconductor layer222at what will be second end284of semiconductor layers (only lowermost layer236shown) opposite what will be first end280of stack124and the semiconductor layers. Dielectric252may be formed in a similar manner to TI108and TI(s)114and may include the same materials, e.g., an oxide, or other ILD materials.

FIG.18shows forming an n-type layer222. Forming n-type layer222may include: epitaxially forming an n-type semiconductor, where the epitaxially forming creates n-type semiconductor layer222over any semiconductor material, e.g., p-type layer220, thereunder and an n-type polycrystalline extension232adjacent n-type semiconductor layer222at second end284of semiconductor layers220,222and over any dielectric (e.g., dielectric252) thereunder. Doping may occur in any now known or later developed fashion, e.g., in-situ doping, ion implanting, among others.FIG.18also shows forming dielectric250adjacent to n-type semiconductor layer222at what will be first end280of semiconductor layers220,222opposite what will be second end284of semiconductor layers220,222, and over extension230M. Dielectric250may be formed in a similar manner to TI108and TI(s)114and may include the same materials, e.g., an oxide, or other ILD material. Formation of dielectric250may remove part of n-type layer222formed over extension230M of p-type layer220.

FIG.19shows forming additional p-type and n-type layers220,222. In the example shown, two more p-type layers220and one more n-type layer222is formed, matching structure200ofFIG.3. Forming another p-type layer220may include: epitaxially forming a p-type semiconductor, where the epitaxially forming creates p-type semiconductor layer222over any semiconductor material, e.g., n-type layer222, thereunder and a p-type polycrystalline extension230adjacent p-type semiconductor layer220at first end280of semiconductor layers220,222and over any dielectric (e.g., dielectric250) thereunder. Again, doping may occur in any now known or later developed fashion, e.g., in-situ doping, ion implanting, among others.FIG.19also shows forming dielectric252adjacent to p-type layer220at second end284of semiconductor layers220,222opposite first end280of semiconductor layers220,222, and over extension232of n-type layer222thereunder. Dielectric252may be formed in a similar manner to TI108and TI(s)114and may include the same materials, e.g., an oxide, or other ILD material. Formation of dielectric252may remove part of p-type layer220and is formed over extension232of n-type layer222.

Referring again toFIG.3, the drawing shows forming CMOS device(s)112in region106of substrate102adjacent (photodetector) region104. For example, TI108and TI(s)114may be formed, as previously described. InFIG.3, TI108separates semiconductor layers120,122between regions104,106, creating p-type layers166and n-type layers168in CMOS region106. CMOS device(s)112can be formed using any now known or later developed semiconductor fabrication techniques. Similarly to the process shown inFIG.10for theFIG.4embodiment, once stack124is complete, a hard mask (not shown inFIG.3, seeFIG.10) may be formed over stack224in region104, and another (undoped) semiconductor layer258may be epitaxially formed over region106adjacent the mask over region104of substrate102. The mask may then be removed using any appropriate removal process for the masking material used. CMOS devices112are built in/on undoped semiconductor layer258over the alternating layers166,168. Dielectric142may be deposited over both regions104,106for interconnect layers.

FIG.3also shows forming contact240operatively coupled to extensions230,230M of p-type layers222. Contact240may also extend through dielectric142. Here, contact240is formed to extend through p-type polycrystalline extensions230of p-type layers220and dielectric250therebetween (and/or thereover). Similarly, forming contact242operatively coupled to extensions232of n-type layers220includes forming contact242to extend through n-type polycrystalline extensions232of n-type layers222and dielectrics252therebetween (and/or thereover). Contact242may also extend through dielectric142. Contacts240,242can be formed using any now known or later developed technique, so long as they extend through extensions230,232, respectively. In this embodiment, a single contact240,242may be operatively coupled to extensions230,232, respectively. Contacts244may also be formed in any known fashion to CMOS device(s)112.

Embodiments of the disclosure provide various technical and commercial advantages, examples of which are discussed herein. Photodetectors110,210are simpler to form than conventional photodetectors and the processes can be integrated into CMOS device formation. Photodetectors110,210can detect and convert near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.