Program code loading and accessing method, memory controller, and memory storage apparatus

A method of loading a program code from a rewritable non-volatile memory module is provided, wherein the program code includes data segments and two program code copies corresponding to the program code are stored in the rewritable non-volatile memory module. The method includes loading a first data segment of a first program code copy and determining whether the first data segment contains any uncorrectable error bit. The method still includes, when the first data segment does not contain any uncorrectable error bit, loading a second data segment of the first program code copy. The method further includes, when the first data segment contains an uncorrectable error bit, loading a first data segment of a second program code copy, and then loading a second data segment of the first program code copy or the second program code copy. Thereby, the program code can be successfully loaded.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 100117417, filed May 18, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

1. Technology Field

The present invention generally relates to a program code loading and accessing method, and more particularly, to a method of loading and accessing a program code in a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same.

2. Description of Related Art

Along with the widespread of digital cameras, cell phones, and MP3 in recently years, the consumers' demand to storage media has increased drastically. Rewritable non-volatile memory is one of the most adaptable storage media to portable electronic products (for example, cell phones, personal digital assistants (PDAs), and notebook computers) due to its many characteristics such as data non-volatility, low power consumption, small volume, non-mechanical structure, and fast access speed. Thus, in recent years, the flash memory industry has become a major part of the electronic industry.

Conventionally, the firmware code (program code) of a flash memory controller in a flash memory storage apparatus is stored in a programmable read-only memory (PROM, therefore is not updatable) inside the flash memory controller and is loaded into a static random access memory (SRAM) inside the flash memory controller to be executed when the flash memory controller is in operation. However, along with the increases in the size, complexity, and revision rate of firmware codes, firmware codes should be updatable and correctable. In order to reduce the sizes of storage apparatuses and conveniently update and correct firmware codes, some techniques have been developed for directly storing a firmware code into a NAND flash memory module of a memory storage apparatus and loading the firmware code into a SRAM of a memory controller when the flash memory storage apparatus is started. Since no additional PROM is disposed, the size and fabrication cost of the memory storage apparatus can be effectively reduced.

However, more bit errors may be detected in data stored in flash memory along with the increase in circuit integrity and the reduction in device size. In order to avoid such situation that a firmware code cannot be successfully loaded and accordingly the system cannot be started caused by too many bit errors, two (or more) program code copies of the firmware code are usually stored in a flash memory of the flash memory storage apparatus. If the entire first program code copy cannot be successfully read, the memory controller tries to load the entire second program code copy. However, if the entire second program code copy is still not successfully loaded, the flash memory storage apparatus cannot be started. Thereby, a more reliable firmware code loading method is desired.

SUMMARY

Accordingly, the present invention is directed to a program code loading method, a program code accessing method, a memory controller, and a memory storage apparatus, wherein a program code can be effectively accessed in a rewritable non-volatile memory module.

According to an exemplary embodiment of the present invention, a program code loading method for loading a program code having a plurality of data segments from a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has at least one first physical block and at least one second physical block. The first physical block stores a first program code copy corresponding to the program code, the second physical block stores a second program code copy corresponding to the program code, and the first program code copy and the second program code copy respectively have a plurality of data segments identical to the data segments of the program code. The program code loading method includes sequentially loading a first data segment of the first program code copy and determining whether the first data segment of the first program code copy contains at least one uncorrectable error bit. The program code loading method further includes, when the first data segment of the first program code copy contains at least one uncorrectable error bit, alternatively loading a part of the first program code copy and a part of the second program code copy.

According to an exemplary embodiment of the present invention, a program code accessing method for accessing a program code in a rewritable non-volatile memory module is provided, wherein the rewritable non-volatile memory module has a plurality of physical blocks and the program code comprises a plurality of data segments. The program code accessing method includes storing a first program code copy corresponding to the program code by using at least one first physical block among the physical blocks, wherein the first program code copy has a plurality of data segments identical to the data segments of the program code. The program code accessing method also includes storing a second program code copy corresponding to the program code by using at least one second physical block among the physical blocks, wherein the second program code copy has a plurality of data segments identical to the data segments of the program code. The program code accessing method still includes sequentially loading a first data segment among the data segments of the first program code copy and determining whether the first data segment of the first program code copy contains at least one uncorrectable error bit. The program code accessing method further includes, when the first data segment of the first program code copy contains at least one uncorrectable error bit, alternatively loading a part of the first program code copy and a part of the second program code copy.

According to an exemplary embodiment of the invention, a memory controller for managing a rewritable non-volatile memory module is provided. The memory controller includes a host interface, a memory interface, and a memory management circuit. The host interface is configured to couple to a host system. The memory interface is configured to couple to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit uses at least one first physical block among the physical blocks to store a first program code copy corresponding to a program code, wherein the program code has a plurality of data segments, and the first program code copy has a plurality of data segments identical to the data segments of the program code. The memory management circuit also uses at least one second physical block among the physical blocks to store a second program code copy corresponding to the program code, wherein the second program code copy has a plurality of data segments identical to the data segments of the program code. The memory management circuit sequentially loads a first data segment among the data segments of the first program code copy and determines whether the first data segment of the first program code copy contains at least one uncorrectable error bit. When the first data segment of the first program code copy contains at least one uncorrectable error bit, the memory management circuit alternatively loads a part of the first program code copy and a part of the second program code copy.

According to an exemplary embodiment of the invention, a memory storage apparatus including a connector, a rewritable non-volatile memory module, and a memory controller is provided. The connector is configured to couple to a host system. The rewritable non-volatile memory module has a plurality of physical blocks. The memory controller is coupled to the connector and the rewritable non-volatile memory module. The memory controller uses at least one first physical block among the physical blocks to store a first program code copy corresponding to a program code, wherein the program code has a plurality of data segments, and the first program code copy has a plurality of data segments identical to the data segments of the program code. The memory controller also uses at least one second physical block among the physical blocks to store a second program code copy corresponding to the program code, wherein the second program code copy has a plurality of data segments identical to the data segments of the program code. The memory controller sequentially loads a first data segment among the data segments of the first program code copy and determines whether the first data segment of the first program code copy contains at least one uncorrectable error bit. When the first data segment of the first program code copy contains at least one uncorrectable error bit, the memory controller alternatively loads a part of the first program code copy and a part of the second program code copy.

As described above, the program code loading method, the program code accessing method, the memory controller, and the memory storage apparatus according to the present invention can effectively avoid a situation that a program code cannot be successfully loaded and accordingly a system cannot be started caused by too many bit errors.

These and other exemplary embodiments, features, aspects, and advantages of the invention will be described and become more apparent from the detailed description of exemplary embodiments when read in conjunction with accompanying drawings.

DESCRIPTION OF THE EMBODIMENTS

First Exemplary Embodiment

Generally speaking, a memory storage apparatus (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage apparatus is usually used along with a host system so that the host system can write data into or read data from the memory storage apparatus.

FIG. 1Aillustrates a host system and a memory storage apparatus according to the first exemplary embodiment of the invention.

Referring toFIG. 1A, the host system1000includes a computer1100and an input/output (I/O) device1106. The computer1100includes a microprocessor1102, a random access memory (RAM)1104, a system bus1108, and a data transmission interface1110. The I/O device1106includes a mouse1202, a keyboard1204, a display1206, and a printer1208, as shown inFIG. 1B. It should be understood that the I/O device1106is not limited to the devices illustrated inFIG. 1Band may further include other devices.

In the present embodiment, a memory storage apparatus100is coupled to other components of the host system1000through the data transmission interface1110. The host system1000can write data into or read data from the memory storage apparatus100through the operations of the microprocessor1102, the RAM1104, and the I/O device1106. The memory storage apparatus100is a rewritable non-volatile memory storage apparatus, such as flash drive1212, a memory card1214, or a solid state drive (SSD)1216, as shown inFIG. 1B.

Generally speaking, the host system1000can be substantially any system that can work with the memory storage apparatus100to store data. Even though the host system1000is described as a computer system in the present exemplary embodiment, in another exemplary embodiment of the invention, the host system1000may be a digital camera, a video camera, a communication device, an audio player, or a video player. For example, if the host system is a digital camera (video camera)1310, the rewritable non-volatile memory storage apparatus is a secure digital (SD) card1312, a multi media card (MMC)1314, a memory stick (MS)1316, a compact flash (CF) card1318, or an embedded storage device1320(as shown inFIG. 1C) used by the digital camera (video camera)1310. The embedded storage device1320includes an embedded MMC (eMMC). It should be mentioned that the eMMC is directly coupled to the motherboard of the host system.

FIG. 2is a schematic block diagram of the memory storage apparatus inFIG. 1A.

Referring toFIG. 2, the memory storage apparatus100includes a connector102, a memory controller104, and a rewritable non-volatile memory module106.

In the present exemplary embodiment, the connector102is compatible to the serial advanced technology attachment (SATA) standard. However, the invention is not limited thereto, and the connector102may also be compatible to the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the peripheral component interconnect (PCI) express standard, the universal serial bus (USB) standard, the SD interface standard, the MS interface standard, the MMC interface standard, the CF interface standard, the integrated device electronics (IDE) standard, or any other suitable standard.

The memory controller104executes a plurality of logic gates or control instructions implemented in a hardware form or a firmware form and performs various data operations on the rewritable non-volatile memory module106according to commands issued by the host system1000. In particular, the memory controller104loads a program code from the rewritable non-volatile memory module106according to the program code accessing method provided by the present exemplary embodiment.

The rewritable non-volatile memory module106is coupled to the memory controller104and configured to store data written by the host system1000. The rewritable non-volatile memory module106includes physical blocks304(0)-304(R). Each physical block has a plurality of physical pages, wherein the physical pages belonging to the same physical block can be individually written but have to be erased all together. To be specific, physical block is the smallest erasing unit. Namely, each physical block contains the least number of memory cells that are erased all together. One physical page is the smallest programming unit. Namely, one physical page is the smallest unit for writing data. In the present exemplary embodiment, the rewritable non-volatile memory module106is a multi level cell (MLC) NAND flash memory module. However, the present invention is not limited thereto, and the rewritable non-volatile memory module106may also be a single level cell (SLC) NAND flash memory module, any other flash memory module, or any memory module having the same characteristics.

FIG. 3is a schematic block diagram of a memory controller according to the first exemplary embodiment of the invention.

Referring toFIG. 3, the memory controller104includes a memory management circuit202, a host interface204, and a memory interface206.

The memory management circuit202controls the overall operation of the memory controller104. To be specific, the memory management circuit202has a plurality of control instructions, and when the memory storage apparatus100is in operation, the control instructions are executed to carry out various data operations.

To be specific, the control instructions of the memory management circuit202are stored in a specific area of the rewritable non-volatile memory module106(for example, a system area in the rewritable non-volatile memory module106exclusively used for storing system data) as program codes. In addition, the memory management circuit202has a microprocessor unit (not shown), a read-only memory (ROM, not shown), and a RAM (not shown). In particular, the ROM has a driving code segment. When the memory controller104is enabled, the microprocessor unit first executes the driving code segment to load the control instructions (i.e., a firmware code) from the rewritable non-volatile memory module106into the RAM of the memory management circuit202. Thereafter, the microprocessor unit runs the control instructions to perform various data operations. In particular, the memory management circuit202loads a program code (also referred to as a firmware code) for controlling the overall operation of the memory controller104from the rewritable non-volatile memory module106according to the program code accessing method provided by the present exemplary embodiment.

The host interface204is coupled to the memory management circuit202and configured to receive and identify commands and data from the host system1000. Namely, commands and data issued by the host system1000are transmitted to the memory management circuit202through the host interface204. In the present exemplary embodiment, the host interface204is compatible to the SATA standard. However, the present invention is not limited thereto, and the host interface204may also be compatible to the PATA standard, the IEEE 1394 standard, the PCI express standard, the USB standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard, or any other suitable data transmission standard.

The memory interface206is coupled to the memory management circuit202and configured to access the rewritable non-volatile memory module106. Namely, data to be written into the rewritable non-volatile memory module106is converted by the memory interface206into a format acceptable to the rewritable non-volatile memory module106.

In addition, in the present exemplary embodiment, the memory controller104may further includes a buffer memory252, a power management circuit254and an error checking and correcting (ECC) circuit256.

The buffer memory252is coupled to the memory management circuit202and configured to temporarily store data and commands from the host system1000or data from the rewritable non-volatile memory module106. In particular, the memory management circuit202loads a program code from the rewritable non-volatile memory module106into the buffer memory252according to the program code accessing method provided by the present exemplary embodiment.

The power management circuit254is coupled to the memory management circuit202and configured to control the power supply of the memory storage apparatus100.

The ECC circuit256is coupled to the memory management circuit202and configured to check and correct error bits, so as to ensure data accuracy. To be specific, when the memory management circuit202receives a write command from the host system1000, the ECC circuit256generates a corresponding ECC code for the data corresponding to the write command, and the memory management circuit202stores the data corresponding to the write command and the corresponding ECC code into the rewritable non-volatile memory module106. Subsequently, when the memory management circuit202reads the data from the rewritable non-volatile memory module106, it also reads the ECC code corresponding to the data, and the ECC circuit256checks and corrects error bits in the data according to the ECC code.

FIG. 4is a schematic block diagram of a rewritable non-volatile memory module according to the first exemplary embodiment of the invention.

Referring toFIG. 4, the rewritable non-volatile memory module106includes physical blocks304(0)-304(R). In the present exemplary embodiment, the physical blocks304(0)-304(R) may belong to the same memory die or different memory dies. Each physical block has a plurality of physical pages, wherein the physical pages belonging to the same physical block can be individually written but have to be erased all together. To be specific, physical block is the smallest erasing unit. Namely, each physical block contains the least number of memory cells that are erased all together. Each of the physical pages is the smallest programming unit. Namely, each of the physical pages is the smallest unit for writing data.

In the present exemplary embodiment, the memory management circuit202logically groups the physical blocks304(0)-304(R) of the rewritable non-volatile memory module106into a data area402, a free area404, a system area406, and a replacement area408.

Physical blocks in the data area402and the free area404are used for storing data received from the host system1000. To be specific, the physical blocks in the data area402are physical blocks already containing data, while the physical blocks in the free area404are used for substituting the physical blocks in the data area402. Thus, the physical blocks in the free area404are either blank or usable physical blocks (i.e., no data is recorded therein or data recorded therein is already marked as invalid data). Namely, an erasing operation is already performed on each physical block in the free area404, or before a physical block is selected from the free area404for storing data, an erasing operation is performed on the selected physical block. Thus, the physical blocks in the free area404are usable physical blocks.

Physical blocks logically belonging to the system area406are used for recording system data, such as the manufacturer and model of the memory storage apparatus, the number of physical blocks in the rewritable non-volatile memory module, and the number of physical pages in each physical block, etc.

Physical blocks logically belonging to the replacement area408are replacement physical blocks. For example, when the rewritable non-volatile memory module106is manufactured, a part of its physical blocks is reserved for replacement purpose. Namely, when physical blocks in the data area402, the free area404, and the system area406are damaged, the physical blocks reserved in the replacement area408are used for replacing the damaged physical blocks (i.e., bad blocks). Thus, if there are still normal physical blocks in the replacement area408and a physical block is damaged, the memory management circuit202selects a normal physical block from the replacement area408to replace the damaged physical block. If there is no more normal physical block in the replacement area408and a physical block is damaged, the memory management circuit202announces that the memory storage apparatus100is in a write protect state and cannot be used for writing data.

It should be understood that during the operation of the memory storage apparatus100, the physical blocks associated with the data area402, the free area404, the system area406, and the replacement area408dynamically changes. For example, when a physical block in the free area404is damaged and replaced by a physical block selected from the replacement area408, the physical block originally in the replacement area408is associated with the free area404.

The memory management circuit202configures logical blocks510(0)-510(H) to be mapped to the physical blocks in the data area402, wherein each of the logical blocks has a plurality of logical pages, and the logical pages are sequentially mapped to the physical pages in a corresponding physical block. For example, when the memory storage apparatus100is formatted, the logical blocks510(0)-510(H) are initially mapped to the physical blocks304(0)-304(D) in the data area402.

The memory management circuit202may maintain a logical block-physical block mapping table to record the mapping relationship between the logical blocks510(0)-510(H) and the physical blocks in the data area402. In addition, because the host system1000accesses data in units of logical access addresses (for example, sector), when the host system1000accesses data, the memory management circuit202converts a logical access address into a corresponding logical page. For example, when the host system1000is about to access a specific logical access address, the memory management circuit202converts the logical access address to be accessed by the host system1000into a multi-dimensional address composed of a corresponding logical block and a corresponding logical page and accesses the data in the corresponding physical page according to the logical block-physical block mapping table.

FIG. 5AandFIG. 5Bare diagrams of a plurality of program code copies of a program code stored in a rewritable non-volatile memory module according to the first exemplary embodiment of the invention.

Referring toFIG. 5AandFIG. 5B, the physical block304(N+1) and the physical block304(N+2) in the system area406are used for storing a first program code copy410corresponding to the program code used for controlling the overall operation of the memory controller104, and the physical block304(N+11) and the physical block304(N+12) in the system area406are used for storing a second program code copy420corresponding to the program code used for controlling the overall operation of the memory controller104. Herein the physical blocks used for storing the first program code copy410are referred to as first physical blocks, and the physical blocks used for storing the second program code copy420are referred to as second physical blocks.

In the present exemplary embodiment, two program code copies corresponding to the program code used for controlling the overall operation of the memory controller104are stored in the rewritable non-volatile memory module106. However, in another exemplary embodiment of the invention, more program code copies corresponding to the program code used for controlling the overall operation of the memory controller104can be stored in the rewritable non-volatile memory module106. In addition, in the present exemplary embodiment, one program code copy is stored by using two physical blocks. However, the present invention is not limited thereto, and the number of physical blocks for storing one program code copy varies with the size of the program code copy.

As described above, the physical block304(N+1) and the physical block304(N+2) store the first program code copy410, wherein the first program code copy410includes n data segments (i.e., data segments1A-nA, wherein n is a natural number), and the data segments of the first program code copy410are identical to the data segments of the program code used for controlling the overall operation of the memory controller104. Similarly, the physical block304(N+11) and the physical block304(N+12) store the second program code copy420of the program code, wherein the second program code copy420also includes n data segments (i.e., data segments1B-nB), and the data segments of the second program code copy420are identical to the data segments of the program code used for controlling the overall operation of the memory controller104. Namely, the data segments1A-nA of the first program code copy410are respectively identical to the data segments1B-nB of the second program code copy420.

Because adjacent physical blocks are related with each other to a certain extent when a damage occurs, in order to prevent adjacent physical blocks (and accordingly corresponding data segments in the first program code copy410and the second program code copy420) from being damaged at the same time, in the present exemplary embodiment, the first physical blocks storing the first program code copy410are not adjacent to the second physical blocks storing the second program code copy420. However, the present invention is not limited thereto.

In addition, if the physical blocks304(0)-304(R) belong to different memory dies, the first physical blocks and the second physical blocks respectively belong to different memory dies. For example, the physical blocks304(0)-304(R) respectively belong to a first memory die and a second memory die, wherein the physical block304(N+1) and the physical block304(N+2) belong to the first memory die, and the physical block304(N+11) and the physical block304(N+12) belong to the second memory die. Namely, the first program code copy410and the second program code copy420are respectively stored in different memory dies, so that the possibility that the two program code copies are damaged at the same time is further reduced.

Particularly, in the present exemplary embodiment, when the memory management circuit202reads a data segment of a program code copy from the rewritable non-volatile memory module106, the ECC circuit256executes an ECC procedure on the data segment. If the data segment contains an error bit, the ECC circuit256tries to correct the error bit. Besides, if the error bit cannot be corrected, the ECC circuit256determines that the data segment contains an uncorrectable error bit.

Particularly, when the ECC circuit256determines that a data segment of the first program code copy410contains at least one uncorrectable error bit, the memory management circuit202alternatively loads a part of the first program code copy410and a part of the second program code copy420. Namely, the memory management circuit202alternatively loads each data segment of the program code from the first program code copy410and the second program code copy420. This will be described below with reference to another example.

FIG. 6is an operation diagram of a program code accessing method according to a first exemplary embodiment of the present invention, wherein it is assumed that the data segment3A and the data segment (n−2)A of the first program code copy410contain error bits (as indicated by the areas with diagonal lines) that cannot be corrected by the ECC circuit256, and it is assumed that none of the data segment3B and the data segment (n−2)B of the second program code copy420contains any uncorrectable error bit.

Referring toFIG. 6, the memory management circuit202of the memory controller104sequentially loads the data segment1A and the data segment2A of the first program code copy410. Subsequently, while loading the data segment3A, because the ECC circuit256cannot correct the error bit, the memory management circuit202cannot load the data segment3A successfully. In this case, the memory management circuit202reads the data segment3B from the second program code copy420. After successfully loading the data segment3B, the memory management circuit202continues to load the next data segment4A from the first program code copy410.

Thereafter, the memory controller104sequentially loads the data segments5A-(n−3)A. Subsequently, while loading the data segment (n−2)A, because the ECC circuit256cannot correct the error bit, the memory management circuit202cannot load the data segment (n−2)A successfully. In this case, the memory management circuit202reads the data segment (n−2)B (the content thereof is identical to that of the data segment (n−2)A) from the second program code copy420. Besides, after successfully loading the data segment (n−2)B, the memory management circuit202continues to load the next data segment (n−1)A from the first program code copy410. Eventually, the memory controller104loads the data segment nA to finish the loading of the entire program code.

It should be noted that in the present exemplary embodiment, it is assumed that the data segment3B and the data segment (n−2)B of the second program code copy420do not contain any uncorrectable error bit. However, if the data segment3B or the data segment (n−2)B of the second program code copy420contains any uncorrectable error bit, the memory management circuit202outputs an error message.

It should be understood that in the present exemplary embodiment, it is assumed that there are only two program code copies corresponding to the program code. However, the present invention is not limited thereto. In an example wherein multiple program code copies are stored, when a data segment of one program code copy contains a uncorrectable error bit, the memory management circuit202tries to load the data segment from other program code copies until it determines that the correct data segment cannot be loaded from any of the program code copies and issues an error message.

FIG. 7AandFIG. 7Bare flowcharts of a program code accessing method according to the first exemplary embodiment of the invention, wherein the steps for storing a program code are illustrated inFIG. 7A, and the steps for loading the program code are illustrated inFIG. 7B.

Referring toFIG. 7A, first, in step S701, a first program code copy410corresponding to the program code is stored in the first physical blocks, and in step S703, a second program code copy420corresponding to the program code is stored into the second physical blocks.

In the present exemplary embodiment, the physical pages of the first physical blocks and the second physical blocks are sequentially used for storing the first program code copy410and the second program code copy420. However, the present invention is not limited thereto, and in another exemplary embodiment of the invention, the first program code copy410and the second program code copy420may also be stored into only specific physical pages of the first physical blocks and the second physical blocks.

To be specific, in the present exemplary embodiment, the rewritable non-volatile memory module106is a MLC NAND flash memory module. Thus, the physical pages of each physical block in the rewritable non-volatile memory module106can be categorized into a plurality of fast physical pages and a plurality of slow physical pages according to their writing characteristics.

To be specific, only single-staged programming can be performed on memory cells of a single level cell (SLC) NAND flash memory, and accordingly, each memory cell can only store one bit. Contrarily, the programming of physical blocks in a MLC NAND flash memory can be performed in multiple stages. For example, the programming of a 4-level cell is carried out in two stages. During the first stage, bits of lower physical pages are programmed, and the physical characteristics of these bits are similar to those of a SLC NAND flash memory. After the first stage is completed, bits of the upper physical pages are programmed. In particular, the write speed of lower physical pages is faster than that of upper physical pages, and the reliability of lower physical pages is higher than that of upper physical pages. Herein lower physical pages are also referred to as fast physical pages, and upper physical pages are also referred to as slow physical pages.

Similarly, an 8-level memory cell or a 16-level memory cell includes more physical pages, and data is written therein in more stages. Herein the physical pages having the fastest write speed are referred to as fast physical pages, and the other physical pages having slower write speeds are all referred to as slow physical pages. Additionally, in other embodiments, the slow physical pages may also be the physical pages having the slowest write speed or the physical pages having the slowest write speed and those physical pages having their write speeds faster than the slowest write speed.

For example, in a 16-level memory cell, the fast physical pages are physical pages having the fastest and the second fastest write speeds, and the slow physical pages are physical pages having the slowest and the second slowest write speeds.

Particularly, in another exemplary embodiment of the present invention, the memory management circuit202stores program code copies by using only the fast physical pages of the first physical blocks and the second physical blocks, so as to increase the access efficiency and reliability. Referring toFIG. 7B, in step S705, a data segment of the first program code copy410is loaded. Then, in step S707, whether the data segment contains any uncorrectable error bit is determined. To be specific, the ECC circuit256executes an ECC procedure on the data segment, and the memory management circuit202determines whether the data segment contains any uncorrectable error bit accordingly.

If the data segment contains an uncorrectable error bit, in step S709, the corresponding data segment is loaded from the second program code copy420. Then, in step S711, whether the corresponding data segment contains any uncorrectable error bit is determined. If the corresponding data segment contains an uncorrectable error bit, in step S713, an error message is output. If the corresponding data segment does not contain any uncorrectable error bit, in step S715, whether there are still other data segments to be loaded is determined. If there are still other data segments to be loaded, step S705is executed again to continue to load the next data segment of the first program code copy410. If there is no any other data segment to be loaded (i.e., the entire program code has been loaded), the program code loading procedure is terminated.

If it is determined in step S707that the data segment does not contain any uncorrectable error bit, step S715is executed to determine whether there are still other data segments to be loaded. If there is no any other data segment to be loaded (i.e., the entire program code has been loaded), the program code loading procedure is terminated. If there are still other data segments to be loaded, step S705is executed again to continue to load the next data segment from the first program code copy410.

Second Exemplary Embodiment

The memory controller, the memory storage apparatus, and the host system in the second exemplary embodiment of the present invention are substantially the same as those in the first exemplary embodiment, and the only difference falls on the program code loading method. To be specific, in the second exemplary embodiment, when an error occurs during the data segment loading procedure, the complete program code is read from two program code copies through a method different from that in the first exemplary embodiment. Below, the difference between the first exemplary embodiment and the second exemplary embodiment will be explained with reference toFIG. 2andFIG. 3.

FIG. 8is an operation diagram of a program code accessing method according to a second exemplary embodiment of the invention, wherein it is assumed that the data segment3A of the first program code copy410and the data segment (n−2)B of the second program code copy420contain error bits that cannot be corrected by the ECC circuit256(as indicated by the areas with diagonal lines), and it is assumed that none of the data segment3B of the second program code copy420and the data segment (n−2)A of the first program code copy410contains any uncorrectable error bit.

Referring toFIG. 8, the memory management circuit202of the memory controller104sequentially loads the data segments1A and2A of the first program code copy410. Subsequently, while loading the data segment3A, because the ECC circuit256cannot correct the error bit, the memory management circuit202cannot load the data segment3A successfully. In this case, the memory management circuit202reads the data segment3B from the second program code copy420. After successfully loading the data segment3B, the memory management circuit202continues to load the next data segment4B from the second program code copy420.

Thereafter, the memory controller104sequentially loads the data segments5B-(n−3)B. Subsequently, while loading the data segment (n−2)B, because the ECC circuit256cannot correct the error bit, the memory management circuit202cannot load the data segment (n−2)B successfully. In this case, the memory management circuit202reads the data segment (n−2)A (the content thereof is identical to that of the data segment (n−2)B) from the first program code copy410. Besides, after successfully loading the data segment (n−2)A, the memory management circuit202continues to load the next data segment (n−1)A from the first program code copy410. Finally, the memory controller104loads the data segment nA of the first program code copy410to complete the loading of the entire program code.

FIG. 9is a flowchart of a program code loading method according to the second exemplary embodiment of the invention.

Referring toFIG. 9, in step S905, a data segment of the first program code copy410is loaded.

Then, in step S907, whether the data segment contains any uncorrectable error bit is determined. For example, the ECC circuit256executes an ECC procedure on the data segment and determines whether the data segment contains any uncorrectable error bit accordingly.

If it is determined in step S907that the data segment does not contain any uncorrectable error bit, step S909is executed to determine whether there are still other data segments to be loaded. If there is no more data segment to be loaded (i.e., the entire program code has been loaded), the program code loading procedure is terminated. If there are still other data segments to be loaded, step S905is executed to continue to load the next data segment from the first program code copy410.

If it is determined in step S907that the data segment contains an uncorrectable error bit, in step S911, the corresponding data segment is loaded from the second program code copy420.

Next, in step S913, whether the corresponding data segment contains any uncorrectable error bit is determined.

If it is determined in step S913that the corresponding data segment contains an uncorrectable error bit, in step S915, an error message is output. If it is determined in step S913that the corresponding data segment does not contain any uncorrectable error bit, in step S917, whether there are still other data segments to be loaded is determined. If there is no more data segment to be loaded (i.e., the entire program code has been loaded), the program code loading procedure is terminated. If there are still other data segments to be loaded, in step S919, the next data segment of the second program code copy420is loaded.

After that, in step S921, whether the d data segment contains any uncorrectable error bit is determined. If it is determined in step S921that the data segment does not contain any uncorrectable error bit, in step S923, whether there are still other data segments to be loaded is determined. If there are still other data segments to be loaded, step S919is executed again to continue to load the next data segment of the second program code copy420. If there is no more data segment to be loaded (i.e., the entire program code has been loaded), the program code loading procedure is terminated.

If it is determined in step S921that the data segment contains an uncorrectable error bit, in step S925, the corresponding data segment is loaded from the first program code copy410.

Next, in step S927, whether the corresponding data segment contains any uncorrectable error bit is determined.

If it is determined in step S927that the corresponding data segment contains an uncorrectable error bit, an error message is output in step S929.

If it is determined in step S927that the corresponding data segment does not contain any uncorrectable error bit, in step S931, whether there are still other data segments to be loaded is determined. If there is no more data segment to be loaded (i.e., the entire program code has been loaded), the program code loading procedure is terminated. If there are still other data segments to be loaded, step S905is executed to continue to load the next data segment from the first program code copy410.

In summary, exemplary embodiments of the invention provide a program code loading method, a program code accessing method, a memory controller, and a memory storage apparatus, wherein a complete program code can be loaded from two or more program code copies, so that the situation that the program code cannot be successfully loaded and accordingly the system cannot be started caused by too many bit errors is avoided. Thereby, the reliability of the memory storage apparatus can be effectively improved. The previously described exemplary embodiments of the present invention have the advantages aforementioned, wherein the advantages aforementioned not required in all versions of the invention.