Pumped pinned photodiode pixel array

The present invention relates to a pumped pixel that includes a first photo-diode accumulating charge in response to impinging photons, a second photo-diode and a floating diffusion positioned on a substrate of the pixel. The pixel also includes a charge barrier positioned on the substrate between the first photo-diode and the second photo-diode, where the charge barrier temporarily blocks charge transfer between the first photo-diode and the second photo-diode. Also included is a pump gate positioned on the substrate adjacent to the charge barrier. The pump gate pumps the accumulated charge from the first photo-diode to the second photo-diode through the charge barrier in response to a pump voltage applied by a controller. Also included is a transfer gate positioned on the substrate between the second photo-diode and the floating diffusion. The transfer gate transfers the pumped charge from the second photo-diode to the floating diffusion in response to a transfer voltage applied by a controller.

FIELD OF THE INVENTION

The present invention relates, in general, to a complementary metal oxide (CMOS) imager that includes a plurality of pumped pixels for storing pixel charge before readout.

BACKGROUND OF THE INVENTION

In conventional dual pinned photo-diode pixels, one of the pinned photo-diodes is utilized as memory to store accumulated charge while reducing the effects of dark current. These conventional pixels, however, have well capacities that are limited to the difference in potential between adjacent wells. In general, a pinned photo-diode receiving charge must have a higher well potential than the well potential of a photo-diode supplying the charge. Charge transfer is performed similar to water transfer by pouring the charge from a lower well potential (shallow well depth) to a higher well potential (deep well depth). Due to limitations in voltage swing (i.e. potential between wells) in a pixel, the charge handling capacities are also limited.

DETAILED DESCRIPTION

As described below, the present invention provides a pumped pixel having dual photo-diodes (e.g. pinned photo-diodes) and at least one virtual charge barrier (e.g. a heavily p-doped region on the surface and an n-doped region underneath). One of the photo-diodes accumulates charge in response to impinging photons. The other photo-diode acts as a memory node that stores the accumulated charge.

In one example, the accumulated charge is pumped (by a pump gate) over the charge barrier and into the photo-diode for storage or into the floating diffusion for readout. In general, the charge barrier blocks the charge from leaking back into the photo-diode from where it was pumped. Being able to pump and store the charge may allow the imager to delay pixel readout and/or extend dynamic range without the need for large voltage differences (differences in well potentials) and/or doping between the photo-diode wells.

A six transistor (6T) circuit for a pixel150of a CMOS imager is illustrated inFIG. 1A. Pixel150is a 6T pixel, where 6T is used to designate the use of six transistors to operate a pixel. The 6T pixel150has photo-sensors such as exposed pinned photo-diode162, a shielded pinned photo-diode164, a reset transistor184, a transfer transistor190, a source follower transistor186, a row select transistor188, an anti-blooming gate166, a pump gate167and a charge barrier165.

It is noted thatFIG. 1Ashows the circuitry for operation of a single pixel150, and that in practical use, there may be an M×N array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.

Photodiode162accumulates photo-electrons generated in response to impinging photons. This accumulated charge is pumped over charge barrier165and into pinned photo-diode164for storage when activated by the PG control signal during a storage period. The stored charge is then transferred to floating diffusion stage node A through transfer transistor190when activated by the TX control signal during a readout period. The source follower transistor186has a gate terminal connected to node A and thus amplifies the signal appearing at floating diffusion node A. When a particular row containing pixel150is selected by an activated row select transistor188, the signal amplified by the source follower transistor186is passed on a column line170to a column readout circuitry242(shown inFIG. 2). Photodiode162accumulates a photo-generated charge in a doped region of the substrate (i.e. in a well). It is noted that the pixel150may include a photo-gate or other photon to charge converting device, in lieu of a pinned photodiode, as the initial accumulator for photo-generated charge.

The gate terminal of transfer transistor190is coupled to a transfer control signal line191for receiving the TX control signal, thereby serving to control the coupling of the photodiode164to node A. A voltage source Vpix is coupled through reset transistor184to node A. The gate terminal of reset transistor184is coupled to a reset control line183for receiving the RST control signal to control the reset operation in which the voltage source Vpix is connected to node A, pinned photo-diode164and pinned photo-diode162for clearing charge.

A row select signal (RS) on a row select control line160is used to activate the row select transistor188. Although not shown, the row select control line160may be used to provide a row select signal (RS) to all of the pixels of the same row of the array, as are the RST and TX lines. Voltage source Vpix is coupled to transistors184and186by conductive line195. A column line170is coupled to all of the pixels of the same column of the array and typically has a current sink176at its lower end. The upper part of column line170, outside of the pixel array, includes a pull-up circuit111which is used to selectively keep the voltage on column line170high. Maintaining a positive voltage on the column line170during an image acquisition phase of a pixel150keeps the potential in a known state on the column line170. Signals from the pixel150are therefore selectively coupled to a column readout circuit through the column line170and through a pixel output (“Pix_out”) line177coupled between the column line170and the column readout circuit.

In general, Pix_out line177is coupled to the sample and hold (S/H) column capacitors114and116(i.e. two capacitors per column line to perform correlated double sampling). Transistors110and112are also included to ensure that the pixel output signals (i.e. the potentials after reset and integration) are each stored on the appropriate capacitor. These two potentials are compared (i.e. subtracted from each other) to perform correlated double sampling.

In general, a value can be read from pixel150in a two step correlated double sampling process. Prior to a charge integration period, node A and the photo-diodes162and164are reset to a high potential by activating reset transistor184, transfer transistor190and pump gate167. Photodiode162can alternatively be reset to a high potential by activating anti-blooming gate166. During the charge integration period, photodiode162produces a charge from incident light. This is also known as the image acquisition period. Charges may be transferred from photo-diode162to photo-diode164by activating pump gate167. Before charge transfer, node A and photo-diode164are reset to a high potential by activating reset transistor184and transfer transistor190to remove parasitic charges accumulated in photo-diode164due to mechanisms such as dark current and light leakage.

During the readout period, node A is again reset to a high potential. The charge (i.e. reset signal) at node A after reset is readout to column line170via the source follower transistor186and row select transistor188. Readout circuitry242inFIG. 2then samples and holds the reset signal on capacitor116. Transfer transistor190is then activated, and the charge from photodiode164is passed to node A, where the charge is amplified by source follower transistor186and passed to column line170through row select transistor188. Readout circuitry242then samples and holds the integrated charge signal on capacitor114. As a result, two different voltage signals are readout, sampled and held on capacitors114and116for further processing. Typically, all pixels in a row are readout simultaneously onto respective column lines170.

FIG. 2shows an example CMOS imager integrated circuit chip201that includes an array230of pixels and a controller232, which provides timing and control signals to enable reading out of signals stored in the pixels. Exemplary arrays have dimensions of M×N pixels, with the size of the array230depending on a particular application. In general, the pixels in the array are reset, exposed to light and readout on a row by row basis (rolling shutter mode), or all the pixels in the array are simultaneously reset, exposed to light, and then readout row by row (global shutter mode). It is noted that the present invention may be utilized in either rolling shutter mode or global shutter mode to increase dynamic range and/or delay pixel readout.

In general, the pixel signals from the array230are read out a row at a time using a column parallel readout architecture. The controller232selects a particular row of pixels in the array230by controlling the operation of row addressing circuit234, row drivers240and column addressing circuit244. Signals corresponding to charges stored in the selected row of pixels and reset signals are provided on the column lines170to a column readout circuit242in the manner described above. The pixel signal read from each of the columns can be read out sequentially using a column addressing circuit244. Pixel signals (Vrst, Vsig) corresponding to the readout reset signal and integrated charge signal are provided as respective outputs Vout1, Vout2of the column readout circuit242where they are subtracted in differential amplifier246, digitized by analog to digital converter248, and sent to an image processor circuit250for image processing.

Shown inFIG. 1Bis a cross sectional view of a pixel substrate shown inFIG. 1A. Specifically, a substrate130may include pinned photo-diodes162and164separated by pump gate167and charge barrier165. The regions under the photodiodes, and the regions151,153(A),153(B) and152under the anti-bloom gate, pump gate and transfer gate respectively include charge wells for storing charge. It is noted that increasing the well potential lowers the well (makes the well deep for charge storage), whereas decreasing the well potential raises the well (makes the well shallow for blocking and/or transferring charge).

During operation, pinned photo-diode162accumulates charge based on impinging photons. This accumulated charge is held in pinned photodiode162due to raised wells151and153(A). The well depths of the various gates may be modulated (raised or lowered) based on the voltage applied to the gate terminals (i.e., based on the voltage signal AB, PG and TX).

For example, during the integration period, anti-blooming gate166and pump gate167are driven by a negative voltage which raises the wells so that charge is isolated in pinned photo-diode162. Then, during a storage period (i.e., after and/or during integration), the pump gate167is driven by a positive voltage to lower a clock barrier in region153(A) and a clock well in region153(B). In general, the clock barrier and clock well are differently doped regions under the pump gate (e.g. the clock well is doped to be deeper than the clock barrier). This allows charge from pinned photo-diode162to transfer (i.e. spill over) into lowered clock well153(B). Once the clock well is filled, pump gate167is then driven by a negative voltage which raises clock barrier153(A) and clock well153(B) thereby transferring (i.e. pumping) the charge over the top of barrier165and into pinned photo-diode164for storage. In general, the clock barrier (due to being higher than the clock well) prevents charge stored in the clock well from spilling back into the first pinned photo-diode during the pumping process. During both the integration and storage period, transfer gate190is closed by applying a negative voltage therefore raising the transfer gate well and blocking charge from spilling into floating diffusion A. However, during a readout period, transfer gate190is pulsed with a high positive voltage which lowers the transfer gate well thereby transferring the stored charge from pinned photo-diode164and into floating diffusion A where the pixel readout procedure (described above) is performed.

In general, the substrate may be designed (i.e., doped) such that the wells in pinned photo-diode162and164have equivalent capacity. In this example, pump gate167is able to pump the charge from pinned photo-diode162over the charge barrier and into pinned photo-diode164regardless of the well depth of the photodiodes.

In another example, the well capacity of pinned photo-diode164may be greater (i.e. deeper) than the well capacity of pinned photo-diode162. This allows for increased dynamic range. As pinned photo-diode162is accumulating charge, pump gate167may periodically (during the integration period) pump the accumulating charge into pinned photo-diode164(which has a deeper well than162) thereby allowing a longer integration time where pinned photo-diode162accumulates with charge multiple times. It is noted that pump gate167may be modulated one time or multiple times during or after integration in order to pump the charge from pinned photo-diode162into pinned photo-diode164. It is also noted that clock well153(B) may be designed to have the same capacity or smaller capacity than pinned photo-diode162in order to transfer the charge in a single pump or in multiple repeated pumps. It is also noted that anti-blooming gate166is optional. Anti-blooming gate166allows excess charge accumulated by pinned photo-diode162to spill over to potential Vpix rather than spilling over into adjacent pixels. Moreover, the anti-blooming gate166can be used to reset photo-diode162.

The charge barrier may be positioned between other areas of the substrate. For example, shown inFIG. 1Cthe charge barrier and pump gate are located between the second pinned photo-diode164and floating diffusion A (i.e. transfer gate and pump gate/barrier are swapped). In this example, accumulated charge in pinned photo-diode162may be transferred over to pinned photo-diode164for storage during a storage period. Then, during a readout period, the charge stored in pinned photo-diode164may be pumped over charge barrier165into floating diffusion A. In this example, a transfer gate has a region153under the gate, and pump gate has regions152(A) and152(B) which are the clock barrier and clock well respectively.

In another example, as shown inFIG. 1D, the pumped pixel may include two pump gates167and190, and two charge barriers165(A) and165(B) (i.e., there may be a pump gate and charge barrier between both pinned photo-diodes and between the pinned photo-diode and the floating diffusion). In general, the first pump gate may include region153(A) and153(B) while the second pump gate may include regions152(A) and152(B) (i.e., the clock barriers and clock wells respectively). The charge barriers may be denoted as165(A) and165(B).

During operation, the charge accumulated by pinned photo-diode162may be pumped over charge barrier165(A) and stored in pinned photo-diode164. Then, during a readout period, the charge stored in pinned photo-diode164may be pumped over charge barrier165B and into the floating diffusion A.

It is noted that inFIGS. 1B-1D, the wells of the pinned photo-diode and the floating diffusion may be designed (i.e. doped) to be shallow or deep depending on the position of the pump gate. For example, as shown inFIG. 1D, the wells for pinned photo-diodes162,164and floating diffusion A may be all the same depth since there is a pump between the regions. However, in another example, the wells under pinned photo-diode164and floating diffusion A may be deeper than that of pinned photo-diode162in order to store more charge and increase dynamic range of the pixel.

Shown inFIGS. 3A-3Gare cross sectional views of the pumped pixels showing the flow of charge at each stage during integration, storage and readout. The operation of the pixel inFIG. 1Bis now described with respect ofFIGS. 3A-3G.

During an integration period, pump gate167and transfer gate190have negative voltage signals PG and TX thereby raising the clock barrier and clock well390and392and transfer well394. During the integration time, the first pinned photo-diode162is accumulating charge302. Since clock barrier390is raised, charge302is isolated in pinned photo-diode162.

Then, during a storage period (which may be after the integration period or during the integration period), pump167voltage PG is increased to a positive voltage which lowers clock barrier390and clock well392. When clock well392is lowered, some or all of the charge (i.e., depending on the size of clock well392) is transferred from the first pinned photo-diode162and into the clock well392as charge304(seeFIG. 3B).

During the second half of the storage period, the pump gate167voltage PG is set to a negative voltage which raises clock barrier390and clock well392thereby pumping charge304over the top of the charge barrier and into the second pinned photo-diode164as charge306(seeFIG. 3C). Since the clock well is raised (i.e. doped differently) with respect to the clock well, charge in the clock well is blocked from spilling back into the first photo-diode during pumping.

The pumping period may be repeated a plurality of times to pump all of charge302from the first pinned photo-diode162over the charge barrier and into the second pinned photo-diode164(charge302has been moved to306). In general, charge306is isolated in the second pinned photo-diode164due to the charge barrier and the raised transfer well394(seeFIG. 3D).

After the storage period, (i.e., during the readout period), transfer gate190may have its TX voltage increased to a positive voltage which lowers transfer well394allowing charge306to spill over (i.e., transfer) into floating diffusion A as charge308(seeFIG. 3E). Once the charge308is transferred into the floating diffusion, the source follower transistor converts the charge to a voltage which is readout as pix_out177(see description of pixel readout as described above).

As shown inFIGS. 1C and 1D, the pump gate may be moved to different regions in the pumped pixel. For example, as shown inFIG. 3F, the pump gate and charge barrier may be swapped with the transfer gate. In this example, during an integration period, transfer gate167and pump gate190may be biased with a negative voltage which raises their respective wells allowing charge to accumulate in first photodiode162.

During the storage period, the voltage on transfer gate167may be increased to a positive voltage which lowers transfer well394allowing charge to spill over into second photodiode164for storage. Then, during a readout period, the pump gate190may have its voltage increased to a positive voltage which lowers clock barrier390and clock well392to fill up with the charge from photodiode164. Once a negative voltage is then applied to pump gate190, the charge in clock well392will pour over the charge barrier165and into floating diffusion A as charge320. As described above, the pumping may be performed in a single pump or multiple pumps depending on the amount of charge.

Similarly, inFIG. 3G, the transfer gate may be replaced with another pump gate (i.e., two pump gates may be utilized). During integration, pump gates167and168are held at negative voltages (i.e., their respective clock barriers and clock wells are raised therefore allowing charge to accumulate in photodiode162). During the storage period, pump gate167voltage may be modulated (i.e., changed to a positive and negative voltage repeatedly) to pump the charge from pinned photo-diode162over charge barrier165(A) and into pinned photo-diode164as charge306. During the readout period, pump gate168voltage may be modulated (i.e., changed to a positive and negative voltage repeatedly) to pump the charge from pinned photo-diode164over charge barrier165(B) and into the floating diffusion A as charge320.

It is noted that the well capacities of the pinned photo-diodes, pump gates, transfer gates and floating diffusions may be designed (i.e., doped and biased) differently. For example, the charge barrier165may be taller or shorter depending on the doping. Similarly, the clock barrier and the clock well on the pump gate may be able to pump more or less charge depending on their relative difference with respect to each other.

As described above, the imager may operate in a rolling shutter mode or a global shutter mode. In a rolling shutter mode, three pointers may be employed (i.e., a reset pointer, a storage pointer and a read pointer). In operation, the reset pointer may traverse from the top to the bottom of the array performing a row by row pixel reset (i.e. the pinned photo-diodes, floating diffusions and gate wells for the pixels in each row are reset to a potential).

Behind the reset pointer may be one of more storage pointers which may traverse from the top to the bottom of the array transferring (i.e., pumping) the charge accumulated in the photodiode into the second pinned photo-diodes for storage. Behind the storage pointer may be a read pointer which may also traverse from the top to the bottom of the pixel array to perform row by row charge transfer of the charge from the second pinned photo-diode into the floating diffusion for read out. In one example, a storage pointer is immediately positioned before the read pointer. Other storage pointers may also be positioned before the read pointer to increase dynamic range.

The storage pointer may be beneficial in rolling shutter mode to control pixels to avoid large voltage swings and/or to increase dynamic range. Specifically, the first pinned photo-diode162may be controlled to accumulate charge repeatedly which is then periodically transferred over the barrier and stored (using the multiple storage pointers) in a second pinned photo-diode164.

In a global shutter mode, each pixel in every row is exposed during the integration period simultaneously, while the rows are still read out sequentially similar to the rolling shutter. Thus, in global shutter mode, a storage of each pixel value may be beneficial for delaying readout. For example, the first pinned photo-diode162of every pixel may accumulate charge during the integration period and then have that charge pumped into the second pinned photo-diode164for storage. That stored charge may then be accessed (i.e., transferred into the floating diffusion) at a later time when the pixels are read out row by row, and while the first photo-diode162is accumulating charge for the next image.

Accordingly, the present invention provides a pumped pixel which includes at least one pump gate and one charge barrier. In general, charge is pumped over the charge barrier by modulating a clock barrier and clock well located below the pump gate. The combination of the pump gate and charge barrier in the pumped pixel allows for adjacent photodiodes to have similar well potentials while still being able to transfer charge (i.e., large well potential differences may be avoided).