Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.

PRIORITY STATEMENT

BACKGROUND

1. Technical Field

The inventive concept relates to methods of fabricating semiconductor devices. More particularly, the inventive concept relates to a semiconductor device including a gate electrode and to a method of fabricating the same.

2. Description of Related Art

The fabricating of semiconductor devices entails forming various patterns using a mask. An example of such a patterning process is the etching of a silicon-containing conductive layer to form a conductive pattern such as a pattern of gate electrodes. The patterning process is followed by a deposition process in which an interlayer dielectric is deposited to fill the space between the gate electrodes. However, when the silicon-containing conductive layer is etched, byproducts of the etching process are produced on the mask. A void or a seam may be formed in the interlayer dielectric due to the etch byproducts. The void or the seam can degrade the electrical characteristics of the semiconductor device.

SUMMARY

According to another aspect of the inventive concept, there is provided a method of fabricating a semiconductor device in which at least one conductive layer is formed on a gate dielectric layer, a mask is formed on the conductive layer(s), and the conductive layer(s) is/are patterned by etching the conductive layer(s) using the mask as an etch mask to thereby form the gate electrode but wherein an oxide byproduct of the etch process may accumulate on the mask. The oxide of the gate dielectric layer and the material of the at least one conductive layer are selected, though, such that the byproduct of the etch process will have an etch selectivity and, in particular, a higher etch rate with respect to a specified etchant, than the oxide of the gate dielectric layer.

According to another aspect of the inventive concept, there is provided a method of fabricating a semiconductor device in which a gate dielectric layer comprising an oxide is formed on a substrate, a first conductive layer comprising silicon is formed on the gate dielectric layer, a second conductive layer comprising a metal or a metal compound is formed on the first conductive layer, a mask is formed on the second conductive layer, an anisotropic etch process is performed on the conductive layers using the mask as an etch mask to thereby form spaced apart gate electrodes each having a segment of the mask thereon, an etch process is subsequently performed to remove a byproduct of the anisotropic etch process from the mask, a source/drain region is formed adjacent opposite sides of the gate electrodes, interlayer dielectric is subsequently deposited on the substrate to such a thickness as to fill openings between the gate electrodes, a contact hole is formed in the interlayer dielectric to expose the source/drain region, and a contact plug is formed in the contact hole.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various embodiments and examples of embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. In the drawings, the sizes and relative sizes and shapes of elements, layers and regions, such as implanted regions, shown in section may be exaggerated for clarity. In particular, the cross-sectional illustrations of the semiconductor devices and intermediate structures fabricated during the course of their manufacture are schematic. Also, when like numerals appear in the drawings, such numerals are used to designate like elements.

Furthermore, spatially relative terms are used to describe an element's and/or feature's relationship to another element(s) and/or feature(s) as illustrated in the figures. Thus, the spatially relative terms may apply to orientations in use which differ from the orientation depicted in the figures. Obviously, though, all such spatially relative terms refer to the orientation shown in the drawings for ease of description and are not necessarily limiting as embodiments according to the inventive concept can assume orientations different than those illustrated in the drawings when in use.

It will also be understood that when an element or layer is referred to as being “on” or “over” or “connected to” another element or layer, it can be directly on or over or directly connected to the other element or layer or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly” on or over or “directly” connected to another element or layer, there are no intervening elements or layers present.

Other terminology used herein for the purpose of describing particular examples or embodiments of the inventive concept is to be taken in context. For example, the terms “comprises” or “comprising” when used in this specification specifies the presence of stated features or processes but does not preclude the presence or additional features or processes.

Examples of a method of fabricating a semiconductor device according to the inventive concept will now be described with reference toFIGS. 1A to 1O.

Referring first toFIG. 1A, a field area104may be formed in a substrate100to define an active area102. For example, the field area104may be formed by a shallow trench isolation (STI) process. More specifically, the field area104may be formed by forming a trench in the substrate100and depositing an oxide, nitride or oxynitride (e.g., silicon oxide, silicon nitride or silicon oxynitride, respectively) in the trench. The active area102delimited by the field area104may have a linear form, as an example, i.e., may be elongated in a first direction.

The substrate100may be a silicon (Si) substrate, a silicon-germanium (Si—Ge) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a silicon-germanium-on-insulator (SGOI) substrate. Furthermore, the substrate100may be doped with (first) impurities of a predetermined (first) conductivity type. For example, in this embodiment of the inventive concept, the substrate100is doped with P-type impurities. The P-type impurities may be boron (B), gallium (Ga), or indium (In).

Referring toFIG. 1B, a gate dielectric layer106, a first conductive layer108, and a second conductive layer110may be formed on the substrate100. According to an embodiment of the inventive concept, the gate dielectric layer106may comprise silicon oxide. In this case, the gate dielectric layer106may be formed by a chemical vapor deposition (hereinafter referred to as “CVD”) process, an atomic layer deposition (hereinafter referred to as “ALD”) process or a thermal oxidation process.

According to another embodiment of the inventive concept, the gate dielectric layer106may comprise a metal oxide layer. Examples of the metal oxide include tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, niobium oxide, cesium oxide, yttrium oxide, indium oxide and iridium oxide. Furthermore, the gate dielectric layer106may be a laminate. In this case, the gate dielectric layer106may be formed by a CVD process, an ALD process or a metal organic CVD (MOCVD) process.

The first conductive layer108may be formed on the gate dielectric layer106. The first conductive layer108contains silicon. For example, the first conductive layer108may be a layer of polysilicon doped with (second) impurities of a conductivity type different from that of the active area102, i.e., the first conductive layer108may be a layer of polysilicon doped with impurities of a second conductivity type. The second impurities thus may be N-type impurities such as phosphorous (P) or arsenic (As).

The second conductive layer110may be formed on the first conductive layer108. The second conductive layer110may comprise a metal, i.e., consists of a metal or a metal compound. For example, the second conductive layer110may comprise tungsten (W), tantalum (Ta), titanium (Ti), copper (Cu), titanium nitride (TiN), cobalt nitride (CoN) or a combination thereof.

The second conductive layer110may be formed by a physical vapor deposition (PVD) process such as a sputtering process. Therefore, the second conductive layer110may prevent a defect, such as whisker growth, at a metal layer during a subsequent (ashing or annealing) process. This will be described more fully later on with reference to Experiment Examples 1.

Referring toFIG. 1C, a gate electrode118may be formed on the gate dielectric layer106.

More specifically, a mask112may be formed on the second conductive layer (110inFIG. 1B). The mask112may comprise a nitride, e.g., silicon nitride. The first and second conductive layers (108and110inFIG. 1B) are patterned by an anisotropic etch process using the mask112. Preferably, the process of etching the first and second conductive layers108and110may be a plasma etch process.

As a result of the anisotropic etch process, gate electrodes118including a first conductive pattern114and a second conductive pattern116are formed on the gate dielectric layer106. Each gate electrode118may extend in a second direction which is substantially different from the first direction. In addition, an opening120may be formed between gate electrodes118.

An etch byproduct122may be produced on the mask112during the plasma etch process. In particular, the etch byproduct122may be produced during the etching of the first conductive layer108and thus, may comprise silicon oxide. As a result, a projection may be formed on an upper portion of the mask112. If left unattended, the upper portion of mask112could cause a void or a seam to be formed in an interlayer dielectric deposited to fill the opening120.

Referring toFIG. 1D, the etch byproduct122may be removed from the mask112. In this embodiment of the inventive concept, the etch byproduct122may be removed from the mask112by an isotropic etch process.

In examples of the inventive concept in which the gate dielectric layer may comprise silicon oxide and the etch byproduct122may be formed as the result of the plasma etching of doped polysilicon constituting the first conductive layer108, the etch byproduct122may be removed by an isotropic etch process that etches the byproduct122at a rate that is about five times higher than that of the gate dielectric layer106. To this end, the etchant employed in the isotropic etch process may comprise diluted hydrofluoric acid (HF), diluted ammonium fluoride (NH4F) or a combination thereof.

In any case, the gate dielectric layer106may be not be substantially etched during the removal of the etch byproduct122. Accordingly, a DRAM including a transistor comprising gate electrode118will have optimal refresh operation characteristics. This will be described more fully later on with reference to Experimental Examples 2.

Furthermore, as alluded to above, a dielectric layer filling the opening120will be free of voids or a seam. This will be described more fully later on with reference to Experimental Examples 5.

Referring toFIG. 1E, a first capping layer124may be then conformally formed on the substrate100, thereby covering the mask112and the gate electrode118. The capping layer124thus does not fill the opening120.

The first capping layer124may comprise an oxide, e.g., silicon oxide. Preferably, the first capping layer124may be formed by an ALD process because an oxide layer formed by an ALD process may be clearer than an oxide layer formed by a thermal oxidation process or a CVD process.

Referring toFIG. 1F, a selective oxidation process may be then optionally performed.

The selective oxidation process may be performed to cure the first conductive pattern114of plasma damage incurred when the first and second conductive layers (108and110inFIG. 1B) are anisotropically etched. As a result, the selective oxidation process may cause the first conductive pattern114to become substantially wider than the second conductive pattern116or the mask112.

Referring toFIG. 1G, a second capping layer126may be then conformally formed on the substrate100, thereby covering first capping layer124. Thus, the second capping layer126does not fill what remains of the opening120.

The second capping layer126may comprise a nitride, e.g., silicon nitride. Preferably, the second capping layer126may be formed by an ALD process because a nitride layer formed by the ALD process is clearer than a nitride layer formed by a CVD process.

Referring toFIG. 1H, a first impurity region128and a halo region130may be formed on the substrate100adjacent to opposite sides of the gate electrode118.

More specifically, (third) impurities of the second conductivity type may be implanted into the substrate100to form the first impurity region128adjacent opposite sides of the gate electrode118, i.e., such that boundary of the first impurity region128is substantially vertically aligned with the sides of the gate electrode118. For example, in the case in which the substrate100contains P-type impurities, the third impurities may be N-type impurities. In this process, the third impurities diffuse into the substrate100below the first and second capping layers124and126.

An ion implantation mask (not shown) may then be formed to cover a central portion of the first impurity region128. Then (fourth) impurities of the first conductivity type are implanted to form halo region130beneath sides of the first impurity region128. For example, in the case in which the first impurities are N-type impurities, the fourth impurities may be P-type impurities. The ion implantation mask may then be removed.

Referring toFIG. 1I, a spacer layer132may be conformally formed on the second capping layer126. Thus, the spacer layer132does not fill what remains of the opening120.

The spacer layer132may comprise a nitride, e.g., silicon nitride. In addition, the spacer layer132may be formed by a CVD process or an ALD process.

Referring toFIG. 1J, the spacer layer132and the first and second capping layers124and126are etched to form a first capping pattern134, a second capping pattern136, and a spacer138on sidewalls of the gate electrode118and the mask112. In an example of this embodiment of the inventive concept, the first and second capping layers124and126are etched by an anisotropic etch process. In this process, those collective portions of the spacer layer132and the first and second capping layers124and126which lie directly over the mask112and the substrate100are removed, while those portions of the spacer layer132and the first and second capping layers124and126which extend along the sidewall surfaces of the gate electrode118are basically not removed. Thus, first and second capping patterns134,136and a spacer138are formed on the sidewall surfaces of the gate electrode118and the mask112.

Referring toFIG. 1K, a second impurity region140may be formed on the substrate100.

More specifically, (fifth) impurities of the second conductivity type are implanted into the substrate100so that the second impurity region140may be formed adjacent opposite sides of the second capping pattern136, i.e., such that the boundary of the second impurity region140may be substantially vertically aligned with the outwardly facing sides of the second capping pattern136. For example, in the case in which the substrate100may be originally doped with P-type impurities and the first impurity region128contains N-type impurities, the fifth impurities are N-type impurities. Furthermore, the fifth impurities are implanted to such a depth that the second impurity region140may be substantially deeper than the first impurity region128. Also, the concentration of impurities at which the substrate is doped to form the second impurity region140may be substantially greater than the concentration of impurities at which the substrate was doped to from the first impurity region128.

As a result, a source/drain region142including the first and second impurity regions128and140may be formed. In the above-described example in which the first impurity region128was formed using a substantially lower concentration of impurities than the second impurity region140, the source/drain region142may be said to have a lightly doped drain (LDD) structure.

Accordingly, a transistor including the gate dielectric layer106, the gate electrode118, the mask112, the first and second capping patterns134and136, and the source/drain region142may be formed on the substrate100.

Referring toFIG. 1L, an etch-stop layer144may be conformally formed on the substrate100, thereby covering the transistor. Thus, the etch-stop layer144does not fill what remains of the opening120.

Referring toFIG. 1M, an interlayer dielectric146may be formed on the substrate100to such a thickness as to fill the opening120.

The interlayer dielectric146may comprise an oxide such as silicon oxide, a nitride such as silicon nitride or an oxynitride such as silicon oxynitride. Examples of the silicon oxide include BSG, PSG, BPSG, and PE-TEOS as well as an HDP oxide.

A seam of void may be not formed in that portion of the interlayer dielectric146formed between the gate electrodes118because, as mentioned above, the opening120may be widened at its top by removing the etch byproduct122from on the mask.

Referring toFIG. 1N, the interlayer dielectric146may be etched to form a contact hole148that exposes the source/drain region142. More specifically, an etch mask may be formed on the interlayer dielectric146. The interlayer dielectric layer146may be etched using the etch mask to form a contact hole148. At this time, the etch-stop layer144serves to establish an endpoint for the etch process. Once the contact hole148may be formed, the etch mask may be removed.

Referring toFIG. 1O, the contact hole148may be filled to form a contact150electrically connected to the source/drain region142. The contact150may also be electrically connected to a bit line or a capacitor formed in a subsequent process. The gate electrode118and the contact150are isolated from each other by the first and second capping patterns134and136to maximize a breakdown voltage between the gate electrode118and the contact150connected to the source/drain region142. This will be described more fully later on with reference to Experimental Examples 3.

Experimental Examples 1

FIG. 2Aillustrates characteristics of a metal layer after an ashing process or an annealing process.

More specifically, inFIG. 2A, reference numeral10designates first tungsten layers10formed by a PVD process and reference numeral20designates second tungsten layers20formed by a CVD process. The first tungsten layers10and the second tungsten layers20are subjected to an ashing process and an annealing process, respectively.

As shown inFIG. 2A, hardly any whisker growth is observable in the tungsten layer10formed by the PVD process and then subjected to the ashing process or the annealing process. On the other hand, whisker growth is observed in the tungsten layer20formed by the CVD process and then subjected to the ashing process or the annealing process. Such whisker growth may cause an electrical defect such as a short-circuit.

Thus, asFIG. 2Ashows, a gate electrode including a metal layer formed by a PVD process has better electrical characteristics than that including a metal layer formed by a CVD process.

Experimental Examples 2

FIG. 2Bis a graphic representation of the dependence of refresh-failure bits on oxide thickness of a semiconductor device, namely a dynamic random access memory (DRAM) device each including a transistor (“A”, “B”, “C”, or “D”) and contact formed similarly to the method described with reference toFIGS. 1A to 1O, and a bit line, and a capacitor. The transistors “A”, “B”, “C”, or “D” thus each include a gate dielectric layer106, a gate electrode118, a mask112, first and second capping patterns134and136, and a source/drain region142.

The X-axis inFIG. 2Brepresents the physical thickness (in units of angstroms, A) of an oxide layer formed on the gate electrode118of a transistor of the DRAM and the Y-axis represents the number of refresh-failure bits of the DRAM. The physical thickness of the oxide layer includes the thickness of any byproduct122and the thickness of the first capping pattern134.

In each of the transistors “A” and “B”, the etch byproduct122was fully removed by an isotropic etch process performed for about 60 seconds. The first capping pattern134of the transistor “A” had a thickness of about 20 Å, and the first capping pattern134of the transistor “B” had thickness of about 40 Å. As shown inFIG. 2B, the number of refresh-failure bits of the transistor “A” was about 410, and the number of refresh-failure bits of the transistor “B” was about 300.

On the other hand, the transistors “C” and “D” each included a first capping pattern134and the etch byproduct122. Specifically, the transistor “C” was isotropically etched for only about 30 seconds thereby leaving an etch byproduct having a thickness of 48 Å. Transistor “D” was isotropically etched for only about 15 seconds thereby leaving an etch byproduct having a thickness of about 74 Å. Furthermore, the first capping pattern134of each of the transistors “C” and “D” was formed to a thickness of about 20 Å. Referring again toFIG. 2B, the number of refresh-failure bits of the transistor “C” was about 280 and the number of refresh-failure bits of the transistor “D” was about 170.

FIG. 2Bshows that the number of refresh-failure bits is inversely proportional to the thickness of the oxide layer.

More specifically, in the case in which the etch byproduct122is not present as in the transistors “A” and “B”, the transistor having the thicker first capping pattern134(namely, transistor “B”) has a substantially smaller number of refresh-failure bits. In the case in which the first capping patterns134have the same thicknesses but in which etch byproduct122is present as in the transistors “C” and “D”, the transistor having the thicker etch byproduct (namely transistor “D”) has a substantially smaller number of refresh-failure bits.

Experimental Examples 3

FIG. 2Cis a graphic representation of breakdown voltage between gate electrodes and contacts of DRAM devices. The X-axis represents contact resistance (in units of ohms, Ω) and the Y-axis represents breakdown voltage (in units of volts, V) between a gate electrode and a contact of a DRAM device. Note also, that the resistance values are those of 1000 contacts because it is not possible to measure resistance of just one contact. The measured values were linearized to obtain plot B of the graph.

In the graph ofFIG. 2C, the DRAM devices whose breakdown voltages are indicated by plots A and B each included transistors and contacts fabricated similarly to the method described with reference toFIGS. 1A to 1Obut in which the oxide capping pattern134was not provided. In each of the DRAM devices used to produce plot A, the etch byproduct122was completely removed. However, in each of the DRAM devices used to produce plot B, the isotropic etch process was performed for only about 15 seconds thereby leaving part of the etch byproduct122on the mask112.

As shown inFIG. 2C, the DRAM devices used to produce plot B had a breakdown voltage of about 13.6 V and the DRAM devices used to produce plot A had a breakdown voltage of about 10.1 V when the resistance of the contacts150of the DRAMs was about 1.6×103Ω. Accordingly, it will be understood that breakdown voltage between the contact150and the gate electrode118is improved when more of the etch byproduct122is removed.

Experimental Examples 4

FIG. 2Dis a graphic representation of the dependence between retention time and the presence of an oxide capping pattern in DRAM devices. The X-axis represents retention time (in units of milliseconds, ms) and the Y-axis represents the number of refresh-failure bits per 1 gigabyte DRAM. Retention time refers to the time from one refresh operation of the DRAM to the next.

InFIG. 2D, the symbols (-▪-) indicate the results obtained from a transistor including a gate dielectric layer106formed by a rapid thermal oxidation process and the symbols (-●-) indicate results obtained from a transistor including a gate dielectric layer106formed by the rapid thermal oxidation process and a capping pattern134formed of an oxide by an ALD process. That is, the transistor used to obtain the results indicated by the symbols (-▪-) did not include an oxide capping pattern134.

As shown inFIG. 2D, retention time of a transistor having an oxide capping pattern134is about 282 ms for the case of 100 refresh-failure bit. In the same case but for a corresponding transistor which does not include a capping pattern134, the retention time was about 243 ms. Accordingly, it will be understood that the capping pattern134serves to extend the retention time.

Experimental Example 5

FIG. 2Eis a map of transistors completed up to the step shown inFIG. 1Maccording to the inventive concept, and indicating voids and seams in the interlayer dielectric146. In the experimental example depicted byFIG. 2E, several spots across an array of the transistors were examined and the number of seams of voids found in the interlayer dielectric146at each of such spots is indicated.

As shown inFIG. 2E, one void or seam was found at a spot A and two voids or seams were found at a spot B. Substantially, no voids or seams were found at the other spots in the interlayer dielectric146. Accordingly, it will be understood that the inventive concept, in which the etch byproduct is removed, minimizes the number of voids and seams that are otherwise likely to be produced in the interlayer dielectric146.

From the results illustrated in and described with reference toFIGS. 2B to 2E, it will be understood that as the oxide layer surrounding the gate electrode increases, the number of refresh-failure bits decreases, the breakdown voltage is improved, and the retention time increases. However, a void or a seam may be formed in the interlayer dielectric146if the etch byproduct122remains on the mask112.

Thus, in an embodiment of the inventive concept, the etch byproduct122is removed. However, to compensate for the reduction in thickness of the oxide surrounding the gate electrode118, a capping pattern134comprising an oxide is formed by ALD. Thus, an oxide layer of superior quality is formed despite its minimal physical thickness. As a result, the semiconductor device according to the inventive concept retains excellent characteristics pertaining to its refresh operation, breakdown voltage, and retention time.

Moreover, the capping pattern134formed by the ALD process has better dielectric characteristics than a capping pattern formed by a thermal oxidation process or a CVD process.

Application Examples

FIG. 3Aillustrates an example of a memory card including an embodiment of a semiconductor device according to the inventive concept.

Referring toFIG. 3A, the memory card300includes a memory controller320that controls data exchange between a host and a memory420including a semiconductor device according to the inventive concept. In this example, an SRAM321is used as a working memory of a central processing unit (CPU)324. A host interface326provides the data exchange protocol for a host to which the memory card300is to be connected. An error correction code circuit (ECC)328detects and corrects errors in data read from the memory420. A memory interface330interfaces with the memory420. The CPU324performs an overall control of the data exchange executed by the memory controller320.

FIG. 3Billustrates an example of an information processing system400having a semiconductor device according to the inventive concept.

Referring toFIG. 3B, the information processing system400may constitute a mobile device, a computer or the like. The information processing system400includes a memory system410including a memory controller412and a memory414having a semiconductor device according to the inventive concept, a modem420, a central processing unit (CPU)430, a RAM440, and a user interface450electrically connected to a system bus460. Data processed by the CPU430or externally input data may be stored in the memory system410. The memory system410may be embodied as a memory card and thus may have the same structure the memory card300described with reference toFIG. 3A. Alternatively, the memory system410may be embodied as a solid state disk (SSD), as a camera image sensor or as another type of chipset. In the case in which the memory system410constitutes a solid-state disk, the information processing system400can stably and reliably store high-capacity data in the memory414.

According to an aspect of the inventive concept as described above, an etch byproduct remaining on a mask is removed to prevent a void or seam from being produced in an interlayer dielectric formed by a subsequent process. Furthermore, according to another aspect, the gate dielectric layer is hardly etched during the removal of the etch byproduct. Thus, a DRAM according to the inventive concept may have excellent refresh characteristics. In addition, the gate electrode is well insulated, i.e., the insulation has a high breakdown voltage.

Finally, embodiments of the inventive concept have been described above in detail. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments described above. Rather, these embodiments were described so that this disclosure is thorough and complete, and fully conveys the inventive concept to those skilled in the art. Thus, the true spirit and scope of the inventive concept is not limited by the embodiments described above but by the following claims.