Phase detector

A phase detection system for providing a phase signal indicative of a phase difference between first and second input signals, with the system including a pair of amplification channels for receiving the input signals, with each channel including a plurality of amplifier stages. The outputs of the two amplification channels are connected to the inputs of a multiplier arrangement, with the arrangement producing an uncompensated phase signal. Compensation circuitry is provided to receive a magnitude signal indicative of the relative magnitudes of the two input signals, with the magnitude signal being used to produce a corrected phase signal indicative of the phase difference between the two input signals.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to phase measurement circuitry and in particular to phase detection circuitry capable of accommodating signal inputs of widely varying amplitudes while maintaining relatively low power consumption.

2. Description of Related Art

Phase detection circuitry has a wide range of applications.FIG. 1shows two input sinusoidal signals IN1and IN2of the same frequency but differing in phase. The two signals IN1and IN2can be respectively expressed as A1*sin(ω0t+φ1) and A2*sin(ω0t+φ2), respectively. Assuming that IN2is leading IN1, the phase difference Δφ is defined as being equal to φ2−φ1.FIG. 2is a prior art circuit of a standard multiplier15sometimes referred to as a Gilbert multiplier. If the two signals IN1and IN2are relatively large in magnitude as compared to the thermal voltages VTof the transistors of theFIG. 2Gilbert multiplier, the input signals operate to completely turn ON or turn OFF the transistors. In that event, the multiplier15operates as a phase detector, with the differential output signal Out switching between +(IEE*RC) and −(IEE*RC) depending upon the phase relationship between the inputs.

The above is illustrated by reference to the timing diagram ofFIG. 3. When the two input signals IN1and IN2have relatively large magnitudes as compared to VT, the signals can be approximately represented as digital signals as shown inFIG. 3. Multiplier15can be considered to operate in a manner similar to an exclusive NOR circuit. If the inputs IN1and IN2differ, then signal Out is low, otherwise the output is high. As can be seen, signal IN2leads signal IN1in phase by a phase difference of Δφ as also shown inFIG. 1. During the period corresponding to Δφ when IN1is low and IN2is high, all of the IEEcurrent is flowing through one of the resistors RC to produce a minimum value of signal Out having an associated area A1. As also indicated, when both signals IN1and IN2are high during the remaining portion of the half cycle π, signal Out is at a maximum value and has an associated area A2.

Inspection of theFIG. 3plot indicates that the average value of signal Out for the range 0≦Δφ≦π is as follows:
Vavg=(A2−A1)/π

Taking into consideration of the actual voltages produced at the output of the multiplier, for this same range of 0≦Δφ≦π, the average voltage can also be expressed as follows:

The average value of signal Out for the range −π≦Δφ≦0 is as follows:
Vavg=(A2−A1)/π=VMULT[(π+Δφ)/π+(Δφ/π)]
or
Vavg=VMULT[1+(2Δφ)/π]  (2)

A low pass filter is used to obtain Vavg, the average multiplier output signal, with Vavgbeing a direct measure of the phase difference Δφ between IN1and IN2.

FIG. 4illustrates an ideal phase detector output signal22after low pass filtering. The reference point is for signal IN1having a phase φ1of 0° with the phase φ2of signal IN2varying from −175° to +175°. The detector output signal is at a maximum value22A of 621.6 mV when φ2is in phase with φ1and drops down in a linear fashion to about −0.59 at22B for −175° and at22C for +175°.

FIG. 5depicts a conventional phase detector for detecting a phase difference between sinusoidal inputs IN1and IN2. Two amplification channels A and B are provided, with each channel having N number of separate differential gain stages. The gain stages function to ensure that the input voltages to the multiplier M1are sufficiently large. The detector output is theoretically independent of any variations in the magnitudes of inputs IN1and IN2. A low pass filter F1is provided to provide the average multiplier output and to remove the ripple at 2× the input frequency. The typical prior art phase detector further includes amplitude mismatch circuitry24for measuring the magnitude ratio or gain between the two input signals IN1and IN2which has an application generally unrelated to carrying out the phase detection function.

Ideally, the two amplifier channels A and B introduce a small and but equal delay into each channel so that no phase errors are introduced. In order to minimize amplitude dispersion and a resulting phase error, the amplifier stages of each channel must have a very high bandwidth. In order to obtain a phase accuracy of around 1° to 2°, a gain stage bandwidth of 16× to 32× of the maximum input frequency is needed. However, such wide bandwidth requires a lot of power, a big drawback in mobile and other low power applications.

There is a need for an accurate phase detector which can be used in low power applications. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, the various disclosed embodiments are capable of providing this capability.

DETAILED DESCRIPTION OF THE INVENTION

In describing the various embodiments of the present invention, a further analysis of prior art phase detection circuitry is useful. A simulation analysis can be used to demonstrate various characteristics of an amplification channel such as the channel ofFIG. 5which includes stages A1through AN. One objective is to characterize the propagation delays and amplitude dispersion along an amplification channel under various operating conditions.

For purposes of simulation, it was assumed that the frequency ratio fratiois defined in terms of gain stage bandwidth and input frequency is as follows:
fratio=f3db—gainstage/fin(3)

In addition, each gain stage has one pole as a first order response. The response time τ (tau) values are normalized so that τ=1. Further, the voltage output Vout of the amplifier stage is as follows:
Vout=Iload*Rload*tanh(Vin/2VT)  (4)where Vin is the amplitude of the input; andVTis the transistor thermal voltage.

The propagation delay tdrc of the rising edge at the output of a gain stage “stage” is expressed as follows:
tdrc(stage,Vin)=td(stage,Vin,re)−td(Vin,re)where tdrc is the propagation delay;td( . . . ) is propagation delay in general;stage is the stage number;Vin is the input magnitude of the first stage; andre is the rising edge, the point at which delay is measured.

Ideally, the propagation delay for each gain stage is fixed so that the total delay through each of the amplification channels A and B having equal stages are fixed and equal. If that were the case, then the amplification channels would not introduce errors in the phase measurements. However, the propagation delay tdrc for a gain stage varies as a function of many variables including (1) the gain of the stage; (2) the bandwidth of the stage in comparison to the input frequency (the fratio); and the magnitude of the input Vin. In fact, it is anticipated that the relative magnitudes of inputs IN1and IN2to a phase detector can vary considerably.

The amplitude dispersion Δtdrc at the output of gain stage “stage” is expressed as follows:
Δtdrc(stage,Vin1,Vin2)=tdrc(stage,Vin1)−tdrc(stage,Vin2)  (5)

In addition, the propagation delay tdr of a rising edge for a specific gain stage “stage” is expressed as follows:
tdr(stage,Vin)=tdrc(stage,Vin)−tdrc(stage−1,Vin)  (6)

FIG. 6Ashows a family of curves illustrating the propagation delay tdr of each stage of a nine stage amplifier channel. Each of the five plots represents a differing magnitude input Vin including 1 mV, 3.16 mV, 10 mV, 31.62 mV and 100 mV. The gain of each stage illustrated inFIG. 6Ais fixed at a relatively low value of 3 and the frequency ratio fratio, which as previously noted relates to the bandwidth of the stage relative to the input frequency, is fixed at a relatively low value of 2. Plot26A2ofFIG. 6Ashows the propagation delays along the amplification channel for the smallest magnitude input (1 mV) and plot28A2shows the propagation delays for the largest magnitude input (100 mV.) The intermediate and undesignated plots ofFIG. 6Aare for 3.16 mV, 10 mV and 31.62 mV inputs.

As can be seen, at the output of the first stage, the normalized value of tdr for the largest magnitude (100 mV) input282A2starts out at 0.92 (out of one), drops down to about 0.85 at the second stage and then stabilizes at about 0.78 at the third stage and remains at that level for each of the remaining six stages. For the smallest magnitude input of 1 mV, plot26A2indicates that value of tdr starts at 0.92, starts to drop from that value at stage4, drops to 0.90 at stage6, drops further to 0.84 at stage7and does not stabilize at 0.77 until the last or ninth stage.

The plots ofFIGS. 6B and 6Care produced under similar circumstances asFIG. 6Aexcept the gain is increased to 5 inFIG. 6Band increased to 10 inFIG. 6C. The 100 mV input plot is designated as28B2and28C2in respectiveFIGS. 6B and 6Cand the 1 mV input plot is designated as26B2and26C2in respectiveFIGS. 6B and 6C. As can be seen in both figures, the value of tdr stabilizes much sooner for all values of inputs, with tdr settling at 0.73 at stage7for a gain of 5 and with tdr settling at 0.70 at stage6.

FIGS. 7A to 7Cshow the various values of Δtdrc, the amplitude dispersion for various ratios on inputs. Each figure depicts ten different plots for the ten input ratios of inputs as set forth in Table 1 below. The absolute values of tdrc are taken from the plots of respectiveFIGS. 6A to 6C. Thus, one plot ofFIG. 7Arepresents an input signal ratio Vin2/Vin1of 100 mV/10 mV. The respective tdr values of 100 mV and 10 mV are taken from the two corresponding plot ofFIG. 6Aand subtracted from one another to produce a corresponding Δtdrc curve.

When the two tdr plots each have reached a saturation level (tdrsaturated) at the final gain stage is approached, the difference between the propagation delays (Δtdrc) will reach some constant level as shown inFIG. 7Aand Table 1. By way of example, plot42A ofFIG. 7Arepresents a Δtdrc associated with an input ratio Vin2/Vin1of 100/1. At about the seventh gain stage, this Δtdrc value becomes constant at a normalized value of 0.71 out of one. (Note the Table 1 has a somewhat better resolution as compared to the plot ofFIGS. 7A to 7Cfor showing the final Δtdrc levels.) Thus, if a phase detector system having amplification channels A and B using amplifiers having a fratioof two and a gain of three and having respective inputs that have a magnitude ratio of 100/1, the difference in propagation delay in the two amplification channels will produce a phase difference measurement error that corresponds to a normalized Δtdrc value of 0.71. Two plots ofFIG. 7Adesignated by44A are for input magnitude ratios of 100/3.16 and 31.6/1 converge at a final stabilized value of Δtdrc of 0.52. Three plots46A are for input magnitude ratios of 100/10, 31.6/3.16 and 10/1 and converge at a final value of Δtdrc of 0.35. Finally, four plots48A for input magnitude ratios of 100/31.6, 31.6/10, 10/3.16 and 3.16/1 all converge as a final value of Δtdrc of 0.19. Thus, as the ratio of input magnitudes is reduced, the potential phase error measurement becomes smaller. Unfortunately, it usually not possible to control this ratio, so differing ratios must be taken into account.

FIG. 7Bshows the changes in Δtdrc that result when the gain is increased from three to five. As also shown in Table 1, the single plot designated by42B (100/1) stabilizes at a final value 0.61, the two plots designated by44B (100/3.16 and 31.6/1) stabilizes at 0.48, the three plots designated by46B (100/10, 31.6/3.16 and 10/1) stabilizes at 0.31 and finally the four plots designated by48B saturate at 0.17.

When the gain is increased from five to ten,FIG. 7Cshows the changes in Δtdrc that result. As also shown in Table 1, the single plot designated by42C (100/1) stabilizes at 0.49, the two plots designated by44C (100/3.16 and 31.6/1) stabilizes at 0.36, the three plots designated by46C (100/10, 31.6/3.16 and 10/1) saturate at 0.23 and finally the four plots designated by48C stabilizes at a final value of 0.11.

FIGS. 8A to 8Care similar to respectiveFIGS. 6A to 6Cexcept to value of fratiois increased from 2 to 4. Each of these figures includes five plots of tdr representing five differing input magnitudes including plots30A4,30B4and30C4associated with an input of 1 mV and including plots32A4,32B4and32C4associated with an input of 100 mV.

The plots ofFIGS. 9A to 9Care similar to those ofFIGS. 7A to 7Cexcept that the value of fratiois increased from 2 to 4. The data of theFIG. 9A to 9Cplots are derived from the plots ofFIG. 8A to 8C. The plots ofFIGS. 9A to 9Calong with Table 2 below show the characteristics of Δtdrc under these new conditions, including the differing stabilized final values. The single plot designated by50A, B, and C (input ratio 100/1) in each of the three figures stabilizes at the various levels best seen in Table 2, the two plots designated by52A, B and C (input ratios 100/3.16 and 31.6/1) in each of the three figures stabilize at the various levels best seen in Table 2. In addition, the three plots designated by54A, B and C (input ratios 100/10, 31.6/3.16 and 10/1) in each of the three figures stabilize at the various levels best seen in Table 2 and finally, the four plots designated as56A, B and C (input ratios 100/31.6, 31.6/10, 10/3.16 and 3.16/1) in each of the three figures stabilize at the various levels best seen in Table 2.

FIGS. 10A to 10Care similar to respectiveFIGS. 6A to 6Cexcept to value of fratiois increased from 2 to 8. Each of these figures includes five plots of tdr representing five differing input magnitudes, including plots34A8,34B8and34C8associated with an input of 1 mV and including plots36A8,36B8and36C8associated with an input of 100 mV.

FIGS. 11A to 11Care also similar to that ofFIGS. 7A to 7Cexcept that the value of fratiois increased from 2 to 8. The data for theFIG. 11A to 11Cplots is taken fromFIGS. 10A to 10C. The plots ofFIGS. 7A to 7Calong with Table 3 below show the characteristics of Δtdrc under these new conditions, including the differing final stabilized levels.

Continuing,FIGS. 12A to 12Care similar to respectiveFIGS. 6A to 6Cexcept to value of fratiois increased from 2 to 16. Once again, each of these figures includes five plots of tdr representing five differing input magnitudes including plots38A16,38B16and38C16associated with an input of 1 mV and including plots40A16,40B16and40C16associated with an input of 100 mV.

FIGS. 13A to 13Care also similar to that ofFIGS. 7A to 7Cexcept that the value of fratiois increased from 2 to 16. The data for plots13A to13C are taken from the tdr plots ofFIGS. 12A to 12C. The plots ofFIGS. 13A to 13Calong with Table 4 below show the characteristics of Δtdrc under these new conditions, including the differing final stabilized levels.

The plots ofFIGS. 6A-6CtoFIGS. 13A-13C, along with Tables 1-4 confirm that there is a logarithmic dependency of the amplitude dispersion Δtdrc (stage, Vin1, Vin2) on the amplitude ratio Vin2/Vin1. This is also illustrated byFIG. 14which is another version ofFIG. 7Awith annotations added. For a 10× increase in the amplitude ratio the amplitude dispersion essentially doubles. Using this fact in combination with the knowledge that a saturated gain stage will have a constant propagation delay (tdrsaturated), it is possible to correct the phase error resulting from amplitude dispersion as long as the amplitude ratio is known.

As previously noted in connection with the prior art phase detector ofFIG. 5, such phase detectors commonly provide circuitry for generating a signal relating to the ratio of the two inputs IN2and IN1. The actual computed ratio of the mismatch detector is logarithmic and is equal to β*Log10(Vin2/Vin1). In that case, a constant α can be found such that:
Δtdrc(stage,Vin1,Vin2)=α*β*Log10(Vin2/Vin1)*tdrsaturated(7)

The constant α or alfa can be determined given that the amplitude dispersion numbers and propagation delay numbers are known for differing values of fratioand stage gains. By way of example,FIG. 15A to 15Ceach show family of ten plots, one for each of the ten Vin2/Vin1magnitude ratios set forth, by way of example, in the left hand column of Table 1. The plots ofFIG. 15Awere made with the assumption that the gain of the amplification stages are each 3. (The drawing resolution is insufficient to show each of the separate plots.) The vertical axis ofFIG. 15Arepresents the various values of factor α or alfa and the horizontal axis is for various values of fratio. Thus, the 10 plots ofFIG. 15Aare derived fromFIGS. 6A,7A (G=3, fratto=2),FIGS. 8A,9A (G=3, fratio=4),FIGS. 10A,11A (G=3, fratio=8),FIGS. 12A,13A (G=3, fratio=16). As can be seen inFIG. 15A, the value of factor α remains fairly constant around 1.1 to 1.2 for a gain of 3 but drops significantly in the input frequency approaches the gain bandwidth where fratio=2.FIG. 15Bis ten plots for a gain of 5 and shows that the value of α is fairly constant around 1.0 to 1.05, again disregarding the low bandwidth condition. Finally,15C shows that the value of factor α is fairly constant around 0.79-0.86 for a gain of 10 assuming that the low bandwidth condition is disregarded.

The foregoing shows that factor α is relatively constant over a wide range of frequencies, but drops significantly if the input frequency approaches the gain stage bandwidth (fratio=1). This means that the phase error due to amplitude dispersion can be fairly well compensated as long as a measure of the amplitude ratio can be found and the delay of the saturated stage (tdrsaturated) can be found. Below are the equations for the uncorrected phase error (ΔPhaseuncorrected) and the corrected phase error (ΔPhasecorrected) which show the improvement in phase error.
ΔPhaseuncorrected=[Δtdrc(stage,Vin1,Vin2)]*(180)/(fratio*π)[°]  (8)where converting τ back to ° is carried out using ΔPhase=(180)Δt/(fratio*π)[°].
ΔPhasecorrected=[[Δtdrc(stage,Vin1,Vin2)]−[α*β*Log10(Vin2/Vin1)*tdrsaturated]]*180/(fratio*π)[°]  (9)where the polarity of Δtdrc depends on which of Vin1and Vin2is larger, since the sign of the “Log10(Vin/Vin)” term depends upon this relationship.

The differences in (ΔPhaseuncorrected) and ΔPhasecorrectedfor various values of gain and fratioare depicted inFIGS. 16A-16C,FIGS. 17A-17CandFIGS. 18A-18C. Each figure includes a vertical axis for the value of phase error and a horizontal axis for the values of fratioand depicts ten different plots for each of the ten different Vin2/Vin1ratios as set forth, by way of example, in the left hand column of Table 1. The resolution of the drawings is generally insufficient to show each of the ten plots, but it can be seen that the plots fall into four separate groupings based upon the Log10of the Vin2/Vin1ratios (2.0, 1.5, 1.0 and 0.5) as also shown in Table 1.

Referring toFIG. 16A, this shows the uncorrected phase error (ΔPhaseuncorrected) when the gain of the amplifier stages is only 3. Grouping74A3is for the largest input ratio (Log10ratio=2.0) for a single plot, grouping76A3is for the second largest input ratio (Log10ratio=1.5) and represents two different plots, grouping78A3is for the next larger input ratio (Log10ratio=1.0 and represents three different plots, with grouping80A3representing the remaining four plots (log10ratio=0.5) As expected, for relatively low bandwidth amplifier channels (fratio=2) and a wide difference in inputs Vin2and Vin1, grouping74A3ofFIG. 16Ashows that the uncorrected phase error is about 20°. That error is reduced to about 4° in the event the bandwidth is increased so that fratiois equal to 16. Such a bandwidth requires a large consumption of power. The groupings for lower ratio inputs,76A3,78A3and80A3, show a smaller phase error, but amplifiers with a wide bandwidth are still required to reduce the phase error to a relatively low value.

FIG. 16Bshows the corrected phase error after the phase is corrected in accordance with equation (9) above. Once again, four groupings are shown (74B3,76B3,78B3and80B3) for the ten differing input ratios. In this case, the factor α is set to 1.0. This results in a substantial reduction in the phase error measurement. The phase error measurement is almost eliminated as shown inFIG. 16Cif α is increased from 1.0 to 1.15. This is consistent withFIG. 15Awhich shows that a higher value of α is a better fit for a gain of 3 and where the values of fratiois greater than four.

FIGS. 17A and 18Ashow the uncorrected phase error when the gain is increased to 5 and to 10, respectively. The phase errors are only slightly improved over that ofFIG. 16A.FIGS. 17B and 17Cshow the corrected phase errors for a gain of 5 where α is 0.92 and 1.05, respectively.FIGS. 18B and 18Care each for a gain of 10 where only the maximum input ratio Vin2/Vin1is depicted (74B10of FIGS.18B and74C10ofFIG. 18C). It can be seen fromFIG. 18B, where the α value is 0.75 that the phase error is fairly good even for a minimum value of fratio=2.FIG. 18Cshows a very accurate phase measurement using an a value of 0.82 if the minimum value of fratiois 4.

Although there is still a tradeoff between power and accuracy, it can be seen that good accuracy can be achieved at relatively low power consumption. Recalling that fratio=f3dB—ganistage/fin, an amplifier stage bandwidth of only 2× to 4× of the input frequency is sufficient to achieve good phase accuracy. This is compared to the standard prior art phase detector where 16× to 32× is usually required.

As indicated by equation (9), two items of information are needed to provide this level of accuracy. First, the value of “Log10(Vin2/Vin1)” needs to be determined since this is a major unknown and cannot be controlled. Second, the value of “tdrsaturated” needs to be ascertained. As previously described, the “Log10[Vin2/Vin1]” term is typically already generated by other circuitry as shown by circuitry24ofFIG. 5. Further, the value of tdrsaturatedcan be extracted from the amplifier channels by deliberating adding a delay in one of the channel before multiplying as will be described.

FIG. 19depicts one embodiment 82 of the present invention. A first amplification channel is provided which includes gain stages A1to AN followed by a delay stage AN+1 that introduces a phase shift Δφ1. A second amplification channel is provided which includes gain stages B1to BN followed by a delay stage BN+1 that introduces a phase shift Δφ2. A multiplication stage M1functions to multiply the output of stage AN+1 with the output of stage BN. Another multiplication stage M2functions to multiply the output of stage BN+1 with the output of stage AN. The phase shift introduced by stage AN+1 is defined as follows:
Δφ1=[tdr(AN+1,IN1)/fratio][rad]  (10)

The phase shift introduced by stage BN+1 is defined as follows:
Δφ2=[tdr(BN+1,IN2)/fratio][rad]  (11)

FIGS. 20A and 20Bare timing diagrams which relate to detector operation where input signal IN2is leading input signal IN1, so that by definition the phase difference Δφ between inputs (φ2−φ1) is positive: 0≦Δφ≦π.FIG. 20Arelates to those signals associated with multiplier M1. The actual phase difference between inputs input signal IN1and input signal IN2is Δφ. The phase shift introduced by amplifier stage AN+1 is Δφ1with this shift being introduced in the signal path of input IN1M1as indicated by the top waveform ofFIG. 20A. In this case, the two phase shifts Δφ and Δφ1add together to increase the apparent phase difference between inputs IN1and IN2as seen by multiplier M1. This is reflected by the output of multiplier M1, which is waveform OUTM1. When the two signals at the inputs to the multiplier M1are different, the output is low, with the output being high in all other cases. Thus when both inputs are high, OUTM1is high for a duration that corresponds to area A2. When the inputs are different, OUTM1is low for a duration that corresponds to area A1. As shown inFIG. 19, OUTM1is passed through low pass filter F1to produce an average value of A2and A1referred to as Vavg—M1.

As can be seen by inspection of signal OUTM1ofFIG. 20A, the average output of multiplier M1after filtering is as follows:
Vavg—M1=(A2−A1)/π
or
Vavg—M1=VMULT[(π−(Δφ+Δφ1))/π−(Δφ+Δφ1)/π]
or
Vavg—M1=VMULT[1−2(Δφ+Δφ1)/π]  (12)

As previously noted, the timing diagram ofFIG. 20Bis also for positive values of Δφ and relates to those signals associated with multiplier M2. The actual phase difference between inputs input signal IN1and input signal IN2remains Δφ. The phase shift introduced by amplifier stage BN+1 is Δφ2with this shift being introduced in the signal path of input IN2M2. Since the phase shift Δφ2is introduced in the opposite amplification channel as compared to shift Δφ1, shift Δφ2subtracts from the actual phase shift Δφ so as to decrease the apparent phase shift seen by multiplier M2. This is reflected by the output of multiplier M2, which is waveform OUTM2. Once again, when both multiplier inputs are high, OUTM2is high for a duration that corresponds to area A2. When the inputs are different, OUTM2is low for a duration that corresponds to area A1. As shown inFIG. 19, OUTM2is passed through low pass filter F2to produce an average value of A2and A1referred to as Vavg—M2.

As can be seen by inspection of signal OUTM2ofFIG. 20B, the average output of multiplier M2after filtering is as follows:
Vavg—M2=(A2−A1)/π
or
Vavg—M2=VMULT[(π−(Δφ−Δφ2))/π−(Δφ−Δφ2)/π]
or
Vavg—M2=VMULT[1−2(Δφ−Δφ2)/π]  (13)

As can be seen inFIG. 19, an adder A1is provided for adding the filtered output of multiplier M1and the filtered output of multiplier M2. The sum is as follows:
Vavg=2VMULT[(1−(2Δφ)/π)−(Δφ1−Δφ2)/π]  (14)

The above value of Vavgalone would provide a fairly accurate measurement of Δφ but only if the inputs IN1and IN2are of similar magnitude so as they have the same propagation delay through the two amplification channels. However, the relative magnitudes of IN1and IN2will vary substantially which, as previously established, results in widely varying propagation delays through the two channels. A further term Vsat is computed to address this problem. The filtered output of multiplier M1is added by adder A2to the filtered and inverted output of multiplier M2to produce the following:
Vsat=−2VMULT[(Δφ1+Δφ2)/π]  (15)

As will be seen, VSATof equation (15) is used with other terms to provide a correction factor to be combined with Vavg to produce a corrected phase measurement.

The above analysis is for 0≦Δφ≦π. A similar analysis of the phase detector ofFIG. 19is carried out when −π≦Δφ≦0 as shown in the waveforms ofFIGS. 21A and 21B. Referring to the timing diagram ofFIG. 21A, this diagram relates to the signals associated with multiplier M1. The actual phase difference between IN1and IN2at the input of the respective amplifier channels is −Δφ where IN1M1is leading IN2M1. Once again, amplification stage AN+1 introduces a phase delay Δφ1in the channel for IN1M1. As can be seen by inspection of the three waveforms IN1M1, IN2M1and OUTM1ofFIG. 21A, the average output of multiplier M1(FIG. 19) after filtering is as follows:
Vavg—M1=(A2−A1)/π
or
Vavg—M1=VMULT[(π−(−Δφ−Δφ1))/π−(−Δφ−Δφ1)/π]
or
Vavg—M1=VMULT[1+2(Δφ+Δφ1)/π]  (16)

Referring to the timing diagram ofFIG. 21B, this diagram relates to the signals associated with multiplier M2when −π≦Δφ≦0. In this case the actual phase difference between IN1and IN2at the input of the respective amplifier channels is −Δφ where IN1M2is leading IN2M2. Once again, amplification stage BN+1 introduces a phase delay Δφ2in the channel for IN2M2. As can be seen by inspection of waveforms IN1M2, IN2M2and OUTM2ofFIG. 21B, the average output of multiplier M2(FIG. 19) after filtering is as follows:
Vavg—M2=(A2−A1)/π
or
Vavg—M2=VMULT[(π−(−Δφ+Δφ2))/π−(−Δφ+Δφ2)π]
or
Vavg—M2=VMULT[1+2(Δφ−Δφ2)/π]  (17)

Referring again toFIG. 19and as previously noted, adder A1is provided for adding the filtered output of multiplier M1and the filtered output of multiplier M2. In this case, to sum is as follows:
Vavg=2VMULT[(1+2Δφ/π)+(Δφ1−Δφ2)/π]  (18)

As previously described, the filtered output of multiplier M1is added to the filtered and inverted output of M2to produce Vsat. Note that Vsatis negative for positive values of Δφ and positive for negative values of Δφ. Thus, Vsatis the same as the previous case described in connection withFIGS. 20A and 20Bbut opposite in sign:
Vsat=2VMULT[(Δφ1+Δφ2)/π]  (19)

As previously noted, Vphaseis equal to Vavg, with a correction factor added as follows:
Vphase=Vavg−α*β*Log10[Vin2/Vin1]*Vsat(20)

It can be assumed that Δφ1=Δφ2=ΔφSwhere ΔφSis the phase shift attributable to tdrsaturated. In that case, ΔφScan be defined as follows:
ΔφS=180*(tdrsaturated)/(π*fratio)[°]  (21)

Substituting the values of Vavgof equation (14) and Vsatof equation (15) into equation (20) for Vphase, the following results for the case where 0≦Δφ≦π:

A similar substitution of Vavgof equation (18) and Vsatof equation (19) into equation (20) for the case where −π≦Δφ≦0 results in the following:
Vphase=2VMULT[(1+2Δφ/π)−α*β*Log10(Vin2/Vin1)*(2ΔφS)/π]  (24)

FIG. 22shows a phase detector output characteristic similar to that shown inFIG. 4. The transfer characteristics are shown for Vavgwhich has the shape of an inverted “V”. The horizontal axis is the phase difference Δφ in radians and the vertical axis is the corrected phase detector output voltage Vphaseis expressed in volts per radian. When the phase difference Δφ is zero, Vphaseis ideally at the maximum value of 2VMULT. Further, when the phase difference Δφ is ±90° or π/2, the value of Vphaseshould ideally be 0 volts.

FIG. 22shows four separate examples of phase error correction. In two of the examples, Δφ is positive meaning that IN2is leading IN1(Δφ=φ2−φ1). In one of those two examples, the amplitude dispersion Δtdr is such that the uncorrected value of Δφ is larger than it should be as indicated by node120A. The actual value of Δφ should be π/2 in this example. The value of Δφ is too large due to the fact that Vin2is larger than Vin1, with signal IN2thus propagating through the amplifier channel more rapidly than signal IN1. In the case of the second example, Δφ is still positive but now Vin1is much larger than Vin2. Thus, signal IN1will propagate more rapidly so that the positive value of Δφ is smaller than it should be as indicated by node120B. Once again, the actual value of Δφ should be π/2 in this second example.

In the case of the other two examples ofFIG. 22, the value of Δφ is negative. In both of these examples, the actual value of Δφ should be −π/2. In one case the ratio of Vin2/Vin1is relatively small so that the uncorrected value of Δφ is low as indicated, by way of example, node120C. In the other case, the ratio of Vin2/Vin1is relatively large so that the uncorrected value of Δφ is high as indicated, by way of example, by node120D.

FIG. 22further depicts the manner in which each of these four examples is corrected. The correction factor for adjusting the uncorrected value of Vphaseis α*β*log10[Vin2/Vin1]*Vsatas previously discussed in connection with equation (20). Addressing the example noted above regarding node120B ofFIG. 22and assuming that Vin2/Vin1is 0.01, α is 1.0 and β is 0.5, the correction factor is −1*VSAT. Taking into account that Vsatis negative for a positive Δφ and that the correction value is subtracted from the uncorrected value of Vphase, Vphaseis moved from node120B to node124A, which corresponds to the correct value of Δφ, namely π/2. If the ratio is reversed as in the case of the example associated with node120A where Vin2/Vin1is 100, the log value changes sign so that the correction factor is +1*VSAT. Thus, Vphasemoves from node120A to124A. The same analysis applies to the examples associated with nodes120C and120D.

A simplified block diagram for implementing equation (24) so as to produce output Vphaseis shown inFIG. 23A. The basic circuit blocks shown inFIG. 23Aare all conventional. As previously described, signal Vavgrepresents the uncompensated phase measurement in accordance with equation (18) while using Δφ1=Δφ2=Δφs, and is produced by adder A1ofFIG. 19. As can be seen inFIG. 23A, Vavgis coupled to one input of a subtractor circuit98.

A correction voltage Vcoris applied to the other input of the subtractor circuit98. Vcoris produced, as indicated by equation (20) using the terms α, β, log10[Vin2/Vin1] and Vsat. The value Vsatis produced by adder circuit A2ofFIG. 19. As previously described, the α term typically has a value near 1.0, but can be adjusted depending upon various factors, including stage gain, as explained in the previous discussion relating toFIGS. 15A to 15C. Vsatand α are multiplied together using a multiplier100to produce an intermediate term. As also previously discussed, the Log10[Vin2/Vin1] term is produced using a prior art circuit similar to circuit24ofFIG. 5. The log term along with the β term, typically 0.5, are applied to the respective inputs of a second multiplier102to produce another intermediate term. The two intermediate terms from multipliers100and102are applied to the respective inputs of a third multiplier circuit104to produce value Vcor. Finally, Vcor is subtracted from Vavgby subtractor circuit98to produce output Vphase.

FIG. 23Bshows the manner in which the Vphase output of subtractor98is converted to a corresponding phase difference Δφ=φ2−φ1. One exemplary Vphase output is shown inFIG. 22. The peak value (node116) of Vphaseis 2Vmultwhich is ideally at a phase difference Δφ of zero degrees. A Vphasevalue of 0 mV ideally indicates a phase difference of either +90° (node124A) or −90° (node124B). To convert a Vphase value to a phase angle Δφ, inspection ofFIG. 22shows the following two linear equations:
Vphase=−(2Vmult/90°)*Δφ+2Vmult(25)
for 0≦Δφ≦π,
and
Vphase=+(2Vmult/90°)*Δφ+2Vmult(26)
for −π≦Δφ≦0.

The value Vphaseis divided by 2*Vmult as indicated by divider106. An angle of 90° is then subtracted from the division step to produce Δφ as indicated by subtractor block108. Finally, Vsatcontrols the sign of Δφ as indicated by sign block110. Sign block110has an output of 1 when the input is above a given threshold and an output of −1 when the input is below the threshold, with the threshold being zero in this case. Note that Vsatinherently provides lead/lag information, thus enabling four quadrant phase detection.

Simulation indicates that the first embodiment phase detector ofFIG. 19,FIGS. 23A and 23B, sometimes referred to herein as “Type 1” provides substantially improved performance. This is particularly true when the amplification stages are implemented with relatively low bandwidth circuitry (fratio°=2).FIGS. 24A-24Dshow the relative performance to the Type 1 circuit assuming a value of α=0.9, a gain G=6, a value of β=0.5 and a relatively high bandwidth (fratio=12) for each of ten input ratios as set forth on the left hand side of Table 1.FIGS. 24A and 24Bshow the relatively similar high performance for the Vphase figure, but theFIGS. 24C and 24Dphase error values show that ΔPhase is considerably improved.FIG. 24Cindicates that for small input ratios (3.16/1, etc.) close to unity indicate by plot81A/81B, for example, the errors may be on the order of ±1° but with the larger ratios (100/1) as indicated by plot83A/83B, the errors can be around ±3°. As can be seen fromFIG. 24D, the Type 1 circuit reduces the phase error value ΔPhase to around ±0.5° for all input ratios.

FIGS. 24E-24Hare for an fratio=4 an indicate that the improvement is even more pronounced for the Type 1 detector.FIG. 24Gshows that for even relatively small input ratios of 3.16 represented by plots84A/84B, the phase error value ΔPhase to around ±3°. For the largest input ratios of 100 indicated by plots85A/85B, the phase error value ΔPhase to around ±10°.FIG. 24Hshows that the phase error value ΔPhase is corrected for all of the input magnitude ratios to around ±2°.

When the value of fratiois reduced to only 2, as expected, the uncorrected phase error value ΔPhase increases substantially. In the example ofFIG. 24K, the ΔPhase value is increased to around ±15° for high input ratios as indicated by plots89A/89B and to around ±5° for the lower input ratios as indicated by plots87A/87B. However, even for this low fratio,FIG. 24Lshows reasonably good phase error values for all of the input magnitude ratios.

FIGS. 25A to 25Cshow the corrected phase angle φ measurements such as produced at the output of multiplier112ofFIG. 23Bfor respective values of fratio=2, 4 and 12 for all ten input magnitude ratios.

A second embodiment of the present invention, referred to as “Type 2”, is shown inFIG. 26. This embodiment is the same as that ofFIG. 19except for the presence of choppers C1and C2which are controlled by a clock signal CLK. When CLK is in a first (H) state, chopper C1connects input IN1to the input of amplifier stage A1and connects input IN2to the input of amplifier stage B1. In addition, the first state of CLK causes chopper C2to connect the output of multiplier M1to filter F1and the output of multiplier M2to filter F2. This is identical to the arrangement ofFIG. 19. When CLK changes state (L), chopper C1reverses the connections of IN1and IN2and chopper C2reverses the connections of the outputs of multipliers M1and M2. The bandwidth of low pass filters should be sufficiently lower than the chopping frequency (CLK) to reduce the ripple. The chopping frequency itself is lower than the input frequency and can be selected over a very wide range.

The equations previously provided in connection with theFIG. 19embodiment apply equally to the embodiment ofFIG. 26. The advantage of providing choppers C1and C2is the cancellation of multiplier M1and M2offsets and equalization of channel gains.

FIG. 27Ashows a still further embodiment of the present invention referred to as “Type 3”. In this case, only a single multiplier M1is used. In addition, only one of the two amplifier channels includes an extra stage AN+1 to provide an additional phase shift ΔφS. Once again, a chopper C1is provided which switches the inputs IN1and IN2between the two first amplifier stages A1and B1. The output of multiplier is connected to filter F1that produces Vavg. In addition, a second chopper C2selectively connects the true output of multiplier M1or the inverted output of the multiplier to filter F2to produce Vsat.FIG. 27Bshows the state of choppers C1and C2when CLK is in a first state (H) andFIG. 27Cshows the state of choppers C1and C2when CLK is in a second state (L).

FIGS. 28A and 28Bare timing diagrams illustrating the operation of theFIG. 27Aembodiment when 0≦Δφ≦π where input IN2leads input IN1by Δφ. TheFIG. 28Adiagram applies when CLK is in the first state (H) shown inFIG. 27B. Input IN2leads IN1by Δφ. In this case, due to the switch of input signals caused by chopper C1, the phase shift Δφsis applied to input IN1so that the apparent phase difference between the two inputs is increased. Inspection ofFIG. 28Aindicates the following:
Vavg—M1(H)=(A2−A1)/π
or
Vavg—M1(H)=VMULT[(π−(Δφ+ΔφS))/π−(Δφ+ΔφS)/π]
or
Vavg—M1(H)=VMULT[1−2(Δφ+ΔφS)/π]  (27)

TheFIG. 28Bdiagram applies when CLK is in the second state (L) shown inFIG. 27C. Input IN2again leads IN1by Δφ. In this case, due to the switch of input signals caused by chopper C1, the phase shift ΔφSis applied to input IN2so that the apparent phase difference between the two inputs is reduced. Inspection ofFIG. 28Bindicates the following:
Vavg—M1(L)=(A2−A1)/π
or
Vavg—M1(L)=VMULT[(π−(Δφ−ΔφS))/π−(Δπ−ΔφS)/π]
or
Vavg—M1(L)=VMULT[1−2(Δφ−ΔφS)/π]  (28)

Vavgis produced at the output of filter F1, with filter F1averaging the output when CLK is in the first state (H) and in the second state (L) and can be expressed as follows:
Vavg=[Vavg—M1(H)+Vavg—M1(L)]/2

From equations (27) and (28), the value of Vavgis as follows:
Vavg=VMULT[1−2Δφ/π]  (29)

Vsatis produced at the output of filter F2, with filter F2averaging the output when CLK is in the first state (H) and the inverse output when CLK is in the second state (L). Thus, Vsatcan be expresses as follows:
Vsat=[Vavg—M1(H)−Vavg—M1(L)]/2

From equations (27) and (28), the value of Vsatis as follows:
Vsat=−VMULT[2ΔφS/π]  (30)

Equations (29) and (30) can be used to combine Vavgand Vsatto produce Vphase and Δφ when 0≦Δφ≦π. The circuitry ofFIGS. 23A and 23Bcan be used for this purpose.

The timing diagrams ofFIGS. 29A and 29Billustrate the operation of theFIG. 27Aembodiment when −π≦Δφ≦0.FIG. 29Ais directed to theFIG. 27Aembodiment when signal CLK is in the first state (H). In that case, the phase delay ΔφSintroduced by stage AN+1 operates to delay input IN1M1H. Inspection of the input waveforms IN1M1Hand IN2M1Hand the output waveform OUTM1Hshows the following:
Vavg—M1(H)=(A2−A1)/π
or
Vavg—M1(H)=VMULT[(π−(−Δφ−ΔφS))/π−(−Δφ−ΔφS)/π]
or
Vavg—M1(H)=VMULT[1+2(Δφ+ΔφS)/π]  (31)

FIG. 29Bis directed to theFIG. 27Aembodiment when signal CLK is in the second state (L). In that case, the phase delay ΔφSintroduced by stage AN+1 operates to delay input IN2M1L. Inspection of the input waveforms IN1M1Land IN2M1Land the output waveform OUTM1Lshows the following:
Vavg—M1(L)=(A2−A1)/π
or
Vavg—M1(L)=VMULT[(π−(−Δφ+ΔφS))/π−(−Δφ+ΔφS)/π]
or
Vavg—M1(L)=VMULT[1+2(Δφ−ΔφS)/π]  (32)

As previously stated, Vavgis produced at the output of filter F1, with filter F1averaging the output when CLK is in the first state (H) and in the second state (L). For −π≦Δφ≦0, Vavgcan be expressed as follows:
Vavg=[Vavg—M1(H)+Vavg—M1(L)]/2

From equations (31) and (32), the value of Vavgis as follows:
Vavg=VMULT[1+2Δφ/π]  (33)

As also previously stated, Vsatis produced at the output of filter F2, with filter F2averaging the output when CLK is in the first state (H) and the inverse output when CLK is in the second state (L). Thus, Vsatcan be expresses as follows:
Vsat=[Vavg—M1(H)−Vavg—M1(L)]/2

From equations (31) and (32), the value of Vsatis as follows:
Vsat=VMULT[2ΔφS/π]  (34)

The previously described circuitry ofFIGS. 23A and 23Bcan then be used to convert Vavgand Vsatto Vphaseand Phase Δφ.

A fourth embodiment, referred to as “Type 4”, is depicted inFIGS. 30A-30C. This embodiment is similar to the Type 3 embodiment ofFIG. 27Aexcept chopper C1is moved from the inputs of the amplifier channels to the inputs of multiplier M1. Since stage AN+1 ofFIG. 27Ais no longer switched, it is necessary to use two delay stages AN+1 and BN+1 with each providing a respective phase delay Δφ1=Δφ2=ΔφS. The equations illustrating operation of theFIG. 30Aembodiment are the same as those previously described in connection with theFIG. 27Aembodiment.

As can be seen in the phase plots ofFIGS. 25A,25B and25C, phase detection accuracy is reduced around 0° and is also a problem around ±180°. A further embodiment of the present invention, referred to as “Type 5” is adapted to address these sources of measurement inaccuracy and is depicted inFIG. 31. The circuitry is similar to that of the Type 1 embodiment ofFIG. 19except for the presence of switchable variable delay stages, including stage ADin amplifier channel A and stage BDin amplifier channel B. Each stage ADand BDcan comprise more than one delay (gain) stage. As will be explained, the delay of one of the two stages ADand BDis selectively modified by associated respective complementary single bit control signals CNTR_ADand CNTR_BDso as to introduce a known delay shift in one of the two amplification channels. This delay translates into a phase shift which is added to one channel or the other so that the multipliers M1and M2are only required to provide a phase measurement in those regions where measurement accuracy it optimal. For a typical multiplier operating at fratio=4, optimal accuracy is achieved for the following two ranges for the phase angle difference at the inputs to the multipliers (ΔφM): −150°≦ΔφM≦−30° and +30°≦ΔφM≦+150°. Thus, stages ADand BDare controlled to ensure that the multiplier operation remains in these two ranges, with operation for a phase difference near 0°, +180° and −180° being avoided.

The phase shift ΔφADintroduced by stage ADis as follows:
ΔφAD=γ(1+CNTR—AD)*(tdr(AD,IN1))/fratio[rad]  (35)where γ is the number of delay stages to be switched, CNTR_ADis the associated control signal and is either a 1 or a 0.

The phase shift ΔφBDintroduced by stage BDis as follows:
ΔφBD=γ(1+CNTR—BD)*(tdr(BD,IN2))/fratio[rad]  (36)where CNTR_BDis the associated control signal and is the complement of CNTR_AD.

As will be described, during operation one or the other delay stages ADor BDis rendered operational so as to provide a specified delay. In the present example, each delay stage (comprising one or more gain stages), when activated, provides an increase phase shift of π/6 or 30°. In order to compensate for the added phase shift when calculating Vphase, the value γ*VSATis either added or subtracted in the calculation.

Each delay stage includes a single stage which is always operational and an additional γ number of individual delay stages which are either in-circuit or bypassed. Assuming that each individual stage provides a delay of about 0.7τ, the phase shift produced by each stage, assuming saturated operation (since the stages are located near the end of each channel) is as follows:

For a 30° phase shift γ should be 3 such that the phase shift in each channel can be increased by 30° so that the total phase shift when switching from one channel to the other is 60°. The manner in which the states of delay stages AD and BD are controlled using signals CNTR_ADand CNTR_BDwill be subsequently described in connection withFIGS. 33A and 33B.

The equations previously set forth describing Type 1 (FIG. 19) detector operation can be readily adapted to take into account the additional delay provided by either stage ADor BD. Modifying equation (23) for Vphase, the new value of Vphase for 0≦φ≦π is as follows:

Similarly, modifying equation (24) for Vphase, the new value of Vphase for −π≦φ≦0 is as follows:

The values for Vsat, as is reflected in the last portion of the two expressions of Vphase set forth above, are not changed from the Type 1 embodiment. Those values of Vsatare as follows:
for 0≦φ≦π,
Vsat=−2VMULT[(Δφ1+Δφ2)/π]  (39)
and for −π≦φ≦0,
Vsat=2VMULT[(Δφ1+Δφ2)/π]  (40)

The circuitry ofFIG. 32is used to convert the various factors previously discussed to produce Vphase. One input to the subtractor circuit126receives the Vavgterm of the Vphaseequation and the other input receives the correction term Vcor. The single bit CNTR_ADand single bit CNTR_BDterms are combined by a subtractor circuit so that the output is a +1 if delay CNTR_ADis active and a −1 if CNTR_BDis active. The γ term and the Vsatterms are multiplied together by circuit130with the sign of the product being controlled by the output of circuit128and multiplier132. Vsatis also multiplied by the α term by circuit134, with the Log10(VIN2/VIN1) and β terms being multiplied together by circuit136. The two products are then multiplied together by circuit138and then added with the output of multiplier132by adder circuit140to produce the correction term Vcor. Finally, Vcoris subtracted from Vavgto produce output Vphaseby subtractor circuit126. The phase can be calculated using the previously described circuitry ofFIG. 23B.

The manner in which the two delay stages ADand BDare controlled is perhaps best illustrated graphically.FIG. 33Ashows an ideal phase detector output86A/86B plotted on a graph having a vertical axis for Vphasein units of volts/division and a horizontal axis in Aphasein units of radians per division. By way of example, when Vphaseis at the maximum value of 2VMULTthe value of Δphaseis 0 radians. When Vphaseis zero, Δphaseis ±π/2 radians and when Vphaseis at a minimum value Aphaseis ±π radians. As previously noted, an actual conventional phase detector has reduced accuracy near 0 radians and near ±π radians. In accordance with one embodiment of the present invention, a controlled phase delay is introduced in either the A or the B amplifier channel. When delay stage ADis in an active state (delay stage BDwill be inactive), a delay ΔφADis introduced into channel A, with the resultant phase detector output being represented by plot88A/88B. When delay stage BDis in an active state (delay stage ADwill be inactive), a delay ΔφBDis introduced into channel B, with the resultant phase detector output being represented by plot90A/90B. As will be seen, the two delay stages are controlled so that phase detector operation never occurs near the reduced accuracy regions near 0 radians and or near ±π radians. Thus, should the actual inputs to multipliers M1or M2approach one of the three regions associated with measurement inaccuracy, this condition is sensed and the presently active delay stage is made inactive and the presently inactive stage is made active. The phase shift introduced by this action is such that the inputs to the multipliers M1or M2will no longer be operating in an inappropriate region. Compensation circuitry following the multipliers will compensate for the introduced phase shift.

In a first example, phase detector operation will be described for Δφ transitioning from −π to +π as depicted inFIG. 33A. Next, operation will be described for Δφ transitioning in the opposite direction from −π to −π as depicted inFIG. 33B. It is necessary to provide initial conditions so that the point of operation on the two Vphase plots88A/88B and90A/90B can be determined. As will be seen, the phase detector switches activation of the delay stages ADand BDwhen Vphase is at one of two threshold voltages VswitchPLUS(142A ofFIG. 33A) and VswitchMINUS(142B ofFIG. 33A). These values are selected so that the multiplier circuits M1and M2only operate, in the present example, in the range of −150°≦Δφ≦−30° and +30°≦Δφ≦+150°.

Referring toFIG. 33A, a Δφ transition from −π to +π will now be described. Assuming delay stage ADis active and that Δφ is at −π (−180°), then Vphaseplot88A/88B is relevant to operation. Since plot88A/88B is offset by +π/6 (+30°), the multipliers actually see a Δφ that is −5π/6 (−150°) rather than −π (−180°). Thus, the multipliers are operating in the desired high accuracy region rather than the low accuracy region of −π (−180°). The compensation circuitry ofFIG. 32disposed after the multipliers converts the +π/6 (+30°) measurement back to the correct value of −π (−180°). As Δφ transitions towards +π, the Vphasevalue moves along plot88B in the direction indicated by arrow144A. As Δφ approaches −π/3 (−60°), the phase detector multiplier actually sees an angle approaching −π/6 (−30°). This is another region of multiplier operation to be avoided as previously noted since it includes the near 0° measurements. However, at this point, the value of Vphase on plot88B will have increased to threshold voltage VswitchPLUSas indicated by point146A at level142A. The detection of this event will cause the delay stage ADto become inactive and delay stage BDto become active. This creates a total phase shift of −π/3 (−60°) which again will be compensated for by the circuitry ofFIG. 32. Now Vphase plot90A/90B is the relevant plot, with the actual multiplier now operating in a region removed from the ±30° region to be avoided. This shift is indicated by arrow144B.

As Δφ transitions closer to +π, the movement is along plot90B as indicated by arrow144C. Eventually, Δφ will approach the region of the Vphase plot90B where actual multiplier input is at −π/6 (−30°), a region to be avoided. At this point on plot90B, the threshold voltage VswitchPLUS (line142A at point146B) is again reached thereby causing delay stage BDto become inactive and delay stage ADto become active again. A transition from Vphase plot90B Vphase plot88A then Occurs.

As Δφ continues to transition closer to +π, the corresponding Vphase movement is along plot88A as indicated by arrow144D. Eventually, the value of Δφ actually applied to the multiplier inputs will approach 5π/6 (150°) which is another region of operation to be avoided. When the Vphase reaches 5π/6 (150°), the lower threshold voltage VswitchMINUSat level142B is also reached. This event at point146C will cause delay stage ADto switch to the inactive state and delay stage BDto become active again. As indicated by arrow144E, phase plot90A replaces phase plot88A. A further movement of Δφ towards it is indicated by arrow144F. When Δφ reaches +π, the actual phase angle at the input to the multipliers is only 5π/6 (150°) so that accurate operation is achieved.

The reverse sequence for Δφ shifting from +π to −π is illustrated inFIG. 33B. The transition sequence is similar to that for −π to +π ofFIG. 33Ain that there are a total of three changes in delay stage operation, but the changes are at different locations. Starting near +π and assuming that delay BDis active, operation is on the phase plot90A. Once again, accurate operation is achieved since the inputs to the multipliers are actually at 5π/6 (150°). As Δφ transitions towards −π, movement is along plot90A as indicated by arrow144G. Once Vphase reaches threshold142A at point146E (VswitchPLUS) where the actual input to the multipliers is approaching +π/6 (+30°). When the threshold is reached, delay stage ADbecomes active and there is a transition to plot88A as indicated by arrow144H. As Δφ moves up plot88A as indicated by arrow144I, Vphase eventually again reaches threshold142A. At this point (146B) delay stage BDbecomes active. As Δφ moves along plot90B as indicated by arrow144J, the lower threshold142B VswitchMINUSwill eventually be reached at point146F. At this point delay stage ADbecomes active and Vphase transitions to plot88B as indicated by arrow144K. Δφ moves along plot88B as indicated by arrow144L until the actual multiplier inputs are at −5π/6 (−150°) which produces an output of −π(−180°) after compensation.

The values of thresholds VswitchPLUSand VswitchMINUSfor switching between delay stages ADand BDshould be at the appropriate values of Vphase. The maxim value of Vphase is +2VMULT, with the threshold voltage VswitchPLUSbeing the maximum value less ΔV. The minimum value of Vphase is −2VMULT, with the threshold voltage VswitchMINUSbeing the minimum value plus ΔV. By inspection ofFIG. 33Ait can be seen that ΔV is as follows:
ΔV=2VMULT*abs[2(ΔφAD−ΔφBD)/π]  (41)

Thus, VswitchPLUSis as follows:
VswitchPLUS=2VMULT−2VMULT*abs[2(ΔφAD−ΔφBD)/π]
or
VswitchPLUS=2VMULT−2VMULT*γ*[abs(CNTR—AD−CNTR—BD)*(2ΔφS)/π]  (42)whereγ is the number of stages for each delay stage;CNTR_ADand CNTR_BDare respective control bits for delay stages ADand BD; and
2ΔφS=ΔφAD−ΔφBD.Thus,
VswitchPLUS=2*VMULT−γ*abs(Vsat)  (43)

A similar analysis shows the following:
VswitchMINUS=−2*VMULTγ*abs(Vsat)  (44)

As can be seen from equations (43) and (44), the switching levels VswitchPLUSand VswitchMINUSare dependent on fratioand can be set using Vsat. Also, the switching points around 0π(point146B) and around +π (point146D) should be provided with a small amount of hysteresis to prevent any switching between modes due to noise. The other switching points146A,146C,146E and146F can be shifted the same amount to simplify implementation.

One advantage of the above-described approach for controlling the states of delay stages ADand BDis that the phase measurements are continuous. Another approach for controlling the states of delay stages can be used but continuous measurements are not made. That approach is to make a pair of measurement, one with a different one of delay stages ADand BDbeing active. The measurement with the lowest absolute Vavgvalue will be the most accurate, so that the other measurement can be discarded. The lowest absolute Vavgwill always be outside the undesired region, as long as the implemented phased shift is sufficiently large.

A variation of the above approach is to first determine which delay stage setting provides the most accurate measurement by determining which setting provides the lowest value of Vavg. Once the optimum setting has been determined, then this setting can be used to make an accurate measurement. The advantage of first determining the lowest value of Vavgis due to the fact that it is not necessary to wait for the low pass filter to fully settle in order to make this determination. Once the optimum setting has been determined, then that setting can be used to make an accurate measurement. Thus, the total time is less than when two accurate measurements must be made.

A still further embodiment, referred to as Type 6, is shown inFIGS. 34A, B and C. This embodiment is similar to the embodiment ofFIGS. 33A, B and C except that the controlled delay stages are disposed after the gain stages AN+1 and BN+1 which provide respective phase information Δφ1and Δφ2used to provide compensation for delay dispersion due to input amplitude differences. One consequence of this approach is that the number of multipliers must be doubled to M1to M4. However, all of the gain stages in each channel are identical and provide equal delays so that implementation is easier.

A signal Set1is used to introduce a delay (ΔφAD) in either channel A or a delay (ΔφBD) in channel B. Each channel can provide γ number of additional delays (AN+2, 3, .. . or BN+2, 3, .. . ) depending on the state of Set1. Compensating for the added phase can be provided when calculating Vphaseby adding or subtracting the value γ*VSAT.

FIG. 34Bshows the active components of theFIG. 34Aembodiment when Set1is high. First, multipliers M3and M4are disabled as are stages BN+2, BN+3 and BN+4, typically by shutting them down to save power. Thus, none of the connections to M3and M4are depicted inFIG. 34B. In this case, stage AN+4 provides two functions including providing part of delay ΔφADand providing delay dispersion information along with stage BN+1. Thus, the input of stage AN+4 is provided to one input of multiplier M2, with the output of stage BN+1 providing the other input to M2. The input of stage BN+1 is applied to one input of multiplier M1, with the other input of M1coming from the output of stage AN+4.

FIG. 34Cshows the active components of theFIG. 34Aembodiment when Set1is low. Multipliers M1and M2are disabled as are stages AN+2, AN+3 and AN+4, with M3and M4being operative. Stage BN+4 provides two functions including providing part of delay ΔφBDand providing delay dispersion information along with stage AN+1. Thus, the input of stage BN+4 is provided to one input of multiplier M3, with the output of stage AN+1 providing the other input to M3. The input of stage AN+1 is applied to one input of multiplier M4, with the other input to M4coming from the output of stage BN+4.

The equations (22) and (23) previously set forth in connection with the Type 1 embodiment ofFIG. 19can be readily adapted to theFIG. 34Aembodiment to take into account the additional delay. For the case where 0≦Δφ≦π, Vphasecan be expressed as follows:

For the case where −π≦Δφ≦0 Vphaseis as follows:

The values of Vsatare unchanged from the Type 1 embodiment. For 0≦Δφ≦π, Vsatis as follows:
Vsat=−2VMULT[(Δφ1+Δφ2)/π]  (47)

FIG. 35is a simplified diagram for producing Vphase. The Vavgterm produced by adder A1ofFIGS. 34A, B and C is provided to an input of a subtractor circuit148. For the case where 0≦Δφ≦π, Vavgcan be expressed as follows:
Vavg=2VMULT[(1−2Δφπ)−γ*(2*Set1−1)(2Δφs)/π]  (49)

For the case where −π≦Δφ≦0, Vavgcan be expressed as follows:
Vavg=2VMULT[(1+2Δφ/π)+γ*(2*Set1−1)(2Δφs)/π]  (50)

A correction value Vcoris provided to another input of subtractor circuit148to produce Vphase. Vcoris produced first by extracting the sign of Set1as indicated by element150. The output of element150is +1 if Set1>0.5 and is −1 if Set1<0.5. The value of γ (3 in the present example) is multiplied by Vsatby multiplier152. The product is multiplied by the output of element150to produce a further product by multiplier154which is sent to one input of an adder circuit155. Vsatis also sent to another multiplier156where it is multiplied by the α term, with the product being sent to a still further multiplier158. The log term and the β terms are multiplied together by multiplier160, where the product is then sent to the other input of multiplier158. The outputs of multipliers154and158are added by adder155to produce Vcor, the correction voltage subtracted from Vavgto produce Vphase.

Thus, various embodiments of the present invention have been disclosed. Although these embodiments have been described in some detail, it is to be understood that certain changes can be made by those skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.