Processing Memory Access Transactions

A memory attribute structure comprises one or more memory address entries. Each memory address entry comprising a respective memory address range mapped to a respective priority level. The memory attribute table is used when processing a memory access transaction through an execution path of a processing system. During said processing, a memory address of the memory access transaction is determined. The memory attribute structure is used to determine a priority level mapped to the determined memory address, and the memory access transaction is processed based on the determined priority level.

TECHNICAL FIELD

The present disclosure relates to the processing of memory access transactions (e.g. load and store transactions) by a processing system.

BACKGROUND

In a computing (or processing) system, a central processing unit (CPU) is responsible for executing instructions of a computer program. A CPU typically includes arithmetic-logic units (ALUs) that perform arithmetic and logic operations, processor registers that supply operands to the ALU and store the results of ALU operations, a control unit responsible for fetching, decoding and executing instructions as part of an instruction cycle, and one or more buses allowing data to flow between the other components. The components of the CPU are arranged in execution paths (or data paths). During a given instruction cycle, an instruction is fetched from program memory, then decoded to determine what the CPU is required to do, and finally executed. Data is transferred along one of the execution paths of the CPU during execution of the instruction.

Processing systems may have a load-store architecture whereby the instruction set architecture (i.e. the set of instructions that are implemented by the system) fall into one of several categories, including: memory access instructions (in which data is transferred between memory and registers), ALU operations (in which data is transferred between registers only), instructions which modify system registers without using the ALU, branches, system calls, barriers, and no-ops (NOPs).

A memory system (or memory access) instruction refers to a load or store instruction. For example, a memory access instruction may be “read the value from memory address1234into value A” or “write value B to memory address 5678”. A given memory access instruction may give rise to one or more memory access transactions, i.e. one or more requests to read or write data from or to memory. When a CPU executes memory instructions, some memory system transactions (i.e. loads or store requests) go through the same execution path, e.g. from the control unit through a memory system unit to a slave (e.g. DRAM controller), and a result may be returned along the same path. Whether transactions go through the same execution path depends on the design of the CPU.

Transactions typically require storing data and control information into buffers inside and outside of the CPU. Put another way, transactions may need to write to certain buffers in the memory system in order to progress through the memory system.

When processing multiple transactions which use the same execution path, a part of the execution path or a buffer may be in use by a previous transaction (e.g. a transaction of a previously executed instruction, or a different transaction resulting from the same instruction), meaning that the processing of a current transaction is delayed until that part of the execution path or buffer becomes available for the current transaction. That is, the processing of one transaction is dependent on the processing of another transaction.

The dependency of the processing of one transaction on another is problematic. For instance, it is problematic if a transaction needs to be executed quickly (i.e. within a certain time frame) and execution of the transaction requires a component of the execution path or a buffer that is currently in use by a different transaction. For example, the transaction may relate to a safety-critical operation which should not be delayed by other non-safety related operations. A specific example is in the context of anti-lock braking systems (ABS). In this context, a transaction relating to an instruction to apply the brakes should not be impacted by other transactions. There is therefore a need for a CPU to be able to prioritise a certain subset of a group of transactions which do use the same execution path.

SUMMARY

This Summary is provided merely to illustrate some of the concepts disclosed herein and possible implementations thereof. Not everything recited in the Summary section is necessarily intended to be limiting on the scope of the disclosure. Rather, the scope of the present disclosure is limited only by the claims.

Some CPUs require that certain memory access instructions have higher determinism or Quality of Service (QOS) guarantees than others. In other words, a CPU may require that a particular memory access instruction is executed within a time threshold, or without any delay. Previous attempts at dealing with this issue involve having separate ports (a port being a collection of signals which are used to send data between two sections of the system) for each memory region (i.e. address range) that needs a determinism guarantee, the location of these ports being in a fixed address space, and the ports being driven by separate, non-shared logic.

Some embodiments of the present disclosure solve the problem by using a memory attribute structure (e.g. a look-up table) to specify certain memory regions as high priority, and prioritise the processing of transactions that require a high priority memory region.

Some embodiments of the present disclosure solve the problem by using a memory attribute structure to specify certain memory regions as high priority, and reserve buffer space (e.g. a collection of registers (or other memory type, such as RAMs) which is used to store the data or control for a transaction) for transactions that require a high priority memory region.

According to embodiments of the present disclosure, marking a transaction as high priority means that it can be prioritised at some or all stages of the execution path. This has the effect that it reaches the slave unit (e.g. DRAM controller) as quickly as possible without having to wait for the execution path to deal with other transactions. Similarly, a result of the transaction may be prioritised when being returned to the CPU.

Similarly, reserving buffer space for high priority transactions has the effect that there are free buffers available for reading and writing the data required by the (load or store) transaction, meaning that processing of the high priority transaction is not delayed until buffer space becomes available.

According to one aspect disclosed herein, there is provided a method of processing a memory access transaction through an execution path of a processing system. A memory attribute structure comprises one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels. The method comprises determining a memory address of the memory access transaction; using the memory attribute structure to determine a priority level mapped to the determined memory address; and processing the memory access transaction based on the determined priority level.

Each memory address entry specifies the respective priority level of the respective memory address range. That is, the respective priority level of a memory address range is defined in (and dictated by) the memory attribute table.

Using the memory attribute structure to determine the priority level may comprise identifying (e.g. looking-up) the memory address of the memory access transaction in the memory attribute table, and identifying the priority level specified for that memory address region as part of the relevant memory address entry.

In embodiments, processing the memory access transaction comprises associating the memory access transaction with the determined priority level, and prioritising the memory access transaction over one or more respective memory access transactions associated with respective priority levels having a lower priority than the determined priority level.

For example, the memory access transaction may be prioritised for one or more of: transmission over one or more interfaces of the processing system, acceptance into buffer space, and processing by one or more components of the execution path.

In embodiments, the memory access transaction may be associated a flag indicating the priority level.

In embodiments, the processing system may comprise one or more buffer spaces reserved for use by memory access transactions associated with a predetermined priority level. The memory access transaction may be allocated to one of said reserved buffer spaces.

In embodiments, the memory attribute structure may be configurable by a user of the processing system. For example, one or more of the following may be configurable: the respective priority level mapped to the respective memory address range, the one or more reserved buffer spaces reserved for use by memory access transactions associated with a respective priority level, a number of priority levels of the set of priority levels is configurable, and a respective number of reserved buffer spaces per respective priority level.

According to another aspect disclosed herein, there is provided a processing system for processing a memory access transaction through an execution path of the processing system. The processing system has stored, in memory, a memory attribute structure comprising one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels. The processing system is configured to: determine a memory address of the memory access transaction; use the memory attribute structure to determine a priority level mapped to the determined memory address; and process the memory access transaction based on the determined priority level.

According to another aspect disclosed herein, there is provided a method of configuring a memory attribute structure for use when processing memory access transactions through an execution path of a processing system. The method comprises configuring one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels. A central processing unit of the processing system is configured to use the memory attribute structure to determine respective priority levels mapped to respective memory addresses of respective memory access transaction, and process the respective memory access transactions based on the respective priority levels.

According to another aspect disclosed herein, there is provided a processing system for processing a memory access transaction through an execution path of the processing system. The processing system has stored, in memory, a memory attribute structure comprising one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels. The processing system is configured to: configure one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels; use the memory attribute structure to determine respective priority levels mapped to respective memory addresses of respective memory access transaction; and process the respective memory access transactions based on the respective priority levels.

According to another aspect disclosed herein, there is provided a memory attribute structure for use by a central processing unit when processing memory access transactions through an execution path of a processing system, wherein the memory attribute structure comprises one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels.

The processing system may be embodied in hardware on an integrated circuit. There may be provided a method of manufacturing, at an integrated circuit manufacturing system, a processing system. There may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture a processing system. There may be provided a non-transitory computer readable storage medium having stored thereon a computer readable description of a processing system that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying a processing system.

There may be provided an integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable description of the processing system; a layout processing system configured to process the computer readable description so as to generate a circuit layout description of an integrated circuit embodying the processing system; and an integrated circuit generation system configured to manufacture the processing system according to the circuit layout description.

There may be provided computer program code for performing any of the methods described herein. There may be provided non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform any of the methods described herein.

DETAILED DESCRIPTION

Embodiments will now be described by way of example only.

FIG.3schematically illustrates a simplified version of a processing system. The processing system includes a CPU (i.e. a main processing unit)302, an interconnect304and a memory system310. The memory system310is external to the CPU302. The CPU302is connected to and configured to communicate with the memory system310via the interconnect304(i.e. a communication bus). The CPU302is connected to the interconnect304via an interface308. Similarly, the interconnect304is connected to the memory system310via an interface306. The processing system also includes a memory attribute structure312. The memory attribute structure may take the form of a table or more generally any type of code. The memory attribute table312may be stored within the CPU302or separate from the CPU. Either way, the CPU is configured to access the memory attribute table. The memory system310may take any suitable form such as, for instance, one or more caches, one or more registers and main memory. The system may include each type of memory. Whilst the memory system310is shown connected to the interconnect304via a single interface306, it will be appreciated that the memory system310may be made up of several sub-systems, each having its own connection to the interconnect.

The memory attribute table includes, amongst other things, a plurality of memory address entries. Each memory address entry specifies a region (or range) of memory. The memory region may be specified by an upper and lower address. Alternatively, the memory region may be specified by a lower address and a size. Each memory range is mapped to (i.e. associated with) a priority level. For example, each memory address entry may be a key-value pair, where the key is the memory range and the value is the priority level. In some examples, there are only two priority levels, e.g. high and low, or prioritised and not prioritised. In these examples, the memory regions that are either mapped to a low priority level or are not prioritised, need not include an indication of the low (or lack of) priority. That is, the absence of an indication of high priority suffices. In some examples, there may be more than two priority levels, e.g. high, medium and low, or very high, high and low. There may be any number of priority levels as long as they follow a hierarchy, with a highest priority level and a lowest priority level. The priority level may be indicated in the memory attribute table in any suitable way, e.g. as an integer (1 or 0), a string (e.g. “high” or “low”), or otherwise. In some examples, only some of the available memory range are included as part of respective entries in the memory attribute table. In other examples, each available memory range is included as part of a respective entry in the memory attribute table. In the former examples, a lack of inclusion of a memory range may be interpreted as that memory range having the lowest priority.

One reason for marking an address range as high priority is that certain peripherals (e.g. external devices) are of particular importance to high priority code and will be in a given address range. Another reason is that the system needs to reserve a small, fast, block of memory for high priority code, and leave the large, slow, block of memory for normal code.

The memory attribute table may include other information, discussed further below.

The processing system is configured to process memory access instructions, i.e. load and store instructions. A given memory access instruction may be decoded into one or more memory access transactions. A memory access transaction is the request to read or write data. For simplicity, examples will primarily be described in the context of a one-to-one mapping of instruction to transaction, but it should be appreciated that the examples may be applied more generally to a one-to-many mapping of instruction to transactions. The examples may also be applied to a many-to-one mapping of transactions to instructions, where multiple instructions are to the same region of memory, and can be combined into one transaction.

Each memory access transaction is associated with a memory address. If the memory access transaction is a request to load (i.e. read) data, the memory address may be an address in memory310where the requested data is stored. If the memory access transaction is a request to store (i.e. write) data, the address may be an address in memory310where the data is to be stored.

The processing system is configured to process memory access transactions based on the associated memory address and a priority level of that memory address. When processing a memory access transaction, the CPU302determines (e.g. when decoding the corresponding memory access instruction) a memory address required by the transaction. The CPU302looks up the memory address in the memory attribute table. That is, the CPU302determines which memory address entry includes a memory range incorporating the memory address required by the transaction. The CPU302then identifies the priority level mapped to the memory range that incorporates the required memory address. Thereafter, the processing of the memory access transaction is based, at least in part, on the priority level.

The CPU302may associate a memory access transaction with a priority level. This may be done in any suitable way. For example, the CPU302may attach (e.g. prepend or append) a flag (e.g. one or more bits) to the transaction which indicates the priority level. The flag may remain attached to the memory access transaction as it passes to each component of the processing system so that the component is aware of its priority level.

The memory access transaction may be prioritised for processing over memory access transactions having a lower priority. That is, the CPU302may determine respective memory addresses required by one or more other memory access transactions, and then determine the corresponding priority levels of those memory addresses. If the memory transaction is associated with a priority level higher (i.e. greater, more important, etc.) than that of one or more of those other memory access transactions, the memory transaction is prioritised over the lower priority transactions. E.g. in the case of only two priority levels, if the transaction is a high priority transaction it is prioritised over low priority transactions. In contrast, the transaction may not be prioritised over transactions having a higher priority than the target priority level. Similarly, in some examples, the transaction is not prioritised over previous transactions (i.e. transactions that the CPU302has already begun processing) having the same priority level.

The memory access transaction may be prioritised over lower priority memory access transactions for transmission to one or more components of the processing system. That is, the memory access transaction may be prioritised when selecting which memory access transaction to send over one or more interfaces between components of the processing system. For instance, the memory access transaction may be prioritised for transmission between the CPU302and interconnect304and/or between the interconnect304and the memory system310. Similarly, a result of the operation(s) triggered to be performed by the memory access transaction may be prioritised when being returned to the CPU302from the memory system310via the interconnect304. In some examples, selection of the memory access transaction is prioritised at each interface of the processing system.

The memory access transaction may be prioritised over lower priority memory access transactions for processing by one or more components of the processing system. For example, the CPU302may process the memory access transaction ahead of one or more lower priority transactions, e.g. the memory access transaction may be chosen for execution ahead of the lower priority transactions. The interconnect304may process the memory access transaction ahead of one or more lower priority transactions, e.g. the memory access transaction may be sent to the memory system310ahead of the lower priority transactions. Similarly, the memory access transaction may be prioritised for acceptance into buffer space ahead of the lower priority transactions. That is, if buffer space is available for accepting a transaction, the memory access transaction may be sent to the buffer instead of the lower priority transactions.

As mentioned, the processing system may include a plurality of buffers. One or more buffers are included in logic internal to the CPU302. One or more buffers may be included in logic internal to the interconnect304. Of those buffers, some may be reserved for prioritising the processing of high priority transactions. That is, some buffers may be marked as “reserved buffers”. When the CPU302determines that a memory access transaction has a certain priority level (e.g. any level above the lowest priority level), one of the reserved buffers may be kept free for accepting the memory access transaction. In other words, the CPU302allocates the memory access transaction to a reserved buffer such that there is no delay in the memory access transaction being sent to and stored in a buffer.

Each memory region may be mapped to one or more reserved buffers. Additionally or alternatively, each priority level may be mapped to one or more reserved buffers. The mappings may be stored in the memory attribute table312. For example, a memory address entry map comprise a memory region mapped to the one or more reserved buffers. The entry may contain an indication or reference of the reserved buffers for use by the CPU302in directing a memory access transaction to one of said buffers.

The memory address entries in the memory attribute table may be fixed or configurable by a user a device embodying the processing system. In the latter case, one or more entries may be pre-loaded. New entries may be created. Entries may be edited. For example, a user may configure the memory attribute table by mapping priority levels to memory address ranges. The number of priority levels may be selected by the user. The user may configure the memory attribute table by marking one or more buffers as reserved buffers. The user may select the number of reserved buffers allocated to each memory range and/or priority level. A total number of reserved buffers may be chosen by the user. The memory attribute table may be configured at build time of the processing system.

FIG.4shows an example flow a memory access transaction according to embodiments described herein. Some steps may be omitted and/or performed in a different order. The flow may involve additional steps not shown. In step S01, the CPU302executes a memory access instruction which generates one or more memory access transactions. For a given memory access transaction, the CPU302determines, in step S02a memory address associated with that transaction. In step S03, the CPU302looks-up the memory address in a memory attribute table312and determines if the memory address is marked as high priority. If the memory address is marked as high priority, the transaction is marked as high priority (e.g. with a flag) in step S04. If the memory address is marked as high priority, buffer space is reserved for the transaction in step S05. In step S06, the high priority transaction is prioritised over lower priority transactions for processing, including: prioritizing selection of the transaction to be sent over a CPU-interconnect interface308and any interconnect-slave interface (e.g. between the interconnect and a slave or secondary processing unit, if present), prioritizing acceptance of the transaction into reserved buffer space, and prioritizing the sending of a result of the transaction being executed to be sent over the slave-interconnect interface and/or interconnect-CPU interface308.

The processing system may have a RISC-V architecture. The memory attribute table may be a physical memory attribution (PMA) table. The RISC-V PMA table may be extended so that it specifies the determinism/QoS requirements for each address range. Each set of memory regions with a shared requirement may have internal buffers and logic reserved for a group of memory accesses and may have its own external interface. The number of groups, amount of reserved logic for each group, and the regions per group, may all be configurable at build time. Existing solutions are not as configurable or flexible, are more complex, and have a higher area cost. For example, if a system had different ports for different memory ranges to provide a determinism guarantee, that would require additional area to provide the dedicated logic for driving the different ports, and the memory ranges could not be changed once the hardware had been manufactured. In contrast, the present solution allows the same hardware logic to be configured in different ways, according to the usage requirements.

FIG.1shows a computer system in which processing systems described herein may be implemented. The computer system comprises a CPU902, a GPU904, a memory906, a neural network accelerator (NNA)908and other devices914, such as a display916, speakers918and a camera922. A processing block910is implemented on the CPU902. The processing block may be configured to perform the methods described herein. In other examples, one or more of the depicted components may be omitted from the system, and/or the processing block910may be implemented on the GPU904or within the NNA908. The components of the computer system can communicate with each other via a communications bus920. A store912is implemented as part of the memory906.

Whilst shown as having different labels, the CPU302, interconnect304and memory310ofFIG.3may be the same components as the CPU902, bus920and memory906ofFIG.1. The processing block910may be configured to perform the operations described above as being performed by the CPU302.

The processing system ofFIGS.1to3are shown as comprising a number of functional blocks. This is schematic only and is not intended to define a strict division between different logic elements of such entities. Each functional block may be provided in any suitable manner. It is to be understood that intermediate values described herein as being formed by a processing system need not be physically generated by the processing system at any point and may merely represent logical values which conveniently describe the processing performed by the processing system between its input and output.

Therefore, there may be provided a method of manufacturing, at an integrated circuit manufacturing system, a processing system as described herein. Furthermore, there may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, causes the method of manufacturing a processing system to be performed.

An integrated circuit definition dataset may be in the form of computer code, for example as a netlist, code for configuring a programmable chip, as a hardware description language defining hardware suitable for manufacture in an integrated circuit at any level, including as register transfer level (RTL) code, as high-level circuit representations such as Verilog or VHDL, and as low-level circuit representations such as OASIS (RTM) and GDSII. Higher level representations which logically define hardware suitable for manufacture in an integrated circuit (such as RTL) may be processed at a computer system configured for generating a manufacturing definition of an integrated circuit in the context of a software environment comprising definitions of circuit elements and rules for combining those elements in order to generate the manufacturing definition of an integrated circuit so defined by the representation. As is typically the case with software executing at a computer system so as to define a machine, one or more intermediate user steps (e.g. providing commands, variables etc.) may be required in order for a computer system configured for generating a manufacturing definition of an integrated circuit to execute code defining an integrated circuit so as to generate the manufacturing definition of that integrated circuit.

An example of processing an integrated circuit definition dataset at an integrated circuit manufacturing system so as to configure the system to manufacture a processing system will now be described with respect toFIG.2.

FIG.2shows an example of an integrated circuit (IC) manufacturing system1002which is configured to manufacture a processing system as described in any of the examples herein. In particular, the IC manufacturing system1002comprises a layout processing system1004and an integrated circuit generation system1006. The IC manufacturing system1002is configured to receive an IC definition dataset (e.g. defining a processing system as described in any of the examples herein), process the IC definition dataset, and generate an IC according to the IC definition dataset (e.g. which embodies a processing system as described in any of the examples herein). The processing of the IC definition dataset configures the IC manufacturing system1002to manufacture an integrated circuit embodying a processing system as described in any of the examples herein.