Multichip package system

A multichip package system is provided forming a substrate having a plurality of molding transfer channel, connecting a first integrated circuit die on a top side of the substrate, connecting a second integrated circuit die on a bottom side of the substrate, and concurrently encapsulating the first integrated circuit die and the second integrated circuit die with a molding compound flow through the plurality of the molding transfer channels.

TECHNICAL FIELD

The present invention relates generally to integrated circuit packages and more particularly to multichip package.

BACKGROUND ART

Modern consumer electronics, such as smart phones, personal digital assistants, and location based services devices, as well as enterprise electronics, such as servers and storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new package technologies while others focus on improving the existing and mature package technologies. Research and development in the existing package technologies may take a myriad of different directions.

One proven way to reduce cost is to use package technologies with existing manufacturing methods and equipments. Paradoxically, the reuse of existing manufacturing processes does not typically result in the reduction of package dimensions. Existing packaging technologies struggle to cost effectively meet the ever demanding integration of today's integrated circuits and packages.

In response to the demands for improved packaging, many innovative package designs have been conceived and brought to market. Integrated circuit stacking is one of the packaging trend for the reduction of package dimensions. Mixed integrated circuit technology or system in package (SIP) is another approach to reduce the space required for the integrated circuits content. But these packaging types have some problems and typically undergo multi-step process for molding the integrated circuits. Another problem is the adverse interactions, such as cross talk, between the integrated circuit in the package in various applications, such as a combination of radio frequency (RF) device and baseband.

Thus, a need still remains for the multichip package system providing low cost manufacturing as well as improved performance. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.

DISCLOSURE OF THE INVENTION

The present invention provides a multichip package system including forming a substrate having a plurality of molding transfer channel, connecting a first integrated circuit die on a top side of the substrate, connecting a second integrated circuit die on a bottom side of the substrate, and concurrently encapsulating the first integrated circuit die and the second integrated circuit die with a molding compound flow through the plurality of the molding transfer channels.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the figures. In addition, where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.

The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure.

Referring now toFIG. 1, therein is shown a cross-sectional view of a first multichip package system100along a line1-1′ shown inFIG. 2in an embodiment of the present invention. The first multichip package system100includes a substrate102having a first molding transfer channel104and a second molding transfer channel106.

A first integrated circuit die108is over the first molding transfer channel104and attaches on a top side110of the substrate102with an adhesive112. First interconnects114, such as bond wires, connect between the first integrated circuit die108and the top side110. A second integrated circuit die116is between the first molding transfer channel104and the second molding transfer channel106on a bottom side118of the substrate102. The adhesive112attaches the second integrated circuit die116on the bottom side118. Second interconnects120, such as bond wires, connect between the second integrated circuit die116and the bottom side118as well as located between the first molding transfer channel104and the second molding transfer channel106. Devices122, such as small packaged components, are on the top side110. The substrate102may include a shield130, such as a conductive material, to isolate adverse interactions, such as cross-talk, between the first integrated circuit die108and the second integrated circuit die116.

A molding compound flows through the first molding transfer channel104and the second molding transfer channel106forming an encapsulation124to cover the first integrated circuit die108, the first interconnects114, the second integrated circuit die116, the second interconnects120, and the devices122. The first molding transfer channel104and the second molding transfer channel106allows the encapsulation124formed in a single process. The encapsulation124forms a center gate mold126on the bottom side118minimally extending beyond the first molding transfer channel104and the second molding transfer channel106providing space for external interconnects128, such as solder balls, for connections to the next system level (not shown), such as a printed circuit board.

Referring now toFIG. 2, therein is shown a bottom view of the first multichip package system100. The bottom view depicts the center gate mold126at a central region of the substrate102. The geometric shape, such as a square, of the center gate mold126is similar to the shape of the substrate102. The external interconnects128are on the substrate102. The location of the center gate mold126forms a symmetric number of rows of the external interconnects128on each side of the center gate mold126.

For illustrative purpose, the center gate mold126is shown as a substantially same geometric shape as the substrate102, although it is understood that the geometric shape of the center gate mold126may be different than that of the substrate102. Also for illustrative purpose, the number of the external interconnects128or the rows of the external interconnects128are shown equal in number extending from each side of the center gate mold126, although it is understood that the external interconnects128may not in a symmetrical configuration in relation to the center gate mold126.

Referring now toFIG. 3, therein is shown a top view of the first multichip package system100. The encapsulation124is shown to cover the top side110ofFIG. 1.

Referring now toFIG. 4, therein is shown a cross-sectional view of a second multichip package system400along a line4-4′ shown inFIG. 5in yet another alternative embodiment of the present invention. The second multichip package system400includes a substrate402having a first molding transfer channel404and a second molding transfer channel406. The first molding transfer channel404and the second molding transfer channel406are optional.

A first integrated circuit die408is between the first molding transfer channel404and the second molding transfer channel406on a top side410of the substrate402. An adhesive412attaches the first integrated circuit die408on the top side410. First interconnects414, such as bond wires, connect between the first integrated circuit die408and the top side410as well as located between the first molding transfer channel404and the second molding transfer channel406. A second integrated circuit die416is between the first molding transfer channel404and the second molding transfer channel406on a bottom side418of the substrate402. The adhesive412attaches the second integrated circuit die416on the bottom side418. Second interconnects420, such as bond wires, connect between the second integrated circuit die416and the bottom side418as well as located between the first molding transfer channel404and the second molding transfer channel406. Devices422, such as small packaged components, are on the top side410also between the first molding transfer channel404and the second molding transfer channel406. The substrate402may include a shield430, such as a conductive material, to isolate adverse interactions, such as cross-talk, between the first integrated circuit die408and the second integrated circuit die416.

A molding compound flows through the first molding transfer channel404and the second molding transfer channel406forming an encapsulation424to cover the first integrated circuit die408, the first interconnects414, the second integrated circuit die416, the second interconnects420, and the devices422. The first molding transfer channel404and the second molding transfer channel406allows the encapsulation424formed in a single process. The cross-sectional view shows the encapsulation424extending beyond the first molding transfer channel404and the second molding transfer channel406on both the top side410and the bottom side418.

Referring now toFIG. 5, therein is shown a bottom view of the second multichip package system400. The bottom view depicts a center gate mold526at a central region of the substrate402with bottom runners530extending from the corners of the center gate mold526to the corresponding comers of the substrate402. The bottom runners530provide channels for the molding compound flow. The geometric shape, such as a square, of the center gate mold526is similar to the shape of the substrate402. External interconnects528are on the substrate402. The location of the center gate mold526forms a symmetric number of rows of the external interconnects528on each side of the center gate mold526.

For illustrative purpose, the center gate mold526is shown as a substantially same geometric shape as the substrate402, although it is understood that the geometric shape of the center gate mold526may be different than that of the substrate402. Also for illustrative purpose, the number of the external interconnects528or the rows of the external interconnects528are shown equal in number extending from each side of the center gate mold526, although it is understood that the external interconnects528may not in a symmetrical configuration in relation to the center gate mold526. Further for illustrative purpose, the bottom runners530are shown extending from the corners of the center gate mold526, although it is understood that the bottom runners530may extend other than the corners of the center gate mold526.

Referring now toFIG. 6, therein is shown a top view of the second multichip package system400. The encapsulation424is shown to cover the top side410ofFIG. 4.

Referring now toFIG. 7, therein is shown a cross-sectional view of a third multichip package system700along the line1-1′ shown inFIG. 2in an alternative embodiment of the present invention. The bottom view ofFIG. 2may also represent a bottom view for the third multichip package system700.

Similarly, the third multichip package system700includes a substrate702having a first molding transfer channel704, a second molding transfer channel706, and a shield730, such as a conductive material. A first integrated circuit die708is over the first molding transfer channel704and attaches on a top side710of the substrate702. First interconnects714, such as bond wires, connect between the first integrated circuit die708and the top side710. Devices722, such as small packaged components, are on the top side710.

A second integrated circuit die716is between the first molding transfer channel704and the second molding transfer channel706on a bottom side718of the substrate702. Second interconnects720, such as solder bumps or solder balls, connect between the second integrated circuit die716and the bottom side718.

Similarly, a molding compound flows through the first molding transfer channel704and the second molding transfer channel706forming an encapsulation724to cover the first integrated circuit die708, the first interconnects714, the second integrated circuit die716, the second interconnects720, and the devices722in a single process. The encapsulation724forms a center gate mold726on the bottom side718minimally extending beyond the first molding transfer channel704and the second molding transfer channel706providing space for external interconnects728, such as solder balls, for connections to the next system level (not shown), such as a printed circuit board.

Referring now toFIG. 8, therein is shown a cross-sectional view of a fourth multichip package system800along the line1-1′ shown inFIG. 2in another alternative embodiment of the present invention. The bottom view ofFIG. 2may also represent a bottom view for the fourth multichip package system800. Similarly, the fourth multichip package system800includes a substrate802having a first molding transfer channel80, a second molding transfer channel806, and a shield830, such as a conductive material. Devices822, such as small packaged components, are on a top side810of the substrate802.

A first integrated circuit die808is over the first molding transfer channel804and attaches on the top side810of the substrate802. First interconnects814, such as solder bumps or solder balls, connect between the first integrated circuit die808and the top side810. A second integrated circuit die816is between the first molding transfer channel804and the second molding transfer channel806on a bottom side818of the substrate802. Second interconnects820, such as solder bumps or solder balls, connect between the second integrated circuit die816and the bottom side818.

Similarly, a molding compound flows through the first molding transfer channel804and the second molding transfer channel806forming an encapsulation824to cover the first integrated circuit die808, the first interconnects814, the second integrated circuit die816, the second interconnects820, and the devices822in a single process. The encapsulation824forms a center gate mold826on the bottom side818minimally extending beyond the first molding transfer channel804and the second molding transfer channel806providing space for external interconnects828, such as solder balls, for connections to the next system level (not shown), such as a printed circuit board.

Referring now toFIG. 9, therein is shown a cross-sectional view of a fifth multichip package system900along the line1-1′ shown inFIG. 2in yet another alternative embodiment of the present invention. The bottom view ofFIG. 2may also represent a bottom view for the fifth multichip package system900. Similarly, the fifth multichip package system900includes a substrate902having a first molding transfer channel904, a second molding transfer channel906, and a shield930, such as a conductive material. Devices922, such as small packaged components, are on a top side910of the substrate902.

A first integrated circuit die908is over the first molding transfer channel904and attaches on the top side910of the substrate902. First interconnects914, such as solder balls or solder bumps, connect between the first integrated circuit die908and the top side910.

Similarly, a second integrated circuit die916is between the first molding transfer channel904and the second molding transfer channel906on a bottom side918of the substrate902. Second interconnects920, such as solder bumps or solder balls, connect between the second integrated circuit die916and the bottom side918as well as located between the first molding transfer channel904and the second molding transfer channel906.

Similarly, a molding compound flows through the first molding transfer channel904and the second molding transfer channel906forming an encapsulation924to cover the first integrated circuit die908, the first interconnects914, the second integrated circuit die916, the second interconnects920, and the devices922in a single process. The encapsulation924forms a center gate mold926on the bottom side918minimally extending beyond the first molding transfer channel904and the second molding transfer channel906providing space for external interconnects928, such as solder balls, for connections to the next system level (not shown), such as a printed circuit board.

Referring now toFIG. 10, therein is shown a top view of a first substrate1000in an embodiment of the present invention. The first substrate1000includes bond pads1002for electrical connections and molding transfer channels1004. A molding compound flows through the molding transfer channels1004providing a single step molding process. The molding transfer channels1004may be a number of different geometric shapes, such as a circle. The molding transfer channels1004are between the edge of the first substrate1000and the bond pads1002. The geometric shape and the number of the molding transfer channels1004may differ than depicted in the top view.

Referring now toFIG. 11, therein is shown a top view of a second substrate1100in an alternative embodiment of the present invention. The second substrate1100includes bond pads1102for electrical connections and slots1104. A molding compound flows through the slots1104providing a single step molding process. The slots1104are between the edge of the second substrate1100and the bond pads1102. The slots1104substantially parallel the vertical edges of the second substrate1100. The geometric shape and the number of the slots1104may differ than depicted in the top view.

Referring now toFIG. 12, therein is shown a top view of a third substrate1200in another alternative embodiment of the present invention. The third substrate1200includes bond pads1202for electrical connections and slots1204between the edge of the third substrate1200and the bond pads1202. Slits1206are each located between the edge of the third substrate1200and the slots1204. A molding compound flows through the slots1204and the slits1206providing a single step molding process. The slits1206are thinner and longer than the slots1204. The slots1204and the slits1206substantially parallel the vertical edges of the third substrate1200. The geometric shape and the number of the slots1204and the slits1206may differ than depicted in the top view.

Referring now toFIG. 13, therein is shown a top view of a fourth substrate1300in yet another alternative embodiment of the present invention. The fourth substrate1300includes bond pads1302for electrical connections and vertical slits1306. The vertical slits1306are between the bond pads1302and the vertical edges of the fourth substrate1300. A molding compound flows through the vertical slits1306providing a single step molding process. The vertical slits1306substantially parallel the vertical edges of the fourth substrate1300.

Referring now toFIG. 14, therein is shown a top view of a fifth substrate1400in yet another alternative embodiment of the present invention. The fifth substrate1400includes bond pads1402for electrical connections and horizontal slots1404. The horizontal slots1404are between the bond pads1402and parallel the horizontal edges of the fifth substrate1400. A molding compound flows through the horizontal slots1404providing a single step molding process.

Referring now toFIG. 15, therein is shown a top view of a sixth substrate1500in yet another alternative embodiment of the present invention. The sixth substrate1500includes bond pads1502for electrical connections, horizontal slots1504, and horizontal slits1506. The horizontal slots1504are between the bond pads1502and parallel the horizontal edges of the sixth substrate1500. The horizontal slits1506also parallel the horizontal edges of the sixth substrate1500and are also above as well as below the bond pads1502. A molding compound flows through the horizontal slots1504and the horizontal slits1506providing a single step molding process.

Referring now toFIG. 16, therein is shown a top view of a seventh substrate1600in yet another alternative embodiment of the present invention. The seventh substrate1600includes bond pads1602for electrical connections and molding transfer channels1604in groups, a first group1606, a second group1608, a third group1610, and a fourth group1612. The first group1606is at the left upper corner of the seventh substrate1600between the bond pads1602and the vertical edges of the seventh substrate1600. The second group1608is at the right upper corner of the seventh substrate1600between the bond pads1602and the vertical edges of the seventh substrate1600. The third group1610is at the right lower corner of the seventh substrate1600between the bond pads1602and the vertical edges of the seventh substrate1600. The fourth group1612is at the left lower corner of the seventh substrate1600between the bond pads1602and the vertical edges of the seventh substrate1600. A molding compound flows through the molding transfer channels1604providing a single step molding process.

Referring now toFIG. 17, therein is shown a top view of an eighth substrate1700in yet another alternative embodiment of the present invention. The eighth substrate1700includes bond pads1702and molding transfer channels1704in a geometric shape of orthogonal segments. The molding transfer channels1704are at the corners of the eighth substrate1700between the edges of the eighth substrate1700and the bond pads1702. A molding compound flows through the molding transfer channels1704providing a single step molding process.

Referring now toFIG. 18, therein is shown a bottom view of a first array1800of a multichip package system1802in an embodiment of the present invention. The multichip package system1802may represent the first multichip package system100ofFIG. 1, the third multichip package system700ofFIG. 7, the fourth multichip package system800ofFIG. 8, and the fifth multichip package system900ofFIG. 9. The first array1800includes rows of the multichip package system1802.

Each of the multichip package system1802includes a center gate mold1804at a central region of a substrate1806. The geometric shape, such as a square, of the center gate mold1804is similar to the shape of the substrate1806. External interconnects1808are on the substrate1806. The location of the center gate mold1804forms a symmetric number of rows of the external interconnects1808on each side of the center gate mold1804.

Referring now toFIG. 19, therein is shown a cross-sectional view of a sixth multichip package system1900along the line4-4′ shown inFIG. 5in yet another alternative embodiment of the present invention. The bottom view ofFIG. 5may also represent a bottom view for the sixth multichip package system1900.

Similarly, the sixth multichip package system1900includes a substrate1902having a first molding transfer channel1904, a second molding transfer channel1906, and a shield1930, such as a conductive material. The first molding transfer channel1904and the second molding transfer channel1906are optional. A first integrated circuit die1908is between the first molding transfer channel1904and the second molding transfer channel1906on a top side1910of the substrate1902. First interconnects1914, such as bond wires, connect between the first integrated circuit die1908and the top side1910. Devices1922, such as small packaged components, are on the top side1910.

A second integrated circuit die1916is between the first molding transfer channel1904and the second molding transfer channel1906on a bottom side1918of the substrate1902. Second interconnects1920, such as solder bumps or solder balls, connect between the second integrated circuit die1916and the bottom side1918.

Similarly, a molding compound flows through the first molding transfer channel1904and the second molding transfer channel1906forming an encapsulation1924to cover the first integrated circuit die1908, the first interconnects1914, the second integrated circuit die1916, the second interconnects1920, and the devices1922in a single process.

Referring now toFIG. 20, therein is shown a cross-sectional view of a seventh multichip package system2000along the line4-4′ shown inFIG. 5in yet another alternative embodiment of the present invention. The bottom view ofFIG. 5may also represent a bottom view for the seventh multichip package system2000. Similarly, the seventh multichip package system2000includes a substrate2002having a first molding transfer channel2004, a second molding transfer channel2006, and a shield2030, such as a conductive material. The first molding transfer channel2004and the second molding transfer channel2006are optional. Devices2022, such as small packaged components, are on a top side2010of the substrate2002.

A first integrated circuit die2008is between the first molding transfer channel2004and the second molding transfer channel2006on the top side2010of the substrate2002. First interconnects2014, such as solder bumps or solder balls, connect between the first integrated circuit die2008and the top side2010. A second integrated circuit die2016is between the first molding transfer channel2004and the second molding transfer channel2006on a bottom side2018of the substrate2002. Second interconnects2020, such as solder bumps or solder balls, connect between the second integrated circuit die2016and the bottom side2018.

Similarly, a molding compound flows through the first molding transfer channel2004and the second molding transfer channel2006forming an encapsulation2024to cover the first integrated circuit die2008, the first interconnects2014, the second integrated circuit die2016, the second interconnects2020, and the devices2022in a single process.

Referring now toFIG. 21, therein is shown a cross-sectional view of an eighth multichip package system2100along the line4-4′ shown inFIG. 5in yet another alternative embodiment of the present invention. The bottom view ofFIG. 5may also represent a bottom view for the eighth multichip package system2100. Similarly, the eighth multichip package system2100includes a substrate2102having a first molding transfer channel2104, a second molding transfer channel2106, and a shield2130, such as a conductive material. The first molding transfer channel2104and the second molding transfer channel2106are optional. Devices2122, such as small packaged components, are on a top side2110of the substrate2102.

A first integrated circuit die2108is between the first molding transfer channel2104and the second molding transfer channel2106on the top side2110of the substrate2102. First interconnects2114, such as solder balls or solder bumps, connect between the first integrated circuit die2108and the top side2110.

Similarly, a second integrated circuit die2116is between the first molding transfer channel2104and the second molding transfer channel2106on a bottom side2118of the substrate2102. Second interconnects2120, such as solder bumps or solder balls, connect between the second integrated circuit die2116and the bottom side2118as well as located between the first molding transfer channel2104and the second molding transfer channel2106.

Similarly, a molding compound flows through the first molding transfer channel2104and the second molding transfer channel2106forming an encapsulation2124to cover the first integrated circuit die2108, the first interconnects2114, the second integrated circuit die2116, the second interconnects2120, and the devices2122in a single process.

Referring now toFIG. 22, therein is shown a bottom view of a multichip package system2200in an embodiment of the present invention. The bottom view may represent a bottom view for the second multichip package system400ofFIG. 4, the sixth multichip package system1900ofFIG. 19, the seventh multichip package system2000ofFIG. 20, and the eighth multichip package system2100ofFIG. 21. The bottom view depicts a center gate mold2226at a central region of a substrate2202with bottom runners2230extending from the left upper and lower corners of the center gate mold2226to the corresponding corners of the substrate2202. The bottom runners2230provide channels for the molding compound flow. The geometric shape, such as a square, of the center gate mold2226is similar to the shape of the substrate2202. External interconnects2228are on the substrate2202. The location of the center gate mold2226forms a symmetric number of rows of the external interconnects2228on each side of the center gate mold2226.

For illustrative purpose, the center gate mold2226is shown as a substantially same geometric shape as the substrate2202, although it is understood that the geometric shape of the center gate mold2226may be different than that of the substrate2202. Also for illustrative purpose, the number of the external interconnects2228or the rows of the external interconnects2228are shown equal in number extending from each side of the center gate mold2226, although it is understood that the external interconnects2228may not in a symmetrical configuration in relation to the center gate mold2226. Further for illustrative purpose, the bottom runners2230are shown extending from the left upper and lower corners of the center gate mold2226, although it is understood that the bottom runners2230may extend other than the left upper and lower corners of the center gate mold2226.

Referring now toFIG. 23, therein is shown a bottom view of a multichip package system2300in an alternative embodiment of the present invention. The bottom view may represent a bottom view for the second multichip package system400ofFIG. 4, the sixth multichip package system1900ofFIG. 19, the seventh multichip package system2000ofFIG. 20, and the eighth multichip package system2100ofFIG. 21. The bottom view depicts a center gate mold2326at a central region of a substrate2302with bottom runners2330extending from the left lower and right upper corners of the center gate mold2326to the corresponding corners of the substrate2302. The bottom runners2330provide channels for the molding compound flow. The geometric shape, such as a square, of the center gate mold2326is similar to the shape of the substrate2302. External interconnects2328are on the substrate2302. The location of the center gate mold2326forms a symmetric number of rows of the external interconnects2328on each side of the center gate mold2326.

For illustrative purpose, the center gate mold2326is shown as a substantially same geometric shape as the substrate2302, although it is understood that the geometric shape of the center gate mold2326may be different than that of the substrate2302. Also for illustrative purpose, the number of the external interconnects2328or the rows of the external interconnects2328are shown equal in number extending from each side of the center gate mold2326, although it is understood that the external interconnects2328may not in a symmetrical configuration in relation to the center gate mold2326. Further for illustrative purpose, the bottom runners2330are shown extending from the left upper and lower corners of the center gate mold2326, although it is understood that the bottom runners2330may extend other than the left upper and lower corners of the center gate mold2326.

Referring now toFIG. 24, therein is shown a bottom view of a second array2400of the second multichip package system400in an embodiment of the present invention. The second array2400may also represent an array of the sixth multichip package system1900ofFIG. 19, the seventh multichip package system2000ofFIG. 20, and the eighth multichip package system2100ofFIG. 21. The second array2400includes rows of a multichip package system2402. Each of the second multichip package system400includes the center gate mold526at a central region of the substrate402. The external interconnects528are on the substrate402.

The bottom runners530of from each of the second multichip package system400in the second array2400are connected forming a molding compound flow channel spanning the second array2400. A first row2404of the second array2400includes an extension2406of the substrate402. The bottom runners530also extend to the edge of the extension2406.

Referring now toFIG. 25, therein is shown a bottom view of a third array2500of the multichip package system2200in an alternative embodiment of the present invention. The second array2400may also represent an array of the second multichip package system400ofFIG. 4, the sixth multichip package system1900ofFIG. 19, the seventh multichip package system2000ofFIG. 20, and the eighth multichip package system2100ofFIG. 21. The second array2400includes rows of the multichip package system2200. Each of the multichip package system2200includes the center gate mold2226at a central region of the substrate2202. The external interconnects2228are on the substrate2202.

The bottom runners2230of from each of the multichip package system2200in the third array2500are connected forming a molding compound flow channel spanning the third array2500. The multichip package system2200at the left upper corner of the third array2500has an additional instance of the bottom runners2230extending from the center gate mold2226to the right upper corner and connecting to one of the bottom runners2230of the adjacent instance of the multichip package system2200. A first row2502of the third array2500includes an extension2504of the substrate2202. The bottom runners2230extend to the edge of the extension2504.

Referring now toFIG. 26, therein is shown a bottom view of a fourth array2600of the multichip package system2300in another alternative embodiment of the present invention. The fourth array2600may also represent an array of the second multichip package system400ofFIG. 4, the sixth multichip package system1900ofFIG. 19, the seventh multichip package system2000ofFIG. 20, and the eighth multichip package system2100ofFIG. 21. The second array2400includes rows of the multichip package system2300. Each of the multichip package system2300includes the center gate mold2326at a central region of the substrate2302. The external interconnects2328are on the substrate2302.

The bottom runners2330of from each of the multichip package system2300in the third array2500are connected forming a molding compound flow channel spanning the third array2500. A first row2602of the fourth array2600includes an extension2604of the substrate2302. The bottom runners2330extend to the edge of the extension2604. The first row2602has the bottom runners2330extending from the center gate mold2326to the left lower and right upper corners of the multichip package system2300. A second row2606has the bottom runners2330extending from the center gate mold2326to the right lower and left upper corners of the multichip package system2300to connect to the bottom runners2330in the first row2602and a third row2608. This pattern of the bottom runners2330from one row to the next row alternates in the fourth array2600.

Referring now toFIG. 27, therein is shown a more detailed bottom view of the extension2406of the first row2404of the second array2400. This bottom view may also represent the bottom view of the third array2500ofFIG. 25or the fourth array2600ofFIG. 26. The bottom view depicts a corner of the extension2406with one instance of the bottom runners530extending from the center gate mold526, and the external interconnects528on the substrate402. The bottom runners530extend into the extension2406. A front slot2702for molding compound flow for the bottom runners530is part of the extension2406.

Referring now toFIG. 28, therein is shown a flow chart of a multichip package system2800for the manufacture of the multichip package system100in an embodiment of the present invention. The system2800includes forming a substrate having a plurality of molding transfer channels in a block2802; connecting a first integrated circuit die on a top side of the substrate in a block2804; connecting a second integrated circuit die on a bottom side of the substrate in a block2806; and concurrently encapsulating the first integrated circuit die and the second integrated circuit die with a molding compound flow through the plurality of the molding transfer channels in a block2808.

It has been discovered that the present invention thus has numerous aspects.

It has been discovered that in the present invention adding molding transfer channels in the substrate or the extension of the substrate allows the molding compound to encapsulate both the top side and the bottom side of the integrated circuit package in a single step.

An aspect is that the present invention provides molding transfer channels in the substrate which may be configured to provide flexibility to accommodate different integrated circuit sizes and other devices on the substrate.

Another aspect of the present invention is that the molding transfer channels in the substrate may be optional. The molding compound may encapsulate the bottom side of the integrated circuit package with one or more front slot molding transfer channels in an extension of the array of the integrated circuit package, before singulation. Bottom runners connect with the front slot in the extension and provide a channel for the molding compound to flow from each integrated circuit package in the array to another.

Thus, it has been discovered that the multichip package system method of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for increasing chip density in systems while simplifying manufacturing process. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing multichip packaged devices.