Signaling with superimposed clock and data signals

A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

TECHNICAL FIELD

The disclosed embodiments relate generally to data communications, and more particularly, to high speed electronic signaling within and between integrated circuits.

BACKGROUND

High speed data communications over a communications channel such as a backplane electrical link present significant engineering challenges. For example, edge-based clock and data recovery (CDR) limits receiver performance.

DESCRIPTION OF EMBODIMENTS

In some embodiments, a data transmission circuit includes a clock driver that obtains a clock signal having a first frequency and drives the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at a symbol rate corresponding to the second frequency. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

In some embodiments, a data transmission circuit includes a clock driver that obtains a clock signal having a first frequency and drives the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than or equal to one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines in a non-return-to-zero (NRZ) format at a symbol rate corresponding to the second frequency. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

In some embodiments, a data receiver circuit includes an interface coupled to one or more transmission lines. The interface simultaneously receives a data signal and a clock signal superimposed on the data signal. The clock signal has a first frequency. The data receiver circuit also includes a clock extraction circuit, coupled to the interface, to extract the clock signal, and a timing circuit to receive the clock signal and to generate a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than or equal to one. The data receiver circuit further includes a sampling circuit to sample the data signal. The sampling circuit is synchronized to the symbol clock.

In some embodiments, a method of transmitting data includes obtaining a clock signal having a first frequency, driving the clock signal onto one or more transmission lines, and generating a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than one. The method further includes obtaining a data signal and driving the data signal onto the one or more transmission lines at a symbol rate corresponding to the second frequency. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

In some embodiments, a method of transmitting data includes obtaining a clock signal having a first frequency, driving the clock signal onto one or more transmission lines, and generating a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than or equal to one. The method further includes obtaining a data signal and driving the data signal onto the one or more transmission lines in a non-return-to-zero (NRZ) format at a symbol rate corresponding to the second frequency. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

In some embodiments, a method of receiving data includes simultaneously receiving a data signal and a clock signal superimposed on the data signal, wherein the clock signal has a first frequency. The method also includes extracting the clock signal and generating a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than or equal to one. The method further includes sampling the data signal, wherein the sampling is synchronized to the symbol clock.

In some embodiments, a data transmission circuit includes means for obtaining a clock signal having a first frequency, means for driving the clock signal onto one or more transmission lines, and means for generating a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than one. The data transmission circuit also includes means for obtaining a data signal and means for driving the data signal onto the one or more transmission lines at a symbol rate corresponding to the second frequency. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

In some embodiments, a data transmission circuit includes means for obtaining a clock signal having a first frequency, means for driving the clock signal onto one or more transmission lines, and means for generating a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than or equal to one. The data transmission circuit also includes means for obtaining a data signal and means for driving the data signal onto the one or more transmission lines in a non-return-to-zero (NRZ) format at a symbol rate corresponding to the second frequency. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

In some embodiments, a data receiver circuit includes means for simultaneously receiving a data signal and a clock signal superimposed on the data signal, wherein the clock signal has a first frequency. The data receiver circuit also includes means for extracting the clock signal and means for generating a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than or equal to one. The data receiver circuit further includes means for sampling the data signal, wherein the means for sampling the data signal is synchronized to the symbol clock.

In some embodiments, a computer readable medium contains circuit description data that, when operated on by a circuit compiler program being executed by a processor, synthesizes a data transmission circuit that includes a clock driver. The clock driver obtains a clock signal having a first frequency and drives the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at a symbol rate corresponding to the second frequency. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

In some embodiments, a computer readable medium contains circuit description data that, when operated on by a circuit compiler program being executed by a processor, synthesizes a data transmission circuit that includes a clock driver. The clock driver obtains a clock signal having a first frequency and drives the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than or equal to one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines in a non-return-to-zero (NRZ) format at a symbol rate corresponding to the second frequency. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

In some embodiments, a computer readable medium contains circuit description data that, when operated on by a circuit compiler program being executed by a processor, synthesizes a data receiver circuit that includes an interface coupled to one or more transmission lines. The interface simultaneously receives a data signal and a clock signal superimposed on the data signal. The clock signal has a first frequency. The data receiver circuit also includes a clock extraction circuit, coupled to the interface, to extract the clock signal, and a timing circuit to receive the clock signal and to generate a symbol clock having a second frequency. The first frequency is a multiple of the second frequency, wherein the multiple is greater than or equal to one. The data receiver circuit further includes a sampling circuit to sample the data signal. The sampling circuit is synchronized to the symbol clock.

Multiple signals, such as a data signal and a clock signal, may be transmitted simultaneously over a channel, such as a transmission line or a pair of transmission lines. In some embodiments, a first signal is transmitted differentially over a pair of transmission lines and a second signal is simultaneously transmitted over the pair of transmission lines in a common mode. For example, a clock signal is transmitted in a common mode and a data signal is simultaneously transmitted differentially, where the data signal has a symbol rate corresponding to the frequency of the clock signal. Differential and common-mode signaling are discussed further with regard toFIGS. 1A and 1B, below. In some embodiments, a first signal is transmitted over a channel and a second signal is simultaneously transmitted over the channel at a frequency outside the frequency band of the first signal. For example, a clock signal is transmitted at a frequency greater than a symbol rate of a simultaneously transmitted data signal, as shown inFIGS. 7A and 7B, below.

In differential signaling, a first transmission line in a pair of transmission lines carries a signal and a second transmission line in the pair carries the inverse of the signal. The inverse of the signal has an equal magnitude and an opposite polarity to the signal. The sum of the voltages on the two transmission lines corresponding to the two signals is constant. A signal transmitted using differential signaling is herein referred to as a differential-mode signal.

FIG. 1Ais a schematic illustration of differential-mode signaling in accordance with some embodiments. A differential-mode signal100includes a first signal102transmitted on a first transmission line and a second signal104transmitted on a second transmission line. The second signal104has an equal magnitude (or a substantially equal magnitude if the circuits producing the two signals are not perfectly matched) and an opposite polarity to the first signal102. At the end of the transmission lines, a combiner106extracts the transmitted signal by taking the difference of the first signal102and the second signal104, producing an extracted signal108.

In some embodiments, a pair of transmission lines that transmits a differential mode signal simultaneously transmits a common-mode signal. In common-mode signaling, the same signal is transmitted over both transmission lines in the pair.

FIG. 1Bis a schematic illustration of common-mode signaling in accordance with some embodiments. A common-mode signal120includes a first signal122transmitted on a first transmission line and a second signal124transmitted on a second transmission line. The first signal122and the second signal124have equal magnitudes (or substantially equal magnitudes if the circuits producing the two signals are not perfectly matched) and equal polarities (i.e., the same polarity). At the end of the transmission lines, a combiner126extracts the transmitted signal by summing the first signal122and the second signal124, producing an extracted signal128.

Differential-mode and common-mode signals transmitted simultaneously over a pair of transmission lines can be independently extracted by a receiver. Taking the difference of the voltages on the two transmission lines (e.g., with a combiner106) will cancel out a common-mode signal and extract a differential-mode signal. Summing the voltages on the two transmission lines (e.g., with a combiner126) will cancel out a differential-mode signal and extract a common-mode signal.

In some embodiments, a pair of transmission lines that transmit differential-mode and/or common-mode signals are implemented as two or more traces on one or more printed circuit boards (e.g., a backplane link), two or more signal paths on a semiconductor device, or a channel in a network (e.g., an Ethernet network).

FIGS. 1C and 1Dillustrate waveforms associated with simultaneously transmitting differential-mode and common-mode signals over a pair of transmission lines in accordance with some embodiments. In these examples, a data signal is transmitted differentially and a clock signal is transmitted in a common-mode; some implementations may choose other different signaling modes for clock and data separation, such as sending data in common mode and clock in differential mode. InFIG. 1C, a data waveform140corresponding to a particular polarity of a differential-mode data signal and a clock waveform142corresponding to a common-mode clock signal have equal amplitudes. The differential-mode data signal and common-mode clock signal are simultaneously driven onto the pair of transmission lines, resulting in a waveform144on the first transmission line and a waveform146on the second transmission line. A receiver can recover the clock and data waveforms140and142, as described below.

InFIG. 1D, a data waveform150corresponding to a particular polarity of a differential-mode data signal has twice the amplitude of a clock waveform152corresponding to a common-mode clock signal. The differential-mode data signal and common-mode clock signal are simultaneously driven onto the pair of transmission lines, resulting in a waveform154on the first transmission line and a waveform156on the second transmission line. (Waveforms154and156are not drawn to scale with respect to waveforms150and152). InFIGS. 1C and 1Ddata transitions are phase-aligned to rising clock edges. Generally, however, data transitions and rising clock edges may be skewed.FIGS. 1C and 1Dare examples of different amplitude ratios between transmitted differential and common-mode signals. It follows from examples 1C and 1D that the ratio of the differential and common-mode signal may be selected to have some fractional amplitude relationship with the possibility of either signal being the larger, as conditions dictate.

FIG. 2Ais a block diagram of a data communications system200in accordance with some embodiments. The data communications system200includes a transmitter202, a pair of transmission lines204, and a receiver206.

The transmitter202receives for transmission a data signal208and a clock signal210. A clock driver218drives the clock signal via interfaces219onto the pair of transmission lines204in a common mode. Simultaneously, a data driver216drives the data signal via interfaces219onto the pair of transmission lines204in a differential mode with a symbol rate corresponding to the clock signal frequency. In some embodiments, the clock driver218and/or the data driver216are line drivers, such as digital-to-analog converters (DACs) (e.g., zero-order hold DACs). In some embodiments, the path between the clock driver218and the pair of transmission lines204includes termination resistors220. In some embodiments, the interfaces219include pins, balls, or other electrical contacts on a semiconductor package.

In some embodiments, a phase adjuster214receives the clock signal210and provides a phase-adjusted clock signal to a data retimer212. The data retimer212receives the data signal208and provides the data signal to the data driver216at a symbol rate corresponding to the clock signal frequency. In some embodiments, the phase adjuster214is a phase interpolator. In some embodiments, the phase adjuster214is a phase-locked loop (PLL), a delay-locked loop (DLL), a voltage controlled delay line (VCDL), or other timing adjustment circuit.

The receiver206receives via interfaces221a transmission signal that includes the differential-mode data signal and the common-mode clock signal. In some embodiments, the interfaces221include pins, balls, or other electrical contacts on a semiconductor package. A differential mode extraction circuit226extracts the differential-mode data signal from the received transmission signal. The extracted data signal is provided to a sampling circuit236that samples the extracted data signal.

A common mode extraction circuit228extracts the common-mode clock signal from the received transmission signal. In some embodiments, the common mode extraction circuit228includes buffers230and a combiner232. The extracted clock signal is provided to the sampling circuit236via an optional limiting amplifier234which can reduce the voltage and timing noise. In some embodiments, the common mode extraction circuit228includes a band-pass filter, such as an LC network with a resonant peak substantially centered on the clock signal frequency.

In some embodiments, a limit amplifier234, also referred to as a clipping amplifier, amplifies the extracted clock signal and provides the amplified clock signal to the sampling circuit236. In some embodiments a timing circuit receives the extracted clock signal and provides a clock signal to the sampling circuit236. In some embodiments, the timing circuit includes a PLL244(receiver242;FIG. 2B) or a DLL (not shown). In some embodiments, the timing circuit includes a phase interpolator (not shown).

In some embodiments, the receiver206includes buffers222to isolate the receiver circuitry from the pair of transmission lines204. In some embodiments, termination resistors224terminate the pair of transmission lines204. Each of the termination resistors224may be coupled at one end to a termination voltage source VTT, and at the other end to a respective transmission line204.

In some embodiments, a first pair of transmission lines transmits a first common-mode clock signal and a second pair of transmission lines transmits a second common-mode clock signal. The first and second common-mode clock signals have opposite polarities. Thus, taken together, the first and second common-mode clock signals provide a single differential clock signal.

FIG. 3is a block diagram of a data communications system300in accordance with some embodiments. The data communications system300includes two transmitters302, two pairs of transmission lines204, and two receivers306. In some embodiments, the first transmitter302-1simultaneously transmits a first differential-mode data signal and a first common-mode output clock signal, and the second transmitter302-2simultaneously transmits a second differential-mode data signal and a second common-mode output clock signal. The first and second common-mode clock signals have opposite polarities and thus effectively provide a single differential clock signal to the two receivers306-1and306-2. This reduces the electromagnetic interference (EMI) caused by the transmission of the clock signal.

Each transmitter302receives for transmission a respective data signal208. In some embodiments, the respective data signals208are provided to respective data retimers212, which also receive an input clock signal210and which provide the respective data signals208to respective data drivers216at a symbol rate corresponding to the input clock signal210frequency. The data drivers216drive the respective data signals208onto the respective transmission line pairs204at a symbol rate corresponding to the input clock signal210frequency.

In some embodiments, a phase adjuster (not shown) adjusts the phase of the clock signal provided to a respective data retimer212-1or212-2.

In some embodiments, the input clock signal210is provided to a clock driver308, which drivers the first common mode output clock signal onto the first pair204-1of transmission lines and the second common mode output clock signal onto the second pair204-2of transmission lines. In some embodiments, the clock driver308includes a phase offset vernier to compensate for skew between the input clock used for data retiming and the clock transmitted by driver308. In some embodiments, the vernier phase offset is approximately 90 degrees.

Each receiver306receives a transmission signal that includes a differential-mode data signal and a common-mode clock signal. Differential mode extraction circuits226extract the differential-mode data signals from the transmission signals. The extracted data signals are provided to sampling circuits236that sample the extracted data signals.

A common-mode extraction circuit228in each receiver extracts the respective common-mode output clock signal from the respective transmission signal. The first and second extracted output clock signals, with opposite polarity, are provided to a combiner310that combines the extracted output clock signals into a single sampling clock signal. The sampling circuits236-1and236-2in the first and second receivers306-1and306-2are synchronized to the sampling clock signal.

In some embodiments, the combiner310provides the sampling clock signal to a timing circuit. The timing circuit receives the sampling clock signal and provides a clock signal to the first236-1and second236-2sampling circuits. In some embodiments, the timing circuit includes a PLL312or a DLL (not shown). In some embodiments, the timing circuit includes a phase interpolator314coupled to the PLL and to a sampling circuit236to adjust the phase of the clock signal provided to the sampling circuit. In the embodiment shown inFIG. 3, optional phase interpolators314-1and314-2couple the PLL to sampling circuits236-1and236-2, respectively, to adjust the phase of the clock signal provided to the sampling circuits.

In some embodiments, the combiner310provides the sampling clock signal to a clipping amplifier (not shown). The clipping amplifier amplifies the sampling clock signal and provides the amplified sampling clock signal to the sampling circuits236.

In some embodiments, one or more transmitters (e.g.,202or302) and one or more receivers (e.g.,206or306) may be implemented together in a single integrated circuit (i.e., on a single chip).

FIGS. 4A and 4Bare block diagrams of two integrated circuits400-A and400-B, each having a transmitter202and a receiver206, in accordance with some embodiments. Each transmitter202and each receiver206includes components described above with regard toFIGS. 2A and 2B. Integrated circuit400-A may simultaneously transmit a differential-mode data signal and a common-mode clock signal to integrated circuit400-B via a first pair of transmission lines204-1and may receive a transmission signal that includes a differential-mode data signal and a common-mode clock signal from integrated circuit400-B via a second pair of transmission lines204-2. Alternatively, integrated circuit400-A may both transmit and receive signals via a single channel (not shown).

In some embodiments, a clock signal402extracted by the receiver206-B is provided to the transmitter202-B of the same integrated circuit400-B, thus sharing a clock signal between the receiver206-B and the transmitter202-B. Clock sharing between a receiver and a transmitter in an integrated circuit saves power by eliminating the need to generate a transmitter clock, and therefore may be attractive in mobile applications such as cell phones, personal digital assistants (PDAs), and other portable devices.

In some embodiments, instead of a transmitter202and a receiver206, each integrated circuit400-A and400-B has two transmitters302and two receivers306(FIG. 3).

Attention is now directed to methods of transmitting and receiving data.

FIG. 5Ais a flow diagram illustrating a method500of receiving data in accordance with some embodiments. While the method500described below includes operations that appear to occur in a specific order, it should be apparent that the method500can include more or fewer operations, that two or more of the operations can be performed in parallel, and that two or more operations can be combined into a single operation.

A transmission signal is received (502) from a pair of transmission lines. For example, the receiver206receives a transmission signal from a pair of transmission lines204.

A common mode clock signal is extracted (504) from the received transmission signal. For example, the common mode extraction circuit228extracts a common mode clock signal. In some embodiments, the extracted clock signal is amplified (506) (e.g., by a limit amplifier234) and provided to a sampling circuit (e.g.,236). In some embodiments, the timing of the extracted clock signal is adjusted (508) and the adjusted clock signal is provided to the sampling circuit. For example, a PLL (e.g.,244) receives the extracted clock signal and provides a clock signal to the sampling circuit. In some embodiments, adjusting the timing of the extracted clock signal includes adjusting the phase of the extracted clock signal. For example, a phase interpolator adjusts the phase of the extracted clock signal and provides the phase-adjusted extracted clock signal to the sampling circuit.

A differential-mode data signal is extracted (510) from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal. For example, the differential mode extraction circuit226extracts a differential-mode data signal from the received transmission signal. In some embodiments, the extracted data signal has a symbol rate equal (512) to the frequency of the extracted clock signal.

The extracted data signal is sampled (514) (e.g., by the sampling circuit236). The sampling is synchronized to the extracted clock signal. In some embodiments, synchronization of the sampling to the extracted clock signal is achieved by providing the amplified extracted clock signal to the sampling circuit. In some embodiments, synchronization of the sampling to the extracted clock signal is achieved by providing a clock signal output by a PLL (e.g.,244) or by a DLL to the sampling circuit, wherein the input to the PLL or to the DLL is the extracted clock signal. In some embodiments, synchronizing the sampling to the extracted clock signal includes adjusting the phase of the clock signal provided to the sampling circuit. In some embodiments, as shown inFIGS. 2A and 2B, the extracted data signal and the extracted clock signal are extracted simultaneously.

FIG. 5Bis a flow diagram illustrating a method530of receiving data in accordance with some embodiments. While the method530described below includes operations that appear to occur in a specific order, it should be apparent that the method530can include more or fewer operations, that two or more of the operations can be performed in parallel, and that two or more operations can be combined into a single operation.

A first transmission signal is received (532) from a first pair of transmission lines (e.g.,204-1;FIG. 3) and a second transmission signal is received (534) from a second pair of transmission lines (e.g.,204-2).

Respective first and second common-mode clock signals are extracted (536) from the respective first and second transmission signals. The first extracted clock signal has a first polarity and the second extracted clock signal has a second polarity opposite to the first polarity. For example, common-mode extraction circuits228-1and228-2(FIG. 3) extract first and second common-mode clock signals that have opposite polarities.

The first and second extracted clock signals are combined (538) into a single sampling clock signal. For example, the combiner310combines the first and second common-mode clock signals extracted by the common-mode extraction circuits228-1and228-2. In some embodiments, the sampling clock signal is amplified (540) and the amplified sampling clock signal is provided to first and second sampling circuits (e.g.,236-1and236-2). In some embodiments, the timing (e.g., the phase) of the sampling clock signal is adjusted (542) and the adjusted sampling clock signal is provided to the first and/or second sampling circuits. For example, a PLL312and/or a phase interpolator314adjust the timing of the sampling clock signal provided to a sampling circuit.

First and second differential-mode data signals are extracted (544) from the respective first and second transmission signals. For example, the first and second differential mode extraction circuits226-1and226-2(FIG. 3) extract respective first and second differential-mode data signals from the respective first and second transmission signals. In some embodiments, the first and second extracted data signals have a symbol rate (546) corresponding to a frequency of the first and second extracted clock signals. In some embodiments, the first and second extracted data signals have a symbol rate equal to a frequency of the first and second extracted clock signals.

The respective first and second extracted data signals are sampled (548). For example, the first and second sampling circuits236-1and236-2sample the respective first and second extracted data signals. The sampling is synchronized to the sampling clock signal. In some embodiments, as shown inFIG. 3, the first and second extracted data signals and the first and second extracted clock signals are extracted simultaneously.

FIG. 6Ais a flow diagram illustrating a method600of transmitting data in accordance with some embodiments. While the method600described below includes operations that appear to occur in a specific order, it should be apparent that the method600can include more or fewer operations, that two or more of the operations can be performed in parallel, and that two or more operations can be combined into a single operation.

A data signal and a clock signal are obtained (602). For example, the transmitter202obtains for transmission a data signal208and a clock signal210(FIG. 2A).

In some embodiments, the clock signal is provided (604) to a data retimer (e.g.,212). The data retimer provides the data signal to a data driver (e.g.,216) at a symbol rate corresponding to the clock signal frequency. In some embodiments, the data retimer provides the data signal to a data driver at a symbol rate equal to the clock signal frequency.

In some embodiments, the phase of the clock signal provided to the data retimer is adjusted (606). For example, the phase adjuster214receives the clock signal210and provides a phase-adjusted clock signal to a data retimer212. In some embodiments, the phase adjuster214is a phase interpolator. In some embodiments, the phase adjuster214is a PLL or a DLL.

The data signal is driven (608) onto a pair transmission lines (e.g.,204) in a differential mode (e.g., by the data driver216). The data signal has a symbol rate corresponding to the clock signal frequency. In some embodiments, the data signal has a symbol rate equal to the clock signal frequency.

The clock signal is driven (610) onto the pair of transmission lines in a common mode (e.g., by the clock driver218), such that the clock signal and the data signal are driven onto the pair of transmission lines simultaneously.

FIG. 6Bis a flow diagram illustrating a method630of transmitting data in accordance with some embodiments. While the method630described below includes operations that appear to occur in a specific order, it should be apparent that the method630can include more or fewer operations, that two or more of the operations can be performed in parallel, and that two or more operations can be combined into a single operation.

A first data signal, a second data signal, and an input clock signal are obtained (632). For example, transmitters302-1and302-2obtain a first data signal208-1, a second data signal208-2, and a clock signal210(FIG. 3).

In some embodiments, the input clock signal is provided (634) to first and second data retimers (e.g.,212-1and212-2). The first and second data retimers provide the respective first and second data signals to respective first and second data drivers at a symbol rate corresponding to the input clock signal frequency. In some embodiments, the first and second data retimers provide the respective first and second data signals to respective first and second data drivers at a symbol rate equal to the input clock signal frequency.

In some embodiments, the phase of the clock signal provided to the first and/or second data retimers is adjusted (636).

The first data signal is driven (638) onto a first pair of transmission lines in a differential mode and the second data signal is driven (640) onto a second pair of transmission lines in a differential mode. For example, the first and second data drivers216-1and216-2drive the respective first and second data signals onto the respective first and second transmission line pairs204-1and204-2in a differential mode.

A first output clock signal is driven (642) onto the first pair of transmission lines (e.g.,204-1) in a common mode (e.g., by the clock driver308). The first output clock signal has a first polarity. A second output clock signal is driven (644) onto the second pair of transmission lines (e.g.,204-2) in a common mode (e.g., by the clock driver308). The second output clock signal has a second polarity opposite to the first polarity. The first data signal, the second data signal, the first output clock signal, and the second output clock signal are driven onto the transmission lines simultaneously.

In some embodiments, the first data signal and the second data signal each has a symbol rate (646) corresponding to a frequency of the first output clock signal and of the second output clock signal. In some embodiments, the first data signal and the second data signal each has a symbol rate equal to a frequency of the first output clock signal and of the second output clock signal.

The method630illustrated inFIG. 6Binvolves transmitting two data signals, each in a differential mode on a respective pair of transmission lines, while a clock signal is effectively transmitted in a differential mode on two pairs of transmission lines, wherein each pair transmits a polarity of the clock signal in a common mode. In a complementary method, clock signals are transmitted in a differential mode on respective pairs of transmission lines and a data signal is effectively transmitted in a differential mode on two pairs of transmission lines, wherein each pair transmits a polarity of the data signal in a common mode.

Attention is now directed to embodiments in which a clock signal and a data signal are simultaneously transmitted over a channel, wherein the clock signal is transmitted at a frequency greater than or equal to the symbol rate of the data signal.

FIGS. 7A-7Cdepict prophetic transmit signal spectrums700(FIG. 7A),720(FIG. 7B), and740(FIG. 7C) for three cases of a data signal and a clock signal simultaneously transmitted over a channel in accordance with some embodiments. The transmit signal spectrums700,720, and740are represented by the single-ended power spectral densities (PSD)702as a function of frequency704, where single-ended PSD702is measured in decibels per hertz (dB/Hz) and frequency704is measured in gigahertz (GHz). In some embodiments, the channel includes one or more transmission lines, such as a pair of transmission lines.

The data signal706has a symbol period T and a symbol rate 1/T710. In some embodiments, the clock signal has a frequency equal to an integer multiple of the symbol rate, where the integer is greater than one. For example, in the transmit signal spectrum700, the clock signal708has a frequency712equal to twice the symbol rate710. In some embodiments, the clock signal has a frequency equal to a non-integer multiple of the symbol rate. For example, in the transmit signal spectrum720, the clock signal722has a frequency724equal to 1.5 times the symbol rate710. In some embodiments, the clock signal has a frequency equal to an integer multiple of the symbol rate, where the integer is equal to one. For example, in the transmit signal spectrum740, the clock signal742has a frequency equal to the symbol rate710.

FIG. 7Dillustrates waveforms associated with simultaneously transmitting data and clock signals over a channel in accordance with some embodiments. In a first example, a waveform750corresponds to a particular polarity of a differential-mode data signal and a waveform752corresponds to a particular polarity of a differential-mode clock signal. The data signal and clock signal are simultaneously transmitted over a pair of transmission lines, such that the symbol rate equals the clock frequency. Other implementations may choose to transmit simultaneously over another propagation mode such as common-mode. A waveform756results on the first transmission line of the pair and a waveform760results on the second transmission line of the pair. In this example, data transitions are phase-aligned with rising clock edges. A receiver can recover the clock and data waveforms750and752from the transmitted waveforms756and760, as described below. In some embodiments, a receiver's sampling of a data bit in a received data signal is timed using a clock edge with which the data bit was aligned for transmission.

A second example includes the waveform750corresponding to the differential-mode data signal and a waveform754corresponding to a particular polarity of a differential-mode clock signal. The data and clock signals are simultaneously transmitted over a pair of transmission lines. A waveform758results on the first transmission line of the pair and a waveform762results on the second transmission line of the pair. In this example, rising clock edges are phase-aligned with the center of data bits. Timing data and clock signals such that rising clock edges are approximately phase-aligned with the center of data bits is desirable for receiver sampling because it provides set-up time for data bits prior to sampling.

In the examples ofFIG. 7D, the clock and data waveforms have equal amplitudes. In other examples, the amplitudes may be distinct. For example, inFIG. 7E, the amplitude of the data waveform770is twice the amplitude of the clock waveform772, resulting in waveforms774and776on the transmission line pair. (Waveforms774and776are not drawn to scale with respect to waveforms770and772.) In other examples, the clock frequency may exceed the symbol rate.FIGS. 7D and 7Eare examples of different amplitude ratios between transmitted differential and common-mode signals. It follows from examples7D and7E that the ratio of the differential and common-mode signal may be selected to have some fractional amplitude relationship with the possibility of either signal being the larger, as conditions dictate.

FIG. 8Ais a block diagram of a data communications system800in accordance with some embodiments. The data communications system800includes a transmitter802, a pair of transmission lines204, and a receiver806.

The transmitter802receives for transmission a data signal808and a clock signal810. A clock driver814drives the clock signal810via interfaces219onto the pair of transmission lines204. In some embodiments, the clock signal810is a single tone, or sinusoidal, wave. In some embodiments, the interfaces219include pins, balls, or other electrical contacts on a semiconductor package.

The clock signal810has a first frequency (i.e., the frequency of the clock signal). A timing circuit812receives the clock signal810and outputs a symbol clock that has a second frequency, wherein the first frequency is a multiple n of the second frequency. In some embodiments, the multiple n is an integer multiple; in some other embodiments, the multiple n is a non-integer multiple equal to a ratio of whole-numbers. In some embodiments, the timing circuit812includes a clock divider813.

In some embodiments, the timing circuit812includes a phase adjuster214. For example, the output of the timing circuit812(e.g., a clock divider813) is coupled to the input of the phase adjuster214to adjust the phase of the symbol clock. In some embodiments, the phase adjuster214is a phase interpolator. The phase adjuster adjusts the phase of the symbol clock and provides the phase-adjusted symbol clock to a data retimer212.

Alternately, in some embodiments, a phase adjuster is coupled to the input of a clock divider (not shown). The phase adjuster receives the clock signal810, adjusts the phase of the clock signal, and provides the phase-adjusted clock signal to the input of the clock divider, which generates the symbol clock.

The data retimer212receives the data signal208and provides the data signal to the data driver216at a symbol rate corresponding to the frequency of the symbol clock. The data driver216drives the data signal via interfaces219onto the pair of transmission lines204with a symbol rate corresponding to the frequency of the symbol clock. In some embodiments, the data driver216drives the data signal onto the pair of transmission lines204using non-return-to-zero (NRZ) formatting, such that a value of the data signal does not transition between successive symbol clock periods if the values of successive signal points corresponding to the successive symbol clock periods are equal. The receiver806can extract the data signal, even in the absence of transitions, by extracting the clock signal and generating a symbol clock to time sampling of the data signal, as described below with regard to the receiver806.

In some embodiments, the data driver216transmits the data signal in a differential mode. In some embodiments, the clock driver810transmits the clock signal in a differential mode. In some other embodiments, the clock signal is transmitted in a common mode.

In some embodiments, the data driver and clock driver have programmable drive strengths, as shown for data driver834and clock driver836of transmitter832in data communications system830(FIG. 8B). In some embodiments, the drive strengths (i.e., output swings) for the data driver834and the clock driver836are complementary: if the data driver834has a normalized drive strength of a, the clock driver836has a normalized drive strength of 1-α. The combined output swing of the data driver834and clock driver836thus remains substantially constant and the respective drive strengths of the data driver834and the clock driver836can be traded off against each other to optimize signal quality. Increasing the drive strength of the clock driver836improves reception of the clock signal by the receiver806, reducing jitter and improving timing margin for reception of the data signal. Increasing the drive strength of the clock driver834improves voltage margin for reception of the data signal by the receiver806.

The receiver806receives via interfaces221a transmission signal that includes the data signal and the clock signal. In some embodiments, the interfaces221include pins, balls, or other electrical contacts on a semiconductor package. A data extraction circuit824extracts the data signal from the received transmission signal. The extracted data signal is provided to a sampling circuit236that samples the extracted data signal.

A clock extraction circuit816extracts the clock signal from the received transmission signal. The extracted clock signal has a first frequency (i.e., the frequency of the extracted clock signal).

A timing circuit822receives the extracted clock signal and generates a symbol clock having a second frequency. The first frequency is a multiple n of the second frequency, wherein the multiple n is greater than one. In some embodiments, the timing circuit822includes a clock divider823. The symbol clock is provided to the sampling circuit236, which is synchronized to the symbol clock.

In some embodiments, clock extraction circuitry includes filter circuitry to substantially filter out the clock signal from a data signal path to the sampling circuit236and to substantially filter out the data signal from a clock signal path to the timing circuit822. The filter circuitry has a center frequency approximately equal to the first frequency. Thus, the filter circuitry acts as a band-reject filter on a data signal path to the sampling circuit236and acts as a band-pass filter for a clock signal path to the timing circuit822. For example, the clock extraction circuit816includes an LC network818coupled to a buffer820. The LC network818is a resonant network with a resonant frequency approximately equal to the first frequency that substantially filters out the clock signal from the signal provided to the data extraction circuit824and substantially filters out the data signal from the signal provided to the buffer820and to the timing circuit822. Thus, the resonant network substantially filters out the clock signal from a data signal path to the sampling circuit236, and substantially filters out the data signal from a clock signal path to the timing circuit822. In some embodiments, the resonant network acts as a band-reject filter on a data signal path to the sampling circuit236, and acts as a band-pass filter for a clock signal path to the timing circuit822. In some embodiments the LC network may vary from the one shown in816. For example, the positions of the L and C elements may be reversed.

In some embodiments, the receiver806includes buffers222to isolate the receiver circuitry from the pair of transmission lines204. In some embodiments, termination resistors224terminate the pair of transmission lines204.

In some embodiments, one or more transmitters802and one or more receivers806may be implemented together in a single integrated circuit (i.e., on a single chip), in a manner analogous to the integrated circuit400ofFIGS. 4A and 4B. For example, a symbol clock generated by the timing circuit822may be provided to a transmitter (e.g., provided as a clock signal810to a transmitter802) on the same chip as the receiver806.

In some embodiments, receiver circuitry includes a Quality of Signal (QOS) evaluation block850, as shown for receiver842inFIGS. 8C and 8D. The QOS evaluation block850evaluates voltage and timing margins of data signals received by the receiver842. In some embodiments, the QOS evaluation block850provides instructions to the transmitter832to adjust the drive strengths of the programmable data driver834and clock driver836in the transmitter832, to improve or optimize timing or voltage margins. In some embodiments, the QOS evaluation block850includes QOS logic864, a digital-to-analog converter856, a combiner858, a sampling circuit860, a variable delay866, and an XOR gate862. The QOS evaluation block850may also include a clock divider823.

The extracted data signal846provided to the sampling circuit236is also provided to the combiner858, which adds a voltage offset received from the DAC856as specified by the QOS logic864. The combiner858provides the offset data signal to the sampling circuit860, which samples the offset data signal. The extracted clock signal848provided to the timing circuit822is also provided to a clock divider823; the divided clock signal is provided to a variable delay circuit866having a variable delay specified by the QOS logic864. Alternately, the output of the timing circuit822is provided to the variable delay circuit866. The variable delay circuit866provides the delayed clock signal to the sampling circuit860, which is synchronized to the delayed clock signal. The outputs of the sampling circuits236and860are provided to the XOR gate862, which acts as a comparator that compares the two outputs and provides the result of the comparison to the QOS logic864.

If the outputs of the sampling circuits236and860agree, the sampling circuit860is presumed to be sampling within an eye opening in a plot of signal voltage level vs. time for the receiver842. The eye opening corresponds to a set of combinations of signal voltage levels and sampling times for which received 1's can be distinguished from received 0's. If the outputs of the sampling circuits236and860do not agree, the sampling circuit860is presumed to be sampling outside of the eye opening. In some embodiments, the outputs of the sampling circuits236and860are considered to agree if at least a minimum percentage (e.g., 99.9%) of respective samples of the sampling circuits236and860are equal (i.e., are both 1 or 0) for a particular combination of voltage offset and delay value, and are considered not to agree if less than the minimum percentage of respective samples are equal. The QOS logic864thus can map out the eye opening by varying the voltage offset and delay value and comparing the outputs of the sampling circuits236and860for various combinations of voltage offset and delay values.

FIGS. 8E and 8Fillustrate eye openings876and884in plots870and882of voltage level872vs. time874in accordance with some embodiments. The time874is shown as varying between zero and the symbol period T. The center of the eye opening876has a height greater than a defined minimum voltage margin878, but has a width less than a defined minimum timing margin880. The center of the eye opening884has a width greater than the minimum timing margin880, but has a height less than the minimum voltage margin878. In some embodiments, the minimum voltage margin878and minimum timing margin880are determined to ensure that the bit-error rate (BER) for the receiver842does not exceed a predefined maximum BER.

In some embodiments, the QOS logic864communicates with the transmitter832to adjust the drive strengths of the programmable data driver834and clock driver836based on characterization of the eye diagram for the receiver842. If characterization reveals that the height of the eye opening is insufficient, indicating a lack of voltage margin (e.g., for eye opening884), then the drive strength of the data driver834is increased (i.e., a is increased). If characterization reveals that the width of the eye opening is insufficient, indicating a lack of timing margin (e.g., for eye opening876), then the drive strength of the clock driver836is increased (i.e., a is decreased). Iterative characterization of voltage and timing margins and adjustment of drive strength is performed until the characterized voltage and timing margins exceed the respective minimum voltage and timing margins.

In some embodiments, the QOS logic864communicates with the programmable drivers834and836via a backchannel844, which may include a single transmission line or a pair of transmission lines. In some embodiments, the QOS logic864communicates with the programmable drivers834and836via the transmission line pair204: for example, a transmitter located in an integrated circuit that also includes the receiver842drives data from the QOS logic864onto the transmission line pair204.

In some embodiments, the QOS evaluation block850may be used to evaluate signals from receivers206(FIG. 2A),242(FIG. 2B), or306(FIG. 3). For example, the data signal from a differential mode extraction circuit226, the sampled data from the corresponding sampling circuit236, and the clock signal provided by the limit amplifier234, PLL244, or PLL312are provided to the QOS evaluation block850in a manner analogous to that shown inFIG. 8D.

FIG. 9Ais a flow diagram illustrating a method900of transmitting data in accordance with some embodiments. While the method900described below includes operations that appear to occur in a specific order, it should be apparent that the method900can include more or fewer operations, that two or more of the operations can be performed in parallel, and that two or more operations can be combined into a single operation.

A clock signal is obtained (902). The clock signal has a first frequency. For example, the transmitter802(FIG. 8) obtains the clock signal810.

The clock signal is driven (904) onto one or more transmission lines (e.g., by the clock driver814or836). In some embodiments, the clock signal is driven onto a pair of transmission lines in a differential mode (906).

A symbol clock signal is generated (908) having a second frequency. In some embodiments, a timing circuit receives the clock signal and generates the symbol clock. In some embodiments, the timing circuit812includes a clock divider813(e.g., the clock divider shown inFIG. 8). The first frequency is a multiple of the second frequency, where the multiple is greater than one. In some embodiments, the first rate is an integer multiple of the second rate (910), where the integer is greater than one.

In some embodiments, the phase of the symbol clock is adjusted (912). For example, the timing circuit includes a phase adjuster (e.g.,214) coupled to the output of a clock divider (e.g.,812) to adjust the phase of the symbol clock. In some embodiments, the phase of the clock signal is adjusted and the phase-adjusted clock signal is provided to a clock divider to generate the symbol clock.

A data signal is obtained (914). For example, the transmitter802obtains for transmission the data signal808. The data signal is driven (916) onto the one or more transmission lines at a symbol rate corresponding to the second frequency (e.g., by the data driver216). The data signal and the clock signal are driven onto the one or more transmission lines simultaneously. In some embodiments, the data signal is driven onto a pair of transmission lines in a differential mode (918). In some embodiments, the data signal is driven in a non-return-to-zero (NRZ) format (920).

FIG. 9Bis a flow diagram illustrating a method930of receiving data in accordance with some embodiments. While the method930described below includes operations that appear to occur in a specific order, it should be apparent that the method930can include more or fewer operations, that two or more of the operations can be performed in parallel, and that two or more operations can be combined into a single operation.

A data signal and a clock signal superimposed on the data signal are simultaneously received (932). The clock signal has a first frequency. For example, the receiver806simultaneously receives a data signal and a clock signal superimposed on the data signal.

The clock signal is extracted (934) (e.g., by a clock extraction circuit816). In some embodiments, the data signal is substantially filtered out (936) from a clock signal path to the timing circuit. For example, a resonant network (e.g., LC network818) substantially filters out the data signal from a clock signal path to the timing circuit.

A symbol clock is generated (938) having a second frequency. The first frequency is a multiple of the second frequency, where the multiple is greater than one. In some embodiments the clock signal is divided (940); the divided clock signal has a frequency corresponding to a specified fraction of the first frequency. For example, a clock divider (e.g.,823) or other timing circuit divides the clock signal to generate the symbol clock.

The data signal is sampled (942) (e.g., by the sampling circuit236). The sampling is synchronized to the symbol clock.

In some embodiments, a band-reject filter coupled to the sampling circuit substantially filters out the clock signal from the signal provided to the sampling circuit. In some embodiments, a resonant network (e.g., LC network818) substantially filters out the clock signal from the signal provided to the sampling circuit.

In operation908of method900(FIG. 9A) and in operation938of method930(FIG. 9B), the ratio of the first frequency to the second frequency is described as being greater than one. In some embodiments, however, the ratio of the first frequency to the second frequency is equal to one. Similarly, in some embodiments, the timing circuit812(FIG. 8A) receives the clock signal810and outputs a symbol clock that has a second frequency equal to the frequency of the received clock signal810. Likewise, the timing circuit822may output a symbol clock that has a second frequency equal to the frequency of the extracted clock signal.

FIG. 10is a block diagram of an embodiment of a system1000for storing computer readable files containing software descriptions of circuits for implementing transmitters and receivers in accordance with some embodiments. The system1000may include at least one data processor or central processing unit (CPU)1010, memory1014, and one or more signal lines or communication busses1012for coupling these components to one another. Memory1014includes high-speed random access memory, such as DRAM, SRAM, DDR RAM or other random access solid state memory devices; and may include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid state storage devices. Memory1014may optionally include one or more storage devices remotely located from the CPU(s)1010. In some embodiments, memory1014stores in one or more of the previously mentioned memory devices a circuit compiler1016, transmitter circuit descriptions1018, and receiver circuit descriptions1042. The circuit compiler1016, when executed by a processor such as CPU(s)1010, processes one or more circuit descriptions to synthesize one or more corresponding circuits.

In some embodiments, the transmitter circuit descriptions1018include circuit descriptions for a clock driver1020, a data driver1022, a data retimer1024, termination resistors1026, a phase adjuster1028, a timing circuit1034, and a transmitter interface1040. In some embodiments, the circuit description for the phase adjuster1028includes circuit descriptions for a phase interpolator1030and for a PLL or DLL1032. In some embodiments, the circuit description for the timing circuit1034includes circuit descriptions for a clock divider1036and for a phase adjuster1038.

In some embodiments, the receiver circuit descriptions1042include circuit descriptions for a receiver interface1044, a differential mode extraction circuit1046, a common mode extraction circuit1048, a sampling circuit1056, a limit amplifier1058, a timing circuit1060, buffers1068, termination resistors1070, a combiner1072, a data extraction circuit1074, and a clock extraction circuit1076. In some embodiments, the circuit description for the common mode extraction circuit1048includes circuit descriptions for buffers1050, a combiner1052, and a band-pass filter1054. In some embodiments, the circuit description for the timing circuit1060includes circuit descriptions for a PLL or DLL1062, a phase interpolator1064, and a clock divider1066. In some embodiments, the circuit description for the clock extraction circuit1076includes circuit descriptions for a band-pass filter1078, a resonant network (e.g., an LC network)1080, and a buffer1082.