Memory Device, System Having the Same, and Method for Manufacturing the Same

A memory device includes a memory cell array including normal memory cells arranged in a form of matrix, and a sense amplifier array including sense amplifiers each amplifying a signal output from each of the normal memory cells. Some of the sense amplifiers have different sizes so that they may have different sense capabilities depending on a layout location. The size is determined according to at least one of a channel length and a channel width of a MOS transistor included in each of the some sense amplifiers.

DETAILED DESCRIPTION OF THE EMBODIMENTS

It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless indicated otherwise, these terms are only used to distinguish one element from another. For example, a first chip could be termed a second chip, and, similarly, a second chip could be termed a first chip without departing from the teachings of the disclosure.

Embodiments described herein will be described referring to plan views and/or cross-sectional views by way of ideal schematic views. Accordingly, the exemplary views may be modified depending on manufacturing technologies and/or tolerances. Therefore, the disclosed embodiments are not limited to those shown in the views, but include modifications in configuration formed on the basis of manufacturing processes. Therefore, regions exemplified in figures have schematic properties, and shapes of regions shown in figures exemplify specific shapes of regions of elements, and the specific properties and shapes do not limit aspects of the invention.

Terms such as “same,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes.

Embodiments disclosed herein relate to a semiconductor device, and more particularly, to a memory device including a sense amplifier array, a system having the same, and a method for manufacturing the same.

The memory device includes a memory cell array for storing data, and an access control circuit for controlling an access operation, e.g., a write operation or a read operation, on the memory cell array.

The access control circuit includes decoding circuits decoding address signals, sense-amplifiers sensing and amplifying data stored in memory cells of the memory cell array based on signals output from the decoding circuits, transmission lines transmitting signals output from the sense amplifiers, and output drivers outputting signals transmitted through the transmission lines.

To read correctly data stored in memory cells of a memory cell array, attributes of sense amplifiers should have certain characteristics.

As used herein, ‘process variation’ refers to naturally occurring variation according to attributes, e.g., a channel length, a channel width, and/or oxide thickness, of an element, e.g., a transistor, when manufacturing a memory device, e.g., an integrated circuit. Process variation may cause circuit elements to vary slightly from their designed shape, size, structure, etc. Due to process variation, certain operations carried out by an element may be affected. In some cases, therefore, process variation can cause a semiconductor device to behave in an unpredictable or undesirable manner. As described further below, in some embodiments, certain circuit elements can be designed to have intentionally different characteristics from other elements (e.g., a larger size), to counteract the effects of process variation, particularly in edge sense amplifiers.

FIG. 1is a plan view of a wafer including a memory device according to an example embodiment. Referring toFIG. 1, a wafer10includes a plurality of memory devices, e.g., a plurality of memory chips20. Here, a memory device20may be called a die.

FIG. 2Ais a block diagram illustrating an example embodiment of the memory device illustrated inFIG. 1.

The memory device20includes a memory cell array100, a row decoder110, a sense amplifier array120, a column decoder130, an input/output gate circuit140, a control logic circuit150, and an output driver block160.

The memory cell array100includes normal memory cells101arranged in a form of matrix. Each of the normal memory cells101is connected to one of word lines WL1to WLn, where n is a natural number, and one of bit lines BL1to BLm, where m is a natural number.

The normal memory cell is distinguished from a redundant memory cell for replacing a defective memory cell. For example, the memory cell array100is distinguished from a redundant memory cell array including a redundant memory cell.

Each of the bit lines BL1to BLm may include a bit line and a complementary bit line.

Each of the normal memory cells101may be embodied in a volatile memory cell or a non-volatile memory cell.

A volatile memory cell may be embodied, for example, in a dynamic random access memory (DRAM), a static random access memory (SRAM), a thyristor RAM (T-RAM), a zero capacitor RAM (Z-RAM), or a twin transistor RAM (TTRAM).

A non-volatile memory cell may be embodied, for example, in an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin-transfer torque MRAM, a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a Phase change RAM (PRAM), a resistive RAM (RRAM), a Nanotube RRAM, a polymer RAM (PoRAM), a Nano floating gate memory (NFGM), a holographic memory, a molecular electronics memory device, or an insulator resistance change memory. The non-volatile memory cell may store one bit or more.

The row decoder110may decode a row address XADD, and activate a corresponding word line among the word lines WL1to WLn or supply a word line voltage to the corresponding word line based on a decoding result.

A sense amplifier array120includes sense amplifiers121-1through121-membodied in a form of an array. Each of the sense amplifiers121-1to121-mmay sense and amplify a signal output from a set of the normal memory cells101. For example, in one embodiment, each sense amplifier can sense and amplify signals output through one of the bit lines BL1to BLm. Here, each of the sense amplifiers121-1through121-mis a sense amplifier configured for normal operation, and can be distinguished from a dummy sense amplifier embodied in other regions, such as regions outside a region in which the normally operating sense amplifiers are located. In one embodiment, dummy sense amplifiers do not operate but may have the same structure as the sense amplifiers121-1through121-m(e.g., they may include the same transistor structure, but without being electrically connected to other circuitry).

According to an example embodiment, each of the sense amplifiers121-1to121-mmay be embodied in a differential sense amplifier.

A column decoder130may decode a column address YADD and generate column selection signals CSL1to CSLm based on a decoding result. Based on the column selection signals CSL1to CSLm, an input/output gate circuit140may control connection between the sense amplifiers121-1to121-membodied in the sense amplifier array120and output drivers (not shown) embodied in an output driver block160.

A control logic circuit150may generate control signals, e.g., XADD, YADD, LANG, LAPG and EQ used for an access operation, e.g., a write operation or a read operation, on the memory cell array100.

FIG. 2Bis a block diagram illustrating another example embodiment of the memory device illustrated inFIG. 1. Except for a plurality of dummy sense amplifier regions120A and120B, a structure and an operation of the memory device20illustrated inFIG. 2Aare substantially the same as a structure and an operation of a memory device20-1illustrated inFIG. 2B.

A dummy sense amplifier region120A including at least one dummy sense amplifier is embodied at the left side of the sense amplifier array120, and a dummy sense amplifier region120B including at least one dummy sense amplifier is embodied at the right side of the sense amplifier array120.

At least one dummy sense amplifier embodied in each of the plurality of dummy sense amplifier regions120A and120B is embodied to secure uniformity of pattern of the normal sense amplifiers121-1to121-membodied in the sense amplifier array120.

Accordingly, at least one dummy sense amplifier embodied in each of the plurality of dummy sense amplifier regions120A and120B does not operate normally, unlike the normal sense amplifiers121-1to121-membodied in the sense amplifier array120. As such, the at least one dummy sense amplifier may not perform a sense amplification operation.

FIG. 3is a plan view illustrating an example embodiment of the sense amplifier array illustrated inFIG. 2Aor2B. Some of sense amplifiers121-1to121-mare embodied so that they may have different characteristics (e.g., different sizes) to have different sensing capabilities according to layout location (e.g., sense amplifier121-1may have different characteristics from sense amplifier121-2, and sense amplifier121-(m-1) may have different characteristics from sense amplifier121-m.

A size of a sense amplifier as discussed herein may refer to a layout size of the sense amplifier. For example, in one embodiment, a size of a sense amplifier is determined based on the channel length of at least one MOS transistor included in the sense amplifier and/or the channel width of at least one MOS transistor included in the sense amplifier.

As illustrated inFIG. 3, in one embodiment, an average size of one or more first amplification elements included in each of sense amplifiers121-1and121-m(hereinafter referred to as “edge sense amplifiers”) laid out or embodied at both edges of a sense amplifier array120-1is greater than an average size of one or more second amplification elements included in each of the rest of the sense amplifiers of the array (hereinafter referred to as ‘inner sense amplifiers).

For example, an average size of one or more first amplification elements may be greater than an average size second amplification elements by more than 10%.

The one or more first amplification elements or the one or more second amplification elements may include at least one P-channel MOS transistor and at least one N-channel MOS transistor. In addition, the first amplification element or the second amplification element may mean a sense amplifier itself according to an example embodiment. For example, each sense amplifier of a sense amplifier array may include a plurality of transistors configured to form the sense amplifier. In certain sense amplifiers (e.g., inner sense amplifiers) the transistors that form the sense amplifier may have a first average size (e.g., average size per transistor based on the sizes of all of the transistors that form the sense amplifier). In other sense amplifiers (e.g., edge sense amplifiers) the transistors that form the sense amplifier may have a second average size (e.g., average size per transistor based on the sizes of all of the transistors that form the sense amplifier). As described below, the first size may be different from the second size (e.g., smaller).

In order for the different sense amplifiers to have different sizes, in one embodiment, attributes (e.g., channel length, channel width, and/or oxide thickness) of MOS transistors included in each of the edge sense amplifiers121-1and121-mare embodied to be intentionally different from attributes (e.g., channel length, channel width and/or oxide thickness) of MOS transistors included in each of the inner sense amplifiers121-2to121-(m-1). For example, the attributes can be made significantly different to counteract larger process variations where they occur.

For convenience of explanation, it is illustrated inFIG. 3that the number of the edge sense amplifiers121-1to121-mis two; however, the number may be four or more according to an example embodiment. For example the closest two sense amplifiers to each edge of the sense amplifier array120-1may include the intentionally different sizes. In other embodiments, there may be multiple rows of sense amplifier arrays within a memory device, and each row may include edge sense amplifiers.

In one embodiment, each of the edge sense amplifiers121-1and121-mhas substantially the same structure and layout, and each of the inner sense amplifiers121-2to121-(m-1) has substantially the same structure and layout. Moreover, in one embodiment, channel width W of each MOS transistor included in each sense amplifier121-1to121-mis substantially the same. Here, ‘substantially the same’ may mean identity where process variation is considered.

In one embodiment, an average value of channel length (or length of a gate electrode corresponding to the channel length) of each MOS transistor P11, P21, N11, N21, P1m,P2m,N1m,N2m,included in each of the edge sense amplifiers121-1and121-m,i.e., a first average value L1, is greater than an average value of channel length (or length of a gate electrode corresponding to the channel length) of each MOS transistor, which is included in each of the inner sense amplifiers121-2to121-(m-1), i.e., a second average value L2. For example, the transistors P11, P21, N11, and N21that make up a first edge sense amplifier121-1may have a first average channel length among those transistors, and the transistors that make up a first inner sense amplifier121-2may have a second average channel length among those transistors. The first channel length may be greater than the second channel length. Alternatively, or additionally, when the entire sense amplifier array is taken as a whole, the average channel length per transistor for all of the transistors that form the edge sense amplifiers may be greater than the average channel length per transistor for all of the transistors that form the inner sense amplifiers.

In one embodiment, the first average value L1may be greater than the second average value L2by 10% or more. The value of 10% is exemplary only. In certain embodiments, an intentional average value difference may be selected to be an amount greater than any expected process variation, to ensure that all edge sense amplifiers have greater average channel length than all inner sense amplifiers. For example, the above value of 10% may be used when a known process variation is as high as +/−4%. However, should a known process variation only cause variations of, for example, +/−2%, then an intentional average size increase less than 10% may be used (e.g., 5%). In one embodiment, each transistor of the edge sense amplifiers121-1to121-mhas a larger size than any transistor of the inner sense amplifiers121-2to121-(m-1), by the designated percentage (e.g., 10%). In one embodiment, a design parameter may be set such that even after process variations are accounted for, the average values, or the transistor sizes discussed above in the edge sense amplifiers are at least a certain percentage (e.g., 10%) larger than the average values or transistor sizes of the inner sense amplifiers.

FIG. 4is a plan view illustrating another example embodiment of a sense amplifier array illustrated inFIG. 2Aor2B. For convenience of explanation, it is illustrated inFIG. 4that the number of the edge sense amplifiers121-1and121-mis two; however, it can be four or more according to other example embodiments.

In a sense amplifier array120-2, each of the edge sense amplifiers121-1and121-mhas substantially the same layout and structure, and each of the inner sense amplifiers121-2to121-(m-1) has substantially the same layout and structure. Additionally, channel length L of each MOS transistor included in each sense amplifier121-1to121-mis substantially the same. Here, ‘substantially the same’ may mean identity where a process variation is considered.

In one embodiment, an average value, i.e., a first average value W1, of channel width (or width of a source/drain region corresponding to the channel width) of each MOS transistor P11, P21, N11, N21, P1m,P2m,N1m,and N2mincluded in each of the edge sense amplifiers121-1and121-mis greater than an average value, i.e., a second average value W2, of channel width (or width of a gate electrode corresponding to the channel width) of each MOS transistor included in each of the inner sense amplifiers121-2to121-(m-1). For example, the transistors P11, P21, N11, and N21that make up a first edge sense amplifier121-1may have a first average channel width among those transistors, and the transistors that make up a first inner sense amplifier121-2may have a second average channel width among those transistors. The first channel width may be greater than the second channel width. Alternatively, or additionally, when the entire sense amplifier array is taken as a whole, the average channel width per transistor for all of the transistors that form the edge sense amplifiers may be greater than the average channel width per transistor for all of the transistors that form the inner sense amplifiers.

In one embodiment, the first average value W1may be greater than the second average value W2by 10% or more, for example. The value of 10% is exemplary only. In certain embodiments, an intentional average value difference may be selected to be an amount greater than any expected process variation, to ensure that all edge sense amplifiers have greater average channel width than all inner sense amplifiers. For example, the above value of 10% may be used when a known process variation is as high as +/−4%. However, should a known process variation only cause variations of, for example, +/−2%, then an intentional average size increase less than 10% may be used (e.g., 5%). In one embodiment, each transistor of the edge sense amplifiers121-1to121-mhas a larger size than any transistor of the inner sense amplifiers121-2to121-(m-1), by the designated percentage (e.g., 10%). In one embodiment, a design parameter may be set such that even after process variations are accounted for, the average values, or the transistor sizes discussed above in the edge sense amplifiers are at least a certain percentage (e.g., 10%) larger than the average values or transistor sizes of the inner sense amplifiers.

FIG. 5is a plan view illustrating still another example embodiment of the sense amplifier array illustrated inFIG. 2Aor2B.

As illustrated inFIG. 5, an average value L1of a channel length of each MOS transistor P11, P21, N11, N21, P1m,P2m,N1mand N2m,which is included in each of the edge sense amplifiers121-1and121-mincluded in a sense amplifier array120-3, is greater than an average value L2of a channel length of each MOS transistor, which is included in each of the inner sense amplifiers121-2to121-(m-1).

Additionally, an average value W1of a channel width of each MOS transistor P11, P21, N11, N21, P1m,P2m,N1mand N2m,which is included in each of the edge sense amplifiers121-1and121-mincluded in a sense amplifier array120-3, is greater than an average value W2of a channel width of each MOS transistor, which is included in each of the inner sense amplifiers121-2to121-(m-1).

In the examples ofFIGS. 3-5, based on the channel widths and/or lengths of the transistors that make up the different sense amplifiers, an average area of the channel for edge sense amplifiers may be a certain amount larger than the average area of the channels for inner sense amplifiers. In one embodiment, the average area for the edge sense amplifiers may be greater than the average area of the channels for the inner sense amplifiers by 10% or more, for example. As in the example above, the value of 10% is exemplary only. In certain embodiments, an intentional average area difference may be selected to be an amount greater than any expected process variation, to ensure that all edge sense amplifiers have greater average channel area than all inner sense amplifiers. For example, the above value of 10% may be used when a known process variation is as high as +/−4%. However, should a known process variation only cause variations of, for example, +/−2%, then an intentional average area increase less than 10% may be used (e.g., 5%). In one embodiment, each transistor of the edge sense amplifiers121-1to121-mhas a larger channel area than any transistor of the inner sense amplifiers121-2to121-(m-1), by the designated percentage (e.g., 10%). In one embodiment, a design parameter may be set such that even after process variations are accounted for, the average channel area discussed above in the edge sense amplifiers is at least a certain percentage (e.g., 10%) larger than the average channel area of the inner sense amplifiers.

FIG. 6illustrates a part of a memory device including an edge sense amplifier included in the sense amplifier array illustrated inFIG. 3,4, or5, according to one embodiment.

An operation of a part20A of a memory device20or20-1(collectively:20) is explained referring toFIGS. 1 to 6.

A normal memory cell101included in a part100A of a memory cell array100is connected to a first word line WL1and a first bit line BL1. An edge sense amplifier121-1is connected to a first bit line BL1and a first complementary bit line/BL1, and senses and amplifies a voltage difference between the first bit line BL1and the first complementary bit line/BL1.

The edge sense amplifier121-1includes an N-channel sense amplifier and a P-channel sense amplifier. The N-channel sense amplifier includes N-channel MOS transistors N11and N21, and the P-channel sense amplifier includes P-channel MOS transistors P11and P21.

During a pre-charge operation, an equalization circuit EQC pre-charges the first bit line BL1and the first complementary bit line/BL1with an equalization voltage VBL in response to an equalization enable signal EQ.

During an amplification operation, a first power supply circuit PS1supplies a ground voltage Vss to a common node of N-channel MOS transistors N11and N21in response to an N-channel sense amplifier enable signal LANG having a high level. During the amplification operation, a second power supply circuit PS2supplies a supply voltage Vdd to a common node of P-channel MOS transistors P11and P21in response to a P-channel sense amplifier enable signal LAPG having a low level.

Accordingly, during the amplification operation, the edge sense amplifier121-1senses and amplifies a signal stored in a normal memory cell101based on a difference between a voltage of the first bit line BL1and a voltage of the first complementary bit line/BL1.

The edge sense amplifier121-1may include each component EQC, PS1and PS2; however, for convenience of explanation, each component121-1, EQC, PS1and PS2is divided and illustrated. A part140A of the output gate circuit140may transmit signals of a bit line pair BL1and /BL1to an input/output line pair IO and /IO based on a column selection signal CSL1having a high level.

FIGS. 7A and 7Billustrate a cross-sectional diagram of N-channel MOS transistors included in a sense amplifier array illustrated inFIG. 3, according to one exemplary embodiment. Referring toFIGS. 3,6,7A and7B, an N-channel MOS transistor123included in the edge sense amplifier121-1includes a drain123-2and a source123-3formed inside a P-type substrate123-1, an oxide film123-4formed on the P-type substrate123-1, and a gate electrode123-5formed on the oxide film123-4. The N-channel MOS transistor123has a channel length L1and a channel width W.

Except for a channel length L2, (e.g., layout, shape, and size) a structure of an N-channel transistor124included in a inner sense amplifier121-2illustrated inFIG. 7Bis substantially the same as a structure of the N-channel MOS transistor123included in the edge sense amplifier121-1illustrated inFIG. 7A. Referring toFIGS. 7A and 7B, in one embodiment, a channel length L1of the N-channel MOS transistor123is longer than a channel length L2of the N-channel MOS transistor124(e.g., by more than 10%).

A gate electrode123-5may be embodied, for example, in metal or poly-silicon.

‘D’ ofFIG. 3depicts a drain or a drain region of a MOS transistor, ‘S’ depicts a source or a source region of the MOS transistor, and ‘G’, ‘G1’ and ‘G2’ depict a gate electrode corresponding to a channel length of a corresponding MOS transistor, respectively. Here, since a channel length L1of each MOS transistor, included in each edge sense amplifier121-1and121-m,is longer than a channel length L2of each MOS transistor, included in the inner sense amplifier121-2to121-(m-1), a length of a gate electrode G1corresponding to the channel length L1is longer than a length of a gate electrode G2corresponding to the channel length L2.

FIGS. 8A and 8Billustrate a cross-sectional diagram of N-channel MOS transistors included in the sense amplifier array illustrated inFIG. 4, according to certain exemplary embodiments. Referring toFIGS. 4,8A and8B, a channel width W1of the N-channel MOS transistor123of an edge sense amplifier121-1illustrated inFIG. 8Ais wider than a channel width W2of the N-channel MOS transistor124of a inner sense amplifier121-2illustrated inFIG. 8B(e.g., by more than 10%).

According to an example embodiment, a channel length and a channel width of each MOS transistor included in each edge sense amplifier121-1and121-mmay be formed greater than a channel length and a channel width of each MOS transistor included in each inner sense amplifier121-1and121-(m-1).

FIGS. 9A and 9Billustrate a cross-sectional diagram of N-channel MOS transistors included in the sense amplifier array illustrated inFIG. 5. Referring toFIGS. 5,9A and9B, a channel length L1and a channel width W1of the N-channel MOS transistor123of the edge sense amplifier121-1illustrated inFIG. 9Aare respectively greater than a channel length L2and a channel width W2of the N-channel MOS transistor124of the inner sense amplifier121-2illustrated inFIG. 9B. For example, L1may be greater than L2by more than 10%, and W1may be greater than W2by more than 10%. Alternatively, or additionally, the combined area based on L1and W1may be greater than the combined area based on L2and W2by more than 10% or some other designated intentionally-set size.

Each channel length L, L1and L2, each channel width W, W1and W2, and each gate electrode G1and G2illustrated inFIGS. 3 through 9Bdepict characteristics that reflect a desired relative size. The actual size of the depicted elements may vary, likely due to process variations that occur in a process of manufacturing the memory device. Therefore, the uniformity in size in the figures may reflect an an average actual value for a set of elements, wherein each element as actually manufactured may vary within a particular size range.

As explained referring toFIGS. 1 through 9B, when the size of each MOS transistor included in each edge sense amplifier121-1and121-mis laid out greater than the size of each MOS transistor included in each inner sense amplifier121-2to121-(m-1), distribution of attributes (or characteristics), e.g., a threshold voltage, an on-state saturation current or an off-state leakage current, of each of MOS transistors, included in each of the edge sense amplifier121-1and121-m,gets decreased compared to distribution of attributes of each of MOS transistors included in each of the inner sense amplifiers121-2to121-(m-1).

Accordingly, a sensing capability of each edge sense amplifier121-1and121-mgets improved further than a sensing capability of each inner sense amplifier121-2to121-(m-1). This counteracts an effect that often occurs at edge sense amplifiers where the process variation tends to be higher than the process variation of inner sense amplifiers. Accordingly, a yield of a device10or20may increase.

Although the above-described figures depict a sense amplifier array for a memory cell array, this is just one example embodiment. For example, a memory cell array may have a plurality of sense amplifier arrays included throughout (e.g., bit lines could be separated in to groups so that certain sense amplifier arrays are used to sense data in cells for sub-portions of a bit line). In one embodiment, for example, sub-bit lines can be used, such that a plurality of sense amplifier arrays are used that correspond to the number of sub-bit lines in each bit line. As such, certain sense amplifiers may be global sense amplifiers, while others may be local sense amplifiers.

FIGS. 10 through 20illustrate example embodiments of systems that may include the memory device illustrated inFIG. 2Aor2B. Referring toFIG. 10, a system300includes the memory device20including the sense amplifier array120, and a memory controller310. The system300may be embodied in a multi-chip module or a system on chip. The memory controller310may control an operation of the memory device20.

FIG. 11is an example of a system including the memory device20or20-1(collectively:20) illustrated inFIG. 2Aor2B, e.g., a semiconductor package410. The semiconductor package410may further include a memory controller411for controlling an operation of the memory device20. According to an example embodiment, unlike a structure illustrated inFIG. 11, the memory device20may be stacked on an upper side of the memory controller411(e.g., the memory device20may either be between a memory controller411and a PCB, or may be above both the memory controller and the PCB).

The memory controller411may be, for example, a processor. In one embodiment, each device20and411may be connected to a printed circuit board (PCB) through bonding wires412. The PCB may communicate with another device through solder balls.

FIG. 12is an example of a system including the memory device20illustrated inFIG. 2Aor2B, e.g., a semiconductor package430. The semiconductor package430may further include a memory controller431for controlling an operation of the memory device20.

Here, the memory controller431may be a processor. Each device20and431may be connected to each printed circuit board PCB1and PCB2through each bonding wire432. Each printed circuit board PCB1and PCB2may communicate with another device through solder balls. Each printed circuit board PCB1and PCB2may be embodied in a single printed circuit board.

The memory device20illustrated inFIG. 2Aor2B may be packaged in a package such as Package On Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Chip On Board (COB), CERamic Dual In-Line Package (CERDIP), plastic metric quad flat pack (MQFP), Thin Quad Flat Pack (TQFP), small-outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), system in package (SIP), multi chip package (MCP), wafer-level package (WLP), or wafer-level processed stack package (WSP) or the like.

As illustrated inFIG. 13, memory devices20-1through20-7may be stacked in a stacked semiconductor chip package. In one embodiment, the memory devices20-1through20-7are stacked on a logic layer520. The logic layer520may be stacked on a package substrate510. Here, a structure and an operation of each of the memory devices20-1through20-7may be substantially the same as a structure and an operation of semiconductor device20or20-1explained referring toFIGS. 1 through 9.

Each device20-1to20-7,520and510may be connected to each other through vertical electrical connection means, e.g., through substrate vias (TSVs, such as through silicon vias). According to an example embodiment, at least one of memory devices20-2to20-7may be replaced with a memory controller or a processor, which may control an operation of the memory device20-1.

As illustrated inFIG. 14, an exemplary system600, e.g., a memory module, includes memory devices612-1through612-k,where k is a natural number, mounted on a PCB610. A structure and an operation of each of the memory devices612-1through612-kare substantially the same as a structure and an operation of the memory device20or20-1explained referring toFIGS. 1 through 9.

The memory module may be, for example, a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a single in-line pin package (SIPP) memory, or a small outline DIMM (SO-DIMM).

As illustrated inFIG. 15, a system700may be embodied, for example, in a personal computer (PC), a laptop computer, or a server. The system700includes a slot703and a processor710which are installed in a main board701. Each of the memory devices612-1to612-kof a memory module600may transmit or receive data with the processor710through the slot703and the main board701. The processor710may be a chipset.

As illustrated inFIG. 16, a system800may be embodied in a mobile computing device. The mobile computing device may be embodied, for example, in a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, or an e-book.

An application processor (AP)810, e.g., a mobile application processor810, may control an operation of each element815,820,841and850.

A structure and an operation of each memory device815and821are substantially the same as a structure and an operation of the memory device20or20-1explained referring toFIGS. 1 through 9.

The memory controller811embodied inside the application processor810may control an access operation on the memory device815. A display driver813embodied inside the application processor810may control an operation of a display850. The display850may be embodied in a Thin film transistor liquid crystal display (TFT-LCD), a light-emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, or a flexible display.

A modem820may interface data transmitted or received between a radio transceiver830and the application processor810. Data processed by the modem820may be stored in the memory device821or transmitted to the application processor810.

Radio data received through an antenna ANT are transmitted to the modem820through the radio transceiver830, data output from the modem820are converted into radio data by the radio transceiver830, and converted radio data are output through the antenna ANT.

An image signal processor841may process a signal output from a camera (or an image sensor840) and transmit processed data to the application processor810.

The application processor810may control execution of at least one of web browsing, e-mail access, video playback, document editing and image editing.

As illustrated inFIG. 17, a system900may be embodied in a processor.

The processor900includes the memory device20, a control unit910, and an arithmetic-logic unit (ALU)920.

According to a control of the control unit910, the ALU920may perform an arithmetic operation and/or a logical operation on input data INPUT and store a result of the performance in the memory device20. In addition, according to a control of the control unit910, the ALU920may perform an arithmetic operation and/or a logical operation on input data INPUT and data output from the memory device20, and store a result of the performance in the memory device20or output it as output data OUTPUT.

For example, the ALU920may perform a bitwise logical operation, e.g., an AND operation, a NOT operation, an OR operation, a NAND operation or a XOR operation.

As illustrated inFIG. 18, a system1000includes the memory device20and an electric optical conversion block1010. The electric-optical conversion block1010may include electric-optical converters, and the electric-optical converters convert electrical signals output from output drivers embodied in the output driver block160into optical signals and output converted optical signals OS.

As illustrated inFIG. 19, a computing system1100includes a host1110, a hard disk controller1120, a hard disk1130and a memory device1140. A hard disk drive may include the hard disk controller1120and the hard disk1130.

A structure and an operation of each memory device1113and1140are substantially the same as a structure and an operation of the memory device20explained referring toFIGS. 1 to 9. During a write operation, data output from the memory device1113are written in the hard disk1130through a write path.

According to a control of a direct memory access (DMA) controller1114or a host CPU1111, data output from the memory device1113are transmitted to a device SATA interface1123through a host SATA interface1115and a channel CH. Each element1111,1113,1114and1115may communicate with each other through a bus1112.

According to a control of a main control unit1121, a buffer controller1124stores data output from the device SATA interface1123in a memory device1140. According to a control of the buffer controller1124, data output from the memory device1140are transmitted to a disk controller1125. The disk controller1125stores data output from the buffer controller1124in the hard disk1130. Each element1121,1123,1124and1125may communicate with each other through a bus1122.

During a read operation, data output from the disk1130may be stored in the memory device1113through a read path.

According to a control of the main control unit1121, the disk controller1125transmits data stored in the hard disk1130to the buffer controller1124. According to a control of the main control unit1121, the buffer controller1124stores data output from the disk controller1125in the memory device1140. According to a control of the main control unit1121, the buffer controller1124transmits data stored in the memory device1140to a SATA interface1115through the device SATA interface1123and the channel CH.

According to a control of the direct memory access (DMA) controller1114or the host CPU1111, data input through the SATA interface1115are stored in the memory device1113. Accordingly, the host CPU1111may read data stored in the memory device1113.

As illustrated inFIG. 20, a system1200may be embodied in a solid state drive (SSD). The system1200includes the memory device20, a host1210, a buffer manager1220, a NAND flash memory controller1230and NAND flash memory devices NAND.

The NAND flash memory controller1230may control a data processing operation, e.g., a program operation, a read operation or an erase operation, of each of the NAND flash memory devices NAND.

The buffer manager1220may control storage of data transmitted or received between the host1210and the NAND flash memory controller1230in the memory device20. Here, the buffer manager1220may include a memory controller. However, the memory controller may be embodied outside the buffer manager1220.

FIG. 21is a flowchart depicting a method of manufacturing the memory device illustrated inFIG. 2Aor2B. Referring toFIGS. 1 to 9B, and21, a memory cell array100including first normal memory cells and second normal memory cells is formed inside and/or on a semiconductor substrate (S110). Each of the first normal memory cells and the second normal memory cells may refer to, for example, a normal memory cell101. The descriptions herein may apply to redundant memory cells as well. However, in certain embodiments, sense amplifier arrays using different-sized sense amplifiers are used either for a set of all normal memory cells, or for a set of all redundant cells.

The edge sense amplifiers121-1and121-meach having a first statistic attribute to amplify a signal output from each of the first normal memory cells, and the inner sense amplifiers121-2to121-(m-1) each having a second statistic attribute to amplify a signal output from each of the second normal memory cells are formed inside and/or on a semiconductor substrate at the same time (S120). According to an example embodiment, dummy sense amplifier regions120A and120B may be formed inside and/or on the semiconductor substrate.

For convenience of explanation, each step S110and S120is divided from each other inFIG. 21; however, each step S110and S120may be formed at the same time by using one mask.

According to the different figures above, the statistic attributes may refer to different aspects related to a size of a sense amplifier or elements of the sense amplifier.

For example, as explained referring toFIGS. 3,7A and7B, the first statistic attribute may be determined according to an average length of MOS transistors included in the edge sense amplifiers121-1and121-m,e.g., a first average channel length L1, and the second statistic attribute may be determined according to an average length of MOS transistors included in the inner sense amplifiers121-2to121-(m-1), e.g., a second average channel length L2. In one embodiment, the first average channel length L1is longer than a second average channel length L2by more than 10%.

In addition, as explained referring toFIGS. 4,8A and8B, the first statistic attribute may be determined according to an average width of MOS transistors included in the edge sense amplifiers121-1and121-m,e.g., a first average channel width W1, and the second statistic attribute may be determined according to an average width of MOS transistors included in the inner sense amplifiers121-2to121-(m-1), e.g., a second average channel width W2. In one embodiment, the first average channel width W1is wider than the second average channel width W2by more than 10%.

In addition, as explained referring toFIGS. 5,9A and9B, the first statistic attribute may be determined according to a first average channel length L1and a first average channel width W1of MOS transistors included in the edge sense amplifiers121-1and121-m,and the second statistic attribute may be determined according to a second average channel length L2and a second average channel width W2of MOS transistors included in the inner sense amplifiers121-2to121-(m-1).

Here, in one embodiment, the first average channel length L1may be longer than the second average channel length L2by more than 10%, and the first average channel width W1may be wider than the second average channel width W2by more than 10%. Alternatively, or additionally, the average channel area for the MOS transistors included in the edge sense amplifiers121-1and121-mmay be more than 10% of the average channel area of the MOS transistors included in the inner sense amplifiers121-2to121-(m-1).

As each of sense amplifiers having different sizes based on a layout location has a different sensing capability, a signal output from a memory cell embodied at an edge of a memory cell array may be correctly sensed.

Accordingly, a yield of a memory device including the sense amplifiers may increase.