Analog-to-digital converter architecture using a capacitor array structure

An analog-to-digital converter architecture is described. An analog-to-digital converter circuit includes a switched capacitor circuit structure to receive an input voltage signal and one or more reference voltage signals. The analog-to-digital converter circuit also includes a comparator device array coupled to the switched capacitor circuit structure. The comparator device array further includes multiple comparator devices coupled in parallel, each comparator device having a pair of inputs coupled to the switched capacitor circuit structure to receive a voltage output signal from the switched capacitor circuit, a voltage value of the voltage output signal being calculated as a difference between an input voltage value of the input voltage signal and a predetermined value of the reference voltage signal, which is dependent on the position of the respective comparator device within the comparator device array, each comparator device experiencing an identical common mode voltage input within the analog-to-digital converter circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to analog-to-digital converters, and, more particularly, to an analog-to-digital converter architecture using a capacitor array structure.

2. Art Background

Low voltage analog design needs to comply with the ever decreasing digital supply voltage used for an entire mixed-signal chip structure. Supply voltages in deep submicron CMOS technologies decrease constantly due to the short channel effects, and, thus, the need arises for low voltage analog-to-digital converters. A flash analog-to-digital converter (“ADC”), also known as a parallel ADC, is the fastest way to convert an analog signal to a digital signal. Generally, a flash ADC is comprised of multiple cascading high-speed comparator devices, each comparator device having two pair of inputs coupled to a resistive divider circuit and an output coupled to a digital encoder.

In a conventional ADC, each comparator device experiences a different common-mode input voltage, which may prove challenging in the design of the comparator device. In addition, each comparator device requires two pairs of inputs, which may increase the complexity of the comparator device and may create a larger undesired input offset voltage. Thus, what is needed is an architecture containing comparator devices, each comparator device experiencing an identical common-mode input voltage at a desired voltage and having only one pair of inputs.

SUMMARY OF THE INVENTION

An analog-to-digital converter architecture is described. In embodiments described in detail below, an analog-to-digital converter circuit includes a switched capacitor circuit structure to receive an input voltage signal and one or more reference voltage signals. The analog-to-digital converter circuit also includes a comparator device array coupled to the switched capacitor circuit structure. The comparator device array further includes multiple comparator devices coupled in parallel, each comparator device having a pair of inputs coupled to the switched capacitor circuit structure to receive a voltage output signal from the switched capacitor circuit, a voltage value of the voltage output signal being calculated as a difference between an input voltage value of the input voltage signal and a predetermined value of the reference voltage signal, which is dependent on the position of the respective comparator device within the comparator device array. In embodiments described in detail below, each comparator device experiences an identical common mode voltage input within the analog-to-digital converter circuit, irrespective of its position within the comparator device array.

DETAILED DESCRIPTION

In embodiments described in detail below, an analog-to-digital converter circuit includes a switched capacitor circuit structure to receive an input voltage signal and one or more reference voltage signals. The analog-to-digital converter circuit also includes a comparator device array coupled to the switched capacitor circuit structure. The comparator device array further includes multiple comparator devices coupled in parallel, each comparator device having a pair of inputs coupled to the switched capacitor circuit structure to receive a voltage signal output by the switched capacitor circuit and having a value calculated as a difference between an input voltage value of the input voltage signal and a predetermined value of the reference voltage signal, which is dependent on the location of the respective comparator device within the comparator device array. In one embodiment, each comparator device receives an identical common mode voltage input within the analog-to-digital converter circuit irrespective of its position within the comparator device array.

FIG. 1is a block diagram illustrating a conventional analog-to-digital converter (“ADC”)100. The ADC100includes multiple comparator devices110coupled in parallel, each comparator device110having at least two pairs of inputs coupled to a resistive divider circuit120and an output coupled to a digital encoder130.

The resistive divider circuit120further includes multiple resistor devices125and generates a reference voltage VREF, ranging between a positive voltage value VREFPand a negative voltage value VREFN. For an N-bit ADC100, such as, for example, a 6-bit converter, the circuit employs 2N−1 comparator devices110, such as, for example, 63 comparator devices, and 2Nresistor devices125, such as, for example, 64 resistor devices.

Each comparator device110compares the input voltage VINPUTat the ADC100to the corresponding value of the reference voltage VREFat the input of the respective comparator device110. The reference voltage VREFvalue for each comparator device110is one least significant bit (“LSB”) greater than the reference voltage VREFvalue for the comparator device110immediately below it. Each comparator device110produces a “1” value if its analog input voltage value VINPUTis higher than the reference voltage value VREFapplied to it. Otherwise, the output of the respective comparator device110is “0.”

In the conventional ADC architecture shown inFIG. 1, each comparator device110experiences a different common-mode input voltage ranging from VREFNto VREFP, which may prove challenging in the design of the comparator device110. In addition, each comparator device110requires two pairs of inputs, which may increase the complexity of the comparator device110and may create a larger undesired input offset voltage.

FIG. 2is a block diagram illustrating an ADC architecture, according to one embodiment of the invention. As shown inFIG. 2, in one embodiment, an ADC200includes multiple cascading comparator devices210within a comparator device array, each comparator device210having at least one pair of inputs coupled to a switched capacitor circuit structure220and an output coupled to a digital encoder230. If N is the number of bits in the ADC architecture200, such as, for example, N=6 bits, then the ADC200includes 2N−1 comparator devices210, such as, for example, 26−1=63 comparator devices.

In one embodiment, the switched capacitor circuit structure220includes multiple capacitor devices, as described in further detail below in connection withFIG. 3. The switched capacitor circuit structure220receives the input voltage signal VINPUTand a reference voltage signal VREF, ranging between a positive voltage value VREFPand a negative voltage value VREFN.

FIG. 3is a schematic diagram illustrating a switched capacitor circuit structure within the analog-to-digital converter architecture, according to one embodiment of the invention. As illustrated inFIG. 3, a switched capacitor circuit300is coupled to each comparator device210within the ADC200shown inFIG. 2.

In one embodiment, the switched capacitor circuit300further includes multiple capacitor devices301through304having capacitance values calculated as a function of a predetermined capacitance value C0and a parameter “k.” The value of the parameter “k” varies from one comparator device210to another and determines the reference voltage signal VREFassociated with each respective comparator device210. In the embodiment ofFIG. 3, capacitor devices301and304have a respective k*C0capacitance value and capacitor devices302and303have a respective (M−k)*C0capacitance value, where k=0, 1, 2, . . . , M and represents the position or location of the comparator device210within the comparator array of the ADC200. Each capacitor device301,302,303,304may be implemented using a known metal-insulator-metal (“MIM”) structure or, in the alternative, a known metal-oxide-metal (“MOM”) structure.

In one embodiment, the switched capacitor circuit300further includes capacitor devices305and306, each being coupled to ground and having a respective L*C0capacitance value. In one embodiment, parameter “L” is an optional parameter for scaling down the reference voltage signal VREFat the input of each comparator device210by a factor of M/(M+L). In one embodiment, L=0. Alternatively, L has a positive value. In one embodiment, the switched capacitor circuit300further includes multiple switches311through323, which are synchronized to maintain an open state or a closed state based on the value of the clock signal within the respective sampling and comparison phases, as described in further detail below.

In one embodiment, during the sampling phase “ph1,” switches311,312,313,316,317,320, and323are closed. As a result, the differential input voltages VINPand VINNare respectively sampled onto the top plate of capacitor devices301through306and a combination of reference voltages VREFPand VREFNis respectively sampled onto the bottom plate of capacitor devices301through304. For example, as shown inFIG. 3, VINPis sampled onto the capacitor devices301,302, and305and VINNis sampled onto the capacitor devices303,304, and306. In addition, VREFPis sampled onto capacitor devices301and303, and VREFNis sampled onto capacitor devices302and304. During the sampling phase “ph1,” the differential input pair of the comparator device210may be shorted by the closing of the switch323and by the opening of switches321and322.

In one embodiment, during the comparison phase “ph2,” switches311and312are open and the differential input voltages are disconnected from the respective capacitor devices301through306. At the same time, switches321and322are closed, switch323is open, and the capacitor array is coupled to the differential input of the comparator device210.

During the comparison phase “ph2,” switches314,315,318,319are also closed and, thus, the reference voltages VREFPand VREFNare respectively sampled onto the bottom plate of capacitor devices301through304opposite to the values sampled during the sampling phase “ph1,” such that VREFPis sampled onto capacitor devices302and304, and VREFNis sampled onto capacitor devices301and303.

In one embodiment, the differential voltage at the input of the comparator device210may be calculated as follows:
VCOMP—IN=(VINP−VINN)−(2(M−2k)/(M+L))(VREFP−VREFN)
where k=0, 1, 2, . . . , M, represents the location of each respective comparator device210within the comparator device array of the ADC200.

Thus, the common mode voltage input to all comparator devices210within the ADC200is:
VCOMP—IN—CM=(VINP+VINN)/2

As a result, according to the above equation, the common mode voltage inputs to each respective comparator device210are identical and are independent of the position of each comparator device210within the comparator device array of the ADC200.

FIG. 4is a schematic diagram illustrating a switched capacitor circuit structure within the analog-to-digital converter architecture, according to an alternate embodiment of the invention. As illustrated inFIG. 4, a switched capacitor circuit400is coupled to each comparator device210within the ADC200shown inFIG. 2.

In one embodiment, the switched capacitor circuit400further includes multiple capacitor devices401through404having capacitance values calculated as a function of a predetermined capacitance value C0and a parameter “k.” The value of the parameter “k” varies from one comparator device210to another and determines the reference voltage signal VREFassociated with each respective comparator device210. In the embodiment ofFIG. 4, capacitor devices401and404have a respective k*C0capacitance value and capacitor devices402and403have a respective (1−k)*C0capacitance value, where k=0, 1, 2, . . . , (M−1)/2, and represents the location of the comparator device210within the comparator array of the ADC200. Each capacitor device401,402,403,404may be implemented using a known metal-insulator-metal (“MIM”) structure or, in the alternative, a known metal-oxide-metal (“MOM”) structure.

In one embodiment, the switched capacitor circuit400further includes capacitor devices405and406, each being coupled to ground and having a respective L*C0capacitance value. In one embodiment, parameter “L” is an optional parameter for scaling down the reference voltage signal VREFat the input of each comparator device210by a factor of M/(M+L). In one embodiment, L=0. Alternatively, L has a positive value. In one embodiment, the switched capacitor circuit400further includes multiple switches411through419, which are synchronized to maintain an open state or a closed state based on the value of the clock signal within the respective sampling and comparison phases, as described in further detail below.

In one embodiment, during the sampling phase “ph1,” switches411,412,413,416, and419are closed. As a result, the differential input voltages VINPand VINNare respectively sampled onto the top plate of capacitor devices401through406and a combination of reference voltages VREFPand VREFNis respectively sampled onto the bottom plate of capacitor devices401and404. For example, as shown inFIG. 4, VINPis sampled onto the capacitor devices401,402, and405and VINNis sampled onto the capacitor devices403,404, and406. In addition, VREFPis sampled onto capacitor device401and VREFNis sampled onto capacitor device404. During the sampling phase “ph1,” the differential input pair of the comparator device210may be shorted by the closing of the switch419and by the opening of switches417and418.

In one embodiment, during the comparison phase “ph2,” switches411and412are open and the differential input voltages are disconnected from the respective capacitor devices401through406. At the same time, switches417and418are closed, switch419is open, and the capacitor array is coupled to the differential input of the comparator device210. During the comparison phase “ph2,” switches414,415are also closed and, thus, the reference voltages VREFPand VREFNare respectively sampled onto the bottom plate of capacitor devices401and404opposite to the values sampled during the sampling phase “ph1,” such that VREFPis sampled onto capacitor device404, and VREFNis sampled onto capacitor device401.

FIG. 5is schematic diagram illustrating a switched capacitor circuit structure within the analog-to-digital converter architecture, according to another alternate embodiment of the invention. As illustrated inFIG. 5, a switched capacitor circuit500is coupled to each comparator device210within the ADC200shown inFIG. 2.

In one embodiment, the switched capacitor circuit500further includes multiple capacitor devices501and502having capacitance values calculated as a function of a predetermined capacitance value C0and a parameter “k.” The value of the parameter “k” varies from one comparator device210to another and determines the reference voltage signal VREFassociated with that respective comparator device210. In the embodiment ofFIG. 5, capacitor device501has a k*C0capacitance value and capacitor device502has a respective (M−k)*C0capacitance value, where k=0, 1, 2, . . . , M, and represents the location of the comparator device210within the comparator array of the ADC200. Each capacitor device501,502may be implemented using a known metal-insulator-metal (“MIM”) structure or, in the alternative, a known metal-oxide-metal (“MOM”) structure.

In one embodiment, the switched capacitor circuit500further includes a capacitor device503coupled to ground and having a respective L*C0capacitance value. In one embodiment, parameter “L” is an optional parameter for scaling down the reference voltage signal VREFat the input of each comparator device210by a factor of M/(M+L). In one embodiment, L=0. Alternatively, L has a positive value. In one embodiment, the switched capacitor circuit500further includes multiple switches511through516, which are synchronized to maintain an open state or a closed state based on the value of the clock signal within the respective sampling and comparison phases, as described in further detail below.

In one embodiment, during the sampling phase “ph1,” switches511,512, and515are closed. Thus, the input voltage VINis sampled onto the top plate of capacitor devices501through503and reference voltages VREFPand VREFNare sampled onto the bottom plate of capacitor devices501and502, respectively.

In one embodiment, during the comparison phase “ph2,” switches511,512, and515are open. Thus, the input voltage VINis disconnected from the respective capacitor devices501through503. At the same time, switches513,514, and516are closed and, thus, the reference voltages VREFPand VREFNare sampled onto the bottom plate of capacitor devices501and502opposite to the values sampled during the sampling phase “ph1,” such that VREFPis sampled onto capacitor device502, and VREFNis sampled onto capacitor device501. The capacitor devices501through503are further coupled to the input of the comparator device210.

In one embodiment, the voltage at the input of the comparator device210may be calculated as follows:
VCOMP—IN=VIN−((M−2k)/(M+L))(VREFP−VREFN)

where k=0, 1, 2, . . . , M, represents the location of each respective comparator device210within the comparator device array of the ADC200. Thus, a trigger point of all comparator devices210within the ADC200may be a fixed reference voltage VREFM, as opposed to a conventional resistive flash ADC100, as shown inFIG. 1, which requires each comparator device110to have a different trigger point ranging in value from VREFNto VREFP.

It is to be understood that embodiments of the present invention may be implemented not only within a physical circuit (e.g., on semiconductor chip) but also within machine-readable media. For example, the circuits and designs discussed above may be stored upon and/or embedded within machine-readable media associated with a design tool used for designing semiconductor devices. Examples include a netlist formatted in the VHSIC Hardware Description Language (VHDL) language, Verilog language or SPICE language. Some netlist examples include: a behavioral level netlist, a register transfer level (RTL) netlist, a gate level netlist and a transistor level netlist. Machine-readable media also include media having layout information such as a GDS-II file. Furthermore, netlist files or other machine-readable media for semiconductor chip design may be used in a simulation environment to perform the methods of the teachings described above.

Thus, it is also to be understood that embodiments of this invention may be used as or to support a software program executed upon some form of processing core (such as the CPU of a computer) or otherwise implemented or realized upon or within a machine-readable medium. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc.

Although the present invention has been described in terms of specific exemplary embodiments, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention.