Method and apparatus of USB 3.1 retimer presence detect and index

An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein an algorithm is to enable the at least one retimer to announce its presence by asserting a bit of a presence message during link initialization. The at least one retimer can declare an index and is accessible via the index.

FIELD

The present techniques generally relate to universal serial bus (USB) communications. More specifically, the present techniques relate to USB retimer presence detection and indexing.

DESCRIPTION OF THE EMBODIMENTS

The Universal Serial Bus (USB) protocol enables electronics communications in accordance with USB standards. The USB standard can define signal properties, timing, and state changes required for compatibility with the protocol. Data is transferred between one or more USB ports according to the USB standard. The ports can be located such that a signal transferring data between the ports deteriorates while traveling from one port to another. A retimer can be used to retime or synchronize the signal to mitigate deterioration during signal transfer from one port to another. Accordingly, the retimer is to synchronize and regenerate deteriorated signals from a receiving port to a transmitting port. A plurality of retimers can be placed between a host port and a device port.

As noted above, USB ports can be located such that a signal transferring data between the ports deteriorates while traveling from one port to another. Signals may also degrade when sent to and from USB Host Controllers, USB Hubs, USB Devices, or any combinations thereof. To maintain signal timing, a plurality of retimers can be placed between USB ports, host controllers, hubs, and devices. In some cases, the retimers are not discoverable or configurable for multi-protocol support.

Embodiments described herein enable a messaging protocol to allow one retimer or a plurality of retimers to announce their presence with a self-index awareness for access by their link partners. In some cases, the retimers are USB 3.1 retimers. An inband approach is used for automatic retimer presence detection and indexing such that a retimer, if equipped with capability of multi-protocol support, may be accessed by a host for feature discovery and protocol configuration. In this manner, the retimer is discoverable and configurable for multi-protocol support. Although the present techniques are described using USB3.1 retimers, the present techniques can be applied to other USB retimers, as well as other retimers such as PCI-E retimers. Moreover, other components to correct signal deterioration, such as other redrivers, can be used according to the present techniques.

Although the following embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. And may be also used in other devices, such as handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatus', methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatus', and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a ‘green technology’ future balanced with performance considerations.

As computing systems are advancing, the components therein are becoming more complex. As a result, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth requirements are met for optimal component operation. Furthermore, different market segments demand different aspects of interconnect architectures to suit the market's needs. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. Yet, it's a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Below, a number of interconnects are discussed, which would potentially benefit from aspects of the invention described herein.

FIG. 1is an exemplary illustration of a topology diagram100for USB configuration. In embodiments, the topology diagram100is a USB 3.1 configuration.FIG. 1includes a first port102and a second port104. The first port102and the second port104may each be USB 3.1 ports. The first port102is a downstream port included within a hub or host of a system including this USB configuration. The second port104is an upstream port included within a hub or peripheral of the system including this USB configuration. A retimer106, a retimer108, a retimer110, and a retimer112are included between the first port102and the second port104. A link114connects the first port102to the second port104. Typically, when traveling between a first port and a second port104, a signal along a typical link may have a reduced amplitude, resulting in signal attenuation and jitter. As illustrated in the diagram100, the retimer106, the retimer108, the retimer110, and the retimer112can each analyze and alter the signal to prevent signal deterioration between the first port and the second port104. In embodiments, one retimer is situated at the host, another retimer is situated at the device, and two retimers are situated at each end of a cable that is to connect the host and the device or peripheral. Additionally, in embodiments, the retimer at the host may be located on the host motherboard, with the retimer at the device located on the device motherboard, and two retimers in the cable that connects the host and the device.

Each retimer functions to retime or synchronize data received from upstream or downstream, whatever the case may be. Although four retimers are illustrated, there may be any number of retimers depending on the system configuration. Using a USB 3.1 configuration, there may be as many as four retimers between the two USB 3.1 ports. In any protocol, each retimer can operate as an encoder for an optical digital transmission. In this manner, the retimer can minimize glitches and jitter distortion. In embodiments, the retimers can control acquisition and transmission of the signals received.

When a port of the host and a port of the device are connected, a closed loop is formed where the number of retimers is determined. An index of each retimer may also be determined. The number of retimers between the host and the device are not known before the connection between the host and the device occurs. Rather, an algorithm is used to determine the number of retimers present, an index or an address of the retimers, and a method to communicate with the retimers. This algorithm can be implemented concurrently with the link initialization. In embodiments, the algorithm is a bubble algorithm. The algorithm enables the retimers to announce their presence and provide an index for them to be accessed for multi-protocol discovery and configuration, such that each port can determine which protocol to operate as during the initialization process. In examples, the protocols can be according to the following: Universal Serial Bus Revision 3.1 Specification released on Jul. 26, 2013; Peripheral Component Interconnect Express (PCI-E) announced Nov. 29, 2011; or DisplayPort. Although specific protocols and standards are listed, the present techniques may be used with any I/O technology.

The bubble algorithm is used to enable each retimer, upon receiving an incoming binary message, to announce its presence by asserting a bit in a reserved field and then forwarding the incoming message. The incoming message can be any message with a reserved field as defined by the protocol used. As illustrated inFIG. 1, multiple retimers exist along the link114. If multiple retimers exist in a link, then each retimer will perform the same operation of asserting a bit in a reserved field and then forwarding the incoming message. The ensuing retimers will also shift the bits asserted by preceding retimers. This exchange is performed in both directions along the link, i.e. from the upstream port to the downstream port and vice versa. In this manner, a port at the destination, being a host/hub downstream port, or a hub/peripheral upstream port, will know how many retimers are present along the link. By announcing the presence of each retimer in both directions, both ports are able to collect link configuration information in terms of number of retimers in between them. Both ports are able to perform retimer accesses based on their relative indexing of each retimer. Each retimer also becomes aware of the link configuration in terms of the number of retimers present, and the retimer's relative location within the link topology. This in turn enables the retimer's automatic index assignment for subsequent address decoding.

FIG. 2is a diagram200of the bubble algorithm applied to a system topology at various point in time. Similar toFIG. 1,FIG. 2includes a first port102and a second port104. The retimer106, the retimer108, the retimer110, and the retimer112are included between the first port102and the second port104along the link114. The link114may be an active cable. In embodiments, the bubble algorithm is executed during an initialization stage of the link114before communication is started between the first port102and the second port104. In some cases, the communication between the first port102and the second port104is high speed communication. All ports and retimers are capable of communicating with each other based on a low-frequency periodic signal (LFPS). In particular, the ports and retimers can communicate using LFPS Based Pulse-width modulation Signaling (LBPS).

Pulse width modulation (PWM) can be used to alter with width of each pulse in order to encode data for transmission. Each pulse occurs during a time period, and the pulse may be a low frequency periodic signal. During each bit time period, the pulse can be used to indicate the particular bit value sent depending on the location of the pulse within the time period. The bit value may be a logic level one or a logic level zero, depending on the pulse during each bit time period. For example, if a pulse occurs during the third of the time period with no pulse during the remaining two thirds of the time period, a logic zero level is encoded. If a pulse occurs during the first two thirds of the time period with no pulse during the remaining third of the time period, a logic one level is encoded.

The LBPS can be used to create an LFPS Based Pulse-width modulation Message (LBPM). The LFPS, LBPS, and LBPM are signaling and messaging techniques each defined by the USB 3.1 protocol. During initialization, the downstream port and upstream port will transmit an LBPM between the two ports to communicate an ensuing USB operation. The ports announce their capabilities, such as data rates, number of lanes, and the like. When retimers are present, the LBPM will pass through the retimers. When each retimer receives the LBPM, it will insert a bit in a reserved field that is dedicated to the retimers in order to announce their presence. The retimers will then forward the LBPM to the next retimer or port along the link. The LBPM includes a reserved field for the retimers to announce their presence may be referred to as a presence LBPM. A presence LBPM is sent by each retimer to announce the retimer's presence during initialization. In embodiments, the presence LBPM may be any message defined by the USB 3.1 protocol. For example, the presence LBPM may be a capabilities message sent during initialization, where the retimers announce their presence using the reserved field of the capabilities message. Although signal and messaging is described herein using the USB 3.1 protocol, the present techniques may be implemented using any input/output (I/O) protocol. Accordingly, each retimer may send a presence message to announce the retimer's presence during initialization, where the presence message is any message used where a retimer inserts a bit in a reserved field that is dedicated to the retimers in order to announce its presence.

In the example ofFIG. 2, USB 3.1 ports are illustrated. The USB 3.1 ports can send a capabilities message as defined by the USB 3.1 standard. In a capabilities message, the upper four bits are reserved, while the lower four bits are used to convey capabilities between the ports. Each retimer can use the upper four reserved bits to announce its presence. While a capability message is used as an example, any message can be used according to present techniques. Further, the bits used to announce the presence of the retimers are not restricted to the upper four bits of the message, and any available bits according to the particular protocol or standard can be used. By using a message as defined by the standard to announce the presence of the retimers, two operations can be combined into a single message. Specifically, the automatic retimer presence detection and indexing may be combined with another message being sent according to the standard. However, in embodiments, an LBPM can be defined for automatic retimer presence detection and indexing.

As illustrated inFIG. 2, at time202, an initial presence LBPM204A is sent along the link114from the downstream port102to the upstream port104. The retimer106examines if any bit in the reserved field is being set to determine if it is immediately placed by the downstream port102, or if there are retimers placed in between itself and the downstream port102. In this example, the retimer106finds no bit is set in the reserved field and concludes that it is placed just after the downstream port102. It then adds a logic level one to the presence LBPM in the reserved field at bit four to announce its presence, as indicated by the LBPM204B. At time204, the presence LBPM204B is sent along the link114from the retimer106to the retimer108. The same operation is performed by the retimer108as the retimer106. The retimer examines the LBPM204B and concludes that it is placed to the downstream port102with one retimer106in between retimer108and the downstream port102. The retimer108then adds a logic level one to the presence LBPM at bit five to announce its presence, as indicated by the LBPM204C.

At time206, the presence LBPM204C is sent along the link114from the retimer108to the retimer110. The retimer110adds a logic level one at bit six of the presence LBPM to announce its presence, as indicated by the LBPM204D. Similarly, at time208, the presence LBPM204D is sent along the link114from the retimer110to the retimer112. The retimer112adds a logic level one to the presence LBPM at bit five to announce its presence, as indicated by the LBPM204E. In this manner, each retimer can determine how many retimers are there between the retimer itself and the downstream port102. Note that the same operation is performed from the upstream port104to the downstream port102, and therefore, each retimer can determine its relative position between the retimer itself and the upstream port104. Thus, at the end of the operation, each retimer can determine its relative position to the downstream port102and the upstream port104. The downstream port102and the upstream port104can also determine how many retimers are there in between them. Every component of the link will automatically recognize the topology and configuration of the link and their relative position within the link. In embodiments, the ports can configure retimers. Specifically, the ports can check the status of each retimer and can also perform a configuration of the retimer. After the presence detection, each port can communicate with each retimer. An access LBPM can be sent to each retimer to alert the retimer that the port wants to communicate with or access the retimer. Additionally, each retimer may be equipped with the ability to support multiple protocols. As a result, although the present techniques are described using a USB 3.1 protocol, the present techniques can be implemented using any I/O protocol.

FIG. 3is an illustration of a logic representation300using a low frequency periodic signal generated through pulse width modulation. In embodiments, the logic representation300is based on LBPS. An LBPM may be defined as 8-bit LBPS with two delimiters at the beginning and the end of the byte as illustrated inFIG. 4. In examples, a logic level zero at reference number302can be represented by a low frequency periodic signal occurring during 30% of a time period304, with 70% no signals during the same time period304. In some cases, the 70% of no low frequency periodic signal can be referred to as low frequency periodic signal electric idle. A logic level one at reference number306can be represented by a low frequency periodic signal occurring during 70% of a time period308, with no signals during 30% of the same time period308. In some cases, the 30% of no low frequency periodic signal can be referred to as low frequency periodic signal electric idle. The signal to no signal ratio described herein is exemplary, and any ration of signal to no signal pulse width modulation can be used.

FIG. 4is an illustration of LFPS Based Pulse-width modulation Message (LBPM). At the start of the LBPM is a delimiter402. The delimiter402includes two tPWM periods. At the end of the LBPM is another delimiter404that includes a single PWM period. The delimiter402uses a tPWM period with a low frequency periodic signal followed by a second tPWM period with no signal. In embodiments, a delimiter such as the delimiter402signals the start of the LBPM. The delimiter404includes a tPWM period with a low frequency periodic signal to indicate the end of the LBPM. In this manner, the delimiter402and delimiter404can be used to transmit a complete byte to a receiver.

For example, consider the downstream port102, retimer106, retimer108, retimer110, retimer112, and the upstream port104illustrated inFIGS. 1 and 2. A presence LBPM is defined such that bit7at reference number402, bit6at reference number404, bit5at reference number406, and bit4at reference number408are used to indicate the LBPM. Also assume that if b7˜b4=“1001”, the LBPM denotes retimer presence message. During the initialization, the downstream port such as the downstream port102may transmit a presence message with b3-b0 de-asserted. Upon detecting the presence LBPM, the retimer106asserts bit-3to indicate its presence before forwarding the presence LBPM, and declares “1000” as its index towards the downstream port102. The retimer108, upon detecting the presence LBPM, performs the same operation as the retimer106by asserting bit-2to indicate its presence before forwarding. The retimer108also becomes aware of its relative location to the downstream port102and declares “1100” as its index towards the downstream port. This process of operation continues through retimers110and112until the presence LBPM reaches the upstream port104. Therefore, the retimers110and112will declare “1110” and “1111” as their respective indexes towards the downstream port. Upon receiving the final presence LBPM, the upstream port104becomes of aware of the number of the retimers in the link. Similarly the same operation is carried out in the reversed direction from the upstream port104through retimer112to retimer106, and to the downstream port102. As a result, the retimers from112to106will declare “0001”, “0011”, “0111” to “1111” as their respective indexes towards the upstream port104. At the end of the operation, both the downstream port102and the upstream port104are aware of the presence of the retimers in the link and their relative index, and may start perform various operations such as discovery of the retimer features and capabilities, and retimer configurations. Although this example referred to a generic LBPM, and presence message can be used.

FIG. 5is a process flow diagram of a method for automatically detecting retimer presence and index. At block502, a link is initialized. In some cases, the link is an active cable. In embodiments, the link is a dual-simplex link that forms a closed loop between an upstream port104and a downstream port102. At block504, each retimer asserts a bit of a message sent during initialization of the link. In embodiments, the message sent during initialization is a defined message according to the link protocol. Additionally, in embodiments, the retimer asserts a bit in a reserved field of the defined message. The defined message is any message according to the protocol supported by the ports. In embodiments, the message is an LBPM sent during initialization according to the USB 3.1 protocol.

FIG. 6is a process flow diagram of a method for accessing a retimer. At block602, the retimer declares an index via a presence message. At block604, the retimer is accessed via an address corresponding to the index. As discussed above, the retimer can asserts a bit in a reserved field of the presence message to announce the present of the retimer and declare an index. In embodiments, the presence message is an LBPM sent during initialization according to the USB 3.1 protocol. The presence message may be combined with any defined message, such as a Capability Message as defined according to a USB3.1 standard.

FIG. 7is a block diagram of an exemplary computer system700. The system700includes a processor with execution units to execute an instruction, where one or more of the interconnects implement one or more features in accordance with one embodiment of the present invention is illustrated. The system700includes a component, such as a processor702to employ execution units708including logic to perform algorithms for process data, in accordance with the present invention, such as in the embodiment described herein. In some cases, system700is representative of processing systems based on the PENTIUM III™, PENTIUM 4™, Xeon™, Itanium, XScale™ and/or StrongARM™ microprocessors available from Intel Corporation of Santa Clara, Calif., although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and the like) may also be used. In embodiments, system700executes a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used. Thus, embodiments of the present invention are not limited to any specific combination of hardware circuitry and software.

The embodiments described herein are not limited to computer systems. Alternative embodiments of the present techniques can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications can include a micro controller, a digital signal processor (DSP), system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform one or more instructions in accordance with at least one embodiment.

In this illustrated embodiment, processor702includes one or more execution units708to implement an algorithm that is to perform at least one instruction711. One embodiment may be described in the context of a single processor desktop or server system, but alternative embodiments may be included in a multiprocessor system. System700is an example of a ‘hub’ system architecture. The computer system700includes a processor702to process data signals. The processor702, as one illustrative example, includes a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. The processor702is coupled to a processor bus710that transmits data signals between the processor702and other components in the system700. The elements of system700(e.g. graphics accelerator712, memory controller hub716, memory720, I/O controller hub725, wireless transceiver726, Flash BIOS728, Network controller734, Audio controller736, Serial expansion port738, I/O controller740, etc.) perform their conventional functions that are well known to those familiar with the art.

In one embodiment, the processor702includes a Level 7 (L1) internal cache memory704. Depending on the architecture, the processor702may have a single internal cache or multiple levels of internal caches. Other embodiments include a combination of both internal and external caches depending on the particular implementation and needs. Register file706is to store different types of data in various registers including integer registers, floating point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and instruction pointer register.

Execution unit708, including logic to perform integer and floating point operations, also resides in the processor702. The processor702, in one embodiment, includes a microcode (ucode) ROM to store microcode, which when executed, is to perform algorithms for certain macroinstructions or handle complex scenarios. Here, microcode is potentially updateable to handle logic bugs/fixes for processor702. For one embodiment, execution unit708includes logic to handle a packed instruction set709. By including the packed instruction set709in the instruction set of a general-purpose processor702, along with associated circuitry to execute the instructions, the operations used by many multimedia applications may be performed using packed data in a general-purpose processor702. Thus, many multimedia applications are accelerated and executed more efficiently by using the full width of a processor's data bus for performing operations on packed data. This potentially eliminates the need to transfer smaller units of data across the processor's data bus to perform one or more operations, one data element at a time.

Alternate embodiments of an execution unit708may also be used in micro controllers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System700includes a memory720. Memory720includes a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or other memory device. Memory720stores instructions711and/or data713represented by data signals that are to be executed by the processor702.

Note that any of the aforementioned features or aspects of the present techniques may be utilized on one or more interconnects illustrated inFIG. 7. For example, an on-die interconnect (ODI), which is not shown, for coupling internal units of processor702implements one or more aspects of the invention described above. The invention is associated with a processor bus710(e.g. Intel Quick Path Interconnect (QPI) or other known high performance computing interconnect), a high bandwidth memory path718to memory720, a point-to-point link to graphics accelerator714(e.g. a Peripheral Component Interconnect express (PCIe) compliant fabric), a controller hub interconnect722, and an I/O or other interconnect (e.g. USB, PCI, PCIe)730A,730B,730C,730D,730E, and730F for coupling the other illustrated components. Some examples of such components include the audio controller736, firmware hub (flash BIOS)728, wireless transceiver726, data storage724, legacy I/O controller710containing user input and keyboard interfaces742, a serial expansion port738such as Universal Serial Bus (USB), and a network controller734. The data storage device724can comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

The block diagram ofFIG. 7is not intended to indicate that the computing device700is to include all of the components shown inFIG. 7. Further, the computing device700may include any number of additional components not shown inFIG. 7, depending on the details of the specific implementation.

An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer. The apparatus also includes control associated with the retimer to assert at least one bit of a presence message during link initialization to announce the retimer's presence.

The at least one retimer may declare an index and is accessible via the index. The control may be based on a bubble algorithm to assert at least one bit of the presence message. Additionally, the at least one retimer is to synchronize and regenerate deteriorated signals from a receiving port to a transmitting port. The at least one retimer may be configurable and discoverable, and the at least one retimer may support multiple protocols. Further, the at least one retimer may control acquisition and transmission of received signals. The at least one retimer may be a USB 3.1 retimer. The apparatus may include a plurality of retimers, wherein a first retimer is a component of a host, a second retimer is a component of a device, and two retimers are situated at each end of a cable that is to connect the host and the device. A first presence message from the host to the device enables each retimer to declare an index from the host to the device, and a second presence message from the device to the host enables each retimer to declare an index from the device to the host.

A system for retimer presence detection and indexing is described herein. The system includes a first port, a second port, and a plurality of retimers. A link including a retimer of the plurality of retimers is to connect the first port and the second port and logic is to enable the plurality of retimers to announce their presence by asserting a bit of a presence message during link initialization and to declare an index based on the presence message.

Each retimer of the plurality of retimers declares an index and may accessible via the index. The logic may be based on a bubble algorithm. Each retimer of the plurality of retimers may also synchronize and regenerate deteriorated signals from a receiving port to a transmitting port. Further, the presence message may be an LFPS Based Pulse-width modulation Message (LBPM). The plurality of retimers may to support multiple protocols. Further, the plurality of retimers may to declare an index and announce their presence by asserting a bit of a presence message during link initialization from the first port to the second port, and vice versa. The link may an active cable, and the plurality of retimers may be USB 3.1 retimers. The logic may determine the link configuration.

A method of retimer presence and detection is described herein. The method includes initializing a link between a first port and a second port, wherein a plurality of retimers are located between the first port and the second port. The method also includes sending a presence message between the first port and the second port, wherein logic is to enable the plurality of retimers to announce their presence by asserting a bit of a presence message during link initialization and to declare an index based on the presence message.

The logic may be based on a bubble algorithm, and each retimer asserts the bit of the presence message before forwarding the presence message along the link. The presence message may be combined with a defined message. Additionally, the link may be an active cable. The presence message may be an LFPS Based Pulse-width modulation Message (LBPM). The first port and the second port may each support multiple protocols. Also, the first port and the second port may be USB 3.1 ports. The logic can be implemented concurrently with the link initialization. The LFPS Based Pulse-width modulation Message (LBPM) may be a Capability message. The plurality of retimers can prevent signal deterioration along the link.

An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein the retimer includes a means to announce the retimer's presence during link initialization.

The means to announce the retimer's presence may assert a bit of a presence message. The means to announce the retimer's presence may also declare an index and may be accessible via the index. The means to announce the retimer's presence can assert a bit of a presence message via an algorithm, and the means to announce the retimer's presence can be based on a bubble algorithm. The at least one retimer may synchronize and regenerate deteriorated signals from a receiving port to a transmitting port. Further, the at least one retimer may be configurable and discoverable using the means to announce the retimer's presence. The at least one retimer may support multiple protocols. The at least one retimer may control acquisition and transmission of received signals. Additionally, the at least one retimer may be a USB 3.1 retimer. The apparatus may include a plurality of retimers, wherein a first retimer may be a component of a host, a second retimer may be a component of a device, and two retimers are situated at each end of a cable that may connect the host and the device. A first presence message from the host to the device may enable each retimer to declare an index from the host to the device, and a second presence message from the device to the host may enable each retimer to declare an index from the device to the host.

A tangible, non-transitory, computer-readable medium is described herein. The tangible, non-transitory, computer-readable medium includes code to direct a processor to initialize a link between a first port and a second port, wherein a plurality of retimers are located between the first port and the second port. The tangible, non-transitory, computer-readable medium also includes code to direct a processor to send a presence message between the first port and the second port, wherein logic is to enable the plurality of retimers to announce their presence by asserting a bit of a presence message during link initialization and to declare an index based on the presence message.

The logic may be based on a bubble algorithm, and each retimer may assert the bit of the presence message before forwarding the presence message along the link. The presence message may be combined with a defined message, and the link may be an active cable. The presence message can be an LFPS Based Pulse-width modulation Message (LBPM). The first port and the second port can each support multiple protocols. The first port and the second port may be USB 3.1 ports. Additionally, the logic may be implemented concurrently with the link initialization. The LFPS Based Pulse-width modulation Message (LBPM) may be a Capability message. The plurality of retimers can prevent signal deterioration along the link.

An apparatus is described herein. The apparatus includes a retimer for a high speed serial interconnect. The retimer includes, but not limited to a receiver, a control, and a transmitter. The receiver is to receive a message that is to include a particular field, and the control is to update the particular field with a retimer value to announce a presence of the retimer inband. The transmitter is to transmit a message to include the particular field.

The control may update the particular field based on a bubble algorithm Updating the particular field may include asserting a bit of the particular field. Additionally, updating the particular field may include a logical shift of at least one bit of the particular field. The transmitter may be coupled to an upstream device. The upstream device may include a control to determine a number of retimers along the high speed serial interconnect, the number of retimers based on the retimer value, and perform retimer access based on the retimer's relative indexing with respect to the number of retimers.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.