Semiconductor package with chip supporting structure

A semiconductor package with a chip supporting structure is provided, including a lead frame having a die pad and a plurality of leads, and a plurality of chip supporting members mounted on the die pad. Each of the chip supporting members has a first surface and an opposing second surface and has an identical height. After the second surfaces of the chip supporting members are attached to the die pad, the first surfaces of the chip supporting members are coplanarly arranged, and a chip is mounted on the first surfaces of the chip supporting members, making the chip supporting members interposed between the chip and die pad. A molding resin for encapsulating the chip is allowed to penetrate through and fill into gaps between the chip and die pad, so as to prevent void formation and assure quality of fabricated products.

FIELD OF THE INVENTION

The present invention relates to semiconductor packages, and more particularly, to a semiconductor package using a die pad of a lead frame as a chip carrier, especially applicable to a lead frame with a window pad.

BACKGROUND OF THE INVENTION

A lead-frame-based semiconductor package using a lead frame as a chip carrier usually renders a reliability issue in terms of thermal stresses being generated due to mismatch in CTE (coefficient of thermal expansion) between a chip and a silver paste for attaching the chip to the lead frame and between the silver paste and the lead frame. In particular, the chip is mounted on a die pad of the lead frame via the silver paste and encapsulated by an encapsulant; due to different CTEs (chip: about 4 ppm, silver paste: about 40 ppm, die pad: about 16 ppm), significant thermal stresses would be induced at interfaces between the chip and silver paste and between the silver paste and die pad, such that under temperature variation in a reliability test or practical operating environment, the semiconductor package may be subject to delamination and chip cracks by effect of thermal stresses, making quality of the semiconductor package undesirably degraded. This situation is more severe in the use of a larger die pad or chip in which contact area between the die pad and chip is increased and the die pad would suffer greater thermal stresses during a temperature cycle, thereby resulting in warpage and poor planarity of the die pad and further causing delamination between the chip and die pad.

In response to the above problems, U.S. Pat. Nos. 5,233,222, 5,327,008 and 5,521,428 disclose a semiconductor package having a die pad being formed with at least an opening. As shown inFIGS. 9A and 9B, this semiconductor package4utilizes a die pad400formed with at least an opening402of a flexible shape such as round, rectangle, square, etc. As such, when a chip42is mounted on the die pad400via a silver paste45, the chip42covers the opening402with its non-active surface being partly exposed to the opening402, making area applied with the silver paste45between the chip42and die pad400effectively reduced; this thereby reduces thermal stress effect on the chip42and die pad400so as to prevent delamination between the same or chip cracks from occurrence. In another aspect, with provision of the opening402, the chip42would be indirect contact with a molding compound (CTE: about 14 ppm) used for forming an encapsulant44that encapsulates the chip42; relatively smaller CTE mismatch between the chip42and encapsulant44helps prevent delamination and thereby assures structural intactness of the semiconductor package4during fabrication processes.

Besides the above benefits accomplished by the semiconductor package4, however, during a process for applying the silver paste45used to attach the chip42to the die pad400, it is necessary to precisely control an applied amount of the silver paste45in order not to affect subsequent packaging processes of the chip42. As shown inFIG. 10A, if an excess amount of silver paste45is used, when the chip42is mounted to and presses on the silver paste45, a portion of the silver paste45would leaks downwardly from a periphery of the opening402and flashes to a bottom surface of the die pad400, which would adversely affect bonding between the bottom surface of the die pad400and the encapsulant44. On the other hand, as shown inFIG. 10B, if an insufficient amount of silver paste45is applied, gaps G may be formed between the chip42and die pad400and normally of a size smaller than 1 mil (about 25.4 μm). Such gaps G failed to be filled or penetrated by a resin compound whose filler size is usually larger than 1 mil during a molding process for fabricating the encapsulant44. Moreover, these considerably small gaps G would impede flowing of the resin compound, making air trapped between the chip42and die pad400not capable of being dissipated and thus form voids, such that the encapsulant44may encounter popcorn effect by virtue of voids in a high temperature environment and thus damages structures of the chip42and semiconductor package4. Therefore, either flashes of the silver paste45or formation of voids would undesirably affect yield and reliability of fabricated package products. However, in respect of precisely controlling a used amount of the silver paste45, it requires improvement in process accuracy or preciseness and thereby increases fabrication costs, which still may not completely eliminate the occurrence of paste flashes or voids.

Moreover, the above die pad400formed with the opening402needs to be fabricated in compliance with size and shape of the chip42, making fabrication costs undesirably increased. For a highly integrated chip of a larger size, if such a larger chip is directly attached to the die pad, this would increase contact area between the chip and die pad and thermal stress effect on the chip and die pad, making adhesion at interfaces between the chip and silver paste and between the silver paste and die pad adversely degraded.

SUMMARY OF THE INVENTION

A primary objective of the present invention is to provide a semiconductor package with a chip supporting structure, which can prevent direct contact between a chip and a die pad, to thereby eliminate chip cracks, delamination between the chip and die pad, and warpage of the die pad in response to thermal stresses, so as to improve quality of the semiconductor package.

Another objective of the invention is to provide a semiconductor package with a chip supporting structure, whereby it is not necessary to fabricate a die pad in compliance with profile of a chip, such that process complexity and costs can be reduce for fabrication of the semiconductor package.

A further objective of the invention is to provide a semiconductor package with a chip supporting structure, which allows a molding compound to fill into gaps between a chip and a die pad to eliminate formation of voids in the gaps.

A further objective of the invention is to provide a semiconductor package with a chip supporting structure for effectively preventing flashes of a silver paste over unintended area such as a bottom surface of a die pad in the semiconductor package.

In accordance of the foregoing and other objectives, the present invention proposes a semiconductor package with a chip supporting structure, comprising: a lead frame having at least a die pad and a plurality of leads; a plurality of chip supporting members each having a first surface and a second surface opposed to the first surface and each having an identical height, wherein the second surfaces of the chip supporting members are attached to the die pad, making the first surfaces of the chip supporting members flush with each other; a chip mounted on the first surfaces of the chip supporting members and electrically connected to the lead frame; and an encapsulant for encapsulating the chip supporting members, chip and lead frame.

The chip supporting members can be flexibly sized and provided in a quantity thereof. In order to allow a molding compound used for forming the encapsulant to penetrate through gaps between the chip and die pad, each of the chip support members preferably has a height larger than a minimum distance (generally about 3 mils) capable of being penetrated by fillers of the molding resin.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of a semiconductor package with a chip supporting structure proposed in the present invention are described in detail with reference toFIGS. 1 to 8.

First Preferred Embodiment

As shown inFIG. 1, the semiconductor package1with a chip supporting structure according to a first preferred embodiment of the invention includes a lead frame10having at least a die pad100and a plurality of leads101; a plurality of chip supporting members11attached to the die pad100; a chip12mounted on the chip supporting members11; a plurality of bonding wires13(such as gold wires) for electrically connecting the chip12to the leads101; and an encapsulant14for encapsulating the chip supporting members11, chip12, bonding wires13and part of the lead frame10.

The lead frame10is made of a metal material such as copper or copper alloy, and is composed of a die pad100and a plurality of leads101around the die pad100. The die pad100can be a full pad, or a window pad formed with at least an opening penetrating through a top surface100aand a bottom surface100bof the die pad100; such an opening can be flexibly shaped as round, rectangle, square or X-shape, etc.

The chip supporting member11can be made of a dummy die of a material same as the chip12, a metal plate (such as copper, aluminum, etc.), or a polymer material having a coefficient of thermal expansion (CTE) similar to that of the chip12. In this embodiment, as shown inFIG. 2, the chip supporting member11can be a cylindrical or square column processed by cutting and grinding, and has a first surface110and a second surface111opposed to the first surface110. Each of the plurality of chip supporting members11has an identical height H. A silver paste15is applied over the second surfaces111of the chip supporting members11for attaching the plurality of chip supporting members11to the top surface100aof the die pad100in a manner that the first surfaces110of the chip supporting members11are flush with each other. Therefore, during a die-bonding process, the silver paste15can be simultaneously applied over the first surfaces110of the chip supporting members11for mounting the chip12thereon by which the chip supporting members11are interposed between the chip12and die pad100and space apart the chip12and die pad100by a distance d, as shown inFIG. 1. The height H of the chip supporting member11is larger than a minimum distance (generally about 3 mils) capable of being penetrated by fillers of a resin used for forming the encapsulant14.

Moreover, the chip supporting members11are flexibly arranged on the die pad100in two strips (as shown inFIG. 3), at four corner portions (as shown inFIG. 4), or at other positions easily subject to delamination (such as positions corresponding to chip corners, as shown inFIG. 5). Under a condition not to affect attachment between the chip12and die pad100, each of the chip supporting members11can be flexibly shaped and oriented without particular limitation.

Therefore, as the chip12is elevated above the die pad100via the chip supporting members11by a height difference, during a molding process for fabricating the encapsulant14, a melted molding resin (not shown) can fill into gaps between the chip12and die pad100without forming voids in the gaps, thereby helping assure reliability of fabricated package products. Furthermore, as contact area between the chip12and chip supporting members11and between the die pad100and chip supporting members11can be effectively decreased, it would facilitate reduction of thermal stress effect generated under a subsequent temperature cycle, thereby preventing chip cracks and delamination at attachment interfaces in the semiconductor package1.

Second Preferred Embodiment

FIG. 6illustrates a semiconductor package according to a second preferred embodiment of the invention. As shown in the drawing, this semiconductor package is similar in structure to that of the first preferred embodiment, with the difference in that the die pad200is formed with at least an opening202, and a periphery of the opening202can be shaped as stairs or gradients without particular limitation; this is to help reduce flow resistance during filling of a molding resin (not shown) and prevent formation of voids in gaps between the chip supporting members21being filled by the molding resin. Moreover, the opening202with the stair- or gradient-shaped periphery can also anchor the silver paste25and prevent the silver paste25from contaminating unintended area such as a bottom surface of the die pad200and leading to delamination. It should be understood that, besides formation of the opening202, other structural designs or arrangements of the die pad200without affecting incorporation of the chip supporting member21on the die pad200are also included within the scope embraced by this invention.

Third Preferred Embodiment

FIGS. 7 and 8illustrate a semiconductor package according to a third preferred embodiment. This semiconductor package3,3′ is similar in structure to that of the first preferred embodiment, with the difference in that the lead frame30,30′ is suitably used in a quad flat non-leaded (QFN) package3or an exposed pad package3′. As shown inFIG. 7, the die pad300and leads301of the lead frame30in the QFN package3are coplanarly arranged, and a bottom surface300bof the die pad300and bottom surfaces of the leads301are exposed to outside of the encapsulant34. As shown inFIG. 8, for the lead frame30′ in the exposed pad package3′, a bottom surface300b′ of the die pad300′ is also exposed to outside of the encapsulant34′ and helps enhance heat dissipating efficiency for the chip32′. Moreover, since the chip supporting members31,31′ can be mounted at any desirable positions on the die pad300,300′, it can be applicable in other types of package structures such as QFP (quad flat package), SOP (small outline package), DIP (dual inline package) and other lead-frame-based packages in which the chip supporting members31,31′ space apart the chip32,32′ and die pad300,300′ to facilitate penetration and flowing of a resin compound under the chip32,32′.