Sensitive high speed solid state preamp

A preamp for coupling to an avalanche photodiode (APD) of an optical receiver has an input stage including a dual gate field effect transistor (FET) and a single gate FET coupled in a cascade arrangement. The dual gate FET has its first gate coupled to the output of the APD, its second gate and source grounded, and its drain driving the gate of the single gate FET in a cascade arrangement. The source of the single gate FET is level-shifted and coupled by means of a feedback resistor to the first gate of the dual gate FET to provide a negative feedback. The output stage is a third FET with its gate coupled through a blocking capacitor to the source of the single gate FET in the input stage and with its drain providing the output of the preamp. In a preferred embodiment, the FETs used are GaAs FETs (GAASFETs).

BACKGROUND OF THE INVENTION 
A. Field of the Invention 
This invention relates to the field of electronics and more particularly to 
the field of solid state preamps for optical receivers. 
B. Description of the Prior Art 
The efficient use of laser communications, particularly for satellites, 
requires the development of a very sensitive and very high speed (gigabit 
data rate) optical receiver which is compact and lightweight. Prior 
receivers of high sensitivity and speed were not completely solid state 
and, hence, were bulky and not acceptable for use in satellites. Until the 
present invention, no reliable, completely solid state receiver could 
approach the sensitivity and speed required for efficient laser 
communications. 
SUMMARY OF THE INVENTION 
It is an object of the invention to provide a preamp having high 
sensitivity for use with a high speed avalanche photodiode. 
It is a further object of the invention to provide a preamp having a very 
wide signal bandwidth for use with a high speed avalanche photodiode. 
It is an object of this invention to provide an all solid state preamp 
having high sensitivity and a very wide signal bandwidth. 
It is an additional object of the invention to provide a solid state 
receiver for use in laser communications. 
According to the invention, the preamp of an optical receiver has an input 
stage including a dual gate field effect transistor (FET) and a single 
gate FET coupled in a cascade arrangement (preferably GaAs FETs). The dual 
gate FET has its first gate coupled to the output of the ADP, its second 
gate and source grounded, and its drain driving the gate of the single 
gate FET in a cascade arrangement. The source of the single gate FET is 
level-shifted and coupled by means of a feedback resistor to the first 
gate of the dual gate FET to provide a negative feedback. The output stage 
is a third FET with its gate coupled through a blocking capacitor to the 
source of the single gate FET in the input stage and with its drain 
providing the output of the preamp. 
These and other objects and features of the present invention will be 
apparent from the following detailed description, taken with reference to 
the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Two fundamental limitations to the sensitivity of a preamp for detecting 
photocurrent pulses exist: (1) The voltage noise-input capacitance limit; 
and (2) the Johnson or thermal noise current in the load or feedback 
resistance. If a photodiode with junction capacitance C.sub.J is connected 
to a preamp with input capacitance C.sub.IN, then a charge pulse Q.sub.P 
from the photodiode will produce a voltage change .DELTA.V .ltoreq. 
Q.sub.P /(C.sub.J + C.sub.IN) (where the .ltoreq. is used since there may, 
in general, be other shunt conductances). If the preamp has a total rms 
input voltage noise e.sub.n, then the minimum detectable charge pulse 
(amount of charge required to make .DELTA.V = e.sub.n) will be Q.sub.MI 
.gtoreq. e.sub.n (C.sub.J + C.sub.IN), or in terms of the number of 
electrons, 
EQU N.sub.o .gtoreq. e.sub.n (C.sub.J + C.sub.IN)/q (1) 
where N.sub.o is the "minimum detectable current pulse" or number of 
electrons in a current impulse required to make the voltage change equal 
the rms noise (q = 1.602 .times. 10.sup.-19 coul). 
As shown by Equation 1, to attain high pulse sensitivity in a preamp for a 
receiver (that is, low N.sub.o) the preamp must have a low input voltage 
noise combined with a total input capacitance (preamp plus photodiode) 
that is extremely small. In practice, the input voltage noises for 
wideband amplifying devices of high quality are not widely different, so 
that the principal way to reduce N.sub.o is to reduce the capacitance 
(C.sub.J + C.sub.IN). This means that the detector with which the preamp 
is used should have a low junction capacitance C.sub.J and negligible 
series resistance. This capacitance advantage can be maintained by 
utilizing field effect transistors (FETs) which also have low input 
capacitance, such as GaAs FETs (GAASFETs). As discussed later, other FETs 
can be utilized; however, they will result in different performance levels 
for the preamp depending upon their electrical characteristics. 
To improve the preamp sensitivity (reduce N.sub.o), the Johnson noise 
current in the load resistor, i.sub.nj = .sqroot.4KT.DELTA.F/R must be 
reduced. The increase in R allowed, for the same bandwidth, by reducing 
(C.sub.J + C.sub.IN) helps, but is insufficient to achieve the two order 
of magnitude increase in R required to achieve a one order of magnitude 
reduction in I.sub.nj. In a feedback mode, or transimpedance-type of 
amplifier with open-loop gain A, the 3db bandwidth is given by f.sub.3db = 
A/2.pi.R.sub.F (C.sub.J + C.sub.IN), as compared with f.sub.3db = 1/2.pi. 
R.sub.L (C.sub.J + C.sub.IN) for a simple load resistor configuration. 
Hence, by going to a feedback mode FET preamp with A = 10 having an order 
of magnitude lower (C.sub.J + C.sub.IN) than a simple bipolar transistor 
preamp, R can be increased by two orders of magnitude and i.sub.nj and 
N.sub. o reduced by at least an order of magnitude. 
For gigabit and higher data rate applications or very short pulse 
detection, it is essential that the operational amplifier stage ("op-amp" 
stage) of the preamp have wide, closed-loop bandwidth and large values of 
feedback resistance R.sub.F. Detailed analysis of experimental single FET 
"op-amp" stage preamps leading to the present invention indicated that the 
principal problem was that the loading capacitance, C.sub.L, on the FET 
was too large and limited the high frequency performance. This problem 
with the experimental designs stems from the fact that the single FET does 
not represent a true operational amplifier because it does not have low 
output impedance. Hence, the loading effect of C.sub.L degrades the 
"op-amp" gain bandwidth. 
In the preamp of the present invention, the input stage 2 is a two FET 
(Q.sub.1, Q.sub.2) true operational amplifier with low output impedance, 
as shown in the simplified circuit diagram, FIG. 1. The gate G.sub.1, of 
the first FET Q.sub.1, is coupled to the preamp input which is shown as 
avalanche photodiode 4. Light, hv, striking the APD creates the signal for 
the preamp. The source S.sub.1 of the first FET is grounded and the drain 
D.sub.1 is connected in parallel to a positive voltage +V.sub.D.sbsb.1 and 
to the gate G.sub.2 of a second FET Q.sub.2. The level shifted V.sub.z 
output from source S.sub.2 is fed back through feedback resistance R.sub.F 
to the input G.sub.1 of the first FET Q.sub.1. The drain D.sub.2 is 
connected to a positive voltage +V.sub.D.sbsb.2. 
The output stage 6 comprises a third FET Q.sub.3 with a grounded source 
S.sub.3 and a gate G.sub.3, coupled to the source S.sub.2 of the second 
FET through a blocking capacitor C.sub.B. While in FIGS. 1 and 2 C.sub.B 
is shown connected to the top (positive side) of V.sub.z, connecting 
C.sub.B to the bottom (negative side) of V.sub.z is actually preferable in 
that low frequency noise on the zener is reduced by feedback in the latter 
configuration, as shown in FIG. 1a. The drain D.sub.3 of the output stage 
FET is connected in parallel to a positive voltge +V.sub.D.sbsb.3 through 
an internal load termination and to the output load 8 of the preamp 
through a transmission line. 
FIG. 2 is a circuit diagram of a preferred embodiment of the preamp coupled 
to an APD 10 at its input and also including a test input loop 12 and a 
test input-out circuit 14. The electrical components in FIG. 2 performing 
similar functions as the components described in FIG. 1 are similarly 
identified. 
The input stage 16 is an "op-amp" voltage gain stage in a cascade 
arrangement with a grounded source FET Q.sub.1 driving a source follower 
FET Q.sub.2. Q.sub.1 is a dual-gate FET with its second gate 
G.sub.1.sbsb.g grounded in order to obtain a high drain output resistance 
which is necessary to achieve high open-loop voltage gain. The use of a 
dual-gate FET Q.sub.1 operated with the second gate G.sub.1.sbsb.g 
grounded, is an operational equivalent of a cascode arrangement of two 
single gate FETs. From a functional standpoint, the input stage 16, with 
dual-gate FET as Q.sub.1, is effectively a three-FET cascode-cascade 
amplifier (grounded source-grounded gate-grounded drain). 
The output from Q.sub.2 is level-shifted by level-shifter zener diode 
V.sub.z and is the output feedback to the input, gate G.sub.1, through 
feedback resistor R.sub.F. Because of this closed-loop negative feedback 
mode of operation of this Q.sub.1 - Q.sub.2 "op-amp," stability can only 
be guaranteed if the sum of the phase shifts in Q.sub.1, Q.sub.2 and the 
feedback resistor (R.sub.F) to input capacitance (C.sub.J + C.sub.IN) 
network is less than 180.degree., at any frequency for which the open-loop 
gain exceeds unity. The use of very wide gain-bandwidth product FETs for 
Q.sub.1 and Q.sub.2 such as GaAs FETs and careful control of the feedback 
capacitance in parallel with R.sub.F assure stable, high speed response. 
It should be noted that operation of Q.sub.1, which has a breakdown voltage 
of the order of V.sub.DS.about. 10 volts from a 45-volt power supply, 
represents a dangerous condition in that if V.sub.gl becomes too negative, 
V.sub.D2 will rise and Q.sub.1 will breakdown, possibly destructively. In 
order to avoid this possible disaster, a diode is connected from the drain 
of Q.sub.1 to a +5 volt zener-limited potential. This diode is normally 
reverse biased, but if V.sub.D1 exceeds 5.5 volts or so, this diode will 
begin conducting and keep V.sub.D1 from exceeding a safe V.sub.DS = 6 
volts. The diode used is a special ultra low capacitance (&lt;0.05pf) 
beamleaded GaAs Schottky barrier mixer diode. An alternate approach would 
be to put this drain voltage limiting diode on the source side of Q.sub.2, 
assuming that it is safe to pass the full drain current of Q.sub.1 
(I.sub.D2 .about. V.sub.D1 /R.sub.L) as a forward current through the gate 
of Q.sub.2 without damaging Q.sub.2. 
The output stage 18, shown in FIG. 2, is a single gate FET Q.sub.3 which is 
coupled by a blocking capacitor C.sub.B to the input stage 16 (again 
C.sub.B might better be coupled to the lower, negative side of V.sub.z 
than the upper side as shown). The drain D.sub.3 of the FET Q.sub.3 is 
directly coupled to the 50.OMEGA. output line, with the dc balance 
adjusted by a trimpot in the power supply controlling the dc bias on 
G.sub.3. The output stage 18 of the preamp has its own internal 
termination 22 with its resistance selected so that the parallel 
combination of the resistance of the internal termination and the drain 
resistance of FET Q.sub.3 is 50 ohms, the transmission line impedance. As 
a result, signal reflections from the following amplifiers will be 
absorbed in the internal termination and will not cause intersymbol 
interference in communications applications. 
The purpose of the output stage 18 is to serve as a low capacitance buffer 
between the high impedance of the Q.sub.2 drain and the 50.OMEGA. output 
impedance. To Q.sub.2, Q.sub.3 looks like a capacitive load (often 
referred to as C.sub.L) and C.sub.L must be kept small in order that an 
acceptable bandwidth be maintained in the input stage 16. For this reason, 
a GaAs FET is used for Q.sub.3 as well as for Q.sub.1 and Q.sub.2. In 
addition, the hybrid circuit layout is optimized for low stray 
capacitance. 
FIG. 3 is a functional block diagram of the preamp according to the 
embodiment shown in FIG. 2. The input stage 16 is coupled to an APD 10 and 
the output stage 18 is coupled to the input stage by coupling capacitor 
C.sub.B. 
FIG. 4 is a circuit diagram for a power supply monitor for the preamp when 
used in an optical receiver 22. Trimpot 20 is used to adjust the dc 
balance of the gate G.sub.3 of FET Q.sub.3 in the output stage 18 of the 
preamp shown in FIG. 2. 
FIG. 5 is a perspective view of an optical receiver 22 utilizing the preamp 
of the invention. The receiver includes an opening 26 for light entrance 
to the APD, a signal output port 28, ports for test loops 30, 32, 34, and 
power supply leads 36. The fins 38 are used to help keep the temperature 
of the APD constant. 
In a preferred first embodiment, the three FETs Q.sub.1, Q.sub.2, Q.sub.3 
are GaAs Schottky barrier FETs (GAASFETS) identified commercially and 
having electrical characteristics as given in Table 1 below. 
TABLE I 
__________________________________________________________________________ 
Drain 
Gate Type 
Resistance 
Transconductance 
Stage 
GAASFET Identity 
Size R.sub.D 
gm 
__________________________________________________________________________ 
Q.sub.1 
Hitachi HCRL-94 
Dual 1.mu. 
.about.1700.OMEGA. 
11.1 mmhos at I.sub.D 
of 13 mA (gate 1) 
Q.sub.2 
Fairchild FMX 950 
Single 2.mu. 
600-800.OMEGA. 
12.1 mmhos at I.sub.D 
of 10.5 mA 
Q.sub.3 
Nippon Electric 
Single 1.mu. 
250-400.OMEGA. 
13.2 mmhos at I.sub.D 
NEC V244 of 17 mA 
__________________________________________________________________________ 
In a preferred second embodiment, a better GAASFET (an NEC V463) for stage 
Q.sub.1 is used which has higher transconductance (18.1 mmhos at at 
I.sub.D of 13.3 mA bias current) and a higher drain resistance R.sub.D of 
2200.OMEGA.. This gives a preamp with higher transimpedance and even lower 
noise, as shown in Table II below: 
TABLE II 
______________________________________ 
PREAMP CHARACTERISTICS 
First Second 
Characteristic Embodiment Embodiment 
______________________________________ 
Open-loop "op-amp" gain 
10.8 19.5 
Open-loop F.sub.3dB (O.L.) 
275 MHz 320 MHz 
Open-loop gain-bandwidth 
.about.2.2-3 GHz 
5 GHz 
Feedback Resistance, R.sub.f 
2500.OMEGA. 5000.OMEGA. 
Transimpedance, 2290.OMEGA. 4750.OMEGA. 
R.sub.o (V.sub.f /i.sub.p) 
3db bandwidth (closed- 
596 MHz 620 MHz 
loop) F.sub.3dB 
RMS output noise through 
12.81 mV rms 
12.15 mV 
cascaded B&H preamps, 
375 KHz to 375 KHz to 
3GH.sub.z B.W. 3 GHz 3 GHz 
Minimum detectable 
782 electrons 
347 electrons 
current pulse (numbers 
375 KHz to 375 KHz to 
of electrons to give 
3 GHz 3 GHz 
peak output equal to 
rms noise output). 
Input capacitance 
.75 pf .28 pf 
______________________________________ 
Other embodiments of the invention may utilize other types of FETs. For 
example, preamps can be constructed utilizing Schottky barrier gate type 
FETs, junction type FETs, and heterojunction gate type FETs. Such FETs can 
be made from GaAs, InP, and other suitable alloys from the Group III-V 
elements. Even silicon Schottky gate type FETs can be utilized, although 
preamp performance will be less than shown for preamps using GaAs FETs. 
The low input capacitance of the preamp, together with its very high speed 
and extreme charge-sensitivity, make it ideal for use in laser 
communication at gigabit data rates utilizing an avalanche photodiode 
having a very low junction capacitance. Depending upon the wavelength 
used, the preamp is suitable for use with any avalanche photodiode having 
low junction capacitance. The preamp has been used with a special inverted 
homo-heterojunction GaAs.sub.1-x Sb.sub.x avalanche photodiode sensitive 
to a 1.064.mu. light signal and having a junction capacitance C.sub.J of 
0.1 pf and peak avalanche gains up to 24 dB at 273 MHz. However, the 
preamp is suitable for use with any avalanche photodiode or signal source 
having a low junction capacitance, preferably less than 0.2 pf. 
Numerous variations and modifications may be made without departing from 
the present invention. Accordingly, it should be clearly understood that 
the form of the present invention described above and shown in the 
accompanying drawings is illustrative only and is not intended to limit 
the scope of the present invention.