Method and apparatus for current-output peak detection

A method and apparatus for a current-output peak detector. A current-output peak detector circuit is disclosed and works in two phases. The peak detector circuit includes switches to switch the peak detector circuit from the first phase to the second phase upon detection of the peak voltage of an input voltage signal. The peak detector generates a current output with a high degree of accuracy in the second phase.

FIELD OF THE INVENTION

The present invention relates to peak detection, and more particularly to a method and apparatus for current-output peak detection.

BACKGROUND

FIG. 1illustrates a block diagram of a prior art front-end circuit for a radiation detector. The circuit includes a low-noise charge amplifier102, a filter104, and a peak detector106. A charge signal Q from a sensor of the radiation detector is amplified by the charge amplifier102and filtered by the filter104, yielding a voltage pulse v(t) with an amplitude proportional to the charge Q. The voltage pulse is processed by the peak detector106which yields a constant voltage vp(t) equal to the peak pulse amplitude U. The constant voltage is then processed by further voltage-input processing electronics108, such as a voltage-input Analog-to-Digital converter.

The peak detector106inFIG. 1is only capable of operating with voltage-input processing electronics108. If a current-input processing device or circuit is required, such as a current-input Analog-to-Digital converter, a stage which converts the voltage vp(t) into a current is required. Such an additional stage utilizes additional power.

Moreover, in order to maximize the dynamic range of the analog front-end circuit, the peak detector106must be able to operate rail-to-rail, i.e. it must be able to process voltages that swing from the minimum (typically ground) supply voltage to the maximum supply voltage, while preserving the required detection precision. Such a rail-to-rail circuit can be affected by non-linear errors due to voltage offsets at the complementary differential input stages, resulting in low-precision peak detection.

In U.S. Pat. No. 6,512,399, which is herein incorporated by reference in its entirety as if fully set forth in this disclosure, G. De Geronimo et al. disclosed a high-precision peak detector capable of operating rail-to-rail by using an offset-cancellation method. However, the disclosed circuit operates with voltage-input processing electronics, and one or more additional stages which precisely convert the voltage vp(t) into a current may be desired. Such additional stage(s), along with utilizing additional power, may be desired to operate with rail-to-rail input voltages but without being affected by non-linear errors due to voltage offsets at the complementary differential input stages.

Therefore, there is a need to develop a peak detector capable of operating with rail-to-rail voltage inputs and providing an output current for operation with current-input processing electronics. There is also a need for a peak detector that is capable of providing high degree of precision peak detection.

SUMMARY

A circuit for processing a received voltage signal is disclosed in the present disclosure. The circuit includes a charge amplifier for amplifying the voltage signal; a filter, coupled with the charge amplifier, receiving and filtering the amplified signal and generating a filtered signal; and a peak detector coupled with the filter at the output terminal of the filter, generating a current output corresponding to the peak voltage amplitude of the received voltage signal.

A current-output peak detector circuit is also disclosed in the present disclosure. According to one embodiment, the peak detector circuit includes an amplifier having a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the amplifier is coupled with an input voltage signal through a first switch, the negative input terminal is coupled with a first resistor, the output terminal is coupled with the gate of a hold transistor MHthrough a second switch, and the drain of the hold transistor is coupled with a first terminal of a hold capacitor.

The peak detector circuit further includes a first transistor MR1. The gate of the first transistor MR1is coupled with the drain of the hold transistor and the gate of a second transistor, the drain of the first transistor MR1is coupled with the negative input terminal of the amplifier, and the second transistor is composed of n1 copies of the first transistor MR1connected in parallel and n1 is an integer. The sources of the first and second transistors and the second terminal of the hold capacitor are coupled to a supply voltage.

The peak detector circuit also includes a reset switch that is connected in parallel with the hold capacitor, and the reset switch is turned off upon, receipt of an input voltage signal at the positive input terminal of the amplifier. The peak detector circuit generates a current output at the drain of the second transistor corresponding to the peak amplitude of the input voltage signal when the first and second switches are turned on and the reset switch is turned off.

According to another embodiment, the current-output peak detector circuit may further include a third transistor MR2. The drain of the third transistor MR2is coupled with the positive input terminal of the amplifier through a third switch and with a second resistor, the gate of the third transistor MR2is coupled with the output terminal of the amplifier through a fourth switch and with the gate of a forth transistor. The resistance value of the second resistor is equal to the resistance value of the first resistor, and the third transistor MR2is a copy of the first transistor MR1. The fourth transistor comprises n2 copies of the third transistor MR2connected in parallel, and n2 is an integer. The sources of the third and fourth transistors are also coupled to the supply voltage.

According to an embodiment, the current-output peak detector circuit works in two phases. During the first phase, the first switch and the second switch are turned on, and the third and fourth switches are turned off. During the second phase, the first switch and the second switch are turned off and the third and fourth switches are turned on. The fifth switch will be switched off upon receipt of an input voltage signal at the positive input terminal of the amplifier. The peak detector circuit switches from the first phase to the second phase upon detection of the peak voltage of the input voltage signal received at the positive input terminal of the amplifier. In one embodiment, the peak detector circuit switches from the first phase to the second phase by a comparator circuit coupled with the output terminal of the amplifier. During the second phase, the peak detector circuit generates a current output at the drain of the fourth transistor corresponding to the peak amplitude of the input voltage signal.

DETAILED DESCRIPTION

The following discussion is presented to enable a person skilled in the art to make and use of the invention. Various modifications will be readily apparent to those skilled in the art, and the general principles described herein may be applied to embodiments and applications other than those detailed below without departing from the spirit and scope of the present disclosure as defined herein. The present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Referring toFIG. 2, a front-end circuit for a radiation detector according to one embodiment of the present disclosure is illustrated. The circuit includes a low-noise charge amplifier202, a filter204, and a current-output peak detector206. A charge signal Q from a sensor of the radiation detector is amplified by the charge amplifier202and filtered by the filter204, yielding a voltage pulse v(t) with an amplitude proportional to the charge Q and peak voltage amplitude U. The voltage pulse is processed by the current-output peak detector206which yields a constant current UI corresponding to the peak voltage pulse amplitude U. The constant current. can then be fed into current-input processing electronics208for further processing.

FIG. 3illustrates a schematic diagram of circuit300of the current-output peak detector206according to an embodiment of the disclosure. The circuit300may operate in two phases.

During the first phase, switches S1are closed and switches S2are open. The positive input terminal of a differential amplifier A is coupled to a voltage input signal v(t) through a first switch S1. For example, the positive input terminal of the amplifier A may be coupled to the output of a filter, such as the filter204inFIG. 2, and v(t) is the output signal of the filter. The negative input terminal of the amplifier A is connected to a resistor R1and to the drain of a transistor MR1. The gate of the transistor MR1is connected to a terminal of a hold capacitor CHand to the drain of a hold transistor MH. The gate of the hold transistor MHis connected to the output of the amplifier A through a second switch S1realizing a negative feedback loop around the amplifier A. The gate of the transistor MR1is also connected to the gate of a transistor M1, where the transistor M1is composed of n1 copies of the transistor MR1connected in parallel, and n1 is an arbitrary integer. The sources of the transistors MR1and M1are connected to a supply voltage Vdd, and the other terminal of the hold capacitor CHis connected to a supply voltage Vdd.

Before the voltage pulse v(t) arrives, the hold capacitor CHis discharged to the supply voltage Vddby closing a reset switch SR, which is coupled in parallel with the hold capacitor CH. When the pulse v(t) arrives, the switch SRis open and the amplifier's output voltage vo(t) increases. The hold capacitor CHdischarges through the hold transistor MH. Due to the negative feedback, the voltage vR(t) at the negative input of the amplifier A, which is also the voltage at the resistor R1, tracks the voltage at the positive input of the amplifier A through the current from the transistor MR1. It would be apparent to those of ordinary skill of art that a current io1(t) equal to n1-times the current in the resistor R1is available at the drain of the transistor M1. In this way the current io1(0is equal to n1-times vR(t)/R1, and thus provides a voltage-to-current conversion of the input signal.

As soon as the input pulse reaches its peak voltage, the input voltage starts decreasing. The voltage vh(t) at node H is held at its minimum value because there is no dc current flowing from the supply voltage Vddto the node H, and the voltage vR(t) at the resister R1remains constant at its maximum value, which is the peak value of the input voltage v(t). Therefore, since the negative input of the differential amplifier A is held constant and the positive input starts decreasing, the amplifier A reacts with a sharp decrease at its output voltage vo(t). The sharp drop at the output voltage refers to a rapidly changing voltage within a timeframe that may be about 2 to 3 orders of magnitude shorter than the time of the input signal. The range of the voltage decrease may depend on the threshold voltage of the hold transistor MH, but may be several hundreds of mV in a few nanoseconds. This sharp decrease in voltage switches off the hold transistor MH. The current io1(t), which is equal to n1-times vR(t)/R1, also provides the voltage-to-current conversion of the peak voltage.

The first phase provides peak detection and voltage-to-current conversion at the same time. In the embodiment ofFIG. 3, the accuracy of the measurement of the peak voltage is limited by a voltage offset voffat the inputs of the differential amplifier A, which introduces an error between v(t) and vR(t) by adding a voltage voffto vR(t). In rail-to-rail input amplifiers, which use complementary differential input stages, the offset voltage voffcan be input voltage dependent. For this reason the output current io1(t), affected by this voltage-dependent error, can only provide a limited measurement accuracy, or is a low-accuracy current output suitable for low-resolution measurements.

In order to correct the amplifier offset, a second phase may be applied. After the peak voltage has been detected, the switches S1are open and the switches S2are closed, and the peak detector circuit300is switched from the first phase to the second phase. In some embodiments, the switching can be either externally controlled or automatically controlled by a comparator circuit at the output of the amplifier A, which triggers at a sharp falling voltage, that is, at the time a peak voltage is detected. During the second phase, the negative input of the amplifier A remains connected to the peak voltage vR(t) which is held constant by the constant voltage vh(t) and by the hold capacitor CH. The positive input of the amplifier A is connected, through a first switch S2, to a resistor R2which is a copy of the resistor R1, and to the drain of a transistor MR2which is a copy of the transistor MR1. The resistor R2has a resistance value that is equal to that of the resistor R1. At this time, the voltage at the resistor R2, vR2(t), is equal to the voltage vR(t). The gate of the transistor MR2is coupled to the output terminal of the amplifier A through a second switch S2. The gate of the transistor MR2is also connected to the gate of a transistor M2, which is composed of n2 copies of the transistor MR2connected in parallel, where n2 is an integer. The sources of the transistor MR2and M2are connected to a supply voltage Vdd.

The value of the current in the resistor R2may be equal to the value of the current in the transistor R1if the offset voltage voffis not considered. The current io2(t) available at the drain of the transistor M2may be n2-times the current in the resistor R2which is equal to vR2(t)/R2. In this way the current io2(t) is equal to n2-times the current flowing through R2. However, the offset voltage voffpreviously added to the voltage vR(t) at the resistor R1may now be subtracted from the voltage vR2(t), thus canceling the error introduced in phase one. That is, vR2(t) is not affected by the offset error introduced in the first phase. For this reason the output current io2(t) may provide a higher degree of measurement accuracy, that is, it is a high-accuracy current output suitable for high-resolution measurements.

Therefore, in the embodiment illustrated inFIG. 3, by switching from the first phase to the second phase, the peak detection precision may no longer be limited by the voltage offset voffat the inputs of the differential amplifier A. The circuit300may provide a peak detection while also providing voltage-to-current conversion at the same time, i.e., simultaneously. After the high-accuracy current output is generated, the circuit300may then be switched back from the first phase to the second phase, where switches S1and SRare closed, and switches S2are open, ready for peak detection of a next pulse signal.

While particular aspects, implementations, and applications of the present disclosure have been illustrated and described, it is to be understood that the present disclosure is not limited to the precise construction and compositions disclosed herein and that various modifications, changes, and variations may be apparent from the foregoing descriptions without departing from the spirit and scope of the disclosed embodiments as defined in the appended claims.