Display device

A display device includes a pixel electrode, a switching element connected to the pixel electrode, a pixel line connected to the switching element and disposed adjacent to the pixel electrode, and a light-transmitting shielding portion made of a conductive film having light-transmitting and disposed adjacent to both the pixel electrode and the pixel line.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to a display device.

Description of the Related Art

As an example of a display device in the prior art, there is known the display device described in Japanese Unexamined Patent Application Publication No. 2007-79568. The display device described in Japanese Unexamined Patent Application Publication No. 2007-79568 includes a substrate made of insulator, a plurality of gate lines formed on the substrate, a plurality of data lines intersecting the plurality of gate lines, a plurality of thin film transistors, a gate and a source of each of the plurality of thin film transistors are respectively connected to a gate line of the plurality of gate lines and a data line of the plurality of data lines, and a plurality of pixel electrodes having a rectangular shape, each connected to a drain of a thin film transistor of the plurality of thin film transistors, arranged in a matrix, and including a first side parallel to a gate line of the plurality of gate lines and a second side shorter than the first side and parallel to a data line of the plurality of data lines. The pixel electrodes adjacent to each other in a column direction are connected to data lines different from each other.

SUMMARY OF THE INVENTION

In the display device set forth in Japanese Unexamined Patent Application Publication No. 2007-79568 described above, each of the pixel electrodes overlaps a storage electrode line including a storage electrode, thereby forming a storage capacitor that enhances a voltage storing capacity of a liquid crystal capacitor. In particular, a stem of the storage electrode line traverses longitudinally across a center of the pixel electrode, and top and bottom boundaries of the pixel electrode are positioned on the storage electrodes extending to the right and left from the stem. When the storage electrode lines are thus arranged, electromagnetic interference formed between the gate lines and the pixel electrodes is blocked by the storage electrodes, thereby stably maintaining the voltage of the pixel electrodes. However, the storage electrode line described above is constituted by a metal film having a light-blocking property, and there is concern that, with the storage electrode partially overlapping the pixel electrode, the amount of transmitted light of the pixel electrode is decreased and luminance reduction is generated.

One aspect of the present disclosure has been completed on the basis of the circumstances described above, and an object of the present disclosure is to block an electrical field while suppressing a luminance reduction.

(1) An embodiment of the present disclosure is a display device including a pixel electrode, a switching element connected to the pixel electrode, a pixel line connected to the switching element and disposed adjacent to the pixel electrode, and a light-transmitting shielding portion made of a conductive film having light-transmitting and disposed adjacent to both the pixel electrode and the pixel line.

(2) Further, in an embodiment of the present disclosure, in addition to the configuration of (1) described above, in the display device, the switching element includes at least a channel region made of a portion of a semiconductor film, and the light-transmitting shielding portion is formed by reducing a resistance of a portion of the semiconductor film, the portion being different from the channel region.

(3) Further, in an embodiment of the present disclosure, in addition to the configuration of (1) or (2) described above, in the display device, the pixel line is disposed aligned with the pixel electrode with an interval between the pixel line and the pixel electrode, and the light-transmitting shielding portion includes a non-overlapping portion interposed between and not overlapping the pixel electrode and the pixel line in an alignment direction of the pixel electrode and the pixel line.

(4) Further, in an embodiment of the present disclosure, in addition to any one of the configurations of (1) to (3) described above, in the display device, the light-transmitting shielding portion includes a pixel electrode overlapping portion overlapping an edge portion of the pixel electrode with an insulating film interposed between the pixel electrode overlapping portion and the edge portion of the pixel electrode.

(5) Further, in an embodiment of the present disclosure, in addition to any one the configurations of (1) to (4) described above, in the display device, the light-transmitting shielding portion includes a pixel line overlapping portion overlapping an edge portion of the pixel line with an insulating film interposed between the pixel line overlapping portion and the edge portion of the pixel line.

(6) Further, in an embodiment of the present disclosure, in addition to the configuration of (5) described above, in the display device, the switching element includes at least a channel region made of a portion of a semiconductor film disposed on an upper layer side of the pixel line with an insulating film interposed between the channel region and the pixel line, and the light-transmitting shielding portion is formed by reducing a resistance of a portion of the semiconductor film, the portion being different from the channel region.

(7) Further, in an embodiment of the present disclosure, in addition to any one of the configurations of (1) to (6) described above, in the display device, the pixel electrode has a longitudinal shape, and the pixel line and the light-transmitting shielding portion extend along an edge portion on a longitudinal side of the pixel electrode.

(8) Further, in an embodiment of the present disclosure, in addition to the configuration of (7) described above, in the display device, the pixel electrode includes a bent portion at a middle of the pixel electrode in a longitudinal direction, and the pixel line and the light-transmitting shielding portion are bent along the bent portion.

(9) Further, in an embodiment of the present disclosure, in addition to the configuration of (7) or (8) described above, the display device further includes a second pixel line extending in a short-hand direction of the pixel electrode, and the switching element includes a first gate electrode connected to the pixel line, a channel region disposed overlapping the first gate electrode on an upper layer side with a first gate insulating film interposed between the channel region and the first gate electrode and made of a semiconductor film, a second gate electrode disposed overlapping the channel region on an upper layer side with the second gate insulating film interposed between the second gate electrode and the channel region and connected to the first gate electrode, a source region connected to a first end portion of the channel region and the second pixel line, and a drain region connected to a second end portion of the channel region and the pixel electrode.

(10) Further, in an embodiment of the present disclosure, in addition to the configuration of (9) described above, in the display device, the second pixel line is disposed with an insulating film interposed between the second pixel line and the second gate electrode, and is made of an conductive film different from that of the second gate electrode.

(11) Further, in an embodiment of the present disclosure, in addition to the configuration of (9) described above, in the display device, the second pixel line is made of the conductive film same as that of the second gate electrode.

(12) Further, in an embodiment of the present disclosure, in addition to the configuration of any one of (1) to (11) described above, the display device further includes a common electrode overlapping the pixel electrode with an insulating film interposed between the common electrode and the pixel electrode, and the light-transmitting shielding portion is connected to the common electrode.

(13) Further, in an embodiment of the present disclosure, in addition to the configuration of any one of (1) to (12) described above, the display device further includes a second shielding portion disposed at least partly overlapping the light-transmitting shielding portion with an insulating film interposed between the second shielding portion and the light-transmitting shielding portion, and made of a conductive film.

(14) Further, in an embodiment of the present disclosure, in addition to the configuration of (13) described above, in the display device, the second shielding portion is constituted by a conductive film having light-blocking properties, and includes a light-blocking pixel line overlapping portion overlapping an edge portion of the pixel line with an insulating film interposed between the light-blocking pixel line overlapping portion and the edge portion of the pixel line, and the light-transmitting shielding portion includes a light-transmitting pixel electrode overlapping portion overlapping an edge portion of the pixel electrode with an insulating film interposed between the light-transmitting pixel electrode overlapping portion and the edge portion of the pixel electrode.

(15) Further, in an embodiment of the present disclosure, in addition to the configuration of (13) or (14) described above, the display device further includes a common electrode overlapping the pixel electrode with an insulating film interposed between the common electrode and the pixel electrode, and an intermediate electrode disposed overlapping the common electrode and the light-transmitting shielding portion via different insulating films and connected to each of the common electrode and the light-transmitting shielding portion through a contact hole formed in each of the insulating films. The second shielding portion is made of the conductive film same as that of the intermediate electrode, and is coupled to the intermediate electrode.

According to one aspect of the present disclosure, it is possible to block an electrical field while suppressing a luminance reduction.

DETAILED DESCRIPTION OF THE INVENTION

First Embodiment

The first embodiment of the present disclosure will be described with reference toFIG. 1toFIG. 13. In the present embodiment, a liquid crystal display device10is exemplified. Note that the X axis, the Y axis, and the Z axis are illustrated in a part of each drawing, and each axial direction is illustrated to be the direction illustrated in each drawing. Further, an upper side and a lower side inFIG. 3,FIG. 4,FIG. 9,FIG. 10,FIG. 11,FIG. 12, andFIG. 13are a front side and a rear side, respectively.

FIG. 1is a schematic plan view of a liquid crystal panel11. The liquid crystal display device10, as illustrated inFIG. 1, includes at least the liquid crystal panel (display device, display panel)11that has a horizontally elongated rectangular shape and is capable of displaying an image, and a backlight device (illumination device), which is an external light source configured to irradiate the liquid crystal panel11with light for use in display. In the present embodiment, the liquid crystal panel11has, for example, a screen size of about 15 inches (specifically, 15.6 inches), and a resolution equivalent to “full high definition (FHD)”. The backlight device includes a light source (for example, a light emitting diode (LED) or the like) disposed on a rear side (back face side) of the liquid crystal panel11and configured to emit light having a white color (white light), an optical member configured to impart an optical effect on the light from the light source, thereby converting the light into planar light, and the like.

In the liquid crystal panel11, as illustrated inFIG. 1, a center portion of a screen is established as a display region (range surrounded by a dot-dash line inFIG. 1) AA in which images are displayed. In contrast, a frame-shaped outer peripheral portion surrounding the display region AA of the screen of the liquid crystal panel11is a non-display region NAA in which images are not displayed. In the present embodiment, a long side dimension of the display region AA is 345.6 mm, for example, and a short side dimension is 194.4 mm, for example. The liquid crystal panel11is formed by bonding a pair of substrates20and21together. A front side (front face side) of the pair of substrates20and21is the color film (CF) substrate (counter substrate)20, and a rear side (back face side) is the array substrate (active matrix substrate, element substrate)21. The CF substrate20and the array substrate21are each formed by layering various films on an inner surface side of the glass substrate. Note that polarizers are bonded to outer face sides of both the substrates20and21, respectively.

The CF substrate20, as illustrated inFIG. 1, has a short side dimension that is shorter than a short side dimension of the array substrate21, and is bonded to the array substrate21with one end portion in a short side direction (Y-axis direction) aligned with the array substrate21. Accordingly, the other end portion in the short side direction of the array substrate21is a CF substrate non-overlapping portion21A protruding laterally relative to the CF substrate20and not overlapping the CF substrate20. A driver (second signal supplying portion)12and a flexible substrate (signal transmitting portion)13are mounted to this CF substrate non-overlapping portion21A. The driver12is constituted by a large-scale integration (LSI) chip including a drive circuit in an interior thereof, is chip-on-glass (COG) mounted to the array substrate21, and processes various signals transmitted by the flexible substrate13. In the present embodiment, in the non-display region NAA of the liquid crystal panel11, four of the drivers12are disposed aligned and intervals therebetween in the X-axis direction. The flexible substrate13has a configuration in which a line pattern including a plurality of lines are formed on a substrate made of a synthetic resin material (for example, a polyimide resin or the like) having insulating properties and flexibility. The flexible substrate13is connected to the non-display region NAA of the liquid crystal panel11at one end side, and connected to a control substrate (signal supply source) at the other end side. Various signals supplied from the control substrate are transmitted to the liquid crystal panel11via the flexible substrate13and outputted to the display region AA after being processed by the drivers12in the non-display region NAA. Further, in the non-display region NAA of the array substrate21, a pair of gate circuit portions (signal supplying portions)14are provided sandwiching the display region AA from both sides in the X-axis direction. The gate circuit portions14are each configured to supply a scanning signal to a gate line26described later, and monolithically provided to the array substrate21.

FIG. 2is a plan view of the display region AA of the array substrate21and the CF substrate20constituting the liquid crystal panel11. As illustrated inFIG. 2, a thin film transistor (TFT; switching element)23and a pixel electrode24are provided on an inner surface side of the display region AA of the array substrate21constituting the liquid crystal panel11. A plurality of the TFTs23and the pixel electrodes24are provided in a matrix shape with intervals therebetween in the X-axis direction and the Y-axis direction. A gate line (pixel line, scanning line)26and a source line (second pixel line, signal line, data line)27orthogonal to (intersecting) each other are provided around the TFTs23and the pixel electrodes24. While the gate line26extends almost along in the X-axis direction, the source line27extends almost along in the Y-axis direction. In the present embodiment, the resolution of the liquid crystal panel11is equivalent to “FHD”, three-color color filters28are configured so that those of different colors are arranged repeatedly along the source line27(Y-axis direction) as described later, and thus the number of installations of the gate line26is “1080×3=3240” and the number of installations of the source line27is “1920”. The gate line26and the source line27are respectively connected to a first gate electrode23A as well as a second gate electrode23E and a source region23B of the TFT23, and the pixel electrode24is connected to a drain region23C of the TFT23. The TFT23is driven on the basis of various signals respectively supplied to the gate line26and the source line27and, with the driving of the TFT23, the supply of electrical potential to the pixel electrode24is controlled. Further, the TFT23is disposed adjacent to one side (left side inFIG. 2) in the X-axis direction of the pixel electrode24to be connected. Further, a spacer SP for maintaining an interval between the pair of substrates20and21is provided in each position of the CF substrate20that overlaps the source line27of the array substrate21and is offset to an upper side illustrated inFIG. 2relative to the TFT23.

The pixel electrode24, as illustrated inFIG. 2, has a horizontally long shape in plan view, with a longitudinal direction thereof matching the X-axis direction and a short-hand direction thereof matching the Y-axis direction. A ratio of a longitudinal dimension to a short-hand dimension of the pixel electrode24is 3. The gate line26and the like are interposed between the pixel electrodes24adjacent to each other in the short-hand direction (Y-axis direction) while the source line27and the like are interposed between the pixel electrodes24adjacent to each other in the longitudinal direction (X-axis direction). The pixel electrodes24are each disposed with a side edge portion on a longitudinal side adjacent to the gate line26with a predetermined interval therebetween in the Y-axis direction, and with a side edge portion on a short-hand side adjacent to the source line27with a predetermined interval therebetween in the X-axis direction. Then, the pixel electrodes24each have a planar shape that is a bent shape with a bent portion24A at a middle in the longitudinal direction. Specifically, the pixel electrodes24are each slightly inclined relative to the X-axis direction at both side edge portions in the longitudinal direction thereof, and bent once at a substantially central position, thereby forming a shallow V-shape in which the apex angle is an obtuse angle The pixel electrodes24each include the bent portion24A in a substantially central position in the longitudinal direction and have a planar shape in which two generally parallelogram portions are connected, making the shape generally line symmetric relative to a virtual centerline extending in the short-hand direction through the bent portion24A. The bent portion24A is positioned at a joining point of the two generally parallelogram portions described above, and forms a straight line connecting the bending points at both side edge portions on the longitudinal side of the pixel electrode24in the short-hand direction of the pixel electrode24. The gate line26interposed between the pixel electrodes24adjacent in the short-hand direction is parallel to the side edge portions on the longitudinal sides of the pixel electrodes24, and is repeatedly bent in a zigzag manner following along the side edge portion on the longitudinal sides of the pixel electrodes24. The arrangement interval of the gate line26is about the same as the short-hand dimension of the pixel electrode24, and the arrangement interval of the source line27is about the same as the longitudinal dimension of the pixel electrode24. Accordingly, compared to when a pixel electrode is given a longitudinally long shape, the arrangement interval of the source line27is about the ratio of the short-hand dimension of the pixel electrode24divided by the longitudinal dimension (for example, approximately ⅓), and thus the number of installations of the source line27per unit length in the X-axis direction is about the same as the ratio described above (approximately ⅓, for example). Note that, compared to when a pixel electrode is given a longitudinally long shape, the arrangement interval of the gate line26is about the ratio of the longitudinal dimension of the pixel electrode24divided by the short-hand dimension (for example, approximately 3), and thus the number of installations of the gate line26per unit length in the X-axis direction is about the same as the ratio described above (approximately 3, for example). This makes it possible to reduce the number of installations of the source line27, and thus the number of image signals supplied to the source lines27is reduced. Note that a black matrix (inter-pixel light blocking portion)29illustrated by a two-dot chain line inFIG. 2is formed on the CF substrate20side. The black matrix29has a planar shape that is substantially a lattice pattern, partitioning the areas between the adjacent pixel electrodes24, and includes a pixel opening29A at a position overlapping a large portion of the pixel electrode24in plan view. This pixel opening29A allows the transmitted light of the pixel electrode24to be emitted outside the liquid crystal panel11. The black matrix29is disposed overlapping at least the TFT23, the gate line26, and the source line27(also including a common line30described later) on the array substrate21side, in plan view.

FIG. 3is a cross-sectional view of the liquid crystal panel11near a center portion of a pixel portion PX in the Y-axis direction.FIG. 4is a cross-sectional view of the liquid crystal panel11near a center portion of the pixel portion PX in the X-axis direction. As illustrated inFIG. 3andFIG. 4, the liquid crystal panel11includes a liquid crystal layer (medium layer)22that is disposed between the pair of substrates20and21and containing liquid crystal molecules, which are substances having optical characteristics that change in accordance with application of an electrical field. The three-color color filters28exhibiting blue (B), green (G), and red (R) are provided to the display region AA on an inner face side of the CF substrate20constituting the liquid crystal panel11. A plurality of the color filters28are arranged in alignment in a matrix shape in the X-axis direction and the Y-axis direction, overlapping the pixel electrodes24on the array substrate21side in plan view. The color filters28are arranged so that those exhibiting mutually different colors are repeatedly aligned along the source lines27(Y-axis direction), and those exhibiting the same color are continuously aligned along the gate lines26(X-axis direction). In this liquid crystal panel11, the R, G, and B color filters28aligned in the Y-axis direction and three pixel electrodes24facing each of the color filters28respectively constitute the three-color pixel portion PX. Then, in this liquid crystal panel11are configured display pixels capable of color display with predetermined gradation by the R, G, and B three-color pixel portions PX adjacent to each other in the Y-axis direction. An arrangement pitch of the pixel portions PX in the Y-axis direction is, for example, about 60 μm, and an arrangement pitch of the pixel portions PX in the X-axis direction is about 180 μm, for example. The black matrix29is disposed partitioning the area between the color filters28facing the adjacent pixel electrodes24. A flattening film OC disposed in a solid manner across substantially the entire region of the CF substrate20is provided on the upper layer side (liquid crystal layer22side) of the color filters28. Note that alignment films for aligning the liquid crystal molecules included in the liquid crystal layer22are respectively formed on innermost faces of both of the substrates20and21that are in contact with the liquid crystal layer22.

Next, a common electrode25will be described with reference toFIG. 2toFIG. 5.FIG. 5is a plan view illustrating a pattern of the common electrode25(second transparent electrode film44described later) provided to the array substrate21. InFIG. 5, the second transparent electrode film44is illustrated in shaded. On the inner face side of the display region AA of the array substrate21, as illustrated inFIG. 2toFIG. 5, the common electrode25is formed on the upper layer side of the pixel electrodes24in a manner that overlaps all of the pixel electrodes24. The common electrode25is supplied with a substantially constant common potential (reference potential) by the common line30, and extends across substantially the entire display region AA. The common line30overlaps the gate line26and the source line27described above in the display region AA in plan view, and is generally routed and formed in a substantially lattice pattern. A lead-out portion of the common line30led out to the non-display region NAA is connected to the flexible substrate13, and thus the common line30is supplied with a common potential from the flexible substrate13. A plurality of pixel overlapping openings (pixel overlapping slits, alignment control slits)25A extending in the longitudinal direction of each pixel electrode24are formed in a portion of the common electrode25overlapping each pixel electrode24. The pixel overlapping openings25A are each parallel to the side edge portion on the longitudinal side of the pixel electrode24and bend at a middle (substantially at a central position). Note that the specific installation quantity, shape, formation range and the like of the pixel overlapping opening25A can be changed as appropriate to other than those illustrated. When a potential difference is generated as the pixel electrodes24are charged between the pixel electrodes24and the common electrodes25overlapping each other, a fringe electrical field (oblique electrical field) including a component along a plate surface of the array substrate21as well as a component in a direction normal to the plate surface of the array substrate21is generated between opening edges of the pixel overlapping openings25A and the pixel electrodes24. Accordingly, by using this fringe electrical field, it is possible to control the alignment state of the liquid crystal molecules included in the liquid crystal layer22, and a predetermined display is formed on the basis of the alignment state of the liquid crystal molecules. In other words, the operation mode of the liquid crystal panel11according to the present embodiment is a fringe field switching (FFS) mode.

The configuration of the TFT23will be described in detail with reference toFIG. 6toFIG. 8.FIG. 6is a plan view illustrating a pattern of the first gate electrode23A, the gate line26, the source line27, and the like (first metal film32and third metal film38described later) of the TFT23provided to the array substrate21. InFIG. 6, the first metal film32and the third metal film38are illustrated in shaded.FIG. 7is a plan view illustrating a pattern of a channel region23D and the like (semiconductor film34described later) of the TFT23provided to the array substrate21. InFIG. 7, the semiconductor film34is illustrated in shaded.FIG. 8is a plan view illustrating a pattern of the second gate electrode23E (second metal film36described later) of the TFT23provided to the array substrate21. InFIG. 8, the second metal film36is illustrated in shaded. As illustrated inFIG. 6, the TFT23includes the first gate electrode (lower layer side gate electrode)23A made of a portion of the gate line26. The first gate electrode23A is made of a portion of the gate line26intersecting the channel region23D. A scanning signal transmitted to the gate line26is supplied to the first gate electrode23A. The TFT23includes the source region23B connected to the source line27, as illustrated inFIG. 6andFIG. 7. The source line27includes a source line widened portion27A that projects, from a position on a side (lower side illustrated inFIG. 6) opposite to the pixel electrode24to be connected in the Y-axis direction to the area intersecting the gate line26, to the pixel electrode24side (right side illustrated inFIG. 6) to be connected in the X-axis direction. The source region23B is substantially L-shaped in plan view, and a portion thereof extending in the X-axis direction is connected to the source line widened portion27A described above. The TFT23, as illustrated inFIG. 7, includes the drain region23C disposed with an interval from the source region23B in the Y-axis direction. The drain region23C is connected to the pixel electrode24at an end portion on a side opposite to the source region23B (channel region23D) side. The TFT23includes the channel region23D disposed overlapping the first gate electrode23A on the upper layer side and continuous to the source region23B and the drain region23C. Similar to the first gate electrode23A, the channel region23D has a horizontally elongated quadrilateral shape in plan view, a first end portion (lower end portion illustrated inFIG. 7) in the Y-axis direction is coupled to a portion of the source region23B extending in the Y-axis direction, and a second end portion (upper end portion illustrated inFIG. 7) is coupled to the drain region23C.

The TFT23includes the second gate electrode (lower layer side gate electrode)23E disposed overlapping the channel region23D on the upper layer side, as illustrated inFIG. 8. Similar to the first gate electrode23A and the channel region23D, the second gate electrode23E has a horizontally elongated quadrilateral shape in plan view. The second gate electrode23E is electrically connected to the first gate electrode23A, and thus the scanning signal transmitted to the gate line26is supplied at the same timing as to the first gate electrode23A. The channel region23D is thus configured to be sandwiched between the lower layer side and the upper layer side in the Z-axis direction by the first gate electrode23A and the second gate electrode23E, making it possible to increase a drain current flowing into the channel region23D compared to when only one gate electrode is disposed overlapping the channel region23D. As a result, the pixel electrode24can be sufficiently charged even when the charging time of the pixel electrode24charged by the TFT23is reduced in association with an increase in the number of installations of the gate line26.

The various films layered and formed on the inner surface side of the array substrate21will now be described with reference toFIG. 9toFIG. 11.FIG. 9toFIG. 11are each a cross-sectional view of the array substrate21near the TFT23. As illustrated inFIG. 9toFIG. 11, in the array substrate21, the first metal film (conductive film)32, a first gate insulating film (lower layer side gate insulating film)33, the semiconductor film34, a second gate insulating film (upper layer side gate insulating film)35, the second metal film (conductive film)36, a first interlayer insulating film (insulating film)37, the third metal film (conductive film)38, a second interlayer insulating film (insulating film)39, a flattening film (insulating film)40, a fourth metal film (conductive film)41, a first transparent electrode film42, an inter-electrode insulating film (insulating film)43, and the second transparent electrode film44are layered in this order from the lower layer side (glass substrate side).

The first metal film32, the second metal film36, the third metal film38, and the fourth metal film41are each a single layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, and the like, or a layered film or alloy made of a different types of metal materials, and thus have conductivity and light-blocking properties. The first metal film32, as illustrated inFIG. 9andFIG. 11, constitutes the gate line26, the first gate electrode23A of the TFT23, and the like. The second metal film36constitutes the second gate electrode23E of the TFT23, and the like. The third metal film38constitutes the source line27as illustrated inFIG. 10and constitutes a pixel intermediate electrode31connected to both the drain region23C and the pixel electrode24as illustrated inFIG. 9. The pixel electrode24is connected to the drain region23C by interposing this pixel intermediate electrode31and thus, compared to when the pixel electrode is directly connected to the drain region23C, failure such as film breakage or the like is not readily generated in the pixel electrode24, resulting in high connection reliability. The fourth metal film41constitutes the common line30and the like. The first transparent electrode42and the second transparent electrode44are made of a transparent electrode material (for example, indium tin oxide (ITO), indium zinc oxide (IZO), and the like). The first transparent electrode film42constitutes the pixel electrodes24and the like. The second transparent electrode film44constitutes the common electrode25and the like.

The semiconductor film34is an oxide semiconductor film employing an oxide semiconductor, for example, as a material, and has light-transmitting. The semiconductor film34constitutes the source region23B, the drain region23C, the channel region23D, and the like constituting the TFT23. Examples of specific materials of the semiconductor film34include an In—Ga—Zn—O based semiconductor (for example, indium gallium zinc oxide). Here, the In—Ga—Zn—O based semiconductor is a ternary oxide of indium (In), gallium (Ga), and zinc (Zn), and a ratio (compositional ratio) of the In, Ga, and Zn is not particularly limited. For example, the ratio includes In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, or In:Ga:Zn=1:1:2, but is not necessarily limited thereto. While the In—Ga—Zn—O based semiconductor may be amorphous or crystalline, when employing a crystalline, the crystalline In—Ga—Zn—O based semiconductor in which a c-axis is oriented substantially perpendicular to a layer surface is preferable. Here, in the semiconductor film34described above, a portion (the portion in which the second metal film36is non-overlapping) is made to have a reduced resistance in the manufacturing process, and thus the semiconductor film34is constituted by a reduced resistance region and a non-reduced resistance region. Specifically, the semiconductor film34, after being patterned to form a predetermined planar shape, is subjected to a resistance reduction treatment with the second gate insulating film35and the second metal film36layered and formed on the upper layer side serving as masks. Of the semiconductor film34, a portion exposed without being covered by the second metal film36(a portion not overlapping the second metal film36) is the reduced resistance region, and a portion covered by the second metal film36(a portion overlapping the second metal film36) is the non-reduced resistance region. Note that, inFIG. 4,FIG. 9,FIG. 10,FIG. 12, andFIG. 13, the reduced resistance region of the semiconductor film34is illustrated in shaded. The reduced resistance region of the semiconductor film34has an extremely low resistivity of, for example, from about 1/10000000000 to 1/100 compared to the non-reduced resistance region, and functions as a conductor. The reduced resistance region of the semiconductor film34constitutes the source region23B, the drain region23C, and the like of the TFT23. The non-reduced resistance region of the semiconductor film34is capable of charge transfer only under specific conditions (when a scanning signal is supplied to each of the gate electrodes23A and23E), while the reduced resistance region is always capable of charge transfer and functions as a conductor. The non-reduced resistance region of the semiconductor film34constitutes the channel region23D of the TFT23.

The first gate insulating film33, the second gate insulating film35, the first interlayer insulating film37, the second interlayer insulating film39, and the inter-electrode insulating film43are each made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiO2). The flattening film40is made of an organic material such as polymethyl methacrylate (PMMA; acrylic resin), for example, and has a film thickness greater than those of the other insulating films33,35,37,38and43made of inorganic material. This flattening film40flattens the surface of the array substrate21. As illustrated inFIG. 9toFIG. 11, the first gate insulating film33keeps the first metal film32on the lower layer side and the semiconductor film34on the upper layer side in an insulated state. In particular, the interval between the first gate electrode23A and the channel region23D is kept constant by a portion of the first gate insulating film33overlapping the first gate electrode23A. The second gate insulating film35keeps the semiconductor film34on the lower layer side and the second metal film36on the upper layer side in an insulated state. In particular, the interval between the second gate electrode23E and the channel region23D is kept constant by a portion of the second gate insulating film35overlapping the second gate electrode23E. The second gate insulating film35is patterned along with the second metal film36disposed on the upper layer side, and has a formation range overlapping substantially the entire region of the second metal film36(excluding a gate contact hole CH4described later). The first interlayer insulating film37keeps the second metal film36on the lower layer side and the third metal film38on the upper layer side in an insulated state. The second interlayer insulating film39and the flattening film40keep the third metal film38on the lower layer side, and the fourth metal film41and the first transparent electrode42on the upper layer side in an insulated state. The inter-electrode insulating film43keeps the first transparent electrode film42on the lower layer side and the second transparent electrode film44on the upper layer side in an insulated state.

As illustrated inFIG. 9, a first pixel contact hole CH1for connecting the pixel intermediate electrode31to the drain region23C is formed in a position of the first interlayer insulating film37overlapping both the drain region23C and the pixel intermediate electrode31. A second pixel contact hole CH2for connecting the pixel electrode24to the pixel intermediate electrode31is formed in respective positions of the second interlayer insulating film39and the flattening film40overlapping both the pixel electrode24and the pixel intermediate electrode31. The drain region23C and the pixel electrode24are connected to the pixel intermediate electrode31through these pixel contact holes CH1and CH2, respectively. The pixel intermediate electrode31is disposed covering, from the upper layer side, the portion of the drain region23C made of the semiconductor film34that is facing the first pixel contact hole CH1, making it possible to prevent the drain region23C from being over-etched when the fourth metal film41is etched through a patterned photoresist. Further, as illustrated inFIG. 10, a source contact hole CH3for connecting the source line widened portion27A to the source region23B is formed in a position of the first interlayer insulating film37overlapping both the source line widened portion27A of the source line27and the source region23B. In addition, as illustrated inFIG. 11, the gate contact hole CH4for connecting the second gate electrode23E to the first gate electrode23A is formed in positions of the first gate insulating film33and the second gate insulating film35overlapping both the first gate electrode23A and the second gate electrode23E and not overlapping the channel region23D.

As illustrated inFIG. 7andFIG. 12, the array substrate21according to the present embodiment is provided with a light-transmitting shielding portion45disposed adjacent to both the pixel electrode24and the gate line26.FIG. 12is a cross-sectional view of the array substrate21near the light-transmitting shielding portion45. The light-transmitting shielding portion45is made of the reduced resistance region of the semiconductor film (conductive film)34and is always capable of being conductive. Accordingly, the light-transmitting shielding portion45has light-transmitting and electrical conductivity. The light-transmitting shielding portion45is electrically connected to the common electrode25, which will be described in detail later. In this manner, an electrical field generated between the pixel electrode24and the gate line26can be blocked by the light-transmitting shielding portion45disposed adjacent to both the pixel electrode24and the gate line26. As a result, a parasitic capacitance generated between the pixel electrode24and the gate line26is suppressed, and thus a reduction in display quality caused by parasitic capacitance is suppressed. In addition, because the light-transmitting shielding portion45is made of the semiconductor film34having light-transmitting, when, for example, a design is adopted in which a portion of the light-transmitting shielding portion45is made to overlap the pixel electrode24or, even with a design in which the light-transmitting shielding portion45does not overlap the pixel electrode24, when a portion of the light-transmitting shielding portion45is disposed overlapping the pixel electrode24due to a shift in alignment or the like that is generated during manufacture, the amount of transmitted light of the pixel electrode24is less likely to decrease due to the light-transmitting shielding portion45. This makes it possible to block an electrical field generated between the pixel electrode24and the gate line26while suppressing a luminance reduction. Furthermore, the light-transmitting shielding portion45is constituted by the reduced resistance region formed by reducing the resistance of a portion of the semiconductor film34constituting the channel region23D of the TFT23that is different from the channel region23D, and thus, during manufacture, these can be patterned using the same photomask, which is suitable for reducing the number of photomasks used and the like.

As illustrated inFIG. 7andFIG. 12, the light-transmitting shielding portion45extends in parallel with the side edge portion on the longitudinal side of the pixel electrode24and the gate line26. Specifically, the light-transmitting shielding portion45is bent once along the bent portion24A of the pixel electrode24at a substantially central position in the length direction in plan view, and forms a shallow V-shape in which the apex angle is an obtuse angle. The light-transmitting shielding portion45has a length dimension that is somewhat shorter than the length dimension of the side edge portion on the longitudinal side of the pixel electrode24, but is disposed adjacent to a large portion of the side edge portion on the longitudinal side of the pixel electrode24(a portion other than both end portions in the length direction). The light-transmitting shielding portion45is disposed with one end portion in the length direction (X-axis direction) adjacent to the TFT23, and the other end portion adjacent to a portion of the common line30extending along the source line27(Y-axis direction). Further, the light-transmitting shielding portion45is also disposed adjacent in the Y-axis direction to the portion of the common line30extending along the gate line26(X-axis direction). In a configuration in which the gate line26extends along the side edge portion on the longitudinal side of the pixel electrode24having a longitudinal shape as in the present embodiment, compared to when the gate line extends along the side edge portion on the short-hand side of the pixel electrode24, the parasitic capacitance that may be generated between the side edge portion on the longitudinal side of the pixel electrode24and the gate line26tends to be greater. In this regard, the light-transmitting shielding portion45extends along the side edge portion on the longitudinal side of the pixel electrode24, and thus the electrical field generated between the side edge portion on the longitudinal side of the pixel electrode24and the gate line26is favorably blocked by the light-transmitting shielding portion45, and a reduction in display quality caused by parasitic capacitance can be more effectively suppressed. Further, in a configuration in which the gate line26is bent along the bent portion24A of the pixel electrode24as in the present embodiment, compared to when the pixel electrode and the gate line extend linearly without being bent at a middle in the longitudinal direction, the gate line26has an increased creepage distance parallel to the side edge portion on the longitudinal side of the pixel electrode24, and thus the parasitic capacitance that may be generated between the side edge portion on the longitudinal side of the pixel electrode24and the gate line26tends to be even larger. In this regard, the light-transmitting shielding portion45is bent along the bent portion24A of the pixel electrode24, and thus the electrical field generated between the side edge portion on the longitudinal side of the pixel electrode24and the gate line26is favorably blocked, and a reduction in display quality caused by parasitic capacitance can be even more effectively suppressed.

As illustrated inFIG. 7andFIG. 12, the light-transmitting shielding portion45has a width dimension wider than the interval between the pixel electrode24and the gate line26aligned in the Y-axis direction. The light-transmitting shielding portion45includes a non-overlapping portion45A interposed between the pixel electrode24and the gate line26in the Y-axis direction (alignment direction of the pixel electrode24and the gate line26), being non-overlapping with the pixel electrode24and the gate line26in plan view. The non-overlapping portion45A has a width dimension substantially equal to the interval between the pixel electrode24and the gate line26aligned in the Y-axis direction. This non-overlapping portion45A can favorably block an electrical field that may be generated between the pixel electrode24and the gate line26through the space opened between the pixel electrode24and the gate line26. In addition, the light-transmitting shielding portion45includes a pixel electrode overlapping portion45B disposed overlapping the side edge portion on the longitudinal side of the pixel electrode24in plan view. The pixel electrode overlapping portion45B made of the semiconductor film34overlaps the side edge portion on the longitudinal side of the pixel electrode24made of the first transparent electrode film42with the first interlayer insulating film37, the second interlayer insulating film39, and the flattening film40interposed therebetween. In this way, even when there is an electrical field that may be generated between the pixel electrode24and the gate line26near the side edge portion on the longitudinal side of the pixel electrode24, the electrical field can be favorably blocked by the pixel electrode overlapping portion45B overlapping the side edge portion on the longitudinal side of the pixel electrode24. Moreover, because the light-transmitting shielding portion45has light-transmitting, the amount of transmitted light of the pixel electrode24is less likely to decrease due to the pixel electrode overlapping portion45B and luminance reduction is suppressed even when the pixel electrode overlapping portion45B overlaps the pixel electrode24. Further, even when, for example, the light-transmitting shielding portion45is positionally offset away from the pixel electrode24in the Y-axis direction due to a shift in alignment that is generated during manufacture or the like, the pixel electrode overlapping portion45B can block an electrical field that may be generated in the space opened between the pixel electrode24and the gate line26. This increases the reliability of blocking an electrical field that may be generated between the pixel electrode24and the gate line26by the light-transmitting shielding portion45.

Furthermore, the light-transmitting shielding portion45, as illustrated inFIG. 7andFIG. 12, includes a gate line overlapping portion (pixel line overlapping portion)45C disposed overlapping the side edge portion of the gate line26in plan view. The gate line overlapping portion45C made of the semiconductor film34overlaps the side edge portion of the gate line26made of the first metal film32with the first gate insulating film (insulating film)33interposed therebetween. In this way, even when there is an electrical field that may be generated between the gate line26and the pixel electrode24near the side edge portion of the gate line26, the electrical field can be favorably blocked by the gate line overlapping portion45C overlapping the side edge portion of the gate line26. Further, even when, for example, the light-transmitting shielding portion45is positionally offset away from the gate line26in the Y-axis direction due to a shift in alignment that is generated during manufacture or the like, the gate line overlapping portion45C can block an electrical field that may be generated in the space opened between the pixel electrode24and the gate line26. This increases the reliability of blocking an electrical field that may be generated between the pixel electrode24and the gate line26by the light-transmitting shielding portion45. Further, the semiconductor film34constituting the light-transmitting shielding portion45is disposed on the upper layer side of the gate line26with the first gate insulating film34interposed therebetween, making it possible to avoid a situation in which the gate line overlapping portion45C of the light-transmitting shielding portion45overlapping the side edge portion of the gate line26is no longer reduced in resistance by the gate line26.

Next, a connection structure between the light-transmitting shielding portion45and the common electrode25will be described. As illustrated inFIG. 6andFIG. 13, the light-transmitting shielding portion45made of the semiconductor film34and the common electrode25made of the second transparent electrode film44are electrically connected by interposing an intermediate electrode46made of the third metal film38.FIG. 13is a cross-sectional view of the array substrate21near the intermediate electrode46. The intermediate electrode46is disposed overlapping the light-transmitting shielding portion45on the upper layer side with the first interlayer insulating film37interposed therebetween, and overlapping the common electrode25on the lower layer side with the second interlayer insulating film39, the flattening film40, and the inter-electrode insulating film43interposed therebetween. Specifically, the intermediate electrode46is disposed overlapping an end portion of the light-transmitting shielding portion45on a side (right side illustrated inFIG. 6) opposite to the TFT23side in the length direction (X-axis direction) in plan view, and connects that same end portion to the common electrode25. A first shielding portion contact hole (contact hole) CH5for connecting the intermediate electrode46to the above-described end portion of the light-transmitting shielding portion45is formed in a position of the first interlayer insulating film37overlapping the intermediate electrode46. A second shielding portion contact hole CH6for connecting the common electrode25to the intermediate electrode46is formed in positions of the second interlayer insulating film39, the flattening film40, and the inter-electrode insulating film43overlapping the intermediate electrode46. The common electrode25and the light-transmitting shielding portion45are connected to the intermediate electrode46through these shielding portion contact holes CH5and CH6, respectively. The intermediate electrode46is disposed covering, from the upper layer side, the portion of the light-transmitting shielding portion45made of the semiconductor film34that is facing the first shielding portion contact hole CH5, making it possible to prevent the light-transmitting shielding portion45from being over-etched when the fourth metal film41is etched through a patterned photoresist. Further, the common electrode25and the light-transmitting shielding portion45are connected by interposing this intermediate electrode46and thus, compared to when the common electrode is directly connected to the light-transmitting shielding portion45, failure such as film breakage or the like is not readily generated in the common electrode25, resulting in high connection reliability.

Further, as illustrated inFIG. 7andFIG. 13, the portion of the common line30extending along the source line27includes a common line widened portion30A partially widened at a position adjacent to the light-transmitting shielding portion45. Then, a common line contact hole CH7for connecting the common electrode25to the common line widened portion30A is formed in a position of the inter-electrode insulating film43interposed between the common electrode25and the common line30that is overlapping both the common electrode25and the common line widened portion30A.

As described above, the liquid crystal panel (display device)11of the present embodiment includes the pixel electrode24, the TFT (switching element)23connected to the pixel electrode24, the gate line (pixel line)26connected to the TFT23and disposed adjacent to the pixel electrode24, and the light-transmitting shielding portion45that is made of a semiconductor film (conductive film)34having light-transmitting and is disposed adjacent to both the pixel electrode24and the gate line26.

In this way, a signal for driving the TFT23or a signal for charging the pixel electrode24is transmitted to the gate line26, and the pixel electrode24is charged in accordance with the driving of the TFT23. Between the pixel electrode24and the gate line26, a parasitic capacitance may be generated, and there is a concern that the display quality may deteriorate due to this parasitic capacitance. For this, the light-transmitting shielding portion45is disposed adjacent to both the pixel electrode24and the gate line26, making it possible to block an electrical field generated between the pixel electrode24and the gate line26by the light-transmitting shielding portion45. As a result, a parasitic capacitance generated between the pixel electrode24and the gate line26is suppressed, and thus a reduction in display quality caused by parasitic capacitance is suppressed. In addition, because the light-transmitting shielding portion45is made of the semiconductor film34having light-transmitting, when, for example, a design is adopted in which a portion of the light-transmitting shielding portion45is made to overlap the pixel electrode24or, even with a design in which the light-transmitting shielding portion45does not overlap the pixel electrode24, when a portion of the light-transmitting shielding portion45is disposed overlapping the pixel electrode24due to a shift in alignment or the like that is generated during manufacture, the amount of transmitted light of the pixel electrode24is less likely to decrease due to the light-transmitting shielding portion45. This makes it possible to block an electrical field generated between the pixel electrode24and the gate line26while suppressing a luminance reduction.

Further, the TFT23includes at least the channel region23D made of a portion of a semiconductor film34, and the light-transmitting shielding portion45is formed by reducing a resistance of a portion of the semiconductor film34, the portion being different from the channel region23D. In this way, the light-transmitting shielding portion45formed by reducing the resistance of a portion of the semiconductor film34different from the channel region23D is disposed adjacent to both the pixel electrode24and the gate line26. The light-transmitting shielding portion45is made of a portion of the semiconductor film34constituting the channel region23D of the TFT23that is different from the channel region23D, and thus, during manufacture, these can be patterned using the same photomask, which is suitable for reducing the number of photomasks used and the like.

Further, the gate line26is disposed aligned with the pixel electrode24with an interval therebetween, and the light-transmitting shielding portion45includes the non-overlapping portion45A interposed between and not overlapping the pixel electrode24and the pixel line26in an alignment direction of the pixel electrode24and the pixel line26. When the pixel electrode24and the gate line26are aligned with an interval therebetween, there is a possibility that an electrical field may be generated between the pixel electrode24and the gate line26through the space opened between the pixel electrode24and the gate line26. The non-overlapping portion45A included in the light-transmitting shielding portion45is interposed between and in the alignment direction of the pixel electrode24and the gate line26and does not overlap the pixel electrode24or the gate line26, and thus can favorably block an electrical field that may be generated in the space opened between the pixel electrode24and the gate line26.

Further, the light-transmitting shielding portion45includes the pixel electrode overlapping portion45B overlapping an edge portion of the pixel electrode24with the first interlayer insulating film37, the second interlayer insulating film39, and the flattening film40(insulating film) interposed therebetween. While there is an electrical field generated between the pixel electrode24and the gate line26near the edge portion of the pixel electrode24, the electrical field can be favorably blocked by the pixel electrode overlapping portion45B of the light-transmitting shielding portion45. Moreover, because the light-transmitting shielding portion45has light-transmitting, the amount of transmitted light of the pixel electrode24is less likely to decrease and luminance reduction is suppressed even when the pixel electrode overlapping portion45B overlaps the pixel electrode24with the first interlayer insulating film37, the second interlayer insulating film39, and the flattening film40interposed therebetween. Further, even when, for example, the light-transmitting shielding portion45is positionally offset away from the pixel electrode24due to a shift in alignment that is generated during manufacture or the like, the pixel electrode overlapping portion45B can block an electrical field that may be generated in the space opened between the pixel electrode24and the gate line26. This increases the reliability of blocking an electrical field that may be generated between the pixel electrode24and the gate line26by the light-transmitting shielding portion45.

Further, the light-transmitting shielding portion45includes the gate line overlapping portion (pixel electrode overlapping portion)45C overlapping an edge portion of the gate line26with the first gate insulating film (insulating film)33interposed therebetween. In this way, while there is an electrical field generated between the gate line26and the pixel electrode24near the edge portion of the gate line26, the electrical field can be favorably blocked by the gate line overlapping portion45C of the light-transmitting shielding portion45. Further, even when, for example, the light-transmitting shielding portion45is positionally offset away from the gate line26due to a shift in alignment that is generated during manufacture or the like, the gate line overlapping portion45C can block an electrical field that may be generated in the space opened between the pixel electrode24and the gate line26. This increases the reliability of blocking an electrical field that may be generated between the pixel electrode24and the gate line26by the light-transmitting shielding portion45.

Further, the TFT23includes at least the channel region23D made of a portion of the semiconductor film34disposed on an upper layer side of the gate line26with the first gate insulating film (insulating film)33interposed therebetween, and the light-transmitting shielding portion45is formed by reducing a resistance of a portion of the semiconductor film34, the portion being different from the channel region23D. In this way, the light-transmitting shielding portion45formed by reducing the resistance of a portion of the semiconductor film34different from the channel region23D is disposed adjacent to both the pixel electrode24and the gate line26. The light-transmitting shielding portion45is made of a portion of the semiconductor film34constituting the channel region23D of the TFT23that is different from the channel region23D, and thus, during manufacture, these can be patterned using the same photomask, which is suitable for reducing the number of photomasks used and the like. Then, the semiconductor film34is disposed on the upper layer side of the gate line26with the first gate insulating film34interposed therebetween, making it possible to avoid a situation in which the portion of the light-transmitting shielding portion45overlapping the edge portion of the gate line26is no longer reduced in resistance by the gate line26.

Further, the pixel electrode24has a longitudinal shape, and the gate line26and the light-transmitting shielding portion45extend along an edge portion on the longitudinal side of the pixel electrode24. In a configuration in which the gate line26thus extends along the edge portion on the longitudinal side of the pixel electrode24having a longitudinal shape, compared to when the gate line extends along the edge portion on the short-hand side of the pixel electrode24, the parasitic capacitance that may be generated between the edge portion on the longitudinal side of the pixel electrode24and the gate line26tends to be greater. In this regard, the light-transmitting shielding portion45extends along the edge portion on the longitudinal side of the pixel electrode24, and thus the electrical field generated between the edge portion on the longitudinal side of the pixel electrode24and the gate line26is favorably blocked, and a reduction in display quality caused by parasitic capacitance can be more effectively suppressed.

Further, the pixel electrode24includes the bent portion24A at a middle of the pixel electrode24in the longitudinal direction, and the gate line26and the light-transmitting shielding portion45are bent along the bent portion24A. In a configuration in which the gate line26is thus bent along the bent portion24A of the pixel electrode24, compared to when the pixel electrode and the gate line extend linearly without being bent at a middle in the longitudinal direction, the gate line26has an creepage distance parallel to the edge portion on the longitudinal side of the pixel electrode24, and thus the parasitic capacitance that may be generated between the edge portion on the longitudinal side of the pixel electrode24and the gate line26tends to be even larger. In this regard, the light-transmitting shielding portion45is bent along the bent portion24A of the pixel electrode24, and thus the electrical field generated between the edge portion on the longitudinal side of the pixel electrode24and the gate line26is favorably blocked, and a reduction in display quality caused by parasitic capacitance can be even more effectively suppressed.

Further, the source line (second pixel line)27extending in the short-hand direction of the pixel electrode24is provided, and the TFT23includes the first gate electrode23A connected to the gate line26, the channel region23D disposed overlapping the first gate electrode23A on an upper layer side with the first gate insulating film33interposed therebetween and made of the semiconductor film34, the second gate electrode23E disposed overlapping the channel region23D on the upper layer side with the second gate insulating film35interposed therebetween and connected to the first gate electrode23A, the source region23B connected to a first end portion of the channel region23D and the source line27, and the drain region23C connected to a second end portion of the channel region23D and the pixel electrode24. In this way, when the signal transmitted to the gate line26is supplied to the first gate electrode23A and the second gate electrode23E, the TFT23is driven. Then, the signal transmitted to the source line27is supplied to the source region23B, and is supplied from the source region23B to the drain region23C via the channel region23D. The drain region23C is connected to the pixel electrode24, and thus the pixel electrode24is charged to a potential on the basis of the signal transmitted to the source line27. Here, in a configuration in which a plurality of the pixel electrodes24, a plurality of the gate lines26, and a plurality of the source lines27are provided, the arrangement interval of the plurality of the source lines27is greater than the arrangement interval of the plurality of the gate lines26, and the number of installations of the plurality of the gate lines26tends to be greater than the number of installations of the plurality of the source lines27. As a result, the driving time of the TFT23driven on the basis of the signal supplied to the gate line26as well as the charging time of the pixel electrode24charged by the TFT23tend to be shortened. In this regard, the TFT23is driven by the first gate electrode23A disposed overlapping the channel region23D on the lower layer side with the first gate insulating film33disposed therebetween, and the second gate electrode23E disposed overlapping the channel region23D on the upper layer side with the second gate insulating film35disposed therebetween and connected to the first gate electrode23A, making it possible to increase the current flowing into the channel region23D compared to when only one gate electrode is disposed overlapping the channel region23D. This makes it possible to sufficiently charge the pixel electrode24even with a short charging time.

Further, the source line27is disposed with the first interlayer insulating film (insulating film)37interposed between the source line27and the second gate electrode23E, and is made of the third metal film38, which is a conductive film different from that of the second gate electrode23E. In this way, compared to when the source line and the second gate electrode are constituted by the same conductive film, a defect in which the source line27and the second gate electrode23E are short-circuited is less likely to be generated.

Further, the common electrode25overlapping the pixel electrode24with the inter-electrode insulating film (insulating film)43interposed therebetween is provided, and the light-transmitting shielding portion45is connected to the common electrode25. In this way, the common electrode25overlapping the pixel electrode24with the inter-electrode insulating film43interposed therebetween is held at a common potential. A potential difference is generated between the charged pixel electrode24and the common electrode25, and the display is made on the basis of the potential difference. The light-transmitting shielding portion45is connected to the common electrode25and is at the same potential as the common electrode25, and thus can favorably block an electrical field that may be generated between the pixel electrode24and the gate line26.

Second Embodiment

The second embodiment of the present disclosure will be described with reference toFIG. 14toFIG. 16. In this second embodiment, an embodiment additionally provided with a second shielding portion47is illustrated. Note that redundant descriptions of structures, actions, and effects similar to those of the first embodiment described above will be omitted.

As illustrated inFIG. 14andFIG. 16, an array substrate121according to the present embodiment is provided with a second shielding portion47disposed overlapping at least a portion of a light-transmitting shielding portion145. The second shielding portion47is constituted by a third metal film (conductive film)138disposed on the upper layer side of a semiconductor film134constituting the light-transmitting shielding portion145with a first interlayer insulating film (insulating film)137interposed therebetween. The second shielding portion47extends parallel to the light-transmitting shielding portion145, and a length dimension thereof is equivalent to a length dimension of the light-transmitting shielding portion145. In this way, in addition to the light-transmitting shielding portion145, the second shielding portion47is disposed adjacent to both a pixel electrode124and a gate line126, and thus, even if a formation defect is generated in the light-transmitting shielding portion145made of the semiconductor film134for manufacturing reasons, an electrical field that may be generated between the pixel electrode124and the gate line126can be blocked by the second shielding portion47made of the third metal film138.

The second shielding portion47, as illustrated inFIG. 14andFIG. 16, is disposed with a portion thereof overlapping a side edge portion of the gate line126in plan view. The third metal film138constituting the second shielding portion47has light-blocking properties, and thus the portion of the second shielding portion47overlapping the side edge portion of the gate line126is referred to as a “light-blocking gate line overlapping portion (light-blocking pixel line overlapping portion)47A”. The light-blocking gate line overlapping portion47A overlaps the side edge portion of the gate line126with a first gate insulating film133and the first interlayer insulating film137(insulating film) interposed therebetween. The second shielding portion47is disposed not overlapping the pixel electrode124. In this way, even when there is an electrical field that may be generated between the gate line126and the pixel electrode124near the edge portion of the gate line126, the electrical field can be favorably blocked by the light-blocking gate line overlapping portion47A of the second shielding portion47. While the light-blocking gate line overlapping portion47A overlaps the gate line126, the second shielding portion47constituted by the third metal film138having light-blocking properties does not overlap the pixel electrode124, and thus a decrease in the amount of transmitted light of the pixel electrode124is avoided. Further, even when, for example, the second shielding portion47is positionally offset away from the gate line126due to a shift in alignment that is generated during manufacture or the like, the light-blocking gate line overlapping portion47A can block an electrical field that may be generated in the space opened between the pixel electrode124and the gate line126.

In contrast, similar to the first embodiment described above, the light-transmitting shielding portion145, as illustrated inFIG. 15andFIG. 16, is disposed with portions thereof respectively overlapping the side edge portion on the longitudinal side of the pixel electrode124and the side edge portion of the gate line126. The semiconductor film134constituting the light-transmitting shielding portion145has light-transmitting and thus the portion of the light-transmitting shielding portion145overlapping the side edge portion on the longitudinal side of the pixel electrode124is referred to as a “light-transmitting pixel electrode overlapping portion145B”, and the portion overlapping the side edge portion of the gate line126is referred to as a “light-transmitting gate line overlapping portion (light-transmitting pixel line overlapping portion)145C”. This light-transmitting pixel electrode overlapping portion145B is the same as the pixel electrode overlapping portion45B described in the first embodiment described above, and the light-transmitting gate line overlapping portion145C is the same as the gate line overlapping portion45C described in the first embodiment described above. The light-transmitting pixel electrode overlapping portion145B overlaps the side edge portion on the longitudinal side of the pixel electrode124with the first interlayer insulating film137, a second interlayer insulating film139, and a flattening film140(insulating film) interposed therebetween. Further, the light-transmitting gate line overlapping portion145C overlaps the side edge portion of the gate line126with the first gate insulating film133interposed therebetween. In this way, even when there is an electrical field that may be generated between the pixel electrode124and the gate line126near the edge portion of the pixel electrode124, the electrical field can be favorably blocked by the light-transmitting pixel electrode overlapping portion145B of the light-transmitting shielding portion145. Moreover, because the light-transmitting shielding portion145has light-transmitting, the amount of transmitted light of the pixel electrode124is less likely to decrease and luminance reduction is suppressed even when the light-transmitting pixel electrode overlapping portion145B overlaps the pixel electrode124. Further, even when, for example, the light-transmitting shielding portion145is positionally offset away from the pixel electrode124due to a shift in alignment that is generated during manufacture or the like, the light-transmitting pixel electrode overlapping portion145B can block an electrical field that may be generated in the space opened between the pixel electrode124and the gate line126. Further, the light-transmitting gate line overlapping portion145C is disposed overlapping the side edge portion of the gate line126in addition to the light-blocking gate line overlapping portion47A of the second shielding portion47, making it possible to more favorably block an electrical field that may be generated near the side edge portion of the gate line126.

As illustrated inFIG. 14, the third metal film138constituting the second shielding portion47also constitutes an intermediate electrode146. Then, the second shielding portion47is directly coupled to the intermediate electrode146. Specifically, of the second shielding portion47extending in parallel with the light-transmitting shielding portion145, an end portion on the side (right side illustrated inFIG. 14) opposite to the TFT123side in the length direction (X-axis direction) of the second shielding portion47is coupled to the intermediate electrode146. The intermediate electrode146, as described in the first embodiment described above, is connected to both a common electrode125and the light-transmitting shielding portion145, making it possible to achieve effects such as a less likelihood of failure such as film breakage or the like in the common electrode125compared to when the common electrode is directly connected to the light-transmitting shielding portion145, resulting in high connection reliability. Note that a connection structure of the intermediate electrode146, the common electrode125, and the light-transmitting shielding portion145(first shielding portion contact hole CH5and second shielding portion contact hole CH6) is as set forth inFIG. 13illustrated in first embodiment described above. Then, in the present embodiment, the second shielding portion47is connected to the common electrode125by interposing the intermediate electrode146along with the light-transmitting shielding portion145, and thus the number of films can be reduced compared to when the second shielding portion and the intermediate electrode are constituted by different conductive films.

As described above, according to the present embodiment, the second shielding portion47made of the third metal film (conductive film)138disposed with at least a portion thereof overlapping the light-transmitting shielding portion145with the first interlayer insulating film (insulating film)137interposed therebetween is provided. In this way, even in a case where a formation defect is generated in the light-transmitting shielding portion145for manufacturing reasons, at least a portion of the second shielding portion47made of the third metal film138is disposed overlapping the light-transmitting shielding portion145with the first interlayer insulating film137interposed therebetween, making it possible to maintain the electrical field blocking function.

Further, the second shielding portion47, in addition to being constituted by the third metal film138having light-blocking properties, includes a light-blocking gate line overlapping portion (light-blocking pixel line overlapping portion)47A overlapping an edge portion of the gate line126with the first gate insulating film133and the first interlayer insulating film137(insulating film) interposed therebetween, and the light-transmitting shielding portion145includes a light-transmitting pixel electrode overlapping portion145B overlapping an edge portion of the pixel electrode124with the first interlayer insulating film137, the second interlayer insulating film139, and the flattening film140(insulating film) interposed therebetween. In this way, while there is an electrical field generated between the pixel electrode124and the gate line126near the edge portion of the pixel electrode124, the electrical field can be favorably blocked by the light-transmitting pixel electrode overlapping portion145B of the light-transmitting shielding portion145. Moreover, because the light-transmitting shielding portion145has light-transmitting, the amount of transmitted light of the pixel electrode124is less likely to decrease and luminance reduction is suppressed even when the light-transmitting pixel electrode overlapping portion145B overlaps the pixel electrode124with the first interlayer insulating film137, the second interlayer insulating film139, and the flattening film140interposed therebetween. Further, even when, for example, the light-transmitting shielding portion145is positionally offset away from the pixel electrode124due to a shift in alignment that is generated during manufacture or the like, the light-transmitting pixel electrode overlapping portion145B can block an electrical field that may be generated in the space opened between the pixel electrode124and the gate line126. On the other hand, while there is an electrical field generated between the gate line126and the pixel electrode124near the edge portion of the gate line126, the electrical field can be favorably blocked by the light-blocking gate line overlapping portion47A of the second shielding portion47. While the light-blocking gate line overlapping portion47A overlaps the gate line126, the second shielding portion47constituted by the third metal film138having light-blocking properties does not overlap the pixel electrode124, and thus a decrease in the amount of transmitted light of the pixel electrode124is avoided. Further, even when, for example, the second shielding portion47is positionally offset away from the gate line126due to a shift in alignment that is generated during manufacture or the like, the light-blocking gate line overlapping portion47A can block an electrical field that may be generated in the space opened between the pixel electrode124and the gate line126. As a result, the reliability of blocking an electrical field that may be generated between the pixel electrode124and the gate line126by the light-transmitting shielding portion145and the second shielding portion47is increased.

Further, the common electrode125overlapping the pixel electrode124with the inter-electrode insulating film (insulating film)143interposed therebetween, and the intermediate electrode146disposed overlapping the common electrode125and the light-transmitting shielding portion145, each with a different insulating film of the first interlayer insulating film137, the second interlayer insulating film139, the flattening film140, and the inter-electrode insulating film143interposed therebetween, and connected to each of the common electrode125and the light-transmitting shielding portion145through the first shielding portion contact hole CH5and the second shielding portion contact hole CH6(contact hole) formed in each of the first interlayer insulating film137, the second interlayer insulating film139, the flattening film140, and the inter-electrode insulating film143are provided. The second shielding portion47is made of the third metal film138, which is the conductive film same as that of the intermediate electrode146, and is coupled to the intermediate electrode146. In this way, the common electrode125overlapping the pixel electrode124with the inter-electrode insulating film143interposed therebetween is held at a common potential. A potential difference is generated between the charged pixel electrode124and the common electrode125, and the display is made on the basis of the potential difference. The first shielding portion contact hole CH5and the second shielding portion contact hole CH6are respectively formed in the second interlayer insulating film139, the flattening film140, and the inter-electrode insulating film143, which are insulating films interposed between the common electrode125and the intermediate electrode146, and in the first interlayer insulating film137, which is an insulating film interposed between the intermediate electrode146and the light-transmitting shielding portion145, and thus the common electrode125and the light-transmitting shielding portion145are connected to the intermediate electrode146through the first shielding portion contact hole CH5and the second shielding portion contact hole CH6. That is, the common electrode125and the light-transmitting shielding portion145are connected via this intermediate electrode146and thus, compared to when the common electrode is directly connected to the light-transmitting shielding portion145, failure such as film breakage or the like is not readily generated in the common electrode125, resulting in high connection reliability. In addition, the second shielding portion47includes the third metal film138, which is the conductive film same as that of the intermediate electrode146, and is coupled to the intermediate electrode146, and thus, is connected to the common electrode125by interposing the intermediate electrode146along with the light-transmitting shielding portion145. Compared to when the second shielding portion and the intermediate electrode are constituted by different conductive films, the number of films can be reduced.

Third Embodiment

The third embodiment of the present invention will be described with reference toFIG. 17toFIG. 19. In this third embodiment, a configuration of a source line227is changed from that of the first embodiment described above. Note that redundant descriptions of structures, actions, and effects similar to those of the first embodiment described above will be omitted.

The source line227according to the present embodiment, as illustrated inFIG. 17, is formed of a second metal film236that is the same as that of a second gate electrode223E. Accordingly, in the present embodiment, the third metal film38constituting the source line27in the first embodiment described above is omitted, and the first interlayer insulating film37disposed on the lower layer side of the third metal film38is omitted. A second gate insulating film235disposed on the lower layer side of the second metal film236constituting the source line227is patterned along with the second metal film236, as described in the first embodiment described above. Therefore, on the lower layer side of the source line227, as illustrated inFIG. 18andFIG. 19, the second gate insulating film235is disposed overlapping substantially the entire region, excluding the gate contact hole CH4. Further, the source contact hole CH3connecting a source line widened portion227A of the source line227made of the second metal film236and a source region223B made of a semiconductor film234is formed in the second gate insulating film235interposed between the semiconductor film234and the second metal film236, as illustrated inFIG. 18. Further, with the third metal film38described in the first embodiment omitted, a pixel intermediate electrode231and an intermediate electrode246are constituted by the second metal film236same as that of the second gate electrode223E and the source line227, as illustrated inFIG. 17.

As described above, according to the present embodiment, the source line227is made of the second metal film236that is the conductive film same as that of the second gate electrode223E. In this way, compared to when the source line and the second gate electrode are constituted by different conductive films, the number of films can be reduced.

Other Embodiments

The present disclosure is not limited to the embodiments described above and illustrated by the drawings, and embodiments such as those described below are also included within the technical scope of the present disclosure.

(1) While, in each of the embodiments described above, a configuration has been illustrated in which the light-transmitting shielding portion includes the pixel electrode overlapping portion (light-transmitting pixel electrode overlapping portion) overlapping the pixel electrode, the configuration may be one in which the light-transmitting shielding portion is disposed not overlapping the pixel electrode and the pixel electrode overlapping portion (light-transmitting pixel electrode overlapping portion) is not included.

(2) While, in each of the embodiments described above, a configuration has been illustrated in which the light-transmitting shielding portion includes the gate line overlapping portion (light-transmitting gate line overlapping portion) overlapping the gate line, the configuration may be one in which the light-transmitting shielding portion is disposed not overlapping the gate line and the gate line overlapping portion (light-transmitting gate line overlapping portion) is not included. In particular, as in the second embodiment described above, as long as the configuration includes the second shielding portion overlapping the gate line, even if the light-transmitting gate line overlapping portion is omitted, an electrical field that may be generated near the side edge portion of the gate line can be blocked by the light-blocking gate line overlapping portion of the second shielding portion.

(3) While, in each of the embodiments described above, a configuration has been illustrated in which the light-transmitting shielding portion includes the non-overlapping portion, the pixel electrode overlapping portion, and the gate line overlapping portion, the light-transmitting shielding portion may not include the pixel electrode overlapping portion and the gate line overlapping portion and only include the non-overlapping portion. Conversely, the light-transmitting shielding portion may not include the non-overlapping portion and may include at least one of the pixel electrode overlapping portion and the gate line overlapping portion. When the light-transmitting shielding portion does not include the non-overlapping portion, a configuration in which the interval between the gate line and the pixel electrode is substantially not formed is possible.

(4) While, in the second embodiment described above, a case has been illustrated in which the second shielding portion includes the light-blocking gate line overlapping portion overlapping the gate line but the second shielding portion is disposed not overlapping the pixel electrode, the second shielding portion may further include a light-blocking pixel electrode overlapping portion overlapping the pixel electrode in addition to the light-blocking gate line overlapping portion.

(5) While, in each of the embodiments described above, a case has been illustrated in which the light-transmitting shielding portion and the common line are connected to the common electrode by different connection structures, the configuration may be one in which the light-transmitting shielding portion is connected to the common line and the light-transmitting shielding portion is not directly connected to the common electrode, that is, a configuration in which the light-transmitting shielding portion is connected to the common electrode by interposing the common line. Even in this case, the common potential transmitted by the common line is supplied to each of the light-transmitting shielding portion and the common electrode.

(6) In addition to the embodiments described above, a formation range and the like of the light-transmitting shielding portion in plan view can be changed as appropriate. Further, the formation range and the like of the second shielding portion, in plan view, described in the second embodiment can be changed as appropriate.

(7) While, in each of the embodiments described above, a case has been described in which the light-transmitting shielding portion is constituted by a reduced resistance region of the semiconductor film, the light-transmitting shielding portion may be constituted by a transparent electrode film, for example, as a conductive film having light-transmitting. In this case, the transparent electrode film is added separately from the first transparent electrode film constituting the pixel electrode and the second transparent electrode film constituting the common electrode, and the transparent electrode film may be disposed on the upper layer side of the first metal film constituting the gate line and on the lower layer side of the first transparent electrode film constituting the pixel electrode.

(8) In addition to the embodiments described above, the specific planar shape of the pixel electrode can be changed as appropriate. For example, the shape may be a planar shape in which the pixel electrode is bent so as to include a plurality of bent portions. Further, the planar shape of the pixel electrode including one bent portion may be different from that illustrated in each of the drawings and, for example, the bent portion may be disposed at a position other than the central position in the longitudinal direction of the pixel electrode. In addition, the pixel electrode may have a shape without a bent portion (for example, a rectangular shape or the like). Further, the pixel electrode may have a planar shape (such as a square) that is not a longitudinal shape.

(9) While, in each of the embodiments described above, a case has been illustrated in which the ratio of the longitudinal dimension to the short-hand dimension of the pixel electrode is three, it is also possible to change the ratio of the longitudinal dimension to the short-side dimension of the pixel electrode to a value other than three. For example, when the color filters aligned in the Y-axis direction are four colors (e.g., white in addition to R, G, and B), the ratio of the longitudinal dimension to the short-side dimension of the pixel electrode may be four.

(10) In addition to the embodiments described above, the specific routing paths of the source line and the gate line can be changed as appropriate. Similarly, the specific routing paths of the common line can be changed as appropriate.

(11) While, in each of the embodiments described above, the number of installations of the gate lines is equal to the arranged number of pixel electrodes in the Y-axis direction, and the number of installations of the source lines is equal to the arranged number of pixel electrodes in the X-axis direction, the number of installations of the gate lines in the liquid crystal panel may be twice the arranged number of pixel electrodes in the Y-axis direction, and the number of the source lines may be half the arranged number of pixel electrodes in the X-axis direction.

(12) While, in each of the embodiments described above, a TFT having a double-gate structure in which the first gate electrode and the second gate electrode are respectively disposed on the lower layer side and on the upper layer side of the channel region, the TFT may have a single gate structure in which the gate electrode is selectively disposed on the lower layer side or the upper layer side of the channel region. In a TFT of a top gate type in which the pixel electrode is disposed on the upper layer side of the channel region, it is also possible to remove the first metal film illustrated in each of the embodiments and configure the gate line with the second metal film. In this case, the light-transmitting shielding portion is preferably disposed not overlapping the gate line. On the other hand, in a TFT of a bottom gate type in which the pixel electrode is disposed on the lower layer side of the channel region, it is also possible to omit the second metal film or the third metal film illustrated in each of the embodiments. In this case, the source line, the pixel intermediate electrode, and the intermediate electrode may be configured by the second metal film or the third metal film, whichever one is not omitted.

(13) In addition to each of the embodiments described above, the specific screen size, resolution, and the like of the liquid crystal panel can be changed as appropriate.

(14) In addition to each of the embodiments described above, the specific arrangement pitch of the pixel portions in the liquid crystal panel can be changed as appropriate.

(15) While, in each of the embodiments described above, a case has been illustrated in which four drivers are mounted to the array substrate, the number of drivers mounted to the array substrate can be changed as appropriate.

(16) While, in each of the embodiments described above, a case has been illustrated in which the driver is Chip-on-Glass (COG) mounted directly to the array substrate, a flexible substrate on which the driver is chip-on-film (COF) mounted may be connected to the array substrate.

(17) While, in each of the embodiments described above, the gate circuit portion is provided to the array substrate, the gate circuit portion may be omitted, and a gate driver having a function similar to that of the gate circuit portion may be mounted to the array substrate. Further, it is also possible to provide a gate circuit portion to only one side portion on one side of the array substrate.

(18) In addition to the embodiments described above, the specific planar shape of the pixel overlapping opening provided to the common electrode can be changed as appropriate. The planar shape of the pixel overlapping opening can be, for example, a W-shape, a straight line, or the like. Further, the specific number of installations, arrangement pitch, and the like of the pixel overlapping opening can be changed as appropriate.

(19) While, in each of the embodiments described above, a case has been illustrated in which the pixel overlapping opening is provided to the common electrode, conversely a common electrode overlapping opening may be provided to the pixel electrode. Further, it is also possible to make the common electrode be made of the first transparent electrode film and the pixel electrode be made of the second transparent electrode film.

(20) While, in each of the embodiments described above, a case has been illustrated in which the TFT is disposed in a planar manner in a matrix shape in the array substrate, the TFT may be disposed in a planar manner in a zigzag shape.

(21) While, in each of the embodiments described above, a case has been illustrated in which the black matrix (inter-pixel light blocking portion) is provided to the CF substrate side, the black matrix (inter-pixel light blocking portion) may be provided on the array substrate side.

(22) In addition to each of the embodiments described above, the semiconductor film constituting the channel portion of the TFT may be polysilicon. In this case, when a single gate structure is adopted, it is preferable that the TFT be a bottom gate type or a top gate type including a light-blocking film at a lower layer of the channel portion (the side on which the backlight device is installed).

(23) In addition to the embodiments described above, the display mode of the liquid crystal panel may be vertical alignment (VA) mode, twisted nematic (TN) mode, in-plane switch (IPS) mode, or the like.

(24) While, in each of the embodiments described above, a liquid crystal panel without a built-in touch panel pattern that exhibits position detection functions is illustrated, the liquid crystal panel may be an in-cell type with a built-in touch panel pattern that exhibits a position detection function.

(25) While, in each of the embodiments described above, a liquid crystal display device including a transmissive liquid crystal panel is exemplified, the liquid crystal display device may be one that includes a reflective liquid crystal panel or a semi-transmissive liquid crystal panel.

(26) While, in each of the embodiments described above, a case has been illustrated in which the planar shape of the liquid crystal display device (liquid crystal panel or backlight device) is a horizontally elongated rectangular shape, the planar shape of the liquid crystal display device may be a longitudinally elongated rectangular shape, a square shape, a circular shape, a semi-circular shape, an elliptical shape, an oblong shape, a trapezoidal shape, or the like.