Capacitance sensing circuit

A capacitance sensing circuit for a touch panel includes an analog capacitance-detecting circuit, a PWM-to-digital circuit and a self-calibration circuit. The analog capacitance-detecting circuit detects the capacitance of the touch panel based on a charging current, and converts the detected capacitance into a PWM control signal. The PWM-to-digital circuit converts the PWM control signal into a sensing count value based on a clock signal. The self-calibration circuit adjusts the value of the charging current or the frequency of the clock signal according to the difference between the range of the sensing count value and a predetermined detecting range. The predetermined detecting range can thus be adjusted for matching the range of the sensing count value.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a capacitance sensing circuit, and more particularly, to a capacitance sensing circuit with adaptive detecting range for use in a touch panel.

2. Description of the Prior Art

Liquid crystal display (LCD) devices with thin appearance have gradually replace traditional bulky cathode ray tube (CRT) displays and been widely used in various electronic products. With rapid shrinkage in size, there is less room for traditional input devices such as keyboards or mice. Therefore, touch panels providing tactile inputs and display function have become more and more popular. There are various types of touch panels, such as resistive, capacitive, surface acoustic or infrared. Among those, capacitive touch panels detect capacitance variations corresponding to changes in static electricity caused by tactile inputs from a human finger or a stylus, thereby capable of determining the actual location of the touch action.

In a traditional capacitance sensing circuit, an analog capacitance-detecting circuit is normally adopted for detecting a measured capacitance CSENSEof a panel, based on which a corresponding digital signal is calculated using a counter. The measured capacitance CSENSEincludes a stray capacitance CPANELwhich is inherently present in the panel and a touch capacitance CFINGERwhich is present due to a touch action. Since panel size normally increases with resolution, the inherent stray capacitance CPANELalso increases accordingly. When a finger is in contact with the panel, the increase in the touch capacitance CFINGERis insignificant compared to the stray capacitance CPANELof the entire panel (CPANEL>>CFINGER). While the capacitance variations due to other noises are also much larger than that in the touch capacitance CFINGER, the prior art capacitance sensing circuit may not be able to provide accurate capacitance measurement. On the other hand, the capacitance input range is normally set within the optimized linear region of the capacitance sensing circuit. However, the prior art capacitance sensing circuit may operate in the non-linear region if the capacitance input range varies with humidity, temperature, operational environment, process or device aging, which largely reduces image resolution.

SUMMARY OF THE INVENTION

In order to overcome the disadvantages of the prior art, the present invention provides a capacitance sensing circuit with adaptive detecting range. The capacitance sensing circuit includes an analog capacitance-detecting circuit configured to detect a touch capacitance of a touch panel when a touch action occurs according to a charging current and convert a detected value of the touch capacitance into a PWM control signal; a PWM-to-digital circuit configured to convert the PWM control signal into a sensing count value according to a clock signal; and a self-calibration counter configured to adjust the charging current or the clock signal according to a difference between the sensing count value and a predetermined detecting range, thereby adjusting the predetermined detecting range for matching a range of the sensing count value.

DETAILED DESCRIPTION

FIG. 1Ais a capacitance sensing circuit10aaccording to a first embodiment of the present invention, andFIG. 1Bis a capacitance sensing circuit10baccording to a second embodiment of the present invention. The capacitance sensing circuit10aincludes an analog capacitance-detecting circuit200, a PWM (pulse width modulation)-to-digital circuit300a, and a self-calibration counter500a. The capacitance sensing circuit10bincludes an analog capacitance-detecting circuit200, a PWM-to-digital circuit300b, and a self-calibration counter500b. The capacitance sensing circuits10aand10bare configured to detect a measured capacitance CSENSEof a touch panel20and convert the detected capacitance into a PWM control signal. As previously stated, the measured capacitance CSENSEincludes the inherent stray capacitance CPANELof the panel20and the touch capacitance CFINGERdue to touch actions. The PWM-to-digital circuits300aand300bare configured to convert the PWM control signal into a digital sensing count value NSENSE. The structures and operations of theses devices will be described in more detail in subsequent paragraphs.

In the capacitance sensing circuit10aaccording to the first embodiment of the present invention, the self-calibration counter500aincludes an input-range calibrator400and a digital control current source700. The input-range calibrator400is configured to output a digital signal DNassociated with touch actions to a back-end circuit (such as a digital signal processor). Meanwhile, the capacitance sensing circuit10ais also configured to store and determine a capacitance-detecting range, based on which a range conversion ratio K is then generated for adjusting a charging current IMoutputted by the digital control current source700. The capacitance-detecting range may thus be optimized by adjusting the length of the overall pulse width.

In the capacitance sensing circuit10baccording to the second embodiment of the present invention, the self-calibration counter500bincludes an input-range calibrator400and a digital control oscillator800. The input-range calibrator400is configured to output a digital signal DNassociated with touch actions to a back-end circuit (such as a digital signal processor). Meanwhile, the capacitance sensing circuit10bis also configured to store and determine a capacitance-detecting range, based on which a clock signal CK of the digital control oscillator800is adjusted. The capacitance-detecting range may thus be optimized by adjusting the overall sampling clock.

FIG. 2is a diagram of an illustrated embodiment of the analog capacitance-detecting circuit200according to the present invention. The analog capacitance-detecting circuit200includes switches QN1-QN3and a comparator CMP. The switch QN1operates according to the PWM signal, the switch QN2operates according to a clock signal SG2, and the switch QN3operates according to a clock signal SG3. The duty cycle of the PWM control signal is determined by a ramp voltage VRAMP, and the clock signals SG2and SG3have opposite phases. The switches QN1-QN3may be metal-oxide-semiconductor (MOS) transistor switches or other devices having similar functions. For ease of explanation, N type metal-oxide-semiconductor (NMOS) transistor switches are used for illustration inFIG. 2. The switch QN1is configured to selectively transmit the charging current IMreceived at its first end to its second end according to the PWM signal received at its control end. The switch QN2, having a first end coupled to the second end of the switch QN1and a second end coupled to the panel20, is configured to control the charging path of the panel20by the charging current IMaccording to the clock signal SG2received at its control end. The switch QN3, having a first end coupled to the panel20and a second end coupled to a negative bias voltage VSS, is configured to control the discharging path of the panel20according to the clock signal SG3received at its control end. The comparator CMP includes a first input end for receiving a reference voltage VREF, a second input end coupled to the second end of the switch QN1, and an output end coupled to the control end of the switch QN1.

In the capacitance detecting circuit10ainFIG. 1A, the charging current IMprovided by the digital control current source700may be adjustable; in the capacitance detecting circuit10binFIG. 1B, the charging current IMmay be provided by a constant current source. When the PWM control signal and the clock signal SG2are at high level, the charging current IMis transmitted to the panel20via the turned-on switches QN1and QN2, thereby raising the ramp voltage VRAMP. When the ramp voltage VRAMPexceeds a reference voltage VREF, the PWM control signal outputted by the comparator CMP switches from high level to low level, thereby turning off the switch QN1. Next, the clock signal SG3switches to high level, thereby discharging the energy stored in the capacitance of panel20to the negative bias voltage VSS via the turned-on switch QN3. With TONrepresenting the duration in a period during which the PWM control signal is at high level (i.e. the turn-on time of the switch QN1), the charging process of the panel20can be illustrated by the following formulae:
IM*TON=CSENSE*VREF=(CFINGER+CPANEL)*VREF
TON=(CFINGER+CPANEL)/IM(1)

FIG. 3Ais a diagram of the PWM-to-digital circuit300aaccording to a first embodiment of the present invention.FIG. 3Bis a diagram of the PWM-to-digital circuit300baccording to a second embodiment of the present invention. In the first illustrated embodiment, the PWM-to-digital circuit300aincludes a phase adjusting unit310and an adder320. The phase adjusting unit310is configured to generate a clock signal CK having a predetermined trigger point and a predetermined frequency FCLK. The adder320is configured to receive the PWM control signal outputted by the analog capacitance detecting circuit200and measure the value of the PWM control signal when triggered by the clock signal CK. If the PWM control signal is at high level, the adder320increases its output sensing count value NSENSEby 1. In the second illustrated embodiment, the PWM-to-digital circuit300bincludes an adder320. The adder320is configured to receive the PWM control signal from the analog capacitance-detecting circuit200and the clock signal CK from the self-calibration counter500b, and measure the value of the PWM control signal when triggered by the clock signal CK. If the PWM control signal is at high level, the adder320increases its output sensing count value NSENSEby 1.

FIG. 4Ais a diagram illustrating the operation of the PWM-to-digital circuit300aaccording to the first embodiment of the present invention.FIG. 4Bis a diagram illustrating the operation of the PWM-to-digital circuit300baccording to the second embodiment of the present invention.FIGS. 4A and 4Bshow the ramp voltage VRAMP, the PWM control signal, the clock signal CK, and the sensing count value NSENSE. Since the stray capacitance CPANELis inherently present in the panel20, the PWM control signal outputted by the analog capacitance-detecting circuit200corresponds to a baseline count value NBASELINEeven without the occurrence of a touch action. When a touch action occurs, the PWM control signal outputted by the analog capacitance-detecting circuit200corresponds to the sensing count value NSENSE. The relationship between the baseline count value NBASELINEand the sensing count value NSENSEare depicted as follows:

According to formulae (2) and (3), an actual count value ΔN associated with the touch action can be obtained as follows:

As depicted in formula (1), the counting time during the turn-on time of the switch QN1in each period (such as TON, TON1-TON3) is determined by whether a touch action occurs and how long the touch action lasts. As depicted in formula (3), the count value NSENSEis inversely proportional to the charging current IMand directly proportional to the frequency fCLKof the clock signal CK. The present invention adjusts the capacitance-detecting range according to the actual count value ΔN, which will be described in more detail in subsequent paragraphs. In the capacitance sensing circuit10aaccording to the first illustrated embodiment, the self-calibration counter500achanges the counting time TON1-TON3by regulating the charging current IM, thereby adjusting the capacitance-detecting range as depicted inFIG. 4A; in the capacitance sensing circuit10baccording to the second illustrated embodiment, the self-calibration counter500badjusts the period of the clock signal CK so that the frequencies fCLK1-fCLK3are different, thereby adjusting the capacitance detecting range as depicted inFIG. 4B.

FIG. 5Ais a diagram of the self-calibration counter500aaccording to the first embodiment of the present invention.FIG. 5Bis a diagram of the self-calibration counter500baccording to the second embodiment of the present invention. The input-range calibrators400in the self-calibration counters500aand500beach include a subtractor410, a comparator420, a maximum value register430, a minimum value register440, a range-adjusting circuit450, and a counter460.

The subtractor410is configured to provide the actual count value ΔN associated with a touch action by subtracting the sensing count value NSENSEtransmitted from the PWM-to-digital circuit300aor300bby the baseline count value NBASELINE. The maximum value register430is configured to store the maximum count value NMAXwhich is the largest among all previously stored count values, while the minimum value register440is configured to store the minimum count value NMINwhich is the smallest among all previously stored count values. The range between the maximum count value NMAXand the minimum count value NMINrepresents the current predetermined capacitance-detecting range. The comparator420is configured to compare the actual count value ΔN with the maximum count value NMAXpreviously stored in the maximum value register430and with the minimum count value NMINpreviously stored in the minimum value register440: if the range of the actual count value ΔN is substantially equal to the predetermined capacitance-detecting range, the range-adjusting circuit450controls the digital control current source700or the digital control oscillator800according to the current actual count value ΔN; if the range of the actual count value ΔN is larger than the predetermined capacitance-detecting range, the range-adjusting circuit450multiplies the actual count value ΔN by a range conversion ratio K (K<1), based on which the charging current IMof the digital control current source700may be increased or the system clock CK of the digital control oscillator800may be decreased; if the range of the actual count value ΔN is smaller than the predetermined capacitance-detecting range, the range-adjusting circuit450multiplies the actual count value ΔN by a range conversion ratio K (K>1), based on which the charging current IMof the digital control current source700may be decreased or the system clock CK of the digital control oscillator800may be increased. Meanwhile, an adjustment period Tadjmay be set using the counter460. For example, if the adjustment period Tadjis set to 100, the range-adjusting circuit450only performs range adjustment each time after receiving 100 actual count values ΔN in order not to vary the capacitance-detecting range too often.

FIGS. 6A-6Care diagrams illustrating the operations of the self-calibration counters500aand500baccording to the present invention. Assuming that the maximum count value NMAXis equal to 1023, the minimum count value NMINis equal to 0, and TTOUCHrepresents the duration of a touch action. In the embodiment illustrated inFIG. 6A, the actual count value ΔN is within the predetermined capacitance-detecting range, and the range-adjusting circuit450thus controls the digital control current source700or the digital control oscillator800according to the current actual count value ΔN. In the embodiment illustrated inFIG. 6B, the range of the actual count value ΔN is 116-749, which means 0-155 and 750-1023 within the predetermined capacitance-detecting range can not be utilized. The range-adjusting circuit450thus enlarges the range of the original actual count value ΔN to 0-1023, thereby providing the optimized capacitance-detecting range. In the embodiment illustrated inFIG. 6C, the range of the actual count value ΔN is 0-1023, in which 1024-1682 is not included in the current predetermined capacitance-detecting range. The range-adjusting circuit450thus reduces the range of the original actual count value ΔN to 0-1023, thereby providing the optimized capacitance-detecting range.

FIG. 7is a diagram of the digital control current source700according to an embodiment of the present invention. The digital control current source700includes two transistor switches QPL and QPR, a capacitor CIN, a reference current source IM, and a current-adjusting circuit750. IMand IM′ respectively represent the conducting current of the transistor switches QPL and QPR, which may be P type metal-oxide-semiconductor (PMOS) transistor switches or other devices having similar function.

The current-adjusting circuit750may be implemented as a current mirror which includes a plurality of transistor switches QP1-QPn, each configured to provide a current whose value is a multiple of the conducting current IMof the transistor switches QPL and which is transmitted to the capacitor CINvia the switches SW1-SWn, respectively. In other words, a part of the conducting current IM′ is supplied by the transistor switch QPR, while other parts of the conducting current IM′ is the sum of the mirrored currents of the conducting current IMprovided by transistor switches QP1-QPn. The transistor switches QP1-QPn may be PMOS transistor switches or other devices having similar function. The conducting current IM′ increases with the number of the switches SW1-SWn which are turned on by the input-range calibrator400. If the actual count value ΔN is smaller than the predetermined capacitance-detecting range, the present invention turns on fewer switches SW1-SWn in order to decrease the charging current IM′. Since a longer capacitance charging time is required with smaller charging current IM′, the counting time may be increased for enlarging the capacitance-detecting range. If the actual count value ΔN is larger than the predetermined capacitance-detecting range, the present invention turns on more switches SW1-SWn in order to increase the charging current IM′. Since a shorter capacitance charging time is required with larger charging current IM′, the counting time may be decreased for reducing the capacitance-detecting range.

In conclusion, if the current capacitance-detecting range can not be effectively utilized when the capacitance input range varies with humidity, temperature, operational environment, process or device aging, the present invention updates the capacitance-detecting range according to the variation in the input capacitance. The updated capacitance-detecting range may thus be maintained in the linear region of the circuit in order to provide accurate capacitance measurement.