DEVICE STRUCTURE AND TECHNIQUES FOR FORMING SEMICONDUCTOR DEVICE HAVING ANGLED CONDUCTORS

A method of forming a device may include forming a component in a first level of a device structure; forming a contact cavity overlapping the component, the contact cavity forming a non-zero angle of inclination with respect to a perpendicular to a substrate plane. The method may further include filling the contact cavity with a conductor, wherein an angled conductor is formed, wherein the angled conductor extends to a second level of the device structure.

FIELD

The present embodiments relate to semiconductor device structures, and more particularly, to structures and processing for memory devices including dynamic random access devices.

BACKGROUND

As semiconductor devices, including logic devices and memory devices, such as dynamic random-access memory (DRAM) devices, scale to smaller dimensions, device patterning increasingly limits the ability to harness the improvements potentially resulting from smaller size. While many semiconductor devices are fabricated as three-dimensional structures, such as DRAM devices, fin-type field effect transistors (finFET), and other structures, fabricating such devices may involve the synthesis of different devices or components in a layer-by-layer fashion, often involving many sequential lithography operations. A given layer or level may define certain components arranged in planar fashion parallel to a surface of the substrate, meaning generally parallel to the flat face of a semiconductor wafer. Such device structures may be considered to be formed in many levels, where devices or components arranged in different levels may electrically communicate with one another through conductive structures arranged in vertical fashion, perpendicular to the substrate plane. As such, known device formation sequences entail layout of two different devices or components in different levels, where the first device is stacked vertically on top of a second device. Said differently, a first device arranged in a first level is arranged to overlap a second device in a second level in plan view, so a vertical connection may be formed between the two devices.

The above considerations place constraints upon device design in multi-level device structures, and in particular on so-called overlay issues. For example, an intervening component or device cannot be placed in an intervening level between a first level and second level, if the intervening component is positioned over the first component or under the second component, and blocks the vertical connection between the first device and second device. In present day DRAM devices, known architectures include so-called 8F2and 6F2, among others. While 6F2architecture provides a higher device density and greater speed than 8F2architecture, the ability to form memory devices having appropriate properties is compromised, in part because of patterning problems, such as overlay.

With respect to these and other considerations, the present disclosure is provided.

BRIEF SUMMARY

In one embodiment, a method of forming a device is provided. The method may include forming a component in a first level of a device structure, forming a contact cavity overlapping the component, the contact cavity forming a non-zero angle of inclination with respect to a perpendicular to a substrate plane. The method may include filling the contact cavity with a conductor, wherein an angled conductor is formed, wherein the angled conductor extends to a second level of the device structure.

In a further embodiment, a multi-level device may include a first component, disposed at least partially in a first level; a second component, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The multi-level device may further include an angled conductor, the angled conductor extending between the first component and the second component, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.

In another embodiment, a method of fabricating a multi-level semiconductor device may include forming an active device region in a first level of the semiconductor device. The method may include forming a set of conductor lines in an intermediate level of the semiconductor device, above the first level. The method may also include forming an angled conductor in contact with the active device region, the angled conductor forming a non-zero angle of inclination with respect to a perpendicular to a substrate plane of the semiconductor device, wherein the angled conductor does not contact the set of conductor lines. The method may further include forming an upper component in an upper level of the multi-level semiconductor device, above the intermediate level, wherein the angled conductor contacts the upper component.

DETAILED DESCRIPTION

The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, where some embodiments are shown. The subject matter of the present disclosure may be embodied in many different forms and are not to be construed as limited to the embodiments set forth herein. These embodiments are provided so this disclosure will be thorough and complete, and will fully convey the scope of the subject matter to those skilled in the art. In the drawings, like numbers refer to like elements throughout.

The present embodiments provide novel techniques and substrate structures to form devices, including logic devices and memory devices, formed in a semiconductor substrate. These techniques may especially be applicable to formation of DRAM devices, while other devices may also be formed according to the embodiments of the disclosure. These other devices may include NAND devices, including 3DNAND devices, NOR devices, X point memories and logic devices

In various embodiments novel techniques are provided to create electrical connections between semiconductor structures in semiconductor devices such as memory devices such as DRAM, NAND, 3DNAND, NOR, X point memories and Logic devices.

Various embodiments provide device structures and techniques employing angled conductor lines as well as angled trenches to enable new semiconductor architectures. Some embodiments provide structures to self-align vias at an angle relative to the surface of a substrate, such as a semiconductor wafer. These angled vias may increase contact area between structures disposed in different levels of a semiconductor device where the structures are not vertically aligned to one another vertically.

In particular embodiments, angled contacts are provided to link different devices or different components of semiconductor devices and circuits, where the different components are arranged in different levels of a multi-level device. In the embodiments to follow techniques and structures are provided where a contact cavity is formed to link a component on the first level of a multi-level device, to another component on another level of the multi-level device. A “component” may refer to a device, an active area of a device, such as a semiconductor region, a conductive structure, such as a conductive line, or other structure, such as a capacitor. The contact cavity of the present embodiments may be arranged at a non-zero angle of inclination with respect to a perpendicular to a substrate plane, meaning the contact cavity is not arranged in a vertical fashion between different levels. The contact cavity may then be filled with a conductor to form an angled conductor linking different components, disposed on different levels of the multi-level device. Because the angled conductor and therefore the contact cavity is disposed at a non-zero angle of incidence, the first end and second end of the angled conductor may be shifted from one another within the substrate plane, as opposed to vertical contact structures, where the first end and second end are mutually disposed over or under one another. In some examples, the first end and second end of the angled conductor may not overlap one another at all. As described below, in configurations of multi-level devices having at least three levels, this novel geometry provides distinct advantages over known device structures. According to some embodiments, described below, a plurality of different angled cavity structures may be formed in a device structure, where the different angled cavity structures are used to form different angled features, operating synergistically to provide improved arrangement of components within a multi-level device structure.

FIG. 1AtoFIG. 1Gshow a device structure100arranged within a substrate101, at various stages of fabrication, according to some embodiments of the disclosure. The substrate101may include other features (not shown), such as a subjacent substrate base, formed of a semiconductor material, such as silicon. The sequence shown begins at a stage of fabrication of a device at a first level102, where the first level102includes a component, shown as an active region106, and an insulator region108, meaning an electrical insulator. The first level may be an isolation level, such as a so-called shallow trench isolation (STI) level, where the active region is monocrystalline semiconductor, such as silicon. The embodiments are not limited in this context. At the instance inFIG. 1A, an insulator layer110has been deposited, defining an adjacent level104. The adjacent level104may be used to define various components or portions of components, including contacts.

Turning toFIG. 1B, there is shown an instance after formation of a mask112on the insulator layer110. The mask112is patterned in a manner to generate an array of openings115. A given opening is used to form a contact via, as detailed below. According to various embodiments, the mask112may include a combination of at least one layer, such as known layers used for patterning, including, but not limited to, nitride, carbon, oxide, or resist. In various non-limiting embodiments, the thickness of the mask112may range from 10 nm to 100 nm. The mask112may be generally made of a different material than the insulator layer110. The mask112may accordingly be used to transfer the pattern of the array of openings115into insulator layer110. As further depicted inFIG. 2B, first angled ions114are directed to the substrate101in a first ion exposure at a non-zero angle of incidence (θ) with respect to a perpendicular103to a substrate plane105. As such, the first angled ions114may etch the insulator layer110, forming angled cavities116. The first angled ions114may etch the insulator layer110(such as silicon oxide, silicon nitride) in a manner selective to the mask112. For example, the first angled ions114may be provided in a reactive ion etching gas composition suitable to etch the insulator layer110at a higher etch rate than the etch rate of material of the mask112. Such recipes are well known for various mask/insulator combinations, including carbon, oxide, nitride, metal(s), and will not be discussed further herein. In other examples where the mask112has sufficient thickness, such as a known hard mask material or a photoresist material, the etch rate of the insulator layer110need not be faster than the etch rate of the material of mask112, to the extent the mask112is not completely eroded before completion of etching of the insulator layer110. After formation of angled cavities116, the angled cavities116may subsequently be filled with conductive material, forming conductive angled structures118, shown inFIG. 1C. As an example, the conductive angled structures118may be formed of silicon or polysilicon in the adjacent level104.

Subsequently to the instance ofFIG. 1C, an additional layer and additional level of the device structure100may be formed, on top of the adjacent level104. For example, in a device structure using conductive lines to interconnect various components, a metal layer may be deposited over the adjacent level104. As an example, a blanket metal deposition may be performed using known techniques to form a blanket layer over the adjacent level104. In embodiments of a DRAM device, the blanket layer may constitute a conductor level for forming wiring to cells of the DRAM device, such as a bitline level. InFIG. 1D, this conductor level is shown as intermediate level120. Exemplary materials for use as a conductor in the intermediate level120may be any suitable metal material, such as tungsten (W), a layer structure, such as W/Ruthenium, and alloy, or other suitable metal. As shown inFIG. 1D, a mask124is deposited on the metal of the intermediate level120, while second angled ions126are directed toward the substrate101. The second angled ions126may, but need not, etch the metal of intermediate level120at a faster etch rate than an etch rate of the material of mask124. As such, the second angled ions126may etch the metal layer throughout the thickness of the intermediate level120, forming angled cavities128, where the angled cavities also define angled conductor lines122. In accordance with some embodiments, the angled conductor lines122may be positioned and angled in a manner to locate the bottom surfaces of the angled conductor lines122to contact designed components in the subjacent layer, such as angled conductive angled structures118in adjacent level104.

In a subsequent operation, depicted atFIG. 1E, the intermediate level120may be filled with insulator130and polished, resulting in the structure shown, where insulator130is disposed between the angled conductor lines122.

Turning now toFIG. 1F, a subsequent operation is depicted, where a mask131is deposited on the intermediate level120. The mask131may be patterned in a manner where openings133in the mask131are aligned with the regions of insulator130. As shown inFIG. 1F, third angled ions132are directed toward the substrate101, and impact regions of insulator130in the intermediate level120, as well as insulator layer110in adjacent level104. The third angled ions132may, but need not, etch the material of the insulator130and insulator layer110faster than material of the mask131. As such, the third angled ions132may etch insulator material throughout the thickness of the intermediate level120, and the adjacent level104, forming angled cavities134, where the angled cavities134extend to the first level102, and abut against the active region106. As shown inFIG. 1F, a liner135may be formed in the angled cavities134, where the liner135is made of an insulator material.

Turning toFIG. 1Gthere is shown a subsequent instance after the angled cavities134are filled with a suitable conductor, forming angled conductors136. As shown, the angled conductors136extend through the adjacent level104, and intermediate level120to contact the active region106. While not shown explicitly inFIG. 1G, in various embodiments, the angled conductors136may abut against a component in a higher level, above the intermediate level120. InFIG. 1H, the

Turning toFIG. 1Hthere is shown one variant of the device structure100, after formation of a component140, in an upper level142, where the upper level142is disposed above the intermediate level120. Various components discussed above are omitted for clarity. Shown inFIG. 1Hare details of the geometry of the angled conductor136. The angled conductor136may be arranged at a non-zero angle of inclination with respect to the perpendicular103to the substrate plane105(X-Y plane). In this variant, conductor lines122A are disposed directly over the active regions106. The conductor lines122A need not be angled conductor lines, as described with respect toFIG. 1D. In this example, the device structure100represents a multi-level device, such as a multi-level semiconductor device, where a first component (active region106) formed in a first level102is electrically connected to a second component (component140) is a second level (upper level142) using an angled conductor136.

A salient feature of the geometry ofFIG. 1His where a third component (conductor lines122A) is arranged above the first component (active region106), while a given conductor line of conductor lines122A is not in electrical contact with the active region106, below. In other words, the angled conductor136establishes electrical contact between the active region106and component140, in a higher level, while another component (conductor lines122A) is disposed above the active region106and does not electrically contact the angled conductor136.

In some embodiments, the active region106may be an active semiconductor region of a dynamic random-access memory (DRAM) cell, where the angled conductor lines122comprise a bitlines of the DRAM cell, and the component140comprises a storage capacitor.

As further shown inFIG. 1H, the angled conductor avoids incomplete overlap of the bottom surface of a conductor connecting the active region106to a component140in a higher level, when the conductor is arranged as a vertical conductor. Notably, when a component (conductor lines122A) is disposed in an intermediate level between another component (active region106) in a first level, and a further component (component140) in a higher level, the use of a vertical conductor136A may force shifting the position of the vertical conductor136A to avoid the conductor lines122A. This shifting (in the X-Y plane) results in an undesirable incomplete overlap between the bottom surface of the conductor and the active region106.

While the embodiment ofFIG. 1Hillustrates an angled conductor where the bottom surface137is displaced with respect to the top surface139along a first direction (Y-axis) in the X-Y plane in other embodiments, in additional embodiments, the bottom surface and top surface of an angled conductor may be shifted from one another in the X- and Y direction.FIG. 2A,FIG. 2B, andFIG. 2Cdepict components of the intermediate level120to illustrate different configurations of an angled conductor. InFIG. 2A, the angled conductor lines122are shown extending along the X-axis in an array of lines within the X-Y plane. AtFIG. 2B, the insulator130is shown, disposed between the angled conductor lines122.

AtFIG. 2C, a portion of the angled conductor136is shown in cross-section, where the angled conductor136is arranged in a two-dimensional array of angled conductors136. In this example, the angled conductor136may represent an array of conductive vias, linking a first level and an upper level. InFIG. 2C, a projection152of an angled conductor136within the X-Y plane is shown, consistent with the geometry ofFIG. 1H, where the angled conductor extends under the angled conductor lines122at the first level102. In the variant of angled conductor136shown by projection152, the angled conductor position of the angled conductor136does not change along the X-axis. InFIG. 2C, another projection, shown as projection154of the angled conductor136within the X-Y plane is shown, consistent with the geometry ofFIG. 1H, where the angled conductor extends under the angled conductor lines122at the first level102. In the variant of angled conductor136shown by projection154, the angled conductor position of the angled conductor136does change along the X-axis.

Turning now toFIG. 3A, there is shown a processing apparatus300, depicted in schematic form. The processing apparatus300represents a processing apparatus for etching portions of a substrate, to form angled cavities, as generally described above. The processing apparatus300may be a plasma based processing system having a plasma chamber302for generating a plasma304therein by any convenient method as known in the art. An extraction plate306may be provided as shown, having an extraction aperture308, where a selective etching may be performed to reactively etch an insulator layer with respect to a mask material. A substrate220, including, for example, the aforementioned structure, device structure100, is disposed in the process chamber322. A substrate plane of the substrate220is represented by the X-Y plane of the Cartesian coordinate system shown, while the perpendicular103to the plane of the substrate220lies along the Z-axis (Z-direction).

The processing apparatus300may employed to generate angled structures by performing an angled reactive ion beam etching, where reactive species may be provided as part of an ion beam or in addition to the ion beam. During an angled reactive ion beam etching operation, an ion beam310is extracted through the extraction aperture308. As shown inFIG. 3A, the ion beam310forms a non-zero angle of incidence with respect to the perpendicular103, shown as θ. The trajectories of ions within the ion beam310may be mutually parallel to one another or may lie within a narrow angular range, such as within 10 degrees of one another or less. Thus, the value of θ may represent an average value of incidence angle where the individually trajectories vary up to several degrees from the average value. The ion beam310may be extracted when a voltage difference is applied using bias supply320between the plasma chamber302and substrate220as in known systems. The bias supply320may be coupled to the process chamber322, for example, where the process chamber322and substrate220are held at the same potential. In various embodiments, the ion beam310may be extracted as a continuous beam or as a pulsed ion beam as in known systems. For example, the bias supply320may be configured to supply a voltage difference between plasma chamber302and process chamber322, as a pulsed DC voltage, where the voltage, pulse frequency, and duty cycle of the pulsed voltage may be independently adjusted from one another.

In various embodiments, for example, the ion beam310may be provided as a ribbon ion beam having a long axis extending along the X-direction of the Cartesian coordinate system shown inFIG. 3B. As further shown inFIG. 3C, during the operation ofFIG. 3A, the substrate220may be oriented in a manner where the long direction of the angled conductor lines122may be oriented at a desired twist angle θ with respect to the long axis of the extraction aperture308. As shown by the arrows inFIG. 3C, the projection (in the X-Y plane) of trajectories of ions of the ion beam310align perpendicularly with respect to the long axis of the extraction aperture308. Thus, in addition to defining the non-zero angle of incidence with respect to the perpendicular, shown as θ. InFIG. 3A, the ion beam310also defines a twist angle with respect to a substrate, or a set of structures within a substrate. Thus, when the angled conductor lines122are oriented with their long direction parallel to the long axis of the extraction aperture308, the angled conductors136may be generated with the orientation as represented by the projection152. When the long direction of the angled conductor lines122are oriented to define a non-zero twist angle, the angled conductors136may be generated with the orientation as represented by the projection154.

By scanning a substrate stage314including substrate220with respect to the extraction aperture308, and thus with respect to the ion beam310along the scan direction316, the ion beam310may etch a set of angled cavities oriented at a non-zero angle of inclination with respect to the perpendicular103, across different portions of the substrate220. In this example ofFIG. 3B, the substrate220is a circular wafer, such as a silicon wafer, the extraction aperture308is an elongated aperture, having an elongated shape. The ion beam310is provided as a ribbon ion beam extending to a beam width along the X-direction, where the beam width is adequate to expose an entire width of the substrate101, even at the widest part along the X-direction. Exemplary beam widths may be in the range of 10 cm, 20 cm, 30 cm, or more while exemplary beam lengths along the Y-direction may be in the range of 3 mm, 5 mm, 10 mm, or 20 mm. The embodiments are not limited in this context.

According to the present embodiments, the ion beam310may be composed of any convenient gas mixture, including inert gas, reactive gas, and may be provided in conjunction with other gaseous species in some embodiments. In particular embodiments, the ion beam310and other reactive species may be provided as an etch recipe to the substrate220so as to perform a directed reactive ion etching of material within a given level of a device structure, such as device structure100. Such an etch recipe may use known reactive ion etch chemistries for etching materials such as oxide, nitride, metal or other material, as known in the art. For a given etch operation, the reactive etch recipe may, but need not be, selective with respect to the material a mask. In accordance with embodiments of the disclosure, a series of different angled cavities may be etched in a series of different etch operations using the processing apparatus300, where the geometry of the ion beam310, as well as the chemistry of the plasma304may be adjusted as appropriate between the different etch operations.

FIG. 4AandFIG. 4Bdepict exemplary results of angled reactive ion beam etching to form angled cavities using a processing apparatus arranged according toFIG. 3A. InFIG. 4A, a substrate400is provided, having a nitride layer402, and an oxide mask404, disposed on the nitride layer402. The oxide mask404is formed from an array of 45 nm lines separated by 45 nm. A reactive ion beam etching process has been performed wherein an ion beam is directed at a 45-degree angle of incidence with respect to the perpendicular to the substrate plane, as described above. As shown inFIG. 4B, a series of angled cavities406are formed within the nitride layer402, at an angle of inclination of 45 degrees.

FIG. 5depicts an exemplary process flow500, according to embodiments of the disclosure. At block502, a lower component is formed in a lower level of a semiconductor device. In some examples, the lower component may be an active device region, such as a semiconductor region.

At block504, an intermediate component is formed above the lower component in an intermediate level.

At block506, an angled conductor is formed in contact with the lower component, in a manner where the angled conductor does not contact the intermediate component in the intermediate level. In some embodiments, the angled conductor may be formed by reactive ion beam etching of a material. In some embodiments may be formed by etching material disposed in more than one level, to form an angled cavity, to be filled by any suitable conductive material.

At block508, an upper component is formed in an upper level, above the intermediate level, where the upper component is in contact with the angled conductor. In this manner, a lower component in a lower level may be electrically connected to an upper component in an upper level, while avoiding contact with an intermediate component in an intermediate level, disposed between the lower level and the upper level.

The present embodiments provide various advantages over known device structures including logic devices, hybrid devices, and memory device such as DRAM devices. For one advantage, the use of angled conductors provides design flexibility for designing different levels of a multi-level device, since components to be connected in different levels need not be situated over one another. For another advantage, contact area between a conductor and components in different levels can be maximized, since use of an angled conductor allows two different components to be shifted from one another in the X-Y plane, while still completely overlapping the angled conductor.