Multi-processor system and controlling method thereof

In order to control sub-processors in parallel without losing extensibility, an execution control circuit (30), which forms a multi-processor system (1), issues a process command (CMD) to each of sub-processors (20—1 to 20—3) based on a process sequence (SEQ) designated by a main processor (10), and acquires a process status (STS) which indicates an execution result of processing executed by each of the sub-processors (20—1 to 20—3) in accordance with the process command (CMD). An arbiter circuit (40) arbitrates transfer of the process command (CMD) and the process status (STS) between the execution control circuit (30) and each of the sub-processors (20—1 to 20—3).

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a National Stage of International Application No. PCT/JP2009/001827 filed Apr. 22, 2009, claiming priority based on Japanese Patent Application No. 2008-203768 filed Aug. 7, 2008, the contents of all of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present invention relates to a multi-processor system and a controlling method thereof, and particularly to a multi-processor system which controls a plurality of sub-processors in parallel and a controlling method thereof.

BACKGROUND ART

A multi-processor system is typically classified into the one of type SMP (Symmetric Multi-Processor) in which functions are homogeneously and symmetrically allocated to respective sub-processors, or into the one of type AMP (Asymmetric Multi-Processor) in which the functions are heterogeneously and asymmetrically allocated to the respective sub-processors.

In the multi-processor system of type AMP, a method where a main processor directly controls a plurality of other sub-processors has been traditionally used. This method is the one where the main processor, which manages the whole system to execute principal processing, also performs activation control of each of the sub-processors functionally distributed. The control over each sub-processor is performed by use of a system bus to which the main processor has the right of access. Each sub-processor inputs an interrupt signal to the main processor, and then the main processor checks the status of each sub-processor by using the system bus, whereby a process completion notification from each sub-processor is performed. Thus, it is possible to aggregate management of the status of the whole system and management of the status of each sub-processor in one place. Therefore, there are advantages of facilitating consideration and implementation of a control sequence in the whole multi-processor system, and of enhancing observability upon debug.

However, in the above-mentioned method, there is a problem that processing in the whole system LSI (Large Scale Integration) collapses due to the growing scale and complexity of the system LSI in recent years. The major factor is that, in the traditional architecture where the main processor performs the whole control, processing load concentrates in the main processor to be congested due to an increase in the number of sub-processors mounted in the system LSI.

There have been already proposed first to third related art for addressing this problem. Hereinafter, the first to third related art will be sequentially described.

FIRST RELATED ART

Patent Literature 1 discloses a multi-processor system including an execution control device which parallelly controls sub-processors as substitute for a main processor. The execution control device generally makes two or more sub-processors operate in a pipelined parallel manner, thereby enhancing load distribution from the main processor and availability of each sub-processor.

Specifically, as shown inFIG. 22, this multi-processor includes a master processor1110operating as the main processor, a slave processor1120and a DMA (Direct Memory Access) controller1130operating as the sub-processors, a local memory1121used as a work area for the slave processor1120, a main memory1140, and a command execution control device1150. In this example, the DMA controller1130controls transfer of data between the local memory1121and the main memory1140. Note that four banks #0to #3are allocated to the local memory1121.

Further, the command execution control device1150includes a communication memory1151in which a plurality of commands used by the master processor1110are preliminarily stored, a command queue1152which accepts series of commands from the master processor1110, an execution controller1160which makes the slave processor1120and the DMA controller1130parallelly execute each command in the series of commands accepted by the command queue1152, a completion acceptor1153which receives completion notification signals indicating execution completion of the command from the slave processor1120and the DMA controller1130, and a completion notifier1170which transmits the completion notification signal in response to a request from the master processor1110.

Further, the execution controller1160includes next command ID holders1161and1162, and a bank table1163. The next command ID holders1161and1162are memory areas for storing IDs of commands which the execution controller1160must make the slave processor1120and the DMA controller1130execute next time. Further, the bank table1163manages virtual bank number used upon instructing access to the local memory1121by the command, in association with physical bank number for actually identifying the bank in the local memory1121.

Furthermore, the completion notifier1170is provided with a completion table1171for managing whether or not the execution of each command has been completed.

SECOND RELATED ART

While not shown in drawings, there has been generally known a technique of implementing a status register in order to check the status of a different sub-processor. Specifically, when one sub-processor writes change in its own status in the status register in a case of desiring to notify the status change, an interrupt signal is generated for another sub-processor which is the notification destination. The sub-processor, which has received the interrupt signal, acquires the status change from the status register.

THIRD RELATED ART

Patent Literature 2 discloses a multi-processor system where communication between two processors is conducted by use of a FIFO (First In First Out) buffer. Specifically, as shown inFIG. 23, this multi-processor system includes a FIFO buffer2103used for communication between processors2101and2102, and an access control circuit2104which controls access to the FIFO buffer. Further, the access control circuit2104is provided with a capacity set register2105for setting the number of stages of data in the FIFO buffer2103. In accordance with the setting value in the register2105, distribution of capacity of the FIFO buffer2103is performed for each of the processors2101and2102. Furthermore, access from the respective processors2101and2102to the FIFO buffer2103is controlled by respectively using write pointers2106and2108, and read pointers2107and2109.

CITATION LIST

Patent Literature

Patent Literature 1

Japanese Unexamined Patent Application Publication No. 2003-208412

Patent Literature 2

Japanese Unexamined Patent Application Publication No. 2003-036240

SUMMARY OF INVENTION

Technical Problem

However, in the above-mentioned first to third related art, there is a problem of being low in extensibility of the multi-processor system. This is because circuit configuration depends on the number of sub-processors.

Specifically, in the execution control device of the above-mentioned first related art, internal circuit configuration depends on the number of sub-processors connected thereto for the reason that the completion notification signals are input from the respective sub-processors in parallel or the like. As described above, in the recent system LSI, a plurality of sub-processors are generally integrated into a single chip and it is required to extend the system (in other words, to increase the number of sub-processors) in a short period. However, it is necessary for the circuit configuration of the execution control device to be changed for every extension of the system.

Further, in the above-mentioned second related art, the number of required status registers changes depending on the number of sub-processors, the number of statuses (the number of types of status changes), and the like. Therefore, it is still necessary for circuit configuration to be changed for every extension of the system. In order to address this, measures to preliminarily implement a lot of status registers may be considered. However, cost of development increases in this case.

Furthermore, in the above-mentioned third related art, it is required to increase the number of FIFOs and communication paths between processors, depending on the number of processors. After all, the change of circuit configuration accrues for every extension of the system.

Accordingly, the present invention aims to provide a multi-processor system and a controlling method thereof, which can control sub-processors in parallel without losing extensibility.

Solution to Problem

In order to achieve the above-mentioned aim, a multi-processor system according to one exemplary aspect of the present invention includes: at least one main processor; a plurality of sub-processors; an execution control means for issuing a process command to each of the sub-processors based on a process sequence designated by the main processor, and acquiring an execution result of processing executed by each of the sub-processors in accordance with the process command; and an arbiter means for arbitrating transfer of the process command and the execution result between the execution control means and each of the sub-processors.

Further, a controlling method of a multi-processor system according to one exemplary aspect of the present invention provides a method of controlling a multi-processor system that includes at least one main processor and a plurality of sub-processors. This method includes: issuing a process command to each of the sub-processors based on a process sequence designated by the main processor, and acquiring an execution result of processing executed by each of the sub-processors in accordance with the process command; and arbitrating transfer of the process command to each of the sub-processors, and transfer of the execution result to the main processor.

Advantageous Effects of Invention

According to the present invention, an interface part which depends on the number of sub-processors is absorbed in an arbiter circuit (or processing equivalent thereto). Therefore, even when the number of sub-processors increases or decreases, no change occurs in configuration of an execution control circuit (or processing equivalent thereto). Accordingly, it is possible to greatly improve extensibility of a multi-processor system compared with the above-mentioned first to third related art. Further, the sub-processors are controlled in parallel. Therefore, it is possible to reduce processing load of a main processor, and to enhance availability of the sub-processors.

DESCRIPTION OF EMBODIMENTS

Hereinafter, first to fifth exemplary embodiments of a multi-processor system according to the present invention will be described with reference toFIGS. 1 to 14,15A and15B, and16to21. Note that the same signs are assigned to the same elements throughout the drawings, and their duplicated explanation is omitted as appropriate for clarifying the description.

Firstly, a configuration example and an operation example, which are common to multi-processor systems according to the first to fifth exemplary embodiments, are schematically described with reference toFIGS. 1 to 3.

As shown inFIG. 1, a multi-processor system1includes a main processor (hereinafter, occasionally abbreviated as MP)10, “n” units (n is an integer number of two or more) of sub-processors (function blocks)20_1to20—n, an execution control circuit30which issues a process command CMD to each of the sub-processors20_1to20—nbased on a process sequence SEQ designated by the main processor10and acquires a process status STS indicating an execution result of processing executed by each of the sub-processors20_1to20—nin accordance with the process command CMD; and an arbiter circuit40which arbitrates transfer of the process command CMD and the process status STS between the execution control circuit30and each of the sub-processors20_1to20—n. Further, the execution control circuit20transmits a process completion notification NTF to the main processor10when all processes based on the process sequence SEQ are completed.

Note that to the sub-processors20_1to20—n, the same function or mutually different functions may be allocated. Namely, the multi-processor system1can operate as any one of type SMP and type AMP.

The above-mentioned process sequence SEQ is a group of structures where a structure in which processing to be executed by each sub-processor is defined, and a structure in which data to be obtained by the processing is defined are linked with each other.FIG. 2shows a specific example of the process sequence SEQ. In the example shown inFIG. 2, the process sequence SEQ indicates the following (1) to (4):

(1) Data D0and D1are obtained by a process PA as output data;

(2) A process PB treats the data D0as input data, and makes data D2as output data;

(3) A process PC treats the data D1as input data, and makes data D3as output data; and

(4) A process PD treats the data D2and D3obtained by the processes PA and PB as input data.

In this case, the execution control circuit30receives a process status STS indicating completion of outputting the data D0from a sub-processor which has executed the process PA, and then issues a process command CMD to start the process PB. The execution control circuit30receives a process status STS indicating completion of outputting the data D1, and then issues a process command CMD to start the process PC. Further, the execution control circuit30receives process statuses STS indicating completion of outputting the data D2and D3from two units of sub-processors which have executed the process PB and PC, and then issues a process command CMD to start the process PD. Note that although the illustration is omitted, commands CMD to start the respective processes PA to PD are defined in the structure in the process sequence SEQ.

Next, overall operation of the multi-processor system1is described with reference toFIG. 3.

As shown inFIG. 3, when there are parameters (including input data) for operating the sub-processors, the main processor10stores the parameters in e.g. a shared memory50which can be accessed from each sub-processor (Step S1). Then, the main processor10outputs the process sequence SEQ to the execution control circuit30(Step S2).

Taking the process sequence SEQ shown inFIG. 2as an example, the execution control circuit30issues a process command CMD1to start the process PA to e.g. the sub-processor20_1, and outputs the process command CMD1to the arbiter circuit40. The arbiter circuit40transfers the process command CMD1to the sub-processor20_1(Step S3).

The sub-processor20_1reads parameters required for the process PA from the shared memory50and executes the process PA, in accordance with the process command CMD1(Steps S4and S5). Then, the sub-processor20_1writes the data D0obtained by the process PA in the shared memory50(Step S6).

After that, the sub-processor20_1transmits a process status STS1which indicates completion of the process PA to the arbiter circuit40. The arbiter circuit40transfers the process status STS1to the execution control circuit (Step S7).

The execution control circuit30recognizes the completion of the process PA, and then outputs a process command CMD2to start the process PB to e.g. the sub-processor20_2through the arbiter circuit40(Step S8).

The sub-processor20_2reads the data D0required for the process PB from the shared memory50and executes the process PB, in accordance with the process command CMD2(Steps S9and S10). Then, the sub-processor20_2writes the data D2obtained by the process PB in the shared memory50(Step S11), and transfers a process status STS2which indicates completion of the process PB to the execution control circuit30through the arbiter circuit40(Step S12).

While not shown, in parallel with the above-mentioned Step S8, the execution control circuit30outputs a process command to start the process PC to any one of the sub-processor20_1and the sub-processors20_3to20—n, in accordance with the process sequence SEQ. The sub-processor, which has received this process command, executes the process PC in parallel with the above-mentioned Steps S9to S12, writes the data D1obtained by the process PC in the shared memory50, and transfers a process status which indicates completion of the process PC to the execution control circuit30. Then, the execution control circuit30outputs a process command to start the process PD to any one of the sub-processors20_1to20—n. The sub-processor, which has received this process command, executes the process PD, writes data obtained by the process PD in the shared memory50, and transfer a process status which indicates completion of the process PD to the execution control circuit30.

Then, the execution control circuit30recognizes that all of the processes PA to PD are completed, and then transmits the process completion notification NTF to the main processor10(Step S13). The main processor10, which has received the process completion notification NTF, reads the output data in the process PD from the shared memory50(Step S14).

In this way, the multi-processor system1can parallelly controls the sub-processors without depending on the number thereof. Further, it is not necessary for the main processor10to perform execution control for the sub-processors20_1to20—nuntil a series of process sequences are completed, so that it is possible to reduce processing load of the main processor10. Note that the above-mentioned shared memory50is not essential. For example, the data may be exchanged between the main processor10and the sub-processors20_1to20—n, by including the parameters required for each process in the process command CMD, and by including the output data obtained by each process in the process status STS or the process completion notification NTF.

Hereinafter, the first to fifth exemplary embodiments will be sequentially described in detail with reference toFIGS. 4 to 14,15A and15B, and16to21.

First Exemplary Embodiment

Configuration Example

As shown inFIG. 4, a multi-processor system1aaccording to this exemplary embodiment includes a main processor10, “n” units of sub-processors20_1to20—n, an execution control circuit30awhich is connected to the main processor10through a system bus B1, an arbiter circuit40which is connected to the execution control circuit30athrough a control bus B2and a status bus B3, and which connects the sub-processors20_1to20—nin parallel to the buses B2and B3, and an interruption controller60which is connected as a peripheral to the system bus B1and the execution control circuit30a. The control bus B2is the one for transferring the above-described process command CMD. The status bus B3is the one for transferring the process status STS.

Further, the execution control circuit30aincludes an interface (hereinafter, referred to as MP interface) IF1to the main processor10, an interface (hereinafter, referred to as B2interface) IF2to the control bus B2, an interface (hereinafter, referred to as B3interface) IF3to the status bus B3, and an interface (hereinafter, referred to as interruption interface) IF4to the interruption controller60.

Furthermore, the execution control circuit30aincludes a control processor (hereinafter, occasionally abbreviated as CP)31, a data memory MEM1for storing the process sequence SEQ input from the main processor10through the IF1, a command memory MEM2in which instruction codes for analyzing the structures in the process sequence SEQ are preliminarily stored, a command FIFO32for storing a command (for example, a command to start the process sequence SEQ (hereinafter, sequence start command)) input from the main processor10through the IF1, a status FIFO33for storing the process status STS input through the IF3, and an interruption FIFO34used for notifying an interruption factor to the main processor10. Since the interruption FIFO34is used, the multi-processor system1ahas high extensibility compared with a multi-processor system in which a general interruption factor register is implemented (in other words, the number of registers depends on the number of interruption factors). Further, since the status FIFO33is used, the multi-processor system1ahas high extensibility compared with a multi-processor system in which such a status register as described in the second related art is implemented. Furthermore, it is not necessary to implement the redundant hardware resource. Therefore, it is possible to prevent the cost of development from increasing.

The data memory MEM1, the command memory MEM2, the command FIFO32and the interruption FIFO34are connected to the IF1through an MP bus B4. Further, the control bus B2, the data memory MEM1, the command FIFO32, the status FIFO33and the interruption FIFO34are mutually connected through a CP bus B5. Furthermore, a bus switch SW enables the main processor10and the control processor31to select the right of access to the CP bus B5. Upon normal operation, the control processor31acquires the right of access to the CP bus B5as shown inFIG. 4. On the other hand, upon a test or the like, the main processor10acquires the right of access to the CP bus B5.

Further, the arbiter circuit40includes a control bus control circuit41which controls transfer of the process command CMD to the control bus B2, and a status bus arbiter circuit42which arbitrates access from the sub-processors20_1to20—nto the status bus B3upon transferring the process status STS. As shown inFIG. 4, each of the control bus control circuit41and the status bus arbiter circuit42can be simply materialized in a single-layer bus configuration.

Further, each of the sub-processors20_1to20—nincludes a command reception controller21which receives the process command CMD from the execution control circuit30athrough the control bus B2, and a status notification controller22which transmits the process status STS to the execution control circuit30athrough the status bus B3. In other words, the command reception controller21is connected as a slave (reception side) of the control bus B2, and has a function of transmitting the acquired process command CMD inside the sub-processor. Further, the status notification controller22is connected as a master (transmission side) of the status bus B3, and has a function of transferring the process status STS generated in the sub-processor to the execution control circuit30a.

Operation Example

Next, operation of this exemplary embodiment is described with reference toFIGS. 5 to 9.FIGS. 5 to 7and9show the operation equivalent respectively to the Step S2(hereinafter, process sequence setting operation), the Step S3(hereinafter, process command issuing operation), the Step S7(hereinafter, process status notifying operation), and the Step S13(hereinafter, process completion notifying operation) shown inFIG. 3. Further,FIG. 8shows a format example of the process status STS used in this exemplary embodiment.

[Example of Process Sequence Setting Operation]

As shown inFIG. 5, the main processor10firstly stores the process sequence SEQ in the data memory MEM1through the MP interface IF1and the MP bus B4in the execution control circuit30a(Step S21). Then, the main processor10writes a sequence start command CMD22in the command FIFO32(Step S22). At this time, an interruption signal generated by the command FIFO32is received at the control processor31. The control processor31, which has received the interruption signal, acquires the sequence start command CMD22from the command FIFO32(Step S23). Note that the process sequence SEQ may be preliminarily stored in the data memory MEM1upon initial activation or the like, as with the instruction codes in the command memory MEM2.

[Example of Process Command Issuing Operation]

After the above-mentioned process sequence setting operation, as shown inFIG. 6, the control processor31firstly reads the process sequence SEQ from the data memory MEM1(Step S31).

Then, the control processor31executes the instruction codes INS read from the command memory MEM2and analyzes a linkage relationship between processes and data defined in the process sequence SEQ, thereby determine a process command to be issued next time. Further, the control processor31recognizes which process has been executed and which sub-processor is in operation based on the acquired process status STS, and determines an issuing destination of the process command. Specifically, if input data required for the process to be executed next time is completed, a writing destination of output data is available, and a sub-processor (operation resource) which can execute this process is not in operation, the control processor31determines this sub-processor as the issuing destination of the process command.

Assuming that the process command CMD1shown inFIG. 3is determined as the process command to be issued next time, and that the sub-processor20_1is determined as an issuing destination of the process command CMD1. The control processor31outputs the process command CMD1to the control bus control circuit41in the arbiter circuit40sequentially through the bus switch SW, the CP bus B5, the B2interface IF2, and the control bus B2. The control bus control circuit41performs address decoding for access from the execution control circuit30ato the control bus, and transfers the process command CMD1to the sub-processor20_1selected as a result of the address decoding. The command reception controller21in the sub-processor20_1transmits necessary parameters such as a process ID (instruction number) set in the process command CMD1inside the sub-processor20_1, so that a process in accordance with the process ID is executed (Step S32).

Note that in a case of processes where input data is continuously generated, the control processor31can also make the sub-processors20_1to20—nexecute a series of processes in a pipelined parallel manner.

[Example of Process Status Notifying Operation]

After the above-mentioned process command issuing operation, as shown inFIG. 7, the status notification controller22in the sub-processor20_1outputs the process status STS1shown inFIG. 3to the status bus B3. The status bus arbiter circuit42transfers the process status STS1to the execution control circuit30a. When access from another sub-processor to the status bus conflicts, the status bus arbiter circuit42performs access arbitration in a round-robin fashion or the like, and transfers the process status from the sub-processor selected as a result of the access arbitration to the execution control circuit30a. The B3interface IF3in the execution control circuit30astores the process status STS1in the status FIFO33(Step S71).

At this time, an interruption signal generated by the status FIFO33is received at the control processor31. The control processor, which has received the interruption signal, acquires the process status STS1from the status FIFO33(Step S72).

FIG. 8shows a format example of the process status STS. In this example, the process status STS is composed of 32 bits. The first 8 bits from MSB (Most Significant Bit) are allocated as a setting area for a sub-processor ID. The subsequent 8 bits are allocated as a setting area for the process ID. The last 16 bits are allocated as a setting area for a status value (which indicates completion of reading the input data, completion of writing the output data, completion of the process, or the like). Each of the sub-processors20_1to20—noutputs the process ID and the status value respectively as an address signal [7:0] of the status bus B3and a data signal [15:0] to the status bus arbiter circuit42. The status bus arbiter circuit42adds the sub-processor ID as upper bits [15:8] in a transferring address signal to the process ID and the status value to be transferred to the execution control circuit30a. Further, the B3interface IF3stores the sub-processor ID, the process ID and the status value as one process status STS in the status FIFO33.

Therefore, the control processor31has only to read the process status STS from the status FIFO33to be able to recognize which process executed by which sub-processor is in which status.

[Example of Process Completion Notifying Operation]

When completion of the process sequence SEQ (completion of all processes) is recognized by the above-mentioned process status notifying operation, as shown inFIG. 9, the control processor31stores interruption factor data DI which indicates completion of the sequence (process completion notification NTF shown inFIG. 3) in the interruption FIFO34(Step S131). At this time, an interruption signal SI generated by the interruption FIFO34is received at the interruption controller60through the interruption interface IF2. The generation of the interruption is transmitted from the interruption controller60to the main processor10(Step S132). Then, the main processor10acquires the interruption factor data DI from the interruption FIFO34through the MP interface IF1and the MP bus B4, thereby recognizing the completion of the sequence (Step S133).

Next, a first example of the application of the multi-processor system1aaccording to this exemplary embodiment to a data processing system, and a second example of the application thereof to a codec system will be respectively described with reference toFIGS. 10 and 11.

[First Example of Application]

As shown inFIG. 10, a data processing system2includes the same main processor10, execution control circuit30a, arbiter circuit40and interruption controller60as those of the multi-processor system1a. Further, a memory controller70which controls access to an external memory (not shown) is connected to the system bus B1. Furthermore, a data transmitting function block23_1which transmits data Dout outside the system, a data receiving function block23_2which receives data Din from outside the system, a timing function block23_3which generates from the received data Din a timing signal TS to be output to the function blocks23_1and23_2, and a data processing function block23_4which performs a predetermined process for the received data Din output from the function block23_2, and stores the processed data Df in the external memory through the memory controller70are used as sub-processors. Each of the function blocks23_1to23_4includes the above-described command reception controller21and status notification controller22. Note that as shown as alternate long and short dash lines inFIG. 10, it may be possible to perform access from the system bus B1to the control bus control circuit41. In this case, it is also possible for the main processor10to directly control the function blocks23_1to23_4.

In operation of receiving the data, the main processor10outputs a process sequence for receiving and a start command thereof to the execution control circuit30a. Then, the execution control circuit30aanalyzes the process sequence for receiving, and issues a process command to start generation of the timing signal TS to the timing function block23_3. When a process status which indicates completion of a process to start the generation of the timing signal TS is received from the timing function block23_3, the execution control circuit30aissues a process command to start reception of the data Din to the data receiving function block23_2. When a process status which indicates completion of a process to start the reception is received from the data receiving function block23_2, the execution control circuit30aissues a process command to write the processed data Df in the external memory to the data processing function block23_4. When a process status which indicates completion of a process to write the processed data Df is received from the data processing function block23_4, the execution control circuit30anotifies the main processor10of an interruption which indicates completion of receiving process.

At this time, the data processing function block23_4issues a process status indicating completion of acquisition at timing when the received data Din is acquired from the data receiving function block23_2. Thus, the execution control circuit30acan issue to the data receiving function block23_2a process command to output the received data Din to the data processing function block23_4in synchronization with the next timing signal TS. Therefore, it is not necessary for the data receiving function block23_2to check the operating status of the data processing function block23_4. Accordingly, the data processing system2can concurrently execute the process to receive the data Din, and the process to write the processed data Df in the external memory. As a result, the function blocks operate in a pipelined parallel manner.

On the other hand, in operation of transmitting the data, the execution control circuit30areceives the completion of the process to start the generation of the timing signal TS from the timing function block23_3and completion of writing the transmitted data Dout in the external memory from the main processor10, and then issues a process command to transmit the transmitted data Dout outside the system to the data transmitting function block23_1. At this time, the data transmitting function block23_1issues a process status indicating completion of acquisition at timing when the transmitted data Dout is acquired from the external memory. Thus, the execution control circuit30acan notify the main processor10of an interruption which indicates that the next transmitted data Dout can be written in the external memory. Therefore, it is not necessary for the main processor10to check the operating status of the data transmitting function block23_1. Accordingly, the data processing system2can concurrently execute the process to transmit the data Dout, and a process to write the next transmitted data Dout in the external memory. As a result, the function blocks operate in a pipelined parallel manner.

Further, it is not necessary at all to change the circuit configuration of the execution control circuit30a, even in a case of adding a data processing function block23_5as shown as dotted lines inFIG. 10, in a case of adding a data transmitting function block23_6, or in a case of expanding the function of the data transmitting function block23_1.

Second Example of Application

As shown inFIG. 11, a codec system3uses as the sub-processors, in place of the function blocks23_1to23_6shown in the first example of the application described above, a transceiving function block24_1which transmits a data signal Dout outside the system and receives a data signal Din from outside the system, decode function blocks24_2to24_4each of which performs a decoding process for the received data Din to obtain decoded data Dd, and encode function blocks24_5and24_6each of which performs an encoding process for processed data Df output from the main processor10to obtain encoded data De. Each of the function blocks24_1to24_6includes the above-described command reception controller21and status notification controller22. Further, the received data Din, the decoded data Dd, the processed data Df and the encoded data De are exchanged through a shared memory50of multi-banked type. Therefore, the function blocks24_1to24_6can access different banks in parallel. Further, each data is exchanged through the shared memory50. Therefore, it is not necessary to conduct direct communication between the function blocks. Furthermore, the main processor10preliminarily writes parameters required for processing in the shared memory50, whereby each function block autonomously acquires the parameters from the shared memory50upon receiving a process command to start from the execution control circuit30a. Therefore, the execution control circuit30ahas only to issue a process command which includes the process ID and an address (pointer) of the stored parameter on the shared memory50, and can control the function blocks in common. Note that as shown as alternate long and short dash lines inFIG. 11, it may be possible to perform access from the system bus B1to the control bus control circuit41. In this case, it is also possible for the main processor10to directly control the function blocks24_1to24_6.

In operation of encoding the data, the main processor10outputs a process sequence for encoding and a start command thereof to the execution control circuit30a. Then, the execution control circuit30aanalyzes the process sequence for encoding, and issues a process command to request the encoding process for the processed data Df to the encode function block24_5upon receiving from the main processor10completion of writing the processed data Df in the shared memory50. When a process status which indicates completion of the encoding process is received from the encode function block24_5, the execution control circuit30aissues a process command to request the encoding process for the processed data Df to the encode function block24_6. When a process status which indicates completion of the encoding process is received from the encode function block24_6, the execution control circuit30aissues a process command to transmit the encoded data De outside the system to the transceiving function block24_1.

At this time, the encode function block24_5issues a process status indicating completion of acquisition at timing when the processed data Df from the main processor10is acquired from the shared memory50. Thus, the execution control circuit30acan notify the main processor10of an interruption which indicates that processed data Df for the next frame can be written in the shared memory50. Therefore, the main processor10can execute a process to write the processed data Df in the shared memory50in parallel with the encoding process by the encode function block24_5. As a result, the function blocks operate in a pipelined parallel manner.

On the other hand, in operation of decoding the data, the main processor10outputs a process sequence for decoding and a start command thereof to the execution control circuit30a. Then, the execution control circuit30aanalyzes the process sequence for decoding, and issues a process command to request the decoding process for the received data Din to the decode function block24_2upon receiving from the transceiving function block24_1process statuses which are constantly and periodically generated and each of which indicates completion of writing the received data Din in the shared memory50. When a process status indicating completion of the decoding process is received from the decode function block24_2, the execution control circuit30aissues a process command to request the decoding process for the received data Din to the decode function block24_3. When a process status indicating completion of the decoding process is received from the decode function block24_3, the execution control circuit30aissues a process command to request the decoding process for the received data Din to the decode function block24_4. When a process status indicating completion of the decoding process is received from the decode function block24_4, the execution control circuit30anotifies the main processor10of an interruption which indicates that the decoded data Dd can be read from the shared memory.

At this time, the decode function block24_3issues a process status indicating completion of acquisition at timing when the received data Din is acquired from the shared memory50. Thus, the execution control circuit30acan issue a process command to read received data Din for the next frame from the shared memory50to the decode function block24_2. Therefore, it is not necessary for the decode function block24_2to check the operating status of the decode function block24_3. Accordingly, it is possible to concurrently execute the decoding process and a process to read the received data Din. As a result, the function blocks operate in a pipelined parallel manner.

Further, as each of the encode function blocks24_2to24_4, and the encode function blocks24_5and24_6, the one which is compatible with a plurality of decoding schemes may be used. In this case, each of the decode function blocks and the encode function blocks selects one decoding scheme in accordance with the process command (process ID) received from the execution circuit30a. Process sequences corresponding to the respective decoding schemes are set in the execution control circuit30a. In a case of changing the whole system from a certain decoding scheme to a different decoding scheme, the main processor10sets a process sequence for the different decoding scheme in the execution control circuit30a, so that it is possible to easily switch the decoding scheme. Further, as described above, the status FIFO33stores the process ID and the status value in pairs. Therefore, the status FIFO33can be shared in the respective decoding schemes.

In this way, the multi-processor system according to this exemplary embodiment can be applied to various systems. Further, there is an advantage of simplifying reconfiguration and reuse of the system. Note that the above-mentioned data processing system2and codec system3may be configured by using one of multi-processor systems according to the second to fifth exemplary embodiments which will be described later.

Next, the second exemplary embodiment is described with reference toFIGS. 12 to 14,15A and15B, and16.

Second Exemplary Embodiment

Configuration Example

As shown inFIG. 12, a multi-processor system1baccording to this exemplary embodiment is different from the above-mentioned first exemplary embodiment, in that it includes an execution control circuit30bas substitute for the execution control circuit30ain the multi-processor system1ashown inFIG. 4. Note that although the illustration is omitted, the multi-processor system1bincludes “n” units of sub-processors20_1to20—nand the arbiter circuit40which arbitrates transfer of the process command CMD and the process status STS between the sub-processors and the execution control circuit30b, as with the multi-processor system1a.

The execution control circuit30bincludes a FIFO memory MEM3, a FIFO memory controller35, a command FIFO manager36, a status FIFO manager37, an interruption FIFO manager38and a control register REG, as substitute for the command FIFO32, the status FIFO33and the interruption FIFO34shown inFIG. 4. On the address space in the FIFO memory MEM3, there are formed a command FIFO area, a status FIFO area and an interruption FIFO area which are equivalent respectively to the command FIFO32, the status FIFO33and the interruption FIFO34. The FIFO memory controller35controls access to the FIFO memory MEM3. The command FIFO manager36holds management information regarding the command FIFO area. The status FIFO manager37holds management information regarding the status FIFO area. The interruption FIFO manager38holds management information regarding the interruption FIFO area. The control register REG holds control information regarding the command FIFO area, the status FIFO area, the interruption FIFO area and the FIFO memory MEM3.

Further, the FIFO memory controller35, the command FIFO manager36, the status FIFO manager37, the interruption FIFO manager38and the control register REG are each connected to the MP bus B4and the CP bus B5. The process status STS from the status bus B3is input to the FIFO memory controller35through the B3interface IF3. Further, the control register REG outputs an interruption signal generated by the interruption FIFO manager38to the interruption controller60through the interruption interface IF4, and outputs interruption signals generated by the command FIFO manager36and the status FIFO manager37to the control processor31.

Specifically, as shown inFIG. 13, each of the FIFO managers36to38includes a management register101, a mask register102, a clear register103and a mask circuit104. The management register101includes a write pointer WP for managing a write address to each FIFO area, a read pointer RP for managing a read address from each FIFO area, stored data number NUM holding the number of data stored in each FIFO area, and a status flag FLG indicating whether each FIFO area is in Full status or Empty status. The mask register102holds binary data which indicates whether or not to output an interruption signal SI generated by the management register101to the control register REG (whether or not to mask the interruption) when write access to each FIFO area occurs. The clear register103holds binary data which indicates whether or not to clear the information in the management register101. The mask circuit104masks the interruption signal SI in accordance with the output value from the mask register102.

The status flag FLG is used for representing and observing the status of the FIFO area. The status flag FLG is composed of two bits of Empty flag and Full flag for example. The Empty flag is set to “1” when the FIFO area is in the Empty status. The Full flag is set to “1” when the FIFO area is in the Full status. The Full flag is reset to “0” by reading the data from the FIFO area. Further, the information in the management register101is initialized to zero by writing “1” in the clear register103. Furthermore, the mask register102is used for masking output of an interruption signal which is generated at a time when the data is written in the FIFO area. If the value of the mask register102is set to “1” (masked status), the interruption signal is not output even when the data is written in the FIFO area. Meanwhile, if there is data in the FIFO area at timing when the mask is canceled (at timing when the value of the mask register102is changed from “1” to “0”), the interruption signal is output. Thus, it is possible to prevent the data in the FIFO from being lost, and to prevent the interruption signal from being unnecessarily generated.

Further, the control register REG stores therein a base address BA of each FIFO area allocated on the FIFO memory MEM3, the number DEP of stages of data which can be stored in each FIFO area, and a data bit width WID of the data stored in each FIFO area (in other words, the above-described sequence start command CMD22, process status STS and interruption factor data DI). The stage number DEP and the data bit width WID are output to each of the FIFO managers36to38.

The above-mentioned write pointer WP is incremented by the number corresponding to the data bit width WID (the number of byte units), every time a write enable signal WE becomes active. For example, in a case where the data bit width WID equals to “16 bits”, the write pointer WP is incremented by two every time the data is written in the FIFO area. In a case where the data bit width WID equals to “32 bits”, the write pointer WP is incremented by four. Meanwhile, the write pointer WP is initialized to zero when its value reaches the one equivalent to the stage number DEP, and then the above-mentioned increment is performed again. The read pointer RP is incremented as with the write pointer WP, every time a read enable signal RE becomes active. The stored data number NUM is used for representing and observing the number of data stored in the FIFO area. The stored data number NUM is calculated based on a difference between the value of the write pointer WP and the value of the read pointer RP. In other words, the data number NUM increases by one when the data is written in the FIFO area. The data number NUM decreases by one when the data is read from the FIFO area.

Furthermore, the FIFO memory controller35includes a control interface201, address/data converter circuits202_1to202_3, and an arbiter circuit203. The control interface201outputs the write enable signal WE and the read enable signal RE for each FIFO area to the management register101, and receives the write pointer WP, the read pointer RP, the base address BA and the data bit width WID from the management register101. The address/data converter circuits202_1to202_3are respectively connected to the status bus B3, the MP bus B4and the CP bus B5, and perform conversion processes for the address based on the write pointer WP, the read pointer RP, the base address BA and the data bit width WID output from the control interface201. Further, the address/data converter circuits202_1to202_3perform conversion processes for data to be transferred to data buses or for data acquired from the data buses, based on a difference between the data bit width WID and a data bit width of the FIFO memory MEM3(in other words, width of parallel data buses connected to the MEM3). The arbiter circuit203arbitrates access from the address/data converter circuits202_1to202_3to the data buses.

Operation Example

Next, operation of this exemplary embodiment is described with reference toFIGS. 14,15A and15B, and16. Note that operation which does not relate to access to the FIFO area in the execution control circuit30bis similar to that of the multi-processor system1ashown inFIG. 4, and thus the description will be omitted.

FIG. 14shows an example of a process to convert the address and a process to arbitrate access to the data buses which are executed by the FIFO memory controller35.

Firstly, the interruption FIFO area AR_I, the command FIFO area AR_C and the status FIFO area AR_S are formed on the address space in the FIFO memory MEM3. The base address and area length of the interruption FIFO area AR_I are set respectively to BA_I and “stage number DEP_I*data bit width WID_I”. Similarly, the base address and area length of the command FIFO area AR_C are set respectively to BA_C and “stage number DEP_C*data bit width WID_C”. The base address and area length of the status FIFO area AR_S are set respectively to BA_S and “stage number DEP_S*data bit width WID_S”. Note that it is possible to vary the area length of each FIFO area by changing the setting values of the base address BA and the stage number DEP.

As shown inFIG. 14, when write access for the interruption factor data DI is generated by the control processor31(Step S1311), the address/data converter circuit202_3in the FIFO memory controller35adds a value of a write pointer WP_I of the interruption FIFO area AR_I received from the control interface201to the base address BA_I to generate a write address WA on the FIFO memory MEM3(Step S1312). At this time, if access from the address/data converter circuit202_3to the data buses conflicts with access from at least one of the status bus B3and the main processor10to the data buses, the arbiter circuit203performs access arbitration (Step S2000). Specifically, the arbiter circuit203performs the access arbitration in “round-robin fashion”, “priority fashion in order of main processor10>control processor31>status bus B3” or the like.

Further, when read access for the sequence start command CMD22is generated by the control processor31(Step S231), the address/data converter circuit202_3adds a value of a read pointer RP_C of the command FIFO area AR_C to the base address BA_C to generate a read address RA on the FIFO memory MEMS (Step S232). Similarly, when read access for the process status STS is generated by the control processor31(Step S721), the address/data converter circuit202_3adds a value of a read pointer RP_S of the status FIFO area AR_S to the base address BA_S to generate the read address RA (Step S722).

On the other hand, when write access for the process status STS from the status bus B3is generated (Step S711), the address/data converter circuit202_1in the FIFO memory controller35adds a value of a write pointer WP_S of the status FIFO area AR_S to the base address BA_S to generate the write address WA (Step S712). Note that the process status STS is written in the status FIFO area AR_S, as it is in the format as shown inFIG. 8.

Further, when read access for the interruption factor data DI is generated by the main processor10(Step S1331), the address/data converter circuit202_2in the FIFO memory controller35adds a value of a read pointer RP_I of the interruption FIFO area AR_I to the base address BA_I to generate the read address RA (Step S1332). Similarly, when write access for the sequence start command CMD22is generated (Step S221), the address/data converter circuit202_2adds a value of a write pointer WP_C of the command FIFO area AR_C to the base address BA_C to generate the write address WA (Step S222).

The arbiter circuit203also performs the access arbitration, when the write address WA or the read address RA is generated at any one of the above-mentioned Steps S232, S722, S712, S1332and S222.

Note that although the illustration is omitted, the control processor31can also perform random access as with the normal memory access by directly designating the address value of the FIFO memory MEM3, for the sake of e.g. testing the memory.

Further, the FIFO memory controller35performs processes to convert the data shown inFIGS. 15A and 15B. For example, as shown inFIG. 15A, in a case where the data bit width WID_I of the interruption factor data DI equals to “8 bits”, the data bus width equals to “32 bits”, and write to the write address WA=“0x040A” is performed, the address/data converter circuit202_3in the FIFO memory controller35transfers the interruption factor data DI to the FIFO memory MEM3by using the data buses [23:16], thereby writing the interruption factor data DI in the 16th to 23rd bits in the area corresponding to the address “0x0408” on the FIFO memory MEM3.

On the other hand, in a case of reading the interruption factor data DI written by the above-mentioned process (that is, in a case of performing read from the read address RA=“0x040A”), the address/data converter circuit202_2reads 8 bits of interruption factor data DI [7:0] from the FIFO memory MEM3through the data buses [23:16].

Further, as shown inFIG. 15B, in a case where the data bit width WID_C of the process command CMD equals to “16 bits” and write to the write address WA=“0x050A” is performed, the address/data converter circuit202_2transfers the process command CMD to the FIFO memory MEM3by using the data buses [31:16], thereby writing the process command CMD in the 16th to 31st bits in the area corresponding to the address “0x0508” on the FIFO memory MEM3.

On the other hand, in a case of reading the process command CMD written by the above-mentioned process (that is, in a case of performing read from the read address RA=“0x050A”), the address/data converter circuit202_3reads 16 bits of process command CMD [15:0] from the FIFO memory MEM3through the data buses [31:16].

FIG. 16shows an example of address maps of the execution control circuit30b, which are viewed from the main processor10and the control processor31. For example, regarding each of the FIFO managers36to38, only access address AA of each of the management register101, the mask register102and the clear register103shown inFIG. 13is mapped. On the other hand, access addresses AA of FIFO areas (read access area for interruption factor data, write access area for command, write access area for interruption factor data, read access area for command, and read access area for status) are mapped on the address spaces of the FIFO memory controller35. That is, for example, the control processor31sequentially accesses the access address AA=“0x00 . . . 0308” of the read access area for status, thereby actually being able to sequentially read process statuses STS from continuous addresses within the status FIFO area AR_S shown inFIG. 14.

In this way, the interruption FIFO area AR_I, the command FIFO area AR_C and the status FIFO area AR_S are formed on one memory. Therefore, it is possible to vary the number of stages of data stored in the FIFO area and the data bit width, so that it is possible to further improve extensibility of the multi-processor system compared with the above-mentioned first exemplary embodiment. Namely, it is possible to flexibly respond to the number or the format of process statuses, process commands or interruption factors being changed by specification change after the development of LSI or the like.

Next, the third exemplary embodiment is described with reference toFIGS. 17 to 19.

Third Exemplary Embodiment

Configuration Example

As shown inFIG. 17, a multi-processor system1caccording to this exemplary embodiment is different from the above-mentioned second exemplary embodiment, in that an execution control circuit3cincludes a data memory controller39which controls access to the data memory MEM1, as substitute for the FIFO memory MEM3and the FIFO memory controller35in the execution control circuit30bshown inFIG. 12. That is, in this exemplary embodiment, the interruption FIFO area AR_I, the command FIFO area AR_C and the status FIFO area AR_S shown in the above-mentioned second exemplary embodiment are formed on the address space in the data memory MEM1. Further, the data memory controller39is connected to the MP bus B4and the CP bus B5. The process status STS from the status bus B3is input to the data memory controller39through the B3interface IF3.

Note that although the illustration is omitted, the multi-processor system1cincludes “n” units of sub-processors20_1to20—nand the arbiter circuit40which arbitrates transfer of the process command CMD and the process status STS between the sub-processors and the execution control circuit30c, as with the multi-processor system1ashown inFIG. 4.

Operation Example

Next, operation of this exemplary embodiment is described with reference toFIGS. 18 and 19. Note that operation which does not relate to access to the FIFO area in the execution control circuit30cis similar to that of the multi-processor system1ashown inFIG. 4, and thus the description will be omitted.

FIG. 18shows an example of a process to convert the address and a process to arbitrate access to the data buses which are executed by the data memory controller39. This example is different from the example of the process to convert the address and the process to arbitrate the access to the data buses shown inFIG. 14, in that the control processor31and the main processor10can execute respective processes at Steps S2100and S2200. In other words, when the FIFO areas AR_I, AR_C and AR_S are formed in the data memory MEM1, the control processor31and the main processor10can perform access to each FIFO area and random access to a data area AR_D by using a single data memory MEM1.

FIG. 19shows an example of address maps of the execution control circuit30c, which are viewed from the main processor10and the control processor31. These address maps are different from those of the execution control circuit30bshown inFIG. 16, in that the access addresses AA for the FIFO areas are allocated to the respective FIFO areas not one by one but by two or more, so as to include at least the top and end of each of the FIFO areas. That is, in this exemplary embodiment, each of the FIFO areas is mapped as an address space with a certain area width.

Accordingly, when any address is accessed within the mapped address space, it means access to the same FIFO (sequential access to data in the FIFO area). On the other hand, the main processor10and the control processor31can also perform incremental burst access (burst access to continuous data in the FIFO area) by using a plurality of access addresses. In this case, it is possible to speed up the access processing for the FIFO.

Next, the fourth exemplary embodiment is described with reference toFIG. 20.

Fourth Exemplary Embodiment

As shown inFIG. 20, a multi-processor system1daccording to this exemplary embodiment includes a bus monitor80which monitors and externally outputs the process command CMD and the process status STS passing respectively through the control bus control circuit41and the status bus arbiter circuit42in the arbiter circuit40, in addition to the configuration of the multi-processor system1ashown inFIG. 4. Note that the bus monitor80may be provided in the multi-processor systems1band1crespectively shown inFIGS. 12 and 17. The following description can be applied also to this case. Further, in a case of conducting communication between sub-processors by use of a shared memory as the above-mentioned second example of the application, observation of the communication may be performed by connecting the bus monitor80to a bus for the shared memory.

In operation, the bus monitor80monitors and externally outputs commands from the execution control circuit30ato the sub-processors20_1to20—n, which request the start of processing and the like, and the process completion notification, an error notification and the like from the sub-processors20_1to20—nto the execution control circuit30a. Therefore, it is possible to observe almost all operating statuses regarding the process execution by each sub-processor. The reason why high observability (debuggability) can be assured in this way is because all communication between the execution control circuit30aand the sub-processors20_1to20—nis conducted through the shared bus without using exclusive lines or buses for the transfer of the process status STS.

Next, the fifth exemplary embodiment is described with reference toFIG. 21.

Fifth Exemplary Embodiment

As shown inFIG. 21, a multi-processor system1eaccording to this exemplary embodiment includes two units of execution control circuits30_1and30_2. Further, the arbiter circuit40includes a control bus arbiter circuit43which arbitrates access from the execution control circuits30_1and30_2to the control bus B2upon transfer of the process command CMD, as substitute for the control bus control circuit41shown in e.g.FIG. 4. Note that the arbiter circuit may be provided for each execution control circuit. Three or more execution control circuits may be provided. Further, a plurality of main processors may be provided. Furthermore, as each of the execution control circuits30_1and30_2, any one of the execution control circuit30ashown inFIG. 4, the execution control circuit30bshown inFIG. 12and the execution control circuit30cshown inFIG. 17may be used.

In operation, the main processor10sets mutually different process sequences in the execution control circuits30_1and30_2, thereby making the execution control circuits30_1and30_2perform the execution control in parallel. Further, when access from the execution control circuits30_1and30_2to the control bus B2conflicts, the control bus arbiter circuit43performs address decoding after performing access arbitration in round-robin fashion or the like, and transfers a process command from the selected execution control circuit to the sub-processor. Similarly, the status bus arbiter circuit42performs the access arbitration in the case where access from the sub-processors20_1to20—nto the status bus B3conflicts.

Thus, it is possible to enhance further load distribution as a whole system. Further, since processing load of the whole system is reduced, it is also possible to increase the number of sub-processors. Furthermore, processing load associated with the execution control can be reduced by implementing a plurality of execution control circuits, even when the number of sub-processors rapidly increases with the growing scale of the system. Therefore, it is possible to prevent the processing in the whole system from collapsing. Note that even in a case of adding the execution control circuit, it is not necessary for the circuit configuration thereof to be changed.

Note that the present invention is not limited to the above-mentioned exemplary embodiments, and it is obvious that various modifications can be made by those of ordinary skill in the art based on the recitation of the claims.

This application is based upon and claims the benefit of priority from Japanese patent application No. 2008-203768, filed on Aug. 7, 2008, the disclosure of which is incorporated herein in its entirety by reference.

INDUSTRIAL APPLICABILITY

The present invention is applicable to a multi-processor system and a controlling method thereof, and particularly to a multi-processor system which controls a plurality of sub-processors in parallel and a controlling method thereof.

REFERENCE SIGNS LIST