Controller, memory system and data processing system

A memory system includes: a first memory subsystem suitable for storing a first segment of map data for first logical addresses in a logical address region; a second memory subsystem suitable for storing a second segment of map data for second logical addresses in the logical address region; and a host interface suitable for: providing any one of the first and second memory subsystems with a first read command of a host according to a logical address included in the read command, providing the host with an activation recommendation according to a read count of the logical address region including the provided logical address, providing map data for the first and second logical addresses obtained from the first and second memory subsystems, wherein the activation recommendation allows the host to further provide a physical address corresponding to a target logical address in the logical address region.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2020-0103345, filed on Aug. 18, 2020, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Various embodiments of the present disclosure generally relate to a controller for controlling a memory device, and a memory system including the controller.

2. Description of the Related Art

The computer environment paradigm has been transitioning to ubiquitous computing, which enables computing systems to be used anytime and anywhere. As a result, use of portable electronic devices such as mobile phones, digital cameras, and laptop computers has rapidly increased. These portable electronic devices generally use a memory system having one or more memory devices for storing data. A memory system may be used as a main memory device or an auxiliary memory device of a portable electronic device.

Since they have no moving parts, memory systems provide advantages such as excellent stability and durability, high information access speed, and low power consumption. Examples of memory systems having such advantages include universal serial bus (USS) memory devices, memory cards having various interfaces, and solid state drives (SSD).

SUMMARY

Various embodiments of the present disclosure are directed to a method and apparatus that enables providing a memory system with a request including a physical address of data to be read by a host, by providing, in a timely manner, the host with map data expected to be frequently referred to by the memory system.

In accordance with an embodiment, a memory system includes: a first memory subsystem suitable for storing a first segment of map data for first logical addresses in a logical address region; a second memory subsystem suitable for storing a second segment of map data for second logical addresses in the logical address region; and a host interface suitable for: providing any one of the first and second memory subsystems with a first read command of a host according to a logical address included in the read command, providing the host with an activation recommendation according to a read count of the logical address region including the logical address, obtaining the first and second segments of map data for the first and second logical addresses from the first and second memory subsystems, respectively, based on a read buffer command of the host, and providing the host with the first and second segments of map data combined as map data for the logical address region, wherein the activation recommendation allows the host to further provide, when providing a second read command including a target logical address in the logical address region, a physical address corresponding to the target logical address.

In accordance with an embodiment, a controller that controls first and second memory devices, includes: a first processor suitable for controlling the first memory device to store a first segment of map data for first logical addresses in a logical address region; a second processor suitable for controlling the second memory device to store a second segment of map data for second logical addresses in the logical address region; and a host interface suitable for: providing any one of the first and second processors with a read command of a host according to a logical address in the read command, providing the host with an activation recommendation according to a read count of the logical address region including the provided logical address, obtaining the first and second segments of map data for the first and second logical addresses from the first and second processors based on a read buffer command of the host, and providing the host with the first and second segments of map data combined as map data for the logical address region, wherein the activation recommendation allows the host to further provide, when providing a second read command including a target logical address in the logical address region, a physical address corresponding to the target logical address.

In accordance with an embodiment, a data processing system includes: a host configured to provide a first request together with a first logical address or a second logical address selected from a host map segment; first and second memory systems configured to store first and second map sub-segments having the first and second logical addresses, respectively, each of the first and second memory systems configured to perform an operation in response to the first request by referring to the provided logical address and the corresponding map sub-segment included therein; and a host interface configured to cause the host to update the host map segment with both of the first and second map sub-segments when a number of accesses to the first and second map sub-segments is greater than a threshold, wherein the first and second map sub-segments respectively have first and second map entries each having a logical address and a corresponding physical address, wherein the host is further configured to provide a second request together with the first map entry or the second map entry selected from the updated host map segment, and wherein each of the first and second memory systems is further configured to perform an operation in response to the second request by referring to the provided map entries corresponding thereto.

The features and advantages obtainable in the present disclosure are not limited to those described herein; those skilled in the art will recognize other features and advantages from the following detailed description.

DETAILED DESCRIPTION

Hereinafter, various embodiments of the present disclosure are described below in detail with reference to the accompanying drawings. The following description focuses on subject matter pertinent to the present disclosure; well-known technical detail may be omitted so as not obscure the subject matter of the disclosed embodiments. Throughout the specification, reference to “an embodiment,” “another embodiment” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s). The term “embodiments” when used herein does not necessarily refer to all embodiments.

FIG. 1is a diagram illustrating a method of sharing map data in accordance with an embodiment.

Referring toFIG. 1, a host102and a memory system110may operably engage to cooperate with each other. The host102may be a computing device and implemented in the form of a mobile device, a computer and/or a server. The memory system110may receive a command from the host102and store or output data in response to the received command.

The host102may include any of various portable electronic devices such as a mobile phone, MP3 player and laptop computer, or any of various non-portable electronic devices such as a desktop computer, a game machine, a television (TV), and a projector.

The host102may include at least one operating system (OS), which may manage and control overall function and operation of the host102, and provide operation between the host102and a user using the data processing system100or the memory system110. The OS may support functions and operations corresponding to the use purpose and usage of a user. The OS may be divided into a general OS and a mobile OS, depending on the mobility of the host102. The general OS may be divided into a personal OS and an enterprise OS, depending on the environment of a user.

The memory system110may operate to store data for the host102in response to a request of the host102. Non-limiting examples of the memory system110include a solid state drive (SSD), a mufti-media card (MMC), a secure digital (SD) card, a universal serial bus (USB) device, a universal flash storage (UFS) device, compact flash (CF) card, a smart media card (SMC), a personal computer memory card international association (PCMCIA) card and memory stick. The MMC may include an embedded MMC (eMMC), reduced size MMC (RS-MMC) and/or micro-MMC. The SD card may include a mini-SD card and micro-SD card.

The memory system110may be embodied by any of various types of storage devices. Examples of such storage devices include, but are not limited to, volatile memory devices such as a dynamic random access memory (DRAM) and a static RAM (SRAM) and nonvolatile memory devices such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase-change RAM (PRAM), a magneto-resistive RAM (MRAM), resistive RAM (RRAM or ReRAM) and a flash memory. The flash memory may have a 3-dimensional (3D) stack structure.

The memory system110may have a storage space including nonvolatile memory cells.

In order to store data requested by the host102in the storage space, the memory system110may perform mapping of a file system used by the host102to the storage space. For example, an address associated with data according to the file system may be referred to as a logical address and an address associated with data in the storage space may be referred to as a physical address.

The memory system110may include a plurality of subsystems that can operate in parallel in order to improve data processing performance. In an example ofFIG. 1, the memory system110may include a first memory subsystem112, a second memory subsystem114and a host interface132.

Each of the first and second memory subsystems112and114may store data used by the host102, and include non-volatile memory cells.

The host interface132may support interfacing between the host102and the first and second memory subsystems112and114.

The host I/F132may be configured to process a command and data of the host102, and may communicate with the host102through one or more of various interface protocols such as universal serial bus (USB), multi-media card (MMC), peripheral component interconnect-express (PCI-e or PCIe), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (DATA), enhanced small disk interface (ESDI) and integrated drive electronics (IDE).

The host interface132may drive firmware which is referred to as a host interface layer. According to an embodiment, the host interface132may be implemented as any one of CPU, TPU and a hardware accelerator.

The host interface132may distribute commands to the first and second memory subsystems112and114based on logical addresses included in the commands received from the host102. For example, the host interface132may provide the first memory subsystem112with a command including an odd-numbered logical address, and provide the second memory subsystem114with a command including an even-numbered logical address.

In other words, the first and second memory subsystems112and114may access different storage spaces based on different logical addresses, respectively. Accordingly, the first and second memory subsystems112and114may store map data for different logical addresses in internal storage spaces, respectively. Hereinafter, the map data stored by the first memory subsystem112is referred to as first sub map data, and the map data stored by the second memory subsystem114is referred to as second sub map data.

When receiving a read command including a logical address from the host102through the host interface132, the first and second memory subsystems112and114may search for a physical address, which corresponds to the logical address, based on the first and second sub map data stored therein, and then output data, which is stored at the physical address found in the search, to the host102through the host interface132.

If the host102performs the physical address search instead of the memory system110, the time it takes for the memory system110to output data corresponding to the read request provided by the host102may be reduced. In this situation, the host102may store map data that the host102may directly access to search for a physical address and provide the physical address found in the search to the memory system110.

Referring toFIG. 1, the memory system110may provide the map data to the host102.

When the memory system110provides the host102with all the map data stored therein, the host102may have difficulty in assigning a storage space in a memory within the host102to store all the map data received from the memory system110. Accordingly, instead of providing the host102with all map data, the memory system110may selectively provide the host102with some map data.

When map data for a logical address to be read is stored in the host102, the host102may provide the memory system110with a physical address obtained by referring to the map data. On the other hand, when the map data for the logical address to be read is not stored in the host102, the host102may provide the memory system110with the logical address, and the memory system110may access an internal storage space with reference to internal map data.

Since the host102can directly search map data stored therein for a physical address corresponding to a logical address, the access performance of the memory system110may be improved when the probability that the map data for the logical address to be read by the host102has been stored in the host102is high. Accordingly, the memory system110may provide the host102with map data including a logical address, which is expected to be frequently read by the host102, among internal map data so as to improve the read operation performance.

Since the host102may directly perform a physical address search for the logical address in the host map data, the higher the probability that a logical address to be read by the host102is included in the host map data, the better the access performance of the memory system110. Accordingly, in order to improve read operation performance, the map manager136may recommend map data, which includes a logical address expected to be frequently read by the host102among the memory map data, to the host102. The memory system110may provide the host102with the map data in response to a request of the host102.

Depending on the spatial locality and temporal locality of a memory, a recently and frequently accessed logical address and adjacent logical addresses may be frequently accessed in the future. Accordingly, based on the read tendency of the host102for each logical address region, the memory system110may expect one or more logical addresses to be frequently read. For example, the expectation that a particular logical address may be frequently read may be based on a read count for each logical address region. The memory system110may provide the host102with map data corresponding to a logical address region whose read count exceeds a threshold.

When the memory system110includes the plurality of memory subsystems112and114, logical addresses included in each of logical address regions may be distributed to the plurality of memory subsystems112and114. That is, each of the memory subsystems112and114may receive only read commands for logical addresses of the corresponding logical address region, and store only map data associated with the corresponding logical address region. Accordingly, it is difficult for each of the memory subsystems112and114to perform a read count for each logical address region and to provide the host102with map data of a logical address region that expected to be frequently read by the host102.

According to an embodiment, when a read command is received from the host102, the host interface132may perform the read count for each logical address region, and select a logical address region, which is expected to be frequently read, according to a read count result. The host interface132may obtain first sub map data and second sub map data for the selected logical address region from the plurality of memory subsystems112and114, and provide the host102with the first and second sub map data as map data of the selected logical address region.

According to an embodiment, even though the map data of a single logical address region is divided and that map data are utilized in different memory subsystems, the host interface132may effectively predict the single logical address region to be frequently read by the host102, and provide the host102with all map data of the single logical address region. Accordingly, the host102may directly search physical addresses for a logical address that is frequently read by the host102, thereby improving the read operation performance of the memory system110.

FIG. 2is a diagram schematically illustrating operations of the host interface132and the host102in accordance with an embodiment.

In operation S202, the host interface132may determine the number of reads that have been performed for each logical address region based on a read command received from the host102to generate a read count for each logical address region, and determine whether or not a logical address region is to be activated according to a read count result. Herein, the activating of the logical address region by the host interface132refers to allowing the host102directly to search for a physical address of the logical address region by providing the host102with map data of the logical address region, and when the host102provides the memory system110with a read command, allowing the host102to provide the read command including the physical address.

In operation S204, the host interface132may provide the host102with an activation recommendation for the logical address region so that the host102activates the logical address region.

In operation S206, the host102may prepare to receive map data of the logical address region in response to the activation recommendation of the host interface132. For example, the host102may allocate an internal storage space for storing the map data.

In operation S208, the host102may provide the host interface132with a read buffer command to obtain the map data from the host interface132. The read buffer command may be for reading a buffer in the memory system110.

In operation S210, the host interface132may prepare the map data of the logical address region in response to the read buffer command. For example, the host interface132may receive first and second sub map data constituting the map data from the first and second memory subsystems112and114, respectively.

In operation S212, the host interface132may provide the host102with the prepared map data.

In operation S214, the host102may store the map data in the allocated internal storage space.

In operation S216, the host102may transfer, to the memory system110, the read command including a logical address LBA and a physical address PBA, by using the map data stored therein.

In operation S218, the memory system110may perform a requested operation, by using the physical address PBA included in the read command.

FIG. 3is a diagram illustrating a data processing system100including a memory system110in accordance with an embodiment.

The data processing system100may include a host102and the memory system110. The host102and the memory system110ofFIG. 3may correspond to the host102and the memory system110described above with reference toFIG. 1, respectively.

The memory system110may include first and second memory devices152and154and a controller130that controls the first and second memory devices152and154.

The memory controller130and the first and second memory device152and154may be integrated into a single semiconductor device. For example, the memory controller130and the first and second memory device152and154may be integrated as one semiconductor device to constitute a solid state drive (SSD). When the memory system110is used as an SSD, the operating speed of the host102connected to the memory system110can be improved. In another embodiment, the memory controller130and the first and second memory device152and154may be integrated as one semiconductor device to constitute a memory card, such as a personal computer memory card international association (PCMCIA) card, compact flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC) including reduced size MMC (RS-MMC) and micro-MMC, secure digital (SD) card including mini-SD card, micro-SD card and SDHC card, or universal flash storage (UFS) device.

Each of the first and second memory devices152and154may be a nonvolatile memory device that retains data stored therein even though power is not supplied. Each of the first and second memory devices152and154may store data provided from the host102through a program operation, and provide data stored therein to the host102through a read operation. Each of the first and second memory devices152and154may include a plurality of memory blocks, each of which may include a plurality of pages, and each of the pages may include a plurality of memory cells coupled to a word line. In an embodiment, each of the first and second memory devices152and154may be a flash memory, The flash memory may have a 3-dimensional (3D) stack structure.

The memory controller130may control the first and second memory devices152and154in response to a request from the host102. For example, the memory controller130may provide data read from either or both of the first and second memory devices152and154to the host102, and store data provided from the host102in one or both of the first and second memory devices152and154. In general, the memory controller130may control read, program and erase operations of the first and second memory devices152and154.

The controller130may include a host interface132, a host interface memory232, first and second FCPU (FTL CPU)s134and136, first and second memory interfaces142and144and first and second sub buffers234and236.

The first memory subsystem112described with reference toFIG. 1may include the first FCPU134, the first memory interface (I/F)142, the first sub buffer234and the first memory device152, The second memory subsystem114described with reference toFIG. 1may include the second FCPU136, the second memory interface (I/F)144, the second sub buffer236and the second memory device154.

The host interface132corresponds to the host interface132described with reference toFIG. 1. The host interface132may distribute commands, which are inputted from the host102, to the first and second FCPUs134and136based on logical addresses included in the commands. For example, the host interface132may provide the first FCPU134with a command including a logical address having a first value as a result of a modulo operation, and provide the second FCPU136with a command including a logical address having a second value as the result of the modulo operation. The logical address having the first value as the result of the modulo operation may be an odd-numbered logical address, and the logical address having the second value as the result of the modulo operation may be an even-numbered logical address.

The host interface memory232may store data for driving the host interface132. The data that can be stored in the host interface memory232according to an embodiment is described below with reference toFIGS. 6A to 6C.

The first and second FCPUs134and136may control overall operations of the first and second memory subsystems112and114, respectively. Each of the first and second FCPUs134and136may be implemented as a CPU, and drive firmware, which is referred to as a flash translation layer (FTL), in order to control the general operations of the first and second memory subsystems112and114.

Each of the first and second FCPUs134and136may drive the FTL to perform a foreground operation corresponding to a command received from the host102. For example, the first FCPU134may control the first memory device152in response to a command including an odd-numbered logical address. In addition, the second FCPU136may control the second memory device154in response to a command including an even-numbered logical address.

Also, the first and second FCPUs134and136may perform a background operation on the first and second memory device152and154, respectively. The background operation may include a garbage collection (GC) operation, a wear-leveling (WL) operation, a map flush operation, or a bad block management operation.

The first and second memory interfaces142and144may serve as a memory/storage interface for interfacing the first and second FCPUs134and136and the first and second memory devices152and154, respectively. When each of the first and second memory devices152and154is a flash memory, specifically a NAND flash memory, the first and second memory interfaces142and144may generate a control signal for the first and second memory devices152and154and process data to be provided to the first and second memory devices152and154under the control of the first and second FCPUs134and136, respectively. The first and second memory interfaces142and144may work as an interface (e.g., a NAND flash interface) for processing a command and data between the first and second FCPUs134and136and the first and second memory device152and154, respectively. Specifically, the first memory I/F142may support data transfer between the first FCPU134and the first memory device152, and the second memory I/F144may support data transfer between the second FCPU136and the second memory device154.

Each of the first and second memory interfaces142and144may be driven through firmware referred to as a flash interface layer (FIL) in order to exchange data with its associated memory device152or154.

The first and second sub buffers234and236may store data for driving the first and second memory subsystems112and114, respectively. For example, the first and second sub buffers234and236may buffer the data until the data received through the host interface132are stored in the first and second memory devices152and154, respectively. Further, the first and second sub buffers234and236may buffer the data in order to transfer, to the host102, data outputted from the first and second memory devices152and154, respectively. In addition, the first and second sub buffers234and236may store first and second map data for converting logical addresses into physical addresses by the first and second FCPUs134and136, respectively.

The host102may include a host processor104, a host cache106and a host controller interface108.

The host102may include the host processor104and the host cache106, which give the host102higher performance and larger capacity as compared with the memory system110. Unlike the memory system110, the host processor104and the host cache106have a spatial limitation but the hardware thereof may be upgraded as needed. Accordingly, in order to improve operational efficiency, the memory system110may utilize resources of the host102.

In accordance with an embodiment, the storage space of the host cache106of the host102may be up to thousands of times greater than the first and second sub buffers234and236of the first and second FCPUs134and136, respectively. Accordingly, the memory system110may provide the host cache106with memory map data used by the first and second FCPUs134and136, thereby allowing the host cache106to be used as a cache memory for an address translation operation performed by the memory system110. In such a case, based on host map data cached in the host cache106, the host102may translate a logical address into a physical address and then provide the physical address to the memory system110together with a request. In that case, the memory system110need not translate the logical address into the physical address. Rather, the memory system110need only access one or the other of the first and second memory devices152and154based on the provided physical address. Thus, it is possible to reduce the operation burden on the first and second FCPUs134and136in using the first and second sub buffer234and236, thereby improving the operational efficiency of the memory system110.

Even though the memory system110provides the map data to the host102, the memory system110may still manage the map data, for example, perform update, deletion, and generation of the map data. This is because the first and second FCPUs134and136performs a background operation such as garbage collection and wear leveling according to the operation state of the first and second memory devices152and154and determines a physical location in the first and second memory devices152and154at which data received from the host102is stored, so that a physical address of data in the first and second memory device152and154may be changed by the first and second FCPUs134and136.

The host map data may include L2P map data for identifying a physical address corresponding to a logical address. Meta data for indicating that a logical address and a physical address correspond to each other may include L2P map data for identifying the physical address corresponding to the logical address and P2L map data for identifying the logical address corresponding to the physical address. The host map data may include the L2P map data. The P2L map data is mainly used for an internal operation of the memory system110, and may not be used for an operation in which the host102stores data in the memory system110or reads data corresponding to a specific logical address from the memory system110. In accordance with an embodiment, the P2L map data may not be sent from the memory system110to the host102.

The first and second FCPUs134and136may store the L2P map data or the P2L map data in the first and second memory device152and154, respectively, while managing (i.e., generating, deleting, updating, and the like) the L2P map data or the P2L map data. Since the host cache106is a volatile memory, the host map data may be lost when an event, such as interruption of the supply of power to the host102and the memory system110, occurs. Accordingly, the first and second FCPUs134and136may not only maintain the host map data in its most recent state, but also store the most recent L2P map data or the P2L map data in the first and second memory devices152and154, respectively.

FIG. 4illustrates specific operations of the host102, which transfers a command including logical and physical addresses (LBA and PBA), and the memory system110, which receives the command from the host102.

Referring toFIG. 4, in operation S412, the host102may generate a request including the logical address LBA. Subsequently, in operation S414, the host102may check whether the physical address PBA corresponding to the logical address LBA is present in map data. When the physical address PBA is not present in the map data (that is, “NO” in operation S414), the host102may transfer the request including the logical address LBA in operation S418.

On the other hand, when the physical address PBA is present in the map data (that is, “YES” in operation S414), the host102may add the physical address PBA to the request including the logical address LBA, in operation S416. In operation S418, the host102may transfer the request including the LBA and PBA.

The memory system110may receive a request from an external device, in operation S422. For example, the host interface132may provide any one of the first and second memory subsystems112and114with the request, based on a logical address included in the request of the host102.

In operation S424, the memory system110may check whether the physical address PBA is included in the received request. When the physical address PBA is not included in the received request (that is, “NO” in operation S424), the memory system110may search for a physical address corresponding to the logical address included in the received request, in operation S432.

When the physical address PBA is included in the received request (that is, “YES” in operation S424), the memory system110may check whether the physical address PBA is valid, in operation S426. The memory system110may transfer the map data to the host102, and the host102may perform a mapping operation based on the map data transferred by the memory system110, and transfer the request including the physical address PBA. However, after the memory system110transfers the map data to the host102, the map data managed by the memory system110may be changed or updated. As such, when the map data is in a dirty state, the physical address PBA transferred by the host102cannot be used as it is. Thus, the memory system110may determine whether the physical address PBA included in the received request is valid. When the physical address PBA included in the received request is valid (that is, “YES” in operation S426), the memory system110may perform an operation corresponding to the request, by using the physical address PBA, in operation S430.

When the physical address PBA included in the received request is not valid (that is, “NO” in operation S426), the memory system110may discard the physical address PBA included in the received request, in operation S428. In this case, the memory system110may search for the physical address PBA based on the logical address LBA included in the received request, in operation S432.

When map data in a map segment of the memory system110is updated, a physical address in the map segment stored by the host102may become invalid. When the host102searches for an invalid physical address and provides the memory system110with a read command including the invalid physical address, the memory system110cannot use the invalid physical address and thus needs to search for a valid physical address. When the map segment stored by the host102includes multiple invalid physical addresses, the host102and the memory system110need to repeatedly search for valid physical addresses, and thus the efficiency of physical address search may decrease.

Accordingly, the memory system110may deactivate a logical address region that has been activated in the past and in which map data has been updated. The deactivating of the previously activated logical address region by the host interface132refers to notifying the host102to no longer search for a physical address of the logical address region and to provide the memory system110with a read command that does not include the physical address for the logical address region. The host interface132may provide the host102with a deactivation recommendation to deactivate the activated logical address region.

FIGS. 5A and 5Bare diagrams illustrating memory map data in accordance with an embodiment.

As illustrated above with reference toFIG. 1, the memory system110may identify, for each logical address region including consecutive logical addresses, the number of times the corresponding logical address region is accessed for a read operation to generate a read count, in order to effectively predict logical addresses likely to be read in the future by the host102. The read count of a logical address region may represent the number of times that a read command including logical address(es) within the logical address region is received from the host102. The read count of each logical address region may be referred to as an activation count of the corresponding logical address region.

Each of first to fourth regions REGION1to REGION4illustrated inFIG. 5Arepresents a logical address region. Each of REGION1to REGION4may include a group of consecutive logical addresses. For example, REGION1may include logical addresses LBA1to LBA100, and REGION2may include logical addresses LBA101to LBA200.

FIG. 5Aillustrates an 11thsub region SUB_REGION11and a 12thsub region SUB_REGION12of the first region REGION1. SUB_REGION11may include odd-numbered logical addresses among the logical addresses included in REGION1. SUB_REGION12may include even-numbered logical addresses among the logical addresses included in REGION1.

AlthoughFIG. 5Adescribes as an example that one logical address region, e.g., REGION1, is divided into two sub regions and the two sub regions that include odd-numbered logical addresses and an even-numbered logical addresses, respectively. However, the present invention is not limited to that specific configuration. For example, when the memory system110includes four memory subsystems, one logical address region may be divided into four sub regions, and logical addresses in that one logical address region may be distributed to the four sub regions according to a result of a modulo operation.

FIG. 5Billustrates a map segment included in the memory map data.

The memory map data may include a plurality of map segments. First to fourth segments SEGMENT1to SEGMENT4illustrated inFIG. 5Bmay include the map data of the logical addresses of the first to fourth regions REGION1to REGION4, respectively.

As shown inFIG. 5Bby way of example for SEGMENT2, each of the plurality of map segments may include a first sub segment including first map data of map entries of odd-numbered logical addresses and a second sub segment including second map data of map entries of even-numbered logical addresses. Each map entry may include a logical address-physical address pair. The first sub segment of each map segment may be stored in the first sub buffer234and the first memory device152, and the second sub segment of each map segment may be stored in the second sub buffer236and the second memory device154.

The host interface132may provide the host102with an activation recommendation when the activation count of a specific logical address region exceeds a threshold value, and may obtain the first and second sub segments, both of which correspond to the logical address region, from the first and second sub buffers234and236according to a read buffer request of the host102and provide the host102with the first and second sub segments. In addition, the host interface132may provide the host102with a deactivation recommendation so as to deactivate the activated logical address region according to whether the map data included in the first and second sub segments are updated.

The host interface memory232may store data for determining whether to provide the activation recommendation or the deactivation recommendation.

FIGS. 6A to 6Care diagrams illustrating data that can be stored in the host interface memory232in accordance with an embodiment.

FIG. 6Aillustrates the data that can be stored in the host interface memory232.

The host interface memory232may store an activation count table602and an activation status bitmap604. The activation count table602may store an activation count for each logical address region. The activation status bitmap604may store whether sub logical address regions included in each of a plurality of logical address regions are activated.

The host interface132may update the activation count of a logical address region in the activation count table602whenever a read command including a logical address in the logical address region is received from the host102. With reference to the activation count table602, the host interface132may provide the host102with an activation recommendation for a logical address region having an activation count equal to or greater than a threshold value.

FIG. 6Billustrates a case in which the host interface132provides the host102with an activation recommendation for a third region because the activation count of the third region is equal to or greater than the threshold value, which may be 32 in this example. An activation recommendation is not made for any of the other regions (e.g., first, second or fourth) because the activation count for each is less than the threshold value.

The host interface132may obtain first and second sub segments, corresponding to a specific logical address region, from the first and second sub buffers234and236according to a read buffer request of the host102, provide the host102with the first and second sub segments, and then set a bit value, corresponding to each of the first and second sub logical address regions included in the logical address region, to “1”.

FIG. 6Cillustrates a case in which the bit value corresponding to each of the first and second sub regions included in the third region is set to “1” after the third region is activated.

FIG. 7illustrates a logical address region activating operation of the data processing system100in accordance with an embodiment.

In operation S702, the host interface132may determine a logical address region to be activated. As described with reference toFIG. 6B, the host interface132may determine the logical address region(s) to be activated, based on an activation count for each logical address region. Hereinafter, each logical address region to be activated is referred to as an activation target logical address region.

In operation S704, the host interface132may provide the host102with an activation recommendation for an activation target logical address region.

In operation S706, the host102may prepare to receive a target segment, which is a map segment corresponding to the activation target logical address region, in response to the activation recommendation. For example, the host102may allocate the host cache106for storing the target segment.

When the host102is prepared to receive the target segment, the host102may provide the memory system110with a read buffer request in operation S708.

The read buffer request refers to a request provided by the host102for reading a buffer of the memory system110. The host102may provide the memory system110with the read buffer request so as to obtain the target segment stored in the buffer of the memory system110. The target segment may be divided into first and second sub target segments and stored in the first and second sub buffers234and236, respectively. For example, the first sub target segment for odd-numbered logical addresses of the logical address region may be stored in the first sub buffer234, and the second sub target segment for even-numbered logical addresses of the logical address region may be stored in the second sub buffer236.

The host interface132may provide the first FCPU134with a first read buffer request so as to obtain the first sub target segment, in operation S710. The host interface132may provide the second FCPU136with a second read buffer request so as to obtain the second sub target segment, in operation S714.

The first FCPU134may provide the host interface132with the first sub target segment, which has been buffered in the first sub buffer234in operation S712, in response to the first read buffer request of operation S710. The first sub buffer234may store information on whether the first sub target segment is activated.

The second FCPU136may provide the host interface132with the second sub target segment, which has been buffered in the second sub buffer236in operation S716, in response to the second read buffer request of operation S714. The second sub buffer236may store information on whether the second sub target segment is activated.

In operation S718, the host interface132may combine the first and second sub target segments to form the target segment, and provide the host102with the target segment.

In operation S720, the host interface132may set the activation status bits for first and second sub regions, included in the activation target logical address region, to “1”. The host102may convert a logical address to a physical address by referring to the target segment received from the memory system110, in order to access the activation target logical address region, and provide the host interface132with a read command including the logical and physical addresses.

FIG. 8is a diagram illustrating a logical address region deactivating operation of the data processing system100in accordance with an embodiment.

In operation S802, the first FCPU134may update a first sub segment. For example, the first FCPU134may change mapping between the logical address and the physical address in response to a write command for an odd-numbered logical address, and update the first sub segment including the logical address.

In operation S804, when the updated first sub segment is for an activated logical address region, the first FCPU134may provide a deactivation signal for a first sub region corresponding to the first sub segment. Referring to operation S712, the first sub buffer234may store information on whether the first sub segment is activated. Therefore, the first FCPU134may determine whether the first sub segment is related to the activated logical address region.

In operation S806, the host interface132may reset a bit for the first sub region to “0” in the activation status bitmap604in response to the deactivation signal of the first FCPU134.

In operation S808, the second FCPU136may update a second sub segment. For example, the second FCPU136may change mapping between the logical address and the physical address in response to a write command for an even-numbered logical address, and update the second sub segment including the logical address.

In operation S810, when the updated second sub segment is for an activated logical address region, the second FCPU136may provide a deactivation signal for a second sub region corresponding to the second sub segment. Referring to operation S716, the second sub buffer236may store information on whether the second sub segment is activated. Therefore, the second FCPU136may determine whether the segment sub segment is related to the activated logical address region.

In operation S812, the host interface132may reset a bit for the second sub region to “0” in the active state bitmap604in response to the deactivation signal of the second FCPU136.

When all the bits for the first and second sub regions included in a specific activated logical address region among the plurality of map segments are reset to “0”, the host interface132may deactivate the activated logical address region in operations S814, S816and S818.

In operation S814, the host interface132may reset the activation count of the activated logical address region in the activation count table602.

In operation S816, the host interface132may provide the host102with a deactivation recommendation for the activated logical address region.

In operation S818, the host102may deactivate the activated logical address region by removing the map segment, corresponding to the activated logical address region, from the host cache106.

According to an embodiment, the memory system110may include the first and second memory subsystems112and114and the host interface132. The first memory subsystem112may store data for first, e.g., odd-numbered, logical addresses, and the second memory subsystem114may store data for second, e.g., even-numbered, logical addresses. The host interface132may sort a plurality of logical addresses into logical address regions, in groups of consecutive logical addresses. Each of the logical address regions may include first logical addresses and second logical addresses, and a map segment corresponding to each of the logical address regions may be divided into sub segments, some of which are stored in the first memory subsystem112and others are stored in the second memory subsystem114.

The host interface132may provide any one of the first and second memory subsystems112and114with a read command based on the logical address included in the read command of the host102, identify a logical address region among multiple logical regions based on their respective activation counts, obtain map data included in the map segment from the first and second memory subsystems112and114according to a result of the activation counts inspection, and provide the host102with the map data.

According to an embodiment, even when map data for one logical address region is divided and that map data are utilized in the different first and second memory subsystems112and114, the host interface132may allow the host102to easily search physical addresses for a logical address, by providing the host102with the whole map segment of the single logical address region.

According to embodiments, a method and apparatus enable timely receipt by a memory system from a host a request including a physical address of data to be read, by providing, in a timely manner, the host with map data expected to be frequently referred to by the memory system.

Advantages and effects of the present disclosure are not limited to those described above; those skilled in the art to which the present disclosure pertains will appreciate from the above detailed description that additional advantages and effects are obtainable as well.

While specific embodiments have been illustrated and described herein, it will be apparent to those skilled in the art in view of the present disclosure that various changes and modifications may be made without departing from the scope of the invention. Therefore, the scope of the present invention is not limited to the described embodiments. Rather, the present invention encompasses all such changes and modifications that fall within the scope of the claims including their equivalents.