Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same

By omitting a growth mask or by omitting lithographical patterning processes for forming growth masks, a significant reduction in process complexity may be obtained for the formation of different strained semiconductor materials in different transistor types. Moreover, the formation of individually positioned semiconductor materials in different transistors may be accomplished on the basis of a differential disposable spacer approach, thereby combining high efficiency with low process complexity even for highly advanced SOI transistor devices.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of different transistor types, such as SOI-like transistors in the form of fully and partially depleted transistors, formed in and on a thin semiconductor layer and having strained channel regions by using an embedded strain layer to enhance charge carrier mobility in the channel region.

2. Description of the Related Art

The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source regions.

The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel, due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.

The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability.

The continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques concerning the above-identified process steps. It has been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the above process adaptations associated with device scaling. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region may increase the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast and powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.

Thus, in some approaches, external stress created by, for instance, overlaying layers, spacer elements and the like is used in an attempt to create a desired strain within the channel region. However, the process of creating the strain in the channel region by applying a specified external stress may suffer from an inefficient translation of the external stress into strain in the channel region.

In another approach, the hole mobility of PMOS transistors is enhanced by forming a strained silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region. To this end, the drain and source regions of the PMOS transistors are selectively recessed, while the NMOS transistors are masked and subsequently the silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth. Thus, complex manufacturing steps, such as etch processes, the formation of appropriate etch and growth masks and selective epitaxial growth techniques have to be incorporated into the CMOS process flow. Moreover, for SOI transistors formed in very thin silicon layers having a thickness of approximately 100 nm and even less, this technique may not result in the expected performance gain as is the case in SOI devices including less scaled active silicon layers or in bulk devices, since the stress transfer is substantially restricted to the channel region located below the gate insulation layer while lower-lying active regions in the thin SOI transistor may not be effectively strained, thereby reducing the overall efficiency of the strain engineering process. In addition, the performance gain for transistors of different conductivity type may lead to an even more complex process flow, as the various steps for the formation of respective strain layers may have to be performed separately for each transistor type.

In view of the above-described situation, there exists a need for an improved technique that enables an increase of performance of PMOS transistors and NMOS transistors on the basis of strained layers in an efficient manner.

SUMMARY OF THE INVENTION

Generally, the present invention is directed to a technique that enables the formation of differently strained semiconductor layers in different transistor types, such as P-channel transistors and N-channel transistors, on the basis of a highly efficient manufacturing process flow since, in one aspect, the provision of a hard mask, typically provided for selectively epitaxially growing strained semiconductor layers, may be omitted for at least one type of transistor, thereby significantly reducing process complexity, while at the same time an additionally grown strained semiconductor material may be advantageously used in further process steps, such as silicidation. In other aspects, one or more hard masks required for the selective epitaxial growth technique may be formed in a highly efficient manner, for instance without requiring a lithography step, thereby also providing a highly efficient technique for the formation of strained semiconductor layers of different characteristics in various transistor types. In yet another aspect of the present invention, a strained layer may be provided for different types of transistors in that a disposable spacer approach may be used, in which appropriate offset spacer elements for each type of transistor may be individually formed, thereby enabling the positioning of strained semiconductor material close to a channel region, which may be highly advantageous in the context of SOI transistor elements with moderately thin active semiconductor layers for the formation of partially and fully depleted transistor devices.

According to one illustrative embodiment of the present invention, a method comprises forming a first recess adjacent to a first gate electrode of a first transistor, wherein the first gate electrode is formed above a substrate comprising a crystalline semiconductor layer. Furthermore, a second recess is formed adjacent to a second gate electrode of a second transistor. Moreover, a first strained semiconductor material is epitaxially grown in the first recess and a second strained semiconductor material is epitaxially grown in the second recess and above the first strained semiconductor material.

According to another illustrative embodiment of the present invention, a method comprises forming a first recess adjacent to a first gate electrode of a first transistor, wherein the first gate electrode is formed above a substrate comprising a crystalline semiconductor layer. A second recess is formed adjacent to a second gate electrode of a second transistor. Additionally, a first strained semiconductor material is formed in the first recess and a second strained semiconductor material is formed in the second recess on the basis of a first and a second epitaxial growth process based on one or more growth masks formed without a lithographical patterning process.

According to yet another illustrative embodiment of the present invention, a method comprises forming a first recess adjacent to a first gate electrode of a first transistor, wherein the first gate electrode has a first sidewall spacer and is formed above a substrate comprising a crystalline semiconductor layer. Furthermore, a first strained semiconductor material is formed in the first recess, while a second transistor is covered. The method further comprises forming a second recess adjacent to a second gate electrode of the second transistor, wherein the second gate electrode has a second sidewall spacer. Furthermore, a second strained semiconductor material is formed in the second recess and the first sidewall spacer is removed. Finally, the second sidewall spacer is removed.

DETAILED DESCRIPTION OF THE INVENTION

Generally, the present invention relates to the formation of field effect transistors of different types, such as different conductivity types, which receive a strained semiconductor layer in the drain and/or source regions in order to provide a desired magnitude and/or type of strain in the respective channel regions of these transistors. For this purpose, an appropriate masking scheme is provided that enables the formation of respective strained semiconductor materials on the basis of epitaxial growth techniques such that, for each transistor type, a specified magnitude and/or type of strain may be created in the semiconductor material, which may be incorporated into the respective drain and/or source regions, thereby providing an embedded strained semiconductor material. In some illustrative embodiments, the transistor types may represent N-channel transistors and P-channel transistors, wherein each type of transistor may receive a strained semiconductor material to enhance the mobility of the respective majority charge carriers in the corresponding channel regions. Since the strained semiconductor material may be provided by epitaxial growth techniques, and in particular embodiments by selective epitaxial growth techniques, highly efficient masking schemes are provided by the present invention in order to maintain process complexity at a low level while nevertheless achieving a significant enhancement in device performance due to the provision of individually adjusted strained semiconductor materials in different transistor types.

In some illustrative embodiments, a highly efficient technique for the formation of silicon-on-insulator (SOI) transistors is provided, wherein the various characteristics of the respective strained semiconductor material may be individually adapted for each transistor type, for instance in terms of offset to the respective channel region, magnitude of strain, type of strain and the like. Consequently, even for highly advanced SOI-like transistors which may be manufactured on the basis of thin semiconductor layers, thereby forming partially or even fully depleted devices, a highly efficient strain-inducing mechanism may be established, although the embedded strained semiconductor material may be provided as a shallow portion in the drain and source regions due to the required crystalline template of the original semiconductor material of the thin semiconductor layer during the epitaxial growth process. In other illustrative embodiments, highly efficient masking schemes for the provision of respective epitaxial growth masks, such as the omission of a growth mask and/or the omission of advanced lithography steps for the formation of respective growth masks, may significantly contribute to a reduced process complexity.

With reference to the accompanying figures, further illustrative embodiments of the present invention will now be described in more detail.FIG. 1aschematically illustrates a cross-sectional view of a semiconductor device100comprising a substrate101, above which is formed a semiconductor layer102. The substrate101may represent any appropriate carrier material for receiving the semiconductor layer102, such as a bulk semiconductor substrate, an insulating carrier material, such as an SOI substrate, and the like. It should be appreciated that the vast majority of complex integrated circuits currently are, and will be in the foreseeable future, fabricated on the basis of silicon and thus, in some illustrative embodiments, the semiconductor layer102may be comprised of silicon, for instance including a significant amount of other materials, such as germanium, carbon and the like, wherein the substrate101may represent a bulk silicon substrate or any other appropriate carrier material. Moreover, in some embodiments, the semiconductor layer102may be appropriately configured to enable the fabrication of fully or partially depleted SOI transistors, as will be explained in more detail with reference toFIGS. 2a-2i. The semiconductor device100may further comprise a first transistor element150pand a second transistor element150n, which may be provided above the substrate101at specified substrate positions according to device requirements. In some illustrative embodiments, the first and second transistors150p,150nmay at least differ in their respective conductivity type, whereas, in other illustrative embodiments, the first and second transistors150p,150nmay differ in their function within a complex circuitry. For example, in the former case, the first transistor150pmay represent a P-channel transistor, while the second transistor150nmay represent an N-channel transistor, which are to receive a respective strained semiconductor material having a compressive and a tensile strain, respectively. In the latter case, in some illustrative embodiments, one of the first and second transistors150p,150nmay represent an advanced transistor of high switching speed, while the other one of the transistors150p,150nmay represent a transistor requiring a reduced leakage current behavior, such as a transistor in a static RAM area and the like. In addition to their different function, in this case, the transistors150p,150nmay or may not differ in their conductivity type, wherein, however, at least a different magnitude of strain may be desired for the two types of transistors. During the following description, it may be assumed that the first and second transistors150p,150ndiffer in their conductivity type and are to receive a strained semiconductor material having a different type of strain.

In the manufacturing stage shown inFIG. 1a, the transistors150p,150nmay each comprise a gate electrode105, which may be formed above a respective channel region103and separated therefrom by a corresponding gate insulation layer104. Moreover, in one illustrative embodiment, a spacer layer106A may be commonly formed above the respective gate electrodes105, wherein a liner107A may be provided to act as an etch stop layer during an etch process108. The spacer layer106A may be comprised of any appropriate material, such as silicon nitride, silicon dioxide and the like, while the liner107A may be provided in the form of any appropriate material having the required etch selectivity to the material of the layer106A. For example, silicon dioxide may be used for the liner107A when the spacer layer106A is comprised of silicon nitride. Furthermore, respective capping layers109, which may be formed of any appropriate material, such as silicon nitride and the like, may be formed on top of the respective gate electrodes105, thereby providing an encapsulation of the gate electrodes105after the completion of the etch process108for forming respective sidewall spacers, as will be described below.

A typical process flow for forming the semiconductor device100as shown inFIG. 1amay comprise the following processes. After the provision of the substrate101and the semiconductor layer102, for instance on the basis of epitaxial growth techniques, wafer bond techniques and the like, depending on the type of substrate and semiconductor material used, any required processes, such as implantation processes for forming vertical dopant profiles, if required, within the layer102, and manufacturing processes for forming isolation structures (not shown), such as shallow trench isolations, may be performed on the basis of well-established techniques. Thereafter, a dielectric layer may be formed by oxidation and/or deposition with a thickness as required for the gate insulation layers104. Next, an appropriate material for the gate electrodes105may be deposited, for instance in the form of polysilicon on the basis of low pressure chemical vapor deposition (CVD) techniques. It should be appreciated that in some process strategies the gate electrodes105in this manufacturing stage may not be represented by a highly conductive material as required, but may be converted into a respective conductive material in a later manufacturing stage. For example, a highly conductive metal silicide may be provided in the gate electrode105in a later manufacturing stage, when initially a polysilicon material may be provided for the gate electrodes105. In other cases, the gate electrodes105may be substantially completely replaced by other materials, such as metals and the like, in a later manufacturing stage. After the deposition of the material of the gate electrodes105, an appropriate capping material, such as silicon nitride and the like, may also be deposited on the gate electrode material, possibly in combination with other material layers, such as anti-reflective coating (ARC) materials and the like, as may be required for the subsequent lithographical patterning of the corresponding layer stack. Consequently, appropriate lithography and etch techniques may be used in order to pattern the resulting layer stack, thereby forming the gate electrode105on the gate insulation layer104and covered by the capping layers109.

Thereafter, the liner107A may be formed, for instance by deposition and/or by oxidation, depending on the device requirements and the material used, followed by a respective deposition process for providing the spacer layer106A, wherein well-established plasma enhanced deposition techniques may be used. A thickness of the spacer layer106A in combination with a thickness of the layer107A may substantially determine a spacer width formed from the layers106A,107A during the etch process108, which in turn may substantially determine a resulting offset from the gate electrode105for a recess to be formed in the semiconductor layer102adjacent to respective channel regions103. It should be appreciated that, in some illustrative embodiments, the spacer layer106A may be formed in accordance with process parameters selected such that corresponding spacer elements may also be used for the formation of drain and source regions by ion implantation during a later manufacturing stage, while, in other illustrative embodiments, the spacer layer106A and the layer107A may be formed with a thickness that is selected merely with respect to a desired offset for recesses to be formed in the layer112later on.

After the deposition of the layers107A,106A, the etch process108is performed on the basis of an appropriate etch chemistry to obtain a substantially anisotropic behavior with a high etch selectivity between the layers106A,107A. Respective selective etch recipes are well established in the art. Thereafter, exposed portions of the liner107A may be removed by a further etch process, for instance based on a wet chemical etch process or any other appropriate technique, such as a high frequency plasma etch and the like. For example, appropriate etch strategies are well established for silicon dioxide, silicon nitride and the like. In other illustrative embodiments, exposed portions of the liner107A may be removed in a subsequent etch process for creating respective recesses adjacent to the gate electrodes105.

FIG. 1bschematically illustrates the semiconductor device100during a respective etch process110, in which recesses111are formed in the layer102adjacent to the corresponding gate electrodes105on the basis of sidewall spacers106that have been formed from the spacer layer106A, as was previously described. Thus, it should be understood that, throughout this description and in the appended claims, any recesses or cavities formed “adjacent to” a gate electrode include the provision of any sidewall spacer structure on the sidewall of the respective gate electrode prior to actually forming the recesses or cavities. Hence, “adjacent to” the gate electrode may enclose a lateral offset provided by a sidewall spacer structure. In some illustrative embodiments, the etch process110may be designed as a substantially anisotropic etch process, thereby obtaining the recesses111as trenches having moderately steep sidewalls, wherein an offset111B of the recess111with respect to the gate electrode105, and thus to the channel region103, is substantially determined by a spacer width106B, which may also include the thickness of the liner107A. In other illustrative embodiments, the etch process110may be designed as a more or less isotropic process, wherein a certain degree of under-etch is achieved wherein the offset111B is then determined by the etch parameters and the spacer width106B. During the etch process110, material erosion in the gate electrodes105may be substantially avoided by the spacers106and the capping layers109.

FIG. 1cschematically illustrates the semiconductor device100in a further advanced manufacturing stage. A growth mask112may be formed to cover the second transistor150nincluding the recesses111, while the first transistor150pis exposed to the deposition ambient of a selective epitaxial growth process113. The growth mask112may be comprised of any appropriate material that is configured to withstand the environmental conditions during the epitaxial growth process113, that is, the growth mask112may have to tolerate temperatures up to several hundred degrees and provide a specified selectivity during the deposition of material in the process113. For instance, silicon nitride, silicon dioxide and the like are dielectric materials for which a plurality of process parameter values are available, which may allow the selective epitaxial growth of a silicon-based material on exposed crystalline silicon areas, while a significant deposition of silicon material on dielectric materials, such as the growth mask112, as well as the capping layer109and the spacer106of the first transistor150p, may be avoided or reduced.

Consequently, during the process113, a silicon-based semiconductor material may be selectively formed in the recess111of the first transistor150p, wherein the underlying material of the layer102acts as a growth template when the semiconductor layer102is a silicon-based material. Moreover, during the epitaxial growth process113, a specific non-silicon material may be added to the deposition atmosphere, at least temporarily, in order to form a semiconductor material, indicated as114p, having a different lattice spacing in its non-strained state so that, upon growing on the crystalline template of the layer102, the material114prepresents a strained semiconductor material, which may thus also induce a respective strain in the adjacent channel region103. In one illustrative embodiment, the strained semiconductor material114pmay represent a compressively strained material, such as a silicon/germanium material, which may efficiently enhance charge carrier mobility in the channel region103when the first transistor150pmay represent a P-channel transistor. As shown, the selective epitaxial growth process113may be controlled such that a desired degree of filling of the recess111is obtained, wherein, depending on device requirements, the recess111may be underfilled or overfilled or may result in a substantially flush configuration.

After the growth process113, the mask112, which may, for instance, be comprised of silicon dioxide may be removed selectively to the material of the capping layer109and the spacers106. For instance, highly selective dry and wet chemical etch processes are available for silicon dioxide, silicon nitride and the like. In still other illustrative embodiments, the first transistor150pmay be covered by a resist mask (not shown) during the removal of the mask112in order to avoid undue damage or material erosion in the first transistor150p. Thereafter, any additional pre-cleaning processes may be performed in order to prepare the exposed transistor150nfor the selective growth of a further strained semiconductor material.

FIG. 1dschematically illustrates the semiconductor device100during a further selective epitaxial growth process115, in which, at least temporarily, a semiconductor material114nis formed in the recess111of the second transistor150n, which differs in its strain characteristics from the material114p. In one illustrative embodiment, the material114nmay be provided as a semiconductor material having a different type of strain compared to the material114p, thereby inducing a different type of strain in the respective channel region103of the second transistor150n. For instance, if the second transistor150nmay represent an N-channel transistor, the strained semiconductor material114nmay be provided as a material having a reduced lattice spacing in its non-strained state compared to the silicon-based material of the layer102. For example, the material114nmay be deposited as a silicon/carbon material wherein a carbon content of 0.5 to several atomic percent may be incorporated into the silicon in order to obtain a desired lattice mismatch so that, when the material114nis grown with a substantially silicon-like lattice spacing, a corresponding tensile strain is generated. It should be appreciated that the type of strain created by the selective epitaxial growth process115, and also by the process113, may depend on the crystalline characteristics of the template material of the layer102. For example, if the semiconductor layer102itself contains a certain amount of non-silicon components, such as germanium, carbon and the like, the material composition of the materials114pand114nmay be correspondingly selected so as to obtain the desired type of strain. In other illustrative embodiments, the first and second transistor elements150p,150nmay be of the same conductivity type and thus require the same type of strain, whereas a different magnitude may be desirable due to device or process specific requirements. In this case, the growth processes113and115may be performed on the basis of substantially the same parameters, except for different amounts of non-silicon species in order to create a different magnitude of the same type of strain.

Moreover, as shown inFIG. 1d, during the epitaxial growth process115, the first transistor150pmay remain exposed to the deposition ambient so that a corresponding material114nmay also be formed on top of the previously formed strained material114p. Consequently, any complex process steps for forming a corresponding growth mask, such as the mask112, and the removal thereof may be omitted, thereby contributing to a reduced overall process complexity. It should be noted that the material114nand the material114pmay exhibit, in some embodiments, a different type of intrinsic strain. The influence of the “capping layer”114non the respective channel region103of the first transistor150pis, however, significantly less compared to the strained material114p, which may substantially directly act on the channel region103. In some embodiments, the effect of the capping material114nabove the layer114pmay be considered inappropriate for the performance of the first transistor150p. Thus, in some illustrative embodiments, the material114nmay be deposited with a thickness that is appropriate for being consumed in a later manufacturing stage, for instance for the formation of metal silicide in the first transistor150p, as will be described later on in more detail.

Thereafter, depending on process strategy, the spacers106may be used for the formation of drain and source regions by ion implantation, while, in other illustrative embodiments, the spacers106may be removed by appropriate selective dry and/or wet chemical etch processes prior to forming respective drain and source regions. For instance, drain and source implantations may be performed on the basis of the spacers106, wherein respective extension regions (not shown) may have been formed prior to the formation of the strained semiconductor materials114p,114n. In other embodiments, respective extension regions, if required, may be formed after the removal of the spacers106, irrespective of whether these spacer elements may have been used as implantation masks for the formation of deep drain and source regions.

FIG. 1eschematically illustrates the semiconductor device100in a further advanced manufacturing stage, in which a spacer structure116is formed on the respective gate electrodes105of the first and second transistors150p,150n. Moreover, drain and source regions117may be formed in the strained semiconductor materials114p,114nand in the semiconductor layer102, wherein the lateral profiling of the drain and source regions117may have been accomplished on the basis of the spacer structure116, which may include two or more individual spacer elements (not shown), or which may also be accomplished on the basis of the spacers106, as previously explained. Moreover, the device100may comprise a layer of refractory metal118, which may be formed above the first transistor150phaving the “capping” layer114nformed above the respective drain and source regions117. In this illustrative embodiment, the metal layer118may not be formed above the second transistor150nso as to allow individually adjusting a corresponding silicidation process with respect to the characteristics of the material114nlocated above the material114pin the first transistor150p.

The device100as shown inFIG. 1emay be formed on the basis of the following processes. The drain and source regions117having a specified vertical and horizontal dopant profile according to device requirements may be formed on the basis of the spacers106and/or116, as previously described, wherein well-established implantation processes may be used, wherein, in some embodiments, a certain dopant species may also be incorporated during the selective epitaxial growth processes113and115. Thereafter, respective anneal processes may be performed to activate the dopants in the regions117and also to re-crystallize implantation-induced damage according to device requirements.

Thereafter the layer118, which may be comprised of any appropriate refractory metal, such as nickel, nickel/platinum, platinum, cobalt and the like, may be deposited on the basis of well-established techniques such as sputter deposition and the like, wherein a thickness of the layer118may be selected on the basis of the material114nformed above the material114pso as to convert a desired amount thereof into a respective metal silicide. For example, the layer118may be deposited and may afterwards be patterned on the basis of a lithography process so as to remove the layer118from the second transistor150n. In still other examples, a respective lithography mask may be formed prior to the deposition of the layer118and a respective patterning of the layer118may be achieved by depositing the material on the device100and removing the lithography mask together with any metal material deposited thereon.

Thereafter, an appropriate heat treatment may be performed to initiate the conversion of the material114nin the first transistor150pinto a respective metal silicide. For instance, if the strained material114nmay be comprised of silicon/carbon including a moderately low amount of carbon, as specified above, a respective metal silicide may be formed. In other illustrative embodiments, prior to initiating a chemical reaction between the layer118and the underlying silicon-containing material, a further refractory metal layer (not shown) may be deposited with a required thickness so as to meet the corresponding device requirements of the second transistor150nso that metal silicides of different characteristics may be formed in the first and second transistors150p,150nin a common heat treatment. For example, the same or a different refractive material may be deposited and subsequently a corresponding heat treatment may be performed, during which respective process parameters, in particular the duration of the heat treatment, may be selected such that a desired amount of the material114nin the first transistor150pis converted into a metal silicide, while in the second transistor150nthe corresponding reaction, i.e., the amount of metal silicide obtained, may be substantially determined by the amount of refractory metal provided at the second transistor150n.

FIG. 1fschematically shows the semiconductor device100after completion of the above-described process sequence. Hence, the device100comprises respective metal silicide regions118A in the first transistor150p, wherein a specified amount of the material114nmay be converted into a metal silicide, while the second transistor150nmay have formed therein respective metal silicide regions119A, which correspond to the device requirements of this transistor. Consequently, the non-desired effect of the strained material114nin the first transistor150pmay be significantly reduced by forming a highly conductive metal silicide therein, thereby also providing the potential for specifically increasing the performance of the first transistor150p, since the respective gate electrode105may also have an increased amount of metal silicide. On the other hand, the second transistor150nmay have the metal silicide regions119A complying with transistor specific requirements, wherein the remaining strained material114nprovides the desired type and magnitude of strain in the respective channel region103. Consequently, the performance characteristics of the transistors150p,150nmay be adjusted in a highly uncorrelated manner while at the same time the process complexity is significantly reduced due to the omission of at least one epitaxial growth mask and any process steps associated therewith. If, for example, the first transistor150prepresents a P-channel transistor, a high degree of compressive strain may be generated by the strained material114p, while, additionally, a high conductivity of the gate electrode105and the respective contact regions of the drain and source regions117is achieved, while the performance of the transistor150nmay be enhanced by providing the material114nhaving a desired magnitude of tensile strain.

With reference toFIGS. 2a-2i, further illustrative embodiments will now be described in more detail, in which a strained semiconductor material of different strain characteristics may be formed adjacent to respective gate electrodes in a highly efficient manner, thereby enabling the positioning of the strained material close to the channel region, which may be highly advantageous in the context of fully depleted and partially depleted transistor elements, which are formed on the basis of thin semiconductor layers.

FIG. 2aschematically shows a cross-sectional view of a semiconductor device200comprising a substrate201having formed thereon, in one illustrative embodiment, a buried insulating layer220, above which is formed a semiconductor layer202. Thus, in this configuration, the device200may represent an SOI-like device, wherein, in some illustrative embodiments, the semiconductor layer202may have characteristics for forming partially or fully depleted transistor elements thereon and therein. Hence, a thickness of the semiconductor layer202, if a silicon-based device is considered, may be approximately 100 nm and significantly less in advanced applications. Moreover, a first transistor250pand a second transistor250nmay be provided, wherein, in this manufacturing stage, respective gate electrodes205are formed on respective gate insulation layers204. Furthermore, respective capping layers209may be formed on the respective gate electrodes205. For forming the device200as shown inFIG. 2a, substantially the same processes may be used as are previously described with reference to the device100.

FIG. 2bschematically illustrates the device200in a further advanced manufacturing stage. Here, a first spacer layer206A, possibly in combination with a respective liner207A, may be formed on the first and second transistors250p,250n. Moreover, the second transistor250nmay be covered by a mask221, such as a resist mask and the like, which may expose the first transistor250pto an anisotropic etch ambient223, while substantially protecting the second transistor250n. The spacer layer206A including the liner207A may be formed on the basis of well-established deposition techniques, such as plasma enhanced chemical vapor deposition (PECVD), wherein a thickness of the conformal spacer layer206A may be selected to provide a desired offset for a recess to be formed adjacent to the gate electrode205of the first transistor250pin a subsequent etch process. For example, a thickness206B of the layer stack206A,207A may range from several nanometers, for instance 3-50 nm, depending on the specific application. Thereafter, the mask221may be formed on the basis of any appropriate material, such as photoresist and the like, using well-established photolithography techniques for patterning a corresponding material layer, thereby forming the mask221. Next, the etch process223may be performed on the basis of well-established anisotropic etch techniques, wherein the etch process223may be reliably stopped in and on the liner207A. Thereafter, the mask221may be removed, for instance on the basis of oxygen plasma-based techniques and the like, and thereafter exposed portions of the layer207A may be removed from the first transistor250p. In other embodiments, the removal of the liner207A may be performed during or after the etch process223and the corresponding mask221may be subsequently removed.

FIG. 2cschematically illustrates the semiconductor device200after the completion of the above-described process sequence. Hence, the transistor250pcomprises respective spacer elements206having a width that substantially corresponds to the thickness206B, while the second transistor250nis still covered by the spacer layer206A. Moreover, the device200is exposed to a further etch ambient210in order to form respective recesses or cavities211pin the first transistor250p. As previously explained, an offset211A of the recess211pwith respect to the gate electrode205and thus the channel region203is influenced by the spacer width206B, and may be substantially determined thereby if the etch process210is a substantially anisotropic process. On the other hand, if the process210comprises an isotropic component, the shape of the recess211pand thus the offset211A may also depend on the process parameters of the etch process210. Consequently, the characteristics of the recess211pmay be individually adapted in accordance with device requirements corresponding to the first transistor250p, while the second transistor250nis reliably covered by the spacer layer206A. After the formation of the recess211p, any cleaning processes may be performed to prepare the device200for the formation of a strained semiconductor material in the recess211p.

FIG. 2dschematically illustrates the device200during an epitaxial growth process213for forming a strained semiconductor material214pin the recess211p, wherein, as previously explained with reference to the device100, any desired degree of underfilling or overfilling or a substantially flush configuration may be accomplished. With respect to the type of strained semiconductor material214p, the same criteria apply as previously explained. For instance, the material214pmay represent a silicon/germanium material with a high intrinsic compressive strain. After the epitaxial growth process213, the spacer layer206A may be removed on the basis of any appropriate selective etch process. For instance, wet chemical etch processes for silicon nitride are well established in the art. Consequently, during a corresponding wet chemical etch process, the layer206A may be removed selectively to the liner207A, while, in the first transistor250p, the spacers206as well as the capping layer209, if comprised of silicon nitride, may also be removed.

FIG. 2eschematically illustrates the semiconductor device200after the completion of the above-described process sequence and with a further spacer layer226A, for instance comprised of silicon nitride and the like, wherein a thickness of the spacer layer226A, indicated as226B, may be selected on the basis of device requirements of the second transistor250n, since the thickness226B may substantially determine the resulting width of spacers formed from the layer226A in the second transistor250n. Consequently, as previously explained, respective characteristics of a recess to be formed in the second transistor250nmay be adjusted substantially independently from respective characteristics of the first transistor250p.

FIG. 2fschematically illustrates the device200in a further advanced manufacturing stage, wherein a further mask224, such as a resist mask or any other appropriate mask, is formed to cover the first transistor250pwhile exposing the second transistor250nto an anisotropic etch ambient225. Consequently, the spacer layer226A is etched in order to form respective spacers226, the width of which is substantially determined by the thickness226B and thus the corresponding width will also be indicated as226B. It should be appreciated that, in some illustrative embodiments, the liner207A, previously formed in combination with the spacer layer206A, may still be present and may be used for etching the spacer layer226A, while, in other illustrative embodiments, after the removal of the spacer layer206A and the respective spacers206, a corresponding liner (not shown) may be formed on the first and second transistors250p,250nprior to the deposition of the spacer layer226A. In this case, the gate electrode205of the first transistor250pand the strained semiconductor material214pmay also be covered by the newly formed liner material. After the etch process225, exposed portions of the liner207A may be removed and the mask224may be subsequently removed on the basis of processes as are previously described. Thereafter, a further etch process may be performed to form a respective recess or cavity211n,as indicated in dashed lines, wherein the respective size and offset of the recesses211nis influenced by the spacer width226B and possibly by the process parameters of the corresponding cavity etch process, as is also explained with reference to the recesses211p. Consequently, the size and the offset of a correspondingly strained semiconductor material may be defined on the basis of the spacers226. For instance, the width226B may range from approximately several nanometers, such as 3-50 nm, depending on the process requirements.

FIG. 2gschematically illustrates the device200in a further advanced manufacturing stage, wherein the device200, after a corresponding cavity etch process for actually forming the recesses211n, is subjected to a further selective epitaxial growth process215for forming a strained semiconductor material214N adjacent to the respective channel region203of the second transistor250n, while the first transistor250pis covered by the spacer layer226A. With respect to the epitaxial growth process215, the same criteria apply as previously explained. For instance, the semiconductor material214N may have a different type of strain and/or may have a different magnitude of strain compared to the material214P. In some illustrative embodiments, the strained semiconductor material214N may comprise a silicon/carbon mixture for imposing a tensile strain to the channel region203of the second transistor250n.

FIG. 2hschematically illustrates the device200in a further advanced manufacturing stage, in which the spacer layer226A and the spacers226have been removed by an appropriate selective etch process, for instance on the basis of a wet chemical etch process, such as a process comprising hot phosphoric acid and the like when the spacer layer226A is substantially comprised of silicon nitride. Moreover, during the corresponding removal process, the capping layer209of the gate electrode205of the second transistor250nmay also be removed. Thereafter, the further processing may be continued by forming source and drain regions in the semiconductor layer202and within the strained semiconductor materials214P,214N on the basis of appropriate spacer techniques and implantation processes.

FIG. 2ischematically illustrates the device200with a corresponding sidewall spacer structure216formed on the respective gate electrodes205, which may have been used for defining respective lateral and vertical dopant profiles for respective drain and source regions217. It should be appreciated that the spacer structures216may comprise any appropriate number of individual spacer elements, depending on the complexity of the required dopant profile of the regions217. Furthermore, the first and second transistors250p,250nmay be covered by a dielectric material, which, in one illustrative embodiment, may be provided as layer portions227P,227N having different intrinsic stresses in order to enhance the strain created in the respective channel regions203. For example, the layer portions227P,227N may comprise silicon nitride, which may be formed so as to include a high intrinsic stress, compressive or tensile, thereby acting as a further stress source for the transistors250p,250n. Thus, in illustrative embodiments, the transistor250pmay represent a P-channel transistor, wherein the strained semiconductor material214P may be a compressive material and the layer portion227P may include a high compressive stress. Similarly, if the second transistor250nrepresents an N-channel transistor, the strained material214N may comprise tensile strain and the layer portion227N may exhibit a high tensile stress. Moreover, respective metal silicide regions218may be formed in the drain and source regions217and the gate electrodes205.

The metal silicide regions218and the layer portions227P,227N may be formed on the basis of well-established recipes, wherein, during the formation of the layers227P,227N, process parameters, such as deposition temperature, ion bombardment, pressure and the like, may be varied to obtain the required type of intrinsic stress. Furthermore, respective masking schemes may be applied to first form one of the layers227P,227N and subsequently remove an unwanted portion thereof and thereafter form the other of the portions227P,227N, followed by the removal of an unwanted portion thereof. Consequently, the device200may be formed to have a high degree of strain with the respective channel regions203, which may be selected to be different at least in one of magnitude and type for the first and second transistors250p,250n, wherein the position of the respective strained semiconductor materials214p,214nmay be selected individually, which may be highly advantageous for SOI-like transistor architectures, as shown inFIGS. 2a-2i, since here a depth of the strained semiconductor material214p,214nmay be restricted due to the restricted thickness of the layer202, of which a significant portion has to be maintained for the respective epitaxial growth processes213,215. Hence, for a reduced thickness of the semiconductor layer202, as may be required for fully and partially depleted SOI transistors in advanced applications, nevertheless an efficient strain-inducing mechanism may be obtained due to the close proximity of the strained semiconductor materials214p,214nto the respective channel regions203, wherein an individual positioning may be accomplished by the above-described process sequence.

With reference toFIGS. 3a-3d, further illustrative embodiments of the present invention will be described in more detail, wherein process complexity for selective epitaxial growth processes for different types of transistors may be reduced by providing at most one growth mask that is formed on the basis of lithography, while other growth masks may be formed in a highly efficient manner.

FIG. 3aschematically illustrates a semiconductor device300at an intermediate manufacturing stage. The device300comprises a first transistor350pand a second transistor350n, which may be formed above a substrate301having formed thereon a respective semiconductor layer302. Moreover, the first and second transistors350p,350nmay comprise respective gate electrodes305covered by capping layers309and sidewall spacers306, possibly in combination with a respective liner307. Moreover, respective gate insulation layers304may be provided between the gate electrodes305and respective channel regions303. Regarding the characteristics and any details for forming the device300as shown inFIG. 3a, the same criteria apply as previously explained with the corresponding components of the devices100and200. Moreover, in this manufacturing stage, the first transistor350pmay have formed adjacent to the channel region303a respective recess311and a growth mask312to cover the first transistor350pwhile exposing the second transistor350nto a deposition ambient of a selective epitaxial growth process313. In one illustrative embodiment, the mask312may be provided in the form of a silicon dioxide mask, while in other embodiments any other appropriate materials may be used.

Consequently, during the selective epitaxial growth process313, a deposition of semiconductor material on the mask312is substantially suppressed, while a corresponding strained semiconductor material314N may grow within a corresponding recess formed in the second transistor350n. Regarding any specifics of the growth process313and the strained semiconductor material314N, the same criteria apply as previously explained with reference to the devices100and200. For instance, the strained semiconductor material314N may comprise a silicon/carbon mixture, at least partially, so as to provide an intrinsic tensile strain when the semiconductor layer302is a silicon layer. In one illustrative embodiment, the strained semiconductor material314N may be provided with a specific excess height314H, which may be used for converting material therein into a dielectric capping layer in a later stage. Moreover, in some illustrative embodiments, the material corresponding to the excess height314H may be provided in the form of a silicon material, when the presence of a non-silicon species may be considered inappropriate for the further processing of the material representing the excess height314H. It should be noted that the excess height314H may not necessarily represent an additional height with respect to a substantially flush transistor configuration and may also accommodate any recessed or raised configurations of the finally obtained strained semiconductor material314N.

FIG. 3bschematically illustrates the semiconductor device300subjected to a surface modification process330, acting on the exposed semiconductor material314N. For instance, in one illustrative embodiment, the modification process330may represent a nitridation process for selectively forming a respective nitrogen-enriched surface on the strained semiconductor material314N. As previously explained, the excess height314H may be provided to represent a surface portion of the material314N, which may be available for a conversion into a dielectric capping layer, such as a silicon nitride-like layer331, that may be formed during the process330. For example, as previously explained, the material314N may be provided in the form of a silicon/carbon mixture so that the corresponding nitridation process330may result in a corresponding silicon nitride layer including a certain amount of carbon. In still other illustrative embodiments, the excess height314H may be formed substantially of pure silicon, irrespective of the type of material previously deposited during the epitaxial growth process313, so as to provide enhanced process flexibility with respect to the material314N. For example, if a silicon/germanium mixture has been grown in the second transistor element350n, which may require a substantial amount of germanium, the additional excess height314H may nevertheless provide the required conditions so as to effectively form the silicon nitride-based material331. During the process330, the mask312, when, for instance, comprised of silicon dioxide, may be affected significantly less by the process330compared to the material314N so that a high degree of etch selectivity between the material331and the mask layer312may still be achieved. Consequently, during a subsequent highly selective etch process, the mask312may be removed on the basis of well-established etch recipes, while the gate electrode305and the regions314N may be effectively protected by the layer331, the capping layer309and the spacers306. Consequently, the mask312may be formed on the basis of a lithography process so as to act as a growth mask during the process313and may also act as a mask for forming the layer331, which, in turn, may act as an epitaxial growth mask in a further growth process for forming a respective strained semiconductor material in the first transistor350p. In the illustrative embodiments described above, the mask312may also be removed without any further lithography processes by using the high etch selectivity between the material331and the mask302. In other embodiments, the mask312may be removed on the basis of a corresponding resist mask (not shown) covering the second transistor350n, when an exposure of this transistor is considered inappropriate during the removal of the mask312.

FIG. 3cschematically illustrates the semiconductor device300after the completion of the above-described process sequence and during a further selective epitaxial growth process315for forming a strained semiconductor material314P in the first transistor350p. During the process315, the material layer331may act as an efficient growth mask, thereby substantially avoiding any material deposition thereon. With respect to the epitaxial growth process315and the strained semiconductor material314P, the same criteria apply as previously explained with reference to the devices100and200.

FIG. 3dschematically illustrates the semiconductor device300after the selective removal of the cap layers309, the spacers306and the layer331. As previously explained, highly selective wet chemical etch processes for silicon nitride-based materials are well established in the art and may be used for this purpose. Consequently, the strained materials314P,314N may be formed on the basis of two selective epitaxial growth processes, wherein a reduced process complexity is obtained, since at least one epitaxial growth mask, i.e., the layer331, may be formed in a highly local fashion without requiring an additional lithographical patterning process. Furthermore, the removal of the “growth mask”331may be performed in a common etch process for removing the spacers306and the capping layer309, thereby also significantly contributing to a reduced process complexity. Based on the device as shown inFIG. 3d, the further processing may be continued by forming respective drain and source regions, based on respective spacer techniques, as is also described with reference to the devices100and200.

With reference toFIGS. 4a-4c, further illustrative embodiments will now be described in which a reduced process complexity is achieved by commonly forming a first strained material in two different transistors and subsequently selectively removing an unwanted portion thereof during the patterning of a respective growth mask.

FIG. 4aschematically illustrates a semiconductor device400including a first transistor450pand a second transistor450nin an advanced manufacturing stage. Each of the transistors450p,450nmay comprise a gate electrode405formed on a respective gate insulation layer404that separates the gate electrodes405from respective channel regions403. Moreover, the gate electrodes405are encapsulated by respective spacers406and capping layers409, wherein a spacer layer426A, possibly in combination with a liner427A, is also formed to cover both transistors450p,450n. The transistors450p,450nmay be formed in and on a respective semiconductor layer402located above a substrate401. With respect to the various components described so far, the same criteria apply as explained before with respect to the same components of the devices100,200and300. Moreover, in this manufacturing stage, the device400comprises a first strained semiconductor material414N formed in respective recesses positioned next to the corresponding channel regions403. With respect to the characteristics of the material414N, the same criteria apply as previously explained. Furthermore, a mask412may be provided to cover the second transistor450nwhile exposing the first transistor450p. The mask412may represent a resist mask or any other appropriate material.

The device400may be formed by the following manufacturing processes. After the formation of the respective gate electrodes405including the spacers406, based on processes as are previously described, respective recesses may be formed by an appropriate etch process, as is also described with reference toFIG. 1dwhen describing the formation of the recesses111. Thereafter, a selective epitaxial growth process may be performed to form the material414N in the correspondingly etched recesses, wherein, during the etch process for forming the recesses and the subsequent epitaxial growth process, a high degree of process uniformity is achieved, since any micro and/or macro loading effects during the etch process and the epitaxial growth process may be significantly reduced as these processes may be performed without masks that may cover extended substrate areas when protecting respective transistors. Consequently, high controllability of the etch process and the subsequent epitaxial growth process may be achieved. Thereafter, the spacer layer426A, possibly in combination with the liner427A, may be deposited on the basis of well-established recipes followed by the formation of the mask412on the basis of lithography techniques. Thereafter, the layer426A may be patterned on the basis of the mask412, wherein, in some illustrative embodiments, a corresponding etch process may be continued so as to also remove the material414N in the first transistor450p. In other illustrative embodiments, the layers426A and427A may be patterned on the basis of the mask412, which may then be removed by any appropriate techniques, such as oxygen plasma-based removal processes.

FIG. 4bschematically illustrates the device400after the completion of the above-described process sequence, when the layer426A is patterned on the basis of the mask412, which may then be removed, while, in a further etch process410, the material414N in the first transistor450pis removed, while the remaining layer426A reliably covers the second transistor450n. During the etch process410, the material414N may be efficiently removed to provide the recess411, while, in other embodiments, the etch process410may also be controlled with respect to shape and depth requirements of the recess411. That is, the etch process410may be performed so that an increased size, for instance an increased depth, of the recess411may be obtained, or, in other embodiments, an isotropic component may be used during the etch process410so as to also significantly modify the shape of the recess411. For convenience, any such change of shape, for instance by under-etching, is not shown.

FIG. 4cschematically illustrates the device400during a further selective epitaxial growth process415for forming a strained semiconductor material414P according to device requirements for the first transistor450p. During the process415, the remaining layer426A acts as a growth mask, as is previously described. Hence, a high degree of process flexibility is obtained, for instance with respect to different sizes and shapes of the strained semiconductor material portions414P,414N, while nevertheless a reduced process complexity is provided due to the usage of a single growth mask, i.e., the patterned layer426A. This may be accomplished by performing a common epitaxial growth process and subsequently removing an unwanted portion of the selectively grown material.

With reference toFIGS. 5a-5e, further illustrative embodiments will now be described in which differently strained semiconductor materials may be formed in a highly efficient manner.

InFIG. 5a, a semiconductor device500may comprise first and second transistors550p,550neach comprising a gate electrode505, a gate insulation layer504, a capping layer509and sidewall spacers506. Regarding these components, the same criteria apply as previously explained with reference to the devices100,200,300,400. Moreover, the device500may be subjected to a process540for defining growth areas adjacent to the respective gate electrodes505which are to receive respective strained semiconductor materials in a later stage. In one illustrative embodiment, the process540may represent an oxidation process during which exposed semiconductor portions may be oxidized, while an oxidation of the gate electrodes505is substantially suppressed by the spacers506and the capping layer509, which may be comprised of silicon nitride. Consequently, a respective oxidized portion511may be formed, wherein the size and shape of the portion511may substantially define the size and shape of a strained semiconductor material to be formed in a later stage. In other illustrative embodiments, the portions511may represent recesses which may be formed by isotropic or anisotropic etch processes, as previously described, wherein additionally an oxidation process may be performed to form an oxidized surface portion in the respective recesses. A corresponding process strategy may be advantageous, when the substantially isotropic behavior of the oxidation process540may be considered inappropriate for the form of the finally obtained strained semiconductor material.

FIG. 5bschematically shows the device500during a further advanced manufacturing stage, in which a mask512, such as a resist mask and the like, is formed in order to cover the first transistor550p, while exposing the second transistor550nto an etch ambient510. For example, a wet chemical etch process or a plasma-based etch process or a combination thereof may be performed to selectively remove oxidized material in the portions511of the second transistor550n. Consequently, the size and shape of the corresponding recesses511A may be defined in some embodiments by a highly controllable oxidation process, such as the process540, since the etch process510may have a high etch selectivity with respect to the semiconductor material of the layer502, thereby substantially not removing any material thereof. In some illustrative embodiments, the etch process510may also include any cleaning processes for removing any contaminants in order to prepare the device500for a subsequent selective epitaxial growth process. To this end, the mask512may be removed and an appropriate etch step may be performed to remove the contaminants as required.

FIG. 5cschematically illustrates the device500after a selective epitaxial growth process, thereby forming a strained semiconductor material514N while the material may not be substantially deposited on the first transistor550pdue to the encapsulation of the gate electrode505and the provision of the oxidized portion511. With respect to the characteristics of the material514N, the same criteria apply as previously explained. Moreover, in some illustrative embodiments, the material514N may be provided with an extra height514H so as to provide excess material that may be available for a surface modification as is also described with reference to the device300.

FIG. 5dschematically illustrates the device500during a corresponding surface modification process530, which, in one illustrative embodiment, may be configured as a nitridation process for selectively converting a portion of the material514N into a silicon nitride-like material. Consequently, the extra height provided in the previous selective epitaxial growth process may be efficiently used to form a nitrogen-enriched silicon material, which may have similar characteristics as a silicon nitride material. As previously explained, the extra height may be provided as a pure silicon material, as a silicon/carbon material and the like. Moreover, during the process530, a corresponding less effective surface modification of the oxidized portion511of the first transistor550pmay nevertheless result in a high etch selectivity with respect to a corresponding material531, as is previously explained. Consequently, the oxidized portion511may be efficiently removed, substantially without attacking the material514N, which is covered by the layer portion531.

FIG. 5eschematically illustrates the device500after the completion of the above-described process sequence and exposed to a further epitaxial growth ambient515for the formation of a respective strained material514P, which may have different characteristics compared to the material514N, similarly as is also described previously. Moreover, during the selective epitaxial growth process515, the layer portion531may act as a growth mask, thereby substantially suppressing any material deposition on the material514N. Thereafter, the layer531, as well as the spacers506and the capping layers509, may be removed in a common etch process, for instance on the basis of highly selective wet chemical etch recipes. Thereafter, the further processing may be performed as is previously described. Hence, a highly efficient and well-controllable technique is provided, in which differently strained semiconductor materials may be formed in different transistors while nevertheless a significantly reduced process complexity is achieved.

As a result, the present invention provides an enhanced technique for the formation of different transistor types each having a different type of strain in the respective channel region, wherein embedded strained semiconductor layers are provided, which may be formed individually for each different transistor type. Hereby, a reduced process complexity may be achieved by significantly reducing the required process steps, especially for the formation of respective growth masks. In some illustrative embodiments, a reduction of process complexity may be achieved by reducing the number of required growth masks by exposing a previously grown strained semiconductor material to a further epitaxial growth ambient so as to form a respective capping layer for the previously formed material. In still other illustrative embodiments, one growth mask may be formed on the basis of a lithographical patterning process, while further growth masks may be formed on the basis of “self-aligned” techniques. In other illustrative embodiments, a high degree of flexibility in positioning respective strained semiconductor layers for different transistor types may be accomplished, while nevertheless a reduced degree of complexity is provided, in that a differential disposable spacer approach is used. Hence, even for highly advanced transistor elements, such as fully or partially depleted SOI devices, an efficient strain engineering for different transistor types may be obtained.