Power amplifier module

A power amplifier module includes a first amplifier that amplifies an input signal to generate a first amplified signal and outputs the first amplified signal, a second amplifier that amplifies the first amplified signal to generate a second amplified signal and outputs the second amplified signal, and a matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier. The first amplifier is provided on a first chip, and the second amplifier is provided on a second chip. The matching network has an impedance transformation characteristic adjustable in accordance with a control signal.

This application claims priority from Japanese Patent Application No. 2016-147664 filed on Jul. 27, 2016. The content of this application is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a power amplifier module. A mobile terminal that uses a communication network for cellular phones includes a power amplifier module having multiple stages of amplifiers for amplifying power of a radio frequency (RF) signal to be transmitted to a base station. For example, Japanese Unexamined Patent Application Publication No. 2006-180151 discloses a power amplifier module in which a comparatively low cost laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) is used for a drive stage and a comparatively high efficiency heterojunction bipolar transistor (HBT) is used for a power stage.

In a power amplifier module, typically, a matching network is disposed between an output terminal of the drive stage and an input terminal of the power stage for matching the output impedance of the drive stage and the input impedance of the power stage. Impedance matching between different semiconductor chips may not result in the realization of the desired impedance due to a change in the ground condition of each semiconductor chip, depending on the arrangement positions of the semiconductor chips, and so on, which hinders high-accuracy impedance matching. Due to this problem, the module disclosed in Japanese Unexamined Patent Application Publication No. 2006-180151 has a problem in that the absence of high-accuracy impedance matching between stages of amplifiers results in an increase in the transmission loss of an RF signal.

BRIEF SUMMARY

Accordingly, the present disclosure provides a power amplifier module that achieves high-accuracy impedance matching while keeping costs low.

According to preferred embodiments of the present disclosure, a power amplifier module includes a first amplifier that amplifies an input signal to generate a first amplified signal and outputs the first amplified signal, a second amplifier that amplifies the first amplified signal to generate a second amplified signal and outputs the second amplified signal, and a matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier. The first amplifier is provided on a first chip, and the second amplifier is provided on a second chip. The matching network has an impedance transformation characteristic adjustable in accordance with a control signal.

According to preferred embodiments of the present disclosure, a power amplifier module that achieves high-accuracy impedance matching while keeping costs low can be provided.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described in detail hereinafter with reference to the drawings. The same or substantially the same elements are assigned the same numerals or symbols and are not described redundantly herein.

FIG. 1illustrates a configuration of a power amplifier module100according to an embodiment of the present disclosure. The power amplifier module100is included in, for example, a mobile communication device such as a cellular phone, and is configured to amplify a radio frequency (RF) signal that is an input signal and to output the amplified signal. The input signal has a frequency of the order of several gigahertz (GHz), for example.

As illustrated inFIG. 1, the power amplifier module100includes, for example, a power amplification circuit102, a switch circuit104, and a control circuit106. The power amplification circuit102includes amplifiers110and111, matching networks (MN)120,121, and122, and power supply lines130and131. The configuration of the power amplifier module100is not limited to that illustrated inFIG. 1, and the power amplifier module100may have any other configuration.

The amplifiers110and111form two stages of amplifiers. The amplifier110(first amplifier) amplifies an input signal RFin and outputs an amplified signal RFamp1(first amplified signal). The amplified signal RFamp1is supplied to the amplifier111via the matching network121. The amplifier111(second amplifier) amplifies the amplified signal RFamp1and outputs an amplified signal RFamp2(second amplified signal). The amplifiers110and111are supplied with a predetermined power supply voltage Vcc via the power supply lines130and131, respectively. The amplifiers110and111are also supplied with a bias current or bias voltage from a bias circuit (not illustrated). The number of stages of amplifiers is not limited to two and three or more stages of amplifiers may be formed.

The matching networks120,121, and122are disposed prior to the amplifier110and prior to and subsequent to the amplifier111, respectively, and are each configured to match impedance between circuits.

The power supply lines130and131are disposed between a power supply circuit (not illustrated) and the amplifier110and between the power supply circuit and the amplifier111, respectively, and are each configured to suppress leakage of an RF signal into the power supply circuit.

The amplified signal RFamp2output from the amplifier111is supplied to the switch circuit104via the matching network122. The switch circuit104outputs an output signal RFout from any one of a plurality of output terminals thereof in accordance with the frequency band of the RF signal. The output signal RFout output from the switch circuit104is transmitted to a base station via an antenna (not illustrated).

The control circuit106supplies control signals cont1and cont2corresponding to the frequency band of the input signal RFin to the matching networks121and122, respectively. The control signals cont1and cont2are signals for controlling the impedance transformation characteristics of the matching networks121and122, respectively. The adjustment of the impedance transformation characteristics for the matching networks121and122will be described below.

FIG. 2illustrates an example configuration of the power amplifier module100(a power amplifier module100A) according to an embodiment of the present disclosure. The power amplifier module100A includes a complementary metal-oxide semiconductor (CMOS) chip200and an HBT chip300. In the power amplifier module100A illustrated inFIG. 2, the control circuit106illustrated inFIG. 1is not illustrated.

The CMOS chip200(first chip) is a chip having integrated thereon elements including a field-effect transistor (a metal-oxide-semiconductor field-effect transistor (MOSFET)). The MOSFET on the CMOS chip200constitutes the amplifier110in a drive stage. CMOS chips are less expensive and have higher noise performance than HBT chips.

The HBT chip300(second chip) is a chip having integrated thereon elements including an HBT. The HBT on the HBT chip300constitutes the amplifier111in a power stage. Since HBT chips are capable of withstanding higher voltages than CMOS chips, it is preferable to use an HBT chip for the power stage with higher output power than the drive stage. In this manner, the amplifiers110and111in the two stages are formed on semiconductor chips constructed by using different processes. Thus, a power amplifier module having excellent noise performance and voltage-withstand capability with reduced manufacturing cost can be provided.

The CMOS chip200and the HBT chip300preferably have a bump structure. The bump structure allows connection between bumps by using an inductor formed as a pattern on a substrate. Different from a wire bonding structure, the bump structure does not cause coupling between wires, resulting in it being likely to ensure characteristics. In addition, no wire sweep occurs when a chip is molded (sealed), resulting in reduced variations and improved quality.

The matching network120includes a capacitor C1and an inductor L1. The capacitor C1has a first end supplied with the input signal RFin, and a second end connected to an input terminal of the amplifier110. The inductor L1has a first end connected to the first end of the capacitor C1, and a second end grounded. For example, the matching network120is disposed prior to the amplifier110on the CMOS chip200to remove the direct-current components from the input signal RFin.

The matching network121includes capacitors C2, C3, and C4and an inductor L2. The capacitor C2has a first end supplied with the power supply voltage Vcc, and a second end connected to an output terminal of the amplifier110. The capacitor C3has a first end connected to the output terminal of the amplifier110, and a second end connected to a first end of the inductor L2. The capacitor C4has a first end connected to the second end of the capacitor C3, and a second end grounded. The inductor L2has a first end connected to the second end of the capacitor C3, and a second end connected to an input terminal of the amplifier111. The matching network121is disposed between the amplifier110(drive stage) and the amplifier111(power stage) and is configured to match the output impedance of the amplifier110and the input impedance of the amplifier111. All of the constituent elements of the matching network121may be provided on the CMOS chip200, or some constituent elements (for example, the capacitors C2, C3, and C4) may be provided on the CMOS chip200and the remaining constituent element or elements (for example, the inductor L2) may be provided outside the CMOS chip200. In this case, the element or elements not provided on the CMOS chip200may be provided directly on a substrate. The inductor L2may be formed as a pattern on the substrate or as a surface mount device (SMD), for example.

The matching network122(an output matching network) includes capacitors C5, C6, C7, and C8and inductors L3and L4. The capacitor C5has a first end connected to an output terminal of the amplifier111, and a second end grounded. The capacitor C6has a first end connected to a second end of the inductor L3, and a second end grounded. The capacitor C7has a first end connected to a second end of the inductor L4, and a second end grounded. The capacitor C8has a first end connected to the second end of the inductor L4, and a second end connected to an input terminal of the switch circuit104. The inductor L3has a first end connected to the first end of the capacitor C5, and a second end connected to the first end of the capacitor C6. The inductor L4has a first end connected to the first end of the capacitor C6, and a second end connected to the first end of the capacitor C7. The matching network122is disposed between the output terminal of the amplifier111and the input terminal of the switch circuit104(i.e., the circuit subsequent to the amplifier111) and is configured to match the output impedance of the amplifier111and the input impedance of the switch circuit104. All of the constituent elements of the matching network122may be provided on the CMOS chip200, or some constituent elements (for example, the capacitors C7and C8) may be provided on the CMOS chip200and the remaining constituent element or elements (for example, the capacitors C5and C6and the inductors L3and L4) may be provided outside the CMOS chip200.

The power supply line130includes an inductor L5and a capacitor C9, and the power supply line131includes an inductor L6and a capacitor C10. The inductors L5and L6have first ends to which the power supply voltage Vcc is applied, and second ends from which power supply is provided to the amplifiers110and111, respectively. The capacitors C9and C10have first ends connected to the first ends of the inductors L5and L6, respectively, and second ends grounded. In this embodiment, the power supply line130and the switch circuit104are provided on the CMOS chip200, and the power supply line131is provided outside the CMOS chip200.

A description will now be given of the function of adjusting the impedance transformation characteristics for the matching networks121and122. A power amplification circuit having multiple stages of amplifiers typically needs impedance matching between amplifiers since the output impedance (for example, approximately 20 to 30Ω) of the amplifier110and the input impedance (for example, approximately 3Ω) of the amplifier111are not equal. In a configuration in which a drive-stage amplifier and a power-stage amplifier are provided on different chips, it is difficult to match the impedances of both amplifiers, compared with a configuration in which both amplifiers are provided on the same chip. The reason for this is that a configuration in which both amplifiers are provided on different chips makes variations in constituent elements (such as capacitors or inductors) on the respective chips less uniform than the configuration in which both amplifiers are provided on the same chip. Another reason is that the use of a plurality of chips may cause variations in mounting when a module is assembled.

This embodiment enables adjustment of the impedance transformation characteristics of the matching networks121and122in accordance with the control signals cont1and cont2output from the control circuit106, respectively. Specifically, for example, the capacitors C2, C3, and C4in the matching network121are assumed to be capacitors whose capacitances are adjustable (first variable capacitor) (a capacitor whose capacitance is adjustable is hereinafter also referred to as a “variable capacitor”). Accordingly, the capacitances of the capacitors C2, C3, and C4are controlled in accordance with the control signal cont1, and the impedance transformation characteristics of the matching network121are adjusted. Thus, high-accuracy matching is achievable between the output impedance of the amplifier110provided on the CMOS chip200and the input impedance of the amplifier111provided on the HBT chip300. In the matching network122, likewise, for example, the capacitor C7is assumed to be a variable capacitor (second variable capacitor). Accordingly, the capacitance of the capacitor C7is controlled in accordance with the control signal cont2, and the impedance transformation characteristics of the matching network122are adjusted. Thus, high-accuracy matching is achievable between the output impedance of the amplifier111provided on the HBT chip300and the input impedance of a circuit subsequent to the amplifier111and provided on the CMOS chip200(for example, the switch circuit104).

FIG. 3illustrates an example configuration of a variable capacitor. A variable capacitor400illustrated inFIG. 3has an example configuration applicable to a capacitor shunt-connected to a signal path, such as the capacitor C4or C7illustrated inFIG. 2. The variable capacitor400includes, for example, capacitors410,411,412,413, and414and MOSFETs421,422,423, and424.

The capacitors410(first capacitor),411(second capacitor),412,413, and414have first ends connected to one another. The capacitor410has a second end grounded. The capacitors411to414are connected in series with the MOSFETs421to424, respectively. The MOSFETs421to424have drains connected to second ends of the capacitors411to414, respectively, gates respectively supplied with control voltages v1to v4(control signals) from the control circuit106, respectively, and sources grounded.

The capacitors410to414may be capacitors having different capacitances, for example. The MOSFETs421to424have a function as switches whose on and off states are switched in accordance with the control voltages v1to v4supplied from the control circuit106, respectively. Specifically, for example, when the control voltage v1is a comparatively high voltage, the MOSFET421(switch) is turned on and electric charge is accumulated in the capacitor411. When the control voltage v1is a comparatively low voltage, the MOSFET421(switch) is turned off and no electric charge is accumulated in the capacitor411. In this way, the combination of the on or off states of the MOSFETs421to424is controlled by using the control voltages v1to v4to achieve the adjustment of the combined capacitance of the capacitors410to414.

In this embodiment, four capacitors are controlled by the control circuit106, and 16-level adjustment is achieved, by way of example. However, the number of capacitors to be controlled is not limited to this number. One, two, or three capacitors may be controlled, or five or more capacitors may be used. InFIG. 3, furthermore, the switches are each formed by an N-channel MOSFET, by way of example. However, the configuration of the switches is not limited to that illustrated inFIG. 3, and each of the switches may be a P-channel MOSFET or any other element having a switching function.

With the configuration described above, in the power amplifier module100A, the impedance transformation characteristics for the matching networks121and122are dynamically adjusted in accordance with the frequency band of the input signal RFin. This makes impedance matching feasible with high accuracy even between different semiconductor chips while reducing cost.

Noise characteristics are determined in accordance with the performance of the drive stage. In this embodiment, the drive stage is constituted by a MOSFET having better noise performance than an HBT. This configuration improves the noise performance, compared with a power amplification circuit in which the drive stage is constituted by an HBT.

InFIG. 2, all of the capacitors C2, C3, and C4included in the matching network121are variable capacitors, by way of example. However, capacitors implemented as variable capacitors are not limited to the capacitors C2, C3, and C4. For example, any one or two of the capacitors (for example, the capacitors C3and C4) may be variable capacitors and the remaining capacitor or capacitors (for example, the capacitor C2) may have a fixed capacitance. Alternatively, the inductor L5in the power supply line130may be a variable inductor. In terms of design flexibility, three or more elements out of the four elements, namely, the capacitors C2, C3, and C4and the inductor L5, are preferably variable, and more preferably all of the four elements are variable.

InFIG. 2, furthermore, the capacitor C7, which is closer to the switch circuit104among the plurality of capacitors included in the matching network122, is a variable capacitor, by way of example. However, a capacitor implemented as a variable capacitor is not limited to the capacitor C7, and any other capacitor (for example, the capacitor C5, C6, or the like) may be variable. It is preferable that a capacitor close to the switch circuit104be variable for the following two reasons. First, since an element of the matching network122closer to the switch circuit104has a higher output impedance (for example, the switch circuit104has an output impedance of approximately 50Ω), the use of a variable capacitor as a capacitor closer to the switch circuit104enables more reduction in the effect of the variable capacitor on resistance. Second, if a circuit or the like is connected to the tip of an output terminal of the matching network122, the use of a variable capacitor as a capacitor closer to the switch circuit104facilitates adjustment.

In addition, the configuration of the matching networks121and122is not limited to that illustrated inFIG. 2. When each of the matching networks121and122includes an inductor, the inductors may be formed of variable inductors whose inductances are adjustable (first variable inductor and second variable inductor) to adjust the impedance transformation characteristics of the matching networks121and122.

FIG. 4schematically illustrates an example chip arrangement in a power amplifier module1000according to an embodiment of the present disclosure. For convenience of illustration, elements of the power amplifier module1000corresponding to the elements illustrated inFIG. 1 or 2are assigned numerals similar to those inFIG. 1 or 2. For convenience of illustration, furthermore, only the following elements among the elements included in the power amplifier module1000are illustrated inFIG. 4, and the remaining elements are not illustrated inFIG. 4.

The power amplifier module1000includes power amplification circuits that support two input signals RFin_a and RFin_b conforming to different communication standards (modes) or having different frequency ranges (bands). Each of the power amplification circuits has the configuration illustrated inFIG. 1. Specifically, the power amplifier module1000includes an amplification path for amplifying the input signal RFin_a and outputting an output signal RFout_a, and an amplification path for amplifying the input signal RFin_b and outputting an output signal RFout_b. These two amplification paths have similar configurations and, in the following description, the configuration of the path for the input signal RFin_a is taken as an example. Note that the power amplifier module1000may not necessarily include two amplification paths, and may include one or more than two amplification paths.

The power amplifier module1000includes a CMOS chip200(first chip) and an HBT chip300a(second chip), each having substantially a rectangular shape. An input terminal Ta to which the input signal RFin_a is supplied is arranged on a side s1(first side) of the CMOS chip200. An amplifier110a(first amplifier) is arranged on the CMOS chip200near the side s1. A matching network121ais arranged in an area adjacent to the amplifier110a. That is, a variable capacitor included in the matching network121a(for example, the capacitors C2, C3, and C4illustrated inFIG. 2) is provided in this area.

The HBT chip300a(second chip) is arranged in a neighboring area of the CMOS chip200near a side s2(second side) of the CMOS chip200, which is perpendicular to the side s1.

The elements included in a matching network122a(namely, a capacitor C5a, an inductor L3a, a capacitor C6a, and an inductor L4a) are arranged within a neighboring area of the CMOS chip200in order from the one nearest to the HBT chip300a.

A capacitor C7aincluded in the matching network122ais arranged in a portion of the CMOS chip200near a side s3(third side) of the CMOS chip200opposite the side s1. A switch circuit104ais arranged in an area adjacent to the matching network122aon the CMOS chip200at a position near the side s3.

The control circuit106is arranged substantially in a center portion of the CMOS chip200. Specifically, the control circuit106is arranged between the matching network121aand the capacitor C7a(i.e., between the amplifier110aand the switch circuit104a).

With the arrangement described above, in the power amplifier module1000, the input signal RFin_a is input to the CMOS chip200through the side s1, and is amplified by the amplifier110a(first amplifier). The amplified signal (first amplified signal) from the amplifier110ais input from the CMOS chip200to the HBT chip300athrough the side s2, and is amplified by an HBT (second amplifier). The amplified signal (second amplified signal) from the HBT chip300ais supplied again to the CMOS chip200through the side s2, and is output from the switch circuit104athrough the side s3.

In this embodiment, the elements included in the matching network122a, namely, the capacitor C5a, the inductor L3a, the capacitor C6a, and the inductor L4a, are arranged to be spaced a predetermined distance (for example, approximately 300 μm) away from the control circuit106included in the CMOS chip200. This arrangement allows the amplified signal to be transmitted along a path (for example, substantially U-shaped path) that bypasses the control circuit106(see a broken-line arrow inFIG. 4). This can reduce the effect of noise output from the control circuit106on an RF signal.

The amplifier110ais arranged on a side of the CMOS chip200opposite the switch circuit104awith the control circuit106interposed therebetween (i.e., the amplifier110ais arranged to be near the side s1). An amplifier111ais also arranged to be spaced a predetermined distance (for example, approximately 300 μm) away from the switch circuit104a. This arrangement can ensure isolation between the amplifiers110aand111aand the output signal RFout_a and reduce the effect of noise on the amplification of an RF signal.

An exemplary embodiment of the present disclosure has been described. The power amplifier modules100,100A, and1000include the amplifier110disposed on the CMOS chip200, the amplifier111disposed on the HBT chip300, and the matching network121between the amplifiers110and111, the matching network121having an impedance transformation characteristic adjustable in accordance with a control signal. Thus, a power amplifier module that achieves high-accuracy impedance matching even between different semiconductor chips while reducing cost can be provided.

In the power amplifier modules100,100A, and1000, the amplifier110in the drive stage is constituted by a MOSFET and the amplifier111in the power stage is constituted by an HBT. Thus, a power amplifier module having excellent noise performance and voltage-withstand capability with reduced manufacturing cost can be provided.

The power amplifier modules100,100A, and1000further include the control circuit106that outputs the control signals cont1and cont2in accordance with the frequency band of the input signal RFin to adjust the impedance transformation characteristics of the matching networks121and122. This allows the impedance transformation characteristics of the matching networks121and122to be dynamically adjusted in accordance with the frequency band of the input signal RFin.

While the configuration of the matching networks121and122is not limited to any specific one, the matching networks121and122may each include a variable capacitor or a variable inductor, for example.

In addition, as illustrated inFIG. 2, the variable capacitors or variable inductors included in the matching networks121and122may be provided on the CMOS chip200. The configuration of the variable capacitors or variable inductors is not limited to this.

In addition, each of the variable capacitors included in the matching networks121and122may include the capacitors410to414, which are connected in parallel, and the MOSFETs421to424(switches), which are connected in series with the capacitors411to414, respectively, and may be configured such that the capacitance of the variable capacitor is adjusted by switching between the on and off states of the MOSFETs421to424. The configuration of the variable capacitors is not limited to this.

The power amplifier modules100,100A, and1000further include, between the output terminal of the amplifier111and the input terminal of the subsequent switch circuit104, the matching network122having an impedance transformation characteristic adjustable in accordance with the control signal cont2. This configuration allows high-accuracy matching between the output impedance of the amplifier111and the input impedance of the subsequent circuit.

The power amplifier module1000further includes the switch circuit104a, which is provided on the CMOS chip200, and the control circuit106is arranged on the CMOS chip200between the amplifier110aand the switch circuit104a. This arrangement ensures isolation between the amplifiers110aand111aand the output signal RFout, and reduces the effect of noise on the amplification of an RF signal.

In the power amplifier module1000, furthermore, the input terminal Ta for the input signal RFin is arranged on the side s1of the CMOS chip200, the HBT chip300ais arranged near the side s2perpendicular to the side s1of the CMOS chip200, and the switch circuit104ais arranged near the side s3opposite the side s1of the CMOS chip200. This configuration allows an amplified signal to be transmitted along a path that bypasses the control circuit106, as illustrated inFIG. 4. This can reduce the effect of noise output from the control circuit106on an RF signal.

The embodiments described above are intended for easy understanding of the present invention, and it is not intended to construe the present invention in a limiting fashion. Various modifications and improvements can be made to the present invention without departing from the gist of the present invention, and equivalents thereof are also included in the present invention. That is, the embodiments may be appropriately modified in design by those skilled in the art, and such modifications also fall within the scope of the present invention so long as the modifications include the features of the present invention. For example, the elements included in the embodiments and the arrangement, materials, conditions, shapes, sizes, and the like thereof are not limited to those described in the illustrated examples but can be modified as appropriate. In addition, the elements included in the embodiments can be combined as much as technically possible, and such combinations of elements also fall within the scope of the present invention so long as the combinations of elements include the features of the present invention.