Methods and apparatus to implement a boundary scan for shared analog and digital pins

An example apparatus includes a buffer configured to, when enabled: obtain an input voltage; and provide the input voltage to a first boundary cell; and a second boundary cell configured to, when the apparatus is used in analog mode and a boundary scan occurs disable the buffer.

TECHNICAL FIELD

This description relates generally to integrated circuitry, and more particularly to methods and apparatus to implement a boundary scan for shared analog and digital pins.

BACKGROUND

A boundary scan is a protocol implemented on a system on chip (SoC) to test interconnects between printed circuit boards, chips, and/or integrated circuits (IC) to verify that the interconnects are working as intended. To facilitate a boundary scan, the printed circuitry boards, chips, and/or ICs include a test cell or boundary cell that is able to override functionality of a pin to drive values into an input and/or obtain values out of an output to verify the outputs correspond to intended values. The boundary scan protocol may be governed by a standard (e.g., the IEEE 1149.1 standard).

SUMMARY

For a boundary scan for shared analog and digital pins, an example integrated circuit includes an buffer including an input terminal, an output terminal, and an enable terminal, the output terminal of the buffer coupled to an input terminal of a first boundary cell: a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to a select terminal of a general purpose input output (GPIO); and a second boundary cell including an input terminal and an output terminal, the input terminal of the second boundary cell coupled to the output terminal of the logic gate and the output terminal of the second boundary cell coupled to the enable terminal of the buffer.

The same reference numbers or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features.

DETAILED DESCRIPTION

The drawings are not necessarily to scale. Generally, the same reference numbers in the drawing(s) and this description refer to the same or like parts. Although the drawings show regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended and/or irregular.

A boundary scan is used to verify that the interconnections between chips and/or circuits on a board are working correctly. A boundary scan may be performed during the manufacturing process, during initialization, and/or periodically, aperiodically, or based on a trigger after initialization. Because boundary scans may be governed by a standard, circuit designers may be limited in the implementation of a chip based on the boundary scan standard. Of particular note, a standard may have restrictions that impede boundary scan testing of pins that support both digital and analog functionality. For example, some standards preclude a circuit design from using a preamble sequence to differentiate between analog and digital operation of a pin. Accordingly, the boundary scan standard may provide hurdles in the configuration of a shared pin capable of operating in analog or digital.

In some designs for digital pins, an output buffer and an input buffer are used in conjunction with boundary cells to facilitate boundary scans for shared (analog and digital) pins. A boundary cell is a circuit that can override the functionality of the IC to cause the IC to obtain and/or output voltages as part of the boundary scan protocol. An output buffer is a buffer that is used to drive a voltage to an input output pin based on a signal from a first and second boundary cell and the input buffer is a buffer that is used to obtain a voltage from the input/output pin and forward the voltage to the second boundary cell. In some such designs, the output buffer is only enabled when the boundary scan protocol corresponds to instructions to drive the output buffer to output a voltage and the input buffer is always enabled. However, for a shared pin, the pin may be configured to operate in analog mode. When the pin is operating in analog mode, an input signal could be a low voltage (e.g., 0 volts (V)) a high voltage (e.g., 3.3 V) or any voltage in between (e.g., for an analog signal). During a boundary scan, shared pins implementing digital functionality are tested in digital mode. In some devices, the analog pins may not be covered as part of the boundary scan. If a shared pin were to simply add the input buffer and output buffer from the designs to implement boundary scan tests for digital pins and the shared pin was operating in analog mode, an analog voltage may be input into the pin at some voltage between the high and low voltages, thereby causing a through-current path to be created in the input buffer. For example, if the input buffer is driven to 1.7 V, depending on the state of the pins, there can be a current path that leads to significant leakage current on the pin. If the design includes multiple pins, a large amount of undesirable leakage current may occur.

Examples disclosed herein provide circuitry that enables boundary scan of a shared pin when in digital mode. In some examples, shared pins are excluded from boundary scan when the pins are in analog mode to avoid leakage current. Examples disclosed herein provide an additional boundary cell and logic circuitry that disables the input buffer during analog mode to avoid leakage current and enables the input buffer for boundary scans when in digital mode. Examples disclosed herein address boundary scan requirements for shared pins (e.g., corresponding to analog general purpose input outputs (AGPIO)) and abide by boundary scan standards with minimal circuitry and low overhead. Additionally, examples disclosed herein allow a user more control over the pin by allowing the user to select analog or digital mode for the pin while allowing boundary scans in digital mode and disabling boundary scans in analog mode.

FIG.1is a schematic diagram of an example circuit board100. The example circuit board100includes example ICs102,104,106,108, an example memory cluster110, example flash112, example cluster circuitry114, example connectors116, a test access port (TAP) controller117, and an example serial interconnect118. Although the example circuitry board100includes a configuration of four ICs and one cluster, the circuit board100may correspond to any configuration that utilizes interconnects between ICs and/or other circuitry.

The ICs102,104,106,108ofFIG.1include semiconductor components to perform one or more functions based on input data. Each IC102,104,106,108includes a number of input terminals for input data and a number of output terminals to output data. For example, the IC102includes multiple inputs and/or output terminals that are coupled to the IC108and/or the connectors116. However, the IC102may be connected with any other component on the circuitry board100. In the example ofFIG.1the interconnects between IC102and IC108are direct interconnects and the interconnects between IC104and106are via the cluster circuitry114. The cluster circuitry114may include additional components that are not part of an IC but may affect the value output by the IC104. The ICs102,104,106,108may access the memory cluster110and/or flash112(e.g., directly or via another IC).

Additionally, the ICs102,104,106,108are connected via the serial interconnect118. Each of the ICs102,104,106,108includes a TAP controller117to facilitate the boundary scan via the serial interconnect118. For example, a connected device (e.g., a test system connected via the connector116) can transmit one or more signals through the TAP controllers117via the serial interconnect118that causes boundary cells in each IC102to control the input and outputs of each IC102,104,106,108to verify that the inputs/outputs correspond to intended outputs based on the driven inputs. For example, the boundary scan may cause the TAP controller117to control a first boundary cell of the IC102to output a first value to the IC108and cause the TAP controller117to control a boundary cell in the IC108to verify that the obtained value corresponds to the instructed first value, thereby verifying whether there is an issue with the interconnect (e.g., if the obtained voltage does or does not match (e.g., by more than a threshold) the intended voltage or expected voltage). If there is circuitry between ICs (e.g., the cluster114between IC104,106), the device operating the boundary scan (e.g., the connected device coupled to connector116) would be aware of the circuitry and would predict the intended input based on the output of the first IC and the functionality of the cluster114. As further described below in conjunction withFIG.2, examples disclosed herein correspond to operation of a shared pin (e.g., input/output pin that can operate as an analog interface/terminal or a digital interface/terminal) that can be part of a boundary scan in both analog mode and digital mode that reduces leakage current. For example, the TAP controller117uses the boundary scan circuitry to override control of a shared interface that includes a shared pin to enable or disable an input buffer in the shared interface based on whether the shared pin is in analog mode or digital mode, as further described below in conjunction withFIG.2.

FIG.2is a schematic diagram of an example shared interface200that is connected to a shared pin of the IC102of the circuit board100ofFIG.1. However,FIG.2may be described in conjunction with any IC (e.g., IC104,106,108ofFIG.1and/or any other IC that has boundary scan functionality). The shared interface200includes an example digital data path201and an example analog data path202. The digital data path201includes circuitry for handling the digital values during a boundary scan while avoiding leakage current for analog values and the analog data path202includes circuitry for handling analog values. Additionally, the digital data path201and/or the analog data path202may include additional circuitry for handling digital values when not operating in boundary scan mode (e.g., normal operation), which is not shown inFIG.2. For example, the digital data path201may include a multiplexer (MUX) or other circuitry to control when the boundary scan circuitry is used and when the boundary scan circuitry is not to be used and the other circuitry is used during normal operation.

The shared interface200includes an example output buffer203, an example input buffer204, example boundary scan cells (BCs)206,208,210, an example general purpose input output (GPIO)212, example logic gates214,216,218, an example pad220(e.g., a shared pad or AGPIO pad), and an example analog pad222(e.g., an analog signal only pad). The example BC206is also referred to herein as the BC, the example BC208is also referred to herein as the BC and the BC210is also referred to herein as the BC. The pad220is coupled to the shared (e.g., AGPIO) pin of the IC102. Accordingly, signals may be obtained and/or transmitted via the pad220. Additionally or alternatively, analog signals may be obtained (e.g., via the analog pad222) and/or transmitted via the pad in the analog data path202. Although the components are illustrated as particular components, other components and/or combinations of components may be used to perform the same functionality as the illustrated components. For example, the enable terminal of the input buffer204may be replaced with a switch or transistor to connect or disconnect the voltage on the pull line into the pull terminal (Pl) of the buffer204(e.g., disconnecting the pull terminal may have the same function as sending a signal to the enable terminal).

In the example ofFIG.2, the output buffer203includes an input terminal coupled to the BC210, an output terminal coupled to the pad220; the input of the input buffer204; and the analog processing circuitry of the analog data path, and an inverted enable (e.g., power) terminal coupled to the output of the BC208. In some examples, the inverted enable may be a regular enable coupled to inverting circuitry (e.g., a NOT gate). The input buffer204includes an output terminal coupled to the BC210, an input terminal coupled to the pad220; the output of the output buffer203; and the analog processing circuitry of the analog data path, an enable (e.g., power) terminal coupled to the output of the BC206, and a pull terminal coupled to the output of the logic gate214. The BC206is coupled to the enable/power terminal of the input buffer204and the output of the logic gate216.

Additionally, the BC206includes an input terminal and output terminal for obtaining and transmitting a signal via the serial interconnect118ofFIG.1, as further described below in conjunction withFIG.4. The BC208is coupled to the inverted enable/power terminal of the output buffer203and the output of the logic gate218. Additionally, the BC208includes an input terminal and output terminal for obtaining and transmitting a signal via the serial interconnect118ofFIG.1, as further described below in conjunction withFIG.4. The BC210is coupled to the output of the input buffer204and the input of the output buffer203.

Additionally, the BC210includes an input terminal and output terminal for obtaining and transmitting a signal via the serial interconnect118ofFIG.1, as further described below in conjunction withFIG.4. The logic gate214(e.g., a logic OR gate) includes a first input terminal coupled to the pull terminal of the GPIO212, a second input terminal coupled to the AMSEL (analog or digital select) terminal of the GPIO212; the input of the logic gate216; and the first input of the logic gate218, and an output terminal coupled to the pull terminal of the input buffer204. The logic gate216(e.g., a logic NOT gate) includes an input terminal coupled to the AMSEL (analog or digital mode select) terminal of the GPIO212, the input of the logic gate214, and the first input of the logic gate218and an output terminal coupled to the BC206. The logic gate218(e.g., a logic OR gate) includes a first input coupled to the GZ terminal of the GPIO212, a second input terminal coupled to AMSEL terminal of the GPIO212; the second input of the logic gate214; and the input of the logic gate216; and an output terminal coupled to the BC208. The GPIO212outputs (e.g., provides) the AMSEL signal as a high voltage or a low voltage based on whether the shared interface200is to operate in analog mode or digital mode (e.g., which may be selected by a user, manufacturer, and/or by a boundary scan controller or protocol).

During normal or functional operation, a user or another device may select to have the shared interface200operate in analog mode or digital mode. When the shared interface200is to operate in digital mode the GPIO212, the GPIO212outputs (e.g., provides) a first value (e.g., ‘0’ or 0 V) from the AMSEL terminal to signify the digital mode. Accordingly, the logic gates214,216,218all obtain a low voltage or ‘0’ value. Accordingly, the pull terminal of the input buffer204is controlled by the pull terminal of the GPIO212(e.g., via the logic gate214) because the logic OR of (A) ‘0’ and (b) the value of pull will equal the value of pull. The pull terminal corresponds to the voltage output from the input buffer204when the input buffer204outputs (e.g., provides) a logic ‘1’ value. Additionally, the enable terminal of the output buffer203is controlled by GZ (e.g., via the output of the logic gate218) because the logic OR of (A) ‘0’ and (B) the value of GZ will equal the value of GZ. Additionally, the voltage at the enable terminal of the input buffer204will be high, thereby enabling the input buffer204for use during the digital boundary scan because the output of the logic gate216is high when the input it low and the BC206will output the high voltage to the enable terminal of the input buffer204. Control of the BC206is based on the signal on the serial interconnect118ofFIG.1and/or the output of the logic gate216as further described below in conjunction withFIG.4.

As described above, the GPIO212further outputs a pull voltage via the pull terminal to control the voltage output by the input buffer204. Additionally, the GPIO212outputs a low or high signal (e.g., ‘0’ or ‘1’, 0 V or 3.3 V, etc.) via the example GZ terminal to enable or disable the output buffer203. For example, if the GPIO212is a low signal, the logic gate218will output a low signal (e.g., 0V from GZ OR 0 V from AMSEL=0V), which, when inverted by the inverted enable terminal of the output buffer203will enable the output buffer203to drive an voltage out to the pad220. If the GPIO212is a high signal, the logic gate218will output a high signal (e.g., 3.3 V from GZ OR 0 V from AMSEL), which, when inverted by the inverted enable terminal of the output buffer203will disable the output buffer203. Accordingly, the GPIO212outputs a low voltage at the GZ terminal to drive a voltage to the pad220and outputs a high voltage to disable the output buffer203(e.g., so that the input buffer204can obtain a digital voltage from the pad220. Thus, during a functional digital mode, the input buffer204can be controlled based on the AMSEL signal. During a functional analog mode, the GPIO212outputs a second value (e.g., ‘1’ or 3.3 V) from the AMSEL terminal to signify analog mode. The second value is input into the logic circuitry214,216,218to control the buffers203,204.

When a boundary scan is to be performed, the GPIO212may lose control and/or output inconsistent values. Accordingly, during a boundary scan, the TAP controller117ofFIG.1takes control of the shared interface200using the example BCs206,208,210. The TAP controller117determines whether the shared interface200is operating in analog mode or in digital mode. When a boundary scan is to be performed and the pin is connected to an analog resource (e.g., corresponding to analog mode), the pin and corresponding shared interface200is not expected to be part of the digital boundary scan. As described above, in functional mode, the GPIO212outputs a second value (e.g., ‘1’ or 3.3 V) from the AMSEL terminal to signify the analog mode. However, the GPIO212cannot control the output value during the boundary scan mode. Thus, the TAP controller117will output instructions via a boundary scan chain which will scan in a value such that BC206cell will get a value of zero (e.g., 0 V). In response to obtaining the value of zero, the BC206will output 0 V, thereby causing the voltage at the enable terminal of the input buffer204to be low (e.g., 0 V), which disables the input buffer204for use during the boundary scan. In this manner, if an analog voltage is obtained from the pad220or output by another component during the boundary scan, the analog voltage will not cause leakage current through the input buffer204because the input buffer204will be disabled. When a boundary scan is to be performed and the pin is connected to a digital resource (e.g., corresponding to digital mode), the pin and corresponding shared interface200is expected to be part of the digital boundary scan. Thus, the TAP controller117will output instructions via a boundary scan chain which will scan in a value such that BC206cell will get a value of ‘1’ (e.g., 3.3 V). In response to obtaining the value of ‘1’, the BC206will output a ‘1’ (e.g., 3.3 V), thereby causing the voltage at the enable terminal of the input buffer204to be high (e.g., 3.3 V), which enabled the input buffer204for use during the boundary scan. Accordingly, the BC206facilitates the enable and disable of the input buffer during boundary scan (e.g., depending on whether the shared interface200is operating in digital mode or analog model) to allow the shared pin coupled to the shared interface200to operate in analog or digital mode and perform a boundary scan. The structure and functionality of the BC206is further described below in conjunction withFIG.4.

FIG.3is a schematic diagram of an alternative portion of one of the shared interface200ofFIG.2. The example portion of the shared interface200ofFIG.3includes the example output buffer203, the example input buffer204, the example BCs206,208,210, and the example logic gates216,218. Additionally, the alternative portion of the shared interface200ofFIG.3may include any of the components ofFIGS.2and/or1. Additionally, the example portion of the shared interface200ofFIG.3includes an example multiplexer (MUX)300.

The MUX300ofFIG.3includes a select (e.g., control) terminal, a first and second input terminal, and an output terminal. The first input terminal of the MUX300is coupled to another device (e.g., a core data register (CDR)) to obtain a design for testing (DFT) input enable (INENA) value. The second input terminal of the MUX300is coupled to the BC206. The output terminal of the MUX300is coupled to the enable terminal of the input buffer204. The select terminal of the MUX300is coupled to another device (e.g., the core data register (CDR)) to obtain a DFT INENA control (CTRL) value.

The MUX300ofFIG.3provides additional control of the input buffer204for a DFT mode. A DFT mode is used to test the signals within the IC102by toggling values throughout digital logic components of the IC102. Because the BC206includes flip flops (e.g., digital logic) the DFT mode will test those components as well. Accordingly, while testing the flip flops of the BC206, the output of the flip flop may toggle high and low, which will cause the input buffer204to toggle between enable and disable. If the toggling is fast enough, the toggling can degrade and/or damage the input buffer204. Accordingly, a component facilitating the DFT can, during a DFT, output a first value (e.g., logic ‘0’, 0 V, etc.) for the DFT INENA control value to the select terminal of the MUX300to cause the MUX to output the DFT INENA value to the enable terminal of the input buffer204, thereby avoiding the toggling output of the BC206while it is under DFT. When a DFT is not being performed, the component facilitating the DFT can output a second value (e.g., logic ‘1’, 3.3 V, etc.) for the DFT INENA control value to the select terminal of the MUX300to cause the MUX300to output the value output by the BC206to the enable terminal of the input buffer.

FIG.4is a schematic diagram of the BC206ofFIG.2. In some examples,FIG.4may be a schematic drawing of any of the BCs206,208,210ofFIG.2. The BC206includes an example MUXs400,406and example flip flops402,404. The example BC206is connected to the example TAP controller117(e.g., through the serial input connection (directly or indirectly), the clockdr connection, and theupdatedr connection). The BC206is also connected to the example GPIO212(e.g., via the logic gate216) and the enable terminal of the input buffer204, as further described above in conjunction withFIG.2.

The MUX400ofFIG.4includes a first input terminal408, a second input terminal410, a select terminal412, and an output terminal414. The first input terminal408of the MUX400is coupled to the GPIO212via the output of the logic gate216. The second input terminal410of the MUX400is coupled to a serial input line that is coupled to (e.g., directly or via one or more other BCs) the example TAP controller117. The select terminal412of the MUX400is coupled to the TAP controller117. The output terminal414of the MUX400is coupled to a first input terminal of the flip flop402. The flip flop402includes a first input terminal (D), a second input terminal (corresponding to clockdr) and an output terminal (Q). The second input terminal of the flip flop402is coupled to the TAP controller117. The output terminal of the flip flop402is coupled to a first input of the second flip flop404and a subsequent BC, the TAP controller117, or another IC. The second flip flop404includes a first input terminal (D), a second input terminal (corresponding to updatedr), and an output terminal (Q). The second input terminal of the flip flop404is coupled to the TAP controller117. The output of the flip flop404is coupled to a second input terminal of the second MUX406. The second MUX406includes a first input terminal416, a second input terminal418, a select terminal420, and an output terminal422. The first input terminal416is coupled to the GPIO212via the example logic gate216and the first input terminal of the MUX400. The second input terminal418is coupled to the output of the flip flop404. The select terminal420is coupled to the example TAP controller117. The output terminal422of the MUX406is coupled to the enable terminal of the example input buffer204ofFIG.2.

The example BC206supports BSCAN instructions including BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST, and HIGHZ. SAMPLE/PRELOAD is similar to the functional operation of the interface200ofFIG.2. The AMSEL input value driven from the design will be captured by the BC206. EXTEST is where the preloaded values (e.g., from the TAP controller117) are used to drive the BC206. For the EXTEST operation, BC206corresponds to the AGPIO with bscan support can be preloaded to ‘0’ for digital operation and the pin will behave according to the signal output by the GPIO212ofFIG.2. In HIGHZ all pins will be tristated by suitably controlling BC206.

As described above, during functional operation, the GPIO212ofFIG.2generates the AMSEL output which is used to control (e.g., enable or disable) the input buffer204ofFIG.2. Accordingly, the TAP controller117ofFIG.1outputs a first value (e.g., ‘0’ or 0 V) to the select terminal of the MUX406to cause the output of the GPIO212to control the input buffer204. However, when a boundary scan occurs, the TAP controller117outputs a second value (e.g., ‘1’ or 3.3V) to the select terminal of the MUX406to disable and/or override the GPIO control. Instead, control of the input buffer204is based on the serial input (e.g., which passes instructions output by the TAP controller117). Because the TAP controller117knows whether the shared interface200is configured for analog mode or digital mode, the instructions via the serial input will include a low value (e.g., if the shared interface200is in analog mode) or a high value (e.g., if the shared pin is in digital mode). The value is stored and output to the MUX406via the flip flops402,404. In this manner, the output of the MUX406corresponds to the instructions of the TAP controller117to disable the input buffer204during a boundary scan test when the shared interface200is in analog mode (e.g., because the output of the BC206is low) or to enable the input buffer204during a boundary scan test when the shared interface200is in digital mode (e.g., because the output of the BC206is high). The TAP controller117outputs values to the second input of the flip flops402404to ensure that the instruction (e.g., the low value or high value) for the shared interface200is output by the BC206of the shared interface206and other instructions for other interfaces are output by the respective BCs of the other interfaces (e.g., via the serial output).

FIG.5is an example flowchart500representative of instructions and/or functionality of the example share interface200ofFIG.2and/or a method corresponding to examples disclosed herein. The example flowchart500begins at block502when the example TAP controller117determines if a boundary scan test should occur. For example, the TAP controller117may initiate a boundary scan test, periodically, aperiodically and/or based on a trigger/instruction.

If the TAP controller117determines that the boundary scan test is not occurring (block502: NO), control continues to block512. If the TAP controller117determines that the boundary scan test is occurring (block502: YES), TAP controller117determines if the shared pin is connected to an analog or digital resource (e.g., if the shared pin is set to analog mode or digital mode) (block504). If the TAP controller117determines that the shared pin is connected to an analog resource (block:504: ANALOG), the TAP controller117controls the example BC206disables the input buffer204by sending a low voltage and/or ‘0’ to the enable terminal of the input buffer204(block506). For example, the BC206may obtain an instructions from the example TAP controller117ofFIG.1, via the serial input ofFIG.4. If the example BC206determines that the shared pin is set to digital mode (block:504: DIGITAL MODE), the TAP controller117controls the example BC206enables the input buffer204by sending a high voltage and/or ‘1’ to the enable terminal of the input buffer204(block506). At block510, the TAP controller117determines if the boundary scan is complete.

If the TAP controller117determines that the boundary scan is not complete (block510: NO), control returns to block504and the process is continued until the boundary scan is complete. If the TAP controller117determines that the boundary scan is complete (block510: YES), the example MUX300ofFIG.3determines if an internal test scan is occurring (block512). For example, a controller or a core data register may transmit a signal (e.g., a high voltage or a low voltage) to the select terminal of the MUX300when an internal scan is occurring. If the example MUX300determines that an internal scan is not occurring (block512: NO), control ends. If the example MUX300determines that an internal scan is occurring (block512: YES), the example MUX300removes boundary cell control over the input buffer (block514). For example, the MUX300may output (e.g., via the output terminal of the MUX300) a signal from a controller (e.g., from the first input terminal of the MUX300), as opposed to the signal from the BC206(e.g., from the second input terminal of the MUX300). As described above, the output terminal of the MUX300is coupled to the enable terminal of the input buffer204. Thus, by not outputting the signal from the BC206, the MUX300removes BC control over the input buffer204.

At block516, the example MUX300determines if the internal scan is complete (e.g., based on the signal at the select terminal of the MUX300from the controller). If the example MUX300determines that the internal scan is not complete (block516: NO), control returns to block516until the internal scan is complete. If the example MUX300determines that the internal scan is complete (block516: YES), the example MUX300returns BC control over the input buffer (block518) by outputting (e.g., via the output terminal of the MUX300) the signal from the BC206. As described above, the output terminal of the MUX300is coupled to the enable terminal for the input buffer204. Thus, by outputting the signal from the BC206, the MUX300returns BC control over the input buffer204.

In this description, the term “and/or” (when used in a form such as A, B and/or C) refers to any combination or subset of A, B, C, such as: (a) A alone: (b) B alone: (c) C alone; (d) A with B: (e) A with C: (f) B with C; and (g) A with B and with C. Also, as used herein, the phrase “at least one of A or B” (or “at least one of A and B”) refers to implementations including any of: (a) at least one A: (b) at least one B; and (c) at least one A and at least one B.

Example methods, apparatus and articles of manufacture described herein improve shared pins in ICs by facilitating the use of the share pin as analog or digital in regular mode, DFT mode, and/or boundary scan mode while reducing and/or eliminating leakage current during the boundary scan and/or avoiding damage to an input buffer during the DFT mode.

Numerical identifiers such as “first”, “second”, “third”, etc. are used merely to distinguish between elements of substantially the same type in terms of structure and/or function. These identifiers as used in the detailed description do not necessarily align with those used in the claims.

While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a metal-oxide-silicon FET (“MOSFET”) (such as an n-channel MOSFET, nMOSFET, or a p-channel MOSFET, pMOSFET), a bipolar junction transistor (BJT—e.g. NPN or PNP), insulated gate bipolar transistors (IGBTs), and/or junction field effect transistor (JFET) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor. While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate: (ii) incorporated in a single semiconductor package: (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.