Multiple chip package and IC chips

A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-313411, filed on Oct. 28, 2004, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1) Field of the Invention

The present invention relates to a multiple chip package that includes a plurality of integrated circuit (IC) chips enclosed in a single package, and the IC chips in the package.

2) Description of the Related Art

FIG. 1is a schematic of an internal configuration of a conventional horizontal multiple chip package. As shown inFIG. 1, in the horizontal multiple chip package, a logic chip1and a memory chip2are laid out horizontally. A clock signal CLK is supplied to the logic chip1from outside via an external clock input pad11. The logic chip1outputs an address signal, a control signal, and a data signal, in synchronism with the clock signal CLK. The logic chip1also outputs the clock signal CLK via a clock output pad12. The clock signal CLK is supplied to the memory chip2via a wire electrode31and a clock input pad21.

The memory chip2inputs the address signal, the control signal, and the data signal, and outputs the data signal, in synchronism with the clock signal CLK supplied from the logic chip1. A return clock signal CLK (hereinafter, “return clock signal ReCLK”) is supplied from the clock input pad21of the memory chip2to the logic chip1, via a wire electrode32and a return clock receiving pad13of the logic chip1. The logic chip1receives the data signal from the memory chip2in synchronism with the return clock signal ReCLK.

FIG. 2is a schematic of an internal configuration of a conventional stacked multiple chip package. As shown inFIG. 2, in the stacked multiple chip package, the logic chip1and the memory chip2are vertically stacked. Similarly to the horizontal multiple chip package, the clock signal CLK output from the clock output pad12is returned to the return clock receiving pad13of the logic chip1as the return clock signal ReCLK, via the clock input pad21.

In both of the horizontal multiple chip package shown inFIG. 1and the stacked multiple chip package shown inFIG. 2, the clock output pad12, output pads14of address signals and control signals, the return clock receiving pad13, and input/output pads15of data signals are all disposed along one side of the logic chip1. The clock input pad21, input pads22of address signals and control signals, and input/output pads23of data signals are all disposed along one side of the memory chip2. Clock trees16and17and a latch circuit18inside the logic chip1, and a clock tree24and a latch circuit25inside the memory chip2, respectively adjust the input timing and the output timing of the control signal, the address signal, and the data signal so that these timings become uniform.

In recent trend, the number of pins in the multiple chip package is increasing. This requires wider band width and higher clock frequency. Therefore, the adjustment of timing inside the logic chip1, the adjustment of timing inside the memory chip2, and the adjustment of timing between the chips become more difficult.FIG. 3is a schematic of an internal configuration of a conventional stacked multiple chip package having multiple pins.

As shown inFIG. 3, in the multiple-pinned logic chip1, the input/output pads15of data signals are disposed not only along a side (a right side inFIG. 3) on which the clock output pads12and the return clock receiving pads13are disposed but also along another side (a left side inFIG. 3). The clock signal CLK is supplied to the data output side of the latch circuit18connected to the input/output pads15at the left side, via the clock tree16of the clock signal CLK. The return clock signal ReCLK is supplied to the data input side of the latch circuit18connected to the input/output pad15, via the clock tree17of the return clock signal ReCLK.

In the multiple-pinned memory chip2, the input/output pads23of data signals are disposed not only along a side (the right side inFIG. 3) on which the clock input pads21are disposed but also along another side (the left side inFIG. 3). While the intermediate part of the clock tree24of the clock signal CLK is not shown inFIG. 3, the clock tree24is actually extended to the left side from the clock input pad21at the right side. The clock signal CLK is supplied to the latch circuit25connected to the input/output pads23at the left side, via the long clock tree24.

There is a memory control circuit configured as follows. In the memory control circuit, a data bus driver and a receiver are disposed in isolation. The data bus is connected from the driver of the data bus to the receiver. A memory module of a synchronous dynamic random access memory (SDRAM) is connected to the data bus. A clock signal line is connected to each SDRAM such that signal propagation delay times are equal, and a signal works as a synchronization signal for fetching data read by the receiver of the memory control circuit. Such a memory control circuit is disclosed in, for example, Japanese Patent Application Laid-open No. 2000-194594. According to a technology disclosed in this patent literature, a difference between the phase of the read data and the phase of the reading clock can be kept constant. Even when number of mounted SDRAM dual in line memory (DIMM) increases, timing margin between the read data and the reading clock can be maintained.

A semiconductor memory that includes internal circuits that operate following clock signals, and a plurality of independent clock input terminals that supplies the clock signals to the internal circuits of the semiconductor chips is disclosed in, for example, Japanese Patent Application Laid-open No. H3-198283. According to the technology disclosed in this patent literature, the length of a clock signal line within the semiconductor chips can be shortened. Therefore, impedance of the clock signal line becomes small, and a deviation of the clock signals due to positions on the semiconductor chips can be made smaller.

According to the above multiple chip package that includes the multiple pins, a delay of the clock signal CLK between the logic chip1and the memory chip2is small. However, the input/output timings of all the signals of the logic chip1are adjusted based on one clock signal CLK and one return clock signal ReCLK. The input/output timings of all the signals of the memory chip2are adjusted based on one clock signal CLK. Therefore, the wiring lengths of the clock trees16,17, and24within the chips1and2become long, and delays of the clock signal CLK and the return clock signal ReCLK within the chips1and2become large. On the other hand, when the clock frequency becomes high according to the increase in the number of pins, a timing window becomes small. Therefore, it becomes difficult to adjust timings.

SUMMARY OF THE INVENTION

It is an object of the present invention to solve at least the above problems in the conventional technology.

A multiple chip package according to one aspect of the present invention accommodates a plurality of integrated circuit chips, and includes a first integrated circuit chip that includes a clock output pad that outputs a clock signal; and a return clock receiving pad that receives a return signal based on the clock signal; and a second integrated circuit chip that includes a clock receiving pad to which the clock signal is supplied and that outputs the return signal. The clock output pad and the return clock receiving pad are arranged near a plurality of sides of the first integrated circuit chip, and the clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad.

A multiple chip package according to another aspect of the present invention accommodates a plurality of integrated circuit chips, and includes a first integrated circuit chip that includes a clock output pad that outputs a clock signal, and a return clock receiving pad that receives a return signal based on the clock output signal; and a second integrated circuit chip that includes a clock receiving pad to which the clock signal is supplied, and a dummy pad to which the clock signal is supplied, and that is not connected to an internal circuit. The clock output pad and the return clock receiving pad are arranged near a plurality of sides of the first integrated circuit chip. The clock input pad is electrically connected to the clock output pad that is arranged near one of the sides and the return clock receiving pad that is arranged near one of the sides, and the dummy pad is electrically connected to the clock output pad that is arranged near another of the sides and the return clock receiving pad that is arranged near another of the sides.

A multiple chip package according to still another aspect of the present invention accommodates a plurality of integrated circuit chips, and includes a first integrated circuit chip that includes a clock output pad that outputs a clock signal, and a return clock receiving pad that receives a return signal based on the clock output signal; a second integrated circuit chip that includes a clock receiving pad to which the clock signal is supplied; and a dummy pad that is arranged on a substrate of the multiple chip package. The clock output pad and the return clock receiving pad are arranged near a plurality of sides of the first integrated circuit chip. The clock receiving pad is electrically connected to the clock output pad that is arranged near one of the sides and the return clock receiving pad that is arranged near one of the sides, and The dummy pad is electrically connected to the clock output pad that is arranged near another of the sides and the return clock receiving pad that is arranged near another of the sides, without being connected to any other circuit.

A multiple chip package according to still another aspect of the present invention accommodates a plurality of integrated circuit chips, and includes a first integrated circuit chip that includes a clock output pad that outputs a clock signal, and a return clock receiving pad that receives a return signal based on the clock signal; a second integrated circuit chip that includes a plurality of clock receiving pads, to each of which the clock signal is supplied. The clock output pad is arranged near a plurality of sides of the first integrated circuit chip and the return clock receiving pad is arranged near one of the sides in the first integrated circuit pad. Each of the clock receiving pads is electrically connected to the clock output pad that is arranged near one of the sides, and one of the clock receiving pads is electrically connected to the return clock receiving pad.

An integrated circuit chip according to still another aspect of the present invention includes a clock output pad that outputs a clock signal; and a return clock receiving pad that receives a return signal based on the clock signal. The clock output pad and the return clock receiving pad are arranged near each of a plurality of sides of the integrated circuit chip.

An integrated circuit chip according to still another aspect of the present invention includes a clock output pad that outputs a clock signal; and a return clock receiving pad that receives a return signal based on the clock signal. The clock output pad is arranged near a plurality of sides of the integrated circuit chip, and the return clock receiving pad is arranged near one of the sides.

An integrated circuit chip according to still another aspect of poi includes a plurality of pad groups each of which includes a plurality of pads. An input and an output of a signal to and from each of the pad groups are controlled based on a clock signal for each of the pad groups.

An integrated circuit chip according to still another aspect of the present invention includes a clock receiving pad to which a clock signal is supplied from outside; a dummy pad to which the clock signal is supplied from the outside; an input circuit to which the clock receiving pad is connected; and a dummy input circuit that is not connected to an internal circuit. A configuration and a size of the dummy pad are same as those of the clock receiving pad, and a configuration and a size of the dummy input circuit are same as those of the input circuit. The dummy pad is connected to the dummy input circuit.

DETAILED DESCRIPTION

Exemplary embodiments of a multiple chip package and IC chips according to the present invention will be explained below in detail with reference to the accompanying drawings. Although not limited thereto, a first IC chip is a logic chip and a second IC chip is a memory chip. The multiple chip package in each embodiment has a structure such that the logic chip and the memory chip are stacked. In the explanations of each embodiment and the accompanying drawings, like constituent elements are designated by like reference signs, and redundant explanations therefor will be omitted.

FIG. 4is a schematic of a multiple chip package according to a first embodiment of the present invention. As shown inFIG. 4, a clock output pad42that outputs the clock signal CLK, a return clock receiving pad43that receives the return clock signal ReCLK, plural output pads44that output an address signal and a control signal, and plural input/output pads45that input/output data signals are disposed respectively, along the right side of a logic chip4.

An output buffer circuit49is connected to the clock output pad42. An input buffer circuit60is connected to a return clock receiving pad43. A latch circuit48is connected to each output pad44via an output buffer circuit49. An output side latch circuit62and an input side latch circuit63are connected to each input/output pad45, via an input/output buffer circuit61. The latch circuit48, the output side latch circuit62, and the input side latch circuit63are connected to an internal circuit (not shown) of the logic chip4.

A clock output pad52, a return clock receiving pad53, plural output pads54, and plural input/output pads55are disposed respectively, along the left side of the logic chip4. An output buffer circuit59is connected to the clock output pad52. An input buffer circuit65is connected to the return clock receiving pad53. A latch circuit58is connected to each output pad54, via the output buffer circuit59. An output side latch circuit67and an input side latch circuit68are connected to each input/output pad55, via an input/output buffer circuit66. The latch circuit58, the output side latch circuit67, and the input side latch circuit68are connected to an internal circuit (not shown) of the logic chip4.

An external clock input pad41to which the clock signal CLK of a clock frequency of27megahertz, for example, is input from an external signal generator (not shown) is provided in the logic chip4. A trunk line40of a clock tree for the clock signal CLK (hereinafter, “CLK clock tree”) is connected to the external clock input pad41, via an input buffer circuit50and a phase-fixing phase locked loop (PLL) circuit51.

At the right half of the logic chip4, the clock signal CLK is supplied to each output buffer circuit49connected to the clock output pad42, each clock terminal of the latch circuit48connected to each output pad44, and a clock terminal of the output side latch circuit62connected to each input/output buffer45, respectively, via the trunk line40of the CLK clock tree and a right-side branch46that is branched from the trunk line40. A right side47of a clock tree for the return clock signal ReCLK (hereinafter, “ReCLK clock tree”) is connected to the input buffer circuit60that is connected to the return clock receiving pad43. The return clock signal ReCLK is supplied to the clock terminal of the input side latch circuit63that is connected to the input/output pad45, via the right side47of the ReCLK clock tree.

At the left half of the logic chip4, the clock signal CLK is supplied to each output buffer circuit59connected to the clock output pad52, each clock terminal of the latch circuit58connected to each output pad54, and a clock terminal of the output side latch circuit67connected to each input/output buffer55, respectively, via the trunk line40of the CLK clock tree and a left-side branch56that is branched from the trunk line40. A left side57of the ReCLK clock tree is connected to the input buffer circuit65that is connected to the return clock receiving pad53. The return clock signal ReCLK is supplied to the clock terminal of the input side latch circuit68that is connected to the input/output pad55, via the left side57of the ReCLK clock tree.

A wiring length of the trunk line40of the CLK clock tree from the external clock input pad41to the right-side output buffer circuit49, the latch circuit48, and the output-side latch circuit62, and to the right-side branch46is equal to a wiring length of the trunk line40of the CLK clock tree from the external clock input pad41to the left-side output buffer circuit59, the latch circuit58, and the output-side latch circuit67, and to the left-side branch56. A wiring length of the right side47of the ReCLK clock tree from the right-side return clock receiving pad43to the input-side latch circuit63is equal to a wiring length of the left side57of the ReCLK clock tree from the left-side return clock receiving pad53to the input-side latch circuit68.

A clock input pad71that receives the clock signal CLK, plural input pads72that receive address signals and control signals, and plural input/output pads73that input/output data signals are disposed respectively, along the right side of the memory chip7. An input buffer circuit76is connected to the clock input pad71. A latch circuit75is connected to each input pad72, via the input buffer circuit77. An output side latch circuit79and an input side latch circuit91are connected to each input/output pad73, via an input/output buffer circuit78. The latch circuit75, the output side latch circuit79, and the input side latch circuit91are connected to an internal circuit (not shown) of the memory chip7.

A clock input pad81, plural input pads82, and plural input/output pads83are disposed respectively, along the left side of the memory chip7. An input buffer circuit86is connected to the clock input pad81. A latch circuit85is connected to each input pad82, via the input buffer circuit87. An output side latch circuit89and an input side latch circuit92are connected to each input/output pad83, via an input/output buffer circuit88. The latch circuit85, the output side latch circuit89, and the input side latch circuit92are connected to an internal circuit (not shown) of the memory chip7.

At the right half of the memory chip7, the input buffer circuit76that is connected to the clock input pad71is connected to the right side74of the clock tree that supplies the clock signal CLK. The clock signal CLK is supplied to clock terminals of the latch circuits75,79, and91that are disposed on the right side of the memory chip7, via the right side74of the clock tree. At the left half of the memory chip7, the input buffer circuit86that is connected to the clock input pad81is connected to the left side84of the clock tree that supplies the clock signal CLK. The clock signal CLK is supplied to clock terminals of the latch circuits85,89, and92that are disposed on the left side of the memory chip7, via the left side84of the clock tree. A wiring length of the right side74of the clock tree is equal to a wiring length of the left side84of the clock tree.

Within a package (not shown), the right-side clock output pad42of the logic chip4is electrically connected to the right-side clock input pad71of the memory chip7, via the wire electrode31. Therefore, in the right half of the memory chip7, the input of address signals, control signals, and data signals, and the output of data signals are carried out synchronously with the clock signal CLK that is supplied from the right-side clock output pad42of the logic chip4. The right-side clock input pad71of the memory chip7is electrically connected to the right-side return clock receiving pad43of the logic chip4, via the wire electrode32. Therefore, in the right half of the logic chip4, data signals are input synchronously with the return clock signal ReCLK as a return of the clock signal CLK that is output from the right-side clock output pad42of the logic chip4.

Each right-side output pad44of the logic chip4is electrically connected to the right-side input pad72of the memory chip7, via the wire electrode33. Each right-side input/output pad45of the logic chip4is electrically connected to the right-side input/output pad73of the memory chip7, via a wire electrode34. Dispositions of the right-side pads42,43,44, and45of the logic chip4connected to the wire electrodes31,32,33, and34are matched with dispositions of the right-side pads71,72, and73of the memory chip7such that the lengths of the wire electrodes31,32,33, and34are substantially equal to each other.

Within a package (not shown), the left-side clock output pad52of the logic chip4is electrically connected to the left-side clock input pad81of the memory chip7, via a wire electrode35. Therefore, in the left half of the memory chip7, the input of address signals, control signals, and data signals, and the output of data signals are carried out synchronously with the clock signal CLK that is supplied from the left-side clock output pad52of the logic chip4. The left-side clock input pad81of the memory chip7is electrically connected to the left-side return clock receiving pad53of the logic chip4, via a wire electrode36. Therefore, in the left half of the logic chip4, data signals are input synchronously with the return clock signal ReCLK as a return of the clock signal CLK that is output from the left-side clock output pad52of the logic chip4.

Each left-side output pad54of the logic chip4is electrically connected to the left-side input pad82of the memory chip7, via a wire electrode37. Each left-side input/output pad55of the logic chip4is electrically connected to the left-side input/output pad83of the memory chip7, via a wire electrode38. Dispositions of the left-side pads52,53,54, and55of the logic chip4connected to the wire electrodes3536,37, and38are matched with dispositions of the left-side pads81,82, and83of the memory chip7such that the lengths of the wire electrodes35,36,37, and38are substantially equal to each other. The lengths of the right-side wire electrodes31,32,33, and34of the logic chip4are substantially equal to the lengths of the left-side wire electrodes3536,37, and38. Therefore, it is easy to adjust timings between pads of the logic chip4.

FIG. 5AtoFIG. 5Eare schematics of waveforms for explaining signal delay levels in a configuration according to the first embodiment shown inFIG. 4and a configuration of the conventional stacked multiple chip package shown inFIG. 3. A waveform of the clock signal CLK is shown inFIG. 5A, a waveform of a data signal is shown inFIG. 5B, and a waveform of the return clock signal ReCLK is shown inFIG. 5C. As shown inFIG. 5D, in the configuration shown inFIG. 4, the return clock signal ReCLK that is input to the return clock receiving pads43and53reaches a node B (the furthest node from the return clock receiving pads43and53) shown inFIG. 4, with a time delay of T1. On the other hand, as shown inFIG. 5E, in the configuration shown inFIG. 3, the return clock signal ReCLK that is input to the return clock receiving pad13reaches a node A (the furthest node from the return clock receiving pad13) shown inFIG. 3, with a time delay of T2. The time delay T1is smaller than the time delay T2.

The time delay according to the configuration shown inFIG. 4is smaller than the time delay according to the configuration shown inFIG. 3, for the following reason. According to the configuration shown inFIG. 3, the return clock receiving pad13is provided on only one side of the logic chip1. On the other hand, according to the configuration shown inFIG. 4, the return clock receiving pads43and53are provided on both the left and the right sides of the logic chip4. Therefore, the wiring length of the ReCLK clock tree becomes shorter than the conventional wiring length by that portion.

According to the first embodiment, there is a margin in the delay time of the return clock signal ReCLK, corresponding to the difference between the time T1and the time T2(time T3). Therefore, there is allowance in the delay time within the logic chip4. As a result, it becomes easy to adjust timing within the logic chip4. Consequently, there is allowance in the clock cycle. This means that even if it is necessary to adjust the timing of the return clock signal ReCLK on the left side and the right side of the logic chip4, this allowance is sufficient enough to compensate for this adjustment.

FIG. 6is a schematic of a multiple chip package according to a second embodiment of the present invention. As shown inFIG. 6, according to the second embodiment, a memory chip107having a dummy pad181and a dummy input buffer circuit186is used, in place of the memory chip7having the clock input pad81and the input buffer circuit86according to the first embodiment (seeFIG. 4). The dummy input buffer circuit186is not connected to an internal circuit of the memory chip107. Further, a clock tree184that connects the latch circuits85, the output-side latch circuits89, and the input-side latch circuits92that are disposed at the left side of the memory chip107to the input buffer circuit76of the clock signal CLK disposed at the right side of the memory chip107is provided, in place of the left side84of the clock tree according to the first embodiment.

In other words, according to the second embodiment, the input/output timings of signals at the left side of the memory chip107are controlled based on the clock signal CLK that is input to the right side of the memory chip107. A configuration and a size of the dummy pad181are the same as those of the clock input pad81. A configuration and a size of the dummy input buffer circuit186are the same as those of the input buffer circuit86. The dummy pad181is electrically connected to the clock output pad52at the left side of the logic chip4via the wire electrode35, and is also electrically connected to the return clock receiving pad53at the left side of the logic chip4via the wire electrode36.

Therefore, the input/output timings of signals at the left side of the logic chip4are controlled based on the return clock signal ReCLK that is output from the left-side clock output pad52and is returned to the left-side return clock receiving pad53via the dummy pad181. Other configurations are similar to those according to the first embodiment. According to the second embodiment, in the same manner as in the first embodiment, the delay time of the return clock signal ReCLK is reduced. The reduced delay time gives a margin in adjusting timing within the logic chip4. Therefore, it becomes easy to adjust timing within the logic4.

FIG. 7is a schematic of a multiple chip package according to a third embodiment of the present invention. As shown inFIG. 7, according to the third embodiment, a memory chip207that does not have the dummy pad181and the dummy input buffer circuit186of the memory chip107shown inFIG. 6is used, in place of the memory chip107according to the second embodiment. A dummy pad30is provided on the substrate3of the package, in place of the dummy pad181. The dummy pad30is electrically connected to the clock output pad52at the left side of the logic chip4via the wire electrode35, and is also connected to the return clock receiving pad53at the left side of the logic chip4via the wire electrode36.

Therefore, similar to the second embodiment, the input/output timings of signals at the left side of the logic chip4are controlled based on the return clock signal ReCLK that is output from the left-side clock output pad52and is returned to the left-side return clock receiving pad53via the dummy pad30. The dummy pad30is not connected to the internal circuit of the substrate3of the package or the internal circuits of the logic chip4and the memory chip207. Other configurations are similar to those according to the second embodiment. According to the third embodiment, in the same manner as in the second embodiment, the delay time of the return clock signal ReCLK is reduced. The reduced delay time gives a margin in adjusting timing within the logic chip4. Therefore, it becomes easy to adjust timing within the logic4.

FIG. 8is a schematic of a multiple chip package according to a fourth embodiment of the present invention. As shown inFIG. 8, according to the fourth embodiment, a logic chip104and a memory chip307in which the input/output pads45and73of data signals are disposed along only one side, that is, the right side in the example shown inFIG. 8, are used, in place of the logic chip4and the memory chip7according to the first embodiment. Because the logic chip104does not receive a data signal at the left side, the left-side return clock receiving pad53that receives the return clock signal ReCLK and the input buffer circuit86connected to the return clock receiving pad53shown inFIG. 4are not present. Other configurations are similar to those according to the first embodiment.

FIG. 9is a plan view of an IC chip according to a fifth embodiment of the present invention. As shown inFIG. 9, a memory chip407has three or more groups of pads, and in the example, has four pad groups501,502,503, and504. Input/output timings of signals in the pad groups501,502,503, and504are controlled based on mutually different clock signals CLK1, CLK2, CLK3, and CLK4, respectively. For example, the first pad group501is disposed at an upper part on the right side, and includes input pads472aand input/output pads473a. The first pad group501is controlled based on the first clock signal CLK1that is supplied to a first clock input pad471a.

The second pad group502is disposed at a lower part on the right side, and includes input pads472band input/output pads473b. The second pad group502is controlled based on the second clock signal CLK2that is supplied to a second clock input pad471b. The third pad group503is disposed at an upper part on the left side, and includes input pads482aand input/output pads483a. The third pad group503is controlled based on the third clock signal CLK3that is supplied to a third clock input pad481a.

The fourth pad group504is disposed at a lower part on the left side, and includes input pads482band input/output pads483b. The fourth pad group504is controlled based on the fourth clock signal CLK4that is supplied to a fourth clock input pad481b. There can be three or five pad groups. Two pad groups are present according to the first embodiment and the fourth embodiment.

As explained above, each clock signal CLK is supplied from the left and the right sides of the memory chips7and307. Therefore, the wiring lengths of the clock trees74and84within the memory chips7and307become short, and the delay in the clock signal CLK becomes small. Further, each return clock signal ReCLK is supplied from the left and the right sides of the logic chip4. Therefore, the wiring lengths of the clock trees47and57of the return clock signal CLK within the logic chip4become short, and the delay in the return clock signal ReCLK becomes small. As a result, it becomes easy to adjust timing within the logic chip4and the memory chips7and307, respectively, thereby improving the band width. It becomes also easy to adjust timing between the logic chips4and104and the memory chips7,107,207, and307, respectively.

The present invention is not limited to the above embodiments, and can be variously modified. For example, the first IC chip is not limited to the logic chip, and can be the IC chip that has a function of outputting the clock signal CLK. The second IC chip is not limited to the memory chip, and can be the IC chip that has a function of receiving the clock signal CLK. The multiple chip package can also have the following configuration. In electrically connecting between the electrode pad of the first IC chip and the electrode pad of the second IC chip, the electrode pad of the first IC chip is electrically connected to the electrode pad of the substrate of the package using a wire electrode. Further, the electrode pad of the substrate of the package is electrically connected to the electrode pad of the second IC chip using a separate wire electrode. The present invention also includes the above configuration, and when the configuration is applied, the second IC chip includes the substrate of the package.

According to the present invention, it is possible to easily adjust timings within each IC chip and adjust timings between the IC chips.