OTPROM ARRAY WITH LEAKAGE CURRENT CANCELATION FOR ENHANCED EFUSE SENSING

Disclosed herein are memory cell arrays and methods for operating memory cell arrays. In one embodiment, a memory cell array includes a plurality of bitcells, a first bitline, a second bitline, a first wordline and a second wordline. The bitcells are arranged into rows and columns and each include a first transistor, a second transistor, and a fuse with a first end and a second end. The second transistor is selectively operable to couple the first end of the fuse to a ground. The first bitline is coupled to the first transistor of each of the bitcells of one column. The second bitline is coupled to the second end of the fuse of each of the bitcells of the column. The first transistor of each of the bitcells of the column is selectively operable to couple the first end of the fuse to the first bitline.

DETAILED DESCRIPTION

The following description refers to elements or nodes or features being “connected or “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element/node/feature is directly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “connect” means that one element/node feature is directly joined to (or directly communicates with) another element/node/feature, and not necessarily mechanically.

FIG. 1illustrates a block diagram of an OTPROM memory cell array100according to some embodiments. The memory cell array100includes a plurality of bitcells102, a wordline driver104, a plurality of bitline drivers106, and a plurality of sense amplifiers107. The bitcells102are arranged in rows and columns. Each bitcell102is coupled to the wordline driver104by one of a plurality of write wordlines108and one of a plurality of read wordlines110. The wordlines108and110provide access to the row of bitcells102in the memory cell array100. For example, the read wordlines110may be enabled (e.g., provided with a voltage) to select the respective row of the bitcells102for reading. Similarly, the write wordlines108may be enabled to select the respective row of bitcells102for programming in cooperation with a bitline.

Each bitcell102is also coupled to one of the bitline drivers106by one of a plurality of write bitlines112and is coupled to one of the sense amplifiers107by one of a plurality of read bitlines116. The bitlines112and116provide access to a column of bitcells102in the memory cell array100. For example, one of the plurality of bitline drivers106is coupled to one of the write bitlines112to both provide a programming current to a selected bitcell102during a write operation and to pass a sensing current to ground during a read operation, as will be described below. In some embodiments, the read bitlines116have dimensions that are less than required dimensions for carrying a burning current for burning the fuse. The smaller dimensions permit a more compact memory cell array100.

FIG. 2is an illustration of a portion200of the memory cell array100according to some embodiments. The portion200includes one of the bitcells102, one of the bitline drivers106coupled to the bitcell102by one of the write bitlines112, and one of the sense amplifiers107coupled to the bitcell102by one of the read bitlines116.

For the exemplary embodiments described herein, the bitcell102, the bitline driver106, and the sense amplifier107are fabricated on an appropriate semiconductor substrate. These semiconductor-based circuits may be formed using well known techniques and process steps (e.g., photolithography, doping, etching, patterning, material growth, material deposition, and the like) that will not be described in detail here. In some embodiments, the semiconductor material used is silicon. In some alternative embodiments, the semiconductor material may include germanium, gallium arsenide, or the like. The semiconductor material may be used to fabricate an N-type metal-oxide-semiconductor (NMOS) transistor or P-type metal-oxide-semiconductor (PMOS) transistor. The NMOS transistors include a source, a drain, a gate, and a bulk that is coupled to a ground, while the PMOS transistors include a source, a drain, a gate, and a bulk that is coupled to a power supply.

The bitcell102shown inFIG. 2includes a first transistor210, a second transistor212, and a fuse214. In the example provided, the transistors210and212are NMOS transistors. The drain of the first transistor210is coupled to the sense amplifier107by the read bitline116. The source of the first transistor210is coupled to a first end of216the fuse214and the drain of the second transistor212. The gate of the first transistor210is coupled to the wordline driver104by the read wordline110. The read wordline110may be enabled to turn on the first transistor210and selectively couple the sense amplifier107to the first end216of the fuse214for sensing the state of the bitcell102, as will be described below. A second end218of the fuse214is coupled to the bitline driver106by the write bitline112.

The source of the second transistor212is coupled to ground. The gate of the second transistor212is coupled to the wordline driver104by the write wordline108. The write wordline108may be enabled to turn on the second transistor212and selectively couple the first end216of the fuse214with ground for burning the fuse, as will be described below. It should be appreciated that the first and second transistors210and212may be any devices that selectively couple the first end216of the fuse214to the read bitline116and ground, respectively.

In some embodiments, the fuse214is a metal fuse device that burns when a current through the fuse214exceeds a threshold amount. In the example provided, the fuse214is an electronically programmable fuse where the first end216is a cathode and the second end218is an anode. It should be appreciated that any suitable fuse, antifuse, or other one-time programmable device may be utilized.

The bitline driver106includes a first transistor220, a second transistor222, a burn port224, a programming voltage port226, and a bitline zeroing port228. In the example provided, the first transistor220is a PMOS transistor and the second transistor222is an NMOS transistor. The source of the first transistor220is coupled to the programming voltage port226, the gate of the first transistor220is coupled to the burn port224, and the drain of the first transistor220is coupled to the write bitline112. The burn port224may be enabled to selectively couple the programming voltage port226to the write bitline112and permit a burning current to flow, as will be described below.

The source of the second transistor222is coupled to ground, the gate of the second transistor222is coupled to the bitline zeroing port228, and the drain of the second transistor222is coupled to the write bitline112. The bitline zeroing port228may be enabled to selectively couple the write bitline112with ground. Accordingly, a voltage VDSacross the drain and source of the second transistors212is substantially zero volts for inactivated bitcells102. The zero volt VDSsubstantially eliminates current leakage through the inactive bitcells102and permits a large number of bitcells102per bitline.

The sense amplifier107has an enable port230, an input port232, an output port234, and a voltage input port236. The sense amplifier107may be of any suitable type and have any suitable transistor configuration. In the example provided, the sense amplifier is a current sense amplifier. The enable port230may be enabled to sense the state of a bitcell102of the column of bitcells102coupled to the sense amplifier107by the read bitline116. The input port232is coupled to the read bitline116for sensing the state of the bitcells102by detecting the current flow through the read bitline116. The output port234generates a signal based on the logic state of the sensed bitcell102, as will be described below.

FIG. 3is a timing diagram of various signals of the memory cell array100ofFIG. 1. The timing diagram illustrates exemplary signal values during each of a burn fuse operation302, a first read bitcell operation304in which the fuse214is unburned, and a second read bitcell operation306in which the fuse214is burned. The burn fuse operation302is initiated by enabling the write wordline108and the burn fuse port224of the bitline driver106. Accordingly, the first transistor220of the bitline driver106and the second transistor212of the bitcell102are on, and the write bitline112is coupled to the programming voltage port226. A burning current310flows from the programming voltage port226through the first transistor220of the bitline driver106, through the write bitline112, through the fuse214, and through the second transistor212of the bitcell102to ground. The burning current310is maintained during the burn fuse operation302to burn the fuse214and permanently change the logic state of the bitcell102.

The first and second read bitcell operations304and306are initiated by enabling the enable port230of the sense amplifier107, the read wordline110, and the bitline zeroing port228of the bitline driver106. Accordingly, the second transistor222of the bitline driver106and the first transistor210of the bitcell102are on. During the first read bitcell operation304, current flows from the input port232of the sense amplifier through the read bitline116, through the first transistor of the bitcell102, through the fuse214, through the write bitline112, and through the second transistor222of the bitline driver106to ground. The voltage of the read bitline116is substantially equal to the voltage drop across the fuse214and the transistors210and222. During the second read bitcell operation306, little or no current flows through the fuse214, and the voltage of the read bitline116is substantially the same as VDDapplied to the voltage input port236of the sense amplifier107.

The memory cell array provided has several beneficial attributes. For example, the write bitline and the second end of each fuse in a bitline is coupled to ground during sensing to restrict leakage current from inactive bitcells. Additionally, the leakage current restriction permits implementation of large bitcell transistors between the first end of the fuse and ground for burning. Low threshold voltage transistors may also be incorporated to reduce the bitcell area. For example, the first transistor210in bitcell102may be small (e.g., 1/10×width/length ratio) compared to the second transistor212. Accordingly, the increase of size of the bitcell may be increased only slightly with the additional transistor210.

Thin lines may also be incorporated for the read bitlines because the read bitlines need only carry sensing current, and not the burning current used to burn the fuse. Furthermore, the first transistor of the bitcell acts as a current source and the impact of voltage drops (IR-drops, Cross-talk) on the read bitline are reduced.