Neuromorphic computational system(s) using resistive synaptic devices

Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.

FIELD OF THE DISCLOSURE

This disclosure relates generally to neuromorphic computational circuitry along with systems and methods of operating the same.

BACKGROUND

Neuromorphic computing has gained great attention as the traditional Boolean computing based on CMOS technology is reaching its physical limits. Inspired by the computational capability of the human brain, cognitive computing and learning has become an increasingly attractive paradigm for future computation beyond the von Neumann architecture. Recent advances in neuro-inspired machine learning algorithms have shown tremendous success in speech/image recognition.

To implement large scale neuromorphic computing, large resistive networks of resistive devices are provided where the resistive devices have conductances that can be provided in multiple conductance states. Building these resistive networks with emerging non-volatile resistive devices is attractive as these non-volatile resistive devices tend to be more compact and less costly. However, current neuromorphic computational systems assume that the conductances of the non-volatile resistive devices can be changed linearly using identical voltage pulses. For many applications, this assumption is not justified and can result in unacceptably computational inaccuracy. One source of non-linearity is that an off conductance state of the resistive devices is not zero. Ideally, an on conductance state to off conductance state ratio (ON/OFF ratio) is infinite and in practice can be assumed to be infinite if the ON/OFF ratio is sufficiently high. Unfortunately, resistive devices typically have ON/OFF ratios of between15and40depending on the type of resistive devices being utilized in the resistive network. Thus, while current neuromorphic computational systems assume that the ON/OF conductance ratio is infinite, an ON/OFF ratio of between15and40is not sufficient to allow the neuromorphic computational systems to operate under this assumption because the non-linearity leads to unacceptably high computational errors. Therefore, new techniques are needed that can ameliorate the effect of finite ON/OFF ratios and thereby provide better computational accuracy in a neuromorphic computational system.

SUMMARY

This disclosure relates generally to neuromorphic computational circuitry along with systems and methods of operating the same. In one embodiment, neuromorphic computational circuitry includes a cross point resistive network and line control circuitry. The cross point resistive network has variable resistive units and a set of conductive lines. Sets of the variable resistive units are connected to a corresponding conductive line. One of the sets of the variable resistive units is configured to generate a correction line current along its corresponding conduction line while other sets of the variable resistive elements may be coupled to generate resultant line currents on their corresponding conductive lines.

For example, in one implementation, the cross point resistive network is arranged so that the variable resistive units are provided in columns where each column of the variable resistive units is connected to a corresponding conductive line of the set of conductive lines. One of the columns of the variable resistive units is configured to generate the correction line current while the other columns of the variable resistive elements are configured to generate resultant line currents on their respective conductive lines. The resultant line currents each have a current level that represents a vector value.

In one implementation, the set of variable resistive units that provides the correction line current is configured to generate the correction line current by providing each of the variable resistive units in this set of resistive units in a minimum conductance state (i.e. the off conductance state).

The line control circuitry is coupled to receive the correction line current and the resultant line currents from the set of conductive lines. The line control circuitry is configured to generate digital vector values. Each of the digital vector values is set in accordance with a difference between the current level of a corresponding one of the resultant line currents and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current and thus computational errors resulting from a finite ON/OFF ratio are reduced or even substantially eliminated.

DETAILED DESCRIPTION

This disclosure relates to neuromorphic computational circuitry that includes a resistive memory system with a cross point resistive network used to represent the matrix values of a matrix. More specifically, the cross point resistive network is a network of variable resistive elements where variable resistive units of one or more of the variable resistive elements each provide a variable conductance that represents a corresponding matrix value of the matrix. For instance, in some implementations, the variable resistive units are each provided by an individual variable resistive element and thus a variable conductance of each of the variable resistive elements in the cross point resistive network represents a matrix value of the matrix. On the other hand, variable resistive units may each be provided by a group of the variable resistive elements (such as for example a subarray of the variable resistive elements) in the cross point resistive network. In this case, the combined variable conductance of each group (e.g., subarray) of the variable resistive elements represents a corresponding matrix value of the matrix.

The resistive memory systems of the neuromorphic computational circuitry can be utilized to implement neuromorphic algorithms that mimic biological neural networks. Stochastic Gradient Descent (SGD) is one of the most efficient algorithms that aims to minimize the reconstruction error Σt∥D·Z−x∥2, where x is an input vector, D is a matrix called a dictionary, and Z is a coefficient vector, which is usually assumed to be sparse in many problems. To implement the neuromorphic algorithms, the matrix values of the matrix D are mapped to the variable conductances of variable resistive units. Learning takes place by updating the matrix values of the matrix D and thus by adjusting the variable conductances of the variable resistive units. Matrix operations, including updating the matrix values, can take place entirely in parallel as described in further detail below. The matrix D may be considered to be an (m×p) matrix of matrix values, where m and p are both integer numbers.

Systems, methods and techniques are disclosed that improve the learning accuracy and computational accuracy of the neuromorphic computational circuitry by reducing the effects of different types of variations between the variable resistive elements in the cross-point resistive network. As such, the neuromorphic computational circuitry can be integrated more reliably to resolve problems such as image recognition with increased speed.

FIG. 1illustrates an exemplary embodiment of a neuromorphic computational circuitry NCC, which includes an exemplary embodiment of a resistive memory system10that is configured to implement matrix vector product operations and conductance update operations in parallel. The resistive memory system10may be configured to perform an artificial intelligence algorithm, such as neuro-inspired machine learning algorithms. The resistive memory system10includes a cross point resistive network12. The cross point resistive network12includes variable resistive elements R11, R12, R13, R14, R15, R16, R1Y, R21, R22, R23, R24, R25, R26, R2Y, R31, R32, R33, R34, R35, R36, R3Y, R41, R42, R43, R44, R45, R46, R4Y, R51, R52, R53, R54, R55, R56, R5Y, R61, R62, R63, R64, R65, R66, R6Y, RX1, RX2, RX3, RX4, RX5, RX6, RXY (referred to generically as variable resistive elements R) and conductive lines WL1, WL2, WL3, WL4, WL5, WL6, WLX, BL1, BL2, BL3, BL4, BL5, BL6, BLY (referred to generically as conductive lines W/BL). Each of the variable resistive elements R may be any type of electronic element with a variable resistance that varies between different resistive states. Thus, each of the variable resistive elements R has a variable conductance that varies between different conductance states. The variable resistive elements may be or may include resistive random access memory (RRAM) elements, conductive bridge random access memory (CBRAM) elements, phase change memory (PCM) elements, spin transfer torque magnetic random access memory (STTMRAM) resistive elements, and/or the like.

The conductive lines W/BL are coupled to the variable resistive elements R such that the conductive lines W/BL and the variable resistive elements R form the cross point resistive network12. Thus, each of the variable resistive elements R is connected between a corresponding pair of the conductive lines W/BL.

In this embodiment, the conductive lines W/BL are arranged to include word lines WL1, WL2, WL3, WL4, WL5, WL6, WLX (referred to generically as word lines WL) and bit lines BL1, BL2, BL3, BL4, BL5, BL6, BLY (referred to generically as bit lines BL). The word lines WL and the bit lines BL extend in substantially orthogonal directions but, in this embodiment, are not directly connected to one another. Instead, each of the variable resistive elements R is connected between a corresponding one of the word lines WL and a corresponding one of the bit lines BL such that the cross point resistive network12is a cross point resistive array. Different sets of the variable resistive elements R can be identified based on the word line WL and bit line BL coupled to the particular set of the variable resistive elements. For example, the variable resistive elements R in the cross point resistive network12shown inFIG. 1are arranged in rows of the variable resistive elements R and columns of the variable resistive elements R. Each of the variable resistive elements R in a row is connected to the same word line WL, and each of the variable resistive elements R in a column is connected to the same bit line BL. There is an integer number Y of variable resistive elements R in each row. There is also an integer number X of the variable resistive elements R in each column.

More specifically, in the embodiment shown inFIG. 1, a set of the variable resistive elements R11, R12, R13, R14, R15, R16, R1Y are in a row O1and are each connected to the word line WL1. A set of the variable resistive elements R21, R22, R23, R24, R25, R26, R2Y are in a row O2and are each connected to the word line WL2. A set of the variable resistive elements R31, R32, R33, R34, R35, R36, R3Y are in a row O3and are each connected to the word line WL3. A set of the variable resistive elements R41, R42, R43, R44, R45, R46, R4Y are in a row O4and are each connected to the word line WL4. A set of the variable resistive elements R51, R52, R53, R54, R55, R56, R5Y are in a row O5and are each connected to the word line WL5. A set of the variable resistive elements R61, R62, R63, R64, R65, R66, R6Y are in a row O6and are each connected to the word line WL6. A set of the variable resistive elements RX1, RX2, RX3, RX4, RX5, RX6, RXY are in a row OX and are each connected to the word line WLX.

Furthermore, in the embodiment shown inFIG. 1, a set of the variable resistive elements R11, R21, R31, R41, R51, R61, RX1are in a column C1and are each connected to the bit line BL1. A set of the variable resistive elements R12, R22, R32, R42, R52, R62, RX2are in a column C2and are each connected to the bit line BL2. A set of the variable resistive elements R13, R23, R33, R43, R53, R63, RX3are in a column C3and are each connected to the bit line BL3. A set of the variable resistive elements R70, R24, R34, R44, R54, R64, RX4are in a column C4and are each connected to the bit line BL4. A set of the variable resistive elements R15, R25, R35, R45, R55, R65, RX5are in a column C5and are each connected to the bit line BL5. A set of the variable resistive elements R16, R26, R36, R46, R56, R66, RX6are in a column C6and are each connected to the bit line BL6. A set of the variable resistive elements R1Y, R2Y, R3Y, R4Y, R5Y, R6Y, RXY are in a column CY and are each connected to the bit line BLY.

It should be noted that the cross point resistive network12shown inFIG. 1is simply exemplary. For example, the cross point resistive network12may not be provided as a cross point resistive array but instead in some other suitable alternative physical arrangement. Furthermore, the integer number of the variable resistive elements R in each row is X, and the integer number of the variable resistive elements R in each column is Y, where the integer number X and the integer number Y may be any integer number greater than one. However, asymmetric or partially asymmetric alternative arrangements may also be provided where a different integer number of the variable resistive elements R are provided within a proper subset of the rows and/or a different integer number of the variable resistive elements R are provided within a proper subset of the columns.

Throughout this disclosure the term “variable resistive unit” refers to a subset of one or more of the variable resistive elements R used to represent a value. For example, when the cross point resistive network12is being used to represent a matrix of matrix values, a variable resistive unit refers to an a subset of one or more of the variable resistive elements R used to represent a corresponding one of the matrix values in the matrix. Thus, each of the matrix values of the matrix may be mapped to a corresponding variable resistive unit provided by the cross point resistive network12.

In the embodiment shown inFIG. 1, the variable resistive units are fixed and in particular each variable resistive unit is provided by a different individual one of the variable resistive elements R. Thus, each of the matrix values of the matrix is represented by a variable conductance of a corresponding one of the variable resistive elements R. However, in alternative embodiments, each of the matrix values of the matrix may be represented using a group of the resistance elements R, such as a subarray of the variable resistive elements R. Accordingly, in these alternative embodiments, the variable resistive units would be groups of the variable resistive elements, such as subarrays of the variable resistive elements R, as explained in further detail below (SeeFIG. 12). Furthermore, alternative embodiments of the cross point resistive network12are configured so that the variable resistive units are reconfigurable (i.e., not fixed) so that different arrangements of one or more of the variable resistive elements R are selectable (SeeFIG. 12).

Referring again toFIG. 1, each of the variable resistive elements R has a variable resistance and thus also a variable conductance. In this embodiment, the variable conductance of each of the variable resistive elements R is configured to be provided in any one of a set of conductance states. The set of conductance states ideally is the same for each of the variable resistive elements R since each of the variable resistive elements R ideally is identical. However, this may not be the case as a result of different types of variations between the variable resistive elements R. The techniques described in this disclosure help reduce the effects of these variations so that the variable resistive elements R are more reliable thereby increasing the performance of the neuromorphic computational circuitry NCC.

Each of the conductance states in the set of the conductance states may be defined by a particular conductance magnitude or a particular range of conductance magnitudes. Thus, for each of the variable resistive elements R, the set of conductance states can be ordered. For example, the set of conductance states may include a minimum conductance state one or more intermediary conductance states, and a maximum conductance state where an order of the conductive states can be from highest to lowest or from lowest to highest. In this manner, each conductance state of the set of conductance states can represent a discrete value in a set of the discrete values. The set of the discrete values are the set of possible values that each matrix value can have in the matrix D. Accordingly, the set of conductance states bijectively correspond to the set of the discrete values. Furthermore, the set of conductance states correspond to the set of the discrete values in a same order of relative degree. Accordingly, the minimum discrete value in the set of the discrete values corresponds to the minimum conductance state, the lowest intermediary discrete value greater than the minimum discrete corresponds to the lowest intermediary conductance state greater than the minimum conductance state, etc. The pattern continues so that the greatest discrete value corresponds with the maximum conductance state.

For example, in one embodiment, each of the variable resistive elements R is configured to vary the variable conductance between any one of a set of sixty-four (64) conductance states. As such, each conductance state in the set of conductance states represents one of a set of sixty-four (64) discrete values. The low discrete value (e.g., 0) is represented by the minimum conductance state. The sixty-two (62) intermediary conductance states correspond in ascending order to the sixty-two (62) intermediary discrete values. Finally, the maximum conductance state corresponds with the greatest discrete value. Ideally, a conductance difference between a conductance state and the next highest and/or the next lowest conductance state is the same for every conductance state. However, variations can result in non-linearity between the conductance states as explained in further detail below.

In one implementation of the neuromorphic computational circuitry NCC shown inFIG. 1, the variable resistive elements R that are not in the column CY are used to represent the matrix values of the matrix D. Accordingly, the variable conductance of each of the variable resistive elements R11, R21, R31, R41, R51, R61, RX1in the column C1represents a corresponding one of the matrix values of the matrix D. The variable conductance of each of the variable resistive elements R12, R22, R32, R42, R52, R62, RX2in the column C2represents a corresponding one of the matrix values of the matrix D. The variable conductance of each of the variable resistive elements R13, R23, R33, R43, R53, R63, RX3in the column C3represents a corresponding one of the matrix values of the matrix D. The variable conductance of each of the variable resistive elements R70, R24, R34, R44, R54, R64, RX4in the column C4represents a corresponding one of the matrix values of the matrix D. The variable conductance of each of the variable resistive elements R15, R25, R35, R45, R55, R65, RX5in the column C5represents a corresponding one of the matrix values of the matrix D. The variable conductance of each of the variable resistive elements R16, R26, R36, R46, R56, R66, RX6in the column C6represents a corresponding one of the matrix values of the matrix D.

The variable resistive elements R that are not in the column CY are referred to generically or collectively as variable resistive elements RD. Thus, each of the variable resistive elements R11, R21, R31, R41, R51, R61, RX1, R12, R22, R32, R42, R52, R62, RX2, R13, R23, R33, R43, R53, R63, RX3, R18, R24, R34, R44, R54, R64, RX4, R15, R25, R35, R45, R55, R65, RX5, R72, R26, R36, R46, R56, R66, RX6is one of the variable resistive elements RD (note that each of these variable resistive elements R are not labeled with RD inFIG. 1but are referred to as RD for the sake of clarity and brevity). To do this, for each variable resistive elements RD in the cross point resistive network12, the row and column position of the variable resistive element RD corresponds directly with a row and column position of the corresponding matrix value being represented by the variable resistive element RD. Furthermore, the variable conductance of each of the matrix variable resistive elements RD is provided in the conductance state of the set of conductance states that corresponds with the discrete value in the set of the discrete values that corresponds to the matrix value.

When the neuromorphic computational circuitry NCC is implementing neuromorphic algorithms to provide machine learning, the matrix values of the matrix D are normalized synapse weights. Thus, each of the matrix values can vary between a set of the discrete values from “0” to “1.” For example, the minimum discrete value of each of the matrix values is “0” while the maximum discrete value of each of the matrix value is “1.” Intermediary discreet values in the set of the discrete values will be greater than “0” but less than “1.” Accordingly, the minimum conductance state of the set of conductance states represents the discreet value of “0,” intermediary conductance states represent discreet values that are greater than “0” but less than “1,” and the maximum conductance state represents the discreet value of “1.”

The minimum conductance state may thus be the off conductance state of the variable resistive elements R while the maximum conductance state of the variable resistive elements R would be the on conductance state of the variable resistive elements R. Ideally then, the off conductance (and thus the minimum conductance state) would be zero conductance while the maximum conductance state would be infinite conductance. Accordingly, the off conductance state (and thus the minimum conductance state) can represent the discrete value of “0 ideally only when a ratio between the on conductance (and thus the maximum conductance state) and the off conductance (and thus the minimum conductance state) is infinity. This however is not practically feasible. Furthermore simulations have shown that the learning accuracy of the computational circuitry implementing neuromorphic algorithms dramatically decreases when the ratio between the on conductance state (and thus the maximum conductance state) and the off conductance state (and thus the minimum conductance state) shrinks below25. This is because calculations involving small matrix values can be significantly distorted by current resulting from the off conductance.

To remedy this and reduce or even eliminate the effect of the off conductance state, the set of the variable resistive elements in the column CY are each provided in the minimum conductance state. Accordingly, the variable conductance of each of the variable resistive elements R1Y, R2Y, R3Y, R4Y, R5Y, R6Y, RXY are each provided in the minimum conductance state. Therefore, the variable resistive elements R in the column CY are configured to generate a correction line current IRY on the conductive line BLY. As explained in further detail below, the correction line current IRY is used to correct the effects of the non-zero minimum conductance state in each of the columns C1, C2, C3, C4, C5, and C6. Except for spatial variation between the synaptic devices in the same row O1-O6, this virtually eliminates the effect of off conductance state during the read operation and therefore results in greater computation accuracy.

To read, write, and update the cross point resistive network12, the resistive memory system10also includes word fine control circuitry18and bit line control circuitry20. The word line control circuitry18is configured to generate a word line output, which in this embodiment may be provided as different combinations of word line voltages VW1, VW2, VW3, VW4, VW5, VW6, VWX (referred to generically as word line voltages VW), as explained in further detail below. The bit line control circuitry20is configured to generate a bit line output, which in this embodiment may be provided as different combinations of bit line voltages VB1, VB2, VB3, VB4, VB5, VB6, VWY (referred to generically as bit line voltages VB). The word line control circuitry18is configured to generate the word line output onto the word lines WL, and the bit line control circuitry20is configured to generate the bit line output onto the bit lines BL such that different types of matrix operations can be performed in parallel. For example, the word line output can be generated to represent a vector to perform matrix multiplication in parallel. Similarly, the bit line output can be generated to represent a vector to perform matrix multiplication in parallel. Furthermore, the word line control circuitry18is configured to generate the word line output onto the word lines WL, and the bit line control circuitry20is configured to generate a bit line output onto the bit lines BL.

The word line control circuitry18includes an integer number X of word line controllers (referred to generically as word line controllers22and specifically as word line controllers22-1through22-X). Each of the word line controllers22is configured to generate a corresponding one of the word line voltages VW onto a corresponding one of the word lines WL, as shown inFIG. 1. With respect to the bit line control circuitry20, the bit line control circuitry20includes an integer number Y of bit line controllers (referred to generically as bit line controllers24and specifically as bit line controllers24-1through24-Y). Each of the bit line controllers24is configured to generate a corresponding one of the bit line voltages VB onto a corresponding one of the bit lines BL, as shown inFIG. 1.

Different types of matrix operations that may be performed with the resistive memory system10using the word line control circuitry18and the bit line control circuitry20. More specifically, the peripheral digital computational circuitry28is configured to control the resistive memory system10so that the matrix operations and neuromorphic algorithms described in this disclosure are implemented with the resistive memory system10. For example, the peripheral digital computational circuitry28may generate control outputs to the word line control circuitry18and the bit line control circuitry20so that the procedures for the operations described herein are performed as described in this disclosure.

As mentioned above, the matrix values of the matrix D are mapped onto the variable resistive units and the variable resistive units inFIG. 1are individual variable resistive elements R. Accordingly, the matrix values of the matrix D are mapped to the variable conductances of the variable resistive elements RD in all of the columns except for the column CY. Each of the word line controllers22and each of the bit line controllers24have write circuitry and read circuitry in order to perform matrix operations, as described herein. The matrix values of the matrix D are represented by G, which are the variable conductances of the variable resistive elements RD. Gijis a particular variable conductance corresponding to the variable resistive unit at a row position i and a column position j.

Learning takes place through a D update operation. Since the matrix values of the matrix D are represented by the variable conductance of a corresponding one of the variable conductance elements RD, the variable conductances of the variable resistive elements RD need to be set to the conductance state in the set of conductance states that corresponds to the corresponding matrix value of the matrix whenever the matrix D is updated. The D update operation is performed by setting the variable conductance of each of the variable conductance elements RD to the conductance state that corresponds to an updated discrete value for the corresponding matrix value represented by the variable conductance. The D update operation is a write type operation that is performed by generating the word line output and the bit line output as large appropriately timed voltage pulses, as explained in further detail below. In this manner, the combined variable conductances of all the variable resistive units (which inFIG. 1are the variable resistive elements RD) in the entire cross point resistive network12are updated in parallel. During the D update operation, the word line output and the bit line output are generated so that the variable conductance of each of the variable resistive elements R1Y, R2Y, R3Y, R4Y, R5Y, R6Y, RXY in the column CY are provided in the minimum conductance state.

The update D operation is performed utilizing write circuits in the word line controllers22of the word line control circuitry18and write circuits in the bit line controllers24of the bit line control circuitry20. Each of the matrix values of the matrix D may have a value range of the discrete values. For example, in one embodiment, each of the matrix values of the matrix D may be provided as any one of sixty four different values. The change in the matrix D is equal to ΔD=η·r·Z. The value η is the learning rate. The change in the matrix D is thus proportional to the matrix multiplication of the resultant vector r·Z. ΔD=η·r·Z thus indicates differences between the discrete value each of the matrix values is currently assigned to prior to the update operation and the discrete value that each of the matrix values is to be updated to as a result of the update operation. The discrete value that each of the matrix values is to be updated to corresponds to a target conductance state in the set of conductance states.

Accordingly, the peripheral digital computational circuitry28is configured to operate the resistive memory system10during the D update operation so that each of the variable resistive units (which inFIG. 1are individual variable resistive elements R) change their variable conductance from a current conductive state prior to the D update operation to the target conductance state that corresponds to the discrete value that each of the matrix values is to be updated to as a result of the update operation. In this manner, the variable conductances of the variable resistive units (which inFIG. 1are individual variable resistive elements R) can represent the matrix values of the D matrix. The change for each variable conductance can thus be represented by changing each of the variable conductances by approximately:
ΔGij=η·ri·Zj

Gijrepresents the variable conductance of the variable resistive unit (which in this example is one of the individual variable resistive elements RD) and thus the above equation provides the required change in the variable conductance. In this embodiment, the peripheral digital computational circuitry28does not calculate Z·r before programming. Instead, the word line control circuitry18is configured to generate the word line output onto the word lines WL and the bit line control circuitry20is configured to generate the bit line output onto the bit lines BL such that each of the plurality of variable conductances provided by the variable resistive units (which inFIG. 1are individual variable resistive elements R) is adjustable in parallel. To do this, the peripheral digital computational circuitry28is configured to generate a digital vector output30of the digital vector values of the vector r and receive a resultant digital vector output32that represents the vector Z from the bit line control circuitry20. The word line control circuitry18is configured to receive the digital vector output30, and the bit line control circuitry20is configured to generate the resultant digital vector output32, as explained in further detail below. A combination of the word line controllers22generates a combination of the word line voltage VW, and a combination of the bit line controllers24will generate the bit line voltages VB. The combination of the word line controllers22, the word line voltage VW, the bit line controllers24, and bit line voltages will depend on the size of the of the variable resistive units (which inFIG. 1are individual variable resistive elements R) selected to provide variable conductances, as explained below with regard to the D·Z operation and the DT·r operation.

However, during the update D operation, the word line voltages VW and the bit line voltages VB are generated at the same time. The matrix values of the vector Zjare always positive numbers, while the vector values riof the vector r can be positive or negative, depending on the residual error. Therefore whether the matrix value of the matrix D and the corresponding variable conductance Gijthat represents the matrix value will increase or decrease depending on the sign of the corresponding the vector value ri, but not the vector value Zj. When vector value riis positive, the matrix value and thus the variable conductance Gijdecreases (also referred to as depression), but when the vector value riis positive, the matrix value and thus the variable conductance Gijincreases (also referred to as potentiation).

Next, write circuits in the word line controllers22of the word line control circuitry18and read circuits in the bit line controllers24of the bit line control circuitry20are used by the peripheral digital computational circuitry28so that the resistive memory system10performs the D·Z operation. As explained in further detail below, this operation is a matrix multiplication operation performed by applying the world line voltages VW representing the vector Z on the word lines WL, and obtaining resultant bit line currents (referred to generically as IR and specifically as IR1-IR6) representing resultant vector from the bit lines BL1-BL6.

The combination of resultant bit line currents IR1-IR6represents the resultant vector of resulting from the D·Z operation. Matrix multiplication is thus achieved in parallel since each of the bit line currents IR1-IR6represents a different vector value of the resultant vector.

The sets of the variable resistive elements RD in each of the columns C1-C6are configured to generate resultant line currents BY1-BY6such that each of the columns C1-C6of the variable resistive elements RD generates a different one of the resultant line currents BY1-BY6on the corresponding conductive line. Accordingly, the word line controllers22will each generate a corresponding word line voltage VW so that all of the word line voltages VW1-VWX are applied to the word lines WL1-WLX. Each of the write circuits in each of the word line controllers22is configured to convert a corresponding one of the digital vector values into its corresponding word line voltage VW such that the word line voltage VW represents the corresponding one of the digital vector values. In this case, the word line controllers22set the word line voltages VW to a voltage magnitude that is proportional to the corresponding digital vector value of the vector Z. For each of the word line voltages VW, the word line voltage VW multiplied by the combined variable conductance Gijrepresents weight times vector value multiplication. Summation takes place since the resultant vector value for a column of variable resistive units (which inFIG. 1are individual variable resistive elements R) is the result of all of the variable conductances of the corresponding column of variable resistive units (which inFIG. 1are individual variable resistive elements R).

With regards to the embodiment shown inFIG. 1, the resultant bit line currents IR1-IR6will be provided in response to the word line voltages VW1-VWX. Each of the resultant bit line currents IR1-IR6is approximately equal to the weighted sum of each word line voltage VW multiplied by the variable conductance of each of the variable resistive elements RD in different corresponding column C1-C6of the variable resistive elements RD. Thus, the current level of each of the resultant bit line currents IR1-IR6represents the resultant vector resulting from the D·Z operation. However, the resultant bit line currents IR1-IR6have current levels that are in error due to the minimum off state conductance. This is corrected by the bit line control circuitry20using the correction bit line current IRY on the bit line BLY, as explained in further detail below.

The bit line control circuitry20is coupled to receive the correction line current IRY and the resultant line currents IR1-IR6from the bit lines BL. Each of the bit line controllers24includes a read circuit. In this case, each of the bit line controllers24of the bit line control circuitry20is configured to receive a corresponding one of the bit line currents IR1-IRY from its corresponding bit line BL. The read circuit in each of the bit line controllers24is configured to convert its corresponding bit line current IR to a digital value representing the current level of the corresponding bit line BL. Thus, the bit line controller24-1is configured to receive the resultant bit line current IR1on the bit line BL1. The resultant bit line controller24-1is configured to generate a digital vector value that indicates a current level of the resultant bit line current IR1. The bit line controller24-2is configured to receive the resultant bit line current IR2on the bit line BL2. The resultant bit line controller24-2is configured to generate a digital vector value that indicates a current level of the resultant bit line current IR2. The bit line controller24-3is configured to receive the resultant bit line current IR3on the bit line BL3. The resultant bit line controller24-3is configured to generate a digital vector value that indicates a current level of the resultant bit line current IR3. The bit line controller24-4is configured to receive the resultant bit line current IR4on the bit line BL4. The resultant bit line controller24-4is configured to generate a digital vector value that indicates a current level of the resultant bit line current IR4. The bit line controller24-5is configured to receive the resultant bit line current IR5on the bit line BL5. The resultant bit line controller24-5is configured to generate a digital vector value that indicates a current level of the resultant bit line current IR5. The bit line controller24-6is configured to receive the resultant bit line current IR6on the bit line BL6. The resultant bit line controller24-6is configured to generate a digital vector value that indicates a current level of the resultant bit line current IR6. Finally, the bit line controller24-Y is configured to receive the correction bit line current IRY on the bit line BLY. The resultant bit line controller24-Y is configured to generate a digital correction value that indicates a current level of the correction bit line current IRY. Note that the digital vector values generated as a result of the resultant bit line current IR6are off due to the off state conductance.

Accordingly, the bit line control circuitry20further includes subtractors (referred to specifically as substrators26-1to26-6and generically as substractors26). The substractors26are configured to generate digital vector values such that each of the digital vector values is set in accordance with a difference between a current level of a corresponding resultant line current IR1-IR6of the resultant current levels and a current level of the correction line current IRY. In this manner, each of the digital vector values output from the substrators26is corrected by the digital correction value and thus for the off state conductance error. More specifically, the subtractor26-1is configured to receive the digital vector value generated by the read circuit of the bit line controller24-1and the digital correction value from the read circuit of the bit line controller24-Y. The subtractor26-1is configured to subtract the digital correction value from the digital vector value52-1and generate a digital vector value equal to difference between the digital vector value from the read circuit of the bit line controller24-Y and the digital correction value. The subtractor26-2is configured to subtract the digital correction value from the digital vector value52-2and generate a digital vector value equal to difference between the digital vector value from the read circuit of the bit line controller24-Y and the digital correction value. The subtractor26-3is configured to subtract the digital correction value from the digital vector value52-3and generate a digital vector value equal to difference between the digital vector value from the read circuit of the bit line controller24-Y and the digital correction value. The subtractor26-4is configured to subtract the digital correction value from the digital vector value52-4and generate a digital vector value equal to difference between the digital vector value from the read circuit of the bit line controller24-Y and the digital correction value. The subtractor26-5is configured to subtract the digital correction value from the digital vector value52-5and generate a digital vector value equal to difference between the digital vector value from the read circuit of the bit line controller24-Y and the digital correction value. The subtractor26-6is configured to subtract the digital correction value from the digital vector value52-6and generate a digital vector value equal to difference between the digital vector value from the read circuit of the bit line controller24-Y and the digital correction value. The resultant digital vector values from the bit line controllers24are combined so that the bit line control circuitry20generates a resultant digital vector output32. The resultant digital vector output32is received by the peripheral digital computational circuitry28to continue implementing the learning algorithm.

The DT·r operation is performed utilizing write circuits in the bit line controllers24of the bit line control circuitry20and read circuits in the word line controllers22of the word line control circuitry18. The DT·r operation is a matrix multiplication operation performed by applying the bit line voltages VB representing the vector r on the bit lines BL and obtaining word line currents (referred to generically as IZ and specifically as IZ1-IZX) representing resultant vector DT·r from the word lines WL. The peripheral digital computational circuitry28is configured to generate the digital vector output30that includes digital vector values of the vector r. Each of the write circuits in each of the bit line controllers24is configured to convert a corresponding one of the digital vector values into its corresponding bit line voltage VB such that the bit line voltage VB represents the corresponding one of the digital vector values. In this case, the bit line controllers24are configured to set each of the voltage magnitudes of each of the bit line voltages VB in accordance with its corresponding digital vector value.

Each of the word line controllers26has a read circuit configured to receive a corresponding one of word line currents IZ from a corresponding one of the word lines WL. The read circuits in the word line controllers26are configured to generate the digital vector output36from the word line currents IZ. More specifically, the read circuit in each of the word line controllers26is configured to generate a corresponding one of the digital vector values such that the corresponding digital vector value is set in accordance with a current level of corresponding word line current IZ received from the corresponding word line WL. The digital vector output36includes each of the digital vector values of the resultant vector Z. The peripheral digital computational circuitry28is configured to receive the digital vector output36in order to perform neuromorphic algorithms, as described in further detail below.

In one exemplary embodiment of the resistive memory system10, all of the variable resistive elements R are each provided as an RRAM element. The cross point resistive network12, the word lines WL, the bit lines BL, the switchable paths W/BS, the switch control circuitry14, the word line control circuitry18, and the bit line control circuitry20are all formed on a semiconductor die38. In one embodiment, the switchable paths W/BS, the word line control circuitry18, and the bit line control circuitry20are formed in a semiconductor substrate of the semiconductor die38. The variable resistive elements R, the word lines WL, and the bit lines BL may be formed within the BEOL of the semiconductor die38. Also, in one exemplary embodiment, the peripheral digital computational circuitry28is provided as an Intel i7 8-core processor, memory, and a digital interface. The memory stores software run by the Intel i7 8-core processor to coordinate the implementation of the learning algorithm along with digital representations of the Z vector, r vector, and x vector. The digital interface operably associates the peripheral digital computational circuitry28with the word line control circuitry18, and the bit line control circuitry20, so that the digital vector output30, the resultant digital vector output32, the digital vector output34and the resultant digital vector output36can be transmitted to and/or from the peripheral digital computational circuitry28.

FIG. 2illustrates an exemplary embodiment of an RRAM element42. In one example, each of the variable resistive elements R of the cross point resistive network12shown inFIG. 1is provided in the same manner as the RRAM element42shown inFIG. 2. The RRAM element42includes a first electrode44, a second electrode46, and an insulating layer48provided between the first electrode44and the second electrode46. The first electrode44and the second electrode46may be provided from any material suitable to provide RRAM elements. The insulating layer48may be formed from an oxide material(s) or any other type of suitable insulating material(s).

The RRAM element42has a variable conductance that is adjustable by applying a voltage pulse across the RRAM element. The change in the variable conductance depends on a temporal length of the voltage pulse. As shown, the RRAM element42is connected between the word line WL and the bit line BL. In this manner, the corresponding word line voltages VW representing the vector value Zjand the bit line voltage VB representing a vector value rjcan adjust the variable conductance of the RRAM element42. Since subarrays of the variable resistive elements R may be interconnected to provide the combined variable resistance representing one of the matrix values of the matrix D, the read inaccuracy can be high with small wire widths (e.g., W=20 nm), due to voltage drop on interconnects. Accordingly, wire widths W may be selected to be approximately 200 nm. The effect of the element spacing (S) on the read accuracy tends to be less prominent. Larger wire width W and smaller element spacing S (or wire pitch) reduce RC delay. However, the current overshoot due to element capacitance can be high when element spacing S is small. Therefore, in one embodiment, the element spacing S is provided to be approximately 1 μm.

FIG. 3illustrates an example of the peripheral digital computational circuitry28operably associated with the word line control circuitry18and the bit line control circuitry20to the bit line control circuitry20. A read circuit in each of the bit line controllers24is configured to generate digital values (referred to generically as digital values50and specifically digital vector values50(1)-50(6) and digital correction value50(Y)). The digital values50(1)-50(6) are digital vectors values representing a current level of a corresponding one of the resultant bit line currents IR1-IR6. The digital value50(Y) is a digital correction value representing a current level of the correction line current IRY. Each of the subtractors26receives a corresponding one of the digital vector values50(1)-50(6) and the digital correction value50(Y). Each of the subtracters26is configured to generate digital vector values (referred to generically as digital vectors values52and specifically as digital vector values52(1)-52(6). The subtractors26are each configured to generate the digital vector values52(1)-52(6) in accordance with a difference between the current level of a corresponding resultant line current IR1-IR6of the resultant current levels and a current level of the correction line current IRY. In this manner, each of the digital vector values52(1)-52(6) output from the substrators26is corrected by the digital correction value50(Y) and thus for the off state conductance error.

More specifically, the subtractor26-1is configured to receive the digital vector value50(1) generated by the read circuit of the bit line controller24-1and the digital correction value50(Y) from the read circuit of the bit line controller24-Y. The subtractor26-1is configured to subtract the digital correction value50(Y) from the digital vector value50(1) and generate a digital vector value52(1) equal to the difference between digital vector value50(1) and the digital correction value50(Y). The subtractor26-2is configured to receive the digital vector value50(2) generated by the read circuit of the bit line controller24-2and the digital correction value50(Y) from the read circuit of the bit line controller24-Y. The subtractor26-2is configured to subtract the digital correction value50(Y) from the digital vector value50(2) and generate a digital vector value52(2) equal to the difference between digital vector value50(2) and the digital correction value50(Y). The subtractor26-3is configured to receive the digital vector value50(3) generated by the read circuit of the bit line controller24-3and the digital correction value50(Y) from the read circuit of the bit line controller24-Y. The subtractor26-3is configured to subtract the digital correction value50(Y) from the digital vector value52-3and generate a digital vector value52(3) equal to the difference between digital vector value50(3) from the read circuit of the bit line controller24-3and the digital correction value50(Y). The subtractor26-4is configured to receive the digital vector value50(4) generated by the read circuit of the bit line controller24-4and the digital correction value50(Y) from the read circuit of the bit line controller24-Y. The subtractor26-4is configured to subtract the digital correction value50(Y) from the digital vector value52-4and generate a digital vector value52(4) equal to the difference between digital vector value50(4) from the read circuit of the bit line controller24-4and the digital correction value50(Y). The subtractor26-5is configured to receive the digital vector value50(5) generated by the read circuit of the bit line controller24-5and the digital correction value50(Y) from the read circuit of the bit line controller24-Y. The subtractor26-5is configured to subtract the digital correction value50(Y) from the digital vector value52-5and generate a digital vector value52(5) equal to the difference between digital vector value50(5) from the read circuit of the bit line controller24-5and the digital correction value50(Y). Finally, the subtractor26-6is configured to receive the digital vector value50(6) generated by the read circuit of the bit line controller24-6and the digital correction value50(Y) from the read circuit of the bit line controller24-Y. The subtractor26-6is configured to subtract the digital correction value50(Y) from the digital vector value52-6and generate a digital vector value52(6) equal to the difference between digital vector value50(6) from the read circuit of the bit line controller24-6and the digital correction value50(Y). The resultant digital vector values (referred to generically as digital vector values52) from the bit line controllers24are combined so that the bit line control circuitry20generates the resultant digital vector output32. The resultant digital vector output32is received by the peripheral digital computational circuitry28to continue implementing the learning algorithm.

In this example, the peripheral digital computational circuitry28includes one or more central processing units (CPUs)54, each including one or more processors56. The CPU(s)54may have cache memory58coupled to the processor(s)56for rapid access to temporarily stored data. The CPU(s)54are coupled to a system bus60and can intercouple master and slave devices included in the peripheral digital computational circuitry28. The system bus60may be a bus interconnect. As is well known, the CPU(s)54communicate with these other devices by exchanging address, control, and data information over the system bus60. For example, the CPU(s)54can communicate bus transaction requests to a memory system62. Although not illustrated inFIG. 3, multiple system buses60could be provided, wherein each system bus60constitutes a different fabric. Other master and slave devices can be connected to the system bus60. The memory system62can include one or more memory units64configured to store computer executable instructions (CEI). The CEI are executable by the processors56and thus allow the neuromorphic computational circuitry NCC to perform the operations described herein using the resultant digital vector output32. The peripheral digital computational circuitry28includes array control circuitry66that is operated by the CPU(s)54in order to perform the operations described in this disclosure. The array control circuitry66is configured to generate the digital vector output30that controls the operation of the word line control circuitry18and the bit line control circuitry20as described with regards to the operations discussed in this disclosure.

Referring now toFIG. 4andFIG. 5A,FIG. 4illustrates equations relevant to the operations for performing a learning algorithm.FIG. 5Aillustrates exemplary steps in a sparse coding algorithm that may be performed by the neuromorphic computational circuitry NCC shown inFIG. 1. In the training phase, the input vector x, the matrix D, and the vector Z are trained iteratively by minimizing the objective error function E, which is shown as Equation (1) inFIG. 4. Stochastic Gradient Descent (SGD) is one of the most efficient algorithms that aims to minimize the reconstruction error:
Σt∥D·Z−x∥2

where minimizing the reconstruction error may be assumed to be sparse in many applications. To implement the learning algorithm, the matrix values of the matrix D are mapped into the combined variable conductances of the subsets of the variable resistive elements R of the cross point resistive network. Learning takes place by updating the matrix values of the matrix D and thus by adjusting the variable conductances of the variable resistive units (which inFIG. 1are provided as individual ones of the variable resistive elements R).

The first term of Equation (1) inFIG. 4generally measures how well the matrix D reconstructs the input data. The second term of Equation (1) imposes constraint of the sparsity of the feature vector. Since both matrix D and the resultant vector Z are unknown, the above optimization problem is a non-convex problem. We propose to alternatively optimize Z with fixed matrix D by the coordinate descent (CD) method and optimize D with fixed Z by the stochastic gradient descent (SGD) method, which converts the problem into a convex optimization problem. Using SGD, the D weight update process can be expressed as Equation (2) inFIG. 4.

It can be seen that D is modulated by the product of ηRZTwhere R is the reconstruction error, and η is the learning rate. For the algorithm ideally implemented in software, the exact value of the equation above can be calculated and applied to update of the matrix D. However, the D update implemented on-chip needs to be translated to the number of pulses applied on the synaptic devices, and the effect of the programming pulses on the conductance of the devices may not represent the exact value of the equation above due to the realistic properties of synaptic devices as mentioned above. In this work, we model the weight update curve and incorporate this model in the D update code in the SC algorithm.

The update D operation is performed utilizing write circuits in the word line controllers22of the word line control circuitry18and write circuits in the bit line controllers24of the bit line control circuitry20. Each of the matrix values of the matrix D may have a value range of the discrete values. For example, in one embodiment, each of the matrix values of the matrix D may be provided as any one of sixty four different values. The change in the matrix values of the matrix D is equal to:
ΔD=η·r·Z.

The value η is the learning rate. The change in the matrix D is thus proportional to the matrix multiplication of the resultant vector r·Z. Accordingly, the subarrays of resistive elements R are each configured to vary their respective combined variable conductance to discrete variable conductance levels that map to the discrete values within the value range. In this manner, the combined variable conductances of the subarrays of resistive elements can represent the matrix values of the D matrix. The change for each combined variable conductance can thus be represented by changing each of the combined variable conductances to equal approximately:
ΔGij=η·ri·Zj

In this embodiment, the peripheral digital computational circuitry28does not calculate Z·r before programming. Instead, the word line control circuitry18is configured to generate the word line output onto the word lines WL and the bit line control circuitry20is configured to generate the bit line output onto the bit lines BL such that each of the plurality of combined variable conductances G provided by the subarrays is adjustable in parallel. To do this, the peripheral digital computational circuitry28is configured to generate the digital vector output30to represent the digital vector values of the vector r and to generate a digital vector output34to represent the digital vector values of the vector Z. The word line control circuitry18is configured to receive the digital vector output30, and the bit line control circuitry20is configured to receive the digital vector output34.

A combination of the word line controllers22generates a combination of the word line voltage VW, and a combination of the bit line controllers24will generate the bit line voltages VB. The combination of the word line controllers22, the word line voltage VW, the bit line controllers24, and bit line voltages VB will depend on the size of the variable resistive units selected to provide variable conductances, as explained above with regard to the D·Z operation and the DT·r operation.

In the example shown inFIG. 1, all of the word line controllers22generate one of the word line voltages VW and the bit line controllers24-1to24-6generate one of the bit line voltages VB because the variable resistive units are each provided by individual variable resistive elements R.

Referring now toFIG. 4andFIG. 5B,FIG. 5Bdescribes the entire process flow that includes dictionary learning (training phase) and classification (testing phase). In this disclosure, MNIST handwriting digits is used as the training and testing data set, where the raw images are densely sampled into small patches with 10×10 pixels as The input vector x with a dimension of 100. In the later analyses, a set of 40 k images is used for training and a different set of 5 k images is used for testing. The size of Z is fixed at 300, thus the size of the D matrix is 100×300. Once the matrix D is trained, the matrix D is fixed as the trained dictionary Dtrain is used as a fixed D in the testing phase to generate the testing features {Ztest}. Before the classification process, a simple maximum pooling operation is employed on both the trained and testing features for each image to select the most active neuron of each feature node, and the output of maximum pooling results in one feature vector per image. Finally, to classify the 10 digits, the support vector machine (SVM) is used. With the input of testing labels, SVM performs classification and gives out the recognition accuracy.

To implement the SC algorithm on-chip, the precision of the matrix D and Z in the algorithm was limited. In the cross-point architecture, the values in the Z vector are stored on local memories in the peripheral digital computational circuitry28, and the values in the D matrix value are represented by the conductance states of the variable resistive elements RD of the cross point resistive network12shown inFIG. 1.FIG. 4shows the learning accuracy with different precisions by truncation of the bits in the SC algorithm. It suggests that a 4-bit Z is sufficient for high learning accuracy and limited precision of the matrix D has more impact on the accuracy. Since the number of bits D is related to how many levels of conductance the synaptic device can achieve, 6-bit values of the matrix D (64 levels) are chosen for later analysis based on the number of multi-level conductance states in today's variable resistive elements R (shown inFIG. 1).

The read accuracy is improved by resolving the problem regarding the non-zero minimum conductance state, as explained above. However, problems are also created by the non-linearity of the conductance state update. More specifically, for any particular variable resistive element R (shown inFIG. 1) the same pulse length or pulse cycle does not change the variable conductance of the variable resistive element R, by the same amount. As such, long-term potentiation (LTP) and long term depression (LTD) result in uneven changes in the variable conductance. Equation (3) inFIG. 4describes the variable conductance GLTPof one of the variable resistive elements R (shown inFIG. 1) as the variable conductance state of the variable resistive element R is changed from the minimum conductance state Gminto the maximum conductance state Gmax. On the other hand, Equation (4) inFIG. 4describes the variable conductance GLTDof one of the variable resistive elements R (shown inFIG. 1) as the variable conductance state of the variable resistive element R is changed from the maximum conductance state Gmaxto the minimum conductance state Gmin.

The maximum conductance state Gmax, the minimum conductance state Gminand and the maximum pulse number Pmaxrequired to switch the device between the minimum and maximum conductance states are directly extracted empirically from the experimental data. The variable P is the number of pulses. The parameter A is the parameter that controls the nonlinear behavior of the weight update, and the parameter B is simply a function of the parameter A that fits the functions within the range of Gmax, Gminand Pmax.

FIG. 6illustrates curves describing the relationship between the variable conductance of one of the variable resistive elements R (shown inFIG. 1) as a function of an integer number n identifying conductance states. With regard to the curves LTP(1), LTP(2), LTP(3) illustrate when the variable conductance is adjusted between the minimum conductance state Gminand the maximum conductance state Gmax. The curves LTP(1), LTP(2), LTP(3) are each provided with different value of the parameter A. With regard to the curves LTD(1), LTD(2), LTD(3) illustrate when the variable conductance is adjusted between the maximum conductance state Gmaxand the minimum conductance state Gmin. The curves LTD(1), LTD(2), LTD(3) are each provided with a different value of the parameter A. The curve in the center is the ideal curve if there was no non-linearity in adjusting the variable conductance. By comparison with the ideal curve, the curves LTP(1), LTP(2), LTP(3), LTD(1), LTD(2), LTD(3) are clearly shown to be non-linear.

FIG. 6thus illustrates the LTP and LTD behavior of updating the variable resistive elements R (shown inFIG. 1) as a function of the integer number n identifying the different conductance states. More specifically, the curve LTP(1) and the curve LPD(1) are provided when the parameter A has the same value. The curve LTP(2) and the curve LPD(2) are provided when the parameter A has the same value, but different than the value of the parameter A as provided for the curve LTP(1) and the curve LPD(1). The curve LTP(3) and the curve LPD(3) are provided when the parameter A has the same value, but different than the value of the parameter A as provided for the curve LTP(1) and the curve LPD(1) and different than the value of the parameter A as provided for the curve LTP(2) and the curve LPD(2). The curves pairs (LTP(1), LTD(1)), (LTP(2), LTD(2)), and (LTP(3), LTD(3)) demonstrate a hysteresis type behavior as the variable conductance is adjusted between the minimum conductance state Gminto the maximum conductance state Gmaxand then from the maximum conductance state Gmaxto the minimum conductance state Gmin. Thus, the change in the variable conductance state also depends on the direction of change (i.e., from a lower conductance state to a higher conductance state or from a higher conductance state to a lower conductance state). Accordingly, in order to change the conductance state of the variable resistive elements RD (shown inFIG. 1) consistently, the pulses utilized to adjust the variable conductance may need to be take into account the non-linear and hysteresis type behavior in order to achieve on the required recognition accuracy.

Another characteristic of the variable resistive elements R (shown inFIG. 1) that can lead to inaccuracies in calculations is spatial variation. Spatial variation refers to differences in behavior between the variable resistive elements R (shown inFIG. 1) due to their physical location. Spatial variation between the variable resistive elements R (shown inFIG. 1) causes drift and diffusion variation of ions and holes from device to device thereby resulting in different ones of the variable resistive elements R (shown inFIG. 1) following different non-linearity baselines.

FIG. 7Aillustrates the effect of spatial variation on the recognition accuracy. More specifically,FIG. 7Aillustrates curves that graph recognition accuracy versus the standard deviation of the variable conductance due to spatial variation. More specifically, curve SV1, curve SV2, curve SV3, and curve SV4each are provided with different degrees of non-linearity in the variable conductance. The curve SV1was provided in the ideal case with no non-linearity in the variable conductance (i.e., linear). The curve SV2is provided with more non-linearity in the variable conductance curve than the curve SV1but less than with the curves SV3, SV4. Curve SV3is provided with more non-linearity in the variable conductance curve than the curves SV1, SV2but less than with the curves SV4. Curve SV4is provided with more non-linearity in the variable conductance curve than the curves SV1, SV2, SV3. As shown by comparing the curves SV1, SV2, SV3, SV4inFIG. 7A, the effect of spatial variation does not have a large effect on recognition accuracy even at a standard deviation of 30% in comparison with the effect of non-linearity on learning accuracy. However, the effects of spatial variation are enhanced somewhat as non-linearity increases.

One possible reason that spatial variation does not have large effects is that the sparse coding algorithm can partially tolerate the spatial variation as the solution to the optimized D matrix is not unique. With the skewed weight update, the optimized D matrix may have converged at the next local minima as this is a non-convex problem. As long as such skew in weight update is deterministic and moderate, the cross point resistive network12(shown inFIG. 1) has the resilience to static variations in weight update. Note that other algorithms may not be as tolerant of spatial variation. Furthermore, although the effects of spatial variation do not seem to be great, they may be significant if the recognition accuracy required is very high. As such, other techniques may be implemented to ameliorate the effects of spatial variation when spatial variation is an issue, as explained in further detail below.

However,FIG. 7Billustrates the effects of another form of variation that does seem to have a more significant impact with some of the embodiments specifically disclosed. In particular,FIG. 7Billustrates the effects of temporal variation during variable conductance updates. The temporal variation is defined as the variation in the change of the variable conductance of one of the variable resistive elements R (shown inFIG. 1) as a result of variation in the temporal length of an applied voltage pulse used to change the variable conductance. More specifically,FIG. 7Billustrates curves that graph recognition accuracy versus the standard deviation of the variable conductance due to temporal variation. The curve TV1, curve TV2, curve TV3, and curve TV4each are provided with different degrees of non-linearity in the variable conductance due to the effects of LTP and LTD. The curve TV1was provided in the ideal case with no non-linearity in the variable conductance (i.e., linear). The curve TV2is provided with more non-linearity in the variable conductance curve than the curve TV1but less than with the curves TV3, TV4. Curve TV3is provided with more non-linearity in the variable conductance curve than the curves TV1, TV2but less than with the curves TV4. Curve TV4is provided with more non-linearity in the variable conductance curve than the curves TV1, TV2, TV3. The curves TV1, TV2, TV2, TV4inFIG. 7Bshow that larger temporal variation can have a significant effect on recognition accuracy which is exacerbated by non-linearity. Temporal variation is inherently stochastic in nature and thus the SC algorithm has less resilience to these types of non-deterministic disturbances. Techniques may be utilized to ameliorate the effects of temporal variation as described in further detail below.

FIGS. 8A and 8B,FIGS. 9A and 9B, andFIGS. 10A and 10Billustrate different pulse schemes applied to each one of the variable resistive element R shown inFIG. 1in order to change the variable conductance of the variable resistive element R from one conductance state to another conductance state. It should be noted that the pulse schemes inFIGS. 8A-10Bare discussed with regards to individual variable resistive elements R (shown inFIG. 1) since with respect toFIG. 1, a matrix value of the D matrix is represented by a single variable resistive element R and therefore each variable resistive element R makes up a variable resistive unit. However, as explained below, groups (such as subarrays) of the variable resistive elements R may be used to represent a matrix value of the D matrix and thus the combined variable conductance of a group (e.g., subarrays) of the variable resistive elements R would be used to represent a matrix value of the D matrix. The techniques described herein are equally applicable to variable resistive units each having group (e.g., subarrays) of the variable resistive elements R. Furthermore, with regards toFIGS. 8A-10B, the variable resistive elements R are presumed to be TaOx/TiO2RRAM elements.

Referring now toFIG. 8AandFIG. 8B,FIG. 8AandFIG. 8Billustrate a technique where a pulse train of pulses (referred to generically as pulses P8and specifically as pulses P8A1, P8A2, P8A3, P8B1, P8B2, P8B3) are utilized to change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from one conductance state to another conductance state. Each of the pulses P8inFIGS. 8A and 8Bare approximately the same temporal length (e.g., 2 ms) and each of the pulses P8change the variable conductance to an adjacent conductance state.

More specifically,FIG. 8Aillustrate pulses P8A1, P8A2, P8A3that each change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from one conductance state to the next highest conductance state. For the sake of clarity, the change from one conductance state to the next highest conductance state is referred to as an increasing conductance step +ΔGS. The pulses P8A1, P8A2, P8A3thus change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) by three increasing conductance steps +ΔGS. In particular, the pulse P8A1changes the variable conductance of the variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from a conductance state (referred to for the sake of clarity as conductance state 1) to the next highest conductance state (referred to for the sake of clarity as conductance state 2) and thus by one increasing conductance step +ΔGS. The pulse P8A2changes the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) from that conductance state (e.g., conductance state 2) to the next highest conductance state (referred to for the sake of clarity as conductance state 3) and thus by one increasing conductance step +ΔGS. Finally, the pulse P8A3changes the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) from that conductance state (e.g., conductance state 3) to the next highest conductance state (referred to for the sake of clarity as conductance state 4).

Each of the pulses P8A1, P8A2, P8A3is the same temporal length (e.g., 2 ms in the specific embodiment shown inFIG. 8A) and has the same positive voltage magnitude (e.g., 2.8V in the specific embodiment shown inFIG. 8A). The pulses P8A1, P8A2, P8A3are all provided during one conductance update cycle in order change the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) by three increasing conductance steps +ΔGS. Clearly,FIG. 8Ais simply an example as more or less of the pulses P8A1, P8A2, P8A3may be provided if the variable conductance is changed by more or less than three increasing conductance steps +ΔGS. Obviously then, the number of pulses provided during a conductance update cycle is dependent on the number of conductance states (e.g., for example three with regard to the example inFIG. 8A) between the conductance state (e.g., conductance state 1) at the beginning of the conductance update cycle and the target conductance state (e.g., conductance state 4) at the end of the conductance update cycle.

With regard toFIG. 8B,FIG. 8Billustrate pulses P8B1, P8B2, P8B3that each change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from one conductance state to the next lowest conductance state. For the sake of clarity, the change from one conductance state to the next lowest conductance state is referred to as a decreasing conductance step −ΔGS. The pulses P8B1, P8B2, P8B3thus change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) by three decreasing conductance steps −ΔGS. In particular, the pulse P8B1changes the variable conductance of the variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from a conductance state (e.g., conductance state 4) to the next lowest conductance state (e.g., conductance state 3) and thus by one decreasing conductance step −ΔGS. The pulse P8B2changes the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) from that conductance state (e.g., conductance state 3) to the next lowest conductance state (e.g., conductance state 2) and thus by one decreasing conductance step −ΔGS. Finally, the pulse P8B3changes the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) from that conductance state (e.g., conductance state 2) to the next lowest conductance state (e.g., conductance state 1).

Each of the pulses P8B1, P8B2, P8B3is the same temporal length (e.g., 2 ms in the specific embodiment shown inFIG. 8B) and has the same negative voltage magnitude (e.g., −2.8V in the specific embodiment shown inFIG. 8B). The pulses P8B1, P8B2, P8B3are all provided during one conductance update cycle in order change the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) by three decreasing conductance steps −ΔGS. Clearly,FIG. 8Bis simply an example as more or less of the pulses P8B1, P8B2, P8B3may be provided if the variable conductance is changed by more or less than three decreasing conductance steps −ΔGS. Obviously then, the number of pulses provided during a conductance update cycle is dependent on the number of conductance states (e.g., for example three with regard to the example inFIG. 8B) between the conductance state (e.g., conductance state 4) at the beginning of the conductance update cycle and the target conductance state (e.g., conductance state 1) at the end of the conductance update cycle.

Referring now toFIG. 9AandFIG. 9B,FIG. 9AandFIG. 9Billustrate a technique where a pulse train of pulses (referred to generically as pulses P9and specifically as pulses P9AP1, P9AN1, P9AP2, P9AN2, P9BN1, P9BP1, P9BN2, P9BP2) are utilized to change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from a current conductance state to a target conductance state. The pulses P9inFIGS. 9A and 9Bare provided in pairs of temporally adjacent pulses P9, where each pair of the pulses P9has a positive pulse (e.g., P9AP1, P9AP2, P9BP1, P9BP2) and a negative pulse (e.g., P9AN1, P9AN2, P9BN1, P9BN2).

With respect toFIG. 9A,FIG. 9Aillustrates pulses P9AP1, P9AN1, P9AP2, P9AN2. The pulse P9AP1and the pulse P9AP2are each positive pulses having the same temporal length (e.g., 10 ms inFIG. 9A) and positive voltage amplitude (e.g., 3V inFIG. 9A). The pulse P9AN1and the pulse P9AN2are each negative pulses having the same temporal length (e.g., 5 ms inFIG. 9A) and negative voltage amplitude (e.g., −2V inFIG. 9A). The temporal length (e.g., 10 ms) of the positive pulses P9AP1, P9AP2is greater than the temporal length (e.g. 5 ms) of the negative pulses P9AN1, P9AN2. Furthermore, a voltage magnitude (e.g., |3V|) of the positive pulses P9AP1, P9AP2is greater than of the voltage magnitude (e.g., |2V|) of the voltage amplitude of the negative pulses P9AN1, P9AN2.

The pulse P9AP1and the pulse P9AN1(referred to collectively as pulse pair PP1) are a pair of temporally adjacent pulses used to change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from one conductance state to the next highest conductance state and thus an increasing conductance step +ΔGS. Furthermore, pulse P9AP2and the pulse P9AN2(referred to collectively as pulse pair PP2) are also a pair of temporally adjacent pulses used to change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from one conductance state to the next highest conductance state and thus an increasing conductance step +ΔGS. Together the pulse pairs PP1, PP2thus change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) by two increasing conductance steps +ΔGS. In particular, the pulse pair PP1changes the variable conductance of the variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from a conductance state (e.g., conductance state 1) to the next highest conductance state (e.g., conductance state 2) and thus by one increasing conductance step +ΔGS. Additionally, the pulse PP2changes the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) from that conductance state (e.g., conductance state 2) to the next highest conductance state (e.g., conductance state 3) and thus by another increasing conductance step +ΔGS.

The pulse pairs PP1, PP2are all provided during one conductance update cycle in order change the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) by two increasing conductance steps +ΔGS. Clearly,FIG. 9Ais simply an example as more or less of the pulse pairs PP1, PP2may be provided if the variable conductance is changed by more or less than three increasing conductance steps +ΔGS. Obviously then, the number of pulse pairs provided during a conductance update cycle is dependent on the number of conductance states (e.g., for example two with regard to the example inFIG. 9A) between the conductance state (e.g., conductance state 1) at the beginning of the conductance update cycle and the target conductance state (e.g., conductance state 3) at the end of the conductance update cycle.

With respect toFIG. 9B,FIG. 9Billustrates pulses P9BP1, P9BN1, P9BP2, P9BN2. The pulse P9BP1and the pulse P9BP2are each negative pulses having the same temporal length (e.g., 10 ms inFIG. 9B) and negative voltage amplitude (e.g., −3V inFIG. 9B). The pulse P9BN1and the pulse P9BN2are each positive pulses having the same temporal length (e.g., 5 ms inFIG. 9B) and positive voltage amplitude (e.g., 2V inFIG. 9B). The temporal length (e.g., 10 ms) of the negative pulses P9BP1, P9BP2is greater than the temporal length (e.g. 5 ms) of the positive pulses P9BN1, P9BN2. Furthermore, a voltage magnitude (e.g., |3V|) of the negative pulses P9BP1, P9BP2is greater than of the voltage magnitude (e.g., |2V|) of the voltage amplitude of the positive pulses P9BN1, P9BN2.

The pulse P9BP1and the pulse P9BN1(referred to collectively as pulse pair PN1) are a pair of temporally adjacent pulses used to change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from one conductance state to the next lowest conductance state and thus a decreasing conductance step −ΔGS. Furthermore, pulse P9BP2and the pulse P9BN2(referred to collectively as pulse pair PN2) are also a pair of temporally adjacent pulses used to change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from one conductance state to the next lowest conductance state and thus a decreasing conductance step −ΔGS. Together the pulse pairs PN1, PN2thus change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) by two decreasing conductance steps −ΔGS. In particular, the pulse pair PN1changes the variable conductance of the variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from a conductance state (e.g., conductance state 3) to the next lowest conductance state (e.g., conductance state 2) and thus by one decreasing conductance step −ΔGS. Additionally, the pulse PN2changes the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) from that conductance state (e.g., conductance state 2) to the next lowest conductance state (e.g., conductance state 1) and thus by another decreasing conductance step −ΔGS.

The pulse pairs PN1, PN2are all provided during one conductance update cycle in order change the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) by two decreasing conductance steps −ΔGS. Clearly,FIG. 9Bis simply an example as more or less of the pulse pairs PN1, PN2may be provided if the variable conductance is changed by more or less than three decreasing conductance steps −ΔGS. Obviously then, the number of pulse pairs provided during a conductance update cycle is dependent on the number of conductance states (e.g., for example two with regard to the example inFIG. 9B) between the conductance state (e.g., conductance state 3) at the beginning of the conductance update cycle and the target conductance state (e.g., conductance state 1) at the end of the conductance update cycle.

Referring now toFIG. 10AandFIG. 10B,FIG. 10AandFIG. 10Billustrate a technique where a pulse train of pulses (referred to generically as pulses P10and specifically as pulses P10A1, P10A2, P10B1, P10B2) are utilized to change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from one conductance state to another conductance state. Each of the pulses P10inFIGS. 10A and 10Bare approximately the same temporal length (e.g., 2 ms) and each of the pulses P10change the variable conductance to an adjacent conductance state.

More specifically,FIG. 10Aillustrate pulses P10A1, P10A2that each change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from one conductance state to the next highest conductance state. For the sake of clarity, the change from one conductance state to the next highest conductance state is referred to as an increasing conductance step +ΔGS. The pulses P10A1, P10A2thus change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) by two increasing conductance steps +ΔGS. In particular, the pulse P10A1changes the variable conductance of the variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from a conductance state (referred to for the sake of clarity as conductance state 1) to the next highest conductance state (referred to for the sake of clarity as conductance state 2) and thus by one increasing conductance step +ΔGS. The pulse P10A2changes the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) from that conductance state (e.g., conductance state 2) to the next highest conductance state (referred to for the sake of clarity as conductance state 3) and thus by one increasing conductance step +ΔGS. Finally, the pulse P10A3changes the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) from that conductance state (e.g., conductance state 3) to the next highest conductance state (referred to for the sake of clarity as conductance state 4).

Each of the pulses P10A1, P10A2has the same positive voltage magnitude (e.g., 3V in the specific embodiment shown inFIG. 10A). The pulses P10A1, P10A2are all provided during one conductance update cycle in order change the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) by two increasing conductance steps +ΔGS. Clearly,FIG. 10Ais simply an example as more or less of the pulses P10A1, P10A2may be provided if the variable conductance is changed by more or less than two increasing conductance steps +ΔGS. Obviously then, the number of pulses provided during a conductance update cycle is dependent on the number of conductance states (e.g., for example two with regard to the example inFIG. 10A) between the conductance state (e.g., conductance state 1) at the beginning of the conductance update cycle and the target conductance state (e.g., conductance state 3) at the end of the conductance update cycle.

However, the pulses P10A1, P10A2each have a different temporal duration. The temporal duration of the P10A1, P10A2is determined by Equation (6) inFIG. 4. In Equation (6), the pulse duration (PD) is empirically determined in accordance with an initial pulse duration (Pi), the current conductance state, and an integer m that indicates a non-linearity factor. An integer n is an integer that identifies the current conductance state by providing an integer number that identifies where the current conductance state ranks relative to an ordered set of all of the possible conductance states. For example, when Equation (6) is used for potentiation to increase the conductance state, the lowest integer value of zero (0) of n indicates the minimum conductance state Gminwhile the highest integer value of n (e.g., 63 if there are 64 possible conductance states) indicates the maximum conductance state Gmax. Each of the possible integer values (e.g., 1-62) of n between the lowest integer value (0) to the highest integer value indicate conductance states between the minimum conductance state Gminand the maximum conductance state Gmaxwhere increasing integer values of n increase correspond bijectively to increasing conductance states between the minimum conductance state Gminand the maximum conductance state Gmax. Accordingly, the integer value (n+1) indicates the integer value identifying the next highest conductance state greater than the current conductance state. The initial pulse duration Piindicates the temporal duration required to change the variable conductance from the minimum conductance state Gminto the lowest possible conductance state (indicated by n=1) greater than the minimum conductance state Gmin. Finally, the integer value m is empirically determined and in this example is equal to 6.

With regard toFIG. 10B,FIG. 10Billustrate pulses P10B1, P10B2, that each change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from one conductance state to the next lowest conductance state. For the sake of clarity, the change from one conductance state to the next lowest conductance state is referred to as a decreasing conductance step −ΔGS. The pulses P10B1, P10B2thus change the variable conductance of a variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) by two decreasing conductance steps −ΔGS. In particular, the pulse P10B1changes the variable conductance of the variable resistive unit (i.e., a single variable resistive element R for the embodiment inFIG. 1) from a conductance state (e.g., conductance state 3) to the next lowest conductance state (e.g., conductance state 2) and thus by one decreasing conductance step −ΔGS. The pulse P10B2changes the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) from that conductance state (e.g., conductance state 2) to the next lowest conductance state (e.g., conductance state 1) and thus by another decreasing conductance step −ΔGS.

Each of the pulses P10B1, P10B2has the same negative voltage magnitude (e.g., −2.5V in the specific embodiment shown inFIG. 10B). The pulses P10B1, P10B2are all provided during one conductance update cycle in order change the variable conductance of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) by two increasing conductance steps +ΔGS. Clearly,FIG. 10Bis simply an example as more or less of the pulses P10B1, P10B2may be provided if the variable conductance is changed by more or less than two increasing conductance steps +ΔGS. Obviously then, the number of pulses provided during a conductance update cycle is dependent on the number of conductance states (e.g., for example two with regard to the example inFIG. 10B) between the conductance state (e.g., conductance state 1) at the beginning of the conductance update cycle and the target conductance state (e.g., conductance state 3) at the end of the conductance update cycle.

However, the pulses P10B1, P10B2each have a different temporal duration. The temporal duration of the P10B1, P10B2is also determined by Equation (6) inFIG. 4. In Equation (6), the pulse duration (PD) is empirically determined in accordance with an initial pulse duration (Pi), the current conductance state, and an integer m that indicates a non-linearity factor. The integer n identifies the current conductance state by providing an integer number that identifies where the current conductance state ranks relative to an ordered set of all of the possible conductance states. However, when Equation (6) is used for depression to decrease the conductance state, the lowest integer value of zero (0) of n indicates the maximum conductance state Gmaxwhile the highest integer value of n (e.g., 63 if there are 64 possible conductance states) indicates the minimum conductance state Gmin. Each of the possible integer values (e.g., 1-62) of n between the lowest integer value (0) to the highest integer value (e.g. 63) indicate conductance states between the maximum conductance state Gmaxand the minimum conductance state Gminwhere increasing integer values of n increase correspond bijectively to decreasing conductance states between the maximum conductance state Gmaxand the minimum conductance state Gmin. Accordingly, the integer value (n+1) indicates the integer value identifying the next lowest conductance state less than the current conductance state. The initial pulse duration Piindicates the temporal duration required to change the variable conductance from the maximum conductance state Gmaxto the highest possible conductance state (indicated by n=1) lower than the maximum conductance state Gmax. Finally, the integer value m is empirically determined and in this example is equal to 4.

FIG. 11illustrates exemplary curves CV8A, CV8B, CV9A, CV9B, CV10A, CV10B ofFIG. 11that graph a normalized variable conductance of a variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) as a function of the integer n indicating the conductance state. Curve CV8A is the result of adjusting the variable conductance state from the minimum conductance state Gminto the maximum conductance state Gmaxusing the pulse scheme described above with respect toFIG. 8A. Curve CV8B is the result of adjusting the variable conductance state from the maximum conductance state Gmaxto the minimum conductance state Gminusing the pulse scheme described above with respect toFIG. 8B. Curve CV9A is the result of adjusting the variable conductance state from the minimum conductance state Gminto the maximum conductance state Gmaxusing the pulse scheme described above with respect toFIG. 9A. Curve CV9B is the result of adjusting the variable conductance state from the maximum conductance state Gmaxto the minimum conductance state Gminusing the pulse scheme described above with respect toFIG. 9B. Curve CV10A is the result of adjusting the variable conductance state from the minimum conductance state Gminto the maximum conductance state Gmaxusing the pulse scheme described above with respect toFIG. 10A. Curve CV10B is the result of adjusting the variable conductance state from the maximum conductance state Gmaxto the minimum conductance state Gminusing the pulse scheme described above with respect toFIG. 10B.

Accordingly, the pulse scheme utilized to change the variable conductance inFIG. 8AandFIG. 8Buses a simple pulse train for both the potentiation and depression where each of the pulses (e.g., the pulses P8A1, P8A2, P8A3shown inFIG. 8A) for potentiation are substantially identical and each of the pulses (e.g., the pulses P8B1, P8B2, P8B3shown inFIG. 8B) for depression are substantially identical. This results in the greatest non-linearity as the amount of change in the variable conductance between adjacent conductance states will be different due to non-linearity of the variable conductance and the fact that the pulses are all the same temporal duration. For example, an amount of increase in the variable conductance due to each increasing conductance step +ΔGS using the pulse scheme described above with respectFIG. 8Awill be substantially different depending on which conductance state is the current conductance state. Additionally, an amount of the matrix Decrease in the variable conductance due to each decreasing conductance step −ΔGS using the pulse scheme described above with respectFIG. 8Bwill also be substantially different depending on which conductance state is the current conductance state.

Next, the pulse scheme utilized to change the variable conductance inFIG. 9AandFIG. 9Buses pulse pairs (e.g., the pulses PP1, PP2inFIG. 9A) for potentiation and pulse pairs (e.g., the pulses PN1, PN2inFIG. 9B) for depression. The pulse pair helps ameliorate the drift and diffusion variation of ions and holes resulting from spatial and temporal variation and thereby reduces non-linearity. However, non-linearity still remains and thus also results in the amount of change in the variable conductance between adjacent conductance states being different. For example, an amount of increase in the variable conductance due to each increasing conductance step +ΔGS using the pulse scheme described above with respectFIG. 9Awill be substantially different depending on which conductance state is the current conductance state. Additionally, an amount of increase in the variable conductance due to each decreasing conductance step −ΔGS using the pulse scheme described above with respectFIG. 9Bwill also be substantially different depending on which conductance state is the current conductance state. As shown byFIG. 11, the pulse schemes described inFIGS. 9A and 9Bhave the less non-linearity than the pulse scheme described inFIGS. 8A and 8B. Since the pulse schemes described inFIGS. 9A and 9Bhave some resilience to spatial and temporal variation, the pulse scheme described byFIGS. 9A and 9Bcould be utilized in some practical implementations.

Finally, the pulse scheme utilized to change the variable conductance inFIG. 10AandFIG. 10Buses a simple pulse train for both the potentiation and depression where a pulse duration of each of the pulses (e.g., the pulses P10A1, P10A2, shown inFIG. 10A) for potentiation and each of the pulses (e.g., the pulses P10B1, P10B2, P10B3shown inFIG. 10B) for depression are determined in accordance with Equation (6), which takes into account non-linearity resulting from spatial and temporal variation. Accordingly, curves CV10A and CV10B are substantially linear. This results in an amount of increase in the variable conductance due to each increasing conductance step +ΔGS using the pulse scheme described above with respectFIG. 10Abeing substantially the same. Additionally, an amount of the matrix Decrease in the variable conductance due to each decreasing conductance step −ΔGS using the pulse scheme described above with respectFIG. 10Bwill also be substantially the same.

However, to provide this non-linearity, the peripheral digital computational circuitry28(shown inFIG. 1) needs to make a conductance measurement indicating the current conductance state of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) before changing the current conductance state of the variable resistive unit. The peripheral digital computational circuitry28is configured to determine the target conductance state of the variable resistive unit (i.e., the single variable resistive element R for the embodiment inFIG. 1) in accordance with the learning algorithm described above. Once the conductance measurement is provided and the target conductance state has been determined, the peripheral digital computational circuitry28is configured to determine the pulse duration of each the pulses in accordance to Equation (6). From the conductance measurement, the peripheral digital computational circuitry28can determine the current conductance state and thus the current integer value of n that identifies the current conductance state. Using the current integer value of n based on the conductance measurement, the peripheral digital computational circuitry28is configured to determine the temporal duration of the initial pulse to be generated during the conductance update cycle needed to change the current conductance state to the next highest conductance state (in case of potentiation) or the next lowest conductance state (in the case of the matrix Depression). If other pulses in addition to the first pulse are needed to change the current conductance state to the target conductance state during a conductance update cycle, the pulse duration of each of these pulses is also determined in accordance with Equation (6). However, the integer value of n for these pulses is determined in accordance to Equation (6) simply incrementing the integer value of n determined from the conductance measurement. Thus, the duration of each of the pulses generated during a conductance update cycle is also based on the conductance measurement. The pulse schemes described above with respect toFIGS. 10A and 10Bare thus clearly the pulse schemes with the greatest recognition accuracy that can provide the most recognition accuracy. However, pulse schemes described above with respect toFIGS. 10A and 10Bare a more complicated because these pulse schemes require a read before write step to determine the current conductance state of the variable resistive unit.

FIG. 12illustrates another exemplary embodiment of the neuromorphic computational circuitry NCC having another embodiment of the resistive memory system10that is configured to implement matrix vector product operations and weight update operations in parallel. The resistive memory system10shown inFIG. 12includes the cross point resistive network12, the word line control circuitry70, the bit line control circuitry20and the peripheral digital computational circuitry28described above with respect toFIG. 1. However, the resistive memory system10shown inFIG. 12includes switchable paths WS12, WS23, WS34, WS45, WS56, WSX-1X, BS12, BS23, BS34, BS45, BS56, and BSY-1Y (referred to generically as switchable paths W/BS). Thus, unlike the resistive memory system10shown inFIG. 1, the resistive memory system10shown inFIG. 12can represent the matrix values of the matrix D with either just the variable conductance of individual variable resistive elements (like the resistive memory system10shown inFIG. 1) or with a combined variable conductance of groups of the individual resistive elements R. Accordingly, a variable resistive unit inFIG. 12can be provided as either an individual variable resistive element or with a group (e.g., subarrays) of the variable resistive elements R.

With respect to the bit line control circuitry20, the bit line switch SB1is connected between the bit line controller24-1and the bit line BL1. The bit line switch SB2is connected between the bit line controller24-2and the bit line BL2. The bit line switch SB3is connected between the bit line controller24-3and the bit line BL3. The bit line switch SB4is connected between the bit line controller24-4and the bit line BL4. The bit line switch SB5is connected between the bit line controller24-5and the bit line BL5. The bit line switch SB6is connected between the bit line controller24-6and the bit line BL6. The bit line switch SBY is connected between the bit line controller24-Y and the bit line BLY.

Each of the word line switches SW and each of the bit line switches SB is configured to be opened and closed. In this manner, the switch control circuitry70is configured to generate a switch control output72that is configured to open and close the word line switches SW and the bit line switches SB based on the size of the subarrays selected by the switch control output72. In this manner, the peripheral digital computational circuitry28(shown inFIG. 3) is configured to change arrangement of the variable resistive elements R that provide a variable resistive unit. The word line controllers22are interconnected by the word line switches SW to the word lines WL so that one of the word line controllers22is provided per row of subarrays while the remainder of the word line controllers22per row of subarrays are decoupled by the word line switches SW. The bit line controllers24are interconnected by the bit line switches SB to the bit lines BL so that one of the bit line controllers24is provided per column of subarrays while the remainder of the bit line controllers24per column of subarrays are decoupled by the bit line switches SB.

To demonstrate, in one exemplary implementation, all of the switchable paths W/BS are open, and thus the variable conductance of each of the switchable paths W/BS represents a different corresponding matrix value of the matrix D. In exemplary implementation, the integer number m of the matrix D would be equal to X, and the integer number p of the matrix D would be equal to Y. However, the switchable paths W/BS are connected to the conductive lines W/BL so that the plurality of switchable paths W/BS are operable to selectively interconnect one or more groups of the conductive lines W/BL such that one or more sets of the variable resistive elements R provide one or more combined variable conductances. Thus, each set of the variable resistive elements R has a combined variable conductance, which can be used to represent one of the matrix values of the matrix D. Thus, multiple variable resistive elements R can be used to represent a single matrix value of the matrix D and thus multiple variable resistive elements R provide a variable resistive unit. This is advantageous because the combined variable conductance of multiple resistive elements R averages out process variations in the variable conductance of the individual resistive elements R. Thus, by using multiple resistive elements R to represent each matrix value of the matrix D, the impact of both temporal and spatial variation can be significantly reduced. However, the techniques and methods for operating the resistive memory system10shown inFIG. 12are the same as described above for the resistive memory system10shown inFIG. 1and described above with respect toFIGS. 1-11.

Nevertheless, using multiple resistive elements R to represent each matrix value of the matrix D can have an impact on energy requirements, area requirements, and latency. Accordingly, the switchable paths W/BS are operable to selectively interconnect different combinations of the conductive lines W/BL of the variable resistive elements R so that the sets of variable resistive elements R are reconfigurable as different combinations of the variable resistive elements R. Thus, the switchable paths W/BS allow for optimization of the resistive memory system10. More specifically, each of the switchable paths W/BS is configured to be opened and closed and is connected between a corresponding pair of the conductive lines W/BL. When one of the switchable paths W/BS is opened, the pair of conductive lines W/BL it is connected to is decoupled, and thus the pair of conductive lines W/BL operates as separate conductive lines W/BL. However, when the switchable conductive paths are closed, the pair of conductive lines W/BL is interconnected, and thus the variable resistive elements R can be grouped to provide the combined variable conductance.

In the embodiment shown inFIG. 12, the switchable paths W/BS include switchable word line interconnection paths WS12, WS23, WS34, WS45, WS56, WSX-1X (referred to generically as switchable word line interconnection paths WS) and switchable bit line interconnection paths BS12, BS23, BS34, BS45, BS56, and BSY-1Y (referred to generically as switchable word line interconnection paths BS). More specifically, the switchable word line interconnection path WS12is connected between the word line WL1and the word line WL2. The switchable word line interconnection path WS12is configured to selectively interconnect the word line WL1and the word line WL2. As such, when the switchable word line interconnection path WS12is open, the word line WL1and the word line WL2are decoupled. However, when the switchable word line interconnection path WS12is closed, the word line WL1and the word line WL2are interconnected and thus essentially operate as a merged word line.

The switchable word line interconnection path WS23is connected between the word line WL2and the word line WL3. The switchable word line interconnection path WS23is configured to selectively interconnect the word line WL2and the word line WL3. As such, when the switchable word line interconnection path WS23is open, the word line WL2and the word line WL3are decoupled. However, when the switchable word line interconnection path WS23is closed, the word line WL2and the word line WL3are interconnected and thus essentially operate as a merged word line.

The switchable word line interconnection path WL34is connected between the word line WL3and the word line WL4. The switchable word line interconnection path WL34is configured to selectively interconnect the word line WL3and the word line WL4. As such, when the switchable word line interconnection path WL34is open, the word line WL3and the word line WL4are decoupled. However, when the switchable word line interconnection path WL34is closed, the word line WL3and the word line WL4are interconnected and thus essentially operate as a merged word line.

The switchable word line interconnection path WS45is connected between the word line WL4and the word line WL5. The switchable word line interconnection path WS45is configured to selectively interconnect the word line WL4and the word line WL5. As such, when the switchable word line interconnection path WS45is open, the word line WL4and the word line WL5are decoupled. However, when the switchable word line interconnection path WS45is closed, the word line WL4and the word line WL5are interconnected and thus essentially operate as a merged word line.

The switchable word line interconnection path WS56is connected between the word line WL5and the word line WL6. The switchable word line interconnection path WS56is configured to selectively interconnect the word line WL5and the word line WL6. As such, when the switchable word line interconnection path WS56is open, the word line WL5and the word line WL6are decoupled. However, when the switchable word line interconnection path WS56is closed, the word line WL5and the word line WL6are interconnected and thus essentially operate as a merged word line.

The switchable word line interconnection path WSX-1X is connected between the word line WLX-1(not explicitly shown inFIG. 12) and the word line WLX. The switchable word line interconnection path WSX-1X is configured to selectively interconnect the word line WLX-1and the word line WLX. As such, when the switchable word line interconnection path WSX-1X is open, the word line WLX-1and the word line WLX are decoupled. However, when the switchable word line interconnection path WSX-1X is closed, the word line WLX-1and the word line WLX are interconnected and thus essentially operate as a merged word line.

The switchable bit line interconnection path BS12is connected between the bit line BL1and the bit line BL2. The switchable bit line interconnection path BS12is configured to selectively interconnect the bit line BL1and the bit line BL2. As such, when the switchable bit line interconnection path BS12is open, the bit line BL1and the bit line BL2are decoupled. However, when the switchable bit line interconnection path BS12is closed, the bit line BL1and the bit line BL2are interconnected and thus essentially operate as a merged bit line.

The switchable bit line interconnection path BS23is connected between the bit line BL2and the bit line BL3. The switchable bit line interconnection path BS23is configured to selectively interconnect the bit line BL2and the bit line BL3. As such, when the switchable bit line interconnection path BS23is open, the bit line BL2and the bit line BL3are decoupled. However, when the switchable bit line interconnection path BS23is closed, the bit line BL2and the bit line BL3are interconnected and thus essentially operate as a merged bit line.

The switchable bit line interconnection path BL34is connected between the bit line BL3and the bit line BL4. The switchable bit line interconnection path BL34is configured to selectively interconnect the bit line BL3and the bit line BL4. As such, when the switchable bit line interconnection path BL34is open, the bit line BL3and the bit line BL4are decoupled. However, when the switchable bit line interconnection path BL34is closed, the bit line BL3and the bit line BL4are interconnected and thus essentially operate as a merged bit line.

The switchable bit line interconnection path BS45is connected between the bit line BL4and the bit line BL5. The switchable bit line interconnection path BS45is configured to selectively interconnect the bit line BL4and the bit line BL5. As such, when the switchable bit line interconnection path BS45is open, the bit line BL4and the bit line BL5are decoupled. However, when the switchable bit line interconnection path BS45is closed, the bit line BL4and the bit line BL5are interconnected and thus essentially operate as a merged bit line.

The switchable bit line interconnection path BS56is connected between the bit line BL5and the bit line BL6. The switchable bit line interconnection path BS56is configured to selectively interconnect the bit line BL5and the bit line BL6. As such, when the switchable bit line interconnection path BS56is open, the bit line BL5and the bit line BL6are decoupled. However, when the switchable bit line interconnection path BS56is closed, the bit line BL5and the bit line BL6are interconnected and thus essentially operate as a merged bit line.

The switchable bit line interconnection path BSY-1Y is connected between the bit line BLY-1(not explicitly shown inFIG. 12) and the bit line BLY. The switchable bit line interconnection path BSY-1Y is configured to selectively interconnect the bit line BLY-1and the bit line BLY. As such, when the switchable bit line interconnection path BSY-1Y is open, the bit line BLY-1and the bit line BLY are decoupled. However, when the switchable bit line interconnection path BSY-1Y is closed, the bit line BLY-1and the bit line BLY are interconnected and thus essentially operate as a merged bit line.

In this manner, each of the word line interconnection paths WS and switchable bit line interconnection paths BS are configured to be opened and closed such that different combinations of the variable resistive elements R are selectively interconnected so that each of the subarrays of the variable resistive elements R provides a corresponding combined variable conductance that represents a corresponding matrix value of the matrix D. All of the subarrays thus provide combined variable conductances within the cross point resistive network12(i.e., the cross point resistive array in this embodiment), which represent the matrix D. In other words, each subarray represents a different matrix value. The resistive memory units are thus reconfigurable into any combination of variable resistive elements R such as, individual variable resistive elements R or such as 1×2, 1×3, 2×1, 2×2, 2×3, 3×1, 3×2, 3×3 subarrays of the variable resistive elements R. Selecting the appropriate implementation of subarrays could be done using scan cells, which allow post-fabrication tuning based on process variation data. This reconfigurability adds a great amount of flexibility that could optimize the number of variable resistive elements R (and thus the area and energy needed to represent a matrix value) in the subarrays versus accuracy requirements for a given application.

The peripheral digital computational circuitry28includes the switch control circuitry70(shown inFIG. 3) configured to open and close the switchable paths W/BS and thus select a particular combination of the subarrays. In this embodiment, the switch control circuitry70is configured to generate a switch control output16. The switch control output16is operable to open and close the switchable paths W/BS. Thus, different permutations of the switch control output72may open and close different combinations of the switchable paths W/BS and thus provide different combinations of the variable resistive elements R in the subarrays that provide the variable resistive units.

For example, if all of the switchable paths W/BS are opened, then the variable resistive units are selected to be individual variable resistive elements R. As such, the variable conductance of every one of the variable resistive elements R will represent a different matrix value of the matrix D. Thus, the integer number m will equal the integer number X, and the integer number p will equal the integer number Y. In this case, to perform the different matrix operations, the word line output includes each of the word line voltages VW1, VW2, VW3, VW4, VW5, VW6, VWX (referred to generically as word line voltages VW), and the bit line output includes all of the bit line voltages VB1, VB2, VB3, VB4, VB5, VB6, VBY, as described above with respect to the resistive memory system10shown inFIG. 1.

Referring again toFIG. 12, different patterns of the words lines WL and different patterns of the bit lines BL may be interconnected so that different sized subarrays are provided to create combined variable conductances that represent the matrix values of the matrix D when the integer number m and the integer number p are changed. However, if at least some of the switchable paths W/BS are closed so that the subarrays include blocks of the variable resistive elements R with multiple resistive elements R, then the integer number m and the integer number p will depend on the size of the subarrays. It should be noted that for the sake of explanation, a particular implementation is discussed with respect toFIG. 12where the variable resistive units are selected to be 3×3 subarrays of the variable resistive elements R. Clearly, this is simply exemplary as the variable resistive units can be selected by the peripheral digital computational circuitry28to be subarrays of the variable resistive elements R of any size. The concepts, methods, and techniques described with respect to the 3×3 subarrays are equally applicable regardless of the size of the subarrays selected to provide the variable resistive units.

Every mutually exclusive set of three adjacent word line switches WS and every mutually exclusive set of three adjacent bit line switches BS can be opened and closed in accordance with a pattern that provides the variable resistive units as the 3×3 subarrays of the variable resistive elements R. In accordance with the pattern, the first and the second word line switches WS of the three adjacent word line switches WS are closed, and the third word line switch WS of the three adjacent word line switches is opened. Furthermore, the first and the second bit line switches BS in the three adjacent switches BS are closed, and the third bit line switch BS of the three adjacent switches is open. By following the pattern for every mutually exclusive set of three adjacent word lines switches WS and for every mutually exclusive set of three adjacent bit line switches, the variable resistive units are selected to be 3×3 subarrays of the variable resistive elements. To illustrate, when following the above mentioned pattern, the word line switches WS12, WS23would be closed, and the word line switch WS34would be opened. Similarly, the bit line switches6S12, BS23would be closed, and the word line switch BS34would be opened. Accordingly, the word lines WL1, WL2, WL3would be interconnected while the word line WL4is decoupled from the word lines WL1, WL2, WL3and the bit lines BL1, BL2, BL3would be interconnected while the bit line BL4would be decoupled from the bit lines BL1, BL2, BL3,

Each of the matrix values of the matrix D are represented by a different corresponding one of the combined variable conductances provided by the other 3×3 subarrays that are not interconnected to the bit line BLY. Thus, when the variable resistive units are 3×3 subarrays of the variable resistive elements R, the combined variable conductances of a column of the 3×3 subarrays interconnected to the bit line BL3represent a corresponding column of the matrix values of the matrix D. Additionally, the combined variable conductances of a column of the 3×3 subarrays interconnected to the bit line BL6represent another corresponding column of the matrix values of the matrix D.

The column of the 3×3 subarrays interconnected to the bit line BL3includes a 3×3 subarray having the variable resistive elements R11, R12, R13, R21, R22, R23, R31, R32, R33, a 3×3 subarray having the variable resistive elements R41, R42, R43, R51, R52, R53, R61, R62, R63, and a 3×3 subarray having the variable resistive elements RX-21(not explicitly shown inFIG. 12), RX-22(not explicitly shown inFIG. 12), RX-23(not explicitly shown inFIG. 12), RX-11(not explicitly shown inFIG. 12), RX-12(not explicitly shown inFIG. 12), RX-13(not explicitly shown inFIG. 12), RX1, RX2, RX3. Each of combined variable conductances of the 3×3 subarrays interconnected to the bit line BL3represent a corresponding one of the matrix values in the corresponding column of the matrix D. During a D·Z operation, the column of the 3×3 subarrays interconnected to the bit line BL3is configured to generate the bit line current IR3.

Additionally, the column of the 3×3 subarrays interconnected to the bit line BL6includes a 3×3 subarray having the variable resistive elements R70, R15, R16, R24, R25, R26, R34, R35, R36, a 3×3 subarray having the variable resistive elements R44, R45, R46, R54, R55, R56, R64, R65, R66, and a 3×3 subarray having the variable resistive elements RX-24(not explicitly shown inFIG. 12), RX-25(not explicitly shown inFIG. 12), RX-26(not explicitly shown inFIG. 12), RX-11(not explicitly shown inFIG. 12), RX-15(not explicitly shown inFIG. 12), RX-16(not explicitly shown inFIG. 12), RX4, RX5, RX6. Each of combined variable conductances of the 3×3 subarrays interconnected to the bit line BL6represent a corresponding one of the matrix values in the corresponding column of the matrix D. During a D·Z operation, the column of the 3×3 subarrays interconnected to the bit line BL6is configured to generate the bit line current IR6.

The set of variable resistive units interconnected to the bit line BLY are configured to generate the correction line current IRY on the conductive line BLY. As with the embodiment shown inFIG. 1, the correction line current IRY inFIG. 12is used to correct the effects of the non-zero minimum conductance state of each of the columns of the variable resistive units not connected to the bit line BLY. For example, when the variable resistive units are 3×3 subarrays of the variable resistive elements R, the column of the 3×3 subarrays interconnected to the bit line BLY are configured to generate the correction line current IRY on the bit line BLY. Thus, when the variable resistive units are 3×3 subarrays of the variable resistive elements R, the column of the variable resistive units interconnected to the bit line BLY includes a 3×3 subarray having the variable resistive elements R1Y, R1Y-1(not explicitly shown inFIG. 12), R1Y-2(not explicitly shown inFIG. 12), R2Y, R2Y-1(not explicitly shown inFIG. 12), R2Y-2(not explicitly shown inFIG. 12), R3Y, R3Y-1(not explicitly shown inFIG. 12), R3Y-2(not explicitly shown inFIG. 12), a 3×3 subarray having the variable resistive elements R4Y, R4Y-1(not explicitly shown inFIG. 12), R4Y-2(not explicitly shown inFIG. 12), R5Y, R5Y-1(not explicitly shown inFIG. 12), R5Y-2(not explicitly shown inFIG. 12), R6Y, R6Y-1(not explicitly shown inFIG. 12), R6Y-2(not explicitly shown inFIG. 12), and a 3×3 subarray having the variable resistive elements RX-2Y (not explicitly shown inFIG. 12), RX-2Y-1(not explicitly shown inFIG. 12), RX-2Y-2(not explicitly shown inFIG. 12), RX-1Y (not explicitly shown inFIG. 12), RX-1Y-1(not explicitly shown inFIG. 12), RX-1Y-2(not explicitly shown inFIG. 12), RXY, RXY-1(not explicitly shown inFIG. 12), RXY-2(not explicitly shown inFIG. 12).

During a D·Z operation, the column of 3×3 subarrays interconnected to the bit line BLY is configured to generate the correction line current IRY. Prior to the D·Z operation, the peripheral digital computational circuitry28is configured to provide each of the combined variable conductances of the 3×3 subarrays in the minimum conductance state. The correction line current IRY is used to virtually eliminate the effect of off state conductance in the columns of the 3×3 subarrays not interconnected to the bit line BLY, such as the column of the 3×3 subarrays interconnected to the bit line BL3and the column of the 3×3 subarrays interconnected to the bit line BL6.

Thus, different combinations of the words lines WL and the bit lines BL may be opened and closed so that different sized subarrays are provided to create combined variable conductances that represent the matrix values of the matrix D when the integer number m and the integer number p are changed. However, the matrix operations are be performed where the word line output will represent vectors having a number of vector values that match the integer number p, and the bit line output will represent vectors having a number of vector values that match the integer m plus. As such, the word line output will include a proper subset of the word line voltages VW1, VW2, VW3, VW4, VW5, VW6, VWX (referred to generically as word line voltages VW), and the bit line output will include a proper subset of the bit line voltages VB1, VB2, VB3, VB4, VB5, VB6, VBY in accordance with the size of the subarrays. Furthermore, for a D·Z read operation, a proper subset of the resultant bit line currents IR1, IR2, IR3, IR4, IR5, IR6are provided to a proper subset of the bit line controllers24-1,24-2,24-3,24-4,24-5,24-6.

To do this, the resistive memory system10includes word line switches (referred to generically as word line switches SW and specifically as word line switches SW1-SWX) connected between a corresponding one of the word line controllers22and a corresponding one of the word lines WL and bit line switches (referred to generically as bit line switches BW and specifically as word line switches SB1-SBY) connected between a corresponding one of the bit line controllers24and a corresponding one of the bit lines BL. More specifically, the word line switch SW1is connected between the word line controllers22-1and the word line WL1. The word line switch SW2is connected between the word line controllers22-2and the word line WL2. The word line switch SW3is connected between the word line controllers22-3and the word line WL3. The word line switch SW4is connected between the word line controllers22-4and the word line WL4. The word line switch SW5is connected between the word line controllers22-5and the word line WL5. The word line switch SW6is connected between the word line controllers22-6and the word line WL6. The word line switch SWX is connected between the word line controllers22-X and the word line WL.

With respect to the bit line control circuitry20, the bit line switch SB1is connected between the bit line controller24-1and the bit line BL1. The bit line switch SB2is connected between the bit line controller24-2and the bit line BL2. The bit line switch SB3is connected between the bit line controller24-3and the bit line BL3. The bit line switch SB4is connected between the bit line controller24-4and the bit line BL4. The bit line switch SB5is connected between the bit line controller24-5and the bit line BL5. The bit line switch SB6is connected between the bit line controller24-6and the bit line BL6. The bit line switch SBY is connected between the bit line controller24-Y and the bit line BLY.

The switch control circuitry70shown inFIG. 3is configured to open and close each of the word line switches SW and each of the bit line switches SB is configured to be opened and closed. In this manner, the switch control circuitry70is configured to generate a switch control output72that is configured to open and close the word line switches SW and the bit line switches SB based on the size of the subarrays selected by the switch control output72. As such, the word line controllers22are interconnected by the word line switches SW to the word lines WL so that one of the word line controllers22is provided per row of subarrays while the remainder of the word line controllers22per row of subarrays are decoupled by the word line switches SW. The bit line controllers24are interconnected by the bit line switches SB to the bit lines BL so that one of the bit line controllers24is provided per column of subarrays while the remainder of the bit line controllers24per column of subarrays are decoupled by the bit line switches SB.

For instance, when 3×3 subarrays are provided by opening and closing the word line switches SW and the bit line switches SB in accordance with the pattern for every mutually exclusive set of three adjacent the word line switches WS and the bit line switches BS described above, then the word line control circuitry18provides the word line output with one of the word line voltages VW for every three interconnected word lines WL, and the bit line control circuitry20provides the bit line output with one of the bit line voltages VB for every three interconnected bit lines BL. Thus, when the variable resistive units are 3×3 subarrays of the variable resistive elements R, the switch control circuitry70may close the word line switches SW1, SW4, SWX and open the word line switches SW2, SW3, SW5, SW6. Furthermore, the switch control circuitry70may close the bit line switches SB3, SB6, SBY and open the bit line switches SB2, SB3, SB5, SB6. As such, the word line output will include the word line voltages VW3, VW6, VWX but not the word line voltages VW1, VW2, VW4, VW5. The bit line output will include the bit line voltages VB3, VB6, and VBY but not the bit line voltages VB1, VB2, VB4, VB5. Furthermore, for a D·Z read operation, the bit line currents IR3, IR6, IRY are provided to the bit line controllers24-3,24-6,24-Y but not the bit line currents IR1, IR2, IR4, IR5to the bit line controllers24-1,24-2,24-4,24-5.

By using the correction line current IRY, the resistive memory system10shown inFIG. 12is configured to reduce or even eliminate the effect of the off conductance state when the variable resistive units are provided as multiple variable resistive elements. More specifically, the peripheral digital computational circuitry28is configured to provide a set of the variable resistive units so that the combined variable conductances of each of the variable resistive units in the set are provided in the minimum conductance state. In particular, the peripheral digital computational circuitry28is configured to provide a column of the variable resistive units interconnected to the bit line BLY so that the combined variable conductances of the variable resistive units interconnected to the bit line BLY are each provided in the minimum conductance state.

Each of the matrix values of the matrix D are represented by a different corresponding one of the combined variable conductances provided by the other 3×3 subarrays that are not interconnected to the bit line BLY. For example, each of the combined variable conductances of the column of the 3×3 subarrays interconnected to the bit line BL3represent a corresponding one of the matrix values of the matrix D.

Each of the matrix values of the matrix D are represented by a different corresponding one of the combined variable conductances provided by the other 3×3 subarrays that are not interconnected to the bit line BLY. Thus, when the variable resistive units are 3×3 subarrays of the variable resistive elements R, the combined variable conductances of a column of the 3×3 subarrays interconnected to the bit line BL3represent a corresponding column of the matrix values of the matrix D. During a D·Z operation, the column of 3×3 subarrays interconnected to the bit line BL3are configured to generate the resultant bit line current IR3on the bit line BL3in response to the word line output representing Z. Additionally, the combined variable conductances of a column of the 3×3 subarrays interconnected to the bit line BL6represent another corresponding column of the matrix values of the matrix D. During the D·Z operation, the column of 3×3 subarrays interconnected to the bit line BL6are configured to generate the resultant bit line current IR6on the bit line BL6in response to the word line output representing Z.

Furthermore, during a D·Z operation, the set of variable resistive units interconnected to the bit line BLY are configured to generate the correction line current IRY on the conductive line BLY in response to the word line output representing Z. As with the embodiment shown inFIG. 1, the correction line current IRY inFIG. 12is used to correct the effects of the non-zero minimum conductance state of each of the columns of the variable resistive units not connected to the bit line BLY. For example, when the variable resistive units are 3×3 subarrays of the variable resistive elements R, the column of the 3×3 subarrays interconnected to the bit line BLY are configured to generate the correction line current IRY on the bit line BLY. The correction line current IRY is used to virtually eliminate the effect of off state conductance in the columns of the 3×3 subarrays not interconnected to the bit line BLY, such as the column of the 3×3 subarrays interconnected to the bit line BL3and the column of the 3×3 subarrays interconnected to the bit line BL6.

In accordance with the patterns of opening and closing of the switches SW, SB, WS, WB the bit line currents IR3, IR6, IRY are provided to the bit line controllers24-3,24-6,24-Y but not the bit line currents IR1, IR2, IR4, IR5to the bit line controllers24-1,24-2,24-4,24-5.

The bit line control circuitry20is coupled to receive the correction line current IRY and a proper subset of the resultant line currents IR1-IR6from the bit lines BL. In accordance with the patterns of opening and closing of the switches SW, SB, WS, WB when the variable resistive units are 3×3 subarrays, the bit line currents IR3, IR6, IRY are provided to the bit line controllers24-3,24-6,24-Y but not the bit line currents IR1, IR2, IR4, IR5to the bit line controllers24-1,24-2,24-4,24-5. The bit line controller24-3is configured to receive the resultant bit line current IR3on the bit line BL3from the column of the 3×3 subarrays coupled to the bit line BL3. The bit line controller24-3is configured to generate the digital vector value that indicates a current level of the resultant bit line current IR3. The bit line controller24-6is configured to receive the resultant bit line current IR6on the bit line BL6from the column of the 3×3 subarrays coupled to the bit line BL6. The resultant bit line controller24-6is configured to generate a digital vector value that indicates a current level of the resultant bit line current IR6. Finally, the bit line controller24-Y is configured to receive the correction bit line current IRY on the bit line BLY from the column of the 3×3 subarrays coupled to the bit line BLY. The resultant bit line controller24-Y is configured to generate a digital correction value that indicates a current level of the correction bit line current IRY. Note that the digital vector values generated as a result of the resultant bit line current IR3, IR6are off due to the off state conductance when received by the bit line controllers24-3,24-6respectively.

The subtractor26-3is configured to subtract the digital correction value from the digital vector value52-3and generate a digital vector value equal to difference between the digital vector value from the read circuit of the bit line controller24-3and the digital correction value. The subtractor26-6is configured to subtract the digital correction value from the digital vector value52-6and generate a digital vector value equal to difference between the digital vector value from the read circuit of the bit line controller24-6and the digital correction value. The resultant digital vector values from the bit line controllers24are combined so that the bit line control circuitry20generates the resultant digital vector output32. In this case, the resultant digital vector output32only includes the resultant digital vector values from the subtractors26-3,26-6. The resultant digital vector output32is received by the peripheral digital computational circuitry28to continue implementing the learning algorithm.

It should be noted that the pulse schemes for a D update operation described above with respect toFIGS. 8A-10Bare implemented by the resistive memory system10shown inFIG. 12in the same manner described above except that the pulses are applied to a variable resistive unit having multiple variable resistive elements in order to adjust the combined variable conductance from a current conductance state to a target conductance state. For example, in accordance with the patterns of opening and closing of the switches SW, SB, WS, WB which provide the variable resistive units as 3×3 subarrays, the pulse schemes can be applied to each of the 3×3 subarrays in the columns of 3×3 subarrays interconnected to the bit lines BL3and BL6. Finally, it should also be noted that while not specifically shown, alternative embodiments of the resistive memory system10can be provided where the variable resistive units are subarrays of multiple variable resistive elements R that are fixed instead of reconfigurable. Still other alternative embodiments may have some of the variable resistive units as fixed subarrays while other variable resistive units are reconfigurable.