Class AB output stage

The present disclosure relates to a class AB amplifier output stage.

BACKGROUND

Several different amplifier circuit arrangements may be utilized to provide output signals. In one example, a class A amplifier circuit arrangement reproduces an entire input signal because an active element of the class A amplifier circuit arrangement, such as a transistor, is constantly in the active mode. However, class A amplifiers typically have a high power consumption because the active element does not stop conducting current.

In another example, a class B amplifier circuit arrangement reproduces half of the input signal since an active element of a class B amplifier circuit arrangement spends half of the time in active mode and the other half in cutoff. Class B amplifier circuit arrangements may include a push-pull configuration that has two active elements with one active element in active mode for half of an input waveform and the other active element in active mode for the other half of the input waveform. The properties of class B amplifier circuit arrangements may vary with load conditions and may suffer from harmonic distortion when the handoff from one element to another does not occur properly.

Class AB amplifier circuit arrangements are a mixture between class A amplifier circuit arrangements and class B amplifier circuit arrangements. Class AB amplifier circuit arrangements include two active elements that are in the active mode more than 50% of the time to decrease the amount of harmonic distortion that occurs during the handoff from one active element to another. Adjustment of output quiescent current in Class AB amplifier circuit arrangements may be problematic.

Some class AB amplifier circuit arrangements may utilize a stack of two diodes to adjust quiescent current. However, such arrangements do not typically operate well at low supply voltages because the stack of two diodes requires a relatively high supply voltage. Other class AB amplifier circuit arrangements may operate at low supply voltages, but may have increased current consumption. For example, class AB amplifier circuit arrangements may include current mirrors that generate a current internally and mirror the current to the output of the circuit arrangement. However, the current consumption of such class AB amplifier circuit arrangements is doubled. Still other class AB amplifier circuit arrangements may operate at low supply voltages and have low current consumption, but suffer from a poor power supply rejection ratio.

DETAILED DESCRIPTION

This disclosure describes at least one class AB amplifier output stage circuit arrangement that can operate at low supply voltages, with minimum current generated. Furthermore, at least one class AB amplifier stage circuit arrangement described herein reacts favorably to a supply voltage, that is, exhibits a good power supply rejection ratio. Moreover, this disclosure describes class AB amplifier output stage circuit arrangements that include a negative channel metal oxide semiconductor (NMOS) transistor current mirror arrangement and a positive channel metal oxide semiconductor (PMOS) transistor current mirror arrangement. In some implementations, a monitoring circuit may be coupled to a class AB amplifier output stage circuit arrangement to offset mismatch that may occur in the class AB amplifier output stage.

According to one exemplary implementation, an apparatus includes a first current mirror arrangement coupled to a first input signal arrangement. The first input signal arrangement includes a first input current source and a first impedance. The apparatus also includes a second current mirror arrangement coupled to a second input signal arrangement. The second input signal arrangement includes a second input current source and a second impedance. The first current mirror arrangement is coupled to the second current mirror arrangement.

According to another implementation, an apparatus includes a first operational transconductance amplifier including an output node coupled to a first variable current source. The first operational transconductance amplifier determines a voltage drop of a first impedance. The apparatus also includes a second operational transconductance amplifier including an output node coupled to a second variable current source. The second operational transconductance amplifier determines a voltage drop of a second impedance. The output node of the second operational transconductance amplifier is coupled to the output node of the first operational transconductance amplifier.

According to another implementation, an apparatus includes a differential amplifier arrangement coupled to a first impedance of a class AB amplifier output stage and coupled to a second impedance of the class AB amplifier output stage. An output node of the differential amplifier arrangement is coupled to a variable current source arrangement and one or more input nodes of the differential amplifier arrangement are coupled to the first impedance and the second impedance.

According to another implementation, a method includes generating an output signal of a first amplifier circuit based on a voltage drop of a first impedance of a class AB amplifier output stage. The method also includes generating an output signal of a second amplifier circuit based on a voltage drop of a second impedance of a class AB amplifier output stage. The method further includes generating a compensating current when the voltage drop of the first impedance is different from the voltage drop of the second impedance. The compensating current adjusts the voltage drop of the first impedance, the voltage drop of the second impedance, or a combination thereof, such that the voltage drop of the first impedance and the voltage drop of the second impedance are adjusted to be approximately equal.

FIG. 1is a schematic diagram of an apparatus100utilized to provide an amplified input signal from a source102to a load106via an amplifier device104. In particular implementations, the source102may include one or more circuit arrangements that provide one or more input signals to the amplifier device104. The input signals may include radio frequency signals, audio signals, digital signals, or other signals carrying data. The load106may include an additional device that receives the output of the amplifier device104as an input signal. For example, the load106may include an output device, such as an audio speaker, an analog to digital conversion circuit, a mixer, or a combination thereof. In some implementations, the circuit100may be included in a high speed amplifier.

The amplifier device104includes an input stage108and a class AB amplifier output stage110. In an illustrative implementation, the input stage108may include one or more devices, such as operational amplifiers, to modify signals from the source102and provide the modified signals to the class AB amplifier output stage110. In turn, the class AB amplifier output stage110may further modify the signals from the source102and provide these signals to the load106. In a particular implementation, the class AB amplifier output stage110may include a positive channel metal oxide semiconductor (PMOS) transistor current mirror arrangement and a negative channel metal oxide semiconductor (NMOS) transistor current mirror arrangement. An impedance, such as a resistor or an arrangement of transistors, may be coupled between the transistors of the PMOS current mirror arrangement. An additional impedance may be coupled between the transistors of the NMOS current mirror arrangement. The circuit arrangement of the class AB amplifier output stage110is configured to provide good regulation of output quiescent current, while operating at low supply voltages or high supply voltages, with a good power supply rejection ratio, and minimum current consumption.

In some implementations, a monitoring circuit112may be utilized in the amplifier device104to reduce mismatch in the class AB amplifier output stage110. In an illustrative implementation, the monitoring circuit112may include a first operational transconductance amplifier (OTA) to generate an output current based on a voltage drop of a first impedance coupled between transistors of a PMOS current mirror arrangement of the class AB amplifier output stage110. The monitoring circuit112may also include a second OTA to generate an output current based on a voltage drop of a second impedance coupled between transistors of an NMOS current mirror arrangement of the class AB amplifier output stage110. The output currents of the first OTA and the second OTA of the monitoring circuit112may be utilized to produce a compensating current to regulate the voltage drops of the impedances of the current mirror arrangements of the class AB amplifier output stage110, such that the voltage drops are approximately equal, in order to provide good control of output quiescent current of the class AB amplifier output stage110.

In some instances, the impedance values of the first impedance and the second impedance are approximately equal and the voltage drop of the first impedance and the voltage drop of the second impedance may be approximately equal when the first impedance and the second impedance receive approximately the same current. In other instances, the impedance values of the first impedance and the second impedance may be different and the current provided to the first impedance and the second impedance may correspond to the difference between the impedance values, such that the voltage drop of the first impedance and the voltage drop of the second impedance are approximately equal. For example, when the impedance value of the first impedance is larger than that of the second impedance, the current provided to the first impedance would be less than the current provided to the second impedance.

In another illustrative implementation, the monitoring circuit112may include a differential amplifier arrangement to offset mismatch in the class AB amplifier output stage110. For example, the monitoring circuit112may include a first differential amplifier to determine a voltage drop of a first impedance coupled between transistors of a PMOS current mirror arrangement of the class AB amplifier output stage110. The monitoring circuit112may also include a second differential amplifier to determine a voltage drop of a second impedance coupled between transistors of an NMOS current mirror arrangement of the class AB amplifier output stage110. The first differential amplifier and the second differential amplifier may be coupled to a third differential amplifier that drives one or more auxiliary variable current sources to produce a compensating current when there is a difference between the voltage drop of the first impedance and the voltage drop of the second impedance. In an alternative implementation, the differential amplifier arrangement may include a differential difference amplifier that produces an output that drives the one or more auxiliary variable current sources to produce a compensating current when there is a difference between the voltage drop of the first impedance and the voltage drop of the second impedance.

FIG. 2is a schematic diagram of a class AB amplifier output stage circuit arrangement200including a PMOS transistor current mirror arrangement and an NMOS transistor current mirror arrangement. The PMOS transistor current mirror arrangement includes a first positive channel metal oxide semiconductor (PMOS) transistor202and a second PMOS transistor204. The PMOS transistor current mirror arrangement is coupled to a first input signal arrangement206. The first input signal arrangement206includes a first impedance208and a first input current source210. A gate of the first PMOS transistor202is coupled to the first impedance208and a drain of the first PMOS transistor202is coupled to a reference current source212. A source of the first PMOS transistor202is coupled to a supply voltage, VDD. A gate of the second PMOS transistor204is coupled to the first impedance208and to the first input current source210and a drain of the second PMOS transistor204is coupled to an output terminal214. Additionally, a source of the second PMOS transistor204is coupled to the supply voltage VDD.

The NMOS transistor current mirror arrangement includes a first negative channel metal oxide semiconductor (NMOS) transistor216and a second NMOS transistor218. The NMOS transistor current mirror arrangement is coupled to a second input signal arrangement220. The second input signal arrangement220includes a second impedance222and a second input current source224. A gate of the first NMOS transistor216is coupled to the second impedance222and a drain of the first NMOS transistor216is coupled to the reference current source212. A source of the first NMOS transistor216is coupled to a ground226. A gate of the second NMOS transistor218is coupled to the second impedance222and to the second input current source224. A drain of the second NMOS transistor218is coupled to the output terminal214and a source of the second NMOS transistor218is coupled to the ground226.

In some implementations, the reference current source212may be replaced by two separate matched current sources to provide appropriate bias currents to the PMOS transistor current mirror arrangement and the NMOS transistor current mirror arrangement. For example, one of the matched current sources may drive the first PMOS transistor202and the other matched current source may drive the first NMOS transistor216.

In an illustrative implementation, the first input current source210, the second input current source224, or a combination thereof, may produce a negative input current decreasing the voltage at the gate of the second PMOS transistor204and decreasing the voltage at the gate of the second NMOS transistor218. In response to a negative input current, the second PMOS transistor204may deliver an increased output current by producing an increased source to drain current that provides a current path between the supply voltage VDDand the output terminal214. The output current of the second NMOS transistor218decreases in response to a negative input current. In some instances, such as with a large input current, the output current of the second NMOS transistor218is shut off and the second NMOS transistor218does not conduct any current. In this way, the output transistors204and218exhibit the desired push-pull behavior based on a negative input current.

In another illustrative implementation, the first input current source210, the second input current source224, or a combination thereof, may produce a positive input current increasing the voltage of the gate of the second PMOS transistor204and increasing the voltage of the gate of the second NMOS transistor218. In response to a positive input current, the second NMOS transistor218delivers an increased output current, while the output current of the second PMOS transistor204decreases. In some instances, such as with a large input current, the output current of the second PMOS transistor204is shut off and does not conduct current from the supply voltage VDDto the output terminal214. In this way, the output transistors204and218exhibit the desired push-pull behavior based on a positive input current.

In a further illustrative implementation, a quiescent condition of the AB amplifier output stage circuit arrangement200occurs when no current is provided by the first input current source210or the second input current source224. In the quiescent condition, the current provided by the reference current source212is mirrored by the second PMOS transistor204and the second NMOS transistor218. Under some circumstances, the first input current source210, the second input current source224, or a combination thereof, may produce some current during the quiescent condition, which may cause a mismatch condition.

FIG. 3is a schematic diagram of a monitoring circuit300of a class AB amplifier output stage circuit arrangement, such as the class AB amplifier output stage circuit arrangement200ofFIG. 2. The monitoring circuit300may be configured to offset mismatch that occurs in the class AB amplifier output stage circuit arrangement. A class AB amplifier output stage circuit arrangement including larger transistors and receiving an accurate steering current may have minimal mismatch; however, when transistors of a class AB amplifier output stage circuit arrangement are smaller in size, such as transistors of a high-speed amplifier, mismatch may have a detrimental effect on control of the quiescent current.

The monitoring circuit300includes a first impedance302of a class AB amplifier output stage. In some implementations, the first impedance302may correspond to the impedance208ofFIG. 2. A first node of the first impedance302may be coupled to a low-pass filter304and a second node of the first impedance302may be coupled to a low-pass filter306. In addition, the first node and the second node of the first impedance302are coupled to a first auxiliary variable current source308. In some implementations, the first auxiliary variable current source308may be connected in parallel with the first current source210ofFIG. 2. In other implementations, the first auxiliary variable current source308and the first current source210ofFIG. 2may represent the same current source. For example, an output current of the monitoring circuit300and an input current to the class AB amplifier output stage200may be combined by a summer circuit (not shown), such as an op-amp, and fed into a single current source308/210that provides current across the first impedance302/208.

The monitoring circuit300also includes a second impedance310of a class AB amplifier output stage. In some implementations, the second impedance310may correspond to the impedance222ofFIG. 2. A first node of the second impedance310may be coupled to a low-pass filter312and a second node of the second impedance310may be coupled to a low-pass filter314. The first node and the second node of the second impedance310are also coupled to a second auxiliary variable current source316. In some implementations, the second auxiliary variable current source316may be connected in parallel with the second current source224ofFIG. 2. In other implementations, the second auxiliary variable current source316and the second current source224ofFIG. 2may represent the same current source. For example, an output current of the monitoring circuit300and an input current to the class AB amplifier output stage200may be combined in a summer circuit (not shown), such as an op-amp, and fed into a single current source316/224that provides current across the second impedance310/222. Further, in particular implementations, such as with linear circuits and small input signals, the low-pass filters304,306,312,314may not be necessary.

Additionally, the monitoring circuit300includes a first operational transconductance amplifier (OTA)318. A non-inverting node of the first OTA318is coupled to the low-pass filter306and an inverting node of the first OTA318is coupled to the low-pass filter304. An output node of the first OTA318is coupled to the first auxiliary variable current source308.

Further, the monitoring circuit300includes a second operational transconductance amplifier (OTA)320. A non-inverting node of the second OTA320is coupled to the low-pass filter312and an inverting node of the second OTA320is coupled to the low-pass filter314. An output node of the second OTA320is coupled to the second auxiliary variable current source316. In addition, the output node of the second OTA320is coupled to the output node of the first OTA318.

In an illustrative implementation, the first OTA318may determine a voltage drop of the first impedance302and the second OTA320may determine a voltage drop of the second impedance310. The output current of the first OTA318is related to the voltage drop of the first impedance302and the output current of the second OTA320is related to the voltage drop of the second impedance310. In some implementations, the voltage drop of the first impedance302and the voltage drop of the second impedance310are approximately equal. When the voltage drop of the first impedance302and the voltage drop of the second impedance310are approximately equal, the respective output currents of the first OTA318and the second OTA320cancel each other and have a sum of zero or approximately zero.

In other implementations, the voltage drop of the first impedance302may be different from the voltage drop of the second impedance310. For example, the voltage drop of the first impedance302and the voltage drop of the second impedance310may be different due to differing currents across the first impedance302and the second impedance310of the class AB amplifier output stage. To illustrate, during a quiescent condition of the class AB amplifier output stage, a first current source of the class AB amplifier output stage may produce a slightly positive current and/or a second current source of the class AB amplifier output stage may produce a slightly negative current. Consequently, an impedance coupled to the first current source would have a different voltage drop than an impedance coupled to the second current source resulting in mismatch of the class AB amplifier output stage.

When the voltage drop of the first impedance302and the voltage drop of the second impedance310are different, the output current of the first OTA318and the output current of the second OTA320drive the first auxiliary variable current source308, the second auxiliary variable current source316, or a combination thereof, to generate a compensating current, such that the voltage drop of the first impedance302and the voltage drop of the second impedance310are adjusted to be approximately equal. Thus, the monitoring circuit300relies on a closed regulation loop to equalize the voltage drop of the first impedance302and the voltage drop of the second impedance310, so that the class AB amplifier output stage will avoid the effect of mismatch and subsequently produce a correct output current as designed.

In some implementations when the voltage drop of the first impedance302and the voltage drop of the second impedance310are different, the first auxiliary variable current source308and the second auxiliary variable current source316may receive the combined output currents of the first OTA318and the second OTA320and produce respective compensating currents such that the voltage drop of the first impedance302and the voltage drop of the second impedance310are adjusted to be approximately equal. For example, when a slightly negative current is provided to the first impedance302during the quiescent condition, the first auxiliary variable current source308may provide a slightly positive compensating current. Moreover, when a slightly positive current is provided to the first impedance302during the quiescent condition, the first auxiliary variable current source308may provide a slightly negative compensating current. In another example, when a slightly positive current is provided to the second impedance310during the quiescent condition, the second auxiliary variable current source316may provide a slightly negative compensating current. Furthermore, when a slightly negative current is provided to the second impedance310during the quiescent condition, the second auxiliary variable current source316may provide a slightly positive compensating current.

In other implementations, the monitoring circuit300may include one auxiliary variable current source rather than the first auxiliary variable current source308and the second auxiliary variable current source316as shown inFIG. 3. For example, the monitoring circuit300may include an auxiliary variable current source to provide compensating current to the first impedance302. In this example, when the voltage drop of the first impedance302and the voltage drop of the second impedance310are different, the auxiliary variable current source provides a compensating current to the first impedance302based on the output signals of the first OTA318and the second OTA320, such that the voltage drop of the first impedance302and the voltage drop of the second impedance310are adjusted to be approximately equal. In another example, the monitoring circuit300may include an auxiliary variable current source to provide compensating current to the second impedance310. In this example, when the voltage drop of the first impedance302and the voltage drop of the second impedance310are different, the auxiliary variable current source provides a compensating current to the second impedance310based on the output signals of the first OTA318and the second OTA320, such that the voltage drop of the first impedance302and the voltage drop of the second impedance310are adjusted to be approximately equal.

FIG. 4is a schematic diagram of a monitoring circuit400of a class AB amplifier output stage circuit arrangement, such as the class AB amplifier output stage circuit arrangement200ofFIG. 2. The monitoring circuit400may be configured to offset mismatch that occurs in the class AB amplifier output stage circuit arrangement.

The monitoring circuit400includes a first impedance402of a class AB amplifier output stage. In some implementations, the first impedance402may correspond to the first impedance208ofFIG. 2. A first node of the first impedance402may be coupled to a low-pass filter404and a second node of the first impedance402may be coupled to a low-pass filter406. In addition, the first node and the second node of the first impedance402are coupled to a first auxiliary variable current source408. In some implementations, the first auxiliary variable current source408may be connected in parallel with the first current source210ofFIG. 2, while in other implementations the first auxiliary variable current source408and the first current source210ofFIG. 2may represent the same current source.

The monitoring circuit400also includes a second impedance410of a class AB amplifier output stage. In some implementations, the second impedance410may correspond to the second impedance222ofFIG. 2. A first node of the second impedance410may be coupled to a low-pass filter412and a second node of the second impedance410may be coupled to a low-pass filter414. The first node and the second node of the second impedance410are also coupled to a second auxiliary variable current source416. In some implementations, the second auxiliary variable current source416may be connected in parallel with the second current source224ofFIG. 2, while in other implementations the second auxiliary variable current source416and the second current source224ofFIG. 2may represent the same current source. Further, in particular implementations, the low-pass filters404,406,412,414may not be necessary.

Additionally, the monitoring circuit400includes a first differential amplifier418. A non-inverting node of the first differential amplifier418is coupled to the low-pass filter406and an inverting node of the first differential amplifier418is coupled to the low-pass filter404. Further, the monitoring circuit400includes a second differential amplifier420. An inverting node of the second differential amplifier420is coupled to the low-pass filter412and a non-inverting node of the second differential amplifier420is coupled to the low-pass filter414. An output node of the first differential amplifier418is coupled to a non-inverting node of a third differential amplifier422and an output node of the second differential amplifier420is coupled to an inverting node of the third differential amplifier422. The output node of the third differential amplifier422is coupled in a negative feedback loop to the first auxiliary variable current source408and to the second auxiliary variable current source416.

In an illustrative implementation, the first differential amplifier418may determine a voltage drop of the first impedance402and provide a corresponding output signal to the third differential amplifier422. The second differential amplifier420may determine a voltage drop of the second impedance410and provide a corresponding output signal to the third differential amplifier422. The third differential amplifier422may determine whether or not there is a difference between the voltage drop of the first impedance402and the voltage drop of the second impedance410. The output signal of the third differential amplifier422may drive the first auxiliary variable current source408and the second auxiliary current source416. For example, when there is a difference between the voltage drop of the first impedance402and the voltage drop of the second impedance410, the third differential amplifier422may drive the first auxiliary variable current source408, the second auxiliary variable current source416, or a combination thereof, to produce a compensating current such that the voltage drop of the first impedance402and the voltage drop of the second impedance410are adjusted to be approximately equal.

Further, the monitoring circuit400may be implemented with one auxiliary variable current source, rather than the first auxiliary variable current source408and the second auxiliary variable current source416shown inFIG. 4. The single auxiliary variable current source may be coupled to the first impedance402or the second impedance410. The single auxiliary variable current source may provide a compensating current to the first impedance402or the second impedance410based on the output signal of the third differential amplifier422when the voltage drop of the first impedance402and the voltage drop of the second impedance410are different, such that the voltage drop of the first impedance402and the voltage drop of the second impedance410are adjusted to be approximately equal.

FIG. 5is a schematic diagram of a monitoring circuit500of a class AB amplifier output stage circuit arrangement, such as the class AB amplifier output stage circuit arrangement200ofFIG. 2. The monitoring circuit500may be configured to offset mismatch that occurs in the class AB amplifier output stage circuit arrangement.

The monitoring circuit500includes a first impedance502of a class AB amplifier output stage. In some implementations, the first impedance502may correspond to the first impedance208ofFIG. 2. A first node of the first impedance502may be coupled to a low-pass filter504and a second node of the first impedance502may be coupled to a low-pass filter506. In addition, the first node and the second node of the first impedance502are coupled to a first auxiliary variable current source508. In some implementations, the first auxiliary variable current source508may be connected in parallel with the first current source210ofFIG. 2, while in other implementations the first auxiliary variable current source508and the first current source210ofFIG. 2may represent the same current source.

The monitoring circuit500also includes a second impedance510of a class AB amplifier output stage. In some implementations, the second impedance510may correspond to the second impedance222ofFIG. 2. A first node of the second impedance510may be coupled to a low-pass filter512and a second node of the second impedance510may be coupled to a low-pass filter514. The first node and the second node of the second impedance510are also coupled to a second auxiliary variable current source516. In some implementations, the second auxiliary variable current source516may be connected in parallel with the second current source224ofFIG. 2, while in other implementations the second auxiliary variable current source516and the second current source224ofFIG. 2may represent the same current source. Further, in particular implementations, the low-pass filters504,506,512,514may not be necessary.

Additionally, the monitoring circuit500includes a differential difference amplifier518. A first non-inverting node of the differential difference amplifier518is coupled to the low-pass filter506and a first inverting node of the differential difference amplifier518is coupled to the low-pass filter504. Further, a second inverting node of the differential difference amplifier518is coupled to the low-pass filter512and a second non-inverting node of the differential difference amplifier518is coupled to the low-pass filter514. An output node of the differential difference amplifier518is coupled in a negative feedback loop to the first auxiliary variable current source508and to the second auxiliary variable current source516.

In an illustrative implementation, the differential difference amplifier518may determine a voltage drop of the first impedance502and a voltage drop of the second impedance510. The differential difference amplifier518may also determine whether or not there is a difference between the voltage drop of the first impedance502and the voltage drop of the second impedance510. The output signal of the differential difference amplifier518may drive the first auxiliary variable current source508and the second auxiliary current source516. For example, when there is a difference between the voltage drop of the first impedance502and the voltage drop of the second impedance510, the differential difference amplifier518may drive the first auxiliary variable current source508, the second auxiliary variable current source516, or a combination thereof, to produce a compensating current such that the voltage drop of the first impedance502and the voltage drop of the second impedance510are adjusted to be approximately equal.

FIG. 6is a flow diagram of a method600of correcting mismatch in a class AB amplifier output stage. The method600may utilize a monitoring circuit to correct mismatch in the class AB amplifier output stage. The class AB amplifier output stage may be the class AB amplifier output stage200illustrated inFIG. 2and the monitoring circuit may be the monitoring circuit300shown inFIG. 3, the monitoring circuit400ofFIG. 4, or the monitoring circuit500ofFIG. 5. The class AB amplifier output stage and the monitoring circuit may be included in a high-speed amplifier.

Specifics of exemplary methods are described below. However, it should be understood that certain acts need not be performed in the order described, and may be modified, and/or may be omitted entirely, depending on the circumstances. Moreover, the acts described may be implemented by a computer, processor or other computing device based on instructions stored on one or more computer-readable media. The computer-readable media can be any available media that can be accessed by a computing device to implement the instructions stored thereon.

At602, the method600includes generating an output signal of a first amplifier circuit, such as an operational transconductance amplifier (OTA) or a differential amplifier, based on a voltage drop of a first impedance of a class AB amplifier output stage. The first impedance may be the impedance208ofFIG. 2and/or the impedance302ofFIG. 3, or the impedance402ofFIG. 4. In addition, the first amplifier circuit may be the first OTA318ofFIG. 3or the first differential amplifier418ofFIG. 4. At604, a second amplifier circuit, such as an OTA or a differential amplifier, generates an output signal based on a voltage drop of a second impedance of a class AB amplifier output stage. The second impedance may be the impedance222ofFIG. 2and/or the impedance310ofFIG. 3, or the impedance410ofFIG. 4. The second amplifier circuit may be the second OTA320ofFIG. 3or the second differential amplifier420ofFIG. 4. In some implementations, the first amplifier circuit and the second amplifier circuit may represent the functionality of the differential difference amplifier518ofFIG. 5and the impedance502ofFIG. 5may represent the first impedance and the impedance510ofFIG. 5may represent the second impedance.

At decision606, the method600includes determining whether the voltage drop of the first impedance and the voltage drop of the second impedance are different. When there is not a difference between the voltage drop of the first impedance and the voltage drop of the second impedance, the method returns to602. When there is a difference between the voltage drop of the first impedance and a voltage drop of the second impedance, the method advances to608. At608, a compensating current is generated such that the voltage drop of the first impedance and the voltage drop of the second impedance are adjusted to be approximately equal. The compensating current may be generated by one or more current sources of the monitoring circuit. In implementations where the first amplifier circuit and the second amplifier circuit are OTAs, the one or more current sources may be driven by the output currents of the OTAs. Further, in implementations where the first amplifier circuit and the second amplifier circuit are differential amplifiers, the output signals of the differential amplifiers may be fed into an additional differential amplifier that produces an output signal to drive the one or more current sources.

CONCLUSION

For the purposes of this disclosure and the claims that follow, the terms “coupled” and “connected” have been used to describe how various elements interface. Such described interfacing of various elements may be either direct or indirect. Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as preferred forms of implementing the claims. The specific features and acts described in this disclosure and variations of these specific features and acts may be implemented separately or may be combined.