Dynamic power reduction in a wireless receiver

Various techniques for dynamically reducing power usage in a wireless receiver are disclosed. A receiver unit receives a wireless signal over a channel and processes the wireless signal, including dynamically changing one or more of the settings of the receiver unit to control its power usage. These setting are changed in response to one or more power setting values that are generated based on a first set of information that includes state information for the channel. The receiver unit may dynamically change a first setting that causes the bias current applied to an analog-to-digital converter to be changed. The channel state information may include information indicative of a received signal strength indication (RSSI), information indicative of a packet error rate (PER) for packets encoded on the wireless signal, and header error check (HEC) and/or cyclical redundancy check (CRC) errors for data packets encoded on the wireless signal.

BACKGROUND OF THE INVENTION

1. Technical Field

This disclosure relates generally to wireless communications, and more specifically, to dynamically reducing power consumption in wireless receivers.

2. Description of the Related Art

Wireless communication involves a transmitting device that modulates a carrier wave to transmit information on the modulated signal over a wireless network. On the receiving end, a receiving device demodulates the carrier wave to decode the transmitted information. Various modulation schemes and transmission protocols are possible.

The Bluetooth standard established by the Bluetooth Special Interest Group is one example of a protocol designed for use in short-range wireless communications over a personal area network (PAN) or piconet. The Bluetooth protocol provides a low-power communication standard that operates in the 2.4 GHz band on devices with an effective communication range of up to 100 meters. The Bluetooth 2.0 and 2.1 standards support a variety of modulations schemes at multiple transmission speeds. The Bluetooth specification also establishes several requirements for transmitting and receiving devices.

SUMMARY

Various techniques for dynamically reducing power usage in a wireless receiver are disclosed.

In one embodiment, a method for controlling power usage of a wireless receiver includes a receiver unit receiving a wireless signal over a channel and processing the wireless signal, where the processing includes the receiver unit dynamically changing one or more of its settings to control its power usage. These setting are changed in response to one or more power setting values that are generated based on a first set of information that includes state information for the channel. In certain embodiments, the receiver unit performs analog-to-digital conversion of the wireless signal using a sigma-delta analog-to-digital converter (ADC), and dynamically changes a first setting of the receiver unit that causes the bias current applied to the ADC to be changed. In some embodiments, the receiver unit detects symbols from a digitized version of the wireless signal using a currently selected one of a plurality of symbol detectors, and dynamically changes a setting that causes the currently active symbol detector to change. In other embodiments, the received wireless signal includes I and Q quadrature components, and the receiver unit dynamically changes a setting that causes the receiver unit to discard one of the quadrature components. In various embodiments, the state information for the channel on which the power setting values are generated may include information indicative of a received signal strength indication (RSSI), information indicative of a packet error rate (PER) for packets encoded on the wireless signal, and information indicative of header error check (HEC) and/or cyclical redundancy check (CRC) errors for data packets encoded on the wireless signal.

In another embodiment, an apparatus including a receiver unit is disclosed. The receiver unit may be a Bluetooth receiver in one embodiment. In one embodiment, the receiver unit may include a power control unit that is configured to generate the one or more power setting values. In certain embodiments, the power control unit includes a processor and memory, and generates the power setting values by the processor executing program instructions stored in the memory. The processor and the receiver unit may be located on a common die. In various embodiments, the receiver unit may include an amplifier unit, a sigma-delta analog-to-digital converter, a signal processing unit, and a plurality of symbol detectors.

In another embodiment, a method is disclosed in which, during a communication session over a wireless channel that includes reception of a wireless signal by a receiver unit, one or more power settings values are dynamically generated responsive to a first set of information that provides partial state information for the wireless channel. The one or more power setting values are conveyed to the receiver unit, where the one or more power setting values cause the receiver unit to change one or more settings that control its analog or digital power usage.

DETAILED DESCRIPTION

This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The power reduction techniques described below may be performed on any suitable type of wireless communication device.FIGS. 1A and 1Bare block diagrams illustrating two embodiments of communication devices that may be used to implement the techniques described below. InFIG. 1A, a communication device100A includes a housing104that contains a receiver unit120coupled to a processor unit130A and to an antenna110. Antenna110may be external (as depicted) or internal to housing104. In other embodiments, receiver unit120may include antenna110. In one embodiment, receiver unit120and processor unit130A may be separate components (e.g., chips), while in another embodiment, receiver unit120and processor unit130A may be located on the same die. For example,FIG. 1Billustrates an embodiment in which a communication device100B contains a processor unit130B including receiver unit120.

Communication devices100A and100B (collectively referred to as communication device100) may be or be included in any of various types of devices, including but not limited to: a mobile phone, wireless headset, pager, global positioning system (GPS) unit, video game console, digital camera, printer, desktop computer, laptop, or personal digital assistant (PDA). Communication device100may be any type of networked peripheral device such as storage devices, switches, modems, routers, etc. In various embodiments, commutation device100may implement any of a variety of communication protocols, including but not limited to: Bluetooth, WiFi, or WiMax.

Processor units130A and130B (collectively referred to as processor unit130) may each contain one or more processors. In various embodiments, processor unit130may include general-purpose processors used to perform multiple various functions, or may include processors designed to perform specialized operations. In various embodiments, processor unit130may include a memory134(as inFIGS. 1A and 1B) or may be externally coupled to a memory134that is external to processor unit130. In various embodiments, memory134may include magnetic storage media or volatile and/or non-volatile semiconductor memory such as flash memory, random access memory (RAM-SRAM, EDO RAM, SDRAM, DDR SDRAM, Rambus® RAM, etc.), and/or read only memory (PROM, EEPROM, etc.). Processor unit130may include various other components (not illustrated) such as a cache, superscalar pipeline, I/O interface, etc. Examples of I/O devices that may be coupled to the I/O interface include storage devices (hard drive, optical drive, removable flash drive, storage array, SAN, or their associated controller), network interface devices (e.g., to a local or wide-area network), or other devices (e.g., graphics, user interface devices, etc.).

Receiver unit120is configured to receive a wireless signal (e.g., from antenna110or circuitry coupled thereto) and process it. Although the term “wireless signal” is used herein for convenience, it is noted that a wireless signal may be regarded as a composite of multiple component signals. The received wireless signal may include digital information signals that have been modulated with a carrier signal and transmitted over a wireless communication channel. Once a transmitted wireless signal is received, the original information signals may be obtained by demodulating the wireless signal. In one embodiment, a wireless signal may be modulated using quadrature modulation where the I and Q quadrature components correspond to respective digital information signals. For example, the quadrature components may be modulated using carrier signals that are 90 degree out-of-phase (e.g., the I quadrature component is modulated using a sine wave while the Q quadrature component is modulated using a cosine wave). In an alternative embodiment, a wireless signal may be modulated using polar modulation where r (amplitude) and Θ (phase) components correspond to respective digital information signals.

In various embodiments, receiver unit120may be configured to implement a Bluetooth protocol, e.g., where receiver unit120receives a 2.4 GHz wireless signal with a signal strength of −90 dBm to 0 dBm. Certain Bluetooth protocols allow a receiver to communicate using a variety of options. Accordingly, receiver unit120may, in one embodiment, be configured to negotiate various appropriate transmission parameters (e.g., modulation schemes, transmission speeds, use of encryption, etc.). In such an embodiment, receiver unit120may perform different operations depending on the negotiated parameters. For example, in various embodiments, receiver unit120may receive wireless signals that are transmitted at 1 Mbps (e.g., using GFSK modulation), 2 Mbps, and 3 Mbps (e.g., using pi/4-DQPSK and 8-DPSK modulation). Thus, for example, when receiver unit120uses a GFSK modulation scheme or a 1 Mbps transmission rate, it may use different methods and/or components than when using, e.g., a pi/4-DQPSK modulation scheme and a 2 Mbps transmission rate.

As will be described in greater detail below, receiver unit120may process a wireless signal using a variety of techniques of varying complexity. Each of these techniques may consume different amounts of power while providing different levels of performance. The power usage of various techniques is often affected by the complexity of circuitry or software that implements the technique. For example, a complex filtering technique, implemented using analog circuitry, may have a higher analog power usage than a less complex filtering technique because the complex filter may consume greater amounts (e.g., watts) of power. In general, when receiver unit120requires better dynamic range, better-performing processing techniques are selected, which typically consume more power. Depending on the selection, the power usage of receiver unit120may be dynamically or automatically controlled or regulated. As used herein, the terms “dynamically” and “automatically” in the context of power usage, refer to controlling or regulating characteristics of a device without explicit operator intervention at that time (e.g., an explicit user command to change a power characteristic). In various embodiments, receiver unit120may be designed to use the most efficient processing techniques to provide sufficient accuracy for the particular wireless communication session. This goal may be achieved, for example, by monitoring channel state information. Such an architecture may permit a communication device100to perform differently under different channel conditions and different interference conditions.

As illustrated inFIGS. 1A and 1B, receiver unit120may be internal or external to processor unit130. As such, various processing components of receiver unit120(described in greater detail below) may be implemented within receiver unit120or processing unit130. In various embodiments, these components may be implemented as hardware or software. For example, if processor unit130contains receiver unit120, processor unit130may implement certain receiver components using analog and digital circuitry, or in software (e.g., program instructions stored in memory134that are executed by one or more processors within processor unit130).

Various embodiments of receiver unit120are described further in U.S. patent application Ser. No. 12/016,955, entitled “Hybrid Zero-IF Receiver” and filed on Jan. 18, 2008, and U.S. application Ser. No. 12/122,013, entitled “Timing Tracker for DPSK Receiver” and filed on May 16, 2008. Both of these applications are incorporated by reference herein in their entireties.

FIGS. 2A-Dare block diagrams illustrating various embodiments of receiver unit120. InFIG. 2A, receiver unit120includes an amplifier unit210, an analog-to-digital converter (ADC) unit220, a signal processing unit230, and a symbol detector240that are coupled together. As shown, a power control unit250may be coupled to amplifier unit210, ADC unit220, signal processing unit230, symbol detector unit240, and processor unit130. In this embodiment, receiver unit120receives wireless signals from antenna110and supplies detected symbols to processor unit130. It is noted that while blocks are depicted in a particular ordering, in other embodiments additional blocks may be added or the ordering may be changed (e.g., ADC unit220and signal processing unit230may appear in a different ordering), and there may be other connections between the various units than those shown. Numerous other configurations of receiver unit120are possible.

In the embodiments shown inFIGS. 2A-D, amplifier unit210receives a wireless signal from antenna110and amplifies it for processing by receiver unit120. In one embodiment, amplifier unit210may contain an automatic gain control (AGC) block that adjusts the amount of amplification based on the changing conditions of the wireless channel. For example, the AGC block (not shown) may automatically increase amplification if the strength of a detected signal weakens, or it may decrease amplification if the signal strengthens. In one such embodiment, the AGC block may include a feedback control loop including a mixer and one or more filters.

In the embodiments shown inFIGS. 2A-D, ADC unit220converts an amplified, analog signal received from amplifier unit210to a digital signal for further processing by receiver unit120. To accomplish this, ADC unit220may sample an incoming signal at variety of sampling rates using different techniques, as desired. ADC unit220is described in greater detail below in conjunction withFIG. 3.

In the embodiments shown inFIGS. 2A, C, and D, signal processing unit230demodulates a digital signal and processes the digital signal (e.g., to remove noise). In general, when a wireless signal is transmitted, it may be affected by interference present in the channel (e.g., from the receiving circuit itself, an interfering signal (referred to as a “blocker”), etc.). Sometimes this interference may occur as the result of another transmission such as one that occurs at only a given frequency range (i.e., a stationary blocker), or one that continually hops between a set frequencies (i.e., a non-stationary blocker). The ratio of the received signal strength to the amount of interference is often referred to as a signal to noise ratio (SNR). The SNR of the received signal may be low if the signal is weak compared to the noise; conversely, the SNR may be high if the signal is strong compared to the noise. Signal processing unit230may process a signal in various embodiments to increase the signal strength or remove undesirable interference using various filters and mixers. For example, in some embodiments, operations of signal processing unit230may include filtering the received signal (e.g., using one or more low pass filters), lowering the sampling rate of the received signal, removing any DC offset, adjusting the phase of the signal, and/or demodulating the received signal. In one embodiment, receiver unit120may also implement an adaptive frequency-hopping (AFH) algorithm in which a wireless signal pseudo-randomly changes carrier frequencies at regular time intervals to avoid interference from a stationary blocker (e.g., a WLAN). In various embodiments, signal processing functionality may be performed by a processor within communication device such as processor unit130.

Symbol detector unit240shown inFIGS. 2A, C, and D may analyze the version of the wireless signal it receives to determine a set of corresponding symbols. In general, the term “symbol” describes the state of the wireless signal during some period of time. Symbols may encode individual bits or a plurality of bits in a set of data. To detect a symbol from the wireless signal, a symbol detector may analyze the (digital or analog) received signal during a symbol interval using one or more samples to determine the amplitude and/or any phase change. In various embodiments, symbol detector unit240may contain a plurality of symbol detectors that implement different detection techniques. Each of these techniques may offer different levels of performance using different amounts of power. In some embodiments, the symbol detector(s) that are used (active) may be unique to certain modulation schemes or a given transmission rate. Symbol detector unit240is described in greater detail below in conjunction withFIGS. 4A and 4B.

FIGS. 2A-2Deach illustrate a power control unit250. Power control unit250is illustrated inFIGS. 2A,2B, and2D with a dotted line to indicate that it may be physically implemented in a variety of different manners. These embodiments thus depict a logical view of power control unit250. InFIGS. 2A-2D, power control unit250may change settings of various blocks in receiver unit120to regulate the performance and power usage of receiver unit120depending on state information of the wireless channel. As shown inFIG. 2A, power control unit250may change settings of any of amplifier unit210, ADC unit220, signal processing unit230, signal detector unit240, and processor unit130. Additionally, power control unit250may receive information from processor unit130. In other embodiments, power control unit250may be coupled with other combinations of blocks. In one embodiment, power control unit250may, during operation, change settings dynamically. In some embodiments, power control unit250may be implemented as combinatorial logic (e.g., configured to implement a state machine). Such logic may be internal or external to receiver unit120. In another embodiment, power control unit250may be a separate processor that is coupled to a memory that stores program instructions executable by the processor. Various inputs and outputs to power control unit250are described further with reference toFIGS. 5A-B.

As noted earlier, amplifier unit210, ADC unit220, signal processing unit230, symbol detector unit240, and power control unit250may be arranged in a variety of ways.

FIG. 2Billustrates another embodiment of receiver unit120that includes only amplifier unit210and ADC unit220. In such an embodiment, receiver unit210receives a wireless signal from antenna110and outputs an amplified, digitized version of the wireless signal to processor unit130. In the embodiment ofFIG. 2B, the remaining functionality is implemented in software (e.g., by a processor such as processor unit130executing program instructions stored in a memory such as memory134).

FIG. 2Cillustrates another embodiment of receiver unit120that includes power control unit250. In such an embodiment, receiver unit120may implement power control unit250in hardware or in software.

FIG. 2Dillustrates yet another embodiment of receiver unit120in which power control unit250is implemented externally to receiver unit120. In the illustrated embodiment, power control unit250is implemented by processor unit130(e.g., executing program instructions stored in memory134). Processor unit130may, in various embodiments, include dedicated functional units that are particularly suited for various signal processing techniques. In yet another embodiment, power control unit250may be implemented in hardware that is external to receiver unit120.

As noted above, receiver unit120may be configured to implement various Bluetooth standards. In the illustrated embodiments ofFIGS. 2A-2D, amplifier unit210, ADC unit220, signal processing unit230, and symbol detector unit240may be configured accordingly. In one embodiment, for example, signal processing unit230may use separate sets of mixers, filters, etc. depending upon whether the received Bluetooth signal is 1, 2, or 3 Mbps. In another embodiment, symbol detector unit240may select different symbol detectors based on modulation scheme and/or transmission rate of the received Bluetooth signal.

FIG. 3is a block diagram illustrating one embodiment of an ADC unit220. As shown, ADC unit220may include an ADC310that receives an amplified analog signal from amplifier unit210, performs analog-to-digital conversion, and provides a digital signal to signal processing unit230. In one embodiment, ADC310may be a sigma-delta analog-to-digital converter. In various embodiments, ADC unit220may include multiple ADC310s for digitizing one or more received signals. In some embodiments, power control unit250may be able to change the operation of ADC unit220by writing to one or more predetermined locations in register bank310.

In one embodiment, ADC unit220may receive either a full-bias current or a reduced-bias current, depending the strength of the wireless signal and the state of the channel. In a full-bias current mode, ADC unit220may consume more power while enabling receiver unit120to intercept a greater dynamic range of wireless signals relative to a reduced-bias current mode. Conversely, during a reduced-bias current mode, ADC unit220may consume less power while providing a lesser dynamic range relative to full-bias current mode. For example, in one embodiment, ADC unit220consumes up to 2 mA less by applying reduced-bias current instead of a full-bias current, where receiver unit120maintains a 40 dB blocker margin (i.e., separation between a received signal and any interfering signal) for received signals of up to −65 dBm when operating in full-bias current mode, and a 35 dB blocker margin when operating in reduced-bias current mode.

In various embodiments, the quantization step size of ADC unit220(e.g., the number of bits used to quantize the analog input signal to unit220) may be adjustable. In one embodiment, the quantization step size of ADC unit220may either be 2 bits or 1 bit. The quantization step size of unit220may be set orthogonally relative to the bias current setting, meaning that unit220's quantization step size is adjustable independent of the bias current setting. Accordingly, the bias current of ADC unit220may be reduced while leaving the quantization step size constant (e.g., at 2 bits). These settings may be employed, for example, when a wireless signal is experiencing a large amount of interference or is small in amplitude. Also, the bias current of ADC unit220may be reduced while also reducing quantization step size (e.g., from 2 bits to 1 bit) by turning off the last stage of unit220. These settings may be employed, for example, when the wireless signal is not experiencing a large amount of interference and the signal is large in amplitude.

In various embodiments, the automatic gain control (AGC) of amplifier unit210may be adjusted depending on the whether ADC unit220is receiving a full-bias current or a reduced-bias current. For example, more gain may be applied when the ADC unit220is operating in a reduced-bias mode, and less gain may be applied when the ADC unit220is operating in a full-bias mode.

FIG. 4Ais a block diagram of a symbol detector unit240A, which is one embodiment of a symbol detector240. In one embodiment, symbol detector unit240A is used during 1 Mbps Bluetooth transmission, which may occur, in one embodiment, when the wireless signal is modulated using GFSK modulation. As shown, symbol detector unit240A includes symbol detectors LS0, LS1, and LS2 (reference numerals414A-C, respectively), which are coupled to a multiplexor (MUX)410. In one embodiment, detectors LS1 and LS2 utilize some of the same hardware, with one of the detectors being selected for operation at a time (in some instances neither LS1 nor LS2 may be in use if LS0 is being used, allowing power to be saved by disabling LS1 and LS2).

In one embodiment, symbol detector unit240may receive a processed signal from signal processing unit230or ADC unit220and provide the received signal to any of the symbol detectors LS0, LS1, and LS2. The output symbols of symbol detectors414are selected by MUX410according to a value provided by, e.g., power control unit250and provided to processor unit130. In one embodiment, more than one output may be provided to processor unit130for further processing (e.g., permitting the comparing of the output of LS0 and the output of LS2 as described below).

The symbol detectors LS0, LS1, and LS2 may employ different techniques of varying complexity for determining a symbol from an input signal (e.g., from unit220or unit230). In one embodiment, LS0 may implement a detection technique that determines a symbol based solely on the phase of a single sample, while LS1 and LS2 may implement more complicated techniques that analyze multiple samples. LS1 and LS2 may compensate for inter-symbol interferences (ISI) using a Gaussian frequency-shaping filter. To implement such a filter, symbol detectors414may analyze a window that includes the current symbol and adjacent symbols. In one embodiment, LS1 may analyze a small window such as one created from the previous, current, and next symbols sampled at time intervals of −1, 0, 1 periods. LS2, in contrast, may analyze a larger window created from sampling the current symbol, adjacent symbols, and the midpoints between the adjacent and current symbols (e.g., sampling at time intervals of −1, −0.5, 0, 0.5, 1 periods). In one embodiment, LS2 may require a signal to be sampled at twice the signal rate as LS1.

In some embodiments, symbol detectors414that perform similar operations may share common circuitry or provide information to each other. In one embodiment, symbol detectors LS0, LS1, and LS2 each need to determine a phase of a signal, and thus share the same phase-determining block between them.

Because of their varying complexity, symbol detectors414(or450and460described below) may consume different amounts of power while providing different levels of performance. As a result, power control unit250may be used to help control the power usage of symbol detector unit240—e.g., by selecting an appropriate symbol detector. For example, power control unit250may select a detector that consumes less power (e.g., LS0) in cases where better-performing symbol detectors (e.g., LS2) are unnecessary. (Note that in some embodiments when one symbol detector (e.g., LS1 or LS2) is currently active, the output of another symbol detector (e.g., LS0) may be used for comparative purposes to determine the accuracy of the current detector.) On the other hand, if conditions change and better performance is needed, power control unit may250may select a better-performing detector. In various embodiments, when power control unit250provides an input to MUX410, symbol detector unit240may change the active symbol detector (i.e., the symbol detector that is currently being used to decode the information on the wireless signal). In one embodiment, changing the active symbol detector includes driving a clock signal for the selected symbol detector and disabling (or clock gating) the clock signal for the non-selected symbol detectors414. In other embodiments, changing the active symbol detector involves selecting its output (e.g., via MUX410). Such functionality may be accomplished in one embodiment by outputs of power control unit250.

FIG. 4Bis a block diagram of a symbol detector unit240B, another embodiment of symbol detector240. In one embodiment, symbol detector unit240B is employed when the wireless signal is 2 or 3 Mbps Bluetooth signal, and/or when the wireless signal is modulated using a PSK modulation scheme. As shown, symbol detector unit240B includes a differential symbol detector450and a coherent symbol detector460, which are coupled to a multiplexer (MUX)470. Symbol detector unit240may receive a processed signal from signal processing unit230or ADC unit220and provide the signal to each symbol detector. The output of the symbol detectors is selected by MUX470and provided to processor unit130. The output of MUX470may be selected in response to an input from power control unit250.

Differential symbol detector450and coherent symbol detector460employ different techniques for determining a symbol. In differential detection, a symbol is determined by measuring the phase change between received consecutive symbols. In coherent detection, a symbol is determined by tracking the signal phase and any frequency drifts. Coherent detection is a more complex operation that consumes more power than differential detection, but it is more resistant to noise and interference. As a result, coherent symbol detector460may be used when larger amounts of noise and interference are present. On the other hand, differential detection450may be used to conserve power in cases where coherent detection is unnecessary. In one embodiment, coherent detection may be used over differential detection when the detected or anticipated interference exceeds 30 dBc in order to provide a 2 dB improvement.

Note that while symbol detector units240A and240B are shown separately, symbol detector unit240may, in one embodiment (e.g., the embodiment shown inFIG. 4C), include all of the detectors shown inFIGS. 4A-B, and select among the various detectors using MUXs410,470, and490based not only on input from power control unit250but on information indicative of the current type of modulation for the wireless signal. (MUXs410,470and490inFIG. 4Ccan of course be implemented as one MUX.) In various embodiments, the clock may be disabled (or clocked gated) for detectors that are not active.

FIG. 5Aillustrates one embodiment of a power control unit250. As shown, power control unit may receive channel state information516and generate power setting values510in response thereto. In this manner, power control unit250may dynamically change one or more power setting valves to control the operation of various blocks (e.g., blocks210-240) in receiver unit120.

Power settings values510are outputs of power control unit250that are used to control the operation of various blocks within receiver unit120(e.g., amplifier unit210, ADC unit220, signal processing unit230, symbol detector unit240, or any combination thereof) or processor unit130. In one embodiment, power setting values510may be used to select an operating mode. For, example if the state of the wireless channel deteriorates, power control unit250may change the bias current in ADC unit220by outputting a particular setting value510(e.g., by writing to register bank330). In another embodiment, power setting values510may be used to select and/or disable specified components with a block of receiver unit120. For example, power control unit250may select or disable various components in signal processing unit230, or select and disable certain symbol detectors in symbol detector unit240. For example, power settings values510may be used to instruct receiver unit120to discard one quadrature component of a received wireless signal to reduce the SNR, which causes a chain of multiple receiver components to be disabled (e.g., one or more ADCs, quadrature filters, etc.).

As will be described in detail next, channel state information516can include a variety of information about the received wireless signal and the state of the channel. This information may include indications of signal strength, information indicative of interference conditions, indications of packet-level date errors, etc. These inputs may be provided from a variety of sources, including processor unit130and various blocks of receiver unit120.

FIG. 5Billustrates one specific embodiment of a power control unit250. As shown, power control unit250outputs power setting values510including bias mode550, detector selection552, and quadrature path selection554in response to receiving channel state information516including received signal strength indication (RSSI)560, packet error indication562, symbol detector difference indication564, and correlation indication566. Many different variations of these particular inputs and outputs are possible.

Received signal strength indication (RSSI)560indicates the strength of a signal as it is received, and is a good indication of channel conditions particularly at signal levels greater than −80 dBm. In various embodiments, RSSI560may be determined in hardware and/or software within receiver unit120and/or processor130. In one embodiment, RSSI560may be determined after the received signal has been processed and prior to symbol detection (e.g., between signal processing unit230and symbol detector unit240). In another embodiment, RSSI560may be determined prior to or during amplification in amplification unit210. In some embodiments, RSSI560may be determined when the received signal is converted from an analog signal to a digital signal in ADC unit220. In other embodiments, RSSI560may be determined from an intermediate frequency (IF) version of the wireless signal (e.g., in signal processing unit230). Generally, RSSI is a metric that is frequently used when describing signal strength, and various methods for determining it are known in the art.

Packet error indication562indicates whether the encoded packets of a received signal are arriving corrupted, and is a good indication for the presence of interference particularly when packet errors are present and/or when the average packet error rate (PER) exceeds a predetermined amount (e.g., 5 out of every 79 packets in one embodiment or 7 out of every 79 packets in another embodiment). In general, packet errors and a PER may be determined in a variety of ways. In one embodiment, a header error checksum (HEC) may be used to determine if errors exist in received packet headers, and packet error indication562may indicate whether any such header errors exist. In another embodiment, a cyclic redundancy checksum (CRC) may be used to determine if errors exist in the contents of received packets, and packet error indication562may indicate whether any such content errors occur. In other embodiments, an packet error rate (PER) may be determined for a set of packets (e.g., based on detected HEC or CRC errors), and packet error indication562may indicate such an error rate. It is noted that, in various embodiments, packet error indication562may be determined by various sources such as processor unit130, receiver unit120, etc.

Symbol detector difference indication564indicates whether the outputs of symbol detectors in symbol detector unit240differ, and provides an indication for the presence of interference particularly when the outputs of symbol detectors differ. In one embodiment mentioned above, multiple outputs of symbol detectors414(or symbol detectors450and460) may be provided to processor unit130for comparison, and processor unit130may generate symbol detector difference indication564to indicate the result of the comparison. In other embodiments, the comparison for symbol detector difference indication564may be performed elsewhere such as receiver unit120or power control unit250.

Correlation indication566is the computed correlation between two symbol detector outputs (e.g., LS0 and LS1/LS2), and is a statistical indicator of an interfering signal at a particular range of frequencies. In particular, correlation indication566, in some embodiments, may indicate a low SNR for the received signal when the variance of correlation indication566is greater than 8, and may indicate a high SNR when the variance of the correlation indication566is less than 1. For example, LS0 requires a high SNR in order for it to obtain the same bit error rate (BER) as LS1 or LS2. If the outputs of LS0 and LS2 are similar, then a high SNR exists and little interference is present. On the other hand, if the outputs of LS0 and LS2 differ significantly, then the SNR must be low due to noise or interference. In one embodiment, processor unit130may generate correlation indication566. In another embodiment, receiver unit120may generate correlation indication566.

Bias mode550selects an appropriate bias current (e.g., full bias or reduced bias) to apply to ADC unit220. In one embodiment, bias mode550may merely indicate the desired mode, which in response causes the receiver unit120to change the bias current that is applied to ADC unit220. For example, power control unit250may change the bias current through adjusting a value in a register of register bank310. In alternative embodiment, power control unit250may directly change the bias current that is applied to ADC unit220through changing the state of a circuit switch. In yet other embodiments, power control unit250may directly supply the bias current, where bias mode550is the bias current of ADC unit220. In various embodiments, the automatic gain control (AGC) of amplifier unit210may be adjusted based on the selection of bias mode550.

Detector selection552may select a desired symbol detector of symbol detector unit240. As mentioned above, detector selection552may be the input of a multiplexer that selects the output of a symbol detector (e.g., MUX410and470). In one embodiment, detector selection552may disable/turn off one or more non-selected symbol detectors.

Quadrature path selection554instructs receiver unit120to operate using one or both of the quadrature datapaths. In one embodiment, quadrature path selection554disables one or more ADCs located in ADC unit220if one quadrature datapath is disabled. In other embodiments, quadrature path selection554disables one or more filters and/or mixers in signal processing unit230when one quadrature datapath is disabled. In some embodiments, quadrature path selection554controls circuitry to clock gate the respective clock signals of various components. In various embodiments, quadrature selection554disables (without limitation) other receiver components, including, but not limited to, various analog or digital circuits including analog mixers, filters, amplifiers, LO drivers, etc. In certain embodiments, quadrature path selection554adaptively changes the low-intermediate frequency (IF) of the received signal—e.g., when receiving Bluetooth enhanced data rate (EDR) frames and using a single quadrature datapath.

As noted above, power control unit250may use different combinations of inputs and outputs as desired in other embodiments. For example, power control unit250may change settings or disable other components of receiver unit120, as desired.

FIG. 6Ais a flowchart of method600. Method600is one embodiment of a method implemented by receiver unit120. In step610, receiver unit120receives a wireless signal over a channel. In step620, receiver unit120processes the received signal using its various components, which may vary, e.g., as shown inFIGS. 2A-Dabove. As state of the channel varies over time, one or more settings of the receiver unit120are dynamically changed to control the receiver unit's power usage in response to power setting values510that are generated based on a first set of information that includes state information for the channel (e.g., channel state information516). For example, if a received signal has ample strength and is experiencing little interference, then less performance may be needed, and the first set of information may indicate to select lower power usage settings. On the other hand, if the signal is weaker or is experiencing significant interference, then the first set of information may indicate to change settings for better performance and greater power usage.

FIG. 6Bis a flowchart of method640. In one embodiment, method640may be implemented by power control unit250. In step650, power control unit250dynamically generates one or more power setting values510responsive to a first set of information that provides partial state information for a wireless channel (e.g. channel state information516), during a communication session over the wireless channel. The communication session may include reception of a wireless signal by receiver unit120that includes at least one analog circuit for processing the wireless signal. In step660, power control unit250conveys the one or more power setting values510to receiver unit120, causing the receiver unit120to change one or more settings to control its power usage (e.g., by controlling one or more analog circuits). For example, if the first set of information indicates that a received signal has ample strength and is experiencing little interference, the generated one or more power settings values510may cause the receiver unit120to lower its power usage (e.g., for a particular analog circuit). On the other hand, if the first set of information indicates that the signal is weaker or is experiencing significant interference, then the generated one or more power settings values510may cause the receiver unit120to increase its power usage.

FIG. 7illustrates a flowchart of one embodiment of a method (method700) for regulating power usage in receiver unit120. In one embodiment, method700may be implemented by power control unit250coupled to an ADC unit220and a symbol detector unit240(connections to other blocks are also possible). In one embodiment, method700may be implemented when the received wireless signal is modulated using GFSK modulation. States710-760represent various states that provide various levels of performance while consuming different amounts of power. When the flowchart proceeds from state710to state760, a receiver consumes less and less power while reducing its dynamic range. Many variations of method700are possible. Method700may be particularly suited to implementing a Bluetooth-compatible receiver unit120.

After initializing, method700begins in state710, with the receiver unit120operating at its highest power setting. There, power control unit250selects symbol detector LS2 and a full-bias current for ADC unit220. When higher performance is no longer needed, power control unit250may move to a lower performance state. For example, if packets encoded on the wireless signal are not experiencing HEC errors or CRC errors, inputs to power control unit250indicate the presence of a “large” blocker, and there are no differences detected between the outputs of detectors LS2 and LS0 (or the differences do not rise to the level of some predetermined threshold), method700proceeds to state720. (Indicators of a large blocker may include, in one embodiment, any of the following conditions: 1) the average PER exceeding 5/79 or 2) the RSSI exceeding −85 dBm and packets experiencing HEC errors.) Alternatively, if the Boolean expression “No LS2/LS0 Bit Diff AND (RSSI>−55 dBm OR (−80 dBm<RSSI<−55 dBm & No Large Blocker Present))” is satisfied (i.e., if there are no differences detected between the outputs of LS2 and LS0 (or the differences do not rise to the level of some predetermined threshold) and either a) the RSSI is greater than −55 dBm or b) the RSSI is between −80 dBm and −55 dBm when no large blockers are present), then method700proceeds to state730.

In state720, power control unit250selects symbol detector LS1 and a full-bias current for ADC unit220. If the Boolean expression “((HEC Errors OR CRC Errors) AND Large Blocker Present) OR LS1/LS0 Bit Diff” is satisfied (i.e., if packets are experiencing HEC errors or CRC errors and a large blocker is present or if the outputs LS0 and LS1 differ (e.g., by some predetermined amount, as determined by processor unit130—e.g., LS0 and LS1 differ by ten 10 bits during some predetermined time period)), method700returns to state710. However, if RSSI is greater than −55 dBm or if the RSSI is between −80 dBm and −55 dBm and no large blockers are present, method700proceeds to state730.

In state730, power control unit250selects symbol detector LS2 and a reduced-bias current. If more performance is required, method700may return to state710when the Boolean expression “LS2/LS0 Bit Diff OR (−80 dBm<RSSI<−55 dBm AND Large Blocker Present)” is satisfied (i.e., LS0 and LS2 differ (e.g., by some predetermined amount, as determined by processor unit130—e.g., LS0 and LS2 differ by ten 10 bits during some predetermined time period) or if the RSSI is between −80 dBm and −55 dBm and a large blocker becomes present. Alternatively, if packet transmission is not experiencing any HEC errors or CRC errors and there are no differences detected between the outputs of detectors LS2 and LS0 (or the difference do not rise to the level of some predetermined threshold), method700proceeds to state740.

In state740, symbol detector LS1 and a reduced-bias current for ADC unit220are selected by power control unit250. If packet transmission is experiencing any HEC or CRC errors, or the outputs of LS0 and LS1 differ (e.g., by some predetermined amount), method700returns to state730. On the other hand, if no HEC and CRC errors exist and there are no differences between the output of symbol detector LS1 and LS0 (or the differences do not rise to some predetermined threshold), method700proceeds to state750.

In state750, symbol detector LS0 and a reduced-bias current for ADC unit220are selected by power control unit250. If packet transmission experiences any HEC or CRC errors, method700returns to state730. Alternatively, if no HEC or CRC errors exist and RSSI is greater than −80 dBm, method700proceeds to state760.

In state760, power control unit250selects symbol detector LS0 and a reduced-bias current for ADC unit220, and instructs receiver unit120to use only one quadrature of the received signal. If the transmission experiences any HEC or CRC errors, method700returns to state740.

It is noted that the method700may not be applicable in all situations or may be modified in various embodiments, as desired. For example, in one embodiment, method700may be applied only when a 1 Mbps transmission rate is used. In such an embodiment, method800(described below with reference toFIG. 8) may be applied when 2 Mbps or 3 Mbps transmission rates are used.

Similarly, method700may not be applicable to all types of packets within a particular transmission rate. For example, within the context of method700, receiver unit120may receive packets that do not contain HEC or CRC fields (e.g. audio packets). In such embodiments, power control unit250may generate different power setting values510based on packet type (e.g. if the packet transmission contains audio packets without checksums, LS0 is selected when RSSI is greater than −55 dBm, and LS2 is selected if the RSSI is less than −55 dBm). In other embodiments, additional states may be added to method700. For example, method700may implement an additional state755, in which symbol detector LS0 and a full-bias current for ADC unit220are selected. Depending on the transmission, method700may proceed to state755from various other states inFIG. 7(e.g., state750or state720). In one embodiment, state755may be implemented as an alternative to state750.

FIG. 8illustrates a flowchart of method800usable to regulate power usage of receiver unit120. In one embodiment, method800may be implemented by a power control unit250coupled to an ADC unit220and various other units. When method800proceeds from blocks810-830, receiver unit120consumes less power while reducing its dynamic range. In one embodiment, method800is used when the received wireless signal is modulated with PI/4-DQPSK and 8-DPSK modulation schemes. Like method700, method800may be particularly suited to implementing a Bluetooth-compatible receiver unit120.

After initializing in state810, power control unit250selects a coherent symbol detector and a full-bias current for ADC unit220. During transmission, method800proceeds to state820when RSSI is greater than −55 dBm or when RSSI is between −80 dBm and −55 dBm and the average packet error rate is less than 5 out of 79.

In state820, power control unit250selects a reduced-bias current for ADC unit220. Method800returns to state810if RSSI is between −80 dBm and −55 dBm and the average packet error rate exceeds 5 out every 79 packets. Alternatively, if RSSI is greater than −55 dBm, the average packet error rate is less than 5 out of 79, and no HEC or CRC errors are present, then method800proceeds to step830.

In state830, power control unit250selects a reduced current mode for ADC unit220and instructs receiver unit120to disable one quadrature datapath. Such a configuration consumes significantly less power because the circuitry that processes one of the two quadrature data streams is disabled. If the transmission experiences any HEC or CRC errors, method800returns to state820.

In certain embodiments, receiver unit120is configured to adaptively change the low-intermediate frequency (IF) when it receives Bluetooth enhanced data rate (EDR) frames. In order for EDR frames to work in a low-IF system, power control unit250may be configured to increase the intermediate frequency (IF) when the receiver unit120is entering single-quadrature mode. In one particular embodiment, receiver unit120may employ a 500 kHz offset for a 1 MHz wide received signal, but such an offset may not work well with 8DPSK frames in EDR mode. As such, receiver unit120may increase the received signal to 700 kHz or more to fix this problem.

Various embodiments for regulating the power usage of a receiver unit described herein may include storing instructions and/or data implemented in accordance with the foregoing description in an article of manufacture such as tangible computer-readable memory medium, including various portions of the memory in receiver unit120, processor unit130(e.g., memory134), and power control unit250. Certain embodiments of these tangible computer-readable memory media may store instructions that are computer executable to perform actions in accordance with the present disclosure. Generally speaking, such an article of manufacture may include storage media or memory media such as magnetic (e.g., disk) or optical media (e.g., CD, DVD, and related technologies, etc.). The article of manufacture may be either volatile or nonvolatile memory. For example, the article of manufacture may be (without limitation) SDRAM, DDR SDRAM, RDRAM, SRAM, flash memory, and of various types of ROM, etc. Power control unit250shown inFIGS. 5A and 5B, for example, may include tangible computer-readable media storing program instructions that are executable for dynamically generating one or more power setting values. Receiver unit120, for example, may include tangible computer-readable media storing program instructions that are executable for dynamically changing one or more settings to control power usage. In general, any of the methods described herein as being implementable in software may be implemented using program instructions that are stored on various forms of tangible computer-readable media.

Further embodiments of programs described herein may include storing/encoding instructions and/or data on signals such as electrical, electromagnetic, or optical signals, conveyed via a communication medium, link, and/or system (e.g., cable, network, etc.), whether wired, wireless or both. Such signals may carry instructions and/or data implemented in accordance with the foregoing description.