Circuit for controlling a latch mode of a pulse width modulation circuit and method thereof

A circuit for controlling a latch mode of a pulse width modulation circuit includes a D flip-flop, a voltage generation unit, a comparator, and a logic unit. The D flip-flop generates a switch control signal according to a latch enable signal. The voltage generation unit generates a discharge current, and a voltage divider resistor group included in the voltage generation unit generates a first voltage when the voltage generation unit is turned on according to the switch control signal. A voltage of a predetermined pin of the pulse width modulation circuit is equal to a predetermined voltage when the discharge current is equal to the charge current. The comparator compares a reference voltage with the first voltage to generate a comparison signal. The logic unit generates a clear signal according to the comparison signal. The D flip-flop clears the switch control signal according to the clear signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit for controlling a latch mode of a pulse width modulation circuit and a method thereof, and particular to a circuit for controlling a latch mode of a pulse width modulation circuit and a method thereof that not only can provide an unlatched voltage which is accurate and is not easily influenced by an external environment of the pulse width modulation circuit, but can also let a user calculate time for the unlatched voltage.

2. Description of the Prior Art

Generally speaking, a pulse width modulation circuit utilizes latch mode protection to prevent an alternating current/direct current converter to which the pulse width modulation circuit is applied from being burned down in an abnormal condition, where the latch mode protection can be over voltage protection, over current protection, over load protection, over temperature protection, and so on. In addition, the prior art utilizes turning-off of an alternating input voltage of the alternating current/direct current converter to let a voltage of a predetermined pin of the pulse width modulation circuit be decreased to a predetermined voltage level, resulting in the latch mode protection of the pulse width modulation circuit being removed.

In the prior art, a stabilizing diode coupled to the predetermined pin of the pulse width modulation circuit is used for setting a voltage level of the predetermined pin of the pulse width modulation circuit after the latch mode protection is removed. However, the prior art has disadvantages as follows: first, the stabilizing diode can increase a chip area of the pulse width modulation circuit; second, the voltage level of the predetermined pin of the pulse width modulation circuit after the latch mode protection is removed is easily influenced by an external environmental temperature of the pulse width modulation circuit; and third, the stabilizing diode usually has a ±5% error.

SUMMARY OF THE INVENTION

An embodiment provides a circuit for controlling a latch mode of a pulse width modulation circuit. The circuit includes a D flip-flop, a voltage generation unit, a comparator, and a logic unit. The D flip-flop is used for generating a switch control signal according to a latch enable signal. The voltage generation unit includes a voltage divider resistor group, where the voltage generation unit generates a discharge current, and the voltage divider resistor group generates a first voltage according to the discharge current and a charge current generated by a primary side of an alternating current/direct current converter which the pulse width modulation circuit is applied to when the voltage generation unit is turned on according to the switch control signal, where a voltage of a predetermined pin of the pulse width modulation circuit is equal to a predetermined voltage when the discharge current is equal to the charge current. The comparator is used for comparing a reference voltage with the first voltage to generate a comparison signal. The logic unit is used for generating a clear signal according to the comparison signal. The D flip-flop is further used for clearing the switch control signal according to the clear signal.

Another embodiment provides a method for controlling a latch mode of a pulse width modulation circuit. A circuit for controlling the latch mode of the pulse width modulation circuit includes a D flip-flop, a voltage generation unit, a comparator, and a logic unit, where the voltage generation unit includes a voltage divider resistor group. The method includes the D flip-flop generating a switch control signal according to a latch enable signal; the voltage generation unit generating a discharge current, and the voltage divider resistor group generating a first voltage according to the discharge current and a charge current generated by a primary side of an alternating current/direct current converter which the pulse width modulation circuit is applied to when the voltage generation unit is turned on according to the switch control signal, where a voltage of a predetermined pin of the pulse width modulation circuit is equal to a predetermined voltage when the discharge current is equal to the charge current; the comparator comparing a reference voltage with the first voltage to generate a comparison signal; the logic unit generating a clear signal according to the comparison signal; and the D flip-flop clearing the switch control signal according to the clear signal.

The present invention provides a circuit for controlling a latch mode of a pulse width modulation circuit and a method thereof. The circuit and the method utilize a D flip-flop to generate a switch control signal according to a latch enable signal. Then, a voltage generation unit is turned on according to the switch control signal, and generates a discharge current, where when the discharge current is equal to a charge current generated by a primary side of an alternating current/direct current converter, a voltage of a predetermined pin of the pulse width modulation circuit is equal to a predetermined voltage. Therefore, a user can adjust the predetermined voltage by controlling the charge current, and the user can know time for the voltage of the predetermined pin being decreased from the predetermined voltage to an unlatched voltage by a capacitor coupled to the predetermined pin. Thus, compared to the prior art, the present invention not only can provide the unlatched voltage which is accurate and is not easily influenced by an external environment of the pulse width modulation circuit, but can also let the user control the time for the voltage of the predetermined pin being decreased from the predetermined voltage to the unlatched voltage by adjusting the capacitor coupled to the predetermined pin.

DETAILED DESCRIPTION

Please refer toFIG. 1.FIG. 1is a diagram illustrating a circuit100for controlling a latch mode of a pulse width modulation circuit according to an embodiment. The circuit100includes a D flip-flop102, a voltage generation unit104, a comparator106, and a logic unit108. The D flip-flop102is used for generating a switch control signal SCS according to a latch enable signal LAT, where an input terminal D of the D flip-flop102is used for receiving a high voltage VH, an input terminal CK of the D flip-flop102is used for receiving the latch enable signal LAT, an input terminal CL of the D flip-flop102is used for receiving a clear signal CS, and an output terminal Q of the D flip-flop102is used for outputting the switch control signal SCS. The voltage generation unit104includes a voltage divider resistor group (voltage divider resistors1042and1044), where when a current source1046included in the voltage generation unit104is turned on according to the switch control signal SCS, the current source1046generates a discharge current ICC according to a voltage VCC of a predetermined pin202of the pulse width modulation circuit200(that is, the discharge current ICC is varied with the voltage VCC of the predetermined pin202), and the voltage divider resistors1042and1044generate a first voltage V1 according to the discharge current ICC and a charge current IDC generated by a primary side of an alternating current/direct current converter which the pulse width modulation circuit200is applied to, where when the discharge current ICC is equal to the charge current IDC, the voltage VCC of the predetermined pin202is equal to a predetermined voltage VP. In addition, as shown inFIG. 1, the charge current IDC is determined by a direct current voltage VDC of the primary side of the alternating current/direct current converter and a charging resistor RC of the primary side. In addition, in another embodiment of the present invention, the charge current IDC is determined by an alternating current voltage VAC of the primary side of the alternating current/direct current converter and the charging resistor RC (as shown inFIG. 2). The logic unit108is used for generating the clear signal CS according to a comparison signal COS. The D flip-flop102is further used for clearing the switch control signal SCS according to the clear signal CS. As shown inFIG. 1, the comparator106is used for comparing a reference voltage VREF with the first voltage V1 to generate the comparison signal COS, where when the reference voltage VREF is greater than the first voltage V1, the comparator106generates the comparison signal COS, and the logic unit108is an inverter. In another embodiment of the present invention (as shown inFIG. 3), the comparator106generates the comparison signal COS when the reference voltage VREF is smaller than the first voltage V1, and the logic unit108is composed of two series connected inverters. In addition, in another embodiment of the present invention (as shown inFIG. 4), the comparator106generates the comparison signal COS when the reference voltage VREF is smaller than the first voltage V1, and the charge current IDC is determined by the alternating current voltage VAC of the primary side of the alternating current/direct current converter and the charging resistor RC.

Please refer toFIG. 5.FIG. 5is a diagram illustrating variation of the voltage VCC of the predetermined pin202. As shown inFIG. 5, an induced voltage VI of an auxiliary winding110of the primary side of the alternating current/direct current converter is gradually increased when the alternating current/direct current converter receives and filters the alternating current voltage VAC into the direct current voltage VDC, so the voltage VCC of the predetermined pin202starts to gradually increase from 0V. Meanwhile, the current source1046is not turned on yet, and the discharge current ICC (e.g. a 15 uA leakage current) flowing through the predetermined pin202is smaller than the charge current IDC (e.g. 220 uA), so the voltage VCC of the predetermined pin202can be continuously increased to a first predetermined voltage VP1 (e.g. 15V). When the voltage VCC of the predetermined pin202is equal to the first predetermined voltage VP1, the pulse width modulation circuit200starts to generate pulse width modulation signals, and a switch112of the primary side of the alternating current/direct current converter starts to be turned on and turned off according to the pulse width modulation signals. When the switch112starts to be turned on and turned off according to the pulse width modulation signals (meanwhile, the current source1046is still turned off), the discharge current ICC (e.g. 2 mA) flowing through the predetermined pin202is provided to other circuits within the pulse width modulation circuit200.

As shown inFIG. 1andFIG. 5, when the pulse width modulation circuit200generates the latch enable signal LAT due to over voltage protection, over current protection, over load protection, over temperature protection, and so on, the D flip-flop102generates the switch control signal SCS to the current source1046according to the latch enable signal LAT, and the pulse width modulation circuit200stops transmitting the pulse width modulation signals to the switch112according to the latch enable signal LAT. Meanwhile, because the current source1046is turned on according to the switch control signal SCS, the first voltage V1 is a partial voltage of the voltage VCC of the predetermined pin202. Because the pulse width modulation circuit200stops transmitting the pulse width modulation signals to the switch112, the voltage VCC of the predetermined pin202starts to be decreased and the discharge current ICC flowing through the predetermined pin202starts to be also decreased.

As shown inFIG. 5, when the voltage VCC of the predetermined pin202is continuously decreased to the predetermined voltage VP, the discharge current ICC flowing through the predetermined pin202is equal to the charge current IDC. Thus, the voltage VCC of the predetermined pin202can be maintained at the predetermined voltage VP. That is to say, a user can adjust the predetermined voltage VP by controlling the charge current IDC. However, when the alternating current voltage VAC is removed, the charge current IDC is decreased to zero. Meanwhile, the voltage VCC of the predetermined pin202starts to be decreased to an unlatched voltage VDL according to the discharge current ICC flowing through the predetermined pin202, where time T for the voltage VCC of the predetermined pin202being decreased from the predetermined voltage VP to the unlatched voltage VDL is determined according to equation (1):
T=(VP−VDL)/C(1)

As shown in equation (1), C is a capacitance of a capacitor114coupled to the predetermined pin202. Therefore, the user can know that how long the alternating current voltage VAC can be connected to the primary side of the alternating current/direct current converter again after the alternating current voltage VAC is removed.

As shown inFIG. 1andFIG. 5, when the voltage VCC of the predetermined pin202is lower than the unlatched voltage VDL, because the reference voltage VREF is greater than first voltage V1, the comparator106generates the comparison signal COS, resulting in the logic unit108generating the clear signal CS according to the comparison signal COS. Therefore, the D flip-flop102can clear the switch control signal SCS according to the clear signal CS, resulting in the voltage generation unit104being turned off, and the first voltage V1 is increased to a high voltage. In addition, in another embodiment of the present invention, when the voltage generation unit104is turned on according to the switch control signal SCS, the voltage generation unit104utilizes a fixed current source to generate the discharge current ICC, where subsequent operational principles thereof can be referred toFIG. 1andFIG. 5, so further description thereof is omitted for simplicity.

Please refer toFIG. 6,FIG. 1,FIG. 2,FIG. 3,FIG. 4, andFIG. 5.FIG. 6is a flowchart illustrating a method for controlling a latch mode of a pulse width modulation circuit according to another embodiment. The method inFIG. 6is illustrated using the circuit100inFIG. 1. Detailed steps are as follows:

Step402: The D flip-flop102generates a switch control signal SCS according to a latch enable signal LAT.

Step404: When the voltage generation unit104is turned on according to the switch control signal SCS, the voltage generation unit104generates a discharge current ICC, and the voltage divider resistors1042and1044generate a first voltage V1 according to the discharge current ICC and a charge current IDC generated by the primary side of the alternating current/direct current converter.

Step406: The comparator106compares a reference voltage VREF with the first voltage V1 to generate a comparison signal COS.

Step408: The logic unit108generates a clear signal CS according to the comparison signal COS.

Step410: The D flip-flop102clears the switch control signal SCS according to the clear signal CS; go to Step402.

In Step402, the pulse width modulation circuit200can generate the latch enable signal LAT to the D flip-flop102due to the over voltage protection, the over current protection, the over load protection, the over temperature protection, and so on. Therefore, the D flip-flop102can generates the switch control signal SCS to the voltage generation unit104according to the latch enable signal LAT. In Step404, the current source1046included in the voltage generation unit104generates the discharge current ICC according to a voltage VCC of the predetermined pin202of the pulse width modulation circuit200(that is, the discharge current ICC is varied with the voltage VCC of the predetermined pin202), and the voltage divider resistors1042and1044generate the first voltage V1 to the comparator106according to the discharge current ICC and the charge current IDC, where the charge current IDC is determined by a direct current voltage VDC of the primary side of the alternating current/direct current converter and the charging resistor RC, the voltage VCC corresponds to an induced voltage VI generated by the auxiliary winding110, and the first voltage V1 is a partial voltage of the voltage VCC of the predetermined pin202. As shown inFIG. 5, when the voltage VCC of the predetermined pin202is continuously decreased to the predetermined voltage VP, the discharge current ICC flowing through the predetermined pin202is equal to the charge current IDC. Thus, the voltage VCC of the predetermined pin202can be maintained at the predetermined voltage VP. In Step406, when the reference voltage VREF is smaller than the first voltage V1, the comparator106does not generate the comparison signal COS. However, as shown inFIG. 5, when the alternating current voltage VAC is removed, the charge current IDC is decreased to zero, resulting in the comparator106generating the comparison signal COS when the first voltage V1 is decreased with the voltage VCC of the predetermined pin202to be lower than the reference voltage VREF (that is, the voltage VCC is lower than the unlatched voltage VDL). But, in another embodiment of the present invention (as shown inFIG. 3andFIG. 4), the comparator106generates the comparison signal COS when the reference voltage VREF is smaller than the first voltage V1. In Step408, the logic unit108(e.g. the inverter as shown inFIG. 1) can generate the clear signal CS according to the comparison signal COS. In Step410, the D flip-flop102clears the switch control signal SCS according to the clear signal CS, resulting in the voltage generation unit104being turned off, and the first voltage V1 is increased to a high voltage again. Thus, the D flip-flop102can wait for the latch enable signal LAT generated by the pulse width modulation circuit200due to the over voltage protection, the over current protection, the over load protection, the over temperature protection, and so on again.

To sum up, the circuit for controlling the latch mode of the pulse width modulation circuit and the method thereof utilize the D flip-flop to generate a switch control signal according to a latch enable signal. Then, the voltage generation unit is turned on according to the switch control signal, and generates a discharge current, where when the discharge current is equal to a charge current generated by the primary side of the alternating current/direct current converter, a voltage of the predetermined pin of the pulse width modulation circuit is equal to the predetermined voltage. Therefore, the user can adjust the predetermined voltage by controlling the charge current, and the user can know time for the voltage of the predetermined pin being decreased from the predetermined voltage to the unlatched voltage by the capacitor coupled to the predetermined pin. Thus, compared to the prior art, the present invention not only can provide the unlatched voltage which is accurate and is not easily influenced by an external environment of the pulse width modulation circuit, but can also let the user control the time for the voltage of the predetermined pin being decreased from the predetermined voltage to the unlatched voltage by adjusting the capacitor coupled to the predetermined pin.