Test pad design for reducing the effect of contact resistances

An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.

CROSS-REFERENCE TO RELATED APPLICATION

This application relates to commonly-assigned U.S. patent application Ser. No. 11/731,444, filed Mar. 30, 2007, and entitled “High Accuracy and Universal On-Chip Switch Matrix Testline,” which application is hereby incorporated herein by reference.

TECHNICAL FIELD

This invention relates generally to the manufacturing of integrated circuits, and more particularly to wafer acceptance tests, and even more particularly to reducing the effect of contact resistances of test pads.

BACKGROUND

Integrated circuit (IC) manufacturers are employing increasingly smaller dimensions and corresponding technologies to make smaller, high-speed semiconductor devices. Along with these advancements, the challenges of maintaining yield and throughput have also increased.

A semiconductor wafer typically includes dies (or chips) separated from each other by scribe lines. Individual chips within the wafer contain circuitry, and the dies are separated by sawing and then are individually packaged. In a semiconductor fabrication process, semiconductor devices on wafers (e.g., an integrated circuit) must be tested at selected steps, or at the end, of the formation so as to maintain and assure device quality. Usually, a testing circuit is simultaneously fabricated on the wafer along with the actual devices. A typical testing method provides a plurality of test pads (commonly referred to as process control monitor pads, or PCM pads) located on the surface scribe lines. The test pads are selected to test different properties of the wafers, such as voltages, drive currents, leakage currents, and the like.

FIG. 1illustrates test line10, which may be formed in a scribe line of a wafer, and may include more or fewer test pads (named as TP1through TP10) than shown inFIG. 1. Each of test pads TP1through TP10is connected to a node of the device (or circuit) to be probed. For example, test pads TP1through TP4may be used to probe a transistor by connecting to the source, drain, gate, and bulk of the transistor.

A portion of a test scheme is shown inFIG. 2, which is used to test (probe) transistor22. Drain24of transistor22is connected to test pad TP1. Sense-measurement-unit (SMU)12is connected to test pad TP1through a test pin, which is symbolized by node14. Resistor Rc represents the contact resistance between the test pin and test pad TP1. SMU12has a forcing node16, which is connected to the output of amplifier18, and a sensing node20, which is connected to the negative input of amplifier18. To test transistor22, SMU12tries to force a voltage, for example, of 1V to drain24of transistor22, and the current I flowing through transistor22is sensed.

Due to the contact resistance Rc, the voltage applied on drain24of transistor22is reduced. For example, if contact resistance Rc is 30 Ohms, and current I is 1 mA, the voltage drop on the contact resistance Rc is 30 mV. When the voltage at test pin14is 1V, the voltage applied on drain24drops to 0.97V, which is a three percent shift from the desirable voltage. The sensed current is shifted accordingly, causing the inaccuracy of the evaluation in the performance of transistor22.

For a 32 nm nominal device having a gate width of about 1 μm and a gate length of about 0.04 μm, the shift in the sensed performance may reach as great as about 10 percent. To make it worse, the contact resistance Rc is affected by various factors, such as the queue-time of the probed wafer, the probe card overdrive, and the probe card quality. As a result, contact resistance Rc may vary in a wide range, making it very difficult to compensate for the inaccuracy of the probe. Accordingly, what is needed in the art is a sensing scheme and structure that may overcome the deficiencies of the prior art.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, an integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in each pair of the plurality of test pads interconnected to each other.

In accordance with another aspect of the present invention, an integrated circuit structure includes a semiconductor wafer including a first semiconductor chip and a second semiconductor chip; a scribe line between the first and the second semiconductor chips; a test line in the scribe line; and a first, a second, a third, and a fourth test pad in the test line. The first and the second test pads are interconnected to form a first pair. The third and the fourth test pads are interconnected to form a second pair.

In accordance with yet another aspect of the present invention, an integrated circuit probing device includes a plurality of sense-measurement-units, each including a forcing node; and a sensing node electrically coupled to the forcing node. The integrated circuit probing device further includes a probe card including a plurality of pairs of probe pins. Each pair of probe pins includes a first probe pin connected to the forcing node, and a second probe pin connected to the sensing node, wherein the forcing node and the sensing node are in a same one of the plurality of sense-measurement-units.

The advantageous features of the present invention include reduced effect of contact resistances between probe pins and test pads. The accuracy of the probing is thus improved.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A novel test pad design and the corresponding probe scheme are provided. The variations and operation of the preferred embodiments are discussed. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.

FIG. 3illustrates wafer30including a plurality of semiconductor chips32therein. Semiconductor chips32are separated from each other by scribe lines34, which are to be sawed during packaging processes in order to separate semiconductor chips32from each other. Test lines36are formed in wafer30. Each test line36includes a plurality of test pads TP (not shown inFIG. 3, please refer toFIG. 4) exposed through the top surface of wafer30. In the preferred embodiment, test lines36are formed in scribe lines34. In alternative embodiments, test lines36may be formed inside semiconductor chips32.

FIG. 4illustrates a top view of an embodiment of an exemplary test line36. In the preferred embodiment, test pads TP (denoted as either test pads TPs or TPf) are formed as pairs. In each pair, one of the test pads TP is used for forcing voltages or currents during the probing of wafer30, and hence is referred to as forcing pad TPf. The other test pad of the pair is used for sensing voltages or currents, and hence is referred to as sensing pad TPs. The design and the dimensions of sensing pads TPs may be identical to that of forcing pads TPf. The connection and the function of a test pad TP during the probing determine whether a test pad is a forcing pad or a sensing pad.

In each pair of the test pads36, sensing pad TPs and forcing pad TPf are interconnected, and are connected to a same node of the device (or a circuit) to be sensed (also referred to as device-under-test, or DUT). Throughout the description, when two test pads are referred to as being “interconnected,” it means the test pads are connected only through the commonly used interconnection lines and vias, and no active devices such as transistors are formed therebetween. Further, no passive devices such as resistors, capacitors, and/or inductors are intentionally formed between the interconnected test pads, although parasitic passive devices are sometimes inevitable. However, the parasitic passive devices need to have as small as possible effect on the interconnected test pads. For example, the resistances of the connection lines between the sensing pad TPs and the forcing pad TPf in a same pair are as small as possible. Accordingly, the forcing pad TPf and the sensing pad TPs may be interconnected at a point close to the forcing pad TPf and the sensing pad TPs, or in other words, close to the top surface of the respective semiconductor chip. In an exemplary embodiment, a metal line in the passivation layer or the top metallization layer interconnects a pad TPs to a pad TPf. The DUT is then connected to the metal line through a common conductive path40, as is also shown inFIG. 4.

By using test line36as shown inFIG. 4, each of the nodes in the DUT is connected to a pair of, instead of only one, test pads TP. In the exemplary embodiment as shown inFIG. 4, transistor44, which is a DUT, includes bulk (substrate)46, drain48, source50, and gate52. Therefore, for the probing of transistor44, four pairs of test pads TP are needed, with each pair being interconnected, and connected to one of the above-discussed nodes. One skilled in the art will realize that for different DUTs, more or fewer pairs of test pads may be needed. For example, for probing a resistor, only two pairs of test pads are needed.

Since each pair of test pads TP is physically separated from other pairs, for the probing of each node of the DUT, a pair of probe pins is needed.FIG. 4schematically illustrates probe card60, which includes a plurality of pairs of probe pins P (denoted either as Pf or Ps). Each pair of probe pins P is connected to a sense-measurement-unit (SMU)62, wherein more details of SMUs62are shown inFIG. 5. Each of the SMUs62has two ends, each being connected to one of the probe pins Pf and Ps, wherein probe pins Pf are used to force voltages and/or currents to the DUT, and probe pins Ps are used to sense voltages and/or currents. The positions of the probe pins Pf and Ps are arranged corresponding to that of test pads TP, so that each of the probe pins Ps/Pf may be in contact with one, and only one, of test pads TP. In other words, with the design of probe card60known, test pads TP need to be arranged to match the positions of probe pins P.

FIG. 5illustrates an exemplary scheme for connecting SMU62to transistor44, which is used as an exemplary DUT. Please note SMU62is illustrated as having operational amplifier64, which is commonly used in the sense-measurement-units. However, in the embodiments of the present invention, a sense-measurement-unit may have different designs. SMU62is connected to a pair of test pads, including sensing pad TPs and forcing pad TPf. SMU62includes forcing node66, which is connected to the output of operational amplifier64, and sensing node68, which is connected to one of the inputs of operational amplifier64. Resistor Rc1represents the contact resistance between test pin Pf and test pad TPf, and resistor Rc2represents the contact resistance between test pin Ps and test pad TPs.

To probe transistor44, SMU62tries to force a voltage, for example 1V, to drain48of transistor44. Accordingly, the voltage at sensing node68is set to 1V. Since the forcing and sensing paths are separated, current I2flowing through contact resistor Rc2may be very low, and may be in the order of nano amps. In an exemplary embodiment, assuming current I2is 1 nA, and contact resistor Rc1has a resistance of 30 Ohms, the voltage drop on the contact resistor Rc2is thus only 0.03 mV. The voltage applied on drain48of transistor44is (1V-0.03 mV), or 0.99997 V. Therefore, contact resistance Rc2has very little effect on the accuracy of the probe, and the desirable voltages can be accurately applied on drain48. Current I1may be sensed through test pad TPs. Since the voltage applied on drain48is accurate, the sensed current I1is also accurate. In the preferred embodiment, during the probing, current I2is at least two orders lower than current I1.

Similarly, an additional SMU62is connected to source50of transistor44through a pair of test pads. Although not shown inFIG. 5, gate52and possibly the bulk (substrate) of transistor44are also each connected to a SMU62through a pair of test pads. A schematic connection is shown inFIG. 4.

Referring back toFIG. 4, in an embodiment of the present invention, the forcing pad Pf and sensing pad Ps in same pairs are closely located. In an exemplary embodiment, distance D1between a forcing pad TPf and a sensing pad TPs in a same pair is less than about 10 μm, and is more preferably between about 0.2 μm and about 10 μm, while distance D2between neighboring test pad pairs is greater than about 10 μm, and is more preferably between about 10 μm and about 100 μm. A ratio of distance D1to distance D2may be less than 1, and is more preferably between about 1/50 and about 1. Accordingly, in probe card60, the probe pins P that belong to a same pair are located closely to match the spacings of test pads TP.

FIG. 6illustrates an alternative embodiment of the present invention. In test line36, the test pads TP are equally spaced. However, sensing pads TPs and forcing pads TPf are placed in an alternating pattern, and sensing pads TPs are connected to respective neighboring forcing pads TPf to form test pad pairs.

FIG. 7illustrates yet another embodiment of the present invention. In test line36, the test pads TP are equally spaced. Sensing pads TPs are placed together as a group, and forcing pads TPf are placed together as another group. Each of the sensing pads TPs is still connected to one of the forcing pads TPf to form a test pad pair. One skilled in the art will realize there are many variations for how to place sensing pads TPs and forcing pads TPf to suit different test requirements. The design of probe card60(refer toFIG. 4) is also arranged accordingly.

In the above-discussed embodiments, test lines are used as examples to explain the concept of the present invention. However, the teaching of the embodiments of the present invention may be applied to test keys, and may be used in the probing of circuits inside semiconductor chips (as compared to in the scribe lines). The paired test pads of the circuits inside a semiconductor chip may be arranged as test lines, as shown inFIG. 3, or in any other form such as pad arrays, as long as the probe cards also have paired test pins whose arrangements match that of the paired test pads.

Advantageously, in the embodiments of the present invention, the accuracy of the probing is significantly improved. Referring back toFIG. 4, assuming current I2is 1 nA, and contact resistor Rc2has a resistance of 30 Ohms, when SMU62tries to force a 1V voltage to node68, the voltage at drain48is shifted from the desirable value by only 0.003 percent. If, however, test pads TPf and TPs are combined into one pad, as in the conventional design, and current I1is 1 nA, the voltage shift will be 3 percent, or 30 mV, which is 1000 times greater than in the embodiments of the present invention.