Laminate stacked capacitor, circuit substrate with laminate stacked capacitor and semiconductor apparatus with laminate stacked capacitor

A method of manufacturing a capacitor includes forming a first ceramic film on a first base made of a metal, forming a second ceramic film on a second base made of a metal, forming a first copper electrode pattern and a first copper via-plug on a surface of one of the first and second ceramic films, the electrode pattern and the via-plug being separate from each other, bonding the first and second ceramic films together with the first electrode pattern and the via-plug therebetween, by applying a pulsed voltage between the first base and the second base while the first base and the second base are pressed so that the first ceramic film and the second ceramic film are pressed on each other, and removing the second base.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-203637, filed on Sep. 10, 2010, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a method for manufacturing capacitor, and to a capacitor, a circuit substrate and a semiconductor apparatus.

BACKGROUND

As electronic apparatuses are miniaturized and their performances are increased, it is desirable that mounting techniques be improved in terms of the miniaturization and performance increase.

In circuit substrates used in electronic apparatuses and information processing apparatuses, such as personal computers and servers, logical elements, such as CPUs, are provided with a decoupling capacitor around them so that stable current supply can be ensured and/or so that noise can be removed even if the power-supply voltage fluctuates. This is increasingly important with the increase in operating frequency of CPUs and with the decrease in operating voltage.

In particular, in order to quickly compensate for the fluctuation of the voltage applied to the CPU, it is effective to control the impedance of the power-supply system including the decoupling capacitor. Accordingly, a high capacitance capacitor having a low inductance is desirable, and it is also desirable to reduce the length and hence the inductance of the power-supply wiring to the decoupling capacitor on the circuit substrate.

In order to reduce the inductance of the power supply wiring to the decoupling capacitor on the circuit substrate, it is believed that the most effective approach is to dispose a decoupling capacitor immediately under the CPU and to dispose the decoupling capacitor within the circuit substrate. This structure can lead to a cost reduction in manufacturing semiconductor devices and circuit substrates.

Related art references include the following documents:

Japanese Laid-open Patent Publication No. 2007-318089 (corresponds to US Publication No. 2007/0263364); and

In a method proposed for incorporating a decoupling capacitor into a circuit substrate, a capacitor component is prepared by firing at a high temperature a multilayer structure including ceramic green sheets on which electrode patterns have been printed, and the resulting capacitor component is embedded in a circuit substrate. Another method has also been proposed in which a capacitor dielectric film is formed for each of a plurality of build-up layers, and the thus formed capacitor dielectric films are stacked in a process for forming a build-up circuit substrate.

Recently, a capacitor has been proposed which includes a platinum lower electrode on a silicon substrate coated with a silicon oxide film, a highly dielectric or ferroelectric ceramic dielectric film formed on the lower electrode by sputtering, a platinum upper electrode on the ceramic dielectric film, and connection electrodes extending upward respectively from the lower electrode and the upper electrode.

For a circuit substrate containing a completed capacitor component, the capacitor component is generally prepared by firing a stack of a plurality of green sheets containing a large amount of organic binder on each of which an electrode pattern has been printed. However, in this instance, the green sheets are significantly shrunk by the firing. Accordingly, it is difficult to form a fine electrode pattern on such a green sheet. For mounting a capacitor component on a circuit substrate, a high-resistance solder is used for bonding. The high-resistance solder increases the impedance of the power-supply system in the entire circuit substrate.

For preparing a capacitor component by a green sheet method, the firing operation for forming a ceramic capacitor dielectric film from a green sheet is performed in an oxidizing atmosphere at a high temperature. Accordingly, capacitor electrodes and via-plugs of the capacitor component are formed of a heat-resistant metal, such as nickel. However, heat resistant metals have higher resistivity than copper used for LSI wiring or the like, and result in increased impedance.

In a capacitor element including a platinum capacitor electrode, the impedance of the element is increased because of the high resistivity of platinum. Also, ceramic dielectric films formed by sputtering, which are amorphous, are heat-treated to be crystallized. However, this heat treatment is likely to cause the dielectric film to crack, and consequently, leakage current can occur undesirably.

From the viewpoint of reducing the impedance, it is desirable that the electrode pattern and via-plugs in the capacitor component be formed of copper, which has low resistivity. However, copper has the melting point of 1084° C. while the firing of known green sheets is performed at a temperature of at least about 1500° C. It is therefore impossible to form an electrode pattern or via-plugs in a capacitor component having a structure in which ceramic dielectric films are disposed on top of one another by a known technique.

In the structure in which capacitor dielectric films are disposed on t of one another in a build-up substrate, the thickness of the entire capacitor becomes the same as the total thickness of the build-up layers. This structure requires longer via-connection and results in an increase in impedance. In addition, this structure increases the number of insulating layers of the circuit substrate, and accordingly increases the number of process steps. Consequently, the manufacturing cost is increased, and, further, the total thickness of the circuit substrate is increased to increase the impedance of the signal line. The capacitor dielectric films for respective build-up layers are formed by a low-temperature process such as sputtering so as to reduce and/or prevent damage to the build-up layers. However, the capacitor dielectric films formed at a low temperature are typically amorphous. Thus, even though a high dielectric material or a ferroelectric material that can originally achieve a high relative dielectric constant of 1000 or more is used, its relative dielectric constant is not more than about 40, and a satisfactory capacitor component cannot be achieved. A build-up substrate may be made of a composite material containing a resin and a high-dielectric ceramic. In this instance, however, the dielectric constant of the composite material is not more than about 50 due to the effect of the resin (typically, epoxy resin) having a low dielectric constant.

SUMMARY

According to an aspect of the embodiment, a method of manufacturing a capacitor is provided. In the method, a first ceramic film is formed on a first metal base, and a second ceramic film is formed on a second metal base. A first copper electrode pattern and a first copper via-plug are provided for a surface of one of the first and second ceramic films in such a manner that the electrode pattern and the via-plug are separate from each other. The first and second ceramic films are bonded together with the first electrode pattern therebetween by applying a pulsed voltage between the first base and the second base while the first base and the second base are pressed so that the first ceramic film and the second ceramic film are pressed on each other. Then, the second base is removed.

DESCRIPTION OF EMBODIMENTS

First Embodiment

FIG. 1is a sectional view of a capacitor element according to a first embodiment;

Referring toFIG. 1, a capacitor element10includes a base11and a stack of dielectric films12,14,16,18and20on the base11. The base11may be made of copper and have a thickness of 1 μm to 50 μm, preferably a thickness smaller than the thickness of a single build-up layer of a build-up circuit substrate, such as 16 μm. The dielectric films are made of, for example, barium titanate (BaTiO3) and have a thickness in the range of 0.3 μm to 5 μm, such as 1 μm. The dielectric films12,14,16,18and20are formed on top of one another by aerosol deposition, as will be described in detail. Each of the dielectric films12,14,16,18and20has been heat-treated at a temperature lower than the melting point of copper. Consequently, each dielectric film is fired, and thus has a granular structure having an average grain size in the range of 5 nm to 500 nm.

A copper layer13is disposed between the dielectric films12and14; a copper layer15is disposed between the dielectric films14and16; a copper layer17is disposed between the dielectric films16and18; a copper layer19is disposed between the dielectric films18and20; and an uppermost copper layer21is disposed on the dielectric film20. These copper layers are formed to a thickness of 200 nm to 500 nm by sputtering. As an alternative to sputtering, the copper layers13,15,17,19and21may be formed by electroplating or electroless plating. If the copper layers13,15,17,19and21are formed by sputtering, a titanium or chromium film of several tens of nanometers in thickness may be formed to enhance the adhesion between the copper layers and the underlying dielectric films, for example, between the copper layer13and the dielectric film12. However, if a recent advanced sputtering technique is applied, such an adhesion layer may be omitted, or is preferably omitted from the viewpoint of reducing resistance.

Copper layers are patterned into electrode patterns and via-plugs. For example, the copper layer13is patterned into electrode patterns13A and13B and a via-plug13C. The dielectric film14covering the copper layer13is7provided with openings14a,14band14cin which the electrode patterns13A and13B and the via-plug13C are exposed, respectively. The openings14a,14band14care filled with, for example, copper via-plugs14A,14B and14C, respectively. The copper via-plugs14A,14B and14C are formed by, for example, copper electroplating. The via-plugs14A,14B and14C may be formed of gold, platinum, tungsten, molybdenum, nickel, chromium, titanium, palladium, iron or the like.

The copper layer15is patterned into electrode patterns15A,15B and15C and via-plugs15D and15E. The dielectric film16covering the copper layer15is provided with copper via-plugs16A and16B corresponding to the via-plugs15D and15E, and with a copper via-plug16C corresponding to the electrode pattern15C.

The copper layer17is patterned into electrode patterns17A and17B and a via-plug17C. The dielectric film18covering the copper layer17is provided with copper via-plugs18A,18B and18C, corresponding to the electrode patterns17A and17B and the via-plug17C, respectively.

The copper layer19is patterned into electrode patterns19A,19B and19C and via-plugs19D and19E. The dielectric film20covering the copper layer19is provided with copper via-plugs20A and20B corresponding to the via-plugs19D and19E, and with a copper via-plug20C corresponding to the electrode pattern19C.

The copper layer21is patterned into electrode patterns21A,21B and21C, corresponding to the via-plugs20A to20C, respectively. These electrode patterns21A,21B and21C doubles as a connection wiring pattern on the top of the capacitor.

The dielectric film12is provided with copper via-plugs12A and12B therein, corresponding to the electrode patterns13A and13B, respectively.

In the capacitor element10shown inFIG. 1, the electrode patterns13A and17A are electrically connected to the base11and the electrode pattern21A through the via-plugs12A,14A,15D,16A,18A,19D and20A, and the electrode patterns15C and19C are electrically connected to the electrode pattern21C through the via-plugs13C,14C,16C,17C,18C and20C. Also, the electrode patterns13B and17B are electrically connected to the base11and the electrode pattern21B through the via-plugs12B,14B,15E,18B,19E and20B.

In this structure, the electrode patterns13A and13B oppose the electrode pattern15C with the dielectric film14therebetween, and these opposing electrode patterns define a capacitor therebetween. Similarly, the electrode patterns15C opposes the electrode patterns17A and17B with the dielectric film16therebetween, and these opposing electrode patterns define a capacitor therebetween. Also, the electrode patterns17A and17B oppose the electrode pattern19C with the dielectric film18therebetween, and these opposing electrode patterns define a capacitor therebetween.

Accordingly, when a ground voltage is applied to the base11or the electrode patterns21A and21B and a supply voltage is applied to the electrode pattern21C, for example, the above-described capacitors are connected in parallel between the supply voltage and the ground voltage, so that the capacitor element10can function as an effective decoupling capacitor. In this instance, the thicknesses of the dielectric films12to20are small as 0.3 μm to 5 μm. For example, if the thickness of each dielectric film is 1 μm, the total thickness of the multilayer structure of the five dielectric films12to20is not more than about 5 μm. Accordingly, the resistances and inductances of the current supply line including the via-plugs12A,14A,15D,16A,18A,19D and20A and the current supply line including the via-plugs13C,14C,16C,17C,18C and20C can be reduced.

Thus, the capacitor element10shown inFIG. 1can be formed at a total thickness of not more than about 20 μm, or less than 20 μm, in total including the substrate16. Accordingly, it can be embedded in a single build-up layer or at most several build-up layers of a circuit substrate on which semiconductor chips are to be mounted.

In the capacitor element10, the current line including the via-plugs12A,14A,15D,16A,18A,19D and20A and the current line including the via-plugs12B,14B,15E,18B and20B are connected to the base11. Therefore, when the capacitor element10is embedded in a circuit substrate, such as a build-up substrate, as will be described below, either the ground voltage or the supply voltage can be applied from the rear side of the circuit substrate at a minimum distance. Thus, the occurrence of parasitic inductance in the circuit substrate can be effectively reduced and/or prevented.

In the first embodiment, the material of the dielectric films12,14,16,18and20can be a material having a base composition such as PbZrTiO3, (Ba,Sr)TiO3, Ba(Zr,Ti)O3, KNbO3, K0.5Na0.5NbO3, KNbO3.NaNbO3.LiNbO3, (Bi1/2K1/2)TiO3, (Bi1/2Na1/2)TiO3, BiFeO3, (Sr,Ca)2NaNb5O15, (Sr,Ba)NbO6, Ba2(Na,K)Nb5O15, Bi4Ti3O12, SrBiTiTaOO3, SiBi2Ta2O9, SrBi2Nb2O9, (Sr,Ca)2Bi4Ti5O18, CaBi4Ti4O15, LiNbO3, LiTaO3or PbNb2O6, or a high dielectric oxide or a ferroelectric oxide, without being limited to BaTiO3.

A method of manufacturing the capacitor element10shown inFIG. 1will now be described with reference toFIGS. 2A to 2P.

Referring toFIG. 2A, a BaTiO3dielectric film12is formed to a thickness of, for example, 1.5 μm on a copper base11having a thickness of, for example, 16 μm, using an aerosol deposition apparatus160shown inFIGS. 4A to 4C.

The aerosol deposition apparatus160shown inFIG. 4Aincludes a work container161that is evacuated by a mechanical booster pump162and a vacuum pump162A through an evacuation channel133. In the work container161, a work substrate W is disposed on a stage161A so as to be displaceable in the X, Y, Z and θ axis directions with an X-Y-Z-θ driving mechanism132. The Z axis extends in the direction perpendicular to the surface of the stage161A, the X and Y axes extend in directions perpendicular to the Z axis, and are also perpendicular to each other. θ represents a rotation on the Z axis.

In the work container161, the work substrate W disposed on the stage161A is opposed to a nozzle161B to which aerosol of BaTiO3material powder is supplied with a dry carrier gas. The aerosol is sprayed as an aerosol jet161conto the surface of the work substrate W from the nozzle161c. In this instance, the aerosol jet161cdoes not contain solvent or any other liquid or a binder or any other organic material.

The BaTiO3powder in the aerosol sprayed on the work substrate W from the nozzle161B is a mixture of large particles having particle sizes in the range of 50 nm to 300 nm and nanoparticles having particle sizes in the range of 1 nm to 20 nm. These particles are formed by pulverizing a material powder having larger particle sizes by mutual collision in the nozzle161B, as schematically shown inFIG. 4B. The BaTiO3particles pulverized in the nozzle161B, which have very active surfaces formed by the pulverization, are solidified effectively on the surface of the work substrate W by impact, and thus a closely packed BaTiO3film having a high relative density of 90% or more is formed as a dielectric film12on the base11. In this state, the dielectric film12contains large grains12L having grain sizes in the range of 50 to 300 nm and nanograins12N having grain sizes in the range of 1 μm to 20 nm.

For forming a nozzle161B, in an example, a carrier pipe161V having a circular section and an inner diameter of 10 mm was provided with a nozzle open end portion161bthat had been formed by transforming a 10 mm long member into a shape having a length of 45 mm and a width gradually narrowed to 0.5 mm at the ejection face. The aerosol jet161cwas ejected through such a nozzle161B. An aerosol jet of an active mixture containing large particles having particle sizes in the range of 50 nm to 300 nm and nanoparticles having particle sizes in the range of 1 nm to 20 nm can be produced from, for example, a material powder containing larger particles, such as commercially available BaTiO3material powder having an average particle size of 100 nm to 800 nm, by the above-described pulverization.

Referring again toFIG. 4A, the aerosol deposition apparatus160has a material container163containing a BaTiO3material powder163afor supplying aerosol to the nozzle161B. By supplying a carrier gas, such as an inert gas or highly pure oxygen, to the material container163from a high-pressure gas source164through a line165and a mass flow controller164A, the aerosol is generated. The material container163shown inFIG. 4Ais held on a vibration table163A to promote the generation of the aerosol. When a valve163B communicating with the evacuation channel133is opened before the generation of aerosol, the water in the material was removed by the pumps162and162A.

More specifically, in the first embodiment, the material container163is charged with a commercially available BaTiO3material powder having an average particle size of 100 nm to 800 nm as the material163a. Ultrasonic vibration is applied to the entirety of the material container163by operating the vibration table163A. While the material powder is being heated at 150° C., the water absorbed in the surface of the material powder is removed by vacuum degassing with the valve163B open.

After the valve163B is closed, the pressure in the work container160is reduced to, for example, 10 Pa or less by operating the mechanical booster pump162and the vacuum pump162A, and highly pure oxygen gas having a pressure of, for example, 2 kg/cm2is supplied to the material container163at a flow rate of, for example, 4 L/min from the high-pressure gas source164through the gas line165and the mass flow controller164A. Thus, an aerosol of the BaTiO3material power is generated. The generated aerosol is supplied to the nozzle161B from the material container163whose inner pressure is kept constant at 200 Pa.

The aerosol jet is ejected to the work substrate W from the nozzle161B for, for example, 2 minutes. Thus, the dielectric film12is formed on the base11at a rate of, for example, 1 μm±0.5 μm/min, in the first embodiment.

FIG. 4Cshows transmission electron micrographs of a section of the boundary between the thus formed BaTiO3dielectric film12and the copper base11.

As shown in micrographs (a) and (b) inFIG. 4C, voids or any other defects were not observed in the boundary between the BaTiO3dielectric film12and the copper base11. Also, micrograph (c)-1, which is an enlargement of a part of the section of the BaTiO3dielectric film12, and micrograph (c)-2, which is a further enlargement of the enlarged portion shown in micrograph (c)-1, show that no void or no other defects are not observed in the BaTiO3dielectric film12. Micrographs (c)-1and (c)-2show that the BaTiO3film12is made of large grains of about 50 nm to 300 nm in diameter, having an average grain size of about 100 nm, and small grains of about 1 nm to 20 nm in diameter, having an average grain size of about 10 nm, and has a section as schematically shown inFIG. 4B.

In particular, micrograph (b) inFIG. 4Cshows that an interlocking layer having a thickness of about 500 nm in which copper and BaTiO3are interlocked with each other without forming a void is formed between the copper base11and the BaTiO3dielectric film12. Also, micrograph (e) inFIG. 4Cshows that an amorphous layer having a thickness of 1 nm or more is formed in the grain boundary of the adjacent crystal grains.

Furthermore, micrographs (c)-3and (e), which are respectively an enlargement of a part of micrograph (c)-2and an enlargement of a part of micrograph (c)-1, show that the lattice image of each BaTiO3crystal grain is observed.

A reciprocal lattice image was obtained from the lattice image by two-dimensional Fourier transform. As a result, the BaTiO3crystal has a (100) spacing of 0.401 nm, a (010) spacing of 0.382 nm, a (110) spacing of 0.279 nm, and an angle of 91.4° between the (100) plane and the (010) plane and an angle of 47.0° between the (100) plane and the (110) plane. Thus, it was confirmed that the BaTiO3crystal of the dielectric film is close to the ideal cubic BaTiO3crystal, which has a (100) spacing of 0.4031 nm, a (010) spacing of 0.4031 nm, and a (110) spacing of 0.2850 nm, and an angle of 90.0° between the (100) plane and the (010) plane and an angle of 45.0° between the (100) plane and the (110) plane.

Referring again toFIG. 2A, the BaTiO3dielectric film12formed as above is heat-treated at a temperature of less than 1084° C., which is the melting point of copper, for example, at 1000° C., to sinter the BaTiO3crystals in the dielectric film12. Although BaTiO3films are generally sintered at a temperature of 1500° C. or more, the BaTiO3film formed by aerosol deposition can be sintered at a temperature of about 1000° C. because of the very small nanograins12N contained in the BaTiO3film. Consequently, the crystal gains in the dielectric film12are grown by the sintering so that the fine structure of the BaTiO3film is changed into a granular structure having an average grain size in the range of 5 nm to 500 nm. Since the BaTiO3dielectric film12has a relative density of more than 90% in a state immediately after the aerosol deposition, it is hardly shrunk even by the sintering. Even if it shrinks about, for example, 0.5 μm in the thickness direction, shrinkage in the in-plane direction does not occur.

Turning now toFIG. 2B, via-holes12aand12bare formed in the dielectric film12, corresponding to the via-plugs12A and12B by a resist process using photolithography and subsequent dry etching. Alternatively, the via-holes12aand12bmay be formed by forming openings by a resist process, and by subjecting the portions of the openings to chemical etching using 5% hydrofluoric acid-nitric acid mixed solution. Then, copper shield films (not shown) are formed in the via-holes12aand12bby electroless plating, and electroplating is performed to fill the via-holes12aand12bwith copper to form the via-plugs12A and12B.FIG. 2Cshows a state where the undesired portions of the film formed by the electroless plating have been removed by wet etching after the formation of the via-plugs12A and12B. The copper base may be used as the shield layer to form the copper via-plugs in the via-holes.

In the first embodiment, at the same time as, or before or after the operations shown inFIGS. 2A to 2C, a second copper base41is prepared as shown inFIG. 2D, and via-holes14ato14care formed in a dielectric film14formed on the base41, corresponding to via-plugs14A to14D, as shown inFIG. 2E.

In the same manner as described with reference toFIG. 2C, via-plugs14A to14C are formed in the via-holes14ato14cas shown inFIG. 2F. The via-holes12aand12band14ato14cmay be formed by irradiation with a laser beam. In the method using a laser beam, when the underlying copper layer is exposed at the bottoms of the via-holes, the laser beam is reflected at the copper layer and the formation of the via-holes is automatically stopped. The via-holes and the via-plugs may be formed in the BaTiO3film heat-treated after aerosol deposition, or in the BaTiO3film immediately after the aerosol deposition without heat treatment.

The formation of the via-holes in the aerosol-deposited film may be performed immediately after the aerosol deposition, or after heat treatment. The via-holes can be formed by chemical etching using a hydrofluoric acid-nitric acid mixed solution, inductively coupled plasma (ICP) etching, reactive ion etching (RIE), ion milling, or dry etching using a laser beam, for example. In addition, a lift-off process may be applied in which a resist layer is formed before depositing a target material and is removed after the deposition.

A copper layer13is formed on the dielectric film14to a thickness of 200 nm to 500 nm by, for example, sputtering, as shown inFIG. 2G. As an alternative to sputtering, the copper layer13may be formed by electroless plating or electroplating.

For forming the copper layer13by sputtering, a titanium or chromium layer may be formed to several tens of nanometers as an adhesion layer on the dielectric film14before forming the copper layer13, as described above. However, such an adhesion layer is liable to increase the resistance, and is preferably omitted.

Subsequently, as shown inFIG. 2H, the copper layer13is patterned to form electrode patterns13A and13B and a via-plug13C on the via-plugs14A,14B and14C, respectively. Then, as shown inFIG. 2I, the structure including the base41and the layers formed on the base41is turned upside down and is, in this state, opposed to the structure shown inFIG. 2Cso as to align the electrode pattern13A and the via-plug14A with the via-plug12A and align the electrode pattern13B and the via-plug14B with the via-plug12B.

Then, as shown inFIG. 2J, the dielectric films12and14with the above alignment are bonded together with the copper electrode patterns13A and13B and via-plug13C therebetween. In this state, the dielectric film14is pressed on the dielectric film12in such a manner that the bases11and41are pressed at a pressure of 1 MPa to 50 MPa, such as 5 MPa, in the directions indicated by arrows shown inFIG. 2Jin an atmosphere of an inert gas, such as nitrogen, or in a vacuum with jigs51and52made of a heat-resistant metal, such as molybdenum, tungsten, titanium or their alloy, or graphite.

In this state, a pulsed voltage of, for example, 12 V is repeatedly applied so that a current of about 100 A to 1500 A flows between the jigs51and52from a high-power pulsed power supply53at a frequency of, for example, 1 kHz, and thus pulsed electric current bonding is performed, as shown inFIG. 2J. Either of the jigs51and52is provided with a thermocouple52A for measuring the temperature of the base11or41. The pulsed electric current bonding is performed for 30 minutes while the temperature of the base11or14measured with the thermocouple52A is being controlled to about 1000° C. As a result of the pulsed electric current bonding, the copper electrode patterns13A and13B are bonded to the corresponding via-plugs12A and12B and the BaTiO3dielectric film12, and the copper via-plug13C is bonded to the BaTiO3dielectric film12. Thus a structure shown inFIG. 2Kis prepared.

Although the portions surrounded by the broken lines inFIG. 2Khave had gaps in the state shown inFIG. 2J, it is observed that they are filled with the BaTiO3dielectric film14, and that the BaTiO3dielectric film12is bonded to the BaTiO3dielectric film14in a state where the boundary between the dielectric films12and14disappears. The reason of this is not clear at the current moment, but may be that a pulsed current flows along the grain boundaries in the dielectric films12and14by a mechanism similar to the mechanism in spark plasma sintering (SPS), and causes local melting, reaction or dispersion of the grain boundaries. Consequently, the BaTiO3grains may move so as to reduce the stress applied by the jigs51and52.

In the structure shown inFIG. 2K, the BaTiO3dielectric films12and14are firmly bonded to each other by the pulsed electric current bonding, with the copper electrode patterns13A and13B and via-plug13C therebetween.

After the base41has been removed to expose the surface of the dielectric film14, as shown inFIG. 2L, by wet etching, a copper layer15(seeFIG. 1) is formed over the surface of the dielectric film14, and is then patterned to form electrode patterns15A and15B opposing the electrode patterns13A and13B with the dielectric film14therebetween, an electrode pattern15C on the via-plug14C, and via-plugs15D and15E on the via-plugs14A and14B, as shown inFIG. 2M.

Through the operations shown inFIGS. 2A to 2M, a first capacitor structure of the capacitor element10is prepared.

A series of these operations is repeated to form another capacitor structure on the capacitor structure shown inFIG. 2M.

More specifically, as shown inFIG. 2N, a BaTiO3dielectric film16having via-plugs16A to16C is formed on the same base42as the base41in the same manner as the operations shown inFIGS. 2D to 2F, and the resulting structure is disposed upside down on the structure shown inFIG. 2M. Then, pulsed electric current bonding is performed under the same pressure as in the operation shown inFIG. 2J, and the base42is removed to yield the structure shown inFIG. 2Oby etching.

Then, as shown inFIG. 2P, electrode patterns17A and17B and a via-plug17C are formed respectively on the via-plugs16A,16B and16C in the dielectric film16. Thus, a second capacitor structure is formed on the capacitor structure shown inFIG. 2M.

By repeating the same operations, a desired number of layers can be formed in the capacitor element10.

The copper electrode patterns13A and13B and via-plug13C may be formed on the dielectric film12, instead of the dielectric film14, as is clear fromFIGS. 2I and 2J.

If the copper bases11and41are heat-treated at a temperature in the range of 300° C. to 600° C. before the aerosol deposition shown inFIG. 2Aor2D, the warp of the bases resulting caused by membrane stress or the degradation of their surfaces can be reduced and/or prevented. However if the heat treatment is performed at a temperature of less than 300° C., the base11or41is warped by the aerosol deposition. Consequently, the patterns may be misaligned when a multilayer structure like the capacitor element10shown inFIG. 1is formed. In contrast, if the heat treatment is performed at a temperature of more than 600° C., the strength of the bases11and41may be reduced, and their surfaces may become nonuniform. If the degree of the warp of the copper base11is so small as it is negligible in terms of pattern precision, the copper base11need not be heat treated from the viewpoint of cost reduction.

In the first embodiment, if the base41is made of copper, its thickness may be reduced instead of completely removing the base41by the operation shown inFIG. 2M, and the rest of the base41is then patterned into the electrode patterns15A to15C and the via-patterns15D and15E.

The via-plugs12A and12B may be omitted without being formed in the dielectric film12, as in the structure10M of a modification shown inFIG. 3A. In this instance, however, when the capacitor element10is mounted on a circuit substrate, one of the supply voltage and the ground voltage is applied to the electrode patterns21A and21B, and the other is applied to the electrode pattern21C.

Alternatively, the base11may be removed as in the structure10N of a modification shown inFIG. 3Bafter the capacitor10has been formed through the operations shown inFIGS. 2A to 2P. However, in the structure shown inFIG. 3B, the electrode patterns11A and11B are formed corresponding to the via-plugs12A and12B exposed at the surface of the dielectric film12by removal of the base11, and also the via-plug12C is formed corresponding to the via-plug13C. Furthermore, the electrode pattern11C is formed on the dielectric film12, corresponding to the via-plug12C.

In order to improve the state of the bonding interface, in the first embodiment, the dielectric film12may be provided with a layer made of a compound containing Li, Bi or Ge, such as LiF, Pb5Ge3O11, Bi2O3or Li2Bi2O5, at a thickness of about 100 nm as a sintering agent layer on the surface thereof before the bonding operation shown inFIG. 2J. Such a sintering agent layer is preferably formed in the spaces between each of the electrode patterns13A and13B and the via-plug13C, or between each of the electrode patterns15A to15C and each of the via-plugs15D and15E by aerosol deposition or sputtering, before the bonding operation shown inFIG. 2Ior2N. In this instance, it is preferable that the sintering agent deposited on the surfaces of the electrode patterns13A and13B and the via-plug13C, or the electrode patterns15A to15C and the via-plugs15D and15E be removed by polishing or the like before the bonding operation.

In the first embodiment, the dielectric films12,14,16,18and20each may be heat-treated every time aerosol deposition is performed as shown inFIG. 2Aor2D, and be bonded one by one by repeating SPS. Alternatively, the heat treatment may be performed by SPS when bonding is performed, instead of after the aerosol deposition. Many dielectric films heat-treated every their aerosol deposition may be stacked and then bonded at one time by SPS. Also, many films formed by aerosol deposition, but not heat-treated, may be prepared, and these films may be aligned and all the films are heat-treated by SPS so that the BaTiO3in each film can be sintered (or may be layered to form the structure of the complete capacitor element10and then heat-treated). In this instance, the heat treatment is performed only once, and thus the efficiency in manufacture is increased.

In the first embodiment, the above-described granular structure having an average grain size in the range of 5 nm to 500 nm is formed in the dielectric films12,14,16,18and20by heat treatment. In this granular structure, unlike the columnar structure often observed in ceramic films formed by sputtering when the ceramic film is heat-treated, the grain boundaries do not continue in a ceramic film from one side to the other, and current paths for leakage current along the grain boundaries are interrupted. Consequently, a highly reliable capacitor element can be obtained.

The number of layers of the multilayer structure is not particularly limited in the first embodiment, and a structure including 100 or more layers is possible.

A capacitor element as shown inFIG. 1was prepared by forming 20 to 50 BaTiO3dielectric layers corresponding to the dielectric films12to20on top of one another under the above-described conditions. As a result, it was confirmed that each dielectric film can be suitably and/or firmly bonded with the copper electrode patterns or via-plugs in contact therewith with no defect.

The relative dielectric constants of the dielectric films of the resulting capacitor element10were 1000 to 1500. The capacitance and the inductance of samples were also measured. The measured capacitances were as very high as 17 to 65 μF/cm2, and the inductances were as very low as 3 pH. This low inductance is owing to the use of copper in the electrode patterns and via-plugs. In the capacitor element of Example 1, via-plugs of 50 μm in diameter were formed at a pitch of 150 μm.

The resulting capacitor element10was mounted within a multilayer circuit substrate60, which will be described with reference toFIG. 6, by electroplating the via-plugs, but not using solder bumps. The impedance of the capacitor portion was measured at a frequency of 1 GHz, and the result was as very low as 0.1 mΩ. On the other hand, in a sample in which the same capacitor element was mounted in the same multilayer circuit substrate with solder bumps, the impedance was increased by 5 mΩ under the same conditions.

COMPARATIVE EXAMPLE 1

In Comparative Example 1, a capacitor element having the same structure as in Example 1 was prepared under the same conditions by hot press, instead of the pulsed electric current bonding as described with reference toFIG. 2J. However, in this instance, the dielectric films bonded together with copper electrode patterns or via-plugs therebetween were separated from each other, and thus, a stable capacitor element was not obtained.

COMPARATIVE EXAMPLE 2

In Comparative Example 2, a capacitor element having the same structure as in Example 1 was prepared under the same conditions by continuously applying a DC voltage, instead of performing the pulsed electric current bonding as described with reference toFIG. 2J. In Comparative Example 2 as well, the dielectric films bonded together with copper electrode patterns or via-plugs therebetween were separated from each other, and thus, a stable capacitor element was not obtained. This suggest that a current flows instantaneously along the grain boundaries in the dielectric films being bonded together at the pulse rise or fall during the pulsed electric current bonding described with reference toFIG. 2J, thereby bonding for example, the dielectric film12with the copper electrode patterns13A and13B or the dielectric film12with the via-plug13C.

COMPARATIVE EXAMPLE 3

In Comparative Example 3, a capacitor element having the same structure as in Example 1 was prepared under the same conditions except that the dielectric films were formed by aerosol deposition using BaTiO3particles having an average particle size of 10 μm in the material container163shown inFIG. 4A. In Comparative Example 3, the dielectric films bonded together with copper electrode patterns or via-plugs therebetween were separated from each other, and thus, a stable capacitor element was not obtained.

The result of Comparative Example 3 shows that, in the first embodiment, it is preferable that the material used for the aerosol deposition have an average particle size of less than 10 μm.

COMPARATIVE EXAMPLE 4

A capacitor element having a different structure, including 20 BaTiO3dielectric layers that had been formed on top of one another by a green sheet method was prepared. In the structure, the via-plugs of 100 μm in diameter were disposed at a pitch of 350 μm. As a result, each dielectric film had a thickness of 5 μm, and a very high relative dielectric constant of 3000. However, the capacitance was as low as 10 μF/cm2. The inductance of the entire capacitor element was 8 pH, and was thus considerably increased relative to that in Example 1. In Comparative Example 4, the electrode patterns were made of nickel, which is resistant to heat and has a high resistance.

COMPARATIVE EXAMPLE 5

BaTiO3dielectric films were formed by sputtering on a silicon substrate covered with a silicon oxide film, and thus a capacitor element having a different structure was prepared in which via-plugs having the same diameter as in Example 1 were disposed at the same pitch. In Comparative Example 5, the capacitor electrodes were made of platinum. In this capacitor element, since the dielectric films were formed by sputtering, the thickness of each dielectric film was not more than about 200 nm to 300 nm, and a crack occurred in some dielectric films by heat treatment for sintering (in the air or in an atmosphere of a gas containing oxygen). Accordingly, it was difficult to form a multilayer structure including many of these dielectric films, and the number of dielectric films was not more than three. The capacitance of the thus prepared capacitor was about 3.5 μF/cm2to 4.5 μF/cm2, and the relative dielectric constant of the dielectric films was not more than about 200 to 300. Also, the inductance of the capacitor was increased to 10 pH.

In Example 1, the pulsed electric current bonding described with reference toFIG. 2Jwas experimented using molybdenum or tungsten jigs as the jigs51and52. The resulting BaTiO3films13and14exhibited very high insulating resistances of 1012Ωcm. In Example 1, since dielectric films having such a very high insulation resistance were used in the capacitor element10shown inFIG. 1, leakage current in the capacitor element can be reduced effectively.

On the other hand, the pulsed electric current bonding described with reference toFIG. 2Jwas experimented using graphite jigs as the jigs51and52. The resulting BaTiO3films13and14exhibited low insulating resistances of 109Ωcm. This is probably because the graphite jigs consumed a trace amount of oxygen in the atmospheric gas to extremely reduce the oxygen partial pressure while the pulsed electric current bonding was performed in an inert gas atmosphere. Consequently, the oxygen atom in the dielectric film was removed through the atmospheric gas to produce a dielectric film having a non-stoichiometric composition expressed by the general formula BaTiO3-x.

Therefore, in the first embodiment, it is preferable that the pulsed electric current bonding shown inFIG. 2Jbe performed using jigs containing molybdenum and tungsten as the jigs51and52, but not denying the use of graphite jigs.

Second Embodiment

FIGS. 5A to 5Hare representations of a method of manufacturing the capacitor element10shown inFIG. 1, according to a second embodiment.

Referring toFIG. 5A, in the second embodiment, a BaTiO3dielectric film12is formed on a base11in the same manner as in the first embodiment, and copper electrode patterns13A and13B and a via-plug13C are formed on the dielectric film12. However, in the second embodiment, via-plugs12A and12B are not formed in the dielectric film12.

A BaTiO3dielectric film14is formed on the base41in the same manner as in the case of the first embodiment at the same time as, or before or after the operation shown inFIG. 5A. However, in the second embodiment, via-plugs14A to14C are not formed in the dielectric film14in the state shown inFIG. 5B.

The structure shown inFIG. 5Bis turned upside down as shown inFIG. 5C, and is disposed in such a manner that the dielectric film14opposes the electrode patterns13A and13B and the via-plug13C on the dielectric film12. Then, pulsed electric current bonding is performed as in the operation shown inFIG. 2Jwhile the bases11and14are being pressed on each other with jigs51and52, as shown inFIG. 5D. Thus the structure shown inFIG. 5Eis prepared.

After the base41is removed as shown inFIG. 5F, via-holes14ato14care formed in the dielectric film14corresponding to the electrode patterns13A and13B and the via-plug13C, respectively, and copper via-plugs14A to14C are formed in the via-holes14ato14c, respectively, as shown inFIG. 5G.

Further, as shown inFIG. 5H, electrode patterns15A to15C and via-plugs15D and15E are formed on the dielectric film14to form the same structure as the structure shown inFIG. 2M.

In the second embodiment, when the pulsed electric current bonding shown inFIG. 5Dis performed, conductor patterns passing through the structure between the bases11and41are not present. Accordingly, current does not concentrate to a specific current path, and power consumption can be reduced.

Third Embodiment

FIG. 6is a sectional view of a multilayer circuit substrate60in which the capacitor element10of the first embodiment is mounted in a resin multilayer structure including build-up layers61to65.FIG. 7is a sectional view of a semiconductor apparatus70including a semiconductor chip71that has been mounted on the multilayer circuit substrate60by flip-chip bonding.

InFIG. 6, many copper electrode pads65T1to65T7for connection with a semiconductor chip71are formed on the uppermost surface of the multilayer circuit substrate60, and external terminals61T1to61T9for connection with a wiring substrate are formed at the bottom or rear side of the multilayer circuit substrate60.

Each of the build-up layers61to65is typically made of an epoxy film containing silica particles or an epoxy resin film reinforced with glass cloth, and has a thickness of, for example, about 20 μm. Also, the build-up layers have a wiring structure through which the electrode pads65T1,65T2,65T6and65T7are electrically connected to the corresponding external connection terminals61T1and61T2and61T7to61T9. For example, the wiring structure may include the copper via-plugs61A and61B and61F to61H formed in the build-up layer61, the copper via-plugs62A to62C formed in the build-up layer62, the copper via-plugs63A and63B formed in the build-up layer63, the copper via-plugs64A and64B formed in the build-up layer64, the copper via-plugs65A,65C and65D formed in the build-up layer65, the copper wiring patterns61P1to61P3formed on the build-up layer61and covered with the build-up layer62, the copper wiring patterns62P1to62P3formed on the build-up layer62and covered with the build-up layer63, the wiring patterns63P1to63P3formed on the build-up layer63and covered with the build-up layer64, and the copper wiring patterns64P1to64P5formed on the build-up layer64covered with the build-up layer65.

For example, the external terminal61T2is electrically connected to the electrode terminal65T1through the via-plugs61B and62A, the wiring pattern62P1, the via-plug63A, the wiring pattern63P1, the via-plug64A, the wiring pattern64P1, and the via-plug65A. Also, the external terminal61T8is electrically connected to the electrode terminal65T7through the via-plugs61C and62C, the wiring pattern62P3, the via-plug63B, the wiring pattern63P3, the via-plug64B, the wiring pattern64P5, and the via-plug65D.

InFIG. 6, the via-plug10A in the capacitor element10represents a current path defined by the via-plugs12A,14A,15D,16A,18A,19D and20A, and is connected to the electrode pad65T3through a through-via plug VT1passing through the build-up layer65. The via-plug10B in the capacitor element10represents a current path defined by the via-plugs12B,14B,15E,16B,18B,19E and20B, and is connected to the electrode pad65T5through a through-via plug VT2passing through the build-up layer65. Thus, the electrode pads65T3and65T5have a ground voltage VGfrom which noise has been removed by the capacitor element10.

Also, the via-plug10C in the capacitor element10represents a current path defined by the via-plugs13C,14C,16C,17C,18C and20C, and is connected to the electrode pad65T4through the through-via plug VT3passing through the build-up layer65.

In the multilayer circuit substrate60, the external connection terminal61T3is a power supply terminal to which the supply voltage VVis applied, and to which the via-plug VT4passing through the build-up layers61to65is connected. The via-plug VT4is electrically connected to the wiring pattern63P2formed on the build-up layer63and covered with the build-up layer64. The wiring pattern63P2extends along the surface of the build-up layer63to be electrically connected to the through-via plug65T4. Thus, the electrode pad65T4has a supply voltage VVfrom which noise has been removed by the capacitor element10.

Fourth Embodiment

As shown inFIG. 7, a semiconductor chip71having electrode pads71A to71G is mounted on the uppermost surface of the multilayer circuit substrate60by flip chip bonding in such a manner that the electrode pads71A to71G come in contact with the corresponding electrode pads65T1to65T7with solder bumps72A to72G, respectively. Thus, a semiconductor apparatus70is produced in which a ground and a supply voltage VGand VVfrom which noise has been removed effectively can be applied to the semiconductor chip71.

The via-plugs61A,61B,61D to61H,62A to62C,63A,63B,64A,64B,65A to65D and the like can be formed by, for example, electroplating, and the wiring patterns61P1to61P3,62P1to62P3,63P1and63P3,64P1to64P4and the like can be formed by, for example, sputtering.

The external connection terminals61T4and61T6of the multilayer circuit substrate60, which are power-supply terminals to which a ground voltage VGis to be applied, are electrically connected to the base11of the capacitor element10with the respective via-plugs61D and61E.

FIGS. 8A and 8Bare sectional views illustrating a method of manufacturing the multilayer circuit substrate60shown inFIG. 6, particularly illustrating the operation for mounting the capacitor element10.

Referring toFIG. 8A, the wiring patterns63P1,63P2and63P3are formed on the build-up layer63, and the build-up layer64is formed on the build-up layer63so as to cover the wiring patterns63P1,63P2and63P3. InFIG. 8A, the portion under the build-up layer63is omitted.

The build-up layer64has an opening64Ap corresponding to the capacitor element10, and the capacitor element10is mounted on the build-up layer63in the opening64Ap as indicated by the arrow, and is bonded with an adhesive layer (not shown). Alternatively, the capacitor element10may be bonded to the surface of the build-up layer63in advance, and then the build-up layer64is formed on the build-up layer63.

Subsequently, the build-up layer65is formed on the build-up layer64together with wiring patterns and via-plugs to form the structure shown inFIG. 8B.

In the multilayer circuit substrate60, the through-via plugs VT1, VT2, VT3and VT4can be connected to the capacitor element10embedded in the build-up layer62by electroplating without using solder bumps. Accordingly, the occurrence of the parasitic resistance in the multilayer circuit substrate60can be suppressed to reduce the parasitic impedance.

FIG. 9is a sectional view of a modification of the circuit substrate shownFIG. 6. The same parts as described with reference toFIG. 6are designated by the same reference numerals, and thus description thereof is omitted.

The circuit substrate shown inFIG. 9includes a stack of build-up layers61to63, and in which the capacitor element10N of the modification described with reference toFIG. 3Bis mounted.

The capacitor element10N used in the structure shown inFIG. 9is produced by repeatedly forming many dielectric films and electrode patterns and via-plugs one on top of another, so that the thickness of the capacitor element10N can be substantially the same as the total thickness of the circuit substrate. Also, in addition to the via-plugs10A to10C, a via-plug10D similar to the via-plug10C is provided adjacent to the via-plug10B. Furthermore, electrode pads63T1to63T4are formed corresponding to the via-plugs10A to10D.

When such a circuit substrate is used in the same semiconductor apparatus as the circuit substrate shown inFIG. 7, the noise of the power supply system transmitted to the semiconductor chip71can be blocked effectively.