Method and system for reducing crosstalk in a backplane

A method and system for configuring the transmit and receive elements or structures in connector such that crosstalk can be reduced. The connector connects serdes modules in first PCB to serdes modules in one or more second PCBs via a backplane. The connector includes: first and second transmit connection positions in a first direction; first and second receive connection positions; and a ground shield positioned in the first direction between the first and second transmit connection positions and the first and second receive connection positions, wherein the first and second transmit connection positions do not have an interposing ground shield in another direction.

FIELD OF THE INVENTION

The present invention relates generally to backplanes and more specifically, transmitter and receiver connection arrangements in a high-speed serial backplane.

BACKGROUND

Serial backplanes have become popular for providing high-speed connections between printed circuit boards (PCBs). Typically, serial backplanes employ a serializer at a transmitting end to convert and transmit data in serial order, and a deserializer at a receiving end to convert the data back to parallel form once received. Such serializer/deserializer (“serdes”) modules have become the benchmark for asynchronous communication and have provided clear advantages over parallel busses.

FIG. 1is a diagram of two PCBs110and112connected together via a high-speed serial backplane114. Printed circuit board110includes a central processing unit (CPU)120connected to a random access memory (RAM)122and logic124. PCB board110also includes a serdes126connected to logic124. The CPU120, RAM122, logic124, and serdes126may be part of a programmable logic device (PLD), for example, a field programmable gate array (FPGA) such as Virtex II Pro™ from Xilinx Corp. of San Jose, Calif., which is attached to board110. Printed circuit board112includes circuitry similar to board110(and also may be part of a second FPGA), such as serdes140connected to logic142, which in turn is connected to CPU144and RAM146. Serdes126is connected to serdes140via high-speed serial backplane114. Serdes126transmits serial data over signal line132to the receiver at serdes140. Serdes140transmits serial data over signal line136to the receiver at serdes126. Connection points130,133,134, and137indicate were a connector may be used to connect the PCBs e.g., boards110and112, to backplane114.

The PCBs (normally called daughtercards), e.g., PCBs110and112, are affixed to circuit board connectors, which allow the PCBs to be electrically connected to the backplane114. Typically a series of circuit board connectors are spaced regularly along the length of the backplane. Multiple circuit layers of the backplane route the transmit and receive signals and power to the connectors and hence connect the PCBs to each other. Plated through holes electrically interconnect runs of different circuit layers as needed.

FIG. 2is a simplified side view of an example of a daughter card connector210and its associated backplane connector220of the prior art. This simplified view represents the GbX™ 4-Pair daughtercard signal module, i.e., a daughtercard connector, and backplane signal module, i.e., a backplane connector, of Teradyne Inc. of Boston, MA. A daughtercard212may be, for example, board110or board112ofFIG. 1. The daughtercard212is affixed to daughtercard connector210. Daughtercard connector210is plugged into backplane connector220. Backplane connector220has the pins, e.g., pins230,231,232,233,234,235,236, and237. Daughtercard connector210has an area214, which has the corresponding female structures to receive the pins.

Backplane connector220is affixed to backplane222(which is similar to backplane114ofFIG. 1). Backplane connector220includes an array of pins (e.g., 8×25).FIG. 2shows a sideview subset of eight pins, e.g.,230–237, and three ground shields240,242and244interposed between each pair of pins, e.g., pin pairs230/231,232/233,234/235, and236/237, respectively. The pin pairs, e.g.,230and231, may receive/transmit a differential signal, where, for example, pin230may be the positive(P) part and pin231may be the negative(N) part of the differential signal. For purposes of illustration, the pins230–237are part of a “column”, e.g., column310, in a connector pin assignment array as shown inFIG. 3. Each ground shield, e.g.,240,242or244, is made up of a metal plate and is connected to ground to provide shielding between the pin pairs.

FIG. 3shows a prior art connector pin assignment300for multiple serdes modules on a daughter card. The connector positions TXP320and TXN322indicate that the positive transmit signal (TXP) of a first serdes and the negative transmit signal (TXN) of the first serdes is assigned to pins230and231in a first column310and first row350. The connector positions RXP324and RXN326indicate that the positive receive signal (RXP) of the first serdes and the negative receive signal (RXN) of the first serdes is assigned to pins in row350and column312(not shown inFIG. 1). Similarly, the connector positions TXP330and TXN332indicate that the positive transmit signal (TXP) of a second serdes and the negative transmit signal (TXN) of the second serdes is assigned to row350and column314(not shown inFIG. 1). The connector positions RXP334and RXN336indicate that the positive receive signal (RXP) of the second serdes and the negative receive signal (RXN) of the second serdes is assigned to row350and column316(not shown inFIG. 1). In addition, the connector positions TXP340and TXN342indicate that the positive transmit signal (TXP) of a third serdes and the negative transmit signal (TXN) of the third serdes is assigned to pins232and233in column310and row352. The connector positions RXP344and RXN346indicate that the positive receive signal (RXP) of the third serdes and the negative receive signal (RXN) of the third serdes is assigned to other pins in a second row352and column312(not shown inFIG. 1). Connector positions TXP360and TXN362are assigned to pin positions of234and235inFIG. 1. Connector positions TXP364and TXN366are assigned to pin positions of236and237inFIG. 1.

The connector pin assignment300ofFIG. 3forms an array with columns310,312,314and316, and rows350,352,354, and356. In each element of the array, for example, column310and row350, is a differential pair, e.g., TXP320and TXN322, indicating a positive and negative portion of a differential signal. Ground shields, e.g.240,242, and244, are interposed between each row, e.g.,350/352,352/354, and354/356, respectively. The side view inFIG. 2of backplane220shows only the first column310and for the example of the GbX™ connector, there may be 25 columns of which only four columns are shown inFIG. 3.

As the speed of data transmission increases into the gigahertz range and beyond, near-end cross talk becomes a significant problem for connector pin assignments such as that ofFIG. 3. As the transmit signal, is relatively much larger than the receive signal, the transmit signal couples with the receive signal. For example, the differential transmit signal from TXP320and TXN322couples into the signal received by RXP324and RXN326and also the signal received by RXP334and RXN336. Since linear equalization circuits cannot typically distinguish a signal from the crosstalk, it is difficult to correct for the crosstalk using circuitry alone. In addition, the transmit circuits may have a transmit pre-emphasis which aggravates the crosstalk.

One prior technique used to reduce cross talk was to either completely shield the transmitters or the receivers. For example, inFIG. 3, TXP320and TXN322would have a ground shields on all four sides. Or, for example, RXP334and RXN336would have ground shields on all four sides. In effect there would not only be ground shields240,242, and244in the horizontal direction, but ground shields in the vertical direction (not shown) between columns310/312,312/314,314/316, and so forth. In the case of the GbX™ 4-Pair backplane signal module, there may be 25 columns. This is a difficult and expensive solution and is typically impractical to implement.

Therefore, an improved connector pin assignment is needed to reduce the crosstalk in a high-speed serial backplane, where the ground shields are substantially in only one direction.

SUMMARY

The present invention relates generally to a method and system for configuring the transmit and receive elements or structures in connector such that crosstalk can be reduced. The connector connects serdes modules in first PCB to serdes modules in one or more second PCBs via a backplane.

An embodiment of the present invention includes a connector for connecting a circuit board to a backplane. The connector includes: first and second transmit connection positions in a first direction; first and second receive connection positions; and a ground shield positioned in the first direction between the first and second transmit connection positions and the first and second receive connection positions, wherein the first and second transmit connection positions do not have an interposing ground shield in another direction.

Another embodiment of the present invention includes a connector to a serial backplane. The connector includes: first receive connection elements on the connector for at least two serializer/deserializer modules, wherein two of the first receive connection elements do not have a first interposing ground plane; second transmit connection elements for the at least two serializer/deserializer modules, wherein the second transmit connection elements are separated from the first receive connection elements by a second interposing ground plane. The connector may further include: third transmit connection elements for other serializer/deserializer modules, the third transmit connection elements positioned adjacent to the second transmit connection elements, wherein the third transmit connection elements are separated from the second transmit connection elements by a third interposing ground plane; and fourth receive connection elements for the other serializer/deserializer modules, where the fourth receive connection elements are positioned adjacent to the third transmit connection elements, wherein the fourth receive connection elements are separated from the third transmit connection elements by a fourth interposing ground plane.

Yet another embodiment of the present invention has a method for connecting serializer/deserializer modules to a backplane. The method includes a step of selecting transmit/receive pairs from the serializer/deserializer modules, where each transmit/receive pair has an associated transmit connection structure and an associated receive connection structure in a connector; and a step of configuring a ground structure between the associated transmit connection structures and the associated receive connection structures, wherein there is no interposing ground structure between the associated receive connection structures or the associated transmit connection structures.

The present invention will be more full understood in view of the following description and drawings.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention.

For serdes modules there is typically a transmit/receive pair of circuits, hence an associated pair of transmit/receive connection elements or structures. In one embodiment of the present invention, the transmit connection elements (or structures) and receive connection elements (or structures) may be pairs of pins indicated by differential pin assignments TXP/TXN and RXP/RXN, respectively. In another embodiment the transmit/receive connection elements or structures may be the corresponding female elements or structures to receive the pairs of pins. In other embodiments rather that differential signals, the signals may be single-ended, e.g., only one pin rather than a pair of pins, and while the following description of the preferred embodiment is for a differential signal, it should be understood that single-ended signals and a mixture of differential and single-ended signals are also included in the scope of the present invention.

FromFIG. 3, one of the reasons there is crosstalk is that there is a mixture of receive connection positions and transmit connection positions in a single row. A preferred embodiment of the present invention has all transmit differential pairs (TXP/TXN) on a first row and the corresponding serdes receive differential pairs (RXP/RXN) on a second row (which may be adjacent to the first row), where the first row and second row are separated by a ground plane or structure, such as a ground shield ofFIG. 1. In the preferred embodiment the ground shields are configured in the backplane connector220ofFIG. 2. In an alternative embodiment the ground shields are configured in the daughtercard connector210.

FIG. 4is a partial connector pin assignment400of a preferred embodiment of the present invention. The complete connector assignment in the preferred embodiment includes four rows and 25 columns.FIG. 4shows four columns410,412,414, and416and four rows450,452,454, and456. The ground planes or structures, for example, ground shields240,242and244(fromFIG. 1) separate each row.FIG. 4is similar toFIG. 3, except the connector pin positions have been reassigned so that each row has only differential receive pin pair connection positions (RXP/RXN) or differential transmit pin pair connection positions (TXP/TXN). The labels for the differential pin pair connection positions inFIG. 4have been maintained fromFIG. 3to show how the pin pair connection positions have been moved.

For example TXP320and TXN322which was in row350and column310ofFIG. 3has been moved to row452and column410ofFIG. 4. The associated serdes differential receive pair RXP324and RXN326located in row350and column312ofFIG. 3has been moved to row450and column410ofFIG. 4. TPX340and TXN342in row352and column310has been moved to row452and column412. RXP344and RXN346in row352and column312has been moved to row450and column412. TPX330and TXN332in row350and column314have been moved to row452and column414. RXP334and RXN336in row350and column316has been moved to row450and column414. HenceFIG. 4illustrates a row450of receive connection positions adjacent to a row452of transmit connection positions, where there is an interposing ground shield240between rows. The row452is adjacent to row454of transmit connection positions, where there is an interposing ground shield242between rows. The row454is adjacent to a row456of receive connection positions, where there is an interposing ground shield244between rows. Hence, crosstalk is significantly reduced because the transmit connection positions are shielded from the receiver connection positions.

FIG. 4shows a row450of receive connection positions (abbreviated by “RX1” for discussion purposes). A row452of transmit connection positions (abbreviated by “TX1” for discussion purposes). A row454of transmit connection positions (abbreviated by “TX2” for discussion purposes). And a row456of receive connection positions (abbreviated by “RX2” for discussion purposes). In other words a partial connector pin assignment of [RX1, TX1, TX2, RX2]. Other permutations of partial connector pin assignments are [RX1, TX1, RX2, TX2][TX1, RX1, TX2, RX2] and [TX1, RX1, RX2, TX2].

With reference toFIGS. 2 and 4, the pins230–237are reassigned to new values as given in column410. RXP324and RXN326are assigned to pins230and231. TXP320and TXN322are assigned to pins232and233. TXP360and TXN362are assigned to pins234and235. RXP370and RXN372are assigned to pins236and237.

FIG. 5is a diagram of some of the connections between two board connectors of an aspect of the present invention. The first board connector includes connector pin assignment400and the second board connector includes connector pin assignment500. Connector pin assignment400was shown inFIG. 4. Connector pin assignment500is similar to connector pin assignment400. Connector pin assignment500has four rows550,552,554, and556, where there are interposing ground shields502,504, and506between each row. Although, only four columns510,512,514, and516are shown, there may be 25 columns. Each element in each column of connector pin assignment400, e.g.,410,412,414, and416, is connected to an associated element in the associated column, e.g.,510,512,514, and516, respectively, in connector pin assignment500. For clarity of illustration only one differential connector pin pair position is shown for a row on400, e.g., RXP/RXN in column416of row450is connected to TXP/TXN in column516and row552. However, the other differential connector pin pair positions in the row on400, e.g. row450, are similarly connected to the associated differential connector pin pair positions in the row in500, e.g., row552. TXP/TXN in row452and column414is connected to RXP/RXN in column514and row550. TXP/TXN in row454and column412is connected to RXP/RXN in column512and row556. RXP/RXN in row456and column410is connected to TXP/TXN in column510and row554.

In the preferred embodiment each row in400is connected to its associated row in500on a different backplane layer. For example, RXP/RXN in row450and column416is connected to TXP/TXN in row552and column516via a first layer of the backplane. TXP/TXN in row452and column414is connected to RXP/RXN in column514and row550via a second layer of the backplane. TXP/TXN in row454and column412is connected to RXP/RXN in column512and row556via a third layer of the backplane. RXP/RXN in row456and column410is connected to TXP/TXN in column510and row554via a fourth layer of the backplane. Using different signal layers of the backplane, where there is an interposing ground layer between each signal layer in the backplane, reduces cross talk between signal wires (see U.S. Pat. No. 5,397,861, titled “Electrical Interconnection Board”, by David H. Urquhart, issued Mar. 14, 1995, which is incorporated by reference, herein).

Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to one of ordinary skill in the art. For example, although only one processor is shown on FPGA100, it is understood that more than one processor may be present in other embodiments. Thus, the invention is limited only by the following claims.