Efficient high-voltage digital I/O protection

A circuit to protect a digital input and output (I/O) terminal from an overvoltage applied externally to the digital I/O terminal. The circuit is arranged similar to a bootstrap switch such that a pass-device protects an output driver from an overvoltage applied to the digital I/O terminal and the output driver controls the operation of the pass-device, such as an N-channel metal-oxide semiconductor (NMOS) transistor. The circuit may include a capacitor and a diode coupled to the gate of the NMOS transistor. A digital zero from the output driver charges the capacitor. A digital one from the output driver causes the charged capacitor, coupled between source and the gate of the NMOS transistor, provides sufficient gate-source voltage to pass the digital one from the driver to the digital I/O terminal. The circuit further includes refresh circuitry configured to maintains the gate source voltage on the capacitor.

TECHNICAL FIELD

The disclosure relates to overvoltage protection of digital circuits.

BACKGROUND

Digital circuits may operate in an environment where a digital output terminal can be subjected to a voltage high enough to damage the digital circuit, for example, a high voltage caused by a fault or transient voltage in the system that may be applied to the digital output terminal. To protect the digital circuitry, a digital circuit may drive the digital output terminal with an output driver that may be resistant to damage from an overvoltage at the digital output terminal. Output drivers that are resistant to overvoltage damage may have a disadvantage in that the driver may occupy a relatively large area on an integrated circuit (IC) and may have slower operating speeds when compared to lower voltage output drivers that are less resistant to overvoltage. In other examples, an overvoltage resistant pass device, such as a transistor, may protect a lower voltage output driver from an overvoltage at the digital output terminal.

SUMMARY

In general, the disclosure is directed to circuits configured to protect a digital input and output (I/O) terminal from an overvoltage applied externally to the digital I/O terminal. The circuits may be arranged to include circuitry similar to a bootstrap switch such that a pass-device protects the output driver from a possible overvoltage applied to the digital I/O terminal and the output driver controls the operation of the pass-device. In one example, the pass-device is an N-channel metal-oxide semiconductor (NMOS) transistor. The circuit may include a capacitor and a diode coupled to the gate of the NMOS transistor. A digital zero from the output driver to the output terminal, may charge the capacitor. When the output driver sends a digital one to the output terminal, the charged capacitor, coupled between source and the gate of the NMOS transistor, is configured to provide sufficient gate-source voltage to pass the digital one from the driver to the digital I/O terminal. The circuits may further include refresh circuitry, configured to maintain the gate source voltage on the capacitor.

In one example, the disclosure is directed to a circuit comprising: a driver circuit comprising an input element and an output element, wherein the output element is electrically coupled to a digital output terminal via a pass-device. The pass-device comprises a first terminal, a second terminal and a control terminal, the pass-device is configured to protect the driver circuit from an overvoltage applied to the digital output terminal, the output element of the driver circuit is electrically connected both to the first terminal of the pass-device and via a capacitor to the control terminal of the pass-device, the control terminal of the pass-device is coupled to a supply voltage through a switch, and the second terminal of the pass-device is coupled to the digital output terminal.

In another example, the disclosure is directed to a method comprising: in response to receiving a digital zero at an input element of a driver circuit, charging a capacitor such that the magnitude of voltage across the capacitor is approximately first supply voltage, wherein the capacitor is coupled to the first supply voltage through a switch, and wherein the capacitor is connected between a gate and a source of an N-channel metal-oxide semiconductor (NMOS) pass-device. In response to receiving a digital one at the input element of the driver circuit, applying, by the driver circuit, a second voltage to the source of the NMOS pass-device such that the gate-source voltage of the NMOS pass-device is approximately the magnitude of voltage across the capacitor.

DETAILED DESCRIPTION

The disclosure is directed to a circuit configured to protect a digital input and output (I/O) terminal from an overvoltage applied externally to the digital I/O terminal. The circuit protects the digital I/O terminal with a pass-device that protects the output driver for the digital I/O terminal from a possible overvoltage applied to the digital I/O terminal. The circuit may be arranged similar to a bootstrap switch, but unlike other examples of protection circuits, the output driver may control the operation of the pass-device rather than additional circuitry, such as a charge pump.

In some examples, the pass-device may comprise an N-channel metal-oxide semiconductor (NMOS) transistor. The circuit may include a capacitor and a diode coupled to the gate of the NMOS transistor. A digital zero from the output driver to the output terminal, charges the capacitor. When the output driver sends a digital one to the output terminal, the charged capacitor, coupled between source and the gate of the NMOS transistor, is configured to provide sufficient gate-source voltage to the NMOS transistor to pass the digital one from the driver to the digital I/O terminal.

In some examples, components in the circuit may be subject to leakage, such as when the digital I/O terminal outputs a digital one for an extended period. Some examples of leakage sources may include gate leakage for the NMOS transistor, leakage across the capacitor, and so on. To counter these or other types of leakage, the circuit may further include refresh circuitry, which maintains the gate source voltage across the capacitor to ensure the pass-device remains ON while outputting a digital one.

FIG. 1is a block diagram illustrating a digital I/O terminal with output driver protection circuitry, according to one or more techniques of this disclosure. Circuit100may be implemented in many different types of circuits in which a digital output terminal provides a digital output signal to one or more other components in a system.

In the example ofFIG. 1, circuit100includes driver circuit102, which is electrically coupled to digital output terminal106through pass-device112. Bootstrap circuitry110includes capacitor C1114and diode D1116, which connects a control terminal134of pass-device112to Vdd. Capacitor C1114connects output element132of driver circuit102to control terminal134. In the example ofFIG. 1, output element132of driver circuit102is electrically connected directly to an input terminal of pass-device112.

Refresh circuit120receives signals from input element104and includes an output element, refresh output element130, which is coupled to the control terminal134of pass-device112. Refresh circuit120also includes clock input element122.

Driver circuit102may comprise a digital output driver that receives digital signals at input element104and outputs a buffered digital signal at output element132. In some examples, the digital signals to input element104may come from digital circuitry on the same IC as circuit100. Driver circuit102may also be connected to digital supply voltage VDDIOand reference voltage Vss. In the example ofFIG. 1, VDDIOis approximately 5V and reference voltage Vss is approximately zero volts. A digital zero received at input element104may cause driver circuit102to output a digital zero at output element132, i.e. approximately zero volts. Similarly, a digital one at input element104may cause driver circuit102to output a digital one at output element132, i.e. approximately VDDIO.

Bootstrap circuitry110functions using principles similar to a bootstrap switch circuit, which is a type of circuit that may be used to drive the gate voltage on a high side switch to cause a gate voltage higher than the power supply rail. However, unlike a typical bootstrap switch circuit, in the example of circuit100, the anode of diode D1116is connected to Vdd, while the cathode connects to control terminal134and to one terminal of capacitor C1114.

In operation, when circuit100receives a digital zero at input element104, driver circuit102outputs a digital zero at output element132, causing capacitor C1114to charge to approximately Vdd. In other words, driver circuit102is configured to output reference voltage Vss to a first plate of capacitor C1114, which causes a second plate of capacitor C1114coupled to the cathode of D1116to charge to approximately a magnitude of the supply voltage, Vdd. The voltage across C1114becomes Vdd, minus the voltage drop across D1116and minus any further voltage drop between output element132and reference voltage Vss. In the example ofFIG. 1, Vss is zero volts. In the example ofFIG. 1, Vdd is approximately half the magnitude of VDDIO. In the example ofFIG. 1, VDDIOis approximately 5V and Vdd is approximately 2V5. In other examples Vdd and VDDIOmay be set to different voltage magnitudes, such as VDDIO=3.3V. In other examples, Vdd may be set to a magnitude different from half of VDDIO.

When circuit100receives a digital one at input element104, driver circuit102outputs a digital one at output element132, which in the example ofFIG. 1is approximately VDDIOless any voltage drop between VDDIOand output element132. Capacitor C1114may retain the voltage between the first plate and the second plate of capacitor C1114, and therefore the magnitude of voltage between the input terminal of pass-device112and control terminal134remains approximately Vdd, to ensure pass-device112allows the digital one from driver circuit102to be output from digital output terminal106. In the example in which pass-device112is an NMOS transistor, capacitor C1114may provide sufficient gate-source voltage (Vgs) to keep the NMOS transistor turned ON. In the example of an insulated gate bipolar transistor (IGBT), capacitor C1114may provide sufficient gate voltage to ensure the IGBT remains ON. Note that the terms “first plate” and “second plate” are used to simplify the explanation of bootstrap circuitry110as shown inFIG. 1. An actual capacitor may be constructed using multiple layers of plates and dielectric material. Also, in this disclosure the first plate may be described as being connected to a first terminal or first element of capacitor C1114. Similarly, the second plate may be described as being connected to a second terminal or second element of capacitor C1114.

In some examples, diode D1116may operate as a switch because D1116may be ON when the voltage at control terminal134is less than Vdd. When the voltage at control terminal134is more than Vdd, D1116will prevent current from flowing from control terminal134to Vdd. Therefore, when the voltage at control terminal134is greater than Vdd, then diode D1116may be considered as a switch that is OFF.

Refresh output element130of refresh circuit120connects to control terminal134. In operation, when circuit100receives a digital one at input element104, enable input element136of activates refresh circuit120to apply a predetermined voltage amplitude at control terminal134of pass-device112. Refresh circuit120is configured to periodically apply the predetermined magnitude of voltage at the gate of the pass-device based on a clock signal received at clock input element122to counter any leakage in bootstrap circuitry110, such as at capacitor C1114. The circuit arrangement of circuit100may provide an advantage in reduced current consumption, when compared to other techniques.

FIG. 2is a schematic diagram illustrating a digital I/O terminal with an example implementation of a refresh circuit, according to one or more techniques of this disclosure. Circuit200is an example of circuit100described above in relation toFIG. 1.

The pass-device in the example of circuit200is high-voltage NMOS transistor M1212with the drain of transistor M1212connected to digital output terminal206. NMOS transistor M1212may provide improved efficiency when compared to other types of pass-devices because of low on-resistance (RDS-ON), for an N-channel MOSFET. Also, for the same on-resistance, an N-channel MOSFET may be lower cost compared with a P-channel MOSFET, e.g., an N-channel MOSFET may require a smaller die footprint on an IC compared to a P-channel MOSFET. However, turning an N-channel MOSFET completely ON requires a high enough VGSto minimize RDS-ON. and avoid losses, such as heat loss, that may reduce efficiency.

As described above in relation toFIG. 1, bootstrap circuitry210may provide a gate-source voltage to ensure transistor M1212remains ON when driver circuit202outputs a digital one (with a magnitude of approximately VDDIO) at output element232.

Therefore, when driver circuit202outputs a digital zero, transistor M1212has a VGSequal to Vdd−Vdiode1, where Vdiode1 is the diode drop of D1216. If input element204receives a logic ‘1,’ then driver circuitry202outputs VDDIO(e.g. 5V) and the gate-source voltage VGSof transistor M1212will be:

VG⁢S=(VD⁢D-Vd⁢i⁢o⁢d⁢e⁢1)-(Cg(C⁢1+Cg)×VDDIO)
where, Cg represents the total parasitic capacitance seen at the gate234of transistor M1212. The capacitance value, i.e. size, of C1214should be selected such that the capacitance of C1214is high enough to limit the voltage drop caused by the parasitic capacitance of NMOS transistor M1212, which may be affected by any parasitic gate current and non-ideal (i.e. finite) internal resistance at the gate of transistor M1212.

Capacitor C1214, and other components of bootstrap circuitry220may allow current leakage when circuit200holds a digital one for an extended period of time. Refresh circuitry220is one example implementation of a refresh circuit to configured to apply a predetermined voltage amplitude at the control terminal of the pass-device, transistor M1212to counter any leakage. The predetermined voltage amplitude may provide a sufficient gate-source voltage at gate234to ensure transistor M1212stays turned ON fully while driver circuit202outputs a digital one. Refresh circuit220includes AND gate224, auxiliary driver circuit226, capacitor C2228, diodes D2236and D3238. Enable input236connects to one input element of AND gate224and clock input element222connects to the second input element of AND gate224. The output of AND gate224connects to the input of auxiliary driver circuit226. Capacitor C2228connects the output of auxiliary driver226to the cathode of diode D2236and to the anode of diode D3238. The cathode of diode D3234is refresh output230, which connects to gate234. Refresh output230is an example of refresh output130described above in relation toFIG. 1.

Similar to driver circuit202and driver circuit102, described above in relation toFIG. 1, auxiliary circuit226is connected to power supply VDDIOand reference voltage Vss. Therefore, auxiliary circuit226will output a digital zero, i.e. approximately zero volts, when auxiliary circuit226receives a digital zero from AND gate224. Similarly, auxiliary circuit226will output a digital one, i.e. approximately VDDIO, when auxiliary circuit226receives a digital one from AND gate224.

In operation, a digital one received by circuit200at input element204will enable a clock signal received at clock input element222to pass through AND gate224to auxiliary driver226. When the clock signal is a logical low, i.e. a digital zero, capacitor C2228charges to approximately Vdd. Similar to the charging of capacitor C1114described above in relation toFIG. 1, auxiliary driver circuit226is configured to tie reference voltage Vss to a first plate of capacitor C2228, which causes a second plate of the capacitor coupled to the cathode of D2236to charge to approximately a magnitude of the supply voltage, Vdd. The voltage across C2228will be Vdd, minus the voltage drop across D2236and minus any further voltage drop between auxiliary driver circuit226and reference voltage Vss.

When the clock signal is a logical one, refresh output230will couple a voltage to gate234, via diode D3238with a magnitude of approximately Vdd+VDDIO−Vdiode3. The magnitude of voltage applied to gate234may be an example of the predetermined magnitude of voltage applied to control terminal134, described above in relation toFIG. 1.

Because auxiliary driver circuitry226in the arrangement of circuit200is not required to drive a high current, auxiliary driver circuitry226may be much smaller than the main driver, i.e. driver circuitry202. Therefore, the example of circuit200may provide an advantage in lower cost, reduced IC footprint and reduced current consumption when compared to other techniques. Also, the frequency of the clock signal applied to clock input element222may be a fairly low frequency when compared to other techniques. A lower frequency clock signal may also reduce cost, cause less interference and reduce current consumption when compared to other techniques. The selected frequency for the clock input to clock input element222may depend on the arrangement and selection of components for circuit200, the capacity, the size of the NMOS, or other switch used as the pass-device, as well as the type of technology used to implement circuit200.

FIG. 3is a timing diagram depicting an example operation of refresh circuit120and refresh circuit220described above in relation toFIGS. 1 and 2. InFIG. 3, before the signal received at input element304is a digital one (342) the clock signal322is disabled, as indicated by refresh output330with a magnitude of Vdd. When the signal at input element304transitions to a digital 1 (342), clock signal322may be applied to auxiliary driver circuitry226through AND gate224, as described above in relation toFIG. 2. Refresh output330applies a voltage with magnitude of approximately Vdd+VDDIOto the control terminal of the pass-device, e.g. gate234of transistor M1212depicted inFIG. 2. As described above in relation toFIG. 2, the voltage applied to the control terminal may be reduced by a voltage drop, such as the voltage drop, Vdiode3, across diode D3238.

The voltage at the control terminal may decay somewhat (344) based on the amount of leakage which may be present at the control terminal. Refresh output330periodically apply the predetermined magnitude of voltage of approximately Vdd+VDDIOto the control terminal of the pass-device when clock signal322is a digital one. Applying the predetermined magnitude of voltage may maintains the gate source voltage across the capacitor to ensure the pass-device remains ON while the circuit is outputting a digital one at a digital output terminal, such as digital output terminal106described above in relation toFIG. 1. When the signal received at the input element304is a digital zero (346), the refresh circuit is disabled and refresh output330returns to a magnitude of Vdd.

FIG. 4Ais a schematic diagram illustrating an example digital I/O protection circuit with overvoltage monitoring according to one or more techniques of this disclosure. Circuit400A is another example of circuit100and circuit200described above in relation toFIGS. 1 and 2. Items depicted inFIG. 4A, such as driver circuitry402, auxiliary driver circuitry426, AND gate424, input element404, clock input terminal422, Vdd, VDDIO446, reference voltage Vss, and digital output terminal406may have the same or similar characteristics as, respectively, driver circuitry102, auxiliary driver circuitry226, AND gate224, input element104, clock input terminal122, Vdd, VDDIO, reference voltage Vss, and digital output terminal106described above in relation toFIGS. 1 and 2.

Similar to circuit100, circuit400A includes a pass-device, transistor Mpass412, to protect driver circuitry402from an overvoltage event at digital output terminal406as well as bootstrap circuitry to ensure that Mpass412stays ON when circuit400A receives a digital one at input element404. In the example of circuit400A, pass-device Mpass412is an NMOS transistor with the source connected to the output of driver circuitry402and the drain connected to digital output terminal406.

The bootstrap circuitry of circuit400A includes capacitor C1414connected between the source and gate of Mpass412and NMOS transistor MN0416, which is a switch that connects the control terminal of pass-device Mpass412to supply voltage Vdd. Transistor MN0416performs a function similar to diode D1116described above in relation toFIG. 1. The drain of MN0416connects to the gate of Mpass412and the gate of MN0416is controlled by the enable signal EN452from comparison circuitry450A.

The bootstrap circuitry also includes pull-down transistors MP0460and MN1470, which are controlled by the pull-down signal PD454from comparison circuitry450A. Transistor MP0460may comprise a PMOS transistor with the source connected to supply voltage Vdd and the drain connected to the source of MN0416. MN1470is an NMOS transistor with the drain connected to the gate of Mpass412and the source connected to reference voltage Vss. In operation, when MP0460receives a pull-down signal from comparison circuitry450A via PD454, i.e. a logical HIGH, MP0460may turn OFF and isolate Vdd from MN0416and the gate of Mpass412. When MN1470receives the pull-down signal via PD454, MN1470may turn ON, which connects the gate of Mpass412to Vss and ensures Mpass12turns OFF to isolate driver circuitry402from digital output terminal406.

The refresh circuitry of circuit400A may be similar to refresh circuit220described above in relation toFIG. 2. The refresh circuitry of circuit400A includes clock input element422, connected to one of the two input terminals of AND gate424. Input element404connects to the second input terminal of AND gate424. The output of AND gate424connects to the input of auxiliary driver circuit426. A first terminal of capacitor C2428connects the output of auxiliary driver circuit426. A second terminal of capacitor C2428connects to the drain of transistor MN2436and to the source and gate of transistor MN4438. Transistor MN2436is controlled by the enable signal EN452from comparison circuitry450A and performs a function similar to that of diode D2236described above in relation toFIG. 2. Transistor MN4438is a diode connected transistor and performs a function similar to the function of diode D3238described above in relation toFIG. 2. The drain of transistor MN4238connects to the gate of Mpass412, as well as to comparison circuitry450A.

The refresh circuitry also includes pull-down transistors MP1464and MN3472, which are controlled by the pull-down signal PD454from comparison circuitry450A, which function similar to pull-down transistors MP0460and MN1470described above. Transistor MP1464is a PMOS transistor with the source connected to supply voltage Vdd and the drain connected to the source of MN2466. MN3472is an NMOS transistor with the drain connected to the drain of MN2466and the source connected to reference voltage Vss. In operation, when MP1464receives a pull-down signal from comparison circuitry450A via PD454, MP1464may turn OFF and isolate Vdd from MN2466.

When MN3472receives the pull-down signal via PD454, MN3472may turn ON, which connects the second terminal of capacitor C2428to Vss, which prevents the refresh output signal from turning on Mpass412via diode connected transistor MN4438.

Similar to circuits100and200described above in relation toFIGS. 1 and 2, in operation, when circuit400A receives a digital zero at input element404, driver circuit402outputs a digital zero causing capacitor C1414to charge to approximately Vdd. In other words, driver circuit402is configured to output reference voltage Vss to a first terminal of capacitor C1414, which causes a second plate of the capacitor coupled to the supply voltage Vdd via MN0416and MP0460, to charge to approximately a magnitude of the supply voltage, Vdd.

In the example of circuit400A, comparison circuitry450A is configured to output the enable signal, i.e. a logical HIGH, via EN452to turn ON transistor MN0416when magnitude of voltage at digital output terminal406is less than the magnitude of voltage at the gate of Mpass412. Comparison circuit450A is configured to output a logical LOW via pull-down PD454when comparison circuit450A determines that there is no overvoltage at digital output terminal406. The enable signal EN452and pull-down signal PD454may be configured to be complementary to each other. That is, when EN452is high, PD454is low and vice versa.

Comparison circuit450A may be implemented by any combination of hardware, firmware or software, such as an application specific integrated circuit (ASIC), a microcontroller, or any other type of processing circuitry. In some examples, comparison circuit450A may include one or more processors, one or more analog-to-digital converters (ADC) and similar circuitry. If implemented in software, the functions may be stored on a tangible computer-readable storage medium and executed by a processor or hardware-based processing unit. Instructions may be executed by the one or more processors, such as one or more DSPs, general purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor,” as used herein, such as may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques could be fully implemented in one or more circuits or logic elements.

When circuit400A receives a digital one at input element404, driver circuit402outputs a digital one which in the example ofFIG. 4Ais approximately VDDIO. Capacitor C1414may retain the voltage between the first plate and the second plate of capacitor C1414, and therefore the magnitude of voltage between the source and the gate VGSof pass-device Mpass412remains approximately Vdd. The VGSwith a magnitude of Vdd may ensure that Mpass412remains ON and allows the digital one from driver circuit402to be output from digital output terminal406.

As described above in relation toFIGS. 1 and 2, the refresh circuitry of circuit400A is configured to periodically apply a predetermined voltage to the control terminal, i.e. the gate of Mpass412to counter any leakage in the bootstrap circuitry, such as at capacitor C1414. The a digital one at input element404, enables a clock signal received at clock input element422to pass through AND gate424to auxiliary driver circuit426. When the clock signal is a logical low, i.e. a digital zero, capacitor C2428charges to approximately Vdd via transistors MP1464and MN2466. Similar to capacitor C1114described above in relation toFIG. 1, auxiliary driver circuit426is configured to tie reference voltage Vss to a first plate of capacitor C2428, which causes a second plate of the capacitor coupled to the MN2466to charge to approximately a magnitude of the supply voltage, Vdd. The voltage across C2228will be Vdd, minus any voltage drops across transistors MP1464and MN2466.

When the clock signal is a logical one, refresh output230will couple a voltage to the gate of Mpass412, via transistor MN4438with a magnitude of approximately Vdd+VDDIO. The magnitude of voltage applied to gate434may be an example of the predetermined magnitude of voltage applied to control terminal134, described above in relation toFIG. 1. Transistors MN0416and MN2466perform a similar switching function as diodes D1116and D2236, described above in relation toFIGS. 1 and 2.

FIG. 4Bis a schematic diagram illustrating an example digital I/O protection circuit with details of an example implementation of overvoltage monitoring according to one or more techniques of this disclosure. Circuit400B is an example of circuit400A, and the functions and characteristics of components of circuit400B are the same as the functions and characteristics of components of circuit400A described above in relation toFIG. 4A, unless otherwise noted. Circuit400B includes one example implementation of a comparison circuit, similar to comparison circuit450A described above in relation toFIG. 4A. In other examples, the arrangement and selection of components in circuits400A and400B may be different than that shown inFIGS. 4A and 4B. As one example, MN0416and MN3472may be implemented with diodes, while leaving the remaining arrangement as shown inFIGS. 4A and 4B.

Comparison circuit450B includes comparator480with the non-inverting input connected to digital output terminal406via resistor R1482and to reference voltage Vss via Zener diode D4456. The inverting input of comparator480connects to the gate of Mpass412. Thus, if an overvoltage at digital output terminal406exceeds a threshold magnitude of voltage compared to a magnitude of voltage at the control terminal of the pass-device, Mpass412, comparator480may output a logical HIGH. In the example of comparison circuit450B, the threshold is set by selecting the characteristics of Zener diode D4456and the value of resistor R1482.

The output of comparator480connects to the gate of transistor MN4488. The source of transistor MN4488connects to the reference voltage Vss and the drain of MN4488connects to Vdd via resistor R2484. The drain of MN4488also connects to the gates of transistors MP2486and MN5490. The source of MN5490connects to Vss and the drain of MN5490connects to the drain of MP2486. The source of MP2connects to Vdd.

FIG. 5is an example digital output protection circuit that uses a charge pump and pull-down circuit to operate a pass-device. The example of circuit500uses additional circuitry, including a charge pump to control the operation of the pass-device rather than controlling the pass-device using the output driver as described above in relation toFIGS. 1-4B.

In the example of circuit500, driver505receives a digital input at input element504and outputs a buffered digital output to digital output terminal506via pass-device, Mpass515. Circuit500includes low-voltage driver505with a high-voltage NMOS pass-device Mpass515in series. Mpass515prevents propagation of high-voltages that might be applied at the digital output terminal506to the LV driver, such as from a short to battery. The high-voltage NMOS pass-device, Mpass515is driven by charge-pump513, to provide a high enough VGS525so Mpass515turns ON with a low enough drain-source resistance RDS-ON. In some examples, depending on the technology used, a circuit such as circuit500may also include pull-down circuit510to dynamically lower the gate voltage of the pass-device when driver505propagates a logic ‘0.’ As one example, for an SPT9U MOSFET, to fulfill the required gate-source voltage (e.g. for an output ‘high’ level of 5V) the maximum VGSmay be 2.65V. Pull-down circuit510is coupled to the gate of Mpass515and controlled by driver505. In the example of circuit500, charge-pump513therefore needs to drive sufficient current to operate pull down circuit510. Therefore, to recharge the capacitors of charge pump513requires a sufficiently high speed clock527, which may increase cost and has an increased risk of interference with other areas of circuit (not shown inFIG. 500). Circuit500may have disadvantages because circuit500may also require a relatively large area on an IC.

One advantage of the techniques of this disclosure described above in relation toFIGS. 1-4Bis that the techniques may achieve an improved power efficiency in terms of current consumption. In the example of circuits100-400B, a charge pump running at high speed is not required to drive the gate of the pass-device, and there is no static current consumption caused by pull-down circuitry, which would be needed by circuit500to limit the VGSof the NMOS when the signal received by input element504goes ‘Low’.

FIG. 6is a flowchart illustrating an example operation of the circuit of this disclosure. The blocks ofFIG. 6will be described in terms ofFIG. 4B, unless otherwise noted.

In response to receiving a digital zero at input element404connected to the input of driver circuit402, capacitor C1414charges via transistor MN0416such that the magnitude of voltage across C1414is approximately equal to supply voltage Vdd, less any voltage drop across MP0460and MN0416(90). C1414is also connected between a gate and a source of NMOS pass-device Mpass412.

In response to receiving a digital one at input element404, driver circuit402may apply digital supply voltage VDDIOto the source of the Mpass412. Because C1414retains Vdd across the two terminals of C1414, the gate-source voltage of Mpass412is approximately the magnitude of voltage across the capacitor (92). As described above in relation toFIG. 4B, the voltage Vdd across C1414is configured to make sure that transistor Mpass412stays ON to send the digital one to digital output terminal406.

Also, receiving a digital one at input element404, enables a clock signal received at clock input element422to pass through AND gate424. The clock signal enables the refresh circuit, e.g. refresh circuit220described above in relation toFIG. 2, to periodically apply a voltage to the control terminal of the pass-device, Mpass412(94).

Comparison circuit450B is configured to compare a of voltage at the gate of pass-device Mpass412to a of voltage at digital output terminal406(96). Based on the comparison, comparator180controls the operation of pull-down transistors, e.g. MP0460and MN1470, as well as switches MN0416and MN3472.

To protect driver402from damage caused by an overvoltage, in response to the voltage at digital output terminal406exceeding the voltage at the gate of the Mpass412by an overvoltage threshold, comparison circuit450B is configured to control switch MN0416to turn OFF, i.e. disable, Mpass412, thereby isolating the digital output terminal from the driver circuit (98).

The techniques of this disclosure may also be described in the following examples.

A circuit comprising: a driver circuit comprising an input element and an output element, wherein the output element is electrically coupled to a digital output terminal via a pass-device. The pass-device comprises a first terminal, a second terminal and a control terminal, the pass-device is configured to protect the driver circuit from an overvoltage applied to the digital output terminal, the output element of the driver circuit is electrically connected both to the first terminal of the pass-device and via a capacitor to the control terminal of the pass-device, the control terminal of the pass-device is coupled to a supply voltage through a switch, and the second terminal of the pass-device is coupled to the digital output terminal.

The circuit of example 1, wherein the pass-device comprises an N-channel metal-oxide semiconductor (NMOS) transistor and wherein the first terminal is a source of the NMOS transistor, the second terminal is a drain and the control terminal is a gate.

The circuit of any combination of examples 1-2, further comprising a refresh circuit configured to apply a predetermined voltage amplitude at the control terminal of the pass-device, the refresh circuit comprising: an enable input element electrically coupled to the input element of the driver circuit, a refresh output element coupled to the control terminal of the pass-device, and a clock input element.

The circuit of any combination of examples 1-3, wherein the capacitor is a first capacitor, the refresh circuit further comprising: a second capacitor; and an auxiliary driver circuit configured to charge the second capacitor in response to receiving a digital one at the enable input element.

The circuit of any combination of examples 1-4, wherein the switch is a first switch, the refresh circuit further comprising a second switch arranged such that the second switch controls the refresh output element.

The circuit of any combination of examples 1-5, wherein in response to receiving a digital zero at the input element: the driver circuit is configured to output a reference voltage to a first plate of the capacitor and a second plate of the capacitor is configured to charge to approximately a magnitude of the supply voltage.

The circuit of any combination of examples 1-6, wherein the pass-device is configured to protect the driver circuit from an overvoltage applied to the digital output terminal of at least forty volts greater than the reference voltage.

The circuit of any combination of examples 1-7, wherein in response to receiving a digital one at the input element: the driver circuit is configured to output a first voltage, wherein: a magnitude of the first voltage is approximately equal to a digital supply voltage, and a magnitude of voltage between the first terminal of the pass-device and the control terminal is approximately equal to the supply voltage.

The circuit of any combination of examples 1-8, wherein an overvoltage is a magnitude of voltage at the digital output terminal that exceeds a threshold magnitude of voltage compared to a magnitude of voltage at the control terminal of the pass-device.

The circuit of any combination of examples 1-9, further comprising comparison circuitry, wherein the comparison circuitry is configured to: determine whether the magnitude of voltage at the digital output terminal is an overvoltage. In response to determining that the magnitude of voltage at the digital output terminal is an overvoltage, control the switch to disable the pass-device, and thereby prevent the overvoltage from reaching the output element of the driver circuit.

The circuit of any combination of examples 1-10, wherein further comprising a refresh circuit, wherein in response to determining that the magnitude of voltage at the digital output terminal is an overvoltage, the comparison circuitry is further configured to disable the refresh circuitry.

The circuit of any combination of examples 1-11, wherein the comparison circuitry comprises one or more processors.

The circuit of any combination of examples 1-12, wherein the comparison circuitry comprises a comparator with a first input element and a second input element and an output element, wherein: the first input element of the comparator is electrically coupled to the digital output terminal, the second input element of the comparator is electrically coupled to the control terminal of the pass-device, and the output element of the comparator causes the switch to pull down the control terminal to isolate the digital output terminal from the output element of the driver circuit.

A method comprising: in response to receiving a digital zero at an input element of a driver circuit, charging a capacitor such that the magnitude of voltage across the capacitor is approximately first supply voltage, wherein the capacitor is coupled to the first supply voltage through a switch, and wherein the capacitor is connected between a gate and a source of an N-channel metal-oxide semiconductor (NMOS) pass-device. In response to receiving a digital one at the input element of the driver circuit, applying, by the driver circuit, a second voltage to the source of the NMOS pass-device such that the gate-source voltage of the NMOS pass-device is approximately the magnitude of voltage across the capacitor.

The method of example 14, further comprising, in response to receiving the digital one at the input element of the driver circuit, enabling a refresh circuit.

The method of any combination of examples 14-15, wherein the refresh circuit is configured to maintain a predetermined magnitude of voltage at the gate of the pass-device and wherein the refresh circuit comprises: an enable input electrically coupled to the input element of the driver circuit, and a refresh output element coupled to the gate of the pass-device.

The method of any combination of examples 14-16, wherein the refresh circuit is configured to periodically maintain the predetermined magnitude of voltage at the gate of the pass-device based on a clock signal input to the refresh circuit.

The method of any combination of examples 14-17, wherein the pass-device is configured to isolate the driver circuit from a digital output element, the method further comprising: comparing a voltage at the gate of the pass-device to a voltage at the digital output element. In response to the voltage at the digital output element exceeding the voltage at the gate of the pass-device by an overvoltage threshold, controlling the switch such that the NMOS pass-device is disabled, thereby isolating the digital output terminal from the driver circuit.

The method of any combination of examples 14-18, further comprising, in response to the voltage at the digital output element exceeding the voltage at the gate of the pass-device by an overvoltage threshold, controlling a second switch to disable a refresh circuit, wherein the refresh circuit is configured to maintain a predetermined magnitude of voltage at the gate of the pass-device.