Semiconductor device

A semiconductor device includes a semiconductor layer, a first conductor film, a second conductor film, and a first protective film. The semiconductor layer has a semiconductor element. The first conductor film is formed on an upper surface of the semiconductor layer and is electrically connected to the semiconductor element. The second conductor film is formed on an outer side surface of the semiconductor layer and is electrically connected to the semiconductor element. The first protective film is formed on the first conductor film and has an opening to expose the first conductor film. A height from the upper surface of the semiconductor layer to an upper surface of the second conductor film is equal to or smaller than a height from the upper surface of the semiconductor layer to an upper surface of the first conductor film.

BACKGROUND

1. Field of the Invention

The present disclosure relates to a semiconductor device.

2. Description of the Related Art

The semiconductor device is provided by singulating and packaging a semiconductor wafer, on which semiconductor elements are formed through processes such as diffusing and wiring, to be connected to an external circuit. A great number of such semiconductor devices are mounted in an electronic device.

In the semiconductor device, a structure in which a major current path is formed between an upper surface and a lower surface of the semiconductor element is used in the semiconductor element such as a metal oxide semiconductor field effect transistor (MOSFET) using a large current, a bipolar transistor, and a diode. The semiconductor device including the above semiconductor element is difficult to miniaturize after the device has been packaged. This is because an electric connection is made from each of the upper surface and the lower surface of the semiconductor element through die bonding and wire bonding, and the packaging needs to be a plastic type or ceramic type.

Meanwhile, Unexamined Japanese Patent Publication No. 2010-129749 discloses a wafer level chip size package (CSP) technique in which an electric connection is ensured by forming a penetration electrode and rewiring, during an assembly process on a wafer. CSP technique has received attention.

Furthermore, a rewiring technique disclosed in Unexamined Japanese Patent Publication No. 2009-224641 is an effective technique for miniaturizing the device. Thus, by a technique to form a side surface electrode as disclosed in the Unexamined Japanese Patent Publication No. 2009-224641, characteristics of the semiconductor element can be improved and an integration degree thereof can be improved due to a more cubical wiring structure.

SUMMARY

A semiconductor device in an aspect of the present disclosure includes a semiconductor layer, a first conductor film, a second conductor film, and a first protective film. The semiconductor layer has a semiconductor element. The first conductor film is formed on an upper surface of the semiconductor layer and is electrically connected to the semiconductor element. The second conductor film is formed on an outer side surface of the semiconductor layer and is electrically connected to the semiconductor element. The first protective film is formed on the first conductor film and has one or more openings to expose the first conductor film. Furthermore, a height from the upper surface of the semiconductor layer to an upper surface of the second conductor film is equal to or smaller than a height from the upper surface of the semiconductor layer to an upper surface of the first conductor film.

According to the semiconductor device in the aspect of the present disclosure, electric resistance is reduced and mechanical strength is enhanced at the same time, and face-down mounting can be readily performed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As for a semiconductor device disclosed in the Unexamined Japanese Patent Publication No. 2010-129749 regions for a through hole and the penetration electrode need to be ensured in a semiconductor substrate, and an external terminal region needs to be formed on an upper surface of the semiconductor substrate to be electrically connected to its lower surface. Thus, compared with the conventional plastic type semiconductor device or ceramic type semiconductor device, the upper surface of the semiconductor substrate is limited in view of a layout. There is a problem that a region of the semiconductor element having the major current path between the upper surface and the lower surface becomes small. As a result, electric resistance in using a circuit is difficult to reduce with respect to an area of the semiconductor substrate, which limits a design of the semiconductor device.

Furthermore, as for the conventional wafer level CSP, since a portion such as the side surface of the semiconductor device is exposed, there is a problem that it is vulnerable to mechanical outer force.

Furthermore, as for a semiconductor device disclosed in the Unexamined Japanese Patent Publication No. 2009-224641, a lower surface electrode is connected to a lead frame with a solder. When the technique in the Unexamined Japanese Patent Publication No. 2009-224641 is used for the face-down mounting which does not use the lead frame, a height from a substrate to an upper surface of an upper surface electrode is smaller than a height from the substrate to an upper surface of a side surface electrode, which causes a connection defect in the upper surface electrode.

In view of the above, the present disclosure provides a semiconductor device which can reduce electric resistance, enhance mechanical strength, and be readily face-down mounted.

Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings. However, a detailed description for a well-known technique, and a duplicated description for substantially the same component are skipped occasionally. The present disclosure is not limited to the following exemplary embodiments, and a plurality of exemplary embodiments may be combined, or an equivalent component may be replaced without departing from the scope of the technique of the present disclosure.

First Exemplary Embodiment

Hereinafter, a semiconductor device in the first exemplary embodiment will be described with reference toFIGS. 1A to 3E.

FIG. 1Ashows an upper surface of the semiconductor device in this exemplary embodiment. The semiconductor device includes conductor films102a,102b, and102c. Conductor film102cserves as a side surface of the semiconductor device. Conductor film102aand conductor film102bare covered with protective film104such as a silicon nitride film. Conductor films102aand102bunder protective film104each have planar shapes shown by broken lines inFIG. 1A.

In this specification, “upper surface” means a surface to be bonded to a mounting substrate at the time of mounting, and “lower surface” means a surface opposite the “upper surface” unless otherwise noted. In addition, “side surface” means a surface other than the “upper surface” and the “lower surface”, and “outer side surface” means “side surface” disposed at outer periphery.

A plurality of openings are provided in protective film104, and conductor films102aand102bare exposed at the openings. Each of the conductor films102aand102bexposed at the openings serves as an external terminal. As shown inFIG. 1A, one opening106ais formed in protect film104for conductor film102a, and three openings106b,106c, and106dare formed in protective film104for conductor film102b. The side surface of the semiconductor device is formed of conductor film102cwhich serves as the external terminal. In this specification, “external terminal” of the semiconductor device means a terminal to be connected to the mounting substrate, such as a gate terminal, a source terminal, or a drain terminal.

FIG. 1Bis a cross-sectional view taken along line1B-1B inFIG. 1A.FIG. 1Bshows a case where the semiconductor device is a field effect transistor (FET). The semiconductor device includes first conductivity type semiconductor layer110, first conductivity type semiconductor layer112disposed on semiconductor layer110, second conductivity type semiconductor portion114formed in a region at an upper surface side of semiconductor layer112, and first conductivity type semiconductor portion116formed in a region at an upper surface side of semiconductor portion114. Semiconductor layer112and semiconductor portion114are composed of, for example, Si. Semiconductor portion114and semiconductor portion116are formed by a method such as ion implantation.

A semiconductor element in the semiconductor device is a so-called vertical MOSFET. That is, semiconductor layer110serves as a drain region, semiconductor portion114serves as a body region, semiconductor layer112serves as a drift region, and semiconductor portion116serves as a source region.

Insulating film124is disposed on a part of the upper surface of semiconductor layer112, and conductor film102aas the gate terminal is disposed on insulating film124. Conductor film102ais electrically connected to gate electrode122.

Conductor film102bas the source terminal is disposed on the semiconductor layer112which is not covered with insulating film124. Conductor film102bis electrically connected to semiconductor portion116serving as the source region. Furthermore, conductor film102bis electrically connected to semiconductor portion114serving as the body region.

Conductor film102cserving as the drain terminal is formed around the side surfaces of semiconductor layer110and the side surfaces of semiconductor layer112. Conductor film102cis electrically connected to semiconductor layer110serving as the drain region. Since conductor film102cis formed on the side surface of the semiconductor device, the semiconductor device is protected by conductor film102c. Thus, mechanical strength of the semiconductor device is increased. Furthermore, since the drain terminal is formed in the region other than the upper surface of the semiconductor layer, other regions for the semiconductor element can be provided in the semiconductor layer and on the upper surface of the semiconductor layer. Therefore, compared with a conventional semiconductor element having the same size, an area for the semiconductor element can be substantially increased, so that electric resistance in using a circuit can be readily reduced.

A height from the upper surface of semiconductor layer112to an upper surface of conductor film102cis equal to or smaller than a height from the upper surface of semiconductor layer112to upper surfaces of conductor film102aand conductor film102b. In this structure, a connection defect is not likely to occur in conductor film102aand conductor film102b, so that face-down mounting to the mounting substrate can be readily performed.

Furthermore, it is preferable that the upper surface of conductor film102a, the upper surface of conductor film102b, and the upper surface of conductor film102care flush with one another. In this structure, the semiconductor device can become readily parallel to the mounting substrate, so that the face-down mounting to the mounting substrate can be readily performed. In this specification, meaning of “flush” includes “substantially flush” including a manufacturing error.

Hereinafter, the semiconductor device inFIG. 1Bwill be described as a Nch FET in which the first conductivity type is an N type and the second conductivity type is a P type.

A voltage is applied between conductor film102c(drain terminal) and conductor film102b(source terminal), and between conductor film102a(gate terminal) and conductor film102b. At this time, conductor film102aand conductor film102cbecome electrically positive, and a channel is formed in semiconductor portion114(body region). When the voltage is applied, circuit current I flows from conductor film102cto conductor film102bthrough a path of conductor film102c, semiconductor layer110(mainly drain region), semiconductor layer112, semiconductor portion114, semiconductor portion116, and conductor film102b.

Furthermore, each region in the path of circuit current I preferably has as low electrical resistance as possible in order to prevent heat generation. For example, conductor film102cprovided in the path of circuit current I is preferably thick in a direction vertical to the side surfaces of semiconductor layer110and semiconductor layer112. More specifically, the thickness is preferably between 10−1μm and 102μm (inclusive). Furthermore, a thickness of semiconductor layer110is preferably between 50 μm and 200 μm (inclusive) to reduce the electrical resistance.

Hereinafter, a description will be given to a configuration in which the semiconductor device is face-down mounted on mounting substrate130.

FIG. 1Cis a cross-sectional view of the semiconductor device mounted on mounting substrate130taken along the same position as line1B-1B inFIG. 1A. As shown inFIG. 1C, each of conductor film102b, conductor film102a, and conductor film102cof the semiconductor device are electrically and mechanically connected to substrate pad134disposed on mounting substrate130through connection material136. Conductor film102aserves as the gate terminal, conductor film102bserves as the source terminal, and conductor film102cserves as the drain terminal. Substrate pad134is disposed on mounting substrate130, and exposed at an opening of substrate coating material132. Substrate coating material132is composed of an insulator, and substrate pad134is composed of, for example, Cu. Furthermore, in a case where mounting substrate130is a flexible substrate, reliability after the mounting is improved compared with the conventional semiconductor device.

As described above, the height from the upper surface of semiconductor layer112to the upper surface of substrate102cis equal to or smaller than the height from the upper surface of semiconductor layer112to the upper surfaces of conductor film102aand the conductor film102b. In this structure, a contact defect is hardly generated between conductor film102aand substrate pad134, and conductor film102band substrate pad134. On the other hand, as for conductor film102c, connection material136extends upward along the side surface of conductor film102c, so that a connection defect does not occur. As a result, the semiconductor device can be readily face-down mounted on the mounting substrate. In addition, although it is not shown, a plurality of recesses may be provided in conductor film102cso as to be disposed apart from each other. In this configuration, a contact area between connection material136and conductor film102cis increased, so that bonding strength and mounting strength are enhanced. Furthermore, a depth and a width of the recess are not limited in particular as long as the mounting can be performed properly.

In a case where thermal expansion coefficients of semiconductor layer110and semiconductor layer112are different from a thermal expansion coefficient of conductor film102c, peeling of conductor film102ccould be generated. This is because due to a change in environmental temperature in a process a counting process, the semiconductor device receives a stress between semiconductor layer110and conductor film102c, and semiconductor layer112and conductor film102c. In order to disperse the stress which causes the peeling, conductor film102cis to be tightly disposed on the side surfaces of semiconductor layers110and112without leaving any defects such as breaks, for example.

Each conductor film may be made of metal, polysilicon having high impurity concentration, or conductive paste. Each conductor film may be a single-layer film composed of alloy, a single-layer film composed of pure element of metal element or semi-metal element, a laminated-layer film composed of alloy, a laminated-layer film composed of pure element of metal element or semi-metal element, or a laminated-layer film composed of alloy and pure element. Examples of the metal element to be used include Ti, W, Al, Cr, Mo, Au, Pt, Ag, Cu, Ni, Co, Pd, Sn, Pb, Bi, and V. Examples of the semi-metal element to be used include Sb, As, B, Si, and Ge. Furthermore, examples of an additive to be used include a non-metal element such as P, C, N, or H. Among them, Au, Ag, Pd, or Bi is preferably used as a surface layer of each conductor film because it has a preferable wettability with the connection material such as solder, in general.

Connection material136may be a solder material selected from PbSn, AuSn, CuSN, AgSn, BiSn, AuSi, AuGe, and AuSb. However, another material may be used instead of the solder material as long as the mechanical strength and the electric resistance can satisfy required specifications after the mounting. For example, the material may be a conductive paste, a conductive resin, or brazing material composed of a mixture of metal such as Ag, Cu, Au, Ni or Al with an organic material.

As shown inFIG. 1A, an area of conductor film102aexposed at opening106a(hereinafter, referred to as opening areas) is preferably equal to an area of conductor film102bexposed at each of openings106bto106din protective film104.

In the face-down mounting, connection material136is printed on substrate pad134of mounting substrate130with a screen mask, for example. After that, the semiconductor device is disposed on uncured connection material136in a face-down state and temporarily fixed thereon. After that, connection material136is melted in a reflow process to bond mounting substrate130to the semiconductor device.

In this way, by equalizing each area of openings106ato106d, a height of connection material136provided in each opening, from an upper surface of substrate pad134is almost at the same level after the reflow process, so that the semiconductor device is prevented from being tilted after it is mounted, and a mounting defect is not likely to occur. Furthermore, a total area of the upper surface of conductor film102cmay be equal to each opening area.

Perimeters of openings106ato106dprovided in protective film104are preferably equal to each other. A surface tension is generated when connection material136is melted, so that connection material136tilts at an edge of the opening. Thus, a degree of the surface tension depends on the perimeter of the opening, so that an angle of the tilt also depends on the perimeter of the opening. Therefore, when the perimeter of the opening is equal, the angle of the tilt can be also equal, so that the mounting defect can be prevented from occurring.

When the opening area is equal and the perimeter is equal in each opening, the height of connection material136from the upper surface of substrate pad134can be the same with high accuracy at the time of mount so that the mounting defect can be reduced.

Variation 1 of First Exemplary Embodiment

Hereinafter, a semiconductor device in variation 1 in the first exemplary embodiment will be described with reference toFIG. 1D.

The semiconductor device in variation 1 differs from the semiconductor device shown inFIGS. 1A and 1B, in a configuration of conductor film102c. Conductor film102cis partially formed on a side surface of the semiconductor device. More specifically, conductor film102cis at least formed on side surface A of lower semiconductor layers (semiconductor layers110and112) and side surface B opposite side surface A. Conductor film102cmay be partially formed on each of two other side surfaces intersecting with side surface A and side surface B. In other words, the semiconductor device may have a pair of side surfaces covered with conductor film102cand a pair of side surfaces partially not covered with conductor film102c. Surface tension of melted connection material136in the reflow process pulls conductor film102chaving a preferable wettability. When conductor film102cis disposed only on the opposite surfaces, the semiconductor device can be prevented from being displaced when it is temporarily fixed to mounting substrate130by use of the surface tension of connection material136. Thus, a mounting defect can be prevented.

Furthermore, conductor film102cmay be partially formed on the side surface, and the side surface may have a portion not covered with conductor film102c. Through the portion not covered with conductor film102c, a wiring of the mounting substrate can be withdrawn to be connected to conductor films102aand102b, so that this configuration is especially useful when the mounting substrate is a single-layer wiring substrate. Furthermore, by appropriately setting the position of conductor film102c, a thick wiring can be withdrawn from the mounting substrate, so that ON-resistance can be readily reduced.

Variation 2 of First Exemplary Embodiment

Hereinafter, a semiconductor device in variation 2 of the first exemplary embodiment will be described with reference toFIG. 1E.

The semiconductor device in variation 2 differs from the semiconductor device shown innFIGS. 1A and 1Bin a configuration that contact region126having lower resistance than semiconductor layer110is formed between semiconductor layer110and conductor film102c.

In this variation, in a case where a conductivity type of semiconductor layer110is the N type, an impurity concentration of contact region126is preferably 1×1020[cm3] or more. In a case where the conductivity type of semiconductor layer110is the P type, the concentration of contact region126is preferably 1×1019[/cm3] or more.

In a case where conductor film102cis made of Mo, Cr, Ti, W, Ni, Au, Pt, Al, or Co by an electron beam (EB) vapor deposition method which is included in a physical vapor deposition (PVD) method, contact region126is naturally formed in semiconductor layer110. In the EB vapor deposition method, a material is evaporated and dispersed, so that the material reaches semiconductor layer110with thermal energy maintained. Thus, the material of conductor film102creacts with a material of the semiconductor layer, whereby contact region126is formed.

Contact region126can be provided by forming a silicide layer by a sputtering method which is included in the PVD method or chemical vapor deposition (CVD) method and performing a heat treatment, or by forming a silicide layer by a sputtering method. Furthermore, contact region126may be formed by additionally doping an impurity to semiconductor layer110, or dispersing an impurity. In addition, when a heat treatment is performed after the impurity is doped, to activate the impurity, the resistance of contact region126can be further lowered.

Furthermore, instead of forming contact region126, semiconductor layer110may be roughened in a contact surface with conductor film102c. That is, an area of the contact surface is increased, so that contact resistance can be lowered.

In this configuration, electric resistance can be reduced between semiconductor layer110and conductor film102c, so that the semiconductor device can be miniaturized.

Other Variations of First Exemplary Embodiment

The description has been given to the Nch FET as the semiconductor element in the first exemplary embodiment and variations 1 and 2, but the same effect can be provided in a Pch FET. Furthermore, the same effect can be provided in a diode shown inFIG. 2A, a bipolar transistor shown inFIG. 2C, a thyristor shown inFIG. 2D, and insulated gate bipolar transistor (IGBT) shown inFIG. 2Eas well as the FET.

The diode shown inFIG. 2Aincludes N-type semiconductor layer200, N-type semiconductor layer202formed on semiconductor layer200, P-type semiconductor portion204formed in semiconductor layer202, and conductor film206formed on semiconductor portion204. Insulating film210is formed on semiconductor layer202to insulate the conductor films from each other. Conductor film206is exposed at an opening in protective film212.

Conductor film206serves as an anode region, and conductor film208serves as a cathode region. An impurity concentration of semiconductor layer200is higher than an impurity concentration of semiconductor layer202.FIG. 2Bis a plan view of the diode shown inFIG. 2A, in which four openings are formed for conductor film206.

Conductor film208serves as a side surface of the semiconductor device and electrically connected to semiconductor layer200and semiconductor layer202. Furthermore, in a case where semiconductor layer200and semiconductor layer202are the P type, and semiconductor portion204is the N-type, the anode region and the cathode region are exchanged.

Conductor film208may cover insulating film210. That is, conductor film208may cover an intersection of an upper surface and a side surface of the semiconductor layer. In this case, end214, provided on insulating film210, of conductor film208is preferably covered with protective film212.

In this structure, end214in which a stress is likely to be concentrated is covered with protective film212, conductor film208can be prevented from being peeled from insulating film210, semiconductor layer202, and semiconductor layer200. This structure can be applied to the semiconductor device shown inFIG. 1B.

Conductor film228electrically connected to semiconductor portion224serves as a base region, and conductor film230electrically connected to semiconductor portion226serves as an emitter region. Conductor film232serves as a collector region. Conductor films are insulated from each other by insulating film234. Conductor film228and conductor film230are exposed at openings provided in protective film236and serve as external terminals. In addition, a plan view showing the conductor film and the protective film in the bipolar transistor inFIG. 2Cis substantially the same as that shown inFIG. 1A.

The thyristor shown inFIG. 2Dincludes P-type semiconductor layer240. N-type semiconductor layer242formed on semiconductor layer240, P-type semiconductor portion244formed in semiconductor layer242, and N-type semiconductor portion246formed in semiconductor portion244. Conductor films are insulated from each other by insulating film254. Conductor film248and conductor film250are exposed at openings provided in protective film256and serve as external terminals.

Conductor film252is electrically connected to semiconductor layer240and serves as an anode region which is an external terminal. Conductor film248electrically connected to semiconductor portion244serves as a gate terminal. Conductor film250electrically connected to semiconductor portion246serves as a cathode region. Furthermore, in a case where semiconductor layer240and semiconductor portion244are the N type, and semiconductor layer242and semiconductor portion246are the P type, the anode region and the cathode region are exchanged. In addition, a plan view of the conductor film and the protective film of the thyristor shown inFIG. 2Dis substantially the same as that shown inFIG. 1A.

The IGBT shown inFIG. 2Eincludes P-type semiconductor layer260, N-type semiconductor layer262formed on semiconductor layer260, N-type semiconductor layer264formed on semiconductor layer262, P-type semiconductor portion266formed in semiconductor layer264, and N-type semiconductor portion268formed in semiconductor portion266. Gate oxide film272is disposed in groove270which is formed so as to penetrate semiconductor portion268and semiconductor portion266to reach semiconductor layer264. Gate electrode274is disposed in gate oxide film272. Conductor film280and conductor film282are exposed at openings formed in protective film284and serve as external terminals.

Conductor film276is electrically connected to semiconductor layer260and serves as a collector, and semiconductor layer262and semiconductor layer264are insulated by insulating film278. Conductor film280insulated from semiconductor layer264by insulating film278is electrically connected to gate electrode274to serve as a gate terminal. Conductor film282electrically connected to semiconductor portion268serves as an emitter. Conductor film280is insulated from conductor film276by insulating film278, and conductor film282is insulated from conductor film276by insulating film278. Note that, a plan view of the conductor film and the protective film of the IGBT shown inFIG. 2Eis substantially the same as that shown inFIG. 1A.

Manufacturing Method

Hereinafter, a method for manufacturing the semiconductor device in the first exemplary embodiment in the present disclosure will be described with reference to cross-sectional views shown inFIGS. 3A to 3F.

First, as shown inFIG. 3A, a semiconductor element such as FET is formed in wafer-like semiconductor substrate300. Wafer-like semiconductor substrate300has upper surface302, and lower surface304opposite upper surface302.

Subsequently, as shown inFIG. 3B, groove306is formed from upper surface302to semiconductor layer110along an outer shape of the FET. Groove306may be formed by blade dicing or laser dicing.

Groove306may be formed by dry etching with a photoresist or hard mask. In this case, the semiconductor device can be prevented from being damaged by dicing. In addition, since the process can be conducted on whole upper surface302of wafer-like semiconductor substrate300, groove306can be formed in a short time. Furthermore, groove306may be formed by wet etching with a mask such as photoresist, silicon oxide film mask, or metal mask.

Subsequently, as shown inFIG. 3C, an opening of insulating film124is formed in upper surface302to form conductor film102b. The opening may be formed by partially etching insulating film124with a mask such as photoresist.

Subsequently, as shown inFIG. 3D, conductor film102ais formed on insulating film124, conductor film102bis formed in the opening, and conductor film102cis formed in groove306. The conductor film is preferably formed by a CVD method. For example, when a CVD film made of Ti or W is used, conductor film102ccan be readily thickened, so that electric resistance of conductor film102ccan be reduced. Conductor film102cmay be formed by a plating method.

Finally, as shown inFIG. 3F, lower surface304of wafer-like semiconductor substrate300is ground to reach groove306, whereby the semiconductor device is completed. The grinding process may be performed by a method such as back grinding, polishing, wet etching, dray etching, or chemical mechanical polishing (CMP). The above methods may be combined.

Second Exemplary Embodiment

Hereinafter, a semiconductor device in the second exemplary embodiment in the present disclosure will be described with reference toFIGS. 4A to 4D.

FIG. 4Ais a plan view of the semiconductor device in the second exemplary embodiment. A broken line shows conductor films402aand402bunder protective film404.

As shown inFIG. 4A, the semiconductor device includes conductor film402a, conductor film402bsurrounded by conductor film402a, and protective film404formed on the conductor films. Two openings406aand406bare provided in protective film404for conductor film402a, while one opening406cis provided in protective film404for conductor film402b. Each of conductor film402a, conductor film402b, and conductor film402cprovided on each of opposite side surfaces of the semiconductor device serves as an external terminal.

FIG. 4Bis a plan view of the semiconductor device mounted on mounting substrate130.FIG. 4Bis a through-view of a portion other than the conductor film in the opening formed in protective film404, and of substrate coating material132which will be described below.FIG. 4Cis a cross-sectional view taken along line4C-4C inFIG. 4B.

As shown inFIGS. 4B and 4C, each conductor film is connected to substrate pad134provided on mounting substrate130through connection material136. Substrate pad134connected to conductor film402aand conductor film402bcan be withdrawn through a region not covered with conductor film402c. Substrate pad134serves as a wiring of mounting substrate130.

In a case where the semiconductor element in the semiconductor device is a field effect transistor (FET), for example, conductor film402aserves as a source electrode, conductor film402bserves as a gate electrode, and conductor film402cserves as a drain electrode. In a case where capacity between the gate and the drain is large, if an input is repeatedly switched between ON and OFF in the FET in a high-frequency switching operation, an output cannot be switched between ON and OFF with high follow ability.

However, according to this exemplary embodiment, conductor film402aserving as the source electrode is disposed between conductor film402bserving as the gate electrode and conductor film402cserving as the drain electrode, so that the capacity between the gate and the drain can be small. This is because capacity between the gate and the source is connected in series with capacity between the source and the drain, so that the capacity between the gate and the drain becomes small when this is seen as an equivalent circuit. Thus, the semiconductor device can be superior in high-frequency driving.

FIG. 4Dis a plan view of a semiconductor device in a variation of this exemplary embodiment.

As shown inFIG. 4D, conductor film402bserving as a gate terminal may be circular in shape, and conductor film402aserving as a source terminal may be formed into a donut shape surrounding conductor film402bin a plan view. In this case, since conductor film402aand conductor film402bhave the circular shape, the semiconductor device could rotate at the time of the face-down mounting. Thus, in order to prevent the semiconductor device from rotating, conductor film402cis formed at four corners of the semiconductor device.

In addition, the semiconductor element may be another semiconductor element which can be driven at high speed such as bipolar transistor or IGBT. Furthermore, the source terminal is not always connected to the ground potential, and may be connected to a lowest potential supplied from an external circuit, in the semiconductor element.

Third Exemplary Embodiment

Hereinafter, a semiconductor device in the third exemplary embodiment in the present disclosure will be described with reference toFIGS. 5A and 5B.FIG. 5Ais a plan view of the semiconductor device.FIG. 5Bis a cross-sectional view of the semiconductor device taken along line5B-5B inFIG. 5A.

Protective film500is formed on a side surface of the semiconductor device, that is, on conductor film102c. Protective film500preferably has an insulating property. Protective film500is made of, for example, silicon oxide, silicon nitride, organic material, resin, silicone, metal oxide, or composed of composite material of the above materials, or may have laminated layers of the above materials. Protective film500may be formed by a CVD method.

In a manufacturing process of the semiconductor device including a mounting process, in order to reduce manufacturing costs by shortening a manufacturing time per semiconductor device, manufacturing speed is increased to maximum within a range tolerated by mechanical strength of the semiconductor device. However, in view of the mechanical strength of the semiconductor device, the manufacturing speed cannot be increased in some cases.

However, in this configuration, since conductor film102cis covered with protective film500, so that the semiconductor device has high mechanical strength. As a result, the manufacturing speed can be increased, so that a mass-productivity can be improved, and the low costs can be achieved.

Fourth Exemplary Embodiment

Hereinafter, a semiconductor device in the fourth exemplary embodiment in the present disclosure will be described with reference toFIGS. 6A and 6B.FIG. 6Ais a plan view of the semiconductor device.FIG. 6Bis a cross-sectional view of the semiconductor device taken along line6B-6B inFIG. 6A.FIG. 6Cis a cross-sectional view of the semiconductor device mounted on a mounting substrate taken along the same position as line6B-6B inFIG. 6A.

As shown inFIGS. 6A and 6B, conductor film600covers a part of conductor films102aand102bexposed at openings106a,106b,106cand106dformed in protective film104, and an upper surface and a part of a side surface of conductor film102c. The side surface of conductor film102cmay be totally covered with conductor film600.

According to the method for manufacturing the semiconductor device in this exemplary embodiment, after conductor film102cis formed in groove306as shown inFIG. 3C, a whole upper surface302of wafer-like semiconductor substrate300is subjected to electroless plating. Through this electroless plating, conductor film600can be formed to have better wettability to connection material136that conductor film102c.

In this configuration, connection material136can be likely to extend upward along conductor film102c, so that a bonding area is increased, and bonding strength can be improved.

Furthermore, a thickness of conductor film600can be appropriately changed by adjusting a concentration of an electroless plating solution, or stirring speed of the plating solution during the plating operation. Conductor film102cand conductor film600may be made of different materials. In addition, when conductor film102cis made of Al, conductor film102chas a poor wettability to a SnAg solder which is a kind of Sn-containing connection material. In this case, electroless plating is performed with Ni or Au which has a good wettability to the SnAg solder. However, the material of conductor film600is not limited to Ni or Au.

Fifth Exemplary Embodiment

Hereinafter, a semiconductor device in the fifth exemplary embodiment of the present disclosure will be described with reference toFIGS. 7A and 7B.

FIG. 7Ais a plan view of the semiconductor device. As shown inFIG. 7A, a plurality of grooves700are formed at intervals along an outer periphery of an upper surface of the semiconductor device. Conductor film702is formed in groove700.

FIG. 7Bis a cross-sectional view of the semiconductor device taken along line7B-7B inFIG. 7A. As shown inFIG. 7B, an upper surface of conductor film702is flush with upper surfaces of conductor film102aand102b. A height of an upper surface of conductor film102cis smaller than a height of the upper surface of conductor film702, based on a lower surface of the semiconductor device, so that level difference704is formed between conductor film102cand conductor film702.

In this structure, compared with the semiconductor device in the first exemplary embodiment in which the connection material only contacts with conductor film102con the side surface of the semiconductor device, the connection material largely contacts with conductor film102cand conductor film702, so that bonding strength with the mounting substrate is further increased.

The method for manufacturing the semiconductor device in this exemplary embodiment is provided by adding the following step to the manufacturing method in the first exemplary embodiment. For example, in the process for forming the semiconductor element, plurality of grooves700are formed so as to be disposed apart from each other in semiconductor layer112. Conductor film702is formed in groove700when conductor films102aand102bare formed. After that, almost the same process as the manufacturing method in the first exemplary embodiment is performed, whereby the semiconductor device is completed.

In addition, a depth of groove700from the upper surface of semiconductor layer112, a width of groove700in a side surface direction, and the number of grooves700may be optionally selected to the extent that an operation of the semiconductor element is not adversely affected. Furthermore, groove700may be formed to reach semiconductor layer110.

Sixth Exemplary Embodiment

Hereinafter, a semiconductor device in the sixth exemplary embodiment of the present disclosure will be described with reference toFIGS. 8A and 8B.FIG. 8Ais a plan view of the semiconductor device.FIG. 8Bis a cross-sectional view of the semiconductor device taken along line8B-8B inFIG. 8A.

As shown inFIG. 8A, conductor film800serves as a side surface of the semiconductor device. As shown inFIG. 8B, a height of an upper surface of conductor film800is smaller than a height of an upper surface of conductor film102c, based on a lower surface of the semiconductor device, so that level difference802is formed between conductor film102cand conductor film800.

In this structure, compared with the semiconductor device in the first exemplary embodiment in which the connection material only contacts with conductor film102con the side surface of the semiconductor device, a connection material largely contacts with conductor film102cand conductor film800, so that bonding strength with the mounting substrate is further increased.

The method for manufacturing the semiconductor device in this exemplary embodiment is provided by adding the following step to the manufacturing method in the first exemplary embodiment. For example, under the condition that upper surface302of the singulated semiconductor device is held, only lower surface304is soaked in an electroless plating bath, and a plated film is ground, whereby the semiconductor device is completed.

Seventh Exemplary Embodiment

Hereinafter, a semiconductor device in the seventh exemplary embodiment of the present disclosure will be described with reference toFIGS. 9A to 9C.FIG. 9Ais a plan view of the semiconductor device.FIG. 9Bis a cross-sectional view of the semiconductor device taken along line9B-9B inFIG. 9A. As shown inFIG. 9A, groove900is formed in an upper surface of protective film104. Groove900is formed between conductor films. As shown inFIG. 9B, groove900is formed not to penetrate protective film104. In addition, groove900may be formed to penetrate protective film104so that conductor film102band insulating film124are exposed.

FIG. 9Cis a cross-sectional view of the semiconductor device mounted on a mounting substrate taken along the same position as line9B-9B inFIG. 9A. In a reflowing process to mount the semiconductor device on the mounding substrate, a capillary phenomenon occurs in a space between the semiconductor device and the mounting substrate. Thus, when a distance between the conductor films is reduced as the semiconductor device is miniaturized, melted connection materials136are connected to each other due to the capillary phenomenon in some cases.

However, according to this exemplary embodiment, protective film104has groove900. In this structure, as shown inFIG. 9C, groove900can prevent connection materials136from being connected to each other due to the capillary phenomenon.

As a result, the distance between the conductor films can be reduced, so that the semiconductor device can be miniaturized.

The method for manufacturing the semiconductor device in this exemplary embodiment is provided by adding the following step to the manufacturing method in the first exemplary embodiment. For example, after protective film104has been formed, groove900is formed between the conductor films in the upper surface of protective film104by etching.

In addition, instead of forming groove900in protective film104, a groove may be formed in substrate coating material132, or grooves may be formed in both of protective film104and substrate coating material132.

Eighth Exemplary Embodiment

Hereinafter, a semiconductor device in the eighth exemplary embodiment of the present disclosure will be described with reference toFIGS. 10A to 10C.FIG. 10Ais a plan view of the semiconductor device in the eighth exemplary embodiment.FIG. 10Bis a cross-sectional view of the semiconductor device taken along line10B-10B inFIG. 10A.FIG. 10Cis a cross-sectional view of the semiconductor device mounted on a mounting substrate taken along the same position as line10B-10B inFIG. 10A.

As shown inFIG. 10A, a side surface of the semiconductor device is covered with protective film1000. As shown inFIG. 10B, the semiconductor device further includes conductor film1002formed on a lower surface of semiconductor layer110and electrically connected to conductor film102c. A side surface of conductor film102cand a side surface and a lower surface of conductor film1002are covered with protective film1000.

A resistance component generated due to sheet resistance of semiconductor layer110becomes dominant with respect to a total resistance component in the semiconductor device in some cases. However, in this structure, due to conductor film1002, the resistance component can be reduced. In addition, as the thickness of conductor film1002is increased, electric resistance can be reduced. For example, the thickness of conductor film1002is preferably 3 μm or more, and its upper value is not limited in particular to the extent that the mounting is not affected. Furthermore, in this structure, in addition to the reduction in electric resistance, mechanical strength is increased in the semiconductor device, so that the manufacturing process including the mounting process of the semiconductor device can be easy to perform.

Since conductor film102cand conductor film1002are covered with protective film1000, the mechanical strength is high in the semiconductor device. Furthermore, protective film1000preferably has an insulating property. For example, it is preferably made of silicon oxide, silicon nitride, organic material, resin, silicone, metal oxide, or composite material of the above materials, or may have a laminated-layer structure composed of the above materials. Furthermore, in a case where conductor film102band conductor film1002have the same thickness, and protective film104and protective film1000formed on the lower surface of conductor film1002have the same thickness, an internal stress of the semiconductor device can be reduced, so that even when the semiconductor layer is thinned, the semiconductor device is not likely to warp, and is easy to handle.

The method for manufacturing the semiconductor device in this exemplary embodiment is provided by adding the following step to the manufacturing method in the first exemplary embodiment. For example, after the lower surface of semiconductor layer110has been ground, conductor film1002is formed by sputtering or vapor deposition. After that, protective film1000is formed on the side surface of conductor film102cand the side surface and the lower surface of conductor film1002, whereby the semiconductor device is completed.

Ninth Exemplary Embodiment

Hereinafter, a semiconductor device in the ninth exemplary embodiment of the present disclosure will be described with reference toFIGS. 11A and 11B.FIG. 11Ais a plan view of the semiconductor device.FIG. 11Bis a cross-sectional view of the semiconductor device taken along line11B-11B inFIG. 11A.FIG. 11Cis a cross-sectional view of the semiconductor device taken along line11C-11C inFIG. 11A.

As shown inFIG. 11A, the semiconductor device includes conductor films1100and1102each formed on an upper surface and a side surface of the semiconductor device, conductor film1104formed on other side surfaces of the semiconductor device, and protective film1106for covering conductor films1100and1102on the upper surface of the semiconductor device. Conductor films1100and1102are disposed on insulating film1108. Conductor film1100serves as a gate electrode, conductor film1102serves as a source electrode, and conductor film1104serves as a drain electrode. As shown inFIG. 11B, each of conductor film1100and conductor film1102covers the upper surface and the side surface of the semiconductor device and is formed integrally.

In a case where the semiconductor devices in the first to eighth exemplary embodiments are miniaturized, an area of conductor film102bserving as the source electrode is reduced in the upper surface of the device, which causes an increase in ON-resistance.

However, according to this exemplary embodiment, since conductor film1102serving as the source electrode is also disposed on the side surface of the semiconductor layer, so that its area can be ensured. As a result, while the ON-resistance is prevented from being increased, the semiconductor device can be miniaturized.

As described above, the first to ninth exemplary embodiments and their variations have been described as the examples of the technique disclosed in this specification. However, the technique of the present disclosure is not limited to the above and can be applied to an exemplary embodiment in which change, replacement, addition, or omission is performed. Furthermore, a new exemplary embodiment can be provided by combining the components described in the first to ninth exemplary embodiments and their variations.

In the exemplary embodiments disclosed in this specification, the semiconductor layer is made of a material having a property of semiconductor such as Si, SiC, GaAs, or GaN.

Furthermore, the effect of the present disclosure can be attained in the above configuration regardless of the polarity of the semiconductor layer. Furthermore, the semiconductor device has the cubic shape in the above embodiments, but the effect of the present disclosure can be attained even when the semiconductor device has a cylindrical shape, a polygonal column shape such as triangular column or hexagonal column, or a polygonal pyramid such as triangular pyramid or hexagonal pyramid.

Furthermore, the above exemplary embodiments are provided only to embody the technique of the present disclosure, so that various change, replacement, addition, and omission can be allowed within the scope of the claims and its equivalent scope.