Trench forming method and structure

An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.

FIELD OF THE INVENTION

The present invention relates to a method for forming trenches in an electrical structure.

BACKGROUND OF THE INVENTION

Forming structures on a substrate typically comprises a complicated process with limited flexibility. Accordingly, there exists a need in the art to overcome at least one of the deficiencies and limitations described herein above.

SUMMARY OF THE INVENTION

The present invention provides a method comprising:

providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over and in contact with a surface of said semiconductor substrate, and an silicon on insulator layer (SOI) formed over and in contact with a surface of said BOX layer, wherein said SOI layer comprises shallow trench isolation (STI) structures formed between a plurality of active electrical devices;

forming a first photoresist layer over entire surfaces of said STI structures and over said plurality of active electrical devices;

simultaneously removing portions of said first photoresist layer existing between each active device of said plurality of active electrical devices;

simultaneously removing portions of said STI structures and portions of said BOX layer existing below said removed portions of said first photoresist layer resulting in trenches formed through said STI structures and said BOX layer, wherein said trenches are formed over portions of said surface of said semiconductor substrate resulting in said portions of said surface of said semiconductor substrate exposed within said trenches;

after simultaneously removing said portions of said STI structures and said portions of BOX layer, forming ion implants within portions of said semiconductor substrate, wherein said portions of said semiconductor substrate exist below each of said trenches;

after said forming said ion implants, simultaneously removing all remaining portions of said first photoresist layer;

forming a dielectric layer over said active electrical devices and within said trenches;

forming a second photoresist layer over said dielectric layer; and

simultaneously removing first portions of said second photoresist layer existing over said active electrical devices resulting in second portions of said second photoresist layer remaining over portions of said dielectric layer within said trenches.

The present invention provides a structure comprising:

a semiconductor substrate comprising ion implants formed within first portions of said semiconductor substrate;

buried oxide (BOX) structures formed over and in contact with second portions of said semiconductor substrate, wherein each BOX structure of said BOX is formed over and in contact with an associated portion of said second portions of said semiconductor substrate, and wherein said first portions of said semiconductor substrate differ from said second portions of said semiconductor substrate;

a plurality of active electrical device structures formed over and in contact with a first group of BOX structures of said BOX structures, wherein each active electrical device structure of said plurality of active electrical device structures comprises an active electrical device and a shallow trench isolation structure, wherein each said active electrical device structure is formed over an associated BOX structure of said first group of BOX structures, wherein trenches are formed between adjacent BOX structures of said first group of BOX structures, wherein each trench of said trenches is located over an associated ion implant of said ion implants, and wherein each said trench comprises a different size; and

a dielectric layer formed over said active electrical device structures, over said BOX structures, and within said trenches, wherein a bottom surface of said dielectric layer is in contact with said ion implants and said active electrical device structures, wherein a top surface of said dielectric layer comprises a planar surface, and wherein said top surface of said dielectric layer is not in contact with any material.

The present invention advantageously provides a simple structure and associated method for forming structures on a substrate.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1-7illustrate and describe stages in a fabrication process of a semiconductor structure2, in accordance with embodiments of the present invention. The electrical structure2illustrated inFIGS. 1-7is a cross sectional view. The semiconductor structure2may comprise any semiconductor structure known to a person of ordinary skill in the art including, inter alia, a semiconductor device, a semiconductor chip, etc. The fabrication process described with respect toFIGS. 1-7comprises the formation of a semiconductor structure comprising ion implants18and a planar surface20e(i.e., seeFIG. 7).

FIG. 1illustrates the semiconductor structure2provided for the fabrication process, in accordance with embodiments of the present invention. Note that the semiconductor structure2comprises a small portion of a semiconductor structure. Semiconductor structure2comprises a semiconductor substrate14(e.g., a semiconductor wafer) with a buried oxide (BOX) layer12(i.e., an insulator) formed over and in contact with the semiconductor substrate14and a silicon on insulator (SOI) layer11formed over and in contact with the BOX layer12. Electrical structure2additionally comprises a photoresist layer4. A portion of the photoresist layer4has been removed resulting in a formed opening6within the photoresist layer4. The removed portion of the photoresist layer4was patterned and removed using a photolithography process. The photolithography process used to pattern and remove the portions of photoresist layer4comprises the use of a first mask for patterning. The SOI layer11comprises shallow trench isolation (STI) structures10(i.e., an insulator) formed between electrical devices8. The electrical devices8may comprise active electrical devices or inactive electrical devices. An active electrical device may comprise any type of active electrical device including, inter alia, transistors, resistors, capacitors, etc. Inactive electrical devices comprise silicon structures that have not been formed into active electrical devices. The photoresist layer4(i.e., the remaining portions of the photoresist layer) is formed over the electrical devices8. The STI structures10comprise portions10a,10b, and10c. The BOX layer comprises portions12a,12b, and12c.

FIG. 2illustrates the semiconductor structure2ofFIG. 1after portion10bof the STI structures10and portion12bof the BOX layer12have been removed, in accordance with embodiments of the present invention. The removed portions10band12bform an opening6a(e.g., a trench, a via, etc) that exposes a portion of a top surface14aof the semiconductor substrate14. Note that the electrical structure2may comprise a plurality of openings similar to the opening6aand that each opening may comprise a different size (e.g., a different size for a width, a depth, a length, etc) and/or shape (e.g., square, circular, etc). Portions10band12bmay be removed using any process including, inter alia, creating a pattern using a photoresist process (i.e., using photoresist layer4) to create the pattern and using a reactive ion etch process using a standard fluorine-containing RIE chemistry. Portions10band12bare then stripped away to create opening6a. ION implants18are then formed in the exposed portion of the top surface14aof the semiconductor substrate14. The ion implants are formed by exposing the portion of the top surface14aof the semiconductor substrate14to an ion beam16comprising an energy level of about 50 thousand electron volts (keV) to about 1.5 million electron volts (meV). The photoresist layer4over the electrical devices8protects or screens the electrical devices8from the ion implant process.

FIG. 3illustrates the semiconductor structure2ofFIG. 2after all of the photoresist layer4has been removed and a dielectric contact layer20has been formed over the electrical devices8and within opening6a, in accordance with embodiments of the present invention. The photoresist layer4may be removed using an ozone and/or wet etching process. Note that although the dielectric contact layer20illustrated inFIG. 3only comprises one dielectric layer, the dielectric contact layer20may comprise a plurality of dielectric layers. The dielectric contact layer20may comprise any dielectric insulating material including, inter alia, oxide (e.g., silicon dioxide, doped silicon dioxide, undoped silicon dioxide, etc), silicon nitride, boro-phospho-silicate glass, borosilicate glass, phosphosilicate glass, or any combination thereof. The dielectric contact layer20may be deposited over the electrical devices8and within opening6ausing any technique including, inter alia, a chemical vapor deposition process, a TEOS deposition process, a plasma deposition process, etc. The dielectric contact layer20comprises portions20a. . .20e.

FIG. 4illustrates the semiconductor structure2ofFIG. 3after a second photoresist layer22has been formed, in accordance with embodiments of the present invention. Portions of the photoresist layer22have been removed resulting in a exposed portions20aand20bof dielectric layer20. The removed portions of the photoresist layer22were patterned and removed using a photolithography process. The photolithography process used to pattern and remove the portions22aand22bof the photoresist layer comprises the use of a second mask for patterning. The second mask used to pattern the photoresist layer22may comprise an opposite pattern from the first mask used to pattern the photoresist layer4ofFIG. 1. Alternatively, the second mask used to pattern the photoresist layer22may comprise a same pattern as the first mask used to pattern the photoresist layer4ofFIG. 1but a polarity of the photoresist layer4may comprise an opposite polarity from a polarity of the photoresist layer22.

FIG. 5illustrates the semiconductor structure2ofFIG. 4after the portions20aand20bof the dielectric contact layer20have been removed, in accordance with embodiments of the present invention. The removed portions20aand20bresult in the formation of openings24aand24b. The openings24aand24bare located over the electrical devices8. After portions24aand24bhave been removed, a small portion of the dielectric contact layer20still remains over and in contact with electrical devices8. The small portion of the dielectric contact layer20still remaining over and in contact with electrical devices8may comprise a thickness T1selected from a range of about 250 nanometers (nm) to about 2000 nm.

FIG. 6illustrates the semiconductor structure2ofFIG. 5after the photoresist layer22has been removed, in accordance with embodiments of the present invention. The photoresist layer22may be removed using an ozone and/or wet etching process. Portions21a,21b, and21cof a top surface21of dielectric layer20are all coplanar.

FIG. 7illustrates the semiconductor structure2ofFIG. 6after portions20cand20dof the dielectric layer20have been removed, in accordance with embodiments of the present invention. Portions20cand20dmay be removed using chemical-mechanical process. Removing the portions20cand20dof the dielectric layer20results in a planer top surface21of dielectric layer20.

FIG. 8illustrates an algorithm describing a process for forming the semiconductor structure2ofFIG. 7, in accordance with embodiments of the present invention. In step800, a semiconductor structure is provided. The semiconductor structure comprises a semiconductor substrate (e.g., semiconductor substrate14ofFIG. 1), a BOX layer (e.g., BOX layer12ofFIG. 1) formed over and in contact with a top surface of the semiconductor substrate, and an SOI layer (e.g., SOI layer11ofFIG. 1) formed over and in contact with a surface of the BOX layer. The SOI layer comprises STI structures (e.g., STI structure10ofFIG. 1) formed between a plurality of electrical devices (e.g., electrical devices8ofFIG. 1). In step802, a first photoresist layer (e.g., photoresist layer4ofFIG. 1) is formed over entire surfaces of the STI structures and over the plurality of electrical devices. In step804, first portions of the first photoresist layer existing between each active device of the plurality of electrical devices are removed (e.g., simultaneously). In step808, portions of the STI structures and portions of the BOX layer existing below the removed portions of the first photoresist layer are removed. The removed portions of the portions of the STI structures and the BOX layer result in the formation of openings (e.g., trenches, opening6aofFIG. 2, etc) formed through the STI structures and the BOX layer. The openings are formed over portions of the top surface of the semiconductor substrate. The openings result in the portions of the top surface of the semiconductor substrate becoming exposed within the openings. In step810, (i.e., after step808is executed), ion implants (e.g., ion implant18ofFIG. 1) are formed within the exposed portions of the semiconductor substrate (i.e., below each of the openings). In step814, all remaining portions of said first photoresist layer are removed (e.g., simultaneously). In step818, a dielectric layer(s) (e.g., dielectric layer20ofFIG. 3) is formed over the electrical devices and within the openings. In step820, a second photoresist layer is formed (e.g., photoresist layer22ofFIG. 4) over the dielectric layer. In step824, first portions of the second photoresist layer existing over the plurality of electrical devices are removed (e.g., simultaneously). The aforementioned step824results in second portions of second photoresist layer remaining over portions of the dielectric layer within the openings. In step828, first portions of the dielectric layer existing over the electrical devices are removed (e.g., simultaneously). In step832, second portions of the second photoresist layer are removed (e.g., simultaneously). In step834, second portions of the dielectric layer are removed (e.g., simultaneously) resulting a formation of a planar top surface of the dielectric layer (e.g., top surface21INFIG. 7).