According to the present disclosure, a semiconductor device includes a semiconductor substrate, a first metal layer provided above the semiconductor substrate, a second metal layer provided above the first metal layer and containing Ni as a material and a third metal layer provided above the second metal layer and containing Cu or Ni as a material, wherein the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and the third metal layer is harder than the first metal layer.

BACKGROUND OF THE INVENTION

Field

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background

JP 2018-37684 A discloses a structure of a surface electrode of a power semiconductor device. The surface electrode is provided with a first Cu layer having a Vickers hardness of 200 to 350 Hv, containing Cu as a main component, and having been formed by electroless plating. A second Cu layer is laminated on the first Cu layer, the second Cu layer being softer than the first Cu layer, having a Vickers hardness of 70 to 150 Hv, containing Cu as a main component, and having been formed by electroless plating. A Cu wire is bonded to the second Cu layer.

In JP 2018-37684 A, for reducing damage to a semiconductor chip at the time of wire bonding, two electroless Cu plating layers are laminated as a surface electrode. Generally, in electroless Cu plating, it is necessary to increase the impurity concentration in order to increase the Vickers hardness. However, when the impurity concentration is increased, there is a possibility that voids due to impurities are generated to make it difficult to increase the Vickers hardness. Therefore, damage to the semiconductor chip may not be reduced sufficiently.

SUMMARY

The present disclosure has been made to solve the problem described above, and it is an object of the present disclosure to provide a semiconductor device and a method for manufacturing the semiconductor device, which can reduce damage to a semiconductor substrate.

The features and advantages of the present disclosure may be summarized as follows.

According to an aspect of the present disclosure, a semiconductor device includes a semiconductor substrate, a first metal layer provided above the semiconductor substrate, a second metal layer provided above the first metal layer and containing Ni as a material and a third metal layer provided above the second metal layer and containing Cu or Ni as a material, wherein the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and the third metal layer is harder than the first metal layer.

According to an aspect of the present disclosure, a method for manufacturing a semiconductor device includes forming a first metal layer above a semiconductor substrate, forming a second metal layer that contains Ni as a material above the first metal layer by plating, and forming a third metal layer that contains Cu or Ni as a material above the second metal layer, wherein the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and the third metal layer is harder than the first metal layer.

Other and further objects, features and advantages of the disclosure will appear more fully from the following description.

DESCRIPTION OF EMBODIMENTS

A semiconductor device and a method for manufacturing the semiconductor device according to each embodiment will be described with reference to the accompanying drawings. Components identical or corresponding to each other are indicated by the same reference characters, and repeated description of them is avoided in some cases.

First Embodiment

FIG.1is a cross-sectional view of a semiconductor device100according to a first embodiment. The semiconductor device100is, for example, a power semiconductor device such as an insulated gate bipolar transistor (IGBT). The semiconductor device100includes a semiconductor substrate. InFIG.1, the semiconductor substrate has a range from the base layer3to the collector layer8.

The semiconductor substrate has a first-conductivity-type drift layer1between an upper surface and a back surface opposite to the upper surface. A first-conductivity-type carrier storage layer2is provided on the upper surface side of the drift layer1. A second-conductivity-type base layer3is provided on the upper surface side of the carrier storage layer2. A first-conductivity-type emitter layer5and a second-conductivity-type contact layer6are provided on the upper surface side of the base layer3. An active trench10and a dummy trench13are formed in the semiconductor substrate. The active trench10penetrates the emitter layer5. the base layer3, and the carrier storage layer2from the upper surface of the semiconductor substrate to reach the drift layer1. A gate electrode11is formed on the inner wall of the active trench10via a gate insulating film12.

A buffer layer7is provided on the back surface side of the drift layer1. A second-conductivity-type collector layer8is provided on the back surface side of the buffer layer7. A collector electrode9is provided on the back surface of the semiconductor substrate.

A first metal layer20is provided on the upper surface of the semiconductor substrate. An interlayer insulating film4having an opening for exposing the semiconductor substrate is provided between the semiconductor substrate and the first metal layer20. The first metal layer20is electrically connected to the semiconductor substrate through the opening of the interlayer insulating film4. The first metal layer20is an emitter electrode. A second metal layer21is provided on the first metal layer20.

The second metal layer21contains Ni as a material. Ni may be the main component of the second metal layer21. A third metal layer22containing Cu or Ni as a material is provided on the second metal layer. The third metal layer22may be mainly composed of Cu. The second metal layer21is harder than the third metal layer22. The third metal layer22is harder than the first metal layer20.

A method for manufacturing the semiconductor device100according to the present embodiment will be described. First, each semiconductor layer illustrated inFIG.1is formed in the semiconductor substrate. Next, the first metal layer20is formed on the semiconductor substrate. Then, the second metal layer21is formed on the first metal layer20by plating. The second metal layer21is formed by, for example, electroless NiP plating. Subsequently, the third metal layer22containing Cu or Ni as a material is formed on the second metal layer21. The third metal layer22is formed by, for example, electrolytic Cu plating. Next, the collector electrode9is formed on the back surface of the semiconductor substrate. Alternatively, the collector electrode9may be formed before the formation of the third metal layer22. For example, the collector electrode9may be formed after the formation of the first metal layer20, and then the second metal layer21may be formed.

A wire or solder is bonded to the third metal layer22. The semiconductor device100is electrically connected to the outside through the wire or solder. In the present embodiment, the hard second metal layer21is disposed under the third metal layer22. This enables a reduction in damage to the semiconductor substrate at the time of wire bonding or solder bonding. Further, the soft first metal layer20is disposed under the second metal layer21. Hence the first metal layer20serves as a buffer material, thus enabling a further reduction in damage to the semiconductor substrate. The Vickers hardness of the second metal layer21is preferably 400 Hv or more.

The second metal layer21may contain P as an impurity. That is, the second metal layer21may be an electroless NiP plating layer. At this time, the Vickers hardness of the second metal layer21is, for example, 600 to 1300 Hv. By the electroless NiP plating, the Vickers hardness of the second metal layer21can be made to be 600 Hv or more even in consideration of variations. It has been confirmed that in the case of adding P to Ni as an impurity, voids do not increase even when the ratio of P is increased. Further, forming the second metal layer21by electroless plating can facilitate impurity implantation. Therefore, it is possible to facilitate an increase in Vickers hardness.

The second metal layer21may be formed by a method except for the electroless NiP plating when the Vickers hardness can be made to be 400 Hv or more. For example, the second metal layer21may be formed by electrolytic Ni plating. Generally, in the electrolytic Ni plating, a Vickers hardness of 200 to 500 Hv is obtained.

When the second metal layer21is a plating layer, the Vickers hardness can be increased more than when the second metal layer21is a sputtering electrode mainly composed of Ni. Note that the Vickers hardness of an Ni electrode formed by sputtering is generally 100 Hv or less.

The third metal layer22is, for example, an electrolytic Cu plating layer. The Vickers hardness of the third metal layer22is, for example, 100 to 300 Hv. Generally, impurities are easily mixed in the electroless Cu plating.

Therefore, there is a possibility that voids due to impurities are generated. In contrast, in the electrolytic Cu plating, the mixing of impurities can be reduced, so that the voids in the Cu plating can be reduced. Reducing the voids in the electrode enables improvement in reliability of the heat cycle, power cycle, and the like. Note that the Vickers hardness of the third metal layer22on the outermost surface need not be high. There is thus no need to inject large amounts of impurities into the third metal layer22by electroless Cu plating. The third metal layer22may be formed by electroless Cu plating when the amount of impurities can be adjusted.

Ni may be the main component of the third metal layer22when the second metal layer21is harder than the third metal layer22. By making the second metal layer21to be a plating layer having high Vickers hardness and mainly composed of Ni, it is possible to facilitate satisfying the relationship that the second metal layer21is harder than the third metal layer22. Hence it is possible to facilitate reducing damage to the semiconductor device100at the time of wire bonding.

The structure of the surface electrode of the present embodiment can be applied to a semiconductor device in addition to the IGBT. The semiconductor device100may be, for example, a diode, a reverse-conducting (RC)-IGBT, or a metal-oxide-semiconductor field-effect transistor (MOSFET).

The semiconductor substrate may be made with a wide-bandgap semiconductor. The wide-bandgap semiconductor is, for example, silicon carbide, gallium nitride-based material, or diamond. According to the present embodiment, the voids in the electrode can be reduced. Therefore, even when the semiconductor substrate is formed of a wide-bandgap semiconductor and operates at a high temperature, the reliability of the heat cycle can be improved.

These modifications can be appropriately applied to semiconductor devices and methods for manufacturing the semiconductor devices according to embodiments below. Meanwhile, for the semiconductor devices and the methods for manufacturing the semiconductor devices according to the embodiments below, dissimilarities with the first embodiment will mainly be explained as they have many similarities with the first embodiment.

Second Embodiment

FIG.2is a cross-sectional view of a semiconductor device101according to a second embodiment. The structure of the surface electrode of the semiconductor device101is different from that of the semiconductor device100. The other structure is the same as that of the semiconductor device100. The semiconductor device101includes a barrier metal layer23provided between the semiconductor substrate and the first metal layer20. The barrier metal layer23is electrically connected to the semiconductor substrate through the opening of the interlayer insulating film4. The barrier metal layer23is harder than the first metal layer20.

With this configuration, the semiconductor substrate and the surface electrode can be favorably brought into contact with each other, and the electrical characteristics can be stabilized. Further, even when the first metal layer20is crushed at the time of wire bonding, damage to the semiconductor substrate can be reduced.

FIG.3is a cross-sectional view of a semiconductor device102according to a modification of the second embodiment. In the semiconductor device101. the barrier metal layer23has been provided on the entire surface of the IGBT cell. Alternatively, as illustrated inFIG.3, a fourth metal layer24. which is a buried electrode layer, may be provided in the opening of the interlayer insulating film4. The fourth metal layer24electrically connects the semiconductor substrate and the first metal layer20. The fourth metal layer24is formed of, for example, tungsten.

Third Embodiment

FIG.4is a cross-sectional view of a semiconductor device103according to a third embodiment. The semiconductor device103is different from the semiconductor device100in including an antioxidant film25provided on the third metal layer22. The other structure is the same as that of the semiconductor device100. For example, a benzotriazole component is used for the antioxidant film25. In wire bonding or solder bonding, it is desirable to remove the antioxidant film25by formic acid reflow or the like.

The surface of the third metal layer22mainly composed of Cu is oxidized easily. According to the present embodiment, the oxidation of the third metal layer22can be prevented, and the wire bonding property and the solder bonding property can be improved. This makes it possible to perform wire bonding or solder bonding without applying excessive energy to the semiconductor device103. Thus, damage to the semiconductor substrate can be reduced.

FIG.5is a cross-sectional view of a semiconductor device104according to a modification of the third embodiment. In the semiconductor device104. a wire26penetrates the antioxidant film25and is electrically connected to the third metal layer22. The wire26contains Cu as a material, for example. When the antioxidant film25is a thin film, the wire may be bonded penetrating the antioxidant film25while the antioxidant film25remains unremoved. This can eliminate the need for a step of reducing a chip such as formic acid reflow, thereby cutting the process cost.

Fourth Embodiment

FIG.6is a cross-sectional view of a semiconductor device105according to a fourth embodiment. The semiconductor device105includes an adhesion layer27, which brings the second metal layer21and the third metal layer22into close contact with each other, between the second metal layer21and the third metal layer22. The other structure is the same as that of the semiconductor device100. The adhesion layer27is formed of, for example. Ti, TiW, W, Ta, TaN, or Mo. The adhesion layer27is formed by, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD).

According to the present embodiment, with the second metal layer21and the third metal layer22adhering to each other, the energy of wire bonding can be transmitted efficiently. Therefore, the bonding is possible without applying excessive energy to the semiconductor substrate, and damage to the semiconductor substrate can be reduced.

Instead of the adhesion layer27. an Au layer may be provided between the second metal layer21and the third metal layer22. The second metal layer21is mainly composed of Ni and is thus easily oxidized in the manufacturing process. The Au layer can prevent the oxidation of the second metal layer21. Accordingly, variations in the electrical characteristics of the surface electrode can be prevented.

Fifth Embodiment

FIG.7is a cross-sectional view of a semiconductor device106according to a fifth embodiment. The semiconductor device106includes a second-conductivity-type well region14at a boundary between a cell region and a termination region. A reduced surface field (RESURF) region15is provided on the upper surface side of the termination region. A gate wiring17is provided on the well region14. A field oxide film16is provided on the RESURF region15. A first protective film18is formed so as to cover the field oxide film16and the gate wiring17. A second protective film19is formed on the upper surface of the first protective film18.

The second protective film19is provided on a part of the upper surface of the first metal layer20in the cell region and covered with the second metal layer21. The second protective film19is, for example, a resin layer. Due to the heat insulation effect of the second protective film19, heat transfer to the first metal layer20at the time of wire bonding can be prevented. Therefore, the first metal layer20can be prevented from being crushed.

The second protective film19is disposed, for example, over the entire cell region. The placement of the second protective film19is not limited thereto.FIG.8is a plan view of a semiconductor device106aaccording to a modification of the fifth embodiment.

The second protective film19may be provided only directly below the region subjected to wire bonding.

Sixth Embodiment

FIG.9is a perspective view of a semiconductor device107according to a sixth embodiment.FIG.10is a cross-sectional view taken along a line A-B ofFIG.9. InFIG.9. the first metal layer, the second metal layer, and the third metal layer are omitted. The semiconductor device107is a MOSFET. In the semiconductor device107, a first-conductivity-type epitaxial layer28is provided on the upper surface side of a first-conductivity-type semiconductor substrate33. A second-conductivity-type well layer29is provided on the upper surface side of the epitaxial layer28. A first-conductivity-type source layer30is partially disposed in the well layer29.

An interlayer insulating film31partially opened is provided on the upper surface of the epitaxial layer28. A gate electrode32and a gate insulating film34disposed between the gate electrode32and the upper surface of the epitaxial layer28are provided in the interlayer insulating film31.

A plurality of openings are formed in the interlayer insulating film31in a dot shape in a plan view. The first metal layer35is electrically connected to the source layer30through a plurality of openings of the interlayer insulating film31. The first metal layer35is a source electrode. A second metal layer21. which is a plating layer mainly composed of Ni, is provided on the upper surface of the first metal layer35. A third metal layer22, which is a plating layer mainly composed of Cu, is disposed on the upper surface of the second metal layer21. As in the first embodiment, the second metal layer21, the third metal layer22, and the first metal layer35are formed in decreasing order in hardness.

Unevenness is formed on the upper surface of the third metal layer22so as to correspond to the openings of the interlayer insulating film31. This minute unevenness improves the bonding property of the wire or solder. It is thus possible to perform the bonding without applying excessive energy to the semiconductor device107, and to reduce damage to the semiconductor substrate.

The openings of the interlayer insulating film31are not limited to the dot shape but may be a lattice shape.

Seventh Embodiment

FIG.11is a cross-sectional view of a semiconductor device108according to a seventh embodiment. The semiconductor device108includes a base plate37. A ceramic substrate38having an electrode pad40is bonded to the upper surface of the base plate37by solder39. A semiconductor chip41is bonded to the upper surface of the ceramic substrate38by the solder39. The semiconductor chip41has a collector pad43on the back surface and a gate pad42and an emitter pad44on the upper surface.

Each of the gate pad42and the emitter pad44is formed of the first metal layer, the second metal layer, and the third metal layer described in the first to sixth embodiments. The wire26is electrically connected to the third metal layer. The wire26contains Cu, for example, as a material. The wire26may be mainly composed of Cu. The electrode pad40is mainly composed of Cu, for example. The gate pad42and the emitter pad44are connected to the electrode pad40through the wire26.

In general, Cu bonding is stronger than Al bonding. Therefore, the use of the Cu bonding can improve the resistance to the power cycle. Note that the ceramic substrate38and the semiconductor chip41may be bonded not only by the solder39but also by an Ag or Cu sinter material.

Eighth Embodiment

FIG.12is a cross-sectional view of a semiconductor device109according to an eighth embodiment. The semiconductor device109is, for example, an IGBT module. The semiconductor device109includes an insulating sheet47, a heat spreader46provided on the upper surface of the insulating sheet47. and a semiconductor chip41bonded to the upper surface of the heat spreader by solder39. The semiconductor chip41has a collector pad43on the lower surface and a gate pad42and an emitter pad44on the upper surface.

Each of the gate pad42and the emitter pad44is formed of the first metal layer, the second metal layer, and the third metal layer described in the first to sixth embodiments. In the present embodiment, the solder39is provided on the third metal layer. A lead frame48, which is a main terminal, is bonded to the emitter pad44by the solder39. A lead frame49, which is a control terminal, is bonded to the gate pad42by the solder39. A mold resin45is provided so as to expose a part of each of the lead frames48,49and cover the semiconductor chip41.

By the solder bonding, damage to the semiconductor chip41can be reduced more than wire bonding. Further, the heat radiation performance of the semiconductor chip41can be improved, and the current density can be increased.

Therefore, the semiconductor device109can be reduced in size.

Ninth Embodiment

FIG.13is a cross-sectional view of a semiconductor device110according to a ninth embodiment. The semiconductor device110is different from the semiconductor device100in that three metal layers are also formed on the back surface side of the semiconductor substrate. The other structure is the same as that of the semiconductor device100. The semiconductor device110includes a fifth metal layer50provided under a semiconductor substrate, a sixth metal layer51provided under the fifth metal layer50and containing Ni as a material; and a seventh metal layer52provided under the sixth metal layer51and containing Cu or Ni as a material. The Vickers hardness of the sixth metal layer51is 400 Hv or more. The sixth metal layer51is harder than the seventh metal layer52. and the seventh metal layer52is harder than the fifth metal layer50.

The fifth metal layer50is a collector electrode. The sixth metal layer51is a plating layer. Ni may be the main component of the sixth metal layer51. The seventh metal layer52is, for example, a plating layer. The seventh metal layer52may be mainly composed of Cu.

With such a structure of the back electrode, heat radiation performance can be improved, and current density can be improved. Hence the device can be reduced in size. In addition, stresses in the plurality of metal layers cancel each other out, thus enabling a reduction in the warpage of the chip. Therefore, void defects on the back surface can be reduced.

Meanwhile, technical features explained in each embodiment may be appropriately combined to use.

In the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure, the hard second metal layer can reduce damage to the semiconductor substrate due to wire bonding or the like.

Obviously many modifications and variations of the present disclosure are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the disclosure may be practiced otherwise than as specifically described.

The entire disclosure of a Japanese Patent Application No. 2021-168314. filed on Oct. 13, 2021 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.