Solid-state imaging device having wiring layer which includes lamination of silicide layer in order to reduce wiring resistance, and manufacturing method for the same

A silicide layer (first silicide layer, second silicide layer) is laminated on top laminate surfaces of gates of a transmission transistor and a reset transistor, respectively. Each of the first silicide layer and the second silicide layer respectively formed on each of the gates extends in a direction along the main surface of the semiconductor substrate among at least a portion of a plurality of image pixels, connecting gates with one another among the respective image pixels. On the other hand, a signal outputter is not in contact with any silicide layers, has the top laminate surface that is covered with an insulating layer, and is connected with other transistors via a metal wiring layer.

CLAIM OF PRIORITY

This application claims the benefit of Japanese Patent Application No. JP 2007-010457, filed on Jan. 19, 2007 and Japanese Application No. JP 2007-261208, filed on Oct. 4, 2007, the disclosures of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to a solid-state imaging device and a manufacturing method for the same, in particular to a structure of an image pixel of a MOS-type solid-state imaging device and a forming method thereof.

(2) Description of the Related Art

MOS-type solid-state imaging devices which are used in digital cameras and the like can be driven with a lower power consumption compared to CCD-type solid-state imaging devices. Also, a sensor region of the MOS-type solid-state imaging device and a peripheral circuit region thereof for driving the sensor region can be manufactured based on the same CMOS processing. Thus, their manufacturing processes can be more simplified, and semiconductor devices can be more integrated, compared to the CCD-type solid-state imaging devices. The structure of the conventional MOS-type solid-state imaging devices will be described using an example of an amplification-type MOS-type solid-state imaging device.

As shown inFIG. 1, the sensor region of the MOS-type solid-state imaging device includes a plurality of image pixels60(FIG. 1shows 4 of the image pixels60). Each image pixel60includes a photodiode61and 4 transistors (a transmission transistor62, an amplifier transistor63, a selection transistor64, and a reset transistor65) as its main components.

In the plurality of image pixels60that are two-dimensionally arranged along the direction of the paper surface ofFIG. 1, gates of the transmission transistors62are connected with one another by lines L61. Likewise, gates of reset transistors65are connected with one another by lines L62, and gates of selection transistors64are connected with one another by lines L63. Also, in the plurality of image pixels60two-dimensionally arranged along the direction of the paper surface ofFIG. 1, sources of the selection transistors64are connected with one another by lines L64.

Among structural components of the image pixel60shown inFIG. 1, the transmission transistor62and its peripheral regions will be described usingFIG. 2A, and the reset transistor65and its peripheral regions will be described usingFIG. 2B.

As shown inFIG. 2A, at the transmission transistor62and the peripheral regions thereof, an n-type signal charge accumulator602is formed in a p-well (p-type device formation region)601on a semiconductor substrate600. Also, a p-type surface shield layer606and an n-type signal outputter605are formed in a vicinity of the surface of the p-well601. The n-type signal charge accumulator602is a component comprising part of a photodiode and accumulates signal charges generated by receiving incident light.

The p-type surface shield layer606is formed in an upper area with respect to the n-type signal charge accumulator602(the p-well601surface side) in order to reduce dark current. The n-type signal outputter605is formed away from both the n-type signal charge accumulation602and the p-type surface shield layer606. Also, an insulating layer603is formed on a region between the p-type surface shield layer606and the n-type signal outputter605of the p-well601. Further, a gate604of the transmission transistor62for controlling transmission of signal charge is provided on the insulating layer603. Additionally, the gate604, the signal outputter605, and the surface shield layer606are covered with an insulating layer621.

Also, an STI (Shallow Trench Isolation) region607is formed adjacent to the surface shield layer606(inFIG. 2A, adjacent to the left side of the surface shield layer606). It should be noted the STI region607is formed in regions separating adjacent image pixels60and the like.

As shown inFIG. 2B, at the reset transistor65and peripheral regions thereof, a source611and a drain612of the reset transistor65are formed apart from each other in a vicinity of one of the surfaces of the p-well601formed on the semiconductor substrate600. Also, the insulating layer603is formed above a region between the source611and the drain612of the semiconductor substrate, and the gate613is provided on the insulating layer603. The source611, the drain612, and the gate613are covered with the insulating layer621.

As shown inFIG. 1, in the sensor region of the MOS-type solid-state imaging device, the transistors62to65of the plurality of image pixels60are connected to one another, respectively, by such as the lines L61to L64. Wiring lengths can be extremely long, and are likely to cause an increase in wiring resistance if the wirings are to be extended to connect with gates and the like. The following describes conventional techniques developed in attempts to solve this problem, with reference toFIG. 3.

As shown inFIG. 3, the conventional MOS-type solid-state imaging devices are structured in such a manner that metal wirings633ato633care provided on each of the gate604of the transmission transistor62and the gate613of the reset transistor65, and the gates604and613are connected with the metal wirings633aand so on with contact plugs641, respectively. The conventional MOS-type solid-state imaging devices attempt to reduce wiring resistance by adopting such a structure. However, as shown inFIG. 3, an insertion of the metal wirings633ato633ccauses a problem, that is, an increase in a light path length, a distance D0, from the on-chip lens631to the signal charge accumulator602via a color filter632. Since the distance D0directly affects the sensitivity of the MOS-type solid-state imaging device, with the conventional MOS-type solid-state imaging devices, it is difficult to reduce wiring resistance while also preventing deterioration of the sensitivity. Additionally, as shown inFIG. 3, the sensitivity deteriorates due to a decrease in a light receivable angle θ0also.

Various attempts have been made to solve the above-mentioned problem. For example, one technique uses a salicide method in laminating a silicide layer on gates, a signal outputter and the like and connects the image pixels60with this silicide layer in order to reduce resistance. Another technique attempts to reduce resistance by forming a silicide layer at peripheral circuits with similar use of the salicide method (for examples, see Japanese laid-open patent application publication No. 2001-111022 and Japanese Patent No. 3782297).

However, when adopting the techniques proposed by the above-mentioned documents (Japanese laid-open patent application publication No. 2001-111022 and Japanese Patent No. 3782297), it is difficult to reduce electrical resistance among the image pixels and prevent the deterioration of playback images at the same time. Specifically, with the technique proposed as a first embodiment of the above-mentioned document (Japanese laid-open patent application publication No. 2001-111022), no silicide layer is formed at a sensor region where image pixels are formed, and thus, wiring resistance cannot be reduced sufficiently. Accordingly, in view of the sensitivity characteristics, it is difficult to adopt the technique proposed as the first embodiment of the above-mentioned document (Japanese laid-open patent application publication No. 2001-111022).

On the other hand, according to a second embodiment of the above-mentioned document (Japanese laid-open patent application publication No. 2001-111022) and the other document mentioned above (Japanese Patent No. 3782297), a silicide layer is formed on everything except for a light receiver of a photoelectric converter in a pixel cell, including drains of transmission transistors. Consequently, when adopting the technique proposed by these, leakage current is likely to occur, and thus, noise is likely to occur due to aliasing output from the signal outputter605.

A junction depth of the signal outputter605and the source611of the reset transistor65is 0.1 [μm] to 0.5 [/μm], and this could be reduced down to approximately 0.05 [μm] to 0.1 [μm] if a pixel size is further miniaturized. Abstracts of 1995 IEEE-IEDM (International Electron Devices Meeting) pp. 449-452 contain a description that cobalt silicide spikes reach a length of 20 [nm] to 100 [nm]. Here, as shown inFIG. 4, a junction between an impurity diffusion layer and a silicon substrate is destroyed due to a cobalt silicide spike, causing leakage current to occur from the impurity diffusion layer to the silicon substrate.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, No. 1, JANUARY 1999 pp. 117-123 contains descriptions on mechanism caused by cobalt silicide, such as that cobalt diffuses from a cobalt silicide layer due to a thermal process, increasing leakage current, and the leakage current value has a distribution within a region, in addition to that the cobalt silicide spikes reach a length of 20 [nm] to 100 [nm].

In other words, according to the techniques proposed by the second embodiment of the above-mentioned document (Japanese laid-open patent application publication No. 2001-111022) and the other document (Japanese Patent No. 3782297), a silicide layer is laminated on the signal outputter605and the source611of the reset transistor65as well as on the gate604of the transmission transistor62and the gate613of the reset transistor65. As a result, a metal-semiconductor compound, the component of the silicide layer, penetrates to the p-well (p-type device formation region)601or even if it does not penetrate to the p-well601, it shortens the distance to the p-well601. Consequently, leakage current increases and has a distribution with in the region.

Due to an increase in the number of pixels for cameras in recent years, when practically used, the signal outputter605and the source611of the reset transistor65electrically connected to the signal outputter605are placed in each of several million to ten million pixels in a pixel array. Also, when the peripheral temperature of the several million to ten million sources611of the reset transistors65, which are electrically connected to the several million to ten million of signal outputters605and the signal outputters605, is 60[° C.], leakage current indicates a distribution as shown inFIG. 5under the condition, for example, that a total area of the signal outputters605and the sources611of the reset transistors65is 0.48[μm2].

FIG. 5shows a case where a sample time for transmitting a signal downstream for an output to eliminate noise is 4.88 [μsec] and a saturation number of electrons of the signal charge accumulator602is 3000. In this case, 90 electrons or more, which approximately account for 3[%] of the saturation number corresponding to a dynamic range of a playback image, that is, image pixels with a leakage current of approximately 300 [fA] or more in the maximum applicable temperature, become visible as a noise in the playback image. As can be seen from the above, the techniques proposed by the second embodiment of the above-mentioned document (Japanese laid-open patent application publication No. 2001-111022) and the other document mentioned above (Japanese Patent No. 3782297) suffer deterioration of playback images due to leakage current generation as a tradeoff for gaining an advantage of reducing wiring resistance by forming silicide layers.

SUMMARY OF THE INVENTION

The present invention was conceived in view of the above problems, and aims to provide a solid-state imaging device which achieves high-sensitivity characteristics by preventing deterioration of playback images due to leakage current and suppressing a distance from an on-chip lens to the surface of the semiconductor substrate.

In order to achieve the stated aim, the present prevention provides a solid-state imaging device in which a plurality of image pixels are disposed in a direction along a main surface of a semiconductor substrate, each of the plurality of image pixels including the following: a signal charge accumulator operable to accumulate a signal charge generated by a photoelectric conversion; a transmission transistor disposed adjacent to the signal charge accumulator; and a reset transistor, a source of which is connected to a drain of the transmission transistor,

And, in the solid-state imaging device in accordance with the present invention, one of (a) the drain of the transmission transistor and (b) a point on a signal path connecting the drain of the transmission transistor and the source of the reset transistor functions as a signal outputter. Also, in the solid-state imaging device in accordance with the present invention, a gate of the transmission transistor is in contact with a first compound layer composed of metal and a semiconductor, and a gate of the reset transistor is in contact with a second compound layer composed of metal and a semiconductor.

In the solid-state imaging device of the present invention, gates of transmission transistors of at least two of the image pixels are electrically connected with each other by the first compound layer which extends in the direction along the main surface, and gates of reset transistors of the at least two of the image pixels are electrically connected with each other by the second compound layer which extends in the direction along the main surface.

In the solid-state imaging device of the present invention, the signal outputter (i) is out of contact with the first compound layer, the second compound layer, and any other compound layer composed of metal and a semiconductor, (ii) has a top surface that is covered with an insulating layer, and (iii) is electrically connected with a metal wiring layer so as to be connected with other transistors (transistors other than the transmission transistor and the reset transistor), the metal wiring layer being disposed on the insulating layer.

It should be noted that the above-mentioned “top surface” is a top surface in the laminating direction.

Also, it should be noted that the above phrase “out of contact” means “not in direct contact”.

In the solid-state imaging device of the present invention, each of the gates of the transmission transistor and the reset transistor is in contact with the first compound layer and the second compound layer (compound layers composed of metal and a semiconductor), and the first and the second compound layers are formed in one piece, respectively, so as to connect the gates of at least a portion of the plurality of the image pixels. As stated above, the gates of the transmission transistors and the reset transistors are connected with each other by the first compound layer and the second compound layer, respectively. Accordingly, the solid-state imaging device in accordance with the present invention, unlike the conventional solid-state imaging devices shown inFIGS. 2 and 3, does not need to have a structure in which the gates are connected by metal wiring layers formed corresponding to the gates via the insulating layer and the gates of the image pixels are electrically connected via the metal wiring layers. Consequently, the solid-state imaging device of the present invention can reduce electric resistance among the gates while achieving a shorter distance from the on-chip lens to the surface of the semiconductor substrate, compared to the conventional solid-state imaging device shown inFIGS. 2 and 3. Also, the solid-state imaging device of the present invention achieves high sensitivity characteristics since the light receiving angle is not likely to decrease.

Additionally, in the solid-state imaging device in accordance with the present invention, the signal outputter is not in contact with any compound layers (any compound layers composed of metal and a semiconductor, including the first and the second compound layers). This prevents penetration of a metal-semiconductor compound to a p-well (p-type device formation region), preventing generation of leakage current as a result. Here, when the peripheral temperature of the several million to ten million signal outputters and the sources of the reset transistors, which are electrically connected to the signal outputters is 60[° C.], leakage current shows a distribution as shown inFIG. 5(indicated by a dashed line) in a case where, for example, a total area of the signal outputters and the sources of the reset transistors is 0.48 [m2]. And, the number of the image pixels with a leakage current of approximately 300 [fA] or more, where the leakage current becomes visible as a noise in a playback image, decreases compared to when a silicide layer is formed on the signal outputter. Consequently, the MOS-type solid-state imaging device in accordance with the present invention is less likely to cause noise due to leakage current, suppressing deterioration of playback images.

Accordingly, the MOS-type solid-state imaging device prevents playback images from deteriorating due to leakage current while achieving the high sensitivity characteristics.

Here, the source of the reset transistor charges a floating diffusion layer to a reset level, and the signal outputter converts electrons accumulated at the signal charge accumulator to a voltage change of the floating diffusion layer. In other words, neither of these outputs current, and thus, it is not necessary to laminate a silicide layer thereover to lower resistance.

The solid-state imaging device of the present invention can adopt a structure in which the source of the reset transistor (i) is out of contact with the first compound layer, the second compound layer, and any other compound layer (composed of metal and a semiconductor), (ii) has a top surface that is covered with an insulating layer, and (iii) is electrically connected with a metal wiring layer disposed on the insulating layer, and the source of the reset transistor and the signal outputter are electrically connected.

Also, the solid-state imaging device of the present invention can adopt a structure in which the drain of the reset transistor is in contact with a third compound layer composed of metal and a semiconductor.

Additionally, the solid-state imaging device of the present invention can adopt a structure in which a peripheral circuit region including a plurality of transistors is positioned at a periphery of where the plurality of image pixels are disposed in the direction along the main surface of the semiconductor substrate, and sources, drains, and gates of the plurality of transistors are in contact with a fourth compound layer composed of metal and a semiconductor so as to be electrically connectable.

In addition, the solid-state imaging device of the present invention can adopt a structure in which the first compound layer and the second compound layer are formed using a salicide method.

Also, the solid-state imaging device of the present invention can adopt a structure in which the plurality of image pixels are grouped into a plurality of pixel groups each composed of two or more adjacent image pixels, and in at least one of the plurality of pixel groups, image pixels thereof share one signal outputter.

Additionally, the solid-state imaging device of the present invention can adopt a structure in which a shield layer is disposed on the signal charge accumulator, the shield layer being capable of reducing dark current, and the shield layer (i) is out of contact with the first compound layer, the second compound layer, and any other compound layer composed of metal and a semiconductor and (ii) has a top surface that is covered with an insulating layer.

Also, in order to achieve the stated aim, the present invention provides a manufacturing method for a solid-state imaging device, which comprise the following steps (a) to (g):

(a) a signal charge accumulator forming step of performing, on a semiconductor substrate, formation of a signal charge accumulator which accumulates a signal charge generated by a photoelectric conversion;

(b) a transistor forming step of performing, on the semiconductor substrate, formation of (i) a transmission transistor adjacent to the signal charge accumulator and (ii) a reset transistor, a source of which is connected to a drain of the transmission transistor;

(c) a first insulating layer forming step of forming a first insulating layer so as to cover (i) a main surface of the semiconductor substrate, (ii) the transmission transistor, and (iii) the reset transistor;

(d) a sidewall forming step of forming, by removing the first insulating layer by etching except for a region above the signal charge accumulator, a sidewall on a lateral surface of a gate of the transmission transistor and on both lateral surfaces of a gate of the reset transistor, the lateral surface of the gate of the transmission transistor being on a drain side of the transmission transistor;

(e) a second insulating layer forming step of forming a second insulating layer so as to cover (i) the main surface, (ii) the transmission transistor, and (iii) the reset transistor;

(f) an opening forming step of forming, on the second insulating layer, an opening above the gate of the transmission transistor and above the gate and the drain of the reset transistor; and

(g) a compound layer forming step of forming, through the openings, a compound layer composed of metal and a semiconductor on the gate of the transmission transistor and on the gate and the drain of the reset transistor.

With the above steps, the manufacturing method in accordance with the solid-state imaging device in accordance with the present invention enables manufacturing of a solid-state imaging device which achieves high-sensitivity characteristics by preventing deterioration of playback images due to leakage current and suppressing a distance from an on-chip lens to the surface of the semiconductor substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The following describes the best mode for carrying out the invention using an embodiment with reference to drawings. Note that the embodiment in the following description is only an example used to provide a clear explanation on a structure of the present invention and effects and advantages obtained therefrom, and the present invention is not limited to this except for its characterizing feature.

1. Overall Structure of MOS-Type Solid-State Imaging Device

An overall structure of a MOS-type solid-state imaging device1in accordance with the present embodiment is described usingFIG. 6. The MOS-type solid-state imaging device shown inFIG. 6is, for example, an image input device used for such as a digital still camera or a digital movie camera.

As shown inFIG. 6, the MOS-type solid-state imaging device1of the present embodiment includes a sensor region21and a peripheral circuit. The sensor region21includes multiple image pixels10. The peripheral circuit includes a vertical selection circuit22, an image signal retention circuit23, a horizontal selection circuit24, and a load circuit25and drives the image pixels10of the sensor region21.

The sensor region21includes the multiple image pixels10which are two-dimensionally disposed on a semiconductor substrate along a main surface thereof. Note that whileFIG. 6does not show the semiconductor substrate, the direction along the main surface of the semiconductor substrate corresponds with the direction along the paper surface.

As shown in a portion surrounded by a two-dot chain line inFIG. 6, the image pixel10is an amplification-type unit pixel and each has an identical circuit configuration. The image pixel10includes a photodiode11, 4 transistors (a transmission transistor12, an amplifier transistor13, a selection transistor14, and a reset transistor15) and the like.

Among the image pixels10arranged in a horizontal direction ofFIG. 6, gates of the transmission transistors12are connected with one another by lines L1, gates of the reset transistors15are connected with one another by lines L2, and gates of the selection transistors14are connected with one another by lines L3. Also, among the image pixels10arranged in a vertical direction, drains of the selection transistors14are connected with one another by lines L4. A configuration of each of the lines L1to L4will be described later.

The photodiode11is a device portion having a photoelectric conversion function which generates signal charge in accordance with intensity of incident light received by each image pixel10. It should be noted that one end of the photodiode11is earthed and the other end is connected with a source of the transmission transistor12. The transmission transistor12is a device portion for transferring the signal charge generated by the photoelectric conversion function of the photodiode11to a drain of the transmission transistor12itself. The drain of the transmission transistor12functions as a detection unit and is connected with a gate of the amplifier transistor13and a source of the reset transistor15.

The reset transistor15is a device portion for resetting the signal charge accumulated in the drain of the transmission transistor12in a predetermined cycle. The drain of the reset transistor15is connected with the power supply voltage VDD. The amplifier transistor13is a device portion for outputting the signal charge accumulated in the drain of the transmission transistor12when the selection transistor14is turned ON according to signals received from a vertical shift resistor22and so on. The drain of the amplifier transistor13is connected with the power supply voltage VDD, and the source of the amplifier transistor13is connected with the drain of the selection transistor14.

Among the four transistors12to15in the pixel10, the amplifier transistor13performs a signal amplification function for the signal charge, and the other transistors12,14and15each perform a switching function.

The vertical selection circuit22and the horizontal selection circuit24are dynamic circuits. They sequentially output drive pulses (switching pulses) to the image pixels10or to the pixel signal retention circuit23according to a signal received from the load circuit25.

Also, the image signal retention circuit23includes switching devices for each column (not shown in figures), and they are sequentially turned ON by receiving pulses from the horizontal selection circuit24. The load circuit25is a circuit for applying a power supply voltage, a timing pulse, and so on to the above-described vertical selection circuit22and the horizontal selection circuit24.

In the MOS-type solid-state imaging device1, in accordance with the above-mentioned structure, the signal charge generated by the photoelectric conversion is read from the image pixel10at a position where a row selected by the vertical selection circuit22intersects with a column whose image signal retention23is turned on.

2. Driving Operations of MOS-Type Solid-State Imaging Device

In the image pixel10, the signal charge generated by the photodiode11with use of the photoelectric conversion is temporarily accumulated in the drain (signal outputter) of the transmission transistor12. The accumulated signal charge is output to the gate of the amplifier transistor13when the transmission transistor12is turned ON based on instruction signals received from the vertical selection circuit22. The amplifier transistor13amplifies the signal charge input to the gate thereof and outputs it to the source of the selection transistor14.

The transmission transistor12performs ON/OFF operations based on the instruction signals received from the vertical selection circuit22, and the reset transistor15eliminates the signal charge accumulated in the signal outputter in a predetermined cycle to reset the accumulation status of the signal charge in the signal outputter.

In the multiple image pixels10of the MOS-type imaging device1, each of the pixels10accumulates the signal charge generated by the photoelectric conversion. In one of these pixels10, which is selected by the selection transistor14in each image pixel10and the image signal retention circuit23based on the instruction signals received from the vertical selection circuit22and the horizontal selection circuit24, the signal charge is amplified and output to the line L4.

3. Structure of Main Part in Image Pixel10

In the following, a description will be given on the transmission transistor12and its peripheral regions, and the reset transistor15and its peripheral regions in the structure of the image pixel10of the MOS-type solid-state imaging device1in accordance with the present embodiment, with reference toFIGS. 7A and 7B.

As shown inFIG. 7A, at the transmission transistor12and the peripheral regions thereof, an n-type signal charge accumulator102, a p-type surface shield layer106, and an n-type signal outputter105are formed in correspondence with a p-well101included in a semiconductor substrate100. Here, the signal charge accumulator102is a component comprising a portion of the photodiode11(seeFIG. 6) and accumulates signal charges generated from input light.

The surface shield layer106is formed in an upper region with respect to the signal charge accumulator102inFIG. 7Ain order to reduce dark current. Also, the signal outputter105is formed away from both the signal charge accumulator102and the surface shield layer106. In a region adjacent to the surface shield layer106, a STI (Shallow Trench Isolation) region107is formed. It should be noted the STI region107is formed in regions separating adjacent image pixels10and the peripheral regions of the photodiodes11except for the transmission transistors12. Here, even higher separation effect can be obtained if an injection layer for separation is formed below the STI regions (not shown in figures).

A gate oxide film103is formed on the surface of the p-well101in a region from a point between the signal outputter105and the surface shield layer106to a point above the signal outputter105such that a part of the gate oxide film partially covers the signal outputter105. The gate104of the transmission transistor12(hereinafter, referred to as “transmission gate”) is laminated on the gate oxide film103.

A silicide layer201(a first compound layer composed of metal and semiconductor) is laminated on a portion of the upper surface of the transmission gate104. And, the transmission gate104, signal outputter105, and surface shield layer106are covered by an insulating layer121except for the upper surface of the silicide layer201. It should be noted that as shown inFIG. 7A, the signal outputter105is not in contact with the silicide layer, and the upper surface of the signal outputter105is covered by the gate oxide film103and the insulating layer121. It should be also noted that the signal charge accumulator102is not in contact with the silicide layer, either. Here, a junction depth of the signal outputter105is 0.05 [μm] to 0.3 [μm].

Note that the silicide layer201of the present embodiment is formed by, for example, using the salicide (Self Aligned Silicide) method.

As shown inFIG. 7B, at the reset transistor15and peripheral regions thereof, the source111and the drain112of the reset transistor15are formed apart from each other in a vicinity of the surface of the p-well101included in the semiconductor substrate100. A silicide layer (a third compound layer composed of metal and a semiconductor material)203is laminated on a portion of the upper surface of the drain112, and the gate oxide film103is formed on the surface of the p-well101above a region between the source111and the drain112. The gate113of the reset transistor15(hereinafter, referred to as “reset gate”) is laminated on the upper surface of the gate oxide layer103. Here, a junction depth of the source111and the drain112of the reset transistor15is 0.05 [μm] to 0.3 [μm].

A silicide layer (a second compound layer composed of metal and a semiconductor)202is laminated on the surface of the reset gate113. Additionally, the surface of the p-well101is covered by the insulating layer121except for the region, where the silicide layer203is formed, on the drain112, and the region, where the silicide layer202is formed, on the reset gate113.

It should be noted that as shown inFIG. 7B, the upper surface of the source111of the reset transistor15(upper surface of the semiconductor diffusion layer) is not in contact with any silicide layers and covered by the gate oxide layer103and the insulating layer121. The upper surface of the reset gate113is, as mentioned above, in contact with the silicide layer202, and the upper surface of the drain112is in contact with the silicide layer203.

Also, the silicide layers (compound layers composed of metal and a semiconductor)202and203are, for example, formed by using the salicide (Self Aligned Silicide) method.

4. Connection Structure among Image Pixels10of Sensor Region21

The following describes a connection structure among the image pixels10of the sensor region21, referring toFIG. 8. Note thatFIG. 8shows a portion of structural components of four image pixels10that comprise one group in relation to the signal outputter105.

As shown inFIG. 8, each signal charge accumulator102is rectangular in shape with one of the corners thereof taper-cut, and four signal charge accumulators102are arranged in a matrix state. The reset transistor15is formed between two signal charge accumulators102, and the reset gate113(FIG. 8shows the silicide layer202laminated on the reset gate113) is formed laterally penetrating a plurality of the image pixels10. In other words, the reset gates113in the image pixels10are connected with the silicide layer202laminated thereon.

The source111and the drain112of the reset transistor15are formed in a rectangular shape, the longitudinal sides thereof paralleling the lateral sides of the paper. Of these, the drain112has the silicide layer203laminated over a partial upper surface thereof. The drain112of the reset transistor15, which is also not shown in figure, is connected with the power supply voltage VDD by the silicide layer203laminated thereon.

Additionally, the transmission gate104is formed substantially in parallel to the reset gate113. As mentioned above, the silicide layer201is laminated over a portion of the upper surface of the transmission gate104. The respective transmission gates104, which are arranged in the horizontal direction of the paper surface, of the image pixels10are also connected with the silicide layer201laminated thereon.

The MOS-type solid-state imaging device1of the present embodiment adopts a structure in which two signal charge accumulators102arranged in a matrix state share one signal outputter105. That is to say, the transmission gate104corresponding to the signal charge accumulator102at the upper right of the paper surface and the transmission gate104corresponding to the signal charge accumulator102at the lower left are formed to correspond to the one signal outputter105. With this structure, the signal charges of the four signal charge accumulators102are output to the one signal outputter105based on the input signals to the transmission gates104.

Also, as shown inFIG. 8, the MOS-type solid-state imaging device1of the present embodiment has a structure such that the signal outputter105and the source111of the reset transistor15are both not in contact with any silicide layer, and are in contact with each other via contact plugs141and142by the metal wiring133. It should be noted that while being schematically shown inFIG. 8, the metal wiring133is formed with different layers sandwiching an inter-layer insulating film. Also, as shown inFIG. 6and the like, the MOS-type solid-state imaging device1includes the plurality of the image pixels10in a matrix state, andFIG. 8shows a portion thereof.

As described above, the MOS-type solid-state imaging device1of the present embodiment is structured in such a manner that the silicide layer201is laminated on a portion of the transmission gate104, and the transmission gates104between the adjacent image pixels10are connected by the silicide layer201. Also, on the upper surface of the reset gate113, the silicide layer202is laminated, and the reset gates113between the adjacent image pixels10are connected with the silicide layer202.

With the above structure, wiring resistance can be reduced in the MOS-type solid-state imaging device1in accordance with the present embodiment. Additionally, with the MOS-type solid-state imaging device1, it is not necessary to increase the number of metal wiring layers for connecting the transmission gates104with one another and for connecting the reset gates113with one another. Accordingly, a distance from an on-chip lens to the photodiode11on the surface of the silicon substrate can be shortened, achieving high sensitivity characteristics. This is described in the following withFIG. 9. It should be noted that inFIG. 9, the semiconductor substrate100is omitted and only a portion from the p-well101up is shown.

As shown inFIG. 9, in the MOS-type solid-state imaging device1of the present embodiment, the transmission gates104and the reset gates113are connected among themselves, respectively, as a result of the image pixels10being connected to the silicide layers201and202laminated thereon. Consequently, the number of the metal wirings133aand133bbetween the on-chip lens131and the surface of the p-well101can be reduced by at least one layer, compared to the conventional MOS-type solid-state imaging device shown inFIGS. 2 and 3.

Consequently, with the MOS-type solid-state imaging device1, a distance D1from the on-chip lens131to the surface of the p-well101can be reduced by a difference in the numbers of the metal wiring layers compared to a distance D0inFIG. 3. Accordingly, a light receivable angle θ1becomes larger than the light receivable angle θ0inFIG. 3, achieving the high sensitivity characteristics as a result.

Also, in the MOS-type solid-state imaging device1, no silicide layer is in contact with either of the upper surfaces of the signal outputter105or the reset transistor15. Consequently, with the MOS-type solid-state imaging device1, it is less likely to have problems such as crystal faults due to implantation of ion in high concentration and penetration of the metal-semiconductor compound into the p-well101, compared to when a silicide layer is formed on the upper surface of the signal outputter105.

Here, when the peripheral temperature of the several million to ten million signal outputters105and the sources111of the reset transistors15, which are electrically connected to the signal outputters105is 60[° C.], leakage current shows a distribution as shown inFIG. 10(indicated by a dashed line) in a case where, for example, a total area of the signal outputters105and the sources11of the reset transistors15is 0.48 [μm2]. And, the number of the image pixels with a leakage current of approximately 300 [fA] or more, where the leakage current becomes visible as a noise in a playback image, decreases compared to when a silicide layer is formed (a distribution indicated by a solid line). Consequently, the MOS-type solid-state imaging device1in accordance with the present embodiment is less likely to cause leakage current and noise due to aliasing output from the signal outputter105.

Additionally, the source111of the reset transistor15charges a floating diffusion layer to a reset level, and the signal outputter105converts electrons accumulated at the signal charge accumulator102to a voltage change of the floating diffusion layer. In other words, neither of these outputs current, and thus, it is not necessary to laminate a silicide layer thereover to lower resistance.

Accordingly, the MOS-type solid-state imaging device1prevents playback images from deteriorating due to leakage current while achieving the high sensitivity characteristics.

The following describes an embodiment of a manufacturing method of the solid-state imaging device1in accordance with the present invention with reference toFIGS. 11A to 16B.FIGS. 11A,12A,13A,14A,15A, and16A show a formation region of the transmission transistor12; andFIGS. 11B,12B,13B,14B,15B and16B show a formation region of the reset transistor15.

First, as shown inFIGS. 11A and 11B, a p-well1010and an STI (Shallow Trench Isolation) region107are included in a semiconductor substrate100of an n-type or a p-type. While, in the present embodiment, as shown inFIG. 11A, the STI region107is formed only in a region where the transmission transistor12is to be formed, the STI region can be formed in regions separating the image pixels10and peripheral regions of the photodiodes11except for the transmission transistor12. Also, higher separation effect can be obtained if an injection layer for separation is formed below the STI regions (not shown in figures).

Next, as shown inFIG. 12A, the signal charge accumulator102is formed in the p-well1011included in the semiconductor substrate100. It should be noted that the reference numeral of the p-well1010in theFIGS. 11A and 11Bis changed to the p-well1011in theFIGS. 12A and 12Bin consideration of the formation of the signal charge accumulator102. Similar changes are made in the following processes.

Following the above, as shown inFIG. 13A, after a silicon oxide film and polysilicon are laminated on the surface of the p-well1011on the semiconductor substrate100, etching is performed to form the gate oxide film103and a transmission gate preparatory layer1040in the region where the transmission transistor12is to be formed. Also, as shown inFIG. 13B, in a region where the reset transistor15is to be formed, the gate oxide film103and a reset gate preparatory layer1130are formed in a similar manner.

Next, as shown inFIG. 14A, the surface shield layer106is formed, and the signal outputter105, which is the drain of the transmission transistor12, is formed. Also, as shown inFIG. 14B, the source111of the reset transistor15and a drain preparatory region1120of the reset transistor15are formed.

Subsequently, as shown inFIGS. 15A and 15B, an insulating preparative layer1210is formed so as to cover the upper surface of the p-well101included in the semiconductor substrate100, the transmission gate preparative layer1040, and the reset gate preparative layer1130. And, as shown inFIGS. 16A and 16B, an opening is formed for the insulating preparative layer1210by etching the region except for the upper surface of the signal discharge accumulator102. This leaves the insulating layer121on the upper surface of the signal charge accumulator102.

Also, as shown inFIGS. 16A and 16B, the insulating layer121remains as a side wall on a right lateral surface (lateral surface on the drain side) of the transmission gate preparative layer1040and on both lateral surfaces of the reset gate preparative layer1130.

Next, again, an insulating preparative layer is formed so as to cover the upper surface of the p-well101included in the semiconductor substrate100, the transmission gate preparative layer1040and the reset gate preparative layer1130. After that, as shown inFIGS. 17A and 17B, an opening is provided above the transmission gate preparative layer1040, the reset gate preparative layer1130, and the drain preparative region1120of the reset transistor15. It should be noted that the insulating layer121is left above the signal charge accumulator102, the signal outputter105, and the source111of the reset transistor15.

Next, at the status shown inFIGS. 17A and 17B, the exposed surfaces of the transmission gate preparative layer1040, the reset gate preparative layer1130, and the drain preparative region1120of the reset transistor15are silicided, forming the silicide layers201,202, and203(seeFIGS. 7A and 7B).

The MOS-type solid-state imaging device1which is manufactured through the above processing is structured such that the surfaces of the signal charge accumulator102, the signal outputter105, and the source111of the reset transistor15are not silicided, which prevents generation of leakage current. At the same time, a metal-semiconductor compound (silicide layers201,202, and203) is laminated on the transmission gate104, the reset gate113, and the drain112of the reset transistor15, lowering connection resistance.

The above-mentioned embodiment only provides an example to describe the structure of the present invention and the effects obtained therewith. Accordingly, the present invention is not restricted to the above-mentioned embodiment except for its characterizing aspects. For instance, as shown inFIG. 8, a layout adopted by the MOS-type solid-state imaging device1of the above-mentioned embodiment can be appropriately changed, allowing an adoption of various structures other than the structure in which two signal charge accumulators102share one signal outputter105.

Also, while the number of the layers of the metal wirings133is shown as two (layers133aand133b) inFIG. 9, this is only schematic, and thus the number of the layers of the metal wirings133is not limited to this.

Further, in the above-mentioned embodiment, every image pixel10of the sensor region21is configured to have the structure of the present invention, that is, the silicide layers201,202, and203(silicide layer) disposed at the above-mentioned corresponding regions. However, since not all the image pixels10need to have the above-mentioned structure, a portion of the image pixels10can have the above-mentioned structure. For instance, silicide can be used or not used in accordance with regions of the sensor region21. Also, in the present embodiment, a silicide layer is defined as a metal-semiconductor compound, as a silicon substrate is adopted as a semiconductor substrate. However, the present invention does not limit the metal-semiconductor compound to silicide.

Further, metal used to form a silicide layer is not limited to cobalt, and can be other metal materials such as nickel.