MEMORY CONTROL DEVICE, INFORMATION PROCESSING APPARATUS, AND MEMORY CONTROL METHOD

Accesses to a memory divided into a plurality of units of operation are controlled. First and second units of operation from among the plurality of units of operation constitute a memory mirror. A reception circuit receives a plurality of read requests including bank identification information corresponding to both a first bank included in a first unit of operation and a second bank included in a second unit of operation, respectively. A determination circuit determines an access target of each read access so that the plurality of read accesses based on the plurality of read requests are made to the first and second units of operation alternately. The control circuit controls each read request so that each read access is made to a unit of operation determined as the access target.

DESCRIPTION OF EMBODIMENTS

Hereinafter, the embodiments will be explained in detail by referring to the drawings.

In a conventional memory mirroring configuration that uses a single MAC, when the MAC has received a plurality of read requests, it continuously accesses one physical rank as long as there is not an uncorrectable error. In a conventional memory mirroring configuration that uses two MACs, when the interconnection unit has received a plurality of read requests, it always transmits the read requests to both of the MACs. And both of the MACs make accesses to physical ranks that are connected respectively to them.

Also, in both of the memory mirroring configurations, using a single MAC and using two MACs, it is desirable that the limitation of tRC of DIMM be met when accesses are made to the same bank continuously in memory accesses based on the closed page mode. tRC is a limitation that defines time intervals between issuance of an active command to a bank of a DIMM from a MAC and another issuance of an active command to the same bank. Also in the open page mode, it is desirable that the limitation of tRC be met when page misses occur continuously in memory accesses to the same bank.

FIG. 3illustrates command issuance intervals in a case when read accesses are made to different banks in the closed page mode. InFIG. 3, “DIMM clock” represents an operation clock signal of a DIMM, “command” represents a command issued to the DIMM from the MAC. “ACT” represents an active command, and “RDA” represents a read command that accompanies auto precharge.

“Physical rank ID” represents identification information of a physical rank output from the MAC to a DIMM, and “bank ID” represents bank identification information. “Data” represents READ data read from the bank corresponding to a bank ID in the physical rank specified by a physical rank ID.

In such a case, active commands “ACT” are issued to the respective banks corresponding to bank IDs “B0” through “B4” at short time intervals without being influenced by the tRC limitation.

FIG. 4illustrates command issuance intervals in a case when read accesses are continuously made to the same bank in the closed page mode. In such a case, active commands “ACT” are issued to a particular bank that corresponds to bank ID “B0” at time intervals defined by tRC. Because read accesses to the same bank are influenced by the tRC limitation as described above, intervals of issuing active commands become longer, leading to longer random access cycles, which is problematic.

In recent Double Data Rate 3 SDRAMs (DDR3 SDRAMs), for example, tRC is set to be approximately 30 cycles in terms of the DIMM clock. Accordingly, when accesses are made to the same bank continuously, the intervals of issuing active commands become approximately 30 cycles. Because one access occupies the data bus for four cycles, the data bus is used only for four cycles out of thirty four cycles. Accordingly, when all accesses made in the closed page mode are assumed to be made to the same bank, the use efficiency of the bus decreases to approximately one eighth.

Because read accesses to the same bank are influenced by the tRC limitation as described above, intervals of issuing active commands becomes longer, leading to a decrease in the use efficiency of the bus, which is problematic.

Also, the above problems occur not only in information processing apparatuses including a DIMM divided into a plurality of physical ranks, but also in information processing apparatuses having a memory divided into a plurality of units of operation, which are different from physical ranks.

Accordingly, it is desired that the use efficiency of a bus be improved when read accesses based on the same bank identification information occur continuously in a memory mirroring configuration.

FIG. 5illustrates a hardware configuration example of a memory control device501according to an embodiment.FIG. 6is a flowchart illustrating an example of memory access control performed by the memory control device501.

The memory control device501illustrated inFIG. 5includes a reception circuit511, a determination circuit512, and a control circuit513, and controls accesses to a memory that has been divided into a plurality of units of operation. The first and second units of operation from among the above plurality of units of operation constitute a memory mirror.

The reception circuit511receives a plurality of read requests including bank identification information corresponding to both a first bank and a second bank that are included in the first and second units of operation, respectively (step601).

The determination circuit512determines the access target for each read access so that a plurality of read accesses based on the above plurality of read requests are made to the first and second units of operation alternately (step602).

The control circuit513controls each read request so that each read access is made to the unit of operation determined as the access target (step603).

According to the memory control device501of the above configuration, the use efficiency of a bus can be improved when read accesses based on the same bank identification information occur continuously in a memory mirroring configuration.

FIG. 7illustrates a hardware configuration example of a server, which is an information processing apparatus (computer) including the memory control device501illustrated inFIG. 5. The server inFIG. 7includes Central Processing Unit (CPU) modules701-1through701-4and input/output (I/O) controllers702-1and702-2.

The server inFIG. 7includes DIMMs703-1through703-K (K is a positive integer), DIMMs704-1through704-K, DIMMs705-1through705-K, and DIMMs706-1through706-K. Each “DIMM703-i” (i=1 through K) represents one or more DIMMs. This is applied also to “DIMM704-i”, “DIMM705-i”, and “DIMM706-i”.

The CPU module707-1includes CPUs (processors)711-1through711-M (M is a positive integer), routers712-1and712-2, a system controller713, and MACs714-1through714-K. The system controller713includes Last Level Cache (LLC). The DIMMs703-1through703-K are connected to the MACs714-1through714-K, respectively.

The CPU module701-2includes CPUs721-1through721-M, routers722-1and722-2, a system controller723, and MACs724-1through724-K. The system controller723includes LLC. The DIMMs704-1through704-K are connected to the MACs724-1through724-K, respectively.

The CPU module701-3includes CPUs731-1through731-M, routers732-1and732-2, a system controller733, and MACs734-1through734-K. The system controller733includes LLC. The DIMMs705-1through705-K are connected to the MACs734-1through734-K, respectively.

The CPU module701-4includes CPUs741-1through741-M, routers742-1and742-2, a system controller743, and MACs744-1through744-K. The system controller743includes LLC. The DIMMs706-1through706-K are connected to the MACs744-1through744-K, respectively.

The I/O controller702-1includes Direct Memory Access Controllers (DMACs)751-1through751-L (L is a positive integer) and a system controller752. The I/O controller702-1also includes interfaces753-1through753-3. The devices707-1through707-3are connected to the interfaces753-1through753-3, respectively.

The I/O controller702-2includes DMACs761-1through761-L, a system controller762, and interfaces763-1through763-3. The devices708-1through708-3are connected to the interfaces763-1through763-3, respectively.

The routers712-2,722-2,732-1, and742-1are connected to each other, and CPU modules701-1through701-4can communicate with each other. Also, the router732-2and the system controller752are connected, and the CPU module701-3and the I/O controller702-1can communicate with each other. Similarly, the router742-2and the system controller762are connected, and the CPU module701-4and the I/O controller702-2can communicate with each other.

In a memory mirroring configuration using a single MAC, each of the MACs714-i,724-i,734-i, and744-i(i=1 through K) corresponds to the memory control device501illustrated inFIG. 5. Each MAC receives a memory access request as, for example, described below, and controls accesses to DIMMs.

(1) A memory access request made by a CPU as the requesting source in the same CPU module

(2) A memory access request made by a CPU as the requesting source in a different CPU module

(3) A memory access request made by a DMAC as the requesting source in an I/O controller

In some cases, the MAC714-1in the CPU module701-1, for example, receives a memory access request as described below.

(1) Memory access requests made by the CPUs721-1through721-M in the CPU module701-2

(2) Memory access requests made by the CPUs731-1through731-M in the CPU module701-3

(3) Memory access requests made by the CPUs741-1through741-M in the CPU module701-4

(4) Memory access requests made by the DMACs751-1through751-L in the I/O controller702-1

(5) Memory access requests made by the DMACs761-1through761-L in the I/O controller702-2

Note that the number of CPU modules is not limited to four, and may be an integer equal to or greater than one. The number of I/O controllers is not limited to two, and may be an integer equal to or greater than one. Also, the number of devices connected to I/O controllers is not limited to three, and may be an integer equal to or greater than one.

Next, by referring toFIGS. 8 through 10, explanations will be given for configurations and operations of a MAC in a case when a memory mirroring configuration using a single MAC has been employed in the server illustrated inFIG. 7.

The memory mirroring configuration inFIG. 8includes a MAC801and a DIMM802. The MAC801corresponds to each of the MACS714-i,724-i,734-i, and744-i(i=1 through K) illustrated inFIG. 7. The DIMM802corresponds to each of the DIMMs703-i,704-i,705-i, and706-i(i=1 through K) illustrated inFIG. 7.

The MAC801includes a request queue811, an address decoder812, a busy check unit813, a request selection unit814, a command generation unit815, and a command issuance unit816. The MAC801also includes a WRITE data reception unit817, an Error Correcting Code (ECC) generation unit818, a WRITE data output unit819, a READ data output unit820, an ECC check unit821, a READ data reception unit822, and a request generation unit823.

The DIMM802includes physical ranks831-1through831-4. Among them, the physical ranks831-1and831-2are of a pair that constitutes a memory mirror, and the physical ranks831-3and831-4are of another pair that constitutes the memory mirror.

The physical rank831-1includes banks832-1through832-N (N is an integer equal to or greater than 1), and each of the physical ranks831-2through831-4also includes N banks similarly to the physical rank831-1. Also, the number of physical ranks is not limited to four, and may be an even number equal to or greater than two.

FIG. 9illustrates a configuration example of the address decoder812illustrated inFIG. 8. The address decoder812illustrated inFIG. 9includes a decoding unit901, a rank specification unit902, a rank table903, and a selection unit904.

The decoding unit901decodes the address included in a memory access request obtained from a requesting source, and generates a column ID, a row ID, a bank ID, and a logical rank ID. A column ID, a row ID, a bank ID, and a logical rank ID are pieces of identification information for a column, a row, a bank, and a logical rank. The decoding unit901outputs a bank ID to the rank table903, and also outputs the logical rank ID to the rank specification unit902and the rank table903.

The rank specification unit902generates two physical rank IDs, which are pieces of identification information of two physical ranks of a pair corresponding to a logical rank ID, and outputs these physical rank IDs to the selection unit904.

Rank table903stores an entry for each combination between a bank ID and a logical rank ID. Each entry includes a PR, which is a physical rank ID, and update control information IM. “LR0” is a logical rank ID corresponding to the pair of the physical ranks831-1and831-2, and “LR1” is a logical rank ID corresponding to the pair of the physical ranks831-3and831-4. “B0” through “BN−1” are pieces of bank identification information for N banks in each of the physical ranks831-i(i=1 through 4).

A PR is the ID of one of the two physical ranks of a pair that corresponds to a logical rank ID, and indicates a physical rank of an access destination for a read access. The rank table903outputs to the selection unit904the physical rank ID of an entry that corresponds to a combination of the bank ID and the logical rank ID output from the decoding unit901.

Each time a read access based on the same combination of a bank ID and a logical rank ID is made, PR on the rank table903is updated to the physical rank ID of the other one of the physical ranks constituting the pair. Update control information IM is information indicating whether or not an updating of PR is permitted, and indicates the permission to update unless an uncorrectable error occurs in READ data.

When an uncorrectable error occurs in READ data in a read access, the PR corresponding to the combination of the bank ID and the logical rank ID is fixed to the physical rank ID of the other physical rank that constitutes a pair together with the physical rank in which the error has occurred. When this is performed, update control information IM is updated to information that prohibits updating so that the PR will not be updated in the future.

When the write flag included in a memory access request from a requesting source indicates a write access, the selection unit904selects and outputs two physical rank IDs from the rank specification unit902. When the write flag does not indicate a write access, i.e., when it indicates a read access, the selection unit904selects and outputs a physical rank ID from the rank table903.

FIG. 10is a flowchart illustrating an example of memory access control performed by the MAC801inFIG. 8.

First, the request queue811receives a memory access request from a requesting source (step1001). Then, the address decoder812decodes the address included in the received memory access request, and generates access information used for accessing the DIMM802(step1002). This access information includes a column ID, a row ID, a bank ID, and a physical rank ID. The access information includes two physical rank IDs for a write access and one physical rank ID for a read access.

Next, the busy check unit813checks whether or not the DIMM802is busy (step103). When the DIMM802is not busy, the request selection unit814selects a memory access request having the highest priority from among a plurality of memory access requests in the request queue811(step1004). The request selection unit814determines whether the selected memory access request is a write request or a read request on the basis of the write flag included in the selected memory access request (step1005).

When the memory access request is a write request (YES in step1005), the request selection unit814transmits a write data request to the requesting source (step1010). Then, the requesting source transmits the WRITE data to the MAC801(step1011).

The WRITE data reception unit817receives the WRITE data from the requesting source after a prescribed number of cycles elapsed after it transmitted a write data request (step1012). The ECC generation unit818generates an ECC of the WRITE data (step1013), and the WRITE data output unit819outputs to the DIMM802the WRITE data to which the ECC has been added (step1014).

The command generation unit815generates a write command used for accessing the DIMM802(step1006), and the command issuance unit816issues a write command to the DIMM802(step1007). The command issuance unit816also outputs the access information to the DIMM802.

The DIMM802receives the write command and the access information from the command issuance unit816(step1008), and receives the WRITE data from the WRITE data output unit819(step1009). Thereafter, the DIMM802stores the WRITE data in the access destination specified by the access information.

When the memory access request is a read request (NO in step1005), the request selection unit814reports to the address decoder812that a read access will be made in accordance with the read request.

In accordance with this report, the address decoder812refers to the entry that corresponds to the combination of the bank ID and the logical rank ID output from the decoding unit901from among entries on the rank table903. When update control information IM of that entry is indicating the permission to update, the address decoder812updates the PR of the entry to the physical rank ID of the other one of the physical ranks that constitute the pair. Thereby, a physical rank different from that of the access destination of the current read access is specified as the access destination of the next read access directed to the same combination of the bank ID and the logical rank ID.

As described above, each time a read access is made to the same combination of the bank ID and the logical rank ID, the physical rank ID of the access destination is updated, and thereby two physical ranks constituting a memory mirror receive read accesses alternately. Accordingly, the use efficiency of the bus can be improved when read accesses based on the same bank ID occur continuously in a memory mirroring configuration.

When update control information IM is indicating the prohibition to update, the address decoder812does not update the PR of the entry.

Next, the command generation unit815generates a read command used for accessing the DIMM802(step1015), and the command issuance unit816issues a read command to the DIMM802(step1016). The command issuance unit816also outputs the access information to the DIMM802.

The DIMM802receives the read command and the access information from the command issuance unit816(step1017), and outputs READ data to the MAC801after a prescribed number of cycles (step1018).

The READ data reception unit822receives the READ data from the DIMM802(step1019). Thereafter, the ECC check unit821checks whether or not the READ data is right on the basis of the ECC that has been added to the READ data (step1020) so as to determine the presence or absence of an error (step1021).

When there are no errors in the READ data (NO in step1021), the READ data output unit820transmits the READ data to the requesting source (step1022).

When there is an error in the READ data (YES in step1021), the ECC check unit821checks whether or not that error is correctable (step1023). When that error is correctable (YES instep1023), the ECC check unit821corrects the error by using the ECC (step1024), and the READ data output unit820transmits the corrected READ data to the requesting source (step1022).

When the error is an uncorrectable error (NO in step1023), the ECC check unit821checks whether or not the read request is a retry request (step1025). A retry request is a request requiring that when an uncorrectable error has occurred in READ data, a read access be made to the other one of the physical ranks constituting the pair.

When the read request is not a retry request (NO in step1025), the ECC check unit821reports to the address decoder812and the request generation unit823that an uncorrectable error has occurred in READ data.

In accordance with this report, the address decoder812refers to the entry that corresponds to the combination of the bank ID and the logical rank ID output from the decoding unit901from among entries on the rank table903. Then, the address decoder812updates update control information IM of that entry to information indicating the prohibition to update. Thereby, the PR of that entry is fixed to the physical rank ID of the other physical rank that constitutes a pair together with the physical rank in which the error has occurred, so that the use of the physical rank in which the error has occurred is prohibited.

Also, the request generation unit823outputs a retry request of the read access to the request queue811in accordance with the report that an uncorrectable error has occurred (step1026). Thereby, the operations in and subsequent to step1001are restarted, and a read access is made to the physical rank other than the physical rank that has been prohibited from being used.

When the read request is a retry request (YES in step1025), the ECC check unit821performs an error process (step1027). In such a case, the MAC801halts the operation because an uncorrectable error occurred in both of the two physical ranks corresponding to the logical rank ID of the read request.

The configurations of the MAC801and the address decoder812illustrated inFIG. 8andFIG. 9are just exemplary, and part of the constituent elements may be omitted or altered in accordance with processes performed by the MAC801. For example, when the check of READ data based on an ECC is not performed, the ECC generation unit818, the ECC check unit821, and the request generation unit823illustrated inFIG. 8may be omitted.

Note that the flowchart inFIG. 10is just exemplary, and some of the processes may be omitted or altered in accordance with the configurations or conditions of the MAC801. For example, when the check of READ data based on an ECC is not performed, the processes insteps1013,1020,1021, and1023through1027inFIG. 10may be omitted.

Next, explanations will be given for a configuration and operations of the interconnection unit in a case when a memory mirroring configuration using two MACs in the server inFIG. 7is employed.

The memory mirroring configuration illustrated inFIG. 11includes an interconnection unit1101, MACs1102-1and1102-2, and DIMMs1103-1and1103-2. The MACs1102-1and1102-2correspond to any two of the following MACs.

(1) Two MACs from among the MACs714-1through714-K illustrated inFIG. 7

(2) Two MACs from among the MACs724-1through724-K illustrated inFIG. 7

(3) Two MACs from among the MACs734-1through734-K illustrated inFIG. 7

(4) Two MACs from among the MACs744-1through744-K illustrated inFIG. 7

Also, the DIMMs1103-1and1103-2correspond to any two of the following DIMMs.

(1) Two DIMMs from among the DIMMs703-1through703-K illustrated inFIG. 7

(2) Two DIMMs from among the DIMMs704-1through704-K illustrated inFIG. 7

(3) Two DIMMs from among the DIMMs705-1through705-K illustrated inFIG. 7

(4) Two DIMMs from among the DIMMs706-1through706-K illustrated inFIG. 7

In such a case, the interconnection unit1101is provided in the system controller713, the system controller723, the system controller733, or the system controller743inFIG. 7. In a memory mirroring configuration using two MACs, the interconnection unit1101corresponds to the memory control device501illustrated inFIG. 5.

The DIMM1103-1includes physical ranks1111-1through1111-4, and the DIMM1103-2includes physical ranks1121-1through1121-4. Among them, the physical rank1111-i(i=1 through 4) and the physical rank1121-iare of a pair that constitutes the memory mirror. In this case, the MACs1102-1and1102-2also operate as a pair that constitutes the memory mirror.

The physical rank1111-1includes banks1112-1through1112-N (N is an integer equal to or greater than 1), and each of the physical ranks1111-2through1111-4also includes N banks similarly to the physical rank1111-1. The physical rank1121-1includes banks1122-1through1122-N, and each of the physical ranks1121-2through1121-4also includes N banks similarly to the physical rank1121-1. Note that the number of physical ranks in each DIMM is not limited to four, and may be an integer equal to or greater than one.

FIG. 12illustrates a configuration example of the interconnection unit1101illustrated inFIG. 11. The interconnection unit1101illustrated inFIG. 12includes a decoding unit1201, a MAC specification unit1202, a MAC table1203, a selection unit1204, a request output unit1205, a request generation unit1206, and a READ data check unit1207.

The decoding unit1201decodes the address included in a memory access request from a requesting source, and generates a bank ID and a logical rank ID. The decoding unit1201outputs the bank ID and the logical rank ID to the MAC table1203.

The MAC specification unit1202generates MAC identification information for the MACs1102-1and1102-2, and outputs these pieces of the MAC identification information to the selection unit1204. The MAC identification information of the MAC1102-1is MAC0, and the MAC identification information of the MAC1102-2is MAC1.

The MAC table1203stores an entry for each combination of a bank ID and a logical rank ID. Each entry includes a PM, which is MAC identification information, and update control information IM.

“LR0” is a logical rank ID corresponding to a pair of the physical ranks1111-1and1121-1, and “LR1” is a logical rank ID corresponding to a pair of the physical ranks1111-2and1121-2. “LR2” is a logical rank ID corresponding to a pair of the physical ranks1111-3and1121-3. “LR3” is a logical rank ID corresponding to a pair of the physical ranks1111-4and1121-4. “B0” through “BN−1” are pieces of bank identification information of N banks included in each of the physical ranks1111-iand1121-i(i=1 through 4).

A PM is MAC identification information of one of the MACs1102-1and1102-2, and indicates a MAC that is an access destination for a read access. The MAC table1203outputs to the selection unit1204the MAC identification information of the entry that corresponds to the combination of the bank ID and the logical rank ID output from the decoding unit1201.

Each PM on the MAC table1203is updated to the MAC identification information of the other one of the MACs that constitute the pair each time a read access is made to the same combination of a bank ID and a logical rank ID. Update control information IM is information indicating whether or not an updating of PMs is permitted, and indicates the permission to update unless an uncorrectable error occurs in READ data.

When the write flag included in a memory access request from a requesting source indicates a write access, the selection unit1204selects and outputs two pieces of MAC identification information from the MAC specification unit1202. When the write flag does not indicate a write access, i.e., when it indicates a read access, the selection unit1204selects and outputs MAC identification information from the MAC table1203.

The request output unit1205outputs a memory access request from a requesting source to a MAC specified by one or two pieces of MAC identification information output from the selection unit1204. Accordingly, a write request is output to both of the MACs1102-1and1102-2, and a read request is output to one of the MACs1102-1and1102-2.

The READ data check unit1207receives, from the MAC1102-1or the MAC1102-2, READ data and determination information indicating whether or not the READ data is normal. A case where READ data is normal corresponds to a case where no errors occurred in the READ data or a case where an error that occurred in the READ data has been corrected. A case where READ data is not normal corresponds to a case where an uncorrectable error occurred in the READ data.

When the received determination information indicates that the READ data is normal, the READ data check unit1207transmits the received READ data to the requesting source.

When the received determination information indicates that the READ data is not normal, the READ data check unit1207updates the update control information IM of the corresponding entry on the MAC table1203to information that prohibits updating. Thereby, the PM of that entry is fixed to the MAC identification information of the MAC connected to the other physical rank that constitutes a pair together with the physical rank in which the error has occurred.

The READ data check unit1207reports to the request generation unit1206that the READ data is not normal. The request generation unit1206generates a retry request in accordance with this report.

FIG. 13is a flowchart illustrating an example of memory access control performed by the interconnection unit1101and the MACs1102-1and1102-2illustrated inFIG. 11.

First, the interconnection unit1101receives a memory access request from a requesting source (step1301). The decoding unit1201decodes the address included in the received memory access request, and generates a bank ID and a logical rank ID. The MAC table1203outputs to the selection unit1204the MAC identification information of the entry that corresponds to the combination of the generated bank ID and the logical rank ID.

The selection unit1204determines whether the request is a write request or a read request on the basis of the write flag included in the received memory access request (step1302).

When the memory access request is a write request (YES in step1302), the selection unit1204outputs, to the request output unit1205, the MAC identification information of the MACs1102-1and1102-2output from the MAC specification unit1202. When the memory access request is a read request (NO in step1302), the selection unit1204outputs, to the request output unit1205, the MAC identification information output from the MAC table1203.

When the memory access request is a write request (YES in step1302), the request output unit1205outputs that write request to both of the MACs1102-1and1102-2(step1303).

The MAC1102-1receives the write request from the request output unit1205(step1306), and performs a write process (step1307). The procedures in a write process are similar to those in steps1006through1014inFIG. 10.

In this write process, the MAC1102-1transmits a write data request to the requesting source, and receives WRITE data from the requesting source. Next, the MAC1102-1generates an ECC for the WRITE data, and outputs to the DIMM1103-1WRITE data to which the ECC has been added. The MAC1102-1generates a write command, and issues that write command to the DIMM1103-1. The DIMM1103-1stores the WRITE data in accordance with the write command.

The MAC1102-2receives the write request from the request output unit1205(step1316), and performs a write process (step1317). The procedure in the write process is similar to that in step1307.

When the memory access request is a read request (NO in step1302), the request output unit1205selects a MAC in accordance with MAC identification information output from the selection unit1204(step1304). Then, the request output unit1205checks whether the MAC identification information indicates the MAC1102-1or the MAC1102-2(step1305).

When the MAC identification information is indicating the MAC1102-1, the request output unit1205outputs the read request to the MAC1102-1(step1308). The MAC1102-1receives the read request from the request output unit1205(step1309), and performs a read process (step1310). The procedures of a read process are similar to those in steps1015through1021and steps1023through1024inFIG. 10.

In this read process, the MAC1102-1generates a read command, and issues that read command to the DIMM1103-1. The DIMM1103-1outputs READ data to the MAC1102-1in accordance with the read command.

The MAC1102-1determines whether or not there are read errors in the READ data on the basis of the ECC added to the READ data. When there are no read errors, the MAC1102-1outputs, to the interconnection unit1101, the READ data and determination information indicating that the READ data is normal (step1311).

When there is an error in the READ data, the MAC1102-1checks whether or not that error is correctable, and, when that error is correctable, corrects the error by using the ECC. Thereafter, the MAC1102-1outputs, to the interconnection unit1101, the corrected READ data and determination information indicating that the READ data is normal.

When the error is an uncorrectable error, the MAC1102-1outputs, to the interconnection unit1101, the READ data and determination information indicating that the READ data is not normal (step1311).

When MAC identification information indicates the MAC1102-2, the request output unit1205outputs the read request to the MAC1102-2(step1312). The MAC1102-2receives the read request from the request output unit1205(step1313), and performs a read process (step1314). The procedure of a read process is similar to that insteps1310. The MAC1102-2outputs, to the interconnection unit1101, the READ data and determination information indicating whether or not the READ data is normal (step1315).

When the request output unit1205has output a read request to the MAC1102-1or1102-2, it refers to an entry corresponding to the combination of the bank ID and the logical rank ID output from the decoding unit1201from among entries on the MAC table1203. When the update control information IM of that entry is indicating the permission to update, the request output unit1205updates the PM of that entry to the MAC identification information of the MAC that is connected to the other of the physical ranks constituting the pair. Thereby, a MAC that is different from the output destination of the current read access is specified as the output destination of the next read access made to the same combination of the bank ID and the logical rank ID.

As described above, each time a read access is made to the same combination of the bank ID and the logical rank ID, the MAC identification information of the output destination is updated so that read accesses are output alternately to the two MACs that constitutes a pair. Thereby, read accesses are alternately made to two physical ranks that constitute a memory mirror. Accordingly, the use efficiency of a bus can be improved when read accesses based on the same bank ID occur continuously in a memory mirroring configuration.

When the update control information IM is indicating the prohibition to update, the request output unit1205does not update the PR of that entry.

The READ data check unit1207receives READ data and the determination information from the MAC1102-1or1102-2(step1318), and checks the received determination information (step1319). When the determination information is indicating that the READ data is normal (YES in step1319), the READ data check unit1207transmits the received READ data to the requesting source (step1320).

When the determination information is indicating that the READ data is not normal, the READ data check unit1207checks whether or not the read request is a retry request (step1321).

When the read request is not a retry request (NO in step1321), the READ data check unit1207refers to the entry that corresponds to the combination of the bank ID and the logical rank ID output from the decoding unit1201, from among entries on the MAC table1203. Then, the READ data check unit1207updates the update control information IM of that entry to information indicating the prohibition to update. Thereby, the PM of that entry is fixed to the MAC identification information of the MAC connected to the other physical rank that constitutes a pair together with the physical rank in which the error has occurred, and the use of the MAC connected to the physical rank in which the error has occurred is prohibited.

The READ data check unit1207reports, to the request generation unit1206, that the READ data is not normal (step1302). On the basis of this report, the request generation unit1206generates a retry request of the read access. Thereby, the operations in and subsequent to step1301are restarted, and a read request to the MAC other than the MAC the use of which has been prohibited is output.

When a read request is a retry request (YES in step1321), the READ data check unit1207performs an error process (step1323). In this case, uncorrectable errors have occurred in both of the two physical ranks that correspond to the logical rank ID of the read request, and accordingly, the operation of the interconnection unit1101is halted.

The configuration of the interconnection unit1101illustrated inFIG. 12is just exemplary, and part of the constituent elements may be omitted or altered in accordance with the processes performed by the interconnection unit1101. For example, when the check of READ data based on an ECC is not performed, the request generation unit1206and the READ data check unit1207illustrated inFIG. 12may be omitted.

Also, the flowchart ofFIG. 13is just exemplary, and some of the processes may be omitted or altered in accordance with the configurations or conditions of the interconnection unit1101. For example, when the check of READ data based on an ECC is not performed, processes in steps1319and1321through1323inFIG. 13may be omitted.

FIG. 14illustrates command issuance intervals in a case when read accesses are continuously made to the same bank in the closed page mode in the memory mirroring configurations illustrated inFIG. 8andFIG. 11. “R0” and “R1” are physical rank IDs of two physical ranks that constitute a memory mirror.

In this case, active commands “ACT” are issued to a particular bank that corresponds to bank ID “B0” in the same physical rank corresponding to “R0” or “R1” at time intervals defined by tRC. However, active commands “ACT” accompanying identical bank IDs “B0” are issued alternately to the physical ranks that correspond to “R0” and “R1”.

This makes it possible to apparently issue active commands “ACT” to the same bank once in about the half of the time interval defined by tRC, improving the use efficiency of a bus to approximately twice that of the case illustrated inFIG. 4. Thereby, the apparent random access cycle in a read access can be reduced to approximately half.

Also in the case of the open page mode, the memory mirroring configurations illustrated inFIG. 8andFIG. 11can improve the use efficiency of a bus when read accesses are continuously made to the same banks.