Metal adhesion layer to promote metal plug adhesion

A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.

BACKGROUND

Metal plugs may be used as contact vias to connect various portions of a semiconductor device (e.g., a source/drain region or epitaxial region, a gate, etc.) to back end of the line (BEOL) metallization layers.

DETAILED DESCRIPTION

To reduce contact resistance between a metal plug and an epitaxial region, a titanium silicide (TiSi) layer may be formed at the bottom of the trench in which the metal plug is to be filled. A titanium silicon nitride (TiSiN) coating (e.g., 2 nanometers) may be used as a metal glue layer to improve adhesion of the metal plug (e.g., cobalt (Co)) to the TiSi layer and to the silicon nitride (SiN) sidewalls of the trench.

However, the TiSiN may suffer from de-wetting from the metal plug. In particular, non-uniform nucleation and uneven coverage of the TiSiN coating may result in poor adhesion with the metal plug and continuity degradation of the TiSiN coating. The poor adhesion and continuity degradation of the TiSiN coating results in voids between the sidewalls of the trench and the metal plug, and results in voids between the bottom layer of the trench and the metal plug. These voids may increase contact resistance of the metal plug, which may decrease the performance of a semiconductor device in which the metal plug is included.

Some implementations described herein provide a thin (e.g., 1-3 nanometers) metal adhesion layer to reduce de-wetting from a metal plug. The metal adhesion layer may be formed on a bottom and a sidewall of a trench (e.g., with or without an intervening TiSiNi layer) prior to formation of the metal plug in the trench. A nitrogen-based plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the nitrogen-based plasma may cause a shift or transformation of the phase composition of the metal adhesion layer from being roughly equally composed of a (111) phase and a (200) phase (or from having less of a (111) phase component than a (200) phase component), to being composed of a (111) dominant phase. As an example, the resulting phase composition of the metal adhesion layer may have a (111) dominant phase in that a ratio between the (111) phase and the (200) phase is between 3:1 and 6:1 or greater.

The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer and the metal plug in that the (111) dominant phase results in a finer-grained micro structure of the metal adhesion layer relative to the (200) phase, results in a crystal structure for the metal adhesion layer that has a higher interfacial nitrogen density relative to the (200) phase, and/or the like. The finer-grained micro structure and the higher interfacial nitrogen density provides a greater quantity of nitrogen atoms to which the metal plug may bond, thereby increasing adhesion between the metal adhesion layer and the metal plug. The increased adhesion between the metal adhesion layer and the metal plug may reduce voids, recesses, and other types of defects in the metal plug, may reduce defects in subsequent processes, and may increase semiconductor manufacturing yields without increasing the complexity of the forming the metal plug.

FIG.1is a diagram of an example environment100in which systems and/or methods described herein may be implemented. As shown inFIG.1, environment100may include a deposition tool102, a plasma tool104, an annealing tool106, a plating tool108, a planarization tool110, and a wafer/die transport device112. The tools and/or devices included in example environment100may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing and/or manufacturing facility, and/or the like.

The deposition tool102is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a semiconductor device. In some implementations, the deposition tool102includes a chemical vapor deposition (CVD) tool, such as an atomic layer deposition (ALD) tool, an epitaxy tool, a metal organic CVD (MOCVD) tool, a plasma-enhanced CVD (PECVD) tool, or another type of CVD tool. In some implementations, the deposition tool102includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the example environment100includes a plurality of types of deposition tools102.

The plasma tool104may include a plasma source that capable of generating a plasma. For example, the plasma tool104includes an inductively coupled plasma (ICP) source, a transformer coupled plasma (TCP) source, or another type of plasma source capable of generating an isotropic plasma, an anisotropic plasma, a partially isotropic plasma, or another type of plasma. In some implementations, the plasma tool104may generate a plasma including an ionized gas that may be used for various semiconductor processes describe herein.

The annealing tool106is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of heating a semiconductor device. For example, the annealing tool106may include a rapid thermal anneal (RTA) tool, a rapid thermal processing (RTP) tool, or another type of annealing tool that is capable of heating a semiconductor device to cause a reaction between two or more materials or gasses, to cause a material to decompose, and/or the like. For example, the annealing tool106may heat a semiconductor device to cause a metal layer on an epitaxial region (e.g., a source region or a drain region) to react and form a metal silicide layer, as described herein.

Plating tool108is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of plating a semiconductor device with one or more metals. Plating, and particularly electroplating (or electro-chemical deposition), is a process by which conductive structures are formed on a substrate (e.g., a semiconductor wafer, a semiconductor device, and/or the like). Plating may include applying a voltage across an anode formed of a plating material and a cathode (e.g., a substrate). The voltage causes a current to oxidize the anode, which causes the release of plating material ions from the anode. These plating material ions form a plating solution that travels through a plating bath toward the substrate. The plating solution reaches the substrate and deposits plating material ions into trenches, vias, interconnects, and/or other structures in and/or on the substrate. In some implementations, plating tool108may include a copper electroplating tool, a cobalt electroplating tool, an aluminum electroplating tool, a nickel electroplating tool, a titanium electroplating tool, a tin electroplating tool, a compound material or alloy (e.g., tin-silver, tin-lead, and/or the like) electroplating tool, and/or an electroplating tool for one or more other types of conductive materials, metals, and/or the like. In some implementations, plating tool108may form a metal plug in a trench, as described herein.

The planarization tool110is a semiconductor processing tool that is capable of polishing and/or planarizing one or more layers of a semiconductor device to increase the flatness of the layers of the semiconductor device, to improve layer stacking for the semiconductor device, and/or the like. The planarization tool110may polish and/or planarize a layer, a substrate, or a wafer using a polishing or planarizing technique such as chemical mechanical polishing/planarization (CMP). A CMP process may include depositing a slurry (or polishing compound) onto a polishing pad. A wafer may be mounted to a carrier, which may rotate the wafer as the wafer is pressed against the polishing pad. The slurry and polishing pad act as an abrasive that polishes or planarizes one or more layers of the wafer as the wafer is rotated. The polishing pad may also be rotated to ensure a continuous supply of slurry is applied to the polishing pad.

Wafer/die transport device112includes a mobile robot, a robot arm, a tram or rail car, and/or another type of device that are used to transport wafers and/or dies between semiconductor processing devices102-110and/or to and from other locations, such as a wafer rack, a storage room, and/or the like. In some implementations, wafer/die transport device112may be a programmed device to travel a particular path and/or may operate semi-autonomously.

The number and arrangement of devices and networks shown inFIG.1are provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or differently arranged devices than those shown inFIG.1. Furthermore, two or more devices shown inFIG.1may be implemented within a single device, or a single device shown inFIG.1may be implemented as multiple, distributed devices. Additionally, or alternatively, a set of devices (e.g., one or more devices) of environment100may perform one or more functions described as being performed by another set of devices of environment100.

FIGS.2A-2Hare diagrams of one or more example implementations200described herein. Example implementation(s)200may include one or more example implementations of forming one or more parts of a semiconductor device202. The semiconductor device202may include a transistor (e.g., a metal oxide field effect transistor (MOSFET) or another type of transistor), a memory device (e.g., a static random access memory (SRAM) or another type of memory device), and/or the like.

As shown inFIG.2A, the semiconductor device202may include various types of semiconductor structures, including a substrate204in which an epitaxial region206may be formed, an optional silicide layer208above and/or on the epitaxial region206in a trench210formed by a plurality of gate spacers214that electrically isolate the trench210and metal gates212formed on each side of the trench210, insulating caps216formed on the metal gates212to permit a self-aligned contact (SAC) or self-aligned metal plug to be formed in the trench210, and/or other semiconductor structures.

The substrate204may include an active region of a transistor, a shallow trench isolation (STI) structure, or another type of substrate204. In some implementations, the substrate204is a silicon wafer or a portion thereof. In some implementations, the substrate204is a layer of silicon or poly-silicon formed on a wafer or a portion thereof. The epitaxial region206may include a source region or a drain region of the semiconductor device. The epitaxial region206may be formed in the substrate204(e.g., by deposition tool102) through epitaxial growth.

Silicide layer208may include a layer of a metal silicide such as a titanium silicide (TiSix), a nickel silicide (NixSi), or another metal silicide, that is to reduce contact resistance between the epitaxial region206and a metal plug to be formed in trench210. In some implementations, the silicide layer208may be formed by depositing (e.g., using deposition tool102) a metal layer or a metal silicide layer on the epitaxial region206. In some implementations, the metal layer or a metal silicide layer is deposited on both sidewalls and bottom of the trench210using a CVD technique, and then portions of the metal layer on sidewalls of the trench210are optionally removed. In some implementations, the metal layer or a metal silicide layer is deposited on sidewalls of the trench210using a PVD technique. An anneal of the semiconductor device202may be performed (e.g., using annealing tool106) to heat the semiconductor device202. The metal layer may include a titanium layer, a tungsten layer, a nickel layer, a ruthenium layer, a molybdenum layer, or another type of metal. The elevated temperature, caused by heating the semiconductor device202, causes the metal layer to react with the epitaxial region206. The reaction causes the metal layer and silicon in the epitaxial region206to form the self-aligned silicide layer208on the epitaxial region206in the trench210.

The trench210may be a narrow trench with a high aspect ratio or another type of trench. The gate spacers214may include an electrically insulating material, such as silicon oxide (SiOx), silicate glass, silicon oxycarbide, silicon nitride (SixNy), and/or the like. The gate spacers214may function as a sidewall of the trench210in addition to providing electrical insulation for the metal gates212. The metal gates212may include an electrically conductive metal, such as titanium, cobalt, tungsten, aluminum, copper, ruthenium, iridium, and/or the like. In examples in which an SAC is to be formed in the trench210, a portion of the metal gates212may be etched (e.g., using a dry etching process, a wet etching process, and/or the like) such that insulating caps216may be formed over each of the metal gates212to electrically insulate the top and/or portions of the side of the metal gates212from the SAC. The insulating cap216may be formed of an electrically insulating material, such as silicon oxide (SiOx), silicate glass, silicon oxycarbide, silicon nitride (SixNy), and/or the like.

As shown inFIGS.2B-2F, one or more processes and/or techniques may be performed on the semiconductor device202to prepare the trench210to be filled with a metal plug, a contact, or an SAC. As shown inFIG.2B, a titanium silicon nitride (TiSiN) layer218may be formed on the bottom and on the sidewall of the trench210. In some implementations, the TiSiN layer218may be formed to a thickness in a range of approximately 2 nanometers to approximately 2.5 nanometers in some areas of the trench210and/or to a thickness in a range of approximately 1 nanometer to approximately 1.5 nanometers in examples where the silicide layer208is formed using a CVD process. In some implementations, the TiSiN layer218may be formed to a thickness in a range of approximately 2 nanometers to approximately 4 nanometers in some areas of the trench210and/or to a thickness in a range of approximately 0.5 nanometer to approximately 1.5 nanometers in examples where the silicide layer208is formed using a PVD process. In some implementations, a semiconductor processing tool (e.g., deposition tool102) may form the TiSiN layer218by a CVD process, a PVD process, an ALD process, or another type of deposition process. In some implementations, a TiSiN layer218is omitted and is not used in the process of filling trench210.

As shown inFIG.2C, a precursor220may be used as a pre-deposition treatment of the TiSiN layer218to prepare the TiSiN layer218for formation of a metal adhesion layer on the TiSiN layer218. For example, the precursor220may be provided to a processing chamber in which the semiconductor device202is included, and may be deposited onto the TiSiN layer218. The precursor220may include a gas, such as tetrakis(dimethylamino)titanium (TDMAT or C8H24N4Ti), that is used as a titanium dioxide (TiO2) precursor for atomic layer deposition of titanium nitride (TiNx) or another type of gas that is used as a precursor for deposition of another type of metal adhesion layer.

As shown inFIG.2D, a metal adhesion material222may be provided to the processing chamber to react with the precursor220to form a metal adhesion layer224on the bottom of the trench210and on the side wall of the trench210(e.g., on and/or over the silicide layer208and/or the TiSiN layer218). The metal adhesion material222, and the metal adhesion layer224by extension, may include titanium nitride (TiNx), tantalum nitride (TaxNy), tungsten nitride (WNx), ruthenium, ruthenium cobalt (RuCo), or another material.

In some implementations, a semiconductor processing tool (e.g., deposition tool102) may deposit the metal adhesion material222to form the metal adhesion layer224by a CVD technique such as atomic layer deposition. Forming the metal adhesion layer224through the use of atomic layer deposition allows for a thin layer of the metal adhesion material222to be deposited in a highly controlled manner. This enables the metal adhesion layer224to be formed to a thickness in a range from approximately 1 nanometer to approximately 3.5 nanometers on the bottom and the sidewall of the trench210.

As shown inFIG.2E, a semiconductor processing tool (e.g., plasma tool104) may provide a plasma226into a processing chamber. The plasma226may be a nitrogen-based plasma (e.g., a plasma including N2ions) that reacts with the metal adhesion layer224. The semiconductor processing tool may provide a flow-in of nitrogen gas, for example, at a rate in a range from approximately 2000 standard cubic centimeters per minute (SCCM) to approximately 5500 SCCM. A plasma source in a range of approximately 3000 watts to approximately 5000 watts may generate the plasma226from the nitrogen gas in the processing chamber at a pressure in a range of approximately 0.5 torr to approximately 2.5 torr and a temperature in a range of approximately 250 degrees Celsius to approximately 400 degrees Celsius.

The plasma226may be used as a treatment for the metal adhesion layer224to increase the adhesion between the metal adhesion layer224and a metal plug to be filled in the trench210. In particular, the plasma226may react with the metal adhesion layer224to cause a phase composition change or transformation (also referred to as a crystal plane orientation change or transformation) for the metal adhesion layer224. As an example, if the metal adhesion layer224is a titanium nitride layer and the plasma226is a nitrogen-based plasma, the nitrogen ions in the plasma may react with the titanium nitride to cause a (111) phase of the titanium nitride to become a dominant phase of the phase composition of the titanium nitride. In this way, the plasma226causes an increase in the (111) phase of the titanium nitride and/or a decrease in a (200) phase of the titanium nitride. Thus, if the phase composition of the titanium nitride is dominated by the (200) phase (or if the phase composition is approximately equal composition of the (111) phase and the (200) phase), the treatment with the plasma226may increase the (111) phase to a ratio between the (111) phase and the (200) phase in a range of approximately 3:1 to approximately 6:1 or greater in the phase composition.

The increase of the (111) phase in the phase composition of the metal adhesion layer224(and/or the decrease of the (200) phase) increases adhesion with a metal plug that is to be filled in the trench210by modifying one or more properties of the metal adhesion layer224. For example, the increase of (111) phase (and/or the decrease of the (200) phase) may cause the nucleation (e.g., the initiation of a new thermodynamic phase or structure) of the metal adhesion layer224to be more uniform relative to the TiSiN layer218, which increases the continuity of the metal adhesion layer224relative to the TiSiN layer218. Moreover, the nitrogen ions from the plasma226treatment diffuse into the metal adhesion layer224to cause the change in phase composition of the metal adhesion layer224to be (111) phase dominant. These nitrogen ions are inserted into the crystal lattice structure of the metal adhesion layer224, which increases the interfacial nitrogen density of the crystal lattice structure. The increased interfacial nitrogen density provides an increased quantity of nitrogen ions to which the metal plug can bond, thereby increasing adhesion between the metal adhesion layer224and the metal plug.

In some implementations, the processes and/or techniques described above in connection withFIGS.2C-2Emay be performed for a plurality of cycles (e.g., 3 cycles, 6 cycles, or another quantity of cycles) to form and treat the metal adhesion layer224. In these examples, a first layer of the metal adhesion layer224may be formed (e.g., the precursor220may be deposited, and the metal adhesion material222may be deposited to react with the precursor220to form the first layer) and treated with the plasma226such that the (111) phase is dominant for the first layer, a second layer of the metal adhesion layer224may be formed on the first layer (e.g., the precursor220may be deposited, and the metal adhesion material222may be deposited to react with the precursor220to form the second layer) and treated with the plasma226such that the (111) phase is dominant for the second layer, and so on for additional layers until the metal adhesion layer224is formed to a particular thickness.

As shown inFIG.2F, once the metal adhesion layer224is formed, a seed layer228may be formed on and/or over the metal adhesion layer224in the trench210. The seed layer228may be an initial metal layer that is formed in the trench210to initiate the formation of the metal plug in the trench210. The seed layer228may be formed of the same material of the metal plug or of a different material. Examples of materials used for the seed layer228include titanium, cobalt, tantalum, tungsten, aluminum, hafnium, ruthenium, zirconium, molybdenum, and/or the like. In some implementations, a semiconductor processing tool (e.g., deposition tool102, plating tool108, or another processing tool) may deposit or form the seed layer228on and/or over the metal adhesion layer224, over the TiSiN layer218, over the bottom and the sidewall of the trench210, and/or the like.

As shown inFIG.2G, a semiconductor processing tool (e.g., deposition tool102, plating tool108, and/or the like) may fill the trench210with a metal plug230. In some implementations, the semiconductor processing tool may deposit material of the metal plug230onto the seed layer228to form the metal plug230. The seed layer228may promote even deposition, void-free deposition, and may increase adhesion between the metal adhesion layer224and the metal plug230. Examples of materials used for the seed layer228and/or the metal plug230include titanium, cobalt, tantalum, tungsten, aluminum, hafnium, ruthenium, zirconium, molybdenum, and/or the like.

As shown inFIG.2H, the semiconductor device202(or one or more layers or semiconductor structures of the semiconductor device202) may be planarized or polished. For example, a semiconductor processing tool (e.g., planarization tool110) may use a CMP technique to flatten or planarize the semiconductor device202such that additional layers and/or semiconductor structures may be formed thereon.

The number and arrangement of structures, layers, and/or the like shown inFIGS.2A-2Hare provided as an example. In practice, a semiconductor device including additional structures and/or layers, fewer structures and/or layers, different structures and/or layers, or differently arranged structures and/or layers than those shown inFIGS.2A-2Hmay be processed according to the techniques described above in connection withFIGS.2A-2H.

FIG.3is a diagram of an example300of phase composition data associated with one or more semiconductor devices described herein. As shown inFIG.3, example300illustrates phase composition data for a semiconductor device that includes a metal plug formed without a plasma-treated metal adhesion layer, and phase composition data for a semiconductor device (e.g., semiconductor device202) that includes a metal plug (e.g., metal plug230) formed with a plasma-treated metal adhesion layer (e.g., metal adhesion layer224). As shown inFIG.3, the (111) phase is increased (e.g., the intensity of the (111) phase is increased) and the (200) phase is decreased (e.g., the intensity of the (200) phase is decreased) for the of the semiconductor device that includes a metal plug formed with the plasma-treated metal adhesion layer relative to the semiconductor device that includes a metal plug formed without a plasma-treated metal adhesion layer.

FIG.4is a diagram of example components of a device400. In some implementations, the deposition tool102, the plasma tool104, the annealing tool106, the plating tool108, the planarization tool110, and/or the wafer/die transport device112may include one or more devices400and/or one or more components of device400. As shown inFIG.4, device400may include a bus410, a processor420, a memory430, a storage component440, an input component450, an output component460, and a communication component470.

Bus410includes a component that enables wired and/or wireless communication among the components of device400. Processor420includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor420is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor420includes one or more processors capable of being programmed to perform a function. Memory430includes a random access memory, a read only memory, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory).

Storage component440stores information and/or software related to the operation of device400. For example, storage component440may include a hard disk drive, a magnetic disk drive, an optical disk drive, a solid state disk drive, a compact disc, a digital versatile disc, and/or another type of non-transitory computer-readable medium. Input component450enables device400to receive input, such as user input and/or sensed inputs. For example, input component450may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system component, an accelerometer, a gyroscope, an actuator, and/or the like. Output component460enables device400to provide output, such as via a display, a speaker, and/or one or more light-emitting diodes. Communication component470enables device400to communicate with other devices, such as via a wired connection and/or a wireless connection. For example, communication component470may include a receiver, a transmitter, a transceiver, a modem, a network interface card, an antenna, and/or the like.

Device400may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory430and/or storage component440) may store a set of instructions (e.g., one or more instructions, code, software code, program code, and/or the like) for execution by processor420. Processor420may execute the set of instructions to perform one or more processes described herein. In some implementations, execution of the set of instructions, by one or more processors420, causes the one or more processors420and/or the device400to perform one or more processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

FIG.5is a flowchart of an example process500associated with forming a semiconductor device or a portion thereof. In some implementations, one or more process blocks ofFIG.5may be performed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools102-110ofFIG.1). Additionally, or alternatively, one or more process blocks ofFIG.5may be performed by one or more components of device400, such as processor420, memory430, storage component440, input component450, output component460, and/or communication interface470.

As shown inFIG.5, process500may include forming a titanium nitride layer over a bottom of a trench of a semiconductor device and over a sidewall of the trench (block510). For example, a semiconductor processing tool (e.g., deposition tool102) may form a titanium nitride layer (e.g., a metal adhesion layer224) over a bottom of a trench210(e.g., over a silicide layer208at the bottom of the trench210) of a semiconductor device202and over a sidewall of the trench210(e.g., formed by a plurality of gate spacers214), as described above.

As further shown inFIG.5, process500may include modifying a phase composition of the titanium nitride layer using a plasma (block520). For example, a semiconductor processing tool (e.g., plasma tool104) may modify a phase composition of the titanium nitride layer (e.g., the metal adhesion layer224) using a plasma, as described above.

As further shown inFIG.5, process500may include forming a metal plug in the trench after modifying the phase composition of the titanium nitride layer (block530). For example, a semiconductor processing tool (e.g., deposition tool102, plating tool108, and/or the like) may form a metal plug230in the trench210after modifying the phase composition of the titanium nitride layer (e.g., the metal adhesion layer224), as described above.

In a first implementation, modifying the phase composition of the titanium nitride layer increases adhesion between the titanium nitride layer and the metal plug. In a second implementation, alone or in combination with the first implementation, modifying the phase composition of the titanium nitride layer includes causing the phase composition of the titanium nitride layer to transition to a (111) dominant phase. In a third implementation, alone or in combination with one or more of the first and second implementations, modifying the phase composition of the titanium nitride layer includes using nitrogen ions in the plasma to increase a (111) phase of the titanium nitride layer.

In a fourth implementation, alone or in combination with one or more of the first through third implementations, process500includes forming a titanium silicon nitride layer (e.g., TiSiN layer218) over the bottom of the trench and over the sidewall of the trench, and wherein forming the titanium nitride layer includes forming the titanium nitride layer on the titanium silicon nitride layer. In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, modifying the phase composition of the titanium nitride layer using the plasma increases uniformity of nucleation of the titanium nitride layer on the titanium silicon nitride layer.

In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, process500includes pretreating the titanium silicon nitride layer with a tetrakis(dimethylamino)titanium (TDMAT) precursor (e.g., precursor220) prior to forming the titanium nitride layer. In a seventh implementation, alone or in combination with one or more of the first through sixth implementations, forming the metal plug includes forming a seed layer228on the titanium nitride layer, and forming the metal plug on the seed layer.

FIG.6is a flowchart of an example process600associated with forming a semiconductor device or a portion thereof. In some implementations, one or more process blocks ofFIG.6may be performed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools102-110ofFIG.1). Additionally, or alternatively, one or more process blocks ofFIG.6may be performed by one or more components of device400, such as processor420, memory430, storage component440, input component450, output component460, and/or communication interface470.

As shown inFIG.6, process600may include forming a first layer of a metal adhesion layer over a bottom of a trench and over a sidewall of the trench (block610). For example, a semiconductor processing tool (e.g., deposition tool102) may form a first layer of a metal adhesion layer224over a bottom of a trench210(e.g., over a silicide layer208at the bottom of the trench210) and over a sidewall of the trench210(e.g., formed by a plurality of gate spacers214), as described above.

As further shown inFIG.6, process600may include increasing, using a plasma, a (111) phase of the first layer (block620). For example, a semiconductor processing tool (e.g., plasma tool104) may increase, using a plasma, a (111) phase of the first layer, as described above.

As further shown inFIG.6, process600may include forming a second layer of the metal adhesion layer on the first layer (block630). For example, a semiconductor processing tool (e.g., deposition tool102) may form a second layer of the metal adhesion layer224on the first layer, as described above.

As further shown inFIG.6, process600may include increasing, using the plasma, a (111) phase of the second layer (block640). For example, a semiconductor processing tool (e.g., plasma tool104) may increase, using the plasma, a (111) phase of the second layer, as described above.

As further shown inFIG.6, process600may include forming a metal plug in the trench over the first layer and the second layer of the metal adhesion layer (block650). For example, a semiconductor processing tool (e.g., deposition tool102, plating tool108, and/or the like) may form a metal plug230, in the trench210over the first layer and the second layer of the metal adhesion layer224, as described above.

In a first implementation, process600includes forming a titanium silicon nitride layer (e.g., TiSiN layer218) over the bottom of the trench and over the sidewall of the trench, and wherein forming the first layer of the metal adhesion layer includes forming the first layer of the metal adhesion layer on the titanium silicon nitride layer. In a second implementation, alone or in combination with the first implementation, process600includes pretreating the titanium silicon nitride layer with a precursor220prior to forming the first layer and the second layer of the metal adhesion layer.

In a third implementation, alone or in combination with one or more of the first and second implementations, a ratio of the (111) phase of the first layer to a (200) phase of the first layer is within a range from approximately 3:1 to approximately 6:1. In a fourth implementation, alone or in combination with one or more of the first through third implementations, the metal adhesion layer includes titanium nitride, tantalum nitride, tungsten nitride, ruthenium, or ruthenium cobalt. In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, process600includes forming the metal plug on a seed layer228, wherein the metal plug and the seed layer each includes titanium, cobalt, tantalum, tungsten, aluminum, hafnium, ruthenium, zirconium, or molybdenum.

AlthoughFIG.6shows example blocks of process600, in some implementations, process600may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted inFIG.6. Additionally, or alternatively, two or more of the blocks of process600may be performed in parallel.

As described above, de-wetting for a metal plug may be reduced by forming a metal adhesion layer on a bottom and a sidewall of a trench prior to formation of the metal plug in the trench. A nitrogen-based plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the nitrogen-based plasma may cause a shift or transformation of the phase composition of the metal adhesion layer from being roughly equally composed of a (111) phase and a (200) phase (or from having less of a (111) phase component than a (200) phase component) to being composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer and the metal plug in that the (111) dominant phase provides a finer-grained micro structure and a higher interfacial nitrogen density, which provides a greater quantity of nitrogen atoms to which the metal plug may bond.

As described in greater detail above, some implementations described herein provide a method. The method includes forming a titanium nitride layer over a bottom of a trench of a semiconductor device and over a sidewall of the trench. The method includes modifying a phase composition of the titanium nitride layer using a plasma. The method includes forming a metal plug in the trench after modifying the phase composition of the titanium nitride layer.

As described in greater detail above, some implementations described herein provide a device. The device includes a first metal gate, a second metal gate, a trench between the first metal gate and the second metal gate, a silicide layer at a bottom of the trench, an epitaxial region below the silicide layer, a titanium nitride layer over the silicide layer and over a sidewall of the trench, and a metal plug over the titanium nitride layer in the trench. The titanium nitride layer has a (111) dominant phase.

As described in greater detail above, some implementations described herein provide a method. The method includes forming a first layer of a metal adhesion layer over a bottom of a trench and over a sidewall of the trench. The method includes increasing, using a plasma, a (111) phase of the first layer. The method includes forming a second layer of the metal adhesion layer on the first layer. The method includes increasing, using the plasma, a (111) phase of the second layer. The method includes forming a metal plug in the trench over the first layer and the second layer of the metal adhesion layer.