Device and method for data protection by scrambling address lines

A device and method for data protection by scrambling address lines is disclosed, which includes a redundancy area-setting unit, a redundancy area-mapping rule unit, an area check unit, an address-mapping unit and a multiplexer. The area check unit compares an address of address bus with addresses of first data area or redundancy area stored in the redundancy area-setting unit and accordingly generates a comparison result. The address-mapping unit converts the address of address bus into an address of redundancy area. The multiplexer outputs the address of redundancy area when the comparison result and a switch control signal are logic true; otherwise the address of address bus is output.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the technical field of processors and, more particularly, to a device and method for data protection by scrambling address lines in a processor.

2. Description of Related Art

Due to the importance of intellectual properties, manufactories usually scramble their intellectual property (IP), including data and programs, off-line for data protection and store the scrambled data in a non-volatile memory or storage medium, such that an unauthorized person cannot access the data even if he/she obtains the memory or storage medium with the scrambled data.

U.S. Pat. No. 6,408,073 granted to Hsu, et al. for an “Scramble circuit to protect data in a read only memory ” discloses a scramble circuit for protecting data stored in a read only memory by applying both a pseudo-random generator and an initial value seed1/seed2 to code ROM (Read Only Memory) data and thus generates encoded data. However, since the scrambling technology uses random numbers as parameters, such a data protection method requires a synchronous random generator for decoding. Thus program codes cannot be executed directly on such a ROM protected by this method, because any branch or jump in a program may dynamically change the decoding sequence. For example,FIG. 1shows an exemplary set of program codes that are encrypted by sequential random numbers and stored in a ROM from 1F00—0000Hto 1F00—0020H. When a processor executes the program codes directly, a conditional branch may lead to a problem. That is, after the processor executes the third instruction (i.e., instr #3 ofFIG. 1) representing bz 1F00—0020Hat address 1F00—000CH, it may jump to address 1F00—0020Hfor next execution in accordance with the content of zero flag. However, on one hand, data stored in address 1F00—0020Hresults in encoding with a number ‘78’ generated by applying a pseudo random generator20to instr #8 ofFIG. 1, and on the other hand, the processor decodes data stored in address 1F00—0020Husing value60generated by the pseudo random generator at this moment, instead of the value ‘78’ in the encoding process. Accordingly, the program is not executed properly due to the cited error, even the processor may stall. Therefore, applying a random generator or pseudo random generator can protect ROM data only, not for RAN (Random Access Memory), Flash and the like.

To solve the problem, U.S. Pat. No. 5,943,283 granted to Wong, et al. for an “Address scrambling in a semiconductor memory” uses address scrambling to convert sequential input addresses into non-sequential physical addresses, thus achieving data protection for RAM or Flash. However, if the stored data has significant sequencing pattern (e.g., Boot-up Strap procedure for a processor, or common function tables), data protection used can easily be cracked by guessing data disposition.

Therefore, it is desirable to provide an improved data protection method to mitigate and/or obviate the aforementioned problems.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a device for data protection by scrambling address lines in a processor core, thereby avoiding the prior scrambling crack from data arrangement guess and achieving data protection.

In accordance with one aspect of the present invention, there is provided a device for data protection by scrambling address lines in a processor core. The processor core executes instructions of the processor and accesses data through an address bus and a data bus. The data is stored in a first data area for important information and a second data area. The device for data protection includes a redundancy area-setting unit, a redundancy area-mapping rule unit, an area check unit, an address-mapping unit and a multiplexer. The redundancy area-setting unit sets addresses of the first data area and addresses of a redundancy area corresponding to the first data area. The redundancy area-mapping rule unit provides rule for converting addresses of the first data area into addresses of the redundancy area. The area check unit is connected to the redundancy area-setting unit and the address bus, for comparing an address on the address bus with addresses of the redundancy area stored in the redundancy area-setting unit and generating a comparison result. The address-mapping unit is connected to the redundancy area-mapping rule unit and the address bus, for converting the address on the address bus into an address of the redundancy area. The multiplexer is controlled by the comparison result and a switch control signal in order to output the address of the redundancy area when the comparison result and the switch control signal are logic true or otherwise output the address of the address bus.

In accordance with another aspect of the present invention, there is provided a method for data protection by scrambling address lines in a processor core. The processor core executes instructions of the processor and accesses data through an address bus and a data bus. The data is stored in a first data area for important information and a second data area. The method for data protection includes steps: (A) copying content of the first data area to a redundancy area; (B) recording both addresses of the first data area and the redundancy area; (C) providing rule for converting addresses of the first data area into addresses of the redundancy area; (D) comparing an address on the address bus with addresses of the first data area or the redundancy area and generating a comparison result when the processor core is to access data; (E) converting the address on the address bus into an address of the redundancy area in accordance with the rule; (F) selecting an output address in accordance with the comparison result and a switch control signal, wherein the address of the redundancy area is output when the comparison result and the switch control signal are logic true, and otherwise the address of the address bus is output.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 2is a block diagram of a device for data protection by scrambling address lines in a processor core201in accordance with the invention. InFIG. 2, the processor core201executes instructions of the processor and accesses data through an address bus203and a data bus202. The accessed data is stored in a memory202on a first data area310for important information and a second data area330.

The device for data protection by scrambling address lines in a processor core includes a redundancy area-setting unit210, a redundancy area-mapping rule unit220, an area check unit230, an address-mapping unit240, a multiplexer250, a random generator260, an AND gate270, a seed generator280and an address scrambler290.

The redundancy area-setting unit210sets address of the first data area310and addresses of a redundancy area320corresponding to the first data area310. For example, the content of the first data area310on addresses 00000H˜0FFFFHis copied to the redundancy area320on addresses F0000H˜FFFFFHwhile the second data area330is on addresses 10000H˜EFFFFH. In this case, address 0xxxxH(in the first data area310) or FxxxxH(in the redundancy area320) are set for address detection in the redundancy area-setting unit210, where ‘x’ means ‘don't care’.

The area check unit230is connected to the redundancy area-setting unit210and the address bus203, for comparing the address stored in the redundancy area-setting unit210with an address on the address bus203and generating a comparison result231. If the processor core201is to read the content at an address 0ABCDH, the area check unit230finds that the address 0ABCDHto be read is matched to address in the redundancy area-setting unit210(i.e., address 0xxxxHof the first data area310) and accordingly outputs the comparison result231as logic true (1). On the other hand, if the processor core201is to read the content at an address 23456H, the area check unit230finds that the address 23456Hto be read is not matched to address in the redundancy area-setting unit210(i.e., addresses 0xxxxHof the first data area310) and accordingly outputs the comparison result231as logic false (0).

The redundancy area-mapping rule unit220provides rule for converting addresses of the first data area310into addresses of the redundancy area320. For example, the address conversion is set as inverting of address lines from bit19to bit16such that addresses of the first data area310is converted into addresses of the redundancy area320.

The address-mapping unit240is connected to the redundancy area-mapping rule unit220and the address bus203, for converting the address of the first data area310on the address bus203into an address of the redundancy area320. For example, when the processor core201is to read data on address 0ABCDH, the address-mapping unit240converts it into an address FABCDH.

The multiplexer250is connected to the address bus203of the processor core201and the output address lines of the address-mapping unit240, and controlled by the comparison result231and a switch control signal261, which can determine to output the address of the address bus203of the processor core201or output address of the address-mapping unit240.

When the processor core201is to read data at address 0ABCDH, the comparison result of the area check unit230is logic true. When the switch control signal261is also logic true, the AND gate270outputs logic true (1) and thus the multiplexer250outputs address FABCDHof the address-mapping unit240. As such, the processor core201accesses data from the address FABCDH. On the other hand, when the switch control signal261is logic false (0), the AND gate270outputs logic false (0) even though the comparison result is logic true. Thus, the multiplexer250outputs address 0ABCDHon the address bus203of the processor core201.

When the processor core201is to read data at address 23456H, the comparison result of the area check unit230is logic false (0) and thus the AND gate270outputs logic false (0). Therefore, the multiplexer250outputs address 23456Hon the address bus203of the processor core201, which is located in the second data area330.

The aforementioned switch control signal261can be generated by the random generator260or the processor core201, thereby increasing uncertainty of accessing the first data area310and the redundancy area320.

The seed generator280randomly generates a seed. The address scrambler290is connected to an output of the multiplexer for performing address scrambling on output address of the multiplexer based on the seed. The address scrambler290can generate a scrambled address in accordance with entire or partial addresses.

The address scrambler290can generate a scrambled address in accordance with (a-r) address lines on the address bus, where a is the number of entire address lines and 2ris word number of a cache line in a cache memory of the processor.

Because physical address lines of a memory are much fewer than address lines used by the processor, address line number q on the address bus is greater than or equal to address line number p after the scrambling performance.

FIGS. 3 and 4are schematic charts of operation examples of scrambling address lines for data protection. InFIG. 3, the content of the first data area is identical to that of the redundancy area. Accordingly, when the processor core201needs program codes or data in the first data area310, the processor core201can read the required data or program codes from the first data area310or the redundancy area320in accordance with the switch control signal261. Such a manner contributes uncertainty to address read by the processor core201due to different address provided in each execution for reading. Therefore, the program codes or data is dynamically protected by different addressing every time.

InFIG. 4, the first data area310is copied to the redundancy area320. The first data area310, the redundancy area320and the second data area330are scrambled to increase address randomness for store. The redundancy area320can increase address randomness during address scrambling performance and difficulty to an unauthorized person for crack. After address scramble, the processor core201does not sequentially execute the program codes anymore. However, when the program codes with the same function (e.g., Bootstrap) are executed by the processor core201each time, an address branch for reading instruction codes has the same rule. As such, address scrambling used can easily be decoded and understood by inversely inferring the rule. To avoid this, the redundancy area320is added to make different address branch to the same program codes for each execution. In this case, important program codes are located on the first data area310to increase execution randomness for data protection. This can prevent both static and dynamic decoding.

In view of foregoing, it is known that the invention applies the redundancy area320and a random generator260or the switch control signal261generated by the processor core201to increase access uncertainty to the first data area310and the redundancy area320. In addition, the invention uses the address scrambler290to enhance address uncertainty in data access. Accordingly, the prior problem that scrambling method used can easily be found by guessing data disposition is overcome, thereby obtaining data protection.