There is provided a semiconductor device in which the inter-wiring capacitance of wiring lines provided in any layout is further reduced. A semiconductor device (1) including: a first inter-wiring insulating layer (120) that is provided on a substrate (100) and includes a recess on a side opposite to the substrate; a first wiring layer (130) that is provided inside the recess in the first inter-wiring insulating layer; a sealing film (140) that is provided along an uneven shape of the first wiring layer and the first inter-wiring insulating layer; a second inter-wiring insulating layer (220) that is provided on the first inter-wiring insulating layer to cover the recess; and a gap (150) that is provided between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer. The second inter-wiring insulating layer has a planarized surface that is opposed to the recess.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National Phase of International Patent Application No. PCT/JP2019/023520 filed on Jun. 13, 2019, which claims priority benefit of Japanese Patent Application No. JP 2018-121524 filed in the Japan Patent Office on Jun. 27, 2018. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device.

BACKGROUND ART

In recent years, finer wiring lines of semiconductor devices each have increased the wire delay, which decreases the operation speed of the semiconductor device. Specifically, finer wiring lines have smaller cross-sectional area and higher wiring resistance. This increases delay (also referred to as RC delay), which is proportional to the product of the wiring resistance and the inter-wiring capacitance.

It is therefore considered to decrease the dielectric constant between the wiring lines to reduce the inter-wiring capacitance. Specifically, it is considered to further reduce the dielectric constant between the wiring lines by removing the insulating material between the wiring lines to provide a gap (also referred to as air gap) having a specific dielectric constant of 1 between the wiring lines.

For example, NPTL 1 below discloses a method of forming a gap between wiring lines by using non-conformal deposition film formation such as CVD (Chemical Vapor Deposition) to place deposits above the wiring lines before the space between the wiring lines is filled with a deposit.

CITATION LIST

NPTL 1: K. Fischer, et. al., “Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14 nm high volume manufacturing”, 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM), 2015

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

The technology disclosed in NPTL 1 has more difficulty in forming a gap between wiring line as the wiring lines have a longer distance because the space between the wiring lines is filled with a deposit. This requires technology that allows a gap to be formed between wiring lines in any layout regardless of the distance between the wiring lines.

Accordingly, the present disclosure proposes a novel and improved semiconductor device and method of manufacturing a semiconductor device that allows the inter-wiring capacitance of wiring lines provided in any layout to be reduced.

Means for Solving the Problems

According to the present disclosure, there is provided a semiconductor device including: a first inter-wiring insulating layer that is provided on a substrate and includes a recess on a side opposite to the substrate; a first wiring layer that is provided inside the recess in the first inter-wiring insulating layer; a sealing film that is provided along an uneven shape of the first wiring layer and the first inter-wiring insulating layer; a second inter-wiring insulating layer that is provided on the first inter-wiring insulating layer to cover the recess; and a gap that is provided between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer. The second inter-wiring insulating layer has a planarized surface that is opposed to the recess.

In addition, according to the present disclosure, there is provided a method of manufacturing a semiconductor device. The method includes: forming a first inter-wiring insulating layer on a substrate; forming a recess in the first inter-wiring insulating layer and exposing the first wiring layer inside the recess; providing a sealing film along an uneven shape of the first wiring layer and the first inter-wiring insulating layer; and providing a second inter-wiring insulating layer on the first inter-wiring insulating layer to cover the recess and forming a gap between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer. The first inter-wiring insulating layer has a first wiring layer embedded on a side opposite to the substrate. The second inter-wiring insulating layer has a planarized surface that is opposed to the recess.

According to the present disclosure, the uneven surface of the first inter-wiring insulating layer and the planarized surface of the second inter-wiring insulating layer are bonded together, thereby making it possible to provide a gap inside the recess in the first inter-wiring insulating layer. In a semiconductor device1, it is thus possible to provide a gap around the first wiring layers provided in any layout inside the recess in the first inter-wiring insulating layer.

Effects of the Invention

According to the present disclosure as described above, it is possible to provide the semiconductor device in which the inter-wiring capacitance of the wiring lines provided in any layout is further reduced.

It is to be noted that the above-described effects are not necessarily limitative. Any of the effects indicated in this description or other effects that may be understood from this description may be attained in addition to the above-described effects or in place of the above-described effects.

MODES FOR CARRYING OUT THE INVENTION

The following describes a preferred embodiment of the present disclosure in detail with reference to the accompanying drawings. It is to be noted that, in this description and the drawings, components that have substantially the same functional configuration are indicated by the same reference signs and redundant description thereof is thus omitted.

In each diagram referred to in the following description, the size of some of the constituent members is exaggerated for convenience of description. Accordingly, the relative size of the components illustrated in each diagram does not necessarily express the size relationship between the actual constituent members with accuracy. In addition, the following description sometimes expresses the direction in which substrates or layers are stacked as an up direction.

It is to be noted that description is given in the following order.

1. First Embodiment

1.1. Structure Example of Semiconductor Device

1.2. Example of Method of Manufacturing Semiconductor Device

1.3. Modification Examples of Semiconductor Device

2. Second Embodiment

2.1. First Structure Example of Solid-State Imaging Device

2.2. Second Structure Example of Solid-State Imaging Device

2.3. Third Structure Example of Solid-State Imaging Device

2.4. Fourth Structure Example of Solid-State Imaging Device

3. Application Examples

1. First Embodiment

1.1. Structure Example of Semiconductor Device

First, a structure example of a semiconductor device according to a first embodiment of the present disclosure is described with reference toFIGS. 1 and 2.FIG. 1is a vertical cross-sectional view schematically illustrating a structure example of the semiconductor device according to the first embodiment of the present disclosure.

As illustrated inFIG. 1, a semiconductor device1includes a substrate100, an inter-layer insulating film110, a first inter-wiring insulating layer120, a first wiring layer130, a barrier layer131, a cap layer132, a sealing film140, a second inter-wiring insulating layer220, and an inter-layer insulating films211and212. In the semiconductor device1, a gap150is formed by the planarized surface of the second inter-wiring insulating layer220and the uneven shape of the first inter-wiring insulating layer120and the first wiring layer130.

The substrate100is a support provided with each component of the semiconductor device1. Specifically, as long as the substrate100is a plate member having rigidity and a planarized surface, a publicly known substrate is usable. Alternatively, it is possible to use various glass substrates, resin substrates, semiconductor substrates, or the like. For example, the substrate100may be a glass substrate formed by using high strain point glass, soda glass, borosilicate glass, sapphire glass, quartz glass, or the like. The substrate100may be a resin substrate formed by using a resin such as polymethyl methacrylate, polyvinyl alcohol, polyimide, or polycarbonate. The substrate100may be a semiconductor substrate formed by using Si, Ge, GaAs, GaN, SiC, or the like.

The inter-layer insulating film110is provided on the substrate100and separates the substrate100and the first wiring layer130from each other. Specifically, in a case where the substrate100is a semiconductor substrate, the inter-layer insulating film110electrically insulates various elements such as transistors formed on the substrate100and the first wiring layers130to prevent them from being conductive to each other. In addition, the inter-layer insulating film110may be provided to prevent each component formed on the inter-layer insulating film110from being influenced by the surface shape of the substrate100. For example, the inter-layer insulating film110may include a low-dielectric-constant material (so-called low-k material) such as carbon-doped SiO2or porous silica or an insulating material such as SiO2, SiCN, SiN, SiOC, or SiOCN.

It is to be noted that, in a case where the substrate100is a semiconductor substrate, parasitic capacitance is generated between the substrate100and the first wiring layer130. To reduce such parasitic capacitance, the inter-layer insulating film110may include a low-dielectric-constant material (so-called low-k material).

The first inter-wiring insulating layer120includes an insulating material and is provided on the inter-layer insulating film110. The first inter-wiring insulating layer120supports the second inter-wiring insulating layer220to form the stacked structure of the semiconductor device1. In addition, a recess including the first wiring layers130therein is formed in the first inter-wiring insulating layer120. The first inter-wiring insulating layer120supports the second inter-wiring insulating layer220with the side wall of the recess to form the gap150inside the recess. This allows the first inter-wiring insulating layer120to have the gap150having a specific dielectric constant of 1 around the first wiring layers130. It is thus possible to reduce the inter-wiring capacitance of the first wiring layers130.

The first inter-wiring insulating layer120may include, for example, a low-dielectric-constant material (so-called low-k material) such as carbon-doped SiO2or porous silica or an insulating material such as SiO2or SiOC. It is, however, preferable that the first inter-wiring insulating layer120include a low-dielectric-constant material (so-called low-k material) or an insulating material such as SiO2or SiOC having a low specific dielectric constant to reduce the inter-wiring capacitance of the first wiring layers130.

Each of the first wiring layers130is a wiring line that electrically couples the respective elements included in the semiconductor device1. The plurality of first wiring layers130is provided to be embedded in the first inter-wiring insulating layer120. Specifically, the first wiring layers130are provided in any layout inside a recess formed in the first inter-wiring insulating layer120. The first wiring layers130are provided to project from the bottom surface of the recess formed in the first inter-wiring insulating layer120. The gap150is provided around the first wiring layers130. The gap150is formed by the recess of the first inter-wiring insulating layer120and the second inter-wiring insulating layer220. This makes it possible to provide the gap150having a specific dielectric constant of 1 between the wiring lines of the first wiring layers130. It is thus possible to reduce the inter-wiring capacitance of the first wiring layers130.

The first wiring layers130are provided to be embedded in the first inter-wiring insulating layer120. The height of each of the first wiring layers130is thus less than or equal to the height of the first inter-wiring insulating layer120. This may cause the gap150to be provided on a portion of the first wiring layers130between the first wiring layer130and the inter-layer insulating film212provided on the surface of the second inter-wiring insulating layer220. In such a case, it is possible to further reduce the inter-wiring capacitance of the first wiring layers130. In contrast, in a case where the more first wiring layers130are in contact with the inter-layer insulating film212on the surface of the second inter-wiring insulating layer220, it is possible to further increase the mechanical strength of the entire semiconductor device1.

The first wiring layers130each include an electrically conductive material. For example, the first wiring layer130may include copper (Cu), aluminum (Al), ruthenium (Ru), or cobalt (Co). Alternatively, the first wiring layer130may include an alloy (e.g., Cu—Mn alloy, Al—Cu alloy, or the like) of these metals. For example, in a case where the first wiring layer130includes copper (Cu) or copper alloy, the first wiring layer130is easy to form to be embedded in the first inter-wiring insulating layer120by using a damascene method.

The barrier layer131includes metal having a high barrier property with respect to an atom. The barrier layer131is provided on a surface of the first wiring layer130other than the upper surface (i.e., surface on the side opposed to the second inter-wiring insulating layer). More specifically, the barrier layer131is provided on a surface on which the first wiring layer130is in contact with the first inter-wiring insulating layer120in the manufacturing step. The barrier layer131prevents an electrically conductive material included in the first wiring layer130from being diffused to the first inter-wiring insulating layer120. The barrier layer131may include, for example, tantalum (Ta), titanium (Ti), manganese (Mn), ruthenium (Ru), or cobalt (Co). Alternatively, the barrier layer131may include nitrides or oxides of these metals. It is preferable that the barrier layer131include a metal material that does not react to materials included in the first wiring layer130and the first inter-wiring insulating layer120and has a high adhesion property with respect to these materials.

The cap layer132includes a material having low permeability with respect to moisture, oxygen, or the like. The cap layer132is provided on the first wiring layer130and the first inter-wiring insulating layer120. Specifically, the cap layers132are provided on the upper surface of the first wiring layer130in contact with the second inter-wiring insulating layer220with the inter-layer insulating film212interposed therebetween and the upper surface of the side wall of the recess in the first inter-wiring insulating layer120. That is, the cap layer132may be each provided in a region in which the first wiring layer130or the first inter-wiring insulating layer120is in contact with the second inter-wiring insulating layer220with the inter-layer insulating film212interposed therebetween. The cap layer132makes it possible to prevent the first wiring layer130and the first inter-wiring insulating layer120from being oxidized by moisture, oxygen, or the like in the manufacturing step to decrease the characteristics, the reliability, and the adhesion property.

The cap layer132may include, for example, SiO2, SiC, SiCN, SiOC, SiON, AlN, or the like as a single-layer film or a stacked film. The cap layer132may include the same material as that of the sealing film140described below or a different material from that of the sealing film140.

The sealing film140includes a material having low permeability with respect to moisture, oxygen, or the like. The sealing film140is provided along the uneven shape of the first wiring layer130and the first inter-wiring insulating layer120. Specifically, the sealing film140is provided on the internal surface of the recess in the first inter-wiring insulating layer120, the surfaces of the first wiring layers130provided inside the recess, and the upper surfaces of the cap layers132. The sealing film140makes it possible to prevent each of the first wiring layers130from being oxidized by the moisture, oxygen, or the like remaining in the gap150to increase the electric resistance of the first wiring layer130or decrease the reliability of the first wiring layer130. The sealing film140may include, for example, SiO2, SiC, SiCN, SiOC, SiON, AlN, or the like as a single-layer film or a stacked film.

The gaps150are provided in the spaces formed by the uneven shape of the first inter-wiring insulating layer120and the first wiring layers130and the planarized surface of the second inter-wiring insulating layer220. For example, the inside of each of the gaps150may be evacuated of air, include an atmosphere, or encapsulate inert gas such as nitrogen.

The second inter-wiring insulating layer220includes an insulating material and is provided above the first inter-wiring insulating layer120with the cap layer132, the sealing film140, and the inter-layer insulating film212interposed therebetween. Specifically, the second inter-wiring insulating layer220has the planarized surface that is opposed to the recess in the first inter-wiring insulating layer120. The second inter-wiring insulating layer220is stacked above the first inter-wiring insulating layer120in a layered manner to form the gap150between the second inter-wiring insulating layer220and the recess in the first inter-wiring insulating layer120. That is, the second inter-wiring insulating layer220is planarized above the upper surface of the side wall of the recess in the first inter-wiring insulating layer120to serve as a lid on the recess. This allows the second inter-wiring insulating layer220to form the gap150having a specific dielectric constant of 1 inside the recess in the first inter-wiring insulating layer120. Here, the planarized surface of the second inter-wiring insulating layer220may mean that the corresponding surface of the second inter-wiring insulating layer220is not provided with any recess, projection, or structure.

The second inter-wiring insulating layer220may include, for example, a low-dielectric-constant material (so-called low-k material) such as carbon-doped SiO2or porous silica or an insulating material such as SiO2or SiOC. It is, however, preferable that, in a case where there are provided wiring layers inside the second inter-wiring insulating layer220, the second inter-wiring insulating layer220include a low-dielectric-constant material (so-called low-k material) or an insulating material such as SiO2or SiOC having a low specific dielectric constant to reduce the inter-wiring capacitance of the wiring layers. It is to be noted that the second inter-wiring insulating layer220may be formed by using the same material as that of the first inter-wiring insulating layer120or a different material.

The inter-layer insulating films211and212each include an insulating material and are provided on both principal surfaces of the second inter-wiring insulating layer220. The inter-layer insulating films211and212each attain, for example, a function of increasing the junction strength between the second inter-wiring insulating layer220and another layer (e.g., sealing film140), a stopper function for an etching process on a member in an upper layer or a lower layer, or the like. It is to be noted that both or one of the inter-layer insulating films211and212does not have to be provided in some cases.

The inter-layer insulating films211and212may each include, for example, a low-dielectric-constant material (so-called low-k material) such as carbon-doped SiO2or porous silica or an insulating material such as SiO2, SiCN, SiN, SiOC, or SiOCN. In a case where the inter-layer insulating films211and212are each formed by using a low-dielectric-constant material (so-called low-k material), the inter-layer insulating films211and212make it possible to further reduce the parasitic capacitance of the semiconductor device1. In addition, in a case where the inter-layer insulating films211and212are each formed by using a silicon oxide film or a silicon nitride film (e.g., SiO2, SiCN, SiN, SiOC, SiOCN, or the like), the inter-layer insulating films211and212make it possible to further increase the junction strength between the first inter-wiring insulating layer120and the second inter-wiring insulating layer220. The inter-layer insulating films211and212may be each formed by using the same material or a different material. In addition, the inter-layer insulating films211and212may be each formed by using the same material as that of the inter-layer insulating film110, the second inter-wiring insulating layer220, or the first inter-wiring insulating layer120or a different material.

Such a structure allows the semiconductor device1to have the gaps150inside the recess in the first inter-wiring insulating layer120by stacking the uneven surface of the first inter-wiring insulating layer120and the planarized surface of the second inter-wiring insulating layer220. In the semiconductor device1, the first wiring layers130are thus formed in the gaps150provided in the recess in the first inter-wiring insulating layer120. This allows the semiconductor device1to have the gaps150each having a specific dielectric constant of 1 around the first wiring layers130even in a case where the first wiring layers130are formed in any layout. It is thus possible to reduce the inter-wiring capacitance of the first wiring layers130.

In addition, it is possible in the semiconductor device1to form the sealing film140on the first wiring layers130along the uneven shape of the first wiring layers130. This allows the semiconductor device1to prevent the first wiring layers130from being exposed to the gaps150and prevent the first wiring layers130from being oxidized by the oxygen or the moisture that may be included in the gaps150. This allows the semiconductor device1to prevent each of the first wiring layers130from having increased electric resistance due to oxidization and prevent the adhesion property from decreasing between the first wiring layer130and the first inter-wiring insulating layer120.

It is to be noted that, in a case where the substrate100is a semiconductor substrate, the first wiring layers130may be electrically coupled to various elements such as transistors formed on the substrate100via through vias formed in the inter-layer insulating film110. The structure of such a semiconductor device1A is described with reference toFIG. 2.FIG. 2is a vertical cross-sectional view schematically illustrating a structure example of the semiconductor device1A in a case where a through via160is formed in the inter-layer insulating film110.

As illustrated inFIG. 2, the through via160is provided to reach the substrate100from under the first wiring layer130through the first inter-wiring insulating layer120and the inter-layer insulating film110. This allows the through via160to electrically couple each of the various elements provided on the substrate100and the first wiring layer130. It is sufficient if the through vias160are provided as appropriate on the basis of the disposition of the various elements provided on the substrate100and the first wiring layers130. The number and disposition of through vias160are not particularly limited. The through vias160each include an electrically conductive material. For example, the through via160may include copper (Cu), aluminum (Al), tungsten (W), tantalum (Ta), titanium (Ti), ruthenium (Ru), or cobalt (Co). Alternatively, the through via160may include an alloy of these metals.

Needless to say, although not illustrated in any of the semiconductor devices1illustrated in the diagrams other thanFIG. 2, each of the semiconductor devices1illustrated in these diagrams may also be provided with the through vias160that electrically couple various elements provided on the substrate100and the first wiring layers130.

1.2. Example of Method of Manufacturing Semiconductor Device

Next, an example of the method of manufacturing the semiconductor device1according to the present embodiment is described with reference toFIGS. 3,4A, 4B, 4C, and 4D.

First, an overview of the method of manufacturing the semiconductor device1according to the present embodiment is described with reference toFIG. 3.FIG. 3is a schematic vertical cross-sectional view describing the overview of the method of manufacturing the semiconductor device1according to the present embodiment.

As illustrated inFIG. 3, it is possible to form the semiconductor device1by bonding a plurality of substrates together. Specifically, the substrate100and an opposed substrate200are first prepared. The substrate100is provided with the inter-layer insulating film110, the first inter-wiring insulating layer120, the first wiring layers130, the barrier layers131, the cap layers132, and the sealing film140. The opposed substrate200is provided with the second inter-wiring insulating layer220and the inter-layer insulating films211and212. Next, the substrate100and the opposed substrate200are bonded together to make the first inter-wiring insulating layer120and the first wiring layers130opposed to the second inter-wiring insulating layer220. This makes it possible to form the semiconductor device1.

In this case, a recess is formed on the bonding surface of the first inter-wiring insulating layer120of the substrate100and the bonding surface of the second inter-wiring insulating layer220of the opposed substrate200is planarized. This allows the semiconductor device1to form the gaps150on the bonding surface of the first inter-wiring insulating layer120and the second inter-wiring insulating layer220.

Next, the details of the method of manufacturing the semiconductor device1according to the present embodiment are described with reference toFIGS. 4A, 4B, 4C, and 4D.FIGS. 4A, 4B, 4C, and 4Dare schematic vertical cross-sectional views describing the respective steps of the method of manufacturing the semiconductor device1according to the present embodiment.

First, as illustrated inFIG. 4A, after the inter-layer insulating film110and the first inter-wiring insulating layer120are formed on the substrate100, the first wiring layers130embedded in the first inter-wiring insulating layer120are formed by using a damascene method and the cap layers132are formed.

Specifically, CVD (Chemical Vapor Deposiotion) or the like is used to form the inter-layer insulating film110and the first inter-wiring insulating layer120on the substrate100in order. The substrate100may be, for example, a silicon substrate. The inter-layer insulating film110may be formed by using, for example, SiO2. The first inter-wiring insulating layer120may be formed by using a low-dielectric-constant material (so-called low-k material).

Next, lithography or the like is used to form an opening in the first inter-wiring insulating layer120. The barrier layer131is formed inside the opening and a film of an electrically conductive material such as copper (Cu) is then formed to fill the opening. Afterward, the electrically conductive material such as copper (Cu) formed on the first inter-wiring insulating layer120other than the opening is removed by CMP (Chemical Mechanical Polish), full-surface etch-back, or the like and planarized to form the first wiring layer130. Subsequently, the cap layer132is formed on the planarized first inter-wiring insulating layer120and first wiring layers130. The barrier layers131may be each formed by using, for example, tantalum nitride (TaN), titanium nitride (TiN), or the like. In addition, the cap layer132may be formed by using the above-described material.

Next, as illustrated inFIG. 4B, a patterned mask layer151is formed on the cap layer132.

Specifically, lithography or the like is used to form the mask layer151patterned to cover the region not provided with the gap150(i.e., to have an opening in the region in which the gap150is provided). The mask layer151may be, for example, a photoresist or the like. Alternatively, the mask layer151may be a stack of a hard mask such as an oxide film or a nitride film and a photoresist.

It is to be noted that the mask layer151may be provided in the regions on the first inter-wiring insulating layer120or provided in the regions on the first wiring layers130. The region between the regions in which the mask layer151is provided on the first inter-wiring insulating layer120serves as a region in which a recess is formed in the first inter-wiring insulating layer120. In addition, through vias that electrically couple wiring lines formed in the second inter-wiring insulating layer220and the first wiring layers130are formed in a subsequent step in the regions in which the mask layer151is provided on the first wiring layers130.

Next, as illustrated inFIG. 4C, after the first inter-wiring insulating layer120around the first wiring layer130is selectively removed to form a recess153in the first inter-wiring insulating layer120, the sealing film140is formed on the first wiring layer130and the first inter-wiring insulating layer120.

Specifically, etching is performed by using the mask layer151illustrated inFIG. 4Bto remove the first inter-wiring insulating layer120and the first wiring layer130in the region that is not covered with the mask layer151and a recess is formed in the first inter-wiring insulating layer120. In this case, etching is performed to cause the first inter-wiring insulating layer120to have a higher etching rate than the etching rate of each of the first wiring layers130. This makes it possible to selectively remove the first inter-wiring insulating layer120around the first wiring layer130. The recess formed in the first inter-wiring insulating layer120may have, for example, a depth of 30 nm to 400 nm. In addition, a step of removing the whole or a portion of the cap layer132may be performed afterward.

Next, the sealing film140is conformally formed on the first wiring layers130and the first inter-wiring insulating layer120along the uneven shape of the first wiring layers130and the first inter-wiring insulating layer120. It is possible to perform such conformal film formation by using, for example, CVD, ALD (Atomic Layer Deposition), p-CVD (plasma CVD), or the like.

Next, as illustrated inFIG. 4D, the opposed substrate200on which the inter-layer insulating film211, the second inter-wiring insulating layer220, and the inter-layer insulating film212are stacked is bonded to the first wiring layer130and the first inter-wiring insulating layer120to form the gap150around the first wiring layer130.

Specifically, CVD or the like is first used to stack the inter-layer insulating film211, the second inter-wiring insulating layer220, and the inter-layer insulating film212on the opposed substrate200in order. The opposed substrate200may be, for example, a silicon substrate. The second inter-wiring insulating layer220may be formed by using a low-dielectric-constant material (so-called low-k material) and the inter-layer insulating films211and212may be formed by using, for example, SiO2.

Next, the substrate100and the opposed substrate200are bonded together to cause the first inter-wiring insulating layer120in which the recess is formed to be opposed to the second inter-wiring insulating layer220having a planarized principal surface. This makes it possible to form the gaps150between the first inter-wiring insulating layer120and the second inter-wiring insulating layer220.

It is to be noted that the bonding surface of the substrate100or the opposed substrate200may be irradiated with plasma or have moisture injected thereon, for example, before the step of bonding the substrate100and the opposed substrate200together. This activates the sealing film140and the inter-layer insulating film212to allow the junction strength to increase. The sealing film140and the inter-layer insulating film212serve as the junction surface of the substrate100and the opposed substrate200. In addition, the step of bonding the substrate100and the opposed substrate200together may be performed in a vacuum. This allows the gaps150to each have less oxygen or moisture left therein. It is therefore possible to further suppress the first wiring layer130being oxidized. Further, after the step of bonding the substrate100and the opposed substrate200together, a heat treatment step may be performed. This allow the junction strength of the sealing film140and the inter-layer insulating film212to further increase. The sealing film140and the inter-layer insulating film212serve as the junction surface of the substrate100and the opposed substrate200.

After the step illustrated inFIG. 4D, the opposed substrate200is peeled off from the inter-layer insulating film211. This allows the semiconductor device1illustrated inFIG. 1to be formed. Specifically, it is possible to remove or peel off the opposed substrate200from the inter-layer insulating film211by using full-surface etching, a back grinder, or the like.

The above-described manufacturing method makes it possible to bond the opposed substrate200and the substrate100together without taking the alignment with the first wiring layers130into consideration because the second inter-wiring insulating layer220or the inter-layer insulating film212is planarized and insulated. The second inter-wiring insulating layer220or the inter-layer insulating film212is the bonding surface of the opposed substrate200. Such a manufacturing method thus makes it possible to manufacture the semiconductor device1with higher productivity.

1.3. Modification Examples of Semiconductor Device

Next, modification examples of the semiconductor device1according to the present embodiment are described with reference toFIGS. 5A, 5B, and 5C.FIGS. 5A, 5B, and 5Care vertical cross-sectional views schematically illustrating structure examples of semiconductor devices according to first to third modification examples, respectively.

First Modification Example

As illustrated inFIG. 5A, a semiconductor device2A according to the first modification example is different from the semiconductor device1in that there is provided a second wiring layer230inside the second inter-wiring insulating layer220and the second wiring layer230and the first wiring layer130are electrically coupled by a through via235. The semiconductor device2A according to the first modification example allows wiring lines to run in more layers.

Specifically, the second wiring layers230are each provided to be embedded in the surface side opposed to the surface of the second inter-wiring insulating layer220that is opposed to the recess of the first inter-wiring insulating layer120. The second wiring layers230are not particularly limited, but formable in any layout. The second wiring layers230each include an electrically conductive material. For example, the second wiring layer230may include copper (Cu), aluminum (Al), ruthenium (Ru), or cobalt (Co). Alternatively, the second wiring layer230may include an alloy (e.g., Cu—Mn alloy, Al—Cu alloy, or the like) of these metals. For example, in a case where the second wiring layer230includes copper (Cu) or copper alloy, it is possible to easily form the second wiring layer230to cause the second wiring layer230to be embedded in the second inter-wiring insulating layer220by using a damascene method.

A barrier layer231includes metal having a high barrier property with respect to an atom. The barrier layer231is provided on the surface of the second wiring layer230on which the second wiring layer230and the second inter-wiring insulating layer220are in contact. A cap layer232includes a material having low permeability with respect to moisture, oxygen, or the like. The cap layer232is provided on the second wiring layer230and the second inter-wiring insulating layer220. The functions and materials of the barrier layer231and the cap layer232are substantially similar to those of the barrier layer131and the cap layer132and are not thus described here.

The through via235is provided to reach the first wiring layer130from under the second wiring layer230through the second inter-wiring insulating layer220, the inter-layer insulating film212, the sealing film140, and the cap layer132. This allows the through via235to electrically couple the first wiring layer130and the second wiring layer230. The through via235is provided in the region in which the first wiring layer130is in contact with the second inter-wiring insulating layer220with the inter-layer insulating film212, the sealing film140, and the cap layer132interposed therebetween. In the region in which the first wiring layer130is in contact with the second inter-wiring insulating layer220, the gap150is not formed between the first wiring layer130and the second inter-wiring insulating layer220. This makes it possible to form the through via235more easily.

It is to be noted that each of the other components is substantially similar to the component of the semiconductor device1described with reference toFIG. 1and therefore is not described here.

The semiconductor device2A like this allows wiring lines to run in more layers.

Second Modification Example

As illustrated inFIG. 5B, a semiconductor device2B according to the second modification example is different from the semiconductor device2A in that the first inter-wiring insulating layer120having the first wiring layers130and the gaps150formed inside the recess is further formed again. The semiconductor device2B according to the second modification example makes it possible to reduce the inter-wiring capacitance of the respective wiring lines formed in a plurality of layers.

Specifically, a third inter-wiring insulating layer320is provided above the first inter-wiring insulating layer120with an inter-layer insulating film312interposed therebetween. The gaps150are formed by the planarized surface of the third inter-wiring insulating layer320and the recess in the first inter-wiring insulating layer120. In addition, the third inter-wiring insulating layer320is provided with third wiring layers330, barrier layers331, cap layers332, and a sealing film340. These components form gaps350as with the first inter-wiring insulating layer120. In the semiconductor device2B illustrated inFIG. 5B, the first wiring layers130and the third wiring layers330have the same layout, but the first wiring layers130and the third wiring layers330may be independently laid out.

The third wiring layer330is electrically coupled to the first wiring layer130by a through via325provided by penetrating the third inter-wiring insulating layer320, the inter-layer insulating film312, the sealing film140, and the cap layer132from under the third wiring layer330. The third wiring layer330is electrically coupled to the second wiring layer230by a through via225provided by penetrating the second inter-wiring insulating layer220, the inter-layer insulating film212, the sealing film340, and the cap layer332from under the second wiring layer230. This makes it possible to electrically couple the first wiring layers130and the third wiring layers330provided with the gaps150and350between the wiring lines and the second wiring layer230to each other.

It is to be noted that the respective components of the third inter-wiring insulating layer320, the third wiring layer330, the barrier layer331, the cap layer332, the sealing film340, and a through via335are substantially similar to those of the first inter-wiring insulating layer120, the first wiring layer130, the barrier layer131, the cap layer132, the sealing film140, and the through via235and are not thus described here.

The semiconductor device2B like this makes it possible to reduce the inter-wiring capacitance of the respective wiring lines formed in a plurality of layers.

Third Modification Example

As illustrated inFIG. 5C, a semiconductor device2C according to the third modification example is different from the semiconductor device2B in that a fifth inter-wiring insulating layer520, a fifth wiring layer530, a fourth inter-wiring insulating layer420, a fourth wiring layer430, and the like are formed and a semiconductor substrate500is further bonded on which a circuit having a predetermined function. The semiconductor device2C according to the third modification example makes it possible to reduce the inter-wiring capacitance in a stacked semiconductor device in which substrates on which circuits having different functions are formed are stacked. For example, the substrate100may be provided with a pixel circuit in which a plurality of pixels is arranged and the semiconductor substrate500may be provided with a logic circuit that performs information processing on pixel signals subjected to photoelectric conversion by a pixel unit.

On the semiconductor substrate500, various elements such as transistors are formed. The semiconductor substrate500may be formed by using Si, Ge, GaAs, GaN, SiC, or the like.

The semiconductor substrate500may have any stacked structure. For example, the fifth inter-wiring insulating layer520may be provided above the semiconductor substrate500with an inter-layer insulating film511interposed therebetween. The fifth wiring layers530may be provided to be embedded in the fifth inter-wiring insulating layer520. There may be provided a fourth inter-wiring insulating layer410above the fifth wiring layers530and the fifth inter-wiring insulating layer520with a cap layer513interposed therebetween. The fourth wiring layers430may be provided embedded in the fourth inter-wiring insulating layer410. In this case, the contact surfaces between the fifth wiring layers530and the fifth inter-wiring insulating layer520and the contact surfaces between the fourth wiring layers430and the fourth inter-wiring insulating layer420may be provided with barrier layers531and431, respectively.

Here, the fourth wiring layers430are each provided to be exposed on the surface of the fourth inter-wiring insulating layer420and the second wiring layers230are each similarly provided to be exposed on the surface of the second inter-wiring insulating layer220. This allows the second wiring layer230and the fourth wiring layer430to form electrical coupling by joining the electrically conductive materials (e.g., copper or copper alloy) exposed on the surfaces to each other by heat treatment or the like. This allows the second wiring layer230and the fourth wiring layer430to be electrically coupled even without forming any through via or the like between the second wiring layer230and the fourth wiring layer430. It is thus possible to further simplify the step of manufacturing the semiconductor device2C.

It is to be noted that the fourth inter-wiring insulating layer420and the fifth inter-wiring insulating layer520are substantially similar to the first inter-wiring insulating layer120. The fourth wiring layers430and the fifth wiring layers530are substantially similar to the first wiring layers130. The inter-layer insulating film511is substantially similar to the inter-layer insulating film312. A cap layer512is substantially similar to the cap layer132. The barrier layers431and531are substantially similar to the barrier layer131. They are not thus described here.

The semiconductor device2C like this makes it possible to reduce the inter-wiring capacitance of wiring lines by forming the gaps150and350in a stacked semiconductor device.

2. Second Embodiment

2.1. First Structure Example of Solid-State Imaging Device

Next, a first structure example of a solid-state imaging device according to a second embodiment of the present disclosure is described with reference toFIGS. 6A, 6B, 7A, and 7B.FIG. 6Ais a vertical cross-sectional view schematically illustrating the first structure example of the solid-state imaging device according to the present embodiment.FIG. 6Bis an explanatory diagram schematically illustrating a pixel circuit of the solid-state imaging device according to the present embodiment.FIGS. 7A and 7Bis planar cross-sectional views each schematically illustrating the planar disposition of the first structure example of the solid-state imaging device according to the present embodiment.

As illustrated inFIG. 6A, a solid-state imaging device10includes inter-layer insulating films710,737, and757and inter-wiring insulating layers720,730,740,750, and760stacked on a semiconductor substrate700such as a silicon substrate. The inter-wiring insulating layers720,730,740, and750are respectively provided with wiring layers723,733,743, and753each including copper, copper alloy, or the like. The wiring layers723,733,743, and753are electrically coupled, for example, by through vias732,742, and752that respectively penetrate the inter-wiring insulating layers730,740, and750. It is to be noted that the contact surfaces between the wiring layers723,733,743, and753and the inter-wiring insulating layers720,730,740, and750may be provided with barrier layers721,731,741, and751. The upper surfaces of the wiring layers733and753may be provided with cap layers736and756.

In the semiconductor substrate700, a photodiode (not illustrated), a power supply (not illustrated), a floating diffusion711, and the like are formed. On the semiconductor substrate700, a plurality of transistors712is formed that includes a transfer transistor, a reset transistor, an amplifying transistor, a selection transistor, and the like. That is, the semiconductor substrate700is provided with the pixel unit of the solid-state imaging device10. The pixel unit of the solid-state imaging device10may include, for example, the pixel circuit illustrated inFIG. 6B.

Specifically, as illustrated inFIG. 6B, the solid-state imaging device10according to the present embodiment includes an imaging unit13(so-called pixel unit) and peripheral circuits. In the imaging unit13(so-called pixel unit), a plurality of pixels12is regularly arranged two-dimensionally. The peripheral circuits include a vertical driving unit14, a horizontal transfer unit15, and an output unit16. The peripheral circuits are disposed around the imaging unit13. The pixels12may each include one photodiode PD, one floating diffusion FD, and four transistors: a transfer transistor Tr1; a reset transistor Tr2; an amplifying transistor Tr3; and a selection transistor Tr4. It is to be noted that the floating diffusion FD and the four transistors of the transfer transistor Tr1, the reset transistor Tr2, the amplifying transistor Tr3, and the selection transistor Tr4do not necessarily have to be provided on the same substrate as that of the photodiode PD. For example, the floating diffusion FD and all or a portion of the four transistors may be provided on a substrate different from the substrate provided with the photodiode PD.

The photodiode PD is a photoelectric conversion element that generates signal charges by photoelectrically converting incident light. The transfer transistor Tr1is a transistor that reads out the signal charges accumulated in the photodiode PD into the floating diffusion FD described below. The floating diffusion FD is a region that is provided between the transfer transistor Tr1and the reset transistor Tr2and accumulates signal charges. The reset transistor Tr2is a transistor for setting the electric potential of the floating diffusion FD at a predefined value. The amplifying transistor Tr3is a transistor for electrically amplifying the signal charges read out into the floating diffusion FD. The selection transistor Tr4is a transistor for reading out amplified pixel signals into a vertical signal line18by selecting one row of the pixel unit of the solid-state imaging device10. It is to be noted that the selection transistor does not have to be provided depending on the configuration of the pixel12thought not illustrated.

These components are electrically coupled to each other, thereby forming the circuits of the pixel12. Specifically, the source of the transfer transistor Tr1is coupled to the photodiode PD and the drain of the transfer transistor Tr1is coupled to the source of the reset transistor Tr2. The floating diffusion FD (corresponding to the drain region of the transfer transistor Tr1and the source region of the reset transistor Tr2) between the transfer transistor Tr1and the reset transistor Tr2is coupled to the gate of the amplifying transistor Tr3. The source of the amplifying transistor Tr3is coupled to the drain of the selection transistor Tr4. The drain of the reset transistor Tr2and the drain of the amplifying transistor Tr3are coupled to the power supply. In addition, the source of the selection transistor Tr4is coupled to the vertical signal line18.

In addition, these components output pixel signals from the pixel12in the operations as described below. Specifically, first, the charges of the photodiode PD are all emptied by turning on the gate of the transfer transistor Tr1and the gate of the reset transistor Tr2. Next, charges are accumulated by turning off the gate of the transfer transistor Tr1and the gate of the reset transistor Tr2. Subsequently, the electric potential of the floating diffusion FD is reset by turning on the gate of the reset transistor Tr2immediately before the charges of the photodiode PD are read out. Afterward, the charges are transferred from the photodiode PD to the floating diffusion FD by turning off the gate of the reset transistor Tr2and turning on the gate of the transfer transistor Tr1. The amplifying transistor Tr3electrically amplifies signal charges in response to the application of the charges to the gate. Meanwhile, the selection transistor Tr4reads image signals subjected to charge-voltage conversion by the amplifying transistor Tr3into the vertical signal line18by turning on only a pixel to be read when the floating diffusion FD is reset.

The vertical driving unit14supplies a row reset signal φRST applied in common to the gates of the reset transistors Tr2of pixels arranged in one row. In addition, the vertical driving unit14similarly supplies a row transfer signal φTRG applied in common to the gates of the transfer transistors Tr1of the pixels in one row. Further, the vertical driving unit14similarly supplies a row selection signal φSEL applied in common to the gates of the selection transistors Tr4in one row.

The horizontal transfer unit15includes, for example, an analog/digital converter19coupled to the vertical signal line18of each column, a column selection circuit SW (e.g., switch), and a horizontal transfer line20(e.g., bus wiring line including the same number of wiring lines as the number of data bit lines). The output unit16includes, for example, a signal processing circuit21that processes an output from the horizontal transfer line20and an output buffer22.

In the solid-state imaging device10like this, the signals of the pixels12in the respective rows are subjected to analog/digital conversion by the respective analog/digital converters19, read out through the sequentially selected column selection circuits SW into the horizontal transfer lines20, and subsequentially transferred horizontally. The image data read out into the horizontal transfer line20is outputted from the output buffer22through the signal processing circuit21.

Description is given with reference toFIG. 6Aagain. The wiring layer723is provided inside the recess in the inter-wiring insulating layer720. There is provided a gap725around the wiring layer723. The gap725is formed by the recess in the inter-wiring insulating layer720and the inter-layer insulating film737. In addition, the wiring layer743is provided inside the recess in the inter-wiring insulating layer740. There is provided a gap745around the wiring layer743. The gap745is formed by the recess in the inter-wiring insulating layer740and the inter-layer insulating film757. This allows the solid-state imaging device10to further reduce the inter-wiring capacitance of the wiring layers723and743.

The wiring layers723and743whose inter-wiring capacitance is reduced may be, for example, FD (floating diffusion) wiring lines or vertical signal lines. Such a configuration is described with reference toFIGS. 7A and 7B.

As illustrated inFIG. 7A, the wiring layer743is a vertical signal line. The wiring layer743may be a wiring line that extends and couples the respective pixels arranged in a matrix in one direction (e.g., column direction). In this case, the gap745may be provided in the region between the through vias752that are each coupled to the wiring layer743. The solid-state imaging device10uses the gap745to reduce the inter-wiring capacitance of the wiring layers743, thereby allowing the transmission speed of analog signals to increase.

As illustrated inFIG. 7B, the wiring layer723is an FD wiring line. The wiring layer723may be a wiring line for a path through which signal charges subjected to photoelectric conversion by a photodiode are transmitted to the plurality of transistors712. In this case, the gap725may be provided in a region other than the region around the through via732that is coupled to the wiring layer723. The solid-state imaging device10uses the gap725to reduce the inter-wiring capacitance of the wiring layers723, thereby making it possible to further increase the conversion efficiency of converting signal charges to pixel signals. The wiring layers723are provided in complicated layout depending on the layout of the photodiodes of the respective pixels and various transistors. Accordingly, the use of the technology according to the present disclosure that makes it possible to form a gap even between wiring lines in any layout allows the gap725to be more certainly provided between the wiring lines of the wiring layers723.

2.2. Second Structure Example of Solid-State Imaging Device

Next, a second structure example of the solid-state imaging device according to the present embodiment is described with reference toFIG. 8.FIG. 8is a vertical cross-sectional view schematically illustrating the second structure example of the solid-state imaging device according to the present embodiment.

In the solid-state imaging device, PD (photodiode)20019receives incident light20001coming from the back surface (upper surface in the diagram) side of a semiconductor substrate20018. Above the PD20019, a planarization film20013, CF (color filter)20012, and a microlens20011are provided. The incident light20001sequentially passing through the respective units is received by a light reception surface20017and is subjected to photoelectric conversion.

For example, in the PD20019, an n-type semiconductor region20020is formed as a charge accumulation region that accumulates charges (electrons). In the PD20019, the n-type semiconductor region20020is provided inside p-type semiconductor regions20016and20041of the semiconductor substrate20018. The n-type semiconductor region20020is provided with the p-type semiconductor region20041on the front surface (lower surface) side of the semiconductor substrate20018. The p-type semiconductor region20041has higher impurity concentration than that of the back surface (upper surface) side. That is, the PD20019has an HAD (Hole-Accumulation Diode) structure. The p-type semiconductor regions20016and20041are formed to suppress the generation of dark currents at the respective interfaces with the upper surface side and lower surface side of the n-type semiconductor region20020.

A pixel separation unit20030that electrically separates a plurality of pixels20010from each other is provided inside the semiconductor substrate20018and the PD20019is provided in a region defined by this pixel separation unit20030. In the diagram, in a case where the solid-state imaging device is viewed from the upper surface side, the pixel separation units20030are formed in a lattice, for example, to be interposed between the plurality of pixels20010. The PDs20019are each formed in the region defined by this pixel separation unit20030.

In each PD20019, the anode is grounded. In the solid-state imaging device, the signal charges (e.g., electrons) accumulated by the PD20019are read out via transfer Tr (MOS FET) or the like that is not illustrated and outputted as electric signals to VSL (vertical signal line) that is not illustrated. It is to be noted that there may be provided a pixel circuit including a plurality of Tr and FD as described in the first structure example from the transfer Tr to the VSL.

A wiring layer20050is provided on the front surface (lower surface) of the semiconductor substrate20018that is opposite to the back surface (upper surface) provided with the respective units such as a light-shielding film20014, the CF20012, and the microlens20011.

The wiring layer20050includes a wiring line20051and an insulating layer20052. The wiring line20051is formed to be electrically coupled to each element in the insulating layer20052. The wiring layer20050is a so-called multi-layer wiring layer and is formed by alternately stacking interlayer insulating films and the wiring lines20051a plurality of times. The inter-layer insulating films are included in the insulating layer20052. Here, as the wiring lines20051, wiring lines to Tr such as the transfer Tr for reading out charges from the PD20019or respective wiring lines such as the VSL are stacked with the insulating layer20052interposed therebetween.

The wiring layer20050is provided with a support substrate20061on the surface opposite to the side on which the PD20019is provided. For example, a substrate including a silicon semiconductor and having a thickness of several hundreds of μm is provided as the support substrate20061.

The light-shielding film20014is provided on the back surface (upper surface in the diagram) side of the semiconductor substrate20018.

The light-shielding film20014is configured to block a portion of the incident light20001from above the semiconductor substrate20018toward the back surface of the semiconductor substrate20018.

The light-shielding film20014is provided above the pixel separation unit20030provided inside the semiconductor substrate20018. Here, the light-shielding film20014is provided to protrude on the back surface (upper surface) of the semiconductor substrate20018in the shape of a projection with an insulating film20015such as a silicon oxide film interposed therebetween. In contrast, to make the incident light20001enter the PD20019, the light-shielding film20014is not provided, but there is an opening above the PD20019provided inside the semiconductor substrate20018.

That is, in a case where the solid-state imaging device is viewed from the upper surface side in the diagram, the light-shielding film20014has a grid planar shape and an opening through which the incident light20001passes to the light reception surface20017is formed.

The light-shielding film20014includes a light-shielding material that blocks light. For example, titanium (Ti) films and tungsten (W) films are sequentially stacked to form the light-shielding film20014. In addition, it is possible to form the light-shielding film20014by sequentially stacking, for example, titanium nitride (TiN) films and tungsten (W) films.

The light-shielding film20014is covered with the planarization film20013. The planarization film20013is formed by using an insulating material that transmits light.

The pixel separation unit20030includes a groove20031, a fixed-charge film20032, and an insulating film20033.

The fixed-charge film20032is formed on the back surface (upper surface) side of the semiconductor substrate20018to cover the groove20031that defines the space between the plurality of pixels20010.

Specifically, the fixed-charge film20032is provided to cover the inner surface of the groove20031formed on the back surface (upper surface) side of the semiconductor substrate20018with a predetermined thickness. The insulating film20033is then provided to fill (be loaded into) the inside of the groove20031covered with the fixed-charge film20032.

Here, the fixed-charge film20032is formed by using a high dielectric material having a negative fixed charge to form a positive-charge (hole) accumulation region at the interface with the semiconductor substrate20018and suppress the generation of dark currents. The fixed-charge film20032is formed to have a negative fixed charge. This causes the negative fixed charge to apply an electric field to the interface with the semiconductor substrate20018and forms a positive-charge (hole) accumulation region.

It is possible to form the fixed-charge film20032by using, for example, a hafnium oxide film (HfO2film). In addition, it is possible to form the fixed-charge film20032to cause the fixed-charge film20032to additionally include at least one of oxides of hafnium, zirconium, aluminum, tantalum, titanium, magnesium, yttrium, lanthanide elements, or the like, for example.

Here, the technology according to the present disclosure is applicable to the wiring layer20050of the solid-state imaging device as described above.

2.3. Third Structure Example of Solid-State Imaging Device

Next, a third structure example of the solid-state imaging device according to the present embodiment is described with reference toFIG. 9.FIG. 9is a vertical cross-sectional view schematically illustrating the third structure example of the solid-state imaging device according to the present embodiment.

FIG. 9illustrates a configuration example of a stacked solid-state imaging device. As illustrated inFIG. 9, a solid-state imaging device23020is configured as one semiconductor chip in which the two dies of a sensor die23021and a logic die23024are stacked and electrically coupled.

In the sensor die23021, PDs (photodiodes), FDs (floating diffusions), and Trs (MOS FETs) included in pixels serving as a pixel region, Tr serving as a control circuit, and the like are formed. Further, a wiring layer23101including a wiring line23110with a plurality of layers is formed in the sensor die23021. In this example, the wiring line23110includes three layers. It is to be noted that it is possible to include (Tr serving as) a control circuit in not the sensor die23021, but the logic die23024. It is to be noted that there may be provided a pixel circuit including a plurality of Tr and FD as described in the first structure example in the sensor die23021.

In the logic die23024, Tr included in a logic circuit is formed. Further, a wiring layer23161including a wiring line23170with a plurality of layers is formed in the logic die23024. In this example, the wiring line23170includes three layers. In addition, a contact hole23171having an insulating film23172formed on the inner wall surface thereof is formed in the logic die23024. The contact hole23171is filled with an interconnecting conductor23173to be coupled to the wiring line23170and the like.

The sensor die23021and the logic die23024are bonded together with the wiring layers23101and23161thereof opposed to each other. This forms the stacked solid-state imaging device23020in which the sensor die23021and the logic die23024are stacked.

The solid-state imaging device23020is formed by superimposing the sensor die23021on the logic die23024to bring the wiring lines23110and23170into direct contact, heating them while applying a desired weight, and directly joining the wiring lines23110and23170. This electrically couples the sensor die23021and the logic die23024via the wiring layer23101and the wiring layer23161.

The technology according to the present disclosure is applicable to the wiring layers23101and23161of the solid-state imaging device23020as described above.

2.4. Fourth Structure Example of Solid-State Imaging Device

Next, a fourth structure example of the solid-state imaging device according to the present embodiment is described with reference toFIG. 10.FIG. 10is a vertical cross-sectional view schematically illustrating the fourth structure example of the solid-state imaging device according to the present embodiment.

FIG. 10illustrates a configuration example of a stacked solid-state imaging device. A solid-state imaging device23401has a three-layer stacked structure in which the three dies of a sensor die23411, a logic die23412, and a memory die23413are stacked. This electrically couples the three dies of the sensor die23411, the logic die23412, and the memory die23413to configure the solid-state imaging device23401as one semiconductor chip.

InFIG. 10, the logic die23412and the memory die23413are stacked under the sensor die23411in this order, but it is possible to stack the logic die23412and the memory die23413under the sensor die23411in the inverse order, that is, in the order of the memory die23413and the logic die23412.

In the logic die23412, Tr included in a logic circuit is formed.

The memory die23413includes a memory circuit that stores, for example, data which is temporarily necessary in signal processing performed in the logic die23412.

PD serving as a photoelectric conversion section of a pixel and a source/drain region of a pixel Tr are formed in the sensor die23411. There may be provided a pixel circuit including a plurality of Tr and FD as described in the first structure example in the sensor die23411.

A gate electrode is formed around PD with a gate insulating film interposed therebetween. The gate electrode and the paired source/drain regions form a pixel Tr23421and a pixel Tr23422.

The pixel Tr23421adjacent to the PD is transfer Tr and one of the paired source/drain regions included in the pixel Tr23421is FD.

In addition, an inter-layer insulating film is formed in the sensor die23411and contact holes are formed in the inter-layer insulating film. Interconnecting conductors23431coupled to the pixel Tr23421and the pixel Tr23422are formed in the contact holes.

Further, a wiring layer23433including a multi-layer wiring line23432coupled to each of the interconnecting conductors23431is formed in the sensor die23411.

In addition, an aluminum pad23434serving as an electrode for external coupling is formed in the lowermost layer of the wiring layer23433in the sensor die23411. That is, the aluminum pad23434is formed at a position closer to a joint surface23440with the logic die23412than the wiring line23432in the sensor die23411. The aluminum pad23434is used as an end of a wiring line for inputting and outputting signals to and from the outside.

Further, a contact23441is formed in the sensor die23411. The contact23441is used for electrical coupling to the logic die23412. The contact23441is coupled to a contact23451in the logic die23412and is also coupled to an aluminum pad23442in the sensor die23411.

In the sensor die23411, a pad hole23443is then formed to reach the aluminum pad23442from the back surface side (upper side) of the sensor die23411.

The technology according to the present disclosure is applicable to the wiring layer23433of the solid-state imaging device23401as described above.

3. Application Examples

(Application to Endoscopic Surgery System)

The technology (the present technology) according to the present disclosure is applicable to a variety of products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

FIG. 12is a block diagram depicting an example of a functional configuration of the camera head11102and the CCU11201depicted inFIG. 11.

The above has described the example of the endoscopic surgery system to which the technology according to the present disclosure may be applied. The technology according to the present disclosure may be applied, for example, to the image pickup unit11402or the like of the camera head11102among the above-described components. Specifically, the solid-state imaging device10illustrated inFIG. 6Aor the like is applicable to the image pickup unit10402. Applying the technology according to the present disclosure to the image pickup unit10402makes it possible to offer a clearer surgical region image with less latency. This allows a surgeon to treat a surgical region as if the surgeon directly observed the surgical region.

It is to be noted that the endoscopic surgery system has been described here as an example, but the technology according to the present disclosure may be additionally applied, for example, to a microscopic surgery system or the like.

(Example of Application to Mobile Body)

For example, the technology according to the present disclosure may be achieved as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a vessel, or a robot.

FIG. 14is a diagram depicting an example of the installation position of the imaging section12031.

The above has described the example of the vehicle control system to which the technology according to the present disclosure may be applied. The technology according to the present disclosure is applicable, for example, to the imaging section12031or the like among the above-described components. Specifically, the solid-state imaging device10illustrated inFIG. 6Aor the like is applicable to the imaging section12031. Applying the technology according to the present disclosure to the imaging section12031makes it possible to offer a clearer shot image. This allows the vehicle control system to have higher image recognition accuracy.

A preferred embodiment(s) of the present disclosure has/have been described above in detail with reference to the accompanying drawings, but the technical scope of the present disclosure is not limited to such an embodiment(s). A person skilled in the art may find various alterations and modifications within the scope of the appended claims, and it should be understood that they will naturally come under the technical scope of the present disclosure.

In addition, the effects described herein are merely illustrative and exemplary, but not limitative. That is, the technology according to the present disclosure may exert other effects that are apparent to those skilled in the art from the description herein in addition to the above-described effects or in place of the above-described effects.

It is to be noted that the following configurations also fall within the technical scope of the present disclosure.

A semiconductor device including:

a first inter-wiring insulating layer that is provided on a substrate and includes a recess on a side opposite to the substrate;

a first wiring layer that is provided inside the recess in the first inter-wiring insulating layer;

a sealing film that is provided along an uneven shape of the first wiring layer and the first inter-wiring insulating layer;

a second inter-wiring insulating layer that is provided on the first inter-wiring insulating layer to cover the recess, the second inter-wiring insulating layer having a planarized surface that is opposed to the recess; and

a gap that is provided between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer.

The semiconductor device according to (1), in which the first wiring layer is provided to project from a bottom surface of the recess.

The semiconductor device according to (2), in which

height of a portion of the first wiring layers is lower than height of the first inter-wiring insulating layer, and

the gap is further provided between the second inter-wiring insulating layer and a portion of the first wiring layers.

a plurality of the first wiring layers is provided inside the recess, and

the gaps are continuously provided between a plurality of the first wiring layers.

The semiconductor device according to any one of (1) to (4), in which a junction surface between the first inter-wiring insulating layer and the second inter-wiring insulating layer is provided with the sealing film.

The semiconductor device according to any one of (1) to (5), in which a surface of the second inter-wiring insulating layer is provided with a silicon oxide film or a silicon nitride film.

The semiconductor device according to any one of (1) to (6), in which a surface of the first wiring layer in contact with the first inter-wiring insulating layer is provided with a barrier layer including an element of any of titanium, tantalum, ruthenium, or cobalt.

The semiconductor device according to any one of (1) to (7), in which

a second wiring layer is further provided on the second inter-wiring insulating layer, and

a through via provided by penetrating the second inter-wiring insulating layer is further provided in a region in which the second inter-wiring insulating layer and the first wiring layer are in contact, the through via electrically coupling the second wiring layer and the first wiring layer.

The semiconductor device according to (8), in which

the second inter-wiring insulating layer includes a recess on a side opposite to the substrate,

the second wiring layer is provided inside the recess in the second inter-wiring insulating layer,

a third inter-wiring insulating layer is further provided on the second inter-wiring insulating layer to cover the recess in the second inter-wiring insulating layer, the third inter-wiring insulating layer having a planarized surface that is opposed to the recess, and

a gap is further provided between the third inter-wiring insulating layer and the second wiring layer and the second inter-wiring insulating layer.

The semiconductor device according to any one of (1) to (9), further including a stacked substrate including a semiconductor substrate on which a circuit having a predetermined function is formed and a multi-layer wiring layer that is stacked on the semiconductor substrate, in which

the stacked substrate is bonded to the substrate to have the multi-layer wiring layer opposed to a surface on a side on which the second inter-wiring insulating layer is provided.

The semiconductor device according to (10), in which the semiconductor substrate or the substrate is provided with a pixel unit in which a plurality of pixels is arranged.

The semiconductor device according to (11), in which

the semiconductor substrate is provided with a logic circuit, and

the substrate is provided with the pixel unit.

The semiconductor device according to (12), in which the first wiring layer includes a floating diffusion wiring line that accumulates a charge from a photoelectric conversion element corresponding to each of the plurality of pixels.

The semiconductor device according to (12) or (13), in which the first wiring layer includes a vertical signal line that transmits pixel signals from the plurality of pixels.

A method of manufacturing a semiconductor device, the method including:

forming a first inter-wiring insulating layer on a substrate, the first inter-wiring insulating layer having a first wiring layer embedded on a side opposite to the substrate;

forming a recess in the first inter-wiring insulating layer and exposing the first wiring layer inside the recess;

providing a sealing film along an uneven shape of the first wiring layer and the first inter-wiring insulating layer; and

providing a second inter-wiring insulating layer on the first inter-wiring insulating layer to cover the recess and forming a gap between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer, the second inter-wiring insulating layer having a planarized surface that is opposed to the recess.

REFERENCE SIGNS LIST