Display device

A display device is provided. The display device includes an internal driving circuit, an external circuit and a plurality of signal lines. The signal lines are electrically connected with the internal driving circuit and the external circuit. Each signal line includes N signal line sections, Ma first turning points and Mb second turning points, wherein the N signal line sections are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of the two adjacent signal line sections, N and Ma are positive integers, Mb is 0 or a positive integer, N≥3, Ma≥2, Ma+Mb≤N−1, the resistance change rate between the two adjacent signal line sections connected with each first turning point is ΔR, and 0<|ΔR|≤10%.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 108144203, filed on Dec. 4, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The present invention relates to a display device, and more particularly, to a display device with an internal driving circuit.

Description of Related Art

In order to realize a slim border display panel, gate driver-on-array (GOA) technology has been developed, which is a technology that an external driving chip is replaced by arranging a gate driving circuit structure in the peripheral area of the display panel. As the requirements of the display panel for resolution continue to increase, in order to meet the requirements of the slim border design, the signal line density of the display panel using GOA technology in the peripheral area is bound to increase. As a result, the temperature rising degree of the signal lines caused by the impedance mismatch of the signal line is likely to increase due to the increased signal line density, thereby causing safety problems.

SUMMARY

The present invention provides a display device, which can effectively suppress the temperature rising degree of the signal line in the peripheral area with high resolution and slim border.

A display device provided by an embodiment of the present invention has a display area and a peripheral area. The peripheral area is located at at least one side of the display area and includes an internal drive circuit area and a wiring area. The display device includes a pixel array, an internal driving circuit, and a plurality of signal lines. The pixel array is disposed in the display area. The internal driving circuit is disposed in the internal driving circuit area, and is electrically connected with the pixel array. The plurality of signal lines are disposed in the wiring area, and are electrically connected with the internal driving circuit and an external circuit, wherein each of these signal lines includes N signal line segments, Ma first turning points and Mb second turning points, the N signal line segments are connected with each other, each of the Ma first turning points and the Mb second turning points is located at a connecting site of two adjacent signal line segments, wherein N and Ma are positive integers, Mb is a positive integer or 0, N≥3, Ma≥2, Ma+Mb≤N−1, and a resistance change rate between two adjacent signal line segments connected with each first turning point is ΔR, 0<|ΔR≤10%.

A display device provided by another embodiment of the present invention has a display area and a peripheral area. The peripheral area is located at at least one side of the display area and includes an internal driving circuit area and a wiring area. The display device includes a pixel array, an internal driving circuit, and a plurality of signal lines. The pixel array is disposed in the display area. The internal driving circuit is disposed in the internal driving circuit area, and is electrically connected with the pixel array. The plurality of signal lines are disposed in the wiring area, and are electrically connected with the internal driving circuit and an external circuit, wherein each of these signal lines includes N signal line segments, Ma first turning points and Mb second turning points, the N signal line segments are connected with each other, and each of the Ma first turning points and the Mb second turning points is located at a connecting site of two adjacent signal line segments, wherein N and Ma are positive integers, Mb is a positive integer or 0, N≥3, Ma≥2, Ma+Mb≤N−1, and a width change rate between two adjacent signal line segments connected with each first turning point is ΔW, 0<|ΔW|≤10%.

Based on the above, in the display device of the present invention, by adjusting the layout design of the signal lines located in the wiring area and electrically connected with the external circuit and the internal driving circuit, the temperature rising degree of the signal lines can be effectively suppressed. In this way, the display device of the present invention can avoid the problem of safety due to excessive temperature, and can be beneficial to be designed with high resolution and slim border.

DESCRIPTION OF THE EMBODIMENTS

Several embodiments of the disclosure will be disclosed below with reference to drawings. For clarity, many details in practice will be described together with the following description. However, it should be understood that these details in practice are not used to limit the disclosure. That is, in some embodiments of the disclosure, these details in practice are unnecessary. In addition, to simplify the drawings, some conventional structures and elements in the drawings will be shown in a simple and schematic manner.

The term “about,” “approximately,” “essentially” or “substantially” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by those skilled in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within, for example, ±30%, ±20%, ±15%, ±10%, ±5% of the stated value. Moreover, a relatively acceptable range of deviation or standard deviation may be chosen for the term “about,” “approximately,” “essentially” or “substantially” as used herein based on optical properties, etching properties or other properties, instead of applying one standard deviation across all the properties.

In the accompanying drawings, thicknesses of layers, films, panels, regions and so on are exaggerated for clarity. Throughout the specification, the same reference numerals in the accompanying drawings denote the same elements. It should be understood that when an element such as a layer, film, region or substrate is referred to as being “on” or “connected to” another element, it can be directly on or connected to the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly connected to” another element, there are no intervening elements present. As used herein, the term “connected” may refer to physically connected and/or electrically connected (or coupled). Therefore, the electrical connection (or coupling) may be refer an intervening elements exist between two elements.

FIG. 1is a schematic top view of a display device according to an embodiment of the invention.FIG. 2is an enlarged schematic view of one signal line inFIG. 1.

Referring toFIG. 1, in the embodiment, the display device10may include a substrate100, a pixel array102, an internal driving circuit104, a plurality of signal lines106, a substrate200and an external circuit300. From another point of view, as shown inFIG. 1, in the embodiment, the display device10may have a display area A and a peripheral area B located at at least one side of the display area A, wherein the peripheral area B includes an internal driving circuit area ID and a wiring area WR.

In the embodiment, the material of the substrate100may be glass, quartz, plastic or organic polymer. In the embodiment, the pixel array102, the internal driving circuit104and the plurality of signal lines106are disposed on the substrate100. In detail, as shown inFIG. 1, the pixel array102is disposed on the substrate100in the display area A, the internal driving circuit104is disposed on the substrate100in the internal driving circuit area ID, the plurality of signal lines106are disposed on the substrate100in the wiring area WR, and the external circuit300are electrically connected with the plurality of signal lines106. In the embodiment, the substrate100and the pixel array102, the internal driving circuit104and the plurality of signal lines106disposed on the substrate100may be regarded as a pixel array substrate. However, the present invention is not limited to the one depicted inFIG. 1, and the pixel array substrate of the display device10may be any pixel array substrate known to those skilled in the art for display devices. For example, in one embodiment, the color filter layer may be disposed on the substrate100to form a color filter on array (COA) pixel array substrate. In addition, in the embodiment, althoughFIG. 1illustrates that the external circuit300is only partially disposed on the substrate100, the present invention is not limited thereto. In other embodiments, the external circuit300may be disposed on the substrate100in the peripheral area B. In addition, in order to make the diagram clear, some components are omitted inFIG. 1, and those skilled in the art should understand that some components, such as bonding pads, fan-out lines, frame glue, etc., which can be reasonably inferred according to the disclosure content of the present invention may exist in the pixel array substrate of the display device10.

In the embodiment, the substrate200and the substrate100are disposed opposite to each other. In the embodiment, the material of the substrate200may be glass, quartz, plastic or organic polymer. In addition, in the embodiment, the substrate200may be regarded as an opposite substrate. The substrate200may be any opposite substrate known to those skilled in the art for display devices. For example, in one embodiment, the substrate200may include, for example, a blank substrate and an element layer on the blank substrate. For example, in one embodiment, the element layer included in the substrate200may include, for example, a color filter layer, a wavelength conversion layer, a light-shielding pattern layer, a opposite electrode layer, or a combination thereof, but the invention is not limited thereto, and may be adjusted and changed depending on requirements.

In the embodiment, the pixel array102may include a plurality of scan lines SL, a plurality of data lines DL, and a plurality of pixel units PX arranged in an array. In the embodiment, the plurality of scan lines SL are not parallel to the plurality of data lines DL, that is, the plurality of scan lines SL and the plurality of data lines DL are disposed to cross each other. In order to make the diagram clear, the wring shown inFIG. 1is only for schematic, and is not intended to limit the present invention. For example, the extending direction of the plurality of scan lines SL and the extending direction of the plurality of data lines DL inFIG. 1are substantially perpendicular to each other, but the present invention is not limited thereto. The actual circuit layout of the plurality of scan lines SL and the plurality of data lines DL may be adjusted according to the architecture, requirements, etc., of the actual display device. In addition, the plurality of scan lines SL and the plurality of data lines DL may be located in different layers, and an insulating layer (not shown) may be interposed between the plurality of scan lines SL and the plurality of data lines DL. Based on conductivity considerations, the plurality of scan lines SL and the plurality of data lines DL are generally made of metal material. However, the present invention is not limited thereto. According to other embodiments, the plurality of scan lines SL and the plurality of data lines DL may be made of, for example, other conductive materials such as an alloy, a nitride of metal material, an oxide of metal material, an oxynitride of metal material, or a stack of said metal material and the aforementioned other conductive materials. In addition, in the embodiment, the plurality of scan lines SL and the plurality of data lines DL may have a single-layer structure or a multi-layer structure, respectively.

In the embodiment, each pixel unit PX is electrically connected with one of the plurality of scan lines SL and one of the plurality of data lines DL. In the embodiment, each pixel unit PX includes an active element T and a pixel electrode PE. The active element T may be any thin film transistor known to those skilled in the art, including, for example, a gate, a channel layer, a source and a drain (not labeled). In the embodiment, the pixel electrode PE is electrically connected with the active element T. The material of the pixel electrode PE may include (but not limited to): metal oxide conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, other suitable oxides, or a stack of at least two of the above. In addition,FIG. 1shows that the pixel electrode PE is a bulk electrode, but the present invention is not limited thereto. In other embodiments, the pixel electrode PE may be an electrode with a slit pattern.

In the embodiment, the internal driving circuit104is electrically connected with the pixel array102. In detail, as shown inFIG. 1, the internal driving circuit104is electrically connected with the plurality of scan lines SL. In other words, in the embodiment, the internal driving circuit104may be a gate driver-on-array (GOA) or a gate driver integrated circuit (IC) for driving the pixel array102, but the invention is not limited thereto.

In the embodiment, the external circuit300is electrically connected with the internal driving circuit104. In detail, as shown inFIG. 1, the external circuit300is electrically connected with the internal driving circuit104through bonding pads (not shown) and then the plurality of signal lines106. In the embodiment, the external circuit300is, for example, a driving chip, a control circuit, a flexible printed circuit (FPC) or a printed circuit board (PCB) provided with a driving chip, etc., so as to drive the pixel array102. In addition, in the embodiment, the external circuit300may use a suitable process, such as: Chip On Glass (COG) process, Chip On Film (COF) process, Chip On Board (COB) process, Tape Automated Bonding (TAB), etc., to be connected with the substrate100.

In the embodiment, the plurality of signal lines106are electrically connected with the external circuit300and the internal driving circuit104, thereby transmitting the signal received from the external circuit300to the internal driving circuit104to drive the pixel array102. In the embodiment where the internal driving circuit104is a gate driver-on-array, the signal line106may be a high-frequency signal line. However, the present invention is not limited thereto. In other embodiments, the signal line106may also be a start signal line, a low-frequency signal line, a low level signal line, or a constant voltage signal line. From another point of view, as shown inFIG. 1, the signal line106may be a wire on array (WOA), that is, the wiring area WR may be referred to as a WOA area, but the present invention is not limited thereto. AlthoughFIG. 1shows that five signal lines106are provided in the wiring area WR, the present invention does not limit the number of signal lines106and may be adjusted according to the actual structure and requirements of the display device10.

Referring toFIG. 1andFIG. 2, in the embodiment, each signal line106includes a signal line segment S1, a signal line segment S2, a signal line segment S3, a signal line segment S4, a signal line segment S5and a signal line segment S6, in which the signal line segment S2is directly connected between the signal line segment S1and the signal line segment S3, the signal line segment S3is directly connected between the signal line segment S2and the signal line segment S4, the signal line segment S4is directly connected between the signal line segment S3and the signal line segment S5, and the signal line segment S5is directly connected between the signal line segment S4and the signal line segment S6. In other words, in the embodiment, each signal line106includes six signal line segments connected with each other. However, the present invention is not limited thereto, as long as each signal line106includes N signal line segments connected with each other, N is a positive integer and N≥3, it falls within the scope of the present invention.

In the embodiment, the signal line106includes a single-layer metal layer structure. That is to say, in the embodiment, the signal line segment S1, the signal line segment S2, the signal line segment S3, the signal line segment S4, the signal line segment S5and the signal line segment S6in each signal line106are formed by the same process and have the same material and thickness. Based on conductivity considerations, the plurality of signal lines106are generally made of a metal material, such as copper, aluminum, titanium or molybdenum. However, the present invention is not limited thereto. According to other embodiments, the plurality of signal lines106may be made of, for example, other conductive materials such as an alloy, a nitride of metal material, an oxide of metal material, an oxynitride of metal material, or a stack of said metal material and the aforementioned other conductive materials.

In the embodiment, each signal line106includes a turning point Pa1, a turning point Pa2, a turning point Pa3, a turning point Pa4and a turning point Pa5. In detail, as shown inFIG. 2, the turning point Pa1is located at the connecting site between the signal line segment S1and the signal line segment S2, the turning point Pa2is located at the connecting site between the signal line segment S2and the signal line segment S3, the turning point Pa3is located at the connecting site between the signal line segment S3and the signal line segment S4, the turning point Pa4is located at the connecting site between the signal line segment S4and the signal line segment S5, and the turning point Pa5is located at the connecting site between the signal line segment S5and the signal line segment S6. In other words, in the embodiment, each of the turning point Pa1, the turning point Pa2, the turning point Pa3, the turning point Pa4and the turning point Pa5is located at the connecting site between two adjacent signal line segments. From another point of view, in the embodiment, two adjacent signal line segment S1and signal line segment S2are together connected to the turning point Pa1, two adjacent signal line segment S2and signal line segment S3are together connected to the turning point Pa2, two adjacent signal line segment S3and the signal line segment S4are together connected with the turning point Pa3, two adjacent signal line segment S4and the signal line segment S5are together connected with the turning point Pa4, and two adjacent signal line segment S5and the signal line segment S6are together connected with the turning point Pa5. From yet another point of view, in the embodiment, the turning point Pa1may be regarded as one end point of the signal line segment S1, the turning point Pa1and the turning point Pa2may be regarded as the opposite end points of the signal line segment S2, the turning point Pa2and the turning point Pa3may be regarded as the opposite end points of the signal line segment S3, the turning point Pa3and the turning point Pa4may be regarded as the opposite end points of the signal line segment S4, the turning point Pa4and the turning point Pa5may be regarded as the opposite end points of the signal line segment S5, and the turning point Pa5may be regarded as one end point of the signal line segment S6.

In the embodiment, as shown inFIG. 2, the width W1of the signal line segment S1is greater than the width W2of the signal line segment S2, the width W2of the signal line segment S2is greater than the width W3of the signal line segment S3, the width W3of the signal line segment S3is smaller than the width W4of the signal line segment S4, the width W4of the signal line segment S4is smaller than the width W5of the signal line segment S5, and the width W5of the signal line segment S5is smaller than the width W6of the signal line segment S6. That is to say, in the embodiment, the widths of two adjacent signal line segments are different from each other, that is, there is a width change rate ΔW between the two adjacent signal line segments. Herein, “width” is defined as: from the top view (that is, from the direction perpendicular to the substrate100), in the direction perpendicular to the extension direction of the opposite and parallel side surfaces of the signal line segment, the distance between the opposite and parallel side surfaces of the signal line segment. In addition, herein, “width change rate ΔW” refers to the value obtained by substituting a width dimension a of a signal line segment which the signal passes first and a width dimension b of an adjacent signal line segment which the signal passes later along the signal transmission direction from the external circuit300to the internal driving circuit104, or the signal transmission direction from the internal driving circuit104to the external circuit300into the following formula: ΔW (%)=100×(b−a)/a.

Specifically, in the embodiment, the absolute value of the width change rate ΔW between the width W1of the signal line segment S1and the width W2of the signal line segment S2is greater than 0 and less than or equal to 10%, the absolute value of the width change rate ΔW between the width W2of the signal line segment S2and the width W3of the signal line segment S3is greater than 0 and less than or equal to 10%, the absolute value of the width change rate ΔW between the width W3of the signal line segment S3and the width W4of the signal line segment S4is greater than 0 and less than or equal to 10%, the absolute value of the width change rate ΔW between the width W4of the signal line segment S4and the width W5of the signal line segment S5is greater than 0 and less than or equal to 10%, and the absolute value of the width change rate ΔW between the width W5of the signal line segment S5and the width W6of the signal line segment S6is greater than 0 and less than or equal to 10%. That is to say, in the embodiment, the width change rate ΔW between two adjacent signal line segments connected with each of the turning point Pa1, the turning point Pa2, the turning point Pa3, the turning point Pa4, and the turning point Pa5meets the following condition: 0<|ΔW|≤10%. In other words, in the embodiment, the width change rate ΔW between two adjacent signal line segments corresponding to each turning point in each signal line106meets the above condition.

As mentioned above, the width change rate ΔW between two adjacent signal line segments corresponding to each of the opposite end points (i.e., the turning point Pa2and the turning point Pa3) of the signal line segment S3meets the above condition. That is to say, in the embodiment, the width change rate ΔW between two adjacent signal line segments corresponding to each of the opposite end points (i.e., the turning point Pa2and the turning point Pa3) of the signal line segment S3with the minimum width W3among the signal line segments S1-S6meets the above condition.

On the other hand, in the embodiment, the resistance change rate ΔR between two adjacent signal line segments connected with each of the turning point Pa1, the turning point Pa2, the turning point Pa3, the turning point Pa4and the turning point Pa5meets the following conditions: 0<|ΔR|≤10%. This indicates that in the embodiment, the width change rate ΔW between two adjacent signal line segments connected with each of the turning point Pa1, the turning point Pa2, the turning point Pa3, the turning point Pa4and the turning point Pa5directly corresponds to the resistance change rate ΔR between two adjacent signal line segments connected with each of turning point Pa1, turning point Pa2, turning point Pa3, turning point Pa4and turning point Pa5.

Those skilled in the art can understand the following relationship formula (1): R/L=ρ/W× t, wherein R/L represents the resistance value per unit length, ρ represents the resistivity of the metal material, W represents the width of the trace and t represents the thickness of the trace. It can be seen from the above relationship formula (1) that when the plurality of signal lines106are formed, the resistivity ρ, width W (i.e., widths W1-W6) and thickness t of each of the signal line segments S1-S6are determined, so in the embodiment where the signal line segments S1-S6have the same material (i.e., the same resistivity ρ) and the same thickness t, when the width W of any one of the signal line segments S1-S6changes, the corresponding resistance value per unit length R/L changes accordingly, and there is an inverse relationship between the width W and the resistance value per unit length R/L. In view of this, by confirming the absolute value of the width change rate ΔW between two adjacent signal line segments, the absolute value of the resistance change rate ΔR between two adjacent signal line segments can be learned. Herein, “resistance change rate ΔR” refers to the value obtained by substituting a resistance value c per unit length of a signal line segment which the signal passes first and a resistance value d per unit length of an adjacent signal line segment which the signal passes later along the signal transmission direction from the external circuit300to the internal driving circuit104, or the signal transmission direction from the internal driving circuit104to the external circuit300into the following formula: ΔR (%)=100×(d−c)/c.

As described above, in the embodiment, the width change rate ΔW between two adjacent signal line segments corresponding to each of the turning points Pa1-Pa5in each signal line106meets the condition of 0<|ΔW|≤10%. However, the present invention is not limited thereto, as long as each signal line106includes N signal line segments, Ma first turning points and Mb second turning points, wherein the N signal line segments are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of two adjacent signal line segments, N and Ma are positive integers, Mb is a positive integer or 0, N≥3, Ma≥2, Ma+Mb≤N−1, and the resistance change rate ΔR between two adjacent signal line segments connected with each first turning point meets the condition of 0<|ΔR|≤10% or the width change rate ΔW between two adjacent signal line segments connected with each first turning point meets the condition of 0<|ΔW|≤10%, it falls within the scope of the present invention. That is to say, in other embodiments, each signal line106may include other turning points different from the turning points Pa1-Pa5, that is, each signal line106may include a turning structure of which the resistance change rate ΔR between two adjacent signal line segments does not meet the condition of 0<|ΔR|≤10% or the width change rate ΔW between two adjacent signal line segments does not meet the condition of 0<|ΔW|≤10%.

For example, please refer toFIG. 3, the signal line106of this embodiment is similar to the signal line106ofFIG. 2, the main difference between the two lies in that the signal line106ofFIG. 3includes a turning point Pb1, and the width change rate ΔW between the adjacent signal line segment S3and the signal line segment S4connected with the turning point Pb1is equal to 0, that is, the width W3of the signal line segment S3and the width W4of the signal line segment S4are substantially the same. Based on the previous description, it can be known that the turning points Pa1-Pa5are the so-called first turning points, and the turning point Pb1is the so-called second turning point. In view of this, in the embodiment ofFIG. 2, the turning points Pa1-Pa5(i.e., the first turning point) in each signal line106exist in a continuous configuration, and in the embodiment ofFIG. 3, the turning points Pa1-Pa2and Pa4-Pa5(i.e., the first turning point) in each signal line106exist in a discontinuous configuration, because the turning point Pb1is located between the turning point Pa2and the turning point Pa4.

Furthermore, in the embodiment ofFIG. 3, only four turning structures among the turning structures corresponding to the five turning points (i.e., turning point Pa1, turning point Pa2, turning point Pa4, turning point Pa5, turning point Pb1) of the signal line106meet the following condition: the absolute value of the width change rate ΔW between two adjacent signal line segments being greater than 0 and less than or equal to 10%. In other words, in the embodiment ofFIG. 3, only four turning structures among the turning structures corresponding to the five turning points (i.e., turning point Pa1, turning point Pa2, turning point Pa4, turning point Pa5, turning point Pb1) of the signal line106meet the following condition: the absolute value of the resistance change rate ΔR between two adjacent signal line segments being greater than 0 and less than or equal to 10%. From another point of view, in the embodiment ofFIG. 3, not all the width change rates ΔW corresponding to the opposite end points (i.e., the turning point Pa2and the turning point Pb1) of the signal line segment S3with the minimum width W3among the signal line segments S1-S6meet the condition of 0<|ΔW|≤10%.

Based on the foregoing description, it can be seen that in the embodiment ofFIG. 2, each signal line106meets the following conditions: N=6, Ma=5, Mb=0, and Ma+Mb=N−1; and in the embodiment ofFIG. 3, each signal line106meets the following conditions: N=6, Ma=4, Mb=1 and Ma+Mb=N−1. However, the present invention is not limited thereto, as mentioned above, as long as N and Ma are positive integers, Mb is a positive integer or 0, N≥3, Ma≥2, Ma+Mb≤N−1, it falls within the scope of the present invention. That is to say, in the display device of the present invention, each signal line106includes at least two first turning points, and the turning structures corresponding to such at least two first turning points each conform to the following condition: the absolute value of the width change rate ΔW between two adjacent signal line segments being greater than 0 and less than or equal to 10%, or the absolute value of the resistance change rate ΔR between two adjacent signal line segments being greater than 0 and less than or equal to 10%. In this way, in the display device of the present invention, the impedance matching between the plurality of signal line segments in each signal line106in the wiring area WR can be improved, so that the temperature rising degree of the signal lines106can be effectively suppressed. Thereby, the safety problem of the display device of the present invention due to excessive temperature can be avoided, and the display device of the present invention can be beneficial to be designed with high resolution and slim border. In some embodiments, each signal line106in the wiring area WR of the display device of the present invention includes at least two first turning points, such that compared with the conventional display device, the temperature of the signal lines106in the display device of the present invention can be reduced by at least about 2.7° C.

In addition, as described above, in the embodiment ofFIG. 2, the width change rate ΔW between two adjacent signal line segments corresponding to each of the opposite end points (i.e., the turning point Pa2and the turning point Pa3) of the signal line segment S3with the minimum width W3among the signal line segments S1-S6meets the condition of 0<|ΔW|≤10%; and in the embodiment ofFIG. 3, not all the width change rates ΔW corresponding to the opposite end points (i.e., the turning point Pa2and the turning point Pb1) of the signal line segment S3with the minimum width W3among the signal line segments S1-S6meet the condition of 0<|ΔW|≤10%. In this way, the display device corresponding to the embodiment ofFIG. 2can suppress the temperature rising degree of the signal lines106to a greater extent than the display device corresponding to the embodiment ofFIG. 3. That is to say, in the display device of the present invention, the opposite ends of the signal line segment with the minimum width (i.e., the maximum resistance value) among the signal line segments of each signal line106in the wiring area WR all are the first turning points, thereby the temperature rising degree of the signal lines106can effectively suppressed.

In the following, in order to prove that the design of the display device of the present invention can indeed achieve the effective suppression of the degree of rising temperature of the signal lines in the wiring area, the display devices of Examples 1 to 2 and the display devices of Comparative Examples 1 to 2 are specifically used to undergo the temperature simulation test on the signal lines in the wiring area, please refer to Table 1 and Table 2 below. In the display devices of Examples 1 and 2 and the display devices of Comparative Examples 1 and 2, each signal line in the wiring area includes a single-layer metal layer structure, and from the external circuit to the internal driving circuit, each signal line in the wiring area includes four signal line segments (i.e., signal line segment WOA1, signal line segment WOA2, signal line segment WOA3, and signal line segment WOA4), wherein a turning point is located between any two adjacent signal line segments.

It can be seen from the simulation results in Table 2 that the signal lines in the wiring area of Examples 1-2 have a lower temperature compared to Comparative Examples 1-2. That is, the degree of rising temperature of the signal lines in the wiring area of Examples 1-2 is reduced.

This result confirms that in the display device of the present invention, each signal line in the wiring area is designed to include N signal line segments, Ma first turning points and Mb second turning points, wherein the N signal line segments are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of two adjacent signal line segments, N and Ma are positive integers, Mb is a positive integer or 0, N≥3, Ma≥2, Ma+Mb≤N−1, and the resistance change rate ΔR between two adjacent signal line segments connected with each first turning point meets the condition of 0<|ΔR|≤10% or the width change rate ΔW between two adjacent signal line segments connected with each first turning point meets the condition of 0<ΔW|≤10%, thereby the temperature rising degree of the signal lines in the wiring area can indeed be effectively suppressed to improve safety.

In addition, according to the foregoing description ofFIGS. 1 to 3and the simulation results, those skilled in the art should understand that the design of the display device of the present invention is not limited to those depicted inFIG. 2andFIG. 3, as long as each signal line in the wiring area includes N signal line segments, Ma first turning points and Mb second turning points, wherein the N signal line segments are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site between two adjacent signal line segments, N and Ma are positive integers, Mb is a positive integer or 0, N≥3, Ma≥2, Ma+Mb≤N−1, and the resistance change rate ΔR between two adjacent signal line segments connected with each first turning point meets the condition of 0<|ΔR|≤10% or the width change rate ΔW between two adjacent signal line segments connected with each first turning point meets the condition of 0<ΔW|≤10%, it falls within the scope of the present invention. That is to say, those skilled in the art should be able to design the specific structure of each signal line in the wiring area based on the actual display device architecture and requirements based on the existing technical level and the disclosure of this application.

In addition, in the embodiment ofFIG. 2orFIG. 3, the signal line106includes a single-layer metal layer structure, but the present invention is not limited thereto. Hereinafter, other embodiments will be described in detail with reference toFIGS. 4 to 6. It should be noted that the reference numerals and some descriptions in the previous embodiment are used in the following embodiments, in which identical or similar reference numerals indicate identical or similar elements, and repeated description of the same technical contents is omitted. The omitted part of the description can refer to the foregoing embodiments, which is not repeated in the following embodiments.

FIG. 4is an enlarged schematic diagram of one signal line according to another embodiment of the invention.FIG. 5is a schematic cross-sectional view taken along a section line I-I′ ofFIG. 4.FIG. 6is a schematic cross-sectional view taken along a section line II-II′ ofFIG. 4. Referring toFIG. 4andFIG. 2, the signal line106ofFIG. 4is similar to the signal line106ofFIG. 2, and therefore identical or similar elements are denoted by identical or similar reference numerals, and the description of the same technical contents is omitted. The omitted part of the description can refer to the foregoing embodiments. Hereinafter, the difference between the signal line106ofFIG. 4and the signal line106ofFIG. 2will be described.

Referring toFIG. 4toFIG. 6, in the embodiment, the signal line106includes a double-layer metal layer structure. It is worth mentioning that although the signal line segment S4is used as an example to illustrate the double-layer metal layer structure, according to the following description based onFIG. 5andFIG. 6, those skilled in the art should understand that the specific structure of each of the signal line segments S1-S3, S5-S6, that is, each of the signal line segments S1-S3, S5-S6includes a double-layer metal layer structure.

In detail, as shown inFIG. 5andFIG. 6, the double-layer metal layer structure includes a first metal layer M1, a second metal layer M2, and an insulation layer L1between the first metal layer M1and the second metal layer M2. Based on conductivity considerations, the first metal layer M1and the second metal layer M2are generally made of metal material, such as copper, aluminum, titanium or molybdenum. However, the present invention is not limited thereto, according to other embodiments, the first metal layer M1and the second metal layer M2may be made of, for example, other conductive materials such as an alloy, a nitride of metal material, an oxide of metal material, an oxynitride of metal material, or a stack of said metal material and the aforementioned other conductive materials. In the embodiment, the material of the first metal layer M1is substantially the same as the material of the second metal layer M2. However, the present invention is not limited thereto. In other embodiments, the material of the first metal layer M1may be different from the material of the second metal layer M2. In addition, in the embodiment, the thickness t1of the first metal layer M1is substantially the same as the thickness t2of the second metal layer M2. However, the present invention is not limited thereto. In other embodiments, the thickness t1of the first metal layer M1may be different from the thickness t2of the second metal layer M2. The material of the insulating layer L1may include inorganic materials, organic materials, or other suitable materials, wherein the inorganic materials include (but are not limited to): silicon oxide, silicon nitride, or silicon oxynitride, and the organic materials include (but are not limited to): polyimide-based resin, epoxy-based resin or acrylic-based resin.

Further, please refer toFIG. 4andFIG. 6, the second metal layer M2is electrically connected with the first metal layer M1through a contact structure C. That is to say, in the signal line106of the embodiment, the contact structure C for electrically connecting the first metal layer M1and the second metal layer M2is disposed in the signal line segment S4. However, the present invention is not limited thereto. In other embodiments, the contact structure C may be provided in at least one of the signal line segments S1-S3, S5-S6. In detail, as shown inFIG. 6, by disposing the contact structure C in a contact window V1of the insulating layer L1and a contact window V2of the insulating layer L2, the second metal layer M2is electrically connected with the first metal layer M1the first metal layer M1. In other words, the contact structure C is directly connected with the first metal layer M1and the second metal layer M2through the contact window V1and the contact window V2. From another point of view, in the embodiment, when the signal line106is used to transmit signals, the first metal layer M1and the second metal layer M2are arranged in parallel. In view of this, in the embodiment, the signal line segment S4can be regarded as being obtained by the parallel connection of the portion of the first metal layer M1corresponding to the signal line segment S4and the portion of the second metal layer M2corresponding to the signal line segment S4, and the configurations of the signal line segments S1-S3, S5-S6are deduced by analogy. The material of the contact structure C may include metal oxide, such as indium tin oxide, indium zinc oxide, or indium gallium zinc oxide. The material of the insulating layer L2may include inorganic materials, organic materials, or other suitable materials, wherein the inorganic materials include (but are not limited to): silicon oxide, silicon nitride, or silicon oxynitride, and the organic materials include (but are not limited to): polyimide-based resin, epoxy-based resin or acrylic-based resin. In addition, the configuration in which the second metal layer M2is electrically connected with the first metal layer M1through the contact structure C is not limited to that shown inFIG. 6. For example,FIG. 6shows that one insulating layer L2is disposed between the contact structure C and the second metal layer M2, but the present invention is not limited thereto. In other embodiments, two or more insulating layers may be provided between the contact structure C and the second metal layer M2. In yet other embodiments, other insulating layers may be provided on the contact structure C.

It can be seen from the above relationship formula (1) that when the plurality of signal lines106are formed, the resistivity ρ, width W (i.e., widths W1-W6) and thickness t (i.e., thicknesses t1-t2) of each of the signal line segments S1-S6are determined, so in the embodiment where the first metal layer M1and the second metal layer M2are arranged in parallel, and the first metal layer M1and the second metal layer M2have the same material (i.e., the same resistivity ρ) and the same thickness t (which means that the thickness t1is equal to the thickness t2), when the width W of any one of the signal line segments S1-S6changes, the corresponding resistance value per unit length R/L changes accordingly, and there is an inverse relationship between the width W and the resistance value per unit length R/L. In view of this, by confirming the absolute value of the width change rate ΔW between two adjacent signal line segments, the absolute value of the resistance change rate ΔR between two adjacent signal line segments can be learned.

As mentioned above, in other embodiments, the thickness t1of the first metal layer M1may be different from the thickness t2of the second metal layer M2. Even so, in the case where the first metal layer M1and the second metal layer M2are arranged in parallel, and the first metal layer M1and the second metal layer M2have the same material (i.e., the same resistivity ρ), by confirming the absolute value of the width change rate ΔW between two adjacent signal line segments, the absolute value of the resistance change rate ΔR between two adjacent signal line segments can still be learned. That is, regardless of whether the thickness t1of the first metal layer M1is the same as the thickness t2of the second metal layer M2, the absolute value of the resistance change rate ΔR between two adjacent signal line segments can be learned by confirming Know the absolute value of the width change rate ΔW between adjacent signal line segments.

In addition, as described above, in other embodiments, the material of the first metal layer M1may be different from the material of the second metal layer M2. Accordingly, from the above relationship formula (1), it can be seen that the resistance value per unit length R/L is affected by both the width W and the resistivity ρ, that is, the absolute value of the resistance change rate between two adjacent signal line segments cannot be learned from the absolute value of the width change rate ΔW between two adjacent signal line segments.

In addition, in the embodiment ofFIG. 2orFIG. 3, the signal line106includes a single-layer metal layer structure, and in the embodiment ofFIG. 4, the signal line106includes a double-layer metal layer structure, but the present invention is not limited thereto. In other embodiments, the signal line106may include both of a single-layer metal layer structure and a double-layer metal layer structure.

In addition, in the embodiment ofFIG. 2,FIG. 3orFIG. 4, the structure of each signal line106is a single bar structure, but the present invention is not limited thereto. Hereinafter, other embodiments will be described in detail with reference toFIG. 7. It should be noted that the reference numerals and some descriptions in the previous embodiment are used in the following embodiments, in which identical or similar reference numerals indicate identical or similar elements, and repeated description of the same technical contents is omitted. The omitted part of the description can refer to the foregoing embodiments, which is not repeated in the following embodiments.

FIG. 7is an enlarged schematic top view of one signal line according to another embodiment of the invention. Referring toFIG. 7andFIG. 2, the signal line106ofFIG. 7is similar to the signal line106ofFIG. 2, and therefore identical or similar elements are denoted by identical or similar reference numerals, and the description of the same technical contents is omitted. The omitted part of the description can refer to the foregoing embodiments. Hereinafter, the difference between the signal line106ofFIG. 7and the signal line106ofFIG. 2will be described.

Referring toFIG. 7, in the embodiment, the signal line segment S1includes a plurality of strip portions f1arranged parallel to each other, and a gap o1is located between two adjacent strip portions f1; the signal line segment S2includes a plurality of strip portions f2arranged parallel to each other, and a gap o2is located between two adjacent strip portions f2; the signal line segment S3includes a plurality of strip portions f3arranged parallel to each other, and a gap o3is located between two adjacent strip portions f3; the signal line segment S4includes a plurality of strip portions f4arranged parallel to each other, and a gap o4is located between two adjacent strip portions f4; the signal line segment S5includes a plurality of strip portions f5arranged parallel to each other, and a gap o5is located between two adjacent strip portions f5; the signal line segment S6includes a plurality of strip portions f6arranged parallel to each other, and a gap o6is located between two adjacent strip portions f6.

In view of this, in the embodiment, the width of the signal line segment S1is the sum of the widths d1of the plurality of strip portions f1, the width of the signal line segment S2is the sum of the widths d2of the plurality of strip portions f2, and the width of the signal line S3The sum of the widths d3of the plurality of strip portions f3, the width of the signal line segment S4is the sum of the widths d4of the plurality of strip portions f4, the width of the signal line segment S5is the sum of the widths d5of the plurality of strip portions f5, and the width of the signal line segment S6The width is the sum of the widths d6of the plurality of strip portions f6.

It can be known from the above relationship formula (1) that when the plurality of signal lines106are formed, the resistivity ρ, width W (that is, the sum of the widths d1of the strip portions f1, the sum of the widths d2of the strip portions f2, the sum of the widths d3of the strip portions f3, the sum of the widths d4of the strip portions f4, the sum of the widths d5of the strip portions f5, the sum of the widths d6of the strip portions f6) and the thickness t of each of the signal line segments S1-S6are determined, so in the embodiment where the signal line segments S1-S6have the same material (i.e., the same resistivity ρ) and the same thickness t, when the width W of any one of the signal line segments S1-S6changes, the corresponding resistance value per unit length R/L changes accordingly, and the width W is inversely proportional to the resistance value per unit length R/L. In view of this, by confirming the absolute value of the width change rate ΔW between two adjacent signal line segments, the absolute value of the resistance change rate ΔR between two adjacent signal line segments can be learned.

As shown inFIG. 7, in the embodiment, the number of strip portions f1is five, the number of strip portions f2is five, the number of strip portions f3is two, and the number of strip portions f4is three, the number of strip portions f5is four, and the number of strip portions f6is three. In addition, as shown inFIG. 7, in the embodiment, the widths d1of the plurality of strip portions f1are the same as each other, the widths d2of the plurality of strip portions f2are the same as each other, the widths d3of the plurality of strip portions f3are the same as each other, the widths d4of the plurality of strip portions f4are the same as each other, the widths d5of the plurality of strip portions f5are the same as each other, and the widths d6of the plurality of strip portions f6are the same as each other. In addition, as shown inFIG. 7, in the embodiment, the sum of the widths d1of the plurality of strip portions f1is greater than the sum of the widths d2of the plurality of strip portions f2, the sum of the widths d2of the plurality of strip portions f2is greater than the sum of the widths d3of the strip portions f3, the sum of the widths d3of the strip portions f3is smaller than the sum of the widths d4of the strip portions f4, the sum of the widths d4of the strip portions f4is smaller than the widths of the strip portions f5, and the sum of the widths d5of the plurality of strip portions f5is smaller than the sum of the widths d6of the plurality of strip portions f6. However, the present invention is not limited to those depicted inFIG. 7. Based on the descriptions of the foregoing embodiments, it can be known that as long as each signal line106includes N signal line segments, Ma first turning point and Mb second turning point, wherein the N signal line segments are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of two adjacent signal line segments, N and Ma are positive integers, Mb is positive integer or 0, N≥3, Ma≥2, Ma+Mb≤N−1, and the resistance change rate ΔR between two adjacent signal line segments connected with each first turning point meets the condition of 0<|ΔR|10% or the width change rate ΔW between two adjacent signal line segments connected with each first turning point meets the condition of 0<|ΔW|≤10%, it falls within the scope of the present invention.

In summary, in the display device of the above embodiments, by adjusting the layout design of the signal lines located in the wiring area and electrically connected with the external circuit and the internal drive circuit, the temperature rising degree of the signal lines can be effectively suppressed. In this way, the display device of the present invention can avoid the problem of safety due to excessive temperature, and can be beneficial to be designed with high resolution and slim border.

Although the invention is disclosed as the embodiments above, the embodiments are not meant to limit the invention. Any person skilled in the art may make slight modifications and variations without departing from the spirit and scope of the invention. Therefore, the protection scope of the invention shall be defined by the claims attached below.