COMPUTATIONAL STORAGE DEVICES AND POWER MANAGEMENT METHODS THEREOF

A computational storage device that is configured to be electrically connected to a host, comprising: a power management integrated circuit that is configured to distribute power; a storage that is configured to store data using a first voltage provided from the power management integrated circuit; a computing module that is configured to perform an operation that is allocated by the host using a second voltage provided from the power management integrated circuit; and a performance monitoring module that is configured to monitor a first workload, a first amount of computation, and/or a first power state of the storage and/or is configured to monitor a second workload, a second amount of computation, and/or a second power state of the computing module and is configured to send a request for additional power to the host based on a monitoring result that is generated by the performance monitoring module.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0017400 filed on Feb. 9, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

BACKGROUND

Embodiments of the present disclosure described herein relates to semiconductor memory devices, and more particularly, to computational storage devices and power management methods thereof.

With the rapid increase in the amount of data to be processed, the demand for a large-capacity storage device is increasing. In addition, the demand for high-performance and high-efficiency storage devices capable of rapidly processing large amounts of data has also increased. Conventional computing devices may be implemented with a centralized architecture in which a specific component is configured to control overall operations. In such centralized architecture, the performance of an electronic device may be limited depending on the performance and throughput of its particular circuit or component. Therefore, the centralized architecture may have a limited capability to meet the demand for high-performance and high-efficiency electronic devices.

Storage developed to solve this problem may include computational storage such as smart solid state drive (SSD) or Compute Express Link (CXL) SSD. That is, technology may be developing in a direction in which storage devices having computational functions, such as computational storage, share specific computations such as artificial intelligence AI computations or machine learning ML of a CPU or processor. During this process, the computing module installed inside the computational storage may require a lot of power for complex calculations including AI calculations or machine learning ML. Excessive current consumption by the computing module may adversely affect internal devices or peripheral devices of the computational storage, and sometimes cause sudden power-off SPO.

SUMMARY

Embodiments of the present disclosure provide computational storage devices that can stably receive power and power management methods thereof.

According to some embodiments, a computational storage device that is configured to be electrically connected to a host, comprising: a power management integrated circuit that is configured to distribute power; a storage that is configured to store data using a first voltage provided from the power management integrated circuit; a computing module that is configured to perform an operation that is allocated by the host using a second voltage provided from the power management integrated circuit; and a performance monitoring module that is configured to monitor a first workload, a first amount of computation, and/or a first power state of the storage and/or is configured to monitor a second workload, a second amount of computation, and/or a second power state of the computing module and is configured to send a request for additional power to the host based on a monitoring result that is generated by the performance monitoring module.

According to some embodiments, a computational storage device that is configured to be electrically connected to a host: a power management integrated circuit that is configured to distribute power; a storage that is configured to store data using a first voltage provided from the power management integrated circuit; a computing module that is configured to perform an operation allocated by the host using a second voltage provided from the power management integrated circuit; and a performance monitoring module that is configured to monitor a first workload, a first amount of computation, and a first power state of the storage and/or is configured to monitor a second workload, a second amount of computation, and a second power state of the computing module and is configured to send a request for additional power to the host based on a monitoring result that is generated by the performance monitoring module.

According to some embodiments, a power management method for a plurality of computational storage devices that are electrically connected to a backplane, the method comprising: monitoring a workload, an amount of computation, and/or a power state of each of the plurality of computational storage devices; requesting additional power from a host that is electrically connected to the plurality of computational storage devices and the backplane or from the backplane based on a monitoring result that is generated by the monitoring; determining an additional power supply priority of each of the plurality of computational storage devices; and supplying the additional power to a computational storage device that is selected among the plurality of computational storage devices based on the additional power supply priority.

DETAILED DESCRIPTION

Examples of various embodiments are illustrated and described further below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the scope of the present disclosure as defined by the appended claims. The same reference numerals may refer to the same elements herein unless the context clearly indicates otherwise.

FIG.1is a block diagram showing a computing system according to some embodiments of the present invention. Referring toFIG.1, a computing system1000may include a host1100and a computational storage device1200. The computing system1000may be, for example, a server, desktop computer, laptop computer, tablet computer, smart phone, wearable device, electric vehicle, home appliance, and the like.

The host1100may manage and process various operations of the computing system1000. The host1100may perform various arithmetic/logical operations. For example, host1100may include one or more processor cores. The host1100may include a central processing unit CPU, a graphic processing unit GPU, a host memory, a network interface card NIC, and/or a system bus, but is not limited thereto. In some embodiments, the host1100may be a device including one or more processor cores, such as a general-purpose central processing unit CPU, a dedicated application specific integrated circuit ASIC, and/or an application processor AP, but is not limited thereto. The host1100may be a processor itself or an electronic device or system including a processor, but is not limited thereto. An operation (e.g., with reference to flowcharts in the drawings), hereinafter, may refer to an operation that can be performed by executing an instruction by at least one hardware, such as, but not limited to, a processor, a device, and a circuit.

The host1100may generate commands and data for access to the computational storage device1200. In particular, the host1100may delegate some operations among operations to be processed to the computational storage device1200. For example, the host1100may request the computational storage device1200to process a machine learning ML or artificial intelligence AI operation including multiple iteration operations or processing of branch statements. However, the embodiments of the present inventive concept is not limited to a machine learning ML or artificial intelligence AI operation. By distributing these operations, which may use relatively large memory resources, to the computational storage device1200, the host1100may use resources efficiently.

The backplane1150may provide a communication interface between the host1100and the computational storage device1200. The backplane1150may include signal lines used for communication links and control links, and power supply lines that supply power to various components of the computational storage device1200. That is, the backplane1150may supply power PWR to the computational storage device1200under the control of the host1100or under the control of its own power control controller. The backplane1150may vary the amount of power PWR supplied according to a request of the output module1230of the computational storage device1200. A module, hereinafter, may refer to a hardware structure, such as, but not limited to, a device or a circuit.

In some embodiments, the backplane1150may include any type of circuit board configured to electrically connect one or more computational storage devices1200to the host1100. Storage device connectors for electrical connecting one or more computational storage devices1200to the backplane1150may be arranged on one side of the circuit board. For example, the backplane1150may include a standard backplane configuration in which one or more other connectors or connection devices for electrical connecting to the host1100are disposed on the other side of the circuit board. In some embodiments, a battery (not shown) to be used as an auxiliary power source of at least one computational storage device1200may be electrically connected to the backplane1150. For example, the backplane1150may stably supply power PWR to one or more computational storage devices1200using a battery and/or constant power.

As used herein, the backplane1150may also refer to a component of a circuit board that can be used to physically and electrically connect one or more computational storage devices1200to the host1100. For example, the backplane1150may include two sets of connectors or interconnect devices on the same side of a circuit board. The backplane1150may include a single circuit board or may be implemented with multiple circuit boards and/or sets of connectors or connections.

The computational storage device1200may store data according to a request of the host1100or may perform an operation requested by the host1100. To this end, the computational storage device1200may include a host interface1210, a power management integrated circuit (PMIC)1220, an output module1230, a computing module1240, a performance monitoring module1250, a buffer1260, and/or SSD1270, but is not limited thereto.

The host interface1210may be provided as a physical and/or an electrical communication channel of the computational storage device1200for data exchange with the host1100. The host interface1210may have an interfacing protocol supporting a direct memory access (DMA) function of at least one of the output module1230, the computing module1240, the performance monitoring module1250, the buffer1260, and the SSD1270. For example, the buffer1260or the SSD buffer (not shown) of the SSD1270may be managed as a virtual memory space by a memory management unit (MMU, not shown) of the host1100and the host interface1210.

The PMIC1220may distribute power PWR provided through the backplane1150to components of the computational storage device1200. The PMIC1220may convert power PWR provided from the backplane1150into a stable voltage. The PMIC1220may supply stabilized voltage to components such as host interface1210, output module1230, computing module1240, performance monitoring module1250, buffer1260, and/or SSD1270.

The output module1230may transmit power status information generated by the performance monitoring module1250and a request for additional power to the host1100through the backplane1150. In some embodiments, the output module1230may transmit power status information generated by the performance monitoring module1250and a request for additional power to another computational storage device (not shown) electrically connected to the backplane1150. In some embodiments, the output module1230may transmit the workload status of the computational storage device1200generated by the performance monitoring module1250, a workload distribution request, and/or a sudden power-off (SPO) prediction flag to the host1100. In some embodiments, the output module1230may transmit at least one of the workload status of the computational storage device1200generated by the performance monitoring module1250, the SPO prediction flag, and the workload distribution request to another computational storage device (not shown) electrically connected to the backplane1150. The output module1230may communicate with the host1100or the backplane1150through the host interface1210. In some embodiments, the output module1230may communicate with the host1100or the backplane1150through an interface independent from the host interface1210. For example, the output module1230may communicate with the host1100or the backplane1150using I2C, UART, and/or SMbus, but the embodiments of the independent interface are not limited therego.

The computing module1240may be an operation logic dedicated to performing a specific operation requested by the host1100. For example, the computing module1240may use the buffer1260to execute an application for processing an operation requested by the host1100. In some embodiments, the computing module1240may be provided as a dedicated processor that executes an operation allocated by the host1100. Here, the operation allocated by the host1100may be an artificial intelligence AI operation or machine learning ML operation, but is not limited thereto. For example, the computing module1240may include a central processing unit CPU, an application processor AP, a graphics processing unit GPU, a neural processing unit NPU, a tensor processing unit TPU, a vision processing unit VPU, ISP(Image Signal Processor), and/or DSP(Digital Signal Processor) to perform the allocated and/or requested operations by the host1100. However, the processor included in the computing module1240of the present inventive concept is not limited thereto. In some embodiments, the computing module1240may be, but is not limited to, a device such as a Field Programmable Gate Array (FPGA) programmed for a specific operation. The computing module1240may perform an operation that is allocated by the host1100using a first voltage provided from the PMIC1220.

The performance monitoring module1250may monitor workloads or calculations of components of the computational storage device1200, such as the computing module1240, the buffer1260, and the SSD1270. Performance monitoring module1250may receive current workload status from components such as computing module1240, buffer1260, and SSD1270. Further, the performance monitoring module1250may transmit an additional power request to the backplane1150or the host1100through the output module1230when an amount of operation equal to or greater than a reference value is observed in a specific component of the computational storage device1200. Then, power PWR supplied to the computational storage device1200by the backplane1150or the host1100may increase.

In some embodiments, the performance monitoring module1250may determine whether a power shortage is caused by an operation in the computing module1240or an operation in the SSD1270executed according to a request of the host1100. For example, the performance monitoring module1250may monitor whether or not power PWR is insufficient due to, for example, the AI operation or the machine learning ML operation performed by the computing module1240. Also, the performance monitoring module1250may monitor whether or not the power PWR for the operation performed inside the SSD1270is insufficient. According to the monitoring result, the performance monitoring module1250may request additional power or give priority of supplying additional power to another computational storage device electrically connected to the backplane1150.

In some embodiments, the performance monitoring module1250may trigger a backup operation in preparation for sudden power-off SPO of the computational storage device1200due to excessive current consumption by the computing module (e.g., computing module1240). If a sudden power-off SPO is expected, the performance monitoring module1250may suspend a specific operation performed in the computing module1240and backs up status information and parameters of the suspended operation. The backed-up status information and parameters may be stored in another computational storage device electrically connected to the output module1230through the backplane1150, in the host1100, or in a separately provided storage. Later, when the computational storage device1200is restored from sudden power-off SPO, the performance monitoring module1250may control the computing module1240to receive the backed-up status information and parameters, and continue the suspended operation. In some embodiments, the performance monitoring module1250may request another computational storage device to continue executing the suspended operation using the backed-up status information and parameters.

The buffer1260may be used as a buffer or operating memory of the computational storage device1200. The buffer1260may write data or output the written data under the control of the host1100. The buffer1260may store a workload status, a power state, an amount of computation, and the like of components such as the computing module1240and/or the SSD1270collected by the performance monitoring module1250. The buffer1260may store status information about whether power PWR is insufficient due to, for example, the AI operation or the machine learning MIL operation of the computing module1240. In some embodiments, the buffer1260may back up parameters or status information of a specific operation suspended in the computing module1240when sudden power-off SPO is expected. Afterwards, the backed-up parameters and status information may be transmitted from the buffer1260to the host1100or other computational storage devices. For example, the Buffer1260may be implemented as high-bandwidth memory HBM. According to some embodiments, the buffer1260may include SDRAM, NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-torque magnetic RAM (STT-MRAM). However, the embodiments of the buffer1260of the present inventive concept are not limited thereto.

The SSD1270may be provided as storage of the computational storage device1200. The SSD1270may write data to or read stored data from a non-volatile memory device (not shown) such as a NAND flash memory in response to various data write and read requests. The SSD1270may include a Flash Translation Layer FTL that internally performs, for example, garbage collection, address mapping, wear leveling, and the like. Disadvantages of the nonvolatile memory device (e.g., NAND flash memory), such as erase-before-write and mismatch between an erase unit and a write unit, may be supplemented by the flash translation layer FTL. Accordingly, a power shortage condition may be caused even in the SSD1270according to an increase in the amount of computation. In addition, the SSD1270may further include a computing device such as an FPGA. A detailed configuration of the SSD1270will be described in detail inFIG.2to be described later. The storage (e.g., SSD1270) may store data using a second voltage provided from the PMIC1220. The storage (e.g., SSD1270) may include an operation block (e.g., circuit) that performs an auxiliary operation for input/output of data.

According to the computing system1000described above, the computational storage device1200that requests additional power from the outside according to the workload status or power state of internal components may be provided. In some embodiments, the computational storage device1200may stop an operation being processed in the computing module1240and perform a backup operation when an event such as sudden power-off SPO is expected. In addition, the computational storage device1200may transfer status information or parameters of the suspended operation to another computational storage device electrically connected to the backplane1150. Then, another computational storage device electrically connected to the backplane1150may continue executing the suspended operation.

FIG.2is a block diagram showing the configuration of the solid state drive shown inFIG.1by way of example. Referring toFIG.2, an SSD1270may include, for example, a backup power supply1271, a power loss prevention logic1272, an FPGA1273, an SSD controller1274, a nonvolatile memory device1275, and an SSD buffer1276. However, the embodiments of the SSD1270of the present inventive concept is not limited thereto.

The backup power supply1271may supply stored energy to the SSD1270when a power-off event occurs in which external power is cut off. The SSD1270may use energy from the backup power supply1271to complete the operation being performed and perform a data backup operation. Therefore, the reliability of the backup operation may be increased by using the limited energy accumulated in the backup power supply1271efficiently. The backup power supply1271may be, for example, a power supply using a capacitor. As used hereinafter, the terms “external/outside device”, “external/outside power”, external/outside signal”, or “outside” are intended to broadly refer to a device, circuit, block, module, power, and/or signal that resides externally (i.e., outside of a functional or physical boundary) with respect to a given circuit, block, module, system, or device.

The power loss prevention logic1272may be a component for preventing data loss due to the loss of the power that is supplied to the SSD1270. The power loss prevention logic1272may be formed as an integrated circuit IC, chip, and/or device. In a situation where external power is normally supplied, the power loss prevention logic1272may provide the external power as device power PWR to the SSD1270. On the other hand, the power loss prevention logic1272may provide the output of the backup power supply1271to the SSD1270as the device power PWR when external power is cut off.

In some embodiments, the power loss prevention logic1272may detect a sudden power-off SPO event such as external power cut-off or serious voltage drop. When a sudden power-off SPO event is detected, the power loss prevention logic1272may provide a power-off detection signal PO_DET to the SSD controller1274. Also, the power loss prevention logic1272may switch the source of the device power PWR for driving the SSD1270from external power to the backup power supply1271.

The FPGA1273may be a programmable semiconductor device and may perform various operations based on, for example, a program input by a user (or a circuit change by a user). The FPGA1273may be replaced with a non-limiting type of device capable of performing various operations according to an input program. The FPGA1273may be configured to implement some functions of various hardware constituting the SSD1270as software using program functions.

The SSD controller1274may be configured to control the nonvolatile memory device1275and the SSD buffer1276according to a command or control from a host1100. For example, the SSD controller1274may write data to the nonvolatile memory device1275or read data stored in the nonvolatile memory device1275according to a request of the host1100. To access the nonvolatile memory device1275, the SSD controller1274may provide commands, addresses, data, and/or control signals to the nonvolatile memory device1275.

The nonvolatile memory device1275may store data received from the SSD controller1274or transmit stored data to the SSD controller1274. The nonvolatile memory device1275may be provided as an actual storage medium of the computational storage device1200. For example, the nonvolatile memory device1275may be provided as a NAND flash memory having a large storage capacity. The nonvolatile memory device1275may include a plurality of NAND flash memory devices.

The SSD buffer1276may be used as a data buffer for exchanging data between the SSD1270and the host1100. Write data provided from the host1100or data read from the nonvolatile memory device1275may be temporarily stored in the SSD buffer1276. When data existing in the nonvolatile memory device1275is cached upon a read request from the host1100, the SSD buffer1276may support a cache function that directly provides the cached data to the host1100. The SSD buffer1276may be provided as synchronous DRAM to provide sufficient buffering in the SSD1270that may be used as a large-capacity auxiliary storage device. However, the embodiments of the SSD buffer1276of the present inventive concept are not limited thereto.

According to the SSD1270of the present invention described above, the amount of computation for managing the SSD1270that is conducted in the FPGA1273and/or the SSD controller1274may increase. The amount of computation or workload of the FPGA1273and/or the SSD controller1274may be separately monitored by the performance monitoring module1250(seeFIG.1). In some embodiments, when the amount of computation increases beyond the reference value, an additional power request may be generated by the performance monitoring module1250.

In some embodiments, some of components such as the backup power supply1271, the power loss prevention logic1272, the FPGA1273, and the SSD buffer1276included in the SSD1270may be placed outside the SSD1270or omitted. That is, in some embodiments, the SSD1270may include only the SSD controller1274and the nonvolatile memory device1275to perform only a simple storage function.

FIG.3is a flowchart briefly illustrating a monitoring operation performed by a performance monitoring module in the computational storage device according to some embodiments of the present invention. Referring toFIG.3, the performance monitoring module1250(seeFIG.1) may monitor the computing module1240of the computational storage device1200and the FPGA1273and/or the SSD controller1274inside the SSD1270. Also, the performance monitoring module1250may request additional power from the backplane1150or the host1100according to the monitoring result.

In step S110, the performance monitoring module1250may monitor the workload for major operations performed in the computational storage device1200. For example, the performance monitoring module1250may monitor the workload of the computing module1240of the computational storage device1200. In some embodiments, the performance monitoring module1250may monitor the workload or calculation amount of the FPGA1273for the SSD1270and the workload or calculation amount of the SSD controller1274.

In step S120, the performance monitoring module1250may receive the workload (e.g., workload information or workload status) WL_CM from the computing module1240. The performance monitoring module1250may compare the workload WL_CM of the computing module1240with the reference value REFc. If the workload WL_CM of the computing module1240exceeds the reference value REFc (‘Yes’ direction), the process may move to step S150to request additional power. When the workload WL_CM of the computing module1240is equal to or less than the reference value REFc (‘No’ direction), the process may move to step S130.

In step S130, the performance monitoring module1250may receive the workload (e.g., workload information or workload status) WL_SSDC of the SSD controller1274from the SSD1270. The performance monitoring module1250may compare the workload WL_SSDC of the SSD controller1274with reference value REFs. If the workload WL_SSDC of the SSD controller1274exceeds the reference value REFs (‘Yes’ direction), the procedure may move to step S150for requesting additional power. When the workload WL_SSDC of the SSD controller1274is equal to or less than the reference value REFs (‘No’ direction), the process may move to step S140.

In step S140, the performance monitoring module1250may receive the workload (e.g., workload information or workload status) WL_FPGA of the FPGA1273for the SSD1270. The performance monitoring module1250compare the workload WL_FPGA of the FPGA1273with the reference value REFf. If the workload WL_FPGA of the FPGA1273exceeds the reference value REFf (‘Yes’ direction), the procedure may move to step S150for requesting additional power. If the workload WL_FPGA of the FPGA1273is equal to or less than the reference value REFf (‘No’ direction), the process may return to step S110to provide workload information on major operations performed in the computational storage device1200.

In step S150, the performance monitoring module1250may request additional power from the backplane1150or the host1100through the output module1230because the workload or calculation amount exceeding the reference value is detected. Then, power PWR supplied to the computational storage device1200by the backplane1150or the host1100may increase. When the supply of additional power is completed, the process may return to step S110.

In the foregoing, a method for monitoring a workload or an amount of computation of computational devices (e.g., the computational storage device1200) included in the computational storage device1200performed by the performance monitoring module1250according to an embodiment of the present invention has been described. The performance monitoring module1250may support stable power supply of the computational storage device1200by requesting additional power from the backplane1150or the host1100when the workload or calculation amount of the computing devices exceeds a reference value.

FIG.4is a block diagram showing a computing system according to some embodiments of the present invention. Referring toFIG.4, a computing system2000may include a host2100and a plurality of computational storage devices2200and2300. The number of the plurality of computational storage devices are not limited to thereto. For example, the number of the plurality of computational storage devices may be more than two. The computing system2000may be, for example, a device or system such as a server or a data center that collects and processes big data.

The host2100may perform substantially the same functions as the host1100ofFIG.1. Host2100may include one or more CPU and/or GPU cores. The host2100may include a host memory, a network interface card NIC, and a system bus. In some embodiments, the host2100may be a device including a processor core, such as a general-purpose central processing unit CPU, a dedicated application specific integrated circuit ASIC, and/or an application processor AP. The host2100may be a processor itself or an electronic device or system including a processor.

The host2100may generate commands and data for access to the computational storage devices2200and/or2300. The host2100may delegate some of the operations to be processed to the computational storage devices2200and/or2300. For example, the host2100may request the computational storage devices2200and/or2300to process machine learning ML or artificial intelligence AI operations. However, the operations delegated to the computational storage devices2200and/or2300of the present inventive concept are not limited thereto. In some embodiments, the host2100may determine an additional power supply priority of the computational storage devices2200and2300. For example, when the host2100receives an additional power request from both of the computational storage devices2200and2300, the host2100may preferentially provide additional power to one computational storage device in consideration of the importance or urgency of the operation to be processed.

The backplane2150may provide a communication interface between the host2100and the computational storage devices2200and2300. Backplane2150may include signal lines used for communication links and control links, and power supply lines that supply power to various components of the computing system2000such as various components of the computational storage devices2200and2300. That is, the backplane2150may supply power PW1 and PW2 to the computational storage devices2200and2300, respectively under the control of the host2100or under the control of the backplane2150's own power controller. The backplane2150may vary the sizes of the supplied powers PW1 and PW2 according to requests from the output modules2230and2330of the computational storage devices2200and2300, respectively.

The computational storage devices2200and2300may store data according to a request of the host2100or perform a specific operation requested by the host2100. To this end, the first computational storage device2200may include, for example, a first PMIC2210, a first performance monitoring module2220, a first output module2230, a first SSD2240, and a first computing module2250, and/or a first buffer2260. Although not shown, the first computational storage device2200may further include a host interface. The second computational storage device2300may include a second PMIC2310, a second performance monitoring module2320, a second output module2330, a second SSD2340, a second computing module2350, and a second buffer2360. Similarly, the second computational storage device2300may further include a host interface.

The first PMIC2210may distribute the power PW1 provided through the backplane2150to various components of the first computational storage device2200. The first PMIC2210may convert the power PW1 provided from the outside into a stable voltage. The first PMIC2210may transmit the stabilized voltage to the first performance monitoring module2220, the first output module2230, the first SSD2240, the first computing module2250, and/or the first buffer2260.

The first performance monitoring module2220may monitor workloads or calculations of the first SSD2240and the first computing module2250, which are components of the first computational storage device2200. In some embodiments, the first performance monitoring module2220may individually monitor the performance of the SSD controller2241and the first FPGA2242of the first SSD2240. The first performance monitoring module2220may receive workload status of the SSD controller2241, the first FPGA2242, and the first computing module2250. In addition, the first performance monitoring module2220may transmit an additional power request to the backplane2150or the host2100through the first output module2230when an operation amount equal to or greater than a reference value is observed in a specific component. Then, power PW1 supplied to the first computational storage device2200by the backplane2150or the host2100may increase. The first performance monitoring module2220may further include a buffer for receiving and temporarily storing workloads, calculation amounts, or power states of the first SSD2240and the first computing module2250.

In some embodiments, the first performance monitoring module2220may detect power shortage caused by a specific operation of the first computing module2250or an operation of the first SSD2240executed according to a request of the host2100. For example, the first performance monitoring module2220may monitor whether the power PW1 is insufficient or overloaded due to an AI operation or a machine learning ML operation performed by the first computing module2250. In some embodiments, the first performance monitoring module2220may monitor whether the power PW1 supplied for the operation performed by the first SSD2240is insufficient or overloaded. According to the monitoring result, the first performance monitoring module2220may request additional power for the first computational storage device2200(e.g., for the first SSD2240) or give priority of supplying additional power to another computational storage device (e.g., the second computational storage device2300) electrically connected to the backplane2150.

In some embodiments, the first performance monitoring module2220may trigger a backup operation in preparation for sudden power-off SPO of the first computational storage device2200. If a sudden power-off SPO is expected, the first performance monitoring module2220may suspend a specific operation performed in the first computing module2250, and back-up the operation parameters and status information of the suspended state. The backed-up operation parameters and status information may be stored in the second computational storage device2300, the host2100, or a separately provided storage through the first output module2230. Then, the second computational storage device2300may instead execute the suspended operation using the backed-up parameter and status information. In some embodiments, when the first computational storage device2200is restored from sudden power-off SPO, the operation parameter and status information that have been backed up may be returned and the suspended operation may be subsequently performed by the first computational storage device2200.

In some embodiments, when a sudden power-off SPO in the first computing module2250is expected, the first performance monitoring module2220may suspend a specific operation performed in the first computing module2250. And then, the first performance monitoring module2220may back up operation parameters and status information of the suspended state to the first SSD2240. The backed-up operation parameters and status information may be returned from the first SSD2240to the first computing module2250when the first computational storage device2200is restored from sudden power-off SPO. Then, the first computing module2250may subsequently perform the suspended operation using the returned operation parameter and status information.

The first output module2230may transmit power status information generated by the first performance monitoring module2220and a request for additional power to the host2100through the backplane2150. In some embodiments, the first output module2230may transmit power status information generated by the first performance monitoring module2220and additional power request to another computational storage device (not shown) electrically connected to the backplane2150. In some embodiments, the first output module2230may transmit, for example, the workload status of the first computational storage device2200generated by the first performance monitoring module2220, a workload distribution request, and/or a sudden power-off SPO prediction flag to the host2100. In some embodiments, the first output module2230may transmit, for example, the workload status of the first computational storage device2200generated by the first performance monitoring module2220, the SPO prediction flag, and/or the workload distribution request to the second computational storage device2300electrically connected to the backplane2150. The first output module2230may communicate with the host2100or the backplane2150through a host interface (not shown), but may communicate with the host2100or the backplane2150through a separate independent interface. For example, the first output module2230may communicate with the host2100or the backplane2150using interfaces, for example, I2C, UART, and/or SMbus.

The first SSD2240may be provided as storage of the first computational storage device2200. The first SSD2240may write data into the NAND flash memory2245or read data stored in the NAND flash memory2245in response to various data write and read requests. The first SSD2240may include an SSD controller2241that executes a Flash Translation Layer FTL that performs, for example, garbage collection, address mapping, wear leveling, and/or the like. In some embodiments, the first SSD2240may include a first FPGA2242capable of performing an operation for memory management or an operation separate from memory management, a power loss protection PLP capacitor2243, a buffer2244, and a NAND flash memory2245. The first performance monitoring module2220may monitor the workload of the SSD controller2241and the first FPGA2242with a large amount of computation together with the workload of the first computing module2250.

The first computing module2250may perform, for example, artificial intelligence AI operation or machine learning ML operation requested by the host2100to the first computational storage device2200. The first computing module2250may process such operations using, for example, CPU, AP, GPU, NPU, TPU, VPU, Image Signal Processor (ISP), and/or Digital Signal Processor (DSP). In some embodiments, the first computing module2250may be a device such as a Field Programmable Gate Array (FPGA) programmed for a specific operation.

The first buffer2260may be used as a buffer or operating memory of the first computational storage device2200. The first buffer2260may write data or output the written data according to the control of the host2100. The first buffer2260may store the workload status of the first SSD2240and/or the first computing module2250collected by the first performance monitoring module2220. The first buffer2260may store status information about whether or not the power PW1 is insufficient or overloaded due to, for example, an AI operation or a machine learning ML operation of the first computing module2250. In some embodiments, the first buffer2260may back up operation parameters and status information of a specific operation suspended by the first computing module2250when a sudden power-off SPO is expected. Then, the backed-up operation parameters and status information may be transmitted from the first buffer2260to the host2100or the second computational storage device2300. In some embodiments, the backed up operation parameters and status information may be backed up from the first buffer2260to the first SSD2240. The second computational storage device2300may include substantially the same components as the first computational storage device2200. That is, the second PMIC2310, the second performance monitoring module2320, the second output module2330, the second SSD2340, the second computing module2350, and the second buffer2360may be the same as those of the first computational storage device2200. Accordingly, a detailed description of the components of the second computational storage device2300will be omitted.

However, the second SSD2340may store data different from that of the first SSD2240. In some embodiments, the second computing module2350may perform an operation different from that of the first computing module2250(e.g., when the first performance monitoring module2220does not request a backup operation). However, if there is an operation requested by the first performance monitoring module2220, the second computing module2350may execute the operation suspended by the first computing module2250instead.

According to the computing system2000described above, the computational storage devices2200and2300that request additional power from the outside according to the workload or power state of their components may be provided. In some embodiments, when the computational storage devices2200and2300need to use limited power, one of the computational storage devices2200and2300may receive more power according to a priority determined by the performance monitoring modules2220and2320. In some embodiments, the computational storage devices2200and2300may stop an operation being processed by the computing modules2250and2350, respectively and perform a backup operation when sudden power-off SPO is expected.

FIG.5is a diagram illustrating a method of supplying additional power by performance monitoring modules of the computational storage devices ofFIG.4according to some embodiments of the present invention. Referring toFIG.5, a power management method when a request for additional power is generated from both of the computational storage devices2200and2300is described.

In step S210, a power shortage state may be detected in the first computational storage device2200. For example, the first performance monitoring module2220may detect the state in which the amount of calculation performed by the first computing module2250exceeds a reference value.

In step S215, the first performance monitoring module2220may transmit an additional power request to the host2100using the first output module2230.

In step S220, a power shortage state of the second computational storage device2300may be detected at the same time as or at a similar point in time when the power shortage of the first computational storage device2200is detected. For example, a state in which the amount of calculation performed by the second SSD2340or the second computing module2350exceeds the reference value may be detected by the second performance monitoring module2320.

In step S225, the second performance monitoring module2320may transmit an additional power request to the host2100using the second output module2330.

In step S230, the host2100may determine whether sufficient power can be supplied to both the computational storage devices2200and2300. If it is determined that the available power to be supplied to each of the computational storage devices2200and2300is sufficient (‘Yes’ direction), the process may move to steps S232and S234. On the other hand, if it is determined that the available power to be supplied to each of the computational storage devices2200and2300is insufficient (‘No’ direction), the process may move to step S240.

In steps S232and S234, the host2100may supply additional power to both the first computational storage device2200and the second computational storage device2300.

In step S240, the host2100may determine power supply priorities of the computational storage devices2200and2300. For example, the host2100may determine power addition priority according to the urgency or importance of a specific operation executed by each of the first computing module2250and the second computing module2350. If the priority of the first computational storage device2200(e.g., the first computing module2250) is higher than the second computational storage device2300(e.g., the second computing module2350), the process may move to step S242. On the other hand, if the priority of the second computational storage device2300(e.g., the second computing module2350) is higher that the first computational storage device2200(e.g., the first computing module2250), the process may move to step S244.

In step S242, the host2100may increase the amount of power supplied to the first computational storage device2200. That is, additional power may be supplied only to the first computational storage device2200.

In step S244, the host2100may increase the amount of power supplied to the second computational storage device2300. That is, additional power may be supplied only to the second computational storage device2300.

In the above, the power supply method in which the host2100determines the power addition priority when additional power requests are generated from both of the computational storage devices2200and2300has been described.

FIG.6is a diagram illustrating a method of supplying additional power to the computational storage devices ofFIG.4according to some embodiments of the present invention. Referring toFIG.6, a power management method when a request for additional power is generated from both of the computational storage devices2200and2300is described.

In step S310, a power shortage state may be detected by the first performance monitoring module2220of the first computational storage device2200. For example, it may be detected whether an overload of a specific component of the first computational storage device2200occurs at the request of the host2100. That is, whether the amount of computation of the first SSD2240or the first computing module2250exceeds a reference value to process the request of the host2100may be detected by the first performance monitoring module2220. If it is determined that additional power is required in the first computational storage device2200(‘Yes’ direction), the process may move to step S312. On the other hand, if it is determined that additional power is not required in the first computational storage device2200(‘No’ direction), the current power supply state may be maintained.

In step S312, the first performance monitoring module2220may transmit a power shortage state of the first computational storage device2200to the backplane2150using the first output module2230. Then, in step S314, the backplane2150may transmit the power shortage state (PW1 state) of the first computational storage device2200to the second computational storage device2300.

In step S320, a power shortage state of the second computational storage device2300may be detected at the same time as or at a similar point in time when the power shortage of the first computational storage device2200is detected. Whether a specific component of the second computational storage device2300causes a load (e.g., power shortage) may be detected according to a request of the host2100. That is, the second performance monitoring module2320may detect whether the amount of operation of the second SSD2340or the second computing module2350exceeds a reference value to process the request of the host2100. If it is determined that additional power is not needed in the second computational storage device2300(‘No’ direction), the process may move to step S322. On the other hand, if it is determined that additional power is required in the second computational storage device2300(‘Yes’ direction), the process may move to step S330.

In step S322, the second performance monitoring module2320may yield the supply of additional power to the first computational storage device2200. To this end, the second performance monitoring module2320may transmit a message about yielding additional power to the backplane2150using the second output module2330. Then, in step S334, the backplane2150may supply additional power to the first computational storage device2200.

In step S330, the second performance monitoring module2320may determine power supply priorities of the computational storage devices2200and2300. For example, the second performance monitoring module2320may determine the priority of power addition according to the urgency or importance of a specific operation executed in each of the first computing module2250and the second computing module2350. If the priority of the first computational storage device2200(e.g., the first computing module2250) is higher than the second computational storage device2300(e.g., the second computing module2350), the process may move to step S332. On the other hand, when the priority of the second computational storage device2300(e.g., the second computing module2350) is higher than the first computational storage device2200(e.g., the first computing module2250), the process may move to step S340.

In step S332, the second performance monitoring module2320may yield the supply of additional power to the first computational storage device2200. To this end, the second performance monitoring module2320may transmit a message about yielding additional power to the backplane2150using the second output module2330. Then, in step S334, the backplane2150may supply additional power to the first computational storage device2200.

In step S340, the second performance monitoring module2320may transmit an additional power request to the backplane2150using the second output module2330.

In step S345, the backplane2150may increase the amount of power supplied to the second computational storage device2300. That is, additional power may be supplied only to the second computational storage device2300.

In the above, when a load (e.g., power shortage) is generated by a specific operation of the computational storage devices2200and2300, the procedure for determining the priority by the computational storage devices2200and2300has been briefly described.

FIG.7is a block diagram showing a computing system according to some embodiments of the present invention. Referring toFIG.7, a computing system3000may include a host3100and a plurality of computational storage devices3200and3300. The number of the plurality of computational storage devices are not limited to thereto. For example, the number of the plurality of computational storage devices may be more than two. The computing system3000may be, for example, a device such as a server or a data center that collects and processes big data. Here, main components of the host3100, the backplane3150, and the computational storage devices3200and3300may be substantially the same as those ofFIG.4. Therefore, a detailed description of these will be omitted. However, a function corresponding to sudden power-off by the performance monitoring modules3220and3320and the output modules3230and3330may be added to the computing system2000ofFIG.4.

The computational storage devices3200and3300may store data according to a request of the host3100or perform a specific operation requested by the host3100. To this end, the first computational storage device3200may include, for example, a first PMIC3210, a first performance monitoring module3220, a first output module3230, a first SSD3240, and a first computing module3250, and/or a first buffer3260. Although not shown, the first computational storage device3200may further include a host interface. The second computational storage device3300may include, for example, a second PMIC3310, a second performance monitoring module3320, a second output module3330, a second SSD3340, and a second computing module3350, and/or a second buffer3360. Similarly, the second computational storage device3300may further include a host interface.

The first performance monitoring module3220may suspend the operation being processed by the first computing module3250when the power of the first computational storage device3200is unstable or when a sudden power-off SPO is predicted. The case where the power is unstable includes, for example, a case where the voltage supplied from the first PMIC3210or the voltage supplied to the first computing module3250drops below a reference value. For example, a case in which power is unstable may include a case in which current consumption of the first computational storage device3200fluctuates beyond a reference width.

When an operation being performed by the first computing module3250is suspended, the first performance monitoring module3220may transmit status information and parameters of the operation suspended by the first computing module3250to the first SSD3240. Such status information and parameters may be backed up to non-volatile memory (e.g., NAND flash memory3245) provided in the first SSD3240separately. The first performance monitoring module3220may transmit backed-up status information and parameters to the first computing module3250so that the first computing module3250may continue to perform the suspended operation when power is restored or recovered from sudden power-off SPO.

In some embodiments, the first performance monitoring module3220may transmit status information and parameters of the operation suspended by the first computing module3250to the host3100through the backplane3150. Then, the host3100may store status information and parameters of the suspended operation and return the information to the first computing module3250when the power of the first computational storage device3200is restored. The first computing module3250may subsequently perform the suspended operation using the returned status information and parameters. In some embodiments, the host3100may transfer status information and parameters of the suspended operation to another device (e.g., the second computational storage device3300) capable of processing, so that the other device may continue to perform the operation suspended by the first computing module3250.

In some embodiments, when an operation being performed by the first computing module3250is suspended, the first performance monitoring module3220may transmit status information and parameters of the suspended operation to a second computational storage device3300. For example, the first performance monitoring module3220may transfer status information and parameters of the operation stopped by the first computing module3250to the second computational storage device3300through the backplane3150. Then, the second performance monitoring module3320of the second computational storage device3300may use the received status information and parameters to perform the operation stopped by the first computing module3250. Accordingly, the operation stopped in the first computing module3250may be subsequently performed by the second computing module3350. A stopped operation may refer to a suspended operation hereinafter.

Here, an example in which status information and parameters of an operation stopped in the first computing module3250may be transferred to the host3100or the second computing module3350has been described, but the present invention is not limited thereto. That is, the status information and parameters of the operation suspended in the second computing module3350may be transferred to the host3100or the first computing module3250to continue the operation suspended.

FIG.8is a flowchart illustrating a backup operation of a specific operation performed in the computing system ofFIG.7according to some embodiments of the present invention. Referring toFIG.8, when power instability or sudden power-off SPO is detected, an operation being executed in at least one computing module of the computational storage devices3200and3300may be stopped (or suspended). In addition, status information and parameters of the suspended operation may be backed up in a non-volatile memory NVM included in the corresponding computational storage device. Here, for convenience of description, the advantages of the present invention will be described based on the control operation performed by the first performance monitoring module3220of the first computational storage device3200. However, it will be well understood that the same function can also be performed by the second performance monitoring module3320of the second computational storage device3300.

In step S410, the first performance monitoring module3220may monitor the power status of the first computational storage device3200. The power status may include, for example, a state of a voltage supplied to the first computational storage device3200. Also, the power status may include a case in which a sudden power-off SPO is detected in any one of the components of the first computational storage device3200.

In step S420, the first performance monitoring module3220may determine whether power instability is detected. For example, this case may correspond to a case in which power shortage is caused by a specific operation of the first SSD3240or the first computing module3250and the power supply voltage for the first computational storage device3200(e.g., the first SSD3240and/or the first computing module3250) is lowered below a reference value. In some embodiments, sudden power-off SPO may be detected due to an excessive workload for the first SSD3240or the first computing module3250or other factors. If power instability is not detected (‘No’ direction), the procedure may return to step S410. On the other hand, if power instability is detected (‘Yes’ direction), the procedure may move to step S430.

In step S430, the first performance monitoring module3220may suspend the operation processed by the first computing module3250(and/or by the first SSD3240or the first SSD controller3241of the first SSD3240).

In step S440, the first performance monitoring module3220may back up status information and parameters of the operation suspended by the first computing module3250. For example, the first performance monitoring module3220may back up parameters of the stopped state and progress state of the operation stopped (suspended) by the first computing module3250to the nonvolatile memory NVM. Here, the nonvolatile memory NVM may be a separate memory prepared for backup or a NAND flash memory3245of the first SSD3240.

In the above, a method of proceeding to the power loss protection PLP mode of the first computational storage device3200according to some embodiments of the present invention has been briefly described. Thereafter, when power is restored, the backed-up status data and parameters may be loaded into the first computing module3250(and/or the first SSD3240or the first SSD controller3241of the first SSD3240) again, and the suspended operation may be subsequently performed.

FIG.9is a flowchart illustrating a backup operation of operations performed in the computing system ofFIG.7according to some embodiments of the present invention. Referring toFIG.9, when power instability or sudden power-off SPO is detected, an operation being executed in the first computing module3250of the first computational storage device3200may be stopped (suspended). In some embodiments, status information and parameters of the suspended operation may be backed up in non-volatile memory NVM. The backed up status information and parameters may be passed on to other devices electrically connected to the backplane3150and used to continue the suspended operation.

In step S510, the first performance monitoring module3220may monitor the power status of the first computational storage device3200. That is, the first performance monitoring module3220may detect a drop in voltage supplied to the first computational storage device3200or sudden power-off SPO.

In step S520, the first performance monitoring module3220may detect power instability. For example, the first performance monitoring module3220may detect a case in which power shortage is caused by a specific operation of the first SSD3240or the first computing module3250and the supply voltage is lowered below a reference value. For example, sudden power-off SPO may be detected in the first SSD3240or the first computing module3250due to an excessive workload or other factors. If power instability is not detected (‘No’ direction), the procedure may return to step S510. On the other hand, if power instability is detected (‘Yes’ direction), the procedure may move to step S530.

In step S530, the first performance monitoring module3220may suspend the operation processed by the first computing module3250(and/or by the first SSD3240or the first SSD controller3241of the first SSD3240).

In step S540, the first performance monitoring module3220may back up status information and parameters of the operation suspended in the first computing module3250(and/or by the first SSD3240or the first SSD controller3241of the first SSD3240). For example, the first performance monitoring module3220may back up parameters of the stopped state and the progress state of the operation stopped by the first computing module3250(and/or by the first SSD3240or the first SSD controller3241of the first SSD3240) to the nonvolatile memory NVM. Here, the nonvolatile memory NVM may be a separate memory prepared for backup or a NAND flash memory3245of the first SSD3240.

In step S550, the first performance monitoring module3220may request the host3100or the second computational storage device3300to continue the suspended operation. That is, the first performance monitoring module3220may transfer the backed up status information and parameters to the host3100or the second computational storage device3300through the backplane3150. Then, the host3100may use the backed-up status information and parameters to instruct another device (e.g., the second computational storage device3300) that stably operates to continue performing the suspended operation. In some embodiments, when the status information and parameters that are backed up may be directly delivered to the second computational storage device3300, the operation stopped (suspended) by the first computational storage device3200may be subsequently executed by the second computational storage device3300.

In the above, a method of proceeding to the power loss protection PLP mode of the first computational storage device3200according to some embodiments of the present invention has been briefly described.

FIG.10is a block diagram showing a computing system according to some embodiments of the present invention. Referring toFIG.10, a computing system4000may include a host4100, a plurality of computational storage devices4200and4300, and an auxiliary power module4400. The number of the plurality of computational storage devices are not limited to thereto. For example, the number of the plurality of computational storage devices may be more than two. The computing system4000may be, for example, a device such as a server or a data center that collects and processes big data. Here, main components of the host4100, the backplane4150, and the computational storage devices4200and4300are substantially the same as those ofFIG.4orFIG.7. Therefore, a detailed description of these will be omitted.

The computational storage devices4200and4300may store data according to a request of the host4100or perform a specific operation requested by the host4100. To this end, the first computational storage device4200may include, for example, a first PMIC4210, a first performance monitoring module4220, a first output module4230, a first SSD4240, a first computing module4250, and/or a first buffer4260. The second computational storage device4300may include, for example, a second PMIC4310, a second performance monitoring module4320, a second output module4330, a second SSD4340, a second computing module4350, and/or a second buffer4360.

The first performance monitoring module4220and the second performance monitoring module4320of the computational storage devices4200and4300may perform the operation of the first performance monitoring module2220or the second performance monitoring module2320ofFIG.4. For example, the first performance monitoring module4220may monitor the workload or calculation amount of the first SSD4240or the first computing module4250. Further, the first performance monitoring module4220may transmit an additional power request to the backplane4150or the host4100through the first output module4230when an operation amount equal to or greater than a reference value is observed in a specific component of the first computational storage device4200. Then, power PW1 supplied to the first computational storage device4200by the backplane4150or the host4100may increase. In this case, power of the auxiliary power module4400may be used to provide additional power. The second performance monitoring module4320may also perform substantially the same monitoring as the first performance monitoring module4220and transmit an additional power request.

In one example, when a certain embodiment may be implemented differently, a function or operation specified in a specific block may occur in a sequence different from that specified in a flowchart. For example, two consecutive blocks may actually be executed at the same time. Depending on a related function or operation, the blocks may be executed in a reverse sequence. Moreover, the function or operation in the specific block (e.g., step) may be separated into multiple blocks (e.g., steps) and/or may be at least partially integrated.

It will be understood that when an element or layer is referred to as being “connected to”, or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element is referred to as being “directly coupled,” “directly connected,” or “directly responsive” to, or “directly on,” another element, there are no intervening elements present. In addition, “electrical connection” conceptually includes a physical connection and a physical disconnection. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

The above are specific embodiments for carrying out the present invention. In addition to the above-described embodiments, the present invention may include simple design changes or easily changeable embodiments. In addition, the present invention will include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, and should be defined by the claims and equivalents of the claims of the present invention as well as the claims to be described later.