Semiconductor device having temporary signal storage unit

A semiconductor device having a unit capable of temporarily storing electrical signals, may include an electrical signal generation unit, a first signal transmission unit electrically connected to the electrical signal generation unit, a first signal storage unit electrically connected to the first signal transmission unit, a second signal transmission unit electrically connected to the first signal storage unit, a second signal storage unit electrically connected to the second signal transmission unit, a reset unit electrically connected to the second signal storage unit, an amplification unit electrically connected to the second signal storage unit, a selection unit electrically connected to the amplification unit, and an output unit electrically connected to the selection unit, for stable signal processing.

BACKGROUND OF THE INVENTION

1. Field of the Invention

A semiconductor device has a signal storage unit capable of temporarily storing electrical signals, more particularly, a semiconductor device has a temporary signal storage unit in which electrical signals are not distorted.

2. Description of the Related Art

Stable electrical signal processing is very important for semiconductor devices having electrical signal generation units. Even though the electrical signal generation unit may operate in a digital manner, it is difficult not to consider signal loss, excessive amplification, interference between signals, signal transmission delay, or the like when processing generated electrical signals. Also, if a semiconductor device operates in an analog manner, very precise control is required from the point in time at which electrical signals are generated to the point in time at which the final output signals are obtained by performing processes, e.g., amplification, transmission, and reset, for the electrical signals.

For example, a semiconductor device, such as a CMOS image sensor, has an electrical signal generation unit that continuously generates electrical signals in response to received light. In this case, when the electrical signals are processed, the electrical signals are often distorted due to the subsequent generation of electrical signals. As a result, abnormal images may be obtained. The signal distortion described above may be overcome by using a sequential signal processing method. However, problems may occur when implementing a method in which all signals are simultaneously processed.

SUMMARY OF THE INVENTION

The present invention is therefore directed to a semiconductor device which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.

It is therefore a feature of an embodiment of the present invention to provide a semiconductor device, more particularly a CMOS image sensor, which is capable of stably and sequentially processing signals, as well as a method of simultaneously processing signals.

At least one of the above and other features and advantages of the present invention may be realized by providing a semiconductor device that may include an electrical signal generation unit, a first signal transmission unit electrically connected to the electrical signal generation unit, a first signal storage unit electrically connected to the first signal transmission unit, a second signal transmission unit electrically connected to the first signal storage unit, a second signal storage unit electrically connected to the second signal transmission unit, a reset unit electrically connected to the second signal storage unit, an amplification unit electrically connected to the second signal storage unit, a selection unit electrically connected to the amplification unit, and an output unit electrically connected to the selection unit.

The first signal transmission unit may include a transistor having a first electrode electrically connected to the electrical signal generation unit and a second electrode electrically connected to the first signal storage unit. The second signal transmission unit may include a transistor having a first electrode electrically connected to the first signal storage unit and a second electrode electrically connected to the second signal storage unit. The electrical signal generation unit may be an optical charge generation unit, and each of the first and second signal storage units may include a conductive region formed by doping impurities into a substrate. The reset unit may include a transistor having a first electrode electrically connected to the second signal storage unit and a second electrode electrically connected to a device voltage node. The amplification unit may include a transistor having a gate electrode electrically connected to the second signal transmission unit and source and drain electrodes, one of which may be electrically connected to the device voltage node. The selection unit may include a transistor having a first electrode electrically coupled to a first electrode of the amplification unit and a second electrode electrically coupled to the output unit. The semiconductor device may further include a discharge unit having a first electrode coupled to the electrical signal generation unit and a second electrode coupled to a device voltage node.

At least one of the above and other features and advantages of the present invention may be realized by providing a CMOS image sensor that may include a pixel array, in which the pixel array may include a first pixel unit having a first signal generation unit, a first signal transmission unit electrically connected to the first signal generation unit, a first signal storage unit electrically connected to the first signal transmission unit, and a second signal transmission unit electrically connected to the first signal storage unit, a second signal storage unit electrically connected to the second signal transmission unit, a reset unit and an amplification unit electrically connected to the second signal storage unit, a selection unit electrically connected to the amplification unit, and an output unit electrically connected to the selection unit.

The reset unit may be a transistor having a first electrode electrically connected to the second signal storage unit and a second electrode electrically connected to a device voltage node. The amplification unit may be a transistor having a gate electrode electrically connected to the second signal storage unit, a first electrode electrically connected to a pixel voltage node, and a second electrode electrically connected to the selection unit. The selection unit may include a transistor having a first electrode electrically connected to the amplification unit and a second electrode electrically connected to the output unit.

The CMOS image sensor may further include a second pixel unit having a second signal generation unit, a third signal transmission unit electrically connected to the second signal generation unit, a third signal storage unit electrically connected to the third signal transmission unit, and a fourth signal transmission unit electrically connected to the second signal storage unit. The first signal transmission unit may include a transistor having a first source electrode and a first drain electrode, one of which may be electrically connected to the first signal generation unit and the other one which may be electrically connected to the first signal storage unit. The second signal transmission unit may include a transistor having a second source electrode and a second drain electrode, one of which may be electrically connected to the first signal storage unit and the other one which may be electrically connected to the second signal storage unit. The third signal transmission unit may include a transistor having a third source electrode and a third drain electrode, one of which may be electrically connected to the second signal generation unit and the other one which may be electrically connected to the second signal storage unit. The fourth signal transmission unit may include a transistor having a fourth source electrode and a fourth drain electrode, one of which may be electrically connected to the third signal storage unit and the other one which may be electrically connected to the second signal storage unit.

The pixel array may further include a first overflow transistor having a first electrode electrically connected to the first signal generation unit and a second electrode connected to a device voltage node, and a second overflow transistor having a first electrode electrically connected to the second signal generation unit and a second electrode connected to the device voltage node.

At least one of the above and other features and advantages of the present invention may be realized by providing a CMOS image sensor that may include an optical charge generation unit that may be formed within a substrate, a first transistor that may be formed on the substrate and may be adjacent to the optical charge generation unit, a first signal storage unit that may be formed within the substrate and may be adjacent to the first transistor, a second transistor that may be formed on the substrate and may be adjacent to the first signal storage unit, a second signal storage unit that may be formed within the substrate and may be adjacent to the second transistor, and a reset transistor that may be formed on the substrate and may be electrically connected to the second signal storage unit.

The first transistor may be formed on the second transistor such that the first transistor may partially overlap the second transistor. The CMOS image sensor may further include a third transistor that may be formed on the substrate adjacent to the optical charge generation unit, and the third transistor may have a source electrode and a drain electrode, one of which may be connected to a device voltage node. The CMOS image sensor may further include an amplifying transistor that may be formed on the substrate and may be electrically connected to the second signal storage unit, a selection transistor that may be electrically connected to the amplifying transistor, and an output transistor that may be electrically connected to the selection transistor. The second signal storage unit and the amplifying transistor may be electrically connected with polysilicon. A device voltage node may electrically connect to at least one of the reset transistor and the amplifying transistor, and the second signal storage may be electrically connected to the gate electrode of the amplifying transistor.

At least one of the above and other features of the present invention is to provide a CMOS image sensor that may include a first signal generation unit, a first signal transmission unit that may be adjacent to the first signal generation unit, a second signal transmission unit that may be formed to partially overlap the first signal transmission unit, a signal storage unit that may be adjacent to the second signal transmission unit, and a reset unit that may be adjacent to the signal storage unit.

The CMOS image sensor may further include a second signal generation unit, a third signal transmission unit that may be adjacent to the second signal generation unit, and a fourth signal transmission unit that may be formed to partially overlap the third signal transmission unit. The fourth signal transmission unit may be adjacent to the signal storage unit.

The CMOS image sensor may further include a fifth signal transmission unit that may be adjacent to the first signal transmission unit and the second signal transmission unit. The CMOS image sensor may further include an amplification unit and a selection unit.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application No. 10-2006-0025023 filed on Mar. 17, 2006, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device Having Temporary Signal Storage Unit,” is incorporated by reference herein in its entirety.

In some of the embodiments of the invention, an optical charge generation unit generating electrical signals by using received light may be depicted as a specific example. However, examples of devices that generate electrical signals may include all kinds of transducers or devices that generate electrical signals in response to pressure, heat, or physical or chemical stimuli, as well as the optical charge generation unit generating electrical signals by using the received light.

The invention will be described with reference to plan views and cross-sectional views, which are ideal schematic views. The embodiments of the invention are not limited to the specific forms that are shown.

A transistor may mean a field effect transistor (FET). In a field effect transistor, a source electrode and a drain electrode may be located at both sides of a gate electrode. The operation of the source and drain electrodes may be symmetrical, and the functions of the source and drain electrodes may be interchanged, that is, the source and drain electrodes may be symmetrical. Therefore, a source electrode referred in this specification may also be regarded as a drain electrode, and a drain electrode may also be regarded as a source electrode. These terms are used only to facilitate an easy understanding of the operation of the FET but do not limit the positions of electrodes of the FET. For this reason, the gate electrode of the FET is referred to as a “gate electrode”, and the source electrode or the drain electrode is referred to as a “first electrode” or a “second electrode”. Here, the “first electrode” may mean one of the source and drain electrodes, and the “second electrode” means the other electrode.

Further, the term “connected” in this specification may mean “electrically connected”. The meaning of “connected” may include a direct physical connection or an indirect connection using a capacitor, a reactor, a resistor, or other electrical elements. In other words, the meaning of “connected” may include “coupled” in addition to “connected”. In some parts of this specification, the term “connected” may be used to make the technology of the invention more easily understood. Furthermore, the term “coupled” may be omitted to prevent the disclosure from becoming complicated due to expressing “connected or coupled” for each explanation. However, in some parts of the disclosure, the term “coupled” may be necessarily used to indicate that the term “connected” should not be regarded as a limiting term.

Furthermore, a term “device voltage node” may be used. The “device voltage node” may be a node at which a maximum voltage Vdd or a minimum voltage Vss is applied, the maximum voltage Vdd or the minimum voltage Vss being a voltage applied to a typical semiconductor device. Also, in a semiconductor device having a cell region, the “device voltage node” may be a node at which a maximum voltage Vcc or a minimum voltage Vss is applied, and the maximum voltage Vcc or the minimum voltage Vss may be a voltage used within the cell. The minimum voltage Vss may be a common voltage used within a semiconductor device, and device voltages Vdd and Vcc may be different from each other or equal to each other. More specifically, the device voltage Vdd may be higher or lower than the cell voltage Vcc. This is because, when designing a semiconductor device, a designer may use various potentials so as to obtain desired operation characteristics of the semiconductor device. Therefore, the terms “device voltage node” and “cell voltage node” used in this specification may be regarded as being interchangeable. For this reason, in this specification, the terms of “device voltage node” and “cell voltage node” are commonly called “device voltage node”.

A semiconductor device according to an embodiment of the invention will be described in detail with reference to the accompanying drawings.

FIG. 1Aillustrates a block diagram explaining the basic configuration of a semiconductor device according to an embodiment of the invention. Connection lines between blocks mean that electrical signals may be transmitted between the blocks.

Referring toFIG. 1A, a semiconductor device may include an electrical signal generation unit10, a first signal transmission unit20electrically connected to the electrical signal generation unit10, a first signal storage unit25electrically connected to the first signal transmission unit20, a second signal transmission unit30electrically connected to the first signal storage unit25, a second signal storage unit35electrically connected to the second signal transmission unit30, a reset unit40electrically connected to the second signal storage unit35, an amplification unit50electrically connected to the second signal storage unit35, a selection unit60electrically connected to the amplification unit50, and an output unit65electrically connected to the selection unit60.

The electrical signal generation unit10may be an optical charge generation unit, e.g., a photodiode, which generates electrical signals in response to incident light. Specifically, the intensity of an electrical signal or the amount of charges may be changed depending on the intensity of the incident light. An electrical signal with low intensity or a small amount of charge may be generated when a small amount of light is received, and an electrical signal with high intensity or a high amount of charges may be generated when a large amount of light is received. The optical signal generation unit10may have differing sensitivities to different intensities of incident light.

The first signal transmission unit20may be turned on or off, so that the first signal transmission unit20may transmit electrical signals generated in the electrical signal generation unit10to the first signal storage unit25. Specifically, the first signal transmission unit20may transmit the electrical signals generated in the electrical signal generation unit10to the first signal storage unit25when the first signal transmission unit20is turned on, but the first signal transmission unit20may not transmit the electrical signals generated in the electrical signal generation unit10to the first signal storage unit25when the first signal transmission unit20is turned off. More specifically, the first signal transmission unit20may include one or more transistors. Either a source electrode or a drain electrode of each of the transistors included in the first signal transmission unit20may be electrically connected to the electrical signal generation unit10. Alternatively, either the source electrode or the drain electrode of each of the transistors may be electrically connected to the first signal storage unit25. A gate electrode of the transistor included in the first signal transmission unit20may be turned on or off in response to a control signal supplied from a control unit (not shown).

The first signal storage unit25may temporarily store the electrical signals transmitted from the first signal transmission unit20. Specifically, the first signal storage unit25may be composed of a conductive region and may serve as a capacitor capable of storing electrical signals when floated. More specifically, the first signal storage unit25may be a capacitor, and the first signal storage unit25may be an impurity-doped region where charges may be stored when floated.

The second signal transmission unit30may be turned on or off, so that the second signal transmission unit30may serve to transmit electrical signals stored in the first signal storage unit25to the second signal storage unit35. Specifically, the second signal transmission unit30may transmit the electrical signals stored in the first signal storage unit25to the second signal storage unit35when the second signal transmission unit30is turned on. However, the second signal transmission unit30may not transmit the electrical signals stored in the first signal storage unit25to the second signal storage unit35when the second signal transmission unit30is turned off. More specifically, the second signal transmission unit30may include one or more transistors. Either a source electrode or a drain electrode of each of the transistors included in the second signal transmission unit30may be electrically connected to the first signal storage unit25. Alternatively, either the source electrode or the drain electrode of each of the transistors may be electrically connected to the second signal storage unit35. A gate electrode of the transistor included in the second signal transmission unit30may be turned on or off in response to a control signal supplied from a control unit (not shown).

The second signal storage unit35may temporarily store the electrical signals transmitted from the second signal transmission unit30. Specifically, the second signal storage unit35may be composed of a conductive region and may serve as a capacitor capable of storing electrical signals when floated. Further, second signal storage unit35may serve as a signal transmission line by which the electrical signals transmitted from the second signal transmission unit30may be transmitted to other components, such as the reset unit40or the amplification unit50. The second signal storage unit35may be a capacitor, and the second signal storage unit35may be an impurity-doped region where charges may be stored when floated.

The reset unit40may be turned on or off. When the reset unit40is turned on, the reset unit40may perform a reset operation in which electrical signals may be input to the second signal storage unit35or electrical signals stored in the second signal storage unit35may be output. Specifically, the reset unit40may include transistors. Either a source electrode or a drain electrode of each of the transistors included in the reset unit40may be electrically connected to the second signal storage unit35or a device voltage node. Further, the transistors included in the reset unit40may be turned on or off in response to electrical signals input to gate electrodes, where the electrical signals may be generated in a reset control unit (not shown). More specifically, when the electrical signal generated in the reset control unit is applied to the gate electrode so as to turn on the transistor, the reset unit40may either i) output electrical signals stored in the second signal storage unit35, or ii) input electrical signals to the second signal storage unit35by electrically shorting the second signal storage unit35and the device voltage node.

The amplification unit50may be electrically connected to the second signal storage unit35, and the amplification unit50may output electrical signals that are amplified corresponding to the intensity of the electrical signals stored in the second signal storage unit35. Specifically, the amplification unit50may include one or more transistors. When electrical signals are supplied from the second signal storage unit35to gate electrodes of the transistors, the amplification unit50may generate electrical signals that are amplified. Either a source electrode or a drain electrode of each of the transistors may be electrically connected to the selection unit60or the cell voltage node. More specifically, the transistors included in the amplification unit50may be turned on when electrical signals are applied from the second signal storage unit35to the gate electrodes of the transistors. When the transistors are turned on, the electrical signals may be transmitted from the cell voltage node to the selection unit60. When the second signal storage unit35is reset by the operation of the reset unit40, the transistors included in the amplification unit50may be turned off.

The selection unit60may serve to selectively transmit the electrical signals, which have been transmitted from the amplification unit50, to the output unit65. Specifically, the selection unit60may include one or more transistors and may transmit electrical signals, which may have been transmitted from the amplification unit50in response to a selection command from a selection control unit (not shown), to the output unit65. Gate electrodes of the transistors included in the selection unit60may be electrically connected to the selection control unit, so that the transistors may turn on or off in response to the selection command transmitted through electrical signals. The electrical signals transmitted from the amplification unit50may be transmitted to the output unit65when the transistors are turned on, but the electrical signals transmitted from the amplification unit50may not be transmitted to the output unit65when the transistors are turned off. That is, source electrodes or drain electrodes of the transistors may be electrically connected to the amplification unit50or the output unit65.

The output unit65may transmit the electrical signals transmitted from the selection unit60to the outside or to functional components that perform specific functions. Specifically, the output unit65may be a signal transmission line by which electrical signals are transmitted. Alternatively, the output unit65may be formed from functional components that perform amplification or buffering.

Hereafter, operation of the semiconductor device illustrated inFIG. 1Awill be described.

First, when the electrical signal generation unit10generates electrical signals, the first signal transmission unit20may be turned on or off to transmit the electrical signals to the first signal storage unit25. The first signal storage unit25may temporarily store the electrical signals transmitted from the first signal transmission unit20. The second signal transmission unit30may be turned on or off to transmit the electrical signals stored in the first signal storage unit25to the second signal storage unit35. At this time, the first signal transmission unit20and the second signal storage unit35may be independently turned on or off according to separate control signals. The second signal storage unit35may then temporarily store the electrical signals transmitted from the second signal transmission unit30and transmit the electrical signals to the reset unit40or the amplification unit50. Then, the amplification unit50may output electrical signals, which are obtained by amplifying the electrical signals transmitted from the second signal storage unit35, to the selection unit60. The amplification unit50may output electrical signals that are amplified in proportion to the intensity of the electrical signals transmitted from the second signal storage unit35. Then, the selection unit60may be turned on or off to output the electrical signals transmitted from the amplification unit50to the output unit65. The selection unit60may be turned on or off in response to a selection control signal. The output unit65may transmit the electrical signals output from the selection unit60to the outside or to other functional components. When the selection unit60is turned on to output electrical signals, the reset unit40may be turned on by a received reset signal so that the second signal storage unit35may be reset.

FIG. 1Billustrates a block diagram explaining the basic configuration of a semiconductor device according to another embodiment of the invention. Connection lines between blocks mean that electrical signals may be transmitted between the blocks.

InFIG. 1B, the semiconductor device may include an electrical signal generation unit10, a first signal transmission unit20electrically connected to the electrical signal generation unit10, a first signal storage unit25electrically connected to the first signal transmission unit20, a second signal transmission unit30electrically connected to the first signal storage unit25, a second signal storage unit35electrically connected to the second signal transmission unit30, a reset unit40electrically connected to the second signal storage unit35, an amplification unit50electrically connected to the second signal storage unit35, a selection unit60electrically connected to the amplification unit50, an output unit65electrically connected to the selection unit60, and a discharge unit70.

The configuration of the device, except for the discharge unit70, has been described above inFIG. 1A, and an explanation of redundant components will be omitted.

When the first signal transmission unit20is turned off, the discharge unit70may discharge electrical signals if electrical signals generated in the electrical signal generation unit10are excessive. Specifically, the discharge unit70may include one or more transistors. Either a source electrode or a drain electrode of each of the transistors may be electrically connected to the electrical signal generation unit10. The transistors included in the discharge unit70may be turned on by a control signal so that the electrical signals generated in the electrical signal generation unit10may be discharged. Alternatively, the discharge unit70may always be in a turned-on state with a threshold voltage. If the discharge unit70is turned on by the control signal, the first signal transmission unit20may be first turned on to transmit the electrical signals generated in the electrical signal generation unit10to the first signal storage unit25, and then turned off. Next, the discharge unit70may be turned on by the control signal, and it may be possible to discharge electrical signals that are excessively or continuously generated in the electrical signal generation unit10and then turned off. The discharge unit70may be electrically connected to the device voltage node.

Next, a CMOS image sensor according to another embodiment of the invention will be described.

FIG. 2Aillustrates a circuit diagram of a CMOS image sensor according to another embodiment of the invention. In particular, a circuit capable of performing one-step signal processing will be explained as a representative example.

InFIG. 2A, the CMOS image sensor may include an optical charge generation unit110, e.g., a photodiode, that generates electrical signals by using absorbed light. A first transistor120having a first electrode may be electrically connected to the optical charge generation unit110and a second electrode to which the electrical signals generated in the optical charge generation unit110are transmitted. A first conductive unit125that may be electrically connected to the second electrode of the first transistor120, and the first conductive unit125may receive and store electrical signals transmitted from the first transistor120. A second transistor130may have a first electrode electrically connected to the first conductive unit125and a second electrode to which the electrical signals generated in the first conductive unit125may be transmitted. A second conductive unit135may be electrically connected to the second electrode of the second transistor130, and the second conductive unit135may receive and store electrical signals transmitted from the second transistor130. A first reset transistor140may have a first electrode electrically connected to the second conductive unit135and a second electrode connected to a first device voltage node145, and the first reset transistor may reset the second conductive unit135by using a reset signal applied to a gate thereof. An amplifying transistor150may have a gate electrode electrically connected to the second conductive unit135, a first electrode connected to a second device voltage node155, and a second electrode electrically connected to a first electrode of a selection transistor160. The selection transistor160may have a first electrode electrically connected to the second electrode of the amplifying transistor150, and the selection transistor160may transmit electrical signals of the first electrode to a second electrode thereof in response to a turn-on/turn-off signal applied to the gate thereof. An output line165may electrically connect to the second electrode of the selection transistor160.

The optical charge generation unit110may be a photodiode that generates electrical signals by using absorbed light.

Since the gate electrode of each of the first transistor120and the second transistor130electrically connects to the control unit (not shown), the first transistor120and second transistor130may be turned on or off in response to electrical signals generated in the control unit. The first transistor120and the second transistor130may operate independently from each other.

Each of the first conductive unit125and the second conductive unit135may be a region of a semiconductor substrate into which impurities may be doped so as to have conductivity. For example, boron, phosphorus, arsenic, or the like may be doped into the region, and in particular, group V impurities, e.g., phosphorus or arsenic, may be doped into the region. Alternatively, the first conductive unit125and the second conductive unit135may be capacitors.

The first reset transistor140may reset the second conductive unit135in response to a reset signal, which may be applied to the gate electrode from the reset control unit (not shown), and the second electrode of the first reset transistor140may be electrically connected to the first device voltage node145.

The amplifying transistor150may operate as a source follower in which the amount of charges to be output to the first electrode may be adjusted on the basis of the intensity of electrical signals applied to the gate electrode, and the second electrode of the amplifying transistor150may be connected to the second device voltage node155. In particular, electrical connection between the second conductive unit135and the amplifying transistor150may be made by using, e.g., polysilicon. Leakage current may be minimized when the polysilicon is used.

The selection transistor160may be turned on or off in response to a selection signal that may be applied to the gate electrode from the selection control unit (not shown), and the selection transistor160may transmit the electrical signals, which are transmitted from the first electrode of the amplification transistor150, to the output line165.

The structure encompassing the optical charge generation unit110to the selection transistor160may be considered a pixel in a broad sense. Alternately, the structure encompassing the optical charge generation unit110to the second transistor130may be considered a pixel in a narrow sense.

Operation of the CMOS image sensor shown inFIG. 2Awill be briefly described.

When the optical charge generation unit110absorbs incident light, the optical charge generation unit110may generate electrical signals proportional to the intensity of the light. Then, the first transistor120may be turned on to transmit the electrical signals generated by the optical charge generation unit110to the first conductive unit125, and the first transistor120may then be turned off. Then, the first conductive unit125may temporarily store the electrical signals transmitted from the first conductive unit125. The second transistor130may subsequently turn on to transmit the electrical signals stored in the first conductive unit125to the second conductive unit135, and the second transistor130may then be turned off. The second conductive unit135may then transmit the electrical signals transmitted from the second conductive unit135to the gate electrode of the amplifying transistor150. Subsequently, the amplifying transistor150may transmit electrical signals, which may be amplified corresponding to the intensity of the electrical signals applied to the gate, to the first electrode of the selection transistor160. Then, the selection transistor160may turn on in response to a turn-on signal applied to the gate, the electrical signals transmitted to the first electrode may be transmitted to the output line165, and the selection transistor160may then be turned off. Then, a reset signal may be applied to the gate electrode of the first reset transistor140so as to reset the second conductive unit135. Thus, an operation during a period for which a pixel outputs an electrical signal may be completed.

In the CMOS image sensor, since the first transistor120may be turned off after transmitting electrical signals to the first conductive unit125, other electrical signals may not be further transmitted to the first conductive unit125to the output line165. Therefore, it may be possible to prevent signals from being distorted due to continuous transmissions of electrical signals.

FIG. 2Billustrates a circuit diagram of a CMOS image sensor according to another embodiment of the invention.

FIG. 2Bdepicts a CMOS image sensor that may be similar to that shown inFIG. 2Abut may further include an overflow transistor170having a first electrode that may electrically connect to the optical charge generation unit110.

A second electrode of the overflow transistor170may electrically connect to a third device voltage node175.

The CMOS image sensor shown inFIG. 2Bmay further perform an operation in which the overflow transistor170may be turned on if electrical signals generated in the optical charge generation unit110are excessive after the first transistor120is turned off. Alternately, the overflow transistor170may be turned on when the first transistor120is turned off so that electrical signals continuously generated in the optical charge generation unit110are discharged to the third device voltage node175. These functions may be in addition to the operations of the CMOS image sensor described with reference toFIG. 2A.

In the CMOS image sensor shown inFIG. 2B, excessive or unnecessary electrical signals generated in the optical charge generation unit110may be discharged through the overflow transistor170. Accordingly, operation of the CMOS image sensor may be stabilized.

FIG. 2Cillustrates a circuit diagram of a CMOS image sensor according to another embodiment of the invention.

FIG. 2Cdepicts a CMOS image sensor that may be similar to that shown inFIG. 2AandFIG. 2B, but may further include a second reset transistor180having a first electrode that may be electrically connected to the first conductive unit125.

A second electrode of the second reset transistor180may be connected to a device voltage node185, and the second reset transistor180may reset the first conductive unit125in response to a reset signal applied to a gate thereof from a control unit (not shown).

FIG. 3Aillustrates a circuit diagram of a pixel array of a CMOS image sensor according to another embodiment of the invention.

InFIG. 3A, the pixel array of the CMOS image sensor may include a first pixel unit A having a first signal generation unit210a, a first signal transmission unit220aelectrically connected to the first signal generation unit210a, a first signal storage unit225aelectrically connected to the first signal transmission unit220a, and a second signal transmission unit230aelectrically connected to the first signal storage unit225a. A second pixel unit B may have a second signal generation unit210b, a third signal transmission unit220belectrically connected to the second signal generation unit210b, a second signal storage unit225belectrically connected to the third signal transmission unit220b, and a fourth signal transmission unit230belectrically connected to the second signal storage unit225b. A third signal storage unit235aand a fourth signal storage unit235bmay be are electrically connected to the second signal transmission unit230aof the first pixel unit A and the fourth signal transmission unit230bof the second pixel unit B.

The pixel array ofFIG. 3Amay further include a first reset unit240and an amplification unit250that may be electrically connected to the third signal storage unit235aand the fourth signal storage unit235b, a selection unit260that may be electrically connected to the amplification unit250, and an output unit265that may be electrically connected to the selection unit260. The first reset transistor240may have an electrode connected to a device voltage node245.

Since the third signal storage unit235aand the fourth signal storage unit235bmay be electrically connected to each other, the third signal storage unit235aand the fourth signal storage unit235bmay accordingly be replaced with one signal storage unit. This will be described in detail below when explaining a circuit operation.

The functions and operation of the first signal generation unit210ato the second signal transmission unit230a, and the function and operations of the second signal generation unit210bto the fourth signal transmission unit230b, may be understood in light of the above explanation made with reference toFIG. 2A.

The two pixel units A and B shown inFIG. 3Amay sequentially output electrical signals. The second signal transmission unit230aand the fourth signal transmission unit230bmay not be simultaneously turned on. Accordingly, the third signal storage unit235aand the fourth signal storage unit235bmay not simultaneously store the transmitted electrical signals. Thus, the third signal storage unit235aand the fourth signal storage unit235bmay be integrated into one component. Even though the third signal storage unit235aand the fourth signal storage unit235bmay be shown as separate components in the drawings in order to make the invention and its operation easily understood, the third signal storage unit235aand the fourth signal storage unit235bmay be considered as one unified component.

Basically, the signal transmission units220a,220b,230a, and230bincluded in the two pixel units A and B may operate independently from one another. On the other hand, the first signal transmission unit220aand the third signal transmission unit220bmay be simultaneously turned on or off by using one kind of control signal. However, when the second signal transmission unit230aand the fourth signal transmission unit230bare simultaneously turned on, two kinds of electrical signals may interfere with each other in the third signal storage unit235aand the fourth signal storage unit235b. For this reason, the second signal transmission unit230aand the fourth signal transmission unit230bmay not be simultaneously turned on. In contrast, even if the first signal transmission unit220aand the third signal transmission unit220bare simultaneously turned on, the electrical signals may be stored in the first signal storage unit225aand the second signal storage unit225b, and accordingly, the two kinds of electrical signals do not interfere with each other. Thus, the first signal transmission unit220aand the third signal transmission unit220bmay be simultaneously turned on or off by using one kind of control signal.

Next, an operation of outputting electrical signals generated in the two pixel units A and B will be briefly described. That is, operation in which two kinds of electrical signals are output will be described.

First, the signal generation units210aand210bof the pixel units A and B may generate electrical signals. Then, the first signal transmission unit220aand the third signal transmission unit220bmay be turned on to transmit the electrical signals to the first signal storage unit225aand the second signal storage unit225b, and the electrical signals may be stored in the first signal storage unit225aand the second signal storage unit225b. Then, the second signal transmission unit230amay be turned on to transmit the electrical signal stored in the first signal storage unit225ato the third signal storage unit235a. The electrical signal transmitted to the third signal storage unit235amay be applied to the amplification unit250, and the amplification unit250transmits an electrical signal, which may be amplified corresponding the intensity of the electrical signal that has been applied, to the selection unit260. The amplification unit may have a voltage node255. Then, the selection unit260may be turned on to output the electrical signal, which may have been transmitted from the amplification unit250, to the output unit265, and thus the selection unit260may be turned off. At the same time as the electrical signal may be output to the output unit265, the first reset unit240may be turned on to reset the third signal storage unit235a. When the first reset unit240is turned off, the fourth signal transmission unit230bmay be turned on to transmit the electrical signal, which has been stored in the second signal storage unit225b, to the fourth signal storage unit235b. The electrical signal transmitted to the fourth signal storage unit235bmay be applied to the amplification unit250, and the amplification unit250may generate an electrical signal, which may be amplified corresponding to the intensity of the electrical signal that has been applied, to the selection unit260. Then, the selection unit260may be turned on to output the electrical signal, which has been transmitted from the amplification unit250, to the output unit265, and thus the selection unit260may be turned off. Then, at the same time as the electrical signal may be output to the output unit265, the first reset unit240may be turned on to reset the fourth signal storage unit235b. As such, an operation, which may be performed during a period, of the CMOS image sensor shown inFIG. 3Amay be completed.

FIG. 3Billustrates a circuit diagram of a pixel array of a CMOS image sensor according to another embodiment of the invention.

InFIG. 3B, the first pixel unit A explained with reference toFIG. 3Amay further include a first discharge unit270a, and the second pixel unit B explained with reference toFIG. 3Amay further include a second discharge unit270b.

The first discharge unit270amay discharge excessive electrical signals generated in the first signal generation unit210a, or the first discharge unit270amay be turned on when the first signal transmission unit220ais turned off so that electrical signals continuously generated in the first signal generation unit210amay discharge. Further, the second discharge unit270bmay discharge excessive electrical signals generated in the second signal generation unit210b, or the second discharge unit270bmay be turned on when the second signal transmission unit220bis turned off so that electrical signals generated in the second signal generation unit210bmay discharge.

The first discharge unit270aand the second discharge unit270bmay be electrically connected to a common node, and the common node may be electrically connected to a third device voltage node275.

FIG. 3Cillustrates a circuit diagram of a pixel array of a CMOS image sensor according to another embodiment of the invention.

FIG. 3Cincludes a pixel array of the CMOS image sensor that may further include a second reset unit280having a first electrode that may be electrically connected to the first signal storage unit225aand the second signal storage unit225b.

A second electrode of the second reset unit280may connect to a fourth device voltage node285, and the second reset unit280may reset the first conductive unit125in response to a reset signal applied to a gate electrode thereof from a control unit (not shown).

FIG. 4Aillustrates a circuit diagram of a pixel array of a CMOS image sensor having multi pixels according to another embodiment of the invention.

InFIG. 4A, the pixel array of the CMOS image sensor may include a first pixel unit A that may have a first signal generation unit310a, a first signal transmission unit320aelectrically connected to the first signal generation unit310a, a first signal storage unit325aelectrically connected to the first signal transmission unit320a, and a second signal transmission unit330aelectrically connected to the first signal storage unit325a. A second pixel unit B may have a second signal generation unit310b, a third signal transmission unit320belectrically connected to the second signal generation unit310b, a second signal storage unit325belectrically connected to the third signal transmission unit320b, and a fourth signal transmission unit330belectrically connected to the second signal storage unit325b. A third signal storage unit335aand a fourth signal storage unit335bmay be electrically connected to the second signal transmission unit330aof the first pixel unit A and the fourth signal transmission unit330bof the second pixel unit B. The pixel array may continue until a final nth pixel unit X that may have an nth signal generation unit310x, an nth signal transmission unit320xelectrically connected to the nth signal generation unit310x, an nth signal storage unit325xelectrically connected to the nth signal transmission unit320x, and an nth signal transmission unit330xelectrically connected to the nth signal storage unit325x. An nth signal storage unit335xand an nth signal storage unit335xmay eventually be electrically connected to the second signal transmission unit330aof the first pixel unit A and the fourth signal transmission unit330bof the second pixel unit B.

The pixel array ofFIG. 4Amay further include a first reset unit340and an amplification unit350that may be electrically connected to the third signal storage unit335a, the fourth signal storage unit335bup to the nth signal storage unit335x. The amplification unit350may have voltage node355. A selection unit360may be electrically connected to the amplification unit350, and an output unit365that may be electrically connected to the selection unit360. The first reset transistor340may have an electrode connected to a device voltage node345. Since the signal storage units335a,335b. . .335xmay be electrically connected to each other, the signal storage units335a,335b. . .335xmay accordingly be replaced with one signal storage unit.

InFIG. 4A, reference numeral “x” may be used to denote any number of elements. Taking the bit configuration of a typical semiconductor device into consideration, “x” may be a number corresponding to 2N, e.g., 4, 8, 16, 64, or 256, but is not limited thereto.

FIG. 4Billustrates a circuit diagram of a pixel array of a CMOS image sensor having multi pixels according to another embodiment of the invention.

InFIG. 4B, the pixel array of the CMOS image sensor having multi pixels includes multiple pixel units A and B, as typically are shown inFIG. 3B. InFIG. 4B, reference numeral “x” may be used to denote multiple elements. Here, “x” may be a number corresponding to 2N, e.g., 4, 8, 16, 64, or 256, but may be not limited thereto.

Multiple discharge units370a,370b. . .370xmay be electrically connected to a common node that electrically connects to a third device voltage node375.

FIG. 4Cillustrates a circuit diagram of a pixel array of a CMOS image sensor having multi pixels according to another embodiment of the invention.

InFIG. 4C, the pixel array of the CMOS image sensor having multi pixels multiple pixel units A and B, as are typically shown inFIG. 3B. InFIG. 4C, reference numeral “x” may be used to denote multiple elements. Here, “x” may be a number corresponding to 2N, e.g., 4, 8, 16, 64, or 256, but may be not limited thereto.

A first electrode of a second reset unit380may electrically connect to first signal storage units325a,325b. . .325xof respective pixel units, and a second electrode of the second reset unit380may electrically connect to a fourth device voltage node385. Further, the second reset unit380may reset the first signal storage units325a,325b. . .325xof the respective pixel units in response to a reset signal applied to a gate electrode thereof from a control unit (not shown).

Next, layouts of the CMOS image sensors according to the various embodiments of the invention, and longitudinal sectional views of the CMOS image sensors on a semiconductor substrate, will be described.

FIG. 5Aillustrates a view of a layout of the CMOS image sensor according to one embodiment of the invention.FIG. 5Billustrates a longitudinal sectional view of the CMOS image sensor ofFIG. 5A

InFIG. 5A, the CMOS image sensor may include a first conductive region410, a first conductive line420, a second conductive region425, a second conductive line430, a third conductive region435, and a third conductive line440which may be disposed to be sequentially adjacent to each other. A fourth conductive region445, a fifth conductive region455, a fourth conductive line450, a sixth conductive region453, a fifth conductive line460, and a seventh conductive region465may be are disposed to be sequentially adjacent to each other.

The third conductive region435and the fourth conductive line450may be electrically connected to each other. The first conductive region410may generate electrical signals. The fourth conductive region445may be electrically connected to a device voltage node, the fifth conductive region455may be electrically connected to a device voltage node, and the seventh conductive region465may be electrically connected to an output unit. The first conductive line420, the second conductive line430, the third conductive line440, and the fifth conductive line460may be respectively supplied with separate control signals.

FIG. 5Billustrates a longitudinal sectional view of the CMOS image sensor according to an embodiment of the invention.

InFIG. 5B, the CMOS image sensor may include the first conductive region410, the second conductive region425spaced apart from the first conductive region410, the third conductive region435spaced apart from the second conductive region425, and the fourth conductive region445spaced apart from the third conductive region435, which may be sequentially formed on the semiconductor substrate. The first conductive line420may be in a portion spaced apart between the first conductive region410and the second conductive region425, the second conductive line430may be in a portion spaced apart between the second conductive region425and the third conductive region435, and the third conductive line440that may be in a portion spaced apart between the third conductive region435and the fourth conductive region445, which may be formed on the semiconductor substrate. The fifth conductive region455, the sixth conductive region453spaced apart from the fifth conductive region455, and the seventh conductive region465spaced apart from the sixth conductive region453, may be sequentially formed on the semiconductor substrate. The fourth conductive line450in a portion spaced apart between the fifth conductive region455and the sixth conductive region453, and the fifth conductive line460that in a portion spaced apart between the sixth conductive region453and the seventh conductive region465, may be formed on the semiconductor substrate.

The third conductive region435and the fourth conductive line450may be electrically connected. The electrical connection may be by using, e.g., conductive polysilicon. The conductive polysilicon electrical connection may be advantageous in minimizing a leakage current. The first conductive region410may generate electrical signals.

The fourth conductive region445may be electrically connected to a first device voltage node, the fifth conductive region455may be electrically connected to a second device voltage node, and the seventh conductive region465may be electrically connected to an output unit.

Further, the first conductive line420, the second conductive line430, the third conductive line440, and the fifth conductive line460may be respectively supplied with separate control signals.

Although not shown, an insulating layer may be interposed between a surface of the semiconductor substrate and the conductive lines420,430,440,450, and460

In all of the conductive regions410,425,435,445,453,455, and465, which are adjacent to each other, and all of the conductive lines420,430,440,450, and460, which are adjacent to each other, adjacent boundary portions may partially overlap. Accordingly, in the drawing figures, the adjacent boundary portions thereof are shown to partially overlap each other. The overlap may not be restricted but may be adjusted in consideration of many variables. Therefore, a detailed explanation on the overlap is omitted.

The invention set forth inFIGS. 5A and 5Bmay be analogized to the circuit diagram set forth inFIG. 2A.

FIG. 6Aillustrates a view of a layout of the CMOS image sensor according to another embodiment of the invention, andFIG. 6Billustrates a longitudinal sectional view of the CMOS image sensor ofFIG. 6A.

InFIG. 6A, the CMOS image sensor may include an eighth conductive region575, a sixth conductive line570, a first conductive region510, a first conductive line520, a second conductive region525, a second conductive line530, a third conductive region535, a third conductive line540, and a fourth conductive region545, which may be disposed to be sequentially adjacent. A fifth conductive region555, a fourth conductive line550, a sixth conductive region553, a fifth conductive line560, and a seventh conductive region565may also be disposed to be sequentially adjacent.

The third conductive region535and the fourth conductive line550may be electrically connected. The first conductive region510may generate electrical signals. The fourth conductive region545may be electrically connected to a first device voltage node, the fifth conductive region555may be electrically connected to a second device voltage node, and the seventh conductive region565may be electrically connected to an output unit.

The first conductive line520, the second conductive line530, the third conductive line540, and the fifth conductive line560may be respectively supplied with separate control signals.

FIG. 6Billustrates a longitudinal sectional view of the CMOS image sensor ofFIG. 6A.

InFIG. 6B, the CMOS image sensor may include the eighth conductive region575, the first conductive region510, the second conductive region525(that may be formed to be spaced apart from the first conductive region510), the third conductive region535(that may be formed to be spaced apart from the second conductive region525), and the fourth conductive region545(that may be formed to be spaced apart from the third conductive region535), which may be sequentially formed on the semiconductor substrate. The sixth conductive line570may be formed in a portion spaced apart between the eighth conductive region575and the first conductive region510, the first conductive line520may be formed in a portion spaced apart between the first conductive region510and the second conductive region525, the second conductive line530may be formed in a portion spaced apart between the second conductive region525and the third conductive region535, and the third conductive line540may be formed in a portion spaced apart between the third conductive region535and the fourth conductive region545, which may be formed on the semiconductor substrate. The fifth conductive region555and the sixth conductive region553may be formed to be spaced apart from the fifth conductive region555, and the seventh conductive region565may be formed to be spaced apart from the sixth conductive region553, which may be sequentially formed on the semiconductor substrate. The fourth conductive line550may be formed in a portion spaced apart between the fifth conductive region555and the sixth conductive region553, and the fifth conductive line560may be formed in a portion spaced apart between the sixth conductive region553and the seventh conductive region565, which may be formed on the semiconductor substrate.

The third conductive region535and the fourth conductive line550may be electrically connected to each other. The first conductive region510may generate electrical signals. The fourth conductive region545may be electrically connected to a first device voltage node, the fifth conductive region555may be electrically connected to a second device voltage node, and the seventh conductive region565may be electrically connected to an output unit.

Further, the first conductive line520, the second conductive line530, the third conductive line540, the fifth conductive line560, and the sixth conductive line570may be respectively supplied with separate control signals.

In all the adjacent conductive regions510,525,535,545,553,555,565, and575, and all the adjacent conductive lines520,530,540,550,560, and570, adjacent boundary portions thereof may partially overlap. Accordingly, the adjacent boundary portions thereof are shown to partially overlap each other in the drawing figures. The overlap may not be specifically set but may be adjusted in consideration of one or of multiple variables.

FIG. 7Aillustrates a layout of the pixel array of a CMOS image sensor according to an embodiment of the invention, which is diagrammed inFIG. 3B.FIG. 7Billustrates a longitudinal sectional view of the pixel array of the CMOS image sensor.

FIG. 7Ashows a pixel array of the CMOS image sensor having a structural geometry that differs from the CMOS image sensor shown inFIG. 6A. InFIG. 7A, two pixel units A and B may share a third conductive region635, a third conductive line640, a fourth conductive region645, a sixth conductive line670, an eighth conductive region675, a fifth conductive region655, a fourth conductive line650, a sixth conductive region653, a fifth conductive line660, and a seventh conductive region665.

Furthermore, a first conductive line620aand a second conductive line630aof the first pixel unit A may overlap each other, i.e., not be the same size. Also, a first conductive line620band a second conductive line630bof the second pixel unit B may overlap each other, i.e., not be the same size.

FIG. 7Billustrates a longitudinal sectional view of the CMOS image sensor shown inFIG. 7A.

Here,FIGS. 5B and 6Bmay be further referred to in addition toFIG. 7B. InFIG. 7B, the first conductive line620aand the second conductive line630amay be formed to partially overlap each other.

The first conductive line620aand the second conductive line630amay overlap each to reduce the area occupied by the pixels. Further, when the two conductive lines620aand630aoverlap each other, an opposite-polarity voltage may be induced due to the mutual inductance effects. As a result, when one of the conductive lines620aand630aturns on, the other one may be in a turned-off state that may be more stable. Specifically, when an electrical signal is applied to the first conductive line620a, and the first conductive line620amay have positive (+) polarity, the second conductive line630amay have negative (−) polarity. As a result, it may be possible to stably prevent a leakage current from generating between the second conductive region625aand the third conductive region635. In contrast, when an electrical signal is applied to the second conductive line630a, and the second conductive line630amay have positive (+) polarity, the first conductive line620amay have negative (−) polarity. As a result, it may be possible to stably prevent a leakage current from generating between the first conductive region610aand the second conductive region625a. The same observations apply to the first conductive line620band a second conductive line630bof the second pixel unit B.

FIGS. 8A to 8Dillustrate layouts of the CMOS image sensors according to various embodiments of the invention. Specifically, in the layouts illustrated inFIGS. 8A to 8D, various conductive lines720,740, and770and various conductive regions735,745, and775may be shared.

FIG. 8Aillustrates one possible configuration of the circuit diagrams and layouts of the CMOS image sensors shown inFIGS. 3A,4A,5A, and6A, where multiple pixel units may share the third conductive line740. For example, a first pixel unit may include a first conductive region710a, a first conductive line720a, a second conductive region725a, a second conductive line730a, a third conductive region750a, a third conductive line740aof conductive line740, and a fourth conductive region745(which may or may not be shared). More specifically, the third conductive line740may be a gate line of a reset unit or a reset transistor. A second pixel region analogously may have a first conductive region710, etc. However, a fourth conductive region (analogous to fourth conductive region745) may be optional in the intermediate pixels typified by the second pixel. Finally, an nth pixel unit may include a first conductive region710x, a first, conductive line720x, a second conductive region725x, a second conductive line730x, a third conductive region735, conductive line740, and a fourth conductive region745.

The circuit diagrams and layouts of the CMOS image sensors shown inFIGS. 3A,4A,5A, and6A may be referred to in order to help elucidate the CMOS image sensor configuration illustrated inFIG. 8B. InFIG. 8B, multiple pixel units share the first conductive line720and the third conductive line740. More specifically, the first conductive line720may be a gate line of a signal transmission unit or a transistor for signal transmission, and the third conductive line740may be a gate line of a reset unit or a reset transistor. In this configuration, a fourth conductive region may be present in the intervening pixels between the first and nth pixels.

InFIG. 8C, the circuit diagrams and layouts of the CMOS image sensors shown inFIGS. 3B,4B,6B,7A, and8A may be referred to in order to better understand the technology. InFIG. 8C, multiple pixel units may share the eighth conductive region775, the sixth conductive line770, and the third conductive line740. More specifically, the eighth conductive region775may be a device voltage node, the sixth conductive line770may be a discharge unit for discharging electrical signals or a gate line of an overflow transistor, and the third conductive line740may be a gate line of a reset unit or a reset transistor. The two illustrated pixel units include first conductive regions710a,710b, a first conductive lines720a,720b, second conductive lines730a,730b, second conductive regions735a,735band fourth conductive regions745a,745b.

InFIG. 8D, the circuit diagrams and layouts of the CMOS image sensors shown inFIGS. 3B,4B,6B,7A, and8A may also be referred to in order to help understand the technology. InFIG. 8D, multiple pixel units share the eighth conductive region775, the sixth conductive line770, the first conductive line720, and the third conductive line740. More specifically, the eighth conductive region775may be a device voltage node, the sixth conductive line770may be a discharge unit for discharging electrical signals or a gate line of an overflow transistor, the first conductive line720may be a gate line of a signal transmission unit or a transistor for signal transmission, and the third conductive line740may be a gate line of a reset unit or a reset transistor.

Although not shown, in the layouts shown inFIGS. 8A to 8D, two pixel units may be disposed as a pair, as shown inFIG. 7A. For example, in the case when “x” is 4, two sets of paired pixel units may be disposed, or in the case when “x” is 8, four sets of paired pixel units may be disposed.

As described above, in the semiconductor devices and the CMOS image sensors according to the embodiments of the invention, it may be possible to perform a precise signal processing that may be free from distortion because electrical signals may be temporarily stored.