Vertical junction based silicon modulator

In one example embodiment, an optical circuit for optical modulation of light may include an input waveguide including a first thickness, an optical modulator including a second thickness, and a tapered transition that optically couples the optical modulator and the input waveguide. The second thickness may be smaller than the first thickness. The tapered transition may adiabatically transform the optical mode of the input waveguide to the optical modulator.

BACKGROUND

The present disclosure generally relates to high efficiency modulators for silicon photonics devices. In particular, some of the embodiments described herein include high efficiency modulators for silicon on insulator (SOI) platforms.

Silicon photonics involve the use of silicon as an optical medium for optical or optoelectronic devices. In some photonics devices, the silicon may be positioned on top of a layer of silicon, such configurations are known as silicon on insulator (SOI). The silicon may be patterned into photonic components or micro-photonic components. Silicon photonic devices may be made using existing semiconductor fabrication techniques, and because silicon is already used as the substrate for some integrated circuits, it may be possible to create hybrid devices in which the optical and electronic components are integrated onto a single microchip.

Silicon photonic devices may be implemented in optical networks used to communicate optical signals for transmitting information among various nodes of a telecommunications network. To transmit data in an optical network, the data may be converted from an electrical signal to an optical signal using an optoelectronic device. Optical networks are one example of an environment where the silicon photonic devices described herein may be implemented. However, the concepts described may also be implemented in other circumstances. For example, silicon photonic devices may be implemented in computer processing, sensors, optical routing, signal processing or other suitable applications. The embodiments disclosed herein are not limited to any specific environment unless indicated by context.

The claimed subject matter is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. This background is only provided to illustrate examples of where the present disclosure may be utilized.

SUMMARY

The present disclosure generally relates to high efficiency modulators for silicon photonics devices. In particular, some of the embodiments described herein include high efficiency modulators for silicon on insulator (SOI) platforms.

In some example embodiments, an optical circuit for optical modulation of light may include an input waveguide including a first thickness, an optical modulator including a second thickness, and a tapered transition that optically couples the optical modulator and the input waveguide. The second thickness may be smaller than the first thickness. The tapered transition may adiabatically transform the optical mode of the input waveguide to the optical modulator.

The tapered transition may include a first waveguide portion including the first thickness and a second waveguide portion including the second thickness. The tapered transition may include a first tapering portion that may include a first length; and a second tapering portion that may include a second length. The first length and the second length may be sufficiently large enough to adiabatically transform the optical mode of the optical signals traveling through the first tapering portion and the second tapering portion.

The tapered transition may include a first waveguide portion that may include a first taper, a second waveguide portion that may include a second taper, and a third waveguide portion that may include a third taper. The first waveguide portion may have a first thickness, the second waveguide portion may have a second thickness, and the third waveguide portion may have a third thickness. The first thickness may be larger than the second thickness, and the second thickness may be larger than the third thickness.

The first waveguide portion may be formed by a first etch, the second waveguide portion may be formed by a second etch deeper than the first etch, and the third waveguide portion may be formed by a third etch deeper than the second etch. The first waveguide portion may be a double rib waveguide and the third waveguide portion may be a rib waveguide.

The tapered transition may include a first tapering portion that includes a first length, a second tapering portion that includes a second length, and a third tapering portion that includes a third length. The first length, the second length, and the third length may be sufficiently large enough to adiabatically transform the optical mode of the optical signals traveling through the first tapering portion and the second tapering portion.

The optical circuit further may include a coupling portion between the second tapering portion and the third tapering portion to allow the mode of optical signals to stabilize before reaching the third tapering portion.

The tapered transition may include a first waveguide portion that includes a first thickness, a second waveguide portion that includes a second thickness, and a third waveguide portion that includes a third thickness. The first thickness may be larger than the second thickness, and the second thickness may be larger than the third thickness. The first waveguide portion may be a rib waveguide, the second taper may be a strip waveguide, and the third waveguide portion may be a rib waveguide.

The optical circuit further may include a first taper decreasing the width of the first waveguide portion, a second taper decreasing the width of the second waveguide portion and the third waveguide portion, a third taper decreasing the width of the second waveguide, and a fourth taper increasing the width of the third waveguide portion.

The optical modulator may be a Mach-Zehder modulator. The first thickness may be between 300 nm and 310 nm and the second thickness may be between 160 nm and 220 nm. The optical modulator may include an n-doped region and a p-doped region. The n-doped region and the p-doped region may be positioned vertically with respect to one another in a waveguide to form a vertical PN junction.

The optical circuit may include a silicon on insulator photonic device. The second thickness of the optical modulator may be smaller than the first thickness of the input waveguide to improve optical confinement of the optical modulator. The tapered transition may confine the optical mode from the first thickness of the input waveguide to the second thickness of the optical modulator. The optical mode may be confined with substantially no transition loss through the tapered transition.

The optical circuit further may include cladding surrounding at least a portion of the tapered transition. In some configurations, the optical modulator includes an input and an output including the second thickness. The optical circuit may further include an output waveguide, and the output waveguide may include the first thickness. The output waveguide may be optically coupled to the optical modulator.

This Summary introduces a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary does not identify key features or essential characteristics of the claimed subject matter, and should not be used as an aid in determining the scope of the claimed subject matter.

DETAILED DESCRIPTION

The present disclosure generally relates to high efficiency modulators for silicon photonics devices. In particular, some of the embodiments described herein include high efficiency modulators for silicon on insulator (SOI) platforms.

Silicon photonics involve the use of silicon as an optical medium for optical or optoelectronic devices. In some photonics devices, the silicon may be positioned on top of a layer of silicon, such configurations are known as silicon on insulator (SOI). The silicon may be patterned into photonic components or micro-photonic components. Silicon photonic devices may be made using existing semiconductor fabrication techniques, and because silicon is already used as the substrate for some integrated circuits, it may be possible to create hybrid devices in which the optical and electronic components are integrated onto a single microchip. A photonic integrated circuit or integrated optical circuit is a device that integrates multiple (at least two) photonic functions.

Silicon photonic devices may be implemented in optical networks used to communicate optical signals for transmitting information among various nodes of a telecommunications network. To transmit data in an optical network, the data may be converted from an electrical signal to an optical signal using an optoelectronic device such as an electro-optic modulator or a directly-modulated laser. An electro-optic modulator may vary the intensity and/or the phase of the optical carrier. In silicon photonics, modulation may be achieved by varying the density of free charge carriers. Modulators may include forward-biased PIN diodes, which generally generate large phase-shifts but generally have lower speeds or reverse-biased PN junctions. Non-resonant modulators, such as Mach-Zehnder interferometers, may have dimensions in the millimeter range and may be used in telecom or datacom applications. Resonant devices, such as ring-resonators, may have dimensions of few tens of micrometers, occupying much smaller areas. To receive data in an optical network, optical signals may be converted to electrical signals using a detector such as a photodiode. Some detectors may implement a PN junction for carrier extraction. In other configurations, detectors may implement metal-semiconductor junctions integrated into silicon waveguides.

Generally, different SOI platforms are defined based on the thickness of the silicon used in the SOI. For example, multi-micron SOI's generally have a thickness of around 1 μm or greater, with a thickness of 3 μm being a common configuration. In another example, submicron SOI's may have a thickness of 160 nm, 220 nm, 250 nm, 300 nm, 306 nm, etc. The thickness of the silicon determines various characteristics of the SOI. For example, thicker SOI's may have relatively good mode confinement because there is less scattering loss, but because the mode itself is large a relatively tight wavelength band may need to be implemented and the footprint of the SOI may be relatively large. Relatively thicker SOI's are typically used for passive components to reduce optical loss and fabrication tolerances, and relatively thinner SOI's are used for active components to improve optical confinement and modulation efficiency. For example, relatively thinner SOI's (e.g., submicron SOI's) may be used for active components such as vertical junction-based modulators.

As used herein, a passive device or component may refer to features that only have photonics, with no electronic components, and an active device or component may refer to features that have both optical and electronic aspects. For example, passive components may include waveguides, directional couplers, splitters, rotators, polarizers, multiplexers, demultiplexers, and others. In another example, active components may include optical transmitters, optical detectors, modulators, lasers, photodiodes, and others.

Reference will be made to the drawings and specific language will be used to describe various aspects of the disclosure. Using the drawings and description in this manner should not be construed as limiting its scope. Additional aspects may be apparent in light of the disclosure, including the claims, or may be learned by practice.

As mentioned, SOI platforms may be used for active components, such as modulators. SOI-based modulators may include lateral junction configurations, where the PN junction is formed laterally in the SOI, and vertical junction configurations, where the PN junction is formed vertically in the SOI.

FIGS. 1A and 1Bare example embodiments of SOI modulators. In particular,FIG. 1Ais a schematic cross-section of a lateral junction SOI modulator100, andFIG. 1Bis a schematic cross-section of a vertical junction SOI modulator140.

As shown inFIG. 1A, the SOI modulator100may include a silicon waveguide with a highly n-doped region102, a n-doped region104, a p-doped region106, a highly p-doped region108, and a lateral PN junction110. The highly n-doped102and highly p-doped region108are used to reduce resistance and needed to be placed far enough from the optical mode to avoid high optical absorption loss. The n-doped104and p-doped region106are used to form the PN junction110. The doping densities in regions104,106will affect the modulation efficiency and may be optimized.

In some circumstances, the doping in the highly n-doped region102may be greater than the doping in the n-doped region104. For example, the doping of the highly n-doped region102may be approximately 1018-1019and the doping of the n-doped region104may be approximately 1017. Similarly, the doping in the highly p-doped region108may be greater than the doping in the p-doped region106. For example, the doping of the highly p-doped region108may be approximately 1018-1019and the doping of the p-doped region106may be approximately 1017.

The SOI modulator100may include dimensions H, S, D, W, and G. H is the height of the waveguide. S is the height of slab region. D is the distance between the highly n-doped region102and the PN junction110. W is the width of the PN junction110. G is the width of slab region. X3is width of the depletion region of the PN junction. The n-doped region104may include a doping level or doping density Nd, and the p-doped region106may include a doping level or doping density NA.

The efficiency of the SOI modulator100may be represented by the Equation 1:

In the above equation, Δn denotes refractive index difference before and after applying modulation voltage denoted as V, neffdenotes optical mode effective index, N denotes free carrier density, H denotes the height of the waveguide, L denotes length of the waveguide, W denotes width of the waveguide, Δwddenotes the change of the depletion region width, V denotes modulation voltage, and ØBdenotes DC bias.

As indicated by Equation 1, for the SOI modulator100with a lateral configuration, efficiency depends on the waveguide width W as well as doping levels Ndand Na. However, for waveguides with the same doping levels, a narrower waveguide will have a higher efficiency.

As shown inFIG. 1B, the vertical junction SOI modulator140includes aspects similar to the lateral junction SOI modulator100, and similar features are indicated with the same numbering asFIG. 1A. However, the vertical junction SOI modulator140includes a vertical PN junction150rather than the lateral PN junction110.

The efficiency of the SOI modulator140may be represented by the Equation 2:

In the above equation, Δn denotes refractive index difference before and after applying modulation voltage denoted as V, neffdenotes optical mode effective index, N denotes free carrier density, H denotes the height of the waveguide, L denotes length of the waveguide, W denotes width of the waveguide, Δwddenotes the change of the depletion region width, V denotes modulation voltage, and ØBdenotes DC bias.

As indicated by Equation 2, for the SOI modulator140with a vertical configuration, if the mode of the optical signals are very well defined inside the waveguide, then we will have an approximation that efficiency is related to the inverse of the height H (e.g., the thickness of the SOI waveguide). Accordingly, a thinner SOI waveguide may results in better SOI modulator performance.

As indicated by Equations 1 and 2, the operation and/or the efficiency of the SOI modulators100,140may depend on the dimensions or geometric design of the PN junctions110,150, waveguide doping levels, and/or optical mode overlap with the depletion region. In some circumstances, if the optical mode is well confined inside the silicon waveguide, to the first-order approximation, the efficiency of the lateral junction SOI modulator100may be proportional to the waveguide width W, which may be limited by the propagation loss. In contrast, for the vertical junction SOI modulator140, if the optical mode is well confined inside the silicon waveguide, to the first-order approximation, the efficiency of the vertical junction SOI modulator140may be proportional to the SOI thickness H, which may depend on the SOI platform implemented (e.g., the thickness of the SOI platform selected).

In some circumstances, the efficiency of vertical junction SOI modulators, such as the vertical junction SOI modulator140, may be greater than that of lateral junction SOI modulator designs, such as the lateral junction SOI modulator100, because the width W of the waveguide may be increased to increase the mode overlap with the depletion region. However, the modulation efficiency of the vertical junction SOI modulator140may be limited by the vertical confinement factor of the optical mode, which may depend on the dimensions of the vertical junction SOI modulator140, and in particular on the width of the waveguide which in turn depends on the SOI platform selected.

Typical submicron SOI platforms that are implemented for SiP may include 300 nm and 220 nm. In general, thicker SOI platforms (e.g., 300 nm and larger) have a well-confined optical mode, and hence lower propagation loss. In addition, performance of passive devices is less affected by processing variations for relatively thicker SOI platforms. However, thinner SOI platforms (e.g., 220 nm and smaller) may result in higher vertical confinement which may further increase the modulation efficiency of vertical junction based high speed modulators, such as the vertical junction SOI modulator140. Nevertheless, some thinner SOI platforms may have higher propagation loss, and may be more susceptible to processing variations and errors.

As mentioned, thinner SOI platforms may be more susceptible to processing variations than thicker SOI platforms. To form certain components on an SOI platform, a substrate layer may be implemented so other layers may be selectively grown on top, for example, a layer of Germanium. A thicker substrate layer may be more suitable for selectively growing such layers. In particular, thicker substrate layers may result in better Germanium growth conditions. Accordingly, SOI platforms may implement thicker substrate layers to improve growing conditions, however, this may also increase the thickness of the SOI platform itself. Furthermore, as explained above, thicker SOI platforms may result in decreased modulation efficiency.

Accordingly, the disclosed embodiments include SOI devices that include two different SOI platforms (e.g., two different thicknesses) within a single SOI substrate. Such configurations may include a transition between a larger (e.g. thicker) SOI platform and a smaller (e.g., thinner) SOI platform. In such configurations, the high speed modulator may be positioned on the thinner SOI platform or layer to achieve higher modulation efficiency and reduced insertion loss, while the remaining portion of the SOI device may be included on the thicker SOI platform, so that the efficiency and performance of such features are not decreased or adversely affected. Some configurations may include vertical PN junctions and/or vertical junction SOI modulators with increased vertical confinement of the optical mode when compared to other devices with the same or similar SOI platforms. The disclosed embodiments may include different transition designs which may be suitable for different manufacturing process constraints.

Additionally or alternatively, the disclosed embodiments include optimized PN junction offset to maximize the mode overlap within depletion regions, and to minimize the doping loss. Further, the disclosed embodiments may result in enhanced phase shift efficiency and reduced doping loss. In addition, the disclosed embodiments may be implemented for high speed modulation with lumped Mach-Zehnder interferometer or modulator configurations.

In one example embodiment, an SOI device may include two different SOI platforms in a single 306 nm SOI substrate. In particular, the SOI device may include a 306 nm platform and a 160 nm platform with a transition in between. A high speed modulator may be included on the thinner 160 nm SOI layer or platform to achieve higher efficiency and lower insertion loss, while the rest of the SOI device may be included on the 306 nm SOI layer or platform, so that the efficiency and performance of such features is not decreased or adversely affected.

FIG. 2is a schematic cross-section of an example of a vertical junction SOI modulator200including depletion regions. As shown inFIG. 2, the SOI modulator200may include a silicon waveguide with an n-doped region202and a p-doped region208, and a vertical PN junction210. The n-doped region202may include a doping level or doping density Nd, and the p-doped region208may include a doping level or doping density NA. Before applying a modulation voltage V, the PN junction210forms an n-side depletion region214and p-side depletion region216. After modulation is turned on (e.g., a modulation voltage V is applied), the n-side depletion region214and the p-side depletion region216increases. In particular, the n-side depletion region increases to an n-side depletion region212and p-side depletion region increases to a p-side depletion region218.

The SOI modulator200may include a vertical center220of the optical mode in the waveguide and a lateral center222of the waveguide. The SOI modulator200may include dimensions Yc, Xj, Yj, and Wp. Ycis the distance from the edge of the waveguide to the vertical center220of the optical mode in the waveguide. Xjand Yjare the positions of the vertical PN junction210in x and y directions with respect to the lateral center222of the waveguide, and the vertical center220of the optical mode. Wpis the change of the depletion width for the voltage swing applied to the SOI modulator200.

In some circumstances, the SOI modulator200may operate on the carrier depletion effect. In such circumstances, optical signals travelling through the SOI modulator200may be modulated by “sweep modulation,” where the modulation is swept on and off the carrier, which changes the index of the waveguide so the optical signals travel through different indices. For such configurations, the carrier depletion effect may be optimized to increase the efficiency of the SOI modulator200as shown inFIG. 2. In particular, the geometry and position of the vertical PN junction210may be optimized to increase the carrier depletion effect.

Before a voltage is applied across the SOI modulator200, the n-side depletion region212and p-side depletion region218includes free carriers. When a voltage is applied across the SOI modulator200, the n-side depletion region212and p-side depletion region218becomes depleted, which causes the free carrier density to change in the newly depleted region which will cause the effective index to change. This effect may be used to modulate optical signals that travel through the SOI modulator200by using it in the Mach-Zehnder interferometer or modulator. In some configurations, voltage may be applied to the SOI modulator200using contacts positioned on opposite sides of the SOI modulator200. In some circumstances, a voltage swing between 0 and 1.5V may be applied to the vertical PN junction210of the SOI modulator200.

If the vertical PN junction210is relatively linear junction at the beginning of its formation, there may be an initial depletion area (e.g., the n-side depletion region212and p-side depletion region218) even though there is no applied voltage. Once a reverse bias or voltage is applied the depletion region may become wider. Since doping levels for such modulators are usually very low, typically in the 1017range, p-doping in this doping level is much more efficient than n-doping. For example, in some circumstances p-doping may be an order of magnitude more efficient than n-doping. Accordingly, it may be desirable to position the vertical PN junction210such that p-side depletion region218has a largest overlap with optical mode to optimize efficiency. In addition, p-doping has relatively lower depletion loss than n-doping. Accordingly, the vertical PN junction210may be positioned offset from the lateral center222of the SOI modulator200so the optical mode overlap in the n-doped region202is minimized. Additionally or alternatively, the vertical PN junction210may be positioned offset from the lateral center222of the SOI modulator200to align the p-side depletion region218with the vertical center220or the vertical mode center.

In some configurations, the vertical PN junction210may be dominated by p-doping. For example, in some aspects the majority of the vertical PN junction210may be p-doped. In another example, between 60% and 95% of the vertical PN junction210may be p-doped, and/or the remainder of the vertical PN junction210may be n-doped. In some configurations, the lateral position of the vertical PN junction210may be limited or determined by implantation process limits, such as implantation resolution.

FIGS. 3A-3Bare contour graphs of optical mode confinement factors in the depletion region for waveguides of different dimensions, such as different waveguide widths and different depletion widths.FIG. 3Arepresents confinement change in the depletion region for a 306 nm SOI platform (e.g., thickness) andFIG. 3Brepresents confinement change in the depletion region for a 160 nm SOI platform (e.g., thickness). InFIGS. 3A-3B, the horizontal axis represents the width of the waveguide in nanometers (nm) and the vertical axis represents the depletion width in nanometers (nm).FIGS. 3A-3Binclude lines representing various confinement factors of the optical mode in the depletion region.

FIG. 3Aincludes a line250, denoting the depletion wave change for a 500 nm wide single mode waveguide on a 306 nm SOI platform andFIG. 3Bincludes a line252, denoting the depletion wave change for a 700 nm wide single mode waveguide on a 160 nm SOI platform. Generally, the waveguide width for different SOI platforms is balanced between overall mode confinement (and thus waveguide propagation loss) and junction capacitance. The 160 nm SOI platform with a 700 nm waveguide width exhibits similar propagation loss as the 306 nm SOI platform with a 500 nm waveguide width. However, as will be explained in further detail below, the optical confinement in the depletion region (e.g., how much of the optical field is confined in the depletion region) is improved in the thinner, 160 nm SOI platform.

FIG. 4is graph illustrating optical confinement versus the depletion width for the configurations ofFIGS. 3A-3B. InFIG. 4, the horizontal axis represents the depletion width in nanometers (nm) and the vertical axis represents optical confinement in the depletion region, expressed as a percentage.FIG. 4includes a line260indicating the optical confinement versus depletion width for the 500 nm wide single mode waveguide on the 306 nm SOI platform, and a line262indicating the optical confinement versus depletion width for the 700 nm wide single mode waveguide on the 160 nm SOI platform. As shown, there is about a 40% improvement in optical confinement of the thinner 160 nm SOI platform versus the thicker 306 nm SOI platform. Accordingly, the thinner SOI platform exhibits improved modulation efficiency than the thicker SOI platform. While the thinner SOI platform has less overall optical confinement in the waveguide (e.g., overall F of 74.18% versus 83.8%), it has a much larger confinement in the depletion region and a larger slope efficiency (e.g., slope of 0.52%/nm versus 0.37%/nm), thereby leading to an improvement in modulation efficiency.

Although the thinner SOI platform exhibits improved modulation efficiency, thinner SOI platforms may be more susceptible to processing variations than thicker SOI platforms. Accordingly, the disclosed embodiments include SOI devices or waveguides that include two different thicknesses within a single SOI substrate (e.g., two different waveguide thicknesses in one SOI platform). In such configurations, the high speed modulator may be positioned on the thinner SOI thickness to achieve higher modulation efficiency and reduced insertion loss, while the remaining devices may be included on the thicker SOI thickness, so that the performance and tolerance for the processing variations are not decreased or adversely affected. Some configurations may include vertical PN junctions and/or vertical junction SOI modulators with increased vertical confinement of the optical mode when compared to other devices with the same or similar SOI platforms.

The disclosed embodiments also include a transition between the thinner SOI platform and the thicker SOI platform, or between a thinner waveguide and a thicker waveguide, to permit the optical signals to travel in between the two SOI thicknesses.FIGS. 5 and 7illustrate example embodiments of SOI devices that include two different thicknesses within a single SOI substrate. Further,FIGS. 5 and 7illustrate example configurations of transitions between larger (e.g. thicker) and a smaller (e.g., thinner) waveguides.

FIGS. 5A-5Care views of an example embodiment of an SOI device300. In particular,FIG. 5Ais a perspective view of the SOI device300,FIG. 5Bis a top view of the SOI device300, andFIG. 5Cis a side section of the SOI device300.

As shown, the SOI device300includes a thicker waveguide portion302and a thinner waveguide portion308with a transition portion310positioned in between. In such configurations, the SOI device300may transition from a relatively thicker waveguide to a relatively thinner waveguide. In the illustrated configuration, the transition portion310includes a304and a second tapering portion306. The first tapering portion304may include a length L1and the second tapering portion306may include a length L2. The SOI device300may include cladding 326 (e.g., a silicon dioxide cladding) surrounding a silicon waveguide.

The SOI device300may transition between the thicker waveguide portion302and the thinner waveguide portion308. For example, in the illustrated configuration the SOI device300transitions between a first waveguide thickness350and a second waveguide thickness352(seeFIG. 5C). In some configurations, the first waveguide thickness350may be approximately 306 nm at the thicker waveguide portion302, and the second waveguide thickness352may be approximately 160 nm at the thinner waveguide portion308, although other configurations may be implemented.

The SOI device300may include a first waveguide portion320, a second waveguide portion322, and a third waveguide portion324. The first waveguide portion320may be formed by a first etch354, the second waveguide portion322may be formed by a second etch356, and the third waveguide portion324may be formed by a third etch358. The first etch354may be a relatively shallow etch, the second etch356may be deeper than the first etch354, and the third etch358may be deeper than the first etch354and the second etch356.

In some circumstances, the first etch354may be a shallow etch, the second etch356may be a deep etch, and the third etch358may be a full etch (e.g., extending fully to the cladding 326. In one example, the first etch354(e.g., shallow etch) may be 150 nm, the second etch356(e.g., deep etch) may be 250 nm and the third etch358(e.g., full etch) may be 306 nm. In such configurations, the first waveguide portion320may have a thickness of approximately 306 nm (depth from the top of the first waveguide portion320to the cladding 326), the second waveguide portion322may have a thickness of approximately 160 nm, and the third waveguide portion324may have a thickness of approximately 50 nm. However, other configurations may be implemented.

In some configurations, the SOI device300may include rib waveguides and strip waveguides. A strip waveguide may have a core with fully etched slabs on both sides of the core, a rib waveguide may have a core with relatively thinner unetched slabs on both sides of the core, a double rib waveguide may have a core with two unetched slabs on both sides of the core. In such configurations, the thicker waveguide portion302may be a double rib waveguide, with two etch slabs (e.g., the second waveguide portion322and the third waveguide portion324) surrounding a core (e.g., the first waveguide portion320). The thinner waveguide portion308may be a single rib waveguide with a slab (e.g., the third waveguide portion324) surrounding a core (e.g., the second waveguide portion322). As shown, the first waveguide portion320does not extend to the thinner waveguide portion308because of the transition portion310, which transitions the SOI device300from a thicker waveguide (e.g., 306 nm) to a thinner waveguide (160 nm).

As shown inFIGS. 5A and 5B, the thicker waveguide portion302includes the first waveguide portion320, the second waveguide portion322, and the third waveguide portion324. At the first tapering portion304, the first waveguide portion320includes a first taper340while the second waveguide portion322and the third waveguide portion324remain constant. In some configurations, the first taper340may taper between a starting width of 400 nm and a decreased or minimum width of 80 nm. The starting width may depend on the input waveguide design. The minimum width may depend on process limitations, such as process resolution.

As shown, the second tapering portion306includes the second waveguide portion322and the third waveguide portion324, not the first waveguide portion320. At the second tapering portion306, the second waveguide portion322includes a second taper342and the third waveguide portion324includes a third taper344. The second taper342may taper between a starting width of 2 μm and a decreased or minimum width of 400 nm. The starting width may depend on design. The minimum width may depend on output rib waveguide design. The third taper344may taper between a starting width of 4 μm and a decreased or minimum width of 400 nm.

In some configurations, the first taper340, the second taper342, and the third taper344may be adiabatic tapers. In such configurations, the mode may be transferred through the waveguide at each of the tapers340,342,344without transition losses. Additionally or alternatively, the transition at the tapers340,342,344may be sufficiently gradual and/or smooth that transition losses at the tapers340,342,344are minimized or eliminated.

In the first tapering portion304, the top waveguide core width (e.g., first waveguide portion320) is tapered down and the optical mode will be pushed down from the 306 nm thick waveguide to 160 nm thick waveguide at the end of the first tapering portion304. The second etch width is large to reduce the mode transition loss and the transition loss between the first tapering portion304and the second tapering portion306. In the second tapering portion306, the rib waveguide core (e.g. the second waveguide portion322) and the slab (e.g., the third waveguide portion324) are both tapered to the standard dimensions of the thinner waveguide portion308.

FIG. 6A-6Bare graphs illustrating transition losses for tapers of different lengths.

FIG. 6Ais a graph illustrating coupling efficiency versus taper length for the second tapering portion306ofFIG. 5. InFIG. 6A, the horizontal axis represents taper length in microns and the vertical axis represents transmission.

FIG. 6Bis a graph illustrating coupling efficiency versus taper length for the first tapering portion304ofFIG. 5. InFIG. 6B, the horizontal axis represents taper length in microns and the vertical axis represents transmission.

As shown inFIGS. 6A-6B, the transition loss through the first tapering portion304and the second tapering portion306is relatively small. Transition loss may depend on the configuration of the first tapering portion304and the second tapering portion306. For example, transition loss may depend on the length of the taper and dimensions of the tip of the taper (e.g., width). As shown, for the configuration illustrated inFIG. 5, the transition loss may be approximately 0.04 decibels (dB) for the first tapering portion304and the second tapering portion306with a total length of less than 200 microns (e.g., transmission of greater than 99%). Accordingly, the configuration of the SOI device300as shown inFIG. 5may transition between the thicker waveguide portion302(e.g., 306 nm) and the thinner waveguide portion308(e.g., 160 nm) with substantially no transition losses or without significant transition losses. The length of the tapers L1and L2may be selected to be sufficiently long such that the tapers340and342are adiabatic tapers. In particular, the length of the tapers L1and L2may be selected to adiabatically transform the optical mode of the optical signals traveling through the waveguides.

In some circumstances, production techniques may permit different etch depths, such as shallow, deep and full etches, to be formed in a single waveguide. However, in other circumstances, this many different etch depths may not feasible for waveguide formation, based on available production techniques. Accordingly, the disclosed embodiments include configurations that have fewer etches, for example, as shown inFIGS. 7A-7C.

FIGS. 7A-7Care views another example embodiment of an SOI device400. In particular,FIG. 7Ais a perspective view of the SOI device300,FIG. 7Bis a top view of the SOI device400, andFIG. 7Cis a side section of the SOI device400.

As shown, the SOI device400includes a thicker waveguide portion402and a thinner waveguide portion408with a transition portion410positioned in between. In the illustrated configuration, the transition portion410includes a first tapering portion404, a second tapering portion406, and a third tapering portion407. The transition portion410also includes coupling portion405with a constant dimension (e.g., width) between the second tapering portion406and the third tapering portion407. The first tapering portion404may include a length L1, the second tapering portion406may include a length L2, and the third tapering portion407may include a length L3. The SOI device300may include cladding 426 (e.g., silicon dioxide cladding) surrounding a silicon waveguide.

The SOI device400may transition between the thicker waveguide portion402and the thinner waveguide portion408. For example, in the illustrated configuration the SOI device400transitions between a first waveguide thickness450and a second waveguide thickness452(seeFIG. 7C). In some configurations, the first waveguide thickness450may be approximately 306 nm at the thicker waveguide portion402, and the second waveguide thickness452may be approximately 160 nm at the thinner waveguide portion408, although other configurations may be implemented.

The SOI device400may include a first waveguide portion420, a second waveguide portion422, and a third waveguide portion424. The first waveguide portion420may be formed by a first etch454, the second waveguide portion422may be formed by a second etch456, and the third waveguide portion424may be formed by a third etch458. The first etch454may be a relatively shallow etch, the second etch456may be deeper than the first etch454, and the third etch458may be deeper than the first etch454and the second etch456.

In some circumstances, the first etch454may be a shallow etch, the second etch456may be a deep etch, and the third etch458may be a full etch (e.g., extending fully to the cladding 426. In one example, the first etch454(e.g., shallow etch) may be 150 nm, the second etch456(e.g., deep etch) may be 250 nm and the third etch458(e.g., full etch) may be 306 nm. In such configurations, the first waveguide portion420may have a thickness of approximately 306 nm (depth from the top of the first waveguide portion420to the cladding 426), the second waveguide portion422may have a thickness of approximately 160 nm, and the third waveguide portion424may have a thickness of approximately 50 nm. However, other configurations may be implemented.

As explained above, some SOI devices may include rib waveguides and strip waveguides. A strip waveguide may have a core with fully etched slabs on both sides of the core, a rib waveguide may have a core with relatively thinner unetched slabs on both sides of the core, a double rib waveguide may have a core with two unetched slabs on both sides of the core. However, some manufacturing processes may not permit double rib waveguide configurations because of process restrictions. Accordingly, the SOI device400ofFIGS. 7A-7Cdoes not include any double rib waveguides, in contrast to the configuration of the SOI device300ofFIGS. 5A-5C, which does include a double rib waveguide.

In the illustrated configuration of the SOI device400, the thicker waveguide portion402includes a single rib waveguide, with one slab (e.g., the second waveguide portion422) surrounding a core (e.g., the first waveguide portion420). The thinner waveguide portion408includes a second single rib waveguide with a slab (e.g., the third waveguide portion424) surrounding a core (e.g., the second waveguide portion422). As shown, the first waveguide portion420does not extend to the thinner waveguide portion308because of the transition portion410, which transitions the SOI device400from a thicker waveguide (e.g., 306 nm) to a thinner waveguide (160 nm).

As shown inFIGS. 7A and 7B, the thicker waveguide portion402includes the first waveguide portion420, the second waveguide portion422, and the third waveguide portion424. At the first tapering portion404, the first waveguide portion420includes a first taper440while the second waveguide portion422and the third waveguide portion424remain constant. In some configurations, the first taper440may taper between a starting width of 400 nm and a decreased or minimum width of 80 nm. The starting width may depend on dimensions of the standard thick rib waveguide. The minimum width may depend on mode transition and may be determined by minimal tip size of the process.

As shown, the second tapering portion406includes only the second waveguide portion422, not the first waveguide portion420. At the second tapering portion406, the second waveguide portion422and the third waveguide portion424includes a second taper442. The second taper442may taper between a starting width of 2000 nm and a decreased or minimum width of 1000 nm. The starting width may depend on standard dimensions of thick rib waveguide.

At the coupling portion405, the second waveguide portion422and the third waveguide portion424include a constant dimension (e.g. width) between the second tapering portion406and the third tapering portion407.

As shown, the third tapering portion407includes the second waveguide portion422and the third waveguide portion424. At the third tapering portion407, the second waveguide portion422includes a third taper444. The third taper444may taper between a starting width of 1000 nm and a decreased or minimum width of 700 nm. The starting width may depend on optical performance. The minimum width may depend on standard dimensions of the thinner waveguide portion408(e.g., rib waveguide).

In addition, at the third tapering portion407, the third waveguide portion424includes a fourth taper445. However, the third taper445may increase the width of the third waveguide portion424. The fourth taper445may taper between a starting width of 1000 nm and an increased or maximum width of 3.6 μm. The starting width may depend on width of the426. The maximum width may depend on the standard dimensions of the thin rib waveguide.

In some configurations, the first taper440, the second taper442, the third taper444, and the fourth taper445may be adiabatic tapers. In such configurations, the mode may be transferred through the waveguide at each of the tapers440,442,444,445without transition losses. Additionally or alternatively, the transition at the tapers440,442,444,445may be sufficiently gradual and/or smooth that transition losses at the tapers440,442,444,445are minimized or eliminated.

In the illustrated configuration, the SOI device400transitions from a single rib waveguide with a thickness of 306 nm (e.g., the first waveguide portion420) to a single rib waveguide with a thickness of 160 nm (e.g., the second waveguide portion422) using a three-level taper design. In particular, the first tapering portion404transitions the single rib waveguide on 306 nm SOI (e.g., the thicker waveguide portion402) to a strip waveguide on 160 nm SOI (e.g., at the second taper406), the second taper406transitions the wide 160 nm strip waveguide to a narrow 160 nm strip waveguide (e.g., at the coupling portion405) to reduce the lateral mode size, and the third taper407transitions the strip waveguide on 160 nm SOI (e.g., the coupling portion405) to a rib waveguide on 160 nm SOI (e.g., at the thinner waveguide portion408). The SOI device400includes the coupling portion405after the second taper406to allow the mode of the optical signals to stabilize before reaching the third tapering portion407.

FIGS. 8A-8Care graphs illustrating transition losses for tapers of different lengths.

FIG. 8Ais a graph illustrating coupling efficiency versus taper length for the first tapering portion404ofFIG. 7. InFIG. 8A, the horizontal axis represents taper length in microns and the vertical axis represents transmission.

FIG. 8Bis a graph illustrating coupling efficiency versus taper length for the second tapering portion406ofFIG. 7. InFIG. 8B, the horizontal axis represents taper length in microns and the vertical axis represents transmission.

FIG. 8Cis a graph illustrating coupling efficiency versus taper length for the third tapering portion407ofFIG. 7. InFIG. 8C, the horizontal axis represents taper length in microns and the vertical axis represents transmission.

As shown inFIGS. 8A-8C, the transition loss through the first tapering portion404, the second tapering portion406, and the third tapering portion407is relatively small. Transition loss may depend on the configuration of the first tapering portion404, the second tapering portion406, and the third tapering portion407. For example, transition loss may depend on the length of the taper and dimensions of the tip of the taper (e.g., width). As shown, for the configuration illustrated inFIG. 7, the transition loss may be approximately 0.04 decibels (dB) for the first tapering portion404, the second tapering portion406, and the third tapering portion407with a total length of less than 100 microns (e.g., transmission of greater than 99%). Accordingly, the configuration of the SOI device400as shown inFIG. 7may transition between the thicker waveguide portion402(e.g., 306 nm) and the thinner waveguide portion408(e.g., 160 nm) with substantially no transition losses or without significant transition losses.

As shown, the length of the tapers L1, L2, L3may be selected to be sufficiently long such that the tapers440,442,444,445are adiabatic tapers. In particular, the length of the tapers L1, L2and L3may be selected to adiabatically transform the optical mode of the optical signals traveling through the waveguides.

In the disclosed embodiments, a wide multimode strip waveguide with a thickness of 160 nm405and406is positioned in the middle of the transitions to improve fabrication tolerance and reduce the risk of etch mask overlay offset errors for the transitions.

FIG. 9Ais a simulated carrier concentration map of a cross-section of a vertical junction SOI modulator. InFIG. 9A, the different shading represents carrier density in the SOI modulator500.

FIG. 9Bis a graph illustrating the performance of the SOI modulator500ofFIG. 9A. InFIG. 9A, the horizontal axis represents reverse bias in Volts, the left side of the vertical axis represents insertion loss in dB/mm, and the right side of the vertical axis represents phase shift in degrees/mm.

FIG. 9Bincludes a line502representing insertion loss of optical signals travelling the SOI modulator500in dB/mm, and a line504representing phase shift of optical signals travelling the SOI modulator500in degrees/mm.FIG. 9Balso includes a table comparing the modulation efficiency VpiL, the insertion loss, and the figure of merit (FOM) for a 306 nm SOI and a 160 nm SOI. The VpiL represents the voltage and length needed to achieve one Pi phase shift. The FOM is determined by VpiL*IL. As shown, the Vpil decreases from 16.2 V·mm at 1.8 V for 306 nm SOI to 7.1 V·mm at 1.5 V for 160 nm SOI; the insertion loss decreases from 0.57 dB/mm to 0.45 dB/mm; and the FOM decreases from 9.2 V·dB to 3.2 V·dB.

In some example embodiments, an optical circuit for optical modulation of light may include an input waveguide including a first thickness, an optical modulator including a second thickness, and a tapered transition that optically couples the optical modulator and the input waveguide. The second thickness may be smaller than the first thickness. The tapered transition may adiabatically transform the optical mode of the input waveguide to the optical modulator.

The tapered transition may include a first waveguide portion including the first thickness and a second waveguide portion including the second thickness. The tapered transition may include a first tapering portion that may include a first length; and a second tapering portion that may include a second length. The first length and the second length may be sufficiently large enough to adiabatically transform the optical mode of the optical signals traveling through the first tapering portion and the second tapering portion.

The tapered transition may include a first waveguide portion that may include a first taper, a second waveguide portion that may include a second taper, and a third waveguide portion that may include a third taper. The first waveguide portion may have a first thickness, the second waveguide portion may have a second thickness, and the third waveguide portion may have a third thickness. The first thickness may be larger than the second thickness, and the second thickness may be larger than the third thickness.

The first waveguide portion may be formed by a first etch, the second waveguide portion may be formed by a second etch deeper than the first etch, and the third waveguide portion may be formed by a third etch deeper than the second etch. The first waveguide portion may be a double rib waveguide and the third waveguide portion may be a rib waveguide.

The tapered transition may include a first tapering portion that includes a first length, a second tapering portion that includes a second length, and a third tapering portion that includes a third length. The first length, the second length, and the third length may be sufficiently large enough to adiabatically transform the optical mode of the optical signals traveling through the first tapering portion and the second tapering portion.

The optical circuit further may include a coupling portion between the second tapering portion and the third tapering portion to allow the mode of optical signals to stabilize before reaching the third tapering portion.

The tapered transition may include a first waveguide portion that includes a first thickness, a second waveguide portion that includes a second thickness, and a third waveguide portion that includes a third thickness. The first thickness may be larger than the second thickness, and the second thickness may be larger than the third thickness. The first waveguide portion may be a rib waveguide, the second taper may be a strip waveguide, and the third waveguide portion may be a rib waveguide.

The optical circuit further may include a first taper decreasing the width of the first waveguide portion, a second taper decreasing the width of the second waveguide portion and the third waveguide portion, a third taper decreasing the width of the second waveguide, and a fourth taper increasing the width of the third waveguide portion.

The optical modulator may be a Mach-Zehder modulator. The first thickness may be between 300 nm and 310 nm and the second thickness may be between 160 nm and 220 nm. The optical modulator may include an n-doped region and a p-doped region. The n-doped region and the p-doped region may be positioned vertically with respect to one another in a waveguide to form a vertical PN junction.

The optical circuit may include a silicon on insulator photonic device. The second thickness of the optical modulator may be smaller than the first thickness of the input waveguide to improve optical confinement of the optical modulator. The tapered transition may confine the optical mode from the first thickness of the input waveguide to the second thickness of the optical modulator. The optical mode may be confined with substantially no transition loss through the tapered transition.

The optical circuit further may include cladding surrounding at least a portion of the tapered transition. In some configurations, the optical modulator includes an input and an output including the second thickness. The optical circuit may further include an output waveguide, and the output waveguide may include the first thickness. The output waveguide may be optically coupled to the optical modulator.

The terms and words used in the description and claims are not limited to the bibliographical meanings, but, are merely used to enable a clear and consistent understanding of the disclosure. It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a component surface” includes reference to one or more of such surfaces.

As used herein, an “electrical component” refers to a component that involves electricity, an “optical component” refers to a component that involves electromagnetic radiation (e.g., visible light or others), and an “optoelectronic component” refers to a component that involves both electrical signals and optical signals, and/or the conversion of electrical signals to optical signals, or vice versa.

Aspects of the present disclosure may be embodied in other forms without departing from its spirit or essential characteristics. The described aspects are to be considered in all respects illustrative and not restrictive. The claimed subject matter is indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.