Programmable logic array with dynamic test capability in the unprogrammed state

The present invention relates to a dynamically testable programmable logic array in an unprogrammed state which adds some circuit components to the static test logic. The static test logic provides the capability to detect stuck-at faults at the input of each logic gate of the programmable logic array, and is inoperative during normal operation of the programmable logic array. The added circuit components cause selected inputs to the product array to partially enable the product array, whereby the remaining inputs to the product array are a function of the inputs to the programmable logic array, thereby providing the dynamic test capability.

RELATED APPLICATIONS 
The present application is related to the following U.S. patent 
applications, which are assigned to Honeywell Information Systems Inc., 
the assignee of the present application, the references listed below being 
incorporated by reference herein: 
(a) "Programmable Logic Array with Test Capability in the Unprogrammed 
State by David W. Still and Peter C. Economopoulos, Ser. No. 446,816 filed 
12/3/82; and 
(b) "A Method of Programming a Programmable Logic Device by Vaporization of 
Metallized Links," by David W. Still and Peter C. Economopoulos, Ser. No. 
451,134 filed 12/20/82. 
BACKGROUND OF THE INVENTION 
This invention relates to a logic circuit, and more particularly to the 
dynamic testability of a programmable logic array. 
In the design of logic circuits, programmable logic arrays (PLA) have 
become increasingly more important for designing combinational logic 
circuits. These programmable logic arrays offer a greater variety and 
flexibility in logic design while lowering parts count and inventory 
requirements, and are also proving to be very cost effective. With 
programmable logic devices, a designer can customize a reliable, high 
volume integrated circuit to fit a specific application, and quickly. 
However, until recently, little has been done to test the programmable 
logic array in the unprogrammed state. This is due in part to the 
unavailability of an adequate number of test points on the chip. The 
various testing techniques devised require augmenting the PLA with a 
substantially large amount of additional logic which can interfere with 
the normal operation of the PLA logic or which requires and dissipates 
additional power even while the PLA is operating normally. 
The related application of paragraph (a) above presents a novel approach 
for providing static (or dc) test capability of a programmable logic array 
in the unprogrammed state with some small amount of added logic which is 
inoperative and dissipates no added power while the PLA is operating in 
its normal environment. 
Presently, ac, or dynamic, testing is either not performed or is performed 
after the programmable logic array is programmed. Thus, it is apparent 
that ac testing of programmed programmable logic arrays (or devices) 
require individualized test procedures or routines. Since many programmed 
combinations may be available, the number of individualized test routines 
can be quite high. 
Hence, it would be highly desirable to ac test a programmable logic array 
in an unprogrammed state. The present invention presents a novel approach 
for providing dynamic (or ac) test capability of a programmable logic 
array in the unprogrammed state. Some additional circuit components are 
added to the test logic of the programmable logic array to provide the 
dynamic test capability without comprising the static test capability. 
SUMMARY OF THE INVENTION 
Therefore, there is supplied a dynamically testable programmable circuit 
array, having a plurality of input terminals, each input terminal adapted 
to receive one of a plurality of input signals. The programmable circuit 
array comprises an input buffer, having a plurality of output terminals 
and inverted output terminals, the input buffer being operatively 
connected to the input terminal, which outputs equivalent input signals 
and inverted input signals, the equivalent input signals forming a first 
output group and the inverted input signal forming a second output group. 
The programmable circuit array also includes a programmable product array 
element which is operatively connected to the output terminals of the 
input buffer for generating a plurality of product terms. A programmable 
sum array element is included for combining the plurality of product terms 
to generate a plurality of sum terms, each of the plurality of sum terms 
being an output of the programmable circuit array. Test logic is also 
included which causes one of the output groups to have a predetermined 
logic state. 
The product array element includes a plurality of AND gates, each AND gate 
coupled to receive a respective input signal, and each AND gate having 
associated therewith a fusible link. The sum array element includes a 
plurality of OR gates, each OR gate coupled to receive a respective 
product term, and each input of each OR gate having associated therewith a 
fusible link. An input buffer can also be included to provide the input 
signal and the complement of the input signal to the product array 
element. The output can include a plurality of exclusive-OR elements each 
exclusive-OR element coupled to a respective output, and each exclusive-OR 
element having a fusible link, thereby providing a programmable capability 
to the output signal whereby the output can be in a normal or inverted 
state. 
Accordingly, it is an object of the present invention to provide a 
programmable logic array having test capability. 
It is another object of the present invention to provide a programmable 
logic array having one hundred percent test capability. 
It is still a further object of the present invention to provide a 
programmable logic device having dynamic test capability of the 
programmable logic device in the unprogrammed state. 
It is still another object of the present invention to provide a 
programmable logic device having one hundred percent test capability for 
detecting stuck-at faults occurring at all the gate inputs of the 
programmable logic array chip. 
It is still a further object of the present invention to provide a 
programmable logic device having dynamic test capability of the 
programmable logic device in the unprogrammed state without compromising 
the static test capability.