Display device

A display device including a substrate, a display portion positioned on the substrate and a pad portion positioned outside the display portion, a jumping portion positioned between the display portion and the pad portion, at least two power lines positioned on the substrate, a connection pattern connecting the at least two power lines to each other in the jumping portion, and an insulating layer spaced apart from the connection pattern and surrounding the connection pattern to prevent residue defects and short circuit defects at the jumping portion.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority from and the benefit under 35 U.S.C. § 119(a) of Korean Patent Application No. 10-2015-0123249, filed on Aug. 31, 2015, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to a display device, and more particularly, to a display device preventing a residue defect and a short circuit defect of lines.

Description of the Related Art

Various flat panel displays (FPDs) have replaced heavier and larger cathode ray tubes (CRTs). Examples of the flat panel display include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an organic light emitting diode (OLED) display.

In more detail, an OLED display is a self-emission display device configured to emit light by exciting an organic compound. The OLED display does not require a backlight unit used in a liquid crystal display and thus has a thin profile and lightness in weight and a simpler manufacturing process. The OLED display can be also manufactured at a low temperature and has a fast response time of 1 ms or less, low power consumption, a wide viewing angle, and a high contrast.

Further, the OLED display includes a light emitting layer formed of an organic material between a first electrode serving as an anode and a second electrode serving as a cathode. The OLED display forms hole-electron pairs, excitons, by combining holes received from the first electrode and electrons received from the second electrode inside the light emitting layer and emits light by energy generated when the excitons return to a ground level.

In addition, the OLED display includes a display area, in which an image is implemented through a plurality of pixels, and a non-display area positioned outside the display area. In the non-display area, a plurality of lines used to supply various signals to the plurality of pixels of the display area are disposed. In particular, the plurality of lines are generally made using metals having a low resistance, but the lines on the same layer occupy a large area of the bezel.

The OLED display uses the anode as the line of the non-display area, so as to decrease the bezel of the non-display area. However, when an anode layer is patterned, a residue of the anode remains. Thus, as shown inFIG. 1, a short circuit defect is generated between the residue of the anode and layers stacked on the residue of the anode due to the residue problem of the anode pattern, thereby reducing the reliability of the OLED display.

SUMMARY OF THE INVENTION

Accordingly, one aspect of the present invention is to provide a display device for preventing a residue defect and a short circuit defect of lines.

In one aspect, a display device includes a substrate, a display portion positioned on the substrate and a pad portion positioned outside the display portion, a jumping portion positioned between the display portion and the pad portion, at least two power lines positioned on the substrate, a connection pattern connecting the at least two power lines to each other in the jumping portion, and an insulating layer spaced apart from the connection pattern and surrounding the connection pattern.

In another aspect, the present invention provides a display device including a display portion on a substrate, a pad portion disposed outside the display portion on the substrate, a first initialization power line extended from the display portion, a second initialization power line connected to the pad portion, and a second initialization power line connected to the pad portion. The display device further includes a high potential power line disposed between the first and second initialization power lines, a low potential power line disposed on one side of the high potential power line and connected to the pad portion, a jumping portion disposed between the display portion and the pad portion, a connection pattern for connecting the first and second initialization power lines to each other in the jumping portion, and an insulating layer surrounding a horizontal portion of the connection pattern and not surrounding a vertical portion of the connection pattern.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. It will be paid attention that detailed description of known arts will be omitted if it is determined that the arts can mislead the embodiments of the invention.

A display device according to an embodiment of the present invention is a plastic display device, in which a display element is formed on a flexible plastic substrate. Examples of the plastic display device include the OLED display, the LCD, and an electrophoresis display. Embodiments of the present invention are described using the OLED display as an example of the plastic display device. The OLED display according to the embodiment of the invention may use a glass substrate as well as the plastic substrate.

A display device according to an embodiment of the present invention may also use a liquid crystal display instead of the above-described OLED display. For example, when an embodiment of the present invention is applied to the liquid crystal display, a pixel electrode or a common electrode of the liquid crystal display is formed as a transparent conductive layer, in the same manner as an anode according to the embodiment of the present invention. Therefore, the anode according to the embodiment of the present invention can be applied to lines of a power supply unit of the liquid crystal display.

Embodiments of the invention are described below with reference toFIGS. 2 to 15.

In more detail,FIG. 2is a schematic block diagram of an OLED display,FIGS. 3 and 4illustrate a first and a second example of a circuit configuration of a subpixel,FIG. 5is a plan view illustrating an OLED display, andFIG. 6is a cross-sectional view of a subpixel of an OLED display according to an embodiment of the present invention.

Referring toFIG. 2, the OLED display according to an embodiment of the invention includes an image processing unit10, a timing controller20, a data driver30, a gate driver40, and a display panel50. The image processing unit10outputs a data signal DATA and a data enable signal DE supplied from the outside, and can output one or more of a vertical sync signal, a horizontal sync signal, and a clock signal in addition to the data enable signal DE. The image processing unit10is formed on a system circuit board in an integrated circuit (IC) form.

Further, the timing controller20receives the data signal DATA and a driving signal including the data enable signal DE or the vertical sync signal, the horizontal sync signal, the clock signal, etc. from the image processing unit10. The timing controller20outputs a gate timing control signal GDC for controlling an operation timing of the gate driver40and a data timing control signal DDC for controlling an operation timing of the data driver30based on the driving signal. The timing controller20is also formed on a control circuit board in an IC form.

In addition, the data driver30samples and latches the data signal DATA received from the timing controller20in response to the data timing control signal DDC supplied from the timing controller20and converts the sampled and latched data signal DATA into a gamma reference voltage. The data driver30then outputs the gamma reference voltage. In particular, the data driver30outputs the data signal DATA through data lines DL1to DLn. Further, the data driver30is formed on a data circuit substrate in an IC form.

The gate driver40outputs a gate signal while shifting a level of a gate voltage in response to the gate timing control signal GDC supplied from the timing controller20. The gate driver40outputs the gate signal through gate lines GL1to GLm, and is formed on a gate circuit board in an IC form or is formed on the display panel50in a gate-in panel (GIP) manner.

In addition, the display panel50displays an image in response to the data signal DATA and the gate signal respectively received from the data driver30and the gate driver40, and as shown includes subpixels SP displaying the image.

Referring toFIG. 3, each subpixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an OLED. Further, the OLED operates to emit light based on a driving current generated by the driving transistor DR.

The switching transistor SW performs a switching operation so that a data signal supplied through a first data line DL1is stored in the capacitor Cst as a data voltage in response to a gate signal supplied through a first gate line GL1. In addition, the driving transistor DR operates so that the driving current flows between a high potential power line VDD and a low potential power line GND based on the data voltage stored in the capacitor Cst.

The compensation circuit CC is a circuit for compensating a threshold voltage of the driving transistor DR. The compensation circuit CC includes one or more thin film transistors and a capacitor. Configuration of the compensation circuit CC may be variously changed depending on a compensation method. As shown inFIG. 4, the subpixel including the compensation circuit CC further includes a signal line and a power line for driving a compensation TFT and supplying a predetermined signal or electric power. The added signal line may be defined as a 1-2 gate line GL1bfor driving the compensation TFT included in the subpixel. InFIG. 4, “GL1a” is a 1-1 gate line for driving the switching transistor SW. The added power line may be defined as an initialization power line INIT for initializing a predetermined node of the subpixel at a predetermined voltage. However, this is merely an example, and the embodiment of the invention is not limited thereto.

In addition,FIGS. 3 and 4illustrate that one subpixel includes the compensation circuit CC, as an example. However, the compensation circuit CC may be omitted when an object (for example, the data driver30) to be compensated is positioned outside the subpixel. The subpixel basically has a configuration of 2T(Transistor)1C(Capacitor) including the switching transistor SW, the driving transistor DR, the capacitor, and the OLED. However, when the compensation circuit CC is added to the subpixel, the subpixel may have various configurations of 3T1C, 4T2C, 5T2C, and the like.

Referring toFIG. 5, a display panel of an OLED display according to an embodiment of the invention includes a substrate110, a display portion DP, a pad portion60, first and second gate drivers40aand40b,a high potential power line VDD, a low potential power line GND, and an initialization power line INIT. As shown, the pad portion60is formed at an upper edge of the substrate110. Also, the pad portion60is electrically connected to an external circuit board. For example, the pad portion60is connected to a data circuit board, on which a data driver is mounted, or a control circuit board, on which a timing controller is mounted, and the like.

The first and second gate drivers40aand40bare circuits outputting a gate signal to subpixels SP formed in the display portion DP. Also, the first gate driver40ais positioned on the left side of the display portion DP and supplies a gate signal, and the second gate driver40bis positioned on the right side of the display portion DP and supplies a gate signal.

Further, the high potential power line VDD is used to transfer a high potential power received from the outside through the pad portion60to the subpixels SP of the display portion DP. The low potential power line GND is used to transfer a low potential power (or a ground level power) received from the outside through the pad portion60to the subpixels SP of the display portion DP. Also, the initialization power line INIT is used to transfer an initialization power received from the outside through the pad portion60to the subpixels SP of the display portion DP.

As shown, the high potential power line VDD and the initialization power line INIT are disposed between the pad portion60and the display portion DP. In particular, the low potential power line GND has an area between the pad portion60and the display portion DP and an area surrounding the display portion DP. The high potential power line VDD, the low potential power line GND, and the initialization power line INIT form a pair and are disposed on the display panel. As shown inFIG. 5, two pairs each including the lines VDD, GND, and INIT can be respectively disposed on the left and right sides of the pad portion60.

Referring toFIG. 6, an OLED display100according to an embodiment of the invention includes a substrate110made of glass, plastic, or metal, etc. In the embodiment of the present invention, the substrate110may be made of plastic, and more specifically, may be made of a polyimide substrate. Thus, the substrate110according to the embodiment of the invention has a flexible characteristic. Further, a first buffer layer112is positioned on the substrate110, and protects a thin film transistor formed in a subsequent process from impurities, for example, alkali ions discharged from the substrate110. The first buffer layer112may be a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof.

In addition, a shield layer114is positioned on the first buffer layer112and prevents a reduction in a panel driving current which may be generated by using the polyimide substrate. The shield layer114may be formed of a conductive material, a semiconductor such as silicon, a metal, and the like. A second buffer layer116is positioned on the shield layer114and protects a thin film transistor formed in a subsequent process from impurities, for example, alkali ions discharged from the shield layer114. The second buffer layer116may be a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof.

Also, a semiconductor layer120is positioned on the second buffer layer116and may be formed of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polycrystalline silicon. The polycrystalline silicon has a high mobility (for example, more than 100 cm2/Vs), low energy power consumption, and excellent reliability, and thus can be applied to a gate driver and/or a multiplexer (MUX) for use in a driving element or applied to a driving TFT of each pixel of the OLED display100.

Because the oxide semiconductor has a low off-current, the oxide semiconductor is suitable for a switching TFT which has a short on-time and a long off-time. Further, because the oxide semiconductor increases a voltage hold time of the pixel due to the low off-current, the oxide semiconductor is suitable for a display device requiring a slow driving and/or low power consumption. In addition, the semiconductor layer120includes a drain region and a source region each including p-type or n-type impurities. The semiconductor layer120also includes a channel region in addition to the drain region and the source region.

Further, a gate insulating layer125is positioned on the semiconductor layer120, and may be a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof. A gate electrode130is positioned on the gate insulating layer125in a predetermined portion of the semiconductor layer120, namely, at a location corresponding to the channel region when impurities are injected. The gate electrode130is formed of one of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a combination thereof. Further, the gate electrode130may be a multilayer formed of one of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a combination thereof. For example, the gate electrode130may be formed as a double layer of Mo/Al—Nd or Mo/Al.

An interlayer dielectric layer135is positioned on the gate electrode130, and may be a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof. Contact holes137and138exposing a portion of the semiconductor layer120are also formed by etching a portion of each of the interlayer dielectric layer135and the gate insulating layer125. In this instance, the portion of the semiconductor layer120exposed by the contact holes137and138may be the source region and the drain region.

A source electrode140and a drain electrode145are also electrically connected to the semiconductor layer120through the contact holes137and138passing through the interlayer dielectric layer135and the gate insulating layer125. Each of the source electrode140and the drain electrode145may be formed as a single layer or a multilayer. When each of the source electrode140and the drain electrode145is formed as the single layer, each of the source electrode140and the drain electrode145may be formed of one of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a combination thereof. When each of the source electrode140and the drain electrode145is formed as the multilayer, each of the source electrode140and the drain electrode145may be formed as a double layer of Mo/Al—Nd or a triple layer of Ti/Al/Ti, Mo/Al/Mo or Mo/Al—Nd/Mo. Thus, a thin film transistor TFT including the semiconductor layer120, the gate electrode130, the source electrode140, and the drain electrode145is formed.

Further, a passivation layer136is positioned on the substrate110including the thin film transistor TFT. The passivation layer136is a protective layer protecting the thin film transistor TFT underlying the passivation layer136and may be a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer thereof. A planarization layer150is also positioned on the passivation layer136for reducing a height difference of an underlying structure. The planarization layer150may be formed of an organic material such as polyimide, benzocyclobutene-based resin, and acrylate, and be formed through a spin-on glass (SOG) method for coating the organic material in a liquid state and then curing the organic material. As shown, the planarization layer150includes a via hole155exposing the drain electrode145of the thin film transistor TFT.

A first electrode160is also positioned on the planarization layer150. The first electrode160is an anode and may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). When the first electrode160is a reflective electrode, the first electrode160further includes a reflective layer. The reflective layer may be formed of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), Pd (palladium) or a combination thereof. Preferably, the reflective layer may be formed of an Ag/Pd/Cu (APC) alloy. Thus, the first electrode160fills the via hole155and can be connected to the source electrode145of the thin film transistor TFT.

In addition, a bank layer165is positioned on the substrate110including the first electrode160. The bank layer165is a pixel definition layer that exposes a portion of the first electrode160to define a pixel. The bank layer165may be formed of an organic material such as polyimide, benzocyclobutene-based resin, and acrylate. As shown, the bank layer165includes an opening167exposing the first electrode160.

An organic light emitting layer170is positioned on the first electrode160exposed by the opening167of the bank layer165. The organic light emitting layer170is a layer, in which electrons and holes combine and emit light. A hole injection layer or a hole transport layer may be positioned between the organic light emitting layer170and the first electrode160, and an electron injection layer or an electron transport layer may be positioned on the organic light emitting layer170.

Further, a second electrode180is positioned on the substrate110, on which the organic light emitting layer170is formed. The second electrode180is positioned on an entire surface of the display portion DP. In addition, the second electrode180is a cathode electrode and may be formed of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or a combination thereof each having a low work function. When the second electrode180is a transmissive electrode, the second electrode180is thin enough to transmit light, and when the second electrode180is a reflective electrode, the second electrode180is thick enough to reflect light. However, the OLED display has a problem of a poor driving or a short circuit that may be generated when the display panel is manufactured.

First Embodiment

FIG. 7is a plan view illustrating a part of an OLED display according to a first embodiment of the invention,FIG. 8is a plan view schematically illustrating a part of a line shown inFIG. 7, andFIG. 9is a cross-sectional view taken along line I-I′ ofFIG. 8.

Referring toFIGS. 7 and 8, a first initialization power line INIT1extended from a display portion DP and a second initialization power line INIT2connected to a pad portion60are disposed on a substrate110. Further, a high potential power line VDD is disposed between the first initialization power line INIT1and the second initialization power line INIT2and is connected to the pad portion60. A low potential power line GND is disposed on one side of the high potential power line VDD and is connected to the pad portion60.

As shown, the first initialization power line INIT1and the second initialization power line INIT2are connected to each other through a connection pattern ALP positioned on the first and second initialization power lines INIT1and INIT2. In particular, the first initialization power line INIT1is connected to the connection pattern ALP through a first contact hole CH1, and the second initialization power line INIT2is connected to the connection pattern ALP through a second contact hole CH2.

The connection pattern ALP is formed of the same transparent conductive material as a first electrode serving as an anode of a subpixel. The connection pattern ALP includes a horizontal portion HP parallel to the first initialization power line INIT1and a vertical portion VP vertical to the first initialization power line INIT1. As shown, the horizontal portion HP of the connection pattern ALP also overlaps the first initialization power line INIT1and is connected to the first initialization power line INIT1. The vertical portion VP of the connection pattern ALP jumps the high potential power line VDD and is connected to the second initialization power line INIT2.

In addition, the connection pattern ALP is surrounded by an insulating layer INL. Namely, the insulating layer INL is positioned to surround the connection pattern ALP. More specifically, the insulating layer INL surrounds the horizontal portion HP of the connection pattern ALP and does not surround the vertical portion VP of the connection pattern ALP. Because the insulating layer INL is formed of the same material as the planarization layer of the subpixel SP shown inFIG. 6and the vertical portion VP of the connection pattern ALP is adjacent to the pad portion60, the insulating layer INL is not formed around the vertical portion VP. However, the embodiment of the invention is not limited thereto. For example, the insulating layer INL may be positioned to surround the vertical portion VP of the connection pattern ALP.

Referring toFIG. 9illustrating a cross-sectional structure of a jumping portion JP, the insulating layer INL is positioned on a passivation layer136. The insulating layer INL is designed to have an inclined portion SLP. The connection pattern ALP is positioned on the insulating layer INL and the passivation layer136. More specifically, the connection pattern ALP is formed on the passivation layer136along the inclined portion SLP of the insulating layer INL from an upper surface of the insulating layer INL. In the embodiment disclosed herein, the connection pattern ALP is formed of the same transparent conductive material (for example, ITO) as the first electrode serving as the anode. In this instance, a residue defect, in which ITO partially remains in an etched portion of the connection pattern ALP after the connection pattern ALP is patterned. Thus, the embodiment of the invention forms the insulating layer INL having the inclined portion SLP at an edge of the connection pattern ALP.

When an edge (i.e., a portion that is etched and removed later) of the connection pattern ALP is positioned on the insulating layer INL, a patterned portion of the connection pattern ALP is positioned at an elevated position. Thus, an exposure amount at an upper part of the connection pattern ALP increases in a process for patterning the connection pattern ALP, and an amount of etchant applied to the connection pattern ALP increases. As a result, the residue defect of the connection pattern ALP can be prevented.

In the embodiment of the invention, when an area of the insulating layer INL increases or an inclination angle of the inclined portion SLP of the insulating layer INL increases, the residue defect of the connection pattern ALP can be prevented more certainly. However, the area of the insulating layer INL cannot increase unlimitedly due to other components adjacent to the insulating layer INL. Thus, the area and the inclination angle of the insulating layer INL may be properly adjusted. A bank layer165is also positioned on the connection pattern ALP which is formed on the substrate110and a second electrode180serving as a cathode is positioned on the bank layer165.

As described above, the OLED display according to the first embodiment of the invention forms the connection pattern ALP connecting the first initialization power line INIT1and the second initialization power line INIT2in the jumping portion JP and forms the insulating layer INL at the edge of the connection pattern ALP, thereby preventing the residue of the connection pattern ALP.

Next,FIGS. 10 and 11are cross-sectional views illustrating that a short circuit is generated in a jumping portion of a display device. Referring toFIGS. 10 and 11, a bank layer165is formed on a connection pattern ALP by thickly coating an organic material and then exposing and baking the organic material. The bank layer165corresponding to the insulating layer INL is more exposed to UV light due to a height of the insulating layer INL. Hence, because a volume of the insulating layer INL decreases in a subsequent baking process, the connection pattern ALP may be exposed. If the connection pattern ALP is exposed, a short circuit may be generated due to a contact between a second electrode180formed on the bank layer165and the connection pattern ALP.

Hereinafter, according to a second embodiment of the present invention, a display device for preventing a short circuit generated in a jumping portion is described.

Second Embodiment

FIG. 12is a plan view illustrating a part of a display device according to a second embodiment of the invention,FIG. 13is a plan view schematically illustrating a part of a line shown inFIG. 12,FIG. 14is a cross-sectional view taken along line II-II′ ofFIG. 13, andFIG. 15is a cross-sectional view illustrating another embodiment ofFIG. 14. Structures and components identical or equivalent to those described in the first embodiment are designated with the same reference numerals, and a further description may be briefly made or may be entirely omitted in the second embodiment.

Referring toFIGS. 12 and 13, a first initialization power line INIT1extended from a display portion DP and a second initialization power line INIT2connected to a pad portion60are disposed on a substrate110. A high potential power line VDD is disposed between the first initialization power line INIT1and the second initialization power line INIT2and is connected to the pad portion60. Further, a low potential power line GND is disposed on one side of the high potential power line VDD and is connected to the pad60. The first initialization power line INIT1and the second initialization power line INIT2are connected to each other through a connection pattern ALP positioned on the first and second initialization power lines INIT1and INIT2.

The connection pattern ALP is surrounded by an insulating layer INL. Namely, the insulating layer INL is positioned to surround the connection pattern ALP. The insulating layer INL according to the second embodiment of the invention is spaced apart from the connection pattern ALP while surrounding the connection pattern ALP. In the first embodiment of the invention, the connection pattern ALP is positioned from the upper surface of the insulating layer INL, but the connection pattern ALP on the upper surface of the insulating layer INL may be exposed by the bank layer. On the other hand, in the second embodiment of the invention, the connection pattern ALP is spaced apart from the insulating layer INL and is not exposed.

In the same manner as the first embodiment of the invention, the insulating layer INL surrounds a horizontal portion HP of the connection pattern ALP and does not surround a vertical portion VP of the connection pattern ALP. Because the insulating layer INL is formed of the same material as the planarization layer of the subpixel SP shown inFIG. 6and the vertical portion VP of the connection pattern ALP is adjacent to the pad portion, the insulating layer INL is not formed around the vertical portion VP. However, the embodiment of the invention is not limited thereto. For example, the insulating layer INL may be positioned to surround the vertical portion VP of the connection pattern ALP. Thus, the insulating layer INL is formed in an island pattern surrounding the connection pattern ALP, and more specifically, in an island pattern surrounding the horizontal portion HP except the vertical portion VP of the connection pattern ALP.

Referring toFIG. 14illustrating a cross-sectional structure of a jumping portion JP, a passivation layer136is positioned on the first initialization power line INIT1, and the insulating layer INL and the connection pattern ALP are positioned on the passivation layer136.

The connection pattern ALP passes through the passivation layer136and is connected to the first initialization power line INIT1. The insulating layer INL is configured to have an inclined portion SLP so that the connection pattern ALP does not remain after the connection pattern ALP is patterned. Further, the connection pattern ALP is positioned on the passivation layer136, and is spaced apart from the insulating layer INL.

In the embodiment disclosed herein, the connection pattern ALP is formed of the same transparent conductive material (for example, ITO) as a first electrode serving as an anode. In this instance, there occurs a residue defect, in which ITO partially remains in an etched portion of the connection pattern ALP after the connection pattern ALP is patterned. Thus, the embodiment of the present invention is configured such that an edge of the connection pattern A LP, that is etched and then removed, is positioned on the inclined portion SLP of the insulating layer INL.

When the edge of the connection pattern ALP, that is etched and then removed, is positioned on the insulating layer INL, a patterned portion of the connection pattern ALP is positioned at an elevated position. Thus, an exposure amount at an upper part of the connection pattern ALP increases in a process for patterning the connection pattern ALP, and an amount of etchant applied to the connection pattern ALP increases. As a result, the residue defect of the connection pattern ALP can be prevented.

In addition, the connection pattern ALP is spaced apart from the insulating layer INL at a predetermined distance through the above-described patterning process. When the connection pattern ALP is spaced apart from the insulating layer INL, a bank layer165positioned in a formation area of the connection pattern ALP can have a uniform thickness. Thus, the connection pattern ALP can be prevented from being exposed to the outside of the bank layer165.

The predetermined distance is not particularly limited and may have any value as long as the connection pattern ALP is not exposed by the bank layer165. Thus, as shown inFIG. 15, a portion of the connection pattern ALP according to the second embodiment of the invention may be positioned on the insulating layer INL. The bank layer165is positioned on the connection pattern ALP which is formed on the substrate, and a second electrode180serving as a cathode is positioned on the bank layer165.

As described above, the display device according to the second embodiment of the invention forms the connection pattern ALP connecting the first initialization power line INIT1and the second initialization power line INIT2in the jumping portion JP and forms the insulating layer INL positioned adjacent to the connection pattern ALP, thereby preventing the residue of the connection pattern ALP.

Further, the embodiments of the invention are configured such that the connection pattern formed in the jumping portion of the first and second initialization power lines is spaced apart from the insulating layer, thereby preventing a short circuit between the connection pattern and the second electrode being generated when the connection pattern is upwardly exposed to the bank layer.