Composite contention aware task scheduling

A mechanism is provided for composite contention aware task scheduling. The mechanism performs task scheduling with shared resources in computer systems. A task is a group of instructions. A compute task is a group of compute instructions. A memory task, also referred to as a communication task, may be a group of load/store operations, for example. The mechanism performs composite contention-aware scheduling that considers the interaction among compute tasks, communication tasks, and application threads that include compute and communication tasks. The mechanism performs a composite of memory task throttling and application thread throttling.

BACKGROUND

The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for composite contention aware task scheduling.

Resource contention is a conflict over access to shared resources, such as memory, disk storage, I/O devices, and cache. Multi-processor data processing systems may have shared memories, for instance. Multi-threaded processors may have a plurality of threads accessing the same caches. Multi-processor and multi-threaded data processing systems may experience latency due to resource contention despite the obvious advantages of multi-processing and multi-threading.

For example, many programs can be broken up into compute tasks and communication tasks. Compute tasks are portions of code that perform computational functions, such as arithmetic functions. Communication tasks are portions of code that perform I/O functions, such as accesses (i.e., load/store) to memory or persistent storage. When several threads access shared resources at the same time, resource contention may introduce latency into the threads.

SUMMARY

In one illustrative embodiment, a method, in a data processing system, for composite contention-aware task scheduling comprises decomposing an application into application threads, compute tasks, and memory tasks. The data processing system comprises a number of processors. A compute task comprises a group of instructions that perform computational functions. A memory task is a group of instructions that perform memory access operations. The method further comprises determining a number of application threads and a number of concurrent memory or compute tasks. The number of application threads and the number of concurrent memory tasks or concurrent compute tasks are less than or equal to the number of hardware threads that can run concurrently on the processors. In a simultaneous multithreading (SMT) enabled processor, more than one hardware thread can run on the same processor. The method further comprises scheduling the application threads, the compute tasks, and the memory tasks on the number of processors based on the number of application threads, the number of compute tasks, and the number of memory tasks or concurrent compute tasks.

DETAILED DESCRIPTION

The illustrative embodiments provide a mechanism for composite contention aware task scheduling. The mechanism performs task scheduling with shared resources in computer systems. A task is a group of instructions. A compute task is a group of compute instructions. A memory task, also referred to as a communication task, may be a group of load/store operations, for example. The mechanism performs composite contention-aware scheduling that considers the interaction among compute tasks, communication tasks, and application threads that include compute and communication tasks. The mechanism performs a composite of memory task throttling and application thread throttling.

FIG. 1is a block diagram of a data processing system with which aspects of the illustrative embodiments may advantageously be utilized. As shown, data processing system100includes processor cards111a-111n. Each of processor cards111a-111nincludes a processor and a cache memory. For example, processor card111acontains processor112aand cache memory113a, and processor card111ncontains processor112nand cache memory113n.

Processor cards111a-111nare connected to main bus115. Main bus115supports a system planar120that contains processor cards111a-111nand memory cards123. The system planar also contains data switch121and memory controller/cache122. Memory controller/cache122supports memory cards123that include local memory116having multiple dual in-line memory modules (DIMMs).

Data switch121connects to bus bridge117and bus bridge118located within a native I/O (NIO) planar124. As shown, bus bridge118connects to peripheral components interconnect (PCI) bridges125and126via system bus119, PCI bridge125connects to a variety of I/O devices via PCI bus128. As shown, hard disk136may be connected to PCI bus128via small computer system interface (SCSI) host adapter130. A graphics adapter131may be directly or indirectly connected to PCI bus128. PCI bridge126provides connections for external data streams through network adapter134and adapter card slots135a-135nvia PCI bus127.

An industry standard architecture (ISA) bus129connects to PCI bus128via ISA bridge132. ISA bridge132provides interconnection capabilities through NIO controller133having serial connections Serial1and Serial2. A floppy drive connection, keyboard connection, and mouse connection are provided by NIO controller133to allow data processing system100to accept data input from a user via a corresponding input device. In addition, non-volatile RAM (NVRAM)140provides a non-volatile memory for preserving certain types of data from system disruptions or system failures, such as power supply problems. A system firmware141is also connected to ISA bus129for implementing the initial Basic Input/Output System (BIOS) functions. A service processor144connects to ISA bus129to provide functionality for system diagnostics or system servicing.

The operating system (OS) is stored on hard disk136, which may also provide storage for additional application software for execution by data processing system. NVRAM140is used to store system variables and error information for field replaceable unit (FRU) isolation. During system startup, the bootstrap program loads the operating system and initiates execution of the operating system. To load the operating system, the bootstrap program first locates an operating system kernel type from hard disk136, loads the OS into memory, and jumps to an initial address provided by the operating system kernel. Typically, the operating system is loaded into random-access memory (RAM) within the data processing system. Once loaded and initialized, the operating system controls the execution of programs and may provide services such as resource allocation, scheduling, input/output control, and data management.

The illustrative embodiment may be embodied in a variety of data processing systems utilizing a number of different hardware configurations and software such as bootstrap programs and operating systems. The data processing system100may be, for example, a stand-alone system or part of a network such as a local-area network (LAN) or a wide-area network (WAN).

Data processing system100is an example of a multi-processing system with shared resources. For example, processor cards111a-111nmay share memory116. Furthermore, processor card111amay have more than one processor112a, and/or processor112amay have multiple cores or may be a multi-threaded processor. In accordance with an illustrative embodiment, an operating system or virtualization layer performs task scheduling with a composite of memory task throttling and application thread throttling as will be described below.

When a task scheduler in an operating system or virtualization layer schedules the same type of tasks without considering the interaction between different types of tasks in a multi-dimensional space, the tasks experience memory latency due to resource contention.FIG. 2is a graph illustrating normalized memory latency versus number of concurrent memory threads (CMT) in accordance with one aspect of the illustrative embodiments. As seen inFIG. 2, as the number of threads performing memory (communication) tasks concurrently increases, memory latency increases substantially.

In one aspect of the illustrative embodiments, the task scheduler divides threads into groups of compute tasks and memory tasks. Compute tasks are groups of instructions that perform computational functions, such as arithmetic functions. Memory tasks generally are groups of instructions that perform input/output functions or, more particularly, load/store operations. In accordance with this aspect of the illustrative embodiments, the task scheduler performs memory task throttling such that fewer threads perform memory tasks concurrently to reduce memory latency due to resource contention.

FIG. 3is a diagram illustrating memory task throttling in accordance with one aspect of the illustrative embodiments. With conventional scheduling, the task scheduler schedules memory tasks on a first processor (P0) and a second processor (P1) without considering the interaction between concurrent memory tasks. As seen inFIG. 3, the threads on P0and P1experience slow down due to resource contention.

With concurrent memory task (CMT) throttling, the thread on P1does not begin its memory task until the memory task on processor P0completes. As seen inFIG. 3, the two threads complete with shorter execution time. In this example, the shorter execution time is for two threads executing two memory tasks and two compute tasks; however, in a data processing system running thirty-two threads concurrently with hundreds or thousands of memory tasks, the improvement in execution time would be significant.

FIG. 4is a diagram illustrating memory task throttling with four processor threads in accordance with one aspect of the illustrative embodiments. As seen inFIG. 4, the threads experience the longest latency when four threads may run memory tasks concurrently (CMT=4). With CMT=1, meaning only one thread may run a memory task at a time, the threads experience the most wasted CPU cycles as threads wait for their turn to run a memory task. The task scheduler in the illustrative embodiment determines the optimal number of concurrent memory tasks. In the example depicted inFIG. 4with four processor threads, the optimal number of concurrent memory tasks is two (CMT=2).

In accordance with another aspect of the illustrative embodiments, the task scheduler performs application thread throttling. In multi-processor and/or multi-threaded data processing systems, the threads contend for resources, such as cache. In certain instances, the data processing system may perform the same amount of work with fewer processors.

FIG. 5is a diagram illustrating application thread throttling in accordance with an illustrative embodiment. In example (a), the application is divided into serial regions and parallel regions. During serial regions, the application runs on processor P0, while processors P1, P2, P3are shut down. During parallel regions, the application runs on all processors P0, P1, P2, P3running at nominal voltage/frequency.

In example (b), the application runs on all processors at reduced power during parallel regions. The task scheduler may use Dynamic Voltage and Frequency Scaling (DVFS). When processor frequency changes, its performance varies. When the supply voltage and processor frequency change, the processor's power consumption varies. Therefore, DVFS is a popular technique to trade off processor performance and power. The task scheduler determines that processors P0, P1, P2, P3perform the same amount of work during parallel regions with reduced power.

In example (c), the task scheduler determines that parallel region A can run on two processors with reduced power and that parallel region D can run on one processor at nominal voltage/frequency. Thus, the task scheduler throttles full processors, shutting down processors P2, P3in parallel region A and processors P1, P2, P3in parallel region D.

In accordance with the illustrative embodiments, the task scheduler decomposes application threads into compute tasks, communication tasks, and application threads (compute tasks+communication tasks). Different types of tasks can be interleaved in sequence in time due to data dependency. The same type of tasks can be parallel. The task scheduler searches for the right number of compute tasks, communication tasks, or application threads in certain order. The task scheduler selects an optimal combination from the search for a certain performance level.

FIG. 6is a diagram illustrating a combination of concurrent memory task scheduling and application thread throttling in accordance with an illustrative embodiment. With conventional scheduling, the task scheduler runs the application on three processors P0, P1, P2with memory tasks executing concurrently. As seen inFIG. 6, the threads experience slowdown due to compute and memory contention. Only one iteration of the throttling is illustrated for simplicity.

With thread throttling, the task scheduler runs the application on two processors, P0, P1with memory tasks executing concurrently. The threads still experience slowdown due to memory contention. With concurrent memory task throttling, the threads experience shorter execution time by throttling concurrent memory tasks. As seen inFIG. 6, the application experiences significantly shorter execution time with a combination of application thread throttling and concurrent memory task throttling.

While not shown explicitly, compute task throttling is beneficial when compute tasks contend for shared resources such as processor pipeline, functional units, register files, etc.

Compute task throttling, memory task throttling, and application thread throttling are all part of the composite contention aware thread and task throttling technique described herein.

In addition to performance, composite contention aware thread and task throttling can be applied to and adjusted by other metrics, such as power and energy consumption.

FIG. 7is a flowchart illustrating operation of a task scheduler for composite contention-aware task scheduling in accordance with an illustrative embodiment. Operation begins, and the task scheduler detects workload phase change by compute-communication ratio (block702). The task scheduler determines whether it detects a new phase (block704). If the task scheduler does not detect a new phase, the task scheduler returns to block702to continue detecting a workload phase change.

If the task scheduler detects a new phase in block704, the task scheduler searches for the best number, I, of application threads (block706) and searches for the best number, J, of concurrent memory tasks within the I application threads (block708). Then, the task scheduler performs a new scheduling with I and J with corresponding power management (block710). Thereafter, operation returns to block702to detect workload phase change.

In an alternative embodiment, the task scheduler may search for the best number of concurrent memory tasks and then search for the best number of application threads given the number of concurrent memory tasks. In yet another embodiment, the task, scheduler may search for the best number of application threads and the number of concurrent memory tasks in a single search, although the search space would be very large and the search would require a large overhead with little benefit over the above-mentioned embodiments.

Thus, the illustrative embodiments provide mechanisms for composite contention aware task scheduling. The mechanism performs task scheduling with shared resources in computer systems. A task is a group of instructions. A compute task is a group of compute instructions, A memory task, also referred to as a communication task, may be a group of load/store operations, for example. The mechanism performs composite contention-aware scheduling that considers the interaction among compute tasks, communication tasks, and application threads that include compute and communication tasks. The mechanism performs a composite of memory task throttling and application thread throttling.

The mechanism identifies a best number of application threads and a best number of concurrent memory tasks within the number of application threads. The mechanism then schedules the application threads on computational resources according to the number of application threads and the number of concurrent memory tasks. The mechanism may be embodied within a compiler or may be a part of runtime thread scheduling, such as in an operating system or virtualization layer.