Nitride semiconductor template and method of manufacturing the same

A nitride semiconductor template and a manufacturing method thereof are provided. The nitride semiconductor template includes a carrier substrate with a first thermal expansion coefficient, a nitride semiconductor layer with a second thermal expansion coefficient different from the first thermal expansion coefficient, and a bonding layer. The nitride semiconductor layer disposed on the carrier substrate is at least 10 μm in thickness. A ratio of a dislocation density of the nitride semiconductor layer at a first surface to that at a second surface is from 0.1 to 10. The bonding layer is disposed between the carrier substrate and the nitride semiconductor layer to adhere the nitride semiconductor layer onto the carrier substrate. The second surface is near an interface between the nitride semiconductor layer and the bonding layer, and the first surface is 10 μm from the second surface.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention is related to a semiconductor template and manufacturing method thereof, and particularly, to a nitride semiconductor template and method of manufacturing the same.

2. Description of Related Art

Recently, a nitride semiconductor has been widely used in electro-optical elements with short wavelength and high frequency elements with high power. However, due to the difficulty of the manufacture of gallium nitride (GaN) substrate and the high price of the GaN substrate, a GaN template is developed which includes a GaN layer formed on a heterogeneous substrate such as sapphire. Though the GaN layer can be successfully formed by using the heteroepitaxy technology on the above substrates, the characteristics of the GaN layer may be negatively affected, for example, bends or cracks may be generated in the GaN layer formed on the heterogeneous substrate.

Since the GaN substrate is expensive to increase the cost of the fabrication of the GaN layer and the conventional GaN template formed by the heteroepitaxy technology has undesirable quality, a new GaN template and the manufacturing method thereof are needed.

SUMMARY OF THE INVENTION

The present invention is related to a nitride semiconductor template including a carrier substrate, a nitride semiconductor layer, and a bonding layer. The carrier substrate has a first thermal expansion coefficient. The nitride semiconductor layer is disposed on the carrier substrate. A thickness of the nitride semiconductor layer is at least 10 μm, and the nitride semiconductor layer has a second thermal expansion coefficient different from the first thermal expansion coefficient. A ratio of a dislocation density of the nitride semiconductor layer at a first surface to the dislocation density of the nitride semiconductor layer at a second surface is from 0.1 to 10. The bonding layer is disposed between the carrier substrate and the nitride semiconductor layer to adhere the nitride semiconductor layer onto the carrier substrate. The second surface is near an interface between the nitride semiconductor layer and the bonding layer, and the first surface is 10 μm from the second surface.

The invention further provides a method of manufacturing a nitride semiconductor template. First, a patterning process is performed on a surface of a nitride semiconductor substrate of a first thermal expansion coefficient to form a structure layer including a plurality of nano rod structures. Next, an epitaxy process is performed on the structure layer to form a nitride semiconductor layer with a thickness of at least 10 μm. Thereafter, a wafer bonding process is performed by using a bonding layer to adhere the nitride semiconductor layer of the nitride semiconductor substrate on a carrier substrate of a second thermal expansion coefficient that is substantially different from the first thermal expansion coefficient. Then, after the wafer bonding process, a cooling process is performed such that the nitride semiconductor layer is self-detached from the structure layer in a vicinity of the structure layer during the cooling process.

In order to make the aforementioned and other features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

As used herein, the term “nitride semiconductor” in reference to a nitride semiconductor substrate or a nitride semiconductor template of the present invention means that a material of group III-nitride semiconductor comprises GaN, such as GaN, AlGaN, InGaN, or AlGaInN. An embodiment described in the present invention is GaN, and the choice of the material is recognized that the invention is not thus limited but can be accomplished by those skilled in the art. The features and the method of the present invention are more fully shown with respect to the following non-limiting example.

FIGS. 1A through 1G,2A through2B, and3through5illustrate a method of manufacturing a nitride semiconductor template according to an embodiment of the present invention. Referring toFIG. 1Afirst, a free-standing GaN substrate100is prepared. The free-standing GaN substrate100has a diameter and a thickness of, for example, 2 inches, and 350 μm. Generally, the average dislocation density of a growth surface of the free-standing GaN substrate100is not more than 107/cm2.

Thereafter, referring toFIG. 1B, an interlayer10and a metal layer20are sequentially formed on the surface of the free-standing GaN substrate100. In an embodiment, a material of the interlayer10includes SiO2or SiNx, and a material of the metal layer20includes Ni, Fe, or Co. Thickness of the interlayer10and the metal layer20are, for example, 3000 Å˜5000 Å and 100 Å˜400 Å, respectively.

Then, referring toFIG. 1BandFIG. 1Csimultaneously, an annealing process is performed on the metal layer20so as to form a plurality of nano balls22on the interlayer10. In the present embodiment, a manufacturing temperature of the annealing process is 700° C.˜950° C. The diameter of the nano balls22may be 50 nm to 400 nm. Thereafter, referring toFIG. 1C and 1Dtogether, an etching process is performed by using the nano balls22as masks to form the nano rod structures104respectively covered by the SiO2top12. In the present embodiment, a height H of each nano rod structure104is, for example, 0.8˜1.3 μm. The SiO2top12is then removed by performing an etching process to expose the nano rod structures104as shown inFIG. 1E.

Referring toFIG. 1F and 1G, a SiO2 layer106′ of 10 nm to 200 nm is formed to cover the nano rod structures104, and then the SiO2layer106′ is partially removed to expose the tops of the nano rod structures104so as to form the passivation layer106by performing another etching process. Accordingly, a structure layer102is made. It is noted that the etching processes and the patterning processes used in the method of forming the structure layer102can include any process such as dry etching process, wet etching process, photo-lithographical process, or other process known by a person in the art.

Referring toFIG. 1Gcontinuously, the structure layer102includes a plurality of nano rod structures104. The sidewalls of the nano rod structures104are covered by the passivation layer106and the tops of the nano rod structures104are exposed, therefore a plurality of concavities108′ are defined therebetween. Besides, the nano rod structures104are randomly or regularly distributed. In an embodiment, the distribution area of the nano rod structures104is substantially 30% to 45% of the area of the surface of the free-standing GaN substrate100. In addition, a material of the passivation layer160can be SiO2, SiNx, TiN, or TaN.

Next, referring toFIG. 2A, an epitaxy process is performed on the structure layer102to form a material layer110′. The epitaxy process includes a hydride vapor phase epitaxy (HVPE), a Molecular Beam Epitaxy (MBE), or a metal-organic vapor-phase epitaxy (MOVPE). It is noted that the material layer110′ is laterally grown from the tops of the nano rod structures104not covered by the passivation layer106during the epitaxy process as shown inFIG. 2A. Then, the material layer110′ is coalesced on the nano rod structures104and a GaN layer110is therefore formed as shown inFIG. 2B. Furthermore, a plurality of voids108are formed between the structure layer102and the GaN layer110.

It is noted that the features of the GaN layer110lies on its thickness and its average dislocation density distribution. As shown inFIG. 2B, the thickness of the GaN layer110is configured for achieving the coalesced first surface112without too thick to cause cracks in the interface between the GaN layer110and the nano rod structures104. Specifically, the thickness of the GaN layer110is, for example, 10 μm to 25 μm, which facilitates the formation of the subsequent elements. In addition, the crystal quality of the free-standing GaN substrate100used in the present embodiment is high, so that the reduction of the average dislocation in the GaN layer110grown laterally from the structure layer102is not significant. For example, if the average dislocation density of the growth surface of the free-standing GaN substrate100is 1×107/cm2, that of the second surface114of the GaN layer110is, for example, reduced to 5.5×106/cm2, but not lower than 1×106/cm2.

Thereafter, referring toFIG. 3andFIG. 4, a wafer bonding process is performed by using a bonding layer120to adhere the GaN layer110of the free-standing GaN substrate100on a carrier substrate130. A complex structure150is, for example, formed by the free-standing GaN substrate100, the GaN layer110, the bonding layer120and the carrier substrate130.

In the present embodiment, the wafer bonding process includes forming a first bonding layer122on the second surface114of the GaN layer110. In addition, a second bonding layer124is formed on a surface of the carrier substrate130. Then, the first bonding layer122and the second bonding layer124are bonded so as to tightly adhere the first bonding layer122and the second bonding layer124.

In the present embodiment, the carrier substrate130is Si, for example, and the materials of the first bonding layer122and the second bonding layer124includes SiO2, SiNx, TaN, or TiN. A process temperature of the bonding process is, for example, 600° C. to 850° C. It is noted that the materials of the first bonding layer122and the second bonding layer124can be the same or be different.

Then, referring toFIG. 4andFIG. 5, after the wafer bonding process, a cooling process is performed to separate the GaN layer110from the free-standing GaN substrate100. As an example, the carrier substrate130is Si, such that the thermal expansion coefficient K1 of the carrier substrate130is different from the thermal expansion coefficient K2 of the GaN layer110(e.g., K1=2.62×10−6K−1; K2=5.5×10−6K−1). When the complex structure150is cooled, the GaN layer110is self-detached from the free-standing GaN substrate100in the vicinity of the structure layer102. Preferably, the cooling process is performed by cooling the complex structure150from the bonding temperature to an ambient temperature for at least 25 minutes. As described above, upon reduction of the temperature, the nano rod structure104can be cracked thereby relieves the stress that is caused by the thermal expansion coefficient mismatch between the carrier substrate130and the free-standing GaN substrate100. Accordingly, in stead of the cracks occurring throughout the GaN layer110, the cracks occur in the nano rod structure104with voids108therebetween which is the weakest portion in the complex structure150. A GaN template200is therefore formed as shown inFIG. 5, and the GaN layer110can thus remain crack-free and viable for fabrication of semiconductor devices thereon.

As shown inFIG. 5, the GaN template200preferably includes the carrier substrate130, the bonding layer120, and the GaN layer110formed by separating from the free-standing GaN substrate100as explained before. Specifically, the thickness of the GaN layer110is configured in the range from 10 μm to 25 μm, which facilitates the formation of the subsequent elements. Therefore, as mentioned above, the reduction of the average dislocation density in the GaN layer110grown laterally from the structure layer102is not significant as explained in above.

Besides, a ratio of the dislocation density of the GaN layer110at the first surface112to the dislocation density of the GaN layer110at the second surface114is from 0.1 to 10 while the second surface114is near an interface between the GaN layer110and the bonding layer120, and the first surface112is, for example, at least 10 μm from the second surface114away from the carrier substrate130. For example, if the average dislocation density of the growth surface of the free-standing GaN substrate100is 1×107/cm2, the average dislocation density of the GaN layer110at the first surface112can be 1×107/cm2, and the average dislocation density of the GaN layer110at the second surface114is, for example, reduced to 5.5×106/cm2, but not lower than 1×106/cm2.

Thereafter, a surface treating process is performed on the first surface112of the GaN layer110in the present embodiment to achieve a flat surface ready for epitaxial growth. Herein, the surface treating process is, for example, a polishing process, a CMP process, a grinding process, or an annealing process, and thus a treated surface S is formed at the first surface112. The treated surface S is smooth with surface roughness (RMS) less than 1 nm as measured by atomic force microscope (AFM) in the 10 μm×10 μm area, for example. In addition, the detached free-standing GaN substrate100can be reused by executing the other surface treating process on the surface of the free-standing GaN substrate100after the separation of the GaN layer110to facilitate the next fabrication process as described inFIG. 1-5above. Similarly, the other surface treating process is, for example, a polishing process, a chemical mechanical polishing, a grinding process, or an annealing process as mentioned above.

A GaN template as disclosed in the present invention is large area, crack-free, and with a high quality for device fabrication applications. For example, the GaN template is 2 inches in diameter with a GaN layer of at least 10 μm thick. And the dislocation density of the growth surface of the GaN layer is not more than 10 times that of the surface located at least 10 μm from the growth surface of the GaN layer. For example, the average dislocation density thereof at the growth surface of the GaN template is substantially equaled to 1×107/cm2, and a reduced dislocation density thereof at a surface located at least 10 μm from the growth surface is lower than 1×107/cm2but not less than 1×106/cm2. In addition, the fabrication of the GaN template is simple and the expansive free-standing GaN substrate used for fabricating the GaN template with a thickness at least 10 μm can be reused so as to be apt to reduce the cost.

Although the present invention has been described with reference to the drawings and specification, it merely discloses a embodiment that is not for purpose of limitation and will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. For example, the thickness of the GaN layer110grown inFIG. 2Bare not necessarily between 10˜25 μm, but can be selected thicker or thinner in combination of certain process such as etching, CMP, grinding, or epitaxy process to meet the features of treated surface S as described in above. Further, modifications can be made for transferring twice to obtain a GaN template with the same structure as shown inFIG. 5except its dislocation density distribution. Namely, with reference toFIG. 5, the GaN layer110of the GaN template200is at least 10 μm thick, and has a dislocation density at the first surface112not less than 0.1 times that of the second surface. For example, the average dislocation density at the first surface112is 5.5×106/cm2, and the dislocation density at the second surface114is 1×107/cm2. An exemplary methods of manufacturing the structure is the same as those described inFIG. 1˜5with additional bonding and separation process similar to those described inFIG. 3˜5, which can be accomplished by conventional processes with appropriately selection of the bonding materials and customized conditions. Accordingly, the invention is intended to be broadly construed, to encompass all such variations, modifications, and alternative embodiments as being within the spirit and scope of the invention as hereafter claimed.