Read systems for 21/2D coincident current magnetic core memory

Organizations are disclosed for driving bit lines of a two-line 21/2D coincident current magnetic core memory in which a bit line not used for reading a bit out of a core is placed physically in parallel with the bit line driven by half select current to approximate in the unused line the capacitive and inductive coupling of the driven line with the word drive line. That coupling produces in the unused line the same noise (crosstalk) produced in the driven bit line by the word drive pulse. The crosstalk signal in the unused line is subtracted from the signal in the driven bit line before amplification and detection. The unused line may be a separate dummy line, or simply another bit line not being used for the bit being read out. In the case of paired bit lines used for common mode rejection of the bit drive signal, a second pair of unused bit lines is arranged in parallel for crosstalk cancellation.

BACKGROUND OF THE INVENTION 
This invention relates to organizations for a two-wire 21/2D coincident 
current core memory comprised of an array of toroidal cores, each core 
having a bit line driven by half select current and a word select line 
driven by half select current, and more particularly to organization for 
bit select (Y drive) lines time shared to read for both drive and sense 
functions with cancellation of cross-coupled noise from word select (X 
drive) lines. 
In a two-line 21/2D memory, selected X and Y drive lines are energized with 
half select current of the proper polarity for both read and write 
operations. Typically, the X line selects a word consisting of a number of 
bits, but first a number of Y drive lines are energized to select the 
bits. Thus, to read a word, the selected bit lines are energized, and 
after all ringing of the bit lines has subsided, the word line is 
energized. Both X and Y drive currents for each bit will have the same 
direction through the core to set it to the bit 0 state. If the core had 
previously stored a bit 1, the flux of the core being switched to a bit 0 
reduces a pulse on its bit line. The bit line may thus be used as a sense 
line, provided noise from the word select pulse also induced into the bit 
line can be cancelled. There are three configurations commonly used for 
achieving that cancellation. 
One configuration, shown in FIG. 1a, uses the same Y bit drive current to 
energize two bit lines L1 and L2 equally. One bit line passes through its 
cores in one direction relative to the X word drive line W1, and the other 
bit lines passes through its cores in the other direction. Since the word 
drive line passes through corresponding cores of both bit lines in the 
same direction, only one core is "selected" to receive coincident half 
select current for read, or write, of the same sense, i.e., direction 
through the core. The other core receives half select current in one 
direction, and the other half in the other direction, so it is not 
switched. The paired lines are connected to a differential sense amplifier 
10 so that only the difference in the currents on the paired sense lines 
will be amplified. As a consequence, the effects of the X drive pulse in 
the two lines will cancel, and only the line with the selected core that 
is switched will have any uncancelled current pulse which is sensed and 
amplified as a bit 1. A memory system employing this configuration for 
common-mode signal rejection is disclosed by the inventor in U.S. Pat. No. 
3,693,176. 
A second configuration very similar to the first employs paired bit drive 
lines, but instead of placing the corresponding cores of two different 
words on the two different bit lines L1 and L2, they are placed on the 
same bit lines, and the word select line W1 is folded as shown in FIG. 1b 
so that the word select pulse cancels itself on the selected bit line. 
Another variation folds the bit lines instead, as shown in FIG. 1c. These 
folded-line arrangements have a significant packaging advantage (lower 
wire termination density) over the unfolded arrangement of balanced sense 
lines and word lines in FIG. 1a, which allows significant cost reduction. 
In any of these arrangements, the sense amplifier 10 is preferably coupled 
to the bit drive lines by a balun transformer T1 shown in FIG. 2 for the 
arrangement of FIG. 1c. However, magnetic and capacitive coupling between 
word and bit lines with either of the folded or the unfolded arrangements 
is now inherently imbalanced, and such imbalance can be minimized only by 
elaborate packaging methods. What is required is an arrangement which does 
not require balanced magnetic and capacitive coupling, yet still permits 
selecting paired bit lines for reading out a word, one bit out of each 
pair of bit lines with cancelled X word drive current induced into the Y 
bit drive lines. 
SUMMARY OF THE INVENTION 
In accordance with the invention, bit lines of a two-line 21/2D coincident 
current magnetic core memory are arranged for reading to be physically in 
parallel with unused bit lines for balanced capacitive and inductive 
coupling between a word drive line and the parallel bit drive lines. Any 
noise signal in the selected bit line and its parallel unused bit lines 
are thus capacitively and inductively balanced for cancellation at the 
input of bit sense amplifiers. In one exemplary embodiment, the other 
unselected bit lines are paired dummy lines physically in parallel with 
selected bit lines connected to opposite ends of a sense transformer. The 
paired dummy lines are connected to opposite ends of a primary winding of 
a second transformer having its secondary winding in series with the 
secondary winding of the sense transformer. In a preferred embodiment, the 
physically parallel bit lines are two sets of paired and folded bit lines, 
only one set of which is selected by switching means to receive bit drive 
current. The unselected pair corresponds to the dummy lines of the 
exemplary embodiment. Diode switches are provided to automatically connect 
the unselected pair to opposite ends of the primary winding of the second 
transformer. The arrangement is otherwise the same as in the exemplary 
embodiment. The bit read out is sensed by a differential amplifier as the 
signal difference between the selected set. In another preferred 
embodiment, the physically parallel bit lines are only two in a set and 
both have the same word line. One bit line is selected to conduct half 
select current from a source at one end of the primary winding of a bit 
sensing transformer connected to a differential sense amplifier, but the 
other (unselected) bit line connected to the same half select current 
source is not. Instead, diode switching means automatically connects the 
unselected bit line to the other end of the primary winding of the sense 
transformer. This allows only a trickle of current through the unselected 
bit line so that its cores cannot be switched by the common X word drive 
line. In that manner, the differential voltage across the primary winding 
of the sense transformer consists of a signal with capacitively and 
magnetically induced noise from the X word drive line appearing as a 
common mode signal on both bit lines which cancel at the sense 
transformer. 
The novel features of the invention are set forth with particularity in the 
appended claims. The invention will best be understood from the following 
description when read in conjunction with the accompanying drawings.

DESCRIPTION OF PREFERRED EMBODIMENTS 
Referring now to FIG. 3, it will be noted by comparing it to FIG. 2 that 
paired bit lines L1 and L2 are coupled by a balun transformer T1 to a 
differential sense amplifier 10 in the folded Y bit line arrangement as 
shown in FIG. 1c. (The same reference numerals are being retained in the 
various figures for corresponding elements in order to facilitate 
comparison and understanding). The difference in the arrangement of FIG. 
3, which exemplifies the present invention, is that unused (dummy) sense 
lines DSL1 and DSL2 are placed in a physically parallel arrangement with 
the used bit drive lines L1 and L2. In a read operation, the Y (bit) 
select current I is turned on first. It divides about equally into the 
selected lines L1 and L2 of a memory array. The selected W (word) drive 
line W1 is then pulsed. Since the line W1 intersects only the line L1, it 
will switch only core 11 from a bit 1 to a bit 0 state because the half 
select X and half select Y currents pass through only that core in the 
same direction. (To select another word with line W1, the polarity of the 
word select pulse is reversed and only a core 12 is switched.) Switching a 
core induces a bit-1 signal in the bit line L1. If the selected core 11 
had been storing a bit 0, a bit-0 signal is induced in the bit line L1 
with some noise. A noise signal is also induced at the core 12 which is 
not switched even if it is storing a bit 1 because it does not receive 
half select current on the line L1 in the same direction. The noise signal 
(referred to hereinafter as crosstalk) includes core reversible flux as 
well as inductively and capacitively coupled components from the word 
select pulse on the line W1. 
The differential sense signal S is detected by the differential sense 
amplifier 10 which is coupled to the paired lines L1 and L2 by the balun 
transformer T1 that rejects the common mode signal and presents the 
difference at the secondary winding of the transformer T1. A transformer 
T2 is used for common mode rejection of the signal on the dummy lines DSL1 
and DSL2, and the output at the secondary winding of the transformer T2 is 
subtracted by adding it out of phase to the output of the sense 
transformer T1. Since the crosstalk from the word drive line is 
approximately the same in the dummy lines as in the used lines, the 
crosstalk portion of the sensed signal will be cancelled from the output 
of the sense amplifier 10. 
It should be noted that a balun sense transformer T1 has two primary 
windings of the same number (N1) of turns, and the secondary winding 
usually has a larger number (N2) to provide a step-up transformer. The 
secondary winding of the transformer T2 also has the same number (N2) of 
turns for a balanced common mode rejection into the amplifier 10. Since 
the transformer T2 has only one primary winding, and the same step-up 
ratio is to be maintained as for the transformer T1, the primary winding 
of the transformer T2 has twice the number of turns as the primary 
windings of the transformer T1. In other words, the arrangement of one 
primary winding in the transformer T2 is the equivalent of the arrangement 
of two primary windings in the transformer T1. 
In practice, a number of bit drive lines share the same sense transformer. 
There may also be a number of dummy lines for the bit drive lines. 
Multiplexing diode switches are then provided to make the necessary 
connections. 
This exemplary embodiment shown in FIG. 3 has the advantages of folded 
Y-drive lines, but the same technique for cancellation of X-drive 
crosstalk could be used to equal advantage in the unfolded configuration 
of FIG. 1a. The problem in either case is that unused (dummy) lines must 
be provided, adding to the expense, bulk and weight of the memory. A 
preferred arrangement for practicing the present invention is therefore 
one shown in FIG. 4 which is like the arrangement of FIG. 3, except that 
the unused lines providing X-drive crosstalk cancellation are paired bit 
drive lines not being used for the selected word. Two sets of paired bit 
drive lines L1a, L2a and L1b, L2b are arranged to be physically parallel 
so that a line of one pair serves as the unused (dummy) line for a bit 
line selected from the other pair. Diodes 14 connected to a load resistor 
R.sub.L automatically switch the unselected pair of bit drive lines to 
primary windings of a balun transformer T22. (This type of transformer is 
here used to facilitate implementing the switching arrangement of the 
multiplexing diodes, but it is otherwise equivalent to the transformer T2 
in FIG. 3.) Selection of one pair or the other of the lines is by Y-drive 
switch pair YD0 and switch pair YD1. Only one switch pair is turned on at 
a time to connect the paired lines L1a and L1b through switch pair YD0 or 
the paired lines L2a and L2b through the switch pair YD1 to the 
transformer T1. 
In operation, a signal (typically five volts) at terminal YS0 selects all 
of the group of Y-drive lines connected at junction PTA, but only one pair 
of bit drive lines will conduct current as selected by the switch pairs 
YD0 and YD1. A source 16 provides the amplitude of current necessary to 
read. If switch pair YD0 is activated (closed), current flows in lines L1a 
and L1b. Diodes D1 and D2 are then forward biased, whereas diodes D3 and 
D4 are not. This is so because conduction through the lines L1a and L1b, 
as determined by the high impedance current source 16, drops the voltage 
on the anodes of the diodes D3 and D4 enough so that they are 
insufficiently forward biased to conduct. But switch pair YD1 is not 
conducting so that the +5 volts at the junction PTA applied to lines L2a 
and L2b will forward bias the diodes D1 and D2. 
After the Y-drive current has become steady through the selected lines L1a 
and L1b, the selected word drive line W1 is pulsed. Only the core 11 will 
have half select current in the same direction in both X and Y lines to 
switch it. A small trickle of current flows through lines L2a and L2b 
adequate to forward bias diodes D1 and D2, but not enough to affect system 
operating margins. When that core 11 is switched, it induces a bit-1 pulse 
on the line L1a which is balanced with the line L1b so that it can be 
sensed, as described with reference to FIG. 2. But the word select line W1 
crosses only the line L1a, so as to induce crosstalk in the line L1a and 
not L1b. This crosstalk would make sensing of the bit-1 signal more 
difficult, so it is cancelled by the crosstalk induced in the line L2a. It 
is thus clear that lines L1a and L2a are paired for crosstalk cancellation 
via transformer T22 while lines L1a and L1b are paired for balanced 
bit-drive of the sense transformer. Similarly, lines L1b and L2b are 
paired for crosstalk cancellation via transformer T22 while lines L2a and 
L2b are paired for balanced bit-drive of the sense transformer T1. The bit 
lines paired for crosstalk cancellation are physically parallel in 
approximately the same paths in the memory so they will have substantially 
the same capacitive and inductive crosstalk from the word drive line. 
The preferred embodiment has been described with reference to FIG. 4 in a 
minimum arrangement, which is two paired lines L1a, L1b and L2a, L2b, each 
pair for common mode signal rejection of the Y drive current when 
selected, and the other pair for cancellation of crosstalk from the X 
drive line during a read cycle in accordance with this invention. For a 
better understanding of how a more complete memory may be organized for 
both read and write cycles, with the present invention implemented for a 
read cycle, reference is now made to FIG. 5. 
To facilitate understanding how the arrangement of FIG. 4 is embodied in 
FIG. 5, the same reference numerals are maintained for the paired bit (Y) 
drive lines L1a, L1b and L2a, L2b. Two additional pairs L3a, L3b and L4a, 
L4b are added to the Y-sink terminal YS0. Each pair for common mode signal 
rejection is separated in the drawing to group all of the "a" lines 
together above, and all of the "b" lines together below since the "a" 
lines are connected to the bottom end of the balun sense transformer T1 
when selected for use during a read cycle by the switch pair YD0 and the 
switch pair YD1 now shown with the pair YD0 separated into switches YD0Ra 
and YD0Rb, and the pair YD1 separated into switches YD1Ra and YD1Rb. The 
additional pairs L3a, L3b and L4a, L4b are arranged in a strictly 
analogous and symmetrically way as the first two pairs. 
The symmetry of the selection switches at the sense transformer T1 and the 
multiplexing diodes 14 at the noise cancellation transformer T22 is 
maintained. The only difference as to the four pairs is that the "a" lines 
are shown above as a group, and the "b" lines are shown below as a group. 
This grouping is a natural arrangement because the "a" lines are crossed 
by one set of word drive lines while the "b" lines are crossed by another 
set of word drive lines. When a core in one group is to be read from one 
of the paired "a" and "b" lines, the other of the pulsed lines is used to 
provide common mode signal injection. All of the remaining "a" and "b" 
lines of unselected pairs grouped together in the "a" group and in the "b" 
group are physically parallel to each other in the "a" and "b" groups. In 
addition, all of the remaining "a" and "b" lines of unselected pairs are 
coupled to the crosstalk rejection transformer T22 where bit drive current 
in the unselected pairs cancel and the crosstalk signal is developed for 
subtraction from the sensed output into the amplifier 10. 
It should be noted that the arrangement thus far described with reference 
to four pair of bit drive lines concerns only one bit of a word. Other 
identical arrangements are provided for other bits of a word, each 
arrangement with its own bit sense amplifier 10, but all sharing the same 
word select lines. 
A second Y-sink terminal YS1 can be provided to accommodate another four 
pairs of bit drive lines L5a, L5b; L6a, L6b; L7a, L7b; and L8a, L8b. These 
four pairs time share the four paired V-drive read switches connected to 
the transformer T1, and the diode multiplexing switches connected to the 
transformer T22. Banks of isolation (buffer) diodes 18 and 20 prevent any 
Y-select current in a pair of bit drive lines selected from the YS0 
terminal from energizing bit drive lines not selected from the YS1 
terminal. 
The banks of isolation diodes include not only one diode for each bit drive 
line connected to one of the Y-drive select switches for a read cycle, but 
also one diode for each bit drive line connected to Y-drive select 
switches for a write cycle shown in two groups of four, one "a" group 
labeled YD0Wa, YD1Wa, YD2Wa and YD3Wa, and one "b" group labeled YD0Wb, 
YD1Wb, YD2Wb and YD3Wb. A write cycle is executed in a conventional 
manner, and it does not include the transformers T1 and T22. For example, 
assume a core 22 is to be set to the "1" state in line L6a intersection by 
word line W3. The group of four bit drive lines that includes the line L6a 
is first selected by a negative pulse on the terminal YS1. Then shortly 
thereafter, the Y-drive switch YD1Wa is activated to provide negative half 
select current through the line L6a. While the terminal YS1 is still 
negative, and the switch YD1Wa is still activated, a terminal XS0 receives 
a positive pulse while a switch XD1Cb is activated to provide negative 
current through the word line W3, i.e., word select current in the same 
direction through the core 22 as the bit select current. The diode of the 
bank of isolation diodes 18 which connects the switch YD1Wa to the line 
L6a will conduct the necessary negative current, i.e., current from a 
source 24 to the terminal YS1, while all other diodes of the bank 18 are 
reverse biased and will therefore not conduct, thus isolating the current 
of the line L6a from all other bit lines connected to the terminal YS1. A 
bank 26 of buffer diodes similarly isolate one energized word line 
connected to a selectively activated terminal XS0 or XS1 from all other 
word lines. 
Operation during a read cycle will now be described by way of a summary for 
the arrangement shown in FIG. 5. Assuming a core 28 is to be read, the bit 
line L2a is first selected by applying a positive pulse to the terminal 
YS0, and then activating the half select read current from the source 16 
through the paired switches YD1Ra and YD1Rb as shown in FIG. 6 for the 
switch YD1Ra. Meantime, the XS0 terminal is made positive to charge the 
word select line W3, and thereafter a read pulse of proper polarity from a 
source 30 is transmitted through an activated switch XD1Cb. The core 28 
then has two half select currents through it of the same polarity to 
switch it to the "0" state. FIG. 6 shows the XS0 voltage and the XD1Cb 
current pulse. The voltage of the word line W3 will be affected by the 
read pulse, as shown in FIG. 6. The result of this shift in voltage on the 
word drive line W3 is to affect shifts in the bit line L2a to the 
transformer T1 that is not cancelled by the paired line L2b due first to 
capacitive and then to inductive coupling of the word drive line L3 to the 
bit line drive L2a. There will also be a pulse on the line L2a if the core 
28 was previously storing a bit 1 as it is switched to the "0" state, as 
shown by a dotted line over the waveform that shows crosstalk to the 
transformer T1. It can be readily appreciated that such crosstalk makes 
detection of the bit-1 pulse read out very difficult, if not impossible in 
some extreme crosstalk situations as that illustrated in FIG. 6. To cancel 
that crosstalk to the transformer T1, all of the other lines L1a, L3a and 
L4a connected to one side of the transformer T22, and all of the 
corresponding lines L1b, L2b and L4b connected in parallel to the other 
end of the transformer T22, produce crosstalk to the transformer T22 that 
is substantially the same as the crosstalk to the transformer T1, but in 
antiphase, so that when added in the secondary circuits of the 
transformers, the net voltage to the amplifier 10 is as shown in the last 
waveform, namely a zero (or reference) voltage with the bit-1 pulse, if 
any, superimposed. That bit-1 pulse can then be easily threshold detected 
at some level that will allow for some low amplitude noise to be 
tolerated. 
In an alternative arrangement for cancellation of word drive line crosstalk 
in the circuit shown in FIG. 7, bit drive current is pulsed through one of 
two folded bit drive lines L1 and L2 which are physically parallel so that 
any crosstalk induced in one by a half-select pulse on the word drive line 
W is also induced in the other bit drive line. One of the two bit drive 
lines is selectively connected to the primary winding of a transformer T 
by activating one of two switches YD0 and YD1. If line L1 is selected, 
diode D1 is forward biased by the half-select bit pulse through the line 
L1 while the switch YD1 is held off. Diode D2 is not forward biased 
because the switch YD0 allows half-select current to flow through line L1, 
thus dropping the voltage on the anode of the diode D2 below the voltage 
on the anode of D1. The coincident half-select word (X) current will then 
switch one of the two cores on the selected bit drive line, depending upon 
the polarity selected for the X pulse, in the normal manner for a Y-folded 
bit drive line. As in the arrangement of FIG. 4, the line L2 paired with 
the line L1 for noise cancellation can be easily arranged so that 
capacitive and inductive crosstalk components from the word drive line 
will be approximately equal for both bit drive lines. Consequently, the 
differential voltage applied across the input of the transformer T will 
consist of only the pulse produced by the switching core. Any noise 
induced in the line L1 will also be induced in the line L2 and therefore 
appear only as a common mode signal rejected by the transformer T. 
It should be noted that since the diode D1 is forward biased when the line 
L1 is selected, there is current in the line L2, but it is not sufficient 
current for one of its two cores to be switched by the X pulse. This 
arrangement is the same in that respect as the arrangement of FIG. 4. What 
is different is that an unused line is not paired with the selected line 
for balancing the half-select current in the selected line, but since the 
bit drive current is steady at the time the X pulse is applied to switch 
the core, the detection of a bit 1 read out of a core will be possible, 
and made easier by cancellation of crosstalk. The advantage of this 
arrangement is its simplicity and lower cost, even considering an optimum 
voltage source 32 shown which will simplify the design of the transformer 
T and the associated dc-restore and sense circuits. The voltage source can 
be implemented by use of resistors, Zener diodes or other means. 
Although particular embodiments of the invention have been described and 
illustrated herein with reference to folded bit lines, it is recognized 
that the invention may be practiced with unfolded bit lines, and that 
other modifications and equivalents may readily occur to those skilled in 
this art. Consequently, it is intended that the claims be interpreted to 
cover such modifications and equivalents.