Source/drain extension implant process for use with short time anneals

The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135) and a dopant implantation (145). The abnormal-angled dopant implantation (135) uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation (145) uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (105), wherein a portion (170) of the source/drain extension (160) is under the gate (120).

TECHNICAL FIELD OF THE INVENTION

The present invention is directed in general to the manufacture of a semiconductor device and, more specifically, to the fabrication of a source/drain extension.

BACKGROUND OF THE INVENTION

There is a continuing push to produce smaller semiconductor devices with lower power consumption and faster switching speeds. With device miniaturization, however, comes a number of new design problems. In particular, as new technologies are implemented to produce smaller device components, there is a need to retain compatibility with other components still being produced by older technologies.

For instance, consider the efforts to scale-down a metal oxide semiconductor (MOS) device. Scaling down the gate length, in addition to increasing device packing density, also facilitates the use of lower voltages and the faster operation of a field effect transistor (FET). Scaling down the gate, however, tends to increase the transistor's leakage current in the off-state. One approach to reduce the leakage current is to form a shallow source/drain extension immediately next to the gate and near the substrate's surface and the channel region. The source/drain extensions, as well understood by those skilled in the art, act as extensions of the more heavily doped source and drain region. The source/drain extensions are also widely referred to as shallow junctions or lightly doped drains (LDD).

Unfortunately, a conventionally-formed, and therefore conventionally-sized source/drain extension, used with a scaled-down gate does not necessarily cure the leakage current problem. A conventionally-sized drain extension can undesirably generate an electrical field that is sufficient to lower the gate threshold voltage and cause drain-induced barrier lowering (DIBL). The gate threshold voltage is reduced because the electric field from the drain penetrates into the channel and acts oppositely to the gate's electric field. DIBL occurs when the electric field from the drain reaches the source, thereby lowering the energy barrier to inject carriers into the channel.

Consequently, it is necessary to also scale-down the source/drain extension to reduce the strength of the electric field generated by the drain. Moreover, it is important to be able to scale down the dimensions of the source/drain extension in proportion to the degree of reduction in gate length. Source/drain extension can be scaled-down by using low dopant implant energies in combination with rapid or spike thermal annealing. The use of increasingly shorter thermal anneal times to provide smaller source/drain dimensions as devices are continuously scaled down, has been problematic, however.

As the duration of the annealing time is reduced, the dopant of the source/drain extension diffuses substantially shorter distances. This advantageously minimizes the depth of the source/drain extension in the substrate and produces extensions having a well-defined border, as exemplified by an abrupt decrease in dopant concentration in transitioning from the extension to substrate. An abrupt border is desirable as this supports the low-voltage operation of transistor devices and better defines the width of the channel region. Unfortunately, short anneal times also limit the extent to which implanted dopants of the source/drain extension diffuse under the gate.

It is desirable to form the source/drain extension such that it overlaps with the gate because this facilitates the electric field generated by the gate to cause majority carriers to accumulate in the border of the source/drain extension. The accumulation of majority carriers, in turn, helps mitigate the increased resistance associated with lower dopant concentrations in the border of the extension. High resistance in the border of the source/drain extension is undesirable because this reduces the transistor's on-state current.

Therefore there is need for an improved method to manufacture scaled-down source/drain extensions in semiconductor devices that avoid the above-mentioned limitations.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art, the present invention provides a process for fabricating a metal oxide semiconductor (MOS) device. The process includes forming a gate on a substrate and forming a source/drain extension in the substrate. Forming the source/drain extension includes an abnormal-angled dopant implantation process, using a first acceleration energy and tilt angle of greater than about zero degrees. There is also a dopant implantation using a second acceleration energy that is higher than the first acceleration energy. In addition, an ultrahigh high temperature anneal of the substrate is performed, wherein a portion of the source/drain extension is under the gate.

In another embodiment, the present invention provides a MOS device. The MOS device comprises a substrate having a top surface, a gate structure on the top surface and a source/drain extension in the silicon substrate. A portion of the source/drain extension is under the gate. The source/drain extension has a border at a depth of less than about 25 nanometers from the top surface of the substrate. The border is defined to occur when there is a decrease in dopant concentration, corresponding to an abruptness of less than about 30 Angstroms/decade.

Yet another embodiment of the present invention is a method of manufacturing an integrated circuit. The method includes forming MOS transistors using the above-described process. The method further includes interconnecting metal lines on one of more insulating layers located over the MOS transistors and interconnecting the MOS transistors to form an operative integrated circuit.

The foregoing has outlined preferred and alternative features of the present invention so that those of ordinary skill in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the scope of the invention.

DETAILED DESCRIPTION

The present invention benefits from an extensive series of investigations directed to the engineering of source/drain extensions having shallow depths. The examination of simulated dopant profiles, generated for various combinations of implantation energies and implantation tilt angles, lead to the realization of the multi-step implantation process of the present invention. The use of a multi-step implantation process of the present invention affords the necessary degrees of freedom to fabricate source/drain extensions having shallow depths and abrupt borders while still overlapping the gate. Moreover, this process can be modified so as to continuously adjust the dimensions of the source/drain extension as other components of the semiconductor device are scaled down.

One embodiment of the present invention is presented inFIGS. 1A to 1F, which illustrate sectional views of selected steps, at various stages of manufacture, of a process for fabricating a MOS semiconductor device100according to the principles of the present invention. Turning first toFIG. 1A, depicted is a partial sectional view of a conventionally formed semiconductor substrate105that has a top surface107. The substrate105can be made of conventional materials, such as silicon. A doped well110can be formed in the substrate to form a p-type or n-type well. For example, an n-type well110is preferably a silicon substrate105doped with an n-type dopant, such as arsenic (As+) or phosphorus (P+) using conventional procedures. A p-type well110is preferably a silicon substrate doped with a p-type dopant like boron (B+). Also shown are conventionally-formed shallow trench isolation structures115, which serve to electrically isolate the MOS device100from other adjacent devices formed in the substrate105.

Turning now toFIG. 1B, illustrated is the MOS device100after forming a gate120structure on the substrate105, using conventional materials, deposition and photolithography techniques. The gate120preferably includes a gate insulating layer122and gate electrode124. In some embodiments, the insulating layer122comprises a dielectric material, such as silicon dioxide. Suitable materials for the gate electrode124include doped polysilicon, metal, or combinations thereof. The shallow trench isolation structure115and gate120, by acting as masks, can advantageously define portions of the substrate105or well110to be exposed to dopants during the formation of the source/drain extension, as further discussed below.

As also illustrated inFIG. 1B, in some cases, it is desirable to deposit an optional thin conformal dielectric layer125, over the substrate105and gate120before forming source/drain extensions. Thus, a portion127of the dielectric layer125is on one or more sidewalls130of the gate120. Preferably, the conformal dielectric layer125is an oxide layer having a thickness132of less than about 100 Angstroms, and more preferably less than about 10 Angstroms.

FIGS. 1C and 1Ddepict an exemplary multi-step implantation process of the present invention used in forming source/drain extensions. For clarity, the implantations to form a single source/drain extension are shown. It would be apparent to one skilled in the art that pairs of source/drain extensions could be formed simultaneously or sequentially using this process. As illustrated inFIG. 1C, one component of forming source/drain extensions involves an abnormal-angled dopant implantation (a beam of dopants represented by arrow135) using a first acceleration energy and tilt angle137of greater than about zero degrees. The term abnormal-angled, refers to the dopant implantation source140being located substantially different from a direction normal to the top surface107of the substrate105. Preferably, the tilt angle137is less than about 20 degrees, because this avoids undesirable shadow mask effects associated with a substrate105densely packed with other device components. Shadow masking occurs when an angled dopant implantation is at least partially blocked by a device component, or partially constructed component, near the MOS device100. Even more preferably, the tilt angle137ranges from between about 10 and about 20 degrees. In some instances, a tilt angle137of between about 10 and about 14 degrees is preferred, because this is conducive to the production of MOS devices100with a higher device packing density on the substrate105. Of course, the abnormal-angled, dopant implantation can be done in a plurality of stages. In some preferred embodiments, for instance, the location of the implantation source140is moved symmetrically around the substrate105with a portion of the implantation done at each location. For example, the implantation source140could be moved to two or four location around the substrate105with one-half or one fourth of the implantation being done at each of the two or four locations, respectively.

As shown inFIG. 1D, another component of forming source/drain extensions involves a dopant implantation (a beam of the dopants being represented by arrows145) using a second acceleration energy that is higher than the first acceleration energy of the dopant implantation145. In some preferred embodiments, the acceleration energy of the abnormal-angled implantation135is less about 3000 eV, and the second acceleration energy is less than about 5000 eV.

Preferably, the dopant implantation145is done at a second tilt angle147that is less than the tilt angle137of the abnormal-angled dopant implantation135. In some instances, for example, the second tilt angle147is about zero degrees. A tilt angle substantially equal to zero degrees can be achieved by situating the dopant implantation145substantially normal (e.g., second tilt angle147less than about ±1 degrees).

In some embodiments, the dopant implantation145is done before the abnormal-angled dopant implantation135. More preferably, however, the abnormal-angled dopant implantation135is done before the dopant implantation145. The latter process sequence is advantageous because the abnormal-angled dopant implantation135serves to disorder or amorphize the substrate surface107so that the higher energy dopant implantation145is less prone to result in excessive depths of dopant channeling into the substrate105. Of course, in some cases, it may be desirable to also perform a pre-amorphization implant to amorphize the substrate surface107before forming the source/drain extension structure. As well understood by those skilled in the art, an amorphized surface is one that has lost its crystallinity and become substantially disordered.

Of course, the choice of dopant and the dose used depend on the type of MOS device100being produced and its intended use. For example, a positive channel metal oxide semiconductor (pMOS) transistor has a source/drain extension comprising p-type dopants such as B+. Alternatively, a negative channel metal oxide semiconductor (nMOS) transistor has a source/drain extension comprising n-type dopants such as P+or As+. Preferably, the abnormal-angled dopant implantation135and dopant implantation145use dopants of the same dopant type. However, the abnormal-angled implantation135and dopant implantation145can have a first and second dopant, respectively, where the second dopant has a different chemical composition than the first dopant. In some embodiments, for instances, the first dopant is P+and the second dopant is As+. One of ordinary skill in the art would understand the appropriate doses of dopants to use.

Turning now toFIG. 1E, illustrated is the partially completed MOS device100after forming sidewall spacers150on the gate sidewall130, and implanting source/drain dopants (represented by arrow155) in the substrate105. The dopant dose and acceleration energy associated with the source/drain implantation155are substantially higher than that used in source/drain extension implantations135,145. For example, implanting the source/drain dopant155includes a conventional dose and acceleration energy of dopants155, and a tilt angle of substantially zero degrees.

The multi-step source/drain extension implantations135,145are done without the source/drain sidewall spacer150in place. Preferably, therefore, the source/drain dopant implantation155is done subsequent to the source/drain extension dopant implantation135,145. In some cases, however, source/drain dopant implantation155is done before source/drain extension dopant implantation135,145. In such embodiments, the sidewall spacer150is formed, and source/drain dopant implantation155is done as described above. Next, the side wall spacer150is removed and then the above-described source/drain extension dopant implantation135,145is performed. One of ordinary skill in the art would understand how to incorporate alternative conventional processes for forming source/drain extension implantations135,145and source/drain dopant implantation155into the present invention.

FIG. 1Fillustrates the MOS device100after performing an ultrahigh high temperature (UHT) anneal of the substrate105to complete the formation of the source/drain extensions160, and the source/drain structures165. The UHT anneal serves to repair the substrate surface107and diffuse dopants to a limited extent into the substrate105. Thus, the UHT anneal and above-described multi-step implantation process cooperate to result in a portion170of the source/drain extension160being under the gate120. In preferred embodiments, the UHT anneal comprises heating to a temperature of greater than about 1150° C. for a time of less than 1000 ms. More preferably, the UHT anneal comprises heating to a temperature between about 1200° C. and about 1400° C. for a time of less than 100 ms, and more preferably, less than about 5 ms.

Preferably, a single UHT anneal is performed after each of the multi-step implantations135,145for the source/drain extension160and after implanting the dopants155for the source/drain structure165. In other embodiments, however, the UHT anneal is done after forming the source/drain structure165. In the latter case, the source/drain structure165is made by forming the sidewall spacer150and implanting source/drain dopants155substantially as described above, followed by a thermal anneal. The thermal anneal to form the source/drain structure165could be an UHT anneal, similar to that described above. Alternatively, the thermal anneal to form the source/drain structure165could be a rapid thermal anneal or spike anneal, where heating is to a temperature up to about 1100° C. for more than 1 second. After the thermal anneal to form the source/drain structure165, the sidewall spacer150is removed, and the above-described multi-step implantation135,145and UHT anneal is performed to form the source/drain extension160.

The abnormal-angled dopant implantation135and dopant implantation145, in cooperation with the UHT anneal, offer at least two degrees of freedom for source/drain extension engineering. The abnormal-angled dopant implantation135governs chiefly the extent to which the source/drain extension is under the gate. The dopant implantation145governs mainly the depth175of the source/drain extension160in the substrate105. Additional dopant implantation steps can be added to the multi-step implantation process, to add additional degrees of freedom and thereby refine the formation of the source/drain extension160. As an example, forming the source/drain extension160can include third and fourth dopant implantations using acceleration energies and tilt angles that are the same or intermediate between the energies and tilt angles used for the abnormal-angled dopant implantation135and dopant implantation145.

Another embodiment of the present invention is illustrated inFIG. 2, a metal oxide semiconductor (MOS) device200. Analogous reference numbers are used to depict similar structure to that presented inFIGS. 1A-1F. Any of the above-described embodiments of methods can be used to fabricate the MOS device200. In some preferred embodiments, the MOS device200can be a PMOS transistor device or an NMOS transistor device.

The MOS device200includes a substrate205having a top surface207, a gate structure220on the top surface207, and a source/drain extension260in the silicon substrate205. A portion270of the source/drain extension260is under the gate220and the source/drain extension260has a border275at a depth278of about 25 nanometers or less from the top surface207.

The border275of the source/drain extension260is defined as the location where there is an abrupt change in the concentration of dopants comprising the source/drain extension260. Those skilled in the art are familiar with the term abruptness. Abruptness is defined in terms of a distance interval one must travel through the source/drain extension260to realize a one-decade decrease in the dopant concentration. A common convention is to define the one-decade decrease in dopant concentration for the dopant concentration range of about 1×1019atoms/cm3to about 1×1018atoms/cm3. Of course, the one-decade decrease could be defined for a different concentration range of dopant, depending on total dopant concentration in source/drain extension260. For the purposes of the present invention, an abrupt change occurs when the abruptness is less than about 30 Angstroms/decade. More preferably, the abruptness is less than about 15 Angstroms/decade

The multi-step implantation process and UHT anneal imparts the source/drain extensions260with several beneficial structural features. For instance, the depth278of the border275can be continuously varied from 25 nanometers to about 1 nanometer. This allows the source/drain extension260to be constructed to suit a wide range of gate lengths280(e.g., lengths280from about 100 nanometers to about 10 nanometers). Moreover, independent of the source/drain extension's depth278, the portion270of the source/drain extension260under the gate structure220can be continuously adjusted to have an overlap285with an outer perimeter290of the gate structure220ranging from about 10 Angstroms to about 70 Angstroms.

As discussed in the context of the exemplary method presented inFIGS. 1A-1F, the source/drain extension260can include a first dopant and a second dopant corresponding to the abnormal-angled dopant implantation135and dopant implantation145, respectively. While first and second dopants are of a same dopant type, they can have the same or different chemical compositions. In certain embodiments, a ratio of the first to the second dopant in the270portion the extension260under the gate220is greater than a second ratio of the first to the second dopant in a second portion295of the extension260not under the gate220.

Of course, preferred embodiments of the MOS device200include a doped well210, source/drain structures265and sidewall spacers250. These structures can be formed as described above, or using other conventional procedures well known to those skilled in the art.

Another aspect of the present invention is a method of manufacturing an integrated circuit.FIGS. 3A and 3Billustrate Sectional views of selected steps, at various stages of manufacture of an exemplary an integrated circuit300. Turning toFIG. 3A, illustrated is a partial completed integrated circuit300, after forming MOS transistors305,310. In some embodiments, the transistors305,310are PMOS and NMOS transistors, respectively, in a complementary metal oxide semiconductor (CMOS) device. The transistors305,310can form part of logic, memory or other conventional circuits300.

Any of the above-described embodiments of the processes for fabricating a MOS device according to the present invention, such as illustrated inFIGS. 1A-1FandFIG. 2, can be used to form the MOS transistors305,310. For instance, forming the MOS transistors305,310includes forming gate structures315on a substrate320and forming source/drain extensions325in the substrate320. The source/drain extensions325are formed via a multi-step implantation scheme, followed by a UHT anneal substantially as described above. Other transistor components, such as wells330, source/drain structures335, sidewall spacers340and shallow trench isolation structures345can be fabricated using process described above, or by other conventional processes.

The ability to fabricate transistors305,310, and in particular source/drain extensions325, according to the present invention permits a higher packing density of device structures because components of the transistors can be scaled down. It is still desirable, however, to maintain a certain minimum separation between transistors305,310so as to avoid detrimental shadow masks effects, as previously discussed above.

Turning toFIG. 3B, illustrated is the integrated circuit300after interconnecting metal lines360on one or more insulating layer365located over the MOS transistors305,310and interconnecting the MOS transistors305,310to form an operative integrated circuit300.

Although the present invention has been described in detail, one of ordinary skill in the art should understand that they can make various changes, substitutions and alterations herein without departing from the scope of the invention.