A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.

BACKGROUND

The present disclosure relates generally to semiconductor device manufacturing techniques and, more particularly, to forming nickel-platinum (NiPt) alloy self-aligned silicide contacts.

In the manufacture of semiconductor devices, salicide (or self-aligned silicide) materials are formed upon gate conductors and diffusion regions to reduce the line resistance of a CMOS device, thereby improving the speed characteristics thereof. In salicide technology, a refractory metal or a near noble metal, such as titanium for example, is deposited on a silicon substrate. The deposited metal is then annealed, thereby forming a silicide layer only on the exposed areas of the substrate. The areas of unreacted metal left on the dielectric may then be selectively etched away without a masking step. Thus, the process is “self-aligning.”

As circuit devices have continued to shrink in size, however, it has been found that titanium silicide (TiSi2) becomes an unsatisfactory silicide material since the sheet resistance thereof begins to sharply increase when the linewidth of the device decreases below 0.20 microns (μm). More recently, cobalt disilicide (CoSi2) has been used as a replacement for titanium in salicide structures since it does not suffer from a linewidth dependent sheet resistance problem. On the other hand, the use of cobalt silicide structures is not without its own drawbacks. For example, unlike titanium, a cobalt layer requires a cap layer such as titanium nitride (TiN) due to the sensitivity of cobalt to contaminants during the annealing process.

Attention has also recently turned to nickel (Ni) as a silicide metal. Among silicide constituents, nickel silicide is considered important to the development of manufacturing processes in 65 nanometer (nm) MOSFET technology and beyond because of characteristics such as low electrical resistivity, low silicon consumption, good resistance behavior in narrow lines, and low processing temperature.

Typically, forming nickel silicide contacts includes forming a nickel metal layer on a semiconductor wafer. A first rapid thermal anneal (RTA) process is then performed to react nickel with silicon to produce nickel-rich silicide. Typically Ni2Si is the first metal-rich phase that nucleates. Thereafter, a selective etching process is performed to remove the portions of the nickel metal layer that are not reacted (i.e., those portions formed on insulating layer). A second rapid thermal anneal process is then performed to complete the fabrication of the nickel silicide, which forms the low resistance NiSi phase.

However, because nickel monosilicide (NiSi) (also referred to generally as “nickel silicide”) has low thermal stability, some nickel material may penetrate through the interface between metal and silicon down to the gate electrode to cause a spiking effect. It is also possible for nickel material to laterally diffuse to the channel region, to causing a nickel “piping” effect. To improve the thermal stability of nickel silicide, several approaches have been proposed, including the use of nickel alloys, and in particular nickel-platinum (NiPt) alloys. Platinum is a noble metal element with stable chemistry properties, and is helpful to improve the thermal stability of nickel silicide. On the other hand, platinum is also a difficult metal to etch, which may results in platinum residue being present following the removal of the unreacted metal layer.

SUMMARY

In an exemplary embodiment, a method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.

In another embodiment, a method of forming a semiconductor device includes forming a field effect transistor (FET) device on a substrate; forming a nickel-platinum alloy (NiPt) layer over the FET device and the substrate; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the FET device, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.

DETAILED DESCRIPTION

With respect to the above described use of NiPt alloys in silicide formation, a selective wet etch process which can remove unreacted NiPt, but that does not attack metal rich phase silicide, is needed. Although a sulfuric peroxide (SP) etch chemistry satisfies these requirements, the etching takes place at a relatively high temperature (e.g., >100° C.). Moreover, an SP chemistry may etch certain other metals, such as titanium nitride (TiN), at a high rate as well. Thus, a hot SP etch may be undesirable for high-k metal gate (HKMG) technologies having gate stack metals such as TiN, due to the risk of gate undercut and floating pattern defects.

Another selective etch approach currently used in the industry is to remove nickel from the unreacted NiPt layer after the first RTA using a wet etch, such as dilute nitric acid (HNO3). The dilute nitric acid etch leaves platinum rich residuals, which are removed with a second etch following a second RTA. The second etch is performed using a chemistry directed to removing platinum, such as Aqua Regia (nitric and hydrochloric acid; i.e., HNO3:HCl). However, this process leaves Pt residuals along the spacer sidewalls (terraces) and shallow trench isolation (STI) following the first etch, such as illustrated in the scanning electron microscope (SEM) image ofFIG. 1. The Pt residuals then react with Si during the second RTA, resulting in the formation of NiPt silicide “stringers” on the gate sidewall surfaces which cause contact shorts.

On the other hand, a conventional strength Aqua Regia etch to remove platinum residual material following the first RTA (and prior to the second RTA) is not selective to the metal rich silicide that forms below 350° C. Such an etch prior to the second RTA causes silicide “attack” or oxide growth in which the silicide metal is leached out. An example of this effect is illustrated in the images ofFIGS. 2 and 3, in which oxide growth has resulted in regions (arrows) above transistor gate electrodes where silicide contact formation is desired.

Accordingly, disclosed herein is an improved selective wet etch process for a NiPt silicide layer that is particularly advantageous in 32/22/14 nm technology nodes that employ HKMG structures. It has been determined that a metal rich silicide surface formed after a first RTA, and thereafter passivated by a first metal etch to remove the nickel constituent of the silicide layer, can then can tolerate a short (e.g., less than 60 second) dilute Aqua Regia etch. Under typical etch conditions using this chemistry, the Aqua Regia would attack the metal rich silicide. However, the chemistries used in exemplary embodiments herein have a very low TiN etch rate (e.g., on the order of few angstroms (Å) per minute), as compared to a hot SP chemistry (that etches TiN at a rate on the order of 100's or 1000's of Å per minute). Thus, the disclosed embodiments are also compatible with HKMG technologies.

Referring now toFIG. 4, there is shown a process flow diagram illustrating a method400of forming NiPt alloy silicide contacts, in accordance with an exemplary embodiment. Individual operations of the method400are further illustrated with reference toFIGS. 5-10, which are a series of cross sectional views of an exemplary FET device illustrating the resulting device structure as each silicide processing operation is performed.

Beginning in block402, a semiconductor device, such as an FET device that is ready for silicide contact formation is first precleaned with an appropriate solution in order to remove any native oxide formation present as a result of fabrication operations to this point. An exemplary FET device500in this regard is shown inFIG. 5. It should be appreciated that the FET device500is exemplary only, and that other device combinations and selection of materials are also contemplated. As illustrated inFIG. 5, the FET device500is formed over a semiconductor substrate502, which may include silicon, germanium, silicon germanium, etc. The substrate502may be a bulk substrate or a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate. Where transistor device isolation is desired, the substrate504may include one or more shallow trench isolation (STI) structures504formed therein, from an insulating material such as silicon dioxide for example.

A gate structure of the FET device500includes a gate insulating layer506, which may include a high-k dielectric layer and a gate electrode formed over the gate insulating layer506. For HKMG technology, the gate electrode may include a gate metal layer (e.g., TiN)508formed over the gate insulating layer506and a polysilicon layer510formed over the gate metal layer508. The patterned gate structure further includes spacers512(e.g., a nitride material) formed along sidewalls thereof. The spacers512may, for example, be formed following a first implantation operation to device source/drain extension regions514in a channel region below the gate insulating layer506, and prior to a second implantation operation to form deep source/drain regions516. Again, it should be appreciated that the FET device500to which the present silicide techniques are applied is exemplary only.

Referring again toFIG. 4, in block404following the precleaning, a NiPt alloy layer is formed over the FET device, which may be followed by or include an optional cap layer. The NiPt alloy layer518, having an exemplary Pt concentration of about 5% to about 30% atomic, is illustrated inFIG. 6, and may be deposited by any suitable technique known in the art. Then, in block406ofFIG. 4, the device is subjected to a first rapid thermal anneal (RTA 1) at a temperature of about 350° C. or less, and more specifically in a range of about 240° C. to 300° C. As shown inFIG. 7, portions of the NiPt alloy layer518in contact with silicon regions react with the silicide layer518to form metal rich silicide regions520. Conversely, portions of the NiPt alloy layer518in contact with insulating regions do not react and remain in the NiPt alloy state.

Following RTA 1, a (first wet) metal etch is performed as indicated in block408ofFIG. 4. In one embodiment, the first wet metal etch may include a standard clean (SC-1) etch, followed by a nitric acid (HNO3) etch, followed by another SC-1 etch. The SC-1 etch may be performed using ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2). Alternatively, the first wet metal etch may be performed using SC-1 only. As a result of the first wet metal etch, the nickel constituent of the unreacted NiPt alloy layer is substantially removed (as well as the optional cap layer), leaving behind a Pt-rich residue522as shown inFIG. 8. Furthermore, the surfaces of the metal rich silicide regions520are passivated by the oxidation aspect of the SC-1 process.

Then, as indicated in block410ofFIG. 4, a (second wet) dilute Aqua Regia etch is applied for a relatively short duration. In an exemplary embodiment, the dilute Aqua Regia etch is performed for a duration of less than 60 seconds, and more particularly for about 15 seconds. Again, in order to prevent attacking of the metal rich silicide regions, the Aqua Regia chemistry is diluted with water. In one embodiment, a HNO3:HCl:H2O ratio range may be, for example, 1:10:200 to 1:1:5, and more specifically about 1:5:4. That is, the dilute Aqua Regia etch may be 1 part nitric acid, 5 parts hydrochloric acid and 4 parts water. The temperature of the aqua regia solution may be between about 25° C. to 80° C., and more specifically at about 35° C.FIG. 9illustrates the structure following the short, dilute Aqua Regia treatment in which the remaining Pt-rich residue is removed, leaving the metal rich silicide regions520substantially intact.

Finally, in block412ofFIG. 4, a second, higher temperature rapid thermal anneal (RTA 2) is applied in order to form final silicide contact regions. The RTA 2 may be performed, in one embodiment, at a temperature of about 360° C. to about 500° C. for a duration of about 1 to about 60 seconds, and more specifically at about 420° C. for a duration of about 30 seconds. The final silicide contact regions524are illustrated inFIG. 10, at which point further processing may continue as known in the art (e.g., dielectric layer and wiring formation, etc.) Optionally, a standard Aqua Regia etch may also be performed at this point, since the final silicide contact regions524formed by the higher temperature anneal are more resistant to Aqua Regia attack.

As will be appreciated, a comparison between the image ofFIG. 11(which illustrates the removal the Pt residue) with the dilute Aqua Regia etch, in contrast to the image ofFIG. 1(which illustrates the removal the Pt residue), demonstrates the effectiveness of the above described approach. By employing a quick, dilute Aqua Regia treatment between the first and second RTAs, silicide stringers formed from Pt residue during the second RTA are avoided, thereby increasing device reliability. Moreover, the increased reliability does not come with the tradeoff of metal gate undercutting, or expensive proprietary platinum etch chemistries.