Method and apparatus for source-synchronous signaling

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

TECHNICAL FIELD

The present embodiments generally relate to circuits and techniques for communicating between integrated circuit devices.

BACKGROUND

Achieving effective power reduction in mobile system link architectures is a challenging task. Efficient low-power interfaces use circuits which may require turn-on or clock phase lock acquisition times. Unfortunately, the power consumption and latency resulting from such times may be inconsistent with the dynamic power and latency requirements of low-power systems. Moreover, architecting various power-modes to achieve bandwidth agility and lower total power involves additional delay to change between the power modes.

DETAILED DESCRIPTION

Overview

The following description presents various exemplary embodiments of a low power, high performance source synchronous chip interface which provides rapid turn-on to facilitate high signaling rates between a transmitter and a receiver located on different chips. In the embodiments presented herein, the chip interface (and associated methods of operation) employ various circuit blocks and techniques which together rapidly achieve a transition from a zero power state to a state in which full data rate transmission occurs, (for example, in about 8 nanoseconds or less). Moreover, in one embodiment, by removing one or more intermediate states between the zero power state and the full data rate state, a significant amount of power saving can be achieved.

However, rapid power switching within a device can cause significant power supply transients when the device goes through a turn-on/turn-off cycle. Some embodiments provide a “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process. For example, the fast turn-on bias circuit can segment the bias into a multi-stage bias network configured to stagger the turn-on process into multiple steps to reduce the power supply ringing.

To further reduce the effect of power supply ringing during rapid power switching, some embodiments use current mode logic (CML) clock buffers in the clock distribution network of the chip interface. These CML clock buffers typically have high immunity to power supply noise and hence provide better power supply noise rejection when they are incorporated into a chip interface using the rapid power switching. In some embodiments, a digitally controlled delay line (DCDL) (which can be inserted in the clock path in series with a clock buffer) can also be implemented with CML circuits. Consequently, some embodiments provide a chip interface that uses rapid power switching implemented in the fast turn-on bias circuit, and combines CML clock buffers and CML DCDLs to achieve both low overall power consumption and a high degree of power supply noise rejection.

In addition to facilitating low power operation, some embodiments achieve high operation speed in the chip interface by employing injection-locked oscillator (ILO)-based clock generation circuits. In some embodiments, ILO clock generation circuits multiply the frequency of reference clocks with a fast turn-on cycle. However, because the oscillator employed in such an ILO is periodically perturbed by the injected reference clock signal, the clock signal can suffer from relatively high deterministic jitter. To mitigate this problem, some embodiments employ matched source-synchronous clocking (MSSC) in combination with the ILO clock generator. In such systems, a DCDL can be inserted in a transmitter-side clock path to the data bits and another DCDL can optionally be inserted in a receiver-side clock path. Using these two delay elements facilitates performing arbitrary phase alignment between the clock and the corresponding data at the receiver. Further, the transmit side data-bit DCDL can be used to deskew the receive-side clock buffer. In this way, the clock edges can be ideally matched and the system can be made more tolerant to high frequency jitter in the ILO-generated source clock. In some embodiments, both the transmitter-side and receiver-side DCDLs are implemented using CML. In some embodiments, by design, the delay of the receive-side clock buffer ensures that all relative phases can be achieved by use of transmit-side DCDLs alone and no receive DCDL is required.

In some embodiments, instead of using a single DCDL in the transmitter-side or the receiver-side clock path in the MSSC system, a “master” DCDL is used in the main clock path to control delays in multiple data paths to compensate for skews that are common across all data paths, while multiple “micro” DCDLs can be added on a per-data pin basis to compensate for any “pin-to-pin” skews which are not covered by the master DCDL while the sum of both delays from both the master DCDL and a given micro DCDL still facilitate deskew of the receive-side clock buffer. In some embodiments, power consumption can be minimized by using fewer micro DCDLs and more main DCDLs by keeping the delays in common between multiple data bits. To further improve the immunity of the DCDLs to power supply induced jitter (PSIJ), some embodiments use DCDLs implemented using CML circuits.

Some embodiments that employ CML circuits in a clock distribution circuit can reduce DC power consumption by turning down the voltage swing, but in doing so can cause large duty-cycle errors in the clock distribution circuit. To remedy this problem, some systems attempt to correct a cumulative duty-cycle error at an end point of a clock path in the clock distribution circuit. However this duty-cycle correction technique can introduce large jitter in the clock path from the accumulated duty-cycle error before the correction point. In some embodiments, distributed duty-cycle corrections can be employed at multiple locations along the clock path, so that the accumulated duty-cycle error can be corrected in smaller increments at these multiple locations.

In one embodiment, a chip interface employs a multiplying ILO (MILO) to multiply up and generate faster clock signals from a reference clock signal to facilitate converting parallel input data signals into a higher speed serial data signal. Some embodiments provide techniques for periodically re-evaluating whether it is safe to retime transmit data signals directly with the faster clock signal.

Embodiments presented herein make reference to a chip interface where source-synchronous signaling involves transmitting a timing reference, in the form of a strobe signal or clock signal, in a path along with data such that the timing reference can then be used at the data receiver for capturing the data. In particular embodiments, a data signal (which could comprise parallel data signals) and a first timing reference are transmitted such that the data signal and the first timing reference have a known phase-relationship with respect to each other. In some embodiments, clock edge transitions which are used to generate the beginning and ending of a particular unit bit time at the transmitter are subsequently used to recover the same bit at the receiver by use of an integrator. In some embodiments, this is achieved by using two delay elements, with one placed on the transmitter-side and the other on the receiver-side. In some embodiments either the edge used to start the bit or to end the bit at the transmitter are used to sample the bit at the receiver.

In the discussion below, timing references are described in the context of “clock signals” or “clocks.” However, it should be understood that other forms of timing references, such as a strobe signal may be substituted for the clock signal, as applicable. Furthermore, the term “retiming” as used throughout the disclosure refers to the process of synchronizing a data signal with a clock signal so that the data signal and the clock signal have a known phase-relationship with respect to each other. When retiming across a mesochronous domain, retiming can also include the concept of moving data into the new clock domain with consistent latency. The term “CML” as used throughout the disclosure, sometimes referred to as “source-coupled logic,” is a differential current-mode-logic signaling scheme that employs low voltage swings and differential noise immunity to achieve high signaling speeds. A CML buffer typically has high immunity to power supply noise and hence provides better power supply noise rejection when it is incorporated into a chip interface including rapid power switching.

FIG. 1presents a block diagram of a MSSC system100. MSSC system100includes a transmitter102that resides on a first integrated circuit device (e.g., a controller device), a receiver104that resides on a second integrated circuit device (e.g., a memory device), and a channel106between transmitter102and receiver104. Channel106, in this embodiment, includes a data link108and clock link110. The transmitter102includes a serializer (SER)112configured to convert parallel data bits121to a serial data bit123, and transmitter102also includes a clock multiplier (×N)114that is configured to generate a faster clock bit_clk118, which has N times the frequency of a reference clock ref_clk120. The transmitter102further includes a clock divider (÷M)116, which is configured to take bit_clk118as an input signal and generate one or more slower clocks than bit_clk118. In one embodiment, the one or more slower clocks include a clock having the same frequency as ref_clk120. In an embodiment, the MSSC system100shown inFIG. 1comprises a single clock link110and multiple data links (while only one data link108is explicitly shown). Also note that data path111between a serializer (e.g., serializer112) on transmitter102and a deserializer, for example deserializer (DES)140that generates parallel data bits141on receiver104, is a data path for one serial data bit, e.g., data bit123. Although not explicitly shown, MSSC system100can include additional data paths which are substantially identical to data path111for transmitting parallel data signals from transmitter102to receiver104.

Note that there are also multiple clock paths in MSSC system100. A first clock path122, which contains a segment between node124and node126on transmitter102, provides a clock for retiming a serial data bit (e.g., data bit123) on transmitter102before transmitting the data bit over channel106. A second clock path128, which contains a segment between transmitter node124and receiver node130, provides the source-synchronous clock for retiming a received serial data bit on receiver104of MSSC system100. Note that both clock paths122and128carry buffered and delayed versions of bit_clk118(note that bit_clk118is rename as bit_clk119on receiver104for clarification purposes), which was multiplied from ref_clk120. Moreover, both clock paths122and128extend upward over the multiple parallel data paths. Hence, each of these clock paths is part of a global clock distribution network which distributes a master clock (bit_clk118) to multiple data paths in MSSC system100. At a local level, each of clock paths122and128is coupled to each data path through a local clock path. For example, clock path122is coupled to a flip-flop132associated with data bit123through a local clock path134, while clock path128is coupled to a data sampler136associated with data bit123through a local clock path138.

As is illustrated inFIG. 1, a clock buffer chain (or “buffer chain”)142is inserted in clock path122on the transmitter side of MSSC system100, while a clock buffer chain144is inserted in clock path128on the receiver side. Each of the buffer chains comprises a number of clock buffers coupled in series, wherein the clock buffers are smaller in size at the input side and increase in size toward the output side. This configuration is useful for generating a clock signal which can drive a large load. In some embodiments, clock buffers in each buffer chain are low-power CMOS clock buffers. In some embodiments, the clock buffers in each buffer chain are CML clock buffers that operate at low signal voltages relative to CMOS clock buffers. Other embodiments may use regulated CMOS buffers or other techniques used to buffer signals that are well known to those skilled in the art.

MSSC system100additionally includes a clock signal equalizer (EQ)143which is inserted in clock path122in series with buffer chain142, and a clock signal equalizer (EQ)145in clock path128in series with buffer chain144. These clock signal equalizers are used to equalize clock signals (e.g., bit_clk118) distributed within MSSC system100to reduce increased jitter during idle to active state transitions caused by inter-symbol interference (ISI) that distorts initial clock edges, and therefore to reduce or eliminate the wait time otherwise required to settle on a stable clock signal. Additionally, the equalizers minimize any jitter amplification that may occur due to transmission of a clock in a band-limited channel. By reducing jitter in the clock signals, MSSC system100can transition more quickly between idle and active states. MSSC system100also includes an equalizer (EQ)147inserted in the receiver-side of data path111that can be used to match the delay and response of received data bit123with equalized clock signal bit_clk118. In some embodiments, some of the equalizers in MSSC system100are continuous-time linear equalizers (CTLEs). A CTLE is an equalizer that is continuous in time, e.g. it does not use any clocking for signal decimation and operates over a range of frequencies.

Fast Turn-on Bias Circuit for Rapid Interface Turn-on/Off

One way to achieve low power operation in MSSC system100is to rapidly turn off the power to MSSC system100when the system is inactive (e.g., no data is being transmitted), and also to rapidly turn on the power when the system becomes active again. Note that such a fast turn-on/off system is often associated with high power supply induced jitter (PSIJ) because a rapid surge in current when the system is turned on (or off) leads to significant power supply transients which then cause jitter through the clock and data paths. In one embodiment, to reduce PSIJ during the rapid power switching, a “fast turn-on” bias circuit comprising one or more charge-sharing bias circuits configured with a staggered on/off mechanism may be used to provide bias voltages to various system components. For example, a “master” fast turn-on bias circuit150in MSSC system100provides bias voltages to transmitter-side circuits while a “slave” fast turn-on bias circuit152provides bias voltages to receiver-side circuits. Exemplary embodiments of the fast turn-on bias circuit with staggered on/off are described below in conjunction withFIGS. 2A,2B,3A, and3B. However, other embodiments of the fast turn-on bias circuit with staggered on/off can also be employed.

Generally, during power-up of a circuit, greater power is consumed to obtain a non-rail analog bias voltage in less time. For example, a circuit may be configured to obtain the desired non-rail voltage (“operating point”) in minimal time by increasing the current in an op-amp based feedback loop, but such a loop may also consume excessive power during normal operation and cause excessive supply collapse by requiring a large current surge during the power-up. Further, in order to keep noise immunity, bypass capacitance may be placed from a bias line to a supply rail, further slowing down the activation of the bias line. Thus, to conserve operating power and maintain integrity of the supply, typical circuits generating non-rail bias voltages exhibit a relatively slow power-on process.

Further, typical integrated circuits exhibit substantial capacitance at the supply node. Due to the inductance of the supply line and on-chip capacitance to reduce noise between the supply rails, any change in current to the bias circuit will induce a ringing in the supply voltage. The “severity” of the ringing will be dependent upon the magnitude of the current change, the speed of the surge, the value of the inductance and effective capacitance, and other factors.

In view of the characteristics of bias circuits and, more generally, circuitry for maintaining a non-rail voltage, example embodiments described below provide optimized non-rail voltages while improving the start-up speed and without inducing a large supply current surge.

FIG. 2Ais a circuit diagram of an embodiment of a bias circuit200that enables fast turn on of the applicable chip interface circuits described herein. The bias circuit200includes a current source220that is selectively enabled by the “Enable” signal to generate, along with a diode connected PMOS device222, a voltage at the bias voltage node Vbiasp. A plurality of outputs210, enabled by the bias voltage node Vbiasp, mirror a current at the current source220. The output nodes Vout1, Vout2and VoutN may be coupled to one or more nodes of a circuit (not shown) associated with the bias circuit200. A control circuit230selectively couples a capacitor232to the network.

Under normal operating conditions (Enable=“1”), the bias node Vbiasp is at a voltage between the supply rails Vdd, Vss. During power down (Enable=“0”), Vbiasp is pulled to Vdd, which in turn disables the outputs210(Vout1, Vout2, VoutN). The current source220may also be turned off to complete a power down of the circuit. The “power on” time, being the time required for the node Vbiasp to transition from Vdd to the given operating voltage, is dependent upon the total capacitance at the node and the value of the current source220as well as the characteristics of the diode connected PMOS device222. The “power on” time can be decreased by increasing operating power or the current at the current source220when the bias circuit200is initially powered on.

The control circuit230selectively couples the capacitor232to the network according to the “Enable” signal. In this manner, the capacitor232has zero volts on the lower terminal during power down, and, during power-up, is coupled to the bias node Vbiasp. Thus, upon startup, the charge on Vbiasp moves onto the capacitor232, thus bringing the voltage at the bias node Vbiasp toward the operating point voltage. As a result of this charge-sharing, the operating voltage can be obtained quickly, with minimal impact upon normal operation, while simultaneously reducing a surge of supply current to the bias circuit200.

In order to configure the control circuit230and capacitor232to achieve the operating voltage, the value of operating voltage for the bias node Vbiasp is first obtained. The total capacitance C for the node, including any residual capacitance exhibited by the circuit components, is obtained by measurement or estimation. The total capacitance C may then be divided into two domains in the power-down state: a first portion of C may be pulled to Vdd during power-down, while a second portion is pulled to Vss during power down. The domains are separated in the power-down state by the control circuit230, which isolates them via a passgate structure. The domains may be configured to be proportional to the desired operating voltage, such that, when the domains are combined upon startup of the circuit200(the control circuit230enables the path at Vbiasp), a voltage approximating or matching the operating voltage appears at the bias node Vbiasp.

A “charge share” may be effected between the capacitor232and the capacitance at the bias node Vbiasp opposite the control circuit230. Given two identical capacitors, if the first capacitor is charged to 1.2V, the second is completely discharged (to 0V), and the two are shorted together via a switch, the resultant voltage will be 0.6V, or halfway between the two capacitors' initial voltages. The charge on the first capacitor is “shared” to the second and since they are identical, the initial charge gets split equally. If the first capacitor is twice as large as the second, then the resultant voltage will be ⅔ of the initial voltage or 0.8V. Similarly, if the second is three times as large as the first, the final voltage will be ¼ of the 1.2V or 0.3V. By adjusting the ratio of capacitance, one can obtain a desired non-rail voltage.

Thus, with respect to the capacitor232, the capacitance value of the capacitor232may be selected based on the proportional capacitance to be achieved as described above. In particular, the capacitor232may be configured as a portion of the total capacitance C that is pulled to Vdd during power down. When the Enable signal is asserted to initiate power-up of the bias circuit200, the two domains combine (“charge share”) to produce the desired operating voltage at Vbiasp.

During power-down, all nodes are pulled to supplies and hence only consume current from device leakage, which may be quite low, and is approximately the same as the leakage of the same capacitance used as bias bypass capacitance. Other supply voltages, if available, may also be employed to optimize start-up time, current surge reduction, silicon area or other design considerations. The additional circuitry can be implemented in parallel to the existing bias circuitry. It may be beneficial to add additional capacitance to the bias node Vbiasp to achieve the target proportion of capacitance at the two domains. For example, a circuit implementation may present obstacles to dividing a node between the two domains during power-down, necessitating the additional capacitance.

Further, the bias node Vbiasp may benefit from additional capacitance to increase noise immunity. By referencing both domains of the total capacitance C to either supply (Vdd, Vss), operational noise within the circuit200may be minimized. However, the circuit200may be configured to “charge share” at power-up as described above, and then disconnect some or all of the capacitance (e.g., capacitor232) after a specified time or when the desired operating voltage is obtained.

For those cases where the desired operating point is a substantial portion of the supply, a single capacitor as shown may be sufficient to obtain (or approximate) the operating point within an acceptable time. When the operating point requires greater accuracy, or is dependent on characteristics of the circuit a number of alternative configurations to the bias circuit may be implemented. For example, an initial sharing may be conducted as described above, to an approximate voltage, followed by a period of normal active feedback control circuit operation to pull in the exact value. In this period the active circuitry consisting of the diode-configured PMOS device222and the current source220pull the bias node Vbiasp to the precise final value. Alternatively, an auto-adjust circuit may be employed to switch in more or less capacitance to compensate, in real time, for a change from the initial conditions. For example, just before a power-up sequence, the amount of capacitance may be adjusted in response to observation of the supply voltage, temperature, or some other circuit or environmental condition as well as the desired bias voltage. Further, a circuit may be implemented to perform a calibration that effectively measures change at the bias node and then adjusts the capacitance for the next power-up sequence. Example embodiments employing such configurations are described below with reference toFIGS. 3A and 3B.

Because the operating voltage and/or the capacitance of a bias node (e.g., bias node Vbiasp) may be dependent on manufacturing variations, or variations due to operating voltage or temperature, it may not be possible, during initial design of a bias circuit, to configure the capacitances of each domain to effect a “charge share” to obtain an exact voltage at power-on of the bias circuit. In such a case, a capacitance ratio can be selected to minimize startup time across corners. Alternatively, an additional bias circuit (not shown) omitting a control circuit may be employed in conjunction with the bias circuit200, where the bias circuit200obtains an approximate of the operating point and the additional bias circuit transitions to the operating point with greater accuracy. In still further embodiments, a bias circuit may employ a programmable capacitance ratio, which may be adjusted automatically based on a comparison with a replica circuit, or may be adjusted periodically under settings maintained at a register. Examples of such embodiments are described below with reference toFIGS. 3A and 3B. Adjustable bias circuits may be configured to compensate for changes in capacitance or other circuit characteristics resulting from the fabrication process, supply voltage or temperature of the bias circuit.

FIG. 2Bis a circuit diagram of a bias circuit201comparable to the circuit200described above, in an alternative configuration. The circuit201includes a current source225that is selectively enabled by the “Enable” signal to generate, along with a diode connected PMOS device227, a voltage at the bias voltage node Vbiasp. A plurality of outputs215, enabled by the bias voltage node Vbiasp, generate output voltages at nodes Vout1, Vout2and VoutN. The output voltages may be coupled to one or more nodes of a circuit (not shown) associated with the bias circuit201. A control circuit235, responsive to the “Enable” signal, selectively couples the two nodes Vbiasp1and Vbiasp.

The bias circuit201may be configured to operate in a manner comparable to the bias circuit200described above with reference toFIG. 2A, with the exception that a discrete capacitor is omitted. Rather, the control circuit235selectively combines the capacitances inherent at each node Vbiasp1, Vbiasp during power-on of the circuit201to obtain the operating point at the bias node Vbiasp. To accomplish this, the control circuit235may be positioned within the circuit201so as to divide the bias node Vbiasp into the two nodes Vbiasp1, Vbiasp when the control circuit235is disabled. The position of the control circuit235may be selected so as to achieve a proportional capacitance between the nodes Vbiasp1, Vbiasp as a function of the desired operating point voltage.

When the bias circuit201enters a power-down mode, the control circuit235pulls the node Vbiasp1to Vdd, and pulls the node Vbiasp to Vss. As a result, the PMOS transistors associated with outputs215are ON. To prevent any current in this mode, the NMOS transistors associated with outputs215are turn off by connection their gates to the “Enable” signal. Upon power-up of the circuit201, the control circuit235combines the nodes Vbiasp1, Vbiasp to form the desired voltage at Vbiasp, and a “charge share” is effected between the capacitances of the nodes Vbiasp1, Vbiasp. As a result of these capacitances being proportional as described above, the bias node Vbiasp is brought to the operating point quickly following power-up of the bias circuit201.

FIG. 3Ais a circuit diagram of a bias circuit300having a selectable array of capacitors. The circuit300includes a current source320that is selectively enabled by the “Enable” signal to generate, along with the diode connected PMOS device322, a voltage at the bias voltage node Vbiasp. A plurality of outputs310, enabled by the bias voltage node Vbiasp, generate output voltages at nodes Vout1, Vout2and VoutN. The output voltages may be coupled to one or more nodes of a circuit (not shown) associated with the bias circuit300. A control circuit330, responsive to the “Enable” signal, selectively couples an array of capacitors to bias node Vbiasp.

The bias circuit300may be configured to operate in a manner comparable to the bias circuit200described above with reference toFIG. 2A, with the exception that the control circuit330selectively enables a plurality of capacitors to be coupled to the bias node Vbiasp. In one embodiment, the control circuit330may be configured to couple all capacitors to the array during power-on of the bias circuit300. The values of the capacitors may be selected, in a manner as described above with reference toFIG. 2A, to achieve a proportional charge-sharing upon power-on of the bias circuit300to obtain a voltage at the bias node Vbiasp that is at or near the desired operating point. In alternative embodiments, during the inactive state, a first portion of the capacitors may be pulled to one rail (e.g., Vdd), while a second portion of the capacitors may be pulled to another rail (e.g., Vss). Under this approach, the first and second portions of capacitors (in addition to other capacitances inherent at the bias node Vbiasp) may be configured proportionately so as to obtain the desired operating point upon power-up.

In further embodiments, the control circuit330may enable only a selection of the capacitors to be coupled to the bias node Vbiasp during power-up. The particular selection of capacitors may be changed over time in response to one or more characteristics of the bias circuit300, a power supply or temperature variation, or associated circuitry. An example control circuit is described below with reference toFIG. 3B.

FIG. 3Bis a circuit diagram of a control circuit301for selecting the capacitors to be coupled to the bias node Vbiasp upon power-up of the bias circuit300ofFIG. 3A. This control circuit301may compensate for variations in the supply voltage Vdd. As Vdd decreases, more capacitance may be needed to bring Vbiasp to the appropriate value upon power-up of the bias circuit300. Accordingly, the control circuit301compares multiple inputs (relative to Vdd) against a reference voltage Vref. Based on this comparison, and in response to the “Enable” signal, the control circuit301outputs a plurality of enable signals “Enable1” . . . “EnableM” to enable a selection of the capacitors to be coupled to the bias node Vbiasp upon power-up of the bias circuit300. In alternative embodiments, the control circuit301may be configured to output the enable signals based on other circuit characteristics, thereby compensating for factors such as temperature variations or differences in the implementation of the circuit300(i.e., process variations).

Fast Turn-on Bias Circuit with Current Mode Logic (CML) Clock Buffers

To further reduce the effect of power supply ringing during the rapid turn-on/off process in an MSSC system, some embodiments use clock buffers implemented with current mode logic (CML). CML as used herein, sometimes referred to as “source-coupled logic,” refers to a differential signaling scheme that employs low voltage swings to achieve relatively high signaling speeds and linear amplification. In one embodiment, both clock buffers in buffer chains142and144are implemented using CML. These CML clock buffers typically have high immunity to power supply noise and hence provide better PSIJ rejection than CMOS clock buffers.

Note that CML clock buffers can also consume more DC power than CMOS clock buffers. However, this problem can be alleviated when CML buffer chains142and144are used in combination with the above-described fast turn-on bias circuit with staggered on/off mechanism. More specifically, when this combination is used during the rapid turn-on/off process, CML buffer chains142and144can be rapidly switched between a power-on state that consumes power and a non-functional power-off state that consumes zero or substantially less power. Hence, when MSSC system100is idle, the power consumed by these CML clock buffers can be completely turned off, so essentially no DC power is consumed by the CML clock buffers during the idle period. On the other hand, when MSSC system100becomes active again, the system (including CML buffer chains142and144) can be turned on quickly with very low PSIJ.

Note that integrating the fast turn-on bias circuit and the CML clock buffers into the fast turn-on/off system facilitates achieving both low overall power consumption and high PSIJ rejection in a given clock path. Although the combined circuit of a fast turn-on bias circuit and CML clock buffers is described in the context of MSSC system100, this combined circuit can generally be used in any type of clock distribution circuit which can experience times of inactivity.

MSSC System Employing a MILO

In some embodiments, to achieve high operating speeds in MSSC system100, clock multiplier114is implemented using a multiplying injection-locked oscillator (MILD)-based clock generation circuit. However, because bit_clk118, which is generated by such an MILO, is subject to periodic injection from ref_clk120that is not the same for every output cycle, bit_clk118can suffer from relatively high deterministic jitter. To mitigate this problem, MSSC system100includes a digitally controlled delay line (DCDL)146in clock path122in transmitter102, and in some embodiments also includes a DCDL148in clock path128in receiver104. Moreover, DCDL146is coupled in series with buffer chain142and equalizer143, while DCDL148is coupled in series with buffer chain144and equalizer145. In some embodiments, DCDLs146and148can be used to minimize or eliminate the skews between the data bits in the respective data paths (such as data path111) and the master clock in the respective clock paths122and128. In some embodiments there is no need for the receiver-side DCDL148. In these embodiments, the delay of clock buffer chain144, when properly designed, ensures that all deskewing can be achieved by using transmitter-side DCDL146alone.

In some embodiments, transmitter-side DCDL146and receiver-side DCDL148are collectively used to “color” the transmitter-side clock edges and the corresponding receiver-side clock edges. In other words, the individual clock edges which generate the beginning and ending of a particular data bit at the transmitter are transmitted in a source-synchronous fashion to the receiver and then the same two edges are used to recover the data bit at the receiver when using an integrating receiver, or one of the two edges is used when using a sampling receiver. As will be shown in more detail below, using these two delay elements facilitates performing arbitrary phase alignment between the clock and the corresponding data at the receiver. In this manner, the clock edges can be ideally matched to the data edges and the system made more tolerant to high frequency jitter in the MILO-generated source clock.

We now describe, in conjunction withFIGS. 4A-4C, high level operation of using the delay elements on both the transmitter and receiver sides to perform arbitrary phase alignment so that the same clock edges at the transmitter which are used to generate a data bit are also used to recover the data bit at the receiver.

FIG. 4Apresents a block diagram illustrating a system400using both transmitter-side and receiver-side delay elements. Note that system400includes a transmitter404that receives even data stream406, odd data stream407and clock408. In this embodiment, a first data transition410in odd data stream407′ is followed by a second data transition412in even data stream406′, while clock408includes a clock window formed by a falling clock edge414followed by a rising clock edge416. Note that although we describe the operation below in terms of a falling-edge-to-rising-edge clock window, the same description is equally applicable to the rising-edge-to-falling-edge clock window. In fact, while an interleaved double-data-rate (“DDR”) system is shown, system400can include a single-data-rate (“SDR”)-base system, a quad-data-rate (“QDR”)-based system, an octal data rate (“ODR”), or systems based on other types of clocking modes.

Note that falling edge414and rising edge416are aligned to transition in approximately the center of odd and even data406′ and407′ after data transitions410and412, respectively. In some embodiments, system400is a source-synchronous signaling system wherein data signal at output node409and clock signal at output node415are source-synchronized signals. In these embodiments, clock edges414and416are used to time the transmission of data resulting from transitions410and412, respectively via appropriate switching of the output mux405.

Transmitter404transmits even data stream406and odd data stream407, which are interleaved together, as well as clock408over channel418through a data link420and a clock link422, respectively. More specifically, even data stream406and odd data stream407pass through a pair of odd/even flip-flops and then through an output multiplexer (omux)405, which combines the two data streams, before passing through a data buffer417to reach a first output node409, where the combined data is transmitted onto data link420. Separately, clock408passes through a 0/1-tied output multiplexer (omux)411and a clock buffer413to reach a second output node415, where clock408is transmitted onto clock link422. The combined data406/407and clock408are received at a receiver424as received data426and received clock428, respectively. In some embodiments, however, the combined data406/407and clock408are transmitted over the same link between transmitter404and receiver424. This can be accomplished by transmitting the data and clock signals over the same link in different modes. Note that the received data426includes a first noise band430corresponding to data resulting from transition410with timing from clock edge414which is followed by a second noise band432corresponding to data resulting from transition412with timing from clock edge416. Moreover, received clock428includes a clock edge434associated with first noise band430, followed by a clock edge436associated with second noise band432.

Receiver424also includes the adjustable-sampling circuit402, which comprises an integrator438coupled to a sense circuit440. Integrator438receives data426as data input and a clock442that controls the start of the integration operation. The output of integrator438is coupled to the data input of sense circuit440, which directly receives clock428to control the sense operation (which effectively ends the integration operation). In some embodiments, sense circuit440is an edge-triggered sense circuit.

Note that system400also includes a transmitter-side delay element444and a receiver-side delay element446. Each of these delay elements can be implemented using a delay-line or other delay means (for example, the DCDL described above). In some embodiments the two different delay elements can use elements in-common, and in some cases, share some or all calibration codes in common. The two delay elements generate two relative timing delays which can be used to adjust the phase-relationships between received data426and received clock428, so that adjustable-sampling circuit402operates with a window within the data eye448between noise bands430and432. It should be noted that there are multiple ways of creating the delays needed on either the transmitter or the receiver side, and the techniques used need not be identical on both sides. In addition, some embodiments may use one or the other of delay elements444and446and not both and thereby experience some but not all of the benefits of a window tuned to eliminate both noise bands.

More specifically, transmitter-side delay element444delays the original clock408by a first delay time to generate a delayed clock452. Delayed clock452is then used to clock even data stream406and odd data stream407through a pair of flip-flops, which delays the combined output data relative to the original transmitter clock408by the same delay time. Consequently, received clock428thus leads the received data426by the same amount because of delay element444, assuming that data link420and clock link422have matching transport delays. In particular, the second clock edge436of the transmitted clock428is a sense edge which is coupled to the clock input of positive edge triggered sense circuit440. Because of the first delay time, the second clock edge436triggers sensing of the received data426earlier than it would in a traditional source-synchronous system, thus facilitating the movement of it ‘inside’ the data eye448and before the noise band432.

FIG. 4Billustrates how noise band432in the delayed data426is adjusted relative to sense edge436. Note that without applying the delay to clock408, sense edge436triggers the sense operation within the noise band432. InFIG. 4A, second noise band432associated with data transition412is delayed relative to sense edge436, which causes sense edge436to shift relative to the data earlier toward the center of the data eye448defined by the inner edges of the noise bands430and432. The amount of delay is calibrated at the first delay element444so that sense edge436substantially aligns with the beginning (edge) of the second noise band432as shown inFIG. 4B. In some embodiments, this calibration accounts for delay mismatch between data link420and clock link422. In some embodiments, the edge of noise band432can be defined based on where an acceptable bit-error-rate is achieved. In some embodiments, other techniques are used to define the edge of noise band432. Consequently, the exactly location of the edge of noise band432may vary depending on the particular technique that is used.

Referring back toFIG. 4A, note that the receiver-side delay element446delays clock428by a second delay time to produce the delayed clock442, which thus contains within it a delayed version of clock edge434. In particular, the delayed version of clock edge434provides a precharge edge which determines the start of the integration operation on integrator438.

FIG. 4Cillustrates how the precharge edge (provided by the delayed version of clock edge434) is adjusted relative to noise band430in delayed data426. Note that without applying the delays to both clock428and data426, the precharge edge is positioned relative to noise band430as shown inFIG. 4B. If a delay is applied to data426but no delay is applied to clock428, in some embodiments the precharge edge is positioned relative to noise band430as shown inFIG. 4Cwhich is to the left of noise band430. Alternately with no delay applied to data426the precharge edge can be positioned in the center of noise band430similar to the sense case. In the embodiment illustrated inFIG. 4A, the precharge edge is delayed by delay element446so that it moves toward data eye448, which is defined by the inner edges of the noise bands. The amount of delay is calibrated at second delay element446so that the precharge edge substantially aligns with the end of the first noise band430as shown inFIG. 4C. In some embodiments, the edge of noise band430can be defined based on where an acceptable bit-error-rate is achieved. In some embodiments, other techniques are used to define the edge of noise band430. Consequently, the exactly location of the edge of noise band430may vary depending on the particular technique that is used.

Note that the two delays are introduced on integrated circuit devices positions at different sides of channel418. More specifically, a sense-edge advance at receiver424is achieved by delaying the input data from the transmitter side, while the precharge-edge delay is achieved by delaying the received clock428at the receiver side. This facilitates maintaining the association between clock edges414and416and the data transitions triggered by these clock edges, thereby facilitating alignment of the precharge edge and sense edge with data eye448. Further precision in the placement of the edges is allowed by use of two separate signals of the same (DDR) clock rate at the receiver. Note, in this example, that this delay and alignment technique does not require adding substantial delay to the clock as a method of deskewing clock and data by creating a skew whose phase would appear to be zero but is in fact ‘rounded up’ to become substantially an integer multiple of 1-unit-interval (“UI”) as is commonly done. Maintaining matching (or ‘coloring’) between clock and data edges, in this example, better facilitates high-speed operation by facilitating keeping sources of jitter and distortion in-common between individual edges of clock and data.

In one embodiment, adjustable-sampling circuit402can include a control mechanism configured to disable/bypass the integrator438so that data426passes through integrator438to the sense circuit440without a substantial integration. This configuration is useful during the process of calibrating the delay on delay element444for aligning the sense edge with the data eye. Adjustable-sampling circuit402is switched back to the regular integrating-sampling mode when this calibration is complete. Alternately the sense circuit may be use to directly sample data with the integrator bypassed if higher performance is achieved this way. In another embodiment, if system margins allow, the integrator may be removed entirely and a sampling receiver only may be used. In this embodiment, the matching of edges is not as ideal as it was with the integrator as the sampling receiver, with only a single edge, can align to only the starting or ending edge of the transmitted bit. However, if system margins allow for it the use of a sampling receiver alone without integration can simplify the MSSC system and circuit design.

Referring back toFIG. 1, in some embodiments, one or both DCDLs146and148in MSSC system100are implemented using CML. As with the above-described CML clock buffers, these CML DCDLs provide high immunity to power supply noise and, hence, better PSIJ rejection than CMOS DCDLs. In these embodiments, the CML DCDLs can also receive bias voltage from a fast turn-on bias circuit configured with the staggered on/off to facilitate reducing PSIJ during rapid power on/off operations. Note that integrating the MILO-based clock generation (without phase detectors) and the CML DCDLs into MSSC system100facilitates both high-speed operation and high PSIJ rejection in a given clock path. Although a system comprising both MILO-based clock generation (without phase detectors) and CML DCDLs is described in the context of MSSC system100, this combined circuit can generally be used in any type of source-synchronous system, not just the implementations of an MSSC system.

In some embodiments, MSSC system100simultaneously uses CML buffer chains142and144, CML DCDLs146and148in clock paths122and128, and a fast turn-on bias circuit with staggered on/off (which is separated into master fast turn-on bias circuit150and slave fast turn-on bias circuit152) to set the bias voltages for the CML clock buffers and CML DCDLs. More specifically, when this combination is used during the rapid turn-on/off process, CML clock buffers and CML DCDLs can be rapidly switched between a power-on state, that consumes power, and a non-functional power-off state, that consumes zero or substantially less power. Hence, when MSSC system100is idle, the power consumed by these CML components can be completely turned off so that essentially no DC power is consumed by the CML clock buffers and CML DCDLs during the idle period. Note that integrating the fast turn-on bias circuit and the CML clock buffers and CML DCDLs into the fast turn-on/off system facilitates achieving both low power consumption and high PSIJ rejection in a given clock path.

Distribution of Duty-Cycle Correction in a Clock Path

Some embodiments which employ CML clock buffers and/or CML DCDLs in MSSC system100can reduce DC power consumption by turning down the voltage swing, but in doing so can cause large duty-cycle errors in the clock distribution circuits. Some systems attempt to correct a cumulative duty-cycle error at an end point of a clock path.

FIG. 5Apresents a block diagram of a clock path500which uses an end-point duty-cycle correction mechanism. As illustrated inFIG. 5A, clock path500includes a DCDL502, an equalizer (EQ)504and a buffer chain506coupled in series. The portion of clock path500which includes these circuits can represent clock path122inFIG. 1. Note that clock path500can also include additional clock path circuits. In some embodiments, DCDL502, EQ504and buffer chain506are made of CML circuits. For low power operation in a CML-based clock path, it is desirable to reduce the rail-to-rail voltage supplied to the CML-based circuits as well as the output swing voltage. This, however, can lead to increased duty-cycle errors in the clock distribution circuits. In one embodiment, to resolve this conflict, a duty-cycle corrector (DCC), such as DCC508, is added at the end of the clock path to detect and correct duty-cycle errors. In the embodiment shown inFIG. 5A, the system attempts to correct a cumulative duty-cycle error through clock path500from DCDL502, EQ504and buffer chain506all at once. However, this end-point correction technique can result in large jitter in the clock path before the correction block, with associated side effects due to pulse shortening and duty-cycle error amplification in cascaded stages.

Note that, while DCC508is shown as a self-contained circuit placed at the end of the forward clock path500, DCC508can also be configured as a closed loop circuit with a feedback coupled to an earlier location in clock path500. For example,FIG. 5Aillustrates an exemplary feedback510(the dotted line) from DCC508, which measures the duty-cycle error at the end of the path, to the input512of DCDL502. In this embodiment, feedback510can send a control signal from DCC508to enable a duty-cycle adjustment at input512.

FIG. 5Bpresents a block diagram of a clock path514which directly incorporates a distributed duty-cycle correction mechanism into one or more clock path circuits. Similarly to clock path500inFIG. 5A, clock path514also includes a DCDL516, an EQ518, and a buffer chain520coupled in series. Note that clock path514can also include additional clock path circuits. In some embodiments, these clock path circuits are CML-based circuits. However, instead of using a single end-point DCC, clock path514uses distributed DCCs integrated with clock path circuits. For example, DCDL516is integrated with a DCC522, EQ518is integrated with a DCC524, and buffer chain520is integrated with a DCC526. Note that in some embodiments one or more clock path circuits are not integrated with a DCC module. For example, in one embodiment, only DCDL516and buffer chain520are integrated with DCC modules. In one embodiment, these distributed DCCs provide an equal amount of duty-cycle corrections; hence, each of the DCCs is responsible for correcting approximately ⅓ of the overall duty-cycle error in clock path514. To achieve this objective, the system can measure the overall duty-cycle error at the end of clock path514, and subsequently compute a common control signal representing ⅓ of the correction amount. All three DCCs can receive this common control signal and then perform an equal amount of duty-cycle correction. Note that this distributed duty-cycle correction technique produces lower accumulated duty-cycle error within clock path514than the end-point correction technique.

FIG. 5Cpresents a block diagram of a clock path528which uses an end-point measurement and distributed duty-cycle correction mechanism. Similarly to clock path514inFIG. 5B, clock path524provides distributed duty-cycle corrections at a series of locations along the clock path. However, instead of providing one DCC for each functional clock path circuit, the embodiment of clock path528treats multiple clock path circuits collectively as a set of serially coupled clock path stages (or “stages”), such as CML stages530-536and one or more additional stages538, and performs distributed duty-cycle corrections on each stage in the set of stages. Note that each functional clock path circuit, such as a DCDL or a buffer chain, can comprise multiple clock path stages, and each clock path stage (or “stage”) can include a simple inverter or a delay element. The set of clock path stages collectively form the clock path. In the embodiment shown, each stage receives a common control signal at its respective differential inputs so that each stage produces an equal amount of duty-cycle correction.

More specifically, a duty-cycle error measurement module540measures the overall duty-cycle error for clock path528at the end of clock path528. Next, a duty-cycle adjustment circuit542generates the common control signal based on the duty-cycle error measured by duty-cycle error measurement module540, wherein the common control signal represents a fraction of the total measured duty-cycle error. For example, if the total measured duty-cycle error is 8% and there are 10 stages involved in the duty-cycle correction, then the common control signal can represent approximately 0.8% of the duty-cycle correction for each stage. Note that inFIG. 5Ca series of feedback paths coupled between duty-cycle adjustment module542and the set of stages apply the common control signal to the differential inputs of these stages. In one embodiment, the common control signal adjusts the differential current source for each CML stage to cause a voltage offset at the outputs of the stage that adjusts the duty-cycle.

While the embodiment illustrated inFIG. 5Cperforms duty-cycle corrections at each stage within clock path528, other embodiments perform distributed duty-cycle corrections at only a subset of the stages, for example, at every other stage instead of every stage. In some embodiments, distributed duty-cycle corrections are only performed on those stages associated with specific clock path circuits. For example, one embodiment performs duty-cycle correction only in stages associated with the DCDL and clock buffers. Note that this distributed duty-cycle correction technique can significantly reduce jitter along the clock path when compared with the end-point correction technique illustrated inFIG. 5A.

FIG. 5Dpresents a block diagram of a clock path544which uses a distributed duty-cycle measurement and correction mechanism. Similarly to clock path528inFIG. 5C, clock path544includes a set of stages, such as CML stages546-552and one or more additional stages554. However, distributed duty-cycle corrections in clock path544are not controlled by a common control signal as inFIG. 5C. Instead, each of the clock path stages uses a separate DCC for duty-cycle error measurement and correction. For example, a dedicated DCC556for stage546includes a duty-cycle error measurement module558which measures an amount of duty-cycle error at the differential outputs of stage546. Dedicated DCC556also includes a duty-cycle adjustment module560which generates a control signal based on the duty-cycle error measured by duty-cycle error measurement module558. This control signal is coupled from duty-cycle adjustment module560to the differential inputs of stage546through a feedback path of DCC556. In one embodiment, the control signal adjusts a differential current source for stage546to cause a voltage offset at the outputs of the stage that adjusts the duty-cycle for stage546. Note that each of the other stages in clock path544is also associated with a dedicated DCC to perform the separate duty-cycle measurement and correction operations for that stage.

The illustrated embodiment of clock path544not only reduces duty-cycle error through a distributed duty-cycle error correction mechanism, but also keeps duty-cycle errors bounded at each stage, thereby increasing resolution in duty-cycle correction by avoiding the non-linear amplification of duty-cycle errors that can occur when such errors become too large. WhileFIG. 5Dillustrates performing duty-cycle measurements and corrections at each stage within clock path544, other embodiments can perform distributed duty-cycle measurements and corrections at only a selected subset of the stages, for example, at every other stage in clock path544. In some embodiments, distributed duty-cycle measurements and corrections are only performed on those stages associated with specific clock path circuits, such as the DCDL and the clock buffers or in a CML to CMOS signaling conversion stage.

Distribution of DCDLs Through Master DCDLs and Micro DCDLs

Master DCDLs602and604remain inserted in the global clock paths122and128that bring a master clock to the multiple data paths. Hence, master DCDLs602and604can be used to compensate for skews that are common for all data paths. For example, master DCDL602can be used to compensate for skews in clock path122caused by buffer chain142, while master DCDL604can be used to compensate for skews in clock path128caused by buffer chain144. In one embodiment, master DCDLs602and604are configured to compensate for a data path having the maximum skew among the multiple data paths.

In contrast, μDCDLs606and608are inserted into local clock paths, such as clock paths134and138, to provide local clock skew compensation for each data bit, such as data bit123. While not explicitly shown, additional pairs of μDCDLs (on both transmitter102and receiver104) are also present at equivalent locations in the local clock paths associated with other data paths in MSSC600. Generally, these μDCDLs compensate for skews which are not corrected by the master DCDLs, thereby providing fine-tuning to the skew associated with a given data bit. For example, these μDCDLs can be used to compensate for “pin-to-pin” skews, i.e., to add additional delays for shorter data links to compensate for skews between shorter data links and longer data links. In some embodiments latter, unused stages of the DCDLs are powered down to minimize power consumption. Note that in these embodiments, power consumption can be reduced by shortening the total delays on the μDCDLs and the longest common delay on the master DCDLs. This can be conveniently calibrated by setting the master DCDL delay (with μDCDL delay set to minimum) to be that of the bit requiring the shortest delay of the parallel data bits, then setting the remaining delay required in the other parallel data μDCDLs.

In some high-speed chip interfaces, a multiplying ILO (MILO) without phase-locking is used to generate higher frequency clock signals from a reference clock signal to facilitate converting parallel data signals into a serial data signal. While absence of phase-locking facilitates achieving a short turn-on cycle time, it is necessary in such systems to retime the input data from the reference clock domain into the faster clock domain.

FIG. 7illustrates a source-synchronous (SS) system700including a MILO for transmitting a serial data signal and an associated clock from a transmitter706to a receiver708over a communication channel710. In particular, the serial data signal and the associated clock are synchronized at the source device to reduce timing skews between the two signals. In one embodiment, SS system700is a simplified version of MSSC system100.

As illustrated inFIG. 7, data702and a reference clock (“ref_clk”)704are inputs to transmitter706, for example, through an interface circuit712within transmitter706. In the embodiment shown, data702is parallel data and data bus703includes a group of parallel channels (shown as the slash on the data path). In some embodiments, data bus703can include a power-of-2 number of channels (e.g., 4, 8, 16 channels, etc.) In one embodiment, the frequency “fref” of ref_clk704is the same as the data rate of each parallel channel within data bus703(e.g. parallel data is edge-triggered off of a single edge into the parallel interface).

A parallel-to-serial circuit714converts parallel data702into serial data716which has a data rate equal to N times the data rate of each parallel channel in data bus703, wherein N is the number of parallel channels in data bus703. We refer to the data rate of serial data716as a “bit rate.” This assumes that parallel data702and serial data716are binary coded data transmitting one bit per symbol, but a similar procedure exists for signaling systems encoding more or less than one bit per symbol, in which case the symbol rate and the bit rate may be different. Serial data716passes through a flip-flop/output multiplexer (OMUX)717and a data buffer719before being transmitted onto data link722. Separately, bit_clk720passes through a flip-flop/OMUX721and a clock buffer723before being transmitted onto clock link724.

In order to provide timing information for serial data716, transmitter706includes a MILO718, which takes ref_clk704as an input and generates a fast clock (referred to as a “bit_clk”)720based on ref_clk704. In one embodiment, the frequency “fbit” of bit_clk720is N times the frequency fref. To provide timing information for parallel-to-serial circuit714, bit_clk720is used to derive a number of slower clocks, which have the frequencies of fbit/2, fbit/4, . . . , and fbit/N, wherein fbit/N equals frefof ref_clk704. These slower clocks which are derived from bit_clk720may be referred to as “div2_clk,” “div4_clk,” . . . , “divN_clk” in accordance with their respective frequencies, for example, div2_clk has the frequency fbit/2. Note that these derived slower clocks may be substantially phase-aligned with bit_clk720. In some embodiments, each of the clock edges within a derived slower clock is substantially aligned with a clock edge in bit_clk720. In some embodiments the derived slower clocks may be phase-aligned but delayed slightly by the Clk to Q of the particular divider circuitry used.

Note that in some embodiments, the input clock (ref_clk704) and the output clock (bit_clk720) of MILO718are not contained in a feedback loop that locks the output clock to a reference clock and therefore fast locking behavior is achieved. Furthermore, when MILO718is turned on, an undetermined (but limited) number of cycles may occur on bit_clk720before the clock has substantially stabilized to its steady state amplitude and phase. Therefore, both because ref_clk704and bit_clk720have an unknown phase-relationship and because of this lack of determinism in the startup of the MILO, while the derived clocks div2_clk, div4_clk, . . . , etc. have a known phase relationship with respect to bit_clk720, they may have an unknown phase-relationships with respect to ref_clk704. Moreover, in the embodiment shown, transmitter706does not include a phase-alignment mechanism (e.g., a PLL module or a DLL module) to perform a phase-alignment between ref_clk704and bit_clk720, or between any of the derived clocks div2_clk, div4_clk, . . . , and ref_clk704.

Note that eliminating a slow phase-locking process facilitates a rapid transitioning of SS system700from a power-off state to a power-on state. However, the phase-relationship between ref_clk704and bit_clk720or any of the derived clocks div2_clk, div4_clk, . . . , is an unknown and may change value each time SS system700is transitions from an idle to an active state, most typically when the MILO is turned on and relocked.

Circuit714also includes a retiming mechanism (not shown) which synchronizes serial data716with bit_clk720. In one embodiment, this synchronization can be achieved by retiming parallel data702using the divN_clk prior to performing the parallel-to-serial conversions in circuit714. Note that the divN_clk is a mesochronous clock (same frequency, indeterminate phase) with respect to ref_clk704. After parallel data702are retimed into the divN_clk domain, the parallel-to-serial conversion which uses the derived slower clocks and optionally bit_clk720can be safely performed, and as a result, input data702can be correctly retimed and serialized from the domain of ref_clk704into the domain of bit_clk720. Finally, serial data716and bit_clk720are transmitted over channel710(through data link722and clock link724, respectively) to receiver708.

FIG. 8provides a timing diagram illustrating the risk involved in retiming a data signal from a first clock domain to a second clock domain when the two clock domains have an unknown phase-relationship. In reference to the embodiment illustrated inFIG. 7, data802inFIG. 8is an exemplary embodiment of data702inFIG. 7, clock804is an exemplary embodiment of ref_clk704inFIG. 7, and clock808is an exemplary embodiment of divN_clk inFIG. 7.

As illustrated inFIG. 8, data802is timed using clock804such that a rising edge transition (e.g., clock transition805) of clock804generates a data transition (e.g., data transition806) in data802. At this point, data802is in the domain of clock804. Also shown inFIG. 8is a mesochronous clock808of clock804, wherein the phase-relationship between the two clocks is unknown. In some embodiments, clock808is used to retime data802from the domain of clock804to the domain of clock808.

Shadowed region810inFIG. 8represents an unsafe region of data802for retiming data802with respect to clock808. Specifically, region810is a region centered around data transition806where the data value may be in transition and could be uncertain. In other words, when sampling data802in the vicinity of data transition806, the sampled value is uncertain. Sampling the data at such a point could lead to metastability in an output flip-flop. For example, in this region non-idealities such as jitter on clock804or clock808or skew on data802can cause an error in the data sampling. As is illustrated inFIG. 8, in the first instance of clock808, a rising edge transition812(assuming rising edge triggered flip-flops are used for the retiming operation) falls within unsafe region810. In such instances, it is unsafe to retime data802directly using clock808.

Note that the boundaries of an unsafe region may vary for different links, and under different operation environments. In one embodiment, the unsafe region is defined by two boundaries surrounding a data transition region, wherein each boundary has a phase distance from the center of the data transition region greater than a threshold phase value. For example, in one embodiment, the unsafe region is defined by two boundaries located −30° and 30° from the center of a data transition (defined as 0°) in data802. In one embodiment, this threshold phase value may be calibrated based on a bit error rate (BER) value, and the threshold phase value represents a location where the BER becomes consistently acceptable.

Because data802has periodic unit intervals (UI) for each bit, each interval can be divided into an unsafe region and a safe region. For example, when the unsafe region for retiming data802using clock808varies between −30° and 30° with respect to a data transition, the safe region for retiming data802includes the remainder of the UI between 30° and 330° with respect to the same data transition. As is illustrated inFIG. 8, in the second instance of clock808, a rising edge transition814(assuming rising edge triggered flip-flops are used) falls within safe region816between two unsafe regions810and818. In such instances, it is safe to retime data802using clock808directly. Note that the safe regions and unsafe regions are interleaved with the same period as clock804or clock808.

Note that the size of an unsafe region may also have an upper bound. Because the retimed data value becomes increasingly more deterministic when a sampling edge (e.g., clock transition812of clock808) is further away (including in both directions) from the center of the data transition, at a certain phase distance from the data transition, the unsafe region crosses into the safe region. One may choose a location in the safe region well beyond the threshold phase value described above as the upper bound of the unsafe region. For example, in one embodiment, the unsafe region may be defined by two boundaries located between −90° and 90° from the center of data transitions in data802. In this embodiment, the safe region for retiming data802is located between 90° and 270° from the same data transition, and hence has the same size as the unsafe region. Note that, if the safe region and the unsafe region for each UI have substantially the same size, (i.e., each is approximately 180°, which can conservatively be defined if the true unsafe region is less than or equal to 180°), it becomes possible to determine whether a sampling edge is within the safe region or the unsafe region by using a binary relative clock phase detector. As the data and clocks are essentially mesochronous to each other as long as retiming flip-flops with adequate performance are used, there will generally be a significant overlap region between the two clock domains where data can be successfully retimed with a latch or sampled with an edge-triggered flip-flop.

FIG. 9Aillustrates a logic circuit900for determining whether a phase-relationship between a first clock902and a second clock904is within an unsafe region for retiming a data signal using the second clock904. It is assumed that the data signal has been previously retimed using clock902, and that clock902and clock904have an unknown phase-relationship.

In the embodiment shown inFIG. 9A, logic circuit900includes a sampling circuit901, wherein clock904is the sampling clock and clock902is the input to sampling circuit901. The clock path of clock904also includes a delay module906which causes a predetermined delay tdto clock904. Next, the delayed clock904′ is used to sample clock902.

FIG. 9Billustrates a timing diagram910associated with logic circuit900which describes the operation of circuit900. Note that, if no delay tdis added to clock904, sampling circuit901outputs logic value 1 when a rising edge transition (e.g., clock transition912) of clock904falls within the half cycle914of clock902associated with logic high, and outputs logic value 0 when a rising edge transition of clock904falls within the half cycle916of clock902associated with logic low (for simplicity, this neglects internal delay in sampling circuit901itself, which can easily be included). However, as explained inFIG. 8, half cycles914and916often do not provide useful representations of safe regions and unsafe regions. This is because an unsafe region as described above is a region encompassing a rising edge transition of clock902, whereas both half cycles914and916are equivalently positioned on either side of a rising edge transition of clock902.

As illustrated inFIG. 9B, by adding delay tdto clock904and using the delayed clock904′ to sample input clock902, sampling circuit901outputs logic value 1 when a rising edge transition (e.g., delayed clock transition912′) of delayed clock904′ falls within the half cycle914of clock902, and outputs logic value 0 when a rising edge transition of delayed clock904′ falls within the half cycle916of clock902. Moreover, the output value 1 corresponds to when a rising edge transition of clock904(e.g., clock transition912) falls within a phase-shifted half cycle918defined by boundaries [−td; −td+180°] with respect to a rising edge transition of clock902. In contrast, an output value 0 corresponds to when a rising edge transition of clock904falls within a phase-shifted half cycle920defined by boundaries [−td+180°; −td+360°] with respect to a rising edge transition of clock902. Note that the region defined by [−td; −td+180°] can be made to encompass a rising edge transition of clock902if delay tdis carefully selected. Moreover, delay tdcan also be used to compensate for the different setup and hold times between the clock paths of clock902and clock904.

For example, when td=30°, the two half-cycle regions corresponding to the output logic values of 1 and 0 become [−30°, 150°] and [150°, 330°], respectively. Note that this example is similar to the first instance of clock808described inFIG. 8, wherein [−30°, 30°] and [30°, 330°] correspond to the unsafe region and the safe region, respectively. In this example, logic circuit900can be used to determine that clock transition912is in an unsafe region when sampling circuit901outputs logic 1, and that clock transition912is in a safe region if sampling circuit901outputs logic 0. In another example, when td=90°, the two half-cycle regions corresponding to the output values of 1 and 0 become [−90°, 90°] and [90°, 270°], respectively. Note that these two phase regions match the unsafe region and safe region described in the second instance of clock808inFIG. 8. Similarly, logic circuit900can be used to determine that clock transition912is in an unsafe region when sampling circuit901outputs logic 1, and that clock transition912is in a safe region when sampling circuit901outputs logic 0. In this manner, logic circuit900can be used to determine whether clock904is in the unsafe region or the safe region to retime the data signal based on the outputs of sampling circuit901.

Note that by using logic circuit900, each clock cycle can be divided into a half cycle which is safe for data retiming based on the retiming clock and the other half cycle which is unsafe for data retiming based on the retiming clock. Also note that, when a transition of the retiming clock is in the unsafe half cycle, the opposite transition of the retiming clock is in the safe half cycle.

FIG. 10presents a circuit1000illustrating an exemplary embodiment of transmitter706inFIG. 7, which includes a mechanism for retiming a data signal from a first clock domain to a second clock domain where the two clock domains have an unknown phase-relationship.

As illustrated inFIG. 10, circuit1000receives parallel data1002and reference clock (“ref_clk”)1004having a frequency of fref. Data1002is then phase-realigned with ref_clk1004, for example, using a rising edge triggered flip-flop1006, which produces phase-realigned data1002′. Note that ref_clk1004is also used to generate a fast clock (“bit_clk”)1008having a frequency of fbitthrough a MILO1010without a phase detector. As a result, bit_clk1008has an unknown phase-relationship with respect to ref_clk1004. As such, bit_clk1008is in a different clock domain from ref_clk1004.

Circuit1000includes a parallel-to-serial circuit1012which receives parallel data1002′ and bit_clk1008and converts parallel data1002′ into serial data1014based on bit_clk1008. More specifically, bit_clk1008, which is a fast clock, is used to generate new clocks with fractional frequencies. For example, parallel-to-serial circuit1012can include a frequency divider1016which receives bit_clk1008as an input. In one embodiment, frequency divider1016comprises a set of serially coupled divide-by-2 frequency dividers which sequentially generate clocks with fractional frequencies of fbit/2, fbit/4, . . . , fbit/N, wherein fbit/N equals fref. For example, when MILO1010produces bit_clk1008which has a frequency of fbit=8×fref, frequency divider1016can include three serially coupled divide-by-2 frequency dividers to sequentially generate clocks with frequencies of fbit/2, fbit/4, and fbit/8=fref. Note that new clock (“div_clk”)1018with frequency frefcan be a mesochronous clock with respect to ref_clk1004. In one embodiment, all derived clocks, including div_clk1018, are substantially phase-aligned with bit_clk1008, or have approximately static phase offsets relative to bit_clk1008, and hence are not phase-locked to data1002′. However, bit_clk1008and each of the derived clocks from bit_clk1008are considered to be in the same clock domain.

As illustrated inFIG. 10, div_clk1018is the primary clock which is used to retime parallel data1002′. In order to retime data1002′ from the domain of ref_clk1004to the domain of div_clk1018, parallel-to-serial circuit1012provides a mechanism to determine whether div_clk1018is in the unsafe region or the safe region for retiming data1002′ according to the discussions in conjunction withFIGS. 8 and 9. In the illustrated embodiment, a “skip” circuit1020is provided to determine the relative phase-relationship between ref_clk1004and div_clk1018. Skip circuit1020generates a skip bit1022, wherein a value of 1 indicates div_clk1018is in the unsafe region and a value of 0 indicates div_clk1018is in the safe region. While logic circuit900inFIG. 9provides an exemplary embodiment of skip circuit1020, other embodiments of skip circuit1020which can produce the equivalent skip bit1022can be used for skip circuit1020.

Additionally, parallel-to-serial circuit1012provides two independent data paths for data1002′: a first data path1024which is selected when it is safe to directly retime data1002′ using div_clk1018and a second data path1026which is selected when it is unsafe to directly retime data1002′ using div_clk1018.

More specifically, data path1024simply passes data1002′ to the retiming portion of parallel-to-serial circuit1012; whereas data path1026delays data1002′ and then passes the phase-delayed data1028to the retiming portion of parallel-to-serial circuit1012. In one embodiment, data path1026uses a delay element1030to delay data1002′ relative to ref_clk1004by one half of a cycle of ref_clk1004. For example, delay element1030can include a falling edge triggered flip-flop or other types of latch circuits which are falling edge triggered. Because data transitions in data1002′ are generated by the rising edge transitions of ref_clk1004, retiming data1002′ using the falling edge transitions of ref_clk1004causes a 180° phase delay of data1002′ relative to ref_clk1004. As described in conjunction withFIGS. 8 and 9, the 180° phase-delay to data1002′ causes a rising edge transition of div_clk1018to relocate from the unsafe region to the safe region for retiming purposes. Note that while the embodiment above adjusts the phase of data signal1002′ relative to the phase of div_clk1018, it is also possible to adjust the phase of div_clk1018relative to the phase of data signal1002′ so that the phase-relationship between data signal1002′ and the phase-adjusted div_clk1018is within a safe range for retiming data signal1002′ using the phase-adjusted div_clk1018. This can be accomplished fairly easily by use of the higher frequency bit_clk1008.

Moreover, both data paths1024and1026are the inputs to a multiplexer (MUX)1032, which receives skip bit1022of skip circuit1020as the selection signal. Hence, when div_clk1018is safe for retiming data1002′ (i.e., skip bit=0), MUX1032chooses data path1024, i.e., the original data1002′ as the output. Otherwise (i.e., skip bit=1), MUX1032chooses data path1026, i.e., phase-delayed data1028as the output. In both cases, it becomes safe to retime the output data from MUX1032using div_clk1018at retiming circuit1034. The retimed parallel data1036is now in the domain of div_clk1018. Next, a serializer1038converts the retimed parallel data1036into serial data1014. In one embodiment, serializer1038is a pipelined converter which sequentially multiplexes parallel data channels by a factor of two until all parallel data channels are combined into a signal data channel. In this embodiment, each pipeline stage in serializer1038is synchronized to an increasingly faster derived clock from bit_clk1008, and the final serial data1014is synchronized to bit_clk1008at the highest bit rate.

Note that circuit1000and hence transmitter706inFIG. 7automatically determine the phase-relationship between a reference clock and a mesochronous clock generated from the reference clock but in a different clock domain from the reference clock each time the associated communication system is transitioned from a power-off state to a power-on state. More specifically, skip bit1022is re-evaluated each time the system is powered on by comparing the phases of the reference clock and the mesochronous clock, and a new data path1024or1026is reselected.

In some embodiments, each time when skip bit1022is being re-evaluated, input data1002does not become active until after a predetermined number of reference clock cycles has elapsed in order to allow for skip circuit1020to complete skip bit calculation first. Moreover, because no data is being transmitted during skip bit calculation, the forwarded clock on the clock path accompanying data1014should also be idle. In other words, toggle flip-flop1040does not start to toggle until a clock cycle of bit_clk1008corresponding to the first data bit of data1014is sent. In one embodiment, this can be achieved by replacing toggle flip-flop1040with a copy of parallel-to-serial circuit1012, wherein the input data of this replacement circuit is configured to start at “all-zeros,” and then switch to a “1010 . . . ” pattern at the moment when a clock cycle of ref_clk1004corresponding to the first parallel data1002appears on the clock path. In some embodiments, the first edge of ref_clk1004used to start injection into MILO1010is the first edge also used to sample parallel data1002.

In some embodiments the use of frequency divider1016at the end of a power-on burst will leave the counters in an indeterminate state. In some embodiments, the dividers in frequency divider1016are reset upon each power-down event so that when a fast power-up is executed they will start from a determinate state.

FIG. 11presents a flowchart illustrating a process of retiming a data signal from a first clock domain to a second clock domain wherein the two clock domains have an unknown phase-relationship.

During operation, a chip signaling interface receives the data signal and the first clock signal which have a known phase-relationship between each other (step1102). While the data signal and the first clock signal may be phase-locked when received, the chip signaling interface may further use the received first clock signal to retime the received data signal, for example, by using a rising edge triggered latch circuit. In doing so, the rising edge transitions of the first clock signal regenerate the data transitions in the retimed data signal.

Next, a second clock signal is generated based on the first clock signal, wherein the second clock signal has an unknown phase-relationship with respect to the first clock signal and the data signal (step1104). In one embodiment, the second clock signal and the first clock signal are mesochronous, i.e., having the same frequency but an unknown phase-relationship.

A logic circuit is then used to determine whether the phase-relationship between the data signal and the second clock signal is safe for retiming the data signal using the second clock signal (step1106). In one embodiment, the logic circuit is configured to determine whether the phase-relationship between the data signal and the second clock signal is safe for retiming by determining whether a sampling edge of the second clock signal is located outside of a predetermined phase distance from a sampling edge of the first clock signal, wherein the sampling edge of the first clock signal is used to generate a data transition in the data signal. In one embodiment, the predetermined phase distance is less than or equal to 90°.

FIG. 12presents a flowchart illustrating a process for determining whether a sampling edge of the second clock signal is located within or outside of a predetermined phase distance from a sampling edge of the first clock signal.

During operation, a delay module is used to first delay the sampling edge of the second clock signal by the predetermined phase distance (step1202). A sampling circuit then samples the first timing signal using the delayed sampling edge of the second clock signal (step1204). If the sampling output equals 1, the process determines that the sampling edge of the second timing signal is located within the predetermined phase distance from the sampling edge of the first clock signal (step1206). If the sampling output equals 0, the process determines that the sampling edge of the second timing signal is located outside of the predetermined phase distance from the sampling edge of the first clock signal (step1208).

Referring back toFIG. 11, if the logic circuit determines that the phase-relationship between the data signal and the second clock signal is not safe for retiming the data signal using the second clock signal, a phase-adjustment circuit is used to adjust the phase of the data signal so that the phase-relationship between the phase-adjusted data signal and the second clock signal is within a safe range for retiming the phase-adjusted data signal using the second clock signal (step1108). In one embodiment, the phase-adjustment circuit adjusts the phase of the data signal by delaying the data signal relative to the first clock signal by one half of a clock cycle of the first clock signal. Note that in step1108it is also possible to adjust the phase of the second clock signal so that the phase-relationship between the data signal and the phase-adjusted second clock signal is within a safe range for retiming the data signal using the phase-adjusted second clock signal. A retiming circuit subsequently retimes the phase-adjusted data signal using the second clock signal (step1110). On the other hand, if the logic circuit determines that the phase-relationship between the data signal and the second clock signal is safe for retiming the data signal using the second clock signal, the retiming circuit directly retimes the data signal using the second clock signal (step1112). In both cases, the data signal is safely retimed into the second clock domain.

In one embodiment, SS system700can be configured as a memory system such that transmitter706is configured as part of a memory controller and receiver708is configured as part of a memory device. In this embodiment, memory system700can be used to perform fast write transactions using the single transmitter-side MILO718. In some embodiments, read transactions from a memory device can also be accommodated in a fully matched source-synchronous manner by placing a fast clock multiplier (e.g., a MILO) on the memory controller. Note that in these embodiments, the transmitter is on the memory device, and the fast clock multiplier is on the receiver, which itself is on the memory controller.

FIG. 13illustrates an embodiment of an MSSC memory system1300which uses a single controller-side MILO1306and a return clock. More specifically, memory controller1302of MSSC memory system1300uses MILO1306to generate a bit clock bit_clk1308based on a reference clock ref_clk1310. Memory controller1302then forwards bit_clk1308via a first clock link1311to memory device1304of MSSC memory system1300. Memory device1304receives bit_clk′1312which is the delayed bit_clk1308, and subsequently transmits bit_clk′1312and read data1314back to memory controller1302via a second clock link1313and a bi-directional data link1315, respectively. Note that memory system1300includes a controller-side DCDL1316which can be configured to compensate for skews between the forward data and clock paths, such as those caused by clock buffers1318. Similarly, it also includes a memory device DCDL1320to compensate for controller clock buffer skew1322. Such DCDLs can, in some embodiments, be split into ‘master’ and ‘μDCDU’ structures as has been previously discussed to minimize power.

The embodiment of MSSC memory system1300circulates the receive clock on the memory device by using the same clock as the transmit clock from the memory device. One problem which can arise from this scheme is accumulation of high-frequency jitter via clock recirculation on the memory device. However, memory system1300can use a memory-side DCDL1320on the return path of memory system1300to compensate for skews between the return data and clock paths, such as those caused by clock buffers1322, thereby creating a matched-source-synchronous return path. Consequently, the impact from this increased high-frequency jitter can be significantly mitigated. While the embodiment of memory system1300describes placing a single MILO on the memory controller, i.e., the receiver-side for reads, some embodiments can place a single MILO on the memory device, i.e., the transmitter-side, instead of the memory controller.

In some embodiments, read transactions from a memory device can also be accommodated in a fully matched source-synchronous manner by placing fast clock multipliers (e.g., MILOs) on both the memory controller and memory device.FIG. 14illustrates an embodiment of an MSSC memory system1400which uses MILOs on both the memory controller and the memory device. As illustrated inFIG. 14, matched MILOs1406and1408are placed on memory controller1402and memory device1404, respectively. Each of the MILOs1406and1408receives a respective reference clock ref_clk1410and ref_clk1412(which can have arbitrary phase between each other), and generate a respective bit clock bit_clk1414and bit_clk1416. Moreover, controller-side MILO1406receives a “fast-power-on” input1418, which is also sent from memory controller1402to memory device1404as a “fast-wakeup” input1420to MILO1408. In this embodiment, each read transaction can operate with as much timing margin as write transactions (e.g., being fully source-synchronous and symmetric to the write operations). In some embodiments, the reference clocks ref_clk1410and ref_clk1412received by the two devices1402and1404can be from different sources, as can the ‘power on’ and ‘wakeup’ signals1418and1420.

In one embodiment, a controller-side DCDL1422and a memory-side DCDL1424can be used to compensate for skews caused by clock buffers1426and1428and by other sources in the similar manner as in memory system1300. While embodiment of memory system1400uses two unidirectional clock links1430and1432, some embodiments can use one bidirectional clock link to transmit both bit_clk1414and bit_clk1416to save device pins but with a trade-off of incurring additional turnaround latency. These embodiments may also help to compensate for the cost of more device pins as both controller and memory devices now need a separate reference clock input. A similar tradeoff can be made on the data links in embodiments of1300or1400where the data links can be made either unidirectional or bidirectional in order to properly balance the tradeoffs between turn-around latency and pin-count.

Clock Multiplier Based on a MILO

FIG. 15Aillustrates a MILO in accordance with embodiments described herein. The MILO illustrated inFIG. 15Aincludes pulse-generator-and-injector1502, and injection-locked oscillators1504and1506.

Pulse-generator-and-injector1502can include pulse generators1520and1522, and delay elements P1-P4. Pulse generator1520can receive reference signal1510and generate a first sequence of pulses which can be provided as input to pulse generator1522. The number of edges in the first sequence of pulses can be twice the number of edges in reference signal1510over the same time period. Pulse generator1522can then generate a second sequence of pulses that has twice the number of edges than the number of edges in the first sequence of pulses over the same time period. In this manner, the output signal of pulse generator1522can have four times the number of edges in reference signal1510over a given time period.

The output of pulse generator1522can then be provided as input to the delay chain comprising delay elements P1-P4. As shown inFIG. 15A, the output signals from delay elements P1-P4can be injected into corresponding delay elements R11-R14of injection-locked oscillator1504. In some embodiments the design of delay elements P1-P4matches that of delay elements R11-R14in order for the injection pulses to arrive at the same relative phase at delay elements R11-R14.

In some embodiments described in this disclosure, the sequence of pulses generated by pulse generator1522may not have equal widths and/or may not have the same amplitude. These variations in the width and/or amplitude of the pulses can show up as deterministic jitter in the output signals from injection-locked oscillator1504. In some embodiments, the amount of deterministic jitter in the output signals can be reduced by adding more injection-locked oscillator blocks to the MILO. Specifically, in some embodiments, the output signals from injection-locked oscillator1504can be injected into corresponding injection points in another injection-locked oscillator, e.g., a non-multiplying injection-locked oscillator1506. Specifically, as shown inFIG. 15A, the outputs from delay elements R11-R14of injection-locked oscillator1504can be injected into corresponding delay elements R21-R24of injection-locked oscillator1506.

In some embodiments described herein, the output signals from delay elements R21-R24can be used to generate the output of the MILO. Specifically, in some embodiments, the output signal from one of the delay elements in the last injection-locked oscillator can be output as the MILO's output signal. For example, as shown inFIG. 15A, the output from delay element R22can be output as the MILO's output signal1524. In some embodiments other outputs in the delay chain can be used, and in some embodiments all outputs can be used to provide separately spaced vectors for interpolation, edge detection, or other purposes.

In some embodiments described herein, the delay elements in the injection-locked oscillators can use differential signals. However, differential signals have not been shown inFIG. 15Afor the sake of clarity and ease of discourse.

FIG. 15Billustrates a 4-stage injection-locked oscillator in accordance with embodiments described herein.

Injection-locked oscillator1504can include delay elements R11-R14arranged in a loop. As shown inFIG. 15B, each delay element can receive and output differential signals. In some embodiments, one or more stages of the injection-locked oscillator may invert the signal. For example, as shown inFIG. 15B, the differential outputs of delay element R14are provided to the opposite polarity inputs of delay element R11(e.g., the “+” and “−” outputs of delay element R14can be coupled with the “−” and “+” inputs of delay element R11, respectively).

FIG. 15Cillustrates a delay element of an injection-locked oscillator in accordance with embodiments described herein. The delay element illustrated inFIG. 15Ccan correspond to a delay element shown inFIG. 15B, e.g., delay element R11.

The delay element shown inFIG. 15Ccan include differential transistor pair M1and M2which can receive the differential input signal SINandSINas input, and differential transistor pair M3and M4which can receive the differential injection signal INJ andINJas input. Transistors M5and M6can act as current sources for the differential pairs, and their currents can be controlled by bias signals SBIASand INJBIAS′, respectively. RL1and RL2can be load resistances, and VDDcan be the supply voltage. The differential output signal SouTandSOUTcan be based on the sum of the drain currents of the corresponding transistors in the differential pairs. Specifically, output signal SOUTis based on the sum of the drain currents of transistors M2and M4, and output signalSOUTis based on the sum of the drain currents of transistors M1and M3.

The injection strength can be modified by adjusting the strength of SBIASand INJBIASrelative to one another. For example, injection strength can be increased by increasing INJBIASand/or decreasing SBIAS. Conversely, injection strength can be decreased by decreasing INJBIASand/or increasing SBIAS. In some embodiments, the total current into the load is maintained at a constant level, i.e., a constant swing is developed across SOUTandSOUT. In some embodiments, the injection strength used for injecting the sequence of pulses into injection-locked oscillator1504is greater than the injection strength used to inject the output of injection-locked oscillator1504into injection-locked oscillator1506.

FIG. 15Dillustrates waveforms associated with the MILO shown inFIG. 15Ain accordance with embodiments described herein. The differential signal waveforms shown inFIG. 15Dare for illustration purposes only, and are not intended to limit the scope of the described embodiments.

Although the MILO and ILO embodiments described in the preceding figures and text are ring-based, in alternate embodiments such MILO and ILO blocks can be implemented as one or more inductor capacitor (LC) type oscillators.

In MSSC system100, further power savings can be achieved by gating the clock signal. Clock gating can be performed in MSSC system100globally at the root of the clock distribution network or locally at selected locations within the clock distribution network which are associated with individual data paths in the system. If clock gating is performed globally, clock gating may be applied to the master clock bit_clk118by inserting clock gating logic between the output of clock multiplier114and node124. On the other hand, when clock gating is performed locally, clock gating logic may be inserted within a local clock path. For example, to selectively gate the clock to data path111, clock gating logic may be inserted in both local clock path134on the transmitter side and local clock path138on the receiver side. While the following discussion focuses on techniques for gating a CML clock, the embodiments described below are applicable to general clock gating operations within MSSC system100. In one embodiment, the main clock ref_clk120in MSSC system100can be a CML clock received from a CML clock source.

According to an embodiment, a high-speed clock distribution system uses a low-swing CML clock signal generated by a CML clock source as the input clock, because such a clock signal generally has a low PSIJ sensitivity. In such systems, power savings can be achieved by gating the CML clock signal (i.e., selectively turning on and off the clock distribution) with a synchronous gate signal. In one embodiment, the clock gating operation is performed by a CML multiplexer which receives the CML clock signal as a data input, and the gate signal as the select input. However, the clock gating operation can be performed by other clock gating means.

In some embodiments, the gate signal is the output of a digital logic (e.g., a high-speed finite state machine (FSM)) built in CMOS technology to achieve higher power efficiency. As a result, the gate signal has a full-swing CMOS level. Moreover, the digital logic generating the gate signal is often in a reference clock domain which is associated with a low timing resolution. Because the CMOS gate signal and the CML clock signal are generated from different clock domains, a finite delay often exists between these two signals. Consequently, when synchronous clock gating is necessary, such as in MSSC system100, it can be challenging for the CMOS gate signal to start at exactly the right time/phase as required for a glitch-free gated clock. This problem is illustrated inFIG. 16, which illustrates timing relationships between a CML clock signal and a CMOS gate signal in both an asynchronous case and a synchronous case.

As illustrated inFIG. 16, an exemplary CML clock signal clk_in1602is a high-speed, low-swing input clock to a clock distribution network. In the asynchronous case1604, an exemplary gate signal gate1606is a CMOS signal which comprises an opening1608. In the discussion below, the terms “clock gate,” “opening,” “window” and “enable window” are used interchangeably to refer to an enabled time interval in the gate signal which is defined between a rising edge transition (also referred to as “the beginning”) and a falling edge transition (also referred to as “the end”). For example, the beginning of opening1608is a rising edge transition1610and the end of opening1608is a falling edge transition1612. Moreover, because a transition can have a finite width, when making a reference to a transition in the following discussion (including rising edge transitions, falling edge transitions, data transitions, clock transitions, and other types of signal level transitions), reference to an approximate middle of that transition is implied.

Note that both transition1610and transition1612are associated with a band of uncertainty, which is shown as a set of parallel dashed lines. As such, the beginning of opening1608is not phase-aligned with clk_in1602. The asynchronous phase relationship between clk_in1602and gate1606produces an output clock clk_out1614which includes a glitch1616and a narrow pulse1618.

Also illustrated inFIG. 16is a synchronous case1620, wherein an exemplary gate signal gate1622comprises an enable window1624that is synchronized to clk_in1602. More specifically, the beginning of window1624(i.e., rising edge transition1626) is phase-aligned with clk_in1602at a location marked by dashed line1628, and the end of window1624(i.e., falling edge transition1630) is phase-aligned with clk_in1602at a later location marked by dashed line1632. Note that both dashed lines1628and1632mark an approximate midpoint in the logic low half of the clock cycle. The synchronous phase relationship between clk_in1602and gate1622produces an output clock clk_out1634which is free of glitches or narrow pulses.

FIG. 17Aillustrates a circuit1700which includes a synchronization mechanism for phase-aligning a CMOS gate signal generated in a CMOS reference clock domain to a CML clock signal generated in a CML clock domain. In an embodiment, circuit1700provides an open-loop synchronization mechanism which does not require a PLL or a DLL.

In the embodiment shown inFIG. 17A, circuit1700receives both a CML clock signal clk_in1702and a CMOS gate signal gate01704. Circuit1700includes a flip-flop1706which receives gate01704as a data input and a 180° phase-inverted version of clk_in1702as the clock input. In a particular embodiment, flip-flop1706is configured as a negative edge triggered flip-flop so that when clk_in1702transitions from high to low, gate01704is sampled and propagated to the output of flip-flop1706as a retimed CMOS gate signal gate11708. Circuit1700also includes a clock gating block in the form of a CML multiplexer (MUX)1710, which receives clk_in1702as a data input and gate11708, which is now phase-aligned with clk_in1702, as a select input. As such, MUX1710outputs a gated CML clock signal clk_out1712without glitches or narrow pulses. Note that the clock gating function in circuit1700may be implemented in other means different from MUX1710.

In one embodiment, flip-flop1706includes at least one CMOS-CML hybrid latch configured to operate with both CMOS level data signals and CML level clock signals, thereby allowing gate01704in the CMOS level to be synchronized to clk_in1702in the CML level. An exemplary design of a hybrid flip-flop is described below in conjunction withFIG. 18.

FIG. 17Bpresents a timing diagram illustrating a phase relationship and time constraints between the CML input clock clk_in1702and the retimed CMOS gate signal gate11708inFIG. 17A. As illustrated inFIG. 17B, a falling edge transition1720in clk_in1702triggers the beginning of an enable window in gate01704(not shown) to cross the clock domain from the CMOS clock domain to the CML clock domain. This produces a delayed (relative to transition1720) beginning (i.e., transition1724) of an enable window1722which is substantially phase-aligned with a desired location in clk_in1702. In the embodiment shown, this desired location is approximately ¼ of one CML clock period (TClkPERIOD) from the middle of transition1720or in the middle of the logic low half cycle of clk_in1702. This requirement provides a timing constraint for the flip-flop design, which can be expressed as:
TC-Q,HybridFF≈¼(TClkPERIOD),
wherein TC-Q,HybridFFis the clock to data output delay of flip-flop1706, measured from a triggering event (e.g., transition1720) to the time when the flip-flop output switches.

Similarly,FIG. 17Balso shows that a second falling edge transition1726in clk_in1702triggers the end of the enable window in gate01704(not shown) to cross the clock domain from the CMOS clock domain to the CML clock domain. This produces a falling edge transition1728in gate11708to mark the end of window1722, wherein transition1728is substantially delayed by ¼ of TClkPERIODfrom transition1726to satisfy the above-described timing constraint. Note that window1722can have an opening duration equal to multiple (e.g., 4, 8, 16, etc.) TClkPERIOD. Consequently, a properly designed flip-flop1706allows synchronizing the CMOS gate signal to the CML input clock. The retimed clock gate11708is subsequently used to gate the input clock clk_in1702to generate a glitch-free CMOS output clock clk_out1712. Note that the design of synchronizing circuit1700provides a direct and fast open-loop solution to achieve glitch-free clock gating. Because no feedback is used in circuit1700, substantial power saving is also achieved when compared to feedback-based techniques.

FIG. 18illustrates an exemplary implementation of a hybrid flip-flop1800for synchronizing a CMOS input signal with a CML clock signal. The hybrid flip-flop illustrated inFIG. 18can correspond to hybrid flip-flop1706inFIG. 17A.

As illustrated inFIG. 18, hybrid flip-flop1800comprises two substantially identical hybrid latches1802and1804cascaded in a manner similar to a conventional master-slave flip-flop. Note that each of the latches receives full-swing CMOS data input and low-swing differential CML clock inputs, and generates full-swing CMOS data output. In one embodiment, hybrid latches1802and1804are “level sensitive” such that each of the latches buffers CMOS input D/Dfrom the data input to the data output Q/Qwhen low-swing differential CML clock inputs CLK/CLKare differentially high, and regenerates Q/Qwhen the differential CML clock inputs CLK/CLKare differentially low. One difference between a conventional clocked regenerative latch and the hybrid latches illustrated inFIG. 18is that the hybrid latches operate with low-swing differential CML clocks. In other words, a conventional latch is generally “level sensitive” when the input clocks have rail-to-rail CMOS swings, while each of the hybrid latches inFIG. 18is “level sensitive” to a typical differential CML clock signal.

FIG. 18also illustrates a detailed transistor level implementation1806of each of the latches1802and1804. More specifically, within hybrid latch1806, the top-outer four transistors M1, M2, M3, and M4coupled to CMOS inputs D/Dform an amplification stage, while the top-inner four transistors M5, M6, M7, and M8are cross-coupled to form a latching stage. In one embodiment, transistors M1-M8are low threshold voltage (LVT) devices. Below those two stages is the differential clock input stage comprising transistors M9and M10coupled to CLK/CLK. In one embodiment, transistors M9and M10are regular threshold voltage (RVT) devices. Further below the clock inputs is the enable signal (EN) input which operates at full-swing CMOS level.

In one embodiment, each of the hybrid latches1802and1804is constructed such that the low-swing CLK/CLKsignals are able to toggle the dominance between the outer buffering branch (e.g., the amplification stage in hybrid latch1806) and the inner regenerative branch (e.g., the latching stage in hybrid latch1806) when CLK/CLKare differentially high and low. To achieve the above function, the transistors in the hybrid latches can be sized so that: (1) without the ability to completely turn off the inner branch, Q/Qwould follow D/Dwhen CLK/CLKare differentially high; and (2) without the ability to completely turn off the outer branch, the inner branch regenerates Q/Qwhen CLK/CLKare differentially low. Note that cascading two identically hybrid latches in series with CLK/CLKconnection reversed between them results in a hybrid flip-flop that behaves like a master-slave flip-flop, but with the additional benefit of the ability to use low-swing differential CML input clocks.

Referring back toFIG. 17A, note that while the simple design of circuit1700provides the basic function of aligning the CML clock signal and the CMOS gate signal, the particular design does not fully address the following issues when the gate signal crosses clock domain directly. First, the gate signal is typically generated from a digital domain that is often associated with a much larger clock period than the CML clock period. As such, each opening duration (“the duration” hereinafter) of the gate signal is often much longer than one CML clock period, and hence offers only a coarse duration control. Second, the gate signal can often have edge skew problems (i.e., the edge can wander early or late due to process-voltage-temperature (PVT) variations), which is common to all synthesized circuits. These variations can make the CML MUX1710toggle at a non-fixed cycle (although the phase can be synchronized), thus resulting in a gate opening duration that fluctuates with time.

In order to provide more accurate time resolution and finer duration control for the CMOS gate signal, a finite-state machine (FSM) with a built-in counter can be inserted before flip-flop1706to refine the gate signal.FIG. 19Aillustrates a circuit1900which includes an FSM for synthesizing a gate signal with a controllable duration and a synchronization mechanism for phase-aligning the synthesized gate signal to a CML clock signal.

As illustrated inFIG. 19A, synchronization circuit1900also receives a high-speed CML clock signal clk_in1902from a CML clock domain, and includes a hybrid CMOS-CML flip-flop1904(or “flip-flop1904”) for synchronizing clk_in1902with a CMOS gate signal, and a CML MUX1906for gating clk_in1902based on a synchronized gate signal output from flip-flop1904. Note that flip-flop1904may be substantially similar in design to flip-flop1706inFIG. 17A. Therefore, the exemplary design of hybrid flip-flop1800described in conjunction withFIG. 18is also applicable to flip-flop1904.

One difference between circuit1700and circuit1900is that circuit1900does not directly receive a CMOS gate signal from a CMOS reference clock domain. Instead, circuit1900uses a CMOS-based FSM (i.e., logic1908) to receive one or more control signals1910from a CMOS reference clock domain, wherein logic1908is configured to use these control signals to synthesize a CMOS gate signal. In some embodiments, control signals1910include initialization control information for initializing logic1908. In one embodiment, the initialization control information includes a trigger signal transition (e.g., a rising edge transition) which is configured to cause logic1908to initialize and subsequently begin the gate signal synthesis. Control signals1910can also include duration control information which specifies the duration of an opening in the gate signal.

In one embodiment, logic1908operates at high speed based on the CML clock signal clk_in1902. Because logic1908is implemented predominantly in CMOS logic for low power operation purposes, a clock converter CML2CMOS1912is inserted between clk_in1902and a clock input of logic1908to convert clk_in1902in the CML level into a new clock clk_CMOS1914in the CMOS level to accommodate logic1908. In the embodiment shown, CML2CMOS1912receives a 180° phase-inverted version of clk_in1902for the same reason as explained in conjunction with circuit1700. As a result, clk_CMOS1914is a CMOS clock signal that is delayed from the inverse version of clk_in1902by a propagation delay TCML2CMOSintrinsic to CML2CMOS1912. Note that logic1908can operate at the speed of the input CML clock signal based on CMOS clock signal clk_CMOS1914, thereby facilitating a tighter timing constraint and high resolution (up to one CML clock period) for synthesizing the gate signal.

In one embodiment, when synthesizing a gate signal based on control signals1910, logic1908operates to control the gate opening duration as a variable equal to the clock period of clk_in1902multiplied by an integer variable N(N≧1) provided in the duration control information in control signals1910. For example, after initializing logic1908based on control signals1910, logic1908generates a rising edge transition as the beginning of the enable window. Next, logic1908may use the duration control information, a built-in counter and clk_CMOS1914to generate the enable window of the gate signal. Logic1908then generates a falling edge transition as the end of the enable window after the counter has counted down N clock cycles.

In some embodiments, when synthesizing a gate signal based on control signals1910, logic1908operates to generate the gate opening duration to be one of a set of predetermined durations. More specifically, logic1908can store a set of predetermined counter values corresponding to a set of fixed gate durations, e.g., 4, 8, 16, and 32, and control signals1910can include one or more selection bits to select one of these counter values. In this way, logic1908can synthesize a gate signal with a predetermined opening duration based on the selection bits received from control signals1910. Note that while embodiments ofFIG. 19Ashow logic1908and CML2CMOS1912as separate modules, other embodiments can combine the function of both logic1908and CML2CMOS1912into a single module.

Still referring toFIG. 19A, note that the output of logic1908is a synthesized CMOS gate signal gate01916with a programmed duration measured in the clock period of CML clock clk_in1902and can be as short as one CML clock period. While gate01916is retimed based on clk_in1902, it may not have the desired phase relationship to gate clk_in1902, as explained previously in conjunction withFIG. 16. At this point, circuit1900uses flip-flop1904to realign gate01916to clk_in1902in a manner substantially similar to the operation of flip-flop1706inFIG. 17A. As illustrated inFIG. 19A, flip-flop1904receives gate01916as a data input and 180° inverted clk_in1902as the clock input, and outputs a retimed CMOS gate signal gate11918which has a desired phase relationship with respect to clk_in1902. The phase relationship between gate11918and clk_in1902is described in more detail below in conjunction withFIG. 19B. Gate11918is the input to clock gate circuit MUX1906, which also receives clk_in1902and outputs a glitch-free gated CML clock signal clk_out1920.

FIG. 19Bpresents a timing diagram illustrating the phase relationship and time constraints between CML input clock clk_in1902and the retimed CMOS gate signal gate11918described inFIG. 19A. As illustrated inFIG. 19B, a rising edge transition1922in control signals1910causes logic1908to initialize itself. In one embodiment, the time for this initialization is substantially equal to one CML clock period (TClkPERIOD). In other embodiments, the initialization can take multiple TClkPERIODto complete. This latency associated with logic initialization may be compensated by properly designed control signals1910, for example, through the time of arrival of transition1922.

Upon completing the initialization, logic1908is conditioned to generate the gate signal in response to the next clock transition of input clock clk_in1902. Note that logic1908does not receive clk_in1902directly. Instead, clk_in1902is first 180° phase-inverted to create an inverse clock clk_in1801932, which is subsequently converted to a CMOS clock clk_CMOS1914by CML2CMOS1912. Clk_CMOS1914is delayed relative to clk_in1801932due to a propagation delay of CML2CMOS1912, denoted as TCML2CMOS. This is shown by a rising edge transition1926in clk_CMOS1914which is delayed from transition1924by TCML2CMOS. In the embodiment shown, logic1908is configured to propagate an input value to the output on rising edge transitions of clk_CMOS1914, such as transition1926. Note that various delays shown inFIG. 19Bare referenced relative to transition1924in clk_in1801932. However, these delays can also be equivalently referenced relative to a corresponding falling edge transition1925in clk_in1902.

Further referring toFIG. 19B, note that transition1926in clk_CMOS1914is used by logic1908to sample control signals1910and generate a rising edge transition1928in gate01916corresponding to the beginning of a synthesized enable window. In one embodiment, the delay from transition1926to transition1928is due to the output stage (i.e., one standard cell) of logic1908after receiving transition1926, which is denoted as TC-Q,StdCELLto represent the output delay of logic1908.

As illustrated inFIG. 19Bwith reference toFIG. 19A, transition1928in gate01916is then phase-aligned with clk_in1902by flip-flop1904. More specifically, flip-flop1904, which is directly controlled by clock clk_in1801932, samples input gate01916and passes the sampled value to the output gate11918on a rising edge transition of clk_in1801932. In the embodiment shown inFIG. 19B, this rising edge transition in clk_in1801932is transition1930one clock cycle after transition1924. In order to satisfy a setup time requirement of flip-flop1904, the time interval between transition1928in gate01916and transition1930in clk_in1801932should be greater than the setup time of flip-flop1904, referred to as TSETUP,HybridFF. As indicated inFIG. 19B, this timing constraint can be collectively expressed as:
TCML2CMOS+TC-Q,StdCELL+TSETUP,HybridFF<TClkPERIOD,  (1)
wherein TClkPERIODis the clock period of clk_in1902, or the time between transitions1924and1930.

After the retiming operation by flip-flop1904, transition1928in gate01916is retimed and output as transition1934in gate11918. As illustrated inFIG. 19B, transition1934in gate11918is substantially phase-aligned with a midpoint location between two consecutive clock transitions in clk_in1801932marked by dashed line1936. In reference to the input clock clk_in1902, location1936corresponds to a midpoint in the logic low half of a clock cycle in clk_in1902. In other words, location1936is approximately equal to ¼ of TClkPERIODfrom transition1930, as previously described in conjunction withFIG. 17B. This timing requirement provides a second time constraint for the design of flip-flop1904, which can be expressed as:
TC-QHybridFF≈¼TClkPERIOD,  (2)
wherein TC-Q,HybridFFis the clock to data output delay of flip-flop1904measured from a triggering clock edge (e.g., transition1930in clk_in1801932) to the flip-flop output switch values (e.g., transition1934in gate11918). Note that the second time constraint does not have to be exact, and depending on a particular design, a tolerance may be added to eqn. (2). For example, this tolerance can be expressed as:
TC-Q,HybridFF=¼TClkPERIOD±p×TClkPERIOD,  (3)
wherein p is a percentage value, such as 10% or 15%. Note that a combination of the two timing constraints (1) and (2) (or (3)) facilitates determining a lower bound for the CML clock cycle TClkPERIOD(i.e., how fast the CML clock can be).

Further referring toFIG. 19Bwith reference toFIG. 19A, note that gate11918is used to control MUX1906to generate glitch-free gated CML clock clk_out1920. As illustrated inFIG. 19B, clk_out1920includes a complete half clock cycle1938corresponding to an original half clock cycle1940in clk_in1902. Also note thatFIG. 19Bdoes not explicitly show the end of the enable window in gate01916or gate11918. However, because the end of an enable window in a gate signal is programmed to occur an integer multiple of TClkPERIODfrom the beginning of the enable window, all above-described timing constraints also apply to and can be simultaneously satisfied by the end of the enable window.

Note that the second timing constraint of eqn. (2) or eqn. (3) does not take into account the effects of PVT variations in the system.FIG. 20presents a timing diagram illustrating the effects of PVT variations on the phase relationship between the CML input clock and the retimed CMOS gate signal.

More specifically,FIG. 20includes three of the signals described inFIGS. 19A and 19B: clk_in1902, gate11918, and clk_out1920. Gate11918comprises an opening defined by a rising edge transition as the beginning of the enable window and a falling edge transition as the end of the enable window. Ideally, the beginning and end of the enable window are phase-aligned with clk_in1902at locations2002and2004marked by the dashed lines, which are midpoints between adjacent clock transitions. However, PVT variations cause the enable window boundaries to drift away from these desired locations. For example, the beginning of the enable window can open early to location2006or open late to location2008. When opened early, gate11918causes a glitch2010in clk_out1920. On the other hand, late opening of the enable window causes a narrow pulse2012in clk_out1920. Similarly, the end of the enable window can also open early to location2014or open late to location2016. When opened early, the beginning of the enable window causes a narrow pulse2018in clk_out1920. On the other hand, late opening of the enable window causes a glitch2020in clk_out1920. However, circuit1900described in conjunction withFIG. 19Adoes not provide a compensation mechanism for the PVT drifts within gate11918. Note that the PVT drifts shown inFIG. 20are for illustration purposes only.

FIG. 21illustrates a circuit2100which is modified version of circuit1900that includes a mechanism for compensating for PVT variations.

Note that circuit2100is substantially similar to circuit1900but includes a compensation module, referred to as CMOS buffer2102, that is inserted between the output of flip-flop1904and the select input of MUX1906. More specifically, CMOS buffer2102receives gate11918as an input, adds a delay to gate11918, and outputs a delayed gate signal gate22104, which is then used to gate clk_in1902. The amount of delay added by CMOS buffer2102is denoted as TBFR. Note that CMOS buffer2102also receives a control input bfr_adj2106from logic1908. In one embodiment, CMOS buffer2102is configured to set the delay value of TBFRbased on bfr_adj2106. Note that by introducing the delay TBFR, the second time constraint in eqn. (2) is modified to:
TC-Q,HybridFF+TBFR≈¼TClkPERIOD,  (4)
wherein TBFRis a controllable delay. Note that PVT variations can be treated as an additional delay term TPVTwhich has a positive value if the enable window opens or closes late, and a negative value if the enable window opens or closes early. Hence, eqn. (4) can be rewritten as
TC-Q,HybridFF+TBFR+TPVT≈¼TClkPERIOD.  (5)
Note that adjustable delay TBFRcan be dynamically varied to compensate for a varying TPVTfor both the open and close of the enable window.

For example, if logic1908determines that the beginning of the enable window drifts to an early location2006, logic1908can send bfr_adj2106which causes TBFRto take on a greater delay value. This way, CMOS buffer2102adjusts the beginning of the enable window back to the desired location2002. Separately, if logic1908determines that the end of the enable window drifts to a late location2016, logic1908can send bfr_adj2106which causes TBFRto take on a smaller delay value. This way, CMOS buffer2102adjusts the end of the enable window back to the desired location2004. In one embodiment, CMOS buffer2102comprises a set of serially coupled inverters, wherein each inverter causes a unit delay. CMOS buffer2102can generate variable delays by passing gate11918through a subset of the set of inverters. In this embodiment, control signal bfr_adj2106may comprise multiple bits to select a specific number of inverters to program TBFRto compensate for a dynamically calibrated TPVT.

Applications and Systems

Note that because the above-described techniques for communicating between integrated circuit devices are applicable to source-synchronous communication between two integrated circuit devices, these techniques can be used in any system that includes a source-synchronous dynamic random access memory device (“DRAM”). Such a system can be, but is not limited to, a mobile system, a desktop computer, a server, and/or a graphics application. Moreover, the DRAM may be, e.g., graphics double data rate (GDDR, GDDR2, GDDR3, GDDR4, GDDR5, and future generations), double data rate (DDR2, DDR3 and future memory types), and low-power double data rate (LPDDR2 and future generations).

The source-synchronous apparatus and techniques described may be applicable to other types of memory, for example, flash and other types of non-volatile memory and static random access memory (SRAM). One or more of the techniques or apparatus described herein are applicable to front side bus, (i.e., processor to bridge chip, processor to processor, and/or other types of chip-to-chip interfaces). Note that the two communicating integrated circuit IC chips (i.e., the transmitter and receiver) can also be housed in the same package, e.g., in a stacked die approach. Furthermore, the transmitter, receiver and the channel can all be built on-die in a system-on-a-chip (SOC) configuration.

Moreover, throughout this description, a clock signal is described and it should be understood that a clock signal in the context of the instant description may be embodied as a strobe signal or other signal that conveys a timing reference.

Additional embodiments of memory systems that may use one or more of the above-described apparatus and techniques are described below with reference toFIG. 22.FIG. 22presents a block diagram illustrating an embodiment of a memory system2200, which includes at least one memory controller2210and one or more memory devices2212. WhileFIG. 22illustrates memory system2200with one memory controller2210and three memory devices2212, other embodiments may have additional memory controllers and fewer or more memory devices2212. Note that the one or more integrated circuits may be included in a single-chip package, e.g., in a stacked configuration.

Memory controller2210may include an I/O interface2218-1and control logic2220-1. In some embodiments, one or more of memory devices2212include control logic2220and at least one of interfaces2218. However, in some embodiments some of the memory devices2212may not have control logic2220. Moreover, memory controller2210and/or one or more of memory devices2212may include more than one of the interfaces2218, and these interfaces may share one or more control logic2220circuits. In some embodiments two or more of the memory devices2212, such as memory devices2212-1and2212-2, may be configured as a memory rank2216.

As discussed in conjunction withFIGS. 7 to 12, one or more of control logic2220-1, control logic2220-2, control logic2220-3, and control logic2220-4may be used to perform clock multiplication and frequency division to generate a set of new clocks from a reference clock, and to retime a received data signal from the reference clock domain to the new clock domain. When performing the retiming operation, the one or more of control logic may use a logic circuit to determine whether it is safe to retime the received data signal using the new clocks. The one or more of control logic may also use a circuit to phase-adjust the received data signal so that it becomes safe to retime the phase-adjusted received data signal based on the new clocks when it is unsafe to directly retime the received data signal. Moreover, the one or more of control logic may use a serializer to serialize a parallel data received by memory controller2210into a retimed serial data signal.

Memory controller2210and memory devices2212are coupled by one or more links2214, such as multiple wires, in a channel2222. While memory system2200is illustrated as having three links2214, other embodiments may have fewer or more links2214. Furthermore, links2214may be used for bi-directional and/or unidirectional communication between the memory controller2210and one or more of the memory devices2212. For example, bi-directional communication between the memory controller2210and a given memory device may be simultaneous (full-duplex communication). Alternatively, the memory controller2210may transmit a command to the given memory device, and the given memory device may subsequently provide requested data to the memory controller2210, e.g., a communication direction on one or more of the links2214may alternate (half-duplex communication). Also, one or more of the links2214and corresponding transmit circuits and/or receive circuits may be dynamically configured, for example, by one of the control logic2220circuits, for bidirectional and/or unidirectional communication.

In some embodiments, commands are communicated from the memory controller2210to one or more of the memory devices2212using a separate command link, i.e., using a subset of the links2214which communicate commands. However, in some embodiments commands are communicated using the same portion of the channel2222(i.e., the same links2214) as data.

Devices and circuits described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. These software descriptions may be: behavioral, register transfer, logic component, transistor and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3½ inch floppy media, CDs, DVDs, and so on.

The preceding description was presented to enable any person skilled in the art to make and use the disclosed embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the disclosed embodiments. Thus, the disclosed embodiments are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present description. The scope of the present description is defined by the appended claims.

Also, some of the above-described methods and processes can be embodied as code and/or data, which can be stored in a non-transitory computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the non-transitory computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the non-transitory computer-readable storage medium. Furthermore, the methods and processes described below can be included in hardware. For example, the hardware can include, but is not limited to, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), and other programmable-logic devices now known or later developed. When the hardware is activated, the hardware performs the methods and processes included within the hardware.