GALLIUM NITRIDE (GAN) INTEGRATED CIRCUIT TECHNOLOGY WITH RESONATORS

Gallium nitride (GaN) integrated circuit technology with resonators is described. In an example, an integrated circuit structure includes a layer or substrate including gallium and nitrogen. A first plurality of electrodes is over the layer or substrate. A resonator layer is on the first plurality of electrodes, the resonator layer including aluminum and nitrogen. A second plurality of electrodes is on the resonator layer. Individual ones of the second plurality of electrodes are vertically over and aligned with corresponding individual ones of the first plurality of electrodes.

TECHNICAL FIELD

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and packaging and, in particular, gallium nitride (GaN) integrated circuit technology with resonators.

BACKGROUND

Power delivery and RF communication are essential to every compute solution. Si and III-V technologies are facing fundamental limits in power and RF. Future compute solutions will require a better semiconductor technology to continue to deliver better energy efficiencies, better performance, and more functionalities in smaller form factors. Amongst semiconductor technologies today, GaN is best for power delivery and RF due to its wide bandgap qualities.

DESCRIPTION OF THE EMBODIMENTS

Gallium nitride (GaN) integrated circuit technology with resonators is described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Terminology. The following paragraphs provide definitions or context for terms found in this disclosure (including the appended claims):

“Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or operations.

“Configured To.” Various units or components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the units or components include structure that performs those task or tasks during operation. As such, the unit or component can be said to be configured to perform the task even when the specified unit or component is not currently operational (e.g., is not on or active). Reciting that a unit or circuit or component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, sixth paragraph, for that unit or component.

“First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

“Coupled”—The following description refers to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element or node or feature is directly or indirectly joined to (or directly or indirectly communicates with) another element or node or feature, and not necessarily mechanically.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

In one aspect, AlN on GaN reconfigurable piezoelectric and piezoresistive resonators for clocking and filtering operations are described.

To provide context, clocking is the heart of every central processing unit/graphics processing unit (CPU/GPU) or wireless chip. To generate the 1 to 10 GHz frequencies required in a CPU/GPU, multiple phase lock loops (PLLs) are cascaded to multiply an external low jitter 25 MHz to 100 MHz reference clock. This may require two or three PLLs in cascade and is a source of a long term jitter (i.e., jitter with a periodicity over tens of cycles of the GHz clock), which degrades the CPU/GPU's maximum performance. In addition, due to extra low jitter requirements for wireless RF transceivers or high frequency wireline transceivers, these circuits also require integrated PLLs that use inductors in their oscillator. However, the integrated inductors do not usually have very high quality factors (Q's), take up large silicon areas, cause crosstalk, and have no possibilities for scaling. Therefore, it would be advantageous to remove (i) the need to cascade multiple PLLs to generate GHz clock frequencies and (ii) inductors that incur a lot of integration challenges, e.g., by using one high frequency (e.g. 10 to 20 GHz), low jitter oscillator in a PLL to derive the many clock frequencies required on a CPU/GPU or 5G RF transceiver.

Previous solutions have included silicon MOSFET-based resonators which have been proposed to realize high-Q on-chip resonators. However, the Si resonator output signal (e.g., Si drive current modulation due to strain) may be relatively small due to the limited magnitude of piezoresistive coefficients of Si channels, so it can be challenging to realize oscillator circuits without additional amplifiers. Also, the resonator frequency is basically determined by the physical structure of the Si transistor itself (e.g., fin pitch), so it is not straightforward to realize reconfigurable resonators.

In accordance with one or more embodiments of the present disclosure, GaN high electron mobility (HEMT)-based piezoresistive resonators making use of the higher piezoresistive response of GaN material (e.g., about 10× higher than those of Si) are implemented. In accordance with one or more embodiments, reconfigurable AlN resonators are implemented using a GaN—AlGaN material system that can also be used for GaN HEMT.

As exemplary structures and operations,FIG.1Aillustrates cross-sectional views of (a) a GaN HEMT, (b) a GaN HEMT-based resonator, and (c) another GaN HEMT-based resonator, in accordance with an embodiment of the present disclosure.FIG.1Billustrates (a) a cross-sectional view of another GaN HEMT-based resonator, and (b) a corresponding plot of operation, in accordance with an embodiment of the present disclosure.

Referring to part (a) ofFIG.1A, an integrated circuit structure100A includes an AlN spacer or buffer layer104on a silicon substrate102. A GaN layer106is on the AlN spacer or buffer layer104. An AlGaN polarization layer108is on the GaN layer106. A source structure110is at a first end of the AlGaN polarization layer108, and a drain structure112is at a second end of the AlGaN polarization layer108. A high-k gate dielectric layer114is on the AlGaN polarization layer108. A gate electrode116is on the high-k gate dielectric layer114. The high-k gate dielectric layer114and the gate electrode116can be seated between protrusions118of the AlGaN polarization layer108, as is depicted. Source or drain contacts120are on the source structure110and on the drain structure112. Interconnects122can be included in a dielectric layer124and be positioned over the gate electrode116, as is depicted.

In an embodiment, structure100A represents a GaN HEMT. However, the same or similar structure can be used to realize resonators. Examples are illustrated in parts (b) and (c) ofFIG.1A(structures100B and100C, respectively), and in part (a) ofFIG.1B(structure100D), where drive and sense transistors (128A and130A, or128B and130B, or128C and130C) are separate but they may share the same GaN layer (106) and gate voltage input (132A, or132B, or132C). As shown in part (b) ofFIG.1A, a capacitive actuation134A may occur across the high-k layer114achieving mechanical resonance126A in the underlying GaN106and buffer layers104. The resonant frequency126A may be changed by changing the thicknesses of the GaN (tGaN) and/or the buffer layer (tbuffer) as shown by the resonant frequency126B of part (c) ofFIG.1A. That is, resonant frequency may be modified by using different layer thicknesses. When the resonance is obtained in the GaN layer, it may be sensed through the sensing transistor, as shown by resonance126C in part (a) ofFIG.1B, where the HEMT current135C is modulated by the dynamic stress at the two-dimensional electron gas (2DEG) position. The output signal may appear as in plot136of part (b) ofFIG.1B, where gPZmay show a resonance peak while the background signal is in principle zero due to the small feed-through in the design with separate drive and sense transistors. Thus, referring toFIG.1B, a sensing (piezoresistive modulation of transistor current) part of the resonator with separate drive and sense transistors is implemented such that an output signal of the resonator can be realized with small feed-through due to the separate drive and sense.

As another possible resonator configuration,FIG.1Cillustrates (a) a cross-sectional view of another GaN HEMT-based resonator, and (b) a corresponding plot of operation, in accordance with an embodiment of the present disclosure. Referring to part (a) ofFIG.1C, a structure100E includes the driving and sensing portions128D and130D combined in one transistor (e.g., with gate132D). In this case, the output signal135D may show a resonance peak126D on top of the baseline signal which represents the intrinsic transconductance of the device, as demonstrated in plot138of part (b) ofFIG.1C. Thus, with reference toFIG.1C, the driving and sensing components can be combined within a same device. An output signal of the resonator can include a background signal that represents the transistor transconductance.

In another aspect, embedded AlN resonators using a material system of a GaN HEMT are described. As described below in association withFIG.1D, unreleased or released resonator structures can be fabricated. As described below in association withFIG.1E, multiple signal inputs and various configurations of actuation voltages across the AlN layer can be implemented, exciting different resonant modes and reconfigure the resonant frequency of the AlN resonator.

FIG.1Dillustrates cross-sectional views representing an embedded AlN resonator using a GaN HEMT material system with (a) an unreleased structure, and (b) a released structure, in accordance with an embodiment of the present disclosure.

Referring to part (a) ofFIG.1D, an integrated circuit structure140A includes an AlN spacer or buffer layer144on a silicon substrate142. A GaN layer146is on the AlN spacer or buffer layer144. A first plurality of electrodes148is over the GaN layer146. An AlN resonator layer150is on the first plurality of electrodes148. A second plurality of electrodes152is on the resonator layer150. Individual ones of the second plurality of electrodes152are vertically over and aligned with corresponding individual ones of the first plurality of electrodes148. Interconnects154can be included in a dielectric layer156, as is depicted. Referring to part (b) ofFIG.1D, an integrated circuit structure140B includes a cavity in the dielectric layer156, the cavity around the resonator layer150. The cavity can also expose portions of the first plurality of electrodes148and the second plurality of electrodes152.

FIG.1Eillustrates cross-sectional views representing reconfigurable embedded AlN resonators, in accordance with an embodiment of the present disclosure. It is to be appreciated that, by putting multiple input signal ports and applying various configurations of actuation voltages, different resonant modes of the AlN layer may be able to be excited in a reconfigurable way.

Referring to part (a) ofFIG.1E, an integrated circuit structure160A includes an AlN spacer or buffer layer164on a silicon substrate162. A GaN layer166is on the AlN spacer or buffer layer164. A first plurality of electrodes168is over the GaN layer166. An AlN resonator layer170A is on the first plurality of electrodes168. A second plurality of electrodes172is on the resonator layer170A. Individual ones of the second plurality of electrodes172are vertically over and aligned with corresponding individual ones of the first plurality of electrodes168. Interconnects174can be included in a dielectric layer176, as is depicted. The first plurality of electrodes168beneath the AlN resonator layer170A are coupled to ground (GND), and the second plurality of electrodes172above the resonator layer170A are coupled to two (−) input signals and one (+) input signal. Referring to part (b) ofFIG.1E, an integrated circuit structure160B includes the first plurality of electrodes168beneath an AlN resonator layer170B coupled to ground, and the second plurality of electrodes172above the resonator layer170B coupled to two (+) input signals and one coupled to ground. Referring to part (c) ofFIG.1E, an integrated circuit structure160C includes the first plurality of electrodes168beneath an AlN resonator layer170C coupled to ground, and the second plurality of electrodes172above the resonator layer170B coupled to one (+) input signals and two coupled to ground.

With reference again toFIGS.1D and1E, it is to be appreciated that any type of piezoelectric (with AlN described above as an example) or piezoresistive semiconductor materials may be placed above the GaN layer to implement the embedded reconfigurable resonator.

With reference again toFIGS.1D and1E, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a layer or substrate including gallium and nitrogen (146or166). A first plurality of electrodes (148or168) is over the layer or substrate including gallium and nitrogen (146or166). A resonator layer (150,170A,170B or170C) is on the first plurality of electrodes (148or168), the resonator layer (150,170A,170B or170C) including aluminum and nitrogen. A second plurality of electrodes (152or172) is on the resonator layer (150,170A,170B or170C). Individual ones of the second plurality of electrodes (152or172) are vertically over and aligned with corresponding individual ones of the first plurality of electrodes (148or168).

In an embodiment, the resonator layer is surrounded by and is in contact with a dielectric layer, e.g., as exemplified in part (a) ofFIG.1Dand in parts (a), (b) and (c) ofFIG.1E. In another embodiment, the resonator layer is in a cavity in a dielectric layer, e.g., as exemplified in part (b) ofFIG.1D.

In an embodiment, the first plurality of electrodes includes two electrodes, and the second plurality of electrodes includes two electrodes, e.g., as exemplified in parts (a) and (b) ofFIG.1D. In another embodiment, the first plurality of electrodes includes three electrodes, and the second plurality of electrodes includes three electrodes, e.g., as exemplified in parts (a), (b) and (c) ofFIG.1E.

In accordance with one or more embodiments of the present disclosure, other GaN-based devices can be integrated together with the above described resonator structures. In a particular embodiment, one or more high voltage scaled GaN devices are integrated together with the above described resonator structures, examples of which are described below.

To provide context, RF power amplifiers (RF PAs) are needed to transmit RF signals between mobile devices and base stations located at far distances away, such as greater than 1 mile. The efficiency of these RF PAs is a key determinant of battery life in mobile handsets and power consumption (cost) in RF base stations. Good linearity of the RF power amplifier is required for modern communication standards such as 4G LTE and 5G standards. RF PAs typically operate at several dB back-off from its saturated mode in order to meet the linearity requirements. Thus, the efficiency suffers and in most PAs, it may degrade by a factor of 2-3×.

Due to its wide bandgap and high critical breakdown electric field, gallium nitride (GaN) transistors are considered for high voltage applications such as power converters, RF power amplifiers, RF switch and high voltage applications. Simple transistor architecture, namely, having a single gate, source and drain, falls short of realizing the full potential of GaN in achieving the maximum breakdown voltage as dictated by its material properties. This is because the drain electric field concentrates at the edge of the gate and causes premature breakdown.

Embodiments of the present disclosure relate to gallium nitride (GaN) transistors having drain field plates. In embodiments, the transistors of the present disclosure have a gallium nitride (GaN) layer disposed above a substrate. A gate structure is disposed above the GaN layer. A source region and a drain region are disposed on opposite sides of the gate structure. The drain field plate may be biased to an electrical potential which is different than a gate voltage and/or VSS offering a greater degree of control of the drain field. The transistors of the present disclosure may enable new circuit architectures, such as a cross-coupled pairs. Additionally, the distance the drain field plate extends above the drain can be independently adjusted to improve the effect the field plate has on the drain field distribution, and hence increase breakdown voltage and linearity. In an embodiment, the transistor is operated in an enhancement mode. In an embodiment the gate structure may have a “T” shape in order to reduce the electrical resistance of the gate structure. In an embodiment, the transistor may include a second gate structure or multiple gate structures disposed between the gate structure and the drain field plate to provide a multigate switch for, for example, an RF voltage divider.

FIG.2illustrates as transistor200having a drain field plate in accordance with embodiments of the present disclosure. Transistor200includes a GaN layer202disposed above a substrate204. A buffer layer206may be disposed between GaN layer202and substrate204. A gate structure208is disposed above GaN layer202as illustrated inFIG.2. Gate structure208may include a gate dielectric210, such as a high-k gate dielectric, such as but not limited to hafnium oxide (e.g., HfO2) and aluminum oxide (e.g., Al2O3), and a gate electrode212, such as a metal gate electrode. A source region214and a drain region216are disposed on opposite sides of gate structure208as illustrated inFIG.2.

Transistor200includes a drain field plate220located above drain region216. Drain field plate220is separated from drain region216by a distance (dDFP) as illustrated inFIG.2. Drain field plate220may be separated from gate structure208by a distance dDG.

In an embodiment, source region214includes a source contact224and drain region216includes a drain contact226. Source contact224may include a source semiconductor contact228and a source metal contact230, and drain contact226may include a drain semiconductor contact232and a drain metal contact234. In an embodiment as illustrated inFIG.2, source semiconductor contact228and drain semiconductor contact232are formed from a group III-N semiconductor, such as but not limited to indium gallium nitride (InGaN). In an embodiment, the group III-N semiconductor has an N+ conductivity, such as, for example, containing Si dopant density greater than 1×1018atoms/cm3. In an embodiment, the source metal contact230and the drain metal contact234include a metal, such as but not limited to titanium. In an embodiment, drain field plate220is located laterally between drain metal contact234and gate structure208as shown inFIG.2.

Transistor200may include a polarization layer240disposed on GaN layer202. Polarization layer240may be formed from a group III-N semiconductor, such as but not limited to aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN) and indium gallium nitride (InGaN). In an embodiment, polarization layer240is sufficiently thick in order to create a two-dimensional electron gas (2DEG) effect or layer250in the top surface of GaN layer202as illustrated inFIG.2. In an embodiment, polarization layer240has a portion242beneath gate structure208which is thinner than portion244above source region214and drain region216so that a 2DEG layer or effect is not created in gallium nitride layer202beneath gate structure208as shown inFIG.2. In an embodiment, polarization layer240is completely removed from under gate structure208and gate structure208is disposed directly on GaN layer202. In an embodiment polarization layer240is multilayer film including a lower AN film and an upper AlInN for example. In an embodiment, transistor200is operated in an enhancement mode.

Drain field plate220and gate structure208are disposed within dielectric layer260as illustrated inFIG.2. In an embodiment, the top surface of drain field plate220, is coplanar with the top surface of gate structure208as illustrated inFIG.2. In an embodiment, the top surface of dielectric layer260is coplanar with the top surface of gate structure208, and drain field plate220as illustrated inFIG.2. In an embodiment, the top surface of source metal contact230and the top surface of drain metal contact234are coplanar with the top surface of gate structure208and the top surface of drain field plate220.

Transistor200has a gate length (Lg) in a first direction extending between the source region214and the drain region216as shown inFIG.2. A channel region is located in GaN layer202beneath gate structure208and between source region214and drain region216. Transistor200has a gate width (Gw) in a direction perpendicular (in and out of the page) to the gate length (Lg) direction. In an embodiment, transistor200has a gate width (Gw) between 0.010 microns-100 microns. In an embodiment, drain field plate220extends the entire gate width (Gw) of transistor200. In an embodiment, gate structure208has a “T” shape as illustrated inFIG.2. Gate structure208may include an upper gate portion213and a lower gate portion215. Upper gate portion213is distal from GaN layer202while lower gate portion215is nearer GaN layer202. In an embodiment, lower gate portion215has a length (Lg) in the gate length direction which defines the gate length (Lg) of transistor200. In an embodiment, upper gate portion213has length (LUG) in the gate length direction which is at least two times, and in other embodiments at least three times, greater than the gate length (Lg) of lower gate portion215. In an embodiment, as shown inFIG.2upper gate portion213extends a distance (dUG) above drain region216which is greater than the distance dDFPthat drain field plate220extends above drain region216. A recessed drain field plate may provide improved control of the drain field. In an embodiment, a recessed drain field plate may exert a depletion effect on the 2DEG in the extended drain region. In an embodiment, upper gate portion213extends a distance (dUG) above drain region216which is the same distance dDFPthat drain field plate220extends above drain region216. In an embodiment, gate dielectric210is disposed along the sidewalls and bottom of upper gate portion213and along the sidewalls and bottom of lower gate portion215as illustrated inFIG.2.

In an embodiment, drain field plate220may be biased separately from a gate voltage (Vg) applied to gate structure208. In an embodiment, drain field plate220may be biased to a potential different than Vss or ground. In an embodiment, drain field plate220may be biased differently than the voltage applied to source region214. In an embodiment, drain field plate220may be biased differently than a voltage applied to drain region216. In an embodiment, drain field plate220is not electrically connected to drain region216.

In an embodiment, a pair of insulative spacers270are disposed along opposite sides of gate structure208as illustrated inFIG.2. In an embodiment, insulative spacers270do not extend the entire height of gate structure208. In an embodiment, insulative spacers270do not contact polarization layer240or GaN layer202. In an embodiment, spacers270are formed beneath upper gate portion213and on sidewalls of lower gate portion215as illustrated inFIG.2. In an embodiment, insulative spacers270are formed from an insulative material, such as but not limited to, silicon nitride and silicon oxynitride, which is different from the dielectric material of dielectric layer260.

In an embodiment, a second dielectric layer280is disposed over dielectric layer260. A plurality of conductive vias282may be disposed in dielectric280to enable independent electrical connections to and control of source region214, drain region216, drain field plate220and gate structure208.

In an embodiment, a high-k dielectric272, such as but not limited to hafnium oxide (e.g., HfO2) and aluminum oxide (e.g., Al2O3) may be disposed and on the sidewalls and bottom surface of drain field plate220as illustrated inFIG.2. In an embodiment, high-k dielectric272is the same high-k dielectric material as gate dielectric layer210of gate structure208.

FIG.3illustrates a GaN transistor300having a drain field plate and multiple gates. Transistor300includes a second gate structure302above GaN layer202and between gate structure208and drain field plate220as illustrated inFIG.3. Second gate structure302may be recessed into polarization layer240so that a 2DEG layer of effect is not formed under second gate structure302as illustrated inFIG.3. Gate structure302may include a gate dielectric such as a high-k gate dielectric310and a gate electrode312as described with respect to gate structure208. In an embodiment, the second gate structure302has a larger gate length (LG2) than the gate length (Lg) of gate structure208. That is, in an embodiment, LG2is greater than Lg. In an embodiment, LG2is equal to Lg. In an embodiment, second gate structure302may have a “T” shape including an upper gate portion313and a lower gate portion315as illustrated inFIG.3.

In an embodiment, two or more additional gate structures302may be disposed over GaN layer202and between gate structure208and drain field plate220. In an embodiment, gate structure208and each of the additional gate structures302may be biased separately. In an embodiment, the multiple gates act as an RF voltage divider allowing each gate to be biased with a lower DC voltage. A single gate NMOS transistor may require a large negative gate voltage (Vg) to keep the transistor in an “OFF” state. In an embodiment, transistor300may be used in a cascoded power amplifier circuit. Transistor300may improve gain by reducing source resistance of the second gate. Having two gate electrodes may protect the corresponding gate oxides from increased voltages.

To provide further context, GaN high voltage transistors in the market are not scaled. GaN transistors in the market today utilize long channel gates and thick p-GaN gate stack that may not be suitable for scaling the transistor to smaller dimensions to improve performance and low resistances. Moreover, coarse lithography techniques that are used may be limited as the industry remains working in 4 inch manufacturing lines that do not have access to the latest lithographic tools and techniques.

In accordance with one or more embodiments of the present disclosure, a heterostructure employing, p-InGaN and p-AlGaN layers in the gate of the GaN transistor, in addition to p-GaN, to enable scaling of the gate stack, thus enabling the further scaling of transistor channel length to improve performance: lower on-resistance and higher drive current. Other enabling features such as p-(III-N) field plate, multi-gate structures and hybrid trench plus implant isolation techniques are also disclosed herein to enable scaling of high voltage GaN transistor solutions. Such features can enable the ultimate scaling of high voltage GaN transistors to provide the highest performance in the smallest possible footprint.

In accordance with an embodiment of the present disclosure, a high voltage GaN transistor technology enables power delivery solutions that are more efficient than what is possible today. Servers and graphics products are powered by power delivery solutions with input voltages ranging between 48V to 72V. Discrete GaN transistors are used to step this high input voltage down to 5V on the board so that a second stage voltage conversion can be used in the subsequent power stages to convert the voltage to a desired supply voltage to integrated circuits, ranging from 3.3V to 0.5V, for example. Many stages of conversion are required using Si technology because at each stage, a different Si transistor technology is used. Dissimilar discrete technologies must thus be made to work together on the board or in bulky thick packages. GaN technology is unique in that it is the only technology that can be used across the entire power delivery value chain from 72V down to 0.6V. With a high voltage GaN transistor technology, power can ultimately be delivered at 48V to the socket of a microprocessor. Many benefits can be realized: the current level (I) on the board can be reduced, power dissipation (proportional to I2) on the board can be significantly reduced, form factor can be significantly reduced (at least 2×shrink, up to 10× or more).

FIG.4illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accordance with an embodiment of the present disclosure.

Referring toFIG.4, a high voltage scaled GaN device400includes a GaN layer402including 2DEG regions404and non 2DEG regions406. A p-GaN/p-InGaN/p-AlGaN field plating layer408is on the GaN layer402to provide a field-redistributing effect. N+ InGaN source or drain regions410and412are on the GaN layer402. A p-GaN, p-InGaN, p-AlGaN regrown layer418is on the field plating layer408. Gate electrodes414A and414B and a field plate electrode416are on the p-GaN, p-InGaN, p-AlGaN regrown layer418. Source or drain contacts420and422are on the N+ InGaN source or drain regions410and412. An interconnect line424couples the source or drain contact420and field plate electrode416. An insulator layer426, such as a silicon nitride (SiN) layer is included over the field plating layer408. An inter-layer dielectric (ILD) layer428is over the structure. An H2-implant shallow-trench isolation layer430is on either side of the N+ InGaN source or drain regions410and412.

FIG.5illustrates cross-sectional views of various structural options for a high voltage scaled GaN device with multi-gate technology, in accordance with an embodiment of the present disclosure.

Referring to part (A) ofFIG.5, a gate structure500for a high voltage scaled GaN device includes a GaN layer502having a 2DEG layer504. An AlGaN layer506is on the GaN layer502. A p-GaN layer508is on the AlGaN layer506. A gate electrode510is on the p-GaN layer508. The gate electrode510and the p-GaN layer508are within a dielectric layer512, such as a silicon nitride (SiN) layer.

Referring to part (B) ofFIG.5, a gate structure520for a high voltage scaled GaN device includes a GaN layer522having a 2DEG layer524. An AlGaN layer526is on the GaN layer522. A p-AlGaN layer528is on the AlGaN layer526. A gate electrode530is on the p-AlGaN layer528. The gate electrode530and the p-AlGaN layer528are within a dielectric layer532, such as a silicon nitride (SiN) layer.

Referring to part (C) ofFIG.5, a gate structure540for a high voltage scaled GaN device includes a GaN layer542having a 2DEG layer544. An AlGaN layer546is on the GaN layer542. A p-InGaN layer548is on the AlGaN layer546. A gate electrode550is on the p-InGaN layer548. The gate electrode550and the p-InGaN layer548are within a dielectric layer552, such as a silicon nitride (SiN) layer.

Referring to part (D) ofFIG.5, a gate structure560for a high voltage scaled GaN device includes a GaN layer562having a 2DEG layer564. An AlGaN layer566is on the GaN layer562. A p-AlGaN layer567is on the AlGaN layer566. A p-InGaN layer568is on the p-AlGaN layer567. A gate electrode570is on the p-InGaN layer568. The gate electrode570, the p-AlGaN layer567and the p-InGaN layer568are within a dielectric layer572, such as a silicon nitride (SiN) layer.

In an embodiment, using a p-InGaN layer can translate to higher active p-dopants being achieved. With higher active p-dopants compared to p-GaN, thinner p-InGaN can be used to deplete 2DEG in channel for e-mode. Thinner EOT enables shorter channel length, hence higher performance (lower Rory and higher drive current). In an embodiment, using a p-AlGaN layer can translate to higher barrier to electrons, although lower p-dopants. With higher energy barrier to electrons, p-AlGaN can be used to reduce the thickness of the p-doped barrier to enable shorter channel length as well as to increase the P-N junction turn-on voltage and reduce gate leakage. Heterostructures, e.g. p-InGaN/p-AlGaN/AlGaN/GaN channel can be used to achieve combinations of the characteristics described above.

FIG.6illustrates cross-sectional views of various structural options for a high voltage scaled GaN device with multi-gate technology, in accordance with another embodiment of the present disclosure.

Referring toFIG.6, a high voltage scaled GaN device600includes a GaN layer602including 2DEG regions604and non 2DEG regions606. N+ InGaN source or drain regions610and612are on the GaN layer602. A p-GaN, p-InGaN, p-AlGaN regrown layer618is on the polarization layer608to provide a field-redistribution effect. Gate electrodes614A and614B are on the p-GaN, p-InGaN, p-AlGaN regrown layer618. Source or drain contacts620and622are on the N+ InGaN source or drain regions610and612. An insulator layer626, such as a silicon nitride (SiN) layer is included over the polarization layer608. An inter-layer dielectric (ILD) layer628is over the structure. An H2-implant shallow-trench isolation layer630is on either side of the N+ InGaN source or drain regions610and612.

In an embodiment, multi-gates can extend the voltage handling capability and incur minimal increase in on-resistance and transistor drive current. Multi-gates also improve drain induced barrier leakage (DIBL), and reduce off-state leakage.

FIG.7illustrates cross-sectional views of various structural options for a high voltage scaled GaN device with multi-gate technology, in accordance with another embodiment of the present disclosure.

Referring toFIG.7, a high voltage scaled GaN device700includes a GaN layer702including 2DEG regions704and non 2DEG regions706. N+ InGaN source or drain regions710and712are on the GaN layer702. A p-GaN, p-InGaN, p-AlGaN regrown layer718is on the polarization layer708to provide a field-redistribution effect. Gate electrodes714A and714B and a field plate electrode716are on the p-GaN, p-InGaN, p-AlGaN regrown layer718. Source or drain contacts720and722are on the N+ InGaN source or drain regions710and712. An interconnect line724couples the source or drain contact720and field plate electrode716. An insulator layer726, such as a silicon nitride (SiN) layer is included over the field plating layer708. An inter-layer dielectric (ILD) layer728is over the structure. An H2-implant shallow-trench isolation layer730is on either side of the N+ InGaN source or drain regions710and712. An H2-implant region732is under a channel region of the device700.

In an embodiment, aside from providing a field-plate (FP) to redistribute the high lateral electric field on the drain side of the transistor, a p-GaN/p-InGaN/p-AlGaN field plate can inject compensating holes into the channel in the drain region to neutralized electrons that are trapped in the high field region on the drain side. High energy hydrogen atoms can be implanted in the shallow-trench isolation region to further isolate each GaN transistor active region from the rest of the wafer. Further, a hydrogen implant plane can be achieved underneath the GaN 2DEG for further isolation of GaN transistor active region from the GaN buffer and substrate. In one embodiment, voltage converter circuit topologies enabled by these devices include LLC resonant converter, switched capacitor converters, buck converters, and others.

Embodiments of the disclosure relate to gallium nitride (GaN) transistors having multiple threshold voltages and their methods of fabrication. A GaN transistor, in accordance with embodiments, includes a gallium nitride layer above a substrate, such as a silicon monocrystalline substrate. A gate stack is disposed above the GaN layer. A source region and a drain region are disposed on opposite sides of the gate stack. A polarization layer including a group III-N semiconductor is disposed on the GaN layer and beneath the gate stack. The polarization layer may have a first thickness, including a zero thickness, beneath a first gate portion of the gate stack and a second thickness greater than the first thickness beneath a second gate portion of the gate stack. The thickness of the polarization layer or lack of a polarization layer beneath the gate stack affects the threshold voltage of the overlying portion of the gate stack. By providing different thicknesses of the polarization layer beneath different portions of the gate stack, a transistor may be engineered to have two or more different threshold voltages. In an embodiment, a transistor has a threshold voltage in the range of 1V to −6V. A GaN transistor having multiple threshold voltages may be fabricated as a planar transistor or a nonplanar transistor. In embodiments of the present disclosure, a GaN transistor having two or more threshold voltages may be used to create a hybrid class A+AB power amplifier with improved linearity.

FIGS.8A-8Cillustrate a GaN transistor800in accordance with embodiments of the present disclosure.FIG.8Ais a top down view illustrating GaN transistor800whileFIG.8Bis as cross-sectional view taken through a first portion802of transistor800andFIG.8Cis a cross-sectional view taken through a section of portion804of transistor800. Transistor800includes a gallium nitride (GaN) layer810disposed above a substrate812, such as but not limited to a silicon monocrystalline substrate. A buffer layer814, such as an aluminum nitride (AlN) layer, may be disposed between substrate812and GaN layer810. GaN layer810provides a channel layer for transistor layer800. A gate stack820is disposed above the GaN layer810as illustrated inFIGS.8B and8C. The gate stack may include a gate dielectric822and a gate electrode824with the gate dielectric822between the gate electrode824and GaN layer810. In an embodiment, the gate dielectric822is a high-k gate dielectric such as but not limited to a hafnium oxide (e.g., HfO2) or aluminum oxide (e.g., Al2O3) gate dielectric layer.

A source region830and a drain region832may be disposed on opposite sides of gate stack820as illustrated inFIGS.8A-8C. In an embodiment source region830and includes a group III-N semiconductor contact834, such as but not limited to InGaN, and drain region832includes a group III-N semiconductor contact836. In an embodiment, group III-N semiconductor contacts834and836are a single crystalline group III-N semiconductor, and may be doped to an N+ conductivity (e.g., greater than 1E18 concentration) with, e.g., silicon. Transistor800has a gate length (Lg) which extends in a first direction between source region830and drain region832. When transistor800is in an “ON” state current flows between source region830and drain region832in the first direction. Transistor800has a gate width (Lw) in a second direction, perpendicular to the first direction or to the gate length direction, and parallel to the source and drain regions830and832as illustrated inFIG.8A. In an embodiment, the gate width of transistor800is between 10 and 100 microns.

Transistor800includes a polarization layer840. In an embodiment, polarization layer840is a group III-N semiconductor, such as but not limited to a group III-N semiconductor including aluminum, gallium, indium and nitrogen or AlxInyGa1−x−yN (0<x<=1, 0<=y<1). In an embodiment, x=0.83 and y=0.17, where Al0.83In0.17N is lattice-matched to GaN. In an embodiment, the polarization layer840is disposed directly on a surface811of GaN layer810which is a (0001) plane or a C-plane of gallium nitride. Depending on the composition and thickness of polarization layer840, polarization layer840may create a 2DEG layer850in the top surface of GaN layer810as illustrated inFIGS.8B and8C.

In an embodiment of the present disclosure, a first portion802of transistor800has a first gate portion826of gate stack820disposed over a first portion842of polarization layer840having a first thickness, which may be a zero thickness, while a second portion804of transistor800has a second gate portion828of gate stack820disposed over a second portion844of polarization layer840having a second thickness, wherein the second thickness is greater than the first thickness. The difference in thicknesses between the first portion842and the second portion844of polarization layer840creates a difference in the threshold voltages for the first gate portion826of gate stack820and the second gate portion828of gate stack820where the threshold voltage (VT1) of the first gate portion826is greater than the threshold voltage (VT2) of the second gate portion828. In an embodiment, the first threshold voltage (VT1) is greater than the second threshold voltage (VT2) by an amount in the range of 100 mV to 9V. In an embodiment, the first threshold voltage (VT1) is greater than the second threshold voltage (VT2) by greater than 2V.

In a specific embodiment, as shown inFIGS.8B and8C, the first portion842of polarization layer840has a thickness of zero. That is, there is no polarization layer840beneath the first gate portion826of gate stack820and the first gate portion826is disposed directly on GaN layer810as illustrated inFIG.8B. Second portion844of polarization layer840has a non-zero thickness beneath the second gate portion828of gate stack820. In an embodiment, second portion844of polarization layer840is sufficiently thick to create a 2DEG layer in the top surface of GaN layer810beneath second portion828of gate stack820. In this way, the first portion826of gate stack820has a threshold voltage (VT1) which is greater than the threshold voltage (VT2) of the second gate portion828of gate stack820. In an alternative embodiment, first portion842of polarization layer840has a zero thickness, and the second portion has a non-zero thickness, which is not sufficiently thick to create a 2DEG layer in GaN layer810beneath second gate portion828of gate stack820. Although, a 2DEG is not formed beneath the second gate portion828of gate stack820in an embodiment, the second portion828of gate stack820may still have a lower threshold voltage (VT2) than the threshold voltage (VT1) of the first gate portion826of gate stack820disposed directly on GaN layer810.

In the embodiment, the first portion842and the second portion844of polarization layer840both have a non-zero thickness. In an embodiment, the first portion842has a first non-zero thickness and a second portion844has a second non-zero thickness greater than the first thickness, wherein the first portion842is not sufficiently thick to create a 2DEG layer in GaN layer810beneath first gate portion826and wherein the second portion844of polarization layer840is also not sufficiently thick to create a 2DEG layer in GaN layer810beneath second gate portion828. In yet another embodiment, the second portion844of polarization layer840is thicker than the first portion842of polarization layer840and the first portion842and the second portion844are each sufficiently thick to create a 2DEG layer in GaN layer810beneath first gate portion826and second gate portion828, respectively. In an embodiment, the second portion844of polarization layer840is approximately 2-3 times thicker than the first portion842of polarization layer840. In a specific embodiment, the first portion842of polarization layer840includes a 1 nanometer AlN layer on the GaN layer810and a 1 nanometer AlInN layer on the 1 nanometer AlN layer, and the second portion844of polarization layer840includes a 1 nanometer AlN layer on the GaN layer810and a 3 nanometer AlInN layer on the 1 nanometer AlN layer. In an embodiment, in either case, the AlInN layer includes Al0.83In0.17N.

In another embodiment, first portion842of polarization layer840has a non-zero thickness that is insufficient to create a 2DEG layer in GaN layer810beneath first gate portion826and wherein the second portion844of polarization layer840has a thickness greater than the thickness of the first polarization layer842and is sufficient to create a 2DEG layer in GaN layer810beneath second gate portion828.

It is to be appreciated, in embodiment of the present disclosure, polarization layer840may have a third portion beneath a third gate portion wherein the third portion of the polarization layer840has a thickness greater than the thickness of the second portion844of polarization layer840which is yet thicker than the first portion842of polarization layer840. In this way, a transistor having three different threshold voltages may be obtained. A similar technique may be practiced to create a GaN transistor with four or more threshold voltages, if desired.

In an embodiment, transistor800includes a pair of insulative sidewall spacers860disposed on opposite sides of gate stack820as illustrated inFIGS.8B and8C. Sidewall spacers may be formed from any well-known material, such as but no limited to silicon oxide, silicon nitride, and silicon oxynitride. One of the sidewall spacers of the pair of sidewall spacers860is disposed on a source portion846of polarization layer840between gate stack820and source group III-N semiconductor contact834. The other sidewall spacer of the pair of sidewall spacers860is disposed on a drain portion848of polarization layer840disposed between gate stack820and drain group III-N semiconductor contact836. In an embodiment, source polarization layer846creates a 2DEG layer850in the top surface of GaN layer810and drain polarization layer848creates a 2DEG layer850in the top surface of GaN layer810as illustrated inFIGS.8B and8C. In embodiments of the present disclosure, source polarization layer846and drain polarization layer848have a thickness greater than the thickness of the second portion844of polarization layer840and greater than the thickness of the first portion842of polarization layer840which may be a zero thickness.

In an embodiment of the present disclosure, the first transistor portion802and the second transistor portion804have the same gate width. In other embodiments, the first transistor portion802has a greater or smaller gate width than second transistor portion804. In this way, the amount of current provided by the first transistor portion may differ from the amount of current provided by the second transistor portion804.

In embodiments of the present disclosure, isolation regions870may be formed in GaN layer810. Isolation regions870may surround transistor800to isolate transistor800from other devices manufactured in GaN810and/or substrate812. An interlayer dielectric872, such as but not limited to, silicon dioxide and carbon doped silicon oxide, may be disposed over transistor800. Contacts874and876, such as metal contacts, may be disposed in dielectric872to create electrical contacts to source group III-N semiconductor contact834and to drain group III-N semiconductor contact836, respectively, as illustrated inFIGS.8B and8C.

FIG.9illustrates a GaN transistor900having multiple threshold voltages in accordance with an embodiment of the present disclosure. GaN transistor900includes a plurality of first transistor portions802and a plurality of second transistor portions804along the gate width (Lw) direction of transistor900as illustrated inFIG.9. Each of the first transistor portions802and each of the second transistor portions804may include transistor structures as illustrated and described with respect toFIGS.8B and8C, respectively. That is, in an embodiment, each first transistor portion802of the plurality of first transistor portions includes a first portion842of polarization layer840having a first thickness, including possibly a zero thickness, and each second transistor portion804of the plurality of second transistor portions includes a second portion844of polarization layer840having a second thickness wherein the second thickness is greater than the first thickness. In an embodiment, the first transistor portions802and the second transistor portions804of GaN transistor900alternate or interleave with one another along the gate width (Lw) direction ofFIG.9. In an embodiment, transistor900includes two first transistor portions802and two second transistor portion804. In another embodiment, transistor900includes three first transistor portions802and three second transistor portions804. In yet another embodiment, transistor900includes three or more first transistors portions802and three or more second transistor portions804. In embodiments, transistor900has more first transistor portions802than second transistor portions804. In yet embodiment, transistor900has more second transistor portions804than first transistor portions802. In an embodiment, interleaving provides a plurality of parallel channels for transistor900.

FIG.10illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor1000having multiple threshold voltages in accordance with embodiments of the present disclosure. Transistor1000includes a GaN fin1010disposed above a substrate1012, such as but not limited to a monocrystalline silicon substrate, silicon carbide substrate, or a sapphire substrate. A buffer layer1014may be disposed between GaN fin1010and substrate1012. Fin1010has a pair of laterally opposite sidewalls1016and a top surface1018between the laterally opposite sidewalls. In an embodiment, top surface1018of GaN fin1010is a (1000) plane or a c-plane of GaN. An oxide layer, such as an oxide of a shallow trench isolation (STI) may be disposed above substrate1012and may surround a bottom portion of fin1010, so that an upper portion of fin1010extends above oxide1017as illustrated inFIG.10.

A polarization layer1040is disposed on the top surface1018of fin1010. In an embodiment, polarization layer1010is a group III-N semiconductor material, such as but not limited to AlGaInN, AlGaN, and AlInN. In an embodiment polarization layer1040is not formed on sidewall1016of fin1010. A gate stack1020is disposed over polarization layer1040on the top surface1018of fin1010and is disposed over the sidewalls1016of fin1010as illustrated inFIG.10. Gate stack1020may include a gate dielectric1022, such as but not limited to hafnium oxide (e.g. HfO2) or aluminum oxide (e.g. Al2O3) and a gate electrode1024such as a metal gate electrode. Gate dielectric1022may be disposed between gate electrode1024and sidewalls1016of gate electrode1024and between gate electrode1024and polarization layer1040on the top surface of GaN fin1010. A source region and a drain region (not shown) may be disposed on opposite sides (into and out of the page) of the gate stack1020as is well-known in the art. The source and drain regions each may include a group III-N semiconductor contact, such as but not limited to InGaN.

In an embodiment, polarization layer1040is of a sufficient thickness to create a 2DEG layer in the top surface of fin1010as illustrated inFIG.10. In an alternative embodiment, polarization layer1040has a thickness which is insufficient to create a 2DEG layer in the top surface of fin1010, however, is of a sufficient thickness in order to provide a different threshold voltage for the portion of the gate stack1020over the top surface1018of fin1010relative to the threshold voltage of the gate stack1020adjacent to the sidewalls1016of fin1010. In either case, transistor1000has two different threshold voltages, a first threshold voltage (VT1) associated with a portion of the gate stack1020over/adjacent to the sidewalls1016of fin1010and second threshold voltage (VT2), such as a lower threshold voltage, associated with the portion of the gate stack1020over polarization layer1040and top surface1018of fin1010. The width (W) of and the height (H) of the portion of fin1010may be chosen to create the desired amount of current provided by the top surface1018of fin1010relative to the sidewalls1016of fin1010. In an embodiment, an additional fin or fins including a top polarization layer may be included to increase the current carrying capability of transistor1000, an example of which is shown inFIG.10.

As described throughout the present application, a substrate may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, a substrate is described herein is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 97%. In another embodiment, a bulk substrate is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. A bulk substrate may alternatively be composed of a group III-V material. In an embodiment, a bulk substrate is composed of a group III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, a bulk substrate is composed of a group III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

As described throughout the present application, isolation regions such as shallow trench isolation regions or sub-fin isolation regions may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or to isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, an isolation region is composed of one or more layers of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, carbon-doped silicon nitride, or a combination thereof.

As described throughout the present application, gate lines or gate structures may be composed of a gate electrode stack which includes a gate dielectric layer and a gate electrode layer. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of a semiconductor substrate. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride. In some implementations, a portion of the gate dielectric is a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.

In one embodiment, a gate electrode is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer. The gate electrode layer may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

As described throughout the present application, spacers associated with gate lines or electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

In an embodiment, approaches described herein may involve formation of a contact pattern which is very well aligned to an existing gate pattern while eliminating the use of a lithographic operation with exceedingly tight registration budget. In one such embodiment, this approach enables the use of intrinsically highly selective wet etching (e.g., versus dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in other approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.

Furthermore, a gate stack structure may be fabricated by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF6. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.

In an embodiment, one or more approaches described herein contemplate essentially a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structure. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature anneal of at least a portion of the permanent gate stack. For example, in a specific such embodiment, an anneal of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed, is performed at a temperature greater than approximately 600 degrees Celsius. The anneal is performed prior to formation of the permanent contacts.

In some embodiments, the arrangement of a semiconductor structure or device places a gate contact over portions of a gate line or gate stack over isolation regions. However, such an arrangement may be viewed as inefficient use of layout space. In another embodiment, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region. In general, prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via, one or more embodiments of the present disclosure include first using a gate aligned trench contact process. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e.g., for integrated circuit fabrication. In an embodiment, a trench contact pattern is formed as aligned to an existing gate pattern. By contrast, other approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches. For example, another process may include patterning of a poly (gate) grid with separate patterning of contact features.

It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. For example, in one embodiment, dummy gates need not ever be formed prior to fabricating gate contacts over active portions of the gate stacks. The gate stacks described above may actually be permanent gate stacks as initially formed. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a trigate device, an independently accessed double gate device, a FIN-FET, a nanowire, or a nanoribbon.

Additional or intermediate operations for FEOL layer or structure fabrication may include standard microelectronic fabrication processes such as lithography, etch, thin films deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, or any other associated action with microelectronic component fabrication. Also, it is to be appreciated that the process operations described for the preceding process flows may be practiced in alternative sequences, not every operation need be performed or additional process operations may be performed, or both.

It is to be appreciated that the layers and materials described above in association with back-end-of-line (BEOL) structures and processing may be formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials, such as substrates including germanium, carbon, or group III-V materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the structures depicted may be fabricated on underlying lower level interconnect layers.

Although the preceding methods of fabricating a metallization layer, or portions of a metallization layer, of a BEOL metallization layer are described in detail with respect to select operations, it is to be appreciated that additional or intermediate operations for fabrication may include standard microelectronic fabrication processes such as lithography, etch, thin films deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, or any other associated action with microelectronic component fabrication. Also, it is to be appreciated that the process operations described for the preceding process flows may be practiced in alternative sequences, not every operation need be performed or additional process operations may be performed or both.

In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.

In an embodiment, as is also used throughout the present description, hardmask materials are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, different hardmask materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hardmask material includes a metal species. For example, a hardmask or other overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride). Potentially lesser amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hardmask layers known in the arts may be used depending upon the particular implementation. The hardmask layers maybe formed by CVD, PVD, or by other deposition methods.

FIG.11illustrates a computing device1100in accordance with one implementation of the disclosure. The computing device1100houses a board1102. The board1102may include a number of components, including but not limited to a processor1104and at least one communication chip1106. The processor1104is physically and electrically coupled to the board1102. In some implementations the at least one communication chip1106is also physically and electrically coupled to the board1102. In further implementations, the communication chip1106is part of the processor1104.

The processor1104of the computing device1100includes an integrated circuit die packaged within the processor1104. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more structures, such as integrated circuit structures built in accordance with implementations of the disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers or memory to transform that electronic data, or both, into other electronic data that may be stored in registers or memory, or both.

The communication chip1106also includes an integrated circuit die packaged within the communication chip1106. In accordance with another implementation of the disclosure, the integrated circuit die of the communication chip is built in accordance with implementations of the disclosure.

In further implementations, another component housed within the computing device1100may contain an integrated circuit die built in accordance with implementations of embodiments of the disclosure.

FIG.12illustrates an interposer1200that includes one or more embodiments of the disclosure. The interposer1200is an intervening substrate used to bridge a first substrate1202to a second substrate1204. The first substrate1202may be, for instance, an integrated circuit die. The second substrate1204may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer1200is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer1200may couple an integrated circuit die to a ball grid array (BGA)1206that can subsequently be coupled to the second substrate1204. In some embodiments, the first and second substrates1202/1204are attached to opposing sides of the interposer1200. In other embodiments, the first and second substrates1202/1204are attached to the same side of the interposer1200. And in further embodiments, three or more substrates are interconnected by way of the interposer1200.

The interposer1200may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer1200may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer1200may include metal interconnects1208and vias1210, including but not limited to through-silicon vias (TSVs)1212. The interposer1200may further include embedded devices1214, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer1200. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer1200or in the fabrication of components included in the interposer1200.

FIG.13is an isometric view of a mobile computing platform1300employing an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

The mobile computing platform1300may be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, mobile computing platform1300may be any of a tablet, a smart phone, laptop computer, etc. and includes a display screen1305which in the exemplary embodiment is a touchscreen (capacitive, inductive, resistive, etc.), a chip-level (SoC) or package-level integrated system1310, and a battery1313. As illustrated, the greater the level of integration in the system1310enabled by higher transistor packing density, the greater the portion of the mobile computing platform1300that may be occupied by the battery1313or non-volatile storage, such as a solid state drive, or the greater the transistor gate count for improved platform functionality. Similarly, the greater the carrier mobility of each transistor in the system1310, the greater the functionality. As such, techniques described herein may enable performance and form factor improvements in the mobile computing platform1300.

The integrated system1310is further illustrated in the expanded view1320. In the exemplary embodiment, packaged device1377includes at least one memory chip (e.g., RAM), or at least one processor chip (e.g., a multi-core microprocessor and/or graphics processor) fabricated according to one or more processes described herein or including one or more features described herein. The packaged device1377is further coupled to the board1360along with one or more of a power management integrated circuit (PMIC)1315, RF (wireless) integrated circuit (RFIC)1325including a wideband RF (wireless) transmitter and/or receiver (e.g., including a digital baseband and an analog front end module further includes a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller thereof1311. Functionally, the PMIC1315performs battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to the battery1313and with an output providing a current supply to all the other functional modules. As further illustrated, in the exemplary embodiment, the RFIC1325has an output coupled to an antenna to provide to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. In alternative implementations, each of these board-level modules may be integrated onto separate ICs coupled to the package substrate of the packaged device1377or within a single IC (SoC) coupled to the package substrate of the packaged device1377.

In another aspect, semiconductor packages are used for protecting an integrated circuit (IC) chip or die, and also to provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support larger circuit density. Furthermore, the demand for higher performance devices results in a need for an improved semiconductor package that enables a thin packaging profile and low overall warpage compatible with subsequent assembly processing.

In an embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount a die to a ceramic or organic package substrate. In particular, C4 solder ball connections can be implemented to provide flip chip interconnections between semiconductor devices and substrates. A flip chip or Controlled Collapse Chip Connection (C4) is a type of mounting used for semiconductor devices, such as integrated circuit (IC) chips, MEMS or components, which utilizes solder bumps instead of wire bonds. The solder bumps are deposited on the C4 pads, located on the top side of the substrate package. In order to mount the semiconductor device to the substrate, it is flipped over with the active side facing down on the mounting area. The solder bumps are used to connect the semiconductor device directly to the substrate.

Processing a flip chip may be similar to conventional IC fabrication, with a few additional operations. Near the end of the manufacturing process, the attachment pads are metalized to make them more receptive to solder. This typically consists of several treatments. A small dot of solder is then deposited on each metalized pad. The chips are then cut out of the wafer as normal. To attach the flip chip into a circuit, the chip is inverted to bring the solder dots down onto connectors on the underlying electronics or circuit board. The solder is then re-melted to produce an electrical connection, typically using an ultrasonic or alternatively reflow solder process. This also leaves a small space between the chip's circuitry and the underlying mounting. In most cases an electrically-insulating adhesive is then “underfilled” to provide a stronger mechanical connection, provide a heat bridge, and to ensure the solder joints are not stressed due to differential heating of the chip and the rest of the system.

In other embodiments, newer packaging and die-to-die interconnect approaches, such as through silicon via (TSV) and silicon interposer, are implemented to fabricate high performance Multi-Chip Module (MCM) and System in Package (SiP) incorporating an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

Thus, embodiments of the present disclosure include gallium nitride (GaN) integrated circuit technology.

The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications.

Example embodiment 1: An integrated circuit structure includes a layer or substrate including gallium and nitrogen. A first plurality of electrodes is over the layer or substrate. A resonator layer is on the first plurality of electrodes, the resonator layer including aluminum and nitrogen. A second plurality of electrodes is on the resonator layer. Individual ones of the second plurality of electrodes are vertically over and aligned with corresponding individual ones of the first plurality of electrodes.

Example embodiment 2: The integrated circuit structure of example embodiment 1, wherein the resonator layer is surrounded by and is in contact with a dielectric layer.

Example embodiment 3: The integrated circuit structure of example embodiment 1, wherein the resonator layer is in a cavity in a dielectric layer.

Example embodiment 4: The integrated circuit structure of example embodiment 1, 2 or 3, wherein the first plurality of electrodes includes two electrodes, and the second plurality of electrodes includes two electrodes.

Example embodiment 5: The integrated circuit structure of example embodiment 1, 2 or 3, wherein the first plurality of electrodes includes three electrodes, and the second plurality of electrodes includes three electrodes.

Example embodiment 6: A computing device includes a board, and a component coupled to the board. The component includes an integrated circuit structure including a layer or substrate including gallium and nitrogen. A first plurality of electrodes is over the layer or substrate. A resonator layer is on the first plurality of electrodes, the resonator layer including aluminum and nitrogen. A second plurality of electrodes is on the resonator layer. Individual ones of the second plurality of electrodes are vertically over and aligned with corresponding individual ones of the first plurality of electrodes.

Example embodiment 7: The computing device of example embodiment 6, further including a memory coupled to the board.

Example embodiment 8: The computing device of example embodiment 6 or 7, further including a communication chip coupled to the board.

Example embodiment 9: The computing device of example embodiment 6, 7 or 8, further including a camera coupled to the board.

Example embodiment 10: The computing device of example embodiment 6, 7, 8 or 9, wherein the component is a packaged integrated circuit die.

Example embodiment 11: The computing device of example embodiment 6, 7, 8, 9 or 10, wherein the resonator layer is surrounded by and is in contact with a dielectric layer.

Example embodiment 12: The computing device of example embodiment 6, 7, 8, 9 or 10, wherein the resonator layer is in a cavity in a dielectric layer.

Example embodiment 13: The computing device of example embodiment 6, 7, 8, 9, 10, 11 or 12, wherein the first plurality of electrodes includes two electrodes, and the second plurality of electrodes includes two electrodes.

Example embodiment 14: The computing device of example embodiment 6, 7, 8, 9, 10, 11 or 12, wherein the first plurality of electrodes includes three electrodes, and the second plurality of electrodes includes three electrodes.

Example embodiment 15: A method of fabricating an integrated circuit structure includes forming a layer or substrate including gallium and nitrogen. A first plurality of electrodes is formed over the layer or substrate. A resonator layer is formed on the first plurality of electrodes, the resonator layer including aluminum and nitrogen. A second plurality of electrodes is formed on the resonator layer. Individual ones of the second plurality of electrodes are vertically over and aligned with corresponding individual ones of the first plurality of electrodes.

Example embodiment 16: The method of example embodiment 15, further including coupling the first plurality of electrodes to ground, and coupling one or more of the second plurality of electrodes to an input signal.

Example embodiment 17: The method of example embodiment 15 or 16, wherein the resonator layer is surrounded by and is in contact with a dielectric layer.

Example embodiment 18: The method of example embodiment 15 or 16, wherein the resonator layer is in a cavity in a dielectric layer.

Example embodiment 19: The method of example embodiment 15, 16, 17 or 18, wherein the first plurality of electrodes includes two electrodes, and the second plurality of electrodes includes two electrodes.

Example embodiment 20: The method of example embodiment 15, 16, 17 or 18, wherein the first plurality of electrodes includes three electrodes, and the second plurality of electrodes includes three electrodes.