Fabrication of CMOS transistors having differentially stressed spacers

CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

BACKGROUND

The present invention relates to CMOS transistors, and more specifically, to n and p channel metal oxide semiconductor (MOS) field effect transistors (FET's) having differentially stressed spacers and differentially stressed channels.

Stressor layers have been one of the techniques used to increase device performance. However, due to the location of the spacers for short channel effect control, the stressor layers are typically located a few hundred angstroms away from the channel over a spacer thereby limiting the extent of performance improvement in carrier mobility in the channel.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, a method for forming n and p field effect transistors is described comprising selecting a substrate having p and n regions for forming n and p field effect transistors respectively therein, forming a first gate dielectric and a first poly silicon gate electrode having sidewalls on at least one p region, forming a second gate dielectric and a second poly silicon gate electrode having sidewalls on at least one n region, forming a first hard mask over the second gate dielectric, the second poly silicon gate electrode and the n region, forming a tensely stressed film over the first poly silicon gate electrode, etching the tensely stressed film to provide a tensely stressed spacer on the sidewalls of the first poly silicon gate electrode, forming a n type halo region in the p region on opposite sides of the first poly silicon gate electrode, forming a n type source and drain extension in the p region overlapping the n type halo regions on opposite sides of the first poly silicon gate electrode, removing the first mask, forming a second mask over the p region, n type source and drain extensions, n type halo regions, tensile stressed spacers and first poly silicon gate electrode, forming a compressively stressed film over the second poly silicon gate electrode, etching the compressively stressed film to provide a compressively stressed spacer on the sidewalls of the second poly silicon gate electrode, forming a p type halo region in the n region on opposite sides of the second poly silicon gate electrode, forming a p type source and drain extension in the n region overlapping the p type halo regions on opposite sides of the second poly silicon gate electrode, and removing the second mask.

The invention further provides a n type field effect transistor comprising a substrate having a p region, a first gate dielectric, a first poly silicon gate electrode there over having sidewalls, a tensely stressed spacer on the sidewalls of the first poly silicon gate electrode, a n type halo region in the p region on opposite sides of the first poly silicon gate electrode, a n type source and drain extension overlapping the n type halo regions on opposite sides of the first poly silicon gate electrode, and electrical contacts to the source extension, drain extension and gate electrode.

The invention further provides a p type field effect transistor comprising a substrate having a n region, a first gate dielectric, a first poly silicon gate electrode there over having sidewalls, a compressively stressed spacer on the sidewalls of the first poly silicon gate electrode, a p type halo region in the n region on opposite sides of the first poly silicon gate electrode, a p type source and drain extension overlapping the p type halo regions on opposite sides of the first poly silicon gate electrode, and electrical contacts to the source extension, drain extension and gate electrode.

DETAILED DESCRIPTION

Referring now to the drawing,FIG. 1shows a cross-section view of a semiconductor substrate12having p regions14and15for forming a n type metal oxide semiconductor (NMOS) field effect transistor (FET) and n regions16and17for forming a p type metal oxide semiconductor (PMOS) FET respectively therein. N region16and p region14are electrically isolated from each other by an isolation trench20of dielectric such as an oxide. P region14and n region17are electrically isolated from each other by an isolation trench22of dielectric such as an oxide. N region17and p region15are electrically isolated from each other by an isolation trench24of dielectric such as an oxide. P regions14and15and n regions16and17may be single crystal Si, SiGe, SiC, Ge, GaAs and combinations thereof and typically with respect to a top view, regions14-17have a square or rectangular shape.

A first gate dielectric25and first poly silicon gate electrode26are formed on p region14. A second gate dielectric27and second poly silicon gate electrode28is formed on n region17. First poly silicon gate electrode26and second poly silicon gate28may be doped n or p type up to 5×1021atoms/cm3. For p type doping, BF2or BF3may be used. For n type doping, an As containing gas may be used.

A first hard mask30which may be for example an oxide, a nitride such as a silicon nitride or an oxide nitride is formed over n region17, over second gate dielectric27and second poly silicon gate electrode28. First hard mask30functions to protect n region17, second gate dielectric27and second poly silicon gate electrode28from damage during processing in p region14. As shown inFIG. 1, first hard mask30completely covers n region17and overlaps isolation trenches22and24which together surround and electrically isolate p region17. A mask comprising photo resist may be used in certain situations in place of first hard mask30.

FIG. 2shows a cross section view of tensely stressed film34formed over n region16, isolation trench20, p region14, first gate dielectric25, first poly silicon gate electrode26, isolation trench22, mask30, isolation trench24and p region15. Tensely stressed film34may be a conformal coating having a thickness in the range from 2 nm to 15 nm formed of oxide nitride, nitride oxide and under conditions to provide a tensile stress on sidewalls29and31of first poly silicon gate electrode26which in turn provides a tensile stress in channel39in p region14underneath first gate dielectric25and first poly silicon gate electrode26. Channel39will function as the channel of NMOS FET86shown inFIG. 6.

FIG. 3is a cross-section view ofFIG. 2after etching tensely stressed film34to form tensely stressed spacers36and38on sidewalls29and31of first poly silicon gate electrode26. Tensely stressed spacers36and38may be formed directly on sidewalls of first poly silicon gate electrode26and function to tensely stress poly silicon gate electrode26in the out of plane direction with respect to the major surface of substrate12. In turn, tensely stressed poly silicon gate electrode26provides tensile stress to channel39directly below gate electrode26. Tensely stressing channel39improves electron carrier mobility in channel39. Tensely stressed spacers40and42are also formed on the sidewalls of mask30at the same time spacers36and38are formed. Tensely stressed film34is preferably etched by Reactive Ion Etching (REI) which etches horizontal surfaces (i.e. parallel with respect to the major surface of substrate12) and the top edges of vertical layers. It is noted that tensely stressed film34is completely etched on the horizontal surfaces of mask30which facilitates the removal of mask30during later processing.

After tensely stressed spacers36and38are formed; n type halo regions44and46are formed on opposite sides of first poly silicon gate electrode26. Halo regions44and46are positioned with respect to tensely stressed spacers36and38. Next, n type source and drain extensions48and50are formed in p region14overlapping the halo regions on opposite sides of first poly silicon gate electrode26. Next, hard mask30is removed by a chemical etch for example by a timed chemical etch. Tensely stressed spacers40and42on either side of mask30are removed when mask30is removed.

FIG. 4is a cross-section view similar toFIG. 3except oxide layers51and52are formed first on sidewalls29and31of first poly silicon gate electrode26prior to forming tensely stressed film34. Oxide layers51and52may be formed by oxidizing the exposed surface of first poly silicon gate electrode26. Oxide layers51and52have a thickness in the range from 0.5 nm to 5 nm and are preferably in the range from 1 nm to 3 nm. Oxide layers51and52results from processing other areas on substrate12without a protective mask over sidewalls29and31or is formed to promote adhesion to sidewalls29and31of first poly silicon gate electrode26of subsequently formed tensely stressed spacers36and38.

FIG. 5is a cross-section view ofFIG. 4after removal of mask30to expose region17and second poly silicon gate electrode28to further processing. A mask56is formed over p region14, source and drain extensions48and50, halo regions44and46, spacers36and38, oxide layers51and52, and first poly silicon gate electrode26to protect them from damage during processing in n region17to form PMOS FET88shown inFIG. 6.

FIG. 5shows oxide layers58and60formed on sidewalls57and59of second poly silicon gate electrode28. Oxide layers58and60may be formed by oxidizing the exposed surface of second poly silicon gate electrode28. Oxide layers58and60may have a thickness in the range from 0.5 nm to 5 nm and preferably in the range from 1 nm to 3 nm. A compressively stressed film (not shown) is formed over mask56, region17, oxide layers58and60and second poly silicon gate electrode28. The compressively stressed film (not shown) is etched by RIE to form compressively stressed spacers64and66on oxide layers58and60on sidewalls57and59respectively of second poly silicon gate electrode28.

Compressively stressed spacers68and70are also formed on mask56at the same time compressively stressed spacers64and66are formed. Compressively stressed spacers64and66function to compress sidewalls57and59of second poly silicon gate electrode28and channel72below which improves the carrier mobility of channel72below shown inFIG. 5with respect to hole carriers. Compressively stressed spacers64and66also function to position during ion implantation halo regions74and76and source/drain extensions78and80with respect to second poly silicon gate electrode28.

After compressively stressed spacers64and66are formed, p type halo regions74and76are formed on opposite sides of second poly silicon gate electrode28. Next, p type source and drain extensions78and80are formed overlapping halo regions74and76on opposite sides of second poly silicon gate electrode28.

FIG. 6is a cross-section view of completed NMOS FET86and PMOS FET88after mask56is removed. Hard mask56may be removed by a chemical etch for example by a timed chemical etch. Compressively stressed spacers68and70on either side of mask56are removed at the same time mask56is removed.

A self aligned silicide process may be used to form silicide regions82-85in source extension48/halo region44, drain extension50/halo region46, source extension78/halo region74and drain extension80/halo region76, respectively, shown inFIG. 7. In the silicide process a layer of metal (not shown) is formed over substrate12and exposed silicon regions14and17shown inFIG. 6. The layer of metal which may be, for example, Ni (not shown) is heated and reacted with the exposed Si regions to form nickel silicide. The unreacted metal is removed by a selective etch. Nickel silicate forms an ohmic contact to source extensions48,50,78and80and halo regions44,46,74and76. The metal may react with the upper surface of first and second poly silicon gate electrodes26and28to form silicide regions which are not shown inFIG. 7. The upper surface may be lowered and silicide regions removed (if present) on poly silicon gate electrodes26and28during chemical mechanical processing (CMP).

FIG. 7is a cross-section view showing electrical contacts to source extension48and drain extension50of NMOS FET86and to source extension78and drain extension80of PMOS FET88. Dielectric layer89may be formed over NMOS FET86and PMOS FET88which may be planarized by CMP to expose upper surface81and87respectively of first and second poly silicon gate electrodes26and28for making electrical contact thereto or for removal of first and second poly silicon gate electrodes26and28such as by chemical etching in a replacement gate process to replace the material of the respective gate dielectric and gate electrode or just the gate electrode which may be replaced with poly silicon or metal. The gate dielectric may be replaced with a gate dielectric known in the art. If silicide regions are formed on upper surface81and87respectively of first and second poly silicon gate electrodes26and28, the silicide regions may be removed by CMP or remain after CMP by discontinuing CMP at the proper time before removal of the silicide regions.

Openings90,92,94and96may be formed in dielectric layer89to source extension48, drain extension50, source extension78, and drain extension80, respectively. Openings90,92,94and96may be filled with a conductor such as W to form contacts98and100to source extension48and drain extension50respectively of NMOS FET86and form contacts102and104to source extension78and drain extension80respectively of PMOS FET88.

InFIGS. 2-7, like references are used for similar structure or apparatus shown in an earlier figure.

While there has been described and illustrated a method for forming n and p channel MOS FETs having differentially stressed spacers and transistor channels, it will be apparent to those skilled in the art that modifications and variations are possible without deviating from the broad scope of the invention which shall be limited solely by the scope of the claims appended hereto.