Detrapping electrons to prevent quick charge loss during program verify operations in a memory device

Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to detrapping electrons to prevent quick charge loss during program verify operations in a memory device.

BACKGROUND

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to detrapping electrons to prevent quick charge loss during program verify operations in a memory device of a memory sub-system. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction withFIG. 1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, offers storage in the form of compact, high density configurations. A non-volatile memory device is a package of one or more dice, each including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. Each block can include a number of sub-blocks, where each sub-block is defined by an associated pillar (e.g., a vertical conductive trace) extending from a shared bit line. Memory pages (also referred to herein as “pages”) store one or more bits of binary data corresponding to data received from the host system. To achieve high density, a string of memory cells in a non-volatile memory device can be constructed to include a number of memory cells at least partially surrounding a pillar of poly-silicon channel material (i.e., a channel region). The memory cells can be coupled to access lines, which are commonly referred to as “word lines,” often fabricated in common with the memory cells, so as to form an array of strings in a block of memory. The compact nature of certain non-volatile memory devices, such as 3D flash NAND memory, means word lines are common to many memory cells within a block of memory.

During a programming operation, a selected memory cell(s) can be programmed with the application of a programming voltage to a selected word line. In some cases, a series of incrementing voltage programming pulses are applied to the selected word line to increase a charge level, and thereby a threshold voltage, of each memory cell connected to that word line. After each programming pulse, or after a number of programming pulses, a program verify operation is performed to determine if the threshold voltage of the memory cell(s) has increased to a desired programming level. After the programming operation is complete, the programmed memory cell(s) can experience multiple forms of charge loss that can cause defects in the data retention characteristics of the memory cell(s), such as single bit charge loss, intrinsic charge loss, and quick charge loss. Quick charge loss (QLC) is the result of electrons trapped in a tunnel oxide layer, also referred to herein as a “band engineering (BE)” layer, after the application of a programming pulse moving back into the channel region of the string of memory cells. When a cell passes the program verify operation, the programmed threshold voltage appears to be higher due to the trapped charge in the tunnel oxide layer. When the memory cell is later read after the programming operation has been completed, however, the cell can have a threshold voltage that is lower than the threshold voltage obtained during the program verify operation due to the charge in the tunnel oxide layer leaking out to the channel region. This can require an enlargement of the threshold voltage distribution in order to accommodate all possible threshold voltages for a given state, and can lead to a higher error rate occurring during any subsequent read operation.

Certain memory devices attempt to mitigate quick charge loss through application of a negative gate bias voltage before the program verify operation. This voltage can detrap some of the electrons trapped in the tunnel oxide layer (i.e., allow those electrons to flow out into the channel region) so that some of the quick charge loss occurs before the sensing during the program verify operation. The application of the negative gate bias voltage, however, can also cause detrapping of electrons in the channel region itself. The detrapping in the channel region leads to changes in the threshold voltages of the memory cells in the string, thereby negatively impacting the read window budget (RWB) between voltage distributions of the memory cells and an increased read error rate. These devices do not separate the detrapping of electrons from the tunnel oxide layer and from the channel region so that they are not occurring at the same time either before or during the program verify operation.

Aspects of the present disclosure address the above and other deficiencies by detrapping electrons to prevent quick charge loss during program verify operations in a memory device. In one embodiment, processing logic in a memory device causes a negative voltage signal (e.g., −1 volt) to be applied to a selected word line (i.e., the word line being programmed (WLn)) of a block of a memory array of the memory device during a certain interval of a program verify phase of a programming operation to enhance detrapping of electrons from the tunnel oxide layer of the memory device. In one embodiment, the negative voltage signal is applied at the beginning of the program verify phase, such as before a positive pass voltage (i.e., Vpassr) is applied to the selected word line. Shortly after detrapping, the voltage signal applied to the selected word line, unselected word lines and a select gate device is ramped up to the pass voltage, which will not only discharge channel boosting due to the pass voltage ramping, but also cause electron trapping inside the poly-silicon channel region of the memory device. The magnitude of the pass voltage is generally not high enough to cause electron trapping in the tunnel oxide layer. In another embodiment, the negative voltage signal is applied at the end of the program verify phase, such as after the pass voltage and one or more verify voltages are applied to the selected word line. The negative voltage signal will detrap electrons from the tunnel oxide layer and from the channel region. During subsequent program operations, extra electron injection due to prior detrapping can program some electrons to a storage nitride layer rather than completely filling the tunnel oxide layer traps. Thus, at the end of the program operation, there are fewer electrons in the tunnel oxide layer traps, and since the negative voltage signal is not applied between the program phase and the program verify phase, the channel region traps remain filled.

Advantages of this approach include, but are not limited to, improved performance in the memory sub-system. In the manner described herein, the separation in time between the detrapping of electrons from the tunnel oxide layer and from the channel region increases the read window budget between voltage distributions in the memory array. This leads to a lower error rate during subsequently performed read operations, and improved reliability and data retention in the memory device. Accordingly, the overall quality of service level of the memory sub-system is improved.

In some embodiments, the memory devices130include local media controllers135that operate in conjunction with memory sub-system controller115to execute operations on one or more memory cells of the memory devices130. An external controller (e.g., memory sub-system controller115) can externally manage the memory device130(e.g., perform media management operations on the memory device130). In some embodiments, a memory device130is a managed memory device, which is a raw memory device130having control logic (e.g., local controller135) on the die and a controller (e.g., memory sub-system controller115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. Memory device130, for example, can represent a single die having some control logic (e.g., local media controller135) embodied thereon. In some embodiments, one or more components of memory sub-system110can be omitted.

In one embodiment, memory sub-system110includes a memory device program management component113that can oversee, control, and/or manage data access operations, such as program operations, performed on a non-volatile memory device, such as memory device130, of memory sub-system110. A program operation, for example, can include a number of phases, such as a program phase and a program verify phase. Program management component113is responsible for applying certain voltages (or indicating which voltages to apply) to memory device130during the program operation. For example, during the program phase, program management component113can cause a program voltage to be applied to a first selected word line (i.e., the word line being programmed (WLn)) of a block of a memory array of memory device130to program a corresponding first memory cell in a string of memory cells in the block to a target voltage (i.e., a voltage representing the data to be stored in the memory cell). During the program verify phase, program management component113can cause a program verify voltage to be applied to the first selected word line to sense the voltage level of the corresponding memory cell. In one embodiment, in order to enhance detrapping of electrons from a tunnel oxide layer of the memory device, during the program verify phase, program management component113can further cause a negative voltage signal to be applied to the first selected word line. Depending on the embodiment, the negative voltage signal can be applied either at a beginning of the program verify phase (i.e., before a positive pass voltage signal is applied to the first selected word line) or at an end of the program verify phase (i.e., after a positive pass voltage signal and one or more program verify voltage signals are applied to the selected word line). Further details with regards to the operations of the program management component113are described below.

FIG. 2Ais a simplified block diagram of a first apparatus, in the form of a memory device130, in communication with a second apparatus, in the form of a memory sub-system controller115of a memory sub-system (e.g., memory sub-system110ofFIG. 1), according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The memory sub-system controller115(e.g., a controller external to the memory device130), may be a memory controller or other external host device.

Memory device130includes an array of memory cells204logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a word line) while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells and a single data line may be associated with more than one logical column. Memory cells (not shown inFIG. 2A) of at least a portion of array of memory cells204are capable of being programmed to one of at least two target data states.

Row decode circuitry208and column decode circuitry210are provided to decode address signals. Address signals are received and decoded to access the array of memory cells204. Memory device130also includes input/output (I/O) control circuitry260to manage input of commands, addresses and data to the memory device130as well as output of data and status information from the memory device130. An address register214is in communication with I/O control circuitry260and row decode circuitry208and column decode circuitry210to latch the address signals prior to decoding. A command register224is in communication with I/O control circuitry260and local media controller135to latch incoming commands.

A controller (e.g., the local media controller135internal to the memory device130) controls access to the array of memory cells204in response to the commands and generates status information for the external memory sub-system controller115, i.e., the local media controller135is configured to perform access operations (e.g., read operations, programming operations and/or erase operations) on the array of memory cells204. The local media controller135is in communication with row decode circuitry208and column decode circuitry210to control the row decode circuitry208and column decode circuitry210in response to the addresses. In one embodiment, local media controller134includes program management component113, which can implement the detrapping of electrons to prevent quick charge loss during program verify operations in memory device130.

The local media controller135is also in communication with a cache register218. Cache register218latches data, either incoming or outgoing, as directed by the local media controller135to temporarily store data while the array of memory cells204is busy writing or reading, respectively, other data. During a program operation (e.g., write operation), data may be passed from the cache register218to the data register270for transfer to the array of memory cells204; then new data may be latched in the cache register218from the I/O control circuitry260. During a read operation, data may be passed from the cache register218to the I/O control circuitry260for output to the memory sub-system controller115; then new data may be passed from the data register270to the cache register218. The cache register218and/or the data register270may form (e.g., may form a portion of) a page buffer of the memory device130. A page buffer may further include sensing devices (not shown inFIG. 2A) to sense a data state of a memory cell of the array of memory cells204, e.g., by sensing a state of a data line connected to that memory cell. A status register222may be in communication with I/O control circuitry260and the local memory controller135to latch the status information for output to the memory sub-system controller115.

Memory device130receives control signals at the memory sub-system controller115from the local media controller135over a control link232. For example, the control signals can include a chip enable signal CE #, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE #, a read enable signal RE #, and a write protect signal WP #. Additional or alternative control signals (not shown) may be further received over control link232depending upon the nature of the memory device130. In one embodiment, memory device130receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controller115over a multiplexed input/output (I/O) bus236and outputs data to the memory sub-system controller115over I/O bus236.

For example, the commands may be received over input/output (I/O) pins [7:0] of I/O bus236at I/O control circuitry260and may then be written into command register224. The addresses may be received over input/output (I/O) pins [7:0] of I/O bus236at I/O control circuitry260and may then be written into address register214. The data may be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry260and then may be written into cache register218. The data may be subsequently written into data register270for programming the array of memory cells204.

In an embodiment, cache register218may be omitted, and the data may be written directly into data register270. Data may also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference may be made to I/O pins, they may include any conductive node providing for electrical connection to the memory device130by an external device (e.g., the memory sub-system controller115), such as conductive pads or conductive bumps as are commonly used.

It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device130ofFIG. 2Ahas been simplified. It should be recognized that the functionality of the various block components described with reference toFIG. 2Amay not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component ofFIG. 2A. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component ofFIG. 2A. Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) may be used in the various embodiments.

FIG. 2Bis a schematic diagram illustrating a string200of memory cells in a data block of a memory device in a memory sub-system in accordance with some embodiments of the present disclosure. In one embodiment, the string200is representative of one portion of memory device130, such as from array of memory cells204, as shown inFIG. 2A. The string200includes a number of memory cells212(i.e., charge storage devices), such as up to 32 memory cells (or more) in some embodiments. The string200includes a source-side select transistor known as a source select gate220(SGS) (typically an n-channel transistor) coupled between a memory cell212at one end of the string200and a common source226. The common source226may include, for example, a commonly doped semiconductor material and/or other conductive material. At the other end of the string200, a drain-side select transistor called a drain select gate230(SGD) (typically an n-channel transistor) and a gate induced drain leakage (GIDL) generator240(GG) (typically an n-channel transistor) are coupled between one of the memory cells212and a data line234, which is commonly referred to in the art as a “bit line.” The common source226can be coupled to a reference voltage (e.g., ground voltage or simply “ground” [Gnd]) or a voltage source (e.g., a charge pump circuit or power supply which may be selectively configured to a particular voltage suitable for optimizing a programming operation, for example).

Each memory cell212may include, for example, a floating gate transistor or a charge trap transistor and may comprise a single level memory cell or a multilevel memory cell. The floating gate may be referred to as a charge storage structure235. The memory cells212, the source select gate220, the drain select gate230, and the GIDL generator240can be controlled by signals on their respective control gates250.

The control signals can be applied by program management component113, or at the direction of program management component113, to select lines (not shown) to select strings, or to access lines (not shown) to select memory cells212, for example. In some cases, the control gates can form a portion of the select lines (for select devices) or access lines (for cells). The drain select gate230receives a voltage that can cause the drain select gate230to select or deselect the string200. In one embodiment, each respective control gate250is connected to a separate word line (i.e., access line), such that each device or memory cell can be separately controlled.

In one embodiment, in order to enhance detrapping of electrons from a tunnel oxide layer that forms part of string200, during the program verify phase of a program operation, program management component113can cause a negative voltage signal to be applied to the first selected word line, which is received at the corresponding control gate250to which the first selected word line is connected. Depending on the embodiment, the negative voltage signal can be applied either at a beginning of the program verify phase (i.e., before a positive pass voltage signal is applied to the first selected word line) or at an end of the program verify phase (i.e., after a positive pass voltage signal and one or more program verify voltage signals are applied to the selected word line). The application of this negative voltage signal can enhance detrapping of electrons from the tunnel oxide layer during the program verify phase without causing detrapping of electrons in the poly-silicon channel region of string200. The specific application of the negative voltage signal can vary depending on whether a single pass or multi-pass program operation is being performed, as is described in more detail below.

FIG. 3is a timing diagram300for operation of a memory device with negative word line biasing at the beginning of a program verify phase of a single pass program operation, in accordance with some embodiments of the present disclosure. During a programming operation performed on a non-volatile memory device, such as memory device130, certain phases can be encountered, including a program phase and a program verify phase. During the program phase, a program voltage is applied to selected word lines of the memory device130, in order to program a certain level of charge to the selected memory cells on the word lines representative of a desired value. During the program verify phase, a read voltage is applied to the selected word lines to read the level of charge stored at the selected memory cells to confirm that the desired value was properly programmed. Since relatively high voltages are applied during the program and program verify operations, program recovery and program verify recovery phases can be implemented to allow the memory device130to recover.

Timing diagram300illustrates the program verify phase, according to one embodiment. In this embodiment, the program verify phase includes four time intervals, during which different voltage signals are applied to various devices in memory device130. During a first time interval310, a reset pass voltage (i.e., Vpass_rst) is applied to all data word lines, including the selected word line (Sel WL) and any unselected word lines (Unsel WLs) as well as a drain select gate (SGD) of the string200. During a second time interval320, program management component113causes a negative voltage signal (Vneg) to be applied to the selected word line (Sel WL). In one embodiment, program management component113sends a signal to the word line driver (or some other component) instructing that driver to apply the negative voltage signal to the word line. The voltage signal(s) applied to the unselected word lines remain at the reset pass voltage and a select gate pass voltage (Vpassr) is applied to the drain select gate. The negative voltage signal will enhance detrapping in the tunnel oxide layer and the channel region of memory string200. After a certain period of time (e.g., several microseconds), a third time interval330can begin. During the third time interval330, a pass voltage (Vpassr) spike is applied to the selected word line and the voltage signal on the unselected word lines is ramped up to the pass voltage (Vpassr/Vpass1r). The pass voltage can discharge channel boosting and also cause electron trapping in the poly-silicon channel region. During a fourth time interval340, one or more program verify voltage signals (pv_1, pv_2, . . . pv_n) are applied to the selected word line. These voltages sense the level of charge stored at the selected memory cells to confirm that the desired value was properly programmed. Since electron detrapping of the tunnel oxide layer was already performed during second time interval320, the shallow traps of the tunnel oxide layer will be empty and will not impact the sensing of program verify operation performed during the fourth time interval340. The voltage signals applied to the unselected word lines and drain select gate can remain at the pass voltage, or optionally ramp down to a ground voltage (gnd), and all voltage signals are eventually ramped down to the reset pass voltage (Vpassr_rst) and ground at the end of the program verify phase300.

FIG. 4Ais a timing diagram400for operation of a memory device with negative word line biasing at the beginning of a program verify phase of a first pass of a multi-pass program operation, in accordance with some embodiments of the present disclosure. Certain memory sub-systems, such as those implementing QLC memory, use a multi-pass programming algorithm, such as a coarse-fine, two pass programing algorithm. In such an embodiment, programming a word line begins by coarsely the memory cells a first pass. The objective of this “coarse,” first pass is to program all cells rapidly to slightly below their final target programming levels. During the slower, “fine,” second pass, the memory cells are programmed to a slightly higher final target programmed voltage. Such two-pass programming minimizes cell to cell (C2C) interference, as every cell and its neighbors are nearly at their final target programmed voltage when the fine programming pass is performed, and need only be “touched-up.” The combination of not requiring precision programming in the first pass, and the minimized C2C coupling, leads to fast programming with high RWB.

Timing diagram400illustrates the program verify phase after a first programming pass, according to one embodiment. In this embodiment, the program verify phase includes four time intervals, during which different voltage signals are applied to various devices in memory device130. During a first time interval410, a reset pass voltage (i.e., Vpass_rst) is applied to all data word lines of the string200. During a second time interval420, program management component113causes a negative voltage signal (Vneg) to be applied to the selected word line (Sel WL) and to a second word line (WLn−1) adjacent to the selected word line on one side of the selected word line. The second word line can be a word line connected to a memory cell that has previously been coarsely programmed. In one embodiment, program management component113sends a signal to the word line driver(s) (or some other component) instructing that driver to apply the negative voltage signal to the word line(s). The voltage signal(s) applied to the unselected word lines remain at the reset pass voltage and a select gate pass voltage (Vpassr) is applied to the drain select gate. The negative voltage signals will enhance detrapping in the tunnel oxide layer and the channel region of memory string200. After a certain period of time (e.g., several microseconds), a third time interval430can begin. During the third time interval430, a pass voltage (Vpassr) spike is applied to the selected word line and select gate and the voltage signals on the second word line (WLn−1) and any unselected word lines, including a third word line (WLn+1) adjacent to the selected word line on a second side of the selected word line, are ramped up to the pass voltage (Vpassr/Vpass1r). The pass voltage on select gate can discharge channel boosting and the pass voltage on selected word line can cause electron trapping in the poly-silicon channel region. During a fourth time interval440, one or more program verify voltage signals (pv_1, pv_2, . . . pv_n) are applied to the selected word line. These voltages sense the level of charge stored at the selected memory cells to confirm that the desired value was properly programmed. Since electron detrapping of the tunnel oxide layer was already performed during second time interval420, the shallow traps of the tunnel oxide layer will be empty and will not impact the sensing of program verify operation performed during the fourth time interval440. The voltage signals applied to the second word line and the unselected word lines can remain at the pass voltage, and all voltage signals are eventually ramped down to the reset pass voltage (Vpassr_rst) and a ground voltage (gnd) at the end of the program verify phase400.

FIG. 4Bis a timing diagram450for operation of a memory device with negative word line biasing at the beginning of a program verify phase of a second pass of a multi-pass program operation, in accordance with some embodiments of the present disclosure. Timing diagram450illustrates the program verify phase after a second programming pass, according to one embodiment. In this embodiment, the program verify phase includes four time intervals, during which different voltage signals are applied to various devices in memory device130. During a first time interval460, a reset pass voltage (i.e., Vpass_rst) is applied to all data word lines of the string200. During a second time interval470, program management component113causes a negative voltage signal (Vneg) to be applied to the selected word line (Sel WL) and to a third word line (WLn+1) adjacent to the selected word line on a second side of the selected word line. The third word line can be a word line connected to a memory cell that has previously been coarsely programmed, but has not yet been finely programmed. In one embodiment, program management component113sends a signal to the word line driver(s) (or some other component) instructing that driver to apply the negative voltage signal to the word line(s). The voltage signal(s) applied to the unselected word lines remain at the reset pass voltage and a select gate pass voltage (Vpassr) is applied to the drain select gate. The negative voltage signals will enhance detrapping in the tunnel oxide layer and the channel region of memory string200. After a certain period of time (e.g., several microseconds), a third time interval480can begin. During the third time interval480, a pass voltage (Vpassr) spike is applied to the selected word line and selected gate and the voltage signals on the third word line (WLn+1) and any unselected word lines, including the second word line (WLn−1), are ramped up to the pass voltage (Vpassr/Vpass1r). The pass voltage on select gate can discharge channel boosting and the pass voltage on selected word line can cause electron trapping in the poly-silicon channel region. During a fourth time interval490, one or more program verify voltage signals (pv_1, pv_2, . . . pv_n) are applied to the selected word line. These voltages sense the level of charge stored at the selected memory cells to confirm that the desired value was properly programmed. Since electron detrapping of the tunnel oxide layer was already performed during second time interval470, the shallow traps of the tunnel oxide layer will be empty and will not impact the sensing of program verify operation performed during the fourth time interval490. The voltage signals applied to the third word line and the unselected word lines can remain at the pass voltage, and all voltage signals are eventually ramped down to the reset pass voltage (Vpassr_rst) and a ground voltage (gnd) at the end of the program verify phase450.

FIG. 5is a timing diagram500for operation of a memory device with negative word line biasing at the end of a program verify phase of a single pass program operation, in accordance with some embodiments of the present disclosure. In this embodiment, the program verify phase includes five time intervals, during which different voltage signals are applied to various devices in memory device130. During a first time interval510, a reset pass voltage (i.e., Vpass_rst) is applied to all data word lines, including the selected word line (Sel WL) and any unselected word lines (Unsel WLs) as well as a drain select gate (SGD) of the string200. During the second time interval520, a pass voltage (Vpassr) spike is applied to the selected word line and select gate and the voltage signal on the unselected word lines and drain select gate is ramped up to the pass voltage (Vpassr/Vpass1r). The pass voltage on select gate can discharge channel boosting and the pass voltage on selected word line can cause electron trapping in the poly-silicon channel region. During a third time interval530, one or more program verify voltage signals (pv_1, pv_2, . . . pv_n) are applied to the selected word line. These voltages sense the level of charge stored at the selected memory cells to confirm that the desired value was properly programmed. The voltage signals applied to the unselected word lines and drain select gate can remain at the pass voltage, or optionally ramp down to a ground voltage (gnd), and all voltage signals are eventually ramped down to the reset pass voltage (Vpassr_rst). During a fourth time interval540, program management component113causes a negative voltage signal (Vneg) to be applied to the selected word line (Sel WL). In one embodiment, program management component113sends a signal to the word line driver (or some other component) instructing that driver to apply the negative voltage signal to the word line. The voltage signal(s) applied to the unselected word lines and the drain select gate remain at the reset pass voltage. The negative voltage signal will detrap electrons in the tunnel oxide layer and the channel region of memory string200. After a certain period of time (e.g., several microseconds), a fifth time interval550can begin. During the fifth time interval550, all voltage signals are ramped down to the ground at the end of the program verify phase500. During subsequent program operations, extra electron injection due to prior detrapping can program some electrons to a storage nitride layer rather than completely filling the tunnel oxide layer traps. Thus, at the end of the program operation, there are fewer electrons in the tunnel oxide layer traps, and since the negative voltage signal is not applied between the program phase and the program verify phase, the channel region traps remain filled.

In another embodiment, program management component113can cause the negative voltage signal to be applied at the end of a program verify phase of a multi-pass program operation. For example, program management component113can cause the negative voltage signal to be applied to the selected word line, as well as to one or more adjacent word lines, after a pass voltage (e.g., Vpassr) and one or more program verify voltages (e.g., pv_1−pv_n) have been applied. In one embodiment, the negative voltage signal is applied to the selected word line and to a second word line (e.g., WLn−1) adjacent to the selected word line on one side of the selected word line during a first programming pass of the multi-pass program operation. Then, during a second pass of the multi-pass program operation, the negative voltage signal is applied to the selected word line and to a third word line (e.g., WLn+1) adjacent to the selected word line on the other side of the selected word line. The application of this negative voltage signal can detrap electrons in the tunnel oxide layer and the channel region of memory string, so that such electrons will not impact subsequent read operation performed on the memory cells of the memory string.

At operation605, a command is received. For example, processing logic (e.g., program management component113) can receive, from a requestor, such as memory sub-system controller115, a command to perform a memory access operation on a memory array, such as memory array204, of a memory device, such as memory device130. In one embodiment, the command comprises a program command and the memory access operation comprises a program operation. For example, the memory access operation can include a QLC program operation associated with a plurality of pages (e.g., four pages) of host data to be written to the memory device.

At operation610, a memory access operation is initiated. For example, the processing logic can initiates a program operation associated with the received command on memory device130. In one embodiment, the program operation includes a program phase and a program verify phase. In certain embodiments, each of these phases can be repeated numerous times in a cycle during a single programming operation.

At operation615, a program voltage signal is applied. For example, the processing logic can cause a program voltage signal to be applied to a first selected word line of a block of the memory array during a program phase of the program operation. The program voltage signal is applied to selected word lines of the memory device130, in order to program a certain level of charge (i.e., a target voltage) to the selected memory cells in a string of memory cells on the word lines representative of a desired value.

At operation620, a negative voltage signal is applied. For example, the processing logic can cause a negative voltage signal to be applied to the first selected word line during the program verify phase of the program operation. In one embodiment, the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block and the first selected word line is associated with the program operation (i.e., is connected to the memory cell(s) being programmed).

At operation625, a determination is made. For example, the processing logic can determine whether the program operation includes a multi-pass program operation. In one embodiment, the program operation is a single pass program operation where the memory cells connected to the selected word line are programmed in a single programming pass. In other embodiments, the program operation is a multi-pass program operation, where the memory cells of the memory array are programmed in two or more programming passes. In one embodiment, during a first pass of the multi-pass programing operations, the processing logic coarsely programs memory cells to initial values representing the pages of host data. In one embodiment, program management component113can cause one or more programming pulses to be applied to the selected word line to store the pages of the host data in the memory cells. The initial values can be slightly below final target values so that the first programming pass can be performed with minimal latency. In one embodiment, during the second pass of the multi-pass programing operation, the processing logic reads the coarsely programmed initial values from the first pass and finely programs the memory cells to final values representing the pages of host data. In one embodiment, program management component113can cause one or more programming voltage pulses to be applied to the memory cells to increase the initial values to the final values representing the pages of host data.

If the program operation is not a multi-pass operation (i.e., the program operation is a single pass program operation), at operation630, additional voltage signals are applied. Depending on the embodiment, a positive pass voltage signal (e.g., Vpassr) and one or more program verify voltage signals (e.g., pv_1-pv_n) are applied either before or after the negative voltage signal during the program verify phase. In one embodiment, the processing logic causes the negative voltage signal to be applied to the first selected word line at the beginning of the program verify phase of the program operation (i.e., before the positive pass voltage signal is applied to the first selected word line). In another embodiment, the processing logic causes the negative voltage signal to be applied to the selected word line at the end of the program verify phase of the program operation (i.e., after the positive pass voltage signal and one or more program verify voltage signals are applied to the selected word line).

If the program operation is a multi-pass operation, at operation635, the negative voltage signal is applied during a first programming pass. For example, the processing logic can cause the negative voltage signal to be applied to the first selected word line (e.g., WLn) and to a second word line (e.g., WLn−1) adjacent to the first selected word line during a first program verify phase of a plurality of program verify phases. The second word line is coupled to a second memory cell of a plurality of memory cells on a first side of the first memory cell in the string of memory cells.

At operation640, the negative voltage signal is applied during a second programming pass. For example, the processing logic can cause the negative voltage signal to be applied to the first selected word line (e.g., WLn) and to a third word line (e.g., WLn+1) adjacent to the first selected word line during a second program verify phase of the plurality of program verify phases. The third word line is coupled to a third memory cell of the plurality of memory cells on a second side of the first memory cell in the string of memory cells.

The example computer system700includes a processing device702, a main memory704(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory706(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system718, which communicate with each other via a bus730.

The data storage system718can include a machine-readable storage medium724(also known as a computer-readable medium) on which is stored one or more sets of instructions726or software embodying any one or more of the methodologies or functions described herein. The instructions726can also reside, completely or at least partially, within the main memory704and/or within the processing device702during execution thereof by the computer system700, the main memory704and the processing device702also constituting machine-readable storage media. The machine-readable storage medium724, data storage system718, and/or main memory704can correspond to the memory sub-system110ofFIG. 1.