Overdrive electrostatic discharge clamp

An electrostatic discharge clamp is shown, which includes a clamping circuit, a driving circuit, a capacitor and resistor network, and a bias circuit. The clamping circuit has a plurality of transistors connected in a cascode configuration. The driving circuit is coupled to the gates of the transistors of the clamping circuit. The capacitor and resistor network introduces an RC delay in response to an electrostatic discharge event to control the driving circuit to turn on the transistors of the clamping circuit for electrostatic discharging. The bias circuit biases the driving circuit to turn off the transistors of the clamping circuit when the capacitor and resistor network does not detect the electrostatic discharge event.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an electrostatic discharge clamp in an overdriving system.

Description of the Related Art

As the technology used in the semiconductor manufacturing process evolves (e.g., scaling down to 5 nm, 4 nm, 3 nm, or below), the maximum applied voltage is suppressed (e.g., down to 1.2 V, much lower than the 1.8V applied to the 7 nm products). If there are 7 nm chips as well as more advanced (5 nm/4 nm/3 nm or below) chips on the same printed circuit board (PCB), the power system should provide an overdriving design (e.g., VDD=2.5 V or 3.3 V), which may result in reliability problems in advanced transistors.

An electrostatic discharge clamp is a necessary device in a chip. An electrostatic discharge clamp having high reliability in an overdriving system is called for.

BRIEF SUMMARY OF THE INVENTION

An electrostatic discharge clamp in accordance with an exemplary embodiment of the present invention includes a clamping circuit, a driving circuit, a capacitor and resistor network, and a bias circuit. The clamping circuit includes a plurality of transistors connected in a cascode configuration. The driving circuit is coupled to the gates of the transistors of the clamping circuit. The capacitor and resistor network introduces an RC delay in response to an electrostatic discharge event to control the driving circuit to turn on the transistors of the clamping circuit for electrostatic discharging. The bias circuit biases the driving circuit to turn off the transistors of the clamping circuit when the capacitor and resistor network does not detect the electrostatic discharge event.

In an exemplary embodiment, the capacitor and resistor network comprises a resistor and a plurality of capacitors. The capacitors are connected in series. A resistor-to-capacitor connection terminal between the resistor and the capacitors is coupled to a first control terminal of the driving circuit. In response to the electrostatic discharge event, a voltage change at the resistor-to-capacitor connection terminal is coupled to the first control terminal of the driving circuit.

In an exemplary embodiment, the number of transistors is N. the number of capacitors in the capacitor and resistor network is N. The first capacitor-to-capacitor connection terminal to the (N−1)thcapacitor-to-capacitor connection terminal connecting the N capacitors in the capacitor and resistor network in series are coupled to a second control terminal to an Nthcontrol terminal of the driving circuit, respectively. The driving circuit has N output terminals coupled one-to-one to the gates of the N transistors of the clamping circuit.

In an exemplary embodiment, the driving circuit comprises N inverters. The first control terminal to the Nthcontrol terminal of the driving circuit are coupled to input terminals of the N inverters one to one. Output terminals of the N inverters are coupled to the N output terminals of the driving circuit one to one.

In an exemplary embodiment, the bias circuit comprises N bias units connected in series. The first connection terminal to the (N−1)thconnection terminal connecting the N bias units in series are coupled to the first capacitor-to-capacitor connection terminal to the (N−1)thcapacitor-to-capacitor connection terminal, respectively.

In an exemplary embodiment, the N transistors are p-channel metal oxide semiconductor field-effect transistors connected between a power line and the system ground. The resistor in the capacitor and resistor network is connected between the resistor-to-capacitor connection terminal and the system ground. The N inverters each have a first bias terminal and a second bias terminal. The first control terminal of the driving circuit is coupled to an input terminal of a first inverter of the N inverters. A second bias terminal of the first inverter is coupled to the system ground. A first bias terminal of an Nthinverter of the N inverters is coupled to the power line. Second bias terminals of the second to the Nthinverter of the N inverters are coupled to output terminals of the first to the (N−1)thinverters of the N inverters, respectively. The first connection terminal to the (N−1)thconnection terminal connecting the bias units in series from the system ground to the power line are further coupled to first bias terminals of the first to the (N−1)thinverters, respectively.

In an exemplary embodiment, the N transistors are n-channel metal oxide semiconductor field-effect transistors connected between a power line and the system ground. The resistor in the capacitor and resistor network is connected between the power line and the resistor-to-capacitor connection terminal. The N inverters each have a first bias terminal and a second bias terminal. The first control terminal of the driving circuit is coupled to an input terminal of a first inverter of the N inverters. A first bias terminal of the first inverter is coupled to the power line. A second bias terminal of an Nthinverter of the N inverters is coupled to the system ground. First bias terminals of the second to the Nthinverter of the N inverters are coupled to output terminals of the first to the (N−1)thinverters of the N inverters, respectively. The first connection terminal to the (N−1)thconnection terminal connecting the bias units in series from the power line to the system ground are further coupled to second bias terminals of the first to the (N−1)thinverters, respectively.

In an exemplary embodiment, there are more than 2 clamping transistors. The electrostatic discharge clamp is operated in an overdriving system.

DETAILED DESCRIPTION OF THE INVENTION

FIG.1illustrates an electrostatic discharge clamp100in accordance with an exemplary embodiment of the present invention, which includes a clamping circuit102, a driving circuit104, a capacitor and resistor network106, and a bias circuit108.

The clamping circuit102includes a plurality of p-channel metal oxide semiconductor field-effect transistors (PMOSs) P1, P2and P3connected in a cascode configuration to deal with the overdriving design (e.g., VDD 2.5 V or 3 V while the chip is manufactured by an advanced process such as 5 nm/4 nm/3 nm or below). In this example, the number of PMOSs is 3 but not intended to be limited thereto. The number of transistors in the coscode configuration between the power line VDD and the system ground VSS depends on the overdriving level (VDD) and the manufacture process of the chip.

The driving circuit104is coupled to the gates of the PMOSs P1, P2and P3of the clamping circuit102. The capacitor and resistor network106introduces an RC delay in response to an electrostatic discharge event (e.g., an ESD stress on the power line VDD) to control the driving circuit104to turn on the PMOSs P1, P2and P3for electrostatic discharging. The bias circuit108biases the driving circuit104to turn off the PMOSs P1, P2and P3when the capacitor and resistor network106does not detect any electrostatic discharge event. The leakage current is efficiently suppressed because of the normally turned-off PMOSs.

As shown, the capacitor and resistor network106comprises a resistor110and a plurality of capacitors112_1,112_2, and112_3. The capacitors112_1,112_2, and112_3are connected in series. A resistor-to-capacitor connection terminal114between the resistor110and the capacitors112_1,112_2, and112_3is coupled to a first control terminal Vc1of the driving circuit104. The resistor110in the capacitor and resistor network106is connected between the resistor-to-capacitor connection terminal114and the system ground Vss. In response to an electrostatic discharge event, a voltage change at the resistor-to-capacitor connection terminal114is coupled to the first control terminal Vc1of the driving circuit104. Note that the resistor number used in the capacitor and resistor network106is just one. The single resistor110guarantees that the turn-on voltage to build an electrostatic discharging path through the PMOSs P1, P2and P3is very low. The electrostatic discharge clamp100is reliable.

The number of capacitors112_1,112_2, and112_3in the capacitor and resistor network106is the same as the number of PMOSs P1, P2and P3in the clamping circuit102, which is 3 (N is 3) in this case. The first capacitor-to-capacitor connection terminal116_1and the second capacitor-to-capacitor connection terminal116_2connecting the three capacitors112_1,112_2, and112_3in the capacitor and resistor network106in series are coupled to the second control terminal Vc2and the third control terminal Vc3of the driving circuit104, respectively. The driving circuit104has output terminals Vo1, Vo2, and Vo3coupled to the gates of the PMOSs P1, P2and P3of the clamping circuit102one to one. The driving circuit comprises three inverters Inv1, Inv2, and Inv3. The control terminals Vc1, Vc2, and Vc3of the driving circuit104are coupled to input terminals of the three inverters Inv1, Inv2, and Inv3one to one. The output terminals of the three inverters Inv1, Inv2, and Inv3are coupled to the three output terminals Vo1, Vo2, and Vo3of the driving circuit104one to one. Each inverter corresponds to the control of one clamping transistor.

The bias circuit108comprises three bias units118_1,118_2, and118_3connected in series. The first connection terminal120_1and the second connection terminal120_2connecting the three bias units in series are coupled to the first capacitor-to-capacitor connection terminal116_1and the second capacitor-to-capacitor connection terminal116_2, respectively.

The bias circuit108further comprises two resistors122_1and122_2. The first connection terminal120_1and the second connection terminal120_2are coupled to the first capacitor-to-capacitor connection terminal116_1and the second capacitor-to-capacitor connection terminal116_2, respectively, through the two resistors122_1and122_2. The resistors122_1and122_2are optional.

The three inverters Inv1, Inv2, and Inv3each have a first bias terminal t1and a second bias terminal t2. The first control terminal Vc1of the driving circuit104is coupled to an input terminal of a first inverter Inv1. The second bias terminal t2of the first inverter Inv1is coupled to the system ground Vss. The first bias terminal t1of the third inverter Inv3is coupled to the power line VDD. The second bias terminals t2of the second and the third inverters Inv2and Inv3are coupled to the output terminals of the first and the second inverters Inv1and Inv2, respectively. The first connection terminal120_1and the second connection terminal120_2connecting the bias units118_1,118_2, and118_3in series from the system ground VSS to the power line VDD are further coupled to the first bias terminal t1of the first inverter Inv1and the first bias terminal t1of the second inverter Inv2, respectively.

The inverters Inv1to Inv3in the driving circuit104are stacked one by one. No diode string is required to bias the inverters Inv_1, Inv2, and Inv3. In a conventional electrostatic discharge clamp, a parasitic leakage path is introduced by a diode string used in the driving circuit. Such a parasitic leakage path does not exist in the driving circuit104of the present invention.

FIG.2illustrates another electrostatic discharge clamp200in accordance with an exemplary embodiment of the present invention, which includes a clamping circuit202, a driving circuit204, a capacitor and resistor network206, and a bias circuit208. The clamping circuit202uses a plurality of n-channel metal oxide semiconductor field-effect transistors (NMOSs) N1, N2and N3to replace the PMOSs P1, P2, and P3ofFIG.1.

The driving circuit204is coupled to gates of the NMOSs N1, N2and N3of the clamping circuit202. The capacitor and resistor network206introduces an RC delay in response to an electrostatic discharge event (e.g., an ESD stress on the power line VDD) to control the driving circuit204to turn on the NMOSs N1, N2and N3for electrostatic discharging. The bias circuit208biases the driving circuit204to turn off the NMOSs N1, N2and N3when the capacitor and resistor network206does not detect any electrostatic discharge event. In such a structure, the NMOSs N1, N2and N3in the clamping circuit202are normally turned off when no electrostatic discharge event occurs. The leakage current is efficiently suppressed.

As shown, the capacitor and resistor network206comprises a resistor210and a plurality of capacitors212_1,212_2, and212_3. The capacitors212_1,212_2, and212_3are connected in series. A resistor-to-capacitor connection terminal214between the resistor210and the capacitors212_1,212_2, and212_3is coupled to a first control terminal Vc1of the driving circuit204. The resistor210in the capacitor and resistor network206is connected between the resistor-to-capacitor connection terminal214and the power line VDD. In response to an electrostatic discharge event, a voltage change at the resistor-to-capacitor connection terminal214is coupled to the first control terminal Vc1of the driving circuit204. Note that the resistor number used in the capacitor and resistor network206is just one. The single resistor210guarantees that the turn-on voltage to build an electrostatic discharging path through the NMOSs N1, N2and N3is very low. The electrostatic discharge clamp200is reliable.

The number of capacitors212_1,212_2, and212_3in the capacitor and resistor network206is the same as the number of NMOSs N1, N2and N3in the clamping circuit202, which is 3 (N is 3) in this case. The first capacitor-to-capacitor connection terminal216_1and the second capacitor-to-capacitor connection terminal216_2connecting the three capacitors212_1,212_2, and212_3in the capacitor and resistor network206in series are coupled to the second control terminal Vc2and the third control terminal Vc3of the driving circuit204, respectively. The driving circuit204has output terminals Vo1, Vo2, and Vo3coupled to the gates of the NMOSs N1, N2and N3of the clamping circuit202one to one. The driving circuit204comprises three inverters Inv1, Inv2, and Inv3. The first, second, and third control terminals Vc1, Vc2, and Vc3of the driving circuit204are coupled to input terminals of the three inverters Inv1, Inv2, and Inv3one to one. The output terminals of the three inverters Inv1, Inv2, and Inv3are coupled to the three output terminals Vo1, Vo2, and Vo3of the driving circuit204one to one. Each inverter corresponds to the control of one clamping transistor.

The bias circuit208comprises three bias units218_1,218_2, and218_3connected in series. The first connection terminal220_1and the second connection terminal220_2connecting the three bias units218_1,218_2, and218_3in series are coupled to the first capacitor-to-capacitor connection terminal216_1and the second capacitor-to-capacitor connection terminal216_2, respectively.

The bias circuit208further comprises two resistors222_1and222_2. The first connection terminal220_1and the second connection terminal220_2are coupled to the first capacitor-to-capacitor connection terminal216_1and the second capacitor-to-capacitor connection terminal216_2, respectively, through the two resistors222_1and222_2.

The three inverters Inv1, Inv2, and Inv3each have a first bias terminal t1and a second bias terminal t2. The first control terminal Vc1of the driving circuit204is coupled to an input terminal of a first inverter Inv1. The first bias terminal t1of the first inverter Inv1is coupled to the power line VDD. The second bias terminal t2of the third inverter Inv3is coupled to the system ground VSS. The first bias terminals t1of the second and the third inverter Inv2and Inv3are coupled to output terminals of the first and second inverters Inv1and Inv2, respectively. The first connection terminal220_1and the second connection terminal220_2connecting the bias units218_1,218_2, and218_3in series from the power line VDD to the system ground VSS are further coupled to the second bias terminal t2of the first inverter Inv1and the second bias terminal t2of the second inverter Inv2, respectively.

The electrostatic discharge clamp200using NMOSs as the clamping transistors also works well.

FIGS.3A to3Eillustrate examples of the bias units in the bias circuit108/208. Each bias unit may be a resistor (FIG.3A). In another exemplary embodiment, each bias unit may comprise a resistor and an off-state PMOS connected in series (FIG.3B), or a resistor and an off-state NMOS connected in series (FIG.3C). In another exemplary embodiment, the bias units form a diode string (referring to the PMOS diode string inFIG.3D, or the NMOS diode string inFIG.3E).

FIGS.4A to4Eillustrate examples of the capacitor and resistor network106. InFIG.4A, each capacitor in the capacitor and resistor network106is a PMOS capacitor. InFIG.4B, each capacitor in the capacitor and resistor network106is an NMOS capacitor. InFIG.4C, the capacitors in the capacitor and resistor network106are all metal-oxide-metal (MOM) capacitors, or are all metal-insulator-metal (MIM) capacitors. InFIGS.4D and4E, the capacitors in the capacitor and resistor network106are in a hybrid configuration formed by metal-oxide-semiconductor and metal-oxide-metal capacitors, or, formed by metal-oxide-semiconductor and metal-insulator-metal capacitors.

FIGS.5A to5Eillustrate examples of the capacitor and resistor network206. InFIG.5A, each capacitor in the capacitor and resistor network206is a PMOS capacitor. InFIG.5B, each capacitor in the capacitor and resistor network206is an NMOS capacitor. InFIG.5C, the capacitors in the capacitor and resistor network206are all metal-oxide-metal (MOM) capacitors, or are all metal-insulator-metal (MIM) capacitors. InFIGS.5D and5E, the capacitors in the capacitor and resistor network206are in a hybrid configuration formed by metal-oxide-semiconductor and metal-oxide-metal capacitors, or, formed by metal-oxide-semiconductor and metal-insulator-metal capacitors.