MEMORY MANAGEMENT APPARATUS AND MEMORY MANAGEMENT METHOD THEREOF

A memory management apparatus and method thereof are disclosed. The memory management apparatus includes a micro translation look-aside buffers, a main translation look-aside buffer, a page address history table and a controller. The page address history table is used to record the space size information for a plurality of page table entry which are written to the main translation look-aside buffer. The controller decides to whether access a page table entry or not from the main translation look-aside buffer according to the page address history table.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a block diagram of a memory management apparatus100according to an embodiment of the invention. Referring toFIG. 1, the memory management apparatus100includes two micro TLBs110and120, a page address history table130, a main TLB140and a controller150. The micro TLBs110and120respectively receive a virtual address VCODADD and a virtual address VDATAADD, in which the virtual address VCODADD can be the virtual address of program code, while the virtual address VDATAADD can be the virtual address of data. When there is a need to looking up a PTE, the controller150of the memory management apparatus100will respectively look up the PTE in the micro TLB110and the micro TLB120according to the virtual addresses VCODADD and VDATAADD to ensure whether or not the required PTE is stored in the micro TLB110or120.

The page address history table130is coupled between the micro TLB110and the main TLB140and between the micro TLB120and the main TLB140. The page address history table130is used to record a plurality of space size information of PTEs written in the main TLB140. When a required PTE can not be found out in the micro TLBs110and120, the controller150will check the content of the page address history table130. It should be noted that the page address history table130is used to record the space size information of PTEs written in the main TLB140. That is, the controller150can judge out whether or not a space size information same as the size of the required PTE has been written in the main TLB according to the page address history table130. If the page address history table130indicates the main TLB140has a PTE with the same space size information as the one of the required PTE written therein, the controller150further performs a looking up operation on the main TLB140. Otherwise, if the page address history table130indicates the main TLB140has no such PTE with the same space size information as the one of the required PTE written therein, the controller150will not perform a looking up operation on the main TLB140, instead, the required PTE will be directly read in an external storage device.

In following, the detail of the operation of the memory management apparatus100is explained. In the initial state, no information is stored in the micro TLBs110and120, the main TLB140and the page address history table130. When the virtual addresses VCODADD and VDATAADD are produced, at the time, the required PTE can not be found in the micro TLBs110and120; and through the page address history table130, the controller150is aware of that the required PTE can not be looked up in the main TLB140so that the required PTE should be read from the external storage device. Next, the obtained PTE read from the external storage device is written into the micro TLBs110and120.

When newer virtual addresses VCODADD and VDATAADD are produced, the memory management apparatus100repeatedly performs the above-mentioned steps. Once the micro TLBs110and120are entirely filled, the controller150chooses an old required PTE in the micro TLBs110and120and moves the old required PTE into the main TLB140. As a result, the micro TLB110or the micro TLB120gets newly added vacant storage space due to moving out the old required PTE, so that the controller150is able to write the required PTE into the newly added vacant storage space.

When the controller150performs an operation of writing the PTE into the main TLB140, the controller150will also update the page address history table130. Specifically, the space size information of the PTE written into the main TLB140is recorded to the page address history table130.

It should be noted that the memory management apparatus100in the embodiment of the invention can have one constructed micro TLB only. In the embodiment, the implementation of two micro TLBs110and120is an embodiment example, which the invention is not limited to. In other embodiments of the invention, the micro TLBs110and120can be merged into a single micro TLB.

FIG. 2is an implementation diagram of a page address history table130according to the embodiment of the invention. Referring toFIGS. 1 and 2, inFIG. 2, the page address history table130has a plurality of space fields210-2N0which are respectively corresponding to a plurality of different space sizes of page addresses. For example, the space fields210-2N0are respectively corresponding to different space sizes of page addresses of 1 KB, 4 KB, 16 KB, 64 KB and 1 MB.

The initial values of the space fields210-2N0can be set as “0”. When the space size of a PTE written in the main TLB140by the controller150is 4 KB, the controller150can set the space field in the page address history table130corresponding to the space size of 4 KB as “1” (for example, the space field210). Thus, when there is a newly required PTE to be looked up, the controller150can be aware of that there is a PTE with the space size of 4 KB stored in the main TLB140according to the space field210set as “1”; if the space size of a newly required PTE is also equal to 4 KB, the controller150will perform a looking up operation of the newly required PTE on the main TLB140.

On the contrary, when the space size of a newly required PTE is 8K, but the space field in the page address history table130corresponding to the space size of 8K is “0”, it indicates the main TLB140certainly does not have the newly required PTE. At the time, the controller150will not perform a looking up operation on the main TLB140; instead, the controller150will directly read the newly required PTE in the external storage device. The page address history table130can have a plurality of space fields with “1” setting.

It should be noted that in order to indicate that there is a PTE with a space size corresponding to the space field stored in the main TLB140, the space field of the page address history table130is not necessarily set as “1”. In fact, the designer can independently set the space field by any value with one bit or multiple bits so as to indicate whether or not the space field of the page address history table130is set already.

FIG. 3is a flowchart of a memory management method according to an embodiment of the invention. Referring toFIG. 3, First in step S310, the memory management apparatus receives a reading requirement of a page table entry; Next in step S320, a page address history table coupled between a micro TLB and a main TLB is provided; then in step S330, it is decided through the controller whether or not to access the main TLB for reading the PTE according to the information recorded in the page address history table, wherein the page address history table is for recording the space size information of a PTE written in the main TLB.

The way for recording the space size information of a PTE written in the main TLB into the page address history table in the embodiment and the details of the above-mentioned steps can refer to the previous embodiment and its implementation, which is omitted to describe.

FIG. 4is a flowchart of a memory management method according to another embodiment of the invention. Referring toFIG. 4, first in step S410, a processor sends out a virtual address; next in step S420, it is checked whether or not a buffer has the corresponding PTE, in which if the checking result is “yes”, it indicates the required PTE is found and the looking up operation of the PTE is completed (step S421). On the contrary, if the checking result of step S420is “no”, it goes to step S430where the space fields with the space sizes of page addresses of 4 KB, 1K, 1 M, 64 KB and 16K in the page address history table are checked to decide whether the space fields are set as “1”. If there is a space field set as 1 in the page address history table, it goes to step S431to perform a looking up operation of the required PTE in the main TLB. It should be noted that when a plurality of ones among the above-mentioned space fields of space size information of the PTE are set as “1”, the looking up operation of the PTE can be performed on the main TLB in multiple times. In addition, if the required PTE can not be found through step S431, the procedure goes to step S440; if the required PTE can be found through step S431, the looking-up operation of the PTE is completed.

In step S430, if it is checked out that none of all the space fields in the page address history table is set as “1”, the procedure can goes to step S440. In step S440, the required PTE will be obtained through the external storage device.

Further, in step S450, it is judged whether or not the micro TLB has a vacant storage space. If the judgement result is “yes”, the procedure goes to step S451so as to write the required PTE read in the external storage device into the vacant storage space. If the judgement result is “no”, the procedure goes to step S460so as to pick out the old required PTE in the micro TLB to make the micro TLB produce a newly added vacant storage space and write the required PTE into the newly added vacant storage space and write the old required PTE into the main TLB. At the time, along with the writing operation on the main TLB, the page address history table should be updated accordingly.

FIG. 5is another implementation diagram of a page address history table500in the embodiment of the invention and the implementation ofFIG. 5is different from the implementation of the page address history table130shown inFIG. 2. Referring toFIG. 5, the page address history table500includes a plurality of space fields510-5N0and each of the space fields510-5N0includes a plurality of virtual address information. Taking the space fields510and5N0as exemplary examples. The space field510includes the virtual address information511-514, while the space field5N0includes the virtual address information5N1-5N4. In the implementation, during checking the page address history table500, in addition to checking whether or not the space fields510-5N0have one/ones set as “1”, the virtual address information of the space field/fields set as “1” is also checked. Since different applications with a same space size may be arranged in different memory addresses. Therefore, by checking the virtual address information of the applications, it can be more clearly aware of whether or not the required PTE corresponding to an application can be looked up in the main TLB. If the controller decides by judgement that the virtual address produced by the processor can not be found in the virtual address information, the procedure can skip the looking up operation on the main TLB, which can further advance the memory management efficiency.

In summary, the invention provides a scheme of recording the space size information of the PTE written into the main TLB by using the page address history table, and by means of the page address history table, it can be decided whether or not to look up the PTE on the main TLB, which can avoid the entire reading operations on the main TLB, effectively save the looking up time of the PTE and increase access efficiency of the memory.