Device including a semiconductor chip and a carrier and fabrication method

A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier.

BACKGROUND

This invention relates to a device including a semiconductor chip and a carrier and a method of fabricating thereof.

Electronic devices may include carriers on which semiconductor chips may be mounted. Furthermore, electronic devices may include materials to attach the semiconductor chips to the carriers. These materials may be electrically conductive so as to provide an electrical coupling between the semiconductor chips and the carriers.

DETAILED DESCRIPTION

As employed in this Specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together; intervening elements may be provided between the “coupled” or “electrically coupled” elements.

Devices containing semiconductor chips are described below. The semiconductor chips may be of different types, may be manufactured by different technologies and may include for example integrated electrical, electro-optical or electro-mechanical circuits or passives. The integrated circuits may, for example, be designed as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, memory circuits or integrated passives. Furthermore, the semiconductor chips may, for example, be configured as power semiconductor chips, such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), power bipolar transistors or power diodes. Furthermore, the semiconductor chips may include control circuits, microprocessors or microelectromechanical components. In one embodiment, semiconductor chips having a vertical structure may be involved, that is to say that the semiconductor chips may be fabricated in such a way that electric currents can flow in a direction perpendicular to the main surfaces of the semiconductor chips. A semiconductor chip having a vertical structure may have electrodes in one embodiment on its two main surfaces, that is to say on its top side and bottom side. In one embodiment, power semiconductor chips may have a vertical structure. By way of example, the source electrode and gate electrode of a power MOSFET may be situated on one main surface, while the drain electrode of the power MOSFET is arranged on the other main surface. Furthermore, the devices described below may include integrated circuits to control the integrated circuits of other semiconductor chips, for example the integrated circuits of power semiconductor chips. The semiconductor chips need not be manufactured from specific semiconductor material, for example Si, SiC, SiGe, GaAs, and, furthermore, may contain inorganic and/or organic materials that are not semiconductors, such as for example insulators, plastics or metals. Moreover, the semiconductor chips may be packaged or unpackaged.

The semiconductor chips may be fabricated on a wafer made of semiconductor material. The surface area of a semiconductor wafer may be standardized according to predetermined wafer diameters, e.g., 4 inches, 8 inches, 10 inches or 12 inches. The thickness of the semiconductor wafer may vary within ranges of typically 10 to 1000 μm, where these values may also be smaller or larger in specific applications. The semiconductor wafers may be thinned, for example by grinding their backsides, down to a thickness in the range from 10 to 220 μm. The semiconductor wafers may be diced thereby separating the individual semiconductor chips.

The semiconductor chips may have electrodes (or contact pads) which allow electrical contact to be made with the integrated circuits included in the semiconductor chips. One or more metal layers may be applied to some electrodes of the semiconductor chips. The metal layers may be manufactured with any desired geometric shape and any desired material composition. The metal layers may, for example, be in the form of a layer covering an area. Any desired metal or metal alloy, for example aluminum, titanium, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium, may be used as the material. The metal layers need not be homogenous or manufactured from just one material, that is to say various compositions and concentrations of the materials contained in the metal layers are possible.

Some of the electrodes may not be covered with metal layers. At these electrodes semiconductor material, for example Si, SiC, SiGe or GaAs, may be exposed. It may be provided that an entire surface of the semiconductor chip, for example the backside of the semiconductor chip or any other surface, is not coated with any metal layer. These electrodes or surfaces of the semiconductor chips may be used to attach the semiconductor chips to carriers. The electrodes or surfaces of the semiconductor chips which are not covered with metal layers may further be free of semiconductor oxide material when the semiconductor chips are attached to the carriers.

The carriers may be of any shape, size or material. During the fabrication of the devices the carriers may be connected to each other. The carriers may also be made from one piece. The carriers may be connected among each other by connection means with the purpose of separating the carriers in the course of the fabrication. Separation of the carriers may be carried out by mechanical sawing, a laser beam, cutting, stamping, milling, etching or any other appropriate method. The carriers may be electrically conductive. They may be fabricated from metals or metal alloys, in one embodiment copper, copper alloys, iron nickel, aluminum, aluminum alloys, or other appropriate materials. The carriers may be made solely of metals or metal alloys. The carriers may be, for example, leadframes or parts of leadframes. Furthermore, the carriers may be plated with an electrically conductive material, for example copper, silver, iron nickel or nickel phosphorus. Carriers consisting of electrically insulating material and having at least one electrically conductive surface may also be employed. A DBC (Direct Bonded Copper) substrate is an example of such a carrier. A DBC substrate is composed of a ceramic carrier with a sheet of copper bonded to one or both sides of the ceramic carrier.

An electrically conductive material may be used to attach the semiconductor chips to the carriers. Furthermore, the electrically conductive material may provide an electrical and thermal coupling between the semiconductor chips and the carriers. The electrically conductive material may, for example, be a solder material. Moreover, the electrically conductive material may consist of metal particles. At least some of the metal particles may have dimensions smaller than 100 nm. In order to attach the semiconductor chips to the carriers the metal particles may be heated. When heating the metal particles they may be sintered.

The devices described below may include external contact elements, which may be of any shape and size. The external contact elements may be accessible from outside the devices and may thus allow electrical contact to be made with the semiconductor chips from outside the devices. Furthermore, the external contact elements may be thermally conductive and may serve as heat sinks for dissipating the heat generated by the semiconductor chips. The external contact elements may be composed of any desired electrically conductive material, for example of a metal, such as copper, aluminum or gold, a metal alloy or an electrically conductive organic material. The external contact elements may be leads of a leadframe.

The devices may include a mold material covering at least parts of the components of the devices. The mold material may be any appropriate thermoplastic or thermosetting material. Various techniques may be employed to cover the components with the mold material, for example compression molding, injection molding, powder molding or liquid molding.

FIGS. 1A to 1Cschematically illustrate one embodiment of a method for production of a device100. A cross section of the device100obtained by the method is illustrated inFIG. 1C. First a semiconductor chip10is provided (seeFIG. 1A). Semiconductor material is exposed at a first surface11of the semiconductor chip10. The semiconductor chip10is placed over a carrier12such that the first surface11of the semiconductor chip10faces the carrier12(seeFIG. 1B). Electrically conductive material13is arranged between the semiconductor chip10and the carrier12. Heat is applied in order to attach the semiconductor chip10to the carrier12(seeFIG. 1C).

FIG. 2schematically illustrates a device200in cross section. The device200includes a carrier12, a sintered metal layer14placed over the carrier12and a semiconductor chip10placed over the sintered metal layer14. The sintered metal layer14is at least partially in direct contact with semiconductor material of the semiconductor chip10.

FIGS. 3A to 3Ischematically illustrate one embodiment of a method for production of a device300, a cross section of which is illustrated inFIG. 3I. The device300is an implementation of the devices100and200. The details of the device300that are described below can therefore be likewise applied to the devices100and200. Furthermore, the method illustrated inFIGS. 3A to 3Iis an implementation of the method illustrated inFIGS. 1A to 1C. The details of the production method that are described below can therefore be likewise applied to the method ofFIGS. 1A to 1C.

The semiconductor chip10as well as all other semiconductor chips described herein may be fabricated on a wafer made of semiconductor material. The semiconductor wafer may have any shape and size and may be manufactured from any semiconductor material. Such a semiconductor wafer20is illustrated inFIG. 3A. The semiconductor wafer20has a first surface21and a second surface22opposite to the first surface21. Semiconductor material may be exposed on the first surface21of the semiconductor wafer20. The first surface21may not be coated with any metal layer, instead bare semiconductor material, for example Si, SiC, SiGe or GaAs, may be exposed. The semiconductor material may be doped with appropriate doping ions to obtain an electrical conductivity of at least portions of the first surface21of the semiconductor wafer20. As indicated inFIG. 3Aby dashed lines, portions of the first surface21of the semiconductor wafer20may be doped such that electrodes23are produced at the first surface21. Since manufacturing processes for the metallization of the first surface21of the semiconductor wafer20are not required, costs for the production of the semiconductor wafer20are reduced.

Further electrodes24and25may be located on the second surface22of the semiconductor wafer20. The electrodes24and25on the second surface22may be coated with one or more metal layers made of aluminum, copper, silver or other metals or metal alloys. The integrated circuits embedded in the semiconductor wafer20can be electrically accessed via the electrodes23to25.

The integrated circuits contained in the semiconductor wafer20may be physically identical, but may also differ from each other. The integrated circuits may, for example, be vertical power diodes or vertical power transistors, for example IGBTs, JFETs, power bipolar transistors or power MOSFETs. In the latter case, which is exemplarily illustrated inFIG. 3A, the electrodes23may be the drain electrodes of the power MOSFETs, and the electrodes24and25may function as the source and gate electrodes of the power MOSFETs, respectively.

Instead of vertical power diodes or vertical power transistors, other integrated circuits, such as logic circuits, may be contained in the semiconductor wafer20. In one embodiment those circuits may be embedded in the semiconductor wafer20which have an electrode on their backside, first side21.

The first surface21of the semiconductor wafer20may be cleaned in an appropriate way, in one embodiment in order to remove any semiconductor oxide material which may be present on the first surface21. Removing the semiconductor oxide may, for example, be carried out by dipping the semiconductor wafer20into a HF solution or by plasma etching with a mixture of argon and hydrogen or by any other appropriate etching method.

After the cleaning process a paste26containing metal particles27may be applied to the first surface21of the semiconductor wafer20as illustrated inFIG. 3B. The metal particles27may, for example, be made of silver, gold, copper, tin or nickel. According to one embodiment, the metal particles27may be made of a pure metal or of a metal alloy. The dimensions (average diameter) of the metal particles27may be smaller than 100 nm and, in one embodiment, smaller than 50 nm or 10 nm. It may also be provided that only a fraction of the metal particles27, which are applied to the semiconductor wafer20, has such dimensions. For example, at least 10% or 20% or 30% or 40% or 50% or 60% or 70% of the metal particles27may have dimensions smaller than 100 nm or 50 nm or 10 nm. The other metal particles27may have larger dimensions. According to one embodiment, the metal particles27have dimensions in the range between 5 and 50 nm.

The metal particles27may be coated with a layer28of an organic material or a flux material, for example colophony. Furthermore, the metal particles27may be dispersed in a suitable liquid or solvent29. The paste26containing the metal particles27may be fluid, viscous or waxy. Pastes containing metal particles, which are coated with a layer of an organic or flux material and dispersed in a solvent, can, for example, be purchased from the companies Coocson Electronic (product name: N 1000), Advanced Nano-Particles (ANP), Harima Chemicals (product names: NPS-H and NHD-1) or NBE Technologies (product name: NBE Tech). Other products from these or other companies may alternatively be used and may serve the same purpose as described below.

The application of the paste26containing the metal particles27dispersed in the solvent29may be performed by stencil printing or other printing technologies. Moreover, the paste26may be distributed by a squeegee. Other techniques for the application of the paste26to the semiconductor wafer20are also possible, for example dispensing or spin-coating.

The solvent29may enable the metal particles27to be applied to the first surface21of the semiconductor wafer20. Therefore, the solvent29may be chosen such that—depending on the application technique—it is fluid, viscous or waxy during the application of the paste26.

After the application of the paste26, the paste26may be exposed to a moderate temperature T1in an oven, which may be smaller than 150° C. The exposure time may be arbitrary, in one embodiment it may be long enough to allow the solvent29to at least partially evaporate leaving the metal particles27localized on the semiconductor wafer20as illustrated inFIG. 3C. The solvent29may evaporate without any residues. The temperature T1may be chosen such that the layers28coating the metal particles27do not melt, in one embodiment if the diameter of the metal particles27is smaller than 50 nm or 10 nm. According to one embodiment, the layers28may at least partially melt or evaporate at the temperature T1.

The layers28coating the metal particles27may prevent premature agglomeration of the metal particles27. Furthermore, the layer of metal particles27covering the semiconductor wafer20and in one embodiment the layers28may prevent oxidation of the bare semiconductor surface21of the semiconductor wafer20.

After the evaporation of the solvent29, the semiconductor wafer20may be diced thereby separating the individual semiconductor chips10as illustrated inFIG. 3D. Singulating the semiconductor wafer20may be carried out by sawing or any other appropriate technique, for example laser ablation, cutting, stamping, milling or etching. Although only two of the semiconductor chips10are illustrated inFIG. 3D, any number of semiconductor chips10can be obtained from the semiconductor wafer20.

The layers28of organic material or flux material coating the metal particles27may ensure that the metal particles27adhere sufficiently well to the first surface21of the semiconductor wafer20and to each other so that at least a sufficient fraction of the metal particles27remain on the first surface21even after the dicing of the semiconductor wafer20.

As illustrated inFIG. 3E, at least one of the semiconductor chips10may be placed over a carrier12with the first surface21and the metal particles27facing the carrier12. The carrier12may, for example, be a part of a leadframe, such as a die pad as illustrated inFIG. 3E. The leadframe may further include leads30and other die pads. The leadframe may be manufactured from a metal or metal alloy, in one embodiment copper, a copper alloy, iron nickel, aluminum, or other electrically conductive materials. Furthermore, the leadframe may be plated with an electrically conductive material, for example copper, silver, iron nickel or nickel phosphorus. The shape of the leadframe is not limited to any size or geometric shape. The leadframe may have been manufactured by punching a metal plate. The die pads and leads of the leadframe may be connected to each other by dams.

InFIG. 3Eonly one semiconductor chip10, which is placed over the leadframe, is illustrated. Further semiconductor chips may also be placed over the leadframe. These semiconductor chips may have been fabricated on the same semiconductor wafer20, but may alternatively have been manufactured on different semiconductor wafers. Furthermore, the semiconductor chips may be physically identical, but may also contain different integrated circuits.

The metal particles27may be exposed to a temperature T2, which is high enough that the layers28coating the metal particles27sublimate or evaporate. Furthermore, the temperature T2may be lower than the melting temperature of the metal particles27. After the layers28are removed, the metal particles27may form a solid layer14by sintering due to the temperature T2. The temperature T2may be in the range from 150 to 500° C., in one embodiment in the range from 180 to 300° C. and may depend on the material and/or the dimensions of the metal particles27.

For producing the sintered joint, the carrier12may be heated by a hot plate to the temperature T2. According to one embodiment, both the carrier12and the semiconductor chip10may be placed in an oven and heated to an appropriate temperature. A pick-and-place tool may be used capable of picking the semiconductor chip10and placing it on the heated carrier12. During the sintering process the semiconductor chip10may be pressed onto the carrier12for an appropriate time, for example some seconds or minutes.

The layers28coating the metal particles27before the sintering process may prevent oxidation of the metal particles27. If an outer layer of the metal particles27is oxidized, a higher temperature T2would be required to sinter the metal particles27. Furthermore, the sinter temperature T2may be reduced by reducing the diameters or dimensions of the metal particles27. Due to the different thermal expansion coefficients of the semiconductor chip10and the carrier12a low temperature T2is desired to reduce the mechanical stress induced into the semiconductor chip10by the carrier12during the sintering process. As an example, copper of which the carrier12may be manufactured has a thermal expansion coefficient of about 17×10−6/K and silicon has a thermal expansion coefficient of about 3×10−6/K. Moreover, due to the low temperature T2diffusion of impurities and metal particles into the semiconductor chip10is inhibited.

As illustrated inFIG. 3F, the sintered metal layer14mechanically attaches the semiconductor chip10to the carrier12and electrically and thermally couples the first surface21of the semiconductor chip10to the carrier12. Since the first surface21of the semiconductor chip10may be free of any metal layer (before the attachment to the carrier12), the sintered metal layer14may be in direct contact with the n-type or p-type semiconductor material of the semiconductor chip10and thus the electrode23. The sintered metal layer14may be of any thickness, in one embodiment its thickness may be in the range from 1 to 30 μm. Pores may be distributed over the sintered metal layer14.

After the attachment of the semiconductor chip10to the carrier12, electrical interconnections may be established from the electrodes24and25of the semiconductor chip10to the leads30. As illustrated inFIG. 3G, these interconnections may be made by wire bonding. For example, ball bonding or wedge bonding may be used as the interconnect technique. One or more bond wires31may be attached to electrically couple each of the electrodes24and25located on the second surface22of the semiconductor chip10to the leads30. The bond wires31may be made up of gold, aluminum, copper or any other appropriate electrically conductive material. The carrier12may be connected to another lead30which is not illustrated inFIG. 3G. This lead30and the carrier12may be made of one piece.

Instead of wire bonding, other interconnect techniques may be used. For example, metallic clips may be placed on the semiconductor chip10and the leads30in order to establish the electrical connections.

A mold transfer process may be carried out to encapsulate the components arranged on the leadframe with a mold material32as illustrated inFIG. 3H. The mold material32may encapsulate any portion of the device300, but leaves at least parts of the leads30uncovered. The exposed parts of the leads30may be used as external contact elements to electrically couple the device300to other components, for example a circuit board, such as a PCB (Printed Circuit Board).

The mold material32may be composed of any appropriate electrically insulating thermoplastic or thermosetting material, in one embodiment it may be composed of a material commonly used in contemporary semiconductor packaging technology. Various techniques may be employed to cover the components of the device300with the mold material32, for example compression molding, injection molding, powder molding or liquid molding.

Before or after the encapsulation with the mold material32, the individual devices300are separated from one another by separation of the leadframe, for example by sawing the dams. Afterwards, the leads30may be bent and/or trimmed as illustrated inFIG. 3I. Instead of having the leads30protruding from the mold material32, it is also possible to have a leadless device300.

It is obvious to a person skilled in the art that the devices100,200and300as illustrated inFIGS. 1C,2and3I are only intended to be exemplary embodiments, and many variations are possible. For example, it is possible to use metal particles27which have dimensions larger than 100 nm, for example in the range from 1 to 3 μm. These metal particles27may, for example, be made of AuSn or other metal alloys. They may also be coated by a layer28made of an organic or flux material and may be dispersed in a solvent29. However, rather than being sintered these metal particles27may be melted when attached to the carrier12. The temperature T2may be in the range from 300 to 500° C. and depends on the material of the metal particles27. Furthermore, instead of using metal particles27any other appropriate solder material may be used to attach the semiconductor chip10with the bare semiconductor surface21to the carrier12.

Another variation of the method illustrated inFIGS. 3A to 3Iis to stack two or more semiconductor chips on top of each other and using the method described above for attaching the semiconductor chips to each other.

Instead of the leadframe other carriers having at least one electrically conductive surface may be used. A DBC (Direct Bonded Copper) substrate may, for example, be used as the carrier to carry the semiconductor chip. A DBC substrate is composed of a ceramic carrier with a sheet of copper bonded to one or both sides.

FIGS. 4A to 4Hschematically illustrate a method for production of a device400, a cross section of which is illustrated inFIG. 4H. The method illustrated inFIGS. 4A to 4His similar or identical to the method ofFIGS. 3A to 3Iin many ways. In contrast to the method ofFIGS. 3A to 3I, the paste26containing the metal particles27is deposited on the carrier12and not on the semiconductor wafer20according to the method ofFIGS. 4A to 4H.

InFIG. 4Athe leadframe including the carrier (die pad)12and the leads30is illustrated. The paste26containing the metal particles27dispersed in the solvent29may be applied to the upper surface of the carrier12as illustrated inFIG. 4B. The application of the paste26may be performed by stencil printing, other printing technologies or any other appropriate technique, for example dispensing or spin-coating metal particles27may include a layer28.

After the application of the paste26, the leadframe may be exposed to the temperature T1in an oven, which may be smaller than 150° C. The exposure time may be arbitrary, in one embodiment it may be long enough to allow the solvent29to at least partially evaporate leaving the metal particles27localized on the carrier12as illustrated inFIG. 4C. The solvent29may evaporate without any residues.

Then the semiconductor chip10may be placed over the metal particles27with the exposed semiconductor surface21facing the carrier12. In order to have an oxide free first surface21so that an electrical contact can be established between the bare semiconductor electrode23(which is indicated inFIG. 4Dby dashed lines) and the carrier12later on, any semiconductor oxide may be removed from the first surface21of the semiconductor chip10before placing the semiconductor chip10on the metal particles27. Removing the semiconductor oxide may, for example, be carried out by dipping the semiconductor chip10into a HF solution or by plasma etching with a mixture of argon and hydrogen or any other appropriate etching method.

After the semiconductor chip10has been placed over the carrier12, the same processes may be carried out as illustrated inFIGS. 3F to 3Iand described above. As illustrated inFIG. 4Eheat may be applied to expose the metal particles27to the temperature T2in order to produce the sintered metal layer14. During the sintering process the semiconductor chip10may be pressed onto the carrier12for an appropriate time. Then electrical contacts between the electrodes24and25and the leads30may be established by bond wires31as illustrated inFIG. 4F. At least some of the components of the device400may be encapsulated with the mold material32as illustrated inFIG. 4G. The individual devices400may be separated from one another by separation of the leadframe, for example by sawing the dams. Afterwards, the leads30may be bent and/or trimmed as illustrated inFIG. 4H.