PRINTED CIRCUIT BOARD

A printed circuit board includes: a first metal layer; an organic insulating layer covering at least a portion of the first metal layer and having a via hole exposing at least a portion of an upper surface of the first metal layer; a first seed metal layer disposed on an upper surface of the organic insulating layer; a second seed metal layer disposed on the first seed metal layer and extending onto a wall surface of the via hole and the exposed upper surface of the first metal layer; and a second metal layer disposed on the second seed metal layer and filling at least a portion of the via hole, wherein the first seed metal layer includes a first sputtering layer including titanium (Ti), and the second seed metal layer includes an electroless plating layer.

CROSS-REFERENCE TO RELATED APPLICATION (S)

This application claims benefit of priority to Korean Patent Application No. 10-2022-0170860 filed on Dec. 8, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a printed circuit board.

2. Description of Related Art

Chiplet technology is emerging in accordance with a limitation in increasing a size of a semiconductor chip to cope with the implementation of multifunctionality and high performance therein, and accordingly, a wiring of a package board has a gradually smaller line with or separation distance. In a semi-additive process (SAP) method, it is necessary to minimize an amount of flash etching by forming a thin seed layer in order to respond to such miniaturization. The thin seed layer for this purpose may require high adhesion to an insulating material having low roughness and an excellent coverage property in a via hole.

SUMMARY

An aspect of the present disclosure may provide a printed circuit board including an organic insulating layer and a seed metal layer which may have high adhesion and may simultaneously have an excellent coverage property in a via hole.

The present disclosure may provide a printed circuit board in which a first seed metal layer including a titanium (Ti) layer or a copper (Cu) layer is formed on an organic insulating material using a sputtering method, and a second seed metal layer is formed on the first seed metal layer and in a via hole using an electroless plating (e.g., chemical copper) method.

According to an aspect of the present disclosure, a printed circuit board may include: a first metal layer; an organic insulating layer covering at least a portion of the first metal layer and having a via hole exposing at least a portion of an upper surface of the first metal layer; a first seed metal layer disposed on an upper surface of the organic insulating layer; a second seed metal layer disposed on the first seed metal layer and extending onto a wall surface of the via hole and the exposed upper surface of the first metal layer; and a second metal layer disposed on the second seed metal layer and filling at least a portion of the via hole, wherein the first seed metal layer includes a first sputtering layer having titanium (Ti), and the second seed metal layer includes an electroless plating layer.

According to another aspect of the present disclosure, a printed circuit board may include: an organic insulating layer; a conductor pad disposed below the organic insulating layer; a wiring layer disposed on the organic insulating layer; and a conductor via penetrating through the organic insulating layer and connecting the wiring layer to the conductor pad, wherein the wiring layer includes a first seed metal layer including a first sputtering layer having titanium (Ti), a second seed metal layer disposed on the first seed metal layer and including an electroless plating layer, and a metal layer disposed on the second seed metal layer and including an electrolytic plating layer, and the conductor via includes the second seed metal layer and the metal layer.

According to still another aspect of the present disclosure, a printed circuit board may include: a first metal layer; an organic insulating layer disposed on the first metal layer; a second metal layer disposed on the organic insulating layer; a via protruding from a lower surface of the second metal layer and disposed in a via hole penetrating through the organic insulating layer; a first seed metal layer including a first sputtering layer having titanium (Ti) and comprising at least a portion disposed between an upper surface of the organic insulating layer and the lower surface of the second metal layer; and a second seed metal layer including an electroless plating layer and comprising at least a portion disposed between a wall surface of the via hole and the via.

DETAILED DESCRIPTION

Electronic Device

FIG.1is a block diagram schematically illustrating an example of an electronic device system.

Referring toFIG.1, an electronic device1000may accommodate a main board1010. The main board1010may include chip-related components1020, network-related components1030, other components1040and the like, which are physically or electrically connected thereto. These components may be connected to other electronic components described below to form various signal lines1090.

The chip-related components1020may include a memory chip such as a volatile memory (for example, a dynamic random access memory (DRAM)), a non-volatile memory (for example, a read only memory (ROM)), or a flash memory; an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller; and a logic chip such as an analog-to-digital (ADC) converter or an application-specific integrated circuit (ASIC). However, the chip-related components1020are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components1020may be combined with each other. The chip-related component1020may be a package including the above-mentioned chip or electronic component.

The other components1040may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, low temperature co-firing ceramics (LTCC), an electro magnetic interference (EMI) filter, a multi-layer ceramic condenser (MLCC) and the like. However, the other components1040are not limited thereto, and may further include a passive device in the form of a chip component used for various other purposes in addition to these components. In addition, the other components1040may be combined with the chip-related components1020or the network-related components1030.

The electronic device1000may include another electronic component that may be or may not be physically or electrically connected to the main board1010, based on a type of the electronic device1000. Another electronic component may be a camera module1050, an antenna module1060, a display1070, a battery1080, etc. However, another electronic component is not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. In addition, another electronic component may be another electronic component used for various purposes, based on the type of the electronic device1000.

The electronic device1000may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet personal computer (PC), a laptop PC, a netbook PC, a television, a video game machine, a smartwatch, an automotive or the like. However, the electronic device1000is not limited thereto, and may also be any other electronic device processing data.

FIG.2is a perspective view schematically illustrating an example of an electronic device.

Referring toFIG.2, the electronic device may be, for example, a smartphone1100. The smartphone1100may accommodate a motherboard1110, and various components1120may be physically or electrically connected to the motherboard1110. In addition, the motherboard1110may accommodate other components that may or may not be physically or electrically connected thereto, such as the camera module1130or a speaker1140. Some of the components1120may be the chip-related components, for example, a component package1121, and are not limited thereto. The component package1121may be in the form of a printed circuit board on which electronic components including active components or passive components are surface mounted. Alternatively, the component package1121may be in the form of a printed circuit board in which the active components or the passive components are embedded. Meanwhile, the electronic device is not necessarily limited to the smartphone1100, and may be another electronic device as described above.

Printed Circuit Board

FIG.3is a cross-sectional view schematically illustrating a printed circuit board according to an exemplary embodiment.

Referring toFIG.3, a printed circuit board100A according to an exemplary embodiment may include an organic insulating layer110, a conductor pad P and a wiring layer W each disposed below and above the organic insulating layer110, and a conductor via V passing through organic insulating layer110and connecting the wiring layer W to the conductor pad P. Here, the conductor pad P may include a first metal layer120. In addition, the wiring layer W may include a first seed metal layer130, a second seed metal layer140, and a second metal layer150. In addition, the conductor via V may include the first seed metal layer130, the second seed metal layer140, and the second metal layer150.

For example, the printed circuit board100A according to an exemplary embodiment may include: the first metal layer120; the organic insulating layer110covering at least a portion of the first metal layer120and having a via hole H exposing at least a portion of an upper surface of the first metal layer120; the first seed metal layer130disposed on an upper surface of the organic insulating layer110; the second seed metal layer140disposed on the first seed metal layer130and extending onto a wall surface of the via hole H and the exposed upper surface of the first metal layer120; and the second metal layer150disposed on the second seed metal layer140and filling at least a portion of the via hole H. Here, the first seed metal layer130may be in contact with at least a portion of the upper surface of the organic insulating layer110, and may extend to be in contact with the via hole H and the exposed upper surface of the first metal layer120. In addition, the second seed metal layer140may be disposed on the first seed metal layer130in the via hole H.

Meanwhile, the first seed metal layer130may include a first sputtering layer131having titanium (Ti), and the second seed metal layer140may include an electroless plating layer141including copper (Cu), for example, a chemical copper plating layer. Accordingly, it is possible to secure excellent adhesion with the organic insulating layer110through the first seed metal layer130. In addition, it is possible to secure an excellent coverage property in the via hole H through the second metal layer150. For example, it is possible to secure both the excellent adhesion with an organic insulating material and the excellent coverage property in the via hole by sequentially forming the first seed metal layer130including a sputtering layer having titanium (Ti) and the second seed metal layer140including an electroless plating layer including chemical copper in this order. If necessary, the electroless plating layer141may include a further metal material, other than copper (Cu). However, it may be more effective to have the above-mentioned effects that the electroless plating layer141includes copper (Cu), that is, the chemical copper layer. Components of the first and second seed metal layers140may be measured by a focused ion beam (FIB) analysis or a transmission electron microscope (TEM) analysis, based on a cut cross section of the printed circuit board100A.

Meanwhile, the sputtering layer may be a layer formed based on a chemical bonding mechanism in which an unstable (e.g., high-energy) atomic metal in a plasma reacts with an organic material, thus securing the excellent adhesion regardless of roughness of the organic material. In addition, the electroless plating layer may be a layer formed based on a mechanism of depositing metal ions in a solution on the organic material, for example, a layer including chemical copper. As such, the electroless plating layer may be formed in a wet process, thus securing the excellent coverage property in the via hole.

How to check: What remains after a seed layer removal process is a lower part of a circuit pattern. It is possible to check the components of the corresponding layer by obtaining a cut surface of this part and performing a component analysis during the FIB or TEM analysis.

Hereinafter, the description describes the components of the printed circuit board100A according to an exemplary embodiment in more detail with reference to the drawings.

The organic insulating layer110may include the organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler, or a glass fiber (i.e., glass fiber, glass cloth or glass fabric) together with this resin. The organic insulating material may be a photosensitive material or a non-photosensitive material. For example, the organic insulating layer110may use an insulating material such Ajinomoto build-up film (ABF), prepreg (PPG), or resin coated copper (RCC), is not limited thereto, and may also use photo imageable dielectric (PID). If necessary, the organic insulating layer110may use another polymer material having excellent rigidity. The organic insulating layer110may include Ajinomoto build-up film (ABF) or Ajinomoto build-up film (ABF) having low roughness, but is not limited thereto.

The conductor pad P may include a metal material. For example, the conductor pad P may include the first metal layer120. The first metal layer120may include an electrolytic plating layer121including copper (Cu). However, the first metal layer120is not limited thereto, and may include the electroless plating layer (or chemical copper) and the electrolytic plating layer (or electrolytic copper). Alternatively, the first metal layer120may include a metal foil (or copper foil) and the electrolytic plating layer (or electrolytic copper). Alternatively, the first metal layer120may include the metal foil (or copper foil), the electroless plating layer (or chemical copper), and the electrolytic plating layer (or electrolytic copper). The first metal layer120may include the sputtering layer instead of the electroless plating layer (or chemical copper), or include both the layers, if necessary. Meanwhile, the electrolytic plating layer121may include a further metal material, other than copper (Cu). The conductor pad P may include a ground conductor pad, a power conductor pad, a signal conductor pad, or the like. Here, the signal conductor pad may include a conductor pad providing an electrical path for various signals other than the ground conductor pad, the power conductor pad, and the like, for example, a data signal. The conductor pad P may be electrically connected to a wiring layer, for example, a line pattern, disposed on the same layer.

The wiring layer W may include the metal material. For example, the wiring layer W may include the first seed metal layer130including the first sputtering layer131having titanium (Ti), the second seed metal layer140disposed on the first seed metal layer130and including the electroless plating layer141including copper (Cu), and the second metal layer150disposed on the second seed metal layer140and including an electrolytic plating layer151including copper (Cu). The electrolytic plating layer151may have a larger grain size than that of the electroless plating layer141, and these two grain sizes may be analyzed and compared using the transmission electron microscope (TEM) based on the cut cross section of the printed circuit board100A. Meanwhile, the electrolytic plating layer151may include a further metal material, other than copper (Cu). The wiring layer W may perform various functions based on a design thereof. For example, the wiring layer W may include a ground pattern, a power pattern, a signal pattern, or the like. Here, the signal pattern may include various signals other than the ground pattern, the power pattern, and the like, for example, the data signal. Each of these patterns may include the line pattern, a plane pattern, or a pad pattern. The pad pattern may include a land pattern.

The conductor via V may include the metal material. The conductor via V may be formed in the same process as the wiring layer W, and may thus be integrated with at least a portion of the wiring layer W. For example, the conductor via V may also include the first seed metal layer130including the first sputtering layer131having titanium (Ti), the second seed metal layer140disposed on the first seed metal layer130and including the electroless plating layer141including copper (Cu), and the second metal layer150disposed on the second seed metal layer140and including an electrolytic plating layer151including copper (Cu). Meanwhile, the electrolytic plating layer151may include a further metal material, other than copper (Cu). The conductor via V may be a filed via filling the via hole H, or may be a conformal via disposed along the wall surface of the via hole H. The conductor via V may perform various functions based on a design thereof. For example, the conductor via V may include a ground via, a power via, a signal via, or the like. Here, the signal via may include a via for transferring various signals other than the ground via, the power via, and the like, for example, the data signal.

Meanwhile, the structure of the printed circuit board100A according to an exemplary embodiment as described above may be applied to at least a portion of a multilayer printed circuit board. For example, the above-mentioned organic insulating layer110, conductor pad P, wiring layer W, conductor via V, and the like may be implemented in a multi-layered stacked form to be applied to the multilayer printed circuit board. In addition, the above-mentioned plurality of conductor pads P, wiring layers W, conductor vias V, and the like may be disposed in the above-mentioned organic insulating layer110at the same level. The multilayer printed circuit board may have various forms such as a coreless-type board and a core-type board. The multilayer printed circuit board may be a board for various purposes such as a package board.

FIG.4is a cross-sectional view schematically illustrating a printed circuit board in another embodiment.

Referring toFIG.4, compared to the above-described printed circuit board100A according to an exemplary embodiment, in a printed circuit board100B in another embodiment, the first seed metal layer130may further include a second sputtering layer132disposed on the first sputtering layer131and including copper (Cu). For example, the first seed metal layer130may include multiple sputtering layers. Meanwhile, the second sputtering layer132may be disposed between the first sputtering layer131and the electroless plating layer141. For example, the electroless plating layer141of the second seed metal layer140that includes copper (Cu), for example, the chemical copper layer, may be disposed on the second sputtering layer132of the first seed metal layer130that includes copper (Cu). However, these two layers may be distinguished from each other even in this case. For example, the second sputtering layer132may include copper (Cu) without nickel (Ni), whereas the electroless plating layer141may further include nickel (Ni) in addition to copper (Cu). Nickel (Ni) may have a high concentration at a boundary with the material and may be found in most regions. Therefore, both the materials may be distinguished from each other by measuring a nickel (Ni) component. Meanwhile, the second sputtering layer132including copper (Cu) may further improve the adhesion between the first sputtering layer131including titanium (Ti) and the electroless plating layer141including copper (Cu). Other contents are substantially the same as those described in the above-described printed circuit board100A according to an exemplary embodiment, and the description thus omits redundant descriptions thereof.

FIG.5is a cross-sectional view schematically illustrating a printed circuit board in still another embodiment.

Referring toFIG.5, compared to the above-mentioned printed circuit board100A according to an exemplary embodiment, in a printed circuit board100C in still another embodiment, the first seed metal layer130may not extend to be disposed inside the via hole H while being in contact with at least a portion of the upper surface of the organic insulating layer110. Accordingly, the second seed metal layer140may be in contact with the wall surface of the via hole H and the exposed upper surface of the first metal layer120. For example, the conductor via V may include the second seed metal layer140and the second metal layer150, and may not include the first seed metal layer130. For example, the first seed metal layer130, for example, the first sputtering layer131including titanium (Ti) may be formed before processing the via hole H, and the second seed metal layer140and the second metal layer150may then be formed after processing the via hole H. In this case, it is possible to suppress occurrence of an interlayer void between the first sputtering layer131including titanium (Ti) and the first metal layer120including the electrolytic plating layer121in a chemical copper process. Other contents are substantially the same as those described in the above-described printed circuit board100A according to an exemplary embodiment, and the description thus omits redundant descriptions thereof.

FIG.6is a cross-sectional view schematically illustrating a printed circuit board in yet another embodiment.

Referring toFIG.6, compared to the above-mentioned printed circuit board100B, in a printed circuit board100D in yet another embodiment, the first seed metal layer130may not extend to be disposed inside the via hole H while being in contact with at least a portion of the upper surface of the organic insulating layer110. Accordingly, the second seed metal layer140may be in contact with the wall surface of the via hole H and the exposed upper surface of the first metal layer120. For example, the conductor via V may include the second seed metal layer140and the second metal layer150, and may not include the first seed metal layer130. For example, the first seed metal layer130, for example, the first sputtering layer131including titanium (Ti) and the second sputtering layer132including copper (Cu) may be sequentially formed before processing the via hole H, and the second seed metal layer140and the second metal layer150may then be formed after processing the via hole H. In this case, it is possible to suppress the occurrence of the interlayer void between the first sputtering layer131including titanium (Ti) and the first metal layer120including the electrolytic plating layer121in the chemical copper process. Other contents are substantially the same as those described in the above-described printed circuit board100A according to an exemplary embodiment and printed circuit board100B in another embodiment, and the description thus omits redundant descriptions thereof.

FIGS.7A,7B and7Care images schematically illustrating cases of forming the first sputtering layer including titanium (Ti) and the second sputtering layer including copper (Cu) as the seed metal layers, respectively. Referring toFIGS.7A,7B and7C, only the first sputtering layer including titanium (Ti) and the second sputtering layer including copper (Cu), that is, the multi-layer sputtering layer, may be formed as the seed metal layer. In this case, the adhesion with the organic insulating material such as ABF may be good, for example, about 0.84 kgf/cm. However, a direction in which the first and second sputtering layers are formed may be fixed to a certain direction, and a through power may thus be lower than that in a case of forming chemical copper, which is the electroless plating layer. Therefore, the coverage property may not be sufficient, such as breakage of the seed metal layer due to roughness of a processed surface in the via hole.

FIGS.8A,8B and8Care images schematically illustrating cases of forming the sputtering layer including titanium (Ti) and the electroless plating layer including copper (Cu) as the seed metal layers, respectively.

Referring toFIGS.8A,8B and8C, the sputtering layer including titanium (Ti) and the electroless plating layer including copper (Cu) may be all formed as the seed metal layers in this order. In this case, the adhesion with the organic insulating material such as ABF may be better, for example, about 0.61 kgf/cm, than the adhesion in a case of simply forming only chemical copper, which is the electroless plating layer, for example, about 0.2 kgf/cm. In addition, it is possible to secure a sufficient plating thickness at the bottom of the via hole, and have the excellent coverage property such as excellent connectivity of the seed metal layer even when the wall surface of the via hole is rough.

FIGS.9A,9B and9Care images schematically illustrating cases of forming the first sputtering layer including titanium (Ti), the second sputtering layer including copper (Cu), the electroless plating layer including copper (Cu) as the seed metal layers, respectively.

Referring toFIGS.9A,9B and9C, the first sputtering layer including titanium (Ti), the second sputtering layer including copper (Cu), and the electroless plating layer including copper (Cu) may be all formed as the seed metal layers in this order. In this case, the adhesion with the organic insulating material such as ABF may be better, for example, about 0.88 kgf/cm. Similarly, it is possible to simultaneously secure the sufficient plating thickness at the bottom of the via hole, and also have the excellent coverage property such as the excellent connectivity of the seed metal layer even when the wall surface of the via hole is rough.

FIG.10is a cross-sectional view schematically illustrating a printed circuit board according to another exemplary embodiment.

Referring toFIG.10, a printed circuit board600according to another exemplary embodiment may include a first board unit300, a second board unit400disposed on the first board unit300, a first resist layer510disposed on the second board unit400, or a second resist layer520disposed on a surface of the first board unit300that is opposite to its surface on which the second board unit400is disposed. The first board unit300may be a general multilayer board, and the second board unit400may be a build-up board including a microcircuit formed on the first board unit300. Here, the structure of the above-described printed circuit boards100A,100B,100C, or100D may be applied to a build-up wiring layer421or a connection via layer431, included in the second board unit400, which is the build-up board including the microcircuit. Here, the structure of the above-described printed circuit boards100A,100B,100C, or100D is not limited thereto, and may be applied to the build-up wiring layers323and324or connection via layers332and333of the first board unit300, if necessary.

Meanwhile, the build-up wiring layer421included in the second board unit400may have a higher wiring density than core wiring layers321and322or the build-up wiring layers323and324, included in the first board unit300. For example, the build-up wiring layer421of the second board unit400may include a higher-density wiring with a relatively fine pitch, and the core wiring layers321and322or build-up wiring layers323and324of the first board unit300may each include a lower-density wiring. For example, the build-up wiring layer421of the second board unit400may have smaller wiring thickness, lines/space, pitch, or the like than the core wiring layers321and322or build-up wiring layers323and324of the first board unit300. In addition, an insulation distance between the build-up wiring layers421disposed on different layers of the second board unit400may also be smaller than an insulation distance between the core wiring layers321and322or the build-up wiring layers323and324, disposed on different layers of the first board unit300.

Hereinafter, the description describes the components of the printed circuit board600a according to another exemplary embodiment in more detail with reference to the drawings.

The first board unit300may be a core-type multilayer board. For example, the first board unit100may include a core insulating layer311, the first and second core wiring layers321and322respectively disposed on upper and lower surfaces of the core insulating layer311, a through via layer331passing through the core insulating layer311and connecting the first and second core wiring layers321and322to each other, a plurality of first build-up insulating layers312disposed on the upper surface of the core insulating layer311, the plurality of first build-up wiring layers323respectively disposed on or in the insulating layers312, the plurality of first build-up plurality of first connection via layers332each passing through at least one of the plurality of first build-up insulating layers312and each connected to at least one of the plurality of first build-up wiring layers323, a plurality of second build-up insulating layers313disposed on the lower surface of the core insulating layer311, the plurality of second build-up wiring layers324respectively disposed on or in the plurality of second build-up insulating layers313, and the plurality of second connection via layers333each passing through at least one of the plurality of second build-up insulating layers313and each connected to at least one of the plurality of second build-up wiring layers324.

The core insulating layer311may include the insulating material. The insulating material may use a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, a material in which this insulating resin is mixed with an inorganic filler such as silica, a resin impregnated into a core material such as a glass fiber (i.e., glass fiber, glass cloth or glass fabric) together with the inorganic filler, for example, copper clad laminate (CCL), or the like, and is not limited thereto. The core insulating layer311may have a thickness greater than each thickness of the first and second build-up insulating layers312and313, and is not limited thereto.

Each of the first and second build-up insulating layers312and313may include the insulating material. The insulating material may use the thermosetting resin such as the epoxy resin or the thermoplastic resin such as the polyimide, the material in which this insulating resin is mixed with the inorganic filler such as silica, the resin impregnated into the core material such as the glass fiber (i.e., glass fiber, glass cloth or glass fabric) together with the inorganic filler, for example, Ajinomoto build-up film (ABF), prepreg, resin coated copper (RCC), or the like, and is not limited thereto. The first and second build-up insulating layers312and313are not limited to a specific number of layers, may have the same number of layers, and are not limited thereto.

The first and second core wiring layers321and322may each include a metal material. The metal material may use copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first and second core wiring layers321and322may each include an electroless plating layer (or chemical copper) and the electrolytic plating layer (or electrolytic copper), and are not limited thereto. The first and second core wiring layers321and322may each include a sputtering layer instead of the electroless plating layer (or chemical copper), or include both the layers. In addition, the first and second core wiring layers321and322may each include a copper foil. The first and second core wiring layers321and322may perform various functions based on designs thereof. For example, the first and second core wiring layers321and322may each include a ground pattern, a power pattern, a signal pattern, or the like. Here, the signal pattern may include various signals other than the ground pattern, the power pattern, and the like, for example, a data signal. Each of these patterns may include a line pattern, a plane pattern, or a pad pattern.

Each of the first and second build-up wiring layers323and324may include the metal material. The metal material may use copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first and second build-up wiring layers323and324may each include the electroless plating layer (or chemical copper) and the electrolytic plating layer (or electrolytic copper), and are not limited thereto. The first and second build-up wiring layers323and324may each include the sputtering layer instead of the electroless plating layer (or chemical copper), or include both the layers. In addition, the first and second build-up wiring layers323and324may each include the copper foil. The first and second build-up wiring layers323and324may each perform various functions based on designs thereof. For example, the first and second build-up wiring layers323and324may each include the ground pattern, the power pattern, the signal pattern, or the like. Here, the signal pattern may include various signals other than the ground pattern, the power pattern, and the like, for example, the data signal. Each of these patterns may include the line pattern, the plane pattern, or the pad pattern.

The through via layer331may include a through via. The through via may include a metal layer formed on a wall surface of a through hole and a plug filling the metal layer. The metal layer may include the metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The plug may include ink including the insulating material. The metal layer may include the electroless plating layer (or chemical copper) and the electrolytic plating layer (or electrolytic copper), and is not limited thereto. The through via layer331may include the sputtering layer instead of the electroless plating layer (or chemical copper), or include both the layers. The through via layer331may perform various functions depending on a design thereof. For example, the through via layer331may include a ground via, a power via, a signal via, or the like. Here, the signal via may include a via for transferring various signals other than the ground via, the power via, and the like, for example, the data signal.

The first and second connection via layers332and333may include microvias. The microvia may be a filled via that fills a via hole or a conformal via that is disposed along a wall surface of the via hole. The microvias may be disposed in a stacked type or a staggered type. Each of the first and second connection via layers332and333may include the metal material, and the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first and second connection via layers332and333may each include the electroless plating layer (or chemical copper) and the electrolytic plating layer (or electrolytic copper), and are not limited thereto. The first and second connection via layers332and333may each include the sputtering layer instead of the electroless plating layer (or chemical copper), or include both the layers. The first and second connection via layers332and333may each perform various functions based on designs thereof. For example, the first and second connection via layers332and333may each include the ground via, the power via, the signal via, or the like. Here, the signal via may include the via for transferring various signals other than the ground via, the power via, and the like, for example, the data signal.

The second board unit400may be the coreless-type multilayer build-up board including the microcircuit. For example, the second board unit400may include a plurality of third build-up insulating layers411, the plurality of third build-up wiring layers421respectively disposed on or in the plurality of third build-up insulating layers411, and a plurality of third connection via layers431each passing through at least one of the plurality of third build-up insulating layers411and each connected to at least one of the plurality of third build-up wiring layers421.

The third build-up insulating layer411may include the insulating material. The insulating material may use the thermosetting resin such as the epoxy resin or the thermoplastic resin such as the polyimide, the material in which this insulating resin is mixed with the inorganic filler such as silica, the resin impregnated into the core material such as the glass fiber (i.e., glass fiber, glass cloth or glass fabric) together with the inorganic filler, for example, Ajinomoto build-up film (ABF), prepreg, resin coated copper (RCC), or the like, and is not limited thereto. The third build-up insulating layer411is not limited to a specific number of layers.

The third build-up wiring layer421may include the metal material. The metal material may use copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The third build-up wiring layer421may include the electroless plating layer (or chemical copper) and the electrolytic plating layer (or electrolytic copper), and is not limited thereto. The third build-up wiring layer421may include the sputtering layer instead of the electroless plating layer (or chemical copper), or include both the layers. In addition, the third build-up wiring layer421may include the copper foil. The third build-up wiring layer421may perform various functions based on a design thereof. For example, the third build-up wiring layer421may include the ground pattern, the power pattern, the signal pattern, or the like. Here, the signal pattern may include various signals other than the ground pattern, the power pattern, and the like, for example, the data signal. Each of these patterns may include the line pattern, the plane pattern, or the pad pattern.

The third connection via layer431may include the microvia. The microvia may be the filled via that fills the via hole or the conformal via that is disposed along the wall surface of the via hole. The microvias may be disposed in the stacked type or the staggered type. The third connection via layer431may include the metal material, and the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The third connection via layer431may include the electroless plating layer (or chemical copper) and the electrolytic plating layer (or electrolytic copper), and is not limited thereto. The third connection via layer431may include the sputtering layer instead of the electroless plating layer (or chemical copper), or include both the layers. The third connection via layer431may perform various functions based on a design thereof. For example, the third connection via layer431may include the ground via, the power via, the signal via, or the like. Here, the signal via may include the via for transferring various signals other than the ground via, the power via, and the like, for example, the data signal.

The first and second resist layers510and520may each include the insulating material, and the insulating material may use a liquid-type or film-type solder resist. However, the first or second resist layer510or520is not limited thereto, and may use another material. The first resist layer510may include a first opening h1exposing at least a portion of each of a plurality of first outer pads P1disposed on an upper surface of the uppermost build-up wiring layer of the second board unit400. For example, one first opening h1may expose at least a portion of each of the plurality of first outer pads P1. A first surface treatment layer may be formed on each of the plurality of first outer pads P1exposed through each first opening h1. Each of the first surface treatment layers may cover the upper surface and side surface of each of the first outer pads P1. The second resist layer520may include a plurality of second openings h2each exposing at least a portion of each of a plurality of second outer pads P2disposed on a lower surface of the lowermost build-up wiring layer of the first board unit300. For example, the plurality of second openings h2may each expose at least a portion of each of the plurality of second outer pads P2. A second surface treatment layer may be formed on each of the plurality of second outer pads P2exposed through each second opening h2. Each of the second surface treatment layers may cover a lower surface of each of the second outer pads P2.

As set forth above, the present disclosure may provide the printed circuit board including the organic insulating layer and the seed metal layer which may have the high adhesion and simultaneously have the excellent coverage property in the via hole.

In the present disclosure, a meaning of the expression, “substantially,” may be determined by including a process error, a positional deviation, an error in measurement, and the like that occur in the process. In addition, connection between two components conceptually includes their indirect connection through a third component as well as their direct connection. In addition, it may be understood that when an element is referred to with terms such as “first” and “second,” the element is not limited thereby. These terms are used only to distinguish the element from another element, and may not limit the sequence or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize each particular feature different from that of another exemplary embodiment. However, the exemplary embodiments provided herein may be implemented in combination with features of another exemplary embodiment. For example, a description of an element in a specific exemplary embodiment may be understood as its description in another exemplary embodiment even though the element is not described in another exemplary embodiment, unless an opposite or contradictory description is provided therein.

The terms used herein are used only to describe an exemplary embodiment rather than limiting the present disclosure. Here, a term of a singular number includes its plural number unless explicitly interpreted otherwise in context.