Package assembly and manufacturing method thereof

A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.

BACKGROUND

Currently, semiconductor packages including both photonic dies (known as P-dies) and electronic dies (known as E-dies) are becoming increasingly popular for their compactness. In addition, due to the widely use of optical fiber-related applications for signal transmission, optical signaling and processing have been used in more applications. Although existing methods of fabricating the semiconductor packages have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, challenges rise to develop robust processes for interconnecting among P-dies, E-dies, and optical fibers.

DETAILED DESCRIPTION

Embodiments of the present disclosure are discussed in the context of semiconductor manufacturing, and in particular, in the context of forming a package assembly, wherein the package assembly includes a package component having a photonic die and an electronic die, and an optical signal port optically coupled to the photonic die of the package component. Some variations of embodiments are discussed and the intermediate stages of forming the package assembly are illustrated in accordance with some embodiments. It should be appreciated that the illustration throughout the drawings are schematic and not in scale.

FIG.1Ais a schematic top view of a package assembly in accordance with some embodiments, andFIGS.1B and1Care schematic cross-sectional views respectively taken along an A-A′ line and a B-B′ line illustrated inFIG.1Ain accordance with some embodiments. Referring toFIGS.1A-1C, a package assembly10includes a first package component100A and an optical signal port200A facing an outer sidewall100sof the first package component100A and optically coupled to the first package component100A.

In some embodiments, the optical signal port200A is an optical input/output (I/O) port where optical signals may enter and/or exit. For example, the optical signal port200A includes at least one fiber210and an optical interface layer220interposed between the fiber210and the first package component100A for bonding the fiber210to the first package component100A. In some embodiments, at least the end portion of the fiber210is inserted into the optical interface layer220. In some embodiments, a plurality of fibers210is arranged in a parallel manner to form a fiber array module. For example, the fiber210may be a lensed fiber in which a lens shape for an optical connection is formed at a tip portion facing the outer sidewall100sof the first package component100A. In some embodiments, a fiber mesa230is configured to abut against the fibers210to support or secure the fibers210. Alternatively, the fiber mesa230is omitted.

In some embodiments, the fibers210are bonded to the first package component100A by applying the optical interface layer220to the end portions of the fibers210and the outer sidewall100sof the first package component100A. For example, the optical interface layer220includes clear (or transparent) adhesive or other suitable optical glue/grease. In some embodiments, the optical interface layer220is facilitated by the optical adhesive to provide optical transparency and mechanical fixation. In some embodiments, the optical interface layer220is a layer of index-matching adhesive. For example, the optical interface layer220is index-matched to the fibers210and to the outer sidewall100sof the first package component100A to reduce optical loss. The refractive index and the thickness of the optical interface layer220may be adjusted according to the refractive indices of the fibers210and the first package component100A. The optical interface layer220may be a single-layer or multi-layer structure. The material of the optical interface layer220may include an epoxy based compound, a silicone based compound, an acrylic based compound, a combination thereof, or the like.

In some embodiments, IC packaging techniques, such as integrated fanout (InFO) packaging techniques, are used to fabricate the first package component100A. Other packaging techniques may be used to form the first package component100A. For example, the first package component100A includes at least one photonic die PD and at least one electronic die ED electrically coupled to the photonic die PD. It is noted that the photonic die PD and the electronic die ED are illustrated in phantom in the top view to indicate that they may be covered. It is also noted that the size, the number, and the configuration of the photonic die PD and/or the electronic die ED are depicted for illustration purpose only.

In some embodiments, the photonic die PD may include photonic integrated circuit to process, receive, and/or transmit optical signals. In some embodiments, the fibers210are aligned with the photonic die PD to enable exchange of optical signals between the photonic die PD and the fibers210. In some embodiments, the photonic die PD may convert electrical signals from the electronic die ED to optical signals. In some embodiments, the photonic die PD may convert optical signals from the optical signal port200A to electrical signals. In some embodiments, the photonic die PD includes active and/or passive optical devices responsible for the I/O of optical signals to/from the optical signal port200A. The active and/or passive optical devices may include I/O couplers, edge couplers, lasers, optical modulators, detectors, waveguides, splitters, converters, switches, grating couplers, etc. Since the bandwidth of the grating couplers is limited and the grating couplers are polarization dependent, the photonic die PD may be free of grating couplers formed therein in accordance with some embodiments. In some embodiments, the photonic die PD includes at least one edge coupler (1111; shown inFIGS.8A-9) which has broad bandwidth with small polarization dependent loss.

For example, the fibers210are laterally aligned with the edge coupler of the photonic die PD to provide the optical signals. In some embodiments, the fiber axis AX may be substantially parallel to a normal direction of the outer sidewall100sof the first package component100A. In some embodiments, an angle (e.g., between a few degrees to about 90 degrees) is formed between the fiber axis AX and the outer sidewall100sof the first package component100A. The angle between the fiber axis AX and the outer sidewall100smay be adjusted depending on the characteristics of the fiber210and depending on how well the optical connection is optimized. It is noted that the angle between the fiber axis AX and the outer sidewall100sconstrue no limitation in the disclosure. In some embodiments, the fibers210are bonded to the edge facet of the outer sidewall100scorresponding to the edge couplers through the optical interface layer220. It is noted that the detailed descriptions of the edge couplers of the photonic die PD will be discussed later in accompanying with figures.

Continue toFIGS.1B-1C, the photonic die PD includes a substrate111. For example, the substrate111may be or may include a bulk silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. In some embodiments, the substrate111is a semiconductor-on-insulator (SOI) substrate including a layer of a semiconductor material formed on an insulator layer. Other substrate may be used. For example, the substrate111includes a top surface111aand a bottom surface111bopposing to the top surface111a. In some embodiments, the photonic die PD includes a plurality of conductive pads112distributed over the top surface111a, a passivation layer113formed over the top surface111aand partially covering the conductive pads112, a plurality of die connectors114formed on the conductive pads112, and a protection layer115formed on the passivation layer113and at least laterally covering the die connectors114. It is noted that the above examples are provided for illustrative purposes only, and other embodiments may utilize fewer or additional elements. For example, additional elements (not shown; e.g., interconnect structure) may be formed on the top surface111aof the substrate111for interconnecting the conductive pads112.

A material of the conductive pads112may include aluminum, but other suitable conductive materials (e.g., copper) may be used. A material of the passivation layer113may be or may include silicon oxide, silicon nitride, low-k dielectric materials such as carbon doped oxides, extremely low-k dielectric materials such as porous carbon doped silicon dioxide, a combination thereof or other suitable material. A material of the die connectors114may be or may include metal (e.g., copper, silver, tungsten, titanium, gold, etc.), metal alloy, a combination thereof, or other suitable conductive material. A material of the protection layer115may be or may include polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or other suitable dielectric material.

In some embodiments, the photonic die PD is laterally encapsulated by a first insulating encapsulation120. For example, the sidewall PDs′ of the photonic die PD is covered by the optical interface layer220, and the first insulating encapsulation120extends along other sidewalls PDs of the photonic die PD. The first insulating encapsulation120may include a low moisture absorption rate and may be rigid for protecting the photonic die PD. A material of the first insulating encapsulation120may be or may include a molding compound (e.g., epoxy resin), a molding underfill, or other suitable electrically insulating material. In some embodiments, a protection layer125is formed on the first insulating encapsulation120and the bottom surface111bof the substrate111for protection. The protection layer125may be or may include a die attach film or other suitable dielectric material(s). Alternatively, the protection layer125is omitted.

Still referring toFIGS.1A-1C, in some embodiments, the photonic die PD and the electronic die ED are stacked upon one another. In some embodiments, the size of the photonic die PD is greater than the size of the electronic die ED. For example, the footprint area occupied by the photonic die PD is greater than the footprint area occupied by the electronic die ED. In some embodiments, as shown inFIG.1A, the footprint area occupied by the electronic die ED fully overlaps the footprint area occupied by the photonic die PD. In some other embodiments, the footprint area occupied by the electronic die ED partially overlaps the footprint area occupied by the photonic die PD in the top view. For example, the photonic die PD and the electronic die ED are stacked in a staggered manner. In some embodiments, the photonic die PD and the electronic die ED are stacked in a face-to-back manner. For example, the electronic die ED includes a substrate131having a top surface131aand a bottom surface131bopposing to each other. In some embodiments, the bottom surface131bof the substrate131(which is the back surface of the electronic die ED) and the top surface111aof the substrate111(which is the active surface of the photonic die PD) may face each other, and such configuration may be referred to as a face-to-back configuration.

In some embodiments, the electronic die ED includes electronic integrated circuits for processing the electrical signals converted from the optical signals in the photonic die PD. In some embodiments, the electronic die ED exchanges electrical signals with the photonic die PD. The electronic die ED may be or may include logic IC dies, memory dies, analog IC dies, application-specific IC (ASIC) dies, or the like. In other embodiments, the electronic die ED is a package structure of which a plurality of die components is encapsulated in a packaging encapsulation (not shown). In some embodiments, the photonic die PD is a photonic integrated circuit (PIC) die and the electronic die ED is an electronic integrated circuit (EIC) die.

In some embodiments, the substrate131of the electronic die ED may be a silicon substrate or a substrate formed of other semiconductor materials such as germanium, silicon germanium, a III-V compound semiconductor material, or the like. In some embodiments, the bottom surface131bof the substrate131is in contact with a die attach film DAF. For example, the substrate131includes a plurality of active/passive devices (not shown) formed thereon. Examples of active components include, but are not limited to, diodes, field effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, and bipolar transistors. Examples of passive components include, but are not limited to, resistors, capacitors, and inductors.

In some embodiments, the electronic die ED includes a plurality of conductive pads132distributed over the top surface131a, a passivation layer133formed over the top surface111aand partially covering the conductive pads132, a plurality of die connectors134formed on the conductive pads132, and a protection layer135formed on the passivation layer133and at least laterally covering the die connectors134. The conductive pads132and the die connectors134formed on the conductive pads132may be electrically coupled to the active/passive devices through an interconnect structure (not shown). Materials of the conductive pads132, the passivation layer133, the die connectors134, and the protection layer135may be respectively similar to the materials of the conductive pads112, the passivation layer113, the die connectors114, and the protection layer115, and the detailed descriptions are omitted for the sake of brevity.

In some embodiments, the electronic die ED is laterally encapsulated by a second insulating encapsulation140. For example, the second insulating encapsulation140extends along the sidewalls EDs of the electronic die ED. The sidewall PDs′ of the photonic die PD is substantially leveled with a sidewall140swof the first insulating encapsulation140. A material of the second insulating encapsulation140may be similar to that of the first insulating encapsulation120, and the detailed descriptions are omitted for the sake of brevity. In some embodiments, a first redistribution structure150including a first patterned dielectric layer152and a first patterned conductive layer154is interposed between the electronic die ED and the photonic die PD. For example, the first patterned dielectric layer152is formed on the photonic die PD and the first insulating encapsulation120, and a plurality of openings (not labeled) of the first patterned dielectric layer152may accessibly expose the die connectors114of the photonic die PD. For example, the first patterned dielectric layer152may be formed of PBO, polyimide, BCB, or the like. In some embodiments, the electronic die ED is attached to the first patterned dielectric layer152through the die attach film DAF. The first patterned conductive layer154may be formed in the openings of the first patterned dielectric layer152to be in physical and electrical contact with the die connectors114of the photonic die PD. For example, the first patterned conductive layer154is formed of a conductive material, which may be a metallic material such as tungsten, copper, titanium, or the like.

In some embodiments, a plurality of through insulating vias (TIVs)160penetrate through the second insulating encapsulation140and may be disposed aside the electronic die ED. In some embodiments, the electronic die ED is surrounded by the TIVs160. The TIVs160may be in physical and electrical contact with the first patterned conductive layer154of the first redistribution structure150. The TIVs160may be formed of conductive material, such as tungsten, copper, titanium, or the like.

In some embodiments, a second redistribution structure170including a second patterned dielectric layer172and a second patterned conductive layer174is formed on the electronic die ED, the second insulating encapsulation140, and the TIVs160. For example, the second patterned dielectric layer172is formed on the electronic die ED, the second insulating encapsulation140, and the TIVs160, and a plurality of openings (not labeled) of the second patterned dielectric layer172may accessibly expose the TIVs160and the die connectors134of the electronic die ED. The second patterned conductive layer174may be formed in the openings of the second patterned dielectric layer172to be in physical and electrical contact with the TIVs160and the die connectors134of the electronic die ED. Materials of the second patterned dielectric layer172and the second patterned conductive layer174may be similar to those of the first patterned dielectric layer152and the first patterned conductive layer154, respectively. The details thereof are not repeated for the sake of brevity.

For example, the electronic die ED is in electrical communication with the photonic die PD through the second redistribution structure170, the TIVs160, and the first redistribution structure150. In this manner, optimal integration including high-speed and low power operation may be achieved. In some embodiments, the second patterned conductive layer174includes under bump metallization (UBM) patterns at least partially exposed by the second patterned dielectric layer172for further electrical connection. In some embodiments, a plurality of conductive terminals180are formed on the second patterned conductive layer174(e.g., UBM patterns). The conductive terminals180may be or may include ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, or the like.

Continue toFIGS.1A-1C, in some embodiments, the package assembly10further includes a second package component300, and the first package component100A may be mounted on and electrically coupled to the second package component300. The second package component300may be or may include a package substrate, a printed circuit board (PCB), a printed wiring board, an interposer, and/or other circuit carrier that is capable of carrying integrated circuits. In some embodiments, the conductive terminals180of the first package component100A are disposed on the top surface300aof the second package component300, and a plurality of external terminals310are distributed on the bottom surface300bof the second package component300for further electrical connection. In some embodiments, the size and the spacing of the external terminals310are greater than those of the conductive terminals180of the first package component100A. In some other embodiments, the external terminals310are omitted. For example, the package assembly10is mounted on a mother board through the external terminals310. Other applications of the package assembly10may be possible.

In some embodiments, the optical signal port200A coupled to the first package component100A is disposed on the top surface300aof the second package component300. For example, the optical interface layer220bonding the fiber210to first package component100A covers a portion of the top surface300aof the second package component300. In some embodiments, the fibers210are arranged to lean against the fiber mesa230, and the fibers210and the second package component300are spatially apart from one other via the fiber mesa230. In alternative embodiments, the fiber mesa230is omitted.

FIG.2Ais a schematic top view of a package assembly in accordance with some embodiments, andFIGS.2B and2Care schematic cross-sectional views respectively taken along an A-A′ line and a B-B′ line illustrated inFIG.2Ain accordance with some embodiments. Referring toFIGS.2A-2C, a package assembly20including a first package component100B and the optical signal port200A optically coupled to the first package component100B. The second package component300is optionally disposed beneath the first package component100B and the optical signal port200A. The second package component300may be electrically coupled to the first package component100B. The package assembly20described with reference toFIGS.2A-2Cmay be similar to the package assembly10described with reference toFIGS.1A-1C. Only the differences therebetween will be discussed, the like or the same part will not be repeated again, and the like numeral references indicate the like elements.

For example, the difference between the package assembly20and the package assembly10lies in the first package component100B. In some embodiments, the first package component100B includes the photonic die PD and the electronic die ED′ stacked upon one another in a face-to-face manner. For example, the top surface131aof the substrate131(which is the active surface of the electronic die ED′) and the top surface111aof the substrate111(which is the active surface of the photonic die PD) may face each other, and such configuration may be referred to as a face-to-face configuration. In this manner, a short electrical signal path between the photonic die PD and the electronic die ED′ is achieved, thereby minimizing a noise between operations and improving signal performance.

In some embodiments, the first redistribution structure150′ interposed between the electronic die ED′ and the photonic die PD is formed as a multi-layer structure including a plurality of first patterned dielectric layers152and a plurality of first patterned conductive layers154alternately stacked. The numbers of layers of the first redistribution structure150′ may be adjusted depending on the circuit design. In some embodiments, the first redistribution structure150′ is referred to as a die-to-die interconnection. In some embodiments, the electrical signals the electronic die ED′ may be transmitted to/from the second package component300through the first redistribution structure150′, the TIVs160, the second redistribution structure170, and the conductive terminals180. In some embodiments, the power introduced from the second package component300to the electronic die ED′ may be provided through the conductive terminals180, the second redistribution structure170, the TIVs160, and the first redistribution structure150′.

In some embodiments, the die connectors134′ of the electronic die ED′ are coupled to the first patterned conductive layer154through a plurality of conductive joints136. The conductive joints136may be or may include micro-bumps. In some embodiments, the conductive joints136include solder material, and the respective die connector134and the first patterned conductive layer154include metal pads for soldering. In some embodiments, an underfill layer137is interposed between the protection layer135and the first patterned dielectric layer152to laterally cover the connection (e.g., the conductive joints136and the first patterned conductive layer154connected to the conductive joints136). Alternatively, the underfill layer137is omitted and the second insulating encapsulation140′ fills the gap between the protection layer135of the electronic die ED′ and the first patterned dielectric layer152to laterally cover the connection of the electronic die ED′ and the first redistribution structure150′. In some other embodiments, the conductive joints136are omitted, and the electronic die ED′ may be coupled to the first redistribution structure150′ using other suitable bonding techniques (e.g., direct surface bonding, metal-to-metal bonding, hybrid bonding, etc.).

Continue toFIG.2B, in some embodiments, the thickness140tof the second insulating encapsulation140′ is greater than the thickness EDt of the electronic die ED′. Each of the TIVs160passing through the second insulating encapsulation140′ may have the thickness160tgreater than the thickness EDt of the electronic die ED′. For example, the second insulating encapsulation140′ covers the sidewalls EDs of the electronic die ED′ and extends to cover the bottom surface131bof the substrate131. In some other embodiments, the bottom surface131bof the substrate131is substantially leveled with the surfaces of the second insulating encapsulation140′ and the TIVs160. For example, the thickness EDt of the electronic die ED′ is substantially equal to the thickness140tof the second insulating encapsulation140′ and the thicknesses160tof the TIVs160.

FIG.3Ais a schematic top view of a package assembly in accordance with some embodiments, andFIGS.3B and3Care schematic cross-sectional views respectively taken along an A-A′ line and a B-B′ line illustrated inFIG.3Ain accordance with some embodiments. Referring toFIGS.3A-3C, a package assembly30including the first package component100A and the optical signal port200B optically coupled to the first package component100A. The second package component300electrically coupled to the first package component100A is optionally disposed beneath the first package component100A and the optical signal port200B. The package assembly30described with reference toFIGS.3A-3Cmay be similar to the package assembly10described inFIGS.1A-1C. Only the differences therebetween will be discussed, the like or the same part will not be repeated again, and the like numeral references indicate the like elements.

For example, the difference between the package assembly20and the package assembly10lies in the optical signal port200B. In some embodiments, the optical interface layer220′ of the optical signal port200B covers the outer sidewall100sof the first package component100A and further extends into a gap G between the first package component100A and the second package component300. For example, a portion of the optical interface layer220′ is interposed between the top surface300aof the second package component300and the second redistribution structure170of the first package component100A. The portion of the optical interface layer220′ may at least laterally cover the conductive terminals180of the first package component100A. In some embodiments, the portion of the optical interface layer220′ serves as an underfill layer for improving the adhesion between the first package component100A and the second package component300. The portion of the optical interface layer220′ may be formed by a capillary flow process or may be formed by a suitable deposition method before the first package component100A is attached to the second package component300.

In some embodiments, the portion of the optical interface layer220′ may merely fill portions of the gap G, and another underfill layer (not shown) fills the remaining portions of the gap G. In some embodiments, the portion of the optical interface layer220′ filling the gap G may be replaced by another underfill layer (not shown).

In some embodiments, as shown in the top view ofFIG.3A, the area of the optical interface layer220′ covering the top surface300aof the second package component300is greater than the footprint area occupied by the first package component100A on the top surface300aof the second package component300. Alternatively, the area of the optical interface layer220′ covering the top surface300aof the second package component300is substantially equal to or less than the footprint area occupied by the first package component100A on the top surface300aof the second package component300. The area of the optical interface layer220′ covering the top surface300amay be adjusted by the dispensed amount of the optical interface layer220′. The disclosure is not limited thereto.

FIG.4Ais a schematic top view of a package assembly in accordance with some embodiments, andFIG.4Bis schematic cross-sectional view taken along an A-A′ line illustrated inFIG.4Ain accordance with some embodiments. Unless specified otherwise, the materials of the elements in the embodiments herein are essentially the same as the like elements, which are denoted by like reference numerals in the embodiments shown inFIGS.1A-3C. The details regarding the materials of the elements hereinafter may be found in the discussion of the embodiments shown inFIGS.1A-3C.

Referring toFIGS.4A-4B, a package assembly40is provided. For example, the package assembly40includes a switch, a hub, a bridge, a router, a communication system, a data center, a network, and/or a computer system (e.g., a multiple-core processor computer system). The package assembly40may be a part of an electronic system for such as computers (e.g., high-performance computer), computational devices used in conjunction with an artificial intelligence system, wireless communication devices, computer-related peripherals, and entertainment devices, etc. The package assembly discussed herein may provide broad bandwidth and dense optical signal I/O communication in accordance with some embodiments. It should be noted that other electronic applications are also possible.

Continue toFIGS.4A-4B, the package assembly40includes a main package component400A, a plurality of first package components100A surrounding the main package component400A, and a plurality of optical signal ports200A optically coupled to the first package components100A. In some embodiments, the package assembly40further includes a second package component300′ electrically coupling the main package component400A to the first package components100A. In some embodiments, each of the first package components100A is electrically coupled to the main package component400A through a plurality of electrical links320of the second package component300′. It is noted that the electrical links320are shown in phantom inFIG.4Ato indicate that they are embedded and may not be seen from the top surface300aof the second package component300′.

In some embodiments, a portion of the first package components100A is disposed side by side along one edge of the second package component300′. For example, the portion of the first package components100A is spatially separated from one another in the top view. In some embodiments, each of the first package components100A is separated from the main package component400A by a lateral distance. For example, the lateral distance is non-zero. It is noted that the lateral distance may depend on product requirements and may construe no limitation in the disclosure. In some embodiments, the first package components100A and the optical signal ports200A are similar to the first package component100A and the optical signal ports200A described inFIGS.1A-1C. In some embodiments, the first package components100A of the package assembly40are partially or entirely replaced with the first package component100B described inFIGS.2A-2C. In some embodiments, the optical signal ports200A of the package assembly40may be partially or entirely replaced with the optical signal ports200B described inFIGS.3A-3C. It is understood that the first package component and the optical signal port illustrated herein are examples, and variations thereof may be carried out while still remaining within the scope of the claims and disclosure.

In some embodiments, IC packaging techniques, such as integrated fanout (InFO) packaging techniques, are used to fabricate the main package component400A. Other packaging techniques may be used to form the main package component400A. For example, the main package component400A includes at least one semiconductor die SD, a main insulating encapsulation420extending along the sidewalls SDs of the semiconductor die SD to laterally cover the semiconductor die SD, a main redistribution structure430disposed on the semiconductor die SD and the main insulating encapsulation420, a plurality of conductive terminals440disposed on the main redistribution structure430opposite to the semiconductor die SD. For example, the semiconductor die SD is electrically coupled to the conductive terminals440through the main redistribution structure430. In some embodiments, a protection layer450is disposed on the semiconductor die SD and the main insulating encapsulation420that are opposite to the main redistribution structure430. In some embodiments, the semiconductor die SD is attached to the protection layer450through the die attach film DAF. Alternatively, the protection layer450and/or the die attach film DAF may be omitted. In some embodiments, a plurality of main TIVs460(shown inFIG.4A) is formed aside the semiconductor dies SD to be electrically connected to the main redistribution structure430. In some embodiments, the main TIVs460may penetrate through the main insulating encapsulation420to provide vertically electrical path. Other circuitry may be used as appropriate for a given application. The above examples are provided for illustrative purposes only, and other embodiments may utilize fewer or additional elements.

In some embodiments, a plurality of semiconductor dies SD is arranged in an array and the main insulating encapsulation420may encapsulate the semiconductor dies SD. Although nine semiconductor dies SD are shown in the top view ofFIG.4A, it is noted that the number, the shape and the size of the semiconductor dies SD construe no limitation in the disclosure. In some other embodiments, a single semiconductor die SD is included in the main package component400A. It is appreciated that the semiconductor dies SD are illustrated in phantom inFIG.4Ato indicate that they may be covered. In some embodiments, the semiconductor dies SD include routers, switches, and/or processor cores for processing electrical signals. For example, electrical signals generated in the semiconductor dies SD may be used to drive the first package components100A. In some embodiments, the semiconductor dies SD may be or may include logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), microcontroller, etc.), application-specific integrated circuit (ASIC) dies, memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing die), the like, or a combination thereof. For example, the main package component400A with the semiconductor dies SD may include a processing subsystem (with one or more processor dies) and a memory subsystem (with memory dies). In some embodiments, the main package component400A includes one or more program modules or sets of instructions stored in the memory subsystem, which may be executed by processing subsystem during operation.

Continue toFIG.4B, for example, each of the semiconductor dies SD includes a substrate411having a top surface411aand a bottom surface411b, a plurality of conductive pads412distributed over the top surface411a, a passivation layer413formed over the top surface411aand partially covering the conductive pads412, a plurality of die connectors414formed on the conductive pads412, and a protection layer415formed on the passivation layer413and at least laterally covering the die connectors414. In some embodiments, the substrate411includes a plurality of active/passive devices (not shown) formed thereon to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, I/O circuitry, or the like. Materials of the substrate411, the conductive pads412, the passivation layer413, the die connectors414, and the protection layer415may be respectively similar to the materials of the substrate131, the conductive pads132, the passivation layer133, the die connectors134, and the protection layer135of the electronic die ED described inFIGS.1B-1C, and the detailed descriptions are omitted for the sake of brevity. A material of the main insulating encapsulation420may be similar to the material of the first insulating encapsulation120(or the second insulating encapsulation140), and the detailed descriptions are also omitted. In some embodiments, the main redistribution structure430includes a plurality of patterned dielectric layers432and a plurality of patterned conductive layers434alternately stacked. The main redistribution structure430and the conductive terminals440formed on the main redistribution structure430may be similar to the second redistribution structure170and the conductive terminals180described inFIGS.1B-1C, and the detailed descriptions are also omitted.

In some embodiments, the main package component400A and the first package components100A are mounted on the top surface300a′ of the second package component300′ through the conductive terminals180and440, respectively. The second package component300′ may be or may include a printed circuit board (PCB), a printed wiring board, a package substrate, an interposer, and/or other circuit carrier that is capable of carrying integrated circuits. In some embodiments, the conductive terminals180of each of the first package components100A are disposed on the peripheral region of the top surface300a′ of the second package component300′, and the conductive terminals440of the main package component400A are disposed on the central region of the top surface300a′ of the second package component300′. For example, the respective first package component100A has one edge optically coupled to the corresponding optical signal port200A and an opposing edge facing the main package component400A. This configuration enables broad bandwidth and a greater number of optical signal I/O.

FIG.5Ais a schematic top view of a package assembly in accordance with some embodiments, andFIG.5Bis schematic cross-sectional view taken along an A-A′ line illustrated inFIG.5Ain accordance with some embodiments. Referring toFIGS.5A-5B, a package assembly50is provided. For example, the package assembly50described herein may be similar to the package assembly40described with reference toFIGS.4A-4B. The like or the same part will not be repeated again, and the like numeral references indicate the like elements.

In some embodiments, the package assembly50includes an integrated package component500A and the optical signal ports200A optically coupled to the integrated package component500A. The optical signal I/O (e.g., the optical signal ports200A) may be connected along the edges of the integrated package component500A. In some embodiments, the integrated package component500A and the optical signal ports200A are disposed on the second package component300, and the integrated package component500A is electrically coupled to the second package component300through the conductive terminals180. The optical signal ports200A of the package assembly50may be partially or entirely replaced with the optical signal ports200B described inFIGS.3A-3C. The integrated package component500A may be formed in a corner-truncated shape in the top view. In some embodiments, the integrated package component500A is fabricated in a wafer form, in a package form, or the like.

In some embodiments, the integrated package component500A includes at least one semiconductor die SD, and at least one electronic die ED disposed next to the semiconductor die SD, at least one photonic die PD stacked over the semiconductor die SD and the electronic die ED. In some embodiments, the photonic die PD is staggered with respect to the semiconductor die SD. For example, the footprint area occupied by the electronic die ED entirely overlaps the footprint area occupied by the photonic die PD in the top view. The footprint area occupied by the semiconductor die SD may partially overlap the footprint area occupied by the photonic die PD in the top view.

In some embodiments, a plurality of semiconductor dies SD are arranged in an array, and a plurality of electronic dies ED are arranged surrounding the array of the semiconductor dies SD. In some embodiments, the semiconductor dies SD are distributed over the central region of the top surface300aof the second package component300, and the electronic dies ED are distributed over the peripheral region of the top surface300aof the second package component300. In some embodiments, nine semiconductor dies SD are arranged in a 3×3 array as shown inFIG.5A, and eight electronic dies ED surround the array of semiconductor dies SD, where the semiconductor die SD located in the middle is not adjacent to any electronic die. A plurality of photonic dies PD may be stacked over the array of semiconductor dies SD, except the semiconductor die SD located in the middle. In some embodiments, the electronic dies ED of the package assembly50may be partially or entirely replaced with the electronic dies ED′ described inFIGS.2B-2C. The electronic die and the photonic die of the package assembly50may be arranged in a face-to-back manner or a face-to-face manner which depends on the product requirements. It is appreciated that the configuration shown inFIG.5Ais merely an example, and the number, the size, and the location of the semiconductor die SD, the photonic die PD, and the electronic die ED may be modified depending on the product requirements.

In some embodiments, the integrated package component500A includes the first insulating encapsulation120partially covering the photonic dies PD, the second insulating encapsulation140extending along the sidewalls EDs of the electronic dies ED and the sidewalls SDs of the semiconductor dies SD, the first redistribution structure150interposed between the first insulating encapsulation120and the second insulating encapsulation140, the second redistribution structure170disposed on the second insulating encapsulation140opposite to the first redistribution structure150, the TIVs160penetrating through the second insulating encapsulation140to be in contact with the first redistribution structure150and the second redistribution structure170, and a plurality of the conductive terminals180disposed on the second redistribution structure170to be connected to the second package component300. The integrated package component500A optionally includes the protection layer125covering the photonic dies PD and the first insulating encapsulation120. In some embodiments, the semiconductor die SD is separated from the adjacent electronic die ED by a first lateral distance, and adjacent semiconductor dies SD are separated from one another by a second lateral distance. The first lateral distance and the second lateral distance are non-zero, and the second insulating encapsulation140may be interposed among the adjacent semiconductor dies SD and the electronic die ED. It is noted that the first lateral distance and the second lateral distance construe no limitation in the disclosure and may be modified according to the product requirements.

The electronic die ED and the corresponding photonic die PD are electrically connected through the first redistribution structure150, the TIVs160, and the second redistribution structure170. In some embodiments, the electronic dies ED and the semiconductor dies SD are electrically connected through the second redistribution structure170. In some embodiments, the semiconductor dies SD are in electrical communication with one another through the second redistribution structure170. In some embodiments, the conductive path for communicating among the photonic die PD, the corresponding electronic die ED, and the corresponding semiconductor die SD is arranged on the peripheral region of the second redistribution structure170. The conductive path for communicating the semiconductor dies SD may be arranged on the central region of the second redistribution structure170. For example, the conductive path for communicating among the photonic die PD, the corresponding electronic die ED, and the corresponding semiconductor die SD may be referred to as the external link, while the conductive path for communicating the semiconductor dies SD may be referred to as the internal link. Other routing layout of the second redistribution structure170may be possible. In some embodiments, the use of the second redistribution structure170to connect the semiconductor dies SD and the electronic dies ED minimizes the footprint area of the integrated package component500A and also achieves high electrical performance.

FIG.6Ais a schematic top view of a package assembly in accordance with some embodiments, andFIG.6Bis schematic cross-sectional view taken along an A-A′ line illustrated inFIG.6Ain accordance with some embodiments. Referring toFIGS.6A-6B, a package assembly60described herein may be similar to the package assembly50described with reference toFIGS.5A-5B. Only the differences therebetween will be discussed, the like or the same part will not be repeated again, and the like numeral references indicate the like elements.

For example, the difference of the package assemblies50and60lies in an integrated package component500B. In some embodiments, the integrated package component500B includes a single semiconductor die SD′ surrounded by the electronic dies ED and laterally encapsulated by the second insulating encapsulation140. In some embodiments, as shown in the top view ofFIG.6A, the footprint area occupied by the semiconductor die SD′ partially overlaps the footprint area occupied by the respective photonic die PD, while the footprint area occupied by the respective electronic die ED fully overlaps the footprint area occupied by the photonic die PD. It is noted that other configuration is possible. In some embodiments, the integration of the electronic dies ED with the semiconductor die SD′ (e.g., switch ASIC) may reduce the distance between the serializer/deserializer (SERDES) and the switch logic, which in turn may reduce the size and the power consumption of the SERDES. In some embodiments, the semiconductor die SD′ may perform one or more functions including memory structures, processing structures, sensors, amplifiers, power distribution, I/O circuitry, or the like.

FIG.7Ais a schematic top view of a package assembly in accordance with some embodiments, andFIG.7Bis schematic cross-sectional view taken along an A-A′ line illustrated inFIG.7Ain accordance with some embodiments. Referring toFIGS.7A-7B, a package assembly70described herein may be similar to the package assembly40described with reference toFIGS.4A-4B. Only the differences therebetween will be discussed, the like or the same part will not be repeated again, and the like numeral references indicate the like elements.

For example, the package assembly70includes at least one semiconductor die SD, at least one electronic die ED, and at least one photonic die PD disposed side by side. By such configuration, the footprint area occupied by the semiconductor die SD, the footprint area occupied by the electronic die ED, and the footprint area occupied by the photonic die PD may not overlap one another in the top view. In some embodiments, a plurality of semiconductor dies SD are arranged in an array, a plurality of electronic dies ED are arranged to surround the array of the semiconductor dies SD, and a plurality of photonic dies PD are arranged aside the electronic dies ED opposite to the array of the semiconductor dies SD. The optical signal I/O (e.g., the optical signal ports200A) may be optically coupled to the photonic dies PD that are arranged along the edges of the integrated package component500C. The optical signal ports200A of the package assembly50may be partially or entirely replaced with the optical signal ports200B described inFIGS.3A-3C.

In some embodiments, the integrated package component500C is fabricated in a wafer form, in a package form, or the like. For example, the integrated package component500C is formed in a corner-truncated shape in the top view. For example, the second insulating encapsulation140extending along the sidewalls EDs of the electronic dies ED and the sidewalls SDs of the semiconductor dies SD. The second insulating encapsulation140may spatially separate the respective semiconductor die SD, the respective electronic die ED, and the respective photonic die PD. In some embodiments, at least one sidewall PDs′ of the respective photonic die PD is exposed by the second insulating encapsulation140but covers by the corresponding optical signal port200A.

In some embodiments, the second redistribution structure170is connected to the photonic dies PD, the electronic dies ED, and the semiconductor dies SD. For example, the conductive path for communicating the semiconductor dies SD may be arranged on the central region of the second redistribution structure170. The conductive path for communicating between the photonic die PD and the corresponding electronic die may be arranged on the peripheral region of the second redistribution structure170. Other routing layout of the second redistribution structure170may be possible. In some embodiments, the die connectors114of each of the photonic dies PD are in physical and electrical contact with the second redistribution structure170. In some embodiments, the photonic dies PD, the electronic dies ED, and the semiconductor dies SD may face down, e.g., the die connectors of each die face toward the second package component300. In some embodiments, the second redistribution structure170is electrically coupled to the second package component300through the conductive terminals180. The protection layer125is optionally disposed over the photonic dies PD, the electronic dies ED, and the semiconductor dies SD. In some embodiments, the photonic dies PD, the electronic dies ED, and the semiconductor dies SD are attached to the protection layer125through the die attach films DAF. Alternatively, the protection layer125is omitted, and the back surfaces of the photonic dies PD, the electronic dies ED, and the semiconductor dies SD may be or may not be exposed.

FIGS.8A-8Fare partially cross-sectional views of various stages of manufacturing a photonic die in accordance with some embodiments. It is appreciated that some elements of the photonic die is omitted for ease of description. The manufacturing method shown inFIGS.8A-8Fmay be used to form the photonic die PD described above. In other words, the photonic die PD described in the disclosure may have the resulting structure shown inFIG.8F. The like or the same part will not be repeated again, and the like numeral references indicate the like elements.

Referring toFIG.8A, the substrate111is provided. For example, the substrate111is a semiconductor-on-insulator (SOI) substrate. In some embodiments, the substrate111includes an edge coupler1111formed on an insulator layer1112. The insulator layer1112may be or may include a buried oxide (BOX) layer, a silicon oxide layer, or the like. In some embodiments, the insulator layer1112is provided on a semiconductor material layer1113. For example, the semiconductor material includes silicon, germanium, a compound semiconductor (e.g., silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, etc.), an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP), a combination thereof, or the like. In some embodiments, the edge coupler1111is made of the semiconductor material. In some embodiments, the semiconductor material layer1113is a silicon substrate or a glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used.

In some embodiments, a dielectric layer1114is formed over the insulator layer1112to cover the edge coupler1111. The dielectric layer1114may be formed of silicon oxide, silicon nitride, a combination thereof, or the like, and may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), a spin-on-dielectric process, the like, or a combination thereof. In some embodiments, the dielectric layer1114, the edge coupler1111, and the insulator layer1112are located at the same level of the interconnect structure (not shown) of the photonic die PD. For example, the passivation layer113(shown inFIGS.1B-1C) is formed over the dielectric layer1114. The interconnect structure may include metal lines and vias for electrically interconnecting some devices on the semiconductor material layer1113and the conductive pads112. For example, the edge coupler1111is formed next to the metal lines and vias of the interconnect structure. In some other embodiments, the interconnect structure (not shown) is formed over the edge coupler1111.

Referring toFIGS.8B-8C, a patterned photoresist layer PR1having an opening OP1is formed over the dielectric layer1114. In some embodiments, the patterned photoresist layer PR1is formed using lithography and etching, or other suitable techniques. For example, the patterned photoresist layer PR1is formed above the edge coupler1111, and the opening OP1of the patterned photoresist layer PR1may expose a first portion RM1of the dielectric layer1114. Next, a first removal step is performed to remove the first portion RM1of the dielectric layer1114corresponding to the opening OP1of the patterned photoresist layer PR1. In some embodiments, a portion of the insulator layer1112underlying the first portion RM1of the dielectric layer1114is also removed to expose the underlying semiconductor material layer1113. For example, one or more etching processes may be performed using the patterned photoresist layer PR1as an etching mask. The arrows illustrated inFIG.8Bmay be viewed as the etching direction. In some embodiments, the patterned photoresist layer PR1is removed from the dielectric layer1114after removing the first portion RM1of the dielectric layer1114and the underlying insulator layer1112. The patterned photoresist layer PR1is removed by, for example, etching, stripping, or other suitable method.

Referring toFIGS.8D-8E, a patterned photoresist layer PR2having the opening OP2is then formed over the dielectric layer1114. For example, the patterned photoresist layer PR2is formed above the edge coupler1111, and a second portion RM2of the dielectric layer1114and the exposed portion of the semiconductor material layer1113are revealed by the opening OP2of the patterned photoresist layer PR2. Next, a second removal step is performed to remove the second portion RM2of the dielectric layer1114and the exposed portion of the semiconductor material layer1113that are revealed by the opening OP2of the patterned photoresist layer PR2. In some embodiments, a portion of the insulator layer1112and a portion of the semiconductor material layer1113underlying the second portion RM2of the dielectric layer1114are also removed. For example, one or more etching processes may be performed using the patterned photoresist layer PR2as an etching mask. The arrows illustrated inFIG.8Dmay be viewed as the etching direction. After removing, the patterned photoresist layer PR2is removed by such as etching, stripping, or other suitable method.

Continue toFIG.8E, in some embodiments, after the second removal step, a recess RS is formed in the substrate111. For example, after etching, the inner sidewalls of the dielectric layer1114, the insulator layer1112, and the semiconductor material layer1113are substantially leveled. The inner sidewalls of the dielectric layer1114, the insulator layer1112, and the semiconductor material layer1113are collectively viewed as the inner sidewall111sof the substrate111. For example, the recess RS is defined by the inner sidewall111sand the exposed surface1113sof the semiconductor material layer1113. In some embodiments, the edge coupler1111is embedded in the dielectric layer1114and may not be revealed at the inner sidewall111s. In some embodiments, the edge coupler1111is in proximity to the inner sidewall111sfor further optically coupling. In other embodiments, the edge coupler1111is revealed at the inner sidewall111s.

Referring toFIG.8F, an optical interface layer1115is formed in the recess RS. In some embodiments, the optical interface layer1115filling into the recess RS includes index matching gel, epoxy, or other suitable material. The optical interface layer1115may have the same or similar material to the optical interface layer220of the optical signal port200A described inFIGS.1A-1C. In some embodiments, the process steps shown inFIGS.8A-8Fare at wafer level. For example, one or more recess RS may be formed at wafer level (when the photonic die is still in the respective wafer), and before the wafer is sawed apart into the photonic dies PD. In some embodiments, a singulation process may be performed to generate a plurality of photonic dies PD after forming the optical interface layer1115and other processes for forming elements (e.g., the conductive pads112, the passivation layer113, the die connectors114, and the protection layer115) over the substrate111. In some embodiments, the singulation process includes a sawing process, a laser process, an etching process, combinations thereof, or the like.

In some embodiments, the singulation process is performed along the scribe lines SL to cut through at least the optical interface layer1115and the underlying semiconductor material layer1113. In some other embodiments, the optical interface layer1115is not cut through during the singulation process of forming the photonic die PD, but may be cut through during the subsequent packaging process for forming the aforementioned package component. The resulting photonic die PD after singulation may have at least one edge formed by coterminous outer sidewalls of the optical interface layer1115and the semiconductor material layer1113. In some embodiments, a polishing process is performed on the coterminous outer sidewalls after separating the photonic dies PD from one another. In some embodiments, a polishing process is performed on the coterminous outer sidewalls before aligning the fiber210with the edge coupler1111. In some embodiment in which the optical interface layer1115is cut through to form the edge facet of the photonic die PD, the optical interface layer1115provides an index-matched interface at the edge of the photonic die PD for coupling the optical interface layer220of the optical signal port200A (or200B).

FIG.9is schematic cross-sectional view of a package assembly in accordance with some embodiments. It is noted that the package assembly10shown inFIG.9is the same as the package assembly10described inFIGS.1A-1C, and the details of the edge coupler in the photonic die PD is illustrated in the enlarged view. The like or the same part will not be repeated again, and the like numeral references indicate the like elements.

Referring toFIG.9, the photonic die PD of the package assembly10may be fabricated using the method described inFIGS.8A-8Fto have the edge coupler1111formed therein. In some embodiments, the edge coupler1111embedded in the dielectric layer1114is in proximity to the sidewall PDs′ of the photonic die PD. Although only one edge coupler1111is illustrated, the photonic die PD may include a plurality of edge couplers1111therein for dense optical coupling. For example, the sidewall PDs′ of the photonic die PD includes the coterminous outer sidewall of the optical interface layer1115and the semiconductor material layer1113. The optical interface layer220of the optical signal port200A may be in physical contact with the sidewall PDs′ of the photonic die PD including the coterminous outer sidewall of the optical interface layer1115and the semiconductor material layer1113. A portion of the sidewall PDs′ of the photonic die PD corresponding to the edge coupler1111may be viewed as the edge facet of the photonic die PD. In some embodiments, the laterally extending direction of the edge coupler1111may be parallel to the fiber axis AX. For example, the fibers210of the optical signal port200A are arranged horizontally and aligned with the edge coupler1111. In some embodiments in which the fiber210is a lensed fiber, a tip portion (not shown) of the lensed fiber may face the sidewall PDs′ of the photonic die PD and may be aligned with the edge coupler1111for optical connection. It is noted that the illustrate of the package assembly inFIG.9is an example, different variations of the package assembly discussed in the disclosure may include the edge coupler1111in the photonic die for optical coupling.

FIGS.10A-10Iare schematic cross-sectional views of various stages of manufacturing a package assembly in accordance with some embodiments. For example, the manufacturing method shown inFIGS.10A-10Iis the method for forming the package assembly60described inFIGS.6A-6B. The materials may be found in the discussion of the embodiments above, and hence are not repeated herein. In addition, the like or the same part will not be repeated again, and the like numeral references indicate the like elements.

Referring toFIG.10A, a plurality of photonic dies PD is disposed over a temporary carrier TC. The temporary carrier TC may be a glass carrier, a ceramic carrier, or the like. In some embodiments, the protection layer125is formed over the temporary carrier TC, and then the bottom surface111bof the photonic dies PD are attached to the protection layer125by, e.g., a pick-and-place process or other suitable method. In some embodiments, a release film (not shown) is interposed between the temporary carrier TC and the protection layer125. For example, the release film is formed of a polymer-based material (e.g., a light-to-heat-conversion (LTHC) material), which may be removed together with temporary carrier TC from the overlying structures that will be formed in subsequent steps.

Referring toFIG.10B, the first insulating encapsulation120is formed on the protection layer125to laterally cover the photonic dies PD. For example, the photonic dies PD are over-molded by an insulating material (not shown) using suitable molding process, and then the insulating material is thinned until at least a portion of the die connectors114of each photonic die PD is accessibly revealed. For example, the insulating material is thinned by chemical mechanical polishing (CMP), mechanical grinding, or the like. In some embodiments, after the first insulating encapsulation120is formed, the top surface120tof the first insulating encapsulation120is substantially leveled with the top surfaces of the photonic dies PD. For example, the top surface of the respective photonic die PD includes the top surfaces114tof the die connectors114and the top surface115tof the protection layer115.

Referring toFIG.10C, the first redistribution structure150is formed on the first insulating encapsulation120and the photonic dies PD. For example, the first patterned dielectric layer152is formed on the top surface120tof the first insulating encapsulation120and the top surfaces of the photonic dies PD, and the openings (not labeled) of the first patterned dielectric layer152may accessibly expose at least a portion of the die connectors114of each photonic die PD. In some embodiments, the first patterned dielectric layer152is formed by deposition, lithography, etching, and/or other suitable process. Next, the first patterned conductive layer154is formed in the openings of the first patterned dielectric layer152to be in physical and electrical contact with the die connectors114of each photonic die PD. For example, the first patterned conductive layer154is formed by depositing a seed layer into the openings, carrying out plating a conductive material on the seed layer, and then planarizing the conductive material to remove excess conductive material from the first patterned conductive layer154. Other suitable processes may be used to form the first patterned conductive layer154. It should be noted that only one layer of the first patterned dielectric layer152and only one layer of the first patterned conductive layer154illustrated herein is merely an example, the first redistribution structure150may be a multi-layer structure in accordance with some embodiments. The number of the first patterned dielectric layer152and the first patterned conductive layer154may change depending on the circuit design, and the number of these layers may construe no limitation in the disclosure.

Subsequently, the TIVs160are formed on the first redistribution structure150. For example, the TIVs160are in physical and electrical contact with the first patterned conductive layer154. In some embodiments, the TIVs160are formed during the same process of forming the first patterned conductive layer154. In other embodiments, the TIVs160are pre-formed and may be disposed on the first patterned conductive layer154.

Referring toFIG.10D, a plurality of electronic dies ED and the semiconductor die SD′ are disposed on the first redistribution structure150by, e.g., a pick-and-place process or other suitable methods. In some embodiments, the electronic dies ED and/or the semiconductor die SD′ may be attached to the first patterned dielectric layer152through the die attach film(s) DAF. In some embodiments, the semiconductor die SD′ may be replaced with the semiconductor die SD described inFIGS.5A-5B. In some embodiments, the semiconductor die SD′ is replaced with additional electronic die ED.

Referring toFIG.10E, the second insulating encapsulation140is formed on the first redistribution structure150to laterally cover the TIVs160, the electronic dies ED, and the semiconductor die SD′. The forming process of the second insulating encapsulation140may be similar to that of the first insulating encapsulation120, and the detailed descriptions are omitted for the sake of brevity. In some embodiments, the top surface140sof the second insulating encapsulation140and the top surfaces160sof the TIVs160are substantially leveled with the top surfaces of the electronic dies ED and the top surface of the semiconductor die SD′. For example, the top surface of the respective electronic die ED includes the top surfaces134tof the die connectors134and the top surface135tof the protection layer135. The top surface of the semiconductor die SD′ may include the top surfaces414tof the die connectors414and the top surface415tof the protection layer415.

Referring toFIG.10Fand also with reference toFIG.1E, the second redistribution structure170is formed on the second insulating encapsulation140, the TIVs160, the electronic dies ED, and the semiconductor die SD′. For example, the second redistribution structure170is a multi-layer structure including a plurality of second patterned dielectric layers172and a plurality of second patterned conductive layers174alternately stacked. In some embodiments, the bottommost one of the second patterned dielectric layers172is formed on the top surface140sof the second insulating encapsulation140and extends to partially cover the top surfaces160sof the TIVs160, the top surfaces of the electronic dies ED, and the top surfaces of the semiconductor die SD′. For example, the openings of the bottommost one of the second patterned dielectric layers172may accessibly reveal the TIVs160, the die connectors134of the electronic dies ED, and the die connectors414of the semiconductor die SD′. Next, the bottommost one of the second patterned conductive layers174is formed in the openings of the bottommost one of the second patterned dielectric layers172and on the top surface of the openings of the bottommost one of the second patterned dielectric layers172using suitable patterning and metallization techniques. The portions of the bottommost one of the second patterned conductive layers174formed in the openings of the bottommost one of the second patterned dielectric layers172may be in physical and electrical contact with the TIVs160, the die connectors134of the electronic dies ED, and the die connectors414of the semiconductor die SD′.

The aforementioned steps may be performed several times to form a multi-layer structure. In some embodiments, the topmost one of the second patterned conductive layer174may include UBM patterns for further electrical connection. It should be noted that the number of the second patterned dielectric layers172and the number of the second patterned conductive layers174may depend on the circuit design and may construe no limitation in the disclosure.

Referring toFIG.10G, the conductive terminals180are formed on the topmost one of the second patterned conductive layers174. For example, the conductive terminals180are formed by initially forming a layer of solder through, e.g., ball placement, evaporation, plating, printing, solder transfer, or the like. A reflow process may be performed on the layer of solder to reshape the material into the desired bump shapes. In some other embodiments, the conductive terminals180are metal pillars formed by sputtering, printing, plating, or the like. In some embodiments, after forming the conductive terminals180, the temporary carrier TC is removed from the protection layer125. In some embodiments in which the release film is interposed between the temporary carrier TC and the protection layer125, the temporary carrier TC is removed by projecting a UV light or a laser beam on the release film, so that release film decomposes under the heat of the UV light or the laser beam. Other removal techniques (e.g., etching, grinding, a combination thereof, etc.) may be used to remove the temporary carrier TC. In some other embodiments, the protection layer125is removed together with the temporary carrier TC in a cleaning process or a backside grinding process.

In some embodiments, after forming the conductive terminals180, a singulation process is performed along the scribe lines (not shown) to form the integrated package components500B. In some embodiments, the second redistribution structure170, the second insulating encapsulation140, the first redistribution structure150, the photonic die PD, and the protection layer125may be cut through during the singulation process. The resulting structure after singulation may have at least one edge formed by coterminous outer sidewalls of the second redistribution structure170, the second insulating encapsulation140, the first redistribution structure150, the photonic die PD, and the protection layer125. For example, after the singulation process, the sidewalls PDs′ of the photonic die PD is accessibly revealed for optical coupling. In some embodiments, a polishing process is performed on the sidewalls PDs′ of the photonic die PD to render a smooth edge facet for optical coupling. For example, since a surface roughness of the sidewalls PDs′ of the photonic die PD corresponding to the optical interface layer1115(shown inFIGS.8A-9) is reduced during the polishing process, the Fresnel loss may be decreased and a better optical coupling may be achieved.

Referring toFIGS.10H-10I, the integrated package component500B is then mounted on the second package component300. In some embodiments, a reflow process is performed to bond the conductive terminals180of the integrated package component500B to the second package component300. Other suitable mounting techniques may be used. Subsequently, the optical signal port200A is bonded to the integrated package component500B and the second package component300. For example, when mounting the optical signal port200A, the coupling between the fiber210and the integrated package component500B is optimized by aligning the fiber210with the edge coupler (not shown) in the photonic die PD. In some embodiments, when optimized coupling connection between the fiber210and the photonic die PD is reached, an optical adhesive material is dispensed therebetween and then cured to form the optical interface layer220. Other suitable aligning and bonding techniques may be used to couple the optical signal port200A. In some embodiments, the optical signal port200A is replaced with the optical signal port200B. For example, a sufficient amount of the optical adhesive material is dispensed to cover the gap between the fiber210and the sidewall of the integrated package component500B and further extended to fill the gap between the integrated package component500B and the second package component300.

It is noted that the aforementioned steps may be used to form the first package component including the photonic die PD and the electronic die ED arranged in a face-to-back manner described above, such as the first package component100A described inFIGS.1A-1C. It is also noted that the aforementioned steps may be used to form the integrated package component500A described inFIGS.5A-5B, where the single semiconductor die SD′ is replaced with the plurality of semiconductor dies SD. Variations thereof may be carried out while still remaining within the scope of the claims and disclosure.

FIGS.11A-11Iare schematic cross-sectional views of various stages of manufacturing a package assembly in accordance with some embodiments. For example, the manufacturing method shown inFIGS.11A-11Iis the method for forming the package assembly20described inFIGS.2A-2C. The process steps and the materials may be found in the discussion of the embodiments above, and hence are not repeated herein. In addition, the like or the same part will not be repeated again, and the like numeral references indicate the like elements.

Referring toFIG.11A, the photonic die PD is disposed over the temporary carrier TC. In some embodiments, the protection layer125is formed over the temporary carrier TC, and then the bottom surface111bof photonic dies PD are attached to the protection layer125. In some embodiments, the first insulating encapsulation120is formed on the protection layer125to laterally cover the photonic dies PD. The step shown inFIG.11Amay be similar to the step described inFIGS.10A-10B, so the detailed descriptions are omitted for the sake of brevity.

Referring toFIG.11B, the first redistribution structure150′ is formed on the photonic die PD. For example, the first redistribution structure150′ is a multi-layer structure including a plurality of first patterned dielectric layers152and a plurality of first patterned conductive layers154alternately stacked. In some embodiments, the bottommost one of the first patterned dielectric layers152is formed on the photonic die PD, where at least a portion of the die connectors114′ is accessibly revealed by the openings of the bottommost one of the first patterned dielectric layers152. Next, the bottommost one of the first patterned conductive layers154is formed in the openings of the bottommost one of the first patterned dielectric layers152and also formed on the top surface of the bottommost one of the first patterned dielectric layers152, where the portions of the bottommost one of the first patterned conductive layers154formed in the openings may be in physical and electrical contact with the die connectors114′ of the photonic die PD.

The aforementioned steps may be performed several times to form a multi-layer structure. It should be noted that the number of the first patterned dielectric layers152and the number of the first patterned conductive layers154may depend on the circuit design and may construe no limitation in the disclosure. In some embodiments, a portion of the topmost one of the first patterned conductive layers154is protruded from the topmost one of the first patterned dielectric layers152for further electrical connection. In some embodiments, after forming the first redistribution structure150′, the TIVs are formed on the topmost one of the first patterned conductive layers154of the first redistribution structure150′.

Referring toFIG.11C, the electronic dies ED′ are mounted on the first patterned conductive layers154of the first redistribution structure150′. In some embodiments, flip-chip packaging techniques may be employed such that the electronic dies ED′ and the photonic die are communicatively coupled to one another through the first redistribution structure150′. In some embodiments, the die connectors134′ of the respective electronic die ED′ are connected to the topmost one of the first patterned conductive layers154through a plurality of conductive joints136. In some embodiments, the underfill layer137may be formed between the gap of the respective electronic die ED′ and the first redistribution structure150′ to laterally cover the conductive joints136.

Referring toFIG.11D, the second insulating encapsulation140′ is formed on the first redistribution structure150′ to cover the electronic dies ED′ and the TIVs160. The forming process of the second insulating encapsulation140′ may be similar to that of the second insulating encapsulation140described inFIG.10E. In some embodiments, the electronic dies ED′ are over-molded by the second insulating encapsulation140′ while at least a portion of the top surfaces160sof the TIVs160is accessibly revealed by the second insulating encapsulation140for further electrical connection. In some other embodiments, the insulating material may be thinned to expose the bottom surfaces131bof the electronic dies ED and the top surfaces160sof the TIVs160.

Referring toFIGS.11E-11F, the second redistribution structure170is formed on the TIVs160and the second insulating encapsulation140′. The second redistribution structure170may be electrically coupled to the electronic dies ED through the TIVs160and the first redistribution structure150′. The conductive terminals180are subsequently formed on the second redistribution structure170. In some embodiments, after forming the conductive terminals180, the temporary carrier TC is de-bonded to reveal the protection layer125. The forming processes of the second redistribution structure170and the conductive terminals180and the de-bonding process may be similar to the processes described inFIGS.10F-10G, so the detailed descriptions are omitted for the sake of brevity.

Referring toFIG.11G, a singulation process is performed along the scribe lines SL shown inFIG.11Gto form a plurality of first package components100B. In some embodiments, a dicing tool (not shown) may cut off the second redistribution structure170, the second insulating encapsulation140′, the first redistribution structure150′, the photonic die PD, and the protection layer125during the singulation process. The resulting structure after singulation may have at least one edge formed by coterminous outer sidewalls of the second redistribution structure170, the second insulating encapsulation140′, the first redistribution structure150′, the photonic die PD, and the protection layer125. For example, after the singulation process, the sidewalls PDs′ of the photonic die PD is accessibly revealed for coupling. In some embodiments, a polishing process is performed on the sidewalls PDs′ of the photonic die PD to provide a better optical coupling. In other words, the sidewalls PDs′ of the photonic die PD is substantially leveled with a sidewall140s′ of the second insulating encapsulation140′.

Referring toFIGS.11H-11I, the first package component100B is then mounted on the second package component300. The mounting process may be similar to the process described inFIG.10H. Subsequently, the optical signal port200A is bonded to the first package component100B and the second package component300. The aligning and bonding techniques may be similar to the process described inFIG.10I. In some embodiments, the optical signal port200A is replaced with the optical signal port200B. The first package component100B with the electronic die ED′ and the photonic die PD arranged in a face-to-face manner may provide optimal integration with high-speed and low power operation. It is noted that in accordance with various embodiments discussed above, some of the components in the first package component have different variations.

According to some embodiments, a package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.

According to some alternative embodiments, a package assembly includes a first package component an optical signal port disposed aside the first package component. The first package component includes an electronic die encapsulated by a first insulating encapsulation, and a photonic die stacked over and electrically coupled to the electronic die. The photonic die is partially covered by a second insulating encapsulation, where a sidewall of the photonic die is substantially leveled with a sidewall of the first insulating encapsulation. The optical signal port faces the sidewall of the photonic die to optically coupling the photonic die.

According to some alternative embodiments, a manufacturing method of a package assembly includes at least the following steps. A first redistribution structure is formed to electrically couple an electronic die and a photonic die encapsulated by an insulating encapsulation. The first redistribution structure and the photonic die are cut through to form an outer sidewall of a package component. A fiber is aligned with the outer sidewall of the package component corresponding to the photonic die.