High quality active matrix-type display device

In an active matrix-type display device where scan bus lines (S.sub.i) and data bus lines (D.sub.j) are formed on different substrates, two kinds of scan bus lines (SP.sub.i, SN.sub.i) are provided. A first switching element (TFTN.sub.ij) is connected between a reference voltage supply line (V.sub.R) and a display electrode (E.sub.ij), and is controlled by a first scan bus line (SN.sub.i), and a second switching element (TFTP.sub.ij) is connected between the reference voltage supply bus line (V.sub.R) and the display electrode, and is controlled by a second scan bus line (SP.sub.i). The first switching element (TFTN.sub.ij) is turned ON by a positive or negative potential at the first scan bus line.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to an active matrix-type display device using 
an electro-optic material such as liquid crystal, and more particularly, 
to an active matrix-type display device without intersections between scan 
bus lines and data bus lines on the same substrate. 
2. Description of the Related Art 
An active matrix-type liquid crystal display device as well as a simple 
matrix-type liquid crystal display device is thin, and therefore, is often 
used in various display devices. In this active matrix-type liquid crystal 
display device, since individual pixel elements are independently driven, 
the contrast is not reduced based upon the reduction of the duty ratio, 
and the angle of visibility is not reduced, even when the display capacity 
is increased to increase the number of lines. Therefore, the active 
matrix-type liquid crystal display device can enable a color display in 
the same way as in a cathode ray tube (CRT), and is prevalent in flat 
display devices. 
In the active matrix-type liquid crystal display device, however, since one 
thin film transistor as a switching element is provided for each pixel, a 
complex manufacturing process is required, and equipment therefor is 
expensive. Also, the manufacturing yield is low. Thus, the active 
matrix-type liquid crystal display device is very expensive. Therefore, a 
panel formed by an active matrix-type liquid crystal display device has to 
be of a small size. 
Also, in order to improve the low manufacturing yield due to the complex 
configuration of the active matrix-type liquid crystal display device, 
there has been suggested a counter-matrix active matrix-type liquid 
crystal device in which scan bus lines and data bus lines are formed on 
different substrates, so that intersections of scan bus lines and data bus 
lines on the same substrate are not used (see: U.S. Pat. Nos. 4,694,287, 
4,717,244, 4,678,282). 
In any type of active matrix-type liquid crystal device, the liquid crystal 
voltage fluctuates due to the generation of a DC component therein, which 
reduces the quality of display. For example, flickers and residual images 
may be generated. Particularly, for a stationary image, a burning 
phenomenon may occur. Also, the life-time of active matrix-type liquid 
crystal devices may be shortened. 
SUMMARY OF THE INVENTION 
An object of the present invention is to improve the quality of display in 
an active matrix-type display device, particularly, such a as a 
counter-matrix type display device. 
According to the present invention, in an active matrix-type display device 
in which scan bus lines and data bus lines are formed on different 
substrates, two kinds of scan bus lines are provided. A first switching 
element, such as an N-channel type thin film transistor, is connected 
between a reference voltage supply line and a display electrode and is 
controlled by a first scan bus line and a second switching element such as 
a P-channel type thin film transistor, is connected between the reference 
voltage supply bus line and the display electrode and is controlled by a 
second scan bus line. The first switching element is turned ON by a 
positive or negative potential at the first scan bus line. 
Both of the first and second switching elements are operated to compensate 
for a DC component.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Before the description of embodiments of the present invention, prior art 
liquid crystal display devices will be explained with reference to FIGS. 1 
through 4. 
In FIG. 1, which illustrates a general liquid crystal display device 
including control portions, reference numeral 1 designates a liquid 
crystal panel having a plurality of scan bus lines S.sub.i (i=0, 1, 2, . . 
. ) and a plurality of data bus lines D.sub.j (j=0, 1, 2, . . . ) which 
are arranged in parallel with each other. The scan bus lines S.sub.i are 
scanned by two scan synchronization circuits 2 and 2', and the data bus 
lines D.sub.j are driven by two data bus drivers 4 and 4'. The scan 
synchronization circuit 2 (2') is formed by a shift register 21 for 
shifting a shift data SD.sub.1 (SD.sub.2) in accordance with a shift clock 
signal SCK.sub.1 (SCK.sub.2), and an analog switch 22 (22') which receives 
a rectangular wave signals SC.sub.OUT1 (SC.sub.OUT2) generated from a 
swith circuit 3(3'). The analog switches 22 (22') pass the rectangular 
wave signals SC.sub.OUT1 (SC.sub.OUT2) in accordance with the outputs of 
the shift register 21 (21' ). Two voltages V.sub.1 and V.sub.2 (V.sub.i ' 
and V.sub.2 ') are applied to the switch circuits 3 (3') for determining a 
maximum level and a minimum level of the output signal SC.sub.OUT1 
(SC.sub.OUT2). Also, the two switch circuits 3 and 3' are operated in 
synchronization with each other by receiving a common clock signal CK. 
Prior art liquid crystal display devices (panels) are explained with 
reference to FIGS. 2 and 3. 
As illustrated in an equivalent circuit in FIG. 2, scan bus lines S.sub.i, 
S.sub.i+1, S.sub.i+2, . . . and data bus lines D.sub.j, D.sub.j+1, . . . 
are perpendicularly formed on one of the two glass substrates (not shown) 
filled with a liquid crystal material therebetween, which substrates 
oppose each other. The scan bus lines S.sub.i, S.sub.i+1, S.sub.i+2, . . . 
are electrically isolated from the data bus lines D.sub.j, D.sub.j+1, . . 
. at their intersections. 
At one intersection of the scan bus line such as S.sub.i and the data bus 
line such as D.sub.j, a thin film transistor TFT.sub.ij is connected 
between the data bus line D.sub.j and a display electrode of a liquid 
crystal cell CL.sub.ij, and is controlled by a potential of the scan bus 
line S.sub.i. That is, the thin film transistor TFT.sub.ij has a drain D 
connected to the data bus line D.sub.j, a gate G connected to the scan bus 
line S.sub.i, and a source S connected to a display electrode E.sub.ij of 
a liquid crystal cell CL.sub.ij whose other electrode is grounded by the 
common electrode (not shown) on the other glass substrate (not shown). 
In the above-mentioned active matrix-type liquid crystal display device of 
FIG. 2, since the scan bus lines S.sub.i, S.sub.i+1, S.sub.i+2, . . . and 
the data bus lines D.sub.j, D.sub.j+1, . . . are formed and intersect on 
the same substrate, insulation defects or short-circuits may occur at the 
intersections, and also disconnections due to a stepwise configuration at 
the intersections may occur in the overlaying bus lines. Therefore, there 
is a limit on the thickness of the underlying bus lines and the thickness 
of the insulating layer between the overlying and underlying bus lines. As 
a result, it is not easy to reduce the resistance of the underlying bus 
lines and increase the thickness of the insulating layers. Thus, it is 
difficult to completely avoid short-circuits at the intersections. 
Therefore, as illustrated in FIGS. 3 and 4, there has been suggested a 
counter-matrix active liquid crystal display device in which the scan bus 
lines S.sub.i are formed on one glass substrate SUB.sub.1 and the data bus 
lines D.sub.j are formed on the other glass substrate SUB.sub.2 which 
opposes the first substrate SUB.sub.1. 
Note that FIG. 3 is an equivalent circuit diagram of a prior art counter 
matrix active liquid crystal display device, and FIG. 4 is its exploded, 
perspective view. 
That is, liquid crystal material is filled between the glass substrates 
SUB.sub.1 and SUB.sub.2. The striped data bus lines D.sub.j, D.sub.j+1, . 
. . are formed on the glass substrate SUB.sub.2, while the san bus lines 
S.sub.i, S.sub.i+1, . . . , the thin film transistors such as TFT.sub.ij, 
display electrodes such as E.sub.ij for forming liquid crystal cells such 
as CL.sub.ij, and reference voltage supplying bus lines V.sub.r (which are 
illustrated as the ground potential in FIG. 3), are formed on the glass 
substrate SUB.sub.1. 
Liquid crystal material is filled between the data bus lines D.sub.j, 
D.sub.j+1, . . . and the display electrodes E.sub.ij, . . . to form the 
liquid crystal cells CL.sub.ij, . . . For example, the liquid crystal cell 
CL.sub.ij is connected between the data bus line D.sub.j and the drain D 
of the thin film transistor TFT.sub.ij whose gate G is connected to the 
scan bus line S.sub.i. Also, the source S of the thin film transistor 
TFT.sub.ij is connected to the reference voltage supply bus line. 
In the above-mentioned configuration, of FIGS. 3 and 4, the data bus lines 
D.sub.j, D.sub.j+1, . . . and the scan bus lines S.sub.i, S.sub.i+1, . . . 
are orthogonal to each other and they sandwich the liquid crystal material 
therebetween, so it is unnecessary to form insulating layers for the 
intersections since the two kinds of bus lines are not formed on the same 
substrate. This makes the configuration simple. Also, since no 
short-circuit occurs between the data bus lines D.sub.j, D.sub.j+1, . . . 
and the scan bus lines S.sub.i, S.sub.i+1, . . . , defects of display are 
reduced thereby improving the manufacturing yield. 
A shift voltage .DELTA.V.sub.1c may be generated at the display electrode 
E.sub.ij in the active matrix-type liquid crystal display devices of FIG. 
2 and FIGS. 3 and 4. 
In the active matrix-type liquid crystal device of FIG. 2, if C.sub.8p is a 
parasitic electrostatic capacity between the scan bus line S.sub.i to 
which the gate G of the thin film transistor TFT.sub.ij is connected and 
the display electrode E.sub.ij ; 
C.sub.dp is a parasitic electrostatic capacity between the display 
electrode E.sub.ij and the data bus line D.sub.j, i.e., a parasitic 
electrostatic capacity between the source and drain D of the thin film 
transistor TFT.sub.ij ; 
C.sub.LC is an electrostatic capacity of the liquid crystal cell CL.sub.ij, 
then 
EQU .DELTA.V.sub.1c =.DELTA.V.sub.D C.sub.dp /(C.sub.gp +C.sub.dp +C.sub.LC) 
(1) 
where .DELTA.V.sub.D is a fluctuation of the potential at the data bus line 
D.sub.j, i.e., the amplitude thereof. 
Conversely, in the active matrix-type liquid crystal device of FIGS. 3 and 
4, 
EQU .DELTA.V.sub.1c =.DELTA.V.sub.D .multidot.(C.sub.gp +C.sub.cp)/(C.sub.gp 
+C.sub.dp +C.sub.LC) (2) 
where V.sub.dp is a parasitic electrostatic capacity between the display 
electrode E.sub.ij and the reference voltage supplying bus line (ground). 
Thus, when the data bus line D.sub.i uses a positive voltage and a negative 
voltage which are changed symmetrically for an odd frame and an even 
frame, the effective voltage applied to the liquid crystal cell CL.sub.ij 
is not symmetrical with respect to the positive voltage and the negative 
voltage, thus creating a DC component. In the liquid crystal voltage 
V.sub.1c. 
The above-mentioned DC component generates a flicker, i.e., a residual 
image in a stationary image, thus reducing the quality of display, and 
also reducing the life time of the active-type liquid crystal display 
device (panel). 
To cope with this, a bias voltage is applied to the common electrode 
(ground) of the liquid crystal cell C.sub.ij, for example, to make the 
effective voltage of the liquid crystal cell C.sub.ij symmetric for a 
positive frame and a negative frame, thus reducing the DC component. In 
this device, however, since the capacity C.sub.1c of the liquid crystal 
cell has a voltage dependency due to the anisotropy of dielectric 
characteristics of the liquid crystal cell C.sub.ij, the shift voltage 
.DELTA.V.sub.1c fluctuates in accordance with the display state of the 
liquid crystal cell CL.sub.ij, and as a result, there is a limit to the 
effective removal of the DC component by only applying a bias voltage to 
the common electrode. 
As another measure, there has been suggested an active-type liquid crystal 
panel where two complementary thin film transistors are used for one pixel 
electrode, and a scan signal having opposite polarities for every frame is 
applied to the gate electrodes of the thin film transistors thus making 
the effective voltage applied to the liquid crystal cell symmetrical (see: 
JP-A-No. 53-144297). 
Also, in this device, the shift voltage .DELTA.V.sub.1c is entirely 
canceled by the scan signal having opposite polarities which are changed 
for each frame, but, in each frame, the shift voltage .DELTA.V.sub.1c is 
still present. 
Further, in view of the above-mentioned formulae (1) and (2), the shift 
voltage .DELTA.V.sub.1c in the counter-matrix-type device of FIGS. 3 and 4 
is larger than the shift voltage .DELTA.V.sub.1c in the device of FIG. 2, 
due to the parasitic electrostatic capacity C.sub.gp. Thus, the 
counter-matrix type device has a problem in that crosstalk is large. That 
is, in the counter matrix-type device, when the thin film transistor 
TFT.sub.ij is turned OFF, the data voltage sequentially applied to the 
data bus line D.sub.j is applied to the liquid crystal cell C.sub.ij via 
the parallel electrostatic capacities C.sub.gp and C.sub.ap, and 
therefore, the other data voltage for other liquid crystal cells 
fluctuates the liquid crystal cell voltage V.sub.1c, thus reducing the 
quality of display. 
Also, in the conventional active matrix type liquid crystal display device 
of FIG. 2, it is possible to lessen the ratio .DELTA.V.sub.1c 
/.DELTA.V.sub.D by adding a storage capacity to the liquid crystal cell. 
Conversely, in the counter matrix type active liquid crystal display 
device of FIGS. 3 and 4, it is difficult to lessen the ratio 
.DELTA.V.sub.1c /.DELTA.V.sub.D, since it is difficult to add such as 
storage capacity to the liquid crystal cell. Further, due to the 
difficulty of addition of such a storage capacity, the level shift of a DC 
voltage immediately after the selection of the scan bus line S.sub.i 
connected to the gate G of the thin film transistor TFT.sub.ij causes a 
residual image phenomenon. Particularly, for a stationary image, a burning 
phenomenon occurs which reduces the quality of display. 
In FIG. 5, which is a first embodiment of the counter-matrix-type display 
device according to the present invention, a plurality of pairs of scan 
bus lines SN.sub.i, SP.sub.i ; SN.sub.i+1, SP.sub.i+1 ; . . . and a 
plurality of data bus lines D.sub.j, . . . are perpendicularly arranged 
with each other on different glass substrates having liquid crystal filled 
therebetween. Also, display (pixel) electrodes E.sub.ij, E.sub.i+1, . . . 
are arranged within pixel areas in a matrix partitioned by the scan bus 
lines SN.sub.i, SP.sub.i, . . . and the data bus lines D.sub.j, . . . 
Further, reference voltage supply lines, which are in this case grounded 
(GND) are arranged in parallel with the scan bus lines SN.sub.i, SP.sub.i, 
. . . 
Liquid crystal cells CL.sub.ij, . . . are formed by the display electrodes 
E.sub.ij with the liquid crystal material. 
In order to control each of the liquid crystal cells CL.sub.ij, two kinds 
of thin film transistors, i.e., an N-channel type thin film transistor TFT 
N.sub.ij and a P-channel type thin film transistor TFTP.sub.ij are 
provided for each liquid crystal cell CL.sub.ij. 
These can be formed by a semiconductor region made of amorphous silicon or 
polycrystalline silicon, and source/drain electrode portions which are, 
for example, P-type semiconductors obtained by doping impurities such as 
boron, or N-type semiconductors obtained by doping impurities such as 
phosphorus or arsenic. Also, when manufacturing thin film transistors, 
photo resist material, an oxidation film, and nitride film are used as 
masks, and boron and arsenic are doped individually by ion plantation or 
diffusion into the semiconductor regions for the source/drain portions, to 
form the two kinds of thin film transistors. 
There are two scan bus lines SN.sub.i and SP.sub.i for one scan line. The 
gate G of the N-channel thin film transistor TFTN.sub.ij is connected to 
the scan bus line SN.sub.i, and the gate G of the P-channel thin film 
transistor TFTP.sub.ij is connected to the scan bus line SP.sub.i. 
Also, the drains D of the thin film transistors TFTN.sub.ij and TFTP.sub.ij 
are connected to the display electrode E.sub.ij of the liquid crystal cell 
CL.sub.ij, and the sources S of the thin film transistors TFTN.sub.ij and 
TFTP.sub.ij are connected to the reference voltage supply line GND. 
The signals of the scan bus lines SN.sub.i and SP.sub.i, and the data bus 
line D.sub.j of FIG. 5 are shown in FIGS. 6A, 6B, and 6C. 
The signals of the scan bus lines SN.sub.i and SP.sub.i are pulse signals 
in synchronization having opposite polarities to each other, and their 
amplitudes are V.sub.GN and V.sub.GP, respectively. That is, the signal of 
the scan bus line SN.sub.i is a pulse signal having a voltage+V.sub.GN, 
and the signal of the scan bus line SP.sub.i is a pulse signal having a 
voltage-V.sub.GP. 
The signals of the scan bus lines SN.sub.i and SP.sub.i are delayed by 
using the shift registers 21 and 21' of the scan synchronization circuits 
2 and 2' of FIG. 1 for one horizontal scanning time period it, and are 
sequentially applied to the downstream side scan bus lines SN.sub.i+1, 
SP.sub.i+1, . . . , thus scanning all of the scan bus lines. 
That is, as shown in FIGS. 6A and 6B, the signals applied to the scan bus 
lines SN.sub.i and SP.sub.i are generated from time t.sub.0 to time 
t.sub.1, the signals applied to the scan bus lines SN.sub.i+1 and 
SP.sub.i+1 generated from time t.sub.1 to time t.sub.2, and so on. 
As shown in FIG. 6C, the signal of the data bus line D.sub.j having an 
amplitude V.sub.D is generated at the same or approximately same timing as 
that of signals of the scan bus lines SN.sub.i and SP.sub.i. However, the 
polarity of the signal of the data bus line D.sub.i is reversed for every 
frame. 
Also, the pulse-width of the signal of the data bus line D.sub.j is 
preferably broader than that of the signals of the scan bus lines SN.sub.i 
and SP.sub.i, but, the present invention is not limited to this. 
The thin film transistors TFTN.sub.i and TFTP.sub.i at each pixel are 
simultaneously turned ON by the signals of the scan bus lines SN.sub.i and 
SP.sub.i, and therefore, the data of the data bus line D.sub.j is written 
into the liquid crystal cell CL.sub.ij. 
At this time, the voltages +V.sub.GN and -V.sub.GP are determined so as to 
satisfy the following relationship: 
EQU (C.sub.gPN +C.sub.dPN).multidot.V.sub.GN =(C.sub.gPP 
+C.sub.dPP).multidot.V.sub.GP (3) 
where C.sub.gPN is a parasitic electrostatic capacity between the scan bus 
line SN.sub.i and the display electrode E.sub.ij ; 
C.sub.dPN is a parasitic electrostatic capacity between the gate-source of 
the N-channel type transistor TFTN.sub.i ; 
C.sub.gPP is a parasitic electrostatic capacity between the scan bus line 
SP.sub.i and the display electrode E.sub.ij ; and 
C.sub.dPP is a parasitic electrostatic capacity between the gate-source of 
the P-channel type transistor TFTP.sub.i. 
Therefore, the level shift voltage .DELTA.V.sub.1CN by the N-channel type 
thin film transistor TFTN.sub.ij is counteracted by the level shift 
voltage .DELTA.V.sub.eCN by the P-channel type thin film transistor 
TFTP.sub.ij in accordance with the above-mentioned formula (2). As a 
result, the total level shift voltage .DELTA.V.sub.1c becomes zero. 
Thus, the voltage .+-.V.sub.D written into the liquid crystal cell 
CL.sub.ij is maintained until the next scan signals are applied to the 
scan bus lines SN.sub.i and SP.sub.i. 
Thus, the generation of a DC component in the AC voltage applied to the 
liquid crystal cell C.sub.ij is avoided. 
The scan signals applied to the scan bus lines SN.sub.i and SP.sub.i of 
FIGS. 6A and 6B are generated by the synchronization circuits 2 and 2' and 
the switch circuit 3 and 3' of FIG. 1. That is, the switch circuit 3 
generates a signal S.sub.COUT1 as shown in FIG. 7A, and the switch circuit 
3' generates a signal SC.sub.OUT2 as shown in FIG. 7E. In this case, the 
voltages V.sub.1 and V.sub.2 of the switch circuit 3 are +V.sub.GN and 
-V.sub.GP, respectively, and the voltages V.sub.1 ' and V.sub.2 ' of the 
switch circuit 3' are also V.sub.GN and -V.sub.GP, respectively. Shift 
data SD.sub.1 as shown in FIG. 7C is supplied to the shift register 22, 
and shift data SD.sub.2 as shown in FIG. 7G is supplied to the shift 
register 22'. Such shift data SD.sub.1 and SD.sub.2 are shifted within the 
shift registers 22 and 22', respectively, in synchronization with shift 
clock signals SCK.sub.1 and SCK.sub.2 as shown in FIGS. 7B and 7F, 
respectively. As a result, the signals applied to the scan bus lines 
SN.sub.i and SP.sub.i are obtained as shown in FIGS. 7D and 7H, 
respectively. 
In FIG. 8, which is a second embodiment of the counter-matrix-type display 
device according to the present invention, only one scan bus line is 
provided for each line. That is, a scan bus line SP.sub.i-1 (SN.sub.i-2) 
is connected to the gate of the P-channel thin film transistor 
TFTP.sub.1-1 and to the gate of the N-channel thin film transistor 
TFTN.sub.i-2. Similarly, a scan bus line SP.sub.i (SN.sub.i-1) is 
connected to the gate of the P-channel thin film transistor TFTP.sub.i-1 
and to the gate of the N-channel thin film transistor TFTN.sub.i-1. 
In other words, the gate of the P-channel thin film transistor TFTP.sub.i 
connected to one display electrode E.sub.ij is connected to a scan bus 
line SP.sub.i (SN.sub.i-1), while the gate of the N-channel thin film 
transistor TFTN.sub.i connected to the same display electrode E.sub.ij is 
connected to a different scan bus line SP.sub.i+1 (SN.sub.i). 
The signals of the scan bus lines SP.sub.i-1 (SN.sub.i-2), SP.sub.i 
(SN.sub.i-1), and SP.sub.i +1 (SN.sub.i) are shown in FIGS. 9A, 9B, and 
9C, respectively. 
These signals are pulse signals having opposite polarities to each other, 
and their amplitudes are V.sub.GN and V.sub.GP, respectively. 
Also, each of the signals of the scan bus lines SP.sub.i-1 (SN.sub.i-2), 
SP.sub.i (SN.sub.i-1), SP.sub.i+1 (SN.sub.i), . . . are sequentially 
delayed by one horizontal scan time period H. A positive signal component 
of its previous scan bus such as SP.sub.i (SN.sub.i-1) is in 
synchronization with a positive signal component of its following scan bus 
line such as SP.sub.i+1 (SN.sub.i). Also, a negative signal component of 
one scan bus line such as SP.sub.i (SN.sub..sub.1-1) is in synchronization 
with a positive signal component of its following scan bus line such as 
SP.sub.i+1 (SN.sub.i). Therefore, for example, the N-channel thin film 
transistor TFTN.sub.ki-1, j is turned ON from time t.sub.D to time 
t.sub.1, and also, the P-channel thin film transistor TFTP.sub.ij is 
turned ON from time t.sub.0 to time t.sub.1. 
Thus, both the N-channel and P-channel thin film transistors such as 
TFTN.sub.ij and TFTP.sub.ij connected to one display electrode such as 
E.sub.ij, are simultaneously turned ON. Therefore, if the voltages 
+V.sub.GN and -V.sub.GP are determined so as to satisfy the 
above-mentioned formula (3), and the shift voltage .DELTA.V.sub.1c is 
zero, thereby avoiding the generation of a DC component in the AC voltage 
applied to the liquid crystal cell CL.sub.ij. 
Note that, for the liquid crystal cell CL.sub.ij (the display electrode 
E.sub.ij), the shift voltage .DELTA.V.sub.1c is not zero at time t.sub.2 
when both of the thin film transistors TFTN.sub.ij and TFTP.sub.ij are 
tuned OFF, however, this shift voltage .DELTA.V.sub.1c finally becomes 
zero at time t.sub.3. 
The signals of the scan bus lines SP.sub.i-1 (SN.sub.i-2) are delayed by 
using the shift registers 21 and 21' of the scan synchronization circuits 
2 and 2' of FIG. 1 and are sequentially applied to the downstream side 
scan bus lines SP.sub.i (SN.sub.i-l) SP.sub.i+1 (SN.sub.i), . . . , thus 
scanning all of the scan bus lines. 
The scan signals applied to the scan bus lines SP.sub.i-1 (SN.sub.i-2) and 
SP.sub.i (SN.sub.i-1) of FIGS. 9A and 9B are generated by the 
synchronization circuits 2 and 2' and the switch circuit 3 and 3'. That 
is, the switch circuit 3 generates a signal SC.sub.OUT1 as shown in FIG. 
10A, and the switch circuit 3' generates a signal SC.sub.OUT2 as shown in 
FIG. 10E. In this case, the voltages V.sub.1 and V.sub.2 of the switch 
circuit 3 are +V.sub.GN and -V.sub.GP, respectively, and the voltages 
V.sub.1 ' and V.sub.2 ' of the switch circuit 3' are also +V.sub.GN and 
-V.sub.GP, respectively. Shift data SD.sub.1 as shown in FIGS. 10C is 
supplied to the shift register 22, and shift data SD.sub.2 as shown in 
FIG. 10G is supplied to the shift register 22'. Such shift data SD, and 
SD.sub.2 are shifted within the shift registers 22 and 22', respectively, 
in synchronization with shift clock signals SCK.sub.1 and SCK.sub.2 as 
shown in FIGS. 10B and 10F, respectively. As a result, the signals applied 
to the scan bus lines SP.sub.i-1 (SN.sub.i-2) and SP.sub.i (SN.sub.i-1) 
are obtained as shown in FIGS. 10D and 10H, respectively. 
Also, according to the active-type liquid crystal display device of FIG. 8, 
since the number of scan bus lines is reduced by 1/2, areas occupied by 
the scan bus lines and the connections therefor are reduced, to simply the 
configuration of a substrate, a control circuit, and the like. 
In FIG. 11, which is a third embodiment of the counter-matrix-type display 
device according to the present invention, the active matrix-type liquid 
crystal display device of FIG. 5 is modified to reduce the number of scan 
bus lines. That is, the scan bus lines SP.sub.i and S N.sub.i are combined 
with the adjacent scan bus lines SN.sub.i-1 and SP.sub.i-1, respectively, 
the scan bus lines SP.sub.i-1 and SN.sub.i+1 are combined with the 
adjacent scan bus lines SN.sub.i and SP.sub.i, respectively, and so on. 
Therefore, pairs of scan bus lines such as SP.sub.i-1 (SN.sub.i) and 
SP.sub.i (SN.sub.i-1) are arranged for every two rows of the liquid 
crystal cells. 
The pair of the signals of the scan bus lines SP.sub.i-1 (SN.sub.i) and 
SP.sub.i (SN.sub.i-1) are in synchronization with each other as shown in 
FIGS. 12A and 12B, but their polarities are opposite. Also, the pair of 
the signals of the scan bus lines SP.sub.i+1 (SN.sub.i +2) and SP.sub.i+2 
(SN.sub.i+1) are in synchronization with each other as shown in FIGS. 12C 
and 12D, but their polarities are opposite. 
For example, from time t.sub.-1 to time t.sub.0, a negative portion of the 
signal of the scan bus line SP.sub.1-1 (SN.sub.i) corresponds to a 
positive portion of the signal of the scan bus line SP.sub.i (SN.sub.i-1), 
while from time t.sub.0 to time t.sub.1, a positive portion of the signal 
of the scan bus line SP.sub.i-1 (SN.sub.i) corresponds to a negative 
portion of the signal of the scan bus line SP.sub.i (SN.sub.i-1). As a 
result, from time t.sub.-1 to time t.sub.0, the P-channel thin film 
transistor TFTP.sub.ij and the N-channel thin film transistor TFTN.sub.ij 
are simultaneously turned ON, and from time t.sub.0 to time t.sub.1, the 
N-channel thin film transistor TFTN.sub.ij and the P-channel thin film 
transistor TFTP.sub.ij are simultaneously turned ON. 
Similarly, from time t.sub.1 to time t.sub.2, a negative portion of the 
signal of the scan bus line SP.sub.i+1 (SN.sub.i+2) corresponds to a 
positive portion of the signal of the scan bus line SP.sub.i+2 
(SN.sub.i+1), while from time t.sub.2 to time t.sub.3, a positive portion 
of the signal of the scan bus line SP.sub.i+1 (SN.sub.i+2) corresponds to 
a negative portion of the signal of the scan bus line SP.sub.i+1 
(SN.sub.i+2). As a result, from time t.sub.1 to time t.sub.2, the 
P-channel thin film transistor TFTP.sub.i+1, j and the N-channel thin film 
transistor TFTN.sub.i+1, j are simultaneously turned ON, and from time 
t.sub.2 to time t.sub.3, the N-channel thin film transistor TFTN.sub.i+2, 
j and the P-channel thin film transistor TFTP.sub.i+2, j are 
simultaneously turned ON. 
The pair of the signals of the scan bus lines SP.sub.1-1 (SN.sub.i) and 
SP.sub.i (SN.sub.i-1) are delayed for two horizontal scanning time periods 
2H to obtain the signals of the pair of the scan bus lines SP.sub.i+1 
(SN.sub.i+2) and SP.sub.+2 (SN.sub.i+1). 
The scan signals applied to the scan bus lines SP.sub.i-1 (SN.sub.i) and 
SP.sub.i (SN.sub.i-1) of FIGS. 12A and 12B are generated by the 
synchronization circuits 2 and 2' and the switch circuit 3 and 3'. That 
is, the switch circuit 3 generates a signal SC.sub.OUT1 as shown in FIG. 
13A, and the switch circuit 3' generates a signal SC.sub.OUT2 as shown in 
FIG. 13E. In this case, the voltages V.sub.1 and V.sub.2 of the switch 
circuit 3 are +V.sub.GN and -V.sub.GP, respectively, and the voltages 
V.sub.1 ' and V.sub.2 ' of the switch circuit 3' are also +V.sub.GN and 
-V.sub.GP, respectively. Shift data SD.sub.1 as shown in FIG. 13 is 
supplied to the shift register 22, and shift data SD.sub.2 as shown in 
FIG. 13G is supplied to the shift register 22'. Such shift data SD.sub.1 
and SD.sub.2 are shifted within the shift registers 22 and 22', 
respectively, in synchronization with shift clock signals SCK.sub.1 and 
SCK.sub.2 as shown in FIGS. 13B and 13F, respectively. As a result, the 
signals applied to the scan bus lines SP.sub.i-1 (SN.sub.i) and SP.sub.i 
(SN.sub.i-1) are obtained as shown in FIGS. 13D and 13H, respectively. 
Also, according to the active-type liquid crystal display device of FIG. 11 
since the number of scan bus lines is reduced by 1/2, areas occupied by 
the scan bus lines and the connections therefor are reduced, to simplify 
the configuration of a substrate, a control circuit, and the like. 
In FIG. 14, which is a fourth embodiment of the counter-matrix-type display 
device according to the present invention, only one scan line is provided 
for each row of the liquid crystal cells (i.e., the display electrodes). 
That is, the gates of the N-channel thin film transistors and the 
P-channel thin film transistors of the display electrodes belonging to one 
row are connected to one scan bus line such as S.sub.i. Also, there are 
two kinds of voltage supply lines +V.sub.R and -V.sub.R, which are 
arranged alternately for every row of the display electrodes such as 
E.sub.ij. The sources of the N-channel thin film transistors such as 
TFTN.sub.ij are connected to the positive voltage supply line +V.sub.R, 
while the sources of the P-channel thin film transistors TFTP.sub.ij are 
connected to the negative voltage supply line -V.sub.R. 
The operation of the active matrix-type liquid crystal device of FIG. 14 is 
explained with reference to FIGS. 15A through 15G. 
As shown in FIGS. 15A, 15B, and 15C, the signal of the scan bus line 
S.sub.i+1 is obtained by delaying the signal of the scan bus line S.sub.i 
for one horizontal scanning time period H, and the signal of the scan bus 
line S.sub.i+2 is obtained by delaying the signal of the scan bus line 
s.sub.i+1 for one horizontal scanning time period H. Also, the polarity of 
the signal of the scan bus line S.sub.i is opposite to that of the signal 
of the scan bus line S.sub.i+1, and the polarity of the signal of the scan 
bus line S.sup.i+1 is opposite to that of the signal of the scan bus line 
S.sub.i+2. Further, each of the signals of the scan bus lines S.sub.i, 
S.sub.i+1, S.sub.i+2, . . . are reversed for every frame. 
That is, in an odd frame, the signal of the scan bus line S.sub.i is pulse 
signal of a voltage +V.sub.GN from time t.sub.0 to time t.sub.1, and the 
signal of the scan bus line S.sub.i+1 is a pulse signal of a voltage 
-V.sub.GP from time t.sub.1 to time t.sub.2. 
Also, in an even-frame, the signal of the scan bus line S.sub.i is a pulse 
signal of a voltage -V.sub.GP from time to time t.sub.1, and the signal of 
the scan bus line S.sub.i+1 is a pulse signal of a voltage +V.sub.GN from 
time t.sub.1 to time t.sub.2 . 
As shown in FIG. 15D, the signal of the data line such as D.sub.j has an 
amplitude of V.sub.D, and the polarity thereof is reversed for each frame. 
As shown in FIG. 15E, the reference voltage supply lines +V.sub.R and 
-V.sub.R are always at a definite positive value and a definite negative 
value, respectively. 
First, in an odd frame, when the voltage of the scan bus line S.sub.i is 
+V.sub.GN, the N-channel thin film transistors such as TFTN.sub.ij 
connected to the scan bus line S.sub.i are turned ON. As a result, 
-V.sub.R, which also defines the voltage of the negative reference voltage 
supply line -V.sub.R, is applied as an electrode voltage V.sub.p as shown 
in FIG. 15F via the turned ON N-channel thin film transistor such as 
TFTN.sub.ij to the display electrode such as E.sub.ij. Therefore, a 
voltage V.sub.D +V.sub.R, which is a difference in potential between the 
display electrode E.sub.ij and the data bus signal D.sub.j, is applied as 
a write voltage (liquid crystal cell voltage V.sub.1c) to the liquid 
crystal cell CL.sub.ij. 
Next, when the voltage of the scan bus line S.sub.i+1 is -V.sub.GP, the 
P-channel thin film transistors such as TFTP.sub.i+1, j connected to the 
scan bus line S.sub.i+1 are turned ON. As a result, +V.sub.R, which also 
defines the voltage of the positive reference voltage supply line 
+V.sub.R, is applied as an electrode voltage V.sub.p via the turned ON 
P-channel thin film transistor such as TFTP.sub.i+1, j to the display 
electrode such as E.sub.i+1, j. Therefore, a voltage -(V.sub.P +V.sub.R), 
which is a difference in potential between the display electrode 
E.sub.i+1, j and the data bus signal D.sub.j, is applied as a write 
voltage (liquid crystal cell voltage Vie) to the liquid crystal cell 
CL.sub.i+1, j. 
Conversely, in an even frame, when the voltage of the scan bus line S.sub.i 
is -V.sub.GP, the P-channel thin film transistors such as TFTP.sub.ij 
connected to the scan bus line S.sub.i are turned ON. As a result, 
+V.sub.R is applied as the electrode voltage V.sub.p as shown in FIG. 15F 
via the turned ON P-channel thin film transistor such as TFTP.sub.ij to 
the display electrode such as E.sub.ij. Therefore, a voltage -(V.sub.D 
+V.sub.R), which is a difference in potential between the display 
electrode E.sub.ij and the data bus signal D.sub.j, is applied as the 
write voltage (liquid crystal cell voltage V.sub.1c) to the liquid crystal 
cell CL.sub.ij. 
Next, when the voltage of the scan bus line S.sub.i+1 is +V.sub.GN, the 
N-channel thin film transistors such as TFTN.sub.i+1, j connected to the 
scan bus line S.sub.i+1 are turned ON. As a result, -V.sub.R is applied as 
an electrode voltage V.sub.p via the turned ON N-channel thin film 
transistor such as TFTN.sub.i+1,j to the display electrode such as 
E.sub.i+1, j. Therefore, a voltage V.sub.D +V.sub.R, which is a difference 
in potential between the display electrode E.sub.i+1, j and the data bus 
signal D.sub.j, is applied as a write voltage (liquid crystal cell voltage 
V.sub.1c) to the liquid crystal cell CL.sub.i+1, j. 
That is, the signal of the data bus line such as D.sub.j is reversed for 
every frame, is applied to each of the liquid crystal cells, and in 
addition, the P-channel thin film transistors and the N-channel thin film 
transistors are alternately turned ON for every frame. As a result, the 
reference voltage -V.sub.R or +V.sub.R is applied as the electrode voltage 
V.sub.p via the turned-ON thin film transistors, and therefore, these 
differences (V.sub.D +V.sub.R) and -(V.sub.D +V.sub.R) are written into 
the liquid crystal cells such as CL.sub.ij, to obtain the liquid crystal 
voltage V.sub.1c. 
Thus, the reference voltage V.sub.R is the same as the write voltage 
applied to the liquid crystal cell CL.sub.ij, i.e., a bias corresponding 
to the reference voltage V.sub.R is given, and therefore, it is possible 
to reduce the voltage .+-.V.sub.D of the data bus lines such as D.sub.j 
required to obtain a minimum liquid crystal cell voltage V.sub.1c. In 
other words, the amplitude of the signal of the data bus lines is reduced. 
That is, if a threshold voltage of a liquid crystal cell is V.sub.th and a 
saturation voltage of the liquid crystal cell is V.sub.sat, the voltage 
V.sub.D of the data bus lines such as D.sub.j and the reference voltage 
V.sub.R can be 
EQU V.sub.D =(V.sub.sat -V.sub.th)/2 
EQU V.sub.R =(V.sub.sat +V.sub.th)/2 
Thus, the voltage V.sub.D can be reduced by 1/4 as compared with the 
devices of FIGS. 5, 8, and 11 where V.sub.D V.sub.sat. Note that V.sub.th 
is usually half of V.sub.sat. 
The scan signals applied to the scan bus lines S.sub.i and S.sub.i+1 of 
FIGS. 15A and 15B are generated by the synchronization circuits 2 and 2' 
and the switch circuit 3 and 3' of FIG. 1. That is, the switch circuit 3 
generates a signal S.sub.COUT1 as shown in FIG. 16A, and the switch 
circuit 3' generates a signal S.sub.COUT2 as shown in FIG. 16E. In this 
case, the voltages V.sub.1 and V.sub.2 of the switch circuit 3 are 
+V.sub.GN and -V.sub.GP, respectively, and the voltages V.sub.1 ' and 
V.sub.2 ' of the switch circuit 3' are also +V.sub.GN and -V.sub.GP, 
respectively. Shift data SD.sub.1 as shown in FIG. 16C is supplied to the 
shift register 22, and shift data SD.sub.2 as shown in FIG. 16G is 
supplied to the shift register 22'. Such shift data SD.sub.1 and SD.sub.2 
are shifted within the shift registers 22 and 22', respectively, in 
synchronization with shift clock signals SCK.sub. 1 and SCK.sub.2 as shown 
in FIGS. 16B and 16F, respectively. As a result, the signals applied to 
the scan bus lines S.sub.i and S.sub.i+1 are obtained as shown in FIGS. 
16D and 16H, respectively. 
The above-mentioned waveforms as shown in FIGS. 16A through 16H are 
generated in an odd frame, but in an even frame, the switch circuits 3 and 
3' generate the waveforms as shown in FIGS. 16E and 16A, respectively. 
According to the active matrix-type liquid crystal display device of FIG. 
14, since the polarity of the signals of the scan bus lines S.sub.i, 
S.sub.i+1, . . . is reversed for every frame, the polarity of the shift 
voltage .DELTA.V.sub.1c due to the parasitic electrostatic capacity is 
reversed for every frame. Therefore, the shift voltage .DELTA.V.sub.1c 
generated during an odd frame is counteracted with the shift voltage 
.DELTA.V.sub.1c generated during an even frame, so that the total shift 
voltage becomes zero. Thus, the generation of a DC component in the AC 
voltage applied to the liquid crystal cells is avoided. 
Also, the crosstalk due to the amplitude of the data bus lines is reduced 
and this improves the display quality. 
In FIG. 17, which is a fifth embodiment of the counter-matrix-type display 
device according to the present invention, the device of FIG. 14 is 
modified to further avoid flickering. That is, the polarities of the 
reference voltage bus line connected to each of the N-channel thin film 
transistors and the P-channel transistors are reversed for very column of 
the liquid crystal cells, i.e., the display electrodes such as E.sub.ij. 
The signals of the device of FIG. 17 are the same as those of the device 
of FIG. 14, except that, as shown in FIGS. 18D and 18E, the polarity of a 
signal of one data bus line such as D.sub.j is opposite to the polarity of 
a signal of another adjacent data bus such as D.sub.j+1, since the 
electrode voltage V.sub.p of the display electrode such as E.sub.ij 
depends on whether or not the N-channel transistor is turned ON. As a 
result, voltages (V.sub.D +V.sub.R) and -(V.sub.D +V.sub.R) are 
alternately written into the liquid crystal cell for every column. 
According to the active matrix-type liquid crystal display device of FIG. 
17, the flickering can be avoided due to the reversing of the polarity of 
the data bus lines for every column, in addition to the effect of the 
device of FIG. 14. 
In FIG. 19, which is a sixth embodiment of the counter-matrix-type display 
device according to the present invention, the device of FIG. 14 is 
modified. That is, each of the scan bus lines S.sub.i, S.sub.i+1, . . . of 
FIG. 14 is split into two pieces S.sub.i (U), S.sub.i (L); S.sub.i+1 (U), 
S.sub.i+1 (L); . . . on both sides of each row of the display electrodes. 
In this case, the gates of the N-channel thin film transistors such as 
TFTN.sub.ij are connected to the upper side scan bus line such as S.sub.i 
(U), while the gates of the P-channel thin film transistors such as 
TFTP.sub.ij are connected to the lower side scan bus line such as S.sub.i 
(L). The operation of the device of FIG. 19 is the same as that of the 
device of FIG. 14. 
According to the device of FIG. 19, the length of the connections between 
the drains of the thin film transistors and their corresponding reference 
voltage supply lines +V.sub.R and -V.sub.R can be shortened, thereby to 
reduce the parasitic capacity between the drains of the thin film 
transistor and the corresponding display electrode, thus reducing the 
crosstalk and increasing the ratio of openings, in addition to the effect 
of the device of FIG. 14. 
In FIG. 20, which is a seventh embodiment of the counter-matrix-type 
display device according to the present invention, the device of FIG. 17 
is modified. That is, the modification of the device of FIG. 17 relative 
to the device of FIG. 20 is the same as that of the device of FIG. 14 
relative to the device of FIG. 19. 
That is, each of the scan bus lines S.sub.i, S.sub.i+1, . . . of FIG. 17 is 
split into two pieces S.sub.i (U), S.sub.i (L); S.sub.i+1 (U), S.sub.i+1 
(L); . . . on both sides of each row of the display electrodes. In this 
case, the gates of the N-channel thin film transistors such as TFTN.sub.ij 
are connected to the upper side scan bus line such as S.sub.i (U), while 
the gates of the P-channel thin film transistors such as TFTP.sub.ij are 
connected to the lower side scan bus line such as S.sub.i (L). 
The operation of the device of FIG. 20 is explained with reference to FIGS. 
21A through 21H. 
As shown in FIGS. 21A, 21B, and 21C, the signals of the scan bus lines 
S.sub.i, S.sub.i+1, and S.sub.i+2 have the same polarity in the same 
frame, and this polarity is reversed for every frame. Therefore, as shown 
in FIGS. 21D and 21E, the signals of the data bus lines D.sub.j, D.sub.j+1 
have different polarities in the same frame, and these polarities are 
reversed for every frame. 
The scan signals applied to the scan bus lines S.sub.i and S.sub.i+1 of 
FIGS. 21A and 21B are generated by the synchronization circuits 2 and 2' 
and the switch circuits 3 and 3' of FIG. 1. That is, the switch circuit 3 
generates a signal SC.sub.OUT1 as shown in FIG. 22A, and the switch 
circuit 3' generates a signal SC.sub.OUT2 as shown in FIG. 22E. In this 
case, the voltages V.sub.1 and V.sub.2 of the switch circuit 3 are 
+V.sub.GN and -V.sub.GP, respectively, and the voltages V.sub.1 ' and 
V.sub.2 ' of the switch circuit 3' are also +V.sub.GN and -V.sub.GP, 
respectively. Shift data SD.sub.1 as shown in FIG. 22C is supplied to the 
shift register 22, and shift data SD.sub.2 as shown in FIG. 22G is 
supplied to the shift register 22'. Such shift data SD.sub.1 and SD.sub.2 
are shifted within the shift registers 22 and 22', respectively, in 
synchronization with shift clock signals SCK.sub.1 and SCK.sub.2 as shown 
in FIGS. 22B and 22F, respectively. As a result, the signals applied to 
the scan bus lines S.sub.i and S.sub.i+1 are obtained as shown in FIGS. 
22D and 22H, respectively. 
The above-mentioned waveforms as shown in FIGS. 22A through 22H are 
generated in an odd frame, but in an even frame, the switch circuits 3 and 
3' generate the waveforms as shown in FIGS. 22E and 22A, respectively. 
According to the active matrix-type liquid crystal device of FIG. 20, all 
the effects of the devices of FIGS. 14, 17, and 19 are obtained. That is, 
the shift voltage .DELTA.V.sub.1c can be compensated for, and the 
flickering can be avoided. Also, the connections between the sources of 
the thin film transistors and their corresponding display electrodes are 
shortened, to reduce the parasitic electrostatic capacity between the of 
the thin film transistors and the corresponding display electrodes. 
In FIG. 23, which is an eighth embodiment of the counter-matrix-type 
display device according to the present invention, and in FIG. 24, which 
is a layout diagram of the device of FIG. 23, all of the thin film 
transistors TFTN.sub.ij, TFTN.sub.ij ' are of an N-channel type. A 
plurality of reference voltage supply bus lines are formed on the device 
in parallel, spaced relationship, each disposed intermediate a related 
pair of scan bus lines (e.g., as shown in FIG. 23, the reference voltage 
supply line VR.sub.i is disposed intermediate the pair of parallel and 
spaced, first and second scan bus lines S.sub.i-1 and S.sub.i). All of the 
parallel reference voltage supply bus lines (V.sub.Ri, V.sub.Ri+1, . . . ) 
are connected to a single reference voltage supply V.sub.R, which thus is 
provided in common to the entire device, and V.sub.R is switched from a 
first level to a second level for every horizontal scanning time period H. 
Also, two scan bus lines such as S.sub.i-1 ' and S.sub.i are arranged on 
both sides of the reference voltage supply line V.sub.R, and the two scan 
bus lines such as S.sub.i-1 ' and S.sub.i are connected at a terminal such 
as T.sub.i, to surround the reference voltage supply line V.sub.R. 
The gates of the N-channel thin film transistors such as TFTN.sub.ij are 
connected to the downstream side scan bus lines such as S.sub.i, and the 
gates of the N-channel thin film transistors such as TFTN.sub.ij ' are 
connected to the upstream side scan bus lines such as S.sub.i '. The 
sources of the thin film transistors are connected to the reference 
voltage supply line V.sub.R and the drains of the thin film transistors 
are connected to the corresponding display electrodes such as E.sub.ij. 
The operation of the device of FIGS. 23 and 24 particularly, the operation 
for the display electrode E.sub.ij (liquid crystal cell (L.sub.ij)) is 
explained with reference to FIGS. 25A through 25F. 
When a scan voltage (+V.sub.g) as shown in FIG. 25B is applied to the scan 
bus line S.sub.i+1 (S.sub.i '), the N-channel thin film transistor such as 
TFTN.sub.ij ' is turned ON, so that the display electrode E.sub.ij is 
electrically connected to the reference voltage supply line V.sub.R. Thus, 
the difference in potential between the reference voltage supply line 
V.sub.R as shown in FIG. 25D and the data bus line D.sub.j as shown in 
FIG. 25E, becomes the liquid crystal voltage Vie as shown in FIG. 25F. 
On the other hand, simultaneously with the application of the scan voltage 
(V.sub.g) to the scan bus line S.sub.i+1 (S.sub.i '), even when a scan 
voltage (-V.sub.cg) as shown in FIG. 25A applied to the scan bus line 
S.sub.i (S.sub.i-1 '), the N-channel thin film transistor TFTN.sub.ij is 
turned OFF. 
This compensates for the shift voltage .DELTA.V.sub.ec appearing in the 
display electrode E.sub.ij. That is, the shift voltage .DELTA.V.sub.ec ' 
due to the change of the scan voltage applied to the scan bus line 
S.sub.i+1 (S.sub.1 ') from +V.sub.g to OV is compensated for by the shift 
voltage .DELTA.V.sub.1c due to the change of the scan voltage applied to 
the scan bus line S.sub.i (S.sub.i-1 ') from -V.sub.cg to OV. 
Also, before the application of the scan voltage (-V.sub.cg) to the scan 
bus line S.sub.i (S.sub.i-1 '), a scan voltage (+V.sub.g) is applied to 
the scan bus line S.sub.i (S.sub.i-1 ') as shown in FIG. 25A, to turn ON 
the N-channel thin film transistor TFTN.sub.ij, thereby writing data into 
the liquid crystal cell CL.sub.ij (E.sub.ij). Usually, this written data 
is immediately canceled by the application of the scan voltage V.sub.g to 
the scan bus line S.sub.i+1 (S.sub.i '). However, if the N-channel thin 
film transistor TFTN.sub.ij is broken for some reason, a write operation 
is performed upon the display electrode E.sub.ij (liquid crystal cell 
CL.sub.ij) via the N-channel thin film transistor TFTN.sub.ij by the scan 
voltage applied to the scan bus line S.sub.i (S.sub.1-1 '). Thus, such a 
redundancy configuration can remedy a defective liquid crystal display 
device where some thin film transistors are defective. 
The scan voltages as shown in FIGS. 25A, 25B, and 25C are sequentially 
generated in the same way as in the device of FIG. 8. 
As a result, as shown in FIG. 25F, the liquid crystal voltage V.sub.1c 
between the display electrode E.sub.ij and the data bus line D.sub.j is 
maintained until the next scan voltages are applied to the scan bus lines 
S.sub.i (S.sub.i-1 ') and S.sub.1+1 (S.sub.i '). 
According to the device of FIGS. 23 and 24, a parasitic electrostatic 
capacity between the reference voltage supply line V.sub.R and the display 
electrodes such as E.sub.ij can be reduced, i.e., the parasitic 
electrostatic capacity Cap in the formula (2) can be reduced, to lessen 
the shift voltage .DELTA.V.sub.1c thereby reducing the crosstalk. 
In FIG. 26, which is a cross-sectional view taken along the line A--A' of 
FIG. 24, a metal layer M.sub.1 (i.e., the display electrode E.sub.ij) and 
a metal layer M.sub.2 are formed on the glass substrate SUB.sub.1. 
Reference S and D are contact layers which serve as a source electrode and 
a drain electrode. The contact layers S and D are formed by N+-type 
amorphous silicon, for example. Reference I designates an intrinsic 
semiconductor layer formed by amorphous silicon. Also, SP.sub.i and 
V.sub.R are metal layers formed by polycrystalline silicon, aluminium, 
tungsten, molybdenum, chromium, or the like. 
In FIG. 27, which shows an example of the transmissibility characteristic 
of a liquid crystal cell, if the absolute value of the liquid crystal 
voltage V.sub.1c is smaller than a threshold voltage V.sub.th, the liquid 
crystal cell is dark, while if the absolute value of the liquid crystal 
voltage Vie is .larger than a saturation voltage V.sub.sat, then the 
liquid crystal cell is bright. 
Assume that V.sub.th =2.5 V and V.sub.sat =5 V. Then, the difference 
between the high level and low level of the reference voltage supply line 
V.sub.R is 12-4.5=7.5 V as shown in FIG. 25D, which corresponds to a value 
of V.sub.th +V.sub.sat (=7.5 V). 
Also, when the reference voltage V.sub.R is 4.5 V and the voltage of the 
data bus line D.sub.j is 9.5 V, as shown in FIGS. 25D and 25E, the liquid 
crystal voltage V.sub.1c is -5 V which means "bright". Conversely, when 
the reference voltage V.sub.R is 4.5 V and the voltage of the data bus 
line D.sub.j is 7 V, as indicated by arrows X in FIGS. 25D and 25E, the 
liquid crystal voltage V.sub.1c is -2.5 V which means "dark". 
The shift voltage .DELTA.V.sub.1c of the liquid crystal voltage V.sub.1c 
can be represented by 
##EQU1## 
where .DELTA.V.sub.D is a fluctuation of the voltage of the data bus line 
such as D.sub.j, and .DELTA.V.sub.R is a fluctuation of the reference 
voltage V.sub.R. Note that, the shift voltage .DELTA.V.sub.1c ' in the 
prior art can be represented by 
##EQU2## 
In the device of FIGS. 23 and 24, the reference voltage V.sub.R is 
alternately switched from 12 V to 4.5 V or vice versa, so that the 
amplitude of the signals of the data bus lines can be reduced. For 
example, the liquid crystal voltage V.sub.1c is .+-.5 V, but the amplitude 
of the signal of the data bus line D.sub.j is 2.5 V (=9.5-7). Further, 
since the reference voltage supply line V.sub.R is surrounded by the scan 
bus lines, the parasitic electrostatic capacity C.sub.dp between the 
source-drain of the thin film transistors is reduced thereby lessening the 
shift voltage .DELTA.V.sub.1c of the liquid crystal voltage V.sub.1c. 
When the operation of the thin film transistors TFTN.sub.ij ' and 
TFTN.sub.i+1, j is carried out by the scan bus lines S.sub.i ' and 
S.sub.i+1, the shift voltage .DELTA.V.sub.1c generated at the liquid 
crystal cell is represented by 
EQU .DELTA.V.sub.1c =V.sub.g .times.C.sub.2 /(C.sub.1 +C.sub.2 +C.sub.dp 
+C.sub.LC) (6) 
where C.sub.1 is a parasitic electrostatic capacity between the display 
electrode E.sub.ij and the scan bus line S.sub.i+1, and C.sub.2 is a 
parasitic electrostatic capacity between the display electrode E.sub.ij 
and the scan bus line S.sub.i '. Therefore, this shift voltage 
.DELTA.V.sub.1c can be on the whole compensated for by applying -V.sub.gp 
via the scan bus line SP.sub.i to the gate of the thin film transistor 
TFTP.sub.ij. In this case, 
EQU -V.sub.cg =-V.sub.g .times.C.sub.2 /C.sub.1 (7) 
Note that V.sub.g =V.sub.cg in FIGS. 25A, 25B, and 25C, if C.sub.1 
=C.sub.2. 
In FIGS. 28A, 28B, and 28C, which are modifications of FIGS. 25A, 25B, and 
25C, respectively, when a scan voltage (+V.sub.g) is applied to the scan 
bus line S.sub.i+1 (S.sub.i '), a scan voltage (-V.sub.cg) is applied to 
the upstream-side scan bus line S.sub.i (S.sub.1-1 ') as indicated by X 
and a scan voltage (-V.sub.cg) is applied to the downstream side scan bus 
line S.sub.i+2 (S.sub.i+1 ') as indicated Y. As a result,even when the 
display electrode E.sub.i+1, j is operated by only the N-channel thin film 
transistor TFTN.sub.i+1, j', the shift voltage .DELTA.Vec appearing in the 
display electrode E.sub.i+1, j can be compensated for. 
The scan signals applied to the scan bus lines S.sub.i (S.sub.i-1 ') and 
S.sub.+1 (S.sub.i ') of FIGS. 28A and 28B are generated by the 
synchronization circuits 2 and 2' and the switch circuit 3 and 3' of FIG. 
1. That is, the switch circuit 3 generates a signal SC.sub.OUT1 as shown 
in FIG. 29A, and the switch circuit 3' generates a signal SC.sub.OUT2 as 
shown in FIG. 29E. In this case, the voltages V.sub.1 and V.sub.2 of the 
switch circuit 3 are +V.sub.g and -V.sub.cg, respectively, and the 
voltages V.sub.1 ' and V.sub.2 ' of the switch circuit 3' are also 
+V.sub.g and -V.sub.cg, respectively. Shift data SD.sub.1 as shown in FIG. 
29C is supplied to the shift register 22, and shift data SD.sub.2 as shown 
in FIG. 29G is supplied to the shift register 22'. Such shift data 
SD.sub.1 and SD.sub.2 are shifted within the shift registers 22 and 22', 
respectively, in synchronization with shift clock signals SCK.sub.1 and 
SCK.sub.2, as shown in FIGS. 29B and 29F, respectively. As a result, the 
signals applied to the scan bus lines SN.sub.i and SP.sub.i are obtained 
as shown in FIGS. 29D and 29H, respectively. 
In FIG. 30, which is a ninth embodiment of the counter-matrix-type display 
device according to the present invention, protrusions or extensions ES 
are added on the downstream side scan bus lines S.sub.i, S.sub.i+1, . . . 
, of FIG. 24. The extensions ES are formed between the display electrodes 
such as E.sub.ij, E.sub.i,j+1, . . . As a result, the parasitic 
electrostatic capacity C.sub.1 between the display electrode E.sub.ij and 
the scan bus line S.sub.i is made larger than the parasitic electrostatic 
capacity C.sub.2 between the display electrode E.sub.ij and the scan bus 
line S.sub.i (C.sub.1 &gt;C.sub.2), thus reducing the compensating voltage 
-V.sub.cg in the formula (7). 
In FIG. 31, which is a tenth embodiment of the counter-matrix-type display 
device according to the present invention, the device of FIG. 24 is 
modified. That is, the distance between the display electrode E.sub.ij and 
the upstream side scan bus line S.sub.i thereof is smaller than a distance 
between the display electrode E.sub.ij and the downstream side scan bus 
line S.sub.i ' thereof. As a result, the parasitic electrostatic capacity 
C.sub.1 between the display electrode E.sub.ij and the scan bus line 
S.sub.i is made larger than the parasitic electrostatic capacity C.sub.2 
between the display electrode E.sub.ij and the scan bus line S.sub.i 
(C.sub.1 &gt;C.sub.2), thus reducing the compensating voltage-Y.sub.cg in the 
formula (7). 
In FIGS. 32A through 32E, which are modifications of FIGS. 25A, and 25B, 
and 25C, an interlaced scanning is carried out. 
In an odd field, when +V.sub.g is applied to the scan bus line S.sub.i+1 
(S.sub.i ') as shown in FIG. 32C, -V.sub.cg is applied to its adjacent two 
scan bus lines S.sub.i (S.sub.i-1 ') and S.sub.i+2 (S.sub.i+1 ') as shown 
in FIGS. 32B and 32D, and the thin film transistors TFTN.sub.ij ' and 
TFTN.sub.i+1,j connected to the scan bus line S.sub.i+1 (S.sub.i ') are 
turned ON, so that the data voltage of the data bus line D.sub.j is 
applied to two liquid crystal cells. 
Then, in the next scanning time period, +V.sub.g is applied to the scan bus 
line S.sub.i+3 (S.sub.i+2 ') and -V.sub.cg is applied to its adjacent two 
scan bus lines, and the data voltage of the data bus line D.sub.j is 
applied to two liquid crystal cells adjacent to the scan bus lines 
S.sub.i+3 (S.sub.i+2 '). In an even field, when +V.sub.g is applied to the 
scan bus line S.sub.i (S.sub.i-1 ') as shown in FIG. 32B, -V.sub.cg is 
applied to its adjacent two scan bus lines S.sub.i (S.sub.i-2 ') (not 
shown) and S.sub.i+1 (S.sub.i ') as shown in FIG. 32B, and the thin film 
transistors TFTN.sub.i-1,j ' and TFTN.sub.ij connected to the scan bus 
line S.sub.i (S.sub.i-1 ') are turned ON, so that the data voltage of the 
data bus line D.sub.j is applied to two liquid crystal cells. 
Then, in the next scanning time period, +V.sub.g is applied to the scan bus 
line S.sub.i+2 (S.sub.i+1 ') and -V.sub.cg is applied to its adjacent two 
scan bus lines, and the data voltage of the data bus line D.sub.j is 
applied to two liquid crystal cells adjacent to the scan bus lines 
S.sub.i+2 (S.sub.i+1 '). 
Thus, in each of the odd field and the even field, data is written into 
every two rows of liquid crystal cells, and in addition, the shift voltage 
in each of the written liquid crystal cells is compensated for by the scan 
voltages applied to the two adjacent scan bus lines. Also, only one row to 
be written is advanced at each switching from an old frame to an even 
frame or vice versa, thereby carrying out an interlaced scanning. Also, in 
this case, the voltage -V.sub.cg is selected so as to reduce the shift 
voltage. 
The scan signals applied to the scan bus lines S.sub.i+1 (S.sub.i+2 ') and 
S.sub.i (S.sub.i+1 ') of FIGS. 32A and 32B are generated by the 
synchronization circuits 2 and 2' and the switch circuit 3 and 3' of FIG. 
1. That is, the switch circuit 3 generates a signal SC.sub.OUT1 as shown 
in FIG. 33A, and the switch circuit 3' generates a signal SC.sub.OUT2 as 
shown in FIG. 33E. In this case, the voltages V.sub.1 and V.sub.2 of the 
switch circuit 3 are +V.sub.g and -V.sub.cg, respectively, and the 
voltages V.sub.1 ' and V.sub.2 ' of the switch circuit 3' are also 
+V.sub.g and -V.sub.cg, respectively. Shift data SD.sub.1 as shown in FIG. 
33C is supplied to the shift register 22, and shift data SD.sub.2 as shown 
in FIG. 33G is supplied to the shift register 22'. Such shift data 
SD.sub.1 and SD.sub.2 are shifted within the shift registers 22 and 22', 
respectively, in synchronization with shift clock signals SCK.sub.1 and 
SCK.sub.2 as shown in FIGS. 33B and 33F, respectively. As a result, the 
signals applied to the scan bus lines SN.sub.i and SP.sub.i are obtained 
as shown in FIGS. 33D and 33H, respectively. 
In FIG. 34, which is an eleventh embodiment of the counter-matrix-type 
display device according to the present invention, the device of FIG. 23 
is modified. That is, the thin film transistors such as TFTP.sub.ig 
connected to the scan bus lines S.sub.i, S.sub.i+1, S.sub.i+2, . . . are 
of a P-channel type, and the thin film transistors such as TFTN.sub.ij 
connected to the scan bus lines S.sub.i-1 ' S.sub.i ', S.sub.i+1 ', . . . 
are of an N-channel type. 
The operation of the device of FIG. 34 is explained with reference to FIGS. 
35A through 35F. 
The reference voltage V.sub.R is changed as shown in FIG. 35D. When 
+V.sub.g is applied to the scan bus line S.sub.i+1 (S.sub.i ') as shown in 
FIG. 35B, and -V.sub.cg is applied to the scan bus line S.sub.i (S.sub.i-1 
') as shown in FIG. 35A, the P-channel thin film transistor TFTP.sub.ij 
connected to the scan bus line S.sub.i is turned ON and the N-channel thin 
film transistor TFTN.sub.ij connected to the scan bus line S.sub.i ' is 
turned ON. As a result, the display electrode E.sub.ij is electrically 
connected to the reference voltage supply line V.sub.R by both of the thin 
film transistors TFTP.sub.ij and TFTN.sub.ij. Therefore, the liquid 
crystal voltage V.sub.1c is the difference between the reference voltage 
V.sub.R and the data voltage of the data bus line D.sub.j as shown in 
FIGS. 35D, 35E, and 35F. 
In the above-mentioned state, the N-channel thin film transistor 
TFTN.sub.i-1, j connected to the adjacent display electrode E.sub.i-1, j 
and the P-channel thin film transistor TFTP.sub.i+1,j connected to the 
adjacent display electrode E.sub.i+1,j are turned OFF, and accordingly, 
the data voltage is not applied to the display electrodes Ell,.sub.j and 
E.sub.i+1,j. 
In the next horizontal scanning time period, when +V.sub.g is applied to 
the scan bus line S.sub.i+2 (S.sub.i+1) as shown in FIG. 35C, and 
-V.sub.cg is applied to the scan bus line S.sub.i+1 (S.sub.i ') as shown 
in FIG. 35B, the P-channel thin film transistor TFTP.sub.i+1,j connected 
to the scan bus line S.sub.i+1 is turned ON and the N-channel thin film 
transistor TFTN.sub.i+1, j connected to the scan bus line S.sub.i+1,' is 
turned ON. As a result, the display electrode E.sub.i+1, j is electrically 
connected to the reference voltage supply line V.sub.R by both of the thin 
film transistors TFTP.sub.i+1,j and TFTN.sub.i+1, j. Therefore, the liquid 
crystal voltage Vie is the difference between the reference voltage 
V.sub.R and the data voltage of the data bus line D.sub.j as shown in 
FIGS. 35D, 35E, and 35F. 
In the above-mentioned state, the N-channel thin film transistor 
TFTN.sub.i, j connected to the adjacent display electrode E.sub.i, j and 
the P-channel thin film transistor TFTP.sub.i+2,j connected to the 
adjacent display electrode E.sub.i+1,j are turned OFF, and accordingly, 
the data voltage is not applied to the display electrodes E.sub.ij and 
E.sub.i+2, j. 
Note that the scan signals of the scan bus lines S.sub.i (S.sub.i-1 '), 
S.sub.+1 (S.sub.i '), . . . can be generated in the same way as in FIGS. 
10A through 10H. 
Also, in FIG. 34, the P-channel thin film transistors and the N-channel 
thin film transistors can be exchanged with each other. 
In FIG. 36, which is a twelfth embodiment of the counter-matrix-type 
display device according to the present invention, the device of FIG. 23 
is modified. In general, in FIG. 23, the gates of thin film transistors 
serve as one part of the scan bus lines, and they are of a multi-layer 
configuration. In addition, the portions of the gates of the thin film 
transistors are easily disconnected. Therefore, if the gates of the thin 
film transistors are disconnected, the scan bus lines are disconnected. 
Particularly, in the device of FIG. 23, the two thin film transistors such 
as TFTN.sub.i-1,j ' and TFTN.sub.ij are very close to each other, so that 
disconnections are easily caused in the scan bus lines. Conversely, in 
FIG. 36, the two thin film transistors TFTN.sub.i-1,j and TFTN.sub.ij each 
connected to a pair of the scan bus lines such as S.sub.i and S.sub.i-1 ', 
are distant from each other, thus avoiding the possible disconnection of 
the scan bus lines. 
Also, the scan signals are supplied to the pairs of the scan bus lines 
S.sub.i-1 ' and S.sub.i, S.sub.i ' and S.sub.i+1, S.sub.i+1 ' and 
S.sub.+2, . . . from both sides thereof. As a result, unless two or more 
continuous disconnections occur in the scan bus lines, all of the thin 
film transistors can be driven by scan signals, so that no defective 
display is generated. 
The manufacturing steps for the active liquid crystal device of FIG. 36 are 
explained with reference to FIGS. 37A through 40A and FIGS. 37B through 
40B, which are cross-sectional views taken along the line B--B of FIGS. 
37A through 40A, respectively. 
As shown in FIGS. 37A and 37B, an ITO having a thickness of about 50 nm is 
deposited on the glass substrate (not shown) by a sputtering method, to 
obtain a transparent conductive layer (M.sub.1, M.sub.2), and n.sup.+ 
-amorphorous silicon having a thickness of about 30 nm is deposited 
thereon by a plasma chemical vapor deposition (CVD) method, to obtain an 
ohmic contact layer (n+A) on the transparent conductive layer. Thereafter, 
a patterning operation using a conventional photolithography method is 
carried out. In FIG. 37B, the transparent conductive layer M.sub.1 is a 
part of the display electrode E.sub.i,j+1, and the transparent conductive 
layer M.sub.2 is used for connecting a reference voltage supply line 
V.sub.R. Also, O.sub.l designates an opening for a thin film transistor. 
Next, as shown in FIGS. 38A and 38B, amorphorous silicon, which is 
intrinsic semiconductor, is deposited, to obtain an intrinsic layer I, and 
a silicon nitride (S.sub.i3 N.sub.4) layer IN is deposited thereon by 
using the plasma CVD method. Note that the amorphorous silicon layer I and 
the S.sub.i3 N.sub.4 layer IN are about 30 nm and 50 nm in thickness, 
respectively. Then, a patterning operation is carried out to obtain a 
configuration as shown in FIG. 38B. 
Next, as shown in FIGS. 39A and 39B, another silicon nitride (S.sub.i3 
N.sub.4) layer IN' having a thickness of about 250 nm is deposited, and 
then, a patterning operation is carried out to form an opening O.sub.2 as 
shown in FIG. 39B. 
Finally, as shown in FIGS. 40A and 40B, an aluminum (Al) layer is deposited 
by the sputtering, and then a patterning operation is carried out to 
obtain the scan bus line S.sub.i and the reference voltage supply line 
V.sub.R. 
In FIG. 41, which is a thirteenth embodiment of the counter-matrix-type 
display device according to the present invention, the device of FIG. 23 
is also modified. That is, connections N.sub.i, N.sub.i+1, N.sub.i+2, . . 
. are provided for the pairs of the scan bus lines S.sub.i-1 ' and 
S.sub.i, S.sub.i ' and S.sub.i+1, S.sub.i+1 ' and S.sub.i+2, . . . As a 
result, unless two or more continuous disconnections occur in the scan bus 
lines, all of the thin film transistors can be driven by scan signals, so 
that no defective display is generated. Particularly, in the case of the 
thin film transistors having a top gate staggered configuration, when a 
conductive layer between the pair of the scan bus lines such as S.sub.i 
and S.sub.1-1 ' is the same as a conductor layer of the sources and drains 
of the thin film transistors, the presence of the above-mentioned 
connections N.sub.i, N.sub.i+1, . . . hardly affects the reference voltage 
supply line V.sub.R at the intersections thereof with the connection 
electrodes such as N.sub.i, N.sub.i+1, . . . (see FIG. 45C). That is, 
these intersections have a cross-sectional configuration similar to thin 
film transistors (see: FIGS. 45B and 45C), thereby to minimize the areas 
occupied by the connections between the pairs of the scan bus lines. For 
example, for a 480.times.640 dot color panel, an occupied area of the thin 
film transistors per one scan line is 5.times.20.times.640.times.3=192000 
.mu.m.sup.2, if an occupied area of one thin film transistor is 5.times.20 
.mu.m.sup.2 (see: S.sub.1 of FIG. 43A). 
Contrary to this, if there are provided ten connections per one pair of 
scan bus lines, an occupied area of the connections per one scan line 
(see: S.sub.2 of FIG. 43A) is 10.times.10.times.10=1000 .mu.m.sup.2. 
Thus, the increased occupied area by the connections is less than 1%. 
The manufacturing steps for the active liquid crystal device of FIG. 41 are 
explained with reference to FIGS. 42A through 45A, FIGS. 42B through 45B, 
which are cross-sectional views taken along the line B--B of FIGS. 42A 
through 45A, respectively, and FIGS. 42C through 45C, which are 
cross-sectional views taken along the line C--C of FIGS. 42A through 45A, 
respectively. 
As shown in FIGS. 42A, 42B, and 40C, an ITO having a thickness of about 50 
nm is deposited on the glass substrate (not shown) by a sputtering method, 
to obtain a transparent conductive layer (M.sub.1, M.sub.2, M.sub.3), and 
N.sup.+ -amorphorous silicon having a thickness of about 30 nm is 
deposited thereon by a plasma chemical vapor deposition (CVD) method, to 
obtain an ohmic contact layer (n+A) to the transparent conductive layer. 
Thereafter, a patterning operation using a conventional photolithography 
method is carried out. In FIG. 42B, the transparent conducive layer 
M.sub.1 is a part of the display electrode E.sub.i,j+2, and the 
transparent conductive layer M.sub.2 is used for connecting a reference 
voltage supply line V.sub.R. Also, O.sub.1 designates an opening for a 
thin film transistor. Further, in FIG. 42C, the transparent conductive 
layer M.sub.3 serves as the connection N.sub.i. 
Next, as shown in FIGS. 43A, 43B, and 43C, amorphorous silicon, which is 
intrinsic semiconductor, is deposited, to obtain an intrinsic layer I, and 
a silicon nitride (S.sub.i3 N.sub.4) layer IN is deposited thereon by 
using the plasma CVD method. Note that the amorphorous silicon layer I and 
the S.sub.i3 N.sub.4 layer IN are about 30 nm and 50 nm in thickness, 
respectively. Then, a patterning operation is carried out to obtain a 
configuration as shown in FIG. 43B and 43C. 
Next, as shown in FIGS. 44A, 44B, and 44C, another silicon nitride 
(S.sub.i3 N.sub.4) layer IN' having a thickness of about 250 nm is 
deposited, and then, a patterning operation is carried out to form an 
opening O.sub.2 as shown in FIG. 44B, and openings O.sub.3 and O.sub.4 as 
shown in FIG. 44C. 
Finally, as shown in FIGS. 45A, 45B, and 45C, an aluminum (Al) layer is 
deposited by sputtering, and then a patterning operation is carried out to 
obtain the scan bus line S.sub.i and the reference voltage supply line 
V.sub.R as shown in FIG. 45B, and the scan bus lines S.sub.i and S.sub.i-1 
' and the reference voltage supply line V.sub.R as shown in FIG. 45C. 
In FIG. 46, which is a fourteenth embodiment of the counter-matrix-type 
display device according to the present invention, the device of FIG. 36 
and the device of FIG. 41 are combined, thus avoiding the occurrence of 
disconnections in the scan bus lines, and avoiding a defective display 
even if some disconnections occur in the scan bus lines. 
The manufacturing steps for the active liquid crystal device of FIG. 46 are 
shown in FIGS. 47A through 50A, FIGS. 47B through 50B, which are 
cross-sectional views taken along the line B--B of FIGS. 47A through 50A, 
respectively, and FIGS. 47C through 50C, which are cross-sectional views 
taken along the line C--C of FIGS. 47A through 50A, respectively. However, 
the description of FIGS. 47A through 50A, FIGS. 47B through 50B, and FIGS. 
47C through 50C is omitted, since these figures can be easily understood 
from the descriptions with respect to FIGS. 37A through 40A, FIGS. 37B 
through 40B, FIGS. 42A through 45A, FIGS. 42B through 45B, and FIGS. 42C 
through 45C. 
Although all the above-mentioned embodiments relate to a 
counter-matrix-type active liquid crystal display device as shown in FIG. 
3, the present invention can be applied to a conventional active 
matrix-type liquid crystal display device as shown in FIG. 2. For example, 
if the device of FIG. 5 is applied to the conventional active matrix-type 
liquid crystal display device, a device as illustrated in FIG. 50 is 
obtained. 
In the above-mentioned embodiments, liquid crystal is used as an 
electro-optic element;, however, an electroluminescence element, an 
electrochromic element, and the like can be also used. Various 
configurations, shapes, materials, and the like can be used for the 
above-mentioned active-type liquid crystal panel. 
As described above, according to the present invention, the shift voltage 
due to the various parasitic electrostatic capacities can be compensated 
for, to reduce the crosstalk, thereby improving the display quality. For 
example, the flickering can be avoided and the generation of a residual 
image phenomenon of a stationary image can be avoided. 
Also, since a redundancy in configuration is present for switching 
elements, it is possible to drive the switching element by one switching 
element even when another switching element is defective.