Substrate comprising recessed interconnects and a surface mounted passive component

A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.

BACKGROUND

Field

Various features relate to substrates for integrated devices, but more specifically to substrates comprising a surface mounted passive component.

Background

FIG. 1illustrates an integrated device100that includes a substrate102and a die104. The die104is coupled to a first surface of the substrate102through a plurality of solder interconnects140, which may include bumps and solder.

The substrate102includes a plurality of dielectric layers120, a plurality of interconnects122, and a plurality of surface interconnects123. Each layer of the dielectric layers120includes a patterned metal layer and vias. The substrate102includes a first solder resist layer124, a second solder resist layer126, and a plurality of solder interconnects130.

A capacitor150is mounted over the first surface of the substrate102. More specifically, the capacitor150is coupled to pads of the substrate102through solder interconnects160and162. The solder interconnects160and162are located over the dielectric layers120. The solder interconnects160and162are located between the capacitor150and the pads of the substrate102. This causes the capacitor150to be located higher over the substrate102, which means that the capacitor150is effectively thicker that its actual thickness. In addition, solder interconnect (e.g.,160,162) for each respective terminal of the capacitor150may flow towards each other and touch each other, causing an unintended joint to occur between the solder interconnects160and162.

Therefore, there is a need for providing a substrate with a surface mounted passive component such that the passive component takes up as little space as possible. Ideally, the surface mounted passive component is mounted over the substrate in such a way that a short does not occur between the terminals of the passive component.

SUMMARY

Various features relate to substrates for integrated devices, but more specifically to substrates comprising a surface mounted passive component.

One example provides a device that includes a substrate and a discrete passive component. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete passive component is coupled to the substrate through a solder interconnect. The solder interconnect is located within the dielectric layer.

Another example provides an integrated device that includes a substrate, a die, and means for capacitance. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The means for capacitance is coupled to the substrate through a means for soldering. The means for soldering is located within the dielectric layer. The die is coupled to the substrate.

Another example provides a method for fabricating a device. The method provides a substrate that includes a dielectric layer, a cavity in the dielectric layer, and a plurality of interconnects formed in the dielectric layer. The method couples a discrete capacitor to the substrate through a solder interconnect such that the solder interconnect is located within the cavity of the dielectric layer.

DETAILED DESCRIPTION

The present disclosure describes a device that includes a substrate, a die, and a discrete passive component (e.g., discrete capacitor). The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete passive component is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes (i) a first cavity that is filled with a first via and the first solder interconnect; and (ii) a second cavity that is filled with a second via and the second solder interconnect. The first via may include a curved surface (e.g. concave surface) that is coupled to the first solder interconnect. The second via may include a curved surface (e.g. concave surface) that is coupled to the second solder interconnect.

Exemplary Device Comprising Substrate with Surface Mounted Discrete Passive Component

FIG. 2illustrates a profile view of a device200that includes a substrate202, a die204and a passive component250. The device200may be an integrated device (e.g., integrated circuit device) and/or an integrated package (e.g., integrated circuit package).

The passive component250may be a discrete passive component (e.g., discrete capacitor). A component that is discrete may be a component that is fabricated separately from the substrate202. For example, the passive component250may be made using a different process than the substrate202. A discrete component may be an off the shelf component. As will be further described below, a passive component (e.g.,250,950) may be a discrete passive component that is coupled to the substrate202in such a manner as to minimize the overall space occupied by the passive component, while using a coupling that reduces the likelihood of shorting to occur. The passive component (e.g.,250,950) may include a multi-layer ceramic capacitor (MLCC).

The substrate202includes a dielectric layer220(e.g., first dielectric layer), a dielectric layer222(e.g., second dielectric layer), a first solder resist layer224, a second solder resist layer226, a plurality of interconnects221, a plurality of interconnects223, and a plurality of interconnects225. The substrate202may be a coreless substrate, such an embedded trace substrate (ETS). The dielectric layers220and222may be made of the same or different material. Materials for the dielectric layers220and222may include dry film, such as Ajinomoto build-up film (ABF) and/or prepreg (PPG). The PPG may include glass fibers with resin. It is noted that the substrate202may include more than two dielectric layers. In some implementations, the dielectric layers220and222may be considered as one dielectric layer.

The plurality of interconnects221may include traces and/or pads. The plurality of interconnects221is formed about a first surface of the substrate202. For example, the plurality of interconnects221may be formed over the first surface of the substrate202and/or embedded in the first surface of the substrate202. The first surface of the substrate202may be a first planar surface that faces the die204.

The die204is coupled to the substrate202through a plurality of bump interconnects240and a plurality of solder interconnects242. For example, the die204may be coupled to the plurality of interconnects221through the plurality of bump interconnects240and the plurality of solder interconnects242.

The plurality of interconnects223may include traces and/or pads. The plurality of interconnects223is formed about a second surface of the substrate202. For example, the plurality of interconnects223may be formed over the second surface of the substrate202and/or embedded in the second surface of the substrate202. The second surface of the substrate202may be a second planar surface that faces away from the die204. The second surface of the substrate202may be a surface that is opposite to the first surface of the substrate202.

The plurality of interconnects225may include traces, pads and/or vias. The plurality of interconnects225is formed in the substrate202. In particular, the plurality of interconnects225is formed in the dielectric layers220and/or222. The plurality of interconnects225may include embedded interconnects. The plurality of interconnects225is coupled to the plurality of interconnects221and the plurality of interconnects223.

As mentioned above, the passive component250may be a discrete capacitor, such as a multi-layer ceramic capacitor (MLCC). A discrete capacitor may be a means for capacitance. The passive component250may include a dielectric252, a first plurality of electrodes253, a second plurality of electrodes255, a first terminal257and a second terminal259. The first plurality of electrodes253is coupled to the first terminal257. The second plurality of electrodes255is coupled to the second terminal259.

The passive component250is coupled to the second surface of the substrate202. In some implementations, the passive component250may be a land side mounted passive component. However, it is noted that the passive component250may be coupled to the first surface of the substrate202. In such an instance, the passive component205may be a die side mounted passive component.

The passive component250is coupled to the substrate202through solder interconnects (e.g., means for soldering). In particular, the first terminal257of the passive component250is coupled to a first solder interconnect260a, and the second terminal259of the passive component250is coupled to a second solder interconnect260b. The first solder interconnect260ais located in a first cavity of the dielectric layer222, and the second solder interconnect260bis located in a second cavity of the dielectric layer222. The first cavity includes a via225a(e.g., first partial via). The first solder interconnect260ais coupled to the via225athrough a curved surface (e.g. concave surface) of the via225a. The via225ais coupled to an interconnect225c(e.g., pad), which is embedded in the dielectric layer of the substrate202. The second cavity includes a via225b(e.g., second partial via). The second solder interconnect260bis coupled to the via225bthrough a curved surface (e.g. concave surface) of the via225b. The via225bis coupled to an interconnect225d(e.g., pad) that is embedded in the dielectric layer of the substrate202. A cavity that includes a partial via and solder interconnect may have a height that is in a range of 15-80 micrometers (μm). For example, the first cavity that includes the via225aand the first solder interconnect260amay have a height that is in a range of 15-80 micrometers (μm). Examples of cavities are illustrated and described inFIGS. 4A-4E and 5A-5E.

FIG. 2illustrates that the solder interconnects that couple the passive component to the substrate, may be coupled to interconnects that are recessed. The term partial via may mean that the electrically conducting material (e.g., metal, copper) that forms the via does not completely fill the cavity. The curved surface of the via may be a concave surface. The curved surface may be referred as a via dimple. The curvature of the surface of the via may be expressed as the height (HD) of a dimple of the via. In some implementations, the height (HD) of the dimple of the via can be quantified as the difference between the lowest point of the surface of the via and the highest point of the surface of the via. In some implementations, the height (HD) is about 0-50 percent (%) of the height of the dielectric layer220. In some implementations, a cavity that includes a partial via and solder interconnect may have a height that is in a range of 15-80 micrometers (μm). The height (HD) may be about 0-50 percent (%) of the height of the cavity (e.g.,430,431) that includes a partial via and solder interconnect.

There are several technical advantages to the structure and configuration ofFIG. 2. One, forming the solder interconnects in the cavities of the dielectric layer222allows the passive component250to be as close to the surface of the substrate202as possible. By taking away part of the via and the surface pad that would normally be there, a passive component250that is thicker can be mounted to the substrate202. When the passive component250is a capacitor, providing a thicker capacitor means providing a capacitor with a higher capacitance value. In many instances, the thickness of the passive component250is limited by the height of the solder interconnects230that are coupled to the substrate202. In some implementations, when the solder interconnects230have a pitch of about 0.35 millimeters (mm) or less, a passive component250that has a maximum thickness of 110 micrometers (μm) may be coupled to the substrate202. However, different implementations may use solder interconnects230with different pitches and/or passive components with different maximum thicknesses.

Two, forming the solder interconnects in the cavities of the dielectric layer (e.g.,222) means that the solder interconnects are less likely to overflow, contact other connections and/or make unintended joints. Since the solder interconnects (e.g.,260a,260b) are in the cavities, the cavities act as a barrier that may prevent a large portion of the solder interconnects from flowing towards other connections, and thereby preventing unintended connections or joints.

FIG. 2illustrates an example of a structure and/or configuration for securely coupling a passive component to a substrate, while reducing the overall amount of space that the passive component occupies and reducing the likelihood of shorting to occur between the terminals of the passive components. An example of fabricating the device200is illustrated and described in at leastFIGS. 4A-4E.

FIG. 3illustrates another example of a device300that includes a passive component coupled to a substrate. The device300is similar to the device200ofFIG. 2.FIG. 3illustrates that the device300includes a substrate302, the die204and the passive component250. The device300may be an integrated device (e.g., integrated circuit device) and/or an integrated package (e.g., integrated circuit package). The substrate302is similar to the substrate202.

FIG. 3illustrates the passive component250is coupled to the substrate302through solder interconnects. In particular, the first terminal257of the passive component250is coupled to a first solder interconnect360a, and the second terminal259of the passive component250is coupled to a second solder interconnect360b. The first solder interconnect360ais located in a first cavity of the dielectric layer222such that the first solder interconnect360aoccupies a majority (e.g., substantially all) of the cavity, and the second solder interconnect360bis located in a second cavity of the dielectric layer222such that the second interconnect360boccupies a majority (e.g., substantially all) of the cavity. The first solder interconnect360ais coupled to the interconnect225c(e.g., pad), which is embedded in the dielectric layer of the substrate302. The second solder interconnect260bis coupled to the interconnect225d(e.g., pad), which is embedded in the dielectric layer of the substrate302. A cavity that includes the solder interconnect may have a height that is in a range of 15-80 micrometers (μm). For example, the first cavity that includes the first solder interconnect360amay have a height that is in a range of 15-80 micrometers (μm). Examples of cavities that include solder interconnects are illustrated and described inFIGS. 4A-4E and 5A-5E.

FIGS. 2 and 3illustrate a substrate with several metal layers (e.g., M1, M2, M3). The labeling of the metal layers of the substrates is exemplary. Different implementations, may label the metal layers differently. For example, the metal layers may be labeled as M1, M2and M3from top to bottom. In some implementations, the M1and M3metal layers are considered as a top metal layer and a bottom metal layer, respectively, of the substrate. In some implementations, the M1and M3metal layers may be considered the first and last metal layers, respectively, of the substrate.FIGS. 2 and 3illustrate that the passive component250may bypass the top and/or bottom metal layers of the substrate (e.g., may bypass the first and/or last metal layers of the substrate), when the passive component250is coupled to the substrate. For example, the passive component250may be coupled through solder interconnects, to the partial vias and/or metal layer(s) between the top and bottom metal layers of the substrate. In a similar manner, when a passive component is coupled to any of the substrates (e.g.,702,802,902,1002) described in the disclosure, the passive component may bypass the top and/or bottom metal layers of the substrates (e.g.,702,802,902,1002). Thus, the passive component may be coupled to one or more metal layers (e.g., middle metal layers, intermediate metal layers) located between the top and bottom metal layers (e.g., between the first and last metal layers) of the substrate. In the example ofFIGS. 2 and 3, the intermediate metal layer may be M2. If there are N metal layers in a substrate, where N is greater than 2, then M1and N may be the top and bottom metal layers, or vice versa, and the metal layer(s) between M1and N are the middle metal layers and/or intermediate metal layers of the substrate.

FIG. 3illustrates an example of a structure and/or configuration for securely coupling a passive component to a substrate, while reducing the overall amount of space that the passive component occupies and reducing the likelihood of shorting to occur between the terminals of the passive components. The dimensions and advantages that are described for the device200may also apply to the device300. An example of fabricating the device300is illustrated and described in at leastFIGS. 5A-5E.

Exemplary Sequence for Fabricating a Device Comprising Substrate with Surface Mounted Discrete Passive Component

FIG. 4(which includesFIGS. 4A-4E) illustrates an exemplary sequence for providing or fabricating a device that includes a die, a substrate and a passive component coupled to the substrate. In some implementations, the sequence ofFIGS. 4A-4Emay be used to provide or fabricate the device200ofFIG. 2, or any of the devices described in the present disclosure.

Stage 1, as shown inFIG. 4A, illustrates a state after a carrier400and a metal layer401are provided. The metal layer401may include several metal layers. The metal layer401may include a foil layer and/or a seed layer. The foil layer and/or the seed layer may include a copper layer.

Stage 2 illustrates a state after a plurality of interconnects221is formed over carrier400. The plurality of interconnects221may include the metal layer401. In some implementations, a plating process may be used to form the interconnects221over the metal layer401. In some implementations, forming the interconnects may include providing a patterned metal layer over and/or in the metal layer401.

Stage 3 illustrates a state after the dielectric layer220(e.g., first dielectric layer) is formed over the plurality of interconnects221. A lamination process may be used to form the dielectric layer220. However, different implementations may use different processes for forming the dielectric layer220. In addition, different materials may be used for the dielectric layer220.

Stage 4 illustrates a state after several cavities410are formed in the dielectric layer220. An etching process (e.g., photo-etching process) or a laser ablation process may be used to form the cavities410.

Stage 5 illustrates a state after the plurality of interconnects225is formed in the cavities410and over the dielectric layer220. A plating process may be used to form the plurality of interconnects225.

Stage 6, as shown inFIG. 4B, illustrates a state after the dielectric layer222(e.g., second dielectric layer) and the metal layer420are provided over the dielectric layer220. The metal layer420may be a seed layer and/or a foil layer.

Stage 7 illustrates a state after the cavities430,431and432are formed in the dielectric layer222. The cavities430and431have a different size than the cavity432. In this example, the cavities430and431are wider and bigger than the cavity432. The cavities430,431and432travel through the metal layer420and the dielectric layer222. An etching process (e.g., photo-etching process) or a laser ablation process may be used to form the cavities430,431and432.

Stage 8 illustrates a state after a dry film layer440is formed over the metal layer420. In this example, some of the dry film layer440is partially covering the cavities430and431.

Stage 9 illustrates a state after the plurality of interconnects223and225are formed in the dielectric layer222. In particular, the first via225ais partially formed in the cavity430(e.g., first cavity), and the second via225bis partially formed in the cavity431(e.g., second cavity). The term partially formed in the cavity may mean that the plating process has not completely filled the cavity with a metal layer. The first via225aand the second via225beach have a curved surface (e.g. concave surface). Different implementations may have vias with different surface curvature. A plating process may be used to form the plurality of interconnects223and225, the first via225aand the second via225b.

Stage 10, as shown inFIG. 4C, illustrates a state after the dry film layer440has been decoupled from the metal layer420. Stage 10 also illustrates a state where part of the metal layer420has been removed (e.g., through metal etching or seed etching).

Stage 11 illustrates a state after the carrier400has been decoupled from the dielectric layer220, leaving the substrate202, which includes the dielectric layers220and222, the plurality of interconnects221, the plurality of interconnects223, and the plurality of interconnects225.

Stage 12 illustrates a state after the first solder resist layer224and the second solder resist layer226are formed over the substrate202. The first solder resist layer224is formed over a first surface of the substrate202, and the second solder resist layer226is formed over a second surface of the substrate202.

Stage 13, as shown inFIG. 4D, illustrates a state after a mask450is formed over the substrate202. The mask450has openings over the cavities430and431.

Stage 14 illustrates a state after the first solder interconnect260ais provided in the cavity430, and the second solder interconnect260bis provided in the cavity431. In some implementations, the first solder interconnects260aand the second solder interconnects260bare provided through a solder printing process. The first solder interconnects260aand the second solder interconnects260bmay be solder balls.

Stage 15 illustrates a state after the mask450has been decoupled from the substrate202, leaving the first solder interconnects260aand the second solder interconnects260bin the cavities430and431, respectively.

Stage 16 illustrates a state after the passive component250has been coupled to the substrate202. In particular, the first terminal257of the passive component250is coupled to the first solder interconnect260a, and the second terminal259of the passive component250is coupled to the second solder interconnect260b. The first solder interconnect260ais located at least partially in the cavity430, and the second solder interconnect260bis located at least partially in the cavity431. The first solder interconnect260ais coupled to the interconnect225a, and the second interconnect260bis coupled to the interconnect225b. Stage 16 may illustrate a state after a reflow process. Stage 16 illustrates a state where a surface of the passive component250is touching and/or aligned with the second surface of the substrate202.

Stage 17, as shown inFIG. 4E, illustrates a state after the plurality of solder interconnects230(e.g., solder balls) is coupled to the plurality of interconnects223.

Stage 18 illustrates a state after the die204is coupled to the substrate202through the plurality of bump interconnects240and the plurality of solder interconnects242. In some implementations, stage 18 illustrates the device200that includes the substrate202, the die204and the passive component250.

FIGS. 4A-4Eillustrate an example of a sequence for fabricating a device that includes a die, a substrate, and a passive component. Different implementations may use a different process and/or sequence.

Exemplary Sequence for Fabricating a Device Comprising Substrate with Surface Mounted Discrete Passive Component

FIG. 5(which includesFIGS. 5A-5E) illustrates an exemplary sequence for providing or fabricating a device that includes a die, a substrate and a passive component coupled to the substrate. In some implementations, the sequence ofFIGS. 5A-5Emay be used to provide or fabricate the device300ofFIG. 3, or any of the devices described in the present disclosure.

It should be noted that the sequence ofFIGS. 5A-5Emay combine one or more stages in order to simplify and/or clarify the sequence for providing or fabricating the device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted without departing from the spirit of the disclosure.

Stage 8, as shown inFIG. 5B, illustrates a state after a dry film layer440is formed over the metal layer420. In this example, some of the dry film layer440covers the cavities430and431.

Stage 9 illustrates a state after the plurality of interconnects223and225are formed in the dielectric layer222. A plating process may be used to form the plurality of interconnects223and225. When the dry film layer440covers the cavities430and431, it prevents plated vias from being formed in the cavities430and431.

Stage 10, as shown inFIG. 5C, illustrates a state after the dry film layer440has been decoupled from the metal layer420. Stage 10 also illustrates a state where part of the metal layer420has been removed (e.g., through metal etching or seed etching).

Stage 11 illustrates a state after the carrier400has been decoupled from the dielectric layer220, leaving the substrate302, which includes the dielectric layers220and222, the plurality of interconnects221, the plurality of interconnects223, and the plurality of interconnects225.

Stage 12 illustrates a state after the first solder resist layer224and the second solder resist layer226are formed over the substrate302. The first solder resist layer224is formed over a first surface of the substrate302, and the second solder resist layer226is formed over a second surface of the substrate302.

Stage 13, as shown inFIG. 5D, illustrates a state after a mask450is formed over the substrate302. The mask450has openings over the cavities430and431.

Stage 14 illustrates a state after the first solder interconnect360ais provided in the cavity430, and the second solder interconnect360bis provided in the cavity431. In some implementations, the first solder interconnects360aand the second solder interconnects360bare provided through a solder printing process. The first solder interconnects360aand the second solder interconnects360bmay be solder balls.

Stage 15 illustrates a state after the mask450has been decoupled from the substrate302, leaving the first solder interconnects360aand the second solder interconnects360bin the cavities430and431, respectively.

Stage 16 illustrates a state after the passive component250has been coupled to the substrate302. In particular, the first terminal257of the passive component250is coupled to the first solder interconnect360a, and the second terminal259of the passive component250is coupled to the second solder interconnect360b. The first solder interconnect360ais located in the cavity430, and the second solder interconnect360bis located in the cavity431. The first solder interconnect360ais coupled to the interconnect225c, and the second interconnect360bis coupled to the interconnect225d. Stage 16 may illustrate a state after a reflow process. Stage 16 illustrates a state where a surface of the passive component250is touching and/or aligned with the second surface of the substrate302.

Stage 17, as shown inFIG. 5E, illustrates a state after the plurality of solder interconnects230(e.g., solder balls) is coupled to the plurality of interconnects223.

Stage 18 illustrates a state after the die204is coupled to the substrate302through the plurality of bump interconnects240and the plurality of solder interconnects242. In some implementations, stage 18 illustrates the device300that includes the substrate302, the die204and the passive component250.

Exemplary Flow Diagram of a Method for Fabricating a Device Comprising Substrate with Surface Mounted Discrete Passive Component

In some implementations, fabricating a device that includes a substrate and a passive component includes several processes.FIG. 6illustrates an exemplary flow diagram of a method600for providing or fabricating a device that includes a substrate and a passive component. In some implementations, the method600ofFIG. 6may be used to provide or fabricate the device ofFIG. 2described in the present disclosure. However, the method600may be used to provide or fabricate any of the devices (e.g.,200,300,700,800,900,1000) described in the disclosure.

It should be noted that the sequence ofFIG. 6may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating a device. In some implementations, the order of the processes may be changed or modified.

The method provides (at605) a carrier (e.g.,400), a dielectric layer (e.g.,220) that includes interconnects (e.g.,221). Stages 1-3 ofFIG. 4A, illustrates an example of a carrier, a dielectric layer that includes interconnects. In some implementations, providing the carrier, the dielectric layer and the interconnects may also include providing a core layer and interconnects in the core layer.

The method forms (at610) interconnects (e.g.,225) in and over the dielectric layer (e.g.,220). One or more cavities may be formed in the dielectric layer and a plating process may be used to form the interconnects. The cavities may be formed using an etching process or laser process. Forming interconnects may include providing a patterned metal layer over and/or in the dielectric layer. Stages 4 and 5 ofFIG. 4A, illustrate an example of interconnects being formed in and over a dielectric layer.

The method forms (at615) another dielectric layer (e.g.,222) over the dielectric layer (e.g.,220) and the interconnects. Different implementations may use different processes for forming the dielectric layer. For example, a lamination process may be used to form the dielectric layer. Stage 6 ofFIG. 4A, illustrates an example of another dielectric layer (e.g., second dielectric layer) being formed over a dielectric layer.

The method forms (at620) cavities (e.g.,430,431,432) in the another dielectric layer (e.g.,222) and forms interconnects (e.g.,225.225a,225b) in and over the another dielectric layer (e.g., second dielectric layer). Forming the interconnects may include providing a dry film layer. A plating process may be used to form the interconnects. The cavities may be formed using an etching process or laser process. Forming interconnects may include providing a patterned metal layer over and/or in the dielectric layer. Some of the cavities may be partially filled or unfilled. Once the interconnects have been formed, the dry film layer may be decoupled. Stages 7-10 ofFIGS. 4B and 4C, illustrate an example of cavities and interconnects being formed in and over a dielectric layer.

The method decouples (at625) the carrier (e.g.,400) from the dielectric layer (e.g.,220). Decoupling the carrier may include removing (e.g., grinding out, etching out) the carrier (e.g.,400) from the dielectric layer, leaving the substrate (e.g.,202,302). In some implementations, decoupling the carrier from the dielectric layer may be performed in several steps. Stage 11 ofFIG. 4C, illustrates an example of a substrate after the carrier has been removed.

The method provides (at630) solder resist layers (224,226) over the dielectric layers. Stage 12 ofFIG. 4Cillustrates an example of providing solder resist layers.

The method provides (at635) solder interconnects in one or more cavities of the dielectric layer of the substrate. In some implementations, a solder printing process is used to provide the solder interconnects in the cavities. In some implementations, a mask is used in the solder printing process. Stages 13-15 ofFIG. 4Dillustrate an example of providing solder interconnects in cavities of a dielectric layer of the substrate. The method also couples (at635) a passive component (e.g.,250,950) to the substrate through the solder interconnects (e.g.,260a,260b,360a,360b) in the cavities of the dielectric layer. In some implementations, coupling the passive component to the substrate include a reflow process. Stage 16 ofFIG. 4Dillustrates an example of a state after a passive component has been coupled to a substrate.

The method couples (at640) solder interconnects (e.g.,230) to the substrate (e.g.,202,302). Stage 17 ofFIG. 4Eillustrates a state after solder interconnects (e.g., solder balls) have been coupled to a substrate.

The method couples (at645) a die (e.g.,204) to the substrate. In some implementations, the die is coupled to the substrate through a plurality of interconnects. Stage 18 ofFIG. 4Eillustrates a state after a die is coupled to a substrate.

The method600ofFIG. 6may be applicable to any of the devices described in the disclosure, including the devices300,700,800,900and/or1000.

Exemplary Devices Comprising a Substrate with Surface Mounted Discrete Passive Component

FIG. 7illustrates another example of a device700that includes a passive component coupled to the substrate. The device700is similar to the device200ofFIG. 2.FIG. 7illustrates that the device700includes a substrate702, the die204and the passive component250. The device700may be an integrated device (e.g., integrated circuit device) and/or an integrated package (e.g., integrated circuit package). The substrate702may be similar to the substrate202. The substrate702includes the plurality of interconnects721, the plurality of interconnects723, and the plurality of interconnects225.

FIG. 7illustrates that the passive component250is located over the same surface of the substrate702as the die204. The passive component250is coupled to the substrate702through solder interconnects. In particular, the first terminal257of the passive component250is coupled to the first solder interconnect260a, and the second terminal259of the passive component250is coupled to the second solder interconnect260b. The first solder interconnect260ais located in a first cavity of the dielectric layer222, and the second solder interconnect260bis located in a second cavity of the dielectric layer222. The first cavity includes the via225a(e.g., first partial via). The first solder interconnect260ais coupled to the via225athrough a curved surface (e.g. concave surface) of the via225a. The via225ais coupled to an interconnect225c(e.g., pad), which is embedded in the dielectric layer of the substrate702. The second cavity includes a via225b(e.g., second partial via). The second solder interconnect260bis coupled to the via225bthrough a curved surface (e.g. concave surface) of the via225b. The via225bis coupled to an interconnect225d(e.g., pad) that is embedded in the dielectric layer of the substrate702. A cavity that includes a partial via and solder interconnect may have a height that is in a range of 15-80 micrometers (μm). For example, the first cavity that includes the via225aand the first solder interconnect260amay have a height that is in a range of 15-80 micrometers (μm).

FIG. 8illustrates another example of a device800that includes a passive component coupled to the substrate. The device800is similar to the device700ofFIG. 7and the device200ofFIG. 2.FIG. 8illustrates that the device800includes a substrate802, the die204and the passive component250. The device800may be an integrated device (e.g., integrated circuit device) and/or an integrated package (e.g., integrated circuit package). The substrate802may be similar to the substrate702and the substrate202. The substrate802includes the plurality of interconnects721, the plurality of interconnects723, and the plurality of interconnects225.

FIG. 8illustrates that the passive component250is located over the same surface of the substrate702as the die204. The passive component250is coupled to the substrate702through solder interconnects. In particular, the first terminal257of the passive component250is coupled to a first solder interconnect360a, and the second terminal259of the passive component250is coupled to a second solder interconnect360b. The first solder interconnect360ais located in a first cavity of the dielectric layer222such that the first solder interconnect360aoccupies a majority (e.g., substantially all) of the cavity, and the second solder interconnect360bis located in a second cavity of the dielectric layer222such that the second interconnect360boccupies a majority (e.g., substantially all) of the cavity. The first solder interconnect360ais coupled to the interconnect225c(e.g., pad), which is embedded in the dielectric layer of the substrate702.

The second solder interconnect260bis coupled to the interconnect225d(e.g., pad), which is embedded in the dielectric layer of the substrate202. A cavity that includes the solder interconnect may have a height that is in a range of 15-80 micrometers (μm). For example, the first cavity that includes the first solder interconnect360amay have a height that is in a range of 15-80 micrometers (μm).

Different implementations may use different types of substrate. In some implementations, the substrate may include a core layer.

Exemplary Devices Comprising a Core Substrate with Surface Mounted Discrete Passive Component

FIG. 9illustrates a profile view of a device900that includes a substrate902, a die204, a passive component250, and a passive component950. The device900may be an integrated device (e.g., integrated circuit device) and/or an integrated package (e.g., integrated circuit package).

The substrate902may be a core substrate. The substrate902includes a core layer920, a dielectric layer922, a dielectric layer924, a dielectric layer926, a dielectric layer928, a first solder resist layer224, a second solder resist layer226, a plurality of interconnects921, a plurality of interconnects923, a plurality of interconnects925, a plurality of interconnects927and a plurality of interconnects929.

The core layer920may include different dielectric materials, such a silicon, glass, quartz, epoxy, or combinations thereof. The dielectric layers922,924,926and928may be made of the same or different material. Materials for the dielectric layers922,924,926and928may include dry film, such as Ajinomoto build-up film (ABF) and/or prepreg (PPG). The PPG may include glass fibers with resin. Different implementations may include different numbers of dielectric layers. The dielectric layers922and924may be considered as one dielectric layer. Similarly, the dielectric layers926and928may be considered as one dielectric layer.

The plurality of interconnects921may include traces and/or pads. The plurality of interconnects921are formed about a first surface of the substrate902. For example, the plurality of interconnects921may be formed over the first surface of the substrate902and/or embedded in the first surface of the substrate902. The first surface of the substrate201may be a first planar surface that faces the die204.

The die204is coupled to the substrate902through a plurality of bump interconnects240and a plurality of solder interconnects242. For example, the die204may be coupled to the plurality of interconnects921through the plurality of bump interconnects240and the plurality of solder interconnects242.

The plurality of interconnects923may include traces and/or pads. The plurality of interconnects923are formed about a second surface of the substrate902. For example, the plurality of interconnects923may be formed over the second surface of the substrate902and/or embedded in the second surface of the substrate902. The second surface of the substrate902may be a second planar surface that faces away from the die204. The second surface of the substrate902may be a surface that is opposite to the first surface of the substrate902.

The plurality of interconnects925may include traces, pads and/or vias. The plurality of interconnects925are formed in the dielectric layers926and928of the substrate902. The plurality of interconnects929may include traces, pads and/or vias. The plurality of interconnects929are formed in the dielectric layers922and924of the substrate902. The plurality of interconnects927may include vias. The vias of the plurality of interconnects927may have angled walls. The plurality of interconnects927is formed in the core layer of920of the substrate902.

FIG. 9illustrates that the passive component250is coupled to the substrate902through solder interconnects. In particular, the first terminal257of the passive component250is coupled to a first solder interconnect260a, and the second terminal259of the passive component250is coupled to a second solder interconnect260b. The first solder interconnect260ais located in a first cavity of the dielectric layer928, and the second solder interconnect260bis located in a second cavity of the dielectric layer928. The first cavity includes a via925a(e.g., first partial via). The first solder interconnect260ais coupled to the via925athrough a curved surface (e.g. concave surface) of the via925a. The via925ais coupled to an interconnect925c(e.g., pad), which is embedded in the dielectric layer of the substrate902. The second cavity includes a via925b(e.g., second partial via). The second solder interconnect260bis coupled to the via925bthrough a curved surface (e.g. concave surface) of the via925b. The via925bis coupled to an interconnect925d(e.g., pad) that is embedded in the dielectric layer of the substrate902. A cavity that includes a partial via and solder interconnect may have a height that is in a range of 15-80 micrometers (μm). For example, the first cavity that includes the via925aand the first solder interconnect260amay have a height that is in a range of 15-80 micrometers (μm).

FIG. 9also illustrates that the passive component950is coupled to the substrate902through solder interconnects. The passive component950may be similar to the passive component250, including having the same or similar components. The first terminal957of the passive component950is coupled to a first solder interconnect360a, and the second terminal959of the passive component950is coupled to a second solder interconnect360b. The first solder interconnect360ais located in a first cavity of the dielectric layer924such that the first solder interconnect360aoccupies a majority (e.g., substantially all) of the cavity, and the second solder interconnect360bis located in a second cavity of the dielectric layer924such that the second interconnect360boccupies a majority (e.g., substantially all) of the cavity. The first solder interconnect360ais coupled to the interconnect929c(e.g., pad), which is embedded in the dielectric layer of the substrate902. The second solder interconnect260bis coupled to the interconnect929d(e.g., pad), which is embedded in the dielectric layer of the substrate902. A cavity that includes the solder interconnect may have a height that is in a range of 15-80 micrometers (μm). For example, the first cavity that includes the first solder interconnect360amay have a height that is in a range of 15-80 micrometers (μm).

FIG. 10illustrates another example of a device1000that includes passive components coupled to the substrate. The device1000is similar to the device900ofFIG. 9.FIG. 10illustrates that the device1000includes a substrate1002, the die204, the passive component250and the passive component950. The device1000may be an integrated device (e.g., integrated circuit device) and/or an integrated package (e.g., integrated circuit package). The substrate1002is similar to the substrate902. The substrate1002includes a plurality of interconnects1027formed in the core layer920. The plurality of interconnects1027may include vias. The vias of the plurality of interconnects1027have approximately vertical walls.

FIG. 10illustrates that the passive component950is coupled to the substrate1002through solder interconnects. In particular, the first terminal957of the passive component250is coupled to a first solder interconnect260a, and the second terminal959of the passive component950is coupled to a second solder interconnect260b. The first solder interconnect260ais located in a first cavity of the dielectric layer924, and the second solder interconnect260bis located in a second cavity of the dielectric layer924. The first cavity includes a via929a(e.g., first partial via). The first solder interconnect260ais coupled to the via929athrough a curved surface of the via929a. The via929ais coupled to an interconnect929c(e.g., pad), which is embedded in the dielectric layer of the substrate1002. The second cavity includes a via929b(e.g., second partial via). The second solder interconnect260bis coupled to the via929bthrough a curved surface of the via929b. The via929bis coupled to an interconnect929d(e.g., pad) that is embedded in the dielectric layer of the substrate1002. A cavity that includes a partial via and solder interconnect may have a height that is in a range of 15-80 micrometers (μm). For example, the first cavity that includes the via929aand the first solder interconnect260amay have a height that is in a range of 15-80 micrometers (μm).

FIG. 10illustrates that the passive component250is coupled to the substrate1002through solder interconnects. The first terminal257of the passive component250is coupled to a first solder interconnect360a, and the second terminal259of the passive component250is coupled to a second solder interconnect360b. The first solder interconnect360ais located in a first cavity of the dielectric layer928such that the first solder interconnect360aoccupies a majority (e.g., substantially all) of the cavity, and the second solder interconnect360bis located in a second cavity of the dielectric layer928such that the second interconnect360boccupies a majority (e.g., substantially all) of the cavity. The first solder interconnect360ais coupled to the interconnect925c(e.g., pad), which is embedded in the dielectric layer of the substrate1002. The second solder interconnect260bis coupled to the interconnect925d(e.g., pad), which is embedded in the dielectric layer of the substrate1002. A cavity that includes the solder interconnect may have a height that is in a range of 15-80 micrometers (μm). For example, the first cavity that includes the first solder interconnect360amay have a height that is in a range of 15-80 micrometers (μm).

FIGS. 9 and 10illustrate that more than one passive component may be coupled to a substrate. In some implementations, a first passive component (e.g.,250,950) may be coupled to a first surface of the substrate and a second passive component (e.g.,250,950) may be coupled to a second surface of the substrate. However, different implementations may have different arrangements of the passive components coupled to a substrate. For example, more than one passive component may be coupled to a surface of the substrate. The sequence ofFIGS. 4 and/or 5may be used to fabricate the device ofFIGS. 9 and 10.

Exemplary Electronic Devices

FIG. 11illustrates various electronic devices that may be integrated with any of the aforementioned device, integrated device, integrated circuit (IC) package, integrated circuit (IC) device, semiconductor device, integrated circuit, die, interposer, package or package-on-package (PoP). For example, a mobile phone device1102, a laptop computer device1104, a fixed location terminal device1106, a wearable device1108, or automotive vehicle1110may include a device1100as described herein. The device1100may be, for example, any of the devices and/or integrated circuit (IC) packages described herein. The devices1102,1104,1106and1108and the vehicle1110illustrated inFIG. 11are merely exemplary. Other electronic devices may also feature the device1100including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the components, processes, features, and/or functions illustrated inFIGS. 2-3, 4A-4E, 5A-5E, and/or6-11may be rearranged and/or combined into a single component, process, feature or function or embodied in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from the disclosure. It should also be noted FIGS.FIGS. 2-3, 4A-4E, 5A-5E, and/or6-11and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations,FIGS. 2-3, 4A-4E, 5A-5E, and/or6-11and its corresponding description may be used to manufacture, create, provide, and/or produce devices and/or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipating device and/or an interposer.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another—even if they do not directly physically touch each other. It is further noted that the term “over” as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (1) the first component is over the second component, but not directly touching the second component, (2) the first component is on (e.g., on a surface of) the second component, and/or (3) the first component is in (e.g., embedded in) the second component. The term “about ‘value X’”, or “approximately value X”, as used in the disclosure shall mean within 10 percent of the ‘value X’. For example, a value of about 1 or approximately 1, would mean a value in a range of 0.9-1.1.

In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a redistribution metal layer, and/or an under bump metallization (UBM) layer. In some implementations, an interconnect is an electrically conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal, ground or power). An interconnect may be part of a circuit. An interconnect may include more than one element or component.