Semiconductor devices and methods for forming the same

A semiconductor device and a method for forming the same are provided. The method includes forming a patterned mask on a substrate, wherein the patterned mask includes a pad oxide layer and a silicon nitride layer over the pad oxide layer. The method also includes forming a trench in the substrate by performing a first etching process on the substrate through an opening of the patterned mask and forming a dielectric material layer in the trench, in the opening, and on the patterned mask. The method further includes performing a planarization process to remove the dielectric material layer outside of the trench, and performing a heat treatment process to form an oxidized portion at the interface of the pad oxide layer and the substrate and adjacent to the dielectric material layer.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to semiconductor devices, and in particular to isolation structures of semiconductor devices and methods for forming the same.

Description of the Related Art

In general, a portion of the semiconductor device is formed in a substrate, and active regions of the semiconductor device are isolated by isolation structures formed in the substrate. As the size of semiconductor devices continues to shrink and device density continues to increase, the problems of surface roughness and the “bird's beak effect,” which is caused by the conventional local oxidation of silicon (LOCOS) isolation technology, have become increasingly non-negligible. Therefore, shallow trench isolation (STI) technology has become a commonly used isolation technique for semiconductor devices with features below 0.25 micrometers.

Although existing isolation structures of semiconductor devices and methods for forming the same have been adequate for their intended purposes, they have not been entirely satisfactory in all respects. Therefore, up to the present, there are still some problems that can be solved in the isolation technologies of semiconductor devices.

BRIEF SUMMARY OF THE INVENTION

Embodiments of shallow trench isolation structures of semiconductor devices and methods for forming the same are provided. To overcome the problems of divots, which are easily formed at edges of an isolation structure and caused by over etching during an etching process for removing additional materials to form the isolation structure, a heat treatment process is performed before removing a patterned mask, which is used to form a trench in a substrate, so that an additional oxidized portion is formed at the edges of the isolation structure and a surface portion of a gate oxide layer formed at a junction of the isolation structure and an active region can be smooth. As a result, gate oxide integrity (GOI) of the gate oxide layer can be increased, and the probability of occurrence of point discharge and electrical breakdown can be decreased. The efficiency and reliability of the semiconductor devices are thereby increased.

Some embodiments of the disclosure provide a method for forming a semiconductor device. The method includes forming a patterned mask on a substrate, wherein the patterned mask includes a pad oxide layer and a silicon nitride layer over the pad oxide layer. The method also includes forming a trench in the substrate by performing a first etching process on the substrate through an opening of the patterned mask and forming a dielectric material layer in the trench, in the opening, and on the patterned mask. The method further includes performing a planarization process to remove the dielectric material layer outside of the trench and performing a heat treatment process to form an oxidized portion at an interface of the pad oxide layer and the substrate and adjacent to the dielectric material layer.

Some embodiments of the disclosure provide a semiconductor device. The semiconductor device includes an isolation structure disposed in a substrate. The semiconductor device also includes a gate oxide layer disposed on the substrate and a portion of the isolation structure, wherein the gate oxide layer has an extension portion at an edge of the isolation structure. The semiconductor device further includes a gate electrode layer disposed on the gate oxide layer and the isolation structure.

DETAILED DESCRIPTION OF THE INVENTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first component over or on a second component in the description that follows may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, such that the first and second components may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described below. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method. In the prior art, since the size and depth of the recess at the edges of the isolation structure is too large, the portion of the gate oxide layer formed on the recess is thinner than the portion of the gate oxide layer formed on the semiconductor substrate, such that the gate electrode layer is too close to the semiconductor substrate at the edges of the isolation structure. Moreover, since the surfaces of the gate oxide layer and the gate electrode layer in the recess are too curved and not smooth, some problems, for example, point discharge, electrical breakdown effects and short circuits, may be caused easily. The embodiments of the present disclosure can overcome the above-mentioned problems, so that the efficiency and reliability of the semiconductor devices can be increased.

FIG. 1Ais a top view of a comparative semiconductor device100aor a semiconductor device100baccording to some embodiments.FIGS. 1B to 1Care cross-sectional views illustrating an exemplary sequential forming process of the comparative semiconductor device100a.FIG. 1C′ is a partial enlarged view of region A ofFIG. 1C.

As shown inFIG. 1A, active regions120of the comparative semiconductor device100ainclude source regions117and drain regions119, and an isolation structure111is located between two adjacent active regions120to isolate and surround two active regions120. A gate structure130of the comparative semiconductor device100aincludes a gate oxide layer113and a gate electrode layer115over the gate oxide layer113(as shown inFIG. 1C). The gate structure130is located between the source region117and the drain region119of the active region120and straddle the active regions120and the isolation structure111.FIG. 1Cis an exemplary cross sectional view of the comparative semiconductor device100aalong line1-1ofFIG. 1A.

As shown inFIG. 1B, the isolation structure111is formed in a substrate101, wherein the substrate101is a semiconductor substrate. The isolation structure111of the comparative semiconductor device100ahas recesses112shown obviously at its edges. The formation of recesses112is that when a patterned mask (not shown) on the substrate101, which is used to form a trench of the isolation structure111, is removed, an isotropic etching process is used. Since the materials of the isolation structure111and a pad oxide layer of the patterned mask are similar, and the pad oxide layer is thinner than the isolation structure111, the over-etching phenomenon can easily happen at the edges of the isolation structure111, where the difference of the thicknesses is the most obvious.

As shown inFIGS. 1C and 1C′, the gate oxide layer113and the gate electrode layer115are formed sequentially on the isolation structure111and the substrate101. Since the isolation structure111has recesses112at its edges, the thickness t2of the gate oxide layer113on the recesses112of the isolation structure111is less than the thickness t1of the gate oxide layer113on the substrate101. In some cases, the ratio of t2to t1is between 0.7 and 0.85. Since a portion of the gate oxide layer113formed on the recesses112is thinner than another portion of the gate oxide layer113formed on the substrate101, the gate electrode layer115is too close to the substrate101at the edges of the isolation structure111. Moreover, since the surfaces of the gate oxide layer113and the gate electrode layer115in the recesses112are too curved and not smooth, some problems, for example, point discharge, the electrical breakdown effect, and short circuits, may be caused easily. Furthermore, as the size of semiconductor devices continues to shrink, the efficiency and reliability of the semiconductor devices are decreased incredibly because of the above-mentioned problems.

FIGS. 2A to 2Iare cross-sectional views illustrating an exemplary sequential forming process of a semiconductor device100bin accordance with some embodiments of the present disclosure.FIG. 2Iis an exemplary cross sectional view of the semiconductor device100balong line1-1ofFIG. 1Ain accordance with some embodiments of the present disclosure. The semiconductor device100bincludes a substrate201. In some embodiments, the substrate201may be made of silicon or other semiconductor materials. Alternatively, the substrate201may include other elementary semiconductor materials such as germanium. In some embodiments, the substrate201is made of a compound semiconductor such as silicon carbide, gallium nitride, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the substrate201is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the substrate201includes a semiconductor-on-insulator (SOI) substrate. In some embodiments, the substrate201includes an epitaxial layer. For example, the substrate201has an epitaxial layer overlying a bulk semiconductor.

As shown inFIG. 2A, a pad oxide layer203and a silicon nitride layer205are formed sequentially on the substrate201, in accordance with some embodiments. In some embodiments, the silicon nitride layer205may be replaced by silicon oxynitride or other similar materials. In some embodiments, the pad oxide layer203is formed by using a thermal oxidation process or other applicable processes. In some embodiments, the silicon nitride layer205is formed by using a chemical vapor deposition (CVD) process or other applicable processes. The pad oxide layer203is used as a buffer layer for releasing the stress between the silicon nitride layer205and the substrate201, and the silicon nitride layer205is used as a stop layer for a planarization process which will be performed later on.

As shown inFIG. 2B, a patterned photoresist layer207is formed on the silicon nitride layer205, in accordance with some embodiments. An isolation structure will be formed subsequently on the region which is not covered by the patterned photoresist layer207(Such as the region of the isolation structure211shown inFIG. 1A), and the region which is covered by the patterned photoresist layer207will become an active region in the following steps (Such as the active region120shown inFIG. 1A). Then, the pad oxide layer203and the silicon nitride layer205are patterned by utilizing the patterned photoresist layer207as a mask, so that a patterned mask204is formed as shown inFIG. 2C. The patterned mask204includes the pad oxide layer203and the silicon nitride layer205, and the patterned mask204will be used in the following etching process to form a trench in the substrate201.

As shown inFIGS. 2C and 2D, a trench202′ is formed in the substrate201by performing a first etching process300on the substrate201through an opening202of the patterned mask204, and the trench202′ inside the substrate201and the opening202of the patterned mask204compose a trench206as shown inFIG. 2D, in accordance with some embodiments. In some embodiments, the first etching process300includes a wet etching process, a dry etching process or other applicable processes. In some embodiments, the dry etching process includes a plasma etching process using a fluorine-containing gas, a chlorine-containing gas, or other applicable gases. In some embodiments, the depth of the trench206is smaller than 0.5 microns, but it is not limited thereto. The depth of the trench206may be adjusted according to the size of the semiconductor device.

Next, as shown inFIG. 2E, a dielectric material layer209is formed in the trench206(i.e. in the trench202′ and the opening202) and on the patterned mask204. In some embodiments, the dielectric material layer209is made of silicon oxide, silicon nitride, silicon oxynitride or another applicable dielectric material. In some embodiments, the material used to form the dielectric material layer209is different from the material used to form the pad oxide layer203. In some embodiments, the dielectric material layer209is formed by using a chemical vapor deposition process, an atmospheric pressure chemical vapor deposition (APCVD) process, a high density plasma chemical vapor deposition (HDPCVD) process or other applicable process.

As shown inFIGS. 2E and 2F, a planarization process400is performed by using the silicon nitride layer205as a stop layer in order to remove a portion of the dielectric material layer209outside of the trench206, that is, the portion of the dielectric material layer209on the silicon nitride layer205, so that the top surface of the dielectric material layer209in the trench206is level with the top surface of the silicon nitride layer205, as shown inFIG. 2F, in accordance with some embodiments. In some embodiments, the planarization process400may further remove a portion of the silicon nitride layer205. In some embodiments, the planarization process400may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, another applicable process, or a combination thereof.

After performing the planarization process400, as shown inFIG. 2F, a heat treatment process500is performed by introducing oxygen gas into the semiconductor device100b, in accordance with some embodiments. The oxygen gas is diffused into the vertical interface among the dielectric material layer209, the substrate201and the pad oxide layer203to form oxidized portions210at the interface between the pad oxide layer203and the substrate201in the horizontal direction, as shown inFIG. 2G. The oxidized portions210are adjacent to the dielectric material layer209at the sidewalls of the trench206(as shown inFIG. 2G). The oxidized portions210are formed on both sides of the edges of the dielectric material layer209in the trench206, and the oxidized portions210are similar to the bird's beak structure caused by the local oxidation of silicon (LOCOS) isolation technology. In some embodiments, the heat treatment process500is operated at a temperature in a range from about 950° C. to about 1050° C. In some embodiments, the duration of the heat treatment process500is in a range from about 15 minutes to about 40 minutes. It is worth noting that the shape and thickness of the oxidized portions210may be controlled by the temperature and time of the heat treatment process500.

Afterwards, as shown inFIG. 2G, a second etching process600is performed in order to remove the silicon nitride layer205, the pad oxide layer203, a portion of the dielectric material layer209and a portion of the oxidized portions210, so that a top surface201aof the substrate201is exposed, and an isolation structure211with sharp portions, which is similar to a bird's beak, at it's both sides is formed as shown inFIG. 2H, in accordance with some embodiments. In some embodiments, the second etching process600includes a wet etching process, a dry etching process or another applicable process. In some embodiments, the wet etching process may use a solution of phosphoric acid to perform a one-step process. In other embodiments, the wet etching process may use solutions of phosphoric acid and hydrofluoric acid to perform a two-step process. In some embodiments, the isolation structure211is a shallow trench isolation (STI) structure whose depth is smaller than 0.5 microns.

Next,FIG. 2H′ is a partial enlarged view of region B ofFIG. 2Hin accordance with some embodiments of the present disclosure. As shown inFIG. 2H′, the isolation structure211has recesses212at the top of both of its sides close to the substrate201. In some embodiments, the vertical distance d between the bottom surface of the recesses212and the top surface201aof the substrate201is less than about 50 Å. It is worth noting that, the depth of the recesses212at the edges of the isolation structure211of the semiconductor device100binFIG. 2H, which is based on the embodiments of the present disclosure, is smaller than the depth of the recesses112at the edges of the isolation structure111of the comparative semiconductor device100ainFIG. 1B. The additional heat treatment process500performed on the semiconductor device100binstead of the semiconductor device100ais the cause of the shallow recesses212, so that a smoother surface is formed on the semiconductor device100bafter the following second etching process600is performed. In some embodiments, the depth of the recesses212(such as the vertical distance d) may be adjusted by the shape and size of the oxidized portions210through the temperature and time duration of the heat treatment process500. In other embodiments, the value of the vertical distance d is small enough to be negligible, so that the whole top surface of the isolation structure211is substantially flat. In other embodiments, the top surface of the isolation structure211is substantially level with the top surface of the substrate201.

As shown inFIG. 2I, a gate oxide layer213of the gate stack230as shown inFIG. 1Ais formed in the recesses212and on the top surface201aof the substrate201(More specifically, the gate oxide layer213is formed near the upper and lower regions of the top surface201a), and a gate electrode layer215of the gate stack230as shown inFIG. 1Ais formed on the isolation structure211and the gate oxide layer213, in accordance with some embodiments. In some embodiments, the gate oxide layer213and the gate electrode layer215are formed respectively by a thermal oxidation process, chemical vapor deposition process, flowable chemical vapor deposition (FCVD) process, atomic layer deposition (ALD) process, low-pressure chemical vapor deposition (LPCVD) process, plasma enhanced chemical vapor deposition (PECVD) process, another applicable process, or a combination thereof. In some embodiments, the gate oxide layer213may be made of silicon oxide or other dielectric materials with a high dielectric constant (high-k). The high-k dielectric materials may be made of hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, other suitable high-k materials, or a combination thereof. In some embodiments, the gate electrode layer215includes metals or other suitable conductive materials, such as tungsten, copper, nickel, aluminum, tungsten silicide, polysilicon or a combination thereof.

As shown inFIG. 2I, the gate oxide layer213has extension portions213ain the recesses212at both sides of the isolation structure211adjacent to the substrate201. In some embodiments, the distance between the top surface of the extension portions213aand the junction of the isolation structure211and the substrate201in a direction that is perpendicular to the surface of the substrate201is in a range from 130 Å to 500 Å.FIG. 2I′ is a partial enlarged view of region C ofFIG. 2Iin accordance with some embodiments of the present disclosure. In some embodiments, the distance t4between the top surface of the extension portions213aand the junction of the isolation structure211and the substrate201in a direction (for example, Z-axis direction) that is perpendicular to the surface of the substrate201is only slightly less or greater than the thickness t3of the gate oxide layer213on the substrate201. In some embodiments, the ratio of t4to t3is greater than about 0.95. The top surface of the gate oxide layer213above the substrate201and the isolation structure211is smooth and substantially flat due to the formation of the extension portions213a.

Compared to the comparative semiconductor device100awith the semiconductor device100bin some embodiments of the present disclosure, the ratio of the thickness t2of the gate oxide layer113at the edges of the isolation structure111to the thickness t1of the gate oxide layer113on the substrate101of the comparative semiconductor device100aas shown inFIG. 1C′ is less than 0.85. Regarding the semiconductor device100bshown inFIG. 2I′ in some embodiments of the present disclosure, the gate oxide layer213has extension portions213aat the edges of the isolation structure211. The ratio of the distance t4between the top surface of the extension portion213aand the junction of the isolation structure211and the substrate201in the direction that is perpendicular to the surface of the substrate201to the thickness t3of the gate oxide layer213on the substrate201is greater than 0.95, and the top surface of the gate oxide layer213in the embodiments is smoother than the surface of the gate oxide layer113in the comparative examples. There is no obvious recess feature in the isolation structure211of the embodiments, and so that the problems of point discharge, electrical breakdown and short circuits can be avoided. Therefore, the efficiency and reliability of the semiconductor devices according to the embodiments of the present disclosure can be increased.

The method for forming the semiconductor device in some embodiments of the present disclosure comprises forming the oxidized portions at the interface among the dielectric material layer, the substrate and the pad oxide layer by performing the heat treatment process, and the oxidized portions are adjacent to the dielectric material layer on the sidewalls of the trench, before removing the patterned mask. Thus, the thickness of the oxide layer at the edges of the isolation structure formed later on is increased. Then, the formation of the recesses at the edges of the isolation structure caused by the etching process for removing the patterned mask later on is avoided, or the size and depth of the recesses is decreased. Therefore, a gate oxide layer with a flat surface is formed through the following steps in order to improve gate oxide integrity.

In known technology, since the size and depth of the recess at the edges of the isolation structure is too large, the portion of the gate oxide layer formed on the recess is thinner than the portion of the gate oxide layer formed on the semiconductor substrate, such that the gate electrode layer is too close to the semiconductor substrate at the edges of the isolation structure. Moreover, in known technology, since the surfaces of the gate oxide layer and the gate electrode layer in the recess are too curved and are not smooth, some problems may easily arise, including point discharge, electrical breakdown, and short circuits. The embodiments of the present disclosure can solve the above-mentioned problems, so that the efficiency and reliability of the semiconductor devices can be increased.