Semiconductor package and method of manufacturing the same which reduces warpage

A semiconductor package and method of producing the same has a semiconductor die having a first face and a second face. A coating material is coupled to the second face of the semiconductor die. A substrate having a cavity is provided wherein the semiconductor die is placed within the cavity. An encapsulant is used to encapsulate the second face of the semiconductor die placed in the cavity. Connection members are provided to couple the semiconductor die and the substrate in order to transfer signals between the semiconductor die and the substrate. Terminal members are couple to the substrate to connect the semiconductor package to an external device. In the semiconductor package, a thermal expansion coefficient of the coating material C and a thermal expansion coefficient of the encapsulant E should be approximately equal in value in order to limit the problems associated with warpage.

FIELD OF THE INVENTION

This invention relates to semiconductor devices and, more specifically, to a semiconductor package and method of manufacturing the same which reduces warpage during the cool down phase of the manufacturing process.

BACKGROUND OF THE INVENTION

In general, a semiconductor package is fabricated using a substrate such as lead frame, printed circuit board, circuit film, circuit tape, or the like. A semiconductor die is coupled to the substrate and packaged to be airtight to protected the semiconductor die from the outer environment as well as to enable the semiconductor package to be electrically connected to external devices.

Namely, each semiconductor package has the structure enabling the semiconductor package to protect the semiconductor die as well as to be mounted on an external device, for example a mother board, or the like. In order to complete such a structure, processes of various steps are required.

Generally speaking, there is Post Mold Cure (PMC) or reflow requiring thermal treatment in the processes of the various steps. On carrying out the PMC or reflow, a process temperature is increased up to a predetermined temperature, and then gradually decreased down to a room temperature.

In a general semiconductor package fabricating method, a face on which an integrated circuit of a semiconductor die is formed should be encapsulated with an encapsulant. In the PMC or reflow process, when the semiconductor package is cooled down after heating, a warpage occurs in the semiconductor package due to a heat expansion coefficient difference between the semiconductor die and the encapsulant.

Namely, the semiconductor die and the encapsulant have different coefficients of thermal expansion (CTE). The difference in the coefficients of thermal expansion brings about a warpage due to the difference of shrinkage on cooling-down.

Unfortunately, the warpage of the semiconductor package causes the following problems or disadvantages. A total height of the semiconductor package increases. Accordingly, a height of the semiconductor package may increases anywhere from 10 to 20% more than its original height due to warpage. Thus, a thin semiconductor package is no more. Moreover, when the semiconductor package having the warpage is mounted on an external device, it is difficult to mount the semiconductor package on the external device properly.

Therefore, a need existed to provide a device and method to overcome the above problem.

SUMMARY OF THE INVENTION

A semiconductor package and method of producing the same has a semiconductor die having a first face and a second face. A coating material is coupled to the second face of the semiconductor die. A substrate having a cavity is provided wherein the semiconductor die is placed within the cavity. An encapsulant is used to encapsulate the second face of the semiconductor die placed in the cavity. Connection members are provided to couple the semiconductor die and the substrate in order to transfer signals between the semiconductor die and the substrate. Terminal members are couple to the substrate to connect the semiconductor package to an external device. In the semiconductor package, a thermal expansion coefficient of the coating material C and a thermal expansion coefficient of the encapsulant E should be approximately equal in value in order to limit the problems associated with warpage.

Common reference numerals are used throughout the drawings and detailed descriptions to indicate like elements.

DETAILED DESCRIPTION

Referring toFIG. 1, a cross-sectional view of one embodiment of a semiconductor package according to the present invention is illustrated.

As shown inFIG. 1, a semiconductor package includes a semiconductor die1. On a surface opposite to a integrated circuit forming face is a coating material12. A cavity200is formed in a substrate20. The cavity200is where the semiconductor die1is placed. An encapsulant40is used to encapsulate the integrated circuit forming face of the semiconductor die1lying in the cavity200. Electrically conductive wire5are used to connect electrically the semiconductor die1to the substrate20for signal transfer between the semiconductor die1and substrate20.

The semiconductor die1has bond pads1alocated so as to leave a predetermined interval from an inner face of the cavity200in the substrate20.

There are various forms for the substrate20used for the semiconductor package. The substrate20may be printed circuit board, circuit film, circuit tape, or the like. The materials for the substrate20are not specially restricted. The substrate20is generally constructed with at least two layers of electrical conductive patterns between which an insulating layer21is inserted. In the drawing, the double-layered electrical patterns24and25are shown exemplary. The electrical conductive patterns24and25are electrically connected to each other through via holes26. In the electrical conductive patterns24and25, most areas of the electrical conductive patterns24formed at the attaching face of conductive balls of the substrate20are covered with a solder resist22. Yet, some areas are exposed in part for input/output of electric signals. The exposed areas include areas of bond fingers24aand ball lands24b. Meanwhile, the rest of the area of the electrical conductive patterns24and25formed on the surface of the substrate20, except the areas of the bond fingers24aand ball lands24b, is covered with the resist22, thereby enabling to protect the electrical conductive patterns24and25as well as prevent the respective patterns from electrical short.

The semiconductor package according to the present invention, as shown in the drawing, uses electrically conductive wire5as contact means between the semiconductor die1and substrate20. The electrically conductive wire5is used for exchanging electric signals between the semiconductor die1and substrate20. One end of the electrically conductive wire5is bonded to bond pads1aof the semiconductor die1. The other end of the electrically conductive wire5is bonded to bond fingers24aof the substrate20. The electrically conductive wire5is made of a metal material having electro-conductivity such as one of Au, Al, Cu, and the like. It should be noted that the present invention is not limited to this scope of the metal materials.

Moreover, the ball lands24b, which are the exposed areas of the electrical conductive patterns of the substrate20, play a role in exchanging electrical signals inside the semiconductor package with an external device.

The conductive balls30, as shown in the drawing, are attached to the ball lands24b, respectively. The conductive balls30are made from a conductive metal material. The conductive balls30are generally solder balls. The conductive balls30may be made from electro-conductive materials such as Au, Cu, Al, and the like. It should be noted that the listing of the electro-conductive materials should not be seen as to limit the scope of the present invention. The conductive balls30are attached to the external device by welding when the completed semiconductor package is mounted on the external device or the like, thereby functioning as media connecting the semiconductor package and external device reciprocally.

The integrated circuit formed face of the semiconductor die1and the electrically conductive wires5are protected by the encapsulant40. The encapsulant40is mainly made of non-conductive paste or film, which is coated on the integrated circuit formed face of the semiconductor die1and then hardened by PMC. Besides, the method of fabricating the semiconductor package requires processes of thermal treatment such as reflow and the like as well as PMC. When the thermal treatment processes are carried out, the components of the semiconductor package have different CTE so as to differ in shrinkage as well as the degree of expansion.

The coating material12coated on the face opposite to the integrated circuit formed face of the semiconductor die1is made of a material of which the CTE is equal or similar to that of the encapsulant40. For instance, the coating material12can use the same material of the encapsulant40as well as an epoxy based resin. Moreover, if the CTE of the coating material12is C and the other CTE of the encapsulant40is E, a ratio C/E satisfies preferably the relation of 0.5≦C/E≦2. For instance, when EMC (epoxy mold compound) is used for the encapsulant40, a CTE of EMC is about 26.2 ppm. Therefore, a material satisfying the relation of 0.5≦C/E≦2 is selected for the coating material12.

Referring toFIG. 2, a cross-sectional view of the semiconductor package according to one embodiment of the present invention is illustrated.FIG. 2explains a shrinkage difference using arrows when encapsulant40, semiconductor die1, and coating material12are shrunk after heat expansion.

As shown inFIG. 2, lengths of the arrows indicate the sizes of the shrinkage forces when the coating material12, semiconductor die1, and encapsulant40are shrunk after thermal expansion.

Being relatively lower than CTE of the coating material12or encapsulant40, the semiconductor die1has the degree of shrinkage smaller than that of the coating material12or encapsulant40when being cooled after thermal expansion.

The coating material12and encapsulant40wrapping both faces of the semiconductor die1have CTEs bigger than that of the semiconductor die1so as to have the shrinkage size bigger than that of the semiconductor die1as well.

In this case, the coating material12and encapsulant40wrapping the two faces of the semiconductor die1have the CTE which are almost identical to each other so as to have the similar shrinkage forces. Thus, the shrinkage forces of the coating material12and encapsulant40cancelled each other so as to meet the reciprocal balance. Therefore, there occurs little to no warpage of the semiconductor package.

Namely, as explained in the above description of the present invention, materials having the same or similar CTE are laid on both faces of the semiconductor die1so as to make the shrinkage quantity similar or identical on the cooling step of the thermal treatment process such as PMC or the like. Thus, the warpage of the semiconductor package is prevented, thereby enabling the semiconductor package to maintain the original designed height. Moreover, being made of the metal material having excellent property of thermal-conductivity, the coating material12plays a role in helping heat dissipation of the semiconductor die1as a heat sink.

Moreover, when the semiconductor die1is detached individually from the wafer in order to attach the semiconductor die1to the substrate20after sawing the thin wafer, an ejector pin (not shown in the drawing) pushes the coating material12instead of the semiconductor die1so as to prevent the damage on the semiconductor die1. Namely, the coating material12prevents die scratch or die crack which may be caused by a direct contact between the ejector pin and semiconductor die1.

Referring toFIG. 3, a flowchart of a method of fabricating a semiconductor package according to the present invention is illustrated.

Referring toFIG. 3, in a first step100, back-grinding is carried out on the face opposite to the integrated circuit formed face of the wafer10. The back-grinded face is then coated with the coating material12.

Since the coating material12makes the handling of the wafer10easier, the wafer10is preferably back-grinded thinner than the related art.

In a second step200, sawing is carried out on the coated wafer10so as to divide the coated wafer10into units of individual semiconductor dies1.

In a third step300, a cover tape60is attached to a backside of the substrate20having the cavity200at a center thereof into which the semiconductor die1is inserted.

In a fourth step400, the sawed semiconductor die1is attached to the substrate20having the cavity200.

In a fifth step500, the semiconductor die1is electrically connected to the substrate20. The electrical connection is preferably achieved using conductive wires or bumps.

In a sixth step600, the integrated circuit formed area of the semiconductor die1and the areas of the bond fingers24aof the substrate20are encapsulated with the encapsulant40.

In a seventh step700, the conductive balls30are attached to the ball lands24bof the substrate20, respectively.

In an eighth step800, the cover tape60attached to the backside of the substrate20is removed so as to complete the package.

Thereafter, a process of marking on the coating material12may be carried out in addition.

Referring toFIG. 4AtoFIG. 4H, views of a method of fabricating one embodiment of a semiconductor package according to the present invention are illustrated.

As shown inFIG. 4A, the wafer10is through the back-grinding process. And, illustrated schematically is a state that the coating material12is being coated on the back-grinded face. For reference, in order to fabricate the semiconductor die1, integrated circuit is firstly formed through a fabrication process on the round wafer20made of SiO2crystals.

The wafer10maintains a predetermined thickness when the integrated circuit is formed. The predetermined thickness should be minimized so as to be applied to the respective products, for which grinding is carried out on the face of the wafer10opposite to the integrated circuit formed face.

The coating material12is preferably coated using spin coating, which is not limited in the present invention. One of stencil coating, sputtering, tape attach, plating, and the like can be selectively applied thereto. For the selection of the coating material12, a physical property of the encapsulant40should be considered. As mentioned in the foregoing description, if the CTE of the coating material12is C and the other CTE of the encapsulant40is E, a ratio C/E satisfies preferably the relation of 0.5≦C/E≦2.

As shown inFIG. 4B, the wafer10inFIG. 4Ais sawed so as to divide the semiconductor dies into individual units.

Scribing lines are already formed on the wafer10. In a sawing process, a rotating saw wheel80is moved along the scribing lines so that blades of the saw wheel80divide the respective semiconductor dies1of the wafer10into the individual units.

The integrated circuit is formed at one face of the semiconductor die1divided into each individual unit, and the coating material12is formed at the other face.

As shown inFIG. 4C, the cover tape60is attached to the backside of the substrate20. The cavity200at the central part of the substrate20provides a space in which the semiconductor die1is inserted, and the cover tape60provides an attachment face for the semiconductor die1.

As shown inFIG. 4D, the semiconductor die1is attached to the substrate20. The semiconductor die1fabricated through the first and second steps is inserted in the cavity200of the substrate20, to which the cover tape60is attached in the third step, so as to be attached to the cover tape60.

As shown inFIG. 4E, the bond pads1aof the semiconductor die1and the bond fingers24aof the substrate20are connected each other through the conductive wires5.

As shown inFIG. 4F, encapsulated are the integrated circuit formed area of the semiconductor die1and the areas of the bond fingers24aof the substrate20at which the conductive wires5are installed.

The encapsulant40, as mentioned already, is preferably made of a material of which the CTE is similar to that of the coating material of the semiconductor die1within a 10% error limit.

As shown inFIG. 4G, the conductive balls30are attached to the ball lands24aof the substrate20, respectively.

As shown inFIG. 4H, the cover tape60attached to the backside of the substrate20is removed so as to complete the semiconductor package according to the present invention.

Thereafter, after the cover tape60has been removed, a process (not shown in the drawing) of marking product information on a surface of the coating material12using ink or laser may be carried out in addition.

Referring toFIG. 5andFIG. 6, a cross-sectional view of a semiconductor package according to another embodiment of the present invention and a layout in which air vents are formed on a surface of a substrate are illustrated respectively.

As shown inFIG. 5andFIG. 6, another embodiment of the present invention is shown. This embodiment is similar to the previous embodiment in aspect of using the semiconductor die1coated with a coating material of which heat expansion coefficient is similar to that of the encapsulant40. However, this embodiment is different from the previous embodiment in that air vents29are formed additionally at a surface of the substrate20. The air vents29, as shown in theFIG. 6, are formed by removing portions of the solder resist22coated on the backside of the substrate20like slots.

Arrows inFIG. 5indicate a flow path of the encapsulant40in an encapsulating process. Namely, while the semiconductor die1wire-bonded to the substrate20is placed in a metal mold, the encapsulant40is injected in a direction opposite to that of the integrated circuit formed face of the semiconductor die1so as to surround a circumference of the semiconductor die1. Likewise, when encapsulation is carried out, air contained in the encapsulant40is discharged outside through air vents29.

Accordingly, if the air vents29are formed at the semiconductor package itself, there is no chance for the encapsulant40to penetrate the ball lands24b. Besides, a flow characteristic of the encapsulant40is improved so as to prevent previously poor encapsulation caused by generation of voids and the like.

As shown inFIG. 6, a plurality of air vents29are formed on a top of the substrate20so as to extend long from a die hole25of the substrate20to the circumference like slot figures.

Each of the air vents29forms the slot figure connecting one corner of the die hole25to a closest corner of the substrate20. In the embodiment of the present invention, four air vents29are formed. The number of the air vents29is not limited to four, but can be adjusted in accordance with a quantity of encapsulation.

Moreover, when the encapsulating process is carried out using EMC and the like, the air vents29are formed at the surface of the substrate20so as to provide smooth flow of EMC in the metal mold. Therefore, the present invention enables one to provide uniform encapsulation surface as well as prevent the encapsulant40from penetrating the ball lands24b.