Dual seed semiconductor photodetectors

Dual seed semiconductor photodetectors and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes an optical layer formed on a dual seed semiconductor layer. The dual seed semiconductor layer includes a seed layer and a buffer layer. The seed layer of a first material is formed on an insulating layer over a substrate. The buffer layer is formed on the seed layer. Next, an optical layer of a second material is formed on the buffer layer. The buffer layer includes the first material and the second material. In one embodiment, the first material is silicon. In one embodiment, the second material is germanium.

FIELD

Embodiments of the invention relate generally to the field of microelectronic device manufacturing, and more specifically, to optical components and methods to fabricate thereof.

BACKGROUND

Currently, to fabricate an optical component, e.g., a photodetector, an optical quality germanium (“Ge”) film is deposited directly on a single crystal silicon (“Si”) substrate or on a silicon on isolator (“SOI”) substrate.

FIG. 1Ashows a Ge photodetector film102deposited directly on a Si substrate101to fabricate a photodetector. Lattice mismatch between germanium and silicon produces defects on an interface103between Ge photodetector film102and Si substrate101. As shown inFIG. 1A, Ge photodetector film102is adjacent to substrate101.

FIG. 1Bshows a Ge photodetector film112grown directly on a silicon substrate111through an opening114in a silicon dioxide (“SiO2”) insulating layer113to fabricate a photodetector. As shown inFIG. 1B, Ge photodetector film112over insulating layer113is in direct contact with silicon substrate111through opening114in insulating layer113.

The optical devices, e.g., photodetectors, formed directly on the semiconductor substrate in a separate process occupy the substrate space that may be needed for other devices. Additionally, forming optical devices, e.g., photodetectors, in close proximity to a substrate introduces substantial optical losses. The optical losses may be in an optical waveguide that carries light to the photodetector, because light may be absorbed in the substrate.

Further, to integrate photodetectors grown in separate processes on the separate substrates, with microprocessor and other circuit chips and devices, flip-chip bonding (to bumps), wire bonding, or other packaging solutions are used. Using the flip-chip bonding, wire bonding, or other packaging solutions introduce parasitics that negatively impact on the performance of the photodetector and other circuit devices.

DETAILED DESCRIPTION

In the following description, numerous specific details, such as specific materials, dimensions of the elements, chemical names, etc. are set forth in order to provide thorough understanding of one or more of the embodiments of the present invention. It will be apparent, however, to one of ordinary skill in the art that the one or more embodiments of the present invention may be practiced without these specific details. In other instances, semiconductor fabrication processes, techniques, materials, equipment, etc., have not been described in great details to avoid unnecessarily obscuring of this description. Those of ordinary skill in the art, with the included description, will be able to implement appropriate functionality without undue experimentation.

While certain exemplary embodiments of the invention are described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention, and that this invention is not restricted to the specific constructions and arrangements shown and described because modifications may occur to those ordinarily skilled in the art.

Moreover, inventive aspects lie in less than all the features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention. While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative rather than limiting.

Dual seed semiconductor optical components, e.g., photodetectors, and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes a photodetector layer formed on the dual seed semiconductor layer. The dual seed semiconductor layer includes a seed layer and a buffer layer. The seed layer of a first material is formed on an insulating layer over a substrate. The buffer layer is formed on the seed layer. Next, an optical layer of a second material is formed on the buffer layer. The buffer layer includes the first material and the second material. In one embodiment, the first material is silicon. In one embodiment, the second material is germanium.

FIG. 2is a cross-sectional view200of one embodiment of a dual seed semiconductor photodetector formed directly on an insulating layer. As shown inFIG. 2, photodetector212has an optical layer206formed on dual seed semiconductor layer210, and contacts208. As shown inFIG. 2, dual seed semiconductor layer210of the photodetector212is formed directly on an insulating layer202. Insulating layer202is formed over substrate201, as shown inFIG. 2. In one embodiment, substrate201includes monocrystalline silicon. In alternate embodiments, substrate201may comprise any material, for example silicon, silicon on insulator, and gallium arsenide, which is used to make any of integrated circuits, passive, and active devices. As shown inFIG. 2, substrate201includes front end device region213. Front end device region213contains active and passive devices203, e.g., transistors, capacitors, diodes, inductors, and interconnects, formed on substrate201. Further, front end device region213may include isolation structures, metal contacts, and other device features which are coupled to conductive and interconnects layers (not shown) and contacts (not shown) formed in insulating layer202. Substrate201may include insulating materials that separate active and passive devices203from a conductive layer or layers that are formed on top of them. As shown inFIG. 2, insulating layer202is formed over substrate201. In one embodiment, insulating layer202may be any one, or a combination of, silicon dioxide (e.g., “SiO2”), silicon nitride (e.g., “Si3N4”), polymer, sapphire, high-k dielectric, e.g., high-k oxide, low-k dielectric, e.g., a porous oxide, carbon doped oxides, or other insulating materials. In one embodiment, insulating layer202may contain metal vias and lines. In one embodiment, insulating layer202is an amorphous interlayer dielectric (“ILD”). In one embodiment, insulating layer202is formed over multiple conductive layers and corresponding dielectric layers over substrate201. In one embodiment, the thickness of insulating layer202is at least 1 micron (“μm”). As shown inFIG. 2, dual seed semiconductor layer210includes a thin buffer layer205deposited on a thin seed layer204. In one embodiment, a material of seed layer204is a polycrystalline material. Generally, polycrystalline materials are made of a large number of single crystals called grains. In one embodiment, a material of seed layer204includes silicon, or other semiconductor material. In one embodiment, seed layer204of polycrystalline silicon is deposited on insulating layer202that includes Si, e.g., silicon oxide, and silicon nitride. In another embodiment, a material of seed layer includes a monocrystalline material, e.g., monocrystalline silicon. Buffer layer205is deposited on seed layer204, as shown inFIG. 2. An optical layer206is formed on dual seed semiconductor layer210, as shown inFIG. 2. In one embodiment, buffer layer205includes a material of seed layer204and a material of optical layer206. Optical layer206may include any material capable of absorbing light and in response, generating an electrical signal. In one embodiment, optical layer206includes germanium, silicon, silicon-germanium, or other semiconductor materials such as gallium arsenide or indium phosphide. In one embodiment, optical layer206includes a material that absorbs light at commercial wavelengths used for long-haul and short-haul optical interconnects. Such materials are known to one of ordinary skill in the art of optical components manufacturing. Accordingly, optical layer206may absorb light with wavelengths in the range of 400 nm to 1700 nm. In one embodiment, optical layer206may absorb light with wavelengths in the range of 850 nm to 1550 nm. In one embodiment, optical layer206includes a polycrystalline Ge. In one embodiment, buffer layer205includes a polycrystalline silicon-germanium (“Si1−xGex”). In one embodiment, the relative content X of Ge is about constant. In another embodiment, the relative content X of Ge in buffer layer205can be gradually increased along the thickness of graded buffer layer205from e.g., 0% at an interface with seed layer204to e.g., 100% at the interface with optical layer206. In one embodiment, the relative content X of Ge in buffer layer205of Si1−xGexis at least 1%. In another embodiment, the relative content X of Ge in buffer layer205of Si1−xGexis in the approximate range of 10% to 90%. In yet another embodiment, the relative content X of Ge in buffer layer205of Si1−xGexis about constant and may be in the approximate range of 20% to 60%. In one embodiment, optical layer206of polycrystalline Ge is formed on buffer layer205of polycrystalline silicon-germanium that is deposited on seed layer204of polycrystalline Si on insulating substrate202that includes Si. In one embodiment, the thickness of seed layer204is between about 25 angstroms and about 1000 angstroms and the thickness of buffer layer205is between about 25 angstroms and about 1000 angstroms. Depositing dual seed semiconductor layer210on insulating layer202is described in further detail below with respect toFIGS. 3A-3Eand4A-4F.

As shown inFIG. 2, electrical contacts208are formed on optical layer206. In one embodiment, electrical contacts208include a metal, a metal alloy or a compound. In one embodiment, electrical contacts208include e.g., copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), Vanadium (V), Molybdenum (Mo), palladium (Pd), gold (Au), silver (Au), platinum Pt, or any combination thereof. In one embodiment, a distance211between metal contacts208defines a window of photodetector212for the incident light. In one embodiment, distance211between metal contacts208may be, e.g., in the approximate range of 10 nanometers (“nm”) to 100 microns (“μm”) depending on the design of photodetector212. In one embodiment, photodetector212captures light through the window defined by contacts208, generates an electrical signal from the received light, and transmits the electrical signal to the front end device region213. As shown inFIG. 2, insulating layer207is formed on top of optical layer between contacts208, and on portions of insulating layer202to electrically isolate photodetector212, e.g., from unwanted electrical parasitics that may be produced by neighboring devices and conductors. As shown inFIG. 2, photodetector212is separated from substrate201by thick insulating layer202that provides an optical isolation for waveguides that can be connected to photodetector212. In one embodiment, thick insulating layer202contains metal vias and lines. Separating the photodetector212from substrate202substantially reduces optical losses. As shown inFIG. 2, contacts208cover up the edges of the optical layer206to make sure that the light does not get into the portions of the photodetector212where there is not an electrical field. As shown inFIG. 2, photodetector212is formed in the back end of the process on insulating layer202after front end device region213having active and passive devices203and/or one or more metal layers (not shown) are formed on substrate201.

FIG. 3Ais a cross-sectional view300of one embodiment of a semiconductor structure to fabricate a dual seed semiconductor photodetector. As shown inFIG. 3A, a seed layer303is deposited on insulating layer302formed on substrate301. In one embodiment, substrate301includes monocrystalline silicon. In alternate embodiments, substrate301may comprise any material, for example silicon, silicon on insulator, and gallium arsenide, which is used to make any of integrated circuits, passive, and active devices, as described above. In one embodiment, a front end device region312that includes active and passive devices, e.g., transistors, capacitors, diodes, inductors, and interconnects is formed on substrate301, as described above with respect toFIG. 2. As shown inFIG. 3A, a thick insulating layer302is formed on substrate301. In one embodiment, thick insulating layer302covers front end device region312that has active and passive devices (not shown) grown on substrate301. In one embodiment, insulating layer302may be any one, or a combination of, silicon dioxide (e.g., “SiO2”), silicon nitride (e.g., “Si3N4”), polymer, sapphire, high-k dielectric, e.g., high-k oxide, low-k dielectric, e.g., a porous oxide, carbon doped oxides, or other insulating materials. In one embodiment, insulating layer302is an amorphous interlayer dielectric (“ILD”) that includes silicon, e.g., SiO2. In one embodiment, the thickness of insulating layer302is at least 1 micron (“μm”). In one embodiment, insulating layer302is deposited using a deposition technique, such as, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or high density plasma chemical vapor deposition (HDP CVD). Deposition of insulating layer302on substrate301of monocrystalline silicon is known to one of ordinary skill in the art of microelectronic device manufacturing. As shown inFIG. 3A, seed layer303is formed on insulating layer302. In one embodiment, seed layer303includes a polycrystalline material, e.g., polycrystalline silicon. In one embodiment, seed layer303of polycrystalline silicon is deposited on insulating layer202that includes Si, e.g., silicon oxide, and silicon nitride. In one embodiment, seed layer303is formed on insulating layer302using a chemical vapor deposition (“CVD”) technique. In one embodiment, seed layer303is formed on insulating layer302using CVD at temperature in the approximate range of 300 C to 900 C and pressure in the approximate range of 1 torr to 500 torr. In another embodiment, seed layer303is formed on insulating layer302by sputtering. The thickness of seed layer303is such that seed layer303is not optically significant. In one embodiment, the thickness of seed layer303is between about 25 angstroms (“Å”) and about 1000 Å. In one embodiment, the thickness of seed layer303of Si deposited on insulating layer of SiO2is in the approximate range of 50 Å to 500 Å.

FIG. 3Bis a view similar toFIG. 3A, after buffer layer304is formed on seed layer303to form a dual seed semiconductor layer. In one embodiment, buffer layer304includes a polycrystalline silicon-germanium (“Si1−xGex”). In one embodiment, the relative content X of Ge is gradually increased along the thickness of graded buffer layer304from about 0% at an interface with seed layer303to about 100% at the interface with optical layer formed later on in the process. In one embodiment, the relative content X of Ge in buffer layer304of Si1−xGexis at least 1%. In another embodiment, the relative constant content X of Ge in buffer layer304of Si1−xGexis in the approximate range of 20% to 80%. In one embodiment, buffer layer304is formed on seed layer303using a chemical vapor deposition technique. In one embodiment, buffer layer304is formed on seed layer303using CVD with simultaneous flow of Silane (SiH4) and Germane (GeH4) gases or simultaneous flow of DichloroSilane (SiCl2H2) and Germane gases. In one embodiment the temperature during the CVD process is in the approximate range of 300 C to 900 C and pressure in the approximate range of 1 torr to 760 torr. In another embodiment, buffer layer304is formed on seed layer303by sputtering. The thickness of buffer layer304is such that buffer layer304is not optically significant. In one embodiment, buffer layer304is formed on seed layer303to a thickness between about 25 Å and about 1000 Å. In one embodiment, the thickness of buffer layer304of Si1−xGexdeposited on seed layer303of Si is in the approximate range of 50 Å to 500 Å.

FIG. 3Cis a view similar toFIG. 3B, after an optical layer305is formed on buffer layer304to form an optical layer/buffer layer/seed layer stack. Optical layer305includes an optical quality material, e.g., optical quality germanium, silicon, silicon-germanium, or other semiconductor materials such as gallium arsenide or indium phosphide. In one embodiment, optical layer305of pure polycrystalline Ge is formed on buffer layer304of polycrystalline Si1−xGex. In one embodiment, photodetector layer305of intrinsic Ge having a carrier concentration less than 1×1015cm−3is deposited on buffer layer304of polycrystalline Si1−xGex. In one embodiment, the relative content X of Ge in buffer layer304of Si1−xGexis gradually increased from about 0 at seed layer303of silicon to about 1 at optical layer305of Ge.

In one embodiment, optical layer305is formed on buffer layer304using a CVD process. In one embodiment, optical layer305is formed on buffer layer304using CVD at temperature in the approximate range of 300° C. to 800° C. and pressure in the approximate range of 1 torr to 760 torr. In another embodiment, optical layer305is formed on buffer layer304by sputtering. In one embodiment, depositing of seed layer303on insulating layer302, buffer layer304on seed layer303is optimized for deposition temperature that may be in the approximate range of 300° C. to 800° C., for annealing times that may be from about 1 minute to about 30 minutes at the annealing temperatures from about 500° C. to about 800° C. range, 0-1 hour and for deposition rates that may be from about 100 A/min to about 500 A/min, to create an optimal grain size in a dual seed semiconductor layer that includes seed layer303and buffer layer304. Such optimization in turn creates an optimal grain size (morphology) of optical layer305deposited on buffer layer304that maximizes photodetector efficiency and minimizes photodetector dark current generation. In one embodiment, optical layer305is deposited to the thickness in the approximate range of 1000 angstroms to 6000 angstroms.

FIG. 3Dis a view similar toFIG. 3C, after an optical layer/buffer layer/seed layer stack is patterned and etched to form a photodetector mesa structure309. In one embodiment, a photoresist (not shown) is deposited on optical layer305, and patterned. Next, the patterned photoresist on the optical layer/buffer layer/seed layer stack is etched to form a photodetector mesa structure309. Patterning and etching is known to one of ordinary skill in the art of microelectronic device manufacturing. Photodetector mesa structure309may have a variety of shapes and sizes. For example, the photodetector mesa structure309may have a substantially square or rectangular cross-sectional shape. Photodetector mesa structure309may extend as far laterally and as high vertically above insulating layer302as needed to capture light. For example, the cross-sectional width310of photodetector mesa structure309may range from 0.5 μm to 100 μm and the cross-sectional thickness of photodetector309may range from 0.1 μm to 1 μm. In an embodiment, the cross-sectional width and thickness of photodetector structure may be approximately 5 μm and 0.5 μm respectively.

FIG. 3Eis a view similar toFIG. 3D, after electrical contacts306are formed on optical layer305. Contacts306may be formed by variety of methods known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, contacts306are patterned on optical layer305by lift-off, or subtractive etch techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In another embodiment, contacts306are formed on optical layer305using a damascene technique that includes etching trenches (not shown) in insulating layer311deposited on optical layer305, filling the trenches with a conductive material (not shown), and then planarizing the conductive material to the top surface of the insulating layer311. Depositing of the insulating layer311, e.g., silicon dioxide (e.g., “SiO2”), silicon nitride (e.g., “Si3N4”), on optical layer305may be performed using one of a deposition technique, such as, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or high density plasma chemical vapor deposition (HDP CVD). In one embodiment, electrical contacts306include a metal, a metal alloy or a compound. In one embodiment, electrical contacts306include e.g., copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), Vanadium (V), Molybdenum (Mo), palladium (Pd), gold (Au), silver (Au), platinum Pt, or any combination thereof. In one embodiment, distance308between electrical contacts306may be, e.g., in the approximate range of 100 nanometers (“nm”) to 100 microns (“μm”) depending on the design of the photodetector. In one embodiment, size307of the contacts306is in the approximate range of 0.01 μm to 10 μm, and distance308between the contacts306is in the approximate range of 0.01 μm to 10 μm. In one embodiment, contacts306are formed on optical layer305parallel to each other. In another embodiment, contacts306on optical layer305form interdigitated contacts. In yet another embodiment, contacts306on optical layer305form interleaved contacts. Parallel, interdigitated, and interleaved contacts are known to one of ordinary skill in the art of microelectronic device manufacturing. As shown inFIG. 3E, photodetector313is formed on insulating layer302deposited over one or more metal layers (not shown) and front end device region312formed on substrate301. In another embodiment, a plurality of photodetectors (not shown) may be formed on insulating layer302using methods described above.

FIG. 4Ais a cross-sectional view400of another embodiment of a semiconductor structure to fabricate a dual seed semiconductor photodetector. As shown inFIG. 4A, an insulating layer402is deposited on substrate401. In one embodiment, substrate401includes monocrystalline silicon. In alternate embodiments, substrate401may comprise any material, for example silicon, silicon on insulator, and gallium arsenide, which is used to make any of integrated circuits, passive, and active devices, as described above. In one embodiment, substrate401includes a front end device region (not shown). The front end device region typically includes active and passive devices, e.g., transistors, capacitors, diodes, inductors, and interconnects formed on substrate401, as described above with respect toFIGS. 2 and 3A. As shown inFIG. 4A, a thick insulating layer402is formed on substrate401. In one embodiment, insulating layer402may be any one, or a combination of, silicon dioxide (e.g., “SiO2”), silicon nitride (e.g., “Si3N4”), polymer, sapphire, high-k dielectric, e.g., high-k oxide, low-k dielectric, e.g., a porous oxide, carbon doped oxides, or other insulating materials. In one embodiment, insulating layer402is an amorphous interlayer dielectric (“ILD”) that includes silicon, e.g., SiO2. In one embodiment, the thickness of insulating layer402is at least 1 micron (“μm”). In one embodiment, insulating layer402is deposited using a deposition technique, such as, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or high density plasma chemical vapor deposition (HDP CVD). Depositing of insulating layer402on substrate401of monocrystalline silicon is known to one of ordinary skill in the art of microelectronic device manufacturing. As shown inFIG. 4A, trench403is formed in insulating layer402. In one embodiment, trench403is formed by patterning and etching insulating layer402. Patterning and etching trenches in insulating layer402is known to one of ordinary skill in the art of microelectronic device manufacturing. As shown inFIG. 4A, trench403has a bottom411and sidewalls412. In one embodiment, trench403has a high aspect ratio. That is, the ratio of depth405to width404of trench403is substantially high, for example, is at least 2. In one embodiment, depth405is between about 0.5 μm and about 2 μm and width404is between about 0.1 μm and about 0.5 μm.

FIG. 4Bis a view similar toFIG. 4A, after seed layer406is formed on insulating layer402. As shown inFIG. 4B, seed layer406covers sidewalls412and bottom411of trench403and top portions of insulating layer402outside trench403. In one embodiment, seed layer406includes a polycrystalline material, e.g., polycrystalline silicon. In one embodiment, seed layer406of polycrystalline silicon is deposited on insulating layer402that includes Si, e.g., silicon oxide, and silicon nitride. In one embodiment, seed layer406is formed on insulating layer402using a chemical vapor deposition (“CVD”) technique, sputtering, or a combination thereof as described above. The thickness of seed layer406is such that seed layer406is not optically significant. In one embodiment, the thickness of seed layer406is between about 25 Å and about 1000 Å. In one embodiment, the thickness of seed layer406is less than one third of the width404of the trench403. In one embodiment, the thickness of seed layer406of Si deposited on insulating layer402of SiO2is in the approximate range of 25 Å to 1000 Å.

FIG. 4Cis a view similar toFIG. 4B, after buffer layer407is formed on seed layer406to form a dual seed semiconductor layer417. In one embodiment, buffer layer407includes a polycrystalline Si1−xGex. In one embodiment, the relative content X of Ge is gradually increased along the thickness of buffer layer304from e.g., 10% at an interface with seed layer406to e.g., 100% at the interface with optical layer formed later on in the process. In one embodiment, the relative content X of Ge in graded buffer layer407of Si1−xGexis at least 1%. In another embodiment, the relative content X of Ge in buffer layer407of Si1−xGexis about constant and may be in the approximate range of 20% to 60%. In one embodiment, buffer layer407is formed on seed layer406using a chemical vapor deposition technique and/or sputtering, as described above. The thickness of buffer layer407is such that buffer layer407is not optically significant. In one embodiment, buffer layer407is formed on seed layer406to a thickness between about 25 Å and about 1000 Å. In one embodiment, the thickness of buffer layer407of Si1−xGexdeposited on seed layer406of Si is in the approximate range of 25 Å to 1000 Å.

FIG. 4Dis a view similar toFIG. 4C, after an optical layer408is formed on buffer layer407. As shown inFIG. 4D, optical layer408fills trench403and covers top portions of dual seed semiconductor layer417outside trench403. Optical layer408includes an optical quality material, e.g., optical quality germanium, silicon, silicon-germanium, or other semiconductor materials such as gallium arsenide or indium phosphide. In one embodiment, optical layer408of pure polycrystalline Ge is formed on buffer layer407of polycrystalline Si1−xGex. In one embodiment, optical layer408of intrinsic Ge having a carrier concentration less than 1×1015cm−3is deposited on buffer layer407of polycrystalline Si1−xGex. In one embodiment, the relative content X of Ge in graded buffer layer407of Si1−xGexis gradually increased from about 0 at seed layer406of silicon to about 1 at optical layer408of Ge. In one embodiment, optical layer305is formed on buffer layer304using a CVD process, and/or sputtering, as described above. In one embodiment, depositing of seed layer406on insulating layer402, buffer layer407on seed layer406is optimized for a high aspect ratio (for example, greater than 2) trench fill, deposition temperature in approximate range of 300 C to 800 C, anneal times of 1 min to 30 min at anneal temperature of 500 C-800 C, and deposition rates range of 100 A/min to 500 A/min, to create optimal grain size in dual seed semiconductor layer417. Such optimization in turn creates an optimal grain size (morphology) of optical layer408deposited on buffer layer407that maximizes photodetector efficiency and minimizes photodetector dark current generation. In one embodiment, optical layer408is deposited onto dual seed semiconductor layer417to the thickness in the approximate range of 1000 angstroms to 6000 angstroms. In one embodiment, optical layer408is deposited onto dual seed semiconductor layer417to the thickness of at least about 1.5 times of depth405of trench403. In one embodiment, if depth405of trench403is in the approximate range of 0.1 μm to 2 μm, optical layer408is deposited to the thickness in the approximate range of 0.15 μm to 3 μm.

FIG. 4Eis a view similar toFIG. 4D, after optical layer408and dual seed semiconductor layer417are planarized to the top surface of dielectric layer402. As shown inFIG. 4E, portions of optical layer408and portions of dual seed semiconductor layer417are removed from the top surface of insulating layer402outside trench403while portion (photodetector body)410of optical layer408remains in trench403. As shown inFIG. 4E, the top surface of photodetector body409levels with the top surface of insulating layer402. In one embodiment, optical layer408and dual seed semiconductor layer417are polished back using a chemical-mechanical polishing (“CMP”) technique known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, multiple photodetector bodies409may be formed on insulating layer302using methods described above to form a plurality of photodetectors.

FIG. 4Fis a view similar toFIG. 4E, after electrical contacts410are formed on photodetector body409. Contacts409may be formed by variety of methods known to one of ordinary skill in the art of microelectronic device manufacturing, as described above with respect toFIG. 2andFIG. 3E.

The processes described above with respect toFIGS. 2,3A-3E,4A-4F allow optical devices, e.g., photodetectors, to be fabricated in the same process flow along with microelectronic circuits, and to be inserted near the end of the process flow, after many layers of metallization. Therefore, the changes in the basic microelectronic device manufacturing process flow are minimal, both in terms of process development and cost. The processes described above also allow for optical isolation for waveguides which connect optical devices such as photo detectors. By enabling an optical layer to be fabricated in the same process flow as electronic devices, optical device parasitics can be reduced and performance of the devices is enhanced.