Memory device performing refresh operation based on a random value and method of operating the same

A memory device includes a memory cell array, a random bit generator, a comparator and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random bit generator generates a random binary code having a predetermined number of bits. The comparator compares the random binary code and a reference binary code to output a matching signal based on a result of the comparison. The refresh controller refreshes target memory cells from among the plurality of memory cells based on addresses accessed by a memory controller during a sampling period randomly determined based on the matching signal and a refresh command from the memory controller.

TECHNICAL FIELD

Example embodiments relate to memory devices, and more particularly, to memory devices performing refresh operation and methods of operating the same.

DISCUSSION OF RELATED ART

A dynamic random access memory (DRAM) device may store data by storing a charge to a capacitor of a memory cell connected to a given word-line. The DRAM device may periodically refresh the memory cell since charges in the capacitor leak over time.

The influence of charges of an adjacent memory cell connected to another word-line adjacent to the given word-line increases as processes for manufacturing memory devices are scaled down and periods between word-lines become narrower. When the given word-line (e.g., the active state word-line) is intensively accessed, a row hammer may occur in an adjacent memory cell. That is, due to a voltage of the active state word-line, data stored in the memory cells connected to other word-lines adjacent to the active state word-line may be lost or changed to an unintended state.

SUMMARY

At least one exemplary embodiment of the inventive concept provides a memory device capable of preventing data from being lost due to a specified word-line being intensively accessed.

At least one exemplary embodiment of the inventive concept provides a method of operating a memory device, capable of preventing data from being lost due to a specified word-line being intensively accessed.

According to an exemplary embodiment of the inventive concept, a memory device includes a memory cell array, a random bit generator, a comparator and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random bit generator generates a random binary code having a predetermined number of bits. The comparator compares the random binary code and a reference binary code to output a matching signal based on a result of the comparison. The refresh controller refreshes target memory cells from among the plurality of memory cells based on addresses accessed by a memory controller during a sampling period randomly determined based on the matching signal and a refresh command from the memory controller.

According to an exemplary embodiment of the inventive concept, a memory device includes a memory cell array, a control logic circuit and a row decoder. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The control logic circuit generates a refresh address based on first sampling addresses accessed by a memory controller during a first sampling period and second sampling addresses accessed by the memory controller during a second sampling period. The row decoder refreshes target memory cells corresponding to the refresh address, from among the plurality of memory cells. The first sampling period is determined based on a first refresh command from the memory controller and a first matching signal that is randomly generated. The second sampling period is determined based on a second refresh command from the memory controller and a second matching signal that is randomly generated.

According to an exemplary embodiment of the inventive concept, a method of operating a memory device including a plurality of memory cells coupled to a plurality of word-lines is provided. The method includes sampling addresses provided from a memory controller in response to a first refresh command to generate first sample addresses; halting an operation to sample the addresses provided from the memory controller in response to a first matching signal randomly generated after receiving the first refresh command; refreshing first memory cells from among the plurality of memory cells based on a second refresh command and one of the first sample addresses to sample addresses provided from the memory controller after the first matching signal being generated to generate second sample addresses; halting an operation to sample the addresses provided from the memory controller in response to a second matching signal randomly generated after receiving the second refresh command; and refreshing second memory cells from among the plurality of memory cells based on a third refresh command and one of the first sample addresses and the second sample addresses. The third refresh command is provided from the memory controller after the second matching signal being generated.

According to an exemplary embodiment of the inventive concept, a memory device includes a memory cell array, a random number generator, and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random number generator is configured to generate a random number. The refresh controller is configured to begin sampling addresses of the memory cell array accessed by the memory controller in response to a first refresh command at a first time, configured to halt the sampling at a second time when the generated random number matches a pre-stored reference number, select an address among the addresses sampled between the first and second times that occurs most frequently, and refresh at least one of the memory cells connected to one of the word-lines associated with an address adjacent the selected address.

Therefore, a memory device according to at least one exemplary embodiment of the inventive concept identifies a target address which is intensively accessed, and refreshes memory cells based on the target address. Accordingly, the memory device may prevent data of memory cells connected to at least one word-line adjacent to the target word-line from being damaged when a target word-line is intensively accessed.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the present inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.

FIG.1is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

Referring toFIG.1, a memory system10includes a memory controller100and a memory device200.

For example, the memory system10may be included or implemented in one of various electronic devices such as a desktop computer, a laptop computer, a workstation, a server, a mobile device, etc.

The memory controller100may control an overall operation of the memory device200. The memory controller100may control the overall data exchange between an external host and the memory device200. For example, the memory controller100may write data to the memory device200or read data from the memory device200in response to a request from the host.

In addition, the memory controller100may transmit a command CMD and an address ADD to the memory device200for controlling the memory device200. The memory controller100may transmit the command CMD and the address ADDR to the memory device200through one channel (the same signal line) or different channels (different signal lines).

The memory controller100may be implemented in a host (not illustrated) and may access the memory device200according to a request from a processor (not illustrated) in the host. For example, the memory controller100may access the memory device200in a direct memory access (DMA) manner. The memory controller100may be implemented with a portion of a system-on chip (SoC), but is not limited thereto.

The memory device200may operate as a buffer memory, a working memory, or a main memory of the host which includes the memory controller100. The memory device200may operate based on the command CMD and the address ADD transmitted by the memory controller100. For example, the memory device200may store data transmitted from the memory controller100or may transmit data to the memory controller100.

The memory device200may include a command buffer210, an address buffer220, a control logic circuit230and a memory cell array240.

The command buffer210may temporarily store the command CMD from the memory controller100and may transfer the command CMD to the control logic circuit230. The address buffer220may temporarily store the address ADD from the memory controller100and may transfer the address ADD to the control logic circuit230.

The control logic circuit230may receive the command CMD and the address ADD from the command buffer210and the address buffer220, respectively. The control logic circuit230may decode the command CMD to generate a decoded result and may control components of the memory device200based on the decoded result.

For example, the control logic circuit230may control the components of the memory device200to enable a word-line corresponding to (designated by) the address ADD in response to an active command (ACT inFIG.2). For example, the control logic circuit230may control the components of the memory device200to refresh memory cells in the memory cell array240in response to a refresh command (REF inFIG.2). In a refresh operation, a plurality of memory cell rows in the memory cell row240may be sequentially refreshed or a specified memory cell row is refreshed. Each of the plurality of memory cell rows may include a plurality of memory cells.

The memory cell array240may include a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. For example, each of the plurality of memory cells may be a DRAM cell. The memory controller100and the memory device200may communicate signals to each other based on a protocol such as double data rate (DDR), low power double data rate (LPDDR), graphics double data rate (GDDR), Wide I/O, high bandwidth memory (HBM) and hybrid memory cube (HMC), but exemplary embodiments of the inventive concept are not limited thereto. The memory cells may be one of memory cells of static random access memory (SRAM), a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM) and a NAND flash memory.

In an exemplary embodiment, a specified address (a target address) is frequently accessed or called by the memory controller100, from among all addresses of the memory device200. The number of times that the target address is accessed by the memory controller100may be relatively greater than the number of times that any other address of the memory device200is accessed by the memory controller100. However, the above operation of the memory controller100may cause a disturbance or coupling with respect to data stored at a location adjacent to a location corresponding to the target address. For example, in a case where frequent, intensive, or iterative activation and deactivation is performed on a word-line corresponding to the target address by the memory controller100, data of memory cells connected to at least one word-line adjacent to the word-line corresponding to the target address may be damaged.

The control logic circuit230may determine a target address which is accessed by the memory controller100more frequently than any other address of the memory device200and may refresh memory cells coupled to at least one word-line adjacent to the target word-line. Therefore, the memory device200may prevent data of memory cells connected to at least one word-line adjacent to the target word-line from being damaged when a target word-line is intensively accessed.

FIG.2is a timing diagram illustrating a refresh operation of the memory device according to an exemplary embodiment of the inventive concept.

Referring toFIGS.1and2, the memory device200receives active commands ACT and an address ADD corresponding to each of the active commands ACT from the memory controller100during a time period from a first time point t1to a fifth time point t5including time points t2, t3and t4. For example, the address ADD may be a row address designating one word-line of the word-lines of the memory device200. As illustrated inFIG.2, the memory device200may receive one of first through fifth addresses ADD1, ADD2, ADD3, ADD4and ADD5in response to one active command ACT from the memory controller100.

In an exemplary embodiment, the memory device200samples addresses provided from the memory controller100during a first time period TP1between the time point t1and the time point t2to generate sampled addresses, stores the sampled addresses as sampling addresses in a separate register and manages the sampling addresses. The memory device200does not sample addresses provided from the memory controller100during a second time period TP2between the time point t2and the time point t5. That is, the memory device200halts an operation to sample addresses provided from the memory controller100after the first time period TP1. Therefore, the memory device200may sample the addresses corresponding to eight active commands ACT during the first time period TP1and does not sample the addresses corresponding to four active commands ACT during the second time period TP2. In this case, the memory device200may sample the first through fourth addresses ADD1, ADD2, ADD3and ADD4.

During the second time period TP2, the memory device200receives a refresh command REF from the memory controller100at each of the time points t3, t4and t5after receiving the active commands ACT. The memory device200may perform a refresh operation in response to the refresh command REF.

The memory device200may perform a normal refresh operation in response to the refresh command REF at respective one of the third time point t3and the fourth time point t4. For example, the memory device200may sequentially refresh memory cells in one of a plurality of memory banks in the memory device200through the normal refresh operation, which is referred to as a per-bank refresh operation, or may sequentially refresh memory cells in all of the plurality of memory banks in the memory device200through the normal refresh operation, which is referred to as an all-bank refresh operation.

The memory device200may perform a refresh operation based on a selected address from among the sampling address in response to the refresh command REF (which is referred to as a row hammer refresh command, hereinafter) at the fifth time point t5. The row hammer refresh command may be an N-th refresh command from among a plurality of refresh commands received from the memory controller100. Here, N is an integer greater than one. As illustrated inFIG.2, the row hammer refresh command may be a third refresh command from among the refresh commands REF. That is, the row hammer refresh command may be a refresh command which is periodically provided from the memory controller100.

The memory device200may determine a selected address from among the sampling addresses in response to a row hammer refresh command and may perform a refresh operation (which is referred to as a row hammer refresh operation, hereinafter) based on the determined selected address.

For example, the memory device200may determine one of the sampling addresses which are sampled during the first time period TP1before receiving the row hammer refresh command as the selected address. In other example embodiments, the memory device200may determine one of the sampling addresses which are sampled during a plurality of time periods including the first time period TP1as the selected address. The memory device200may refresh memory cells coupled to at least one word-line adjacent to a word-line corresponding to the selected word-line.

In an exemplary embodiment of the inventive concept, the memory device200randomly determines a time period during which the memory device200samples addresses accessed by the memory controller100. For example, the first time period TP1and the second time period TP2may be randomly determined. Determination of a time period for sampling addresses will be described with reference toFIGS.5through7D.

InFIG.2, the memory device200is illustrated as performing the row hammer refresh operation in response to the row hammer refresh command from the memory controller100, but exemplary embodiments of the inventive concept are limited thereto. The memory device200may periodically perform the row hammer refresh operation based on an operation mode even when the memory device200does not receive the row hammer refresh command from the memory controller100. Hereinafter, it is assumed that the memory device200performs the row hammer refresh operation in response to the row hammer refresh command from the memory controller100for convenience of explanation.

FIG.3illustrates an example of selected address associated with performing a refresh operation inFIG.2.

Referring toFIGS.1through3, the memory device200counts an access number of each of the first through fourth addresses ADD1˜ADD4sampled during the first time period TP1. For example, the control logic circuit230may manage or maintain an access number of each of the sampling addresses ADD1˜ADD4. As illustrated inFIGS.2and3, an access number of each of the first through fourth addresses ADD1˜ADD4sampled during the first time period TP1may correspond to ‘2’, ‘4’, ‘1’, and ‘1’ respectively.

The control logic circuit230may determine the second address ADD2whose access number is greatest (i.e., maximum) from among the sampling addresses ADD1˜ADD4as a maximum access address. That is, the second address ADD2is the maximum access address since the second address ADD2was accessed more often than the first address ADD1, the third address ADD3, and the fourth address ADD4during the first time period TP1(i.e., a sampling period). For example, the control logic circuit may determine a maximum address based on a space saving algorithm, but exemplary embodiments of the inventive concept are not limited thereto. The memory device200may determine the maximum access address as a selected address and may perform the row hammer refresh operation based on the maximum access address. For example, the memory device200may refresh memory cells coupled to at least one word-line adjacent to a word-line corresponding to the second address ADD2.

As described above, the memory device200may sample addresses accessed during a sampling period (i.e., a time period) which is randomly determined in response to the row hammer refresh command, and may perform the row hammer refresh operation based on a maximum access address from among the sampling addresses. In this case, when the memory controller100repeatedly accesses the addresses with a regular pattern, the memory device200performs the row hammer refresh operation to prevent data from being lost. There, the memory device200may enhance data integrity.

FIG.4is a block diagram illustrating an example of the memory device inFIG.1according to an exemplary embodiment of the inventive concept.

Referring toFIG.4, the memory device200may further include a row decoder250, a column decoder260, a sense amplifier/write driver270and a data input/output (I/O) buffer280.

The command buffer210may transfer the command CMD from the memory controller100to the control logic circuit230and the address buffer220may transfer the address ADD from the memory controller100to the control logic circuit230. In an exemplary embodiment, the address buffer220may separate the address ADD into a row address and a column address and may transfer the row address and the column address to the control logic circuit230.

The control logic circuit230may generate control signals for controlling components of the memory device200based on the command CMD from the command buffer210and the address ADD from the address buffer220.

For example, the control logic circuit230may generate a refresh control signal RCS associated with a refresh operation based on the refresh command REF (inFIG.2). For example, the control logic circuit230may generate a refresh control signal RCS such that a normal refresh operation or a row hammer refresh operation is performed.

The control logic circuit230may generate a refresh address RADD corresponding to (designating) a word-line coupled to memory cells to be refreshed. For example, the refresh address RADD, generated for the row hammer refresh operation, may designate at least one word-line adjacent to a word-line corresponding to the maximum access address. In addition, the control logic circuit230may generate the refresh address RADD such that memory cell rows are sequentially refreshed in the normal refresh operation.

Although not illustrated, the control logic circuit230may include a command decoder that decodes the command CMD and a mode register that sets an operation mode of the memory device200. In addition, the control logic circuit230may further include an address separator that separates the address ADD into a row address and a column address. The control logic circuit230may output the refresh address RADD and the column address CADD to the row decoder250and the column decoder260, respectively based on the separated row address and the column address.

The memory cell array240may include a plurality of memory cells which are respectively located at points where a plurality of word-lines WLs and a plurality of bit-lines BLs intersect each other.

The row decoder250may be coupled to the memory cell array240through the word-lines WLs. The row decoder250may control voltages of the word-lines WLs under control of the control logic circuit230. For example, the row decoder250may refresh memory cells coupled to a word-line corresponding to the refresh address RADD by enabling and disabling the word-line corresponding to the refresh address RADD based on the refresh address RADD and the refresh control signal RCS.

The column decoder260may be coupled to the memory cell array240through the bit-lines BLs. The column decoder260may select one of the bit-lines BLs under control of the control logic circuit230. For example, the column decoder260may select a bit-line corresponding to the column address CADD from the control logic circuit230.

The sense amplifier/write driver270may receive a write data from the data I/O buffer280and may store the write data in memory cells selected by the row decoder250and the column decoder260. The sense amplifier/write driver270may read data from the memory cells selected by the row decoder250and the column decoder260and may provide the read data to the data I/O buffer280.

The data I/O buffer280may temporarily read data provided from the sense amplifier/write driver270and write data provided from an outside source such as a host device. The data I/O buffer280may provide the read data to the memory controller100inFIG.1, or may receive the write data to provide the write data to the sense amplifier/write driver270.

FIG.5is a block diagram illustrating an example of the control logic circuit inFIG.4according to an exemplary embodiment of the inventive concept.

Referring toFIG.5, the control logic circuit230includes a random bit generator231(e.g., a logic circuit), a comparator232(e.g., a comparison circuit) and a refresh controller233(e.g., a control circuit).

The random bit generator231may generate a random binary code RBC having a predetermined number of bits. The random binary code RBC may be a pseudo random sequence. That is, the random bit generator231may generate the random binary code RBC based on the pseudo random sequence. The random bit generator231may output the random binary code RBC to the comparator232in response to an output control signal OCS from the refresh controller233.

The refresh controller233may output the output control signal OCS to the random bit generator231based on the command CMD. For example, the refresh controller233may provide the output control signal OCS to the random bit generator231whenever the refresh controller233receives the active command ACT (inFIG.2).

That is, the random bit generator231may output the random binary code RBC in response to the active command ACT. For example, the random bit generator231may output a first random binary code in response to a first active command and may output a second random binary code in response to a second active command. When the random binary code RBC is a pseudo random sequence, the random binary code RBC, output from the random bit generator231according to the active command ACT may be periodically repeated.

In an exemplary embodiment, the comparator232compares the random binary code RBC and a pre-stored reference binary code PBC to output a matching signal MTC based on a result of the comparison. The reference binary code PBC may be the same as at least one of values of the random binary code RBC that the random bit generator231is capable of outputting. For example, the reference binary code PBC may be provided from an external register or may be stored in a register in the comparator232. When bits of the random binary code RBC are the same as bits of the reference binary code PBC (i.e., when the random binary code RBC matches the reference binary code PBC), the comparator232may output the matching signal MTC to the refresh controller233. For example, when the random binary code RBC is periodically repeated, the comparator232may output the matching signal MTC which is periodically repeated based on the random binary code RBC. In an exemplary embodiment, the comparator232outputs the matching signal MTC at a first logic level when the random binary code RBC matches the reference binary code PBC and outputs the matching signal MTC at a second other logic level when the random binary code RBC does not match the reference binary code PBC.

In example embodiments, the comparator232may compare the random binary code RBC with a plurality of reference binary codes PBC. In this case, a frequency of generating the matching signal MTC may vary according to a number of the reference binary codes PBC. For example, a frequency of generating the matching signal MTC may increase as the number of the reference binary codes PBC increases.

The refresh controller233may receive the command CMD, the address ADD and the matching signal MTC. The refresh controller233may generate the refresh control signal RCS and the refresh address RADD based on the refresh command REF.

For example, when the refresh controller233receives the row hammer refresh command, the refresh controller233may generate the refresh address RADD such that the row hammer refresh operation is performed in response to the row hammer refresh command. For example, the refresh address RADD may designate at least one word-line adjacent to a word-line corresponding to the maximum access word-line. In an exemplary embodiment, the refresh controller233generates the refresh address RADD such that the normal refresh operation is performed in response to the refresh command except the row hammer refresh command.

The refresh controller233may determine a sampling period corresponding to a time period (for example, the first time period TP1inFIG.2) during which the control logic circuit230samples the address ADD and a non-sampling period corresponding to a time period (for example, the second time period TP2inFIG.2) during which the control logic circuit230halts an operation to sample addresses ADD based on the matching signal MTC and a command CMD. Determination of the sampling period by the refresh controller233will be described with reference toFIGS.7A through7D.

The refresh controller233may store addresses accessed during the sampling period in a refresh register circuit234including a plurality of refresh registers. The refresh controller233may select a refresh register to store the address ADD based on values of the address ADD.

For example, the refresh controller233may store a first address ADD1(refer toFIG.7A) in a first refresh register, and may store a second address ADD2(refer toFIG.7A) in a second refresh register. When the refresh controller233receives a specified address repeatedly during the sampling period, the refresh controller233may increase a counting value corresponding to a refresh register storing the specified address. The refresh controller233may maintain counting values corresponding to the refresh registers based on the address ADD accessed during the sampling period.

The refresh controller233may determine an address stored in a refresh register corresponding to a maximum counting value, from among the refresh registers corresponding to the counting values, respectively, as the maximum access address, which will be described with reference toFIG.8.

FIG.6is a circuit diagram illustrating an example of the random bit generator inFIG.5according to an exemplary embodiment of the inventive concept.

Referring toFIG.6, the random bit generator231includes a register circuit REGC and a logical operation circuit LOC.

In an exemplary embodiment, the random bit generator231is implemented with a linear feedback shift register. That is, the register circuit REGC and the logical operation circuit LOC may constitute a linear feedback shift register.

The linear feedback shift register may determine feedback bits based on a characteristic polynomial having a coefficient of ‘0’ or 1′. The feedback bits are output through a feedback path of the linear feedback shift register. Bits generated by a logical operation based on the feedback bits may be input to input terminals of the linear feedback shift register. The linear feedback shift register may generate a pseudo random sequence based on the bits input to the input terminals.

For example, when the random bit generator231is implemented based on a characteristic polynomial of x11+x9+x7+x2+1 as illustrated inFIG.6, the register circuit REGC may include first through eleventh registers REG1˜REG11and the logical operation circuit LOC may include first through third logic circuits XOR1˜XOR3.

For example, each of the first through eleventh registers REG1˜REG11may store a respective one of first through eleventh bits b1˜b11. Values of the first through eleventh bits b1˜b11may vary according to a shift operation. Each of the first through third logic circuits XOR1˜XOR3may perform an exclusive OR operation.

The random bit generator231may output the random binary code RBC through the register circuit REGC. The random bit generator231may output the random binary code RBC having a predetermined number of bits. For example, the random bit generator231may output the random binary code RBC having four bits based on the first through fourth bits b1˜b4stored in the first through fourth registers REG1˜REG4.

The logical operation circuit LOC may be positioned in a feedback path of the random bit generator231. The first logical circuit XOR1is positioned in output path of the second register REG2, the second logical circuit XOR2is positioned in output path of the seventh register REG7and the third logical circuit XOR3is positioned in output paths of the ninth register REG9and the eleventh register REG11.

For example, the third logical circuit XOR3performs a logical operation based on the ninth bit b9in the ninth register REG9and the eleventh bit b11in the eleventh register REG11. The second logical circuit XOR2performs a logical operation based on the seventh bit b7in the seventh register REG7and an output of the third logical circuit XOR3. The first logical circuit XOR1performs a logical operation based on the second bit b2in the second register REG1and an output of the second logical circuit XOR2.

The output of the first logical circuit XOR1may vary based on the second bit b2, the seventh bit b7, the ninth bit b9and the eleventh bit b11. That is, each of the second bit b2, the seventh bit b7, the ninth bit b9and the eleventh bit b11may be a feedback bit. The output of the output of the first logical circuit XOR1may be provided to the first register REG1as an input.

The first register REG1may store the output of the first logical circuit XOR1as the first bit b1. The bit input through a feedback path may be shifted through the first through eleventh registers REG1˜REG11based on a control signal (for example, the output control signal OCS inFIG.5). For example, the random bit generator231performs a bit shift operation based on the output control signal OCS and may output the random binary code RBC based on the first through fourth bits b1˜b4stored in the first through fourth registers REG1˜REG4.

As described above, the random bit generator231may be implemented with a linear feedback shift register, and the random binary code RBC may be a pseudo random sequence. Therefore, the random bit generator231may output the random binary code RBC which is periodically repeated.

While the random bit generator231ofFIG.6is described based on a characteristic polynomial of x11+x9+x7+x2+1, exemplary embodiments of the inventive concept are not limited thereto. The random bit generator231is implemented based on one of various characteristic polynomials and a number of registers in the register circuit REGC and a number of logical circuits in the logical operation circuit LOC may be varied.

FIGS.7A through7Dillustrate examples of the refresh controller inFIG.6determining a sampling period according to exemplary embodiments of the inventive concept.

FIGS.7A and7Billustrate an example where the refresh controller inFIG.6determines a sampling period according to a first scheme andFIGS.7C and7Dillustrate an example where the refresh controller inFIG.6determines a sampling period according to a second scheme.

Referring to,FIGS.5and7A, the refresh controller233receives a first refresh command REF1from the memory controller100at a first time point tn. The first refresh command REF1may be a row hammer refresh command (i.e., an N-th refresh command). The refresh controller233may sample addresses ADD received from the memory controller100in response to the first refresh command REF1. The refresh controller233may sample addresses ADD received from the memory controller100in response to the active command CMD after the refresh controller233receives the first refresh command REF1.

The refresh controller233receives a first matching signal MTC1provided from the comparator232at a second time point t12. The refresh controller233halts an operation to sample addresses ADD received from the memory controller100in response to the first matching signal MTC1. Therefore, the refresh controller233may sample the addresses ADD received from the memory controller100during a first time period TP11and does not sample the addresses ADD received from the memory controller100during a second time period TP12. For example, the refresh controller233receiving a first matching signal MTC1of a first logic level may indicate that a current generated random binary code RBC matches a pre-stored binary code PBC and the refresh controller233receiving a first matching signal MTC1of a second other logic level may indicate that the current generated random binary code RBC does not match the pre-stored reference binary code PBC.

For example, as illustrated inFIG.7A, the refresh controller233samples eight addresses ADD received from the memory controller100during the first time period TP11and does not sample four addresses ADD received from the memory controller100during the second time period TP12. The refresh controller233halts an operation to sample the addresses ADD received from the memory controller100in response to the active command ACT after the first matching signal MTC1is generated.

The refresh controller233receives a second refresh command REF2from the memory controller100at a third time point t13. The second refresh command REF2may be a row hammer refresh command. The refresh controller233may determine a maximum access address based on the addresses sampled during the first time period TP11in response to the second refresh command REF2.

Referring to,FIGS.5and7B, the refresh controller233samples addresses ADD received from the memory controller100in response to the second refresh command REF2. The refresh controller233may sample the addresses ADD received from the memory controller100in response to the active command CMD after the refresh controller233receives the second refresh command REF2.

The refresh controller233may receive a second matching signal MTC2provided from the comparator232at a second time point t14. The refresh controller233halts an operation to sample addresses ADD received from the memory controller100in response to the second matching signal MTC2. Therefore, the refresh controller233may sample the addresses ADD received from the memory controller100during a third time period TP13and does not sample the addresses ADD received from the memory controller100during a fourth time period TP14. For example, as illustrated inFIG.7B, the controller233samples six addresses ADD received from the memory controller100during the third time period TP13and does not sample six addresses ADD received from the memory controller100during the fourth time period TP14.

The refresh controller233receives a third refresh command REF3from the memory controller100at a third time point t15. The third refresh command REF3may be a row hammer refresh command. The refresh controller233may determine a maximum access address based on the addresses sampled during the first time period TP11and the third time period TP13in response to the third refresh command REF3.

As described with reference toFIGS.7A and7B, the sampling period and/or a number of sampling addresses may be randomly determined based on a generation timing of the matching signal MTC. A period of the first time period TP11(the first sampling period) determined based on the first matching signal MTC1may be different from a period of the third time period TP13(the second sampling period) determined based on the second matching signal MTC2. For example, a number of first sampling addresses (eight) determined based on the first matching signal MTC1may be different from a number of second sampling addresses (six) determined based on the second matching signal MTC2.

InFIGS.7C and7D, commands, addresses and matching signals correspond to the commands, addresses and matching signals inFIGS.7A and7B, and thus repeated description will be omitted.

Referring to,FIGS.5and7C, the refresh controller233receives the first refresh command REF1from the memory controller100at a first time point t21. The refresh controller233does not sample addresses ADD received from the memory controller100in response to the first refresh command REF1. The refresh controller233receives the first matching signal MTC1at a second time point t22. The refresh controller233samples the addresses ADD received from the memory controller100in response to the first matching signal MTC1. Therefore, the refresh controller233does not sample eight addresses ADD received from the memory controller100during a first time period TP21and samples four addresses ADD received from the memory controller100during a second time period TP22.

The refresh controller233samples the addresses ADD received from the memory controller100in response to the active command ACT after the first matching signal MTC1is generated. The refresh controller233receives the second refresh command REF2from the memory controller100at a third time point t23. The refresh controller233may determine a maximum access address based on the addresses sampled during the second time period TP22in response to the second refresh command REF2.

Referring to,FIGS.5and7D, the refresh controller233does not sample addresses ADD received from the memory controller100in response to the second refresh command REF2.

The refresh controller233receive the second matching signal MTC2provided from the comparator232at a second time point t24. The refresh controller233sample the addresses ADD received from the memory controller100in response to the second matching signal MTC2. Therefore, the refresh controller233does not sample six addresses ADD received from the memory controller100during a third time period TP23and samples six addresses ADD received from the memory controller100during a fourth time period TP24as illustrated inFIG.7D. The refresh controller233receives the third refresh command REF3from the memory controller100at a third time point t25. The refresh controller233may determine a maximum access address based on the addresses sampled during the second time period TP22and the fourth time period TP24in response to the third refresh command REF3.

As described with reference toFIGS.7A through7D, the refresh controller233may determine a sampling period based on the matching signal MTC and the refresh command REF. The sampling period and/or a number of sampling addresses may be randomly determined based on a generation timing of the matching signal MTC.

Determining a sampling period based on the matching signal MTC and the refresh command REF is not limited to the examples shown inFIGS.7A through7D, and the refresh controller233may determine a sampling period based on various schemes. For example, in an exemplary embodiment, the refresh controller233samples the addresses in response to the row hammer refresh command and does not sample the addresses when three matching signals MTC are received.

FIG.8illustrates an example in which the refresh controller inFIG.5determines a maximum access address.

FIG.8illustrates an example in which the refresh controller233inFIG.5determines a maximum access address MADD based on each of the second refresh command REF2inFIG.7Aand the third refresh command REFS inFIG.7B.

Referring to,FIGS.5,7A and8, the refresh controller233samples eight addresses ADD received from the memory controller100during the first time period TP11by using the refresh register circuit234.

For example, the refresh controller233may store the second address ADD2, received at a first time, in a first refresh register in the refresh register circuit234. The refresh controller233may increase a counting value corresponding to the first refresh register to ‘1’. The refresh controller233may increase the counting value corresponding to the first refresh register to ‘2’ based on the second address ADD2received at a second time. The refresh controller233may store the third address ADD3, received at a third time, in a second refresh register in the refresh register circuit234. The refresh controller233may increase a counting value corresponding to the second refresh register to ‘1’.

Similarly, the refresh controller233may store the first address ADD1and the fourth address ADD4, in a third refresh register and a fourth refresh register in the refresh register circuit234, respectively.

Since the refresh controller233receives the first address ADD1two times, the second address ADD2four times, the third address ADD2once and the fourth address ADD4once during the first time period TP11, the refresh controller233may set the counting value corresponding to the first refresh register to ‘4’, the counting value corresponding to the second refresh register to ‘2’, the counting value corresponding to the third refresh register to ‘1’, and the counting value corresponding to the fourth refresh register to ‘1’, respectively. The refresh controller233may determine the second address ADD2in the first refresh register, corresponding to a maximum counting value, as the maximum access address MADD in response to the second refresh command REF2.

The refresh controller233generates the refresh address RADD based on the second address ADD2which is determined as the maximum access address MADD. Therefore, the refresh controller233may perform the row hammer refresh operation based on the second address ADD2. The counting value corresponding to the first refresh register may be reset to ‘0’ after the row hammer refresh operation is performed.

Referring to,FIGS.5,7B and8, after the counting value corresponding to the first refresh register is reset to ‘0’, the refresh controller233may sample six addresses ADD received from the memory controller100during the third time period TP13by using the refresh register circuit234.

The refresh controller233may set the counting value corresponding to the first refresh register to ‘1’ based on the second address ADD2received at a first time. The refresh controller233may increase the counting value corresponding to the second refresh register by ‘1’ to set the counting value corresponding to the second refresh register to ‘2’ based on the third address ADD3received at a second time. The refresh controller233may increase the counting value corresponding to the third refresh register by ‘3’ to set the counting value corresponding to the third refresh register to ‘5’ based on the first address ADD1received at third, fourth, and sixth times. The refresh controller233may increase the counting value corresponding to the fourth refresh register by ‘1’ to set the counting value corresponding to the fourth refresh register to ‘2’ based on the fourth address ADD4received at a fifth time. The refresh controller233may determine the first address ADD1in the third refresh register, corresponding to a maximum counting value, as the maximum access address MADD in response to the third refresh command REFS.

The refresh controller233may generate the refresh address RADD based on the first address ADD1which is determined as the maximum access address MADD. Therefore, the refresh controller233may perform the row hammer refresh operation based on the second address ADD2since the second address ADD2is adjacent the maximum access address MADD of the first address ADD1. The counting value corresponding to the third refresh register may be reset to ‘0’ after the row hammer refresh operation is performed.

FIG.9illustrates an example of a row hammer refresh operation performed in the memory device according to an exemplary embodiment of the inventive concept.

Referring toFIG.9, the memory cell array240may be coupled to the row decoder250through first through n-th word-lines WL1˜WLn, where n is an integer greater than four. The memory cell array240may include first through n-th memory cells MC1˜MCn coupled to respective one of the first through n-th word-lines WL1˜WLn. For example, the first memory cells MC1may be coupled to the first word-line WL1and the second memory cells MC2may be coupled to the second word-line WL2.

The row decoder250may enable and disable a word-line corresponding to the refresh address RADD in response to the refresh control signal RCS. Therefore, the memory cells coupled to a word-line designated by the refresh address RADD may be refreshed.

As illustrated inFIG.9, when an address corresponding to the second word-line WL2is determined ass the maximum access address MADD, the refresh address RADD may include a first adjacent address AD_RA1corresponding to the first word-line WL1and a second adjacent address AD_RA2corresponding to the third word-line WL3.

The row decoder250may enable the first word-line WL1and the third word-line WL3. For example, the row decoder250may enable the third word-line WL3after enabling the first word-line WL1. For example, the row decoder250may enable the first word-line WL1after enabling the third word-line WL3. Since the first word-line WL1and the third word-line WL3are enabled, the first memory cells MC1and the third memory cells MC3are refreshed, and data stored in the first word-line WL1and the third word-line WL3are prevented from being lost due to the second word-line WL being frequently accessed.

FIG.10is a flow chart illustrating a method of operating a memory device inFIG.1according to an exemplary embodiment of the inventive concept.

Referring toFIGS.1through10, in operation S201, the memory device200receives N refresh commands REF. The N-th refresh command may be a row hammer refresh command designating a row hammer refresh operation.

In operation S202, the memory device200samples addresses accessed during a sampling period which is randomly determined in response to the N-th refresh command and determines a maximum access address from among the addresses accessed during the sampling period.

For example, the memory device200may generate a random binary code RBC having a predetermined number of bits in response to an active command ACT from the memory controller100. The memory device200may compare the random binary code RBC and a reference binary code PBC to output the matching signal MTC based on a result of the comparison. The memory device200may determine a sampling period based on the matching signal MTC and the refresh command REF and may sample addresses accessed during the sampling period. The memory device200may determine a maximum access address, which is accessed most often or most frequently from among sampling addresses which are sampled during the sampling period. The memory device200may determine an address stored in a refresh register corresponding to a maximum counting value, from among refresh registers corresponding to counting values, respectively, as the maximum access address.

In operation S203, the memory device200refreshes memory cells based on the maximum access address. For example, the memory device200may refresh memory cells coupled to at least one second word-line adjacent to a first word-line corresponding to the maximum access address.

FIG.11is a block diagram illustrating an example of a memory system according to an exemplary embodiment of the inventive concept.

Referring toFIG.11, a memory system20includes a memory controller300and a memory module400.

For example, the memory system20may be one of various electronic devices such as a desktop computer, a laptop computer, a workstation, a server, a mobile device, etc. The memory controller300may correspond to the memory controller100inFIG.1, and thus repeated description will be omitted.

The memory controller200may control the memory module300. The memory controller200may transmit or issue a command CMD and an address ADD to the memory module for controlling the memory module400.

The memory module400may operate based on the command CMD and the address ADD transmitted by the memory controller300. The memory module400may store data transmitted from the memory controller300or may transmit data to the memory controller300. The memory module400may include a register clock driver410and a memory device420. The number of register clock drivers and the number of memory devices420are not limited to the example ofFIG.11, and the memory module400may include one or more register clock drivers and one or more memory devices.

The register clock driver410may be connected to one or more memory devices420to drive the one or more memory devices420. The register clock driver420may buffer the command CMD and the address ADD received from the memory controller300, and may transmit the buffered command CMD and the buffered address ADD to the memory devices420.

The register clock driver410may include a command buffer411transmitting the command CMD to the memory devices420and an address buffer412transmitting the address ADD to the memory devices420. The register clock driver410may output the command CMD from the command buffer411and the address ADD from the address buffer412to the memory device420as an internal command ICMD and an internal address IADD.

The register clock driver410may be a buffer chip for transmitting the command CMD and the address ADD of the memory controller300to the memory devices420. The memory devices420may receive the internal command ICMD and the internal address IADD from the memory controller300through the register clock driver410instead of receiving the command CMD and the address ADD directly from the memory controller300. The register clock driver410may improve signal integrity (SI) of the command CMD and the address ADD transmitted from the memory controller300to the memory devices420.

The register clock driver410may further include a control logic circuit413. The control logic circuit413may correspond to the control logic circuit230described with reference toFIGS.1through10.

The control logic circuit413may generate the internal command ICMD and the internal address IADD associated with a row hammer refresh operation in response to a refresh command received through the command buffer411. For example, the control logic circuit413may sample addresses accessed during a sampling period which is randomly determined, may determine a maximum access address based on sample addresses and may generate the internal address IADD based on the maximum access address.

The memory devices420may operate based on the internal command ICMD and the internal address IADD received from the register clock driver410.

The memory devices420may perform a refresh operation based on the internal command ICMD and the internal address IADD associated with a normal refresh operation and/or a row hammer refresh operation. The memory devices420may employ the memory device200ofFIG.4. The memory devices420may include a memory cell array, a row decoder, a column decoder, a sense amplifier/write driver and a data I/O buffer. The memory devices420may refresh target memory cells in the memory cell array through the row hammer refresh operation. Therefore, the memory devices420may prevent data stored in the target memory cells from being lost due to a specified word-line being intensively accessed.

FIG.12is a block diagram illustrating an example of a memory system according to an exemplary embodiment of the inventive concept.

Referring toFIG.12, a memory system1000may include a memory controller1100and a memory module1200.

The memory module1200may include a register clock driver1210, memory devices1220, and data buffers1230. The register clock driver1210may be implemented by using one of a SoC, an application specific integrated circuit (ASIC) and a field-programmable gate array (FPGA).

The register clock driver1210may receive the command CMD and the address ADD from the memory controller1100. The register clock driver1210may transmit internal command ICMD and an internal address IADD to the memory devices1220based on the command CMD and the address ADD.

For example, the register clock driver1210may transmit the command CMD and the address ADD to the memory devices1220or generate the internal command ICMD and the internal address IADD based on the command CMD and the address ADD and transmit the internal command ICMD and the internal address IADD to the memory devices1220.

For example, the register clock driver1210may correspond to the register clock driver410inFIG.11. In this case, the register clock driver1210may generate the internal command ICMD and the internal address IADD associated with a row hammer refresh operation based on the command CMD and the address ADD.

Each of the memory devices1220may operate based on the internal command ICMD and the internal address IADD received from the register clock driver1210.

Each of the memory devices1220may correspond to the memory device200inFIG.1or the memory device400inFIG.11.

When each of the memory devices1220corresponds to the memory device200inFIG.1, each of the memory devices1220may generate the refresh control signal RCS and the refresh address RADD associated with a row hammer refresh operation based on the internal command ICMD and the internal address IADD. Each of the memory devices1220may perform a row hammer refresh operation based on the refresh address RADD. When each of the memory devices1220corresponds to the memory device420inFIG.11, each of the memory devices1220may perform a refresh operation based on the internal command ICMD and the internal address IADD.

The memory devices1220may share a path for receiving the internal command ICMD and the internal address IADD. In an exemplary embodiment, the memory devices disposed in a first side with respect to the register clock driver1210shares a first path for receiving the internal command ICMD and the internal address IADD and the memory devices disposed in a second side with respect to the register clock driver1210shares a second path for receiving the internal command ICMD and the internal address IADD. For example, the memory devices located to the left of the register clock driver1210may correspond to the memory devices in the first side and the memory devices to the right of the register clock driver1210may correspond to the memory devices in the right side.

Each of the memory devices1220may communicate data signals DQ with the memory controller1100through the data buffer1230. Each of the memory devices1220may exchange data with the memory controller1100through the data buffer1230. The memory devices1220may be accessed in parallel by the memory controller1100. InFIG.12, it is illustrated as the memory module1200including nine memory devices1220, but embodiments of the inventive concept are not limited thereto.

FIG.13is a block diagram illustrating an example of a mobile system according to an exemplary embodiment of the inventive concept.

Referring toFIG.13, a mobile system2000may include a camera2100, a display2200, an audio processor2300, an I/O device2400, a memory device2500, a storage device2600, an antenna2700and an application processor (AP)2800.

The mobile system2000may be implemented with one of a laptop computer, a portable terminal, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device and internet of things (IoT). In addition, the mobile system2000may be implemented with a server or a PC.

The camera2100may capture an image or a video under control of a user. The camera2100may communicate with the AP2800through a camera interface (I/F)2870.

The display2200may include, for example, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an active matrix (AM)-OLED, or a plasma display panel (PDP). The display2200may receive input signals through a user's touch and may be used as an input device of the mobile system2000. The display2200may communicate with the AP2800through a display I/F2860.

The audio processor2300may process audio data in contents transferred from the memory device2500or the storage device2600. The audio processor2300may perform encoding/decoding or noise filtering on the audio data.

The I/O device2400may include various devices that provide a digital input and/or digital output such as a device to generate signal based on input of the user, a universal serial bus (USB), a digital camera, a secure digital (SD) card, a digital versatile disc (DVD) or a network adaptor. The audio processor2300and the I/O device2400may communicate with the AP2800through a peripheral I/F2850.

The AP2800may control overall operation of the mobile system2000through a central processing unit (CPU)2810.

The AP2800may control the display2200to display a portion of the contents stored in the storage device2600. In addition, when a user's input is received through the I/O device2400, the AP2800may perform control operation corresponding to the user's input. The AP2800may include a bus2890through which a modem2880, the CPU2810, an accelerator2820, a memory I/F2830, a storage I/F2840, the peripheral I/F2850, the display I/F2860and the camera I/F are connected to each other.

The AP2800may be implemented with an SoC to run an operating system (OS). The AP2800, a memory device2500and the storage device2600may be implemented by using packages such as package on package (PoP), ball gridarrays (BGAs), chip scale packages (CSPs), system in package (SIP), multi-chip package (MCP), wafer-level fabricated package (WFP), and wafer-level processed stack package (WSP), etc.

The AP2800may further include an accelerator2820. The accelerator2820may be a function block to perform a specified function. The accelerator2820may include a graphic processing unit (GPU) to process graphic data or a neural processing unit (NPU) to perform an artificial neural network operation such as training and/or inference.

The AP2800may include a modem2880or a modem chip disposed in an outside of the AP2800. The modem2880receives and/or transmits wireless data through an antenna2700, modulates signals to be transmitted to the antenna2700and demodulates signals received from the antenna2700.

The AP2800may include a memory I/F2830to communicate with the memory device2500. The memory I/F2830may include a memory controller to control the memory device2500and the memory device2500may be directly connected to the AP2800. The memory controller in the memory I/F2830may control the memory device2500by changing read/write instructions from the CPU2810, the accelerator2820or the modem2880to commands for controlling the memory device2500.

The AP2800may communicate with the memory device2500through a predefined interface protocol. The AP2800may communicate with the memory device2500through an interface protocol such as LPDDR4 or LPDDR5 conformed to JEDEC standards. The AP2800may communicate with the memory device2500through an interface protocol such as HBM, HMC or Wide I/O conformed to high bandwidth JEDEC standards.

For example, the memory device2500may be implemented with a DRAM device, but exemplary embodiments of the inventive concept are not limited thereto. The memory device2500may include memory cells of SRAM, PRAM, MRAM, FRAM, a hybrid RAM, and a NAND flash memory.

The memory device2500may have a relatively smaller latency and bandwidth than the I/O device2400and the storage device2600. The memory device2500may be initialized at a timing of power on of the mobile system2000and an OS and application data are loaded into the memory device2500. The memory device2500may be used for temporarily storing the OS and application data or a space for executing software.

In exemplary embodiments, the memory device2500may correspond to the memory device200described with reference toFIGS.1through10. For example, the memory device2500may sample addresses accessed during a sampling period which is randomly determined based on the command and the address from the memory controller in the AP2800, may determine a maximum access address based on sample addresses and may perform a row hammer refresh operation based on the maximum access address.

The AP2800may include a storage I/F2840to communicate with the storage device2600and the storage device2600may be directly connected to the AP2800. The storage device2600may be provided as a separate chip and the AP2800and the storage device2600may be fabricated into one package. The storage device2600may be implemented with a NAND flash memory, but example embodiments are not limited thereto.