Semiconductor apparatus and method for fabricating the same

A semiconductor apparatus includes a semiconductor integrated circuit including a conductive pattern; an insulating layer which is formed on the semiconductor integrated circuit to forms a plurality of base members having uneven heights; an opening which is formed through the insulating layer to expose a part of the conductive pattern; and a conductive layer which is formed on the insulating layer and the opening, the conductive layer is extending from the exposed portion of the conductive pattern to the top surface of the highest base member. An electrode is composed of the insulating layer, the opening and the conductive layer.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor apparatus and a method for fabricating the same, and more particularly to an electrode structure of a semiconductor integrated circuit and a method for fabricating the same. The invention further relates to a method and a structure for mounting a semiconductor substrate.

BACKGROUND OF THE INVENTION

Conventionally, for mounting process of a semiconductor integrated circuit to a connection substrate, a tape carrier package structure, a chip on board structure and a chip on glass structure have been used. According to those structures, the space between the semiconductor substrate and the connection substrate are filled with a seal resin. For an electrode structure in such a mounting structure, a bump bonding structure using a bump electrode has been used. The bump electrode may be a metal bump electrode, such as a gold (Au) bump electrode, a solder electrode made of an alloy of lead (Pb) and tin (Sn), and the like.

Such a metal bump electrode is deformed plastically, and the alloy of Pb—Sn may be broken from its crystal surface. The difference of the thermal expansion coefficients between the semiconductor substrate and the connection substrate makes some thermal stress in the electrode. Such thermal stress can be also made by the difference of the thermal expansion coefficients between the seal resin and the bump electrode itself. The thermal stress makes thermal fatigue in the electrode, and therefore the electrode may be broken in some cases. The semiconductor integrated circuit is metal-plated, then the metal plate is etched to form the bump electrode. In the semiconductor substrate, a region which is uncovered with a protection layer, such as a trimming circuit, may be seriously affected by the plating process and etching process. Such a conventional electrode structure does not have high enough reliability of electrical connection, because the surface of the semiconductor integrated circuit is not enough protected.

OBJECTS OF THE INVENTION

Accordingly, an object of the invention is to provide a semiconductor apparatus and a method for fabricating the same, in which an electrode has a high reliability of electrical connection.

Another object of the invention is to provide a semiconductor apparatus and a method for fabricating the same, in which the surface of the semiconductor integrated circuit can be protected sufficiently after an electrode is formed.

SUMMARY OF THE INVENTION

According to a first aspect of the invention, a semiconductor apparatus includes a semiconductor integrated circuit including a conductive pattern; an insulating layer which is formed on the semiconductor integrated circuit to forms a plurality of base members having uneven heights; an opening which is formed through the insulating layer to expose a part of the conductive pattern; and a conductive layer which is formed on the insulating layer and the opening, the conductive layer is extending from the exposed portion of the conductive pattern to the top surface of the highest base member. An electrode is composed of the insulating layer, the opening and the conductive layer.

According to a second aspect of the invention, a semiconductor apparatus includes a semiconductor substrate including a semiconductor integrated circuit, and an electrode, which is composed of a base member of insulating material formed on the semiconductor integrated circuit and a conductive layer formed on the surface of the base member; a connection substrate on which the semiconductor substrate is mounted with a face-down technique; and a seal member which is filled in the space between the semiconductor substrate and the connection substrate. The base member and the seal member are made of the same material.

According to a third aspect of the invention, in a method for fabricating a semiconductor apparatus, an insulating layer is formed on a semiconductor integrated circuit. Then, an opening is formed through the insulating layer to expose a part of a conductive pattern. A conductive layer is formed over the insulating layer with the opening; the conductive layer is patterned except a portion extending from the exposed part of the conductive pattern to a predetermined portion of the insulating layer; and the insulating layer is shaped at the portion uncovered with the conductive layer to have a height lower than the portion covered with the conductive layer.

According to a fourth aspect of the invention, in a method for fabricating a semiconductor apparatus, a semiconductor substrate is fabricated to include a semiconductor integrated circuit, and an electrode, which is composed of a base member of insulating material formed on the semiconductor integrated circuit and a conductive layer formed on the surface of the base member. The semiconductor substrate is placed to be face-down to a connection substrate; then the electrode is connected to the connection substrate. Nest, a seal member is filled in the space between the semiconductor substrate and the connection substrate. The base member and the seal member are made of the same material.

According to the first and third aspects of the invention, the semiconductor integrated circuit is protected by the base members. Further, the electrode is prevented from being broken due to a thermal stress and thermal fatigue, because the electrode to be connected to another substrate is formed on the top surface of the highest (tallest) base member. As a result, the semiconductor apparatus can be fabricated to have a high reliability.

According to the second and fourth aspects of the invention, the space between the semiconductor substrate and the connection substrate is filled with the seal member that is made of the same material of the base member, so that the base member and the seal member have the same thermal expansion coefficient. As a result the electrode is prevented from being broken due to a thermal stress and thermal fatigue, and therefore, the semiconductor apparatus can be fabricated to have a high reliability.

DETAILED DISCLOSURE OF THE INVENTION

FIGS. 1A and 1Bshow an electrode structure of a semiconductor apparatus according to a first preferred embodiment of the invention. A conductive pattern101and a surface protection layer102are first formed on a semiconductor-integrated-circuit substrate100, which is a silicon wafer, to provide a semiconductor integrated circuit. The semiconductor-integrated-circuit substrate100is hereinafter called “semiconductor substrate100.” A reference number103shows a traction portion of the conductive pattern101. The conductive pattern101is made of aluminum (Al) or an alloy of aluminum (Al) and silicon (Si), copper (Cu) or the like. The surface protection layer102is formed to cover the surface of the semiconductor integrated circuit for protection. The surface protection layer102is made of silicon oxide (SiO2), silicon chloride (SixNy), or the like. The traction portion103may be located on a pad of the conductive pattern, such as a bonding pad, or at via-hole (not shown).

On the semiconductor integrated circuit, a plurality of base members104aand104bare formed to have the different heights. These base members104aand104bare made of insulating material, such as polyimide resin. An conductive layer105is formed on the semiconductor integrated circuit. An opening106is formed around the higher (taller) base member104a. The base members104aand104b, the conductive layer105and the opening106compose an electrode of the semiconductor integrated circuit. The top surface104b-aof the lower (shorter) base member104bis designed to be “ΔT” lower in position than the top surface104a-aof the base member104a. The shape of the top surface104a-ais not limited by square.

The opening106is formed between the higher base member104aand lower base member104bover the traction portion103to expose the conductive pattern101. As shown inFIGS. 1A and 1B, the opening106is formed to surround the higher base member104aand to separate the base members104aand104bfrom each other. The opening106can be designed not to surround the base member104a, as long as it exposes the conductive pattern101. The base members104aand104bcan be designed not to be separated from each other, as long as those have the different heights.

The conductive layer105is formed over the base member104a, the conductive pattern101and the surface protection layer102to make a connection terminal of the conductive pattern101at the top of the higher base member104a. InFIGS. 1A and 1B, although the conductive layer105entirely covers the higher base member104a, some regions on the surface of the base member104can be uncovered with the conductive layer105. The conductive layer105is of metal or an alloy, which is selected with consideration of a connecting process to a connection substrate (300,301). The conductive layer105may be designed to have a single layer structure or multi-layered structure. For example, the conductive layer105may be designed to have a single layer structure of gold (Au), copper (Cu), an alloy of lead (Pb) and tin (Sn), and the like; or to have a double-layered structure of gold (Au) and nickel (Ni), hereinafter indicated by Ni/Au layer, or of gold (Au), titan (Ti) and tungsten (W), hereinafter indicated by Ti—W/Au layer.

The higher base member104a, the conductive layer105and the opening106forms an electrode section107. The lower base member104bforms a surface protecting section108, which protects the surface of the semiconductor integrated circuit. The lower base members104bcan be designed to have the different heights from each other, as long as the higher base member104ais the highest. In other words, there can be more than three different heights of base members including the highest base member.

Now, the fabrication steps of the electrode structure shown inFIGS. 1A and 1Bare described in conjunction withFIGS. 2Ato2D. Referring toFIG. 2A, the conductive pattern101, the surface protection layer102are formed on the semiconductor substrate100. Then, an insulating layer204, which is of hardenable polyimide resin, is coated on the entire structure using a spin coating technique. Next, the opening106is formed through the insulating layer204to expose the conductive pattern101and to shape the higher base member104a. After that, the insulating layer204is baked at 350° C. to be hardened.

Referring now toFIGS. 2B and 2C, the conductive layer205is formed over the insulating layer204, which is provided with the opening106. The conductive layer205is patterned to remove unnecessary portions, so that the conductive pattern105is formed on an area extending from the conductive pattern101to the top surface104a-aof the higher base member104a. In more detail, the conductive layer205of copper is formed over the insulating layer204by spattering technique, and a photo-resist207is patterned on the conductive layer205. Then, the conductive layer205is patterned by wet-etching technique using the photo-resist207as an etching mask.

Next, referring toFIG. 2D, the insulating layer204is shaved at portions that is not covered with the conductive layer105(205) to form the lower base members104b. As a result, the electrode is formed on the semiconductor substrate100, shown inFIGS. 1A and 1B. Thus fabricated semiconductor substrate100is mounted to the connection substrate. InFIGS. 1A and 1B, the conductive pattern105located at the top surface104a-aof the higher base member104ais to be connected to the connection substrate. The lower base member104bis not connected to the connection substrate. The space between the lower base member104band the connection substrate may be filled with a seal resin.

FIG. 3Ashows the positional relation between the electrode structure of the first preferred embodiment and a lead301of a connection substrate, such as a tape carrier.FIG. 3Bshows the positional relation between the electrode structure of the first preferred embodiment and a conductive wire302of a connection substrate300. InFIG. 3A, the conductive layer105is bonded to the lead301by a thermal-compression bonding technique. InFIG. 3B, the conductive layer105is bonded to the conductive wire302by a reflow technique.

According to the above described first preferred embodiment, the semiconductor integrated circuit is covered entirely with the base members104aand104b, which are made of insulating material, so that the surface of the semiconductor integrated circuit is enough protected when the electrode is fabricated and when the bonding process is performed, especially at an area where the surface protection layer102is not formed. The top surface104a-aof the higher base member104bis designed to be ΔT higher than that of the lower base member104b, so that the conductive layer105at the top surface104a-acan be bonded to the connection substrate easily.

The base member104ais made of polyimide resin, which has a polymeric structure having an elastic limit higher than metal, so that the electrode section107is not plastically deformed, just elastically deformed in response to stress or thermal stress generated in the bonding process. As a result, the electrode is prevented from being broken due to thermal fatigue, and therefore, the reliability of the electrode improves.

The conductive layer105to be bonded is apart from the conductive pattern101by the height of the base member104a, so that the electrode can be prevented from deterioration due to metal diffusion at the connected face between the conductive layer105and the conductive pattern101even if the electrode is bonded by thermal-compression technique. As a result, an extra metal layer for preventing metal diffusion, which is required for a bump electrode, can be omitted in this embodiment. The base member104acan be formed not only over the traction portion103but also over the surface protection layer102, therefore, the top surface104a-aof the base member104can be freely designed in size and shape independently from the size and shape of the traction portion103.

FIGS. 4A and 4Bshow an electrode structure of a semiconductor apparatus according to a second preferred embodiment of the invention. In those figures, the same or corresponding components to those in the first preferred embodiment are represented by the same reference numbers, and the same description is not repeated for avoiding redundant description. In the second preferred embodiment, a higher base member404aand lower base members404bare formed on a semiconductor substrate100so that the higher base member404ais ΔT higher than the lower base members104b. An opening406is formed through the higher base member404aand the lower base member404b. A conductive layer405is formed over the semiconductor integrated circuit to extend from a conductive pattern101to the top surface404a-aof the higher base member404a. The higher and lower base members404aand404bare made of polyimide resin. The conductive layer405is made of the same material as the conductive layer105, shown inFIGS. 1A and 1B.

As shown inFIG. 4B, the higher base member404aand lower base member404bare formed in one united body, which is one feature of the embodiment. Another feature of the embodiment is that the conductive layer405is not formed over the base members404aand404bentirely. In more detail, the conductive layer405is not formed on the top surface of the lower base member404bnor on the side surface404a-bof the higher base member404a. The opening406is designed not to surround the higher base member404a, in contrast the opening106of the first preferred embodiment is surrounding the higher base member104a. The higher base member404a, the conductive layer405and the opening compose an electrode section407. The lower base member404bcomposes a surface protecting section408, which protects the surface of the semiconductor substrate100.

Now, the fabrication steps of the electrode structure shown inFIGS. 4A and 4Bare described in conjunction withFIGS. 5Ato5D. Referring toFIG. 5A, the conductive pattern101, the surface protection layer102are formed on the semiconductor substrate100. Then, an insulating layer204, which is of hardenable polyimide resin, is coated over the entire structure. Next, the opening406is formed through the insulating layer204to expose the conductive pattern101and to shape a part of the higher base member404a.

Referring now toFIGS. 5B and 5C, the conductive layer205is formed over the insulating layer204and the conductive pattern101at the bottom of the opening406. The conductive layer205is patterned to remove unnecessary portions, so that the conductive pattern405is formed on an area extending from the conductive pattern101to the top surface404a-aof the higher base member404a. In more detail, the conductive layer205of copper is formed over the insulating layer204by spattering technique, and a photo-resist207is patterned on the conductive layer205. Then, the conductive layer205is patterned by wet-etching technique using the photo-resist207as an etching mask.

Next, referring toFIG. 5D, the insulating layer204is shaved at portions that is not covered with the conductive layer405(205) to complete the higher and lower base members404aand404b. As a result, the electrode is formed on the semiconductor substrate100, shown inFIGS. 4A and 4B. Thus fabricated semiconductor substrate100is mounted to a connection substrate (300). InFIGS. 4A and 4B, the conductive pattern405located at the top surface404a-aof the higher base member404ais to be connected to the connection substrate. The space between the lower base member404band the connection substrate may be filled with a seal resin.

FIG. 6Ashows the positional relation between the electrode structure of the second preferred embodiment and a lead301of a connection substrate, such as a tape carrier.FIG. 6Bshows the positional relation between the electrode structure of the second preferred embodiment and a conductive wire302of a connection substrate300. The conductive layer405is bonded to the lead301or the conductive wire302by thermal-compression bonding technique, reflow technique, or the like.

According to the above described second preferred embodiment, the higher and lower base members404aand404bare not covered with the conductive layer405entirely, so that a stress, generated due to elastic deformation in the bonding process, and a gas, generated in thermal processes for fabricating the electrode, can go off easily. As a result, the conductive layer405is not broken easily, and therefore, the electrode has a high connection reliability.

Even though the higher base member404ais entirely covered with the conductive layer as shown inFIGS. 2Ato2D, the above mentioned advantage can be obtained. Further, even though the higher base member104ais separated from the lower base member104bas shown inFIGS. 1A and 1B, the above mentioned advantage can be obtained as long as the higher base members104ais expose in part.

FIG. 7shows an electrode structure of a semiconductor apparatus according to a third preferred embodiment of the invention. InFIG. 7, the same or corresponding components to those in the first and second preferred embodiments are represented by the same reference numbers, and the same description is not repeated for avoiding redundant description. In the third preferred embodiment, a surface protection layer is not formed on a semiconductor substrate100, instead base member404bitself is functioning as a protection layer. That is the difference from the second preferred embodiment. An opening406is formed through the higher base member404aand the lower base member404b. A conductive layer405is formed over the semiconductor integrated circuit to extend from a conductive pattern101to the top surface of the higher base member404a. The higher and lower base members404aand404bare made of polyimide resin. The conductive layer405is made of the same material as the conductive layer105, shown inFIGS. 1A and 1B.

As shown inFIG. 7, the higher base member404aand lower base member404bare formed in one united body and the conductive layer405is not formed over the base members404aand404bentirely, in the same manner as the second preferred embodiment. The electrode is connected to a connection substrate in the same manner as the second preferred embodiment, shown inFIGS. 6A and 6B.

FIGS. 8A and 8Bshow steps for fabricating the electrode structure of the semiconductor apparatus shown in FIG.7. In those figures, the same or corresponding components to those in the first and second preferred embodiments are represented by the same reference numbers, and the same description is not repeated for avoiding redundant description.

In fabrication, as shown inFIG. 8A, the conductive pattern101is first formed on the semiconductor substrate100. Then, an insulating layer204, which is of hardenable polyimide resin, is coated over the entire structure. Next, the opening406is formed through the insulating layer204to expose the conductive pattern101and to shape a part of the higher base member404a. After the formation of the opening406, the insulating layer204is hardened.

Next, the conductive layer205(not shown) is formed over the insulating layer204and the conductive pattern101at the bottom of the opening406. The conductive layer205is patterned to remove unnecessary portions, so that the conductive pattern405is formed along an area extending from the conductive pattern101to the top surface of the higher base member404a, as shown in FIG.8B. In more detail, the conductive layer205of copper is formed over the insulating layer204by spattering technique, and a photo-resist (not shown) is patterned on the conductive layer205. Then, the conductive layer205is patterned to form the conductive layer405by a wet-etching technique using the photo-resist as an etching mask. Substantially, the insulating layer204is shaved at portions that is not covered with the conductive layer405(205) to complete the higher and lower base members404aand404b. As a result, the electrode is formed on the semiconductor substrate100, shown in FIG.7. Thus fabricated semiconductor substrate100is mounted to a connection substrate (not shown). The conductive pattern405located at the top surface of the higher base member404ais to be connected to the connection substrate. The space between the lower base member404band the connection substrate may be filled with a seal resin.

According to the above described third preferred embodiment, the insulating layer204, especially the lower base member404b, is functioning as a protection layer, so that the surface protection layer (102), used in the first and second preferred embodiments, can be omitted. As a result, the fabrication process of the semiconductor apparatus is simplified, and therefore, the cost of fabrication can be reduced.

FIGS. 9A and 9Bshow steps for fabricating an electrode structure of a semiconductor apparatus, according to a fourth preferred embodiment of the invention. In those figures, the same or corresponding components to those in the first to third preferred embodiments are represented by the same reference numbers, and the same description is not repeated for avoiding redundant description.FIGS. 9A and 9Bespecially show the steps for forming an insulating layer504and an opening406. The semiconductor apparatus of the fourth preferred embodiment is designed to have the same structure as the second preferred embodiment. The steps for fabricating the electrode of the fourth preferred embodiment is similar to those of the second preferred embodiment. In the fourth preferred embodiment, however, the insulating layer504is made of photo-sensitive resin, and the opening406is formed by lithographic technique.

In more detail, as shown inFIG. 9A, a conductive pattern101and a surface protection layer102are first formed on a semiconductor substrate100. Then, the insulating layer504, which is of photo-sensitive polyimide resin, is coated over the entire structure using a spin coating technique. Next, an exposure light501is applied to the insulating layer504at a region where the opening406is to be formed. The exposure light501includes a wavelength that is sensitive to the polyimide resin, which composes the insulating layer504.

Next, the insulating layer504is dipped in a developer liquid to remove the exposed portion to form the opening406, so that the conductive pattern101is exposed. The semiconductor substrate100(wafer) is baked at 350° C. to be hardened. After that, the steps shown inFIGS. 5Bto5D are performed. Thus fabricated semiconductor substrate100is mounted to a connection substrate (not shown).

According to the above described fourth preferred embodiment, the opening406is formed using the lithographic technique, so that the opening406can be shaped more precisely, finely and efficiently as compared to with a mechanical formation technique. The method for shaping the opening according to the fourth preferred embodiment is applicable to the first and third preferred embodiments.

FIGS. 10A and 10Bshow steps for fabricating an electrode structure of a semiconductor apparatus, according to a fifth preferred embodiment of the invention. In those figures, the same or corresponding components to those in the first to fourth preferred embodiments are represented by the same reference numbers, and the same description is not repeated for avoiding redundant description.FIGS. 10A and 10Bespecially show the steps for forming an insulating layer604and an opening406. The semiconductor apparatus of the fifth preferred embodiment is designed to have the same structure as the second preferred embodiment. The steps for fabricating the electrode of the fourth preferred embodiment is similar to those of the second preferred embodiment. In the fourth preferred embodiment, however, the opening406is formed by a laser machining technique, which is the feature of the embodiment.

As shown inFIG. 10A, a conductive pattern101and a surface protection layer102are first formed on a semiconductor substrate100. Then, the insulating layer604, which is of polyimide resin, is coated over the entire structure. Next, a laser beam601is applied to the insulating layer604to burn it off at a region where the opening406is to be formed, so that the opening is well shaped.

Next, a baking treatment of 350° C. is applied to the insulating layer604, which is provided with the opening406, to harden the insulating layer604. After that, the steps shown inFIGS. 5Bto5D are performed. Thus fabricated semiconductor substrate100is mounted to a connection substrate (not shown).

According to the above described fifth preferred embodiment, the opening406is formed by the laser machining technique, so that the opening406can be shaped more precisely, finely and efficiently as compared to with a mechanical formation technique. The method for shaping the opening according to the fourth preferred embodiment is applicable to the first and third preferred embodiments.

FIGS. 11A and 11Bshow steps for fabricating an electrode structure of a semiconductor apparatus, according to a sixth preferred embodiment of the invention. In those figures, the same or corresponding components to those in the first to fifth preferred embodiments are represented by the same reference numbers, and the same description is not repeated for avoiding redundant description.FIGS. 11A and 11Bespecially show the steps for cutting off a part of an insulating layer604. The semiconductor apparatus of the sixth preferred embodiment is designed to have the same structure as the second preferred embodiment. The steps for fabricating the electrode of the fourth preferred embodiment is similar to those of the second preferred embodiment. In the fourth preferred embodiment, however, a part of the insulating layer604is cut of by a plasma-etching technique using a conductive layer405as an etching mask, which is the feature of the embodiment.

In fabrication, as shown inFIG. 11A, a conductive pattern101and a surface protection layer102are first formed on a semiconductor substrate100. Then, the insulating layer604, which is of polyimide resin, is coated over the entire structure, then the opening406is shaped. Next, the conductive layer405is formed on the conductive pattern101and a part of the insulating layer604, as shown in FIG.11A.

Referring now toFIG. 11B, a plasma etching process is performed to the semiconductor substrate100, having the conductive layer405, with an etching gas701mainly including oxygen (O2) using the conductive layer405as an etching mask. By the etching process, the insulating layer604is selectively etched to form higher and lower base members404aand404b. In other words, the insulating layer604is etched by ΔT at regions where the lower base members404bare to be formed, so that the lower base members404bare shaped to have heights ΔT lower than that of the higher base member404a. Thus fabricated semiconductor substrate100is mounted to a connection substrate (not shown).

According to the above described sixth preferred embodiment, the lower base members404bare shaped by the plasma etching technique, so that the difference of height ΔT (depth of etching) between the higher and lower base members404aand404bcan be precisely controlled.

FIG. 12shows an electrode structure of a semiconductor apparatus according to a seventh preferred embodiment of the invention. InFIG. 12, the same or corresponding components to those in the first to sixth preferred embodiments are represented by the same reference numbers, and the same description is not repeated for avoiding redundant description. The steps for fabricating the electrode of the seventh preferred embodiment is similar to those of the second preferred embodiment. In the seventh preferred embodiment, however, a trimming process is performed before the steps ofFIGS. 5Ato5D. The features of the embodiment are that an opening406is formed to expose a trimming pattern801, and a trimming pad802is covered with an insulating layer204.

In fabrication, as shown inFIG. 13A, a conductive pattern101, a surface protection layer102and the trimming pattern801are first formed on a semiconductor substrate100. Then, an electrical test is performed to the semiconductor integrated circuit. On the basis of the result of the test, a part of the trimming pattern801, which is exposed at the trimming pad802, is cut off.

Referring toFIG. 13B, an insulating layer204, which is of hardenable polyimide resin, is coated over the entire structure, and the opening406is formed through the insulating layer204to expose the conductive pattern101. After the formation of the opening406, the insulating layer204is hardened. The opening406is formed not over the trimming pad802so that the trimming pad802keeps to be protected by the insulating layer204. After that, the processes shown inFIGS. 5Bto5D are performed.

According to the above described seventh preferred embodiment, the trimming pattern801of the trimming pad802keeps to be covered with the insulating layer204even after the opening406is formed, so that the trimming pattern801can keep the condition when it is just formed. In other words, the trimming pattern801is not affected by any processes performed after the formation thereof, especially the processes for forming a conductive layer and of patterning.

FIG. 14shows an electrode structure of a semiconductor apparatus according to an eighth preferred embodiment of the invention. InFIG. 14, the same or corresponding components to those in the first to seventh preferred embodiments are represented by the same reference numbers, and the same description is not repeated for avoiding redundant description. The electrode structure of the eighth preferred embodiment is similar to that of the second preferred embodiment. The electrode structure of the eighth preferred embodiment, however, includes a bump electrode901on a conductive layer405at a top surface404a-aof a higher base member404a. The bump electrode901may be made of metal having a high melting point, such as gold (Au) and copper (Cu), or metal having a low melting point, such as Pb—Sn and indium (In).

The higher base member404a, the conductive layer405, an opening406and the bump electrode901compose an electrode section907. Lower base members404bcompose surface protecting sections408. It is assumed that the bump electrode901is designed to have a height of “H,” a connecting level of the electrode section907is “H” higher than that of the second preferred embodiment. The bump electrode901is usually formed after the steps shown inFIGS. 5Ato5D are completed.

FIG. 15Ashows the positional relation between the electrode structure of the eighth preferred embodiment and a lead301of a connection substrate, such as a tape carrier.FIG. 15Bshows the positional relation between the electrode structure of the eighth preferred embodiment and a conductive wire302of a connection substrate300. The bump electrode901of the electrode section907is bonded to the lead301or the conductive wire302by thermal-compression bonding technique, reflow technique, or the like.

According to the above described eighth preferred embodiment, the semiconductor apparatus is provided with the bump electrode901on the conductive layer405at the top surface of the higher base member404a, so that the distance to the lead301or conductive wire302becomes wider, as compared to the electrode structure of the second preferred embodiment. As a result, a thermal stress is easily absorbed, and therefore, the semiconductor apparatus can be fabricated to have a high reliability. If the bump electrode901is made of solder, the electrode can be roughly connected to the connection substrate because of a self-alignment effect.

FIG. 16shows a part of a semiconductor apparatus, according to a ninth preferred embodiment of the invention. In this embodiment, a semiconductor substrate1000is mounted to a connection substrate300with a face-down mounting technique, and the space between the substrates1000and300are filled with a seal resin1001. The seal resin1001may be made of polyimide resin. The semiconductor substrate1000is provided with an electrode section107, which consists of a base member1004and a conductive layer1005. The base member1004may be made of a polyimide resin. The main feature of the embodiment is that the seal resin1001and the base member1004are made of the same material, polyimide resin.

In a conventionally semiconductor apparatus, a semiconductor substrate with a metal bump electrode is mounted to a connection substrate with the face-down technique, and the space between the substrates are filled with a seal resin. According to such a conventional semiconductor apparatus, however, a thermal stress is generated because of the difference of thermal expansion coefficients between the bump electrode and the seal resin. As a result, the bump electrode is extended with the thermal stress and may be broken due to a thermal fatigue.

In contrast, according to the ninth preferred embodiment, the seal resin1001and the base member1004are made of the same material, polyimide resin, so that the electrode section1007is prevented from being broken. Consequently, the apparatus according to the embodiment can be fabricated to have a high reliability.

It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended with the meaning and range of equivalents of the appended claims.