Printed circuit board

A printed circuit board according to an embodiment includes: a first insulating portion having a cavity; a second insulating portion disposed on the first insulating portion; a third insulating portion disposed under the first insulating portion; and an electronic device disposed in the cavity, wherein a number of layers of the second insulating portion is different from a number of layers of the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is the U.S. national stage application of International Patent Application No. PCT/KR2019/017333, filed Dec. 10, 2019, which claims the benefit under 35 U.S.C. § 119 of Korean Application No. 10-2018-0158282, filed Dec. 10, 2018, the disclosures of each of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

An embodiment relates to a printed circuit board, and more particularly, to a printed circuit board embedding an electronic device.

BACKGROUND ART

Unlike conventional printed circuit boards in which passive devices and active devices share the surface of a printed circuit board, an embedded printed circuit board has devices such as resistors and capacitors embedded in the board. Since it is possible to secure a free space on a surface of the substrate, it is possible to increase a wiring density compared to the conventional printed circuit board, thereby enabling the development of a more compact electronic device.

In addition, these embedded printed circuit board has effect of reducing problems such as impedance generation and signal delay due to parasitic effects in electronic devices that use high-frequency signals because the elements are connected in a vertical direction and the wiring length is greatly reduced.

The core technology of such an embedded printed circuit board is a technology for embedding an element in the board and a technology for precisely connecting the embedded element and a wiring circuit.

In general, the embedded printed circuit board performs a cavity forming process of removing a device mounting area after forming the insulating layer. In the related art, an embedded printed circuit board is manufactured by mounting a device in the formed cavity and laminating an additional insulating layer on top and bottom of the insulating layer on which the device is mounted, respectively.

DISCLOSURE

Technical Problem

In the embodiment, a printed circuit board and a method of manufacturing the same are provided with an embedded electronic device having an asymmetric structure.

In addition, in the embodiment, an electronic device embedded printed circuit board and a manufacturing method thereof capable of improving design freedom while reducing the thickness of the substrate are provided.

The technical problems to be achieved in the proposed embodiment are not limited to the technical problems mentioned above, and other technical problems not mentioned may be clearly understood by those of ordinary skill in the art to which the proposed embodiment belongs from the following description.

Technical Solution

A printed circuit board according to an embodiment includes: a first insulating portion having a cavity; a second insulating portion disposed on the first insulating portion; a third insulating portion disposed under the first insulating portion; and an electronic device disposed in the cavity, wherein a number of layers of the second insulating portion is different from a number of layers of the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.

In addition, the first insulating portion includes at least one first insulating layer; a first circuit pattern buried in a lower part of the first insulating layer; a second circuit pattern disposed on an upper surface of the first insulating layer; and a first via disposed in the first insulating layer and connecting the first and second circuit patterns.

Further, the first insulating layer is formed of a prepared containing glass fibers.

In addition, the second insulating portion includes a second insulating layer disposed in the cavity and on the first insulating layer; a third circuit pattern disposed on an upper surface of the second insulating layer; and a second via disposed in the second insulating layer and connecting the second and third circuit patterns, wherein the second insulating layer is composed of an insulating material different from the insulating layer constituting the first insulating layer and the third insulating portion.

In addition, the second insulating layer is formed of RCC (Resin Coated Copper).

In addition, the third insulating portion may include a third insulating layer disposed under the first insulating layer; at least one fourth insulating layer disposed under the third insulating layer; a third via disposed in the third insulating layer; a fourth via disposed in the fourth insulating layer; a fourth circuit pattern disposed under a lower surface of the third insulating layer; and a fifth circuit pattern disposed under a lower surface of the fourth insulating layer, wherein the third insulating layer is formed of an insulating material different from the first, second, and fourth insulating layers.

In addition, the third insulating layer is formed of ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric).

In addition, the third insulating layer has a thickness smaller than each of the first insulating layer, the second insulating layer, and the fourth insulating layer.

In addition, the third via includes a first sub-third via overlapping the electronic device in a vertical direction and directly connected to a terminal of the electronic device, and a second sub-third via disposed at a position not overlapping the electronic device in a vertical direction, wherein the first sub-third via has a width smaller than that of the second sub-third via.

In addition, a width of the second sub-third via is same as a width of each of the first via, the second via, and the fourth via.

Meanwhile, a method of manufacturing a printed circuit board according to an embodiment includes forming a first insulating portion including at least one first insulating layer, a first circuit pattern buried in a lower part of the first insulating layer, and a second insulating layer disposed on an upper surface of the first insulating layer, and a first via disposed in the first insulating layer and connecting the first and second circuit patterns; forming a cavity passing the first insulating layer in the first insulating portion; forming a film layer under the first insulating portion; attaching an electronic device on the film layer exposed through the cavity; forming a second insulating portion on the first insulating portion, wherein the second insulating portion includes a second insulating layer disposed in the cavity and on the first insulating layer, a third circuit pattern disposed on an upper surface of the second insulating layer, and a second via disposed in the second insulating layer and connecting the second and third circuit patterns, removing the film layer; and forming a third insulating portion including a third insulating layer disposed under the first insulating portion, at least one fourth insulating layer disposed under the third insulating layer, a third via disposed in the third insulating layer, and a fourth via disposed in the fourth insulating layer, a fourth circuit pattern disposed under a lower surface of the third insulating layer, and a fifth circuit pattern disposed under a lower surface of the fourth insulating layer, wherein the forming of the third insulating portion includes forming a dummy insulating portion on the second insulating portion to correspond to each of the at least one fourth insulating layer, the fourth via, and the fifth circuit pattern, and removing the dummy insulating portion when the third insulating portion is formed, wherein the number of layers of the insulating layer constituting the second insulating portion is different from the number of layers of the insulating layer constituting the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.

In addition, the first and fourth insulating layers are formed of a prepreg containing glass fiber, the second insulating layer is formed of RCC (Resin Coated Cu), and the third insulating layer is ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric).

In addition, the third via includes a first sub-third via overlapping the electronic device in a vertical direction and directly connected to a terminal of the electronic device, and a second sub-third via disposed at a position not overlapping the electronic device in a vertical direction, wherein the first sub-third via has a width smaller than that of the second sub-third via, and a width of the second sub-third via is same as widths of the first via, the second via and the fourth via.

Effects of the Invention

According to an embodiment, the printed circuit board includes a first insulating portion in which a cavity in which an electronic device is disposed is formed. In addition, a circuit pattern or a pad is buried and disposed in the first insulating portion. Accordingly, as the circuit pattern or the pad is buried and disposed in the first insulating portion, the thickness of the printed circuit board can be reduced by the thickness of the circuit pattern compared to the prior art, and design freedom can be improved. In addition, since the first insulating portion uses a prepreg including glass fiber, it is possible to minimize the occurrence of panel cracking or warping that occurs when manufacturing a thin substrate.

Further, according to an embodiment, a second insulating portion is disposed under the first insulating portion of the printed circuit board. At this time, the second insulating portion is configured to form an insulating layer using a film-type resin (for example, ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric) which is a photosensitive insulating material) in a region in direct contact with the first insulating portion. Accordingly, in the embodiment, the thickness of the insulating layer of the second insulating portion may be reduced compared to the prior art, and design freedom may be improved.

In addition, according to an embodiment, a small via may be formed by forming the second insulating portion on the area in direct contact with the first insulating portion with a film-type resin, and thus a fine pattern may be implemented.

In addition, the prior art has a vertical symmetry structure as the chip is placed in the center. On the other hand, according to an embodiment, a fan out panel level package (fan pit panel level package) structure may be implemented with an asymmetric structure.

BEST MODE

However, the spirit and scope of the present invention is not limited to a part of the embodiments described, and may be implemented in various other forms, and within the spirit and scope of the present invention, one or more of the elements of the embodiments may be selectively combined and replaced.

In addition, unless expressly otherwise defined and described, the Willis used in the embodiments of the present invention (including technical and scientific terms may be construed the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and the terms such as those defined in commonly used dictionaries may be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art. Further, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention.

In this specification, the singular forms may also include the plural forms unless specifically stated in the phrase, and may include at least one of all combinations that may be combined in A, B, and C when described in “at least one (or more) of A (and), B, and C”. Further, in describing the elements of the embodiments of the present invention, the terms such as first, second, A, B, (a), and (b) may be used.

These terms are only used to distinguish the elements from other elements, and the terms are not limited to the essence, order, or order of the elements. In addition, when an element is described as being “connected”, “coupled”, or “contacted” to another element, it may include not only when the element is directly “connected” to, “coupled” to, or “contacted” to other elements, but also when the element is “connected”, “coupled”, or “contacted” by another element between the element and other elements.

In addition, when described as being formed or disposed “on (over)” or “under (below)” of each element, the “on (over)” or “under (below)” may include not only when two elements are directly connected to each other, but also when one or more other elements are formed or disposed between two elements. Further, when expressed as “on (over)” or “under (below)”, it may include not only the upper direction but also the lower direction based on one element.

FIG. 1is a view illustrating a structure of a printed circuit board according to an embodiment.

Referring toFIG. 1, the printed circuit board may include a first insulating portion, a second insulating portion, and a third insulating portion. The first insulating portion may include a central insulating layer, the second insulating portion may include an upper insulating layer disposed on the first insulating portion, and the third insulating portion may include a lower insulating layer disposed under the first insulating portion.

The first insulating portion includes an insulating layer in which the electronic device300is buried. To this end, the first insulating portion may include a first insulating layer110and a second insulating layer125. In addition, a cavity C in which the electronic device300is disposed may be formed in the first insulating layer110and the second insulating layer125. In this case, the first insulating portion may be referred to as a core insulating portion, and accordingly, the first insulating layer110and the second insulating layer125may be referred to as a core insulating layer.

The first insulating layer110and the second insulating layer125are substrates on which electric circuits capable of changing wiring are arranged, and this may include all of a printed circuit board, a wiring board, and an insulating substrate made of an insulating material capable of forming at least one circuit pattern on a surface.

The first insulating layer110and the second insulating layer125may include glass or plastic. In detail, the first insulating layer110and the second insulating layer125include chemically strengthened/semi-tempered glass such as soda lime glass or aluminosilicate glass, or strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) and polycarbonate (PC), or sapphire.

In this case, a plurality of circuit patterns may be disposed on surfaces of the first insulating layer110and the second insulating layer125.

A first circuit pattern105may be buried in a lower part of the first insulating layer110. A second circuit pattern120may be disposed on an upper surface of the first insulating layer110. Also, a third circuit pattern135may be disposed on an upper surface of the second insulating layer125. In this case, when the first insulating layer110and the second insulating layer125are viewed as one insulating layer, a lower circuit pattern disposed under the insulating layer is buried and disposed in the insulating layer, and an upper circuit pattern disposed above the insulating layer is disposed to protrude on the insulating layer. That is, in the related art, both the upper and lower circuit patterns are formed to protrude from the upper and lower surfaces of the insulating layer. On the contrary, in the embodiment, the first circuit pattern105may be buried in a lower part of the first insulating layer110. Accordingly, in the embodiment, the thickness of the insulating layer (to be described later)150disposed under the first insulating layer110can be reduced by the thickness of the first circuit pattern105. That is, basically, since the insulating layer is disposed while covering the circuit pattern, the thickness of the circuit pattern is determined as the basic offset thickness. On the other hand, in the embodiment, as the first circuit pattern105is buried and disposed in a lower part of the first insulating layer110, the thickness of the insulating layer to be laminated under the first insulating layer110may be reduced by about 12 to 18 μm compared to the prior art.

In addition, the first circuit pattern105, the second circuit pattern120, and the third circuit pattern135are wires that transmit electrical signals, and may be formed of a metal material having high electrical conductivity. To this end, the first circuit pattern105, the second circuit pattern120and the third circuit pattern135may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the first circuit pattern105, the second circuit pattern120, and the third circuit pattern135may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding power. Preferably, the first circuit pattern105, the second circuit pattern120, and the third circuit pattern135may be formed of copper (Cu) having high electrical conductivity and a relatively inexpensive price.

The first circuit pattern105, the second circuit pattern120, and the third circuit pattern135can be formed by an additive process, a subtractive process, MSAP (Modified Semi Additive Process) and SAP (Semi Additive Process) method or the like, which are typical printed circuit board manufacturing processes, and a detailed description thereof will be omitted.

A first via115is formed in the first insulating layer110. In addition, a second via130is formed in the second insulating layer125. The first via115and the second via130electrically connect circuit patterns disposed on different layers to each other. The first via115may electrically connect the first circuit pattern105and the second circuit pattern120. In addition, the second via130may electrically connect the second circuit pattern120and the third circuit pattern135.

The first via115and the second via130may penetrate only one of the first insulating layer110and the second insulating layer125, and alternatively, it may be formed while passing through at least two of the plurality of insulating layers in common. Accordingly, the first via115and the second via130electrically connect circuit patterns disposed on surfaces of different insulating layers to each other.

The first via115and the second via130may be formed by filling a through hole (not shown) passing through at least one of the first insulating layer110and the second insulating layer125with a conductive material.

The through hole may be formed by any one of mechanical, laser, and chemical processing. When the through hole is formed by machining, methods such as milling, drilling, and routing may be used, and when formed by laser processing, a UV or CO2 laser method may be used. In addition, when formed by chemical processing, at least one of plurality of insulating layers may be opened by using a chemical containing aminosilane, ketones, or the like.

Meanwhile, the laser processing is a cutting method that concentrates optical energy on a surface to melt and evaporate a part of the material to take a desired shape, accordingly, complex formations by computer programs can be easily processed, and even composite materials that are difficult to cut by other methods can be processed.

In addition, the laser processing has a cutting diameter of at least 0.005 mm, and has a wide range of possible thicknesses.

As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. YAG laser is a laser that can process both copper foil layers and insulating layers, and CO2 laser is a laser that can process only insulating layers.

When the through hole is formed, the first via115and the second via130may be formed by filling the inside of the through hole with a conductive material. The metal material forming the first via115and the second via130is selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the conductive material filling may use any one of electroless plating, electroplating, screen printing, sputtering, evaporation, ink jetting, and dispensing, or a combination thereof.

The electronic device300may be embedded in the cavity C commonly formed in the first insulating layer110and the second insulating layer125.

The electronic device300may be an electronic component such as a chip, and may be divided into an active device and a passive device. In addition, the active device is a device that actively uses a non-linear part, and the passive device refers to a device that does not use non-linear characteristics even though both linear and non-linear characteristics exist. In addition, the passive device may include a transistor, an IC semiconductor chip, and the like, and the passive device may include a capacitor, a resistor, and an inductor. The passive element is mounted on a conventional printed circuit board to increase a signal processing speed of a semiconductor chip, which is an active element, or to perform a filtering function.

The electronic device300may vary depending on the application to which the printed circuit board is applied. For example, when applied to a NAND flash memory product applied to a smartphone, the electronic device300may be a control device component.

A terminal310may be formed on a lower surface of the electronic device300. In this case, a lower surface of the terminal310may be disposed on the same plane as the lower surface of the first insulating layer110. The lower surface of the terminal310may be disposed on the same plane as the lower surface of the first circuit pattern105. Meanwhile, the upper surface of the electronic device300may be disposed on the same plane as the upper surface of the second insulating layer125. Preferably, the upper surface of the electronic device300may be disposed lower than the upper surface of the second insulating layer125. That is, the cavity C may have the same thickness as the electronic device300, and may have a thickness greater than the thickness of the electronic device300to improve reliability. Preferably, the cavity C may have a thickness greater than that of the electronic device300by about 10 μm. Accordingly, the upper surface of the electronic device300may be positioned lower than the upper surface of the second insulating layer125. In addition, the width of the cavity C may have a greater width than the width of the electronic device300for stable arrangement of the electronic device300.

Here, the first insulating portion compared to the existing structure, the first circuit pattern105has a structure buried in lower part of the first insulating layer110rather than a structure protruding from the lower surface of the first insulating layer110. This may be achieved by a differentiated manufacturing process in an embodiment, not a typical printed circuit board manufacturing process. This will be described in more detail below.

According to an embodiment, the printed circuit board includes a first insulating portion in which a cavity in which an electronic device is disposed is formed. In addition, a circuit pattern or a pad is buried in the first insulating portion and disposed. Accordingly, as the circuit pattern or the pad is buried and disposed in the first insulating portion, the thickness of the printed circuit board can be reduced by the thickness of the circuit pattern compared to the prior art, and design freedom can be improved. In addition, since the first insulating portion uses a prepreg including glass fiber, it is possible to minimize the occurrence of panel cracking or warping that occurs when manufacturing a thin substrate.

A second insulating portion may be disposed on the first insulating portion, and a third insulating portion may be disposed under the first insulating portion. In this case, in an embodiment, the second insulating portion may be composed of a single insulating layer, and the third insulating portion may be composed of a plurality of insulating layers.

In this case, the insulating layer constituting the second insulating portion, a part of insulating layers constituting the third insulating portion, and the insulating layer constituting the first insulating portion may all be formed of different insulating materials. That is, as described above, the first insulating layer110and the second insulating layer125of the first insulating portion are formed of a prepreg including glass fibers.

Alternatively, the third insulating layer140constituting the second insulating portion may be formed of Resin Coated Cu (RCC). In this case, the third insulating layer140is disposed on the second insulating layer125and is also disposed in the cavity C formed in the second insulating layer125and the first insulating layer110. That is, the third insulating layer140may be disposed on the second insulating layer125to have a predetermined thickness while filling the cavity C.

That is, as described above, the third insulating layer140must be disposed on the second insulating layer125with a uniform thickness while stably filling the cavity C. In this case, a curvature may be formed on the upper surface of the third insulating layer140according to the area of the cavity C. This is because the thickness of the third insulating layer140in the region where the cavity C exists and the region other than the region are different from each other. Accordingly, in an embodiment, by forming the third insulating layer140in the RCC type as described above, while solving the above problems, it is possible to manufacture a reliable substrate.

A fourth circuit pattern210may be disposed on an upper surface of the third insulating layer140. In addition, a third via225may be disposed in the third insulating layer140while passing through the third insulating layer140. The third via225may electrically connect the third circuit pattern135disposed on the second insulating layer125and the fourth circuit pattern210disposed on the third insulating layer140.

Meanwhile, a third insulating portion is disposed under the first insulating portion. Unlike the second insulating portion, the third insulating portion has a plurality of insulating layer structures. Accordingly, in an exemplary embodiment, the electronic device300may have an asymmetric structure with respect to the first insulating portion on which the electronic device300is disposed. That is, in the conventional structure, the upper insulating portion and the lower insulating portion have a symmetrical structure (same layer structure) with respect to the insulating portion in which the electronic device300is disposed. On the contrary, in the embodiment, by applying a manufacturing process differentiated from the conventional manufacturing process, the second insulating portion and the third insulating portion have a mutually asymmetric structure with respect to the first insulating portion as described above.

The third insulating portion includes a plurality of insulating layers.

Preferably, the third insulating portion may include a fourth insulating layer150disposed under the first insulating layer110, a fifth insulating layer165disposed under the fourth insulating layer150, a sixth insulating layer180disposed under the firth insulating layer165and a seventh insulating layer195disposed under the sixth insulating layer180.

In this case, the fourth insulating layer150, the fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195may be formed of different insulating materials. Preferably, the fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195may be formed of the same insulating material. In addition, the fourth insulating layer150may be formed of an insulating material different from the fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195.

The fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195may be formed of the same insulating material as the first insulating layer110and the second insulating layer125.

The fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195may include glass fiber or plastic. In detail, the fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195may include glass or plastic. In detail, the first insulating layer110and the second insulating layer125include chemically strengthened/semi-tempered glass such as soda lime glass or aluminosilicate glass, or strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) and polycarbonate (PC), or sapphire.

In addition, the fourth insulating layer150may be formed of a film-type resin. Preferably, the fourth insulating layer150may be formed of a film-type prepreg. Preferably, the fourth insulating layer150may be formed of an Aginomoto Build-up Film (ABF) or a photo Imagable Dielectric (PID) which is a photosensitive insulating material.

The fourth insulating layer150has a predetermined thickness and is disposed under the first insulating layer110. In this case, there is no circuit pattern protruding from the lower surface of the first insulating layer110. That is, the first circuit pattern105is formed by being buried in a lower part of the first insulating layer110. Accordingly, the fourth insulating layer150may be formed without considering the thickness of the circuit pattern. That is, the general insulating layer is disposed for stable interlayer insulation while covering the circuit pattern, and for this purpose, the final thickness may be determined based on the thickness of the circuit pattern. For example, in the case of the third insulating layer140, the thickness should be determined in consideration of the thickness of the third circuit pattern135disposed on the second insulating layer125. That is, when the thickness of the third circuit pattern135is 12 μm, the thickness of the third insulating layer140may be 20 μm. In addition, when the thickness of the third insulating layer140is 10 μm, the thickness of the third insulating layer140may be 15 μm. On the other hand, the fourth insulating layer150may be formed without considering the thickness of the circuit pattern, and thus may be formed to have a thickness of about 10 μm.

That is, the thickness of the fourth insulating layer150is smaller than the thickness of each of the first insulating layer110, the second insulating layer125, the third insulating layer140, the fifth insulating layer165, the sixth insulating layer180and the seventh insulating layer195.

A fifth circuit pattern160may be disposed on the lower surface of the fourth insulating layer150. In addition, a fourth via155aand a fifth via155bmay be formed in the fourth insulating layer150.

In this case, the fifth circuit pattern160formed on the lower surface of the fourth insulating layer150may have a line width different from that of other circuit patterns. Preferably, the fifth circuit pattern160may have a smaller line width than circuit patterns disposed on other layers. Also, the fifth circuit pattern160may have a smaller pitch than circuit patterns disposed on other layers. This may be achieved by physical properties of the fifth insulating layer165.

Meanwhile, a fourth via155aand a fifth via155bare formed in the fourth insulating layer150. The fourth via155ais a via directly connected to the terminal310of the electronic device300, and the fifth insulating layer165is a via connected to the first circuit pattern105. Preferably, the fourth via155amay overlap with the electronic device300in a vertical direction, and the fifth via155bmay not overlap with the electronic device300in a vertical direction. In addition, the fourth via155aand the fifth via155bmay have different widths. That is, a width of a via formed in the fourth insulating layer150may be formed smaller than that of a via formed in another layer. In this case, when all the vias disposed in the fourth insulating layer150are formed as small vias, a problem may occur in alignment with the vias disposed in other layers. In contrast, when all the vias disposed on the fourth insulating layer150are formed to have the same width as the vias disposed on other layers, reliability in a via connected to the terminal310of the electronic device300may be degraded. Accordingly, in the embodiment, the fourth via155aand the fifth via155bdisposed in the same layer are formed to have different widths according to their respective functions. That is, as the fifth via155bis connected to vias of another layer, the fifth via155bmay have the same width as the vias of the other layer. Vias disposed in the other layers may mean vias disposed in the first insulating layer110, the second insulating layer125, the third insulating layer140, the fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195, respectively. Accordingly, the fifth via155bmay have a minimum width of 40 μm. Preferably, the fifth via155bmay have a width between 40 μm and 100 μm.

Meanwhile, the fourth via155ais directly connected to the terminal310of the electronic device300so that it is formed as a small via. Preferably, the fourth via155ahas a width smaller than that of the fifth via155b. For example, the fourth via155amay have a width of 10 μm to 35 μm. For example, the fourth via155amay have a width of 20 μm to 25 μm.

A sixth circuit pattern170is disposed on a lower surface of the fifth insulating layer165. In addition, a sixth via175may be formed in the fifth insulating layer165.

In addition, a seventh circuit pattern185is disposed on the sixth insulating layer180. In addition, a seventh via190may be formed in the sixth insulating layer180.

*In addition, an eighth circuit pattern200is disposed on the seventh insulating layer195. In addition, an eighth via205may be formed in the seventh insulating layer195.

Meanwhile, a first protective layer215may be disposed on the third insulating layer140. In addition, a second protective layer220may be disposed under the seventh insulating layer195.

The first protective layer215and the second protective layer220may be formed of at least one or more layers using one or more of Solder Resist (SR), oxide, and Au.

According to an embodiment, the printed circuit board includes a first insulating portion in which a cavity in which an electronic device is disposed is formed. In addition, a circuit pattern or a pad is buried and disposed in the first insulating portion. Accordingly, as the circuit pattern or the pad is buried and disposed in the first insulating portion, the thickness of the printed circuit board can be reduced by the thickness of the circuit pattern compared to the prior art, and design freedom can be improved. In addition, since the first insulating portion uses a prepreg including glass fiber, it is possible to minimize the occurrence of panel cracking or warping that occurs when manufacturing a thin substrate.

Further, according to an embodiment, a second insulating portion is disposed under the first insulating portion of the printed circuit board. At this time, the second insulating portion is configured to form an insulating layer using a film-type resin (for example, ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric) which is a photosensitive insulating material) in a region in direct contact with the first insulating portion. Accordingly, in the embodiment, the thickness of the insulating layer of the second insulating portion may be reduced compared to the prior art, and design freedom may be improved.

In addition, according to an embodiment, a small via may be formed by forming the second insulating portion on the area in direct contact with the first insulating portion with a film-type resin, and thus a fine pattern may be implemented.

In addition, the prior art has a vertical symmetry structure as the chip is placed in the center. On the other hand, according to an embodiment, a fan pit panel level package structure may be implemented with an asymmetric structure.

Hereinafter, a process of manufacturing the printed circuit board shown inFIG. 1will be described. The method of manufacturing a printed circuit board according to the embodiment may be included a first process for having a structure such that a first circuit pattern is buried and disposed in the first insulating layer110, a second process of disposing the electronic device300in the first insulating portion, and a third process of laminating the second and third insulating portions having a vertical asymmetric structure with respect to the first insulating portion.

FIGS. 2 to 15are views for illustrating a method of manufacturing the printed circuit board ofFIG. 1in order of processes.

Referring toFIG. 2, first, a carrier board CB for manufacturing a first insulating portion is prepared. The carrier board CB may be a substrate that is a basis for manufacturing a printed circuit board. The carrier board CB may have a structure in which metal layers20are formed on both surfaces of the support substrate10as the center.

The carrier board CB is a general support substrate, and may use CCL (Copper Claded Laminate).

Meanwhile, a surface treatment may be performed on the surface of the metal layer20of the carrier board CB to facilitate separation from the first insulating portion be performed later.

Next, referring toFIG. 3, a first circuit pattern105is formed on the carrier board CB. The first circuit patterns105may be formed on both surfaces of the carrier board CB.

The first circuit pattern105may be formed by plating a metal material on the metal layer20using the metal layer20as a seed layer. Alternatively, the first circuit pattern105may be formed by forming a plating layer (not shown) on the metal layer20and etching the formed plating layer.

The first circuit pattern105may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the first circuit pattern105may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding power. Preferably, the first circuit pattern105may be formed of copper (Cu) having high electrical conductivity and a relatively inexpensive price.

The first circuit pattern105can be formed by an additive process, a subtractive process, MSAP (Modified Semi Additive Process) and SAP (Semi Additive Process) method or the like, which are typical printed circuit board manufacturing processes, and a detailed description thereof will be omitted.

Next, referring toFIG. 4, a first insulating layer110is formed on the metal layer20on which the first circuit pattern105is formed. In this case, a copper foil layer may be present on the first insulating layer110.

The first insulating layer110may be formed of a prepreg including glass fiber.

Preferably, the first insulating layer110include glass or plastic. In detail, the first insulating layer may include chemically strengthened/semi-tempered glass such as soda lime glass or aluminosilicate glass, or strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) and polycarbonate (PC), or sapphire.

In addition, a first via115may be formed in the first insulating layer110.

The first via115may be formed by filling a through hole (not shown) passing through the first insulating layer110with a conductive material. The through hole may be formed by any one of mechanical, laser, and chemical processing. When the through hole is formed by machining, methods such as milling, drilling, and routing may be used, and when formed by laser processing, a UV or CO2 laser method may be used. In addition, when formed by chemical processing, at least one of plurality of insulating layers may be opened by using a chemical containing aminosilane, ketones, or the like.

Meanwhile, the laser processing is a cutting method that concentrates optical energy on a surface to melt and evaporate a part of the material to take a desired shape, accordingly, complex formations by computer programs can be easily processed, and even composite materials that are difficult to cut by other methods can be processed.

In addition, the laser processing has a cutting diameter of at least 0.005 mm, and has a wide range of possible thicknesses.

As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. YAG laser is a laser that can process both copper foil layers and insulating layers, and CO2 laser is a laser that can process only insulating layers.

When the through hole is formed, the first via115may be formed by filling the inside of the through hole with a conductive material. The metal material forming the first via115is selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the conductive material filling may use any one of electroless plating, electroplating, screen printing, sputtering, evaporation, ink jetting, and dispensing, or a combination thereof.

Next, when the first via115is formed, a second circuit pattern120may be formed on the upper surface of the first insulating layer110.

In this case, the process of forming the first insulating layer110, the first via115, and the second circuit pattern120may be simultaneously performed on both sides of the carrier board CB.

Next, referring toFIG. 5, a second insulating layer125is laminated on the first insulating layer110. In addition, a second via120is formed in the second insulating layer125. In addition, a third circuit pattern135is formed on the upper surface of the second insulating layer125. In this case, the second insulating layer125may be formed of a prepreg including the same glass fiber as the first insulating layer110.

In this case, the process of forming the second insulating layer125, the second via120, and the third circuit pattern135may be simultaneously performed on both sides of the carrier board CB.

Next, referring toFIG. 6, a process of separating the first insulating portions respectively formed above and below the carrier board CB may be performed. Accordingly, in an embodiment, a plurality of first insulating portions may be simultaneously manufactured in a single process. In addition, according to an embodiment, the first circuit pattern105may be buried in a lower part of the first insulating layer110. A second circuit pattern120may be disposed on the upper surface of the first insulating layer110. Also, a third circuit pattern135may be disposed on the upper surface of the second insulating layer125. In this case, when the first insulating layer110and the second insulating layer125are viewed as one insulating layer, a lower circuit pattern disposed under the insulating layer is buried and disposed in the insulating layer, and an upper circuit pattern disposed above the insulating layer is disposed to protrude on the insulating layer. That is, in the related art, both the upper and lower circuit patterns are formed to protrude from the upper and lower surfaces of the insulating layer. On the contrary, in the embodiment, the first circuit pattern105may be buried in a lower part of the first insulating layer110. Accordingly, in the embodiment, the thickness of the insulating layer (to be described later)150disposed under the first insulating layer110can be reduced by the thickness of the first circuit pattern105. That is, basically, since the insulating layer is disposed while covering the circuit pattern, the thickness of the circuit pattern is determined as the basic offset thickness. On the other hand, in the embodiment, as the first circuit pattern105is buried and disposed in a lower part of the first insulating layer110, the thickness of the insulating layer to be laminated under the first insulating layer110may be reduced by about 12 to 18 μm compared to the prior art.

When the first insulating portion is manufactured, a cavity C may be formed in the first insulating portion. The cavity C may be formed through the first insulating layer110and the second insulating layer125in common. That is, the cavity C may have the same thickness as the electronic device300, and may have a thickness greater than the thickness of the electronic device300to improve reliability. Preferably, the cavity C may have a thickness greater than that of the electronic device300by about 10 μm. Accordingly, the upper surface of the electronic device300may be positioned lower than the upper surface of the second insulating layer125. In addition, the width of the cavity C may have a greater width than the width of the electronic device300for stable arrangement of the electronic device300. The cavity C may be formed by any one of mechanical, laser, and chemical processing. When the through hole is formed by machining, methods such as milling, drilling, and routing may be used, and when formed by laser processing, a UV or CO2 laser method may be used. In addition, when formed by chemical processing, the first insulating layer110and the second insulating layer125may be opened using a chemical containing aminosilane, ketones, or the like.

Next, referring toFIG. 7, a film layer A is formed under the lower surface of the first insulating layer110. The film layer (A) is attached to the lower surface of the first insulating layer110, and accordingly may be disposed to cover a lower part of the cavity (C). The film layer (A) may be disposed covering one surface of the cavity (C) in order to arrange and fix the electronic device300in the cavity (C). The film layer (A) may be a polyimide film, but is not limited thereto.

Next, referring toFIG. 8, the electronic device300is attached on the film layer A exposed through one surface of the cavity C. The electronic device300may be an electronic component such as a chip, and may be divided into an active device and a passive device. In addition, the active device is a device that actively uses a non-linear part, and the passive device refers to a device that does not use non-linear characteristics even though both linear and non-linear characteristics exist. In addition, the passive device may include a transistor, an IC semiconductor chip, and the like, and the passive device may include a capacitor, a resistor, and an inductor. The passive element is mounted on a conventional printed circuit board to increase a signal processing speed of a semiconductor chip, which is an active element, or to perform a filtering function.

The electronic device300may vary depending on the application to which the printed circuit board is applied. For example, when applied to a NAND flash memory product applied to a smartphone, the electronic device300may be a control device component.

A terminal310may be formed on a lower surface of the electronic device300. In this case, a lower surface of the terminal310may be disposed on the same plane as the lower surface of the first insulating layer110. The lower surface of the terminal310may be disposed on the same plane as the lower surface of the first circuit pattern105. Meanwhile, the upper surface of the electronic device300may be disposed on the same plane as the upper surface of the second insulating layer125. Preferably, the upper surface of the electronic device300may be disposed lower than the upper surface of the second insulating layer125. That is, the cavity C may have the same thickness as the electronic device300, and may have a thickness greater than the thickness of the electronic device300to improve reliability. Preferably, the cavity C may have a thickness greater than that of the electronic device300by about 10 μm. Accordingly, the upper surface of the electronic device300may be positioned lower than the upper surface of the second insulating layer125. In addition, the width of the cavity C may have a greater width than the width of the electronic device300for stable arrangement of the electronic device300.

Next, referring toFIG. 9, a second insulating portion is formed on the first insulating portion. That is, when the arrangement process of the electronic device300is completed, the third insulating layer140is formed on the second insulating layer125. The third insulating layer140may be formed of Resin Coated Cu (RCC). In this case, the third insulating layer140is disposed on the second insulating layer125and is also disposed in the cavity C formed in the second insulating layer125and the first insulating layer110. That is, the third insulating layer140may be disposed on the second insulating layer125to have a predetermined thickness while filling the cavity C.

That is, as described above, the third insulating layer140must be disposed on the second insulating layer125with a uniform thickness while stably filling the cavity C. In this case, a curvature may be formed on the upper surface of the third insulating layer140according to the area of the cavity C. This is because the thickness of the third insulating layer140in the region where the cavity C exists and the region other than the region are different from each other. Accordingly, in an embodiment, by forming the third insulating layer140in the RCC type as described above, while solving the above problems, it is possible to manufacture a reliable substrate.

In addition, a coating layer145coated with copper may be formed on the third insulating layer140. The coating layer145may be a metal layer for later forming the fourth circuit pattern210.

In addition, when the formation of the third insulating layer140is completed, the film layer A attached under the second insulating layer125is removed.

Next, referring toFIG. 10, a fourth insulating layer150is formed under the first insulating layer110. In this case, the fourth insulating layer150may be formed of an insulating material different from the first insulating layer110, the second insulating layer125, and the third insulating layer140. Preferably, the fourth insulating layer150may be formed of a film-type resin. Preferably, the fourth insulating layer150may be formed of a film-type prepreg. Preferably, the fourth insulating layer150may be formed of an Aginomoto Build-up Film (ABF) or a photo Imagable Dielectric (PID) which is a photosensitive insulating material.

The fourth insulating layer150has a predetermined thickness and is disposed under the first insulating layer110. In this case, there is no circuit pattern protruding from the lower surface of the first insulating layer110. That is, the first circuit pattern105is formed by being buried in a lower part of the first insulating layer110. Accordingly, the fourth insulating layer150may be formed without considering the thickness of the circuit pattern. That is, the general insulating layer is disposed for stable interlayer insulation while covering the circuit pattern, and for this purpose, the final thickness may be determined based on the thickness of the circuit pattern. For example, in the case of the third insulating layer140, the thickness should be determined in consideration of the thickness of the third circuit pattern135disposed on the second insulating layer125. That is, when the thickness of the third circuit pattern135is 12 μm, the thickness of the third insulating layer140may be 20 μm. In addition, when the thickness of the third insulating layer140is 10 μm, the thickness of the third insulating layer140may be 15 μm. On the other hand, the fourth insulating layer150may be formed without considering the thickness of the circuit pattern, and thus may be formed to have a thickness of about 10 μm.

That is, the thickness of the fourth insulating layer150may be smaller than the thickness of each of the first insulating layer110, the second insulating layer125, and the third insulating layer140.

Next, a fifth circuit pattern160may be formed on the lower surface of the fourth insulating layer150. In addition, a fourth via155aand a fifth via155bmay be formed in the fourth insulating layer150, respectively.

In this case, the fifth circuit pattern160formed on the lower surface of the fourth insulating layer150may have a line width different from that of other circuit patterns. Preferably, the fifth circuit pattern160may have a smaller line width than circuit patterns disposed on other layers. Also, the fifth circuit pattern160may have a smaller pitch than circuit patterns disposed on other layers. This may be achieved by physical properties of the fifth insulating layer165.

Meanwhile, a fourth via155aand a fifth via155bare formed in the fourth insulating layer150. The fourth via155ais a via directly connected to the terminal310of the electronic device300, and the fifth insulating layer165is a via connected to the first circuit pattern105. Preferably, the fourth via155amay overlap with the electronic device300in a vertical direction, and the fifth via155bmay not overlap with the electronic device300in a vertical direction. In addition, the fourth via155aand the fifth via155bmay have different widths. That is, a width of a via formed in the fourth insulating layer150may be formed smaller than that of a via formed in another layer. In this case, when all the vias disposed in the fourth insulating layer150are formed as small vias, a problem may occur in alignment with the vias disposed in other layers. In contrast, when all the vias disposed on the fourth insulating layer150are formed to have the same width as the vias disposed on other layers, reliability in a via connected to the terminal310of the electronic device300may be degraded. Accordingly, in the embodiment, the fourth via155aand the fifth via155bdisposed in the same layer are formed to have different widths according to their respective functions. That is, as the fifth via155bis connected to vias of another layer, the fifth via155bmay have the same width as the vias of the other layer. Vias disposed in the other layers may mean vias disposed in the first insulating layer110, the second insulating layer125, the third insulating layer140, the fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195, respectively. Accordingly, the fifth via155bmay have a minimum width of 40 μm. Preferably, the fifth via155bmay have a width between 40 μm and 100 μm.

Meanwhile, the fourth via155ais directly connected to the terminal310of the electronic device300so that it is formed as a small via. Preferably, the fourth via155ahas a width smaller than that of the fifth via155b. For example, the fourth via155amay have a width of 10 μm to 35 μm. For example, the fourth via155amay have a width of 20 μm to 25 μm.

Thereafter, a build-up process may be performed in which an additional insulating layer is laminated on the third insulating layer140and under the fourth insulating layer150, respectively. In this case, in the embodiment, the second insulating portion and the third insulating portion are arranged with an asymmetric structure with respect to the first insulating portion. Accordingly, the number of layers of the second insulating portion and the number of layers of the third insulating portion may be different. This can be achieved by the process described later.

Referring toFIG. 11, a fifth insulating layer165is laminated on the third insulating layer140and under the fourth insulating layer150, respectively. In this case, a metal layer166may be formed on a surface of the fifth insulating layer165.

Next, referring toFIG. 12, a process of forming the sixth via175in the fifth insulating layer165may be performed. In addition, a process of forming the sixth circuit pattern170on the surface of the fifth insulating layer165may be performed using the metal layer166.

Thereafter, when the formation of the sixth via175and the sixth circuit pattern170is completed, a process of laminating the sixth insulating layer180on the fifth insulating layer165may be performed. In this case, the metal layer181may also be disposed on the surface of the sixth insulating layer180.

Next, referring toFIG. 13, a process of forming the seventh via190in the sixth insulating layer180may be performed. In addition, a process of forming the seventh circuit pattern185by removing the metal layer181may be performed.

Thereafter, when the formation of the seventh via190and the seventh circuit pattern185is completed, a process of laminating the seventh insulating layer195on the sixth insulating layer180may be performed. In this case, the metal layer196may also be disposed on the surface of the seventh insulating layer195.

In this case, the laminating process of the fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195was performed at an upper part of the third insulating layer140and a lower part of the fourth insulating layer150, respectively. In addition, the fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195formed on the third insulating layer140are dummy insulating portions to be removed. The fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195formed on the third insulating layer140are dummy insulating portions for forming an asymmetric structure according to the embodiment.

And, referring toFIG. 14, while maintaining the fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195formed under the fourth insulating layer150, a process of removing the fifth insulating layer165, the sixth insulating layer180, and the seventh insulating layer195formed on the third insulating layer140may be performed.

Thereafter, a process of forming the eighth via205and the eighth circuit pattern200in the seventh insulating layer195may be performed.

In addition, a process of forming the via and the fourth circuit pattern210in the third insulating layer140may be performed.

That is, in the embodiment, the number of layers of the second insulating portion on the first insulating portion and the number of layers of the third insulating portion under the first insulating portion are different from each other by using the dummy insulating portion as described above, and this makes it possible to have a mutually asymmetric structure.

Next, referring toFIG. 15, a process of disposing the first protective layer215on the third insulating layer140, and a process of disposing the second protective layer220under the seventh insulating layer195may be performed.

The first protective layer215and the second protective layer220may be formed of at least one or more layers using one or more of Solder Resist (SR), oxide, and Au.

According to an embodiment, the printed circuit board includes a first insulating portion in which a cavity in which an electronic device is disposed is formed. In addition, a circuit pattern or a pad is buried and disposed in the first insulating portion. Accordingly, as the circuit pattern or the pad is buried and disposed in the first insulating portion, the thickness of the printed circuit board can be reduced by the thickness of the circuit pattern compared to the prior art, and design freedom can be improved. In addition, since the first insulating portion uses a prepreg including glass fiber, it is possible to minimize the occurrence of panel cracking or warping that occurs when manufacturing a thin substrate.

Further, according to an embodiment, a second insulating portion is disposed under the first insulating portion of the printed circuit board. At this time, the second insulating portion is configured to form an insulating layer using a film-type resin (for example, ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric) which is a photosensitive insulating material) in a region in direct contact with the first insulating portion. Accordingly, in the embodiment, the thickness of the insulating layer of the second insulating portion may be reduced compared to the prior art, and design freedom may be improved.

In addition, according to an embodiment, a small via may be formed by forming the second insulating portion on the area in direct contact with the first insulating portion with a film-type resin, and thus a fine pattern may be implemented.

In addition, the prior art has a vertical symmetry structure as the chip is placed in the center. On the other hand, according to an embodiment, a fan pit panel level package structure may be implemented with an asymmetric structure.

FIG. 16is a view illustrating a structure of a printed circuit board according to another embodiment.

Referring toFIG. 16, the printed circuit board100A differs only in the number of layers of the second insulating portion and the number of layers of the third insulating portion compared to the printed circuit board100ofFIG. 1, and other configurations may be the same.

The printed circuit board100A may include a first insulating portion, a second insulating portion on the first insulating portion, and a third insulating portion under the first insulating portion. In this case, the basic structures of the first insulating portion, the second insulating portion, and the third insulating portion have been described inFIG. 1, and thus detailed descriptions thereof will be omitted.

In this case, the second insulating portion may have a two-layer structure different from the second insulating portion ofFIG. 1. That is, the second insulating portion may further include a third insulating layer140and a third-first insulating layer225disposed on the third insulating layer140. In addition, a via235may be disposed in the third-first insulating layer225. In addition, a fourth-first circuit pattern230may be additionally disposed on the third-first insulating layer225.

In addition, the third insulating portion may have a three-layer structure different from the third insulating portion inFIG. 1.

That is, the third insulating portion may have a structure including the fourth insulating layer150, the fifth insulating layer165, and the sixth insulating layer180.

That is, according toFIG. 16, with the first insulating portion as the center, the second insulating portion disposed above may have a two-layer structure, and the third insulating portion disposed below may have a three-layer structure.

FIG. 17is a view illustrating a package substrate according to an exemplary embodiment.

Referring toFIG. 17, the package substrate may include the printed circuit board100described inFIG. 1. In this case, the first electronic device300may be disposed in the printed circuit board100.

In addition, the second electronic device400may be attached on the circuit pattern210disposed on an uppermost portion of the printed circuit board100.

In addition, a third electronic device410electrically connected to the circuit pattern210and a connection wire (e.g., a metal wire) may be further formed on the uppermost portion of the printed circuit board100.

To this end, the first protective layer215may include at least one opening (not shown) exposing an upper surface of the circuit pattern210disposed on the uppermost portion. In addition, the second electronic device400may be attached on the circuit pattern210exposed through the opening by a flip chip bonding method.

In addition, an adhesive layer420may be disposed on the first protective layer215.

The adhesive layer420may be formed of a conductive adhesive, and differently, may be a non-conductive adhesive. The conductive adhesive is largely divided into an anisotropic conductive adhesive and an isotropic conductive adhesive, and it is basically composed of conductive particles such as Ni, Au/polymer, or Ag, and a blend type insulating resin in which the properties of thermosetting, thermoplastic, or both are mixed.

In addition, the non-conductive adhesive may be a polymer adhesive, and preferably, a non-conductive polymer adhesive including a thermosetting resin, a thermoplastic resin, a filler, a curing agent, and a curing accelerator.

In addition, a third electronic device410may be attached on the adhesive layer420. In this case, a terminal (not shown) may be disposed on the third electronic device410. In this case, the third electronic device410may be attached on the adhesive layer420while the terminal of the third electronic device410is disposed to face upward. In addition, the terminal of the third electronic device410and the circuit pattern210may be electrically connected through an additional connection wire such as a metal wire.

At this time, each of the first electronic device300, the second electronic device400, and the third electronic device410may include at least one of a control IC chip, a memory chip, a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip and a chip capacitor.

For example, when the package substrate is a NAND flash memory product applied to a smartphone, the first electronic device300may be a control IC chip, the second electronic device400is a NAND flash memory, and the third electronic device410may be at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor.

FIG. 18is a view illustrating a package substrate according to another embodiment.

Referring toFIG. 18, the package substrate may include the printed circuit board100described inFIG. 1. In this case, the first electronic device300may be disposed in the printed circuit board100.

In addition, the second electronic device400may be attached on the circuit pattern210disposed on the uppermost portion of the printed circuit board100.

In addition, a circuit pattern210and a third electronic device410may be further attached to the uppermost portion of the printed circuit board100.

To this end, the first protective layer215may include a plurality of openings (not shown) exposing an upper surface of the circuit pattern210disposed on the uppermost portion. In addition, the second electronic device400may be attached on the circuit pattern210exposed through the opening by a flip chip bonding method.

In addition, a third electronic device410may be attached on the exposed circuit pattern210by a flip chip bonding method.

To this end, a solder ball420may be formed between the third electronic device410and the circuit pattern210. The solder ball420may contain materials of different components in solder. The solder may be composed of at least one of SnCu, SnPb, and SnAgCu. In addition, the material of the different component may include any one of Al, Sb, Bi, Cu, Ni, In, Pb, Ag, Sn, Zn, Ga, Cd, and Fe.

In addition, although not shown inFIGS. 17 and 18, a conductive adhesive portion (not shown) such as the solder ball is also disposed between the second electronic device400and the circuit pattern210, and accordingly, the second electronic device400may be attached to the circuit pattern210.

According to an embodiment, the printed circuit board includes a first insulating portion in which a cavity in which an electronic device is disposed is formed. In addition, a circuit pattern or a pad is buried and disposed in the first insulating portion. Accordingly, as the circuit pattern or the pad is buried and disposed in the first insulating portion, the thickness of the printed circuit board can be reduced by the thickness of the circuit pattern compared to the prior art, and design freedom can be improved. In addition, since the first insulating portion uses a prepreg including glass fiber, it is possible to minimize the occurrence of panel cracking or warping that occurs when manufacturing a thin substrate.

Further, according to an embodiment, a second insulating portion is disposed under the first insulating portion of the printed circuit board. At this time, the second insulating portion is configured to form an insulating layer using a film-type resin (for example, ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric) which is a photosensitive insulating material) in a region in direct contact with the first insulating portion. Accordingly, in the embodiment, the thickness of the insulating layer of the second insulating portion may be reduced compared to the prior art, and design freedom may be improved.

In addition, according to an embodiment, a small via may be formed by forming the second insulating portion on the area in direct contact with the first insulating portion with a film-type resin, and thus a fine pattern may be implemented.

In addition, the prior art has a vertical symmetry structure as the chip is placed in the center. On the other hand, according to an embodiment, a fan pit panel level package structure may be implemented with an asymmetric structure.

Features, structures, effects, and the like described in the embodiments above are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in each embodiment may be combined or modified for other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, the contents related to these combinations and modifications should be construed as being included in the scope of the embodiment.

In the above, the embodiments have been described mainly, but these are only examples and are not intended to limit the embodiments, and those of ordinary skill in the field to which the embodiment belongs will appreciate that various modifications and applications not illustrated above are possible without departing from the essential characteristics of the embodiment. For example, each component specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the embodiments set in the appended claims.