Method using low temperature wafer bonding to fabricate transistors with heterojunctions of Si(Ge) to III-N materials

A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to wafer bonding for electronic devices, for example, microwave and power electronics.

2. Description of the Related Art

(Note: This application references a number of different publications as indicated throughout the specification by one or more reference numbers within brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled “References.” Each of these publications is incorporated by reference herein.)

Recent advances in GaN device technology have shown significant promise for high performance transistors. Currently, GaN based transistors have the highest output power density for high frequency electronics with over 30 W/mm at 8 GHz [1], and 8.6 W/mm at 40 GHz [2]. Furthermore, discrete AlGaN/GaN high electron mobility transistors (HEMTs), with a rated output power as high as 180 W at 2.2 GHz, have recently been offered commercially by Eudyna (Fujitsu) for applications such as cell phone base stations, suggesting that these devices are both manufacturable and commercially viable.

While the unique properties of the III-Nitride (III-N) material system make the AlGaN/GaN HEMT an ideal candidate for microwave and high power electronics, the flexibility in design and function along with the integration available in more mature technologies, such as Si and the III-Arsenide (III-As) systems, offer exciting new possibilities when combined with the capabilities of GaN.

Although epitaxial growth techniques such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE) have traditionally been utilized to fabricate the material layer structures used in semiconductor devices, these epitaxial techniques are limited to materials of similar lattice constant, crystalline structure, and coefficient of thermal expansion. Wafer bonding, which joins two materials placed in intimate contact under elevated temperature and pressure, has proven to be effective in forming a number of heterogeneous devices from lattice-mismatched materials. These devices include GaAs/InP vertical-cavity and micro disk lasers, InGaAs/Si avalanche photodiodes, InGaAsP/AlGaAs photonic crystal lasers, and AlGaAs/GaAs/GaN heterojunction bipolar transistors (HBTs) [4].

The present invention uses wafer bonding to combine the capabilities of high speed injectors such as Si, SiGe, and the III-As or III-P system, with the high power collector capabilities of the III-N system.

SUMMARY OF THE INVENTION

The present invention proposes that wafer bonding can be used to fabricate transistors between Si, SiGe and compound semiconductors containing nitrogen such as gallium nitride. Using low temperature bonding techniques, materials with dissimilar thermal expansion coefficients such as Si, Ge, and GaN can be bonded to form heterojunctions that cannot be readily grown with high quality using conventional epitaxial techniques. This invention describes a method using low temperature bonding to fabricate opto-electronic and electronic devices which combine the benefits of Si or SiGe with the III-N material system. In particular, these devices include high voltage transistors combining enhancement mode Si CMOS based injectors with III-N based electron collector or drain structures. This can also include Si/SiGe heterojunction bipolar injectors with a III-N based collector, as well as optoelectronic devices such as solar cells, light emitting diodes (LEDs), and photo-detectors. Si or Si/Ge injector structures may be bonded to either the Ga-face, the N-Face or some other crystal orientation of the III-N collector or drain structures, and may include intermediate layers such as GaP, InP or other materials to enhance the bond strength or to reduce barriers to electronic conduction.

The present invention discloses a method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a second semiconductor material, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the second semiconductor material, wherein the second semiconductor material is a III-nitride and the first semiconductor material has a different material composition from the second semiconductor material.

The method may further comprise forming one or more injector regions in the first semiconductor material prior to, or subsequent to, the wafer bonding step, wherein the first semiconductor material is not a III-nitride. The first semiconductor material may have superior properties for the injector region as compared to the second semiconductor material. The superior properties may be a higher speed of the injector region, higher electron mobility, lower access resistance, or a combination thereof. The first semiconductor material may have a different lattice constant, thermal properties, and crystalline structure as compared to the second semiconductor material, such that the device quality heterojunction cannot be epitaxially grown. The first semiconductor material may be Si, SiGe, Si and SiGe, GaP, InP, GaInP or a III-P compound, III-As, or a III-As compound.

The method may further comprise introducing In, InP, or a III-P or III-As compound on a bonding face of the first semiconductor material or second semiconductor material, prior to the wafer bonding step.

A device may be fabricated using the method, for example, a heterojunction bipolar transistor or field effect transistor.

The present invention further discloses an electronic device, comprising a semiconductor material including one or more injector regions; a III-nitride material including one or more collector, drain or active regions; and a device quality heterojunction formed between the semiconductor material and the III-nitride, wherein the semiconductor material is not a III-nitride, the injector regions have one or more superior properties as compared to III-nitride injector regions, and the superior properties include higher speed of the injector region, higher electron mobility, lower access resistance, or a combination thereof.

The device may further comprise a wafer bond formed between the semiconductor material and the III-nitride to form the device quality heterojunction for reducing thermal mismatch strain, dislocation distribution and impurity distribution in the device.

The device may further comprise an intermediate region between the semiconductor material and the III-nitride, for enhancing bond strength and conductivity of the device quality heterojunction, wherein the intermediate region is selected from a group comprising In, InP, a III-P or III-As compound, and is on a bonding face of the semiconductor material or III-nitride material.

The injector regions may have reduced dopant diffusion and current leakage as compared to a heterojunction formed at a temperature above 550° C. The injector and collector or drain regions may be unipolar. The semiconductor material may be selected from a group comprising Si, SiGe, or Si and SiGe, III-As or a III-As compound.

The device may be a heterojunction bipolar transistor (HBT) or a field effect transistor (FET), for example.

The HBT may further comprise an emitter region; a base region between the emitter region and the collector regions; the collector regions including a first collector layer and a second collector layer, wherein the second collector layer, on the first collector layer, is doped with a same charge carrier type as the first collector layer but with a smaller charge concentration; the semiconductor material selected from a group comprising Si, SiGe, Si and SiGe, GaP, InP, GaInP or a III-P compound, III-As, or a III-As compound, wherein the semiconductor material includes the injector region and the injector region includes the emitter region and the base region; the III-nitride including the collector regions, wherein the III-nitride is gallium nitride (GaN); and a wafer bond formed between the base region of the semiconductor material and the second collector layer of the GaN, thereby forming the device quality heterojunction between the base region and the second collector layer.

The FET may further comprise a source region; a semiconducting region between the source region and the drain region; a first drift region between the semiconducting region and the drain region; and a second drift region between the first drift region and the drain region, wherein: the semiconductor material is silicon and includes the injector region and the first drift region, and the injector region includes the source region and the semiconducting region; the III-nitride is gallium nitride (GaN) and includes the second drift region and the drain region; the first drift region is doped with a same charge carrier type as the drain region, but with a smaller charge concentration than the drain region; and a wafer bond formed between the first drift region of the semiconducting material and the second drift region of the GaN, thereby forming the device quality heterojunction between the first drift region and the second drift region.

The present invention further discloses an electronic device fabricated using a process comprising wafer bonding a first semiconductor material to a second semiconductor material at a temperature below 550° C. to form a device quality heterojunction between the first semiconductor material and the second semiconductor material; wherein the first semiconductor material includes one or more injector regions, and the second semiconductor material includes one or more active regions; and wherein the second semiconductor material comprises a III-nitride semiconductor, the first semiconductor material is different from the second semiconductor material, and the first semiconductor material is selected for superior properties in the injector region as compared to the second semiconductor material. The active region may be a collector, drain, channel, light emitting region, or light sensitive region.

DETAILED DESCRIPTION OF THE INVENTION

Overview

The present invention proposes merging the injector properties of Si and/or Si/SiGe with the collector properties of the III-N material system (using the Ga-face, N-face or other orientations) of III-N structures such as GaN or AlGaN/GaN using wafer bonded heterojunctions.

Technical Description

For electronic devices to take advantage of wafer bonded heterojunctions, the conduction and valence band energy lineup must be favorable. Van De Walle and Neugebauer have predicted the band lineups of several semiconductor systems [3].FIG. 1, which is based on the predicted line-ups [3], is a graph plotting the conduction band minimum and valence band maximum of various semiconductors and insulators, showing the favorable conduction band lineup of Si, and SiGe with GaN, wherein the circled area100indicates the predicted line-up of SiGe to GaN, the dashed line102is a guide line to show the conduction band line-up of GaAs with GaN, and the dashed line104is a guide line to show the conduction band line-up of Ge with GaN.

Incorporation of indium (In) or other materials into the bonding face of III-N collector structures may also be used to fine-tune this lineup to create extremely low conduction band barriers across bonded interfaces.

Table 1 shows a few key material properties relevant to high power switching and communications devices in Si and GaN. With superior electron saturation velocities and breakdown fields, GaN is an ideal candidate for both power switching and communications electronics. The increase in bandgap leads to higher breakdown fields, allowing the use of thinner collector/drain layers, while the increased saturated electron velocities (combined with the thinner drift region) leads to transit times which are reduced by more than an order of magnitude. Combining this performance with the injector performance and integration available to Si, SiGe, the present invention is for providing high performance devices with applications ranging from microwave and mm-wave communications to high voltage switching. To address this wide range of possible applications, the present invention discloses and investigates the following device designs.

FIG. 2is a schematic of a wafer bonded Si/SiGe/GaN Dual Heterojunction Bipolar Transistor (DHBT)200, comprising a semiconductor material including an injector region (described below), a III-nitride material202including one or more collector regions, in this case two collector regions204a,204b, forming part of a collector structure204c, a device quality heterojunction206between the semiconductor material and the III-nitride202, and a wafer-bond208between the semiconductor material and the III-nitride202to form the device quality heterojunction206.

The DHBT200further comprises an emitter region210, and a base region212between the emitter region210and the collector structure204c. The collector structure204ccomprises a first GaN collector layer204abetween a second GaN collector layer204band a SiC collector layer214. The second collector layer204bmay be the active part of the collector structure204c. The first collector layer204aand the SiC collector layer214may be subcollectors. The second collector204bis doped with a same charge carrier type (n−type or GaN N−) as the first collector204a(n+-type or GaN N+), but with a smaller charge concentration than the charge concentration in the first collector204a.

The semiconductor material comprises Si and SiGe, and includes the emitter region210(comprised of Si) and the base region212(comprised of SiGe). The injector region comprises the emitter region210and the base region212.

The III-nitride202is GaN and includes the second collector layer204bon the first collector layer204a.

The wafer-bond208between the base region212of the semiconductor material and the second collector layer204bof the GaN202forms the heterojunction206between the base region212and the collector region/structure204c.

The base layer212has contacts216, and the emitter layer210has contact218. The SiC214is optional.

SiGe Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) ICs are overtaking GaAs based devices in a number of high frequency applications. The combination of GaN with SiGe can increase the frequency of operation at high power densities and provide high performance integrated communications functionality on a single die. Because of the higher breakdown voltage associated with the GaN collector, Si/SiGe/GaN DHBTs (as illustrated inFIG. 2, for example) can offer a higher combination of operating frequency and voltage than conventional bipolar transistors. The present invention uses Si/SiGe/III-N DHBTs to extend the output power capability of conventional Si/SiGe HBTs, and Si/III-N HBTs to extend Si bipolar structures for high voltage switching applications. The GaN collector structure202can lead to increased voltage swing with the same emitter/base structure as conventional SiGe HBTs and Si bipolar junction transistors (BJTs), leading to high frequency devices combining the advantages of Si/SiGe HBT technology with GaN high power capability.

Compared to field effect devices, bipolar transistors are normally off, and typically have lower on-state power dissipation. Device fabrication may include front-side conventional SiGe or Si process steps including ion implantation, metallization, etc., followed by wafer transfer to a GaN vertical collector structure202or an AlGaN/GaN lateral collector (or drain) structure and low temperature direct wafer bonding.

Si Vertical Double Diffused Metal Oxide Semiconductor (VDMOS)

FIG. 3is a schematic of an Si/GaN VDMOS device300, comprising a semiconductor material302including two injector regions (described below), a III-nitride material304including one or more drain regions, in this case two drain regions306a,306b, a device quality heterojunction308between the semiconductor material302and the III-nitride304, and a wafer bond308abetween the semiconductor302and the III-nitride304to form the device quality heterojunction308.

The semiconductor material302is not a III-nitride and the injector regions have one or more superior properties as compared to III-nitride injector regions and the superior properties are higher speed of the injector region, higher electron mobility, lower access resistance, or a combination of these superior properties.

A first Field Effect Transistor (FET) of the device300comprises a first source region310(n+-type Si or N+Si), drain regions306a,306b, a first semiconducting region312(p-type Si or P Si) between the first source region310and the first drain region306a, a first drift region314(n-type Si or N Si) between the first semiconducting region312and the first drain region306a, and a second drain region306bbetween the first drift region314and the first drain region306a, wherein the semiconductor material302is Si and includes the first injector region and the first drift region314, and the first injector region comprises the first source region310and the first semiconducting region312.

The III-nitride304is gallium nitride (GaN) and includes the drain regions306a,306b, and the drain region306bis a second drift region on the first drain region306a. In this case, layer306ais the drain, and layers306band314are drift regions.

The first drift region314is doped with a same charge carrier type (n-type) as the drain region306a(n+-type or N+GaN), but with a smaller charge concentration than the charge concentration of the drain region306a(the first drift region314is doped n-type, and the GaN drain region306ais doped n+-type). The second drift layer (GaN)306bmay also be doped n-type, smaller than the n+-type doping of the drain layer306a. Alternatively, the first drift region314and the second drift region306bmay be additional drain layers.

The wafer-bond308abetween the first drift region314of the semiconducting material302and the second drift region306bof the GaN304forms the heterojunction308between the first drift region314and the second drift region306b.

The first FET further comprises a gate318, separated from the first injector region by an insulator320.

The device300comprises a second FET, comprising a second n+-type Si source region322, drain regions306a,306b, a second semiconducting region (p-type Si)324between the second source region322and the first drain region306a, the first drift region314(n-type Si) between the second semiconducting region324and the first drain region306a, and the second drain region306bbetween the first drift region314and the first drain region306a, wherein the semiconductor material302is Si and includes the second injector region and the first drift region314. The second injector region comprises the second source region322and the second semiconducting region324.

The second FET further comprises a gate326, separated from the second injector region by an insulator320.

The first GaN drain306ais between a substrate328and the second GaN drain306b. The substrate328also a drain region, but is optional. The first source310has contact330, the second source322has contact332, and the drain306ahas contact334. The FETs may be MOSFETs, for example, or any other device structure using the layers ofFIG. 3.

The combination of Si VDMOS and GaN (as illustrated inFIG. 3, for example) can increase the performance of high voltage switching devices. The Si VDMOS injector has the advantages of normally-off operation, low on-resistance, and the sophisticated manufacturing and integration capabilities associated with Si CMOS. The high critical fields (2 MV/cm) and saturated electron velocities (2.4×107cm/s) of a GaN collector can reduce the drain drift region thickness by approximately 10 times, and electron transit times by as much as 20 times. The device of this embodiment may be processed using conventional Si processing techniques, and then transferred to a GaN film grown on Si or SiC to form a wide-bandgap drain. Improvements in transistor switching speed lead to reductions in the sizes of passive components, and integration with conventional CMOS or BiCMOS may lead to gains in size and cost efficiency.

AlGaAs/GaAs/GaN DHBT with a Lateral Collector

FIG. 4is a schematic of an AlGaAs/GaAs/GaN DHBT400comprising a lateral collector contact402. The DHBT further comprises a semiconductor material including an injector region (described below), a III nitride404including a collector region406, a heterojunction408between the semiconductor and the III-nitride404, and a wafer bond410for wafer-bonding the injector region404to the collector region406and forming the heterojunction408.

The injector region comprises an AlGaAs emitter layer412and a GaAs base layer414. The collector region406comprises an n-type GaN layer416. The n-type GaN layer (N GaN collector)416is on a Si buffer418which is on a substrate420.

The wafer bond410wafer bonds the n-type GaN416to the GaAs base414, so that the heterojunction is between the collector416and the base414. A collector contact402is made to the n-type GaN416, an emitter contact422is made to the AlGaAs emitter412, and a base contact424is made to the GaAs base414.

Device Fabrication

The present invention also develops wafer bonding technology for low temperature bonding of GaN to Si and GaAs. Si/Si and Si/InP direct wafer bonding reports have shown that strong electrically conductive bonds can be formed between Si wafers or Si and InP wafers with anneal temperatures as low as 250° C. [6]. The present invention applies this process to GaN wafer bonding, allowing the maximum fabrication flexibility, along with the advantages of reduced thermal mismatch strain and dislocation or impurity distribution associated with high temperature processes. A plasma activation system may be used for low temperature wafer bonding. The bonding of Si and GaAs to GaN is characterized to determine optimum plasma activation conditions as evaluated by physical bond strength. Devices include P-N and N-N heterojunctions to characterize the interface and band-lineup of various material combinations. The present invention may use capacitance-voltage and temperature dependent current-voltage measurements to characterize conduction band discontinuities between bonded semiconductors. Transmission Electron Microscopy (TEM) may be used to characterize extended defects initiated at the bonded interfaces, and secondary ion mass spectroscopy may be used to determine contamination levels at interfaces, and their penetration into bulk bonded layers. These techniques may be used to evaluate various bonding techniques and material combinations, including various crystallographic orientations of bonded materials, bonding temperature, bonding ambient, and bonding surface preparation.

Building on the bonding methods developed above, for example, the present invention proposes transistors based on Si(Ge)/GaN and GaAs/GaN heterojunctions. Evaluations of heterojunctions investigated in the preceding paragraph may guide efforts to fabricate devices most likely to succeed in transistor form. Transistor contact structures compatible with high frequency measurements may be fabricated and characterized to determine transit delay across bonded junctions. Temperature dependent DC and RF measurements may be used to characterize bonded devices. Extensive electronic measurement capabilities, including large signal RF power to 40 GHz, and cryo-RF small signal measurements, may be used to characterize communications devices. Feedback from these measurements may be used to further improve wafer bonding methods to develop processes which maximize small signal and RF performance of transistors.

Improved bonding processes developed above may be implemented in new devices with structures optimized for bonded heterojunctions. In addition, more sophisticated device fabrication tools developed for GaN HEMTs may be incorporated, such as ion implantation of GaN and two dimensional electron gas (2DEG) Al(In)GaN/GaN collector structures. Various GaN substrate options such as freestanding GaN vs. GaN on Si, or GaN on SiC, may be evaluated and used. RF power measurements may be used to evaluate device design as well as process improvements, and structure design may be refined to maximize power performance.

Process Steps

FIG. 5is a flowchart illustrating a method for fabricating an electronic device, comprising one or more of the following steps:

Block500represents the step of selecting a first semiconductor material for its injector properties. The first semiconductor material may be selected because the first semiconductor material has superior properties for the injector region as compared to the second semiconductor material. The superior injector properties may be a higher speed of the injector region, higher electron mobility, lower access resistance, or a combination of these superior properties. The first semiconductor material may have a different lattice constant, thermal properties, and crystalline structure as compared to the second semiconductor material, such that the device quality heterojunction cannot be epitaxially grown. The first semiconductor material may be Si, SiGe, Si and SiGe, GaP, InP, GaInP or a III-P compound, III-As, or a III-As compound, for example. The first semiconductor material may be a non-III-nitride material.

Block502represents the step of characterizing a bond interface between the first semiconductor material and a III-nitride semiconductor material. For example, the characterizing may comprise measuring bond strength, conduction discontinuities, extended defects, contamination levels, and contamination penetration at the interface between the semiconductor material and the III-nitride. The step may further comprise characterizing the electrical, frequency, and/or optical response across the bonded interface.

Block504represents the step of evaluating various bonding techniques and material combinations based on the characterization of block502, and choosing the best technique for a specific device application.

Block506represents the step of introducing In, InP, or a III-P or III-As compound on a bonding face of the first or second semiconductor material, prior to the wafer bonding step.

Block508represents the step of wafer bonding a first semiconductor material to a second semiconductor material, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the second semiconductor material, wherein the second semiconductor material is a III-nitride and the first semiconductor material is different from the second semiconductor material.

Block510represents the step of processing one or more injector regions in the first semiconductor material prior to, or subsequent to, the wafer bonding step508.

Block512represents a device fabricated using the above method. The device may be a heterojunction bipolar transistor or field effect transistor, for example. If the device is an optical device, such as a light emitting diode, diode laser, solar cell or photodetector, the injector region would include the n-type and/or p-type region, and the III-nitride would include the active light emitting region or active light sensitive region. The injector regions of the device may have reduced dopant diffusion and current leakage as compared to a heterojunction formed at a temperature above 550° C.

Block512also represents an electronic device fabricated using a process comprising wafer bonding a first semiconductor material to a second semiconductor material at a temperature below 550° C. to form a device quality heterojunction between the first semiconductor material and the second semiconductor material, wherein the first semiconductor material includes one or more injector regions, and the second semiconductor material includes one or more active regions, and wherein the second semiconductor material comprises a III-nitride semiconductor, the first semiconductor material has a different material composition from the second semiconductor material, and the first semiconductor material is selected for superior properties in the injector region as compared to the second semiconductor material. The active region may be a collector, drain, channel, light emitting region, or light sensitive region.

Possible Modifications

The device200may be an HBT or a DHBT, for example. The device200may be an n-p-n or p-n-p transistor, and the source310and drain306amay be n-type or p-type. The injector and collector or drain regions may be unipolar.

Devices200,300may further comprise an additional intermediate region between the semiconductor material302and the III-nitride304, for enhancing bond strength and conductivity of the heterojunction308, wherein the additional intermediate region is selected, for example, from a group comprising In, InP, a III-P or III-As compound, and is on a bonding face of the semiconductor material302or III-nitride material304.

Advantages and Improvements

The wafer bond between the semiconductor and the III-nitride to form the device quality heterojunction, may be for reducing thermal mismatch strain, dislocation distribution and impurity distribution in the semiconductor material and the III-nitride material.

REFERENCES

CONCLUSION