Transmitting/receiving system, method, and computer readable medium

A transmitting/receiving system includes a first transmitting/receiving apparatus which includes a first transmitting unit and a first receiving unit, and a second transmitting/receiving apparatus which includes a second receiving unit, a detector, a second generator, and a second transmitting unit. The first transmitting unit transmits data with an error detecting code after a bit-number conversion. The first receiving unit receives a response to the data after a bit-number inverse conversion. The second receiving unit subjects the data to a bit-number inverse conversion. The detector detects an error from the error detecting code. The second generator generates a positive or negative acknowledgement depending on the error detection and uses a code which enables distinguishing between positive and negative acknowledgements when a 1-bit error occurs during transportation. The second transmitting unit transmits the acknowledgement after a bit-number conversion to the first transmitting/receiving apparatus.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2012-001221 filed Jan. 6, 2012.

BACKGROUND

(i) Technical Field

The present invention relates to a transmitting/receiving system, a method, and a computer readable medium.

(ii) Related Art

Systems are known in which an error occurring during transportation is detected by using a cyclic redundancy check (CRC) code as an error detecting code, and in which, as a reception response, a positive acknowledgement (ACK) is transmitted when no errors are detected, whereas a negative acknowledgement (NAK) is transmitted when an error is detected.

SUMMARY

According to an aspect of the present invention, a transmitting/receiving system includes first and second transmitting/receiving apparatuses. The first transmitting/receiving apparatus includes a first transmitting unit and a first receiving unit. The first transmitting unit subjects transmission data to which an error detecting code is attached, to a conversion of the number of bits and transmits the converted transmission data. The first receiving unit subjects a response to the transmission of the transmission data to which the error detecting code is attached, to an inverse conversion of the number of bits and receives the converted response. The second transmitting/receiving apparatus includes a second receiving unit, a detector, a second generator, and a second transmitting unit. The second receiving unit subjects the transmission data which has been transmitted by the first transmitting unit of the first transmitting/receiving apparatus, to an inverse conversion of the number of bits. The detector detects an error on the basis of the error detecting code attached to the transmission data that has been subjected to the inverse conversion of the number of bits by the second receiving unit. The second generator generates a positive acknowledgement or a negative acknowledgement in accordance with the presence or absence of the error detection performed by the detector and uses a code with which it is possible to distinguish between the positive acknowledgement and the negative acknowledgement even when a 1-bit error occurs. The 1-bit error is caused by transportation when the positive acknowledgement or the negative acknowledgement is transmitted to the first transmitting/receiving apparatus. The second transmitting unit subjects the positive acknowledgement or the negative acknowledgement generated by the second generator, to a conversion of the number of bits and transmits the converted acknowledgement to the first transmitting/receiving apparatus.

DETAILED DESCRIPTION

Hereinafter, an exemplary embodiment of the present invention will be described with reference to the drawings. In the drawings, the components having substantially the same function are designated with an identical reference character, and the repeated description will be avoided.

FIG. 1is a block diagram illustrating an exemplary configuration of a transmitting/receiving system according to an exemplary embodiment of the present invention. A transmitting/receiving system1includes a first transmitting/receiving apparatus2and a second transmitting/receiving apparatus4which are connected via a transmission path3for transmitting/receiving information in serial form. The transmission path3is formed of a first lane31, a second lane32, and a third lane33.

Configuration of First Transmitting/Receiving Apparatus

The first transmitting/receiving apparatus2includes an input/output controller21, a transmission packet generator22, 8B10B converters (8B10Bs)24A and24B and parallel/serial converters (P/Ss)26A and26B which are provided for the first lane31and the second lane32, and a retransmission controller23, a 10B8B converter (10B8B)25, and a serial/parallel converter (S/P)27which are provided for the third lane33. The transmission packet generator22exemplifies a first generator. The 8B10B converters24A and24B and the parallel/serial converters26A and26B exemplify a first transmitting unit. The 10B8B converter25and the serial/parallel converter27exemplify a first receiving unit.

Configuration of Second Transmitting/Receiving Apparatus

The second transmitting/receiving apparatus4includes serial/parallel converters (S/Ps)41A and41B, 10B8B converters (10B8Bs)43A and43B, and a cyclic redundancy check (CRC) unit45which are provided for the first lane31and the second lane32, a parallel/serial converter (P/S)42, an 8B10B converter (8B10B)44, and a response packet generator46which are provided for the third lane33, and an input/output controller47. The serial/parallel converters41A and41B and the 10B8B converters43A and43B exemplify a second receiving unit. The parallel/serial converter42and the 8B10B converter44exemplify a second transmitting unit. The CRC unit45exemplifies a detector. The response packet generator46exemplifies a second generator.

Transmission Path

The transmission path3is an electric cable for transporting electric signals. Alternatively, an optical cable for transporting optical signals may be used. When an optical cable is used, it is necessary to provide photoelectric converters on both of the transmission side and the reception side. Each of the lanes31,32, and33which form the transmission path3may include two lines which form a differential transmission line for transporting differential signals.

Configurations of Units of First and Second Transmitting/Receiving Apparatuses

The input/output controller21of the first transmitting/receiving apparatus2receives/transmits data from/to, for example, a reproducing apparatus. The input/output controller47of the second transmitting/receiving apparatus4receives/transmits data from/to, for example, a video display apparatus. The input/output controller21of the first transmitting/receiving apparatus2includes a transmission buffer (not illustrated) for storing transmitted data to be used for reproduction until a positive acknowledgement (ACK) is received.

The transmission packet generator22of the first transmitting/receiving apparatus2includes CRC generators221A and221B provided for the first lane31and the second lane32, and packetizes data, e.g., image information, to be transferred (transmission data) so as to generate a transmission packet. The transmission packet will be described in detail below.

The retransmission controller23of the first transmitting/receiving apparatus2includes an error detector231and an error correction unit232, and extracts data from the packet transmitted from the second transmitting/receiving apparatus4to the first transmitting/receiving apparatus2. When a negative acknowledgement (NAK) is transmitted from the second transmitting/receiving apparatus4, the retransmission controller23instructs the input/output controller21to retransmit the data.

The 8B10B converters24A and24B of the first transmitting/receiving apparatus2and the 8B10B converter44of the second transmitting/receiving apparatus4perform an 8B10B conversion which is a conversion of the number of bits of 8-bit data so as to output data on a 10-bit basis. The 10B8B converter25of the first transmitting/receiving apparatus2and the 10B8B converters43A and43B of the second transmitting/receiving apparatus4perform an 8B10B inverse conversion (10B8B conversion) which is an inverse conversion of the number of bits of 10-bit data by using a conversion table so as to output data on an 8-bit basis. The 8B10B conversion is a conversion for adjusting the direct current (DC) balance so that transmission data includes 0s and 1s in an appropriate manner. In a technique known as 8B10B, a group of data on an 8-bit basis is converted into 10-bit data having a ratio of the number of 0s to that of 1s which is close to a predetermined ratio of 50%, thereby adjusting the DC balance.

The CRC unit45extracts pieces of data from packets transmitted from the first transmitting/receiving apparatus2to the second transmitting/receiving apparatus4, and performs CRC calculation on them. When no CRC errors are present, the CRC unit45merges the pieces of data with each other, and outputs the merged data to the input/output controller47. The CRC unit45notifies the response packet generator46of each of the CRC results.

The response packet generator46generates a response packet in accordance with the CRC result, and transmits it to the first transmitting/receiving apparatus2. The response packet will be described in detail below.

The parallel/serial converters26A and26B of the first transmitting/receiving apparatus2and the parallel/serial converter42of the second transmitting/receiving apparatus4each convert parallel data into serial data, i.e., perform P/S conversion, so as to transmit the serial data, and include a register for settings of, for example, the de-emphasis for attenuating the direct-current component of a signal waveform, the pre-emphasis for emphasizing the high-frequency components of a signal waveform, and a differential voltage, as initial settings at the time of power-on.

The serial/parallel converter27of the first transmitting/receiving apparatus2and the serial/parallel converters41A and41B of the second transmitting/receiving apparatus4each convert serial data into parallel data, i.e., perform S/P conversion, and include a register for settings of, for example, an equalizer for correcting degradation in a signal waveform which is caused in the transmission path3, as initial settings at the time of power-on.

A part or the entirety of each of the components of the first and second transmitting/receiving apparatuses2and4, such as the input/output controller21and the serial/parallel converters41A and41B, may be formed of a hardware circuit, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). Alternatively, the components of the first and second transmitting/receiving apparatuses2and4, such as the input/output controller21and the serial/parallel converters41A and41B, may be implemented by CPUs operating in accordance with programs in the computers in the first and second transmitting/receiving apparatuses2and4.

Error Patterns

The error patterns will be described.

When 8-bit data is transmitted, the 8-bit data is converted into 10-bit data through the 8B10B conversion. There are ten patterns of the possibility that a 1-bit error occurs in the 10-bit data.FIGS. 2A to 2Hillustrate pieces of reception data which are subjected to the 8B10B inverse conversion and which correspond to the ten error patterns. InFIGS. 2A to 2H, “D00.0” to “D31.7” in the column on the left side represent transmission data before the 8B10B conversion, and “1 bit” to “10 bit” represent the position of the bit at which an error occurs and which indicates a position from the first bit. Here, the data is represented by Dxx.y, where “xx” corresponds to the lower-order five bits which represent 0 to 31, and “y” corresponds to the higher-order three bits which represent 0 to 7. For example, inFIG. 2A, in the case where the transmission data D00.0is subjected to a conversion from 8-bit into 10-bit, when an error occurs in the first bit, the data D00.0is converted into the reception data D00.2. In the case where the transmission data D00.0is subjected to a conversion from 8-bit into 10-bit, when an error occurs in the third bit, a not-in-table (NIT) error occurs because the corresponding data is not present in the conversion table.FIGS. 2A to 2Hillustrate that all pieces of data corresponding to the “6 bit” to the “10 bit”, i.e., lower-order five bits, are not-in-table (NIT) errors inFIGS. 2A,2D,2E, and2H.

FIG. 3is a table describing the error patterns inFIGS. 2A to 2Has the relationship between the transmission data and the reception data. InFIG. 3, ‘C’ represents correct reception data, and ‘E’ represents reception data in which a 1-bit error occurs. In the case where Dxx.0is transmitted as transmission data, as seen inFIG. 2A, Dxx.0, Dxx.1, Dxx.2, Dxx.5, or Dxx.6may be received as reception data. In the case where Dxx.3is transmitted as transmission data, as seen inFIG. 2D, Dxx.3, Dxx.4, or Dxx.7may be received as reception data.

Structure of Transmission Packet

FIG. 4illustrates an exemplary configuration of a transmission packet generated by the transmission packet generator22of the first transmitting/receiving apparatus2. A transmission packet100includes a header110, data120to be transferred, a CRC code130, and an end packet140indicating the end of the transmission packet100. The header110includes a start packet111constituted by a code, such as a K code, indicating the start of the transmission packet100, a dummy bit stream112of 3 bits, and a sequence ID113which identifies the first lane31or the second lane32and which serves as identification information of the transmission packet100. For example, serial numbers are alternately attached as the sequence IDs to a transmission packet100to be transmitted via the first lane31and a transmission packet100to be transmitted via the second lane32, whereby it is possible to identify the transmission packets100and to identify the first lane31or the second lane32, depending on whether the least significant bit (LSB) of sequence ID113is ‘0’ or ‘1’. The CRC code130exemplifies an error detecting code.

Each of the CRC generators221A and221B performs CRC calculation on data120to be transferred, so as to generate a CRC code130. The transmission packet generator22adds a header110, the CRC code130generated in the CRC generators221A or221B, and an end packet140to the data120to be transferred, so as to generate a transmission packet100. The transmission packet generator22uses, as the dummy bit stream112and the sequence ID113, a code, e.g., Dxx.y (xx: 0 to 31, y=0) illustrated inFIGS. 2A to 2H, with which it is possible to recognize the occurrence of a 1-bit error which is caused by the transportation when the transmission packet100is transmitted to the second transmitting/receiving apparatus4. The characters “xx” represent the lower-order five bits corresponding to the sequence ID113, and the character ‘y’ represents the higher-order three bits corresponding to the dummy bit stream112. Thus, in the case where each of the 8B10B converters24A and24B converts the dummy bit stream112and the sequence ID113from 8-bit to 10-bit and transmits the resulting data, when an error occurs in any one bit among the ten bits, the sequence ID corresponding to the lower-order five bits results in a NIT error indicating that such data is not present in the conversion table, or is received without an error.

Configuration of Response Packet

FIGS. 5A and 5Billustrate exemplary configurations of a response packet generated by the response packet generator46of the second transmitting/receiving apparatus4.FIG. 5Aillustrates a response packet for ACK andFIG. 5Billustrates a response packet for NAK.

As illustrated inFIG. 5A, an ACK response packet200aincludes a start packet210constituted by K28.0, and multiple, e.g., three, pieces of response information220a.The response information220aincludes a positive acknowledgement (ACK)221a in the higher-order three bits, and a sequence ID222in the lower-order five bits which is used to identify the lane31or32and transmission packet100. As the response information220ain the ACK response packet200a, a code, e.g., Dxx.0, is used, with which it is possible to distinguish between the ACK and the NAK even when a 1-bit error occurs which is caused by the transportation when the response information220ais transmitted to the first transmitting/receiving apparatus2. The second transmitting/receiving apparatus4transmits the response information220athree times. The number of pieces of response information220aincluded in the ACK response packet200ais not limited to three. In the start packet210, other codes other than K28.0 may be used.

As illustrated inFIG. 5B, an NAK response packet200bincludes the start packet210constituted by K28.0, and three pieces of response information220b. The response information220bincludes a negative acknowledgement (NAK)221bin the higher-order three bits, and the sequence ID222in the lower-order five bits which is used to identify the lane31or32and the transmission packet100. As the response information220bof the NAK response packet200b, a code, e.g., Dxx.3, is used, with which it is possible to distinguish between the ACK and the NAK even when a 1-bit error occurs which is caused by the transportation when the response information220bis transmitted to the first transmitting/receiving apparatus2. The second transmitting/receiving apparatus4transmits the response information220bthree times. It is possible to determine in which lane, i.e., the lane31or32, an error occurs with respect to which transmission packet100, from the NAK221band the sequence ID222. Data Dxx.3may be used in the response information220ain the ACK response packet200a,and data Dxx.0may be used in the response information220bof the NAK response packet200b. The number of pieces of response information220bincluded in the NAK response packet200bis not limited to three.

The CRC unit45performs CRC calculation. The CRC unit45merges the pieces of data to output the merged data to the input/output controller47when no CRC errors are present, and notifies the response packet generator46of each set of the CRC result and the sequence ID.

Receiving the CRC result and the sequence ID from the CRC unit45, the response packet generator46generates an ACK response packet200aillustrated inFIG. 5Aor an NAK response packet200billustrated inFIG. 5Bin accordance with the CRC result.

When the response packet generator46transmits Dxx.0as the response information220a, as illustrated inFIG. 3, the first transmitting/receiving apparatus2may receive Dxx.0, Dxx.1, Dxx.2, Dxx.5, or Dxx.6due to a 1-bit error. Accordingly, when the error detector231detects Dxx.1, Dxx.2, Dxx.5, or Dxx.6, the error correction unit232corrects the detected data Dxx.1, Dxx.2, Dxx.5, or Dxx.6into Dxx.0. When the response packet generator46transmits Dxx.3as the response information220b, as illustrated inFIG. 3, the first transmitting/receiving apparatus2may receive Dxx.3, Dxx.4, or Dxx.7due to a 1-bit error. Accordingly, when the error detector231detects Dxx.4or Dxx.7as the response information220b, the error correction unit232corrects the detected data Dxx.4or Dxx.7into Dxx.3. When the error detector231detects a NIT error, the error correction unit232discards the response packet200aor200b. Accordingly, as long as all pieces of data received N times do not result in NIT errors, it is possible for the first transmitting/receiving apparatus2to receive an ACK/NAK correctly.

Receiving an NAK response packet200bfrom the second transmitting/receiving apparatus4, the retransmission controller23of the first transmitting/receiving apparatus2controls the input/output controller21to retransmit the data corresponding to the sequence ID222. The input/output controller21outputs the data which corresponds to the sequence ID222and which is stored in the transmission buffer as retransmission data, to the transmission packet generator22.

Operations of Exemplary Embodiment

An example of operations according to the exemplary embodiment will be described.

(1) Generation and Transmission of Transmission Packet

The CRC generators221A and221B of the first transmitting/receiving apparatus2perform CRC calculation on pieces of data120that are output from the input/output controller21and that are to be transferred, to generate CRC codes130. The transmission packet generator22adds, to each piece of the data120to be transferred, a header110, a corresponding one of the CRC codes130, and an end packet140to generate a transmission packet100.

The transmission packets100generated by the transmission packet generator22are subjected to the 8B10B conversion from 8-bit data to 10-bit data by the 8B10B converters24A and24B, are converted from parallel data to serial data by the parallel/serial converters26A and26B, and are transmitted in serial form from the first transmitting/receiving apparatus2via the first lane31and the second lane32in the transmission path3to the second transmitting/receiving apparatus4.

(2) Generation and Transmission of Response Packet

When the second transmitting/receiving apparatus4receives the transmission packets100, the transmission packets100are converted from serial data to parallel data by the serial/parallel converters41A and41B, are subjected to the 8B10B inverse conversion from 10-bit data into 8-bit data by the 10B8B converters43A and43B, and are input to the CRC unit45.

The CRC unit45performs CRC calculation on the received pieces of data. When no CRC errors are present, the CRC unit45merges the pieces of data, and then outputs the merged data to the input/output controller47and notifies the response packet generator46of the CRC results and the sequence IDs.

Receiving the CRC results and the sequence IDs from the CRC unit45, the response packet generator46generates an ACK response packet200aor an NAK response packet200bin accordance with each of the CRC results.

The ACK response packet200aor the NAK response packet200bgenerated by the response packet generator46is subjected to the 8B10B conversion from 8-bit data into 10-bit data by the 8B10B converter44, and is then converted from parallel data to serial data by the parallel/serial converter42. The resulting data is transmitted in serial form from the second transmitting/receiving apparatus4via the third lane33in the transmission path3to the first transmitting/receiving apparatus2.

(3) Reception and Error Correction of Response Packet

When the first transmitting/receiving apparatus2receives an ACK response packet200aor an NAK response packet200b, the ACK response packet200aor the NAK response packet200bis converted from serial data into parallel data by the serial/parallel converter27, is subjected to the 8B10B inverse conversion from 10-bit data into 8-bit data by the 10B8B converter25, and is input into the retransmission controller23.

The retransmission controller23extracts data from the response packet200aor200btransmitted from the second transmitting/receiving apparatus4to the first transmitting/receiving apparatus2.

When the error detector231detects Dxx.4or Dxx.7other than Dxx.0and Dxx.3as the response information220a, the error correction unit232corrects the detected data Dxx.4or Dxx.7to Dxx.3. When the error detector231detects an NIT error, the error correction unit232discards the response packet200aor200b.

When the transmitting/receiving apparatus4transmits an NAK response packet200b, the retransmission controller23instructs the input/output controller21to retransmit the data.

The input/output controller21transmits data which corresponds to the sequence ID222and which is stored in the transmission buffer as data for retransmission to the transmission packet generator22, and the transmission packet generator22is instructed to retransmit it and generates a transmission packet100. The transmission packet100which is again generated is subjected to the 8B10B conversion and the parallel/serial conversion as described above, and is then transmitted to the second transmitting/receiving apparatus4.

Effect of Exemplary Embodiment

According to the exemplary embodiment, it is possible to transmit a response packet for a transmission packet without using complicated control. In addition, by transmitting response information sequentially multiple times, it is possible to transmit an ACK or an NAK correctly in comparison with a configuration in which response information is transmitted once.

As described above, the exemplary embodiment of the present invention is described. The present invention is not limited to the above-described exemplary embodiment, and various modifications may be made and embodied as long as the gist of the present invention is not modified. For example, the present invention may be used in the case where information about “Memory-Full” or “Memory-Empty” which indicates the buffer memory state on the reception side is transmitted.

In addition, for example, as long as the gist of the present invention is not modified, some of the components according to the exemplary embodiment may be removed, and steps may be, for example, added, removed, modified, or switched in the flowchart according to the exemplary embodiment. Further, programs used in the above-described exemplary embodiment may be stored in a recording medium such as a compact disc-read-only memory (CD-ROM) so as to be provided.