Apparatuses and methods for different burst lengths for stacked die

In some examples, a master die may receive data from one or more slave die. The master die may provide data from the master die and the data from the one or more slave die to a plurality of output terminals. Data from the master die may be provided for a portion of a data burst and data from the slave die may be provided for another portion of the data burst. In some examples, a master die may provide data to one or more slave die. The master die may provide data to the master die and the data to the one or more slave die from a plurality of input terminals. Data from the input terminals may be provided to the slave die for a portion of a data burst and data may be provided from the master die for another portion of the data burst.

BACKGROUND

In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking die vertically and coupling the die using through-silicon (or through-substrate) vias (TSVs) and/or wire bonds. Thus, 3D memory may also be referred to as “stacked memory.” 3D memory may provide greater memory capacity and/or higher bandwidth with less increase in area than non-3D memory. Example 3D memory devices include Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM), and Master-Slave Memory (MSM).

MSM may include multiple dynamic random access memory (DRAM) die coupled to one another in a stack. One die may serve as a master die and the remaining die may serve as slave die. The master die may control memory operations of the slave die. In some MSM, the master die and slave die may be identical with either a hardwired or programmable designation as to which die serves as the master die. In other MSM, the master die may have a different design than the slave die. The master die may be the only die of the MSM to directly interface with a component external to the memory (e.g., a substrate, a memory controller). Having only one die directly coupled to a component external to the MSM in a device including the MSM (e.g., a memory module including multiple MSMs, a computing device) may reduce loading on the device. However, this advantage may require that all data from the slave die is transmitted through the master die, which may limit bandwidth and/or speed of the MSM.

DETAILED DESCRIPTION

The apparatuses and methods disclosed herein may allow for 3D memory/stacked memory, such as master slave memory (MSM) to provide and/or receive longer burst lengths without increasing a number of connectors between the die of the stack in some embodiments. For example, a memory device may include multiple die, one of which may be a master die. The master die may include multiple input and/or output terminals. For some memory access operations, such as read operations, the memory device may retrieve data from the multiple die. Data from the die may be provided to the master die. The master die may provide data from one or more of the multiple die for different portions of a data burst (also referred to as a burst of data). For some memory access operations, such as write operations, the memory device may provide data to the multiple die. Data may be provided to the master die. The master die may provide the data to one or more of the multiple die for different portions of a data burst.

FIG.1is a schematic diagram of a memory device10including multiple die11in accordance with an embodiment of the present disclosure. In the embodiment shown inFIG.1, memory device10includes eight die11, however, memory device10may include two or more die. In some embodiments, the die11may be arranged in a stack that includes a master die12and one or more slave die13. In some embodiments, the die11may be identical to one other with respect to circuit configurations. In some embodiments, master die12may be designated as the master die and slave die13may be designated as slave die by hardwiring (e.g., fuse blowing) and/or programmed (e.g., writing to a register) on the die11. The master die (Die-0)12may include one or more pads PAD14that are coupled to a package substrate15via one or more bonding wires16. The one or more bonding wires16may be coupled to lands (e.g., pads) (not shown) of the package substrate15. Bonding Pads (PAD) of each of the slave die13(Die-1 to Die-7) may be in a floating state, decoupled from the package substrate15. The master die11may communicate with each of the slave die13(Die-1 to Die-7) by way of vias TSV17(e.g., through-substrate or through-silicon vias) and/or wire bonds (not shown). Bump electrodes18may be disposed on an outer surface of the package substrate15. The bump electrodes18may be coupled to power lines or signal channels (not shown) of memory device10or of a device including memory device10(not shown).

The memory device10may be a Master-Slave Memory (MSM) in some embodiments. That is, the master die12may be the only die of the MSM to directly interface with a component external to the memory (e.g., a substrate, a memory controller). The external component may be included in a host20(e.g., computing device, computing system) in some examples. The master die12may receive commands, addresses, data, and/or other signals from the host20and relay the commands, addresses, data and/or other signals to one or more of the slave die13when an operation utilizes one or more of the slave die13.

FIG.2is a block diagram of a memory die20in accordance with an embodiment of the present disclosure. In some embodiments, the memory die20may be used to implement one or more of die11shown inFIG.1. In some embodiments, memory die20may be a memory device. For example, the memory die20may be a volatile memory device, such as a dynamic random access memory, a static random access memory, or the like. The memory die20may be a non-volatile memory device, such as a NOR or NAND flash memory device. The memory die may also be other examples of memory devices, such as, magnetoresistive random access memory, ferroelectric memory, etc. As shown inFIG.2, the memory die20may include a memory cell array21. The memory cell array21includes a plurality of banks (e.g., BANK-0 to BANK-15), each bank including a plurality of memory cells MC arranged at intersections of a plurality of word lines WL and a plurality of bit lines BL. However, for clarity, only a single memory cell MC, word line WL, and bit line BL are shown inFIG.2. A selection of the word line WL is performed by a row decoder/driver22and a selection of the bit line BL is performed by a column decoder/driver23. Sense amplifiers SA28are coupled to corresponding bit lines BL and connected to local I/O line pairs LIOT/B. Local IO line pairs LIOT/B are connected to main IO line pairs MIOT/B via transfer gates TG29which are configured as switches.

Turning to the explanation of a plurality of external terminals (or pads) included in the memory die20, the plurality of external terminals (or pads) may include command/address terminals31, clock terminals38, data terminals37, power supply terminals41and42, and layer ID terminals50. In some embodiments, the plurality of external terminals may be included in pads14inFIG.1. The command/address terminals31may receive command address signals CA and provide the command address signals CA to a command address input circuit26. The command address input circuit26may decode the command address signals CA to generate address signals ADD provided to an address decoder27in the master die (e.g., Die-0). The address decoder27of each slave die of the slave die (e.g., Die-1 to Die-7) may receive the address signals ADD through address via45from the master die (e.g., Die-0). The address decoder27may provide decoded row address signals XADD to the row decoder/driver22, and decoded column address signals YADD to the column decoder/driver23. The address decoder27may also provide bank address signals BADD to the row decoder/driver22. While the command address terminals31and the command address input circuit26may be also included in each slave die of the slave die (e.g., Die-1 to Die-7), the address decoder27of each slave die of the slave dies (e.g., Die-1 to Die-7) may receive the address signals ADD through address via45from the master die (e.g., Die-0). That is, in some embodiments, the command address terminals31and/or command address input circuit26may be disabled and/or unused on slave die.

In master die (e.g., Die-0), the command address input circuit26may provide the command signals COM to a command decoder34. The command signals COM may include one or more separate signals. The command signals COM received by the command address terminals31may be provided to the command decoder34. The command decoder34may decode the command signals COM and provide the decoded command signals to an internal control signal generator35. The decoded command signals may be provided to an internal control signal generator35of each slave die (e.g., Die-1 to Die-7) through command via46. Thus, in some embodiments, the command decoder34of the slave die may be disabled and/or unused. The internal control signal generator35may generate various control signals. For example, the control signals may include a row command signal to select a word line and a column command signal, such as a read command or a write command, to select a bit line, and an auto refresh signal that may be provided to a self-refresh circuit36.

When a row activation command is issued and a row address is timely supplied with the activation command, and a column address is timely supplied with a read command, read data is read from memory cell or cells MC in the memory cell array21designated by the row address and column address responsive to a data strobe signal received at a DQS pad of the data terminals37. The read data DQ is provided as output signals at DQ pads of the data terminals37through a read/write amplifier (RW AMP)24and an input/output (110) circuit25and/or through data via48between the read/write amplifier24and the input/output circuit25. Similarly when the row activation command is issued and a row address are timely supplied with the activation command, and a column address is timely supplied with a write command, and then write data DQ is supplied to the DQ pads together with the data strobe signal at the DQS pad of the data terminals37, the write data DQ is supplied via the input/output circuit25and the read/write amplifier24to the memory cell array21and written in the memory cells MC designated by the row address and the column address.

The data paths between the input/output circuit25and the read/write amplifier24in a master die (e.g., Die-0) may be coupled through the data via48to the data paths between the input/output circuit25and the read/write amplifier24in each slave die of slave dies (e.g., Die-1 to Die-7). Thus, the input/output circuit25of master die (e.g., Die-0) may receive read data from one or more slave die (e.g., Die-1 to Die-7) and write data to be written into one or more slave die (e.g., Die-1 to Die-7). In some embodiments, while the slave die may include I/O circuit25and data terminals37, the I/O circuit25and/or one or more of the data terminals37may be disabled and/or unused. In some embodiments, the I/O circuit25may include switches, logic circuits and/or other control circuitry (not shown) that determines whether data from the master die or data from one or more of the slave die is provided to the DQ pads of the data terminals37. As will be described in more detail, in some embodiments, the I/O circuit25of the master die may provide data from the master die and one or more slave die on the DQ pads of the data terminals37. For example, data terminals37may include DQ pads DQ0-7. The I/O circuit25may provide data from the master die on DQ pads for a first half of a data burst and provide data from the slave die on DQ pads for a second half of the data burst.

The clock terminals38may receive external clock signals CK_t and CK_c of the master die (e.g., Die-0), respectively. These external clock signals CK_t and CK_c are complementary to each other and are supplied to a clock input circuit39. The clock input circuit39may receive the external clock signals CK_t and CK_c and may generate an internal clock signal ICLK. The clock input circuit39may provide the internal clock signal ICLK an internal clock and timing signal generator40and thus a phase controlled internal clock signal LCLK may be generated based on the received internal clock signal ICLK. Although not limited thereto, a DLL circuit can be used as the internal clock and timing signal generator40. The phase controlled internal clock signal LCLK is supplied to the input/output circuit25and may be used as a timing signal for determining an output timing of the read data DQ. The internal clock signal ICLK is also supplied to the command decoder34for decoding the command signal COM to generate various control signals. The internal clock signal ICLK from the clock input circuit39of the master die (e.g., Die-0) may be supplied through clock via47to an internal clock and timing signal generator40of the slave die (e.g., Die-1 to Die-7) to perform similar operations to the internal clock and timing signal generator40of the master die (e.g., Die-0). In some embodiments, the clock input circuit39may not be used and/or disabled on the slave die.

The power supply terminals41are supplied with power supply potentials VDDQ and VSSQ. These power supply potentials VDDQ and VSSQ are supplied to the input/output circuit25. The power supply potentials VDDQ and VSSQ may be the same potentials as the power supply potentials VDD and VSS that are supplied to the power supply terminals42, respectively. However, the dedicated power supply potentials VDDQ and VSSQ may be used for the input/output circuit25so that power supply noise generated by the input/output circuit25does not propagate to the other circuit blocks.

The power supply terminals42are supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS are supplied to a power circuit43. The internal power circuit43may generate various internal potentials VARY, VPERI, VCCP and the like based on the power supply potentials VDD and VSS. The internal potential VCCP may be a voltage higher than the power supply potential VDD generated by a charge pumping circuit (not shown) and may be mainly used in the row decoder/driver22. The internal potential VARY may be mainly used in the sense amplifiers28included in the memory cell array21, and the internal potential VPERI may be used in many other circuit blocks. The power supply potentials VDD and VSS supplied to the power supply terminals42of the master die (e.g., Die-0) may be provided to a power circuit43of each slave die (e.g., Die-1 to Die-7) through power via49in order to generate internal potentials for each slave die.

The memory die20may include pads and vias. As mentioned earlier, the pads may include the command and address terminals31, the data terminals37, the clock terminals38, and power terminals41and42. For example, the vias may be through silicon vias and the vias may include the address via45, the command via46, the clock via47, the data via48, the power via49, and layer via52. As mentioned earlier, the memory die20may be one of the plurality of die11inFIG.1and the pads of the plurality of die11and the vias of the plurality of die11may be vertically aligned with one another. The vias of the plurality of die11may be coupled to one another. Thus, various signals such command signals, address signals, data signals for receiving and transmitting from and/or to an external apparatus may be shared across the plurality of dies through the vias. In other embodiments, the vias may be replaced by wire bonds. In some embodiments, the die and/or wire bonds may not be vertically aligned (e.g., the wire need not be straight).

In some embodiments, the memory die20may include a layer identifier (ID) circuit44. The layer ID circuit44may set layer ID information unique to each memory die20in a start-up (e.g., initializing) sequence. The memory die20may further include a set of layer ID terminals50that may receive layer ID information to designate a memory die to be accessed in access operations. While the layer ID information at the terminals50is supplied to the input circuit51, the input circuit51may provide the layer ID information to the layer ID circuit44of the master die (e.g., Die-0) and may simultaneously provide the layer ID information to the layer ID circuit44of each slave die of the slave dies (e.g., Die-1 to Die-7) through the layer via52. The layer ID circuit44may activate the memory die20in response to the layer ID information and the command signals received at the command address terminals31, if the layer ID information is indicative of the memory die20. In some embodiments, the layer ID information may indicate which die in a stack of die is the master die and which die are slave die. However, in some embodiments, the master/slave assignments and/or layer ID information may be hardcoded (e.g., wired, fuse blowing) in the memory die20, for example, within the layer ID circuit44. The layer ID circuit44may also activate the internal control signal generator35and/or other circuits in some embodiments.

FIG.3is a layout diagram of a memory die30in accordance with an embodiment of the present disclosure. In some embodiments, memory die30may be included in memory die20ofFIG.2and/or one or more memory die11ofFIG.1. The memory die30may include one or more memory banks divided into groups. For example, the number of memory banks may be sixteen (e.g., BANK-0 to BANK-15) and the memory banks may be divided into four bank groups (e.g., BANK Group-0 to BANK Group-3). Thus, each bank group may include one or more banks (e.g., four banks).

The memory die30may also include peripheral areas including a central area and edge areas. The peripheral areas may include various elements shown inFIG.2. For example, one or more pads (PADs)301may be included in a central peripheral area of the memory die30. One or more vias (e.g., TSVs)302may also be included in the central peripheral area and disposed around or in the vicinity of the pads301. In some embodiments, some or all of the vias302may be replaced by wire bonds. The vias302may be used for communication between different die of a stack such as between master die12and slave die13ofFIG.1. For example, the vias302may be used to transmit commands and/or data between die. Various circuits may be disposed in the peripheral area of the memory die30. For example, input/output circuits303and read/write amplifiers304may be disposed in the central peripheral area. The input/output circuit304and the read/write amplifiers304may operate as previously described with reference toFIG.2. The arrangement of components inFIG.3is provided only as an example and the layout of the banks and peripheral areas of memory die30may be different in other embodiments. Although only the pads301and vias302, and input/output circuits303and read/write amplifiers304are shown, as noted previously, the peripheral areas may include some or all of the elements shown inFIG.2. This may leave limited space for vias and/or wire bonds.

FIG.4is a schematic diagram of a memory device400. The memory device400includes a master die402and a slave die404. In the example shown inFIG.4, the memory device400is a ×4 device with a burst length of 16 bits (16 BL). That is, the IO width is four bits (e.g., number of DQ pads406is four) and each of the DQ pads406outputs 16 bits of data in series during a burst (e.g., of a read operation). The master die402and slave die404may be coupled together (e.g., wired) such that the data provided to the DQ pads406come from the master die402or the slave die404. As discussed with reference toFIG.2, data output circuits408of the master die402may receive data from the master die402and/or slave die404and data selection circuits410of the data output circuits408may be used to provide to the DQ pads406. In some embodiments, the data selection circuit410may include a multiplexer and/or one or more OR logic gates to select between data from the master die402and slave die404.

Although only four connectors412are shown between the master die402and slave die404, in actuality, there are many more connectors (e.g., wire bonds, vias) between the master die402and slave die404to transmit data. Continuing the above example, for a ×4 IO width and a 16 BL, 64 bits of data must be transmitted to the DQ pads406. Typically, all 64 bits are provided to the data output circuits408in parallel, which then serializes the bits with a serializer circuit414for output to the DQ pads406. In some embodiments, the serializer circuit414may include a first-in-first-out (FIFO) circuit. Providing all of the bits in parallel from the slave die404to the master die402requires 64 vias and/or wire bonds.

If a burst length of 32 bits (32 BL) rather than 16 bit (16 BL) was desired from memory device400, 128 connectors would be required. In some applications, the memory die may not be capable of supporting 128 connectors. Thus, a memory device that can support longer burst lengths without increasing (or without significantly increasing) the number of connectors between master and slave die is desired.

In some embodiments of the disclosure, a memory device may include multiple die, one of which may be a master die. The master die may include multiple output terminals (e.g., DQ pads). The memory device may retrieve data (e.g., responsive to a read command) from the multiple die, and data from the die may be provided to the master die. The master die may serialize data from each of the multiple die and provide the data to the output terminals. Serialized data from one die may be provided for one portion of a data burst and serialized data from another die may be provided for another portion of the data burst. By using the multiple die to provide data for different portions of the data bust, in some embodiments, the burst length of the memory device may be increased. In some embodiments, the burst length may be increased without increasing a number of connectors between the die or decreasing a number of additional connectors required.

FIG.5is a schematic diagram of a memory device500in accordance with an embodiment of the present disclosure. In some embodiments, memory device500may be included in memory device10ofFIG.1. In some embodiments, memory device500may include memory die20ofFIG.2and/or memory die30ofFIG.3. In some embodiments, memory device500may be a ×4 device with a burst length of 32 bits (32 BL).

Memory device500may include a master die502and a slave die504. Master die502and slave die504may have similar or identical circuit layouts in some embodiments. For example, master die502and slave die504may both include all of the components shown in memory die20shown inFIG.2. In some embodiments, one or more components on the slave die504may be disabled and/or unused. For example, the command decoder may be disabled and/or unused on the slave die504. Master die502and slave die504may be coupled by one or more connectors512. In some embodiments, the connectors512may include TSVs and/or wire bonds. Other suitable connectors may be used in other embodiments. As will be described, at least some of the connectors512may be used to transmit and/or receive data between the master die502and slave die504.

The master die502may include multiple output terminals506. In the example shown inFIG.5, the master die includes four output terminals506DQ0-3. One or more of the output terminals from output terminals506may be coupled to a component external to memory device500(e.g., a substrate, a memory controller). The output terminals506may receive data from an data output circuits508of the master die502. The data output circuits508may be included in an IO circuit, such as IO circuit25, in some embodiments. The data output circuits508may include a serializer circuit514and an output buffer516in some embodiments. In some embodiments, such as the one shown inFIG.5, the data output circuits508may include a serializer circuit514and an output buffer516for each of the output terminals506.

The data output circuits508may receive data from a memory cell array (not shown inFIG.5), such as memory cell array21, of the master die502via data path520. Data path520may include a conductive line between a read/write amplifier (not shown inFIG.5), such as read/write amplifier24, and the IO circuit25in some embodiments. The data output circuits508may receive data from a memory cell array (not shown inFIG.5) of slave die504via connectors512. In some embodiments, such as the one shown inFIG.5, the data may be provided to the connectors512via data path522. In some embodiments, the data path522may include a conductive line between a read/write amplifier (not shown inFIG.5) of the slave die504. The data output circuit508receives data from the master die502and the slave die504and provides the data from both die during a burst of data.

Data may be provided from the memory arrays of the master die502and slave die504as parallel data. For example, data paths520and522may include conductive lines for each bit of data to be transmitted. Furthermore, to transmit data from the slave die504to the master die502, the number of connectors512may equal the number of conductive lines in data path522. The parallel data may be provided to the serializer circuit514. In some embodiments, the serializer circuit514may include one or more FIFO circuits. The serializer circuit514may receive the parallel data and serialize the data prior to providing the data to the output terminals506. In some embodiments, the serializer circuit514may serialize the data from the master die502or the slave die504prior to serializing the data from the other die (e.g., the data may be serialized at different times in series). In some embodiments, the serializer circuit514may serialize data from the master die502and the slave die504concurrently (e.g., the data may be serialized at the same time or nearly the same time). In some embodiments, the serialized data may be provided to an output buffer516prior to being provided to the output terminals506.

The slave die502may also include data output circuits524. In some embodiments, the output circuits524may include similar or identical components to the data output circuits508. For example, the output circuits524may include serializer circuit526, which may be similar or identical to the serializer circuit514. However, the data output circuits524may be disconnected and/or disabled. For example, a layer ID circuit, such as layer ID circuit44, of the slave die502may disable the data output circuits524. In some examples, the data output circuits524may be disabled when data from the data paths522are provided to the data output circuits508of the master die502. In some embodiments, the data output circuits524may be disconnected and/or disabled by hard wiring and/or fuse blowing.

In some embodiments, data for 16 bits per output terminal506(e.g., 64 bits) may be retrieved from the master die502and the slave die504. In some embodiments, the serializer circuit514may serialize data from the master die502to provide data for one portion of a data burst and serialize data from the slave die504to provide data for another portion of a data burst. Thus, each die may provide a portion of the data for a data burst. In the example shown inFIG.5, the master die502and the slave die504each provide 16 bits of data such that the memory device500outputs data for a burst length of 32.

In addition to providing parallel data from the memory arrays, in some embodiments, the data from the master die502and slave die504may be accessed/retrieved concurrently. That is, the data may be retrieved from both die and provided to the data output circuit508simultaneously and/or near simultaneously in some embodiments. In other embodiments data may be provided from the master die502or the slave die504first and data from the other die may be provided later. In these embodiments, data may be retrieved from one die while data from the other die is being serialized and/or provided as an initial portion of a data burst. Thus, in some embodiments, the data transmission rate between the slave die504and the master die502may be slower than the transmission rate of data between the master die502and the output terminals506. This may reduce power consumption and/or reduce stress on the connectors512in some embodiments.

In contrast to the embodiment shown inFIG.4, instead of providing data for the entire data burst from either the master die502or the slave die504as in memory device400, in some embodiments, memory device500may provide a portion of the data from the master die502and another portion of the data from the slave die504for a data burst. Providing different portions of the data from different die of the memory device500for a data burst may reduce a number of connectors512required to support, for example a 32 BL, in some embodiments. For example, to support a 32 BL, memory device500may only require 64 connectors512instead of 128 as memory device400would require.

In some embodiments, the number of connectors512may be further reduced by using double pumping. In double pumping, two bits are provided serially to the data output circuits508. Thus, the number of connectors512may be reduced from64to32. However, double pumping could require transferring data at twice the speed and/or utilize more power.

Embodiments of the disclosure are not limited to a particular number of die (e.g., two die as shown inFIG.5) or a particular burst length (e.g., 32 BL as shown inFIG.5). Rather, apparatuses and methods disclosed herein may be applied to any number of die and burst length. Furthermore, in some embodiments, different die may provide different proportions of the data burst (e.g., the master die may provide 24 bits and the slave die may provide 8 bits).

FIG.6is a block diagram of a serializer circuit600in accordance with an embodiment of the present disclosure. In some embodiments, the serializer circuit600may be included in serializer circuit514. In some embodiments, serializer circuit600may be included in IO circuit25. The serializer circuit600may receive bits <DM0:DM15> from a master die, such as master die502or master die12. The bits <DM0:DM15> may be received as parallel data from data path602. In some embodiments, data path602may be included in data path520. The serializer circuit600may receive bits <DS0;DS15> from a slave die, such as slave die504or slave die13. The bits <DS0:DS15> may be received as parallel data from data path604. In some embodiments, data path604may be included in data path522and/or connectors512. In some embodiments, bits <DM0:DM15> and bits <DS0:DS15> may be received concurrently. In some embodiments, bits <DM0:DM15> and bits <DS0:DS15> may be received at different times. For example, in some embodiments, bits <DM0:DM15> may be received prior to bits <DS0:DS15>.

The serializer circuit600may serialize bits <DM0:DM15> and bits <DS0:DS15> to provide bits <D0:D31> of a 32-bit burst of data608. The burst of data608may be provided through data path606to an output terminal (not shown), such as output terminals506or output terminals37. In the example shown inFIG.6, bits <D0:D15> of the burst of data608include bits <DM0:DM15> from the master die and bits <D16:D31> of the burst of data608include bits <DS0:DS15> from the slave die. However, the arrangement of bits from the master and slave die in the burst of data608may be different in other examples (e.g., bits <D0:D15> of the burst of data608include bits <DS0:DS15> from the slave die and bits <D16:D31> of the burst of data608include bits <DM0:DM15> from the master die; the data <DM0:DM15> from the master die and the data <DS0:DS15> from the slave die may be interleaved, etc.). Alternatively or additionally, in other examples, other portions of the burst of data608may have come from other die. For example, bits <D0:D15> of the burst of data608may include bits <DS0:DS15> from the slave die and bits <D16:D31> of the burst of data608may include bits <DM0:DM15> from the master die.

FIG.7is a schematic diagram of a memory device700in accordance with an embodiment of the present disclosure. In some embodiments, memory device700may be included in memory device10ofFIG.1. In some embodiments, memory device700may include memory die20ofFIG.2and/or memory die30ofFIG.3. In some embodiments, memory device700may be a ×4 device. Memory device700may include master die702and slave die704,705, and707. The master die702and slave die704,705, and707may include one or more components substantially the same as master die502and slave die504, respectively, for example, data output circuits, data paths, and connectors. For brevity, an explanation of these components will not be repeated here.

In some embodiments, a 32 BL may be supported by memory device700by providing a portion of the data from each die702,704,705, and707for different portions of the data burst. In some embodiments, each die702,704,705, and707may provide 8 bits of data for the 32 bit data burst. For example, bits <31:0> of the 32-bit burst may include: bits <7:0> from the master die702, bits <15:8> from die704; bits <23:16> from die705; and bits <31:24> from die707. Data for the data burst from all of the die are provided from the master die702to output terminals706.

Similar to memory device500, data may be provided from the memory arrays of the master die702and slave die704,705, and707as parallel data which may then be serialized on the master die702. In some embodiments, the data from the master die702and slave die704,705, and707may be accessed/retrieved concurrently. That is, the data may be retrieved from all die and provided the data output circuits of the mater die702simultaneously or near simultaneously. However, in other embodiments, retrieving and/or providing the data from the die may be staggered in time (e.g., data from slave die704is provided prior to the data from slave die705). In some embodiments, memory device700may require fewer connectors between the die702,704,705, and707to support a 32 BL than a memory device that acquires all of the data from a single die.

FIG.8is a flow chart of a method800in accordance with an embodiment of the present disclosure. In some embodiments, some or all of the method800may be performed by memory device10, memory die20, memory die30, memory device500, and/or memory device700.

At block802, “receiving a read command” may be performed. In some embodiments, the read command may be received at a command decoder, such as command decoder34. At block804, “providing a decoded read command” may be performed. The decoded read command may be provided by the command decoder in some embodiments. In some embodiments, the decoded read command may be provided to a first die and a second die. In some embodiments, the first die may be a master die, such as master die12,502, and/or702. In some embodiments, the second die may be a slave die, such as slave die13,504,704,705, and/or707. In some embodiments, the command decoder is located on the first die.

At block806, “retrieving first data” may be performed. In some embodiments, the retrieving is performed responsive to the decoded read command. In some embodiments, the first data may be retrieved from a memory cell array, such as memory cell array21, of the first die. At block808, “retrieving second data” may be performed. In some embodiments, the retrieving is performed responsive to the decoded read command. In some embodiments, the second data may be retrieved from a memory cell array, such as memory cell array21, of the second die. In some embodiments, blocks806and808may be performed concurrently (e.g., at the same time, simultaneously or near simultaneously). In some embodiments, block806may be performed before block808. In some embodiments, block808may be performed before block806. That is, blocks806and808may be performed in series.

At block810, “providing first data” may be performed. In some embodiments, the first data is provided to an IO circuit, such as IO circuit25and/or a data output circuit such as data output circuit508. At block812, “providing second data” may be performed. In some embodiments, the second data is provided to an IO circuit, such as IO circuit25and/or a data output circuit such as data output circuit508. In some embodiments, blocks810and812may be performed concurrently (e.g., at the same time, simultaneously or near simultaneously). In some embodiments, block810may be performed before block812. In some embodiments, block812may be performed before block810. That is, blocks810and812may be performed in series.

At block814, “serializing the data” may be performed. Serializing the data may include serializing the first data and serializing the second data in some embodiments. In some embodiments, the serializing may be performed by a serializer circuit, such as serializer circuit514and/or serializer circuit600. In some embodiments, serializing the first data and serializing the second data may be performed concurrently. In other embodiments, serializing the first data and serializing the second data are performed in series.

At block816, “providing the data to output terminals” may be performed. In some embodiments, the output terminals may be output terminals37,505, and/or706. In some embodiments, the first data may be provided to the output terminals as a portion of a data burst. In some embodiments, the second data may be provided to the output terminals as another portion of the data burst. For example, the first data may be bits <15:0> and the second data may be bits <31:16> of a 32 BL data burst. In another example, the second data may be bits <15:0> and the first data may be bits <31:16>.

FIG.9is a timing diagram900in accordance with embodiments of the present disclosure. The timing diagram900shows the timing of serializing data from a first die DM, such as a master die, the timing of serializing data from a second die DS, such as a slave die, and the timing of providing the serialized data as a burst of data (e.g., a data burst) DQ. In some embodiments, the serializing may be performed by a serializer circuit, such as serializer circuit514and/or serializer circuit600. However, the timing of the serializing operations shown in timing diagram900are not limited to the serializer circuits514and600. Furthermore, the timings of serializing operations shown inFIG.9are merely examples and the timing of serializing operations and the operation of serializer circuits514and600are not limited to the example timings provided.

In a first example, Example A, illustrated above line902, data from both the first die and the second die are serialized beginning at or around time T0. In the example shown, 16 bits of data are provided from each die. After the data from the first die and the second die have been serialized, beginning at or around time T2, the serialized data from the first die and the second die are provided as a data burst. In the example shown inFIG.9, a delay of one unit interval (UI) is provided between the completion of serializing the data and providing the data burst. However, in other examples, there may be a different delay (e.g., zero, 2, 4 UIs). A unit interval may correspond to the duration of one bit of data. In the example shown, the burst length is 32-bits where the first 16 bits include data from the first die and the second 16 bits include data from the second die. However, the data burst may include other arrangements of the data from the first die and the second die in other examples (e.g., the first portion of the data burst may include data from the second die). In some embodiments, Example A may provide a timing of operations for when data is received from the first die and the second die concurrently. In other embodiments, data from one die may be provided prior to data being provided from the other die and the serializer circuit may wait until all data is received before serializing the data concurrently. However, in these embodiments, a delay between a read operation and providing the data for the data burst may be greater.

In a second example, Example B, illustrated below line902, data from the first die is serialized beginning at or around time T0. Data from the second die is serialized beginning at or around time T1. In the example shown, 16 bits of data are provided from each die. In the example shown, the delay between time T1and time T2is three UIs. However, in other examples, there may be a different delay between time T1and time T2(e.g., 2, 4, 8 UIs). In some embodiments of the disclosure, after the data from the first die has been serialized, but prior to the completion of serializing data from the second die, beginning at or around time T2, the serialized data from the first die is provided followed by the serialized data from the second die as a data burst. In the example shown inFIG.9, a delay of one UI is provided between the completion of serializing the data from the first die and providing the data burst. However, in other examples, there may be a different delay (e.g., zero, 2, 4 UIs). In the example shown, the burst length is 32-bits where the first 16 bits include data from the first die and the second 16 bits include data from the second die. In some embodiments, Example B may provide a timing of operations for when data is received from the first die and the second die at different times. In some embodiments, this may permit communications between the first die and the second die to occur at a slower rate.

Although the above descriptions have been in reference to access operations where data is provided from a memory device (e.g., read operations), embodiments of the present disclosure may apply to access operations where data is provided to a memory device (e.g., write operations). For example, a burst of data may be provided to the memory device from a memory controller. The data may be received at a master die of the memory device. A portion of the burst of data may be stored on the master die and another portion of the burst of data may be stored on a slave die of the memory device. For example, if a data burst is 32-bits, the first 16 bits may be stored on the master die and the second 16 bits may be stored on the slave die.

FIG.10is a schematic diagram of a memory device1000in accordance with an embodiment of the present disclosure. In some embodiments, memory device1000may be included in memory device10ofFIG.1and/or memory device500inFIG.5. In some embodiments, memory device1000may include memory die20ofFIG.2and/or memory die30ofFIG.3. In some embodiments, memory device1000may be a ×4 device with a burst length of 32 bits (32 BL).

Memory device1000may include a master die1002and a slave die1004. Master die1002and slave die1004may have similar or identical circuit layouts in some embodiments. For example, master die1002and slave die1004may both include all of the components shown in memory die20shown inFIG.2. In some embodiments, one or more components on the slave die1004may be disabled and/or unused. For example, the command decoder may be disabled and/or unused on the slave die1004. Master die1002and slave die1004may be coupled by one or more connectors1012. In some embodiments, the connectors1012may include TSVs and/or wire bonds. Other suitable connectors may be used in other embodiments. As will be described, at least some of the connectors1012may be used to transmit and/or receive data between the master die1002and slave die1004.

The master die1002may include multiple input terminals1006. In some embodiments, the input terminals1006may also be used as output terminals during other operations, such as output terminals506. In the example shown inFIG.10, the master die1002includes four input terminals1006DQ0-3. One or more of the input terminals from input terminals1006may be coupled to a component external to memory device1000(e.g., a substrate, a memory controller). The input terminals1006may provide data to data input circuits1008of the master die1002. The data input circuits1008may be included in an IO circuit, such as IO circuit25, in some embodiments. The data input circuits1008may include a deserializer circuit1014and an input buffer1016in some embodiments. In some embodiments, such as the one shown inFIG.10, the data input circuits1008may include a deserializer circuit1014and an input buffer1016for each of the input terminals1006.

The data input circuits1008may provide data to a memory cell array (not shown inFIG.10), such as memory cell array21, of the master die1002via data path1020. Data path1020may include a conductive line between a read/write amplifier (not shown inFIG.10), such as read/write amplifier24, and the IO circuit25in some embodiments. The data input circuits1008may provide data to a memory cell array (not shown inFIG.10) of slave die1004via connectors1012. In some embodiments, such as the one shown inFIG.10, the data may be provided from the connectors1012to data path1022. In some embodiments, the data path1022may include a conductive line between a read/write amplifier (not shown inFIG.10) of the slave die1004and the connectors1012. The data input circuit1008receives data during a burst of data and provides the data to the master die1002and the slave die1004.

Data may be provided to the memory arrays of the master die502and slave die504as parallel data. For example, data paths520and522may include conductive lines for each bit of data to be transmitted. Furthermore, to transmit data to the slave die1004from the master die1002, the number of connectors1012may equal the number of conductive lines in data path1022. The parallel data may be provided from the deserializer circuit1014. The deserializer circuit1014may receive serial data from the input terminal1006and deserialize the data prior to providing the data to the master die1002and slave die1004. In some embodiments, the deserializer circuit1014may deserialize the data for the master die1002or the slave die1004and begin providing the parallel data to one of the die prior to providing the parallel data to the other. In some embodiments, the deserializer circuit1014may deserialize data from the master die1002and the slave die1004and provide the parallel data to both die concurrently (e.g., the data may be provided at the same time or nearly the same time). In some embodiments, the serialized data may be provided to an input buffer1016prior to being provided to the deserializer circuit1014.

The slave die1002may also include data input circuits1024. In some embodiments, the input circuits1024may include similar or identical components to the data input circuits1008. For example, the input circuits1024may include deserializer circuit1026, which may be similar or identical to the deserializer circuit1014. However, the data input circuits1024may be disconnected and/or disabled. For example, a layer ID circuit, such as layer ID circuit44, of the slave die1002may disable the data input circuits1024. In some embodiments, the data input circuits1024may be disconnected and/or disabled by hard wiring and/or fuse blowing.

In some embodiments, data for 16 bits per input terminal1006(e.g., 64 bits) may be provided to the master die1002and the slave die1004. In some embodiments, the deserializer circuit1014may deserialize data received in a burst of data to provide a portion of the data for a portion of the burst to the master die1002and provide another portion of the data for another portion of the data burst to slave die1004. Thus, each die may receive a portion of the data from a data burst. In the example shown inFIG.10, the master die1002and the slave die1004each receive 16 bits of data such that the memory device1000receives data for a burst length of 32. For example, bits <D0:15> may be provided to the master die1002and bits <D16:31> may be provided to the slave die1004.

The apparatuses and methods disclosed herein may allow for 3D memory/stacked memory, such as master slave memory (MSM) to provide and/or receive longer burst lengths without increasing a number of connectors between the die of the stack in some embodiments. For example, a memory device may include multiple die, one of which may be a master die. The master die may include multiple input/output terminals. For some memory access operations, such as read operations, the memory device may retrieve data from the multiple die. Data from the die may be provided to the master die. The master die may provide data from one or more of the multiple die for different portions of a data burst. For some memory access operations, such as write operations, the memory device may provide data to the multiple die. Data may be provided to the master die. The master die may provide the data to one or more of the multiple die for different portions of a data burst.

The description of certain embodiments herein is merely exemplary in nature and is in no way intended to limit the scope of the disclosure or its applications or uses. In the detailed description of the present apparatuses, systems and methods, reference is made to the accompanying drawings which form a part hereof, and which are shown by way of illustration specific embodiments in which the described apparatuses, systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice presently disclosed apparatuses and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the disclosure. Moreover, for the purpose of clarity, detailed descriptions of certain features are not discussed when they would be apparent to those with skill in the art so as not to obscure the description of embodiments of the disclosure. The detailed description is therefore not to be taken in a limiting sense, and the scope of the disclosure is defined only by the appended claims.

Of course, it is to be appreciated that any one of the examples, embodiments or processes described herein may be combined with one or more other examples, embodiments and/or processes or be separated and/or performed amongst separate devices or device portions in accordance with the present systems, devices and methods. Finally, the above-discussion is intended to be merely illustrative and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while various embodiments of the disclosure have been described in particular detail, it should also be appreciated that numerous modifications and alternative embodiments may be devised by those having ordinary skill in the art without departing from the broader and intended spirit and scope of the present disclosure as set forth in the claims that follow. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.