INTEGRATED CIRCUIT PACKAGES AND METHODS

An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include a first die having a first substrate and a first through via extending through the first substrate, a first gap-fill layer along a sidewall of the first substrate, an isolation layer on a surface of the first substrate and a surface of the first gap-fill layer, a first bonding layer over the isolation layer, and a first bonding pad in the first bonding layer. The isolation layer may overlap an interface between the sidewall of the first substrate and a sidewall of the first gap-fill layer, and may extend on sidewalls of the first through via.

BACKGROUND

The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged.

DETAILED DESCRIPTION

An integrated circuit package with an isolation layer over interfaces between a semiconductor device and an encapsulant, and a method of forming the same are provided. In accordance with some embodiments, one or more lower integrated circuit dies may be encapsulated in a lower gap-fill layer, and an isolation layer may be formed on surfaces of the lower gap-fill layer and the lower integrated circuit dies. The isolation layer may be over interfaces between the lower integrated circuit dies and the lower gap-fill layer. A bonding layer may be formed on the isolation layer and bonding pads may be formed in the bonding layer. One or more upper integrated circuit dies may be bonded to the bonding layer and the bonding pads, wherein the upper integrated circuit dies may be directly over interfaces between the lower integrated circuit dies and the lower gap-fill layer. By forming the isolation layer directly over interfaces between the lower integrated circuit dies and the lower gap-fill layer, the effect of the coefficient of thermal expansion (CTE) mismatch between the lower integrated circuit dies and the lower gap-fill layer on the bonding integrity between the upper integrated circuit dies and the bonding layer as well as the bonding pads may be eliminated or reduced, thereby eliminating or reducing the risk of the delamination of the upper integrated circuit dies during the manufacturing and the operation of the integrated circuit package. As a result, better reliability of the integrated circuit package may be achieved.

FIGS.1-13illustrate intermediate processing steps in forming an integrated circuit package. Referring first toFIG.1, lower integrated circuit dies100are attached to a carrier112by an adhesive114. The carrier112may be a semiconductor carrier, a glass carrier, a ceramic carrier, or the like. The carrier112may be a wafer. In some embodiments, the adhesive114is a thermal-release layer, such as an epoxy-based light-to-heat-conversion (LTHC) release material, which loses its adhesive property when heated. In some embodiments, the adhesive114is a UV glue, which loses its adhesive property when exposed to UV light. The layout of the lower integrated circuit dies100over the carrier112shown inFIG.1is an example, and other layouts are contemplated.

Each lower integrated circuit die100may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) die), the like, or combinations thereof.

Each lower integrated circuit die100may have a semiconductor substrate102, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate102may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate102may have an active surface (e.g., the surface facing downwards inFIG.1), which may be called a front side, and an inactive surface (e.g., the surface facing upwards inFIG.1), which may be called a back side. The back side of the semiconductor substrate102may also be referred to as a back side of the lower integrated circuit die100and the front side of the semiconductor substrate102may face a front side of the lower integrated circuit die100.

Devices (not separately illustrated) may be disposed at the active surface of the semiconductor substrate102. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, or the like. An interconnect structure104may be disposed on the active surface of the semiconductor substrate102. The interconnect structure104may interconnect the devices to form an integrated circuit. The interconnect structure104may comprise metallization patterns (not separately shown) in dielectric layers (not separately shown). The dielectric layers may be low-k dielectric layers. The metallization patterns may include metal lines and vias, which may be formed in the dielectric layers by a damascene process, such as a single damascene process, a dual damascene process, or the like. The metallization patterns may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. The metallization patterns may be electrically coupled to the devices. A seal ring105may extend through the interconnect structure104of each lower integrated circuit die100. The seal ring105may encircle the metallization patterns of the corresponding interconnect structure104in a top-down view and a region between the seal ring105and the metallization patterns may be referred to as a keep-out zone (KOZ). The seal ring105may be formed of the same or similar material and by the same or similar process as the metallization patterns. The seal ring105may be electrically isolated from the devices.

Conductive vias106may be disposed in the semiconductor substrate102. The conductive vias106may be electrically coupled to the metallization patterns of the interconnect structure104. The semiconductor substrate102may be thinned in a subsequent process to expose the conductive vias106at the inactive surface of the semiconductor substrate102. After the thinning process, the conductive vias106may be through-substrate vias (TSV), such as through-silicon vias. In some embodiments, the conductive vias106are formed by a via-first process, such that the conductive vias106may extend into the semiconductor substrate102but not into the interconnect structure104. The conductive vias106formed by a via-first process may be connected to a lower metallization pattern (e.g., closer to the semiconductor substrate102) of the interconnect structure104. In some embodiments, the conductive vias106are formed by a via-middle process, such that the conductive vias106may extend through a portion of the interconnect structure104and into the semiconductor substrate102. The conductive vias106formed by a via-middle process may be connected to a middle metallization pattern of the interconnect structure104. In some embodiments, the conductive vias106are formed by a via-last process, such that the conductive vias106may extend through an entirety of the interconnect structure104and into the semiconductor substrate102. The conductive vias106formed by a via-last process may be connected to an upper metallization pattern (e.g., further from the semiconductor substrate102) of the interconnect structure104.

A bonding layer108may be disposed on the interconnect structure104at the front side of each lower integrated circuit die100. The bonding layer108may be formed of an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a tetraethyl orthosilicate (TEOS) based oxide, or the like; a nitride such as silicon nitride or the like; or the like. The bonding layer108may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. One or more passivation layer(s) (not separately illustrated) may be disposed between the bonding layer108and the interconnect structure104.

Bonding pads110may extend through the bonding layer108and be electrically coupled to metallization patterns of the interconnect structure104. The bonding pads110may include conductive pillars, conductive pads, or the like, to which external connections can be made. In some embodiments, the bonding pads110include conductive pads at the front side of the lower integrated circuit die100and conductive vias that connect the conductive pads to the upper metallization pattern of the interconnect structure104. In such embodiments, the bonding pads110, including the conductive pads and the conductive vias, may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. The bonding pads110may be formed of a conductive material, such as copper, aluminum, or the like, by a suitable coating process, such as plating or the like.

InFIG.2, a lower gap-fill layer116is formed around the lower integrated circuit dies100and the semiconductor substrates102of the lower integrated circuit dies100are thinned to expose the conductive vias106. The lower gap-fill layer116may encircle the lower integrated circuit dies100in the top-down view. The lower gap-fill layer116may extend along sidewalls of the lower integrated circuit dies100(including the semiconductor substrates102, the interconnect structure104, and the bonding layer108). The lower gap-fill layer116may have a different CTE from components of the lower integrated circuit dies100(e.g., the semiconductor substrates102). The lower gap-fill layer116may be an insulating layer and may be formed of a dielectric material, such as silicon oxide, PSG, BSG, BPSG, a TEOS based oxide, polymer, or the like, which may be formed by a suitable deposition process such as CVD, ALD, spin-coating, or the like. Initially, the lower gap-fill layer116may cover the back sides of the lower integrated circuit dies100.

One or more thinning processes may be performed to level top surfaces of the lower gap-fill layer116with top surfaces of the lower integrated circuit dies100and to expose top surfaces the conductive vias106. The one or more thinning processes may be a chemical-mechanical polishing (CMP) process, a grinding process, an etch-back process, combinations thereof, or the like, which is performed at the back sides of the lower integrated circuit dies100. After the one or more thinning processes, the top surfaces of the lower gap-fill layer116, the lower integrated circuit dies100(including the semiconductor substrates102and the conductive vias106) may be substantially coplanar or level (within process variations).

InFIG.3, portions of the semiconductor substrates102and the lower gap-fill layer116are further removed to expose sidewalls of the conductive vias106. The removal process may be an etching process, such as a dry etching process, which selectively removes the semiconductor substrates102and the lower gap-fill layer116while leaving the conductive vias106substantially intact. In some embodiments, a removal rate of the semiconductor substrates102is similar to a removal rate of the lower gap-fill layer116, and after the removal process, the top surfaces of the lower gap-fill layer116and the semiconductor substrates102are substantially coplanar or level (within process variations).

InFIG.4, an isolation layer117is formed on the lower gap-fill layer116, the lower integrated circuit dies100, and the conductive vias106. The isolation layer117may isolate each of the conductive vias106from neighboring conductive vias106to prevent current leakage. The isolation layer117may be formed as a conformal layer, which is in contact with the sidewalls of the conductive vias106, as well as the top surfaces of the lower gap-fill layer116, the semiconductor substrates102, and the conductive vias106. The isolation layer117may overlap interfaces between the lower integrated circuit dies100(including the semiconductor substrates102) and the lower gap-fill layer116, such as the sidewalls of the semiconductor substrates102and sidewalls of the lower gap-fill layer116. As discussed in greater details below, forming the isolation layer117directly over the interfaces between the lower integrated circuit dies100and the lower gap-fill layer116may eliminate or reduce the effect of the CTE mismatch between the materials underneath, such as between the components of the lower integrated circuit dies100(e.g., the semiconductor substrates102) and the lower gap-fill layer116, on the bonding integrity between a bonding layer which is subsequently formed on the isolation layer117and upper integrated circuit dies which are subsequently bonded to the bonding layer.

The isolation layer117may be formed of one or more dielectric materials with high Young's moduli and by one or more suitable deposition processes such as CVD, ALD, or the like. In some embodiments, the isolation layer117comprises a first sublayer117A formed on the lower gap-fill layer116, the lower integrated circuit dies100, and the conductive vias106, and a second sublayer117B formed on the first sublayer117A. In such embodiments, the first sublayer117A and the second sublayer117B may comprise different materials. For example, the first sublayer117A may comprise silicon nitride, silicon carbide, or the like, and the second sublayer117B may comprise silicon oxide or the like. In some embodiments, the isolation layer117comprises a single material, such as silicon nitride or the like.

InFIG.5, portions of the isolation layer117are removed to re-expose the top surfaces of the conductive vias106. Portions of the conductive vias106may also be removed. The removal process may be, a CMP process, a grinding process, an etch-back process, combinations thereof, or the like. After the removal process, top surfaces of the isolation layer117and the conductive vias106may be substantially coplanar or level (within process variations). Portions of the isolation layer117may extend continuously from the sidewall of the conductive via106of one lower integrated circuit die100to the sidewall of the conductive via106of another lower integrated circuit die100. In the embodiments where the isolation layer117comprises the first sublayer117A and the second sublayer117B, the first sublayer117A becomes U-shaped after the removal process and extends between the sidewalls of neighboring conductive vias106of the same lower integrated circuit die100or neighboring lower integrated circuit dies100as shown in the cross-sectional view ofFIG.5. The top surfaces of the first sublayer117A, the second sublayer117B, and the conductive vias106are substantially coplanar or level (within process variations).

InFIG.6, an etch stop layer119is formed on the isolation layer117and the conductive vias106, a bonding layer118is formed on the etch stop layer119, and bonding pads120are formed in the bonding layer118and the etch stop layer119. The etch stop layer119may protect the underlying conductive vias106during the formation of the bonding pads120. The bonding pads120may be used for bonding with the upper integrated circuit dies in a subsequent process. The bonding pads120may extend through the bonding layer118and the etch stop layer119. In some embodiments, the bonding layer118is directly formed on the isolation layer117and the conductive vias106, and the bonding pads120are formed in the bonding layer118.

The bonding pads120may comprise active bonding pads120A and dummy bonding pads120B. The active bonding pads120A may be the bonding pads120that are electrically coupled with circuitry, such as the circuitry of the lower integrated circuit dies100. The active bonding pads120A may be in contact with the conductive vias106and the isolation layer117. The isolation layer117may be between the active bonding pads120A and the semiconductor substrates102. The dummy bonding pads120B may be the bonding pads120that are electrically isolated from circuitry, such as the circuitry of the lower integrated circuit dies100. The dummy bonding pads120B may be in contact with the isolation layer117and bottom surfaces of the dummy bonding pads120B may be covered by the isolation layer117. The dummy bonding pads120B may be directly over the lower gap-fill layer116and the semiconductor substrates102, and may be separated from the lower gap-fill layer116and the semiconductor substrates102by the isolation layer117.

The etch stop layer119may be formed of a dielectric material, such as silicon nitride, silicon carbide, or the like, which may be formed by a suitable deposition process such as CVD, ALD, or the like. The bonding layer118may be formed of an oxide, such as silicon oxide, PSG, BSG, BPSG, a TEOS based oxide, titanium oxide, or the like; or a nitride, such as silicon nitride, silicon oxynitride, silicon carbonitride, aluminum nitride, which may be formed by a suitable deposition process such as CVD, ALD, or the like. The bonding pads120may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. The bonding pads120may be formed of a metal, such as copper, aluminum, or the like, which can be formed by plating or the like. In some embodiments, a planarization process such as a CMP process, a grinding process, an etch-back process, combinations thereof, or the like, is performed on the bonding layer118and the bonding pads120. After the planarization process, top surfaces of the bonding layer118and the bonding pads120may be substantially coplanar or level (within process variations).

InFIG.7, one or more upper integrated circuit dies200are bonded to the bonding layer118and the bonding pads120. The upper integrated circuit dies200may overlap lower integrated circuit dies100. For example,FIG.7illustrates embodiments in which the upper integrated circuit dies200A overlap one lower integrated circuit die100and the upper integrated circuit die200B overlaps two lower integrated circuit dies100. The upper integrated circuit die200B also overlaps the interfaces between the lower integrated circuit dies100(including the semiconductor substrates102) and the lower gap-fill layer116. Each of the two upper integrated circuit dies200A may be electrically coupled to the corresponding lower integrated circuit dies100underneath. The upper integrated circuit die200B may be electrically coupled to both of the lower integrated circuit dies100. As a result, the lower integrated circuit dies100may be electrically coupled to each other by the upper integrated circuit die200B. In some embodiments, the upper integrated circuit die200B does not comprise any active devices and thus may be referred to as a bridge die or silicon bridge. In some embodiments, the upper integrated circuit die200B comprises active devices may be referred to as an active integrated circuit die. The layout of the upper integrated circuit dies200on the bonding layer118shown inFIG.7is an example, and other layouts are contemplated.

Each upper integrated circuit die200may be a logic die (e.g., CPU, GPU, SoC, AP, microcontroller, etc.), a memory die (e.g., DRAM die, SRAM die, etc.), a power management die (e.g., PMIC die), a RF die, a sensor die, a MEMS die, a signal processing die (e.g., DSP die), a front-end die (e.g., AFE die), the like, or combinations thereof. The materials and manufacturing processes of the features in the upper integrated circuit dies200may be found by referring to the like features in the lower integrated circuit die100. Each upper integrated circuit die200may include a semiconductor substrate202, which may have an active surface (e.g., the surface facing downwards inFIG.7), which may be called a front side, and an inactive surface (e.g., the surface facing upwards inFIG.7), which may be called a back side. The back side of the semiconductor substrate202may also be referred to as a back side of the upper integrated circuit die200and the front side of the semiconductor substrate202may face a front side of the upper integrated circuit die200.

Devices (not separately illustrated) may be disposed at the active surface of the semiconductor substrate202. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, or the like. An interconnect structure204may be disposed on the active surface of the semiconductor substrate202. The interconnect structure204may interconnect the devices to form an integrated circuit. The interconnect structure204may comprise metallization patterns (not separately shown) in dielectric layers (not separately shown). The metallization patterns may be electrically coupled to the devices. A bonding layer206may be disposed on the interconnect structure204, at the front side of the upper integrated circuit die200. One or more passivation layer(s) (not separately illustrated) may be disposed between the bonding layer206and the interconnect structure204. The bonding layer206may comprise same or similar materials to the bonding layer118.

Bonding pads208may extend through the bonding layer206may be electrically coupled to the metallization patterns of the interconnect structure204. The bonding pads208may comprise active bonding pads208A and dummy bonding pads208B. The active bonding pads208A may be the bonding pads208that are in contact with the active bonding pads120A (shown inFIG.6). The dummy bonding pads208B may be the bonding pads120that are in contact with the dummy bonding pads120B (shown inFIG.6). The active bonding pads120A and active bonding pads208A may be electrically coupled to the circuitry of the lower integrated circuit dies100and/or circuitry of the upper integrated circuit dies200. The dummy bonding pads120B and dummy bonding pads208B may be electrically isolated from the circuitry of the lower integrated circuit dies100and the circuitry of the upper integrated circuit dies200. The bonding pads208may comprise same or similar materials to the bonding pads120.

A seal ring205may extend through the interconnect structure204of each upper integrated circuit die200. The seal ring205may encircle the metallization patterns of the corresponding interconnect structure204in the top-down view and a region between the seal ring205and the metallization patterns may be referred to as the KOZ. The seal ring205may be formed of the same or similar material and by the same or similar process as the metallization patterns. The seal ring205may be electrically isolated from the devices.

The upper integrated circuit dies200may be bonded to the bonding layer118and the bonding pads120by placing the upper integrated circuit dies200using a pick-and-place process or the like, then bonding the upper integrated circuit dies200to the bonding layer118and the bonding pads120. The bonding layers206of the upper integrated circuit dies200may be directly bonded to the bonding layer118through dielectric-to-dielectric bonding, and the bonding pads208of the upper integrated circuit dies200may be directly bonded to respective bonding pads120through metal-to-metal bonding. In the embodiments illustrated inFIG.7, the size and shape of the bonding pads208are the same or similar to the respective bonding pads120. In other embodiments, the size (e.g., width) of the bonding pads208is smaller than the respective bonding pads120.

The bonding may include a pre-bonding and an annealing. During the pre-bonding, a small pressing force may be applied to press the upper integrated circuit dies200against the bonding layer118and the bonding pads120. The pre-bonding may be performed at a low temperature, such as room temperature. After the pre-bonding, direct bonds such as dielectric-to-dielectric bonds may be formed between the bonding layers206and the bonding layer118. The bonding strength between the bonding layers206and the bonding layer118may be then improved in a subsequent annealing step at a higher temperature. The bonding pads208may be in contact with the bonding pads120after the pre-bonding, or may expand to be brought into contact with the bonding pads120during the annealing. Further, during the annealing, the material of the bonding pads208may intermingle or bond with the material of the bonding pads120, so that metal-to-metal bonds may be formed.

The isolation layer117directly over the interfaces between the lower integrated circuit dies100and the lower gap-fill layer116may eliminate or reduce the effect of the CTE mismatch between the materials underneath, such as components of the lower integrated circuit dies100(e.g., the semiconductor substrates102) and the lower gap-fill layer116on the bonding integrity between the upper integrated circuit dies200and the bonding layer118as well as the bonding pads120, thereby eliminating or reducing the risk of the delamination of the upper integrated circuit dies200during the manufacturing and the operation of the integrated circuit package. As a result, better reliability of the integrated circuit package may be achieved.

FIG.7illustrates a front-to-back bonding configuration as an example, wherein the back sides of the lower integrated circuit dies100face the front sides of the upper integrated circuit dies200after bonding. Other bonding configurations may be used, such as a front-to-front bonding configuration or other bonding configuration. In the front-to-front bonding configuration the front sides of lower integrated circuit die100.

InFIG.8, an upper gap-fill layer210is formed around the upper integrated circuit dies200. The upper gap-fill layer210may encircle the upper integrated circuit dies200in the top-down view. The upper gap-fill layer210may extend along sidewalls of the upper integrated circuit dies200(including the semiconductor substrates202, the interconnect structure204, and the bonding layer206). The upper gap-fill layer210may be formed by the same or similar method and formed of the same or similar dielectric material as the lower gap-fill layer116. A thinning process may be performed to remove portions of the back sides of the semiconductor substrates202and the upper gap-fill layer210. The thinning process may be, a CMP process, a grinding process, an etch-back process, combinations thereof, or the like. After the thinning process, top surfaces of the upper gap-fill layer210, and the upper integrated circuit dies200(including the semiconductor substrates202) may be substantially coplanar or level (within process variations).

InFIG.9, a carrier212is bonded to the top surfaces of the semiconductor substrates202and the upper gap-fill layer210. The carrier212may be a semiconductor carrier, a glass carrier, a ceramic carrier, or the like. The carrier212may be a wafer having the same or similar size as the carrier112. In some embodiments, the carrier212is bonded to the semiconductor substrates202and the upper gap-fill layer210using bonding layers213and214. The bonding layer213is formed on the semiconductor substrates202and the upper gap-fill layer210, and the bonding layer214is formed on the carrier212. The bonding layer213and the bonding layer214may each comprise a dielectric material, such as silicon dioxide or the like, and may be formed by a suitable deposition process such as CVD, ALD, or the like. The structure over the carrier112may be bonded to the carrier212by bonding the bonding layer213and the bonding layer214by the same or similar process used for bonding the bonding layer118and the bonding layer206described with respect toFIG.7.

InFIG.10, the carrier112and the adhesive114is removed, and a dielectric layer216is formed on the lower gap-fill layer116and the front sides of the lower integrated circuit dies100. The removal process may include projecting a light beam such as a laser beam or a UV light beam on the adhesive114(shown inFIG.6) so that the adhesive114decomposes upon exposure to the light beam and the carrier112may be removed. In some embodiments, the dielectric layer216comprises PBO, polyimide, a BCB-based polymer, or the like, and is formed by a suitable coating process such as spin coating, lamination, or the like. In some embodiments, the dielectric layer216comprises silicon dioxide, silicon nitride, or the like, and is formed by a suitable deposition process such as CVD, ALD, or the like. In some embodiments, a redistribution structure (not separately illustrated) may be formed prior to forming the dielectric layer216to provide additional routing.

InFIG.11, under-bump metallizations (UBMs)218and electrical connectors220are formed. The UBMs218may have portions extending along a surface of the dielectric layer216and portions extending through the dielectric layer216to physically and electrically couple to the bonding pads110and the bonding pads110. As a result, the UBMs218are electrically coupled to the lower integrated circuit dies100.

As an example to form the UBMs218, the dielectric layer216may be patterned to form openings exposing the underlying bonding pads110and bonding pads110. The patterning may be done by an acceptable photolithography and etching processes, such as forming a mask then performing an anisotropic etching. The mask may be removed after the patterning. A seed layer (not separately illustrated) may be formed on the dielectric layer216, in the openings through the dielectric layer216, and on the exposed portions of the bonding pads110and the bonding pads110. The seed layer may be a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using a suitable deposition process, such as physical vapor deposition (PVD) or the like. A photoresist may be then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist may correspond to the UBMs218. The patterning may form openings through the photoresist to expose the seed layer.

A conductive material may be formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroless plating, electroplating, or the like. The conductive material may comprise a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof. Then the photoresist and portions of the seed layer on which the conductive material is not formed may be removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, portions of the seed layer on which the conductive material is not formed may be removed by an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material may form the UBMs218.

Electrical connectors220may be formed on the UBMs218. The electrical connectors220may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. In some embodiments, the electrical connectors220comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. The electrical connectors220may be formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the layer of solder has been formed on the structure, a reflow may be performed to shape the solder into the desired bump shapes. In some embodiments, the electrical connectors220comprise metal pillars, such as a copper pillar, formed by a sputtering, printing, electroplating, electroless plating, CVD, or the like, which are solder free and have substantially vertical sidewalls. A metal cap layer may be formed on top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process. The structure shown inFIG.8may be referred to as a wafer structure250.

InFIG.12, the wafer structure250is singulated to form individual integrated circuit package components250′. The processes discussed above may be performed using wafer-level processing. The carrier212may be a wafer and may include many structures (not separately illustrated) similar to the one illustrated inFIG.8. The wafer structure250may be placed on a tape222supported by a frame224. The wafer structure250may be then singulated along scribe lines226, so that the wafer structure250may be separated into discrete integrated circuit package components250′. The singulation process may include a sawing process, a laser cutting process, or the like. A cleaning process or rinsing process may be performed after the singulation process.

InFIG.13, the integrated circuit package component250′ is bonded to a package substrate228and an underfill234is formed between the integrated circuit package component250′ and the package substrate228. The package substrate228may comprise conductive pads230. In some embodiments, the package substrate228comprise materials such as fiberglass reinforced resin, bismaleimide-triazine (BT) resin, other printed circuit board (PCB) materials, or the like. In some embodiments, the package substrate228comprise materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, or the like.

The package substrate228may include active and passive devices (not separately illustrated), such as transistors, capacitors, resistors, combinations thereof, or the like. The devices may be formed using any suitable methods. The package substrate228may comprise metallization layers and vias (not separately illustrated) physically and electrically coupled to the conductive pads230. The metallization layers may be formed over the active and passive devices and may connect the various devices to form functional circuitry. The metallization layers may be alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material. In some embodiments, the package substrate228is free of active and passive devices.

During the bonding process the electrical connectors220may be reflowed to bond the integrated circuit package component250′ to the conductive pads230. The electrical connectors220may electrically and physically couple the package substrate228to the integrated circuit package component250′. In some embodiments, a solder resist (not separately illustrated) is formed on the package substrate228. The electrical connectors220may be disposed in openings in the solder resist to electrically and physically couple to the conductive pads230. The solder resist may be used to protect areas of the package substrate228from external damage.

The underfill234may surround the electrical connectors220and protect the joints resulting from the reflowing of the electrical connectors220. The underfill234may encircle the integrated circuit package component250′ in the top-down view. The underfill234may be formed by a capillary flow process after the integrated circuit package component250′ is attached or by a suitable deposition method before the integrated circuit package component250′ is attached. The underfill234may be subsequently cured. The structure shown inFIG.10may be referred to as an integrated circuit package300.

FIGS.14A and14Billustrate embodiments in which the semiconductor substrates102is recessed below the top surfaces of the lower gap-fill layer116.FIGS.14A and14Billustrate a step performed after the processes discussed above with reference toFIGS.1and2.FIG.14Ashows a structure similar to the one shown inFIG.3, in accordance with some embodiments, wherein like features refer to like features formed by like processes. InFIG.14A, portions of the semiconductor substrates102and the lower gap-fill layer116are further removed to expose sidewalls of the conductive vias106. The removal rate of the semiconductor substrates102may be higher than the removal rate of the lower gap-fill layer116, and after the removal process, the top surfaces of the semiconductor substrates102may be below the top surfaces of the lower gap-fill layer116, and the sidewalls of the lower gap-fill layer116may be exposed.

FIG.14Bshows an integrated circuit package302, which is similar to the integrated circuit package300shown inFIG.13, in accordance with some embodiments, wherein like features refer to like features formed by like processes. The integrated circuit package302may correspond to a structure obtained based on the embodiments illustrated inFIG.14Aafter the processes described with respect toFIGS.4-13are performed. InFIG.14B, the isolation layer117may overlap the interfaces between the lower integrated circuit dies100(including the semiconductor substrates102) and the lower gap-fill layer116, such as the sidewalls of the semiconductor substrates102and the sidewalls of the lower gap-fill layer116. The isolation layer117may extend on the sidewalls of the lower gap-fill layer116. Bottom surfaces of the isolation layer117may be below the top surfaces of the lower gap-fill layer116.

FIGS.15A and15Billustrate embodiments in which the lower gap-fill layer116is recessed below the top surfaces of the semiconductor substrates102.FIGS.15A and15Billustrate a step performed after the processes discussed above with reference toFIGS.1and2.FIG.15Ashows a structure similar to the one shown inFIG.3, in accordance with some embodiments, wherein like features refer to like features formed by like processes. InFIG.15A, portions of the semiconductor substrates102and the lower gap-fill layer116are further removed to expose sidewalls of the conductive vias106. The removal rate of the semiconductor substrates102may be lower than the removal rate of the lower gap-fill layer116, and after the removal process, the top surfaces of the lower gap-fill layer116may be below the top surfaces of the semiconductor substrates102, and the sidewalls of the semiconductor substrates102may be exposed.

FIG.15Bshows an integrated circuit package304, which is similar to the integrated circuit package300shown inFIG.13, in accordance with some embodiments, wherein like features refer to like features formed by like processes. The integrated circuit package304may correspond to a structure obtained based on the embodiments illustrated inFIG.15Aafter the processes described with respect toFIGS.4-13are performed. InFIG.15B, the isolation layer117may overlap the interfaces between the lower integrated circuit dies100(including the semiconductor substrates102) and the lower gap-fill layer116, such as the sidewalls of the semiconductor substrates102and the sidewalls of the lower gap-fill layer116. The isolation layer117may extend on the sidewalls of the semiconductor substrates102. Bottom surfaces of the isolation layer117may be below the top surfaces of the semiconductor substrates102.

Various embodiments are described above in the context of a system on integrated chips (SoIC) package configuration. It should be understood that various embodiments may also be adapted to apply to other package configurations, such as integrated fan-out on substrate (InFO), chip on wafer on substrate (CoWoS) or the like.

The embodiments may have some advantageous features. By forming the isolation layer117directly over the interfaces between the lower integrated circuit dies100and the lower gap-fill layer116, the effect of the CTE mismatch between components of the lower integrated circuit dies100(e.g., the semiconductor substrates102) and the lower gap-fill layer116on the bonding integrity between the upper integrated circuit dies200and the bonding layer118as well as the bonding pads120may be eliminated or reduced, thereby eliminating or reducing the risk of the delamination of the upper integrated circuit dies200during the manufacturing and the operation of the integrated circuit packages300,302, and304. As a result, better reliability of the integrated circuit packages300,302, and304.

In an embodiment, an integrated circuit package includes a first die, wherein the first die includes a first substrate and a first through via extending through the first substrate; a first gap-fill layer along a sidewall of the first substrate; an isolation layer on a surface of the first substrate and a surface of the first gap-fill layer, wherein the isolation layer overlaps an interface between the sidewall of the first substrate and a sidewall of the first gap-fill layer, and wherein the isolation layer extends on sidewalls of the first through via; a first bonding layer over the isolation layer; and a first bonding pad in the first bonding layer. In an embodiment, the first bonding pad is directly over the first gap-fill layer, and wherein the first bonding pad is separated from the first gap-fill layer by the isolation layer. In an embodiment, the first bonding pad is in contact with the isolation layer, and wherein the first bonding pad is electrically isolated from circuitry. In an embodiment, the integrated circuit package further includes a second bonding pad in the first bonding layer, wherein the second bonding pad is in contact with the first through via, and wherein the second bonding pad is electrically coupled to circuitry. In an embodiment, the isolation layer is between the second bonding pad and the first substrate. In an embodiment, the isolation layer includes two sublayers of different materials. In an embodiment, the integrated circuit package further includes an etch stop layer between the first bonding layer and the isolation layer, wherein the first bonding pad extends through the etch stop layer. In an embodiment, the integrated circuit package further includes a second die bonded to the first bonding layer and the first bonding pad, wherein the second die overlaps the interface between the sidewall of the first substrate and the sidewall of the first gap-fill layer.

In an embodiment, an integrated circuit package includes a first die, wherein the first die includes a first substrate and a first through via protruding from a top surface of the first substrate; a first gap-fill layer around the first die, wherein a coefficient of thermal expansion of the first gap-fill layer is different from a coefficient of thermal expansion of the first substrate; an isolation layer in contact with the top surface of the first substrate and a top surface of the first gap-fill layer, wherein the isolation layer overlaps an interface between the first substrate and the first gap-fill layer, and wherein the first through via extends through the isolation layer; a first bonding layer on the isolation layer; a first bonding pad in the first bonding layer; and a second die, wherein the second die includes a second bonding layer and a second bonding pad in the second bonding layer, wherein the second bonding layer is bonded to the first bonding layer, and wherein the second bonding pad is bonded to the first bonding pad. In an embodiment, the top surface of the first substrate and the top surface of the first gap-fill layer are level. In an embodiment, the top surface of the first substrate is below the top surface of the first gap-fill layer. In an embodiment, the top surface of the first substrate is above the top surface of the first gap-fill layer. In an embodiment, the first bonding pad is separated from the first gap-fill layer by the isolation layer, and wherein the first bonding pad is a dummy bonding pad.

In an embodiment, a method of forming an integrated circuit package includes attaching a first die to a carrier, wherein the first die includes a first substrate and a first through via in the first substrate; forming a first gap-fill layer on sidewalls of the first die, wherein the first gap-fill layer includes a dielectric material; removing a portion of the first gap-fill layer and a portion of the first substrate to expose the first through via; forming an isolation layer on the first substrate and the first gap-fill layer, wherein the isolation layer overlaps an interface between the first substrate and the first gap-fill layer, and wherein the first through via extends into the isolation layer; forming a first bonding layer over the isolation layer; and forming a first bonding pad in the first bonding layer, wherein the first bonding pad is in contact with the first through via. In an embodiment, forming the isolation layer includes forming a first isolation sublayer on the first substrate and the first gap-fill layer, and forming a second isolation sublayer on the first isolation sublayer, and wherein the first isolation sublayer and the second isolation sublayer include different materials. In an embodiment, a top surface of the isolation layer and a top surface of the first through via are level. In an embodiment, the isolation layer includes a silicon nitride layer. In an embodiment, the method further includes forming an etch stop layer on the isolation layer before forming the first bonding layer, wherein the first bonding pad extends through the etch stop layer. In an embodiment, the method further includes forming a second bonding pad in the first bonding layer, wherein the second bonding pad is directly over the first gap-fill layer, and wherein a bottom surface of the second bonding pad is covered by the isolation layer. In an embodiment, the method further includes bonding a second die to the first bonding layer, the first bonding pad, and the second bonding pad using dielectric-to-dielectric bonding and metal-to-metal bonding.