Current magnitude compensation for memory cells in a data storage array

A data storage device and associated method for providing current magnitude compensation for memory cells in a data storage array. In accordance with some embodiments, unit cells are connected between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common current magnitude through each of the unit cells by adjusting a voltage applied to the cells in relation to a location of each of the cells along the first and second control lines.

BACKGROUND

Solid state memories (SSMs) often comprise one or more arrays of individually programmable memory cells configured to store data by the application of write currents to the cells to store a sequence of bits. The stored bits can be subsequently read during a read operation by applying suitable read currents and sensing voltage drops across the cells.

Some SSM cell configurations employ a resistive sense element coupled to a channel based switching device. The resistive element can be programmed to different resistances to represent different bit states. The switching device provides selective access to the resistive sense element during read and write operations. The cells in an SSM array are often arranged into rows and columns, and are individually accessed by asserting various control lines such as word lines, bit lines and source lines. Some SSM configurations utilize a common source plane in lieu of individual source lines.

A continued trend is to provide SSM arrays with larger data capacities and smaller manufacturing process feature sizes (e.g., F=45 nanometers, nm or F=32 nm, where F is a minimum feature dimension of the associated manufacturing process.). While operable in providing greater data storage capacity and density levels, the use of increasingly larger arrays and/or smaller feature sizes can lead to significant increases in process parameter variations, such as variations in the electrical resistance of the control lines.

Depending on the location of a given cell within an array, it has been found that the electrical resistance of a line from an associated driver to the cell may be substantially equal in magnitude to the programmed resistance of the cell. This can make it difficult to accurately sense the programmed state of the cell, particularly when relatively small magnitudes of sense voltages are used.

SUMMARY

Accordingly, various embodiments of the present invention are generally directed to a data storage device and associated method for compensating for current magnitudes applied to memory cells (unit cells) in a data storage array.

In accordance with some embodiments, the unit cells are connected between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common current magnitude through each of the unit cells by adjusting a voltage in relation to a location of each of the unit cells along the first and second control lines.

These and other features and advantages which characterize the various embodiments of the present invention can be understood in view of the following detailed discussion and the accompanying drawings.

DETAILED DESCRIPTION

The present disclosure generally relates to the transfer of data to and from a memory space, and in particular to compensating for different magnitudes of current that may be applied to the memory cells in a data storage array during read and write operations. Prior art memory arrays often cannot reliably regulate the amount of current applied to groups of memory cells at different locations in an array for a number of reasons, such as variations in the electrical resistance of control lines connected to the cells.

Accordingly, a data storage device compensation architecture and methodology is disclosed herein that, as explained below, connects unit cells between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common current magnitude through each of the unit cells by adjusting a voltage in relation to a location of each of the unit cells along the first and second control lines.

Turning to the drawings,FIG. 1provides a functional block representation of a data storage device100constructed and operated in accordance with various embodiments of the present invention. The device100includes a top level controller102, an interface (I/F) circuit104and a data storage array106. The I/F circuit104operates under the direction of the controller102to transfer user data between the array106and a host device (not shown).

In some embodiments, the device is characterized as a solid-state drive (SSD), the controller102is a programmable microcontroller, and the array106comprises an array of nonvolatile memory cells108. In other embodiments, the data storage array106can have separate X and Y decoders110and112, respectively, to provide access to selected memory cells108. However, the configuration and operation of the various components of the data storage device100are not required or limited and can be modified, as desired.

FIG. 2shows a prior art data storage array120that incorporates a number of memory (unit) cells, denoted as122A-F. A plurality of control lines are provided to access the cells, including first, second, and third bit lines BL0124, BL1126, and BL2128, first and second word lines WL0130and WL1132, and a source plane134(VL). Each memory cell122is connected directly with the source plane134while being controlled by the respective bit and word lines.

To carry out an access operation upon a selected memory cell such as the memory cell122A, the associated bit line BL1and word line WL1are charged up to selected voltage potentials, such as VDD. A read or write current can then be induced to flow from the bit line BL1, through the cell memory element122A and into the source plane134. While operable, certain disadvantages are associated with such operation, particularly for relatively large arrays or arrays of relatively small feature sizes (e.g., F=45 nm or 32 nm).

In such cases, the electrical resistance of the bit lines increases dramatically and the resistance of the entire line can reach the same order of magnitude as the memory cell itself. This leads to significant upstream voltage drops across the bit lines, especially for cells located far away from the bit line driver. For example, for a given bit line voltage the memory cell122A will experience a significantly higher voltage as compared to the memory cell122D, due to the differences in the electrical resistance of the bit line.

FIG. 3shows another prior art data storage array140that utilizes individual source lines (SL)142rather than a common source plane134as shown inFIG. 2. The source lines142interconnect a number of memory cells144along each row (or column) in the array140. The memory cells144are denoted as M1-M4, and each includes a resistive sense element146connected to a switching device148, such as a metal oxide semiconductor field effect transistor (MOSFET). Bit lines (BL) are denoted at150and word lines WL0-WL3are denoted at152. The electrical resistance of respective portions of the source lines142and bit lines150are represented by individual resistors R1-R7.

The lengths and resistances of the source lines142and bit lines150can be standardized so that the series resistance at each memory cell is substantially equal. In this way, the voltage drop at each memory cell144can be made to be substantially the same. For example, it can be seen that for a given current I supplied to the bit line150, a voltage drop VM1across the memory cell M1can be expressed as:
VM1=I(R1)+I(R5+R6+R7)=I(R1+R5+R6+R7)  (1)
while a voltage drop VM4across the memory cell M4can be expressed as:
VM4=I(R1+R2+R3+R4)  (2)
If R1=R2=R3=R4=R5=R6=R7, then VM1will substantially equal VM4. Thus, by providing a bit line142and source line144with a common resistance per length, the data storage array140can use the same bit line voltage to access each the respective memory cells146.

However, one limitation with this arrangement is the source potential of the transistors148of the various memory cells146, which will vary significantly depending on location along the respective bit and source lines. For example, the source voltage of the transistor148of memory cell M4will be substantially at ground potential, whereas the source voltage of the transistor148of memory cell M1will be at a voltage substantially equal to V=I(R5+R6+R7). The transistor148of memory cell M4will thus drive considerably more current than the transistor148of memory cell M1if the same gate voltage is applied to the respective transistor gates via word lines WL0and WL3.

This can lead to a number of problems during operation. The provision of widely different magnitudes of current through the various cells along the same row (or column) can interfere with reliable read and write operations upon the cells. For example, if the source potential is too high, insufficient write current may be presented to a particular cell so that a desired programmed state may not be obtained. Similarly, the application of too much write current may, in some cases, present a possibility of damage to the device through overheating. Excessively high write currents may also lead to other deleterious effects, such as excessive power consumption and ultimately, reduced battery life.

Some devices read the programmed state of a cell by applying a relatively small read bias current to the cell, sensing the associated voltage drop across the cell, and using a sense amplifier to compare the voltage drop to a suitable reference voltage. Wide variations in the amounts of current flowing through individual memory cells responsive to the application of a given bit line voltage may adversely affect the ability to correctly discriminate the programmed states of the cells.

Accordingly, by compensating for differences in resistance along a row by adjusting voltage, a common current can be applied to each unit cell which reduces processing time and power consumption. In contrast, differences in resistances among unit cells along a row due to various causes such as control line resistance can increase the amount of processing time and power needed to conduct common data access operations. The operation of a equalization circuit capable of independently adjusting the resistance and voltage of unit cells along a row further allows for advantageous data access operations.

FIG. 4provides an exemplary data storage array (device)160constructed and operated in accordance with various embodiments of the present invention. The array160operates to compensate for different memory cell source potentials to provide a common current magnitude to each of a plurality of unit cells162(memory cells). The exemplary cells are denoted inFIG. 4as M1-M8.

The memory cells162are arranged into rows and columns, and may have a form as set forth inFIG. 3or may take some other form. First and second control lines164and166respectively interconnect the memory cells along each row. It is contemplated that the control lines164,166have substantially the same common length and resistance per unit length. The associated parasitic resistance of each control line per length is represented by resistors168, all of which have the same resistance level.

Drivers170,172are configured to respectively direct read and write currents through each of the cells in turn in opposing directions. In some embodiments, the first control lines164are characterized as a plurality of spaced apart bit lines which extend across the top of the array for topside interconnection with the memory cells, and the second control lines166are characterized as a plurality of spaced apart source lines which extend underneath the array for bottom side interconnection with the memory cells. It is contemplated that the bit lines are parallel to the source lines and both extend in the same direction across the array.

Select lines174run in a transverse direction to the bit and source lines, and are coupled to each of the memory cells162along each column. In some embodiments, the select lines174are characterized as word lines which interconnect the gate regions of switching devices in the memory cells, as inFIG. 3.

An equalization circuit176includes respective drivers to apply variable gate voltages to the select lines174. The gate voltages are supplied in relation to the relative locations of the unit cells along the first and second control lines164,166, as well as in relation to the direction of current through the unit cells. The equalization circuit176can incorporate the bit and source line drivers170,172as desired.

When an access operation is carried out upon memory cell M1for a current direction that flows from driver170to driver172, a first gate voltage will be provided to the associated select line174by the equalization circuit176. This first gate voltage will place the memory cell M1into a conductive state, allowing a read or write current to pass from the driver170, along the first control line164, through the memory cell M1, along the second control line166, and to the driver172. While the first gate voltage will also be applied to the gate of memory cell M5(as well as any other memory cells along that column), the associated control lines for the memory cell M5will be deactivated (such as the same potential, e.g. ground), so substantially no current will flow through memory cell M5during the access operation upon M1.

It is contemplated that the switching device in M1will be operated in its linear range (e.g., not saturated), so that the magnitude of current that flows through M1will be regulated by the gate voltage supplied by the equalization circuit176to a desired, predetermined level.

To carry out an access operation upon memory cell M4in the same current direction, the equalization circuit176will apply a different, second gate voltage to the associated word line174. Because of the lower source potential of the switching device in M4due to its proximity to the driver172, the second gate voltage will be lower than the first gate voltage. In this way, the respective access currents supplied through M1and M4will be maintained at the same predetermined level (i.e., will have a common current magnitude).

FIG. 5provides another exemplary data storage device180constructed and operated in accordance with various embodiments of the present invention. Unit cells182are arranged into rows and columns, and each include a resistive sense element (RSE)184coupled to a MOSFET switching device186. The cells182are interconnected by control lines188,190and select lines192. As before, drivers194,196direct read and write currents along the respective control lines188,190in the appropriate directions to carry out read and write operations upon the memory cells182.

An equalization circuit200utilizes respective drivers202to apply different gate voltages to the gates of the MOSFETs186in relation to the location of the memory cells along the control lines188,190, as well as in relation to the direction of the read and write currents through the cells. In this way, the equalization circuit200provides a common current magnitude through each of the memory cells for a given type of operation.

As before, the control lines188,190are contemplated as being of the same common length and having substantially the same resistance per length. The parasitic resistances of the control lines188(bit lines) are represented by resistors RB204, and the parasitic resistances of the control lines190(source lines) are represented by resistors RS206.

In some embodiments, the values of the resistors204,206are nominally the same (i.e., RB=RS). In other embodiments, the resistors206of the source lines190are reduced slightly in value with respect to the resistance of the resistors204of the bit lines188, such as within 5% (e.g., 0.95 RB=RS). The use of a slightly reduced RSresistance further aids in the equalization of the current magnitudes through the respective cells, since the range of source potentials for the MOSFETs186will be slightly less through the use of reduced source resistances.

It should be noted that while the various RSEs184are not limited to a certain size, orientation, or type, in some embodiments the RSEs will constitute bidirectional memory elements that can be set to a first resistive state by current traveling in a first direction through each cell and a second resistive state by current traveling in a second direction through each cell opposite the first direction. While some embodiments contemplate that all of the memory cells182will be subjected to a common current magnitude (such as a given read current for programmed state sensing), it is further contemplated that different current magnitudes may be supplied for the memory cells along each row (or each column).

FIG. 6shows a selected unit cell182fromFIG. 5. When bidirectional memory cells are utilized, the RSE184can exhibit asymmetric write characteristics, in that a greater driver effort can be required to switch to some programmed states as compared to other programmed states. For example,FIG. 6identifies a hard programming direction for the RSE182by arrow208, and an easy programming direction for the RSE by arrow210. The hard direction208corresponds to the direction of current flow from the second control line190to the first control line188, and the easy direction210flows current in the opposite direction from the first control line188to the second control line190.

The differences between the hard and easy directions can relate to characteristics of the RSE184. By way of illustration,FIG. 7Ashows the unit cell182ofFIG. 6with a spin-torque transfer random access memory (STRAM) configuration. The RSE184is characterized as a magnetic tunneling junction (MTJ) with a fixed reference layer212and a programmable free layer214(recording layer) separated by an intervening tunneling (barrier) layer216. The reference layer212has a fixed magnetic orientation in a selected direction, as indicated by arrow218. This fixed magnetic orientation can be established in a number of ways, such as via pinning to a separate magnet (not shown).

The free layer214has a selectively programmable magnetic orientation that can be parallel (solid arrow220) or anti-parallel (dotted arrow222) with the selected direction of the reference layer212. Other respective magnetization orientations can be used, as desired.

A low resistance state for the RSE184is achieved when the magnetization of the free layer214is oriented to be substantially in the same direction (parallel) as the magnetization of the reference layer212. To orient the RSE184in the parallel low resistance state, a write current passes through the RSE so that the magnetization direction of the reference layer212sets the magnetic orientation of the free layer214. Since electrons flow in the direction opposite to the direction of current, the write current direction passes from the free layer214to the reference layer212, and the electrons travel from the reference layer to the free layer.

A high resistance state for the RSE184is established in the anti-parallel orientation in which the magnetization direction of the free layer214is substantially opposite that of the reference layer212. To orient the RSE184in the anti-parallel resistance state, a write current passes through the RSE from the reference layer212to the free layer214so that spin-polarized electrons flow into the free layer in the opposite direction. It has been found that writing to the anti-parallel state can require greater driver effort, including a larger magnitude of write current, as compared to writing to the parallel state.

FIG. 7Bshows the unit cell182ofFIG. 6with a resistive random access memory (RRAM) configuration. The RSE184is formed from opposing metal or metal alloy electrode layers224,226separated by an intervening oxide layer228. The oxide layer228normally provides the RSE with a high resistive state.

Application of a suitable programming voltage across the RSE induces metal migration from one or both of the electrodes224,226, resulting in the formation of one or more conductive filaments230that extend across the oxide layer228. The filament(s) significantly reduce the resistance of the RSE184to a second, low resistive state. The filament(s) can be retracted by the application of a second programming voltage opposite the first voltage, thereby returning the RSE to its initial, high resistance state. It has been found that some RRAM configurations can require greater write effort in programming the RSE to one state as compared to the other.

The relative ordering of the RSE184and the switching device186within the unit cell182can also induce write current asymmetries. With reference again toFIG. 6, it is noted that the easy direction210passes current through the RSE184prior to passing through the switching device186, so that the voltage at the RSE is equal to the voltage of the first control line (bit line)188. By contrast, in the hard direction208the current passes through the switching device186prior to passing through the RSE184, so that the voltage at the RSE is reduced in relation to the voltage across the switching device.

Thus, the equalization circuits disclosed herein, such as the circuit176inFIG. 4and the circuit200inFIG. 5, can be configured to obtain common current magnitudes by providing different gate voltages in relation to location of the memory cell (e.g., physical distance from driver), direction of current (e.g., from BL to SL or SL to BL), the type of access operation (e.g., a read operation or a write operation), and whether the current is being driven in the hard or easy direction through the selected cell. While in some embodiments generally the same voltages will be applied to the respective control lines, in other embodiments variations in control line voltages can also be supplied in view of the foregoing factors.

In some embodiments, voltage level values for each cell can be empirically derived or otherwise calculated, stored in a table and then referenced as required when a particular access operation is being carried out on a particular memory cell. In some embodiments, the values can be supplied to a digital to analog converter (DAC) to adjust the respective select line and/or control line drivers.

FIG. 9provides a flow chart for a COMPENSATION ROUTINE300, generally illustrative of steps carried out in accordance with various embodiments of the present invention. At step302, a plurality of unit cells are arranged in rows and columns that are connected by first and second control lines. In various embodiments, the columns of unit cells are connected by equalization (select) lines connected to an equalization circuit and the first and second control lines are substantially the same length. In addition, each unit cell can comprise an RSE coupled to a switching device that is controlled by the equalization lines.

The matching of the lengths of the first and second control lines can provide an equal series resistance at each unit cell, but generally may not fully compensate for varying source potentials experienced by the switching devices depending on the location along the row and the other factors discussed above. The voltage of predetermined unit cells are thus subsequently adjusted with an equalization circuit in step304to allow a common current to be applied to each of the unit cells along the row.

Decision step306then determines whether the direction of the current through the predetermined unit cell would be in the hard direction that could contribute to a higher voltage drop across the unit cell. If the predetermined unit cell would have current pass in the hard direction, step308further adjusts the voltage of the predetermined unit cell with the equalization circuit so that the common current can be applied to all the unit cells in the row. However, if the predetermined unit cell will not receive current in the hard direction, the compensation routine can pass to completion at step310while retaining the ability to apply a common current to each unit cell along a row.

It should be noted that the steps of the compensation routine300are merely illustrative not limited; for example, the routine shows separate adjustments for location and direction (hard or easy), but this is merely to illustrate various factors taken into account by the exemplary equalization circuits set forth herein. In some embodiments, a determination is made of all of the relevant factors associated with a particular access operation and a single, associated voltage is output in response.

As can be appreciated by one skilled in the art, the various embodiments illustrated herein provide advantages in both data storage device efficiency and complexity due to the elimination of technically challenging and erratic operations. The equalization circuit allows for more precise data access operations with more consistent operating parameters. Moreover, data access accuracy can be greatly improved by reducing the complexity associated with the various data read and write methods. However, it will be appreciated that the various embodiments discussed herein have numerous potential applications and are not limited to a certain field of electronic media or type of data storage devices.

For purposes of the appended claims, consistent with the foregoing discussion the terms “common length,” “common electrical resistance per length” and “common current magnitude” will each be understood to encompass a range of about ±5% of a nominal value. For example, two lines will be considered to have a common length if the two lines have lengths that are within ±5% of each other, and so on.