Crystal oscillator and method for performing startup of crystal oscillator

A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.

BACKGROUND

The present invention is related to crystal oscillators (XOs), and more particularly, to a XO and a method for performing startup of a XO.

For future communications application (e.g., a duty-cycled wireless/wired system), operations of a duty-cycled wireless/wired system may include three modes such as a sleep mode, a wakeup mode and a listen mode. When the system is operating in the sleep mode, a crystal oscillator (XO) therein (e.g., oscillation of the XO) can be disabled in order to save power. The system may enter the wakeup mode in order to perform startup of the XO. When oscillation of the XO turns into a steady state (e.g., an output swing of the XO reaches a predetermined level), the system may enter the listen mode in order to detect whether there is any data to be sent or received. If the speed of the startup of the XO can be improved, a time period of the system operating in the wakeup mode can be reduced, thereby reducing overall power consumption of the system.

Some fast startup methods are proposed in related arts. Some disadvantages exist in the related art, however. For example, temperature variation may impact a time length of startup of the XO, where the related arts may adopt passive devices such as inductors that are less sensitive to the temperature variation for implementing some startup related circuits, in order to make the requirement of the temperature variation as simple as possible. However, utilizing such devices may greatly increase an overall circuit area in practice.

Thus, there is a need for a novel architecture of a fast startup XO and a related fast startup method, in order to ensure that performance (e.g., speed) of startup of a XO can be less sensitive to temperature variation.

SUMMARY

An objective of the present invention is to provide a crystal oscillator (XO) and a method for performing startup of a XO, which can ensure that a fast startup technique adopted in the XO can properly work under temperature variation.

At least one embodiment of the present invention provides a XO. The XO comprises a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit comprises a resistive circuit. The XO core circuit is configured to generate a XO signal. The auxiliary oscillator is configured to generate an auxiliary signal. The frequency detection circuit is configured to generate a detection voltage according to a driving signal associated with the auxiliary signal and a first impedance of the resistive circuit. During a first phase of the XO, the auxiliary oscillator is calibrated by utilizing the XO signal as a reference signal, and the resistive circuit is calibrated by controlling the first impedance to make the detection voltage approach a reference voltage. During a second phase of the XO, the auxiliary oscillator is calibrated to make a frequency of the driving signal to be a driving frequency which makes the detection voltage approach the reference voltage, and the driving signal having the driving frequency is injected to the XO core circuit for accelerating the startup of the XO core circuit.

At least one embodiment of the present invention provides a method for performing startup of a XO. The method comprises: utilizing a XO core circuit of the XO to generate a XO signal; utilizing an auxiliary oscillator of the XO to generate an auxiliary signal; utilizing a frequency detection circuit to generate a detection voltage according to a driving signal associated with the auxiliary signal and a first impedance of the resistive circuit within the frequency detection circuit; during a first phase of the XO, calibrating the auxiliary oscillator by utilizing the XO signal as a reference signal; during the first phase, calibrating the resistive circuit by controlling the first impedance to make the detection voltage approach a reference voltage; during a second phase of the XO, calibrating the auxiliary oscillator to make a frequency of the driving signal to be a driving frequency which makes the detection voltage approach the reference voltage; and injecting the driving signal having the driving frequency to the XO core circuit for accelerating the startup of the XO core circuit.

The XO and the method provided by the embodiment of the present invention utilizes the frequency detection circuit as a reference for calibrating the auxiliary oscillator during the second phase, thereby ensuring that a frequency error between the driving signal and the XO signal falls in an allowable range even if the temperature varies. Thus, time for the startup of the XO core circuit during the second phase can be greatly reduced by injecting the driving signal to the XO core circuit. In addition, as the auxiliary oscillator can be implemented with small sized circuits such as ring oscillators, the circuit area will not be greatly increased.

DETAILED DESCRIPTION

FIG.1is a diagram illustrating startup of a crystal oscillator (XO)10with aid of an auxiliary oscillator12according to an embodiment of the present invention. As shown inFIG.1, the crystal oscillator10may comprise a XO core circuit100, a bandgap circuit101, a low dropout regulator (LDO)102and a digital control circuit103. When controlling the XO10to enter a wakeup mode from a sleep mode for eventually entering a listen mode, if there is no external oscillation source injecting initial energy to the XO core circuit100, the crystal oscillator10will takes a few milliseconds (ms) for accumulating energy on a crystal resonator of the XO core circuit100by intrinsic oscillation only, in order to makes an output swing of a XO signal FREFgrow to an available level. Thus, an auxiliary oscillator12which has a lower quality factor but a higher startup speed can be configured to inject energy to the XO core circuit100by transmitting a driving signal FDRVto the XO core circuit100, in order to accelerate startup of the XO core circuit100.

It should be noted that different relative phases (e.g. phase error) between the driving signal FDRVand the XO signal FREFmay result in different patterns of growth of the XO signal FREF, and more particularly, when a frequency of the driving signal FDRVis different from a frequency of the XO signal FREF, a beating behavior shows up, which means a growth rate of a voltage swing of the XO signal FREFis not always positive. For example, when a frequency error Δf between the driving signal FDRVand the XO signal FREFis 10000 parts per million (ppm), the startup of the XO core circuit100may operate in a positive growth rate for 1.25 microseconds (μs). When the frequency error Δf between the driving signal FDRVand the XO signal FREFis 100 ppm, the startup of the XO core circuit100may operate in a positive growth rate for 125 μs. Thus, an time period of external signal injection that is capable of accelerating the startup of the XO core circuit depends on the frequency error Δf. In practice, 1 μs of the external signal injection may be required to ensure that the XO signal FREFcan grow to an acceptable level, which makes subsequent steps of the startup be properly executed.

In practice, the XO10may be periodically switched among the sleep mode, the wakeup mode and the listen mode. Even though the frequency of the FDRVoutput from the auxiliary oscillator12may be calibrated to make the frequency error Δf less than a predetermined threshold when the XO10is first time powered on (e.g. when an electronic device such as a wireless/wired system is powered on), temperature of the electronic device may vary as time goes by, resulting the frequency error Δf exceeding an allowable range.

In order to prevent frequency error Δf introduced by temperature variation from impacting the performance of the fast startup mechanism, the auxiliary oscillator12in some embodiments may be implemented with an inductor-capacitor (LC) oscillator, which is less sensitive to the temperature variation as inductors and capacitors inherently have smaller temperature coefficients in comparison with active loads such as transistors. The inductors and the capacitors require larger area in comparison with the active devices, however. Thus, the LC oscillator may be shared by the auxiliary oscillator12and an existing frequency synthesizer within the system, instead of utilizing a dedicated LC oscillator configured for the startup of the XO10. In practice, the XO10typically has its own power management circuit (e.g. the bandgap circuit101and the LDO) and associated digital control such as the digital control circuit103, and the frequency synthesizer (e.g. the shared LC oscillator therein) has its own power management circuit and associated digital control. When performing the startup of the XO10with aid of the shared LC oscillator, the XO signal FREF, the driving signal FDRV, reference related signals (e.g. bandgap currents) and associated digital control signals need to be transmitted between the XO10and the frequency synthesizer, but the XO10and the frequency synthesizer are typically far from each other in practice (e.g. about 2000 micrometers apart), making the routing and associated multiplexer control complicated.

For a purpose of simplifying the design, it is preferable to utilize a dedicated oscillator for implementing the auxiliary oscillator12. In this embodiment, the auxiliary oscillator12may comprise a ring oscillator200which is much smaller than the LC oscillator. As the ring oscillator200is much more sensitive to the temperature variation, the auxiliary oscillator12may further comprise a calibration circuit210configured to calibrate the auxiliary oscillator12in response to the frequency error Δf introduced by process variation and temperature variation. As the auxiliary oscillator12(e.g. the ring oscillator200) is dedicated for the startup of the XO10, instead of being shared with other functional blocks, the auxiliary oscillator12can be physically close to the XO (e.g. about 100 micrometers apart), and the routing can be greatly simplified in comparison with utilizing a shared LC oscillator.

FIG.2is a diagram illustrating a fast startup XO20according to an embodiment of the present invention. As shown inFIG.2, the fast startup XO20may comprise a XO core circuit such as the XO core circuit100(labeled “XO” inFIG.2for brevity), an auxiliary oscillator such as the ring oscillator200, and a frequency detection circuit150. The XO core circuit100is configured to generate the XO signal FREF, and the ring oscillator is configured to generate an auxiliary signal FRO. In this embodiment, the fast startup XO20may further comprise an interfacing circuit coupled to the XO core circuit100, the ring oscillator200and the frequency detection circuit150, where the interfacing circuit is configured to generate the driving signal FDRVaccording to the auxiliary signal FRO. The interfacing circuit is preferable to be implemented with a divider220, but the present invention is not limited thereto. In this embodiment, the divider220is configured to perform frequency division on the auxiliary signal FROto generate the driving signal FDRV. Thus, when the calibration circuit210utilizes the XO signal FREFas a reference signal for calibrating the ring oscillator200by controlling a calibration code DCAL, related calibration flows can be executed at a frequency of the auxiliary signal FRO, thereby improving efficiency of calibration of the ring oscillator200, but the present invention is not limited thereto.

In this embodiment, the frequency detection circuit150comprises a resistive circuit such as a resistor ladder150R1(labeled “R-Ladder” inFIG.2for brevity). The frequency detection circuit150is configured to generate a detection voltage VIMPaccording to the driving signal FDRVassociated with the auxiliary signal FROand a first impedance ZRof the resistive circuit such as the resistor ladder150R1. During a first powered on phase of the fast startup XO20, the ring oscillator200is calibrated by utilizing the XO signal FREFas a reference signal after startup of the XO core circuit100is completed, and the resistor ladder150R1is calibrated by controlling the first impedance ZRto make the detection voltage VIMPapproach a reference voltage VREF. During a second powered on phase of the fast startup XO20after the first power on phase, the ring oscillator200is calibrated to make a frequency of the driving signal FDRVto be a driving frequency which makes the detection voltage VIMPapproach the reference voltage VREF, and the driving signal FDRVhaving the driving frequency can be injected to the XO core circuit100for accelerating the startup of the XO core circuit100.

In this embodiment, the frequency detection circuit150may further comprise a switched-capacitor resistor150R2, where the switched-capacitor resistor150R2is configured to provide a second impedance ZSCAaccording to the frequency of the driving signal FDRV. The frequency detection circuit150may generate the detection voltage VIMPaccording to the first impedance ZRof the resistor ladder150R1and the second impedance ZSCAof the switched-capacitor resistor150R2. In detail, the switched-capacitor resistor150R2may comprise a capacitor150C, switches SW1and SW2, and a non-overlap clock generator140. The capacitor150C has a first end coupled to a first reference terminal such as a supply voltage VDD. The switch SW1is coupled between a second reference terminal such as a ground voltage and a second end of the capacitor150C. The switch SW2is coupled between the second end of the capacitor150C and the R-ladder150R1. The non-overlap clock generator140may generate two control signals according to the driving signal FDRV, and the switches SW1and SW2are respectively controlled by the two control signals, where the two control signals non-overlap each other. According to control of the switches SW1and SW2, the second impedance ZSCAof the switched capacitor resistor150R2may be (1/(fOSC×C)), where fOSCmay represent the frequency of the driving signal FDRV, and C may represent a capacitance of the capacitor150C. In this embodiment, the reference voltage VREFmay be generated according to a ratio of a resistance of a resistor RD1to a resistance of a resistor RD2. Assuming that the resistance of the resistor RD1is equal to the resistance of the resistor RD2, when the frequency fOSCis equal to (1/(ZR×C)), the detection voltage VIMPmay be equal to the reference voltage VREF. The fast startup XO20may further comprise a comparator, where the comparator160is configured to compare the detection voltage VIMPwith the reference voltage VREFto generate a comparison result AD, and the fast startup XO20may calibrate the first impedance ZRand the frequency fOSCaccording to the comparison result AD. For example, the comparator160may utilize a first input terminal (which is labeled “+” in figures) to receive the detection voltage VIMPand utilize a second input terminal (which is labeled “−” in figures) to receive the reference voltage VREF. Related details will be described in the following paragraphs.

FIG.3is a diagram illustrating operations of the fast startup XO20during the first powered on phase and the second powered on phase according to an embodiment of the present invention, where the first powered on phase is labeled “1stpower on” inFIG.3, and the second powered on phase is labeled “2ndpower on” inFIG.3. In specific, the first powered on phase may represent a condition where a system comprising the fast startup XO20is powered on (e.g. powered on by a user). The second powered on phase may represent a condition where the fast startup XO20enters the wakeup mode from the sleep mode, where the system comprising the fast startup XO20is already active. The present invention is aimed at improving the startup of the fast startup XO20during the second powered phase.

During the first powered on phase, as the frequency error Δf may exceed the allowable range due to process variation and temperature variation, the startup of the XO core circuit100is performed without injecting the driving signal FDRVto the XO core circuit100, and is performed with intrinsic oscillation only, therefore taking a longer time to make the output swing of the XO core circuit100reaches the available level as illustrated by the bar labeled “XO power on”. After the startup of the XO core circuit100is completed, the calibration circuit210may calibrate the ring oscillator200by utilizing the XO signal F REF as the reference signal, to generate the calibration code DCALwhich controlling the frequency of the auxiliary signal FRO, thereby controlling the frequency of the driving signal FDRVto approach the frequency of the XO signal FREFas illustrated by the bar labeled “Process FCAL”. After the calibration of the ring oscillator200is completed, the frequency error Δf can be greatly reduced such as reduced to 267 ppm (which means the frequency of the driving signal FDRVis sufficiently close to the frequency of the XO signal FREF), and the fast startup XO20may calibrate the resistive circuit such as the resistor ladder150R1by controlling the first impedance ZRto make the detection voltage VIMPapproach the reference voltage VREFas illustrated by the bar labeled “REF CAL”. For example, the fast startup XO20may calibrate the resistor ladder150R1by utilizing the driving signal FDRVas a reference signal, and control the first impedance ZRof the resistor ladder (e.g. controlling switches within the resistor ladder150R1) according to the comparison result AD. In specific, as the frequency fOSCof driving signal FDRVis correct (e.g. sufficiently close to the frequency of the XO signal FREF) after the calibration of the ring oscillator200is completed, the comparison result AD indicating whether the detection voltage VIMPis greater or less than the reference voltage VREFmay also indicate whether the first impedance ZRneeds to be increased or reduced, but the present invention is not limited thereto.

During the second powered on phase after the first powered on phase, the frequency error Δf may exceed the allowable range again, e.g. Δf=93801 ppm, as the temperature is different from that during the first powered on phase. The fast startup XO20may calibrate the ring oscillator200to make the frequency of the driving signal FDRVto be a driving frequency which makes the detection voltage VIMPapproach the reference voltage VREFas illustrated by the bar labeled “Ring CAL”. For example, the fast startup XO20may calibrate the ring oscillator200(e.g. calibrate the frequency of the driving signal FDRVby utilizing the first impedance ZRof the resistor ladder150R1as a reference) according to the comparison result AD. Even though the first impedance ZRof the resistor ladder150R1may vary in response to the temperature variation, temperature coefficients of resistors are typically small enough to ensure that the frequency error Δf can be reduced to 10000 ppm or less than 10000 ppm after the calibration of the ring oscillator200is completed. In addition, mismatch of the temperature coefficients of resistors are typically ignorable. In specific, as the first impedance ZRof the resistor ladder150R1has been calibrated and the temperature coefficient of the resistor ladder150R1is small enough to be ignored, the comparison result AD indicating whether the detection voltage VIMP is greater or less than the reference voltage VREFmay also indicate whether the frequency fOSCof the driving signal FDRV(or the frequency of the auxiliary signal FROgenerated by the ring oscillator200) needs to be increases or reduced. After the calibration of the ring oscillator200by utilizing the resistor ladder150R1as a reference is completed, the subsequent startup operations properly can work. For example, the driving signal FDRVwhich has the driving frequency with the frequency error Δf not greater than 10000 ppm can be injected to the XO core circuit100for at least 1 μs as illustrated by the bar labeled “Step1” to make the swing of the XO signal F REF grows to the available level (e.g. available for being a reference signal) in order to accelerate the startup of the XO core circuit100. Then, the calibration circuit210may calibrate the ring oscillator200by utilizing the XO signal FREFwith the growth swing as the reference signal as illustrated by the bar labeled “Step2 (Temp FCAL)”, in order to further reduce the frequency error Δf, e.g. reduced to 267 ppm. As the frequency error Δf is further reduced, the driving signal FDRVcan be injected to the XO core circuit100with a higher frequency accuracy as illustrated by the bar labeled “Step 3”. Finally, the swing of the XO signal F REF can grow to a predetermined level, and the path from the divider220to the XO core circuit100may be disabled as illustrated by the bar labeled “Step4”, which means the startup of the fast startup XO20is completed.

It should be noted that as long as the frequency detection circuit150can generate the detection voltage VIMPat least according to the frequency fOSCof the driving signal FDRV, detailed implementation of the frequency detection circuit150may be different from that shown inFIG.2. For example, even though the resistor ladder150R1is coupled between the first input terminal of the comparator160and the ground voltage, and the switched capacitor resistor150R2is coupled between the first input terminal of the comparator160and the supply voltage VDD, but the present invention is not limited thereto.

FIG.4is a diagram illustrating a fast startup XO40according to another embodiment of the present invention. As shown inFIG.4, the resistor ladder150R1may be coupled between the first input terminal of the comparator160and the supply voltage VDD, and the switched capacitor resistor150R2may be coupled between the first input terminal of the comparator160and the ground voltage. The remaining blocks within the fast startup XO40are the same as the fast startup XO20, related details are not repeated here for brevity.

In addition, the resistive circuit does not have to be implemented by a resistor ladder. As long as the resistive circuit can provide the first impedance which is adjustable, alternative designs of the resistive circuit should belong to the scope of the present invention. As shown inFIG.5, which is a diagram illustrating a fast startup XO50according to yet another embodiment of the present invention, the resistive circuit may be implemented with a resistor150R1′, switches SW3and SW4, and a mesh control circuit170. In this embodiment, the switch SW3is coupled between one end of the resistor150R1′ and the ground voltage, and the switch SW4is coupled between the resistor150R1′ the other end of the resistor150R1′ and the first input terminal of the comparator160. The mesh control circuit170is coupled to the switches SW3and SW4, where the mesh control circuit170is configured to generate at least one control signal to control a ratio of a time period of the switches SW3and SW4being turned on to a time period of the switches SW3and SW4being turned off, in order to determine the first impedance ZRof the resistive circuit. For example, a control signal for controlling the switch SW3may be the same as a control signal for controlling the switch SW4, where during a first time period, both the switches SW3and SW4are turned on, and during a second time period, both the switches SW3and SW4are turned off. An equivalent value of the first impedance ZRcan be determined according to a ratio of the first time period to the second time period. The remaining blocks within the fast startup XO50are the same as the fast startup XO20, related details are not repeated here for brevity.

In some embodiment, one of the switches SW3and SW4may be omitted. For example, the switch SW3may be omitted, where the resistor150R1′ may be coupled between the switch SW4and the ground voltage. In another example, the switch SW4may be omitted, where the resistor150R1′ may be coupled between the switch SW3and the first input terminal of the comparator160.

FIG.6is a diagram illustrating a fast startup XO60according to still another embodiment of the present invention. As shown inFIG.4, the resistive circuit implemented with the resistor150R1′, the switches SW3and SW4, and the mesh control circuit170may be coupled between the first input terminal of the comparator160and the supply voltage VDD, and the switched capacitor resistor150R2may be coupled between the first input terminal of the comparator160and the ground voltage. The remaining blocks within the fast startup XO60are the same as the fast startup XO20, related details are not repeated here for brevity.

FIG.7is a diagram illustrating a working flow of a method for performing startup of a XO (e.g. the fast startup XOs20,40,50and60, and more particularly, the XO core circuit therein) according to an embodiment of the present invention. It should be noted that one or more steps may be added, deleted or modified in the working flow shown inFIG.7. In addition, if an overall result is not hindered, these steps do not have to be executed in the exact order shown inFIG.7.

In Step S710, the XO may utilize a XO core circuit thereof to generate a XO signal.

In Step S720, the XO may utilize an auxiliary oscillator thereof to generate an auxiliary signal.

In Step S730, the XO may utilize a frequency detection circuit to generate a detection voltage according to a driving signal associated with the auxiliary signal and a first impedance of the resistive circuit within the frequency detection circuit.

In Step S740, during a first powered on phase of the XO, the XO may calibrate the auxiliary oscillator by utilizing the XO signal as a reference signal after startup of the XO core circuit is completed.

In Step S750, during the first powered on phase, the XO may calibrate the resistive circuit by controlling the first impedance to make the detection voltage approach a reference voltage.

In Step S760, during a second powered on phase of the XO after the first power on phase, the XO may calibrate the auxiliary oscillator to make a frequency of the driving signal to be a driving frequency which makes the detection voltage approach the reference voltage.

In Step S770, the XO may inject the driving signal having the driving frequency to the XO core circuit for accelerating the startup of the XO core circuit.

To summarize, the fast startup XO and the associated method provided by the embodiments of the present invention calibrate the frequency detection circuit (more particularly, a resistive circuit therein) which is less sensitive to the temperature variation in comparison with the auxiliary oscillator during the first powered on phase, and then calibrate the auxiliary oscillator by utilizing the frequency detection circuit as a reference during the second powered on phase. Thus, the subsequent startup operations can be performed based on a condition where the frequency error is less than 10000 ppm, which allows the injection of the auxiliary signal to be performed at least 1 μs, ensuring that the swing of the XO signal can grow to the available level. In addition, the embodiments of the present invention will not greatly increase overall costs. Thus, the present invention can solve the problem of the related art without introducing any side effect or in a way that is less likely to introduce side effects.