STACKED MULTI-GATE DEVICE WITH AN INSULATING LAYER BETWEEN TOP AND BOTTOM SOURCE/DRAIN FEATURES

Semiconductor structures and methods of forming the same are provided. An exemplary method includes depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over a bottom epitaxial source/drain feature formed in a bottom portion of a source/drain trench, etching back the CESL and the ILD layer to expose a top portion of the source/drain trench, performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, where the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench. Method also includes removing the second portion of the insulating layer and forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the source/drain trench.

BACKGROUND

Such scaling down has also increased the complexity of processing and manufacturing ICs. For example, as integrated circuit (IC) technologies progress towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure, or portion thereof, disposed over more than one side of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. A FinFET has an elevated channel wrapped by a gate on more than one side (for example, the gate wraps a top and sidewalls of a “fin” of semiconductor material extending from a substrate). An MBC transistor has a gate structure that can extend, partially or fully, around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel regions, an MBC transistor may also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor. The channel region of an MBC transistor may be formed from nanowires, nanosheets, other nanostructures, and/or other suitable structures. The shapes of the channel region have also given an MBC transistor alternative names such as a nanosheet transistor or a nanowire transistor.

As the semiconductor industry further progresses into sub-10 nanometer (nm) technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have led to stacked device structure configurations, such as complementary field effect transistors (C-FETs) where an n-type multi-gate transistor and a p-type multi-gate transistor are stacked vertically, one over the other. Source/drain feature(s) of the n-type multi-gate transistor sometimes are isolated from source/drain feature(s) of the p-type multi-gate transistor by a combination of contact etch stop layer and an interlayer dielectric layer formed over the lower one of the source/drain feature(s) of the C-FET. While existing isolation structures between the lower one of the source/drain feature(s) of the C-FET and the upper one of the source/drain feature(s) of the C-FET are generally adequate, they are not satisfactory in all aspects.

DETAILED DESCRIPTION

A stacked multi-gate device refers to a semiconductor device that includes a bottom multi-gate device and a top multi-gate device stacked over the bottom multi-gate device. When the bottom multi-gate device and the top multi-gate device are of different conductivity types, the stacked multi-gate device may be a complementary field effect transistor (C-FET). The multi-gate devices in a C-FET may be FinFETs or MBC transistors. In some fabrication processes for forming C-FET devices, the two levels of multi-gate devices are formed sequentially. For example, source/drain features of the bottom multi-gate device (i.e., bottom source/drain features) are formed before source/drain features of the top multi-gate device (i.e., top source/drain features). In some instances, a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer are first deposited over the bottom source/drain features, and a pre-clean process is performed to the semiconductor structure before the top source/drain features are being deposited. The pre-clean process may damage the interlayer dielectric layer, disadvantageously increasing the risk of electrical short between the top and bottom source/drain features. There is a need to enhance the electrical isolation between top and bottom source/drain features without substantially damaging the channel layers of the top multi-gate device.

The present disclosure provides a method of forming an insulating layer between the bottom source/drain feature and the top source/drain feature without substantially damaging the channel layers of the top multi-gate device. In an embodiment, after etching back a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer formed on the bottom source/drain feature, a plasma-enhanced atomic layer deposition process (PEALD) is performed to form an insulating layer over the etched CESL and ILD layer. Parameters associated with the PEALD are adjusted such that a horizontal portion of the insulating layer formed on the etched CESL and ILD layer has a greater deposition thickness and better quality than the deposition thickness and quality of a vertical portion of the insulating layer that extends along sidewalls of the channel layers of the top multi-gate device. The vertical portion of the insulating layer is then selectively removed without substantially damaging the channel layers of the top multi-gate device, leaving the horizontal portion on the etched CESL and ILD layer. A top source/drain feature is then formed on the horizontal portion after a pre-clean process is performed. By forming the insulating layer between the top and bottom source/drain features, electrical isolation therebetween is advantageously enhanced, and reliability of the stacked multi-gate device is improved.

The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,FIG.1illustrates a perspective view of a semiconductor device including a vertical C-FET, according to one or more aspects of the present disclosure.FIG.2illustrates a flow chart of a method100for forming a semiconductor device200including a vertical C-FET, according to one or more aspects of the present disclosure. Method100is described below in conjunction withFIGS.3A-19, which are fragmentary cross-sectional views of the workpiece200at different stages of fabrication according to embodiments of method100. Method100is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated therein. Additional steps may be provided before, during and after method100, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity. Because the workpiece200will be fabricated into a semiconductor device200upon conclusion of the fabrication processes, the workpiece200may be referred to as the semiconductor device200as the context requires. Additionally, throughout the present application and across different embodiments, like reference numerals denote like features with similar structures and compositions, unless otherwise excepted. For avoidance of doubts, the X, Y and Z directions in the figures are perpendicular to one another and are used consistently.

FIG.1depicts an exemplary semiconductor device (e.g., C-FET)10. The semiconductor device10includes a lower device10L (e.g., p-type transistor) and an upper device10U (e.g., n-type transistor) over the lower device10L. The lower device10L includes channel layer26′L wrapped around by a bottom gate structure. The bottom gate structure includes a gate dielectric layer78and a conductive structure80L. The lower device10L also includes source/drain features (e.g., p-type epitaxial source/drain features)62L coupled to the channel layers26′L and adjacent the bottom gate structure.

The upper device10U includes channel layer26′U wrapped around by an upper gate structure. The upper gate structure includes the gate dielectric layer78and a conductive structure80U. The upper device10U also includes source/drain features (e.g., n-type epitaxial source/drain features)62U coupled to the channel layers26′U and adjacent the upper gate structure. An isolation layer90is disposed between the upper device10U and the lower device10L to electrically insulate the upper gate structure of the upper device10U from the bottom gate structure of the lower device10L. The configurations of the elements in the semiconductor device10described above are given for illustrative purposes and can be modified depending on the actual implementations. It is understood that some features are omitted in this figure for reason of simplicity.

Referring now toFIGS.2and3A-3B, method100includes a block102where a workpiece200is received.FIG.3Adepicts a cross-sectional view of the workpiece200, andFIG.3Bdepicts a cross-sectional view of the workpiece200taken along line B-B shown inFIG.3A. The workpiece200includes a substrate202. In one embodiment, the substrate202may be a silicon (Si) substrate. In some other embodiments, the substrate202may include other semiconductors such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate202may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Although not explicitly shown in the figures, the substrate202may include an n-type well region and a p-type well region for fabrication of transistors of different conductivity types. When present, each of the n-type well and the p-type well is formed in the substrate202and includes a doping profile. An n-type well may include a doping profile of an n-type dopant, such as phosphorus (P) or arsenic (As). A p-type well may include a doping profile of a p-type dopant, such as boron (B). The doping in the n-type well and the p-type well may be formed using ion implantation or thermal diffusion and may be considered portions of the substrate202. For ease of reference, the substrate202and structures formed thereon during the method100may be referred to as a workpiece200.

The workpiece200also includes fin-shaped structures210formed over the substrate202. In the present embodiments, the fin-shaped structure210is formed from a superlattice structure204and a portion of the substrate202. The superlattice structure204may be deposited over the substrate202using an epitaxy process. Suitable epitaxy processes include vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and/or other suitable processes. The superlattice structure204includes a number of channel layers208interleaved by a number of sacrificial layers206. The sacrificial layers206and the channel layers208are deposited alternatingly, one-after-another, to form the superlattice structure204. The channel layers208and the sacrificial layers206may have different semiconductor compositions. In some implementations, the channel layers208are formed of silicon (Si) and sacrificial layers206are formed of silicon germanium (SiGe). In these implementations, the additional germanium content in the sacrificial layers206allow selective removal or recess of the sacrificial layers206without inducing substantial damages to the channel layers208.

For ease of references, the superlattice structure204may be vertically divided into a bottom portion204B, a middle sacrificial layer206M on the bottom portion204B, and a top portion204T on the middle sacrificial layer206M. In this depicted example, the bottom portion204B of the super lattice structure204includes channel layers208L1,208L2and208L3interleaved by sacrificial layers206L1,206L2, and206L3. The top portion204T of the super lattice structure204includes channel layers208U1,208U2and208U3interleaved by sacrificial layers206U1and206U2. The channel layers208L1,208L2,208L3,208U1,208U2, and208U3will provide nanostructures for the C-FET10. In some embodiments, the channel layers208U1-208U2, and the channel layers208L2-208L3will provide channel members for a top MBC transistor and a bottom MBC transistor in the C-FET10, respectively. The term “channel member(s)” is used herein to designate any material portion for channel(s) in a transistor with nanoscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. A germanium content of the middle sacrificial layer206M may be different from the germanium content of other sacrificial layers (e.g., sacrificial layers206U1-206U3, sacrificial layers206L1-206L3) of the top portion204T and bottom portion204B. In some embodiments, a germanium content of the middle sacrificial layer206M may be greater than a germanium content of the other sacrificial layers206U1-206U3and206L1-206L3such that the entirety of the middle sacrificial layer206M may be selectively removed during the formation of inner spacer recesses.

It is noted that the superlattice structure204inFIGS.3A-3Bincludes six (6) layers of the channel layers208interleaved by six (6) layers of sacrificial layers206, which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of the channel layers208can be included in the superlattice structure204and distributed between the bottom portion204B and the top portion204T. The number of layers depends on the desired number of channels members for the top MBC transistor and the bottom MBC transistor. In some embodiments, the number of the channel layers208in the superlattice structure204may be between 4 and 10. The thicknesses of the channel layers208and the sacrificial layers206may be selected based on device performance considerations of the bottom MBC transistor, the top MBC transistor, and the C-FET as a whole.

After forming the superlattice structure204, the superlattice structure204and a portion of the substrate202are then patterned to form the fin-shaped structures210. For patterning purposes, a hard mask layer may be deposited over the superlattice structure204. The hard mask layer may be a single layer or a multilayer. In one example, the hard mask layer includes a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. As shown inFIGS.3A-3B, each fin-shaped structure210extends vertically along the Z direction from the substrate202and extends lengthwise along the Y direction. The fin-shaped structures210may be patterned using suitable processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers, or mandrels, may then be used as an etch mask to etch the superlattice structure204and the substrate202to form the fin-shaped structures210.

The workpiece200also includes an isolation feature212(shown inFIG.3A) formed around the fin-shaped structures210to separate two adjacent fin-shaped structures210. The isolation feature212may also be referred to as a shallow trench isolation (STI) feature212. In an example process, a dielectric material for the isolation feature212is deposited over the workpiece200, including the fin-shaped structure210, using CVD, subatmospheric CVD (SACVD), flowable CVD, spin-on coating, and/or other suitable process. Then the deposited dielectric material is planarized and recessed to form the isolation feature212. As shown inFIG.3A, the fin-shaped structure210rises above the isolation feature212. The dielectric material for the isolation feature212may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials.

Referring toFIGS.2and4, method100includes a block104where dummy gate stacks214are formed over channel regions210C of the fin-shaped structure210. In some embodiments, a gate replacement process (or gate-last process) is adopted where the dummy gate stack214serves as a placeholder for a functional gate structure. Other processes and configurations are possible. To form the dummy gate stack214, a dummy dielectric layer216, a dummy gate electrode layer218, and a gate-top hard mask layer220are deposited over the workpiece200. The deposition of these layers may include use of low-pressure CVD (LPCVD), CVD, plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, e-beam evaporation, other suitable deposition techniques, and/or combinations thereof. The dummy dielectric layer216may include silicon oxide, the dummy gate electrode layer218may include polysilicon, and the gate-top hard mask layer220may be a multi-layer that includes silicon oxide and silicon nitride. Using photolithography and etching processes, the gate-top hard mask layer220is patterned. The photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. The etching process may include dry etching, wet etching, and/or other etching methods. Like the fin-shaped structures210, the dummy gate stack214may also be patterned using double-patterning or multiple-patterning techniques. Thereafter, using the patterned gate-top hard mask220as an etch mask, the dummy dielectric layer216and the dummy gate electrode layer218are then etched to form the dummy gate stack214. The dummy gate stack214extends lengthwise along the X direction to wrap over the fin-shaped structure210and lands on the isolation feature212. The portion of the fin-shaped structure210underlying the dummy gate stack214defines a channel region210C. The channel region210C and the dummy gate stack214also define source/drain regions210SD that are not vertically overlapped by the dummy gate stack214. The channel region210C is disposed between two source/drain regions210SD along the Y direction. Source/drain region(s) may refer to a source region for forming a source or a drain region for forming a drain, individually or collectively dependent upon the context.

Still referring toFIGS.2and4, method100includes a block106where source/drain regions210SD of the fin-shaped structure210are recessed to form source/drain recesses224. Operations at block106may include formation of at least one gate spacer222over the sidewalls of the dummy gate stack214before the source/drain regions210SD are recessed. In some embodiments, the formation of the at least one gate spacer222includes deposition of one or more dielectric layers over the workpiece200. In an example process, the one or more dielectric layers are conformally deposited using CVD. SACVD, or ALD. The one or more dielectric layers may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and/or combinations thereof. After the deposition of the at least one gate spacer222, an anisotropic etch process is performed to the workpiece200to form the source/drain recesses224. The etch process at block106may be a dry etch process or other suitable etch process. An example dry etch process may implement an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF4, SF6, NF3, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBr3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. As shown inFIG.4, sidewalls of the sacrificial layers206and the channel layers208in the channel regions210C are exposed in the source/drain recesses224.

Referring toFIGS.2and5, method100includes a block108where inner spacer features226are formed. At block108, the sacrificial layers206exposed in the source/drain recesses224are selectively and partially recessed to form inner spacer recesses, while the exposed channel layers208are substantially unetched. The middle sacrificial layer206M, due to its greater germanium content, may be substantially removed during the formation of inner spacer recesses. In some embodiments, the selective recess may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent at which the sacrificial layers206are recessed is controlled by duration of the etching process. The selective dry etching process may include use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include use of hydrogen fluoride (HF) or ammonium hydroxide (NH4OH).

After the formation of the inner spacer recesses, an inner spacer material layer is deposited over the workpiece200, including in the inner spacer recesses. Additionally, as shown inFIG.5, the inner spacer material layer may also be deposited in the space left behind by selective removal of the middle sacrificial layer206M. The inner spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excess portions of the inner spacer material layer over the dummy gate stack214, the gate spacer222, and sidewalls of the channel layers208, thereby forming the inner spacer features226and the middle dielectric layer226M as shown inFIG.5. In the present embodiments, the inner spacer features226includes inner spacer features226aand226bdisposed over the middle dielectric layer226M and inner spacer features226c.226d, and226edisposed under the middle dielectric layer226M. Each of the inner spacer features226a-226cand the middle dielectric layer226M is disposed between two vertically adjacent channel layers208. For example, the inner spacer feature226bis disposed between the channel layer208U2and the channel layer208U3, and the inner spacer feature226cis disposed between the channel layer208L1and the channel layer208L2. In some embodiments, the etch back process at block108may be a dry etch process that includes use of an oxygen-containing gas, hydrogen, nitrogen, a fluorine-containing gas (e.g., NF3, CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBr3), an iodine-containing gas (e.g., CF3I), other suitable gases and/or plasmas, and/or combinations thereof.

Still referring toFIGS.2and5, method100includes a block110where bottom source/drain features230are formed in the source/drain recesses224. In some embodiments, before the deposition of the bottom source/drain features230, a blocking layer (not shown) may be deposited over the workpiece200to cover sidewalls of the top portion204T of the superlattice structure204. The blocking layer may also cover sidewalls of the middle dielectric layer226M and the channel layer208L1. The blocking layer may include dielectric materials. After the formation of the blocking layer, the bottom source/drain features230may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the composition of the substrate202as well as the channel layers208not covered by the blocking layer. In the present embodiments, the epitaxial growth of bottom source/drain features230may take place from both the top surface of the substrate202and the exposed sidewalls of the bottom channel layers208L2and208L3. The blocking layer, due to its dielectric composition, blocks formation of the bottom source/drain features230on sidewalls of the channel layers208U1-208U3and208L1. As illustrated inFIG.5, the bottom source/drain features230are in physical contact with (or adjoining) the channel layers208L2and208L3. Depending on the design, the bottom source/drain features230may be n-type or p-type. In the depicted embodiments, the bottom source/drain features230are p-type source/drain features and may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable material and may be in-situ doped during the epitaxial process by introducing a p-type dopant, such as boron or gallium, or ex-situ doped using a junction implant process.

Referring toFIGS.2and6, method100includes a block114where the bottom CESL232and the bottom ILD layer234are etched back. As shown inFIG.6, the bottom CESL232and the bottom ILD layer234are etched back to exposed sidewalls of the channel layers208U1and208U2. In embodiments presented byFIG.6, after being etched back, the bottom CESL232is in direct contact with the inner spacer features226b-226c, the channel layers208U3,208L1, and the middle dielectric layer226M. The blocking layer may be removed during the etch back of the bottom CESL232and the bottom ILD layer234.

Referring toFIGS.2and7, method100includes a block116where an insulating layer236is deposited over the workpiece200by performing a deposition process238. The insulating layer236may include silicon nitride or any other suitable materials. In an embodiment, the insulating layer236includes silicon nitride. As depicted inFIG.7, the insulating layer236has a non-uniform deposition thickness over the workpiece200. Specifically, the insulating layer236includes a bottom portion236adeposited on and in direct contact with a top surface of the bottom CESL232and the bottom ILD layer234, a side portion236bextending along sidewalls of the gate spacers222and sidewalls of the channel layers (e.g., the channel layers208U1and208U2) and inner spacer features (e.g., the inner spacer features226aand226b) exposed in the source/drain recesses224, and a top portion236cformed on the top surfaces of the dummy gate stacks214and gate spacers222. The bottom portion236ahas a thickness T1along the Z direction, the side portion236bhas a thickness T2along the Y direction, and the top portion236chas a thickness T3along the Z direction. In the present embodiments, the thickness T1is greater than the thickness T2. Providing this thickness relationship would facilitate the formation of a satisfactory insulating layer in the final structure of the semiconductor device200. In the present embodiments, the thickness T3is also greater than the thickness T2. The thickness T1may be greater than or equal to the thickness T3.

In the present embodiments, the deposition process238includes a plasma-enhanced atomic layer deposition process (PEALD) and may be also referred to as PEALD238. In PEALD238, the deposition is achieved by using alternating cycles of precursor gas and plasma exposure. Exemplary steps of one cycle of the PEALD238includes, after loading the workpiece200into a chamber of the tool performing the PEALD238, flowing a precursor gas into the chamber. The precursor gas molecules adsorb onto the surface of the workpiece200, forming a self-limiting monolayer. After the precursor gas exposure, a purge process is performed to purge the precursor gas and any by-products from the chamber. A plasma treatment process that involves flowing a gas into the chamber with charged ions is then performed. During the plasma treatment process, an electromagnetic field, a radiofrequency (RF), or other suitable energy source is applied to direct the ions toward the workpiece200. The plasma breaks down the precursor molecules and initiates chemical reactions on the surface of the workpiece200, leading to film growth. The plasma species react with the precursor monolayer on the workpiece200, resulting in the formation of a thin film. The ionized gas may be removed from the chamber before the next layer deposition cycle is performed.

Parameters of the PEALD238are adjusted to form the insulating layer236having the non-uniform deposition thickness. In the present embodiments, during the plasma treatment process, the energy source (e.g., electromagnetic field, a radiofrequency (RF)) is adjusted such that surfaces of the workpiece200that face up will receive more ions than sidewalls of the workpiece200during the PEALD238. That is, the bottom surface of the source/drain recesses224receives more plasma than the sidewall surface of the source/drain recesses224. As a result, the bottom portion236aof the insulating layer236has the thickness T1that is greater than the thickness T2of the side portion of the insulating layer236. In the present embodiments, since plasma dosage received by the bottom surface of the source/drain recesses224is greater than the plasma dosage received by the sidewall surface of the source/drain recesses224, chemical reaction happened at the bottom surface of the source/drain recesses224may be a full reaction, and the chemical reaction happened at the sidewall surface of the source/drain recesses224may be a half reaction. As a result, the film quality of the bottom portion236aof the insulating layer236is better than the film quality of the side portion236bof the insulating layer236. For example, composition and/or density of the bottom portion236aof the insulating layer236are different than composition and/or density of the side portion236bof the insulating layer236, and different composition(s) and/or density provide an etch selectivity between the side portion236band the bottom portion236aof the insulating layer236. In some embodiments, the top portion236chas similar composition and density as the bottom portion236a, and the thickness T3is substantially equal to the thickness T1and is greater than the thickness T2.

For embodiments in which the insulating layer236includes silicon nitride, the precursor gas may include dichlorosilane (DCS, SiH2Cl2), diiodosilane (DIS, SiH2I2), or other suitable materials; and the gas implemented in the plasma treatment may include nitrogen (N2), ammonia (NH3), or a combination thereof. In some embodiments, the gas implemented in the plasma treatment may further include argon (Ar). In the present embodiments, a ratio of nitrogen concentration to silicon concentration (i.e., N/Si) of the insulating layer236is in a range between about 1.7 and about 1.9. That is, N/Si of the insulating layer236is greater than the N/Si of the bottom CESL232. In some embodiments, about 300 cycles to 400 cycles may be performed to achieve the desired deposition thickness (e.g., T1, T2, and T3). The plasma power of provided by the energy source is in a range between about 20 W and about 100 W. If the plasma power is less than 20 W, then the gas may not be satisfactorily ionized to form plasma. If the plasma power is greater than 100 W, then the side portion236bof the insulating layer may have good quality, and the etch selectivity between the side portion236band the bottom portion236amay be not high enough to ensure the side portion236bto be selectively removed by a subsequent etching process. In an embodiment, the deposition temperature (e.g., between about 400° C. and about 500° C.) of the PEALD238is lower than the deposition temperature (e.g., between about 500° C. and about 700° C.) of the formation of the bottom source/drain features230to reduce dopant diffusions and thus substantially keep the dopant concentration of the bottom source/drain features230.

Referring toFIGS.2and8, method100includes a block118where a mask layer240is formed in the source/drain recesses224to cover the bottom portion236aand a lower part of the side portion236bof the insulating layer236. In some embodiments, the mask layer240is deposited over the workpiece200and is patterned to cover the bottom portion236aof the insulating layer236while the top portion236cis exposed. In one embodiment, the mask layer240is a bottom antireflective coating (BARC) layer that may include polysulfones, polyureas, polyurea sulfones, polyacrylates, poly(vinyl pyridine), or a silicon-containing polymer.

Referring toFIGS.2and9, method100includes a block120where a first etching process242is performed to remove portions of the insulating layer236not covered by the mask layer240. After forming the mask layer240, the first etching process242is performed to selectively etch back the insulating layer236without substantially etching the dummy gate stacks214, the gate spacers222, and the channel layers208. In the embodiments, the first etching process242selectively removes the top portion236cand an upper part of the side portion236bof the insulating layer236. The first etching process242may be an isotropic dry etching and may include hydrogen fluoride (HF), ammonia (NH3), or a combination thereof. Other suitable etchants may also be implemented by the first etching process242. The side portion236bof the insulating layer236after the performing of the first etching process242may be referred to as side portion236b′. Referring toFIGS.2and10, after the performing of the first etching process242, the mask layer240is selectively removed without substantially etching the dummy gate stacks214, the gate spacers222, the channel layers208, and the insulating layer236.

Referring toFIGS.2and11, method100includes a block122where a second etching process244is performed to etch back the insulating layer236. In some embodiments, the second etching process244is an isotropic wet etching process. The etchant of the second etching process244may include diluted hydrogen fluoride (HF). In some embodiments, the etchant of the second etching process244and the etchant of the first etching process242may include the same composition in different states (e.g., hydrogen fluoride solution and hydrogen fluoride gas). The extent at which the insulating layer236is recessed is controlled by duration of the second etching process244. In an embodiment, the performing of the second etching process244is stopped when the side portion236b′ of the insulating layer236is fully removed. As described above with reference toFIG.7, the quality of the bottom portion236aof the insulating layer236is better than the quality of the side portion236b′ of the insulating layer. In the present embodiments, the etchant(s) of the second etching process244etches the side portion236b′ at a rate greater than it etches the bottom portion236a. The bottom portion236aafter the performing of the second etching process244is referred to as the insulating layer236a′. The insulating layer236a′ has a thickness T4. Due to the etch rate difference, a difference between the thickness T1(shown inFIG.7) and the thickness T4(i.e., T1-T4) is less than the thickness T2of the side portion236b′ of the insulating layer236. That is, the extent at which the bottom portion236aof the insulating layer236is recessed is less than that of the side portion236b. In the present embodiments, as depicted inFIG.11, an entirety of the sidewall surface of the insulating layer236a′ is in direct contact with the inner spacer feature226b. In some embodiments, the thickness T4is in a range between about 1 nm and about 20 nm to provide enough isolation between the top source/drain features248and bottom source/drain features230without substantially increasing the fabrication cost.

Referring toFIGS.2and12, method100includes a block124where a third etching process246is performed to the workpiece200. In the embodiments, the third etching process246is performed to selectively remove native oxide layer (e.g., silicon oxide) or other by-products formed on the sidewall surfaces of the channel layers (e.g., the channel layers208U1and208U2), on the sidewall surfaces of the inner spacer features (e.g., the inner spacer features226aand226b), and/or on the top surface of the insulating layer236a′ exposed by the source/drain recesses224without substantially etching the insulating layer236a′ to get the workpiece200ready for subsequent epitaxial growth process. The third etching process246may also be referred to as a pre-clean process246. In some embodiments, the pre-clean process246may include NF3, NH3, H2, or other suitable etchants. In an embodiments, the pre-clean process246includes a mixture of NF3, NH3, and H2.

Referring toFIGS.2and13, method100includes a block126where top source/drain features248are formed over the insulating layer236a′. The top source/drain features248may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with composition of the channel layers (e.g., channel layers208U1and208U2) of the top portion204T of the superlattice structure204. The epitaxial growth of top source/drain features248may take place from the exposed sidewalls of the top channel layers208U1and208U2. The deposited top source/drain features248are in physical contact with (or adjoining) the channel layers of the top portion204T of the superlattice structure204. Depending on the design, the top source/drain features248may be n-type or p-type. In the depicted embodiments, the top source/drain features248are n-type source/drain features and may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable material and may be in-situ doped during the epitaxial process by introducing an n-type dopant, such as phosphorus, arsenic, or antimony, or ex-situ doped using a junction implant process.

Still referring toFIGS.2and13, method100includes a block128where a top CESL250and a top ILD layer252are deposited over the top source/drain features248. The top CESL250may include silicon nitride, silicon oxynitride, and/or other materials known in the art and may be formed by CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the top CESL250is first conformally deposited on the workpiece200and the top ILD layer252is then deposited over the top CESL250by spin-on coating. FCVD, CVD, or other suitable deposition technique. The top ILD layer252may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In some embodiments, after formation of the top ILD layer252, the workpiece200may be annealed to improve integrity of the top ILD layer252. To remove excess materials and to expose top surfaces of the dummy gate stacks214, a planarization process, such a chemical mechanical polishing (CMP) process may be performed.

Referring toFIGS.2and14, method100includes a block130where the dummy gate stack214is replaced with a gate structure254. Operations at block130may include removal of the dummy gate stacks214, release of the channel layers208as channel members (including top channel members2080U1,2080U2, and bottom channel members2080L1, and2080L2) and nanostructures (including the nanostructures2080N1and2080N2) and formation of gate structures254to wrap around the channel members2080. The removal of the dummy gate stacks214may include one or more etching processes that are selective to the material in the dummy gate stacks214. For example, the removal of the dummy gate stacks214may be performed using as a selective wet etch, a selective dry etch, or a combination thereof. After the removal of the dummy gate stacks214, sidewalls of the channel layers208and sacrificial layers206in the channel regions210C are exposed. Thereafter, the sacrificial layers206in the channel regions210C are selectively removed to release the channel layers208as the channel members (including the top channel members2080U1,2080U2, the bottom channel members2080L1, and2080L2) and nanostructures (including the nanostructures2080N1and2080N2). The selective removal of the sacrificial layers206may be implemented by a selective dry etch, a selective wet etch, or other selective etch processes. In some embodiments, the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In some other embodiments, the selective removal includes SiGe oxidation followed by a silicon germanium oxide removal. For example, the oxidation may be provided by ozone clean and then silicon germanium oxide removed by an etchant such as NH4OH.

In embodiments represented byFIG.14, the top channel members2080U1and2080U2are in direct contact with the top source/drain features248; the bottom channel members2080L1and2080L2are in direct contact with the bottom source/drain features230; and the nanostructures2080N1,2080N2and the middle dielectric layer226M are in direct contact with the bottom CESL232.

After the selective removal of the sacrificial layers206, the gate structure254is deposited to wrap around each of the top channel members2080U1and2080U2and bottom channel members2080L1and2080L2, thereby forming a bottom multi-gate transistor (e.g.,10L inFIG.1) and a top multi-gate transistor (e.g.,10U inFIG.1) disposed over the bottom multi-gate transistor. In the depicted embodiments, both the bottom multi-gate transistor and the top multi-gate transistor are MBC transistors. In some embodiments, the gate structure254may be a common gate structure to engage the bottom channel members and the top channel members. In some other embodiments depicted in the drawings, the gate structure254includes a bottom gate portion254B to engage bottom channel members2080L1and2080L2and a top gate portion254T to engage the top channel members2080U1and2080U2. The bottom gate portion254B and the top gate portion254T have different work function layers. When the gate structure254includes a bottom gate portion254B and a top gate portion254T, the two gate portions may be electrically isolated from each other by the middle dielectric layer226M. For example, the bottom gate portion254B may include n-type work function layers and the top gate portion254T may include p-type work function layers. While not explicitly shown in the figures, the gate structure254includes an interfacial layer to interface the channel members. The gate structure254also includes a gate dielectric layer254dover the interfacial layer, a work function layer254c/254f(e.g., a p-type work function layer or an n-type work function layer). The gate dielectric layer254dis deposited over the workpiece200using ALD, CVD, and/or other suitable methods. The gate dielectric layer254dis formed of high-K dielectric materials. As used and described herein, high-k dielectric materials include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The gate dielectric layer254dmay include hafnium oxide. Alternatively, the gate dielectric layer254dmay include other high-K dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3(STO), BaTIO3(BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3(BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable material.

After the deposition of the gate dielectric layer254d, n-type work function layer254cand the p-type work function layer254fmay be formed over the channel regions210C. The p-type work function layer254fand the n-type work function layer254cmay include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer). By way of example, the p-type work function layer254fmay include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicide (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), nickel silicide (NiSi2), other p-type work function material, or combinations thereof. The n-type work function layer254cmay include titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicide nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), other n-type work function material, or combinations thereof. The gate structure254may also include a metal fill to reduce contact resistance. In some instance, the metal fill includes tungsten (W). The gate structure254may also include a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. In the depicted embodiment, the top gate portion254T also includes a dielectric capping layer254cformed over the n-type work function layer254c.

Referring toFIGS.2and15, method100includes a block132where further processes are performed to complete the fabrication of the semiconductor device200. Such further processes may include forming a silicide layer256over the top source/drain features248and forming a multi-layer interconnect (MLI) structure258over the workpiece200. The MLI258may include various interconnect features, such as vias258vand conductive lines258m, disposed in dielectric layers258d, such as etch-stop layers and ILD layers. In some embodiments, the vias are vertical interconnect features configured to interconnect device-level contacts, such as source/drain contacts260formed over the top source/drain features248. Other processes may be further performed.

In the above embodiments represented byFIG.15, an entirety of the sidewall surface of the insulating layer236a′ is in direct contact with the inner spacer feature226b. In an alternative embodiment represented byFIG.16, the sidewall surface of the insulating layer236a′ is in direct contact with both the inner spacer feature226band the nanostructure2080N1. In another alternative embodiment represented byFIG.17, the sidewall surface of the insulating layer236a′ is in direct contact with the inner spacer feature226b, the nanostructure2080N1, and the middle dielectric layer226M.

In the above embodiments represented byFIGS.15-17, the semiconductor device200includes the bottom CESL232and the bottom ILD layer234, and the bottom surface of the insulating layer236a′ is in direct contact with both the bottom CESL232and the bottom ILD layer234. In an alternative embodiment represented byFIG.18which is a cross-sectional view of the semiconductor device200, there is no bottom ILD layer234formed on the bottom CESL232, and an entirety of the bottom surface of the insulating layer236a′ is in direct contact with the bottom CESL232. In this alternative embodiment, depending on the total thickness of the bottom CESL232and the insulating layer236a′, an entirety of the sidewall surface of the insulating layer236a′ may be in direct contact with the inner spacer feature226b, may be in direct contact with both the inner spacer feature226band the nanostructure2080N1, may be in direct contact with the inner spacer feature226b, the nanostructure2080N1, or may be in direct contact with the inner spacer feature226b, the nanostructure2080N1, the middle dielectric layer226M, and the nanostructure2080N2.FIG.19depicts a fragmentary cross-sectional view of the workpiece200taken along line C-C shown inFIG.18. As depicted inFIG.19, the top source/drain feature248is isolated from the bottom source/drain feature230by a combination of the bottom CESL232and the insulating layer236a′. The workpiece200also includes a fin sidewall spacer222′ disposed adjacent to the bottom source/drain feature230. The fin sidewall spacer222′ may be formed along with the gate spacers222. Some features are omitted in this figure for reason of simplicity.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, the present disclosure provides an insulating layer disposed between two vertically adjacent source/drain features to prevent electrical short therebetween, thereby improving the overall reliability of the semiconductor device.

The present disclosure provides for many different embodiments. Semiconductor structures and methods of fabrication thereof are disclosed herein. In one exemplary aspect, the present disclosure is directed to a method. The method includes receiving a workpiece including a fin-shaped structure comprising a channel region and a source/drain region adjacent the channel region, wherein the fin-shaped structure comprises a first semiconductor stack over a substrate and a second semiconductor stack over the first semiconductor stack, and a gate stack over the channel region. The method also includes recessing the source/drain region to form a source/drain trench, forming a first source/drain feature in the source/drain trench and coupled to the first semiconductor stack, depositing a first contact etch stop layer (CESL) and a first interlayer dielectric (ILD) layer over the first source/drain feature, depositing an insulating layer over the workpiece, the insulating layer comprising a horizontal portion on the first ILD layer and a vertical portion extending along a sidewall surface of the second semiconductor stack, wherein a thickness of the horizontal portion is greater than a thickness of the vertical portion, removing the vertical portion of the insulating layer, forming a second source/drain feature on the horizontal portion of the insulating layer, and depositing a second CESL and a second ILD layer over the second source/drain feature.

In some embodiments, the depositing of the insulating layer may include performing a plasma-enhanced atomic layer deposition process (PEALD). In some embodiments, the insulating layer may include silicon nitride, the first CESL may include silicon nitride, and a ratio of nitrogen concentration to silicon concentration of the insulating layer may be different than a ratio of nitrogen concentration to silicon concentration of the first CESL. In some embodiments, the ratio of nitrogen concentration to silicon concentration of the insulating layer may be in a range between about 1.7 and about 1.9. In some embodiments, the depositing of the insulating layer over the workpiece further forms a top portion directly over the gate stack, and a thickness of the top portion may be greater than the thickness of the vertical portion. In some embodiments, the removing of the vertical portion of the insulating layer may include forming a mask layer to cover the horizontal portion of the insulating layer and a lower part of the vertical portion of the insulating layer, performing a first etching process to selectively remove portions of the insulating layer not covered by the mask layer, after the performing of the first etching process, selectively remove the mask layer, and performing a second etching process to remove the lower part of the vertical portion of the insulating layer. In some embodiments, the performing of the second etching process further etches the horizontal portion of the insulating layer, and etchant of the second etching process etches the horizontal portion of the insulating layer at a first rate and etches the lower part of the vertical portion of the insulating layer at a second rate, the second rate is greater than the first rate. In some embodiments, the first semiconductor stack may include a first plurality of channel layers interleaved by a first plurality of sacrificial layers, and the second semiconductor stack may include a second plurality of channel layers interleaved by a second plurality of sacrificial layers, and the method may also include, after the recessing of the source/drain region to form the source/drain trench, performing a third etching process to selectively recess the first plurality of sacrificial layers and the second plurality of sacrificial layers to form a first plurality of inner spacer recesses and a second plurality of inner spacer recesses, respectively, forming a first plurality of inner spacer features in the first plurality of inner spacer recesses and a second plurality of inner spacer features in the second plurality of inner spacer recesses, after depositing the second CESL and the second ILD layer, selectively removing the gate stack, selectively removing the first plurality of sacrificial layers and the second plurality of sacrificial layers, and forming a gate structure over the workpiece. In some embodiments, the fin-shaped structure further may include a silicon germanium layer disposed between the first semiconductor stack and the second semiconductor stack, and the performing of the third etching process further removes the silicon germanium layer to form a space, wherein the forming the first plurality of inner spacer features and the second plurality of inner spacer features further forms a dielectric layer in the space. In some embodiments, the horizontal portion of the insulating layer is in direct contact with a bottommost inner spacer feature of the second plurality of inner spacer features. In some embodiments, the method may also include, after the removing the vertical portion of the insulating layer and before the forming of the second source/drain feature over the horizontal portion of the insulating layer, performing an etching process to pre-clean the workpiece, wherein the etching process does not substantially etch the horizontal portion of the insulating layer.

In another exemplary aspect, the present disclosure is directed to a method. The method includes depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over a bottom epitaxial source/drain feature, wherein the bottom epitaxial source/drain feature is formed in a bottom portion of a source/drain trench, etching back the CESL and the ILD layer to expose a top portion of the source/drain trench, performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, wherein the insulating layer may include a non-uniform deposition thickness and may include a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench, removing the second portion of the insulating layer, and forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the top portion of the source/drain trench.

In some embodiments, during the PEALD, a bottom surface of the top portion of the source/drain trench receives a first plasma dosage, and the sidewall surface of the top portion of the source/drain trench receives a second plasma dosage less than the first plasma dosage. In some embodiments, film quality of the first portion of the insulating layer may be better than film quality of the second portion of the insulating layer. In some embodiments, the removing of the second portion of the insulating layer may include forming a mask layer to cover the first portion of the insulating layer and a lower part of the second portion of the insulating layer, performing a first etching process to selectively remove an upper part of the second portion of the insulating layer, selectively remove the mask layer, and performing a second etching process to etch back the insulating layer to remove the lower part of the second portion of the insulating layer. In some embodiments, etchant of the second etching process may etch the lower part of the second portion of the insulating layer faster than it etches the first portion of the insulating layer. In some embodiments, composition of the insulating layer may be different than composition of the CESL and composition of the ILD layer.

In yet another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, a lower source/drain feature disposed over the substrate, a first plurality of nanostructures coupled to the lower source/drain feature, a first gate structure wrapping around each of the first plurality of nanostructures, a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over the lower source/drain feature, an insulating layer over and in contact with the CESL and the ILD layer, wherein a ratio of nitrogen concentration to silicon concentration of the insulating layer is greater than a ratio of nitrogen concentration to silicon concentration of the CESL, an upper source/drain feature over the insulating layer, a second plurality of nanostructures coupled to the upper source/drain feature, and a second gate structure wrapping around each of the second plurality of nanostructures.

In some embodiments, the first gate structure and the second gate structure may be vertically spaced apart from one another by a dielectric layer. In some embodiments, a sidewall of the dielectric layer may be in contact with the insulating layer.