System and method for using current slew-rate telemetry in an information handling system

An information handling system includes a current detector module and a baseboard management controller (BMC). The current detector module is configured to detect current slew-rate for an element of the information handling system, to determine that the current slew-rate is greater than a current slew-rate threshold, and to provide an indication that the current slew-rate is greater than the current slew-rate threshold on a communication interface. The BMC may enter an item into a log of the information handling system in response to receiving an indication.

FIELD OF THE DISCLOSURE

This disclosure generally relates to information handling systems, and more particularly relates to a system and method for using current slew-rate telemetry in an information handling system.

BACKGROUND

SUMMARY

An information handling system may include a current detector module and a baseboard management controller (BMC). The current detector module may be configured to detect current slew-rate for an element of the information handling system, to determine that the current slew-rate is greater than a current slew-rate threshold, and to provide an indication that the current slew-rate is greater than the current slew-rate threshold on a communication interface. The BMC may be coupled to the communication interface. The BMC may enter an item into a log of the information handling system in response to receiving the indication.

DETAILED DESCRIPTION OF DRAWINGS

FIG. 1illustrates a power control system100for an information handling system. Power control system100includes one or more PSU102, a current monitor combiner106, a system current monitor splitter108, one or more CPU VR114, a complex programmable logic device (CPLD)118, an Inter-Integrated Circuit (I2C) interface multiplexor (I2C MUX)120, a baseboard management controller (BMC)122, one or more CPU128, one or more PCIe adapter130, another system current monitor splitter132, one or more Non-Volatile Memory Express (NVMe) interface134, and a current slew-rate detector module140. It will be understood that power control system100is representative of the various monitoring, management, and control aspects of an overall power system for an information handling system, and thatFIG. 1is not intended to show the actual power distribution network of the subject information handling system. A simplified power supply system is shown inFIG. 2, as described further, below.

PSU102represents a switching power converter device that receives input power (typically an alternating current (AC) power line input) and provides one or more output voltage rails (typically direct current power rails). PSU102is configurable to operate in various operating modes, such as a standby mode, a normal power mode, and a constant current mode. Further, based upon various platform power states enacted on the information handling system, one or more of the voltage rails may be powered on while other power rails are powered off. As such, PSU102includes an I2C interface that is connected via I2C MUX120to BMC122and that permits the communication of various status and configuration information to the BMC and the receipt of various control information from the BMC, as described further below. In addition, PSU102provides various hardware status signals to power control system100. Such hardware status signals may include various bi-state signals, such as an over-current warning (OCW), as provided by an OCW module104, a power-ok signal (POK), a constant current (CC) signal, an input voltage status (Vin_Good) signal, a System Management Bus (SMB) alert (SMB_ALERT) signal, or other bi-state status signals, as needed or desired. The hardware status signals may also include various analog signals such as a PSU current level (PSU_IMON) signal, or other analog signals, as needed or desired. The SMB_ALERT signal is provided to CPLD118in response to an over-current warning provided by OCW module104, as described further below.

In a particular embodiment, the PSU_IMON signal is a voltage level signal, such as where PSU102provides a current sense resistor in a main power source, and where the PSU_IMON signal is representative of the voltage across the sense resistor. In another embodiment, the PSU_IMON signal is a current level signal, such as where PSU102provides a current follower circuit whose output current is based upon the current of the main power source. In either embodiment, current monitor combiner106operates to receive the PSU current level (PSU_IMON signal from PSU102and other PSU current level signals from the one or more additional PSUs of power control system100, and to combine the PSU current level signals to provide a system current level (Sys_IMON) signal. For example, where the PSU_IMON signals are voltage level signals, the Sys_IMON signal can be provided as an output of a voltage adder circuit such that the Sys_IMON voltage is proportional to the sum of the PSU_IMON voltages. In another example, where the PSU_IMON signals are current level signals, the Sys_IMON signal can be provided as an output of a current adder circuit such that the Sys_IMON current is proportional to the sum of the PSU_IMON currents. It will be understood that where a particular PSU is dedicated to providing power for a particular portion of an information handling system, such as a sub-system of the information handling system, that a current monitor combiner similar to current monitor combiner106may be utilized to provide a current level signal for the portion or sub-system of the information handling system, as needed or desired. Note that the Sys_IMON signal is indicative of a total amount of current being provided by PSU102and the one or more additional PSUs, and should not be confused with a total current being provided to a load of the information handling system.

In a typical information handling system, the Sys_IMON signal is received by CPU VR114as a current proportional signal, and the CPU VR conditions the power provided to CPU126based upon the Sys_IMON signal. For example, CPU VR114can determine that PSU102is providing less than a fully rated power level to the information handling system, and in response, the CPU VR can increase one or more of an operating frequency and a voltage level to CPU126to increase the performance of the CPU, thereby utilizing more of the power capacity of PSU102. In another example, CPU VR114can determine that PSU102is providing at or near the fully rated power level to the information handling system, and in response, the CPU VR can decrease one or more of the operating frequency and the voltage level to CPU126to decrease the performance of the CPU, thereby reducing the power utilization of PSU102. In a typical case, the Sys_IMON signal can be utilized to optimize the power consumption of the memory devices. For example, CPU126may throttle the memory devices or other subsystems of information handling system in response to the Sys_IMON signal, or BMC122can perform the throttling in response to the Sys_IMON signal. As such, the Sys_IMON signal is utilized in power control system100to prospectively inform CPU VR114of power conditions on the information handling system, such that the CPU VR can proactively respond to the power conditions to better utilize PSU102. CPU VR114provides information as to the status and operation of the CPU VR (CPU_Inf) to CPU126, such that the CPU can condition the processing operations of the CPU upon the information, as needed or desired. CPU VR114further includes an I2C interface that is connected via I2C MUX120to BMC122and that permits the communication of various status and configuration information to the BMC and the receipt of various control information from the BMC, as described further below. In addition, CPU VR114provides an over-current alert (ALERT #), as provided by an OCW module116to CPLD118, as described further below.

In the present embodiment, power control system100provides the Sys_IMON signal to PCIe adapter130, to NVMe interface134, and to other elements of the information handling system, so that the PAU, the PCIe adapter, the NVMe interface and the other elements of the information handling system may prospectively be informed of the power conditions on the information handling system, and can proactively respond to the power conditions to better utilize PSU102. However, because the Sys_IMON signal is a current proportional signal, the Sys_IMON signal cannot be fanned out to PCIe adapter130, to NVMe interface134, and to other elements of the information handling system directly. Instead, the Sys_IMON signal from current monitor combiner106is provided to system current monitor splitter108to generate multiple copies of the Sys-IMON signal. In particular, system current monitor splitter108provides individual copies of the Sys_IMON signal to CPU VR114, and to system current monitor splitter132. Further, system current monitor splitter132provides individual copies of the Sys_IMON signal to PCIe adapter130and to NVMe interface134. For example system current monitor splitters108and132can utilize current mirror circuits that generate one or more mirrored current signal outputs based upon a received current signal input. CPU VR114is typically provided in conjunction with or by a manufacturer of CPU126. As such, the requirements associated with the Sys_IMON signal are typically defined by a specification for CPU VRs that may be published by the manufacturer of the CPU. For example, the Sys_IMON signal may be analogous to various system level power signals as specified in various specifications published by one or more microprocessor manufacturer. Here, each device of power control system100that receives Sys_IMON will be understood to be in compliance with the particular CPU VR specification.

CPLD118represents a programmable device that provides various logic functions for the information handling system that utilizes power control system100. In particular, CPLD118includes multiple general purpose I/O (GPIOs) and is programmed to provide various relations between the signals received on the GPIOs and the signals provided on the GPIOs. As such, CPLD118is configured to receive the SMB_ALERT signal from PSU102, and the ALERT #signal from CPU VR118. CPLD118is further configured to provide a processor over-temperature signal (PROCHOT #) to CPU126and power brake (BRAKE) signals to PCIe adapter130(B30), and NVMe interface134(UI), as described further below.

PCIe adapter130represents one or more PCIe root ports and endpoint devices of the information handling system that includes power control system100. In a particular embodiment, the Sys_IMON signal is received by PCIe adapter130as a current proportional signal as split by Sys_IMON splitter132. In another embodiment, where PCIe adapter130is configured to receive a voltage proportional signal, the Sys_IMON signal is converted into the voltage proportional signal, such as by including a to convert the current proportional signal to the voltage proportional signal. In either case, PCI adapter130conditions its power profile based upon the Sys_IMON signal. For example, PCIe adapter130can determine that PSU102is providing less than a fully rated power level to the information handling system, and in response, the PCIe adapter can increase its performance, thereby utilizing more of the power capacity of PSU102. In another example, PCIe adapter130can determine that PSU102is providing at or near the fully rated power level to the information handling system, and in response, the PCIe adapter can decrease its performance, thereby reducing the power utilization of PSU102. PCIe adapter130further includes an I2C interface that is connected via I2C MUX120to BMC122and that permits the communication of various status and configuration information to the BMC and the receipt of various control information from the BMC, as described further below. It will be understood that PCIe adapter130may represent two or more PCIe adapters that each receive a separate Sys_IMON signal from Sys_IMON splitter132, as needed or desired.

NVMe interface134represents one or more non-volatile memory controller of the information handling system that includes power control system100. In a particular embodiment, the Sys_IMON signal is received by NVMe interface134as a current proportional signal as split by Sys_IMON splitter132. In another embodiment, where NVMe interface134is configured to receive a voltage proportional signal, the Sys_IMON signal is converted into the voltage proportional signal, such as by including a to convert the current proportional signal to the voltage proportional signal. In either case, NVMe interface134can determine that PSU102is providing less than a fully rated power level to the information handling system, and in response, the NVkle interface can increase its performance, thereby utilizing more of the power capacity of PSU102. In another example, NVMe interface134can determine that PSU102is providing at or near the fully rated power level to the information handling system, and in response, the NVMe interface can decrease its performance, thereby reducing the power utilization of PSU102. NVMe interface130further includes an I2C interface that is connected via I2C MUX120to BMC122and that permits the communication of various status and configuration information to the BMC and the receipt of various control information from the BMC, as described further below. It will be understood that NVMe interface134may represent two or more NVMe interfaces that each receive a separate Sys_IMON signal from Sys_IMON splitter132, as needed or desired. It will be further understood that the I2C interface of NVMe interface may share a common I2C bus with the I2C interface of PCIe adapter130. Further, it will be understood that power management system100may include one or more additional subsystem, such as a network interface device (NIC), a storage adapter, or another subsystem of an information handling system that may receive the Sys_IMON signal and adapt the performance of the subsystem accordingly, as needed or desired.

I2C MUX120operates to multiplex I2C busses from PSU104, CPU VR114, CPU126, PCIe adapters130, and NVMe interface134to an I2C interface of BMC122. Here, BMC122operates to monitor, manage, and maintain the operations of PSU104, CPU VR114, CPU126, PCIe adapters130, and NVMe interface134via communications over the various I2C busses. In particular, BMC122may include a processor that runs management code to perform the functions of the BMC, and may further include a co-processor that, under the direction of the management code, offloads the BMC processor from various repetitive tasks, such as I2C service routines. It will be understood that the configuration of the I2C busses and I2C MUX120are exemplary, and that the information handling system that utilizes power control system100may employ an I2C bus configuration that is different than the one shown herein. Moreover, it will be understood that the communications between BMC122and PSU104, CPU VR114, CPU126, PCIe adapters130, and NVMe interface134may be via other communication standards, as needed or desired. For example, the communication between BMC122and CPU126may be channeled via an I2C bus to a Platform Controller Hub (PCII) that is in communication with the CPU, or the BMC may communicate directly with the CPU via a Platform Environment Control Interface (PECI), as needed or desired.

Current slew-rate detector module140represents a high-speed analog-to-digital converter (ADC) that receives as an input the current provided at a particular location on the information handling system that utilizes power control system100. Current slew-rate detector module140operates to detect the rate of rise (slew-rate) in the current supplied at the particular location. Current slew-rate detector module140includes a I2C interface and operates to communicate indications related to the current slew-rate at the particular location to BMC122. It will be understood that power control system100may include more than one current slew-rate detector module similar to current slew-rate detection module140, each to receive as an input the current provided at a different location on the information handling system and to detect the current slew-rate in the current supplied at the different locations. For example, power control system100can include current slew-rate detector modules that are associated with the overall system current for each particular voltage rail from PSU102, current slew-rate detector modules that are associated with particular subsystems of the information handling system, such as memory subsystems, I/0subsystems, or the like, current slew-rate detector modules that are associated with one or more CPU VR or VR controller, or the like, as needed or desired.

In particular, current slew-rate detector module140can receive one or more of the IMON signals from power control system100. For example, current slew-rate detector module140can be integrated into CPU VR114, and the features of the current slew-rate detector module as described herein can be based upon the Sys_IMON signal. Here, CPU VR114can determine a power or current delta between multiple samples of the received Sys_IMON signal over a given time period to calculate the system-level slew-rate. Then, if CPU VR114detects a slew-rate that is above one or more preprogrammed thresholds, the CPU VR can trigger various warnings or actions as described herein. In another example, other endpoint devices or subsystems of the information handling system can support associated IMON outputs, or IMON devices could be placed on the voltage feeds to various subsystems to be provided to current slew-rate detector module140to provide the features of the current slew-rate detector module as described herein.

Current slew-rate detector module140operates to detect the current slew-rate supplied at its associated location, and to provide indications as to the current slew-rate to BMC122via the I2C interface. In a particular embodiment, current slew-rate detector140implements one or more current slew-rate thresholds. Here, current slew-rate detector module140provides indications when the one or more current slew-rate thresholds are exceeded. In a particular case, current slew-rate detector module140is pre-configured with the one or more current slew-rate thresholds, based upon the current being monitored. In another case, current slew-rate detector module140operates to receive the one or more current slew-rate thresholds from BMC122. In this case, power control system100can implement each current slew-rate module as a common device that is added to the power control system as needed or desired, and each added current slew-rate monitor module is then programmed by BMC122for its associated location. It will be understood that a current slew-rate monitor module may be implemented as a discrete element, or may be integrated into other elements of the information handling system as needed or desired. The input current signal to current slew-rate detector module140may be provided by any suitable current detection means, as is known in the art, such as by utilizing a loop current detector, a resistor-based current detector, or the like. Further details of current detection, being known in the art, will not be disclosed herein except as needed to illustrate the present embodiments. Note that, as used with respect to a current slew-rate detection module, the term “location” is used to mean a node or trace of a power rail from which the input current is sensed, or to otherwise situate the node or trace of the power rail within a power layout on a printed circuit board (PCB), at a connector, at a connection, such as a surface mount connection or the like, as needed or desired.

In operation, power control system100provides three mechanisms for controlling the flow of power to the loads of the information handling system that includes the power control system: a hardware protection mechanism as shown by the dashed signal lines, a fast firmware control loop as shown by the dotted signal lines, and a slow firmware control loop as shown by the solid signal lines. The hardware control mechanism is the fastest control mechanism and is primarily controlled by CPLD118. Further, the hardware control mechanism provides a coarsest response, such as by applying a maximum throttling to the operations of the information handling system, and thus degrades performance more that the fast or slow firmware control loops. Here, CPLD118receives the SMB_ALERT signal from PSU102and the ALERT #signal from CPU VR114. These signals each provide an indication that the respective sending element is in a critical load condition. For PSU102and CPU VR116, the critical load conditions represent the fact that the PSU or the CPU VR are at a maximum loading and can supply no further current to their respective loads, leading to a potential voltage drop on one or more of their power rails. When CPLD118receives one or more of the critical load condition signals, the CPLD provides the PROCHOT #signal to CPU126. In response, CPU126takes actions to lower the power consumption of the CPU, such as by lowering a performance state of the CPU by lowering one or more of an operating frequency or an operating voltage of the CPU, or shutting down internal units of the CPU, as needed or desired. CPLD118further responds to one or more of the critical load condition signals by providing the BRAKE signal to PCIe adapter130and NVMe interface134. In response, PCIe adapter130and NVMe interface134take actions to lower their power consumption. The particular steps taken by a CPU, a PCIe adapter or device, or a NVMe interface to lower their respective power consumption are known in the art and are beyond the scope of the present disclosure, and will be described no further herein except as needed to further describe the present embodiments. Note that other hardware power control signals may be provided in a typical information handling system and that may make up other functions of the hardware protection mechanism. For example, a particular architecture may include a MEMHOT #or EVENT #signal for memory components. Other hardware based power control signals may be provided on other architectures, and such signals will be understood to be included in a hardware protection mechanism, as needed or desired. Further, the distinction between the hardware protection mechanism and the fast and slow firmware control loops is not intended to be exclusive. For example, a CPLD may further operate in response to a critical load condition to provide an interrupt to a BMC, and the BMC may then apply specific firmware-based controls in response.

The fast firmware control loop consists of the PSU_IMON signal and the distributed Sys_IMON signals. Here, CPU VR114, PCIe adapter130, and NVMe interface134respond to variations in the system current level, as indicated by the Sys_MON signal, as described above. The slow firmware control loop consists primarily of the I2C interfaces, through which BMC122operates to monitor, manage, and maintain PSU102, CPU VR114, CPU126, PCIe adapter130, and NVMe interface134. The slow firmware control loop provides different regulation schemes in different platform load states, such as during emergency power-down conditions, or other load conditions or system operating states as needed or desired.

It has been observed by the inventors of the present disclosure that increasing power requirements in information handling systems, and particularly in dense processing environments such as a data center, are leading to current spikes that exceed the ability of present power supply solutions to maintain voltage levels within specified ranges. That is, if a current demand in the load of an information handling system has a slew-rate that exceeds the current slew-rate of the PSU powering the information handling system, the voltage level supplied by the PSU may drop to an unacceptably low level, thereby causing an under-voltage fault in the PSU. For example, a typical PSU may have a current slew-rate limit of 2 Amps per second (A/s) on its output, and so any current demand in the load on the information handling system that draws current with a slew-rate of greater than 2 A/s may cause an under-voltage fault on the PSU. This problem is particularly exacerbated when the information handling system includes various third-party components, such as general purpose graphics processing units (GPGPUs), field-programmable gate array (FPGA) devices, and the like, that may not be designed in conformance with various industry standards in terms of power demand and the like. Such current spike problems have been correlated by the inventors of the present disclosure with high current slew-rates on the power supply lines for the various subsystems of the information handling system.

In a particular embodiment, current slew-rate detector module140operates to detect the current slew-rate at the location of the information handling system, and to provide alerts to the BMC122via the I2C interface when the current slew-rate exceed a particular slew-rate threshold. In particular, current slew-rate detector module140includes signal processing circuits that operate to detect and characterize the current slew-rate. Then, when the current slew-rate exceeds a one or more slew-rate threshold, current slew-rate detector module140operate to provide indications to BMC122via the I2C interface. Here, current slew-rate detector module140may implement multiple current slew-rate thresholds, as needed or desired. Here, when the current slew-rate exceeds a first threshold, current slew-rate detector module140will provide a warning indication that the current slew-rate is increasing, but is not at an alert level. When the current slew-rate exceeds a second threshold, current slew-rate detector module140will provide a warning indication that the current slew-rate has increased beyond the warning level to the alert level. Finally, when the current slew-rate exceeds a third threshold, current slew-rate detector module140will provide a critical indication that the current slew-rate is above the critical level.

When BMC122receives an indication that the current slew-rate has exceeded one or more current slew-rate threshold, the BMC operates to trigger various responses on power control system100and on the associated information handling system. In a particular embodiment, BMC122operates to receive indications from current slew-rate detector module140, such as warning indications, alert indications, and critical indications, and to log the indication in a system event log managed by the BMC. Here, the system event log can be maintained by a hosted environment of the information handling system, by the BMC in a non-volatile memory associated with the BMC, in an event manager of a management system for a data center that includes the information handling system, or in a combination thereof.

Further, BMC122operates to correlate indications of high current slew-rate with other power management functions of the information handling system and of power control system100. For example, BMC122can operate to receive a warning indication from PSU102, and can operate to mask other power quality indications, such as hardware indications from PSU102indicating an input power fault. Here, a typical operation of power control system100may include receiving an input power fault indication from PSU102or detecting the assertion of the SMB_ALERT signal from the PSU. Here, BMC122may operate to communicate to PSU102via the I2C interface to withhold the assertion of the SMB_ALERT signal while the current slew-rate is less than a particular indication level, such as the warning level, or the BMC may provide an input to CPLD118that operates to mask the SMB_ALERT to the CPLD until either an indication from current slew-rate detector module140of a higher level current slew-rate issue is received by the BMC, or an indication from the current slew-rate detector module that the current slew-rate issue has subsided. In this way, BMC122operates to filter out hardware faults that would tend to unnecessarily exercise the throttling functions of power control system100, permitting the power control system to tide through minor current slew-rate issues. Additionally, BMC122operates to provide indications to a user of the information handling system that current slew-rate issues may be responsible for throttling events or other impacts to system performance.

As noted above, power control system100may include two or more PSUs similar to PSU102. Here, in a typical operating mode, one or more PSU is active while one or more PSU is held as a hot-spare. Here, when the active PSU suffers a fault, the hot-spare can quickly be brought on line to maintain good power for the information handling system. In a particular embodiment, when BMC122receives an indication from current slew-rate detector module140of a current slew-rate issue, the BMC brings up one or more of the hot-spare PSUs in order to ensure that the current slew-rate issue does not affect the performance of the information handling system. Here, the presence of two or more active PSUs may permit the overall power supply to more readily supply current to handle the current slew-rate. For example, where a pair of PSUs each have a current slew-rate limit of 2 A/s, with one PSU operating as a hot spare PSU, a current slew-rate on the load that is greater than 2 A/s can be handled by bringing the hot spare PSU on line, such that the combined slew-rate limit of both PSUs would then be 4 A/s, thereby handling the current slew-rate of the load without triggering an under-voltage condition. When BMC122brings up one or more of the hot-spare PSUs, the BMC further provides an indication that the hot-spare PSUs have been activated, and that the hot-spare PSUs are not otherwise available in case of failure of a PSU. The indication may be provided to one or more of the hosted environment of the information handling system, to a log maintained by BMC122, and to a management system of a data center that includes the information handling system.

In a particular embodiment, the information handling system includes various persistent memory architectures. Here, when BMC122receives an indication of a high current slew-rate, the BMC operates to trigger a persistent memory SAVE operation to direct the persistent memory to store the contents of volatile memory elements to their associated non-volatile memory elements in anticipation of a complete loss of power on the information handling system. Here, while the high current slew-rate may otherwise be insufficient to trigger a persistent memory SAVE operation, for example, because the current slew-rate issue is not sufficiently poor to cause PSU102to withdraw a POWER_OK signal or a Vin_GOOD signal, the current slew-rate may be sufficiently bad to cause the charge on the bulk capacitor of the PSU to be reduced to a level that is insufficient to sustain the voltage on the power rails for a long enough duration to perform the persistent memory SAVE operation. For example, where a persistent memory architecture includes 3D Xpoint memory, a power supply may be expected to provide sufficient voltage on the power rails for up to 2 milliseconds (ms) after the loss of the POWER_OK or Vin_GOOD signals. In another example, where a persistent memory architecture includes N-type non-volatile DIMMs (NV-DIMM-Ns), a power supply may be expected to provide sufficient voltage for 3 ms before the loss of the POWER_OK signal to permit the a backup power supply or battery to provide an output voltage, and so the information handling system may typically rely on the deassertion of the Vin_GOOD signal to trigger the backup power supply or battery to come on line. Here, BMC122substitutes an indication that the current slew-rate is high and that a bulk capacitor charge on PSU102is lower than a persistent memory SAVE operation level, and triggers the backup power supply or battery to come on line without the deassertion of the Vin_GOOD signal. In a particular case, where a PSU subsystem is assessed as being in a redundant state, that is, with at least one hot spare PSU, the detection of a current slew-rate that is higher than a single PSU's slew-rate limit would serve to indicate that the PSU subsystem is in fact operating in the non-redundant state. Here, when the PSU subsystem is operating in the redundant state, a SAVE operation is typically not triggered until both PSUs have indicated a fault. However, having detected that the PSU subsystem is in fact operating in the non-redundant state, the SAVE operation would be triggered as soon as a single PSU indicates a fault, as the remaining PSU would also be unable to handle the slew-rate alone.

In another embodiment, the information handling system implements a throttling policy for various power conditions detected on power control system100. Here, when BMC122receives an indication of a high current slew-rate, the BMC operates to trigger the throttling policy in order to reduce the load on drawn by the information handling system in order to permit the bulk capacitor of PSU102adequate opportunity to recharge to handle a full load on the information handling system.

FIG. 2illustrates a method of using power line input telemetry in an information handling system, starting at block200. A current slew-rate detector module detects the current slew-rate at a location of an information handling system in block202. For example, a current slew-rate detector module may be associated with an overall system current for each particular voltage rail from a PSU of an information handling system, may be associated with a particular subsystem of the information handling system, such as a memory subsystem, an I/O subsystem, the like, or may be associated with one or more CPU VR or VR controller of the information handling system, or may be associated with the current at another location of the information handling system. A decision is made as to whether or not the current slew-rate exceeds a current slew-rate threshold in decision block204. For example, the detected current slew-rate can exceed a first current slew-rate threshold, indicating that the current slew-rate is at an alert level, the detected current slew-rate can exceed a second current slew-rate threshold, indicating that the current slew-rate is at a warning level, or the detected current slew-rate can exceed a third current slew-rate threshold, indicating that the current slew-rate is at a critical level.

If the detected current slew-rate does not exceed a current slew-rate threshold, the “NO” branch of decision block204is taken, and the method returns to block202, where the current slew-rate detector module detects the current slew-rate at the location of the information handling system. If the detected current slew-rate exceeds a current slew-rate threshold, the “YES” branch of decision block204is taken, and the current slew-rate detector module sends an indication to a BMC of the information handling system in block206. For example, when the detected current slew-rate exceeds the first current slew-rate threshold, the power monitor module sends a current slew-rate alert indication that the detected current slew-rate is at the alert level, when the detected current slew-rate exceeds the second current slew-rate threshold, the power monitor module sends a current slew-rate warning indication that the detected current slew-rate is at the warning level, or when the detected current slew-rate exceeds the third current slew-rate threshold, the power monitor module sends a current slew-rate critical indication that the detected current slew-rate is at the critical level. The method then proceeds to block208, where the BMC mitigates the current slew-rate issue for the information handling system. For example, the BMC may write to a log maintained by the host environment of the information handling system, to a log maintained by the BMC, or to a log maintained by a management system of a datacenter that includes the information handling system, the BMC may throttle one or more component of the information handling system, the BMC initiate a persistent memory save operation, or the BMC may take other actions as described above. The method ends in block210.

The utilization of a current slew-rate detector module, as described above, permits the quick detection of high current slew-rates and rapid response to minimize the load that the PSU subsystem must handle. In a particular embodiment, a throttling response is masked until PSU redundancy is lost. For example, where there are two PSUs, and a single PSU cannot handle the current slew-rate of the load, then an information handling system can induce throttling only if there was a fault that reduced the number of active PSUs from two to one. Such functionality could be provided by hardware logic in, for example, a CPLD that qualifies a slew-rate based throttle request signal with the number of active PSUs (POK).

Information handling system300can include devices or modules that embody one or more of the devices or modules described above, and operates to perform one or more of the methods described above. Information handling system300includes a processors302and304, a chipset310, a memory320, a graphics interface330, include a basic input and output system/extensible firmware interface (BIOS/EFI) module340, a disk controller350, a disk emulator360, an input/output (I/O) interface370, and a network interface380. Processor302is connected to chipset310via processor interface306, and processor304is connected to the chipset via processor interface308. Memory320is connected to chipset310via a memory bus322. Graphics interface330is connected to chipset310via a graphics interface332, and provides a video display output336to a video display334. In a particular embodiment, information handling system300includes separate memories that are dedicated to each of processors302and304via separate memory interfaces. An example of memory320includes random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.

BIOS/EFI module340, disk controller350, and I/O interface370are connected to chipset310via an I/O channel312. An example of I/O channel312includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. Chipset310can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/IFI module340includes BIOS/EFI code operable to detect resources within information handling system300, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/EFI module340includes code that operates to detect resources within information handling system300, to provide drivers for the resources, to initialize the resources, and to access the resources.

Disk controller350includes a disk interface352that connects the disc controller to a hard disk drive (HDD)354, to an optical disk drive (ODD)356, and to disk emulator360. An example of disk interface352includes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulator360permits a solid-state drive364to be connected to information handling system300via an external interface362. An example of external interface362includes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drive364can be disposed within information handling system300.

I/O interface370includes a peripheral interface372that connects the I/O interface to an add-on resource374, to a TPM376, and to network interface380. Peripheral interface372can be the same type of interface as I/O channel312, or can be a different type of interface. As such, I/O interface370extends the capacity of I/O channel312when peripheral interface372and the I/O channel are of the same type, and the I/O interface translates information from a format suitable to the I/O channel to a format suitable to the peripheral channel372when they are of a different type. Add-on resource374can include a data storage system, an additional graphics interface, a network interface card (NIC), a sound/video processing card, another add-on resource, or a combination thereof. Add-on resource374can be on a main circuit board, on separate circuit board or add-in card disposed within information handling system300, a device that is external to the information handling system, or a combination thereof.

Network interface380represents a NIC disposed within information handling system300, on a main circuit board of the information handling system, integrated onto another component such as chipset310, in another suitable location, or a combination thereof. Network interface device380includes network channels382and384that provide interfaces to devices that are external to information handling system300. In a particular embodiment, network channels382and384are of a different type than peripheral channel372and network interface380translates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channels382and384includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channels382and384can be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.