Disposable pillars for contact formation

Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.

RELATED APPLICATIONS

This application is related to pending U.S. patent application Ser. No. 10/690,317, filed Oct. 20, 2003, entitled FORMATION OF SELF-ALIGNED CONTACT PLUGS, the entirety of which is hereby incorporated by reference and made part of this specification.

BACKGROUND OF THE INVENTIONS

1. Field of the Inventions

The disclosed inventions relate generally to integrated circuit fabrication, techniques for fabrication of computer memory, and contact formation therefor.

2. Description of the Related Art

As a consequence of many factors, including demands for increased portability, computing power, memory capacity, and energy efficiency in modern electronics, integrated circuits are continuously being reduced in size. To facilitate these size reductions, the sizes of the constituent features, such as electrical devices and interconnect line widths, that form the integrated circuits, are also constantly being decreased.

The trend of decreasing feature size is most evident in memory circuits or devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, etc. To take one example, DRAM typically comprises millions of identical circuit elements, known as memory cells.

By decreasing the sizes of constituent electrical devices and the conducting lines that access them, the sizes of the memory devices incorporating these features can be decreased. Storage capacities for a given chip area can thus be increased by fitting more memory cells onto memory devices without increasing the overall size of the devices.

The continual reduction in feature size places ever greater demands on the techniques used to form the features. One well-known technique is photolithography, commonly used to pattern features, such as conductive lines, on a substrate. The concept of pitch can be used to describe the size of these features. For the repeating patterns typical of memory arrays, pitch is defined as the distance between an identical point in two neighboring features. Adjacent features are typically separated by a material, such as an insulator. As a result, pitch can be viewed as the sum of the width of the feature and of the width of the space or material separating that feature from a neighboring feature. Due to optical factors, such as lens limitations and light or radiation wavelength, photolithographic techniques have minimum pitches below which a particular photolithographic technique cannot reliably form features. This minimum pitch is commonly referred to by a variable defining one half of the minimum pitch, or feature size F. This variable is often referred to as a “resolution.” The minimum pitch definable by photolithography, 2F, places a theoretical limit on feature size reduction.

One method for improving the density possible using conventional photolithographic techniques is to change the layout of a memory device in order to fit more memory cells in the same area without changing the pitch. Using such a method, the size of the memory device can be reduced without exceeding the minimum pitch, 2F, dictated by optical limitations. Alternatively, the memory device may be configured to hold more memory cells, while maintaining a constant pitch.

Memory layout changes, particularly those accompanied by increased feature density, and other factors have contributed to the need for improved subcomponent configurations and methods for forming subcomponents that are adapted to the memory layout changes.

SUMMARY OF THE INVENTIONS

Some embodiments comprise a method of forming an integrated circuit having multiple levels. The method can comprise the following steps: providing active areas; providing a plurality of word lines above the active areas; coating the word lines with a sacrificial material; patterning the sacrificial material in a first pattern having continuous lines and removing intervening portions of the sacrificial material that are not part of the first pattern; coating the patterned sacrificial material with an insulating material; planarizing the insulating material down to a first plane to expose portions of the sacrificial material; removing the exposed portions of the sacrificial material to leave voids; depositing a conductive material into the voids; and planarizing the conductive material to leave isolated plugs within the voids.

Some embodiments comprise an integrated circuit that includes a plurality of conductive plugs for use in an integrated circuit. The conductive plugs can comprise blocks of conductive material with a nonrectangular, parallelogram footprint, flanked on first and second opposite sides by two word lines and flanked on second and third opposite sides by blocks of insulating material, the blocks of conductive material being configured to contact underlying active areas and provide an electrical connection with an overlying bit line. The blocks of conductive material in the integrated circuit can be associated with a plan view pattern, the pattern comprising the following portions: first columns, each first column comprising a word line; second columns alternating regularly with the first columns, each second column comprising the box of conductive material, which alternate up and down the column with blocks of insulating material, the second columns arranged in ascending and descending trios. The ascending trios can comprise three sequential second columns having blocks of conductive material with parallelogram footprints, each parallelogram footprint having a top edge parallel to a bottom edge wherein the top and bottom edges of parallelogram slope upwardly to the right, and each top edge is aligned with the top edge of two other blocks of conductive material in other second columns in the ascending trios. The descending trios can comprise three sequential second columns having blocks of conductive material with parallelogram footprints, each parallelogram footprint having a top edge parallel to a bottom edge, wherein the top and bottom edges of the parallelogram slope downwardly to the right, and each top edge is aligned with the top edge of two other blocks of conductive material in other second columns in the descending trios.

Some embodiments comprise a memory device having a first component grouping. As seen in plan view, the first component grouping can comprise: a first elongate active area defining a first axis, the first active area comprising a first source and at least first and second drains; at least two substantially parallel word lines that cross and overly the first active area, at least a portion of a first word line located between the first drain and to the first source, at least a portion of a second word line located between the second drain and the first source; and a first plurality of contact plugs on the same vertical level as the word lines, the contact plugs comprising rhomboid portions of conductive material the first plurality of contact plugs contacting and generally overlying the first active area, at least one of the first plurality of contact plugs extending between the at least two word lines and at least one of the first plurality of contact plugs extending outwardly from either word line, each of the first plurality of contact plugs being aligned with the first axis.

Some embodiments comprise a method of forming conductive plugs for a computer memory array. The methods can comprise patterning a sacrificial material in continuous lines that cross word lines. The method can further comprise filling spaces between the sacrificial material and word lines with insulating material. The method can further comprise removing the sacrificial material to form plug voids, the plug voids being separated by word lines in one dimension and separated by the insulating material in another dimension. The method can further comprise filling the plug voids with conductive material to form conductive plugs. Some embodiments comprise a method of manufacturing a portion of the memory device. The method can include providing a substrate and a defining an elongate active area within the substrate, the axis of elongation of the active area defining a first axis. The method can further comprise defining at least one pair of word lines that define a second axis, the second axis crossing the first axis at an angle in a range of approximately 20 to approximately 80 degrees. Moreover, the method can comprise filling a space between the word lines and over the active area with a sacrificial material. The method can also comprise removing the sacrificial material and replacing it with a conductive material to form a conductive contact, the conductive material having two sides that are parallel to the first axis and two sides that are parallel to the second axis.

Some embodiments comprise a method of forming conductive plugs between transistor gates. The method can comprise patterning a sacrificial material in continuous zig-zag (in plan view) lines. The zig-zag lines having thinner (in cross-section) bridge portions that cross the transistor gates and thicker fill portions that fill the space between the gates. The method can further comprise removing at least the thicker fill portions to form voids with sidewalls formed from insulating material. The method, moreover, can comprise filling the voids with conductive material to form conductive plugs.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIG. 1A, active areas32are schematically illustrated, forming a pattern in an active area level30. In the illustrated embodiment, a pair of memory cells comprises three electrical devices: two storage capacitors and an access field effect transistor having a single source shared by the memory cells, two gates, two channels, and two drains. The pair of memory cells, therefore, has two addressable locations that can each store one bit (binary digit) of data. A bit can be written to one of the cells' locations through the transistor and read by sensing charge on the drain electrode from the source electrode site. In some embodiments, rows36of oval-shaped active areas32form a zig-zag pattern. From left to right across a row36, the right-hand tip of each active area in a zig-zag row is near the left-hand tip of the subsequent active area in the zig-zag row. In the illustrated embodiment, the elongate axes of each of the oval active areas32in a particular row36are not aligned, but instead differ by an angle φ. Some embodiments have a symmetrical zig-zag pattern in that each successive intersection of elongate axes in a particular row36differs by the same angle φ. The angle φ can be in a range of approximately 45 degrees to approximately 179 degrees, for example. Preferably, the angle φ is approximately 130 degrees.

In some embodiments, columns38of oval-shaped active areas32do not have a zig-zag pattern. Thus, the elongate axes of each of the oval active areas32in a particular column38can be parallel, as shown. Thus, the repeating pattern of active areas can have a successive rows36of zig-zag lines that form a hound's tooth or herringbone pattern. The zig-zag configuration can have two slopes that intersect at an angle in a range of between 45 and 179 degrees, for example.

The active areas32are formed in a semiconductor material such as silicon. The active areas32are doped regions of a semiconductor substrate as shown in various cross-sectional views (see, e.g.,FIG. 2B). The active areas32can be portions of a conductively doped silicon wafer that forms a substrate for an integrated circuit. The raised active areas32are surrounded in the same vertical level by insulating material or field isolation regions34, which can be field oxide or shallow trench isolation material, for example.

In some embodiments, the active areas32comprise different regions that have different properties from one another. For example, the different regions can have different conductive properties. In the illustrated embodiments, each active area comprises a source region, as well as two channel regions and two drain regions. For an illustration of where these regions can be located within the active area32, seeFIG. 13. The silicon in the various regions of the active area can be doped differently. For example, in some preferred embodiments, the silicon in the source and drain regions has been heavily doped (e.g., n+), whereas the silicon in the channel regions has been less heavily doped with opposite conductivity type (e.g., p−).FIG. 13shows how the source and drain regions can be oriented in the active area32with respect to other structures in an integrated circuit.

Referring toFIG. 1B, word lines42are schematically illustrated as stripes that cross the active areas32in an overlying word line level. The word lines42overlie the active areas32, and each active area32contacts two word lines42. In particular, the word lines42preferably contact the active area32in the channel regions of the active areas32(seeFIG. 13). As can be understood from the cross-sectional views discussed below, the word lines42define insulated transistor gate electrodes where they cross the active areas32. Thus, the active areas32can create an electrical connection between two insulated transistor gate electrodes, or word lines42. The word lines42are separated by spaces44, and the word lines42comprise multiple layers and/or portions that are illustrated inFIG. 2B.

As shown inFIG. 1B, the overlying bit lines52can be configured to cross over the central regions of the active areas32. The central regions of the active areas32can correspond to the source regions of the active areas32. The source regions can connect with the overlying bit lines52through bit line contacts62. In the illustrated embodiment, spaces54between bit lines52cross over the peripheral regions of the active areas32, which can correspond to the drain regions of the active areas32. Cell contacts64connect the drain regions to memory storage devices (not shown), such as capacitors. As used in this specification, the term “bit line” also encompasses the structure sometimes referred to as a “digit line.”

Referring toFIG. 2A, a sacrificial material220has been deposited over the word lines42and the active areas32, which are both shown in phantom. The sacrificial material220fills the spaces44between word lines42, and thus portions of the sacrificial material220occupy the same vertical level as a word line level. In preferred embodiments, the sacrificial material220is photoresist or conformal amorphous carbon. These materials are advantageous because they can be removed with high selectivity, as discussed further below. The sacrificial material220preferably coats the word lines42, and it is shown as a planarized layer inFIG. 2B. However, the layer220need not be smooth or planarized because a later CMP step will be used.

Referring toFIG. 2B, the sacrificial material220, word lines42, active areas32, and insulating material or field isolation regions34are shown in cross section. The word lines42comprise multiple layered portions, including a gate dielectric portion230, a first conductive portion240, a second conductive portion250, and an insulating cap portion260. The gate dielectric portion230can extend across the whole active area at this stage. As illustrated, the word lines42are insulated from surrounding materials both by the insulating cap portions260and by word line spacers280. The gate dielectric portions230can be formed from silicon oxide or high k materials such as Ta2O5, HfO2or ZrO2. The first conductive portions can 240 can be formed from poly silicon, metal silicide, or newer materials and metal compounds with tailored work functions. The second conductive portions250can be formed from metal silicide, elemental metals and metal compounds with higher conductivity. The insulating cap portions260and the word line spacers280can be formed from silicon nitride, silicon oxide or similar dielectrics. As shown inFIG. 2B, the active areas32can be raised plateau portions of an underlying semiconductor substrate210. The active areas32can have substantially vertical walls236that define the boundary between the active areas32and the insulating material or field isolation regions34. Alternatively, the walls236can be sloped as shown.

Referring toFIG. 2C, a cross section taken along lines2C-2C shows a different perspective of the layered configuration of the partly-formed integrated circuit.

Referring toFIG. 3A, the sacrificial material220has been patterned in a continuous wavy line or zig-zag pattern such that portions of the sacrificial material220are intact over each row36(FIG. 1A) of active areas32. The lines of sacrificial material220generally follow the contours of successive oval-shaped active areas32(shown in phantom), extending the length of one active area32, bridging to cover another active area32, bridging to cover yet another active area32, and so forth from left to right in the illustrated view. As illustrated, the lines of sacrificial material220cross over portions of the word lines42as well as the spaces44(FIG. 1B) between word lines.

The pattern of continuous zig-zag lines of sacrificial material can effectively overlie the various active areas32, having similar angles and intersecting elongate axes in a way similar to the above description of the rows36of active areas32(seeFIG. 1). In particular, each zig-zag row of sacrificial material can overlie a row36of active areas32.

Because the elongate axes of a particular column38(seeFIG. 1A) of oval active areas32are aligned or parallel, successive zig-zag rows36of active areas can form a hound's tooth pattern as discussed above with respect toFIG. 1A. Furthermore, the zig-zag rows of patterned sacrificial material generally overlie the rows36of active areas32. Thus, the zig-zag lines of patterned sacrificial material do not overlap with each other and have zig-zag lines of space in between them. The illustrated embodiment has a constant separation distance between each zig-zag line. In some embodiments, the continuous wavy lines intersect the word lines42at an angle between 10 and 80 degrees. For example, inFIG. 3A, one of the wavy zig-zag lines intersects one of the word lines42at an angle α. In some embodiments, the angle α is the same as an angle β. Such a symmetrical configuration can make it easier to pattern large arrays of structures such as those described herein. In some embodiments, the angle φ is twice the angle α.

Patterning the sacrificial material220in a continuous line can provide higher resolution than would otherwise be possible with a more disjointed pattern having discreet elements (not shown). The sacrificial material220can be patterned through a photolithographic process. For example, if the sacrificial material220is photoresist, conventional photolithography can be used. In some embodiments, where the sacrificial material220is amorphous carbon, for example, a dry develop etch process can be used to pattern the sacrificial material220. In particular, a dry develop process can involve dry-developing the resist and removing material that is not protected by the resist, then stripping the resist pattern to leave behind lines of amorphous carbon over the active areas.

With continued reference toFIG. 3A, after the zig-zag pattern of sacrificial material220has been formed and portions of the sacrificial material coating have been removed as shown, there are voids330in the spaces44(FIG. 1B) between word lines42, and the voids330are flanked above and below (in plan view) by the thicker portions320of the lines of sacrificial material220. (The lines of sacrificial material also have thinner portions340, where the lines cross over the word lines42). Thus, the sacrificial material220has been patterned in a pattern having continuous lines, and the portions of intervening sacrificial material that are not part of the pattern have been removed.

Referring toFIG. 3B, which shows a cross section of the structure illustrated inFIG. 3A, the lines of sacrificial material220have thicker portions320in between the word lines42and thinner portions340as the sacrificial material220crosses over the top of the word lines42. Furthermore,FIG. 3Billustrates the wordline spacers280that provide insulating material between the inner portions of the wordlines42and the materials external to the wordlines42. In particular, the wordline spacers280flank the left and right sides (in plan view) of the voids330. Thus, the voids330are surrounded by four insulating side walls, two formed from the thicker portions320and two formed from the wordline spacers280.

Referring toFIG. 3C, the illustrated cross section is taken along one of the word lines42, and thus shows two thinner portions340of sacrificial material220.

Referring toFIG. 4A, a coating of insulating material420has been applied to the structure ofFIGS. 3A-3C. The insulating material420has filled in the voids330(FIG. 3A). The insulating material420is deep enough, in the depicted embodiment, to cover all the structure ofFIGS. 3A-3C. The insulating material420can be a spin-on dielectric (SOD). The insulating material420can be densified at this point, or later as indicated below.

Referring to the cross-sectional views ofFIGS. 4B and 4C, the insulating material420is shown covering the sacrificial material220.

Referring toFIG. 5A, both the sacrificial material220and the insulating material420have been planarized (if not already planar) and etched back. In the illustrated embodiment, both materials have been removed generally down to a plane that corresponds to the top of the word lines42. The remaining portions of the sacrificial material220form pillars520. The pillars520are defined and surrounded by the word lines42to the left and right (inFIG. 5A), and by insulating material420to the top and bottom (inFIG. 5A). The pillars520have parallelogram “footprints.” Preferably, the pillars520have rhomboidal footprints. As used herein, a footprint refers to an object's shape when it is seen from a top or bottom plan view, for example when a cross-section of the object is taken along a plane parallel to the plan of the plan view ofFIG. 5A, for example. In the illustrated embodiment, the pillars520have parallelogram, rhomboid footprints as seen in the plan view, each parallelogram having an interior angle α′ that corresponds to the angle α. The angle α′ is an interior angle of the rhomboid represented by the footprint of the pillar520. The angles α′ and α are preferably in a range between 10 and 80 degrees. Thus, in the illustrated embodiment ofFIG. 5A, the parallelograms are non-rectangular. In particular, the illustrated parallelograms are rhomboids.

Referring toFIG. 5B-5D, planarization has removed the thinner portions340(FIG. 3B) of the sacrificial material220, but left the pillars520(corresponding to the thicker portions320ofFIG. 3B) that are located in between the word lines42generally intact. The pillars520generally overlie portions of the active areas32, as illustrated byFIG. 5D. Planarization can be accomplished using an etch step with a mechanical component, such a chemical mechanical polishing (CMP) etch. Other processes that can be used to planarize include selective dry etch back processes. In a preferred embodiment, CMP is used and when the CMP reaches the level of the insulating cap portions260of the word lines42, the CMP is halted. Because the insulating cap portions260can be formed from nitride, CMP can be referred to as a “stop-on nitride” (or SON) process. Alternatively, the described CMP etch can be referred to as a SON CMP etch.

Referring toFIG. 6A, the sacrificial material220that remained after planarization has been removed, leaving plug voids620in between word lines42. In the spaces44(FIG. 1B), remaining portions of insulating material420form periodic blocks of material that alternate with the plug voids620. The plug voids620leave portions of the active areas32exposed. The plug voids620can have the same shape and angle characteristics of the removed pillars520(FIGS. 5A-5D) of sacrificial material. For example, in the illustrated embodiment, the plug voids620have parallelogram footprints as seen in the plan view, each parallelogram having an interior angle α′ that corresponds to the angle α. The angle α′ is an interior angle of the parallelogram represented by the footprint of the void620. The angles α′ and α are preferably in a range between approximately 10 and approximately 80 degrees. Thus, in the illustrated embodiment ofFIG. 6A, the parallelograms are non-rectangular. In particular, the parallelograms are preferably rhomboids.

The sacrificial material220can be removed by a selective etch step. For example, if the sacrificial material220is photoresist, an oxygen plasma etch can be used. If the sacrificial material220is amorphous carbon, a similar or sulfur/oxygen plasma can be used. If the remaining insulating material has not already been densified, it can be densified after the sacrificial material220has been removed as illustrated.

Referring toFIG. 6B, in the illustrated cross section, the free-standing word lines42alternate with plug voids620. The back wall of the insulating material420is omitted to more clearly illustrate the voids1020.

Referring toFIG. 6C, the cross-section taken along the word line42is unchanged from the structure shown inFIG. 5C.

Referring toFIG. 7A, the structure ofFIG. 6Ahas been coated with a conductive material720, which has filled the plug voids620left by removal of the sacrificial material220. The conductive material720can be silicon, polysilicon, metal, tungsten, titanium, or a laminated conductor, for example. In some embodiments, polysilicon is preferred because it can withstand processing temperatures. In the illustrated embodiment, the conductive material720forms the plugs that fill the plug voids620.

Referring toFIGS. 7B and 7C, cross-sectional views of the conductive material720overlying the structure ofFIGS. 6B and 6Care shown. Referring toFIG. 7D, a cross sectional view taken along the line7D-7D ofFIG. 7Ais shown.

Referring toFIG. 8A, the conductive material720has been planarized such that all material above a plane generally corresponding to the top of the word lines42has been removed. Etch back processes or CMP, as described above with respect toFIGS. 5A-5D, can also be used to achieve the structure illustrated inFIGS. 8A-8D. The planarization has created plugs820from the conductive material720. The conductive plugs820can fill the role of bit line contacts (see bit line contacts62inFIG. 1Babove) or cell contacts (see cell contacts64inFIG. 1Babove), depending on their position with respect to an underlying active area32. The conductive plugs820form conductive contacts with the underlying active areas32by passing down between the word lines42. By removing the sacrificial material220to form the voids620(FIGS. 6A-6B), the plugs820can be formed by coating the structure and planarizing, as shown. Furthermore, the conductive plugs820are self-aligned in that the voids allow the conductive material720to fill in to form plugs820that are directly aligned with the underlying active areas32and do not require a mask step after depositing the conductive material. As described above with respect to the pillars520of sacrificial material220and the voids620, in the illustrated embodiment, the plugs820can have parallelogram (e.g., rhomboid) footprints as seen in the plan view, each parallelogram having an interior angle α′ that corresponds to the angle α. The angle α′ is an interior angle of the parallelogram represented by the footprint of the pillar520. The angles α′ and α are preferably in a range between 10 and 80 degrees. In particular, the parallelograms are preferably rhomboids.

As seen in the plan view ofFIG. 8A, the illustrated plugs820have a non-rectangular parallelogram footprint. In the illustrated embodiment, the opposing top and bottom sides of each plug820are either ascending from right to left, as with the plugs820overlying the central active area32inFIG. 8A, or they are descending from right to left, as is the case with some of the plugs820which are only partially visible inFIG. 8A. For example, if the word lines42form columns (in plan view) as illustrated inFIG. 8A, the lines42alternate with columns830formed from the plugs820and blocks of insulating material with complementary shapes, the two parallelogram (or rhomboid) blocks alternating in a striped pattern in the columns830up and down (in the view ofFIG. 8A) between word lines42. As illustrated, the angles of the stripes in the columns formed between word lines42corresponds to the angle of the elongate axis of the underlying active areas32. In particular, three striped columns830and two word lines42cross each active area32. The striped columns830are grouped in ascending trios where they cross active areas32that slope upwardly to the right, and in descending trios where they cross active areas32that slope downwardly to the right.

Referring toFIGS. 8B-8D, the cross sectional views show how the plane of planarization corresponds to the top of the word lines42. The illustrated planarization can be achieved using an etch step with a mechanical components, such as chemical mechanical polishing. Other processes that can be used to planarize include a selective dry etch or a non-selective dry etch timed to stop after reaching the top of the word lines42or otherwise configured (e.g., with optical end point detection) to end after exposure of the insulating caps260. As illustrated byFIG. 8D, the plugs820generally overlie the active areas32. The two plugs820illustrated inFIG. 8Dcan function as cell contacts because they overlie the end regions of the active areas32. InFIG. 8D, the side wall of the wordline42that would otherwise be visible in such a cross-sectional view has been omitted to more clearly illustrate the lack of structure between the plugs820along the column830(FIG. 8A).

FIGS. 9-12show an alternative embodiment to that described inFIGS. 5-8. Indeed, the two alternative processes can be used to achieve similar structure, as shown byFIGS. 8 and 12.

Referring toFIG. 9A, the insulating material420ofFIGS. 4A-4Chas been planarized. In this embodiment, the insulating material420has been removed generally down to a plane that corresponds to the top of the sacrificial material220above the insulator word line. Because planarization has been stopped earlier than the step described atFIG. 5above, this etch step leaves intact the thicker portions of the insulating material420and the sacrificial material220.

Referring toFIGS. 9B and 9C, planarization has left intact the thinner portions340of the sacrificial material220, in contrast to the planarization illustrated inFIGS. 5B and 5C, which removed the thinner portions340. As can be seen fromFIG. 9C, the thinner portions340of sacrificial material220are interspersed between thin portions940of insulating material420, which also crosses the word lines42.

Planarization can be accomplished using an etch step with a mechanical component, such as chemical mechanical polishing. Other processes that can be used to planarize include dry etching timed or otherwise configured (e.g. by optical endpoint detection) to stop on the sacrificial material220.

Referring toFIG. 10A, the sacrificial material220that remained after planarization has been removed, leaving deep plug voids1020bordered by the word lines42and the wavy lines of insulating material420. The deep plug voids1020are different from the plug voids620illustrated inFIG. 6because the insulating material that forms two walls of each void is taller for the deep plug voids1020inFIG. 10A. However, the word lines42that form the other two walls of each void are the same height for the plug voids620and the deep plug voids1020. Furthermore, despite their differences, the deep plug voids1020leave portions of the active areas32exposed, just as did the plug voids620illustrated inFIG. 6.

The sacrificial material220can be removed by a selective etch step. For example, if the sacrificial material220is photoresist, a dry develop or oxygen plasma etch can be used. If the sacrificial material220is amorphous carbon, an oxygen plasma or SO2-based plasma can be used.

If the remaining insulating material420has not already been densified, it can be densified after the sacrificial material220has been removed as illustrated. In some embodiments, densified material can be easier to remove than nondensified material. In some embodiments that use photoresist (as the sacrificial material220) and SOD (as the insulating material420), densification at this point is advantageous because photoresist may not be able to withstand the cure temperatures of SOD. In some embodiments, furthermore, even if amorphous carbon is used as the sacrificial material220, that amorphous carbon may not be able to withstand some temperatures (e.g., in a range of approximately 500 to 600 degrees Celsius). In this case, removing all of the sacrificial material220before densification of the insulating material420(e.g., of SOD) can allow for higher curing temperatures and/or longer cure times, providing more processing flexibility.

Referring toFIG. 10B, in the illustrated cross section, the free-standing word lines42alternate with plug voids1020. The back wall of the insulating material420is omitted to more clearly illustrate the voids1020.

Referring toFIG. 10C, the cross-section taken along the word line42illustrates that removal of the sacrificial material has resulted in the absence of the thinner portions340of sacrificial material220, but that the thin portions940of insulating material420are still in place generally on the word lines42where they cross the insulating material or field isolation regions34.

Referring toFIG. 11A, a coating of conductive material1120has been added to the structure illustrated inFIG. 10A. The conductive material1120has filled the deep plug voids1020left by removal of the sacrificial material220. The conductive material1120can be silicon, tungsten or any other suitable plug material. In the illustrated embodiment, the conductive material1120forms the plugs that fill the plug voids1020.

Referring toFIGS. 11B and 11C, cross-sectional views are shown of the conductive material1120that overlies the structure ofFIGS. 10B and 10C. Referring toFIG. 11D, a cross sectional view is shown taken along lines11D-11D ofFIG. 11A.

Referring toFIG. 12A, the conductive material1120has been planarized such that all material above a plane generally corresponding to the top of the word lines42has been removed. The planarizing processes described above with respect toFIGS. 5A-5Cand8A-8C can also be used to achieve the illustrated structure. The planarization has created isolated plugs1220from the interconnected conductive material1120. The conductive plugs1220form a conductive contact with the active areas32underlying the word lines42. The conductive plugs1220can act as bit line contacts (see bit line contacts62inFIG. 1Babove) or cell contacts (see cell contacts64inFIG. 1Babove), depending on their position with respect to and underlying active area32. By removing the sacrificial material220to form the deep voids1020, the plugs1220can be easily formed by simply coating the structure and planarizing, as shown. Furthermore, the conductive plugs1220are self-aligned in that the deep voids1020allow the conductive material1120to fill in and form the plugs1220that are directly aligned with the underlying active areas32without a mask step. The conductive plugs1220can be structurally identical to the conductive plugs820ofFIG. 8.

Referring toFIGS. 12B-12D, the cross sectional views show how the plane of planarization corresponds to the top of the word lines42. The illustrated planarization can be achieved using an etch step with a mechanical component, such as chemical mechanical polishing. Other processes that can be used to planarize include dry etching. As illustrated byFIG. 12D, the plugs1220generally overlie the active areas32. The two plugs1220illustrated inFIG. 8Dcan function as cell contacts because they overlie the end regions of the active areas32. InFIG. 12D, as inFIG. 8D, the side wall of the wordline42that would otherwise be visible in such a cross-sectional view has been omitted to more clearly illustrate the lack of structure between the plugs1220.

Referring toFIG. 13, the schematic, cross-sectional view illustrates an embodiment of an electronic device with which the structure ofFIGS. 12A-12Ccan be used. In particular, a first capacitor1320overlies two of the word lines42at the left of the figure, and a second capacitor1330overlies two of the word lines42at the right of the figure. Each capacitor has a top electrode1324and a bottom electrode1328. The top electrode1324can be a continuous common layer for an entire array, with periodic holes formed to allow the passage of structures such as the bit line contact1340, for example. In between the electrodes1324and1328is a capacitor dielectric material1326. In between the two capacitors1320and1330, a bit line plug1340forms an electrical contact between a conductive plug1220and an overlying bit line52. A source region1360of the active area32is located below a conductive plug1220in the central region of the active area32. On either side of the active area1360are channel regions1380. The tips of the active area32have drain regions1370, such that the channel regions1380can provide a connection between the source region1360and the drain regions1370.

In operation, electrical current can travel along the bit line52, down the bit line plug1340, and into the source region1360. Then, if the appropriate voltage is applied to the first conductive portions240of the word lines42and the appropriate charge carriers populate the channel regions1380, current can flow from the source region1360to the drain regions1370. The word lines42can act as “gates” because the field generated by the first conductive portions240attracts electrical carriers to the gate dielectric230and allows current to flow through the channel regions1380. When the gate is “open,” allowing current to flow through the channel region1380, an inversion layer of charge carriers (either holes or electrons) is formed in the channel region1380. After flowing across the channel regions1380, the current can then flow through the two side conductive plugs1220and across the intermediate contacts1390to the two bottom electrodes1328for storage. The intermediate contacts can be formed from a conductive material (e.g., polysilicon or metal). The described current flow can also happen in reverse to drain the stored charge from the capacitors1320and1330. In this configuration, the outermost word lines42can be inactive.

Referring toFIG. 14, the schematic plan view illustrates a layout for a portion of an integrated circuit similar to the layout ofFIG. 1B. However,FIG. 14includes exemplary plugs820such as those illustrated inFIGS. 8A and 12A(1220). The plugs820are illustrated along with the underlying active areas32and the overlying bit lines52to show how the plugs820can help connect the source regions1360of the active areas32to the overlying bit lines52.

As shown inFIG. 14, the plugs820can be grouped according to whether they have top and bottom (in the plan view ofFIG. 14) borders that slope upwardly or downwardly. In particular, the memory device can comprise a first component grouping that has a first elongate active area defining a first axis. The first axis can slope upwardly to the right, for example, in the illustrated plan view. The first elongate active area can have a first source and first and second drains. The drains can be located toward the tips of the oval-shaped active area, while the source can be located toward the center of the active area. The first component grouping can further comprise two substantially parallel word lines that cross and overlie the first active area, and at least a portion of a first word line can be located between the first drain and the first source. The first component grouping can further comprise a first plurality of contact plugs located on the same vertical level as the word lines. The contact plugs can comprise parallelogram (or rhomboid) portions of conductive material. The plurality of contact plugs can generally contact and overlie the first active area. At least one of the first plurality of contact plugs can extend between the at least two word lines and at least one of the first plurality of contact plugs can extend outwardly to the right and left from either wordline. The first plurality of contact plugs is preferably aligned with the first axis, as illustrated.

A second component grouping can be described similarly to the first component grouping, but with an axis that slopes downwardly to the right. Several groupings that meet the descriptions of first and second component groupings are illustrated inFIG. 14. Furthermore, the slopes of the first and second axes can have the same magnitude but opposite direction, as illustrated. (SeeFIG. 1Afor an illustration of exemplary elongate axes of active areas).

The structure, principles and advantages discussed herein are applicable to a variety of contexts in which sacrificial plugs are formed in connection with features of an Accordingly, it will be appreciated by those skilled in the art that various other omissions, additions and modifications may be made to the methods and structures described above without departing from the scope of the invention. All such modifications and changes are intended to fall within the scope of the inventions, as defined by the appended claims.