Display apparatus having a frame rate converter to convert a frame rate of input image data and method of driving display panel

A method of driving a display panel including converting a frame rate of input image data to generate first image data, writing the first image data to a memory, outputting a flag signal to a timing controller, reading the first image data from the memory according to the flag signal, compensating the first image data to generate second image data, and converting the second image data into an analog data voltage and outputting the data voltage to the display panel.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 2011-76806, filed on Aug. 2, 2011, which is hereby incorporated by reference for all purposes as if fully set forth.

BACKGROUND OF THE INVENTION

Exemplary embodiments of the present invention relate to a method of driving a display panel and a display apparatus for performing the method. More particularly, exemplary embodiments of the present invention relate to a method of driving a display panel for improving a display quality and a display apparatus for performing the method.

2. Discussion of the Background

A display apparatus includes a display panel and a panel driver driving the display panel. The display panel includes a plurality of gate lines, a plurality of data lines and a plurality of pixels connected to the gate lines and the data lines.

Generally, the panel driver includes a frame rate converter, a timing controller, a memory, a gate driver and a data driver. The timing controller includes a video interface to receive image data from the frame rate converter and a memory interface to communicate with the memory.

The timing controller includes both the video interface and the memory interface, and the timing controller includes many signal wirings so that a manufacturing cost of the display apparatus increases.

In addition, due to a complex structure for data transmission of the panel driver, a transmission speed decreases so that a display quality of the display panel for a three-dimensional image display, a high speed image display and a high resolution image display deteriorates.

The above information disclosed in the Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form any part of the prior art nor what the prior art may suggest to a person of ordinary skill in the art.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a method of driving a display panel simplifying a structure for data transmission of a panel driver to decrease a manufacturing cost of a display apparatus and to improve a display quality of the display panel.

Exemplary embodiments of the present invention also provide a display apparatus for performing the method of driving the display panel.

An exemplary embodiment of the present invention discloses a method of driving a display panel, the method including converting a frame rate of input image data to generate first image data, writing the first image data to a memory, outputting a flag signal to a timing controller, reading the first image data from the memory according to the flag signal, compensating the first image data to generate second image data, and converting the second image data into an analog data voltage and outputting the data voltage to the display panel.

An exemplary embodiment of the present invention also discloses a display apparatus including a display panel, a frame rate converter, a timing controller and a data driver. The display panel displays an image. The frame rate converter converts a frame rate of input image data using a first memory to generate first image data. The frame rate converter writes the first image data to a second memory. The frame rate converter generates a flag signal. The timing controller selectively reads the first image data from the second memory according to the flag signal. The timing controller compensates the first image data to generate second image data. The data driver converts the second image data into an analog data voltage. The data driver outputs the data voltage to the display panel.

An exemplary embodiment of the present invention also discloses a display apparatus including a display panel, a frame rate converter, a timing controller and a data driver. The display panel displays an image. The frame rate converter converts a frame rate of input image data using a memory to generate first image data. The frame rate converter writes the first image data to the memory. The frame rate converter generates a flag signal. The timing controller selectively reads the first image data from the memory according to the flag signal. The timing controller compensates the first image data to generate second image data. The data driver converts the second image data into an analog data voltage. The data driver outputs the data voltage to the display panel.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or directly connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers present. It will be understood that for the purposes of this disclosure, “at least one of X, Y, and Z” can be construed as X only, Y only, Z only, or any combination of two or more items X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ).

Hereinafter, exemplary embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

FIG. 1is a block diagram illustrating a display apparatus according to a first exemplary embodiment of the present invention.

Referring toFIG. 1, the display apparatus includes a display panel100and a panel driver driving the display panel100.

The panel driver includes a frame rate converter200, a first memory300, a timing controller400, a second memory500, a gate driver600and a data driver700.

The display panel100includes a plurality of gate lines GL1to GLN, a plurality of data lines DL1to DLM, and a plurality of pixels connected to the gate lines GL1to GLN and the data lines DL1to DLM.

The gate lines GL1to GLN extend in a first direction D1, and the data lines DL1to DLM extend in a second direction D2crossing the first direction D1.

Each pixel includes a switching element (not shown), a liquid crystal capacitor (not shown) and a storage capacitor (not shown). The liquid crystal capacitor and the storage capacitor are electrically connected to the switching element. The pixels are arranged in a matrix form.

The frame rate converter200receives input image data RGB and an input control signal from an external apparatus (not shown). The input image data RGB may include red image data, green image data and blue image data. The input control signal may include a master clock signal, a data enable signal, a vertical synchronizing signal and a horizontal synchronizing signal.

The frame rate converter200converts a frame rate of the input image data RGB using the first memory300to generate first image data FRGB. The frame rate converter200writes the first image data FRGB having the converted frame rate to the second memory500.

The frame rate converter200generates a flag signal FLAG. The frame rate converter200outputs the flag signal FLAG to the timing controller400.

A structure and an operation of the frame rate converter200are explained referring toFIGS. 2 and 3in detail below.

The timing controller400receives the input control signal from the frame rate converter200. Alternatively, the timing controller400receives the input control signal from an external apparatus.

The timing controller400generates a first control signal CONT1for controlling a driving timing of the gate driver600and a second control signal CONT2for controlling a driving timing of the data driver700based on the input control signal. The timing controller400outputs the first control signal CONT1to the gate driver600. The timing controller400outputs the second control signal CONT2to the data driver700.

The first control signal CONT1includes a vertical start signal and a gate clock signal. The second control signal CONT2includes a horizontal start signal and a load signal. The second control signal CONT2may further include a polarity inverting signal.

The timing controller400receives the flag signal FLAG from the frame rate converter200. The timing controller400selectively reads the first image data FRGB from the second memory500according to the flag signal FLAG.

The timing controller400compensates the first image data FRGB to generate second image data DATA. The timing controller400outputs the second image data DATA to the data driver700.

A structure and an operation of the timing controller400are explained referring toFIGS. 4 and 5in detail below.

The gate driver600receives the first control signal CONT1from the timing controller400. The gate driver600generates gate signals for driving the gate lines GL1to GLN in response to the first control signal CONT1. The gate driver600sequentially outputs the gate signals to the gate lines GL1to GLN.

The gate driver600may be disposed, e.g., directly mounted, on the display panel100, or be connected to the display panel100in a tape carrier package (“TCP”) type. Alternatively, the gate driver600may be integrated on the display panel100.

The data driver700receives the second control signal CONT2and the second image data DATA from the timing controller400. The data driver700receives a gamma reference voltage from a gamma voltage generator (not shown). The gamma voltage generator may be disposed in the timing controller400or in the data driver700.

The data driver700converts the second image data DATA into analog data voltages using the gamma reference voltage in response to the second control signal CONT2. The data driver700sequentially outputs the data voltages to the data lines DL1to DLM.

The data driver700may be disposed, e.g., directly mounted, on the display panel100, or be connected to the display panel100in a TCP type. Alternatively, the data driver700may be integrally formed on the display panel100.

FIG. 2is a block diagram illustrating the frame rate converter200ofFIG. 1.FIG. 3is a block diagram illustrating a first image processor230ofFIG. 2.

Referring toFIGS. 1 to 3, the frame rate converter200includes a first signal generator210, an image receiver220, the first image processor230, a compression encoder240and a first buffer250.

The first signal generator210generates a first memory control signal, a second memory control signal and the flag signal FLAG.

The first memory control signal controls an operation of the first memory300. The first signal generator210outputs the first memory control signal to the first memory300.

The second memory control signal controls an operation of the second memory500. The first signal generator210outputs the second memory control signal to the second memory500.

The flag signal FLAG controls an operation of the timing controller400. The first signal generator210outputs the flag signal FLAG to the timing controller400. For example, the flag signal FLAG may include a read signal and a write signal. For example, the flag signal FLAG may include a previous frame data read signal, a present frame data write signal, and a present frame data read signal.

The flag signal FLAG may have a differential mode. A signal in a differential mode is defined by a difference between a first reference voltage and a second reference voltage. When a noise is generated at a wiring transmitting the flag signal FLAG, both the first reference voltage and the second reference voltage may be influenced by the noise so that the difference between the first reference voltage and the second reference voltage may be maintained. Thus, the flag signal FLAG may maintain a uniform value regardless of the noise. Alternatively, the flag signal FLAG may have a transistor to transistor logic (“TTL”) mode.

The image receiver220receives the input image data RGB. The image receiver220includes a video interface. The image receiver220may receive the input image data RGB from a television set board. The image receiver220may transmit the input image data RGB to the first image processor230. The image receiver220may transmit the input image data RGB to the first buffer250.

The first image processor230converts a first frame rate of the input image data RGB into a second frame rate to generate the first image data FRGB having the second frame rate. The first image processor230may convert the first frame rate into the second frame rate, which is a multiple of the first frame rate. For example, the first frame rate may be about 60 Hz. For example, first image processor230may convert the first frame rate of about 60 Hz into the second frame rate of about 120 Hz. For example, first image processor230may convert the first frame rate of about 60 Hz into the second frame rate of about 240 Hz.

The first image processor230includes an image copying part231and a motion compensating part232. The image copying part231may read the first input image data RGB of the first frame rate stored in the first memory300in the second frame rate. Thus, the first image processor230may generate the first image data FRGB of the second frame rate including the copied image data.

The motion compensating part232may compensate the copied image data by comparing the input image data of the present frame to the input image data of the previous frame. Thus, the motion compensating part232may generate the motion compensated first image data FRGB. The motion compensating part232may be selectively operated according to the input image data RGB or a set-up of a user.

The compression encoder240receives the first image data FRGB from the first image processor230. The compression encoder240compresses the first image data FRGB to decrease a size of the first image data FRGB. The compression encoder240outputs the compressed first image data FRGB to the first buffer250. For example, the compression encoder240may compress the first image data FRGB to ⅓ of an original size of the first image data FRGB.

The compression encoder240may be omitted according to the input image data RGB. For example, the compression encoder240may be omitted when the input image data RGB represents a three-dimensional (“3D”) image.

The first buffer250is an input-output buffer. The first buffer250receives the input image data RGB from the image receiver220. The first buffer250writes the input image data RGB to the first memory300. The first buffer250reads the input image data RGB from the first memory300.

The first buffer250receives the first image data FRGB from the compression encoder240. When the compression encoder is omitted, the first buffer250receives the first image data FRGB from the first image processor230. The first buffer250writes the first image data FRGB to the second memory500.

The first buffer250includes a pad part including an input part and an output part. The pad part may permit bidirectional communication. The pad part may further include a variable resistor connected to the input part and the output part in parallel. A resistance of the variable resistor may be adjusted to compensate for a noise of the input image data RGB and a noise of the first image data FRGB. The compensating method using the variable resistor, as explained above, is called “On Die Termination.”

The first memory300receives the input image data RGB from the frame rate converter200and stores the input image data RGB according to the first memory control signal. The first memory300outputs the input image data RGB to the frame rate converter200according to the first memory control signal.

The first memory300includes a pad part including an input part and an output part. The pad part of the first memory300may permit bidirectional communication. The pad part of the first memory300may further include a variable resistor connected to the input part and the output part in parallel.

FIG. 4is a block diagram illustrating the timing controller400ofFIG. 1.FIG. 5is a block diagram illustrating a second image processor440ofFIG. 4.

Referring toFIGS. 1,4and5, the timing controller400includes a second signal generator410, a second buffer420, a compression decoder430and the second image processor440.

The second signal generator410generates the first control signal CONT1and the second control signal CONT2based on the input control signal. The second signal generator410outputs the first control signal CONT1to the gate driver600. The second signal generator410outputs the second control signal CONT2to the data driver700.

The second buffer420is an input-output buffer. The second buffer420reads the first image data FRGB from the second memory500. The second buffer420may selectively read the first image data FRGB from the second memory500according to the flag signal FLAG.

The second buffer420outputs the first image data FRGB to the compression decoder430. When the compression encoder240is omitted, the compression decoder430is omitted. When the compression decoder430is omitted, the second buffer420outputs the first image data FRGB to the second image processor440.

The second buffer420includes a pad part including an input part and an output part. The pad part of the second buffer420may permit bidirectional communication. The pad part of the second buffer420may further include a variable resistor connected to the input part and the output part in parallel.

The compression decoder430receives the first image data FRGB from the second buffer420. The compression decoder430decompresses the compressed first image data FRGB. The compression decoder430outputs the decompressed first image data FRGB to the second image processor440.

The second image processor440compensates the first image data FRGB to generate the second image data DATA. The second image processor440may compensate the first image data FRGB according to the flag signal FLAG.

The second image processor440may include a dynamic capacitance compensation (“DCC”) part441and an adaptive color correction (“ACC”) part442.

The DCC part441provides dynamic capacitance compensation which compensates a grayscale data of the present frame data using the previous frame data and the present frame data.

When the flag signal FLAG is the read signal, the second buffer420reads the previous frame data of the first image data FRGB from the second memory500. When the flag signal FLAG is the write signal, the frame rate converter200writes the present frame data of the first image data FRGB to the second memory500. When the flag signal FLAG is the read signal, the second buffer420reads the present frame data of the first image data FRGB from the second memory500. The DCC part441may compensate the present frame data of the first image data FRGB using the previous frame data of the first image data FRGB and the present frame data first image data FRGB, which are stored in the second buffer420.

The ACC part442provides adaptive color correction to the first image data FRGB. The ACC part442compensates the first image data FRGB using a gamma curve.

Positions of the DCC part411and the ACC part442may be switched with each other. Orders of the DCC operation and ACC operation may be switched with each other.

The second memory500receives the first image data FRGB from the frame rate converter200and stores the first image data FRGB according to the second memory control signal. The second memory500outputs the first image data FRGB to the timing controller400according to the second memory control signal.

The second memory500includes a pad part including an input part and an output part. The pad part of the second memory500may permit bidirectional communication. The pad part of the second memory500may further include a variable resistor connected to the input part and the output part in parallel.

Referring again toFIG. 1, the frame rate converter200may write the input image data RGB to the first memory300through a first wiring. The frame rate converter200may read the input image data RGB from the first memory300through the first wiring. The frame rate converter200may write the first image data FRGB to the second memory500through a second wiring. The timing controller400may read the first image data FRGB from the second memory500through a third wiring.

According to the present exemplary embodiment, the frame rate converter200directly transmits the first image data FRGB to the second memory500without passing through the timing controller400so that an image receiver may be omitted in the timing controller400. Thus, a manufacturing cost of the display apparatus may be decreased.

In addition, a transmission speed between the frame rate converter200and the second memory500is greater than a transmission speed between the frame rate converter200and the timing controller400so that the amount of signal wiring may be decreased. Thus, a manufacturing cost of the display apparatus may be decreased.

In addition, a transmission speed between the frame rate converter200and the second memory500is greater than a transmission speed between the frame rate converter200and the timing controller400so that a 3D image display, a high speed image display and a high resolution image display may be efficiently processed. Thus, a display quality of the display panel may be improved.

In addition, a transmission speed between the frame rate converter200and the second memory500is greater than a transmission speed between the frame rate converter200and the timing controller400so that the compression encoder240and the compression decoder430may be omitted. Thus, a distortion of an image due to the compression may be prevented so that a display quality of the display panel may be improved.

FIG. 6is a block diagram illustrating a display apparatus according to a second exemplary embodiment of the present invention.

A display apparatus according to the second exemplary embodiment is substantially the same as the display apparatus of the first exemplary embodiment explained referring toFIGS. 1 to 5except for a wiring structure connecting the frame rate converter200, the first memory300and the second memory500. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the previous exemplary embodiment ofFIGS. 1 to 5and any repetitive explanation concerning the above elements will be omitted.

Referring toFIG. 6, the display apparatus includes a display panel100and a panel driver driving the display panel100.

The panel driver includes a frame rate converter200, a first memory300, a timing controller400, a second memory500, a gate driver600and a data driver700.

The frame rate converter200, the first memory300and the second memory500are connected with one another through a first wiring having three terminals. A first terminal of the first wiring is connected to the frame rate converter200. A second terminal of the first wiring is connected to the first memory300. A third terminal of the first wiring is connected to the second memory500. The frame rate converter200may write the input image data RGB to the first memory300through the first wiring. The frame rate converter200may read the input image data RGB from the first memory300through the first wiring. The frame rate converter200may write the first image data FRGB to the second memory500through the first wiring. The timing controller400may read the first image data FRGB from the second memory500through a second wiring.

According to the second exemplary embodiment, the frame rate converter200, the first memory300and the second memory500are connected with one another through the first wiring having the three terminals so that a structure for data transmitting of the display apparatus may be more simplified, as compared to the display apparatus of the previous exemplary embodiment, as shown inFIGS. 1 to 5. Thus, a manufacturing cost of the display apparatus may be decreased, and a display quality of the display panel100may be improved.

FIG. 7is a block diagram illustrating a display apparatus according to a third exemplary embodiment of the present invention.

A display apparatus according to the third exemplary embodiment is substantially the same as the display apparatus of the first exemplary embodiment explained referring toFIGS. 1 to 5except that the frame rate converter200and the timing controller400use a single memory300A. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the first exemplary embodiment ofFIGS. 1 to 5and any repetitive explanation concerning the above elements will be omitted.

Referring toFIG. 7, the display apparatus includes a display panel100and a panel driver driving the display panel100.

The panel driver includes a frame rate converter200, a memory300A, a timing controller400, a gate driver600and a data driver700.

The frame rate converter200converts a frame rate of the input image data RGB using the memory300A to generate first image data FRGB. The frame rate converter200writes the first image data FRGB having the converted frame rate to the memory300A.

The memory300A receives the input image data RGB from the frame rate converter200and stores the input image data RGB. The memory300A outputs the input image data RGB to the frame rate converter200.

In addition, the memory300A receives the first image data FRGB from the frame rate converter200and stores the first image data FRGB. The memory300A outputs the first image data FRGB to the timing controller400.

The memory300A includes a pad part including an input part and an output part. The pad part of the memory300A may permit bidirectional communication. The pad part of the memory300A may further include a variable resistor connected to the input part and the output part in parallel.

The timing controller400selectively reads the first image data FRGB from the memory300A according to the flag signal FLAG.

The frame rate converter200may write the input image data RGB to the memory300A through a first wiring. The frame rate converter200may read the input image data RGB from the memory300A through the first wiring. The frame rate converter200may write the first image data FRGB to the memory300A through the first wiring. The timing controller400may read the first image data FRGB from the memory300A through a second wiring.

According to the third exemplary embodiment, the frame rate converter200and the timing controller400use a single memory300A so that a structure for transmitting data of the display apparatus may be more simplified as compared to the display apparatus of the first exemplary embodiment, as shown inFIGS. 1 to 5. Thus, a manufacturing cost of the display apparatus may be decreased, and a display quality of the display panel100may be improved.

FIG. 8is a block diagram illustrating a display apparatus according to a fourth exemplary embodiment of the present invention.

A display apparatus according to the fourth exemplary embodiment is substantially the same as the display apparatus of the third exemplary embodiment explained referring toFIG. 7except for a wiring structure connecting the frame rate converter200, the memory300A and the timing controller400. Thus, the same reference numerals will be used to refer to the same or like parts as those described in the third exemplary embodiment ofFIG. 7and any repetitive explanation concerning the above elements will be omitted.

Referring toFIG. 8, the display apparatus includes a display panel100and a panel driver driving the display panel100.

The panel driver includes a frame rate converter200, a memory300A, a timing controller400, a gate driver600and a data driver700.

The frame rate converter200, the memory300A and the timing controller400are connected with one another through a first wiring having three terminals. A first terminal of the first wiring is connected to the frame rate converter200. A second terminal of the first wiring is connected to the memory300A. A third terminal of the first wiring is connected to the timing controller400. The frame rate converter200may write the input image data RGB to the first memory300through the first wiring. The frame rate converter200may read the input image data RGB from the memory300A through the first wiring. The frame rate converter200may write the first image data FRGB to the memory300A through the first wiring. The timing controller400may read the first image data FRGB from the memory300A through the first wiring.

According to the fourth exemplary embodiment, the frame rate converter200, the memory300A and the timing controller400are connected with one another through the first wiring having the three terminals so that a structure for transmitting data of the display apparatus may be more simplified as compared to the display apparatus of the third exemplary embodiment shown inFIG. 7. Thus, a manufacturing cost of the display apparatus may be decreased, and a display quality of the display panel100may be improved.

According to the fourth exemplary embodiments of the present invention as explained above, a structure for transmitting data of the panel driver may be simplified so that a manufacturing cost of the display apparatus may be decreased and a display quality of the display panel may be improved.

Although the display panel of the exemplary embodiments described above is a liquid crystal display panel, other display panels may be used. For example, exemplary embodiments of the present invention could be used with a plasma display panel, an organic light emitting diode display panel, etc.