METHODS AND SYSTEMS OF CURRENT SENSING IN SWITCHING POWER CONVERTERS

Current sensing in switching power converters. At least one example is a method comprising: discharging an inductor of a buck converter using a low-side FET during a discharge mode of a first cycle; providing, during the discharge mode, a signal indicative of instantaneous current to a voltage regulator, the signal indicative of instantaneous current proportional to current through the inductor during at least a portion of the discharge mode; charging the inductor using a high-side FET during a charge mode, the charge mode in a second cycle subsequent to the discharge mode; and providing, during the charge mode, an emulated signal to the voltage regulator, the emulated signal generated based on the current through the inductor in the discharge mode.

CROSS-REFERENCE TO RELATED APPLICATIONS

Not Applicable.

BACKGROUND

In the high performance computer market, such as severs in a data center, as the performance of the processors is increasing, the supply voltages to the processors is decreasing and supply current is increasing. The lower voltage and higher current operation of the processors may strain the DC-DC switching power converters that regulate the voltage. For example, a DC-DC switching power convert may be provided an unregulated input voltage between 10 Volts (V) and 15V, and the DC-DC switching power converter may produce a regulated output voltage of about 1.0V. The relatively large voltage differential between the unregulated input voltage and the regulated output voltage, in combination with the high current demand, may force the DC-DC switching power converter to operate at high switching frequencies.

SUMMARY

One example is a method of operating a switching power converter, the method comprising: discharging an inductor of a buck converter using a low-side FET during a discharge mode of a first cycle; providing, during the discharge mode, a signal indicative of instantaneous current to a voltage regulator, the signal indicative of instantaneous current proportional to current through the inductor during at least a portion of the discharge mode; charging the inductor using a high-side FET during a charge mode, the charge mode in a second cycle subsequent to the discharge mode; and providing, during the charge mode, an emulated signal to the voltage regulator, the emulated signal generated based on the current through the inductor in the discharge mode.

In the example method, providing the signal indicative of instantaneous current to the voltage regulator may further comprise driving the signal indicative of instantaneous current to a first terminal of a power module; and providing the emulated signal may further comprise driving the emulated signal to the first terminal of the power module.

In the example method, providing the emulated signal may further comprise: sensing that the buck converter is in non-transient operation; and providing, during the charge mode of the second cycle, a signal indicative of average current to the voltage regulator, the signal indicative of average current having a magnitude proportional to an average current through the inductor during at least a portion of the first cycle. Providing the signal indicative of instantaneous current during the discharge mode may further comprise sensing a voltage drop across the low-side FET, and driving the signal indicative of instantaneous current proportional to the voltage drop across the low-side FET; and providing the signal indicative of average current may further comprise: generating, during the first cycle, the signal indicative of average current through the inductor during the discharge mode; and driving, during the charge mode of the second cycle, the signal indicative of average current. Sensing that the buck converter is in non-transient operation may further comprise sensing that a discharge mode has a duration longer than a blanking time for measuring voltage drop across the low-side FET.

In the example method, providing the emulated signal may further comprise: sensing that the buck converter is in transient operation; and providing a ramp signal to the voltage regulator, the ramp signal having a slope proportional to an absolute value of a slope of the signal indicative of instantaneous current in the discharge mode. Sensing that the buck converter is in transient operation may further comprise sensing that a discharge mode has a duration shorting than a blanking time for measuring voltage drop across the low-side FET.

In the example method, providing the emulated signal further comprise: sensing that a discharge mode has a duration shorting than a blanking time for measuring voltage drop across the low-side FET; and responsive to the discharge mode having a duration shorting than a blanking time, providing a ramp signal to the voltage regulator, the ramp signal having a slope proportional to an absolute value of a slope of the signal indicative of instantaneous current in the discharge mode.

Yet another example is a power module comprising: a switch-node terminal, a PWM-input terminal, and a monitor-output terminal; a high-side FET defining a drain, a source coupled to the switch-node terminal, and a gate; a low-side FET defining drain coupled to the switch-node terminal, a source, and a gate; and a controller coupled to the gate of the high-side FET, the gate of the low-side FET, the PWM-input terminal, and the monitor-output terminal. The controller may be configured to: responsive to de-assertion of the PWM-input terminal, make the high-side FET non-conductive and the low-side FET conductive to define a discharge mode in a first cycle; drive, during the discharge mode, a signal indicative of instantaneous current to the monitor-output terminal, the signal indicative of instantaneous current directly proportional to voltage drop across the low-side FET during at least a portion of the discharge mode; responsive to assertion of the PWM-input terminal, make the low-side FET non-conductive and the high-side FET conductive to define a charge mode in a second cycle subsequent to the first cycle; and drive, during the charge mode of the second cycle, an emulated signal to the monitor-output terminal, the emulated signal generated based on the current through the low-side FET in the first cycle.

In the example power module, when the controller drives the emulated signal to the monitor-output terminal, the controller may be further configured to: sense non-transient operation; and drive, during the charge mode of the second cycle, a signal indicative of average current to the monitor-output terminal, the signal indicative of average current having a magnitude proportional to an average current through the low-side FET during at least a portion of the first cycle. When the controller drives the signal indicative of average current to the monitor-output terminal, the controller may be further configured to: generate, during the first cycle, an intermediate signal indicative of average current through low-side FET during the discharge mode; and drive, during the charge mode of the second cycle, the signal indicative of average current based on the intermediate signal indicative of average current. When the controller senses the non-transient operation, the controller may be further configured to sense that a discharge mode has a duration longer than a blanking time for measuring a voltage drop across the low-side FET.

In the example power module, when the controller drives the emulated signal to the monitor-output terminal, the controller may be further configured to: sense transient operation; and drive, during the charge mode of the second cycle, a ramp signal to the monitor-output terminal, the ramp signal having a slope proportional to an absolute value of a slope of the signal indicative of instantaneous current in the discharge mode. When the controller senses the transient operation, the controller is further configured to sense that a discharge mode has a duration shorting than a blanking time for measuring a voltage drop across the low-side FET.

Yet another example is a system comprising: an inductor defining a first lead and a second lead coupled to a load; a voltage regulator defining a voltage-monitor input coupled to the second lead, a PWM output, and a current-monitor input; and a power module defining a switch node coupled to the first lead, a PWM input coupled to the PWM output, and a monitor output coupled to the current-monitor input. The power module may comprise: a high-side FET defining a source coupled to the switch node and a gate; a low-side FET defining drain coupled to the switch node, and a gate; and a controller coupled to the gate of the high-side FET, the gate of the low-side FET, the PWM input, and the current-monitor input of the voltage regulator. The controller may be configured to: responsive to de-assertion of the PWM input, make the high-side FET non-conductive and the low-side FET conductive to discharge the inductor during a discharge mode of a first cycle; drive, during the discharge mode, a signal indicative of instantaneous current to the current-monitor input, the signal indicative of instantaneous current proportional to an instantaneous current through the inductor during at least a portion of the discharge mode; responsive to assertion of the PWM input, make the low-side FET non-conductive and the high-side FET conductive to charge the inductor during a charge mode of a second cycle subsequent to the first cycle; and drive, during the charge mode of the second cycle, an emulated signal to the current-monitor input, the emulated signal generated based on the current through the inductor in the first cycle.

In the example system, when the controller drives the emulated signal to the current-monitor input, the controller is further configured to: sense a non-transient operation of the system; and drive, during the charge mode of the second cycle, a signal indicative of average current to the current-monitor input, the signal indicative of average current having a magnitude proportional to an average current through the inductor during at least a portion of the first cycle.

In the example system, when the controller drives the signal indicative of instantaneous current to the current-monitor input, the controller is further configured to sense a voltage drop across the low-side FET, and drive the signal indicative of instantaneous current proportional to the voltage drop across the low-side FET, and when the controller drives the signal indicative of average current to the current-monitor input, the controller may be further configured to: generate an intermediate signal indicative of average current through the inductor during the discharge mode of the first cycle; and drive, during the charge mode of the second cycle, the signal indicative of average current based on the intermediate signal indicative of average current. When the controller senses the non-transient operation, the controller may be further configured to sense that a discharge mode has a duration longer than a blanking time for measuring voltage drop across the low-side FET.

In the example system, when the controller drives the emulated signal to the current-monitor input, the controller may be further configured to: sense transient operation of the system; and drive, during the charge mode of the second cycle, a ramp signal to the current-monitor input, the ramp signal having a slope proportional to an absolute value of a slope of the signal indicative of instantaneous current in the discharge mode of the first cycle. When the controller senses the transient operation, the controller is further configured to sense that a discharge mode has a duration shorting than a blanking time for measuring voltage drop across the low-side FET.

DEFINITIONS

“About” in reference to a recited parameter shall mean the recited parameter plus or minus ten percent (+/−10%) of the recited parameter.

“DC” shall mean direct current.

“FET” shall mean a field effect transistor, such as a junction-gate FET (JFET) or metal-oxide-silicon FET (MOSFET).

“Closing” in reference to an electrically-controlled switch (e.g., a FET) shall mean making the electrically-controlled switch conductive. For example, closing a FET used as an electrically-controlled switch may mean driving the FET to the fully conductive state.

“Opening” in reference to an electrically-controlled switch (e.g., a FET) shall mean making the electrically-controlled switch non-conductive.

The terms “input” and “output” when used as nouns refer to connections (e.g., electrical, software), and shall not be read as verbs requiring action. For example, a timer circuit may define a clock output. The example timer circuit may create or drive a clock signal on the clock output. In systems implemented directly in hardware (e.g., on a semiconductor substrate), these “inputs” and “outputs” define electrical connections. In systems implemented in software, these “inputs” and “outputs” define parameters read by or written by, respectively, the instructions implementing the function.

“Assert” shall mean changing the state of a Boolean signal. Boolean signals may be asserted high or with a higher voltage, and Boolean signals may be asserted low or with a lower voltage, at the discretion of the circuit designer. Similarly, “de-assert” shall mean changing the state of the Boolean signal to a voltage level opposite the asserted state.

“Controller” shall mean, alone or in combination, individual circuit components, an application specific integrated circuit (ASIC), a microcontroller with controlling software, a reduced-instruction-set computing (RISC) with controlling software, a digital signal processor (DSP), a processor with controlling software, a programmable logic device (PLD), a field programmable gate array (FPGA), or a programmable system-on-a-chip (PSOC), configured to read inputs and drive outputs responsive to the inputs.

DETAILED DESCRIPTION

Various examples are directed to methods and systems of current sensing in switching power converters. More particularly, various examples are directed to creating a current-monitor signal (Imon) provided from a power module to a voltage regulator, where the current-monitor signal is generated during discharge modes by measuring the voltage drop across a low-side FET and driving the current-monitor signal proportional to the voltage drop across the low-side FET. The voltage drop across the low-side FET is proportional to the current flow through the inductor during the discharge mode. During charge modes, the power module provides an emulated signal, where nature of the emulated signal is based on an operational state of the power converter. For example, during non-transient operation, the emulated signal is a signal indicative of the average current through the inductor in a previous discharge mode, such as the immediately previous discharge mode. During transient operation, the emulated signal is a ramp signal having a slope proportional to the slope of the inductor current in a previous discharge mode, such as an immediately previous discharge mode. In this way, the power module provides the current-monitor signal within accuracy limits without measuring voltage drop across the high-side FET during charge modes. The specification now turns to an example system to orient the reader.

FIG.1shows an example system100. In particular,FIG.1shows a power module102, an inductor104, a smoothing capacitor106, a load108(shown as RL), and a voltage regulator110. The example power module102defines an input voltage terminal112coupled to the input voltage VIN, a switch-node terminal114, a reference-voltage terminal116coupled to a reference voltage (e.g., ground or common), a monitor-output terminal118, and PWM-input terminal120. The example inductor104defines a first lead coupled to the switch-node terminal114, and the switch-node terminal114and the first lead thus define the switch node of the system. The second lead of the inductor104defines the output voltage VOUTlead or terminal, and the second lead is coupled the load108. The smoothing capacitor106defines a first lead coupled to the second lead of the inductor104and thus the output voltage VOUT, and a second lead coupled to the reference voltage. The example voltage regulator110defines a PWM output122coupled to the PWM-input terminal120, a monitor input124coupled to the monitor-output terminal118, and a feedback input126coupled to the output voltage VOUT.

In one example, the input voltage VINmay range from 10V to 15V. The output voltage VOUTmay be selectable, at the design stage, in a range from between and including 0.8V and 1.8V, in some cases 1.0V. Thus, the power module102and the inductor104are arranged as a buck converter or for buck-type operation. The example ofFIG.1shows the voltage regulator110associated with a single power module102. However, in practice the voltage regulator110may couple to and control an array of power modules, with each power module in the array operating in a phased manner to provide voltage and current to the shared load108.

In operation, the voltage regulator110asserts the PWM-input terminal120of the power module102to begin a charge mode of the inductor104. In the charge mode, the power module102couples the input voltage VINto the switch node defined by the switch-node terminal114. However, because current through an inductor cannot change instantaneously, during the charge mode the current through the inductor104ramps upward as energy is stored the field around the inductor104. The voltage regulator110then de-asserts the PWM-input terminal120to begin a discharge mode of the inductor104. In the discharge mode, the power module102couples the reference voltage at the reference voltage terminal116to the switch node defined by the switch-node terminal114. Again however, because current through the inductor104cannot change instantaneously, during the discharge mode the field around the inductor collapses as the inductor104continues to provide current to the smoothing capacitor106and load108. A charge mode and contiguous discharge mode constitutes a single cycle of the operation of the buck converter.

The example voltage regulator110may be a part number FD3501 or part number FD5001 available from On Semiconductor, Phoenix, Arizona. The example voltage regulator110receives two feedback signals for operation of the system100. The first feedback signal is an indication of output voltage VOUTreceived by way the feedback input126. The second feedback signal is a current-monitor signal (Imon) driven from the monitor-output terminal118to the monitor input124of the voltage regulator110. In particular, the example system100does not directly measure load current with a current sensor (e.g., current sensor associated with the second lead of the inductor104). Rather, in the example system the power module102is designed and constructed to generate and provide the current-monitor signal to the voltage regulator110, and based on the current-monitor signal the voltage regulator110controls the frequency of assertion of the PWM-input terminal120.

In some example systems, the amount of energy supplied from the input voltage VINto the output voltage VOUTis directly proportional to the frequency of operation. For example, as the load108increases, drawing higher current, the frequency of the PWM signal applied to the PWM-input terminal120increases. As the load108decreases, drawing less current, the frequency of the PWM signal applied to the PWM-input terminal120decreases. The specification now turns to example waveforms to explain various time frames of interest.

FIG.2shows an example timing diagram. In particular,FIG.2shows: plot200showing an example PWM signal; plot202showing inductor current; and plot204showing an example current-monitor signal of the related-art. The plots are shown on corresponding time axes, but the plots are not necessarily to scale. Referring initially to the PWM signal of plot200. Between time t0and time t1, the example PWM signal is shown asserted, here asserted high or with a high voltage. It is noted that the asserted state (e.g., high voltage or low voltage) of the PWM signal may be selected at the discretion of the circuit designer. The duration between t0and t1may be referred to as the charge mode or TON, referring to the period of time that the inductor104(FIG.1) is coupled to the input voltage VINthrough the power module102(FIG.1). Between time t1and t6, the example PWM signal is shown de-asserted, here de-asserted low or with a low voltage. The time duration between t1and t6may be referred to as the discharge mode or TOFF, referring to the period of time that the first lead of the inductor104is coupled to the reference voltage (e.g., ground) through the power module102. The time duration between time t0and time t6is the switching period TSW, and the inverse of the switching period TSWis the switching frequency. In example cases, the time duration between t0and t6(i.e., the switching period TSW) is referred to as a switching cycle or just cycle and is made up of a single charge mode and a contiguous single discharge mode. In the example ofFIG.2, the time duration between t6and t10is a second cycle, the cycle subsequent to and contiguous with the first cycle between times t0and t6. Thus,FIG.2shows two complete cycles, and one partial cycle (to the right of t10).

Plot202shows the inductor current over time. For example, during the charge mode between times t0and t1, the first lead of the inductor104(FIG.1) is coupled to the input voltage VIN, and thus the inductor current is rising over time. At time t1, the voltage regulator110(FIG.1) de-asserts the PWM signal, and thus the power module102(FIG.1) de-couples the first lead of the inductor from the input voltage VINand couples the first lead of the inductor104to the reference voltage (e.g., ground). Thus, during the discharge mode between times t1and t6the inductor current falling over time. The subsequent charge mode begins anew at time t6.

A few points about the plots200and202. First, the example plots represent a non-transient operation. That is, the load current (e.g., the average current) provided from the example system is relatively steady for the example PWM signal of plot200and the example inductor current of plot202. The specification expressly discusses transient operation in greater detail below. Second, in example systems, neither the power module102nor the voltage regulator110measure the inductor current of plot202directly. The plot202is shown to orient the reader the ideas of charge mode or on time TON, discharge mode or off time TOFF, and switching cycles.

In related-art systems the power modules provide to the voltage regulator a current-monitor signal that is a scaled version of the sawtooth waveform of the inductor current of plot202. Plot204ofFIG.2shows an example current-monitor signal206that may be provided from the related-art power modules, with the current-monitor signal206reproducing the sawtooth waveform of the inductor current. The current-monitor signal created by related-art power modules may be created by use of a current sensor within the power module (e.g., a current transformer created in silicon, or a low resistance shunt resistor). In other cases in related-art systems, the portion of the current-monitor signal during the charge mode may be created by measuring voltage drop across a high-side switch (i.e., the switch that couples the input voltage VINto the switch node), and driving the current monitor signal proportional to the voltage drop across the high-side switch. However, as the output voltage VOUTdecreases relative to input voltage VIN, and as switching frequencies continue to increase, the time duration of each charge mode becomes increasingly shorter. The short duration charge modes make measuring voltage drop across a high-side switch, as a proxy for inductor current, increasingly difficult to implement.

The inventors of the present specification discovered that power modules need not reproduce, by way of the current-monitor signal, the full sawtooth waveform of the inductor current (in scaled form). Rather, the inventors of the present specification discovered that, so long as the current-monitor signal has an average value within a predetermined tolerance (e.g., 3%) of the actual average value, the current-monitor signal need not reproduce the full sawtooth waveform. Stated otherwise, the current-monitor signal may reproduce only portions the sawtooth waveform, and the remaining portions may be emulated signals that do not track the sawtooth waveform and still the overall cycle-by-cycle average accuracy is present.

Returning toFIG.1. In various examples, during each discharge mode the power module102is designed and constructed to provide a signal indicative of instantaneous current to the monitor input124of the voltage regulator110. The signal indicative of instantaneous current is proportional to current through the inductor during at least a portion of the discharge mode. In a subsequent charge mode, such as an immediately subsequent charge mode, the power module102is designed and constructed to provide an emulated signal to the monitor input124of the voltage regulator110. The emulated signal takes different forms depending on the operational state of the system100. In non-transient operation (e.g., shown inFIG.2), the emulated signal is a signal indicative of average current through the inductor104during a previous discharge mode, such as the immediately previous discharge mode. In transient operation, the emulated signal is a ramp signal have a slope proportional to an absolute value of a slope of the signal indicative of instantaneous current in a previous discharge mode, such as the immediately previous discharge mode. In this way, the voltage regulator110is provided a current-monitor signal that has an average value that closely matches the actual average value.

FIG.3shows a partial electrical schematic, partial block diagram, of an example power module102. In particular,FIG.3shows the input-voltage terminal112, the switch-node terminal114, the reference-voltage terminal116, the monitor-output terminal118, and the PWM-input terminal120. Other terminals may be present, but such additional terminals are not shown or described so as not to unduly complicate the discussion. Internally, the example power module102implements a high-side electrically-controlled switch illustratively shown as a FET (and hereafter high-side FET300). The example high-side FET300defines a drain coupled to the input-voltage terminal112, a source coupled to the switch-node terminal114, and a gate. The example power module further implements a low-side electrically-controlled switch illustratively shown as a FET (and hereafter low-side FET302). The example low-side FET302defines a drain coupled to the switch-node terminal114, a source coupled to the reference-voltage terminal116, and a gate. The example power module102further implements a controller304. The controller304is coupled to the gate of the high-side FET300, the switch-node terminal114, the gate of the low-side FET302, the reference-voltage terminal116, the monitor-output terminal118, and the PWM-input terminal120. To aid in the further discussion, also shown inFIG.3are the input voltage VIN, the reference voltage (e.g., ground or common), the inductor104, and the load108.

The electrical devices of the power module102may be monolithically created on one more substrates and encapsulated within packaging to form a packaged-semiconductor product or packaged-semiconductor device. For example, the controller304may be constructed on a substrate306, the high-side FET300may be constructed on a substrate308distinct from the substrate306, and the low-side FET302may be constructed on a substrate310distinct from the other substrates. All three substrates may be electrically coupled to each other and co-packaged (e.g., multi-chip module). In other cases, the controller304and low-side FET302may be constructed on the same substrate and packaged with a distinct substrate308for the high-side FET300. The various terminals may be electrical connections or pins accessible on the outside surface of the packaging.

The example controller304may be, alone or in combinations, individual circuit components, an application specific integrated circuit (ASIC), a microcontroller with controlling software, a reduced-instruction-set computing (RISC) with controlling software, a digital signal processor (DSP), a processor with controlling software, a programmable logic device (PLD), a field programmable gate array (FPGA), or a programmable system-on-a-chip (PSOC), configured to read inputs and drive outputs responsive to the inputs. The discussion now turns to operation of the power module102in greater detail.

Because the operation of the power module102in the charge mode is controlled in part by various readings and measurements taken during a prior discharge mode (e.g., the immediately previous discharge mode), the discussion of operation begins with a description of the discharge mode. In particular, in a prior charge mode, the PWM-input terminal120is asserted and the high-side FET300is conductive. Responsive to de-assertion of the PWM-input terminal120, the example controller304is designed and constructed to de-assert the gate of the high-side FET300, and after a blanking time assert the gate of the low-side FET302. Stated otherwise, responsive to de-assertion of the PWM-input terminal120the controller304makes the high-side FET300non-conductive, thus beginning the discharge mode.

The blanking time (e.g., between 100 and 200 nano-seconds (ns)) ensures the input voltage VINis not shorted to the reference voltage through the FETs. Stated otherwise, the blanking time ensures there is no cross-conduction of the input voltage VINthrough the FETs to the ground or common. Within the discharge mode but during the blanking time, current drawn by the inductor104flows through the body diode312of the low-side FET302. After the blanking time, the controller304asserts the gate of the low-side FET302to make the low-side FET302fully conductive. Thus, the downward ramping current through the inductor104is drawn first through the body diode312, and then through the low-side FET302itself.

During the discharge mode, the controller304is designed and constructed to drive, to the monitor-output terminal118, a signal indicative of instantaneous current through the inductor104. In example cases, the signal indicative of instantaneous current is created by measuring the voltage drop across the low-side FET302during the discharge mode. That is, even in a fully conductive state, the low-side FET302has an inherent resistance (Rds(on)). Thus, the current through the low-side FET302produces a voltage drop with a magnitude over time directly proportional to the magnitude over time of the current through the inductor104.

In an ideal case, the controller304measures the voltage drop across the low-side FET302at all times during the discharge mode as an indication of current flow through the inductor104. However, during the blanking time, the low-side FET302is non-conductive and the inductor current is drawn through the body diode312. Thus, during the blanking time the voltage drop across the low-side FET302is limited to the diode forward voltage drop. Moreover, the various electrical circuits used to measure the voltage drop across the low-side FET302have a settling time (e.g., between 100 and 200 ns), and thus during the settling time the readings may not be stable. In some examples, the controller304is designed and constructed to drive the signal indicative of instantaneous current to the monitor-output terminal118starting at the end of the blanking time. The discussion now turns to an immediately subsequent charge mode.

Responsive to assertion of the PWM-input terminal120, the example controller304is designed and constructed to de-assert to the gate of the low-side FET302, and after another blanking time, assert the gate the gate of the high-side FET300. Stated otherwise, responsive to assertion of the PWM-input terminal120the controller304makes the low-side FET302non-conductive and the high-side FET300conductive, thus beginning a charge mode.

During the charge mode, the controller304is designed and constructed to drive, to the monitor-output terminal118, an emulated signal generated based on the current through the inductor in the prior discharge mode. In particular, during non-transient operation, the controller304is designed and constructed to drive a signal indicative of average current having a magnitude proportional to an average current through the inductor during at least a portion of the last discharge mode.

FIG.4shows an example timing diagram. In particular,FIG.4shows: plot400showing an example PWM signal; plot402showing inductor current; and plot404showing an example current-monitor signal provided from the power module to the voltage regulator. The plots are shown on corresponding time axes, but the plots are not necessarily to scale. Referring initially to the PWM signal of plot200. As before, between time t0and time t1the example PWM signal is shown asserted to define the charge mode of the inductor104(FIG.1). Between time t1and t6, the example PWM signal is shown de-asserted to define the discharge mode of the inductor104. Again as before, the time duration between t6and t10is a second cycle, the second cycle subsequent to and contiguous with the first cycle between times t0and t6.

Again as before plot402shows the inductor current over time. Between times t0and t1is the charge mode with the inductor current rising over time. Between times t1and t6is the discharge mode with the inductor current falling over time. Again, the example plots represent a non-transient operation. Moreover, in example cases neither the power module102nor the voltage regulator110measure the inductor current of plot202directly. The plot402is shown as a reference regarding the actual inductor current over time.

Before addressing the specifics of the current-monitor signal produced by the example power module102(FIG.3), a few additional time frames or time durations are introduced. In particular, the time duration between time t1and t2(TBLANK) is the blanking time discussed above, and used to ensure there is no cross-conduction through the power module102between input voltage VINand common or ground, and also used as a settling time for a measurement amplifier (discussed more below). Moreover, the time duration between time t2and t3is the setting time for a measurement circuit. Similarly for the second cycle shown, the time duration between time t7and t8is a blanking time, and the time duration between time t8and t9is a setting time for the measurement circuit.

Plot404shows an example current-monitor signal provided by the controller304(FIG.3) to the monitor-output terminal118(FIG.3). Following the sequence of discussing a discharge mode before discussing the charge mode, responsive to de-assertion of the PWM signal at time t1, the example controller304makes the high-side FET300non-conductive, thus beginning the discharge mode. During the blanking time between t1and t2, the inductor104current flows through the body diode312of the low-side FET302. After the blanking time, and starting at time t2, the controller304makes the low-side FET302conductive. Between times t2and t6, and again in non-transient operation, the controller304provides or drives a signal406indicative of instantaneous current through the inductor. In the time duration between times t2and t3, as the measurement circuit settles, the signal driven approaches the representation of the instantaneous current. And starting at time t3the example signal406indicative of instantaneous current more closely matches the instantaneous current. The signal406indicative of instantaneous current may be scaled to be 5 micro-Amps (μA) of current-monitor signal for each amp of inductor current (5 μA/A). Co-plotted, in dashed line form, in plot404is a scaled version of the inductor current for reference.

The example controller304(FIG.3) performs several measurements and calculations during the example discharge mode between times t1and t6. For example, in measuring the voltage drop across the low-side FET302(FIG.3) and generating the signal406indicative of instantaneous current, the controller304also creates a signal or value indicative average current through the inductor during the discharge mode. Though discussed in greater detail below, creating the value indicative of average current may involve low-pass filtering the signal406to arrive at the value indicative of average current. However, any averaging technique may be used.

Also during the example discharge mode between times t1and t6, the example controller304determines or measures the slope of the signal406indicative of instantaneous current. For example, the controller304is designed and constructed to sample the magnitude of the signal406at time t4(the sample indicated by dot408). The controller304may sample the magnitude of the signal406at time t5(prior to the end of the charge mode), as indicated by dot410. The time duration between t2and t4may be referred to TSAMPLE1. Similarly, the time duration between t2and t5may be referred to TSAMPLE2. Using the two samples or the two magnitudes, the controller304calculates a value indicative of slope. During non-transient operation, and in the next cycle, the slope calculated may be used to correct the average current values for shortcomings associated with the blanking time and measurement settling time. Also, the slope may be used in a subsequent charge mode during transient operation to set the slope of a ramp signal.

Still referring toFIG.4. Responsive to assertion of the PWM signal at time t6, the example controller304makes the low-side FET302non-conductive and makes high-side FET300conductive, thus beginning the charge mode of the next cycle. In accordance with various examples, between times t6and at least t7, and in non-transient operation, the controller304provides or drives a signal412indicative of average current through the inductor. In example cases, the signal412indicative of average current through the inductor is based on the value indicative of average current created during the previous discharge mode, in this example the value indicative of average current created during times t2and t6of the immediately previous discharge mode. Stated otherwise, in spite of the fact that the actual inductor current (e.g., of plot402) is ramping upward, the controller304is designed and constructed to provide signal412having a substantially constant magnitude, the magnitude proportional to the average current through the inductor in the previous discharge mode.

Responsive to de-assertion of the PWM signal at time t7, the example controller304makes the high-side FET300non-conductive, thus beginning the next discharge mode. In some examples, the controller304is designed and constructed to drive the signal412indicative of average current through blanking time (i.e., to time t8). The controller304is designed and constructed to begin driving a signal414proportional to voltage across the low-side FET302starting at time t8even though the measurement circuit may not have yet settled. In particular, the example signal414indicative of instantaneous current comprises a settling portion416between times t8and t9.

The example controller304will likewise perform measurements and calculations during the example discharge mode between times t7and t10. For example, the example controller304creates anew the value indicative average current through the inductor during the discharge mode. The value indicative average current through the inductor may be used in a subsequent charge mode (e.g., the charge mode beginning at time t10). Moreover, the controller304may calculate the slope of the signal414indicative of instantaneous current, again for use in a subsequent charge mode (e.g., the charge mode beginning at time t10). The dots representing the sample times within the second cycle for calculating the slope are omitted so as onto to further complicate the figure.

The operation of the example power module102and related system100in reference toFIG.4assumes non-transient operation. That is, the discussion assumes that the voltage regulator110(FIG.1), the power module102(FIG.1), and the inductor104(FIG.1) are providing substantially constant average current to the load108(FIG.1). However, current drawn by the load108may be highly variable. For example, the load108in the example form of a server may go from lightly loaded to fully loaded in just a few cycles of the system100. Thus, the discussion turns to operation of the example system in transient conditions.

FIG.5shows an example timing diagram for transient operation. In particular,FIG.5shows: plot500showing an example PWM signal; and plot502showing an example current-monitor signal provided from the power module to the voltage regulator. The plots are shown on corresponding time axes, but the plots are not necessarily to scale. Referring initially to the PWM signal of plot500. Between time t10and time t11the example PWM signal is shown asserted to define the charge mode of the inductor104(FIG.1). Between time t11and t12, the example PWM signal is shown de-asserted to define a discharge mode. In this example, the discharge mode is short, and the PWM signal of plot500is again asserted at times t12through t14. Another short discharge mode is defined between times t14and t15, and again the PWM signal is asserted between times t15and t17. Between times t17and t19the PWW signal is de-asserted, defining a longer discharge mode. The plot500ofFIG.500thus shows an example transient operation in which the frequency of operation is increased because of higher current drawn by the load108(FIG.1). Stated otherwise, the higher current drawn is provided, at least in part, by shortening the discharge modes. At time t17, the example transient operation effectively ends, and an extended-length discharge mode is present between times t17and t19.

Turning to plot502. For purposes of discussion, assume that operation of the example system prior to time t10was non-transient operation. In that prior non-transient operation, a value indicative of average current was determined, and the slope of the prior signal indicative of instantaneous current was determined, as discussed above. An example (scaled) inductor current is shown in plot502(in dashed line form) for reference. Consistent with the prior operation, starting at time t10the power module102(FIG.3) provides a current-monitor signal being the signal504indicative of average current through the inductor during the last discharge mode. When the charge mode ends at time t11, the example power module102continues to the provide the signal504with goal of providing the signal504through and to the end of the blanking time at time t13. However, in the example ofFIG.5the next charge mode begins at time t12—before the end of the blanking time at t13. Stated otherwise, the PWM signal is again asserted before the end of the blanking time TBLANK. The next charge mode beginning within the blanking time TBLANKis an indication that the system is in transient operation. Thus, the power module102senses that the system is in transient operation and responsive thereto the power module102is designed and constructed to provide a ramp signal506to the voltage regulator110(FIG.1). In one example, the ramp signal506has a slope proportional to an absolute value of a slope of the signal indicative of instantaneous current in the previous discharge mode. The ramp signal506is shown offset from the scaled version of the inductor current to show the correlation, but in practice the ramp signal506may closely match the scaled version of the inductor current.

The power module102continues to provide the example ramp signal506until the end of the charge mode at time t14. The peak value of the ramp signal at time t14may be driven during the discharge mode, but in the example ofFIG.5the next charge mode begins again at time t15, again before the expiration of the blanking time TBLANKat time t16. Thus again, in this example the ramp signal506is driven having a slope proportional to the absolute value of a slope of the signal indicative of instantaneous current in the previous discharge mode (i.e., the discharge mode prior to time t10). The ramp signal506between times t15and t17is again shown offset from the scaled version of the inductor current to show the correlation, but in practice the ramp signal506may closely match the scaled version of the inductor current.

Still referring to plot502, at time t17the charge mode ends, and in this case the discharge modes extends beyond the blanking time TBLANK. Based on the discharge mode having a time duration longer than the blanking time TBLANK, the power module102senses that the transient operation ended, and non-transient operation begins. Thus, the peak value of the ramp signal is driven during the blanking time TBLANKbetween t17and t18. At the end blanking time TBLANK, the power module again drives a signal508indicative of instantaneous current through the inductor, including an example settling portion510, in this example settling from above the instantaneous value rather than below. The discussion now turns to an example electrical circuit to perform the noted functions.

FIG.6shows an example electrical circuit. In particular,FIG.6shows the high-side FET300, the low-side FET302, and the inductor104to orient the circuit to the components previously introduced. Throughout the discussion ofFIG.6are several signals related to the charge mode, the discharge mode, and the blanking time. So as not to unduly complicate the drawing, several signals are defined, but the hardware to implement the signals is not specifically shown so as not to further complicate the figure. The following signals are thus defined: a signal that is asserted during each charge mode, referred to as the TONsignal (e.g., the PWM signal); a signal that is asserted during each discharge mode, referred to as the TOFFsignal (e.g., the logical NOT of the PWM signal); a signal that is asserted during each blanking time, referred to as the TBLANKsignal; a signal that is asserted during each discharge mode starting at the end of the blanking time and de-asserted at the first sample time, referred to as the TSAMPLE1signal; and a signal that is asserted during each discharge mode starting at the end of the blanking time and de-asserted at the second sample time, referred to as the TSAMPLE2signal. The discussion starts with a discharge mode, and initially focuses on the lower half ofFIG.6.

The low-side FET302is associated with a sensing amplifier600defining an inverting input coupled to the switch node by way of a trim resistor, a non-inverting input coupled to the reference voltage, and a sense output. In example cases, the sense amplifier600is designed and constructed to have a gain G of about negative 5, the negative to account for the polarity of the voltage across the low-side FET302, but any suitable gain may be used. The external resistors to implement the gain are not shown so as not to further complicate the figure. An electrically-controlled switch (hereafter just switch602) is coupled between the inputs of the sensing amplifier600. The switch602is closed or conductive during each charge mode, and open or non-conductive during each discharge mode. Thus, in this example the control input of the switch602is coupled to the TONsignal. When the switch602shorts the inputs of the sensing amplifier600during each charge mode, the sensing amplifier600is disabled. When the switch602opens during each discharge mode, the sensing amplifier600is enabled to read the voltage drop across the low-side FET302.

The sense output of the sensing amplifier600is coupled to an electrically-controlled switch (hereafter just switch604). In example systems, the switch604is closed or conductive during each discharge mode starting at the end of the blanking time TBLANK. Hence, an example AND gate606is shown with an output coupled to the control input of switch604, and with the inputs of the AND gate606coupled to the TOFFsignal and the logical NOT of the TBLANKsignal. It follows that, during the discharge mode but before the end of the end of the blanking period TBLANK, the switch604is open or non-conductive. During the discharge mode and after the end of the blanking period TBLANK, the switch604closes and the sense amplifier600drives a sense signal to the capacitor608, where the sense signal is proportional to the voltage drop across the low-side FET302. The settling portion416(ofFIG.4) and the settling portion510(ofFIG.5) may be attributable to the charging time of the capacitor608taking into account the inherent resistance of the switch604.

Skipping for now the amplifier614in the lower middle, the next portion of the example circuit is a transconductance amplifier610on the lower right. The transconductance amplifier610defines a non-inverting input coupled to the first lead of the capacitor608by way of an electrically-controlled switch (hereafter switch612), and an inverting input coupled to the reference voltage (e.g., ground or common). As a transconductance amplifier610, the amplifier output is a current signal having a magnitude proportional to the voltage at the non-inverting input. In various examples, the switch612is closed or conductive during the same periods of time as the switch604(i.e., during the discharge mode after the blanking period), and thus the control input of switch612is coupled to the output of the AND gate606. The transconductance amplifier610reads the voltage on the capacitor608and drives a current-monitor signal (Imon) having an instantaneous magnitude proportional to the instantaneous magnitude of the voltage on the capacitor608(i.e., the downward ramping signal). Stated otherwise, during the discharge mode after the blanking period, the transconductance amplifier610drives the signal indicative of instantaneous current based on the voltage drop across the low-side FET302.

Returning now to the amplifier614in the lower middle. As discussed above, the controller304(FIG.3) makes several measurements during each discharge mode. One of those measurements is a measurement of average current through the inductor during the discharge mode. To that end, the amplifier614defines a non-inverting input coupled to the first lead of the capacitor608by way of a resistor. The amplifier614defines an inverting input coupled to the follower output, and thus the amplifier614is a voltage follower—following the voltage on the capacitor608. Downstream of the amplifier614is another electrically-controlled switch (hereafter switch616). The first lead of switch612is coupled to the follower output of the amplifier614, and the second lead is coupled to an averaging circuit. Inasmuch as the goal is to create the value indicative of average current during the discharge mode, the switch616is closed or conductive during the same periods of time as the switch604(i.e., during the discharge mode after the blanking period), and thus the control input of switch616is coupled to the output of the AND gate606.

In the example ofFIG.6, the averaging circuit is an RC circuit comprising resistor618and capacitor620. The RC circuit is effectively a low-pass filter designed and constructed to determine the average value of the voltage held on the capacitor608. In order for the RC to determine the average, the time constant Tau of the RC circuit may need to be greater than provided by the following formula:

where Tau is the time constant, and FSWMINis the minimum switching frequency. For a minimum switching frequency of 500 kHz, Tau may need to be at least 1 micro-second (μs). Thus, at the end of the discharge mode when the switch616is opened, the voltage on the capacitor620is the value indicative of average current.

Still referring to the lower half ofFIG.6, and now considering a subsequent charge mode during non-transient operation. During the subsequent charge mode in non-transient operation, the voltage held on the capacitor620, being the value indicative of average current during the last discharge mode, is provided to the transconductance amplifier610, and the transconductance amplifier610drives the current-monitor signal proportional to value indicative of average current (i.e., drives the signal indicative of average current). To that end, another electrically-controlled switch (hereafter just switch622) has a first lead coupled to the first lead of the capacitor620, a second lead coupled to the non-inverting input of the transconductance amplifier610, and a control input. Inasmuch as the signal indicative of average current is driven during charge modes, and also driven during the blanking time of a subsequent discharge mode, the control input of the switch622may be coupled to the logical OR of the TONsignal and the TBLANKSignal.

Still referring toFIG.6, and now referring to the upper-half of the drawings. In example systems the controller304, during each discharge mode in non-transient operation, determines the slope of the signal indicative of instantaneous current through the inductor.FIG.6shows, in the upper left-hand corner, an example current-monitor signal during non-transient operation. During the discharge mode, the controller304is designed and constructed to sample, read, or measure two sample values, and from those two sample values generate various signals related to the slope. To that end, the example circuit comprises an electrically-controlled switch (hereafter switch623) having a first lead coupled to a representation of the signal indicative of instantaneous current. In one example, the first lead of the switch is coupled to the first lead of the capacitor608, but the connection is not shown so as not to further complicate the figure. The second lead of the switch622is coupled to the sample capacitor624. The example switch623is conductive during each discharge starting at the end of the blanking period, and the example switch is opened or made non-conductive at the end of the first sample time. Thus, the control input of the switch622is coupled to the TSAMPLE1signal. In this way, the voltage on the sample capacitor624when the switch624opens is representative of the voltage of the signal indicative of instantaneous current at the first sample time.

The example circuit further implements another electrically-controlled switch (hereafter switch628) having a first lead coupled to the representation of the signal indicative of instantaneous current (e.g., coupled to the first lead of the capacitor608). The second lead of the switch628is coupled to a sample capacitor630. The example switch628is conductive during each discharge starting at the end of the blanking period, and the example switch is opened or made non-conductive at the end of the second sample time. Thus, the control input of the switch628is coupled to the TSAMPLE2signal. In this way, the voltage on the sample capacitor630when the switch628opens is representative of the voltage of the signal indicative of instantaneous current at the second sample time.

The example circuit further comprises an amplifier632defining a non-inverting input coupled to the first lead of the sample capacitor624, an inverting input coupled to the first lead of the sample capacitor630, and a difference output. The example amplifier632has a unity gain, but any suitable gain may be used. After the switch628opens, the amplifier632produces a difference voltage having a magnitude proportional to the slope. The difference output of the amplifier632is coupled to sample-and-hold capacitor634by way of an electrically-controlled switch (hereafter switch636). In particular, the example switch636is closed or made conductive momentarily after the second sample period TSAMPLE2such that the sample-and-hold capacitor634holds a voltage indicative of slope throughout the next cycle. For simplicity then, the control input of the switch636is shown coupled to the TONsignal, though the switch636can be opened at any point after the voltage on the sample-and-hold capacitor634settles.

The example controller304uses the slope in at least two ways. The first use of the slope is to correct small errors in the signal indicative of average current generated in each discharge mode, and driven during each charge mode. That is, if the current through the inductor104could be measured throughout the entire discharge mode, then the average current would be given by the following equation:

where IAVGis the average current over the entire discharge mode, and IPEAKis the peak-to-peak current during the discharge mode. However, because of the blanking time, a small error is introduced. In accordance with example embodiments the slope may be used to correct the error in the signal indicative of average current introduced by the blanking time. In particular, the formula for average current during the non-blanking times of the discharge mode may be given by the following formula:

where IBLANK_AVGis the average current during the non-blanking times of the discharge mode, TBLANKis the time duration of the blanking period, L is the inductance of the inductor104, and the remaining variables are as discussed above. It follows that, to correct the small error introduced by the blanking time, the second portion of Equation (3) (i.e., 0.5 TBLANK(VOUT/L)), needs to be added back. However, the example power module102is not provided an indication of the output voltage VOUT; rather, the power module102merely receives the PWM signals and acts accordingly. Moreover, the example power module102is not provided an indication of the value of the inductance of the inductor104. Stated differently, there are no dedicated pins or terminals of the power module102that receive an indication of the setpoint for the output voltage VOUTor an indication of the value of the inductance of the inductor104. However, the slope of the signal indicative of instantaneous current is proportional the ratio of (VOUT/L), and thus in example case the controller304uses the value indicative of slope accordingly.

Still referring to the upper half ofFIG.6. The voltage held on the sample-and-hold capacitor634is applied to another transcondcutance amplifier638which generates a current representative of the error (hereafter the error current). The error current is integrated by the capacitor640coupled across the inputs of yet another transconductance amplifier642. The transconductance amplifier642produces three current signals, where each current has a magnitude proportional to the slope of the signal indicative of instantaneous current. The left-most current source draws current from the capacitor624to make the circuit a closed-loop circuit for stability reasons.

The right-most current source, designated ISLOPEin the figure, generates a current that is summed with the voltage held on the capacitor608in the lower half of the figure. Conceptually, the signal produced by the amplifier600(i.e., the signal indicative of voltage drop across the low-side FET302) is summed, at certain times, with the ISLOPEcurrent to at least partially address the small error introduced by the blanking time. Stated otherwise, the ISLOPEcurrent, representative of the second portion of the Equation (3), is added to at least partially correct the small error in the determination of the value indicative of average current caused by the blanking time.

Inasmuch as the value indicative of average current is created during each discharge mode in non-transient operation, the ISLOPEcurrent is added during periods of time when the average is being determined. Stated otherwise, the ISLOPEcurrent is added during each discharge mode so as affect the value indicative of average current, and the value indicative of average current is driven during the next charge mode as the signal indicative of average current. Thus, in example cases, the switch644, which enables and disables the ISLOPEcurrent, is closed or conductive during discharge modes. Thus, in the example circuit the control input of the switch644is coupled the TOFFsignal.

The discussion now turns to transient operation. Transient operation may be detected by the duration TOFFof the discharge mode being shorter than the duration of the blanking time TBLANK. Stated otherwise, if the example system is still within the blanking period when the next charge mode begins, then the system is in transient operation.FIG.6shows an example circuit to test for the transient operation. In particular, the example controller304includes a D-type flip-flop646. The clock input of the flip-flop646is clocked with the TONsignal. The D input is coupled to the TBLANKsignal. Thus, if the TBLANKsignal is still asserted when the next charge mode begins, the Q output of the flip-flop646is asserted, latching in an indication of the transient operation.

As discussed with respect toFIG.5, when in transient operation, rather than drive the signal indicative of average current, the example system drives a ramp signal designed to closely emulate the actual ramping current. The slope of the current during a charge mode is given by the following formula:

where MCHARGEis slope of the current during the charge mode, VINis the input voltage, and the remaining variables are as defined above. As before, however, the example power module102is not provided an indication of the input voltage VINor the output voltage VOUT. Moreover, the example power module102is not provided an indication of the value of the inductance of the inductor104. Stated differently, there are no dedicated pins or terminals of the power module102that receive an indication of the input voltage VIN, the setpoint for the output voltage VOUT, or an indication of the value of the inductance of the inductor104. It turns out, however, that input voltage VINcan be approximated based on the duty cycle of the PWM signal. And as noted above, the ratio of VOUT/L can be approximated based on the slope of the current in a discharge mode. Thus, it can be mathematically shown that a good approximation of the slope of current signal during charges modes may be given by:

where MAPPROXis an approximated slope of the current during the charge mode, DUTY is the duty cycle of the PWM signal (expressed as a value between zero and one), and the remaining variables are as described above.

Still referring toFIG.6, and in particular the right side of the upper half. The third current produced by the transconductance amplifier642(i.e., the middle source in the figure) feeds a circuit that generates a ramp signal based following Equation (5). That is, the middle current source of the transconductance amplifier642produces a current whose magnitude is proportional to VOUT/L, as discussed above. That current is provided to a set of electrically-controlled switches (hereafter just switches648and650) arranged to implement the (1/DUTY) portion of Equation (5) above. The control input of switch648selectively couples the middle current source to an RC circuit of resistor652and capacitor654. The control input of the switch648is coupled to the logical NOT of the PWM signal (i.e., the TONsignal). The control input of switch650is coupled to the TONsignal. Thus, during TOFFtimes, the switch648is closed or conductive, and the current is enabled to flow the RC circuit. During TONtimes, switch648is open or non-conductive, and the switch650is closed or conductive, draining current from the capacitor654. The result of the circuit is that the capacitor654holds a voltage that is proportional MAPPROXof Equation (5) above. The capacitor654is coupled across the inputs of transconductance amplifier656, which produces a current having a magnitude proportional MAPPROXof Equation (5) above. The current produced by the transconductance amplifier656may be selectively applied to the capacitor608by way of electrically-controlled switch (hereafter just switch658).

In charge modes during transient operation, when the Q output of the flip-flop646is asserted, switch658is closed or conductive. The current having a magnitude proportional to MAPPROXis applied to the capacitor608, producing an upward ramping signal at the output of the amplifier614. In order to apply the upward ramping signal to the transconductance amplifier610, a bypass electrically-controlled switch (hereafter just bypass switch660) bypasses the resistor618and couples the upward ramping signal to the capacitor620and switch622. The control input of the bypass switch660is thus coupled to the Q output of the flip-flop646(as shown by the bubble “B”). It follows that the upward ramping signal is applied to the transconductance amplifier610, and the transconductance amplifier610produces the emulated signal in the form of the ramp signal (e.g., ramp signal506ofFIG.5) having a slope proportional to an absolute value of a slope of the signal indicative of instantaneous current in the last discharge mode. When the transient operation ends, the capacitor620holds the peak value achieved, which is then provided to the transconductance amplifier610(see, e.g., the portion510ofFIG.5decaying away from the peak value achieved).

FIG.7shows a method in accordance with at least some embodiments. In particular, the method starts (block700) and comprises: discharging an inductor of a buck converter using a low-side FET during a discharge mode of a first cycle (block702); providing, during the discharge mode, a signal indicative of instantaneous current to a voltage regulator, the signal indicative of instantaneous current proportional to current through the inductor during at least a portion of the discharge mode (block704); charging the inductor using a high-side FET during a charge mode, the charge mode in a second cycle subsequent to the discharge mode (block706); and providing, during the charge mode, an emulated signal to the voltage regulator, the emulated signal generated based on the current through the inductor in the discharge mode (block708). Thereafter the method ends (block710).

Many of the electrical connections in the drawings are shown as direct couplings having no intervening devices, but not expressly stated as such in the description above. Nevertheless, this paragraph shall serve as antecedent basis in the claims for referencing any electrical connection as “directly coupled” for electrical connections shown in the drawing with no intervening device(s).