Electrical isolation of monolithic circuits using a conductive through-hole in the substrate

A monolithic electronic chip including: a substrate; a first circuit formed on a first circuit portion of the substrate; a second circuit formed on a second circuit portion of the substrate; and at least one conductive impedance tap formed a through-hole in the substrate. The substrate includes first and second opposing surfaces and at least one through-hole extending from the first surface to the second surface. Each of the circuit portions is disposed on one or both of the opposing surfaces. Each conductive impedance tap is coupled to the surface of the through-hole it is formed in to electrically couple the substrate to a reference voltage. The impedance between each circuit and the reference voltage via the conductive impedance tap(s) is less than the crosstalk impedance between the first circuit and the second circuit via the substrate.

FIELD OF THE INVENTION

The present invention concerns electrical isolation of multiple circuits formed in monolithic electronic chips. In particular, the present invention allows for the monolithic production of systems on a chip using a single substrate.

BACKGROUND OF THE INVENTION

The demand for more and more complicated integrated circuits that may be monolithically formed on a single chip is driven by a desire for more compact electronic devices, as well as the potential for simplified post-fabrication assembly and packaging of these devices. Simplifying the assembly and packaging of electronic devices may improve durability and quality, as well as potentially decrease the cost of manufacture for the completed devices.

One difficulty that designers of such systems on a chip often face is ensuring proper electrical isolation between different circuits within these monolithic chips. In multi-chip designs, electrical isolation can be achieved by placing circuits that are likely to experience undesirable levels of crosstalk on separate electrically isolated substrates; however, in system on a chip designs, chip designers have no such luxury.

FIG. 1illustrates this potential issue for a monolithically integrated system on a chip using single substrate100. Circuits102and104represent two circuits that form part of the total system, but which desirably are electrically isolated from one another. For example, circuit102may be a radio frequency (RF) circuit and circuit104may be a digital baseband circuit. If impedance106though substrate100between circuit102and circuit104has a sufficiently high value, for both baseband and RF signals in this example, then these two monolithic circuits may operate without significant crosstalk; however, if impedance106has a low value, then undesirable levels of crosstalk are likely to occur during operation.

Reducing the doping of substrate100and/or increasing the separation distance between circuits102and104may increase the value of impedance106; however, these relatively simple approaches often prove to be undesirable in ever shrinking circuit designs.

T. Blalack et al. describe a number of alternative approaches in ON-CHIP RF ISOLATION TECHNIQUES (IEEE Proceedings of Bipolar/BiCMOS Circuits and Technology Meeting 2002). These alternative methods include separating circuits with trenches, guard rings, shielding, capacitive decoupling and package inductance. In the first of these approaches, the trenches are cut through a low impedance buried layer so that the chip is held together by a significantly higher impedance layer that is not cut by the trenches. The low impedance buried layer is connected to a low impedance AC ground to act as a shield between the circuits. The guard ring and shielding approaches require forming a patterned layer of conductor(s) to reduce crosstalk between the circuits.

The present invention uses a new approach to isolate multiple circuits that are monolithically formed on a single substrate.

SUMMARY OF THE INVENTION

An exemplary embodiment of the present invention is a monolithic electronic chip including: a substrate; a first circuit formed on a first circuit portion of the substrate; a second circuit formed on a second circuit portion of the substrate; and at least one conductive impedance tap formed a through-hole in the substrate. The substrate includes first and second opposing surfaces and at least one through-hole extending from the first surface to the second surface. Each of the circuit portions is disposed on one or both of the opposing surfaces. Each conductive impedance tap is coupled to the surface of the through-hole it is formed in to electrically couple the substrate to a reference voltage. The impedance between the first circuit and the reference voltage via the conductive impedance tap(s) is less than the crosstalk impedance between the first circuit and the second circuit via the substrate. So is the impedance between the second circuit and the reference voltage via the conductive impedance tap(s).

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of the present invention include use of through-holes to provide electrical isolation between separate circuits formed on a single substrate.

FIGS. 2A-2Cillustrate exemplary monolithic electronic chips including two circuits with through-hole electrical isolation according to the present invention. This exemplary monolithic electronic chip includes: substrate100, which has a through-hole, designated201extending from one surface to the other surface of the substrate; first circuit102and second circuit104, which are each formed on at least one of the surfaces of substrate100; and a conductive impedance tap (labeled as element200inFIGS. 2A and 2Band element214inFIG. 2C) formed within the through-hole in substrate100. The conductive impedance tap (200or214) is coupled to the surface of the through-hole to electrically couple substrate100to reference voltage202, which may be a ground reference. The through-hole is positioned and conductive impedance tap is coupled such that both impedance204between first circuit102and reference voltage202via the conductive impedance tap (200or214) and impedance206between second circuit104and reference voltage202via the conductive impedance tap (200or214) is less than crosstalk impedance106(only shown inFIG. 1) between first circuit102and second circuit104via substrate100.

Substrate100may be include a variety of materials and may be formed as a bulk material or may be formed as a multi-layer structure. The material of substrate100may include an n-type semiconductor material or a p-type semiconductor material. Although it may be desirable for substrate100to have a relatively low resistivity so that it also provides a ground path for the circuits, a higher resistivity substrate may be used in the exemplary embodiments of the present invention.

Referring now toFIG. 2B, substrate100is shown separated by dashed line208into first circuit portion210and second circuit portion212. Thus, dashed line208represents a boundary between first circuit portion210and second circuit portion212of the substrate. The through-hole201may desirably be located on or near, this boundary between first circuit portion210and second circuit portion212.FIG. 2Bshows one edge of the through-hole (which is filled by solid conductive impedance tap200) as abutting boundary208, whileFIG. 3illustrates an alternative exemplary embodiment in which a plurality of through-holes and solid conductive impedance taps200, straddle the dashed lines representing the boundaries between different circuits.

The through-hole(s) in substrate100may take a variety of prismatic shapes (including cylinders) with different cross-sections, such as the rectangular cross-section shown inFIG. 2Band the circular cross-sections shown inFIG. 3. Each conductive impedance tap may desirably fill the through-hole in which it formed, as illustrated by solid conductive impedance taps200inFIGS. 2A,2B and3; however, it is also contemplated that a conductive impedance tap may instead be formed as hollow conductive impedance tap214, as shown inFIG. 2C. Although it may be desirable for the conductive impedance tap(s) (200or214) to be formed of metal, other conductive material, such as polysilicon or organic conductors, may be used as well.

In addition to showing hollow conductive impedance tap214,FIG. 2Calso illustrates an exemplary embodiment in which circuit102is formed on one surface of substrate100and circuit104is formed on the other surface. It is also contemplated that one or both circuits102and104may be formed on both surfaces of substrate100.

Circuits102and104may be one of a variety of circuits, such as an RF circuit, an RF detection circuit, a microwave circuit, a microwave detection circuit, a digital baseband circuit, a logic circuit or a signal processing circuit.

FIG. 3illustrates several exemplary embodiments of the present invention. The exemplary monolithic electronic chip ofFIG. 3includes three circuits102,104and300that are electrically isolated from each other using a plurality of through-holes in substrate100, including conductive impedance taps200.

First circuit102is formed on first circuit portion302of substrate100, second circuit104is formed on second circuit portion304of substrate100and third circuit300is formed on third circuit portion306of substrate100. First circuit portion302and second circuit portion304are separated by boundary208. First circuit portion302and third circuit portion306are separated by boundaries208and308. Second circuit portion304and third circuit portion306are separated by boundary310.

In this exemplary embodiment, the impedance between each circuit and the reference voltage via conductive impedance taps200is less than the crosstalk impedance between each pair of circuits via substrate100. A plurality of through-holes200are substantially evenly spaced along each of these boundaries208,308and310to electrically isolate circuits102,104and300. Additional through-holes are arranged around second circuit104such that conductive impedance taps200also form a two-dimensional Faraday cage around this circuit, providing additional electrical isolation between second circuit104and the other two circuits.

It is noted that all conductive impedance taps200inFIG. 3are electrically coupled to a common reference voltage. These conductive impedance taps may also be shorted together either by one or more conductor(s) formed on one or both surface(s) of substrate100, such as conductive strip312, by wire bonds between conductive impedance taps200, or by solder balls or other metal balls used in flip chip technology.

The present invention includes a number of exemplary embodiments of monolithic electronic chips, having multiple electrically isolated circuits. Although the invention is illustrated and described herein with reference to specific embodiments, it is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention. In particular, one skilled in the art may understand that many features of the various specifically illustrated embodiments may be mixed to form additional exemplary monolithic electronic chips also embodied by the present invention.