Heterojunction diode having an increased non-repetitive surge current

A heterojunction diode is provided, including first and second semiconductor layers made of III-N material, the layers being superposed to form a two-dimensional electron gas; an anode and a cathode that are selectively electrically connected to each other by the electron gas; a third semiconductor layer positioned under the gas; a p-doped first semiconductor element contacting the anode the third layer, and forming a separation between the anode and the third layer; and an n-doped second semiconductor element contacting the cathode and the third layer, and forming a separation between the cathode and the third layer, the third layer and the first and second elements forming a p-i-n diode.

The invention relates to heterojunction diodes, and in particular to power diodes having to support a substantially increased transient surge current.

III-N type heterojunction diodes are increasingly used for power applications in order to respond to significant constraints in terms of electric power consumption, voltages and operating currents.

Patent US 2014/231873 discloses a heterojunction diode. This heterojunction diode comprises a superposition of a GaN layer and an AlGaN layer. An electron gas layer is formed at the interface between the AlGaN layer and the GaN layer as a result of spontaneous biasing and piezoelectric biasing. The electron gas layer acts as a channel for the diode and permits a very high density current with very low conduction resistance. Such a diode also has a very low threshold voltage, allowing electric power consumption to be reduced when it is directly biased.

A Schottky contact is formed on the AlGaN layer to form an anode. An ohmic contact is formed through the AlGaN layer and is in contact both with the AlGaN layer and the GaN layer to form a cathode. A passivation layer made of SiN is formed on the AlGaN layer between the anode and the cathode. A P-doped GaN layer is formed on the AlGaN layer. It is shaped so that it is laterally delimited by the anode and the passivation layer and it is covered by the anode and the passivation layer. This GaN layer is intended to reduce the leakage currents between the anode and the cathode in the off-state, such leakage currents can occur at the interface between the passivation layer and the AlGaN layer.

The power diodes particularly have to handle a non-repetitive surge current specification, denoted using the acronym IFSM, without degrading performance. This value preferably must be approximately ten times the rating of the forward current of the diode. The electron gas layer has limitations in terms of maximum supported current, limiting the amplitude of the IFSM current relative to the rating.

Therefore, a requirement exists for a power diode having a relatively high IFSM surge current relative to its rating and for which the structure is relatively easy to produce.

Document JP 2015 198175, with reference toFIG. 7thereof, discloses a heterojunction diode comprising:a first semi-conductive layer31made of GaN;a second semi-conductive layer14made of AlGaN superposed on the first layer to form an electron gas A;an anode35A and a cathode35C selectively connected to each other by means of the electron gas layer;a third semi-conductive layer31positioned under the electron gas layer and under the first semi-conductive layer31;a first P-doped semi-conductor element33in contact with the anode35A;a second N-doped semi-conductor element34in contact with the cathode35C and forming a separation between the cathode35C and the third layer31;the third semi-conductive layer31, the second semi-conductor element34and part of the first semi-conductive layer32interposed between the first semi-conductor element33and the third semi-conductive layer31forming a PIN diode.

Such a diode has disadvantages. In order to increase the current in the on-state, the document uses a high concentration of dopants in the third semi-conductive layer31, to the detriment of the breakdown voltage resistance between the anode and the cathode. For high voltages, in practice this means that the thickness of the part of the first semi-conductive layer32that is interposed between the semi-conductor element33and the semi-conductive layer31is substantial.

Document JP 2012 028409 discloses:a heterojunction diode comprising:a first layer made of GaN;a second layer made of AlGaN superposed on the first layer to form an electron gas;an anode and a cathode selectively connected to each other by means of the electron gas layer;a first P-doped semi-conductor element in contact with the anode;a second N-doped semi-conductor element in contact with the cathode;a subjacent PIN diode formed with the semi-conductor elements.

The aim of the invention is to overcome one or more of these disadvantages. Therefore, the invention relates to a heterojunction diode as defined in appended claim1.

The invention further relates to the variations defined in the appended dependent claims. A person skilled in the art will understand that each of the features of these variations can be combined independently of the features of claim1, without as such forming an intermediate generalization.

The invention further relates to a method for manufacturing a heterojunction diode as defined in the appended claims.

The invention proposes forming a PIN diode under a heterojunction diode, between the anode and the cathode of this heterojunction diode. The structure that is thus obtained both affords the benefit of a high current density for the heterojunction diode in the on-state and allows additional conduction by the PIN diode in the event of a transient surge.

FIG. 1is a section view of an integrated circuit including a diode structure1according to an example of a first embodiment of the invention. In the example shown, two heterojunction diodes are formed with a common anode. The diode structure1comprises:a substrate11. The substrate11can be an insulator or an intrinsic or doped silicon type semi-conductor. The substrate11can be of the mesh orientation silicon type (111), for example. The substrate11also particularly can be made of silicon carbide or of sapphire. The substrate11can be approximately 650 μm thick, typically included in a range of 400 μm and 2 mm;possibly an adaptation layer12disposed on the substrate11. The adaptation layer12, which is deposited on the substrate11in a manner per se known, acts as an intermediary between this substrate and the semi-conductive layer13described hereafter, or another semi-conductive layer in the absence of the layer13. The adaptation layer12allows a mesh adaptation between the substrate11and this semi-conductive layer13. The adaptation layer12typically can be made of aluminum nitride for a semi-conductive layer13made of GaN;possibly a semi-conductive buffer layer13(for example, of the III-V type, for example, made of group III element nitride, typically of unintentionally doped GaN), which in this case is disposed on the adaptation layer12. An unintentionally doped semi-conductor normally denotes a semi-conductor in which impurities have not been introduced intentionally. Such a semi-conductor typically has an impurities concentration that is at most equal to 1015cm−3. Doped GaN also can be used that includes high concentrations of carbon (for example, greater than 1018cm−3with a view to increasing the electric insulation properties of this layer);a semi-conductive layer14(made of GaN, which is the particular case of III-N type material) with reduced doping. The layer14in this case is formed on the semi-conductive buffer layer13. The layer14is N-doped with a concentration that is at most equal to 4*1016cm−3, with this concentration advantageously being at least equal to 5*1015cm−3. The semi-conductive layer14typically is at least 100 nm thick, preferably at least 150 nm thick;an unintentionally doped semi-conductive layer15made of GaN. The semi-conductive layer15in this case is formed on the semi-conductive layer14. The semi-conductive layer15typically is 100 nm thick;a semi-conductive layer17made of III-N material (for example, a III-N type ternary alloy, for example, AlGaN, in particular AlGaN having a molar fraction of aluminum included in a range of 20% and 30%). The semi-conductive layer17in this case is formed on the semi-conductive layer15. The semi-conductive layer comprises a higher forbidden band than that of the semi-conductive layer15made of AlGaN, InAlN or AlN, for example. The semi-conductive layer17typically is 25 nm thick, included in a range of 10 and 40 nm, for example. The semi-conductive layers15and17are superposed in a manner per se known to form an electron gas layer16at the interface or in the vicinity of the interface between these layers15and17. The electron gas layer16is thus formed above the semi-conductive layer14;a P-doped semi-conductor element19(for example, a III-N type alloy, for example, GaN or AlGaN, or polysilicon). The concentration of P-dopants in this semi-conductor element19advantageously is included in a range of 5*1017cm−3and 1020cm−3. The highest concentrations of P-dopant in particular can be obtained for a semi-conductor element19made of polysilicon. The semi-conductor element19is in contact with the layer14;semi-conductor elements31and32disposed either side of the semi-conductor element19at a distance from this semi-conductor element19. The semi-conductor elements31and32are N-doped. The concentration of N-dopants of the semi-conductor elements31and32advantageously is included in a range of 5*1017cm−3and 1020cm−3. The semi-conductor elements31and32are in contact with the layer14. The semi-conductor elements31and32are formed, for example, by implanting N-dopant in the layers15and17made of silicon, for example. The elements31and32also can be made of N-doped polysilicon. The highest concentrations of N-dopant in particular can be obtained for semi-conductor elements31and32made of polysilicon;a metal anode23in contact with the semi-conductor element19. The semi-conductor element19forms a separation between the layer14and the anode23. In the example, the metal anode23covers the semi-conductor element19. The metal anode23comprises a central portion230covering the semi-conductor element19. The anode23has a laterally projecting portion231. The portion231is projecting relative to the semi-conductor element19toward the cathode21. The projecting portion231passes through the passivation layer18and forms a Schottky contact232with the layer17. The projecting portion231has an extension233toward the anode21, beyond the Schottky contact232, overhanging the passivation layer18.

The central portion230and the projecting portion231of the anode23can be made of two different materials. The portion231is configured to form a Schottky contact with the layer17, the central portion preferably forming an ohmic contact at the interface with the semi-conductor element19. The materials for the central portion230and/or for the projecting portion231are selected from nickel, palladium, gold, TiN, platinum or a superposition of layers of at least two of these materials, for example. If a high work function is desired for part of the anode23, the selection of nickel allows a good compromise to be obtained between its cost and the level of the work function that it is able to obtain. For a P-doped semi-conductor element19made of GaN, a central portion230of the anode23with a high work function is sought, for example. For a P-doped semi-conductor element19made of polysilicon, a central portion230of the anode23can be used with a lower work function, obtained by silicidation and TiN deposition, for example;metal cathodes21and22, respectively in contact with the semi-conductor elements31and32. The metal cathodes21and22form ohmic contacts with the semi-conductor elements31and32, respectively. The semi-conductor elements31and32form a separation between the layer14and the cathodes21and22, respectively. The cathodes21and22are disposed either side of the anode23at a distance from this anode23. The cathodes21and22are intended, in a manner per se known, to be selectively connected to the anode23by means of the electron gas layer16, as a function of the potentials that are applied thereto. The metal cathodes21and22can be formed, in a manner per se known, by aluminum and titanium, aluminum and tantalum multilayer films. In the example shown inFIG. 14(applicable to all the embodiments), the metal cathodes21and22form an overlap on the layer17;advantageously, a passivation layer18(for example, made of silicon nitride, of SiO2or of Al2O3). This passivation layer18typically is at least 100 nm thick, produced with one or more superposed layers. The passivation layer18is formed on the semi-conductive layer17. The passivation layer18forms a protection for the layer17and an electric insulation between the anode23and the cathodes21and22.

Circuits, not shown, selectively apply electric biasing to the cathodes21,22and to the anode23. The dimensions of the various elements and layers are only shown schematically, their dimensions and structures can significantly differ from the illustration ofFIG. 1.

The diode structure1ofFIG. 1forms a circuit4, schematically shown inFIG. 3, between the anode23and the cathode21, on the one hand, and between the anode23and the cathode22, on the other hand. The circuit4comprises a Schottky heterojunction diode41, on the one hand, and a PIN diode42, on the other hand, connected in parallel (common anodes and cathodes).

A heterojunction diode41is formed between the anode23and the cathode21. In the absence of biasing on the anode23and on the cathode21, the diode41that is formed is in the off-state. Indeed, the P-doped semi-conductor element19and the Schottky contact232generate a depleted zone161at the interface between the layers15and17, in the vicinity of the element19and directly below the Schottky contact232. The electron gas layer16is thus interrupted before arriving below the Schottky contact232. An off-state heterojunction diode is thus formed between the Schottky contact232and the cathode21, through the element31, the electron gas layer16and the layers15and17. With the application of a potential difference between the cathode21and the anode23that is greater than its threshold voltage, the electron gas layer16is reconstituted directly below the Schottky contact232. The diode41that is formed is then in the on-state, with electric conduction through the element31, the electron gas layer16and the layer17, as shown by the dotted arrow schematically representing the current in the on-state. The on-state of the heterojunction diode41is obtained, in a manner per se known, with a relatively low potential difference between the anode23and the cathode21(for example, a threshold voltage of approximately 0.5 V), allowing the potential drop and losses to be limited in this diode41in the on-state.

A PIN diode42is formed between the anode23and the cathode21. The P-doped zone of the PIN diode42is formed by the element19. The N-doped zone of the PIN diode42is formed by the element31. The zone, called intrinsic zone, of the PIN diode42is formed by the layer14(weakly n-doped) interposed between the elements19and31. With the application of a suitable potential difference between the cathode21and the anode23, this diode42is brought to the on-state. The PIN diode42then provides electric conduction by means of the element19, the layer14and the element31, as shown by the electron current represented by the dashed line arrow inFIG. 1. With a PIN diode ideally being bipolar, a hole current also exists in the opposite direction. The potential difference to be applied between the cathode21and the anode23is greater than the threshold voltage of the heterojunction diode41. Thus, during a transient current surge, the PIN diode42that is formed provides a second conduction channel physically separated from that of the heterojunction diode41. The diode structure1that is thus formed consequently allows a transient surge current to be obtained that is significantly greater than the nominal current of the heterojunction diode41.

As previously described, the layer14made of GaN has a concentration of dopants at most equal to 4*1016cm−3. Such a concentration of dopants avoids a breakdown of this layer14almost independently of its length (anode-cathode length), for potential differences between the anode and the cathode of several hundred volts, typically up to 2,000 V. The concentration of dopants in the layer14is less than the concentration of dopants in the semi-conductor element19and the concentration of dopants in the semi-conductor elements31or32. The layer14advantageously has a concentration of dopants at least equal to 5*1016cm−3, particularly if this layer14is made of GaN. Such a concentration of dopants allows electric conduction in the PIN diode42to be promoted when it is in the on-state.

In the example shown inFIG. 1, a channel35is arranged through the layers15and17. The bottom of the channel35is delimited by the layer14, with the lateral walls and the bottom of the channel35being covered by the semi-conductor element19, so that the semi-conductor element19is in contact with the layer14in the bottom of the channel35. The bottom of the element19is intended to form the P-doped zone of the PIN diode42. The sides (optional) of the element19in contact with the walls of the channel35in this case are advantageously arranged to deplete part of the interface between the layers15and17. In this case, the height of the sides of the element19is at least equal to the sum of the thicknesses of the layers15,17and18(typically greater than 200 nm).

The width of the semi-conductor element19is designed as a function of the transient surge current intended to be conducted through the PIN diode42brought to the on-state. This width typically can be included in a range of 1 and 5 μm for a power diode structure1. The width of the semi-conductor element19advantageously will be limited, in order to maintain a sufficient width for a projecting portion231, with this projecting portion being intended to conduct the current of the heterojunction diode41in the on-state, during normal operation.

The anode23in this case comprises an extension233toward the cathode21, beyond the Schottky contact232. This extension233overhangs the passivation layer18and allows the range of the electric field applied by the anode23at the interface between the layers15and17to be increased, when the diode41is biased in the on-state. In order to reduce the risks of breakdown of the passivation layer18, the thickness of the layer18advantageously increases under the extension233toward the cathode21. The extension233and the subjacent layer18in this case are step-shaped toward the cathode21. Such a configuration allows the risks of breakdown of the layer18to be limited for high voltages.

The width of the Schottky contact232is designed in a manner per se known to allow the passage of the nominal current of the diode41in the on-state.

FIG. 2is a section view of a diode structure1according to an example of a second embodiment of the invention. As with the structure ofFIG. 1, two heterojunction diodes are formed with a common anode.

The diode structure1ofFIG. 2comprises the following elements, with a structure and a composition similar to that of the first embodiment and which therefore will not be described again:a substrate11;an adaptation layer12;a semi-conductive layer13;a semi-conductive layer14;a semi-conductive layer15;a semi-conductive layer17;an electron gas layer16;a semi-conductor element19;semi-conductor elements31and32;cathodes21and22;a channel35arranged through the layers15and17.

In the second embodiment, the diode structure1also comprises an anode23in contact with the semi-conductor element19. The anode23also covers the semi-conductor element19. The metal anode23comprises a central portion230covering the semi-conductor element19. The anode23also has a laterally projecting portion231. The portion231projects relative to the semi-conductor element19toward the cathode21. The projecting portion231passes through a passivation layer18. The projecting portion231forms an ohmic or (preferably) Schottky contact234passing through the passivation layer to form a contact with the layer17.

The central portion230and the projecting portion231of the anode23can be made of two different materials, as shown herein. The materials for the central portion230and/or the projecting portion231are selected, for example, from aluminum, titanium, nickel or from a superposition of layers of these materials. The previously described criteria for selecting materials for the central and projecting portions of the anode23are also applicable to this embodiment. The projecting portion231has an extension235toward the anode21, beyond the ohmic contact234. The extension235overhangs a P-doped semi-conductor element191, typically made of the same material as the semi-conductor element19. The semi-conductor element191in this case is positioned between the ohmic contact234and the cathode21. The semi-conductor element191is in contact with the layer17.

A heterojunction diode41(with reference toFIG. 3) in this case is also formed between the anode23and the cathode21. In the absence of biasing on the anode23and on the cathode21, the diode41that is formed is in the off-state. Indeed, the P-doped semi-conductor element191generates a depleted zone163at the interface between the layers15and17, directly below this element191. The electron gas layer16is thus interrupted before arriving below the ohmic contact234. The P-doped semi-conductor element19also generates a depleted zone162at the interface between the layers15and17. An off-state heterojunction diode is thus formed between the contact234and the cathode21, through the element31, the electron gas layer16and the layers15and17. With the application of a potential difference between the cathode21and the anode23that is greater than its threshold voltage, the electron gas layer16is reconstituted directly below the semi-conductor element191. The diode41that is formed is then in the on-state, with electric conduction through the element31, the electron gas layer16and the layer17, as shown by the dotted arrow schematically showing the current in the on-state. The on-state of the heterojunction diode41is obtained in a manner per se known with a relatively low potential difference between the anode23and the cathode21(for example, a threshold voltage of approximately 0.5 V), allowing the potential drop and losses to be limited in this diode41in the on-state.

A PIN diode42is formed between the anode23and the cathode21and has an identical structure to that described with reference toFIG. 1. The potential difference to be applied between the cathode21and the anode23is greater than the threshold voltage of the heterojunction diode41. Thus, as with the first embodiment, during a transient current surge, the PIN diode42that is formed provides a second conduction channel physically separated from that of the heterojunction diode41. The diode structure1that is thus formed consequently allows a transient surge current to be obtained that is significantly greater than the nominal current of the heterojunction diode41.

Circuits, not shown, selectively apply electric biasing to the cathodes21,22and to the cathode23.

The width of the contact234is designed in a manner per se known to allow passage of the nominal current of the diode41in the on-state.

FIGS. 4 to 13are section views of various steps of an example of a method for manufacturing a diode structure1according to the first embodiment.

InFIG. 4, a wafer is supplied comprising a substrate11, overlaid with an adaptation layer12, overlaid with a semi-conductive buffer layer13, overlaid with a reduced-doped semi-conductive layer14made of III-N material, overlaid with a semi-conductive layer15made of III-N material, overlaid with a semi-conductive layer17made of III-N material in order to form, in a manner per se known, an electron gas layer16at the interface between these layers15and17. The layers11to17can have a composition and dimensions as previously described. The semi-conductor elements31and32are arranged at a distance from each other. The semi-conductor elements31and32each extend depthwise from the surface of the layer17up to contact with the layer14. The semi-conductor elements31and32are in lateral contact with the layers15and17and with the electron gas layer16.

The semi-conductor elements31and32can be produced, for example, by implanting N-dopant in the layers15and17, by silicon implantation, for example. The implantation of the silicon can be followed by a step of dopant activation annealing, in a manner per se known. The semi-conductor elements31and32also can be produced by etching, then depositing a layer of polysilicon, with N-doping. The semi-conductor elements31and32also can be produced following a step of epitaxy growth of an N-doped semi-conductor on the layer14.

FIG. 5shows the formation of a full slice passivation layer18. This formation is produced, for example, by full slice deposition of an insulating layer such as SiN. The aforementioned step of activation annealing advantageously will be carried out following the formation of the passivation layer18.

FIG. 6shows the removal of the passivation layer18directly above the semi-conductor elements31and32, so as to arrange clear zones33and34granting access to the upper faces of the semi-conductor elements31and32, respectively. In order to form cathodes21and22overlapping the layer17, as previously described, the removal of the passivation layer18can laterally exceed the semi-conductor elements31and32. The zones33and34are, for example, formed by steps of photolithography, then of etching the passivation layer18to clear access to the upper faces of the semi-conductor elements31and32, then of removing the photolithography mask.

FIG. 7shows the formation of the cathodes21and22in ohmic contact with the semi-conductor elements31and32, respectively. The cathodes21and22in this case comprise, in a manner per se known, an overlap on the passivation layer18. The cathodes21and22remain electrically insulated by means of the passivation layer18. The formation of the cathodes21and22comprises, for example, a step of full slice metal deposition, followed by a step of photolithography, followed by a step of etching the pattern of the cathodes21and22, followed by a step of removing the photolithography mask.

FIG. 8shows the formation of a channel35between the cathodes21and22, at a distance from the cathodes21and22. The channel35is formed through the layers18,17and15until the layer14is revealed. The formation of the channel35comprises, for example, a step of photolithography, followed by etching of the channel35, followed by the removal of the photolithography mask. The channel35advantageously has lateral walls that are inclined relative to the vertical.

FIG. 9shows the full slice formation of a layer10of a III-N type P-doped semi-conductor material. The formation of the layer10is carried out, for example, by epitaxy growth, for example, by epitaxy growth of a P-doped GaN. Magnesium particularly can be used as P-dopant.

FIG. 10shows the shaping of the P-doped semi-conductor element19. The shaping of the element19can, for example, comprise a step of photolithography, followed by etching of the element19, followed by the removal of the photolithography mask. In the configuration shown, the element19comprises lateral parts overhanging respective edges of the passivation layer18.

FIG. 11shows the formation of a central portion230of the anode. To this end, a metal layer is deposited that is configured to form an ohmic contact with the semi-conductor element19. This deposition typically is carried out with a full slice, followed by a step of photolithography and of etching to define the shape of the central portion230. The deposit therefore is only maintained on the channel35to obtain a central portion230covering the main part of the element19, but the deposit is removed elsewhere, particularly to reveal the layer18.

FIG. 12shows the formation of the openings37and38through the passivation layer18until the layer17is revealed through these openings37and38. The openings37and38are arranged between the element19and the cathodes21and22, respectively. In this case, the openings37and38are adjoined to the element19. Part of the passivation layer18is preserved under the lateral parts of the element19. The formation of the openings37and38comprises, for example, a step of photolithography, followed by etching of the passivation layer18until a portion of the layer17is revealed, followed by the removal of the photolithography mask.

FIG. 13shows the formation of the projecting portions231of the anode23. The projecting portions231in this case are formed as one-piece with a metal deposit covering the central portion230. Electric contact is thus formed between the projecting portions231and the central portion230. The projecting portions231are laterally projecting toward the cathodes21and22, respectively. The projecting portions231each comprise a Schottky contact232in contact with the layer17through the openings37and38. The projecting portions231in this case comprise an overlap233beyond the Schottky contacts232, above the passivation layer18. An MIS type electrode is thus formed by this overlap233above the passivation layer18. Of course, the anode23remains insulated from the cathodes21and22by means of the passivation layer18. The material for forming a Schottky contact232can be selected as previously described.

The formation of the projecting portions231is carried out, for example, by full slice deposition of a metal forming a Schottky contact with the layer17, followed by photolithography and etching of the metal deposit around the anode23, followed by the removal of the photolithography mask.

By way of a variation of this manufacturing method, a passivation layer18can be produced with a stepped zone covered by an overlap233of the projecting portion231of the anode23, as shown inFIG. 14.

FIGS. 15 and 16show a variation of the previously described manufacturing method. This variation of the manufacturing method is implemented on the basis of the step shown inFIG. 10. On completion of the step ofFIG. 10, the semi-conductor element19that is formed is made of polysilicon or amorphous silicon.FIG. 15shows the full slice deposition of a layer239of Ni+TiN.

FIG. 16shows N2annealing so as to cause the Ni of the layer239to react with the silicon of the semi-conductor element19. In line with the element19, the layer239is converted to NiSi. The remainder of the layer239that has not reacted (and in particular the entire part of the layer139that does not cover the element19) was then selectively withdrawn by wet processing, for example.

Advantageously, the passivation layer18can include a plurality of superposed layers made of different materials, for example, a superposition of layers of SiN/SiO2. Through selective etching, the various layers of the passivation layer18can be successively opened, to form a step-shape as previously described. A single metallization then can be produced to form the contact232and the extensions233.

The method described with reference toFIGS. 4 to 13also can be modified as follows. In this case, the steps implemented with reference toFIGS. 4 and 5can be reproduced. A channel35is then formed between the cathodes21and22, at a distance from the cathodes21and22, as shown inFIG. 17. The channel35is formed through the layers18,17and15until the layer14is revealed. The formation of the channel35comprises, for example, a step of photolithography, followed by etching of the channel35, followed by the removal of the photolithography mask. The channel35advantageously has lateral walls inclined relative to the vertical.

FIG. 18shows the full slice formation of a layer10of a III-N type P-doped semi-conductor material. The formation of the layer10is carried out, for example, by epitaxy growth, for example, by epitaxy growth of a P-doped GaN. Magnesium particularly can be used as P-type dopant.

FIG. 19shows the shaping of the P-doped semi-conductor element19. The shaping of the element19can comprise, for example, a step of photolithography, followed by etching of the element19, followed by the removal of the photolithography mask. In the configuration shown, the element19comprises lateral parts overhanging respective edges of the passivation layer18.

FIG. 20shows the removal of the passivation layer18directly above the semi-conductor elements31and32, so as to arrange clear zones33and34granting access to the upper faces of the semi-conductor elements31and32, respectively.

In order to form cathodes21and22overlapping on the layer17, as previously described, the removal of the passivation layer18can laterally exceed the semi-conductor elements31and32. The zones33and34are formed, for example, by steps of photolithography, then of etching the passivation layer18to clear access to the upper faces of the semi-conductor elements31and32, then of removing the photolithography mask.

FIG. 21shows the formation of the cathodes21and22in ohmic contact with the semi-conductor elements31and32, respectively. The cathodes21and22in this case comprise, in a manner per se known, an overlap on the passivation layer18. The cathodes21and22remain electrically insulated by means of the passivation layer18. The formation of the cathodes21and22comprises, for example, a step of full slice metal deposition, followed by a step of photolithography, followed by a step of etching the pattern of the cathodes21and22, followed by a step of removing the photolithography mask.

The method can be continued as described with reference toFIGS. 11 to 14.

In the examples shown, the layers15and17are in direct contact in order to form an electron gas layer16at their interface. In a manner per se known, an intermediate layer also can be interposed, for example, an AlN layer when the layer15is made of GaN and the layer17is made of AlGaN. Such an AlN layer typically is 1 nm thick.