SEMICONDUCTOR DEVICE STRUCTURE WITH BARRIER LAYER AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor device structure is provided. The method includes removing a portion of a dielectric layer to form a trench in the dielectric layer. The method includes forming a barrier layer in the trench. The method includes forming a seed layer in the trench and over the barrier layer. The seed layer is doped with manganese. The method includes annealing the seed layer in a first process gas including a first hydrogen gas. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the seed layer to the barrier layer during the annealing of the seed layer in the first process gas.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs.

However, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

DETAILED DESCRIPTION

The term “substantially” in the description, such as in “substantially flat” or in “substantially coplanar”, etc., will be understood by the person skilled in the art. In some embodiments the adjective substantially may be removed. Where applicable, the term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. The term “substantially” may be varied in different technologies and be in the deviation range understood by the skilled in the art. For example, the term “substantially” may also relate to 90% of what is specified or higher, such as 95% of what is specified or higher, especially 99% of what is specified or higher, including 100% of what is specified, though the present invention is not limited thereto. Furthermore, terms such as “substantially parallel” or “substantially perpendicular” may be interpreted as not to exclude insignificant deviation from the specified arrangement and may include for example deviations of up to 10°. The word “substantially” does not exclude “completely” e.g. a composition which is “substantially free” from Y may be completely free from Y.

The term “about” may be varied in different technologies and be in the deviation range understood by the skilled in the art. The term “about” in conjunction with a specific distance or size is to be interpreted so as not to exclude insignificant deviation from the specified distance or size. For example. the term “about” may include deviations of up to 10% of what is specified, though the present invention is not limited thereto. The term “about” in relation to a numerical value x may mean × ±5 or 10% of what is specified, though the present invention is not limited thereto.

FIGS.1A-1Kare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown inFIG.1A. a substrate110is provided, in accordance with some embodiments. The substrate110includes, for example, a semiconductor substrate. The substrate110includes, for example, a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer.

In some embodiments, the substrate110is made of an elementary semiconductor material including silicon or germanium in a single crystal structure, a polycrystal structure, or an amorphous structure. In some other embodiments, the substrate110is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide. an alloy semiconductor, such as SiGe or GaAsP, or a combination thereof. The substrate110may also include multi-layer semiconductors. semiconductor on insulator (SOI) (such as silicon on insulator or germanium on insulator), or a combination thereof.

As shown inFIG.1A, various device elements120are formed over and/or in the substrate110, in accordance with some embodiments. For the sake of simplicity and clarity,FIG.1Aonly shows one of the device elements120, in accordance with some embodiments.

Examples of the various device elements120include active devices, passive devices, other suitable elements (e.g., conductive lines), or a combination thereof. The active devices may include transistors or diodes formed at a surface of the substrate110. The passive devices include resistors. capacitors. or other suitable passive devices.

Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form the various device elements120. The FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in the substrate110. The isolation features are used to surround active regions and electrically isolate the device elements120formed in and/or over the substrate110in the active regions. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.

As shown inFIG.1A, a dielectric layer130is then deposited over the substrate110and the device elements120, in accordance with some embodiments. The dielectric layer130is made of any suitable dielectric material, such as silicon oxide, silicon oxynitride, SiOC, SiOCN, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), hydrogenated silicon oxycarbide (SiCO:H), a low-k material, a porous dielectric material, or a combination thereof, in accordance with some embodiments.

The dielectric layer130is deposited by any suitable process, such as a chemical vapor deposition (CVD) process, a high density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, a sputtering process. or a combination thereof, in accordance with some embodiments. In some embodiments (not shown), an etch stop layer is deposited over the substrate110and the device elements120, and the dielectric layer130is deposited over the etch stop layer, in accordance with some embodiments.

As shown inFIG.1A, a mask layer140is formed over the dielectric layer130, in accordance with some embodiments. The mask layer140is made of a material different from the material of the dielectric layer130, in accordance with some embodiments.

The mask layer140is made of nitrides (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride). TEOS (tetra-ethyl-ortho-silane), tungsten carbide (WC), TiN, or a nitrogen free anti-reflective coating (NFARC) material, in accordance with some embodiments. The mask layer140is a combination of 1 to 5 layers or more, in accordance with some embodiments. The mask layer140is formed by any suitable process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process. or a combination thereof, in accordance with some embodiments.

As shown inFIG.1A, a mask layer M1is formed over the mask layer140, in accordance with some embodiments. The mask layer M1has trenches OP1and OP2. in accordance with some embodiments. The trenches OP1and OP2expose portions of the mask layer140. in accordance with some embodiments.

The mask layer M1is made of a photoresist material or another suitable material, which is different from the material of the mask layer140, in accordance with some embodiments. The mask layer M1is a combination of 1 to 5 layers or more, in accordance with some embodiments. The number of the layers depends on the following etching processes. The mask layer M1is formed using a photolithography process, in accordance with some embodiments.

As shown inFIG.1B, the exposed portions of the mask layer140are removed through the trenches OP1and OP2of the mask layer M1to form trenches142and144in the mask layer140, in accordance with some embodiments. The trenches142and144expose portions of the dielectric layer130, in accordance with some embodiments. The removal process includes an etching process, such as a dry etching process (e.g., a plasma etching process), in accordance with some embodiments.

As shown inFIG.1C, the mask layer M1is removed, in accordance with some embodiments. The removal process includes an etching process, such as a dry etching process (e.g., a plasma etching process) and/or a wet etching process, in accordance with some embodiments.

As shown inFIG.1D, portions of the dielectric layer130are removed through the trenches142and144of the mask layer140, in accordance with some embodiments. The removal process forms trenches132and134in the dielectric layer130, in accordance with some embodiments.

The removal process also etches the edges of the mask layer140, and therefore the edges of the mask layer140are rounded, in accordance with some embodiments. The removal process includes an etching process, such as a dry etching process (e.g., a plasma etching process), in accordance with some embodiments.

FIG.1E-1is an enlarged view of a portion A of the semiconductor device structure ofFIG.1E, in accordance with some embodiments. As shown inFIGS.1E and1E-1, a barrier layer150is formed in the trenches132and134of the dielectric layer130and the trenches142and144of the mask layer140, in accordance with some embodiments.

The barrier layer150is conformally formed over the mask layer140, inner walls132aand a bottom surface132bof the trench132. and inner walls134aand a bottom surface134bof the trench134, in accordance with some embodiments. Therefore, the barrier layer150has trenches151and153respectively in the trenches132and134, in accordance with some embodiments.

The barrier layer150is configured to block the diffusion of metal atoms of a conductive layer subsequently formed on the barrier layer150, in accordance with some embodiments. The barrier layer150has layers152and154. in accordance with some embodiments.

The layer154is over the layer152, in accordance with some embodiments. The layer152has a thickness T152 ranging from about 5 Å to about 40 Å, in accordance with some embodiments. The layer154has a thickness T154 ranging from about 5 Å to about 80 Å, in accordance with some embodiments.

The formation of the barrier layer150includes depositing the layer152in the trenches132and134; and depositing the layer154over the layer152, in accordance with some embodiments. The layers152and154are made of different materials, in accordance with some embodiments.

In some embodiments, the barrier layer150includes tantalum, tantalum nitrides, cobalt (Co), ruthenium (Ru), titanium, titanium nitrides, or other suitable materials. In some embodiments, the layer152is made of tantalum nitrides, and the layer154is made of cobalt, ruthenium, tantalum, or titanium.

In some other embodiments (not shown), the barrier layer150further includes one or more layers over the layer154, and the one or more layers are made of cobalt, ruthenium, tantalum, or titanium. The one or more layers and the layer154are made of different materials, in accordance with some embodiments. In some embodiments, the barrier layer150is formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or another suitable process.

Thereafter, as shown inFIG.1F, a seed layer160is formed over the barrier layer150and in the trenches151and153of the barrier layer150, in accordance with some embodiments. The seed layer160is doped with manganese170, in accordance with some embodiments.

In some embodiments, an atomic concentration of the manganese170in the seed layer160ranges from about 0.5 % to about 2.5 %. The manganese170is able to improve the adhesion between the seed layer160and the barrier layer150, in accordance with some embodiments.

The seed layer160includes copper, copper alloys, cobalt (Co), ruthenium (Ru) or other suitable conductive materials, in accordance with some embodiments. In some embodiments, the seed layer160is formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an electroless plating process, or another suitable process. The physical vapor deposition process includes a plasma deposition process, in accordance with some embodiments.

FIG.1G-1is an enlarged view of a portion A of the semiconductor device structure ofFIG.1G, in accordance with some embodiments. As shown inFIGS.1G and1G-1, the seed layer160is annealed in a process gas, in accordance with some embodiments.

The process gas includes a hydrogen gas, in accordance with some embodiments. The process gas has a high hydrogen volume concentration, in accordance with some embodiments. In some embodiments, the process gas further includes nitrogen or an inert gas.

The manganese170diffuses from the seed layer160to the barrier layer150during the annealing of the seed layer160in the process gas, in accordance with some embodiments. In the process gas with the high hydrogen volume concentration, the manganese170tends to move to the barrier layer150. in accordance with some embodiments.

The manganese170in the barrier layer150improves electromigration resistance of the barrier layer150, in accordance with some embodiments. After the seed layer160is annealed, an atomic concentration of the manganese170in the barrier layer150is greater than an atomic concentration of the manganese170in the seed layer160. in accordance with some embodiments.

As shown inFIGS.1F and1G, the seed layer160is reflowed and therefore upper portions161of the seed layer160partially flow downwardly during the annealing of the seed layer160in the process gas, in accordance with some embodiments. Therefore, the upper portions161become thinner and the lower portions162of the seed layer160become thicker, in accordance with some embodiments.

The hydrogen tends to react with the residue in or on the seed layer160to form volatile species that can be removed from the chamber, which may form voids in the seed layer160, in accordance with some embodiments. The reflowed seed layer160fills the voids during the annealing process, in accordance with some embodiments.

In some embodiments, a volume ratio of the hydrogen gas to the process gas ranges from about 50% to about 100%. The volume ratio of the hydrogen gas to the process gas ranges from about 60% to about 100%, in accordance with some embodiments. If the volume ratio of the hydrogen gas to the process gas is less than about 50%, the manganese170diffusing from the seed layer160to the barrier layer150is not enough to improve electromigration resistance of the barrier layer150, in accordance with some embodiments.

The partial pressure of hydrogen in the process gas ranges from about 400 torr to about 760 torr, in accordance with some embodiments. The process temperature of the annealing process ranges from about 200° C. to about 400° C. in accordance with some embodiments. The process time of the annealing process ranges from about 1 minute to about 10 minutes, in accordance with some embodiments.

As shown inFIG.1G-1, the barrier layer150has a hole156, in accordance with some embodiments. In some embodiments, the hole156is formed during the formation of the seed layer160. The process for forming the seed layer160may damage the barrier layer150. In some other embodiments (not shown), the hole156is formed during the formation of the barrier layer150.

The manganese170diffuses from the seed layer160into the hole156to react with the oxygen atoms in the dielectric layer130after the seed layer160is annealed, in accordance with some embodiments. In some embodiments, an atomic concentration of the manganese170in the hole156is greater than the atomic concentration of the manganese170in the barrier layer150after the seed layer160is annealed.

Since the manganese170fills the hole156. the manganese170repairs the barrier layer150, which improves electromigration resistance (or barrier ability) of the barrier layer150, in accordance with some embodiments. Therefore, the yield and the reliability of conductive lines subsequently formed on the barrier layer150are improved, which reduces the resistance of the conductive lines, in accordance with some embodiments.

Afterwards, as shown inFIG.1H, a conductive layer180is formed over the seed layer160, in accordance with some embodiments. The conductive layer180is doped with manganese170, in accordance with some embodiments. In some embodiments, an atomic concentration of the manganese170in the conductive layer180ranges from about 0.5 % to about 2.5 %.

The conductive layer180includes copper, copper alloys, cobalt (Co), ruthenium (Ru) or other suitable conductive materials, in accordance with some embodiments. In some embodiments, the conductive layer180is formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an electroless plating process, or another suitable process. The physical vapor deposition process includes a plasma deposition process, in accordance with some embodiments.

FIG.1I-1is an enlarged view of a portion A of the semiconductor device structure ofFIG.1I, in accordance with some embodiments. As shown inFIGS.1H,1I, and1I-1, the conductive layer180is annealed in a process gas to fuse the conductive layer180with the seed layer160so as to form a thick conductive layer190, in accordance with some embodiments.

The process gas includes a hydrogen gas, in accordance with some embodiments. In some embodiments, the process gas further includes nitrogen or an inert gas. As shown inFIGS.1H,1I, and1I-1, upper portions181of the conductive layer180flow downwardly during the annealing of the conductive layer180, in accordance with some embodiments.

In some embodiments, a volume ratio of the hydrogen gas to the process gas ranges from about 50% to about 100%. The volume ratio of the hydrogen gas to the process gas ranges from about 60% to about 100%, in accordance with some embodiments.

The partial pressure of hydrogen in the process gas ranges from about 400 torr to about 760 torr, in accordance with some embodiments. The process temperature of the annealing process ranges from about 200° C. to about 400° C., in accordance with some embodiments.

The manganese170diffuses from the conductive layer180to the barrier layer150during the annealing of the conductive layer180in the process gas, in accordance with some embodiments. After the conductive layer180is annealed, an atomic concentration of the manganese170in the barrier layer150is greater than an atomic concentration of the manganese170in the thick conductive layer190, in accordance with some embodiments. The thick conductive layer190is embedded in the barrier layer150, in accordance with some embodiments. The barrier layer150is embedded in the dielectric layer130. in accordance with some embodiments.

As shown inFIG.1J, a conductive layer210is formed over the thick conductive layer190, in accordance with some embodiments. The conductive layer210includes copper, copper alloys, cobalt (Co), ruthenium (Ru) or other suitable conductive materials, in accordance with some embodiments. In some embodiments, the conductive layer210is formed by an electroplating process.

FIG.1K-1is an enlarged view of a portion A of the semiconductor device structure ofFIG.1K. in accordance with some embodiments. As shown inFIGS.1K and1K-1, the conductive layer210. the mask layer140, and upper portions of the thick conductive layer190, the dielectric layer130, and the barrier layer150are removed, in accordance with some embodiments. The removal process includes a planarization process, such as a chemical mechanical polishing process, in accordance with some embodiments.

After the removal process, the conductive layer190remaining in the trench132forms a conductive line192, and the conductive layer190remaining in the trench134forms a conductive line194, in accordance with some embodiments. The width W192 of the conductive line192is less than or equal to about 2000 nm, in accordance with some embodiments. The width W192 ranges from about 1 nm to about 2000 nm, in accordance with some embodiments. In some embodiments, the width W192 is greater than about 2000 nm, in accordance with some embodiments.

In some embodiments, a pitch P (or a distance) between the center C192of the conductive line192and the center C194of the conductive line194ranges from about 1 nm to about 150 nm, in accordance with some embodiments. The pitch P ranges from about 1 nm to about 40 nm, in accordance with some embodiments. In some embodiments, the pitch P is greater than about 150 nm, in accordance with some embodiments.

The barrier layer150has a central portion157and peripheral portions158and159, in accordance with some embodiments. The peripheral portion158is adjacent to the thick conductive layer190, in accordance with some embodiments. The peripheral portion159is adjacent to the dielectric layer130, in accordance with some embodiments.

The concentration of the manganese170in the central portion157is greater than the atomic concentration of the manganese170in the peripheral portion158, in accordance with some embodiments. The concentration of the manganese170in the central portion157is greater than the atomic concentration of the manganese170in the peripheral portion159, in accordance with some embodiments.

The boundary B between the layers152and154is in the central portion157, in accordance with some embodiments. In this step, a semiconductor device structure100is substantially formed, in accordance with some embodiments. The manganese170reduces the resistance of the conductive lines192and194, in accordance with some embodiments.

FIGS.2A-2Jare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown inFIG.2A, a substrate210is provided, in accordance with some embodiments. The substrate210includes, for example, a semiconductor substrate. The substrate210includes, for example, a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer.

In some embodiments, the substrate210is made of an elementary semiconductor material including silicon or germanium in a single crystal structure, a polycrystal structure, or an amorphous structure. In some other embodiments, the substrate210is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as SiGe or GaAsP, or a combination thereof. The substrate210may also include multi-layer semiconductors, semiconductor on insulator (SOI) (such as silicon on insulator or germanium on insulator), or a combination thereof.

As shown inFIG.2A, various device elements220are formed over and/or in the substrate210, in accordance with some embodiments. For the sake of simplicity and clarity,FIG.2Aonly shows one of the device elements220, in accordance with some embodiments.

Examples of the various device elements220include active devices, passive devices, other suitable elements (e.g., conductive lines), or a combination thereof. The active devices may include transistors or diodes formed at a surface of the substrate210. The passive devices include resistors, capacitors, or other suitable passive devices.

Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form the various device elements220. The FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in the substrate210. The isolation features are used to surround active regions and electrically isolate the various device elements220formed in and/or over the substrate210in the active regions. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.

As shown inFIG.2A, a dielectric layer230is then deposited over the substrate210and the device elements220, in accordance with some embodiments. The dielectric layer230is made of any suitable dielectric material, such as silicon oxide, silicon oxynitride, SiOC, SiOCN, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), hydrogenated silicon oxycarbide (SiCO:H), a low-k material, a porous dielectric material, or a combination thereof, in accordance with some embodiments.

The dielectric layer230is deposited by any suitable process, such as a chemical vapor deposition (CVD) process, a high density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, a sputtering process, or a combination thereof, in accordance with some embodiments.

As shown inFIG.2A, a mask layer240is formed over the dielectric layer230, in accordance with some embodiments. The mask layer240has trenches242and244, in accordance with some embodiments. The mask layer240is made of a material different from the materials of the dielectric layer230, in accordance with some embodiments.

The mask layer240is made of nitrides (e.g., silicon nitride) or oxynitride (e.g., silicon oxynitride), TEOS (tetra-ethyl-ortho-silane), tungsten carbide (WC), TiN, or a nitrogen free anti-reflective coating (NFARC) material, in accordance with some embodiments. The mask layer240is a combination of 1 to 5 layers or more, in accordance with some embodiments. The mask layer240is formed by any suitable process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or a combination thereof, in accordance with some embodiments.

As shown inFIG.2A, portions of the dielectric layer230are removed through the trenches242and244of the mask layer240, in accordance with some embodiments. The removal process forms trenches232and234in the dielectric layer230, in accordance with some embodiments.

The removal process also etches the edges of the mask layer240, and therefore the edges of the mask layer240are rounded, in accordance with some embodiments. The removal process includes an etching process, such as a dry etching process (e.g., a plasma etching process), in accordance with some embodiments.

Thereafter, as shown inFIG.2A, a portion of the dielectric layer230is removed to form a via236in the dielectric layer230, in accordance with some embodiments. The via236exposes a portion of the device element220, in accordance with some embodiments.

FIG.2B-1is an enlarged view of a portion A of the semiconductor device structure ofFIG.2B, in accordance with some embodiments. As shown inFIGS.2B and2B-1, a barrier layer250is formed in the trenches232and234and the via236of the dielectric layer230and the trenches242and244of the mask layer240, in accordance with some embodiments.

The barrier layer250is conformally formed over the mask layer240, inner walls232aand a bottom surface232bof the trench232. inner walls234aand a bottom surface234bof the trench234, inner walls236aof the via236, and the device element220, in accordance with some embodiments. Therefore, the barrier layer250has trenches251and253and a via256respectively in the trenches232and234and the via236, in accordance with some embodiments.

The barrier layer250is configured to block the diffusion of metal atoms of a conductive layer subsequently formed on the barrier layer250, in accordance with some embodiments. The barrier layer250has a layer252and a layer254, in accordance with some embodiments.

The layer254is over the layer252, in accordance with some embodiments. The formation of the barrier layer250includes depositing the layer252in the trenches232and234; and depositing the layer254over the layer252, in accordance with some embodiments. The layers252and254are made of different materials, in accordance with some embodiments.

In some embodiments, the barrier layer250includes tantalum, tantalum nitrides, cobalt (Co), ruthenium (Ru), titanium, titanium nitrides, or other suitable materials. In some embodiments, the layer252is made of tantalum nitrides, and the layer254is made of cobalt, ruthenium, tantalum, or titanium.

In some other embodiments (not shown), the barrier layer250further includes one or more layers over the layer254, and the one or more layers are made of cobalt, ruthenium, tantalum, or titanium. The one or more layers and the layer254are made of different materials, in accordance with some embodiments.

In some embodiments, the barrier layer250is formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or another suitable process.

Thereafter, as shown inFIG.2C, a seed layer260is formed over the barrier layer250and in the trenches251and253of the barrier layer250, in accordance with some embodiments. The seed layer260is doped with manganese270, in accordance with some embodiments. In some embodiments, an atomic concentration of the manganese270in the seed layer260ranges from about 0.5 % to about 2.5 %.

The seed layer260includes copper, copper alloys, cobalt (Co), ruthenium (Ru) or other suitable conductive materials, in accordance with some embodiments. In some embodiments, the seed layer260is formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an electroless plating process, or another suitable process. The physical vapor deposition process includes a plasma deposition process, in accordance with some embodiments.

FIG.2D-1is an enlarged view of a portion A of the semiconductor device structure ofFIG.2D, in accordance with some embodiments. As shown inFIGS.2D and2D-1, the seed layer260is annealed in a process gas including a hydrogen gas, in accordance with some embodiments.

In some embodiments, a volume ratio of the hydrogen gas to the process gas ranges from about 50% to about 100%. The volume ratio of the hydrogen gas to the process gas ranges from about 60% to about 100%, in accordance with some embodiments.

The partial pressure of hydrogen in the process gas ranges from about400torr to about760torr, in accordance with some embodiments. The process temperature of the annealing process ranges from about 200° C. to about 400° C., in accordance with some embodiments.

The manganese270diffuses from the seed layer260to the barrier layer250during the annealing of the seed layer260in the process gas, in accordance with some embodiments. After the seed layer260is annealed, an atomic concentration of the manganese270in the barrier layer250is greater than an atomic concentration of the manganese270in the seed layer260, in accordance with some embodiments.

The layer252has portions252aand252b, in accordance with some embodiments. The portion252ais adjacent to the layer254, in accordance with some embodiments. The portion252bis adjacent to the dielectric layer230, in accordance with some embodiments. In some embodiments, the atomic concentration of the manganese270in the portion252ais greater than the atomic concentration of the manganese270in the portion252bafter the seed layer260is annealed, in accordance with some embodiments.

The layer254has portion254aand254b, in accordance with some embodiments. The portion254ais adjacent to the layer252, in accordance with some embodiments. The portion254bis adjacent to the seed layer260, in accordance with some embodiments. The concentration of the manganese270in the portion254ais greater than the atomic concentration of the manganese270in the portion254bafter the seed layer260is annealed, in accordance with some embodiments.

The process gas includes a hydrogen gas, in accordance with some embodiments. In some embodiments, the process gas further includes nitrogen or an inert gas. As shown inFIGS.2C and2D, the seed layer260is reflowed and therefore upper portions261of the seed layer260partially flow downwardly during the annealing of the seed layer260in the process gas, in accordance with some embodiments. Therefore, the upper portions261become thinner and the lower portions262of the seed layer260become thicker, in accordance with some embodiments.

As shown inFIG.2D-1, the barrier layer250has a hole256, in accordance with some embodiments. In some embodiments, the hole256is formed during the formation of the seed layer260. The process for forming the seed layer260may damage the barrier layer250. In some other embodiments (not shown), the hole256is formed during the formation of the barrier layer250.

The manganese270diffuses from the seed layer260into the hole256after the seed layer260is annealed, in accordance with some embodiments. In some embodiments, an atomic concentration of the manganese270in the hole256is greater than the atomic concentration of the manganese270in the barrier layer250after the seed layer260is annealed.

As shown inFIG.2E, a seed layer280is formed over the seed layer260, in accordance with some embodiments. The seed layer280is doped with manganese270, in accordance with some embodiments. In some embodiments, an atomic concentration of the manganese270in the seed layer280ranges from about 0.5 % to about 2.5 %.

The seed layer280includes copper, copper alloys, cobalt (Co), ruthenium (Ru) or other suitable conductive materials, in accordance with some embodiments. In some embodiments, the seed layer280is formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an electroless plating process, or another suitable process. The physical vapor deposition process includes a plasma deposition process, in accordance with some embodiments.

FIG.2F-1is an enlarged view of a portion A of the semiconductor device structure ofFIG.2F. in accordance with some embodiments. As shown inFIGS.2F and2F-1. the seed layers260and280are annealed in a process gas to fuse the seed layer260with the seed layer280so as to form a thick seed layer290, in accordance with some embodiments.

The process gas includes a hydrogen gas, in accordance with some embodiments. In some embodiments, a volume ratio of the hydrogen gas to the process gas ranges from about 50% to about 100%. The volume ratio of the hydrogen gas to the process gas ranges from about 60% to about 100%, in accordance with some embodiments.

The partial pressure of hydrogen in the process gas ranges from about 400 torr to about 760 torr, in accordance with some embodiments. The process temperature of the annealing process ranges from about 200° C. to about 400° C., in accordance with some embodiments.

The manganese270diffuses from the seed layers260and280to the barrier layer250during the annealing of the seed layers260and280in the process gas, in accordance with some embodiments. After the seed layers260and280are annealed, an atomic concentration of the manganese270in the barrier layer250is greater than an atomic concentration of the manganese270in the thick seed layer290, in accordance with some embodiments.

In some embodiments, the atomic concentration of the manganese270in the portion252ais greater than the atomic concentration of the manganese270in the portion252bafter the seed layers260and280are annealed. The concentration of the manganese270in the portion254ais greater than the atomic concentration of the manganese270in the portion254bafter the seed layers260and280are annealed, in accordance with some embodiments.

Afterwards, as shown inFIG.2G. a conductive layer310is formed over the thick seed layer290, in accordance with some embodiments. The conductive layer310is doped with manganese270, in accordance with some embodiments. In some embodiments, an atomic concentration of the manganese270in the conductive layer310ranges from about 0.5 % to about 2.5 %.

The conductive layer310includes copper, copper alloys, cobalt (Co), ruthenium (Ru) or other suitable conductive materials, in accordance with some embodiments. In some embodiments, the conductive layer310is formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an electroless plating process, or another suitable process. The physical vapor deposition process includes a plasma deposition process, in accordance with some embodiments.

FIG.2H-1is an enlarged view of a portion A of the semiconductor device structure ofFIG.2H, in accordance with some embodiments. As shown inFIGS.2G,2H, and2H-1, the conductive layer310is annealed in a process gas to fuse the conductive layer310with the thick seed layer290so as to form a thick conductive layer320, in accordance with some embodiments. As shown inFIGS.2G,2H. and 2H-1, upper portions311of the conductive layer310flow downwardly during the annealing of the conductive layer310, in accordance with some embodiments.

The process gas includes a hydrogen gas, in accordance with some embodiments. In some embodiments, the process gas further includes nitrogen or an inert gas. In some embodiments, a volume ratio of the hydrogen gas to the process gas ranges from about 50% to about 100%. The volume ratio of the hydrogen gas to the process gas ranges from about 60% to about 100%, in accordance with some embodiments.

The partial pressure of hydrogen in the process gas ranges from about400torr to about760torr, in accordance with some embodiments. The process temperature of the annealing process ranges from about 200° C. to about 400° C., in accordance with some embodiments.

The manganese270diffuses from the conductive layer310to the barrier layer250during the annealing of the conductive layer310in the process gas, in accordance with some embodiments. After the conductive layer310is annealed, an atomic concentration of the manganese270in the barrier layer250is greater than an atomic concentration of the manganese270in the thick conductive layer320, in accordance with some embodiments.

The thick conductive layer320is embedded in the barrier layer250, in accordance with some embodiments. The barrier layer250is embedded in the dielectric layer230, in accordance with some embodiments.

As shown inFIG.2I, a conductive layer330is formed over the thick conductive layer320, in accordance with some embodiments. The conductive layer330includes copper, copper alloys, cobalt (Co), ruthenium (Ru) or other suitable conductive materials, in accordance with some embodiments. In some embodiments, the conductive layer330is formed by an electroplating process.

FIG.2J-1is an enlarged view of a portion A of the semiconductor device structure ofFIG.2J, in accordance with some embodiments. As shown inFIGS.2J and2J-1. the conductive layer330, the mask layer240, and upper portions of the thick conductive layer320, the dielectric layer230, and the barrier layer250are removed, in accordance with some embodiments.

After the removal process, the conductive layer320remaining in the trench232forms a conductive line322, and the conductive layer320remaining in the trench234forms a conductive line324, in accordance with some embodiments. The removal process includes a planarization process, such as a chemical mechanical polishing process, in accordance with some embodiments.

The barrier layer250has a central portion257and peripheral portions258and259, in accordance with some embodiments. The peripheral portion258is adjacent to the thick conductive layer320. in accordance with some embodiments. The peripheral portion259is adjacent to the dielectric layer230, in accordance with some embodiments.

The atomic concentration of the manganese270in the central portion257is greater than the atomic concentration of the manganese270in the peripheral portion258, in accordance with some embodiments. The atomic concentration of the manganese270in the central portion257is greater than the atomic concentration of the manganese270in the peripheral portion259, in accordance with some embodiments.

The boundary B between the layers252and254is in the central portion257, in accordance with some embodiments. In this step, a semiconductor device structure200is substantially formed, in accordance with some embodiments.

Processes and materials for forming the semiconductor device structure200may be similar to, or the same as, those for forming the semiconductor device structure100described above. Elements designated by the same or similar reference numbers as those inFIGS.1A to2Jhave the same or similar structures and the materials. Therefore, the detailed descriptions thereof will not be repeated herein.

In accordance with some embodiments, semiconductor device structures and methods for forming the same are provided. The methods (for forming the semiconductor device structure) anneal a seed layer in a high concentration of a hydrogen gas, and therefore manganese in the seed layer diffuses to a barrier layer, which improves the barrier ability of the barrier layer. The barrier layer is configured to block the diffusion of metal atoms of a conductive layer formed on the barrier layer. Therefore, the reliability of the semiconductor device structures with the barrier layer is improved.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes removing a portion of a dielectric layer to form a trench in the dielectric layer. The method includes forming a barrier layer in the trench. The method includes forming a seed layer in the trench and over the barrier layer. The seed layer is doped with manganese. The method includes annealing the seed layer in a first process gas including a first hydrogen gas. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the seed layer to the barrier layer during the annealing of the seed layer in the first process gas.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a trench in a dielectric layer. The method includes depositing a barrier layer in the trench. The method includes forming a first seed layer in the trench and over the barrier layer. The first seed layer is doped with manganese. The method includes forming a second seed layer over the first seed layer. The second seed layer is doped with manganese. The method includes annealing the first seed layer and the second seed layer in a first process gas including a first hydrogen gas to fuse the first seed layer with the second seed layer so as to form a thick seed layer. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the first seed layer and the second seed layer to the barrier layer during the annealing of the first seed layer and the second seed layer in the first process gas.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure includes a barrier layer in the dielectric layer. The barrier layer is doped with manganese, the barrier layer has a central portion and a first peripheral portion, the first peripheral portion is between the dielectric layer and the central portion, and a first concentration of the manganese in the central portion is greater than a second concentration of the manganese in the first peripheral portion. The semiconductor device structure includes a conductive layer in the barrier layer.