Boost converter and boost converter cell

A boost converter and a cell applicable to the boost converter are provided. The cell comprises a control circuit configured to generate a bottom control signal related to a bottom plate of a capacitor, and a top control signal related to a top plate of the capacitor to connect the capacitor based on one or more operational phases, and a booster configured to convert the top control signal generated by the control circuit, wherein the capacitor is configured to be sequentially connected to voltage levels through switches, based on the bottom control signal and the converted top control signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 USC § 119(a) of Korean Patent Application No. 10-2019-0063680 filed on May 30, 2019 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

The following description relates to a boost converter that implements soft charging and a cell applicable to the boost converter.

2. Description of Related Art

When an existing direct current-direct current (DC-DC) converter is used, ΔV=N*VIN−VOUT, a quantity Q of electric charge transferred during charge sharing is proportional to ΔV, and an energy loss Elossis proportional to ΔV2. That is, when ΔV increases, the quantity of electric charge transferred increases, while the energy efficiency for voltage conversion sharply decreases. Thus, technology for maintaining the quantity of electric charge transferred and the energy efficiency for voltage conversion to be constant is desirable.

SUMMARY

In a general aspect, a cell includes a control circuit configured to generate a bottom control signal related to a bottom plate of a capacitor, and a top control signal related to a top plate of the capacitor to connect the capacitor based on one or more operational phases; and a booster configured to convert the top control signal generated by the control circuit to a converted top control signal by increasing a voltage level of the top control signal; and wherein the capacitor may be configured to be sequentially connected to voltage levels through switches, based on the bottom control signal and the converted top control signal.

The converted top control signal may be a signal which connects the top plate of the capacitor to a voltage level higher than an input voltage, and the bottom control signal may be a signal which connects the bottom plate of the capacitor to a voltage level lower than the input voltage.

The voltage levels may include M voltage levels between an input voltage and a ground GND, and N voltage levels between the input voltage and an output voltage.

The cell may include a phase number adjusting circuit configured to determine the N voltage levels and the M voltage levels.

The phase number adjusting circuit may be configured to determine the N voltage levels between the input voltage and the output voltage based on a potential difference between the output voltage and the input voltage, based on a charge redistribution loss (CRL) and a switching loss.

The phase number adjusting circuit may be configured to determine the M voltage levels between the input voltage and the ground based on a potential difference between the input voltage and the ground, based on a charge redistribution loss (CRL) and a switching loss.

The N voltage levels may increase in response to an increase in a difference between the output voltage and the input voltage, and the M voltage levels may increase in response to an increase in a difference between the input voltage and the ground.

The capacitor may be charged or discharged when sequentially connected to each of the voltage levels based on an input clock.

A variation in a voltage of the charged or discharged capacitor may be determined based on a ratio of an input voltage and N voltage levels.

The control circuit may include an OR gate configured to receive a clock as an input and control the switches.

In a general aspect, a cell includes a control circuit configured to generate a bottom control signal related to a first capacitive plate and a top control signal related to a second capacitive plate to connect a capacitor based on one or more operational phases, a booster configured to convert the top control signal generated by the control circuit to a converted top control signal by increasing a voltage level of the top control signal; and a first capacitor configured to be connected to a voltage level corresponding to a charging phase through a first switch, and a second capacitor configured to be connected to a voltage level corresponding to a discharging phase through a second switch, based on the bottom control signal and the converted top control signal. The first capacitor to be connected to the voltage level corresponding to the charging phase through the first switch may be charged based on the converted top control signal which connects a top plate of the capacitor to a voltage level higher than an input voltage, and the bottom control signal which connects a bottom plate of the capacitor to a voltage level lower than the input voltage.

The second capacitor configured to be connected to the voltage level corresponding to the discharging phase through the second switch may be discharged by controlling the second switch in an inverse order of the first switch connected to the voltage level corresponding to the charging phase, based on the converted top control signal and the bottom control signal.

The bottom control signal may be configured to connect a bottom plate of a charged capacitor from an input voltage level to a ground through the first switch, and connect a bottom plate of a discharged capacitor from the ground to the input voltage level through the first switch.

The converted top control signal may be configured to connect a top plate of a charged capacitor from an input voltage level to an output voltage level through the second switch, and connect a top plate of the discharged capacitor from the output voltage level to the input voltage level through the second switch.

The voltage levels may include M voltage levels between an input voltage and a ground GND, and N voltage levels between the input voltage and an output voltage.

The cell may include a phase number adjusting circuit configured to determine the N voltage levels and the M voltage levels, wherein the phase number adjusting circuit may be configured to determine the N voltage levels between the input voltage and the output voltage based on a potential difference between the output voltage and the input voltage based on a charge redistribution loss (CRL) and a switching loss, or determine the M voltage levels between the input voltage and the ground based on a potential difference between the input voltage and the ground based on the CRL and the switching loss.

A variation in a voltage of a charged capacitor or a discharged capacitor may be determined based on a ratio of an input voltage and the N voltage levels.

In a general aspect, a boost converter includes a clock divider configured to determine a number of phases, a frequency controller configured to adjust a shifting rate of the clock divider; and at least one cell configured to softly charge or softly discharge a capacitor by controlling switches synchronized with a clock input through the clock divider.

In a general aspect, a method includes generating a bottom control signal to control one or more first switches to sequentially connect a bottom plate of a capacitor to first voltage levels between an input voltage and a ground (GND) to charge or discharge the capacitor, generating a top control signal, converting, with a booster, the top control signal to a converted top control signal; and controlling one or more second switches with the converted top control signal to sequentially connect a top plate of the capacitor to second voltage levels between the input voltage and an output voltage to charge or discharge the capacitor.

DETAILED DESCRIPTION

Although terms such as “first,” “second,” and “third” may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples. Herein, it is noted that use of the term ‘may’ with respect to an example or embodiment, e.g., as to what an example or embodiment may include or implement, means that at least one example or embodiment exists where such a feature is included or implemented while all examples and embodiments are not limited thereto.

When describing the examples with reference to the accompanying drawings, like reference numerals refer to like constituent elements and a repeated description related thereto will be omitted. In the description of examples, detailed description of well-known related structures or functions will be omitted when it is deemed that such description will cause ambiguous interpretation of the present disclosure.

Hereinafter, examples will be described in detail with reference to the accompanying drawings.

FIGS. 1A and 1Billustrate an example of a change in energy occurring during charge sharing, in accordance with one or more embodiments.

Referring toFIGS. 1A and 1B, a left capacitor110and a right capacitor120may have the same capacitance C. The left capacitor110may be charged with a potential of V+ΔV, and the right capacitor120may be charged with a potential of V−ΔV. The capacitors110,120each include a top plate and a bottom plate. When charge sharing is performed by connecting the top plates of the capacitors110,120through a switch connection130, an electric charge of CΔV is transmitted through the circuit such that the capacitors110,120both have a potential of V. Before charge sharing occurs, the left capacitor110and the right capacitor120may have energies as expressed by Equation 1 below.
½C(V+ΔV)2+½C(V−ΔV)2Equation 1:

After charge sharing occurs, energies of the left capacitor110and the right capacitor120are expressed by Equation 2 below. Through a comparison of Equation 1 and Equation 2, during charge sharing, an energy of CΔV2is consumed such that an energy of CVΔV is exchanged between the two capacitors110,120, and the left capacitor110and the right capacitor120may each have an energy of ½CV2.
½CV2+½CV2+(CVΔV−CVΔV)  Equation 2:

In an example, as a result of comparing Equation 1 and Equation 2, the energy exchanged between the capacitors may be proportional to ΔV, and the energy consumed by charge sharing may be proportional ΔV2. When an input voltage is converted and output to a predetermined voltage using a switched-capacitor structure, charge sharing is performed. In this example, when a loss decreases in proportion to ΔV2, the efficiency of charge sharing improves.

If charge sharing is performed N times, a capacitor voltage increases by ΔV/N through a single charge sharing, and the capacitor voltage increases by

(Δ⁢⁢VN)*N
through N charge sharings. In this example, the energy consumed during the N charge sharings is

C⁡(ΔVN)2⁢N,
which is reduced to 1/N when compared to CΔV2. In this manner, charging sharing that repeats changing a small voltage a number of times to exchange a small quantity of electric charge is referred to as soft charging. When soft charging is used, the loss occurring in the switched-capacitor structure may be reduced by a factor of 1/N.

FIGS. 2A and 2Billustrate an example of charging a capacitor using soft charging, in accordance with one or more embodiments.

FIG. 2Aillustrates an example of charging a 200 mV-charged capacitor210to 800 mV by a single switching operation.FIG. 2Billustrates an example of charging a 200 mV-charged capacitor210to 400 mV, 600 mV, and 800 mV by three separate switching operations.

In the examples ofFIG. 2AandFIG. 2B, the final voltages of the capacitors may equally be 800 mV. However, different energies may be consumed to charge the capacitors to 800 mV. That is, a loss occurring when charging the capacitor to 800 mV through the three processes or operations illustrated inFIG. 2Bcorresponds to ⅓ a loss occurring when charging the capacitor to 800 mV through the single process or operation as shown inFIG. 2A, whereby the efficiency improves.

Specifically, power may be lost when sequentially charging the capacitor from 200 mV to 400 mV, from 400 mV to 600 mV, and from 600 mV to 800 mV as shown inFIG. 2B. However, the total loss occurring during the sequential charging operation ofFIG. 2Bmay correspond to ⅓ the total loss that may occur during the single charging operation ofFIG. 2A. Thus, when soft charging is used, the energy efficiency improves.

FIG. 3illustrates an example of a cell applicable to a boost converter, in accordance with one or more embodiments.

Referring toFIG. 3, a cell300applicable to a boost converter may include a control circuit310, a booster320, and a capacitor330. The capacitor330includes a bottom plate and a top plate. The control circuit310may include an OR gate configured to receive CLK<1:N> and may connect the capacitor to a corresponding voltage level by controlling switches related to each phase. The booster320increases a voltage level of a top control signal to control a switch of a voltage level higher than VIN.

The control circuit310receives CLK<1:N> and generates a bottom control signal BOT<1:N> to control a connection of the bottom plate of the capacitor to each voltage level, and a top control signal TOP<1:N> to control a connection of the top plate of the capacitor to each voltage level.

In this example, the bottom control signal BOT<1:N> generated by the control circuit310controls a switch configured to connect the bottom plate of the capacitor to a voltage level lower than an input voltage VIN. However, the top control signal TOP<1:N> generated by the control circuit310may not directly control a switch configured to connect the top plate of the capacitor to a voltage level higher than the input voltage VIN. Thus, the booster320generates a converted top control signal TOP_H<1:N> by converting the top control signal TOP<1:N> so as to swing by an output voltage VOUT. The converted top control signal TOP_H<1:N> may directly control the switch configured to connect the top plate of the capacitor to the voltage level higher than the input voltage VIN.

In the example ofFIG. 3, in a normal phase operation, the bottom control signal BOT<1:N> may control a switch at a voltage level VBN<1:N>, and the converted top control signal TOP_H<1:N> may control a switch at a voltage level VTN<1:N>.

A cell applicable to a boost converter using soft charging through a switched-capacitor structure may be applicable to an energy harvesting system (for example, a circuit which charges a battery using solar heat or infrared rays) and/or a battery-free system which directly uses received energy.

FIGS. 4A and 4Billustrate an example of charging a capacitor implementing soft charging, and transferring power using the charged capacitor, in accordance with one or more embodiments.FIG. 4Aillustrates an example of charging a capacitor implementing a virtual voltage level for soft charging, andFIG. 4Billustrates an example of transferring power by implementing the charged capacitor.

FIG. 4Aillustrates a process of charging a fully discharged capacitor to VOUT. GND denotes a ground, and a horizontal solid line411denotes a voltage level corresponding to the ground. VINdenotes an input voltage, and a horizontal solid line415denotes a voltage level corresponding to the input voltage VIN. VOUTdenotes an output voltage, and a horizontal solid line423denotes a voltage level corresponding to the output voltage VOUT. Dotted lines412through414denote virtual voltage levels between GND and VIN, and dotted lines416through422denote virtual voltage levels between VINand VOUT. Voltage levels corresponding to a solid line and a dotted line at lower positions are lower than voltage levels corresponding to a solid line and a dotted line at higher positions. For example, the voltage level VOUTcorresponding to the solid line423is higher than the voltage level VINcorresponding to the solid line415, which indicates an example of an up-conversion of voltage from VINto VOUT.

In an example, a capacitor symbol is depicted as parallel plates, and a vertical line between a solid line and a dotted line indicating voltage levels indicates connection states of a top plate and a bottom plate of each capacitor.

Referring toFIG. 4A, the leftmost capacitor C1indicates a state in which both a top plate and a bottom plate of capacitor C1are connected to the voltage level415corresponding to VIN, and indicates that the capacitor C1is fully discharged since there is no potential difference between the top plate and the bottom plate. Referring again toFIG. 4A, the second capacitor C2from the left indicates a state in which a top plate thereof is connected to the voltage level415corresponding to VIN, and a bottom plate thereof is connected to a voltage level corresponding to the dotted line414, which is ΔV lower than VIN. InFIG. 4A, the third capacitor C3from the left indicates a state in which a top plate thereof is connected to the voltage level415corresponding to VIN, and a bottom plate thereof is connected to a voltage level corresponding to the dotted line413, which is 2ΔV lower than VIN. In the example ofFIG. 4A, electric charge of CΔV is used for soft charging through a change of a connection state of a bottom plate or a top plate.

Referring toFIG. 4A, the fifth capacitor C5from the left indicates a state in which a top plate thereof is connected to the voltage level415corresponding to VIN, and a bottom plate thereof is connected to the voltage level411corresponding to GND, and indicates that the fully discharged capacitor C5is charged to VIN. Then, the top plate of the capacitor is sequentially connected to virtual voltage levels existing between VINand VOUTat an interval of ΔV, and the VIN-charged capacitor is charged to VOUT.

FIG. 4Billustrates an example of transferring power with the capacitor charged to VOUT. InFIG. 4B, a bottom plate of the leftmost capacitor is connected to the voltage level411corresponding to GND, and a top plate thereof is connected to the voltage level423corresponding to VOUT. Thus, the capacitor is charged to VOUT.

When the bottom plate of the capacitor charged to VOUTis sequentially connected to the virtual voltage levels between GND and VIN, power is transferred to an output. Further, when a top plate of a capacitor connected between VINand VOUTis sequentially connected to virtual rails existing between VOUTand VINat an interval of ΔV, the capacitor is fully discharged by soft discharging. Referring toFIG. 4B, both a top plate and a bottom plate of the rightmost capacitor C1are connected to the voltage level415corresponding to VIN, and thus the capacitor is fully discharged.

Thus, the capacitor charged to VOUTby the process ofFIG. 4Ais fully discharged after transferring power to VOUTthrough the process ofFIG. 4B, and the fully discharged capacitor is charged by the process ofFIG. 4A.

FIG. 5illustrates an example of a cell applicable to a boost converter, in accordance with one or more embodiments.

Referring toFIG. 5, a cell500applicable to a boost converter includes a control circuit510, a booster520, and a capacitor530. The capacitor530includes a bottom plate and a top plate. The control circuit510includes an OR gate configured to receive CLK<1:N> and connect the capacitor to a corresponding voltage level by controlling switches pertaining to each phase. The booster520increases a voltage level of a top control signal to control a switch of a voltage level higher than VIN.

The control circuit510receives CLK<1:N>, and generates a bottom control signal BOT<1:N> to connect the bottom plate of the capacitor to each voltage level, and a top control signal TOP<1:N> to connect the top plate of the capacitor to each voltage level.

In this example, the bottom control signal BOT<1:N> generated by the control circuit510controls a switch configured to connect the bottom plate of the capacitor to a voltage level lower than an input voltage VIN. However, the top control signal TOP<1:N> generated by the control circuit510may not directly control a switch configured to connect the top plate of the capacitor to a voltage level higher than the input voltage VIN. Thus, the booster520generates a converted top control signal TOP_H<1:N> by converting the top control signal TOP<1:N> so as to swing by an output voltage VOUT. The converted top control signal TOP_H<1:N> directly controls the switch configured to connect the top plate of the capacitor to the voltage level higher than the input voltage VIN.

When the cell500applicable to a boost converter operates in a normal phase, the bottom control signal BOT<1:N> controls a switch at a voltage level VBN<1:N>, and the converted top control signal TOP_H<1:N> controls a switch at a voltage level VTN1:N>. Further, when the cell500applicable to a boost converter operates in a counter phase, the bottom control signal BOT<1:N> controls a switch at a voltage level VBN<N:1> in an inverse order of the normal phase, and the converted top control signal TOP_H<1:N> controls a switch at a voltage level VTN<N:1> in an inverse order of the normal phase. Here, the counter phase indicates an example in which there is a phase difference of 180 degrees from the normal phase. Unlike the cell ofFIG. 3including the capacitor operating in the normal phase, the cell ofFIG. 5includes capacitors operating in the normal phase and in the counter phase.

Thus, when the bottom control signal BOT<1:N> is used, a bottom plate of the capacitor operating in the normal phase is sequentially connected from GND to VIN, and a bottom plate of the capacitor operating in the counter phase is sequentially connected from VINto GND. Additionally, when the converted top control signal TOP_H<1:N> is used, a top plate of the capacitor operating in the normal phase is sequentially connected from VINto VOUT, and a top plate of the capacitor operating in the counter phase is sequentially connected from VOUTto VIN.

In the example ofFIG. 3in which the counter phase is not used, flying capacitor Cflyoperating in the normal phase may be present in each of P cells. Thus, the total capacitance is P*Cfly. InFIG. 3, C1is Cfly. Conversely, in the example ofFIG. 5in which the normal phase and the counter phase are used, Cfly1operating in the normal phase is present in each of P/2 cells, and Cfly2operating in the counter phase is present in each of the remaining P/2 cells. Thus, the total capacitance is P/2*(Cfly1+Cfly2). If Cfly1equals to Cfly2, the total capacitance is P*Cfly. InFIG. 5, C1is Cfly1, and C1,CNTis Cfly2.

A cell applicable to a boost converter using soft charging through a switched-capacitor structure may be implemented in an energy harvesting system (for example, a circuit which charges a battery using solar heat or infrared rays) and/or a battery-free system which directly uses received energy.

FIGS. 6A through 6Dillustrate an example of generating a virtual voltage level through a connection of capacitors operating in a counter phase, in accordance with one or more embodiments. Voltages levels ofFIGS. 6A through 6Dmay be the same as the voltage levels ofFIGS. 4A and 4B. Capacitors C1through C24ofFIGS. 6A through 6Dhave the same capacitance.

FIGS. 6A and 6Billustrate an example of forming a virtual voltage level through a connection between a capacitor in which a potential of a bottom plate thereof decreases by ΔV and a capacitor in which a potential of a bottom plate thereof increases by ΔV conversely. For example, a potential of a bottom plate of the capacitor C2decreases by ΔV, and conversely a potential of a bottom plate of the capacitor C12increases by ΔV. When bottom plates of capacitors having a potential difference of 2ΔV, among capacitors having the counter phase, are connected to each other, one capacitor is charged by ΔV, and the counter-phase capacitor is discharged by ΔV, whereby a virtual voltage level is formed between GND and VIN.

FIGS. 6C and 6Dillustrate an example of forming a virtual voltage level through a connection between a capacitor, in which a potential of a top plate thereof increases by ΔV, and a capacitor in which a potential of a top plate thereof decreases by ΔV conversely. For example, a potential of a top plate of the capacitor C10increases by ΔV, and conversely a potential of a top plate of the capacitor C16decreases by ΔV. When top plates of capacitors having a potential difference of 2ΔV, among capacitors having the counter phase, are connected to each other, one capacitor is charged by ΔV, and the counter-phase capacitor is discharged by ΔV, whereby a virtual voltage level is formed between VINand VOUT.

When a capacitor operating in the normal phase is connected to the capacitor operating in the counter phase, a virtual voltage level is formed such that an up-conversion switched-capacitor structure reducing a charge redistribution loss (CRL) is implemented. In this example, individual capacitors having a different potential difference for each phase are synchronized with a clock such that power is transferred from VINto VOUT.

FIG. 7illustrates an example of controlling capacitors to be positioned in Φ1through ΦP, in a state in which respective cells are synchronized with CLK<1:P>. In an example, it is assumed that P is “24”. Thus, a clock is CLK<1:24>, and there are cells1through24and phases Φ1through Φ24. The cell ofFIG. 3, which is applicable to a boost converter, may perform an operation as shown inFIG. 7.

In the example ofFIG. 7, virtual voltage levels of VBN<1>, VBN<2>, and VBN<3> may be formed between GND and an input voltage VINat an interval of ΔV, and virtual voltage levels of VTN<1>, VTN<2>, VTN<3>, VTN<4>, VTN<5>, VTN<6>, and VTN<7> may be formed between VINand VOUTat an interval of ΔV.

InFIG. 7, the capacitors C1through C24may be included in the cells1through24, respectively. For example, the capacitor C1is included in the cell1, and the capacitor C2is included in the cell2, and a capacitor CP (for example, capacitor C24) is included in a cell P (for example, cell24). That is, each cell may include a single capacitor.

In an example, at CLK<1>, the cell1may control the capacitor C1to be positioned in the phase Φ1. In this example, a top plate of the capacitor C1is connected to VIN, and a bottom plate thereof is connected to VBN<3>. At CLK<1>, the cell2may control the capacitor C2to be positioned in the phase Φ2. In this example, a top plate of the capacitor C2is connected to VIN, and a bottom plate thereof is connected to VBN<2>. At CLK<1>, the cell24may control the capacitor C24to be positioned in the phase Φ24. In this example, a top plate of the capacitor C24is connected to VIN, and a bottom plate of the capacitor C24is connected to VIN, and thus the capacitor C24is fully discharged.

At a subsequent clock CLK<2>, the cell1may control the capacitor C1to be positioned in the phase Φ2, the cell2may control the capacitor C2to be positioned in the phase Φ3, and the cell24may control the capacitor C24to be positioned in the phase Φ1. Further, at a subsequent clock CLK<3>, the cell1may control the capacitor C1to be positioned in the phase Φ3, the cell2may control the capacitor C2to be positioned in the phase Φ4, and the cell24may control the capacitor C24to be positioned in the phase Φ2. In this manner, the capacitors are sequentially positioned in the respective phases Φ1through Φ24based on the CLK<1:24>.

Here, the phases Φ1through Φ12each indicate a state in which a capacitor is charged, and the phases Φ13through Φ24each indicate a state in which a capacitor is discharged. For example, the phase Φ2indicates a state in which the capacitor C2is charged by CΔV as the bottom plate of the capacitor C2is connected from VBN<2> to VBN<1>, and the phase Φ23indicates a state in which the capacitor C23is discharged by CΔV as a top plate of the capacitor C23is connected from VTN<2> to VTN<1>.

Accordingly, when CLK<1:P> is sequentially shifted and input into cells, capacitors are charged or discharged by exchanging electric charge of CΔV for each shifting.

FIG. 8illustrates an example of binding two 180-shifted capacitors into a single cell with a counter phase. In this example, it is assumed that P is “24”. Thus, a clock CLK<1:P> is CLK<1:24>, a cell P is a cell24, and a phase ΦPis a phase Φ24. The cell ofFIG. 5, which may be applicable to a booster converter implementing a counter phase, may perform an operation as shown inFIG. 8.

In the example ofFIG. 8, virtual voltage levels of VBN<1>, VBN<2>, and VBN<3> may be formed between GND and an input voltage VINat an interval of ΔV, and virtual voltage levels of VTN<1>, VTN<2>, VTN<3>, VTN<4>, VTN<5>, VTN<6>, and VTN<7> may be formed between VINand VOUTat an interval of ΔV.

Unlike the example ofFIG. 7in which a single capacitor is included in each cell,FIG. 8illustrates an example in which capacitors operable using an inverted signal, among capacitors C1through C24, may be included in one cell. Specifically, among the capacitors C1through C12positioned in the charging phases Φ1through Φ12and the capacitors C13through C24positioned in the discharging phases Φ13through Φ24, two capacitors shifted 180 degrees may be included in one cell using a counter phase at CLK<1>.

In an example, the two capacitors shifted 180 degrees may be capacitors with ΔΦ=12. For example, at CLK<1>, the cell1includes the normal-phase capacitor C1positioned in the phase Φ1and the counter-phase capacitor C13positioned in the phase Φ13, and the cell12includes the normal-phase capacitor C12positioned in the phase Φ12and the counter-phase capacitor C24positioned in the phase Φ24. InFIG. 8, the counterphase capacitor C1,CNTis capacitor C13, and the counterphase capacitor C12,CNTis capacitor C24.

At a subsequent clock CLK<2>, the cell1may include the normal-phase capacitor C2positioned in the phase Φ2and the counter-phase capacitor C14positioned in the phase Φ14, and the cell12may include the normal-phase capacitor C13positioned in the phase Φ13and the counter-phase capacitor C1positioned in the phase Φ1. When CLK<1:P> is sequentially shifted and input into cells, capacitors are charged/discharged by exchanging electric charge of CΔV for each shifting.

When the counter phase is used as inFIG. 8, the operation ofFIG. 7is performed with a half of the total number of cells ofFIG. 7. For example, when P is “24”, 24 cells may be needed in the example ofFIG. 7, whereas the operation ofFIG. 7is performed using 12 cells in the example ofFIG. 8.

FIG. 9illustrates an example of a boost converter.

Referring toFIG. 9, a switch-cap type boost converter900implementing soft charging may include a clock divider910, a frequency controller920, and a cell930. In an example, the boost converter900transfers power from an input to an output through voltage up-conversion, and the cell930may include a plurality of cells. The cell930operates in the manner described with reference toFIGS. 7 and 8, and thus a duplicated description will be omitted for brevity.

The clock divider910sequentially executes CLK corresponding to the number of phases, and the frequency controller920senses an input voltage or an output voltage and controls the input or output voltage depending on a particular purpose of the boost converter9000. For example, in an example of a system voltage regulation, the frequency controller920may control a frequency to regulate the output voltage to a target voltage. Further, in example of a battery charger, the frequency controller920may control a frequency to regulate the output voltage to an input voltage at a maximum power point.

FIG. 10illustrates an example of a phase number adjusting circuit.FIG. 11illustrates an example of a change in virtual voltage levels N in response to a difference between VOUTand VIN.

A boost converter may further include a phase number adjusting circuit. InFIG. 10, N denotes the number of virtual voltage levels between VOUTand VIN, and M denotes the number of virtual voltage levels between VINand GND. In an example, M and N are determined such that the energy loss Plossoccurring in response to changes in VOUTand VINis minimized. In an example, Plossis determined based on a charge redistribution loss (CRL) and a switching loss SWloss.

InFIG. 11, a graph1110,1130is a graph of a CRL occurring in response to a difference between VOUTand VIN, and a graph1120,1140is a graph of a switching loss SWloss occurring in response to a difference between VOUTand VIN.

NOPT1is determined based on the CRL1130and the switching loss1140when a difference between VOUT1and VINis less than a difference between VOUT2and VIN. NOPT2is determined based on the CRL1110and the switching loss1120when the difference between VOUT2and VINis greater than the difference between VOUT1and VIN. That is, when VOUTchanges, NOPTminimizing the power loss changes. The phase number adjusting circuit ofFIG. 10determines NOPTminimizing the power loss.

Similarly, MOPTminimizing the power loss is determined based on a difference between VINand GND. The phase number adjusting circuit ofFIG. 10determines MOPTminimizing the power loss.

In detail, the phase number adjusting circuit ofFIG. 10determines NOPTand MOPTminimizing the power loss based on the following equations. A CRL occurring per hour is determined based on Equation 3 below. In Equation 3, fclk denotes an operation count of a cell per second, and Cflydenotes a capacitance of a capacitor included in each cell.

A CRL of Cfly*(VIN/M)2occurs on a bottom plate due to a potential change of (VIN/M) in a capacitor with the capacitance Cfly. Thus, a CRL of 2M*Cfly*(VIN/M)2occurs on 2M bottom plates. Similarly, a CRL of 2N*Cfly*((VOUT−VIN)/N)2occurs on a top plate. A CRL of 2M*Cfly*(VIN/M)2+2N*Cfly*((VOUT−VIN)/N)2occurs in response to a single phase change, and thus the CRL occurring per hour is expressed by Equation 3.

A switching loss SWloss is determined based on Equation 4 below. In Equation 4, α denotes a coefficient for reflecting a switching loss caused by a parasitic capacitor existing in a control circuit, and β denotes a coefficient for reflecting a switching loss caused by a parasitic capacitor existing in a booster.
fclk[2(M+N)*αVIN2+2N*βVOUT2]  Equation 4:

The power loss Plossis determined based on Equation 5 below. Thus, the phase number adjusting circuit determines N and M such that Plossis minimized in response to changes in VOUTand/or VIN.

FIG. 12illustrates an example of a phase number adjusting circuit considering a start-up.FIGS. 10 and 11illustrate an example in which a phase number adjusting circuit determines N and M such that an energy loss Ross occurring in a steady state is minimized, whileFIG. 12illustrates a process before the steady state is reached.

By dynamically adjusting the number of virtual voltage levels generated for soft charging, an operation is performed with an optimal efficiency depending on an application, or a start-up time is advanced. For example, when the number of virtual voltage levels decreases by binding several virtual voltage levels, a capacitance of each capacitor increases, a pumping capacity improves, and thus a fast start-up is enabled. In this example, when there are a relatively large number of virtual voltage levels, a power consumption for moving electric charge between capacitors decreases, while a switching power consumption for generating each voltage level increases. Conversely, when there are a relatively few number of virtual voltage levels, the power consumption for moving electric charge between capacitors increases, while the switching power consumption decreases. Thus, an optimal efficiency is obtained by determining the number of virtual voltage levels appropriate for input and output voltages and an output power situation. Further, in a hybrid form, a fast start-up time is obtained by binding several virtual voltage levels at an early stage, and the number of virtual voltage levels may be adjusted to be suitable for the optimal efficiency after the start-up.

In an example, an output current IOUTcorresponding to an output voltage VOUTis expressed by Equation 6 below. In an example, unit capacitance denotes a capacitance Cflyof a capacitor in each cell. If there are a total of 2(N+M) cells, the total capacitance Ctotal=2(N+M)*Cflyis satisfied.
IOUT=frequency*number of cells*ΔV*unit capacitance  Equation 6:

An output current IOUT_normalin the steady state is expressed by Equation 7 below, and an output current IOUT_start-upin the start-up process is expressed by Equation 8 bellow. Thus, when IOUTincreases by binding K capacitors in a cell at an early stage, a start-up time from a start point to a point where the steady state is reached decreases. That is, when a start-up signal indicating an initial state is received, the phase number adjusting circuit increases K, increases IOUT, quickly increases VOUT, and thereby decreases the start-up time. After that, when VOUTreaches a target voltage, K decreases to improve the efficiency.

FIG. 13illustrates an example of an efficiency and QOUTwhen soft charging is implemented.

When an interval of virtual voltage levels is uniformly ΔV, CΔV transmitted from an input to an output in a single cycle is constant. Thus, a uniform efficiency is maintained despite a change in a ratio of the input and the output. Here, ΔV=VIN/N is determined irrespective of VOUT, whereby the uniform efficiency is maintained. That is, when soft charging is implemented, the peak efficiency and the average efficiency may have similar values, and thus a relatively high efficiency may be maintained.

FIG. 14illustrates an example of a change in potential of a top plate of a capacitor and a change in potential of a bottom plate of the capacitor. A capacitor is charged or discharged by soft charging as a phase changes based on a CLK. Specifically, i) in a period of charging, Charging1, the capacitor is charged as a potential of a bottom plate of the capacitor changes from VINto GND while a potential of a top plate of the capacitor is uniformly VIN. Further, ii) in a period of charging, Charging2, the capacitor is charged as the potential of the top plate of the capacitor changes from VINto VOUTwhile the potential of the bottom plate of the capacitor is uniformly GND. Further, iii) in a period of discharging, Discharging1, the capacitor is discharged as the potential of the bottom plate of the capacitor changes from GND to VINwhile the potential of the top plate of the capacitor is uniformly VOUT. Further, iv) in a period of discharging, Discharging2, the capacitor is discharged as the potential of the top plate of the capacitor changes from VOUTto VINwhile the potential of the bottom plate of the capacitor is uniformly VIN.