Floating switch and drive circuit thereof

An apparatus can include: a drive circuit for a floating switch having first and second transistors coupled in series, where gate terminals of the first and second transistors are coupled together, and source terminals of the first and second transistors are coupled together; a control circuit coupled to the gate terminals of the first and second transistors, and being configured to control on and off states of the first and second transistors; and a clamp circuit configured to clamp gate-source voltages of the first and second transistors to maintain current switching states of the first and second transistors.

RELATED APPLICATIONS

This application claims the benefit of Chinese Patent Application No. 201811290979.5, filed on Oct. 31, 2018, which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention generally relates to the field of power electronics, and more particularly to floating switches and associated drive circuitry.

BACKGROUND

A switched-mode power supply (SMPS), or a “switching” power supply, can include a power stage circuit and a control circuit. When there is an input voltage, the control circuit can consider internal parameters and external load changes, and may regulate the on/off times of the switch system in the power stage circuit. Switching power supplies have a wide variety of applications in modern electronics. For example, switching power supplies can be used to drive light-emitting diode (LED) loads.

DETAILED DESCRIPTION

In analog integrated circuits, floating switches are widely used in high-voltage digital-to-analog converters, high-voltage multiplexers, high-voltage amplifiers with adjustable gains, and the like. The driving signal of the floating switch can be generated by a driving circuit and a level shifter. When the floating switch is turned on, current may flow from the driving circuit to the node of the floating switch, which can affect the accuracy of the node of the floating switch.

Referring now toFIG. 1, shown is a schematic block diagram of an example high voltage multiplexer with a floating switch. In this example, high voltage multiplexer1can include floating switch11, and floating switch11can include switch S and drive circuit111. Drive circuit111can control the on and off states of switch S to obtain different output voltages at output terminal “o.” Since the voltage at both ends of switch S varies, it is expected that switch S exhibits the characteristics of an ideal switch; that is, switch S itself may not exert any influence on the voltage at both ends of switch S, which can be important in applications that require higher accuracy.

Referring now toFIG. 2, shown is a schematic block diagram of an example floating switch. In this particular example, floating switch11can include drive circuit2and transistors Q1and Q2. Gate terminals of transistors Q1and Q2can be commonly connected with each other and source terminals of transistors Q1and Q2may be commonly connected with each other. Drive circuit2can include voltage source U1, control circuit21, and level shifter22. Also, the source terminals of transistors Q1and Q2can be connected to one end of voltage source U1(e.g., a negative electrode of voltage source U1). Control circuit21can connect to the gate terminals of transistors Q1and Q2for controlling the on and off states of transistors Q1and Q2.

Level shifter22can convert the level of logic signal log to drive control circuit21to generate drive signal GATE for transistors Q1and Q2. Voltage source U1can supply power for control circuit21and level shifter22. Since the source terminals of transistors Q1and Q2are connected to voltage source U1, when transistors Q1and Q2are turned on, a current may flow from drive circuit2to the source terminals of transistors Q1and Q2, thereby affecting the accuracy of the circuit. That is, in the high voltage multiplexer to which the floating switch is applied, when switch S is turned on, a current may flow from drive circuit111to one end of switch S, thereby affecting the current flowing to output terminal o, which may reduce the accuracy of the high voltage multiplexer. In particular embodiments, when the floating switch is in an on state, no current may flow from its drive circuit to source terminals of transistors in the floating switch, thereby improving the accuracy of the circuit.

In one embodiment, an apparatus can include: (i) a drive circuit for a floating switch having first and second transistors coupled in series, where gate terminals of the first and second transistors are coupled together, and source terminals of the first and second transistors are coupled together; (ii) a control circuit coupled to the gate terminals of the first and second transistors, and being configured to control on and off states of the first and second transistors; and (iii) a clamp circuit configured to clamp gate-source voltages of the first and second transistors to maintain current switching states of the first and second transistors.

Referring now toFIG. 3, shown is a schematic block diagram of a first example floating switch, in accordance with embodiments of the present invention. In this particular example, floating switch3can include transistors Q31and Q32and drive circuit31. Similarly, gate terminals of transistors Q31and Q32can be commonly connected with each other and source terminals of transistors Q31and Q32may be commonly connected with each other. Also, drive circuit31can connect to the gate terminals and source terminals of transistors Q31and Q32, and may generate drive signals for transistors Q31and Q32to control on and off states of transistors Q31and Q32. For example, transistors Q31and Q32can be metal-oxide-semiconductor field-effect transistors (MOSFETs) of the same channel type. In particular embodiments, transistors Q31and Q32are both N-channel transistors.

Drive circuit31can include control circuit311and clamp circuit312. Control circuit311can connect to the gate terminals of transistors Q31and Q32, and may control on and off states of transistors Q31and Q32according to logic signal logic1. Clamp circuit312can clamp the gate-source voltages of transistors Q31and Q32according to logic signal logic1, in order to maintain the current switching states of transistors Q31and Q32. Also, no current may flow from drive circuit31to the source terminals of transistors Q31and Q32due to clamp circuit312.

After logic signal logic1switches to a first state, transistors Q31and Q32can be controlled to be turned on by control circuit311, and the gate-source voltages of transistors Q31and Q32can be clamped to a “first” predetermined value by clamp circuit312, such that transistors Q31and Q32remain in the turn-on states. After logic signal logic1switches to a second state, transistors Q31and Q32can be controlled to be turned off by control circuit311, and the gate-source voltages of transistors Q31and Q32can be clamped to a “second” predetermined value by clamp circuit312, such that transistors Q31and Q32maintain in the turn-off states. It is easy to understand that the first and second predetermined values and can be set according to the conduction conditions of transistors Q31and Q32.

Control circuit311can include current source I1, switch S1, and current source I2coupled in series between pull-up power supply terminal Vcc and a ground. Current source I1can connect between pull-up power supply terminal Vcc and the gate terminal of transistor Q31. Switch S1can connect in series between current sources I1and I2, and may be controlled to be turned on or off by logic signal logic1. Current source I2can connect between switch S1and the ground. In addition, an output current of current source I2may be greater than an output current of current source I1. In some examples, the output current of current source I2may be twice the output current of current source I1.

After logic signal logic1switches to the first state, switch S1can be controlled to be turned off. Thus, current source I1can charge parasitic capacitor C1of transistor Q31, such that the gate-source voltage of transistor Q31satisfies the conduction condition, and then the transistor Q31may be turned on. After logic signal logic1switches to the second state, switch S1can be controlled to turn on, and the output current of current source I1may flow to current source I2through switch S1. Since the output current of current source I2is greater than the output current of current source I1, current source I2may also need to draw current I3from the parasitic capacitor C1of transistor Q31(e.g., parasitic capacitor C1can be discharged) to make the current reach a balance. That is to say, I2=I1+I3at this time. Thus, the gate-source voltage of transistor Q31can gradually decrease, such that transistor Q31can be turned off.

It should be understood that since the gate terminals of transistors Q31and Q32are commonly connected with each other, and the source terminals of transistors Q31and Q32are commonly connected with each other, the on and off states of transistor Q32may be consistent with (e.g., the same as) that of transistor Q31. Clamp circuit312can include transistor Q33, transistor Q34, and diodes D1and D2. The channel type of transistor Q33may be opposite to that of transistor Q31, and the channel type of transistor Q34can be the same as that of transistor Q31. That is, in some examples, transistor Q33is a P-channel transistor and transistor Q34is an N-channel transistor.

In particular embodiments, diodes D1, D2and transistor Q33can be sequentially connected in series between the gate terminal of transistor Q31and the ground. A source terminal of transistor Q33can connect to a cathode of diode D2, and a drain terminal of transistor Q33can connect to the ground. Transistor Q34can connect between pull-up power supply terminal Vcc and the gate terminal of transistor Q32. A drain terminal of transistor Q34can connect to pull-up power supply terminal Vcc, and a source terminal of transistor Q34can connect to the gate terminal of transistor Q32. In particular embodiments, gate terminals of transistors Q33and Q34can connect with each other, and to the source terminals of transistors Q31and Q32. Since the gate terminals of the transistors substantially have no current flowing in or out, and the source terminals of transistors Q31and Q32can be connected to the gate terminals of transistors Q33and Q34, when transistors Q31and Q32are turned on, substantially no current may flow from drive circuit31to the source terminals of transistors Q31and Q32, such that no current flows to both ends of the floating switch to affect the voltage at both ends. Therefore, the accuracy of the circuit can be improved.

In particular embodiments, diodes D1and D2can adjust the clamp voltage of clamp circuit312, such that the clamp voltage is sufficient to maintain the current switching states of transistors Q31and Q32. In this particular example, only two diodes are shown, but those skilled in the art will recognize that the number and parameters of diodes in the clamp circuit can be determined according to the conduction condition of transistors Q31and Q32.

In particular embodiments, after logic signal logic1switches to the first state, switch S1can be controlled to be turned off. Then, current source I1may begin to charge parasitic capacitor C1of transistor Q31, such that gate voltage Vg1of transistor Q31gradually increases, and gate-source voltage Vgs1also gradually increases. When gate-source voltage Vgs1of transistor Q31meets the conduction conditions, transistor Q31can be controlled to be turned on. In this example, the source terminal of transistor Q33can be coupled to the gate terminal of transistor Q31through diodes D1and D2, and the gate terminal of transistor Q33can connect coupled to the source terminal of transistor Q31. Therefore, source voltage Vs3of transistor Q33may equal Vg1−Vd1−Vd2(where Vd1and Vd2are conduction voltage drops of diodes D1and D2, respectively), and gate voltage Vg3of transistor Q33may be equal to source voltage Vs1of transistor Q31.

When current source I1charges parasitic capacitor C1of transistor Q31, source-gate voltage Vsg3of transistor Q33may also gradually increase, such that after transistor Q31is turned on, source-gate voltage Vsg3of transistor Q33can meet its conduction condition and then transistor Q33may be controlled to be turned on. After transistor Q33is turned on, gate-source voltage Vgs1of transistor Q31can be clamped to Vg1−Vs1. That is, Vgs1=(Vs3−Vg3)+Vd1+Vd2(e.g., the source-gate voltage of transistor Q33plus the conduction voltage drops of diodes D1and D2). Thus, transistor Q31can continue to be turned on.

When logic signal logic1is in the second state, switch S1may be controlled to turn on, and the output current of current source I1may flow to current source I2through switch S1. Since the output current of current source I2is greater than the output current of current source IL current source I2may also need to draw current I3from parasitic capacitor C1of transistor Q31(e.g., parasitic capacitor C1is discharged) to make the current reach a balance. Thus, gate voltage Vg1of transistor Q31can begin to decrease to turn off transistor Q31. Since the source terminal of transistor Q34is connected to the gate terminal of transistor Q31, and the gate terminal of transistor Q34is connected to the source terminal of transistor Q31, the source voltage of transistor Q34can gradually decrease, such that the gate-source voltage of transistor Q34may meet the corresponding conduction condition, and then transistor Q34can be controlled to be turned on.

After transistor Q34is turned on, a current loop can be formed from pull-up power supply terminal VCC—transistor Q34—switch S1—current source I2, in order to maintain the current balance. Therefore, current source I2may no longer draw current from parasitic capacitor C1, such that the gate-source voltage of transistor Q31may be clamped to a negative value, thereby maintaining the off-state of transistor Q31. It should be understood that since the gate terminals of transistors Q31and Q32are commonly connected with each other, and the source terminals of transistors Q31and Q32are commonly connected with each other, the on and off states of transistor Q32may be consistent with that of transistor Q31.

In some examples, transistors Q31and Q32can be configured as high voltage transistors, such that the floating switch may have a higher withstand voltage. In this case, the conduction voltages of transistors Q31and Q32may be different from that of switch S1. Although switch S1is a low-voltage switch, since clamp circuit312is controlled by the current, and the first and second predetermined values can be adjusted by adjusting the number and parameters of diodes, the drive circuit of the floating switch can control the on and off states of the high-voltage transistors through the low-voltage switch without requiring a level shifter, which can simplify the circuit structure and reduce costs.

In particular embodiments, the switching states of transistors Q31and Q32may be controlled according to a logic signal, and the gate-source voltages of transistors Q31and Q32can be clamped by a clamp circuit, in order to maintain current switching states of transistors Q31and Q32while causing no current to flow from the drive circuit to the source terminals of transistors Q31and Q32, thereby improving the accuracy of the circuit.

Referring now toFIG. 4, shown is a waveform diagram of example operation of the first example floating switch, in accordance with embodiments of the present invention. During time t0-t1, logic signal logic1is at a low level (e.g., in the first state), switch S1may remain in the off state, and gate-source voltages of transistor Q31and transistor Q32can be clamped at predetermined value V1by clamp circuit312. In particular embodiments, transistors Q31and Q32are N-channel transistors, such that transistors Q31and Q32can be maintained in the on state when the gate-source voltages of transistors Q31and Q32are at predetermined value V1. For example, predetermined value V1may be set according to the conduction conditions of transistors Q31and Q32.

During time t1-t2, logic signal logic1is at a high level (e.g., in the second state), switch S1may remain in the on state, and clamp circuit312can clamp the gate-source voltages of transistors Q31and Q32at predetermined value V2. Since predetermined value V2is less than 0, transistors Q31and Q32can be maintained in the off state during time t1-t2. Since the source terminals of transistors Q31and Q32are connected to the gate terminals of transistors Q33and Q34in clamp circuit312, no current may flow from drive circuit31to the source terminals of transistors Q31and Q32when transistors Q31and Q32are turned on, thereby improving the accuracy of the circuit.

Referring now toFIG. 5, shown is a schematic block diagram of an example drive circuit for the first example floating switch in accordance with embodiments of the present invention. In this particular example, drive circuit31can include current sources I1and I2. Both current source I1and current source I2can be mirror current sources. Current source I1can include transistors Q3and Q4. The gate terminals of transistors Q3and Q4can be commonly connected with each other and the source terminals of transistors Q3and Q4can be commonly connected with each other. That is, current source I1can be a cascode current mirror. Also, current source I1may generate an output current according to input bias voltage Bias1. In addition, current source I2can include transistors Q5and Q6.

The gate terminals of transistors Q5and Q6can be commonly connected with each other and the source terminals of transistors Q5and Q6can be commonly connected with each other. That is, current source I2may also be a cascode current mirror. Also, current source I2can generate an output current according to input bias voltage Bias2. Therefore, the output current of current source I2can be greater than the output current of current source I1by setting the parameters of input bias voltages Bias1and Bias2. While current sources I1and I2are exemplified herein, other circuits capable of realizing the current source function can alternatively be applied in certain embodiments.

Referring now toFIG. 6, shown is a schematic block diagram of a second example floating switch, in accordance with embodiments of the present invention. In this particular example, floating switch6can include transistors Q61and Q62and drive circuit61. Gate terminals of transistors Q61and Q62can be commonly connected with each other and source terminals of transistors Q61and Q62can be commonly connected with each other. Drive circuit61can connect to the gate terminals and source terminals of transistors Q61and Q62, and may generate drive signals to control transistors Q61and Q62to be turned on and off. Transistors Q61and Q62can be metal-oxide-semiconductor field-effect transistors (MOSFET) of the same channel type. In this particular example, transistors Q61and Q62may both be P-channel transistors.

Drive circuit61can include control circuit611and clamp circuit612. Control circuit611can be coupled to the gate terminals of transistors Q61and Q62, and may control on and off states of transistors Q61and Q62according to logic signal logic2. Clamp circuit612can clamp the gate-source voltages of transistors Q61and Q62according to logic signal logic2, in order to maintain the current switching states of transistors Q61and Q62, and no current may flow from drive circuit61to the source terminals of transistors Q61and Q62due to clamp circuit612.

After logic signal logic2switches to the first state, transistors Q61and Q62can be controlled to be turned off by control circuit611. Gate-source voltages of transistors Q61and Q62can be clamped to a “first” predetermined value by clamp circuit612, such that transistors Q61and Q62remain in the off states. After logic signal logic2switches to the second state, transistors Q61and Q62can be controlled to be turned on by control circuit611. The gate-source voltages of transistors Q61and Q62can be clamped to a “second” predetermined value by clamp circuit612, such that transistors Q61and Q62remain in the on states. For example, the first and second predetermined values can be set according to the conduction conditions of transistors Q61and Q62.

Control circuit611can include current source I3, switch S2, and current source I4, coupled in series between pull-up power supply terminal Vcc and the ground. In some examples, current sources I3and I4can be mirror current sources. Current source I3can connect between pull-up power supply terminal Vcc and the gate terminal of transistor Q62. Switch S2can connect between current sources I3and I4, and may be controlled to be turned on or off by logic signal logic2. Current source I4can connect between switch S2and the ground. In addition, an output current of current source I4may be greater than an output current of current source I3. In some examples, the output current of current source I4can be twice the output current of current source I3.

After logic signal logic2switches to the first state, switch S2may be controlled to be turned off. Then, current source I3can charge parasitic capacitor C2of transistor Q62, such that transistor Q62may be controlled to be turned off. After logic signal logic2switches to the second state, switch S2can be controlled to turn on, and the output current of current source I3may flow to current source I4through switch S2. Since the output current of current source I4is greater than the output current of current source I3, current source I4may also need to draw a current from parasitic capacitor C2of transistor Q62(e.g., parasitic capacitor C2is discharged) to balance the current. Thus, the gate-source voltage of transistor Q62may gradually decrease to meet the conduction conditions, and then transistor Q62can be controlled to be turned on. It should be understood that since the gate terminals of transistors Q61and Q62are commonly connected with each other, and the source terminals of transistors Q61and Q62are commonly connected with each other, the on and off states of transistor Q61can be consistent with that of transistor Q62.

Clamp circuit612can include transistor Q63, transistor Q64, and diodes D3and D4. The channel type of transistor Q63may opposite to that of transistor Q61, and the channel type of transistor Q64can be the same as that of transistor Q61. For example, transistor Q63is an N-channel transistor, and transistor Q64is a P-channel transistor. Transistor Q63, diodes D3and D4can be sequentially coupled in series between pull-up power supply terminal Vcc and the gate terminal of transistor Q62. A source terminal of transistor Q63can connect to the anode of diode D3, and a drain terminal of transistor Q63can connect to pull-up power supply terminal Vcc. Transistor Q64can connect between the ground and the gate terminal of transistor Q61. A drain terminal of transistor Q64can connect to the ground, and a source terminal of transistor Q64can connect to the gate terminal of transistor Q61.

Also, gate terminals of transistors Q63and Q64may be commonly connected with each other, and can connect to the source terminals of transistors Q61and Q62. Since the gate terminals of the transistors have substantially no current flowing in or out, and the source terminals of transistors Q61and Q62are connected to the gate terminals of the transistors Q63and Q64, when transistors Q61and Q62are turned on, substantially no current may flow from drive circuit61to the source terminals of transistors Q61and Q62, such that no current may flow to both ends of the floating switch to affect the voltage at both ends. Thus, the accuracy of the circuit can be improved. In particular embodiments, diodes D3and D4can adjust the clamp voltage of clamp circuit612, such that the clamp voltage is sufficient to control transistors Q61and Q62to be turned on. While two diodes are exemplified herein, those skilled in the art will recognize that the number and parameters of diodes in clamp circuit612can be adjusted according to the conduction conditions of transistors Q61and Q62.

After logic signal logic2switches to the first state, switch S2can be controlled to be turned off. Then, current source I3may begin to charge parasitic capacitor C2of transistor Q62, and the gate voltage of transistor Q62can gradually increase, such that transistor Q62may be controlled to be turned off. For example, the source terminal of transistor Q64can connect to the gate terminal of transistor Q62, the gate terminal of transistor Q64can connect to the source terminal of transistor62, and the channel type of transistor Q64may be the same as that of transistor Q62. Therefore, when current source I3starts to charge parasitic capacitor C2of transistor Q62, the source voltage of transistor Q64may gradually increase, such that after transistor Q62is turned off, the source-gate voltage of transistor Q64meets the conduction condition, and transistor Q64is controlled to be turned on. After transistor Q64is turned on, the source-gate voltage of transistor Q62can be clamped to a greater positive value, such that transistor Q64can maintain in an off state.

After logic signal logic2switches to the second state, switch S2may be controlled to be turned on, and the output current of current source I3can flow to current source I4through switch S2. Since the output current of current source I4is greater than the output current of current source I3, current source I4may also need to draw a current from parasitic capacitor C2of transistor Q62(e.g., parasitic capacitor C2is discharged) to balance the current. Thus, the gate voltage of transistor Q62may gradually be reduced, such that the source-gate voltage of transistor Q62satisfies the conduction condition, and then transistor Q62can be controlled to be turned on. Since the source terminal of transistor Q63is coupled to the gate terminal of transistor Q62through diodes D3and D4and the gate terminal of transistor Q63is connected to the source terminal of transistor Q62, when the gate voltage of transistor Q62decreases, the source voltage of transistor Q63can accordingly decrease.

Therefore, after transistor Q62is turned on, the gate-source voltage of transistor Q63may meet the conduction condition and transistor Q63can be controlled to be turned on. After transistor Q63is turned on, a current loop of pull-up power supply terminal Vcc—transistor Q63—diode D3—diode D4—switch S2—current source I4may be formed to maintain current balance. Therefore, current source I4may no longer draw current from parasitic capacitor C2, such that the source-gate voltage of transistor Q62is clamped to a negative value, thereby maintaining the on-state of transistor Q62. It should be understood that since the gate terminals of transistors Q61and Q62are commonly connected with each other, and the source terminals of transistors Q61and Q62are commonly connected with each other, the on and off states of transistor Q61may be consistent with that of transistor Q62.

In some embodiments, transistors Q61and Q62can be configured as high voltage transistors, such that the floating switch can have a higher withstand voltage. In this case, the conduction voltages of transistors Q61and Q62may be different from that of switch S2. Although switch S2is a low-voltage switch, since clamp circuit612is controlled by current, and the predetermined values can be adjusted by adjusting the number and parameters of diodes, the drive circuit of the floating switch can realize the function of controlling the on and off states of the high-voltage transistors through the low-voltage switch without requiring a level shifter, which can simplify the circuit structure and reduce costs.

In particular embodiments, the switching states of transistors Q61and Q62may be controlled according to a logic signal, and the gate-source voltages of transistors Q61and Q62can be clamped by a clamp circuit, in order to maintain current switching states of transistors Q61and Q62while causing no current to flow from the drive circuit to the source terminals of transistors Q61and Q62, thereby improving the accuracy of the circuit.

Referring now toFIG. 7, shown is a waveform diagram of example operation of the second example floating switch, in accordance with embodiments of the present invention. In this particular example, during time t3-t4, logic signal logic2is at a low level (e.g., in the first state), switch S2remains in the off state, and the gate-source voltage of transistors Q61and Q62can be clamped at predetermined value V3by clamp circuit612. For example, transistors Q61and Q62are P-channel transistors, such that transistors Q61and Q62can be maintained in the off state when the gate-source voltage of transistors Q61and Q62are predetermined value V3. For example, predetermined value V3can be set according to the conduction conditions of transistors Q61and Q62.

During time t4-t5, logic signal logic2is at a high level (e.g., in the second state), switch S2remains on, and clamp circuit612can clamp gate-source voltage Vgs2of transistors Q61and Q62at predetermined value V4. Since predetermined value V4is less than 0, transistors Q61and Q62can be maintained in the on states during time t4-t5. Since the source terminals of transistors Q61and Q62are connected to the gate terminals of transistors Q63and Q64in clamp circuit612, when transistors Q61and Q62are turned on, no current may flow from drive circuit61to the source terminals of transistors Q61and Q62, thereby improving the accuracy of the circuit.