Liquid crystal display device having particular connections among drain and pixel electrodes and contact hole

A liquid crystal display device and a method of fabricating the same are disclosed. The device, as disclosed, reduces the number of masks required to fabricate. Thus, cost is reduced and yield is increased. The device includes a plurality of gate lines, a plurality of data lines crossing the gate lines such that active regions are defined near the crossover points, thin film transistors are formed near the active regions, and a plurality of pixel electrodes are formed within regions defined by the adjacent gate and data lines. Also, pixel electrodes overlap gate lines and the two electrodes function as a storage capacitor. A fabrication method includes forming a gate line; forming a data line region, protections layers, and an active area where drain and source electrodes are spaced apart a predetermined distance; forming a data line, a gate line protection layer, and a gate insulating layer; and forming pixel electrodes by depositing a transparent conductive material, such that each pixel electrode also overlaps a portion of a gate line.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a device and method for fabricating the LCD device having a thin film transistor (TFT).

2. Discussion of the Prior Art

Generally, an LCD device includes top and bottom glass substrates and a liquid crystal injected therebetween. On the bottom glass substrate, a plurality of gate lines extending in one direction and a plurality of data lines extending in perpendicular direction are formed. In this matrix arrangement, a plurality of TFTs are disposed near the crossover points of the data and gate lines.

On the top glass substrate, red (R), green (G) and blue (B) color filter layers and a common electrode are disposed. Generally, a light shielding layer (black matrix) is formed on the top glass substrate and a pair of polarizers are disposed on the outer surfaces of the top and bottom glass substrates to selectively transmit light.

A conventional LCD device will be described in detail below with reference toFIG. 1, which is a plan view of a conventional LCD device.

As illustrated inFIG. 1, the conventional LCD device includes a plurality of gate lines22formed on a transparent substrate, a plurality of data lines24perpendicularly crossing the gate lines22, a plurality of TFTs “S” formed near the crossover points of the gate and data lines22and24, and a plurality of pixel electrodes14connected to the TFTs “S”. The gate lines22are separated by intervals from each other and extend in one direction, whereas the data lines24are separated by intervals from each other and extend in a perpendicular direction to the gate lines22. Each end portion of gate and data lines22and24has gate and data pads21and23, respectively. A storage capacitor “Cst” is arranged on a predetermined portion of the gate line22. Two adjacent gate lines22and two adjacent data lines24define the boundaries of a pixel region. In each pixel region, a TFT “S” and a pixel electrode14are disposed.

Each TFT includes a gate electrode26, a source electrode28and a drain electrode30. A gate insulating layer is formed between the gate and source electrodes28and30and between the gate and drain electrodes26and30. The gate electrode26extends from the gate line22and the source electrode28extends from the data line24. The drain electrode30connects the pixel electrode14through a contact hole31.

The TFT transmits a signal of the data line24to the pixel electrode14in response to a signal of the gate line22.

In the conventional LCD device having the above-described TFTs, if a signal voltage is applied to the gate electrode26, the TFT is turned on so as to transmit a data voltage representing picture data to the pixel electrode14and the liquid crystal.

FIGS. 2A to 2Eshow fabrication process steps of an active matrix liquid crystal display device according to the conventional art.

First, a first metal layer is deposited on a substrate1by a sputtering process after a cleaning process in order to remove organic materials and alien substances from the substrate1, thereby enhancing adhesion between the substrate1and the metal layer.FIG. 2Ashows a step for forming a gate electrode26and a first capacitor electrode22by patterning the first metal layer using a first mask.

A low resistance metal such as aluminum is used to form the gate electrode26so as to reduce the RC delay. However, pure aluminum has weak resistance to most enchants and may result in line defects due to a formation of a hillock during a high temperature process. Thus, an aluminum alloy is used. And in some cases, a double layered gate is used wherein another metal layer covers the aluminum or aluminum alloy.

A gate insulating layer50is deposited on the whole surface of the substrate1covering the gate and capacitor electrodes26and22. Then, a pure amorphous silicon (a-Si:H) layer52and a doped amorphous silicon (n+a-Si:H) layer54are deposited sequentially on the gate insulating layer50.

As shown inFIG. 2B, an active layer55and a semiconductor island53are formed by patterning the silicon layers52and54using a second mask. The doped amorphous silicon layer54(i.e. ohmic contact layer) reduces the contact resistance between the active layer55and an electrode which is formed later.

FIG. 2Cshows a step for forming a data line24, source and drain electrodes28and30by depositing a second metal layer. At the same time, a second capacitor electrode58is formed on the gate insulating layer50, covering a portion of the first capacitor electrode22.

Then, the ohmic contact layer between the source and drain electrodes28and30is etched using the source and drain electrodes28and30as a mask.

As depicted inFIG. 2D, an insulating layer is deposited on the entire surface of the substrate1covering the source and drain electrodes28and30. The insulating layer is patterned using a fourth mask to form a protection film56. The protection film56may be selected from inorganic materials such as SiNxand SiO2or organic materials such as a BCB (benzocyclobutene). In addition, a material having a high light transmittance, humidity resistance and durability is used to form the protection film56in order to protect the channel area of the TFT and major portions of a pixel region from possible exposure to humidity and scratches during later processing steps.

Further, a data pad contact hole33is formed on the data pad23, and drain and capacitor contact holes31and59are formed on the drain electrode30and the second capacitor electrode58, respectively.

FIG. 2Eshows a step for forming a pixel electrode14by depositing a transparent conducting oxide (TCO) layer15and patterning it using a fifth mask. Indium tin oxide (ITO) is usually employed for the transparent conducting oxide layer. The pixel electrode14contacts the second capacitor electrode58through the capacitor contact hole59and the drain electrode30through the drain contact hole31. Another portion of the transparent conducting oxide layer15is also formed contacting the data pad23through the data pad contact hole33.

As described, the conventional art requires at least five masks in fabricating the TFT array panel of the LCD device, and each mask process requires many steps such as cleaning, depositing, baking and etching. Therefore, if the number of mask processes is reduced, even if only by one, then production would be increased and cost would be decreased.

SUMMARY OF THE INVENTION

Therefore it is an object of the present invention to provide a thin film transistor array panel of a liquid crystal display device and methods of forming the same that eliminates the problems of conventional methods.

A further object of the present invention is to fabricate the liquid crystal display device with a high yield and a reduced fabrication time. The present invention provides, in one embodiment, a method for fabricating a liquid crystal display array panel, comprising the steps of: forming a gate line by depositing a first metal layer on a substrate and patterning the first metal layer using a first mask; depositing an insulating layer, a pure amorphous silicon layer, a doped amorphous silicon layer and a second metal layer sequentially on the entire surface of the substrate and covering the gate line; forming a data line region, a gate line protection layer and an active area by patterning the second metal layer and the doped amorphous silicon layer using a second mask, the data line region having a source electrode and the gate line protection layer having a drain electrode spaced at a predetermined distance from the source electrode; depositing a protection layer on the entire surface of the substrate while covering the data line region, the gate line protection layer and the active area; forming a data line, a protection film and a gate insulating layer using a third mask; depositing a transparent conductive material on the entire surface of the substrate while covering the data line and the source and drain electrodes; and forming a pixel electrode and exposing a portion of the gate line using a fourth mask, the pixel electrode being connected with the drain electrode, the exposed portion extending from the active area.

The present invention provides, in another embodiment, a method for fabricating a liquid crystal display device, comprising steps of: forming a gate line by depositing a first metal layer on a substrate and patterning the first metal layer using a first mask; depositing an insulating layer, a pure amorphous silicon layer, a doped amorphous silicon layer and a second metal layer sequentially on the entire surface of the substrate and covering the gate line; forming an active area using a second mask by selectively patterning the second metal layer and the pure amorphous silicon layer, the second metal layer covering the entire surface of the substrate except for the active area; depositing a protection layer on the entire surface of the substrate while covering the data line region, the gate line protection layer and the active area; forming a data line, a protection film, a gate insulating layer, and source and drain electrodes by patterning the second metal layer, the pure amorphous metal layer, the doped amorphous silicon layer and the insulating layer using a third mask; depositing a transparent conductive material on the entire surface while covering the data line and the source and drain electrodes; and forming a pixel electrode and exposing a portion of the gate line using a fourth mask, the pixel electrode being connected with the drain electrode, the exposed portion extending from the active area.

The present invention provides, in a further embodiment, a method for fabricating a liquid crystal display device, comprising steps of: forming a gate line by depositing a first metal layer on a substrate and patterning the first metal layer using a first mask; depositing an insulating layer, a pure amorphous silicon layer, a doped amorphous silicon layer and a second metal layer sequentially on the entire surface of the substrate while covering the gate line; forming an active area and a data line region using a second mask by selectively patterning the second metal layer and the pure amorphous silicon layer, the second metal layer away from the data line region and covering the entire surface of the substrate excluding the active area and the data line; depositing a protection layer on the entire surface of the substrate and covering the data line region, the gate line protection layer and the active area; forming a data line, a protection film, a gate insulating layer, and source and drain electrodes using a third mask by patterning the second metal layer, the pure amorphous metal layer, the doped amorphous silicon layer and the insulating layer; depositing a transparent conductive material on the entire surface including the data line and the source and drain electrodes; and forming a pixel electrode and exposing a portion of the gate line using a fourth mask, the pixel electrode being connected with the drain electrode, the exposed portion extending from the active area.

The first metal layer can be anyone of Cr, Mo, and an aluminum-based metal. The present invention provides a method further comprising, a step of removing the exposed portion of the gate line. The transparent conductive material is Indium Zinc Oxide. In the third mask process is formed a contact hole to connecte the drain electrode with the pixel electrode. A contacting area between the drain electrode and the pixel electrode is larger than a cross section area of the drain electrode. The active area has a “C” shape.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the preferred embodiments of the present invention, an example of which is illustrated in the accompanying drawings.

FIG. 3is a plan view illustrating a liquid crystal display (LCD) device fabricated by a method according to an embodiment of the invention. The fabrication steps will be explained with reference toFIGS. 4A to 4DandFIGS. 5A to 5D, which are plan views and sectional views taken along line V—V ofFIG. 3, respectively.

First,FIGS. 4A and 5Ashow a process step to form a gate line on a substrate1using a first mask.

A gate line100having a gate electrode102is formed by depositing and patterning a first metal layer. A metal such as Cr and Mo may be used as the first metal layer, but an aluminum-based alloy metal with dual layered structure of AlNd and Mo is preferred. Though the gate electrode is defined as a portion102in the gate line100, the gate electrode102can be formed to protrude from the gate line100.

As shown inFIGS. 4B and 5B, an insulating layer151, a pure amorphous silicon layer152, a doped amorphous silicon layer154and a second metal layer156are deposited sequentially on the entire surface of the substrate1including the gate line100. The second metal layer156and the doped amorphous silicon layer154are patterned using a second mask to form a data line region104, a gate line protection layer106, and drain and source electrodes108and110. In this step, an active area or channel101of a thin film transistor (TFT) is defined between the drain electrode108and the source electrode110. The gate line protection layer106is larger in width than the gate electrode100, and is used to protect a predetermined portion of the insulating layer151which protects the gate electrode100from being damaged in a later etching process.

As shown inFIGS. 4C and 5C, a protection layer158is deposited on the entire substrate1and covers the data line region104and the gate line protection layer106. Then, a third mask process is performed to form protection films160and162, a data line112and a gate insulating layer150, which covers the gate electrode100. At this point, the etched region after the third mask process can be defined as two regions “A” and “C”. The region “A” is etched so that the substrate1is exposed, and the region “C” is etched so that the gate insulating layer150is exposed. Layers on the two regions “A” and “C” are etched simultaneously. As explained above, the gate insulating layer150prevents the gate line100from being damaged.

As shown inFIGS. 4D and 5D, a pixel electrode116is formed using a fourth mask. A transparent conductive material is employed for the pixel electrode116. Indium Zinc Oxide (IZO) is preferred due to its good light transmittance characteristics.

To form a storage capacitor “S”, the pixel electrode116is formed to overlap a portion of the gate line100. Namely, the gate line100serves as a first capacitor electrode, the pixel electrode116serves as a second capacitor electrode, and the gate insulating layer150between the gate line100and the pixel electrode116functions as a dielectric layer. Therefore, an overlapping portion of the pixel electrode116and the gate line100constitute the storage capacitor “S”.

Further, a portion120of the gate line100extending from the active area101should be exposed when the pixel electrode116is formed with the fourth mask. This prevents a short between the gate electrode100and the active area101from occurring. At this time, during the fourth mask process, the exposed portion120is affected by a developer or developing solution. Thus, if the gate line100is made of aluminum-based metal, which has weak resistance to the developer, the exposed portion120is preferably etched by a developer after the fourth mask process in order to prevent a short between the exposed portion120and the active area101. But the exposed portion120need not be removed if the gate line100is made of a chromium-based metal, which has a high corrosion resistance.

FIG. 6is a sectional view illustrating a connection between the drain electrode108and the pixel electrode116along the line VI—VI inFIG. 4D. As shown inFIG. 6, the drain electrode108connects with the pixel electrode116at a portion “Z” through a contact hole114, which is formed during the third mask process shown inFIG. 4C. Thus, a length of a contacting surface between the drain electrode108and the pixel electrode116is determined by the dimensions of the contact hole114.

As shown inFIGS. 7A and 7B, the drain electrode108has a sloped end portion108a, which may be concave or convex and the end portion108adirectly contacts the pixel electrode116. In this case, the contacting surface between the drain and pixel electrodes108and116is larger than a width of the drain electrode108, which in turn lowers contact resistance.

FIG. 8shows another method for the second mask process. InFIGS. 4B and 5B, after the second metal layer156is deposited on the doped silicon layer154, portions of the metal layer156and the doped silicon layer154are etched using the second mask except for the data line region104and the gate line protection layer106. On the other hand, as shown inFIG. 8, during the second mask process only a channel region or active area101of the metal layer156is etched. In this case, only the active area is formed using a second mask, and the data region104and the gate line protection layer106are not formed.

FIG. 9shows yet another method for the second mask process of the invention. As shown inFIG. 9, the second metal layer156is deposited and patterned to form the data line region104and the gate line protection layer106spaced apart from the data line region104. The channel area101is also formed during this second mask process.

The third and fourth mask processes shown inFIGS. 5C and 5Dare also adapted to fabricate the LCD device for the modified processes as shown inFIGS. 8 and 9.

The embodiments of the invention have the following advantages. The manufacture of the liquid crystal display device is accomplished using fewer mask steps, thus, the fabrication time and the cost are reduced, which leads to high yield with less misalignment.

Since the data line is formed at the same time when the protection layer is patterned, a width of the data line can be controlled.

Further, since the pixel electrode and the gateline act as electrodes of a capacitor, a separate intervening conductive layer (as in the conventional art) is not needed, i.e., can be eliminated.

It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be construed as encompassing all the features of patentable novelty that reside in the present invention, including all features that would be treated as equivalents thereof by those skilled in the art which this invention pertains.