Method for overcoming broken line and photoresist scum issues in tri-layer photoresist patterning

A method of patterning a semiconductor device using a tri-layer photoresist is disclosed. A material layer is formed over a substrate. A tri-layer photoresist is formed over the material layer. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a photo-sensitive layer disposed over the middle layer. A lithography process is performed to pattern the photo-sensitive layer into a mask having one or more openings. Undesired portions of the mask are removed via a first etching process. Thereafter, the middle layer is patterned via a second etching process. The second etching process includes forming a coating layer around the mask while the middle layer is being etched. In some embodiments, the second etching process includes a continuous plasma etching process. The plasma etching process is performed using at least a CxHyFz gas and an H2 gas.

TECHNICAL FIELD

The present disclosure relates generally to a method of patterning a semiconductor device, and more particularly, to an improved patterning technique using a tri-layer photoresist.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.

The decreasing geometry sizes may lead to various manufacturing difficulties. For example, a tri-layer photoresist is commonly used to pattern layers in semiconductor processes. However, as the device sizes become smaller and smaller, the use of tri-layer photoresist may cause broken line and/or photoresist scum issues, which may degrade semiconductor device performance or even lead to device failures.

Therefore, while existing methods of patterning semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

DETAILED DESCRIPTION

Illustrated inFIG. 1is a flowchart of a method11for patterning a semiconductor device with a tri-layer photoresist. The method11includes a step13, in which a material layer is formed over a substrate. The method11includes a step15, in which a tri-layer photoresist is formed over the material layer. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a photo-sensitive top layer disposed over the middle layer. The bottom layer includes a first CxHyOzmaterial, the middle layer includes a SiCxHyOzmaterial, and the photosensitive top layer includes a second CxHyOzmaterial and a photo-sensitive element. The method11includes a step17, in which a lithography process is performed to pattern the photo-sensitive top layer into a mask having one or more openings. The mask includes scum that extends laterally outward from the mask. The method11includes a step19, in which the mask is de-scummed by performing a first etching process. The first etching process is performed using an Ar gas and a CF4gas. The method11includes a step21, in which the middle layer is patterned via a second etching process. The second etching process includes continuously depositing a polymer coating layer around the de-scummed mask while the middle layer is being etched. The second etching process is performed using at least a CxHyFzgas and an H2gas. In some embodiments, a flow rate of the H2gas of the second etching process is in a range from about 50 standard cubic centimeters per minute (sccm) to about 250 sccm. In some embodiments, the second etching process includes an Inductively Coupled Plasma (ICP) process with a bias voltage ranging between about 120 volts and about 240 volts. The method11includes a step23, in which the bottom layer is patterned via a third etching process. The mask and the polymer coating layer are both removed during the third etching process. The method11includes a step25, in which the material layer is patterned using the patterned bottom layer.

FIGS. 2A-7Aare diagrammatic fragmentary top level views of a portion of a semiconductor device30during various patterning stages in accordance with an embodiment of the method11described inFIG. 1.FIGS. 2A-7Aare two-dimensional views, wherein the two dimensions respectively extend along an X axis and a Y axis perpendicular to the X axis.FIGS. 2B-7Bare diagrammatic fragmentary cross-sectional side views of the portion of the semiconductor device30observed in a direction that is along the Y axis. Alternatively stated, the cross-section is cut in the direction along the X axis. The various forming and etching processes (discussed later) performed on the semiconductor device30are done along a Z axis that is perpendicular to an imaginary plane formed by the X axis and the Y axis.

The semiconductor device30may be a portion of an integrated circuit (IC) chip and may include various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), laterally diffused MOS (LDMOS) transistors, high power MOS transistors, or other types of transistors. It is understood thatFIGS. 2A-7Aand2B-7B have been simplified for a better understanding of the inventive concepts of the present disclosure. Accordingly, it should be noted that additional processes may be provided before, during, and after the method11ofFIG. 1, and that some other processes may only be briefly described herein.

Referring toFIGS. 2A and 2B, the semiconductor device30includes a substrate35. The substrate35may be a semiconductor wafer, or may be an under-layer such as a metal layer (Mxto Mx+1). For example, the substrate35may include silicon. The substrate35may alternatively be made of some other suitable elementary semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Alternatively, the substrate35may include a non-semiconductor material such as a glass substrate for thin-film-transistor liquid crystal display (TFT-LCD) devices, or fused quartz or calcium fluoride for a photomask (mask). The substrate35may include various doped regions and/or dielectric features for various microelectronic components, such as a complementary metal-oxide-semiconductor field-effect transistor (CMOSFET), imaging sensor, memory cell, and/or capacitive element.

A silicide-blocking layer (SBL)40is formed over the substrate35. The silicide-blocking layer40may also be referred to as a silicidation-blocking layer. In some embodiments, the silicide-blocking layer40is formed by a suitable process such as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), or combinations thereof. The silicide-blocking layer40includes a dielectric material such as silicon oxide or silicon nitride in the present embodiment, but may include another suitable material in alternative embodiments. It is understood that in some embodiments, the silicide-blocking layer40may not be formed directly on the upper surface of the substrate35. Instead, other suitable layers may be formed between the substrate35and the silicide-blocking layer40.

A Tetraethyl orthosilicate (TEOS) layer45is formed over the silicide-blocking layer40. In some embodiments, the TEOS layer50is formed by a process such as PVD, CVD, plasma enhanced chemical vapor deposition (PECVD), combinations thereof, or another suitable technique.

A low-k dielectric layer50is formed over the TEOS layer45. In some embodiments, the low-k dielectric layer50is formed by a process such as PVD, CVD, PECVD, ALD, combinations thereof, or another suitable technique. The low-k dielectric layer50includes a low-k material, which is a material having a dielectric constant less than that of standard silicon dioxide (dielectric constant of silicon oxide is about 3.9). In various embodiments, the low-k dielectric material may include, but is not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, spin-on organic polymeric dielectrics, spin-on silicone based polymeric dielectric, polyimides, aromatic polymers, fluorine-doped amorphous carbon, vapor-deposited parylene, etc.

An anti-reflective coating (ARC) layer55is formed over the low-k dielectric layer50. In some embodiments, the anti-reflective coating55is a nitrogen-free anti-reflective coating (NFARC) layer. The anti-reflective coating layer55may be formed by a suitable deposition technique known in the art.

A titanium nitride layer60is then formed over the ARC layer55. The titanium nitride layer60is formed by a radio-frequency physical vapor deposition (RFPVD) process in the present embodiment, but may be formed by an alternative process in another embodiment.

A Tetraethyl orthosilicate (TEOS) layer65is then formed over the titanium nitride layer60. In some embodiments, the TEOS layer50is formed by a process such as PVD, CVD, plasma enhanced chemical vapor deposition (PECVD), combinations thereof, or another suitable technique.

An amorphous silicon layer70is then formed over the TEOS layer65. The amorphous silicon layer70is formed by a process such as PVD, CVD, sputtering, or another suitable technique. The amorphous silicon layer70herein serves as a mask layer to be patterned by a photoresist layer (discussed below). In other embodiments, a mask layer of another suitable material may be used instead of the amorphous silicon layer70.

It is understood that the layers40-70are merely example layers that can be patterned by a photoresist layer. In other embodiments, a subset of the layers40-70or different layers may be formed over the substrate35and may be patterned by the photoresist layer discussed below.

A tri-layer photoresist90is formed over the hard mask layer80. In the present embodiment, the tri-layer photoresist90includes a bottom layer91, a middle layer92, and a top layer93. In some embodiments, the bottom layer91includes a CxHyOzmaterial, the middle layer92includes a SiCxHyOzmaterial, and the top layer93includes a CxHyOzmaterial. The CxHyOzmaterial of the bottom layer91may be identical to the CxHyOzmaterial of the top layer93in some embodiments, but they may also be different in other embodiments. The top layer93also includes a photo-sensitive element, such as a photo-acid generator (PAG). This allows a photolithography process to be performed to pattern the top layer93. It is understood that in other embodiments, one or more layers of the tri-layer photoresist may be omitted, or additional layers may be provided as a part of the tri-layer photoresist, and the layers may be formed in difference sequences.

Typically, the top layer93is patterned by a photolithography process, which may include one or more exposure, developing, rinsing, and baking processes (not necessarily performed in this order). The photolithography process patterns the top layer93into a photoresist mask, which may have one or more trenches or openings that expose the middle layer92therebelow. The middle layer92is then etched using the photoresist mask to form a patterned middle layer, and the bottom layer91is then etched using the patterned middle layer to form a patterned bottom layer. The patterned bottom layer is then used to pattern the various layers below. Unfortunately, conventional techniques of performing these patterning and etching processes tend to cause broken line and/or photoresist scum issues, which may degrade semiconductor device performance or cause semiconductor device failure.

According to the various aspects of the present disclosure, an improved lithography/patterning technique is used to substantially reduce or alleviate the broken line and/or photoresist scum issues associated with conventional techniques. The details of the present disclosure are discussed below.

Referring now toFIGS. 3A-3B, a photolithography process100is performed to the top layer93to form a patterned photoresist mask. The patterned photoresist mask includes segments93A and93B, which are being separated by a gap or an opening110. In some embodiments, a width (i.e., horizontal dimension) of the gap110is in a range from about 20 nanometers (nm) to about 100 nm. The segments93A and93B also have a height (i.e., vertical dimension)120. In some embodiments, the height120is in a range from about 400 Angstroms to about 700 Angstroms.

Due to various imperfections of the photolithography process100, undesirable photoresist scum may be formed. For example, a laterally-protruding portion130near the bottom of the segment93A represents the photoresist scum and may be hereinafter referred to as such. As is illustrated, the photoresist scum130effectively reduces the gap110between the adjacent segments93A and93B and enlarges the size of the segment93A. As such, the presence of the photoresist scum130may lead to inaccuracies or other failures in subsequent patterning processes. Hence, it is desirable to remove the photoresist scum130.

Referring now toFIGS. 4A-4B, the photoresist scum130is removed in a de-scumming process140. In some embodiments, the de-scumming process140includes an etching process. According to the various aspects of the present disclosure, the etching process is performed at an etching chamber using a continuous plasma process, for example an inductively coupled plasma (ICP) process. In certain embodiments, an etching gas of the de-scumming process140includes Ar and CF4. The Ar gas and the CF4gas may each have a flow rate in a range from about 30 standard cubic centimeters per minute (sccm) to about 50 sccm, for example about 40 sccm. In some embodiments, the Ar gas and the CF4gas have a flow ratio of about 1:1. The etching process is performed at a pressure in a range from about 1 milli-Torr (mT) to about 3 mT, for example about 2 mT. A source power for the ICP process may be in a range from about 200 Watts (W) to about 250 W, for example about 220 W. A bias voltage for the IPC process may be in a range from about 80 Volts (V) to about 150 V, for example about 110 V.

As a result of the de-scumming process140, the segments93A and93B are reduced to a lower height150, which is less than the height120shown inFIG. 3Bbefore the de-scumming process140was performed. In some embodiments, the height150is in a range from about 300 Angstroms to about 500 Angstroms. The segments93A and93B of the patterned top layer may now be used to pattern the middle layer92below.

Referring now toFIGS. 5A and 5B, an etching process160is performed to “open” the middle layer92. In other words, the middle layer92is patterned into segments92A and92B. The segments93A and93B serve as a photoresist mask in this etching process160. The etching process160may be performed in the same etching chamber that was used to perform the de-scumming process140discussed above. In other words, the etching process160also involves a continuous plasma process (a pulsing-free process), for example the ICP process. In certain embodiments, an etching gas of the etching process160includes CF4, CHF3, H2, N2, and Ar. The CHF3gas serves as a main gas in the present embodiment, and the N2and Ar gases serve as assistant gases in the present embodiment. The CF4gas may have a flow rate in a range from about 50 sccm to about 70 sccm, for example about 60 sccm, the CHF3gas may have a flow rate in a range from about 45 sccm to about 65 sccm, for example about 55 sccm, the H2gas may have a flow rate in a range from about 50 sccm to about 250 sccm, for example about 150 sccm, the N2gas may have a flow rate in a range from about 50 sccm to about 80 sccm, for example about 65 sccm, and the Ar gas may have a flow rate in a range from about 40 sccm to about 60 sccm, for example about 50 sccm.

It is understood that the flow rate of the H2gas is optimized in the range from about 50 sccm to about 250 sccm, as a slower flow rate may lead to incomplete or ineffective etching, and a faster flow rate may lead to too much photoresist loss (i.e., the loss of the segments93A and93B). This will be discussed in more detail below with reference toFIG. 8. It is also understood that in alternative embodiments, other suitable CxHyFz(where x>0, y>=0, and z>0) gases may be used as a main gas instead of the CHF3gas used in the present embodiment,

The etching process is performed at a pressure in a range from about 5 mT to about 20 mT, for example about 12 mT. A source power for the ICP process may be in a range from about 500 W to about 700 W, for example about 600 W. A bias voltage for the IPC process may be in a range from about 120 V to about 240 V, for example about 200 V. It is also understood the bias voltage range of about 120 V to about 240 V is optimized, as a bias voltage lower than 120 V may lead to incomplete or ineffective etching, and a bias voltage greater than 240 V may lead to too much photoresist loss (i.e., the loss of the segments93A and93B). It is also understood that the etching process160is preferably performed using a continuous plasma process, since a pulsing type of etching process—which is discontinuous but commonly used in many etching processes—may lead to incomplete or ineffective etching as well.

As a result of the etching process160, the middle layer92is patterned into segments92A and92B. The segments92A and92B align with the segments93A and93B, respectively, since the segments93A and93B serve as a mask during the etching process160. In addition, a coating layer180is formed over the top surface and sidewall surfaces of the segments93A-93B and92A-92B. In some embodiments, the coating layer180includes a polymer material. The formation of the coating layer180is attributed at least in part to the addition of the H2gas. Due to various chemical reactions, the coating layer180is being continuously deposited on the segments93A-93B and92A-92B, while the etching continuously takes place as well. Stated differently, the etching of the middle layer92and the formation of the coating layer180occur substantially simultaneously and in a continuous manner. At the conclusion of the etching process160, a collective height185of the segment93A and the coating layer180is in a range from about 410 Angstroms to about 610 Angstroms.

As discussed above, the etching of the middle layer of a tri-layer photoresist according to conventional processes may not include, among other things, the inclusion of the H2gas as an etchant. As such, the conventional processes for etching the middle layer would not have resulted in a coating layer (or a layer similar to the coating layer180) being continuously deposited on the photoresist mask (i.e., portions of the top layer similar to the segments93A-93B). In other words, no protecting coating material would have been formed on the photoresist mask in conventional etching processes. The lack of protection for the photoresist mask often leads to over-etching of the photoresist mask, where the photoresist mask suffers greater-than-expected height loss. In some cases, portions of the photoresist mask may be etched away in its entirety. In either of these scenarios, the over-etched photoresist mask cannot be properly used to carry out etching of the middle layer, as that would likely result in broken line issues. For example, a segment of the middle layer that should not have been etched is now etched due to the insufficient photoresist mask. Consequently, semiconductor device performance may be degraded, and device failures may increase.

In comparison, the present disclosure continuously deposits the coating layer180around the segments93A-93B of the top layer93(i.e., the photoresist mask). The coating layer180prevents the over-etching of the segments93A-93B by protecting them while the middle layer92is being etched. As such, the etching process160of the present disclosure is unlikely to cause broken line issues that are commonly found for conventional etching processes.

Referring now toFIGS. 6A-6B, another etching process190is performed to “open” the bottom layer91. In other words, the bottom layer91is patterned into segments91A and91B. The segments92A and92B of the patterned middle layer serve as a mask in this etching process190. The etching process190may or may not be performed in the same etching chamber that was used to perform the de-scumming process140and the etching process160discussed above. The coating layer180may be removed during the etching process190, or it may be removed before the etching process190is performed.

In certain embodiments, an etching gas of the etching process190includes HBr, Cl2, O2, and N2. The HBr gas may have a flow rate in a range from about 40 sccm to about 60 sccm, for example about 50 sccm, the Cl2gas may have a flow rate in a range from about 5 sccm to about 40 sccm, for example about 20 sccm, the O2gas may have a flow rate in a range from about 40 sccm to about 150 sccm, for example about 90 sccm, and the N2gas may have a flow rate in a range from about 30 sccm to about 80 sccm, for example about 50 sccm.

Referring now toFIGS. 7A-7B, another etching process200is performed to pattern the amorphous silicon layer70. In other words, the amorphous silicon layer70is patterned into segments70A and70B. The segments91A and91B of the patterned bottom layer serve as a mask in this etching process200. The etching process200may or may not be performed in the same etching chamber that was used to perform the de-scumming process140and the etching processes160and190discussed above. The segments92A-92B of the middle layer may be removed during the etching process200, or it may be removed before the etching process200is performed.

Although not specifically illustrated or discussed for reasons of simplicity, one or more the various layers40-65may also be patterned using various etching processes. As a result of these etching processes, various semiconductor features such as trenches or islands may be formed. Again, due to the continuous formation of the coating layer180and the continuous etching of the middle layer92during the middle layer etching process, the various semiconductor features being patterned thereafter will be much less likely to suffer from inaccurate or inadequate patterning as a result of photoresist scum or broken line issues discussed above in association with conventional processes.

FIG. 8is a graphical chart that illustrates three different phases220-222that correspond to different flow rates of the H2gas in the etching process160shown inFIG. 5B. InFIG. 8, various etching performance parameters are plotted as the Y-axis with respect to different flow rates of the H2gas as the X-axis. For example, AMI CD denotes after-mask-inspection critical dimension, LWR denotes line width roughness, ML EP or BL EP denote middle layer endpoint or bottom layer end point, respectively (amount of etching time associated with the middle layer92or the bottom layer91as they are etched through), and PR EP denotes photoresist end point (amount of etching time associated with the complete removal of the top layer93). In the etching process160, there three mechanisms take place:Mechanism A is directed to fluorine etching. Mechanism A includes the following chemical reactions: e−+CF4—=>CF3+F+e−, and Si+4F=>SiF4.Mechanism B is directed to fluorine formation reduction and polymer formation. Mechanism B includes the following chemical reactions: H+F=>HF, and CF4+H2=>CxHyFz.Mechanism C is directed to fluorine formation. Mechanism C includes the following chemical reactions: HF+e−=>H+F+e−, and H+HF*=>H2+F.

In phase 1, the mechanism B dominates. As a result, AMI CD decreases, LWR remains relatively constant, ML EP increases, and BL EP increases too. In phase 2, the mechanisms A, C, and C are relatively balanced. In other words, none of these mechanisms dominates. As a result, AMI CD is on target, LWR decreases, ML EP decreases or remains relatively constant, and BL EP decreases too. In phase 3, the mechanism C dominates. As a result, AMI CD increases, LWR increases, ML EP remains relatively constant, and BL EP decreases.

The behavior associated with the three phases220-222discussed above is also graphically illustrated inFIG. 8. It can be seen that an optimized and balanced performance is achieved in phase 2, where the H2gas is approximately in a range from about 50 sccm to about 250 sccm. In other words, phase 2 corresponds to a state where the etching of the middle layer and deposition of the protecting coating on the photoresist mask can occur continuously in a balanced manner. No over etching of the photoresist mask would occur, nor does etching take an excessively long time. Hence, the H2gas flow rate in phase 2 is considered optimized and is therefore implemented in the etching process160of the present disclosure.

One aspect of the present disclosure involves a method of fabricating a semiconductor device. The method includes: forming a material layer over a substrate; forming a tri-layer photoresist over the material layer, the tri-layer photoresist including a bottom layer, a middle layer disposed over the bottom layer, and a photo-sensitive layer disposed over the middle layer; performing a lithography process to pattern the photo-sensitive layer into a mask having one or more openings; removing undesired portions of the mask via a first etching process; and thereafter patterning the middle layer via a second etching process, wherein the second etching process includes forming a coating layer around the mask while the middle layer is being etched.

In some embodiments, the method further includes: patterning the bottom layer via a third etching process, wherein the mask and the coating layer are collectively removed during the third etching process; and using the patterned bottom layer to pattern the material layer.

In some embodiments, the undesired portions of the mask include photoresist scum that protrudes outward from the mask.

In some embodiments, the first etching process is performed using an Ar gas and a CF4gas; and the first etching process is performed at a pressure of about 2 milli-Torrs.

In some embodiments, the second etching process includes a plasma etching process, and wherein the plasma etching process is performed using at least a CxHyFzgas and an H2gas.

In some embodiments, the H2gas is configured to induce a polymer material to be deposited around the mask as the coating layer while the middle layer is being etched.

In some embodiments, a flow rate of the H2gas is in a range from about 50 standard cubic centimeters per minute (sccm) to about 250 sccm.

In some embodiments, the plasma etching process includes a continuous plasma process.

In some embodiments, the plasma etching process is performed at a bias voltage in a range from about 120 volts to about 240 volts.

In some embodiments, the bottom layer includes a first CxHyOzmaterial; the middle layer includes a SiCxHyOzmaterial; and the photo-sensitive layer includes a second CxHyOzmaterial and a photo-acid generator.

Another aspect of the present disclosure involves a method of fabricating a semiconductor device. The method includes: forming a material layer over a substrate; forming a tri-layer photoresist over the material layer, the tri-layer photoresist including a first layer, a second layer disposed over the first layer, and a third layer disposed over the second layer, wherein the third layer contains a photo-sensitive material; forming a patterned third layer via a lithography process, the patterned third layer including one or more openings that expose the second layer therebelow; de-scumming the patterned third layer via a first etching process; after the de-scumming, forming a patterned second layer via a second etching process, wherein the second etching process includes continuously coating a polymer layer around the patterned third layer as the second layer is being etched; forming a patterned first layer via a third etching process, wherein the patterned second layer and the polymer layer coated thereon are collectively removed during the third etching process; and patterning the material layer using the patterned first layer.

In some embodiments, the first layer includes a first CxHyOzmaterial; the second layer includes a SiCxHyOzmaterial; and the third layer includes a second CxHyOzmaterial and a photo-acid generator.

In some embodiments, the first etching process is performed using an Ar gas and a CF4gas; and the first etching process is performed at a pressure of about 2 milli-Torrs.

In some embodiments, the second etching process includes a plasma etching process that is pulsing-free, and wherein the plasma etching process is performed using at least a CxHyFzgas and an H2gas.

In some embodiments, a flow rate of the H2gas is ranging between about 50 standard cubic centimeters per minute (sccm) and about 250 sccm.

In some embodiments, the plasma etching process includes an Inductively Coupled Plasma (ICP) process.

In some embodiments, the plasma etching process is performed at a bias voltage ranging between about 120 volts and about 240 volts.

Yet another aspect of the present disclosure involves a method of fabricating a semiconductor device. The method includes: forming a material layer over a substrate; forming a tri-layer photoresist over the material layer, the tri-layer photoresist including a bottom layer, a middle layer disposed over the bottom layer, and a photo-sensitive top layer disposed over the middle layer, wherein the bottom layer includes a first CxHyOzmaterial, the middle layer includes a SiCxHyOzmaterial, and the photosensitive top layer includes a second CxHyOzmaterial and a photo-sensitive element; performing a lithography process to pattern the photo-sensitive top layer into a mask having one or more openings, wherein the mask includes scum that extend laterally outward from the mask; de-scumming the mask by performing a first etching process, wherein the first etching process is performed using an Ar gas and a CF4gas; thereafter patterning the middle layer via a second etching process, wherein the second etching process includes continuously depositing a polymer coating layer around the de-scummed mask while the middle layer is being etched, and wherein the second etching process is performed using at least a CxHyFzgas and an H2gas; patterning the bottom layer via a third etching process, wherein the mask and the polymer coating layer are both removed during the third etching process; and patterning the material layer using the patterned bottom layer.

In some embodiments, the second etching process includes an Inductively Coupled Plasma (ICP) process with a bias voltage ranging between about 120 volts and about 240 volts.

In some embodiments, a flow rate of the H2gas of the second etching process is in a range from about 50 standard cubic centimeters per minute (sccm) to about 250 sccm.