A three-dimensional crossbar array may include a metal layer, and an insulator layer disposed adjacent the metal layer. A trench may be formed in the metal layer to create sections in the metal layer, and a portion of the trench may include an insulator. A hole may be formed in the trench and contact a section of the metal layer. The hole may define a via. A contact region between the via and the section of the metal layer may define a crossbar array.

BACKGROUND

Memristor and two-terminal devices generally may utilize a crossbar configuration including a switching material or device disposed between two conducting electrodes that overlap one another perpendicularly. Since such devices do not need a single-crystal silicon or a monolithic substrate, they can be integrated at a greater density compared to standard microelectronic devices when using a stacked three-dimensional structure. The stacking capability can lead to advances in the storage capacity, for example, of memory chips. However, stacking multiple layers of crossbar structures may need a number of lithography process steps proportional to the number of layers stacked, which can add expense to devices using such crossbar structures.

For example, fabrication of a single plane of crossbar arrays may generally use two or more lithography steps. Therefore, stacking multiple (e.g., N) layers of the single plane of crossbar arrays may use at least 2*N lithography steps. Additional lithography steps may be needed to form vias that contact these arrays. A via is a vertical electrical connection between different layers of conductors, for example, in a printed circuit board. For an eight layer stacked architecture, therefore, upwards of sixteen lithography steps may be needed. As discussed above, such multiple steps can add expense to devices using such crossbar structures that may include multiple layers.

DETAILED DESCRIPTION OF EMBODIMENTS

For simplicity and illustrative purposes, the principles of the embodiments are described by referring mainly to examples thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. It will be apparent that the embodiments may be practiced without limitation to all the specific details. Also, the embodiments may be used together in various combinations.

Memristor and other non-silicon-based two-terminal devices may utilize a stacked three-dimensional structure because their active channels may include materials that can be deposited as thin films, and may be independent of a silicon substrate, unlike silicon-based devices such as, for example, NAND Flash or DRAM devices. The stacking capability can lead to advances in the storage capacity, for example, of memory chips. However, stacking multiple layers of crossbar structures may need a number of lithography process steps proportional to the number of layers stacked, which can add expense to devices using such crossbar structures utilizing multiple layers.

A three-dimensional crossbar array and a fabrication method thereof is provided for reducing the number of lithography steps. The three-dimensional crossbar array may include an insulator layer and a metal layer, or alternatively, a plurality of alternating insulator and metal layers disposed adjacent each other. The vertically integrated crossbar geometry of the three-dimensional crossbar array may include multiple stacked horizontal metal lines and vertical via lines. It should be noted that the terms horizontal and vertical, and any reference to a dimension or coordinate system are provided solely for facilitating an understanding of the three-dimensional crossbar array and the fabrication method thereof. The group of parallel metal lines in the horizontal direction of the crossbar structure may be realized by stacking alternating layers of metal and insulator, patterning the stacks into stripes, and etching vertically to form mesas that include stacks of isolated horizontal metal lines. The remaining volume between the mesas may be filled with insulator material. The vertical via lines may be realized by etching holes vertically into the substrate such that they partially overlap and contact the metal lines. The holes may extend fully or partially through the crossbar array. The sidewalls of the vias may then be coated with memristive metal-oxide film, and the interior may be filled with a metal core. The overlap of the horizontal and vertical lines may therefore be comparable to a memristor structure, that is, a (metal electrode)-(metal-oxide film)-(metal electrode) junction.

The three-dimensional crossbar array may include a metal layer, and an insulator layer disposed adjacent the metal layer. A trench may be formed in the metal layer to create sections in the metal layer, and a portion of the trench may include an insulator. The sections may be referred to as metal lines, and are described in further detail below. A hole may be formed in the trench and contact a section of the metal layer. The hole may define a via. A contact region between the via and the section of the metal layer may define a crossbar array. The metal layer may be formed of a homogeneous material, or instead may be formed of a heterogeneous stack of materials including, for example, a combination of Platinum (Pt), Titanium Nitride (TiN), Tungsten (W), Copper (Cu), Tantalum Nitride (TaN), Titanium (Ti), Tantalum (Ta), Aluminum (Al) and metal oxides such as Ti407. The sections of the metal layer may be isolated from each other.

Fabrication of a single plane of crossbar arrays may generally use two or more lithography steps. Therefore, stacking multiple (e.g., N) layers of the single plane of crossbar arrays may use at least 2*N lithography steps. Additional lithography steps may be needed to form vias that contact these arrays. For an eight layer stacked architecture, therefore, upwards of sixteen lithography steps may be used. The three-dimensional crossbar array described herein may provide for increase in the integration density, for example, for a microelectronic chip (i.e., memory) device by stacking, with a smaller and fixed number of lithography steps. The number of lithography steps for the three-dimensional crossbar array may be independent of the number of stacked layers, as the crossbar array structure may allow for lithography steps to simultaneously define features encompassing multiple layers.

The crossbar architecture for the three-dimensional crossbar array may realize stacked three-dimensional integration of memristive, or other types of two-terminal devices, at an increased density compared to stacked integration of the single plane of crossbar arrays. This is because the same amount of stacking density may be achieved with a smaller number of lithography masking steps or sequences, therefore reducing cost and fabrication complexity. As discussed above, the number of lithography sequences needed in the fabrication may be fixed regardless the number of layers that are stacked.

An example is provided for estimating densities that can be expected from the three-dimensional crossbar array architecture. For example, assuming a structure has eight stacked horizontal layers, assumptions regarding the lithography constraints may be determined as follows. Since the vias may be etched between the horizontal lines, and there are possibly branched extensions of the horizontal lines, the pitch of the horizontal lines may be assumed to be 4 F, assuming the lines themselves are of width 1˜1.5 F. Depending on the series resistance constraints of the lines, the width of the horizontal lines may vary, and therefore the pitch of the horizontal lines may range between 3 F˜5 F. The pitch of the vias may be set at approximately 3 F, but may be as small as 2 F. Taking into account the base assumed values above, in the area of 4 F times 3 F=12 F2, one via may contact one stack of eight devices, which gives the area of 1.5 F2per device. When the number of stacked layers increases, for example, to sixteen, the area per device may decrease to 0.75 F2. However, calculating using the low values may result in eight (or sixteen) stacked devices in 6 F2, leading to half of the above densities. Thus regardless of the number of stacked layers, the number of lithography sequences may remain constant at approximately three to fabricate the crossbar structure itself, or approximately seven-eight to fabricate connections to devices external to the crossbar structure.

2. Structure and Method

FIG. 1illustrates a structure for a two-terminal device100, such as a memristor, according to an embodiment. Referring toFIG. 1, each layer of the device100may include platinum (Pt) electrodes101,102, and sandwiched there-between titanium dioxide (TiO2and TiO2-x) layers103,104. Other metals or combinations of metals may be used for the electrodes. The TiO2-xlayer104may be designated the conductor region and include oxygen vacancies. Under an electric field, the oxygen vacancies may migrate toward the TiO2layer103. Each layer of the two-terminal device100may need three mask steps per layer. For example, for a device100with N layers, a minimum of two and a maximum of four masking steps may be needed. The minimum number of masking steps may be based on elimination of the masking step for the middle TiO2and TiO2-xlayers. Thus for the two-terminal device100with N layers, 3N masking steps may be needed.

FIGS. 2A-2Cillustrate a three-dimensional stacked crossbar array110with vertical via lines and a fabrication method thereof, according to an embodiment. Referring toFIGS. 2A-2C, a profile view is shown at the left hand side and a top view is shown at the right hand side. As shown inFIG. 2A, the stacked crossbar array110may include deposited alternating layers of metal111, such as, for example, Platinum (Pt), Titanium Nitride (TiN), Tungsten (W), Copper (Cu), Tantalum Nitride (TaN), Titanium (Ti), Tantalum (Ta), Aluminum (Al) and metal oxides such as, for example, Ti407, and insulator112such as, for example, Silicon Dioxide (SiO2), Silicon Nitride (Si3N4), spin-on glass and Silicon (Si). Metal111may be homogeneous or include a combination of metals. As shown inFIG. 2B, the stacked structure ofFIG. 2Amay be patterned and trenches113,114may be etched to create isolated horizontal metal lines in each layer. As indicated above, it should be noted that the terms horizontal and vertical, and any reference to a dimension or coordinate system are provided solely for facilitating an understanding of the three-dimensional crossbar array and the fabrication method thereof. The trenches113,114may be filled with an insulator, such as, for example, SiO2, and planarized, for example, by chemical mechanical polishing (CMP) to level the surface. Referring toFIG. 2C, the stacked crossbar array110may be pattered and holes115,116, may be etched to define vias that contact and overlap horizontal metal lines117-119of each layer of the metal111. The holes115,116forming the vias may be circular, oval or another shape. As shown inFIG. 2C, the holes115may contact the metal lines117,118of each layer of the metal111on both sides of each via, and the holes116may contact the metal lines119of each layer of the metal111on one side of the via. The holes116constituting the vertical lines of the stacked crossbar array110may be filled by coating the inner surface of the via holes with a thin transition metal oxide (TMO) film120and filling the interior with a metal core121. The TMO film120may be formed of materials such as, for example, TiO2, Ta2O5or its reduced variants, such as, for example, TaOx, NiO, ZnO, ZrO, HfO2, and Al2O3, and may function as the memristive switching material. The intersection of the horizontal conductive line (terminal1), the metallic portion of the vertical via line (terminal2), and the TMO coating of the via lines sandwiched in between these metallic elements, combined operate as a two-terminal resistive switching device in which the states of the device may be defined by the resistive state of the TMO film(s) that were subjected to electrical stimuli by the metallic terminal contacts. To achieve a different type of two-terminal device, such as, for example, a magnetoresistive memory (MRAM) element, the interior surfaces of the vias may be coated by other types of films, such as, for example, ferromagnetic, ferroelectric, and insulating thin films, and the composition of the horizontal lines may change accordingly. The metal core121may be homogeneous or include a combination of metals, such as, for example, Tungsten, Titanium Nitride and Tantalum Nitride. The metal core121may allow current to flow through all or some of the memristive devices it is in contact with. The overlapped junction between the vias and the metal lines may thus function as a crossbar structure rotated 90°, as described below.

Referring toFIGS. 1-3, overlapped junctions shown at130inFIG. 3may function as a crossbar structure rotated 90° (see two-terminal device100ofFIG. 1). Referring toFIG. 3, the TMO film120may function as the memristor switching line layer, and coat the sidewalls of the holes by an atomic layer deposition (ALD) process. When the holes115,116are filled with the metal core121, a M-I-M structure may be formed in a crossbar configuration between the via and horizontal line. The crossbar configuration may thus include vertical vias formed by the holes115,116and intersect multiple stacked horizontal lines, such as the metal lines117-119ofFIG. 2C. Compared to the memristor configuration ofFIG. 1which may be considered to have a structure oriented in the X and Y directions, the overlapped junctions shown at130ofFIG. 3may be considered to have a structure oriented in the Y and Z directions. The overlapped junctions shown at130show that a plurality of layers (e.g., three layers) may be produced by two masking steps. Comparably, for the structure for the two-terminal device100ofFIG. 1, two or more masking steps may be used to produce one plane of memristors, and for N layers of memristors, the number of masking steps would be based on the number of layers multiplied by the number of masking steps. As described below, other sidewall-coating layers and junction structures may replace the TMO film120to realize various two-terminal devices.

Referring toFIG. 3, for the TiO2, TiO2-xlayers131,132, as discussed above with reference toFIG. 1, the TiO2-xlayer132may be designated the conductor region and include oxygen vacancies. Under an electric field applied to the electrode101adjacent the TiO2layer, the oxygen vacancies in the TiO2-xlayer may migrate into the TiO2layer131towards the electrode101. Based on migration of the oxygen vacancies through the TiO2layer131towards the electrode101, the effective size of the TiO2layer131decreases. The gap represented by w(t1) at133may thus be narrowed based on migration of the oxygen vacancies through the TiO2layer131, thus increasing conductivity of the junction for providing switching.

Referring toFIG. 4, in order to minimize the affect of misalignment between the edge of the metal lines140(similar to the metal lines117-119ofFIG. 2C) and the vias141(similar to the vias ofFIG. 2C) in a patterning process and associated variation in overlap between the two, branches142may be provided. For example, as shown at the bottom left ofFIG. 4, any alignment error may change junction area. The branches142may cover the range of misalignment that may be resolved. The holes forming the vias141may also be elongated into ovals or other shapes to cover the misalignment in an orthogonal direction. In order to form the branches142, the metal lines may include the branches142that overlap with the holes forming the vias141. The holes forming the vias141may be patterned and etched to define the vias that contact and overlap the branches of the metal lines140. The interior of the holes forming the vias141may be filled with a TMO film143(similar to TMO film120ofFIG. 2C) and metal core144(similar to metal core121ofFIG. 2C). As shown at the bottom right ofFIG. 4, the branches142may thus increase the margin for error in lithography alignment.

FIGS. 5A-5Fillustrate an integrated three-dimensional crossbar array150with isolated contacts and a fabrication method thereof, according to an embodiment. The fabrication method described herein may allow the metal lines to be contacted without excessive lithography. Compared to the crossbar array110ofFIGS. 2A-2Cfor which the trenches113,114are defined after deposit of the layers111,112, forFIGS. 5A and 5B(and furtherFIGS. 5C-5F), a trench151may be defined before deposit of the layers. The crossbar array150ofFIGS. 5A-5Fprovides a structure that may be integrated and contacted outside the substrate. If the multiple layers were to be stacked in parallel, additional lithography may be needed to etch vias to contact each layer. In order to avoid this, the parallel layers may be bent over a stepped structure such that segments of the layers may point vertically. CMP may then expose the segment ends, which can then be simultaneously contacted in one or two lithography steps. Thus as shown inFIG. 5A, which shows a side view of the crossbar array150, the trench151may be defined into an inter layer dielectric (ILD) SiO2substrate152. The width of the trench151may be greater than the intended length of the metal lines. The length of the trench151may be indefinite, and in the configuration ofFIG. 5A, the length may span the width of the substrate152. Referring toFIG. 5B, which shows a side view of the crossbar array150, multiple alternating metallic and ILD films153,154may be deposited over the trench151. As shown inFIG. 5B, once the metallic and ILD films153,154have been deposited, the structure may be capped with a thick insulator layer155, such as, for example, Silicon Dioxide (SiO2), Silicon Nitride (Si3N4), spin-on glass and Silicon (Si).

FIGS. 5C and 5Dillustrate planarization of a film stack, exposing vertical edges of metal film layers. Referring toFIG. 5C, which shows a side view of the crossbar array150, after planarization by CMP, vertical edges156of the metal films153may be exposed. The metal lines thus fabricated may be contacted from the top surface at the exposed vertical edges156.FIG. 5Dshows a top view of the crossbar array150. The planarization results in the majority of the length of the metal films to be buried in the remaining insulator layer155.

FIG. 5Eillustrates etching of trenches to separate metallic lines and filling with (inter-layer dielectric) ILD. Referring toFIG. 5E, which shows a top view of the crossbar array150, trenches157may be etched to separate the metal film layers153. The trenches157may include side branches158and trenches159may be etched without side branches. The trenches157,159may be filled with an insulator, and planarized to level the surface. Compared to the configuration ofFIG. 2Cthat includes holes115,116forming the vias, the vertical edges156provide additional contacts as described below.

FIG. 5Fillustrates patterning and etching of holes to define vias, and coating the interior of via holes. Referring toFIG. 5F, holes160,161and162forming the vias may be etched, overlapping metal lines163(seeFIG. 5E) or branches158in a similar manner asFIG. 2C. The etched holes may be filled with a TMO film164and metal core165. In the configuration ofFIG. 5F, the number of devices fabricated in the area would thus include 96 devices (e.g., 4 metal layers)×(3 metal lines contacted)×(8 via holes per line)). Although the lateral lithography density may be reduced from the spacing needed for the fabrication scheme described herein (e.g., with the branches158), the layer stacking and vertical integration allows for increased density based on number of layers. Moreover, the integration ofFIGS. 5A-5Fmay be achieved in three mask steps regardless the number of layers.

FIG. 6Aillustrates contacting of stacked metal lines for the integrated three-dimensional crossbar array150. Referring toFIG. 6A, the vias formed by the holes160,161and162may land directly into the metal line ends. In order to connect to vias coming up from the bottom, lateral fan-out lines170may be patterned. The vias may be placed down to the metallic contacts171. The contacts171may be provided such that after filling with ILD (seeFIG. 5E), the vias may be etched and contact may be provided with the fan-out lines170. Thus the exposed vertical edges156of the metal film layers153may be contacted from above or to vias etched into the adjacent insulating region. Alternatively contacts172may be provided for direct contact. For the contacts172, after covering with ILD (seeFIG. 5E), vias may be etched directly to the vertical edges156of the metal film layers153.

FIG. 6Billustrates contacting of vertical via holes. Referring toFIG. 6B, the exposed ends of the vias formed by the holes160,161and162may be addressed and contacted by patterning a series of metal lines173perpendicular to the horizontal metal lines (as seen from the top view) that connect to the exposed top ends of the vias. The metal lines173may be contacted at174to control devices at the substrate level or externally by vias.

FIG. 7Aillustrates addressing of an integrated three-dimensional crossbar array180. Generally, for the addressing scheme described in further detail below, the horizontal metal lines (oriented along the x axis) may be arrayed in a matrix of vertical stacks (z) and lateral columns (y) and are each contacted independently, and the vertical vias (oriented along the z axis) may be connected and bundled by contact lines (on the top surface) running in the y-direction. Specifically, referring toFIG. 7A, for the crossbar array180, each device may be addressed by a horizontal metal line181, a vertical via line182, which in turn is connected to an orthogonal contact line183. As shown inFIG. 7A, the stacked horizontal metal lines181extend in the x-direction. The horizontal metal lines181may be stacked in the z-direction and lined up in the y-direction. The via lines182(coated with the metal oxide sidewall) may be in the z-direction, and share a contact line (e.g., the contact line183) going in the y-direction. An example of a junction184(e.g., a memristor device) is illustrated connecting a horizontal metal line to a via line. Each device may be therefore uniquely addressed by a signal applied to the horizontal metal line181and a signal applied to the contact line183that connects to a group of vertical vias.

FIG. 7Billustrates addressing of an integrated three-dimensional crossbar array190. Referring toFIG. 7B, for the crossbar array190, each device may be addressed by a horizontal metal line191independently addressed from the set of horizontal metal lines shown, a respective vertical via line192, which in turn is connected to a respective orthogonal contact line193. Examples of junctions194(e.g., a memristor device) are illustrated connecting a horizontal metal line to a via line. Assuming the left-most junction194in theFIG. 7Bconfiguration is to be addressed, a pulse may be applied to the left-most contact line193, and the top-most horizontal metal line191(four horizontal metal lines labeled inFIG. 7B). Thus a contact line193may link to other junctions via other vertical via lines192. Thus for the left-most junction194, addressing the left-most contact line193, and the top-most horizontal metal line191is sufficient to address the left-most junction194.

As shown inFIG. 8and discussed above with reference toFIG. 2A, a stacked crossbar array may include deposited alternating layers of metal, such as, for example, Platinum (Pt), Titanium Nitride (TiN), Tungsten (W), Copper (Cu), Tantalum Nitride (TaN), Titanium (Ti), Tantalum (Ta), Aluminum (Al) and metal oxides such as, for example, Ti407, and insulator, such as, for example, Silicon Dioxide (SiO2), Silicon Nitride (Si3N4), spin-on glass and Silicon (Si). The metal may be homogeneous or include a combination of materials. The combinations of materials may include, for example, a vacancy-rich metal oxide that serves as a vacancy and/or oxygen source, and a metal that forms a Schottky barrier with the switching layer. These combinations may be provided in addition to the main conductor metal layer. For example, as shown inFIG. 8, the diagram of a stacked crossbar array200illustrates metal layers201including Titanium Nitride (TiN), Tungsten and Ti407. For the foregoing examples of metals, Titanium Nitride may be more robust compared to Tungsten or Copper. Ti407 may be an example of a vacancy-rich metal oxide that serves as a vacancy and/or oxygen source. TiN may be an example of an interface metal, and Tungsten may be an example of the main conductor. By using TiO2or Ti407, a reservoir of oxygen vacancies may be provided to the transition metal oxide layer that coats the interior of the via hole. The multiple components may be deposited sequentially and processed (e.g., etched) simultaneously. For trench etching, use of Tungsten or Copper may facilitate lateral undercutting or etching.

Referring toFIG. 9, when such multi-component thin film stacks are etched through during line patterning, the difference in the etch rates can result in a selective lateral underetching of the layers. As shown inFIG. 9at202, in some etch chemistries, Tungsten may etch significantly faster than TiN or Ti407. The use of such metal combinations may facilitate control of the switching functionality of a device.

Referring toFIG. 10, at203, the stacked crossbar array200is shown after the filling insulator is deposited into the etched trenches and planarized. At204, vertical vias may be etched through and contact the edges of the metal lines. The inside of the via holes may be coated with the switching oxide and a barrier metal, and the interior of the holes may be filled with a metal. For example, the TMO film205may be formed of TiO2and/or Tantalum Oxide (TaOx), and include an inner layer206formed of TiN between the TMO film and metal core207. This configuration provides contact to be selectively made with the protruding components of the etched lines, and switching may occur at208.

While the embodiments have been described with reference to examples, various modifications to the described embodiments may be made without departing from the scope of the claimed embodiments.