Multiport memory with matching address control

A multiport SRAM has an array of cells, a first port, and a second port. During a period of different row addresses for the ports, the first port uses first word lines and first bit lines. The second port uses second word lines and second bit lines. In response to the second port switching to the same address as the first port to make a row match, the second port and the first port use the first plurality of word lines, but the first port uses the first plurality of bit lines and the second port uses the second plurality of bit lines. If the row match is removed by the first port changing row addresses, a correlation swap is performed so that the first port performs accesses using the second word lines and bit lines and the second port performs accesses using the first word lines and bit lines.

BACKGROUND

This disclosure relates generally to semiconductor devices, and more specifically, to multiport semiconductor memory devices.

2. Related Art

Along with recent advancements of semiconductor technologies, smaller-size and larger-capacity memories that allow high-speed reading/writing operations have been developed. Further, a so-called multiport memory including plural input ports and output ports has been used for reading/writing data of different addresses.

Multi-port memories, by providing access to the storage element of memory cells (otherwise known as bit cells) to more than one resource, such as in the case of multi-core processor or an interface between a processor and a bus, have become more commonly used. One of the issues with multi-port memories is how to coordinate this aspect of providing access to more than one resource. Often this ability is achieved using wait states and/or arbitration. This can result in unpredictable access times which is undesirable. Furthermore, in some scenarios, it is necessary for a multiport memory to interface to other logic units having different operating frequencies.

Accordingly there is a need for a multi-port memory that improves upon one or more of the issues discussed above.

DETAILED DESCRIPTION

In one aspect, a multiple port memory (i.e. a multiport memory) supports simultaneous read and write accesses. For example, the multiport memory may be a dual port memory having ports A and B, in which each of ports A and B can process an access request simultaneously. For example, in one embodiment, the multiport memory can include an array of bit cells which is independently addressable by first circuitry, which may be referred to as X-circuitry, and second circuitry, which may be referred to as Y-circuitry. The X-circuitry may include corresponding word lines and bit line pairs coupled to the array of bit cells, along with corresponding access and control circuitry, and the Y-circuitry may include corresponding word lines and bit line pairs coupled to the array of bit cells, along with corresponding access and control circuitry. In this manner, each bit cell of the array can either be accessed by the X-circuitry or the Y-circuitry. The X-circuitry operates in accordance with a corresponding clock (CLKX), and the Y-circuitry operates in accordance with a corresponding clock (CLKY). CLKX and CLKY may be asynchronous to each other. That is, they may be out of phase with each other and/or have different frequencies.

In one embodiment, port assignment control circuitry within the multiport memory is used to assign which of the X-circuitry or Y-circuitry is used to process access requests from port A or port B. Either of X-circuitry or Y-circuitry can be assigned by the port assignment control circuitry to process access requests from either port A or port B. Note that if the X-circuitry is assigned to process requests from port A, then the Y-circuitry is assigned to process requests from port B, and vice versa. For example, in the former case, the word lines and bit line pairs corresponding to the X-circuitry are used to access the bit cells for the read or write request from port A and the word lines and bit line pairs corresponding to circuitry Y are used to access the bit cells for the read or write request from port B. In one embodiment, X-circuitry is able to process an access received at its assigned port within one cycle of CLKX and Y-circuitry is able to process an access received at its assigned port within one cycle of CLKY.

No conflict arises so long as different rows are being accessed by each port. However, when the same row is addressed by the access requests on ports A and B (but different bit cells, i.e. columns, within the same row are being addressed by the access requests), a bit line pair and selected word line of only one of the X-circuitry or Y-circuitry is used to access the bit cells. In this situation, the bit line pair of the other of the X-circuitry or Y-circuitry is kept decoupled from the bit cells and the word line of the other of the X-circuitry or Y-circuitry is kept disabled. In this manner, the capacitance of the bit line pair of the circuitry not being used to access the bit cells is kept from adversely impacting the access to the selected bit cells. However, upon port A or B receiving a subsequent access request to a different row, the port assignment control circuitry may “swap” or “toggle” the assignments of the X and Y circuitry in order to take advantage of the X or Y circuitry that was not being used for the previous access request. If the X-circuitry was assigned to port A and the Y-circuitry to port B, a “swap” or “toggle” would result in X-circuitry being assigned to port B and the Y-circuitry being assigned to port A. The port assignment control circuitry, based on a variety of conditions, can determine when this port assignment swap should be performed.

For example, if the X-circuitry is assigned to port A and is currently processing an access request from port A, and an access request is received from port B which also addressees the same row, the X-circuitry will be “shared” to process both the access from port A and the access from port B, even though the Y-circuitry is currently assigned to port B. This “sharing” results in the word lines and bit lines of the X-circuitry being used to access the bit cells addressed by the access request from port A as well to access the bit cells addressed by the access request from port B. At this point, note that the Y-circuitry is not being utilized to access the array. A subsequent access request on port A may address a different row; however, the X-circuitry which is still assigned to port A may not be available because it may still be processing access requests from port B. Therefore, in this situation, the port assignment control circuitry may swap the assignments such that the X-circuitry is assigned to continue processing the access request and subsequent access requests from port B, and the Y-circuitry is assigned to process access requests from port A. In this manner, the subsequent access request received at port A can be immediately processed using the Y-circuitry, which B was not using due to “sharing” the X-circuitry for the same row access. This “swapping” as well as other aspects of the multiport memory will be further understood in reference to the drawings and the following description.

Shown inFIG. 1is a memory100having an array146, a column address buffer port A126, a column address buffer port B128, a crossbar switch104, a row address buffer port A120, a row address buffer port B122, a crossbar switch156, a row decoder X130, a row decoder Y132, I/O circuitry102, column circuitry118, an address match detector and clock arbitrator124, precharge circuit X162, precharge circuit Y166, port assignment (PA) control circuitry148, and X/Y access timing control106. Array146comprises bit cells138,140,142, and144.

PA control circuit148of memory100outputs a port assignment control signal, PA, which indicates which circuitry is assigned to which port (i.e. which circuitry is correlated to which port). In the descriptions herein, it will be assumed that when PA control circuitry148outputs PA as a logic level one, the X-circuitry is assigned to (i.e. correlated to) port A and the Y-circuitry is assigned to (i.e. correlated to) port B, and when PA is output as a logic level zero, the X-circuitry is assigned to (i.e. correlated to) port B and the Y-circuitry is assigned to (i.e. correlated to) port A. Therefore, based on the PA signal, the X or Y circuitry can either be assigned to process the access requests from either port A or port B. Alternate embodiments may assign the X-circuitry to port A when PA is a logic level zero and to port B when PA is a logic level one. Therefore, the PA signal provides the correlation between the X and Y circuitries and the ports. As will be described below, PA will be used by the crossbar switches to appropriately route port A and port B signals to the corresponding assigned X or Y circuitry. In one embodiment, the X-circuitry includes the X word lines, WL0X, WL1X, etc., the X bit lines, BL0X, BL0Xb, BL1X, BL1Xb, row decoder X130, precharge X162, and any other circuitry within column circuitry118, I/O circuitry102, and X/Y access timing control106used to access the bit cells of array146using the X word lines and X bit line pairs. In one embodiment, the Y-circuitry includes the Y word lines, WL1Y, WL1Y, etc., the Y bit lines, BL0Y, BL0Yb, BL1Y, BL1Yb, row decoder Y132, precharge Y166, and any other circuitry within column circuitry118, I/O circuitry102, and X/Y access timing control106used to access the bit cells of array146using the Y word lines and Y bit line pairs.

Column address buffer port A126receives a port A clock signal (CLKA) and a port A input column address (CAINA), and provides a buffered port A column address (CAA) to crossbar switch104. Similarly, column address buffer port B128receives a port B clock signal (CLKB) and a port B input column address (CAINB), and provides a buffered port B column address (CAB) to crossbar switch104. Based on PA, crossbar switch104provides CAA as column address X (CAX) or column address (Y) to column circuitry118and CAB as CAX or CAY to column circuitry118. For example, if PA is a logic level one, CAA is provided as CAX and CAB as CAY, and if PA is a logic level zero, CAA is provided as CAY and CAB as CAX. Row address buffer port A120receives CLKA and a port A input row address (RAINA), and provides a buffered port A row address (RAA) to crossbar switch156. Similarly, row address buffer port B122receives CLKB and a port B input row address (RAINB), and provides a buffered port B row address (RAB) to crossbar switch156. Based on PA, crossbar switch156provides RAA as RAX or RAY to row decoder X130or row decoder Y132, and RAB as RAX or RAY to row decoder X130or row decoder Y132. For example, if PA is a logic level one, RAA is provided as RAX to row decoder X130and RAB is provided as RAY to row decoder Y132, and if PA is a logic level zero, RAA is provided as RAY to row decoder Y132and RAB is provided as RAX to row decoder X130. Therefore, port A and port B can either be processed by the X-circuitry portion and Y-circuitry portion of memory100, respectively, or the Y-circuitry portion and the X-circuitry portion of memory100, respectively, based on the value of PA.

Shown inFIG. 8is a circuit diagram of an exemplary memory cell89which is exemplary for the other bit cells of array146such as memory cells138,140,142, and144. Bit cell138, which is a static random access memory (SRAM) cell, comprises inverters80and82connected to nodes84and86and transistors88,90,92, and94which are N channel transistors in this example. Inverter81has an input connected to node84and an output connected to node86. Inverter83has an input connected to node86and an output connected node84. Nodes84and86are storage nodes of memory cell138. Transistor88has a first current electrode connected to node84, a control electrode connected to word line WLX which is a word line of the X-circuitry, and a second current electrode connected to bit line BLXb which is a complementary bit line of the X-circuitry. Transistor90has a first current electrode connected to node86, a control electrode connected to word line WLX, and a second current electrode connected to bit line BLX which is a true bit line of the X-circuitry. Transistor92has a first current electrode connected to node84, a control electrode connected to a word line WLY, which is a word line of the Y-circuitry, and a second current electrode connected to complementary bit line BLYb of the Y-circuitry. Transistor94has a first current electrode connected to node86, a control electrode connected to word line WLY, and true bit line BLY of the Y-circuitry. Nodes84and86are storage nodes that are accessed through transistors88and92for node84and transistors90and94for node86. Inverters81and83together may be considered a storage latch. Transistors90and88are enabled when memory cell89is selected by the X-circuitry and for coupling the storage nodes to the bit line pair (BLX, BLXb) of the X-circuitry. Transistors92and94are enabled when memory cell89is selected by the Y-circuitry. In this example the bit lines are used for either writing to storage nodes84and86or reading from storage nodes84and86. The word lines are for enabling the coupling between storage nodes and bit lines. The control electrodes of transistors88and90may be considered X enable inputs corresponding to the X-circuitry and the control electrodes of transistors92and94may be considered Y enable inputs corresponding to the Y-circuitry. The second current electrodes of transistors88and90may be considered X access nodes corresponding to the X-circuitry, and the second current electrodes of transistors92and94may be considered Y access nodes corresponding to the Y-circuitry. In this manner, memory cell89can be accessed by way of the X-circuitry (using WLX, BLX, and BLXb) or by way of the Y-circuitry (using WLY, BLY, and BLYb).

Array146includes more than the four bit cells, which may be called memory cells, shown as memory cells138,140,142, and144inFIG. 1and accordingly more bit line pairs and word lines than shown. Memory cells138and140have their X enable inputs connected to word line WL0X and their Y enable inputs connected to word line WL0Y. The X access nodes of memory cell138are connected to true and complementary bit lines BL0X and BL0Xb, and the Y access nodes are connected to true and complementary bit lines BL0Y and BL0Yb. The X access nodes of memory cell140are connected to true and complementary bit lines BL1X and BL1Xb, and the Y access nodes are connected to true and complementary bit lines BL1Y and BL1Yb. Memory cells142and144have their X enable inputs connected to word line WL1X and their Y enable inputs connected to word line WL1Y. The X access nodes of memory cell142are connected to true and complementary bit lines BL0X and BL0Xb and the Y access nodes for are connected to true and complementary bit lines BL0Y and BL0Yb. The X access nodes of memory cell144are connected to true and complementary bit lines BL1X and BL1Xb, and the Y access nodes are connected to true and complementary bit lines BL1Y and BL1Yb.

RAX provides true and complementary row address signals which are routed to the X-circuitry from either port A or port B. RAY provides true and complementary row address signals which are routed to the Y-circuitry from either port A or port B. Row decoder X130is coupled to the combination of true and complementary address signals of RAX, and row decoder Y132is coupled to the combination of true and complementary address signals of RAY. Row decoder X130is coupled to each of the X word lines (WL0X, WL1X, etc.), and when row decoder X130outputs a logic level high for a word line, that word line is selected. Row decoder Y132is coupled to each of the Y word lines (WL0Y, WL1Y, etc.), and when row decoder Y132outputs a logic level high for a word line, that word line is selected.

Column circuitry118is coupled to bit lines BL0X, BL0Xb, BL0Y, BL0Yb, BL1X, BL1Xb, BL1Y, and BL1Yb, and in response to column addresses CAX and CAY, selects among these bit lines to sense data at the selected bit lines and couple the sensed data to global data lines GDLX for the X-circuitry and GDLY for the Y-circuitry or to provide write data from GDLX and GDLY to the selected bit lines for storage into array146. True and complementary bit lines of the same circuitry connected to the same column of cells may be referenced as a bit line pair. For example, bit lines BL0X and BL0Xb form a bit line pair. Similarly, data lines GDLX and GDLXb may be referenced as a data line pair. Column circuitry118will be described in more detail in reference toFIGS. 4 and 5.

I/O circuitry102is coupled to global data lines GDLX, GDLXb, GDLY, and GDLYb and appropriately routes data from the global data lines to DOUTB and/or DOUTA or from DINB and/or DINA to the global data lines. Within I/O circuitry102, PA is used to appropriately communicate data between GDLX (and GDLXb) and the port to which the X-circuitry is assigned and between GDLY (and GDLYb) and the port to which the Y-circuitry is assigned. I/O circuitry102will be described in more detail in reference toFIGS. 6 and 7.

FIG. 2illustrates address match detector and clock arbitrator124in more detail. Address match detector and clock arbitrator124receives CLKA, CLKB, TOG, XDONE, and YDONE and provides XFIRST, YFIRST, CLKX, CLKY, and MATCHRC. CLKA and CLKB refer to the clocks by which port A and port B, respectively, operate. They may be asynchronous with each other. That is, they may be out of phase and/or have different frequencies. As illustrated inFIG. 2, CLKA and CLKB are both provided to crossbar switch206, which provides CLKX and CLKY. CLKA and CLKB are provided as either CLKX and CLKY, respectively, or as CLKY and CLK X, respectively, based on PA. For example, as assumed herein, when PA is a logic level one, X-circuitry is assigned to port A and Y-circuitry to port B, therefore, CLKA is provided as CLKX, and CLKB is provided as CLKY. XDONE indicates when an access to array146is finished by the X-circuitry and YDONE indicates when an access to array146is finished by the Y-circuitry.

Referring back toFIG. 1, CLKX and CLKY are provided to X/Y access timing control106which outputs PCCKX, PCCKY, XDONE, and YDONE. In the illustrated embodiment, an access to array146is self timed based on rising edges of CLKX and CLKY. That is, all necessary timing signals used to activate the X-circuitry and the Y-circuitry (such as PCCKX, PCCKY, XDONE, and YDONE) are derived from the rising edges of CLKX and CLKY. An access using the X-circuitry (e.g. X word lines and X bit line pairs) is performed using CLKX in which, in response to a rising edge of CLKX, X/Y access timing control106asserts XDONE a predetermined amount of time later at which point the use of the X-circuitry for the access initiated by the rising edge of CLKX is completed. Similarly, an access using the Y-circuitry (e.g. Y word lines and Y bit line pairs) is performed using CLKY in which, in response to a rising edge of CLKY, X/Y access timing control106asserts YDONE a predetermined amount of time later at which point the use of the Y-circuitry for the access initiated by the rising edge of CLKY is completed. In this manner, XDONE and YDONE provide an indication of when the X-circuitry and the Y-circuitry, respectively, are not busy (and thus available for a next access). Also, X/Y access timing control106, provides precharge clock PCCKX based on CLKX to precharge X162and precharge clock PCCKY based on CLKY to precharge Y166. As will be described in reference to the timing diagram ofFIG. 3, precharge X162precharges the bit line pairs of the X-circuitry (e.g. BL0X, BL0Xb, BL1X, BL1Xb) and precharge Y166precharges the bit line pairs of the X-circuitry (e.g. BL0Y, BL0Yb, BL1Y, BL1Yb). In the case when each of port A and port B do not result in accessing a same row, precharge X162precharges the bit line pairs of the X-circuitry when XDONE is asserted, in preparation for a next access by the X-circuitry, and precharge Y166precharges the bit line pairs of the Y-circuitry when YDONE is asserted, in preparation for the next access by the Y-circuitry. However, in the case of a row match, precharging of the X or Y bit line pairs may be delayed, as will be seen in reference toFIG. 3.

Referring back toFIG. 2, address match detector and clock arbitrator124includes an address match detector204which receives CAA, CAB, RAA, and RAB, and provides MATCHR and MATCHC. If RAA and RAB match, then the row addresses of port A and port B match indicating that a same row is being accessed by the ports and MATCHR is therefore asserted to a logic level one to indicate a row match. If RAA and RAB do not match, then MATCHR is negated (a logic level zero). If CAA and CAB match, then the column address of port A and port B match indicated that a same column is being accessed by the ports and MATCHC is therefore asserted to a logic level one to indicate a column match. If CAA and CAB do not match, then MATCHC is negated (a logic level zero). MATCHR and MATCHC together are used to determine if both a row and column match has occurred. If so, MATCHRC may be asserted to a logic level one. Otherwise, if only a row match or a column match has occurred, MATCHRC is not asserted. Arbitrator202receives CLKA and CLKB and provides AF and BF. AF indicates whether CLKA was received first with respect to CLKB and BF indicates whether CLKB was received first with respect to CLKA. For example, upon the occurrence of rising or falling edges of either CLKA or CLKB, arbitrator selectively changes the values of AF and BF when CLKA and CLKB differ in value. For example, upon a rising edge of CLKA, if CLKB is a logic level zero at that point in time, AF is set to a logic level one and BF to a logic level zero indicating that CLKA is first. Similarly, when the falling edge of CLKA occurs and CLKB is a logic level high at that point, BF is set to a logic level one and AF is changed to a logic level zero indicating that CLKB is first. Therefore, in the illustrated embodiment, upon a transition of either CLKA or CLKB, AF is set to a logic level one if CLKA is a logic level one or BF is set to a logic level one if CLKB is a logic level one. This information provides a real time snapshot as to which is first in time, independent of whether or not the access addresses of port A and port B result in any matches. However, when a row match does occur, as indicated by assertion of MATCHR, the values of AF and BF are latched into set-reset (SR) flip flops210and212, respectively, as AFIRST and BFIRST. Therefore, AFIRST and BFIRST indicate which of CLKA or CLKB was first at the time a row match occurred. These values, along with the value of PA, can therefore be used to determine which circuitry, the X-circuitry or the Y-circuitry was being used first at the point at which a row match occurred.

As illustrated inFIG. 2, address match detector and clock arbitrator124includes AND gates224,226,228,230, and232, and SR flip flops210and212. Each of SR flip flops210and212includes a reset (R) input, a set (S) input, and a data output (Q). In operation, Q becomes a logic level one upon providing a logic level one to the S input, and Q remains a logic level one until a logic level one is provided to the R input (which resets Q to a logic level zero). AND gate226has a first input coupled to receive AF from arbitrator202, a second input coupled to receive an output of inverter222, and a third input coupled to receive MATCHR from address match detector204. AND gate228has a first input coupled to receive BF from arbitrator202, a second input coupled to receive the output of inverter222, and a third input coupled to receive MATCHR from address match detector204. AND gate230has a first input coupled to receive an output of AND gate226and a second input coupled to receive an output of inverter236. An input of inverter236is coupled to Q of SR flip flop212and thus receives BFIRST. An output of AND gate230is coupled to the S input of SR flip flop210. AND gate232has a first input coupled to receive an output of AND gate228and a second input coupled to receive an output of inverter234. An input of inverter234is coupled to Q of SR flip flop210and thus receives AFIRST. An output of AND gate232is coupled to the S input of SR flip flop212. The R input of each of SR flip flops210and212are coupled to the output of reset circuitry240. Note that when the output of reset circuitry240is asserted (i.e. a logic level one), each of AFIRST and BFIRST is reset to a logic level zero. The output of reset circuitry240is coupled to an input of inverter222. Therefore, while the output of reset circuitry240is not asserted (i.e. is a logic level zero), the output of inverter222is a logic level one and the outputs of AND gates226and228are determined by their other two inputs.

Therefore, in operation, when a MATCHR occurs and the output of reset circuitry240is not asserted (i.e. is a logic level zero), the value of AF is latched into SR flip flop210as AFIRST and the value of BF is latched into SR flip flop212as BFIRST. For example, if AF is a logic level one and MATCHR is asserted, the second input of AND gate230is a logic level one. Also, the previous value of Q of SR flip flop210is a logic level zero and thus the output of inverter236(and the first input of AND gate230) is a logic level one, thus latching AFIRST as a logic level one. In this case, the second input of AND gate232is a logic level zero (because BF is a logic level zero when AF is a logic level one), and the first input of AND gate232is also a logic level zero, thus ensuring that BFIRST remains at a logic level zero. Note that, in this example, AFIRST remains latched at a logic level one until reset by the assertion of the output of reset circuitry240.

AFIRST and BFIRST are each provided to crossbar switch214which, based on PA, provides AFIRST and BFIRST as either XFIRST and YFIRST, respectively, or YFIRST and XFIRST, respectively. Since PA determines which of X or Y circuitry is assigned to each port, XFIRST and YFIRST provide an indication as to which circuitry was in use first upon a row match and thus which circuitry will be “shared” as a result of the row match. For example, if PA is a logic level one, indicating that the X-circuitry is assigned to port A and the Y-circuitry to port B, then if AFIRST is asserted, XFIRST is also asserted by way of crossbar switch214. Since XFIRST is asserted, the X-circuitry is already in use to perform the access request initiated by the earlier rising edge of CLKA at the time a row match occurs (which results in the assertion of MATCHR due to RAB received from port B). Therefore, as will be described in reference to the timing diagram ofFIG. 3, the access request received later by port B which resulted in the row match will be performed by the X-circuitry, even though the PA value of a logic level one indicates that the Y-circuitry is assigned to port B. Similarly, if BFIRST is asserted, YFIRST is also asserted. In this case, the Y-circuitry is already in use to perform the access request initiated by the earlier rising edge of CLKB at the time a row match occurs (which results in the assertion of MATCHR due to RAA received from port A). Therefore, the access request received later by port A which resulted in the row match will be performed by the Y-circuitry, even though the PA value of a logic level one indicates that the X-circuitry is assigned to port A. Note that analogous descriptions would apply in the case in which PA is a logic level zero.

MATCHC, the output of inverter222, and MATCHR are provided as first, second, and third inputs of AND gate224. An output of AND gate224is coupled to the S input of SR flip flop208. The output of reset circuitry240is provided to the R input of SR flip flop208and the Q output of SR flip flop208provides MATCHRC. When the output of reset circuitry240is asserted (i.e. a logic level one), MATCHRC is reset to a logic level zero. While the output of reset circuitry240is not asserted (i.e. is a logic level zero), the output of inverter222is a logic level one and the outputs of AND gate224is determined by MATCHC and MATCHR. When the output of reset circuitry240is not asserted, an asserted value (a logic level one) of MATCHRC is latched in SR flip flop208because the output of AND gate224goes high. MATCHRC remains a logic level one until reset by the assertion of the output of reset circuitry240.

Reset circuitry240includes AND gates216and218, and OR gate220. AND gate216has a first input coupled to receive XDONE and a second input to receive YFIRST, and AND gate218has a first input to receive XFIRST and a second input to receive YDONE. OR gate220has a first input coupled to an output of AND gate216, a second input coupled to receive a toggle indicator (TOG) and a third input coupled to an output of AND gate218. An output of OR gate220provides the output of reset circuitry240and is coupled to the input of inverter222, and the R inputs flip flops208,210, and212. TOG is a signal generated within port assignment control circuitry148to indicate when a port assignment toggle should occur, in which each of X-circuitry and Y-circuitry is no longer assigned to its current port assignment, but switched and assigned to the other port. Therefore, note that a reset of the MATCHRC, AFIRST, and BFIRST (and also XFIRST and YFIRST) occurs when YFIRST and XDONE are both asserted, or when TOG is asserted, or when both XFIRST and YDONE are asserted. Under any of these conditions, operation of memory100returns to normal until another row match occurs.

Under normal operation, X-circuitry processes access requests from its assigned port and Y-circuitry processes access requests from its assigned port, in which the X-circuitry and Y-circuitry can operate to process requests simultaneously. However, operation changes upon a row match occurring, in which either the X or Y circuitry is shared by both ports. Furthermore, under certain conditions, the port assignments, as indicated by PA, are toggled by PA control circuitry148. The details of PA control circuitry148will be described in further detail below, after the description of column circuitry118.

FIGS. 4 and 5illustrate column circuitry118ofFIG. 1in more detail. The portion of column circuitry118inFIG. 4illustrates the coupling between the two illustrated columns of bit cells of array146ofFIG. 1and the corresponding data lines, e.g. DLX0, DLX0b, DLY0, and DLY0b. The portion of column circuitry118ofFIG. 4illustrates the R/W circuitry coupling the illustrated data lines ofFIG. 4and global data lines GDLX and GDLY. Note that additional circuitry similar to that ofFIGS. 4 and 5would be present to handle the remaining columns of array146.

Referring first toFIG. 4, column circuitry118includes transistors402,404,406,408,410,412,414,416,418,420,424,426,428,430, and432, OR gates434,446,464, and454, NOR gate462, and AND gates436,438,442,466,440,444,448,450,452,456,458, and460. Signals CAX0, CAY0, CAX1, and CAY1result from decoding CAX for signals CAX0and CAX1and result from decoding CAY for signals CAY0and CAY1. These signals may be referred to as an X or Y column address signal or an X or Y column decode signal. Transistor402has a first current electrode coupled to true bit line BL0X, a control electrode coupled to an output of OR gate434, and a second current electrode coupled to a true data line DLX0of the X-circuitry. Transistor404has a first current electrode coupled to complementary bit line BL0Xb, a control electrode coupled to the output of OR gate434, and a second current electrode coupled to a complementary data line DLX0bof the X-circuitry. Transistor406has a first current electrode coupled to true bit line BL0X, a control electrode coupled to an output of AND gate442, and a second current electrode coupled to a true data line DLY0of the Y-circuitry. Transistor408has a first current electrode coupled to complementary bit line BL0Xb, a control electrode coupled to the output of AND gate442, and a second current electrode coupled to a complementary data line DLY0bof the Y-circuitry. AND gate436has a first input coupled to receive XFIRST and a second input coupled to receive CAX0. AND gate438has a first input coupled to receive CAX0and a second input coupled to an output of NOR gate462. A first input of OR gate434is coupled to the output of AND gate436and a second input of OR gate434is coupled to the output of AND gate438. AND gate442has a first input coupled to receive MATCHRCb (the complement of MATCHRC), a second input coupled to receive CAY0, and a third input coupled to receive XFIRST. Transistor410has a first current electrode coupled to true bit line BL0Y, a control electrode coupled to an output of OR gate464, and a second current electrode coupled to a true data line DLY0of the Y-circuitry. Transistor412has a first current electrode coupled to complementary bit line BL0Yb, a control electrode coupled to the output of OR gate464, and a second current electrode coupled to a complementary data line DLY0bof the Y-circuitry. Transistor414has a first current electrode coupled to true bit line BL0Y, a control electrode coupled to an output of AND gate444, and a second current electrode coupled to a true data line DLX0of the X-circuitry. Transistor416has a first current electrode coupled to complementary bit line BL0Yb, a control electrode coupled to the output of AND gate444, and a second current electrode coupled to a complementary data line DLX0bof the X-circuitry. AND gate466has a first input coupled to receive YFIRST and a second input coupled to receive CAY0. AND gate440has a first input coupled to receive CAY0and a second input coupled to the output of NOR gate462. A first input of OR gate464is coupled to the output of AND gate466and a second input of OR gate464is coupled to the output of AND gate440. AND gate444has a first input coupled to receive YFIRST, a second input coupled to receive CAX0, and a third input coupled to receive MATCHRCb.

Continuing withFIG. 4, transistor418has a first current electrode coupled to true bit line BL1X, a control electrode coupled to an output of OR gate446, and a second current electrode coupled to DLX0of the X-circuitry. Transistor420has a first current electrode coupled to complementary bit line BL1Xb, a control electrode coupled to the output of OR gate446, and a second current electrode coupled to DLX0bof the X-circuitry. Transistor422has a first current electrode coupled to true bit line BL1X, a control electrode coupled to an output of AND gate452, and a second current electrode coupled to DLY0of the Y-circuitry. Transistor424has a first current electrode coupled to complementary bit line BL1Xb, a control electrode coupled to the output of AND gate452, and a second current electrode coupled to DLY0bof the Y-circuitry. AND gate448has a first input coupled to receive XFIRST and a second input coupled to receive CAX1. AND gate450has a first input coupled to receive CAX1and a second input coupled to the output of NOR gate462. A first input of OR gate446is coupled to the output of AND gate448and a second input of OR gate446is coupled to the output of AND gate450. AND gate452has a first input coupled to receive MATCHRCb, a second input coupled to receive CAY1, and a third input coupled to receive XFIRST. Transistor426has a first current electrode coupled to true bit line BL1Y, a control electrode coupled to an output of OR gate454, and a second current electrode coupled to DLY0of the Y-circuitry. Transistor428has a first current electrode coupled to BL1Yb, a control electrode coupled to the output of OR gate454, and a second current electrode coupled to DLY0bof the Y-circuitry. Transistor430has a first current electrode coupled to true bit line BL1Y, a control electrode coupled to an output of AND gate460, and a second current electrode coupled to DLX0of the X-circuitry. Transistor432has a first current electrode coupled to BL1Yb, a control electrode coupled to the output of AND gate460, and a second current electrode coupled to DLX0bof the X-circuitry. AND gate456has a first input coupled to receive YFIRST and a second input coupled to receive CAY1. AND gate458has a first input coupled to receive CAY1and a second input coupled to the output of NOR gate462. A first input of OR gate454is coupled to the output of AND gate456and a second input of OR gate454is coupled to the output of AND gate458. AND gate460has a first input coupled to receive XFIRST, a second input coupled to receive CAX1, and a third input coupled to receive MATCHRCb. NOR gate462has a first input coupled to receive XFIRST and a second input coupled to receive YFIRST.

During normal operation, in which no row match exists, XFIRST and YFIRST are each at a logic level zero and, as a result, the output of NOR gate462is a logic level one. AND gates436and448are deselected by XFIRST (such that its output is a logic level zero), and AND gates466and456are deselected by YFIRST (such that its output is a logic level zero). NAND gates438,440,450, and438receive a logic level one from the output of NOR gate462and are therefore activated to provide outputs corresponding to their respective address inputs. Therefore, the decoded column address signals CAX0and CAX1determine which of BL0X/BL0Xb or BL1X/BL1Xb are coupled to DLX0/DLX0bby way of AND gates438and450, and the decoded column address signals CAY0and CAY1determine which of BL0Y/BL0Yb or BL1Y/BL1Yb are coupled to DLY0/DLY0bby way of AND gates440and458. For example, for the decoded column address signals which are decoded from CAX (e.g. CAX0and CAX1), only one of the decoded column address signals will be a logic level high. Therefore, assuming CAX0is a logic level one, CAX1will be a logic level zero. In this case, the output of OR gate434is a logic level one and the output of OR gate464is a logic level zero. In this manner, DLX0is coupled to BL0X and decoupled from BL1X and DLX0bis coupled to BL0Xb and decoupled from BL1Xb. That is, for a given X-circuit column address, CAX, only one of BL0X/BL0Xb or BL1X/BL1Xb is coupled to DLX0/DLX0b. Analogous description applies the Y-circuitry. That is, based on the values of CAY0and CAY1, only one of BL0Y/BL0Yb or BL1Y/BL1Yb is coupled to DLY0/DLY0b.

When a row match as well as a column match exists, note that both the X-circuitry and Y-circuitry are accessing the same bit cells. When a row and column match exist, one of XFIRST or YFIRST is asserted, and MATCHRCb is a logic level zero (since MATCHRC is a logic level one). In this case, the addressed bit cells will be coupled to only one of the data line pairs (DLX0/DLX0bor DLY0/DLY0b). If XFIRST is asserted, the decoded column address signals CAX0and CAX1determine which of BL0X/BL0Xb or BL1X/BL1Xb are coupled to DLX0/DLX0bby way of AND gates436and448. In this case, no bit lines are coupled to DLY0/DLY0b(due to YFIRST being a logic level zero, MATCHRCb being a logic level zero, and XFIRST NOR YFIRST being a logic level zero, thus ensuring that the outputs of OR gates464and454, and AND gates442and452are logic level zeros). However, if YFIRST is asserted, the decoded column address signals CAW) and CAY1determine which of BL0Y/BL0Yb or BL1Y/BL1Yb are coupled to DLY0/DLY0bby way of AND gates466and456. In this case, no bit lines are coupled to DLX0/DLX0b(due to XFIRST being a logic level zero, MATCHRCb being a logic level one, and XFIRST NOR YFIRST being a logic level zero, thus ensuring that the outputs of OR gates434and446and AND gates444and460are logic level zeros).

When a row match exists, but no column match exists, note that one of XFIRST or YFIRST is asserted (as was described above in reference to address match detector and clock arbitrator124inFIGS. 1 and 2). Also, in this case, MATCHRCb is a logic level one (since MATCHRC is a logic level zero). In this case, the later received matching row address (corresponding to one of RAX or RAY) will share the bit lines and word lines in use by the earlier received matching row address. For example, if XFIRST is asserted, then the X-circuitry was processing an access request with RAX on X-circuitry when an access request with RAY for processing by the Y-circuitry resulted in a match with RAX. In this case, the selected word line of the X-circuitry can be activated by row decoder X130(in which row decoder Y132will be disabled by XFIRST since RAX and RAY have the same value, thus resulting in none of the word lines of the Y-circuitry being activated). Furthermore, the access request corresponding to RAY is processed using the addressed bit lines of the X-circuitry by coupling the X-circuitry bit lines of the addressed bit cells to the data lines (DLY0and DLY0b) of the Y-circuitry. In addition, since the access request corresponding to RAY is being processed by the X-circuitry, the addressed bit lines of the Y-circuitry are decoupled from the data lines (DLY0and DLY0b) of the Y-circuitry. Note that port A can be assigned to either X-circuitry or Y-circuitry and port B to the other of the X-circuitry or Y-circuitry, based on PA. That is, assertion of XFIRST may correspond to either the assertion of AFIRST or BFIRST, based on PA. In the case where PA is a logic level one and thus port A is assigned to the X-circuitry, if XFIRST is asserted, then the X-circuitry was processing an access request from port A when an access request arrived at port B having a row address which matches the row address of the access request from port A. Similarly, in the case where PA is a logic level zero and thus port B is assigned to the X-circuitry, if XFIRST is asserted, then the X-circuitry was processing an access request from port B when an access request arrived at port A having a row address which matches the row address of the access request from port B. Therefore, operation of the portion of column decoder118illustrated inFIG. 4operates the same regardless of the port assignment (i.e. regardless of the value of PA).

In order to better describe operation ofFIG. 4, an example will be described in which it is assumed that XFIRST is asserted, and that when XFIRST is asserted, MATCHRC is a logic level zero and MATCHRCb is a logic level one (indicating no column match), CAX0is a logic level zero, and CAY0is a logic level one. It is assumed for this example that CAY0is a logic level one before and after XFIRST is asserted. Note that since there is no column match, CAX0and CAY0cannot have the same value. Since CAX0is a logic level zero, CAX1must be a logic level one, and since CAY0is a logic level one, CAY1is a logic level zero. Therefore, just prior to XFIRST being asserted (when both XFIRST and YFIRST are logic level zeros), BL1X and BL1Xb are coupled by transistors418and420to DLX0and DLX0bsince the output of AND gate450is a logic level one, and BLX1and BLX1bare maintained decoupled from DLY0and DLY0bbecause the output of AND gate452is a logic level zero. Also, BL0Y and BL0Yb are coupled to DLY0and DLY0bby transistors410and412since the output of AND gate440is a logic level one, and BL0Y and BL0Yb are maintained decoupled from DLX0and DLX0bbecause the output of AND gate444is a logic level zero. Because CAX0is a logic level zero, BL0X and BL0Xb are decoupled from DLX0and DLX0b, and because CAY1is a logic level zero, BL1Y and BL1Yb are decoupled from DLY0and DLY0b. Therefore, both data line pairs DLX0and DLX0band data line pair DLY0and DLY0bare coupled to the corresponding selected X and Y bit line pairs prior to assertion of XFIRST. However, when XFIRST is asserted, the addressed bit cells use the bit lines of the X-circuitry to communicate with the data lines of the Y-circuitry. In the current example, since CAX0is a logic level zero and CAW) is a logic level one, the output of AND gate442is a logic level one, thus coupling BL0X and BL0Xb to DLY0and DLY0bby way of transistors406and408. Also, the word line addressed by RAX (which is the same address as RAY) is activated by row decoder X130. Therefore, the bit cells addressed by CAY and RAY (which resulted in a row match) use the word line and bit lines of the X-circuitry to communicate with the data lines of the Y-circuitry. Also, since XFIRST is asserted, BL0Y and BL0Yb are decoupled from DLY0and DLY0b(due to the output of AND gate440being a logic level zero and the output of AND gate466being a logic level zero). Therefore, in this example in which the Y-circuitry is using or “sharing” the word line and bit lines of the X-circuitry, note that the bit lines and word line of the Y-circuitry are deselected. Therefore, both ports A and B are using the same X-circuitry to address their bit cells. As will be described below in reference toFIG. 3, though, the port currently assigned to the X-circuitry by PA, whose word lines and bit lines are being used by the Y-circuitry, may receive an access request to an address which no longer results in a row match with RAY. In this case, that port, rather than waiting for the X-circuitry to complete the access being performed for the Y-circuitry, can be reassigned by PA control circuitry148to the currently unused Y-circuitry. Furthermore, the port currently assigned to the unused Y-circuitry is reassigned to the X-circuitry (which is the circuitry currently being used to process its access request). This results in a swap or toggle of port assignments (in which PA toggles in value).

Referring back to PA control circuitry148ofFIG. 1, PA control circuitry148provides PA and also determines when to toggle the value of PA, which results in a toggle of port assignments. PA control circuitry148includes inverters110and112, AND gates114and116, an OR gate118, and a toggle (T) flip flop108. T flip flop108has a clock input, and provides a data output, Q. When a rising clock edge is received at the clock input, the value of Q is toggled. That is, if output Q was a logic level one, then upon a rising edge of the clock input, it is transitioned to a logic level zero, and if it was a logic level zero, then upon a rising edge of the clock input, it is transitioned to a logic level one. Inverter110has an input coupled to receive YDONE, and inverter112has an input coupled to receive XDONE. AND gate114has a first input coupled to receive CLKX, a second input coupled to receive XFIRST from address match detector and clock arbitrator124, and a third input coupled to an output of inverter110. AND gate116has a first input coupled to receive YFIRST from address match detector and clock arbitrator124, a second input coupled to an output of inverter112, and a third input coupled to receive CLKY. OR gate118has a first input coupled to an output of AND gate114, a second input coupled to an output of AND gate116, and an output coupled to the clock input of T flip flop108. The output of OR gate118also provides the toggle signal (TOG) to address match detector and clock arbitrator124.

In operation, when XFIRST is asserted, indicating that Y is using the X-circuitry to perform its access, then once a rising edge of CLKX is received and the access for Y (which is using the X-circuitry) has not yet finished, TOG is asserted such that PA is toggled to switch the port assignments. Similarly, when YFIRST is asserted, indicating that X is using the Y-circuitry to perform its access, then once a rising edge of CLKY is received and the access for X (which is using the Y-circuitry) has not yet finished, TOG is also asserted such that PA is toggled to switch port assignments. That is, note that if the X-circuitry is being shared with the Y-circuitry, and the Y-circuitry is idle, PA may be toggled in the case where a next rising edge of CLKX is received but the Y access using the X-circuitry is not yet done. In this manner, by toggling the port assignments, even though the Y access using the X-circuitry has not finished, the port assignments are switched such that the port which was assigned to the X-circuitry and thus whose accesses were previously being performed by the X-circuitry can now be assigned to the Y-circuitry, which is currently idle due to the sharing in response to the row match. The new port assignment remains as toggled until a future timing condition, similar to the example above, results in another toggle. This will be further described in reference toFIG. 3.

FIG. 3illustrates, in timing diagram form, an example of a port assignment toggle in accordance with one example which includes waveforms of many of the signals described above. The timing diagram ofFIG. 3includes CLKA, a port A access address (AADD), CLKB, a port B access address (BADD), MATCHRC, PA, CLKX, CLKY, XDONE, YDONE, PCCLKX, PCCLKY, XFIRST, and YFIRST. Note that CLKA and CLKB have different frequencies and are out of phase with each other. A series of access addresses (AR0C0, AR1C1, AR2C2, and AR3C3) are received at port A at the rising edge of each clock cycle of CLKA. A series of access addresses (BR0C5, BR6C6, BR7C7, BR2C2, and BR8C8) are received at port B at the rising edge of each clock cycle of CLKB. The first letter of the access address nomenclature indicates whether the access address if from port A or ort B. The “R” portion of the access address nomenclature refers to the row address of the access address, and the “C” portion in the access address nomenclature refers to the column address of the access address. Initially, PA is a logic level one, which in the illustrated embodiment, indicates that port A is assigned to the X-circuitry and port B to the Y-circuitry. Therefore, CLKA is provided as CLKX, and CLKB as CLKY, as was described above in reference to address match detector and clock arbitrator124.

Upon the first illustrated rising edge of CLKX, the access request AR0C0is accepted for processing by the X-circuitry of memory100. Based on the rising edge of CLKX, self timed X/Y access timing control106asserts XDONE, which indicates when the X-circuitry is done processing AR0C0. Note that in the illustrated embodiment, memory100is capable of processing an access request received at port A within one clock cycle of CLKA, and processing an access request received at port B within one clock cycle of CLKB. Also, note that prior to the first illustrated rising edge of CLKX, the bit lines of the X-circuitry have been precharged by precharge X162, and prior to the first illustrated rising edge of CLKY, the bit lines of the Y-circuitry have been precharged by precharge Y166.

At time T1(which corresponds to a rising edge of CLKB and thus CLKY), the access request BR0C5is accepted for processing by the Y-circuitry of memory100. The row address of this access request, R0, matches the row address of the previous access request on port A, which is also R0. Therefore, a row match occurs at the rising edge of CLKY. However, no column match occurs because C0and C5do not match. XFIRST is asserted because the rising edge of CLKX which commenced processing of AR0C0occurred prior to the rising edge of CLKY which commenced processing of BR0C5. Also, MATCHRC remains negated at a logic level zero. Note that since a row match occurs, but not a column match, the Y-circuitry will use the addressed bit lines and word line of the X-circuitry to process the access request. That is, as described above in reference toFIG. 4, the column address, C5, will be used to determine which of the bit line pairs of the X-circuitry will be coupled to the data lines of the Y-circuitry. Also, the bit lines and word lines of the Y-circuitry are now idle because they are not being used to access BR0C5even though port B is assigned to the Y-circuitry. Based on self timing, other portions of the Y-circuitry, such as sensing or writing, may continue to be provided timing signals (not shown) from X/Y access timing control106prior to the assertion of YDONE at the end of the Y access. In the embodiment ofFIG. 3, YDONE is asserted at time T2.

In a non row match situation, X/Y access timing control106asserts PCCLKX based on XDONE and asserts PCCLY based on YDONE. That is, in a non row match situation, once the current access is done by the corresponding circuitry, the corresponding bit lines can be precharged. However, in a row match situation, in which bit lines are being shared, the precharge may need to be delayed until the sharing circuitry completes its access. For example, referring toFIG. 3, since the Y-circuitry is using the addressed word line and bit lines of the X-circuitry to process BR0C5, the bit lines of the X-circuitry cannot be precharged until both XDONE and YDONE are asserted, even though XDONE was asserted prior to T2. Therefore, both PCCLKX and PCCLKY are asserted at time T2in response to YDONE (since BR0C5is actually being processed by the bit lines and word lines of the X-circuitry). Even though the Y bit lines were not used, the Y bit lines are precharged to restore any drift in the voltage level during the time they were inactive. Also, when XFIRST and YDONE are both asserted, occurring at time T2, XFIRST is reset back to a logic level zero. Since XFIRST is reset to a logic level zero prior to the next rising edge of CLKX, no port swap is needed. That is, the sharing the word line and bit lies of the X-circuitry by the Y-circuitry ended prior to the X-circuitry having to access a different row. Upon the next rising302of CLKX (also corresponding to the next rising edge of CLKA), XFIRST is back to a logic level zero (and YFIRST remains a logic level zero), therefore, TOG is not asserted, and PA remains a logic level high.

At rising edge302of CLKX, since no toggle occurred, port A remains assigned to the X-circuitry and port B remains assigned to the Y-circuitry. At rising edge302, access address AR1C1is received and processed by the X-circuitry, and at the subsequent rising edge304of CLKY (also corresponding to the subsequent rising edge of CLKB), BR6C6is received and processed by the Y-circuitry. In this case, no row match occurs, so each access request is processed by its assigned circuitry without sharing. That is, the bit lines and word line of the X-circuitry addressed by AR1C1is used to process this request, and the bit lines and word line of the Y-circuitry addressed by BR6C6is used to process this request. XDONE is asserted in response to rising edge302, as is PCCLKX. YDONE is asserted in response to rising edge304, as is PCCLKY. Note that PCCLKX does not depend on YDONE in this case, and PCCLKY does not depend on XDONE since a row match did not occur.

At a subsequent rising edge306of CLKX (also corresponding to the subsequent rising edge of CLKA), access address AR2C2is received for processing by the X-circuitry. At a subsequent rising edge308of CLKY (also corresponding to the subsequent rising edge of CLKB), which occurs at time T3, access address BR2C2is received for processing by the Y-circuitry. In this case, both a row match and column match occur, therefore MATCHRC is asserted. Also, XFIRST is asserted at T3since AR2C2was received by port A prior to BR2C2being received by port B (and PA is a logic level one). Since XFIRST is asserted, the addressed bit lines and word line of the X-circuitry is being used to perform the access to both AR2C2and BR2C2(since they address the same bit cell) while the bit lines and word lines of the Y-circuitry are unused. Therefore, no precharging of the bit lines of the X or Y circuitry can be performed until the access to the same bit cell is done (until both XDONE and YDONE are asserted). However, at the subsequent rising edge310of CLKA at time T4, even though port A is still assigned to the X-circuitry, the X-circuitry cannot yet begin to process AR3C3(which is at a different row than currently being accessed by the X-circuitry) because, at time T4, YDONE has not yet been asserted. Note that although both AR2C2and BR2C2are accessing the same bit cell, the processing of BR2C2began later and will be completed later in time as compared to AR2C2since BR2C2is being processed in accordance with CLKY and not CLKX. Therefore, the X-circuitry must wait for YDONE to be asserted before processing a new access request to a different row (not R2anymore), such as AR3C3. In this case, upon occurrence of rising edge310of CLKA, which is still being provided as CLKX due to PA being a logic level one, since XFIRST is a logic level high (indicating that the X0-circutiry is being used to process a request assigned to the Y-circuitry) and YDONE has not yet been asserted, PA port assignment148asserts TOG to toggle PA so that PA, just after time T4, becomes a logic level low. At this point, port A is now assigned to the Y-circuitry and port B to the X-circuitry. This toggle also resets XFIRST and MATCHRC back to a logic level zero (as can be seen in the logic ofFIG. 2).

Therefore, due to the port assignment toggle, AR3C3is now processed by the Y-circuitry which was not being used by port B when port B was assigned to it. Furthermore, since the Y-circuitry is unused at time T4, AR3C3can immediately be processed. In this manner, the access request on port A can still be processed within a clock cycle of CLKA, without needing to incur any wait states, even though its circuitry was “shared” by the other port. Also, since port B is now assigned to the X-circuitry, the subsequently received access request by port B, corresponding to BR8C8, is processed by the X-circuitry. Therefore, note that in the first situation (with AR0C0and BR0C5) in which XFIRST was asserted, the “sharing” completed early enough before a port assignment toggle was needed, and thus the next accesses are processed by the same circuitry assigned to the port before the “sharing” occurred. However, in the second situation at time T4, the port assigned to the X-circuitry changed such that, while the X-circuitry was assigned to process the requests from port A just prior to assertion of XFIRST, after the transition of PA at time T4, the Y-circuitry is assigned to process the requests from port A and the X-circuitry is assigned to process the requests from port B. Because, at the time PA switched, the port B access request was already being processed using the X-circuitry and because the timing provided by X/Y access timing control106is self timed, the port B access request continues to completion without interruption in a single clock cycle of CLKB.

Referring now toFIG. 5,FIG. 5illustrates a second portion of column circuitry118which includes a portion of the R/W circuitry of column circuitry118coupling the illustrated data lines ofFIG. 4and global data lines GDLX and GDLY.FIG. 5includes an X sense amplifier (SA)502and an X write driver504which both correspond to the X-circuitry, and a Y SA506and a Y write driver508which both correspond to the Y-circuitry.FIG. 5also includes inverters514and524, AND gates510,516,520, and528, and NOR gates512,518,522, and530. A first sensing input of X SA502is coupled to DLX0, a second sensing input of X SA502is coupled to DLX0b, a control input of X SA502is coupled to an output of NOR gate512to receive an active low SA tri-state enable signal (SATSXb), and an output of X SA502is coupled to the GDLX bus. A first output of X write driver504is coupled to DLX0, a second output of X write driver504is coupled to DLX0b, and a control input of X write driver504is coupled to an output of NOR gate518to receive an active low write driver tri-state enable signal (WTTSXb). The input of X write driver504is coupled to global data line GDLX. A first input of AND gate510is coupled to receive YFIRST, a second input of AND gate510is coupled to receive MATCHRC. A first input of NOR gate512is coupled to an output of AND gate510, and a second input of NOR gate512is coupled to an output of inverter514. An input of inverter514is coupled to receive R/WX. A first input of AND gate516is coupled to receive MATCHRC, a second input of AND gate516is coupled to receive YFIRST. A first input of NOR gate518is coupled to an output of AND gate516, and a second input of NOR gate518is coupled to receive R/WX. A first sensing input of Y SA506is coupled to DLY0, a second sensing input of Y SA506is coupled to DLY0b, a control input of Y SA506is coupled to an output of NOR gate522to receive an active low SA tri-state enable signal (SATSYb), and an output of Y SA506is coupled to the GDLY bus. A first output of Y write driver508is coupled to DLY0, a second output of Y write driver508is coupled to DLY0b, and a control input of Y write driver508is coupled to an output of NOR gate530to receive an active low write driver tri-state enable signal (WTTSYb). The input of Y write driver508is coupled to global data line GDLY. A first input of AND gate520is coupled to receive XFIRST, a second input of AND gate520is coupled to receive MATCHRC. A first input of NOR gate522is coupled to an output of AND gate520, and a second input of NOR gate522is coupled to an output of inverter524. An input of inverter524is coupled to receive R/WY. A first input of AND gate528is coupled to receive MATCHRC, a second input of AND gate528is coupled to receive XFIRST. A first input of NOR gate530is coupled to an output of AND gate528, and a second input of NOR gate530is coupled to receive R/WY. Each of R/WX and R/WY may be provided with the access requests received by the port assigned to the X-circuitry and the port assigned to the Y-circuitry, respectively, as control signals provided with the access requests. The R/W signal indicates whether the corresponding access request is a read or a write. In the illustrated embodiment, if the R/W signal is asserted (e.g. a logic level one), then the access request is a read, else the access request is a write. The active low tri state enable signals (such as SATSXb, WTTSXb, SATSYb, and WTTSYb) disable (i.e. deactivate) the corresponding SA or write driver by placing the corresponding SA or write driver in tri-state mode when the signal is a logic level low or zero, and enable (i.e. activate) the corresponding SA or write driver when the signal is a logic level high or one. R/WX and R/WY will be further discussed in reference toFIG. 6.

In operation, when there is no row match, XFIRST and YFIRST are each logic level zeros and MATCHRC is also a logic level zero. Therefore, the outputs of AND gates510,516,520, and528are all logic level zeros. In this case, R/WX controls which of X SA514or X write driver504is enabled, and R/WY controls which of Y SA506or T write driver508is enabled. For example, for a read, R/WX is a logic level one causing inverter514to output a logic level zero, and therefore, the output of NOR gate512is a logic level one, thus enabling X SA502, and the output of NOR gate518is a logic level zero, thus disabling X write driver504. When X SA502is enabled, X SA502senses DLX0/DLX0band provides a data value for GDLX0to the global data line GDLX. For a write, R/WX is a logic level zero, and therefore, the output of NOR gate512is a logic level zero, thus disabling X SA502and the output of NOR gate518is a logic level one, thus enabling X write driver504. When X write driver504is enabled, X write driver504writes data from the global data line GDLX to DLX0/DLX0b. Note that analogous descriptions apply to R/WY, Y SA506and Y write driver508.

Similar operation occurs when there is a row match (in which XFIRST or YFIRST is a logic level one) but there is no column match (and thus MATCHRC is a logic level zero). Again, due to MATCHRC being a logic level zero, the outputs of AND gates510,516,520, and528are all logic level zeros. In this case, as in the case in which there is no row match described above, R/WX controls which of X SA514or X write driver504is enabled, and R/WY controls which of Y SA506or T write driver508is enabled.

However, when there is a row match and a column match, only one of the X portion of the R/W circuitry ofFIG. 5or the Y portion of the R/W circuitry ofFIG. 5(depending on which of the X-circuitry or the Y-circuitry was in use first) is used while the other of the X or Y portion ofFIG. 5is inhibited. For example, if XFIRST is a logic level one, then the X-circuitry was in use first at the time the row match occurred, as was described above, and YFIRST is a logic level zero. In this case, the output of AND gates510and516are a logic level zero, and the R/WX controls the enabling or disabling of X SA502and X write driver504. However, because XFIRST is a logic level one and MATCHRC is a logic level one, the outputs of each of AND gate520and528is a logic level one. Therefore, the output of NOR gates522and530are logic level zeros, regardless of the value of R/WY. Each of Y SA506and Y write driver508are therefore inhibited when there is a row and column match and XFIRST is a logic level one. Similarly, if YFIRST is a logic level one, then the Y-circuitry was in use first at the time the row match occurred, as was described above, and XFIRST is a logic level zero. In this case, the output of AND gates520and528are a logic level zero, and the R/WY controls the enabling or disabling of Y SA506and Y write driver508. However, because YFIRST is a logic level one and MATCHRC is a logic level one, the outputs of each of AND gate510and516is a logic level one. Therefore, the output of NOR gates512and518are logic level zeros, regardless of the value of R/WX. Each of X SA502and X write driver504are therefore inhibited when there is a row and column match and YFIRST is a logic level one.

R/W buffer B644receives an R/W input control signal corresponding to port B (referred to as R/WBIN), which is also provided to I/O buffers B646. An output of R/W buffer B644is coupled to an input of R/W latch B636, an output of which is coupled to provide R/WB (corresponding to a buffered and latched version of R/WBIN) to I/O buffers B646and I/O latches B638. R/W latch B636also receives CLKB. I/O buffers B646receive input data by port B (referred to as DINB) which may correspond to write data provided with a write access request on port B. I/O buffers B646also provide output data external to memory100from port B (referred to as DOUTB) which may correspond to read data provided in response to a read access request on port B. I/O buffers B646provide a buffered version of DINB to I/O latches B638as DIB, and receive latched data DOB from I/O latches B638. I/O latches B638is also coupled to an output of ARB632, an output of OR gate631, a first data terminal of transmission gate630, CLKB, MATCHRC, and R/WA (provided from R/W latch A642, to be described below). ARB632is coupled to the first terminal of transmission gate630, to a first terminal of transmission circuitry624, and is coupled to an output of OR gate631. OR gate631has a first input coupled to an output of AND gate633and a second input coupled to receive BDONE. AND gate633has a first input coupled to receive ADONE and a second input coupled to receive MATCHRC. Note that the output of OR gate631provides an enable signal to control inputs of ARB632and I/O latches B638.

R/W buffer A650receives an R/W input control signal corresponding to port A (referred to as R/WAIN), which is also provided to I/O buffers A648. An output of R/W buffer A650is coupled to an input of R/W latch A642, an output of which is coupled to provide R/WA (corresponding to a buffered and latched version of R/WAIN) to I/O buffers A648, I/O latches A640, and to I/O latches B638. R/W latch A642also receives CLKA. I/O buffers A648receive input data by port A (referred to as DINA) which may correspond to write data provided with a write access request on port A. I/O buffers A648also provide output data external to memory100from port A (referred to as DOUTA) which may correspond to read data provided in response to a read access request on port A. I/O buffers A648provide a buffered version of DINA to I/O latches A640as DIA, and receive latched data DOA from I/O latches A640. I/O latches A640is also coupled to an output of ARB634, an output of OR gate627, a second data terminal of transmission gate630, CLKBA, and MATCHRC. ARB634is coupled to the second terminal of transmission gate630, to a first terminal of transmission circuitry626, and is coupled to an output of OR gate627. OR gate627has a first input coupled to receive ADONE and a second input coupled an output of AND gate629. AND gate629has a first input coupled to receive BDONE and a second input coupled to receive MATCHRC. Note that the output of OR gate627provides an enable signal to control inputs of ARB634and I/O latches A640.

A second terminal of transmission circuitry624is coupled to an output of AND gate622, a third terminal of transmission circuitry624is coupled via the GDLB bus to crossbar switch604, and a fourth terminal of transmission circuitry624is coupled to an output of AND gate610. AND gate622has a first input coupled to receive R/WB and a second input coupled to an output of NAND gate608. NAND gate608has a first input coupled to receive the complement of R/WA (R/WAb), a second input coupled to receive BFIRST, and a third input coupled to receive MATCHRC. AND gate610provides TB to transmission circuitry624, and has a first input coupled to receive AFIRST and a second input coupled to receive MATCHRC. A control input of transmission gate630is coupled to receive MATCHRC, and an inverse control input of transmission gate630is coupled to an output of inverter628, whose input is coupled to receive MATCHRC. A second terminal of transmission circuitry626is coupled to an output of AND gate618, a third terminal of transmission circuitry626is coupled via the GDLA bus to crossbar switch604, and a fourth terminal of transmission circuitry626is coupled to an output of AND gate616. AND gate618has a first input coupled to receive R/WA and a second input coupled to an output of NAND gate620. NAND gate620has a first input coupled to receive the complement of R/WB (R/WBb), a second input coupled to receive MATCHRC, and a third input coupled to receive AFIRST. AND gate616provides TA to transmission circuitry626, and has a first input coupled to receive BFIRST and a second input coupled to receive MATCHRC.

Crossbar switch602has a control input coupled to receive PA and, based on PA, routes XDONE and YDONE to ADONE and BDONE, respectively, or to BDONE and ADONE, respectively. For example, if PA is a logic level one, then XDONE is routed to ADONE and YDONE to BDONE since the X-circuitry is assigned to port A and the Y-circuitry to port B. Crossbar switch604has a control input to receive PA, and, based on PA, routes the GDLX bus and the GDLY bus to the GDLA bus and the GDLB bus, respectively, or to the GDLB bus and GLDA bus, respectively. For example, if PA is a logic level one, then the GDLX bus is routed to the GDLA bus and the GDLY bus to the GDLB bus since the X-circuitry is assigned to port A and the Y-circuitry to port B. Crossbar switch606has a control input to receive PA, and, based on PA, routes R/WA and R/WB to R/WX and R/WY, respectively, or to R/WY and R/WX, respectively. For example, if PA is a logic level one, then R/WA is routed to R/WX and R/WB to R/WY since the X-circuitry is assigned to port A and the Y-circuitry to port B.

FIG. 7illustrates an example implementation of transmission circuitry626or624, in which the signals T, R/W, D, and GDL correspond to either TA, the output of AND gate618, DA, and GDLA ofFIG. 6or to TB, the output of AND gate622, DB, and GDLB ofFIG. 6. Transmission circuitry626and624are capable of being tri-stated (when T is a logic level one) in which D and GDL are held at high impedance or, when not in tri-state mode (when T is a logic level zero), allow for bidirectional communication between D and GDL, based on the value of R/W. For example, using transmission circuitry624as an example, if T is negated (i.e. a logic level zero) and R/W is a logic level one (indicating read), then the value of GDLB is provided as DB to the input of ARB632and the first terminal of transmission gate630. If T is negated and R/W is a logic level zero (indicating a write), then the value of DB is provided to GDLB. However, if T is asserted (i.e. a logic level one), then the transmission circuitry is in tri-state mode in which DB and GDLB are held at high impedance.

In operation, when there is no row match, or when there is a row match but not a column match, GDLB communicates with I/O latches B638by way of R/W transmission circuitry624to perform the access request on port B and GDLA communicates with I/O latches640by way of R/W transmission circuitry626to perform the access request on port A. However, when there is a row match and a column match, either AFIRST or BFIRST is a logic level one. Note that that results in either XFIRST or YFIRST being asserted, as was described above in reference toFIG. 2, in which one of XFIRST or YFIRST is a logic level one is asserted is based on the value of PA. Also, with both a row match and a column match, MATCHRC is a logic level one. In this case, one of R/W transmission circuitry624or R/W transmission circuitry626is disabled and placed in high impedance mode such that only one R/W transmission circuitry is shared by port A and port B. For example, if AFIRST is asserted (and MATCHRC is a logic level one), then the output of AND gate610is a logic level one, thus asserting TB at the T input of transmission circuitry624, placing it in tri-state mode. In this case, GDLB and DB are held at high impedance. Also, if AFIRST is asserted, then BFIRST is a logic level zero, and the output of AND gate616is a logic level zero, thus negating TA at the T input of transmission circuitry626, thus allowing transmission circuitry626to communicate data between DA and GDLA based on the output of AND gate618. (Analogous descriptions apply in the case of BFIRST being asserted in which transmission circuitry624would be enabled to communicate data between DB and GDLB based on its R/W input and transmission circuitry626would be placed in tri-state mode.)

Continuing with the example in which AFIRST is a logic level one and MATCHRC is a logic level one, port A and port B both share transmission circuitry626for performing its read or write. It is also assumed that both port A and port B cannot both be performing a write to the same location (which thus resulted in the row and column match). Therefore, port A and port B, at the time a row and column match occurs, may either be performing a read and a read, respectively, a read and write, respectively, or a write and a read, respectively. In the case of both ports performing a read, R/WA and R/WB are both logic level ones. Therefore, the output of NAND gate620is a logic level one (since R/WBb, the complement of R/WB, is a logic level zero) and the output of AND gate618is a logic level one. Transmission circuitry626is thus enabled to provide the values of GDLA to DA. The value of DA is provided through ARB634to I/O latches A640and I/O buffers A648to be provided as DOUTA. ARB634, in this case, is enabled by MATCHRC and ADONE both being a logic level one. Also, since both ports A and B are reading to the same location, the value of DA is also provided via transmission gate630(enabled since MATCHRC is a logic level one) to I/O latches B638and I/O buffers B646to be provided as DOUTB. Therefore, as was described above, only one of the X-circuitry or Y-circuitry is used to access the same data location, and the data (originally from either GDLY or GDLX) is then provided as the output of both ports A and B.

Continuing with the above example, in the case of port A performing a write and port B performing a read, R/WA is a logic level zero and R/WB is a logic level one. In this case, the output of AND gate618is a logic level zero. Transmission circuitry626is thus enabled to perform a write in which the values of DA are provided to GDLA. In this example, since port A is performing a write, DINA is provided through ARB634and via I/O buffers A648and I/O latches A640as DA to GDLA. ARB634is enabled, in this case, by MATCHRC and ADONE both being a logic level one. Furthermore, GDLA is provided as either GDLX or GDLY by crossbar switch604based on the value of PA. Also, since port B is performing a read to the same location that port A is writing, port B need not read the value from the bit cell itself. Instead, the write value from port A provided as DINA can be provided as the read value, DOUTB, for port B. In this case, the value of DA is also provided, via transmission gate630, as DB to I/O latches B638and I/O buffers B646to be provided as DOUTB. That is, note that DA and DB form a common bus when transmission gate630is enabled by the assertion of MATCHRC.

Continuing with the above example, in the case of port A performing a read and port B performing a write, R/WA is a logic level one and R/WB is a logic level zero. In this case, the output of AND gate618is again a logic level zero thus enabling transmission circuitry626to perform a write in which the values of DA are provided to GDLA. Since port B is performing a write, DINB is provided via I/O buffers B646and I/O latches B638as DB. Since DB forms a common bus with DA via transmission gate630, DB is provided as DA which is provided to GDLA via transmission circuitry626. Furthermore, GDLA is provided as either GDLX or GDLY by crossbar switch604based on the value of PA. Also, since port A is performing a read to the same location that port B is writing, port A need not read the value from the bit cell itself. Instead, the write value from port B provided as DINB can be provided as the read value, DOUTA, for port A. In this case, the value of DB is also provided, via transmission gate630, as DA to I/O latches A640and I/O buffers A648to be provided as DOUTA.

Note that analogous operation occurs in the case of a row match and a column match in which BFIRST is asserted. In this case, for each situation described above (a read on both ports A and B, a write on port A and a read on port B, or a read on port A and a write on port B), transmission circuitry624would be shared. In the case of both ports performing a read, the data from GDLB via transmission circuitry624would be provided as both DOUTB and DOUTA. In the case of a read on port A and a write on port B, DINB would be provided as GDLB via transmission circuitry624and provided by the common bus formed by transmission gate630as DA to be provided as DOUTA. In the case of a write on port A and a read on port B, DINA would be provided as GDLB via transmission gate630and transmission circuitry624and would also be provided as DOUTB.

Note that DB is provided both to I/O latches B638and to ARB632which is also coupled to the output of OR gate631, and DA is provided to I/O latches A640and to ARB634which is also coupled to the output of OR gate627. The arbiters are used in the situation in which one port is performing a read and a late write occurs which results in a match. In this situation, the arbiters are designed so that they either choose to provide the read data that is read from the bit cell of array146and provided by one of GDLY or GDLX (based on PA) or the to provide the write data received at the other port corresponding to the late write. The arbiter may be designed such that if a later write to a same location is received within a predetermined time of the earlier read on the other port, then the write data is provided as the read data at the other port, else the read data read from array146itself is provided as the read data at the other port. The timing for the arbitrator and latching the output of the arbitrator into the I/O latch is done when the signal BDONE for port B or ADONE for port A is asserted. For example, in the above example in which port B is a write and port A is a read, port A may have been performing its read first when the write at port B is received. At the time ADONE is asserted, then ARB634may direct the read data DA received from transmission circuitry626to I/O latches A640to be output as DOUTA. However, if the data DA is in transition due to a late write driving the bus, the value on DA may be indeterminate and the arbiter forces a decision as to whether read data or write data is written to I/O latches A640and outputted as DOA to I/O buffers A648.

Therefore, by now it can be appreciated how a multiple port memory may be interfaced with asynchronous circuitry such that the ports of the multiple port memory can operate according to different clocks. Each bit cell of the memory can be accessed by different sets of word lines and bit lines, in which each port of the memory can be assigned to a particular set of word lines and bit lines for performing its read and write access requests to the memory. In the case of a row match but not a column match between access requests on multiple ports, a particular set of word lines and bit lines may be shared by the multiple ports. However, if the port currently assigned to the shared set of word lines and bit lines needs to access a different row, the port assignments may be toggled so that the port can use a different (non-shared) set of word lines and bit lines rather than wait for the shared set of word lines and bit lines to be free. This toggling of the port assignments prevents occurrence of increased access latencies or wait states.

Because the apparatus implementing the present disclosure is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present disclosure and in order not to obfuscate or distract from the teachings of the present disclosure.

Although the disclosure is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. For example the invention was described in the context of two ports, it may be applied to memory architectures in which there are more than two ports. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

The following are various embodiments of the present disclosure.

Item 1 includes a method of operating a multiple port static random access memory (SRAM) having an array of bit cells arranged in rows and columns, a first port and a second port, a first row circuit coupled to the first port, a second row circuit coupled to the second port, a first column circuit coupled to the first port, a second column circuit coupled to the second port, a first plurality of word lines along the rows and a first plurality of bit lines along the columns working together to perform accesses to the array, and a second plurality of word lines along the rows and a second plurality of bit lines along the columns working together to perform accesses to the array, wherein each bit cell of the array is coupled to a word line from the first plurality of word lines and a word line from the second plurality of word lines. The method includes, during a first period of operation in which the rows being accessed by the first port are different than the rows being accessed by the second port, having a correlation in which the first port accesses the array using the first plurality of word lines and the first plurality of bit lines and the second port accesses the array using the second plurality of word lines and the second plurality of bit lines; in response to the second port switching to a row address that is the same as the row address of the first port, accessing the array for the second port using the first plurality of word lines and the first plurality of bit lines; and if the first port switches to a different row address prior to the second port switching to a different row address, performing a correlation swap so that the first port accesses the array using the second plurality of word lines and the second plurality of bit lines and the second port accesses the array using the first plurality of word lines and the first plurality of bit lines. Item 2 includes the method of item 1, wherein, if the second port switches to a different row address prior to the first port switching to a different row address, maintaining the correlation so that the first port accesses the array using the first plurality of word lines and the first plurality of bit lines and the second port accesses the array using the second plurality of word lines and the second plurality of bit lines. Item 3 includes the method of item 2, if the correlation swap is performed and there is a subsequent occurrence of the second port switching to a same row address as the first port, accessing the array for the first port and the second port using the second plurality of word lines and the second plurality of bit lines. Item 4 includes the method of item 3, and further includes, if after accessing the array for the first port and the second port using the second plurality of word lines and the second plurality of bit lines, the first port switches to a different row address prior to the second port switching to a different address, performing a correlation swap so that the first port accesses the array using the first plurality of word lines and the first plurality of bit lines and the second port performs accesses using the second plurality of word lines and the second plurality of bit lines. Item 5 includes the method of item 3, wherein, if after accessing the array for the first port and the second port using the second plurality of word lines and the second plurality of bit lines, the second port switches to a different row address prior to the first port switching to a different address, correlation of the first port accessing the array using the second plurality of word lines and the second plurality of bit lines and the second port accessing the array using the first plurality of word lines and the first plurality of bit lines is maintained. Item 6 includes the method of item 1, wherein, if the row addresses are different, accessing further includes accessing the first plurality of bit lines with a first read/write circuit and the second plurality of bit lines with a second read/write circuit. Item 7 includes the method of item 6, wherein, if the correlation swap occurs different accessing further includes accessing the first plurality of bit lines with a second read write circuit and the second plurality of bit lines with a first read write circuit. Item 8 includes the method of item 2, wherein, if the correlation swap is performed and an occurrence of the first port switching to the same row address as the second port, accessing the array for the first port and the second port using the first plurality of word lines and the first plurality of bit lines. Item 9 includes the method of item 1, wherein if the row address is the same for the first and second ports and a column address is the same for the first and second ports and the access is a read, using first column circuit to perform the read and providing results of the read for the first port and for the second port. Item 10 includes the method of item 1, if the correlation swap has been performed, coupling the second row circuit to the first plurality of word lines, the second column circuit to the first plurality of bit lines, the first row circuit to the second plurality of word lines, and the first column circuit to the second plurality of bit lines.

Item 11 includes a multiport static random access memory (SRAM) having a first correlation and a second correlation, and having a first port having a first row address buffer for receiving a first row address, a first column address buffer for receiving a first column address, and a first input/output buffer; a second port having a second row address buffer for receiving a second row address, a second column address buffer for receiving a second column address; and a second input/output buffer; an array of memory cells arranged in rows and columns; a first plurality of word lines along the rows and a first plurality of bit lines along the columns working together to perform accesses to the array, wherein each memory cell of the array of memory cells is coupled to a word line of the first plurality of word lines; a second plurality of word lines along the rows and a second plurality of bit lines along the columns working together to perform accesses to the array, wherein each memory cell of the array of memory cells is coupled to a word line of the second plurality of word lines; column circuitry coupled to the first and second plurality of bit lines; a column switch coupled to outputs of the first column address buffer and the second column address buffer and coupled to the column circuitry; a row switch coupled to an output of the first row address buffer and an output of the second row address buffer; a first row decoder coupled to the first plurality of word lines and a first output of the row switch; and a second row decoder coupled to the second plurality of word lines and a second output of the row switch, wherein: in the first correlation: the column switch couples the output of the first column address buffer to a first input of the column circuitry and couples the output of the second column address buffer to a second input of the column circuitry, in the second correlation: the row switch couples the output of the first address buffer to the second row decoder and the output of the second address buffer to the first row decoder; and the column switch couples the output of the first column address buffer to the second input of the column circuitry and couples the output of the second column address buffer to the first input of the column circuitry. Item 12 includes the multiport SRAM of item 11, in response to a row match in which the second row address becomes the same as the first row address when in the first correlation, the column circuitry decouples from the second plurality of bit lines and accesses a bit line pair of the first plurality of bit lines selected by the second column address. Item 13 includes the multiport SRAM of item 12, wherein the column circuitry is further characterized as having a first data line pair and a second data line pair in which, during the first correlation and the second correlation in the absence of a row match, the bit line pair of the first plurality of bit lines selected by the first column address is coupled to the first data line pair and a bit line pair of the second plurality of bit lines selected by the second column address is coupled to the second data line pair. Item 14 includes the multiport SRAM of item 13, wherein, in response to the row match in which the second row address becomes the same as the first row address in the first correlation, the column circuitry couples the bit line pair of the first plurality of bit lines selected by the second column address to the second data line pair. Item 15 includes the multiport SRAM of item 14, wherein the column circuitry further includes a write driver and a sense amplifier circuit coupling the first data line pair to first global data lines and the second data line pair to second global data lines. Item 16 includes the multiport SRAM of item 15, wherein the first port further includes a first input/output circuit and the second port further includes a second input/output circuit, the multiport SRAM further includes a crossbar switch that couples the first global data lines to the first input/output circuit and the second global data lines to the second input/output circuit in the first correlation and the first global data lines to the second input/output circuit and the second global data lines to the first input/output circuit in the second correlation. Item 17 includes the multiport SRAM of item 12, in response to removing the row match by changing the first row address, the multiport SRAM switches to the second correlation. Item 18 includes the multiport SRAM of item 12, in response to removing the row match by changing the second row address, the multiport SRAM remains in the first correlation. Item 19 includes the multiport SRAM of item 13, wherein a column match is present in addition to a row match, the bit line pair from the first plurality of the bit line pairs selected by both the first column address and the second column address is coupled to only the first data line.

Item 20 includes a method of operating a multiple port static random access memory (SRAM) having an array of memory cells arranged in rows and columns, a first port and a second port, a first plurality of word lines along the rows and a first plurality of bit lines along the columns working together to perform accesses to the array, and a second plurality of word lines along the rows and a second plurality of bit lines along the columns working together to perform accesses to the array, wherein each bit cell of the array is coupled to a word line from the first plurality of word lines and a word line from the second plurality of word lines. The method includes during a first period of operation in which the rows being accessed by the first port are different than the rows being accessed by second port, using the first plurality of word lines and the first plurality of bit lines to access the array for the first port and the second plurality of word lines and bit lines to access the array for the second port; in response to the second port switching to a row address that is the same as the row address of the first port, accessing the array for the second port using the first plurality of word lines and the first plurality of bit lines; and in response to the first port switching to a different row address prior to the second port switching to a different row address, accessing the array for the first port using the second plurality of word lines and the second plurality of bit lines and accessing the array for the second port using the first plurality of word lines and the first plurality of bit lines.