Semiconductor device with a step gate dielectric structure

A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an isolation structure formed in a substrate to define an active region of the substrate. The active region has a field plate region therein. A step gate dielectric structure is formed on the substrate in the field plate region. The step gate dielectric structure includes a first layer of a first dielectric material and a second layer of the dielectric material, laminated vertically to each other. The first and second layers of the first dielectric material are separated from each other by a second dielectric material layer. An etch rate of the second dielectric material layer to an etchant is different from that of the second layer of the first dielectric material. A method for forming a semiconductor device is also disclosed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method for forming the same, and in particular, to a semiconductor device having a shallow trench isolation (STI) structure and a method for forming the same.

2. Description of the Related Art

A power management integrated circuit (PMIC) is presently primarily applied to bipolar-CMOS (complementary metal oxide semiconductor transistor)-LDMOS (lateral diffused metal oxide semiconductor transistor) (BCD) structures. Complementary metal oxide semiconductor (CMOS) transistors may be used in digital circuits, bipolar transistors may be used for driving high current, and lateral diffused metal oxide semiconductor (LDMOS) transistors have high voltage (HV) handling capacity. The trends of power saving and high speed performance affect the structure of the LDMOS transistor. LDMOS transistor structures with lower leakage and on-resistance (RDSon) have been developed by semiconductor manufacturers.

The LDMOS devices are developed in various structures or by increasing the device size thereof to withstand a high off-state breakdown voltage. However, since the device size is increased, it is hard to reduce the on-resistance of the conventional LDMOS devices. RDSon is an important factor which affects the power consumption of the conventional LDMOS device. Therefore, the conventional LDMOS devices have a high on resistance to drain-source breakdown voltage ratio (Bvdss) (Ron/BVdss ratio), thereby affecting the reliability of the BCD processes.

Thus, a semiconductor device and a method for forming the same are desired to solve the aforementioned problems.

BRIEF SUMMARY OF INVENTION

A semiconductor device and a method for forming the same are provided. An exemplary embodiment of a semiconductor device comprises an isolation structure formed in a substrate to define an active region of the substrate. The active region has a field plate region therein. A step gate dielectric structure is formed on the substrate in the field plate region, wherein the step gate dielectric structure comprises a first layer of a first dielectric material and a second layer of the first dielectric material, laminated vertically to each other. The first and second layers of the first dielectric material are separated from each other by a second dielectric material layer. An etch rate of the second dielectric material layer to an etchant is different from that of the second layer of the first dielectric material to the etchant.

An exemplary embodiment of a method for forming a semiconductor device, comprises providing a substrate. A first layer of a first dielectric material and a second dielectric material layer are formed on a surface of the substrate in sequence. The first layer of the first dielectric material and the second dielectric material layer are patterned. A portion of the substrate is removed using the patterned first layer of the first dielectric material and the patterned second dielectric material layer as a hard mask to form an isolation trench. An isolation structure in the isolation trench is formed to define an active region of the substrate. A second layer of the first dielectric material is entirely formed. A mask pattern is formed on the second layer of the first dielectric material in the active region to define a field plate region in the active region. An etching process is performed to remove the second layer of the first dielectric material not covered by the mask pattern to form a second layer pattern of the first dielectric material, wherein the patterned second dielectric material layer serves as an etching stop layer for the etching process. The patterned first layer of the first dielectric material and the patterned second dielectric material layer not covered by the second layer pattern of the first dielectric material are removed to form a step gate dielectric structure on the substrate in the field plate region.

DETAILED DESCRIPTION OF INVENTION

The following description is of a mode for carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts.

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice the invention.

Embodiments provide a semiconductor device. In this embodiment, the semiconductor device may be a P-type bipolar-CMOS (complementary metal oxide semiconductor transistor)-LDMOS (lateral diffused metal oxide semiconductor transistor) (BCD). Embodiments use a hard mask layer used for formation of isolation structures (such as shallow trench isolations (STIs)), an additional deposition process and an additional photolithography/etching process to form a step gate dielectric structure on a surface of a substrate, in a field plate region of the substrate. The step gate dielectric structure is used to replace the STI field plate structure used in the conventional high voltage device. Compared with the conventional high voltage device, one embodiment of a step gate dielectric structure used in a high voltage device may have a reduced current path from a source region to a drain region of the high voltage device, thereby reducing the on-resistance (RDSon) while maintaining high breakdown voltage of a semiconductor device. Further, power consumption of a LDMOS transistor device can be reduced.

FIG. 1is a top view of one embodiment of a semiconductor device500of the invention.FIG. 2is a cross section taken along a line A-A′ ofFIG. 1, showing a cross section along a channel length direction of one embodiment of a semiconductor device500of the invention.FIG. 3is a cross section taken along a line B-B′ ofFIG. 1, showing a cross section along a channel width direction of one embodiment of a semiconductor device500of the invention. In this embodiment, the semiconductor device500may be a P-type BCD. As shown inFIGS. 1-3, in one embodiment, the semiconductor device500may comprise a substrate200, an isolation structure210and a step gate dielectric structure224. The isolation structure210is disposed in the substrate200to define an active region300of the substrate200, wherein the active region300has a field plate region302therein. Additionally, the step gate dielectric structure224is formed on the substrate200in the field plate region302. In one embodiment, the step gate dielectric structure224may comprise a first layer of a first dielectric material202and a second layer of the first dielectric material222vertically laminated to each other. Also, the step gate dielectric structure224may comprise a second dielectric material layer204. In one embodiment, the first and second layers of the first dielectric materials202and222are separated from each other by the second dielectric material layer204.

As shown inFIGS. 1-3, in one embodiment, the semiconductor device500may further comprise a first doped region216disposed in the active region300between the field plate region302and the isolation structure210, wherein a conductive type of the first doped region216is different from that of the substrate200in the active region300. The semiconductor device500may further comprise a second doped region212disposed in the substrate200in the active region300, wherein the second doped region212surrounds the first doped region216, and a conductive type of the first doped region216is different from that of the second doped region212. The semiconductor device500may further comprise a third doped region216disposed in the substrate200on the outside of the active region300, surrounding the isolation structure210, wherein the conductive type of the first doped region216is the same as that of the third doped region214. The semiconductor device500may further comprise a gate structure230disposed on the substrate200in the active region300, extended covering the first doped region216to the step gate dielectric structure224.

In one embodiment, the first layer of the first dielectric material202and the second dielectric material layer204, which are respectively formed by materials different from each other, may be collectively used as a hard mask for formation of isolation structures (such as shallow trench isolations (STIs)). Additionally, in one embodiment, both the first and second layers of the first dielectric materials202and222may be formed of materials which are the same as each other. Therefore, the second dielectric material layer204of the step gate dielectric structure224may be used as an etching stop layer of an etching process for formation of the step gate dielectric structure224.

FIGS. 4-5,6aand7aare cross sections taken along a line A-A′ ofFIG. 1, showing cross sections of one embodiment of a method for forming a semiconductor device500of the invention.FIGS. 6band7bare cross sections taken along a line B-B′ ofFIG. 1, showing cross sections of one embodiment of a method for forming a semiconductor device500of the invention. Please refer toFIGS. 1 and 4, first, a substrate200is provided. In one embodiment, the substrate200may comprise a silicon substrate. In alternative embodiments, SiGe, bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI), and other commonly used semiconductor substrates can be used for the semiconductor substrate200. The semiconductor substrate200may have a desired conductive type by implanting P-type or N-type dopants. In one embodiment, a conductive type of the substrate200is P-type.

Next, please refer toFIGS. 1 and 4, a first layer of a first dielectric material202and a second dielectric material layer204may be formed on the surface200in sequence by a deposition process. In one embodiment, the first layer of the first dielectric material202may comprise a pad oxide layer, and the second dielectric material layer204may comprise a nitride layer. The first layer of the first dielectric material202and the second dielectric material layer204may collectively serve as a hard mask layer206for formation of subsequently formed isolation structures210.

Next, please refer toFIGS. 1 and 4, the hard mask layer206is patterned to define formation positions of the subsequently formed isolation structures210?, and a portion of a surface201of the substrate200is exposed from the patterned hard mask layer206. Next, an etching process is performed to etch the exposed substrate200using the hard mask layer206as a hard mask to form at least one isolation trench208in the substrate200. Next, a liner layer232is formed on a sidewall209of the isolation trench208. Next, a high density plasma chemical vapor deposition (HDPCVD) process is performed to form a dielectric material234, for example, a high density plasma (HDP) oxide, on the hard mask layer206, filling the isolation trench208.

Next, please refer toFIGS. 1 and 5, a chemical mechanical polishing (CMP) process is performed to remove the unnecessary dielectric material234over the patterned second dielectric material layer204of the hard mask206to planarize surfaces of the dielectric material234and the second dielectric material layer204to form an isolation structure210, for example, shallow trench isolations (STIs), in the isolation trench208. The isolation structure210is formed from the surface201of the substrate200and extends into the substrate200. Also, a top surface of the isolation structure210is aligned to a top surface of the second dielectric material layer204. In this embodiment, the isolation structure210is used to define a position of an active region300of the substrate200.

Next, please refer toFIGS. 1,6aand6b, a doped region212may be formed in the substrate200in the active region300by an implantation process. A conductive type of the doped region212is different from that of the substrate200in the active region300. Also, a dopant concentration of the doped region212may be larger than that of the substrate200. In this embodiment, the doped region212may serve as an N-type drift doped region212, used as a channel region and a source region of a resulting semiconductor device.

Next, please refer toFIGS. 1,6aand6bagain, a doped region214may be formed in the substrate200on the outside of the active region300by another implantation process. The doped region214surrounds side boundaries of the isolation structure210and the doped region212. But a bottom boundary of the doped region212is not surrounded by the doped region214. In this embodiment, a conductive type of the doped region214may be the same as that of the substrate200. In this embodiment, a dopant concentration of the doped region214may be larger than that of the substrate200. In this embodiment, the doped region214may serve as a P-type well (PW) doped region214. In one embodiment, a process sequence of the doped regions212and214is not limited, and the process sequence of the doped regions212and214can be exchanged.

Next, please refer toFIGS. 1,6aand6bagain, a doped region216may be formed in the substrate200in the active region300by yet another implantation process. The doped region216may be formed in the active region300between the isolation structure210and a subsequently formed field plate region302. In this embodiment, a boundary of the doped region216may be surrounded by the doped region212. Also, a conductive type of the doped region216is different from that of the substrate200(i.e. a conductive type of the doped region216is different from that of the doped region214). In this embodiment, the doped region216may serve as a P-type drift doped region216, used as a drain region of a resulting semiconductor device. In one embodiment, an annealing process may be performed after forming the doped region216to laterally diffuse a dopant of the doped region216with a graded concentration distribution.

Next, please refer toFIGS. 1,6aand6bagain, a second layer of the first dielectric material221is entirely formed by a chemical vapor deposition (CVD) or atomic layer CVD (ALD) process on the hard mask206and the isolation structure210. In this embodiment, the second layer of the first dielectric material221may comprise a high temperature oxide (HTO). In one embodiment, a thickness of the second layer of the first dielectric material221, formed by the CVD or ALD process, may be well controlled according to design requirements. In one embodiment, a thickness of the second layer of the first dielectric material221may be much larger than a total thickness of the hard mask layer206. Also, a thickness of the first layer of a first dielectric material202may be less than that of the second layer of the first dielectric material221. In this embodiment, the first layer of a first dielectric material202and the second layer of the first dielectric material221may be formed by materials which are the same as each other, and the second layer of the first dielectric material221and the second dielectric material layer204may be designed to be formed by materials which are different from each other.

Next, please refer toFIGS. 1,6aand6bagain, a photolithography process is performed to form a mask pattern223on the second layer of the first dielectric material221in the active region300. The mask pattern223is used to define a formation position of a field plate region302in the active region300.

Next, please refer toFIGS. 1,7aand7b, an etching process, for example, an anisotropic etching process, is performed using the mask pattern223as an etching mask to remove the second layer of the first dielectric material221which is not covered by the mask pattern (as shown inFIGS. 6aand6b). In one embodiment, because the second layer of the first dielectric material221and the second dielectric material layer204are formed by materials different from each other, an etch rate of the second layer of the first dielectric material221to an etchant for the etching process is different from that of the second dielectric material layer204to the etchant for the etching process. Therefore, the etching process is performed until a surface of the second dielectric material layer204is exposed. After performing the etching process, a second layer pattern of the first dielectric material222is formed, wherein the patterned second dielectric material layer222may serve as an etching stop layer for the etching process

Next, please refer toFIGS. 1,2and3, another etching process, for example, a wet etching process, is performed to remove the patterned first layer of the first dielectric material202and the patterned second dielectric material layer204(i.e. the hard mask206) which is not covered by the second layer pattern of the first dielectric material222to the surface201of the substrate200is exposed, thereby forming a step gate dielectric structure224on the substrate200in the field plate region300. In one embodiment, the step gate dielectric structure224may comprise the patterned first layer of the first dielectric material202and the patterned second dielectric material layer204(i.e. the patterned hard mask206) and the second layer pattern of the first dielectric material222on the patterned second dielectric material layer204. In this embodiment, the step gate dielectric structure222may be an oxide-nitride-oxide (ONO) composite structure, in which the patterned first layer of the first dielectric material202is a pad oxide layer, the patterned second layer of the first dielectric material222is a high temperature oxide layer, and the patterned second dielectric material layer204is a nitride layer.

Next, please refer toFIGS. 1,2and3again to describe formations of a gate structure230, a first pick-up doped region218and a second pick-up doped region220. A gate dielectric layer226is formed on the substrate200in the active region300by a thermal oxidation, chemical vapor deposition (CVD) or atomic layer CVD (ALD) process. The gate dielectric layer226may comprise commonly used dielectric materials such as oxide nitride oxynitride, oxycarbide or combinations thereof. Also, the gate dielectric layer226may comprise high dielectric constant (k) dielectric materials (k>8) of aluminum oxide (Al2O3), hafnium oxide, (HfO2), hafnium oxynitride (HfON), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium oxynitride lanthalum oxide, (La2O3), cerium oxide, (CeO2), titanium oxide (TiO2), tantalum oxide (Ta2O5). Next, a gate layer228may be formed on the gate dielectric layer226by a film deposition process such as a CVD process. The gate layer228may comprise silicon or polysilicon. The gate layer228may be doped by a dopant to reduce sheet resistance thereof. Alternatively, the gate layer228may comprise amorphous silicon.

Next, please refer toFIGS. 1,2and3again, a pattern photoresist (not shown) is formed covering the gate layer228to define a formation position of a gate structure230. A portion of the gate dielectric226and a portion of the gate layer228to from a gate structure230on the substrate200in the active region300by an anisotropic etching process. Next, the patterned photoresist is removed. As shown inFIGS. 1,2and3, in one embodiment, the gate structure230is extended to cover the doped region216to the step gate dielectric structure224. In this embodiment, the gate structure230covers a portion of the doped region216and a portion of the step gate dielectric structure224. Also, a portion of the doped region216and a portion of the step gate dielectric structure224are exposed.

Next, please refer toFIGS. 1,2and3again, an implantation process is performed to form a first pick-up doped region218in a portion of the doped region212. Also, another implantation process is performed to form a second pick-up doped region220in a portion of doped region216. In one embodiment, a conductive type of the first pick-up doped region218is the same as that of the doped region212, and a conductive type of the second pick-up doped region220is the same as that of the doped region216. In this embodiment, the first pick-up doped region218may serve as a pick-up doped region of an N-type drift doped region of the semiconductor device, and a conductive type of the first pick-up doped region218is, for example, N-type. Additionally, the second pick-up doped region220may serve as a pick-up doped region of a P-type drift doped region of the semiconductor device, and a conductive type of the second pick-up doped region220is, for example, P-type. After performing the aforementioned processes, one embodiment of a semiconductor device500is formed completely.

As shown inFIGS. 1,2and3, the semiconductor device500uses a step gate dielectric structure224formed on the substrate200in the field plate region302to replace the local oxidation of silicon (LOCOS) structures or shallow trench isolation (STI) structures, which serve as a field plate structure of the conventional high voltage device. In one embodiment, the step gate dielectric structure may be an oxide-nitride-oxide (ONO) composite structure, in which an oxide at a lower layered-level (the first layer of the first dielectric material202) and a nitride at a middle layered-level (the second dielectric material layer204) of the ONO composite structure are collectively a hard mask layer for the formation isolation structures (such as STI structures). Also, the nitride at the middle layered-level of the ONO composite structure may serve as an etching stop layer for the etching process for the formation of the resulting step gate dielectric structure. Therefore, the gate structure230of the semiconductor device500may be extended to cover the step gate dielectric structure224on the substrate200to improve a reduced surface field (RESURF) of the semiconductor device500. The semiconductor device500may maintain high drain-source breakdown voltage (Bvdss). In this embodiment, a thickness T2of the step gate dielectric structure224may be designed (through the forming process) to not equal to a thickness T1of the isolation structure210. In this embodiment, a width W2of the step gate dielectric structure224may be designed to be less than that or equal to a width W1of the isolation structure210. Further, the step gate dielectric structure224is formed over the substrate200without extending into the substrate200. Therefore, compared with the conventional high voltage device, one embodiment of a step gate dielectric structure used in a high voltage device may have a reduced current path from a source region to a drain region of the high voltage device with maintaining a high drain-source breakdown voltage (Bvdss) of the semiconductor device500. So that the on-resistance (RDSon) can be reduced while maintaining high drain-source breakdown voltage (Bvdss) of the semiconductor device. Further, a power consumption of a LDMOS transistor device can be reduced. Moreover, the semiconductor device500having the reduced on-resistance (RDSon) while maintaining high drain-source breakdown voltage (Bvdss) may effectively decrease the on resistance to drain-source breakdown voltage ratio (Bvdss) (Ron/BVdss ratio), so that the semiconductor device500may withstand a higher operation voltage. Also, the semiconductor device500may have reduced pitch sizes and reduced cell sizes.