Magnetic memory with metal oxide etch stop layer and method for manufacturing the same

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; a magnetic layer in the second passivation layer; and an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide. A method for manufacturing a semiconductor structure is also disclosed.

BACKGROUND

Generally, an inductor is a passive electrical component that can store energy in a magnetic field created by an electric current passing through it. An inductor may be constructed as a coil of conductive material wrapped around a core of dielectric or magnetic material. One parameter of an inductor that may be measured is the inductor's ability to store magnetic energy, also known as the inductor's inductance. Another parameter that may be measured is the inductor's Quality (Q) factor. The Q factor of an inductor is a measure of the inductor's efficiency and may be calculated as the ratio of the inductor's inductive reactance to the inductor's resistance at a given frequency.

Traditionally, inductors are used as discrete components which are placed on a substrate such as a printed circuit board (PCB) and connected to other parts of the system, such as an integrated circuit (IC) chip, via contact pads and conductive traces. Discrete inductors are bulky, require larger footprints on the PCB, and consume lots of power. Due to the continued miniaturization of electric devices, it is desirable to integrate inductors into IC chips. Therefore, there is a need for manufacturing integrated inductors that provide the benefit of size, cost and power reduction without sacrificing the electrical performance.

DETAILED DESCRIPTION

The embodiments will be described with respect to embodiments in a specific context, namely an integrated inductor with a magnetic core. The embodiments may also be applied, however, to other integrated components.

FIG. 1illustrates a cross-sectional view of a semiconductor device100having an integrated inductor formed in passivation layers during the Back-End-Of-Line (BEOL) processing of semiconductor manufacturing process in accordance with an embodiment of the present disclosure. As shown inFIG. 1, an integrated inductor168includes a plurality of coils or windings that are concatenated and formed around a magnetic core142. The magnetic core142has an upper surface A and a lower surface A. The surfaces A and A′ are parallel to a substrate101. Each of the plurality of coils may include an upper portion162(hereafter upper coil segment162) and a lower portion132(hereafter lower coil segment132). In some embodiments, the lower coil segment132is formed in a passivation layer130below the magnetic core142, and the upper coil segment162is formed in another passivation layer160above the magnetic core142, and vias152connect the upper coil segment162with the lower coil segment132.

The integrated inductor168may connect to conductive traces and conductive pads, which may further connect to other conductive features of the semiconductor device100to perform specific functions of the design. Although not shown inFIG. 1, the integrated inductor may be connected through, e.g., vias to other conductive features formed in various layers of the semiconductor device100, in some embodiments.

The integrated inductor168, which includes the lower coil segment132, the vias152, the upper coil segment162and the magnetic core142, is formed in a plurality of passivation layers over semiconductor substrate101. Note that depending on the specific design for the upper coil segment162and the lower coil segment132, the upper coil segment162or the lower coil segment132may not be visible in a cross-sectional view, in some embodiments. In other embodiments, at least a portion of the upper coil segment162or/and at least a portion of the lower coil segment132may not be visible in a cross-sectional view. To simplify illustration, both the upper coils segments162and the lower coil segment132are shown as visible in all cross-sectional views in the present disclosure without intent to limit. One of ordinary skill in the art will appreciate that the embodiments illustrated in the present disclosure can be easily applied to various designs for the upper coils segments162and the lower coil segment132without departing from the spirit and scope of the present disclosure.

The semiconductor substrate101may include bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOD substrate. Generally, an SOL substrate includes a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.

The semiconductor substrate101may include active de not shownFIG. 1for conciseness). As one of ordinary skill in the art will recognize, a wide variety of active devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the desired structural and functional requirements of the design for the semiconductor device100. The active devices may be formed using any suitable methods.

The semiconductor substrate101may also include metallization layers (also not shown inFIG. 1for conciseness). The metallization layers may be formed over the active devices and are designed to connect the various active devices to form functional circuitry. The metallization layers (not shown) may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) and may be formed through any suitable process (such as deposition, damascene, dual damascene, etc,).

As illustrated inFIG. 1, passivation layers (e.g., a first passivation layer110, a second passivation layer120, the third passivation layer130, a fourth passivation layer140and the fifth passivation layer160) are formed consecutively over the substrate101, in some embodiments. The first passivation layer110may be disposed over the substrate101, and post-passivation interconnect (PPI)112may be formed in the first passivation layer110. The PPI may be connected to metal layers in the substrate101or other layers of the semiconductor device100by vias (not shown), in some embodiments. The PPI may be connected to the lower coil segment132formed in the third passivation layer130by the vias122, which are formed in the second passivation layer120, in some embodiments. The magnetic core142is formed in the fourth passivation layer140and is surrounded by and insulated from the lower coil segment132, the upper coil segment162, and the vias152. The magnetic core142has a trapezoidal cross-section. However, this is not a limitation of the present disclosure. In some embodiments, the magnetic core142may have a rectangular cross-section.

A lower surface A′ of the magnetic core142overlies the third passivation layer130, wherein an etch stop layer141is located between the lower surface A′ of the magnetic core142and the third passivation layer130. A fifth passivation layer160is formed over the fourth passivation layer140and the magnetic core142. The upper coil segment162is formed in the fifth passivation layer160. The vias152extend through the fourth passivation layer140to connect the upper coil segment162with the lower coil segment132. Solder balls172may be formed on the fifth passivation layer160for external connections.

The embodiment inFIG. 1shows five passivation layers, however, one of ordinary skill in the art will appreciate that more or less than five passivation layers may be formed without departing from the spirit and scope of the present disclosure. For example, there may be more passivation layers over the upper coil segment162, and there could be more or less passivation layers under lower coil segment132than those illustrated inFIG. 1. In addition, other features such as contact pads, conductive traces, and external connectors may be formed in/on the semiconductor device100, but are not shown inFIG. 1for conciseness.

FIG. 2A-FIG. 2Cillustrate cross-sectional views of the magnetic core142and the etch stop layer141in accordance with some embodiments of the present disclosure. InFIG. 2A, a first type of the etch stop layer141is disclosed. The etch stop layer141is formed around the lower surface A′ of the magnetic core142. The etch stop layer141includes an acid resistant layer which is acid resistant against a wet etching agent used to chemically etch the magnetic core142. Edge portions B′ extend from a central portion B of the etch stop layer141by a first distance d1. An upper surface of the edge portions B′ is lower than an upper surface of the central portion B of the etch stop layer141(i.e. the lower surface A′ of the magnetic core142) by a second distance d2. However, this is not a limitation of the present disclosure. In some embodiments, the edge portions B′ may not extend from the central portion B of the etch stop layer141. For example, the first distance d1equals 0. In some embodiments, the upper surface of the edge portions B′ may not lower than the upper surface of the central portion B of the etch stop layer141. For example, the second distance d2equals 0.

InFIG. 2B, a second type of the etch stop layer141is disclosed. The etch stop layer141includes an acid resistant layer141_2acting in the same way as the acid resistant layer ofFIG. 2A. The etch stop layer141ofFIG. 2Bfurther includes a stress buffer layer141_1acting as a stress buffer to reduce stress induced around an interface between the acid resistant layer141_2and the third passivation layer130underlying the acid resistant layer141_2. Sidewalls of the stress buffer layer141_1align with sidewalls of the acid resistant layer141_2. InFIG. 2B, the second distance d2is shorter than a distance d3between of the lower surface A′ of the magnetic core142and a lower surface of the acid resistant layer141_2. The distance d3may be the same to a thickness of the stress buffer layer141_1. However, this is not a limitation of the present disclosure. In some embodiments, the distance d3may be thicker or thinner than the thickness of the stress buffer layer141_1.

InFIG. 2C, a third type of the etch stop layer141is disclosed. The etch stop layer141includes two stress buffer layers141_1and141_3acting in the same way as the stress buffer layers141_1ofFIG. 2B, and two acid resistant layers141_2and141_4acting in the same way as the acid resistant layer ofFIG. 2AandFIG. 2B. In other words, two sets of the stress buffer layer and the acid resistant layer are orderly stacked under the magnetic core142in a repeating manner with the stress buffer layer and the acid resistant layer being interlaced. However, this is not a limitation of the present disclosure. In some embodiments, more than two sets of the stress buffer layer and the acid resistant layer may be formed under the the magnetic core142. InFIG. 2C, the second distance d2is shorter than a distance d4between of the lower surface A′ of the magnetic core142and a lower surface of the acid resistant layer141_4. The distance d3may be the same to a thickness of the stress buffer layer141_3, the acid resistant layer141_2and the stress buffer layers141_1. However, this is not a limitation of the present disclosure.

FIG. 3-FIG. 18illustrate cross-sectional views of the semiconductor device100at various stages of fabrication according to embodiments of the present disclosure. As illustrated inFIG. 3, the first passivation layer110may be formed on the semiconductor substrate101. The first passivation layer112may be made of polymers, such as polybenzoxazole (PBC)), polyimide, or benzocyclobutene, in some embodiments, or silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide, or aluminum oxide, in some other embodiments. The first passivation layer112may be formed through a process such as chemical vapor deposition (CVD), although any suitable process may be utilized. The first passivation layer112may have a thickness between about 0.5 urn and about 5 μm, however, other ranges of thickness are also possible, depending on the designs and requirements of the semiconductor device100.

The post-passivation interconnect (PPI)112may be formed over the semiconductor substrate101and within the first passivation layer110to provide an electrical connection between the integrated inductor168and other circuits of the semiconductor device100, in some embodiments. For example, the PPI112may be connected to metal layers (not shown) in the substrate101. The PPI112may be comprised of copper, but other materials, such as aluminum, may alternatively be used. An opening through the first passivation layer112may be made in the desired location of PPI112through a suitable process, such as a suitable photolithographic masking and etching. For example, a photoresist (not shown) may be formed on the first passivation layer110and may then be patterned in order to provide an opening in the first passivation layer110. The patterning may be performed by exposing the photoresist to a radiation such as light in order to activate photoactive chemicals that may make up one component of the photoresist. A positive developer or a negative developer may then be used to remove either the exposed or unexposed photoresist depending on whether positive or negative photoresist is used.

Once the photoresist has been developed and patterned, PPI112may be constructed by using the photoresist as a mask to form the opening into or through the first passivation layer110using, e.g., an etching process. The conductive material may then be formed into the opening into or through the first passivation layer110, e.g., by first applying a seed layer (not shown) into and along the sidewalls of the opening. The seed layer may then be utilized in an electroplating process in order to plate the conductive material into the opening into or through the first passivation layer110, thereby forming the first interconnect112. However, while the material and methods discussed are suitable to form the conductive material, these materials are merely exemplary. Any other suitable materials, such as tungsten, and any other suitable processes of formation, such as CVD or physical vapor deposition (PVD), may alternatively be used to form the PPI112.

A second passivation layer120may be formed over the first passivation layer110, as illustrated inFIG. 4. In some embodiments, the second passivation layer120may be comprised of the same material as the first passivation layer110. Alternatively, the second passivation layer120may include other suitable dielectric materials different from the materials in the first passivation layer110. Deposition process such as CVD, PVD, combinations thereof, or any other suitable processes of formation, can be used to form the second passivation layer120. The second passivation layer120may have a thickness between about 0.5 μm and about 5 μm, however, other ranges of thickness are also possible, depending on the designs and requirements of the semiconductor device100.

Vias122may be formed in the second passivation layer120to provide a conductive path between the PPI112in the first passivation layer110and the integrated inductor168formed in subsequent processing. The vias122may include copper, but other materials, such as aluminum or tungsten, may alternatively be used. The vias122may be formed, e.g., by forming openings for the vias122through the second passivation layer120using, e.g., a suitable photolithographic mask and etching process. After the openings for vias122have been formed, vias112may be formed using a seed layer (not shown) and a plating process, such as electrochemical plating, although other processes of formation, such as sputtering, evaporation, or plasma-enhanced CVD (PECVD) process, may alternatively be used depending upon the desired materials. Once the openings for vias112have been filled with conductive material, any excess conductive material outside of the openings for the vias112may be removed, and the vias112and the second passivation layer120may be planarized using, for example, a chemical mechanical polishing (CMP) process.

As illustrated inFIG. 5, the lower coil segment132is formed over the second passivation layer120. In accordance with some embodiments, the lower coil segment132may include copper. In one embodiment, the lower coil segment132has a thickness in a range between about 5 um and about 20 um. The above thickness range is merely an example, the dimensions of the integrated inductor168(e.g., the lower coil segment132, the upper coil segment162, the vias152and the magnetic core142) are determined by various factors such as the functional requirements for the integrated inductor168and process technologies, thus other dimensions for the integrated inductor168are possible and are fully intended to be included within the scope of the current disclosure.

Next, a third passivation layer130may be formed over the second passivation layer120and the lower coil segment132. The third passivation layer130may be comprised of the same material as the first passivation layer110and may be formed by CVD, P\/D, or any other suitable processes of formation, in some embodiments. Alternatively, the third passivation layer130may include other suitable materials different from the dielectric materials in the first passivation layer110. The thickness of the third passivation layer130may be larger than the thickness of the lower coil segment132so that the lower coil segment132is encapsulated in the third passivation layer130. The third passivation layer112may have a thickness between about 5 μm and about 20 μm, however, other ranges of thickness are also possible, depending on the designs and requirements of the semiconductor device100.

Referring next toFIG. 6, an etching process is performed to remove an upper portion of the third passivation layer130to expose an upper surface of the lower coil segment132, in some embodiments. As a result of the etching process, openings C extend into the third passivation layer130. The etching process is controlled to stop when reaching the lower coil segment132. Sidewalk of the openings C may be sloped. However, in some embodiments of the present disclosure, the openings C may have straight sidewalls

Next,FIG. 7toFIG. 8illustrate the formation of the first type of the etch stop layer141according to an embodiment of the present disclosure. InFIG. 7, a layer of the stress buffer layer141_1is blanket deposited over the third passivation layer130and the lower coil segment132. The stress buffer layer141_1may be made of one or more suitable materials such as tantalum (Ta), titanium (Ti), or the like. A thickness of the stress buffer layer141_1may be about 50 angstroms to about 300 angstroms, however, other ranges of thickness are also possible, depending on the designs and requirements of the semiconductor device100. InFIG. 8, the acid resistant layer141_2is obtained through an oxygen treatment performed upon the stress buffer layer141_1. In the embodiment, i.e., for the first type of the etch stop layer141, the layer141_1of Ta or Ti fully reacts with oxygen and completely turns into the layer141_2of TaO or TiO. In other words, the etch stop layer141only includes the acid resistant layer141_2. In some embodiments, formation of the first type of the etch stop layer141may be directly blanket depositing the acid resistant layer141_2of TaO or TiO over the third passivation layer130and the lower coil segment132by any suitable processes such as CVD, PVD, or combinations thereof.

FIG. 7andFIG. 14illustrate the formation of the second type of the etch stop layer141according to an embodiment of the present disclosure. InFIG. 8, the acid resistant layer141_2is obtained through an oxygen treatment performed upon the stress buffer layer141_1. In the embodiment, i.e., for the second type of the etch stop layer141, the layer141_1of Ta or Ti reacts with oxygen and an upper portion of the layer141_1turns into the layer141_2of TaO or TiO. A lower portion of the layer141_1keeps unreacted. In other words, the etch stop layer141includes the acid resistant layer141_2and the stress buffer layer141_1. A thickness of the stress buffer layer141_1may be about 50 angstroms to about 150 angstroms, and a thickness of the acid resistant layer141_2may be about 50 angstroms to about 250 angstroms. However, other ranges of thickness are also possible, depending on the designs and requirements of the semiconductor device100. In some embodiments, formation of the first type of the etch stop layer141may be directly blanket depositing the acid resistant layer141_2of Tao) or TiO over the stress buffer layer141_1.

FIG. 15toFIG. 18illustrate the formation of the third type of the etch stop layer141according to an embodiment of the present disclosure. The etch stop layer141ofFIG. 18includes two stress buffer layers141_1and141_3and two acid resistant layers141_2and141_4. In short, the third type of the etch stop layer141may be obtained by by repeating a deposition and oxygen treatment process two times or cycles, where each cycle of the deposition and oxygen treatment process forms the structure as the one illustrated inFIG. 14. In some embodiments, the total thickness of the etch stop layer141, including the stress buffer layers141_1, the acid resistant layers141_2, the stress buffer layers141_3and the acid resistant layers141_4, may be substantially the same to the thickness of the etch stop layer141of the first type or the second type. However, other ranges of thickness are also possible, depending on the designs and requirements of the semiconductor device100. In some embodiments, the third type of the etch stop layer141may be obtained by repeating the deposition and oxygen treatment process ofFIG. 14more than two cycles.

Referring back toFIG. 9, the magnetic material142is deposited over the etch stop layer141by a PVD, CVD, PE-CVD, combinations thereof, or any other suitable deposition process. In accordance with an embodiment, without intent of limiting, the magnetic material142is conformally deposited over the etch stop layer141. In accordance with some embodiments, the magnetic material142includes CoxZryTaz (CZT), where x, y, and z represents the atomic percentage of cobalt (Co), zirconium (Zr), and tantalum (Ta), respectively. In some embodiments, x is in a range from about 0.85 to about 0.95, v is in a range from about 0.025 to about 0.075, and z is in a range from about 0.025 to about 0.075. In accordance with some embodiments, the magnetic core142has a thickness of about 5 urn.

InFIG. 10, a portion of the magnetic material142may be removed through a wet etch. The remaining magnetic material142forms the magnetic core142. A wet etching agent for the wet etch may include a I-IF solution, a HNO3solution, a CH3COOH solution, combinations thereof, or other suitable solution. Although the etch stop layer141is acid resistant against the wet etching agent, however, an upper portion of the etch stop layer141may be still etched away during the wet etch. The etched away portion of the etch stop layer141has a thickness of d2as better illustrated inFIG. 2AtoFIG. 2C, inFIG. 11, a portion of the etch stop layer141may be removed through a non-chemical etch procedure, such as a dry etch, to at least expose the lower coil segment132again.

Next, as illustrated inFIG. 12, a fourth passivation layer140is formed over the magnetic core142and the third passivation layer130. The fourth passivation layer140may be comprised of the same material as the first passivation layer110and may be formed by CVD, PVD, or any other suitable processes of formation, in some embodiments. Alternatively, the fourth passivation layer140may include other suitable materials different from the dielectric materials in the first passivation layer110. The third passivation layer112may have a thickness between about 5 μm and about 10 μm, however, other ranges of thickness are also possible, depending on the designs and requirements of the semiconductor device100.

After the fourth passivation layer140is formed, the vias152may be formed, e.g., by forming openings for the vias152through the fourth passivation layer140using, e.g., a lithography and etching process. The vias152may be formed adjacent to opposing sidewalls of the magnetic core142. After the openings for vias152have been formed, the vias152may be formed using a seed layer (not shown) and a plating process, such as electrochemical plating, although other processes of formation, such as sputtering, evaporation, or PECVD process, may alternatively be used depending upon the desired materials. Once the openings for vias152have been filled with conductive material such as copper, any excess conductive material outside of the openings for vias152may be removed, and the vias152and the fourth passivation layer140may be planarized using, for example, a CMP process.

Next, referring toFIG. 13, the upper coil segment162is formed over the fourth passivation layer140. In some embodiments, the upper coil segment162is made of copper. In one embodiment, the upper coil segment162has a thickness in a range between about 10 um and about 15 um, such as about 12 um. Other dimensions are possible and may depend on, for example, the functional requirements for the integrated inductors168and process technologies.

Next, a fifth passivation layer160may be formed over the fourth passivation layer140and the upper coil segment162. The fifth passivation layer160may be comprised of the same material as the first passivation layer110and may be formed by CVD, PVD, or any other suitable processes of formation, in some embodiments. Alternatively, the fifth passivation layer160may include other suitable materials different from the dielectric materials in the first passivation layer110. The thickness of the fifth passivation layer160may be larger than the thickness of the upper coil segment162so that upper coil segment162is encapsulated in the sixth passivation layer160and protected from outside environment, in some embodiments, one or more passivation layers may be formed over the fifth passivation layer160. Referring back toFIG. 1, conductive terminals such as solder balls172can be formed over the fifth passivation layer160in order to make external connection to a voltage source.

Some embodiments of the present disclosure provide a semiconductor structure, including: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; a magnetic layer in the second passivation layer; and an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide.

Some embodiments of the present disclosure provide a semiconductor structure, including: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; a third passivation layer over the second passivation; a lower coil segment in the first passivation layer; an upper coil segment in the third passivation layer; a magnetic core in the second passivation layer and insulated from the lower coil segment and the upper coil segment, wherein the magnetic core includes an upper surface and a lower surface opposite to the upper surface; an acid resistant layer around the lower surface of the magnetic core, the acid resistant layer including a central portion and an edge portion, the edge portion laterally extruding from the central portion, and the edge portion having an upper surface lower than an upper surface of the central portion.

Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including: providing a semiconductor substrate; forming a lower coil segment over the semiconductor substrate; forming a passivation layer over the semiconductor substrate and the lower coil segment; removing an upper portion of the passivation layer to expose an upper surface of the lower coil segment; blanket depositing a stress buffer layer over the passivation layer and the lower coil segment; performing an oxygen treatment upon the stress buffer layer to obtain an acid resistant layer; and blanket depositing a magnetic material over the acid resistant layer.