Local clock injection and independent capture for circuit test of multiple cores in clock mesh architecture

A circuit comprises a burst clock control and gating device configured to generate a modified clock signal in a test mode by allowing a preset number of clock pulses of a clock signal to go through during each clock cycle of a reference clock signal, and a plurality of clock gating devices. Each of the plurality of clock gating devices comprises a multiplexing device, wherein the modified clock signal is coupled to a selector input of the multiplexing device, and input signal generation circuitry configured to ensure the timing of the transitions on the output are derived purely from the timing of the transitions of the clock and not by the timing of the transition of the first and second inputs of the multiplexer.

FIELD OF THE DISCLOSED TECHNIQUES

The presently disclosed techniques relates to clock control and generation for scan test. Various implementations of the disclosed techniques may be particularly useful for independently testing multiple cores of a circuit in clock mesh architecture.

BACKGROUND OF THE DISCLOSED TECHNIQUES

An integrated circuit often takes multiple steps to perform a function and uses an electrical signal known as a “system clock” to pace how quickly each of these steps is performed. The higher the frequency of the system clock pulses, the faster the integrated circuit will operate. A clock (also referred to as “a clock signal”) has a period that specifies the duration of a repeated high and low pattern. The period is inversely related to the clock frequency. The duty cycle of the clock is the ratio of high to low time in the period, usually 50%.

An integrated circuit can have multiple system clocks for simultaneously performing multiple tasks. Different system clocks can control different portions or regions of an integrated circuit. Such regions are referred to as clock domains. As integrated circuits grow to include billions of transitions, it is virtually impossible to design them flat (with no partitioning). Electronic Design Automation (EDA) tools would not be able to process them efficiently. Additionally, there is significant reuse of Intellectual Property (IP) from one design to another. Large designs, known as Systems-On-A-Chip (SOCs), include a large number of “cores” that are used as building blocks (also referred to circuit blocks). Each core can have one or more clock domains.

Circuit defects are unavoidable no matter whether the manufacturing process is at the prototype stage or the high-volume manufacturing stage. It is thus necessary to test chips during the manufacturing process. Structural testing attempts to ascertain that the circuit-under-test has been assembled correctly from some low-level building blocks as specified in a structural netlist and that these low-level building blocks and their wiring connections have been manufactured without defect. Scan testing is the most common technique of structural testing. Under this technique, a series of known values (test stimuli or test pattern) are shifted-in (or loaded into) state elements called scan cells through their sequential inputs. These scan cells are interconnected into scan chains for scan testing. The shifting-in occurs by placing the integrated circuit in a special mode, known as shift mode, and then applying a series of clock pulses, called “shift pulses” or “shift clock pulses.” Each shift clock pulse pushes a bit of test stimuli into a scan cell in each of the scan chains. This continues until all scan cells in the scan chains are filled with test pattern bits.

Then, one or more clock pulses, called “capture pulses” or “capture clock pulses,” are applied to the circuit as they would be in normal operation. This is referred to as capture mode. After the test pattern bits are injected into the circuit, the results of the test (test responses) are “captured” and stored in the scan cells. The circuit then returns to shift mode, and with each additional clock pulse, a bit of the test responses is pushed or shifted out as each bit of new test pattern is pushed or shifted in. The shifted out test responses are then compared with expected results to determine and locate any errors. Shift mode and capture mode together may be called as test mode.

Shift clock pulses and capture clock pulses can be derived from a system clock signal. To reduce power dissipation, the frequency of shift clock pulses is often kept lower than the system clock signal, for example, a frequency between 20 MHz and 100 MHz vs. several GHz. If a circuit block under test has a single clock entry point for a system clock using clock tree technology, on-chip clock control circuitry for deriving shift clock pulses and capture clock pulses from the system clock can be inserted at the clock entry point. At advanced technology nodes, the manufacturing process exhibits multiple sources of on-chip variations effects. Clock mesh technology provides uniform, low skew clock distribution and offers better tolerance to on-chip variations than clock tree technology. In clock mesh technology, each circuit block can have hundreds or even thousands of balanced clock entry points. Shift clock pulses and capture clock pulses need be generated at the base of the clock mesh if conventional technology is employed. This arrangement, however, prevents multiple cores receiving the same system clock signal from being tested independently. Further, each of the multiple cores may have multiple clock domains driven by different system clocks. These system clocks are often asynchronous. It is thus challenging to inject scan test clocks locally for independently testing multiple cores in clock mesh architecture.

BRIEF SUMMARY OF THE DISCLOSED TECHNIQUES

Various aspects of the disclosed technology relate to local clock injection for independent testing of multiple circuit blocks in clock mesh architecture. In one aspect, there is a circuit, comprising: a burst clock control and gating device configured to generate a modified clock signal in a test mode by allowing a preset number of clock pulses of a clock signal to go through during each clock cycle of a reference clock signal; and a plurality of clock gating devices, each of the plurality of clock gating devices comprising: a multiplexing device, wherein the modified clock signal is coupled to a selector input of the multiplexing device, and input signal generation circuitry configured to generate, and to send to inputs of the multiplexing device, a first input signal which does not change when the selector input is at “0” and a second input signal which does not change when the selector input is at “1”, wherein the multiplexing device selects the first input signal to send to an output of the multiplexing device when the selector input is at “0” and selects the second input signal to send to the output of the multiplexing device outputted when the selector input is at “1”.

The circuit may further comprise: a second burst clock control and gating device configured to generate a second modified clock signal in the test mode by allowing a second preset number of clock pulses of a second clock signal to go through during each clock cycle of the reference clock signal, the second clock signal having a clock frequency different from the clock signal; and a second plurality of clock gating devices, wherein the second modified clock signal is coupled to a selector input of a multiplexing device in each of the second plurality of clock gating devices. The reference clock signal may be a bus clock signal for a data bus which transports test data in the test mode or is obtained by dividing frequency of the clock signal or the second clock signal.

The preset number of clock pulses of the clock signal may be a largest even integer of clock pulses of the clock signal fitting in one clock cycle of the reference clock signal.

The input signal generation circuitry may receive a shift clock enable signal and a capture clock enable signal and generate the first input signal and the second input signal based at least in part on the shift clock enable signal and the capture clock enable signal, and the output of the multiplexing device may comprise clock pulses for scan shift and for scan capture corresponding to the shift clock enable signal and the capture clock enable signal, respectively.

The input signal generation circuitry may comprise logic gates and latches which generate the first input signal and the second input signal based on a third signal and a fourth signal, and wherein the output of the multiplexing follows the clock signal when the third signal is at “1” and the fourth signal is at either “0” or “1”, is at “0” when both the third signal and the fourth signal are at “0”, and is at “1” when the third signal is at “0” and the fourth signal are at “1”. The each of the plurality of clock gating devices may further comprise a device configured to generate the third signal and the fourth signal based on scan clock control signals, the scan clock control signals comprising a shift clock enable signal and a capture clock enable signal. Alternatively, the circuit may further comprise a device configured to generate the third signal and the fourth signal based on scan clock control signals, the scan clock control signals comprising a shift clock enable signal and a capture clock enable signal.

The circuit may further comprise a plurality of circuit blocks, and clock mesh circuitry configured to provide the clock signal or the modified clock signal to each of the plurality of circuit blocks through a plurality of clock entry points, wherein each of the plurality of clock entry points is coupled to one of the plurality of clock gating devices.

In another aspect, there are one or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising: creating the above circuit in a circuit design for testing a chip fabricated according to the circuit design.

DETAILED DESCRIPTION OF THE DISCLOSED TECHNIQUES

Various aspects of the disclosed technology relate to local clock injection for independent testing of multiple circuit blocks in clock mesh architecture. In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the disclosed technology.

Some of the techniques described herein can be implemented in software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of both. Some of the disclosed techniques, for example, can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on networked computers.

Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the disclosed flow charts and block diagrams typically do not show the various ways in which particular methods can be used in conjunction with other methods.

The detailed description of a method or a device sometimes uses terms like “couple” and “generate” to describe the disclosed method or the device function/structure. Such terms are high-level descriptions. The actual operations or functions/structures that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

Additionally, as used herein, the term “design” is intended to encompass data describing an entire integrated circuit device. This term also is intended to encompass a smaller group of data describing one or more components of an entire device such as a portion of an integrated circuit device nevertheless.

FIG. 1illustrates an example of a circuit100configured to generate scan test clock signals for testing cores independently in clock mesh architecture according to various embodiments of the disclosed technology. The circuit100comprises two circuit blocks (cores)140and145. Two system clock signals150and155enter each of the circuit blocks140and145through multiple clock entry points130. At each of the clock entry points130, one of clock gating devices120is inserted. At bases of the clock meshes, burst clock control and gating devices110and115are inserted for the clock signals150and155, respectively. As will be described in detail below, the burst clock control and gating device110is configured to generate a modified clock signal from the clock signal150in a test mode by allowing a first preset number of clock pulses of the clock signal150to go through during each clock cycle of a reference clock signal. Similarly, the burst clock control and gating device115is configured to generate a modified clock signal from the clock signal155in a test mode by allowing a second preset number of clock pulses of the clock signal155to go through during each clock cycle of the same reference clock signal. As also will be described in detail below, each of the clock gating devices120receives the modified clock signal from either the burst clock control and gating device110or the burst clock control and gating device115and can use it to generate scan clock signals.

In a test in which test data are delivered by a tester through a data bus, the reference clock signal used by the burst clock control and gating devices110and115can be the clock signal driving the data bus or derived from it. In a test in which logic built-in self-test is used, the reference clock signal can be derived by dividing the clock frequency of one of the system clock signals by a number. For example, if the clock signal150has a frequency of 1.8 GHz and the clock signal155has a frequency of 812 MHz, the reference lock signal can be obtained by dividing the frequency of the clock signal155by 4. In this situation, the burst clock control and gating device115is not needed for the clock signal155.

The two clock signals150and155are often asynchronous, independent high-speed clocks. Thus, they do not run in lockstep, which is problematic for testing a circuit block having two or more clock domains. Even if one is a multiple of the other, a small deviation (e.g., a few parts per million) can cause drifting of one clock signal with respect to the other. By allowing, per reference clock cycle, a fixed number of clock pulses for each of the clock signals150and155to go through, the burst clock control and gating devices110and115effectively generate the two modified clock signals operating in lockstep. As a result, the two clock domains can share a single data bus interface device or a single logic BIST controller (which operates on one of the clock domains) for scan data delivery.

FIG. 2illustrates an example of waveforms for a reference clock signal210, two system clock signals220and230, and corresponding modified clock signals225and235generated by the burst clock control and gating devices110and115, respectively. In this example, the frequencies and the corresponding clock periods (in brackets) of the reference clock signal210and the two system clock signals220and230are 200 MHz (5 ns), 1.8 GHz (555 ps) and 812 MHz (1.23 ns), respectively. With some implementations of the disclosed technology, the preset number of clock pulses allowed to go through the corresponding burst clock control and gating device is chosen to be the largest even integer fitting in one reference clock period. In the above example, the preset numbers of clock pulses are eight clock pulses for the clock signal220and four clock pulses for the clock signal230. Because one reference clock cycle can hold nine clock pulses plus a small fraction of a tenth for the clock signal220, one or two in every nine or ten clock pulses of the modified clock signal225are gated off, as illustrated inFIG. 2. On the other hand, four clock periods of the clock signal230is nearly as long as one reference clock cycle, and thus one original clock pulse is gated off every sixty-four clock pulses (5/(5−1.232×4)=64). InFIG. 2, the modified clock signal235shows that only one pulse at a position240is gated off due to the limited width of the window.

FIG. 3illustrates an example of a block diagram of a burst clock control and gating device300according to various embodiments of the disclosed technology. The burst clock control and gating device300comprises a burst clock control device310and a gating device320. The burst clock control device310can use one or more counters to generate a burst clock control signal based on a reference clock signal340and a system clock signal330. The gating device320can then use the burst clock control signal to allow a preset number of clock pulses of the system clock signal330to pass through per clock cycle of the reference clock signal340.

FIG. 4illustrates an example of a block diagram of a burst clock control device400and an example of corresponding waveforms405for the burst clock control device400according to various embodiments of the disclosed technology. The burst clock control device400comprises two registers460and470, two state elements440and450, and two counters410and420. The state elements440and450are retiming devices and can detect rising edges of a reference clock signal480. The counter410is used to delay the first pulse in a burst of clock pulses of a system clock signal490with respect to the rising edge of a pulse of the reference clock signal480. The delay is to ensure that the first pulse of a burst of system clock pulses aligns close to the rising edge of a pulse of the reference clock signal480. The counter420is used to count a preset number of clock pulses of a system clock signal490. Under this arrangement, every burst of system clock pulses (the preset number of consecutive clock pulses of the system clock signal490) will be confined within one clock period of the reference clock signal480. The registers460and470are used to store preset number of clock pulses of the system clock signal490and the number of clock pulses for delay, respectively.

In the example of the waveforms405, it is assume to take three clock cycles of the system clock signal490to detect a clock edge485of the reference clock signal480. The preset number of the system clock signal490to be allowed to pass through the burst clock control device400is eight. Then the number of clock pulses for delay can be set as five. As such, the first clock pulse486of the first clock burst is close to the next clock edge487of the reference clock signal480. After eight system clock pulses, the ninth one is gated off by a gating device430. By repeating this process, a modified system clock signal495having eight pulses per clock cycle of the reference clock signal480is generated.

FIG. 5illustrates an example of a block diagram for a clock gating device500according to various embodiments of the disclosed technology. The clock gating device500comprises a multiplexing device520and circuitry for generating multiplexer input signals530. The multiplexing device520is a device that selects between signals at two inputs (a first input522and a second input525) based on a signal at a selector input527, and forwards it to an output529. The multiplexing device520can be implemented with a conventional multiplexer. In contrast to conventional uses of a multiplexer, however, the selector input527of the multiplexing device520is coupled to a clock signal510. The clock signal510can to be gated to generate capture pulses or used to generate slow shift clock pulses. The clock gating device500may be used to implement the clock gating devices120shown inFIG. 1, and the clock signal510can be a modified system clock signal generated by either the burst clock control and gating device110or the burst clock control and gating device115depending on the clock domains.

FIG. 5also illustrates a truth table540describing how the multiplexing device520operates. When the two inputs522and525are kept at different logic values, either “1” for one and “0” for the other or the opposite, the output529either follows the clock signal510or sends out an inverse copy of the clock signal510. When both of the inputs522and525are kept at “0”, the output529is also kept at “0” and thus the clock signal510is gated off or disabled. When both of the inputs522and525are kept at “1”, the output529is also kept at “1”. By keeping the inputs522and525alternatively at “1” for a number of clock periods of the clock signal510and at “0” for the same number of clock periods of the clock signal510, the multiplexing device520can output clock pulses which are slower than the clock signal510and have a duty cycle about 50%.

The ability to generate a slow clock with a 50% duty cycle is particularly useful for scan test because both rising and falling edges of a clock pulse are often used for scan shift. A conventional clock gater can generate slow clock pulses from a fast system clock signal, but the duty cycle can be very low. For example, an AND gate-based clock gater allows original clock pulses (1 GHz) to pass through once every 20 clock pulses. The resulted output clock signal is at 50 MHz, twenty times slower than the original one. While this is a typical frequency for scan shift, the duty cycle is only about 2.6%, which can cause timing problems for scan shift. A similar result will be obtained if the multiplexing device520is used as a conventional clock gating device with the clock signal510coupled to one of its two inputs.

The circuitry for generating multiplexer input signals530is configured to generate a first input signal and a second input signal and to send them to the first input522and second input525of the multiplexing device520, respectively. The first input signal does not change when the selector input527is at “0” and the second input signal does not change when the selector input527is at “1”. This makes sure that the transitions on the output529are timed from the transitions on the clock signal510.

FIG. 6illustrates an example of a block diagram for circuitry for generating multiplexer input signals630according to various embodiments of the disclosed technology. The circuitry for generating multiplexer input signals630comprises a device610. The device610comprises latches611,612and613, an AND gate614, and an OR gate615. A clock signal640is coupled to a selector input of a multiplexer620and also drives enable/clock inputs of the latches611,612and613. Here, the latches611and613updates their outputs only when the clock signal640is at “0” while the latch612changes its state only when the clock signal640is at “1”. This arrangement helps ensure that the first input623does not change when the clock signal640is at “0” and the second input625does not change when the clock signal640is at “1”.

When a CE input616of the device610is set at “1”, the first and second inputs623,625of the multiplexer620will be set at “0” and “1”, respectively, regardless of whether a DE input617is at either “0” or “1”. As such, an output650of the multiplexer620will follow the clock signal640. When both of the CE input616and the DE input617are set at “0”, both of the first input623and the second input625are also set at “0” and thus the output650will be “0”. When the CE input616is at “0” and the DE input617is at “1”, both of the first input623and the second input625are set at “1” and thus the output650will be at “1”. The above is summarized in a truth table660.

FIG. 7illustrates an example of waveforms for signals of the clock gating device shown inFIG. 6. Specifically, waveforms for a clock signal710and signals at the CE input711, the DE input712, the first input714, the second input713, and the output715are displayed. In the figure, the second input713changes only when the clock signal710is at “0”, and the first input714changes only when the clock signal710is at “1”. In region720, the output715follows the clock signal710because the CE input711is at “1”. Two pulses of the clock signal710is thus allowed to pass through the multiplexer620. In region730, the output715is at “0” because both the CE input711and the DE input712are at “0”. As such, the clock signal710is gated off during this period. In region740, the output715is at “1” for about three clock pulses of the clock signal710because the CE input711is at “0” and the DE input712is at “1”. The output715then returns to “0”. If it the output715is kept at “0” for three clock period of the clock signal710before changes back to “1” and this pattern of alternating between “1” and “0” every three clock periods repeats itself, a slow clock pulses (one third of the frequency of the clock710) with 50% duty cycle will be generated. These slow clock pulses can be used as scan shift clock pulses. The “at-speed” clock pulses such as the two clock pulses in the region720can be used as scan capture clock pulses.

A person of ordinary skill in the art would appreciate that the device610shown inFIG. 6is just an example, and that a different device may be used to generate signals for the two inputs of the multiplexing device according to various embodiments of the disclosed technology.

FIG. 8illustrates an example of a block diagram for a clock gating device800which can generate clock pulses for scan shift and scan capture based on scan clock control signals according to various embodiments of the disclosed technology. Like the clock gating device500shown inFIG. 5, the clock gating device800comprises a multiplexing device830and circuitry for generating multiplexer input signals850. Unlike the circuitry for generating multiplexer input signals630inFIG. 6, the circuitry for generating multiplexer input signals850is shown to comprise not only a device820but also circuitry for generating CE/DE signals860. The device820generates signals for a first input832and a second input835of the multiplexing device830based on CE and DE signals received at a CE input826and a DE input827, respectively. An example of the device820is the device610shown inFIG. 6. A clock signal801is coupled to a selector input837of the multiplexing device830, and also drives the device820.

The circuitry for generating CE/DE signals860comprises a counter device840, an injector device810and a gating device870. It generates the CE and DE signals based on a shift clock enable signal803and a capture clock enable signal804. The shift clock enable signal803and the capture clock enable signal804may be generated by a test controller such as a logic BIST (built-in self-test) controller or a data bus interface device for the circuit block of interest. Here, the data bus delivers scan data to each of circuit blocks (cores) in the circuit under test.

The counter device840is driven by the clock signal801and generates clock pulses based on preset shift pulse count initial & maximum numbers and capture pulse count initial & maximum numbers802. The gating device870uses these clock pulses to gate the shift clock enable signal803and the capture clock enable signal804. The injector810then generates the CE and DE signals based on the output of the gating device870. It should be noted that additional clock control signals such as a test compression clock enable signal for a test compression controller may be supplied to the gating device870. The clock gating device800can generate clock pulses for the test compression controller based on the test compression clock enable signal. The circuitry for generating CE/DE signals860allows the scan clock control signals such as the shift clock enable signal803and the capture clock enable signal804to be transported through multicycle paths rather than through pipeline paths.

FIG. 9illustrates another example of a block diagram for a clock gating device900which can generate clock pulses for scan shift and capture, for test compression controllers, and for a data bus interface device for a circuit block according to various embodiments of the disclosed technology. Like the clock gating device800inFIG. 8, the clock gating device900comprises a multiplexing device910, a device for generating multiplexer input signals920, and circuitry for generating CE/DE signals930. Unlike the circuitry for generating CE/DE signals860inFIG. 8, the circuitry for generating CE/DE signals930is shown to have at least three rather than one counter devices: a three-bit stage-1 counter device940, a three-bit burst counter device950and a four-bit counter device960. The three-bit stage-1 counter device940is used to divide the frequency of a clock signal905to generate a slow clock signal for the data bus interface device. The clock signal905can be derived from a system clock signal by a burst clock control and gating device such as the burst clock control and gating device400shown inFIG. 4. If the clock signal905has eight pulses within one clock cycle of the reference clock signal (about 1.6 GHz), for example, the clock signal905can be divided by 4 to obtain a 400 MHz clock signal for the data bus interface device. Here, the data bus interface device is designed to operate at two times the frequency of the reference clock signal for the data bus.

The four-bit counter device960and the three-bit stage-1 counter device940work together to produce a signal with a frequency needed for scan shift, for example, 80 MHz. The obtained signal is use to gate a shift clock enable signal to produce pulses for an injector device970. The injector device970can use them to produce a DE signal needed for producing slow scan shift clock pulses with duty cycle close to 50%. The three-bit burst counter device950is used to ensure at-speed capture pulses to be generated close to the start of a burst of pulses of the modified clock signal905.

FIG. 10illustrates an example of a circuit block1000comprising two clock domains, clock gating devices, and burst clock control and gating devices according to various embodiments of the disclosed technology. Two clock signals1010and1015for the two clock domains enters the circuit block1000in clock mesh architecture. Two burst clock control and gating devices1020and1025are inserted at the bases of the clock signals1010and1015, respectively, to convert them into modified clock signals with fixed numbers of clock pulses per clock cycle of a reference clock signal (not shown) in the test mode. Two groups of clock gating devices1030and1035are configured in the test mode (“00”) to drive functional circuits and scan chains in the two clock domains, respectively. A third group of clock gating devices1040are configured in the test mode (“01”) to drive one or more test compression controllers1045used in the circuit block1000. A fourth group of clock gating devices1050are configured in the test mode (“10”) to drive a data bus interface device1055for the circuit block1000. These clock gating devices1030,1035,1040and1050can be implemented using the clock gating device900inFIG. 9. The burst clock control and gating devices1020and1025can be implemented using the burst clock control device400along with the gating device430inFIG. 4. The data bus interface device1055can be configured to generate three multi-cycle path signals (scan shift clock enable, scan capture clock enable, and test compression controller clock enable) for the clock gating devices1030,1035, and1040. The static configuration signals for these clock gating devices1030,1035,1040and1050can be delivered through an IJTAG network1060.

FIG. 11illustrates an example of a clock gating device1100having smaller footprint than the clock gating device900inFIG. 9according to various embodiments of the disclosed technology. The clock gating device1100comprises a multiplexing device1130, a device1110for generating input signals for the multiplexing device1130, and two AND gates1120and1140. The device1110is shown to have the same topology as the device610shown inFIG. 6. It should be noted, however, that a device different from the device610may be employed here as long as it can follow the truth table660shown inFIG. 6and ensure that the first input signal1133does not change when the selector input of the multiplexing device1130is at “0” and that the second input signal1135does not change when the selector input of the multiplexing device1130is at “1”.

Unlike the clock gating device900, the clock gating device1100does not have a device similar to the circuitry for generating CE/DE signals960. Instead, the CE and DE signals for the device1110are delivered through a single pipeline path, referred to as a CE and DE pipelined signal1102in the figure. This is feasible because the CE and DE signals do not need to be changed in the same time. A CE/DE selection MCP signal1104is used to decouple the CE and DE signals from the CE and DE pipelined signal1102using the two AND gates1120and1140. As the name suggests, the CE/DE selection MCP signal1104can be send through a multicycle path. This architecture reduces pipeline devices needed.

FIG. 12illustrates an example of a circuit block1200comprising two clock domains, clock gating devices, burst clock control and gating devices, and circuitry for generating CE/DE signals in each of the two clock domain according to various embodiments of the disclosed technology. Two clock signals1210and1215for the two clock domains enters the circuit block1200in clock mesh architecture. Two burst clock control and gating devices1220and1225are inserted at the bases of the clock signals1210and1215, respectively, to convert them into modified clock signals with fixed numbers of clock pulses per clock cycle of a reference clock signal (not shown) in the test mode. Two groups of clock gating devices1230and1235are configured in the test mode to drive functional circuits and scan chains in the two clock domains, respectively. A third group of clock gating devices1240are configured in the test mode to drive one or more test compression controllers1245used in the circuit block1000. A fourth group of clock gating devices1250are configured in the test mode to drive a data bus interface device1255for the circuit block1200. These clock gating devices1230,1235,1240and1250can be implemented using the clock gating device1100inFIG. 11. The burst clock control and gating devices1220and1225can be implemented using the burst clock control and gating device shown inFIG. 4. The data bus interface device1255can be configured to generate multi-cycle path signals including scan shift clock enable, scan capture clock enable, and test compression controller clock enable for circuitry for generating CE/DE signals1260in one clock domain for the clock signal1210and for circuitry for generating CE/DE signals1265in the other clock domain for the clock signal1215. The circuitry for generating CE/DE signals1260and1265can be implemented by the circuitry for generating CE/DE signals930inFIG. 9along with a circuit that can combines the CE and DE signals into a single CE/DE signal and also can generate another decoupling signal to be used for decoupling the signal CE/DE signal. The single CE/DE signal is transmitted through a pipeline path while the decoupling signal can be transmitted through a multi-cycle path (MCP). These two signals are used by the clock gating devices1230,1235,1240and1250.

Various examples of the disclosed technology may be implemented through the execution of software instructions by a computing device, such as a programmable computer. Accordingly,FIG. 13shows an illustrative example of a computing device1301. As seen in this figure, the computing device1301includes a computing unit1303with a processing unit1305and a system memory1307. The processing unit1305may be any type of programmable electronic device for executing software instructions, but it will conventionally be a microprocessor. The system memory1307may include both a read-only memory (ROM)1309and a random access memory (RAM)1311. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM)1309and the random access memory (RAM)1311may store software instructions for execution by the processing unit1305.

The processing unit1305and the system memory1307are connected, either directly or indirectly, through a bus1313or alternate communication structure, to one or more peripheral devices. For example, the processing unit1305or the system memory1307may be directly or indirectly connected to one or more additional memory storage devices, such as a “hard” magnetic disk drive1315, a removable magnetic disk drive1317, an optical disk drive1319, or a flash memory card1321. The processing unit1305and the system memory1307also may be directly or indirectly connected to one or more input devices1323and one or more output devices1325. The input devices1323may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices1325may include, for example, a monitor display, a printer and speakers. With various examples of the computer1301, one or more of the peripheral devices1315-1325may be internally housed with the computing unit1303. Alternately, one or more of the peripheral devices1315-1325may be external to the housing for the computing unit1303and connected to the bus1313through, for example, a Universal Serial Bus (USB) connection.

With some implementations, the computing unit1303may be directly or indirectly connected to one or more network interfaces1327for communicating with other devices making up a network. The network interface1327translates data and control signals from the computing unit1303into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the interface1327may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

It should be appreciated that the computer1301is illustrated as an example only, and it is not intended to be limiting. Various embodiments of the disclosed technology may be implemented using one or more computing devices that include the components of the computer1301illustrated inFIG. 13, which include only a subset of the components illustrated inFIG. 13, or which include an alternate combination of components, including components that are not shown inFIG. 13. For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, a plurality of single and/or multiprocessor computers arranged into a network, or some combination of both.

Conclusion

Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments to which the principles of the disclosed technologies can be applied, it should be recognized that the illustrated embodiments are only preferred examples of the technologies and should not be taken as limiting the scope of the disclosed technology. Rather, the scope of the disclosed technology is defined by the following claims and their equivalents. We therefore claim as our disclosed technology all that comes within the scope and spirit of these claims.