Semiconductor integrated circuit

A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which samples the test data and extracts recovery data, and a detector which detects an error of the recovery data.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2007-065518, filed Mar. 14, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit including a data extractor for extracting recovery data from external input data and, more particularly, to a semiconductor integrated circuit including a test circuit for testing the data extractor.

2. Description of the Related Art

When transferring high-speed data exceeding 1 Gbit/sec, “the characteristics of transmitting and receiving circuits or the characteristics of transmission lines including connecting tools connected to transmitting and receiving terminals” cause delay or reflection of pulses, or mutual interference between signal pulses and reflected pulses. Even when the transmitting side simultaneously transmits transmission data and a transmission clock, therefore, a difference (skew) is produced between the times of arrival of reception data and a reception clock on the receiving side. This makes it difficult to discriminate the contents of the reception data on the receiving side.

Accordingly, in high-speed serial transfer that transfers serial data at a high speed, for example, a receiving-side apparatus that receives serial data uses a clock and data recovery (CDR) circuit. The CDR circuit detects the phase of the input serial data, and generates a recovery clock phase-locked with the serial data. The CDR circuit then outputs retiming data obtained by sampling the serial data in synchronism with this recovery clock.

Conventionally, the jitter resistance of the CDR circuit incorporated into a large-scale integrated circuit (LSI) is measured as follows. A receiver receives a modulated signal obtained by modulating, by a modulator, a high-frequency, pseudo-random bit sequence (PRBS) signal generated by an external PRBS generator, and the CDR circuit extracts recovery data from the modulated signal. A PRBS detector checks matching of the extracted recovery data. If the recovery data does not match, the PRBS detector outputs an error flag. The external PRBS generator and the internal PRBS detector of the LSI are preset to have the same code sequence.

To measure the jitter resistance by generating data exceeding the GHz band outside an LSI, however, expensive apparatuses are necessary, and a new installation cost is required in mass-production.

A communication apparatus capable of testing the jitter resistance of a receiver is disclosed as a related technique of this kind (Jpn. Pat. Appln. KOKAI Publication No. 2006-25114).

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a clock generator which generates a first clock; a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock; a data extractor which samples the test data and extracts recovery data; and a detector which detects an error of the recovery data.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a clock generator which generates a first clock; a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock; a data extractor which samples the test data and extracts recovery data; and a detector which detects an error of the recovery data. The test data generator includes: a phase interpolator which generates a second clock by modulating the phase of the first clock; and a generator which generates the test data by adding jitter to a bit sequence by using the second clock.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a clock generator which generates a first clock; a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock; a data extractor which samples the test data and extracts recovery data; and a detector which detects an error of the recovery data. The data extractor includes: a phase interpolator which generates a recovery clock by modulating the phase of the first clock; and a sampling circuit which samples the test data on edges of the recovery clock.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention will be explained below with reference to the accompanying drawing. Note that in the following explanation, the same reference numerals denote elements having the same functions and arrangements, and a repetitive explanation will be made only when necessary.

FIG. 1is a block diagram illustrating the arrangement of a semiconductor integrated circuit (LSI)10according to the embodiment of the present invention. The LSI10comprises a receiver11, selector (SEL)12, phase locked loop (PLL) circuit13, data extractor (CDR circuit)14, test data generator15, and PRBS data detector (PRBS_DET)16. The LSI10is fabricated as a chip in which these circuits are mounted on the same substrate.

A reference clock R_CLK is input to the PLL circuit (clock generator)13. The frequency of the reference clock R_CLK is set to an integral fraction of the reception data rate. The reference clock R_CLK can be input from an external circuit to the PLL circuit13, or from an oscillator included in the LSI10to the PLL circuit13.

The PLL circuit13generates internal clocks (ICK, QCK, ICKB, and QCKB to be described later) from the reference clock R_CLK. These internal clocks are set at a frequency that is an integral multiple of the frequency of the reference clock R_CLK. This frequency is the same as the reception data rate. For example, when the reception data rate is 1 Gbit/s, the output frequency from the PLL circuit13is 1 GHz. The PLL circuit13makes it possible to generate the internal clocks having stable phases.

The test data generator15generates test data to which jitter (phase noise) is added, by using the internal clocks generated by the PLL circuit13. More specifically, the test data generator15generates pseudo-random bit sequence (PRBS) data, and generates test data by adding jitter to this PRBS data. The test data generator15is also capable of freely changing the amplitude and frequency of jitter to be added to the PRBS data. A practical arrangement of the test data generator15will be described later. The test data generated by the test data generator15is input to the first input terminal of the selector12.

The selector12receives, at the second input terminal, input data that is a differential signal input from the external circuit to the LSI10via the receiver11. The selector12selects one of the test data input to the first input terminal, and the input data input to the second input terminal. A test selection signal TS input from the external circuit controls this selecting operation. More specifically, on the basis of the test selection signal TS, the selector12selects the test data when conducting a jitter resistance test on the CDR circuit14, or the input data in a normal operation except for the test.

The CDR circuit14detects the phase of the input data (or test data) input from the selector12, and generates a recovery clock phase-locked with the input data. In addition, the CDR circuit14outputs, as recovery data, retiming data obtained by sampling the input data in synchronism with the phase of the recovery clock.

The output recovery data from the CDR circuit14is output to the external circuit, and input to the PRBS data detector (PRBS_DET)16. During the test, the PRBS data detector16detects whether the recovery data matches the PRBS data generated by the test data generator15. “A PRBS data generator55included in the test data generator15” and the PRBS data detector16are preset to have the same code sequence. If the data comparison result indicates that the two data do not match, the PRBS data detector16outputs an error flag to the external circuit.

FIG. 2is a block diagram illustrating an example of the CDR circuit14. The CDR circuit14comprises a sampling circuit21, phase comparator22, loop filter (low-pass filter [LPF])23, current output digital-to-analog converter (IDAC)24, and phase interpolator25.

The phase comparator22compares the phase of the input data with that of the recovery clock supplied from the phase interpolator25. The phase comparator22outputs an UP signal if the phase of the recovery clock lags behind that of the input data, and a DOWN signal if the phase of the recovery clock leads that of the input data.

The LPF23removes (integrates) the high-frequency component from a pulse-like phase difference signal output from the phase comparator22, and inputs the signal to the IDAC24. The IDAC24converts the phase difference signal input from the LPF23into a current value.

The phase interpolator25receives the internal clocks ICK, ICKB, QCK, and QCKB from the PLL circuit13, in addition to the current value from the IDAC24. The phase interpolator25adjusts the phases of the internal clocks by using the phase difference signal from the IDAC24, thereby generating a recovery clock phased with the input data. This recovery clock is fed back to the phase comparator22, and input to the sampling circuit21.

The input data is input to the sampling circuit21. The sampling circuit21samples and holds the input data on the leading edge of the recovery clock. Finally, the sampling circuit21outputs, as recovery data, retiming data sampled on the leading edge of the recovery clock phased with the input data.

FIG. 3is a view illustrating the timing at which the sampling circuit21samples the input data. UI shown inFIG. 3indicates a minimum width (unit interval) of data. The sampling circuit21performs sampling intermediate between input data transition regions. Therefore, if the leading edge of the recovery clock output from the phase interpolator25exists in the input data transition region, the phase comparator22outputs a phase difference signal for adjusting the phase amount of the recovery clock.

This phase difference signal is input to the phase interpolator25via the LPF23for removing the high-frequency component and the IDAC24for adjusting the current value. The phase interpolator25adjusts the phases of the internal clocks from the PLL circuit13in accordance with the controlled current value from the IDAC24. Finally, this feedback control allows the sampling circuit21to sample the phase relationship between the input data and recovery clock intermediate between the data transition regions.

FIG. 4is a circuit diagram illustrating an example of the phase interpolator25shown inFIG. 2.FIG. 5is a timing chart illustrating the internal clocks ICK, QCK, ICKB, and QCKB supplied from the PLL circuit13to the phase interpolator25. The phases of the internal clocks ICK, QCK, ICKB, and QCKB are shifted 90° from each other in the order named.

The phase interpolator25comprises four differential amplifiers. The phase interpolator25includes two resistors31and32, eight N-channel MOS (NMOS) transistors33to40, and four variable current sources41to44.

More specifically, one terminal of the resistor31is connected to a power supply terminal to which a power supply voltage VDD is supplied. The other terminal of the resistor31is connected to the drains of the NMOS transistors33,35,37, and39. One terminal of the resistor32is connected to the power supply terminal to which the power supply voltage VDD is supplied. The other terminal of the resistor32is connected to the drains of the NMOS transistors34,36,38, and40.

The internal clock ICK is supplied to the gates of the NMOS transistors33and40. The internal clock QCK is supplied to the gates of the NMOS transistors34and35. The internal clock ICKB is supplied to the gates of the NMOS transistors36and37. The internal clock QCKB is supplied to the gates of the NMOS transistors38and39.

The sources of the NMOS transistors33and34are grounded (connected to a ground voltage VSS) via the variable current source41. The sources of the NMOS transistors35and36are grounded via the variable current source42. The sources of the NMOS transistors37and38are grounded via the variable current source43. The sources of the NMOS transistors39and40are grounded via the variable current source44.

The IDAC24supplies a current I1to the control terminal of the variable current source41. The IDAC24supplies a current I2to the control terminal of the variable current source42. The IDAC24supplies a current I3to the control terminal of the variable current source43. The IDAC24supplies a current I4to the control terminal of the variable current source44.

In the phase interpolator25configured as above, the four-phase clocks (ICK, QCK, ICKB, and QCKB) supplied form the PLL circuit13are input to the four differential amplifiers to adjust weighting of each of the variable current sources41to44. Thus, the phase interpolator25can adjust the phase of the recovery clock from 0 to 360°.

FIG. 6is a view illustrating recovery clock phase modulation performed by the phase interpolator25. For example, in clock generation in the first quadrant ofFIG. 6, only I1is adjusted by setting I2=I3=I4=0. In clock generation in the second quadrant ofFIG. 6, only I2is adjusted by setting I1=I3=I4=0. In clock generation in the third quadrant ofFIG. 6, only I3is adjusted by setting I1=I2=I4=0. In clock generation in the fourth quadrant ofFIG. 6, only I4is adjusted by setting I1=I2=I3=0. In this way, with respect to the four-phase clocks (ICK, QCK, ICKB, and QCKB) having phases shifted 90° from each other, the phase of an output OUT changes in accordance with the magnitudes of the currents I1to I4supplied from the IDAC24. Finally, the phase-adjusted recovery clock is output from an output terminal OUT connected to the other terminal of the resistor31, and from an output terminal OUTB connected to the other terminal of the resistor32.

Next, an example of the test data generator15will be explained below.FIG. 7is a block diagram illustrating the arrangement of the test data generator15shown inFIG. 1. The test data generator15comprises a counter51, decoder52, IDAC53, phase interpolator54, and PRBS data generator (PRBS_GEN)55. The IDAC53and phase interpolator54respectively have the same arrangements as those of the IDAC24and phase interpolator25shown inFIG. 2.

The counter51receives a counter clock C_CLK and counter mode switching signal CMS from the external circuit. The counter51counts pulses of the counter clock C_CLK. The counter mode switching signal CMS switches the operation modes (count-up and count-down) of the counter51. That is, the counter51repeats up-count or down-count of a predetermined amount on the basis of the counter mode switching signal CMS.

The decoder52decodes the count of the counter51, and converts the decoded count into a weighting amount to be used in the IDAC53on the output stage. The IDAC53supplies a current magnitude to the phase interpolator54. The phase interpolator54generates a modulated clock by performing phase modulation and frequency modulation on the four-phase clocks (ICK, QCK, ICKB, and QCKB) from the PLL circuit13. This modulated clock is supplied to the PRBS data generator55. The PRBS data generator55generates test data by adding jitter to the PRBS data by using the modulated clock.

In the test data generator15configured as above, the modulation amount of the modulated clock can be adjusted by changing the amount of switching from up-count to down-count by using the signal CMS for switching the operation modes of the counter51. Finally, the phase and frequency of the test data output from the test data generator15can be modulated in synchronism with the counter clock C_CLK.

Examples of the modulated clock generated by the phase interpolator54will be explained below. Assume that the phase adjustment amount of the phase interpolator54is divided by 64, and the count of the counter51ranges from 0 to 63.

FIG. 8shows the first example of the modulated clock generated by the phase interpolator54. That is,FIG. 8is a graph illustrating the modulated clock when the phase adjustment amount is 1 UI.FIG. 9is a view illustrating a phase change of the modulated clock in the first example. Referring toFIG. 8, the ordinate indicates the phase modulation amount of the modulated clock, and the abscissa indicates the count of the counter51.

In the first example, the count increases for every cycle of the counter clock C_CLK, so the phase adjustment amount of the modulated clock generated by the phase interpolator54is 1 UI. Accordingly, the phase interpolator54can change the phase of the modulated clock through 360°. Note that the time (frequency) required for the change of 1 UI can be changed by changing the frequency of the counter clock C_CLK.

FIG. 10shows the second example of the modulated clock. That is,FIG. 10is a graph illustrating the modulated clock when the phase adjustment amount is 0.5 UI.FIG. 11is a view illustrating a phase change of the modulated clock in the second example.

In the second example, the increase/decrease amount of the counter value is set such that the count repetitively increases or decreases from 0 to 31. Since the count increases for every cycle of the counter clock C_CLK, the phase adjustment amount of the modulated clock generated by the phase interpolator54is 0.5 UI. The time (frequency) required for the change of 0.5 UI can be changed by changing the frequency of the counter clock C_CLK.

FIG. 12shows the third example of the modulated clock. That is,FIG. 12is a graph illustrating the modulated clock when the phase adjustment amount is 0.25 UI.FIG. 13is a view illustrating a phase change of the modulated clock in the third example.

In the third example, the increase/decrease amount of the counter value is set such that the count repetitively increases or decreases from 0 to 15. Since the count increases for every cycle of the counter clock C_CLK, the phase adjustment amount of the modulated clock generated by the phase interpolator54is 0.25 UI. The time (frequency) required for the change of 0.25 UI can be changed by changing the frequency of the counter clock C_CLK.

FIG. 14is an eye pattern illustrating the movement of the test data generated by the test data generator15. The use of the test data generator15shown inFIG. 7makes it possible to freely control the intensity (amplitude) and frequency of the jitter of the test data.

FIG. 15is a graph for evaluating the jitter resistance of the LSI10. Referring toFIG. 15, the ordinate indicates the jitter amplitude, and the abscissa indicates the jitter frequency.

As described above, the intensity (amplitude) and frequency of the jitter of the test data can be freely controlled by using the test data generator15of this embodiment. Since this makes it possible to add a desired jitter to the test data without using any measurement apparatus, the jitter resistance can be accurately evaluated.

That is, as shown inFIG. 15, the jitter resistance of the LSI10can be evaluated by using a matrix. Therefore, a chip satisfying the specifications of the jitter resistance can be accurately and easily selected. For example, the boundary between hollow circles (fail) and solid circles (pass) becomes clear in the jitter matrix shown inFIG. 15. This allows accurate selection of a chip capable of recovering data against jitter.

In this embodiment as has been described in detail above, test data having a desired jitter can be generated inside the LSI10. This makes it possible to conduct a jitter resistance test on the LSI10(more specifically, the CDR circuit14) without using any expensive test apparatus. Consequently, defects in the mass-production process of the LSI10can be detected in advance.

It is also possible, by using the internal clocks generated by the PLL circuit13, to generate test data containing jitter and not synchronized with the internal clocks. This embodiment can also freely change the intensity and frequency of the jitter. Accordingly, the jitter resistance test can be accurately conducted.

Furthermore, circuit design is facilitated because the IDAC and phase interpolator identical to those used in the CDR circuit14can also be used in the test data generator15.