High frequency integrated circuit for wireless communication

According to an embodiment, a high frequency integrated circuit includes a signal splitter, an attenuator, a first conductive element, and first to eighth switches. The signal splitter receives a high frequency signal at an input terminal, splits the high frequency signal to two lines, and outputs the signals split into the two lines from a first output terminal and a second output terminal. The attenuator has multiple amounts of attenuation values. In the first conductive element, a first amount of attenuation is set. The high frequency integrated circuit outputs a plurality of output signals having different gain values from the first high frequency output terminal and the second high frequency output terminal, respectively.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2021-018591, filed on Feb. 8, 2021, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein are related to a high frequency integrated circuit.

BACKGROUND

Communication technologies in wireless communication and the like have been undergoing evolution for higher frequency and higher functionality. In particular, in the wireless communication, communication standards have been reviewed in each generation (such as 3G, 4G, 5G, and so on), and adaptation to higher frequency in used bands and modularization have been progressing rapidly.

High frequency integrated circuits used for the wireless communication device have been required to meet various specifications of characteristics for each generation of the communication standards or to deal with two or more such generations. For example, such a high frequency integrated circuit is required to output multiple signals having different gains output from a high frequency output terminal of a receiving block or a transmitting block.

The requirement will not be satisfied by simply adopting a variable gain amplifier, a signal splitter, and the like. In addition, it is also required not to deteriorate insertion loss, isolation, and the like.

DETAILED DESCRIPTION

According to an embodiment, a high frequency integrated circuit includes a signal splitter, an attenuator, a first conductive element, and first to eighth switches. The signal splitter receives a high frequency signal at an input terminal, splits the high frequency signal into two lines, and outputs the signals split into the two lines from a first output terminal and a second output terminal. The attenuator has multiple amount of attenuation. The first conductive element has a first amount of attenuation. The first switch is placed between a first output terminal of the signal splitter and the first conductive element, and selects conductive or non-conductive between the first output terminal of the signal splitter and the first conductive element. The second switch is placed between the first output terminal of the signal splitter and the attenuator, and, selects conductive or non-conductive between the first output terminal of the signal splitter and the attenuator. The third switch is placed between a second output terminal of the signal splitter and the first conductive element, and selects conductive or non-conductive between the second output terminal of the signal splitter and the first conductive element. The fourth switch is placed between the second output terminal of the signal splitter and the attenuator, and selects conductive or non-conductive between the second output terminal of the signal splitter and the attenuator. The fifth switch is placed between the first conductive element and a first high frequency output terminal, and selects conductive or non-conductive between the first conductive element and the first high frequency output terminal. The sixth switch is placed between the first conductive element and a second high frequency output terminal, and selects conductive or non-conductive between the first conductive element and the second high frequency output terminal. The seventh switch is placed between the attenuator and the first high frequency output terminal, and selects conductive or non-conductive between the attenuator and the first high frequency output terminal. The eighth switch is placed between the attenuator and the second high frequency output terminal, and selects conductive or non-conductive between the attenuator and the second high frequency output terminal. The high frequency integrated circuit outputs a plurality of output signals having different power levels from the first high frequency output terminal and the second high frequency output terminal, respectively.

More embodiments will be described below with reference to the drawings. In the drawings, the same reference numerals represent the same or similar portions.

A high frequency integrated circuit according to a first embodiment will be described with reference to the drawings.FIG.1is a circuit diagram illustrating the high frequency integrated circuit.

In the first embodiment, first to fourth switches are arranged between a signal splitter that splits a high frequency signal into two signal lines and a se of an attenuator and a conductive element, while fifth to eighth switches are arranged between the set of the attenuator and the conductive element and a set of a first high frequency output terminal and a second high frequency output terminal. The plurality of signals having different power levels are output from the first high frequency output terminal and the second high frequency output terminal, respectively.

As illustrated inFIG.1, a high frequency integrated circuit100includes a gain amplifier1, a signal splitter2, a conductive element3, an attenuator4, switches SW1to SW8, a high frequency input terminal Pin1, a high frequency output terminal Pout1, and a high frequency output terminal Pout2, The high frequency integrated circuit100is applied to a receiving block, a transmitting block, and the like in the wireless communication device according to any of the 3G, 4G, and 5G communication standards, for example.

The gain amplifier1is placed between the high frequency input terminal Pin1and a node N1. The gain amplifier1amplifies a high frequency signal input through the high frequency input terminal Pin1and outputs the amplified signal from the node N1. The gain amplifier1corresponds to a low noise amplifier (LNA) when the high frequency integrated circuit100is the receiving block in the wireless communication device, or corresponds to a power amplifier (PA) when the high frequency integrated circuit100is the transmitting block in the wireless communication device.

The signal splitter2is placed between the node N1and a set of a node N2and a node N3. The signal splitter2receives the high frequency signal output from the gain amplifier1at an input terminal (the node N1), distributes the high frequency signal to two lines, and then outputs the two signals said above. The signal splitter2is also called a power divider, a power splitter, a divider, or the like.

The switches SW1to SW4are arranged between the signal splitter2and a set of the conductive element3and the attenuator4.

The switch SW1is placed between the node N2and a node N4as an input terminal of the conductive element, and controls on and off states between the node N2and the node N4based on a control signal.

The switch SW2is placed between the node N2and a node N5(the attenuator4), and controls on and off states between the node N2and the node N5(the attenuator4) based on the control signal.

The switch SW3is placed between the node N3and the node N4as an input terminal of the conductive element, and controls on and off states between the node N3and the node N4(the conductive element3) based on the control signal.

The switch SW4is placed between the node N3and the node N5(the attenuator4), and controls on and off states between the node N3and the node N5(the attenuator4) based on the control signal.

The conductive element3is placed between the node N4and a node N6. The conductive element has a predetermined amount of attenuation (also referred to as an amount of loss). The conductive element3received a signal at the node N4and outputs an attenuated signal from the node N6.

The attenuator4is placed between the node N5and a node N7. A plurality of amounts of attenuation having different values are set in the signal passband in the attenuator4. The attenuator4received a signal at the node N5and outputs an attenuated signal from the node N7.

The switches SW5to SW8are arranged between a set of the conductive element3and the attenuator4and a set of the high frequency output terminal Pout1and the high frequency output terminal Pout2.

The switch SW5is placed between the node N6and a node N8(the high frequency output terminal Pout1), and controls on and off states between the node N6and the node N8(the high frequency output terminal Pout1) based on the control signal.

The switch SW6is placed between the node N6and a node N9(the high frequency output terminal Pout2), and controls on and off states between the node N7and the node N9(the high frequency output terminal Pout2) based on the control signal.

The switch SW7is placed between the node N7and the node N8(the high frequency output terminal Pout1), and controls on and off states between the node N7and the node N8(the high frequency output terminal Pout1) based on the control signal.

The switch SW8is placed between the node N7and the node N9(the high frequency output terminal Pout2), and controls on and off states between the node N7and the node N9(the high frequency output terminal Pout2) based on the control signal.

The high frequency output terminal Pout1outputs multiple power levels by variable attenuated value of the attenuator4and the predetermined gains of the gain amplifier1. The high frequency output terminal Pout2outputs multiple power levels by variable attenuated value of the attenuator4and the predetermined gains of the gain amplifier1(to be described later in detail).

In the embodiment, the multiple power levels by variable attenuated value of the attenuator4and the predetermined gains of the gain amplifier1output from the high frequency output terminal Pout1and the high frequency output terminal Pout2, respectively, are set equal to one another. However, the invention is not limited only to the above-described configuration. The multiple power levels output from the high frequency output terminal Pout1and the high frequency output terminal Pout2, respectively, may be different from one another.

A specific configuration of the switches SW1to SW8will be described with reference toFIG.2andFIG.3.FIG.2is a circuit diagram illustrating each of the switches.FIG.3is a diagram to explain transistors constituting the switches illustrated inFIG.2.

As illustrated inFIG.2, each of the switches SW1to SW8is a T-type switch that is formed from switches SWa to SWc. Each of the switches SW1to SW8is a high frequency switch having a very small insertion loss property in the passband (such as a gigahertz band) when the switch is on and a very large isolation property when the switch is off.

The switch SWa is placed between an input side and a node N11, and selects conductive or non-conductive between the input side and the node N11based on a control signal. The switch SWb is placed between the node N11and an output side, and controls on and off states between the node N11and the output side based on a control signal. The switch SWc is placed between the node N11and ground potential (a common voltage potential) Vss, and controls on and off states between the node N11and the ground potential (the common voltage potential) Vss. Note that time and a period for the on and off control with the control signal to control the switch may vary among the switches SW1to SW8.

As illustrated inFIG.3, each of the switches SW1to SW8includes N-channel MOS transistors NMOST1to NMOST3formed on a silicon-on-insulator (SOI) substrate.

The N-channel MOS transistor NMOST1has a first terminal (a drain) coupled to the input side, a second terminal (a source) coupled to the node N11, and a control terminal (a gate) that receives the control signal. The N-channel MOS transistor NMOST2has a first terminal (a drain) coupled to the node N11, a second terminal (a source) coupled to the output side, and a control terminal (a gate) that receives the control signal input to the control terminal of the N-channel MOS transistor NMOST1. The N-channel MOS transistor NMOST3has a first terminal (a drain) coupled to the node N11, a second terminal (a source) coupled to the ground potential (the common voltage potential) Vss, and a control terminal (a gate) that receives a control signal.

Here, any of a pseudomorphic high electron mobility transistor (pHEMT), a GaAs MESFET, an N-channel MOS transistor formed on a silicon substrate, and the like may be used instead of the N-channel MOS transistor formed on a SOI substrate.

A specific configuration and loss modes of the attenuator4will be described with reference toFIG.4andFIG.5.FIG.4is a circuit diagram illustrating the attenuator, andFIG.5is a diagram listing loss modes of the attenuator.

As illustrated inFIG.4, the attenuator4is formed of a T-type attenuator10, a T-type attenuator11, and a conductive element12. The T-type attenuator10, the T-type attenuator11, and the conductive element12are arranged between an input side and an output side. In the attenuator4, three types of loss modes to attenuate an input signal can be set. Although the attenuator4has two sets of the T-type attenuator10and the T-type attenuator11herein, the invention is not necessarily limited only to the above-described configuration. The attenuator4may have one set of the T-type attenuator, for example.

The conductive element12is placed between the input side and the output side, and is represented by an equivalent circuit in which a switch SW10and a resistor R7are coupled in series. In the conductive element12, the same amount of loss as the conductive element3is set. The switch SW10is placed between the input side and a node N20, and controls on and off states between the input side and the output side based on a control signal. The resistor R7is placed between the node N20and the output side, and attenuates a signal at the node N20and outputs the attenuated signal to the output side.

The T-type attenuator10is placed between the input side and the output side, and is composed of switches SW11to SW13and resistors R1to R3. The attenuation frequency characteristics of the T-type attenuator10in a band of interest is small. In the T-type attenuator10, an amount of loss larger than those by the conductive element3and the conductive element12is set so that the input signal is attenuated more than those attenuated by the conductive element3and the conductive element12.

The switch SW11is placed between the input side and a node N21, and selects conductive or non-conductive between the input side and the node N21based on a control signal. The resistor R1is placed between the node N21and a node N22, and attenuates a signal at the node N21. The resistor R2is placed between the node N22and a node N23, and attenuates a signal at the node N22. The resistor R1attenuates the signal at the node N21. The resistor R2attenuates the signal at the node N21The switch SW12is placed between the node N23and the output side, and controls on and off states between the node N23and the output side based on a control signal. The resistor R3is placed between the node N22and a node N24, and attenuates the signal at the node N22. The switch SW13is placed between the node N24and the ground potential (the common voltage potential) Vss, and controls on and off states between the node N24and the ground potential (the common voltage potential) Vss based on a control signal.

The T-type attenuator11is placed between the input side and the output side, and is formed from switches SW14to S16and resistors R4to R6. The T-type attenuator11is an attenuator of which the dependency on the frequency in a band that the signal passes through is small. In the T-type attenuator11, an amount of loss larger than that of the T-type attenuator10is set so that the input signal is attenuated more than that attenuated by the T-type attenuator10. However, the invention is not necessarily limited to the above-described configuration.

The switch SW14is placed between the input side and a node N25, and selects conductive or non-conductive between the input side and the node N25based on a control signal. The resistor R4is placed between the node N25and a node N26, and attenuates a signal at the node N25. The resistor R5is placed between the node N26and a node N27, and attenuates a signal at the node N26. The switch SW15is placed between the node N27and the output side, and controls on and off states between the node N27and the output side based on a control signal. The resistor R6is placed between the node N26and a node N28, and attenuates the signal at the node N26. The switch SW16is placed between the node N28and the ground potential (the common voltage potential) Vss, and controls on and off states between the node N28and the ground potential (the common voltage potential) Vss based on a control signal.

As illustrated inFIG.5, three loss modes can be set in the attenuator4. In a loss mode1, the conductive element12is set to an “active” state, each of the T-type attenuator10and the T-type attenuator11is set to an “inactive” state. Specifically, the switch SW10is set “on”, the switches SW11, SW12are set “off”, the switch SW13is set “on”, the switches SW14, SW15are set “off”, and the switch SW16is set “on”. An amount of loss in the loss mode1is set equal to an amount of loss of the conductive element3.

In a loss mode2, the T-type attenuator10is set to the “active” state, each of the conductive element12and the T-type attenuator11is set to the “inactive” state. Specifically, the switch SW10is set “off”, the switches SW11, SW12are set “on”, the switch SW13is set “off”, the switches SW14, SW15are set “off”, and the switch SW16is set “on”.

In a loss mode3, the T-type attenuator11is set to the “active” state, each of the conductive element12and the T-type attenuator10is set to the “inactive” state. Specifically, the switch SW10is set “off”, the switches SW11, SW12are set “off”, the switch SW13is set “on”, the switches SW14, SW15are set “on”, and the switch SW16is set “off”.

As illustrated inFIG.6, the conductive element3is placed between an input side and an output side, and is represented by an equivalent circuit in which a switch SW20and a resistor R8are connected in series. The switch SW20is placed between the input side and a node N30, and controls on and off states between the input side and the output side based on a control signal. The resistor R8is placed between the node N30and the output side, and attenuates a signal and outputs the attenuated signal to the output side.

Next, vain settings of the high frequency integrated circuit100will be described with reference toFIG.7andFIG.8.FIG.7andFIG.8are diagrams each explaining a gain setting of the high frequency integrated circuit.

Assuming that the amount of loss of each of the conductive element3and the conductive element12is loss amount1, that the amount of loss of the T-type attenuator10is loss amount2, and that the amount of loss of the T-type attenuator11is loss amount3, the amounts of loss are set to satisfy:
loss amount 1<loss amount 2<loss amount 3  Formula (1).

A gain of the signal output from the gain amplifier1is defined as Gamp(a gain amp). An amount of loss of the signal split into the two lines and output from the signal splitter2is assumed to be 3 dB, The insertion losses of the switches SW1to SW8are extremely small on state, and can therefore be deemed as negligible level. Meanwhile, the switches SW1to SW8have the large isolation properties when the switches are off, hence the influence of the switches that are off to the other switches is negligible.

As illustrated inFIG.7, when the switches SW1, SW4, SW5, SW8are set “on” and the switches SW2, SW3, SW6, SW7are set “off”, specifically, a first signal route of the node N2→the switch SW1→the node N4→the conductive element3→the node N6→the switch SW5→the node N8→the high frequency output terminal Pout1and a second signal route of the node N3→the switch SW4→the node N5→the attenuator4→the node N7→the switch SW8→the high frequency output terminal Pout2are made.

One type of the gain of the signal output from the high frequency output terminal Pout1in the first signal route is set up. The gain of the signal output from the high frequency output terminal Pout1can be expressed as the Gamp(a, gain amp) minus the amount of loss of the signal splitter2(3 dB) minus the loss amount1.

Three types of the gain of the signal output from the high frequency output terminal Pout2in the second signal route are set up. The first type can be expressed as the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount1. The second type can be expressed as the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount2. The third type can be expressed as the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount3.

As illustrated inFIG.8, when the switches SW2, SW3, SW6, SW7are set “on” and the switches SW1, SW4, SW5, SW8are set “off”, specifically, the first signal route of the node N2→the switch SW2→the node N5→the attenuator4→the node N7→the switch SW7→the node N8→the high frequency output terminal Pout1and the second signal route of the node N3→the switch SW3→the node N4→the conductive element3→the node N6→the switch SW→the node N9→the high frequency output terminal Pout2are made.

One type of the gain of the signal output from the high frequency output terminal Pout2in the second signal route is set up. The gain of the signal output from the high frequency output terminal Pout2can be expressed as the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount1.

Three types of the gain of the signal output from the high frequency output terminal Pout1in the first signal route are set up. The first type can be expressed as the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount1. The second type can be expressed as the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount2. The third type can be expressed as the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount3.

Here, in a case where the amounts of loss in the passband of the switches SW1to SW8are not negligible, all of the amounts of loss of the switches SW1to SW4when the switches are on are deemed to be the same loss amount SWILoss1, and all of the amounts of loss of the switches SW5to SW8when the switches are on are deemed to be the same loss amount SWLoss2.

The gain expressed as the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount1can be expressed by the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount1minus (the loss amount SWLoss1plus the loss amount SWLoss2). The vain expressed as the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount2can be expressed by the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount2minus (the loss amount SWLoss1plus the loss amount SWLoss2). The gain expressed as the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount3can be expressed by the gain amp minus the amount of loss of the signal splitter2(3 dB) minus the loss amount3minus (the loss amount SWLoss1plus the loss amount SWLoss2).

Next, high frequency integrated circuits of comparative examples will be described with reference toFIG.9andFIG.10.FIG.9is a circuit diagram illustrating a high frequency integrated circuit of a first comparative example.FIG.10is a circuit diagram illustrating a high frequency integrated circuit of a second comparative example.

As illustrated inFIG.9, a high frequency integrated circuit200of the first comparative example includes a gain amplifier1, a signal splitter2, a high frequency input terminal Pin1, a high frequency output terminal Pout1, and a high frequency output terminal Pout2. In the high frequency integrated circuit200of the first comparative example, a whole gain, which is defined as output power minus input power, in available single state is output from the high frequency output terminal Pout1and the high frequency output terminal Pout2.

As illustrated inFIG.10, a high frequency integrated circuit201of the second comparative example includes a variable gain amplifier5, a signal splitter2, a high frequency input terminal Pin1, a high frequency output terminal Pout1, and a high frequency output terminal Pout2. In the high frequency integrated circuit201of the second comparative example, a whole gain, which is defined as output power minus input power, is available multiple stale.

As described above, the high frequency integrated circuit of the embodiment has the gain amplifier1, the signal splitter2, the conductive element3, the attenuator4, the switches SW1to SW8, the high frequency input terminal Pin1, the high frequency output terminal Pout1, and the high frequency output terminal Pout2. The switches SW1to SW4are arranged between the signal splitter2that distributes the high frequency signal to two lines and the set of the attenuator4and the conductive element3, while the switches SW5to SW8are arranged between the set of the attenuator4and the conductive element3and the set of the first high frequency output terminal Pout1and the second high frequency output terminal Pout2. Each of the switches SW1to SW8has only a small insertion loss property in the passband when the switch is on and a very large isolation property when the switch is off. Moreover, using the switches SW1to SW8, the two signal routes are set between the set of the output terminal (the node N2) and the output terminal (the node N3) of the signal splitter2and the set of the high frequency output terminal Pout1and the high frequency output terminal Pout2.

Accordingly, it is possible to output a plurality of signals having different gain values from the high frequency output terminal Pout1and the high frequency output terminal Pout2, respectively.

Although three types of loss modes are set in the attenuator4in the embodiment, the invention is not limited only to the above-described configuration. Two types or four or more types of loss modes may be set in the attenuator4. Although the values of the amounts of loss of the conductive element3and the conductive element12are set equal to each other, the invention is not limited only to the above-described configuration. The amounts of loss may be set different values.

Alternatively, the conductive element3may be replaced with an attenuator that is similar to the attenuator4. In this case, although a circuit scale of the high frequency integrated circuit is increased, it is possible to increase the numbers of combinations of the gain values. In particular, the numbers of combinations of the gain values increases from 5 to 9.

A high frequency integrated circuit according to a second embodiment will be described with reference to the drawings.FIG.11is a circuit diagram illustrating the high frequency integrated circuit.

In the second embodiment, a variable gain amplifier is used in the high frequency integrated circuit. A first high frequency output terminal and a second high frequency output terminal, respectively, output multiple output signals. Each of the multiple output signals has a different gain value.

In the following, the same portions as those in the first embodiment will be designated by the same reference numerals, explanations of those portions will be omitted, and only different portions will be described.

As illustrated inFIG.11, a high frequency integrated circuit101includes a variable gain amplifier5, the signal splitter2, the conductive element3, the attenuator4, the switches SW1to SW8, the high frequency input terminal Pin1, the high frequency output terminal Pout1, and the high frequency output terminal Pout2. The high frequency integrated circuit101is applied to a receiving block and the like in the wireless communication device according to any of the 3G, 4G, and 5G communication standards, for example.

The variable gain amplifier5is placed between the high frequency input terminal Pin1and the node N1. The variable gain amplifier5receives and amplifies a signal input through the high frequency input terminal Pint and outputs the amplified signal from the node N1. Here, in the variable gain amplifier5, multiple gain values are available to set. The signal splitter2receives the various gain signal output from the variable gain amplifier5and splits the signal to two lines.

Next, vain settings of the high frequency integrated circuit101will be described with reference toFIG.12.FIG.12is a diagram to explain gain settings of the high frequency integrated circuit.

As illustrated inFIG.12, it is assumed that the amount of attenuation (the amount of loss) of the signal splitter2is 3 dB, the amount of attenuation (the amount of loss) of the conductive element3is 1 dB, the amount of attenuation (the amount of loss) in the case where the conductive element12of the attenuator4is selected is 1 dB, the amount of attenuation (the amount of loss) in the case where an attenuator10of the attenuator4is selected is 3 dB, the amount of attenuation (the amount of loss) in the case where an attenuator11of the attenuator4is selected is 5 dB, Each amount of loss of the switches SW1to SW8is negligible.

In the case where the gain of the signal output from the variable gain amplifier5is equal to 20 dB, for example, signals having three types of gains, namely, 16 dB, 13 dB, and 11 dB are output from the high frequency output terminal Pout1and the high frequency output terminal Pout2. Combinations of the gains are five types, namely, 16 dB/16 dB, 16 dB/13 dB, 16 dB/11 dB, 13 dB/16 dB, and 11 dB/16 dB.

In the case where the gain of the signal output from the variable gain amplifier5is equal to 15 dB, for example, signals having three types of gains, namely, 11 dB, 8 dB, and 6 dB are output from the high frequency output terminal Pout1and the high frequency output terminal Pout2. Combinations of the signals to be output from the high frequency output terminal Pout1and the high frequency output terminal Pout2are set to five types, namely, 11 dB/11 dB, 11 dB/8 dB, 11 dB/6 dB, 8 dB/11 dB, and 6 dB/11 dB.

As described above, the high frequency integrated circuit of the embodiment has the variable gain amplifier5, the signal splitter2, the conductive element3, the attenuator4, the switches SW1to SW8, the high frequency input terminal Pin1, the high frequency output terminal Pout1and the high frequency output terminal Pout2. The variable gain amplifier5is placed between the high frequency input terminal Pint and the node N1, and outputs the multiple gain values.

As a consequence, it is possible to output more multiple gain values from the high frequency output terminal Pout1and the high frequency output terminal Pout2than the first embodiment.

Meanwhile, in the embodiment, the conductive element3may be replaced with an attenuator that is similar to the attenuator4. In this case, although a circuit scale of the high frequency integrated circuit is increased, it is possible to increase multiple gain values from the high frequency output terminal Pout1and the high frequency output terminal Pout2, and increase the number of the combination of the gain values from 5 to 9.

A high frequency integrated circuit according to a third embodiment will be described with reference to the drawing.FIG.13is a circuit diagram illustrating the high frequency integrated circuit.

In the third embodiment, n SPnT switches collectively constituting a first SPnT switch group (n being an integer equal to or above 3) are arranged between a signal splitter, which splits a high frequency signal to n lines, and a set of (n−1) attenuators and a conductive element, and n SPnT switches collectively constituting a second SPnT switch group are arranged between the set of the (n−1) attenuators and the conductive element and first to n-th high frequency output terminals. Multiple gain values are output from the first to n-th high frequency output terminals, respectively.

In the following, the same portions as those in the first embodiment will be designated by the same reference numerals, explanations of those portions will be milled, and only different portions will be described.

As illustrated inFIG.13, a high frequency integrated circuit110includes the gain amplifier1, a signal splitter2a, the conductive element3, attenuators41to4n−1, SPnT switches SPnT1to SPnTn, SPnT switches SPnT11to SPnT1n, the high frequency input terminal Pin1, and high frequency output terminals Pout1to Poutn. The high frequency integrated circuit110is applied to a receiving block, a transmitting block, and the like in the wireless communication device according to any of the 3G, 4G, and 5G communication standards, for example. Here, n is an integer equal to or above 3.

The signal splitter2ais placed between the gain amplifier1and a set of the SPnT switches SPnT1to SPnT1arranged and constituting the first SPnT switch group. The signal splitter2asplits a signal output from the gain amplifier1to n lines (where n is the integer equal to or above 3), and outputs the signals split into the n lines from first to n-th output terminals (nodes N41to N4n), respectively. Here, the larger the number of split lines are increased, the more the amount of attenuation (the amount of loss) of the signal at the signal splitter2ais increased.

Each of the SPnT (which stands for “single pole n throw”) switches SPnT1to SPnT and the SPnT switches SPnT11to SPnT1nis a high frequency switch having only a very small insertion loss property in the passband (such as a gigahertz band) when the switch is on and a large isolation property when the switch is off. The insertion loss properties of the SPnT switches SPnT1to SPnTnand the SPnT switches SPnT11to SPnT1nare preferably set equal to one another.

The SPnT switches SPnT1to SPnTnarranged and constituting the first SPnT switch group are placed between the signal splitter2aand a set of the conductive element3and the (n−1) attenuators41to4n−1.

The SPnT switch SPnT1of the first SPnT switch group is placed between the first output terminal (the node N41) of the signal splitter2aand the set of the conductive element3(a node N51) and the (n−1) attenuators41to4n−1(nodes N52to N5n). The SPnT switch SPnT1selects conductive or non-conductive between the first output terminal (the node N41) of the signal splitter2aand one of the set of the conductive element3(the node N51) and the (n−1) attenuators41to4n−1(the nodes N52to N5n), and turns off between the first output terminal (the node N41) of the signal splitter2aand the rest of the set of the conductive element3(the node N51) and the (n−1) attenuators41to4n−1(the nodes N52to N5n).

The SPnT switch SPnT2of the first SPnT switch group is placed between the second output terminal (the node N42) of the signal splitter2aand the set of the conductive element3(the node N51) and the (n−1) attenuators41to4n−1(the nodes N52to N5n). The SPnT switch SPnT2selects conductive or non-conductive between the second output terminal (the node N42) of the signal splitter2aand one of the set of the conductive element3(the node N51) and the (n−1) attenuators41to4n−1(the nodes N52to N5n), and turns off between the second output terminal (the node N42) of the signal splitter2aand the rest of the set of the conductive element3(the node N51) and the (n−1) attenuators41to4n−1(the nodes N52to N5n).

The SPnT switch SPnTnof the first SPnT switch group is placed between the n-th output terminal (the node N4n) of the signal splitter2aand the set of the conductive element3(the node N51) and the (n−1) attenuators41to4n−1(the nodes N52to N5n). The SPnT switch SPnTnselects conductive or non-conductive between the n-th output terminal (the node N4n) of the signal splitter2aand one of the set of the conductive element3(the node N51) and the (n−1) attenuators41to4n−1(the nodes N52to N5n), and turns off between the n-th output terminal (the node N4n) of the signal splitter2aand the rest of the set of the conductive element3(the node N51) and the (n−1) attenuators41to4n−1(the nodes N52to N5n).

The conductive element3and the (n−1) attenuators41to4n−1are placed between the SPnT switches SPnT11to SPnTncollectively constituting the first switch group and the SPnT switches SPnT11to SPnT1ncollectively constituting the second switch group.

The conductive element3has the same configuration and properties as that of the conductive element3of the first embodiment, and is placed between the node N51and a node N61. The (n−1) attenuators41to4n−1have the same configuration and properties as those of the attenuator4of the first embodiment.

The SPnT switches SPnT11to SPnT1nconstituting the second SPnT switch group are placed between the set of the conductive element3and the (n−1) attenuators41to4n−1and a set of the high frequency output terminals Pout1to Poutn.

The SPnT switch SPnT11of the second SPnT switch group is placed between the conductive element3(the node N61) and the set of the high frequency output terminals Pout1to Poutn (nodes N71to N7n). The SPnT switch SPnT11selects conductive or non-conductive between the conductive element3(the node N61) and one of the high frequency output terminals Pout1to Poutn (nodes N71to N7n), and turns off between the conductive element3(the node N61) and the rest of the high frequency output terminals Pout1to Poutn (the nodes N71to N7n).

The SPnT switch SPnT12of the second SPnT switch group is placed between the attenuator41(a node N62) and the set of the high frequency output terminals Pout1to Poutn (the nodes N71to N7n). The SPnT switch SPnT12selects conductive or non-conductive between the attenuator41(the node N62) and one of the high frequency output terminals Pout1to Poutn (the nodes N71to N7n), and turns off between the attenuator41(the node N62) and the rest of the high frequency output terminals Pout1to Poutn (the nodes N71to N7n).

The SPnT switch SPnT1nselects conductive or non-conductive is placed between the attenuator4n−1(a node N6n) and the set of the high frequency output terminals Pout1to Poutn (the nodes N71to N7n). The SPnT switch SPnT1nselects conductive or non-conductive between the attenuator4n−1(the node N6n) and one of the high frequency output terminals Pout1to Poutn (the nodes N71to N7n), and turns off between the attenuator4n−1(the node N6n) and the rest of the high frequency output terminals Pout1to Poutn (the nodes N71to N7n).

The high frequency output terminals Pout1to Poutn (the nodes N71to N7n) output a plurality of signals having different gain values, respectively.

As described above, the high frequency integrated circuit of the embodiment has the gain amplifier1, the signal splitter2a, the conductive element3, the attenuators41to4n−1, the SPnT switches SPnT1to SPnTn, the SPnT switches SPnT11to SPnT1n, the high frequency input terminal Pin1, and the high frequency output terminals Pout1to Poutn. The n SPnT switches SPnT1to SPnTncollectively constituting the first SPnT switch group are arranged between the signal splitter2a, which splits the high frequency signal to n lines, and the set of the (n−1) attenuators41to4n−1and the conductive element3, and the n SPnT switches SPnT11to SPnTincollectively constituting the second SPnT switch group are arranged between the set of the (n−1) attenuators41to4n−1and the conductive element3and the set of the high frequency output terminals Pout1to Poutn. The plurality of signals having different gain values are output from the high frequency output terminals Pout1to Poutn, respectively.

As a consequence, it is possible to output signals having different gain values from a larger number of high frequency output terminals than in the first embodiment.

Meanwhile, in the embodiment, the conductive element3may be replaced with an attenuator that is similar to the attenuators41to4n−1. In this case, although a circuit scale of the high frequency integrated circuit is increased, it is possible to increase multiple gain values output from the high frequency output terminals Pout1to Poutn.

A high frequency integrated circuit according to a fourth embodiment will be described with reference to the drawing.FIG.14is a circuit diagram illustrating the high frequency integrated circuit.

In the fourth embodiment, a variable gain amplifier is used in the high frequency integrated circuit. A plurality of signals having different gain values are output from first to n-th high frequency output terminals, respectively.

In the following, the same portions as those in the third embodiment will be designated by the same reference numerals, explanations of those portions will be omitted, and only different portions will be described.

As illustrated inFIG.14, a high frequency integrated circuit120includes a variable gain amplifier5, the signal splitter2a, the conductive element3, the attenuators41to4n−1, the SPnT switches SPnT1to SPnTn, the SPnT switches SPnT11to SPnT1n, the high frequency input terminal Pin1, and the high frequency output terminals Pout1to Poutn. The high frequency integrated circuit120is applied to a receiving block and the like in the wireless communication device according, to any of the 3G, 4G and 5G communication standards, for example. Here, n is an integer equal to or above 3.

The variable gain amplifier5is placed between the high frequency input terminal Pin1and the node N1. The variable gain amplifier5receives and amplifies a signal input through the high frequency input terminal Pin1and outputs the amplified signal from the node N1. Here, in the variable gain amplifier5, a plurality of stages of gains are set. The signal splitter2areceives the variable gain signal output from the variable gain amplifier5and splits the signal to n lines.

As described above, the high frequency integrated circuit of the embodiment has the variable gain amplifier5, the signal splitter2a, the conductive element3, the attenuators41to4n−1, the SPnT switches SPnT1to SPnTn, the SPnT switches SPnT11to SPnT1n, the high frequency input terminal Pint, and the high frequency output terminals Pout1to Poutn. The variable gain amplifier5outputs the variable gain signal.

As a consequence, it is possible to output more multiple gain values from the high frequency output terminals Pout1to Poutn than the third embodiment.

Meanwhile, in the embodiment, the conductive element3may be replaced with an attenuator that is similar to the attenuators41to4n−1. In this case, although a circuit scale of the high frequency integrated circuit is increased, it is possible to increase multiple gain values from the high frequency output terminals Pout1to Poutn, compared to the third embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only and are not intend to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of the other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.