Package comprising wire bonds configured as a heat spreader

A package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.

FIELD

Various features relate to packages that include an integrated device, but more specifically to a package that includes an integrated device, a substrate, and wire bonds configured as a heat spreader.

BACKGROUND

FIG.1illustrates a package100that includes a substrate102, an integrated device104, and an encapsulation layer108. The substrate102includes at least one dielectric layer120, a plurality of interconnects122, and a plurality of solder interconnects124. A plurality of solder interconnects144is coupled to the substrate102and the integrated device104. The integrated device104may be a flip chip. The encapsulation layer108encapsulates the integrated device104and the plurality of solder interconnects144. Encapsulating the integrated device104with the encapsulation layer108can restrict and slow down the heat that dissipates from the integrated device104, which can cause the integrated device104to overheat. There is an ongoing need to provide efficient heat dissipation for integrated devices.

SUMMARY

Various features relate to packages that include an integrated device, but more specifically to a package that includes an integrated device, a substrate, and wire bonds configured as a heat spreader.

One example provides a package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.

Another example provides a device that includes a package. The package includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.

Another example provides an apparatus that includes a substrate, an integrated device, means for wire interconnection, means for wire heat dissipation and means for encapsulation. The integrated device is coupled to the substrate. The means for wire interconnection is coupled to the integrated device and the substrate. The means for wire interconnection is configured to provide at least one electrical path between the integrated device and the substrate. The means for wire heat dissipation is coupled to the integrated device. The means for wire heat dissipation is configured to be free of an electrical connection with a circuit of the integrated device. The means for encapsulation is located over the substrate and the integrated device. The means for encapsulation encapsulates the integrated device, the means for wire interconnection and the means for wire heat dissipation.

Another example provides a method for fabricating package. The method provides a substrate. The method couples an integrated device to the substrate. The method couples a plurality of first wire bonds to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The method couples at least one second wire bond to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The method forms an encapsulation layer over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.

DETAILED DESCRIPTION

The present disclosure describes a package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond. The at least one second wire bond is configured to dissipate heat from the integrated device. The package may further include a metal layer formed over an outer surface of the encapsulation layer, where the metal layer is configured as an electromagnetic interference (EMI) shield. The at least one second wire bond is coupled to the metal layer. The package provides a package that can efficiently and effectively dissipate heat away from the integrated device. The wire bonds are much closer to the heat source (e.g., integrated device), thus the wire bonds may provide better and improved heat dissipation from the integrated device. Additionally, using wire bonds adds minimal fabrication costs, since wire bonds are already being formed over the integrated device to provide electrical connections for the integrated device.

Exemplary Package Comprising a Substrate, an Integrated Device and a Wire Bond Configured as a Heat Spreader

FIG.2illustrates a profile view of a package200that includes wire bonds as a heat spreader. Through the use of wire bonds, the package200provides a package with an efficient and effective structure for heat dissipation from an integrated device. The package200may provide a cost-effective solution of providing heat dissipation from an integrated device. As shown inFIG.2, the package200includes a substrate202, an integrated device206, a plurality of first wire bonds210, at least one second wire bond212, an encapsulation layer208, and a metal layer230.

The substrate202includes at least one dielectric layer220and a plurality of interconnects222. Different implementations may provide different types of substrates. The substrate202may be a coreless substrate (e.g., embedded trace substrate), a laminate substrate, or a substrate that includes a core layer. The at least one dielectric layer220may include different materials, such as prepreg layer, a polyimide (e.g., photo-etchable dielectric layer), an organic layer, and/or a ceramic.

The integrated device206is coupled to the substrate202. The integrated device206may include a semiconductor bare die. The integrated device206may include a front side and a back side (e.g., bare die may include a front side and a back side). The back side of the integrated device206may be coupled to a first surface (e.g., top surface) of the substrate202through an attach260(e.g., die attach). The plurality of first wire bonds210is coupled to the integrated device206and the substrate202. The plurality of first wire bonds210is configured to provide at least one electrical path between the integrated device206and the substrate202. The plurality of first wire bonds210may be a means for wire interconnection. Examples of how the plurality of first wire bonds210is coupled to the integrated device206and the substrate202are further illustrated and described below in at leastFIGS.3-4.

The at least one second wire bond212is coupled to the integrated device206. The at least one second wire bond212may be a means for wire heat dissipation. The at least one second wire bond212is configured to be free of an electrical connection with a circuit of the integrated device206. A circuit of the integrated device206may include active devices. An active device may include at least one transistor. Examples of how the at least one second wire bond212is coupled to the integrated device206are further illustrated and described below in at leastFIGS.3-4. The plurality of first wire bond210and the at least one second wire bond212may be made of similar material or the same material.

The encapsulation layer208is formed and located over the substrate202and the integrated device206. The encapsulation layer208may be coupled to a first surface (e.g., top surface) of the substrate202. The encapsulation layer208may encapsulate the integrated device206, the plurality of first wire bonds210and the at least one second wire bond212. The encapsulation layer208may include a mold, a resin and/or an epoxy. The encapsulation layer208may be a means for encapsulation. The at least one second wire bond212is configured to dissipate heat from the integrated device206. The at least one second wire bond212may be configured to dissipate heat from an integrated device206by providing a thermally conductive path for heat to dissipate from the integrated device and towards a top surface of the encapsulation layer208. The at least one second wire bond212may travel away from the integrated device206(e.g., travel vertically relative to a surface of the integrated device206). However, as will be described below, the at least one second wire bond212may travel in different directions and/or paths.

The metal layer230is formed and located over an outer surface of the encapsulation layer208and/or a side surface of the substrate202. The metal layer230may be coupled to the outer surface of the encapsulation layer208and/or the side surface of the substrate202. The metal layer230may be configured as an electromagnetic interference (EMI) shield. The metal layer230may include several metal layers. The at least one second wire bond212is coupled to the metal layer230. In some implementations, the at least one second wire bond212and/or the metal layer230may be configured to be coupled to ground. The metal layer230may help with heat dissipation. The metal layer230may be a conformal metal layer. The metal layer230may be an outer metal layer.

A plurality of solder interconnects240is coupled to the second surface (e.g., bottom surface) of the substrate202. The plurality of solder interconnects240may be coupled to the plurality of interconnects222through a reflow process.

FIGS.3and4illustrate close up views of how wire bonds may be coupled to an integrated device and a substrate.FIG.3illustrates an integrated device206that includes a die substrate302, a plurality of active devices310located over the die substrate302, and a plurality of die interconnects320(e.g.,320a,320b), at least one die substrate via330and a passivation layer340. The integrated device206includes a front side and a back side. The front side of the integrated device206may include the side with the passivation layer340, the plurality of die interconnects320and/or the plurality of active devices310. The plurality of active devices310may include at least one transistor. The back side of the integrated device206may include the side with the die substrate302. As shown inFIG.3, the back side of the integrated device206(e.g., die substrate of the integrated device) may be coupled to the first surface of the substrate202, through the attach260. For example, the back side of the bare die is coupled to the first surface of the substrate202through an attach (e.g.,260) die attach, and the front side of the bare die is configured to be electrically coupled to the first surface of the substrate202through the plurality of first wire bonds210.

The plurality of die interconnects320may include a plurality of first die interconnects320aand at least one second die interconnect320b. The plurality of first die interconnects320a(e.g., pad) is coupled to the plurality of active devices310. The at least second die interconnect320bis coupled to the at least one second wire bond212. The at least one second die interconnect320bmay be configured to be free of electrical connection with the plurality of active devices310. That is, the at least one second die interconnect320bmay be configured to be free of electrical connection with transistors of the integrated device206.

The plurality of first wire bonds210is coupled to the plurality of first die interconnects320a(e.g., wire bond pad) of the integrated device206. The plurality of first wire bonds210is coupled to the plurality of interconnects222(e.g., wire bond pad of substrate). Thus, at least one electrical current (e.g., electrical signal) between the integrated device206and the substrate202may travel through the plurality of first wire bonds210. In particular, at least one electrical current between the plurality of active devices310and the substrate202may travel through the plurality of first wire bonds210.

The at least one second wire bond212is coupled to the at least one second die interconnect320b(e.g., pad). The at least one second die interconnect320bmay be coupled to the at least one die substrate via330. The at least one die substrate via330may travel through the back side of the die substrate302. Heat from the integrated device206may dissipate through the at least one second wire bond212, the at least second die interconnect320band/or the at least one die substrate via330. The at least one second wire bond212, the at least second die interconnect320band/or the at least one die substrate via330may be configured to be free of an electrical connection with the plurality of active devices310(e.g., transistors) of the integrated device206. The at least one second wire bond212, the at least second die interconnect320band/or the at least one die substrate via330may be configured to be coupled to ground. In some implementations, the at least one second wire bond212may be located as close as 50 micrometers to the plurality of active devices310. For example, a vertical distance between the at least one wire bond212and an active device from the plurality of active devices310may be about 50 micrometers or greater.

FIG.4illustrates an integrated device206that includes the die substrate302, the plurality of active devices310located over the die substrate302, and the plurality of die interconnects320, at least one die substrate via330, at least one die interconnect430and a passivation layer340. The integrated device206ofFIG.4is similar to the integrated device206ofFIG.3. However, as shown inFIG.4, the at least one die interconnect430(e.g., pad) is coupled to the at least one die substrate via330. The at least one die interconnect430may be located over the back side of the integrated device206(e.g., over the back side of the die substrate302). The at least one die interconnect430may be located over the first surface of the substrate202. The at least one die interconnect430may be coupled to the at least one dielectric layer220and/or at least one interconnect located in and/or over the at least one dielectric layer220.

FIG.5illustrates a plan view of the package200that includes the integrated device206, the metal layer230, the plurality of first wire bonds210, the at least one second wire bond212, and the plurality of interconnects222.FIG.5may illustrate a top view of the package200.FIG.5illustrates that the plurality of first wire bonds210and the at least one second wire bond212may be coupled to various components, and is thus not limited to being coupled to integrated devices. Some of the interconnects from the plurality of interconnects222may be configured as passive devices, such as an inductor.

FIG.6illustrates a profile view of a package600. The package600is similar to the package200. Thus, the package600includes similar components and/or the same components as the package200.FIG.6illustrates that at least some of the wire bonds that are configured for heat dissipation may be aligned and/or oriented in different directions. The package600includes the substrate202, the integrated device206, the plurality of first wire bonds210, at least one second wire bond612(e.g.,612a-612d), the encapsulation layer208, and the metal layer230. The at least one second wire bond612may be a means for wire heat dissipation. The at least one second wire bond612is similar to the at least one second wire bond212, and may be coupled to the integrated device206in a similar manner as described inFIGS.2-4. The at least one second wire bond612may include at least one vertical wire bond, at least one diagonal wire bond, at least one curved wire bond, at least one non-linear wire bond, or combinations thereof. A wire bond that travels vertically (e.g., extends vertically) may extend vertically linearly and/or non-linearly, with respect to a surface of a component. A wire bond that travels vertically may extend away from a surface of a component to which the wire bond is coupled to. A wire bond that travels vertically may include a wire bond that extends diagonally (linearly and/or non-linearly).

FIG.7illustrates a profile view of a package700. The package700is similar to the package200and/or the package600. Thus, the package700includes similar components and/or the same components as the package200and/or the package600.FIG.7illustrates that a package may include more than one integrated device. The package700includes the substrate202, the integrated device206, the plurality of first wire bonds210, at least one second wire bond212, an integrated device706, a plurality of first wire bonds710, at least one second wire bond712, the encapsulation layer208, and the metal layer230. The plurality of first wire bonds710is similar to the plurality of wire bonds210, and may be coupled to the integrated device706in a similar manner as described inFIGS.2-4. Similarly, the at least one second wire bond712is similar to the at least one second wire bond612, and may be coupled to the integrated device706in a similar manner as described inFIGS.2-4and6. The integrated device (e.g.,206,706) may include a power amplifier. The package (e.g.,200,600,700) may include a radio frequency front end (RFFE) package.

An integrated device (e.g.,206,706) may include a die (e.g., bare die). The integrated device may include a radio frequency (RF) device, an analog device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a surface acoustic wave (SAW) filters, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si) based integrated device, a silicon carbide (SiC) based integrated device, a GaAs based integrated device, a GaN based integrated device, a memory, power management processor, and/or combinations thereof.

Having described various packages that include wire bonds as a heat spreader, various methods for fabricating the substrate and the package will now be described below.

Exemplary Sequence for Fabricating a Substrate

In some implementations, fabricating a substrate includes several processes.FIGS.8A-8Billustrate an exemplary sequence for providing or fabricating a substrate. In some implementations, the sequence ofFIGS.8A-8Bmay be used to provide or fabricate the substrate202ofFIG.2. However, the process ofFIGS.8A-8Bmay be used to fabricate any of the substrates described in the disclosure. It is noted that other types of substrates may be used instead of the substrate shown inFIGS.8A-8B.

Stage1, as shown inFIG.8A, illustrates a state after a carrier800is provided and a metal layer is formed over the carrier800. The metal layer may be patterned to form interconnects802. A plating process and etching process may be used to form the metal layer and interconnects.

Stage2illustrates a state after a dielectric layer820is formed over the carrier800and the interconnects802. A deposition process may be used to form the dielectric layer820. The dielectric layer820may include polyimide. However, different implementations may use different materials for the dielectric layer.

Stage3illustrates a state after at least one cavity810is formed in the dielectric layer820. The at least one cavity810may be formed using an etching process (e.g., photo etching process) or a laser process.

Stage4illustrates a state after interconnects812are formed in and over the dielectric layer820. For example, a via, pad and/or traces may be formed. A plating process may be used to form the interconnects. The interconnects812may be part of the plurality of interconnects222.

Stage5illustrates a state after another dielectric layer822is formed over the dielectric layer820. A deposition process may be used to form the dielectric layer822. The dielectric layer822may be the same material as the dielectric layer820. However, different implementations may use different materials for the dielectric layer (e.g.,820,822).

Stage6, as shown inFIG.8B, illustrates a state after at least one cavity830is formed in the dielectric layer822. An etching process or a laser process may be used to form the at least one cavity830.

Stage7illustrates a state after interconnects814are formed in and over the dielectric layer822. For example, via, pad and/or trace may be formed. A plating process may be used to form the interconnects. The interconnects814may be part of the plurality of interconnects222.

Stage8illustrates a state after the carrier800is decoupled (e.g., removed, grinded out, dissolved) from the at least one dielectric layer220, leaving the substrate202. The at least one dielectric layer220may represent the dielectric layer820and the dielectric layer822. The plurality of interconnects222may represent the plurality of interconnects802,812and/or814. Stage8may illustrate the substrate202ofFIG.2.

Different implementations may use different processes for forming the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and/or a physical vapor deposition (PVD) process may be used for forming the metal layer(s). For example, a sputtering process, a spray coating process, and/or a plating process may be used to form the metal layer(s).

Exemplary Flow Diagram of a Method for Fabricating a Substrate

In some implementations, fabricating a substrate includes several processes.FIG.9illustrates an exemplary flow diagram of a method900for providing or fabricating a substrate. In some implementations, the method900ofFIG.9may be used to provide or fabricate the substrate202ofFIG.2, or any of the substrates described in the disclosure.

It should be noted that the method ofFIG.9may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified.

The method provides (at905) a carrier800. Different implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz and/or carrier tape. Stage1ofFIG.8Aillustrates an example after a carrier is provided.

The method forms (at910) a metal layer over the carrier800. The metal layer may be patterned to form interconnects. A plating process may be used to form the metal layer and interconnects. Stage1ofFIG.8Aillustrates an example after a metal layer and interconnects802are formed.

The method forms (at915) at least one dielectric layer (e.g., dielectric layer820) over the carrier800and the interconnects802. The dielectric layer820may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g.,810) in the dielectric layer820. A deposition process may be used to form the at least one dielectric layer. The plurality of cavities may be formed using an etching process (e.g., photo etching) or laser process. Stages2-3ofFIG.8Aillustrate an example of forming a dielectric layer and cavities in the dielectric layer.

The method forms (at920) interconnects in and over the dielectric layer. For example, the interconnects812may be formed in and over the dielectric layer820. A plating process may be used to form the interconnects. Forming interconnects may include providing a patterned metal layer over and/or in the dielectric layer. Stage4ofFIG.8Aillustrates an example of forming interconnects in and over a dielectric layer.

In some implementations, several dielectric layers (e.g.,822) and several interconnects (e.g.,814) may be formed in and over the dielectric layers. Stages2-8ofFIGS.8A-8Billustrate examples of forming at least one dielectric layer and a plurality of interconnects in and over the dielectric layer(s).

The method forms (at925) a solder resist layer over the at least one dielectric layer (e.g.,220) and the at least one interconnect222. A deposition process may be used to form the solder resist layer(s).

Different implementations may use different processes for forming the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and/or a physical vapor deposition (PVD) process may be used for forming the metal layer(s). For example, a sputtering process, a spray coating process, and/or a plating process may be used to form the metal layer(s).

Exemplary Sequence for Fabricating a Package that Includes a Substrate, an Integrated Device and Wire Bonds Configured as a Heat Spreader

FIGS.10A-10Cillustrate an exemplary sequence for providing or fabricating a package that includes wire bonds configured as a heat spreader. In some implementations, the sequence ofFIGS.10A-10Cmay be used to provide or fabricate the package200ofFIG.2, or any of the packages described in the disclosure.

It should be noted that the sequence ofFIGS.10A-10Cmay combine one or more stages in order to simplify and/or clarify the sequence for providing or fabricating the package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted without departing from the spirit of the disclosure. The sequence ofFIGS.10A-10Cmay be used to fabricate one package or several packages at a time (as part of a wafer).

Stage1, as shown inFIG.10A, illustrates a state after a substrate202is provided. The substrate202may be provided by a supplier or fabricated. A process similar to the process shown inFIGS.8A-8Bmay be used to fabricate the substrate202. However, different implementations may use different types of substrate and/or may use different processes to fabricate a substrate. Examples of processes that may be used to fabricate a substrate include a semi-additive process (SAP) and a modified semi-additive process (mSAP).

The substrate202includes a first surface (e.g., top surface) and a second surface (e.g., bottom surface). The substrate202includes at least one dielectric layer220and a plurality of interconnects222. The plurality of interconnects222is located at least in and over the at least one dielectric layer220. As mentioned above, the substrate202may include a solder resist layer on the first surface and another solder resist layer on the second surface of the substrate202.

Stage2illustrates a state after the back side of the integrated device206is coupled to the first surface (e.g., top surface) of the substrate202. The integrated device206may be coupled to the substrate202through an attach260(e.g., die attach). The integrated device206may include a power amplifier.

Stage3illustrates a state after a plurality of wire bonds are formed and coupled to the integrated device206and/or the substrate202. A wire bonding process may be used to couple the plurality of first wire bonds210to the integrated device206and the substrate202. The plurality of first wire bonds210may be coupled to interconnects (e.g.,320a) of the integrated device206and interconnects (e.g.,222) of the substrate202. For example, the plurality of first wire bonds210may be coupled to pads of the integrated device206and pads of the substrate202. The wire bonding process may further be used to couple at least one second wire bond212to the integrated device206. For example, the at least one second wire bond212may be coupled to pads of the integrated device206. The at least one second wire bond212may travel and/or extend in different directions (e.g., vertically, diagonally, curved, non-linearly), as illustrated and described in at leastFIGS.6and7above.

Stage4, as shown inFIG.10B, illustrate a state after the encapsulation layer208is formed over the first surface of the substrate202such that the encapsulation layer208encapsulates the integrated device206, the plurality of first wire bonds210and the at least one second wire bond212. The encapsulation layer208may include a mold, a resin and/or an epoxy. The process of forming and/or disposing the encapsulation layer208may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

Stage5illustrates a state after portions of the encapsulation layer208and portions of the at least one second wire bond212are removed. A grinding process (e.g., strip grinding process) may be used to remove portions of the encapsulation layer208and portions of the at least one second wire bond212. A top portion of the at least one second wire bond212may be co-planar with a top surface (e.g., top outer surface) of the encapsulation layer208.

Stage6, as shown inFIG.10C, illustrates a state after the metal layer230is formed over the outer surface of the encapsulation layer208and the side surface of the substrate202. The metal layer230may be configured as an EMI shield (e.g., means for electromagnetic interference (EMI) shield). A sputtering process, a spray coating, and/or a plating process may be used to form the metal layer230. The metal layer230may include an electrically conductive layer. The metal layer230may be formed over and coupled to the at least second wire bond212. The metal layer230may be configured to be coupled to ground.

Stage7illustrates a state after the plurality of solder interconnects240is coupled to the plurality of interconnects222through a reflow process. The plurality of solder interconnects240may be coupled to the second surface (e.g., bottom surface) of the substrate202. Stages6and/or7may illustrate the package200.

The packages (e.g.,200,400,600,700) described in the disclosure may be fabricated one at a time or may be fabricated together as part of one or more wafers and then singulated into individual packages.

Exemplary Flow Diagram of a Method for Fabricating a Package That Includes a Substrate, an Integrated Device and Wire Bonds Configured as a Heat Spreader

In some implementations, fabricating a package that includes wire bonds as a heat spreader includes several processes.FIG.11illustrates an exemplary flow diagram of a method1100for providing or fabricating a package that includes wire bonds as a heat spreader. In some implementations, the method1100ofFIG.11may be used to provide or fabricate the package200ofFIG.2described in the disclosure. However, the method1100may be used to provide or fabricate any of the packages described in the disclosure.

It should be noted that the method ofFIG.11may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating a package. In some implementations, the order of the processes may be changed or modified.

The method provides (at1105) a substrate (e.g.,202). The substrate202may be provided by a supplier or fabricated. The substrate202includes a first surface (e.g., top surface) and a second surface (e.g., bottom surface). The substrate202may include at least one dielectric layer220and a plurality of interconnects222. The plurality of interconnects222is located at least in and over the at least one dielectric layer220.

Different implementations may provide different substrates. A process similar to the process shown inFIGS.8A-8Bmay be used to fabricate the substrate202. However, different implementations may use different types of substrate and may use different processes to fabricate the substrate202. Stage1ofFIG.10Aillustrates and describes an example of providing a substrate.

The method couples (at1110) at least one component (e.g., power amplifier, integrated device) to the substrate (e.g.,202). For example, the method may couple the back side of the integrated device206to a first surface (e.g., top surface) of the substrate202through the attach260. Stage2ofFIG.10Aillustrates and describes an example of coupling at least one component to a substrate.

The method forms and couples (at1115) a plurality of wire bonds to the integrated device206and/or the substrate202. A wire bonding process may be used to couple a plurality of first wire bonds210to the integrated device206and the substrate202. The plurality of first wire bonds210may be coupled to interconnects (e.g.,320a) of the integrated device206and interconnects (e.g.,222) of the substrate202. For example, the plurality of first wire bonds210may be coupled to pads of the integrated device206and pads of the substrate202. The wire bonding process may further be used to form and couple at least one second wire bond212to the integrated device206. For example, the at least one second wire bond212may be coupled to pads of the integrated device206. The at least one second wire bond212may travel and/or extend in different directions (e.g., vertically, diagonally, curved, non-linearly). Stage3ofFIG.10Aillustrates and describes an example of forming wire bonds.

The method forms (at1120) an encapsulation layer (e.g.,208) over the first surface of the substrate (e.g.,202). The encapsulation layer may be formed over the first surface of the substrate such that the encapsulation layer208encapsulates the integrated device206, the plurality of first wire bonds210and the at least one second wire bond212. The encapsulation layer may be coupled to the first surface of the substrate. The process of forming and/or disposing the encapsulation layer208may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage4ofFIG.10B, illustrates and describes an example of an encapsulation layer that is located over the substrate and encapsulates the integrated device and wire bonds.

The method removes (at1125) portions of the encapsulation layer208and portions of the at least one second wire bond212. A grinding process (e.g., strip grinding process) may be used to remove portions of the encapsulation layer208and portions of the at least one second wire bond212. However, different implementations may use different processes for removing portion of the encapsulation layer and/or portions of the at least one second wire bond. Stage5ofFIG.10Billustrates and describes an example of portions of the encapsulation layer and portions of wire bonds that are removed.

The method forms (at1130) a metal layer230over the outer surface of the encapsulation layer208and the side surface of the substrate202. The metal layer230may be configured as an EMI shield. A sputtering process, a spray coating, and/or a plating process may be used to form the metal layer230. The metal layer230may include an electrically conductive layer. The metal layer230may be formed and coupled to the at least second wire bond212. The metal layer230may be configured to be coupled to ground. Stage6ofFIG.10Cillustrates and describes an example of a metal layer formed over an encapsulation layer and configured as an EMI shield.

The method may couple a plurality of solder interconnects (e.g.,240) to the substrate (e.g.,202). A reflow process may be used to couple the solder interconnects240to the plurality of interconnects222of the substrate202. Stage8ofFIG.10Cillustrates and describes an example of coupling solder interconnects to a substrate.

Exemplary Electronic Devices

FIG.12illustrates various electronic devices that may be integrated with any of the aforementioned device, integrated device, integrated circuit (IC) package, integrated circuit (IC) device, semiconductor device, integrated circuit, die, interposer, package, package-on-package (PoP), System in Package (SiP), or System on Chip (SoC). For example, a mobile phone device1202, a laptop computer device1204, a fixed location terminal device1206, a wearable device1208, or automotive vehicle1210may include a device1200as described herein. The device1200may be, for example, any of the devices and/or integrated circuit (IC) packages described herein. The devices1202,1204,1206and1208and the vehicle1210illustrated inFIG.12are merely exemplary. Other electronic devices may also feature the device1200including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the components, processes, features, and/or functions illustrated inFIGS.2-7,8A-8B,9,10A-10C and/or11-12may be rearranged and/or combined into a single component, process, feature or function or embodied in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from the disclosure. It should also be notedFIGS.2-7,8A-8B,9,10A-10C and/or11-12and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations,FIGS.2-7,8A-8B,9,10A-10C and/or11-12and its corresponding description may be used to manufacture, create, provide, and/or produce devices and/or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipating device and/or an interposer.

It is noted that the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be exemplary. In some implementations, various components and/or parts in the figures may be optional.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another—even if they do not directly physically touch each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electrical current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electrical current traveling between the two objects. The use of the terms “first”, “second”, “third” and “fourth” (and/or anything above fourth) is arbitrary. Any of the components described may be the first component, the second component, the third component or the fourth component. For example, a component that is referred to a second component, may be the first component, the second component, the third component or the fourth component. The term “encapsulating” means that the object may partially encapsulate or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component that is located on top may be located over a component that is located on a bottom. A top component may be considered a bottom component, and vice versa. As described in the disclosure, a first component that is located “over” a second component may mean that the first component is located above or below the second component, depending on how a bottom or top is arbitrarily defined. In another example, a first component may be located over (e.g., above) a first surface of the second component, and a third component may be located over (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. It is further noted that the term “over” as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (1) the first component is over the second component, but not directly touching the second component, (2) the first component is on (e.g., on a surface of) the second component, and/or (3) the first component is in (e.g., embedded in) the second component. A first component that is located “in” a second component may be partially located in the second component or completely located in the second component. The term “about ‘value X’”, or “approximately value X”, as used in the disclosure means within 10 percent of the ‘value X’. For example, a value of about 1 or approximately 1, would mean a value in a range of 0.9-1.1.

In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a redistribution metal layer, and/or an under bump metallization (UBM) layer. In some implementations, an interconnect is an electrically conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground and/or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and/or sequences for forming the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and/or a plating process may be used to form the interconnects.