IC chip package disabling device

A chip package comprises: an IC substrate, wherein the IC substrate comprises at least one electronic device; a photovoltaic cell, wherein the photovoltaic cell generates an electrical current when exposed to light; a light blocking shield, wherein the light blocking shield prevents light from striking the photovoltaic cell only while the chip package is mounted on a circuit board, and wherein the light blocking shield ceases to prevent light from striking the photovoltaic cell upon the chip package being dismounted from the circuit board; and a disabling logic, wherein the electrical current, which is generated by the photovoltaic cell in response to the chip package being dismounted from the circuit board, causes the disabling logic to disable the IC substrate.

BACKGROUND

The present disclosure relates to the field of integrated circuits (ICs), and specifically to ICs packaged within chip packages. Still more particularly, the present disclosure relates to a device for disabling ICs within chip packages.

An integrated circuit (IC) is a set of electronic components, such as transistors, diodes, resistors, etc. on a small plate of semiconductor material, such as silicon. An IC, also called a “chip”, is typically contained within a package of ceramic or plastic material known as a chip package (also called an “IC package” or an “IC chip package”).

SUMMARY

In an embodiment of the present invention, a chip package comprises: an IC substrate, wherein the IC substrate comprises at least one electronic device; a photovoltaic cell, wherein the photovoltaic cell generates an electrical current when exposed to light; a light blocking shield, wherein the light blocking shield prevents light from striking the photovoltaic cell only while the chip package is mounted on a circuit board, and wherein the light blocking shield ceases to prevent light from striking the photovoltaic cell upon the chip package being dismounted from the circuit board; and a disabling logic, wherein the electrical current, which is generated by the photovoltaic cell in response to the chip package being dismounted from the circuit board, causes the disabling logic to disable the IC substrate.

In an embodiment of the present invention, a computer system comprises: a system bus; a chip package electrically coupled to the system bus, wherein the chip package comprises: an IC substrate, wherein the IC substrate comprises at least one electronic device; a photovoltaic cell, wherein the photovoltaic cell generates an electrical current when exposed to light; a light blocking shield, wherein the light blocking shield prevents light from striking the photovoltaic cell only while the chip package is mounted on a circuit board, and wherein the light blocking shield ceases to prevent light from striking the photovoltaic cell upon the chip package being dismounted from the circuit board; and a disabling logic, wherein the electrical current, which is generated by the photovoltaic cell in response to the chip package being dismounted from the circuit board, causes the disabling logic to disable the IC substrate.

In an embodiment of the present invention, a chip package comprises: an IC substrate, wherein the IC substrate comprises at least one electronic device; a disabling post assembly, wherein the disabling post assembly comprises: a post cap; a post connected to the post cap, wherein the post cap is connected to a first end of the post, wherein the post traverses through a post channel in the IC substrate, and wherein the post cap is initially positioned above the IC substrate; a post base connected to a second end of the post, wherein the post base is connected to a surface of a circuit board to which the chip package is electrically connected, wherein the post cap is physically pulled through the IC substrate while the chip package is subsequently removed from the circuit board, and wherein removing the chip package causes the post cap to physically destroy the IC substrate.

DETAILED DESCRIPTION

The present invention is directed to disabling IC chips if they are removed from a circuit board. For example, some government agencies require that all programmable parts on a server board be erased or secured before leaving their facility for either return or repair. If a server board does get out of the facility without this action being taken, chips could be removed from the board and read using a device reader/programmer. Thus, the present invention provides a layer of code security at the chip package level, either by using a photovoltaic cell that is activated when the chip package is removed from the server board, or by a physical post system that physically damages the chip inside the chip package when the chip package is removed from a circuit board, such that the contents of the chip package are unreadable and thus secure. Note that in one or more embodiments of the present invention, the IC chip (e.g., IC substrate104/304described below) is disabled by electricity generated by a photovoltaic cell, not by direct exposure to ultraviolet or other electromagnetic light shining on the elements of the IC chip itself.

With reference now to the figures, and specifically toFIG. 1, an exemplary chip package102, in accordance with one or more embodiments of the present invention, is presented. Chip package102is a chip package that is encased within a body made of ceramic, plastic, etc. Within the chip package102is an IC substrate104. In various embodiments, IC substrate104(e.g., silicon) creates an IC circuit that has one or more electronic components, such as transistors, diodes, resistors, capacitors, induction coils, etc. Together these electronic components make up a processor, an application specific integrated circuit (ASIC), a memory (e.g., volatile memory such as a random access memory (RAM), or nonvolatile memory such as a read only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), etc.).

As depicted inFIG. 1and in an embodiment of the present invention, the chip package102includes a photovoltaic cell (PVC)106. PVC106incorporates photodiodes that convert light into electrical current. As known to those skilled in the art, the photodiodes create an electron-hole pair upon being struck by photons, thus creating electricity according to a physics phenomenon known as the inner photoelectric effect.

As shown inFIG. 1, the chip package102is initially mounted on a circuit board108. Electrical connections are made between the chip package102and its internal components (including, but not limited to, IC substrate104) via pins110that are inserted into socket holes112, which include electrically conductive linings that allow current to flow to circuitry (not shown) within the circuit board108. The connection between the pins110and the socket holes112may be via mechanical clamping mechanisms (not shown), or by soldering the pints110to the socket holes112. In the case of a ball grid array (BGA) device, this connection is made by melting the solder balls on the BGA directly onto the circuit board108.

As depicted inFIG. 1, while the pins110are mated into the socket holes112, thereby mounting the chip package102to the circuit board108, the opening to the PVC106is blocked, thereby preventing light from reaching the photodiodes within the PVC106such that the PVC106produces no (or at least minimal) electricity. This light occlusion/blockage may be due to the close proximity between circuit board108and the chip package102while mated together (thereby blocking any ambient light), and/or the light occlusion/blockage may be enhanced by a light collar114, which provides a circumferential barrier around the PVC106. In an embodiment of the present invention, this light collar114is a cap that is affixed to either the bottom of the chip package102or to the top of the circuit board108.

As depicted, the chip package102includes a disabling logic116, a memory erasing logic118, and/or a system disabling logic120. In order to understand how these components work according to one or more embodiments of the present invention, reference is now made toFIG. 2, which illustrates the chip package102inFIG. 1after it has been removed (decoupled) from the circuit board108.

As shown inFIG. 2, removing the chip package102from the circuit board108(e.g., by desoldering the pins110or otherwise disengaging pins110from socket holes112) exposes the PVC106to an ambient light source202, which may be ambient room lighting. When the ambient light source202strikes the photodiodes within the PVC106, an electrical current is generated. This electrical current is sent to disabling logic116.

In an embodiment of the present invention, disabling logic116transfers the current from the PVC106to the IC substrate104. If the current/voltage is high enough (depending on the design of the PVC106), this current/voltage/power will be enough to “fry” the circuitry within the IC substrate104(e.g., cause permanent damage by overloading the circuitry to the point of irrevocably damaging transistors, diode, etc.). However, if the PVC106does not produce adequate power to permanently damage the IC substrate104, then a voltage transformer122within the disabling logic116will boost the voltage level to that which will permanently damage the IC substrate104by exceeding its voltage rating. For example, if the IC substrate104uses 5.0VDC, then pushing 25VDCthrough the IC substrate104will cause irreversible damage to the IC substrate104, thereby rendering the IC substrate104unusable.

In an embodiment of the present invention, the disabling logic116is logic that is more subtle in how it disables the IC substrate. In this embodiment, the disabling logic116is powered up by electricity from the PVC106(which is generated only when the chip package102is removed from the circuit board108). This allows the disabling logic116to reconfigure, rather than “fry”, the IC substrate104to the point that is it disabled. For example, assume that the IC substrate is an electrically erasable programmable read only memory (EEPROM). Power from the PVC106causes the disabling logic116to direct the memory erasing logic118to set a protection bit in the EEPROM. Initially, the EEPROM remains functionally intact, and data stored within the EEPROM is still present. However, when the chip package102is subsequently powered up (e.g., by being plugged into another circuit board), the protection bit directs the EEPROM to be erased, thus removing all data from the EEPROM. Thus, the power from the PVC106does not directly erase the contents of the EEPROM. Rather, the PVC106activates the disabling logic116, which sets the protection bit for subsequent use.

In another embodiment of the present invention, assume that the IC substrate104is a processor. In this embodiment, the system disabling logic120prevents the processor from operating, both immediately upon being removed from the circuit board108and upon being reinstalled on another circuit board. In an embodiment of the present invention, the system disabling logic120is a power switch to the processor, which is permanently set to the “off” position (i.e., creates a permanent break in a power line between the IC substrate104/processor and a power supply) by the power from the PVC106. For example, the system disabling logic120may include a power fuse (not shown) that, when hit by power from the PVC106, melts, thereby permanently preventing power from reaching the processor.

In another embodiment of the present invention, the system disabling logic120drives a voltage spike through the processor. As with the EEPROM described above, this voltage spike permanently disables the processor by permanently damaging (i.e., “frying”) circuitry within the processor (e.g., by melting certain circuits, permanently “blowing” transistors by exceeding their voltage ratings, etc.). This voltage spike may be generated directly by the PVC106(if powerful enough), or it may be generated through the use of the voltage transformer122found in the disabling logic116.

Thus,FIG. 1andFIG. 2depict a chip package that permanently disables a circuitry upon a photovoltaic cell being exposed to ambient light. One embodiment of the present invention is a chip package that comprises: an IC substrate (e.g., IC substrate104). This IC substrate comprises at least one electronic device, such as a memory cell, a transistor, a diode, a resistor, a capacitor, an internal connection wiring, etc. A photovoltaic cell (e.g., PVC106) within the chip package generates an electrical current when exposed to light and/or other light on the electromagnetic spectrum. A light blocking shield prevents light from striking the photovoltaic cell only while the chip package is mounted on a circuit board (e.g., circuit board108), and the light blocking shield ceases to prevent light from striking the photovoltaic cell upon the chip package being dismounted from the circuit board. This light blocking shield may be effectuated just by the lack of space between the chip package and the circuit board while the chip package is mounted on the circuit board (thus preventing light from entering between the chip package and the circuit board), and/or the light blocking shield may be (or may be augmented by) a light collar (e.g., light collar114).

With reference now toFIG. 3, a chip package302that has a disabling device (i.e., a disabling post assembly) that mechanically destroys an IC substrate304within the chip package302is presented. As shown, the disabling device (disabling post assembly) includes a post320, which traverses through a post channel322through the IC substrate304. IC substrate304is analogous to the IC substrate104shown inFIG. 1, with the stipulation that the post channel322cuts through a section of the IC substrate304that has no useful circuitry, components, etc. Affixed to a first end of the post320is a post cap324. Affixed to a second end of the post320is a post base326. When the chip package302is mounted onto the circuit board308(e.g., by inserting pins310into socket holes312), the post base326presses against an adhesive328. This causes the post base326to be permanently affixed to the circuit board. In an alternative embodiment, the post base326locks into an interlocking dock (not shown), which preferably cannot be disengaged without damaging the chip package302.

As shown inFIG. 4, when the chip package302is physically removed from the circuit board308, the post base326remains affixed to the circuit board308by the adhesive328. The physical/mechanical movement of the chip package302causes the post cap324to be pulled through functional components of the IC substrate404, which is now destroyed (i.e., is physically damaged to the point that it is no longer able to be used at all). If the IC substrate404was a memory, then this physical destruction ensures that the data that was once stored thereon can never be recovered. Similarly, if the IC substrate404was a processor, the physical destruction of the processor ensures that the processor will never again be functional, since it is now reduced to broken pieces.

Thus,FIG. 3andFIG. 4depict a chip package that contains an IC substrate (initially IC substrate304inFIG. 3and subsequently destroyed IC substrate404inFIG. 4). The IC substrate comprises at least one electronic device, such as a memory cell, a transistor, a diode, a resistor, a capacitor, an internal connection wiring, etc.

A disabling post assembly comprises a post cap (e.g., post cap324); a post (e.g., post320) connected to the post cap, wherein the post cap is connected to a first end of the post, wherein the post traverses through a post channel (e.g., post channel322) in the IC substrate, and wherein the post cap is initially positioned above the IC substrate. (Note that terms such as “above” and “below” are not intended to connote altitude, but rather are used vernacularly to describe the relative positions depicted in the figures.)

As shown inFIG. 3andFIG. 4, a post base (e.g., post base326) is connected to a second end of the post, wherein the post base is connected to a surface of a circuit board (e.g., circuit board308) to which the chip package is electrically connected (e.g., via pins310mating with socket holes312), wherein the post cap is physically pulled through the IC substrate while the chip package is subsequently removed from the circuit board, and wherein removing the chip package causes the post cap to physically destroy the IC substrate. The IC substrate may be a processor, a memory, or any other IC device.

With reference now toFIG. 5, there is depicted a block diagram of an exemplary computer502in which the presently-described chip packages may be utilized. In the context of the present invention, chip packages102/302that may be permanently disabled as described herein may be the processor504and/or the memory520depicted inFIG. 5and/or any other chip package coupled to a circuit board within computer502.

Exemplary computer502includes processor504that is coupled to a system bus506. Processor504may utilize one or more processors, each of which has one or more processor cores. System bus506is coupled via a bus bridge508to an input/output (I/O) bus510. An I/O interface512is coupled to I/O bus510. I/O interface512affords communication with various I/O devices via various ports (not shown). While the format of the ports connected to I/O interface512may be any known to those skilled in the art of computer architecture, in one embodiment some or all of these ports are universal serial bus (USB) ports. Power is supplied to computer502by a power source514, which may incorporate an AC/DC converter to provide the requisite DC power needed by components of the computer502.

A hard drive interface516is also coupled to system bus506. Hard drive interface516interfaces with a hard drive518. In one embodiment, hard drive518populates a system memory, such as memory520. Memory520may be any IC device capable of storing data, including but not limited to single in-line memory modules (SIMMS), dual in-line memory modules (DIMMS), erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), volatile random access memory (RAM), etc.

Note that the hardware elements depicted in computer502are not intended to be exhaustive, but rather are representative to highlight essential components required by the present invention.