STACKED STRUCTURE INCLUDING CONDUCTIVE PATTERN FOR SELF-ALIGNMENT

A stacked structure includes a lower substrate and a first semiconductor chip stacked on an upper surface of the lower substrate, the lower substrate includes a lower conductor pattern disposed on the upper surface of the lower substrate, the first semiconductor chip may have first and second surfaces facing each other, the second surface of the first semiconductor chip may face the upper surface of the lower substrate, and the first semiconductor chip may include a first conductor pattern disposed on the second surface. The first conductor pattern may be aligned with the lower conductor pattern in a first direction perpendicular to the upper surface of the lower substrate, and the first conductor pattern may be spaced apart from the lower conductor pattern in the first direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No.10-2023-0070894, filed on Jun. 1, 2023, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to a stacked structure including conductor patterns used for self-alignment by magnetic force.

BACKGROUND

An assembling process on a board or a package productor that packages multiple devices includes measuring a fiducial marker formed on a substrate to determine displacement and moving a device to a corresponding coordinate through motor control to mount the device. However, in the case of large-area, thin, and composite material products, non-linearity occurs due to warpage and thermal deformation, thereby decreasing precision.

SUMMARY

An object of the present disclosure is to provide a stacked structure including a conductor pattern for self-alignment.

The problem to be solved by the present disclosure is not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In general, aspects of the subject matter described in this specification can be embodied in stacked structure including: a lower substrate and a first semiconductor chip stacked on an upper surface of the lower substrate, and the lower substrate may include a lower conductor pattern disposed on the upper surface of the lower substrate. The first semiconductor chip may have first and second surfaces facing each other, and the second surface of the first semiconductor chip may face the upper surface of the lower substrate, and the first semiconductor chip may include a first conductor pattern disposed on the second surface. The first conductor pattern may be aligned with the lower conductor pattern in a first direction perpendicular to the upper surface of the lower substrate, and the first conductor pattern may be spaced apart from the lower conductor pattern in the first direction.

Another general aspect can be embodied in a stacked structure that includes: a lower semiconductor chip and a first semiconductor chip stacked on an upper surface of the lower semiconductor chip, the lower semiconductor chip may include a lower conductor pattern disposed on the upper surface, the first semiconductor chip may have first and second surfaces facing each other, and the second surface of the first semiconductor chip may face the upper surface of the lower semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, second chip pads disposed on a first surface of the first semiconductor substrate, first through electrodes penetrating the first semiconductor substrate and respectively connected to the second chip pads, a first circuit layer disposed on a lower surface of the first semiconductor substrate, a first conductor pattern and first chip pads disposed on the second surface of the first semiconductor chip, and first bumps respectively disposed on the first chip pads, the first conductor pattern may be aligned with the lower conductor pattern in a first direction perpendicular to the upper surface of the lower semiconductor chip, the first conductor pattern may be spaced apart from the lower conductor pattern in the first direction, and the lower semiconductor chip and the first semiconductor chip may be connected to each other through the first bumps.

Another general aspect can be embodied in a stacked structure that includes: a lower substrate, and a semiconductor structure stacked on an upper surface of the lower substrate, the lower substrate may include a lower conductor pattern disposed on the upper surface of the lower substrate, the semiconductor structure may have upper and lower surfaces facing each other, and the lower surface of the semiconductor structure faces the upper surface of the lower substrate. The semiconductor structure may include a conductor pattern disposed on the lower surface, the conductor pattern may be aligned with the lower conductor pattern in a first direction perpendicular to the upper surface of the lower substrate, the conductor pattern may be spaced apart from the lower conductor pattern in the first direction, the conductor pattern may include a first coil pad and a second coil pad horizontally spaced apart from each other and a line portion connecting the first coil pad and the second coil pad, the line portion may have a coil shape surrounding the second coil pad, and the semiconductor structure may be a semiconductor package or a semiconductor chip.

DETAILED DESCRIPTION

FIG.1is a plan view of a lower substrate.FIGS.2A to2Care plan views illustrating a shape of a lower conductor pattern ofFIG.1. InFIG.1, some components are omitted for simplicity.

Referring toFIG.1, a lower substrate1000may include lower conductor patterns A and B. The lower conductor patterns A and B may be disposed on a peripheral1000SD of the lower substrate1000. Although the example inFIG.1depicts both lower conductor patterns A and B disposed on a peripheral1000SD of the lower substrate1000, the present disclosure is not limited to what is shown. In some implementations, there is only one of the lower conductor patterns A and B.

The lower conductor patterns A and B may include metal. The lower conductor patterns A and B may include, for example, copper, aluminum, tungsten, titanium, gold, silver, or the like, or alloys thereof. A ferromagnetic material such as iron, nickel, or cobalt may be included to enhance magnetic force generated when current is applied.

Referring toFIGS.2A and2B, the first lower conductor pattern A may have a meander-shape, an undulating shape, zigzag shape, or the like. In detail, the first lower conductor pattern A has a first pad portion PAD1and a second pad portion PAD2spaced apart from each other in a second direction D2parallel to the upper surface of the lower substrate1000and includes a line portion LN extending in the second direction D2between the first pad portion PAD1and the second pad portion PAD2. The line portion LN may extend in a zigzag shape in a third direction D3parallel to the upper surface of the lower substrate1000and crossing the second direction D2. The line portion LN may have a first side surface Aa and a second side surface Ab that face each other along the third direction D3. The line portion LN may include second holes H2and a fourth hole H4having a bar shape extending from the first side surface Aa to the second side surface Ab and may include a first hole H1and third holes H3having a bar shape extending from the second side surface Ab to the first side surface Aa. The second holes H2and the third holes H3may be alternately disposed in the second direction D2. The second holes H2may have a first portion H2aadjacent to the first side surface Aa and a second portion H2badjacent to the second side surface Ab of the line portion LN, and the third holes H3may have a third portion H3aadjacent to the first side surface Aa and a fourth portion H3badjacent to the second side surface Ab of the line portion LN. The first portion H2aand the second portion H2bof the second holes H2may each have a first width L1and a second width L2in the second direction D2, and the third portion H3aand the fourth portion H3bof the third holes H3may each have a third width L3and a fourth width L4in the second direction D2. The second holes H2may have a shape in which the first width L1is smaller than the second width L2, and the third holes H3may have a shape in which the third width L3is greater than the fourth width L4. For example, referring toFIG.2A, the second width L2of the second holes H2and the third width L3of the third holes H3may be kept constant in the second direction D2. As another example, referring toFIG.2B, the second width L2of the second holes H2and the third width L3of the third holes H3may increase in the second direction D2. That is, a pitch of the lower conductor pattern A may increase in the second direction D2. However, the pitch and shape of the lower conductor pattern A is not limited to the illustrated inFIGS.2A and2B. In addition, the lower conductor pattern A may have a shape extending in the third direction D3instead of the second direction D2.

When a current is applied to the lower conductor pattern A, a magnetic field may be generated, and accordingly, chips on which the lower conductor patterns are formed or the chip and the substrate may be self-aligned with each other due to a magnetic force applied therebetween. As illustrated inFIG.2B, in the case of the lower conductor patterns A having different pitches, when a current is applied to the lower conductor patterns A, a strength of a magnetic field may be different, and thus the chips on which the lower conductor patterns are formed or the chip and the substrate may be self-aligned with each other in a sliding manner due to a magnetic force differently applied therebetween.

Referring toFIG.2C, the lower conductor pattern B may have a coil shape. As illustrated, for example, the coil shape can include a square spiral with right angle turns. In detail, the lower conductor pattern B may include a first coil pad CP1and a second coil pad CP2spaced apart from each other in the second direction D2and the third direction D3, and may include a line portion CL connecting the first coil pad CP1and the second coil pad CP2. The line portion CL may be disposed to surround the second coil pad CP2when viewed in a plan view. When a current is applied through the first coil pad CP1and the second coil pad CP2, a magnetic field may be formed at a center of the lower conductor pattern B, and thus the chips on which the lower conductor patterns B are formed or the chip and the substrate may be self-aligned with each other due to a magnetic force applied therebetween. However, the shape of the lower conductor pattern B may have a shape different from that described above without being limited to the illustrated inFIG.2C.

According to the present disclosure described above, the chips on which the lower conductor patterns A and B are formed or the chip and the substrate may be self-aligned with each other due to the magnetic force. Accordingly, a separate optical measurement step is unnecessary, and warpage or nonlinear deformation due to thermal deformation may be prevented even in the case of large-area, thin, composite products.

FIG.3is a cross-sectional view illustrating an example of self-alignment by magnetic force when a lower substrate and a semiconductor chip are stacked. For simplicity of description, descriptions overlapping those described with reference toFIGS.1to2Care omitted.

Referring toFIG.3, lower conductor patterns1100and first substrate pads1200may be provided on an upper surface1000aof a lower substrate1000. Although not shown, the lower conductor patterns1100may be electrically connected to external terminals, through which current may be applied to the lower conductor patterns1100.

A first semiconductor chip200A which is stacked on the upper surface1000aof the lower substrate1000in a first direction D1perpendicular to the upper surface1000aof the lower substrate1000may be provided. The first semiconductor chip200A may have a first surface200Aaand a second surface200Abthat face each other in the first direction D1, and the second surface200Abof the first semiconductor chip200A may face the upper surface1000aof the lower substrate1000. First conductor patterns270A may be disposed on the second surface200Abof the first semiconductor chip200A. Although not shown, the first conductor patterns270A may be electrically connected to external terminals, through which current may be applied to the first conductor patterns270A. A current may be applied to the lower conductor patterns1100and the first conductor patterns270A to generate a magnetic field, and accordingly, the lower conductor patterns1100and the first conductor patterns270A may be aligned with each other in the first direction D1by magnetic force. When the first conductor patterns270A are aligned with the lower conductor patterns1100, the first conductor patterns270A may be spaced apart from the lower conductor patterns1100in the first direction D1.

The lower conductor patterns1100and the first conductor patterns270A may have substantially the same shape as the lower conductor patterns A and B described above with reference toFIGS.2A to2C. However, the present disclosure is not limited thereto, and the lower conductor patterns1100and the first conductor patterns270A may have shapes different from those described above.

The first semiconductor chip200A may include a first semiconductor substrate210A, the aforementioned first conductor pattern270A, first chip pads240A disposed on the second surface200Abof the first semiconductor chip200A, and first bumps250A respectively disposed on the first chip pads240A. The first bumps250A may be respectively connected to the first substrate pads1200of the lower substrate1000. The first semiconductor chip200A may be electrically connected to the lower substrate1000through first chip pads240A, first bumps250A, and first substrate pads1200.

FIGS.4A to4Care cross-sectional views illustrating lower substrates aligned with a semiconductor chip. For simplicity of description, descriptions overlapping with those described above are omitted.

Referring toFIG.4A, the lower substrate1000described with reference toFIG.3may be a redistribution substrate500. The first semiconductor chip200A may be stacked on an upper surface1000aof the redistribution substrate500. The upper surface1000aof the redistribution substrate500may correspond to the upper surface1000aof the lower substrate1000described with reference toFIG.3. The redistribution substrate500may include a redistribution insulating layer510, redistribution patterns520disposed in the redistribution insulating layer510, first redistribution pads550and second redistribution pads530connected to the redistribution patterns520, and redistribution bumps540each disposed on the second redistribution pads530.

The redistribution patterns520may include a metal such as copper, aluminum, titanium, or tungsten, and the redistribution insulating layer510may include a photo-imageable dielectric material. The first and second redistribution pads550and530may be electrically connected to corresponding redistribution patterns520. The first and second redistribution pads550and530may include a conductive material (e.g., metal). The redistribution bumps540may include a conductive material (e.g., metal) and may have a shape of at least one of a solder ball, a bump, and a pillar.

The lower conductor patterns1100and the first substrate pads1200may be disposed on the upper surface1000aof the redistribution substrate500. The lower conductor patterns1100may be aligned with the first conductor patterns270A of the first semiconductor chip200A in the first direction D1by the magnetic force F. When the first conductor patterns270A are aligned with the lower conductor patterns1100, the first conductor patterns270A may be spaced apart from the lower conductor patterns1100in the first direction D1. The first bumps250A of the first semiconductor chip200A may be respectively connected to the first substrate pads1200. The first semiconductor chip200A may be electrically connected to the redistribution substrate500through first chip pads240A, first bumps250A, and first substrate pads1200.

Referring toFIG.4B, the lower substrate1000described with reference toFIG.3may be an interposer substrate600. The first semiconductor chip200A may be stacked on the upper surface1000aof the interposer substrate600. The upper surface1000aof the interposer substrate600may correspond to the upper surface1000aof the lower substrate1000described with reference toFIG.3. The interposer substrate600may include a first base substrate610, a wiring layer620on the first base substrate610, first substrate pads1200on the wiring layer620, a plurality of through electrodes630penetrating the first base substrate610, second substrate pads640respectively connected to the plurality of through electrodes630, and first base bumps650respectively disposed on the second substrate pads640.

The first base substrate610may be, for example, a silicon substrate.

The plurality of through electrodes630may be horizontally spaced apart from each other within the first base substrate610. The plurality of through electrodes630may include, for example, a metal such as copper. The wiring layer620may be adjacent to the upper surface1000aof the interposer substrate600and may include metal patterns electrically connected to the plurality of through electrodes630. The first substrate pads1200may be disposed on the upper surface1000aof the interposer substrate600and may be electrically connected to the metal patterns in the wiring layer620. The second substrate pads640may be disposed on a lower surface of the first base substrate610. The second substrate pads640may be electrically connected to the through electrodes630, respectively. The second substrate pads640may include a conductive material (e.g., metal). The first base bumps650may include a conductive material (e.g., metal) and may have a shape of at least one of a solder ball, a bump, and a pillar.

The lower conductor patterns1100and the first substrate pads1200may be disposed on the upper surface1000aof the interposer substrate600. The lower conductor patterns1100may be aligned with the first conductor patterns270A of the first semiconductor chip200A in the first direction D1by the magnetic force F. When the first conductor patterns270A are aligned with the lower conductor patterns1100, the first conductor patterns270A may be spaced apart from the lower conductor patterns1100in the first direction D1. The first bumps250A of the first semiconductor chip200A may be respectively connected to the first substrate pads1200. The first semiconductor chip200A may be electrically connected to the interposer substrate600through first chip pads240A, first bumps250A, and first substrate pads1200.

Referring toFIG.4C, the lower substrate1000described with reference toFIG.3may be a printed circuit board. The first semiconductor chip200A may be stacked on the upper surface1000aof the second base substrate700. The upper surface1000aof the second base substrate700may correspond to the upper surface1000aof the lower substrate1000described with reference toFIG.3. The printed circuit board may include a second base substrate700, third substrate pads710disposed on the lower surface of the second base substrate700, and second base bumps720respectively disposed on the third substrate pads710.

The third substrate pads710may include a conductive material (e.g., metal). The second base bumps720may include a conductive material (e.g., metal) and may have a shape of at least one of a solder ball, a bump, and a pillar.

The lower conductor patterns1100and the first substrate pads1200may be disposed on the upper surface1000aof the second base substrate700. The lower conductor patterns1100may be aligned with the first conductor patterns270A of the first semiconductor chip200A in the first direction D1by the magnetic force F. When the first conductor patterns270A are aligned with the lower conductor patterns1100, the first conductor patterns270A may be spaced apart from the lower conductor patterns1100in the first direction D1. The first bumps250A of the first semiconductor chip200A may be respectively connected to the first substrate pads1200. The first semiconductor chip200A may be electrically connected to the printed circuit board through first chip pads240A, first bumps250A, and first substrate pads1200.

FIGS.5A to5Care cross-sectional views illustrating examples of semiconductor chips aligned with a lower substrate. For simplicity of description, descriptions overlapping with those described above are omitted.

Referring toFIG.5A, a first semiconductor chip200A may include a first semiconductor substrate210A, a first circuit layer220A, first through electrodes230A, first chip pads240A, second chip pads260A, and first bumps250A. The first semiconductor substrate210A may be a silicon substrate, a germanium substrate, and/or a silicon-germanium substrate. The first circuit layer220A may include integrated circuits formed on the first semiconductor substrate210A.

The first through electrodes230A may pass through the first semiconductor substrate210A and may be horizontally spaced apart from each other within the first semiconductor substrate210A. The first through electrodes230A may be spaced apart from each other in the second direction D2and may be electrically connected to the first circuit layer220A. The first through electrodes230A may include metal (e.g., copper, tungsten, titanium, tantalum, etc.).

The first chip pads240A may be disposed on a second surface200Abof the first semiconductor chip200A and may be electrically connected to the first circuit layer220A. The first bumps250A may be respectively disposed on the first chip pads240A and may be respectively connected to the first chip pads240A. The second chip pads260A may be disposed on a first surface200Aaof the first semiconductor chip200A and may be respectively connected to the first through electrodes230A. The first and second chip pads240A and260A may include metal (e.g., copper). The first bumps250A may include a conductive material and may have a shape of at least one of a solder ball, a bump, and a pillar.

The first circuit layer220A may include a first sub-circuit layer221A and a second sub-circuit layer222A. A sub-conductor pattern271A may be disposed on a lower surface of the first sub-circuit layer221A. Although not shown, the sub-conductor pattern271A may be electrically connected to external terminals and a current may be applied to the sub-conductor pattern271A. The sub conductor pattern271A may have substantially the same shape as the lower conductor patterns A and B described with reference toFIGS.2A to2C. The first conductor pattern270A and the sub-conductor pattern271A may be included to form a greater magnetic force compared to a case where only the first conductor pattern270A exists, and accordingly, the first semiconductor chips200A may be more easily driven and aligned with each other.

Referring toFIG.5B, the first semiconductor chip200A may include an interlayer circuit layer224A disposed on the lower surface of the first semiconductor substrate210A. A first circuit layer220A may be disposed on a lower surface of the interlayer circuit layer224A, and a shielding layer223A may be interposed between the interlayer circuit layer224A and the first circuit layer220A. The shielding layer223A may include, for example, gold (Au), silver (Ag), copper (Cu), titanium (Ti), tungsten (W), iron (Fe), or tin (Sn). In a process of aligning the first semiconductor chip200A and the lower substrate1000by the magnetic force between the first conductor pattern270A and the lower conductor pattern1100, the shielding layer223A may serve to prevent damage to the semiconductor device caused by the magnetic force.

Referring toFIG.5C, a semiconductor device may include an interlayer circuit layer224A disposed on a lower surface of a first semiconductor substrate210A, and may further include a first circuit layer220A disposed on a lower surface of the interlayer circuit layer224A, and a shielding layer223A interposed between the interlayer circuit layer224A and the first circuit layer220A. The first circuit layer220A may include a first sub-circuit layer221A and a second sub-circuit layer222A, and a sub-conductor pattern271A may be disposed on a lower surface of the first sub-circuit layer221A. In other words, the characteristic components ofFIGS.5A and5Bmay be included together.

FIGS.6A and6Bare cross-sectional views illustrating alignment of a lower substrate and semiconductor chips.FIGS.7A and7Bare cross-sectional views illustrating alignment of semiconductor chips and chips. For simplicity of description, descriptions overlapping with those described above will be omitted.

Referring toFIG.6A, a lower substrate1000may include a plurality of lower semiconductor chips100A. A first semiconductor chip200A may be stacked on the lower semiconductor chip100A in a first direction D1perpendicular to an upper surface of the lower semiconductor chip100A. The first semiconductor chip200A may be substantially the same as that described with reference toFIGS.5A to5C.

The lower semiconductor chip100A may include a lower semiconductor substrate110A, a lower circuit layer120A, lower through electrodes130A, lower chip pads140A, and lower bumps150A. The lower semiconductor substrate110A may be a silicon substrate, a germanium substrate, and/or a silicon-germanium substrate. The lower circuit layer120A may include integrated circuits formed on the lower semiconductor substrate110A.

The lower through electrodes130A may pass through the lower semiconductor substrate110A and may be horizontally spaced apart from each other within the lower semiconductor substrate110A. The lower through electrodes130A may be spaced apart from each other in a second direction D2parallel to the upper surface of the lower semiconductor chip100A. The lower through electrodes130A may be electrically connected to the lower circuit layer120A. The lower through electrodes130A may include metal (e.g., copper, tungsten, titanium, tantalum, etc.).

The lower chip pads140A may be disposed on a lower surface of the lower semiconductor chip100A and may be electrically connected to the lower circuit layer120A. The lower bumps150A may be respectively disposed on the lower chip pads140A and may be respectively connected to the lower chip pads140A. The lower bumps150A may be connected to external terminals. The first substrate pads1200may be disposed on the upper surface of the lower semiconductor chip100A and may be respectively connected to the lower through electrodes130A. The lower chip pads140A may include metal (e.g., copper). The lower bumps150A may include a conductive material and may have a shape of at least one of a solder ball, a bump, and a pillar.

A lower conductor pattern1100may be disposed on an upper surface of the lower semiconductor chip100A. The lower conductor pattern1100may have the shape of the lower conductor patterns A and B described above with reference toFIGS.2A to2C. Although not shown, the lower conductor pattern1100may be electrically connected to external terminals and a current may be applied to the lower conductor pattern1100.

The lower semiconductor chips100A may be provided on a carrier substrate300. An adhesive layer310may be provided between the lower surface of the lower semiconductor chip100A and the carrier substrate300and may be interposed between the lower bumps150A. The lower semiconductor chips100A may be attached to the carrier substrate300by the adhesive layer310.

Referring toFIG.6B, as described above with reference toFIG.3, the first conductor patterns270A and the lower conductor patterns1100may be aligned in the first direction D1by magnetic force, and the first semiconductor chips200A may be stacked on the lower semiconductor chips100A. The first semiconductor chips200A and the lower semiconductor chips100A may be electrically connected through the first bumps250A.

Referring toFIGS.7A and7B, second semiconductor chips200B may be stacked on the first semiconductor chips200A in the first direction D1, respectively.

The first semiconductor chips200A may include upper conductor patterns280A and second chip pads260A disposed on a first surface Aa of the first semiconductor chip200A.

The upper conductor patterns280A may have substantially the same shape as the lower conductor patterns A and B described with reference toFIGS.2A to2C. Although not shown, the upper conductor pattern280A may be electrically connected to external terminals and a current may be applied to the upper conductor pattern280A.

Each of the second semiconductor chips200B may have a third surface200Baand a fourth surface200Bbthat face each other. Each of the second semiconductor chips200B may be provided so that each of the fourth surfaces200Bbof the second semiconductor chips200B face each of the first surfaces200Aaof the first semiconductor chips200A. Each of the second semiconductor chips200B may include a second semiconductor substrate210B, a second circuit layer220B, second through electrodes230B, third chip pads240B, fourth chip pads260B, second conductor patterns270B, and second bumps250B. The second semiconductor substrate210B may be a silicon substrate, a germanium substrate, and/or a silicon-germanium substrate. The second circuit layer220B may include integrated circuits formed on the second semiconductor substrate210B.

The second through electrodes230B may pass through the second semiconductor substrate210B and may be horizontally spaced apart from each other within the second semiconductor substrate210B. The second through electrodes230B may be spaced apart from each other in the second direction D2and may be electrically connected to the second circuit layer220B. The second through electrodes230B may include metal (e.g., copper, tungsten, titanium, tantalum, etc.).

The third chip pads240B may be disposed on the fourth surface200Bbof the second semiconductor chip200B and may be electrically connected to the second circuit layer220B. The second bumps250B may be respectively disposed on the third chip pads240B and may be respectively connected to the third chip pads240B. The fourth chip pads260B may be disposed on the third surface200Baof the second semiconductor chip200B and may be respectively connected to the second through electrodes230B. The third and fourth chip pads240B and260B may include metal (e.g., copper). The second bumps250B may include a conductive material and may have a shape of at least one of a solder ball, a bump, and a pillar.

The second conductor patterns270B may be disposed on the fourth surface200Bbof the second semiconductor chip200B. The second conductor patterns270B may have substantially the same shape as the lower conductor patterns A and B described above with reference toFIGS.2A to2C. Although not shown, the second conductor patterns270B may be electrically connected to external terminals, and a current may be applied to the second conductor patterns270B. The second conductor patterns270B may have shapes different from those described above.

The first and second semiconductor chips200A and200B may be memory chips. The lower semiconductor chips100A may be a memory chip, a logic chip, an application processor (AP) chip, or a system on a chip (SOC). The first and second semiconductor chips200A and200B and the lower semiconductor chips100A may be electrically connected to each other and constitute a high bandwidth memory (HBM) chip.

Referring toFIG.7B, the first surfaces200Aaof the first semiconductor chips200A and the fourth surfaces200Bbof the second semiconductor chips200B may face each other. A current may be applied to the upper conductor patterns280A and the second conductor patterns270B to generate a magnetic field, and accordingly, the upper conductor patterns280A and the second conductor patterns270B may be aligned with each other in the first direction D1by magnetic force. When the second conductor patterns270B are aligned with the upper conductor patterns280A, the second conductor patterns270B may be spaced apart from the upper conductor patterns280A in the first direction D1.

FIG.8is a cross-sectional view of a semiconductor package.FIGS.9A and9Bare cross-sectional views illustrating alignment of a semiconductor package and a lower substrate. Hereinafter, differences from the above description will be mainly described for simplicity of description.

Referring toFIG.8, a semiconductor structure900may include a semiconductor chip400, a substrate800, a molding layer420, bump pads830, bumps840, and a conductor pattern850.

The semiconductor chip400may be mounted on an upper surface of the substrate800. When viewed in a plan view, the semiconductor chip400may be disposed on a center of the substrate800. The semiconductor chip400may be a memory chip, a logic chip, an application processor (AP) chip, or a system on a chip (SOC). The substrate800may be a redistribution board, a printed circuit board, or an interposer board.

The semiconductor chip400may have an upper surface400aand a lower surface400bthat face each other. The lower surface400bof the semiconductor chip400may be in contact with the substrate800. The semiconductor chip400may include integrated circuits and chip pads410. The chip pads410may be disposed on the lower surface400bof the semiconductor chip400and electrically connected to integrated circuits.

The molding layer420may be disposed on the upper surface of the substrate800and may cover the upper surface400aand side surfaces of the semiconductor chip400. The molding layer420may not extend between the substrate800and the semiconductor chip400. The molding layer420may include an insulating polymer such as an epoxy-based molding compound.

The substrate800may include an insulating layer810, first pads811, a protective layer820and second pads821. The insulating layer810may be disposed on a lower surface400bof the semiconductor chip400and a lower surface of the molding layer420. For example, the insulating layer810may include an organic material such as a photo-imageable dielectric (PID) material. The photo-imageable dielectric material may include, for example, at least one of photosensitive polyimide, polybenzoxazole, phenol-based polymer, and benzocyclobutene-based polymer. Although the example inFIG.8depicts one insulating layer810, there can be multiple insulating layers810.

The first pads811may be provided in the insulating layer810. The protective layer820may be disposed on a lower surface of the insulating layer810to cover the insulating layer810and the first pads811. The protective layer820may absorb stress. The stress may be stress due to differences in thermal expansion coefficients of components, but the cause of stress is not limited thereto. The protective layer820may include, for example, silicon, a polymer, an adhesive insulating layer, or a photo-imageable dielectric (PID) material. The polymer may be, for example, a polyimide or an epoxy-based polymer. The adhesive insulating layer may include Ajinomoto build-up layer (ABF).

The second pads821may be provided in the protective layer820. Although not shown, the semiconductor chip400may be electrically connected to the second pads821by a metal wiring in the protective layer820and the insulating layer810.

The bump pads830may be provided on a lower surface820bof the protective layer820. The bump pads830may be electrically connected to the second pads821, respectively. The bumps840may be respectively disposed on the bump pads830. The bumps840may include a conductive material and may have a shape of at least one of a solder ball, a bump, and a pillar.

The first pads811, the second pads821, and the bump pads830may include metal (e.g., copper).

The conductor patterns850may be disposed on a lower surface820bof the protective layer820. The conductor patterns850may have substantially the same shape as the lower conductor patterns A and B described with reference toFIGS.2A to2C. Although not shown, the conductor pattern850may be electrically connected to external terminals and a current may be applied to the conductor pattern850. The conductor pattern850may have a shape different from that described above.

Referring toFIGS.9A and9B, a semiconductor structure900may be stacked on an upper surface1000aof a lower substrate1000in a first direction D1perpendicular to the upper surface1000aof the lower substrate1000. The semiconductor structure900may have an upper surface900aand a lower surface900bthat face each other, and the lower surface900bof the semiconductor structure900may face the upper surface1000aof the lower substrate1000.

As described with reference toFIG.3, the lower substrate1000may include lower conductor patterns1100on the upper surface1000aof the lower substrate1000. A current may be applied to the lower conductor patterns1100and the conductor patterns850to generate a magnetic field, and accordingly, the lower conductor patterns1100and the conductor patterns850may be aligned with each other in the first direction D1by magnetic force. When the conductor patterns850are aligned with the lower conductor patterns1100, the conductor patterns850may be spaced apart from the lower conductor patterns1100in the first direction D1.

In some implementations, the current may be applied through the conductor pattern formed on the semiconductor device or the substrate to generate the magnetic field, and semiconductor device or the substrate may be self-aligned due to attraction by the magnetic field. The conductor pattern may be provided on the lower substrate and/or the semiconductor chip. The size and spacing of the magnetic field pattern formed depending on the required alignment precision may be designed. The conductor shielding structure may be added to prevent the circuit damage in the device due to the magnetic force.

While embodiments are described above, a person skilled in the art may understand that many modifications and variations are made without departing from the spirit and scope of the present disclosure defined in the following claims. Accordingly, the example embodiments of the present disclosure should be considered in all respects as illustrative and not restrictive, with the spirit and scope of the present disclosure being indicated by the appended claims.