Low power memory system using dual input-output voltage supplies

Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

BACKGROUND

Next generation low-power double data rate (LPDDR) memory (e.g., LPDDR6) can offer a balance of high performance, low power, competitive memory cost, various package types, and multi-sourcing availability that are attractive for mobile and non-mobile applications.

SUMMARY

Various disclosed aspects may include apparatuses and methods for memory system using dual input/output (IO) voltage supplies. Various aspects may include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer may communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

In some aspects, the first IO voltage supply is a first dedicated IO voltage supply, and the second IO voltage supply is a second dedicated IO voltage supply.

In some aspects, the first IO voltage supply is a dedicated IO voltage supply, and the second IO voltage supply is a shared IO voltage supply.

Some aspects may further include a first core voltage supply and a second core voltage supply, in which each of the first core voltage supply and the second core voltage supply are electrically connected to the memory device, and in which the shared IO voltage supply is electrically connected to the second core voltage supply.

Some aspects may further include a third core voltage supply, in which the third core voltage supply is electrically connected to the memory device, and in which a voltage of the second core voltage supply is greater than a voltage of the third core voltage supply.

Some aspects may further include a first core voltage supply, a second core voltage supply, and a third core voltage supply, in which each of the first core voltage supply, the second core voltage supply, and the third core voltage supply are electrically connected to the memory device, in which the shared IO voltage supply is electrically connected to the third core voltage supply, and in which a voltage of the second core voltage supply is greater than a voltage of the third core voltage supply.

In some aspects, a voltage of the second IO voltage supply is greater than a voltage of the first IO voltage supply.

In some aspects, the data of the memory transaction is binary data, and the memory device and the memory physical layer may further convert between the binary data and 3 level PAM IO scheme signals using the first IO voltage supply and the second IO voltage supply.

In some aspects, the memory device may encode the data of the memory transaction for generating a 3 level PAM signal, and generate the 3 level PAM signal by controlling selective electrical connection of the first IO voltage supply, the second IO voltage supply, or a ground to a component of the memory device according to the encoded data.

In some aspects, the memory physical layer may encode the data of the memory transaction for generating a 3 level PAM signal, and generate the 3 level PAM signal by controlling a selective electrical connection of the first IO voltage supply, the second IO voltage supply, or a ground to a component of the memory physical layer according to the encoded data.

Various aspects include computing devices having means for performing any of the functions of the computing device summarized above. Various aspects include methods to perform any of the functions of the computing device summarized above.

DETAILED DESCRIPTION

Various embodiments include circuitry, methods, and computing devices implementing such methods for memory systems using dual input/output (IO) voltage supplies. Some embodiments may include memory systems having dual input/output (IO) voltage supplies in which a memory interface of a system on chip (SoC) and an IO block of a memory device are connected to and receive voltage from dual IO voltage supplies. Some embodiments may include IO structures configured to implement 3 level pulse amplitude modulation (PAM or PAM-3) using dual IO voltages.

The terms “computing device” and “mobile device” are used interchangeably herein to refer to any one or all of cellular telephones, smartphones, personal or mobile multi-media players, personal data assistants (PDA's), laptop computers, tablet computers, convertible laptops/tablets (2-in-1 computers), smartbooks, ultrabooks, netbooks, palm-top computers, wireless electronic mail receivers, multimedia Internet enabled cellular telephones, mobile gaming consoles, wireless gaming controllers, and similar personal electronic devices that include a memory, and a programmable processor. The term “computing device” may further refer to stationary computing devices including personal computers, desktop computers, all-in-one computers, workstations, super computers, mainframe computers, embedded computers, servers, home theater computers, and game consoles.

The adjectives “high,” “higher,” “low” and “lower” are used herein as relative terms to distinguish different levels of voltage or power demand characterizing various aspects, such as voltage supplies, IO schemes, memory systems, etc. For example, two voltage supplies included in a memory system that differ in terms of their voltage levels may be distinguished in the following descriptions of various embodiments as a “high voltage supply” and a “low voltage supply.” The terms “high,” “higher,” “low” and “lower” are not intended to indicate or suggest a particular value of level of the characterized aspect. For example, the voltage of a “high voltage supply” may differ from the voltage of a “low voltage supply” by one, two or a few volts.

Embodiments described herein include memory systems using dual IO voltage supplies for implementing a 3 level PAM IO scheme, that enable improved performance and reduced power demand compared to conventional memory systems. The memory systems may include a memory interface of an SoC and an IO block of a memory device connected to and configured to receive voltage from dual IO voltage supplies. In some embodiments, the dual IO voltage supplies may include two dedicated IO voltage supplies. In some embodiments, the dual IO voltage supplies may include a dedicated IO voltage supply and a shared IO voltage supply. The shared IO voltage supply may include a core voltage supply of the memory device. In some embodiments, shared IO voltage supply may include a core high voltage supply of the memory device. In some embodiments, the shared IO voltage supply may include a core low voltage supply of the memory device. As used herein, the term “IO voltage supply” refers to a voltage supply connected to the IO block of the memory device. As used herein, the term “core voltage supply” refers to a voltage supply connected to the internal circuitry of the memory device, which may include, for example, a memory bitcell array. As used herein, the term “shared IO voltage supply” refers to a voltage supply connected to the IO block and to a core voltage supply.

In some embodiments, an IO block of the memory device may include structures configured to control an output of signals for implementing the 3 level PAM IO scheme. The IO block may be, for example, a 3 level pulse amplitude modulator. The IO block may receive a data signal and encode the data signal to transmitter input signals. The IO block may interpret the transmitter input signals and control selection and output of the voltage supplied to the IO block from the dual IO voltage supplies configured to represent the signal states of the 3 level PAM IO scheme. In some embodiments, the IO block may also receive 3 level PAM signals, and include structures configured to convert the 3 level PAM signals to data signals and output the data signals. In some embodiments, the IO block may compare the 3 level PAM signals to voltage reference signals, which may generate and output receiver output signals. The IO block may decode the receiver output signals and generate and output the data signals.

In some embodiments, system error correction code (ECC), link ECC, or other system functions may be supported to enhance memory system reliability and stability. The ECC or other system function values may be encoded and decoded along with the data signals as part of the 3 level PAM IO scheme.

Using the dual IO voltage supplies to implement the 3 level PAM IO scheme allows for increased bandwidth for communication with the memory device by increasing the number of IO signaling levels used in such communication as compared to two IO signaling level (e.g., high and low) schemes. While providing higher memory system bandwidth than existing low-power double data rate memory (LPDDR) specifications (e.g., LPDDR5), the IO signaling levels increase and dual rank support allow for flexible memory package options and configurations that many systems require without significant cost overhead.

Further, embodiments described herein provide memory systems using an IO scheme that draws less power than conventional single IO voltage 3 level PAM scheme memory systems. By using a lower voltage IO voltage supply in addition to an existing higher IO voltage supply, overall memory system power consumption may be reduced as the higher IO voltage supply may be used less often, such as when the lower voltage IO voltage supply is used. Additionally, in some embodiments, by sharing a memory core voltage supply with one of the dual IO voltage supplies, there may be no further system cost overhead to support the additional IO voltage supply in the memory system.

Some of the embodiments described herein may be particularly well suited for memory sub-systems and memory devices for user equipment, mobile computing, automotive, and artificial intelligence systems by providing high performance, memory systems. In particular, various embodiments may be implemented with next generation LPDDR specification (LPDDR6) and associated double data rate memory (DDR) physical layer (PHY) chipsets used in mobile device or non-mobile computing devices.

FIG.1illustrates a system including a computing device10suitable for use with various embodiments. The computing device10may include a system-on-chip (SoC)12with a processor14, a memory16, a memory physical layer34, a communication interface18, a storage memory interface20, a clock controller30, and an interconnect32. The computing device10may further include a communication component22, such as a wired or wireless modem, a storage memory24, an antenna26for establishing a wireless communication link, a power manager28, and a memory36. The processor14may include any of a variety of processing devices, for example a number of processor cores.

The term “system-on-chip” (SoC) is used herein to refer to a set of interconnected electronic circuits typically, but not exclusively, including a processing device, a memory, and a communication interface. A processing device may include a variety of different types of processors14and processor cores, such as a general purpose processor, a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), an accelerated processing unit (APU), a secure processing unit (SPU), neural network processing unit (NPU), a subsystem processor of specific components of the computing device, such as an image processor for a camera subsystem or a display processor for a display, an auxiliary processor, a single-core processor, a multicore processor, a controller, and a microcontroller. A processing device may further embody other hardware and hardware combinations, such as a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), other programmable logic device, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and time references. Integrated circuits may be configured such that the components of the integrated circuit reside on a single piece of semiconductor material, such as silicon.

An SoC12may include one or more processors14. The computing device10may include more than one SoC12, thereby increasing the number of processors14and processor cores. The computing device10may also include processors14that are not associated with an SoC12. The processors14may each be configured for specific purposes that may be the same as or different from other processors14of the computing device10. One or more of the processors14and processor cores of the same or different configurations may be grouped together. A group of processors14or processor cores may be referred to as a multi-processor cluster.

The computing device10may include any number and combination of memories, such as the memory16integral to the SoC12and the memory36separate from the SoC12. Any of the memories16,36may be a volatile or non-volatile memory configured for storing data and processor-executable code for access by the processor14. The computing device10and/or SoC12may include one or more memories16,36configured for various purposes. One or more memories16,36may include volatile memories such as random access memory (RAM) or main memory, including static RAM (SRAM), such as the memory16, dynamic RAM (DRAM), such as the memory36, or cache memory. These memories16,34may be configured to temporarily hold a limited amount of data received from a data sensor or subsystem, data and/or processor-executable code instructions that are requested from a non-volatile memory16,24,36loaded to the memories16,34from the non-volatile memory16,24,36in anticipation of future access based on a variety of factors, and/or intermediary processing data and/or processor-executable code instructions produced by the processor14and temporarily stored for future quick access without being stored in non-volatile memory16,24,36. The memory16,36may be configured to store data and processor-executable code in parts of the memory16,36configured to store data and processor-executable code for secure computing operations, referred to herein as a secure portion. The memory16,36may be configured to store data and processor-executable code in parts of the memory16,36configured to store data and processor-executable code for non-secure computing operations, referred to herein as a non-secure portion.

The memory physical layer34may work in unison with the memory36to enable the computing device10to store and retrieve data and processor-executable code on and from the memory36. The memory physical layer34may control access to the storage memory36and allow the processor14to read data from and write data to the memory36.

The storage memory interface20and the storage memory24may work in unison to allow the computing device10to store data and processor-executable code on a non-volatile storage medium. The storage memory24may be configured much like an embodiment of the memory16in which the storage memory24may store the data or processor-executable code for access by one or more of the processors14. The storage memory24, being non-volatile, may retain the information after the power of the computing device10has been shut off. When the power is turned back on and the computing device10reboots, the information stored on the storage memory24may be available to the computing device10. The storage memory interface20may control access to the storage memory24and allow the processor14to read data from and write data to the storage memory24.

The power manager28may be configured to control power states of and/or power delivery to the components of the SoC12. In some embodiments, the power manager28may be configured to signal power states to the components of the SoC12to prompt the components of the SoC12to transition to the signaled power states. In some embodiments, the power manager28may be configured to control amounts of power provided to the components of the SoC12. For example, the power manager28may be configured to control connections between components of the SoC12and power rails (not shown). As another example, the power manager28may be configured to control amounts of power on power rails connected to the components of the SoC12.

A clock controller30may be configured to control clock signals transmitted to the components of the SoC12. In some embodiments, the clock controller30may be configured to signal clock states, such as gated or ungated, to components of the SoC12to prompt the components of the SoC12to transition to the clock state. For example, a component of the SoC12may transition to a gated clock state in response to receiving a gated clock state signal from the clock controller30by disconnecting from a clock signal and may transition to an ungated clock state in response to receiving an ungated clock state signal from the clock controller30by connecting to the clock signal. In some embodiments, the clock controller30may be configured to control clock signals to components of the SoC12. For example, the clock controller30may disconnect a component of the SoC12from a clock signal to transition the component of the SoC12to a gated clock state and may connect the component of the SoC12to the clock signal to transition the component of the SoC12to an ungated clock state.

The interconnect32may be a communication fabric, such as a communication bus, configured to communicatively connect the components of the SoC12. The interconnect32may transmit signals between the components of the SoC12. In some embodiments, the interconnect32may be configured to control signals between the components of the SoC12by controlling timing and/or transmission paths of the signals.

Some or all of the components of the computing device10and/or the SoC12may be arranged differently and/or combined while still serving the functions of the various embodiments. The computing device10may not be limited to one of each of the components, and multiple instances of each component may be included in various configurations of the computing device10.

FIGS.2A-2Cillustrates examples of memory systems using dual input/output (IO) voltage supplies for implementing various embodiments. With reference toFIGS.1-2C, a memory system200a,200b,200cmay be, in whole or in part, integral to an SoC (e.g., SoC12inFIG.1). The memory system200a,200b,200cmay include a memory controller204, a memory physical layer206, any number and combination of memory devices208(e.g., memory16,24inFIG.1), and a power management integrated circuit (PMIC)210(e.g., power manager28inFIG.1). The memory devices208may further include an IO block212and any number and combination of memory banks214. The IO block212may be, for example, a 3 level pulse amplitude modulator.

The PMIC210may be configured to control and/or provide voltage to the memory device208and to the memory physical layer206. The PMIC210may control and/or provide voltage to the memory device208via core voltage supplies216a,216b,216c, which may also be referred to as rails, lines, etc. In some embodiments the core voltage supplies216a,216b,216cmay include a first core voltage supply216a, and a second core voltage supply216band/or a third core voltage supply216c. The core voltage supplies216a,216b,216cmay be electrically connected to internal circuitry of the memory device208, such as the memory banks214or memory bitcell arrays (not shown) of the memory banks214. The core voltage supplies216a,216b,216cmay be differently configured from each other to provide voltages, alone or in any combination, needed for the memory device208to perform any number and combination of functions, including storing, reading, writing, and/or retaining data. In some embodiments, the core voltage supplies216a,216b,216cmay be differently configured from each other to provide voltages, alone or in any combination, needed for the memory device208to perform any number and combination of the various functions at different speeds and/or for differently sized portions of the memory device208. In an example including two core voltage supplies216a,216b, the first core voltage supply216amay be greater than the second core voltage supply216b. In an example including three core voltage supplies216a,216b,216c, the first core voltage supply216amay be greater than the second core voltage supply216b, and the second core voltage supply216bmay be greater than the third core voltage supply216c. As a specific and nonlimiting example, such as per the Joint Electron Device Engineering Council (JEDEC) LPDDR5 specification, the first core voltage supply216amay be approximately 1.8V and the second core voltage supply216bmay be approximately 1.05V. As another specific and nonlimiting example, such as per the JEDEC LPDDR5 specification, the first core voltage supply216amay be may be approximately 1.8V, the second core voltage supply216bmay be approximately 1.05V, and the third core voltage supply216cmay be approximately 0.9V.

The PMIC210may control and/or provide voltage to the memory device208and to the memory physical layer206via IO voltage supplies218a,218b, which may also be referred to as rails, lines, etc. The IO voltage supplies218a,218bmay be referred to herein together as dual IO voltage supplies. The dual IO voltage supplies218a,218bmay include a high IO voltage supply and a low IO voltage supply in which the high IO voltage supply provides a higher voltage than the low IO voltage supply. The voltage provided to the memory device208and to the memory physical layer206via the dual IO voltage supplies218a,218bmay enable the memory system200a,200b,200cto implement a 3 level PAM IO scheme. In some embodiments, the voltage provided to the memory device208via the dual IO voltage supplies218a,218bmay be provided to the IO block212of the memory device208to enable the memory device to implement the 3 level PAM IO scheme as described herein.

The memory device208and to the memory physical layer206may be communicatively connected via a communication bus220. The communication bus220may be configured to transmit signals and data for implementing memory transactions between the memory device208and to the memory physical layer206. For example, the communication bus220may include any number and combination of buses or lines for transmitting data, clock signals, command and address information, etc. In some embodiments, the communication bus220may be communicatively connected between the SoC and the memory device208external to the SoC. In some embodiments, implementing a 3 level PAM IO scheme using the dual IO voltage supplies218a,218bmay decrease power for executing the same memory transactions as compared to IO schemes, such as a 3 level PAM IO scheme, using a single IO voltage supply. The low IO voltage supply of the dual IO voltage supplies218a,218bmay provide a lower voltage than the single IO voltage supply, and use of the low IO voltage supply for executing the same memory transactions as the single IO voltage supply may enable the memory device208to use less power than executing the transactions using the voltage of the single IO voltage supply. In some embodiments, implementing a 3 level PAM IO scheme using the dual IO voltage supplies218a,218bmay increase memory system bandwidth for executing the same memory transactions as compared to IO schemes using a single IO voltage supply. The 3 level PAM IO scheme may be implemented using a greater number of signal states, collectively referred to herein as states, based on the dual IO voltage supplies218a,218bthan other IO schemes that use a single IO voltage supply. The greater number of signal states enables encoding a greater amount of data and information in 3 level PAM signals on the communication bus220than other IO schemes that use a single IO voltage supply.

In some embodiments, the memory system200a,200b,200cmay receive memory transactions from any number and combination of processors202a,202b,202c(e.g., processor14inFIG.1). The memory system200a,200b,200cmay execute a memory transaction received from a processor202a,202b,202cand/or provide a response of the executed memory transaction to the processor202a,202b,202c.

In the example illustrated inFIG.2A, the memory system200amay include dedicated IO voltage supplies218a,218bproviding the two voltage levels. The PMIC210may control and/or provide designated voltages of each of the dedicated dual IO voltage supplies218a,218bto the memory device208and to the memory physical layer206via individual ones of the dual IO voltage supplies218a,218b.

In the example illustrated inFIG.2B, the memory system200cmay include a shared IO voltage supply218aand a dedicated IO voltage supply218b, with the combination providing the two voltage levels. The shared IO voltage supply218amay share a common voltage with the second core voltage supply216bby electrical connection to the second core voltage supply216b. The PMIC210may control and/or provide a designated voltage of the shared dual IO voltage supply218ato the memory device208and to the memory physical layer206via controlling and/or providing the designated voltage on the second core voltage supply216b. The PMIC210may control and/or provide a designated voltage the dedicated IO voltage supply218bto the memory device208and to the memory physical layer206via the individual dedicated IO voltage supply218b.

In the example illustrated inFIG.2C, the memory system200cmay include a shared IO voltage supply218aand a dedicated IO voltage supply218b, with the combination providing the two voltage levels. The shared IO voltage supply218amay share a common voltage with the third core voltage supply216cby electrical connection to the third core voltage supply216c. The PMIC210may control and/or provide a designated voltage of the shared dual IO voltage supply218ato the memory device208and to the memory physical layer206via controlling and/or providing the designated voltage on the third core voltage supply216c. The PMIC210may control and/or provide a designated voltage the dedicated IO voltage supply218bto the memory device208and to the memory physical layer206via the individual dedicated IO voltage supply218b.

FIG.3is a circuit block diagram illustrating an example dual IO voltage 3 level PAM IO structure for implementing various embodiments. With reference toFIGS.1-3, a dual IO voltage 3 level PAM IO structure300(e.g., memory physical layer206, IO block212inFIGS.2A-2C) may include an encoder302, a decoder304, and any number and combination of 3 level PAM transmitters306a,306b, and 3 level PAM receivers308a,308b. In some embodiments, the dual IO voltage 3 level PAM IO structure300may include two 3 level PAM transmitters306a,306band two 3 level PAM receivers308a,308b. The 3 level PAM transmitters306a,306bmay be electrically connected to the dual IO voltage supplies218a,218b. In some embodiments, the dual IO voltage supplies218a,218bmay be two dedicated IO voltage supplies218a,218b. In some embodiments, the dual IO voltage supplies218a,218bmay be a shared IO voltage supply218aand a dedicated IO voltage supply218b. In some embodiments, the 3 level PAM transmitters306a,306band 3 level PAM receivers308a,308bmay be communicatively connected.

Via an input316, the encoder302may receive data and/or information for transmission as part of a memory transaction. The encoder302may receive the data and/or information as binary signals. The encoder302may encode the binary signals into transmitter input signals for generating 3 level PAM signals. For example, the encoder302may encode three binary signals into the transmitter input signals for two 3 level PAM transmitters306a,306b. The transmitter input signals may be output by the encoder302to the 3 level PAM transmitters306a,306b.

The 3 level PAM transmitters306a,306bmay receive the transmitter input signals from the encoder302, and generate and output the 3 level PAM signals. The 3 level PAM transmitters306a,306bmay include pre-drivers310a,310b, pull up circuits312a,312b,312c,312d, which are referred to herein as “pull ups,” and pull down circuits314a,314b, which are referred to herein as “pull downs.” The pull ups312a,312b,312c,312dmay be electrically connected to the dual IO voltage supplies218a,218b. For example, the pull ups312a,312b,312c,312dmay each be electrically connected to one of the dual IO voltage supplies218a,218b, and the pull ups312a,312b,312c,312dof the same 3 level PAM transmitters306a,306bmay each be electrically connected to a different one of the dual IO voltage supplies218a,218b. As another example, the pull ups312a,312cmay be electrically connected to the IO voltage supply218a, and the pull ups312b,312dmay be electrically connected to the IO voltage supply218b. The pull downs314a,314bmay be selectively electrically connected to the dual IO voltage supplies218a,218bvia the pull ups312a,312b,312c,312d. For example, the pull down314amay be selectively electrically connected to the IO voltage supply218avia the pull up312aand selectively electrically connected to the IO voltage supply218bvia the pull up312b. The pull down314bmay be selectively electrically connected to the IO voltage supply218avia the pull up312cand selectively electrically connected to the IO voltage supply218bvia the pull up312d.

The 3 level PAM transmitters306a,306bmay output the 3 level PAM signals via outputs322a,322b. The outputs322a,322bmay be selectively electrically connected to the dual IO voltage supplies218a,218bvia the pull ups312a,312b,312c,312dand selectively electrically connected to ground via the pull downs314a,314b. For example, the output322amay be selectively electrically connected to the IO voltage supply218avia the pull up312a, selectively electrically connected to the IO voltage supply218bvia the pull up312b, and selectively electrically connected to ground via the pull down314a. The output322bmay be selectively electrically connected to the IO voltage supply218avia the pull up312c, selectively electrically connected to the IO voltage supply218bvia the pull up312d, and selectively electrically connected to ground via the pull down314b.

The pre drivers310a,310bmay interpret the received transmitter input signals and accordingly control the pull ups312a,312b,312c,312dand the pull downs314a,314bto selectively electrically connect the outputs322a,322bto the dual IO voltage supplies218a,218bor ground to generate and output state signals. For example, the pre driver310amay interpret the received transmitter input signals and accordingly control the pull ups312a,312band the pull down314ato selectively electrically connect the output322ato the dual IO voltage supplies218a,218bor ground. The pre driver310bmay interpret the received transmitter input signals and accordingly control the pull ups312c,312dand the pull down314bto selectively electrically connect the output322bto the dual IO voltage supplies218a,218bor ground.

In some embodiments, the 3 level PAM transmitters306a,306bmay generate and output up to nine state signals based on the selective connection of the outputs322a,322bto the dual IO voltage supplies218a,218bor ground. For example, each 3 level PAM transmitter306a,306bmay generate and output three level signals (e.g., high “H”, medium “M”, and low “L”). The 3 level PAM signals output by each 3 level PAM transmitter306a,306bmay be combined as any of the up to nine state signals.

The 3 level PAM receivers308a,308bmay receive the 3 level PAM signals, and generate and output receiver output signals. The 3 level PAM receivers308a,308bmay include comparator circuits324a,324b,324c,324dconfigured to compare the received 3 level PAM signals and voltage reference signals326a,326b. For example, the comparator circuits324a,324cmay be configured to compare whether states of the received 3 level PAM signals are less than the voltage reference signal326a. As another example, the comparator circuits324b,324dmay be configured to compare whether states of the received 3 level PAM signals are less than, or greater than, the voltage reference signal326b. In such examples, the voltage reference signal326amay be greater than the voltage reference signal326b. The results of the comparisons may prompt the comparator circuits324a,324b,324c,324dto output receiver output signals of values that represent the states of received 3 level PAM signals.

The decoder304may receive the receiver output signals from the 3 level PAM receivers308a,308b, and generate and output data and/or information of the memory transaction. The decoder304may decode the receiver output signals to generate the binary signals as received by the encoder302. The decoder304may output the binary signals via an output318.

In some embodiments, the encoder302and the 3 level PAM transmitters306a,306boutputting the 3 level PAM signals, and the decoder304and the 3 level PAM receivers308a,308breceiving the 3 level PAM signals may be parts of different dual IO voltage 3 level PAM IO structures300. For example, the encoder302and the 3 level PAM transmitters306a,306bmay be part of a memory physical layer, and the decoder304and the 3 level PAM receivers308a,308bmay be part of an IO block. As another example, the encoder302and the 3 level PAM transmitters306a,306bmay be part of an IO block, and the decoder304and the 3 level PAM receivers308a,308bmay be part of a memory physical layer.

FIG.4illustrates an example dual IO voltage 3 level PAM timing diagram for implementing various embodiments. With reference toFIGS.1-4, the timing diagram includes an IO voltage 1 (e.g., voltage of one of IO voltage supply218a,218binFIGS.2A-3), an IO voltage 2 (e.g., voltage of the other of IO voltage supply218a,218binFIGS.2A-3), a ground voltage (“GND”) (e.g., ground inFIG.3), a voltage reference 1 (“Vref 1”) (e.g., voltage of one of voltage reference signal326a,326binFIG.3), and a voltage reference 2 (“Vref 2”) (e.g., voltage of the other of voltage reference signal326a,326binFIG.3).

As described herein, a dual IO voltage 3 level PAM IO structure (e.g., dual IO voltage 3 level PAM IO structures300inFIG.3) may encode and output and/or receive and decode 3 level signals (e.g., high “H”, medium “M”, and low “L”). The value of a signal may depend on the control of the selective connections of 3 level PAM transmitters (e.g., 3 level PAM transmitters306a,306binFIG.3) to IO voltage supplies (e.g., IO voltage supplies218a,218binFIGS.2A-3). A high signal may result from selective electrical connection to a high IO voltage supply that may supply a high level voltage (“voltage 1”). A medium signal may result from a selective electrical connection to a low IO voltage supply that may supply a medium level voltage (“voltage 2”). A low signal may result from a selective electrical connection to ground. The dual IO voltage 3 level PAM IO structure may determine the type, value, level, or state of the 3 level PAM signal by comparison with Vref 1 and/or Vref 2. For example, 3 level PAM receivers (e.g., 3 level PAM receivers308a,308binFIG.3) of the dual IO voltage 3 level PAM IO structure may determine the type, value, level, or state of the 3 level PAM signal.

In some embodiments, the medium level voltage affects both high and medium signal timing and voltage margin. The low IO voltage supply level from a PMIC (e.g., PMIC210inFIGS.2a-2C) may be adjusted globally to balance between high and medium signal timing and voltage margin during Write & Read data training in a computing device (e.g., computing device10inFIG.1). An SoC (e.g., SoC12inFIG.1) may provide certain control signals to the PMIC to adjust the low IO voltage supply.

FIG.5illustrate an example of 3 level PAM coding for implementing various embodiments. With reference toFIGS.1-5, the table500illustrated inFIG.5shows an example of potential mapping between binary signals and 3 level PAM signals for encoding and decoding between the binary signals and 3 level PAM signals by an encoder (e.g., encoder302inFIG.3) and a decoder (e.g., decoder304inFIG.3). The table500includes the binary signal values high “H” and low “L”, and the 3 level PAM signal values high “H”, medium “M”, and low “L”. In this example, three binary signals may each have one of two values for a total of eight possible combinations. The corresponding two 3 level PAM signals may each have one of three values. There may be nine possible combinations of 3 level PAM signals. However, the number of combinations of 3 level PAM signals is limited by the number of possible combinations of binary signals. Each combination of three binary signals may correspond to a combination of two 3 level PAM signals. In the illustrated example, the “HH” combination of 3 level PAM signals is omitted as it is the most power intensive. However, the claims and descriptions are not intended to be limited in scope by the example shown inFIG.5.

FIGS.6A and6Billustrate example dual IO voltage memory system interfaces for 3 level PAM IO schemes for implementing various embodiments. With reference toFIGS.1-6B, a dual IO voltage memory system interface for 3 level PAM IO schemes600a,600bmay be implemented by various components of a memory system (e.g., memory system200a,200b,200cinFIGS.2A-2C). Such components may include a memory physical layer206, any number and combination of memory devices208, dual IO voltage supplies218a,218b, and a communication bus (e.g., communication bus220inFIGS.2A-2C). In some embodiments, the communication bus may include any number and combination of data buses602a,602b, data clock buses604a,604b, read strobe clocks buses606a,606b, a command and address bus610, a clock bus612, and data strobe buses614a,614b.

The data buses602a,602bmay vary in size. In some embodiments, the data buses602a,602bmay be configured to transmit a same amount of data and/or information for a memory transaction as a single IO voltage memory system interface. In such embodiments, the dual IO voltage 3 level PAM IO scheme may encode more data per line of the data buses602a,602bbased on having extra possible signal types, values, levels, or states. As such, the data buses602a,602bmay be implemented with fewer lines compared to a single IO voltage memory system interface. For example, a data bus for a single IO voltage memory system interface may include eight binary data bit lines and binary function bit line (e.g., an error correction code parity bit line). Various binary bits may be encoded into fewer 3 level PAM signal bits, as described further herein. For example, three binary bits may be encoded as two 3 level PAM signal bits. Thus, nine binary bits may be reduced to six 3 level PAM signal bits and the number of lines of the data buses602a,602bmay be reduced accordingly for a dual IO voltage memory system interface for 3 level PAM IO schemes600a,600b.

In some embodiments, the data buses602a,602bmay be configured to transmit more data and/or information for a memory transaction as a single IO voltage memory system interface. In other words, the data buses602a,602bmay have a higher bandwidth. In such embodiments, the dual IO voltage 3 level PAM IO scheme may transmit more data over more lines of the data buses602a,602bwithout incurring extra power cost based on using lower power 3 level PAM signals than single IO voltage memory system interface. For example, a data bus for a single IO voltage memory system interface may include eight binary data bit lines and binary function bit line (e.g., an error correction code parity bit line). Various binary bits may be encoded into fewer 3 level PAM signal bits, as described further herein. For example, three binary bits may be encoded as two 3 level PAM signal bits. Thus, nine binary bits may be reduced to six 3 level PAM signal bits. The bandwidth of the data buses602a,602bmay be doubled in comparison to the single IO voltage memory system interface by increasing the number of lines of the data buses602a,602bto twelve lines for a dual IO voltage memory system interface for 3 level PAM IO schemes600a,600b.

In some embodiments, the dual IO voltage memory system interface for 3 level PAM IO schemes600a,600bmay be configured for different clock schemes. For example, the dual IO voltage memory system interface for 3 level PAM IO schemes600aillustrated inFIG.6Aincludes data clock buses604a,604band read strobe clocks buses606a,606bof an LPDDR5 scheme. As another example, the dual IO voltage memory system interface for 3 level PAM IO schemes600billustrated inFIG.6Bincludes data strobe buses614a,614bof an LPDDR4 scheme.

FIG.7illustrates an example of signal allocations in a dual IO voltage memory system interface for 3 level PAM IO schemes for implementing various embodiments. With reference toFIGS.1-7, example table700,702,704list signal allocations to data buses (e.g., communication bus220inFIGS.2A-2C, data buses602a,602binFIGS.6A and6B) in a dual IO voltage memory system interface for 3 level PAM IO schemes. As described herein, binary bits may be encoded into fewer 3 level PAM signal bits. As such, the data buses may be implemented with fewer lines compared to a single IO voltage memory system interface. Table700shows signal allocations of a burst of data of a memory transaction for a single IO voltage memory system interface using a nine line data bus. Table702shows signal allocations of a burst of data of a memory transaction for a dual IO voltage memory system interface for 3 level PAM IO schemes using a six line data bus. Table704shows the mapping between the lines of a data bus for single IO voltage memory system interface and the lines of a data bus for a dual IO voltage memory system interface for 3 level PAM IO schemes. Using the mapping shown in table704, the comparison of table700and table702shows the signal allocation in tables700and702are for equivalent data bursts using different signaling and different size data buses. The signal allocation in table702allocates the equivalent data burst using fewer lines than the allocation in table700. In the example inFIG.7, the table704and the comparison of table700and702show a reduction ratio of 3:2. However, the claims and descriptions are not limited in scope by the example ofFIG.7.

FIG.8illustrates a method800for a method for dual IO voltage 3 level PAM IO according to an embodiment. With reference toFIGS.1-8, the method800may be implemented in a computing device (e.g., computing device10inFIG.1), in software executing in a processor (e.g., processor14, inFIG.1), in general purpose hardware, in dedicated hardware (e.g., memory16,24inFIG.1, memory system200a,200b,200c, memory physical layer206, memory device208, IO block212inFIGS.2A-2C, dual IO voltage 3 level PAM IO structure300, encoder302, decoder304, 3 level PAM transmitter306a,306b, and 3 level PAM receiver308a,308b, pre driver310a,310b, comparator circuits324a,324b,324c,324dinFIG.3), or in a combination of a software-configured processor and dedicated hardware, such as a processor executing software within a memory power control system that includes other individual components, and various memory/cache controllers. In order to encompass the alternative configurations enabled in various embodiments, the hardware implementing the method800is referred to herein as a “dual IO voltage controller.”

In block802, dual IO voltage controller may receive a data signal. The data signal may be part of a received memory transaction from any number and combination of processors (e.g., processor202a,202b,202cinFIGS.2A-2C). In some embodiments, the data signal may be a binary signal. In some embodiments, the dual IO voltage controller receiving the data signal in block802may be a memory physical layer, an IO block, and/or an encoder.

In block804, the dual IO voltage controller may encode the data signal as a transmitter input signal for generating a 3 level PAM signal and output the transmitter input signal. For example, the dual IO voltage controller may encode three binary signals into two groups of transmitter input signals for generating 3 level PAM signals. The binary signals may be represented by high and low values and the transmitter input signals may be translated as high, medium, and low signals. A combination of binary signal bits may be encoded into fewer 3 level PAM signals. In some embodiments, the dual IO voltage controller encoding the data signal as the transmitter input signal for generating a 3 level PAM signal and outputting the transmitter input signal in block804may be a memory physical layer, an IO block, and/or an encoder.

In block806, the dual IO voltage controller may receive and interpret the transmitter input signal. The transmitter input signals may be configured as control signals for selective electrical connection of an output of the dual IO voltage controller (e.g., output322a,322binFIG.3) to dual IO voltage supplies (e.g., dual IO voltage supplies218a,218binFIGS.2A-2C and3) and/or ground. In some embodiments, the dual IO voltage controller receiving and interpreting the transmitter input signal in block806may be a memory physical layer, an IO block, a 3 level PAM transmitter, and/or a pre driver.

In block808, the dual IO voltage controller may control a pull up unit(s) (e.g., pull up312a,312b,312c,312dinFIG.3) and/or a pull down unit (e.g., pull down314a,314binFIG.3) to control receipt of voltage from the dual IO voltage supplies based on the transmitter input signal. The dual IO voltage controller may signal control signals to the pull up unit(s) to selectively electrically connect the output to the dual IO voltage supplies. The dual IO voltage controller may signal control signals to the pull down unit to selectively electrically connect the output to ground. The voltage received at the output in response to the selective electrical connection to the dual IO voltage supplies and/or ground may be a 3 level PAM signal derived from the data signal through encoding of the data signal to the transmitter input signal. In some embodiments, a signal state of the 3 level PAM signal may be high in response to selective electrical connection to a high IO voltage supply of the dual IO voltage supplies, medium in response to selective electrical connection to a low IO voltage supply of the dual IO voltage supplies, and low in response to selective electrical connection to ground. In some embodiments, the dual IO voltage controller controlling the pull up unit(s) and/or the pull down unit to control receipt of voltage from the dual IO voltage supplies based on the transmitter input signal in block808may be a memory physical layer, an IO block, a 3 level PAM transmitter, and/or a pre driver.

In block810, the dual IO voltage controller may output the 3 level PAM signal based on the voltage received from the IO voltage supply or ground according to the transmitter input signal. The dual IO voltage controller may output the 3 level PAM signal having a signal state resulting from the selective electrical connection of the output to the dual IO voltage supplies and/or ground via the pull up unit(s) and/or the pull down unit. In some embodiments, the dual IO voltage controller outputting the 3 level PAM signal based on the voltage received from the IO voltage supply or ground according to the transmitter input signal in block810may be a memory physical layer, an IO block, and/or a 3 level PAM transmitter.

In block812, the dual IO voltage controller may receive the 3 level PAM signal. The output 3 level PAM signal may be targeted to a receiving device based on the target of the memory transaction and/or return of the memory transaction. The target of the memory transaction and/or return of the memory transaction may receive the output 3 level PAM signal. In some embodiments, the dual IO voltage controller receiving the 3 level PAM signal in block812may be a memory physical layer, an IO block, a 3 level PAM receiver, and/or a comparator circuit.

In block814, the dual IO voltage controller may compare the 3 level PAM signal to a voltage reference (e.g., voltage reference signals326a,326binFIG.3). For example, the dual IO voltage controller may compare whether the received 3 level PAM signal is less than a high voltage reference signal. As another example, the dual IO voltage controller may compare whether the received 3 level PAM signal is less than, or greater than, a low voltage reference signal. In such examples, the high voltage reference signal may be greater than the low voltage reference signal. In some embodiments, the dual IO voltage controller comparing the 3 level PAM signal to the voltage reference in block814may be a memory physical layer, an IO block, a 3 level PAM receiver, and/or a comparator circuit.

In block816, the dual IO voltage controller may generate and output the result of the comparison as a receiver output signal. The receiver output signal resulting from the comparison may be configured to describe the state of the received 3 level PAM signal. In some embodiments, the dual IO voltage controller generating and outputting the result of the comparison as the receiver output signal in block816may be a memory physical layer, an IO block, a 3 level PAM receiver, and/or a comparator circuit.

In block818, the dual IO voltage controller may receive and decode the receiver output signal as a data signal. The data signal resulting from decoding the receiver output signal may be the data signal received in block802. In some embodiments, the dual IO voltage controller receiving and decoding the receiver output signal as a data signal in block818may be a memory physical layer, an IO block, and/or a decoder.

In block820, the dual IO voltage controller may output the data signal. In some embodiments, the data signal may be output to a memory device. In some embodiments, the data signal may be output to a processor, such as via a memory controller. In some embodiments, the dual IO voltage controller outputting the data signal in block820may be a memory physical layer, an IO block, and/or a decoder.

Various embodiments (including, but not limited to, embodiments described above with reference toFIGS.1-8) may be implemented in a wide variety of computing systems including mobile computing devices, an example of which suitable for use with the various embodiments is illustrated inFIG.9. The mobile computing device900may include a processor902coupled to a touchscreen controller904and an internal memory906. The processor902may be one or more multicore integrated circuits designated for general or specific processing tasks. The internal memory906may be volatile or non-volatile memory, and may also be secure and/or encrypted memory, or unsecure and/or unencrypted memory, or any combination thereof. Examples of memory types that can be leveraged include but are not limited to DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touchscreen controller904and the processor902may also be coupled to a touchscreen panel912, such as a resistive-sensing touchscreen, capacitive-sensing touchscreen, infrared sensing touchscreen, etc. Additionally, the display of the mobile computing device900need not have touch screen capability.

The mobile computing device900may have one or more radio signal transceivers908(e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio) and antennae910, for sending and receiving communications, coupled to each other and/or to the processor902. The transceivers908and antennae910may be used with the above-mentioned circuitry to implement the various wireless transmission protocol stacks and interfaces. The mobile computing device900may include a cellular network wireless modem chip916that enables communication via a cellular network and is coupled to the processor.

The mobile computing device900may include a peripheral device connection interface918coupled to the processor902. The peripheral device connection interface918may be singularly configured to accept one type of connection, or may be configured to accept various types of physical and communication connections, common or proprietary, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface918may also be coupled to a similarly configured peripheral device connection port (not shown).

The mobile computing device900may also include speakers914for providing audio outputs. The mobile computing device900may also include a housing920, constructed of a plastic, metal, or a combination of materials, for containing all or some of the components described herein. The mobile computing device900may include a power source922coupled to the processor902, such as a disposable or rechargeable battery. The rechargeable battery may also be coupled to the peripheral device connection port to receive a charging current from a source external to the mobile computing device900. The mobile computing device900may also include a physical button924for receiving user inputs. The mobile computing device900may also include a power button926for turning the mobile computing device900on and off.

The various embodiments (including, but not limited to, embodiments described above with reference toFIGS.1-8) may be implemented in a wide variety of computing systems include a laptop computer1000an example of which is illustrated inFIG.10. Many laptop computers include a touchpad touch surface1017that serves as the computer's pointing device, and thus may receive drag, scroll, and flick gestures similar to those implemented on computing devices equipped with a touch screen display and described above. A laptop computer1000will typically include a processor1002coupled to volatile memory1012and a large capacity nonvolatile memory, such as a disk drive1013of Flash memory. Additionally, the computer1000may have one or more antenna1008for sending and receiving electromagnetic radiation that may be connected to a wireless data link and/or cellular telephone transceiver1016coupled to the processor1002. The computer1000may also include a floppy disc drive1014and a compact disc (CD) drive1015coupled to the processor1002. In a notebook configuration, the computer housing includes the touchpad1017, the keyboard1018, and the display1019all coupled to the processor1002. Other configurations of the computing device may include a computer mouse or trackball coupled to the processor (e.g., via a USB input) as are well known, which may also be used in conjunction with the various embodiments.

The various embodiments (including, but not limited to, embodiments described above with reference toFIGS.1-9) may also be implemented in fixed computing systems, such as any of a variety of commercially available servers. An example server1100is illustrated inFIG.11. Such a server1100typically includes one or more multicore processor assemblies1101coupled to volatile memory1102and a large capacity nonvolatile memory, such as a disk drive1104. As illustrated inFIG.11, multicore processor assemblies1101may be added to the server1100by inserting them into the racks of the assembly. The server1100may also include a floppy disc drive, compact disc (CD) or digital versatile disc (DVD) disc drive1106coupled to the processor1101. The server1100may also include network access ports1103coupled to the multicore processor assemblies1101for establishing network interface connections with a network1105, such as a local area network coupled to other broadcast system computers and servers, the Internet, the public switched telephone network, and/or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, 5G, LTE, or any other type of cellular data network).

Computer program code or “program code” for execution on a programmable processor for carrying out operations of the various embodiments may be written in a high level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, a Structured Query Language (e.g., Transact-SQL), Perl, or in various other programming languages. Program code or programs stored on a computer readable storage medium as used in this application may refer to machine language code (such as object code) whose format is understandable by a processor.

Implementation examples are described in the following paragraphs. While some of the following implementation examples are described in terms of an example computing device memory system, further example implementations may include: the example functions of the computing device memory system discussed in the following paragraphs implemented as methods of the following implementation examples; and the example computing device memory system discussed in the following paragraphs implemented by a computing device memory system including means for performing functions of the computing device memory system of the following implementation examples.

Example 1. A computing device memory system, having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

Example 2. The computing device memory system of example 1, in which the first IO voltage supply is a first dedicated IO voltage supply, and the second IO voltage supply is a second dedicated IO voltage supply.

Example 3. The computing device memory system of example 1, in which the first IO voltage supply is a dedicated IO voltage supply, and the second IO voltage supply is a shared IO voltage supply.

Example 4. The computing device memory system of any of examples 1-3, further including a first core voltage supply and a second core voltage supply, in which each of the first core voltage supply and the second core voltage supply are electrically connected to the memory device, and in which the shared IO voltage supply is electrically connected to the second core voltage supply.

Example 5. The computing device memory system of any of examples 1-4, further including a third core voltage supply, in which the third core voltage supply is electrically connected to the memory device, and in which a voltage of the second core voltage supply is greater than a voltage of the third core voltage supply.

Example 6. The computing device memory system of any of examples 1-3, further including a first core voltage supply, a second core voltage supply, and a third core voltage supply, in which each of the first core voltage supply, the second core voltage supply, and the third core voltage supply are electrically connected to the memory device, in which the shared IO voltage supply is electrically connected to the third core voltage supply, and in which a voltage of the second core voltage supply is greater than a voltage of the third core voltage supply.

Example 7. The computing device memory system of any of examples 1-5, in which a voltage of the second IO voltage supply is greater than a voltage of the first IO voltage supply.

Example 8. The computing device memory system of any of examples 1-7, in which the data of the memory transaction is binary data, and the memory device and the memory physical layer further convert between the binary data and 3 level PAM IO scheme signals using the first IO voltage supply and the second IO voltage supply.

Example 9. The computing device memory system of any of examples 1-8, in which the memory device encodes the data of the memory transaction for generating a 3 level PAM signal, and generates the 3 level PAM signal by controlling selective electrical connection of the first IO voltage supply, the second IO voltage supply, or a ground to a component of the memory device according to the encoded data.

Example 10. The computing device memory system of any of examples 1-9, in which the memory physical layer encodes the data of the memory transaction for generating a 3 level PAM signal, and generates the 3 level PAM signal by controlling selective electrical connection of the first IO voltage supply, the second IO voltage supply, or a ground to a component of the memory physical layer according to the encoded data.

The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the claims. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein, but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.