Hybrid inverting PWM power converters

A hybrid power converter includes a primary switching circuit, an LC circuit, and a secondary switching circuit. The primary switching circuit includes three or more switching transistors in series that may turn on or off according to a switching cycle to generate a series of voltage pulses at a connecting node between two switching transistors. The LC circuit may be coupled via the to the secondary switching circuits to the connecting node of the primary switching circuit. The LC circuit may receive, from the primary switching circuit, a series of pulses via the secondary switching circuits and may generate an inductor current in the LC circuit. The inductor current may charge a capacitor of the LC circuit to generate an output voltage of the hybrid power converter. The output voltage may have a reverse polarity with respect to an input voltage that may be coupled to the primary switching circuit.

FIELD OF THE DISCLOSURE

The disclosure relates generally to power converter circuits and, more particularly, to the power converter circuits providing reverse polarity between input and output voltages.

BACKGROUND

Hybrid power converter circuits provide efficient power solutions for power supply design. A hybrid power converter circuit is a type of power converter that provides direct current to direct current (DC-DC) conversion based on switched capacitor converters and inductor-based converters. A hybrid power converter contains one or more switching elements (e.g., one or more transistors) and reactive elements (e.g., capacitors and inductors) that, in connection with a periodic switching of the switching elements provides DC output voltage.

A shortcoming of existing power converters that provide reverse polarity between input and output voltages is that they may provide high voltage and/or current on the switches of the power converters and the power density may be limited by the sizes of magnetic components, including transformer and inductor sizes, that are used for providing the reverse polarity.

Accordingly, what is needed is a design for a higher efficiency converter, without adding considerable cost and complexity, which can provide reverse polarity between input and output voltages with lower voltage and/or current of the switches and at a higher switching frequency to increase power density.

SUMMARY OF THE DISCLOSURE

A hybrid power converter includes a primary switching circuit, an LC circuit, and one or more secondary switching circuits. The primary switching circuit includes three or more switching transistors in series that may turn on or off according to a switching cycle to generate a series of voltage pulses at a one or more connecting node between two switching transistors of the three or more switching transistors. The LC circuit that includes a capacitor and an inductor is series may be coupled via the one or more secondary switching circuits to one or more connecting nodes of the primary switching circuit. The LC circuit may receive, from the primary switching circuit, one or more series of pulses via the one or more secondary switching circuits and may generate an inductor current in the LC circuit. The inductor current may charge the capacitor of the LC circuit to generate an output voltage of the hybrid power converter. The output voltage may have a reverse polarity with respect to an input voltage that may be coupled to the primary switching circuit.

A hybrid power converter according to various implementations includes a primary switching circuit that includes three or more switching transistors that are connected in series and have a first end and a second end. Each one of the three or more switching transistors are linked to an adjacent transistor of the three or more switching transistors by a respective node of a first plurality of nodes. The first plurality of nodes include a first node, a second node, and a third node. The primary switching circuit also includes one or more capacitors that include a first capacitor. The first capacitor may be coupled to the second node. The first capacitor may be coupled across two of the three or more switching transistors that are connected in series. The primary switching circuit further includes a first flying capacitor that may be coupled to at least one of the first node and the third node of the first plurality of nodes. The hybrid power converter also include an LC circuit that comprises a third capacitor and an inductor connected in series. The LC circuit may be coupled to the primary switching circuit via a first secondary switching circuit. The LC circuit may receive a first voltage of the primary switching circuit via the first secondary switching circuit and may generate an output voltage across the third capacitor. The output voltage may have a reverse polarity with respect to an input voltage that may be coupled to the primary switching circuit.

A hybrid power converter according to various implementations comprises a primary switching circuit that includes three or more switching transistors connected in series. The hybrid power converter also includes at least one secondary switching circuit that is coupled between the primary switching circuit and an LC circuit. The hybrid power converter further includes the LC circuit that comprises a capacitor and an inductor connected in series. The LC circuit may be coupled across a switching transistor of the at least one secondary switching circuit. The LC circuit may receive a first voltage from the at least one secondary switching circuit and may generate, based on the first voltage, an essentially constant output voltage across the capacitor. The output voltage may have a reverse polarity with respect to an input voltage that may be coupled to the primary switching circuit. The at least one secondary switching circuit may be coupled to a node linking two adjacent switching transistors of the three or more switching transistors of the primary switching circuit. The at least one secondary switching circuit may receive a series of pulses from the primary switching circuit and may generate the first voltage for the LC circuit.

A method of operating a hybrid power converter according to various implementations comprises pre-charging one or more first capacitors of a primary switching circuit and one or more second capacitors of one or more secondary switching circuits to predefined respective voltages. After pre-charging, the method includes applying switching signals according to a switching cycle to three or more switching transistors of the primary switching circuit and to one or more switching transistors of the one or more secondary switching circuits. Applying switching signals may turn the three or more switching transistors of the primary switching circuit and the one or more switching transistors of the one or more secondary switching circuits on or off. The switching cycle may comprise two or more duty cycles for the switching signals. The method also includes providing a series of pulses by the primary switching circuit and through the one or more secondary switching circuits to an LC circuit. The LC circuit may comprise a capacitor and an inductor connected in series. The method includes adjusting the series of pulses by the one or more secondary switching circuits and providing a voltage across the capacitor of the LC circuit as an output voltage of the hybrid power converter. The output voltage may have a reverse polarity with respect to an input voltage that is coupled to the primary switching circuit. The method further includes adjusting at least one duty cycle of the two or more duty cycles of the switching signals to set the output voltage at a predefined and essentially constant value.

A hybrid power converter according to various implementations comprises means for applying switching signals to primary and secondary switching circuits and means for applying an input voltage to the primary switching circuit. The hybrid power converter includes means for providing a series of pulses to an LC circuit from the primary switching circuit and means for adjusting the series of pulses via the secondary switching circuit. The hybrid power converter also includes means for turning on or off switching transistors of the primary and secondary witching circuits with the switching signals and means for controlling a frequency and duty cycle of the series of pulses. The hybrid power converter further includes means for providing an essentially constant output voltage by the LC circuit. The output voltage may have a reverse polarity with respect to the input voltage.

Other aspects disclosed herein include corresponding methods, systems, apparatuses, and electronic device products for implementation of the hybrid power converter. It is understood that other configurations will become readily apparent to those skilled in the art from the following detailed description, wherein various exemplary configurations and implementations are shown and described by way of illustration.

DETAILED DESCRIPTION

Aspects and features, and exemplary implementations practices and applications are disclosed in the following description and related drawings. Alternatives to disclosed examples may be devised without departing from the scope of disclosed concepts.

The term “converter,” as used herein, encompasses but is not limited to any one of, or any combination of “regulator,” “DC regulator,” “voltage regulator,” “DC voltage regulator,” “DC-DC converter,” “DC converter” and “converter,” and includes, but is not limited to, the plain meaning of any one or more of these terms.

The subject disclosure provides a hybrid power converter that includes a primary switching circuit, an LC circuit, and one or more secondary switching circuits. The primary switching circuit includes three or more switching transistors in series. The three or more switching transistors of the primary switching circuit that are in series have a first end a second end. Each one of the three or more switching transistors may be connected to an adjacent switching transistor of the three or more switching transistors by a respective connecting node of a plurality of connecting nodes. An input voltage, e.g., a DC voltage, may be coupled between the first end and the second end where the second end may be grounded. A control circuit may be couple to the switching transistors to generate switching signals that may be provided to the switching transistors to turn on or off the switching transistors according to a switching cycle. The turning on or off the switching transistors may generate a series of voltage pulses between each one of the connecting nodes and the ground. In some embodiments, the switching transistors of the primary switching circuit turn on or off according to a switching cycle that comprises two or more switching signals where each one of the switching signals may have a different duty cycle such that two duty cycles can be inverse of each other and the switching signals may switched on or off the switching transistors of the primary switching circuit in phase opposition, e.g., complementary.

The secondary switching circuit may include two switching transistors that may switch in synchronization with switching transistors of the primary switching circuit with the two duty cycles. The LC circuit may be coupled to one or more connecting nodes of the primary switching circuit via the one or more secondary switching circuits. The one or more connecting nodes of the primary switching circuit may provide one or more series of pulses to the LC circuit to generate an inductor current in the LC circuit. The inductor current may vary and may increase and decrease. The inductor current may charge a capacitor of the LC circuit to generate an output voltage of the hybrid power converter. The output voltage of the hybrid power converter may have a reverse polarity with respect to the input voltage that is couples to the primary switching circuit.

FIGS. 1A and 1Bare circuit diagrams of an exemplary hybrid PWM buck converter and a switching signal of the hybrid PWM buck converter.FIG. 1Aincludes an exemplary hybrid PWM power converter, e.g., a hybrid PWM buck converter100. In some examples, hybrid PWM buck converter100includes a switching circuit130, which includes four switching transistors Q1, Q2, Q3, and Q4that are connected in series. Switching transistors Q1and Q3may switch on or off complementary to switching transistors Q2and Q4according to a switching cycle (e.g., at a predetermined switching frequency and duty cycle) to drive LC circuit140. In some examples, switching transistors Q1and Q3may switch on for a duration of Ton and may switch off for a duration of Toff providing duty cycle D=Ton/(Ton+Toff) for switching transistors Q1and Q3. In some examples switching transistors Q1and Q3and switching transistors Q2and Q4may be switched at a 50% duty cycle, wherein the switching transistors Q1and Q3is switched on or off in phase opposition to switching transistors Q2and Q4for exactly the same time period. In some examples, the duty cycle D of the switching transistors Q1and Q3is less than 50% and the duty cycle of the switching transistors Q2and Q4is more than 50% or vice versa. LC circuit140includes one or more inductors Ls and one or more capacitors Cs that are energized by each pulse from switching circuit130. In some embodiments, hybrid PWM buck converter100is an exemplary hybrid PWM buck converter and amplitude of the output voltage Vo is about ½ Vin times the duty cycle D. In some embodiments, capacitor Cs has a large value and provides filtering function, e.g., low pass filtering function, for the output voltage Vo of the hybrid PWM buck converter100.

FIG. 1Bincludes switching signals190of hybrid PWM buck converter ofFIG. 1A. Power flow through LC circuit140may be controlled by changing the switching duty cycle of switching transistors Q1and Q3and switching transistors Q2and Q4(e.g., by changing the duty cycle of the switching signals192and194).

As shown inFIG. 1A, switching circuit130further includes nodes112,114, and116that are coupled between two switching transistors and link the two switching transistors. Switching circuit130also includes nodes110and118that are coupled to one switching transistor. Node118couples a transistor to ground120and node110couples a transistor to input source Vin that is coupled between node110and ground120. Switching circuit130further includes flying capacitor Cfly that is coupled between nodes112and116and capacitor C1that is coupled between nodes114and118. In addition, LC circuit140is coupled between node116of switching circuit130and the ground. An output voltage is defined as the voltage across capacitor Cs that is coupled between node108of LC circuit140and ground120.

Hybrid PWM converter100may include, as depicted inFIG. 1A, a control circuit102configured to provide the switching signals106that can be coupled to gates of the transistors Q1-Q4. Switching signals106may provide switching signals192and194that are square wave signals. In some examples, control circuit102controls the frequency and duty cycle of the switching signals192and194. In some embodiments, the switching signals106of control circuit102, in addition to providing the switching signals of the switching transistors may provide control signals to control other switches of the hybrid PWM converter100and may connect or disconnect a portion of the hybrid PWM converter100.

According to various implementations, control circuit102may be a pulse-width modulation (PWM) controller that generates PWM signals to switching circuit130to switch the switching transistors (e.g., Q1-Q4) of the bridge on or off according to a predefined switching frequency and/or duty cycle. In this regard, control circuit102may include an input/output (I/O) interface104, and may be programmed (e.g., before start-up of the converter) with a predetermined switching frequency and/or duty cycle, for example, by way of the I/O interface104. Switching signals106, e.g., control signals, may be transmitted as first switching signal192by control circuit102to the gates of switching transistors Q land Q3to switch on Q1and Q3, respectively, and transmitted at a second switching signal194to switch off the transistors Q2and Q4.

In some embodiments, before switching of the switching transistor Q1-Q4, flying capacitor Cfly that is coupled between nodes112and116and capacitor C1that is coupled between nodes114and118are each pre-charged to ½ of Vin via a separate circuit that is controlled by control circuit102. The pre-charging of capacitors Cfly and C1may reduce high voltage and/or current of switching transistors during a start-up of the converter. Pre-charging of the capacitors is described with respect toFIGS. 10A and 10B.

In some examples, a voltage and/or current, e.g., an output voltage and/or an output current of a hybrid converter, or a voltage or current of an element of a hybrid converter, e.g., hybrid converter300, may be defined as within a percent range (e.g., 20 percent above or below) of a voltage value and/or current value that may be defined as an essentially constant voltage value and/or current value.

FIGS. 2A and 2Bare diagrams of an exemplary hybrid inverting PWM buck converter and a switching signal of the hybrid inverting PWM buck converter.FIG. 2Aincludes an exemplary hybrid PWM buck converter200. In some examples, hybrid PWM buck converter200includes a switching circuit230, which includes four switching transistors Q1, Q2, Q3, and Q4that are connected in series. Switching transistors Q1and Q3may switch on or off complementary to switching transistors Q2and Q4according to a switching cycle to drive LC circuit240. In some examples, switching transistors Q1and Q3may switch on for a duration of Ton and may switch off for a duration of Toff providing duty cycle D=Ton/(Ton+Toff) for switching transistors Q1and Q3and providing duty cycle 1-D for Q2and Q4. In some examples switching transistors Q1and Q3may be switched on or off in phase opposition to switching transistors Q2and Q4. LC circuit240may include one or more inductors Ls and one or more capacitors Cs that are energized by each pulse from switching circuit230. In some embodiments, hybrid PWM buck converter200is an exemplary hybrid PWM converter and amplitude of the output voltage Vo is about −Vin times (1-D) divided by (1+D). In some examples, when D is 50%, hybrid PWM buck converter200is an inverting buck converter providing an output amplitude of about −⅓ Vin. In some embodiments, capacitor Cs has a large value and provides filtering function, e.g., low pass filtering function, for the output voltage Vo of the hybrid PWM buck converter200and the LC circuit may generate an essentially constant output voltage. In some embodiments, the output voltage has a reverse polarity with respect to an input voltage Vin that is coupled to the primary switching circuit230. In some examples, the output voltage level, Vo, can be adjusted by changing D between 0.1 and 0.9, e.g., by setting D=0.5.

FIG. 2Bincludes switching signals290of hybrid PWM buck converter ofFIG. 2Athat are provided by control circuit102. Power flow through LC circuit240may be controlled by changing the switching duty cycle of switching transistors Q1and Q3and switching transistors Q2and Q4.

As shown inFIG. 2A, switching circuit230includes nodes112,114, and116that are coupled between two switching transistors and link the two switching transistors. Switching circuit230also includes nodes110and118that are coupled to one switching transistor. Input source Vin is coupled between node118and ground120and thus is coupled between switching transistor Q4and ground120. Node110that is coupled to switching transistor Q1is also coupled to LC circuit240. In some embodiments, LC circuit240is coupled between nodes110and112of switching circuit230and the ground120as well. Switching circuit230further includes flying capacitor Cfly that is coupled between nodes112and116, capacitor C1that is coupled between nodes110and114, and capacitor C2that is coupled between nodes114and118. An output voltage is defined as the voltage across capacitor Cs that is coupled between node108of LC circuit240and ground120. In some embodiments, switching circuit230includes one of the capacitors C1or C2. In some examples, capacitors C1, C2, and Cfly are between 1 micro farad and 20 micro farads, e.g. 8 micro farads or 16 micro farads.

In some embodiments, before switching of the switching transistors Q1-Q4, flying capacitor Cfly that is coupled between nodes112and116, capacitor C1that is coupled between nodes110and114, and capacitor C2that is coupled between nodes114and118are each pre-charged to ½ of (|Vin|+|Vo|) via a separate circuit that is controlled by control circuit102. The pre-charging of capacitors Cfly, C1, C2may limit high voltage or current of the switching transistors during a start-up of the converter. Pre-charging of the capacitors is described with respect toFIGS. 10A and 10B. In some embodiments, pre-charging may limit voltage value of switching transistors Q1-Q4to ½(|Vin|+|Vo|).

FIGS. 3A and 3Bare diagrams of an exemplary hybrid inverting PWM buck converter and a switching signal of the hybrid inverting PWM buck converter.FIG. 3Aincludes an exemplary hybrid PWM buck converter300. In some examples, hybrid PWM buck converter300includes a switching circuit330, which includes four switching transistors Q1, Q2, Q3, and Q4that are connected in series. Switching transistors Q1and Q3may switch on or off complementary to switching transistors Q2and Q4according to a switching cycle to drive LC circuit340. In some examples, switching transistors Q1and Q3may switch on for a duration of Ton and may switch off for a duration of Toff providing duty cycle D=Ton/(Ton+Toff) for switching transistors Q1and Q3and providing duty cycle 1-D for Q2and Q4. LC circuit340may include one or more inductors Ls and one or more capacitors Cs that are energized by each pulse from switching circuit330. In some embodiments, hybrid PWM buck converter300is an exemplary hybrid PWM converter and amplitude of the output voltage Vo is about −Vin times D. In some examples, when D is 50%, hybrid PWM buck converter300is an inverting buck converter providing an output amplitude Vo that is about −½ Vin. In some embodiments, capacitor Cs has a large value and provides filtering function for the output voltage Vo of the hybrid PWM buck converter300and the LC circuit may generate an essentially constant output voltage. In some embodiments, the output voltage has a reverse polarity with respect to an input voltage Vin that is coupled to the primary switching circuit330.

FIG. 3Bincludes switching signals390of hybrid PWM buck converter ofFIG. 3Athat are provided by control circuit102. Power flow through LC circuit340may be controlled by changing the switching duty cycle of switching transistors Q1and Q3and switching transistors Q2and Q4.

As shown inFIG. 3A, switching circuit330includes nodes112,114, and116that are coupled between two switching transistors and link the two switching transistors. Switching circuit330also includes nodes110and118that are coupled to one switching transistor. Input source Vin that is coupled between node118and ground120is thus coupled between switching transistor Q4and ground120. Node112that is coupled between switching transistors Q1and Q2is also coupled to LC circuit340. In some embodiments, LC circuit340is coupled between nodes112and114of switching circuit330where node114is coupled to ground120and thus the input source Vin is coupled across two of the switching transistors Q3and Q4. Switching circuit330further includes flying capacitor Cfly that is coupled between nodes112and116, capacitor C1that is coupled between nodes110and114, and capacitor C2that is coupled between nodes114and118. An output voltage Vo may be provided as the voltage across capacitor Cs that is coupled between node108of LC circuit340and ground120. In some embodiments, switching circuit330includes one of the capacitors C1or C2.

In some embodiments, before switching of the switching transistors Q1-Q4, flying capacitor Cfly that is coupled between nodes112and116, capacitor C1that is coupled between nodes110and114, and capacitor C2that is coupled between nodes114and118are each pre-charged to |Vin| via a separate circuit that is controlled by control circuit102. The pre-charging of capacitors Cfly, C1, C2may reduce high voltage or current of the switching transistors during a start-up of the converter. Pre-charging of the capacitors is described with respect toFIGS. 10A and 10B. In some embodiments, pre-charging may limit voltage value of switching transistors Q1-Q4to |Vin|.

FIGS. 4A and 4Bare diagrams of an exemplary hybrid inverting PWM buck converter and a switching signal of the hybrid inverting PWM buck converter.FIG. 4Aincludes an exemplary hybrid PWM buck converter400. In some examples, hybrid PWM buck converter400includes a switching circuit430, which includes four switching transistors Q1, Q2, Q3, and Q4that are connected in series. Switching transistors Q1and Q3may switch on or off complementary to switching transistors Q2and Q4according to a switching cycle to drive LC circuit440. In some examples, switching transistors Q1and Q3may switch on for a duration of Ton and may switch off for a duration of Toff providing duty cycle D=Ton/(Ton+Toff) for switching transistors Q1and Q3and providing duty cycle 1-D for Q2and Q4. LC circuit440may include one or more inductors Ls and one or more capacitors Cs that are energized by each pulse from switching circuit330. In some embodiments, hybrid PWM buck converter400is an exemplary hybrid PWM converter and amplitude of the output voltage Vo is about −Vin times (1-D). In some examples, when D is 50%/o, hybrid PWM buck converter400is an inverting buck converter providing an output amplitude Vo that is about −½ Vin. In some embodiments, capacitor Cs has a large value and provides filtering function for the output voltage Vo of the hybrid PWM buck converter400and the LC circuit may generate an essentially constant output voltage. In some embodiments, the output voltage has a reverse polarity with respect to an input voltage Vin that is coupled to the primary switching circuit430.

FIG. 4Bincludes switching signals490of hybrid PWM buck converter ofFIG. 4Athat are provided by control circuit102. Power flow through LC circuit340may be controlled by changing the switching duty cycle of switching transistors Q1and Q3and switching transistors Q2and Q4.

As shown inFIG. 4A, switching circuit430includes nodes112,114, and116that are coupled between two switching transistors and link the two switching transistors. Switching circuit430also includes nodes110and118that are coupled to one switching transistor. Input source Vin that is coupled between node110and ground120is thus coupled between switching transistor Q1and ground120. Node114that is coupled between switching transistors Q2and Q3is also coupled to LC circuit440. In some embodiments, LC circuit440is coupled between nodes114and116of switching circuit430where node114is coupled to ground120and thus the input source Vin is coupled across two of the switching transistors Q1and Q2. Switching circuit430further includes flying capacitor Cfly that is coupled between nodes112and116, capacitor C1that is coupled between nodes110and114, and capacitor C2that is coupled between nodes114and118. An output voltage Vo may be defined as the voltage across capacitor Cs that is coupled between node108of LC circuit340and ground120. In some embodiments, switching circuit430includes one of the capacitors C1or C2.

In some embodiments, before switching of the switching transistors Q1-Q4, flying capacitor Cfly that is coupled between nodes112and116, capacitor C1that is coupled between nodes110and114, and capacitor C2that is coupled between nodes114and118are each pre-charged to |Vin| via a separate circuit that is controlled by control circuit102. The pre-charging of capacitors Cfly, C1, C2may limit, e.g., reduce, high voltage or current of the switching transistors during a start-up of the converter. Pre-charging of the capacitors is described with respect toFIGS. 10A and 10B. In some embodiments, pre-charging may limit voltage value of switching transistors Q1-Q4to |Vin|.

FIGS. 5A and 5Bare diagrams of an exemplary hybrid inverting PWM boost converter and a switching signal of the hybrid inverting PWM boost converter.FIG. 5Aincludes the same components ofFIG. 3Awith the exception that capacitor Cs instead of being coupled between nodes108and ground120is coupled between node118and ground120. Input source Vin is coupled between nodes108and ground120and output voltage Vo is defined across capacitor Cs from node118to ground120. In some embodiments, the output voltage has a reverse polarity with respect to an input voltage Vin. In some embodiments,FIG. 5Aincludes hybrid PWM boost converter500that generated an output voltage Vo having an amplitude that is −Vin divided by (1-D). In some examples, when D is 50%, hybrid PWM boost converter500is an inverting boost converter providing an output amplitude Vo that is Vo=−2*Vin.

FIG. 5Bincludes a diagram590of exemplary a switching signals of hybrid PWM boost converter ofFIG. 5Athat are provided by control circuit102. Power flow through LC circuit540may be controlled by changing the switching frequency of switching transistors Q1and Q3and switching transistors Q2and Q4, changing the duty cycle, or both.

In some embodiments, before switching of the switching transistors Q1-Q4, flying capacitor Cfly that is coupled between nodes112and116, capacitor C1that is coupled between nodes110and114, and capacitor C2that is coupled between nodes114and118are each pre-charged to |Vo| via a separate circuit that is controlled by control circuit102. The pre-charging of capacitors Cfly, C1, C2may reduce high voltage and/or current of switching transistors during a start-up of the converter. In some embodiments, switching circuit530includes one of the capacitors C1or C2. Pre-charging of the capacitors is described with respect toFIGS. 10A and 10B. In some embodiments, pre-charging may limit voltage value of switching transistors Q1-Q4to |Vo|.

FIGS. 6A and 6Bare diagrams of an exemplary hybrid inverting PWM buck converter and a switching signal of the hybrid inverting PWM buck converter.FIG. 6Aincludes an exemplary hybrid PWM buck converter600. In some examples, hybrid PWM buck converter600includes a primary switching circuit630, which includes four switching transistors Q1, Q2, Q3, and Q4that are connected in series. Switching transistors Q1and Q3may switch on or off complementary to switching transistors Q2and Q4according to a switching cycle to drive LC circuit640. In some examples, switching transistors Q1and Q3may switch on for a duration of Ton and may switch off for a duration of Toff providing duty cycle D=Ton/(Ton+Toff) for switching transistors Q1and Q3and providing duty cycle 1-D for Q2and Q4. In some examples, hybrid PWM buck converter600includes one secondary switching circuit655, which includes two switching transistors Q5and Q6. Switching transistor Q5may switch in synchronization with Q1and Q3and switching transistor Q6may switch in synchronization with transistors Q2and Q4according to a switching cycle to drive LC circuit640. The secondary switching circuit may adjust a series of voltage pulses received from the primary switching circuit630to provide the series of voltage pulses to the LC circuit. LC circuit640may include one or more inductors Ls and one or more capacitors Cs that are energized by each pulse from primary switching circuit630. In some embodiments, hybrid PWM buck converter600is an exemplary hybrid PWM converter and amplitude of the output voltage Vo is about −½Vin times D. In some examples, when D is 50%, hybrid PWM buck converter600is an inverting buck converter providing an output amplitude Vo that is about −¼Vin. In some embodiments, capacitor Cs has a large value and provides filtering function for the output voltage Vo of the hybrid PWM buck converter600and the LC circuit may generate an essentially constant output voltage. In some embodiments, the output voltage has a reverse polarity with respect to an input voltage Vin that is coupled to the primary switching circuit630.

FIG. 6Bincludes switching signals690of hybrid PWM buck converter ofFIG. 6Athat are provided by control circuit102. Power flow through LC circuit640may be controlled by changing the switching duty cycle of switching transistors Q1, Q3.

As shown inFIG. 6A, primary switching circuit630includes nodes112,114, and116that are coupled between two switching transistors and link the two switching transistors. Primary switching circuit630also includes nodes110and118that are coupled to one switching transistor. Input source Vin is coupled between node118and node110where node110is coupled to ground120and thus source Vin is coupled across switching transistors Q1-Q4. Node112that is coupled between switching transistors Q1and Q2is also coupled to secondary switching circuit655and the secondary switching circuit655is coupled to LC circuit640. In some embodiments, LC circuit640is coupled between nodes602of secondary switching circuit655and ground120. Primary switching circuit630further includes first flying capacitor Cfly1that is coupled between nodes112and116, capacitor C1that is coupled between nodes110and114, and capacitor C2that is coupled between nodes114and118. In some embodiments, secondary switching circuit655is coupled between primary switching circuit630and LC circuit640. Secondary switching circuit655includes node602that is coupled between two switching transistors Q5and Q6and links the two switching transistors. Secondary switching circuit655also includes node604that is coupled to switching transistor Q5. Switching transistor Q6of secondary switching circuit655is coupled between node602and ground120. Secondary switching circuit655further includes second flying capacitor Cfly2that is coupled between nodes112and602and capacitor C3that is coupled between nodes604and ground120. In some examples, secondary switching circuit655may create a path for discharging the pulses received from primary switching circuit630to ground and thus reducing output voltage Vo. An output voltage Vo may be defined as the voltage across capacitor Cs that is coupled between node108of LC circuit640and ground120. In some embodiments, switching circuit630includes one of the capacitors C1or C2.

In some embodiments, before switching of the switching transistors Q1-Q6, first flying capacitor Cfly1that is coupled between nodes112and116, capacitor C1that is coupled between nodes110and114, capacitor C2that is coupled between nodes114and118, second flying capacitor Cfly2that is coupled between nodes112and602, and capacitor C3that is coupled between nodes604and ground120each may be pre-charged to ½*|Vin| via a separate circuit that is controlled by control circuit102. The pre-charging of capacitors Cfly1, Cfly2, C1, C2, and C3may reduce high voltage and/or current of switching transistors during a start-up of the converter. Pre-charging of the capacitors is described with respect toFIGS. 10A and 10B. In some embodiments, pre-charging may limit voltage value of switching transistors Q1-Q6to ½*|Vin|.

FIGS. 7A and 7Bare diagrams of an exemplary hybrid inverting PWM buck converter and a switching signal of the hybrid inverting PWM buck converter.FIG. 7Aincludes an exemplary hybrid PWM buck converter700. In some examples, hybrid PWM buck converter700includes a primary switching circuit730, which includes four switching transistors Q1, Q2, Q3, and Q4that are connected in series. Switching transistor Q1may switch on or off complementary to switching transistor Q2according to a switching cycle to drive LC circuit740. Additionally, switching transistor Q3may switch on or off complementary to switching transistor Q4according to the switching cycle to drive LC circuit740. In some examples, however, as shown inFIG. 7B, there is a time delay752, e.g., a phase difference, between switching signals of switching transistors Q1and Q3and thus Q2and Q4. In some examples, the time delay is used to control a ripple of a DC output voltage of the hybrid inverting PWM power converter. In some examples, switching transistors Q1, Q3, Q5, and Q7may switch on for a duration of Ton and may switch off for a duration of Toff providing duty cycle D=Ton/(Ton+Toff) for switching transistors Q1, Q3, Q5, and Q7and providing duty cycle 1-D for Q2, Q4, Q6, and Q8. In some examples, the phase difference between switching signals of switching transistors Q1and Q3and thus Q2and Q4is less than 180 degrees. In some embodiments, the switching cycle includes one or more switching duty cycles for the switching transistors Q1-Q8. In some examples, one or more duty cycles are equal or complementary.

In some examples, hybrid PWM buck converter700includes a switching circuit755, which includes two secondary switching circuits with four switching transistors Q5, Q6, Q7and Q8. Switching transistor Q5may switch in synchronization with Q1and switching transistor Q6may switch in synchronization with Q2. Switching transistor Q7may switch in synchronization with Q3and switching transistor Q8may switch in synchronization with Q4according to a switching cycle to drive switching circuit755. LC circuit740may include one or more inductors, e.g., two inductors Ls1and Ls2, and one or more capacitors, e.g., one capacitor Cs, that are energized by each pulse from primary switching circuit730and via switching circuit755. In some embodiments, hybrid PWM buck converter700is an exemplary hybrid PWM converter and amplitude of the output voltage Vo is about −½Vin times D. In some examples, when D is 50%, hybrid PWM buck converter700is an inverting buck converter providing an output amplitude Vo that is about −¼Vin. In some embodiments, capacitor Cs has a large value and provides filtering function for the output voltage Vo of the hybrid PWM buck converter700and the LC circuit may generate an essentially constant output voltage. In some embodiments, the output voltage has a reverse polarity with respect to an input voltage Vin that is coupled to the primary switching circuit730.

FIG. 7Bincludes switching signals790of hybrid PWM buck converter ofFIG. 7Athat are provided by control circuit102. Power flow through LC circuit740may be controlled by changing the switching duty cycle of switching transistors Q1, and Q5, Q2and Q6, Q3and Q7, and Q4and Q8.

As shown inFIG. 7A, primary switching circuit730includes nodes112,114, and116that are coupled between two switching transistors and link the two switching transistors. Primary switching circuit730also includes nodes110and118that are coupled to one switching transistor. Input source Vin is coupled between node118and node110where node110is coupled to ground120and thus source Vin is coupled across switching transistors Q1-Q4. Node112that is coupled between switching transistors Q1and Q2is also coupled to a first secondary switching circuit and the first secondary switching circuit is coupled to LC circuit740. In some embodiments, LC circuit740is coupled between node702of first secondary switching circuit and ground120and node706of second secondary switching circuit and ground120. Primary switching circuit730includes capacitor C1that is coupled between nodes110and114, and capacitor C2that is coupled between nodes114and118. Switching circuit755includes first flying capacitor Cfly1that is coupled between nodes116and706of second secondary switching circuit, second flying capacitor Cfly2that is coupled between nodes112and702of first secondary switching circuit. In some embodiments, switching circuit755is coupled between primary switching circuit730and LC circuit740. Switching circuit755includes node702that is coupled between two switching transistors Q5and Q6and links the two switching transistors. Switching circuit755also includes node704that is coupled to switching transistor Q5. Switching transistor Q6of switching circuit755is coupled between node702and ground120. Switching circuit755further includes capacitor C3that is coupled between nodes704and ground120and also includes capacitor C4that is coupled between nodes708and ground120. In some examples, switching circuit755may create a path for discharging the pulses received from primary switching circuit730to ground and thus reducing output voltage Vo. An output voltage Vo may be defined as the voltage across capacitor Cs that is coupled between node108of LC circuit740and ground120. In some examples, nodes704and708are coupled via connection710and thus capacitors C3and C4may be coupled in parallel. In some embodiments, switching circuit730includes one of the capacitors C1or C2.

In some embodiments, before switching of the switching transistors Q1-Q8, second flying capacitor Cfly2that is coupled between nodes112and702, capacitor C1that is coupled between nodes110and114, capacitor C2that is coupled between nodes114and118, capacitor C3that is coupled between nodes704and ground120, and capacitor C4that is coupled between nodes708and ground120each may be pre-charged to ½*|Vin|, and first flying capacitor Cfly that is coupled between nodes116and706may be pre-charged to |Vin|, via a separate circuit that is controlled by control circuit102. The pre-charging of capacitors Cfly1, Cfly2, C1, C2, C3, and C4may reduce high voltage and/or current of switching transistors during a start-up of the converter. Pre-charging of the capacitors is described with respect toFIGS. 10A and 10B. In some embodiments, pre-charging may limit voltage value of switching transistors Q1-Q8to ½*|Vin|.

FIGS. 8A and 8Bare diagrams of an exemplary hybrid inverting PWM buck converter and a switching signal of the hybrid inverting PWM buck converter.FIG. 8Aincludes an exemplary hybrid PWM buck converter800. In some examples, hybrid PWM buck converter800includes a primary switching circuit830, which includes three switching transistors Q1, Q2, and Q4that are connected in series. Switching transistor Q1and Q4may switch on or off synchronously and switching transistor Q2may switch on or off with a time delay892, e.g., a phase difference, with respect to switching transistors Q1and Q4according to a switching cycle as shown inFIG. 8Bto drive LC circuit840. In some examples, the time delay is used to control a ripple of a DC output voltage of the hybrid inverting PWM power converter. In some examples, switching transistors Q1, Q2, Q4, Q5, and switching transistor Q7may switch on for a duration of Ton and may switch off for a duration of Toff providing duty cycle D=Ton/(Ton+Toff) for switching transistors Q1, Q2, Q4, Q5, and Q7and providing duty cycle 1-D for Q6and Q8. In some examples, duty cycle D is limited to a value of less or equal to 0.5.

In some examples, hybrid PWM buck converter800includes a switching circuit855, which includes two secondary switching circuits with four switching transistors Q5, Q6, Q7and Q8. Switching transistor Q5may switch in synchronization with Q1and switching transistor Q6may switch in phase opposition to switching transistors Q1and Q5. Switching transistor Q7may switch in synchronization with Q2and switching transistor Q8may switch in phase opposition to switching transistors Q2and Q7according to a switching cycle to drive switching circuit855. LC circuit840may include one or more inductors, e.g., two inductors Ls1and Ls2, and one or more capacitors, e.g., one capacitor Cs, that are energized by each pulse from primary switching circuit830and via switching circuit855. In some embodiments, hybrid PWM buck converter800is an exemplary hybrid PWM converter and amplitude of the output voltage Vo is about −½Vin times D. In some examples, when D is 50%, hybrid PWM buck converter800is an inverting buck converter providing an output amplitude Vo that is about −¼Vin. In some embodiments, capacitor Cs has a large value and provides filtering function for the output voltage Vo of the hybrid PWM buck converter800and the LC circuit may generate an essentially constant output voltage. In some embodiments, the output voltage has a reverse polarity with respect to an input voltage Vin that is coupled to the primary switching circuit830.

FIG. 8Bincludes switching signals890of hybrid PWM buck converter ofFIG. 8Athat are provided by control circuit102. Power flow through LC circuit840may be controlled by changing the switching duty cycle of switching transistors Q1, Q4, Q5, Q6, Q2, Q7, and Q8.

As shown inFIG. 8A, primary switching circuit830includes nodes112, and114that are coupled between two switching transistors and link the two switching transistors. Primary switching circuit830also includes nodes110and118that are coupled to one switching transistor. Input voltage source Vin is coupled between node118and node110where node110is coupled to ground120and thus input source Vin is coupled across switching transistors Q1, Q2, and Q4. Node112that is coupled between switching transistors Q1and Q2is also coupled to a first secondary switching circuit and the first secondary switching circuit is coupled to LC circuit840. In some embodiments, LC circuit840is coupled between node802of first secondary switching circuit and ground120and node806of second secondary switching circuit and ground120. Switching circuit855includes first flying capacitor Cfly1that is coupled between nodes114and806and second flying capacitor Cfly2that is coupled between nodes112and802. In some embodiments, switching circuit855is coupled between primary switching circuit830and LC circuit840. Switching circuit855includes node802that is coupled between two switching transistors Q5and Q6and links the two switching transistors. Switching circuit855also includes node804that is coupled to switching transistor Q5. Switching transistor Q6of switching circuit855is coupled between node802and ground120. Switching circuit855further includes capacitor C1that is coupled between nodes804and ground120and also includes capacitor C2that is coupled between nodes808and ground120. In some examples, switching circuit855may create a path for discharging the pulses received from primary switching circuit830to ground and thus reducing output voltage Vo. An output voltage Vo may be defined as the voltage across capacitor Cs that is coupled between node108of LC circuit840and ground120. In some examples, nodes804and808are coupled via connection810and thus capacitors C1and C2may be coupled in parallel.

In some embodiments, before switching of the switching transistors Q1, Q2, and Q4-Q8, second flying capacitor Cfly2that is coupled between nodes112and802, capacitor C1that is coupled between nodes804and ground120, and capacitor C2that is coupled between nodes808and ground120each may be pre-charged to ½*|Vin|, and first flying capacitor Cfly1that is coupled between nodes114and806may be pre-charged to |Vin|, via a separate circuit that is controlled by control circuit102. The pre-charging of capacitors Cfly1, Cfly2, C1, and C2may reduce high voltage and/or current of switching transistors during a start-up of the converter. Pre-charging of the capacitors is described with respect toFIGS. 10A and 10B. In some embodiments, pre-charging may limit voltage value of switching transistors Q1and Q4-Q8to ½*|Vin| and may limit voltage value of switching transistor Q2to |Vin|.

FIGS. 9A and 9Bare diagrams of an exemplary hybrid inverting PWM buck converter and a switching signal of the hybrid inverting PWM buck converter.FIG. 9Aincludes an exemplary hybrid PWM buck converter900. In some examples, hybrid PWM buck converter900includes a primary switching circuit930, which includes four switching transistors Q1, Q2, Q3, Q4, and Q0that are connected in series. Switching transistor Q1may switch on or off in synchronization with switching transistors Q3and Q0according to a switching cycle to drive LC circuit940. Additionally, switching transistor Q2may switch on or off in synchronization with switching transistor Q4according to the switching cycle to drive LC circuit940. In some examples, however, as shown inFIG. 9B, there is a time delay992, e.g., a phase difference, between switching signals of switching transistors Q1, Q3, and Q0with switching signals of switching transistors Q2and Q4. In some examples, the time delay is used to control a ripple of a DC output voltage of the hybrid inverting PWM power converter. In some examples, switching transistors Q1, Q2, Q3, Q4, and Q0may switch on for a duration of Ton and may switch off for a duration of Toff providing duty cycle D=Ton/(Ton+Toff) for switching transistors Q0, Q1, Q2, Q3, Q4, Q5, Q7, Q9, and Q11and providing duty cycle 1-D for Q6, Q8, Q10, and Q12. In some examples, the phase difference between switching signals of switching transistors Q1, Q3, and Q0with switching signals of switching transistors Q2and Q4is less than 180 degrees. In some examples, duty cycle D is limited to a value of less or equal to 0.5.

In some examples, hybrid PWM buck converter900includes a switching circuit955, which includes four secondary switching circuits with eight switching transistors Q5, Q6, Q7, Q8, Q9, Q10, Q11, and Q12. Switching transistors Q5and Q9may switch on or off in synchronization with Q1and switching transistors Q6and Q10may switch on or off complementary to switching transistors Q5and Q9. Switching transistor Q7and Q11may switch in synchronization with switching transistors Q2and Q4and switching transistors Q8and Q12may switch on or off complementary to switching transistors Q7and Q11according to a switching cycle to drive switching circuit955. LC circuit940may include one or more inductors, e.g., four inductors Ls, Ls2, Ls3and Ls4, and one or more capacitors, e.g., one capacitor Cs, that are energized by each pulse from primary switching circuit930and via switching circuit955. In some embodiments, hybrid PWM buck converter900is an exemplary hybrid PWM converter and amplitude of the output voltage Vo is about −¼Vin times D. In some examples, when D is 50%, hybrid PWM buck converter900is an inverting buck converter providing an output amplitude Vo that is about −⅛Vin. In some embodiments, capacitor Cs has a large value and provides filtering function for the output voltage Vo of the hybrid PWM buck converter900and the LC circuit may generate an essentially constant output voltage. In some embodiments, the output voltage has a reverse polarity with respect to an input voltage Vin that is coupled to the primary switching circuit930.

FIG. 9Bincludes switching signals990of hybrid PWM buck converter ofFIG. 9Athat are provided by control circuit102. Power flow through LC circuit940may be controlled by changing the switching duty cycle of switching transistors Q1-Q12.

As shown inFIG. 9A, primary switching circuit930includes nodes112,114,116, and118that are coupled between two switching transistors and link the two switching transistors. Primary switching circuit930also includes nodes110and920that are coupled to one switching transistor. Input voltage source Vin is coupled between node920and node110where node110is coupled to ground120and thus voltage source Vin is coupled across five switching transistors Q0-Q4. Node112that is coupled between switching transistors Q1and Q2is also coupled to a first secondary switching circuit and the first secondary switching circuit is coupled to LC circuit940. In some embodiments, LC circuit940is coupled between node902of first secondary switching circuit and ground120, between node906of second secondary switching circuit and ground120, between node908of third secondary switching circuit and ground120, and between node910of fourth secondary switching circuit and ground120. Switching circuit955includes capacitor C1that is coupled between node904and ground120. Switching circuit955further includes first flying capacitor Cfly1that is coupled between nodes112and902, second flying capacitor Cfly2that is coupled between nodes114and906, third flying capacitor Cfly3that is coupled between nodes116and908, and fourth flying capacitor Cfly4that is coupled between nodes118and910. In some embodiments, switching circuit955is coupled between primary switching circuit930and LC circuit940. Switching circuit955may include node902that is coupled between two switching transistors Q5and Q6and links the two switching transistors. Switching circuit955may also include node904that is coupled to switching transistor Q5. Switching transistor Q6of switching circuit955is coupled between node902and ground120. Additionally, switching circuit955may include: i) node906that is coupled between two switching transistors Q7and Q8and links the two switching transistors, ii) node908that is coupled between two switching transistors Q9and Q10and links the two switching transistors, and iii) node910that is coupled between two switching transistors Q11and Q12and links the two switching transistors. In some examples, switching circuit955may create a path for discharging the pulses received from primary switching circuit930to ground and thus reducing output voltage Vo. An output voltage Vo may be defined as the voltage across capacitor Cs that is coupled between node108of LC circuit940and ground120. In some examples, one end of switching transistors Q5, Q7, Q9, and Q11are all coupled to node904of capacitor C1and thus capacitor C1is coupled between switching transistors Q5, Q7, Q9, and Q11and ground120.

In some embodiments, before switching of the switching transistors Q1-Q12, capacitor C1that is coupled between node904and ground120may be pre-charge to ¼*|Vin|, first flying capacitor Cfly1that is coupled between nodes112and902may be pre-charge to ¼*|Vin|, second flying capacitor Cfly2that is coupled between nodes114and906may be pre-charge to ½*|Vin|, third flying capacitor Cfly3that is coupled between nodes116and908may be pre-charge to ¾*|Vin|, and fourth flying capacitor Cfly4that is coupled between nodes118and910may be pre-charged to |Vin| via a separate circuit that is controlled by control circuit102. The pre-charging of capacitors C1, Cfly1, Cfly2, Cfly3, and Cfly4may reduce high voltage and/or current of switching transistors during a start-up of the converter. Pre-charging of the capacitors is described with respect toFIGS. 10A and 10B. In some embodiments, pre-charging may limit voltage value of switching transistors Q2, Q3, Q4to ½*|Vin|.

FIGS. 10A and 10Bare diagrams of an exemplary hybrid PWM converter with a pre-charging circuit for charging the capacitors. In some embodiments, a pre-charging circuit, e.g., pre-charging circuit ofFIG. 10A or 10Bis initially applied to hybrid power converters ofFIGS. 2A-9Awhen the switching transistors are turned off to pre-charge the capacitors. After pre-charging the capacitors, hybrid power converters ofFIGS. 2A-9Amay start switching on or off.FIG. 10Ashows primary switching circuit1030with three capacitors Cfly, C1, and C2. As s shown in hybrid PWM buck converter1000ofFIG. 10A, the three capacitors Cfly, C1, and C2may be charged via current sources i1, i2, and i3when the switching transistors Q1-Q4are off. In some embodiments, control circuit102, in addition to providing the switching signals of the switching transistors may provide control signals to control other switches of the hybrid PWM converter1000and to connect or disconnect current sources i1, i2, and i3. In some examples, after hybrid power converters ofFIGS. 2A-9Astart switching on or off a switching duty cycle of the switching transistors may be increased to increase an output voltage of the hybrid power converter to a predefined value. In some examples, the duty cycle of the switching transistors may be increased according to a predefined pattern, e.g., a gradual increase pattern.

FIG. 10Bshows primary switching circuit1035with two capacitors C1, and C2and switching circuit1055having two secondary switching circuits and four capacitors Cfly1, Cfly2, C3, and C4. As shown in hybrid PWM buck converter1050ofFIG. 10B, the six capacitors Cfly1, Cfly2, C1, C2, C3, and C4may be charged via current sources i1, i2, i3, i4, i5, and i6when the switching transistors Q1-Q8are off. In some embodiments, control circuit102, in addition to providing the switching signals of the switching transistors Q1-Q8may provide control signals to control other switches of the hybrid PWM converter1050and to connect or disconnect current sources i1, i2, i3, i4, i5, and i6.

FIG. 11is a flowchart of an exemplary process for providing a reverse polarity output voltage in a hybrid inverting PWM power converter circuit, according to some implementations described herein. For explanatory purposes, the various blocks of exemplary process1100are described herein with reference toFIGS. 2A-4AandFIGS. 6A-9A, and the components and/or processes described herein. The one or more of the blocks of process1100may be implemented, for example, by any of the various power converter circuits described herein. In some implementations, one or more of the blocks may be implemented apart from other blocks, and by one or more different processors or devices. Further for explanatory purposes, the blocks of exemplary process1100are described as occurring in serial, or linearly. However, multiple blocks of exemplary process1100may occur in parallel. In addition, the blocks of exemplary process1100need not be performed in the order shown and/or one or more of the blocks of exemplary process1100need not be performed.

The process1100begins at step1102; first capacitors of a primary switching circuit and second capacitors of one or more secondary switching circuits are pre-charged. The pre-charging may be performed by connecting a pre-charging circuit that includes one or more current sources to the capacitors of the primary switching circuit and to the capacitors of the one or more secondary switching circuits. Pre-charging is described with respect toFIGS. 10A and 10B. In some embodiments, during pre-charging the switching transistors of the primary switching circuit and the secondary switching circuits are turned off. In some embodiments, control circuit102may turn off the switching transistors of primary switching circuits230,330,430,530,630,730,830, and930ofFIGS. 2A-9Aduring pre-charging. In some embodiments, control circuit102may connect the pre-charging circuit to the capacitors, e.g., capacitors Cfly, C1, and C2of the primary switching circuits to pre charge the capacitors. After pre-charging, the control circuit may disconnect the pre-charging circuit and may start switching the switching transistors of the primary switching circuits230,330,430,530,630,730,830, and930. In some embodiments, control circuit102may turn off the switching transistors of switching circuits655,755,855, and955ofFIGS. 6A-9Aduring pre-charging. In some embodiments, control circuit102may connect the pre-charging circuit to the capacitors of the secondary switching circuits to pre-charge the capacitors, e.g., to pre-charge capacitors Cfly2and C3of switching circuit655. After pre-charging, the control circuit may disconnect the pre-charging circuit and may start switching the switching transistors of switching circuits655,755,855, and955. In some examples, an input voltage source Vin is coupled the primary switching circuits and the one or more capacitors of the primary and secondary switching circuits are pre-charged to a fraction of |Vin| or may be pre-charged to |Vin|. In some embodiments, the pre-charging prevents high voltage values across the switching transistors of the primary and secondary switching circuits at an initial stage of starting a hybrid power converter.

In step1104, switching signals are applied according to a switching cycle to switching transistors of the primary switching circuit and the secondary switching circuits. In some examples as shown inFIG. 7A, the switching signals may be applied to four switching transistors Q1-Q4of primary switching circuit730and to four switching transistors Q5-Q8of two secondary switching circuits of switching circuit755. A primary switching circuit may include three or more switching transistors that are connected in series and a secondary switching circuit may include two or more switching transistors. The primary and secondary switching circuits are shown inFIG. 2A-9A. Primary switching circuits230,330,430,530,630, and730include four switching transistors Q1-Q4that are connected in series. The switching signals are shown as switching signals290,390,490,590,690,790,890, and990inFIGS. 2B-9B. The switching signals inFIGS. 2B-6Bturn the switching transistors Q1and Q3on for a duration of Ton and turn the switching transistors Q1and Q3off for a duration of Toff. In some embodiments, the switching cycle comprises two or more switching signals where each one of the switching signals may have a different duty cycle such that two duty cycles can be inverse of each other. In some examples, different switching transistors are switched on or off in phase opposition, e.g., complementary to each other. In some examples, by applying switching signals250ofFIG. 2B, switching transistors Q1and Q3are turned on and switching transistors Q2and Q4are turned off and vice versa. In some embodiments, after pre-charging, the switching signals are applied to the switching transistors of the primary switching circuits and secondary switching circuits to turn the switching transistors on or off. In some examples, the switching signals include three duty cycles where a first and second duty cycle are inverse of each other and a third duty cycle is different from the first and second duty cycles. In some examples, as shown inFIGS. 7B-9B, the third duty cycle may be the same as one of the first or second duty cycles but the switching signals produced by the third duty cycle may have phase shift with respect to the switching signals produced by first and second duty cycles.

In step1106, a series of pulses is provided by the primary switching circuit through the secondary switching circuits to an LC circuit that includes a capacitor and an inductor. In some examples, the series of pulses is a voltage that is provided by the primary switching circuit to the LC circuit to generate an inductor current in the inductor and to generate a voltage across the capacitor of the LC circuit. As shown inFIGS. 6A-9A, the series of pulses are provided by primary switching circuits630,730,830, and930through one, two, three, or four secondary switching circuits of respective switching circuits655,755,855, and955to the LC circuit. In some embodiments as shown inFIGS. 2A-4A, the series of pulses are directly provided through an input port of the LC circuit that is coupled across a switching transistor of the primary switching circuit.

In step1108, the series of pulses are adjusted by the secondary switching circuits. As shown inFIGS. 6A-9A, the series of pulses that are provided by primary switching circuits630,730,830, and930are adjusted, e.g., modified, by one, two, three, or four secondary switching circuits of respective switching circuits655,755,855, and955before reaching the LC circuit. In some examples as shown inFIG. 6A, a voltage between node112and ground120is applied via secondary switching circuit655to LC circuit640. In some examples as shown inFIG. 7A, voltages between node112and ground120and between node116and ground120are applied via switching circuits755that includes two secondary switching circuits to LC circuit740. In some examples, the LC circuit740includes two inductors Ls1and Ls2that each are coupled between one of the secondary switching circuits and the capacitor Cs of the LC circuit740.

In step1110, a voltage across the capacitor of the LC circuit is provided as an output voltage. In some examples, as shown inFIGS. 2A-4AandFIGS. 6A-9A, the voltage across capacitor Cs between node108and ground120is provided as the output voltage. The output voltage may have a reverse polarity with respect to an input voltage Vin that may be coupled to the primary switching circuit as shown inFIGS. 2A-4AandFIGS. 6A-9A.

In step1112, at least one duty cycle of the two or more duty cycles of the switching signals are adjusted. The duty cycles may be adjusted to set an output voltage at a predefined value, e.g., predetermined value. The duty cycles may be constantly adjusted to keep the output voltage within an predefined range of the predetermined output voltage value, e.g., within 10 percent. In some examples, at least one duty cycle may be gradually increased to increase the output voltage to the predetermined value.

FIG. 12is a diagram of an exemplary electronic system1200that implements an inverting PWM power converter, according to various implementations described herein. Electronic system1200, in combination with the disclosure regardingFIGS. 2A-4AandFIGS. 6A-9A, may be any electronic device utilizing power from a power source. For example, electronic system1200may be representative of a computing device (e.g., a personal computer or a mobile device such as a smartphone, tablet computer, laptop, PDA, a wearable such as a watch or band, or combination thereof), or a consumer appliance, television or other display device, radio or telephone, home audio system, or the like.

In some implementations, electronic system may include a power delivery device1202(e.g., a power supply) and a load. The load may include various components of electronic system1200, including one or more of a central processing unit (CPU)1204, various memory systems1206, one or more input and/or output (I/O) devices1208, a power interface1210, and one or more batteries1212. The CPU1204may be a multi-core processor, a general-purpose microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, gated logic, discrete hardware components, or a combination of the foregoing.

A memory system1206may include, for example, volatile memory used to temporarily store data and information used to manage electronic system1200, a random access memory (RAM), and/or non-volatile memory such as a magnetic disk, flash memory, peripheral SSD, and the like. I/O device1208may include an input device such as a keyboard, a touch screen, a touch pad, voice control system, or other device for input of data. I/O device1208may include an output device such as a display device, audio device (e.g., a speaker), or data interface (e.g., a host data bus) for output of data. In some implementations, one or more elements of electronic system1200can be integrated into a single chip. In some implementations, the elements can be implemented on two or more discrete components.

Power delivery device1202may include any of the previously described power converter circuits (including an auxiliary bypass circuit), including a corresponding control circuit. Accordingly, power delivery device1202may be configured (e.g., as a step up or step down converter) to convert a first voltage to a second voltage, different than the first voltage. Power delivery device1202may receive an input power (e.g., at a voltage Vin) from an external power source1214via power interface1210. The input power may be a DC power. In some implementations, the input power may be an alternating current source that is converted to DC (e.g., by power interface1210) before being utilized by power delivery device1202. Additionally or in the alternative, the input power may be DC from battery1212.

Power delivery device1202may produce a voltage according to the load requirements of various components of electronic system1200. In this regard, power delivery device1202may implement multiple different types of converter circuits to accommodate different load requirements of the various components of electronic system1200. Additionally or in the alternative, power delivery device1202may be configured to provide charge to battery1212(e.g., as part of a battery charger system) based on power from external power source1214.

It is understood that the specific order or hierarchy of steps in the processes disclosed is presented as an illustration of some exemplary approaches. Based upon design preferences and/or other considerations, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. For example, in some implementations some of the steps may be performed simultaneously. Thus the accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

The predicate words “configured to”, “operable to”, and “programmed to” do not imply any particular tangible or intangible modification of a subject, but, rather, are intended to be used interchangeably. For example, a circuit or processor configured to monitor and control an operation or a component may also mean the circuit or processor being programmed to monitor and control the operation or being operable to monitor and control the operation. Likewise, a circuit or processor configured to execute code may be construed as a circuit or processor programmed to execute code or operable to execute code.

The terms “start-up” and “power-up” are intended to include, but not be limited to, the plain meaning of each respective term, and for the purposes of this disclosure may be used interchangeably. The terms “start-up” and “power-up” may include, for example, a point in time at which a circuit is turned on (e.g., started) and/or a period of time shortly thereafter.

A phrase such as an “aspect” does not imply that such aspect is essential to the present disclosure or that such aspect applies to all configurations of the present disclosure. A disclosure relating to an aspect may apply to all configurations, or one or more configurations. An aspect may provide one or more examples. A phrase such as an aspect may refer to one or more aspects and vice versa. A phrase such as an “implementation” does not imply that such implementation is essential to the present disclosure or that such implementation applies to all configurations of the present disclosure. A disclosure relating to an implementation may apply to all aspects, or one or more aspects. An implementation may provide one or more examples. A phrase such as an “implementation” may refer to one or more implementations and vice versa. A phrase such as a “configuration” does not imply that such configuration is essential to the present disclosure or that such configuration applies to all configurations of the present disclosure. A disclosure relating to a configuration may apply to all configurations, or one or more configurations. A configuration may provide one or more examples. A phrase such as a “configuration” may refer to one or more configurations and vice versa.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. In addition, description of a feature, advantage or mode of operation in relation to an example combination of aspects does not require that all practices according to the combination include the discussed feature, advantage or mode of operation.

As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Numeric terms such as “first”, “second”, “third,” etc., unless specifically stated, are not used herein to imply a particular ordering of the recited structures, components, capabilities, modes, steps, operations, or combinations thereof with which they are used.

The terms “comprise,” “comprising,” “includes,” and “including”, as used herein, specify the presence of one or more recited structures, components, capabilities, modes, steps, operations, or combinations thereof, but do not preclude the presence or addition of one or more other structures, components, capabilities, modes, steps, operations, or combinations thereof.