Semiconductor device

A disclosed semiconductor device includes a gate insulation film formed on a silicon substrate and a metal gate electrode formed in the gate insulation film, wherein the gate insulation film includes a first insulation film, a second insulation film that is formed on the first insulation film and has a greater dielectric constant than the first insulation film, and a third insulation film formed on the second insulation film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a fabrication method of the same, specifically, to a Metal Oxide Semiconductor (MOS) device having a gate insulation layer formed on a silicon substrate and a gate electrode formed on the gate insulation layer, and a fabrication method of such an MOS device.

2. Description of the Related Art

A Metal Oxide Semiconductor (MOS) device having a gate insulation layer formed on a silicon substrate and a gate electrode formed on the gate insulation layer has been widely used as a semiconductor device.

In a technology field of semiconductor devices, further miniaturization for high integration, high speed performance, low voltage operation, and the like have been demanded. In order to address such demands, further reduction of a gate insulation layer thickness is under vigorous investigation. Because gate leakage current due to a tunneling effect is increased when a conventional gate insulation layer made of silicon oxide is thinned, a so-called high-k (high dielectric constant) film such as HfO2(hafnium oxide) film may be used instead of silicon oxide.

When such a high-k insulation layer is employed along with a poly-silicon gate electrode, silicide may be formed between the insulation layer and the gate electrode. In order to avoid silicide formation, use of a stacked layer gate insulator including a silicon oxide film, a high-k film such as HfO2film formed on the silicon oxide film, and a metal nitride film formed on the high-k film has been proposed in an MOS device employing a poly-silicon gate electrode (See Japanese Patent Application Laid-Open Publication No. 2005-64317).

However, it is difficult to control a threshold voltage because of Fermi Level Pinning in the above MOS device, especially, a p-type MOS Field Effect Transistor (FET) device employing the poly-silicon gate electrode. In addition, when a metal gate electrode is used, it becomes difficult to control a threshold voltage because of flat-band voltage rolloff.

The present invention has been made in view of the above, and is directed to a semiconductor device where a threshold voltage can be controlled in an appropriate range and a flat-band voltage rolloff is suppressed, and a fabrication method of the same.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a semiconductor device including a gate insulation film formed on a silicon substrate and a metal gate electrode formed in the gate insulation film, wherein the gate insulation film includes a first insulation film, a second insulation film that is formed on the first insulation film and has a greater dielectric constant than the first insulation film, and a third insulation film formed on the second insulation film.

Another embodiment of the present invention provides a fabrication method of a semiconductor device. This fabrication method includes steps of forming a first insulation film on a silicon substrate; forming a second insulation film on the first insulation film, the second insulation film having a greater dielectric constant than the first insulation film; forming a third insulation film on the second insulation film; and forming a metal gate electrode on the third insulation film.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Non-limiting, exemplary embodiments of the present invention are described with reference to the accompanying drawings. In the drawings, the same or corresponding reference marks are given to the same or corresponding members or components. It is to be noted that the drawings are illustrative of the invention, and the specific thickness or size should be determined by a person having ordinary skill in the art in view of the following embodiments.

FIG. 1illustrates a primary portion of a semiconductor device, which may be a p-type Metal Oxide Semiconductor Field Effect Transistor (PMOSFET), according to a first embodiment of the present invention. InFIG. 1, “1” represents a silicon substrate. A gate oxide film2is formed on the silicon substrate1, and a metal gate electrode3is formed on the gate oxide film2. The metal gate electrode3may be formed of W, Ti, Al, Ta, Pt, TiN, or the like.

The gate oxide film2includes a first insulation film2aformed at the bottom (i.e., on the silicon substrate1), a second insulation film2bthat is formed on the first insulation film2aand has a dielectric constant greater than the dielectric constant of the first insulation film2a, and a third insulation film2cformed on the second insulation film2b. The first insulation film2amay be formed of SiO2and have a thickness of one to several nanometers. Specifically, the first insulation film2ais 1 nanometer thick in this embodiment.

The second insulation film2bis formed of a so-called high-k material (a material having a high dielectric constant), specifically, HfO2in this embodiment. In other embodiments, the second insulation film2bmay be formed of lanthanoid oxides, Y2O3, Al2O3, ZrO2, or the like. The second insulation film2bformed of HfO2may be several nanometers thick, specifically, about 3 nm thick in this example. The second insulation film2bcan be formed by an Atomic Layer Deposition (ALD) method, a Chemical Vapor Deposition (CVD) method, or the like.

The third insulation film2cis formed of silicon oxide and has a thickness of 0.3 through 2 nm in this embodiment. The third insulation film2cmay be formed by the ALD (atomic layer deposition) method, the CVD (chemical vapor deposition) method, or the like. As stated, the gate oxide film2has a stacked layer structure including the first insulation film2a, the second insulation film2b, and the third insulation film2c, which are deposited in this order on the silicon substrate1.

In this embodiment, the third insulation film2cis formed to be 0.3 through 2 nm thick. The reason why the thickness of the third insulation film2cis in such a range may be explained in the following manner along with measurement results.FIG. 2is a graph illustrating a relationship of a flat-band voltage (VFB) with respect to an equivalent oxide thickness (EOT). In this graph, open triangles indicate the VFBs for the gate oxide film2not including the third insulation film2c(0 nm), closed circles indicate the VFBs for the gate oxide film2including the third insulation film2cof about 1 nm thick, and open diamonds indicate the VFBs for the gate oxide film2including the third insulation film2cof about 2 nm thick.

As shown by an arrow inFIG. 2, when the gate oxide film2does not include the third insulation film2c,the flat-band voltage rolloff is observed. On the other hand, when the gate oxide film2includes the third insulation film2cof about 1 nm or 2 nm thick, the flat-band voltage rolloff is suppressed.

FIG. 3is another graph illustrating the flat-band voltages (VFB) with respect to the equivalent oxide thickness (EOT). In this graph, open triangles indicate the VFBs for the gate oxide film2not including the third insulation film2c, open circles indicate the VFBs for the gate oxide film2including the third insulation film2cof about 3 nm thick, closed diamonds indicate the VFBs for the gate oxide film2including the third insulation film2cof about 4 nm thick, and open squares indicate the VFBs for the gate oxide film2including the third insulation film2cof about 5 nm thick.

As shown inFIG. 3, when the third insulation film2cis about 3 nm thick or more, the flat-band voltage rolloff is clearly observed. Namely, when the third insulation film2cbecomes 3 nm thick or more, no suppressing effect is demonstrated on the flat-band voltage rolloff, or the rolloff becomes rather significant.

FIG. 4is a graph illustrating a relationship of capacitance C with respect to a gate voltage Vg. In this graph, open triangles indicate the capacitance for the gate oxide film2not including the third insulation film2c, and closed squares indicate the capacitance for the gate oxide film2including the third insulation film2cof about 0.3 nm thick. Use of the third insulation film2chaving the thickness of about 0.3 nm reduces a negative shift, as clearly understood when compared with the case where the third insulation film2cis not employed.

FIG. 5is a graph of a relationship between a flat-band voltage (VFB), which is taken along the vertical axis, and a thickness of the third insulation film2c,which is taken along the horizontal axis. A sample used for this measurement has the first insulation film2a(SiO2film) of about 1 nm and the second insulation film2b(HfO2film) of about 3 nm. As shown in this graph, a negative shift in the flat-band voltage is suppressed in a thickness range of 0.3 nm through 2 nm. From the foregoing, the third insulation film2cis determined to be in such a thickness range in this embodiment. By setting the third insulation film2cto fall within this range, a threshold voltage can be controlled in an appropriate range.

The reason why the rolloff takes place may be explained in the following manner. When the third insulation film2cis absent in the gate oxide film2, oxygen atoms diffuse out from the second insulation film2bduring a heating process, leaving boundary dipoles10aat the boundary between the first insulation film2aand the second insulation film2b, as shown inFIG. 6A. On the other hand, when the third insulation film2cis present on the second insulation film2b, boundary dipoles10bare also created at the boundary between the second insulation film2band the third insulation film2c. The boundary dipoles10bmay counterbalance the boundary dipoles10a, thereby suppressing the flat-band voltage rolloff. According to this, when the third insulation film2cbecomes thick, the oxygen atoms in the second insulation film2bare not likely to diffuse out. As a result, boundary dipoles having the same direction as the boundary dipoles10aare created at the boundary between the second insulation film2band the third insulation film2c, which may increase the flat-band voltage rolloff.

The present application is based on Japanese Patent Application No. 2008-239214, filed on Sep. 18, 2008 with the Japanese Patent Office, the entire content of which is hereby incorporated herein by reference.