Transistor having raised source/drain self-aligned contacts and method of forming same

A transistor structure and a method of forming same. The transistor structure includes: a semiconductor substrate having a gate-side surface; a gate disposed on the gate-side surface, the gate extending above the gate-side surface by a first height; a semiconductor extension disposed on the gate-side surface and extending above the gate-side surface by a second height larger than the first height, the semiconductor extension including a diffusion region having a diffusion surface located at the second height; and a diffusion contact element electrically coupled to the diffusion surface.

FIELD OF THE INVENTION

Embodiments of the present invention relate generally to microelectronic layout and fabrication. In particular, embodiments relate to structures for addressing contact to gate shorting liabilities in transistors and to methods of achieving such structures.

BACKGROUND OF THE INVENTION

The ongoing scaling of transistors presents an ever expanding array of new issues to be overcome as the transistor dimensions shrink. Once such issue concerns guarding against contacts shorting to the gate structures as the transistors are scaled to ever smaller dimensions. Historically, contact-to-gate shorting has been a key obstacle to aggressive transistor dimensional scaling owing to the extreme difficulty of placing diffusion contacts between closely spaced transistor gates.

FIGS. 1a-1drepresent a conventional process flow for providing contacts to the diffusion of a transistor structure. As seen inFIG. 1a, a transistor structure100includes a pair of gates102disposed next to each other on a substrate103, spacers104at each side of each of the gates, and a diffusion layer106between the pair of gates. The diffusion layer106may include a source region between the two gates, and drain regions on opposite sides of the gates (not designated in the figures), or vice versa. Referring next toFIG. 1b, the prior art deposits an oxide layer108onto the gates and diffusion layer as shown, such as, for example, by way of chemical vapor deposition.FIG. 1cin turn shows the oxide layer108as having been patterned to define a contact opening110therein. The contact opening110may typically be provided using well known lithography and etching techniques. Thereafter, as shown inFIG. 1da conductive material may be provided inside the contact opening110to provide a contact plug112. The contact opening110may for example be filled using an electroless and/or an electrolytic plating technique. The resulting transistor structure100shown inFIG. 1dposes a concern with respect to a possible shorting between the contact plug112and each of the gates102, as suggested by example by arrows S. The above becomes even more of a concern as a function of the generational scaling of transistor geometries.

The prior art attempts to solve the above issues by either making the contact plugs smaller, tightening alignment requirements between the contact masking layer and the gate masking layer, and/or providing larger transistors. Smaller contact plugs, however, by virtue of an increased resistance of the plug, can lead to degraded transistor performance. In addition, smaller contact openings may be difficult to fill with the conductive plug material, in this way affecting process margins. Tightening alignment requirements between the contact masking layer and the gate masking layer, on the other hand, presents limitations as well, to the extent that, since alignment is a mechanical process, and since limits of tool alignment are rapidly being approached with the scaling of transistor structures, such tightening may not be a viable option for future generation transistors. Larger transistors, on the other hand, significantly impact both transistor performance and the need for a generational scaling of transistor and chip sizes.

The prior art fails to provide a cost-effective and reliable manner of reducing the possibility of contact to gate shorting in a transistor structure.

For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.

DETAILED DESCRIPTION

In the following detailed description, embodiments of a transistor structure, a method of forming the transistor structure, and a system incorporating the transistor structure are disclosed. Reference is made to the accompanying drawings within which are shown, by way of illustration, specific embodiments by which the present invention may be practiced. It is to be understood that other embodiments may exist and that other structural changes may be made without departing from the scope and spirit of the present invention.

The terms on, above, below as used herein refer to the position of one element relative to other elements. As such, a first element disposed on, above, or below a second element may be directly in contact with the second element or it may include one or more intervening elements. However, as used herein, a first element described as being disposed adjacent a second element, including super-adjacent (adjacent and above) or supra-adjacent (adjacent and below) the second element, is in contact with the second element.

Referring toFIGS. 2a-2f, stages of forming a transistor structure as depicted inFIG. 2fare shown, where the structures are depicted in cross-section. Like reference numerals inFIGS. 2a-2fdesignate like components.

Referring first now toFIG. 2f, an embodiment of a transistor structure200comprises a semiconductor substrate202having a gate-side surface204as shown. Substrate202may include an insulative substrate, such as, for example, a silicon on insulator (SOI) substrate. Thus, “substrate” as used herein may refer to a substrate comprising an insulative layer, such as an oxide, on which is disposed a semiconductor layer, such as Si. In the alternative, substrate202may include a monocrystalline silicon substrate. Moreover, the substrate may include a non-silicon based semiconductor material, such as for example, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, etc. The transistor structure200also includes a pair of adjacent gates206disposed on the gate-side surface204of substrate202, the gates extending above the gate-side surface204by a first height H1. The gates may include either metal gates, or non metal gates such as gates including polysilicon. It is to be noted that the gages206inFIGS. 2a-2fare shown in a schematic form only. Thus, the gates may include one or more layers, such as, for example, a single gate electrode layer including a metal or a polysilicon material, or a gate including multiple layers such as a metal or a polysilicon material, and, in addition, other layers such as salicide/silicide layers, or layers having different conductivities with respect to one another. Additionally, althoughFIG. 2f, and associatedFIGS. 2a-2e, show a transistor structure including a pair of gates, embodiments are not so limited, and include within their scope a transistor structure including one or more gates. Moreover, althoughFIGS. 2a-2fshow a pair of gates where the gates have identical heights H1, embodiments are not so limited, and include within their scope a transistor structure including a pair of adjacent gates having different heights with respect to one another. In the latter case, the height H1would refer to the height of the tallest gate of the pair of gates.

Conventional spacers215are disposed at each side of a given one of the gates206as shown. The transistor structure200additionally includes a semiconductor extension208which is disposed on the gate-side surface204, and which extends above the gate-side surface of the substrate by a second height H2which is larger than the first height H1. The semiconductor extension208includes a diffusion region210which has a diffusion surface212located at the second height H2. The diffusion region210may take any form as would be within the knowledge of a person skilled in the art. Thus, the diffusion region210may for example take any form as it would in the prior art, with the difference being that, according to embodiments, the diffusion region210is raised with respect to the gates such that the diffusion surface is at a height H2larger than H1. In the shown embodiment, the diffusion region210is shown as comprising a silicide layer, although embodiments are not so limited. Thus, the diffusion region210may, for example, include a highly doped region, or a silicide layer, or a combination of both. The diffusion region210may provide a source region or a drain region between the two gates. Transistor structure200further includes a diffusion contact element or contact214electrically coupled to the diffusion surface212. Contact214is a self-aligned contact or SAC to the extent that it aligns itself automatically with respect to the already provided extension208during its formation. As seen inFIG. 2f, transistor structure further includes an etch stop layer218disposed on a top surface of the gates206, and which has a top surface213that is co-planar with the diffusion surface212. The etch stop layer218may be made, for example, of a nitride material, and is adapted to serve as an etch stop during a patterning of the contact214, as will be explained in detail further below with respect toFIGS. 2dand2e. In the shown embodiment, the etch stop layer218is itself disposed on the gate-side surface204, encompasses the gates206, and extends beyond the gate-side surface204by a height substantially equal to the second height H2. Referring still toFIG. 2f, the pair of gates include a first gate206aand a second gate206b, the extension208is disposed between the two gates206aand206b, and the diffusion region210corresponds to one of a source region and a drain region of the transistor structure associated with each one of the gates206aand206b. The transistor structure200may further include an inter-layer dielectric layer (ILD layer)220, such as an oxide layer, disposed on the etch stop layer218. The contact214is shown as extending through the ILD layer220to the diffusion surface212. It is possible as suggested for example inFIG. 2f, that a transistor structure according to embodiments may exhibit a misalignment or offset between the semiconductor extension208and a corresponding contact214by virtue of the respective extension and contact as having been provided/patterned at different times. However, provision of the etch stop layer218would effectively prevent shorting even in the case of a misalignment as noted above.

FIGS. 2a-2fillustrate a structure at different stages of its formation into the transistor structure200ofFIG. 2fdescribed above, according to a method embodiment.

Referring first toFIG. 2aby way of example, a method embodiment includes providing a structure, which includes the semiconductor substrate202as described above, a pair of gates206disposed on the gate-side surface204of substrate202, the gates including spacers215. The gates206and spacers215have already been described above in relation toFIG. 2f.

Referring next toFIG. 2bby way of example, a method embodiment further includes providing a semiconductor extension on the gate-side surface, such as extension208on gate-side surface204of substrate202. As seen inFIG. 2b, and as explained with respect toFIG. 2fabove, the extension208extends above the gate-side surface204by the second height H2, and includes the diffusion region210having the diffusion surface212. According to one embodiment, the extension208may be provided by epitaxially growing the extension onto the gate-side surface204in a weal known manner. The extension208may automatically assume a tapered profile, as shown in the cross-sectional view ofFIGS. 2b-2, during its formation by way of epitaxial growth, mainly as a result of an orientation of the crystal planes during epitaxial formation, as would be recognized by one skilled in the art. A tapered profile would be preferable in any event in order to increase a distance between the diffusion surface214and each of the gates206. Embodiments are not so limited, however, and include within their scope the provision of an extension of any shape, such as one having parallel side-walls, according to application needs. After formation of the extension208, a diffusion region210may be provided onto the extension according to any one of well known techniques for providing a diffusion region.

Referring next toFIG. 2cby way of example, a method embodiment further comprises providing an etch stop dielectric layer218which is disposed on a top surface of the gates206, and which has a top surface213that is co-planar with the diffusion surface212. As noted above, the etch stop layer may include a nitride material, or, in the alternative, a carbide material, and may for example be provided using chemical vapor deposition, or using any other ones of well known techniques for providing a dielectric layer, as would be within the knowledge of a skilled person. The etch stop layer is disposed to protect the gates during a contact opening etch process as described further below in relation toFIGS. 2dand2e. Preferably, the etch stop layer218may be disposed on the gate-side surface204as shown, and to encompass the gates. The etch stop layer218“encompasses,” the gates as used herein in the sense that is includes the gates in the extent of its volume, as suggested for example inFIGS. 2c-2f, although embodiments are not so limited. According to an embodiment, after provision of an etch stop material onto the top surfaces of gates206, such as by way of chemical vapor deposition, the etch stop material may be planarized, such as through polishing, such that a top surface of the etch stop layer218is co-planar with the diffusion surface212.

Referring next toFIG. 2dby way of example, a method embodiment includes providing an ILD layer220onto the etch stop layer218. Provision of the ILD layer220may be by way of chemical vapor deposition, for example, or through any other method as would be within the knowledge of a skilled person. The ILD material of the ILD layer may be deposited by way of chemical vapor deposition, and then polished back, for example, in a well known manner, to achieve the structure shown inFIG. 2d, the ILD layer may include, for example, an oxide material, or any other material that would serve as an ILD as would be within the knowledge of a skilled person. A thickness of the ILD layer may be chosen as a function of yield considerations with respect to a subsequent formation of the contact214therein as will be described in further detail regardingFIG. 2e, and further as a function of electrical considerations regarding the contact214, as would be within the knowledge of the skilled person.

Referring next toFIG. 2eby way of example, a method embodiment includes patterning the ILD layer220to create a contact opening222therein, the opening222extending through the ILD layer220to the diffusion surface212. Patterning of the ILD layer220to provide the opening222may, for example, be achieved by using well known lithography and etching techniques, as would be within the knowledge of one skilled in the art. Since the diffusion region210is raised by virtue of the extension208above the height H1of the gates, the etch stop layer218below the diffusion surface212will prevent shorting to the gates206. It is noted that an etch stop layer having an adequate selectivity to the ILD etch performed to provide the contact opening may be chosen.

Referring next toFIG. 2fby way of example, a method embodiment includes filling the contact opening222with a conductive material, such as a metal, for example, to provide the diffusion contact element or contact214. Contact214may be provided using any one of well known techniques to fill a contact opening, such as, for example, by using electroless and/or electrolytic plating. As noted previously, the contact214may exhibit a misalignment or offset with the semiconductor extension208by virtue of the respective extension and contact as having been provided/patterned at different times. Even in such a case, however, the presence of the extension at a height H2which is larger than height H1, coupled with the presence of the etch stop layer218, prevent a shorting between the contact214and the gates206.

Advantageously, embodiments provide a transistor structure where the diffusion surface is raised above the height of the gate. Embodiments therefore address the disadvantage of prior art transistor structures where the diffusion contact penetrated the gap between two tightly spaced gates, leaving the transistor structure vulnerable to contact-to-gate shorting. Embodiments further advantageously provide an etch stop layer to protect the top of the gate so that a contact that may misalign with respect to the diffusion surface to a considerable extend would still not cause any shorting to the gate. Additionally, advantageously, method embodiments may rely on well known process flow techniques, and are thus simple and cost-effective to implement, as they would not require tool changes or extensive tool adjustments.

Referring toFIG. 3, there is illustrated one of many possible systems900in which embodiments of the present invention may be used. In one embodiment, the electronic assembly1000may include a transistor structure, such as transistor structure200ofFIG. 2f. Assembly1000may further include a microprocessor. In an alternate embodiment, the electronic assembly1000may include an application specific IC (ASIC). Integrated circuits found in chipsets (e.g., graphics, sound, and control chipsets) may also be packaged in accordance with embodiments of this invention.

For the embodiment depicted byFIG. 3, the system900may also include a main memory1002, a graphics processor1004, a mass storage device1006, and/or an input/output module1008coupled to each other by way of a bus1010, as shown. Examples of the memory1002include but are not limited to static random access memory (SRAM) and dynamic random access memory (DRAM). Examples of the mass storage device1006include but are not limited to a hard disk drive, a compact disk drive (CD), a digital versatile disk drive (DVD), and so forth. Examples of the input/output module1008include but are not limited to a keyboard, cursor control arrangements, a display, a network interface, and so forth. Examples of the bus1010include but are not limited to a peripheral control interface (PCI) bus, and Industry Standard Architecture (ISA) bus, and so forth. In various embodiments, the system90may be a wireless mobile phone, a personal digital assistant, a pocket PC, a tablet PC, a notebook PC, a desktop computer, a set-top box, a media-center PC, a DVD player, and a server.

The various embodiments described above have been presented by way of example and not by way of limitation. Thus, for example, while embodiments disclosed herein teach the formation of protective caps using sacrificial caps, other methods of providing the protective caps are also within the scope of embodiments.

Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.