THREE DIMENSIONAL (3D) MEMORY DEVICE AND FABRICATION METHOD

A method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a channel hole structure, forming an opening that exposes the sacrificial layer, removing the sacrificial layer to create a cavity and expose a part of the channel hole structure, forming a semiconductor layer to fill the cavity, filling the opening with a filling structure, and forming a second dielectric stack over the filling structure. The opening is made for a gate line slit (GLS) structure.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority of Chinese Patent Application No. 202211651307.9, filed on Dec. 21, 2022, the content of which is incorporated herein by reference in its entirety.

FIELD OF THE TECHNOLOGY

This application relates to the field of semiconductor technology and, specifically, to a three-dimensional (3D) memory device and fabrication method thereof.

BACKGROUND OF THE DISCLOSURE

Not-AND (NAND) memory is a non-volatile type of memory that does not require power to retain stored data. The growing demands of consumer electronics, cloud computing, and big data bring about a constant need of NAND memories of larger capacity and better performance. As conventional two-dimensional (2D) NAND memory approaches its physical limits, three-dimensional (3D) NAND memory is now playing an important role. 3D NAND memory uses multiple stack layers on a single die to achieve higher density, higher capacity, faster performance, lower power consumption, and better cost efficiency.

In some cases, a 3D NAND memory device contains multiple stacks or decks that are formed sequentially based on a substrate along a vertical direction. Each deck contains layers of memory cells. During the fabrication process, channel hole structures and gate line slit (GLS) structures are made separately, and the multiple stacks may have instability risks. The disclosed memory structures and methods may improve certain aspects of the fabrication process.

SUMMARY

In one aspect of the present disclosure, a method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a first channel hole structure extending through the first dielectric stack and sacrificial layer, forming a first opening that extends through the first dielectric stack for a GLS structure and exposes the sacrificial layer, removing the sacrificial layer by etch to create a cavity and expose a part of the first channel hole structure in the cavity, forming a semiconductor layer to fill the cavity, filling the first opening with a filling structure after forming the semiconductor layer, and forming a second dielectric stack over the filling structure. The first dielectric stack includes a first dielectric layer and a second dielectric layer alternately stacked. The second dielectric stack includes a third dielectric layer and a fourth dielectric layer alternately stacked.

In another aspect of the present disclosure, a 3D memory device includes a first conductor/insulator stack having a first conductive layer and a first dielectric layer alternatingly stacked, a second conductor/insulator stack formed over and aligned with the first conductor/insulator stack and having a second conductive layer and a second dielectric layer alternatingly stacked, a channel hole structure extending through the first and second conductor/insulator stacks along a first direction, and a GLS structure. The GLS structure includes a first taper part through the first conductor/insulator stack and a second taper part through the second conductor/insulator stack along the first direction.

In another aspect of the present disclosure, a system includes a memory device, and a memory controller for controlling the memory device. The memory device includes a first conductor/insulator stack containing a first conductive layer and a first dielectric layer alternatingly stacked, a second conductor/insulator stack formed over and aligned with the first conductor/insulator stack and having a second conductive layer and a second dielectric layer alternatingly stacked, a channel hole structure extending through the first and second conductor/insulator stacks along a first direction, and a GLS structure. The GLS structure includes a first taper part through the first conductor/insulator stack and a second taper part through the second conductor/insulator stack along the first direction.

DETAILED DESCRIPTION

The following describes the technical solutions according to various aspects of the present disclosure with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Apparently, the described aspects are merely some but not all of the aspects of the present disclosure. Features in various aspects may be exchanged and/or combined.

FIGS.1-33schematically show a fabrication process of an exemplary 3D array device100according to aspects of the present disclosure. The 3D array device100is a part of a memory device and may also be referred to as a 3D memory structure. Among the figures, top views are in an X-Y plane and cross-sectional views are taken along a line in the X-Y plane.

As shown inFIG.1, a structure of the 3D array device100includes a substrate110. In some aspects, the substrate110may include a single crystalline silicon layer. The substrate110may also include a semiconductor material, such as germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), polysilicon, or a Group III-V compound such as gallium arsenide (GaAs) or indium phosphide (InP). Optionally, the substrate110may also include an electrically non-conductive material such as glass, a plastic material, or a ceramic material. When the substrate110includes glass, plastic, or ceramic material, the substrate110may further include a thin layer of polysilicon deposited on the glass, plastic, or ceramic material. In this case, the substrate110may be processed like a polysilicon substrate. As an example, the substrate110includes an undoped or lightly doped single crystalline silicon layer in descriptions below.

In some aspects, layers111-113are deposited over the substrate110, as shown inFIG.1. The deposition may be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. The layers111and113are exemplarily undoped or lightly doped polysilicon layers, and the layer112is exemplarily a silicon oxide layer. In some other cases, the layer111represents a part of the substrate110. In these cases, there is no boundary between the layer111and substrate110. Optionally, the layer113is a sacrificial layer. Further, a portion of the layer113is removed by a selective etch process, such as a selective a dry etch process or a combination of selective dry and wet etch processes. The etch creates an opening (not shown) that exposes the layer112at the bottom. The opening is subsequently filled by a carbon material to form a carbon block114, as shown inFIGS.2and3. The carbon block114may be referred to as a block region. In some other aspects, the block114may be made from another material other than carbon. The cross-sectional view shown inFIG.2is taken along a line AA′ ofFIG.3. The filling process may be done by CVD or ALD.

Further, a dielectric stack140is formed over the substrate110, layers111-113, and carbon block114. A dielectric layer115is formed over the dielectric stack140, as depicted inFIG.4. The carbon block114is sandwiched between the dielectric stack140and the substrate110or the layers111-112in the Z direction or a direction perpendicular to the substrate110. The layer115may include silicon oxide. The dielectric stack140may be considered as a dielectric stack structure that includes multiple pairs of stack layers, for example, including first dielectric layers141and second dielectric layers142, stacked alternately over each other. Some layers of the dielectric stack140are used to form memory cells. In some cases, the layers for fabricating memory cells may include 64 pairs, 128 pairs, or more than 128 pairs of the first and second dielectric layers141and142.

In some aspects, the first dielectric layers141and the second dielectric layers142are made of different materials. In descriptions below, the first dielectric layer141includes a silicon oxide layer exemplarily, which may be used as an isolation stack layer, while the second dielectric layer142includes a silicon nitride layer exemplarily, which may be used as a sacrificial stack layer. The sacrificial stack layer will be subsequently etched out and replaced by a conductive stack layer. The first dielectric layers141and second dielectric layers142may be deposited via CVD, PVD, ALD, or a combination thereof.

FIGS.5and6show a schematic cross-sectional view and a schematic top view of the structure of the 3D array device100after openings116and160are etched according to aspects of the present disclosure. The cross-sectional view shown inFIG.5is taken along a line BB′ ofFIG.6. The opening116may be referred to as a channel hole and is made for forming a channel hole structure, while the opening160is made for a gate line slit (GLS). The GLS may also be referred to as a GLS structure. The channel holes and opening160may be formed at the same time by, for example, a selective dry etch process or a combination of selective dry and selective wet etch processes. In some cases, one mask or one mask set may be used for the etch. Optionally, the channel holes and opening160may be made separately at different time periods with the same process or similar processes. The selective etch process is arranged such that the etch rate of the polysilicon layers111and113and silicon oxide layer112is much faster than the etch rate of the carbon block114. Consequently, the channel holes are etched such that they extend deeper than the opening160in the Z direction or a direction approximately perpendicular to the substrate110.

The channel holes may have a cylinder shape or pillar shape that extends through the dielectric stack140, the layers112-113, and partially penetrates the layer111. A portion of the layer111is exposed at the bottom of the channel hole. The opening160is aligned to the carbon block114along the Z direction or the vertical direction, and extends in the Y direction in the X-Y plane. The opening160passes through the dielectric stack140and reaches or partially penetrates the carbon block114, because of the slower etch rate of the block114. In some aspects, the openings116and160have a taper angle. The horizontal dimension of the openings116decreases gradually from the top to the bottom. The width of the opening160, i.e., the horizontal dimension of the opening160in the X direction, also decreases gradually from the top to the bottom. The taper parts of the openings116and160pass through dielectric stack140. The carbon block114is exposed at the bottom of the opening160. The quantity, dimension, shape, and arrangement of the channel holes and opening160shown inFIGS.5and6are exemplary and for description purposes, although any suitable quantity, dimension, and arrangement may be used for the disclosed 3D array device100according to various aspects of the present disclosure.

As illustrated above, since both the channel hole and GLS structures extend through the dielectric stack140, the channel holes and the opening for GLS (i.e., the opening160) may be formed at the same time by the same process with one mask or one mask set. Compared to etching the channel holes and the opening for GLS separately in two processes with multiple masks or multiple mask sets, the fabrication cost may be reduced in some cases.

Further, a carbon material is deposited over the top surface of the structure of the 3D array device100to form a layer117via CVD and/or ALD. As shown inFIG.7, the layer117fills the channel holes (i.e., openings116). The layer117also covers the sidewall and exposed surface of the carbon block114at the bottom of the opening160. After a timed selective etch, e.g., a selective wet etch, certain exposed portions of the layer117are etched away, while the carbon material deposited inside the channel holes remains there. As shown inFIG.8, the channel holes are filled with a filling structure118and the carbon block114is exposed again.

Further, nitrogen-doped silicon carbide (NDC) is deposited via CVD and/or ALD, which fills the opening160with a filling structure161. After the filling process, the filling structure118is removed selectively. As the filling structure118is carbon, it may be removed by a burning process. Optionally, the filling structure118may be removed by a selective etch process such as a selective wet etch process. As shown inFIGS.9and10, the channel holes (or openings116) reappear, while the opening160is filled with the filling structure161.

Further, a functional layer151is deposited on the sidewall and bottom surface of the channel hole. The functional layer151includes a blocking layer on the sidewall to block an outflow of charges, a charge trap layer on a surface of the blocking layer to store charges during an operation of the 3D array device100, and a tunneling layer on a surface of the charge trap layer. The blocking layer may include one or more layers that may include one or more materials. The material for the blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, or another wide bandgap material. The charge trap layer may include one or more layers that may include one or more materials. The materials for the charge trap layer may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, a high-k dielectric material such as aluminum oxide or hafnium oxide, or another wide bandgap material. The tunneling layer may include one or more layers that may include one or more materials. The material for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, or another wide bandgap material.

Further, a semiconductor channel155is deposited on a surface of the tunneling layer. The semiconductor channel155includes a polysilicon layer in some aspects. Optionally, the semiconductor channel155may include an amorphous silicon layer. The semiconductor channel155extends through the dielectric stack140and into the layer111in certain cases. The blocking layer, the charge trap layer, the tunneling layer, and the semiconductor channel155may be deposited by, e.g., CVD and/or ALD. The structure formed in a channel hole in the stack140, including the functional layer151and semiconductor channel155, may be referred to as a lower channel hole structure. Similar to the opening116, the lower channel hole structure has a taper part extending through the stack140in some embodiments.

After the semiconductor channel155is formed, the opening of the channel hole is filled by an oxide material156and a conductive plug is formed at the top of the lower channel hole structure, as shown inFIG.11. The conductive plug is electrically connected to the semiconductor channel155and may be formed by, e.g., doped polysilicon. The lower channel hole structures are formed in channel hole regions150. A conductive plug in the lower channel hole structure may be referred to as a lower conductive plug.

In some cases, the functional layer151includes an oxide-nitride-oxide (ONO) structure. That is, the blocking layer is a silicon oxide layer, the charge trap layer is a silicon nitride layer, and the tunneling layer is another silicon oxide layer.

Optionally, the functional layer151may have a structure different from the ONO configuration. In the following descriptions, the ONO structure is used exemplarily for the blocking layer, the charge trap layer, and the tunneling layer.

Further, an oxidation process is performed. Certain portions at the top of the lower channel hole structure, including a part of the lower conductive plug, are converted into silicon oxide and become a part of the dielectric layer115.FIG.12shows a schematic cross-sectional view of the structure of the 3D array device100after the oxidation process and a selective etch process. The selective etch process, e.g., a selective wet etch process, removes the filling structure161to make the opening160reappear.

Further, NDC is deposited to form a spacer layer162on the sidewall and bottom surface of the opening160by CVD and/or ALD. The spacer layer162on the sidewall is configured to protect the first and second dielectric layers141and142. In some other cases, the spacer layer162may include another material that is different from materials of the layers141and142, such as aluminum oxide. Alternatively, the spacer layer162may include a multilayer that contains layers similar to the layers141and142. The layer162at the bottom of the opening160is subsequently removed by an etch, e.g., a dry etch. The etch exposes the carbon block114at the bottom of the opening160, as shown inFIG.13.

Further, one or more selective etch processes, e.g., selective wet etch processes, are performed to remove the carbon block114and layer113, respectively. As shown inFIG.14, removal of the layer113creates a cavity157and exposes the layer112and certain portions of the blocking layers formed in the lower sections of the channel holes. Then, multiple selective etch processes, e.g., multiple selective wet etch processes, are performed to remove the exposed portions of the blocking layer, the charge trap layer, and the tunneling layer consecutively, which exposes portions of the semiconductor channel155in the cavity157, as shown inFIG.15. In some cases, the blocking layer, tunneling layer, and layer112are silicon oxide. When the blocking and tunneling layers are etched, the layer112is etched as well. Provided the layer112is much thicker than the blocking and tunneling layers. As such, the layer112remains in the cavity157and the thickness change of the layer112is not shown inFIG.15for simplicity.

After the etch processes, the layer112and certain lower parts of the semiconductor channels155are exposed in the cavity157. As shown inFIG.16, the cavity is filled by a semiconductor material, e.g., polysilicon, to form a semiconductor layer158. A CVD and/or ALD deposition process may be performed. The semiconductor layer158is n-doped, formed on the exposed surface of the layer112and exposed parts of the semiconductor channels155. The semiconductor layer158passes through the functional layer151, surrounds the exposed parts of the semiconductor channel155, and electrically contacts the semiconductor channel155. The sacrificial layer113is removed when there is only one dielectric stack, i.e., the stack140. The single stack structure has a lower risk of mechanical instability compared a multi-stack structure when the cavity157is created. As such, the yield and reliability may be improved.

Further, a selective etch process such as a selective wet etch process is performed to remove the spacer layer162on the sidewall of the opening160. The opening160is then filled with a carbon material by CVD and/or ALD. As shown inFIG.17, a filling structure163fills the opening160and then a chemical mechanical polishing (CMP) may be conducted for a planarization process. In some cases, a cavity (not shown) forms inside the filling structure163.

Optionally, in order to increase the layers for memory cells, a dielectric stack143is formed over the layer115, the filling structure163, and dielectric stack140, and a dielectric layer119is formed over the dielectric stack143, which is illustrated inFIG.18. The layer119may include silicon oxide. The dielectric stack143is aligned to the stack140along the Z direction or a direction approximately perpendicular to the substrate110. Similar to the dielectric stack140, the stack143includes multiple pairs of stack layers, for example, including third dielectric layers141A and fourth dielectric layers142A, stacked alternately over each other. In some cases, the layers for fabricating memory cells may include 64 pairs, 128 pairs, or more than 128 pairs of the third and fourth dielectric layers141A and142A.

In some aspects, the third dielectric layer141A includes a silicon oxide layer exemplarily, which may be used as an isolation stack layer, while the fourth dielectric layer142A includes a silicon nitride layer exemplarily, which may be used as a sacrificial stack layer. The third dielectric layers141A and fourth dielectric layers142A may be deposited via CVD, PVD, ALD, or a combination thereof.

FIG.19show a schematic cross-sectional view of the structure of the 3D array device100after openings116A and164are etched according to aspects of the present disclosure. The opening116A may be referred to as a channel hole and is made for forming an upper channel hole structure, while the opening164is made for GLS. The openings116A and164are aligned to and expose the lower channel hole structures and the filling structure163, respectively. The openings116A and164may be formed simultaneously by, for example, a selective dry etch process or a combination of selective dry and selective wet etch processes. At the bottom of the opening116A, the lower conductive plug of the lower channel hole structure appears.

The channel holes (i.e., the openings116A) and opening164pass through the dielectric stack143in the Z direction. Optionally, the quantity and pattern of the openings116A and164in an X-Y plane may be the same as or similar to that of the openings116and160with respect toFIG.6. Similar to the openings116and160, the openings116A and164may have a taper part extending through the dielectric stack143in some aspects. As the opening116A tapers toward the bottom, the bottom dimension of the opening116A is smaller than the top dimension of the lower channel hole structure. For the same reason, the bottom width of the opening164is smaller than the top width of the filling structure163.

The channel holes and the opening for GLS (i.e., the opening164) may be formed at the same time by the same process. Compared to etching the channel holes and the opening for GLS separately in two processes, the fabrication cost may be reduced in some cases.

Further, polysilicon is deposited to fill the channel holes by CVD and/or ALD. A filling structure116B is formed in the channel hole. The polysilicon layer deposited inside the opening164is subsequently etched away by a timed selective etch (e.g., a selective wet etch), exposing the filling structure163. The filling structure116B and the opening164after the timed selective etch are shown schematically inFIG.20.

Thereafter, NDC or carbon is deposited to fill the opening164by CVD and/or ALD. A filling structure165is formed over the filling structure163in the opening164, followed by a planarization process. The top of the filling structure163and the bottom of the filling structure165are connected. The bottom width of the filling structure165is smaller than the top width of the filling structure163in the X direction. Further, a selective etch (e.g., a selective wet etch) is performed to remove the filling structures116B and the openings116A reappear. The filling structure165and the openings116A after the selective etch are shown schematically inFIG.21. The selective etch exposes the lower conductive plugs of the lower channel hole structures. In certain cases, the lower conductive plug is made from polysilicon. In these cases, the selective etch is arranged such that part of the lower conductive plug may be etched away in the selective etch, while a certain portion of the lower conductive plug remains there.

After the openings116A are formed by the selective etch, the lower conductive plugs are exposed. Further, a functional layer151A is deposited on the sidewall and bottom surface of the channel hole (i.e., the opening116A) by CVD and/or ALD. The functional layer151A may be the same as or similar to the functional layer151with respect toFIG.11. The functional layer151A includes a blocking layer, a charge trap layer on a surface of the blocking layer, and a tunneling layer on a surface of the charge trap layer. Further, an etch such as a dry etch is performed to etch away the functional layer151A at the bottom of the channel hole, exposing the remaining lower conductive plug underneath the opening116A.

Further, a semiconductor channel155A is deposited on the surface of the tunneling layer and the remaining lower conductive plug at the bottom of the opening116A by CVD and/or ALD. The semiconductor channel155A includes a polysilicon layer in some aspects. The semiconductor channel155A extends through the dielectric stack143and is electrically connected with the semiconductor channel155via the remaining lower conductive plug. The structure formed in the channel hole or opening116A, including the functional layer151A and semiconductor channel155A, may be referred to as an upper channel hole structure. Similar to the openings116A, the upper channel hole structure has a taper part extending through the dielectric stack143in some aspects. The taper parts of the upper and lower channel hole structures have connected ends with different dimensions. The bottom dimension of the upper channel hole structure is smaller than the top dimension of the lower channel hole structure.

After the semiconductor channel155A is formed, the opening of the channel hole is filled by an oxide material and a conductive plug is formed at the top of the upper channel hole structure, as shown inFIG.22. The conductive plug is connected to the semiconductor channel155A and may be formed by, e.g., doped polysilicon. The upper channel hole structures are formed in channel hole regions150A. The conductive plug in the upper channel hole structure may be referred to as an upper conductive plug.

FIG.23shows a schematic cross-sectional view of the structure of the 3D array device100after an opening121for a staircase contact (SCT) is formed according to aspects of the present disclosure. The opening121is in an SCT region120as depicted in the figure. The opening121may be formed by, for example, a dry etch process or a combination of dry and wet etch processes. The opening may extend through the dielectric stack143or stacks143and140in the Z direction to reach a target layer, such as a dielectric layer142A or142. The opening121has a taper angle in some cases. Provided the opening121penetrates through the stacks143and140and at the bottom of the opening121, exposes a target dielectric layer142of the stack140. Further, a dielectric material (e.g., aluminum oxide) is deposited to grow a spacer layer122on the sidewall and bottom surface of the opening121by CVD or ALD. The spacer layer122may be configured to electrically isolate the SCT. Further, an etch, such as a dry etch, is conducted to etch away the spacer layer122at the bottom of the opening121, exposing the target dielectric layer142again. Then, a selective etch, such as a selective wet etch, is arranged to etch out a portion of the target dielectric layer142(i.e., a silicon nitride layer). The selective etch may last for a predetermined time to create a cavity121A after the portion of the layer142is removed, as shown inFIG.24. After the etch, a material such as polysilicon is deposited to fill the opening121and cavity121A by CVD and/or ALD. The deposition process creates a filling structure123in the opening121and a layer124in the cavity121A, as depicted inFIG.25. The layer124is between the dielectric layers141. In some cases, a void forms in the filling structure123.

FIGS.26and27show a schematic cross-sectional view and a schematic top view of the structure of the 3D array device100after a filling structure133and an opening166are formed according to aspects of the present disclosure. The cross-sectional view shown inFIG.26is taken along a line CC′ ofFIG.27. After the filling structure123is made in the SCT region120, similar processes may be performed to etch additional openings and fill these openings with filling structures. Provided an opening (not shown) is formed in an SCT region130, exposing a target dielectric layer142of the stack140. A dielectric material (e.g., aluminum oxide) is deposited to grow a spacer layer132on the sidewall and bottom surface of the opening. The spacer layer132at the bottom of the opening is etched to expose the target dielectric layer142. A selective etch is performed to remove a portion of the target dielectric layer142to create a cavity (not shown). Thereafter, a material such as polysilicon is deposited to fill the opening and cavity, creating a filling structure133and a layer134.

A planarization process may be performed by CMP after the filling structure133is made. Further, one or more selective etches, such as selective wet etches, are performed to etch away filling a part of the structures165and163, respectively. An opening166is formed that extends through the dielectric stacks143and140along the Z direction and exposes the semiconductor layer158. For reasons illustrated above, the opening166has taper parts through the dielectric stacks140and143, respectively, in some cases.

As shown inFIG.27, the selective etch removes a part of the filling structure165, while the remaining filling structure165stay there. The opening166exposes sides of the dielectric layers142and142A of the dielectric stacks140and143. Further, a selective etch (e.g., a selective wet etch) is performed to remove certain portions of the dielectric layers142and142A, leaving cavities144between the dielectric layers141and cavities144A between dielectric layers141A, as shown inFIG.28. As such, parts of the dielectric stacks140and143are changed into dielectric stack145and146, respectively.

Further, a conductive material such as tungsten (W) is grown to fill the cavities144and144A, forming conductive layers147and147A, respectively. After the conductive layers147and147A are made, the dielectric stacks145and146are converted into conductor/insulator stacks148and149, as shown inFIG.29. The conductor/insulator stack148(or149) may be referred to as a conductor/insulator stack structure that has the dielectric layers141(or141A) and the conductive layers147(or147A) alternatingly stacked over each other. The stacks148and149contain the upper and lower channel hole structures, including the functional layers151and151A and semiconductor channels155and155A. The stacks148and149may also be referred to as decks that are stacked and aligned in the Z direction or vertical direction. The upper and lower channel hole structures each have a taper part through a conductor/insulator stack (the stack148or149), in some cases.

In some aspects, before metal W is deposited in the cavities144and144A, a layer (not shown) of a high-k dielectric material such as aluminum oxide may be deposited. Thereafter, a layer of a conductive material such as titanium nitride (TiN) (not shown) is deposited. Further, metal W is deposited to form the conductive layers147and147A. CVD and/or ALD may be used in the deposition processes. Alternatively, another conductive material, such as molybdenum (Mo), ruthenium (Ru), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), doped silicon, or any combination thereof, may be used to form the conductive layers147and147A.

Referring toFIG.29, a portion of each functional layer151(or151A) in a channel hole structure is between a portion of one of the conductive layers147(or147A) and a portion of a semiconductor channel155(or155A) in the channel hole structure. Each conductive layer147(or147A) is configured to connect rows of NAND memory cells in an X-Y plane and is configured as a word line for the 3D array device100. A pair of the connected semiconductor channels155and155A is configured to connect a column or a string of NAND memory cells along the Z direction and configured as a bit line for the 3D array device100. As such, a portion of the functional layer151(or151A) in an X-Y plane, as a part of a NAND memory cell, is arranged between a conductive layer147(or147A) and a semiconductor channel155(or155A), i.e., between a word line and a bit line. The functional layer151(or151A) may also be considered as disposed between the semiconductor channel155(or155A) and the conductor/insulator stack148(or149). A portion of the conductive layer147(or147A) that is around a portion of the lower (or upper) channel hole structure functions as a control gate or gate electrode for a NAND memory cell. The 3D array device100can be considered as including a 2D array of strings of NAND cells (such a string is also referred to as a “NAND string”) in the stacks148and149or the conductor/insulator stack structures. Each NAND string contains multiple NAND memory cells and extends vertically toward the substrate110. The NAND strings form a 3D array of the NAND memory cells through the conductor/insulator stacks148and149over the substrate110.

After the conductive layers147and147A are grown in the cavities, a dielectric layer (e.g., a silicon oxide layer) is deposited on the sidewall and bottom surface of the opening166by CVD and/or ALD. A dry etch process or a combination of dry etch and wet etch processes is performed to remove the dielectric layer at the bottom of the opening166to expose a part of the semiconductor layer158. The opening166is filled with a conductive material (e.g., doped polysilicon) and a conductive plug168(e.g., metal W). The conductive material forms a conductive filling structure167in the opening that extends through the conductor/insulator stacks148and149and electrically contacts the semiconductor layer158, as shown inFIG.30. The materials deposited in the opening166form the GLS structure. The conductive filling structure167is considered as an array common source for the 3D array device100in some aspects. Optionally, forming the array common source in the opening166includes depositing a conductive layer (such as TiN, W, Co, Cu, or Al), and then a conductive material such as doped polysilicon.

The GLS structure has a lower taper part and upper taper part extending through the conductor/insulator stack148and149in the vertical direction or Z direction, respectively, in some cases. The lower and upper taper parts taper along the vertical direction. For example, the horizontal dimension of the top end of the lower (or upper) taper part is larger than the horizontal dimension of the bottom end of the lower (or upper) taper part, as shown inFIG.30. The top end of the lower taper part connects with the bottom end of the upper taper part. In some cases, the horizontal dimension of the top end of the lower taper part is larger than the horizontal dimension of the bottom end of the upper taper part, as shown inFIG.30. In some other cases, the horizontal dimension of the top end of the lower taper part is smaller than the horizontal dimension of the bottom end of the upper taper part by a predetermined value. In these cases, when the opening164is made to expose the filling structure163, the horizontal dimension of the bottom of the opening164is larger than the horizontal dimension of the top of the filling structure163by a certain value. As such, the bottom of the opening164completely overlaps the top of the filling structure163with certain margins in the vertical direction.

Further, a selective etch (e.g., a selective wet etch) is performed to remove the filling structures123and133and layers125and135in the SCT regions120and130, forming openings126and136, and cavities125A and135A between the dielectric layers141. Before the etch, a dielectric layer (not shown) may be deposited over the channel hole structure regions150A to protect the upper channel hole structures. Certain conductive layers147(not shown) are exposed in the cavities125A and135A, while the spacer layers122and132remain as the sidewalls of the openings126and136.

After the conductive layers147are exposed in the cavities125A and135A, a conductive material (e.g., W) is deposited to fill the cavities and form conductive layers over the spacer layers122and132, respectively. The partially filled opening126and136are then filled with a dielectric material (e.g., silicon oxide), forming filling structures128and138. Cavities may form in the filling structures128and138in some cases. The conductive material (e.g., W) is deposited again to make SCTs127and137in the SCT regions120and130, respectively. The SCTs127and137are respectively connected to the conductive layers147electrically and used as contacts of word lines.

With reference toFIG.22, a third dielectric stack (not shown) may be deposited over the stack143in certain other embodiments. The third dielectric stack may have a similar structure to that of the dielectric stack140or143. With methods similar to that illustrated above, openings may be made that are aligned to the upper channel hole structures and the filling structure165, an additional filling structure may be deposited on the filling structure165, and additional channel hole structures may be formed that are aligned to and electrically connected with the upper channel hole structures. Then, three conductor/insulator stacks may be formed. A combined channel hole structure includes three sections or three taper parts passing through the three conductor/insulator stacks, respectively. The GLS structure also includes three taper parts passing through the three conductor/insulator stacks, respectively.

With reference toFIG.19, when the openings116A are etched, the opening164may not be etched in some cases. In these cases, after the upper channel hole structures are made, a third dielectric stack (not shown) may be deposited over the stack143. The third dielectric stack may have a similar structure to that of the dielectric stack140or143. With methods similar to that illustrated above, openings may be made that are aligned to the upper channel hole structures, and then additional channel hole structures may be formed that have a taper angle and are aligned to and electrically connected with the upper channel hole structures. Further, an opening may be formed that has a taper angle, is aligned to the filling structure163, extends through the third dielectric stack and the dielectric stack143, and exposes the filling structure163. Further, three conductor/insulator stacks may be formed. A combined channel hole structure includes three sections or three taper parts extending through the three conductor/insulator stacks, respectively. The GLS structure includes two taper parts that are connected with ends of different dimensions. One taper part of the GLS structure extends through the upper two conductor/insulator stacks, while the other taper part extends through the bottom conductor/insulator stack.

Referring toFIG.32, a CVD or PVD process is performed to deposit a dielectric material (e.g., silicon oxide) to cover the SCT regions120and130and the channel hole structure regions150A, thickening the dielectric layer119. Openings (not shown) for vias171-174are formed by a dry etch process or a combination of dry and wet etch processes. The openings are subsequently filled by a conductive material (e.g., W, Co, Cu, Mo, Ru, or Al) to form the vias171-174. The vias171-174electrically contact the array common source, the upper conductive plugs, and the SCTs, respectively. Optionally, a layer of a conductive material (e.g., TiN) may be deposited as a contact layer before another conductive material is deposited when the vias171-174are fabricated.

Further, conductor layers175for interconnect are grown by CVD, PVD, and/or ALD. The conductor layers175are deposited over and connected to the vias171-174, respectively, and include a conductive material such as W, Co, Cu, Al, Mo, Ru, or a combination thereof. Optionally, a contact layer (e.g., TiN) may be deposited before the conductive material is deposited to create the conductor layers175.

Further, vias176are formed over the conductor layers175. For example, a dielectric material may be deposited to cover the conductor layers175and make the dielectric layer119thicker. After openings for vias176are formed, a thin layer of TiN may be deposited in some cases. The openings are then filled with a conductive material to form the vias176. The conductive material of the vias176may include W, Co, Cu, Al, Mo, or Ru.

Further, a CVD or PVD process is performed to deposit a dielectric material (e.g., silicon oxide) to cover the vias176and thicken the dielectric layer119further. Openings are made and then filled to form connecting pads177,178, and179that serve as interconnects with a periphery device. As shown inFIG.33, the connecting pads177-179are deposited over and electrically contact the vias176, respectively. The connecting pads177-179may include a conductive material such as W, Co, Cu, Al, or a combination thereof. Optionally, a contact layer of a conductive material (e.g., TiN) may be deposited first before filling the openings to form the connecting pads177-179.

FIG.34shows a schematic cross-sectional view of a periphery device180according to aspects of the present disclosure. The periphery device180is a part of a 3D memory device and may also be referred to as a peripheral structure. The periphery device180includes a substrate181that may include single crystalline silicon, Ge, SiGe, SiC, SOI, GOI, polysilicon, or a Group III-V compound such as GaAs or InP. Periphery CMOS circuits186(e.g., control circuits) are fabricated on the substrate181and used for facilitating the operation of the 3D memory device. For example, the periphery CMOS circuits186may include metal-oxide-semiconductor field-effect transistors (MOSFETs) and provide functional devices such as page buffers, sense amplifiers, column decoders, and row decoders. A dielectric layer182is deposited over the substrate181and the CMOS circuits186. Connecting pads (such as connecting pads183-185) and vias for interconnect are formed in the dielectric layer182. The dielectric layer182includes one or more dielectric materials such as silicon oxide and silicon nitride. The connecting pads183-185are formed to connect with the 3D array device100and may include a conductive material such as W, Co, Cu, Al, Ti or a combination thereof.

For the 3D array device100and periphery device180, the bottom side of the substrate110or181may be referred to as the back side, and the side with the connecting pads177-179or183-185may be referred to as the front side or face side.

FIG.35schematically shows a fabrication process of an exemplary 3D memory device190in a cross-sectional view according to aspects of the present disclosure. The 3D memory device190includes the 3D array device100shown inFIG.33and the periphery device180shown inFIG.34.

The 3D array device100and periphery device180are bonded by a flip-chip bonding method to form the 3D memory device190, as shown inFIG.35. In some aspects, the 3D array device100is flipped vertically and becomes upside down with the top surfaces of the connecting pads177-179facing downward. The two devices are placed together such that the 3D array device100is above the periphery device180. After an alignment is made, e.g., the connecting pads177-179are aligned with the connecting pads183-185, respectively, the 3D array device100and periphery device180are joined face to face and bonded together. The conductor/insulator stacks148-149and the periphery CMOS circuits become sandwiched between the substrates110and181or between the layer111and the substrate181. In some aspects, a solder or a conductive adhesive is used to bond the connecting pads177-179with the connecting pads183-185, respectively. As such, the connecting pads177-179are connected to the connecting pads183-185, respectively. The 3D array device100and periphery device180are in electrical communication after the flip-chip bonding process is completed.

Thereafter, other fabrication steps or processes are performed to complete fabrication of the 3D memory device190. The other fabrication steps and processes are not reflected inFIG.35for simplicity. For example, from the bottom surface (after the flip-chip bonding), part of the substrate110may be removed by a thinning process, such as wafer grinding, dry etch, wet etch, CMP, or a combination thereof. Further, a passivation layer is deposited, contact pads are formed, and additional fabrication steps or processes are performed. Details of the additional fabrication steps or processes are omitted for simplicity.

FIG.36shows a schematic flow chart200for fabricating a 3D memory device according to aspects of the present disclosure. At210, a substrate is provided for fabricating a 3D array device. In some aspects, a first polysilicon layer, a silicon oxide layer, and a second polysilicon layer as a sacrificial layer are deposited over the substrate sequentially. A portion of the sacrificial layer is removed to create an opening by a selective etch. The opening is subsequently filled by a carbon material to form a carbon block that is embedded in the sacrificial layer. Further, a first dielectric stack of the 3D array device is fabricated over the sacrificial layer and carbon block. The first dielectric stack includes a first stack layer and a second stack layer that are alternately stacked. The first stack layer includes a first dielectric layer and the second stack layer includes a second dielectric layer that is different than the first dielectric layer. In some aspects, one of the first and second dielectric layers is used as a sacrificial stack layer. Assuming that the first dielectric layer is silicon oxide, while the second dielectric layer is silicon nitride and used as the sacrificial stack layer.

At211, openings for channel holes (i.e., channel holes) and an opening for GLS are formed that extend through the first dielectric stack. The opening for GLS is aligned to the carbon block along a direction approximately perpendicular to the substrate. The openings are etched by a selective etch at the same time. The etch rate of silicon oxide and silicon nitride is much faster than the etch rate of the carbon block. As such, the channel holes pass through the first dielectric stack and the sacrificial layer, and penetrate the first polysilicon layer partially, while the opening for GLS passes through the first dielectric stack, penetrates the carbon block partially, and does not reach the first polysilicon layer. The channel hole is deeper than the opening for GLS. The carbon block is exposed at the bottom of the opening for GLS.

At212, the channel holes are filled with a carbon material, and the opening for GLS is filling with NDC, respectively. The carbon material in the channel holes is removed in a selective etch, and first channel hole structures are formed in the channel holes. For example, a first functional layer is deposited on the sidewall and bottom surface of the channel hole. The first functional layer includes a blocking layer, a charge trap layer, and a tunneling layer that are deposited sequentially. Thereafter, a first semiconductor channel is grown on a surface of the tunneling layer. The first channel hole structure includes the first functional layer and first semiconductor channel.

At213, the filling material in the opening for GLS is removed in a selective etch, and NDC is deposited to grow a spacer layer on the sidewall of the opening for GLS. The NDC spacer layer is configured to protect the first and second dielectric layers. The carbon block is removed in another selective etch to expose the sacrificial layer at the bottom of the opening. The exposed sacrificial layer is etched in an additional selective etch, creating a cavity.

The cavity exposes a portion of the blocking layer of the first functional layer in the cavity. Then, the layers of the first functional layer exposed sequentially in the cavity, including the blocking layer, the charge trap layer, and the tunnel insulation layer, are etched away by, e.g., one or more selective etch processes, respectively. As a result, a portion of the first functional layer that is close to the substrate is removed and the side portion of the first semiconductor channel is exposed in the cavity. The cavity is filled with polysilicon to form a semiconductor layer. The semiconductor layer is connected with the first semiconductor channel electrically. Thereafter, the opening for GLS is filled again with a carbon material, forming a carbon filling structure.

At214, a second dielectric stack of the 3D array device is deposited over the first dielectric stack, the first channel hole structure, and the carbon filling structure. The second dielectric stack includes a third stack layer and a fourth stack layer that are alternately stacked. The third stack layer includes a third dielectric layer and the fourth stack layer includes a fourth dielectric layer that is different than the third dielectric layer. In some aspects, one of the third and fourth dielectric layers is used as a sacrificial stack layer. Exemplarily, the third dielectric layer is silicon oxide, while the fourth dielectric layer is silicon nitride and used as the sacrificial stack layer.

At215, openings for channel holes (i.e., channel holes) and an opening for GLS are formed at the same time by the same etch process. The openings extend through the second dielectric stack. The channel holes are aligned to the first channel hole structures, respectively. The opening for GLS is aligned to the carbon filling structure. The alignment is made along a direction approximately perpendicular to the substrate. At the bottom of the openings, the first channel hole structures and the carbon filling structure are exposed.

At216, the channel holes are filled with polysilicon, and the opening for GLS is filled with NDC. Polysilicon in the channel holes is removed in a selective etch, exposing the conductive plug of the first channel hole structure. Part of the conductive plug may be etched out when the conductive plug contains polysilicon. Further, second channel hole structures are formed in the channel holes. For example, a second functional layer is deposited on the sidewall and bottom surface of the channel hole. The second functional layer includes a blocking layer, a charge trap layer, and a tunneling layer that are deposited sequentially. The second functional layer on the bottom surface of the channel hole is etched away. Thereafter, a second semiconductor channel is grown on a surface of the tunneling layer and the conductive plug of the first channel hole structure. The second channel hole structure includes the second functional layer and second semiconductor channel. The second semiconductor channel electrically contacts the conductive plug of the first channel hole structure. The first and second channel hole structures are electrically connected, since the first and second semiconductor channels are electrically connected.

In some cases, a third dielectric stack may be deposited over the second dielectric stack and similar methods may be used to make the third channel hole structures and a filling structure in an opening for GLS. For simplicity, processes to make the third dielectric stack and third channel hole structures are omitted. Descriptions below illustrate the 3D array device with the first and second dielectric stacks.

At217, an opening for SCT is formed by etch. The opening for SCT extends toward the substrate to reach and expose a target second dielectric layer or fourth dielectric layer. A dielectric material such as aluminum oxide is deposited to form a spacer layer on the sidewall of the opening for SCT. A selective etch is performed to create a cavity by removing a section of the target second or fourth dielectric layer. The opening and cavity are then filled with polysilicon in a deposition process. Further, additional openings and cavities may be made and then filled with polysilicon. The additional cavities each expose a respective second dielectric layer or fourth dielectric layer. In some embodiments, the openings for SCT may be formed and then filled between214and215, i.e., after the second dielectric stack is made and before the openings for the second channel hole structure and GLS are etched. In these cases, the second channel hole structures may be fabricated after the openings for SCT are formed.

Further, NDC filled in the opening for GLS and the carbon filling structure are removed in selective etches, forming a GLS opening that reaches and exposes the semiconductor layer at the bottom. The first to fourth dielectric layers are also exposed on the sidewall. The exposed second and fourth dielectric layers are etched out in a selective etch and cavities are formed. The cavities are filled with a conductive material to form conductive layers in a cavity filling process. The conductive layers are word lines. Optionally, the cavity filling process may include depositing a layer of a high-k dielectric material, a layer of TiN, and a metallic material (e.g., W) consecutively. The first and second dielectric stacks are transformed into the first and second conductor/insulator stacks.

Further, a dielectric layer such as an oxide layer is deposited on the sidewall and bottom surface of the opening for GLS. Part of the dielectric layer on the bottom surface is etched out selectively to expose the semiconductor layer. Electrically conductive materials, such as TiN, W, Cu, Al, and/or doped polysilicon is deposited in the opening for GLS to form an array common source that electrically contacts the semiconductor layer.

Further, polysilicon in the openings for SCT and cavities is removed in a selective etch, which exposes the dielectric spacer layers on the sidewalls and corresponding conductive layers in the cavities. A conductive material, such as W, Co, Cu, or Al, is deposited in the openings for SCT and cavities to form SCTs. The SCTs electrically contact the exposed conductive layers and thus are electrically connected with certain word lines, respectively. Optionally, a layer of TiN may be grown as a contact layer and/or barrier layer before depositing the conductive material to make the SCTs.

At218, etching and deposition processes are performed to form other contacts including through silicon contacts that extend from the top surface towards the substrate. These contacts may be made of a conductive material such as W, Co, Cu, or Al. Further, silicon oxide is deposited to form a silicon oxide layer that covers the top surface. Openings are formed and filled in the silicon oxide layer to make vias. The vias may connect with the SCTs, the second channel hole structures, the through silicon contacts, etc. Thereafter, conductor layers, additional vias, and connecting pads are fabricated for the 3D array device.

Further, a flip-chip bonding process is performed to bond the 3D array device and a periphery device to create a 3D memory device. In some aspects, the 3D array device is flipped upside down and positioned above the periphery device. The connecting pads of the 3D array device and the periphery device are aligned and then bonded. Optionally, the substrate of the 3D array device is thinned. Etching and deposition processes are performed to form vias, conductor layers, and contact pads for the 3D memory device. The contact pads are configured for wire bonding for connection with other devices.

As illustrated above, the channel holes and opening for GLS are formed simultaneously by the same process. Compared to forming the channel holes and opening for GLS separately by two processes, the fabrication cost may be reduced in some cases. In addition, multiple dielectric stacks may be built by depositing a first dielectric stack, forming first channel hole structures, forming a first filling structure in a first GLS opening, depositing a second dielectric stack over the first dielectric stack, forming second channel hole structures, forming a second filling structure in a second GLS opening, and so on. As such, more layers for memory cells may be fabricated. The capacity of the 3D memory device may be increased. Further, certain risks of mechanical instability may be lowered to improve the yield and reliability.

FIG.37shows a block diagram of an exemplary system300having a memory device according to various aspects of the present disclosure. The system300may be a mobile phone (e.g., a smartphone), a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown inFIG.37, the system300may include a host308and a memory system302having one or more memory devices304and a memory controller306. The host308may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host308may be configured to send or receive data to or from the memory devices304.

The memory controller306is coupled to the memory devices304and host308and is configured to control the memory devices304, according to some implementations. The memory controller306may manage the data stored in the memory devices304and communicate with the host308. In some embodiments, the memory controller306is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some other embodiments, the memory controller306is designed for operating in a high duty-cycle environment, such as solid-state drives (SSDs) or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. The memory controller306may be configured to control operations of the memory device304, such as read, erase, and program operations.

The memory controller306may also be configured to manage various functions with respect to the data stored or to be stored in the memory device304including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, the memory controller306is further configured to process error correction codes (ECCs) with respect to the data read from or written to the memory device304. Any other suitable functions may be performed by the memory controller306as well, for example, formatting the memory device304. The memory controller306may communicate with an external device (e.g., the host308) according to a particular communication protocol. For example, the memory controller306may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

The memory device304may be any memory device disclosed in the present disclosure, such as the 3D memory device190shown inFIG.35. As the 3D memory device190may have lower fabrication costs and improved yield and reliability due to reasons described above, when the device190is used, the system300may have these merits, as well.

The memory controller306and one or more memory devices304may be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, the memory system302may be implemented and packaged into different types of end electronic products.FIGS.38and39exemplarily illustrate block diagrams of a memory card400and an SSD500according to various aspects of the present disclosure. As shown inFIG.38, a memory controller404and a single memory device402may be integrated into the memory card400. The memory device402may be any memory device illustrated above, such as the 3D memory device190shown inFIG.35. The memory card400may include a PC card (personal computer memory card international association (PCMCIA)), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, or MMCmicro), an SD card (SD, miniSD, microSD, or SDHC), a UFS, etc. The memory card400may further include a memory card connector406configured to couple the memory card400to a host (e.g., the host308shown inFIG.37). As shown inFIG.39, a memory controller504and multiple memory devices502may be integrated into the SSD500. The memory devices502may be any aforementioned memory device, such as the 3D memory device190shown inFIG.35. The SSD500may further include an SSD connector506configured to couple the SSD500to a host (e.g., the host308shown inFIG.37). In some embodiments, the storage capacity and/or the operation speed of the SSD500is greater than those of the memory card400.

Although the principles and implementations of the present disclosure are described by using specific aspects in the specification, the foregoing descriptions of the aspects are only intended to help understand the present disclosure. In addition, features of aforementioned different aspects may be combined to form additional aspects. A person of ordinary skill in the art may make modifications to the specific implementations and application range according to the idea of the present disclosure. Hence, the content of the specification should not be construed as a limitation to the present disclosure.