Prioritized power budget arbitration for multiple concurrent memory access operations

A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to prioritized power budget arbitration for multiple concurrent memory access operations.

BACKGROUND

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to prioritized power budget arbitration for multiple concurrent memory access operations. One example of non-volatile memory devices is a negative-and (NAND) memory device. A memory device, to include each die of a multi-dice memory device, can be made up of bits arranged in a two-dimensional or a three-dimensional grid of memory cells. One or more physical blocks of memory cells can be grouped together to form a plane of the memory device in order to allow concurrent operations to take place on each plane, where these physical blocks are made up of groups of pages of memory cells.

Each memory die can include circuitry that performs concurrent memory page accesses of two or more memory planes. For example, each memory die can include multiple access line driver circuits and power circuits that can be shared by the planes of each memory die to facilitate concurrent access of pages of two or more memory planes, including different page types. For ease of description, these circuits can be generally referred to as independent plane driver circuits. Control logic on each die of the memory device includes a number of separate processing threads to perform concurrent memory access operations (e.g., read operations, program operations, and erase operations). For example, each processing thread corresponds to a respective memory plane and utilizes the associated independent plane driver circuits to perform the memory access operations on the respective memory plane. As these processing threads operate independently, the power usage and requirements associated with each processing thread also varies.

The capacitive loading of three-dimensional memory is generally large and may continue to grow as process scaling continues. Various access lines, data lines and voltage nodes can be charged or discharged very quickly during sense (e.g., read or verify), program, and erase operations so that memory array access operations can meet the performance specifications that are often required to satisfy data throughput targets as might be dictated by customer requirements or industry standards, for example. For sequential read or programming, multi-plane operations are often used to increase the system throughput. As a result, a typical memory die can have a high peak current usage, which might be four to five times the average current amplitude. Thus, with such a high average market requirement of total current usage budget, it can become challenging to operate more than four memory dice concurrently, for example.

A variety of techniques have been utilized to manage power consumption of memory sub-systems containing multiple memory dice, many of which rely on a memory sub-system controller to stagger the activity of the memory dice seeking to avoid performing high power portions of access operations concurrently in more than one memory dice. Further, as additional processing threads are utilized on each individual memory die (e.g., 4, 6, or 8 processing threads), these power management techniques are not adequate to account for the added complexity associated with budgeting current usage within each individual memory die.

Aspects of the present disclosure address the above and other deficiencies by providing prioritized power budget arbitration for multiple concurrent access operations in a memory device of a memory sub-system. In some embodiments, the memory device includes multiple dice, each die including multiple processing threads configured to perform the concurrent memory access operations, e.g., on corresponding memory planes of the memory dice. Each memory die further includes a threads manager and a peak power manager (PPM) that are together configured to perform prioritized power budget arbitration for the multiple processing threads on respective memory die of the multiple memory dice.

In these embodiments, the memory sub-system employs a token-based round robin protocol, whereby each PPM rotates (e.g., after a set number of cycles of a shared clock signal) as a holder of the token and broadcasts a quantized current budget to be consumed by its respective memory die during a given time period. The other PPMs on each other memory die receive this broadcast information, and thus, can determine an available current budget in the memory device during the time period. While holding the token, a PPM can request a certain amount of current for its respective memory die up to the available current budget in the memory device and based on an amount of current being consumed by the other memory dice of the memory device. As described in further detail below, the PPM can employ a number of different techniques to allocate the requested current among the multiple processing threads of the respective memory die, at least some of which include prioritized management of multiple concurrent processing threads.

In at least some embodiments, each die also includes a priority ring counter and a data structure (such as a lookup table) where the data structure is to store an association between a value of the priority ring counter and a subset of the multiple processing threads. Each die can further include a threads manager configured to manage the multiple processing threads presented to the PPM for power allocation. In these embodiments, the threads manager can increment the value of the priority ring counter before a power management cycle. Each new counter value changes the subset of the multiple processing threads under consideration for power allocation, and thus simplifies the number of processing threads that the PPM can manage concurrently. The threads manager can also identify one or more prioritized processing threads within the subset of the multiple processing threads, and provide identification of prioritization with the one or more prioritized processing threads to the PPM. The PPM can then prioritize allocation requests when the die of the PPM holds the token, e.g., by prioritizing allocation of power to the one or more prioritized processing threads located within the subset of the multiple processing threads during the power management cycle. The PPM of the die can also check power allocation to the one or more prioritized processing threads against a power (e.g., current) budget available and thus avoid going over budget despite prioritization of some processing threads over others.

In at least some embodiments, the PPM of a die can also manage shifts between non-prioritized management of subsets of the multiple processing threads and prioritized management of the subsets of the multiple processing threads. For example, the PPM can start a timer while a non-prioritized processing thread (e.g., an erase operation or a program operation) is running and in response to detecting allocation of the power also to a prioritized thread of the multiple processing threads (e.g., a read operation or a program operation). The timer can track a predetermined amount of time in order to ensure that prioritized allocation requests do not starve the non-prioritized processing thread of current needed to complete processing. Thus, if the timer expires while the non-prioritized processing thread is still running, the control logic can force a transition back to allocating power between subsets of the processing threads based on increments to the value of a non-priority counter, e.g., based on non-prioritized power allocation.

Advantages of this approach include, but are not limited to, an effective power management scheme for a multi-dice memory sub-system where each memory die supports multiple processing threads operating concurrently. The disclosed techniques allow support for independent parallel plane access in a memory device with significantly reduced hardware resources in the memory sub-system. This approach is highly scalable as the number of processing threads increases and does not rely on external controller intervention. Further, by prioritizing power allocation to some processing threads depending on which subset of multiple processing threads is being managed, memory operations that should be processed quickly (such as read operations and some program operations) can be prioritized over memory operations that can be performed more slowly (such as erase operations and some program operations). The allocated power to the prioritized processing threads can still be checked against a power (e.g., current) budget to ensure not exceeding the budget. Further, as mentioned, use of the timer and shifting protocols can ensure that non-prioritized processing threads are not starved of power budget. Thus, the overall performance and quality of service provided by each memory die is improved.

FIG.1Aillustrates an example computing system100that includes a memory sub-system110according to at least some embodiments. The memory sub-system110can include media, such as one or more volatile memory devices (e.g., memory device140), one or more non-volatile memory devices (e.g., one or more memory device(s)130), or a combination of such media or memory devices. The memory sub-system110can be a storage device, a memory module, or a hybrid of a storage device and memory module.

The memory device(s)130can be non-volatile memory device(s). One example of non-volatile memory devices is a negative-and (NAND) memory device. A non-volatile memory device is a package of one or more dice or logical unit (LUNs). Thus, each memory device130can be a die (or LUN) or can be a multi-dice package that includes multiple dice (or LUNs) on a chip, e.g., an integrated circuit package of dice. Each die can include one or more planes. Planes can be grouped into logic units (LUN). For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values.

Each memory device130can be made up of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are etched onto a silicon wafer in an array of columns (also hereinafter referred to as bitlines) and rows (also hereinafter referred to as wordlines). A wordline can refer to one or more rows of memory cells of a memory device that are used with one or more bitlines to generate the address of each of the memory cells. The intersection of a bitline and wordline constitutes the address of the memory cell.

In at least some embodiments, each memory device130includes a peak power manager (PPM) wrapper150that includes a threads manager155and a PPM160(peak power manager). In one embodiment, local media controller135of each memory device130includes at least a portion of the PPM wrapper150. In such an embodiment, PPM wrapper150can be implemented using hardware or as firmware, stored on each memory device130, executed by the control logic (e.g., local media controller135) to perform the operations related to prioritized power budget arbitration for multiple concurrent access operations described herein. In some embodiments, the memory sub-system controller115includes at least a portion of the PPM wrapper150. For example, the memory sub-system controller115can include a processor117(e.g., a processing device) configured to execute instructions stored in local memory119for performing the operations described herein.

In at least some embodiments, the PPM wrapper150can manage power prioritized budget arbitration for multiple concurrent access operations in the memory device(s)130. In one embodiment, memory sub-system110employs a token-based protocol, where a token rotates (e.g., in round robin fashion) among multiple PPM wrappers150of multiple memory dice (e.g., after a set number of cycles of a shared clock signal). When the PPM wrapper150of a die holds the token, the PPM wrapper150can determine the power (e.g., current) requested by multiple processing threads (e.g., implemented by local media controller135) of each memory device130, select one or more prioritized processing threads of those multiple processing threads based on an available power budget in the memory sub-system, request that power from a shared current source in memory sub-system110, and allocate the requested power to the selected processing threads. In some embodiments, if power is allocated to all prioritized processing threads and budget remains, the PPM wrapper150can allocate power to non-prioritized processing threads as well. The PPM wrapper150can further broadcast a quantized current budget to be consumed by the memory die during a given time period, so that the other PPM wrappers in memory sub-system110are aware of the available power budget. Further details with regards to the operations of each PPM wrapper150are described below.

FIG.1Bis a simplified block diagram of a first apparatus, in the form of the one or more memory device(s)130, in communication with a second apparatus, in the form of a memory sub-system controller115of a memory sub-system (e.g., the memory sub-system110ofFIG.1A), according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The memory sub-system controller115(e.g., a controller external to each memory device130), can be a memory controller or other external host device.

Each memory device130includes an array of memory cells104logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a word line) while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line can be associated with more than one logical row of memory cells and a single data line can be associated with more than one logical column. Memory cells (not shown inFIG.1B) of at least a portion of the array of memory cells104are capable of being programmed to one of at least two target data states.

Row decode circuitry108and column decode circuitry111are provided to decode address signals. Address signals are received and decoded to access the array of memory cells104. Each memory device130also includes input/output (I/O) control circuitry112to manage input of commands, addresses and data to the memory device130as well as output of data and status information from each memory device130. An address register114is in communication with the I/O control circuitry112and row decode circuitry108and column decode circuitry111to latch the address signals prior to decoding. A command register124is in communication with the I/O control circuitry112and the local media controller135to latch incoming commands.

A controller (e.g., the local media controller135internal to each memory device130) controls access to the array of memory cells104in response to the commands and generates status information for the external memory sub-system controller115, i.e., the local media controller135is configured to perform access operations (e.g., read operations, programming operations and/or erase operations) on the array of memory cells104. The local media controller135is in communication with row decode circuitry108and column decode circuitry111to control the row decode circuitry108and column decode circuitry111in response to the addresses.

The local media controller135is also in communication with a cache register118and a data register121. The cache register118latches data, either incoming or outgoing, as directed by the local media controller135to temporarily store data while the array of memory cells104is busy writing or reading, respectively, other data. During a program operation (e.g., write operation), data can be passed from the cache register118to the data register121for transfer to the array of memory cells104; then new data can be latched in the cache register118from the I/O control circuitry112. During a read operation, data can be passed from the cache register118to the I/O control circuitry112for output to the memory sub-system controller115; then new data can be passed from the data register121to the cache register118. The cache register118and/or the data register121can form (e.g., can form at least a portion of) the page buffer of each memory device130. The page buffer can further include sensing devices such as a sense amplifier, to sense a data state of a memory cell of the array of memory cells104, e.g., by sensing a state of a data line connected to that memory cell. A status register122can be in communication with I/O control circuitry112and the local memory controller135to latch the status information for output to the memory sub-system controller115.

Each memory device130receives control signals at the memory sub-system controller115from the local media controller135over a control link132. For example, the control signals can include a chip enable signal CE #, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE #, a read enable signal RE #, and a write protect signal WP #. Additional or alternative control signals (not shown) can be further received over control link132depending upon the nature of each memory device130. In one embodiment, each memory device130receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controller115over a multiplexed input/output (I/O) bus134and outputs data to the memory sub-system controller115over I/O bus134.

For example, the commands can be received over input/output (I/O) pins [7:0] of I/O bus134at I/O control circuitry112and can then be written into a command register124. The addresses can be received over input/output (I/O) pins [7:0] of I/O bus134at I/O control circuitry112and can then be written into address register114. The data can be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry112and then can be written into cache register118. The data can be subsequently written into data register121for programming the array of memory cells104.

In an embodiment, cache register118can be omitted, and the data can be written directly into data register121. Data can also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference can be made to I/O pins, they can include any conductive node providing for electrical connection to each memory device130by an external device (e.g., the memory sub-system controller115), such as conductive pads or conductive bumps as are commonly used.

FIG.2is a block diagram illustrating a multi-dice package with multiple memory dice in a memory sub-system according to at least some embodiments. As illustrated, multi-dice package200includes any of memory dice230(0)-230(7). In other embodiments, however, multi-dice package200can include some other number of memory dice, such as additional or fewer memory dice. In at least one embodiment, the multi-dice package200is at least one of the memory devices130illustrated and discussed with respect toFIGS.1A-1B. In one embodiment, memory dice230(0)-230(7) share a clock signal ICLK which is received via a clock signal line. Memory dice230(0)-230(7) can be selectively enabled in response to a chip enable signal (e.g. via a control link), and can communicate over a separate I/O bus. In addition, a peak current magnitude indicator signal HC # is commonly shared between the memory dice230(0)-230(7). The peak current magnitude indicator signal HC # can be normally pulled to a particular state (e.g., pulled high). In one embodiment, each of memory dice230(0)-230(7) includes an instance of the PPM wrapper150, which receives both the clock signal ICLK and the peak current magnitude indicator signal HC #.

In one embodiment, a token-based protocol is used where a token cycles through each of the memory dice230(0)-230(7) for determining and broadcasting expected peak current magnitude, even though some of the memory dice230(0)-230(7) might be disabled in response to their respective chip enable signal. The period of time during which a given PPM wrapper150holds this token (e.g. a certain number of cycles of clock signal ICLK) can be referred to herein as a power management cycle of the associated memory die. At the end of the power management cycle, the token is passed to a next memory die in sequence. Eventually the token is received again by the same PPM wrapper150which signals the beginning oft hew power management cycle for the associated memory die. In one embodiment, the encoded value for the lowest expected peak current magnitude is configured such that each of its digits correspond to the normal logic level of the peak current magnitude indicator signal HC # where the disabled dice do not transition the peak current magnitude indicator signal HC #. In other embodiments, however, the memory dice can be configured, when otherwise disabled in response to their respective chip enable signal, to drive transitions of the peak current magnitude indicator signal HC # to indicate the encoded value for the lowest expected peak current magnitude upon being designated.

When a given PPM wrapper150holds the token, it can determine the peak current magnitude for the respective one of memory die230(0)-230(7), which can be attributable to one or more processing threads on that memory die, and broadcast an indication of the same via the peak current magnitude indicator signal HC #. As described in more detail below, during a given power management cycle, the PPM wrapper150can arbitrate among the multiple processing threads on the respective memory die using one of a number of different arbitration schemes in order to allocate that peak current to enable concurrent memory access operations.

FIG.3is a block diagram illustrating a multi-plane memory device130A configured for independent parallel plane access according to at least some embodiments. In at least one embodiment, the multi-plane memory device130A is at least one of the memory device(s)130illustrated and discussed with reference toFIGS.1A-1B. The memory planes372(0)-372(3) can each be divided into blocks of data, with a different relative block of data from two or more of the memory planes372(0)-372(3) concurrently accessible during memory access operations. For example, during memory access operations, two or more of data block382of the memory plane372(0), data block383of the memory plane372(1), data block384of the memory plane372(2), and data block385of the memory plane372(3) can each be accessed concurrently.

The memory device130A includes a memory array370divided into memory planes372(0)-372(3) that each includes a respective number of memory cells. The multi-plane memory device130A can further include local media controller135, including a power control circuit and access control circuit for concurrently performing memory access operations for different memory planes372(0)-372(3). The memory cells can be non-volatile memory cells, such as NAND flash cells, or can generally be any type of memory cells.

The memory planes372(0)-372(3) can each be divided into blocks of data, with a different relative block of data from each of the memory planes372(0)-372(3) concurrently accessible during memory access operations. For example, during memory access operations, data block382of the memory plane372(0), data block383of the memory plane372(1), data block384of the memory plane372(2), and data block385of the memory plane372(3) can each be accessed concurrently.

Each of the memory planes372(0)-372(3) can be coupled to a respective page buffer376(0)-376(3). Each page buffer376(0)-376(3) can be configured to provide data to or receive data from the respective memory plane372(0)-372(3). The page buffers376(0)-376(3) can be controlled by local media controller135. Data received from the respective memory plane372(0)-372(3) can be latched at the page buffers376(0)-376(3), respectively, and retrieved by local media controller135, and provided to the memory sub-system controller115via the NVMe interface.

Each of the memory planes372(0)-372(3) can be further coupled to a respective access driver circuit374(0)-374(3), such as an access line driver circuit. The driver circuits374(0)-374(3) can be configured to condition a page of a respective block of an associated memory plane372(0)-372(3) for a memory access operation, such as programming data (i.e., writing data), reading data, or erasing data. Each of the driver circuits374(0)-374(3) can be coupled to a respective global access lines associated with a respective memory plane372(0)-372(3). Each of the global access lines can be selectively coupled to respective local access lines within a block of a plane during a memory access operation associated with a page within the block. The driver circuits374(0)-374(3) can be controlled based on signals from local media controller135. Each of the driver circuits374(0)-374(3) can include or be coupled to a respective power circuit, and can provide voltages to respective access lines based on voltages provided by the respective power circuit. The voltages provided by the power circuits can be based on signals received from local media controller135.

The local media controller135can control the driver circuits374(0)-374(3) and page buffers376(0)-376(3) to concurrently perform memory access operations associated with each of a group of memory command and address pairs (e.g., received from memory sub-system controller115). For example, local media controller135can control the driver circuits374(0)-374(3) and page buffer376(0)-376(3) to perform the concurrent memory access operations. Local media controller135can include a power control circuit that serially configures two or more of the driver circuits374(0)-374(3) for the concurrent memory access operations, and an access control circuit configured to control two or more of the page buffers376(0)-376(3) to sense and latch data from the respective memory planes372(0)-372(3), or program data to the respective memory planes372(0)-372(3) to perform the concurrent memory access operations.

In operation, local media controller135can receive a group of memory commands and address pairs via the NVMe bus, with each pair arriving in parallel or serially. In some examples, the group of memory commands and address pairs can each be associated with different respective memory planes372(0)-372(3) of the memory array370. The local media controller135can be configured to perform concurrent memory access operations (e.g., read operations or program operations) for the different memory planes372(0)-372(3) of the memory array370responsive to the group of memory commands and address pairs. For example, the power control circuit of local media controller135can serially configure, for the concurrent memory access operations based on respective page type (e.g., UP, MP, LP, XP, SLC/MLC/TLC/QLC page), the driver circuits374(0)-374(3) for two or more memory planes372(0)-372(3) associated with the group of memory commands and address pairs. After the access line driver circuits374(0)-374(3) have been configured, the access control circuit of the local media controller135can concurrently control the page buffers376(0)-376(3) to access the respective pages of each of the two or more memory planes372(0)-372(3) associated with the group of memory commands and address pairs, such as retrieving data or writing data, during the concurrent memory access operations. For example, the access control circuit can concurrently (e.g., in parallel and/or contemporaneously) control the page buffers376(0)-376(3) to charge/discharge bitlines, sense data from the two or more memory planes372(0)-372(3), and/or latch the data.

Based on the signals received from local media controller135, the driver circuits374(0)-374(3) that are coupled to the memory planes372(0)-372(3) associated with the group of memory command and address command pairs can select blocks of memory or memory cells from the associated memory plane372(0)-372(3), for memory operations, such as read, program, and/or erase operations. The driver circuits374(0)-374(3) can drive different respective global access lines associated with a respective memory plane372(0)-372(3). As an example, the driver circuit374(0) can drive a first voltage on a first global access line associated with the memory plane372(0), the driver circuit374(1) can drive a second voltage on a third global access line associated with the memory plane372(1), the driver circuit374(2) can drive a third voltage on a seventh global access line associated with the memory plane372(2), etc., and other voltages can be driven on each of the remaining global access lines. In some examples, pass voltages can be provided on all access lines except on an access line associated with a page of a memory plane372(0)-372(3) to be accessed. The local media controller135, the driver circuits374(0)-374(3) can allow different respective pages, and the page buffers376(0)-376(3) within different respective blocks of memory cells, to be accessed concurrently. For example, a first page of a first block of a first memory plane can be accessed concurrently with a second page of a second block of a second memory plane, regardless of page type.

The page buffers376(0)-376(3) can provide data to or receive data from the local media controller135during the memory access operations responsive to signals from the local media controller135and the respective memory planes372(0)-372(3). The local media controller135can provide the received data to memory sub-system controller115.

It will be appreciated that the memory device130A can include more or less than four memory planes, driver circuits, and page buffers. It will also be appreciated that the respective global access lines can include 8, 16, 32, 64, 128, etc., global access lines. The local media controller135and the driver circuits374(0)-374(3) can concurrently access different respective pages within different respective blocks of different memory planes when the different respective pages are of a different page type. For example, local media controller135can include a number of different processing threads, such as processing threads334(0)-334(3). Each of processing threads334(0)-334(3) can be associated with a respective one of memory planes372(0)-372(3) and can manage operations performed on the respective plane. For example, each of processing threads334(0)-334(3) can provide control signals to the respective one of driver circuits374(0)-374(3) and page buffers376(0)-376(3) to perform those memory access operations concurrently (e.g., at least partially overlapping in time). Since the processing threads334(0)-334(3) can perform the memory access operations, each of processing threads334(0)-334(3) can have different current requirements at different points in time. According to the techniques described herein, the PPM wrapper150can determine the power budget needs of processing threads334(0)-334(3) in a given power management cycle and identify one or more of processing threads334(0)-334(3) using one of a number of power budget arbitration schemes described herein. The one or more processing threads334(0)-334(3) can be determined based on an available power budget in the memory sub-system110during the power management cycles. For example, the PPM wrapper150can determine respective priorities of processing threads334(0)-334(3), and allocate current to processing threads334(0)-334(3) based on the respective priorities.

FIG.4is a block diagram illustrating a memory die400configured for power budget arbitration for multiple processing threads according to at least some embodiments. In some embodiments, the memory die400includes control logic, such as the PPM wrapper150, which in turn includes the threads manager155and the PPM160discussed with reference toFIG.1A. The memory die400further includes a memory456, e.g., a register, DRAM, SDRAM, or the like, although the memory456can also make reference to the memory array370in some embodiments. In these embodiments, the threads manager155includes request registers452(or other internal PPM memory) and includes or is coupled to a timer478. The threads manager155can further include a non-priority ring counter444and a priority ring counter454that are coupled to the memory456, e.g., for access to a data structure448and a data structure458, respectively. The PPM160is coupled to the threads manager155, can also be coupled with the memory456, and receives both the clock signal ICLK and the peak current magnitude indicator signal HC #, as were discussed previously.

In some embodiments, the threads manager155identifies one or more processing threads, such as multiple processing threads434(0)-434(3) in memory die400, and requests the PPM160to determine whether an available current (e.g., power) budget can support running the one or more processing threads based on an amount of power associated with the one or more processing threads during a power management cycle. More specifically, because the multiple processing threads434(0)-434(3) can generate different requests asynchronously, to manage such complexity, the threads manager155can manipulate and summarize these asynchronous requests in a simplified number of requests for the PPM160. In some embodiments, a set of simplified requests sent to the PPM160can contain randomized thread requests to ensure equity of allocation of current to the multiple processing threads434(0)-434(3). As will be discussed in more detail, the randomization of the requests sent by the threads manger155to the PPM160can be performed by the non-priority ring counter444, by the priority ring counter454, or can shift between the two ring counters as will be discussed. In some embodiments, the multiple processing threads434(0)-434(3) correspond to the processing threads334(0)-334(3) (FIG.3).

In some embodiments, the PPM160periodically asserts a polling window signal460, which is received by the threads manager155. The polling window signal460is asserted after the end of a previous power management cycle (e.g., when the PPM160gives up the token) and prior to the beginning of a subsequent power management cycle (e.g., when PPM160receives the token again). As the processing threads434(0)-434(3) are regularly issuing requests for current depending on associated processing operations, during a period when the polling window signal460is asserted, the threads manager155stores or buffers the received requests in a the request registers452. While requests are often referred to herein as requesting current allocation, this should be understood as requesting power generally, e.g., can also include requesting voltage allocation.

In some embodiments, the PPM160tracks the token and can determine when the token will be received (e.g., based on synchronous clock signal ICLK) and can de-assert the polling window signal460in advance of that time. Responsive to the polling window signal460being deasserted (i.e., during the subsequent the power management cycle), the threads manager155can stop storing additional requests in request registers452so that the contents of request registers452is static. Any new requests are not considered during this cycle, but are saved and can be considered in a subsequent power management cycle. The threads manager155can generate multiple current level signals, such as a full signal462, a middle signal464, a low signal466, and a high-to-low signal468where each current level signal corresponds to the current associated with a respective set of at least one of the requests in the request registers452. For example, the full signal462can represent the sum of all current requests in the request registers452, the middle signal464can represent the sum of two or more, but less than all, of the current requests in the request registers452(e.g., the first two or more requests in the request registers452), the low signal466can represent one current request from the request registers452(e.g., the first request in the request registers452), and the high-to-low signal468can represent a low current request when a high current budget has already been allocated. The high-to-low signal468can be associated with requests in the request registers452for which the PPM160will immediately allocate current, without checking against a current budget, and will track such allocation as with tracking other current allocations. By polling the processing threads between power management cycles, the threads manager155can save significant time and processing resources compared to waiting until the token is actually received.

In these embodiments, the PPM160receives the full signal462, the middle signal464, the low signal466, and the high-to-low signal468and determines whether the amount of current associated with any of these current level signals can be satisfied by an amount of current available in the memory sub-system110during the current power management cycle. Responsive to the amount of current available satisfying at least one of the current level signals, the PPM160can request that amount of current and provide an authorization signal472, e.g., an acknowledgement, to the threads manager155. The authorization signal472can indicate which of the current level signals is satisfied by the amount of available current, for example. The threads manager155can thus authorize one or more of processing threads434(0)-434(3) to perform one or more memory access operations corresponding to the request in the request registers452based on which requests were authorized by the authorization signal472.

FIG.5is a block diagram illustrating operation of the non-priority ring counter444implemented by the threads manager155of a memory die, which were discussed with reference toFIG.4according to some embodiments. In one embodiment, the non-priority ring counter444is formed in PPM160using flip-flops, or other devices, connected into a shift register, such that the output of the last flip-flop feeds into the input of the first flip-flop, to form the circular or “ring” structure. In one embodiment, the non-priority ring counter444is an n-bit counter representing 2ndifferent states, where 2nrepresents the number of different processing threads, such as processing threads434(0)-434(3) in the memory device130or130A. In some embodiments, the priority ring counter454functions similarly to the non-priority ring counter444, but the incremented value of the priority ring counter454can track subsets of prioritized processing thread as will be discussed in more detail.

As illustrated inFIG.5by way of example, the non-priority ring counter444is a 2-bit counter representing 4 different states (i.e., state0502, state1504, state2,506, and state3508. In operation, the non-priority ring counter444cycles sequentially through each of the 4 states502-508responsive to a change in the power management cycle. For example, if the non-priority ring counter444is initially set to state0402, when the PPM160receives the token, a value of the non-priority ring counter444is incremented (e.g., by 1) causing the non-priority ring counter444to shift to state1504. Similarly, the next time the PPM160receives the token, the value is again incremented causing the ring counter to shift to state2506, and so forth. When set to state3508, and the value is incremented, the non-priority ring counter444will return to state0502. As described in more detail below, each state (or value) of the non-priority ring counter444is associated with one or more processing threads, thereby allowing the threads manager155to select one or more processing threads of the memory device based on the current state of the non-priority ring counter444. Thus, a subset of the multiple processing threads sent to the PPM160changes according to the non-priority ring counter444, allowing the PPM160to handle power allocation of fewer number of threads at a time. This simplifies the control logic of the PPM160. Further, the non-priority ring counter444functions so as rotate to all the processing threads equally after passing through the four values or states of the non-priority ring counter444.

More specifically, Table 1 is an example of the data structure448of the PPM wrapper150used for power budget arbitration for multiple processing threads in the memory device130or130A. In one embodiment, the data structure448is formed in or managed by the threads manager155using a lookup table, an array, a linked list, a record, an object, other some other data structure. In one embodiment, the data structure448includes a number of entries, each corresponding to one of the states of the non-priority ring counter444. For example, for each state of the non-priority ring counter444, the data structure448can identify a leading thread, and a thread combination. The leading thread can be a single processing thread having the highest priority when the non-priority ring counter444is in the corresponding state, and the thread combination can be a set of two or more processing threads, but less than all of the processing threads, which have a higher priority than other threads not in the set, but a lower priority than the leading thread, when the non-priority ring counter444is in the corresponding state.

In some embodiments, to allocate available power budget during a power management cycle, the threads manager155can determine a current state of the non-priority ring counter444and determine, from the data structure448, a leading thread and a thread combination corresponding to the current state of the non-priority ring counter444. The threads manager155can then send requests to the PPM160, e.g., the full signal462, the middle signal464, and the low signal466based on identification of the leading thread and the thread combination. Responsive to an amount of current available in the memory sub-system during that power management cycle satisfying an amount of current associated with at least one of the leading thread or the thread combination, the PPM160can request that amount of current associated with the at least one of the leading thread or the thread combination and allocate that current budget accordingly.

By way of an additional example, Table 2 illustrates the data structure448in which a 3-bit non-priority counter444can hold up to eight states or values, and thus the data structure448can store additional combinations of possible leading threads and thread combinations. The 3-bit example of Table 2 and other Tables included below are merely exemplary for purposes of explanation, as other are envisioned, including those of 4-bit and beyond. In Table 2, the “Reg_hc_max” value corresponds to the full signal462, the “Reg_hc_middle” corresponds to the middle signal464, and the “Reg_hc_min” corresponds to the low signal466.

In this example, the full signal462can correspond to all of the multiple processing threads requesting current, e.g., a main processing thread of the local media controller135, and five additional co-processors (“coproc”) that can be associated with individual additional threads such as the threads0-thread3434(0)-434(3), although more co-processors are envisioned. Further, the middle signal464can include a subset of the multiple processing threads (e.g., a thread combination), and the low signal466can include just one of the processing threads (e.g., leading thread) of the multiple processing threads. In one embodiment, the subset of the multiple processing threads is no more than half of the multiple processing threads.

FIG.6is a flow diagram of an example method600of power budget arbitration in a memory device using a ring counter according to at least some embodiments. The method600can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method600is performed by the PPM wrapper150ofFIG.1AandFIG.4. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation605, power requests are sampled. For example, processing logic (e.g., PPM160) can sample power requests, such as current requests or peak current magnitude requests, from one or more processing threads, such as processing threads334(0)-334(3), of a memory device. In one embodiment, responsive to the PPM160receiving the token, which signals the start of a current power management cycle, PPM160alerts the threads manager155of the start of the polling window460. In response, the threads manager155sends polling requests to each of the processing threads to obtain an indication of current requested during the current power management cycle. The amount of current requested can be based on a number of memory access requests pending for each processing thread and the type of memory access requests pending for each processing thread. In one embodiment, each processing thread returns a separate response to the polling request, such that threads manager155can determine the current request of each processing thread separately. In one embodiment, another component, or a sub-component of the PPM wrapper150can issue the polling requests to and receive the current requests from the processing threads.

At operation610, an available power budget is determined. For example, the processing logic can determine an amount of current available in the memory device during the power management cycle. In one embodiment, the PPM160receives a signal, such as peak current magnitude indicator signal HC #, indicating the current utilized by each other PPM160in the multi-dice package200and subtracts that amount from a total amount of available current in the memory sub-system110or memory device130or130A. In one embodiment, the processing logic compares the total current associated with all processing threads (e.g., the sum of the individual current requests) to the amount of available current during the power management cycle to determine if the available current budget satisfies the current requests of all processing threads. If the amount of current available is equal to or greater than the amount of current associated with (e.g., demanded by) all of the processing threads, the processing logic determines that the amount of current available satisfies the amount of current associated with all of the processing threads.

At operation615, current is requested and allocated. If the processing logic determines that the amount of current available satisfies the amount of current associated with all of the processing threads, the processing logic can request the amount of current associated with all of the processing threads. For example, the PPM160can issue the request to a common current supply or other power source in the memory device130or130A or memory sub-system110. The PPM160can subsequently allocate the requested current to the processing threads, allowing all of the processing threads to complete their pending memory access operations.

If the processing logic determines that the amount of current available does not satisfy the amount of current associated with all of the processing threads, at operation620, a thread combination is examined. For example, the processing logic can identify, from a data structure, such as data structure448, a thread combination that corresponds to a current state of a ring counter, such as the non-priority ring counter444. The thread combination corresponding to each state of the non-priority ring counter444is different ensuring that different threads are serviced in different power management cycles and no threads are ignored. In one embodiment, the processing logic compares the total current associated with the identified thread combination (e.g., the sum of the individual current requests) to the amount of available current during the power management cycle to determine if the available current budget satisfies the current requests of the thread combination. If the amount of current available is equal to or greater than the amount of current associated with the thread combination, the processing logic determines that the amount of current available satisfies the amount of current associated with the thread combination.

At operation625, current is requested and allocated. If the processing logic determines that the amount of current available satisfies the amount of current associated with the thread combination, the processing logic can request the amount of current associated with the thread combination. For example, the PPM160can issue the request to a common current supply or other power source in the memory device130or130A or memory sub-system110. The PPM160can subsequently allocate the requested current to the processing threads, allowing the processing threads identified in the thread combination to complete their pending memory access operations.

If the processing logic determines that the amount of current available does not satisfy the amount of current associated with the thread combination, at operation630, a leading thread is examined. For example, the processing logic can identify, from a data structure, such as data structure448, a leading thread that corresponds to a current state of a ring counter, such as the non-priority ring counter444. The leading thread corresponding to each state of the non-priority ring counter444is different ensuring that different threads are serviced in different power management cycles and no threads are ignored. In one embodiment, the processing logic compares the requested current associated with the identified leading thread to the amount of available current during the power management cycle to determine if the available current budget satisfies the current request of the leading thread. If the amount of current available is equal to or greater than the amount of current associated with the leading thread, the processing logic determines that the amount of current available satisfies the amount of current associated with the leading thread.

At operation635, current is requested and allocated. If the processing logic determines that the amount of current available satisfies the amount of current associated with the leading thread, the processing logic can request the amount of current associated with the leading thread. For example, the PPM160can issue the request to a common current supply or other power source in the memory device130or130A or memory sub-system110. The PPM160can subsequently allocate the requested current to the leading thread, allowing the leading thread to complete its pending memory access operations.

If the processing logic determines that the amount of current available does not satisfy the amount of current associated with the leading thread, at operation640, the current requests are paused. For example, the processing logic can pause execution of the processing threads and maintain the current requests from those processing threads until a subsequent power management cycle. In the subsequent power management cycle, there can possibly be a larger amount of available current in the memory device which can be sufficient to satisfy the request associated with at least one of the processing threads.

FIG.7is a flow diagram of an example method of power budget arbitration in a memory device using a polling window according to at least some embodiments. The method700can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method700is performed by the PPM wrapper150ofFIG.1AandFIG.4. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation705, current level signals are received. For example, processing logic (e.g., PPM160) can receive one or more current level signals, such as full signal462, middle signal464, and low signal466, associated with a respective set of at least one of the requests in the request registers452. In one embodiment, the current level signals are based on requests identified during a polling window (e.g., when polling window signal460is asserted) between power management cycles. In one embodiment, during the polling window, threads manager155receives and storing current request from the processing threads, with each request including an indication of current requested. The amount of current requested can be based on a number of memory access requests pending for each processing thread and the type of memory access requests pending for each processing thread. In one embodiment, each processing thread sends one or more separate requests, such that the threads manager155can determine the current request(s) of each processing thread separately, and add the corresponding request(s) to request registers452.

At operation710, an available power budget is determined. For example, the processing logic can determine an amount of current available in the memory device during the power management cycle (i.e., once the token is received and the polling window closes). In one embodiment, the PPM160receives a signal, such as peak current magnitude indicator signal HV #, indicating the current utilized by each other PPM160in the multi-dice package200and subtracts that amount from a total amount of current in the memory sub-system110or memory device130or130A. In one embodiment, the processing logic compares the total current associated with the full signal462(e.g., the sum of all the individual current requests in request registers452) to the amount of available current during the power management cycle to determine if the available current budget satisfies the full signal462. If the amount of current available is equal to or greater than the amount of current associated with the full signal462, the processing logic determines that the amount of current available satisfies the full signal462.

At operation715, current is requested and allocated. If the processing logic determines that the amount of current available satisfies the full signal462, the processing logic can request the amount of current associated with all of the requests in request registers452. For example, the PPM160can issue the request to a common current supply or other power source in the memory device130or130A or memory sub-system110. The PPM160can subsequently allocate the requested current to the processing threads via authorization signal472, allowing all of the current requests in request registers452to be performed.

If the processing logic determines that the amount of current available does not satisfy the full signal462request, another current level signal is examined. For example, the processing logic compares the current associated with the middle signal464(e.g., the sum two or more current requests in request registers452) to the amount of available current during the power management cycle to determine if the available current budget satisfies the middle signal464. If the amount of current available is equal to or greater than the amount of current associated with the middle signal464, the processing logic determines that the amount of current available satisfies the middle signal464.

At operation725, current is requested and allocated. If the processing logic determines that the amount of current available satisfies the amount of current associated with the middle signal464, the processing logic can request the amount of current associated with the two or more requests from request registers452. For example, PPM160can issue the request to a common current supply or other power source in the memory device130or130A or memory sub-system110. The PPM160can subsequently allocate the requested current to the processing threads via authorization signal472, allowing two or more of the current requests in request registers452to be performed.

If the processing logic determines that the amount of current available does not satisfy the amount of current associated with the middle signal464, at operation730, another current level signal is examined. For example, the processing logic compares the current associated with the low signal466(e.g., one current request in request registers452) to the amount of available current during the power management cycle to determine if the available current budget satisfies the low signal466. If the amount of current available is equal to or greater than the amount of current associated with the low signal466, the processing logic determines that the amount of current available satisfies the low signal466.

At operation735, current is requested and allocated. If the processing logic determines that the amount of current available satisfies the amount of current associated with the low signal466, the processing logic can request the amount of current associated with one request from request registers452. For example, the PPM160can issue the request to a common current supply or other power source in the memory device130or130A or memory sub-system110. The PPM160can subsequently allocate the requested current to the processing threads via authorization signal472, allowing one current requests in request registers452to be performed.

If the processing logic determines that the amount of current available does not satisfy the amount of current associated with the any of the current level signals, at operation740, the current requests are paused. For example, the processing logic can pause execution of the processing threads and maintain the current requests from those processing threads until a subsequent power management cycle. In the subsequent power management cycle, there can possibly be a larger amount of available current in the memory device which can be sufficient to satisfy at least one of the requests.

FIG.8is a block diagram illustrating a combination of memory command packets802A and802B and a timing diagram804according to at least some embodiments. The memory command packet802A illustrates a format of the packet in which a prefix can be appended to the command packet, which also includes an initial command, address information to which the memory operation is directed, and a close command to indicate termination of a memory operation associated with the memory command packet802A. The memory command packet802B includes possible prefix values, such as 0x1, 0x2, or 0x3 or other such indicators to indicate a read command or program command without priority. In other memory command packets, the possible prefixes include, e.g., 0x41, 0x42, 0x43 or other such designators to indicate a read command or a program command with priority. In disclosed embodiments, an erase command is not prioritized. In these embodiments, the ready/busy signal (RB #) of the memory die, illustrated in the timing graph804, is asserted while handling of the memory operation associated with the memory command packet802A or802B, and is deasserted after completion of the memory operation.

In various embodiments, because the multiple processing threads334(0)-334(3) can asynchronously correspond to memory access operations such as a read operation or a program operation, the PPM wrapper150can be programmed to manage power so that snap reads and other such memory access operations can be prioritized, e.g., over non-prioritized memory operations such as some program operations and any erase operation. Thus, the memory sub-system controller115(or other processing device sending memory commands within the memory sub-system110) can add the prefix value, which indicates prioritization, to different memory command packets for a memory operation sent to the memory device130or130A.

In at least some embodiments, once a die, and thus an individual PPM wrapper150, receives a memory command packet such as discussed with reference toFIG.8, the threads manager155can parse the memory command packet to access the prefix value, the memory command packet associated with a targeted processing thread of the multiple processing threads334(0)-334(3). The threads manager155can further determine, from the prefix value, whether the memory command packet is prioritized. The threads manager155can further, in response to the memory command packet being prioritized, tag the targeted processing thread as being prioritized.

With additional reference toFIG.4, the threads manager155can, based on one or more of the multiple processing threads in the request registers452being prioritized, select the data structure458(from multiple data structures) that includes prioritization indicators associated with the one or more prioritized processing threads within the middle signal464, or thread combination, and the low signal468, to leading thread, requests. So long as the set of processing threads retain priority, the threads manager155can also increment the priority ring counter454, where the data structure458stores an association between the value of the priority ring counter454and a subset of the multiple processing threads334(0)-334(3), as illustrated in Tables 3-7. In these embodiments, the PPM160can then prioritize allocation of power to the one or more prioritized threads during each new power management cycle.FIGS.10A-10BandFIG.11will discuss additional processes by which to ensure that such prioritized processing threads do not starve any non-prioritized processing threads of processing power, e.g., current allocation.

In various embodiments, Tables 3-7 illustrate examples of the data structures that can be selected as the data structure458for different sets of prioritized processing threads. A prioritized processing thread is labeled with a capital “P” to indicate prioritization. Table 3 illustrates that the leading thread (“Low”) is the main processing thread and is prioritized over any other thread combination. In some cases, however, the leading thread can also be included within the thread combination (“Middle”) and thus could also be authorized along with one or more additional non-prioritized processing threads.

In one embodiment, Table 4 illustrates priority between two different processing threads, namely coproc1 and coproc4, at least one of which is the leading thread (“Min”) for each respective value of the priority ring counter454. In this embodiment, these two prioritized processing threads are also located within the thread combination (“Middle”). Assuming the priority ring counter454is incremented four times (through value 011), the PPM160can achieve uniformity in allocation of power to the prioritized processing threads. Thus, in some embodiments, the values of “100” and “101” of the priority ring counter454are not included in an incrementing cycle.

In one embodiment, Table 5 illustrates priority between three different processing threads, namely main, coproc2, and coproc5. Because the data structure458represented by Table 5 is programmed with these three prioritized threads into the middle signal464and the low signal466requests, the PPM160can allocate power to these prioritized processing threads in cases where there is insufficient power budget to allocate to all of the multiple processing threads.

In one embodiment, Table 6 illustrates priority between four different processing threads, namely main, coproc1, coproc2, and coproc5. Because the data structure458represented by Table 5 is programmed with these three prioritized threads into the middle signal464and the low signal466requests, the PPM160can allocate power to these prioritized processing threads in cases where there is insufficient power budget to allocate to all of the multiple processing threads. Further, assuming the priority ring counter454is incremented four times (through value 011), the PPM160can achieve uniformity in allocation of power to the prioritized processing threads. Thus, in some embodiments, the values of “100” and “101” of the priority ring counter454are not included in an incrementing cycle.

In one embodiment, Table 7 illustrates priority between five different processing threads, namely main, coproc1, coproc2, coproc4, and coproc5. Because the data structure458represented by Table 7 is programmed with these three prioritized threads into the middle signal464and the low signal466requests, the PPM160can allocate power to these prioritized processing threads in cases where there is insufficient power budget to allocate to all of the multiple processing threads. Further, assuming the priority ring counter454is incremented five times (through value “100”), the PPM160can achieve uniformity in allocation of power to the prioritized processing threads. Thus, in some embodiments, the value of “101” of the priority ring counter454is not included in an incrementing cycle.

Thus, it can be seen that the one or more prioritized processing threads, which relates to given counter value, includes the leading thread in the low signal466that is a main processing thread of the memory die in one embodiment. In another embodiment, the one or more prioritized processing threads includes the leading thread and one or more processing threads of a thread combination, e.g., the middle signal464within the subset of the multiple processing threads. This subset, e.g., the combination of the leading thread and the thread combination, can therefore, be understood to include all prioritized processing threads.

With additional reference toFIG.4, in at least some embodiments, the PPM160determines a total amount of current available budget for power consumption, which can be determined based on a quantized amount of current to be consumed by the multiple memory dice during the power management cycle, as discussed previously. The PPM160can further determine an amount of power demand associated with the multiple processing threads, and in response to determining that the amount of available budget satisfies the amount of power demand, allocate the amount of power demand to the plurality of processing threads.

With additional reference toFIG.4, in at least some embodiments, the PPM160allocates current to each respective prioritized processing thread of the one or more prioritized processing threads followed by allocating current to any non-prioritized processing thread of the subset of the plurality of processing threads. So, for example, in Table 4, there is at least one processing thread within the middle signal464that is not prioritized. The PPM160can further track a total amount of current allocated to the one or more prioritized processing threads and to any non-prioritized processing threads and, in response to an amount of current for a new current allocation exceeding the available budget less the total amount of current already allocated, pause allocation of current to any new processing thread. In this way, the PPM160ensures that, despite prioritizing allocation of power to the one or more prioritized processing threads, the overall allocated power does not exceed the available budget of current (e.g., power).

FIG.9is a graph illustrating multi-plane, prioritized power budget arbitration for multiple concurrent memory access operations according to at least some embodiments. A series of concurrent memory operations902are illustrated along a top of the graph, including a non-prioritized operation (“pgr0”), a program operation for this example, followed by a series of additional asynchronous program operations (e.g., iWL commands “pgr3,” “pgr4,” and “pgr5”), which are prioritized. When the PPM160receives the token (illustrated in the timing graph at bottom), the non-priority ring counter444has a value of “011” and only the non-prioritized program operation is running and is thus allocated power assuming sufficient available current budget. Each dashed indicator905is associated with the full signal462, each dashed indicator907is associated with the middle signal464, and each dashed indicator909is associated with the low signal466, which were discussed. Thus, the three prioritized processing threads (pgr3, pgr4, and pgr5) are encompassed within the middle signal464while the pgr 4 is the leading thread encompassed within the low signal466.

In response to the PPM160allocating power (e.g., current) to a prioritized processing thread (e.g., “pgr3”), the threads manager155can, before the end of the polling period associated with the polling window signal460, increment the value of the priority ring counter454, e.g., which in this example is a value of “100.” Thus, the management of power allocation has passed to prioritized allocation governed by the value of the priority ring counter454. This operation includes ensuring, during the power management cycle when the PPM160holds the token, that the amount of current for a new current allocation does not exceed an available budget less the total amount of currently already allocated by the PPM160.

In these embodiments, if the amount of current for a new current allocation, e.g., to the pgr5 prioritized processing thread, does exceed an available budget less the total amount of currently already allocated, then the PPM160pauses allocation of power (or current) to non-prioritized processing thread, pgr0. If pausing allocation to the non-prioritized processing thread does not free up enough power budget to handle the pgr5 prioritized processing thread, then the PPM160may have to further pause allocating power to any new processing threads until sufficient budget is made available. In this way, the prioritized threads are prioritized over the non-prioritized processing threads. While these operations explained with reference toFIG.9allow prioritization of processing threads indicated as prioritized within the low signal466or the middle signal464, these operations do not ensure that the non-prioritized processing thread, pgr0, is not starved of power indefinitely or for an unacceptably long time.

FIGS.10A-10Bare a graph illustrating multi-plane, prioritized power budget arbitration for multiple concurrent memory access operations according to at least some additional embodiments, which are to ensure that the non-prioritized processing thread, pgr0, discussed with referenced toFIG.9, is not starved of power.FIG.10Agenerally tracks what is illustrated with reference toFIG.9, for example, that control logic of the PPM wrapper150allocates power to the non-prioritized processing thread, pgr0, of multiple processing threads based on a value of the non-priority ring counter444.

Different thanFIG.9, however,FIG.10Aillustrates that the control logic (e.g., of the threads manager155) starts the timer478while the non-prioritized processing thread, pgr0, is running and in response to detecting allocation of the power to a prioritized processing thread, pgr3, of the one or more prioritized processing threads (pgr3, pgr4, pgr5). Further,FIG.10Balso illustrates two additional subsequent power management cycles in which the PPM160receives the token. In the third power management cycle, the timer478has not expired, and therefore, the threads manager155still increments the value of the priority ring counter454for each power management cycle, this time to a value of “101” so that the PPM160can still prioritize the one or more prioritized processing threads. More specifically, the control logic of the PPM160prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the multiple processing threads corresponding to a value of the priority ring counter454. While the thread combination of the middle signal464sent to the PPM160still includes the three prioritized processing threads pgr3, pgr4, and pgr5, the leading thread of the low signal466has shifted to the pgr5 prioritized processing thread.

With continued reference toFIG.10B, and in at least some embodiments, in response to the timer478expiring before completion of the non-prioritized processing thread, pgr0, the threads manager155transitions power allocation between subsets of the multiple processing threads based on increments to the value of the non-priority ring counter454. In these embodiments, these subsets of the multiple processing threads can be those associated with the full signal462, the middle signal464, and the low signal466of Table 2 andFIGS.6-7, in which the individual processing threads are not tagged or identified as being prioritized. This means that the non-prioritized processing threads will get equal power sharing, depending on the state or value of the non-priority processing counter444. This transition is illustrated during the fourth power management cycle in which the leading thread (indicator909) is now the pgr0 processing thread and the thread combination (indicator907) includes the pgr0 processing thread. Thus, the PPM160will allocate available power budget to the non-prioritized processing thread, pgr0, during this fourth power management cycle, avoiding starving the pgr0 processing thread of power.

In some embodiments, although not specifically illustrated, upon detecting completion of the previously non-prioritized processing thread, pgr0, control logic of the threads manager155resets the timer478. In other embodiments, the threads manager155resets the time in response to completion of all previously non-prioritized processing threads. Then, again, while the timer is running, the threads manager increments the priority ring counter454before each power management cycle so that the PPM160can prioritize allocation of the power to the one or more prioritized processing threads located within the subset of the multiple processing threads corresponding to the value of the priority ring counter454, e.g., as illustrated in Tables 3-7. In this way, the control logic of the PPM wrapper150can transition back to prioritized power management until a situation occurs in which the PPM160allocates power to at least one non-prioritized processing thread and at least one prioritized processing threads. In response to such a situation, the threads manager155can again start the timer478as illustrated inFIG.10A.

FIG.11is a flow diagram of an example method of prioritized power budget arbitration for multiple concurrent processing threads according to at least some embodiments. The method1100can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method1100is performed by the PPM wrapper150ofFIG.1AandFIG.4. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation1110, a non-prioritized processing threads is allocated power. More specifically, the processing logic allocates power to a non-prioritized processing thread of multiple processing threads based on a value of a non-priority ring counter, the multiple processing threads to execute memory access operations on the memory array370(FIG.3). The non-priority ring counter can be the non-priority ring counter44ofFIG.4.

At operation1120, allocation of power to a prioritized processing thread is detected More specifically, the processing logic determines whether allocation of the power to a prioritized processing thread has been detected. This creates the situation just discussed in which at least one non-prioritized processing thread and at least one prioritized processing thread has been allocated power and are running concurrently.

At operation1130, at timer is started. More specifically, in response to an affirmative detection of allocation of power to the prioritized processing thread, the control logic starts a timer, such as the timer478(FIG.4).

At operation1140, a priority ring counter is incremented. More specifically, while the timer is running, the processing logic increments a priority ring counter before each power management cycle. The priority ring counter can be the priority ring counter454ofFIG.4.

At operation1150, prioritized processing threads are prioritized. More specifically, while the timer is running, the processing logic prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the multiple processing threads corresponding to a value of the priority ring counter.

At operation1160, timer expiration is checked. More specifically, the processing logic, determine whether the timer expires before completion of the non-prioritized processing thread. If the answer is no, at operation1160, then the method1100cycles back to operations1140and1150and continues with prioritized power management, as was done at power management cycle three with reference toFIGS.10A-10B.

At operation1160, power management transitions back to non-prioritized management. More specifically, in response to the timer expiring before completion of the non-prioritized processing thread, the processing logic transitions power allocation between subsets of the multiple processing threads based on increments to the value of the non-priority ring counter.

The example computer system1200includes a processing device1202, a main memory1204(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory1206(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system1218, which communicate with each other via a bus1230.

Processing device1202represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device1202can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device1202is configured to execute instructions1226for performing the operations and steps discussed herein. The computer system1200can further include a network interface device1208to communicate over the network1220.

The data storage system1218can include a machine-readable storage medium1224(also known as a computer-readable medium, such as a non-transitory computer-readable medium) on which is stored one or more sets of instructions1226or software embodying any one or more of the methodologies or functions described herein. The instructions1226can also reside, completely or at least partially, within the main memory1204and/or within the processing device1202during execution thereof by the computer system1200, the main memory1204and the processing device1202also constituting machine-readable storage media. The machine-readable storage medium1224, data storage system1218, and/or main memory1204can correspond to the memory sub-system110ofFIG.1A.