Semiconductor package with TSV inductor

A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

BACKGROUND

The present disclosure relates generally to the field of semiconductor technology. More particularly, the present disclosure relates to an improved semiconductor package with high-performance through-silicon via (TSV) inductor.

The implementation of on-chip inductors in integrated circuit application remains a challenge to satisfy the requirements of high quality factor (Q factor), small area consumption, limited parasitic coupling, ease of layout, and manufacture.

Conventionally, additional metal layers of an interconnection structure of a chip or a die are used in the flip chip package fabrication process to improve the Q factor. However, the additional metal layers increase on-die area and fabrication costs, and negatively affect fabrication throughput.

SUMMARY

It is one object of the invention to provide an improved semiconductor package to solve the above-mentioned deficiencies or shortcomings.

According to one aspect of the invention, a semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

According to some embodiments, the first die is electrically connected to the second die through a conductive pad on the upper surface of the first die and a micro bump.

According to some embodiments, the micro bump extends between a bonding pad of the second die and the conductive pad of the first die.

According to some embodiments, the second die and the upper surface of the first die are encapsulated by a first molding compound.

According to some embodiments, a gap between the second die and the first die is filled with the first molding compound.

According to some embodiments, the first die comprises a die substrate, and wherein the TSVs penetrate through the die substrate.

According to some embodiments, the die substrate comprises a silicon substrate, a silicon-on-insulator substrate, or a silicon germanium substrate.

According to some embodiments, a back-end of line (BEOL) structure is disposed on the die substrate.

According to some embodiments, a back-end of line (BEOL) structure is disposed on the die substrate, and wherein the BEOL structure comprises at least one ultra-low dielectric constant (ultra-low k) layer on the die substrate.

According to some embodiments, the BEOL structure further comprises at least one inter-layer dielectric (ILD) layer on the ultra-low k layer.

According to some embodiments, the ILD layer comprises an un-doped silicate glass layer.

According to some embodiments, at least one metal interconnect layer is formed in the ILD layer, and wherein the metal interconnect layer has a thickness less than 3.0 micrometers.

According to some embodiments, the TSVs penetrate through the die substrate and at least the ultra-low k layer, and wherein the TSVs are electrically connected to the metal interconnect layer in ILD layer.

According to some embodiments, the TSVs are connected to connecting pads of the interposer layer.

According to some embodiments, the connecting pads are connected to an inductor formed from a metal trace in the interposer layer, and wherein the metal trace has a thickness that is equal to or greater than 3.0 micrometers.

According to some embodiments, the inductor is disposed in a horizontal level of the interposer layer under the lower surface of the first die.

According to some embodiments, the inductor is disposed directly under the first die.

According to some embodiments, the first die, the first molding compound, and an upper surface of the interposer layer are encapsulated by a second molding compound.

According to some embodiments, the semiconductor package further comprises: a re-distribution layer on the second molding compound and the second die; a semiconductor package may be mounted on the re-distribution layer; and a plurality of through molding vias in the second molding compound. The semiconductor package is electrically coupled to the interposer layer through the through molding vias.

According to some embodiments, the semiconductor package comprises a DRAM package.

DETAILED DESCRIPTION

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, structural, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.

It will be understood that, although the terms first, second, third, primary, secondary, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first or primary element, component, region, layer or section discussed below could be termed a second or secondary element, component, region, layer or section without departing from the teachings of the present inventive concept.

It is noted that: (i) same features throughout the drawing figures will be denoted by the same reference label and are not necessarily described in detail in every drawing that they appear in, and (ii) a sequence of drawings may show different aspects of a single item, each aspect associated with various reference labels that may appear throughout the sequence, or may appear only in selected drawings of the sequence.

The present invention pertains to a stacked die package comprising a first die and a second die stacked on the first die. The proposed inductor is designed to be placed at the backside of the first die in a fan-out interposer layer for efficiently utilizing the silicon area and can be connected to the front side circuits of the lower die through TSVs.

Please refer toFIG.1.FIG.1is a schematic, cross-sectional diagram showing a stacked die package1according to one embodiment of the invention. As shown inFIG.1, the stacked die package1comprises a first die10and a second die20stacked on the first die10. According to one embodiment, the first die10and the second die20are performed as different functions and manufactured by different process node technology, for example, the first die10may be a modem die manufactured by 5 nm process and the second die20may be a processor die manufactured by 3 nm process, but not limited thereto. As can be seen in the circle region on the right showing an enlarged view of a portion of the stacked die package1, the first die10has an upper surface S1and a lower surface S2opposite to the upper surface S1. The second die20is mounted on the upper surface S1.

The first die10may be electrically connected to the second die20through a conductive pad AP on the upper surface S1of the first die10and a micro bump BP. The micro bump BP extends between a bonding pad201of the second die20and the conductive pad AP of the first die10. According to some embodiments, a solder layer SP may be further provided between the bonding pad201and the conductive pad AP, but is not limited thereto. In some embodiment, the conductive pad AP may be made of aluminum, but is not limited thereto. A gap G between the second die20and the first die10may be filled with a sealant or a molding compound MC1, but is not limited thereto.

The first die10includes a die substrate100. The die substrate100may be a semiconductor substrate, for example, a silicon substrate. It is to be understood that other types of semiconductor substrates may be used. For example, in some embodiments, the die substrate100may be a silicon-on-insulator, silicon germanium or other types of semiconductor substrates. Circuit components102may be formed on or in the die substrate100. For example, the circuit components102may include a transistor having a gate and source/drain regions.

A back-end of line (BEOL) structure BL is disposed on the die substrate100. According to one embodiment, for example, the BEOL structure BL comprises at least one ultra-low dielectric constant (ultra-low k) layer110formed on the die substrate100. According to one embodiment, for example, the ultra-low k layer110may have a dielectric constant that is smaller than 2.6, for example, 2.55, but is not limited thereto. The BEOL structure BL may further comprise at least one inter-layer dielectric (ILD) layer120such as an un-doped silicate glass (USG) layer formed on the ultra-low k layer110. According to one embodiment, for example, the ILD layer120may have a dielectric constant that is about 3.3, but is not limited thereto. At least one metal interconnect layer121may be formed in the ILD layer120. For example, the metal interconnect layer121may have a thickness of about 2.8 micrometers. For example, the metal interconnect layer121may have a thickness less than 2.8 micrometers. For example, the metal interconnect layer121may have a thickness of less than 3.0 micrometers. The conductive pad AP may be formed on the ILD layer120. A passivation layer130such as a silicon nitride layer may be formed on the ILD layer120. An opening APO may be provided in the passivation layer130to partially expose the conductive pad AP. The micro bump BP may be formed on the conductive pad AP through the opening APO.

According to one embodiment, the first die10further comprises a plurality of through silicon vias (TSVs)150. The TSVs150penetrate through the die substrate100and at least the ultra-low k layer110. The TSV150may be electrically connected to the metal interconnect layer121in ILD layer120. The other end of each of the TSV150may be connected to a connecting pad350of a fan-out interposer layer (or a re-distribution layer)30disposed on the lower surface S2of the first die10. According to one embodiment, the connecting pad350may be further connected to an inductor360formed from a metal trace ML in the fan-out interposer layer30. For example, the inductor360is disposed in a horizontal level of the fan-out interposer layer30under the lower surface S2of the first die10. The dielectric layer310of the fan-out interposer layer30separates the inductor360from the die substrate100. In some embodiments, the dielectric layer310is made of polymer material.

FIG.2shows a top view of an exemplary inductor. The inductor360, for example, includes metal trace ML forming first and second concentric loops. According to one embodiment, the metal trace ML has a thickness that is equal to or greater than 3.0 micrometers. The loops include the geometric shape of an inductor circuit. The loops which including at least one outer segment361and at least one inner segment362are separated by an inter-loop spacing363. The inductor360includes first and second terminals365and366. The first and second terminals365and366of the inductor360are coupled to first ends E1of the outer segment361. The second end E2of the outer segment361is coupled to second end E2of the inner segment362via a cross-over coupling367. The cross-over coupling367, for example, is provided on a second plane horizontal level of the fan-out interposer layer30, which is different than first horizontal level where the loops of the inductor360are formed. The first and second terminals365and366are directly connected to the corresponding TSVs150.

The inductor360, as described above, is for purpose of illustration and should not be limited thereto. The inductor360may include other suitable types of configurations. For example, the inductor360may be formed on multiple metal levels.

As shown inFIG.1, the fan-out interposer layer (or re-distribution layer)30may be used to fan out the terminals of the first die10on the second surface S2from a tighter pitch to a looser pitch. On the lower surface S3of the fan-out interposer layer30, a plurality of solder balls SB may be provided for further connection. The first die10and the second die20may be encapsulated by a molding compound MC2. The first die10, the molding compound MC1, and an upper surface of the fan-out interposer layer30are encapsulated by the molding compound MC2. The bottom surface of the molding compound MC2may be approximately flush with the lower surface S2of the first die10. The fan-out interposer layer30is disposed on the bottom surface of the molding compound MC2and on the lower surface S2of the first die10. The lower ends of the TSVs150of the first die10are electrically connected to the metal layers of the fan-out interposer layer30. Preferably, the inductor360is disposed directly under the first die10as to develop a shorter electrical path between the inductor360and the first die10and will provide a better chip performance. It is to be understood that the inductor360may be partially overlapped with the first die10in some embodiments so as to achieve a shorter electrical path between the first die10and the inductor360.

Please refer toFIG.3.FIG.3is a schematic, cross-sectional diagram showing a stacked die package2according to another embodiment of the invention, wherein like elements, regions or layers are designated by like numeral numbers or labels. Likewise, as shown inFIG.3, the stacked die package2comprises a first die10and a second die20stacked on the first die10. The first die10may be electrically connected to the second die20through micro bumps BP. The inductor360is disposed in the fan-out interposer layer30under the first die10. The terminals of the inductor360are directly coupled to the corresponding TSVs150that penetrate through the first die10. The stacked die package2further comprises a re-distribution layer50on the molding compound MC2and the second die20. A semiconductor package40such as a memory package or DRAM package may be mounted on the re-distribution layer50. The semiconductor package40may be electrically coupled to the fan-out interposer layer30through the through molding vias (TMVs)450.