IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME

An image sensor includes photoelectric conversion device regions in a substrate; and an isolation structure extending in a direction from a first surface of the substrate to a second surface opposing the first surface, surrounding the photoelectric conversion device regions in a plan view, and having first regions adjacent to side surfaces of the photoelectric conversion device regions and second regions adjacent to each corner of the photoelectric conversion device regions. The isolation structure includes first isolation layers surrounding the photoelectric conversion device regions, respectively, second isolation layers surrounding the first isolation layers, first gap-fill patterns filling at least a portion of a space between the second isolation layers in the first regions, and second gap-fill patterns filling at least a portion of a space between the second isolation layers in the second regions, in the plan view.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit of priority to Korean Patent Application No. 10-2021-0167056 filed on Nov. 29, 2021 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Example embodiments of the present inventive concepts relate to image sensors and methods of manufacturing the same.

An image sensor capturing an image and converting the image into an electrical signal has been used in consumer electronic devices such as a digital camera, a mobile phone camera and a portable camcorder, and also in cameras mounted on automobiles, security devices, and robots. Since there has been demand for miniaturization and high resolution of such an image sensor, various studies have been conducted to meet the demand therefor.

SUMMARY

Some example embodiments of the present inventive concepts provide an image sensor in which dark current properties may be addressed and which may have improved optical property efficiency and improved sensitivity, and/or methods of manufacturing the same.

According to some example embodiments of the present inventive concepts, an image sensor may include a first chip structure including a first substrate and first circuit devices on the first substrate; and a second chip structure on the first chip structure. The second chip structure may include a second substrate having a first surface facing the first chip structure and a second surface opposing the first surface; second circuit devices on the first surface of the second substrate; anti-reflective layers on the second surface of the second substrate; color filters on the anti-reflective layers; microlenses on the color filters; an isolation structure in the second substrate; and photoelectric conversion device regions spaced apart from each other by the isolation structure in the second substrate. The isolation structure may have first regions adjacent to side surfaces of the photoelectric conversion device regions and second regions adjacent to each corner of the photoelectric conversion device regions. The isolation structure may include first isolation layers surrounding the photoelectric conversion device regions, respectively, second isolation layers surrounding the first isolation layers, first gap-fill patterns filling at least a portion of a space between the second isolation layers in the first regions, and second gap-fill patterns filling at least a portion of a space between the second isolation layers in the second regions, in a plan view, and wherein the second gap-fill patterns are in contact with the first gap-fill patterns, in the plan view.

According to some example embodiments of the present inventive concepts, an image sensor may include photoelectric conversion device regions in a substrate; and an isolation structure extending in a direction from a first surface of the substrate to a second surface opposing the first surface, surrounding the photoelectric conversion device regions in a plan view, and having first regions adjacent to side surfaces of the photoelectric conversion device regions and second regions adjacent to each corner of the photoelectric conversion device regions, wherein the isolation structure includes first isolation layers surrounding the photoelectric conversion device regions, respectively, second isolation layers surrounding the first isolation layers, first gap-fill patterns filling at least a portion of a space between the second isolation layers in the first regions, and second gap-fill patterns filling at least a portion of a space between the second isolation layers in the second regions, in the plan view.

According to some example embodiments of the present inventive concepts, an image sensor may include a photoelectric conversion device region in a substrate; and an isolation structure extending in a direction from a first surface of the substrate to a second surface opposing the first surface, and surrounding the photoelectric conversion device region, wherein the isolation structure includes a first isolation layer surrounding the photoelectric conversion device region, a second isolation layer surrounding the first isolation layer, first gap-fill patterns in contact with the second isolation layer, and second gap-fill patterns in contact with the second isolation layer in a region adjacent to each corner of the photoelectric conversion device region, in a plan view, and wherein the second gap-fill patterns are spaced apart from each other by the first gap-fill patterns.

According to some example embodiments of the present inventive concepts, a method of manufacturing an image sensor includes forming an isolation trench having line regions and cross regions based on etching a substrate; forming a first isolation layer in the isolation trench; forming a second isolation layer on the first isolation layer in the isolation trench; forming a first gap-fill material layer on the second isolation layer, where the first gap-fill material layer fills the isolation trench in the line regions, and the first gap-fill material layer partially fills the isolation trench in the cross regions; forming first gap-fill patterns in the line regions based on etching the first gap-fill material layer and exposing the second isolation layer in the cross regions; forming a second gap-fill material layer filling the isolation trench in the cross regions and in contact with the second isolation layer; forming second gap-fill patterns in the cross regions by etching the second gap-fill material layer; and forming a capping layer on the first gap-fill patterns and the second gap-fill patterns.

According to some example embodiments of the present inventive concepts, a method of manufacturing an image sensor forming a first structure including a first substrate, a first circuit device on the first substrate, a first wiring structure on the first circuit device, and a first insulating layer covering the first wiring structure; forming a second structure including a second substrate, photoelectric conversion device regions in the second substrate, an isolation structure extending in a direction from a first surface of the second substrate to a second surface opposing the first surface, a second circuit device on a first surface of the second substrate, a second wiring structure, and a second insulating layer covering the second wiring structure; and bonding the first structure to the second structure such that the first insulating layer are in direct contact with to the second insulating layer, wherein the forming the isolation structure includes forming an isolation trench having line regions and cross regions and semiconductor patterns spaced apart from each other by the isolation trench by etching the second substrate; forming a plurality of layers within the isolation trench; forming first gap-fill patterns filling the isolation trench in the line regions; and forming second gap-fill patterns filling the isolation trench and in contact with the first gap-fill patterns in the cross regions.

DETAILED DESCRIPTION

Hereinafter, some example embodiments of the present inventive concepts will be described as follows with reference to the accompanying drawings.

Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are “substantially perpendicular” with regard to other elements and/or properties thereof will be understood to be “perpendicular” with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from “perpendicular,” or the like with regard to the other elements and/or properties thereof that is equal to or less than 10% (e.g., a. tolerance of ±10%).

Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are “substantially parallel” with regard to other elements and/or properties thereof will be understood to be “parallel” with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from “parallel,” or the like with regard to the other elements and/or properties thereof that is equal to or less than 10% (e.g., a. tolerance of ±10%).

Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are “substantially coplanar” with regard to other elements and/or properties thereof will be understood to be “coplanar” with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from “coplanar,” or the like with regard to the other elements and/or properties thereof that is equal to or less than 10% (e.g., a. tolerance of ±10%).

While the term “same,” “equal” or “identical” may be used in description of some example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±10%).

As described herein, when an operation is described to be performed “by” performing additional operations, it will be understood that the operation may be performed “based on” the additional operations, which may include performing said additional operations alone or in combination with other further additional operations.

Elements that are described herein to be in “contact” with one or more other elements or with each other may be interchangeably referred to as being in “direct contact” with the one or more other elements or with each other. Elements that are described herein to be spaced apart from each other may be interchangeably referred to as being “isolated from direct contact with each other.”

FIG.1Ais a diagram illustrating an image sensor, an enlarged diagram illustrating a portion of an image sensor, according to some example embodiments.

FIG.1Bis an enlarged diagram illustrating a region of an image sensor including an isolation structure, illustrating region “A” of the image sensor inFIG.1A, according to some example embodiments.

FIGS.2A and2Bare cross-sectional diagrams illustrating an image sensor according to some example embodiments.FIG.2Ais a cross-sectional diagram illustrating an image sensor taken along line I-I′ inFIG.1A.FIG.2Bis a cross-sectional diagram illustrating an image sensor taken along line II-II' inFIG.1A.

FIG.2Cis an enlarged diagram illustrating a region of an image sensor including an isolation structure according to some example embodiments.FIG.2Cillustrates region “B1” inFIG.2Aand region “B2” inFIG.2B.

Referring toFIGS.1A to2B, an image sensor1000in some example embodiments may include a first chip structure100and a second chip structure200. The second chip structure200may be disposed on the first chip structure100. The first chip structure100may be configured as a logic chip, and the second chip structure200may be configured as an image sensor chip including a plurality of pixel regions PX. In some example embodiments, the first chip structure100may be configured as a stack chip structure including a logic chip and a memory chip.

The first chip structure100may include a first substrate101, a first device isolation layer110defining an active region on the first substrate101, a first circuit device120on the first substrate101, and a first wiring structure130and a first insulating layer140on the first circuit device120.

The first substrate101may include a semiconductor material, such as, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first circuit device120may include a device such as a transistor including a gate122and a source/drain124. The first insulating layer140may cover the first circuit device120and the first wiring structure130on the first substrate101, and may include a plurality of insulating layers. For example, the first insulating layer140may be configured as multiple layers including at least two of a silicon oxide layer, a low dielectric layer, or a silicon nitride layer.

The second chip structure200may include a second substrate201having a first surface201S1and a second surface201S2opposing each other, a second device isolation layer210disposed on the first surface201S1of the second substrate201and defining an active region, a second circuit device220, a second wiring structure230, and a second insulating layer240disposed between the first surface201S1of the second substrate201and the first chip structure100, photoelectric conversion device regions PD in the second substrate201, an isolation structure IS penetrating the second substrate201and surrounding the photoelectric conversion device regions PD, an insulating structure270disposed on the second surface201S2of the second substrate201, color filters280on the insulating structure270, and microlenses290on the color filters280.

The second substrate201may include a semiconductor material, such as, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the second substrate201may be configured as a single crystal silicon substrate.

The second device isolation layer210may be formed by, for example, a shallow trench isolation (STI) process. The second device isolation layer210may partially extend from the first surface201S1of the second substrate201into the second substrate201. The second device isolation layer210may be formed of an insulating material, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

The second circuit device220may include a transfer gate TG, a floating diffusion region FD, and circuit transistors221. The circuit transistor221may include a gate222and a source/drain224. The transfer gate TG may transfer electric charges from an adjacent photoelectric conversion device region PD to an adjacent floating diffusion region FD. The circuit transistor221may be configured as at least one of a source follower transistor, a reset transistor, or a select transistor. The transfer gate TG may be configured as a vertical transfer gate including a portion extending from the first surface201S1of the second substrate201into the second substrate201.

The second wiring structure230may include multiple wirings disposed in layers on different levels and vias electrically connecting the multiple wirings and electrically connecting the multiple wirings to the second circuit device220.

The second insulating layer240may cover the second circuit device220and the second wiring structure230below the first surface201S1of the second substrate201, and may include a plurality of insulating layers. For example, the second insulating layer240may be formed as multiple layers including at least two of a silicon oxide layer, a low dielectric layer, or a silicon nitride layer. The second insulating layer240may be in contact with and bonded to the first insulating layer140.

The photoelectric conversion device regions PD may be formed in the second substrate201and may be spaced apart from each other by the isolation structure IS. The pixel regions PX may be defined as regions including the photoelectric conversion device regions PD. For example, each of the pixel regions PX may include a photoelectric conversion device region PD. The photoelectric conversion device region PD may generate and accumulate electric charges corresponding to incident light. For example, the photoelectric conversion device region PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or any combination thereof.

The isolation structure IS may be disposed to surround the pixel regions PX including each of the photoelectric conversion device regions PD. The isolation structure IS may be disposed in the isolation trench DT penetrating through the second substrate201. The isolation structure IS may be formed in a direction from the first surface201S1of the second substrate201to the second surface201S2opposing the first surface201S1. For example, at least a portion of the isolation structure IS may penetrate the second substrate201. In another example, the isolation structure IS may be disposed to partially penetrate the second substrate201rather than completely penetrating the second substrate201. The isolation structure IS may be connected to a portion of the second device isolation layer210. For example, the isolation structure IS may penetrate the second device isolation layer210.

As illustrated inFIGS.1A and1B, the isolation structure IS may include first regions LR adjacent to side surfaces S of the photoelectric conversion device regions PD and second regions CR adjacent to each corner C of the photoelectric conversion device regions PD. The second regions CR may be intersecting regions of a grid pattern of the isolation structure IS in a plan view, and may include, for example, regions in which patterns extending in the X-direction intersect with patterns extending in the Y-direction.

In a plan view, the isolation structure IS may include first isolation layers251and second isolation layers252surrounding the photoelectric conversion device regions PD, respectively. The first isolation layers251may surround the photoelectric conversion device regions PD, respectively, and the second isolation layers252may surround the first isolation layers251, respectively. The first isolation layers251and the second isolation layers252may extend from the first regions LR to the second regions CR, and may include a rounded portion surrounding each corner of the photoelectric conversion device regions PD in the second regions CR.

The isolation structure IS may further include first gap-fill patterns261filling at least a portion of a space between the second isolation layers252in the first regions LR and second gap-fill patterns262filling at least a portion of a space between the second isolation layers252in the second regions CR. The second gap-fill patterns262may be in contact with the first gap-fill patterns261. The second gap-fill patterns262may be disposed adjacent to each corner of the plurality of photoelectric conversion device regions PD, and may be spaced apart from each other by the first gap-fill patterns261. The first gap-fill patterns261may be disposed between adjacent photoelectric conversion device regions PD in a first direction (X-direction or Y-direction) in a plan view, and the second gap-fill patterns262may be disposed between the photoelectric conversion device regions PD adjacent to each other in a second direction (W1direction or W2direction) oblique to the first direction and parallel to the second surface201S2of the second substrate201in a plan view. The first gap-fill patterns261may have a first minimum width W1in the first direction (X-direction or Y-direction), the second gap-fill patterns262may have a second minimum width W2in the second direction (W1direction or W2direction), and the first minimum width W1may be smaller than the second minimum width W2. For example, the second minimum width W2may be about 1.3 times to about 4 times, or about 1.8 times to about 2.2 times the first minimum width W1. The first gap-fill pattern261may include a first portion having a first minimum width W1and a second portion having a width W1e greater than the first minimum width W1, and the second gap-fill pattern262may include a first portion having a second minimum width W2and a width W2e greater than the second minimum width W2.

The second gap-fill patterns262may have a cross shape in a plan view. Side surfaces of the second gap-fill patterns262in contact with the first gap-fill patterns261may be curved surfaces, curved toward the first gap-fill patterns261. Surfaces of a first element that are herein described to be curved “toward” another element may be “convex” surfaces of the first element. The second gap-fill patterns262may include a concave region CS facing a portion of each corner C of the photoelectric conversion device region PD in a plan view. The concave region CS may be in contact with the second isolation layer252.

The isolation structure IS may include liner layers253disposed between the first isolation layers251and the second isolation layers252and a capping layer268covering first gap-fill patterns261and second gap-fill patterns262between the first isolation layers251. The liner layers253may surround the first isolation layers251in a plan view, respectively. The liner layers253may be formed of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The first isolation layers251may extend longer toward the first surface201S1of the second substrate201than the second isolation layers252and the liner layers253, and may be in contact with the capping layer268. The capping layer268may be formed of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

For example, the second gap-fill patterns262may include a material different from a material of the first gap-fill patterns261, and may include the same material as a material of the second isolation layers252. For example, the first isolation layers251may include a material different from a material of the second isolation layers252. The liner layers253may include a material different from a material of the first isolation layers251and the second isolation layers252. The first isolation layer251may be formed of an insulating material, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The second isolation layer252may include a semiconductor material, such as, for example, polysilicon doped with n-type or p-type impurities or undoped polysilicon. The first gap-fill pattern261may be formed of an insulating material, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The second gap-fill pattern262may include a semiconductor material, such as, for example, polysilicon doped with n-type or p-type impurities or undoped polysilicon. N-type impurities may include at least one of phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb), and p-type impurities may include at least one of boron (B), indium (In), or gallium (Ga).

Differently from the above example, each of the first and second isolation layers251and252and the first and second gap-fill patterns261and262forming the isolation structure IS may include a conductive material, such as, for example, at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium (Ti), tungsten (W), aluminum (Al), or copper (Cu).

Each of the first isolation layer251, the second isolation layer252, the liner layer253, the first gap-fill pattern261, and the second gap-fill pattern262may be exaggerated in the diagrams to indicate the structure of the isolation structure IS of the image sensor1000, and each component may have a thickness relatively reduced as compared to the illustrated example. The second isolation layer252may have a thickness greater than that of the first isolation layer251, but some example embodiments thereof is not limited thereto, and thicknesses of the components included in the isolation structure IS may be the same or different.

In some example embodiments, a negative voltage may be applied to the second gap-fill pattern262. A negative voltage may be applied to the second isolation layer252in contact with the second gap-fill pattern262through the second gap-fill pattern262. Positive charges generated by the photoelectric conversion device region PD may be removed through the second isolation layer252surrounding the photoelectric conversion device region PD, thereby potentially reducing the dark current that may be generated in the image sensor1000and which may otherwise degrade quality of images generated based on electrical signals generated by the image sensor1000. Accordingly, dark current properties of the image sensor may improve (e.g., the image sensor1000may be configured to have reduced dark current therein, thereby the image sensor1000may have improved image generating performance due to the reduction of dark current) based on the second gap-fill pattern262being in contact with the second isolation layer252.

For example, the second gap-fill pattern262includes a polysilicon layer, and the polysilicon layer is used as a material layer gap-filling the entire internal space of the isolation trench DT between the second isolation layers252, a portion of incident light may be absorbed by the polysilicon layer instead of the photoelectric conversion device region PD, such that optical property efficiency may degrade. In some example embodiments, a first gap-fill pattern261may be formed as a gap-fill material layer in the first regions LR, and a second gap-fill pattern262may be formed as a gap-fill material layer in the second regions CR. The second gap-fill pattern262may be locally disposed to be adjacent to a corner of the photoelectric conversion device region PD (e.g., based on the second gap-fill pattern262filling at least a portion of a space between the second isolation layers in the second region CR where the second region CR is adjacent to a corner of the photoelectric conversion device region PD, such that absorption of a portion of incident light by the polysilicon layer may be reduced, and thus optical property efficiency of the image sensor1000may be improved such that performance of the image sensor1000may be improved due to reduction of such absorption, based on the second gap-fill pattern262being adjacent to the corner of the photoelectric conversion device region PD.

That is, since the second gap-fill pattern262in the second region CR is in contact with the second isolation layer252, an electrical connection path through which a negative voltage may be applied to the second isolation layer252may be provided, such that dark current properties of the image sensor may be addressed, and by locally or intermittently disposing the second gap-fill pattern262in the second region CR, the optical property efficiency and sensitivity of the image sensor may improve.

The insulating structure270may cover the second substrate201and the isolation structure IS. The insulating structure270may include an anti-reflective layer configured to allow incident light to travel to the photoelectric conversion device regions PD with high transmittance by adjusting a refractive index. The insulating structure270may include a plurality of insulating layers stacked in sequence. For example, the insulating structure270may include a first layer271, a second layer272, a third layer273, and a fourth layer274stacked in sequence. The first to fourth layers271,272,273, and274may include at least one of aluminum oxide, hafnium oxide, silicon oxynitride, silicon oxide, or silicon nitride.

The color filters280may allow light of a specific wavelength to transmit and to reach the photoelectric conversion device regions PD. For example, the color filters280may be formed of a material in which a pigment including a metal or a metal oxide is mixed with a resin. The color filters280may include a green filter, a red filter, and a blue filter. In example embodiments, the color filters280may not be provided, and the image sensor1000may include an organic photoelectric conversion film provided together with the color filters280or replacing the color filters280.

The microlenses290may overlap each of the photoelectric conversion device regions PD in the vertical direction (Z). The microlenses290may be convex in a direction away from the second substrate201to condense incident light. The microlenses290may condense incident light into the photoelectric conversion device regions PD. The microlenses290may be formed of a transparent photoresist material or a transparent thermosetting resin material. For example, the microlenses290may be formed of a TMR-based vertical (manufactured by Tokyo Ohka Kogo, Co.) or an MFR-based resin (manufactured by Japan Synthetic Rubber Corporation), but some example embodiments thereof is not limited thereto.

FIG.3is a plan diagram illustrating an image sensor according to some example embodiments.

FIGS.4A and4Bare cross-sectional diagrams illustrating an image sensor according to some example embodiments.FIG.4Aillustrates a cross-sectional diagram illustrating the image sensor inFIG.3taken along line III-III′ andFIG.4Billustrates a cross-sectional diagram illustrating the image sensor inFIG.3taken along line IV-IV′.

Referring toFIGS.3to4B, in the second chip structure200of an image sensor1000A in some example embodiments, the isolation structure IS may not include the liner layers253. The second isolation layer252may surround the first isolation layer251and may be in direct contact with the first isolation layer251. Each of the first gap-fill patterns261and the second gap-fill patterns262may include a portion in contact with the first isolation layer251.

FIGS.5A,5B,5C,5D,5E, and5Fare enlarged diagrams illustrating a region of an image sensor including an isolation structure according to some example embodiments.FIGS.5A to5Fare enlarged diagrams illustrating regions corresponding to regions “B1” and “B2” inFIG.2C, respectively.

Referring toFIG.5A, in an image sensor1000B, with reference to the first surface201S1of the second substrate201, the lower surface of the first gap-fill pattern261and the lower surface of the second gap-fill pattern262may be disposed lower than in some example embodiments, including the example embodiments shown inFIG.2C. For example, the lower surface of the first gap-fill pattern261and the lower surface of the second gap-fill pattern262may be disposed on a level lower than the level in some example embodiments, including the example embodiments shown inFIG.2C. For example, the lower surface of the first gap-fill pattern261and the lower surface of the second gap-fill pattern262may be disposed on the same level as a level of the upper surface of the second device isolation layer210in the second substrate201. However, some example embodiments thereof is not limited thereto, and the lower surface of the first gap-fill pattern261and the lower surface of the second gap-fill pattern262may be disposed on a level higher than a level of the upper surface of the second device isolation layer210in the second substrate201. Alternatively, the lower surface of the first gap-fill pattern261may be disposed on a level different from a level of the lower surface of the second gap-fill pattern262.

Referring toFIG.5B, in an image sensor1000C, with reference to the first surface201S1of the second substrate201, each of the lower surface of the first gap-fill pattern261and the lower surface of the second gap-fill pattern262may have a concave lower surface. The shape of the lower surface of the first gap-fill pattern261may be formed in the process of etching the first gap-fill pattern261, and the shape of the lower surface of the second gap-fill pattern262may be formed the process of etching the second gap-fill pattern262, and each shape may be varied in example embodiments.

Referring toFIG.5C, in an image sensor1000D, each of the lower surface of the first gap-fill pattern261and the lower surface of the second gap-fill pattern262may have a concave lower surface, and a lower surface of the second gap-fill pattern262may provide a relatively deep recess with respect to the first surface201S1of the second substrate201. The recess may extend to a region between internal side surfaces of the second isolation layers252facing each other, and an upper end thereof may be disposed on a level lower than or on the same level as a level of an upper surface of the second gap-fill pattern262.

Referring toFIG.5D, the image sensor1000E may not include the second device isolation layer210through which the isolation structure IS penetrates. The isolation structure IS may work as an isolation layer defining an active region between the second circuit devices220.

Referring toFIG.5E, in an image sensor1000F, a portion262aof the second gap-fill pattern262of the isolation structure IS may extend in a direction from the capping layer268toward an upper end of the first gap-fill pattern261in the first gap-fill pattern261in the first regions LR. In the first regions LR, when the first gap-fill material layer261′ (FIG.9B) does not completely fill the isolation trench DT such that a seam is formed therein, a recess having a predetermined depth may be formed in the first gap-fill pattern261in the process (FIG.9C) of etching the first gap-fill material layer261′. A portion262aof the second gap-fill pattern262may be formed by filling the recess with the second gap-fill material layer262′ when the second gap-fill material layer262′ (FIG.9D) is formed. The portion262aof the second gap-fill pattern262in the first regions LR may not be in contact the second isolation layer252and may have a shape of which a width decreases toward the second surface201S2of the second substrate201. For example, the portion262aof the second gap-fill pattern262may have a pointy shape toward the second surface201S2of the second substrate201.

Referring toFIG.5F, in an image sensor1000G, similarly to the image sensor inFIG.5E, a portion262a′ of the second gap-fill pattern262of the isolation structure IS may extend in a direction from the capping layer268toward an upper end of the first gap-fill pattern261in the first gap-fill pattern261in the first regions LR, and the portion262a′ of the second gap-fill pattern262may be in contact with the second isolation layer252. In some example embodiments, including the example embodiments shown inFIG.5F, the etching of the first gap-fill material layer261′ may be performed more excessively in the first regions LR than in some example embodiments, including the example embodiments shown inFIG.5E.

FIG.6is a plan diagram illustrating an image sensor according to some example embodiments.

Referring toFIG.6, the image sensor1000H may include a second chip structure200including pixel regions PX configured in a Q-cell pattern, and for example, the four photoelectric conversion device regions PD adjacent to each other may share a single microlens290, and the connection region PD_C connecting the four photoelectric conversion device regions PD adjacent to each other to each other may be disposed in a central region of the four photoelectric conversion device regions PD. Accordingly, a dynamic range of the image sensor1000F may be improved or optimized. By intermittently disposing the second gap-fill pattern262in each region adjacent to corners of the four photoelectric conversion device regions PD, optical property efficiency and sensitivity of the image sensor may improve.

FIG.7is a flowchart illustrating processes of a method of manufacturing an image sensor in order according to some example embodiments.

FIG.8is a diagram illustrating a substrate on which an isolation trench is formed in relation to a method of manufacturing an image sensor in order according to some example embodiments.

FIGS.9A,9B,9C,9D,9E,9F, and9Gare diagrams illustrating processes of a method of manufacturing an image sensor in order according to some example embodiments.FIGS.9A to9Gillustrate cross-sectional regions of the substrate taken long lines V-V′ and VI-VI′ inFIG.8.

FIGS.10A,10B,11A, and11Bare diagrams illustrating processes of a method of manufacturing an image sensor in order according to some example embodiments.

Referring toFIGS.7,8, and9A, an isolation trench DT having line regions LR and cross regions CR may be formed by etching the second substrate201(S10), and a first isolation layer251, a liner layer253, and a second isolation layer252may be formed in the isolation trench DT (S20).

A second substrate201may be prepared, a mask pattern MK may be formed on the first surface201S1of the second substrate201, an etching process may be performed on the second substrate201using the mask pattern MK, a shallow isolation trench ST may be formed, and a device isolation layer210′ may be formed in the shallow isolation trench ST. The device isolation layer210′ may completely fill the shallow isolation trench ST and may cover the mask pattern MK. The upper surface of the device isolation layer210′ may be formed on a level higher than a level of the first surface201S1of the second substrate201.

Thereafter, a mask (not illustrated) may be formed on the device isolation layer210′, and the isolation trench DT may be formed by anisotropically etching the device isolation layer220′ and the second substrate201. As illustrated inFIG.9, the isolation trench DT may be formed in the form of a grid pattern. For example, the isolation trench DT may include first line patterns extending in the X-direction and second lines extending in the Y-direction. The isolation trench DT may include line regions LR having a line shape in a plan view and cross regions CR including regions in which the first and second line patterns intersect with each other. By the isolation trench DT, as illustrated inFIG.8, semiconductor patterns201P arranged in a matrix form in the X- and Y-directions on the second substrate201and spaced apart from each other by the isolation trench DT may be formed. The first distance d1between the side surfaces S of the semiconductor patterns201P in the line regions LR may be less than a second distance d2between the corners C of the semiconductor patterns201P in the cross regions CR.

Thereafter, a first isolation layer251conformally covering an internal side surface and a bottom surface of the isolation trench DT may be formed in the isolation trench DT, a liner layer253may be formed on the first isolation layer251in the isolation trench DT, and the second isolation layer252may be formed on the liner layer253in the isolation trench DT. In example embodiments, the forming the liner layer253may not be performed, and in this case, the second isolation layer252may be formed on the first isolation layer251. The second isolation layer252may be formed on the isolation trench DT and may be recessed to a level lower than a level of the lower surface of the shallow isolation trench ST by an etching process. The upper side surface of the second isolation layer252may be inclined toward an internal wall of the isolation trench DT, but some example embodiments thereof is not limited thereto.

Referring toFIGS.7and9B, the first gap-fill material layer261′ filling the isolation trench DT in the line regions LR and partially filling the isolation trench DT in the cross regions CR′ may be formed (S30).

The first gap-fill material layer261′ may completely fill the isolation trench DT in the line regions LR and may extend to the isolation trench DT. Since the space between the semiconductor patterns201P is wider in the cross regions CR than in the line regions LR, the first gap-fill material layer261′ may partially fill the isolation trench DT in the cross regions CR. For example, the first gap-fill material layer261′ may not completely gap-fill the isolation trench DT in the cross regions CR. The first gap-fill material layer261′ may conformally cover the second isolation layer252and the liner layer253in the cross regions CR.

Referring toFIGS.7and9C, the first gap-fill patterns261may be formed in the line regions LR by etching the first gap-fill material layer261′, and the second isolation layer252may be exposed in the cross regions CR (S40).

The first gap-fill material layer261′ may be partially removed from an upper portion in the line regions LR such that an upper end thereof may be formed on a lower level than a level of the first surface201S1of the second substrate201, such as, for example, a level lower than a level of a lower end of the shallow isolation trench ST. The first gap-fill material layer261′ may be etched and may be formed as first gap-fill patterns261in the line regions LR. A portion of the first gap-fill material layer261′ covering the second isolation layer252may be removed in the cross regions CR and the second isolation layer252may be exposed.

Referring toFIGS.7and9D, a second gap-fill material layer262′ filling the isolation trench DT in the cross regions CR may be formed (S50).

The second gap-fill material layer262′ may be formed to be in contact with the second isolation layer252in the cross regions CR and to at least partially fill the isolation trench DT. The second gap-fill material layer262′ may be deposited on the first surface201S1of the second substrate201, and may partially cover the first gap-fill pattern261in the line regions LR.

Referring toFIGS.7and9E, second gap-fill patterns262may be in the cross regions CR by etching the second gap-fill material layer262′ (S60).

The second gap-fill material layer262′ may be partially removed from an upper portion in the cross regions CR such that an upper end thereof may be disposed on a level lower than the first surface201S1of the second substrate201, that is, for example, on a level lower than a level of a lower end of the shallow isolation trench ST. The second gap-fill material layer262′ may be etched and may be formed as second gap-fill patterns262in the cross regions CR. The second gap-fill patterns262may be spaced apart from each other by the first gap-fill patterns261disposed in the line regions LR and may be locally disposed only in the cross regions CR. The upper ends of the second gap-fill patterns262may be formed on substantially the same level as a level of the lower end of the shallow isolation trench ST. As the second gap-fill patterns262are formed, a portion of the second gap-fill material layer262′ covering a portion of the first gap-fill pattern261in the line regions LR may also be removed.

Referring toFIGS.7and9F, the liner layer253may be partially removed (S70).

The liner layer253exposed on the first gap-fill patterns261and the second gap-fill patterns262may be selectively removed with respect to the first gap-fill patterns261and the second gap-fill patterns262. By removing the liner layer253, the first isolation layer251on the second substrate201may be exposed. When the liner layer253is not formed in process S20, this process may not be performed.

Referring toFIGS.7and9G, a capping layer268may be formed on the first gap-fill patterns261and the second gap-fill patterns262(S80).

A capping layer268covering the first gap-fill patterns261and the second gap-fill patterns262and in contact with an internal surface of the first isolation layers251may be formed. The capping layer268may fill an upper region of the isolation trench DT. The capping layer268may be formed by depositing an insulating layer on the second substrate201and performing a planarization process. When the planarization process is performed, a portion of the device isolation layer210′ on the first surface201S1of the second substrate201may be removed such that the second device isolation layer210filling the shallow isolation trench ST may be formed. In an example, the mask pattern MK may be removed after the planarization process is performed, thereby reducing or preventing damages to the first surface201S of the second substrate201.

Thereafter, referring toFIGS.10A and10B, photoelectric conversion device regions PD may be formed by doping the semiconductor patterns201P with impurities, and a transfer gate TG, a second circuit device220including a floating diffusion region FD and circuit transistors221, a second wiring structure230, and a second insulating layer240may be formed on the first surface201S of the second substrate201. Specifically, the forming the second circuit device220may include forming the transfer gate TG and the gate222on the active region defined by the second device isolation layer210, and forming a floating diffusion region FD and a source/drain224by doping the active region with impurities. A plurality of layers forming the second insulating layer240may be formed on the first surface201S1of the second substrate201and the second wiring structure230may be formed in the second insulating layer240.

Referring toFIGS.11A and11B, a first chip structure100including a first substrate101, a first device isolation layer110, a first circuit device120, a first wiring structure130, and a first insulating layer140may be prepared, and the substrate structure inFIGS.10A and10Bmay be turned upside down and may be bonded to the first chip structure100. The first insulating layer140and the second insulating layer240may be in direct contact with and bonded to each other.

A vertical thickness of the second substrate201may be reduced by removing a portion of the second substrate201. The second substrate201may include grinding or polishing the second surface201S2′ opposing the first surface201S1, and anisotropic and isotropic etching the second surface201S2′. Accordingly, each of the first isolation layer251, the second isolation layer252, the liner layer253, the first gap-fill pattern261, and the second gap-fill pattern262may be partially removed and the surfaces thereof may be removed. Accordingly, the isolation structure IS penetrating through the second substrate201may be formed.

Referring back toFIGS.2A and2B, an insulating structure270, color filters280, and microlenses290may be formed on the second surface201S2of the second substrate201, thereby forming the second chip structure200. Accordingly, the image sensor1000including the first chip structure100and the second chip structure200on the first chip structure100may be manufactured.

FIG.12is a flowchart illustrating processes of a method of manufacturing an image sensor in order according to some example embodiments.FIG.12is a flowchart illustrating another example of a method of etching the first gap-fill material layer261′ to expose the second isolation layer252in the cross regions CR.

FIGS.13A,13B, and13Care diagrams illustrating processes of a method of manufacturing an image sensor in order according to some example embodiments.FIGS.13A to13Cillustrate cross-sectional regions of the substrate inFIG.8taken along line V-V′ and VI-VI′.

Referring toFIGS.12to13C, exposing the second isolation layer252in the cross regions CR (S40) may include forming a photoresist pattern PR covering the first gap-fill material layer261′ in the line regions LR and exposing the first gap-fill material layer261′ in the cross regions CR (S41), etching the first gap-fill material layer261′ in the cross regions CR using the photoresist pattern PR as an etch mask (S42), and removing the photoresist pattern PR (S43).

Referring toFIG.13A, a photoresist may be formed on the first gap-fill material layer261′, and a photolithography process may be performed such that the photoresist may be opened to expose the first gap-fill material layer261′ in the cross regions CR, thereby forming the photoresist pattern PR.

Thereafter, referring toFIG.13B, an etching process may be performed such that the first gap-fill material layer261′ may be removed from the cross regions CR through the open region of the photoresist pattern PR. The first gap-fill material layer261′ may not remain in the isolation trench DT in the cross regions CR. Accordingly, the second isolation layer252may be exposed.

Thereafter, referring toFIG.13C, the photoresist pattern PR may be removed by performing a stripping process and an ashing process. The other processes of the manufacturing the image sensor may be the same as the processes described with reference toFIGS.7to11B.

According to at least some of the aforementioned example embodiments, by disposing the first gap-fill patterns in the line regions of the isolation trench and disposing the second gap-fill patterns in the cross regions of the isolation trench, an image sensor having improved optical property efficiency and improved sensitivity and a method of manufacturing the same may be provided.