Light emitting device, optical device, and measurement device

A light emitting device includes a wiring board having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer, and a laser having a cathode electrode and an anode electrode, mounted on the wiring board, and driven through low-side driving. The first wiring layer includes a cathode wire connected to the cathode electrode, an anode wire connected to the anode electrode, and a first reference potential wire connected to a reference potential. The second wiring layer includes a second reference potential wire connected to the reference potential. An area of an overlap between the second reference potential wire and the anode wire is larger than an area of an overlap between the second reference potential wire and the first reference potential wire.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2020-030317 filed Feb. 26, 2020.

BACKGROUND

(i) Technical Field

The present disclosure relates to a light emitting device, an optical device, and a measurement device.

(ii) Related Art

Japanese Unexamined Patent Application Publication No. 2008-252129 describes a light emitting device including a light-transmissive ceramic substrate, a light emitting element mounted on the front face of the ceramic substrate, a wiring pattern for power supply to the light emitting element, and a metalized layer made of a metal having light reflectivity. The metalized layer is formed inside the ceramic substrate to reflect light emitted from the light emitting element.

SUMMARY

Aspects of non-limiting embodiments of the present disclosure relate to the following circumstances. Three-dimensional shapes of targets may be measured based on so-called Time of Flight (ToF) using a time of traveling light. In this case, it is appropriate to reduce a rising period of light to be emitted from a laser by reducing an inductance of a drive circuit that supplies a drive current to the laser.

Aspects of non-limiting embodiments of the present disclosure relate also to a light emitting device including a wiring board having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer, and a laser mounted on the wiring board and driven through low-side driving. In the light emitting device, it is appropriate to use more capacitive components between wires as a drive current for driving the laser compared with a case where the area of an overlap between a reference potential wire of the second wiring layer and an anode wire of the first wiring layer is smaller than the area of an overlap between the reference potential wire of the second wiring layer and a reference potential wire of the first wiring layer.

According to an aspect of the present disclosure, there is provided a light emitting device comprising a wiring board having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer, and a laser having a cathode electrode and an anode electrode, mounted on the wiring board, and driven through low-side driving. The first wiring layer comprises a cathode wire connected to the cathode electrode, an anode wire connected to the anode electrode, and a first reference potential wire connected to a reference potential. The second wiring layer comprises a second reference potential wire connected to the reference potential. An area of an overlap between the second reference potential wire and the anode wire is larger than an area of an overlap between the second reference potential wire and the first reference potential wire.

DETAILED DESCRIPTION

An exemplary embodiment of the present disclosure is described below in detail with reference to the accompanying drawings.

There is a measurement device that measures three-dimensional shapes of targets based on so-called Time of Flight (ToF) using a time of traveling light. In ToF, the three-dimensional shape of a target is determined by measuring a period from a timing when a light source of the measurement device emits light to a timing when the emitted light is reflected on the target and received by a three-dimensional sensor (hereinafter referred to as “3D sensor”) of the measurement device. The term “target” refers to an object subjected to measurement of its three-dimensional shape. The measurement of the three-dimensional shape may be referred to as “three-dimensional measurement”, “3D measurement”, or “3D sensing”.

For example, the measurement device is mounted on a portable information processing apparatus and is used for facial recognition of users who are trying to access the apparatus. Related-art portable information processing apparatuses have employed user authentication using passwords, fingerprints, or irises. In recent years, there is a demand for authentication with higher security levels. To meet the demand, measurement devices that measure three-dimensional shapes are mounted on portable information processing apparatuses. That is, a three-dimensional image of the face of a user who is trying to access the portable information processing apparatus is acquired to determine whether the user is permitted to make access. Only a user authenticated as being permitted to make access may use the portable information processing apparatus.

The measurement device is also used in augmented reality (AR) or other technologies to continuously measure three-dimensional shapes of targets.

In the measurement device that measures three-dimensional shapes based on ToF, it is appropriate to reduce a rising period of light to be emitted from a laser (hereinafter referred to as “light source”) in view of measurement accuracy. The rising period decreases along with a decrease in an inductance of a drive circuit that supplies a drive current for driving the light source. That is, as the inductance of the drive circuit increases, a drive current having a high frequency is difficult to flow. As a result, the rising period increases.

Structures, functions, methods, and other matters to be described in this exemplary embodiment below are applicable to measurement of three-dimensional shapes of targets in technologies other than facial recognition and augmented reality.

FIG. 1is a block diagram illustrating an example of the structure of a measurement device1that measures three-dimensional shapes.

The measurement device1includes an optical device3and a controller8. The controller8controls the optical device3. The controller8includes a three-dimensional shape determiner81that determines three-dimensional shapes of targets. The controller8is a computer including a CPU, a ROM, and a RAM. The ROM is a non-volatile rewritable memory such as a flash memory. Programs and constants stored in the ROM are loaded on the RAM and the CPU executes the programs to implement the three-dimensional shape determiner81. Thus, three-dimensional shapes of targets are determined.

The optical device3includes a light emitting device4and a 3D sensor5.

The light emitting device4includes a wiring board10, a light source20, a light diffusion member30, a driver50, a holder60, and capacitors70A and70B. The capacitor70A is a capacitor whose equivalent series inductance (ESL) is reduced (hereinafter referred to as “low ESL capacitor”). The capacitor70B is a capacitor having a higher ESL than the capacitor70A (hereinafter referred to as “non-low ESL capacitor”). As described later, the wiring board10has a capacitor formed from a parasitic capacitance due to the structure of the wiring board10(“capacitor70C” inFIGS. 5 and 9A to 9C). AlthoughFIG. 1illustrates a single capacitor70A and a single capacitor70B, a plurality of capacitors may be provided as either or both of the capacitors70A and70B. The light emitting device4may have circuit components such as other capacitors or resistors to operate the driver50. The capacitors70A,70B, and70C are referred to as “capacitors70” or “capacitors” unless otherwise distinguished. The capacitors (low ESL capacitor and non-low ESL capacitor) are described later. The capacitor may be referred to as “capacitive element”. The capacitors70A and70B are examples of the capacitive element. The capacitor formed from the parasitic capacitance (capacitor70C) is an example of a capacitive component.

The light source20, the driver50, the capacitors70A and70B, and the holder60are provided on the front face of the wiring board10. InFIG. 1, the 3D sensor5is not provided on the front face of the wiring board10but may be provided on the front face of the wiring board10. The light diffusion member30is provided on the holder60. The term “front face” is a near side of the drawing sheet ofFIG. 1. More specifically, a side of the wiring board10where the light source20and other components are provided is referred to as “front face”, “front side”, or “front face side”.

The light source20is a surface emitting laser element array having a plurality of surface emitting laser elements arranged in a two-dimensional matrix (seeFIG. 2). Examples of the surface emitting laser element include a vertical cavity surface emitting laser (VCSEL). The surface emitting laser element is hereinafter described as the VCSEL. Since the light source20is provided on the front face of the wiring board10, the light source20emits light outward in a direction perpendicular to the front face of the wiring board10. The light source20is an example of the laser.

The light emitted from the light source20enters the light diffusion member30and is output while being diffused by the light diffusion member30. The light diffusion member30covers the light source20. That is, the light diffusion member30keeps a predetermined distance from the light source20on the wiring board10by the holder60provided on the front face of the wiring board10. Thus, the light emitted from the light source20is diffused by the light diffusion member30and is radiated onto a target. Compared with a case where the light diffusion member30is not provided, the light emitted from the light source20is radiated in a wider range by being diffused by the light diffusion member30.

In the three-dimensional measurement based on ToF, it is appropriate that the driver50drive the light source20to emit, for example, pulsed light at a frequency of 100 MHz or higher and a rising period of 1 ns or shorter (hereinafter referred to as “emitted light pulse”). That is, the light source20is driven to emit the emitted light pulse by a drive current pulse supplied from a drive circuit that drives the light source20. In the example of facial recognition, the light radiation distance is about 10 cm to about 1 m. The light radiation range is about 1 m2. The light radiation distance is referred to as “measurement distance”. The light radiation range is referred to as “radiation range” or “measurement range”. An imaginary plane in the radiation range or the measurement range is referred to as “radiation plane”. In technologies other than facial recognition, the measurement distance to a target and the radiation range on the target may take values other than the above.

The 3D sensor5has a plurality of light receiving cells and outputs a signal corresponding to a period from a timing when the light source20emits light to a timing when the 3D sensor5receives the light. For example, each light receiving cell of the 3D sensor5receives pulsed reflected light, which is originally the emitted light pulse from the light source20and is reflected on the target (hereinafter referred to as “received light pulse”), and accumulates a charge corresponding to a period required until the light reception. The 3D sensor5is a CMOS device in which each light receiving cell has two gates and charge accumulators associated with the gates. Photoelectrons generated by alternately applying pulses to the two gates are transferred to one of the two charge accumulators at high speed. Each charge accumulator accumulates a charge corresponding to a phase difference between the emitted light pulse and the received light pulse. The 3D sensor5outputs a digital signal corresponding to the phase difference between the emitted light pulse and the received light pulse in each light receiving cell via an AD converter. That is, the 3D sensor5outputs a signal corresponding to a period from a timing when the light source20emits light to a timing when the 3D sensor5receives the light. In other words, a signal corresponding to a three-dimensional shape of the target is acquired from the 3D sensor5. Therefore, it is appropriate to reduce a rising period of the emitted light pulse and a rising period of the received light pulse. That is, it is appropriate to reduce a rising period of the drive current pulse to be supplied to drive the light source20. The AD converter may be provided inside or outside the 3D sensor5. The 3D sensor5is an example of a light receiver.

For example, if the 3D sensor5is the CMOS device, the three-dimensional shape determiner81of the controller8acquires the digital signal for each light receiving cell and calculates a distance to the target for each light receiving cell. The three-dimensional shape determiner81determines the three-dimensional shape of the target based on the calculated distance and outputs the determination result.

As described above, the controller8is the computer and the three-dimensional shape determiner81is implemented by the programs. Those components may be implemented by an integrated circuit such as an ASIC or an FPGA. Those components may also be implemented by software such as a program and an integrated circuit such as an ASIC.

As described above, the measurement device1diffuses the light emitted from the light source20and radiates the diffused light onto the target, and the 3D sensor5receives the light reflected on the target. In this manner, the measurement device1measures the three-dimensional shape of the target.

InFIG. 1, the optical device3and the controller8are provided separately but may be integrated together.

Description is first made of the light source20, the light diffusion member30, the driver50, and the capacitors (capacitors70A,70B, and70C) of the light emitting device4.

(Structure of Light Source20)

FIG. 2is a plan view of the light source20. The light source20has a plurality of VCSELs in a two-dimensional array. InFIG. 2, the VCSELs are arrayed at individual lattice points of a square lattice but may be arrayed by other methods. As described above, the light source20is the surface emitting laser element array having the VCSELs as surface emitting laser elements. In the drawing sheet, a rightward direction is an x direction and an upward direction is a y direction. A direction orthogonal counterclockwise to the x direction and the y direction is a z direction. A front face of the light source20is a face on a near side of the drawing sheet, that is, on a +z side. A back face of the light source20is a face on a far side of the drawing sheet, that is, on a −z side. The plan view of the light source20is an illustration of the light source20viewed from the front face. The “front face”, “front side”, or “front face side” of the light source20is a side of an epitaxial layer that functions as an emission layer (active region206described later).

The VCSEL is a surface emitting laser element having an active region serving as a light emitting region between a lower multilayer mirror and an upper multilayer mirror stacked on a semiconductor substrate200(seeFIG. 3) and configured to emit laser light in a direction perpendicular to the surface. For example, the light source20has 100 to 1000 VCSELs. The plurality of VCSELs are connected and driven in parallel. The number of VCSELs is an example and may be set depending on the measurement distance or the radiation range.

An anode electrode218common to the plurality of VCSELs is provided on the front face of the light source20. A cathode electrode214is provided on the back face of the light source20(seeFIG. 3). That is, the plurality of VCSELs are connected in parallel. Since the plurality of VCSELs are connected and driven in parallel, high-intensity light is emitted compared with a case where the VCSELs are driven individually.

The shape of the light source20viewed from the front face (hereinafter referred to as “plan shape”) is a rectangular shape. A lateral face on a −y side is a lateral face21A. A lateral face on a +y side is a lateral face21B. A lateral face on a −x side is a lateral face22A. A lateral face on a +x side is a lateral face22B. The lateral face21A is opposite to the lateral face21B. The lateral face22A and the lateral face22B connect the lateral face21A to the lateral face21B and are opposite to each other.

FIG. 3illustrates the sectional structure of one VCSEL of the light source20. The VCSEL is a λ-cavity VCSEL. In the drawing sheet, an upward direction is a z direction, a +z side is an upper side, and a −z side is a lower side.

In the VCSEL, an n-type lower distributed Bragg reflector (DBR)202obtained by alternately stacking AlGaAs layers having different Al compositions, the active region206having a quantum well layer sandwiched between an upper spacer layer and a lower spacer layer, and a p-type upper DBR208obtained by alternately stacking AlGaAs layers having different Al compositions are stacked in this order on the n-type GaAs semiconductor substrate200.

The n-type lower DBR202is a stack of Al0.9Ga0.1As layers and GaAs layers in pairs. The layers of the lower DBR202each have a thickness of λ/4nr(λ is an oscillation wavelength and nris a refractive index of a medium) and are alternately stacked by 40 periods. As a carrier, the lower DBR202is doped with silicon (Si), which is an n-type impurity. For example, the carrier density is 3×1018cm−3.

The active region206is a stack of the lower spacer layer, the quantum well active layer, and the upper spacer layer. For example, the lower spacer layer is an undoped Al0.6Ga0.4As layer, the quantum well active layer includes an undoped InGaAs quantum well layer and an undoped GaAs barrier layer, and the upper spacer layer is an undoped Al0.6Ga0.4As layer.

The p-type upper DBR208is a stack of p-type Al0.9Ga0.1As layers and GaAs layers in pairs. The layers of the upper DBR208each have a thickness of λ/4nrand are alternately stacked by 29 periods. As a carrier, the upper DBR208is doped with carbon (C), which is a p-type impurity. For example, the carrier density is 3×1018cm−3. A p-type GaAs contact layer is preferably formed as an uppermost layer of the upper DBR208, and a p-type AlAs current confinement layer210is preferably formed as a lowermost or internal layer of the upper DBR208.

The stacked semiconductor layers from the upper DBR208to the lower DBR202are etched to form a columnar mesa M on the semiconductor substrate200. Thus, the current confinement layer210is exposed at the lateral faces of the mesa M. Through oxidation, the current confinement layer210has an oxide region210A that is oxidized from the lateral faces of the mesa M, and a conductive region210B surrounded by the oxide region210A. In the oxidation, the AlAs layer has a higher oxidation rate than the AlGaAs layer, and the oxide region210A is oxidized at a substantially constant rate from the lateral faces of the mesa M to the inside of the mesa M. Therefore, the sectional shape of the conductive region210B is a shape that reflects the outer shape of the mesa M, that is, a circular shape, and the center of the conductive region210B substantially coincides with the axis of the mesa M indicated by the chain line. In this exemplary embodiment, the mesa M has a columnar structure.

An annular metal p-side electrode212obtained by stacking Ti/Au layers is formed as an uppermost layer of the mesa M. The p-side electrode212is in ohmic contact with the contact layer of the upper DBR208. An inner part of the annular p-side electrode212is a light exit port212A through which laser light is emitted to the outside. That is, the VCSEL emits light in the +z direction perpendicular to the front face of the semiconductor substrate200(face on the +z side). The axis of the mesa M is an optical axis. The cathode electrode214is formed on the back face of the semiconductor substrate200as an n-side electrode. The front face (face on the +z side) of the upper DBR208on the inner side of the p-side electrode212is a light emitting surface.

An insulating film216covers the surface of the mesa M except for the light exit port212A and a part where the anode electrode218is connected to the p-side electrode212. The anode electrode218is in ohmic contact with the p-side electrode212except for the light exit port212A. The anode electrode218is common to the plurality of VCSELs. That is, the p-side electrodes212of the plurality of VCSELs of the light source20are connected in parallel by the anode electrode218.

InFIG. 3, an anode symbol [A] is placed at the anode electrode218, and a cathode symbol [K] is placed at the cathode electrode214.

The VCSEL may oscillate in a single transverse mode or a multiple transverse mode. For example, the power of light from one VCSEL is 4 mW to 8 mW. If the light source20has 500 VCSELs, the power of light from the light source20is 2 W to 4 W.

(Structure of Light Diffusion Member30)

FIGS. 4A and 4Billustrate an example of the light diffusion member30.FIG. 4Ais a plan view andFIG. 4Bis a sectional view taken along the line IVB-IVB inFIG. 4A. In the drawing sheet ofFIG. 4A, a rightward direction is an x direction and an upward direction is a y direction. A direction orthogonal counterclockwise to the x direction and the y direction is a z direction. In the light diffusion member30, a +z side is referred to as “front face” or “front face side”, and a −z side is referred to as “back face” or “back face side”. In the drawing sheet ofFIG. 4B, a rightward direction is the x direction, a rearward direction is the y direction, and an upward direction is the z direction.

As illustrated inFIG. 4B, the light diffusion member30has, for example, a resin layer32having irregularities for light diffusion on the back face (−z side) of a flat glass base31having parallel faces. The light diffusion member30outputs light incident from the VCSELs of the light source20while increasing a divergence angle of the light. That is, the irregularities of the resin layer32of the light diffusion member30refract or scatter the incident light to output the light at a larger divergence angle. As illustrated inFIG. 4B, the light diffusion member30diffuses light emitted from the VCSELs at a divergence angle θ and entering the back face (−z side) of the light diffusion member30and outputs the light from the front face (+z side) at a divergence angle σ larger than the divergence angle θ (θ<σ). With the light diffusion member30, the area of the radiation plane of the light emitted from the light source20is increased compared with a case where the light diffusion member30is not used. Each of the divergence angles θ and σ is a full width at half maximum (FWHM).

The plan shape of the light diffusion member30is a rectangular shape. A thickness td (in the z direction) of the light diffusion member30is 0.1 mm to 1 mm. The plan shape of the light diffusion member30may be a polygonal shape, a circular shape, or other shapes.

To drive the light source20at a higher speed, low-side driving is appropriate. The low-side driving refers to a structure in which a drive element such as a MOS transistor is positioned on a downstream side of a driving target such as the VCSEL along a path where a current flows (hereinafter referred to as “current path”). Conversely, a structure in which the drive element is positioned on an upstream side is referred to as “high-side driving”.

FIG. 5illustrates an example of an equivalent circuit in a case where the light source20is driven through the low-side driving.FIG. 5illustrates the VCSEL of the light source20, the driver50, the capacitors70A,70B, and70C, and a power supply82. As described above, the capacitor70C is the parasitic capacitance due to the structure of the wiring board10. The capacitor70C is indicated by broken lines.FIG. 5also illustrates the controller8inFIG. 1. The power supply82is provided on the controller8. The power supply82generates a DC voltage with a power supply potential on a positive side and a reference potential on a negative side. The power supply potential is supplied to a power supply line83. The reference potential is supplied to a reference line84. The reference potential may be a ground potential (may be represented by “GND”; symbol [G] inFIG. 5).

As described above, the light source20has the plurality of VCSELs connected in parallel. The anode electrode218of the VCSEL (seeFIG. 3; symbol [A] inFIG. 5) is connected to the power supply line83.

The driver50includes an n-channel MOS transistor51and a signal generation circuit52that turns ON or OFF the MOS transistor51. A drain of the MOS transistor51(symbol [D] inFIG. 5) is connected to the cathode electrode214of the VCSEL (seeFIG. 3; symbol [K] inFIG. 5). A source of the MOS transistor51(symbol [S] inFIG. 5) is connected to the reference line84. A gate of the MOS transistor51is connected to the signal generation circuit52. That is, the VCSEL and the MOS transistor51of the driver50are connected in series between the power supply line83and the reference line84. The controller8controls the signal generation circuit52to generate an “H-level” signal for turning ON the MOS transistor51, and an “L-level” signal for turning OFF the MOS transistor51.

In each of the capacitors70A,70B, and70C, a first terminal is connected to the power supply line83(symbol [A] in the VCSEL ofFIG. 5) and a second terminal is connected to the reference line84(symbol [G] inFIG. 5).

Next, description is made of a method for driving the light source20through the low-side driving.

First, the signal generated by the signal generation circuit52of the driver50is “L-level”. In this case, the MOS transistor51is OFF. That is, no current flows between the source ([S] inFIG. 5) and the drain ([D] inFIG. 5) of the MOS transistor51. Thus, no current flows through the VCSEL connected in series to the MOS transistor51. That is, the VCSEL does not emit light.

The capacitors70A,70B, and70C are connected to the power supply82. The first terminals of the capacitors70A,70B, and70C (terminals on the [A] side in the VCSEL ofFIG. 5) connected to the power supply line83have power supply potentials. The second terminals of the capacitors70A,70B, and70C (terminals on the [G] side inFIG. 5) connected to the reference line84have reference potentials. Thus, the capacitors70A,70B, and70C are charged with flows of current from the power supply82(with supply of charges).

Next, the signal generated by the signal generation circuit52of the driver50becomes “H-level” and the MOS transistor51is switched from OFF to ON. Then, closed loops are formed between the capacitors70A,70B, and70C and the MOS transistor51and the VCSEL connected in series, and the charges accumulated in the capacitors70A,70B, and70C are supplied to the MOS transistor51and the VCSEL. That is, a current flows through the VCSEL and the VCSEL emits light. The closed loop is a drive circuit that supplies a drive current for causing the light source20to emit light. The drive current is supplied from each of the capacitors70A,70B, and70C. Therefore, the drive circuit is formed in association with each of the capacitors70A,70B, and70C. The supply of the drive current for causing the light source20to emit light may be expressed as “driving of the light source20”.

When the signal generated by the signal generation circuit52of the driver50becomes “L-level” again, the MOS transistor51is switched from ON to OFF. Therefore, the closed loops between the capacitors70A,70B, and70C and the MOS transistor51and the VCSEL connected in series become open loops, and no current flows through the VCSEL. Thus, the VCSEL stops light emission. Then, the capacitors70A,70B, and70C are charged with flows of current from the power supply82(with supply of charges).

As described above, the MOS transistor51is repeatedly turned ON and OFF and the light emission of the VCSEL is also repeatedly turned ON and OFF every time the signal output from the signal generation circuit52changes between “H-level” and “L-level”. The repetition of ON/OFF of the MOS transistor51may be referred to as “switching”.

As described above, when the MOS transistor51is switched from OFF to ON, the drive current is supplied to the VCSEL by releasing the charges in the capacitors70A,70B, and70C at a time.

The capacitors (low ESL capacitor and non-low ESL capacitor) are described.

FIGS. 6A and 6Billustrate the capacitors.FIG. 6Aillustrates an equivalent circuit of a capacitor.FIG. 6Billustrates frequency characteristics of impedances of the capacitors. InFIG. 6B, the horizontal axis represents a frequency and the vertical axis represents an impedance.

As illustrated inFIG. 6A, the capacitor is represented by an equivalent circuit in which a capacitance C, an equivalent series inductance ESL, and an equivalent series resistance ESR are connected in series.

As illustrated inFIG. 6B, if the frequency is low, the impedance is determined by the capacitance C of the capacitor. That is, the capacitor is capacitive and the impedance decreases along with the frequency. If the frequency is high, the impedance is determined by the equivalent series inductance ESL of the capacitor. That is, the capacitor is inductive and the impedance increases along with the frequency. A frequency at which the same impedance is obtained by both the capacitance C and the equivalent series inductance ESL is referred to as “resonance frequency”.

To reduce the rising period of the drive current pulse to be supplied to the light source20, it is appropriate to reduce the impedance at a high frequency, that is, reduce the equivalent series inductance ESL. That is, it is appropriate to use a capacitor configured to reduce the equivalent series inductance ESL, that is, use the low ESL capacitor to reduce the rising period of the drive current pulse. As illustrated inFIG. 6B, the low ESL capacitor has a smaller impedance at a high frequency than the non-low ESL capacitor having a higher equivalent series inductance ESL than the low ESL capacitor.

FIGS. 7A and 7Billustrate examples of the low ESL capacitor (capacitor70A) and the non-low ESL capacitor (capacitor70B).FIG. 7Aillustrates the low ESL capacitor (capacitor70A).FIG. 7Billustrates the non-low ESL capacitor (capacitor70B). Those capacitors are dual-terminal multilayer ceramic capacitors. As illustrated inFIGS. 7A and 7B, the multilayer ceramic capacitor is structured by a plurality of stacks of a ceramic sheet71made of a titanium oxide or a barium titanate and having a rectangular shape as its plan shape, and an internal wire72provided on the front face of the ceramic sheet71.

In the low ESL capacitor70A illustrated inFIG. 7A, a current flows in a transverse direction of the ceramic sheet71having the rectangular shape as its plan shape. That is, the low ESL capacitor is a dual-terminal multilayer ceramic capacitor having electrodes at both ends in the transverse direction. A length L1is defined in the current flow direction of the ceramic sheet71(transverse direction) and a width W1is defined in a direction orthogonal to the current flow direction (longitudinal direction). In this case, the length L1is smaller than the width W1(L1<W1). By reducing the length of the current path in this manner, the equivalent series inductance ESL is lower than that of the non-low ESL capacitor described next. The low ESL capacitor having the width W1larger than the length L1may be referred to as “LW-reverse type capacitor”.

In the non-low ESL capacitor70B illustrated inFIG. 7B, a current flows in a longitudinal direction of the ceramic sheet71having the rectangular shape as its plan shape. That is, the non-low ESL capacitor is a dual-terminal multilayer ceramic capacitor having electrodes at both ends in the longitudinal direction. A length L2is defined in the current flow direction of the ceramic sheet (longitudinal direction) and a width W2is defined in a direction orthogonal to the current flow direction (transverse direction). In this case, the length L2is larger than the width W2(L2>W2). Thus, the length of the current path increases and the equivalent series inductance ESL is higher than that of the low ESL capacitor.

The area of the low ESL capacitor mounted on the wiring board10is large but the rated capacity is relatively small. If the low ESL capacitor70A is used alone without the non-low ESL capacitor70B, a plurality of capacitors70A are needed to drive the light source20at about 2 W. In this case, the capacitors70A differ from each other in terms of current paths to the VCSEL. In a long current path, a wiring inductance increases. That is, the area of the plurality of low ESL capacitors70A mounted on the wiring board10increases but the equivalent series inductance ESL is not sufficiently low.

The non-low ESL capacitor uses a ceramic sheet71having a high dielectric constant and the rated capacity is relatively large though the area of the non-low ESL capacitor mounted on the wiring board10is small. Therefore, one non-low ESL capacitor suffices to drive the light source20at about 2 W. However, the equivalent series inductance ESL is higher than that of the low ESL capacitor. Therefore, it is difficult to reduce the rising period of the drive current pulse to be supplied to the light source20.

In this exemplary embodiment, the low ESL capacitor70A and the non-low ESL capacitor70B are used in combination. The low ESL capacitor70A and the non-low ESL capacitor70B are connected in parallel.

In this exemplary embodiment, the capacitor70C formed from the parasitic capacitance due to the structure of the wiring board10is used. Therefore, the rising period of the drive current pulse to be supplied to the light source20may further be reduced. As described later, the equivalent series inductance ESL of the capacitor formed from the parasitic capacitance due to the structure of the wiring board10is lower than that of the low ESL capacitor. By using the capacitor70C formed from the parasitic capacitance, the rising period of the current pulse to be supplied to the light source20may further be reduced. As described below, the parasitic capacitance due to the structure of the wiring board10is increased in this exemplary embodiment.

FIG. 8illustrates the drive current pulse to be supplied to the light source20. InFIG. 8, the horizontal axis represents time and the vertical axis represents a current.

As illustrated inFIG. 8, a rising start part α of the drive current pulse is supplied by using the capacitor70C formed from the parasitic capacitance. A rising part β of the drive current pulse is supplied by using the low ESL capacitor70A. A drive current supply part γ is supplied by using the non-low ESL capacitor70B.

Next, the light emitting device4is described in detail.

FIGS. 9A to 9Cillustrate the light emitting device4to which this exemplary embodiment is applied.FIG. 9Ais a plan view.FIG. 9Bis a sectional view taken along the line IXB-IXB inFIG. 9A.FIG. 9Cis a sectional view taken along the line IXC-IXC inFIG. 9A.FIG. 9Ais a see-through view of the light diffusion member30. In the drawing sheet ofFIG. 9A, a rightward direction is an x direction and an upward direction is a y direction. A direction orthogonal counterclockwise to the x direction and the y direction (frontward direction in the drawing sheet) is a z direction. Regarding individual members to be described below (e.g. the wiring board10and the light diffusion member30), a front side (+z side) in the drawing sheet is referred to as “front face” or “front face side”, and a rear side (−z side) in the drawing sheet is referred to as “back face” or “back face side”. In the following description, a see-through view of each member from the front face side is referred to as “top view”. In the drawing sheets ofFIGS. 9B and 9C, a rightward direction is the x direction, a rearward direction is the y direction, and an upward direction is the z direction.

As illustrated inFIGS. 9A and 9B, the light source20, the driver50, the capacitors70A and70B, and the holder60are provided on the front face of the wiring board10. The light diffusion member30is provided on the holder60.

In the wiring board10, for example, wiring layers including metal wires formed from copper (Cu) foil are provided on an insulating base (may be referred to as “insulating layer”) made of a glass epoxy resin. The wire is a conductor pattern connected into an electric circuit and its shape is not limited. The wiring board10is described as a printed wiring board having four wiring layers. Examples of the base made of a glass epoxy resin include a glass composite substrate (CEM-3) and a glass epoxy substrate (FR-4).

As illustrated inFIG. 9A, the light source20and the driver50of the light emitting device4are arranged in the x direction on the wiring board10.

As illustrated inFIG. 9A, the holder60has walls surrounding the light source20(inFIG. 9A, the walls are indicated by broken lines on the light source20side). As illustrated inFIG. 9B, the walls of the holder60hold the light diffusion member30. That is, the light diffusion member30keeps a predetermined distance from the light source20on the wiring board10by the holder60. The light diffusion member30covers the light source20. The description “the light diffusion member30covers the light source20” means that the light diffusion member30is provided on a path of light emitted from the light source20and the light emitted from the light source20passes through the light diffusion member30. That is, the description means that the light source20and the light diffusion member30overlap each other in top view from the front face side of the light diffusion member30.

The holder60is molded from, for example, a resin. To absorb light emitted from the light source20, the holder60may be colored in, for example, black. Therefore, the light emitted from the light source20and radiated onto the holder60is absorbed by the holder60.

As illustrated inFIGS. 9B and 9C, the wiring board10has a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer in this order from the front face of the wiring board10(+z side). The first wiring layer and the second wiring layer are insulated by an insulating layer11A. The second wiring layer and the third wiring layer are insulated by an insulating layer11B. The third wiring layer and the fourth wiring layer are insulated by an insulating layer11C. The insulating layers11A,11B, and11C are referred to as “insulating layers11” unless otherwise distinguished.

The first wiring layer includes a cathode wire12, an anode wire13F, and reference potential wires14-1F,14-2F, and14-3F that are electrically isolated from each other. InFIG. 9A, parts of the cathode wire12, the anode wire13F, and the reference potential wire14-3F hidden by the driver50are indicated by chain lines.

The second wiring layer includes a reference potential wire14M. As indicated by broken lines inFIG. 9A, the reference potential wire14M is provided over the entire wiring board10, that is, so-called solidly. The cathode wire12, the anode wire13F, and the reference potential wires14-1F,14-2F, and14-3F overlap the reference potential wire14M in top view. InFIG. 9A, the reference potential wire14M is provided widely so that the edges of the reference potential wire14M project beyond all the edges of the cathode wire12, the anode wire13F, and the reference potential wires14-1F,14-2F, and14-3F. However, the edges of the reference potential wire14M need not project beyond all the edges of the cathode wire12, the anode wire13F, and the reference potential wires14-1F,14-2F, and14-3F.

The third wiring layer includes a power supply potential wire13M. The power supply potential wire13M may be provided over the entire wiring board10, that is, so-called solidly similarly to the reference potential wire14M. The power supply potential wire13M may be connected to the anode wire13F to supply a power supply potential to the anode wire13F.

The fourth wiring layer includes a signal wire for transmitting a signal from the controller8to the driver50to control the signal generation circuit52. For example,FIGS. 9A and 9Billustrate signal wires15-1and15-2.

As illustrated inFIGS. 9A and 9B, the cathode wire12of the first wiring layer has a rectangular shape as its plan shape and connects the light source20to the driver50. The light source20is provided at one end of the cathode wire12. That is, the light source20(VCSELs) is mounted on the cathode wire12so that the cathode wire12is in contact with the cathode electrode214of the VCSELs of the light source20. The other end of the cathode wire12is connected to the driver50, specifically, to the drain of the MOS transistor51of the driver50(see the symbol [D] inFIG. 5).

The anode wire13F of the first wiring layer is provided close to three sides of the cathode wire12, that is, a −x side and ±y sides. At the lateral face21A of the light source20, the anode electrode218of the VCSELs of the light source20(seeFIGS. 2 and 3) is connected to the anode wire13F by bonding wires23.

The anode wire13F has two openings. The reference potential wires14-1F and14-2F are provided on an inner side of the respective openings. The reference potential wire14-3F is provided at an end of the wiring board10in the x direction. The reference potential wire14-3F is connected to the driver50, specifically, to the source of the MOS transistor51of the driver50(see the symbol [S] inFIG. 5).

As illustrated inFIGS. 9B and 9C, the reference potential wires14-1F and14-3F of the first wiring layer are connected to the reference potential wire14M of the second wiring layer by through conductors14-1V and14-3V provided through the insulating layer11A. Although illustration is omitted, the reference potential wire14-2F is also connected to the reference potential wire14M by a through conductor provided through the insulating layer11A. The through conductor is obtained by providing a conductive material such as copper (Cu) into a through hole of the insulating layer11, and electrically connects a wire on the front face side of the insulating layer11to a wire on the back face side of the insulating layer11. The through conductor may be referred to as “via”.

The anode wire13F of the first wiring layer is connected to the power supply potential wire13M of the third wiring layer by a through conductor13V provided through the insulating layer11A and the insulating layer11B. The through conductor13V is electrically isolated from the reference potential wire14M of the second wiring layer.

As illustrated inFIG. 9A, the capacitor70A is provided between the anode wire13F and the reference potential wire14-1F and the capacitor70B is provided between the anode wire13F and the reference potential wire14-2F in the first wiring layer of the wiring board10. As described above, the reference potential wires14-1F and14-2F are provided on the inner side of the two openings of the anode wire13F. Thus, the capacitor70A and the capacitor70B are surrounded by the anode wire13F. The anode wire13F may surround only one of the capacitors, for example, the capacitor70A.

The anode wire13F has the two openings and the reference potential wire14-1F and the reference potential wire14-2F are provided on the inner side of the respective openings. However, the anode wire13F may have one opening and an integrated reference potential wire obtained by connecting the reference potential wire14-1F and the reference potential wire14-2F may be provided on an inner side of the opening.

As illustrated inFIG. 9C, the capacitor70C is a parasitic capacitance caused between the anode wire13F of the first wiring layer and the reference potential wire14M of the second wiring layer in the wiring board10. The anode wire13F of the first wiring layer and the reference potential wire14M of the second wiring layer are insulated by the insulating layer11A. To increase the capacity of the capacitor70C, the area of the anode wire13F is increased. For example, the area of an overlap between the reference potential wire14M of the second wiring layer and the anode wire13F of the first wiring layer is set larger than the area of an overlap between the reference potential wire14M of the second wiring layer and the reference potential wire14-3F of the first wiring layer.

In the first wiring layer, the area of the anode wire13F is set larger than the area of the reference potential wires14-1F,14-2F, and14-3F.

The anode wire13F of the first wiring layer of the wiring board10accounts for 50% or more of the area of the front face of the wiring board10. The anode wire13F of the first wiring layer of the wiring board10preferably accounts for 75% or more of the area of the front face of the wiring board10.

To increase the capacity of the capacitor70C formed from the parasitic capacitance, a thickness tcof the insulating layer11A is 100 μm or less. The thickness tcof the insulating layer11A is preferably 80 μm or less.

FIGS. 10A to 10Cillustrate a comparative light emitting device4′ to which this exemplary embodiment is not applied.FIG. 10Ais a plan view.FIG. 10Bis a sectional view taken along the line XB-XB inFIG. 10A.FIG. 10Cis a sectional view taken along the line XC-XC inFIG. 10A.FIG. 10Ais a see-through view of the light diffusion member30. Members having the same functions as those of the light emitting device4illustrated inFIGS. 9A, 9B, and 9Cto which this exemplary embodiment is applied are represented by the same reference symbols. Description is omitted about the same parts as those of the light emitting device4, and differences are described.

The light emitting device4′ differs from the light emitting device4in terms of the anode wire13F and a reference potential wire14F of the first wiring layer of the wiring board10. The anode wire13F has a rectangular shape as its plan shape and is provided near the lateral face21A of the light source20(−y side). That is, the anode wire13F is connected to the anode electrode218of the light source20by the bonding wires23and is connected to the first terminals of the capacitors70A and70B. The reference potential wire14F surrounds the cathode wire12and the anode wire13F. The reference potential wire14F is connected to the reference potential wire14M of the second wiring layer by a through conductor14V.

In the light emitting device4′, the cathode wire12, the anode wire13F, and the reference potential wire14F of the first wiring layer of the wiring board10overlap the reference potential wire14M of the second wiring layer of the wiring board10in top view similarly to the light emitting device4. In the first wiring layer of the wiring board10, the reference potential wire14F is provided except for the parts corresponding to the cathode wire12and the anode wire13F. The area of an overlap between the reference potential wire14M of the second wiring layer and the anode wire13F of the first wiring layer is set smaller than the area of an overlap between the reference potential wire14M of the second wiring layer and the reference potential wire14F of the first wiring layer.

In the first wiring layer, the area of the anode wire13F is set smaller than the area of the reference potential wire14F.

The anode wire13F of the first wiring layer of the wiring board10accounts for less than 50% of the area of the front face of the wiring board10.

Hitherto, the wiring board10is generally designed such that the cathode wire12and the anode wire13F are provided at parts of the first wiring layer where electrical connection is needed, and the reference potential wire14F is provided at the remaining part. In this design, the area of the overlap between the anode wire13F of the first wiring layer and the reference potential wire14M of the second wiring layer in the wiring board10is smaller than in the case of the light emitting device4. Therefore, the capacity of the capacitor70C formed from the parasitic capacitance (seeFIG. 5) is small. In the light emitting device4′, the capacitor70C does not supply a sufficient current for the rising start part (“α” inFIG. 8) of the drive current pulse for causing the light source20to emit light. That is, in the light emitting device4′, the rising period of the drive current pulse to be supplied to the light source20is not sufficiently reduced.

As described above, in the light emitting device4to which this exemplary embodiment is applied, the area of the anode wire13F is set to a large area to increase the area of the overlap between the anode wire13F of the first wiring layer and the reference potential wire14M of the second wiring layer via the insulating layer11A in the wiring board10.

The power of light from the light source20of the light emitting device4is 2 W to 4 W. Such a high-power light source20generates a large amount of heat. It is therefore appropriate to efficiently dissipate the heat from the light source20. Thus, the light source20may be provided on an insulating heat dissipation base having a higher thermal conductivity than the wiring board10, and the heat dissipation base may be provided on the wiring board10. The thermal conductivity of the insulating layer called “FR-4” for use in the wiring board10is about 0.4 W/m·K. Therefore, the thermal conductivity of the heat dissipation base is preferably 10 W/m·K or more, more preferably 50 W/m·K or more, and still more preferably 100 W/m·K or more. Examples of a material having the thermal conductivity of 10 W/m·K or more include alumina (Al2O3) having a thermal conductivity of 20 to 30 W/m·K. Examples of a material having the thermal conductivity of 50 W/m·K or more include silicon nitride (Si3N4) having a thermal conductivity of about 85 W/m·K. Examples of a material having the thermal conductivity of 100 W/m·K or more include aluminum nitride (AlN) having a thermal conductivity of 150 to 250 W/m·K. Those materials may be referred to as “ceramic materials”. The entire heat dissipation base may be made of the ceramic material. The heat dissipation base may be made of other insulating materials having a high thermal conductivity, such as silicon (Si) undoped with impurities.

In the light emitting device4to which this exemplary embodiment is applied, the low ESL capacitor70A and the non-low ESL capacitor70B are used. If the capacity of the capacitor70C formed from the parasitic capacitance is large, the low ESL capacitor70A may be omitted.

In the light emitting device4to which this exemplary embodiment is applied, the capacitor70C is the parasitic capacitance caused between the anode wire13F of the first wiring layer and the reference potential wire14M of the second wiring layer in the wiring board10. A wiring layer to which the reference potential is supplied (referred to as “capacitor layer”) may be provided in the insulating layer11A to face the anode wire13F, and a capacitance caused between the anode wire13F and the capacitor layer may be used as the capacitor70C. The capacitance caused between the anode wire13F and the capacitor layer is another example of the capacitive component.

In the light emitting device4to which this exemplary embodiment is applied, the light source20and the driver50are provided on the front face of the wiring board10. A circuit board having the light source20and a circuit board having the driver50may be provided separately and connected by a flexible flat cable (FFC) or a flexible printed circuit (FPC).

In the light emitting device4to which this exemplary embodiment is applied, the light diffusion member30that outputs incident light at a larger divergence angle through diffusion is used as an example of an optical member. The optical member may be a diffractive optical element (DOE) that outputs incident light with its direction changed to a different direction. The optical member may also be a condenser lens, a microlens, a protective cover, or other transparent members.