Semiconductor device and display apparatus

A semiconductor device according to the present invention includes: a gate electrode (62) of a thin film transistor (10) and an oxygen supply layer (64), the gate electrode (62) and the oxygen supply layer (64) being formed on a substrate (60); a gate insulating layer (66) formed on the gate electrode (62) and the oxygen supply layer (64); an oxide semiconductor layer (68) of the thin film transistor (10), the oxide semiconductor layer (68) being formed on the gate insulating layer (66); and a source electrode (70S) and a drain electrode (70d) of the thin film transistor (10), the source electrode (70S) and the drain electrode (70d) being formed on the gate insulating layer (66) and the oxide semiconductor layer (68).

TECHNICAL FIELD

The present invention relates to a semiconductor device and display device having a thin film transistor.

BACKGROUND ART

Generally speaking, a liquid crystal display device or an organic EL (Electro Luminescence) display device of an active matrix type includes: a substrate on which a thin film transistor (Thin Film Transistor; hereinafter also referred to as “TFT”) is formed as a switching element for each pixel (hereinafter also referred to as “TFT substrate”); a counter substrate on which a counter electrode, color filters, and the like are formed; and an optical modulation layer, e.g., a liquid crystal layer, provided between the TFT substrate and the counter substrate.

On the TFT substrate, a plurality of source lines, a plurality of gate lines, and a plurality of TFTs respectively disposed at intersections therebetween, pixel electrodes for applying a voltage across the optical modulation layer such as a liquid crystal layer, storage capacitor lines and storage capacitor electrodes, and the like are formed.

The construction of a TFT substrate is disclosed in Patent Document 1, for example. Hereinafter, with reference to the drawings, the construction of a TFT substrate disclosed in Patent Document 1 will be described.

FIG. 16(a) is a schematic plan view showing the TFT substrate in outline, and theFIG. 16(b) is an enlarged plan view showing one pixel of the TFT substrate.FIG. 17is a cross-sectional view of a TFT and terminal portions of the semiconductor device shown inFIG. 16.

As shown inFIG. 16(a), the TFT substrate includes a plurality of gate lines2016and a plurality of source lines2017. Each region2021surrounded by these lines2016and2017defines a “pixel”. In a region2040of the TFT substrate other than the region (displaying region) where the pixels are formed, a plurality of connecting portions2041for allowing the plurality of gate lines2016and source lines2017to be respectively connected to a driving circuit are provided. Each connecting portion2041constitutes a terminal portion for providing connection to external wiring.

As shown inFIG. 16(b) andFIG. 17, a pixel electrode2020is provided so as to cover each region2021defining a pixel. Moreover, a TFT is formed in each region2021. The TFT includes a gate electrode G, gate insulating films2025and2026covering the gate electrode G, a semiconductor layer2019disposed on the gate insulating film2026, and a source electrode S and a drain electrode D respectively connected to both end portions of the semiconductor layer2019. The TFT is covered by a protection film2028. An interlayer insulating film2029is formed between the protection film2028and the pixel electrode2020. The source electrode S of the TFT is connected to a source line2017, whereas the gate electrode G is connected to a gate line2016. The drain electrode D is connected to the pixel electrode2020within a contact hole2030.

Moreover, a storage capacitor line2018is formed in parallel to the gate line2016. The storage capacitor line2018is connected to a storage capacitor. Herein, the storage capacitor is composed of a storage capacitor electrode2018bwhich is made of the same conductive film as the drain electrode D, a storage capacitor electrode2018awhich is made of the same conductive film as the gate line2016, and the gate insulating film2026interposed therebetween.

On the connecting portion2041extending from each gate line2016or source line2017, the gate insulating films2025and2026and the protection film2028are not formed, but a connection line2044is formed so as to be in contact with an upper face of the connecting portion2041. As a result, electrical connection between the connecting portion2041and the connection line2044is ensured.

As shown inFIG. 17, in the liquid crystal display device, the TFT substrate is disposed so as to oppose a substrate2014on which a counter electrode and color filters are formed, with a liquid crystal layer2016interposed therebetween.

When fabricating such a TFT substrate, the regions2021to become pixels (also referred to as “pixel portions”) and the terminal portions are preferably formed through a common process, so as to reduce increase in the number of masks and the number of steps.

In order to fabricate the aforementioned TFT substrate, it is necessary to etch away the portions of the gate insulating films2025and2026and the protection film2028that are located in the terminal deployment region2040, and the portions of the gate insulating film2025and the protection film2028that are located in the regions where the storage capacitors are to be formed. Patent Document 1 discloses forming an interlayer insulating film2029by using an organic insulating film, and by using this as a mask, etching the insulating films2025and2026and the protection film2028.

In the recent years, it has been proposed to form a channel layer of a TFT by using an oxide semiconductor film such as IGZO (InGaZnOx), instead of a silicon semiconductor film. Such a TFT is referred to as an “oxide semiconductor TFT”. An oxide semiconductor has higher mobility than does amorphous silicon. Therefore, an oxide semiconductor TFT is able to operate more rapidly than an amorphous silicon TFT. Moreover, an oxide semiconductor film is formed through simpler processes than those of a polycrystalline silicon film, and therefore is also applicable to devices which require a large area.

Patent Document 2 describes an example of an oxide semiconductor TFT. Patent Document 3 describes an example of a field-effect transistor having an active layer of an amorphous oxide semiconductor.

For forming an amorphous oxide semiconductor layer, Patent Document 3 describes, prior to forming an amorphous oxide semiconductor layer on a substrate, irradiating the substrate surface with ultraviolet in an ozone ambient, irradiating the substrate surface with plasma, or cleaning the substrate surface with hydrogen peroxide. Moreover, this document describes: performing a step of forming an active layer containing amorphous oxide in an ambient such as ozone gas or nitrogen oxide gas; after forming amorphous oxide on a substrate, conducting a heat treatment at a temperature which in the case where is higher than the film-formation temperature of the amorphous oxide; and so on.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

However, an oxide semiconductor TFT may allow oxygen defects to occur during the production process of the TFT, e.g., a heat treatment step, possibly resulting in a problem of carrier electrons causing an unwanted OFF current. Another problem may be that, in a step of etching the source and drain electrodes and a step of forming an insulating layer thereabove, the oxide semiconductor film under them may undergo reduction or other damages.

As a result of a study by the inventors, it has been found that, in an oxide semiconductor TFT of a construction such that the oxide semiconductor layer is in contact with an underlying gate insulating layer or an overlying protection layer, etc., a defect level due to oxygen defects or the like is prone to occur inside the oxide semiconductor layer, or near an interface between the oxide semiconductor layer and an insulating layer, a protection layer, or the like, thus causing problems such as deterioration in TFT characteristics, lowered reliability, and quality fluctuations.

Patent Document 3 above describes, after forming an amorphous oxide, conducting a heat treatment at a temperature which is higher than the film-formation temperature of the amorphous oxide, and so on, this being in order to obtain a transistor with good characteristics. However, even with such a method, the defect level associated with oxygen defects cannot be reduced, and it is difficult to obtain satisfactory TFT characteristics.

The present invention has been made in view of the above, and aims to produce a semiconductor device with good TFT characteristics by reducing defects occurring in an oxide semiconductor layer of an oxide semiconductor TFT. Moreover, the present invention aims to provide a high-performance display device having such a semiconductor device as the TFT substrate.

Solution to Problem

A semiconductor device according to the present invention is a semiconductor device having a thin film transistor, the semiconductor device comprising: a gate electrode of the thin film transistor and an oxygen supply layer, the gate electrode and the oxygen supply layer being formed on a substrate; a gate insulating layer formed on the gate electrode and the oxygen supply layer; an oxide semiconductor layer of the thin film transistor, the oxide semiconductor layer being formed on the gate insulating layer; and a source electrode and a drain electrode of the thin film transistor, the source electrode and the drain electrode being disposed on the gate insulating layer and the oxide semiconductor layer.

In one embodiment, the oxygen supply layer is a layer made of a material containing water (H2O), an OR group, or an OH group.

In one embodiment, the oxygen supply layer is made of a silicone resin, or a resin material containing a silanol group or an Si—OH group.

In one embodiment, the oxygen supply layer is made of an ester-polymerization resin, or a resin material containing a CO—OR group.

In one embodiment, the oxygen supply layer is made of an acrylic resin or a material containing an SOG material.

In one embodiment, the semiconductor device comprises: a lower connection line made of a same material as the gate electrode; an upper connection line made of a same material as the source electrode and the drain electrode; and a connecting portion to which the upper connection line and the lower connection line are connected, wherein, at the connecting portion, the upper connection line and the lower connection line are connected via a contact hole penetrating through the oxygen supply layer and the gate insulating layer.

In one embodiment, the semiconductor device comprises: a lower connection line made of a same material as the gate electrode; an upper connection line made of a same material as the source electrode and the drain electrode; a protection layer formed on the source electrode and the drain electrode; a conductive layer formed on the protection layer; and a connecting portion to which the upper connection line and the lower connection line are connected, wherein, at the connecting portion, the upper connection line and the lower connection line are connected via the conductive layer formed in a contact hole penetrating through the oxygen supply layer, the gate insulating layer, and the protection layer.

In one embodiment, the semiconductor device comprises: a lower connection line made of a same material as the gate electrode; an upper connection line made of a same material as the source electrode and the drain electrode; a protection layer formed on the source electrode and the drain electrode; a conductive layer formed on the protection layer; and a connecting portion to which the upper connection line and the lower connection line are connected, wherein, at the connecting portion, the upper connection line and the conductive layer are connected via a first contact hole penetrating through the protection layer, and the conductive layer and the lower connection line are connected via a second contact hole penetrating through the protection layer, the gate insulating layer, and the oxygen supply layer.

In one embodiment, the semiconductor device comprises a storage capacitor including: a storage capacitor electrode made of a same material as the gate electrode; and a storage capacitor counter electrode opposing the storage capacitor electrode, the storage capacitor counter electrode being made of a same material as the source electrode and the drain electrode.

In one embodiment, the semiconductor device comprises a second oxygen supply layer formed above the oxide semiconductor layer, the source electrode, and the drain electrode.

In one embodiment, the semiconductor device comprises a protection layer formed between: the oxide semiconductor layer, the source electrode, and the drain electrode; and the second oxygen supply layer.

In one embodiment, the second oxygen supply layer is a layer made of a material containing water (H2O), an OR group, or an OH group.

Another semiconductor device according to the present invention is a semiconductor device having a thin film transistor, comprising: a gate electrode of the thin film transistor, the gate electrode being formed on a substrate; a gate insulating layer formed on the gate electrode; an oxygen supply layer formed on the gate insulating layer; an oxide semiconductor layer of the thin film transistor, the oxide semiconductor layer formed on the oxygen supply layer; and a source electrode and a drain electrode of the thin film transistor, the source electrode and the drain electrode being disposed on the oxide semiconductor layer.

In one embodiment, an aperture is formed in the oxygen supply layer; and the oxide semiconductor layer is in contact with the gate insulating layer in the aperture of the oxygen supply layer.

In one embodiment, the oxygen supply layer is a layer made of a material containing water (H2O), an OR group, or an OH group.

In one embodiment, the oxygen supply layer is made of a silicone resin, or a resin material containing a silanol group or an Si—OH group.

In one embodiment, the oxygen supply layer is made of an ester-polymerization resin, or a resin material containing a CO—OR group.

In one embodiment, the oxygen supply layer is made of an acrylic resin or a material containing an SOG material.

A display device according to the present invention is a display device comprising the above semiconductor device.

Advantageous Effects of Invention

According to the present invention, H2O, an OR group, or an OH group is supplied from an oxygen supply layer to an oxide semiconductor layer, whereby a high-performance semiconductor device having an oxide semiconductor layer whose defects are better restored can be provided. Moreover, according to the present invention, a highly-reliable semiconductor device with little variation for each TFT characteristic can be obtained. Moreover, according to the present invention, high-quality displaying can be provided by a display device having an oxide semiconductor TFT with good characteristics.

DESCRIPTION OF EMBODIMENTS

Hereinafter, with reference to the drawings, display devices and semiconductor devices according to embodiments of the present invention will be described. However, the scope of the invention is not to be limited to the following embodiments. The semiconductor device of the present invention is a TFT substrate on which an oxide semiconductor TFT is formed, and broadly encompasses TFT substrates of various display devices, electronic devices, and the like. In the description of the present embodiment, the semiconductor device will be illustrated as a TFT substrate of a display device having oxide semiconductor TFTs as switching elements.

FIG. 1is a perspective view schematically showing the construction of a liquid crystal display device1000according to Embodiment 1 of the present invention.

As shown inFIG. 1, the liquid crystal display device1000include: a TFT substrate (semiconductor device)100and a counter substrate200, which oppose each other with a liquid crystal layer interposed therebetween; polarizers210and220provided respectively outside the TFT substrate100and the counter substrate200; and a backlight unit230which emits light for displaying toward the TFT substrate100. On the TFT substrate100, a scanning line driving circuit240for driving a plurality of scanning lines (gate bus lines) and a signal line driving circuit250for driving a plurality of signal lines (data bus lines) are disposed. The scanning line driving circuit240and the signal line driving circuit250are connected to a control circuit260which is internal or external to the TFT substrate100. Under control of the control circuit260, scanning signals for switching the TFTs ON/OFF are supplied from the scanning line driving circuit240to the plurality of scanning lines, and display signals (applied voltages to the pixel electrodes20shown inFIG. 3) are supplied from the signal line driving circuit250to the plurality of signal lines.

The counter substrate200includes color filters and a common electrode. In the case of displaying in three primary colors, the color filters include an R (red) filter, a G (green) filter, and a B (blue) filter each provided corresponding to a pixel. The common electrode is formed so as to cover the plurality of pixel electrodes20, with the liquid crystal layer interposed therebetween. In accordance with a potential difference applied between the common electrode and each pixel electrode20, the liquid crystal molecules between the electrodes become aligned for the respective pixel, whereby displaying is performed.

FIG. 2is a plan view schematically showing the construction of the TFT substrate100, andFIG. 3is a plan view schematically showing the construction of a displaying region DA of the TFT substrate100.

As shown inFIG. 2, the TFT substrate100has the display section DA and a peripheral portion FA located outside the display section DA. In the peripheral portion FA, electrical elements such as the scanning line driving circuit240, the signal line driving circuit250, and voltage supply circuits are disposed in COG (Chip on Glass) fashion. The electrical elements such as TFTs or diodes in the peripheral portion FA may be formed through the same production steps as the TFTs in the display section DA. Moreover, terminal portions30are provided near outer ends of the peripheral portion FA for attaching external devices, e.g., FPCs (Flexible Printed Circuits). Furthermore, connecting portions25for electrically connecting upper connection lines such as signal lines and lower connection lines such as scanning lines are provided in the peripheral portion FA.

Although not shown, a plurality of connection lines are formed at the boundary between the displaying region DA and the peripheral region FA. Each signal line12is electrically connected to a connection line via a correspondingly-formed connecting portion. Via the connecting portion, a signal line12as the upper connection line is connected to a connection line as the lower connection line.

As shown inFIG. 3, a plurality of pixels50are arranged in a matrix array in the display section DA, and a plurality of scanning lines14and a plurality of signal lines12are disposed orthogonal to one another. The scanning lines14partly constitute gate electrodes of the TFTs10. Near each of the intersections between the plurality of scanning lines14and the plurality of signal lines12, a thin film transistor (TFT)10is formed as an active element for each pixel50. In each pixel50, a pixel electrode20which is made of e.g. ITO (Indium Tin Oxide) is disposed, the pixel electrode20being electrically connected to the drain electrode of the TFT10. Moreover, between any two adjacent scanning lines14, a storage capacitor line (also referred to as a Cs line)16extends in parallel to the scanning lines14.

In each pixel10, a storage capacitor (Cs)18is formed, and a part of the storage capacitor line16serves as a storage capacitor electrode (lower electrode) of the storage capacitor18. This storage capacitor electrode, a storage capacitor counter electrode (upper electrode), and a layer disposed between both electrodes together constitute a storage capacitor18. The drain electrode of the TFT10is connected to the storage capacitor counter electrode, and the storage capacitor counter electrode is connected to the pixel electrode20via a contact hole which is formed in the interlayer insulating layer. The gate electrode of the TFT10, the scanning line14, the storage capacitor line16, and the storage capacitor electrode are made of the same material and through the same step. The source electrode and the drain electrode of the TFT10, the signal line12, and the storage capacitor counter electrode are made of the same material and through the same step.

FIG. 4is a cross-sectional view schematically showing the construction of the TFT10on the TFT substrate100according to Embodiment 1 (which may also be referred to as the “semiconductor device100”).

As shown inFIG. 4, the TFT10includes: a gate electrode62formed on a substrate60such as a glass substrate; an oxygen supply layer64formed on the substrate60so as to partially cover the gate electrode62; a gate insulating layer66(which may simply be referred to as the “insulating layer66”) formed on the oxygen supply layer64; an oxide semiconductor layer68formed on the gate insulating layer66; a source electrode70sand a drain electrode70dformed on the gate insulating layer66and the oxide semiconductor layer68; and a protection layer72formed on the source electrode70sand drain electrode70d.

As will be shown later inFIG. 8(h), a pixel electrode20of a transparent electrically conductive material is formed on the protection layer72. A contact hole74his formed in the protection layer72under the pixel electrode20, such that the pixel electrode20is in contact with the drain electrode70dof the TFT10at the bottom of the contact hole74h. Note that a construction where an interlayer insulating layer is disposed between the protection layer72and the pixel electrode20would also be possible.

The gate electrode62may have a two-layer structure where an upper gate electrode of copper (Cu), for example, is formed on a lower gate electrode of titanium (Ti), for example. The gate electrode may have a three-layer construction of Ti/Al(aluminum)/Ti or the like.

The oxygen supply layer64is a layer made of a material containing water (H2O), an OR group, or an OH group. In the present embodiment, the oxygen supply layer64is formed by applying a spin-on glass (SOG) material containing a silicone resin by spin coating technique, for example. As the SOG material, a material containing silanol (Si(OH)4), alkoxysilane, a siloxane resin, or the like may also be used. The oxygen supply layer64may be made of another resin material containing a silanol group or an Si—OH group. Moreover, the oxygen supply layer64may be made of an acrylic resin, an ester-polymerization resin, or a resin material containing a CO—OR group.

The gate insulating layer66is made of silicon nitride. The gate insulating layer66may be made of silicon oxide, and may have a two-layer construction of a silicon nitride layer and a silicon oxide layer. The gate insulating layer66is in contact with the gate electrode62within an aperture which is formed in the oxygen supply layer64.

The oxide semiconductor layer68is a layer of an In—Ga—Zn—O type semiconductor (IGZO). The source electrode70sand drain electrode70dformed on the oxide semiconductor layer68are conductive layers having a three-layer construction of Ti/Al/Ti. The source electrode70sand drain electrode70dmay have a two-layer construction of Al/Ti, Cu/Ti, Cu/Mo (molybdenum), or the like.

The protection layer72is made of silicon oxide (SiO2) or silicon nitride (SiNx). A construction omitting the protection layer72would also be possible.

As shown inFIG. 5, since the oxygen supply layer64contains H2O, an OR group, or an OH group, in a heat treatment step such as annealing, the H2O, OH group, or OR group is diffused into the oxide semiconductor layer68from the oxygen supply layer64via the gate insulating layer66, thereby making up for the defects associated with oxygen defects or the like in the oxide semiconductor layer68. Therefore, the TFT characteristics are improved, and a high-quality semiconductor device with little TFT-to-TFT variation can be provided. Moreover, in the TFT10, the source electrode70sand drain electrode70dare formed from an end of the oxide semiconductor layer64to over the oxygen supply layer64outside thereof. Therefore, the H2O, OR group, or OH group which has migrated from the oxygen supply layer64to the gate insulating layer66is reflected at the bottom faces of the source electrode70sand drain electrode70d, so that parts thereof migrate toward the oxide semiconductor layer68. Thus, when conducting a heat treatment after forming the source electrode70sand drain electrode70d, the source electrode70sand drain electrode70dwill serve as diffusion prevention layers, thus allowing greater amounts of H2O, an OR group, or an OH group to be supplied to the oxide semiconductor layer68, and more defects restored.

FIG. 6(a) is a graph showing voltage-current characteristics of the TFT10of Embodiment 1, and (b) is a graph representing voltage-current characteristics of a TFT lacking an oxygen supply layer. In both graphs, the horizontal axis represents gate voltage values, and the vertical axis represents source-drain current values; and characteristics under a drain voltage of 10 V are indicated by a solid line, while the characteristics under a drain voltage of 0.1 V are indicated by a broken line.

As shown inFIG. 6(a), in the TFT10of Embodiment 1, the current rise characteristics (S value) near a gate voltage of 0 V are constant irrespective of the drain voltage, and an appropriate current value which is in accordance with the applied voltage is being obtained once the TFT is ON. On the other hand, as shown inFIG. 6(b), in a TFT lacking an oxygen supply layer, the S value varies for each drain voltage, and there are fluctuations in the rise position of the ON current and in the OFF current value. These comparisons indicate that the TFT10having the oxygen supply layer54according to Embodiment 1 provides a high-performance semiconductor device with more stable TFT characteristics.

Next, a method for producing the TFT substrate100F will be described with reference toFIG. 7andFIG. 8.

FIGS. 7(a) to (f) andFIGS. 8(g) to (h) are schematic cross-sectional views showing production steps for the TFT substrate100.

First, a Ti layer and a Cu layer are stacked in this order on the substrate60by a sputtering technique or the like. The Ti layer has a thickness of 30 to 150 nm, and the Cu layer has a thickness of 200 to 500 nm. Next, the two stacked layers are patterned by using known photolithography and wet etching techniques (first masking step) to obtain a gate electrode62shown inFIG. 7(a). At this time, scanning lines14, storage capacitor lines16, storage capacitor electrodes, lower connection lines, and the like not shown are also formed at the same time. Thereafter, the remaining resist is removed and the substrate is cleaned.

Next, as shown inFIG. 7(b), by spin coating, an oxygen-supplying material64mis formed on the substrate60so as to cover the gate electrode62. Herein, a silicone resin or an SOG material is used as the oxygen-supplying material64m. As the SOG material, a material containing silanol (e.g., Si(OH)4), alkoxysilane, a siloxane resin or the like may also be used. The oxygen supply layer64may be made of any other resin material containing a silanol group or an Si—OH group. Moreover, the oxygen supply layer64may be made of an acrylic resin, an ester-polymerization resin, or a resin material containing a CO—OR group.

Next, as shown inFIG. 7(c), an aperture is made in the oxygen-supplying material64mover the gate electrode62by a photolithography technique (second masking step), whereby an oxygen supply layer64is formed.

Next, as shown inFIG. 7(d), a gate insulating layer66is stacked on the oxygen supply layer64so as to cover the aperture. The gate insulating layer66is a silicon nitride layer which is stacked to a thickness of 100 to 700 nm by a plasma CVD technique. Instead of silicon nitride, silicon oxide (SiO2) may be stacked, or both silicon nitride and silicon oxide may be stacked. Within the aperture of the oxygen supply layer64, the gate insulating layer66is in contact with the gate electrode62.

Next, an oxide semiconductor is stacked on the gate insulating layer66. The oxide semiconductor is formed by stacking, for example, an In—Ga—Zn—O type semiconductor (IGZO) to a thickness of 10 to 100 nm using a sputtering technique. The oxide semiconductor may be stacked by an application technique or an ink jet technique.

Thereafter, the stacked oxide semiconductor is patterned by a photolithography technique, e.g., a wet etching technique using oxalic acid (third masking step), thereby obtaining an oxide semiconductor layer68to become a channel layer of the TFT10, as shown inFIG. 7(e). Thereafter, the remaining resist is removed and the substrate is cleaned. As the oxide semiconductor, other types of oxide semiconductor films may be used, instead of IGZO.

Next, by a sputtering technique, Ti, Al, and Ti are stacked in this order on the gate insulating layer66so as to cover the oxide semiconductor layer68. Next, by photolithography and wet etching techniques, these three layers are patterned to obtain the source electrode70sand drain electrode70d(fourth masking step), as shown inFIG. 7(f). Thereafter, the remaining resist is removed, and the substrate is cleaned. Dry etching may be used instead of wet etching. Rather than stacking Ti, Al, and Ti, instead, Al/Ti, Cu/Ti, or Cu/Mo may be stacked. In this step, signal lines12, storage capacitor counter electrodes, upper connection lines, and the like not shown are also formed at the same time.

Next, silicon oxide is stacked on the entire substrate by a CVD technique. Instead of silicon oxide, silicon nitride may be stacked, or both silicon oxide and silicon nitride may be stacked. The layer thus formed is called a PAS film. Thereafter, the PAS film was subjected to an annealing treatment at a temperature of 200° C. to 400° C. in an atmospheric ambient. Through the annealing treatment, a reflective layer is formed between the lower faces of the source electrode70sand drain electrode70dand the oxide semiconductor layer68.

This low-reflection layer is formed as an oxidation-reduction reaction occurs between the titanium composing the lower layers of the source electrode70sand drain electrode70dand the oxide semiconductor layer68, whereby the titanium is oxidized and at the same time the indium in the oxide semiconductor68is reduced. If the low-reflection layer did not exist, light originating from the backlight unit and external light such as sunlight that enter the TFT substrate10would repeatedly undergo reflection between the lower faces of the source electrode70sand drain electrode70dand the upper face of the gate electrode62, and a large part thereof would reach the channel portion of the oxide semiconductor layer68to deteriorate the TFT characteristics. In the TFT10of the present embodiment, because of a low-reflection layer being formed as mentioned above, reflection of incident light is prevented, and the amount of light entering the channel portion can be reduced. As a result, a highly-reliable TFT substrate with reduced characteristics variation can be provided.

Thereafter, the stacked PAS film is patterned by a photolithography technique (fifth masking step) to obtain a protection layer72shown inFIG. 8(g). Through the patterning, an aperture72his formed in the protection layer72.

Next, on the protection layer72, a transparent electrically conductive material is deposited by a sputtering technique, for example. At this time, the transparent electrically conductive material is in contact with the drain electrode70dwithin the contact hole74h. ITO is used as the transparent electrically conductive material. IZO, ZnO, or the like may be used as the transparent electrically conductive material. Then, by a known photolithography technique, the transparent electrode layer is patterned (sixth masking step), whereby a pixel electrode20is formed as shown inFIG. 8(h).

Through the above steps, the TFT substrate100having the TFT10is completed.

Next, with reference toFIG. 9toFIG. 11, first to third construction examples of the connecting portion25of the TFT substrate100will be described.FIG. 9toFIG. 11schematically show cross sections of first to third construction examples of the connecting portion25, respectively.

First Construction Example

The connecting portion25according to a first construction example includes, as shown inFIG. 9, a lower connection line62dformed on the substrate60, an oxygen supply layer64formed on the lower connection line62d, a gate insulating layer66formed on the oxygen supply layer64, and an upper connection line70uformed on the gate insulating layer66. The lower connection line62dis a metal layer which is made at the same time and of the same material as the gate electrode62. The upper connection line70uis a metal layer which is made at the same time and of the same material as the source electrode70sand drain electrode70d.

At the connecting portion25, in each of the oxygen supply layer64and the gate insulating layer66, an aperture is made at a mutually overlapping position, with a contact hole25habeing made so as to penetrate through these two layers. The aperture in the gate insulating layer66is larger than the aperture in the oxygen supply layer64, and in the contact hole25ha, side faces of the gate insulating layer66and the oxygen supply layer64are formed in step shapes. The upper connection line70uand the lower connection line62dare connected via the contact hole25ha. In other words, the upper connection line70uformed in the contact hole25hais connected to the lower connection line62dat the bottom of the contact hole25ha.

When stacking the metal layer of the upper connection line70u, if the side face of the contact hole25hais a steep slope, the metal layer is likely to be disrupted at the side face, so that line breaking may occur at the connecting portion. In this construction example, the upper connection line70uis formed on the step-shaped side faces of the gate insulating layer66and the oxygen supply layer64, rather than on a side face with a steep gradient; therefore, disruption of the upper connection line70uis unlikely to occur. Therefore, a highly-reliable connecting portion25can be formed.

Second Construction Example

The connecting portion25according to a second construction example includes, as shown inFIG. 10, a lower connection line62dformed on the substrate60, an oxygen supply layer64formed on the lower connection line62d, an gate insulating layer66formed on the oxygen supply layer64, an upper connection line70uformed on the gate insulating layer66, a protection layer72formed on the upper connection line70u, and a conductive layer20tformed on the protection layer72. The lower connection line62dis a metal layer which is made at the same time and of the same material as the gate electrode62, whereas the upper connection line70uis a metal layer which is made at the same time and of the same material as the source electrode70sand drain electrode70d. The conductive layer20tis made at the same time and of the same material as the pixel electrode20.

At the connecting portion25, in each of the oxygen supply layer64, the gate insulating layer66, the upper connection line70u, and the protection layer72, an aperture is made at a mutually overlapping position. The aperture is formed so as to increase in size from lower layers to upper layers, and a contact hole25hbis formed so as to penetrate through these layers. In the contact hole25hb, the ends of the layers are formed in step shapes, so as to be located increasingly outside in increasingly upper layers.

The upper connection line70uand the lower connection line62dare connected via the conductive layer20tin the contact hole25hb. In other words, in the contact hole25hb, the conductive layer20tis formed so as to cover the side faces of the oxygen supply layer64, the gate insulating layer66, the upper connection line70u, and the protection layer72. At these side faces, the conductive layer20tand the upper connection line70uare connected; and the conductive layer20tand the lower connection line62dare connected at the bottom of the contact hole25ha.

When forming the conductive layer20tin the contact hole25hb, a metal such as ITO or IZO is stacked by a sputtering technique. If the side face of the contact hole25hais a steep slope, disruption of the metal layer or insufficient contact between the metal layer and the upper connection line70uis likely to occur. Moreover, trying to form the layers so that their ends are at the same position might result in the end of a lower layer being formed outside the end of an upper layer, owing to mask misalignment in photolithography, variations in etching shift, overhang, and so on; this causes line breaking in the conductive layer20t.

In this construction example, since the side faces of the layers are formed so as to be located increasingly outside in increasingly upper layers, the side face of the contact hole25hbis formed in step shapes, thereby preventing line breaking of the conductive layer20tand insufficient contact between the conductive layer20tand the upper connection line70u. Moreover, since connection at a site of multilayer construction is achieved via a single contact hole, the connecting portion can be reduced in area. This allows for higher density and downsizing of the TFT substrate. Moreover, the contact hole25hbcan be formed by performing a batch etching of the respective layers by utilizing half-tone exposure, resist ashing, or the like. In this case, the production efficiency is improved, and the TFT substrate can be produced at low cost.

Third Construction Example

The connecting portion25according to a third construction example includes, as shown inFIG. 11, a lower connection line62dformed on the substrate60, an oxygen supply layer64formed on the lower connection line62d, an gate insulating layer66formed on the oxygen supply layer64, an upper connection line70uformed on the gate insulating layer66, a protection layer72formed on the upper connection line70u, and a conductive layer20tformed on the protection layer72. The lower connection line62dis a metal layer which is made at the same time and of the same material as the gate electrode62, whereas the upper connection line70uis a metal layer which is made at the same time and of the same material as the source electrode70sand drain electrode70d. The conductive layer20tis made at the same time and of the same material as the pixel electrode20.

In the connecting portion25, a first contact hole25hcpenetrating through the protection layer72, and a second contact hole25hdpenetrating through the protection layer72, the gate insulating layer66, and the oxygen supply layer64, are formed. The upper connection line70uand the conductive layer20tare connected within the first contact hole25hc. In other words, in the contact hole25hc, the conductive layer20tis formed so as to cover the side face of the protection layer72, such that the conductive layer20tand the upper connection line70uare connected at the bottom of the contact hole25hc. The conductive layer20tand the lower connection line62dare connected within the second contact hole25hd. In other words, in the contact hole25hd, the conductive layer20tis formed so as to cover the side faces of the protection layer72, the gate insulating layer66, and the oxygen supply layer64, such that the conductive layer20tand the lower connection line62dare connected at the bottom of the contact hole25hd.

In this manner, the upper connection line70uand the lower connection line62dare electrically connected via the conductive layer20t. Similarly to the first and second construction examples, the side faces of the contact holes25hcand25hdmay be formed in step shapes, whereby line breaking of the conductive layer20tcan be prevented.

Next, other embodiments of the present invention (Embodiments 2 to 5) will be described. In the following description, identical reference numerals will be given to constituent elements which are identical to those in Embodiment 1, and the detailed descriptions thereof will be omitted. Similar effects can be obtained from constituent elements of similar construction.

FIG. 12is a cross-sectional view schematically showing the construction of a TFT10according to Embodiment 2. Unless otherwise described below, the basic construction of the TFT substrate in the present embodiment is identical to that of the TFT substrate100of Embodiment 1.

As shown inFIG. 12, similarly to Embodiment 1, the TFT10includes a gate electrode62, an oxygen supply layer64, a gate insulating layer66, an oxide semiconductor layer68, a source electrode70sand a drain electrode70d, and a protection layer72, which are successively stacked on a substrate60. Furthermore, the TFT10of the present embodiment includes a second oxygen supply layer78formed on the protection layer72. An implementation in which no protection layer72is formed is also encompassed by the TFT10of the present embodiment. The second oxygen supply layer78is formed in the place of the interlayer insulating layer74of Embodiment 1. An interlayer insulating layer74may possibly be formed on the second oxygen supply layer78.

The second oxygen supply layer78is formed by, for example, applying an acrylic resin by a spin coating technique at step (H) in Embodiment 1. Instead of an acrylic resin, an SOG material containing a silicone resin or the like may be used. Similarly to the oxygen supply layer64, the second oxygen supply layer78is a layer made of a material containing H2O, an OR group, or an OH group, and may be made of the material for the oxygen supply layer64described in Embodiment 1.

With the TFT10of Embodiment 2, H2O, an OR group, or an OH group can be supplied to the channel portion of the oxide semiconductor layer68not only from the oxygen supply layer64but also from the second oxygen supply layer78. Therefore, an oxide semiconductor layer68in which defects are better restored than in Embodiment 1 can be obtained, and a highly-reliable semiconductor device with even better TFT characteristics can be obtained.

FIG. 13is a cross-sectional view schematically showing the construction of a TFT substrate100according to Embodiment 3. Unless otherwise described below, the TFT substrate100of the present embodiment is identical in basic construction to the TFT substrate100of Embodiment 1, and may be employed as the TFT substrate100shown inFIG. 1andFIG. 2.

As shown inFIG. 13, the TFT substrate100includes a contact portion85, a line crossing portion87, a TFT portion80, and a Cs portion88. In the contact portion85, a connecting portion25is formed; in the TFT portion80, a TFT10is formed; and in the Cs portion88, a storage capacitor18is formed. The line crossing portion87is a site at which the signal line12as an overlying connection line and the scanning line14as an underlying connection line intersect each other.

The connecting portion25in the contact portion85is basically identical in construction to the connecting portion25of the second construction example according to Embodiment 1. However, instead of the interlayer insulating layer74in the second construction example, a second oxygen supply layer78is stacked. In the connecting portion25of the present embodiment, too, a plurality of layers are formed so as to be located increasingly outside in increasingly upper layers at the side face of the contact hole25hb; as a result, the side face of the contact hole25hbis formed in step shapes, thereby preventing line breaking of the conductive layer20tand insufficient contact between the conductive layer20tand the upper connection line70u. Moreover, since line connection is achieved via a single contact hole, the connecting portion can be reduced in area. The connecting portion25of the first or third construction example according to Embodiment 1 may be formed in the contact portion85.

The line crossing portion87includes a substrate60, a scanning line14formed on the substrate60, an oxygen supply layer64stacked so as to cover the scanning line, a gate insulating layer66formed on the oxygen supply layer64, a signal line12formed on the gate insulating layer66, a protection layer72formed so as to cover the signal line12, and a second oxygen supply layer78formed on the protection layer. By disposing the oxygen supply layer64in between the scanning line14and the signal line12, the parasitic capacitance created between these lines can be reduced.

In the TFT portion80, the TFT10of Embodiment 2 is formed. A drain electrode70dand a pixel electrode20of the TFT10are connected via a contact hole which is formed in the protection layer72and the second oxygen supply layer78.

In the Cs portion88, a storage capacitor electrode62c, the oxygen supply layer64, the gate insulating layer66, a storage capacitor counter electrode70c, the protection layer72, and the second oxygen supply layer78are stacked in this order. The storage capacitor18is constituted by the storage capacitor electrode62c, the opposing storage capacitor counter electrode70c, and the gate insulating layer66sandwiched between these electrodes. Between these electrodes, an aperture in the oxygen supply layer64is formed, with the gate insulating layer66being formed so as to fill this aperture. Since this allows the interspace between both electrodes, it is possible to form a storage capacitor18having a large capacitance in a narrow region in the TFT substrate100of a multilayer construction including the oxygen supply layer64, too.

FIG. 14is a cross-sectional view schematically showing the construction of a TFT10according to Embodiment 4. Unless otherwise described below, the basic construction of the TFT substrate in the present embodiment is identical to that of the TFT substrate100of Embodiment 1.

As shown inFIG. 14, the TFT10includes a gate electrode62formed on a substrate60, a gate insulating layer66stacked so as to cover the gate electrode62, an oxygen supply layer64formed on the gate insulating layer66, an oxide semiconductor layer68formed on the oxygen supply layer64, a source electrode70sand a drain electrode70dformed on the oxide semiconductor layer68, and a protection layer72stacked on these electrodes.

In the TFT10of the present embodiment, the oxygen supply layer64is disposed between the gate insulating layer66and the oxide semiconductor layer68. The oxygen supply layer64has an aperture above the gate insulating layer66over the gate electrode62, in which aperture the oxide semiconductor layer68is in contact with the gate insulating layer66. The portion of the oxide semiconductor layer68that is in contact with the gate insulating layer66is a portion corresponding to the channel portion CH of the TFT10. Any other portion of the oxide semiconductor layer68is directly in contact with the oxygen supply layer64.

In the production of the TFT10, at step (B) described in Embodiment 1, the gate insulating layer66is stacked on the substrate60so as to cover the gate electrode62, by a CVD technique. Next, an oxygen-supplying material is applied on the gate insulating layer66by a spin coating technique or the like. A similar material to what is described in Embodiment 1 is used as the oxygen-supplying material64m. Next, at step (C), the oxygen-supplying material is patterned by a photolithography technique (second masking step), whereby the oxygen supply layer64is completed. During the patterning, an aperture is provided above the gate electrode62.

In the present embodiment, since the oxide semiconductor layer68has a portion which is directly in contact with the oxygen supply layer64, oxygen is supplied from the oxygen supply layer64to the oxide semiconductor layer68with a high efficiency. Therefore, a high-performance TFT whose defects are better restored can be provided.

In a construction where the oxygen supply layer64is directly in contact with the channel portion CH of the oxide semiconductor layer68, a large amount of impurity exists in the oxygen supply layer64, and diffusion of such impurity may possibly lower the reliability of the TFT. Therefore, a layer with little impurity, e.g., a silicon oxide film, is preferably disposed at the site which is in contact with the channel portion CH. According to the present embodiment, the oxide semiconductor layer68in the channel portion CH is not directly in contact with the oxygen supply layer64, but is in contact with the gate insulating layer66, which is a silicon oxide film or the like; therefore, the TFT reliability can be further enhanced.

Furthermore, the gate insulating layer66of silicon oxide, silicon nitride, or the like is formed at the opposite side of the oxygen supply layer64from the oxide semiconductor layer68. The gate insulating layer66of such material has a function of restricting diffusion of H2O or the like. Thus, since greater amounts of H2O, an OR group, or an OH group can be migrated from the oxygen supply layer64to the oxide semiconductor layer68, an oxide semiconductor layer68whose defects are better restored can be obtained.

Next, an organic EL display device1002according to Embodiment 5 of the present invention will be described.

FIG. 15is a cross-sectional view schematically showing the construction of an organic EL display device1002(which may be simply referred to as “display device1002”). As shown in the figure, the display device1002includes a TFT substrate140, a hole transport layer144provided on the TFT substrate140, a light emission layer146provided on the hole transport layer144, and a counter electrode108provided on the light emission layer146. The hole transport layer144and the light emission layer146constitute an organic EL layer. The organic EL layer is partitioned by insulative protrusions147, such that each partitioned organic EL layer defines the organic EL layer of one pixel.

The TFT substrate140basically has the same construction as the TFT substrates100of Embodiments 1 to 4, and includes TFTs10formed on a substrate60. As the TFTs10, the TFTs10which are described in Embodiments 1 to 4 can be used. The TFT substrate140includes an interlayer insulating layer74stacked so as to cover the TFTs10and pixel electrodes109which are formed on the interlayer insulating layer74. Each pixel electrode109is connected to a drain electrode of the TFT10within a contact hole which is formed in the interlayer insulating layer74. The planar construction of the TFT substrate140is basically the same as that shown inFIGS. 2 and 3, and the description thereof is omitted. Note that the TFT substrate140may lack the storage capacitors20.

When a voltage is applied across the organic EL layer by a pixel electrode109and the counter electrode148, holes occurring at the pixel electrode109are sent via the hole transport layer144to the light emission layer146. At the same time, electrons occurring at the counter electrode148move to the light emission layer146, and light emission occurs in the light emission layer146through recombination of such holes and electrons. Desired displaying is achieved by controlling light emission in the light emission layer146for each pixel by using the TFT substrate140, which is an active matrix substrate.

Known materials and structures may be employed for the materials of the hole transport layer144, the light emission layer146, and the counter electrode148, and their layer structures. It is possible to provide a hole injection layer between the hole transport layer144and the light emission layer146for an improved hole injection efficiency. In order to enhance the efficiency of light emission and achieve a high electron injection efficiency into the organic EL layer, it is preferable to use a material with a high transmittance and a small work function for the counter electrode148.

Since TFTs10as described in Embodiments 1 to 4 are used in the organic EL display device1002of the present embodiment, effects similar to those described in Embodiments 1 to 4 are obtained. According to the present embodiment, an organic EL display device1002capable of high-performance displaying can be provided with a good production efficiency.

INDUSTRIAL APPLICABILITY

The present invention is suitably used for a semiconductor device having thin film transistors, a liquid crystal display device having thin film transistors on a TFT substrate, and a display device such as an organic EL display device.

REFERENCE SIGNS LIST