Semiconductor modules with semiconductor dies bonded to a metal foil

A method of manufacturing semiconductor modules includes providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer, attaching a first surface of a plurality of semiconductor dies to the metal foil prior to structuring the metal foil, and encasing the semiconductor dies attached to the metal foil in an electrically insulating material. The metal layer and the metal foil are structured after the semiconductor dies are encased with the electrically insulating material so that surface regions of the electrically insulating material are devoid of the metal foil and the metal layer. The electrically insulating material is divided along the surface regions devoid of the metal foil and the metal layer to form individual modules.

TECHNICAL FIELD

The present application relates to semiconductor modules, in particular manufacturing of semiconductor modules having semiconductor dies bonded to a metal foil.

BACKGROUND

Recent advancements in power semiconductor die (chip) packaging technology utilize chip embedding concepts. Standard packaging processes such as wire or clip bonding, as well as common molding techniques, are replaced with galvanic processes. The semiconductor dies also are protected by a laminate. The results are a significantly reduced package footprint, package resistance and inductance, as well as low thermal resistance. For example, dies are typically soldered to structured lead frames. During the panel lamination process, several lead frames, together with FR4 laminate, are laminated together.

Due to aligning tolerances between the lead frames and non-linear shrinkage/expansion during the lamination process caused by aligning fixing pins that keep the lead frames in position, optical measurement of die and lead frame positions and corresponding data file corrections are required. Also, warpage of the dies, lead frames and panel is relatively high due to CTE (coefficient of thermal expansion) mismatch and thickness differences between the lead frames and dies, causing differences in micro-via height and challenges in the lamination and micro-via plating processes.

Furthermore, the die attach solder is conventionally deposited on the wafer back surface before die singulation (separation) in case of diffusion solder, or is dispensed on the die pad of the lead frames or stencil printed to the wafer back surface as well. Dicing through a thick metal layer on the backside of a wafer is challenging and reduces dicing quality, lowers throughput and reduces the life time of the dicing blade. Also, part of the solder on the die backside is squeezed out during the bonding process. This ‘squeeze out’ of the die backside solder is not uniform, not easy to control and not repeatable.

SUMMARY

According to an embodiment of a method of manufacturing semiconductor modules, the method comprises: providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer; attaching a first surface of a plurality of semiconductor dies to the metal foil prior to structuring the metal foil; encasing the semiconductor dies attached to the metal foil in an electrically insulating material; structuring the metal layer and the metal foil after the semiconductor dies are encased with the electrically insulating material so that surface regions of the electrically insulating material are devoid of the metal foil and the metal layer; and dividing the electrically insulating material along the surface regions devoid of the metal foil and the metal layer to form individual modules.

According to an embodiment of a semiconductor module, the semiconductor module comprises a metal composite substrate including a metal layer attached to a first surface of a structured metal foil. The structured metal foil has a second surface opposite the first surface and is thinner than the metal layer. The metal layer has tapered sidewalls extending outward from the first surface of the structured metal foil. The semiconductor module further comprises at least one semiconductor die having a first surface attached to the second surface of the structured metal foil, a laminate attached to the second surface of the structured metal foil and encasing the at least one semiconductor die, and a structured metal layer on a surface of the laminate facing away from the metal composite substrate. The structured metal foil has sidewalls extending outward from the laminate. The sidewalls of the structured metal foil are uncovered by the laminate and aligned with the sidewalls of the metal layer of the metal composite substrate. The laminate has an edge extending between opposing first and second main surfaces of the laminate. The edge of the laminate is uncovered by metal.

According to an embodiment of a method of attaching semiconductor dies to a metal composite substrate, the method comprises: providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer; coating a surface of the metal foil opposite the metal layer with solder of a lower melting point than the metal foil and the metal layer; diffusion soldering a first surface of a plurality of semiconductor dies to the metal foil via the solder, including isothermal solidification of the solder to high melting point phases; and encasing the semiconductor dies in an electrically insulating material after the first surface of the semiconductor dies is diffusion soldered to the metal foil.

DETAILED DESCRIPTION

According to some embodiments described herein, a relatively thick metal composite substrate is provided for bonding semiconductor dies to a thin metal foil of the metal composite substrate using a batch die attach process. A metal layer can be used to structure the metal foil. The metal foil can also be structured before optional solder coating, bonding and lamination. According to other embodiments described herein, the die attach solder is deposited on the metal foil instead of the dies, eliminating the need to singulate (separate) dies with a thick backside metallization. The die attach solder deposited on the metal foil can be used as a hard mask to pattern the unstructured metal foil, and the solder can be removed if desired by a simple selective etching process after the die attach process. These embodiments can be combined at least to the extent that such combinations are not mutually exclusive.

FIG. 1illustrates a cross-sectional view of an embodiment of a semiconductor module100. The semiconductor module100comprises a metal composite substrate102including a metal layer104such as an aluminum layer attached to a first surface105of a structured metal foil106such as a copper foil. The structured metal foil106has a second surface107opposite the first surface105and is thinner than the metal layer104. For example, the metal layer104can have a thickness (T1) between 30 μm and 400 μm and the structured metal foil106can have a thickness (T2) between 3 μm and 100 μm. The metal layer104has tapered sidewalls108extending outward from the first surface105of the structured metal foil106.

The semiconductor module100further comprises at least one semiconductor die110having a first surface111attached to the second surface107of the structured metal foil106. This region of connection/attachment between the dies110and the structured metal foil106is labeled ‘DAR’ inFIG. 1, which is shorthand for ‘die attach region’. Any type of semiconductor die110can be included in the module100, such as power semiconductor dies like power MOSFETs (metal oxide semiconductor field effect transistors) or IGBTs (insulated gate bipolar transistors), logic dies (e.g. driver, controller) that are bonded to the metal foil106e.g. by an insulating adhesive (no back side connection), etc.

The semiconductor module100also comprises a dielectric layer112such as a laminate, resin layer, etc. attached to the second surface107of the structured metal foil106and a structured metal layer114on a surface113of the dielectric layer112facing away from the metal composite substrate102. The dielectric layer112encases the semiconductor dies110.

The structured metal foil106has sidewalls116extending outward from the dielectric layer112. The sidewalls116of the structured metal foil106are uncovered by the dielectric layer112and aligned with the sidewalls108of the metal layer104of the metal composite substrate102. The dielectric layer112has an edge region118where the edge120of the dielectric layer112extends between opposing first and second main surfaces113,115of the dielectric layer112. The edge120of the dielectric layer112is uncovered by metal.

One or more first micro-via connections122extend through the dielectric layer112from a second surface117of the dies110opposite the first surface111to the structured metal layer114on the surface113of the dielectric layer112facing away from the metal composite substrate102. The first micro-via connections122provide points of external electrical contact for terminals124at the second surface117of the dies110.

One or more second micro-via connections126extend through the dielectric layer112from the structured metal foil106to the structured metal layer114on the surface113of the dielectric layer112facing away from the metal composite substrate102. The second micro-via connections126provide points of external electrical contact for terminals at the first surface111of the dies110. If one or more of the dies110do not have a terminal at the first surface111of the dies110(e.g. in the case of lateral transistor dies), then the second micro-via connections126can be omitted. Whether a terminal is provided at the first surface111of the dies110depends on the type of die, and therefore such terminals are not shown inFIG. 1for ease of illustration. The metal layer104of the metal composite substrate102can be structured as shown inFIG. 1and act as a heat sink during operation of the dies110, dissipating heat from the first surface111of the dies110through the structured metal foil106.

FIG. 2, which includesFIGS. 2A through 2K, illustrates an embodiment of a method of manufacturing a semiconductor module of the kind illustrated inFIG. 1.FIG. 2Ais a top-down plan view of a metal composite substrate panel200including metal foil strips202on a metal layer204. In general, the metal foil can cover the entire metal layer204and can also be structured. The metal foil strips202are thinner than and comprise a different material than the metal layer204. In one embodiment, the metal layer204is an aluminum layer having a thickness between 50 μm and 200 μm and the metal foil strips202are copper foil strips each having a thickness between 3 μm and 100 μm. Copper foils can be plated, coated, sputtered, etc. onto an aluminum layer. In one example the substrate200is a Cu/Al composite substrate including Cu foil strips202having a thickness of about 9 μm and an Al layer204having a thickness of about 100 μm.

The metal foil strip arrangement shown inFIG. 2Aallows for a higher package density because the entire production panel200can be used for assembly. Also, the metal foil strip arrangement allows for a higher maximum current for testing the usable area of the modules where the dies are attached. The mechanical properties of the metal composite substrate panel200formed by the metal foil strips202and the metal layer204can be adjusted by optimizing the material thicknesses. The metal composite structure of the panel200yields a more stable panel and also the sub-processes are more feasible and reliable.FIGS. 2B through 2Kare respective cross-sectional views taken along the line labeled A-A′ inFIG. 2Aat different stages of the manufacturing method.

InFIG. 2B, a first surface205of a plurality of semiconductor dies206is attached to the illustrated metal foil202prior to structuring of the metal foil202. The first surface205of the dies can have one or more terminals or be devoid of terminals as previously described herein, and therefore terminals are not shown at the first surface205of the dies206inFIG. 2for ease of illustration. The second surface207of the dies206opposite the first surface has one or more terminals208.

By attaching the dies206to a one-piece metal foil202such as a copper foil, subsequent lamination results in relatively linear shrinkage during the lamination process which can be more easily modeled to calculate a compensation factor. The metal foil202is eventually structured e.g. by etching, but after the dies206are first attached to the foil202. In one embodiment, the first surface205of the dies206is the backside of the dies206. The dies206can be attached to the metal foil202using any standard die attach material210and process such as soldering, diffusion soldering, sintering, gluing, etc. In the case of diffusion soldering, which is described in more detail later herein in connection withFIGS. 3 through 8, the metal foil202can be a copper foil. Other materials can be used such as nickel alloys like NiAu or NiCu for the metal foil202, or any other metal materials compatible diffusion soldering.

In each case, the dies206can be diffusion soldered to the metal foil202in parallel as a batch process at a temperature less than 300° C. e.g. about 250° C. Diffusion soldering is typically performed serially (i.e. one die at a time) at a higher temperature of about 350° C. in order to reduce the overall die attach time. Diffusion soldering at a lower temperature of 300° C. or less results in slower phase formation (i.e. more time is needed for high melting point phases to form), but less warpage results because the die attach process temperature is significantly lower. Diffusion soldering the dies206to the metal foil202in parallel as part of a batch process reduces substantially the overall die attach process time compared to conventional serial die attach processes even though the die attach temperature is lower in the batch process. Alignment marks and jig holes can be manufactured in the metal foil202before die attach e.g. using a laser process such as UV-laser. Alignment marks and jig holes are not shown inFIG. 2for ease of illustration.

By using a metal composite substrate200where the semiconductor dies206are attached to a metal foil202using a batch die attach process as shown inFIG. 2B, heat sink structures can be manufactured from the metal layer204of the metal composite substrate202e.g. with a selective etching process after lamination and patterning processes of the front surface. Some favorable characteristics of the resulting structure is that heat sinks are in metallurgical contact with the metal foil202where the dies206are attached and the heat sinks can be manufactured with an etching process after lamination and patterning of the front surface is done. Also, attaching the dies206to a relatively thin metal foil202(e.g. between 3 μm and 100 μm thick) allows the dies206to deform the metal foil202and therefore provide a stress release mechanism which is not possible for conventional thick Cu foils that do not deform during die attach.

InFIGS. 2C and 2D, the semiconductor dies206attached to the metal foil202are encased in an electrically insulating material212. According to the embodiment shown inFIGS. 2C and 2D, the electrically insulating material212is a laminate. In the case of lamination, the panel200can be placed e.g. in a jig table using a laser-structured prepregs214and Cu or Cu/Al top foil216, can be structured with drilling, routing, punching, etc. or a material that needs no structuring such as polymer/resin films (or even printing, coating etc.) can be used. A prepreg comprises pre-impregnated composite fibers where a matrix material, such as epoxy, is already present. The lamination process can be performed in a standard PCB (printed circuit board) vacuum press system. During the press cycle, the prepreg resin214melts and fills the surroundings of the components206before the resin214fully crosslinks. Other electrically insulating materials212can be used to encase the semiconductor dies206such as a molding compound, epoxy, etc. The laminated structure can include a metal layer216on the surface213of the laminate212facing away from the metal composite substrate200. In one embodiment, this metal layer216comprises copper.

InFIGS. 2E and 2F, first micro-via openings218are formed in the electrically insulating material212which extend from the surface213of the electrically insulating material212facing away from the metal composite substrate200to the second surface207of the dies206i.e. the surface207of the dies206facing away from the metal composite structure200. In the case of the electrically insulating material212being a laminate, the first micro-via openings218can be formed in a two-step process or with a direct laser drilling process. The two-step process includes first etching openings220into the metal layer216on the surface213of the laminate212facing away from the metal composite substrate200to form a mask. The laminate resin is then removed where exposed by the openings220in the metal layer216to form the first micro-via openings218in the electrically insulating material212e.g. using a CO2 laser.

InFIG. 2G, the first micro-via openings218are filled e.g. using a direct metallization process or an electroless and electrochemical plating process or remain un-filled but plated or coated with an electrically conductive material. In each case, the resulting first micro-vias connections222extend through the electrically insulating material212from the terminals208at the second surface207of the dies206to the metal layer216on the surface213of the electrically insulating material212facing away from the metal composite substrate200. Second micro-via connections can be similarly formed which extend through the electrically insulating material212from the metal foil202to the metal layer216on the surface213of the electrically insulating material212facing away from the metal composite substrate200e.g. as shown inFIG. 1. The second micro-via connections can connect one or more terminals at the first surface205of the dies206to the metal layer216on the surface213of the electrically insulating material212facing away from the metal composite substrate200. Such second micro-via connections may not be needed e.g. in the case of a lateral transistor die in which all terminals208of the die206are provided at the second surface207of the die206.

InFIG. 2H, the metal layer204of the metal composite substrate200is structured (patterned) to form heat sink structures224. In one embodiment, a photoresist226is laminated/coated on the metal layer204after the micro-via connections222are formed. The photoresist226is exposed, developed and etched to expose regions of the metal layer204. The exposed regions of the metal layer204are then removed e.g. using a highly selective etching process in the case of an aluminum metal layer to form the desired heat sink structures224which have tapered sidewalls225.

InFIG. 2I, a photoresist228is laminated/coated on the metal layer216disposed on the surface213of the electrically insulating material212facing away from the metal composite substrate200. The photoresist228is then exposed and developed to form a mask having a defined structure.

InFIG. 2J, the metal layer216on the surface213of the electrically insulating material212facing away from the metal composite substrate200is structured by etching the metal layer216using the developed photoresist228as a mask. The metal foil202at the opposite side of the structure is also etched using the previously structured metal layer204of the metal composite substrate200as a mask. That is, the heat sink structures224previously formed from the metal layer204of the metal composite substrate200expose regions of the metal foil202which are removed. The metal foil202and the metal layer216on the surface213of the electrically insulating material212facing away from the metal composite substrate200can be structured using the same etchant if both comprise the same material such as copper.

At this point in the manufacturing method, the metal layer204and the metal foil202of the metal composite substrate200have both been structured after the semiconductor dies206are encased with the electrically insulating material212so that surface regions230of the electrically insulating material212are devoid of the metal foil202and the metal layer204of the composite substrate200and devoid of the metal layer216on the surface213of the electrically insulating material212facing away from the metal composite substrate200.

InFIG. 2K, the electrically insulating material212is divided along the surface regions230devoid of the metal structures202,204,216to form individual modules. This can include cutting the panel200to a strip size, coating the surface of the resulting strips with solder resist on the front side and separating the individual modules of each strip using a laminate dicing process.

The order of the process flow described in connection withFIG. 2can be different. Also, additional build-up layers can be laminated to the top surface213of the electrically insulating material212. The prepregs214can be replaced e.g. with structured laminates and resin films (e.g. bonding film) that bond the substrate200, the structured laminate and the metal layer216together. The exposed (bottom) surface of the metal layer204of the metal composite substrate200can be protected e.g. with a thin laminate layer (not shown) that is placed on the backside e.g. during the batch die attach process. A Cu/Al composite substrate is only one option. Other metal foils and/or composite foils can also be used. Alternative soldering processes or materials also can be used to attach the dies206to the metal foil202. For example a diffusion soldering process can be employed as previously described with reference to the die attach process, the result of which is illustrated inFIG. 2B.

Diffusion soldering is a hybrid of diffusion bonding and soldering. The principle of diffusion soldering is to run a minute volume of an interlayer of low melting point solder such as In, Sn or InSn into a joint between components that are pressed together and heated to form a liquid filler that solidifies by conversion to high melting point phases through isothermal reaction with the substrates. The liquid filler forms because the melting point of the interlayer solder is exceeded or due to a eutectic reaction between the low- and high-melting point components. The isothermal solidification of the liquid filler forms strong bonds at a relatively low temperature which then remain solid at much higher temperatures. The term ‘lower melting point’ as used herein with reference to the interlayer die attach solder used in the diffusion soldering process means that the solder has a lower melting point than the components being joined. The joint produced through inter-diffusion or reaction diffusion does not re-melt unless heated to the temperature at which the high melting point phases melt. Conventional diffusion soldering processes for semiconductor components involve applying the die attach solder to the wafer backside prior to die singulation (separation), which adversely impacts the wafer singulation process by requiring that a thick wafer backside metallization be cut through as part of the singulation process.

FIG. 3illustrates an embodiment of a method attaching semiconductor dies to a metal composite substrate e.g. of the kind previously described herein with reference toFIGS. 1 and 2, using a diffusion soldering process where the die attach solder is applied to the metal composite substrate instead of the dies. The method includes providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer (Block300). The metal foil can comprise Cu, Ni, Ag, etc. The surface of the metal foil opposite the metal layer is then coated with a die attach solder of a lower melting point than the metal foil and the metal layer (Block302). The problem of solder ‘squeeze out’ is avoided by covering the entire or most of the metal foil with the die attach solder.

The die attach solder can be structured (Block306) or remain unstructured (Block308) prior to die attach. In the case of structuring the die attach solder, the structured solder can be used as a mask to pattern the underlying metal foil (Block310) and the dies are then placed on the structured die attach material (Block312). In the case of the die attach solder remaining unstructured prior to die attach, the dies are placed on the unstructured die attach material (Block314).

In either case (structured or unstructured die attach solder), the dies are then attached to the metal foil by diffusion soldering whereby the dies and the metal composite substrate are pressed together and heated to form a liquid filler from the die attach solder that solidifies by conversion to high melting point phases through isothermal reaction with the dies and the metal composite substrate (Block316). Excess solder such as the unreacted part of the solder i.e. the part of the solder that does not bond with the dies can be removed from the metal foil (Block318) e.g. by selective etching. The module assembly process then continues (Block320) e.g. by encasing the semiconductor dies in an electrically insulating material, forming micro-via connections and module singulation as previously described herein.

FIGS. 4 and 5illustrate different stages of the diffusion soldering method shown inFIG. 3, for structured and unstructured die attach solders.FIG. 4, which includesFIGS. 4A through 4G, illustrates an embodiment of the diffusion soldering method in which the die attach solder remains unstructured prior to die attach.FIG. 5, which includesFIGS. 5Athrough5I, illustrates an embodiment of the diffusion soldering method in which the die attach solder is structured prior to die attach.

In the case of the die attach solder remaining unstructured prior to the die attach process, a metal composite substrate400including a metal foil402attached to a metal layer404is provided and the surface401of the metal foil402opposite the metal layer404is coated with a die attach solder406of a lower melting point than the metal foil402and the metal layer404as shown inFIG. 4A. The metal foil402is thinner than and comprises a different material than the metal layer404. For example, the metal layer404can be an aluminum layer having a thickness between 50 μm and 200 μm and the metal foil402can be a copper foil having a thickness between 3 μm and 100 μm. Other materials can be used such as nickel alloys like NiAu or NiCu for the metal foil402, or any other metal materials compatible diffusion soldering. Any die attach solder406suitable for diffusion soldering can be used such as Sn, In, Zn or a solder alloy e.g. AuSn, SnAg, InAg, InSn or SAC solder, J-alloy or another sufficiently low melting metal or solder alloy.

In the case of structuring the die attach solder before the die attach process, a metal composite substrate500including a metal foil502attached to a metal layer506is provided and the surface501of the metal foil502opposite the metal layer504is coated with a die attach solder506of a lower melting point than the metal foil502and the metal layer504as shown inFIG. 5A. As described above in connection withFIG. 4A, the metal foil502is thinner than and comprises a different material than the metal layer504. For example, the metal layer504can be an aluminum layer having a thickness between 50 μm and 200 μm and the metal foil502can be a copper foil having a thickness between 3 μm and 100 μm. Other materials can be used such as nickel alloys like NiAu or NiCu for the metal foil502, or any other metal materials compatible diffusion soldering. Any die attach solder506suitable for diffusion soldering can be used such as Sn, In, Zn or a solder alloy e.g. AuSn, SnAg, InAg, InSn or SAC solder, J-alloy or another sufficiently low melting metal or solder alloy. Prior to die attach, the die attach solder506is structured e.g. using a photolithography process and etching as shown inFIG. 5B. The structured solder506is then used as a hard mark for structuring the metal foil502beneath the solder506e.g. by etching as shown inFIG. 5C.

In either embodiment ofFIG. 4 or 5, one or more of a sinter layer, a solder paste and glue can be applied to the surface401/501of the metal foil402/502opposite the metal layer404/504before the semiconductor dies are diffusion soldered to the metal foil402/502. Such additional layers are not shown inFIGS. 4 and 5for ease of illustration.

InFIGS. 4B and 5D, semiconductor dies408/508are attached to the metal foil402/502at a first surface407/507of the dies408/508by diffusion soldering whereby the dies408/508and the metal composite substrate400/500are pressed together and heated to form a liquid filler from the die attach solder406/506that solidifies by conversion to high melting point phases through isothermal reaction with the dies408/508and the metal composite substrate400/500. In one embodiment, a metallization410/510is applied to the first surface407/507of the semiconductor dies408/508before the first surface407/507of the dies408/508is diffusion soldered to the metal foil402/502. For example, a backside metallization410/510such as Ti/Cu/Ag, Al/Ti/Cu/Ag or Al/Ti/NiV/Ag can be applied to the first surface407/507of the dies408/508and bonded to the die attach solder406/506by diffusion soldering. The opposite (second) surface409/509of the dies408/508faces away from the metal foil402/502and includes one or more terminals412/512such as bond pads.

InFIGS. 4C and 5E, excess solder406/506is removed from the surface401/501of the metal foil402/502to which the dies408/508are diffusion soldered e.g. using an etching process. The excess part of the die attach solder406/506uncovered by the dies408/508does not react i.e. bond with the dies408/508as part of the diffusion soldering process. As such, these unreacted parts of the solder406/506can be removed from the metal foil402/502after the dies408/508are diffusion soldered to the metal foil402/502and before the dies408/508are encased in an electrically insulating material.

InFIGS. 4D and 5F, the semiconductor dies408/508are encased in an electrically insulating material414/514after being diffusion soldered to the metal foil402/502. In one embodiment, the electrically insulating material414/514is realized by a lamination process e.g. as described previously herein in connection withFIGS. 2C and 2D. The prepregs used in a standard lamination process can be replaced e.g. with structured laminates and resin films (e.g. bonding film) that bond the components together. Other electrically insulating materials414/514can be used to encase the semiconductor dies408/508such as a molding compound, epoxy, etc. In each case, a metal layer416/516such as a copper layer can be provided on the surface413/513of the electrically insulating material414/514facing away from the metal composite substrate400/500.

InFIGS. 4E and 5G, first micro-via connections418/518are formed which extend through the electrically insulating material414/514from the terminals412/512at the second surface409/509of the dies408/508to the metal layer416/516on the surface413/513of the electrically insulating material414/514facing away from the metal composite substrate400/500. Optional second micro-via connections420/520extend through the electrically insulating material414/514from the metal foil402/502to the metal layer416/516on the surface413/513of the electrically insulating material414/514facing away from the metal composite substrate400/500. The micro-via connections418/518,420/520can be manufactured using standard photolithography, etching and laser drilling processes e.g. as described previously herein in connection withFIGS. 2E, 2F and 2G.

InFIGS. 4F and 5H, the metal layer404/504of the metal composite substrate400/500is patterned using standard photolithography and selective etching processes. The structured metal layer404/504can be used as heat sinks in the final module products, or removed after structuring of the metal foil402/502.

InFIGS. 4G and 5I, the metal layer416/516on the surface413/513of the electrically insulating material414/514facing away from the metal composite substrate400/500is structured e.g. using standard photolithography and selective etching processes. In the case of the metal foil402/502not being previously structured, the metal foil402/502can also be structured now using the structured metal layer404/504of the metal composite substrate400/500as a mask. The structured metal layer404/504of the metal composite substrate400/500can be removed after structuring of the metal foil402/502, or can remain as heat sink structures422/522. The electrically insulating material414/514can be divided along surface regions devoid of the metal foil402/502and the metal layers404/504,416,516to form individual modules e.g. as previously described herein in connection withFIGS. 2J and 2K.

FIG. 6, which includesFIGS. 6A through 6H, illustrate different stages of yet another embodiment of the diffusion soldering method shown inFIG. 3.

InFIG. 6A, a metal composite substrate600such as a Cu/Al substrate is provided that includes a metal foil602attached to a metal layer604. The metal layer604underlying the metal foil602is used as a temporary carrier during the manufacturing process according to this embodiment. The metal foil602is thinner than and comprises a different material than the metal layer604. For example, the metal layer604can be an aluminum layer having a thickness between 50 μm and 200 μm and the metal foil602can be a copper foil having a thickness between 3 μm and 100 μm. Other materials can be used such as nickel alloys like NiAu or NiCu for the metal foil602, or any other metal materials compatible diffusion soldering.

InFIG. 6B, a die attach solder606is applied to the exposed surface601of the metal foil602. The solder material606can be e.g. Sn, In, Zn or a solder alloy e.g. AuSn, SnAg, InAg, InSn or SAC solder, J-alloy or another sufficiently low melting metal or solder alloy. In addition to covering the exposed surface601of the metal foil602with the solder material606, one or more additional materials (not shown for ease of illustration) such as glue, nano-paste, a sintering material, etc. can also be applied to the surface601of the metal foil602.

InFIG. 6C, the die attach solder606is structured e.g. using standard photolithography and etching processes. The structured die attach solder606can be used as a hard mark for structuring the metal foil602beneath the solder606. Alternatively, the metal foil602can be structured before application of the solder606to the metal composite substrate600.

InFIG. 6D, semiconductor dies608(only one is shown for ease of illustration) with a backside metallization610such as Ti/Cu/Ag, Al/Ti/Cu/Ag or Al/Ti/NiV/Ag are bonded to the die attach solder606via diffusion soldering as previously described herein. In general the backside metallization610can include any suitable material system for soldering, including a contact layer for providing electrical contact with a semiconductor material (e.g. Si, SiN, GaAs, GaN, etc.) a barrier layer (e.g. Ti, TiW, W, etc.) and one or more functional layers (Cu, Ni, Ag, etc.) and on or several layers (e.g. Cu/Ag, etc.) to provide electrical contact formation with the die attach material606. The dies608have terminals612disposed at the second surface609of the dies608opposite the first surface607. The first surface607of the dies is diffusion soldered to the metal foil602. The metal foil602can be previously structured as shown inFIG. 6D, or remain unstructured at this point in the process.

InFIG. 6E, excess solder606is optionally removed from the top surface601of the metal foil602e.g. using an etching process as previously described herein in connection withFIGS. 4C and 5E.

InFIG. 6F, layup and lamination with a laminate614and topside metallization616can be done using standard layup and lamination processes and materials as previously described herein e.g. in connection withFIGS. 4D and 5F.

InFIG. 6G, the metal layer604of the metal composite substrate600is removed e.g. with a selective etching process. Micro-via connections618,620are also formed e.g. using standard photolithography, etching, laser drilling and plating processes as previously described herein e.g. in connection withFIGS. 4E and 5G.

InFIG. 6H, the topside metal layer616on the electrically insulating material laminate614is structured e.g. using standard photolithography and selective etching processes. In case the metal foil602was not structured in advance, the metal foil602can be structured during the same process step by applying a photoresists as masks.

FIG. 7illustrates a cross-sectional view of an embodiment of a semiconductor module700manufactured in accordance with the method ofFIG. 3. The semiconductor module700comprises a metal composite substrate702including a metal layer704such as an aluminum layer attached to a first surface705of a structured metal foil706such as a copper foil. The structured metal foil706has a second surface707opposite the first surface705and is thinner than the metal layer704. For example, the metal layer704can have a thickness between 50 μm and 200 μm and the metal foil706can have a thickness between 3 μm and 100 μm. The metal layer704has tapered sidewalls708extending outward from the second surface707of the structured metal foil706.

The semiconductor module700further comprises at least one semiconductor die710diffusion soldered to the second surface707of the structured metal foil706in accordance with the method ofFIG. 3. That is, a die attach solder712is applied to the surface707of the metal foil706to which each die710is to be attached. The die(s)710are then pressed against the metal foil706under pressure and temperature, so that each die710is diffusion bonded to the metal foil706via high melting point phases formed by isothermal solidification of the die attach solder712as previously described herein. The surface of each die710diffusion soldered to the metal foil706can have a metallization711as previously described herein.

FIG. 7includes an exploded view of the interface between one die710and the metal foil706in a corner region714of the module700. According to this embodiment, unreacted parts716of the die attach solder712are not removed from the metal foil706before diffusion soldering the dies710to the metal foil706. Any type of semiconductor die710can be diffusion soldered to the metal foil702, such as power semiconductor dies like power MOSFETs or IGBTs, one or more logic dies (e.g. driver, controller), etc. A laminate718such as FR4 is attached to the second surface707of the structured metal foil706. A structured metal layer720is provided on the laminate718. The laminate718encases the semiconductor dies710.

The structured metal foil706has sidewalls722extending outward from the laminate718. The sidewalls722of the structured metal foil706are uncovered by the laminate718and aligned with the sidewalls708of the metal layer704of the metal composite substrate702. The laminate718has an edge724extending between the opposing main surfaces719,721of the laminate718. The edge724of the laminate718is uncovered by metal.

One or more first micro-via connections726can extend through the laminate718from die terminals728at a surface of the dies710opposite the structured metal foil706to the structured metal layer720on the surface719of the laminate718facing away from the metal composite substrate702. The first micro-via connections726provide points of external electrical contact for the die terminals728at the surface of the dies710opposite the metal composite substrate702.

One or more second micro-via connections730extend through the laminate718from the structured metal foil706to the structured metal layer720on the surface719of the laminate718facing away from the metal composite substrate702. The second micro-via connections730provide points of external electrical contact for terminals (if provided) at the surface of the dies710diffusion soldered to the metal foil706. If one or more of the dies710do not have a terminal at this surface (e.g. in the case of lateral transistor dies), then the second micro-via connections730can be omitted. The metal layer704of the metal composite substrate702acts as a heat sink during operation of the dies710, dissipating heat from the dies710through the structured metal foil706.

FIG. 8illustrates a cross-sectional view of another embodiment of a semiconductor module800manufactured in accordance with the method ofFIG. 3. The embodiment shown inFIG. 8is similar to the embodiment shown inFIG. 7, however, the unreacted parts716of the die attach solder712are removed from the metal foil706before diffusion soldering of the dies710to the metal foil706as shown in greater detail in the exploded view ofFIG. 8.