Seals used for testing on an integrated circuit tester

A system for reducing condensation during testing of an integrated circuit is disclosed. An exemplary embodiment includes two seals which close both ends of an enclosed channel formed when the load board is secured to the device tester. Clean dry air with a pressure greater than that of the environment is feed into the enclosed channel and is trapped because of the seals.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuit testing.

BACKGROUND

FIG. 1is an exploded perspective view showing a conventional ATE system100, which represents a typical system utilized to test packaged integrated circuits (ICs) prior to sale to an end user. Conventional ATE system100includes an IC test signal generator (device tester)110(partially shown), a load board120, a docking plate130, and an automated handler (not shown) for mounting IC DUTs onto load board120. Briefly described, the handler associated with ATE system100moves an IC DUT from a shipping tray (not shown) onto a test socket127that is mounted on load board120. Alternatively, this process may be done by hand (i.e., manually). Testing is then carried out by transmitting electrical signals from device tester110to an IC DUT through test socket127, and processing test data returned from the IC DUT in response to the applied test signals. This testing process is typically used to identify non-functional ICs.

Referring to the lower portion ofFIG. 1, device tester110is an expensive piece of computing equipment that includes a base unit (partially shown) having a test surface112located at one end. Extending from test surface112are a first platform140having a first group113of compressible test (“pogo”) pins arranged in a first column, and a second platform150having a second group115of compressible test pins arranged in a second column that is parallel to the first column such that a central channel117is defined between first and second platforms140and150. A blow-up of an example set of pogo pins is shown as113-1. Not shown in order to simplify the description are the seals which surround the compressible test pins113and115(see for example, seals142and152ofFIG. 5). Also extending from test surface112are several connection bolts119that are used to secure load board120to device tester110. An example of conventional device testers that are consistent with device tester110is the Integra J750 Test Family, which is produced by Teradyne, Inc. of Boston Mass., USA.

Located above device tester110is load board120, which is a printed circuit board (PCB) having a lower surface121facing test surface112and an upper surface122facing away from test surface112, and includes a first plurality of test contacts123, a second plurality of test contacts125, and one or more test sockets127. First test contacts123are arranged in a first column, and each test contact includes a contact pad located on lower surface121such that each contact pad abuts the tip of a corresponding compressible pin of first group113when load board120is mounted onto device tester110. Similarly, contact pads of second test contacts125are arranged on lower surface121in a second column such that each test contact abuts the tip of a corresponding compressible pin of second group115. Test sockets127are mounted on upper surface122, and include pins or other contact structures that are connected to corresponding first and second test contacts123and125by conductive traces (wires)128, which are formed in accordance with known practices. Finally, load board120is secured to device tester110using connectors129that receive the ends of bolts119and hold load board120such that the compressible pins of first group113are firmly pressed against the contact pads of first test contacts123, and such that the compressible pins of second group115are firmly pressed against the contact pads of second test contacts125.

Shown above load board120is docking plate130, which is a rigid (e.g., aluminum) structure that is fixed (e.g., screwed) to upper surface122of load board120, and includes openings135that mount over test sockets127.

FIG. 2is a cross-sectional side view showing conventional ATE system100with docking plate130mounted on load board120, and load board120fastened to device tester110. Note that compressible test pins of each group113and115are electrically connected to the DUT via corresponding conductive traces128, and receive test signals from a central processing unit (CPU)210. As indicated in the lower portion ofFIG. 2, compressible pin groups113and115are mounted on a support plate220that has sufficient strength to resist the downward force from the compressible pins of groups113and115when load board is fastened onto the ends of bolts119. As indicated previously, the seals surrounding compressible pin groups113and115are not shown in order to simplify the explanation.

As indicated at the top ofFIG. 2, during testing, docking plate130functions to prevent bending of load board120, which is subjected to a downward force P that is needed to press a DUT against test socket127. Downward force P is used to provide the necessary connection between the contact structures of test socket127and contact structures (e.g., solder balls or bumps) formed on a lower surface of the DUT.

Low-temperature semiconductor device testing is often used to verify the conformance of a semiconductor device such as an IC with military specifications. During low-temperature testing, semiconductor devices are placed in a special low-temperature box containing a cool dry environment maintained at a temperature in the range of, e.g., 0° C. to −58° C., and a handler that moves the cooled semiconductor devices between a loading tray and a test socket that is coupled to a device tester.

FIG. 3is an exploded perspective view and a simplified cross-sectional side view showing a portion of a conventional low-temperature testing arrangement300that utilizes test system100(described above). The conventional low-temperature testing arrangement300generally includes device tester110, a low-temperature handler system350, and load board120, which connect between device tester110and handler system350during low-temperature testing procedures. Low-temperature handler system350includes an insulated box352connected to a cooling system (not shown), and a device handling mechanism (handler)355mounted inside of insulated box352. An opening357is provided in a side wall of insulated box352through which test sockets127of handler board120are exposed to the cool dry environment maintained inside insulated box352. Device handling mechanism355(partially shown) is an expensive precise robot including an arm for moving a DUT from a storage location (e.g., a shipping tray) to the test socket127during test procedures. The storage location is also inside of insulated box352so that the DUTs are maintained at a desired low temperature throughout the test procedures. Conventional systems meeting the description of low-temperature handler system350are produced, for example, by Delta Design of San Diego, Calif., USA.

A major problem associated with conventional low-temperature testing arrangement300is that, during low temperature testing, the low temperature of the DUT can cause condensation to form on the back surface121of load board120. The potential for condensation is particularly high on the back surface121of load board120opposite test sockets127because of the cold temperatures conducted along contact structures128(seeFIG. 2) from the cooled DUT. This condensation can cause a short circuit between any traces128or related contact structures that are exposed on back surface121, thereby producing erroneous test signals.

What is needed is a structure for the low-temperature testing arrangements described above that reduces condensation during low temperature testing.

SUMMARY

The present invention includes a system for reducing condensation during testing of an integrated circuit. An exemplary embodiment of the present invention includes two seals which close both ends of an enclosed channel formed when the load board is secured to the device tester. Clean dry air with a pressure greater than that of the environment is feed into the enclosed channel and is trapped because of the seals. In this embodiment the seal formed by the two seals is not airtight so that some air leaks out. In an alternative embodiment an airtight seal can be used when there are enough holes in the board to allow some air flow.

One embodiment of the invention has a system for integrated circuit testing. The system includes a support structure with a first substantially rectangular platform having a first group of test pins, and a second substantially rectangular platform having a second group of test pins, such that a channel is formed between the first and second substantially rectangular platforms; a dry air source configured to provide dry air to the channel; and a seal having a substantially rectangular shaped middle portion and tapered end portions; and wherein at least part of seal is interposed between the first and second substantially rectangular platform and is configured to close at least part of one end of the channel.

A second embodiment of the invention has a system for semiconductor device testing comprising, device tester including a support plate. The support plate includes a first substantially rectangular platform having a first group of test pins, and a second substantially rectangular platform having a second group of test pins, wherein the first and second substantially rectangular platforms are located such that a channel is formed between them. The system further includes a board positioned above the first and second substantially rectangular platforms and enclosing the channel; a dry air source configured to provide dry air to the enclosed channel; and two substantially rectangular shaped plugs, where each substantially rectangular shaped plug has tapered ends; and wherein each rectangular-shaped plug is configured to close at least part of one end of the enclosed channel such that the dry air is substantially contained in the enclosed channel.

Yet another embodiment of the invention includes a tester system for semiconductor device testing. The system includes: a base having a support plate and a channel between a first and second potion of the support plate, where the first portion has a first sealing ring and a first group of compressible test pins therein and the second portion has a second sealing ring and a second group of compressible test pins therein; a load board mounted over the first and second sealing rings and including first and second pluralities of test pin contacts formed on a first surface facing the base, and a device test socket mounted on a second surface facing away from the base, wherein the device test socket is located between the first and second groups of test pin contacts, and wherein when the first plurality of test pin contacts abut the tips of the first group of compressible test pins, and the second plurality of test pin contacts abut the tips of the second group of compressible test pins, the channel is enclosed; and a boxed shaped structure having at least two ends narrowed in at least one dimension, the box shaped structure closing one end of the enclosed channel, where examples of the boxed shaped structure are an outer edge seal, a plug, or like structures.

The present invention will be more full understood in view of the following description and drawings.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention.

FIG. 4is a top view of a portion of a semi-conductor device tester, which is used with an embodiment of the present invention. The labels inFIG. 4correspond to those inFIG. 7and are explained below with regard toFIG. 7. One example length and width of the device tester shown inFIG. 4is about 13.3 inches by 13.4 inches. An example width of channel117is about 5 inches. The depth of the recessed area162is about 0.83 in. and the height from the bottom of the recessed are to the top of the platforms140and150is about 1.165 in. These measurements are for illustration purposes only and dimensions vary from device tester to device tester.

FIGS. 5 and 6are a perspective view and a simplified cross-sectional side view showing an ATE system500for testing semiconductor devices according to a first embodiment of the present invention. Similar to conventional system100(discussed above), ATE system500includes an IC device tester (base)510(partially shown), a load board120, and a conventional automated handler (not shown) for mounting IC DUTs onto load board120. Aside from the modifications described below, device tester510and load board120operate as described above with reference to device tester110and load board120of conventional system100. Accordingly, structures of device tester510and load board120are identified with similar reference numbers, and detailed description of these structures is omitted below for brevity.

In accordance with an embodiment of the present invention, device tester510is modified to include pipe548coupled to a source of dry gas545via a valve547in order to provide the dry gas to the channel117. In the simplified illustrated embodiment, plug560(likewise plug562) is a three-dimensional rectangular structure with a length about equal to the width of the channel117. In other embodiments plug560(likewise plug562) is a three-dimensional rectangular shaped structure whose length is greater that the width of the channel117and whose lengthwise ends are tapered. In one embodiment a tapered end includes a concave shape.

As shown inFIG. 6, when load board120is secured to device tester510, load board120will make contact with first sealing ring142, which is at the edge of platform140and surrounds the first group of compressible test pins113, and with second sealing ring152, which is at the edge of platform150and surrounds the second group of compressible test pins115. One example of the sealing ring is found on the Teradyne J750 device tester (seeFIG. 4). The attached load board120will enclose the channel117forming a duct which is open on both ends. The purpose of the two outer edge seals or plugs560and562is to close both ends of the duct, hence forming a closed chamber. In one embodiment dry air with a dew point of −100 degrees Fahrenheit or below and above one atmosphere pressure is provided to the closed chamber in order to significantly reduce condensation during low temperature testing of the one or more ICs. In another embodiment the dew point may be above −100 degrees Fahrenheit as long as the gas is reasonably dry, and the gas pressure need only be greater than the external pressure so that gas flows outward, when the seal is not air-tight.

As indicated inFIG. 6, according to a first embodiment of the present invention, plugs560and562are constructed to reduce or prevent bending of load board520during test operations. Plug562(and likewise plug560) have length, height, and thickness as shown inFIG. 5. In this embodiment the plugs560and562are formed from a rigid, preferably non-conducting material, and have a thickness that provides sufficient strength to resist the downward bending of load board520during all types of DUT testing operations. In an alternative embodiment, the plugs560and562are made in two layers, with first layer from the same material as the device tester510(for example, aluminum) and a second layer from the same material as the sealing rings142and152.

According to a second embodiment of the present invention, outer edge seals560and562are constructed to form a closed chamber from channel117when load board120is mounted onto device tester510, which is then used to provide a dry gas environment on lower surface121of load board120opposite to test sockets127. In this embodiment the outer edge seals560and562are formed from a flexible, preferably non-conducting material, and have a narrow or sheet-like thickness in order to maintain the dry gas environment. In this embodiment an outer edge seal includes a narrow 3-D rectangular like structure and one or more layers. The 3-D rectangular like structure is configured to be mounted at the outer edge of channel117. Thus in one example, the 3-D rectangular like structure includes three cylindrical like structures (e.g., see the cylindrical like structures surround holes618and620and alignment pin622for outer edge seal810inFIG. 9) attached on the inside surface of flat and narrow 3-D rectangular like structure is configured to be mounted on the outer edge of channel117. As indicated inFIG. 5, one or more pipes or tubes548are formed in, for example, end wall531to facilitate the selective passage of dry gas (e.g., dry air) into channel117from a source (e.g., gas canister)545via a control valve547.

As indicated inFIG. 6, when load board120is mounted onto device tester510, load board120makes contact with platform seals142and152. Load board120forms an ceiling that along with plug560(and plug562not shown) encloses channel117to form a closed chamber. Subsequently, when dry cool gas from source545is pumped into chamber535, the dry cool gas prevents condensation from forming on back surface121opposite test sockets127, thereby preventing short-circuit conditions that can lead to erroneous test data.

FIG. 7shows a simplified schematic of another an embodiment of the present invention. The seals610and630are trapezoidal in shape. Seal610has a two bolt like objects612and614than fit into holes618and620, respectively, where holes618and620may be threaded. An alignment pin or bolt622fits into hole616, which may or may not be threaded. Seal610is configured to make contact with ledge160, i.e., a non-recessed area of channel117. Similarly, seal630has a two bolt like objects632and634than fit into holes638and640, respectively, where holes638and640may be threaded. An alignment pin or bolt642fits into hole636, which may or may not be threaded. Seal630is configured to make contact with ledge164, i.e., a non-recessed area of channel117. As illustrated inFIG. 7channel117has three parts: a recessed portion162, a first non-recessed portion160and a second non-recessed portion164.

InFIG. 7a dry, clean gas is supplied via a source650via tubes652-1and652-2to supply dry air654to channel117when it is enclosed by seals610and630and load board120(not shown). While seal610(and/or likewise seal630) is illustrated as trapezoidal in shape, in other embodiments the ends615and616of seal610may have a curved like structure, in one case concave, in order to make a better seal with platforms140and150, including platform seals142and152. In one embodiment seal610(and likewise seal630) are made of FR-4. In another embodiment seal610(and likewise seal630) are composed of two layers, where the top layer which makes contact with the platform seals142and152is made of silicon foam and the bottom layer which makes contact with the more rigid body of platforms150and140is made of FR-4.

FIG. 8illustrates the attachment of seals610and630ofFIG. 7to the test device510. As shown both ends of the recessed portion162of channel117are closed in a non-air-tight seal. The load board120will form the top of the chamber having the recessed portion162of channel117. In an alternative embodiment the enclosed chamber is substantially air-tight.

FIG. 9is an illustration ofFIG. 4with the two end seals810and812of an embodiment of the present invention. In this embodiment the seals810and812are made of a fiberglass layer (about 0.932 inches high and 5 inches in length) with a silicon foam layer on top (about 0.3 inches in height and 5 inches in length). The seals810and812would only contact the outer edge of the load board120and have a thickness of about ½ inch.

FIG. 10shows yet another embodiment of the present invention with the seals610and920attached to the testing device110ofFIG. 1. Here there is no modification of the testing device110. The seal920has a hole916connected to dry air supply912via hose914in order to supply air to the enclosed chamber.

FIG. 11is a top view of a portion of the Teradyne J750 Semi-conductor device tester. The same labels used inFIG. 7are used inFIG. 11to represent the same or similar items. LikeFIG. 7,FIG. 9has a recessed portion162of channel117. UnlikeFIG. 7, the non-recessed portion has two parts arranged in a step like fashion, a first non-recessed portion164-1and a higher second non-recessed portion164-2. Also as illustrated inFIG. 11, alignment pin622may be on a non-recessed portion of channel117above non-recessed portion160. Other embodiments of the device tester may have various non-recessed portions in various combinations and heights above recessed portion162.

FIGS. 12A and 12Bshow a front view and back view, respectively, of a simplified seal1010of an embodiment of the present invention.FIG. 12Ashows a front view of a two layer seal1010with the top layer1012having sealing foam and the bottom layer having a Printed Circuit Board (PCB) material such as FR-4. Two hoses1016attached to layer1014provide the clean dry air to the channel117. With reference toFIGS. 7,11and12A, inFIG. 12bwhere the items are similar or the same, the same reference numbers are used. InFIG. 12Bthe bottom layer1014of seal1010includes a first part1014A having the two holes1022and1024which are to be aligned with holes638and640respectively, inFIG. 11, where the flat first part1014A is configured to be attached to the non-recessed (or partially recessed) portion164-1via the holes1022–1024. The bottom layer1014further includes a 3D rectangular second part1014B having two air holes1030for the air hoses1016and having a small 3D rectangular section1020removed from the base of part1014B in order that the part1014B can sit on top of non-recessed portion164-2inFIG. 11. In another embodiment rectangular portion1014B is thin enough to fit above the non-recessed (or partially recessed) portion164-2. The seal1010further includes a rubber like or silicon foam or other flexible material donut1040which fits over alignment pin642and which may or may not be attached to part1014B of the seal1010. The donut1040is shown smaller than what is needed for ease of illustration, and should be of a size to form a seal (air tight or nearly air tight) between the platform seal140ofFIG. 11and second part1014B of seal1010.

Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to one of ordinary skill in the art. For example, while some of embodiments have shown that channel117has a recessed portion and a non-recessed portion, in other embodiments channel117has no recessed portion. In addition, while some embodiments of the invention have been described in the context of low temperature testing, the scope of the invention includes any other testing where an enclosed gas filled chamber under a load board is needed. Thus, the invention is limited only by the following claims.