POWER SUPPLY HAVING ADAPTIVE ADJUSTABLE FREQUENCY RANGE OF VOLTAGE COMPENSATION MECHANISM

A power supply includes a noise suppression circuit, an active power factor correction circuit, an active clamp flyback conversion circuit, a voltage-stabilizing feedback compensation circuit, and a control circuit. The active power factor correction circuit and the active clamp flyback conversion circuit convert an AC voltage into an output voltage for driving a load. The voltage-stabilizing feedback compensation circuit performs voltage-stabilizing feedback compensation to the output voltage. The active clamp flyback conversion circuit switches its operational mode based on the instantaneous output loading of the power supply. The control circuit controls the operation of the voltage-stabilizing feedback compensation circuit based on the operational mode of the active clamp flyback conversion circuit, thereby adjusting the equivalent capacitance of the voltage-stabilizing feedback compensation circuit for providing a corresponding voltage-stabilizing feedback compensation range associated with the instantaneous output loading of the power supply.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a power supply, and more particularly, to a power supply having adaptive adjustable frequency range of voltage compensation mechanism.

2. Description of the Prior Art

Power supply circuits are commonly used to convert alternative-current (AC) power into direct-current (DC) voltages for driving various components in a computer system which may have different operating voltages. The unlimited extraction of natural resources and the consequences of overlooking the environmental costs of such behavior have made more and more people aware of the importance of eco-design measures. Many frameworks have been established for the setting of eco-design requirements for energy-using products, such as consumer electronics, office equipment, household appliances, or power supplies. For example, Energy Star is a program run by the U.S. Environmental Protection Agency (EPA) and U.S. Department of Energy (DOE) that promotes energy efficiency. The program provides information on the energy consumption of products and devices using different standardized methods.

For a power supply and its related system design, its rated power factor is required to be larger than 0.9 according to Energy Star standard. Therefore, a high-power power supply typically includes a boost front-end circuit and a buck back-end circuit. The boost front-end circuit of the high-power power supply may be a boost power factor correction (PFC) circuit capable of improving the power factor of the AC voltage. The buck back-end circuit of the high-power power supply may be a step-down flyback converter capable of converting a high voltage (such as 400V) outputted by the boost active PFC circuit into a low voltage (such as 19.5V) for supplying the operation of a load device (such as a laptop computer).

In order to meet the requirement of stricter power-saving specification, a power supply usually adopts a voltage-stabilizing feedback compensation mechanism for reducing power consumption. However, the prior art power supply only adopts a single frequency range of voltage compensation based on its maximum loading rate, and is thus unable to achieve optimized power reduction when operating in different modes. Therefore, there is a need for a power supply having adaptive adjustable frequency range of voltage compensation.

SUMMARY OF THE INVENTION

The present invention provides a power supply with an adaptive adjustable frequency range of voltage compensation mechanism and configured to convert an AC voltage into an output voltage for supplying power to a loading device. The power supply includes a noise suppression circuit, a boost active PFC circuit, an active clamp flyback converting circuit, a voltage-stabilizing feedback compensation circuit and a control circuit. The noise suppression circuit is configured to filter noises in the AC voltage for providing a processed AC voltage. The boost active PFC circuit is configured to convert the processed AC voltage into a DC voltage and then convert the DC voltage into a first pulse DC voltage. The active clamp flyback converting circuit is configured to convert the first pulse DC voltage into the output voltage and provide a detecting voltage associated with the output voltage. The voltage-stabilizing feedback compensation circuit is configured to perform voltage stabilization to the output voltage selectively using a first voltage-stabilizing feedback compensation range or a second voltage-stabilizing feedback compensation range. The control circuit is configured to output a first control signal for controlling an operation of the boost active PFC circuit, wherein a voltage level of the first control signal periodically switches between a first enable level and a first disable level; output a second control signal for controlling an operation of the active clamp flyback converting circuit, wherein a voltage level of the second control signal periodically switches between a second enable level and a second disable level; determine a current operational mode of the active clamp flyback converting circuit based on the detecting voltage; control the voltage-stabilizing feedback compensation circuit to perform voltage-stabilizing feedback compensation to the output voltage using the first voltage-stabilizing feedback compensation range when it is determined based on the detecting voltage that the active clamp flyback converting circuit is operating in a first mode; and control the voltage-stabilizing feedback compensation circuit to perform voltage-stabilizing feedback compensation to the output voltage using the second voltage-stabilizing feedback compensation range when it is determined based on the detecting voltage that the active clamp flyback converting circuit is operating in a second mode. A first instantaneous output loading of the power supply when the active clamp flyback converting circuit is operating in the first mode is larger than a second instantaneous output loading of the power supply when the active clamp flyback converting circuit is operating in the second mode. The first voltage-stabilizing feedback compensation range is larger than the second voltage-stabilizing feedback compensation range.

DETAILED DESCRIPTION

FIG.1is a functional diagram illustrating a power supply100with an adaptive adjustable frequency range of voltage compensation mechanism according to an embodiment of the present invention. The power supply100includes a noise suppression circuit10, a boost active power factor correction (PFC) circuit20, an active clamp flyback converting circuit30, a voltage-stabilizing feedback compensation circuit40, and a control circuit50. The noise suppression circuit10is configured to receive an AC voltage VACprovided by AC mains and filter differential-mode/common-mode noises in the AC voltage VAC, thereby providing a corresponding processed AC voltage VAC′. The boost active PFC circuit20is configured to convert the processed AC voltage VAC′ into a pulse DC voltage VO1. The active clamp flyback converting circuit30is configured to convert the pulse DC voltage VO1into an output voltage VOUTfor supplying power to a loading device (not shown inFIG.1) and provide a detecting voltage VS associated with the status of the output voltage VOUT. The voltage-stabilizing feedback compensation circuit40is configured to monitor the status of the output voltage VOUTfor providing a corresponding feedback voltage VFB, and perform voltage-stabilizing feedback compensation to the output voltage VOUTaccording to the operational mode of the active clamp flyback converting circuit30. The control circuit50is configured to control the operations of the boost active PFC circuit20, the active clamp flyback converting circuit30and the voltage-stabilizing feedback compensation circuit40according to the feedback voltage VFBand the detecting voltage VS in order to perform voltage conversion and voltage-stabilizing feedback compensation, and adaptively adjust the frequency range of voltage-stabilizing feedback compensation according to the operational mode of the active clamp flyback converting circuit30in order to reduce power consumption.

FIG.2is a diagram illustrating an implementation of the power supply100according to an embodiment of the present invention. The noise suppression circuit10may be coupled to AC mains via a live pin L1and a neutral pin N1for receiving the AC voltage VAC, and output the processed AC voltage VAC′ via a live pin L2and a neutral pin N2. However, the implementation of the transmission interface between the noise suppression circuit10and AC mains does not limit the scope of the present invention.

In the embodiment depicted inFIG.2, the noise suppression circuit10includes common-mode inductors LC1-LC2, a coupling inductor LTC, an X-capacitor CX and Y-capacitors CY1and CY2. The coupling inductor LTC includes three windings (represented by respective numbers of turns NC1-NC3), wherein the windings NC1and NC3are disposed on the first side of the coupling inductor LTC and the winding NC2is disposed on the second side of the coupling inductor LTC. In the coupling inductor LTC, the first terminal of the winding NC1is coupled to the first input end of the noise suppression circuit10(i.e., the live pin L1), and the second terminal of the winding NC1is coupled to the first output end of the noise suppression circuit10(i.e., the live pin L2). The first terminal of the winding NC2is coupled to the second input end of the noise suppression circuit10(i.e., the neutral pin N1), and the second terminal of the winding NC2is coupled to the second output end of the noise suppression circuit10(i.e., the neutral pin N2). The first terminal and the second terminal of the winding NC3are coupled to the voltage-stabilizing feedback compensation circuit40. The first end of the common-mode inductor LC1is coupled to the first terminal of the winding NC1in the coupling inductor LTC, and the second end of the common-mode inductor LC1is coupled to the second terminal of the winding NC1in the coupling inductor LTC. The first end of the common-mode inductor LC2is coupled to the first terminal of the winding NC2in the coupling inductor LTC, and the second end of the common-mode inductor LC2is coupled to the second terminal of the winding NC2in the coupling inductor LTC. The first end of the X-capacitor CX is coupled between the live pin L1and the first end of the common-mode inductor LC1, and the second end of the X-capacitor CX is coupled between the neutral pin N1and the first end of the common-mode inductor LC2. The first end of the Y-capacitor CY1is coupled between the live pin L2and the second end of the common-mode inductor LC1, and the second end of the Y-capacitor CY1is coupled to an earth ground FG. The first end of the Y-capacitor CY2is coupled between the neutral pin N2and the second end of the common-mode inductor LC2, and the second end of the Y-capacitor CY2is coupled to the earth ground FG.

The AC voltage VACprovided by AC mains may include differential-mode noises or common-mode noises. Differential-mode noises refer to the voltage noises with a frequency range of 10 KHz-30 MHz which exist between the live pin L1and the neutral pin N1and do not flow into the earth ground FG. Common-mode noises refer to the voltage noises with a frequency range of 10 KHz-30 MHz which flow from the live pin L1or the neutral pin N1into the earth ground FG. In the present invention, the noise suppression circuit10may filter the differential-mode noises in the AC voltage VACusing the X-capacitor CX, and filter the common-mode noises in the AC voltage VACusing the Y-capacitors CY1and CY2. In the present invention, the noise suppression circuit10may filter the common-mode noises in the AC voltage VACfurther using the common-mode inductors LC1-LC2whose values are determined based on the bandwidth of the noises. In an embodiment, the inductance of the common-mode inductor LC1is equal to the inductance of the common-mode inductor LC2in order to optimize noise filtering. However, the implementation of the noise suppression circuit10does not limit the scope of the present invention.

In the embodiment depicted inFIG.2, the boost active PFC circuit20includes a rectifier12, a power switch Q1, a boost diode DO1, a storage capacitor C1, and a boost inductor L1. The boost active PFC circuit20is configured to convert the processed AC voltage VAC′ into a pulse DC voltage VO1. In an embodiment of the present invention, the rectifier12may be implemented as a bridge rectifier which includes rectifying diodes D1-D4coupled to the live pin L2and the neutral pin N2for receiving the processed AC voltage VAC′ and is configured to convert the processed AC voltage VAC′ into a DC voltage VIN. However, the implementation of the rectifier12does not limit the scope of the present invention.

The boost inductor L1includes a first end coupled to the rectifier12for receiving the DC voltage VINand a second end selectively coupled to a ground level GND1via the power switch Q1for storing the energy of the DC voltage VIN. The storage capacitor C1includes a first end coupled to the pulse DC voltage VO1and a second end coupled to the ground level GND1for storing the energy of the pulse DC voltage VO1. The boost diode DO1includes an anode coupled to the second end of the boost inductor L1and a cathode coupled to the first end of the storage capacitor CO1. The power switch Q1includes a first end coupled between the second end of the boost inductor LM1and the anode of the boost diode DO1, a second end coupled to the ground level GND1, and a control end for receiving a control signal GD1. The power switch Q1is periodically turned on and turned off according to the control signal GD1so as to allow the boost inductor LM1to store energy and discharge energy. This way, the input current may vary with the input voltage, thereby increasing the power factor and decreasing current harmonics.

In the boost active APF circuit20, the boost inductor LM1, the boost diode DO1, the storage capacitor CO1and the power switch Q1are operated to provide voltage step-up operation. During the period when the power switch Q1is turned on by the AC voltage VACprovided by AC mains, the second end of the boost inductor LM1is coupled to the ground level GND1so that the boost inductor LM1may sense the variations in the DC voltage VINand the resulting time-varying magnetic field induces an electromotive force (voltage) which is stored as magnetic energy in the boost inductor LM1. During the period when the power switch Q1is turned off by the AC voltage VACprovided by AC mains, the boost inductor LM1is cut off from the ground level GND1and its stored magnetic energy is converted into electrical energy, thereby generating large current which charges the storage capacitor CO1via the boost diode DO1. After the power switch Q1switches between the turned-on state and turned-off state multiple times, the DC voltage VINmay be boosted to a desired level for supplying the pulse DC voltage VO1.

In the embodiment depicted inFIG.2, the active clamp flyback converting circuit30includes a transformer TR, a power switch Q2, a magnetizing inductor LM2, a storage capacitor CO2, a detecting resistor Rs, and an output diode DO2. The active clamp flyback converting circuit30is configured to receive the pulse DC voltage VO1via its input end and provide the output voltage VOUTvia its output end. The transformer TR includes a primary winding (represented by its number of turns NP), a secondary winding (represented by its number of turns NS) and an auxiliary winding (represented by its number of turns NX). The primary winding NP and the auxiliary winding are disposed on the primary side of the transformer TR, and the secondary winding NS is disposed on the secondary side of the transformer TR. The undotted terminal of the primary winding NP is selectively coupled to the ground level GND1via the power switch Q2, and the dotted terminal of the secondary winding NS is coupled to the ground level GND2. The magnetizing inductor LM2includes a first end coupled the dotted terminal of the primary winding NP and a second end coupled the undotted terminal of the primary winding NP. The power switch Q2includes a first end coupled the undotted terminal of the primary winding NP, a second end coupled the ground level GND1, and a control end for receiving a control signal GD2. The output diode DO2includes an anode coupled to the undotted terminal of the secondary winding NS and a cathode coupled to the output end of the power supply100(i.e., the output voltage VOUT). The storage capacitor CO2includes a first end coupled to the cathode of the output diode DO2and a second end coupled to the ground level GND2for storing the energy of the output voltage VOUT, wherein IOUTrepresents the output current flowing through the storage capacitor CO2. The detecting resistor Rs includes a first end coupled to the second end of the storage capacitor CO2and a second end coupled to the ground level GND2for storing the energy of the output current IOUT, thereby providing a corresponding detecting voltage VS.

The pulse DC voltage VO1outputted by the boost active PFC circuit20is the input voltage of the active clamp flyback converting circuit30. The power switch Q2is configured to periodically switch between a turned-on state and a turned-off state according to the control signal GD2, thereby allowing the magnetizing inductor LM2to store energy and discharge energy. The transformer TR is configured to transfer the energy of the pulse DC voltage VO1stored in its primary winding NP to its secondary winding NS for providing a pulse DC voltage VO2. When the output diode DO2is forward-biased, the pulse DC voltage VO2may be transmitted to the output end of the power supply100, and the storage capacitor CO2may store the energy stored in the secondary winding NS for supplying the output voltage VOUT. When the output diode DO2is not forward-biased, the power supply path of the power supply100is cut off, and the power supply100has no output (VOUT=0).

In the embodiment depicted inFIG.2, the voltage-stabilizing feedback compensation circuit40includes a compensation capacitor CC, a feedback capacitor CB, a start resistor RP, bandwidth-limiting inductors LX1-LX2, voltage-dividing resistors RO1-RO2, auxiliary switches Q3-Q4, a linear optocoupler PC and a voltage regulator TL. The voltage-dividing resistors RO1and RO2are coupled in series between the output voltage VOUTand the ground level GND2, and is configured to provide a reference voltage VREFassociated with the output voltage VOUTacross the voltage-dividing resistor RO2, wherein VREF=VOUT*RO2/(RO1+RO2). The voltage regulator TL includes a reference terminal R coupled between the voltage-dividing resistors RO1and RO2for receiving the reference voltage VREF, an anode terminal A coupled to the ground level GND2, and a cathode terminal K coupled to the linear optocoupler PC, wherein VKArepresents the voltage established across the cathode terminal K and the anode terminal A. The compensation capacitor CC includes a first end coupled to the cathode terminal K of the voltage regulator TL and a second end coupled to reference terminal R of the voltage regulator TL. The voltage regulator TL is configured to adjust a compensation current Icflowing from its cathode terminal K to its anode terminal A according to the status of its reference terminal R. More specifically, the voltage regulator TL is configured to compare the reference voltage VREFreceived via its reference terminal R with a built-in baseline voltage and adjust its gain according to the difference between the reference voltage VREFand the built-in baseline voltage using the compensation capacitor CC coupled between its cathode terminal K and its reference terminal R of the voltage regulator TL. This way, the compensation current Icflowing through the voltage regulator TL may reflect the value of the reference voltage VREF, thereby reflecting the value of the output voltage VOUT.

The linear optocoupler PC includes a light-emitting diode42and a phototransistor44and is configured to perform electrical-optical-electrical conversion between the primary side and the secondary side of the transformer TR. The light-emitting diode42is coupled between a first input end and a second input end of the linear optocoupler PC, wherein the anode of the light-emitting diode42is coupled to the first end of the storage capacitor CO2(i.e., the output voltage VOUT) via the start resistor RP and the cathode of the light-emitting diode42is coupled to the cathode terminal K of the voltage regulator TL. The phototransistor44is coupled between a first output end and a second output end of the linear optocoupler PC, wherein the first end of the phototransistor44is coupled to the control circuit50and the second end of the phototransistor44is coupled to the feedback capacitor CB. The feedback capacitor CB includes a first end coupled to the second end of the phototransistor44and a second end coupled to the ground level GND1. Since the compensation current Icflowing through the light-emitting diode42is associated with the value of the output voltage VOUT, the linear optocoupler PC may detect the variations in the output voltage VOUTusing the light-emitting diode42on its input side and convert the electrical energy associated with the variations in the output voltage VOUTinto optical energy, which is then received by the phototransistor44on its output side and converted into a feedback current IFB. This way, the feedback capacitor CB may be charged by feedback current IFBfor providing the corresponding feedback voltage VFB.

The bandwidth-limiting inductor LX1includes a first end selectively coupled to the first end of the compensation capacitor CC via the auxiliary switch Q3and a second end coupled to the second end of the compensation capacitor CC. The bandwidth-limiting inductor LX2includes a first end selectively coupled to the first end of the bandwidth-limiting inductor LX1via the auxiliary switch Q4and a second end coupled to the second end of the bandwidth-limiting inductor LX1. The auxiliary switch Q3includes a first end coupled to the first end of the bandwidth-limiting inductor LX1, a second end coupled to the first end of the compensation capacitor CC, and a control end for receiving a control signal GD3. The auxiliary switch Q4includes a first end coupled to the first end of the bandwidth-limiting inductor LX2, a second end coupled to the first end of the bandwidth-limiting inductor LX1, and a control end for receiving a control signal GD4.

The present invention can adjust the equivalent capacitance of the voltage-stabilizing feedback compensation loop provided by the voltage-stabilizing feedback compensation circuit40by changing the status of the auxiliary switches Q3and Q4. When the auxiliary switches Q3and Q4are both turned off, the bandwidth-limiting inductors LX1and LX2are isolated from the voltage-stabilizing feedback compensation loop, and the equivalent capacitance of the voltage-stabilizing feedback compensation loop is thus determined by the compensation capacitor CC alone. When the auxiliary switch Q3is turned on and the auxiliary switch Q4is turned off, the bandwidth-limiting inductor LX1may be coupled in parallel with the compensation capacitor CC, and the equivalent capacitance of the voltage-stabilizing feedback compensation loop is thus determined by the parallel structure of the compensation capacitor CC and the bandwidth-limiting inductor LX1. When the auxiliary switches Q3and Q4are both turned on, the bandwidth-limiting inductors LX1and LX2may be coupled in parallel with the compensation capacitor CC, and the equivalent capacitance of the voltage-stabilizing feedback compensation loop is thus determined by the parallel structure of the compensation capacitor CC, the bandwidth-limiting inductor LX1and the bandwidth-limiting inductor LX2.

In the embodiment depicted inFIG.2, the first end of the bandwidth-limiting inductor LX1may be coupled to the first end of the winding NC3in the coupling inductor LTC of the noise suppression circuit10, and the second end of the bandwidth-limiting inductor LX1may be coupled to the second end of the winding NC3in the coupling inductor LTC of the noise suppression circuit10, the first end of the bandwidth-limiting inductor LX2may be coupled to the first end of the auxiliary winding NX in the transformer TR of the active clamp flyback converting circuit30, and the second end of the bandwidth-limiting inductor LX2may be coupled to the second end of the auxiliary winding NX in the transformer TR of the active clamp flyback converting circuit30. In another embodiment, the first end of the bandwidth-limiting inductor LX1may be coupled to the first end of the auxiliary winding NX in the transformer TR of the active clamp flyback converting circuit30, the second end of the bandwidth-limiting inductor LX1may be coupled to the second end of the auxiliary winding NX in the transformer TR of the active clamp flyback converting circuit30, first the end of the bandwidth-limiting inductor LX2may be coupled to the first end of the winding NC3in the coupling inductor LTC of the noise suppression circuit10, and the second end of the bandwidth-limiting inductor LX2may be coupled to the second end of the winding NC3in the coupling inductor LTC of the noise suppression circuit10.

In the embodiment depicted inFIG.2, the control circuit50may be a microcontroller unit (MCU) which includes pins P1-P6. The control circuit50is configured to output the control signal GD1which periodically switches between a first enable level and a first disable level to the control end of the power switch Q1via its pin P1, output the control signal GD2which periodically switches between a second enable level and a second disable to the control end of the power switch Q2via its pin P2, output the control signal GD3having a third enable level or a third disable to the control end of the auxiliary switch Q3via its pin P3, and output the control signal GD4having a fourth enable level or a fourth disable to the control end of the auxiliary switch Q4via its pin P4. Also, the control circuit50is coupled to the active clamp flyback converting circuit30via its pin P5for receiving the detecting voltage VS, and coupled to the voltage-stabilizing feedback compensation circuit40via its pin P6for receiving the feedback voltage VFB.

As depicted inFIGS.1and2, when the power supply100is connected to AC mains, the noise suppression circuit10may filter the noises in the AC voltage VACsupplied by AC mains, thereby providing the processed AC voltage VAC′. The rectifier12of the boost active PFC circuit20may convert the processed AC voltage VAC′ into the DC voltage VIN. The control circuit50is configured to output the control signal GD1which periodically switches between the first enable level and the first disable level to the control end of the power switch Q1, so that the power switch Q1may be periodically turned on and turned off correspondingly in order to allow the boost inductor LM1to periodically store energy and discharge energy, thereby providing the boosted pulse DC voltage VO1on the primary side of the transformer TR. Next, the control circuit50is configured to output the control signal GD2which periodically switches between the second enable level and the second disable level to the control end of the power switch Q2, so that the power switch Q2may be periodically turned on and turned off correspondingly in order to periodically transfer the energy stored on the primary side of the transformer TR to the secondary side of the transformer TR, thereby providing the output voltage VOUT. Meanwhile, the output current IOUTassociated with the output voltage VOUTmay flow to the ground level GND2via the detecting resistor RS, thereby establishing the detecting voltage VS on the detecting resistor Rs. This way, the control circuit50may receive the detecting voltage VS via its pin P5, thereby acquiring the instantaneous status of the output current IOUT.

As previously stated, the voltage-stabilizing feedback compensation circuit40may monitor the instantaneous status of the output voltage VOUTusing the voltage-dividing resistors RO1-RO2, the feedback capacitor CC/the bandwidth-limiting inductor LX1/the bandwidth-limiting inductor LX2, the linear optocoupler PC and the voltage regulator TL, thereby providing the corresponding feedback voltage VFB. The control circuit50may receive the feedback voltage VFBvia its pin P6and compare the feedback voltage VFBwith a built-in triangular voltage, thereby adjusting the duty cycle of the control signal GD2using pulse width modulation (PWM) technique in order to stabilize the output voltage VOUT.

In the present invention, the active clamp flyback converting circuit30is configured to switch its operational mode based on the instantaneous value of the output current IOUTrequired for driving a loading device (not shown inFIGS.1and2), and the detecting voltage VS may reflect the instantaneous status of the output current IOUT(VS=IOUT*Rs). In the present invention, the control circuit50is configured to provide the control signals GD3and GD4based on the operational mode of the active clamp flyback converting circuit30, thereby adjusting the equivalent capacitance of the voltage-stabilizing feedback compensation loop in order to provide suitable voltage-stabilizing feedback compensation ranges for different output loadings. For illustrative purpose, it is assumed that the present active clamp flyback converting circuit30have three operational modes: a continuous conduction mode (CCM), a quasi-resonant mode (QRM) and a burst mode (BRM).

FIG.3Ais a diagram illustrating the waveforms of related signals when the active clamp flyback converting circuit30is operating in the continuous conduction mode according to an embodiment of the present invention. In the waveform depicted on the top ofFIG.3A, the horizontal axis represents the control signal GD2of the power switch Q2, and the horizontal axis represents time. In the waveform depicted on the bottom ofFIG.3A, the horizontal axis represents the current ILM2flowing through the magnetizing inductor LM2, and the horizontal axis represents time. When the instantaneous output loading of the power supply100is within 75%-100% of its maximum loading IOMAX, the active clamp flyback converting circuit30is configured to operate in the continuous conduction mode so as to provide the output voltage VOUThaving a larger average power. In the continuous conduction mode, the current ILM2flowing through the magnetizing inductor LM2remains larger than zero, and the power switch Q2is operating based on a larger switching frequency within 120K-165 KHz.

FIG.3Bis a diagram illustrating the waveforms of related signals when the active clamp flyback converting circuit30is operating in the quasi-resonant mode according to an embodiment of the present invention. In the waveform depicted on the top ofFIG.3B, the horizontal axis represents the control signal GD2of the power switch Q2, and the horizontal axis represents time. In the waveform depicted on the bottom ofFIG.3B, the horizontal axis represents the voltage VDS established across the power switch Q2(i.e., the voltage difference between the first end and the second end of the power switch Q2), and the horizontal axis represents time. When the instantaneous output loading of the power supply100is within 15%-75% of its maximum loading IOMAX, the active clamp flyback converting circuit30is configured to operate in the quasi-resonant mode so as to improve the overall power conversion efficiency. In the quasi-resonant mode, the power switch Q2is able to achieve soft-switching at zero-voltage and is operating based on a switching frequency within 65K-100 KHz.

FIG.3Cis a diagram illustrating the waveforms of related signals when the active clamp flyback converting circuit30is operating in the burst mode according to an embodiment of the present invention. In the waveform depicted on the top ofFIG.3C, the horizontal axis represents the control signal GD2of the power switch Q2in the continuous conduction mode, and the horizontal axis represents time. In the waveform depicted on the bottom ofFIG.3C, the horizontal axis represents the control signal GD2′ of the power switch Q2in the burst mode, and the horizontal axis represents time. When the instantaneous output loading of the power supply100is lower than 15% of its maximum loading IOMAX, the active clamp flyback converting circuit30is configured to operate in the burst mode in order to reduce switching loss and satisfy the light-load power efficiency requirement. In the burst mode, the power switch Q2is operating based on a switching frequency smaller than 15 KKHz, and the switching of the power switch Q2does not take place during each cycle. Also, the duty cycle of the control signal GD2′ in the burst mode is shorter than the duty cycle of the control signal GD2in the continuous conduction mode.

FIGS.4A-4Care diagrams illustrating the equivalent circuits of the voltage-stabilizing feedback compensation circuit40when the power supply100is operating in different modes according to embodiments of the present invention.FIG.5is a diagram illustrating different voltage-stabilizing feedback compensation ranges when the power supply100is operating in different modes according to an embodiment of the present invention.

When the active clamp flyback converting circuit30is operating in the continuous conduction mode, the power switch Q2is configured to operate based on a larger switching frequency, and a larger voltage-stabilizing feedback compensation range is thus required. When the control circuit50determines based on the detecting voltage VS received via its pin P5that the active clamp flyback converting circuit30is currently operating in the continuous conduction mode, the control circuit50is configured to output the control signal GD3having the third disable level via its pin P3and output the control signal GD4having the fourth disable level via its pin P4in order to turning off the auxiliary switches Q3and Q4. Under such circumstance, the voltage-stabilizing feedback compensation loop provided by the voltage-stabilizing feedback compensation circuit40only includes the compensation capacitor CC (as depicted inFIG.4A). In other words, the equivalent capacitance of the voltage-stabilizing feedback compensation loop may be adjusted to a maximum value for providing the largest voltage-stabilizing feedback compensation range BW1(as depicted inFIG.5).

When the active clamp flyback converting circuit30is operating in the burst mode, the power switch Q2is configured to operate based on a smaller switching frequency, and a smaller voltage-stabilizing feedback compensation range is thus required. When the control circuit50determines based on the detecting voltage VS received via its pin P5that the active clamp flyback converting circuit30is currently operating in the burst mode, the control circuit50is configured to output the control signal GD3having the third enable level via its pin P3for turning on the auxiliary switches Q3and output the control signal GD4having the fourth disable level via its pin P4for turning off the auxiliary switch Q4. Under such circumstance, the voltage-stabilizing feedback compensation loop provided by the voltage-stabilizing feedback compensation circuit40includes the parallel structure formed by the compensation capacitor CC and the bandwidth-limiting inductor LX1(as depicted inFIG.4C). Since the bandwidth-limiting inductor LX1may compensate the effect of the compensation capacitor CC, the equivalent capacitance of the voltage-stabilizing feedback compensation loop may be adjusted to the minimum value for providing the smallest voltage-stabilizing feedback compensation range BW3(as depicted inFIG.5).

When the active clamp flyback converting circuit30is operating in the quasi-resonant mode, the power switch2is configured to operate based on a medium switching frequency, and a medium voltage-stabilizing feedback compensation range is thus required. When the control circuit50determines based on the detecting voltage VS received via its pin P5that the active clamp flyback converting circuit30is currently operating in the quasi-resonant mode, the control circuit50is configured to output the control signal GD3having the third enable level via its pin P3and output the control signal GD4having the fourth enable level via its pin P4for simultaneously turning on the auxiliary switches Q3and Q4. Under such circumstance, the voltage-stabilizing feedback compensation loop provided by the voltage-stabilizing feedback compensation circuit40includes the parallel structure formed by the compensation capacitor CC, the bandwidth-limiting inductor LX1and the bandwidth-limiting inductor LX2(as depicted inFIG.4B). As well-known to those skilled in the art, the overall inductance of the bandwidth-limiting inductors LX1and LX2coupled in parallel is smaller than the inductance of each bandwidth-limiting inductor alone, and thus compensates the effect of the compensation capacitor CC with a smaller degree. In other words, the equivalent capacitance of the voltage-stabilizing feedback compensation loop may be adjusted to a medium value for providing a medium voltage-stabilizing feedback compensation range BW2which is smaller than BW1and larger than BW3(as depicted inFIG.5).

In an embodiment of the present invention, each of the power switches Q1-Q2and the auxiliary switches Q3-Q4may be a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), or another device with similar function. For N-type transistors, the enable level is logic 1 and the disable level is logic 0; for P-type transistors, the enable level is logic 0 and the disable level is logic 1. However, the types of the power switches Q1-Q2and the auxiliary switches Q3-Q4do not limit the scope of the present invention.

In conclusion, the power supply100of the present invention, the boost active PFC circuit20may improve the power factor of the AC voltage, the active clamp flyback converting circuit30may convert the voltage outputted by the boost active PFC circuit20into an output voltage VOUTrequired for driving a load, and the voltage-stabilizing feedback compensation circuit40may perform voltage-stabilizing feedback compensation to the output voltage VOUT. The active clamp flyback converting circuit30may switch its operational mode based on the instantaneous output loading of the power supply100, and the control circuit50may control the operation of the voltage-stabilizing feedback compensation circuit40based on the operational mode of the active clamp flyback converting circuit30. Therefore, the equivalent capacitance of the voltage-stabilizing feedback compensation loop may be adjusted according to different output loadings for providing different voltage-stabilizing feedback compensation ranges, thereby optimizing power consumption in different operational modes.