Signal generation circuit, micro-controller, and control method thereof

A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan Patent Application No. 110122278, filed on Jun. 18, 2021, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a signal generation circuit, and more particularly to a signal generation circuit that provides an analog signal.

Description of the Related Art

Generally, a signal generation circuit generates an output signal according to input data. The input data is provided by a specific data source. Generally, the data source can be changed by the intervention of a central processing unit (CPU). However, when the intervention times increases, it will consume the resources of the CPU and reduce system performance.

BRIEF SUMMARY OF THE INVENTION

In accordance with an embodiment of the disclosure, a signal generation circuit comprises a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads either the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

In accordance with another embodiment of the disclosure, a micro-controller comprises a central processing unit (CPU), a first peripheral circuit, a first control circuit, a second control circuit, an arbiter circuit, a DAC circuit, and a second peripheral circuit. The first peripheral circuit is coupled to the CPU. The first control circuit is coupled to the first peripheral circuit and stores a first string of data. In response to a first event occurring in the first peripheral circuit, the first control circuit enables a first trigger signal. The second control circuit is coupled to the first peripheral circuit and stores a second string of data. In response to a second event occurring in the first peripheral circuit, the second control circuit enables a second trigger signal. The arbiter circuit reads either the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output. The second peripheral circuit operates according to the analog output.

In accordance with a further embodiment of the disclosure, a control method applied in a micro-controller comprising a CPU is described in the following paragraph. In an initial period, the CPU is utilized to set a first peripheral circuit and activate a DAC circuit. In an operation period: a first string of data is written to a first control circuit, a second string of data is written to a second control circuit; a first trigger signal is enabled in response to a first event occurring in the first peripheral circuit; a second trigger signal is enabled in response to a second event occurring in the first peripheral circuit; either the first control circuit or the second control circuit is read according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled; and the digital input is converted to an analog output.

Control method may be practiced by the signal generation circuit or the micro-controller which has hardware or firmware capable of performing particular functions and may take the form of program code embodied in a tangible media. When the program code is loaded into and executed by an electronic device, a processor, a computer or a machine, the electronic device, the processor, the computer or the machine becomes a signal generation circuit or a micro-controller for practicing the disclosed method.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

FIG.1is a schematic diagram of an exemplary embodiment of a micro-controller according to various aspects of the present disclosure. As shown inFIG.1, the micro-controller100comprises a central processing unit (CPU)110, peripheral circuits120and130, and a signal generation circuit140. In an initial period, the CPU110initializes the peripheral circuit120and the signal generation circuit140. The disclosure does not limit how the CPU110initializes the peripheral circuit120and the signal generation circuit140. In one embodiment, the CPU110may send a set signal SS1to activate the logic circuits (not shown) in the peripheral circuit120and set the registers (not shown) of the peripheral circuit120. Additionally, the CPU110may send a set signal SS2to activate the signal generation circuit140.

The peripheral circuit120is coupled between the CPU110and the signal generation circuit140. In the initial period, the peripheral circuit120receives the set signal SS1and sets the internal registers in the peripheral circuit120according to the set signal SS1. Next, in an operation period, the peripheral circuit120starts operating. In this embodiment, the operation of the peripheral circuit120does not require support from the CPU110. In other words, when the peripheral circuit120operates, the CPU110may be in an idle state or enter a power-down mode. In the operation period, the peripheral circuit120performs at least one specific operation. After finishing the specific operation, the peripheral circuit120causes an event. In this embodiment, the peripheral circuit120may perform at least one specific operation to cause the events EV1˜EVn.

The kinds of events EV1˜EVn are not limited in the present disclosure. One of the events EV1˜EVn is the same as another of the events EV1˜EVn. For example, the event EV1may be an overflow event which occurs when the counting value of the counter circuit (now shown) in the peripheral circuit120arrives a first target value. The event EV2may be an overflow event which occurs when the counting value of the counter circuit (now shown) in the peripheral circuit120or the counting value of another counter circuit (not shown) in the peripheral circuit120arrives a second target value. The second target value may be different from the first target value. In this case, the events EV1and EV2belong to the same event, such as the overflow event.

In other embodiments, one of the events EV1˜EVn may be different from another of the events EV1˜EVn. For example, the event EV1may be an overflow event caused by a counter circuit. In this case, the event EVn occurs when the level of a specific pin (not shown) in the peripheral circuit120is equal to a specific level, such as a high level or a low level. In some embodiments, at least one of the events EV1˜EVn is caused by a software. In this case, the event EV1may be caused when a specific software is executed or when a controller (not shown) in the peripheral circuit120executes a specific program code.

The signal generation circuit140retrieves digital data strings from a corresponding data source according to the events EV1˜EVn and then converts the digital data string to generate an analog output DAC_OUT. Taking the events EV1and EV2as an example, when the event EV1occurs, the signal generation circuit140retrieves a first string of data of a first data source and converts the first string of data to generate the analog output DAC_OUT. When the event EV2occurs, the signal generation circuit140retrieves a second string of data of a second data source and converts the second string of data to generate the analog output DAC_OUT.

Since the signal generation circuit140reads a corresponding data source according to the occurrence of the event, it does not need the intervention of the CPU110. Therefore, after initialing the peripheral circuit120, the CPU110can enter a power-down mode to reduce the power consumption. In other embodiments, when the signal generation circuit140operates, the CPU is in an idle state. Additionally, since the signal generation circuit140does not require support from the CPU110, the CPU110is capable of performing other operations. Therefore, the performance of the CPU110is increased.

Furthermore, since the signal generation circuit140generates the analog output according to the strings of data from different data sources, the signal generation circuit140is capable of generating waveforms with different slopes. For example, when the signal generation circuit140generates the analog output DAC_OUT according to many strings of data from a first data source, the analog output DAC_OUT has a first slope. When the signal generation circuit140generates the analog output DAC_OUT according to many strings of data from a second data source, the analog output DAC_OUT has a second slope. In this case, the first slope is different from the second slope.

The peripheral circuit130operates according to the analog output DAC_OUT. The type of analog output DAC_OUT is not limited in the present disclosure. In one embodiment, the analog output DAC_OUT is used as a reference voltage. In other embodiments, the micro-controller100further comprises a peripheral circuit150. The peripheral circuit150comprises a memory151and a control circuit152. In this case, the CPU110utilizes the set signal SS3to direct the control circuit152to access the memory151. The control circuit152moves a plurality of data strings stored in the memory151to a corresponding data source in the signal generation circuit140.

Assume that the memory151stores a first string of data, a second string of data, a third string of data, and a fourth string of data. The CPU110utilizes the set signal SS3to assign the first string of data and the third string of data to a first data source in the signal generation circuit140and assign the second string of data and the fourth string of data to a second data source in the signal generation circuit140. In one embodiment, the control circuit152may store the first string of data and the second string of data in the first and second data sources in the signal generation circuit140. Then, when the event EV1occurs, the signal generation circuit140reads and converts the first string of data stored in the first data source. When the signal generation circuit140starts to convert the first string of data, the control circuit152moves the third string of data to the first data source to replace the first string of data. At this time, if the event EV1occurs again, the signal generation circuit140reads and converts the third string of data stored in the first data source. However, if the event EV2occurs, the signal generation circuit140reads and converts the second string of data stored in the second data source. When the signal generation circuit140starts to convert the second string of data, the control circuit152moves the fourth string of data to the second data source to replace the second string of data.

The kind of memory151is not limited in the present disclosure. In one embodiment, the memory151is a static random access memory (SRAM). The structure of the control circuit152is not limited in the present disclosure. In one embodiment, the control circuit152is a peripheral direct memory access (PDAM) controller.

In an initial period, the CPU110utilizes the set signals SS1˜SS3to initialize the peripheral circuit120, the signal generation circuit140, and the peripheral circuit150. Then, in an operation period, the peripheral circuit120, the signal generation circuit140, and the peripheral circuit150operate according to the information which is provided by the CPU110in the initial period. In the operation period, the operations of the peripheral circuit120, the signal generation circuit140, and the peripheral circuit150do not require support from the CPU110.

FIG.2is a schematic diagram of an exemplary embodiment of the signal generation circuit according to various aspects of the present disclosure. As shown inFIG.2, the signal generation circuit200comprises control circuits210_1˜210_n, an arbiter circuit220, and a digital-to-analog converter (DAC) circuit230. Since the operations of control circuits210_1˜210_nare the same, the control circuits210_1and210_2are provided as an example. The control circuit210_1stores a first string of data. The control circuit210_2stores a second string of data. In one embodiment, the control circuit210_1serves as a first data source, and the control circuit210_2serves as a second data source. Additionally, the control circuit210_1receives the event EV1, and the control circuit210_2receives the event EV2. When the event EV1occurs, the control circuit210_1enables a trigger signal TR1. When the event EV2occurs, the control circuit210_2enables a trigger signal TR2.

The arbiter circuit220is coupled to the control circuits210_1˜210_nto receive the trigger signals TR1˜TRn. In this embodiment, the arbiter circuit220stores the order of priority. The order of priority relates with the priority weights of the control circuits210_1˜210_n. When many trigger signals are enabled, the arbiter circuit220reads a corresponding control circuit according to the order of priority to use the string of data stored in the corresponding control circuit as a digital input DGI. For example, assume that the control circuit210_1has the highest priority weight, the control circuit210_2has the second priority weight, and the control circuit210_nhas the lowest priority weight. In this case, when the trigger signals TR1and TR2are enabled, the arbiter circuit220reads the control circuit210_1to use the first string of data stored in the control circuit210_1as the digital input DGI.

In this embodiment, the arbiter circuit220further receive a notification signal NT. When the notification signal NT is enabled, the arbiter circuit220determines which trigger signal is enabled. If one trigger signal is enabled, the arbiter circuit220reads the string of data stored in the corresponding control circuit. If many trigger signal is enabled, the arbiter circuit220reads the string of data stored in the corresponding control circuit having the highest priority weight according to the order of priority. For example, if only trigger signal TR2is enabled, the arbiter circuit220reads the string of data stored in the control circuit2102to update the digital input DGI. The arbiter circuit220may directly use the second string of data stored in the control circuit210_2as the digital input DGI. However, after the notification signal NT is enabled, the trigger signals TR1and TR2may be enabled. In this case, since the priority weight of the control circuit210_1is higher than the priority weight of the control circuit210_2, the arbiter circuit220still reads the string of data stored in the control circuit210_1and uses the string of data stored in the control circuit210_1as the digital input DGI. In some embodiments, if only one trigger signal is enabled, the arbiter circuit220uses the string of data stored in the corresponding control circuit as the digital input DGI.

In one embodiment, after the arbiter circuit220uses the first string of data stored in the control circuit210_1as the digital input DGI, the arbiter circuit220stores the data string DT provided by the external peripheral circuit (e.g.,150) to the control circuit210_1to update the data string in the control circuit210_1. Since the CPU110has stored the data strings to be provided to the control circuits210_1˜210_nin the memory151, after the arbiter circuit220outputs the corresponding data string, the peripheral circuit150updates the data string of the corresponding control circuit via the arbiter circuit220. In other embodiments, the peripheral circuit150may directly provide the data string DT to the corresponding control circuit.

The DAC circuit230converts the digital input DGI to generate the analog output DAC_OUT. The structure of the DAC circuit230is not limited in the present disclosure. In this embodiment, the DAC circuit230comprises a controller231and a DAC232. The controller231generates output data DIN according to the digital input DGI. In one embodiment, the controller231is a DAC controller. The DAC232converts the input data DIN to generate the analog output DAC_OUT. In one embodiment, the DAC232is a resistive DAC (RDAC).

In other embodiments, the controller231comprises a counter circuit233. When the DAC232starts to convert the input data DIN, the counter circuit233performs a counting operation. When the duration for which the counter circuit233performs the counting operation arrives a set time (e.g., 5 sec), it means that the DAC232finishes the conversion operation. Therefore, the counter circuit233enables the notification signal NT to direct the arbiter circuit220to read the corresponding control circuit according to the trigger signals TR1˜TRn and the priority weights of the control circuits210_1˜210_n. In some embodiments, the counter circuit233may be disposed independent of the controller231.

In one embodiment, the controller231further provides a power-down signal pd to the DAC232. When the power-down signal pd is enabled, the DAC232stops operating. At this time, the DAC232may enter a power-down mode. Additionally, the controller231may provide a turning-on signal EN to activate the DAC232.

In other embodiments, the DAC232further receives operation voltages AVDD, DVDD, AGND, and DGND. The operation voltages AVDD and AGND are provided to the analog elements in the DAC232. The operation voltage AVDD is higher than the operation voltage AGND. The operation voltages DVDD and DGND are provided to the digital elements in the DAC232. The operation voltage DVDD is higher than the operation voltage DGND.

In some embodiments, the DAC232further receives a power-on control signal PON. When the operation voltages AVDD, DVDD, AGND, and DGND are unstable, the power-on control signal PON is disabled. Therefore, the DAC232does not operate. When the operation voltages AVDD, DVDD, AGND, and DGND are stable, the power-on control signal PON is enabled. Therefore, the DAC232starts to operate.

In other embodiments, the DAC232further receives reference voltages VREFP and VREFM. The reference voltage VREFP may be provided from a specific pin234. The DAC232may comprise a resistor string. The resistor string receives the reference voltages VREFP and VREFM and divides the reference voltage VREFP to generate many divided voltages. In one embodiment, the DAC232selects a corresponding divided voltage according to the input data DIN and serves the corresponding divided voltage as the analog output DAC_OUT.

In an initial period, the CPU110activates the DAC circuit230. Therefore, the DAC circuit230starts operate. In an operation period, the CPU does not intervene the operations of the control circuits210_1˜210_n, the arbiter circuit220, and the DAC circuit230. In this period, the CPU110may operate in a power-down mode. In other embodiments, when the control circuits210_1˜210_n, the arbiter circuit220, and the DAC circuit230operate, the CPU110is in an idle state.

Additionally, in the operation period, when the trigger signal TR1is enabled and the trigger signals TR2˜TRn are not enabled, the arbiter circuit220reads the control circuit210_1to retrieve the string of data (referred to as first string of data) stored in the control circuit210_1and serve the string of data stored in the control circuit210_1as the digital input DGI. At this time, when the arbiter circuit220serves the first string of data as the digital input DGI, the control circuit210_1reads and stores the string of data (referred to as a third string of data) stored in an external memory (e.g.,151).

In the operation period, when the trigger signal TR2is enabled and the trigger signals TR1and TR3˜TRn are not enabled, the arbiter circuit220reads the control circuit210_2to retrieve the string of data (referred to as a second string of data) stored in the control circuit210_2and serve the second string of data as the digital input DGI. At this time, when the arbiter circuit220serves the second string of data as the digital input DGI, the control circuit210_2reads and stores the string of data (referred to as a fourth string of data) stored in the external memory.

FIG.3is a flowchart of an exemplary embodiment of a control method of the micro-controller according to various aspects of the present disclosure. In an initial period310, step S311is performed. In an operation period, steps S321˜323are performed. Step S311is to set a peripheral circuit by a CPU and activate a DAC circuit. Step S321is to write the string of data into a corresponding control circuit. Step S322is to determine whether an event occurs. When an event occurs, step S323reads and convers the string of data stored in a corresponding control circuit.

TakingFIG.1as an example, the CPU110sets the peripheral circuit120and activates the DAC circuit of the signal generation circuit140in step S311. The invention does not limit how the CPU110sets the peripheral circuit120. In one embodiment, the CPU110sets the values of the registers of the peripheral circuit120. In this case, the peripheral circuit120operates according to the values of registers.

TakingFIG.2as an example, step S321writes the strings of data into the control circuits210_1˜210_n. Step S322determines whether the events EV1˜EVn occur according to the trigger signals TR1˜TRn. For example, when the trigger signal TR1is enabled, it means that the event EV1occurs. Similarly, when the trigger signal TR2is enabled, it means that the event EV2occurs. Step S323converts the corresponding string of data according to the occurrence of the event to generate an analog output. For example, when the event EV1occurs and the events EV2˜EVn do not occur, the arbiter circuit220serves the string of data (referred to as a first string of data) of the control circuit210_1as a digital input DGI. The DAC circuit230converts the digital input DGI to generate the analog output DAC_OUT. Similarly, if only the event EV2occurs, the arbiter circuit220serves the string of data (referred to as a second string of data) of the control circuit210_2as a digital input DGI.

However, when many trigger signals are enabled, step S323reads a corresponding control circuit according to the order of priority. For example, when the trigger signals TR1and TR2are enabled, if the order of priority indicates that the priority weight of the control circuit210_1is higher than the priority weight of the control circuit210_2, the arbiter circuit220serves the string of data stored in the control circuit210_1, which has a high priority weight as the digital input DGI. In this case, the order of priority may be stored outside of the arbiter circuit220or stored in a memory disposed outside of the arbiter circuit220. In other embodiments, after the arbiter circuit220serves the string of data stored in the control circuit210_1as the digital input DGI, if the trigger signals TR1and TR2are still enabled, the arbiter circuit220serves the string of data stored in the control circuit210_1as the digital input DGI again. In this case, after the arbiter circuit220serves the string of data stored in the control circuit210_1as the digital input DGI, if only the trigger signal TR2is enabled, the arbiter circuit220serves the string of data stored in the control circuit210_2as the digital input DGI.

In this embodiment, the operations of steps S321˜S323do not require support from the CPU110in the operation period320. Therefore, the CPU can enter an idle mode or an power-down mode in the operation period320. In other embodiments, when the DAC circuit230converts the digital input DGI, step S323updates the string of data stored in the corresponding control circuit.

For example, when the arbiter circuit220serves the string of data stored in the control circuit210_1as the digital input DGI, step S323writes a new string of data (referred to as a third string of data) to the control circuit210_1. Similarly, when the arbiter circuit220serves the string of data stored in the control circuit210_2as the digital input DGI, step S323writes a new string of data (referred to as a fourth string of data) in the control circuit210_2.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). For example, it should be understood that the system, device and method may be realized in software, hardware, firmware, or any combination thereof. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.