Data storage device for processing a sequential unmap entry by using trim instruction data and operating method thereof

A data storage device includes a nonvolatile memory device and a memory having an unmap command queue configured to store an unmap command received from a host, and a sequential unmap table configured to store a sequential unmap entry corresponding to an unmap command for sequential logical addresses, and a controller including a first core and a second core. The second core configured to read an unmap-target map segment including the sequential logical addresses from an address mapping table stored in the nonvolatile memory device, store the read unmap-target map segment in the memory, and change, within the stored unmap-target map segment, physical addresses mapped to the sequential logical addresses to trim instruction data at the same time, the trim instruction data being included in the sequential map entry.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2019-0001718, filed on Jan. 7, 2019, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to an electronic device, and more particularly, to a data storage device and an operating method thereof.

2. Related Art

Recently, the paradigm for the computing environment has changed to a ubiquitous computing environment in which computer systems can be used anytime and anywhere. Therefore, the use of portable electronic devices such as mobile phones, digital cameras and notebook computers has rapidly increased. Such potable electronic devices generally use a data storage device using a memory device. The data storage device is used to store data which are used in the portable electronic devices.

Since a data storage device using a memory device has no mechanical driver, the data storage device has excellent stability, excellent durability, high information access speed, and low power consumption. The data storage device having such advantages includes a universal serial bus (USB) memory device, a memory card having various interfaces, a universal flash storage (UFS) device, and a solid state drive (SSD).

SUMMARY

Various embodiments are directed to a data storage device capable of effectively shortening or reducing an unmap operation time and an operating method thereof.

In an embodiment, a data storage device may include: a nonvolatile memory device; a memory including an unmap command queue configured to store an unmap command received from a host, and a sequential unmap table configured to store a sequential unmap entry corresponding to an unmap command for sequential logical addresses; and a controller including a first core configured to receive the unmap command transferred from the host and store the received unmap command in the unmap command queue of the memory; and a second core configured to read an unmap-target map segment including the sequential logical addresses from an address mapping table stored in the nonvolatile memory device, store the read unmap-target map segment in the memory, and change, within the stored unmap-target map segment, physical addresses mapped to the sequential logical addresses to trim instruction data at the same time, the trim instruction data being included in the sequential map entry.

In an embodiment, there is provided an operating method for a data storage device which includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device. The operating method may include: reading an unmap-target map segment including sequential logical addresses from an address mapping table stored in the nonvolatile memory device when a map update operation is triggered, and storing the read unmap-target map segment in a memory; and changing, within the stored unmap-target map segment, physical addresses mapped to the sequential logical addresses to trim instruction data at the same time, the trim instruction data being included in a sequential unmap entry corresponding to the sequential logical addresses.

In an embodiment, there is provided an operating method for a data storage device. The operating method may include: generating a single piece of trim data for a group of sequential logical addresses; and unmapping a mapping relationship of the group by collectively changing physical addresses, which are mapped to the group, to the single piece in a batch processing way.

DETAILED DESCRIPTION

Hereinafter, a data storage device and an operating method thereof according to the present disclosure will be described below with reference to the accompanying drawings through exemplary embodiments.

FIG. 1illustrates a configuration of a data storage device10in accordance with an embodiment.

Referring toFIG. 1, the data storage device10in accordance with the present embodiment may store data accessed by a host (not illustrated) such as a mobile phone, MP3 player, laptop computer, desktop computer, game machine, TV, or in-vehicle infotainment system. The data storage device10may be referred to as a memory system.

The data storage device10may be fabricated as any one of various storage devices, according to an interface protocol coupled to the host. For example, the data storage device10may be configured as any one of various types of storage devices which include a solid state drive (SSD), a multi-media card (MMC) such as an eMMC, RS-MMC or micro-MMC, a secure digital (SD) card such as a mini-SD or micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnection (PCI) card-type storage device, a PCI express (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card and a memory stick.

The data storage device10may be fabricated as any one of various types of packages. For example, the data storage device10may be fabricated as any one of various types of packages such as a package-on-package (POP), a system-in-package (SIP), a system-on-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabricated package (WFP) and a wafer-level stack package (WSP).

The data storage device10may include a nonvolatile memory device100and a controller200.

The nonvolatile memory device100may operate as a storage medium of the data storage device10. The nonvolatile memory device100may be configured as any one of various types of nonvolatile memory devices such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase change random access memory (PRAM) using chalcogenide alloys, and a resistive random access memory (ReRAM) using transition metal oxide, depending on memory cells.

For simplification of the drawing,FIG. 1illustrates the nonvolatile memory device100as one block, but the nonvolatile memory device100may include a plurality of memory chips. The present embodiment may also be applied in the same manner to the data storage device10including the nonvolatile memory device100constituted by a plurality of memory chips.

The nonvolatile memory device100may include a memory cell array (not illustrated) having a plurality of memory cells arranged at the respective intersections between a plurality of bit lines (not illustrated) and a plurality of word lines (not illustrated). The memory cell array may include a plurality of memory blocks, and each of the memory blocks may include a plurality of pages.

For example, each memory cell of the memory cell array may be configured as a single level cell (SLC) for storing 1-bit data, a multi-level cell (MLC) for storing 2-bit data, a triple level cell (TLC) for storing 3-bit data, or a quadruple level cell (QLC) for storing 4-bit data. The memory cell array110may include one or more of the SLC, the MLC, the TLC and the QLC. For example, the memory cell array110may include memory cells with a two-dimensional horizontal structure and memory cells with a three-dimensional vertical structure.

The controller200may control overall operations of the data storage device10. The controller200may process requests received from the host. The controller200may generate control signals for controlling an operation of the nonvolatile memory device100based on the requests received from the host, and provide the generated control signals to the nonvolatile memory device100. The controller200may include a first core210, a memory220and a second core230.

The first core210may be configured to interface the host and the data storage device10in response to a protocol of the host. Therefore, the first core210may be referred to as a protocol core. For example, the first core210may communicate with the host through any one protocol of USB (universal serial bus), UFS (universal flash storage), MMC (multimedia card), PATA (parallel advanced technology attachment), SATA (serial advanced technology attachment), SCSI (small computer system interface), SAS (serial attached SCSI), PCI (peripheral component interconnection) and PCIe (PCI express).

The first core210may include a micro control unit (MCU) and a central processing unit (CPU). The first core210may receive commands transferred from the host, and provide the received commands to the second core230.

The first core210may store data (for example, write data) received from the host in a write buffer of the memory220. For this operation, the controller200may further include a separate data transfer block (not illustrated) for transferring the data received from the host to the write buffer of the memory220. For example, the data transfer block may receive data from the host according to a control signal received from the first core210, and store the received data in the write buffer of the memory220.

The first core210may transfer data (for example, read data) stored in a read buffer of the memory220to the host. For example, the data transfer block may read the data stored in the read buffer of the memory220according to the control signal received from the first core210, and transfer the read data to the host.

The first core210may generate a descriptor based on a command received from the host, and provide the generated descriptor to the second core230. The descriptor may indicate a statement of work, which includes information required for the second core230to process the command received from the host.

When an unmap command is received from the host, the first core210may queue the received unmap command in an unmap command queue (which will be described with reference toFIGS. 2 and 3) allocated in a command queue of the memory220.

The memory220may be configured as a RAM such as a static RAM (SRAM), but it not limited thereto. The memory220may be physically and electrically coupled to the first and second cores220and230. The memory220may store the firmware driven by the second core230. Furthermore, the memory220may store data required for driving the firmware, for example, metadata. That is, the memory220may operate as a working memory of the second core230.

The memory220may include a buffer for temporarily storing write data to be transferred to the nonvolatile memory device100from the host or read data to be transferred to the host from the nonvolatile memory device100. That is, the memory220may operate as a buffer memory. The internal configuration of the memory220will be described in detail with reference toFIG. 2.

The second core230may control overall operations of the data storage device10by driving firmware or software loaded to the memory220. The second core230may decode and drive a code-based instruction or algorithm such as firmware or software. Therefore, the second core230may also be referred to as a flash translation layer (FTL) core. The second core230may include a micro control unit (MCU) and a central processing unit (CPU).

The second core230may generate control signals for controlling an operation of the nonvolatile memory device100based on the command provided through the first core210, and provide the generated control signals to the nonvolatile memory device100. The control signals may include a command, address and operation control signal for controlling the nonvolatile memory device100. The second core230may provide write data to the nonvolatile memory device100, or receive read data from the nonvolatile memory device100.

The second core230may further include an error correction code (ECC) circuit which generates parity data by performing ECC encoding on write data provided from the host, and performs ECC decoding on data read from the nonvolatile memory device100using the parity data.

Referring toFIG. 2, the memory220in accordance with the present embodiment may be divided into first and second regions, but the present embodiment is not limited thereto. For example, the first region of the memory220may store software analyzed and driven by the second core230and metadata required for the second core230to perform a computation and processing operation, and the second region of the memory220may include buffers for temporarily storing write data, read data, map data and the like. However, the present embodiment is not limited thereto. For example, a distance between the first region of the memory220and each of the first and second cores210and230may be smaller than a distance between the second region of the memory220and each of the first and second cores210and230, but the present embodiment is not limited thereto. As the first region of the memory220is located physically close to the first and second cores210and230, the first and second cores210and230may quickly access the first region of the memory220.

For example, the first region of the memory220may store the FTL. The FTL may indicate software driven by the second core230, and the second core230may drive the FTL to control a unique operation of the nonvolatile memory device100, and provide device compatibility to the host. As the FTL is driven, the host may recognize and use the data storage device10as a general data storage device such as a hard disk.

The FTL may include modules for performing various functions. For example, the FTL may include a read module, a write module, a garbage collection module, a wear-leveling module, a bad block management module, a map module and the like. The FTL may be stored in a system region (not illustrated) of the nonvolatile memory device100. When the data storage device10is powered on, the FTL may be read from the system region of the nonvolatile memory device100and loaded to the first region of the memory220. The FTL loaded to the first region of the memory220may be loaded to a memory (not illustrated) which is dedicated to the second core230and separately provided inside or outside the second core230.

The first region of the memory220may include a meta region for storing metadata required for driving various modules included in the FTL. The meta region may store a sequential unmap table (SUT) generated by the second core230. The SUT will be described with reference toFIG. 4.

The first region of the memory220may include a command (CMD) queue in which commands received from the host are queued. The command queue may include a plurality of command queues which are divided according to the attributes of the commands. The first core210may queue the commands received from the host in the corresponding command queues according to the attributes of the commands.

The second region of the memory220may include a write buffer, a read buffer, a map update buffer and the like.

The write buffer may be configured to temporarily store write data to be transferred to the nonvolatile memory device100from the host. The read buffer may be configured to temporarily store read data which is read from the nonvolatile memory device100and will be transferred to the host. The map update buffer may be configured to temporarily store a map segment whose mapping information is to be updated.

FIG. 3is a diagram illustrating the command queue ofFIG. 2.

As described above, the command queue may include a plurality of command queues. For example, as illustrated inFIG. 3, the command queue may include a write command queue in which write commands are queued, a read command queue in which read commands are queued, and an unmap command queue in which unmap commands are queued. For convenience of description,FIG. 3illustrates three command queues in which three types of commands are queued, but the present embodiment is not limited thereto.

When unmap commands are received from the host, the first core210may sequentially queue the received unmap commands in the unmap command queue. At this time, although not specifically illustrated inFIG. 3, each of the queued unmap commands may correspond to logical addresses, which run without discontinuity from a start logical address. Each of the queued unmap commands may include a start logical address Start LBA and length information (or data size information) Length of the corresponding logical addresses. The length information Length may correspond to a total number of the corresponding logical addresses. The data size information may correspond to the sum of data sizes stored in storage regions indicated by the corresponding logical addresses.

The unmap commands received from the host may be classified into random unmap commands and sequential unmap commands according to the length information (or data size information) of the corresponding logical addresses. For example, the second core230may determine that an unmap command whose length information (or data size information) of the corresponding logical addresses is equal to or more than a preset threshold value, among the unmap commands queued in the unmap command queue, is a sequential unmap command.

The logical addresses corresponding to the sequential unmap command may be sequential logical addresses having a greater length or data size than the preset threshold value. In an embodiment, the logical addresses corresponding to the sequential unmap command may be those in one or more map segments, which will be described with reference toFIG. 6.

FIG. 4is a diagram illustrating the sequential unmap table (SUT) in accordance with the present embodiment.

As described above, the second core230may determine whether each of the unmap commands queued in the unmap command queue is a sequential unmap command based on the length information (or data size information) included in the unmap command. As illustrated inFIG. 4, the second core230may generate sequential unmap entries corresponding to the sequential unmap commands, and generate the SUT composed of one or more sequential unmap entries. The second core230may store the SUT in the meta region of the first region of the memory220, but the present embodiment is not limited thereto. The second core230may store the SUT in a random region of the memory220.

Referring toFIG. 4, each of the sequential unmap entries may include fields of a start logical address Start LBA of the sequential logical addresses corresponding to the sequential unmap command, length information Length of the sequential logical addresses and trim instruction data. The trim instruction data may have any predetermined pattern having a format of a physical address. For example, the trim instruction data indicates address-type data in which a trim bit is set to a ‘set’ state, and the other bits except the trim bit are set to zero (0). The trim instruction data may replace physical addresses mapped to the sequential logical addresses corresponding to the sequential unmap command. Trimming may indicate removing a mapping relationship between a logical address and a physical address.

For example, when the trim instruction data includes 32 bits, one specific bit of the 32 bits may be used as the trim bit. For example, the trim bit having a first value may indicate removing (i.e., trimming) of the relationship between a logical address and a physical address. For example, the trim bit having a second value may indicate keeping of the relationship between a logical address and a physical address. The first value may be set to ‘1’, and the second value may be set to ‘0’. However, the present embodiment is not limited thereto. In the present embodiment, the case in which ‘1’ is used as the first value will be taken as an example for description.

Referring toFIGS. 3 and 4, when unmap commands Unmap CMD1to Unmap CMD3are all sequential unmap commands, the second core230may generate sequential unmap entries corresponding to the respective unmap commands Unmap CMD1to Unmap CMD3, and generate the SUT composed of the sequential unmap entries. For example, trim instruction data included in each of the sequential unmap entries may have a value of ‘0x00000001’. This may indicate an example in which the zeroth bit of the trim instruction data including 32 bits is used as the trim bit, and the other bits except the trim bit, i.e. the first to 31st bits, are set to ‘0’.

FIG. 5is a diagram illustrating an address mapping table.

Although not illustrated inFIG. 1, the nonvolatile memory device100may include the address mapping table illustrated inFIG. 5.

Referring toFIG. 5, the address mapping table may include a plurality of map segments. Each of the map segments may include a plurality of logical to physical (L2P) entries. Each of the L2P entries may include one physical address mapped to one logical address. The logical addresses included in each of the map segments may be sorted and fixed in ascending order, and physical addresses mapped to the respective logical addresses may be updated. For convenience of description,FIG. 5illustrates an example in which the address mapping table includes 100 map segments 0 to 99, and each of the map segments 0 to 99 includes 100 L2P entries. However, the number of the map segments and the number of the L2P entries are not specifically limited thereto.

FIG. 6is a diagram illustrating a process of trimming mapping information of sequential logical addresses. Here, ‘mapping information’ may indicate information including logical addresses and physical addresses mapped to the logical addresses. For example, ‘mapping information’ may indicate L2P information.

When a map update operation is triggered, the second core230may read a map segment to be updated, among the map segments stored in the address mapping table of the nonvolatile memory device100, and store the read map segment in the map update buffer of the memory220. The map update operation may be triggered under various conditions including the case in which a P2L (Physical-to-Logical) table included in the meta region of the memory220is full or the case in which a request is provided from the host. However, the present embodiment is not limited thereto, and the map update operation may be triggered under various conditions, according to design and need.

In general, the map update operation may be performed through a series of processes of reading a map segment to be updated from the address mapping table, storing the read map segment in the map update buffer of the memory220, changing physical addresses mapped to logical addresses by referring to the P2L table, and storing the map segment, whose physical addresses have been changed, in the address mapping table again.

During the map update operation, a map segment to be unmapped may be trimmed. Hereafter, the map segment to be unmapped will be referred to as an unmap-target map segment. For example, the second core230may read the unmap-target map segment (for example, ‘map segment 0’) among the map segments stored in the address mapping table of the nonvolatile memory device100, and store the read map segment in the map update buffer of the memory220.

Referring toFIG. 6, each region of the ‘map segment 0’ stored in the map update buffer may correspond to one logical address, and a value stored in each region may indicate a physical address currently mapped to the logical address of a corresponding region. Referring toFIGS. 4 and 5, the map segment 0 stored in the map update buffer inFIG. 6may correspond to the first unmap command Unmap CMD1.

The second core230may refer to the SUT ofFIG. 4, in order to trim the logical addresses ‘LBA0to LBA99’ of the ‘map segment 0’ stored in the map update buffer. For example, the second core230may check a sequential unmap entry corresponding to the first unmap command Unmap CMD1in the SUT, and replace all physical addresses in all regions (i.e., regions from the first region corresponding to ‘LBA0’ to the last region corresponding to ‘LBA99’) with the trim instruction data (i.e., ‘0x00000001’) within the map segment 0.

Therefore, data of which the trim bit is T and the other bits are ‘0’ may be stored in all the regions of the ‘map segment 0’ stored in the map update buffer. For example, the operation of replacing the physical addresses with the trim instruction data of ‘0x00000001’ in all the regions of the ‘map segment 0’ may be performed through a memset function. The memset function may store the same values (i.e., the value ‘0x00000001’ of the trim instruction data) in all regions within a preset space (e.g., the map segment 0) at the same time, according to variables such as the start region (e.g., the first region corresponding to ‘LBA0’), a value (e.g., the value ‘0x00000001’ of the trim instruction data) to be stored in the preset space (e.g., the map segment 0), and the size (e.g., 100 corresponding to LBA0to LBA99) of the preset space (e.g., the map segment 0).

For example, the second core230may replace the physical addresses with the trim instruction data of ‘0x00000001’ in the regions ‘LBA0to LBA99’ of the ‘map segment 0’ at a same time, using the memset function.

When the replacement of the physical addresses with the trim instruction data of ‘0x00000001’ is completed in all the regions of the ‘map segment 0’, the second core230may store the trimmed ‘map segment 0’, in which the physical addresses are replaced with the trim instruction data of ‘0x00000001’, in the nonvolatile memory device100. Therefore, the trimming process for the ‘map segment 0’ may be completed.

As described above, the data storage device may generate a sequential unmap entry corresponding to sequential logical addresses when an unmap request for the sequential logical addresses is provided, and may unmap mapping information of the sequential logical addresses through collective change of physical addresses mapped to the sequential logical addresses to a single piece of trim instruction data at a same time (i.e., in a batch processing way) by using the sequential unmap entry during the map update operation, thereby shortening the time required for the trimming process.

FIG. 7is a flowchart illustrating an operating method of the data storage device in accordance with an embodiment. While the operating method of the data storage device10in accordance with the present embodiment is described with reference toFIG. 7, one or more ofFIGS. 1 to 6may be referred to.

In step S710, the second core230of the controller200may determine whether the current condition has reached a condition to trigger a map update operation. Since the condition to trigger the map update operation has been described above, the detailed descriptions thereof will be omitted herein. When the current condition reaches the condition to trigger the map update operation, the process may proceed to step S720.

In step S720, the second core230may read an unmap-target map segment including logical addresses from the address mapping table of the nonvolatile memory device100, and store the read map segment in the map update buffer of the memory220.

As described above, each of the unmap commands may correspond to logical addresses, which run without discontinuity from a start logical address. Each of the unmap commands may include a start logical address Start LBA and length information (or data size information) Length of the corresponding logical addresses. The second core230may determine that an unmap command whose length information (or data size information) of the corresponding logical addresses is equal to or more than a preset threshold value, among the unmap commands queued in the unmap command queue, is a sequential unmap command. The logical addresses corresponding to the sequential unmap command may be sequential logical addresses having a greater length or data size than the preset threshold value.

In step S730, the second core230may replace, in response to the sequential unmap command, all physical addresses in all regions (e.g., regions from the first region corresponding to ‘LBA0’ to the last region corresponding to ‘LBA99’) with the trim instruction data (e.g., ‘0x00000001’) within the unmap-target map segment stored in the map update buffer using the memset function. The trim instruction data may have a trim bit of ‘1’ and the other bits of ‘0’. The trim instruction data of the respective logical addresses to be trimmed, included in the unmap-target map segment, may be equal to one another.

In step S740, the second core230may store the trimmed unmap-target map segment in the nonvolatile memory device100. Therefore, the unmap operation for the unmap-target map segment may be completed.

In accordance with the present embodiments, the data storage device and the operating method thereof may generate a sequential unmap entry corresponding to an unmap request for sequential logical addresses, and trim mapping information of the sequential logical addresses using the sequential unmap entry at the same time, thereby shortening the unmap operation time.

FIG. 8illustrates a data processing system including a solid state drive (SSD) in accordance with an embodiment. Referring toFIG. 8, a data processing system2000may include a host apparatus2100and a SSD2200.

The SSD2200may include a controller2210, a buffer memory device2220, nonvolatile memory devices2231to223n, a power supply2240, a signal connector2250, and a power connector2260.

The controller2210may control an overall operation of the SSD2220.

The buffer memory device2220may temporarily store data to be stored in the nonvolatile memory devices2231to223n. The buffer memory device2220may temporarily store data read from the nonvolatile memory devices2231to223n. The data temporarily stored in the buffer memory device2220may be transmitted to the host apparatus2100or the nonvolatile memory devices2231to223naccording to control of the controller2210.

The nonvolatile memory devices2231to223nmay be used as a storage medium of the SSD2200. The nonvolatile memory devices2231to223nmay be coupled to the controller2210through a plurality of channels CH1to CHn. One or more nonvolatile memory devices may be coupled to one channel. The nonvolatile memory devices coupled to the one channel may be coupled to the same signal bus and the same data bus.

The power supply2240may provide power PWR input through the power connector2260to the inside of the SSD2200. The power supply2240may include an auxiliary power supply2241. The auxiliary power supply2241may supply the power so that the SSD2200is normally terminated even when sudden power-off occurs. The auxiliary power supply2241may include large capacity capacitors capable of charging the power PWR.

The controller2210may exchange a signal SGL with the host apparatus2100through the signal connector2250. The signal SGL may include a command, an address, data, and the like. The signal connector2250may be configured of various types of connectors according to an interfacing method between the host apparatus2100and the SSD2200.

FIG. 9illustrates the controller2210ofFIG. 9. Referring toFIG. 8, the controller2210may include a host interface unit2211, a control unit2212, a random access memory (RAM)2213, an error correction code (ECC) unit2214, and a memory interface unit2215.

The host interface unit2211may perform interfacing between the host apparatus2100and the SSD2200according to a protocol of the host apparatus2100. For example, the host interface unit2211may communicate with the host apparatus2100through any one among a secure digital protocol, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, an embedded MMC (eMMC) protocol, a personal computer memory card international association (PCMCIA) protocol, a parallel advanced technology attachment (PATH) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface (SCSI) protocol, a serial attached SCSI (SAS) protocol, a peripheral component interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, and a universal flash storage (UFS) protocol. The host interface unit2211may perform a disc emulation function that the host apparatus2100recognizes the SSD2200as a general-purpose data storage apparatus, for example, a hard disc drive HDD.

The control unit2212may analyze and process the signal SGL input from the host apparatus2100. The control unit2212may control operations of internal functional blocks according to firmware and/or software for driving the SDD2200. The RAM2213may be operated as a working memory for driving the firmware or software.

The ECC unit2214may generate parity data for the data to be transferred to the nonvolatile memory devices2231to223n. The generated parity data may be stored in the nonvolatile memory devices2231to223ntogether with the data. The ECC unit2214may detect errors for data read from the nonvolatile memory devices2231to223nbased on the parity data. When detected errors are within a correctable range, the ECC unit2214may correct the detected errors.

The memory interface unit2215may provide a control signal such as a command and an address to the nonvolatile memory devices2231to223naccording to control of the control unit2212. The memory interface unit2215may exchange data with the nonvolatile memory devices2231to223naccording to control of the control unit2212. For example, the memory interface unit2215may provide data stored in the buffer memory device2220to the nonvolatile memory devices2231to223nor provide data read from the nonvolatile memory devices2231to223nto the buffer memory device2220.

FIG. 10illustrates a data processing system including a data storage apparatus in accordance with an embodiment. Referring toFIG. 10, a data processing system3000may include a host apparatus3100and a data storage apparatus3200.

The host apparatus3100may be configured in a board form such as a printed circuit board (PCB). Although not shown inFIG. 10, the host apparatus3100may include internal functional blocks configured to perform functions of the host apparatus3100.

The host apparatus3100may include a connection terminal3110such as a socket, a slot, or a connector. The data storage apparatus3200may be mounted on the connection terminal3110.

The data storage apparatus3200may be configured in a board form such as a PCB. The data storage apparatus3200may refer to a memory module or a memory card. The data storage apparatus3200may include a controller3210, a buffer memory device3220, nonvolatile memory devices3231to3232, a power management integrated circuit (PMIC)3240, and a connection terminal3250.

The controller3210may control an overall operation of the data storage apparatus3200. The controller3210may be configured to have the same configuration as the controller2210illustrated inFIG. 9.

The buffer memory device3220may temporarily store data to be stored in the nonvolatile memory devices3231and3232. The buffer memory device3220may temporarily store data read from the nonvolatile memory devices3231and3232. The data temporarily stored in the buffer memory device3220may be transmitted to the host apparatus3100or the nonvolatile memory devices3231and3232according to control of the controller3210.

The nonvolatile memory devices3231and3232may be used as a storage medium of the data storage apparatus3200.

The PMIC3240may provide power input through the connection terminal3250to the inside of the data storage apparatus3200. The PMIC3240may manage the power of the data storage apparatus3200according to control of the controller3210.

The connection terminal3250may be coupled to the connection terminal3110of the host apparatus3100. A signal such as a command, an address, and data and power may be transmitted between the host apparatus3100and the data storage apparatus3200through the connection terminal3250. The connection terminal3250may be configured in various forms according to an interfacing method between the host apparatus3100and the data storage apparatus3200. The connection terminal3250may be arranged in any one side of the data storage apparatus3200.

FIG. 11illustrates a data processing system including a data storage apparatus in accordance with an embodiment. Referring toFIG. 11, a data processing system4000may include a host apparatus4100and a data storage apparatus4200.

The host apparatus4100may be configured in a board form such as a PCB. Although not shown inFIG. 11, the host apparatus4100may include internal functional blocks configured to perform functions of the host apparatus4100.

The data storage apparatus4200may be configured in a surface mounting packaging form. The data storage apparatus4200may be mounted on the host apparatus4100through a solder ball4250. The data storage apparatus4200may include a controller4210, a buffer memory device4220, and a nonvolatile memory device4230.

The controller4210may control an overall operation of the data storage apparatus4200. The controller4210may be configured to have the same configuration as the controller2210illustrated inFIG. 9.

The buffer memory device4220may temporarily store data to be stored in the nonvolatile memory device4230. The buffer memory device4220may temporarily store data read from the nonvolatile memory device4230. The data temporarily stored in the buffer memory device4220may be transmitted to the host apparatus4100or the nonvolatile memory device4230through control of the controller4210.

The nonvolatile memory device4230may be used as a storage medium of the data storage apparatus4200.

FIG. 12illustrates a network system5000including a data storage apparatus in accordance with an embodiment. Referring toFIG. 12, the network system5000may include a server system5300and a plurality of client systems5410to5430which are coupled through a network5500.

The server system5300may serve data in response to requests of the plurality of client systems5410to5430. For example, the server system5300may store data provided from the plurality of client systems5410to5430. In another example, the server system5300may provide data to the plurality of client systems5410to5430.

The server system5300may include a host apparatus5100and a data storage apparatus5200. The data storage apparatus5200may be configured of the data storage device10ofFIG. 1, the SSD2200ofFIG. 8, the data storage apparatus3200ofFIG. 10, or the data storage apparatus4200ofFIG. 11.

FIG. 13illustrates a nonvolatile memory device included in a data storage apparatus in accordance with an embodiment. Referring toFIG. 13, a nonvolatile memory device100may include a memory cell array110, a row decoder120, a column decoder140, a data read/write block130, a voltage generator150, and a control logic160.

The memory cell array110may include memory cells MC arranged in regions in which word lines WL1to WLm and bit lines BL1to BLn cross to each other.

The row decoder120may be coupled to the memory cell array110through the word lines WL1to WLm. The row decoder120may operate through control of the control logic160. The row decoder120may decode an address provided from an external apparatus (not shown). The row decoder120may select and drive the word lines WL1to WLm based on a decoding result. For example, the row decoder120may provide a word line voltage provided from the voltage generator150to the word lines WL1to WLm.

The data read/write block130may be coupled to the memory cell array110through the bit lines BL1to BLn. The data read/write block130may include read/write circuits RW1to RWn corresponding to the bit lines BL1to BLn. The data read/write block130may operate according to control of the control logic160. The data read/write block130may operate as a write driver or a sense amplifier according to an operation mode. For example, the data read/write block130may operate as the write driver configured to store data provided from an external apparatus in the memory cell array110in a write operation. In another example, the data read/write block130may operate as the sense amplifier configured to read data from the memory cell array110in a read operation.

The column decoder140may operate though control of the control logic160. The column decoder140may decode an address provided from an external apparatus (not shown). The column decoder140may couple the read/write circuits RW1to RWn of the data read/write block130corresponding to the bit lines BL1to BLn and data input/output (I/O) lines (or data I/O buffers) based on a decoding result.

The voltage generator150may generate voltages used for an internal operation of the nonvolatile memory device100. The voltages generated through the voltage generator150may be applied to the memory cells of the memory cell array110. For example, a program voltage generated in a program operation may be applied to word lines of memory cells in which the program operation is to be performed. In another example, an erase voltage generated in an erase operation may be applied to well regions of memory cells in which the erase operation is to be performed. In another example, a read voltage generated in a read operation may be applied to word lines of memory cells in which the read operation is to be performed.

The control logic160may control an overall operation of the nonvolatile memory device100based on a control signal provided from an external apparatus. For example, the control logic160may control an operation of the nonvolatile memory device100such as a read operation, a write operation, an erase operation of the nonvolatile memory device100.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the data storage device and the operating method thereof, which have been described herein, should not be limited based on the described embodiments.