The disclosure relates to the field of semiconductor technologies, and to a semiconductor structure and a method for forming the same, and a memory. The semiconductor structure of the disclosure includes a substrate, a word line structure, a conductive contact structure and a buffer layer. The substrate includes an active area; the active area includes a channel area, and a source area and a drain area that are respectively distributed on two sides of the channel area; the channel area has a word line groove; the word line structure is located in the word line groove; the conductive contact structure is connected to a top of the drain area; and the buffer layer is located between the conductive contact structure and the word line structure.

BACKGROUND

A Dynamic Random Access Memory (DRAM) is widely applied to mobile devices such as mobile phones and tablet computers due to its advantages of small size, high degree of integration and fast transmission speed.

With the advancing of a semiconductor technology, the miniaturization of a DRAM related space size greatly facilitates the saving of costs and the creation of benefits. The size of a DRAM is positively correlated to the reliability of the DRAM, so that how to ensure that the performance of the DRAM is not affected or even better while the size of the DRAM is miniaturized becomes a research hotspot. However, as the size miniaturizes, the leak current between internal structures of the DRAM gets larger and larger, resulting in reduction of device reliability and increasing of stand-by power consumption.

It is to be noted that, information disclosed in the above Background section is merely for enhancement of understanding of the background of the disclosure, and may include information that does not constitute the prior art that is already known to those of ordinary skill in the art.

SUMMARY

The disclosure relates to the field of semiconductor technologies, and specifically, to a semiconductor structure and a method for forming the same, and a memory.

An aspect of the disclosure provides a semiconductor structure, including a substrate, a word line structure, a conductive contact structure and a buffer layer.

The substrate includes an active area. The active area includes a channel area, and a source area and a drain area that are respectively distributed on two sides of the channel area. The channel area has a word line groove.

The word line structure is located in the word line groove.

The conductive contact structure is connected to a top of the drain area.

The buffer layer is located between the conductive contact structure and the word line structure.

An aspect of the disclosure provides a method for forming a semiconductor structure. The method includes the following operations.

A substrate is provided. The substrate includes an active area. The active area includes a channel area, and a source area and a drain area that are respectively distributed on two sides of the channel area. The channel area has a word line groove.

A word line structure is formed in the word line groove.

A conductive contact structure is formed on a top of the drain area. The conductive contact structure is connected to the drain area.

A buffer layer is formed between the conductive contact structure and the word line structure.

An aspect of the disclosure provides a memory, including the semiconductor structure described in any one of the above.

It should be understood that, the above general description and the following detailed description are merely exemplary and explanatory, and cannot limit the disclosure.

DETAILED DESCRIPTION

Exemplary embodiments are described more comprehensively with reference to the drawings. However, exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. In contrast, these embodiments are provided for more thorough and complete understanding of the disclosure, and to fully convey the concept of the exemplary embodiments to a person skilled in the art. The same reference numerals in the drawings denote same or similar structures, and thus detailed descriptions will be omitted. In addition, the drawings are merely schematic illustrations of the disclosure and are not necessarily drawn to scale.

Although relative terms such as “on” and “under” are used in this specification to describe a relative relationship of one component illustrated in drawings to another component, these terms are used in this specification only for convenience, for example, according to a direction of the example described in the drawings. It may be understood that, if the apparatus illustrated in the drawings is turned upside down, the “on” component described will become the “under” component. When a certain structure is “on” other structures, it may mean that the certain structure is integrally formed on other structures, or that the certain structure is “directly” disposed on other structures, or that the certain structure is “indirectly” disposed on other structures via another structure.

The terms “a”, “an”, “the”, “said” and “at least one” are used to indicate the presence of one or more elements/components/and the like. The terms “including” and “having” are used to indicate an open-ended inclusive meaning and mean that additional elements/components/and the like may be present in addition to the listed elements/components/and the like. The terms “first”, “second” and the like are merely used as marks and are not intended to limit the number of objects.

An embodiment of the disclosure provides a semiconductor structure.FIG.1is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure. Referring toFIG.1, the semiconductor structure may include a substrate1, a word line structure2, a conductive contact structure3and a buffer layer5.

The substrate1may include an active area11. The active area11includes a channel area, and a source area111and a drain area112that are respectively distributed on two sides of the channel area. The channel area has a word line groove.

The word line structure2is located in the word line groove.

The conductive contact structure3is connected to a top of the drain area112.

The buffer layer5is located between the conductive contact structure3and the word line structure2.

In the semiconductor structure of the disclosure, the source area111, the drain area112and partial word line structure located at the channel area form an embedded transistor, so that the integration level of a device can be enhanced. In addition, the conductive contact structure3connected to the drain area112is connected to a capacitor (not shown in the figure). Since the buffer layer5is located between the conductive contact structure3and the word line structure2, a physical dimension between the word line structure2and the conductive contact structure3is increased, so that an electric field between a drain and a gate can be reduced, so as to reduce Gate-Induced Drain Leakage (GIDL) current. In addition, due to the increasing of the physical dimension, in addition to effectively reducing stand-by power consumption and improving the reliability of the device, large interface leak current between the substrate and source-drain doping areas (p-n) caused by excessively deep depth can be effectively avoided during etching.

Details of portions of the semiconductor structure according to the embodiments of the disclosure are described in detail below.

As shown inFIG.1, the substrate1may be of a flat-plate structure, which may be a rectangle, a circle, an ellipse, a polygon, or an irregular shape. A material of the substrate may be a semiconductor material, for example, may be silicon, but is not limited to the silicon or other semiconductor materials, and the shape and material of the substrate1are not specifically limited thereto.

In an embodiment, the substrate1may be a silicon substrate, and a plurality of shallow trench isolation structures (not shown in the figure) are formed in the substrate. The shallow trench isolation structures may be formed by first forming grooves in the substrate1and then filling insulation material layers in the grooves. A material of the shallow trench isolation structure may include silicon nitride or silicon oxide, which is not specially limited herein. A shape of a cross section of the shallow trench isolation structure may be designed according to actual requirements. The plurality of shallow trench isolation structures may be distributed side by side, and can isolate a plurality of active areas11on the substrate1. Each active area11may include a first doping area and a second doping area that are arranged in a spaced manner.

The substrate1may be p-type substrate. The first doping area and the second doping area may be doped to respectively form a source area111and a drain area112. For example, n-type doping may be performed on the first doping area and the second doping area, so as to form an n-type doping area. The n-type doping area may be form a p-n junction with the p-type substrate.

It is to be noted that, there may be a channel area (not shown in the figure) between the source area111and the drain area112(that is, the active area11may include the channel area, and the source area111and the drain area112that are respectively distributed on two sides of the channel area). A current may flow in the channel area. The current in the channel area may be controlled by a voltage of the word line structure2that is subsequently formed in the channel area, so as to achieve a gate-control function.

In an exemplary embodiment of the disclosure, a word line groove may be formed in the channel area and may be configured to form the word line structure2. For example, the substrate1may be etched to form the word line groove. The word line groove is penetrable on two ends and may be in a strip shape. The word line groove may penetrate a plurality of active areas11, and a portion of the word line groove that penetrates the active areas11and is in the active areas11may be located in the channel areas of the active areas11.

For example, a photoresist layer may be formed on a surface of the substrate1by means of spin coating or other manners. A material of the photoresist layer may be a positive photoresist or a negative photoresist, which is not particularly limited herein.

The photoresist layer may be exposed by using a mask. A pattern of the mask may match a pattern required for the word line groove. Then, the exposed photoresist layer may be developed to form a development area. Each development area may expose the surface of the substrate1. A pattern of the development area may be the same as the pattern required for the word line groove. A size of the development area may match a size required for the word line groove.

By means of a plasma etching process, the substrate1may be etched in the development area, so as to form the word line groove in the substrate1. After the etching process is completed, the photoresist layer may be cleaned by means of a cleaning solution or removed by means of processes such as ashing, so that the substrate1having the word line groove is exposed.

The word line structure2may be located in the word line groove. In some embodiments of the disclosure, a top of the word line structure2may be lower than a top surface of the word line groove, so as to leave space for a protective layer71that is subsequently formed. That is to say, the word line structure2may be formed in the word line groove.

In an exemplary embodiment of the disclosure,FIG.2is a schematic diagram of a word line structure according to an embodiment of the disclosure. As shown inFIG.2, the word line structure2may include an inter-gate dielectric layer21and a conductive layer22.

The fitly attached inter-gate dielectric layers21may be formed on a sidewall and bottom of each word line groove. A material of the inter-gate dielectric layer21may include silicon oxide and the like, or may be a combination of the foregoing materials. A thickness of the inter-gate dielectric layer may range from 1 nm to 9 nm, for example, may be 1 nm, 2 nm, 4 nm, 6 nm, 8 nm, or 9 nm. Definitely, there may be other thicknesses, which are not enumerated herein.

For example, the fitly attached inter-gate dielectric layers21may be formed on the sidewall and bottom of each word line groove by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation or thermal oxidation. Definitely, the inter-gate dielectric layer21may be formed in other manners, which is not specially limited herein. For ease of process, in a process of forming the inter-gate dielectric layer21, the inter-gate dielectric layer21may completely cover the top surface of the substrate1. Then, the inter-gate dielectric layer21on the top surface of the substrate1may be removed, and only the inter-gate dielectric layers21on the sidewall and bottom of each word line groove are retained.

In some embodiments of the disclosure, a surface of the inter-gate dielectric layer21may be processed by means of a thermal oxidation process, to improve the compactness of a film layer of the inter-gate dielectric layer21, so as to reduce leak current and enhance gate-control capabilities.

In an exemplary embodiment of the disclosure, continuously referring toFIG.2, the conductive layer22may fill the word line groove having the inter-gate dielectric layer21. A surface of the conductive layer22may be lower than the top surface of the word line groove. That is to say, the surface of the conductive layer22may be lower than the surface of the substrate1. In some embodiments of the disclosure, a material of the conductive layer22may be tungsten or titanium nitride. Definitely, the conductive layer may also be made of other materials with strong conductive performance, which is not enumerated herein.

The conductive layer22may be formed in the word line groove having the inter-gate dielectric layer21by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition or physical vapor deposition. Definitely, the conductive layer22may also be formed in other manners, and the manner of forming the conductive layer22is not specifically limited herein.

In some embodiments of the disclosure, the semiconductor structure of the disclosure may further include the protective layer71. The protective layer71may be formed in the word line groove, which may be a thin film formed on a surface of the conductive layer22, or may be a coating formed on the surface of the conductive layer22. A specific form of the protective layer71is not specifically limited herein. A material of the protective layer71may be an insulation material. For example, the material may be SiCN. Insulation protection may be performed on the surface of the word line structure2by means of the protective layer71, so that damage to the surface of the word line structure2caused by the follow-up process may be avoided, and the possibility of coupling or short circuit between the word line structure2and other surrounding structures may be reduced, thereby increasing product yield.

For example, the protective layer71may be formed on the surface of the conductive layer22by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. It is to be noted that, a surface of the protective layer71away from the conductive layer22may be flush with the surface of the substrate1.

In an exemplary embodiment of the disclosure, as shown inFIG.3, in the process of forming the protective layer71, a protective material layer710may be formed, by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition and so on, on a surface of a structure formed by the substrate1and the conductive layer22together. The protective material layer710may fill the word line groove, and covers the surface of the substrate1. Then, the protective material layer710in an area outside the word line groove may be removed by means of the etching process, and only the protective material layer710in the word line groove is retained, so that the protective material layer710in the word line groove may be defined as the protective layer71.

Continuously referring toFIG.1, a conductive contact structure3and a bit line contact structure4may be respectively formed on the top of the substrate1. The conductive contact structure3and the bit line contact structure4may respectively be used as a source and a drain, and form an embedded transistor together with the word line structure2, so that the integration level of a device can be enhanced.

For example, the conductive contact structure3and the bit line contact structure4may respectively be formed on tops of the source area111and the drain area112on the two sides of the word line groove. The bit line contact structure4, the conductive contact structure3and the word line structure2may be separated from each other by means of the insulation material, so as to avoid the coupling or short circuit between structures. For example, the bit line contact structure4, the conductive contact structure3and the word line structure2may be separated from each other through the protective layer71, the passivation layer7or an insulation layer8.

In an exemplary embodiment of the disclosure, the conductive contact structure3may extend in the direction perpendicular to the substrate1, and an end portion of the conductive contact structure close to the substrate1may extend into the drain area112. In the direction parallel to the substrate1, a width of a portion of the conductive contact structure3extending into the drain area112may be less than a width of a portion of the conductive contact structure away from the substrate1, so that a contact area between the conductive contact structure3and the drain area112can be decreased, thereby facilitating the reduction of contact resistance and increasing product yield. The conductive contact structure3may be made of a conductive material. For example, the material of the conductive contact structure3may be tungsten or titanium nitride. Definitely, the conductive contact structure may also be made of other materials with desirable conductive performance. The material of the conductive contact structure3is not specifically limited herein.

In some embodiments of the disclosure, as shown inFIG.4, the drain area112may include a recessed portion311that is recessed inward from the top. Due to an etching selection ratio, and when there is the buffer layer5(for example, selecting SiC-Ti0), an excessively-deep etching depth of the surface of the substrate can be alleviated when the recessed portion311is formed, so that not only the GIDL current but also p-n junction leak current can be improved. For example, the drain area112may be etched by means of the etching process, so as to form the recessed portion311in the drain area112. The semiconductor structure of the disclosure may further include a conductive material layer6.FIG.5is a schematic diagram of the conductive material layer6according to an embodiment of the disclosure. As shown inFIG.5, the conductive material layer6may be fitly attached to an inner wall of the recessed portion311. The conductive material layer6may be a thin film that is fitly attached to the sidewall and bottom of the recessed portion311, or may be a coating that is fitly attached to the sidewall and bottom of the recessed portion311. The form of the conductive material layer6is not specifically limited herein. The conductive material layer6may be formed on the sidewall and surface of the recessed portion311by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc. Definitely, the conductive material layer6may also be formed in other manners, and the manner of forming the conductive material layer6is not specifically limited herein.

Continuously referring toFIG.1, the end portion of the conductive contact structure3close to the substrate1may extend into the recessed portion311, and is connected to the conductive material layer6in the recessed portion311in a contact manner. For example, the recessed portion311having the conductive material layer6may be filled with the conductive contact structure3.

A material of the conductive material layer6may be different from the material of the conductive contact structure3. In order to reduce the contact resistance, a resistance value of the material of the conductive material layer6may be less than a resistance value of the material of the conductive contact structure3. For example, the material of the conductive contact structure3may be tungsten, and the material of the conductive material layer6may be silicon titanide or silicon nickel.

In an exemplary embodiment of the disclosure, the conductive contact structure3may extend in the direction perpendicular to the substrate1, and an end portion of the conductive contact structure close to the substrate1may extend into the drain area112. In the direction parallel to the substrate1, a width of a portion of the conductive contact structure3extending into the drain area112may be less than a width of a portion of the conductive contact structure away from the substrate1, so that a contact area between the conductive contact structure3and the drain area112can be decreased, thereby facilitating the reduction of contact resistance and improving the reliability of products. The conductive contact structure3may be made of a conductive material. For example, the material of the conductive contact structure3may be tungsten or titanium nitride. Definitely, the conductive contact structure may also be made of other materials with desirable conductive performance. The material of the conductive contact structure3is not specifically limited herein.

In some embodiments of the disclosure, as shown inFIG.1, the bit line contact structure4may be connected to the source area111. For example, the source area111may include a recess that is recessed inward from the top. For example, the source area111may be etched by means of the etching process, so as to form the recess in the source area111. An end of the bit line contact structure4may extend into the recess, and may fill the recess. In an embodiment, the bit line contact structure4may extend in the direction perpendicular to the substrate1. An orthographic projection of the bit line contact structure on the substrate1does not overlap with an orthographic projection of the conductive contact structure3on the substrate1.

In an exemplary embodiment of the disclosure, the semiconductor structure of the disclosure may further include an ohmic contact layer. The ohmic contact layer may be fitly attached to the inner wall of the recess. The ohmic contact layer may be a thin film that is fitly attached to the sidewall and bottom of the recess, or may be a coating that is fitly attached to the sidewall and bottom of the recess. The specific form of the ohmic contact layer is not specifically limited herein. The ohmic contact layer may be formed on the sidewall and surface of the recess by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc. Definitely, the ohmic contact layer may also be formed in other manners, and the manner of forming the ohmic contact layer is not specifically limited herein.

It is to be noted that, the end portion of the bit line contact structure4close to the substrate1may extend into the recess, and is connected to the ohmic contact layer in the recess. For example, the recess having the ohmic contact layer may be filled with the bit line contact structure4.

A material of the ohmic contact layer may be different from the material of the bit line contact structure4. In order to reduce the contact resistance, a resistance value of the material of the ohmic contact layer may be less than a resistance value of the material of the bit line contact structure4. For example, the material of the bit line contact structure4may be tungsten, and the material of the ohmic contact layer may be metal silicide, for example, cobalt silicide.

In some embodiments of the disclosure,FIG.6is a schematic diagram of a buffer layer according to an embodiment of the disclosure. As shown inFIG.6, the buffer layer5may be located between the conductive contact structure3and the bit line contact structure. For example, the buffer layer5may be formed on the surface of the drain area112, and may be connected to the conductive contact structure3in a contact manner. In addition, the buffer layer5may also be disposed in an insulated manner with the word line structure2. The buffer layer5in this embodiment of the disclosure may, for example, have an arcuate surface, so that the buffer layer can be fitly attached to the surface of the conductive contact structure3, and the closer to the position of the word line structure2, the larger the size of the buffer layer5. In this embodiment of the disclosure, through the design of the buffer layer5, the physical dimension between the word line structure2and the conductive contact structure3is increased, so that an electric field between a drain and a gate can be reduced, so as to reduce the GIDL current. In addition, due to the increasing of the physical dimension, in addition to effectively reducing stand-by power consumption and improving the reliability of the device, large interface leak current between the substrate and source-drain doping areas (p-n) caused by excessively deep depth can be effectively avoided during etching.

In an exemplary embodiment of the disclosure, the buffer layer5may be made of a conductive material. For example, the material of the buffer layer5may be titanium containing silicon carbide or nickel containing silicon carbide. These materials have good conductivity and adhesion, so that the performance of the buffer layer can be guaranteed. The buffer layer5may be formed on the surface of the drain area112by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc. Definitely, the buffer layer5may also be formed in other manners, and the manner of forming the buffer layer5is not specifically limited herein.

In an exemplary embodiment of the disclosure, the semiconductor structure of the disclosure may further include a passivation layer7.FIG.7is a schematic diagram of the passivation layer7according to an embodiment of the disclosure. As shown inFIG.7, the passivation layer7may cover the surfaces of the buffer layer5and the substrate1. The passivation layer7fills the word line groove. The conductive contact structure3may penetrate the passivation layer7, and is connected to the drain area112. In addition, continuously referring toFIG.1, the bit line contact structure4may penetrate the passivation layer7, and is connected to the source area111.

In some embodiments of the disclosure, continuously referring toFIG.7, the passivation layer7may include a passivation material layer72. The passivation material layer72may cover a surface of a structure formed by the substrate1, the buffer layer5and the protective layer71together. The material of the passivation material layer may be an insulation material with a low dielectric constant. Continuously referring toFIG.1, the conductive contact structure3may penetrate the passivation material layer72, and is connected to the drain area112. In addition, the bit line contact structure4may penetrate the passivation material layer72, and is connected to the source area111. Therefore, parasitic capacitance between the word line structure2and the conductive contact structure3and the bit line contact structure4can be reduced by means of the passivation material layer72with the low dielectric constant.

For example, the material of the passivation material layer72may be the same as the material of the protective layer71. For example, the material of the passivation material layer may be SiCN. The passivation material layer72may be formed, by means of atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc., on the surface of the structure that is formed by the substrate1, the buffer layer5and the protective layer71together. Definitely, the passivation material layer72may also be formed in other manners, and the manner of forming the passivation material layer72is not specifically limited herein. In some embodiments of the disclosure, the protective layer71and the passivation material layer72may jointly form the passivation layer7. The passivation layer7may be made of a material with a low dielectric constant, so that the parasitic capacitance between the word line structure2and the bit line contact structure4and the conductive contact structure3can be reduced through the passivation layer7.

In an exemplary embodiment of the disclosure, referring toFIG.4andFIG.5, the semiconductor structure of the disclosure may further include an insulation layer8. The insulation layer8may cover a surface of the passivation layer7. The conductive contact structure3may penetrate the insulation layer8and the passivation layer7, and is connected to the drain area112. In addition, the bit line contact structure4may penetrate the insulation layer8and the passivation layer7, and is connected to the source area111.

In some embodiments of the disclosure, a material of the insulation layer8may be an insulation material. Double insulation protection may be performed on the surface of the word line structure2through the insulation layer8and the passivation layer7, so that the coupling or short circuit between the word line structure2and other structures can be avoided, thereby increasing product yield. In addition, the bit line contact structure4and the conductive contact structure3may be separated through the insulation layer8, so that the coupling or short circuit between the bit line contact structure4and the conductive contact structure3can be avoided, thereby further increasing product yield. For example, the material of the insulation layer8may be silicon oxide.

For example, the insulation layer8may be formed on the surface of the passivation layer7by means of atomic layer deposition, chemical vapor deposition, physical vapor deposition, vacuum evaporation, magnetron sputtering, etc. Definitely, the insulation layer8may also be formed in other manners, and the manner of forming the insulation layer8is not specifically limited herein.

An embodiment of the disclosure further provides a method for forming a semiconductor structure.FIG.8is a flowchart of a method for forming a semiconductor structure according to an embodiment of the disclosure. Referring toFIG.8, the method may include S110to S140.

At S110, a substrate is provided. The substrate includes an active area. The active area includes a channel area, and a source area and a drain area that are respectively distributed on two sides of the channel area. The channel area has a word line groove.

At S120, a word line structure is formed in the word line groove.

At S130, a conductive contact structure is formed on a top of the drain area. The conductive contact structure is connected to the drain area.

At S140, a buffer layer is formed between the conductive contact structure and the word line structure.

In the method for forming a semiconductor structure in the disclosure, the conductive contact structure3may be used as a drain, and forms an embedded transistor together with the word line structure2and the subsequently-formed bit line contact structure4, so that the integration level of a device can be enhanced. In addition, since the buffer layer is located between the conductive contact structure3and the word line structure2, a physical dimension between the word line structure2and the conductive contact structure3is increased, so that an electric field between a drain and a gate can be reduced, so as to reduce a GIDL current. In addition, due to the increasing of the physical dimension, in addition to effectively reducing stand-by power consumption and improving the reliability of the device, large interface leak current between the substrate and source-drain doping areas (p-n) caused by excessively deep depth can be effectively avoided during etching.

Operations of the method for forming a semiconductor structure according to the disclosure are described in detail below.

In S110, the substrate1is provided. The substrate1includes an active area11. The active area11includes a channel area, and a source area111and a drain area112that are respectively distributed on two sides of the channel area. The channel area has a word line groove.

As shown inFIG.1, the substrate1may be of a flat-plate structure, which may be a rectangle, a circle, an ellipse, a polygon, or an irregular shape. A material of the substrate may be a semiconductor material, for example, may be silicon, but is not limited to the silicon or other semiconductor materials, and the shape and material of the substrate1are not specifically limited thereto.

In an embodiment, the substrate1may be a silicon substrate, and a plurality of shallow trench isolation structures (not shown in the figure) are formed in the substrate. The shallow trench isolation structures may be formed by first forming grooves in the substrate1and then filling insulation material layers in the grooves. A material of the shallow trench isolation structure may include silicon nitride or silicon oxide, which is not specially limited herein. A shape of a cross section of the shallow trench isolation structure may be designed according to actual requirements. The plurality of shallow trench isolation structures may be distributed side by side, and can isolate a plurality of active areas11on the substrate1. Each active area11may include a first doping area and a second doping area that are arranged in a spaced manner.

The substrate1may be p-type substrate. The first doping area and the second doping area may be doped to respectively form a source area111and a drain area112. For example, n-type doping may be performed on the first doping area and the second doping area, so as to form an n-type doping area. The n-type doping area may be form a p-n junction with the p-type substrate.

It is to be noted that, there may be a channel area (not shown in the figure) between the source area111and the drain area112(that is, the active area11may include the channel area, and the source area111and the drain area112that are respectively distributed on two sides of the channel area). A current may flow in the channel area. The current in the channel area may be controlled by a voltage of the word line structure2that is subsequently formed in the channel area, so as to achieve a gate-control function.

In an exemplary embodiment of the disclosure, a word line groove may be formed in the channel area and may be configured to form the word line structure2. For example, the substrate1may be etched to form the word line groove. The word line groove is penetrable on two ends and may be in a strip shape. The word line groove may penetrate a plurality of active areas11, and portions of the word line groove penetrating the active areas11and within the active areas may be located in the channel areas of the active areas11.

For example, a photoresist layer may be formed on a surface of the substrate1through spin coating or other manners. A material of the photoresist layer may be a positive photoresist or a negative photoresist, which is not particularly limited herein.

The photoresist layer may be exposed by using a mask. A pattern of the mask may match a pattern required for the word line groove. Then, the exposed photoresist layer may be developed to form a development area. Each development area may expose the surface of the substrate1. A pattern of the development area may be the same as the pattern required for the word line groove. A size of the development area may match a size required for the word line groove.

By means of a plasma etching process, the substrate1may be etched in the development area, so as to form the word line groove in the substrate1. After the etching process is completed, the photoresist layer may be cleaned by means of a cleaning solution or removed by means of processes such as ashing, so that the substrate1having the word line groove is exposed.

In S120, the word line structure2is formed in the word line groove.

The word line structure2may be located in the word line groove. In some embodiments of the disclosure, a top of the word line structure2may be lower than a top surface of the word line groove, so as to leave space for a protective layer71that is subsequently formed. That is to say, the word line structure2may be formed in the word line groove.

In an exemplary embodiment of the disclosure, the operation (that is, S120) of forming the word line structure2in the word line groove may include S210and S220.

At S210, a fitly-attached inter-gate dielectric layer21is formed in the word line groove.

The fitly attached inter-gate dielectric layers21may be formed on a sidewall and bottom of each word line groove. A material of the inter-gate dielectric layer21may include silicon oxide, silicon nitride, silicon oxynitride and the like, or may be a combination of the foregoing materials. A thickness of the inter-gate dielectric layer may range from 1 nm to 9 nm, for example, may be 1 nm, 2 nm, 4 nm, 6 nm, 8 nm, or 9 nm. Definitely, there may be other thicknesses, which are not enumerated herein.

For example, the fitly attached inter-gate dielectric layers21may be formed on the sidewall and bottom of each word line groove by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, thermal oxidation, etc. Definitely, the inter-gate dielectric layer21may be formed in other manners, which is not specially limited herein. For ease of process, in a process of forming the inter-gate dielectric layer21, the inter-gate dielectric layer21may completely cover the top surface of the substrate1. Then, the inter-gate dielectric layer21on the top surface of the substrate1may be removed, and only the inter-gate dielectric layers21on the sidewall and bottom of each word line groove are retained.

In some embodiments of the disclosure, a surface of the inter-gate dielectric layer21may be processed by means of a thermal oxidation process, to improve the compactness of a film layer of the inter-gate dielectric layer21, so that leak current can be reduced, gate-control capabilities can be enhanced, the effect of the inter-gate dielectric layer21to block impurities in the substrate1can be enhanced, and the impurities in the substrate1can be prevented from diffusing into the word line groove, thereby improving the stability of a structure.

At S220, a conductive layer22is formed in the word line groove having the inter-gate dielectric layer21, and a surface of the conductive layer22is lower than the surface of the substrate1.

In an exemplary embodiment of the disclosure, referring toFIG.2, the conductive layer22may fill the word line groove having the inter-gate dielectric layer21. A surface of the conductive layer22may be lower than the top surface of the word line groove. That is to say, the surface of the conductive layer22may be lower than the surface of the substrate1. In some embodiments of the disclosure, a material of the conductive layer22may be tungsten or titanium nitride. Definitely, the conductive layer may also be made of other conductive materials, which is not enumerated herein.

The conductive layer22may be formed in the word line groove having the inter-gate dielectric layer21by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc. Definitely, the conductive layer22may also be formed in other manners, and the manner of forming the conductive layer22is not specifically limited herein.

In S130, the conductive contact structure3is formed on the top of the drain area112. The conductive contact structure3is connected to the drain area112.

Continuously referring toFIG.1, in the embodiments of the disclosure, a drain and a source form an embedded transistor together with the word line structure2, so that the integration level of a device can be enhanced.

In an exemplary embodiment of the disclosure, the conductive contact structure3may be formed on the top of the drain area112. The conductive contact structure3may extend in the direction perpendicular to the substrate1, and an end portion of the conductive contact structure close to the substrate1may extend into the drain area112. In the direction parallel to the substrate1, a width of a portion of the conductive contact structure3extending into the drain area112may be less than a width of a portion of the conductive contact structure away from the substrate1, so that a contact area between the conductive contact structure3and the drain area112can be decreased, thereby facilitating the reduction of contact resistance and increasing product yield. The conductive contact structure3may be made of a conductive material. For example, the material of the onductive contact structure may be tungsten or titanium nitride. Definitely, the conductive contact structure may also be made of other materials with desirable conductive performance. The material of the conductive contact structure3is not specifically limited herein.

In some embodiments of the disclosure, as shown inFIG.4, the drain area112may include a recessed portion311that is recessed inward from the top. For example, the drain area112may be etched by means of the etching process, so as to form the recessed portion311in the drain area112. The method for forming a semiconductor structure may further include the following operations.

At S150, a conductive material layer6fitly attached to an inner wall of the recessed portion311is formed. The conductive contact structure3extends in a direction perpendicular to the substrate1. An end portion of the conductive material layer close to the substrate1extends into the recessed portion311and fills the recessed portion311having the conductive material layer6.

FIG.5is a schematic diagram of the conductive material layer6according to an embodiment of the disclosure. As shown inFIG.5, the conductive material layer6may be fitly attached to an inner wall of the recessed portion311. The conductive material layer6may be a thin film that is fitly attached to the sidewall and bottom of the recessed portion311, or may be a coating that is fitly attached to the sidewall and bottom of the recessed portion311. The form of the conductive material layer6is not specifically limited herein. The conductive material layer6may be formed on the sidewall and surface of the recessed portion311by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc. Definitely, the conductive material layer6may also be formed in other manners, and the manner of forming the conductive material layer6is not specifically limited herein.

Continuously referring toFIG.1, the end portion of the conductive contact structure3close to the substrate1may extend into the recessed portion311, and is connected to the conductive material layer6in the recessed portion311in a contact manner. For example, the recessed portion311having the conductive material layer6may be filled with the conductive contact structure3.

A material of the conductive material layer6may be different from the material of the conductive contact structure3. In order to reduce the contact resistance, a resistance value of the material of the conductive material layer6may be less than a resistance value of the material of the conductive contact structure3. For example, the material of the conductive contact structure3may be tungsten, and the material of the conductive material layer6may be silicon titanide or silicon nickel.

In an exemplary embodiment of the disclosure, the conductive contact structure3may extend in the direction perpendicular to the substrate1, and an end portion of the conductive contact structure close to the substrate1may extend into the drain area112. In the direction parallel to the substrate1, a width of a portion of the conductive contact structure3extending into the drain area112may be less than a width of a portion of the conductive contact structure away from the substrate1, so that a contact area between the conductive contact structure3and the drain area112can be decreased, thereby facilitating the reduction of contact resistance and improving the reliability of products. The conductive contact structure3may be made of a conductive material. For example, the material may be tungsten or titanium nitride. Definitely, the conductive contact structure may also be made of other materials with desirable conductive performance. The material of the conductive contact structure3is not specifically limited herein.

In some embodiments of the disclosure, the method for forming a semiconductor structure may further include the following operations.

At S160, a bit line contact structure4is formed on a top of the source area111. The bit line contact structure4penetrates the insulation layer8and the passivation layer7and connected to the source area111, and an orthographic projection of the bit line contact structure4on the substrate1does not overlap with an orthographic projection of the conductive contact structure3on the substrate1.

Continuously referring toFIG.1, the bit line contact structure4may be connected to the source area111. For example, the source area111may include a recess that is recessed inward from the top. For example, the source area111may be etched by means of the etching process, so as to form the recess in the source area111. An end of the bit line contact structure4may extend into the recess, and may fill the recess. In an embodiment, the bit line contact structure4may extend in the direction perpendicular to the substrate1. An orthographic projection of the bit line contact structure on the substrate1does not overlap with an orthographic projection of the conductive contact structure3on the substrate1.

In an exemplary embodiment of the disclosure, the method for forming a semiconductor structure may further include the following operations.

At S170, an ohmic contact layer fitly attached to the inner wall of the recess is formed.

The ohmic contact layer may be a thin film that is fitly attached to the sidewall and bottom of the recess, or may be a coating that is fitly attached to the sidewall and bottom of the recess. The specific form of the ohmic contact layer is not specifically limited herein. The ohmic contact layer may be formed on the sidewall and surface of the recess by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc. Definitely, the ohmic contact layer may also be formed in other manners, and the manner of forming the ohmic contact layer is not specifically limited herein.

It is to be noted that, the end portion of the bit line contact structure4close to the substrate1may extend into the recess, and is connected to the ohmic contact layer in the recess in contact manner. For example, the recess having the ohmic contact layer may be filled with the bit line contact structure4.

A material of the ohmic contact layer may be different from the material of the bit line contact structure4. In order to reduce the contact resistance, a resistance value of the material of the ohmic contact layer may be less than a resistance value of the material of the bit line contact structure4. For example, the material of the bit line contact structure4may be tungsten, and the material of the ohmic contact layer may be metal silicide, for example, cobalt silicide.

In S140, the buffer layer5is formed between the conductive contact structure3and the word line structure2.

FIG.6is a schematic diagram of a buffer layer according to an embodiment of the disclosure. As shown inFIG.6, the buffer layer5may be formed on the surface of the drain area112, which may be connected to the conductive contact structure3in a contact manner. In addition, the buffer layer5may also be disposed in an insulated manner with the word line structure2. The buffer layer5in this embodiment of the disclosure may, for example, have an arcuate surface, so that the buffer layer can be fitly attached to the surface of the conductive contact structure3, and the closer to the position of the word line structure2, the larger the size of the buffer layer5. In this embodiment of the disclosure, through the design of the buffer layer5, the physical dimension between the word line structure2and the conductive contact structure3is increased, so that an electric field between a drain and a gate can be reduced, so as to reduce the GIDL current. In addition, due to the increasing of the physical dimension, in addition to effectively reducing stand-by power consumption and improving the reliability of the device, large interface leak current between the substrate and source-drain doping areas (p-n) caused by excessively deep depth can be effectively avoided during etching.

In an exemplary embodiment of the disclosure, the buffer layer5may be made of a conductive material. For example, the material may be titanium containing silicon carbide or nickel containing silicon carbide. These materials have good conductivity and adhesion, so that the performance of the buffer layer can be guaranteed. The buffer layer5may be formed on the surface of the drain area112by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc. Definitely, the buffer layer5may also be formed in other manners, and the manner of forming the buffer layer5is not specifically limited herein.

In an exemplary embodiment of the disclosure, the method for forming a semiconductor structure may further include the following operations.

At S180, a passivation layer7covering the buffer layer5and a surface of the substrate1is formed. The passivation layer7fills the word line groove.

FIG.7is a schematic diagram of the passivation layer7according to an embodiment of the disclosure. As shown inFIG.7, the passivation layer7may cover the surfaces of the buffer layer5and the substrate1. The passivation layer7fills the word line groove. The conductive contact structure3may penetrate the passivation layer7, and is connected to the drain area112. In addition, continuously referring toFIG.1, the bit line contact structure4may penetrate the passivation layer7, and is connected to the source area111.

In some embodiments of the disclosure, the operation (that is, S180) of forming the passivation layer7covering the surfaces of the buffer layer5and the substrate1, where the passivation layer7fills the word line groove, may include S310and S320.

At S310, a protective layer71covering the surface of the word line structure2is formed, and a surface of the protective layer is flush with the surface of the substrate1.

The protective layer71may be formed in the word line groove, which may be a thin film formed on a surface of the conductive layer22, or may be a coating formed on the surface of the conductive layer22. A specific form of the protective layer71is not specifically limited herein. A material of the protective layer71may be an insulation material. For example, the material of the protective layer may be SiCN. Insulation protection may be performed on the surface of the word line structure2through the protective layer71, so that damage to the surface of the word line structure2caused by the follow-up process may be avoided, and the possibility of coupling or short circuit between the word line structure2and other surrounding structures may be reduced, thereby increasing product yield.

For example, a material of the protective layer71may be silicon oxide or silicon nitride. The protective layer71may be formed on the surface of the conductive layer22by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. It is to be noted that, a surface of the protective layer71away from the conductive layer22may be flush with the surface of the substrate1.

In an exemplary embodiment of the disclosure, as shown inFIG.3, in the process of forming the protective layer71, a protective material layer710may be formed, by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc., on a surface of a structure formed by the substrate1and the conductive layer22together. The protective material layer710may fill the word line groove, and covers the surface of the substrate1. Then, the protective material layer710of an area outside the word line groove may be removed by means of the etching process, and only the protective material layer710in the word line groove is retained, so that the remaining protective material layer710in the word line groove may be defined as the protective layer71.

At S320, a passivation material layer72is formed on a surface of a structure that is formed by the substrate1, the buffer layer5and the protective layer71together.

Continuously referring toFIG.7, the passivation material layer72may cover a surface of a structure formed by the substrate1, the buffer layer5and the protective layer71together. The material of the passivation material layer may be an insulation material with a low dielectric constant. Continuously referring toFIG.1, the conductive contact structure3may penetrate the passivation material layer72, and is connected to the drain area112. In addition, the bit line contact structure4may penetrate the passivation material layer72, and is connected to the source area111. Therefore, parasitic capacitance between the word line structure2and the conductive contact structure3and the bit line contact structure4can be reduced by means of the passivation material layer72with the low dielectric constant.

For example, the material of the passivation material layer72may be the same as the material of the protective layer71. For example, the material of the passivation material layer may be SiCN. The passivation material layer72may be formed, by means of atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc., on the surface of the structure that is formed by the substrate1, the buffer layer5and the protective layer71together. Definitely, the passivation material layer72may also be formed in other manners, and the manner of forming the passivation material layer72is not specifically limited herein. In some embodiments of the disclosure, the protective layer71and the passivation material layer72may jointly form the passivation layer7. The passivation layer7may be made of a material with a low dielectric constant, so that the parasitic capacitance between the word line structure2and the bit line contact structure4and the conductive contact structure3can be reduced by means of the passivation layer7.

In an exemplary embodiment of the disclosure, the method for forming a semiconductor structure may further include the following steps.

At S190, an insulation layer8covering a surface of the passivation layer7is formed. The conductive contact structure3can penetrate the insulation layer8and the passivation layer7, and fill the recessed portion311having the conductive material layer6.

Referring toFIG.4andFIG.5, the insulation layer8may cover the surface of the passivation layer7. The conductive contact structure3may penetrate the insulation layer8and the passivation layer7, and is connected to the drain area112. In addition, the bit line contact structure4may penetrate the insulation layer8and the passivation layer7, and is connected to the source area111.

In some embodiments of the disclosure, a material of the insulation layer8may be an insulation material. Double insulation protection may be performed on the surface of the word line structure2by means of the insulation layer8and the passivation layer7, so that the coupling or short circuit between the word line structure2and other structures can be avoided, thereby increasing product yield. In addition, the bit line contact structure4and the conductive contact structure3may be separated through the insulation layer8, so that the coupling or short circuit between the bit line contact structure4and the conductive contact structure3can be avoided, thereby further increasing product yield. For example, the material of the insulation layer8may be silicon oxide.

For example, the insulation layer8may be formed on the surface of the passivation layer7by means of atomic layer deposition, chemical vapor deposition, physical vapor deposition, vacuum evaporation, magnetron sputtering, etc. Definitely, the insulation layer8may also be formed in other manners, and the manner of forming the insulation layer8is not specifically limited herein.

In an exemplary embodiment of the disclosure, the operation of forming the conductive contact structure3, which is connected to the drain area112, on the top of the drain area112may include S410and S420.

At S410, the insulation layer8, the passivation layer7and the drain area112are etched, so as to form a capacitor contact hole31. The capacitor contact hole31includes the recessed portion311formed in the drain area112, a first hole section312exposing the buffer layer5and a second hole section313formed on a side of the first hole section312away from the recessed portion311. In a direction perpendicular to the substrate1, the recessed portion311, the first hole section312and the second hole section313successively interfaced. In a direction parallel to the substrate1, a width of the recessed portion311is less than a width of the first hole section312and/or a width of the second hole section313.

In some embodiments of the disclosure, after the passivation layer7and the insulation layer8are formed, the conductive contact structure3and the bit line contact structure4may be formed. After the bit line contact structure4is formed, a bit line400may be formed on the side of the bit line contact structure4away from the substrate1. For example, anisotropic etching may be performed on the insulation layer8, the passivation layer7and the drain area112of the substrate1, so as to form the capacitor contact hole31.FIG.4is a schematic diagram of the capacitor contact hole31according to an embodiment of the disclosure. As shown inFIG.4, the capacitor contact hole31may be a blind hole. For example, the capacitor contact hole31may penetrate the insulation layer8and the passivation layer7, and may extend to the drain area112of the substrate1. The capacitor contact hole31does not penetrate the drain area112of the substrate1, and a portion of the capacitor contact hole extending into the drain area112is distributed in a spaced manner with the channel area.

In an exemplary embodiment of the disclosure, the capacitor contact hole31may include the recessed portion311, the first hole section312and the second hole section313. In the direction perpendicular to the substrate1, the recessed portion311, the first hole section312and the second hole section313may successively interfaced, so as to form the capacitor contact holes31that successively communicate with each other. For example, the recessed portion311may be located in the source area111of the substrate1, an opening of the recessed portion311may face a side where the passivation layer7and the insulation layer8are located. The first hole section312may penetrate the passivation layer7, and passes through partial thickness of the insulation layer8. The first hole section312may include a first open end and a second open end that communicate with each other. The first open end may interface with an opening of the recessed portion311. The second open end may extend toward, in the direction perpendicular to the substrate1, a side away from the first open end. The sidewall of the first hole section312may be expose the buffer layer5, so that the conductive contact structure3subsequently formed in the second hole section313is connected to the buffer layer5in a contact manner, thereby improving the performance of the semiconductor structure. The second hole section313may be a via, of which one end may be flush with the surface of the insulation layer8, and the other end may interface with the second open end of the first hole section312.

In some embodiments of the disclosure, in the direction parallel to the substrate1, a width of the recessed portion311located in the drain area112may be less than the width of the first hole section312and/or the width of the second hole section313, so that a contact area between the conductive contact structure3subsequently formed in the recessed portion and the substrate1can be decreased, thereby reducing contact resistance.

At S420, the capacitor contact hole31is filled with a conductive material, so as to form the conductive contact structure3.

The capacitor contact hole31may be filled with the conductive material by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc., so as to form the conductive contact structure3. In an embodiment, the conductive material may be tungsten. Definitely, the conductive material may also be other materials with strong conductive performance, which is not enumerated herein.

It is to be noted that, the capacitor contact hole31may be filled with the conductive material. That is to say, the surface of the conductive contact structure3may be flush with the surface of the substrate1. In the direction parallel to the substrate1, the width of the portion of the conductive contact structure3located in the drain area112is less than the width of the portion of the conductive contact structure outside the substrate1, so that the contact area between the conductive contact structure3and the substrate1can be decreased, thereby reducing contact resistance.

It is to be noted that, before the conductive contact structure is formed, a conductive material layer6may be formed in the recessed portion311of the drain area112. For example, after the capacitor contact hole31is formed, a fitly-attached metal conductive layer22may be formed in the recessed portion311. A material of the metal conductive layer22may be titanium or nickel. Then, the metal conductive layer22may be annealed. During annealing, the titanium or nickel in the metal conductive layer22may react with silicon in the substrate1, so as to form the conductive material layer6. When the substrate1is the silicon substrate, the material of the conductive material layer6may be silicon titanide or silicon nickel.

In an exemplary embodiment of the disclosure, the operation (that is, S140) of forming the buffer layer5between the conductive contact structure3and the word line structure2may include S510to S550.

At S510, a first mask layer9is formed on the surface of the substrate1. An orthographic projection of the first mask layer9on the substrate1does not overlap with an orthographic projection of the drain area112on the substrate1.

In some embodiments of the disclosure, a mask material layer91may be formed on the surface of the substrate1by means of chemical vapor deposition, physical vapor deposition, vacuum evaporation, magnetron sputtering, atomic layer deposition or other manners. The mask material layer91may be a multilayer film layer structure, or may be a single-layer film layer structure. A material of the mask material layer may be at least one of polymer, SiO2, SiN, polysilicon or SiCN. Definitely, the material may be other materials, which is not enumerated herein.FIG.9is a schematic diagram of a mask material layer91according to an embodiment of the disclosure.

In some embodiments, the mask material layer91may include a plurality of layers, which may include a polymer layer, an oxide layer and a hard mask layer. The polymer layer may be formed on the surface of the substrate1, and the oxide layer may be located between the hard mask layer and the polymer layer. The polymer layer may be formed on the surface of the substrate1by means of a chemical vapor deposition process. The oxide layer may be formed on a surface of the polymer layer by means of a vacuum evaporation process. The hard mask layer may be formed on a surface of the oxide layer by means of an atomic layer deposition process.

A photoresist layer92may be formed on a surface of the mask material layer91away from a base by means of spin coating or other manners. A material of the photoresist layer92may be a positive photoresist or a negative photoresist, which is not particularly limited herein.

The photoresist layer92may be exposed by using a mask. An orthographic projection of a pattern of the mask on the substrate1may at least partially overlap with the drain area112. Then, the exposed photoresist layer92may be developed to form a plurality of development areas that are distributed in a spaced manner. Each development area may expose the surface of the mask material layer91. A pattern of the development areas may be the same as a pattern required for the first mask layer9. A size of the development area may be the same as a size required for the first mask layer9.

The mask material layer91may be etched in each development area by means of an anisotropic etching process, and the etched area may expose the substrate1, so that a plurality of mask patterns are formed on the mask material layer91, and the mask material layer91having the mask patterns may be defined as the first mask layer9. It is to be noted that, when the mask material layer91is the single-layer structure, the mask patterns may be formed by means of one-time etching process. When the mask material layer91is the multilayer structure, the film layers may be layered for etching. That is to say, one layer may be etched by means of the one-time etching process, and the mask material layer91may be fully etched by using the etching process for a plurality of times, so as to form the mask patterns. In an embodiment, the shapes and sizes of the mask patterns may be the same as the pattern and size required for each first mask layer9.

It is to be noted that, after the etching process is completed, the photoresist layer92may be cleaned by means of a cleaning solution or removed by means of processes such as ashing, so that the etched first mask layer9is no longer covered by the photoresist layer92.FIG.10is a schematic diagram after S510is completed according to an embodiment of the disclosure.

At S520, a buffer material layer51is formed on a surface of a structure that is formed by the first mask layer9and the substrate1together.

The buffer material layer51may be formed, by means of chemical vapor deposition, physical vapor deposition, vacuum evaporation, magnetron sputtering, atomic layer deposition or other manners, on the surface of the structure that is formed by the first mask layer9and the substrate1together. The buffer material layer51may at least cover the sidewall and surface of the first mask layer9. In some embodiments of the disclosure, a material of the buffer material layer51may be silicon carbide.FIG.11is a schematic diagram after S520is completed according to an embodiment of the disclosure.

At S530, the buffer material layer51is etched, and only the buffer material layer51located on the sidewall of the first mask layer9is retained.

The buffer material layer51may be etched by means of a dry etching process, so as to remove the portion of the buffer material layer51outside the sidewall of the first mask layer9, and only the buffer material layer51on the sidewall of the first mask layer9is retained. It is to be noted that, in the process of removing the buffer material layer51, an end portion, close to the substrate1, of the remaining buffer material layer51on the sidewall of the first mask layer9may be connected to the substrate1in a contact manner, so that the buffer material layer51may be supported by the substrate1, and the buffer material layer51can be prevented from collapsing after the first mask layer9is subsequently removed, thereby increasing product yield. As shown inFIG.11, in the process of removing the buffer material layer51, a second mask layer93may be formed on the surface of the buffer material layer51. The second mask layer93may be consumed during the etching of the buffer material layer51.FIG.12is a schematic diagram after S530is completed according to an embodiment of the disclosure.

At S540, the first mask layer9is removed.

The first mask layer9may be removed by means of a selective etching process. An etching gas or an etching solution may be set according to the specific material of the first mask layer9. The etching gas or the etching solution of the first mask layer9is not specifically limited herein, as long as the first mask layer9can be removed and other film layer structures cannot be damaged.

At S550, annealing treatment is performed on the remaining buffer material layer51, so as to form the buffer layer5.

In an exemplary embodiment of the disclosure, the same annealing process may be performed on the buffer material layer51and the metal conductive layer22, so as to cause the buffer material layer51to be converted into the buffer layer5, and at the same, cause the metal conductive layer22to be converted into the conductive material layer6. For example, after the capacitor contact hole31is formed, the metal conductive layer22may be formed in the capacitor contact hole31. The metal conductive layer22may be fitly attached to the bottom and sidewall of the capacitor contact hole31. That is to say, the metal conductive layer22may be fitly attached to the sidewall and bottom of the recessed portion311, and may also be attached to the surface of the buffer layer5. The capacitor contact hole31having the metal conductive layer22may be annealed. In this process, when the material of the metal conductive layer22is titanium or nickel, the silicon carbide in the buffer layer5may react with the titanium or nickel, so as to form titanium containing silicon carbide or nickel containing silicon carbide. In addition, the silicon in the substrate1may react with the titanium or nickel, so as to form silicon titanide or silicon nickel. The material in the sidewall of the capacitor contact hole31does not react with the titanium or nickel.

In the above process, the material of the buffer layer5is titanium containing silicon carbide or nickel containing silicon carbide. These materials have good conductivity and adhesion, so that the performance of the buffer layer can be guaranteed. In addition, since the buffer layer5is located between the conductive contact structure3and the word line structure2, a physical dimension between the word line structure2and the conductive contact structure3is increased, so that an electric field between a drain and a gate can be reduced, so as to reduce a GIDL current. In addition, due to the increasing of the physical dimension, in addition to effectively reducing stand-by power consumption and improving the reliability of the device, maximum interface leak current between the substrate and source-drain doping areas (p-n) caused by excessively deep depth can be effectively avoided during etching.

It is to be noted that, although the various steps of the method for forming a semiconductor structure in the disclosure are described in a particular order in the drawings, this does not require or imply that the steps must be performed in the particular order, or that all shown steps must be performed to achieve desired results. Additionally or alternatively, certain steps may be omitted, a plurality of steps may be combined into one step for execution, and/or one step may be decomposed into a plurality steps for execution, and the like.

An embodiment of the disclosure further provides a memory. The memory may include the semiconductor structure in any of the above embodiments. The specific details, formation process and beneficial effects of the memory have been described in detail in the corresponding semiconductor structure and the method for forming a semiconductor structure, which are not be described herein again.

For example, the memory may be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like. Definitely, the memory may also be other storage apparatuses, which is not listed herein.

Other embodiment solutions of the disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. The disclosure is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common knowledge or techniques in the technical field that are not disclosed by the disclosure. The specification and examples are to be regarded as exemplary only, with the true scope and spirit of the disclosure being indicated by the appended claims.