Semiconductor structure formed without requiring thermal oxidation

Briefly, in accordance with one or more embodiments, a semiconductor device is manufactured by forming at least two or more cavities below a surface of a semiconductor substrate wherein the at least two or more cavities are spaced apart from each other by a selected distance, filling at least a portion of the at least two or more cavities with a dielectric material to form at least two or more dielectric structures, removing a portion of the substrate between the at least two or more dielectric structures to form at least one additional cavity, and covering the at least one additional cavity.

TECHNICAL FIELD

Embodiments disclosed in the present disclosure relate generally to electrical and semiconductor technology, and more specifically to a semiconductor structure that includes a dielectric structure.

BACKGROUND

For some applications, such as higher frequency or radio frequency (“RF”) applications, integrated passive devices may be formed using semiconductor processing technology or alternatively integrate passive devices such as inductors and/or capacitors may be formed together with active devices such as transistors using conductive silicon substrates such, as for example, a semiconductor die. However, passive devices may have relatively lower quality factors (“Qs”) when these passive devices are formed on, or in relatively close proximity to, the conductive silicon substrate. In addition, due to parasitic capacitive coupling between these passive devices and the conductive silicon substrate, the frequency of operation of the integrated devices may be reduced. Electrically conductive interconnects or busses may be used to electrically couple different devices within the die and external to the die. The frequency of operation may also be adversely reduced by parasitic capacitive coupling between the interconnects and the conductive silicon substrate.

Further, regions of a semiconductor substrate may be physically and/or electrically isolated from each other. Additionally, some semiconductor devices, such as power transistors, provide a relatively high power output to be utilized in some RF, industrial, and medical applications as some examples. Power transistor designers are continually seeking ways to efficiently increase power output by varying the output voltage and current characteristics of a power transistor. For example, a power transistor may be designed to have an increased breakdown voltage to enable the power transistor to operate at a relatively higher voltage and provide a relatively higher power output.

For simplicity of illustration and ease of understanding, elements in the various figures are not necessarily drawn to scale, unless explicitly so stated. Further, if considered appropriate, reference characters have been repeated among the figures to indicate corresponding and/or analogous elements. In some instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present disclosure. The following detailed description is merely exemplary in nature and is not intended to limit the disclosure of this document and uses of the disclosed embodiments. Furthermore, there is no intention that the appended claims be limited by the title, technical field, background, or abstract.

DETAILED DESCRIPTION

In the following description and claims, the terms “comprise” and “include,” along with their derivatives, may be used and are intended as synonyms for each other. In addition, in the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. “Connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. For example, “coupled” may mean that two or more elements do not contact each other but are indirectly joined together via another element or intermediate elements. Finally, the terms “on,” “overlying,” and “over” may be used in the following description and claims. “On,” “overlying,” and “over” may be used to indicate that two or more elements are in direct physical contact with each other. However, “over” may also mean that two or more elements are not in direct contact with each other. For example, “over” may mean that one element is above another element but not be in contact with each other and may have another element or elements in between the two elements.

FIG. 1is a cross-sectional view of a semiconductor structure100that illustrates a dielectric platform (“DP”)18, active regions20and21, and an electrically conductive material24in accordance with an embodiment of the present invention. Dielectric platform18may be referred to as a dielectric structure or a dielectric region, and active regions20and21may also be referred to as active area regions, active areas, or portions of active areas since active devices, or portions of active devices, may be formed in active regions20and21. In one or more embodiments, a dielectric platform, dielectric structure, and/or dielectric region may refer to a semiconductor structure or feature capable of providing reduced parasitic capacitances, relatively higher frequencies of operation, relatively higher breakdown voltages, relatively higher quality factor passive devices, and/or improved isolation between devices, or combinations thereof. In general, such a structure or region may be referred to a dielectric platform. It should be noted that a dielectric platform may implement one or more of the above mentioned characteristics, or alternatively may implement one or more other characteristics, for example structural integrity or stress reduction in a semiconductor device, however a dielectric structure is not required to implement any specific characteristics, and the scope of the claimed subject matter is not limited in this respect.

Dielectric platform18of semiconductor structure100comprises a plurality of sealed cavities820A bounded by dielectric material formed in a substrate14. In addition to sealed cavities820A, dielectric platform18shown inFIG. 1includes dielectric layer50, capping material910, sealing material1010and dielectric structures64A. As will be discussed further below, at least a portion of dielectric platform18may be between electrically conductive material24and substrate14to reduce parasitic capacitance between electrically conductive material24and substrate14. In other embodiments of the present invention, at least a portion of dielectric platform18is between at least a portion of electrically conductive material24and at least a portion of substrate14to reduce capacitance between electrically conductive material24and substrate14.

Sealed cavity820A may also be referred to as a sealed cavity, a sealed gap, a sealed void, a closed cell, or a closed cell void. In some embodiments, sealed cavity820A may be evacuated to a pressure less than atmospheric pressure. In other words, the pressure in sealed cavity820A may be below atmospheric pressure. As an example, the pressure in cavity820A may range from approximately 0.1 Torr to approximately 10 Torr. The type of substance or material within sealed cavity820A may include a variety or substances or materials, and the scope of the claimed subject matter is not limited in this respect. For example, sealed cavity820A may contain a solid material or a fluid such as a liquid or a gas.

Active regions20and21are comprised of a portion of substrate14. In some embodiments, substrate14may be referred to as a device layer or an active layer. Further, in some embodiments, substrate14may include one or more epitaxial layers or bonded layers. Substrate14may be used as an active area where active devices, such as, for example, transistors or diodes, or portions of active devices, may be subsequently formed. In some embodiments, semiconductor material14may be formed on a substrate comprised of the same or a different material. In one example, semiconductor material14is silicon which is epitaxially grown on a silicon substrate. It should be understood that a substrate may mean a semiconductor material, one or more epitaxial layers formed on a semiconductor material, a semiconductor material disposed on an insulating material, or the like, and the scope of the claimed subject matter is not limited in this respect. Accordingly, substrate14may also be referred to as a semiconductor substrate. Active devices may be formed in active regions20and21using conventional metal oxide semiconductor (MOS), complementary metal oxide semiconductor (CMOS), bipolar, or bipolar-CMOS (BiCMOS) processes, and so on. Substrate14may comprise a semiconductor material such as, for example, silicon, and may be doped or undoped depending on the application.

In one or more embodiments, all or substantially all of the dielectric portions of dielectric platform18may be formed without thermally formed oxidation. For example, in the case where substrate14comprises silicon, the present invention eliminates or greatly reduces the need for long oxidation steps at higher temperatures to create thick silicon oxide regions by thermal oxidation of silicon substrate14. Thick thermal oxides may generate stress because of the approximately 2.2 times volume expansion that typically occurs when silicon is oxidized. Stress on the silicon lattice may lead to defects or dislocations in the silicon region which may result in undesirable excessive leakage currents in active devices formed in the active region adjacent to dielectric platform18. In addition to stress caused by the expansion of silicon oxide when formed by thermal oxidation of silicon, the relatively longer times at higher temperature utilized to practicably form thick silicon oxide layers may be reduced or eliminated in one or more embodiments. Such an arrangement reduces additional stress that may be generated during heating and cooling of the dielectric structure and the silicon region due to the coefficient of thermal expansion (“CTE”) mismatch between silicon and oxide. In another embodiment, substrate14may comprise a material, for example germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) and the like, that does not form a suitably stable oxide. Other methods of forming a dielectric platform that require thick thermal oxides may not be suitable for such substrates, whereas the present invention may be used to practicably form a DP in such substrates.

In some embodiments, the depth or thickness of dielectric platform18may range from about 1 μm to about 40 μm. In some embodiments, lower surface90of dielectric platform18is parallel to, or substantially parallel to, top surface16of substrate14, however the scope of the claimed subject matter is not limited in this respect, and in other embodiments lower surface90of dielectric platform18may not be parallel to surface16and/or may not all be at one level. In some embodiments, lower surface90of dielectric platform18is at a distance of at least about one μm or greater below top surface16and the width of dielectric platform18is at least about three μm or greater. In other embodiments, lower surface90of dielectric platform18is at a distance of at least about 3 μm or greater below top surface16and the width of dielectric platform18is at least about 5 μm or greater. In one example, the thickness of dielectric platform18may be about ten μm and the width of dielectric platform18may be about 10 μm. In yet other embodiments, the thickness of dielectric platform18may be equal to, or approximately equal to, the thickness of substrate14, for example, the thickness of the semiconductor die and the width of dielectric platform18may be up to about 1000 μm. The thickness and width of dielectric platform18may be varied depending on the application for dielectric platform18and the desired die size of the resulting semiconductor device that uses substrate14. For example, a relatively thicker dielectric platform may be desired in applications where dielectric platform18is used to form high Q passive devices compared to an application where dielectric platform18is used for isolation.

In some embodiments, the height of dielectric structures64A is equal to, or approximately equal to, the depth of cavities820(FIG. 9), however the scope of the claimed subject matter is not limited in this respect. In other embodiments, the height of dielectric structures64A may be greater than, or less than, the depth of cavity820.

The combination of sealing material1010, capping material910, dielectric layer50, dielectric structures64A and sealed cavities820A reduces the overall permittivity of dielectric platform18so that dielectric platform18has a relatively low dielectric constant. In other words, the combination of sealing material1010, capping material910, dielectric layer50, dielectric structures64A and sealed cavities820A results in dielectric platform18having a lower or reduced dielectric constant. Silicon dioxide has a dielectric constant of about 3.9. Accordingly, a solid or filled dielectric structure that includes no cavities and includes silicon dioxide may have a dielectric constant of about 3.9. Since empty space has the lowest dielectric constant (the dielectric constant of empty space is 1), the more empty space or void space incorporated into the dielectric platform, the lower the overall dielectric constant. Accordingly to minimize the dielectric constant of dielectric platform18, the depth of dielectric platform18may be increased, the volume of sealed cavities820A may be increased, the volume of dielectric material in dielectric structures64A may be reduced, and/or the amount of dielectric capping material910, dielectric layer50and/or sealing material1010contained in dielectric platform18may be reduced.

In some embodiments described herein, dielectric platform18includes one or more cavities occupying in excess of about 40% of the total volume of dielectric platform18. This may result in an effective dielectric constant reduction of about 30% or greater, from a dielectric constant of about 3.9 to an effective dielectric constant of about 2.74. In one embodiment, dielectric platform18includes one or more cavities occupying in excess of 50% of the total volume. This may result in an effective dielectric constant reduction of about 39%, from a dielectric constant of about 3.9 to an effective dielectric constant of about 2.39. Increasing the volume of air or empty space in dielectric platform18may result in dielectric platform18having a dielectric constant of about 1.5 or less. As a result, passive elements formed over dielectric platform18have reduced parasitic capacitances to substrate14. The parasitic substrate capacitance is reduced by both the reduced effective dielectric constant of dielectric platform18and the increased thickness of dielectric platform18.

In addition, dielectric platform18may be used to increase the frequency of operation of any devices formed using semiconductor structure100. For example, passive components such as, for example, inductors, capacitors, or electrical interconnects, may be formed over embedded dielectric platform18and may have reduced parasitic capacitive coupling between these passive components and substrate14since embedded dielectric platform18has a relatively low dielectric constant or permittivity and since embedded dielectric platform18increases the distance between the passive components and the conductive substrate. Reducing parasitic substrate capacitances may increase the frequency of operation of any devices formed using a dielectric platform. As an example, the passive component may comprise electrically conductive material24, wherein electrically conductive material24may comprise, for example, aluminum, copper, or doped polycrystalline silicon. In various examples, the passive component may be an inductor, a capacitor, a resistor, an electrical interconnect, or a combination thereof and may be coupled to one or more active devices formed in active regions20and21.

Since at least a portion of dielectric platform18is formed in and/or below the surface of the substrate, dielectric platform18may be referred to as an embedded dielectric structure. Embedded may mean that at least a portion of dielectric platform18is below a plane (not shown) that is coplanar to, or substantially coplanar to, top surface16of substrate14. In some embodiments, the portion of dielectric layer18below the plane extends from the plane to a depth of at least about three μm or greater below the plane and the portion of dielectric platform18below the plane has a width of at least about five μm or greater. In other words, at least a portion of dielectric platform18is embedded in substrate14and extends a distance of at least about 3 μm or greater from top surface16toward the bottom surface of substrate14and the portion of dielectric platform18embedded in substrate14has a width of at least about 5 μm or greater in some embodiments.

Further, dielectric platform18may be used to form relatively higher quality factor passive devices such as, for example, capacitors and/or inductors having a relatively higher Q since dielectric platform18may be used to isolate and/or separate the passive devices from the substrate. Active devices, such as transistors or diodes, may be formed in regions adjacent to, or abutting, dielectric platform18, and these active devices may be coupled to passive components such as spiral inductors, interconnects, microstrip transmission lines and the like that are formed on a planar top or upper surface of dielectric platform18. Increasing the distance between the passive components and substrate14allows higher Qs to be realized for these passive components.

As an example, a field effect transistor (FET)76may be formed in active region20and FET89may be formed in active region21. FET76may be a MOSFET and may include a source region78in a portion of substrate14, a drain region80in a portion of substrate14, a gate oxide86over a portion of substrate14, a gate88over gate oxide86, and a channel region84formed in a portion of substrate14under gate oxide86and between source and drain regions78and80, respectively. FET89may be a MOSFET and may include a source region92in a portion of substrate14, a drain region90in a portion of substrate14, a gate oxide96over a portion of substrate14, a gate98over gate oxide96, and a channel region94formed in a portion of substrate14under gate oxide96and between source and drain regions92and90, respectively.

As discussed above, substrate14may comprise a semiconductor material such as, for example, silicon. Substrate14may serve as part of a drain region of a vertical transistor formed in active region21. In this example, a source contact or electrode (not shown) may be formed on or adjacent to an upper surface of substrate14and a drain electrode (not shown) may be formed on or adjacent to a lower surface of substrate14. During operation, the electrical current flow from the source electrode to the drain electrode in the vertical transistor may be substantially perpendicular to the upper and lower surfaces of semiconductor structure100. In other words, current flows essentially vertically through the vertical transistor from the electrode located adjacent a top surface of semiconductor structure100to a drain electrode located adjacent to the opposite bottom surface of semiconductor structure100. An example of a vertical transistor is described in United States (“US”) patent application having application Ser. No. 10/557,135, titled “POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR,” filed Nov. 17, 2005, which claims priority to Patent Cooperation Treaty (“PCT”) International Application Number PCT/US2005/000205 titled “POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR,” having an International Filing Date of Jan. 6, 2005, and an International Publication Date of Jul. 28, 2005, the contents of both of these patent applications are incorporated herein by reference in their entireties.

Power transistors having relatively higher breakdown voltages, and consequently relatively higher power output, may be realized by forming a vertical transistor in an active area adjacent to dielectric platform18, as dielectric platform18may provide edge termination for the equipotential lines from an electric field in an active area that is adjacent to dielectric platform18. Higher breakdown voltages may be achieved as the edge termination provided by dielectric platform18may reduce curvature of the equipotential lines. As is generally understood, curvature of the equipotential lines results in lower breakdown voltages. To maximize breakdown voltage, the equipotential lines are parallel, or substantially parallel, to top surface16of substrate14, and these equipotential lines are planar with little to no curvature.

If devices are designed to have relatively high breakdown voltages, then the lateral sidewall of dielectric platform18that contacts the active region is formed to be a dielectric material that is perpendicular, or substantially perpendicular, relative to top surface16of substrate14, for example as shown inFIG. 1, to allow the equipotential lines to terminate substantially perpendicular at the lateral sidewall of dielectric platform18. Dielectric platform18may be adjacent to, abutting, and/or surrounding, active regions20and21to provide edge termination for terminating equipotential lines in active regions20and21, which may result in relatively higher breakdown voltages for active devices formed in the active regions.

In addition, if dielectric platform18surrounds one or more active regions, then dielectric platform18may also be used to provide electrical isolation. For example, dielectric platform18may be used to electrically isolate active regions from each other, which may also result in electrical isolation between any active devices formed in the isolated active regions.

Although only a single active device is discussed as being formed in active regions20and21, the methods and apparatuses described herein are not limited in this regard. In some embodiments, a plurality of active devices may be formed in active regions20and21. Further, the types of active devices are not limited to being FETS. Other types of devices that may be formed in active regions20and21include bipolar junction transistors, junction field effect transistors, insulated gate bipolar junction transistors, diodes, thyristors, passive devices, or the like, and the scope of the claimed subject matter is not limited in these respects.

FIG. 2is a cross-sectional view of a semiconductor structure at a beginning stage of manufacture, in accordance with an embodiment. What is shown inFIG. 2is substrate14, which may be used as a substrate for the fabrication of semiconductor structure100ofFIG. 1, semiconductor structure200ofFIG. 11, and/or semiconductor structure300ofFIG. 19, which represent different embodiments as discussed herein. Substrate14may comprise a semiconductor material such as, for example, silicon, and may be doped or undoped depending on the application, although the claimed subject matter is not limited in this regard. Substrate14may have a thickness ranging from about 100 μm to about 1,000 μm. However, the thickness of substrate14may be reduced through subsequent thinning processes in some embodiments.

A layer of dielectric material50may be formed over substrate14. Layer50may comprise, for example, silicon dioxide (“SiO2”) and may have a thickness ranging from about 100 Å to about 5,000 Å. Silicon dioxide layer50may be formed using deposition techniques or thermal growth techniques such as, for example, thermal oxidation of silicon.

After the oxidation process is performed, silicon dioxide layer50and substrate material14may be patterned using photolithography and etching processes. Photolithography processes or operations involve the use of masks and may sometimes be referred to as masking operations or acts. The photolithography and etching may include forming a layer of a radiation-sensitive material, such as photoresist (not shown), over the semiconductor structure, then exposing the photoresist using, for example, ultraviolet (“UV”) radiation to form a mask, and then etching portions of silicon dioxide layer50using an isotropic or anisotropic etch process such as, for example, wet chemical etching or a reactive ion etch (“RIE”), respectively, to form one or more opening44. Masked area48formed using dielectric layer50may also formed in this process.

Silicon dioxide layer50may serve as a hard mask, and may be referred to as a masking layer. Since the photoresist over silicon dioxide layer50is also etched as part of the silicon etch used to etch portions of substrate14, dielectric layer50may be used as a hard mask to prevent the undesired etching of the upper surface of substrate14during the formation of cavity64(FIG. 3). Layer50is optional, as in alternate embodiments, the subsequent photoresist layer may be made relatively thick such that it is not completely eroded during the etching process of cavity64as shown inFIG. 3, and therefore, the photoresist may be used as a masking layer rather than using layer50.

In some embodiments the width of opening44may be in the range of about 1 μm to about 5 μm and the width of mask area48may be in the range of about 1 μm to about 15 μm. The width of opening44may determine the width of subsequently formed cavity64as shown inFIG. 3, as well as the spacing between cavities64as shown inFIG. 3. The dielectric constant of the DP is determined at least in part by the relative amounts of void space and dielectric and since void space has a dielectric constant lower than that of dielectric, the overall dielectric constant of the dielectric platform may reduced by maximizing, or nearly maximizing, the volume of void space and/or by minimizing, or nearly minimizing, the volume of dielectric within the dielectric platform. In one embodiment this may be achieved by minimizing the width of opening44and thus cavity64ofFIG. 3, and by maximizing the width of masked area48. As will be discussed in further detail, below, one limitation to maximization of masked area48may be the processing ability to cap the final structure, however the scope of the claimed subject matter is not limited in this respect.

FIG. 3is a cross-sectional view of the structure ofFIG. 2at a later stage of manufacture.FIG. 4is a top view of the structure ofFIG. 3in accordance with an embodiment of the present invention, andFIG. 3is a cross-sectional view taken along section line3-3ofFIG. 4. With reference toFIGS. 3 and 4, after formation of openings44ofFIG. 2a portion of the exposed portions of substrate14are removed by, for example, etching, to form one or more cavity64having sidewalls62. Cavity64may also be referred to as an open cavity, an opening, a void, a gap, an empty region, an empty space, a trench or the like.

The etch process for formation of cavity64is preferably anisotropic but in some embodiments may be isotropic. In one embodiment cavity64may be formed using an anisotropic etch, for example RIE. In some embodiments, cavity64may be formed using at least one etch operation to remove portions of silicon dioxide50and substrate14. In other embodiments, two etching operations may be used to form cavity64. For example, one etch operation may be used to remove portions of silicon dioxide layer50while a second etch operation may be used to remove portions of substrate14.

In other words, the etch forms cavity64having a floor66from which structures60extend. Structures60extend from floor66to top surface16. Turning now toFIG. 4, cavity64may be in the form of a straight trench and the extent of trench64may determine the size and shape of dielectric platform18ofFIG. 1. Although cavity64is described and shown as a trench herein, the claimed subject matter is not limited in this regard, and cavity64may have other shapes. In some embodiments trench64may have a length in the range of about 2 μm to about 1000 μm, however the scope of the claimed subject matter is not limited in this respect, and in other embodiments trench64may be either shorter or longer.

In another embodiment cavity64may be in the form of closed trenches, as shown inFIG. 5.FIG. 5shows a top view of a semiconductor structure similar to that shown inFIG. 4, but with closed trenches. In other words, cavity64may be formed surrounding a portion of substrate14. In this way the dielectric platform may isolate a portion of substrate14from another portion of substrate14using dielectric platform18. As shown inFIG. 4, the end of trench64terminates in substrate14. In contrast, inFIG. 5, trench64forms a loop enclosing a portion of substrate14. This embodiment may be used to form a dielectric platform that isolates active region20from active region21Although cavity64inFIG. 4andFIG. 5are shown with a rectangular cross section, the scope of the claimed subject matter is not limited in this respect, and in other embodiments cavity64may have other shapes including a polygonal shape, a circular shape, or any arbitrary shape.

In some embodiments, the etch chemistry may be selected so that sidewalls62form an angle that is perpendicular, or substantially perpendicular to top surface16. However, the scope of the claimed subject matter is not limited in this respect, and in other embodiments, sidewalls62may be non-perpendicular to surface16. Since cavity64will be filled with dielectric in the final structure ofFIG. 1, in one embodiment the dielectric constant of dielectric platform18may be reduced if sidewalls62form an angle with surface16that is less than 90°. However, this may reduce the width of the top opening of cavity64, making it more difficult to fill in a subsequent processing step. In the example shown inFIG. 3, sidewalls62are shown as substantially perpendicular to surface16.

The depth of cavity64may be in the range of about 1 μm to about 40 μm. In one or more embodiments, the depth of cavity64may be greater than the width of cavity64. Thus, in some embodiments the depth of cavity64may be at least two times (“2×”) greater than the width of cavity64. Alternatively, the depth of cavity64may be at least about ten times (“10×”) greater than the width of cavity64. For example, if the width of cavity64is about 1 μm, the depth of cavity64may be about 10 μm or more.

FIG. 6is a cross-sectional view of the semiconductor structure ofFIG. 3at a later stage of manufacture. After formation of cavity64, a layer of photoresist600may be dispensed over silicon dioxide layer50and cavity64and patterned to form opening610. The exposed portions of silicon dioxide50, including mask region48(FIG. 1) may then be removed to expose the surface portions of substrate14. Silicon dioxide layer50may be removed for example by using an isotropic or anisotropic etch process such as, for example, wet chemical etching or a reactive ion etch (RIE). After removal of the exposed portions of silicon dioxide layer50, photoresist600may be stripped or removed.

FIG. 7is a cross-sectional view of the semiconductor structure ofFIG. 6at a later stage of manufacture. After removal of photoresist600, cavity64ofFIG. 6may be filled with a dielectric material710. In some embodiments dielectric material710may be formed in a conformal process. For example dielectric material710may comprise an oxide or a nitride. In other embodiments dielectric material710may comprise phosphorus silicate glass (PSG), boron silicate glass (BSG), or boron phosphorus silicate glass (BPSG). Suitable techniques for forming dielectric material710include Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), low pressure CVD (LPCVD), spin-on processing, sputtering, evaporation, or the like. In one example dielectric material710may comprise silicon oxide and may be formed using low pressure chemical vapor deposition (LPCVD), for example using a hot wall tetraethylorthosilicon (TEOS) process.

In some embodiments dielectric material710may completely fill cavity64ofFIG. 6, and in other embodiments dielectric material710may partially fill cavity64ofFIG. 6. The dielectric constant of the dielectric platform may be determined at least in part by the relative amounts of void space and dielectric and since void space has a dielectric constant lower than that of dielectric, the overall dielectric constant of the dielectric platform may be relatively reduced by, for example lining cavity64ofFIG. 6with dielectric material710instead of filling cavity64ofFIG. 6with dielectric material710.

In contrast to other processes used to form a dielectric platform, in one or more embodiments dielectric material710is deposited and is not formed by the partial oxidation or nitridation of substrate14, or using any other process that consumes a portion of substrate14. Oxidation or nitridation of substrate14otherwise creates higher stress in the semiconductor and may lead to the generation of defects that can adversely affect device performance. In accordance with one or more embodiments, dielectric material710may be deposited, resulting in relatively lower stress and thus may reduce or eliminate the generation of defects.

After formation of dielectric material710, the portions of dielectric material710above a plane parallel to surface16of substrate14may be removed, for example by etching or by chemical mechanical polishing (CMP), forming oxide structures64A ofFIG. 8. In the example where dielectric material710is silicon oxide, silicon oxide710may be removed using a blanket or an anisotropic etch, for example RIE. The process to remove portions of silicon oxide710above a plane parallel to surface16of substrate14may also optionally remove silicon oxide layer50. In the example shown inFIG. 7, silicon oxide layer50is not removed. In the example shown inFIG. 7andFIG. 8, dielectric material710is removed such that the top of oxide structures64A is level with surface16of substrate14, however the scope of the claimed subject matter is not limited in this respect, and in other embodiments the top of oxide structures64A may be at a height above or below surface16of substrate14

FIG. 8is a cross-sectional view of the semiconductor structure ofFIG. 7at a later stage of manufacture. After removal of portions of silicon oxide710ofFIG. 7above a plane parallel to surface16of substrate14, the remaining silicon oxide710ofFIG. 7may form oxide structures64A. After formation of oxide structures64A, a layer of photoresist800may be dispensed over dielectric layer50, oxide structures64A and the exposed surface16of substrate14and patterned to form opening810. Portions of the exposed portions of substrate14may then be removed to form cavities820. The exposed portions of substrate14may be removed, removed for example by using an isotropic or anisotropic etch process such as, for example, wet chemical etching or a reactive ion etch (“RIE”). In some embodiments, the etchant has a high selectivity between silicon and silicon oxide. In other words the etch rate for silicon may be relatively higher than for oxide. In one embodiment the etch rate of silicon may be at least 10 times greater than the etch rate of oxide. In another embodiment the etch rate of silicon may be at least 50 times greater than the etch rate of oxide. After formation of oxide structure64A, photoresist800may be stripped or removed. In the example shown inFIG. 8, the bottom of cavity820is shown as being as the same level as the bottom of oxide structure64A, however the scope of the claimed subject matter is not limited in this respect, and in other embodiments the bottom of cavity820may be either above or below the bottom of oxide structure64A.

FIG. 9is a cross-sectional view of the semiconductor structure ofFIG. 8at a later stage of manufacture. After removal of photoresist800, a capping material910may be formed over dielectric layer50, portions of substrate14and over the top surface and optionally over portions of sidewalls of oxide structure64A. Capping material910may be deposited, grown, spun-on, or the like. By way of example, capping material910may be a dielectric material that may be non-conformally deposited using, for example, evaporation or sputtering. In some embodiments capping material910may be deposited using a vapor deposition process, for example CVD, LPCVD or PECVD. Suitable dielectric materials for capping material910include silicon oxide, nitride, or the like.

Subsequent sealing of cavities820may be facilitated by the formation of capping material910which reduces the width or lateral dimension of the top of cavities820. In other words, by forming capping material910over oxide structures64A, the distance between capping material910over oxide structures64A may be substantially smaller, or less than, the distance between the lower portions of oxide structures64A. This may facilitate sealing and reduce the overall dielectric constant of the resulting dielectric platform. Thus in one embodiment, capping material910may be formed such that the subsequent spacing between capping material910over oxide structures64A may be minimized, or nearly minimized. The amount of capping material910that is deposited depends at least in part on the spacing between oxide structures64A, the lateral and vertical deposition rate of capping material910, the desired dielectric constant of the dielectric platform, and/or the ability of the subsequently formed sealing layer1010ofFIG. 10to bridge the gaps between capping material910over oxide structures64A. In some embodiments, the thickness of capping material910may range from about 0.5 μm to about 8 μm, however the scope of the claimed subject matter is not limited in this respect, and in other embodiments capping layer may be either thicker or thinner. In some embodiments the distance between the capping materials910on oxide structures64A may be about 2 μm or less. In one example oxide structure64A may be about 2 μm wide, cavity820may be about 5 μm and capping material910may extend about 2 μm past the edge of oxide structure64A, leaving a gap between capping materials910over oxide structure64A of about 1 μm.

FIG. 10is a cross-sectional view of the semiconductor structure ofFIG. 9at a later stage of manufacture. After formation of capping material910, sealing material1010may be formed in a conformal process over capping material910, cavities820and optionally over portions of the interior surfaces of cavities820to bridge the gaps between capping materials910over oxide structures64A and seal cavity820ofFIG. 9to form sealed cavity820A. For example sealing material1010may comprise an oxide or a nitride and may be formed using low pressure chemical vapor deposition (LPCVD), for example a hot wall tetraethylorthosilicon (TEOS) process to deposit silicon dioxide. In some embodiments sealing material1010may partially or completely line cavity820ofFIG. 9, and in other embodiments sealing material1010may not enter into cavity820ofFIG. 9. The dielectric constant of the dielectric platform may be determined at least in part by the relative amounts of void space and dielectric, and since void space has a dielectric constant lower than that of dielectric, the overall dielectric constant of the dielectric platform may be relatively reduced, for example by increasing the volume of sealed cavities820A, reducing the volume of dielectric material in dielectric structures64A, and/or reducing the amount of dielectric capping material910and sealing material1010contained in dielectric platform18. In some embodiments sealing material1010may have a thickness in the range of about 0.25 μm to about 4 μm.

In some embodiments sealing material1010may hermetically seal cavity64A. In other embodiments an optional layer (not shown), for example, silicon nitride (Si3N4), may be formed over sealing material1010to hermetically seal cavity64A. The optional silicon nitride layer may be formed using a low pressure chemical vapor deposition (LPCVD) technique and may have a thickness ranging from about 100 Å to about 1,000 Å.

In some embodiments, sealed cavity820A is evacuated to a pressure less than atmospheric pressure. In other words, the pressure in sealed cavity820A is below atmospheric pressure. As an example, the pressure in sealed cavity820A may range from about 0.1 Torr to about 10 Torr. The type of substance or material within cavity820A is not a limitation of the present invention. For example, sealed cavity820A may contain solid matter or a fluid such as a gas or a liquid.

Referring back toFIG. 1, the portions of sealing material1010, capping material910, and silicon dioxide layer50in active regions20and21are removed after the formation of sealing material1010. Active and passive semiconductor devices may be formed in or from the portions of substrate14adjacent dielectric platform18. In addition, active or passive circuit elements, or portions thereof, may be formed on dielectric platform18. By way of example, a passive circuit element24is formed on dielectric platform18.

Although four capped or sealed cavities64A are described with reference toFIGS. 1-10, the scope of the claimed subject matter is not limited in this regard. In other embodiments, the number of sealed cavities may be smaller or greater than shown in this example. Sealing material1010and capping material910in combination with oxide structures64A and sealed cavities820A form dielectric platform (DP)18as shown inFIG. 1.

Although dielectric platform18is described as having one or more cavities820A, scope of the claimed subject matter is not limited in this regard. For example, in alternate embodiments, cavity820A could be filled with a material, such as, for example, a material comprising an oxide, nitride, or silicon if so desired, to form a solid or filled dielectric platform (not shown) that is devoid of any cavities. Such a solid filled dielectric platform would have a relatively higher dielectric constant compared to a sealed cavity dielectric platform such as dielectric platform18since the material used to fill cavity820A would have a higher dielectric constant compared to a cavity, opening, or void. Examples of materials that may be used to fill, or backfill, cavity820A may include silicon nitride, polycrystalline silicon, or an oxide material formed using, for example, a hot wall tetraethylorthosilicon (TEOS) process.

As discussed above, the dielectric constant of DP18may be minimized, or nearly minimized, by increasing the volume of sealed cavities820A, reducing the volume of dielectric material in dielectric structures64A, and reducing the amount of dielectric layer50, dielectric capping material910and sealing material1010contained in dielectric platform18. Semiconductor structure100has one or more dielectric structures64A that act to increase the dielectric constant of dielectric platform18. In another embodiment of the present invention, the number of dielectric structures64A may be reduced or eliminated to increase the volume of void space and relatively decrease the dielectric constant.

FIG. 11is a cross-sectional view of semiconductor structure200in accordance with another embodiment. Semiconductor structure200comprises dielectric platform (DP)18, active regions20and21, and an electrically conductive material24in accordance with an embodiment of the present invention. Dielectric platform18may be referred to as a dielectric structure or a dielectric region, and active regions20and21may also be referred to as active area regions, active areas, or portions of active areas since active devices, or portions of active devices, typically are formed in active regions20and21.

Dielectric platform18of semiconductor structure200comprises a sealed cavity1610A bounded by dielectric material1410A. In addition to sealed cavity1610A and dielectric material1410A, dielectric platform18shown inFIG. 11includes optional support layer1810.

In one embodiment, the initial processing steps for forming semiconductor structure200shown inFIG. 11may be the same as described inFIGS. 2-7. AccordinglyFIG. 12is a cross-sectional view of the semiconductor structure ofFIG. 7at a later stage of manufacture. After removal of portions of silicon oxide710ofFIG. 7above a plane parallel to surface16of substrate14, the remaining silicon oxide710(FIG. 7) may form oxide structures64A.

After formation of oxide structures64A, a layer of photoresist1280may be dispensed over oxide layer50, oxide structures64A and the exposed surface16of substrate14and patterned to form opening1210. Portions of the exposed portions of substrate14may then be removed to form cavities820. The exposed portions of substrate14may be removed, removed for example by using an isotropic or anisotropic etch process such as, for example, wet chemical etching or a reactive ion etch (RIE). In some embodiments, the etchant has a higher selectivity between silicon and silicon oxide. In other words the etch rate for silicon may be relatively higher than for oxide. In one embodiment the etch rate of silicon may be at least 10 times greater than the etch rate of oxide. In another embodiment the etch rate of silicon may be at least 50 times greater than the etch rate of oxide. After formation of cavities820, photoresist1280may be stripped or removed.

In the example shown inFIG. 12, the bottom of cavity820is shown as being as below the level of the bottom of oxide structure64A. In some embodiments, the height of oxide structures64A may range from about 1 μm to about 40 μm and the depth of open cavities820may range from about 1 μm to about 50 μm. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments the bottom of cavity820may be either above or equal to the bottom of oxide structure64A.

FIG. 13is a cross-sectional view of the semiconductor structure ofFIG. 12at a later stage of manufacture. After removal of photoresist1280, cavities820ofFIG. 12may be filled with dielectric material1310that will subsequently form oxide structures820A. In some embodiments dielectric material1310may be formed in a conformal process. For example dielectric material1310may comprise an oxide or a nitride. In other embodiments dielectric material1310may comprise phosphorus silicate glass (PSG), boron silicate glass (BSG), or boron phosphorus silicate glass (BPSG). Suitable techniques for forming dielectric material1310may include Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), low pressure CVD (LPCVD), sputtering, evaporation, or the like. In one example dielectric material1310may comprise silicon oxide and may be formed using low pressure chemical vapor deposition (LPCVD), for example using a hot wall tetraethylorthosilicon (TEOS) process. In some embodiments dielectric material1310may completely, or nearly completely, fill cavity820ofFIG. 12, and in other embodiments dielectric material1310may partially fill cavity820ofFIG. 12.

In contrast to other processes used to form a dielectric platform, in accordance with one or more embodiments dielectric material1310is deposited and is not formed by the partial oxidation or nitridation of substrate14, or using any other process that consumes a portion of substrate14. Oxidation or nitridation of substrate14may create higher stress in the semiconductor and lead to the generation of defects that can adversely affect device performance. In one or more embodiments dielectric material710may be deposited, resulting in relatively lower stress and thus may reduce or eliminate the generation of defects.

FIG. 14is a cross-sectional view of the semiconductor structure ofFIG. 13at a later stage of manufacture. After formation of dielectric material1310, the portions of dielectric material1310above a plane parallel to surface16of substrate14may be removed, for example by etching or by chemical mechanical polishing (CMP), forming oxide structures820A. In the example where dielectric material1310is silicon oxide, silicon oxide1310may be removed using a blanket or an anisotropic etch, for example RIE. The process to remove portions of silicon oxide1310above a plane parallel to surface16of substrate14may also optionally remove silicon oxide layer50. In the example shown inFIG. 14, silicon oxide layer50is not removed. In the example shown inFIG. 14, dielectric material1310is removed such that the top of oxide structures820A is level with surface16of substrate14and the top of oxide structures64A. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments the top of oxide structures64A may be at a height above or below surface16of substrate14and the top of oxide structures820A may be at a height above or below surface16of substrate14. Furthermore, the tops of oxide structure820A and oxide structure64A may or may not be at the same height. After formation of oxide structures820A, capping layer1410may be formed over portions of substrate14, dielectric structures64A, oxide layer50and dielectric structures820A.

Capping layer1410may comprise a material for which a selective etch exists with respect to the material comprising dielectric structures64A and820A. In one embodiment, in subsequent processing steps openings will be formed in capping layer1410to permit the introduction of an etchant to remove dielectric structures64A and820A. The etchant should have a relatively high etch rate for the material comprising dielectric structures64A and820A compared to the material comprising capping layer1410, such that not all of capping layer1410is removed prior to removal of dielectric structures64A and820A. In one example the etch rate of the material comprising dielectric structures64A and820A may be at least ten times higher than the etch rate of the material comprising capping layer1410. In another example, the etch rate of the material comprising dielectric structures64A and820A may be at least one hundred times higher than the etch rate of the material comprising capping layer1410. In one example capping layer1410may comprise polysilicon or silicon nitride and dielectric structures64A and820A may comprise silicon oxide. Suitable techniques for forming capping layer1410may include Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), low pressure CVD (LPCVD), sputtering, evaporation, spinning on or the like. In one example capping layer1410may have a thickness in the range of about 0.1 μm to about 10 μm.

FIG. 15is a cross-sectional view of the semiconductor structure ofFIG. 14at a later stage of manufacture. After formation of capping layer1410, capping layer1410may be patterned to form openings1510in capping layer1410. In one example, a layer of photoresist (not shown) may be dispensed over capping layer1410(FIG. 14) and patterned to form openings exposing portions of capping layer1410that may then be removed to form openings1510. The exposed portions of capping layer1410may be removed, for example by using an isotropic or anisotropic etch process such as, for example, wet chemical etching or a reactive ion etch (RIE). The width of openings1510may be sufficient to permit a subsequent etchant to access dielectric structures64A and820A and to permit removal of etching products, yet may be small enough to permit subsequent capping. In one example openings1510may have a width in the range of about 0.1 μm to about 1 μm. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments openings1510may be smaller or larger.

FIG. 16is a cross-sectional view of the semiconductor structure ofFIG. 15at a later stage of manufacture. After formation of openings1510in capping layer1410, dielectric structures64A and820A may be removed resulting in the formation of a single open cavity1610with a plurality of openings1510. Open cavity1610may also be referred to as a cavity, a gap, a void, an open cell or the like. Dielectric structures64A and820A may be removed, for example by using an etchant that has a relatively higher etch rate for the materials that comprise dielectric structures64A and820A compared to the etch rate for materials that comprise capping layer1410, as discussed above. The etchant may be either anisotropic or isotropic and may be a wet chemical etch, a dry, for example RIE etch or a vapor etch. In one example in which dielectric structures64A and820A comprise silicon oxide and capping layer1410comprises polysilicon, the etchant may comprise either a hydrofluoric (HF) based wet chemical etch or a HF-based vapor etch. In one example all or substantially all of dielectric structures64A and820A may be removed. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments a portion of either dielectric structures64A and/or820A may be removed. In another embodiment, the previously deposited photoresist may be left over capping layer1410and portions of capping layer1410and all or portions of dielectric structures64A and820A may be removed using one etching step.

The removal of dielectric structures64A and820A results in the formation of a single open cavity1610with a plurality of openings1510. The width of cavity1610may be approximately n1*w1+n2*w2, where n1and n2are the number of dielectric structures64A and820A respectively and w1and w2are the widths of dielectric structures64A and820A respectively. In the example shown inFIGS. 12-15, n1=5 and n2=4, however the scope of the claimed subject matter is not limited in this respect, and in other embodiments, n1and n2may be either larger or smaller than the values presented in this example. Using n1and n2fromFIGS. 12-15, In one example w1may be about 1 μm and w2may be about 2 μm, resulting in a width of open cavity1610of 13 μm. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments the width of cavity1610may be either smaller or larger. As the width of cavity1610increases, the thickness of capping layer1410may increase to retain the integrity of capping layer1410and ensure no cracks or breakage in this layer.

FIG. 17is a cross-sectional view of the semiconductor structure ofFIG. 16at a later stage of manufacture. After removal of dielectric structures64A and820A, open cavity1610ofFIG. 16may be sealed to form closed cavity1610A. Closed cavity1610A may also be referred to as a sealed cavity, a sealed gap, a closed void, a closed cell or the like. In one embodiment in which capping layer1410comprises polysilicon, for example as shown inFIG. 11,FIG. 17and/orFIG. 18, polysilicon layer1410may be oxidized to form silicon oxide. Because of the about 2.2 times volume expansion that occurs when silicon is oxidized, the oxide will expand laterally into openings1510ofFIG. 16and eventually close openings1510ofFIG. 16, thereby forming sealed cavity1610A. In one embodiment of the present invention, the oxidizing ambient may also enter into open cavity1610ofFIG. 16and oxidize the interior surfaces of open cavity1610ofFIG. 16at the same time, or nearly at the same time, as openings1510FIG. 16are being closed by the oxidation process. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments only a portion of, or none of, the interior surfaces of open cavity1610ofFIG. 16may be oxidized. In the example shown inFIG. 17, polysilicon layer1410may be completely, or nearly completely, oxidized to form a continuous, or nearly continuous, oxide layer1410A over sealed cavity1610A and over the interior surfaces of sealed cavity1610A. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments polysilicon layer1410may not be completely oxidized.

The thickness of oxide layer1410A may depend in part on the width of openings1510ofFIG. 16. Relatively smaller openings1510ofFIG. 16may utilize a smaller amount of oxide to form sealed cavity1610A. A relatively smaller oxide thickness may result in lower stress induced by both the volume expansion of silicon upon oxidation and the different coefficients of thermal expansion in semiconductor structure200. In one example oxide layer1410A may be in the range of about 0.1 μm to about 2 μm.

In another embodiment (not shown), a sealing material may be formed in a conformal or non-conformal process over capping layer1410ofFIG. 16and open cavity1610ofFIG. 16to close openings1510ofFIG. 16in capping layer1410ofFIG. 16to form sealed cavity1610A. For example the sealing material may comprise an oxide or a nitride and may be formed using low pressure chemical vapor deposition (LPCVD), for example a hot wall tetraethylorthosilicon (TEOS) process to deposit silicon dioxide. In some embodiments the sealing material may partially or completely line cavity1610A and in other embodiments the sealing material may not enter into cavity1610A. In some embodiments the sealing material may have a thickness in the range of about 0.25 μm to about 4 μm.

In some embodiments, sealed cavity1610A may be evacuated to a pressure less than atmospheric pressure. In other words, the pressure in sealed cavity1610A may be below atmospheric pressure. As an example, the pressure in sealed cavity1610A may range from about 0.1 Torr to about 10 Torr. The type of substance or material within cavity1610A is not a limitation of the present invention. For example, sealed cavity1610A may contain solid matter or a fluid such as a gas or a liquid.

FIG. 18is a cross-sectional view of the semiconductor structure ofFIG. 17at a later stage of manufacture. After formation of sealed cavity1610A, an optional support layer1810may be formed over capping layer1410A. Optional support layer1810may be used to impart additional structural rigidity to dielectric platform18ofFIG. 11, and/or to ensure that sealed cavity1610A is spanned without cracking or breakage which could destroy the integrity of sealed cavity1610A. In one embodiment of the present invention support layer1810may be formed in a conformal or non-conformal process over oxide layer1410A. For example optional support material1810may comprise an oxide or a nitride and may be formed using low pressure chemical vapor deposition (LPCVD), for example a hot wall tetraethylorthosilicon (TEOS) process to deposit silicon dioxide. In some embodiments support layer1810may have a thickness in the range of about 0.25 μm to about 20 μm.

Oxide layer1410A in combination with sealed cavity1610A and optional support layer1810form dielectric platform (DP)18shown inFIG. 11. Although one sealed cavity1610A is described with reference toFIGS. 12-18, the scope of the claimed subject matter is not limited in this regard. In other embodiments, dielectric platform18ofFIG. 11may comprise two or more sealed cavities1610A.

Referring back toFIG. 11, the portions of oxide layer1410A, silicon dioxide layer50and optional support layer1810in active regions20and21may be removed after the formation of oxide layer1410A and optional support layer1810. Active and passive semiconductor devices may be formed in or from the portions of substrate14adjacent dielectric platform18. In addition, active or passive circuit elements, or portions thereof, may be formed on dielectric platform18. By way of example, a passive circuit element24is formed on dielectric platform18.

Although dielectric platform18is described as having one sealed cavity1610A, the scope of the claimed subject matter is not limited in this regard. For example, in alternate embodiments, cavity1610A optionally could be filled with a material, such as, for example, a material comprising an oxide, nitride, or silicon, to form a solid or filled dielectric platform (not shown) that is devoid or nearly devoid of any cavities. Such a solid filled dielectric platform would have a relatively higher dielectric constant compared to a sealed cavity dielectric platform such as dielectric platform18since the material used to fill cavity1610A would have a higher dielectric constant compared to a cavity, opening, or void. Examples of materials that may be used to fill, or backfill, cavity16610A may include silicon nitride, polycrystalline silicon, or an oxide material formed using, for example, a hot wall tetraethylorthosilicon (TEOS) process.

As discussed above, the dielectric constant of dielectric platform18may be minimized, or nearly minimized, by increasing the volume of sealed cavity1610A, for example by reducing the depth of the dielectric platform, reducing the volume of oxide in oxide layer1410A and/or reducing the amount of dielectric material in optional support layer1810contained in dielectric platform18.

FIG. 19is a cross-sectional view of semiconductor structure300in accordance with another embodiment. Semiconductor structure300comprises dielectric platform (DP)18, active regions20and21, and an electrically conductive material24in accordance with an embodiment of the present invention. Dielectric platform18may be referred to as a dielectric structure or a dielectric region, and active regions20and21may also be referred to as active area regions, active areas, or portions of active areas since active devices, or portions of active devices, typically are formed in active regions20and21. Dielectric platform18of semiconductor structure300comprises sealed cavity2410A, dielectric structures64B, dielectric layer50, capping layer2110and sealing layer2510.

In one embodiment of the present invention the initial processing steps for semiconductor structure300shown inFIG. 19may be the same as described inFIGS. 2-7. AccordinglyFIG. 20is a cross-sectional view of the semiconductor structure ofFIG. 7at a later stage of manufacture. After removal of portions of silicon oxide710ofFIG. 7above a plane parallel to surface16of substrate14, the remaining silicon oxide710ofFIG. 7may form oxide structures64A. In the example shown inFIG. 20, the width of openings44ofFIG. 2and masked areas48FIG. 2are substantially equal. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments, for example shown inFIG. 2, the width of openings44ofFIG. 2and masked areas48ofFIG. 2may not be equal. In the example shown inFIG. 20, the width of oxide structures64A may be in the range of about 1 μm to about 15 μm and the spacing between oxide structures64A may be in the range of about 1 μm to about 15 μm.

FIG. 21is a cross-sectional view of the semiconductor structure ofFIG. 20at a later stage of manufacture. After formation of oxide structures64A, capping layer2110may be formed over oxide layer50, dielectric structures64A and portions of substrate14.

Capping layer2110may comprise a material for which a selective etch exists with respect to the material comprising substrate14. In one embodiment openings will subsequently be formed in capping layer2110to permit the introduction of an etchant to remove portions of substrate14. The etchant should have a relatively high etch rate for the material comprising substrate14compared to the material comprising capping layer2110, such that not all of capping layer2110is removed prior to completion of the etch of portions of substrate14. In one example the etch rate of the material comprising substrate14may be at least ten times higher than the etch rate of the material comprising capping layer2110. In another example, the etch rate of the material comprising substrate14may be at least one hundred times higher than the etch rate of the material comprising capping layer2110. In one example of the present invention, the etchant used to remove portions of substrate14may also have a relatively low etch rate for the material comprising dielectric structures64A. In one example capping layer2110may comprise silicon nitride and dielectric structures64A may comprise silicon oxide. Suitable techniques for forming capping layer2110may include Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), low pressure CVD (LPCVD), sputtering, evaporation, spinning on or the like. In one example capping layer2110may have a thickness in the range of about 0.1 μm to about 10 μm.

FIG. 22is a cross-sectional view of the semiconductor structure ofFIG. 21at a later stage of manufacture. After formation of capping layer2110, capping layer2110may be patterned to form openings2210in capping layer2110. In one example, a layer of photoresist (not shown) may be dispensed over capping layer2110ofFIG. 20and patterned to form openings exposing portions of capping layer2110that may then be removed to form openings2210. The exposed portions of capping layer2110may be removed, for example by using an isotropic or anisotropic etch process such as, for example, wet chemical etching or a reactive ion etch (RIE). The width of openings2210may be sufficient to permit a subsequent etchant to access substrate14and to permit removal of etching products, yet may be small enough to permit subsequent capping. In one example openings2210may have a width in the range of about 0.1 μm to about 1 μm. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments openings2210may be smaller or larger.

FIG. 23is a cross-sectional view of the semiconductor structure ofFIG. 22at a later stage of manufacture. After formation of openings2210ofFIG. 22in capping layer2110, portions of substrate14between dielectric structures64A may be removed resulting in the formation of open cavities2320. Open cavities2320may also be referred to as a cavity, a gap, a void, an open cell or the like. Portions of substrate14may be removed, for example by using an etchant that has a relatively high etch rate for the materials that comprise substrate14compared to the etch rate for materials that comprise capping layer2110, as discussed above. The etchant may be either anisotropic or isotropic and may be a wet chemical etch, a dry, for example RIE etch or a vapor etch. In one example in which substrate14comprises silicon and capping layer2110comprises silicon nitride, the etchant may comprise either a wet chemical etch or a vapor etch. In one example all, or substantially all, of the portions of substrate14between dielectric structures64A may be removed. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments only a portion of the portion of substrate14between dielectric structures64A may be removed. In yet another embodiment, portions of substrate14below bottom surface2350of dielectric structures64A may also be removed. In one example, shown inFIG. 23, the etchant is an isotropic etch and has removed all of the portion of substrate14between dielectric structures64A as well as a portion of substrate14below bottom surface2350of dielectric structures64A. In such an example, relatively more silicon is removed from the dielectric platform, resulting in a lower overall dielectric constant of dielectric platform18. In one embodiment of this example, the lateral etching of substrate14below bottom surface2350of dielectric structures64A may be limited so as not to permit meeting of etch fronts from two adjacent cavities2320. However, the scope of the claimed subject matter is not limited in this respect, and in other embodiments, the bottom surface of cavities2320may be coplanar, or nearly coplanar, with bottom surface2350of dielectric structures64A or the bottom surface of cavities2320may be at a level higher or lower than bottom surface2350of dielectric structures64A. In another embodiment of the present invention, the previously deposited photoresist may be left over capping layer2110and portions of capping layer2110and portions of substrate14may be removed using one etching step.

FIG. 24is a cross-sectional view of the semiconductor structure ofFIG. 23at a later stage of manufacture. After removal of portions of substrate14between dielectric structures64A ofFIG. 23, portions of dielectric structures64A ofFIG. 23may be removed to form a single open cavity2410with a plurality of openings2210. Open cavity24100may also be referred to as a cavity, a gap, a void, an open cell or the like. The width of cavity2410may be approximately n1*w1+n2*w2, where n1and n2are the number of dielectric structures64A ofFIG. 23and the number of open cavities2320ofFIG. 23, respectively, and w1and w2are the widths of dielectric structures64A ofFIG. 23and the spacing between dielectric structures64A ofFIG. 23, respectively. In the example shown inFIGS. 20-23, n1=4 and n2=3, however the scope of the claimed subject matter is not limited in this respect, and in other embodiments, n1and n2may be either larger or smaller than the values presented in this example. In one example w1may be about 3 μm and w2may be about 3 μm, resulting in a width of cavity1610of 21 μm. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments the width of cavity2410may be either smaller or larger. As the width of cavity2410increases, the thickness of capping layer2110may increase to retain the integrity of capping layer2110and ensure little or no cracks or breakage in this layer.

Portions of dielectric structures64A ofFIG. 23may be removed, for example by using an etchant that has a relatively high etch rate for the materials that comprise dielectric structures64A ofFIG. 23compared to the etch rate for materials that comprise capping layer2110. The etchant may be either anisotropic or isotropic and may be a wet chemical etch, a dry, for example RIE etch or a vapor etch. In one example in which dielectric structures64A ofFIG. 23comprises silicon oxide and capping layer2110comprises silicon nitride, the etchant may comprise either a wet chemical etch or a vapor etch. In one example all or substantially all of dielectric structures64A ofFIG. 23may be removed. In another embodiment, as shown inFIG. 24, dielectric structures64A ofFIG. 23on the edge of dielectric platform18, that is adjacent to substrate14, may be only partially removed while dielectric structures64A ofFIG. 23within the interior of dielectric platform18are completely, or nearly completely, removed. In this example, a portion of dielectric structures64A ofFIG. 23on the edge of dielectric platform18are partially removed, leaving dielectric structures64B. However the scope of the claimed subject matter is not limited in this respect, and in other embodiments portions of or all of dielectric structures64A may be removed. In another embodiment, the previously deposited photoresist used to pattern openings2210in capping layer2110may be may be left over capping layer2110and portions of capping layer2110, portions of substrate14and portions or all of dielectric structures64A ofFIG. 23may be removed using one or more etching steps.

FIG. 25is a cross-sectional view of the semiconductor structure ofFIG. 24at a later stage of manufacture. After formation of open cavity2410ofFIG. 24, sealing layer2510may be formed over openings2210ofFIG. 24, open cavity2410and capping layer2110ofFIG. 24to form closed cavity2410A.

Sealing layer2510may be formed in a conformal or non-conformal process over openings2210ofFIG. 24and capping layer2110to close openings2110ofFIG. 24in capping layer2110to form closed cavity2410A. Closed cavity2410A may also be referred to as a sealed cavity, a sealed gap, a closed void, a closed cell or the like. In one example sealing layer2510may comprise a dielectric material such a silicon oxide or silicon nitride and may be formed using low pressure chemical vapor deposition (LPCVD), for example a hot wall tetraethylorthosilicon (TEOS) process to deposit silicon dioxide. In other examples, sealing layer2510may be formed using a spin-on process, or by evaporation, sputtering or the like. In other embodiments sealing layer2510may partially enter into sealed cavity2410A and in other embodiments sealing layer2510may not enter into cavity2410A. In some embodiments sealing layer2510may have a thickness in the range of about 0.25 μm to about 4 μm.

In some embodiments, sealed cavity2410A may be evacuated to a pressure less than atmospheric pressure. In other words, the pressure in sealed cavity2410A may be below atmospheric pressure. As an example, the pressure in sealed cavity2410A may range from about 0.1 Torr to about 10 Torr. However, this is one example of the type of substance or material within cavity2410A, and the scope of the claimed subject matter is not limited in this respect. For example, sealed cavity2410A may contain solid matter or a fluid such as a gas or a liquid.

In some embodiments an optional support layer (not shown) may be formed over sealing layer2510. The optional support layer may be used to impart additional structural rigidity to dielectric platform18ofFIG. 19and to ensure that sealed cavity2410A is spanned without cracking or breakage which would otherwise destroy the integrity of sealed cavity2410A. In one embodiment of the optional support layer may be formed in a conformal or non-conformal process over sealing layer2510. In one example the optional support material may comprise an oxide or a nitride and may be formed using low pressure chemical vapor deposition (LPCVD), for example a hot wall tetraethylorthosilicon (TEOS) process to deposit silicon dioxide. In other embodiments, optional support layer may be formed using a spin-on process, evaporation, sputtering or the like. In some embodiments the optional support layer may have a thickness in the range of about 0.25 μm to about 20 μm.

Capping layer2110and sealing layer2510in combination with sealed cavity2410A, dielectric layer50and dielectric structures64B form dielectric platform (DP) as18shown inFIG. 19. Although one sealed cavity2410A is described with reference toFIGS. 19-25, the scope of the claimed subject matter is not limited in this regard. In other embodiments, dielectric platform18ofFIG. 19may comprise two or more sealed cavities2410A.

Referring back toFIG. 19, the portions of dielectric layer50, capping layer2110and sealing layer2510in active regions20and21are removed after the formation of sealing layer2510. Active and passive semiconductor devices may be formed in or from the portions of substrate14adjacent dielectric platform18. In addition, active or passive circuit elements, or portions thereof, may be formed on dielectric platform18. By way of example, a passive circuit element24is formed on dielectric platform18.

Although dielectric platform18is described as having one sealed cavity2410A, the scope of the claimed subject matter is not limited in this regard. For example, in alternate embodiments, cavity2410A could be filled with a material, such as, for example, a material comprising an oxide, nitride, or silicon if so desired, to form a solid or filled dielectric platform (not shown) that is devoid, or nearly devoid, of any cavities. Such a solid filled dielectric platform would have a relatively higher dielectric constant compared to a sealed cavity dielectric platform such as dielectric platform18since the material used to fill cavity2410A would have a higher dielectric constant compared to a cavity, opening, or void. Examples of materials that may be used to fill, or backfill, cavity2410A may include silicon nitride, polycrystalline silicon, or an oxide material formed using, for example, a hot wall tetraethylorthosilicon (TEOS) process.

Accordingly, various structures and methods have been disclosed to provide a relatively thicker, embedded dielectric platform that may be a dielectric support structure capable of supporting one or more passive devices over the dielectric platform. In various embodiments, the disclosed dielectric platform may provide electrical isolation, reduce parasitic substrate capacitance, allow for the formation of passive devices having a relatively higher Q, and enable relatively higher frequency of operation of one or more devices formed using, or in conjunction with, a structure that includes the dielectric platform. In addition, the disclosed dielectric platform and/or the methods for making the dielectric platform may reduce thermal stress that may be imparted to regions adjacent to the dielectric platform compared to other techniques and structures. Further, methods and apparatuses have been disclosed that provide a semiconductor structure having a relatively high thermal conductivity, which may be utilized in applications where the efficient removal of heat is desired.

Although the claimed subject matter has been described with a certain degree of particularity, it should be recognized that elements thereof may be altered by persons skilled in the art without departing from the spirit and/or scope of claimed subject matter. It is believed that the subject matter pertaining to a semiconductor structure as discussed herein and/or many of its attendant utilities will be understood by the forgoing description, and it will be apparent that various changes may be made in the form, construction and/or arrangement of the components thereof without departing from the scope and/or spirit of the claimed subject matter or without sacrificing all of its material advantages, the form herein before described being merely an explanatory embodiment thereof, and/or further without providing substantial change thereto. It is the intention of the claims to encompass and/or include such changes.