Semiconductor device including output circuit constituted of plural unit buffer circuits in which impedance thereof are adjustable

The semiconductor device comprises an output circuit that includes a plurality of unit buffer circuits each of which has an adjustable impedance, a control circuit that selectively activates one or ones of the unit buffer circuits, and an impedance adjustment unit that adjusts the impedances of the unit buffer circuits and includes a power line, a replica circuit, which has a replica impedance that is substantially equal to the adjustable impedance of each of the unit buffer circuits, and a load current generation circuit, which changes current flowing therethrough in accordance with the number of activated the one or ones of the unit buffer circuits. The replica circuit and the load current generation circuit are connected in common to the power line.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device that includes an impedance adjustment unit.

2. Description of Related Art

As a data transfer speed between semiconductor devices increases, impedance of an output circuit is needed to become more accurate.

In particular, some DRAMS, which are one type of semiconductor memory, are so formed as to be able to change the impedance of an output circuit thereof at the time of data outputting in accordance with the impedance of a data bus connected to the DRAMs.

For example, Japanese Patent Application Laid-Open No. 2006-203405 shows a semiconductor device including an impedance adjustment unit that is designed to adjust the impedance of an output circuit. More specifically, the output circuit includes a plurality of unit buffer circuits; an impedance adjustment unit provided in common to the unit buffer circuits to adjust the impedances of the unit buffer circuits in common to a desired impedance. By changing the number of unit buffer circuits that are activated at the time of data outputting, the output circuit drives an output terminal with a required impedance.

The impedance adjustment unit uses a replica circuit corresponding to one unit buffer circuit to adjust the impedances of the unit buffer circuits in common. Meanwhile, the output circuit uses one or more unit buffer circuits to drive the output terminal. In this manner, if the output circuit uses two or more unit buffer circuits to drive the output terminal, the number of the unit buffer circuits that actually drive the output terminal is not reflected in the impedance adjustment unit. In the output circuit, according to the number of the unit buffer circuits activated, the voltage drop (and voltage rise) between a power supply line and a unit buffer circuit varies. Therefore, in the impedance adjustment process of Japanese Patent Application Laid-Open No. 2006-203405, there is concern that the impedance of the output circuit could deviate from the required impedance.

SUMMARY

In one aspect of this disclosure, there is provided a semiconductor device comprising: an output circuit including a plurality of unit buffer circuits each having an impedance that is adjustable; a control circuit selectively activating one or ones of the unit buffer circuits; and an impedance adjustment unit adjusting the impedances of each of the unit buffer circuits, the impedance adjustment unit including a power line, a replica circuit and a load current generation circuit, the replica circuit and the load current generation circuit being connected in common to the power line, the replica circuit having an replica impedance that is substantially equal to the impedance of each of the unit buffer circuits, the load current generation circuit changing current flowing therethrough in response to the number of activated the one or ones of the unit buffer circuits.

In another aspect of this disclosure, there is provided a device comprising: a first terminal; a plurality of output buffers coupled in common to the first terminal; an output control circuit receiving a first control signal and activating one or ones of the output buffers in response to the first control signal; and an impedance adjustment unit including a replica circuit, a plurality of current generation circuits and a power line, the replica circuit and the current generation circuits being coupled in common to the power line, the impedance adjustment unit adjusting an impedance of each of the output buffers in response to an impedance of the replica circuit, the impedance adjustment unit further including a current control circuit receiving the first control signal and activating one or ones of the current generation circuits in response to the first control signal.

In still another aspect of this disclosure, there is provided a system comprising a control device and a memory device coupled to the control device. The memory device comprising; a first terminal coupled to the control device; a plurality of output buffers coupled in common to the first terminal; an output control circuit receiving a first control signal and activating one or ones of the output buffers in response to the first control signal; and an impedance adjustment unit including a replica circuit, a plurality of current generation circuits and a power line. The replica circuit and the current generation circuits are coupled in common to the power line. The impedance adjustment unit adjusts an impedance of each of the output buffers in response to an impedance of the replica circuit. The impedance adjustable circuit further includes a current control circuit receiving the first control signal and activating one or ones of the current generation circuits in response to the first control signal.

According to the present invention, the impedance adjustment unit changes the quantity of current flowing through the impedance adjustment unit in accordance with the number of unit buffer circuits selectively activated, in the load current generation circuit that is connected in parallel to the replica circuit. Therefore, the impedance of the replica circuit is adjusted in accordance with the number of unit buffer circuits. The result of adjusting the impedance of the replica circuit, which is adjusted in accordance with the number of unit buffers, is reflected in the process of adjusting the impedance of the output circuit. As a result, it is possible to improve the accuracy of adjusting the impedance of the output circuit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1schematically shows the configuration of a semiconductor device10at a time when the present invention is applied to a semiconductor device, or to a SDRAM (Synchronous Dynamic Random Access Memory) that operates in synchronization with a clock signal supplied from outside, for example. Incidentally, all the circuit blocks shown inFIG. 1are formed on the same semiconductor chip made of single crystal silicon. For example, the circuit blocks each are made up of a plurality of transistors, such as PMOS transistors (P-channel MOS transistors) and NMOS transistors (N-channel MOS transistors). Those indicated by symbol o (circle) are pads that serve as external terminals provided on the semiconductor chip.

The semiconductor device10includes a memory cell array20, a control circuit21, a mode register22, and a data input/output unit100.

The data input/output unit100, which is one of the features of the semiconductor device10of the present invention, has a DS function. The DS (Driver Strengthen) function is of adjusting the impedance of an output buffer at the time of data outputting. The semiconductor device10enables the DS function by changing the number of unit buffers activated in accordance with an impedance setting code Ron <1, 0> (or an impedance setting signal). The unit buffers make up the output buffer.

The DS function will be detailed later. First, the following outlines the semiconductor device10.

The semiconductor device10includes the following as external terminals (or pads on the semiconductor chip): command terminals12a, address terminals13, data terminals DQ0to DQn, and a calibration terminal ZQ. The semiconductor device10also includes other external terminals, such as clock terminals and power supply terminals; the other external terminals, however, are not shown in the diagram because the other external terminals are substantially unrelated to the present invention.

The command terminals12acollectively represent terminals to which a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, a chip select signal /CS, and any other signal are supplied, for example. A combination of signals input into the above terminals makes up a command signal CMD. The command terminals12aare connected to the control circuit21.

The address terminals13are terminals to which address signals ADD are supplied, and are connected to the control circuit21.

The data terminals DQ are terminals for outputting read data and inputting write data, and are connected to the data input/output unit100. The data input/output unit100is also connected to the calibration terminal ZQ. A calibration operation (described later) in the data input/output unit100is carried out after an external resistance is connected to the calibration terminal ZQ.

The memory cell array20includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; the memory cells are disposed at the intersections of the word and bit lines.

The control circuit21supplies various operation control signals ICNT, which are used to control an operation of the memory cell array20, to the memory cell array20in accordance with a command signal CMD supplied from outside via the command terminals12a, and address signals ADD supplied from outside via the address terminals13.

By supplying various operation control signals ICNT to the memory cell array20, the control circuit controls a read operation and a write operation: the read operation is reading data from memory cells in the memory cell array20; and the write operation is writing data to memory cells.

More specifically, when the command signal CMD is a read command (RD command), the control circuit21supplies an output enable signal OE to the data input/output unit100; the control circuit21also controls the memory cell array20in such a way that data of a memory cell specified by address signals ADD are output to the data input/output unit100as data “Data”. When the command signal CMD is a write command (WT command), the control circuit21controls the data input/output unit100and the memory cell array20in such a way that data “Data” accepted by the data input/output unit100from outside are written into a memory cell specified by address signals ADD among the memory cells of the memory cell array20.

When a command indicating the execution of a calibration operation (or CAL command) is supplied from outside via the command terminals12aas a command signal CMD, the control circuit21supplies a control signals ACT1and ACT2to the data input/output unit100.

When a mode register set command (MRS command) is supplied from outside via the command terminals12aas a command signal CMD, the control circuit21supplies to the mode register22the address signals ADD that are supplied to the address terminals13at a time when the MRS command is supplied, along with the mode register set signal MRS.

The mode register22(MR) changes various settings of the semiconductor device10in accordance with a mode register set signal MRS supplied from the control circuit21and address signals ADD. More specifically, in the case ofFIG. 1, the mode register22supplies to the data input/output unit100an impedance setting code Ron <1, 0> to set the impedances of output circuits of the data input/output unit100. As described later, the impedance setting code Ron <1, 0> is used at a time when data are output in the data input/output unit100, or a signal that specifies the number of unit buffers activated at a time when data are output during a read operation.

Incidentally, according to the present embodiment, for example, among the address signals ADD, the logic level of an address signal A1corresponds and is equal to the logic level of an impedance setting code Ron <0> in the impedance setting code Ron <1, 0>; the logic level of an address signal A5corresponds and is equal to the logic level of an impedance setting code Ron <1>. The mode register22outputs to the data input/output unit100an H-level (high-level) or L-level (low-level) impedance setting code Ron <0> in response to a H-level or L-level of address signal A1; and an H-level or L-level impedance setting code Ron <1> in response to a H-level or L-level of address signal A5.

When the command supplied to the control circuit21is an RD command, and when the memory cell array20is performing a read operation, the data input/output unit100receives data. “Data” supplied from the memory cell array20, and outputs the received data “Data” to outside via the data terminals DQ0to DQn (Data output operation). At this time, the data input/output unit100controls the number of unit buffers driving the data terminals DQ0to DQn at the time of data outputting in accordance with an impedance setting code Ron <1, 0> supplied from the mode register22. When the command supplied to the control circuit21is a WT command, and when the memory cell array20is performing a write operation, the data input/output unit100supplies data “Data” input from outside via the data terminals DQ0to DQn to the memory cell array20.

The data input/output unit100is connected to the calibration terminal ZQ. The calibration terminal ZQ is connected to an impedance adjustment resistance (or external resistance RZQ) of a desired resistance value. The data input/output unit100adjusts the impedance of the data input/output unit100in accordance with the external resistance RZQ. Incidentally, impedance adjustment activation signals (control signals ACT1and ACT2) that are supplied from the control circuit21to the data input/output unit100are used to control the execution of an impedance adjustment operation of the data input/output unit100.

The following describes the data input/output unit100with reference toFIG. 2.

FIG. 2is a block diagram showing the configuration of the data input/output unit100. As shown inFIG. 2, the data input/output unit100includes a first output buffer110and a second output buffer120, which are connected to a data terminal DQ; an impedance adjustment unit130, which is connected to the calibration terminal ZQ; and an input buffer170, which is connected to the data terminal DQ. Incidentally, the input buffer170is activated at a time when data are input. However, the configuration of the input buffer170and the details of a data input operation are not related directly to the fundamentals of the present invention, and therefore will not be described. In the present specification, suppose that an output buffer101of the data input/output unit100is made up of the first output buffer110and the second output buffer120.

The first output buffer110, which makes up the output buffer101, includes four unit buffers111to114that are connected in parallel. The second output buffer120, which makes up the output buffer101, includes three unit buffers121to123that are connected in parallel. The unit buffers111to114and121to123are used to drive the data terminal DQ during a read operation, and are connected in parallel with respect to the data terminal DQ as shown inFIG. 2. The unit buffers111to114and121to123have the same circuit configuration; in one example, the impedances of all the unit buffers111to114and121to123are set to 240Ω (which is the value after adjustment) according to the present embodiment. The impedances can be adjusted by an impedance control signal DRZQ (code) generated by the impedance adjustment unit130during a calibration operation (described later).

Accordingly, for example, when all the unit buffers111to114and121to123are activated, the impedance (target value) of the output buffer101when seen from the data terminal DQ is about 34.3Ω (=240 Ω/7). Moreover, for example, when the four unit buffers111to114of the first output buffer and the two unit buffers121and122of the second output buffer become activated, without activating the unit buffer123of the second output buffer, the impedance (target value) of the output buffer101when seen from the data terminal DQ is 40Ω (=240Ω/6).

However, the resistance of a power supply line to which a plurality of the unit buffers are connected in common varies depending on the number of unit buffers activated. Accordingly, the impedances of a plurality of the unit buffer circuits activated each differ from a predetermined set value (240Ω in this case), which has been adjusted during a calibration operation, at the time of data outputting or at any other time. As a result, the impedance of the output buffer101deviates from the target value. For example, in the case of the above example, when all the unit buffers (seven in this case) are selectively activated, the voltage of the power supply line to which the unit buffers each are connected in common is more likely to drop than when one unit buffer is selectively activated. During a calibration operation, with the use of a replica buffer equivalent to one unit buffer, the impedances of a plurality of the unit buffers each are set to 240Ω. Therefore, when seven unit buffers are selectively activated, the impedances of the unit buffers become higher than the adjusted 240Ω; as a result, the impedance of the output buffer101is set to a higher value than about 34.3Ω, which is the target. In this manner, depending on the number of unit buffers selectively activated, the impedances could differ from a predetermined set value (240Ω in this case), which has been adjusted in advance, at the time of data outputting or at any other time. As a result, the impedance of the output buffer101deviates from the target value.

Accordingly, the impedance adjustment unit130generates an impedance control signal DRZQ on the basis of the number of unit buffers activated, and then supplies the impedance control signal DRZQ to the output buffer101, thereby bringing the impedance of the output buffer101closer to the target value.

The impedance adjustment unit130receives from the mode register22an impedance setting code Ron <1, 0> as the number of unit buffer circuits activated; generates an impedance control signal DRZQ (or an impedance adjustment signal) on the basis of the setting code; and supplies the impedance control signal DRZQ to a plurality of unit buffers (unit buffers111to114and121to123) via pre-stage circuits161to163, thereby adjusting the impedances of a plurality of the unit buffers.

The operation of the unit buffers111to114is controlled by operation signals161P and161N, which are supplied from the pre-stage circuit161. The operation of the unit buffers121and122is controlled by operation signals162P and162N, which are supplied from the pre-stage circuit162. The operation of the unit buffer123is controlled by operation signals163P and163N, which are supplied from the pre-stage circuit163.

The pre-stage circuits161to163specify output transistors from among a plurality of output transistors (described later) contained in the corresponding unit buffers111to114and121to123to turn on. An operation of turning the output transistors ON (conductive) or OFF (non-conductive) is controlled by operation signals161P to163P and operation signals161N to163N. As shown inFIG. 2, to the pre-stage circuits161to163, an impedance control signal DRZQ is supplied in common from the impedance adjustment unit130. Moreover, from an output control circuit150, selection signals151P to153P and selection signals151N to153N are individually supplied.

The output control circuit150specifies unit buffers from among a plurality of unit buffers111to11nto activate, and also specifies an output level for driving the DQ terminal. The unit buffers to be activated are specified in the following manner: the output control circuit150receives an impedance setting code Ron <1, 0> from the mode register22, and then outputs, on the basis of the setting code, the selection signals151P to153P and the selection signals151N to153N to the pre-stage circuits161to163. The output level of a unit buffer activated is determined based on data “Data” supplied from the memory cell array20in the case of a read operation.

Hereinafter, the circuit blocks that make up the data input/output unit100each will be described in detail.

FIG. 3is a circuit diagram of the unit buffer111. As shown inFIG. 3, the unit buffer111includes plural (five in this embodiment) P-channel MOS transistors211to215connected in parallel, plural (five in this embodiment) N-channel MOS transistors221to225connected in parallel, and resistors231and232that are connected in series between the transistors211to215and the transistors221to225. A contact point between the resistor231and the resistor232is connected to the data pin DQ. Of the unit buffer111, a part including the P-channel MOS transistors211to215and the resistor231constitutes a pull-up circuit PU. A part including the N-channel MOS transistors221to225and the resistor232constitutes a pull-down circuit PD.

Five operation signals161P1to161P5that constitute the operation signal161P are supplied respectively to the gates of the transistors211to215. Five operation signals161N1to161N5that constitute the operation signal161N are supplied respectively to the gates of the transistors221to225. Based on this arrangement, the ten transistors that are included in the unit buffer111can be individually on/off controlled based on the ten operation signals including the operation signals161P1to161P5and the operation signals161N1to161N5.

The parallel circuit including the transistors211to215, and the parallel circuit including the transistors221to225are designed to have resistance of 120Ω during the conduction time. However, the on resistance of the transistors varies depending on manufacturing conditions, and also varies depending on the ambient temperature and the power supply voltage during the operation. Therefore, desired impedance is not always obtained. In order to set 120Ω to the impedance, the number of transistors to be turned on needs to be adjusted. For this purpose, the parallel circuits including plural transistors are used. In order to adjust the impedance finely and in a wide range, it is preferable to mutually differentiate a W/L ratio (a gate width to gate length ratio) of the plural transistors that constitute the parallel circuit. Preferably, weight of the power of two is used. Considering this point, according to this embodiment, when the W/L ratio of the transistor211is “1”, the W/L ratios of the transistors212to215are set to “2”, “4”, “8”, and “16”, respectively (The values of the W/L ratios are relative values, and do not represent actual W/L ratios. This similarly applies to the following explanations).

By suitably selecting the transistors to be turned on based on the operation signals161P1to161P5and the operation signals161N1to161N5, the on resistance of the parallel circuit can be fixed to substantially 120Ω, regardless of the variation due to the manufacturing conditions and a temperature change.

The resistances of the resistors231and232are set to 120Ω, respectively. With this arrangement, when at least one of the parallel circuit including the transistors211to215and the parallel circuit including the transistors221to225is in the on state, the impedance of the unit buffer111from the viewpoint of the data pin DQ becomes 240Ω. A tungsten (W) resistor can be used for the resistors231and232.

Other unit buffers112to114that constitute the first output buffer110also have circuit structures that are the same as that of the unit buffer111shown inFIG. 3, and are controlled by the same operation signals161P1to161P5and the operation signals161N1to161N5. On the other hand, other unit buffers121to123that constitute the second output buffer120have the same circuit structures as that of the unit buffer111shown inFIG. 3. However, the operations of the unit buffers121and122are controlled by the operation signals162P and162N, and the operation of the unit buffer123is controlled based on the operation signals163P and163N. The operation signals162P,162,163P, and163N also have five operation signals, respectively, and are used to control the corresponding pull-up circuit UP or the pull-down circuit PD.

FIG. 4is a circuit diagram of the pre-stage circuit161. As shown inFIG. 4, the pre-stage circuit161includes five OR circuits411to415and five AND circuits421to425. An output control circuit150supplies a selection signal151P in common to the OR circuits411to415, and the impedance adjustment unit130supplies the impedance control signals DRZQP1to DRZQP5to the OR circuits411to415, respectively. On the other hand, the output control circuit150supplies the selection signal151N in common to the AND circuits421to425, and the impedance adjustment circuit130supplies the impedance control signals DRZQN1to DRZQN5to the AND circuits421to425, respectively.

The operation signals161P1to161P5that form the operation signal161P output from the OR circuits411to415, and the operation signals161N1to161N5that form the operation signal161N output from the AND circuits421to425, are supplied in common to the unit buffers111to114, as shown inFIG. 2, thereby controlling the corresponding transistors.

The other pre-stage circuits162and163also have circuit configurations similar to those of the pre-stage circuit161shown inFIG. 4. In this case, the selection signals152P and152N from the output control circuit150are supplied in common to the OR circuit and the AND circuit respectively that are included in the pre-stage circuit162. The selection signals153P and153N from the output control circuit150are supplied in common to the OR circuit and the AND circuit respectively that are included in the pre-stage circuit163.

FIG. 5is a circuit diagram of the impedance adjustment unit130. The impedance adjustment unit.130includes a load current selection circuit140, pull-up circuits131and132, pull-down circuit133. The impedance adjustment circuit also includes counter134for controlling the pull-up circuit134, counter135for controlling the pull-down circuit133, a comparator136for controlling the counter134and a comparator137for controlling the counter135.

FIG. 6is a circuit diagram of the load current selection circuit140and the pull-up circuit131. The load current selection circuit140includes a logic circuit140e, which is a three-input NAND circuit; a logic circuit140f, which is a three-input NAND circuit; and an AND circuit140g.

To the logic circuit140e, the following signals are input: a logically inverted signal of an impedance setting code Ron (0); a logically inverted signal of an impedance setting code Ron (1); and a control signal ACT1.

To the logic circuit140f, the following signals are input: an impedance setting code Ron (0); a logically inverted signal of an impedance setting code Ron (1); and a control signal ACT1.

The AND circuit140gcalculates a logical product of the output signal of the logic circuit140eand the conduction control signal RON10, and then outputs a conduction control signal RON00.

That is, when the impedance setting code Ron (0) is at a L-level, the impedance setting code Ron (1) at a L-level, and the control signal ACT1at a H-level, the load current selection circuit140changes the conduction control signal RON00from a H-level to a L-level, and keeps the conduction control signal RON10at a H-level.

When the impedance setting code Ron (0) is at a H-level, the impedance setting code Ron (1) at a L-level, and the control signal ACT1at a H-level, the load current selection circuit140changes the conduction control signal RON00from a H-level to a L-level, and changes the conduction control signal RON10from a H-level to a L-level.

The pull-up circuit131includes a replica circuit131eand a load current generation circuit131f.

As shown inFIG. 6, the replica circuit131e(replica circuit) has substantially the same circuit configuration as the pull-up circuits PU that the unit buffers111to114and121to123include. That is, the replica circuit131eincludes five PMOS transistors311to315, which are connected in parallel; and a resistor331, one end of which is connected to the drains of the PMOS transistors. The other end of the resistor331is connected to the calibration terminal ZQ.

The PMOS transistors311to315in the replica circuit131ecorrespond to the PMOS transistors211to215shown inFIG. 3. The PMOS transistors311to315each have the same impedance. Therefore, as in the case of the W/L ratios of the PMOS transistors211to215, the W/L ratios of the PMOS transistors311to315are set to “1,” “2,” “4,” “8,” and “16,” respectively.

The resistor331, too, corresponds to the resistor231shown inFIG. 3. Therefore, the resistance value thereof is set to 120Ω.

To the gates of the PMOS transistors311to315, impedance control signals DRZQP1to DRZQP5are respectively supplied from the counter134. As a result, the operation of the replica circuit131eis controlled. The impedance control signals DRZQP1to DRZQP5correspond to the operation signals161P1to161P5.

The load current generation circuit131fincludes two transistors and a resistor. The load current generation circuit131fincludes series circuits61to66, which are connected to a power supply line (VDD) of the replica circuit131e, a resistor67R, a resistor68R, and an operational amplifier69. The series circuits61to66each are formed by connecting a PMOS transistor (second transistor), a NMOS transistor (first transistor), and a resistor in series: the conduction control signal RON00or RON10is input into the gate of the PMOS transistor; an output signal of the operational amplifier69is input into the gate of the NMOS transistor.

For example, the series circuit61includes a PMOS transistor61P, a NMOS transistor61N, and a resistor61R. The source of the PMOS transistor61P is connected to the power supply line of the replica circuit131e. The gate of the PMOS transistor61P is connected to the load current selection circuit140, and the conduction control signal RON00is input to the gate. The drain of the PMOS transistor61P is connected to the drain of the NMOS transistor61N. The drain of the NMOS transistor61N is connected to the drain of the PMOS transistor61P. The gate of the NMOS transistor61N is connected to the output of the operational amplifier69. The source of the NMOS transistor61N is connected to one end (referred to as a connection point Nd61) of the resistor61R. One end of the resistor61R is connected to the connection point Nd61, and the other end grounded.

Similarly, the series circuits j (j=62 to 65) each include a PMOS transistor jP, a NMOS transistor jN, and a resistor jR. The source of the PMOS transistor jP is connected to the power supply line of the replica circuit131e. The gate of the PMOS transistor P is connected to the load current selection circuit140, and the conduction control signal RON00is input to the gate. The drain of the PMOS transistor jP is connected to the drain of the NMOS transistor jN. The drain of the NMOS transistor jN is connected to the drain of the PMOS transistor jP. The gate of the NMOS transistor jN is connected to the output of the operational amplifier69. The source of the NMOS transistor jN is connected to one end of the resistor jR. One end of the resistor jR is connected to the source of the NMOS transistor jN, and the other end grounded.

The series circuit66includes a PMOS transistor66P, a NMOS transistor66N, and a resistor66R. The source of the PMOS transistor66P is connected to the power supply line of the replica circuit131e. The gate of the PMOS transistor66P is connected to the load current selection circuit140, and the conduction control signal RON10is input to the gate. The drain of the PMOS transistor66P is connected to the drain of the NMOS transistor66N. The drain of the NMOS transistor66N is connected to the drain of the PMOS transistor66P. The gate of the NMOS transistor66N is connected to the output of the operational amplifier69. The source of the NMOS transistor66N is connected to one end of the resistor66R. One end of the resistor66R is connected to the source of the NMOS transistor66N, and the other end grounded.

The resistor67R (of resistance value R1) and the resistor68R (of resistance value R1) make up a voltage-dividing circuit. The voltage-dividing circuit outputs a reference voltage of (VDD/2) to an non-inverting input terminal (+) of the operational amplifier69.

Meanwhile, the inverting input terminal (−) of the operational amplifier69is connected to the connection point Nd61of the series circuit61. The operational amplifier69adjusts the voltage level of the output signal thereof in response to the voltage levels of the two input terminals and outputs the output signal to the gates of the NMOS transistors61N to66N of the series circuits61to66.

When the voltage level of the connection point Nd61is lower than the reference voltage (VDD/2), the operational amplifier69raises the voltage level of the output signal so that a current driving capability of each of the NMOS transistors61N to66N increases. When the voltage level of the connection point Nd61is higher than the reference voltage (VDD/2), the operational amplifier69lowers the voltage level of the output signal so that the current driving capability of each of the NMOS transistors61N to66N decreases.

In this manner, the resistance value R2of the resistor61R of the series circuit61is set to the same value as the external resistance RZQ. Therefore, the value of the current flowing through the resistor61R (indicated by i in the diagram) can be substantially equal to the value of the current that flows through the external resistance RZQ at a time when the voltage level of the calibration terminal ZQ is (VDD/2). During a calibration operation, to the replica circuit131e, impedance control signals DRZQP (DRZQP1to DRZQP5) are input; the impedance control signals DRZQP are adjusted in such a way that the voltage level of the calibration terminal ZQ comes to (VDD/2). In the resistor61R, the operational amplifier69operates to adjust the current driving capability of the NMOS transistor61N, thereby bringing the voltage level of one end of the resistor61R to (VDD/2). As a result, the value i of the current flowing through the resistor61R is substantially equal to the current value of the external resistance RZQ.

In that manner, in the series circuit61, the PMOS transistor61P is turned ON during the calibration operation. Therefore, the current whose current value i is substantially equal to that of the current flowing from the power supply line of the replica circuit131eto the ground via the external resistance RZQ connected to the calibration terminal ZQ flows through the series circuit61. In this manner, the voltage level of the power supply line of the replica circuit131eis decreased.

The resistance values of the resistors in the other series circuits are set to the same resistance value R2of the series circuit61.

That is, during the calibration operation, a L-level conduction control signal RON00is output from the load current selection circuit140to the load current generation circuit131f, thereby operating five series circuits61to65in total. Therefore, when the six unit buffers shown inFIG. 2, or the unit buffers111to114and121to122, are activated in total, it is possible to cause a drop in the voltage level of the power supply line of the replica circuit131ethat is akin in magnitude to a drop in the voltage level of the power supply line to which the above unit buffers are connected.

Moreover, the L-level conduction control signal RON00and the L-level conduction control signal RON10are output from the load current selection circuit140to the load current generation circuit131f, thereby operating six series circuits61to66in total. Therefore, when the seven unit buffers shown inFIG. 2, or the unit buffers111to114and121to122and123, are activated in total, it is possible to cause a drop in the voltage level of the power supply line of the replica circuit131ethat is substantially equal in voltage level to a drop in the voltage level of the power supply line to which the above unit buffers are connected.

In that manner, the load current generation circuit131fchanges, during the calibration operation, the current flowing therethrough depending on the number of unit buffers activated during the data outputting, thereby causing a voltage drop on the power supply line of the replica circuit131ethat is substantially equal in voltage level to a drop in the voltage level of the power supply line to which the activated unit buffers are connected. Therefore, the impedance control signals DRZQ, which are determined during the calibration operation, can be adjusted in such a way as to reflect the number of unit buffers activated.

Incidentally, when the unit buffers and a power supply line to which the unit buffers are connected are arranged substantially same layout configuration to the load current generation circuit131f, the replica circuit131e, and a power supply line to which the load current generation circuit131fand the replica circuit131eare connected, the resistance value R2may be set equal to the resistance value of the resistance RZQ as described above. However, when the layout configurations of both are different, the resistance value R2may be set to a different value than the resistance value of the resistance RZQ by running a circuit simulation in such a way as to reflect each layout configuration.

FIG. 7is a circuit diagram of the pull-up circuit132and the pull-down circuit133. As shown inFIG. 7A, the pull-up circuit132has a circuit structure substantially the same as that of the pull-up circuit PU inFIG. 3. The gates of five PMOS transistors in the pull-up circuit132is supplied with the impedance control signals DRZQP1to DRZQP5.

As shown inFIG. 7B, the pull-down circuit133has a circuit structure substantially the same as that of the pull-down circuit PD included in the unit buffers111to114and121to123, respectively. In other words, the pull-down circuit132includes five N-channel MOS transistors321to325that are connected in parallel, and a resistor332of which one end is connected to drains of these transistors. The transistors321to325included in the pull-down circuit133correspond to the transistors221to225shown inFIG. 3, and have the same impedance, respectively. The configuration of the pull-down circuit133is similar to that of the pull-up circuit131, in this respect. The resistor332also corresponds to the resistor232shown inFIG. 3. Therefore, resistance of the resistor332is also set to 120Ω.

The counter135supplies impedance control signals DRZQN1to DRZQN5to the gates of the transistors321to325, respectively, thereby controlling the pull-down circuit133. The impedance control signals DRZQN1to DRZQN5correspond to the operation signals161N1to161N5.

As explained above, the replica circuit131eof the pull-up circuit131and the pull-up circuit132have substantially the same circuit structures as that of the pull-up circuit PU included in the unit buffers111to114and121to123, respectively. The pull-down circuit133has substantially the same circuit structure as that of the pull-down circuit PD included in the unit buffers111to114and121to123, respectively. The impedances of these replica circuits131e,132, the pull-down circuit133are adjusted in accordance with the number of activated unit buffers during the calibration process.

Returning toFIG. 5, a non-inverted input terminal (+) of the comparator137is connected to a contact node A at which the pull-up circuit132and the pull-down circuit133are connected to each other.

The counter134counts up or counts down when a control signal ACT1is activated. When a comparison signal COMP1that is output from the comparator136is at a high level, the counter134continues counting up, and when the signal COMP1is at a low level, the counter134continues counting down. A noninverted input terminal (+) of the comparator136is connected to the calibration pin ZQ, and a noninverted input terminal (−) is connected to an intermediate point between the resistors138and139that is connected to a power supply potential (VDD) and a ground potential (GND). Based on this structure, the comparator136compares the potential of the calibration pin ZQ with the intermediate voltage (VDD/2). When the former potential is higher, the output comparison signal COMP1is set to a high level. When the latter potential is higher, the comparison signal COMP1is set to a low level.

On the other hand, the counter135counts up or counts down when a control signal ACT2is activated. When a comparison signal COMP2that is output from the comparator137is at a high level, the counter135continues counting up, and when the signal COMP2is at a low level, the counter135continues counting down. A non-inverted input terminal (+) of the comparator137is connected to a contact node A as the output end of the replica buffer, and a non-inverted input terminal (−) is connected to an intermediate point between the resistors138and139. Based on this structure, the comparator137compares the output potential of the replica buffer with the intermediate voltage (VDD/2). When the former potential is higher, the output comparison signal COMP2is set to a high level. When the latter potential is higher, the comparison signal COMP2is set to a low level.

When the control signals ACT1and ACT2are inactivated, the counters134and135stop the count operation, and hold the current count value. As described above, the count value of the counter134is used for the impedance control signal DRZQP, and the count value of the counter135is used for the impedance control signal DRZQN. The collective impedance control signal DRZQ, which is adjusted based on the number of activated unit buffers by the load current generation circuit131fin the calibration process, is supplied in common to the pre-stage circuits161to163shown inFIGS. 2 and 4.

The described above is the configuration of the data input/output unit100of the present embodiment. The operation of the data input/output unit100will be described especially in calibration and data output operations in series with reference to theFIGS. 8 and 9.

FIG. 8is a flowchart for explaining the calibration operation.FIG. 9is a graph showing a change of potential at the calibration pin ZQ, contact node A during the calibration operation;

The calibration operation is for adjusting the impedance of the output buffers101, as described above. The calibration operation is carried out to correct variations of the impedance due to process conditions at the manufacturing time, and to correct changes of the impedance due to changes in the ambient temperature and variations in the power supply voltage. Therefore, when high precision is required, it is preferable to periodically execute the calibration operation during the actual operation, instead of carrying out the calibration operation only once at the power up time or the initialization time such as the resetting time. The output circuit100according to this embodiment is particularly effective when the calibration operation is periodically executed during the actual operation as explained above. The calibration operation is explained in detail below.

In executing the calibration operation, first, the external resistor RZQ needs to be connected to the calibration pin ZQ (seeFIG. 2andFIG. 5). The external resistor RZQ needs to have impedance that is the same as the impedance (i.e., the impedance of a replica buffer) required for the unit buffers111to114and121to123. Therefore, in this embodiment, the external resistor RZQ having 240Ω is used.

Moreover, suppose that, before a calibration command (CAL command) is supplied to the semiconductor device10as a command signal CMD to instruct the semiconductor device10to perform a calibration operation, a mode register command (MRS command) is supplied to the semiconductor device10as a command signal CMD. Furthermore, suppose that, to the semiconductor device10, together with the MRS command, a mode setting code (or a DS setting code=[0,1] including a code [A5, A1]) is supplied as an address signal ADD through the address terminals13; and that the mode register22keeps the impedance setting code Ron <0> at a H-level in the impedance setting code Ron <1, 0> while changing the impedance setting code Ron <1> from a H-level to a L-level, and outputs each code to the data input/output unit100.

First, when the calibration operation is instructed by a CAL command (step S11: YES), the control signal ACT1is activated, and the counter134included in the impedance adjustment unit130starts a count operation (step S12). In the initialization state before the control signal ACT1is activated, the count value of the counter134is all reset to 1 (“5′b11111” in this example). Therefore, the inductance control signals DRZQP1to DRZQP5are all at the high level. Consequently, the transistors311to315that are included in the replica circuit131ein the pull-up circuit131are all in the off state. As a result, the comparison signal COMP1that is the output of the comparator136is at the low level.

Therefore, the counter134continues counting down. The on/off state of the transistors311to315is switched over linked to the count-down.

Specifically, because the W/L ratios of the transistors311to315are set to “1”, “2”, “4”, “8”, and “16”, respectively, the least significant bit (LSB) of the counter134is allocated to the impedance control signal DRZQP1, and the most significant bit (MSB) of the counter134is allocated to the impedance control signal DRZQP5. With this arrangement, the impedance of the pull-up circuit131can be changed at a minimum pitch.

The load current selection circuit140brings both the conduction control signals RON00and RON10to a L-level in accordance with the impedance setting code Ron <1, 0>. As a result, all the series circuits61to66of the load current generation circuit131foperate, thereby decreasing the voltage level of the power supply line that supplies power to the replica circuit131ein accordance with the number of unit buffers activated (seven in this case) along with the replica circuit131e.

When the count-down continues, the impedance of the replica circuit131egradually decreases, and the potential of the calibration pin ZQ gradually increases. When the impedance of the replica circuit131edecreases to less than the target impedance 240Ω, the potential of the calibration pin ZQ exceeds the intermediate voltage (VDD/2). Therefore, the comparison signal COMP1that is output from the comparator136is inverted to a high level. In response to this, the counter134continues counting up, thereby increasing the impedance of the pull-up circuit131ethis time.

By repeating this operation, the potential of the calibration pin ZQ is stabilized near the intermediate voltage (VDD/2). Thereafter, the control signal ACT1is inactivated, thereby stopping the count operation of the counter134(step S13). The load current selection circuit140high-activates connection control signals RON00and RON10, PMOS transistor (second transistor) is set to off in any of DC circuits61to66in the load current generation circuit131fand the load current generation circuit131fis electrically cut off from the lines of the replica circuit131e. As a result, the count value of the counter134is fixed, and the levels of the impedance control signals DRZQP1to DRZQP5are firmed.

Based on the above operation, the impedances of the replica circuit131eand pull-up circuit132are adjusted in accordance with the number of activated unit buffers. In this case, the initial value of the counter134can be a set value of 240Ω, instead of all one, and this value can be adjusted by counting up or counting down according to the level of the comparison signal COMP1.

The control signal ACT2is then activated, thereby starting the count operation of the counter135included in the impedance adjustment unit130(step S14). In the initial state before the control signal ACT1is activated, the count value of the counter135is reset to all zero (“5′b00000” in this example), as an example. Therefore, the impedance control signals DRZQP1to DRZQP5that are output from the counter135are all at the low level. Consequently, the transistors321to325included in the pull-down circuit133are all in the off state. As a result, the comparison signal COMP2that is output from the comparator137becomes at a high level.

In response to this, the counter135continues the count up. The on/off state of the transistors321to325is switched over linked to this count up. In this case, the W/L ratios of the transistors321to325are set to “1”, “2”, “4”, “8”, and “16”, respectively. Corresponding to these W/L ratios, the least significant bit (LSB) of the counter135is allocated to the impedance control signal DRZQN1, and the most significant bit (MSB) of the counter135is allocated to the impedance control signal DRZQN5. With this arrangement, the impedance of the pull-down circuit133can be changed at a minimum pitch.

When the count up continues, the impedance of the pull-down circuit133gradually decreases, and as shown inFIG. 9B, the potential of the node A gradually decreases. When the impedance of the pull-down circuit133decreases to less than the target impedance 240Ω, the potential of the node A becomes lower than the intermediate voltage (VDD/2). Therefore, the comparison signal COMP2that is output from the comparator137is inverted to a low level. In response to this, the counter135continues the count-down, thereby increasing the impedance of the pull-down circuit133this time.

By repeating this operation, the potential of the contact node A is stabilized near the intermediate voltage (VDD/2). Thereafter, the control signal ACT2is inactivated, thereby stopping the count operation of the counter135(step S15). As a result, the count value of the counter135is fixed, and the levels of the impedance control signals DRZQN1to DRZQN5are firmed.

Based on the above operation, the impedance of the pull-down circuit133is also adjusted in accordance with the number of unit buffers same as the replica circuit131eand pull-up circuit132. In this case, the initial value of the counter135can be a set value of 240Ω, instead of all zero, and this value can be adjusted by counting up or counting down according to the level of the comparison signal COMP2.

The process returns to step S11, and the instruction for the calibration operation based on a CAL command is awaited. When the calibration operation is instructed (step S11: YES), the above series of operation is carried out again.

The above is the calibration operation. The impedance control signal DRZQ that is firmed by the calibration operation is supplied in common to the pre-stage circuits161to163shown inFIGS. 2 and 4. Therefore, the unit buffers111to114and121to123that are controlled by the pre-stage circuits161to163can also operate accurately in the impedance which is adjusted in accordance with the number of activated unit buffers. In other words, the plurality of unit buffers can be collectively calibrated.

When a DS setting code [00], along with the MRS command, is supplied to the semiconductor device10before a CAL command is supplied to instruct the semiconductor device10to perform a calibration operation, the mode register22changes the impedance setting code Ron<0> from a H-level to a Low-level, and the impedance setting code Ron<1> from a H-level to a Low-level, and outputs each of the codes to the data input/output unit100. In this case, during a period of time when the control signal ACT1is at an activity level, the load current selection circuit140changes the conduction control signal RON00to a L-level and the conduction control signal RON10to a H-level in accordance with the impedance setting code Ron<1, 0>. As a result, the series circuits61to65of the load current generation circuit131foperate. Together with the replica circuit131e, the load current generation circuit131fdecreases the voltage level of the power supply line that supplies power to the replica circuit131ein accordance with the number of unit buffers activated (six in this case). Therefore, the unit buffers111to114and121to122, which are controlled by the pre-stage circuits161to163, are able to operate after the impedances of the unit buffers111to114and121to122are adjusted in accordance with the number of unit buffers activated (six in this case).

The following describes a data output operation.

After a read command is supplied from a memory controller, the output control circuit150activates one or ones of the unit buffers111to114and121to123of the output buffer101. The number of activated unit buffers is designated by a DS setting code supplied from the mode register22. The activated unit buffers, or the one or ones of the unit buffers, drive a corresponding data terminal DQ to a logic level corresponding to “Data” supplied from the memory cell array20. In this case, one of the pull-up circuit PU and pull-down circuit PD of each of the activated unit buffers drives the corresponding data terminal with the impedance based on an impedance control signal DRZQ supplied from the impedance adjustment unit130.

Incidentally, the data output operation needs to be performed after the above-described calibration operation is carried out at least once, thereby ensuring that the operation is carried out with the correct impedance.

As described above, the semiconductor device10includes an output circuit (output buffer101), which includes a plurality of unit buffer circuits whose impedances each are adjustable; a control circuit (output control circuit150), which selectively activates one or ones of the unit buffer circuits; and an impedance adjustment unit (impedance adjustment unit130), which is an impedance adjustment unit that adjusts the impedances of the plurality of unit buffer circuits, and which includes a replica circuit (replica circuit131e) that has the replica impedance that is substantially equal to impedance of each of the unit buffer circuits, and a load current generation circuit (load current generation circuit131f) that is connected in parallel to the replica circuit and changes the quantity of current flowing therethrough in accordance with the number of unit buffer circuits selectively activated by the control circuit.

Therefore, the impedance of the replica circuit131eis adjusted according to the number of unit buffer circuits selectively activated. The impedance adjustment result of the replica circuit is reflected in the process of adjusting the impedances of unit buffer circuits that make up the output buffer101(output circuit). As a result, the number of the unit buffer circuits is reflected in the process of adjusting the impedance of the output circuit. Therefore, it is possible to improve the accuracy of adjusting the impedance of the output circuit.

Hereinafter, as for suppression of the impedance deviation ΔRon (Ron deviation) of the output buffer101that is attributable to the number of unit buffer circuits activated, the advantageous effects achieved by the present invention will be described based on experimental results.

FIGS. 10 and 11are diagrams illustrating the impedance deviation ΔRon relative to the number of unit buffer circuits.

In the cases ofFIG. 10AandFIG. 11, the present invention is not applied;FIG. 10AandFIG. 11show the impedance deviation ΔRon at a time when one, two, four, or seven unit buffers in the output buffer101are activated. In the case ofFIG. 10B, the present invention is applied;FIG. 10Bshows the impedance deviation ΔRon at a time when one or seven unit buffers in the output buffer101are activated.

Incidentally, inFIGS. 10A,10B,11A,11B and11C, the relationship between the impedance control signals DRZQ (ZQ adjustment codes) and the impedance deviation ΔRon of the replica circuit131ethat is adjusted by the ZQ adjustment codes is plotted by symbol “square shape”.

InFIGS. 10A,10B,11A,11B and11C, the impedance deviation ΔRon of the output buffer101(which corresponds to the DQ circuit (RZQ/1) in the diagrams) at a time when one unit buffer is activated is plotted by symbol “(black) triangle shape”; the impedance deviation ΔRon of the output buffer101(which corresponds to the DQ circuit (RZQ/7) or the like in the diagrams) at a time when a plurality of unit buffers are activated is plotted by symbol “rhombus shape”.

According to the present embodiment, the impedance deviation ΔRon of the replica circuit131erepresents the following in percentage: (the impedance value of the replica circuit131e−240Ω)/240Ω. The impedance deviation ΔRon of the output buffer101represents the following in percentage: (the impedance of the output buffer101−240Ω/the number of unit buffers activated)/(240Ω/the number of unit buffers activated). Incidentally, “(240Ω/the number of unit buffers activated)” turns out to be a target impedance of the output buffer101after a calibration operation, i.e. after the impedance is adjusted by a ZQ adjustment code.

According to the present embodiment, the impedance of the replica circuit131eis adjusted to 240Ω. Therefore, as shown inFIGS. 10A,10B,11A,11B and11C, when the ZQ adjustment code=15 (=“5′b01111”=“0Fh”), the impedance deviation ΔRon of the replica circuit131eis substantially 0%. Incidentally, the impedance of the replica circuit131edecreases as the value of the ZQ adjustment code becomes larger; the impedance deviation ΔRon grows toward the (−) side as a result. The impedance of the replica circuit131eincreases as the value of the ZQ adjustment code becomes smaller; the impedance deviation ΔRon grows toward the (+) side as a result.

As shown inFIGS. 10A and 10B, when one unit buffer in the output buffer101becomes activated, the impedance deviation ΔRon of the output buffer101is substantially equal to the impedance deviation ΔRon of the replica circuit131e. The reason is as follows: During the calibration operation, one unit buffer is activated in the output buffer101, and a voltage drop that occurs on the power supply line of the output buffer101is therefore substantially equal to a voltage drop that occurs on the power supply line of the replica circuit131e.

However, when the present invention is not applied, as shown inFIG. 10A, the impedance deviation ΔRon of the output buffer101at a time when seven unit buffers in the output buffer101become activated differs significantly from the impedance deviation ΔRon of the replica circuit131e: For example, when the ZQ adjustment code=15, the impedance deviates toward the (+) side by about 10%. The reason is as follows: During the calibration operation, seven unit buffer are activated in the output buffer101, and a voltage drop that occurs on the power supply line of the output buffer101is therefore larger than a voltage drop that occurs on the power supply line of the replica circuit131e.

As the present invention is applied, as shown inFIG. 10B, there is a great improvement in the impedance deviation ΔRon of the output buffer101at a time when seven unit buffers in the output buffer101become activated, compared with the case where the present invention is not applied: For example, when the ZQ adjustment code=15, there is an improvement to such a degree that the impedance deviates toward the (+) side by about 4%. The reason is as follows: During the calibration operation, the load current generation circuit131fcauses a voltage drop on the power supply line of the replica circuit131ein accordance with the number of unit buffers activated in the output buffer101, and a voltage drop that occurs on the power supply line of the output buffer101is therefore substantially equal to a voltage drop that occurs on the power supply line of the replica circuit131e.

That is, according to the present invention, the number of unit buffer circuits activated is reflected in the process of adjusting the impedance of the output circuit, thereby improving the accuracy of adjusting the impedance of the output circuit.

Incidentally, as shown inFIGS. 11A to 11C, as the number of unit buffers activated in the output buffer101increases, the percentage of the impedance deviation ΔRon of the output buffer101becomes larger. For example, the following takes a look at the percentage of the impedance deviation ΔRon of the output buffer101when the external resistance RZQ=240Ω, and when the product specifications (Spec) are ±10%.

The 10% deviation from Spec at RZQ/1 means 240Ω×10%=24Ω. The 10% deviation from Spec at RZQ/2 means 240Ω×(1/2)×10%=12Ω. The 10% deviation from Spec at RZQ/4 means 240Ω×(1/4)×10%=6Ω. The 10% deviation from Spec at RZQ/7 means 240Ω×(1/7)×10%=3.4Ω.

That is, when the amount of deviation is similarly about 3Ω, there is not much impact in the case of RZQ/1 because the percentage of the deviation is as follows: (3/24)×10%=1.3%. However, in the case of RZQ/7, there is a great impact because the percentage of the deviation is as follows: (3/3,4)×10%=8.8%.

According to the present embodiment, what is described as an example is the process of adjusting the impedance of the replica circuit131e, aimed at the situation (RZQ/6, RZQ/7) where the number of unit buffers is increased, or the situation where the percentage of the impedance deviation ΔRon of the output buffer101is large.

As described above, even if Code (impedance control signal DRZQ) that has been adjusted for a large number of unit buffers is used in the situation (RZQ/2, RZQ/4) where the number of unit buffers is small, the percentage of the impedance deviation ΔRon of the output buffer101is small as described above in the situation where the number of DC buffers is small, thereby having almost no impact. Therefore, according to the present invention, while keeping the percentage of the impedance deviation ΔRon of the output buffer101substantially at a conventional level in the situation where the number of unit buffers activated in the output buffer101is small, it is possible to make an improvement in the percentage of the impedance deviation ΔRon of the output buffer101in the situation where the number of unit buffers activated in the output buffer101is large, i.e. the situation where the percentage of the impedance deviation ΔRon of the output buffer101is remarkable.

The load current generation circuit131fin the pull-up circuit131is not limited to the above-described circuit configuration, and may have the circuit configuration described below, for example.

FIG. 12is a diagram corresponding toFIG. 6, showing the circuit configuration of a load current selection circuit140aand a pull-up circuit131a. Incidentally, inFIG. 12, the same components as those in the load current selection circuit140and pull-up circuit131shown inFIG. 6are represented by the same reference symbols, and will not be described again.

The load current selection circuit140ais so formed as to include a logic circuit140h, which is a three-input NAND circuit; and a logic circuit140f, which is a three-input NAND circuit.

To the logic circuit140h, the following signals are input: a logically inverted signal of an impedance setting code Ron (0); a logically inverted signal of an impedance setting code Ron (1); and a control signal ACT1.

The logic circuit140fhas the same configuration as that of the load current selection circuit140. To the logic circuit140f, the following signals are input: an impedance setting code Ron (0); a logically inverted signal of an impedance setting code Ron (1); and a control signal ACT1.

That is, as in the case of the load current selection circuit140, when the impedance setting code Ron (0) is at a L-level, the impedance setting code Ron (1) at a L-level, and the control signal ACT1at a H-level, the load current selection circuit140achanges the conduction control signal RON00from a H-level to a L-level, and keeps the conduction control signal RON10at a H-level.

When the impedance setting code Ron (0) is at a H-level, the impedance setting code Ron (1) at a L-level, and the control signal ACT1at a H-level, the load current selection circuit140akeeps the conduction control signal RON00at a H-level, and changes the conduction control signal RON10from a H-level to a L-level.

The pull-up circuit131aincludes a replica circuit131eand a load current generation circuit131g. The replica circuit131eis identical to the replica circuit131eof the pull-up circuit131, and therefore will not be described.

The load current generation circuit131gis different from the load current generation circuit131fof the pull-up circuit131: the series circuits each include a voltage-dividing circuit and an operational amplifier.

That is, each portion of the load current generation circuit131gincludes a voltage-dividing circuit and a comparator. The load current generation circuit131gincludes a ×5 load current generation circuit71(load current generation unit), which allows current five times as large as the current flowing through the replica circuit131eto flow through the ×5 load current generation circuit71during calibration depending on the number of unit buffers activated; and a ×6 load current generation circuit72(load current generation unit), which allows current six times as large as the current to flow through the ×6 load current generation circuit72.

The ×5 load current generation circuit71includes a series circuit71a, which is connected to the power supply line (VDD) of the replica circuit131e, a resistor71Ru, a resistor71Rd, and an operational amplifier71c. The ×6 load current generation circuit72includes a series circuit72a, which is connected to the power supply line of the replica circuit131e, a resistor72Ru, a resistor72Rd, and an operational amplifier71c.

In the ×5 load current generation circuit71, the series circuit71aincludes a PMOS transistor71P, a NMOS transistor71N, and a resistor71R. The source of the PMOS transistor71P is connected to the power supply line of the replica circuit131e. The gate of the PMOS transistor71P is connected to the load current selection circuit140a, and a conduction control signal RON00is input into the gate. The drain of the PMOS transistor71P is connected to the drain of the NMOS transistor71N. The drain of the NMOS transistor71N is connected to the drain of the PMOS transistor71P. The gate of the NMOS transistor71N is connected to the output of the operational amplifier71c. The source of the NMOS transistor71N is connected to one end (referred to as a connection point Nd71) of the resistor71R. One end of the resistor71R (of resistance value R3) is connected to the connection point Nd71, and the other end grounded.

In the ×5 load current generation circuit71, the resistor71Ru (of resistance value R1) and the resistor71Rd (of resistance value R2) make up a voltage-dividing circuit. The voltage-dividing circuit divides the voltage level of the power supply line of the replica circuit131e, and outputs the resulting voltage level (V1) to an non-inverting input terminal (+) of the operational amplifier71c.

Meanwhile, the inverting input terminal (−) is connected to the connection point Nd71of the series circuit71a. The operational amplifier71cadjusts the voltage level of the output signal thereof in response to the voltage levels of the two input terminals, and outputs the output signal to the gate of the NMOS transistor71N of the series circuit71a.

When the voltage level of the connection point Nd71is lower than the voltage level (V1), the operational amplifier71craises the voltage level of the output signal so that a current driving capability of the NMOS transistor71N increases. When the voltage level of the connection point Nd71is higher than the voltage level (V1), the operational amplifier71clowers the voltage level of the output signal so that the current driving capability of the NMOS transistor71N decreases.

In this manner, the resistance value of the resistor71R of the series circuit71ais set to the resistance value R3. Therefore, the value of the current flowing through the resistor71R (indicated by i6in the diagram) becomes five times as large as the value of the current flowing through the external resistance RZQ at a time when the voltage level of the calibration terminal ZQ is (VDD/2). During the calibration operation, the impedance control signals DRZQ are input into the replica circuit131e; the impedance control signals DRZQ are adjusted in such a way that the voltage level of the calibration terminal ZQ comes to (VDD/2). Meanwhile, as for the resistor71R, the operational amplifier71cadjusts the current driving capability of the NMOS transistor71N so that the voltage level of one end of the resistor71R comes to (V1). In this case, as the resistance value R3is set to V1/((VDD/2)/240Ω×5), the value i6of the current flowing through the resistor71R becomes substantially five times as large as the value of the current of the external resistance RZQ.

That is, during the calibration operation, as the L-level conduction control signal RON00is input and as the PMOS transistor71P is turned ON, the ×5 load current generation circuit71equipped with the series circuit71aallows the current whose current value i6is substantially five times as large as the current flowing from the power supply line of the replica circuit131einto the ground via the external resistance RZQ connected to the calibration terminal ZQ to flow through the ×5 load current generation circuit71. As a result, the voltage level of the power supply line of the replica circuit131edrops.

Similarly to the ×5 load current generation circuit71, in the ×6 load current generation circuit72, the series circuit72aincludes a PMOS transistor72P, a NMOS transistor72N, and a resistor72R. The source of the PMOS transistor72P is connected to the power supply line of the replica circuit131e. The gate of the PMOS transistor72P is connected to the load current selection circuit140a, and a conduction control signal RON10is input into the gate. The drain of the PMOS transistor72P is connected to the drain of the NMOS transistor72N. The drain of the NMOS transistor72N is connected to the drain of the PMOS transistor72P. The gate of the NMOS transistor72N is connected to the output of the operational amplifier72c. The source of the NMOS transistor72N is connected to one end (referred to as a connection point Nd72) of the resistor72R. One end of the resistor72R (of resistance value R4) is connected to the connection point Nd72, and the other end grounded.

In the ×6 load current generation circuit72, the resistor72Ru (of resistance value R1) and the resistor72Rd (of resistance value R2) make up a voltage-dividing circuit. The voltage-dividing circuit divides the voltage level of the power supply line of the replica circuit131e, and outputs the resulting voltage level (V1) to an non-inverting input terminal (+) of the operational amplifier72c.

Meanwhile, the inverting input terminal (−) is connected to the connection point Nd72of the series circuit72a. The operational amplifier72cadjusts the voltage level of the output signal thereof in response to the voltage levels of the two input terminals, and outputs the output signal to the gate of the NMOS transistor72N of the series circuit72a.

When the voltage level of the connection point Nd72is lower than the voltage level (V1), the operational amplifier72craises the voltage level of the output signal so that a current driving capability of the NMOS transistor72N increases. When the voltage level of the connection point Nd72is higher than the voltage level (V1), the operational amplifier72clowers the voltage level of the output signal so that the current driving capability of the NMOS transistor72N decreases.

In this manner, the resistance value of the resistor72R of the series circuit72ais set to the resistance value R4. Therefore, the value of the current flowing through the resistor72R (indicated by i7in the diagram) becomes six times as large as the value of the current flowing through the external resistance RZQ at a time when the voltage level of the calibration terminal ZQ is (VDD/2). During the calibration operation, the impedance control signals DRZQ are input into the replica circuit131e; the impedance control signals DRZQ are adjusted in such way that the voltage level of the calibration terminal ZQ comes to (VDD/2). Meanwhile, as for the resistor72R, the operational amplifier72coperates to adjust the current driving capability of the NMOS transistor72N so that the voltage level of one end of the resistor72R comes to (V1). In this case, as the resistance value. R4is set to V1/((VDD/2)/240Ω×6), the value i7of the current flowing through the resistor72R becomes substantially six times as large as the value of the current of the external resistance RZQ.

That is, during the calibration operation, as the L-level conduction control signal RON10is input and as the PMOS transistor72P is turned ON, the ×6 load current generation circuit72equipped with the series circuit72aallows the current whose current value i7is substantially six times as large as the current flowing from the power supply line of the replica circuit131einto the ground via the external resistance RZQ connected to the calibration terminal ZQ to flow through the ×6 load current generation circuit72. As a result, the voltage level of the power supply line of the replica circuit131edrops.

In that manner, the load current generation circuit131gchanges the current flowing through the load current generation circuit131gdepending on the number of unit buffers activated during the calibration operation, thereby causing a voltage drop on the power supply line of the replica circuit131ethat is equal in magnitude to a drop in the voltage level of the power supply line to which the activated unit buffers are connected. Therefore, the impedance control signals DRZQ, which are determined during the calibration operation, can be adjusted in such a way as to reflect the number of unit buffers activated.

Incidentally, the resistance values R1to R4can be set by running a circuit simulation in such a way as to reflect a unit buffer, the layout configuration of a power supply line to which a unit buffer is connected, the load current generation circuit131g, and the layout configuration of a power supply line to which the replica circuit131eis connected.

The above embodiment has been described by focusing on the impedance of the output buffer101at data outputting. However, selectively activating unit buffers is also performed during a terminating resistance (ODT) operation. Therefore, the present invention is not limited to the data output operation, and may be applied to the terminating resistance operation, for example. The following provides a brief description of a semiconductor device10athat carries out the data output operation and the ODT operation.

FIG. 13is a block configuration diagram of the semiconductor device10a, corresponding toFIG. 1that shows the circuit configuration of the semiconductor device10. InFIG. 13, the same units as those inFIG. 1are represented by the same reference symbols, and will not be described.

The semiconductor device10ahas an ODT function, as well as a DS function. The ODT (On-Die Termination) function prevents the reflection of signals by causing an output buffer to function as a terminating resistance at a time when another semiconductor device is transferring data on an external bus to which a data terminal DQ (second terminal) is connected. The semiconductor device10aenables the ODT function by changing the number of unit buffers activated in accordance with an impedance setting code: the unit buffers make up the output buffer.

In that manner, as opposed to the semiconductor device10, the semiconductor device10afurther includes an On-Die Termination terminal12bas an external terminal (or a pad on a semiconductor chip). The On-Die Termination terminal12bis a terminal to which an On-Die Termination signal ODT is supplied. The On-Die Termination terminal12bis connected to a control circuit21a.

The control circuit21acontrols the activity and non-activity levels of an internal On-Die Termination control signal IODT in accordance with the On-Die Termination signal ODT supplied from outside via the On-Die Termination terminal12b. Furthermore, when a command indicating the execution of a calibration operation (CAL command) is supplied as a command signal CMD from outside via the command terminals12a, the control circuit21abrings (or activates) the control signals ACT1and ACT2to a H-level twice, and supplies the control signals ACT1and ACT2to the data input/output unit100. The reason is because an impedance adjustment unit130bof the data input/output unit100carries out a calibration operation of an output buffer corresponding to a data output operation, and a calibration operation of an output buffer corresponding to an ODT operation.

A mode register22asupplies the following codes to the data input/output unit100a: an impedance setting code Ron <1, 0> (first setting signal) and an impedance setting code Rtt <1, 0> (second setting signal), which are signals required to set the impedance of an output circuit of a data input/output unit100a. The impedance setting code Rtt <1, 0> is used at the time of ODT in the data input/output unit100a. That is, the impedance setting code Rtt <1, 0> is a signal specifying the number of unit buffers to be activated at the time of ODT.

Incidentally, according to the present embodiment, for example, the logic level of an address signal A2that is among the address signals ADD and is different from an address signal used for the impedance setting code Ron <1, 0> corresponds to and is equal to the logic level of an impedance setting code Rtt <0> in the impedance setting code Rtt <1, 0>; the logic level of an address signal A6corresponds to and is equal to the logic level of an impedance setting code Rtt <1>. That is, the mode register22aoutputs a H-level or L-level impedance setting code Rtt <0> in response to a H-level or L-level of the address signal A2to the data input/output unit100a, and a H-level or L-level impedance setting code Rtt <1> in response to a H-level or L-level of the address signal A6to the data input/output unit100a.

The following describes the data input/output unit100awith reference toFIG. 14.

FIG. 14is a block diagram showing the configuration of the data input/output unit100a, corresponding toFIG. 2that shows the configuration of the data input/output unit100. InFIG. 14, the same units as those inFIG. 2are represented by the same reference symbols, and will not be described.

An impedance adjustment unit130breceives from the mode register22aan impedance setting code Ron <1, 0> and an impedance setting code Rtt <1, 0> as the number of unit buffer circuits activated; and generates an impedance control signal DRZQ1and an impedance control signal DRZQ2(or an impedance adjustment signal) on the basis of the setting codes. Depending on the logic level of the internal On-Die Termination control signal IODT, the impedance adjustment unit130bsupplies one of the control signals to a plurality of unit buffers (unit buffers111to114and121to123) via the pre-stage circuits161to163as an impedance control signal DRZQ, thereby adjusting the impedances of a plurality of the unit buffers.

An output control circuit150aspecifies unit buffers from among a plurality of unit buffers111to11nto activate, and also specifies an output level for driving a DQ terminal. The unit buffers to be activated are specified in the following manner: the output control circuit150areceives an impedance setting code Ron <1, 0> and an impedance setting code Rtt <1, 0> from the mode register22a, and then outputs, on the basis of the setting codes, the selection signals151P to153P and the selection signals151N to153N to the pre-stage circuits161to163.

FIG. 15is a block diagram showing the configuration of the impedance adjustment unit130b, corresponding toFIG. 5that shows the configuration of the impedance adjustment unit130. InFIG. 15, the same units as those inFIG. 5are represented by the same reference symbols, and will not be described.

The impedance adjustment unit130bincludes a load current selection circuit140b, a pull-up circuit131a, a pull-up circuit132, and a pull-down circuit133. Moreover, the impedance adjustment unit130bincludes a counter134, which controls the pull-up circuit132; a counter135, which controls the pull-down circuit133; a comparator136, which controls the counter134; and a comparator137, which controls the counter135.

Furthermore, the impedance adjustment unit130bincludes a latch and selection circuit140pthat latches an impedance control signal DRZQ1and an impedance control signal DRZQ2, which are generated during a calibration operation, and outputs the impedance control signal DRZQ1or DRZQ2to the pre-stage circuits161to163depending on the internal On-Die Termination control signal IODT.

FIG. 16is a circuit diagram of a load current selection circuit140band a pull-up circuit131a, corresponding toFIG. 12that shows the circuit configuration of the load current selection circuit140aand the pull-up circuit131a. InFIG. 16, the same units as those inFIG. 12are represented by the same reference symbols, and will not be described.

The load current selection circuit140bis so formed as to include a logic circuit140h, which is a three-input NAND circuit; a logic circuit140f, which is a three-input NAND circuit; a logic circuit140i, which is a three-input NAND circuit; a logic circuit140j, which is a three-input NAND circuit; an AND circuit140k; and an AND circuit140m.

To the logic circuit140h, the following signals are input: a logically inverted signal of an impedance setting code Ron (0); a logically inverted signal of an impedance setting code Ron (1); and a control signal ACT1a. When all three signals input are at a H-level, the logic circuit140houtputs a L-level conduction control signal RON00a. When at least one of the three signals input is at a L-level, the logic circuit140houtputs a H-level conduction control signal RON00a.

To the logic circuit140f, the following signals are input: an impedance setting code Ron (0); a logically inverted signal of an impedance setting code Ron (1); and a control signal ACT1a. When all three signals input are at a H-level, the logic circuit140foutputs a L-level conduction control signal RON10a. When at least one of the three signals input is at a L-level, the logic circuit140foutputs a H-level conduction control signal RON10a.

To the logic circuit140i, the following signals are input: an impedance setting code Rtt (0); an impedance setting code Rtt (1); and a control signal ACT1b. When all three signals input are at a H-level, the logic circuit140ioutputs a L-level conduction control signal RON11a. When at least one of the three signals input is at a L-level, the logic circuit140ioutputs a H-level conduction control signal RON11a. To the logic circuit140j, the following signals are input: an impedance setting code Rtt (0); a logically inverted signal of an impedance setting code Rtt (1); and a control signal ACT1b. When all three signals input are at a H-level, the logic circuit140joutputs a L-level conduction control signal RON10b. When at least one of the three signals input is at a L-level, the logic circuit140joutputs a H-level conduction control signal RON10b.

The AND circuit140kcalculates a logical product of the conduction control signal RON00aand the conduction control signal RON11a, and then outputs a conduction control signal RON00.

The AND circuit140mcalculates a logical product of the conduction control signal RON10aand the conduction control signal RON10b, and then outputs a conduction control signal RON10.

When the impedance setting code Ron (0) in the impedance setting code Ron <1, 0> is at a L-level, the impedance setting code Ron (1) at a L-level, and the control signal ACT1aat a H-level, the load current selection circuit140bchanges the conduction control signal RON00from a H-level to a L-level, and keeps the conduction control signal RON10at a H-level. When the impedance setting code Ron (0) in the impedance setting code Ron <1, 0> is at a H-level, the impedance setting code Ron (1) at a L-level, and the control signal ACT1aat a H-level, the load current selection circuit140bkeeps the conduction control signal RON00at a H-level, and changes the conduction control signal RON10from a H-level to a L-level. When the impedance setting code Rtt (0) in the impedance setting code Rtt <1, 0> is at a H-level, the impedance setting code Rtt (1) at a H-level, and the control signal ACT1bat a H-level, the load current selection circuit140bchanges the conduction control signal RON00from a H-level to a L-level, and keeps the conduction control signal RON10at a H-level. When the impedance setting code Rtt (0) in the impedance setting code Rtt <1, 0> is at a H-level, the impedance setting code Rtt (1) at a L-level, and the control signal ACT1bat a H-level, the load current selection circuit140bkeeps the conduction control signal RON00at a H-level, and changes the conduction control signal RON10from a H-level to a L-level.

Returning toFIG. 15, when the control circuit21aactivates the control signal ACT1twice, the counter134counts up or down during each activation period. When the control signal ACT1is deactivated, the counter134stops the counting operation. At a time when the control signal ACT1is changed from an active level to an inactive level for the second time, the counter134retains each count value.

When the control circuit21aactivates the control signal ACT2twice, the counter135counts up or down during each activation period. At a time when the control signal ACT2is changed from an active level to an inactive level for the second time, the counter135retains each count value.

At a time when the control signal ACT2is changed from an active level to an inactive level for the second time, the latch and selection circuit140platches the count value of the counter134and the count value of the counter135.

At a time when the control signal ACT2is changed from an active level to an inactive level for the first time, the latch and selection circuit140platches the count value of the counter134as an impedance control signal DRZQP1, and the count value of the counter135as an impedance control signal DRZQN1. The impedance control signal DRZQP1and the impedance control signal DRZQN1are collectively referred to as an impedance control signal DRZQ1, which is adjusted by the load current generation circuit131gduring a calibration so as to reflect the number of unit, buffers activated. The latched impedance control signal DRZQ1is supplied in common to the pre-stage circuits161to163shown inFIGS. 2 and 4as an impedance control signal DRZQ at a time when the internal On-Die Termination control signal IODT is at a L-level.

At a time when the control signal ACT2is changed from an active level to an inactive level for the second time, the latch and selection circuit140platches the count value of the counter134as an impedance control signal DRZQP2, and the count value of the counter135as an impedance control signal DRZQN2. The impedance control signal DRZQP2and the impedance control signal DRZQN2are collectively referred to as an impedance control signal DRZQ2, which is adjusted by the load current generation circuit131gduring a calibration so as to reflect the number of unit buffers activated. The latched impedance control signal DRZQ2is supplied in common to the pre-stage circuits161to163shown inFIGS. 2 and 4as an impedance control signal DRZQ at a time when the internal On-Die Termination control signal IODT is at a H-level.

The following describes the data output operation and the ODT operation.

After a read command is supplied from a memory controller, the output control circuit150aactivates unit buffers out of unit buffers111to114and121to123of the output buffer101, with the number of unit buffers activated determined based on an impedance setting code Ron <1, 0> supplied from the mode register22a. The output control circuit150aalso drives the data terminals DQ to a logic level corresponding to Data supplied from the memory cell array20. The impedance adjustment unit130boutputs the impedance control signal DRZQ1as the impedance control signal DRZQ. Accordingly, after being activated, the pull-up circuits PU and pull-down circuits PD of the unit buffers111to114and121to123drive the data terminals with the impedance corresponding to the impedance control signal DRZQ1supplied from the impedance adjustment unit130b.

After an On-Die Termination signal is supplied from a memory controller, the output control circuit150aactivates unit buffers out of unit buffers111to114and121to123of the output buffer101, with the number of unit buffers activated determined based on an impedance setting code Rtt <1, 0> supplied from the mode register22a; and therefore terminates the data terminals DQ. The impedance adjustment unit130boutputs the impedance control signal DRZQ2as the impedance control signal DRZQ. Accordingly, after being activated, the pull-up circuits PU and pull-down circuits PD of the unit buffers111to114and121to123drive the data terminals with the impedance corresponding to the impedance control signal DRZQ2supplied from the impedance adjustment unit130b.

In that manner, the semiconductor device10aadjusts the impedances of unit buffers during the calibration in accordance with the number of unit buffers activated by the data output operation and the ODT operation. As a result, during the data output operation and the ODT operation, the semiconductor device10acan keep the impedance of the output circuit from deviating from a target value even when the number of unit buffers activated varies; and it is possible to improve the accuracy of adjusting the impedance of the output circuit (output buffer101).

The following describes a memory system that uses a semiconductor device of the present invention with reference toFIG. 17.

FIG. 17is a block diagram showing the configuration of a memory system that includes a data processor420and a DRAM10.

As shown inFIG. 17, the data processor420and the DRAM10(10a) are connected to each other via a control bus423and a data bus424. The control bus423is designed to transfer a clock, command, address, and any other control signals from the data processor420to the DRAM10(10a). The data bus424is designed to transfer data between the data processor420and the DRAM10(10a). In this case, the data are transmitted in both directions between the data processor420and the DRAM10(10a). Accordingly, as shown inFIG. 17, the data processor420also includes a data input/output unit421. In the description of the above embodiment, a data input/output unit200of the DRAM10(10a) is described in detail. The data input/output circuit421of the data processor420may have a similar impedance adjustment function to that of the data input/output circuit100(100a) of the DRAM10(10a).

The technical concept of the present application can be applied to semiconductor devices having various functions other than the memory function. Furthermore, the circuitry form in each of the circuit blocks disclosed in the drawings, as well as a circuit that generates other control signals, is not limited to the circuitry form disclosed in the examples. For example, according to the above embodiment, the output buffer101includes seven unit buffers, and activates six or seven unit buffers when the data output operation and the ODT operation are performed. However, the total number of unit buffers is not specifically limited, as long as the number is two or more. Moreover, the number of unit buffers activated during the data output operation or ODT operation is not specifically limited.

The technical concept of the present invention may be applied to, for example, semiconductor products in general, including CPUs (Central Processing Units), MCUs (Micro Control Units), DSPs (Digital Signal Processors), ASICs (Application Specific Integrated Circuits), ASSPs (Application Specific Standard Product), and memories. Examples of the product types of the semiconductor devices to which the present invention is applicable include an SOC (System On Chip), MCP (Multi Chip Package), and POP (Package On Package). The present invention may be applied to semiconductor devices that have any of such product types and package types. When the transistors are field effect transistors (FETs), various FETs are applicable, including MIS (Metal Insulator Semiconductor) and TFT (Thin Film Transistor) as well as MOS (Metal Oxide Semiconductor). The device may even include bipolar transistors.

The N-channel transistors or NMOS transistors are a representative example of the transistor of first conductivity type. The P-channel transistors or PMOS transistors are a representative example of the transistor of second conductivity type.