Display controller, electronic equipment and method for supplying image data

The display controller includes a first memory storing image data and being accessed with a sequential access operation having a shorter access time than that of a random access operation, a second memory storing image data and consuming a less power than the first memory does at the time of the access operation and a data transfer control part performing an image data transfer control between the first memory and the second memory. The data transfer control part performs a transfer control to transfer the image data from the first memory to the second memory and transfer the image data written in the second memory after the image processing from the second memory to the first memory. The display controller supplies the image data in the first memory to a display driver.

RELATED APPLICATIONS

This application claims priority to Japanese Patent Application No. 2004-195607 filed Jul. 1, 2004 which is hereby expressly incorporated by reference herein in its entirety.

BACKGROUND

1. Technical Field

The present invention relates to a display controller, electronic equipment and a method for supplying image data.

2. Related Art

Mobile devices (electronic equipment in a broad sense) such as a mobile phone often have display panels including a liquid crystal display (LCD) panel in recent years. A display panel is driven by a display driver based on image data. The image data is sometimes taken by a camera module and sometimes is generated or converted by a host. The display driver receives such image data and a display synchronizing signal and performs a driving control of the display panel.

A display controller can take over the supply of the image data and the display synchronizing signal from the host. This means that the display controller can reduce a processing load of the host. Some display controllers have memories which serve as video memories with the aim of reducing power consumption.

The display controllers mounted in the mobile devices are strongly required to be driven with low power consumption. For this reason, the memory installed in the display controller was often a static random access memory (SRAM) which uses less power compared to a dynamic random access memory (DRAM). Thereby, a capacity of the memory in the display controller tended to be relatively small. However, the small capacity of the memory was enough since a display size of the LCD panel was small. Besides, a chip size of the display controller could be small. Therefore, it was an advantage in terms of cost and packaging.

Recently, there has been great demand for a LCD panel having a display size of quarter video graphics array (QVGA) (240 pixels×320 pixels) or a larger display size. When the display size becomes larger, a data size of the image data also becomes larger. Therefore, it takes a longer time to transfer the image data from the host to the memory housed in the display controller and from the display controller to the display driver. It could also happen that a perceptible flicker appears in an image which is renewed at a certain frequency in the LCD panel. In addition, a control for image data readout from the video memory becomes complicated. This tendency gets prominent when a static image data is consecutively rewritten or a motion image data is rewritten.

Furthermore, the host cannot process other transaction during this data transfer process. It leads to a low performance of the whole system.

A disadvantage in the packaging is pointed out when the capacity of the memory becomes larger and the chip size also gets larger. However, a packaging technique has advanced recently and it is not necessarily the case that the display controller embedded with the SRAM as a memory has an advantage in the packaging.

The present invention has been developed in consideration of the above-mentioned problems, and intended to provide a display controller which can prevent the system performance from being lowered and a quality of the image from being deteriorated. The present invention also intended to provide electronic equipment and a method of supplying image data.

SUMMARY

In order to solve the above-mentioned problems, a display controller of a first aspect of the present invention includes a display driver driving a display panel and to which image data is supplied from the display controller, a first memory storing image data and being accessed with a sequential access operation having a shorter access time per predetermined data unit than an access time of a random access operation, a second memory storing image data and consuming a less power than the first memory does at a time of the access operation and a data transfer control part performing an image data transfer control between the first memory and the second memory. The data transfer control part performs a control to read out an image data from the first memory and write the image data in the second memory, an image processing is performed to the image data written in the second memory by the writing control, the data transfer control part performs a control to read out the image data that is rewritten in the second memory after the image processing from the second memory and to write the image data in the first memory, and the image data written in the first memory by the data transfer control part or the image data stored in the second memory is supplied to the display driver.

In the first aspect of the invention, the first memory storing image data is accessed with the sequential access operation having the shorter access time per predetermined data unit than the access time of the random access operation. In addition to the first memory, the second memory that consumes the less power than the first memory does at the time of the access operation is provided. The data transfer control part performs an image data transfer control between the first memory and the second memory. In other words, the data transfer control part performs the control to read out an image data from the first memory and to write the image data into the second memory. The image processing is then performed to the image data written into the second memory and the image data is rewritten in the second memory. The data transfer control part then performs a control to transfer the image data from the second memory to the first memory. The display controller supplies the image data written in the first memory by the data transfer control part or the image data stored in the second memory to the display driver. Here, it is preferred that the display controller reads out the image data written in the first memory with the sequential access operation and supplies the image data to the display driver.

According to the first aspect of the invention, the image data stored in the first memory is once transferred to the second memory. The image processing is performed to the image data in the second memory and rewritten in the second memory, and then it is again written in the first memory. In this way, it can prevent that an image processing time becomes long which is caused by the long access time of the first memory at the time of random access and the long data transfer time. Accordingly, a processing load for controlling the display controller can be allotted to other process because the data transfer time is shortened. This can help a system performance including the display controller not to be lowered.

Furthermore, the power consumption at the time of the image processing can be reduced because the second memory consuming a less power is accessed when the image data to which the image processing is performed is accessed.

The display controller may further include a first key color register in which a first key color data is set and the data transfer control part may perform a control to write an image data of a pixel that is read out from the first memory and whose pixel value is inconsistent with the first key color data into the second memory.

In the display controller, the data transfer control part may mask a writing control signal for writing the image data of the pixel read out from the first memory into the second memory if the pixel value of the pixel in the image data read out from the first memory conforms to the first key color data.

In this way, it is possible to simply perform an image composition process because the data transfer control part performs the control to write only the image data of the pixel that is read out from the first memory and whose pixel value is inconsistent with the first key color data into the second memory.

The display controller may further include a second key color register in which a second key color data is set and the data transfer control part may perform a control to write an image data of a pixel that is read out from the second memory and whose pixel value is inconsistent with the second key color data into the first memory.

In the display controller, the data transfer control part may mask a writing control signal for writing the image data of the pixel read out from the second memory into the first memory if the pixel value of the pixel in the image data read out from the second memory conforms to the second key color data.

In this way, it is possible to simply perform the image composition process because the data transfer control part performs the control to write only the image data of the pixel that is read out from the second memory and whose pixel value is inconsistent with the second key color data into the first memory.

The display controller may further include a host interface performing an interface process from and to the host. The image data read out from the second memory may be outputted to the host through the host interface. The image data after the image processing performed by the host may be inputted through the host interface and written into the second memory.

The display controller may further include an image processing part performing the image processing to the image data read out from the second memory and writing the image data after the image processing into the second memory.

In the display controller, the image processing part may perform at least one of processes including an averaging process, an edge enhancing process, an isolated point removing process and a color tone modifying process to the image data read out from the second memory.

The display controller may further include a display driver interface for supplying the image data written in the first memory by the data transfer control part or the image data stored in the second memory to the display driver.

In the display controller, the first memory may be a dynamic random access memory and the second memory may be a static random access memory.

The display controller may be a stacked type semiconductor device in which a first chip including the first memory and a second chip including the second memory and the data transfer control part are piled up.

In this way, it is possible to mount the first memory on electric equipment with a small mounting area even though the first memory has a large capacity. It does not have any disadvantages compared with a display controller that only has a memory with a small chip size in terms of the packaging. It rather has an advantage of the large capacity of the first memory.

Electronic equipment of a second aspect of the invention includes any of the above-described display controllers and a display driver driving the display panel based on an image data supplied from the display controller.

The Electronic equipment may further include a host inputting and outputting the image data to/from the display controller.

According to the second aspect of the invention, it is possible to provide electronic equipment which can prevent from the performance of the system and the image quality from being deteriorated.

A method for supplying image data to a display driver that drives a display panel of a third aspect of the invention includes a step of reading out an image data stored in a first memory and writing the image data in a second memory, a step of performing an image processing to the image data written in the second memory and writing the image data after the image processing in the second memory, a step of reading out the image data after the image processing from the second memory and writing the image data in the first memory and a step of supplying the image data written in the first memory to the display driver.

In the method for supplying image data, an image data of a pixel that is read out from the first memory and whose pixel value is inconsistent with a predetermined first key color data may be written into the second memory.

In the method for supplying image data, an image data of a pixel that is read out from the second memory and whose pixel value is inconsistent with a predetermined second key color data may be written into the first memory.

In the method for supplying image data, the first memory may be a dynamic random access memory and the second memory may be a static random access memory.

DETAILED DESCRIPTION

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Note that the embodiments described hereunder do not in any way limit the scope of the invention defined by the claims laid out herein. Note also that all of the elements of these embodiments should not be taken as essential requirements to the means of the present invention.

1. Display System

FIG. 1shows a configuration example of a display system to which a display controller according to an embodiment of the present invention is applied. For example, the display system shown inFIG. 1is mounted on electronic equipment.

A display system100includes a host10, a display controller20, a display driver50and a display panel60. The host10has a central processing unit (CPU) and a memory. The CPU reads out a program stored in the memory and performs a process corresponding to the program. In this way, a certain function is realized. Here, the host10generates or converts an image data which corresponds to an image displayed on the display panel60and supplies the image data to the display controller20.

The display controller20can supply the image data from the host10to the display driver50that drives the display panel60. The display controller20can also supply the processed image data.

The display driver50can drives the display panel60based on the image data supplied form the display controller20. As the display panel60, for example, an active matrix type or a simple matrix type LCD panel may be adopted.

As described above, the display controller20is provided between the host10and the display driver50. The display controller20can take over, for example, a process of converting the image data from the host. This means that the display controller20can reduce a processing load of the host10.

2. Display Controller

FIG. 2is a block diagram showing a configuration example of the display controller20according to the embodiment.

The display controller20includes a dynamic random access memory (DRAM)22(a first memory) and a static random access memory (SRAM)24(a second memory). Here, though the DRAM22consumes more power than the SRAM24does at the time of access (reading or writing), the DRAM22has a larger storage capacity than that of the SRAM24. In other words, the SRAM24consumes less power than the DRAM22does at the time of the access (reading or writing) though it has a smaller storage capacity than that of the DRAM22.

The display controller20also includes a data transfer control part30(a data transfer controller). The data transfer control part30controls an image data transfer between the DRAM22and the SRAM24. More specifically, the data transfer control part30can control a process in which the image data stored in the DRAM22is read out and written into the SRAM24. The data transfer control part30can also control a process in which the image data stored in the SRAM24is read out and written into the DRAM22.

The display controller20supplies the image data written in the DRAM22or the image data stored in the SRAM24by the data transfer control part30to the display driver50. In order to realize this function, the display controller20has a LCD interface (I/F) circuit38(a display driver interface in a broad sense).

The LCD I/F circuit38outputs the image data read out from the DRAM22and the SRAM24to the display driver50. The LCD I/F circuit38performs an interface process (transmission process to the display driver and buffering of signals) of the image data. The LCD I/F circuit38then outputs the image data after the interface process to the display driver50. The LCD I/F circuit38includes a synchronizing signal generation circuit (not shown in the figure). The synchronizing signal generation circuit generates synchronizing signals (a vertical synchronizing signal (VSYNC), a horizontal synchronizing signal (HSYNC), a dot clock (DCLK) and the like) for driving the display panel60. The LCD I/F circuit38can supplies these synchronizing signals to the display driver50.

Whereas such display controller20, the host10can write the image data in the DRAM22and read out the image data from the DRAM22. The host10can also write the image data in the SRAM24and read out the image data from the SRAM24. In order to realize this function, the display controller20includes a host I/F circuit32(a host interface in a broad sense), a DRAM controller34and a SRAM controller36. An image data inputted from the host10though the host I/F circuit32is written into the DRAM22by the DRAM controller34. The image data inputted from the host10though the host I/F circuit32is also written into the SRAM24by the SRAM controller36.

A motion image data or a static image data (an image data) from the host10is inputted to the host I/F circuit32. At this time, the host I/F circuit32performs an interface process (data reception process from the host and buffering of signals). The image data after the interface process is supplied to the DRAM controller34or the SRAM controller36. The image data read out from the DRAM22by the DRAM controller34and the image data read out from the SRAM24by the SRAM controller36are supplied to the host10through the host I/F circuit32. In this case, the host I/F circuit32performs an interface process (transmission process to the host and buffering of signals). The host I/F circuit32then outputs the image data after the interface process to the host10.

The DRAM controller34assigns a write address of the DRAM22and can control writing of the image data from the host10. The DRAM controller34also assigns a read address of the DRAM22and can control reading of the image data from the DRAM22.

The SRAM controller36assigns a write address of the SRAM24and can control writing of the image data from the host10. The SRAM controller36assigns a read address of the SRAM24and can also control reading of the image data from the SRAM24.

The display controller20further includes a control register40. The host10can set a control data (control information) in the control register40through the host I/F circuit32. An unshown control part in the display controller20controls each part of the display controller20based on the control data in the control register40.

Here, the embodiment will be explained by comparison with a comparative example.

FIG. 3is a block diagram schematically showing a structure of a display controller of the comparative example according to the embodiment of the invention.

A display controller150in the comparative example includes a host I/F circuit152, a LCD I/F circuit154and a SRAM156. In the display controller150, the image data from the host is stored in the SRAM156through the host I/F circuit152. In the display controller150, a predetermined image process will be performed to the image dada stored in the SRAM156. The display controller150supplies the image data read out from the SRAM156to the display driver through the LCD I/F circuit154. It is possible to reduce the power consumption with such display controller150since it employs the SRAM156which uses less power than the DRAM does at the time of the access.

However, the storage capacity of the SRAM156in the display controller150of the comparative example is not large enough to store the motion image data. For this reason, when a motion image data with a large data size is stored in the SRAM156, the motion image data has to be repeatedly written into the SRAM156. As a result, a load of the motion image data writing process (transfer process) of the host increases and the motion image data writing process could be delayed. This leads to deterioration of the motion image quality.

In order to deal with such problem, the display controller20of the embodiment has the DRAM22and decreases a frequency of access from the host. This makes it possible to reduce the loads of a large size image data writing process (transfer process) such as the motion image data. Furthermore, it is possible to prevent the image quality from being deteriorated, which is caused by the delay of the motion image data writing process and the like, since a plurality of frames worth of motion image data can be written into the DRAM22, for example. Therefore, a smooth motion picture can be shown.

The display controller20of the embodiment can make the SRAM24store at least one frame (for example, one frame or two frames) worth of static image data which has a small data size. The storage capacity of the SRAM24is enough for the static image data since the static image data has a relatively small data size compared with that of the motion image data. In addition, the power consumption is small at the time of access to supply the data to the display driver and it is possible to realize the low power consumption. For example, when the static image data is supplied to a display driver that does not have a display memory, it is necessary to access the SRAM24at a predetermined display frequency. In this case, the above-described low power consumption advantage especially becomes prominent according to the embodiment.

Moreover, in this embodiment, the image data stored in the DRAM22is once transferred to the SRAM24and a rewriting process (image processing) is performed. The image data after the rewriting process is then rewritten in the SRAM24. Again the image data is read out from the SRAM24and rewritten in the DRAM22. In this way, it can prevent that a processing time for the rewriting becomes long, which is caused by the long access time of the DRAM22at the time of random access. This respect is now described in detail below.

FIG. 4shows an example of a random access timing of the DRAM22. InFIG. 4, an example of a reading timing at the time of the random access is shown.

For example, after making a chip select signal SC active and taking a raw address in with a raw address strobe signal RAS, the chip select signal SC is activated again and a column address is taken in with a column address strobe signal CAS. The data in a storage area specified by the raw address and the column address is outputted from the DRAM22. In a case shown inFIG. 4, a read access time is 5 clock periods.

FIG. 5shows an example of a random access timing of the SRAM24. InFIG. 5, an example of the reading timing at the time of the random access is shown.

For example, when the read address is specified, a read data is read out from the SRAM24at the next clock period. In a case shown inFIG. 5, the read access time is 2 clock periods.

As described above, the DRAM22takes a longer time to read out one read data than the SRAM24dose. Therefore, the access time of the random access in which the access address is irregular becomes longer than the access time of the SRAM24.

However, the DRAM22can access sequential data at a high speed by an access operation generally called a high-speed column access operation. In the high-speed column access operation, sequential column addresses are specified while the raw address is fixed. This high-speed column access operation can also be referred as a sequential access in a broad sense.

FIG. 6shows a timing example of the high-speed column access operation of the DRAM22. InFIG. 6, an example of a reading timing of the high-speed column access operation is shown.

For example, after making the chip select signal SC active and taking the raw address in with the raw address strobe signal RAS, the chip select signal SC is activated again and the column address is taken in with the column address strobe signal CAS. The data in the storage area specified by the raw address and the column address is outputted from the DRAM22. The column address is then sequentially incremented in the DRAM22. Every time the column address is incremented, the read data which correspond to the row address and the incremented column address are outputted. This can be carried out by, for example, the following procedures. A word line specified by the row address is selected. All memory cells coupled to the selected word line are amplified by a sense amplifier and are read out to a data output line. The data specified by the column address is then sequentially taken out. In the case shown inFIG. 6, a read access time for eight sets of data is 12 clock periods. When the sequential data are accessed, the access time of one read data can be shortened.

Though the reading timing is described inFIG. 6, the above-mentioned process can also be applied to the writing timing.

In this way, the DRAM22can be referred as a memory which is accessed with a sequential access operation having a shorter access time per predetermined data unit than that of the random access operation.

The display controller20according to the embodiment can set a setting, such as whether the high-speed column access operation is performed to the DRAM22or not, the number of increments and the like, in an unshown control register of the control register40. The DRAM controller34conducts the above-described high-speed column access operation according to the setting of the control register and a command from the data transfer control part30. For this reason, the data transfer control part30can perform a burst transfer control to the DRAM controller34.

When the random access is conducted while the image data stored in the DRAM22is directly rewritten, not only the access time becomes longer but also the power consumption increases as described above. Thereby, in this embodiment, the image data stored in the DRAM22is once transferred to the SRAM24and the rewriting process (image processing) is performed. Then, the image data after the rewriting process is stored in the SRAM24and the data is further rewritten into the DRAM22from the SRAM24.

FIG. 7is an explanatory drawing schematically showing an operation of the data transfer control part30according to the embodiment of the invention.

Assume that an image data of a display image D1is stored in the DRAM22. The data transfer control part30reads out the image data of the display image D1from the DRAM22and controls the image data to be written into the SRAM24. Accordingly, an image data of a display image D2is stored in the SRAM24.

The host10then reads out the image data from the SRAM24through the host I/F circuit32and performs the rewriting process. Here, the host10rewrites the image so as to composite a display image E1and produces an image data of a display image D3. The host10again writes the image data of the display image D3after the rewriting process into the SRAM24through the host I/F circuit32. In this case, the image data is read out by the random access of the host10to the SRAM24. Therefore, it is possible to shorten the access time and reduce the power consumption at the time of the access compared with a case where the host10performs the random access to the DRAM22.

Next, the data transfer control part30reads out the image data of the display image D3from the SRAM24and performs a control in order to write the image data into the DRAM22. Accordingly, an image data of a display image D4is stored in the DRAM22.

In this way, it is possible to shorten the access time of the random access to the image data which is going to be rewritten according to the embodiment. In addition, it is possible to reduce the power consumption at the time of the access by the random access to the SRAM24compared with the case of the random access to the DRAM22.

In this embodiment, it is preferred that the data transfer control part30can conduct a key color process. In other words, the data transfer control part30receives the image data read out from an RAM which is a source. But the data transfer control part30preferably does not transfer an image data of a pixel which corresponds to a predetermined pixel value but holds the forwarding image data. The data transfer control part30then superposes (composites) the images of the two image data. To do this, the control register40includes a first key color register42in this embodiment. A first color data of the pixel is set in the first key color register42as a key color. The data transfer control part30performs the writing control in the SRAM24only to image data which are read out from the DRAM22and whose pixel values do not correspond to a first key color data. In this way, it is possible to simply perform the image composition process.

FIG. 8is an explanatory drawing for the key color process in the embodiment.

Assume that an image data of a display image D10is stored in the DRAM22and an image data of a display image D11is stored in the SRAM24. Also assume that a first key color data KC which is identical with a pixel value of a pixel in a background part F10of the display image D10is stored in the first key color register42.

The data transfer control part30reads out the image data of the display image D10from the DRAM22and performs a control so as to write the image data into the SRAM24. At this time, the pixel value of the pixel in the background part F10of the display image D10is identical with the first key color data KC. Therefore, the data transfer control part30does not perform the writing control to the image data of the pixel having the pixel value of the background part F20of the display image D10to be written in the SRAM24. As a result, an image data of a display image D12is stored in the SRAM24.

The host10then reads out the image data from the SRAM24through the host I/F circuit32and performs the rewriting process. Here, the host10rewrites the image so as to composite a display image E11and produces an image data of a display image D13. The host10again writes the image data of the display image D13after the rewriting process into the SRAM24through the host I/F circuit32.

Next, the data transfer control part30reads out the image data of the display image D13from the SRAM24and performs a control in order to write the image data into the DRAM22. Accordingly, an image data of a display image D14is stored in the DRAM22.

In this way, it is possible to easily compose the image of the display image D11and the image of the display image stored in the DRAM22as making the image of the display image D11stored in the SRAM24in advance as the background image.

Detailed configuration example of the display controller20according to the above-described embodiment will now be described.

Firstly, a configuration example of the control register40in the display controller20shown inFIG. 2is described.

FIG. 9shows the configuration example of the control register40in the display controller20shown inFIG. 2. Control information is set in each register included in the control register40through the host I/F circuit32by the host.

As described above, the first key color data of the pixel is set in the first key color register42as the key color. A first key color data KeyColor1set in the first key color register42is outputted to the data transfer control part30. The data transfer control part30performs the key color process by using the first key color data KeyColor1in the way as described above.

In a source image area setting register180, control information for setting an image area which is read from an RAM (the DRAM22or the SRAM24) that is a source of the transferring is set. The control information set in the source image area setting register180is outputted as a source image area setting information SrcArea. The data transfer control part30performs the reading control from the DRAM22or the SRAM24by using the source image area setting information SrcArea.

FIG. 10shows a configuration example of the source image area setting register180shown inFIG. 9.

FIG. 11is an explanatory drawing for the setting value of the source image area setting register180shown inFIG. 10.

InFIG. 10, a start address SA, a horizontal pixel width PW, an offset address OFFADD and the number of lines VL are set in the source image area setting register180.

An image data storage area SIAREA of the image data in the source image area is provided in a memory area MEMAREA of the RAM which is the source shown inFIG. 11. In this case, the start address SA is a reading start address for the image data storage area SIAREA of the image data in the source image area. The horizontal pixel width PW is the number of the pixels in the horizontal direction of the image in the source image area. The offset address OFFADD is a differential address between an address (final address) of an image data of the last pixel in a line where the image of the source image area is and an address of an image data of the top pixel in the next line in the vertical direction of the image in the source image area. The number of lines VL is the number of the lines in the vertical direction of the image of the source image area.

Return toFIG. 9and continue the description. Control information for setting an image area that is written into a forwarding RAM (the SRAM24or the DRAM22) is set in a forwarding image area setting register182. The control information set in the forwarding image area setting register182is outputted as a forwarding image area setting information DestArea. The data transfer control part30performs the writing control to the SRAM24or the DRAM22by using the forwarding image area setting information DestArea. A data size of an image data in an image area specified by the source image area setting information SrcArea is equal to a data size of an image data in an image area specified by the forwarding image area setting information DestArea. The forwarding image area setting register182has the same structure as that of the above-described source image area setting register180.

A transfer start control register184is a register for commanding a start of the data transfer control by the data transfer control part30. The data transfer control part30starts the data transfer control when the host10accesses the transfer start control register184through the host I/F circuit32. For example, a transfer direction can be set in the transfer start control register184and the data transfer control part30starts the data transfer control according to the transfer direction.

A reading start address or a writing start address for the DRAM22is set in a DRAM address setting register186. The address set in the DRAM address setting register186is outputted as a DRAM address DADRS. The DRAM controller34reads out the image data from the DRAM22by using a read address that is renewed based on the DRAM address DADRS. The DRAM controller34also writes the image data from the host into the DRAM22by using a write address that is renewed based on the DRAM address DADRS. The image data read out from the DRAM22is supplied to the host10through the host I/F circuit32or supplied to the display driver50through the LCD I/F circuit38together with a synchronizing signal for display.

A reading start address or a writing start address for the SRAM24is set in a SRAM address setting register188. The address set in the SRAM address setting register188is outputted as a SRAM address SADRS. The SRAM controller36reads out the image data from the SRAM24by using a read address that is renewed based on the SRAM address SADRS. The SRAM controller36also writes the image data from the host into the SRAM24by using a write address that is renewed based on the SRAM address SADRS. The image data read out from the SRAM24is supplied to the host10through the host I/F circuit32or supplied to the display driver50through the LCD I/F circuit38together with the synchronizing signal for display.

Various control information set in the control register40shown inFIG. 9are outputted to the data transfer control part30, the DRAM controller34and the SRAM controller36shown inFIG. 2.

FIG. 12is a block diagram showing a configuration example of the data transfer control part30shown inFIG. 2.

The data transfer control part30includes a DRAM transfer control circuit200, a SRAM transfer control circuit210, a comparator CMP1, a latch LAT1and a latch LAT2.

The DRAM transfer control circuit200generates an address, a reading request signal RDReq and a writing request signal WRReq based on the source image area setting information SrcArea or the forwarding image area setting information DestArea from the control register40and supplies them to the DRAM controller34. More specifically, the DRAM transfer control circuit200sequentially updates the read address specified by the source image area setting information SrcArea or the write address specified by the forwarding image area setting information DestArea according to the command for the start of transferring. The DRAM transfer control circuit200generates a read address for the DRAM controller34and the reading request signal RDReq. When the reading operation finishes, the DRAM transfer control circuit200is notified of the completion by an acknowledge signal RACK from the DRAM controller34. The DRAM transfer control circuit200also generates a write address for the DRAM controller34and the writing request signal WRReq. When the writing operation finishes, the DRAM transfer control circuit200is notified of the completion by an acknowledge signal WACK from the DRAM controller34. The DRAM transfer control circuit200performs the reading control and the writing control of the image data by pixels. Such DRAM transfer control circuit200specifies the burst transfer control for the DRAM controller34and realizes the high-speed column access operation at the timing shown inFIG. 6.

The SRAM transfer control circuit210generates the address, the reading request signal RDReq and the writing request signal WRReq based on the source image area setting information SrcArea or the forwarding image area setting information DestArea from the control register40and supplies them to the SRAM controller36. More specifically, the SRAM transfer control circuit210sequentially updates the read address specified by the source image area setting information SrcArea or the write address specified by the forwarding image area setting information DestArea according to the command for the start of transferring. The SRAM transfer control circuit210generates a read address for the SRAM controller36and the reading request signal RDReq. When the reading operation finishes, the SRAM transfer control circuit210is notified of the completion by the acknowledge signal RACK from the SRAM controller36. The SRAM transfer control circuit210also generates a write address for the SRAM controller36and the writing request signal WRReq. When the writing operation finishes, the SRAM transfer control circuit210is notified of the completion by the acknowledge signal WACK from the SRAM controller36. The SRAM transfer control circuit210performs the reading control and the writing control of the image data by pixels.

The writing request signal WRReq (a writing control signal for writing the pixel of the image data read out from the DRAM22into the SRAM24) outputted from the SRAM transfer control circuit210is mask-controlled by a mask circuit MASK1.

The read data that is read out from the DRAM22by pixels and controlled to be read by the DRAM transfer control circuit200is temporarily stored by the latch LAT1and then supplied to the SRAM24as the write data. At this time, the writing control to the SRAM24is performed by the SRAM transfer control circuit210.

The read data that is read out from the SRAM24by pixels and controlled to be read by the SRAM transfer control circuit200is temporarily stored by the latch LAT2and then supplied to the DRAM22as the write data. At this time, the writing control to the DRAM22is performed by the DRAM transfer control circuit210.

The comparator CMP1compares the first key color data KeyColor1set in the first key color register42with the image data of the pixel stored in the latch LAT1. Output of the comparator CMP1becomes a low (L) level when these data are identical while the output of the comparator CMP1becomes a high (H) level when these data are not identical. Therefore, the mask circuit MASK1masks the writing control in order to prevent the image data of the pixel corresponding to the first key color data KeyColor1from being written into the SRAM24. Accordingly, the data transfer control part30can only perform the writing control for writing the image data of the pixel corresponding to the first key color data KeyColor1into the SRAM24.

FIG. 13shows a configuration example of the DRAM controller34shown inFIG. 2.

The DRAM controller34includes a write FIFO260, a read FIFO262, a control signal generation circuit264, an arbiter circuit266and a refresh request generation circuit268.

The write FIFO260accumulates the image data from the host through the host I/F circuit32and sequentially outputs the write data to the DRAM22at the timing specified by the control signal generation circuit264. The read FIFO262accumulates the read data from the DRAM22and sequentially outputs the read data to the host I/F circuit32, the LCD I/F circuit38and the data transfer control part30at the timing specified by the control signal generation circuit264.

The control signal generation circuit264generates a control signal and an address for performing the writing operation or the reading operation to the DRAM22based on a read address or write address for transferring sent from the DRAM transfer control circuit200, a write address for writing or a read address for displaying sent from an unshown control part and a result of arbitration by the arbiter circuit266. As such control signal, there are the chip select signal CS, a write enable signal WE, the raw address strobe signal RAS, the column address strobe signal CAS and the like as shown inFIG. 4orFIG. 6.

The arbiter circuit266arbitrates a writing request, a reading request from the DRAM transfer control circuit200or an unshown control part and a refresh request from the refresh request generation circuit268. The arbiter circuit266notifies the control signal generation circuit264of the arbitration result and notifies the completion of the access for the request signal by the acknowledge signals WACK and RACK.

The refresh request generation circuit268generates the refresh request in a refresh period of the DRAM22and sends it to the arbiter circuit266.

FIG. 14shows a configuration example of the SRAM controller36shown inFIG. 2.

The SRAM controller36includes a control signal generation circuit270and an arbiter circuit272.

The control signal generation circuit270generates a control signal and an address for performing the writing operation or the reading operation to the SRAM24based on a read address or write address for transferring that is sent from the SRAM transfer control circuit210, a write address for writing or a read address for displaying sent from the unshown control part and a result of arbitration by the arbiter circuit272. As such control signal, there is the write enable signal WE shown inFIG. 5and the like.

The arbiter circuit272arbitrates a writing request and a reading request from the SRAM transfer control circuit210or the unshown control part. The arbiter circuit272notifies the control signal generation circuit270of the arbitration result and notifies the completion of the access for the request signal by the acknowledge signals WACK and RACK.

As described above, the data transfer control part30conducts the data transfer control in which the DRAM controller34accesses the DRAM22and the SRAM controller36accesses the SRAM24. In the unshown control part, the DRAM controller34accesses the DRAM22and the SRAM controller36accesses the SRAM24. Then, the unshown control part controls the output of the image data to the display driver through the LCD I/F circuit38. The unshown control part also controls the writing and the reading to and from the host through the host I/F circuit32.

FIG. 15shows an example of an operation sequence of the display controller20and the host10according to the embodiment.

Firstly, the host10supplies an image data through the host I/F circuit32in the display controller20(SEQ1). In the display controller20, the DRAM controller34writes the image data from the host into a storage area of the DRAM22which is specified by the DRAM address DADRS set in the DRAM address setting register186(SEQ2).

The host10then sets a readout area of the DRAM22, a write area of the SRAM24and the key color (first key color data) in the control register40of the display controller20. The readout area is an image area where the host wants to perform the rewriting process later. The host10then accesses the transfer start control register184in the control register40(SEQ3). By doing this, the data transfer control part30reads out the image data in the readout area of the DRAM22by the high-speed column access operation and performs the control to sequentially write the image data into the write area of the SRAM24. In this way, the burst transfer is performed (SEQ4).

Next, the host10reads out the image data written in the write area of the SRAM24which is set in SEQ3through the host I/F circuit32(SEQ5).

The host10performs the rewriting process (image processing in a broad sense) to the image data read out from the SRAM24(SEQ6). As such rewriting process, there is an effect process such as an averaging process of pixels, an edge enhancing process, an isolated point removing process and a color tone modifying process.

The host10writes the image data that was rewritten in the above-described way into the SRAM24once again through the host I/F circuit32(SEQ7). As a result, the image data after the rewriting process is stored in the SRAM24(SEQ8).

The host10then sets a readout area of the SRAM24and a write area of the DRAM22in the control register40in the display controller20. This readout area of the SRAM24can be same as the write area of the SRAM24set in SEQ3(or the read out area by the host in SEQ5or the written area in the host in SEQ7). The write area of the DRAM22can be same as the read out area of the DRAM22set in SEQ3. The host10then accesses the transfer start control register184in the control register40(SEQ9). By doing this, the data transfer control part30reads out the image data in the readout area of the SRAM24and performs the control to write the image data into the write area of the DRAM22by the high-speed column access operation. In this way, the burst transfer is performed (SEQ10).

After that, in the display controller20, at least one frame worth of image data including the image data after the rewriting process is read out from the DRAM22and supplied to the display driver50together with the synchronizing signal through the LCD I/F circuit38(SEQ11). In this way, the display driver50controls the display of the display panel60.

2.1 First Modification Example

Though the data transfer control part30performs the key color process when the image data is transferred from the DRAM22to the SRAM24in the above-described embodiment, the present invention is not limited to this.

Besides when the image data is transferred from the DRAM22to the SRAM24, the key color process is also performed when the image data is transferred from the SRAM24to the DRAM22in a first modification example of the invention.

FIG. 16is a block diagram showing a configuration example of a data transfer control part300in the first modification example. The same structures as those of the data transfer control part30in the above-described embodiment shown inFIG. 12are given the identical numerals and those explanations will be omitted.

In the data transfer control part300shown inFIG. 16, a comparator CMP2and a mask circuit MSK2are added to the data transfer control part30shown inFIG. 12. A second key color is provided in the control register40as the key color of the pixel at the time of transferring the image data from the SRAM24to the DRAM22in the first modification example. A second key color data KeyColor2which is a setting value of a second key color register is inputted in the comparator CMP2.

In the first modification example, a writing request signal WRReq (a writing control signal for writing the pixel of the image data read out from the SRAM24into the DRAM22) outputted from the DRAM transfer control circuit200is mask-controlled by the mask circuit MASK2.

The comparator CMP2compares the second key color data KeyColor2set in the second key color register with an image data of the pixel stored in the latch LAT2. Output of the comparator CMP2becomes the low (L) level when these data are identical while the output of the comparator CMP2becomes the high (H) level when these data are not identical. Therefore, the mask circuit MASK2masks the writing control in order to prevent the image data of the pixel corresponding to the second key color data KeyColor2from being written into the DRAM22. Accordingly, the data transfer control part300can only perform the writing control to write the image data of the pixel corresponding to the second key color data KeyColor2into the DRAM22.

Other parts of the display controller of the first modification example are the same as those of the display controller20in the above-described embodiment. Therefore, those descriptions will be omitted. According to the first modification example, it is possible to simply realize the image composition process in the same way as the case described with reference toFIG. 8.

Note that the present invention is not limited to the above-described embodiment or the first modification example. The key color process may be performed only when the image data is transferred from the SRAM24to the DRAM22. It is obvious that the display controller in the first modification example may be applied to the display system shown inFIG. 1.

2.2 Second Modification Example

Though the host reads out the image data after the data transfer controlled by the data transfer part from the SRAM24and performs the rewriting process in the above-described embodiment and the first modification example, the invention is not limited to this. In a second modification example of the present invention, the display controller includes an image processing part360which performs the rewriting process (for example, the effect processes such as the averaging process of pixels, the edge enhancing process, the isolated point removing process and the color tone modifying process) instead of the host in the above-described embodiment and the first modification example. This rewriting process can be referred as the image processing in a broad sense.

FIG. 17is a block diagram showing a configuration example of a display controller in the second modification example. The same structures as those of the display controller20in the above-described embodiment shown inFIG. 2are given the identical numerals and those explanations will be omitted.

A display controller350in the second modification example has the image processing part360in addition to the display controller in the above-described embodiment and the first modification example. This image processing part360can perform the effect processes such as the averaging process of pixels, the edge enhancing process, the isolated point removing process and the color tone modifying process as the rewriting process of the image data stored in the SRAM24.

In the second modification example, the image processing part360requests the SRAM controller36for reading the image data of the pixel in the image area to which the writing process is performed from the SRAM24. The image processing part360also requests the SRAM controller36for rewriting the image data after the rewriting process into the SRAM24. When the image data is rewritten into the SRAM24, it is preferred that the image data is rewritten in the read area of the rewriting process.

Such process of the image processing part360may be started by a command from the host10or the image processing part360may start the process itself when it receives the completion notice of the data transfer control from the data transfer control part30.

FIG. 18is an explanatory drawing of the effect process performed by the image processing part360in the second modification example.

As the effect process performed by the image processing part360, for example, there are the averaging process of pixels, the edge enhancing process, the isolated point removing process and the color tone modifying process.

In the averaging process of pixels, a pixel value of each pixel in a image area PIC of the image data read out from the SRAM24is renewed by an average value averaging the pixel value and pixel values of eight pixels around the pixel. For example, a coefficient register, an offset register and a DIV value register are added to the control register40. Assume that the image data of each pixel is in a YUV format and a target pixel is a pixel P5shown inFIG. 18, the renewed value is derived from the following formula by using pixel values p1though p9(pixel value of the pixel P5is p5) of pixels P1, P2. . . P4, P6. . . P9around the pixel P5, setting values (k1through k9), a setting value (offset) of the offset register in the control register40and a setting value (DIV) of the DIV value register in the control register40.
P5=offset+(P1×k1+P2×k2+ . . . P5×k5+ . . . +P9×k9)/DIV(1)

The renewed value is obtained with respect to each of a Y component, a U component and a V component from the above-referred formula and the pixel P5is renewed by these obtained values. In this way, an effect image in which the image is shaded off can be realized by performing the above-described process to each pixel in the image area PIC or a predetermined area.

In the edge enhancing process, a contrast between the pixel value of the pixel and a pixel value of the adjacent pixel is calculated with respect to the pixel value of each pixel in the image area PIC of the image data read out from the SRAM24. If the calculated contrast exceeds a predetermined threshold value, the contrast is replaced by a corrected value in which the contrast is increased. In this way, it is possible to generate an effect image in which a contour of the image is emphasized by performing the above-described process to each pixel in the image area PIC or a predetermined area.

In the isolated point removing process, a pixel that is considered to be a noise is removed. For example, a difference between the pixel value of each pixel in the image area PIC of the image data read from the SRAM24and each pixel value of the eight pixels around the pixel is calculated. If the difference value is not within a predetermined range and the number of such difference values is more than a predetermined number, the pixel is judged as the noise and the correction process to correct the pixel is performed. In the correction process, the pixel value of the pixel is replaced by the average of the pixels values of the pixels around the pixel. In this way, it is possible to generate an effect image in which the isolated point that exits in the image is removed by performing the above-described process to each pixel in the image area PIC or a predetermined area.

In the color tone modifying process, when color information of each pixel in the image area PIC of the image data read out from the SRAM24is predetermined color information, it is corrected to be other color information. In this way, it is possible to generate an effect image in which a color balance is changed or a contrast is modified by performing the above-described process to each pixel in the image area PIC or a predetermined area.

The image processing part360may perform at least one of the above-mentioned processes, the averaging process of pixels, the edge enhancing process, the isolated point removing process and the color tone modifying process.

In the second modification example, the key color process may be performed when the data is transferred from the DRAM22to the SRAM24and when the data is transferred from the SRAM24to the DRAM22in the same way as the first modification example. The key color process may be performed only when the data is transferred from the SRAM24to the DRAM22in the second modification example. It is obvious that the display controller in the second modification example may be applied to the display system shown inFIG. 1.

As described above, the display controller in the embodiment, the first and second modification examples can be equipped with the DRAM22which has a large capacity. If the chip size becomes large because of the DRAM, it is preferable that the semiconductor chip is mounted on the display controller by a three dimensional packaging. To be more specific, so called stacked-type semiconductor device in which a first semiconductor chip and a second semiconductor chip are piled up. The DRAM22is formed in the first semiconductor chip and the SRAM24and the data transfer control part30are formed in the second semiconductor chip.

FIG. 19shows an example of a cross-sectional structure of the display controller formed as the stacked-type semiconductor device.

In this case, an electrode is provided on a package substrate PAB. The electrode is electrically coupled to a solder ball that serves as an external connection part and formed on the package substrate PAB. A first semiconductor chip CHIP1in which the DRAM22is formed is provided on the package substrate PAB with an insulating layer interposed therebetween. A second semiconductor chip CHIP2in which the SRAM24and the data transfer control part30are formed is provided on the first semiconductor chip CHIP1with an insulating layer interposed therebetween.

An electrode is formed on each of the first semiconductor chip CHIP1and the second semiconductor chip CHIP2and electrically coupled to the electrode formed on the package substrate PAB with a bonding wire. The first semiconductor chip CHIP1and the second semiconductor chip CHIP2are sealed with an insulating resin IM.

By employing such packaging, it is possible to mount the display controller on the mobile devices even though the display controller has the large-capacity DRAM22. It does not have any disadvantage compared with a display controller that only has a memory with a small chip size in terms of the packaging. It rather has an advantage of the large capacity DRAM22.

3. Electronic Equipment

FIG. 20is a block diagram schematically showing a structure of electronic equipment to which the display controller according to the embodiment, the first and the second modification example is applied. Here, as the electronic equipment, a cellular phone is taken as an example and a block diagram of the configuration example of the cellular phone is shown.

A cellular phone400includes a camera module410. The camera module410includes a Charge-Coupled device (CCD) camera and supplies an image data taken by the CCD camera in YUV format to a display controller402. As the display controller402, the display controller described in the embodiment, the first modification example and the second modification example can be adopted.

The cellular phone400includes a display panel420. As the display panel420, a liquid crystal display panel can be adopted. In this case, the display panel420is driven by a display driver430. The display panel420includes a plurality of scan lines, a plurality of data lines and a plurality of picture elements. The display driver430has a function of a scan driver which is to select a one scan line or a few scan lines out of the plurality of scan lines and a function of a data driver which is to supply a voltage that corresponds to the image data to the plurality of the data lines.

The display controller402is coupled to the display driver430and supplies an image data in RGB format to the display driver430. Transfer of the image data between the RGB format and the YUV format can be conducted in the display controller402.

A host440is coupled to the display controller402. The host440controls the display controller402. The host440can also decode the image data received through an antenna466in a modem unit450and supply the decoded data to the display controller402. The display controller402displays the image on the display panel420by the display driver430based on the image data.

The host440can modulate the image data that is generated in the camera module410in the modem unit450. The host440can then instruct to send the image data to other communication devices through the antenna460.

The host440performs the sending or receiving process of the image data, an encoding process, a process of taking images by the camera module410and a display process of the display panel according to instructional information from an input operation part470.

Though the liquid crystal panel is described as the example of the display panel420inFIG. 24, the case is not limited to this. The display panel420may be an electroluminescence or plasma display device and the present invention can be applied to the display controller which supplies the image data to the display driver that drives these devices.

The present invention is not limited to the above-described embodiments but applied to various kinds of modifications within the scope and spirit of the present invention.

Though the DRAM was taken as an example for the memory that is accessed by the sequential access operation having the shorter access time than that of the random access operation in the above-described embodiments, the present invention is not limited to this. The invention is also not limited by a structure of the memory element. The structure of the memory element may be the DRAM memory element and a way to access the memory may be a way like accessing the SRAM. Moreover, though the SRAM was taken as an example for the memory having the smaller power consumption compared with the DRAM at the time of the access, the invention is not limited to this and not limited by the structure of the memory element.

In inventions according to the dependent claims laid out herein, note that a part of the components appear in the independent claim may be omitted. Also note that essential parts of the independent claim may depend on other independent claim.