THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MEMORY OPENINGS ARRANGED IN NON-EQUILATERAL TRIANGULAR LAYOUT AND METHOD OF MAKING THEREOF

A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, where a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle, and memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.

FIELD

The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including memory openings arranged in a non-equilateral triangular layout and methods of manufacturing the same.

BACKGROUND

Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High-Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.

SUMMARY

According to an aspect of the present disclosure, a memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, where a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle, and memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.

According to another aspect of the present disclosure, a memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, wherein each of the memory openings has a respective elongated horizontal cross-sectional shape having a respective a major axis and a respective minor axis, and the major axes of the memory openings extend in a nearest neighbor memory opening direction; and memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a vertical semiconductor channel and a vertical stack of memory elements.

According to yet another aspect of the present disclosure, a method of forming a memory device comprises forming an alternating stack of insulating layers and sacrificial material layers over a substrate; forming memory openings vertically extending through the alternating stack, wherein a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle; forming memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and vertical semiconductor channels; removing the sacrificial material layers from between the memory opening fill structures to form laterally-extending cavities; and forming electrically conductive layers in the laterally extending cavities.

DETAILED DESCRIPTION

As discussed above, embodiments of the present disclosure are directed to a three-dimensional memory device including memory openings arranged in a non-equilateral triangular layout for facilitating lateral diffusion of a reactant during formation of replacement word lines and methods of manufacturing the same, the various aspects of which are described below. In one embodiment, the memory openings may be elongated along the nearest neighbor distance.

Generally, a semiconductor die, or a semiconductor package, can include a memory chip. Each semiconductor package contains one or more dies (for example one, two, or four). The die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (typically one or two). Identical, concurrent operations can take place on each plane, although with some restrictions. Each plane contains a number of blocks, which are the smallest unit that can be erased by in a single erase operation. Each block contains a number of pages, which are the smallest unit that can be programmed, i.e., a smallest unit on which a read operation can be performed.

Referring toFIG.1, an exemplary structure according to an embodiment of the present disclosure is illustrated. The exemplary structure comprises a substrate9, which may be a semiconductor substrate or a conductive substrate. For example, the substrate9may comprise a commercially available silicon wafer. Alternatively, the substrate9may comprise a carrier substrate9which is formed of any material that may be removed selective the materials of insulating layers32and dielectric material portions to be subsequently formed.

An optional insulating material layer can be formed on a top surface of the carrier substrate9. The insulating material layer can be subsequently employed as a stopping material layer for a process that removes the carrier substrate9, and is herein referred to as a stopper insulating layer106, or as a backside pad dielectric layer. If a polishing process such as a chemical mechanical polishing process is employed to subsequently remove the carrier substrate9, the stopper material layer106may be subsequently employed as a polishing stopper material layer. If an etch process such as a wet etch process is employed to subsequently remove the carrier substrate9, the stopper material layer106may be subsequently employed as an etch stop material layer. In one embodiment, the stopper insulating layer106comprises a dielectric material such as undoped silicate glass, a doped silicate glass, or silicon nitride. The thickness of the stopper insulating layer106may be in a range from 50 nm to 600 nm, such as from 100 nm to 300 nm, although lesser and greater thicknesses may also be employed.

Optional in-process source-level material layers110′ can be formed over the stopper insulating layer106. The in-process source-level material layers110′ may include various layers that are subsequently modified to form source-level material layers. The source-level material layers, upon formation, include a source contact layer that functions as a common source region for vertical field effect transistors of a three-dimensional memory device. In one embodiment, the in-process source-level material layers110′ may include, from bottom to top, a lower source-level semiconductor layer112, an optional lower sacrificial liner103, a source-level sacrificial layer104, an optional upper sacrificial liner105, and an upper source-level semiconductor layer116.

The lower source-level semiconductor layer112and the upper source-level semiconductor layer116may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source-level semiconductor layer112and the upper source-level semiconductor layer116may be the opposite of the conductivity of vertical semiconductor channels to be subsequently formed. For example, if the vertical semiconductor channels to be subsequently formed have a doping of a first conductivity type, the lower source-level semiconductor layer112and the upper source-level semiconductor layer116have a doping of a second conductivity type that is the opposite of the first conductivity type. The thickness of each of the lower source-level semiconductor layer112and the upper source-level semiconductor layer116may be in a range from 10 nm to 300 nm, such as from 20 nm to 150 nm, although lesser and greater thicknesses may also be used.

The source-level sacrificial layer104includes a sacrificial material that may be removed selective to the lower sacrificial liner103(or selective to the lower source-level semiconductor layer112) and the upper sacrificial liner105(or selective to the upper source-level semiconductor layer116). In one embodiment, the source-level sacrificial layer104may include a semiconductor material such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source-level sacrificial layer104may be in a range from 30 nm to 400 nm, such as from 60 nm to 200 nm, although lesser and greater thicknesses may also be used. The lower sacrificial liner103(if present) and the upper sacrificial liner105(if present) include materials that may function as an etch stop material during removal of the source-level sacrificial layer104. For example, the lower sacrificial liner103and the upper sacrificial liner105may include silicon oxide, silicon nitride, and/or a dielectric metal oxide. In one embodiment, each of the lower sacrificial liner103and the upper sacrificial liner105may include a silicon oxide layer having a thickness in a range from 2 nm to 30 nm, although lesser and greater thicknesses may also be used.

An alternating stack of first material layers and second material layers can be formed over the in-process source-level material layers110′. The first material layers may be insulating layers, and the second material layers may be spacer material layers. In one embodiment, the spacer material layers may comprise sacrificial material layers42. In this case, an alternating stack (32,42) of insulating layers32and sacrificial material layers42can be formed over the in-process source-level material layers110′. The insulating layers32comprise an insulating material such as undoped silicate glass or a doped silicate glass, and the sacrificial material layers42comprise a sacrificial material, such as silicon nitride or a silicon-germanium alloy. In one embodiment, the insulating layers32(i.e., the first material layers) may comprise silicon oxide layers, and the sacrificial material layers42(i.e., the second material layers) may comprise silicon nitride layers. The alternating stack (32,42) may comprise multiple repetitions of a unit layer stack including an insulating layer32and a sacrificial material layer42. The total number of repetitions of the unit layer stack within the alternating stack (32,42) may be, for example, in a range from 8 to 1,024, such as from 32 to 256, although lesser and greater number of repetitions may also be employed. The topmost one of the insulating layers32is hereafter referred to as a topmost insulating layer32T. The bottommost one of the insulating layers32is an insulating layer32that is most proximal to the carrier substrate9is herein referred to as a bottommost insulating layer32B.

Each of the insulating layers32other than the topmost insulating layer32may have a thickness in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed. Each of the sacrificial material layers42may have a thickness in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed. In one embodiment, the topmost insulating layer32may have a thickness of about one half of the thickness of other insulating layers32.

The exemplary structure comprises a memory array region100in which a three-dimensional array of memory elements is to be subsequently formed, and a contact region300in which layer contact via structures contacting word lines are to be subsequently formed.

While an embodiment is described in which the spacer material layers are formed as sacrificial material layers42, the spacer material layers may be formed as electrically conductive layers in an alternative embodiment. Generally, spacer material layers of the present disclosure may be formed as, or may be subsequently replaced at least partly with, electrically conductive layers.

In an alternative embodiment, driver circuit semiconductor devices (e.g., transistors) may be formed over the substrate9next to the alternating stack (32,42) or underneath the alternating stack (32,42). In yet another alternative embodiment, the in-process source-level material layers110′ may be omitted, in case the substrate9is a carrier substrate which is later removed and a top source contact layer is formed on an exposed surface of the memory device.

Each sacrificial material layer42other than a topmost sacrificial material layer42within the alternating stack (32,42) laterally extends farther than any overlying sacrificial material layer42within the alternating stack (32,42) in the terrace region. The stepped surfaces of the alternating stack (32,42) continuously extend from a bottommost layer within the alternating stack (32,42) (such as the bottommost insulating layer32B) to a topmost layer within the alternating stack (32,42) (such as the topmost insulating layer32T).

Optionally, drain-select-level isolation structures (not shown) can be formed through the topmost insulating layer32T and a subset of the sacrificial material layers42located at drain-select-levels. The drain-select-level isolation structures can be formed, for example, by forming drain-select-level lateral isolation trenches and filling the drain-select-level lateral isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the topmost insulating layer32T.

Referring toFIGS.3A and3B, an etch mask layer (not shown) can be formed over the alternating stack (32,42), and can be lithographically patterned to form various openings therein. An anisotropic etch process can be performed to transfer the pattern of the openings in the etch mask layer through the alternating stack (32,42). Various openings can be formed through the alternating stack (32,42). The various openings may comprise memory openings49that are formed in the memory array region100and support openings19that are formed in the contact region300. Each of the memory openings49and the support openings19can vertically extend through the alternating stack (32,42) and into the in-process source-level material layers110′ In one embodiment, bottom surfaces of the memory openings49and the support openings19may be formed within the lower source-level semiconductor layer112or at an interface between the lower source-level semiconductor layer and the stopper insulating layer106.

The support openings19may have a diameter in a range from 60 nm too 400 nm, such as from 120 nm to 300 nm, although lesser and greater thicknesses may be employed. The memory openings49may have a diameter in a range from 60 nm too 400 nm, such as from 120 nm to 300 nm, although lesser and greater thicknesses may be employed.

In one embodiment, the memory array region100may be laterally spaced apart from the contact region300along a first horizontal direction hd1. The memory openings49may comprise rows of memory openings49that are arranged along the first horizontal direction hd1and laterally spaced apart along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd2. Multiple clusters of memory openings49, each containing a respective two-dimensional periodic array of memory openings49, may be formed in the memory array region100. The clusters of memory openings49may be laterally spaced apart along the second horizontal direction hd2.

FIGS.4A-4Iare magnified top-down views of various configurations of a portion of a memory array region100after the processing steps ofFIGS.3A and3B.

Referring toFIG.4A, a portion of the memory array region100is shown after the processing steps ofFIGS.3A and3Baccording to a first embodiment. In the first embodiment, each memory opening49within the multiple rows of memory openings49has a respective circular horizontal cross-sectional shape. As used herein, “circular” includes exactly circular shapes or slightly off circular shapes due to lithography and etching deviations.

The smallest unit shape of three nearest neighbor memory openings49is a non-equilateral triangle. In one embodiment, the non-equilateral triangle comprises a scalene triangle having three sides A, B and C which do not equal to each other (i.e., A≠B≠C) and three angles θ1, θ2and θ3which do not equal to each other (i.e., θ1≠θ≠θ3). The vertices of the scalene triangle are located at the geometric centers of the three memory openings49in a horizontal plane. In this configuration of memory opening, there exists a direction providing a greater average lateral distance between neighboring pairs of memory openings49. This horizontal direction is labeled as “direction of easy lateral diffusion,” and provides a wider diffusion path during subsequent processing steps that are employed to isotropically etch the sacrificial material layers42to form laterally-extending cavities, and to conformally deposit at least one conductive material to form electrically conductive layers. Thus, the direction of easy lateral diffusion comprises a first diffusion path is provided in the laterally-extending cavities between a first set of memory openings49which is wider than a second diffusion path provided in the laterally extending cavities between a second set of memory openings. Thus, improved electrically conductive layer filling may be achieved. Such paths also provide enhanced fluorine out diffusion paths if fluorine is used to deposit the electrically conductive layers (e.g., if WF6is used to deposit tungsten electrically conductive layers). Thus, less fluorine becomes trapped in the device, which improves device reliability because trapped fluorine may damage various device layers due to solid state diffusion between device layers.

Referring toFIG.4B, a portion of the memory array region100is shown after the processing steps ofFIGS.3A and3Baccording to a second embodiment. In the second embodiment, the memory openings49are arranged in a zig-zag configuration. The smallest unit shape of three nearest neighbor memory openings49is still a non-equilateral triangle, such as a scalene triangle. However, in this configuration, the direction of easy lateral diffusion (DELD) is a zig-zag horizontal direction.

Referring toFIG.4C, a portion of the memory array region100is shown after the processing steps ofFIGS.3A and3Baccording to a third embodiment. In the third embodiment, the memory openings49have non-circular horizontal cross-sectional shapes. For example, the memory openings may have oval horizontal cross-sectional shapes having a long axis and a short axis. The long axes extend along the nearest neighbor memory opening direction, such as the DELD direction. The smallest unit shape of three nearest neighbor memory openings49is still a non-equilateral triangle, such as a scalene triangle.

Referring toFIG.4D, a portion of the memory array region100is shown after the processing steps ofFIGS.3A and3Baccording to the fourth embodiment. In the fourth embodiment, the memory openings49have non-circular, such as oval, horizontal cross-sectional shapes. The smallest unit shape of three nearest neighbor memory openings49is an equilateral triangle, having all three sides “A” equal to each other and all three angles equal to 60 degrees. Thus, in this configuration, the memory openings49are arranged in a hexagonal close packed lattice.

FIGS.4E to4Iillustrate additional geometric features of the memory opening49layouts of the various embodiments of the present disclosure.

Referring toFIG.4E, a first configuration of a portion of the memory array region100is shown after the processing steps ofFIGS.3A and3B. In the first configuration, each memory opening49within the multiple rows of memory openings49has a respective circular horizontal cross-sectional shape.

According to an aspect of the present disclosure, multiple rows of memory openings49can be formed through the alternating stack (32,42) in each cluster of memory openings49. Each row among the multiple rows comprises a respective one-dimensional periodic array of memory openings49having a uniform pitch p along the first horizontal direction hd1. The multiple rows are laterally spaced from each other along the second horizontal direction hd2, which is perpendicular to the first horizontal direction hd1.

Upon sequentially numbering the multiple rows of memory openings49in any cluster of memory openings49with integers beginning with 1 along the second horizontal direction hd2, the multiple rows of memory openings49comprise odd-numbered rows and even-numbered rows. For each memory opening49, a respective geometrical center can be defined as the center of gravity of a hypothetical object having a same volume (i.e., occupying the same space) as the memory opening49and having a uniform density throughout. Further, for each memory opening49, a respective vertical axis passing through the geometrical center can be defined. Each vertical axis passing through the geometrical center of a respective memory opening49is perpendicular to the top surface of the carrier substrate9and/or to the bottommost surface of the alternating stack (32,42).

In the illustrated example, five rows of memory openings49are illustrated, which comprise an (i−2)-th row (labeled “R_i−2”), an (i−1)-th row (labeled “R_i−1”), an i-th row (labeled “R_i”), an (i+1)-th row (labeled “R_i+1”), and an (i+2)-th row (labeled “R_i+2). If R is an odd number, the (i−2)-th row, the i-th row, and the (i+2)-th row are odd-numbered rows, and the (i−1)-th row and the (i+1)-th row are even-numbered rows. In one embodiment, the center-to-center distance between neighboring rows of memory openings49may be √3/2 times the uniform pitch p. In another embodiment, center-to-center distance between neighboring rows of memory openings49may be different from √3/2 times the uniform pitch p, and may be in a range from 0.85 times √3/2 times the uniform pitch p to 1.15 times √3/2 times the uniform pitch p, and/or in a range from 0.90 times √3/2 times the uniform pitch p to 1.10 times √3/2 times the uniform pitch p, and/or in a range from 0.95 times √3/2 times the uniform pitch p to 1.05 times √3/2 times the uniform pitch p.

Generally, the pattern of the memory openings49may have three directions of periodic repetitions. The first direction of periodic repetition DPR_1can be the first horizontal direction hd1, and the pattern of the memory openings49may repeat along the first direction of periodic repetition DPR_1with the uniform pitch p, which is the center-to-center distance between geometrical centers of a neighboring pair of memory openings49within any row of memory openings49. The second direction of periodic repetition DPR_2can be rotated along a first rotation direction (which may be anticlockwise or clockwise) from the first direction of periodic repetition DPR_1by an angle π/3−α, which is less than π/3. The pattern of the memory openings49may be repeated at every other row along the second direction of periodic repetition DPR_2. The third direction of periodic repetition DPR_3can be rotated along a second rotation direction (which is the opposite direction of the first rotation direction) from the opposite direction of the first direction of periodic repetition DPR_1by an angle π/3+β, which is greater than π/3. The pattern of the memory openings49may be repeated at every other row along the third direction of periodic repetition DPR_3.

According to an aspect of the present disclosure, for each first vertical axis VA1passing through a geometrical center of a respective memory opening49in any odd-numbered row, a second vertical axis VA2passing through a geometrical center of a most proximal memory opening49within a most proximal odd-numbered row is laterally offset from the first vertical axis VA1along the first horizontal direction hd1by a first lateral offset distance Δ that is greater than 0 and is less than one half of the uniform pitch p. In one embodiment, the first lateral offset distance Δ may be greater than 0.01 times the uniform pitch p, and/or may be in a range from 0.02 times the uniform pitch p, and/or may be in a range from 0.03 times the uniform pitch p, and/or may be in a range from 0.05 times the uniform pitch p, and/or may be in a range from 0.10 times the uniform pitch p, and/or may be in a range from 0.15 times the uniform pitch p, and/or may be in a range from 0.20 times the uniform pitch p, and/or may be in a range from 0.25 times the uniform pitch p, and/or may be in a range from 0.30 times the uniform pitch p, and/or may be in a range from 0.35 times the uniform pitch p, and/or may be in a range from 0.40 times the uniform pitch p. Further, the first lateral offset distance Δ may be less than 0.49 times the uniform pitch p, and/or may be in a range from 0.48 times the uniform pitch p, and/or may be in a range from 0.47 times the uniform pitch p, and/or may be in a range from 0.45 times the uniform pitch p, and/or may be in a range from 0.40 times the uniform pitch p, and/or may be in a range from 0.35 times the uniform pitch p, and/or may be in a range from 0.30 times the uniform pitch p, and/or may be in a range from 0.25 times the uniform pitch p, and/or may be in a range from 0.20 times the uniform pitch p, and/or may be in a range from 0.15 times the uniform pitch p, and/or may be in a range from 0.10 times the uniform pitch p.

In one embodiment, for each first vertical axis VA1passing through the geometrical center of the respective memory opening49in any odd-numbered row, a third vertical axis VA3passing through a geometrical center of a most proximal memory opening49within a most proximal even-numbered row is laterally offset from the first vertical axis VA1along the first horizontal direction hd1by a second lateral offset distance (p−Δ)/2−η that is greater than 0 and is less than (p−Δ)/2. In this case, the periodicity of the pattern of the memory openings49along the second horizontal direction hd2is greater than the center-to-center distance between neighboring pairs of rows, and may be the same as twice the center-to-center distance between neighboring pairs of rows.

In one embodiment, the difference between (p−Δ)/2 and the second lateral offset distance (p−Δ)/2−η is a lateral shift distance η that is greater than 0 and is less than Δ/2. In one embodiment, the lateral shift distance η may be greater than 0.05 times Δ/2, and/or may be greater than 0.1 times Δ/2, and/or may be greater than 0.2 times Δ/2, and/or may be greater than 0.3 times Δ/2, may be greater than 0.4 times Δ/2, and/or may be greater than 0.5 times Δ/2, may be greater than 0.6 times Δ/2, and/or may be greater than 0.7 times Δ/2, may be greater than 0.8 times Δ/2, and/or may be greater than 0.9 times Δ/2. Further, the lateral shift distance η may be less than 0.95 times Δ/2, and/or may be less than 0.9 times Δ/2, and/or may be less than 0.8 times Δ/2, and/or may be less than 0.7 times Δ/2, may be less than 0.6 times Δ/2, and/or may be less than 0.5 times Δ/2, may be less than 0.4 times Δ/2, and/or may be less than 0.3 times Δ/2, may be less than 0.2 times Δ/2, and/or may be less than 0.1 times Δ/2.

In one embodiment, for each first vertical axis VA1passing through the geometrical center of the respective memory opening49in any odd-numbered row, a planar vertical plane that passes through the first vertical axis VA1and is parallel to the second horizontal direction hd2does not pass through a geometrical center of any memory opening49within any nearest-neighboring row of memory openings49or within any second-nearest-neighboring row of memory openings49.

In one embodiment, a first vertical plane VP1passing through a geometrical center of a memory opening49within an odd-numbered row of memory openings49and passing through a geometrical center of a memory opening49within a nearest-neighboring odd-numbered row of memory openings49is at a first angle (π/3−α) with respective to the first horizontal direction hd1. The first vertical plane VP1can be parallel to the second direction of periodic repetition DPR_2. The first angle (π/3−α) is less than π/3 and is greater than arctan(√{square root over (3)}/(1.5)). In case the center-to-center distance between neighboring rows of memory openings49is √3/2 times the uniform pitch p, the lateral offset distance along the first horizontal direction between the geometrical center of the memory opening49within the odd-numbered row of memory openings49and the geometrical center of a memory opening49within the nearest-neighboring odd-numbered row of memory openings49is greater than p, and is less than 1.5 times p. In the present disclosure, all angles are measured in radians.

In one embodiment, a second vertical plane VP2passing through the geometrical center of the memory opening49within the odd-numbered row of memory openings49and passing through a geometrical center of another memory opening49within the nearest-neighboring odd-numbered row of memory openings49is at a second angle (π/3+β) with respective to the first horizontal direction hd1. The second angle (π/3+β) is greater than π/3 and is less than arctan(√{square root over (3)}/(1.5)). The second vertical plane VP2can be parallel to the third direction of periodic repetition DPR_3.

In one embodiment, a third vertical plane VP3passing through the geometrical center of the memory opening49within the odd-numbered row of memory openings49and passing through a geometrical center of a memory opening49a nearest-neighboring even-numbered row of memory openings49is at a third angle (π/3+γ) with respective to the first horizontal direction hd1. The third angle (π/3+γ) is greater than the second angle (π/3+β).

The first configuration of the array of memory openings49provides a horizontal direction providing a greater average lateral distance between neighboring pairs of memory openings49. This horizontal direction is labeled as “direction of easy lateral diffusion,” and provides high-diffusivity diffusion paths during subsequent processing steps that are employed to isotropically etch the sacrificial material layers42to form laterally-extending cavities, and to conformally deposit at least one conductive material to form electrically conductive layers. In the illustrated example, the “direction of easy lateral diffusion” may be parallel to the third direction of periodic repetition DPR_3.

Referring toFIG.4F, a second configuration of a portion of the memory array region100is shown after the processing steps ofFIGS.3A and3B. In the second configuration, each memory opening49within the multiple rows of memory openings49has a respective circular horizontal cross-sectional shape. The second configuration of the memory openings49can be derived from the first configuration of the memory openings49illustrated inFIG.4Aby setting the value of the parameter η to be equal to zero. Further, the value of the parameter γ can be the same as the value of β in the second configuration. In the second configuration, for each first vertical axis VA1passing through the geometrical center of the respective memory opening49in any odd-numbered row, a third vertical axis VA3passing through a geometrical center of a most proximal memory opening49within a most proximal even-numbered row is laterally offset from the first vertical axis VA1along the first horizontal direction hd1by a second lateral offset distance that equals p/2.

In the second configuration, the pattern of the memory openings49may have three directions of periodic repetitions. The first direction of periodic repetition DPR_1can be the first horizontal direction hd1, and the pattern of the memory openings49may repeat along the first direction of periodic repetition DPR_1with the uniform pitch p, which is the center-to-center distance between geometrical centers of a neighboring pair of memory openings49within any row of memory openings49. The second direction of periodic repetition DPR_2can be rotated along a first rotation direction (which may be anticlockwise or clockwise) from the first direction of periodic repetition DPR_1by an angle π/3−α, which is less than π/3. The pattern of the memory openings49may be repeated at every row along the second direction of periodic repetition DPR_2. Thus, the repetition distance along the second direction of periodic repetition DPR_2is halved in the second configuration compared to the repetition distance in the first configuration. The third direction of periodic repetition DPR_3can be rotated along a second rotation direction (which is the opposite direction of the first rotation direction) from the opposite direction of the first direction of periodic repetition DPR_1by an angle π/3+β, which is greater than π/3. The pattern of the memory openings49may be repeated at every row along the third direction of periodic repetition DPR_3. Thus, the repetition distance along the third direction of periodic repetition DPR_3is halved in the second configuration compared to the repetition distance in the first configuration.

The second configuration of the array of memory openings49provides a horizontal direction providing a greater average lateral distance between neighboring pairs of memory openings49. This horizontal direction is labeled as “direction of easy lateral diffusion,” and provides high-diffusivity diffusion paths during subsequent processing steps that are employed to isotropically etch the sacrificial material layers42to form laterally-extending cavities, and to conformally deposit at least one conductive material to form electrically conductive layers. In the illustrated example, the “direction of easy lateral diffusion” may be parallel to the third direction of periodic repetition DPR_3.

Referring toFIG.4G, a third configuration of a portion of the memory array region100is shown after the processing steps ofFIGS.3A and3B. In the third configuration, each memory opening49within the multiple rows of memory openings49has a respective non-circular horizontal cross-sectional shape, which may be an elliptical shape. In other words, the third configuration of the memory openings49can be derived from the first configuration of the memory openings49illustrated inFIG.4Aby elongating each of the memory openings49along a horizontal direction in a manner that generates a horizontal direction providing a greater average lateral distance between neighboring pairs of memory openings49.

In the illustrated example, the elongation direction of the memory openings49may be parallel to the “direction of easy lateral diffusion” discussed with reference toFIG.4A. By selecting the elongation direction of the memory openings49to be parallel to the “direction of easy lateral diffusion,” the diffusion paths that are parallel to the “direction of easy lateral diffusion” can provide high-diffusivity diffusion paths during subsequent processing steps that are employed to isotropically etch the sacrificial material layers42to form laterally-extending cavities, and to conformally deposit at least one conductive material to form electrically conductive layers. In the illustrated example, the “direction of easy lateral diffusion” may be parallel to the third direction of periodic repetition DPR_3.

In the third configuration of the array of memory openings49, multiple rows of memory openings49vertically extend through the alternating stack (32,42). Each row among the multiple rows comprises a respective one-dimensional periodic array of memory openings49having a uniform pitch p along the first horizontal direction hd1. The multiple rows are laterally spaced among one another along the second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. Each memory opening49within the multiple rows of memory openings49has a respective elongated horizontal cross-sectional shape having a respective horizontal direction of a major axis and a respective horizontal direction of a minor axis. As used herein, the major axis of a two-dimensional shape is the maximum lateral dimension of the two-dimensional shape, and minor axis of the two-dimensional shape is the minimum lateral dimension of the two-dimensional shape. In case the two-dimensional shape if an ellipse, the major axis can be the same as the mathematical definition of the major axis of an ellipse, and the minor axis can be the same as the mathematical definition of the minor axis of the ellipse.

Each horizontal direction of the major axis of the memory openings49in the multiple rows of memory openings49can be parallel among one another, and can be at a non-zero and non-orthogonal angle with respect to the first horizontal direction hd1. In one embodiment, the non-zero and non-orthogonal angle is greater than π/3 and is less than arctan(2√{square root over (3)}). In one embodiment, the horizontal direction of the major axes of the memory openings49may be parallel to the third direction of periodic repetition DPR3, or may along an azimuthal direction that deviates from the third direction of periodic repetition DPR3by an angle less than π/6, and/or less than π/12, and/or less than π/24. The ellipticity e of the horizontal shape of each memory opening49, as defined by e=(1−(b/a)2)1/2in which a is the major axis and b is the minor axis, may be greater than 0 and less than 0.6 (which corresponds to b/a of 0.8). In one embodiment, the ellipticity e may be greater than 0.001, and/or greater than 0.01, and/or greater than 0.03, and/or greater than 0.1, and/or greater than 0.2, and/or greater than 0.3, and/or greater than 0.4, and/or greater than 0.5. Further, the ellipticity e may be less than 0.59, and/or less than 0.5, and/or less than 0.4, and/or less than 0.3, and/or less than 0.2, and/or less than 0.1, and/or less than 0.05, and/or less than 0.03.

In one embodiment, the multiple rows comprise, upon sequentially numbering with integers beginning with 1 along the second horizontal direction hd2, odd-numbered rows and even-numbered rows, and each pattern of memory openings49in any odd-numbered row is periodically repeated in every other odd-numbered row along the second horizontal direction hd2with a periodicity that equals a center-to-center distance between neighboring pairs of odd-numbered rows within the multiple rows. In one embodiment, for each first vertical axis VA1passing through a geometrical center of a respective memory opening49in any odd-numbered row, a second vertical axis VA2passing through a geometrical center of a most proximal memory opening49within a most proximal odd-numbered row is laterally offset from the first vertical axis VA1along the first horizontal direction hd1by a first lateral offset distance Δ that is greater than 0 and is less than one half of the uniform pitch p.

Generally, the values of the various parameters α, β, γ, Δ, and η in the third configuration may be in the same range as the corresponding values of the various parameters in the first configuration.

Referring toFIG.4H, a fourth configuration of a portion of the memory array region100is shown after the processing steps ofFIGS.3A and3B. In the fourth configuration, each memory opening49within the multiple rows of memory openings49has a respective elongated horizontal cross-sectional shape. The fourth configuration of the memory openings49can be derived from the third configuration of the memory openings49illustrated inFIG.4Cby setting the value of the parameter η to be equal to zero. Further, the value of the parameter γ can be the same as the value of β in the fourth configuration. In the fourth configuration, for each first vertical axis VA1passing through the geometrical center of the respective memory opening49in any odd-numbered row, a third vertical axis VA3passing through a geometrical center of a most proximal memory opening49within a most proximal even-numbered row is laterally offset from the first vertical axis VA1along the first horizontal direction hd1by a second lateral offset distance that equals (p−Δ)/2.

In the fourth configuration, the pattern of the memory openings49may have three directions of periodic repetitions. The first direction of periodic repetition DPR_1can be the first horizontal direction hd1, and the pattern of the memory openings49may repeat along the first direction of periodic repetition DPR_1with the uniform pitch p, which is the center-to-center distance between geometrical centers of a neighboring pair of memory openings49within any row of memory openings49. The second direction of periodic repetition DPR_2can be rotated along a first rotation direction (which may be anticlockwise or clockwise) from the first direction of periodic repetition DPR_1by an angle π/3−α, which is less than π/3. The pattern of the memory openings49may be repeated at every row along the second direction of periodic repetition DPR_2. Thus, the repetition distance along the second direction of periodic repetition DPR_2is halved in the fourth configuration compared to the repetition distance in the third configuration. The third direction of periodic repetition DPR_3can be rotated along a second rotation direction (which is the opposite direction of the first rotation direction) from the opposite direction of the first direction of periodic repetition DPR_1by an angle π/3+β, which is greater than π/3. The pattern of the memory openings49may be repeated at every row along the third direction of periodic repetition DPR_3. Thus, the repetition distance along the third direction of periodic repetition DPR_3is halved in the fourth configuration compared to the repetition distance in the third configuration.

The fourth configuration of the array of memory openings49provides a horizontal direction providing a greater average lateral distance between neighboring pairs of memory openings49. This horizontal direction is labeled as “direction of easy lateral diffusion,” and provides high-diffusivity diffusion paths during subsequent processing steps that are employed to isotropically etch the sacrificial material layers42to form laterally-extending cavities, and to conformally deposit at least one conductive material to form electrically conductive layers. In the illustrated example, the “direction of easy lateral diffusion” may be parallel to the third direction of periodic repetition DPR_3.

Referring toFIG.4I, a fifth configuration of a portion of the memory array region100is shown after the processing steps ofFIGS.3A and3B. In the fifth configuration, each memory opening49within the multiple rows of memory openings49has a respective elongated horizontal cross-sectional shape. The fifth configuration of the memory openings49can be derived from the fourth configuration of the memory openings49illustrated inFIG.4Cby setting the value of the parameter Δ to be equal to zero. Further, the value of the parameter γ can be the same as the value of β in the fifth configuration. In the fifth configuration, for each first vertical axis VA1passing through the geometrical center of the respective memory opening49in any odd-numbered row, a fourth vertical axis VA3passing through a geometrical center of a most proximal memory opening49within a most proximal even-numbered row is laterally offset from the first vertical axis VA1along the first horizontal direction hd1by a second lateral offset distance that equals p/2.

In the fifth configuration, the pattern of the memory openings49may have three directions of periodic repetitions. The first direction of periodic repetition DPR_1can be the first horizontal direction hd1, and the pattern of the memory openings49may repeat along the first direction of periodic repetition DPR_1with the uniform pitch p, which is the center-to-center distance between geometrical centers of a neighboring pair of memory openings49within any row of memory openings49. The second direction of periodic repetition DPR_2can be rotated along a first rotation direction (which may be anticlockwise or clockwise) from the first direction of periodic repetition DPR_1by an angle π/3−α, which is less than π/3. The pattern of the memory openings49may be repeated at every row along the second direction of periodic repetition DPR_2. Thus, the repetition distance along the second direction of periodic repetition DPR_2is halved in the fifth configuration compared to the repetition distance in the fourth configuration. The fourth direction of periodic repetition DPR_3can be rotated along a second rotation direction (which is the opposite direction of the first rotation direction) from the opposite direction of the first direction of periodic repetition DPR_1by an angle π/3+β, which is greater than π/3. The pattern of the memory openings49may be repeated at every row along the fourth direction of periodic repetition DPR_3. Thus, the repetition distance along the fourth direction of periodic repetition DPR_3is halved in the fifth configuration compared to the repetition distance in the fourth configuration.

The fifth configuration of the array of memory openings49provides a horizontal direction providing a greater average lateral distance between neighboring pairs of memory openings49. This horizontal direction is labeled as “direction of easy lateral diffusion,” and provides high-diffusivity diffusion paths during subsequent processing steps that are employed to isotropically etch the sacrificial material layers42to form laterally-extending cavities, and to conformally deposit at least one conductive material to form electrically conductive layers. In the illustrated example, the “direction of easy lateral diffusion” may be parallel to the fourth direction of periodic repetition DPR_3.

In one embodiment, the geometrical centers of the memory openings49in the fifth configuration of the memory array49may be located at lattice sites of a periodic, close-packed hexagonal array.

Referring toFIG.5, an optional etch stop liner (not shown) and a sacrificial fill material (not shown) can be deposited in the memory openings49and the support openings. The optional etch stop liner (if present) comprises a thin dielectric material layer comprising silicon oxide, silicon nitride, or a dielectric metal oxide and having a thickness in a range from 1 nm to 6 nm. The sacrificial fill material may comprise a carbon-based material (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as amorphous silicon or polysilicon), a dielectric fill material (such as borosilicate glass or organosilicate glass), or a polymer material. Excess portions of the sacrificial fill material can be removed from above the horizontal plane including the topmost layer of the alternating stack (32,42) by a planarization process such as an etch back process. Remaining portions of the sacrificial fill material that fill the memory openings49and the support openings19constitute sacrificial memory opening fill structures (not shown) and sacrificial support opening fill structures (not shown).

A photoresist layer (not shown) can be applied over the alternating stack (32,42) and the retro-stepped dielectric material portion65, and can be lithographically patterned to cover the memory array region100without covering the contact region300. The sacrificial support opening fill structures and portions of the optional etch stop liner in the contact region300can be removed selective to the materials of the retro-stepped dielectric material portion65and the alternating stack (32,42). For example, an etch process or an ashing process may be employed to remove the sacrificial support opening fill structures and portions of the optional etch stop liner in the contact region300. The photoresist layer can be subsequently removed.

A dielectric fill material, such as silicon oxide, can be deposited in the support openings19by a conformal deposition process. Excess portions of the dielectric fill material can be removed from above the top surface of the topmost insulating layer32T, for example, by a recess etch process. Each portion of the dielectric fill material that fills a respective support opening19constitutes a support pillar structure20, which can be employed to provide structural support to the insulating layers32and the retro-stepped dielectric material portion65during replacement of the sacrificial material layers42with electrically conductive layers.

Subsequently, the sacrificial memory opening fill structures and portions of the optional etch stop liner in the memory array region100can be removed selective to the materials of the retro-stepped dielectric material portion65and the alternating stack (32,42). For example, an etch process or an ashing process may be employed to remove the sacrificial memory opening fill structures and portions of the optional etch stop liner in the memory array region100. Voids are formed in the volumes of the memory openings49.

FIGS.6A-6Dare sequential schematic vertical cross-sectional views of a memory opening49within the exemplary structure during formation of a memory opening fill structure58according to an embodiment of the present disclosure.

Referring toFIG.6A, a memory opening49is illustrated after the processing steps ofFIG.5.

Referring toFIG.6B, a layer stack including a memory material layer54can be conformally deposited. In an illustrative example, the layer stack may comprise an optional blocking dielectric layer52, the memory material layer54, and an optional dielectric liner56. The memory material layer54includes a memory material, i.e., a material that can store data bits therein. The memory material layer54may comprise a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing a change in the electrical resistivity, ferroelectric polarization, or any other measurable physical property. In case the memory material layer54comprise a charge storage material, the optional dielectric liner56may comprise a tunneling dielectric layer.

A semiconductor channel material layer60L can be deposited over the layer stack (52,54,56) by performing a conformal deposition process. If the semiconductor channel material layer60L is doped, the semiconductor channel material layer60L may have a doping of a first conductivity type, which may be p-type or n-type. In one embodiment, the first semiconductor material comprises a first doped silicon material having a doping of the first conductivity type. In an illustrative example, the atomic concentration of dopants of the first conductivity type in the semiconductor channel material layer60L may be in a range from 1.0×1013/cm3to 3.0×1011/cm3, such as 1.0×1014/cm3to 3.0×1016/cm3, although lesser and greater atomic concentrations may also be employed. A dielectric core layer62L comprising a dielectric fill material can be deposited in remaining volumes of the memory openings49and over the alternating stack (32,42).

Referring toFIG.6C, the dielectric core layer62L can be vertically recessed such that each remaining portion of the dielectric core layer62L has a top surface at, or about, the horizontal plane including the bottom surface of the topmost insulating layers32T. Each remaining portion of the dielectric core layer62L constitutes a dielectric core62.

Referring toFIG.6D, a doped semiconductor material having a doping of a second conductivity type can be deposited within each recessed region above the dielectric cores62. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

Excess portions of the deposited semiconductor material having a doping of the second conductivity type and a horizontal portion of the semiconductor channel layer60L can be removed from above the horizontal plane including the top surface of the topmost insulating layer32T, for example, by chemical mechanical planarization (CMP) or a recess etch process. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each remaining portion of the semiconductor channel layer60L (which has a doping of the first conductivity type) constitutes a vertical semiconductor channel60.

Each portion of the layer stack including the memory material layer54that remains in a respective memory opening49constitutes a memory film50. In one embodiment, a memory film50may comprise an optional blocking dielectric layer52, a memory material layer54, and an optional dielectric liner56. Each contiguous combination of a memory film50and a vertical semiconductor channel60constitutes a memory stack structure55. Each combination of a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49constitutes a memory opening fill structure58. Each memory opening fill structure58comprises a respective vertical stack of memory elements, which may comprise portions of the memory material layer54located at levels of the sacrificial material layers42, or generally speaking, at levels of spacer material layers that may be formed as, or may be subsequently replaced at least partly with, electrically conductive layers.

Referring toFIG.7, the exemplary structure is illustrated after formation of memory opening fill structures58within the memory openings49. Each of the memory opening fill structures58may comprise a respective vertical semiconductor channel60that is laterally surrounded by the respective vertical stack of memory elements (which may be embodied as portions of the memory film50located at levels of the sacrificial material layers42that are subsequently replaced with electrically conductive layers).

Referring toFIGS.8A and8B, a dielectric material such as undoped silicate glass or a doped silicate glass can be deposited over the alternating stack (32,42) to form a contact-level dielectric layer80. The thickness of the contact-level dielectric layer80may be in a range from 100 nm to 600 nm, such as from 200 nm to 400 nm, although lesser and greater thicknesses may also be employed.

A photoresist layer (not shown) can be applied over the contact-level dielectric layer80, and can be lithographically patterned to form elongated openings that laterally extend along the first horizontal direction hd1between neighboring clusters of memory opening fill structures58. An anisotropic etch process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer80, the alternating stack (32,42), the stepped dielectric material portion65, and the in-process source-level material layers110′. Lateral isolation trenches79laterally extending along the first horizontal direction hd1can be formed through the alternating stack (32,42), the stepped dielectric material portion65, the contact-level dielectric layer80, and the in-process source-level material layers110′. Each of the lateral isolation trenches79may comprise a respective pair of lengthwise sidewalls that are parallel to the first horizontal direction hd1and vertically extend from the stopper insulating layer106to the top surface of the contact-level dielectric layer80. A top surface of the stopper insulating layer106can be physically exposed underneath each lateral isolation trench79. The photoresist layer can be subsequently removed, for example, by ashing.

Referring toFIG.9, an etchant that etches the material of the source-level sacrificial layer104selective to the materials of the alternating stack (32,42), the contact level dielectric layer80, the stepped dielectric material portion65, the lower source-level semiconductor layer112, the upper source-level semiconductor layer116, the upper sacrificial liner105(if present), and the lower sacrificial liner103(if present) may be introduced into the lateral isolation trenches79by performing an isotropic etch process. For example, if the source-level sacrificial layer104includes undoped amorphous silicon or a silicon-germanium alloy, a wet etch process using hot trimethyl-2 hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) may be used to remove the source-level sacrificial layer104selective to the alternating stack (32,42), the contact level dielectric layer80, the stepped dielectric material portion65, the lower source-level semiconductor layer112, and the upper source-level semiconductor layer116. A source cavity109is formed in the volume from which the source-level sacrificial layer104is removed.

Wet etch chemicals such as hot TMY and TMAH are selective to doped semiconductor materials such as the p-doped semiconductor material and/or the n-doped semiconductor material of the upper source-level semiconductor layer116and the lower source-level semiconductor layer112. Thus, use of selective wet etch chemicals such as hot TMY and TMAH for the wet etch process that forms the source cavity109provides a large process window against etch depth variation during formation of the lateral isolation trenches79. Specifically, even if sidewalls of the upper source-level semiconductor layer116are physically exposed or even if a surface of the lower source-level semiconductor layer112is physically exposed upon formation of the source cavity109, collateral etching of the upper source-level semiconductor layer116and/or the lower source-level semiconductor layer112is minimal, and the structural change to the exemplary structure caused by accidental physical exposure of the surfaces of the upper source-level semiconductor layer116and/or the lower source-level semiconductor layer112during manufacturing steps do not result in device failures. Each of the memory opening fill structures58is physically exposed to the source cavity109. Specifically, each of the memory opening fill structures58includes a sidewall and that are physically exposed to the source cavity109.

A sequence of isotropic etchants, such as wet etchants, may be applied to the physically exposed portions of the memory films50to sequentially etch the various component layers of the memory films50from outside to inside, and to physically expose cylindrical surfaces of the vertical semiconductor channels60at the level of the source cavity109. The upper sacrificial liner105(if present) and the lower sacrificial liner103(if present) may be collaterally etched during removal of the portions of the memory films50located at the level of the source cavity109. The source cavity109may be expanded in volume by removal of the portions of the memory films50at the level of the source cavity109and the upper and lower sacrificial liners. A top surface of the lower source-level semiconductor layer112and a bottom surface of the upper source-level semiconductor layer116may be physically exposed to the source cavity109. The source cavity109is formed by isotropically etching the source-level sacrificial layer104and a bottom portion of each of the memory films50selective to at least one source-level semiconductor layer (such as the lower source-level semiconductor layer112and the upper source-level semiconductor layer116) and the vertical semiconductor channels60.

Referring toFIG.10, a semiconductor material having a doping of the second conductivity type may be deposited on the physically exposed semiconductor surfaces around the source cavity109. The physically exposed semiconductor surfaces include bottom portions of outer sidewalls of the vertical semiconductor channels60and a horizontal surface of the at least one source-level semiconductor layer (such as a bottom surface of the upper source-level semiconductor layer116and/or a top surface of the lower source-level semiconductor layer112). For example, the physically exposed semiconductor surfaces may include the bottom portions of outer sidewalls of the vertical semiconductor channels60, the top horizontal surface of the lower source-level semiconductor layer112, and the bottom surface of the upper source-level semiconductor layer116.

In one embodiment, the doped semiconductor material of the second conductivity type may be deposited on the physically exposed semiconductor surfaces around the source cavity109by a selective semiconductor deposition process. A semiconductor precursor gas, an etchant, and a dopant gas may be flowed concurrently into a process chamber including the exemplary structure during the selective semiconductor deposition process. For example, the semiconductor precursor gas may include silane, disilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and the dopant gas may include a hydride of a dopant atom such as phosphine, arsine, stibine, or diborane. In this case, the selective semiconductor deposition process grows a doped semiconductor material having a doping of the second conductivity type from physically exposed semiconductor surfaces around the source cavity109. The deposited doped semiconductor material forms a source contact layer114, which may contact sidewalls of the vertical semiconductor channels60. The atomic concentration of the dopants of the second conductivity type in the deposited semiconductor material may be in a range from 1.0×1020/cm3to 2.0×1021/cm3, such as from 2.0×1020/cm3to 8.0×1020/cm3. The source contact layer114as initially formed may consist essentially of semiconductor atoms and dopant atoms of the second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process may be used to form the source contact layer114. Optionally, one or more etch back processes may be used in combination with a plurality of selective or non-selective deposition processes to provide a seamless and/or voidless source contact layer114.

The duration of the selective semiconductor deposition process may be selected such that the source cavity109is filled with the source contact layer114. In one embodiment, the source contact layer114may be formed by selectively depositing a doped semiconductor material having a doping of the second conductivity type from semiconductor surfaces around the source cavity109. In one embodiment, the doped semiconductor material may include doped polysilicon. Thus, the source-level sacrificial layer104may be replaced with the source contact layer114. The layer stack including the lower source-level semiconductor layer112, the source contact layer114, and the upper source-level semiconductor layer116constitutes a source layer110, which replaces the in-process source-level material layers110′. The source layer110contacts an end portion of each of the vertical semiconductor channels60.

Referring toFIG.11, an isotropic etch process can be performed to remove the sacrificial material layers42selective to the insulating layers32, the stopper insulating layer106, the memory opening fill structures58, the sacrificial etch stop liners71, and the source layer110. According to an embodiment of the present disclosure, the presence of the direction of easy lateral diffusion (illustrated inFIGS.4A-4I) facilitates lateral diffusion of the isotropic etchant during the isotropic etch process. Generally, the direction of easy lateral diffusion provides a greater lateral spacing between neighboring pairs of memory opening fill structures58than other lateral directions in the exemplary structure (such as the first direction of periodic repetition DPR_1or the third direction of periodic repetition DPR_3). The greater lateral spacing among neighboring pairs of memory opening fill structures58along a horizontal direction that is perpendicular to the direction of easy lateral diffusion in the various embodiments of the present disclosure allows more effective lateral diffusion of the isotropic etchant during the isotropic etch process than a comparative exemplary structure employing a hexagonal periodic array of memory opening fill structures58having a respective circular horizontal cross-sectional shape (thereby not providing any direction of easy lateral diffusion). Thus, the various configurations of the present disclosure provide more effective etching of the sacrificial material layers42.

Laterally-extending cavities43can be formed in volumes from which the sacrificial material layers42are removed. Sidewall surface segments of the memory opening fill structures58can be physically exposed to the laterally-extending cavities43. In an illustrative example, if the sacrificial material layers42comprise silicon oxide, the isotropic etch process may comprise a wet etch process employing hot phosphoric acid, which is a process in which the exemplary structure is immersed in phosphoric acid at, or near, the boiling point of the phosphoric acid. A suitable clean process may be performed as needed.

Referring toFIG.12, a backside blocking dielectric layer (not shown) can be optionally formed in the laterally-extending cavities43by a conformal deposition process. At least one conductive material, such as at least one metallic material, can be conformally deposited in the laterally-extending cavities43. At least one chemical vapor deposition process and/or at least one atomic layer deposition process can be employed to deposit the at least one conductive material. According to an embodiment of the present disclosure, the presence of the direction of easy lateral diffusion (illustrated inFIGS.4A-4I) facilitates lateral diffusion of a reactant gas during the conformal deposition process(es). Generally, the direction of easy lateral diffusion provides a greater lateral spacing between neighboring pairs of memory opening fill structures58than other lateral directions in the exemplary structure (such as the first direction of periodic repetition DPR_1or the third direction of periodic repetition DPR_3). The greater lateral spacing among neighboring pairs of memory opening fill structures58along a horizontal direction that is perpendicular to the direction of easy lateral diffusion in the various embodiments of the present disclosure allows more effective lateral diffusion of the reactant gas during each conformal deposition process than a comparative exemplary structure employing a hexagonal periodic array of memory opening fill structures58having a respective circular horizontal cross-sectional shape (thereby not providing any direction of easy lateral diffusion). Thus, the various configurations of the present disclosure provide more effective conformal deposition of the at least one conductive material while minimizing formation of any unfilled void.

The at least one conductive material may comprise, for example, a combination of a metallic barrier material and a metallic fill material. The metallic barrier material may comprise, for example, TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof. The metallic fill material may comprise, for example, Ti, Ta, Mo, Co, Ru, W, Cu, other transition metals, and/or alloys or layer stacks thereof. Excess portions of the at least one conductive material that are deposited in the lateral isolation trenches79or above the contact-level dielectric layer80can be removed by performing an etch-back process, which may comprise an isotropic etch process and/or an anisotropic etch process. Each remaining portion of the at least one conductive material filling a respective one of the laterally-extending cavities43constitutes an electrically conductive layer46. An alternating stack of insulating layers32and electrically conductive layers46can be formed between each neighboring pair of lateral isolation trenches79over the carrier substrate9. A plurality of alternating stacks of insulating layers32and electrically conductive layers46can be laterally spaced apart among one another by the lateral isolation trenches79.

Referring toFIGS.13A and13B, an insulating fill material may be conformally deposited in the lateral isolation trenches79. Excess portions of the insulating fill material may be removed from above the contact-level dielectric layer80, for example, by a recess etch process. Each remaining portion of the insulating fill material that fills a respective lateral isolation trench79constitutes an isolation trench fill structure76. Alternatively, each isolation trench fill structure76may comprise a combination of a tubular insulating spacer (not expressly shown) and a conductive connection via structure (not expressly shown) that is laterally surrounded by the tubular insulating spacer.

A photoresist layer (not shown) can be applied over the contact-level dielectric layer80, and can be lithographically patterned to form openings over each of the memory opening fill structures58over the horizontally-extending surfaces of the stepped surfaces in the contact region. An anisotropic etch process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer80and the retro-stepped dielectric material portion65. Drain contact via cavities can be formed through the contact-level dielectric layer80over the memory opening fill structures58. Layer contact via structures can be formed through the contact-level dielectric layer80and the retro-stepped dielectric material portion65on a top surface of a respective one of the electrically conductive layers46. The photoresist layer can be subsequently removed, for example, by ashing.

At least one conductive material, such as a combination of a metallic barrier material and a metallic fill material, can be deposited in the drain contact via cavities and the layer contact via cavities. Excess portions of the at least one conductive material can be removed from above the horizontal plane including the top surface of the contact-level dielectric layer80by a planarization process, which may employ a recess etch process and/or a chemical mechanical polishing process. Remaining portions of the at least one conductive material that fill the drain contact via cavities constitute drain contact via structures88contacting a top surface of a respective one of the drain regions63. Remaining portions of the at least one conductive material that fill the layer contact via cavities constitute layer contact via structures86contacting a top surface of a respective one of the electrically conductive layers46.

Referring toFIGS.14A and14B, a connection-level dielectric layer90can be formed above the contact-level dielectric layer80. Connection via cavities can be formed through the connection-level dielectric layer90, and can be filled with at least one conductive material (which may comprise at least one metallic material) to form connection-level via structures (98,96). The connection-level via structures (98,96) comprise drain connection via structures98that contact a respective one of the drain contact via structures88, and layer connection via structures96that contact a respective one of the layer contact via structures86.

A bit-line-level dielectric layer120can be formed above the connection-level dielectric layer90. Bit-line-level line cavities can be formed through the bit-line-level dielectric layer120, and can be filled with at least one conductive material (which may comprise at least one metallic material) to form bit-line-level metal lines (128,126). The bit-line-level metal lines may comprise bit lines128that laterally extend generally along the second horizontal direction hd2with periodic change of lateral extension directions such that the periodicity of the periodic change of the lateral extension directions is the same as the periodicity of the isolation trench fill structures76. This feature can occur when the first lateral offset distance Δ is not equal to zero, as in the case of the first through fourth configurations of the arrays of memory openings49(and thus, of the arrays of memory opening fill structures58) described above. In this case, the tilt angle of longer sections of the bit lines128relative to the second horizontal direction hd2may be the arctangent of the ratio of the first lateral offset distance Δ to the center-to-center distance between neighboring pairs of even-numbered rows of memory openings49(which is the same as the center-to-center distance between neighboring pairs of even-numbered rows of memory opening fill structures58).

Referring toFIG.15, additional dielectric material layers and additional metal interconnect structures can be formed over the bit-line-level dielectric layer120. The additional dielectric material layers may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and/or at least one additional line-and-via-level dielectric layer. The additional metal interconnect structures may comprise metal via structures, metal line structures, and/or integrated metal line-and-via structures. The additional dielectric material layers that are formed above the bit-line-level dielectric layer120are herein referred to as memory-side dielectric material layers960. The additional metal interconnect structures are collectively referred to as memory-side metal interconnect structures980.

Metal bonding pads, which are herein referred to as upper bonding pads988, may be formed at the topmost level of the memory-side dielectric material layers960. The upper bonding pads988may be electrically connected to the memory-side metal interconnect structures980and various nodes of the three-dimensional memory array including the alternating stacks of insulating layers32and electrically conductive layers46and the memory opening fill structures58. A memory die900can thus be provided.

The memory-side dielectric material layers960are formed over the alternating stacks (32,46). The memory-side metal interconnect structures980are embedded in the memory-side dielectric material layers960. The memory-side bonding pads988can be embedded within the memory-side dielectric material layers960, and specifically, within the topmost layer among the memory-side dielectric material layers960. The memory-side bonding pads988can be electrically connected to the memory-side metal interconnect structures980.

In one embodiment, the memory die900may comprise: a three-dimensional memory array underlying the first dielectric material layer110and comprising an alternating stack (32,46) of insulating layers32and electrically conductive layers46, a two-dimensional array of memory openings49vertically extending through the alternating stack (32,46), and a two-dimensional array of memory opening fill structures58located in the two-dimensional array of memory openings49and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel60; a two-dimensional array of drain contact via structures88electrically connected to a respective one of the vertical semiconductor channels60; and a two-dimensional array of layer contact via structures86electrically connected to a respective one of the electrically conductive layers46, a subset of which functions as word lines for the three-dimensional memory array.

Generally speaking, a memory die900comprises a memory array, memory-side metal interconnect structures980, and memory-side bonding pads988embedded within memory-side dielectric material layers960. The memory die900comprises a memory device, which may comprise a three-dimensional memory array including an alternating stack of insulating layers32and electrically conductive layers46, and further comprises a two-dimensional array of NAND strings (e.g., the memory opening fill structures58) vertically extending through the alternating stack (32,46). In one embodiment, the electrically conductive layers46comprise word lines of the two-dimensional array of NAND strings.

Referring toFIG.16, a logic die700is provided. The logic die700comprises a peripheral circuit720that is formed on a logic-side substrate709. According to an aspect of the present disclosure, the peripheral circuit720can be configured to control operation of the memory array within the memory die900. For example, the peripheral circuit720may comprise word line driver regions, bit line driver regions, sense amplifier regions, input/output buffer regions, etc. Logic-side metal interconnect structures780embedded within logic-side dielectric material layers760can be formed over the peripheral circuit720. The logic die700comprises logic-side bonding pads788embedded within logic-side dielectric material layers760.

Referring toFIG.17, a bonded assembly can be formed by bonding the logic die700with the memory die900. The logic die700can be attached to the memory die900, for example, by bonding the logic-side bonding pads788to the memory-side bonding pads988. The bonding between the memory die900and the logic die700may be performed employing a wafer-to-wafer bonding process in which a two-dimensional array of memory dies900is bonded to a two-dimensional array of logic dies700, by a die-to-bonding process, or by a die-to-die bonding process. The logic-side bonding pads788within each logic die700can be bonded to the memory-side bonding pads988within a respective memory die900.

The logic die700can be attached to the memory die900, for example, by bonding the logic-side bonding pads788to the memory-side bonding pads988. The bonding between the memory die900and the logic die700may be performed employing a wafer-to-wafer bonding process in which a two-dimensional array of memory dies900is bonded to a two-dimensional array of logic dies700, by a die-to-bonding process, or by a die-to-die bonding process. The logic-side bonding pads788within each logic die700can be bonded to the memory-side bonding pads988within a respective memory die900.

Referring toFIG.18, the carrier substrate9can be optionally removed, for example, by grinding, polishing, cleaving, an isotropic etch process, and/or an anisotropic etch process. If a polishing process such as a chemical mechanical polishing process is employed to remove the carrier substrate9, the stopper insulating layer106may be subsequently employed as a polishing stopper material layer. If an etch process such as a wet etch process is employed to remove the carrier substrate9, the stopper insulating layer106may be subsequently employed as an etch stop material layer.

Referring to all drawings and according to the first, second and third embodiments of the present disclosure, a memory device comprises: an alternating stack (32,46) of insulating layers32and electrically conductive layers46; memory openings49vertically extending through the alternating stack, wherein a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle; and memory opening fill structures58located in the memory openings, wherein each of the memory opening fill structures comprises a vertical semiconductor channel60and a vertical stack of memory elements (e.g., portions of the memory film50).

In one embodiment, the non-equilateral triangle comprises a scalene triangle.

In one embodiment, the memory openings49are arranged as multiple rows of memory openings. Each row of the multiple rows comprises a respective one-dimensional periodic array of memory openings49having a uniform pitch p along a first horizontal direction hd1, and the multiple rows are laterally spaced apart from each other along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1, wherein the multiple rows comprise, upon sequentially numbering with integers beginning with 1 along the second horizontal direction hd2, odd-numbered rows and even-numbered rows, and wherein, for each first vertical axis VA1passing through a geometrical center of a respective memory opening49in any odd-numbered row, a second vertical axis VA2passing through a geometrical center of a most proximal memory opening49within a most proximal odd-numbered row is laterally offset from the first vertical axis VA1along the first horizontal direction hd1by a first lateral offset distance Δ that is greater than 0 and is less than one half of the uniform pitch p.

In one embodiment, for each first vertical axis VA1passing through the geometrical center of the respective memory opening49in any odd-numbered row, a third vertical axis VA3passing through a geometrical center of a most proximal memory opening49within a most proximal even-numbered row is laterally offset from the first vertical axis VA1along the first horizontal direction hd1by a second lateral offset distance (p−Δ)/2−η that is greater than 0 and is less than (p−Δ)/2. In one embodiment, a difference between said (p−Δ)/2 and the second lateral offset distance (p−Δ)/2−η is a lateral shift distance η that is greater than 0 and is less than Δ/2.

In one embodiment, for each first vertical axis VA1passing through the geometrical center of the respective memory opening49in any odd-numbered row, a third vertical axis VA3passing through a geometrical center of a most proximal memory opening49within a most proximal even-numbered row is laterally offset from the first vertical axis VA1along the first horizontal direction hd1by a second lateral offset distance that equals (p−Δ)/2.

In one embodiment, for each first vertical axis VA1passing through the geometrical center of the respective memory opening49in any odd-numbered row, a planar vertical plane that passes through the first vertical axis VA1and is parallel to the second horizontal direction hd2does not pass through a geometrical center of any memory opening49within any nearest-neighboring row of memory openings49or within any second-nearest-neighboring row of memory openings49.

In one embodiment, a first vertical plane VP1passing through a geometrical center of a memory opening49within an odd-numbered row of memory openings49and passing through a geometrical center of a memory opening49within a nearest-neighboring odd-numbered row of memory openings49is at a first angle (π/3−α) with respective to the first horizontal direction hd1, wherein the first angle (π/3−α) is less than π/3 and is greater than arctan(√{square root over (3)}/(1.5)). In one embodiment, a second vertical plane VP2passing through the geometrical center of the memory opening49within the odd-numbered row of memory openings49and passing through a geometrical center of another memory opening49within the nearest-neighboring odd-numbered row of memory openings49is at a second angle (π/3+β) with respective to the first horizontal direction hd1, wherein the second angle (π/3+β) is greater than π/3 and is less than arctan(√{square root over (3)}/(1.5)). In one embodiment, a third vertical plane VP3passing through the geometrical center of the memory opening49within the odd-numbered row of memory openings49and passing through a geometrical center of a memory opening49a nearest-neighboring even-numbered row of memory openings49is at a third angle (π/3+γ) with respective to the first horizontal direction hd1, wherein the third angle (π/3+γ) is greater than the second angle (π/3+β).

In the first and second embodiments, each of the memory openings49has a respective circular horizontal cross-sectional shape. In the third embodiment, each of the memory openings49respective elongated horizontal cross-sectional shape having a respective major axis and a respective a minor axis. The major axes of the memory openings extend in a nearest neighbor memory opening direction.

According to the third and fourth embodiments, a memory device comprises: an alternating stack (32,46) of insulating layers32and electrically conductive layers46; memory openings49vertically extending through the alternating stack, wherein each of the memory openings49has a respective elongated horizontal cross-sectional shape having a respective a major axis and a respective minor axis, and the major axes of the memory openings extend in a nearest neighbor memory opening direction; and memory opening fill structures58located in the memory openings, wherein each of the memory opening fill structures comprises a vertical semiconductor channel60and a vertical stack of memory elements (e.g., portions of the memory film50).

In one embodiment, the memory openings49are arranged as multiple rows of memory openings. Each row of the multiple rows comprises a respective one-dimensional periodic array of memory openings49having a uniform pitch p along a first horizontal direction hd1, and the multiple rows are laterally spaced from each other along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1, and the major axes of the memory openings49are parallel to each other, and are at a non-zero and non-orthogonal angle with respect to the first horizontal direction hd1.

In one embodiment, the multiple rows comprise, upon sequentially numbering with integers beginning with 1 along the second horizontal direction hd2, odd-numbered rows and even-numbered rows; and each pattern of memory openings49in any odd-numbered row is periodically repeated in every other odd-numbered row along the second horizontal direction hd2with a periodicity that equals a center-to-center distance between neighboring pairs of odd-numbered rows within the multiple rows.

In one embodiment, the multiple rows comprise, upon sequentially numbering with integers beginning with 1 along the second horizontal direction hd2, odd-numbered rows and even-numbered rows; and for each first vertical axis VA1passing through a geometrical center of a respective memory opening49in any odd-numbered row, a second vertical axis VA2passing through a geometrical center of a most proximal memory opening49within a most proximal odd-numbered row is laterally offset from the first vertical axis VA1along the first horizontal direction hd1by a first lateral offset distance Δ that is greater than 0 and is less than one half of the uniform pitch p. In one embodiment, the non-zero and non-orthogonal angle is greater than p/3 and is less than arctan(2√{square root over (3)}).

In the third embodiment, a smallest unit shape of three nearest neighbor memory openings is a scalene triangle. In the fourth embodiment, a smallest unit shape of three nearest neighbor memory openings is an equilateral triangle.