Reference voltage generation circuit, drive device, print head, and image forming apparatus

A reference voltage generation circuit includes a first current-mirror circuit including a first MOS transistor connected to a first power source and a second MOS transistor of the first conductive type connected to the first power source; a second current-mirror circuit including a third MOS transistor and a fourth MOS transistor; a first resistor connected to the first node; a first bipolar transistor having a collector connected to the first resistor, an emitter connected to a second power source, and a base connected to the first node; a second bipolar transistor having a collector connected to the second node, an emitter connected to the second power source, and a base connected to the first bipolar transistor; a fifth MOS transistor connected between the first power source and an output terminal; and a third resistor connected between the output terminal and the second power source.

BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT

The present invention relates to a reference voltage generation circuit for generating a reference voltage to selectively and cyclically drive a group of driven elements such as, for example, an array of light emitting elements disposed in an electro-photography printer, an array of heating resistors disposed in a thermal printer, and an array of display units disposed in a display device. The present invention also relates to a drive device including the reference voltage generation circuit; a print head including the drive circuit; and an image forming apparatus including the print head.

In a conventional image forming apparatus such as an electro-photography printer, a plurality of light emitting elements is arranged to form an exposure device. The light emitting element includes an organic electro luminescence element (referred to as an organic EL) and a light emitting thyristor, in addition to a light emitting diode (referred to as LED).

In general, the light emitting element as the driven element exhibits temperature dependence, and a luminescence output thereof tends to decrease with an increase in a temperature. In the conventional image forming apparatus such as the electro-photography printer, when the luminescence output of the light emitting element decreases, a print density varies, thereby causing a printing problem. To this end, it is configured such that a drive current for driving the light emitting element increases, thereby making it possible to compensate the decrease in the luminescence output of the light emitting element due to the increase in the temperature when the light emitting element is driven.

In the configuration, a drive device is provided with a reference voltage Vref, so that the drive current of the light emitting element is set reversely proportional to the reference voltage Vref. Further, the reference voltage Vref is provided with a positive temperature coefficient, so that is it possible to compensate the decrease in the luminescence output according to the temperature. Patent Reference has disclosed a conventional reference voltage generation circuit for generating an output voltage as the reference voltage Vref reversely proportional to the absolute temperature.

When the drive device, the print head, and the image forming apparatus are provided with the conventional reference voltage generation circuit disclosed in Patent Reference, there have been the following problems.

In the print head, a large number of the light emitting elements are arranged. Accordingly, it is necessary to drive a large number of the light emitting elements. As a result, it is necessary to generate a large power source current for driving the light emitting elements, thereby causing a large variance in a power source voltage. Even when the light emitting elements are driven and the power source voltage drops significantly, it is still necessary to maintain a luminescence output of the light emitting elements at a specific level. To this end, it is necessary to design the drive device and a peripheral circuit thereof such that an influence of the large variance in the power source voltage is minimized.

In the conventional reference voltage generation circuit disclosed in Patent Reference, a pair of bipolar transistors is provided for detecting a temperature. The bipolar transistors have a characteristic in which a difference in voltages between a base and an emitter of the bipolar transistors varies according to a temperature. Accordingly, the conventional reference voltage generation circuit is configured such that the difference in the voltages is output as the reference voltage. When the power voltage decreases, the reference voltage tends to decrease. As a result, the drive current varies, thereby causing a variance in a print density.

In view of the problems described above, an object of the present invention is to provide a reference voltage generation circuit capable of solving the problems of the conventional reference voltage generation circuit. A further object of the present invention is to provide a drive device including the reference voltage generation circuit, a print head including the drive circuit, and an image forming apparatus including the print head.

SUMMARY OF THE INVENTION

In order to attain the objects described above, according to a first aspect of the present invention, a reference voltage generation circuit includes a first current-mirror circuit including a first MOS transistor of a first conductive type connected to a first power source and a second MOS transistor of the first conductive type connected to the first power source; and a second current-mirror circuit including a third MOS transistor of a second conductive type and a fourth MOS transistor of the second conductive type. Further, the second current-mirror circuit is disposed between the first current-mirror circuit, and a first node and a second node, and is vertically connected to the first current-mirror circuit.

According to the first aspect of the present invention, the reference voltage generation circuit further includes a first resistor having one end portion connected to the first node; a first bipolar transistor having a collector connected to the other end portion of the first resistor, an emitter connected to a second power source having a potential different from that of the first power source, and a base connected to the first node; a second bipolar transistor having a collector directly connected to the second node or connected to the second node through a second resistor, an emitter connected to the second power source, and a base connected to the collector of the first bipolar transistor; a fifth MOS transistor connected between the first power source and an output terminal for outputting a reference voltage so that a conductive state of the fifth MOS transistor is controlled according to an output voltage of the first current-mirror circuit; and a third resistor connected in series between the output terminal and the second power source.

According to a second aspect of the present invention, the reference voltage generation circuit in the first aspect of the present invention may further include a sixth MOS transistor of the second conductive type. The sixth MOS transistor is connected between the fifth MOS transistor and the output terminal through a diode connection.

According to a third aspect of the present invention, the reference voltage generation circuit in the first aspect of the present invention may further include a third current-mirror circuit including a seventh MOS transistor of the first conductive type connected to the first power source and an eighth MOS transistor of the first conductive type connected to the first power source; and a fourth current-mirror circuit including a ninth MOS transistor of the second conductive type and a tenth MOS transistor of the second conductive type. The second current-mirror circuit is disposed between the third current-mirror circuit, and a third node and a fourth node, and is vertically connected to the third current-mirror circuit.

According to the third aspect of the present invention, the reference voltage generation circuit in the first aspect of the present invention may further include a third bipolar transistor having a collector and a base connected to the third node and an emitter connected to the second power source; a fourth resistor connected in series between the fourth node and the second power source; an eleventh MOS transistor connected between the first power source and a fifth node so that a conductive state of the eleventh MOS transistor is controlled according to an output voltage of the third current-mirror circuit; and a fifth current-mirror circuit including a twelfth MOS transistor of the second conductive type disposed between the fifth node and the output terminal and connected in series to the eleventh MOS transistor, and a thirteenth MOS transistor of the second conductive type connected in parallel to the third resistor.

According to a fourth aspect of the present invention, the reference voltage generation circuit in the third aspect of the present invention may further include a fourteenth MOS transistor connected between the fifth MOS transistor and the output terminal through a diode connection, and a fifteenth MOS transistor connected between the eleventh MOS transistor and the fifth node through a diode connection.

According to a fifth aspect of the present invention, a drive device may include the reference voltage generation circuit in one of the first aspect to the fourth aspect of the present invention; and a control voltage generation circuit for receiving a reference voltage output from the reference voltage generation circuit to generate a control voltage according to the reference voltage.

According to the fifth aspect of the present invention, the drive device may further include a logic circuit having a power source terminal for receiving a power source voltage output from the first power source, and a ground terminal for receiving the control voltage. The logic circuit is provided for receiving a strobe signal and data, so that the logic circuit controls output of the data according to the strobe signal, and outputs a voltage with a high level substantially equal to the power source voltage or a voltage with a low level substantially equal to the control voltage. Further, the drive device may include a drive circuit for receiving the power source voltage, and supplying a drive current to a driven element according to an output voltage of the logic circuit.

According to a sixth aspect of the present invention, a print head may include the drive device in the fifth aspect of the present invention and a light emitting element array for emitting light according to the drive current. In the light emitting element array, a plurality of light emitting elements is arranged as the driven element.

According to a seventh aspect of the present invention, an image forming apparatus may include the print head in the fifth aspect of the present invention, so that the print head exposes to form an image on a recording medium.

In the reference voltage generation circuit in the first aspect and the second aspect of the present invention, a current-mirror circuit portion is formed of the first current-mirror circuit and the second current-mirror circuit, and is provided for driving the first bipolar transistor and the second bipolar transistor. Accordingly, it is possible to provide the first node and the second node with a substantially equal potential. As a result, even when the power voltage of the first power source varies, it is possible to minimize a variance in a collector potential of the second bipolar transistor, thereby reducing a variance in the reference voltage generated from the reference voltage generation circuit to a minimum level.

In the reference voltage generation circuit in the third aspect and the fourth aspect of the present invention, in addition to the configuration of the reference voltage generation circuit in the first aspect and the second aspect of the present invention, there are provided the third current-mirror circuit, the fourth current-mirror circuit, and the fifth current-mirror circuit. Accordingly, the reference voltage is generated substantially proportional to a voltage between the base and the emitter of the first bipolar transistor and the second bipolar transistor.

Further, in the reference voltage generation circuit in the third aspect and the fourth aspect of the present invention, the reference voltage is subtracted from the reference voltage generated in the reference voltage generation circuit in the first aspect and the second aspect of the present invention. Accordingly, it is possible to generate the reference voltage with a large temperature coefficient, thereby generating the reference voltage at a desired level. As a result, it is possible to set the temperature coefficient of the reference voltage at a desired level. Further, it is possible to set a voltage value at a desired level independently from the temperature coefficient. Further, similar to the first aspect and the second aspect of the present invention, even when the power voltage of the first power source varies, it is possible to reduce the variance in the reference voltage generated from the reference voltage generation circuit to a minimum level.

In the fifth aspect and the sixth aspect of the present invention, the drive device and the print head include the reference voltage generation circuit in one of the first aspect to the fourth aspect of the present invention. Accordingly, it is possible to stably drive the driven element without being subject to an influence of the variance in the power source voltage or the temperature.

In the seventh aspect of the present invention, the image forming apparatus includes the print head having the reference voltage generation circuit in one of the first aspect to the fourth aspect of the present invention. Accordingly, it is possible to provide the image forming apparatus with high quality, excellent space efficiency, and excellent light output efficiency.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereunder, preferred embodiments of the present invention will be explained with reference to the accompanying drawings. Similar components in the drawings are designated with the same reference numerals. It is noted that the drawings are presented only for an explanation purpose, and the present invention is not limited thereto.

First Embodiment

A first embodiment of the present invention will be explained.FIG. 2is a schematic sectional view showing a configuration of an image forming apparatus1according to the first embodiment of the present invention.

In the embodiment, the image forming apparatus1is an electro-photography type color printer. In the electro-photography type color printer, print heads13using a light emitting element (for example, an LED) as a driven element are disposed.

As shown inFIG. 2, the image forming apparatus1includes four process units10-1to10-4for forming images in colors of black (K), yellow (Y), magenta (M), and cyan (C). The process units10-1to10-4are arranged from an upstream side in this order along a transportation path of a recording medium20(for example, a sheet). The process units10-1to10-4have an identical internal configuration, and an internal configuration of the process unit10-3for magenta will be explained in the following description as an example.

In the embodiment, a photosensitive member (for example, a photosensitive drum11) as an image supporting member is disposed in the process unit10-3to be freely rotatable in an arrow direction inFIG. 2. There are provided around the photosensitive drum11in this order a charging device12for supplying electrons and charging a surface of the photosensitive drum11and an exposure device (for example, the print head13) for selectively irradiating light on the surface of the photosensitive drum11to form a static latent image thereon.

In the embodiment, the process unit10-3further includes a developing device14for attaching toner in magenta (a specific color) to the surface of the photosensitive drum11with the static latent image formed thereon, so that a visualized image is formed on the photosensitive drum11. Further, the process unit10-3includes a cleaning device15for removing remaining toner after the visualized image of toner on the photosensitive drum11is transferred to the recording medium20. Each of the components described above includes a drum and/or a roller, and a drive source (not shown) transmits a drive force through a gear and the like to rotate the drum and/or the roller.

In the embodiment, a sheet cassette21is disposed at a lower portion of the image forming apparatus1for storing the recording medium20in a stacked state. A hopping roller22is disposed above the sheet cassette21for separating and transporting the recording medium20one by one. A pinch roller23and a transportation roller25are disposed on a downstream side of the hopping roller22in a transportation direction of the recording medium20for sandwiching and transporting the recording medium20. Further, a pinch roller24and a register roller26are disposed on the downstream side of the hopping roller22in the transportation direction of the recording medium20for correcting a skew of the recording medium20and transporting the recording medium20to the process unit10-1. A drive source (not shown) transmits a drive force through a gear and the like to rotate the transportation roller25and the register roller26.

In the embodiment, a transfer device27is disposed at a position to face the photosensitive drum11in each of the process units10-1to10-4. The transfer device27is formed of a semi-conductive rubber and the like. A voltage is applied to the transfer device27. Accordingly, a potential difference is created between a surface potential of the photosensitive drum11and a surface potential of the transfer device27, so that the visualized image of toner attached to the photosensitive drum11is transferred to the recording medium20.

In the embodiment, the image forming apparatus1further includes a fixing device28on the downstream side of the process unit10-4. The fixing device28includes a heating roller with a heater disposed therein and a backup roller, so that the fixing device28heats and presses toner transferred to the recording medium20, so that the visualized image is fixed to the recording medium20. Further, discharge rollers29and30, pinch rollers31and32of a discharge portion, and a sheet stacker portion33are disposed on the downstream side of the fixing device28.

After the recording medium20is discharged from the fixing device28, the discharge rollers29and30and the pinch rollers31and32of the discharge portion sandwich and transport the recording medium20to the sheet stacker portion33. A drive source (not shown) transmits a drive force through a gear and the like to rotate the rollers in the fixing device28, the discharge rollers29and30, and the pinch rollers31and32of the discharge portion.

An operation of the image forming apparatus1will be explained next. First, the hopping roller22separates and transports the recording medium20stored in the sheet cassette21in the stacked state from the upper most position one by one. Then, the transportation roller25, the register roller26, and the pinch rollers23and24sandwich and transport the recording medium20between the photosensitive drum11of the process unit10-1and the transfer device27.

In the next step, the photosensitive drum11and the transfer device27sandwich the recording medium20, so that a toner image is transferred to a recording surface of the recording medium20. At the same time, the photosensitive drum11rotates to transport the recording medium20. Similarly, the recording medium20sequentially passes through the process units10-2to10-4. During the process, the developing device14develops the static latent image formed with the print head13to form the toner image in each color, and the toner image is sequentially transferred and overlapped on the recording surface of the recording medium20.

After the toner image in each color is sequentially transferred and overlapped on the recording surface of the recording medium20, the fixing device28fixes the toner image to the recording medium20. Then, the discharge rollers29and30and the pinch rollers31and32sandwich the recording medium20, so that the recording medium20is discharged on the sheet stacker portion33outside the image forming apparatus1. Through the process described above, a color image is formed on the recording medium20.

A control system of the image forming apparatus1will be explained next.FIG. 3is a block diagram showing a configuration of the control system of the image forming apparatus1according to the first embodiment of the present invention.

As shown inFIG. 3, the control system of the image forming apparatus1includes a print control unit40. The print control unit40is formed of a microprocessor; a read-only memory (referred to as an ROM); a random access memory (referred to as an RAM); an input-output port for inputting and outputting a signal; a timer; and the likes. The print control unit40is provided for performing a sequence control of an entire portion of the image forming apparatus1and a printing operation according to a control signal SG1, a video signal SG2(in which dot map data are arranged one-dimensionally), and the likes from an image processing unit (not shown).

As shown inFIG. 3, the print control unit40is connected to the print head13in each of the process units10-1to10-4; a heater28aof the fixing device28; drivers41and43; a sheet inlet sensor45; a sheet discharge outlet sensor46, a sheet remaining amount sensor47; a sheet size sensor48; a fixing device temperature sensor49; a charging high voltage power source50; a transfer high voltage power source51; and the likes. The driver41is connected to a developing transfer process motor42(PM). The driver42is connected to a sheet transportation motor44(PM). The charging high voltage power source50is connected to the developing device14. The transfer high voltage power source51is connected to the transfer device27.

An operation of the control system of the image forming apparatus1will be explained next. When the print control unit40receives a print direction along with the control signal SG1from the image processing unit (not shown), the print control unit40first detects whether the heater28adisposed in the fixing device28is within an operable temperature range using the fixing device temperature sensor49. When the heater28aof the fixing device28is not within the operable temperature range, the print control unit40energizes the heater28ato heat the fixing device28up to an operable temperature.

In the next step, the print control unit40controls the developing transfer process motor42to rotate through the driver41. At the same time, the print control unit40turns on the charging high voltage power source50with a charge signal SGC, thereby charging the developing device14.

In the next step, the sheet remaining amount sensor47and the sheet size sensor48detects the sheet20and a size thereof, and the sheet20is transported. The sheet supply motor44is connected to a planetary gear mechanism (not shown), so that the sheet supply motor44is capable of rotating in two directions through the driver43. Accordingly, when the sheet supply motor44rotates in a specific direction, it is possible to selectively drive the transportation roller25or other different rollers in the image forming apparatus1.

In the next step, each time the printing operation starts for printing one page, the print control unit40controls the sheet supply motor44to rotate in a reverse direction to transport the sheet20for a specific distance until the sheet inlet sensor45detects the sheet20. Then, the print control unit40controls the sheet supply motor44to rotate in a forward direction to transport the sheet20into a printing mechanism in the image forming apparatus1.

When the sheet20reaches a printable position, the print control unit40sends a timing signal SG3(including a main scanning synchronization signal and a sub scanning synchronization signal) to the image processing unit (not shown), and the print control unit40receives the video signal SG2from the image processing unit (not shown). The image processing unit (not shown) edits the video signal SG2per page. When the print control unit40receives the video signal SG2, the print control unit40sends the video signal SG2as a print data HD-DATA to each of the print heads13. Each of the print heads13is formed of a plurality of LEDs arranged therein each for printing one dot (pixel).

When the print control unit40receives the video signal SG2for one line, the print control unit40sends a latch signal HD-LOAD to each of the print heads13, so that the print data signal HD-DATA is stored in each of the print heads13. Note that the print control unit40is capable of printing the print data HD-DATA stored in each of the print heads13while the print control unit40receives a next video signal SG2from the image processing unit (not shown).

In the embodiment, a clock signal HD-CLK (referred to as a clock) is transmitted to each of the print heads13for sending the print data HD-DATA to each of the print heads13. Further, a drive on off instruction signal HD-STB-N (for example, a strobe signal) is also transmitted to each of the print heads13. In the drive on off instruction signal HD-STB-N, a symbol “-N” represents a negative logic signal.

In the embodiment, the video signal SG2is sent and received per print line. Each of the print heads13irradiates light on the photosensitive drum11charged with a negative potential. Accordingly, information to be printed is converted to the static latent image on the photosensitive drum11as a dot with an increased potential. In the developing device14, toner charged with a negative potential is attracted to each dot through an electric attraction force, thereby forming and developing the toner image.

In the next step, the toner image formed on the photosensitive drum11is transported to the transfer device27. The transfer high voltage power source51is turned on and becomes a negative potential with a transfer signal SG4, so that the transfer device27transfers the toner image to the sheet20passing between the photosensitive drum11and the transfer device27.

After the toner image is transferred to the sheet20, the sheet20abuts against the fixing device28with the heater28adisposed therein, and is transported further, thereby fixing the toner image to the sheet20through heat of the fixing device28. After the toner image is fixed to the sheet20, the sheet20is transported further, and is discharged from the printing mechanism of the image forming apparatus1to outside the image forming apparatus1after passing through the sheet discharge outlet sensor46.

In the embodiment, the print control unit40applies a voltage from the transfer high voltage power source51to the transfer device27only when the sheet20passes through the transfer device27according to detections of the sheet size sensor48and the sheet inlet sensor45. After the printing operation is performed and the sheet20passes through the sheet discharge outlet sensor46, the print control unit40stops applying the voltage from the charging high voltage power source50to the developing device14, and stops the developing transfer process motor42. Afterward, the printing operation described above is repeated.

A configuration of the print head13will be explained next.FIG. 4is a block diagram showing a configuration of the print head13of the image forming apparatus1according to the first embodiment of the present invention.

In the following description, as an example, the print head13is capable of printing on a sheet with A-4 size at a resolution of 600 dots per one inch.

In the embodiment, the print head13includes a print circuit board (not shown). A reference voltage generation circuit60, a plurality of driver monolithic integrated circuits (referred to as driver ICs)100(equal to100-1to100-n, where n is equal to, for example, 26), and a plurality of light emitting element arrays200(equal to200-1to200-n, where n is equal to 26) are arranged on the print circuit board. The light emitting element arrays200and the driver ICs100for driving the light emitting element arrays200are arranged to face each other. It is noted that the reference voltage generation circuit60and the driver ICs100-1to100-n constitute a drive device of the image forming apparatus1.

In the embodiment, the reference voltage generation circuit60is provided for generating a reference voltage Vref according to a potential of a first power source (for example, a power source voltage VDD). An output terminal of the reference voltage generation circuit60is connected to the driver ICs100. An output terminal of each of the driver ICs100is connected to each of the light emitting element arrays200.

In the embodiment, a plurality (for example, 192) of LEDs is arranged linearly in each of the light emitting element arrays200. Accordingly, a total number of the LEDs is 4,992 (dots). The driver ICs100for driving the light emitting element arrays200are formed of an identical circuit, and adjacent driver ICs (for example, the driver IC100-1and100-2) are connected in a cascade connection (a vertical connection). One single chip of the driver IC100is capable of driving 192 LEDs, and 26 chips of the driver ICs100are connected in the cascade connection for transmitting in a serial fashion the print data HD-DATA transmitted from the print control unit40when the printing operation is performed.

In the embodiment, each of the driver ICs100includes a control voltage generation circuit110for generating a control voltage; a shift resister120for receiving the clock signal HD-CLK transmitted from the print control unit40and performing shift transfer of the print data HD-DATA; a latch circuit130for latching an output signal of the shift resister120according to the latch signal HD-LOAD transmitted from the print control unit40; an inverter141for inverting the strobe signal HD-STB-N transmitted from the print control unit40; a logic circuit (for example, a negative logical product circuit or an NAND circuit142) for obtaining a logic of an output signal of the latch circuit130and the inverter141; and a drive circuit150for supplying a drive current to the light emitting element arrays200from the power source voltage VDD.

In the embodiment, the control voltage generation circuit110is provided for maintaining the drive current of the drive circuit150at a constant level. As shown inFIG. 4, the reference voltage generation circuit60is disposed in the print head13for commonly controlling the driver ICs100-1to100-n. Alternatively, the reference voltage generation circuit60may be provided in each of the driver ICs100.

A configuration of the reference voltage generation circuit60will be explained next.FIG. 1is a circuit diagram showing the configuration of the reference voltage generation circuit60of the image forming apparatus1according to the first embodiment of the present invention.

As shown inFIG. 1, the reference voltage generation circuit60includes a current-mirror circuit portion61. The current-mirror portion61includes a first current-mirror circuit and a second current-mirror circuit. The first current-mirror circuit is formed of a first MOS transistor of a first conductive type (for example, a P-channel MOS, or a PMOS61a) and a second MOS transistor of the first conductive type (for example, a PMOS61b). The second current-mirror circuit is formed of a third MOS transistor of a second conductive type (for example, an N-channel MOS, or an NMOS61c) and a fourth MOS transistor of the second conductive type (for example, an NMOS61d). The first current-mirror circuit is vertically connected to the second current-mirror circuit.

In the embodiment, a source of the PMOS61aof the first current-mirror circuit is connected to a power source VDD, and a gate of the PMOS61ais connected to a gate of the PMOS61bthrough a node N1. Accordingly, the PMOS61ais configured such that a drain current I1flows between the source and a drain thereof. Further, a source of the PMOS61bof the first current-mirror circuit is connected to the power source VDD, and a drain of the PMOS61bis connected to a gate thereof. Accordingly, the PMOS61bis configured to operate in a saturated state, and a drain current I2thereof flows between the source and the drain thereof.

In the embodiment, a drain and a gate of the NMOS61cof the second current-mirror circuit are connected to the drain of the PMOS61a, and a source of the NMOS61cis connected to a first node N3corresponding to a control side terminal of the current-mirror circuit portion61. Accordingly, the NMOS61cis configured to have a gate-source voltage Vgs1. Further, a drain of the NMOS61dof the second current-mirror circuit is connected to the drain of the PMOS61b, a gate of the NMOS61dis connected to the gate of the NMOS61cthrough a node N2, and a source of the NMOS61dis connected to a second node N4corresponding to a follower side terminal of the current-mirror circuit portion61. Accordingly, the NMOS61dis configured to have a gate-source voltage Vgs2.

As shown inFIG. 1, the reference voltage generation circuit60further includes a first bipolar transistor (for example, an NPN transistor or an NPNTR65) and a second bipolar transistor (for example, an NPN transistor or an NPNTR66). A collector of the NPN transistor65is connected to the first node N3through a first resistor62with a resistivity R1and a node N5. A base of the NPN transistor65is connected to the first node N3, and an emitter of the NPN transistor65is connected to a second power source (for example, a ground GND). Accordingly, the NPN transistor65is configured to have a base-emitter voltage Vbe1. A collector of the NPN transistor66is connected to the second node N4through a second resistor63with a resistivity R2. A base of the NPN transistor66is connected to the node N5on a side of the collector of the NPN transistor65, and an emitter of the NPN transistor66is connected to the ground GND. Accordingly, the NPN transistor66is configured to have a base-emitter voltage Vbe2.

As shown inFIG. 1, the reference voltage generation circuit60further includes a fifth MOS transistor (for example, a PMOS61e). A gate of the PMOS61eis connected to the drain of the PMOS61b, a source of the PMOS61eis connected to the power source VDD, and a drain of the PMOS61eis connected to an output terminal Vref for outputting the reference voltage Vref through a node N6. Accordingly, the PMOS61eis configured such that a drain current I3flows between the source and the drain og the PMOS61e. The node N6is connected to the ground GND through the third resistor63with the resistivity R2.

In the embodiment, the second resistor63is provided for making a collector potential of the NPN transistor66substantially equal to a collector potential of the NPN transistor65. When it is not necessary to match an operation point of the NPN transistor65to that of the NPN transistor66, the second resistor63may be omitted.

In the embodiment, the NPN transistor66is configured to have an emitter area larger than an emitter area of the NPN transistor65by N times (N>1). The PMOSs61a,61b, and61eare configured to have a substantially identical gate length. Further, the sources of the PMOSs61a,61b, and61eare connected to the gates thereof to have a substantially identical voltage between the gates and the sources, so that the PMOSs61a,61b, and61eare in a current-mirror relationship.

For a simple explanation, when the gates of the PMOSs61a,61b, and61ehave an identical width, the drain currents I1to I3thereof become identical. Accordingly, an output characteristic of the PMOSs61a,61b, and61ebecomes approximately a constant current characteristic. In order to improve the constant current characteristic, it is preferred that the PMOSs61a,61b, and61ehave a large gate length.

Similarly, when the gates of the NMOSs61cand61dhave an identical length and an identical width, it is possible to match an operation state of the NMOS61cto that of the NMOS61d. As described above, the drain current I1is equal to the drain current I2. Accordingly, the drain currents of the NMOSs61cand61dare identical, and the gate-source voltages Vgs1and Vgs2are identical. The gate of the NMOS61cis connected to the gate of the NMOS61dthrough the node N2, so that the gates of the NMOSs61cand61dhave an identical potential. Accordingly, it is possible to make a potential of the node N3equal to that of the node N4.

In the embodiment, it is possible to set the resistivity R1of the first resistor62equal to the resistivity R3of the second resistor63. When the NPN transistor65has a large current amplifying ratio, it is possible to ignore a base current relative to a collector current. Accordingly, the drain currents I1and I2are equal to currents flowing through the first resistor62and the second resistor63, and further are equal to collector currents of the NPN transistor65and the NPN transistor66. As described above, the drain current I1is equal to the drain current I2and the drain current I3. Accordingly, a voltage drop generated at both end portions of the first resistor62and the second resistor63becomes identical. Further, it is possible to make a collector potential of the NPN transistor65equal to that of the NPN transistor66.

In the reference voltage generation circuit60, for example, when the potential of the node N3drops, the potential of the node N2on the gate side drops according to a value of the gate-source voltage Vgs1of the NMOS61c. At this moment, the gate-source voltage Vgs2of the NMOS61dis equal to the gate-source voltage Vgs1of the NMOS61c. Accordingly, the potential of the node N4drops as well and becomes equal to the potential of the node N3. Similarly, when the potential of the node N3increases, the potential of the node N4increases.

In the embodiment, the node N3is connected to the base of the NPN transistor65. Accordingly, even when a value of the power source VDD fluctuates, a base potential of the NPN transistor65does not fluctuate to a large extent. As described above, the potential of the node N4is substantially equal to the potential of the node N3, and, the collector potential of the NPN transistor65is substantially equal to the collector potential of the NPN transistor66. Accordingly, even when the value of the power source VDD fluctuates, it is possible to minimize a variance in the collector potentials of the NPN transistor65and the NPN transistor66.

In order to clearly explain an effect of the reference voltage generation circuit60in the first embodiment, a comparative example will be explained. First, a configuration of a reference voltage generation circuit60A of the comparative example will be explained.

FIG. 5is a circuit diagram showing the configuration of the reference voltage generation circuit60A of the comparative example. Components of the reference voltage generation circuit60asimilar to those of the reference voltage generation circuit60are designated with the same reference numerals.

As shown inFIG. 5, instead of the current-mirror circuit portion61of the reference voltage generation circuit60in the first embodiment, the reference voltage generation circuit60A includes a current-mirror circuit61A having a configuration different from that of the current-mirror circuit portion61. Further, the second resistor63in the reference voltage generation circuit60is omitted. The current-mirror circuit61A is formed of the PMOS61aand the PMOS61bin the first embodiment. Other configurations of the comparative example are similar to those in the first embodiment.

When the reference voltage generation circuit60A of the comparative example is compared with the reference voltage generation circuit60in the first embodiment, in the reference voltage generation circuit60in the first embodiment, the NMOS61cand the NMOS61dare disposed between the PMOS61aand the PMOS61b, and the NPN transistor65and the NPN transistor66. Accordingly, it is possible to make the potential of the node N3substantially equal to the potential of the node N4. Further, the node N3on the source side of the NMOS61cis connected to the base of the NPN transistor65. Accordingly, even when the value of the power source voltage VDD fluctuates, the base potential of the NPN transistor65does not fluctuate to a large extent. Further, the potential of the node N3is substantially equal to the potential of the node N4. Accordingly, the collector potential of the NPN transistor65and the NPN transistor66does not fluctuate to a large extent as well.

On the other hand, in the reference voltage generation circuit60A of the comparative example, when the power source voltage VDD increases, the collector potential of the NPN transistor66follows and increases. Accordingly, the collector current of the NPN transistor66increases. This is known to be a phenomenon due to an insufficient early voltage of the NPN transistor66.

As well-known in the art, in a bipolar transistor operating in an active region, when a collector-emitter voltage Vce increases, a collector current Ic increases. In a graph representing a relationship between the collector-emitter voltage Vce and the collector current Ic, a tangential line of a characteristic curve in the active region crosses a horizontal axis of the graph, i.e., a collector-emitter voltage Vce axis, in a negative region. The early voltage corresponds to the collector-emitter voltage Vce (in the negative region) corresponding to the cross point.

For example, when the NPN transistor65and the NPN transistor66are disposed in a Complementary Metal Oxide Semiconductor transistor (referred to as CMOS), the NPN transistor65and the NPN transistor66are formed as a parasitic element. Accordingly, the NPN transistor65and the NPN transistor66are hardly provided with an ideal property, and it is difficult to increase the early voltage. As a result, the drain currents I1, I2, and I3flowing through the PMOS61a, the PMOS61b, and the PMOS61etend to be greater than a specific value, and the potential of the node N6tends to increase. Accordingly, the reference voltage Vref output from the output terminal VREF increases. Similarly, when the power source voltage VDD decreases, the reference voltage Vref decreases, thereby causing a problem.

As explained above, in the reference voltage generation circuit60A of the comparative example, it is difficult to obtain the satisfactory performance. To this end, in the reference voltage generation circuit60in the first embodiment, the NMOS61cand the NMOS61dare disposed between the PMOS61aand the PMOS61b, and the NPN transistor65and the NPN transistor66, thereby solving the problem of the comparative example.

A configuration of a drive device will be explained next.FIG. 6is a circuit diagram showing the configuration of the drive device according to the first embodiment of the present invention. The circuit diagram shown inFIG. 6represents the drive device for driving one dot (for example, one LED as the driven element).

As shown inFIG. 6, in the drive device in the first embodiment, a control voltage generation circuit110is connected to the output terminal VREF of the reference voltage generation circuit60. It is noted that one control voltage generation circuit110is provided for each of the driver ICs100.

In the embodiment, the drive device includes an operational amplifier (referred to as an operation amplifier111), a resistor112with a resistivity Rref, and a PMOS transistor113. It is noted that the operation amplifier111, the resistor112, and the PMOS transistor113constitute a feedback control circuit.

In the embodiment, an inversion terminal of the operation amplifier111is connected to the output terminal VREF and a non-inversion terminal of the operation amplifier111is connected to the ground GND through the resistor112. The non-inversion terminal of the operation amplifier111is further connected to a drain of the PMOS transistor113. An output terminal of the operation amplifier111is connected to a gate of the PMOS transistor113for outputting a control voltage Vcontrol. A source of the PMOS transistor113is connected to the power source VDD. The control voltage generation circuit110is configured such that a reference current Iref flowing through the resistor112, i.e., a current flowing between the source and the gate of the PMOS transistor113, is not dependent on the power source voltage VDD, and is determined only by the reference voltage Vref input to the control voltage generation circuit110and the resistivity Rref of the resistor112.

In the embodiment, the drive device further includes a latch circuit (referred to as an LT131) for one dot constituting the latch circuit130. The latch circuit131includes a terminal G for inputting the latch signal HD-LOAD, a data input terminal D for inputting the print data output from the control voltage generation circuit110, and a data output terminal Q. When the latch signal HD-LOAD is input, the print head131latches the print data output from the control voltage generation circuit110, and outputs the print data from the output terminal. An NAND circuit142is connected to the output terminal Q of the print head131and an output terminal of an inverter141for inverting the strobe signal HD-STB-N.

In the embodiment, a power source terminal of the NAND circuit142is connected to the power source VDD, and a ground terminal of the NAND circuit142is connected to the output terminal of the operation amplifier111. Accordingly, when an output potential of the NAND circuit142is at a high level (referred to as an H level), a potential substantially equal to the power source voltage VDD is output. When the output potential of the NAND circuit142is at a low level (referred to as an L level), a potential substantially equal to the control voltage Vcontrol is output.

Further, an output terminal of the NAND circuit142is connected to a gate of a drive element (for example, a PMOS151) for one dot constituting the drive circuit150. A source of the PMOS151is connected to the power source VDD. A drain of the PMOS151is connected to anode of an LED201for one dot in the light emitting element arrays200, and a cathode of the LED201is connected to the ground GND.

In the embodiment, the PMOS transistor113of the control voltage generation circuit110is configured such that a gate length of the PMOS transistor113is substantially equal to a gate length of the PMOS151and the like. In the control voltage generation circuit110, the operation amplifier111is provided for controlling such that a potential of the inversion terminal of the operation amplifier111becomes substantially equal to a potential of the non-inversion terminal of the operation amplifier111. Accordingly, the potential of the non-inversion terminal of the operation amplifier111becomes substantially equal to the reference voltage Vref thus input. As a result, the reference current flowing through the resistor112is given by the following equation:
Iref=Vref/Rref

In the embodiment, it is configured such that gate length of the PMOS transistor113is substantially equal to the gate length of the PMOS151and the like for driving the LED201. When the LED201is driven, the gate potential of the PMOS113becomes equal to the control voltage Vcont. Accordingly, the PMOS113and the PMOS151and the like for driving the LED201operate in a saturated region, and have a current-mirror relationship. Accordingly, the drive current of the LED201and the like is proportional to the reference current Iref, and the reference current I ref is proportional to the reference voltage Vref input from the output terminal VREF. As a result, it is possible to collectively adjust the drive current of the LED201according to the reference voltage Vref.

An operation of the print head13will be explained next.FIG. 7is a time chart showing the operation of the print head13of the image forming apparatus1according to the first embodiment of the present invention.

When a printing operation starts, the print control unit40shown inFIG. 3outputs one pulse of a timing signal SG3per print one line cycle, so that the pulse is transmitted to the image processing unit (not shown). With the timing signal SG3, the image processing unit generates a video signal SG2per an N−1 line, an N line, an N=1 line, . . . , so that the video signal SG2is transmitted to the print control unit40. At the same time, the print control unit40inputs the clock signal HD-CLK and the print data HD-DATA to the print head13.

In the embodiment, as an example, the print head13is capable of printing on a sheet with A-4 size at the resolution of 600 dots per one inch, and the total number of the LEDs201is 4,992 (dots). Accordingly, the total number of the pulses of the clock signal HD-CLK is 4,992. After 4,992 of the pulses are transmitted, the print control unit40generates a pulse of the latch signal HD-LOAD, and the latch circuit130latches the print data HD-DATA shift input to the shift resister120in the print head13.

In the next step, the print control unit40generates the strobe signal HD-STB-N with the L level per an N−1 line, an N line, an N=1 line, . . . . During an LED driving time t when the strobe signal HD-STB-N is at the L level, the LED201emits light. Accordingly, the print head13irradiates light on the photosensitive drum11shown inFIG. 2, thereby forming the static latent image thereon.

An operation of the reference voltage generation circuit60shown inFIG. 1will be quantitatively explained. First, the drain current I1flowing through the PMOS61ais determined. As well known in the art, there is a relationship between an emitter current Ie and a base-emitter voltage Vbe of a bipolar transistor represented with the following equation (1):
Ie≈Is×exp(qVbe/(kT))  (1)
where Is is a saturated current, i.e., a constant determined proportional to an element area of the bipolar transistor; exp ( ) is an exponent function; q is a charge of an electron (q=1.6×10−19C); k is the Boltzmann constant (k=1.38×10−23J/K); and T is an absolute temperature (=about 298 K at a room temperature 25° C.).

When the equation (1) is modified, it is possible to obtain the following equation (2):
Vbe=(kT/q)×ln(Ie/Is)  (2)
where ln( ) is a natural logarithmic function.

It is supposed that the NPN transistor65and the NPN transistor66have base-emitter voltages Veb1and Veb2, emitter currents Ie1and Ie2, and saturated currents Is1and Is2, respectively. Accordingly, with respect to the NPN transistor65and the NPN transistor66, the following equation (3) is established:
Vbe1=(kT/q)×ln(Ie1/Is1)
Vbe2=(kT/q)×ln(Ie2/Is2)  (3)

InFIG. 1, one end portion of the first resistor62with the resistivity R1has a potential equal to the base-emitter voltage Vbe1, and the other end portion of the first resistor62has a potential equal to the base-emitter voltage Vbe2. Accordingly, a voltage difference ΔVbe generated between the end portions of the first resistor62is given by the following equation (4):
ΔVbe=Vbe1−Vbe2  (4)

When the equation (3) is incorporated into the equation (4), the following equation (5) is obtained:
ΔVbe=(kT/q)×[ln(Ie1/Is1)−ln(Ie2/Is2)]  (5)

As described above, the ratio of the emitter area of the NPN transistor66relative to the emitter area of the NPN transistor65is set 1:N (N>1). Further, the saturated currents Is1and Is2are proportional to the element areas of the NPN transistor65and the NPN transistor66. Accordingly, the saturated current Is2is N times greater than the saturated current Is1(Is2=Is1×N). Further, the PMOSs61aand61bare in the current-mirror relationship. Accordingly, the drain current I1is equal to the drain current I2(I1=I2). As a result, the emitter current Ie1is substantially equal to the emitter current Ie2, and the following equation (6) is obtained:
ΔVbe=(kT/q)×ln(N)  (6)

In the embodiment, the drain current I1shown inFIG. 1is substantially equal to the current flowing through the first resistor62with the resistivity R1. Accordingly, the following equation (7) is obtained:
I1=ΔVbe/R1=(1/R1)×(kT/q)×ln(N)  (7)

Further, as explained above, the PMOSs61a,61b, and61eare in the current-mirror relationship, so that the drain currents I1, I2, and I3have an identical value (I1=I2=I3). Accordingly, the reference voltage Vref generated at the node N6on the side of the one end portion of the resistor64with the resistivity R2is given by the following equation (8):
Vref=I3×R2=(R2/R1)×(kT/q)×ln(N)  (8)

In the embodiment, the reference voltage Vref is proportional to the absolute temperature T, so that the reference voltage Vref has a positive temperature coefficient Tc. The temperature coefficient Tc is given by the following equation (9):

Accordingly, the temperature coefficient Tc of the reference voltage generation circuit60shown inFIG. 1is equal to 1/T (Tc=1/T), and becomes about +0.33%/° C. at a room temperature (about 25° C.).

A temperature characteristic of a luminescence output of the LED201as the driven element will be explained next.

For example, when the LED201is formed of a material such as AlGaAs, the luminescence output of the LED201has a characteristic decreasing at a rate of −0.25%/° C. with an increase in a temperature when the LED201is driven with a constant current. In order to compensate the temperature characteristic of the LED201, it is necessary to increase the drive current with the increase in the temperature. More specifically, it is necessary to increase the drive current with the temperature coefficient of about 0.25%/° C.

When the LED201is formed of a material such as GaAs, the temperature coefficient of the drive current becomes about 0.6%/° C. in order to compensate the temperature characteristic of the LED201. When the LED201is formed of a material such as AlGaInP, the temperature coefficient of the drive current becomes about 1.0%/° C. in order to compensate the temperature characteristic of the LED201.

As described above, depending on the material of the LED201or a luminescence wave length (a luminescence color), the temperature coefficient of the drive current tends to vary. In the reference voltage generation circuit60shown inFIG. 1, the temperature coefficient thereof becomes about +0.33%/° C., similar to the temperature coefficient of the LED201formed of AlGaAs. Accordingly, the reference voltage generation circuit60is preferably provided for driving the LED201.

A dependence of the power source voltage VDD in the reference voltage generation circuit60shown inFIG. 1will be explained next. As described above, in the reference voltage generation circuit60shown inFIG. 1, the NMOS61cand the NMOS61dare disposed between the PMOS61aand the PMOS61b, and the NPN transistor65and the NPN transistor66. Accordingly, it is possible to make the potential of the node N3substantially equal to the potential of the node N4. Further, the node N3on the source side of the NMOS61cis connected to the base of the NPN transistor65. Accordingly, even when the value of the power source voltage VDD fluctuates, the base potential of the NPN transistor65does not fluctuate to a large extent. Further, the potential of the node N3is substantially equal to the potential of the node N4. Accordingly, even when the value of the power source voltage VDD fluctuates, the collector potential of the NPN transistor65and the NPN transistor66does not fluctuate to a large extent as well. As a result, in the reference voltage generation circuit60in the first embodiment, even when the value of the power source voltage VDD fluctuates, it is possible to minimize the property variance associated with the fluctuation.

On the other hand, in the reference voltage generation circuit60A of the comparative example shown inFIG. 5, when the power source voltage VDD increases, the collector potential of the NPN transistor66follows the power source voltage VDD and increases. Accordingly, the collector current of the NPN transistor66increases. As a result, the drain currents I1to I3become larger than a specific level. Accordingly, the potential of the node N6increases, thereby increasing the reference voltage Vref.

FIGS. 8(a) and8(b) are graphs showing the power source voltage VDD dependence of the reference voltage Vref generated from the voltage generation circuit60A of the comparative example shown inFIG. 5.FIGS. 9(a) and9(b) are graphs showing the power source voltage VDD dependence of the reference voltage Vref generated from the voltage generation circuit60shown inFIG. 1according to the first embodiment of the present invention.

InFIGS. 8(a) and8(b) showing the characteristics of the reference voltage generation circuit60A of the comparative example,FIG. 8(a) is a graph showing a relationship between the reference voltage Vref and the power source voltage VDD. InFIG. 8(a), the horizontal axis represents the power source voltage VDD, and the vertical axis represents the reference voltage Vref thus generated. As shown inFIG. 8(a), in the characteristics of the reference voltage generation circuit60A of the comparative example, when the power source voltage VDD becomes about 1.2 V, the reference voltage Vref starts increasing. Further, the reference voltage Vref increases substantially linearly with the increase in the power source voltage VDD.

FIG. 8(b) is a graph corresponding toFIG. 8(a). InFIG. 8(b), the horizontal axis represents the power source voltage VDD, and the vertical axis represents a power source voltage VDD dependence coefficient (%/V). The power source voltage VDD dependence coefficient is converted from a change rate of the reference voltage Vref. As shown inFIG. 8(b), when the power source voltage VDD becomes about 5.0 V, the power source voltage VDD dependence coefficient of the reference voltage Vref reaches about 5%/V. Accordingly, when the power source voltage VDD fluctuates, the reference voltage Vref significantly fluctuates.

InFIGS. 9(a) and9(b) showing the characteristics of the reference voltage generation circuit60in the first embodiment,FIG. 9(a) is a graph showing a relationship between the reference voltage Vref and the power source voltage VDD. InFIG. 9(a), the horizontal axis represents the power source voltage VDD, and the vertical axis represents the reference voltage Vref thus generated. As shown inFIG. 9(a), in the characteristics of the reference voltage generation circuit60in the first embodiment, when the power source voltage VDD becomes about 2.0 V, the reference voltage Vref starts increasing. However, even when the power source voltage VDD increases further, the reference voltage Vref is maintained at a substantially same level.

FIG. 9(b) is a graph corresponding toFIG. 9(a). InFIG. 9(b), the horizontal axis represents the power source voltage VDD, and the vertical axis represents a power source voltage VDD dependence coefficient (%/V). The power source voltage VDD dependence coefficient is converted from a change rate of the reference voltage Vref. As shown inFIG. 9(b), when the power source voltage VDD becomes about 5.0 V, the power source voltage VDD dependence coefficient of the reference voltage Vref reaches only about 0.4%/V. Accordingly, when the power source voltage VDD fluctuates, the reference voltage Vref only fluctuates to a negligibly minimum level.

As described above, in the first embodiment, the reference voltage generation circuit60, the drive device, the print head13, and the image forming apparatus1are capable of providing the following effects.

As described above, in the reference voltage generation circuit60in the first embodiment, the current-mirror circuit formed of the NMOS61cand the NMOS61dis disposed on the side of driving the collector currents of the NPN transistor65and the NPN transistor66as a source follower circuit, thereby compensating the low early voltage of the NPN transistor65and the NPN transistor66for detecting the temperature. Accordingly, even when the power source voltage VDD fluctuates, it is possible to minimize the variance in the collector currents of the NPN transistor65and the NPN transistor66.

More specifically, in the reference voltage generation circuit60in the first embodiment, the current-mirror portion61includes the first current-mirror circuit and the second current-mirror circuit. The first current-mirror circuit is formed of the PMOS61aand the PMOS61b. The second current-mirror circuit is formed of the NMOS61cand the NMOS61d. The first current-mirror circuit is vertically connected to the second current-mirror circuit. Further, the current-mirror circuit portion61is provided for driving the NPN transistor65and the NPN transistor66.

Accordingly, it is possible to make the potential of the node N3substantially equal to the potential of the node N4. Accordingly, even when the value of the power source voltage VDD fluctuates, the base potential of the NPN transistor65does not fluctuate to a large extent. Further, the potential of the node N3is substantially equal to the potential of the node N4. Accordingly, the collector potential of the NPN transistor65and the NPN transistor66does not fluctuate to a large extent as well. As a result, it is possible to reduce the variance in the reference voltage Vref to a negligibly minimum level.

As described above, in the reference voltage generation circuit60in the first embodiment, it is possible to obtain the temperature coefficient of +0.33%/° C. Accordingly, when the reference voltage generation circuit60is provided for temperature compensation of the drive device of the LED201formed of a material such as AlGaAs, it is possible to provide the drive device with good temperature characteristics. Further, even when the value of the power source voltage VDD fluctuates, it is possible to reduce the variance in the reference voltage Vref generated from the reference voltage generation circuit60to a negligibly minimum level.

Further, in the image forming apparatus1in the first embodiment, the print head13is provided with the reference voltage generation circuit60. Accordingly, it is possible to provide the image forming apparatus1(such as a printer, a copier, a facsimile, a multi-function product, and the like) with high quality, high space efficiency, and high luminescence efficiency. Further, in addition to the image forming apparatus1, when the print head13is disposed in a monochrome image forming apparatus or a multicolor image forming apparatus, it is possible to obtain a similar effect. Especially, when the print head13is a full color image forming apparatus, in which it is necessary to dispose a large number of the print heads13as the exposure device, it is possible to obtain a further significant effect.

Second Embodiment

A second embodiment of the present invention will be explained next. It is possible to modify the reference voltage generation circuit60in the first embodiment through applying the similar technical concept.FIG. 10is a circuit diagram showing a configuration of a reference voltage generation circuit60B according to the second embodiment of the present invention. Components in the second embodiment similar to those in the first embodiment are designated with the same reference numerals.

As shown inFIG. 10, in the reference voltage generation circuit60B in the second embodiment, a sixth MOS transistor of the second conductive type (for example, an NMOS61f) is disposed through a diode connection between a node N7on a side of the drain of the PMOS61eand the node N6on the side of the output terminal VREF. More specifically, a drain and a gate of the NMOS61fare connected to the drain of the PMOS61ethrough the node N7. A source of the NMOS61fis connected to the output terminal VREF and the one end portion of the resistor64through the node N6. Accordingly, the NMOS61fhas a gate-source voltage Vgs3. Other configuration of the reference voltage generation circuit60B is similar to that of the reference voltage generation circuit60in the first embodiment.

Similar to the first embodiment, the second resistor63is provided for making the collector potential of the NPN transistor66substantially equal to the collector potential of the NPN transistor65. When it is not necessary to match an operation point of the NPN transistor65to that of the NPN transistor66, the second resistor63may be omitted.

Similar to the first embodiment, in the reference voltage generation circuit60B in the second embodiment, for a simple explanation, when the gates of the PMOSs61a,61b, and61ehave an identical width, the drain currents I1to I3thereof become identical. Accordingly, an output characteristic of the PMOSs61a,61b, and61ebecomes approximately the constant current characteristic. In order to improve the constant current characteristic, it is preferred that the PMOSs61a,61b, and61ehave a large gate length.

Similarly, when the gates of the NMOSs61cand61dhave an identical length and an identical width, it is possible to match an operation state of the NMOS61cto that of the NMOS61d. As described above, the drain currents I1to I3of the PMOSs61a,61b, and61eare identical. Accordingly, the drain currents of the NMOSs61c,61d, and61fare identical, and the gate-source voltages Vgs1, Vgs2, and Vgs3thereof are identical.

In the reference voltage generation circuit60B in the second embodiment, it is possible to obtain an effect similar to that in the reference voltage generation circuit60in the first embodiment. Further, the drain of the NMOS61fis connected to the gate thereof. Accordingly, the drain potential of the PMOS61econnected to the node N7on the side of the drain of the NMOS61fis greater than the potential of the node N6connected to the output terminal VREF by the gate-source voltage Vgs3. As a result, as compared with the reference voltage generation circuit60in the first embodiment without the NMOS61f, the drain potential of the PMOS61ebecomes closer to the drain potential of the PMOS61b. Accordingly, it is possible to match an operation state of the PMOS61ato that of the PMOS61band the PMOS61e, thereby making it possible to minimize a current variation between the drain currents I1, I2, and I3.

Third Embodiment

A third embodiment of the present invention will be explained next. In the third embodiment, the image forming apparatus1and the print head13have configurations similar to those of the image forming apparatus1and the print head13in the first embodiment. In the third embodiment, a reference voltage generation circuit60C disposed in a drive device has a configuration different from the reference voltage generation circuit60in the first embodiment. Accordingly, the reference voltage generation circuit60C will be explained.

FIG. 11is a circuit diagram showing a configuration of the reference voltage generation circuit60C according to the third embodiment of the present invention. Components of the reference voltage generation circuit60C similar to those of the reference voltage generation circuit60shown inFIG. 1are designated with the same reference numerals.

In the second embodiment, the reference voltage generation circuit60C is configured such that it is possible to set the temperature coefficient of the reference voltage Vref thus output at a greater level. More specifically, in addition to the configuration of the reference voltage generation circuit60in the first embodiment, the reference voltage generation circuit60C further includes a current-mirror circuit portion161; an eleventh MOS transistor of the first conductive type (for example, a PMOS161e); a third bipolar transistor (for example, a NPNTR162); a fourth resistor163with a resistivity R4; and a fifth current-mirror circuit164. As shown inFIG. 11, the current-mirror circuit portion161, the PMOS161e, the NPNTR162, the fourth resistor163, and the fifth current-mirror circuit164are disposed between the current-mirror circuit portion61, the first resistor62, the second resistor63, the NPN transistor65, and the NPN transistor66, and the PMOS61eand the resistor64.

In the embodiment, the current-mirror circuit portion161is connected between the power source VDD, and a third node N10and a fourth node N11. Further, the current-mirror circuit portion161has a configuration and characteristics similar to those of the current-mirror circuit portion61. More specifically, the current-mirror portion161includes a third current-mirror circuit and a fourth current-mirror circuit. The third current-mirror circuit is formed of a seventh MOS transistor of the first conductive type (for example, a PMOS161a) and an eighth MOS transistor of the first conductive type (for example, a PMOS161b). The fourth current-mirror circuit is formed of a ninth MOS transistor of the second conductive type (for example, an NMOS161c) and a tenth MOS transistor of the second conductive type (for example, an NMOS161d). The third current-mirror circuit is vertically connected to the fourth current-mirror circuit.

In the embodiment, a source of the PMOS161aof the third current-mirror circuit is connected to the power source VDD, and a gate of the PMOS161ais connected to a gate of the PMOS161bthrough a node N8. Accordingly, the PMOS161ais configured such that a drain current I4flows between the source and a drain thereof. Further, a source of the PMOS161bof the third current-mirror circuit is connected to the power source VDD, and a drain of the PMOS161bis connected to the gate thereof. Accordingly, the PMOS161bis configured to operate in a saturated state, and a drain current I5thereof flows between the source and the drain thereof.

In the embodiment, a drain and a gate of the NMOS161cof the fourth current-mirror circuit are connected to the drain of the PMOS161a, and a source of the NMOS161cis connected to a node N10corresponding to a control side terminal of the current-mirror circuit portion161. Accordingly, the NMOS161cis configured such that a source current I7flows through the node N10. Further, a drain of the NMOS161dof the fourth current-mirror circuit is connected to the drain of the PMOS161b, a gate of the NMOS161dis connected to the gate of the NMOS161cthrough a node N9, and a source of the NMOS161dis connected to a second node N11corresponding to a follower side terminal of the current-mirror circuit portion161. Accordingly, the NMOS161dis configured such that a source current I8flows through the node N11.

In the embodiment, a collector of the NPNTR162is connected to a base thereof, and an emitter of the NPNTR162is connected to the ground GND. The node N11is connected to the ground GND through the fourth resistor163with the resistivity R4.

In the embodiment, the drain of the PMOS161bis connected to a drain of the PMOS161e. A source of the PMOS161eis connected to the power source VDD, and a drain of the PMOS161eis connected to a fifth node N12on a control side. Accordingly, the PMOS161eis configured such that a drain current I6flows through the fifth node N12. The PMOSs161a,161b, and161eare configured to have a substantially identical gate length. Further, the sources of the PMOSs161a,161b, and161eare connected to the gates thereof to have a substantially identical voltage between the gates and the sources, so that the PMOSs161a,161b, and161eare in a current-mirror relationship.

As shown inFIG. 11, the reference voltage generation circuit60C includes the fifth current-mirror circuit164disposed between the node N12on the control side and the node N6on the follower side, and the ground GND. The fifth current-mirror circuit164is formed of a twelfth MOS transistor of the second conductive type (for example, an NMOS164a) and a thirteenth MOS transistor of the second conductive type (for example, an NMOS164b).

In the embodiment, a drain and a gate of the fifth current-mirror circuit164aof the fifth current-mirror circuit164are connected to the drain of the PMOS161e, and a source of the fifth current-mirror circuit164ais connected to the ground GND. Further, a drain of the fifth current-mirror circuit164bof the fifth current-mirror circuit164is connected to the output terminal VREF through the node N6on the follower side, and the drain of the PMOS61e. A gate of the fifth current-mirror circuit164bis connected to the gate of the PMOS161a, and a source of the fifth current-mirror circuit164bis connected to the ground GND.

Other configurations of the reference voltage generation circuit60C are similar to those of the reference voltage generation circuit60in the first embodiment. As described above, the second resistor63is provided for making the collector potential of the NPN transistor66substantially equal to the collector potential of the NPN transistor65. When it is not necessary to match the operation point of the NPN transistor65to that of the NPN transistor66, the second resistor63may be omitted.

For a simple explanation, in the current-mirror circuit portion161, when the gates of the PMOSs161a,161b, and161ehave an identical width, the drain currents I4to I6thereof become identical. Accordingly, an output characteristic of the PMOSs161a,161b, and161ebecomes approximately a constant current characteristic. In order to improve the constant current characteristic, it is preferred that the PMOSs161a,161b, and161ehave a large gate length.

Similarly, when the gates of the NMOSs161cand161dhave an identical length and an identical width, it is possible to match an operation state of the NMOS161cto that of the NMOS161d. As described above, the drain current I4is equal to the drain current I5. Accordingly, the drain currents of the NMOSs161cand161dare identical, and the gate-source voltages thereof are identical. Further, the drain current I4of the PMOS161ais equal to the source current I7of the NMOS161c, and the drain current I5of the PMOS161bis equal to the source current I8of the NMOS161d. Accordingly, the source current I7is equal to the source current I8.

As explained in the first embodiment, on the side of the current-mirror circuit portion61, the potential of the node N3is substantially equal to that of the node N4. Similarly, on the side of the current-mirror circuit portion161, the potential of the node N10is substantially equal to that of the node N11. The potential of the node N10is equal to the base-emitter voltage Vbe of the NPNTR162, and the node N11is connected to one end portion of the fourth resistor163with the resistivity R4. Accordingly, the source current I8of the NMOS161dis given by the following equation:
I8=Vbe/R4

As well known in the art, for example, the base-emitter voltage Vbe of the NPNTR162formed of a silicon material is typically about 0.6 V, and has a temperature dependence of −2 mV/° C. Accordingly, the temperature coefficient Tc of the base-emitter voltage Vbe is given by the following calculation:
Tc=−2×10−3/0.6=−0.33(%/° C.)

When the temperature coefficient of the fourth resistor163with the resistivity R4is negligible, the temperature coefficient of the source currents I7and I8also becomes −0.33%/° C.

As explained above, the currents I4to I8are identical, so that the temperature coefficient of the drain current I6of the PMOS161ealso becomes −0.33%/° C. The drain current I6flows into the node N12of the fifth current-mirror circuit164formed of the fifth current-mirror circuit164aand the fifth current-mirror circuit164b. Accordingly, a flow-in current inversely proportional to the drain current I6is generated in the node N6on the follower side of the fifth current-mirror circuit164. It is possible to arbitrarily set a ratio of currents flowing into the node N12on the control side and the node N6on the follower side of the fifth current-mirror circuit164through adjusting a size ratio of the fifth current-mirror circuit164aand the fifth current-mirror circuit164b.

An operation of the reference voltage generation circuit60C shown inFIG. 11will be explained.FIGS. 12(a) to12(d) are a circuit diagram and graphs showing the operation of the reference voltage generation circuit60C according to the third embodiment of the present invention.

More specifically,FIG. 12(a) is a circuit diagram showing a surrounding portion of the current-mirror circuit164of the reference voltage generation circuit60C shown inFIG. 11.FIG. 12(b) is a graph showing a relationship between a temperature and the current I3flowing in the surrounding portion of the current-mirror circuit164,FIG. 12(c) is a graph showing a relationship between a temperature and a current I3B flowing in the surrounding portion of the current-mirror circuit164, andFIG. 12(d) is a graph showing a relationship between a temperature and a current I3A flowing in the surrounding portion of the current-mirror circuit164.

As shown inFIG. 12(a), the PMOS61eand the PMOS161ehave the drain currents I3and I6, respectively. The current I3A flows in the resistor64with the resistivity R2, and the current I3B flows in the drain of the fifth current-mirror circuit164b.

FIGS. 12(b) to12(d) are the graphs showing changes in the currents I3, I3B, and I3A with the temperature. InFIG. 12(b), as explained above, the current I3has the characteristic proportional to the absolute temperature (T), and has the temperature coefficient of about 0.33%/° C. Further, as explained above, the drain current I6of the PMOS161ehas the characteristic decreasing with an increase in the temperature, and has the temperature coefficient of about −0.33%/° C. The drain current I6and the current I3B are in the current-mirror relationship. Accordingly, the current I3B also has the characteristic decreasing with an increase in the temperature, and has the temperature coefficient of about −0.33%/° C.

InFIG. 12(a), the current I3is equal to a sum of the current I3A and the current I3B (I3=I3A+I3B). Accordingly, the current I3A is equal to a difference between the current I3and the current I3B (I3A=I3−I3B). As a result, the characteristic line of the current I3A inFIG. 12(d) corresponds to a difference between the current I3shown inFIG. 12(b) and the current I3B shown inFIG. 12(c). In other words, the characteristic line of the current I3A inFIG. 12(d) has the temperature dependence greater than those of the current I3shown inFIG. 12(b) and the current I3B shown inFIG. 12(c).

The property described above will be explained quantitatively in more detail. For the simple explanation, the current I3is represented with I; the current I3A is represented with Ia; and the current I3B is represented with Ib. Further, the temperature coefficient of the current I is represented with αq; the temperature coefficient of the current Ib is represented with αc; the temperature coefficient of the current Ia is represented with Tc. Accordingly, the following equation (10) is established:

Accordingly, the following equation (11) is established:

As described above, the current Ia is given by the following equation (12):
Ia=I−Ib(12)

Accordingly, the temperature coefficient Tc of the current Ia is given by the following equation (13):

When the equation (13) is reorganized, the following equation (14) is obtained:

As described above, the temperature coefficient αq of the current I3is about 0.33%/° C., and the temperature coefficient αc of the current I3B is about −0.33%/° C. Accordingly, the following equation (15) is established:
αq=−αc  (15)

Accordingly, when the equation (14) is reorganized using the equation (15), the following equation (16) is established:

In the equation (16), the temperature coefficient αq is determined in advance. Accordingly, it is possible to change the temperature coefficient Tc of the current I through adjusting a ratio between the current Ib and the current I.

FIGS. 13(a) and13(b) are graphs showing characteristics of the voltage generation circuit60C according to the third embodiment of the present invention. More specifically,FIG. 13(a) is a graph No. 1 showing a relationship between the temperature coefficient αq and the current, andFIG. 13(b) is a graph No. 2 showing the relationship between the temperature coefficient αq and the current.

InFIG. 13(a), the vertical axis represents a proportional term (1+Ib/I)/(1−Ib/I) of the temperature coefficient αq, and the horizontal axis represents the ratio of the currents Ib/I. InFIG. 13(b), the vertical axis represents the temperature coefficient Tc obtained by substituting the temperature coefficient αq with an actual specific value 0.33%/° C., and the horizontal axis represents the ratio of the currents Ib/I.

As shown inFIGS. 13(a) and13(b), when the ratio of the currents Ib/I increases, a graph curve increases. As shown at a point U inFIG. 13(b), when the ratio of the currents Ib/I, that is the ratio of the current I3B and the current I3, becomes 0.3, the temperature coefficient Tc of the current I3A becomes about 0.6%/° C. Further, as shown at a point V inFIG. 13(b), when the ratio of the currents Ib/I, that is the ratio of the current I3B and the current I3, becomes 0.5, the temperature coefficient Tc of the current I3A becomes about 1.0%/° C.

As described above, when the LED201is formed of a material such as GaAs, the temperature coefficient of the drive current becomes about 0.6%/° C. in order to compensate the temperature characteristic of the LED201. When the LED201is formed of a material such as AlGaInP, the temperature coefficient of the drive current becomes about 1.0%/° C. in order to compensate the temperature characteristic of the LED201.

As shown inFIG. 13(b), when the ratio of the currents Ib/I is set at the point U or V, it is possible to obtain the temperature coefficient Tc matching to the temperature coefficient of the material of the LED201.

As described above, in the reference voltage generation circuit60C in the third embodiment, it is possible to increase the temperature coefficient further than the first embodiment. More specifically, as indicated with the following equation (17), the current I3B with the negative temperature coefficient is subtracted from the current I3with the positive temperature coefficient to generate the current I3A. Accordingly, it is possible to increase the temperature coefficient.
I3A=I3−I3B(17)

In the embodiment, while the current I3A has the temperature coefficient greater than that of the current I3, the absolute value of the current I3A is smaller than that of the current I3. However, according to the decrease in the absolute value of the current I3A, when the resistivity R2of the resistor64increases, it is possible to easily set the reference voltage Vref at a specific level.

As described above, in the reference voltage generation circuit60C in the third embodiment, in addition to the configuration of the reference voltage generation circuit60in the first embodiment, the current-mirror circuit portion161and the fifth current-mirror circuit164with the configurations similar to those in the first embodiment are provided.

Accordingly, the reference voltage generation circuit60C generates the reference current I3B inversely proportional to the base-emitter voltage of the NPN transistor65and the NPN transistor66. Further, the reference current I3B is subtracted from the reference current I3obtained from the configuration in the first embodiment, thereby generating the reference current I3A with the large temperature coefficient. According to the reference current I3A, it is possible to generate the reference voltage Vref at the specific level. Accordingly, it is possible to set the temperature coefficient of the reference voltage generation circuit60C according to the temperature coefficient of the LED201, and to freely set the reference voltage Vref.

More specifically, in the reference voltage generation circuit60C in the third embodiment, it is possible to freely set the temperature coefficient of the reference voltage Vref output from the output terminal VREF thereof. Further, it is possible to freely set the reference voltage Vref at the specific level independent from the temperature coefficient thereof.

Further, in the second embodiment, similar to the first embodiment, even when the value of the power source voltage VDD fluctuates, it is possible to reduce the variance in the reference voltage Vref generated from the reference voltage generation circuit60to a negligibly minimum level. Accordingly, it is possible to apply the reference voltage generation circuit60C to various LEDs and drives device thereof.

Fourth Embodiment

A fourth embodiment of the present invention will be explained next. It is possible to modify the reference voltage generation circuit60C in the third embodiment through applying the similar technical concept.FIG. 14is a circuit diagram showing a configuration of a reference voltage generation circuit60D according to the fourth embodiment of the present invention. Components in the fourth embodiment similar to those in the third embodiment are designated with the same reference numerals.

As shown inFIG. 14, in the reference voltage generation circuit60D in the fourth embodiment, a fourteenth MOS transistor of the second conductive type (for example, an NMOS61f) is disposed through a diode connection between the node N7on a side of the drain of the PMOS61eand the node N6on the side of the output terminal VREF. Further, a fifteenth MOS transistor of the second conductive type (for example, an NMOS161f) is disposed through a diode connection between a node N13on a side of the drain of the PMOS161eand the fifth node N12on the side of the drain of the fifth current-mirror circuit164a. Accordingly, it is possible to minimize a difference in the operational points relative to the PMOS61band the PMOS161b.

More specifically, the drain and the gate of the NMOS61fare connected to the drain of the PMOS61ethrough the node N7. The source of the NMOS61fis connected to the output terminal VREF and the one end portion of the resistor64through the node N6. Accordingly, the NMOS61fhas the gate-source voltage Vgs3. Further, the drain and the gate of the NMOS161fare connected to the drain of the PMOS161ethrough the node N13. The source of the NMOS61fis connected to the drain and the gate of the fifth current-mirror circuit164aand the gate of the resistor64through the fifth current-mirror circuit164b. Accordingly, the NMOS161fhas the gate-source voltage Vgs4. Other configuration of the reference voltage generation circuit60D is similar to that of the reference voltage generation circuit60C in the third embodiment.

In the reference voltage generation circuit60D in the fourth embodiment, it is possible to obtain an effect similar to that in the reference voltage generation circuit60C in the third embodiment. More specifically, the potential of the node N13on the side of the drain and the gate of the NMOS161fis greater than the potential of the node N12on the side of the source of the NMOS161fby the gate-source voltage Vgs4. Further, the potential of the node N7on the side of the drain and the gate of the NMOS61fis greater than the potential of the node N6on the side of the source of the NMOS61fby the gate-source voltage Vgs3. As a result, it is possible to set the potential close to those of the POMS61band the PMOS161b. Accordingly, it is possible to match the drain potential and the operation state of the PMOS61a, the PMOS61b, the PMOS61e, the PMOS161a, the PMOS161b, and the PMOS161e, thereby making it possible to minimize a current variation between the drain currents I1, I2, I3, I4, I5, and I6.

It is noted that the present invention is not limited to the embodiments described above, and may be modified as follows.

In the configurations shown inFIGS. 1,6,10,11, and14, even when the polarity of the MOS transistors or the bipolar transistors constituting the circuits is changed, or the polarity of the power source is changed, it is possible to obtain the similar effect. More specifically, the PMOS may be changed to NMOS, or the NOMS may be changed to the PMOS. Further, the NPNTR may be changed to the PNP transistor (PNPTR), or the first power source may be changed to the ground GND and the second power source may be changed to the power source VDD according to the change in the transistors.

In the embodiments described above, the present invention is applied to the LED201as the light source, and may be applicable to other driven elements such as a light emitting thyristor and a light emitting transistor. The present invention may be effectively applied to a device for controlling a voltage applied to an organic EL element or a heating resistor.

For example, the present invention is applicable to a printer including an organic EL head formed of an array of organic EL elements, or a thermal printer including an array of heating resistors. Further, the present invention is applicable for controlling a voltage applied to a display device (for example, a display element arranged in a row or a matrix pattern).

Further, the present invention is applicable for driving a four-terminal thyristor SCS (Semiconductor Controlled Switch) having a first gate and a second gate, in addition to a thyristor having a three-terminal structure.

The disclosure of Japanese Patent Application No. 2010-100209, filed on Apr. 23, 2010, is incorporated in the application by reference.