Method and storage system with a non-volatile bad block read cache using partial blocks

A storage system has a memory with a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block. The storage system repurposes the partially-bad SLC block as a non-volatile read cache for data stored in the MLC block (e.g., cold data that is read relatively frequently) to improve performance of host reads. Because the original version of the data is still stored in the MLC block, the original version of the data can be read if there is an error in the copy of the data stored in the partially-bad SLC block, thus avoiding the need for extensive error-correction handling to account for the poor reliability of the partially-bad SLC block.

BACKGROUND

A memory of a storage system comprises a plurality of blocks of memory cells. Some of these blocks may have problems with storing data reliably, such as when a block has word lines that are not functioning properly (“bad word lines”). Such blocks are often referred to as “bad blocks.” In some cases, a bad block is marked in the manufacturing process as unavailable for use. However, a bad block may still be able to store data to a certain extent, albeit not as reliably as a “good block.” Such blocks are often referred to as “partially-bad blocks.” Some storage systems use partially-bad blocks to store data but provide extensive error-correction handling to account for the poor reliability of the blocks.

DETAILED DESCRIPTION

The following embodiments are generally related to a method and storage system with a non-volatile bad block read cache using partial blocks. In one embodiment, a storage system is provided comprising a memory comprising a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block and a controller. The controller is configured to copy data stored in the MLC block into the partially-bad SLC block, wherein the data is stored both in the MLC block and the partially-bad SLC block; receive a request from a host to read the data; and read the data from the partially-bad SLC block instead of the MLC block. In another embodiment, a method is provided for used in a storage system comprising a memory comprising a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block configured for use as a read cache. The method comprises identifying data stored in the MLC block to be copied into the read cache; storing a copy of the data in the read cache; receiving a request from a host to read the data; and in response to the request, reading the copy of the data from the read cache. In yet another embodiment, a storage system is provided comprising a memory and means for repurposing a partially-bad SLC block in the memory as a non-volatile read cache for data stored in a multi-level cell (MLC) block in the memory. Other embodiments are provided, and each of these embodiments can be used alone or in combination.

Turning now to the drawings, storage systems suitable for use in implementing aspects of these embodiments are shown inFIGS.1A-1C.FIG.1Ais a block diagram illustrating a non-volatile storage system100(sometimes referred to herein as a storage device or just device) according to an embodiment of the subject matter described herein. Referring toFIG.1A, non-volatile storage system100includes a controller102and non-volatile memory that may be made up of one or more non-volatile memory die104. As used herein, the term die refers to the collection of non-volatile memory cells, and associated circuitry for managing the physical operation of those non-volatile memory cells, that are formed on a single semiconductor substrate. Controller102interfaces with a host system and transmits command sequences for read, program, and erase operations to non-volatile memory die104.

As used herein, a non-volatile memory controller is a device that manages data stored on non-volatile memory and communicates with a host, such as a computer or electronic device. A non-volatile memory controller can have various functionality in addition to the specific functionality described herein. For example, the non-volatile memory controller can format the non-volatile memory to ensure the memory is operating properly, map out bad non-volatile memory cells, and allocate spare cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the non-volatile memory controller and implement other features. In operation, when a host needs to read data from or write data to the non-volatile memory, it can communicate with the non-volatile memory controller. If the host provides a logical address to which data is to be read/written, the non-volatile memory controller can convert the logical address received from the host to a physical address in the non-volatile memory. (Alternatively, the host can provide the physical address.) The non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused). Also, the structure for the “means” recited in the claims can include, for example, some or all of the structures of the controller described herein, programmed or manufactured as appropriate to cause the controller to operate to perform the recited functions.

Non-volatile memory die104may include any suitable non-volatile storage medium, including resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), phase-change memory (PCM), NAND flash memory cells and/or NOR flash memory cells. The memory cells can take the form of solid-state (e.g., flash) memory cells and can be one-time programmable, few-time programmable, or many-time programmable. The memory cells can also be single-level cells (SLC), multiple-level cells (MLC), triple-level cells (TLC), quad-level cell (QLC) or use other memory cell level technologies, now known or later developed. Also, the memory cells can be fabricated in a two-dimensional or three-dimensional fashion.

The interface between controller102and non-volatile memory die104may be any suitable flash interface, such as Toggle Mode200,400, or800. In one embodiment, storage system100may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card (or USB, SSD, etc.). In an alternate embodiment, storage system100may be part of an embedded storage system.

Although, in the example illustrated inFIG.1A, non-volatile storage system100(sometimes referred to herein as a storage module) includes a single channel between controller102and non-volatile memory die104, the subject matter described herein is not limited to having a single memory channel. For example, in some storage system architectures (such as the ones shown inFIGS.1B and1C),2,4,8or more memory channels may exist between the controller and the memory device, depending on controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the controller and the memory die, even if a single channel is shown in the drawings.

FIG.1Billustrates a storage module200that includes plural non-volatile storage systems100. As such, storage module200may include a storage controller202that interfaces with a host and with storage system204, which includes a plurality of non-volatile storage systems100. The interface between storage controller202and non-volatile storage systems100may be a bus interface, such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe) interface, or double-data-rate (DDR) interface. Storage module200, in one embodiment, may be a solid state drive (SSD), or non-volatile dual in-line memory module (NVDIMM), such as found in server PC or portable computing devices, such as laptop computers, and tablet computers.

FIG.1Cis a block diagram illustrating a hierarchical storage system. A hierarchical storage system250includes a plurality of storage controllers202, each of which controls a respective storage system204. Host systems252may access memories within the storage system via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) or fiber channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated inFIG.1Cmay be a rack mountable mass storage system that is accessible by multiple host computers, such as would be found in a data center or other location where mass storage is needed.

FIG.2Ais a block diagram illustrating components of controller102in more detail. Controller102includes a front end module108that interfaces with a host, a back end module110that interfaces with the one or more non-volatile memory die104, and various other modules that perform functions which will now be described in detail. A module may take the form of a packaged functional hardware unit designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example. The controller102may sometimes be referred to herein as a NAND controller or a flash controller, but it should be understood that the controller102can be used with any suitable memory technology, example of some of which are provided below.

Referring again to modules of the controller102, a buffer manager/bus controller114manages buffers in random access memory (RAM)116and controls the internal bus arbitration of controller102. A read only memory (ROM)118stores system boot code. Although illustrated inFIG.2Aas located separately from the controller102, in other embodiments one or both of the RAM116and ROM118may be located within the controller. In yet other embodiments, portions of RAM and ROM may be located both within the controller102and outside the controller.

Front end module108includes a host interface120and a physical layer interface (PHY)122that provide the electrical interface with the host or next level storage controller. The choice of the type of host interface120can depend on the type of memory being used. Examples of host interfaces120include, but are not limited to, SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe. The host interface120typically facilitates transfer for data, control signals, and timing signals.

The storage system100also includes other discrete components140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller102. In alternative embodiments, one or more of the physical layer interface122, RAID module128, media management layer138and buffer management/bus controller114are optional components that are not necessary in the controller102.

FIG.2Bis a block diagram illustrating components of non-volatile memory die104in more detail. Non-volatile memory die104includes peripheral circuitry141and non-volatile memory array142. Non-volatile memory array142includes the non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells and/or NOR flash memory cells in a two dimensional and/or three dimensional configuration. Non-volatile memory die104further includes a data cache156that caches data. Peripheral circuitry141includes a state machine152that provides status information to the controller102.

Returning again toFIG.2A, the flash control layer132(which will be referred to herein as the flash translation layer (FTL) or, more generally, the “media management layer,” as the memory may not be flash) handles flash errors and interfaces with the host. In particular, the FTL, which may be an algorithm in firmware, is responsible for the internals of memory management and translates writes from the host into writes to the memory104. The FTL may be needed because the memory104may have limited endurance, may only be written in multiples of pages, and/or may not be written unless it is erased as a block. The FTL understands these potential limitations of the memory104, which may not be visible to the host. Accordingly, the FTL attempts to translate the writes from host into writes into the memory104.

The FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allotted cache memory. In this way, the FTL translates logical block addresses (“LBAs”) from the host to physical addresses in the memory104. The FTL can include other features, such as, but not limited to, power-off recovery (so that the data structures of the FTL can be recovered in the event of a sudden power loss) and wear leveling (so that the wear across memory blocks is even to prevent certain blocks from excessive wear, which would result in a greater chance of failure).

Turning again to the drawings,FIG.3is a block diagram of a host300and storage system (sometimes referred to herein as a device)100of an embodiment. The host300can take any suitable form, including, but not limited to, a computer, a mobile phone, a digital camera, a tablet, a wearable device, a digital video recorder, a surveillance system, etc. The host300comprises a processor330that is configured to send data (e.g., initially stored in the host's memory340) to the storage system100for storage in the storage system's memory104.

FIG.4is a block diagram showing a basic block layout of the memory104in one embodiment. As shown inFIG.4, the memory104comprises a plurality of blocks of memory cells. Some blocks are configured as single-level cell (SLC) blocks, and other blocks are configured as multi-level cell (MLC) blocks, such as triple-level cell (TLC) blocks and quad-level cell (QLC) blocks. In general, SLC blocks provide faster read performance than MLC blocks, whereas MLC blocks have a large storage capacity than SLC blocks. In one embodiment, SLC blocks are used to store data in burst mode, where data is quickly coming into the storage system100for storage (e.g., when a user holds down the shutter button on a camera application on a mobile device), and the data is later moved from the SLC blocks to MLC blocks for longer-term storage.

As shown inFIG.4, some of the blocks are designated as “bad” or “partial bad” blocks. As noted above, if a block has problems storing data reliably, such as when a block has word lines that are not functioning properly (“bad word lines”), the block can be marked as “bad” during the manufacturing process and made unavailable for use. There are many reasons why a block may not be functioning properly. For example, with various new developments in NAND technology, it is observed that as the nodes are transitioned, the physical block sizes grow with each node. While the block sizes have increased rapidly, the defect rate in terms of percentage of blocks per plane have not improved considerably, which means that a significant portion of the blocks are not being utilized due to process defects.

Among these bad blocks, not all blocks are completely bad and can still be partially used to store data. A bad block that is able to store data to a certain extent, albeit not as reliably as a “good block,” is often referred to as “partial bad block” (the terms “partial bad block,” “partially-bad block,” and “partially-usable block” will be used interchangeably herein). Partially-bad blocks can be identified in any suitable way. For example, a differential memory screen can be defined for this purpose or special-purpose production firmware can be used that is targeted to identify such blocks with basic write/read/compare cycles (to detect partial word lines that can be utilized). The pool of partially-bad blocks can be maintained separately by the controller102(e.g., using firmware). Each memory can be a different number of partially-bad blocks that the controller can maintain. It should be noted that instead of or in addition to partially-bad blocks being identified during the manufacturing process, the blocks can be identified during runtime (e.g., good blocks can become bad or partially-bad over time).

Concerns remain on reliability of data stored in such blocks over the long term due to process impact, and this concern is compounded when exposed to high erase cycles, and blocks can go bad in the field. As such, using partially-bad blocks may be not desirable or even feasible for client (e.g., original equipment manufacturer (OEM)) or enterprise applications where reliability is a major criterion. Even if partially-bad blocks were used for shorter-term data, such as control data, some kind of redundancy or extensive exception handling/error-correction handling algorithms may be desired to ensure that the blocks can be used intermittently. Long-term reliability issues would remain the longer the data is stored. Further, using exception handling mechanisms can result in a decrease in performance for the storage system.

As illustrated by the above examples, reliability of data in partially-bad blocks is a major concern and can be a deterrent to their usage in many client/OEM/enterprise use-cases, and the need for additional error handling mechanisms can nullify the actual gains of using such blocks.

The following embodiments provide a new use for the partially-bad blocks in the memory104that avoids these issues. In one embodiment, partially-bad blocks are used as a read cache for data that is already stored in another block in the memory104. In one particular implementation, the partially-bad block has a faster read access time than the good block storing the data, such as when the partially-bad block is an SLC block, and the good block is an MLC block. So, by storing a copy of the data in the faster, partially-bad block, the data can be read more quickly than from the slower, good block. This provides for improved host read performance in multiple scenarios which would have otherwise had slower MLC read performance. And because the original data is still stored in the good block, if an error occurs in reading the partially-bad block, the data can simply be read from the good block. This avoids the need for using extensive error-handling with the partially-bad block.

The following paragraphs provide several examples uses of these embodiments. It should be understood that these are merely examples and other implementations can be used.

Turning again to the drawings,FIG.5is a flow chart of read operation for the “base case” situation illustrated inFIG.4where partially-bad blocks in the memory104are not used. In this example, “Data B” is stored in a good block in the memory104, which is an MLC (e.g., TLC/QLC) block. As shown inFIG.5, when the storage system100receives a read request from the host300for Data B stored in a particular logical address, the controller102uses a logical-to-physical address table or map to find the physical address of the memory block in the memory104that corresponds with the logical address (act510). The controller102then reads the data from the memory block (act520) and transfers the data to the internal transfer RAM116(seeFIG.4) in the memory (act530). From there, the data is returned to the host300.

In this example, the data is stored in an MLC block instead of an SLC block. This may be because the data was considered to be “cold” (e.g., due to a lack of host updates or some other criterion that indicates the data is not updated or accessed above a threshold number of times). In general, for performance reasons, the controller102may want to store “hot” (frequently updated/accessed) data in SLC blocks because those blocks are read faster than MLC blocks. However, SLC blocks are in limited supply. So, when the controller102determines that data is cold, it can move the data to the slower MLC block.

However, there are situations in which the data, although not “hot enough” to be stored in an SLC block, is still accessed somewhat frequently (e.g., above a threshold number of times) and, thus, is a good candidate to move to a faster SLC cache. For example, even with the introduction of a hybrid-blocks algorithm allowing MLC blocks to be used as SLC, there remains multiple use-cases which are real user-scenarios (e.g., boot operating system (Boot-OS) or frequently-loaded read-only data) where host data goes cold and is moved to MLC but is still read quite frequently. Considering a typical QLC use case with NAND memory, QLC sense can be three-times more time consuming as compared to SLC sense. To address this issue, the data can be copied to a partially-bad SLC block. Any suitable mechanism can be used to identify data to be stored in the cache. For example, the controller102can use pre-existing heuristics to identify cold data with additional read counter mapping. As another example, caching of certain data can be triggered by a host communication/information. Any other algorithm to identify the data set can be used.

As shown inFIG.6, in this embodiment, the read cache is formed from partially-bad blocks. As shown inFIG.7, data can be marked for caching and then copied to partially-bad blocks. When data is copied to the partially-bad block, a write error may occur (e.g., due to a bad word line), in which case, the controller102can skip the bad word line and find a good word line in the block to use. The copying can be done in any suitable way. For example, having identified the data and available cache, the controller102can utilize a background operation (BKOPS) as a way to copy the data to the partially-bad block and allow a bit as part of control data to allow detection and availability of the data in the cache. In this way, a read can be serviced from the partially-bad block instead of from the MLC block, but the MLC block would still store the original data. Instead of doing the copying as a background operation, the copying can be done as a foreground operation based on a combination of multiple criteria (e.g., when the host300has crossed certain read thresholds on MLC blocks without overwrites on that block, when cache space is available, when the program-erase count (PEC) of the cache block being significantly low, etc.).

When a request comes in for the data, the data can be read from the faster partially-bad SLC block instead of the slower MLC block. And because the data is still stored in the MLC block, if there is an error reading the partially-bad SLC block, the data can simply be read from the MLC block. That is, since the partially-bad blocks in this embodiment are just used as a cache, the partially-bad blocks do not need to guarantee reliability or use extensive exception-handling mechanisms. Additionally, considering a typical QLC use case with NAND memory, by caching the read data in a partially-bad SLC block, QLC read disturb is reduced. This reduction will reduce the QLC read scrub rate (depending on the use case, as data retention type of read scrub is not saved) and, thus, save a few QLC program-erase (PE) cycles, which can now be used for hybrid and improve performance as well.

FIG.8shows a flow chart800for reading data from the read cache in this embodiment. As shown inFIG.8, when the storage system100receives a read command with the logical block address of Data B, the controller102in the storage system100determines if the data is cached in a partially-bad block (act810). If the data is not cached in a partially-bad block, the data is read from the MLC block (acts820-840), similar to the process illustrated inFIG.5. However, if the data is cached in a partially-bad block, the controller102find the partially-bad block that corresponds to the good block that stores the original version of the data (act850). This can be done in any suitable way. For example, the controller102can create a mapping (in the logical-to-physical address table or elsewhere) between a good MLC block and a partially-bad SLC block. That way, the controller102can redirect the read operation from the MLC block to the partially-bad SLC block, so that the partially-bad SLC block is read instead of the MLC block (act860).

Because the partially-bad SLC block is not completely reliable, it is possible that the data read from the partially-bad SLC block contains errors. So, in this embodiment, the controller102determines if the read passes an error detection/correction check (act870). For example, if the number of errors in the data is zero or below a threshold, the data is can be returned to the host300(act840). Otherwise, the controller102can clear the mapping, erase the partially-bad block, and read the data from the good block (act880). That is, in this embodiment, the data is still maintained in the MLC block after a copy of the data is stored in the partially-bad block, so the original data can simply be read from the MLC block, thereby avoiding the need for extensive error correction handling.

There are many alternatives that can be used with these embodiments. For example, the controller102can utilize host-based hints more effectively to have a non-volatile cache and allow better performance as compared to any regular device for such cases. Additionally, there is no data-reliability concern since it is just a cache of the data, and the actual data is stored in a good block. Also, program-erase (PE) cycling of partially-bad blocks can be limited due to the cold nature of data and can be artificially restricted as well. Further, a program-erase count (PEC) cycles of MLC blocks can be saved, giving hybrid usage some additional PEC. Additionally, growth of bad regions in these blocks will be maintained as well until the partial good part is low enough to reduce gains.

There are several advantages associated with these embodiments. In general, these embodiments provide a unique approach and simple design of utilizing partially-bad blocks with high potential of performance gains, while addressing reliability concerns on these blocks. Current client SSD devices do not have any partial bad block handling. Hence, they are part of a bad block pool that is utilized since, even with known approaches, reliability remains a major concern due to unpredictability in the NAND behavior across various scenarios for bad blocks. With these embodiments, partially-bad blocks can be used for enhanced host read performance for the host operation system or host-application-specific caching, which are typically read only; hence, greatly improving the user-experience. This advantage is illustrated inFIGS.9-11.FIG.9shows the configuration of the memory blocks in an empty memory104. After normal usage, Data A and Data B are stored in QLC blocks (seeFIG.10). In this example, Data A is frequently read, but Data B is not. So, improvement in read performance for Data A can be achieved using these embodiments. More specifically, as shown inFIG.11, a copy of Data A can be stored in a partially-bad block, and that copy can be read when the host requests a read of Data A.

One of skill in the art will recognize that this invention is not limited to the two dimensional and three dimensional structures described but cover all relevant memory structures within the spirit and scope of the invention as described herein and as understood by one of skill in the art.