On-chip circuit for transition delay fault test pattern generation with launch off shift

A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed to the design and manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to the design and testing of logic for detecting transition delay faults in an integrated circuit.

2. Description of Related Art

To facilitate testing of integrated circuits using automated test equipment (ATE), test logic is generally included in the integrated circuit itself. The test logic usually functions only during testing and has no utility during normal operation of the integrated circuit in the field.

In a scan test, the flip-flop elements in the integrated circuit design are connected in large scan chains. During the scan test, test patterns typically generated by an automatic test pattern generator (ATPG) are shifted through the scan chains to initialize the flip-flop elements to a predetermined state. The output data from the logic elements connected to the flip-flop elements is captured by other flip-flop elements that are also part of the scan chains. The captured data is then shifted out. The automated test equipment (ATE) controls the shifting and capture phases and transmits the test patterns to the integrated circuit. The same clock signal is used during the shift and capture phases, and a scan enable signal is used to control when shifting occurs and when data is captured. The ATE also receives the captured data when it is shifted out and compares the captured data to expected results. There are two types of transition delay fault (TDF)/inline resistance fault (IRF) pattern formats: double-capture and launch-off-shift. The double-capture format generates two capture clock pulses when the scan enable signal is driven LOW, while the launch-off-shift format generates only one capture clock pulse when the scan enable is driven LOW. The launch-off-shift method of testing is called launch-off-shift because the logic under test begins to transition to the state that is captured immediately after the final shift.

SUMMARY OF THE INVENTION

In one embodiment, a clock pulse controller includes a clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.

In another embodiment, a method of generating clock pulses for an integrated circuit includes steps of receiving test clock pulses, receiving a scan enable signal having a first state and a second state, and receiving a trigger pulse. A launch clock pulse and a capture clock pulse are generated from the test clock pulses immediately after receiving a predetermined number of test clock pulses immediately following the trigger pulse. A delayed scan enable signal is generated that transitions from the first state to the second state in the interval between the leading edge of the launch clock pulse and the leading edge of the capture clock pulse.

Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to point out distinctive features in the illustrated embodiments of the present invention.

DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The following description is not to be taken in a limiting sense, rather for the purpose of describing by specific examples the general principles that are incorporated into the illustrated embodiments. For example, certain actions or steps may be described or depicted in a specific order to be performed. However, practitioners of the art will understand that the specific order is only given by way of example and that the specific order does not exclude performing the described steps in another order to achieve substantially the same result. Also, the terms and expressions used in the description have the ordinary meanings accorded to such terms and expressions in the corresponding respective areas of inquiry and study except where other meanings have been specifically set forth herein.

To simplify referencing in the description of the illustrated embodiments of the present invention, indicia in the figures may be used interchangeably to identify both the signals that are communicated between the elements and the connections that carry the signals. For example, an address communicated on an address bus may be referenced by the same number used to identify the address bus.

Testing of integrated circuits such as latch based random access memory has previously been done using scan automatic test pattern generation (ATPG), for example, with Mentor Macrotest. For high-speed testing, the launch-off-shift method has been used in conjunction with a precise interval between the launch and capture clock pulses during pattern generation to increase the test speed. Typically, the ATE supplies the scan clock pulses directly. Consequently, the test speed is usually limited to between 200 and 300 MHz by the ATE clock edge placement accuracy and cycle limit.

To overcome the frequency limitations of the ATE, phase locked loops such as those routinely used in integrated circuit designs may advantageously be used to multiply the frequency of the scan clock to a desired test clock frequency. A clock suppression circuit separates two consecutive high speed test clock pulses from the phase locked loop output to generate launch and capture clock pulses. A clock multiplexer circuit switches between the two high speed test clock pulses and the slower ATE scan shift clock at appropriate points in the test pattern, and a scan enable pipeline/multiplexer circuit may be used with the scan enable signal to supply the last shift operation necessary for the launch-off-shift operation.

In one embodiment, a clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.

FIG. 1illustrates a block diagram of a clock pulse controller100for transition delay fault test pattern generation with launch off shift. Shown inFIG. 1are a scan clock pulse input102, a scan enable input104, a phase locked loop106, a clock pulse suppressor108, a clock pulse multiplexer110, a scan enable multiplexer112, launch/capture pulses114, and a delayed scan enable output116.

InFIG. 1, the clock pulse input102receives scan clock pulses, for example, from automated test equipment (ATE). The phase locked loop106generates test clock pulses at a desired test frequency, typically the design operating frequency of the integrated circuit under test. The integrated circuit under test (not shown) includes scan chains used for transition delay fault according to well-known integrated circuit testing techniques. The clock pulse suppressor108receives the test clock pulses from the phase locked loop106and generates the launch clock pulse and the capture clock pulse after the scan enable signal104transitions from the shift mode to the scan mode. The clock pulse controller100may be included on the integrated circuit chip, which typically already includes a phase locked loop.

FIG. 2illustrates a schematic diagram200of a clock pulse suppressor for the clock pulse controller100ofFIG. 1. Shown inFIG. 2are a delay counter202, a test clock pulse input204, a clock pulse trigger input206, a clock pulse separator208, and a suppressed clock pulse output210.

InFIG. 2, a trigger pulse received at the clock pulse trigger input206, for example, from the automated test equipment (ATE), enables the delay counter202to count a selected number of test clock pulses from the phase locked loop106inFIG. 1received by the test clock pulse input204. In this example, five test clock pulses are counted to delay the transition of the logical output of the delay counter202from “0” to “1” at the clock pulse separator208. In other embodiments, the number of test clock pulses may be selected to suit specific applications within the scope of the appended claims. The trigger pulse is held to a logical “1” long enough for the delay counter202to generate a logical “1” at the clock pulse separator208and is then driven to a logical “0” to clear the delay counter202. Other means for generating a delayed logical “1” to the clock pulse separator208as a function of the number of test clock pulses from the test clock pulse input204may be used according to well-known integrated circuit design and manufacturing techniques.

The clock pulse separator208receives test clock pulses from the test clock pulse input204and generates the launch and capture clock pulses from two consecutive test clock pulses at the suppressed clock pulse output210in response to the logical “1” received from the delay counter202. The launch and capture clock pulses at the suppressed clock output210have the same frequency and interval as the test clock pulses generated by the phase locked loop106, advantageously overcoming the limitations of frequency and pulse intervals inherent in the automated test equipment (ATE). A pair of launch and capture clock pulses is generated at the clock pulse output210for each trigger pulse received at the clock pulse trigger input206.

FIG. 3illustrates a timing diagram300for the clock pulse suppressor ofFIG. 2. Shown inFIG. 3are a clock pulse trigger302, test clock pulses304, and launch and capture clock pulses306.

InFIG. 3, the launch and capture clock pulses306are generated following a delay of five consecutive test clock pulses after the transition of the clock pulse trigger302from a logical “0” to a logical “1”.

FIG. 4illustrates a schematic diagram400for the clock pulse controller ofFIG. 1with a clock pulse multiplexer. Shown inFIG. 4are a phase locked loop106, a clock suppressor108, a suppressed clock pulse output210, a clock pulse multiplexer110, a scan enable input402, a scan clock pulse input404, and a clock multiplexer output406.

InFIG. 4, the launch and capture clock pulses from the suppressed clock pulse output210are gated to the clock multiplexer output406when the scan enable input402is driven to a logical “0”. When the scan enable input402is a logical “1”, the scan clock pulses received at the scan clock pulse input404from the automated test equipment (ATE) are gated to the clock multiplexer output406. The flip-flop in the clock pulse multiplexer110converts the scan clock pulses404to a non-clock signal that selects the multiplexer driven by the flop Q-output when the scan enable input402is driven to a logical “1”. This feature satisfies the requirement by the ATPG tool that the scan clock is always run as a clock.

FIG. 5illustrates a timing diagram500for the clock pulse controller ofFIG. 4. Shown inFIG. 5are a phase locked loop reference clock502, a scan enable signal504, scan clock pulses506, a clock pulse trigger508, test clock pulses510, and clock multiplexer output pulses512.

InFIG. 5, the phase locked loop reference clock502is received as input to the phase locked loop106, for example, from a local oscillator on-chip, to set the frequency of the test clock pulses510according to well-known integrated circuit design and manufacturing techniques. The clock multiplexer output pulses512are identical to the scan clock pulses506when the scan enable signal504is a logical “1” and are identical to the launch and capture pulses generated by the clock pulse output210when the scan enable signal504is a logical “0”.

FIG. 6illustrates a schematic diagram600of an integrated circuit with the clock pulse controller ofFIG. 4for multiple scan clocks. Shown inFIG. 6are a top level module602, a second level module604, and clock pulse controllers606,608, and610.

InFIG. 6, the top level module602includes the second level module604and the clock pulse controllers606,608, and610added for testing with phase locked loops. The second level module604includes the scan chains in integrated circuit design that interface to the clock pulse controllers606,608, and610in the top level module602. The top level module602and the second level module604may be constructed according to well-known integrated circuit design and manufacturing techniques.

The clock pulse controller606includes an additional multiplexer for gating the functional clock, that is, the normal operating clock pulses, to the integrated circuit in the second level module604when not in the scan mode. The clock pulse controllers608and610do not include the additional multiplexer. In this embodiment, an additional multiplexer for each scan clock is included in the second level module604according to well-known integrated circuit techniques.

FIG. 7illustrates a schematic diagram700of an integrated circuit of the prior art with multiple scan clock inputs. Shown inFIG. 7are a top level module702, a second level module704, scan clock inputs706and708, a scan mode input710, and phase locked loops712and714.

InFIG. 7, the multiplexers inside the second level module704switch the scan chain clock inputs inside the second level module704between the functional clocks and the scan clock inputs706and708in response to the scan mode input710. The scan clock inputs706and708typically share the same pins with other signals used during normal operation of the integrated circuit in the second level module704but not during testing.

FIG. 8illustrates a schematic diagram800of an integrated circuit including clock pulse controllers for multiple scan clock inputs. Shown inFIG. 8are a top level module802, a second level module804, scan clock inputs806and808, a scan mode input810, a scan enable input812, a clock pulse trigger input814, and clock pulse controllers816and818.

InFIG. 8, the multiplexers inside the second level module804switch the scan chain clock inputs between the functional clocks and the scan clock inputs806and808in response to the scan mode input810. The clock pulse controllers816and818switch the scan chain clock inputs inside the second level module804between the scan clock inputs806and808and the launch/capture pulses generated by the clock pulse controllers816and818in response to the signals received at scan enable input812and the clock pulse trigger input814as described above with reference toFIG. 2.

FIG. 9illustrates a timing diagram900of a launch-off-shift test pattern generated by a previous automated test pattern generation (ATPG) scheme according to the prior art. Shown inFIG. 9are a scan enable signal902, scan clock pulses904, and a launch/capture interval906.

InFIG. 9, the automated test equipment (ATE) must generate two consecutive high speed clock pulses for the launch and the capture operation. The two consecutive high speed clock pulses are separated by the launch/capture interval906. Typically, the ATE is only capable of generating clock pulses at much lower frequencies than those required by the integrated circuit under test. Consequently, at-speed testing at the design operating frequency is impractical. However, using the high speed clock pulses generated by a phase locked loop, the clock pulse controller described above may be used to generate a launch-off-shift transition delay fault test pattern to overcome the limitations of the ATE with a pipeline multiplexer as follows.

FIG. 10illustrates a schematic diagram1000of a clock pulse controller with a scan enable pipeline multiplexer. Shown inFIG. 10are a scan enable pipeline multiplexer1002, functional logic1004, a clock pulse controller1006, a scan enable input1008, a clock pulse output1010, and a delayed scan enable1012.

InFIG. 10, the scan enable pipeline multiplexer1002holds the delayed scan enable1012HIGH until after the rising edge of the launch clock pulse. The delayed scan enable1012is then driven LOW before the rising edge of the capture clock pulse to perform the capture operation. Other means may be implemented according to well-known integrated circuit design and manufacturing techniques to generate the delayed scan enable1012so that the transition from HIGH to LOW occurs in the interval between the leading edges of the launch and capture clock pulses.

FIG. 11illustrates a timing diagram1100for a launch-off-shift test pattern generated by for the clock pulse controller ofFIG. 10. Shown inFIG. 11are a scan enable signal1102, a scan enable pipeline “Q” output1104, a scan enable multiplexer select signal1106, scan clock pulses1108, a delayed scan enable signal1110, multiplexed test clock pulses1112, and a transient1114.

InFIG. 11, the scan enable signal1102is inverted in the scan enable pipeline multiplexer1002to generate the scan enable multiplexer select signal1106. The flip-flop and the multiplexer in the scan enable pipeline multiplexer1002generate the delayed scan enable signal1110in response to the scan enable signal1102and the launch pulse from the clock pulse output1010of the clock pulse controller1006. The falling edge of the delayed scan enable signal1110occurs between the rising edge of the launch clock pulse and the rising edge of the capture clock pulse to ensure proper launch-off-shift operation. In the illustrated embodiment, the rising clock edges are the leading edges that are used to initiate the launch and capture operations. In other embodiments, the leading edges used to initiate the launch and capture operations may be the falling edges of the launch and capture clock pulses.

The transient1114added to the scan enable pipeline flop Q-output1104in the delayed scan enable signal1110results from the transition of the scan enable multiplexer select signal1106in the scan enable pipeline multiplexer1002. However, the clock pulse controller1006inhibits scan clock pulses in the multiplexed test clock pulses1112, which avoids inducing errors in the transition delay fault test.

The rising edge of the last shift clock pulse1112inFIG. 11, the launch clock, occurs while the delayed scan enable1110is HIGH. The delayed scan enable1110then transitions to LOW between the launch and capture clock pulses to perform the capture operation.

In another embodiment, a method of generating clock pulses for an integrated circuit includes steps of receiving test clock pulses, receiving a scan enable signal having a first state and a second state, and receiving a trigger pulse. A launch clock pulse and a capture clock pulse are generated from the test clock pulses immediately after receiving a predetermined number of test clock pulses immediately following the trigger pulse. A delayed scan enable signal is generated that transitions from the first state to the second state in the interval between the leading edge of the launch clock pulse and the leading edge of the capture clock pulse.

FIG. 12illustrates a flow chart1200for a method of controlling clock pulses for launch-off-shift transition delay fault testing.

Step1202is the entry point of the flow chart1200.

In step1204, test clock pulses are received, for example, from a phase locked loop.

In step1206, a scan enable signal is received having a first state and a second state.

In step1208, a trigger pulse is received, for example, from a test pattern generated for automated test equipment (ATE).

In step1210, a launch clock pulse and a capture clock pulse are generated from the test clock pulses immediately after receiving a predetermined number of test clock pulses immediately following the trigger pulse.

In step1212, a delayed scan enable signal is generated as output that transitions from the first state to the second state in the interval between the leading edge of the launch clock pulse and the leading edge of the capture clock pulse. This feature allows the launch-off-shift test scheme to function properly without having to tune the scan enable signal to accommodate various test configurations.

Step1214is the exit point of the flow chart1200.

Advantages of the clock pulse controller described above include testing integrated circuits at the operating frequency limit, using existing phase locked loop circuits in the integrated circuit design to generate the capture clock pulses, and using clock pulses generated by automated test equipment (ATE) as a backup test and for debugging the integrated circuit design. Also, the clock pulse controller described above may be used with any transition delay fault/inline resistance fault (TDF/IRF) test pattern that uses the launch-off-shift format for at-speed launch and capture using the high speed clock pulses generated by a phase locked loop.

Although the method illustrated by the flowchart description above is described and shown with reference to specific steps performed in a specific order, these steps may be combined, sub-divided, or reordered without departing from the scope of the claims. Unless specifically indicated herein, the order and grouping of steps is not a limitation of the present invention.

The specific embodiments and applications thereof described above are for illustrative purposes only and do not preclude modifications and variations that may be made within the scope of the following claims.