Chain logic scheme for programmed logic array

Additional data processing capability can be added to a programmed logic array (PLA), having an AND plane and an OR plane connected serially between an input register and an output register, by inserting a multistage domino CMOS logic network between the OR plane and the output register. The OR plane is an array of single-stage domino CMOS logic and is timed so that it precharges simultaneously with the multistage network. Without prolonging the individual phase durations or adding any registers, the added domino logic network can have a propagation delay time corresponding to more than one phase of the PLA, and hence the network can have correspondingly more stages and more added data processing capability.

FIELD OF THE INVENTION 
This invention relates to semiconductor logic circuits and more 
particularly to such circuits which employ programmed logic arrays (PLAs). 
Still more particularly, this invention relates to logic circuits 
including two or more PLAs where data signal outputs of a given PLA are 
processed with data signal outputs of another PLA before being delivered 
to other parts of the circuit or before being fed back to the given PLA, 
in order to have a circuit which requires less semiconductor area and 
which can operate at a higher speed than a circuit comprising only a 
single (but larger) PLA. 
BACKGROUND OF THE INVENTION 
Programmed logic arrays (PLAs) are often incorporated in semiconductor 
integrated circuits used in data processing systems. A PLA performs logic 
computations or transformations, that is, it processes data by delivering 
data signal outputs as determined by data signal inputs in accordance with 
a prescribed logic computation or transformation rule. 
A PLA typically has two main portions or planes, known as the AND plane and 
the OR plane, respectively. Outputs of the AND plane are inputs to the OR 
plane; and some of the outputs of the OR plane are fed back as inputs to 
the AND plane, so that the PLA implements a finite state machine. Each 
plane is in the form of a crosspoint logic array, that is, a rectangular 
array of intersecting row lines and column lines. Each plane is programmed 
in that at each crosspoint intersection of a row line with a column line, 
a separate driver transistor is connected or not, depending upon the 
desired logic function or transformation of that plane. Each of the input 
and output data signals of the plane can be a LOW or a HIGH voltage, 
corresponding to binary digital (1's and 0's) data signals entering into 
and emanating from the plane. 
Basically, each plane of a PLA is designed to perform NOR logic functions 
of selected inputs thereto in accordance with the desired logic function 
or transformation of the inputs entering that plane, as described in 
greater detail below. The specifics of the NOR functions implemented by 
each of the planes are determined by the configurations in the respective 
planes of the presences versus absenses of the crosspoint driver 
transistors at the various crosspoints. 
More specifically, in a PLA, inputs to a given plane thereof are applied 
along parallel (row) input lines (wires) to the gate electrodes of the 
driver transistors in the logic array corresponding to that plane, and 
outputs from the plane emanate along parallel (column) output lines 
orthogonal to the input lines. In one particularly useful form, each logic 
plane of a PLA is configured as a single stage of pseudo-NMOS logic. That 
is, each input line is connected to the gate electrode of each of the 
driver transistors (all n-channel MOS) that are present at crosspoints of 
that input line; each output line is connected through the source-drain 
path of a separate p-channel MOS precharge pullup transistor to a first 
power supply line (V.sub.DD) and is also connected through the 
source-drain paths of each of the driver transistors (that are present at 
crosspoints of that output line) in series through the source-drain path 
of an n-channel MOS pulldown transistor to a second power supply line 
(V.sub.SS). During the precharge phase of a given plane during each PLA 
cycle of operation, the pullup transistors are turned on while the 
pulldown transistor is turned off, whereby all the output lines are 
charged to the voltage (V.sub.DD) of the first power supply line; and 
during each evaluation phase immediately succeeding the precharge phase, 
the pullup transistors are turned off while the pulldown transistor is 
turned on, whereby each output line does or does not discharge to the 
voltage (V.sub.SS) of the second power supply line, depending upon whether 
or not any of the driver transistors present at crosspoints of that output 
line is then on. 
During each cycle of the PLA operation, in order to supply inputs to the 
AND plane during appropriate time intervals of each cycle, an input 
register controls the flow of the inputs into the AND plane; similarly, in 
order to supply outputs from the OR plane to the rest of the system, as 
well as feedback to the AND plane during appropriate time intervals, an 
output register controls the flow of outputs from the OR plane. 
The input and output registers, as well as the AND and OR planes, operate 
in accordance with an orderly control timing sequence. For timing purposes 
in a synchronous data processing system, suitable clock pulse timing 
sequences can be delivered to the registers, as well as to the AND and OR 
planes, in order to ensure this orderly timing of operation. Thus, the 
registers, as well as the planes, can operate to receive, as well as to 
deliver, new data signals during appropriate phases of each cycle of the 
clock. Thus, for example, during a first phase of each such cycle the 
input register by the AND plane, during a second phase the AND plane 
generates new corresponding data for propagation to and reception by the 
OR plane, during a third phase the OR plane generates new corresponding 
data for propagation to and reception by the output register, and during a 
fourth phase the output register receives the new data from the OR plane 
for propagation to other parts of the system as well as for propagation as 
feedback to the input register. 
The duration of each of the pulses which enables the input register to be 
transparent--i.e., to receive fresh data--is ordinarily equal to the 
duration of each of the pulses which enable the output register to be 
transparent, but each pulse is applied to the input register during a 
different portion (first phase) of the cycle from that (fourth phase) 
during which each pulse is applied to the output register. Thus, the first 
and fourth phases are equal in time duration, but are not coincident. 
In general, there is at least one output line of the OR plane to which so 
many crosspoint transistors are connected that the resulting response time 
delay of such output line is so long (owing to crosspoint transistor 
capacitance loading) that it is necessary for the fourth phase to succeed 
(rather than coincide with) the third phase. Thus, in general, the first, 
second, third, and fourth phases are successive phases. The time durations 
of all such phases are advantageously mutually equal, moreover, for 
simplicity of design of the circuitry that supplies the control timing for 
these phases. 
In a variety of data processing contexts it is desirable to perform further 
logic transformations upon the output data emanating from the OR plane of 
a PLA before delivering the data to other parts of the system, such as to 
the ALU (Arithmetic Logic Unit), or before feeding back the data to the 
AND plane. In U.S. Pat. No. 4,339,516, issued to Blahut et al on Aug. 16, 
1983 entitled "Stored-Program Control Machine," a single logic 
gate--specifically a static (unclocked) AND gate--was inserted in each of 
the feedback lines of a given PLA to receive data from the PLA output 
register, as well as data from one or more other PLAs in the data 
processing system, and to process and deliver data back to the PLA input 
register. In that manner, some additional data processing capability was 
added to the PLA. The amount of such additional processing on each line, 
however, is limited because of the need for the data emanating from the 
added logic network to be valid as soon as the input register becomes 
transparent, i.e., at the beginning of each first phase; othewise the data 
would not arrive soon enough at the crosspoint driver transistors of the 
AND plane, particularly in view of the propagation delays along the paths 
from the input register to these crosspoint drivers. And further, because 
of inherent propagation delays in the feedback lines, the additional 
processing capability was thus limited to an amount corresponding to a 
propagation delay of less than the duration of a single clock phase, if 
the processing is done by the relatively slow static logic. On the other 
hand, in certain systems it is desirable to add more data processing 
capability, such as a multistage logic network, having a propagation delay 
corresponding to more than only a single phase, that is, to insert a 
multistage logic network having a plurality of successive stages (a 
plurality of successive logic gates in tandem). Such a multistage logic 
network, however, has a propagation time delay for new data propagating 
therethrough which is longer than that of the OR plane, and can be even 
longer than the duration of a transparent phase of the output register. 
Such a desired longer propagation delay for the added logic network makes 
it very difficult to insert the added logic network into the PLA in this 
manner unless the duration of each of the mutually equal phases is 
prolonged and hence the speed of operation is undesirably slowed down. 
SUMMARY OF THE INVENTION 
In a data processing system, a multistage logic network having a 
propagation delay which is longer than that of the OR plane in a given PLA 
and can be longer than that of a transparent phase of the output register 
of the PLA is connected for receiving data from the OR plane as well as 
from another part of the data processing system (such as one or more other 
PLAs) and for delivering data to the output register of the PLA. At the 
same time, no registers at all need be added, and the speed of operation 
is not slowed down. 
Accordingly, this invention involves a semiconductor integrated circuit 
which includes a PLA having an input register, an AND plane connected for 
receiving first data from the input register, an OR plane connected for 
receiving second data from the AND plane, an output register, and a logic 
network connected for receiving third data from the OR plane and for 
delivering fourth data to the output register, the propagation delay o the 
logic network being longer than that of the OR plane. The logic network is 
advantageously a multistage domino CMOS logic network, i.e., a multistage 
network of the type described, for example, in a paper entitled 
"High-Speed Compact Circuits with CMOS," by R. H. Krambeck et al published 
in IEEE Journal of Solid State Circuits, Vol. SC-17, pp. 614-619 (1982). 
Further, the OR plane is advantageously an array of single-stage domino 
CMOS logic having control timing the same as that of the multistage domino 
CMOS network, whereby the precharge and evaluation phases of the OR plane 
coincide respectively with the precharge and evaluation phases of the 
domino logic network. 
The sum of the propagation time delays of the OR plane and the logic 
network is advantageously less than twice the time duration of the clock 
pulse phase which, during each cycle of PLA operation, enables the output 
register to receive fresh data from the logic network (i.e., the clock 
pulse that makes the output register transparent). Thus, a smaller 
propagation delay in the OR plane enables more delay in the logic network 
and hence enables the logic network to have more stages. On the other 
hand, the propagation delay of the OR plane is undesirably increased by 
those output lines thereof which have relatively high capacitance loading, 
such loading being typically caused by the presence of a relatively large 
number of crosspoint driver transistors connected to each of such lines, 
whereby the allowed delay of, and hence the allowed number of stages in, 
the logic network is limited. Accordingly, if it is desired to increase 
the allowed number of stages in the logic network, the propagation delay 
time of the OR plane is reduced to a lower amount by splitting any output 
line of the OR plane that is unduly slow (i.e., any output line having a 
propagation delay time which is a significant fraction of the 
above-mentioned lower amount) into a pair of parallel lines and combining 
the outputs of the pair by connecting them through a separate suitable 
logic gate--such as a domino CMOS OR gate--to the multistage logic 
network. Thus, further in accordance with the invention, a semiconductor 
integrated circuit contains a PLA comprising an input register connected 
for delivering data to an AND plane, the AND plane being connected for 
delivering data to an OR plane, the OR plane being connected for 
delivering data to a multistage logic network, the multistage network 
being connected for delivering data to an output register, a pair of 
output lines of the OR plane being connected through a logic gate to the 
multistage logic, the logic gate advantageously being an OR gate. In this 
way the propagation delay time through the OR plane plus the OR gate can 
be made to be less than the duration of the transparent phase interval of 
the output register by a first predetermined amount of time, and the 
propagation delay through the multistage logic network can then be more 
than the duration of the transparent phase of the output register by a 
second amount of time, the second amount being less than the first so that 
the sum of the propagation delays of the OR plane, the OR gate, and the 
multistage logic network is less than twice the transparent phase interval 
of the output register, whereby data exiting from the logic network arrive 
at the output register early enough in time for being received and latched 
therein. In this manner, the system can be timed so that data from the 
output register can be available (valid) after a delay equal to only two 
phase intervals subsequent to the validity of data entering the OR plane, 
even though the data must traverse both the OR plane and the multistage 
logic circuit, the latter alone having a propagation delay greater than 
one transparent phase interval of the output register, while the amount of 
logic computation capability of the multistage circuit can correspond to 
more than the duration of, for example, the transparent phase interval of 
the output register by an extra amount of logic capability corresponding 
to the second predetermined amount of time. 
In a specific embodiment of the invention, a cycle of operation has four 
equal consecutive clock phases, .phi..sub.1, .phi..sub.2, .phi..sub.3, and 
.phi..sub.4. Each phase typically corresponds to the pulse duration of 
first, second, third, and fourth clock pulse sequences (FIG. 5). An input 
register is timed to be transparent during each first phase .phi..sub.1. 
The output data of the register is delivered to the AND plane of a PLA. 
Each of the AND and OR planes of the PLA has the configuration of a 
single-stage dynamic NMOS logic. The AND plane is timed so as to precharge 
during the first phase .phi..sub.1 and to deliver its output data which 
are valid during the second phase .phi..sub.2. Each second phase commences 
substantially immediately following the termination of the corresponding 
first phase .phi..sub.1. The output data from the AND plane are then 
delivered to the OR plane of the PLA which precharges during the second 
phase .phi..sub.2. The resulting output data from the OR plane are valid 
commencing with the end of the second clock phase .phi..sub.2, and these 
output data are then delivered from the OR plane to a multistage domino 
logic network which precharges during each second phase .phi..sub.2 (i.e., 
simultaneously with the precharging of the OR plane). After the data from 
the OR plane propagate through and are processed by the domino network, 
output data from the domino network are valid at some time during the 
fourth phase .phi..sub.4. These output data from the domino circuit are 
then delivered to an output register which is timed to be transparent 
during each fourth phase .phi..sub.4. The output register then delivers 
its outputs to other parts of the system, as well as back to the input 
register. In addition, to speed up the operation of the OR plane itself, 
at least one pair of output lines of the OR plane is advantageously 
connected to an OR gate whose output terminal is connected to an input 
terminal of the domino network. Thus, the PLA can handle added domino 
logic corresponding to a propagation delay of more than one clock phase.

DETAILED DESCRIPTION 
FIG. 1 illustrates in data stream sequence: an input register 100, an AND 
plane 200, an OR plane 300, a domino logic network 400, and an output 
register 500. The input register 100 is controlled by timing t.sub.1 
(.phi..sub.1), the AND plane 200 by timing t.sub.2 (.phi..sub.1), the OR 
plane 300 by timing t.sub.3 (.phi..sub.2), and the output register 500 by 
timing t.sub.4 (.phi..sub.4). For the sake of definiteness, operation 
during a given cycle t.sub.1 through t.sub.5 (FIG. 5) will be described in 
detail, with the understanding that during each of the succeeding cycles, 
the sequence of operation is similar. 
Typically, the time t.sub.1 is the time of commencement of a first 
positive-going phase clock pulse .phi..sub.1, as indicated in FIG. 5, 
whereas t.sub.2, t.sub.3, and t.sub.4 are the respective times of 
commencement of subsequent second, third, and fourth clock phases 
.phi..sub.2, .phi..sub.3, .phi..sub.4. In general, the time intervals 
t.sub.1 t.sub.2, t.sub.2 t.sub.3, t.sub.3 t.sub.4, and t.sub.4 t.sub.5 are 
all mutually equal. The input register 100 is transparent during t.sub.1 
t.sub.2 (and t.sub.5 t.sub.6 during the next cycle) and latches data 
during t.sub.2 t.sub.5 ; the output register 500 is transparent during 
t.sub.4 t.sub.5 and latches during t.sub.1 t.sub.4 (and t.sub.5 t.sub.8). 
More specifically, during the time interval t.sub.1 t.sub.2, fresh data 
inputs I.sub.1, I.sub.2, . . . F enter the input register 100, and these 
inputs together with their complements IHD 1, IHD 2, . . . F are thus 
delivered to the AND plane 200 as fresh data commencing at time t.sub.1 
(except for small propagation delays in the input register). In 
particular, the input F is supplied as feedback from the output register 
500, and the inputs I.sub.1, I.sub.2, . . . are supplied by other parts of 
the system (not shown). 
After passage through and processing by the AND plane 200, fresh data 
emanate during the given cycle from this AND plane along wordlines 
W.sub.1, W.sub.2, W.sub.3 . . . W.sub.m commencing at time t.sub.2, and 
these data are then delivered to the OR plane 300. Typically, t.sub.2 is 
the time of commencement of the positive-going phase clock pulse 
.phi..sub.1, the complement of .phi..sub.1 (FIG. 5), except for possible 
safety margins (not shown). After passage through and processing by the OR 
plane 300, fresh date Z.sub.1, Z.sub.2, . . . Z.sub.N emanate from this OR 
plane commencing at time t.sub.3 (FIG. 3), and these data are then 
delivered to the domino logic 400. 
Note that the data Z.sub.1 is produced by processing a pair of output 
signals SHD 1, SHD 2 emanating directly from the OR plane 300 through a 
dynamic OR gate 330 whose timing is controlled by .phi..sub.2 (fresh data 
can emanate from the OR gate 330 commencing at t.sub.3), for reasons 
described more fully below in connection with FIGS. 2 and 3. Briefly, the 
use of the dynamic OR gate 330 enables splitting an otherwise slow 
(heavily capacitively loaded) output line of the OR plane 300 into two 
faster (less heavily loaded) output lines and thus enables earlier 
availability of the data Z.sub.1 for further processing by the domino 
logic 400. In terms of the outputs SHD 1 and SHD 2 emanating from the OR 
plane: Z.sub.1 =SHD 1+SHD 2, where the "plus" sign denotes a logical sum, 
i.e., the logic OR function (Z.sub.1 is TRUE if and only if either or both 
of the logic variables SHD 1, SHD 2 are TRUE). 
In addition to Z.sub.1, Z.sub.2, . . . Z.sub.N, input signals INP 
originating from one or more other OR planes of the other PLAs (not shown) 
and/or other domino logic (not shown) that are clock-timed identically as 
are the OR plane 300 and the domino logic 400, but are located in other 
parts of the system, can also directly deliver input date to the logic 
network 400. Conversely, any of the signals Z.sub.1, Z.sub.2, . . . 
Z.sub.N can also be directly delivered to such other domino logic located 
in other parts of the system, as indicated by the arrow labeled Z.sub.N. 
By the term "directly" it is meant that the data are delivered along paths 
without any intervening registers. 
After passage through and processing by the domino logic network 400, fresh 
output data O.sub.1, O.sub.2, . . . F would emanate from the domino logic 
network 400 commencing at the time t.sub.3, except for the unavoidable 
propagation delays encountered in the domino logic 400, but in general, 
these data actually emanate from the domino network 400 commencing at some 
time after t.sub.4 but before t.sub.5. These data from the domino logic 
400 are then delivered directly to the output register 500 and/or directly 
to other domino logic (not shown) located in other parts of the system, as 
indicated by the arrow O.sub.1. The output register 500 is transparent and 
delivers fresh data during the given cycle commencing at time t.sub.4, 
typically the commencement of a positive-going fourth clock phase pulse, 
.phi..sub.4. Also, this output register latches at time t.sub.5 (and 
continues to deliver the same data during t.sub.5 t.sub.8 of the next 
cycle). The sum of the propagation delays of fresh data propagating from 
the OR plane to the domino logic and then through the domino logic 400 to 
the output register 500 should therefore be significantly less than the 
time interval t.sub.3 t.sub.5 in order to ensure arrival of the data at 
the register 500 in time for latching (at t.sub.5) therein. Thus, the 
output register 500 delivers these fresh output data O.sub.1, O.sub.2, . . 
. to other parts of the data processing system (such as an arithmetic 
logic unit) and delivers the output F as feedback to the input register 
along a feedback data line 600. 
FIGS. 2 and 3, as related to each other in accordance with FIG. 4, show a 
circuit diagram of a PLA chain logic scheme in accordance with a specific 
embodiment of the invention. Elements of FIGS. 2 and 3 which are the same 
as or illustrative of those of FIG. 1 are denoted by the same reference 
numerals. For the sake of simplicity of labeling, in the description that 
follows, the same reference label is often used to refer to a signal and 
to the corresponding signal line on which the signal propagates. 
As shown in FIG. 2, the input register 100 receives input data signals 
I.sub.1, I.sub.2, . . . , as well as feedback data signal F on feedback 
line 600, and delivers all these inputs together with their complements 
IHD 1, IHD 2, . . . F0 to the AND plane 200. The input register 100 
basically is a parallel load register, that is, a parallel array of 
clocked static latches. Each of the input signals I.sub.1, I.sub.2, . . . 
, as well as the feedback signal F, passes through a separate clocked 
latch for delivery of the respective signals to the AND plane 200, as 
shown in FIG. 2 in detail for the signal I.sub.1 as an example. Thus, the 
signal I.sub.1 is delivered to input node 102.1 of a clocked inverter 102, 
and then passes through both the clocked inverter 102 and an unclocked 
inverter 103. The clocked inverter 102 typically is a clocked CMOS 
inverter as illustrated in greater detail in FIG. 6 and as described in 
greater detail below. The complementary input signal IHD 1 is thereby 
developed at an intermediate node 102.2 between the clocked inverter 102 
and the (unclocked) inverter 103. A (complementary) clocked CMOS inverter 
104 is connected in a feedback loop between the output node 102.3 of the 
inverter 103 and the intermediate node 102.2 for the purpose of providing 
suitably timed static latching of the complementary input signal IHD 1, 
that is, latching during the time interval t.sub.2 t.sub.5 (FIG. 5), when 
the first clock pulse phase .phi..sub.1 is LOW. The clocked inverter 102 
is transparent and passes the complement of I.sub.1 during the time 
interval t.sub.1 t.sub.2 when the first clock pulse phase .phi..sub.1 is 
HIGH. Similarly, each of the other input signals I.sub.2 . . . F passes 
through a separate similarly constructed clocked static latch in the input 
register 100. 
The AND plane 200 (FIG. 2) is constructed as a two-dimensional crosspoint 
array of single-stage dynamic pseudo-NMOS gates. Clocked (.phi..sub.1) 
pullup PMOS transistors 221, 222, 223, . . . 224 are connected for 
precharging the wordlines W.sub.1, W.sub.2, W.sub.3, . . . W.sub.m, 
respectively, to the voltage V.sub.DD. A (.phi..sub.1) clocked NMOS 
transistor 226 is connected to serve as a pulldown transistor, that is, to 
pull down during each evaluation phase the voltage of each of the 
wordlines to V.sub.SS if and when at least one driver connected to the 
corresponding wordline is in its ON state at any time during the 
evaluation phase. The wordlines W.sub.1, W.sub.2, W.sub.3, . . . W.sub.m 
all run horizontally in the AND plane 200 and intersect therein, at 
various crosspoints, a plurality of groundlines G.sub.1, G.sub.2, . . . 
G.sub.m which run vertically. At each crosspoint, an NMOS driver 
transistor (T.sub.11, T.sub.22, T.sub.24 T.sub.33, T.sub.44) is or is not 
connected depending upon the desired logic transformation to be performed 
by the PLA. For example, NMOS driver transistor T.sub.11 is connected at 
the crosspoint of wordline W.sub.1 and groundline G.sub.1, and the gate 
electrode of T.sub.11 is connected to signal line I.sub.1. Thus, for 
example, transistors 221, T.sub.11, and 226 operate together as one stage 
of dynamic pseudo-NMOS; as do transistors 222, T.sub.22, and 226; 222, 
T.sub.24, and 226; 223, T.sub.33, and 226; and 224, T.sub.44, and 226. An 
auxiliary clocked pullup transistor 225 is added, if needed, for 
precharging intermediate interval node 227 which otherwise would 
undesirably share charge with one or more of the wordlines during 
precharge phases. 
The OR plane 300 (FIG. 2) is constructed similarly to the AND plane 200 
(rotated in the plane of the drawing by 90 degrees). The wordlines 
W.sub.1, W.sub.2, W.sub.3, . . . W.sub.m serve as input lines of this OR 
plane 300. Clocked (.phi..sub.2) pullup transistors 313, 314, . . . 315 
precharge the output signal lines S.sub.1, S.sub.2, . . . S.sub.N to the 
voltage V.sub.DD. An auxiliary PMOS pullup transistor 312 can be added to 
prevent undesirable charge sharing (similarly as was the auxiliary pullup 
transistor 225 previously described in the AND plane 200) between the 
output signal lines S.sub.1, S.sub.2, . . . S.sub.N and the intermediate 
node 327. Crosspoint NMOS driver transistors M.sub.11, M.sub.13, M.sub.22, 
M.sub.31, M.sub.41 are connected at selected crosspoints of the wordlines 
W.sub.1, W.sub.2, W.sub.3, . . . W.sub.m and the output signal lines 
S.sub.1, S.sub.2, . . . S.sub.N in accordance with the desired logic 
transformation to be performed by the OR plane 300. A clocked NMOS 
pulldown transistor 311 pulls down the voltage of each of the output 
signal lines S.sub.1, S.sub.2, . . . S.sub.N to V.sub.SS during each 
evaluation phase if and when at least one driver connected to the 
corresponding output signal line is in its ON state. Each of these output 
signal lines has an (unclocked) inverter 321, 322, . . . 323 to invert 
these output signals to SHD 1, SHD 2, . . . SHD N. Thus, the OR plane 
300--including the inverters 321, 322, . . . 323--is an array of 
single-stage domino CMOS logic. 
The dynamic OR gate 330 (FIG. 2) is formed by a NOR gate feeding an 
inverter. This NOR gate is advantageously implemented by a single stage of 
dynamic pseudo-NMOS as shown in FIG. 2. More specifically, this NOR gate 
is formed by a pair of parallel NMOS drivers 331 and 332, together with a 
clocked (.phi..sub.2) pullup transistor 333 (and the pulldown transistor 
311 of the OR plane 300), in accordance with a dynamic pseudo-NMOS stage. 
The inverter is formed by PMOS pullup transistor 334 in series with NMOS 
pulldown transistor 335. The output signals Z.sub.1 =SHD 1+SHD 2, etc., of 
this inverter, together with the other output signals Z.sub.N --some or 
all of which may or may not also be derived from the corresponding output 
signals S.sub.N through OR gate(s) (not shown)--are delivered to domino 
logic network 400 (FIG. 3). Only for the sake of clarity and resulting 
simplicity of the drawing, none of the output signals between S.sub.2 and 
S.sub.N is explicity indicated in FIG. 3. 
The domino CMOS logic network 400 (FIG. 3) is only illustrative of the many 
possible domino CMOS arrangements. Accordingly, in the network 400 
illustratively only three successive stages are explicitly shown: (1) a 
first stage with drivers 402 and 403, (2) a second stage with drivers 422, 
423, and 424, and (3) a third stage with drivers 442, 443, 444, and 445. 
The domino logic network 400 has PMOS pullup transistors 401, 421, and 441 
and NMOS pulldown transistors 404, 424, and 446--all of which are timed by 
the second complementary clock phase .phi..sub.2 in the same way as the 
pullup and pulldown transistors, respectively, in the OR plane 300 (FIG. 
2). A CMOS inverter 413, formed by PMOS transistor 411 and NMOS transistor 
412, inverts the output of the first stage developed at its output node 
410 to form an input to driver 422 of the second stage. Another CMOS 
inverter 431 inverts the output of the second stage developed at its 
output node 430 to form an output signal O.sub.1 which can illustratively 
serve both as an input to driver 442 of the third stage and as an output 
of the logic network 400, and hence ultimately as the input O.sub.1 to the 
output register 500. Another output O.sub.2 is illustratively developed by 
CMOS inverter 451 connected to output node 450 of the third stage of the 
domino network 400; and still other outputs (not shown), as well as the 
output F, are developed by further stages (not shown) thereof. Input 
signals INP fed to drivers 443 and 444, for example, can, but need not, 
come from the same PLA: they can also come from other PLAs that are 
identically clocked. Therefore, the chain logic scheme of this invention 
can combine many PLA output variables at high speed. 
The output signals O.sub.1, O.sub.2, . . . F emanating from the network 400 
are delivered to the output register 500 (FIGS. 1 or 3). This output 
register has an array of parallel latches timed by .phi..sub.4. Each latch 
is arranged for receiving a different one of the output signals O.sub.1, 
O.sub.2, . . . F, similar to the way in which the input register is 
arranged for receiving the input signals I.sub.1, I.sub.2, . . . F. The 
output register is transparent during the time interval t.sub.4 t.sub.5 
(FIG. 5) of the given cycle t.sub.1 t.sub.5, i.e., during the interval 
when the clocked inverter 502 is transparent and passes fresh data. This 
clocked inverter 502 is typically constructed similarly to the clocked 
inverter 102 in the input register 100, and it is connected for delivering 
data to an (unclocked) inverter 503. Another clocked inverter 504 is 
connected across this inverter 503 to form a feedback loop for latching 
data during the time interval t.sub.1 t.sub.4 of the given cycle (and 
during t.sub.5 t.sub.8 of the next succeeding cycle). 
Note that the third clock pulse sequence .phi..sub.3 (FIG. 5) is not 
actually used in the chain logic scheme of FIG. 1 or of FIGS. 2 and 3, but 
is illustrated solely to indicate the timing relationships of the second 
and fourth pulse clock sequences .phi..sub.2 and .phi..sub.4. 
FIG. 6 shows the details of construction of the clocked CMOS inverter 102 
(FIG. 2) at the transistor level. All the other clocked CMOS inverters 
104, 502, and 504 are similarly constructed. The clocked CMOS inverter 102 
(FIG. 6) is basically formed by a pair of series-connected PMOS 
transistors 601 and 602 connected in series with a pair of 
series-connected NMOS transistors 603 and 604 between power supply voltage 
terminals V.sub.DD and V.sub.SS. Input signal line I.sub.1 enters the 
clocked inverter 102 at the input node thereof, 102.1, and the 
complementary signal IHD 1 emanates at the output node 102.2 of this 
clocked inverter 102. The input signal I.sub.1 is applied to the gate 
terminals of both the PMOS transistor 601 and the NMOS transistor 604, the 
first clock phase pulse sequence .phi..sub.1 is applied to the gate 
terminal of the NMOS transistor 603, and the first complementary clock 
phase pulse sequence .phi..sub.1 is applied to the gate terminal of the 
PMOS transistor 602. During t.sub.1 t.sub.2 when .phi..sub.1 goes High and 
hence .phi..sub.1 goes LOW, both NMOS transistor 603 and PMOS transistor 
602 turn ON. Accordingly, if the input I.sub.1 is then (during t.sub.1 
t.sub.2) HIGH, NMOS transistor 604 is then ON while PMOS transistor 601 is 
then OFF, so that the voltage at the output node 102.2 goes to V.sub.SS, 
i.e., the output IHD 1 is LOW. On the other hand, if during t.sub.1 
t.sub.2 the input I.sub.1 is LOW, NMOS transistor 604 is OFF and PMOS 
transistor 601 is ON, so that the voltage at the output node 102.2 goes to 
V.sub.DD, i.e., the output IHD 1 is HIGH. Furthermore, during the 
following time interval t.sub.2 t.sub.5 when .phi..sub.1 is LOW and 
.phi..sub.1 is HIGH, then both the NMOS transistor 603 and the PMOS 
transistor 602 are OFF, so that the output node 102.2 floats, i.e., 
remains at substantially the same voltage as at the end of the time 
interval t.sub.1 t.sub.2. Accordingly, the clocked CMOS inverter 102 is 
transparent and passes the inverted value of the input I.sub.1 during the 
time interval t.sub.1 t.sub.2 when .phi..sub.1 is HIGH, and is in a high 
impedance state during the remaining portion t.sub.2 t.sub.5 of the given 
cycle, just as desired of a clocked inverter. On the other hand, the other 
clocked CMOS inverter 104 is timed in complementary fashion relative to 
the timing of the clocked inverter 102, since the timing control terminals 
to which .phi..sub.1 and .phi..sub.1 are connected in the inverter 102 are 
respectively the noninverting and inverting timing control terminals (the 
gate terminals of transistors 603 and 602 in FIG. 6), i.e., in the reverse 
order from the connections of .phi..sub.1 and .phi..sub.1, respectively, 
to the corresponding timing control terminals of the clocked inverter 104. 
During operation, after the inverted input signal IHD 1 emanates from the 
clocked inverter 102 at node 102.2 of the input register 100, this signal 
IHD 1 then passes through a nonclocked inverter 103 and is thus delivered 
as noninverted (doubly inverted) signal I.sub.1 to line 251 of the AND 
plane 200. In 
addition, the inverted signal IHD 1 is delivered directly from the output 
node 102.2 to line 252 of the AND plane. Similarly, I.sub.2 . . . F0 are 
delivered to input lines 253 . . . 254 or the OR plane. 
The OR plane 200 operates as follows during the given cycle t.sub.1 
t.sub.5. During the interval t.sub.1 t.sub.2 when .phi..sub.1 is HIGH and 
.phi..sub.2 is LOW, the PMOS pullup transistors 221, 222, . . . 225 are 
all ON. At the same time, the pulldown transistor 226 is OFF. Hence the 
intermediate internal node 227 and all the wordlines W.sub.1, W.sub.2, . . 
. W.sub.m are precharged HIGH, i.e., essentially to V.sub.DD. Thereafter, 
during the immediately succeeding time interval t.sub.2 t.sub.5 when 
.phi..sub.1 is LOW and .phi..sub.1 is HIGH, the pullup transistors 221, 
222, . . . 225 are all OFF but the pulldown transistors 226 is ON, whereby 
each of the wordlines W.sub.1, W.sub.2, . . . W.sub.m does or does not go 
LOW, i.e., discharge essentially to V.sub.SS, depending upon whether or 
not there is any crosspoint driver transistor connected to that wordline 
which is ON, i.e., which has an input to its gate terminal that is HIGH. 
Thus, the time interval t.sub.1 t.sub.2 corresponds to a precharge phase 
during which every wordline is charged HIGH, and the time interval t.sub.2 
t.sub.5 corresponds to an evaluation phase during which the voltage on 
every wordline is valid, i.e., depends upon the input signals in 
accordance with the prescribed logic transformation of the AND plane. 
The OR plane 300 operates similarly as the AND plane except that the 
precharge phase is t.sub.2 t.sub.3, i.e., the phase during which the 
second clock sequence .phi..sub.2 is HIGH. Thus, the output signals 
S.sub.1, S.sub.2, . . . S.sub.N of the OR plane are valid during t.sub.3 
t.sub.6, rather than t.sub.2 t.sub.5 as in the case of the AND plane. 
These output signals S.sub.1, S.sub.2, . . . S.sub.N respectively pass 
through inverters 321, 322, . . . 323 and become complementary outputs SHD 
1, SHD 2, . . . SHD N. As discussed above, the output signals SHD 1 and 
SHD 2 pass through the OR gate 330 to become the signal Z.sub.1 for input 
to the domino logic network 400. On the other hand, assuming that the 
output line S.sub.N is not heavily loaded and hence need not be split into 
two (or more) lines, then SHD N itself is directly utilized as the input 
Z.sub.N to the domino logic network 400. 
The domino logic network 400 (FIG. 3) operates as follows. During the time 
interval t.sub.2 t.sub.3 when .phi..sub.2 is HIGH and .phi..sub.2 is LOW, 
the PMOS pullup transistors 401, 421, and 441 are all ON; so that all the 
output nodes 410, 430, . . . which are located on the input side of the 
inverters 413, 431, . . . are HIGH; and all the output nodes 414, 432, . . 
. which are located on the output side of these inverters are LOW. 
Accordingly, all outputs O.sub.1, O.sub.2, . . . F of the domino logic 400 
are LOW during t.sub.2 t.sub.3. On the other hand, beginning at time 
t.sub.3, the outputs S.sub.1, S.sub.2, . . . S.sub.N of the OR plane 300 
become valid and propagate through the domino logic network to the output 
register 500. 
The output register 500 is a parallel load register similar to the input 
register 100. For example, the signal F from the domino logic network 400 
is delivered to a clocked inverter 502 whose timing is controlled by the 
fourth clock pulse phase .phi..sub.4. This clocked inverter is thus 
transparent and passes fresh data during t.sub.4 t.sub.5 of the given 
cycle. Latching of the data in the feedback loop is supplied by the 
clocked inverter 504 and occurs throughout t.sub.1 t.sub.4 of the given 
cycle (t.sub.1 t.sub.5) and t.sub.5 t.sub.8 of the next succeeding cycle 
(t.sub.5 t.sub.9). Thus, in particular, during the given cycle the 
(latched) outputs O.sub.1, O.sub.2, . . . F emanating from the output 
register 500 during the time intervals t.sub.1 t.sub.4 and t.sub.5 t.sub.8 
are determined by the data arriving at this output register from the logic 
network 400 at times t.sub.1 and t.sub.5, respectively. In particular, the 
outputs O.sub.1, O.sub.2, . . . F emanating from the output register which 
are valid during the next succeeding cycle are those arriving at the 
output register 500 essentially at t.sub.5 (that is, at t.sub.5 except for 
a small response delay time of the register). Accordingly, the output 
register 500 is timed to latch fresh data from the logic network 400 
corresponding to fresh data delivered to the OR plane 300 from the AND 
plane as late as at t.sub.3. Since the time duration of all phases are 
equal (t.sub.1 t.sub.2 =t.sub.2 t.sub.3 =t.sub.3 t.sub.4 =t.sub.4 
t.sub.5), the output register can properly handle data during a given 
cycle which have suffered a total propagation delay, in the OR plane 300 
plus the domino logic network 400, equal to as much as essentially t.sub.3 
t.sub.4 +t.sub.4 t.sub.5 =2t.sub.4 t.sub.5, or twice the time interval of 
the transparent phase (t.sub.4 t.sub.5) of the output register. 
It should be understood that although the invention has been described in 
terms of specific embodiments, various modifications can be made without 
departing from the scope of the invention. For example, the OR gate 330 
can be a multiple input OR gate with more than two input terminals, so 
that the outputs on more than two output lines of the OR plane can be 
connected to and combined by the multiple input OR gate for delivery to 
the logic network 400 in case the operating speed is not sufficiently 
reduced by splitting an original output line into just two lines. 
Moreover, each of more than one pair of output lines can be connected to a 
pair of input terminals of a separate OR gate in case it is desirable to 
split more than one of the original output lines in order to increase the 
operating speed of these additional lines.