BOTTOM ELECTRODE VIA AND CONDUCTIVE BARRIER DESIGN TO ELIMINATE ELECTRICAL SHORT IN MEMORY DEVICES

In some embodiments, the present disclosure relates to an integrated chip (IC), including a bottom electrode overlying an interconnect structure disposed within a lower inter-level dielectric (ILD) layer, a top electrode over the bottom electrode, a data storage structure between the top electrode from the bottom electrode, a conductive barrier layer directly overlying the interconnect structure, and a bottom electrode via (BEVA) vertically separating and contacting a bottom surface of the bottom electrode and a top surface of the conductive barrier layer. A maximum width of the BEVA is less than a width of the data storage structure.

BACKGROUND

Many modern-day electronic devices contain electronic memory, such as hard disk drives or random access memory (RAM). Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory is able to retain its stored data in the absence of power, whereas volatile memory loses its data memory contents when power is lost. Electronic memory can comprise data storage structures such as magnetic tunnel junctions (MTJs), which can be used in hard disk drives and/or RAM, and may be promising candidates for next generation memory solutions.

DETAILED DESCRIPTION

A memory device includes a data storage structure arranged between top and bottom electrodes. The data storage structure is able to store a bit of information as a logical “1” or a logical “0”. By applying an electrical bias to the memory device and across the data storage structure, the bit may be switched from a logical “0” to a logical “1” and vice versa. A bottom electrode via (BEVA) electrically couples a metal interconnect to the bottom electrode, such that an electrical bias can be applied.

A memory device may be formed by forming a BEVA over a metal interconnect. Then a bottom electrode may be formed over the BEVA, a data storage structure may be formed over the bottom electrode, and a top electrode may be formed over the data storage structure. A hard mask structure may then be deposited over the top electrode. The top electrode may undergo a first etch according to the hard mask structure. Then, the top electrode may be used as a mask for a second etch of the data storage structure and the bottom electrode.

The BEVA may be designed to be wider than the data storage structure to minimize via resistance. By minimizing via resistance, power consumption is also minimized, thus increasing the efficiency of the memory device. However, if the BEVA, and/or the metal interconnect are wider than the data storage structure, in many cases, the second etch may etch away a portion of the BEVA, and/or the metal interconnect. In doing so, the second etch may cause metallic by-product from the BEVA, and/or the metal interconnect to be re-deposited on sidewalls of the data storage structure. The re-deposited metallic by-product may result in the memory device being electrically shorted, which impacts a reliability of the memory device to read, write, and store bits of information. In some cases, an electrical short can render the memory device useless.

In the present disclosure, a method of manufacturing memory devices is presented to produce reliable memory devices. The new manufacturing method makes the BEVA narrower. To compensate for an increase in resistance due to making the BEVA narrower, using a low resistivity metal is disposed between a bottom of the BEVA and an underlying metal interconnect. The low resistivity metal shortens a height of the BEVA, and thereby compensating for the increase in resistance. By narrowing the BEVA and the metal interconnect, the new manufacturing method ensures that during the second etch of the data storage structure, no metallic by-product from the BEVA and/or the metal interconnect is re-deposited on sidewalls of the data storage structure, and thus prevents the memory device from being electrically shorted. In doing so, the memory device may reliably read, write, and store bits of information.

FIG. 1illustrates a cross-sectional view100of some embodiments of an integrated chip (IC) comprising a bottom electrode via (BEVA) having a narrow width that is configured to reduce shorting due to re-deposition of a conductive material during manufacturing.

The IC comprises a lower inter-layer dielectric (ILD) layer104disposed over a semiconductor substrate102. The ILD layer104comprises an interconnect structure106, and a conductive barrier layer108overlies the interconnect structure106. In some embodiments, the conductive barrier layer108comprises a lower surface that laterally extends past outer sidewalls of the interconnect structure106. A dielectric layer110overlies the conductive barrier layer108. In some embodiments, the dielectric layer110surrounds outer sidewalls of the conductive barrier layer108. The conductive barrier layer108electrically couples the interconnect structure106to a bottom electrode via (BEVA)112. The BEVA112extends through an opening103defined by inner sidewalls of the dielectric layer110and electrically couples the conductive barrier layer108to a memory device113.

In some embodiments, the memory device113may comprise a bottom electrode114disposed over the BEVA112, and a top electrode118over the bottom electrode114. A data storage structure116is disposed between the bottom electrode114and the top electrode118. The data storage structure116is configured to store a bit of data. In some embodiments, a dielectric structure120surrounds outer sidewalls of the top electrode118, the bottom electrode114, and the data storage structure116. In some embodiments, the dielectric structure120extends to vertically below a bottom surface of the dielectric layer110. In some embodiments, the data storage structure116may be or otherwise comprise, for example, a magnetic tunnel junction (MTJ), a ferroelectric layer, or any other suitable data storage structure(s).

The ILD layer104laterally extends to non-zero distances past opposing sides of the interconnect structure106. By extending past opposing sides of the interconnect structure106, the ILD layer104is able to prevent the exposure of the interconnect structure106during etching processes used to manufacture the memory device113. In some embodiments, the ILD layer104may have a first width W1that extends from an outer sidewall of the ILD layer104to an outer sidewall of the interconnect structure106. In some embodiments, the first width W1may range from approximately 5 nm to approximately 50 nm, from approximately 5 nanometers to approximately 30 nanometers, from approximately 10 nm to approximately 20 nm, or other similar values. Similarly, the dielectric layer110laterally extends to non-zero distances past opposing sides of the BEVA112. By extending past opposing sides of the BEVA112, the dielectric layer110is able to prevent the exposure of the BEVA112during etching processes used to manufacture the memory device113. In some embodiments, the dielectric layer110has a second width W2at a top surface of the dielectric layer110that extends from an outer sidewall of the dielectric layer110to an outer sidewall of the BEVA112. In some embodiments, the second width W2may range from approximately 1 nm to approximately 20 nm, from approximately 2 nanometers to approximately 15 nanometers, from approximately 5 nm to approximately 10 nm, or other similar values. In some embodiments, a bottommost surface of the bottom electrode114continuously extends past opposing outermost sidewalls of the BEVA112.

By implementing a non-zero lateral distance between the BEVA112and the outer sidewalls of the dielectric layer110, between the conductive barrier layer108and the outer sidewalls of the dielectric layer110, and between the interconnect structure106and outer sidewalls of the ILD layer104, the IC ensures that during an etch of the data storage structure116, no metallic by-product from the BEVA112, the conductive barrier layer108, and/or the interconnect structure106is re-deposited on sidewalls of the data storage structure.

FIG. 2illustrates a cross-sectional view200of some embodiments of an integrated chip (IC) comprising a plurality of memory regions with a bottom electrode via (BEVA) having a narrow width that is configured to reduce shorting due to re-deposition of a conductive material during manufacturing.

The IC comprises a lower inter-layer dielectric (ILD) layer104disposed over a semiconductor substrate102. A plurality of memory regions202overlie the ILD layer104. The plurality of memory regions202comprise a first memory region202aand a second memory region202b. In some embodiments, the plurality of memory regions202may comprise additional memory regions. The plurality of memory regions202respectively comprise an interconnect structure106disposed within the ILD layer104, and a conductive barrier layer108overlying the interconnect structure106. An etch stop layer204overlies the conductive barrier layers108. In some embodiments, the etch stop layer204surrounds outer sidewalls of the conductive barrier layer108.

A dielectric layer110is disposed over the etch stop layer204. A bottom electrode via (BEVA)112extends through an opening103defined by inner sidewalls of the dielectric layer110and inner sidewalls of the etch stop layer204. A bottom electrode114overlies the BEVA112and the dielectric layer110. A top electrode118overlies the bottom electrode114, and a data storage structure116is disposed between the bottom electrode114and the top electrode118. The data storage structure116is configured to store a bit of data. In some embodiments, a bit of data may be written to the data storage structure116by providing an electrical bias across the data storage structure116.

In some embodiments, the data storage structure116comprises a magnetic tunnel junction (MTJ)207that comprises a pinned ferromagnetic layer207aunderlying and separated from a free ferromagnetic layer207cby a tunnel dielectric layer207b. The pinned ferromagnetic layer207ahas a fixed magnetization direction, and the free ferromagnetic layer207chas a dynamic magnetization direction. In further embodiments, the data storage structure116further comprises a seed layer206underlying the MTJ207and separating the MTJ207from the bottom electrode114. The seed layer206may promote crystalline growth of the MTJ207. In further embodiments, the data storage structure116further comprises an encapsulation layer209overlying the MTJ207and separating the MTJ207from the top electrode118. The encapsulation layer209protects the MTJ207from exposure to gas and/or moisture. The encapsulation layer209further prevents metal from diffusing into the MTJ207.

In some embodiments wherein the data storage structure116comprises the MTJ207, the dynamic magnetization direction of the free ferromagnetic layer207ccan be switched by applying an electrical bias across the tunnel dielectric layer207b. By applying a current in a first direction from the free ferromagnetic layer207cto the pinned ferromagnetic layer207a, electrons with a magnetization direction the same as that of the pinned ferromagnetic layer207aflow into and accumulate in the free ferromagnetic layer207c, causing the magnetization of the free ferromagnetic layer207cto be parallel to the pinned ferromagnetic layer207a, writing the MTJ207to a low resistance state, representing the bit of data as a logical ‘0’. By applying a current in a second direction from the pinned ferromagnetic layer207ato the free ferromagnetic layer207c, electrons with a magnetization direction opposite that of the pinned ferromagnetic layer207aflow into and accumulate in the free ferromagnetic layer207c, causing the magnetization of the free ferromagnetic layer207cto be antiparallel to the pinned ferromagnetic layer207a, writing the MTJ207to a high resistance state, representing the bit of data as a logical ‘1’. By measuring the resistance across the MTJ207, this bit of data can be read.

In some embodiments, a dielectric structure120surrounds outer sidewalls of the top electrode118, the bottom electrode114, and the data storage structure116. In some embodiments, the dielectric structure120continuously extends over the first memory region202aand the second memory region202b. A sidewall spacer208is disposed along opposing sidewalls of the data storage structure116. In some embodiments, the sidewall spacer208continuously extends from a top surface of the top electrode118to the ILD layer104, such that the sidewall spacer208is disposed along opposing sidewalls of the dielectric layer110.

In some embodiments, the conductive barrier layer108has a third width W3. In some embodiments, the third width W3may range from approximately 30 nanometers to approximately 80 nanometers, from approximately 20 nanometers to approximately 100 nanometers, or other similar values. The BEVA112and the corresponding opening103respectively have a fourth width W4. In some embodiments, the fourth width W4of the BEVA112is measured at a top surface of the BEVA112. In some embodiments the third width W3of the conductive barrier layer108is greater than the fourth width W4. In some embodiments, the fourth width W4is a maximum width of the BEVA112and the corresponding opening103. In some embodiments, the fourth width W4may range from approximately 30 nanometers to approximately 80 nanometers, from approximately 20 nanometers to approximately 100 nanometers, or other similar values. The bottom electrode114has a fifth width W5. In some embodiments, the fifth width W5of the bottom electrode114may be greater than a maximum width of 6 the data storage structure116and the top electrode118. In some embodiments, the fifth width W5of the bottom electrode114is measured at a bottom surface of the bottom electrode114. In some embodiments, the fifth width W5is a maximum width of the bottom electrode114. In some embodiments, the fifth width W5may range from approximately 20 nanometers to approximately 150 nanometers, from approximately 34 nanometers to approximately 114 nanometers, from approximately 50 nanometers to approximately 100 nanometers, or other similar values. In some embodiments, the BEVA112is above a topmost surface of the conductive barrier layer108.

A bottommost surface of the etch stop layer204is disposed below a topmost surface of the ILD layer104by a distance D1. Further, a top surface of the interconnect structure106is the distance D1above an upper surface of the ILD layer104located laterally outside of the conductive barrier layer108. In some embodiments, inner sidewalls of the etch stop layer204contact outer sidewalls of the ILD layer104. In some embodiments, the distance D1may range from approximately 5 nanometers to approximately 15 nanometers, from approximately 2 nanometers to approximately 20 nanometers, or other similar values. The conductive barrier layer has a first height H1. In some embodiments, the first height H1may range from 3 nanometers to 15 nanometers. The BEVA112has a second height H2. In some embodiments, the second height H2may range from approximately 30 nanometers to approximately 80 nanometers, from approximately 30 nanometers to approximately 100 nanometers, from approximately 20 nanometers to approximately 150 nanometers, or other similar values. Based on the distance D1and the first height H1, a first upper surface of the etch stop layer204located above the conductive barrier layer108may be above a second upper surface of the etch stop layer204contacting the sidewall spacer208.

In some embodiments, the etch stop layer204continuously extends from over the conductive barrier layer108to below the conductive barrier layer108. In some embodiments, the etch stop layer204shares a curved sidewall with the dielectric layer110. In some embodiments, the ILD layer104is laterally between outermost sidewalls of the interconnect structure106and the sidewall spacer208. In some embodiments, a bottom surface of the data storage structure116continuously extends past the opposing outermost sidewalls of the BEVA112. In some embodiments, outer sidewalls of the sidewall spacer208may be slanted at a first angle A1of other than 90 degrees with respect to a top surface of the ILD layer104. In some embodiments, sidewalls of the dielectric layer110may be slanted at a second angle A2of other than 90 degrees with respect to a top surface of the ILD layer104. In some embodiments, the first angle A1may be different than the second angle A2. In further embodiments, the second angle A2may be greater than the first angle A1.

FIG. 3illustrates a cross-sectional view300of some embodiments of an integrated chip (IC) comprising a bottom electrode via (BEVA) having a narrow width that is configured to reduce shorting due to re-deposition of a conductive material during manufacturing.

The IC comprises a memory cell region302aand a logic region302b. Both the memory cell region302aand the logic region302bcomprise a transistor structure314disposed in a semiconductor substrate102. In various embodiments, the transistor structure314may comprise a field effect transistor (FET), a planar FET, a finFET, a gate all around structure (GAA) transistor, or the like. The transistor structure314comprises heavily doped regions such as a source304and a drain306disposed within the semiconductor substrate102. A gate structure308is disposed over a top surface of the semiconductor substrate102and between the source304and the drain306. A lower inter-layer dielectric (ILD) layer310is disposed over the semiconductor substrate102and surrounding outer sidewalls of the gate structure308. A contact plug312is disposed within the lower ILD layer310. In some embodiments, the contact plug312is electrically coupled to the transistor structure314. In further embodiments, the contact plug312may be electrically coupled to the drain306. In some embodiments, the gate structure308may comprise a conductive gate electrode that is separated from the semiconductor substrate102by a gate dielectric layer (not shown).

The memory cell region302acomprises an ILD layer104overlying the lower ILD layer310. The ILD layer104surrounds an interconnect structure106. In some embodiments, the interconnect structure106is electrically coupled to the transistor structure314of the memory cell region302a. A conductive barrier layer108overlies the interconnect structure106and comprises one or more outer sidewalls that are laterally outside of outer sidewalls of the interconnect structure106. A bottom electrode via (BEVA)112extends through an opening103defined by inner sidewalls of the dielectric layer110and inner sidewalls of the etch stop layer204. In some embodiments, the outer sidewalls of the conductive barrier layer108are slanted at a third angle A3. In some embodiments, the third angle A3may be an acute angle as measured through the conductive barrier layer108and with respect to a bottom surface of the conductive barrier layer108. In some embodiments, the BEVA112may comprise opposing outer sidewalls tilted at a fourth angle A4. In some embodiments, the fourth angle A4may range from approximately 90 degrees to approximately 120 degrees, from approximately 85 degrees to approximately 135 degrees, or other similar values as measured through the BEVA112and with respect to a top surface of the conductive barrier layer108. In some embodiments, the conductive barrier layer108has a maximum width at a bottom surface of the conductive barrier layer108. An etch stop layer204overlies the conductive barrier layer108. A dielectric layer110is disposed over the etch stop layer204.

A bottom electrode114contacts a top surface of the BEVA112. A data storage structure116overlies the bottom electrode114, and a top electrode118overlies the data storage structure116. A sidewall spacer208is disposed along sidewalls of the data storage structure116, sidewalls of the top electrode118, and sidewalls of the bottom electrode114. In some embodiments, the sidewall spacer208is further disposed along sidewalls of the dielectric layer110, sidewalls of the etch stop layer204, and sidewalls of the ILD layer104. A dielectric structure120overlies the top electrode118and surrounds outer sidewalls of the top electrode118. A top electrode via (TEVA)316overlies the top electrode118and electrically couples the top electrode118to a first overlying interconnect structure318. In some embodiments, the TEVA316is narrower than the top electrode118. In some embodiments, a bottom surface of the first overlying interconnect structure318overlies the TEVA316and extends laterally past opposing sidewalls of the TEVA316.

The logic region302bcomprises an underlying interconnect structure320disposed within the ILD layer104. In some embodiments, the underlying interconnect structure320is electrically coupled to transistor structure314of the logic region302b. The etch stop layer204overlies the underlying interconnect structure320. In some embodiments, outer sidewalls of the underlying interconnect structure320are laterally between inner sidewalls of the etch stop layer204. An inter-tier interconnect structure322is disposed within the dielectric structure120, and electrically couples the underlying interconnect structure320to a second overlying interconnect structure324. In some embodiments, the inter-tier interconnect structure322has a maximum width at a top surface of the inter-tier interconnect structure322.

In some embodiments, the contact plug312, the TEVA316, the first overlying interconnect structure318, the underlying interconnect structure320, the inter-tier interconnect structure322, and the second overlying interconnect structure324are conductive and may be or otherwise comprise, for example, tungsten, aluminum copper, copper, aluminum, some other suitable metal(s), or some other suitable conductive material(s). The lower ILD layer310may be or otherwise comprise, for example, nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or some other suitable material(s). The gate structure308may be or otherwise comprise, for example, doped polysilicon, metal, or some other suitable conductive material(s).

In some embodiments, the conductive barrier layer108may be or otherwise comprise, for example, tantalum, tantalum nitride, titanium, titanium nitride, tungsten carbide, or some other suitable material(s). In some embodiments, the BEVA112may comprise a conductive material having a relatively low diffusivity (e.g., less than or equal to approximately 10−9cm2/s, less than or equal to approximately 10−10cm2/s, less than or equal to approximately 10−11cm2/s, or other similar values) and a relatively low resistivity (e.g., less than or equal to approximately 15μ(micron)-Ohm-cm, less than or equal to approximately 10μ-Ohm-cm, less than or equal to approximately 5μ-Ohm-cm, or other similar values). In various embodiments, the conductive material of the BEVA112may be or otherwise comprise, for example, tungsten, nickel, cobalt, platinum, gold, iron, or the like. The relatively low diffusivity of the conductive material allows for the BEVA112to be disposed within the dielectric layer110without a surrounding diffusion barrier layer. Having the conductive material of the BEVA without a surrounding diffusion barrier layer allows for the conductive material to have a relatively wide width that provides for a good resistance, while still being covered by the dielectric layer110to protect from re-deposition during manufacturing. Therefore, having the BEVA comprise a conductive material that has both a low resistivity and a low diffusivity allows for the BEVA of the disclosed IC to have a resistance that may be lower than that of a conventional BEVA.

For example,FIG. 4illustrates a graphical representation400of an exemplary relationship between resistance and bottom electrode via (BEVA) width in an integrated circuit (IC). The IC may be, for example, the IC ofFIG. 1.

A first line402represents a conventional BEVA with a first height and a first resistivity. A second line404represents a disclosed BEVA with a second height and a second resistivity. The first height larger than the second height, and the first resistivity larger than the second resistivity. The x-axis represents a resistance of the BEVA, while the Y axis represents a width of the BEVA. As shown inFIG. 4, despite using a smaller BEVA width, the disclosed BEVA still has a lower resistance than a conventional BEVA due to a small height of the BEVA and the low resistivity and diffusivity of the BEVA. Thus, by using a shorter, low-resistivity BEVA, a narrower BEVA can be implemented, ensuring that during an etch of the data storage structure, no metallic by-product from the BEVA can be re-deposited on sidewalls of the data storage structure, while still minimizing power consumption impact of high resistance.

With reference toFIGS. 5-18, a series of cross sections500-1800illustrate some embodiments of a method for forming an integrated chip (IC) comprising a plurality of memory regions with a bottom electrode via (BEVA) having a narrow width that is configured to reduce shorting due to re-deposition of a conductive material during manufacturing. AlthoughFIGS. 5-18are described in relation to a method, it will be appreciated that the structures disclosed inFIGS. 5-18are not limited to such a method, but instead may stand alone as structures independent of the method.

As illustrated by the cross-sectional view500ofFIG. 5, an interconnect structure106is formed within an inter-layer dielectric (ILD) layer104over a semiconductor substrate102. In some embodiments, the semiconductor substrate102may be or otherwise comprise, for example, a bulk silicon substrate, a bulk germanium substrate, a group III-V substrate, or some other suitable semiconductor substrate. In some embodiments, the ILD layer104may be or otherwise comprise, for example, nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or some other suitable material(s). In some embodiments, the interconnect structure106is conductive and may be or otherwise comprise, for example, tungsten, aluminum copper, copper, aluminum, some other suitable metal(s), or some other suitable conductive material(s).

In some embodiments, the ILD layer104may be formed by way of a deposition process (e.g., a chemical vapor deposition (CVD) process, a plasma enhanced CVD process, a physical vapor deposition process, or the like). In some embodiments, the interconnect structure106may be formed by way of a damascene process (e.g., a single damascene process, a dual damascene process), in which the ILD layer104is selectively patterned to form an opening that is subsequently filled with a conductive material.

As illustrated by the cross-sectional view600ofFIG. 6, a conductive barrier structure602is formed over the ILD layer104. In some embodiments, the conductive barrier layer108may be formed to a height H1. In various embodiments, the height H1may be between approximately 3 nm and approximately 15 nm, between approximately 5 nm and approximately 30 nm, or other similar values. In some embodiments, the conductive barrier structure602may be formed by way of a deposition process (e.g., a chemical vapor deposition (CVD) process, a plasma enhanced CVD process, a physical vapor deposition process, or the like). In some embodiments, the conductive barrier structure602may be or otherwise comprise, for example, tantalum, tantalum nitride, titanium, titanium nitride, tungsten carbide, or some other suitable material(s).

As illustrated by the cross-sectional view700ofFIG. 7, the conductive barrier structure602is patterned by a first etching process to form a conductive barrier layer108in respective ones of a plurality of memory regions202, such that a first memory region202aand a second memory region202brespectively comprise a conductive barrier layer108overlying respective portions of the interconnect structure106. The first etching process may be or otherwise comprise, for example, a wet etching process, or a dry etching process. In various embodiments, the wet etching process may utilize a wet etchant comprising hydrofluoric acid (HF), potassium hydroxide (KOH), an alkali wet etchant, or the like. In some embodiments, the dry etching process may utilize a dry etchant comprising a plasma etchant, an ion bombardment etchant, or the like. In some embodiments, the first etching process removes a portion of the ILD layer104such that the ILD layer104that is directly below the conductive barrier layer108protrudes outward from an upper surface of the ILD layer104by a distance D1after the first etching process is completed. In some embodiments, the distance D1may range from approximately 5 nanometers to approximately 15 nanometers, from approximately 2 nanometers to approximately 20 nanometers, or other similar values.

As illustrated by the cross-sectional view800ofFIG. 8, an etch stop structure802is formed over the ILD layer104and the conductive barrier layer108. The etch stop structure802may be formed to have a thickness ranging from 10 nanometers to 40 nanometers. The etch stop structure802may be formed by way of a deposition process (e.g., a chemical vapor deposition (CVD) process, a plasma enhanced CVD process, a physical vapor deposition process, or the like). In some embodiments, the etch stop structure802may be or otherwise comprise, for example, silicon dioxide, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide, silicon oxycarbide), some other suitable etch stop material(s), or a combination of the aforementioned materials.

As illustrated by the cross-sectional view900ofFIG. 9, a dielectric material902is formed over the etch stop structure802. The dielectric material902may be formed by way of a deposition process (e.g., a chemical vapor deposition (CVD) process, a plasma enhanced CVD process, a physical vapor deposition process, or the like). In some embodiments, the dielectric material902may be or otherwise comprise, for example, silicon dioxide, silicon nitride, some other suitable low-k dielectric(s), or any combination of the foregoing.

As illustrated by the cross-sectional view1000ofFIG. 10, a hole1002is etched in the dielectric material902and the etch stop structure802over the conductive barrier layer108by a second etching process. In some embodiments, the hole1002is etched into respective ones of the plurality of memory regions202. In some embodiments (not shown), the second etching process may be performed by forming a mask (e.g., a hard mask, a photoresist, or the like) over the dielectric material902, then exposing the dielectric material902to an etchant according to the mask to form the hole1002. The mask is then removed after performing the second etching process.

As illustrated by the cross-sectional view1100ofFIG. 11, a bottom electrode via (BEVA)112is formed in the hole1002. In some embodiments, the BEVA112is formed by depositing a conductive material within respective ones of the plurality of memory regions202. A planarization process is subsequently performed to remove the conductive material from over a top surface of the dielectric material902to form the BEVA112. The BEVA112has a second height H2. In some embodiments, the second height H2may range from approximately 30 nanometers to approximately 80 nanometers, from approximately 30 nanometers to approximately 100 nanometers, from approximately 20 nanometers to approximately 150 nanometers, or other similar values. The planarization process may be or otherwise comprise, for example, a chemical-mechanical planarization (CMP), grinding, an etch, or some other suitable process. In various embodiments, the conductive material may be deposited by a deposition process that may be or otherwise comprise, for example, chemical vapor deposition, physical vapor deposition, sputtering, and/or a plating process (e.g., an electroplating process, an electro-less plating process). In some embodiments, the conductive material may be or otherwise comprise, for example, tungsten, nickel, cobalt, platinum, gold, iron, or some other suitable low resistivity and slow diffusivity conductive material(s).

As illustrated by the cross-sectional view1200ofFIG. 12, a bottom electrode structure1202is formed over the dielectric material902and the BEVA112, such that the bottom electrode structure1202continuously extends to respective ones of the plurality of memory regions202. In some embodiments, the bottom electrode may have a thickness ranging from approximately 5 nanometers to approximately 30 nanometers, from approximately 10 nanometers to approximately 45 nanometers, or other similar values. The bottom electrode structure1202may be or otherwise comprise, for example, tantalum, titanium, tungsten, titanium nitride, tantalum nitride, or the like. The bottom electrode structure1202may be formed by, for example, chemical vapor deposition, physical vapor deposition, sputtering, and/or a plating process (e.g., an electroplating process, an electro-less plating process).

As illustrated by the cross-sectional view1300ofFIG. 13, a data storage element1302is formed over the bottom electrode structure1202, such that the data storage element1302continuously extends to respective ones of the plurality of memory regions202. In some embodiments, forming the data storage element1302comprises forming a seed structure1304over the bottom electrode structure1202, forming a MTJ structure1306over the seed structure1304, and forming an encapsulation structure1308over the MTJ structure1306. In further embodiments, forming the MTJ structure1306comprises forming a pinned ferromagnetic structure1306aover the seed structure1304, forming a tunnel dielectric structure1306bover the pinned ferromagnetic structure1306a, and forming a free ferromagnetic structure1306cover the tunnel dielectric structure1306b. The free ferromagnetic structure1306cand the pinned ferromagnetic structure1306amay be or otherwise comprise, for example, a cobalt-iron-boron alloy, a cobalt-iron alloy, a nickel-iron alloy, or any suitable ferromagnetic material(s). The tunnel dielectric structure1306bmay be or otherwise comprise, for example, magnesium oxide, another suitable oxide, or any suitable dielectric material(s). The seed structure1304may be or otherwise comprise, for example, tantalum nitride, magnesium, cobalt, nickel, chromium, platinum, manganese, some other suitable material(s), or a combination of the foregoing. The encapsulation structure1308may be or otherwise comprise, for example, ruthenium, molybdenum, cobalt, iron, boron, magnesium, magnesium oxide, some other suitable material(s), or a combination of the foregoing. The seed structure1304, the encapsulation structure1308, the free ferromagnetic structure1306c, the tunnel dielectric structure1306b, and the pinned ferromagnetic structure1306amay be formed by, for example, deposition processes (e.g., a chemical vapor deposition (CVD) process, a plasma enhanced CVD process, a physical vapor deposition process, or the like).

As illustrated by the cross-sectional view1400ofFIG. 14, a top electrode structure1402is formed over the data storage element1302, such that the top electrode structure1402continuously extends to respective ones of the plurality of memory regions202. In some embodiments, the top electrode structure1402may be formed to have a thickness ranging from approximately 15 nanometers to approximately 50 nanometers, from approximately 10 nanometers to approximately 75 nanometers, or other similar values. The top electrode structure1402may be or otherwise comprise, for example, tantalum, titanium, tungsten, titanium nitride, tantalum nitride, or the like. The top electrode structure1402may be formed by, for example, chemical vapor deposition, physical vapor deposition, sputtering, and/or a plating process (e.g., an electroplating process, an electro-less plating process).

As illustrated by the cross-sectional view1500ofFIG. 15, the top electrode structure1402is patterned by a third etching process. In some embodiments (not shown), the third etching process may be performed by forming a mask (e.g., a hard mask, a photoresist, or the like) over the top electrode structure1402, then exposing the top electrode structure1402to an etchant according to the mask to define a pattern for the top electrode structure1402. In some embodiments, the top electrode structure1402is patterned to form a top electrode118in separate portions overlying the BEVA112in respective ones of the plurality of memory regions202. The mask is then removed after performing the third etching process.

As illustrated by the cross-sectional view1600ofFIG. 16, the data storage element1302and the bottom electrode structure1202are patterned by a fourth etching process to respectively form sidewalls of a data storage structure116and a bottom electrode114, such that respective ones of the plurality of memory regions202comprise an individual data storage structure116and an individual bottom electrode114. In some embodiments, the fourth etching process further etches the dielectric material902and the etch stop structure802to respectively form sidewalls of a dielectric layer110and an etch stop layer204, such that respective ones of the plurality of memory regions202comprise a dielectric layer110and an etch stop layer204. In further embodiments, the fourth etching process further etches a portion of the ILD layer104to form sidewalls of the ILD layer104laterally between the first memory region202aand the second memory region202b. In some embodiments (not shown), the fourth etching process may be performed by using the top electrode118as a hard mask, and exposing the data storage element1302to an etchant according to the top electrode118.

As illustrated by the cross-sectional view1700ofFIG. 17, a sidewall spacer208is formed along the sidewalls of the top electrode118, the sidewalls of the data storage structure116, and the sidewalls of the bottom electrode114of respective ones of the plurality of memory regions202. In some embodiments, the sidewall spacer208continuously extends along the sidewalls of the dielectric layer110, the sidewalls of the etch stop layer204, and the sidewalls of the ILD layer104of respective ones of the plurality of memory regions202. In some embodiments (not shown), laterally extending portions of the sidewall spacer208are formed over a top surface of the top electrode118and along a top surface of the ILD layer104. In further embodiments, the laterally extending portions of the sidewall spacer208are removed by a removal process. In some embodiments, a portion of the sidewall spacer208laterally aligned with the bottom electrode114comprises sidewalls tilted at a first angle A1measured with respect to a top surface of the dielectric layer110. In further embodiments, a portion of the sidewall spacer208laterally aligned with the dielectric layer110comprises sidewalls tilted at a second angle A2different than the first angle A1measured with respect to a top surface of the ILD layer104. The sidewall spacer208may be or otherwise comprise, for example, silicon dioxide, silicon nitride, titanium nitride, any other suitable material(s), or any combination of the foregoing. The sidewall spacer208may be formed by, for example, a deposition process (e.g., a chemical vapor deposition (CVD) process, a plasma enhanced CVD process, a physical vapor deposition process, or the like). The removal process may be or otherwise comprise, for example, a wet etching process. In various embodiments, the wet etching process may utilize a wet etchant comprising hydrofluoric acid (HF), potassium hydroxide (KOH), an alkali wet etchant, or the like.

As illustrated by the cross-sectional view1800ofFIG. 18, a dielectric structure120is formed over the top electrode118. In some embodiments, the dielectric structure120continuously extends over both the first memory region202aand the second memory region202b. The dielectric structure120may be or otherwise comprise, for example, silicon dioxide, silicon nitride, titanium nitride, any other suitable material(s), or any combination of the foregoing. The dielectric structure120may be formed by, for example, a deposition process (e.g., a chemical vapor deposition (CVD) process, a plasma enhanced CVD process, a physical vapor deposition process, or the like). The removal process may be or otherwise comprise, for example, a wet etching process.

With respect toFIG. 19, a flowchart1900illustrates some embodiments of a method for forming an integrated chip (IC) comprising a plurality of memory regions with a narrow bottom electrode via (BEVA). The method may, for example, correspond to the method ofFIGS. 5-18.

At act1902, an interconnect structure is formed within an inter-layer dielectric (ILD) layer over a semiconductor substrate.FIG. 5illustrates a cross-sectional view500of some embodiments corresponding to act1902.

At act1904, a conductive barrier structure is formed over the ILD layer.FIG. 6illustrates a cross-sectional view600of some embodiments corresponding to act1904.

At act1906, the conductive barrier structure is patterned to form a conductive barrier layer in respective ones of a plurality of memory regions.FIG. 7illustrates a cross-sectional view700of some embodiments corresponding to act1906.

At act1908, an etch stop structure is formed over the conductive barrier layer and the ILD layer.FIG. 8illustrates a cross-sectional view800of some embodiments corresponding to act1908.

At act1910, a dielectric material is formed over the etch stop structure.FIG. 9illustrates a cross-sectional view900of some embodiments corresponding to act1910.

At act1912, a hole is etched into the dielectric material and the etch stop structure over the conductive barrier layer.FIG. 10illustrates a cross-sectional view1000of some embodiments corresponding to act1912.

At act1914, a bottom electrode via (BEVA) is formed into the hole.FIG. 11illustrates a cross-sectional view1100of some embodiments corresponding to act1914.

At act1916, a bottom electrode structure is formed over the BEVA and the dielectric material.FIG. 12illustrates a cross-sectional view1200of some embodiments corresponding to act1916.

At act1918, a data storage element is formed over the bottom electrode structure.FIG. 13illustrates a cross-sectional view1300of some embodiments corresponding to act1918.

At act1920, a top electrode structure is formed over the data storage element.FIG. 14illustrates a cross-sectional view1400of some embodiments corresponding to act1920.

At act1922, the top electrode structure is patterned to form an individual top electrode in respective ones of the plurality of memory regions.FIG. 15illustrates a cross-sectional view1500of some embodiments corresponding to act1922.

At act1924, the data storage element and the bottom electrode structure are patterned according to the individual top electrode to form a data storage structure and bottom electrode in respective ones of the plurality of memory regions.FIG. 16illustrates a cross-sectional view1600of some embodiments corresponding to act1924.

At act1926, a sidewall spacer is formed along sidewalls of the data storage structure.FIG. 17illustrates a cross-sectional view1700of some embodiments corresponding to act1926.

At act1928, a dielectric structure is formed over the plurality of memory regions.FIG. 18illustrates a cross-sectional view1800of some embodiments corresponding to act1928.

Accordingly, in some embodiments, the present disclosure relates to an integrated chip (IC), comprising a bottom electrode overlying an interconnect structure disposed within a lower inter-level dielectric (ILD) layer, a top electrode over the bottom electrode, a data storage structure between the top electrode from the bottom electrode, a conductive barrier layer directly overlying the interconnect structure, and a bottom electrode via (BEVA) vertically separating and contacting a bottom surface of the bottom electrode and a top surface of the conductive barrier layer, wherein a maximum width of the BEVA is less than a width of the data storage structure.

In other embodiments, the present disclosure relates to a method for forming an integrated chip (IC), comprising forming an interconnect structure within an inter-layer dielectric (ILD) layer, forming a conductive barrier layer over the interconnect structure, forming an dielectric material over the barrier layer, forming a bottom electrode via (BEVA) extending from a top surface of the dielectric material to the barrier layer, forming a bottom electrode structure over the BEVA and the dielectric material, forming an data storage element over the bottom electrode structure, forming a top electrode over the data storage element, and etching the data storage element, the bottom electrode structure, and the dielectric material to respectively form outer sidewalls of a data storage structure, outer sidewalls of a bottom electrode, and outermost sidewalls of a dielectric layer, wherein the dielectric layer separates the BEVA from the outermost sidewalls of the dielectric layer.

In yet other embodiments, the present disclosure relates to an integrated chip (IC) integrated chip (IC), comprising a first metal interconnect structure disposed within a lower dielectric structure, a top electrode vertically stacked over a bottom electrode, a magnetic tunnel junction (MTJ) between the top electrode and the bottom electrode, a conductive barrier layer disposed over the first metal interconnect structure, wherein the first metal interconnect structure is narrower than the conductive barrier layer, an etch stop layer arranged along an upper surface and sidewalls of the conductive barrier layer, and a bottom electrode via (BEVA) between the conductive barrier layer and the bottom electrode, wherein a bottommost surface of the bottom electrode continuously extends past opposing outermost sidewalls of the BEVA.