INTERCONNECT STRUCTURES WITH NITROGEN-RICH DIELECTRIC MATERIAL INTERFACES FOR LOW RESISTANCE VIAS IN INTEGRATED CIRCUITS

Integrated circuit structures including an interconnect feature without a higher-resistance liner material. In absence of a liner, metal of low resistance directly contacts an adjacent dielectric material, enabling lower resistance interconnect. Even for low-k dielectric compositions, adhesion of the metal to the dielectric material is improved through the incorporation of nitrogen proximal to the interface. Prior to deposition of the metal upon a surface of the dielectric, the surface is exposed to nitrogen species to form a nitrogen-rich compound at the surface. The metal deposited upon the surface may then be nitrogen-lean, for example a substantially pure elemental metal or metal alloy.

BACKGROUND

Demand for higher performance integrated circuits (ICs) in electronic device applications has motivated increasingly dense transistor architectures. Interconnect parasitics become a greater challenge as the density of interconnect metallization structures keeps pace with transistor density. For example, the resistance-capacitance (RC) delay associated with interconnects of an IC increases with the density of the interconnects.

FIG.1Aillustrates a conventional interconnect structure that includes a metal line101within a first interconnect level. A transverse width of metal line101has some lateral critical dimension CD1. A dielectric material102is over metal line101, and a via opening103is subtractively patterned through dielectric material102in the z-dimension to expose a portion of metal line101. Via opening103has a depth Dv associated with the thickness of dielectric material102. A diameter of via opening103has some lateral critical dimension CD2. Often, CD2is made smaller than CD1by an amount sufficient to ensure via opening103will land fully upon metal line101. The ratio of depth Dv to CD2is referred to as the aspect ratio of via opening103. Metal line width CD1scales down as metal line density increases with increasing transistor density, and so CD2must also scale down and the aspect ratio of via opening103increases.

As further illustrated inFIG.1B, via opening103and trench106is filled with one or more metals to form a metal line108that extends within the x-y plane to intersect conductive material in via opening103so that two interconnect levels are electrically connected. In this example, an interconnect liner material105is on surfaces of trench106and via103to improve adhesion of a fill metal107that would otherwise suffer delamination or other deleterious effects of poor adhesion with dielectric material102. However, liner material105often has significantly higher electrical resistance than fill material107. As structural dimensions scale, liner material105threatens to become a greater portion of an interconnect structure, leading to higher interconnect resistances.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references (e.g., up, down, top, bottom, etc.) may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or layer disposed over or under another may be directly in contact or may have one or more intervening materials or layers. Moreover, one material disposed between two materials or layers may be directly in contact with the two materials/layers or may have one or more intervening materials/layers. In contrast, a first material or layer “on” a second material or layer is in direct contact with that second material/layer. Similar distinctions are to be made in the context of component assemblies.

As used herein, the qualifier “substantially” is employed in the recognition that manufacturing processes output a population characterized by some distribution statistics. Unless explicitly stated otherwise, no more than incidental variation is to be expected between two things that are substantially the same.

Unless otherwise specified in the specific context of use, the term “predominantly” means more than 50%, or more than half. For example, a composition that is predominantly a first constituent means more than half of the composition is the first constituent (e.g., >50 at. %). The term “primarily” means the most, or greatest, part. For example, a composition that is primarily a first constituent means the composition has more of the first constituent than any other constituent. A composition that is primarily first and second constituents means the composition has more of the first and second constituents than any other constituent. The term “substantially” means there is only incidental variation. For example, composition that is substantially a first constituent means the composition may further include <0.5 at. % of any other constituent. A composition that is substantially first and second constituents means the composition may further include <0.5 at. % of any constituent substituted for either the first or second constituent.

Described below are examples of integrated circuit (IC) structures having an interconnect feature, such as a line or a via, that includes a metal in direct contact with a dielectric material. Advantageous for highest electrical conductivity, the metal has a low concentration of impurities, such as nitrogen. In accordance with embodiments herein, the dielectric material is also of low nitrogen content, which may be advantageous for lowest relative permittivity. However, adhesion of the metal to the dielectric material is enhanced by introducing nitrogen into a surface thickness of the dielectric material. By treating only the surface of the dielectric material, nitrogen content may remain low within a majority of the dielectric material. Where the incorporation of nitrogen in the surface of the dielectric material improves adhesion sufficiently, interconnect features may be substantially linerless, or liner-free. In absence of any liner, an entirety of the metal in the interconnect feature may have high electrical conductivity.

As described below, one or more techniques may be integrated into a damascene metal interconnect process, or a subtractively patterned metal interconnect process, to introduce nitrogen into a dielectric material surface that will be in direct contact with a subsequently deposited metal. As such, a portion of the dielectric material, for example after via opening and/or trench patterning, may be modified for improved adhesion. A metal subsequently deposited, for example by physical vapor deposition (PVD) or chemical vapor deposition (CVD), may then bind more strongly to a nitrogen-based ligand (e.g., —NH) at the dielectric surface than in would otherwise to an oxygen-based ligand (e.g., —OH).

FIG.2is a flow chart of methods200for fabricating one or more levels of an integrated circuit interconnect structure including a metal in direct contact with a nitrogen-enriched regions of a dielectric material, in accordance with some embodiments. Methods200begin at input201where a workpiece including a dielectric material is received. The workpiece may be as a large format (e.g., 300-450 mm) semiconductor wafer, for example. The wafer may include a Group IV semiconductor material layer (e.g., Si, Ge, SiGe, GeSn, etc.), a Group III-V semiconductor material layer, a Group II-VI semiconductor material layer, or the like. The workpiece may include one or more underlying device layers including a semiconductor material layer and may also have one or more interconnect levels interconnecting devices (e.g., transistors) of the device layer(s).

On a surface of the workpiece there is a dielectric material, which may have any chemical composition suitable for an IC interlayer dielectric (ILD). In advantageous embodiments, the dielectric material has a low nitrogen content (e.g., <<1at. %) ensuring a low bulk relative permittivity. The dielectric material may be, for example, silicon-based with oxygen being another primary constituent. In some embodiments, the dielectric material may include SiO2, and have a relative permittivity of about 3.5. However, in exemplary embodiments, the dielectric material has a low-k composition, for example having a relative permittivity less than 3.5, and more specifically in the range of 2.2-3.0. There are many such low-k dielectric materials, with several of them also including silicon and oxygen as primary constituents supplemented with various other constituents, such as carbon, and hydrogen, that stabilize a microstructure of lower density/greater porosity, etc.

In some damascene embodiments, methods200continue at block205where at least one of a trench or via opening is subtractively patterned into the dielectric material. The trench and/or via interconnect structure may be any “dual-damascene” or “single-damascene” type structure patterned into the dielectric material, for example. Block205is illustrated in dashed line to emphasize that the dielectric material need not be patterned, with block205skipped, for example if the dielectric material received at input201was planarized with a lower level of interconnect metal features upstream of methods200.

In dual-damascene embodiments, both a trench and a via opening are patterned into the dielectric material at block205. In single-damascene embodiments, only a via opening is patterned in a first iteration of block205. The trench and/or via opening patterned at operation205may expose some underlying land, such as a lower-level interconnect metallization feature. For example, in some dual-damascene interconnect fabrication processes, the via opening, but not the trench, exposes some region of an underlying line or via of a lower-level interconnect structure, or exposes some region of an underlying device terminal metallization. In an exemplary single-damascene interconnect fabrication process, a via opening exposes some region of an underlying metallization via or line of a lower-level interconnect structure or exposes some region of an underlying device terminal metallization.

At block210, a working surface of the dielectric material is exposed to a nitrogen species to incorporate nitrogen into a thickness of the dielectric material proximal to the surface. Advantageously, the nitrogen content is localized to the surface, maintaining a low relative permittivity throughout a remainder (bulk) of the dielectric material. For embodiments where the dielectric material is patterned at block205, nitrogen is introduced through surfaces of the trench and/or via opening, as well as through a top surface of the dielectric material. In other embodiments, where the dielectric material is unpatterned, nitrogen is incorporated into only the top, planarized surface of the dielectric material.

In some exemplary embodiments, at block210the dielectric material surface(s) are exposed to a nitrogen species activated by energizing a nitrogen source gas with a direct or remote plasma. Nitrogen source gases, such as, but not limited to, N2, N2O, NH3, N2H4, or N2:H2(e.g., a 4% forming gas) may be energized with an RF or magnetron source, for example. In some other embodiments, block210entails exposing the dielectric material surface to a transient thermal process, such as, but not limited to, a flash anneal, laser anneal, or rapid thermal anneal, practiced in the presence of a nitrogen source gas, such as any of those described above. In some other embodiments, the dielectric material surface may be exposed to ion or electron beam irradiation in the presence of a nitrogen source gas, which may implant nitrogen into a surface thickness of the dielectric material. Notably, the methods practiced at block210do not deposit a thin film over the dielectric material, but rather modify the chemical composition of the existing dielectric material near the surface to be nitrogen-enriched.

Following nitrogen enrichment, at block215a metal is deposited directly upon the nitrogen-enriched dielectric material surface. The metal deposited is advantageously of low nitrogen content, for example to ensure high electrical conductivity. The metal may be deposited by any technique known to be suitable for the particular metal and/or capable of adequately filling any topographic features (e.g., via openings and/or trenches) in the dielectric material. In some exemplary embodiments, metal is deposited by PVD. In other embodiments, metal is deposited by CVD, or atomic layer deposition (ALD). An electrolytic plating process may also be practiced at operation215. Although any metal may be deposited at block215, in some advantageous embodiments the metal comprises predominantly one of Ru, Mo, or a NiAl alloy. In some advantageous embodiments, substantially pure Ru is deposited at block215. In other advantageous embodiments, substantially pure Mo is deposited at block215. In some other advantageous embodiments, NiAl alloy having a Nickel at. % of 40-70 is deposited at block215. Regardless of the metal(s) deposited at block215, the nitrogen content of the metal formed is advantageously below 1 at. %, and ideally comprises no more than a trace (e.g., below 0.3 at. %) of nitrogen.

In further embodiments, multiple deposition processes may be practiced at block215. Deposition of the metal may comprise two or more of any of PVD, CVD, ALD, or electroless plating. For example, an electrolytic plating process may be preceded by physical vapor deposition (PVD) of a seed layer. Regardless of how many deposition processes may be practiced at block215, various layers of metal deposited at block215may have substantially the same composition, or not.

For damascene embodiments, block215may be completed with a planarization (e.g., CMP) of the metal and the dielectric material, which exposes a top surface of the dielectric material surrounding metal within a trench or via opening. As described further below, the planarization process may remove the nitrogen-enriched region of the dielectric material beyond a perimeter of an interconnect structure, or not, depending on the amount of over polish.

For dual-damascene embodiments, methods200are substantially complete following block215with one level of interconnect metal fabricated. Methods200may be repeated for each successive interconnect level that is to include a dual-damascene interconnect structure. With each iteration, additional dielectric material may be deposited at block225, for example with any CVD, plasma-enhanced (PE) CVD, or spin-on process known to be suitable for a dielectric material of a desired composition. In some embodiments, the dielectric material deposited at block225has substantially the same composition as the dielectric material received on the workpiece at input201.

Alternatively, in single-damascene embodiments where only a via opening is filled at operation215, methods200continue with operation225where additional dielectric material is deposited over the via structure thus far formed. Methods200may then continue with a second iteration of operation205, for example where a trench is formed in the dielectric material deposited at operation225to expose a portion of the interconnect via formed at block215. Then, at another iteration of block210, nitrogen may again be incorporated into a surface of the dielectric material deposited at operation225. Hence, for single-damascene embodiments, two nitrogen pretreatment operations210may be performed to complete one interconnect level. Methods200may then complete with additional metal deposited again at block215.

In some other embodiments where the metal deposited at block215is amenable to an etch process, the metal may be subtractively patterned at block220. For example, Ru deposited at block215, may be etched at block220with a plasma comprising Cl2, or through an electrochemical atomic layer etch (EALE) process. For embodiments where the metal is subtractively patterned at block220, nitrogen-enriched dielectric material may be retained only below the metal features. An overetch of the metal may, for example, remove nitrogen-enriched regions of the dielectric material adjacent to a metal feature. Following the subtractive etch process, methods200may continue at block225where additional dielectric material is deposited over, and adjacent to sidewalls of, the patterned metal feature. However, as described further below, an interface between a sidewall of the metal feature and this additional dielectric material will not be similarly nitrogen-enriched.

Embodiments of methods200are further described below in the context ofFIG.3A-10C.FIG.3A,4A,5A and6Aillustrate a plan view of a portion of an IC interconnect structure301evolving as the methods200are practiced, in accordance with some dual-damascene embodiments.FIG.3B,4B,5B and6Bfurther illustrate a cross-sectional view of a portion of IC interconnect structure301evolving, in accordance with some dual-damascene embodiments.

Referring first toFIG.3AandFIG.3B, interconnect structure301includes a via opening315through a thickness T1of a material330. Thickness T1may vary with implementation, but in some exemplary embodiments is 10 nm-50 nm. An underlying metallization feature (e.g., a line)310is exposed at a bottom of via opening315. Metallization feature310is in a lower interconnect level below dielectric material330. Metallization feature310may have any composition, with some examples including copper, tungsten, titanium, molybdenum, cobalt, ruthenium, ruthenium-cobalt alloy, or a nickel-aluminum alloy. InFIG.3A, portions of metallization feature310outlined in dashed line are below the working surface.

Interconnect structure portion301further includes trench341over via opening315, within a thickness T2of dielectric material330. Thickness T2may vary with implementation, but in some exemplary embodiments is 10-50 nm, or more. Another trench342laterally spaced apart from trench341is further illustrated, and the cross-section of trench342shown inFIG.3Bis representative of a cross-section of trench341out of the plane of theFIG.3Bwhere there is no via opening315. As shown inFIG.3A, trench341has a longitudinal length L1and a transverse width W1. In exemplary embodiments, longitudinal length L1is significantly (e.g., 3×) larger than transverse width W1Via opening315has a maximum lateral diameter D0, which may vary with implementation, but is generally significantly smaller than the length of a trench (e.g., diameter D0is significantly smaller than longitudinal lengths L1and L2). Trench341has ends somewhere beyond the perimeter of the portion of interconnect structure301illustrated. Trench342is substantially parallel to trench341, but with a shorter longitudinal length L2to further illustrate a trench end.

Although not illustrated, there may be an etch stop material layer over dielectric material330, surrounding trenches341,342. An etch stop material layer may also be present between the thickness T1and thickness T2of dielectric material330, and is represented inFIG.3Bby a dashed line. Although such etch stop layers may have a different chemical composition than dielectric material330, the film thickness of any such etch stop layers is much smaller than thicknesses T1and T2, and so is ignored for the sake of clarity.

Any single-step or multi-step reactive ion etch (RIE) process (e.g., based on a CxFyplasma chemistry) may define trenches341,342and via opening315, as embodiments are not limited in this respect. Trenches341,342and via opening315are depicted with a tapered sidewall and positive slope such that a top width of via opening315having feature diameter DOis slightly larger than the bottom width. While such tapered slope is representative of typical subtractively patterned dielectrics, other profiles are possible as a function of the dielectric etch process.

Dielectric material330may include any dielectric material suitable for electrical isolation of integrated circuitry. Dielectric material330, may be a low-k dielectric material having a relative permittivity below 3.5, for example. In some examples, dielectric material330comprises both silicon and oxygen, and may be any of SiO2, hydrogen silsesquioxane, or methyl silsesquioxane, for example. In further embodiments, dielectric material330comprises significantly less nitrogen than oxygen, and advantageously has a nitrogen content less than 1 at. %, with ideally no more than a trace amount of nitrogen (e.g., <0.3 at. %). Dielectric material330may be deposited as a flowable oxide, for example, and/or may be otherwise planarized to have a substantially planar top surface311.

As further shown inFIG.3B, interconnect structure portion301is over a portion of an underlying substrate that includes a device layer305. A plurality of devices306is within device layer305. In exemplary embodiments, devices306are metal-oxide-semiconductor field effect transistor (MOSFET) structures. However, devices306may also be other transistor types, such as, but not limited to other FET architectures, thin film transistors (TFTs), or tunnel FETs (TFETS), etc. Devices306may also be devices other than transistors that may, for example, include one or more semiconductor junctions (e.g., diodes, etc.).

In the example further illustrated inFIG.4AandFIG.4B, surfaces of dielectric material330are exposed to nitrogen species401, activated for example by plasma, a transient thermal process, or ion/electron beam radiation. The nitrogen enters dielectric material330and reacts with constituents, such as silicon and hydrogen, of dielectric material330to form compounds containing nitrogen (e.g., saturated and/or unsaturated amine and/or amide groups, such as —N, —NH, —NH2, —CON, CONH, —CONH2).

As shown, nitrogen enters dielectric material330to form a nitrogen-enriched dielectric sidewall region450A within both trench342and via opening315. In contrast to a thin film deposition, nitrogen treatment of dielectric330therefore retains feature diameter D0, with nitrogen entering dielectric330to some treated diameter D1, larger than feature diameter D0. The nitrogen-enriched sidewall dielectric region450A has a thickness T3within which the nitrogen concentration is higher than within other regions of dielectric material330unshaded inFIG.4B. In some exemplary embodiments, thickness T3is less than 10 nm (e.g., 5-8 nm). Nitrogen also reacts with dielectric material330to form a nitrogen-enriched trench bottom dielectric region450B, which may also have the thickness T3. In the illustrated example, nitrogen also reacts with the planar top surface of the dielectric to form a nitrogen-enriched dielectric top surface region450C, which may also have the thickness T3.

Nitrogen may also react with metallization feature310, for example exposed at the bottom of via315, to form a nitrogen-enriched metal region450D. However, the reactivity of the nitrogen species with metallization feature310may be low as a result of the chemical composition of metallization feature310. Nitrogen-enriched metal region450D may therefore be undetectable, or, if detectable, will typically have a lower peak nitrogen concentration than nitrogen-enriched trench bottom dielectric region450B as well as a thickness T4that is significantly less than thickness T3. For example, in some embodiments where thickness T3is 5-8 nm, thickness T4is only 1.5-3 nm. Although illustrated as continuous surface regions, nitrogen-enriched sidewall region450A, nitrogen-enriched trench bottom dielectric region450B, nitrogen-enriched dielectric top surface region450C, and nitrogen-enriched metal region450D may each be discontinuous.

FIG.4Cis a graph illustrating a nitrogen concentration profile through a portion of a dielectric material330, in accordance with some embodiments. As shown, within nitrogen-enriched region450the nitrogen content increases with proximity to the surface (depth=0). In this example, at depths beyond thickness T3, the composition of dielectric material is substantially homogeneous and comprises only a trace of nitrogen (e.g., <0.3at. %). The low, but non-zero, background nitrogen content of dielectric material330may be attributable to a precursor employed in the deposition of dielectric material330, for example. Within thickness T3, nitrogen content increases monotonically from the background level to a concentration peak at the surface. In some embodiments, the peak concentration of nitrogen is less than 10 at. %, and may be, for example, between 1 at. % and 10 at. %. The monotonic increase in nitrogen content with proximity to the surface of dielectric material330illustrates a gradient distinct from the more abrupt transitions of a film stack comprising multiple dielectric layers of different nitrogen content, sequentially deposited for example.

FIG.5AandFIG.5Bfurther illustrate an example following deposition of an interconnect metal555by any technique suitable for the particular metal, such as PVD, CVD or ALD. Metal555is in direct physical contact with nitrogen-enriched regions of dielectric material330. In this example, metal555completely fills via opening315and trenches341,342. In absence of any metal liner, metal555occupies the full feature diameter D0. Several metals display higher binding energies with amine groups than hydroxyl groups and, although not bound by theory, the higher metal adhesion strength measured for embodiments herein may be attributable to these higher binding energies as the nitrogen surface treatment is thought to increase the amount of amine groups relative to hydroxyl groups at the surface of dielectric material330.

As noted above, metal555may be one or more metals. In some exemplary embodiments metal555comprises Ru, Mo, or NiAl. Although alloys are possible, in some embodiments, metal555is substantially pure Ru having only trace impurities. In other examples metal555is substantially pure Mo having only trace impurities. In still other embodiments, metal555is a NiAl alloy. Regardless of the metal constituent(s), nitrogen content within metal555is advantageously low (e.g., less than 1 at. % and more advantageously less than 0.3 at. %).

Depending on the implementation, nitrogen treatment may be performed ex-situ of the deposition process employed to form metal555, or performed as an in-situ nitrogen pretreatment where the treatment may be properly integrated into a metal deposition process.

As further illustrated inFIG.5B, metal555is also in direct physical contact with metallization feature310. For some embodiments where a nitrogen-enriched bottom metal region450D is present, there will be an interconnect metal nitrogen content peak at the interface between the metal555and the underlying metal of feature310of lower nitrogen content. However, any nitrogen-enriched bottom metal region450D should not significantly increase interconnect electrical resistance as the peak concentration is expected to be less than 10 at. %, and the thickness of nitrogen-enriched metal should be only a couple of nanometers.

In the example further illustrated inFIG.6AandFIG.6B, metal555has been patterned into metal interconnect features660through a planarization process (e.g., CMP) that exposes a top surface of dielectric material330. In the illustrated examples, metal interconnect feature660substantially backfills both via opening315as well as trenches341,342. In this example, an overpolish has removed nitrogen-enriched dielectric top surface region450C. However, in other embodiments, a nitrogen-enriched dielectric top surface region450C may remain after planarization. As illustrated inFIG.6A and6B, interconnect structure301now includes one level of interconnect metallization comprising a linerless line metallization and linerless via metallization in direct contact with nitrogen-enriched dielectric regions450A and450B. Interconnect structure301may be augmented, for example by iterating through methods200, to have any number of levels of interconnect metallization needed for a particular IC.

FIG.6Cis a graph further illustrating a nitrogen concentration profile through a portion of dielectric material and metal interfacing the dielectric material, in accordance with some embodiments. The nitrogen concentration profile illustrated inFIG.6Cfurther demonstrates an exemplary embodiment where interconnect metal feature660has a low background level of nitrogen, far below the peak nitrogen concentration within the nitrogen-enriched dielectric region450. In this example, the concentration of nitrogen within interconnect metal feature660is below 1 at. % even at the interface (depth=0) with the nitrogen enriched dielectric material. Moving away from the dielectric interface within metal feature660, at a distance equal to thickness T3(depth=−T3), nitrogen content is below the background level of nitrogen within dielectric material330, with the exemplary metal having a trace level below 0.3 at. %.

FIG.7A,8A, and9Aillustrate a plan view of a portion of an IC interconnect structure portion701evolving as methods200are practiced, in accordance with some single-damascene embodiments.FIG.7B,8B and9Bfurther illustrate a cross-sectional view of a portion of the IC interconnect structure portion701, in accordance with some embodiments. Reference numbers introduced for IC interconnect structure portion301are retained where one or more of the attributes introduced above are also applicable to interconnect structure portion701.

InFIG.7AandFIG.7B, interconnect structure portion701includes a via715extending through a thickness T1of dielectric material330. Via715comprises a metal that is electrically coupled to underlying metallization feature310. Via715may have been fabricated according to a first single-damascene process, for example. Via715is liner-free, and may comprise a first metal, such as any of those described above (e.g., Ru, Mo, NiAl). Without a liner, the metal is in direct physical contact with metallization feature310, and in direct physical contact with nitrogen-enriched dielectric sidewall region450A. A top surface of via715is exposed at a bottom of trench741patterned into dielectric material330. A second trench742is further illustrated, and is representative of trench741out of the plane of via715. As a result of the separate patterning of via715and trench741, there may be a non-zero lateral offset or profile discontinuity at the interface of the sidewall of trench741and a sidewall of via715.

In the single-damascene example further illustrated inFIG.8AandFIG.8B, surfaces of dielectric material330are again exposed nitrogen treatment401, for example substantially as described above. The nitrogen treatment forms nitrogen-enriched dielectric sidewall regions450A, nitrogen-enriched dielectric trench bottom region450B, and nitrogen-enriched dielectric top surface region450C, substantially as described above. In some embodiments, metal of via715may also become slightly nitrogen enriched within region850C.

As further illustrated inFIG.9AandFIG.9B, following metal deposition and planarization, interconnect metal feature660is again in direct contact with nitrogen-enriched dielectric regions (e.g.,450A and450B). Interconnect structure701is therefore a single damascene structure associated with one level of interconnect metallization comprising a line metallization and via metallization. Interconnect structure701may be augmented, for example by iterating methods200(FIG.2), to have any number of levels of interconnect metallization needed for a particular IC.

FIG.10A-10Dillustrate a cross-sectional view of a portion of an IC interconnect structure evolving as methods200(FIG.2) are practiced, in accordance with some subtractive metal patterning embodiments. Referring first toFIG.10A, an interconnect structure1001includes via715embedded within dielectric material330. Dielectric material330has a top surface1020that is substantially planar with a top surface of via715. In some embodiments, top surface1020comprises primarily oxygen and silicon, and has less than 1 at. % nitrogen.

InFIG.10B, a nitrogen-enriched dielectric surface region450C is formed with a nitrogen pretreatment, for example substantially as described elsewhere herein. Next, as shown inFIG.10C, a metal1055is deposited in direct contact with via715, and in direct contact with nitrogen-enriched dielectric surface region450C. Metal1055may be any metal amenable to an etch process, and may be one of those described elsewhere herein (e.g., Ru, Mo, NiAl). As shown inFIG.10D, metal1055is subtractively patterned by practicing any etch process known to be suitable for the particular metal to define interconnect metal features1060. In this example, an overetch of metal1055erodes some of the underlying dielectric material, substantially removing nitrogen-enriched dielectric surface region450C from between adjacent metal features1060. Accordingly, nitrogen-enriched dielectric surface region450C remains only directly under metal features1060. However, if the etch of metal1055has sufficient selectivity, nitrogen-enriched dielectric surface region450C may remain substantially as illustrated inFIG.10C.

Although not depicted, any subsequently deposited dielectric material may be deposited over metal features1060, for example during another iteration of methods200. This dielectric material will be adjacent to sidewalls of metal features1060. However, with such dielectric material deposited after the formation of metal features1060, there will not be a nitrogen-enriched region of dielectric material in direct contact with sidewalls of metal features1060.

The interconnect structures described above may be incorporated into any IC. To illustrate a few examples,FIG.11depicts a mobile computing platform1105and a data server computing platform1106employing an IC with interconnect structures that include a metal in direct contact with a nitrogen-enriched dielectric material, for example as described elsewhere herein. The server platform1106may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing. In one exemplary embodiment, server platform1106includes a microprocessor1101with interconnect structures that include a metal in direct contact with a nitrogen-enriched dielectric material, for example as described elsewhere herein.

The mobile computing platform1105may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform1105may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system1110, and a battery1115. At least one IC of chip-level or package-level integrated system1110includes interconnect structures with a metal in direct contact with a nitrogen-enriched dielectric material, for example as described elsewhere herein. In the example shown in expanded view1150, integrated system1110includes microprocessor1101, which may have interconnect structures that include a metal in direct contact with a nitrogen-enriched dielectric material, for example as described elsewhere herein. Microprocessor1150may be further coupled to a board1160, a substrate, or an interposer. One or more of a power management integrated circuit (PMIC)1130, or an RF (wireless) integrated circuit (RFIC)1125including a wideband RF (wireless) transmitter and/or receiver (TX/RX), may be further coupled to board1160.

Functionally, PMIC1130may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery1115and with an output providing a current supply to other functional modules (e.g., microprocessor1150). As further illustrated, in the exemplary embodiment, RFIC1125has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 4G, 5G, and beyond.

FIG.12is a functional block diagram of an electronic computing device1200, in accordance with an embodiment of the present invention. Computing device1200may be found inside platform1105or server platform1106, for example. Device1200further includes a motherboard1201hosting a number of components, such as, but not limited to, a processor1204(e.g., an applications processor). Processor1204may be physically and/or electrically coupled to motherboard1201. In some examples, processor1204includes interconnect structures with a metal in direct contact with a nitrogen-enriched dielectric material, for example as described elsewhere herein. In general, the term “processor” or “microprocessor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips1206may also be physically and/or electrically coupled to the motherboard1201. In further implementations, communication chips1206may be part of processor1204. Depending on its applications, computing device1200may include other components that may or may not be physically and electrically coupled to motherboard1201. These other components include, but are not limited to, volatile memory (e.g., DRAM1232), non-volatile memory (e.g., ROM1235), flash memory (e.g., NAND or NOR), magnetic memory (MRAM1230), a graphics processor1222, a digital signal processor, a crypto processor, a chipset1212, an antenna1225, touchscreen display1215, touchscreen controller1265, battery1216, audio codec, video codec, power amplifier1221, global positioning system (GPS) device1240, compass1245, accelerometer, gyroscope, speaker1220, camera1241, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. In some exemplary embodiments, at least one of the functional blocks noted above include interconnect structures with a metal in direct contact with a nitrogen-enriched dielectric material, for example as described elsewhere herein.

Communication chips1206may enable wireless communications for the transfer of data to and from the computing device1200. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips1206may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device1200may include a plurality of communication chips1206. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

It will be recognized that the invention is not limited to the embodiments described above, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features as further provided below.

In first examples, an integrated circuit (IC) structure comprises a line or via comprising a metal with less than 1 at. % nitrogen, and a dielectric material in direct contact with the metal along an interface of the line or via. Nitrogen content with the dielectric material increases with proximity to the interface.

In second examples, for any of the first examples the line or via consists of the metal.

In third examples, for any of the first through second examples the metal comprises at least one of Ru, Mo, or Ni.

In fourth examples, for any of the first through third examples the metal is substantially pure Ru or substantially pure Mo.

In fifth examples, for any of the first through fourth examples, the metal is substantially pure Ru.

In sixth examples, for any of the first through third examples the metal is an alloy of Ni and Al.

In seventh examples, for any of the first through sixth examples within 10 nm of the interface, the nitrogen content within the dielectric material is more than 1 at. %, and beyond 10 nm from the interface, the nitrogen content within the dielectric material is less than 1 at. %.

In eighth examples, for any of the first through seventh examples the nitrogen content within the dielectric material peaks at no more than 10 at. %.

In ninth examples, for any of the first through eighth examples the dielectric material comprises silicon and oxygen.

In tenth examples, for any of the first through ninth examples the nitrogen content within the metal over the distance in a second direction from the interface is lower than that of the dielectric material.

In eleventh examples, for any of the first through tenth examples the line or via is in contact with an underlying second line or via comprising a second metal, and nitrogen content within the second metal increases with proximity to a second interface between the metal and the second metal.

In twelfth examples, for any of the eleventh examples the second metal is different than the first metal, a second dielectric material is in direct contact with the metal along a third interface of the second line or via. Nitrogen content within the second dielectric material also increases with proximity to the third interface.

In thirteenth examples, for any of the first through eleventh examples the line or via is a line and the interface is under the line, a second dielectric material is in direct contact with the metal along a sidewall of the line, and wherein nitrogen content within the second dielectric material does is independent of proximity to the interface.

In fourteenth examples, a computer platform comprises a power supply, and an integrated circuit (IC) coupled to the power supply. The IC comprises a device layer comprising a plurality of transistors comprising one or more semiconductor materials, and an interconnect level. The interconnect level further comprises a line or via coupled to one or more of the transistors. The line or via comprises a metal with less than 1 at. % nitrogen. The interconnect level comprises a dielectric material in direct contact with the metal along an interface of the line or via. The chemical composition of the dielectric material comprises silicon and oxygen, and is more nitrogen rich proximal to the interface than distal from the interface.

In fifteenth examples, for any of the fourteenth examples the IC comprises a microprocessor.

In sixteenth examples, a method of fabricating an integrated circuit (IC) structure comprises depositing a dielectric material, introducing nitrogen into the dielectric material through a surface of the dielectric material, depositing a metal in contact with the surface of the dielectric material, patterning the metal into an interconnect feature.

In seventeenth examples, for any of the sixteenth examples introducing the nitrogen comprises exposing the surface of the dielectric material to at least one of a nitrogen species activated by plasma of a source gas comprising nitrogen, a thermal or laser anneal performed in the presence of the source gas comprising nitrogen, or electron or ion beam radiation in the present of the gas comprising nitrogen.

In eighteenth examples, for any of the seventeenth examples the source gas comprising nitrogen comprises at least one of N2, N2O, NH3, N2H4, N2:H2forming gas.

In nineteenth examples, for any of the sixteenth through eighteenth examples depositing the dielectric material comprises depositing a compound comprising less than 1% nitrogen, and introducing nitrogen into the dielectric material increases a content of the nitrogen within the dielectric material to more than1at. % proximal to the surface.

In twentieth examples, for any of the nineteenth examples introducing nitrogen into the dielectric material increases a content of the nitrogen within the dielectric material to no more than 10 at. % within 10 nm of the surface.

In twenty-first examples, for any of the sixteenth through twentieth examples depositing the metal comprises depositing substantially pure Ru or substantially pure Mo.

In twenty-second examples, for any of the sixteenth through twenty-first examples the method further comprises forming at least one of a via opening or a trench in the dielectric material. Introducing the nitrogen into the dielectric material comprises introducing nitrogen into the dielectric material through a surface of the via opening or the trench. Depositing the metal comprises depositing the metal into the via opening or the trench, and patterning the metal comprises planarizing the metal with the dielectric material.