Latch comparator device and operation method thereof

A latch comparator device includes a differential input amplifier coupled between a first system voltage and a second system voltage and including a first differential output signal terminal and a second differential output signal terminal, a latch coupled to a third system voltage including a first latch signal terminal and a second latch signal terminal, a switch module including a first switch device and a second switch device, wherein the first switch device is coupled between the first differential output signal terminal and the second latch signal terminal and the second switch device is coupled between the second differential output signal terminal and the first latch signal terminal, and a third switch device is coupled between the latch and a fourth system voltage.

DETAILED DESCRIPTION

In the specification and the claim of the present invention may use a particular word to indicate an element, which may have diversified names named by distinct manufacturers. The present invention distinguishes the element depending on its function rather than its name. The phrase “comprising” used in the specification and the claim is to mean “is inclusive or open-ended but not exclude additional, un-recited elements or method steps.” In addition, the phrase “electrically connected to” or “coupled” is to mean any electrical connection in a direct manner or an indirect manner. Therefore, the description of “a first device electrically connected or coupled to a second device” is to mean that the first device is connected to the second device directly or by means of connecting through other devices or methods in an indirect manner.

Please refer toFIG. 2, which illustrates a schematic diagram of a latch comparator device20according to an embodiment of the invention. As shown inFIG. 2, the latch comparator device20comprises a differential input amplifier200, a latch202, a switch module204and a third switch device206. The differential input amplifier200is coupled between a first system voltage (such as a stable voltage source VDD) and a second system voltage (such as a grounding voltage GND or other referenced voltage sources), wherein the differential input amplifier comprises a first differential output signal terminal DOP_1and a second differential output signal terminal DOP_2. The latch202is coupled to a third system voltage (such as the same stable voltage source VDD as the first system voltage) and comprises a first latch signal terminal OP_1and a second latch signal terminal OP_2. The switch module204comprises a first switch device2040and a second switch device2042. The first switch device2040is coupled between the first differential output signal terminal DOP_1and the second latch signal terminal OP_2, and the second switch device2042is coupled between the second differential output signal terminal DOP_2and the first latch signal terminal OP_1. Besides, the third switch device206is coupled between the latch202and a fourth system voltage (such as the same grounding voltage GND as the second system voltage).

InFIG. 2, a detailed schematic diagram of the differential input amplifier200is also shown according to an embodiment of the invention. In the embodiment, the differential input amplifier200comprises a differential input module2000, a load module2002and a current source2004. The differential input module2000can be realized via a first input transistor M1and a second input transistor M2, and is not limited herein. The load module2002can be realized via a first load transistor M3and a second load transistor M4, and is not limited herein. The current source2004is only utilized for providing the stable current, and does not limit the scope of the invention.

In the embodiment, the first input transistor M1and the second input transistor M2are realized as the first type MOS transistor (such as the PMOS), and the first load transistor M3and the second load transistor M4are realized as the second type MOS transistor (such as the PMOS). Gates of the first input transistor M1and the second input transistor M2are utilized as a first differential input signal terminal IP_1and a second differential input signal terminal IP_2, respectively. Sources of the first input transistor M1and the second input transistor M2are coupled to one terminal of the current source2004, and drains of the first input transistor M1and the second input transistor M2are coupled to drains of the second load transistor M4and the first load transistor M3, respectively. The drain of the first load transistor M3is coupled to a gate of the first load transistor M3to form the second differential output signal terminal DOP_2. The drain of the second load transistor M4is coupled to a gate of the second load transistor M4to form the first differential output signal terminal DOP_1. Sources of the second load transistor M4and the first load transistor M3are coupled to the first system voltage VDD, and another terminal of the current source2004is coupled to the second system voltage GND.

Noticeably, the transistors M3, M4of the load module2002can be formed as a diode-connected load, and more specifically, can be formed as an NMOS diode-connected load. In other embodiments, the transistors M3, M4can also be replaced as diodes or other numbers/types of diode-connected loads, which is also in the scope of the invention. Certainly, the other embodiments can utilize different types of the load modules due to practical requirements, such as a resistive load, a combination load, an active type load or a passive type load, which is not described herein for brevity.

Please refer toFIG. 2again. The switch module204is coupled between the differential input amplifier200and the latch202, and comprises a first switch device2040and a second switch device2042to be coupled to the first differential output signal terminal DOP_1and the second differential output signal terminal DOP_2, respectively. The first switch device2040and the second switch device2042are correspondingly conducted via a first control signal S_C1. Accordingly, based on conduction conditions of the first switch device2040and the second switch device2042, the first differential output signal terminal DOP_1and the second differential output signal terminal DOP_2are connected or broken with the second latch signal terminal OP_2and the first latch signal terminal OP_1, respectively.

Further, a detailed schematic diagram of the latch202is also shown according to an embodiment of the invention. In the embodiment, the latch202comprises a first latch transistor M5, a second latch transistor M6, a third latch transistor M7and a fourth latch transistor M8, wherein the first latch transistor M5and the second latch transistor M6can be realized as the first type MOS transistor (such as the PMOS) and the third latch transistor M7and the fourth latch transistor M8can be realized as the second type MOS transistor (such as the NMOS).

In detail, within the latch202, gates of the first latch transistor M5and the third latch transistor M7are coupled to each other, and are coupled to the second switch device2042, drains of the second latch transistor M6and the fourth latch transistor M8, to form the first latch signal terminal OP_1. Similarly, drains of the first latch transistor M5and the third latch transistor M7are coupled to each other, and are coupled to the first switch device2040, gates of the second latch transistor M6and the fourth latch transistor M8, to form the second latch signal terminal OP_2.

According to different perspectives, the first latch transistor M5and the third latch transistor M7can be regarded as a first complementary transistor pair, such that a source of the first latch transistor M5is coupled to the third switch device206and a source of the third latch transistor M7is coupled to the third system voltage VDD. Symmetrically, the second latch transistor M6and the fourth latch transistor M8can be regarded as a second complementary transistor pair, such that a source of the second latch transistor M6is coupled to the third switch device206and a source of the fourth latch transistor M8is coupled to the third system voltage VDD. Besides, the first complementary transistor pair and the second complementary transistor pair are coupled to each other via the first latch signal terminal OP_1and the second latch signal terminal OP_2. Noticeably, other structural latches can also be utilized to cooperate with the differential input amplifier200, and do not limit the scope of the invention.

The third switch device206is coupled between the latch202and the ground GND, and is correspondingly conducted via a second control signal S_C2. Preferably, the differential input amplifier200and the latch202are adaptively connected/disconnected to each other via the first control signal S_C1(or regarded as a pre-amplification control signal), and the latch202is adaptively connected/disconnected to the ground GND via the second control signal S_C2(or regarded as a latch control signal).

Referring to operations of the latch comparator device20, the latch comparator device20receives the first differential input signal and the second differential input signal via the first differential input signal terminal IP_1and the second differential input signal terminal IP_2, respectively, and accordingly, the pre-amplification control signal (i.e. the first control signal S_C1) and the latch control signal (i.e. the second control signal S_C2) are utilized to sequentially process a pre-amplification operation, a voltage shift operation and a latch operation, so as to process the analog-to-digital signal conversion for transforming the input differential signals.

Additionally, the latch comparator device20of the embodiment utilizes the switch module204and the third switch device206to be connected/disconnected at different operational periods, so as to effectively isolate electrical connection between the first differential output signal terminal DOP_1, the second differential output signal terminal DOP_2as well as the first latch signal terminal OP_1, the second latch signal terminal OP_2. Thus, the generation of the kick back noise effect can be easily prevented to correspondingly improve the signal conversion accuracy as well as the switch mechanism, so as to increase the processing efficiency of the latch comparator device20.

Noticeably, the embodiment of the invention has the basis of the first system voltage being equivalent to the third system voltage and the second system voltage being equivalent to the fourth system voltage, and does not limit the scope of the invention. In other embodiments, those skilled in the art can adaptively exchange the utilization of the PMOS and the NMOS for practical requirements.

Please refer toFIG. 3, which illustrates a schematic diagram of related signals for processing the analog-to-digital signal conversion of the latch comparator device20according to an embodiment of the invention, wherein the first differential input signal terminal IP_1receives the first differential input signal SIP_1, which can be a constant value as 1.4000 volts in the embodiment, and the second differential input signal terminal IP_2receives the second differential input signal SIP_2, which can be designed as a periodical change, such as a fluctuation from 1.380 volts to 1.402 volts in the embodiment, none of which should limit the scope of the invention. As shown inFIG. 3, a first operational period P1, a second operational period P2and a third operational period P3correspond to changes of the related signals for processing the analog-to-digital signal conversion of the latch comparator device20.

First, within the first operational period P1, the first differential input signal SIP_1is 1.4000 volts, the second differential input signal terminal IP_2is 1.380 volts, the pre-amplification control signal PREAMP is a high level signal and the latch control signal LATCH is a low level signal, such that the first switch device2040and the second switch device2042of the switch module204are conducted and the third switch is disconnected. Under such circumstances, the first differential output signal terminal DOP_1and the second differential output signal terminal DOP_2of the differential input amplifier200are coupled to the first latch signal terminal OP_1and the second latch signal terminal OP_2of the latch202, and the first latch transistor M5and the second latch transistor M6of the latch202are disconnected from the fourth system voltage (the ground GND). Accordingly, the latch202is utilized as a load of the differential input amplifier200, and the latch202samples voltage levels of the first differential output signal and the second differential output signal, such that a first initial voltage level of the first latch output signal SOP_1and a second initial voltage level of the second latch output signal SOP_2are generated at the first latch signal terminal OP_1and the second latch signal terminal OP_2. In other words, the first initial voltage level and the second initial voltage level are stored at the first latch signal terminal OP_1and the second latch signal terminal OP_2of the latch202, respectively.

For example, the first input transistor M1has a gain gm1, the first load transistor M3has a gain gm3, the third latch transistor M7has a gain gm7, and the gain gm7of the third latch transistor is smaller than the gain gm3of the first load transistor M3. Besides, the first differential input signal terminal IP_1and the second differential input signal terminal IP_2are formed to be an input signal voltage difference VIN, and the first latch signal terminal OP_1and the second latch signal terminal OP_2are formed to be an output signal voltage difference VOUT, such that the output signal voltage difference VOUT and the input signal voltage difference VIN, within the first operational period P1, form a ratio of

Next, within the second operational period P2, the pre-amplification control signal PREAMP and the latch control signal LATCH are the low level signals, such that the first switch device2040, the second switch device2042of the switch module204and the third switch206are disconnected, which means that the first differential output signal terminal DOP_1and the second differential output signal terminal DOP_2are disconnected from the first latch signal terminal OP_1and the second latch signal terminal OP_2, and the first latch transistor M5and the second latch transistor M6are disconnected from the fourth system voltage (i.e. the ground GND) as well. Under such circumstances, the latch comparator20processes the voltage shift operation, and the voltage levels of the first latch output signal SOP_1and the second latch output signal SOP_2shift from the first initial voltage level and the second initial voltage level toward the same direction, for example, both increasing by 0.0005 volts. In the embodiment, the voltage level of the first latch output signal SOP_1is 2.167 volts, and the voltage level of the second latch output signal SOP_2is 1.9024 volts.

Last, within the third operational period P3, the pre-amplification control signal PREAMP is the low level signal and the latch control signal LATCH is the high level signal, such that the first switch module2040and the second switch device2042of the switch module204are disconnected and the third switch206is conducted, which means the first differential output signal terminal DOP_1and the second differential output signal terminal DOP_2are disconnected from the first latch signal terminal OP_1and the second latch signal terminal OP_2, and the first latch transistor M5and the second latch transistor M6are connected with the ground GND. Under such circumstances, the latch comparator device20processes the latch operation, and the latch202regenerates voltage levels of the first latch output signal SOP_1and the second latch output signal SOP_2according to the first initial voltage level and the second initial voltage level, and the voltage levels of the first latch output signal SOP_1and the second latch output signal SOP_2comply with voltage levels of the digital signal. This means the voltage level of the second latch output signal SOP 2 equals to the digital signal of VDD, and the voltage level of the first latch output signal SOP_1equals to the digital signal of GND.

Noticeably, another reversal operation can be operated after the latch comparator device20finishes related operations corresponding to the first operational period P1, the second operational period P2and the third operational period P3. Accordingly, the first differential input signal SIP_1is fixed at 1.4000 volts, and the second differential input signal terminal IP_2is changed to be 1.402 volts. The pre-amplification control signal PREAMP and the latch control signal LATCH are the low level signals, and after a period, the pre-amplification control signal PREAMP becomes the high level signal and the latch control signal LATCH maintains the low level signal. Under such circumstances, the voltage levels of the first latch output signal SOP_1and the second latch output signal SOP_2outputted from the first latch signal terminal OP_1and the second latch signal terminal OP_2, respectively, are ready for reversing, which means a newly generated voltage level of the second latch output signal SOP_2is similar to the original variation of the first latch output signal SOP_1, and a newly generated voltage level of the first latch output signal SOP_1is similar to the original variation of the second latch output signal SOP_2. Detailed operations can be referenced based on the related operations corresponding to the first operational period P1, the second operational period P2and the third operational period P3, and are not described herein. In other words, the latch comparator device20can be divided into a normal operational period P0and a reversal operational period Q0, and the mentioned operational periods are symmetrical for the pre-amplification operation, the voltage shift operation and the latch operation, so as to process the analog-to-digital signal conversion for transforming the input differential signals into the outputted digital signals.

In the embodiment, an operational method applying to the latch comparator device20can be derived into an operational process40, as shown inFIG. 4. The operational process40includes the steps as follows:

Step402: The differential input amplifier200receives the first differential input signal SIP_1and the second differential input signal SIP_2, and processes the pre-amplification operation according to the pre-amplification control signal PREAMP and the latch control signal LATCH, so as to output the first initial voltage level and the second initial voltage level at the first latch signal terminal OP_1and the second latch signal terminal OP_2.

Step404: The voltage shift operation is processed according to the pre-amplification control signal PREAMP and the latch control signal LATCH, so as to shift the voltage levels of the first latch output signal SOP_1and the second latch output signal SOP_2from the first initial voltage level and the second initial voltage level toward the same direction.

Step406: The latch operation is processed according to the pre-amplification control signal PREAMP and the latch control signal LATCH, and the voltage levels of the first latch output signal SOP_1and the second latch output signal SOP_2are regenerated to reach a digital signal level according to the first initial voltage level and the second initial voltage level.

Additionally, detailed operations of Step402can be further derived into a pre-amplification operational process50, as shown inFIG. 5. The pre-amplification operational process50includes the steps as follows:

Step502: The pre-amplification control signal PREAMP is the high level signal to conduct the first switch device2040and the second switch device2042, and the latch control signal LATCH is the low level signal to disconnect the third switch206, such that the differential input amplifier200and the latch202are coupled to each other and the latch202is disconnected from the ground GND.

Step504: The gates of the first input transistor M1and the second input transistor M2receive the first differential input signal SIP_1and the second differential input signal SIP_2, and accordingly, the first differential output signal and the second differential output signal are generated at the first differential output signal terminal DOP_1and the second differential output signal terminal DOP_2.

Step506: The latch202samples the voltage levels of the first differential output signal and the second differential output signal, and generates the first initial voltage level of the first latch output signal SOP_1and the second initial voltage level of the second latch output signal SOP_2at the first latch signal terminal OP_1and the second latch signal terminal OP_2, respectively, so as to reach the digital signal level.

Additionally, detailed operations of Step404can be further derived into a voltage shift process60, as shown inFIG. 6. The voltage shift process60includes the steps as follows:

Step602: The pre-amplification control signal PREAMP is the low level signal to disconnect the first switch device2040and the second switch device2042, and the latch control signal LATCH is the low level signal to disconnect the third switch206, such that the differential input amplifier200is disconnected from latch202, and the latch202is disconnected from the ground GND as well.

Step604: The voltage levels of the first latch output signal SOP_1and the second latch output signal SOP_2shift from the first initial voltage level and the second initial voltage level toward the same direction, for example, both increase by 0.005 volts.

Additionally, detailed operations of Step406can be further derived into a latch operational process70, as shown inFIG. 7. The latch operational process70includes the steps as follows:

Step702: The pre-amplification control signal PREAMP is the low level signal to disconnect the first switch device2040and the second switch device2042, and the latch control signal LATCH is the high level signal to conduct the latch202and the third switch206, such that the differential input amplifier200is disconnected from latch202, and the latch202is conducted with the ground GND.

Step704: The latch202regenerates the voltage levels of the first latch output signal SOP_1and the second latch output signal SOP_2according to the first initial voltage level and the second initial voltage level, so as to reach the digital signal level.

Detailed operations of the operational process40, the pre-amplification operational process50, the voltage shift process60and the latch operational process70can be understood via the above embodiments,FIG. 1toFIG. 3and the related paragraphs thereof, which are not described herein. In the embodiment, a voltage level difference of the first differential input signal SIP_1and the second differential input signal SIP_2is only 0.02 volts which is a small signal (i.e. a difference between 1.4 volts and 1.38 volts). After processing the pre-amplification operational process50, the voltage shift process60and the latch operational process70, a larger signal of 0.26 volts is correspondingly obtained across the first latch signal terminal OP_1and the second latch signal terminal OP_2(i.e. a difference between 1.9024 volts and 2.167 volts). Besides, those skilled in the art can simultaneously consider responsive periods, layout areas and gate numbers of the transistors utilized in the embodiment, to adaptively adjust channel conditions of the transistors utilized in the embodiment, so as to obtain a gain ranging from 10 to 20, which does not limit the scope of the invention. Noticeably, the embodiment utilizes the same control signal to simultaneously conduct/disconnect the first switch device2040and the second switch device2042, which does not limit the scope of the invention. Thus, those skilled in the art can adaptively modify conductive periods and/or disconnecting periods of the embodiments, such as separating the conductive periods and/or disconnecting periods by a predetermined period.

In summary, the embodiments of the invention provide a latch comparator device and an operational method thereof, which utilize a plurality of switch devices coupled between a differential input amplifier, a latch and a ground. Based on a pre-amplification control signal and a latch control signal for adaptively connecting/disconnecting the plurality of switch devices at different operational periods, the differential input amplifier and the latch can process a pre-amplification operation, a voltage shift operation and a latch operation at different operational periods, to correspondingly process an analog-to-digital signal conversion for transforming differential input signals (i.e. small value signals) into digital signals (i.e. large value signals). Therefore, the embodiments of the invention can avoid the generation of the kick back noise effect and correspondingly improve signal conversion accuracy as well as processing efficiency thereof, so as to increase application ranges of the latch comparator device.