Microprocessor controlled apparatus

A microprocessor controlled apparatus includes a microprocessor (2) with e.g. eight address lines (A,.sub.0,A.sub.1 . . . A.sub.7) on which signals may be applied by the microprocessor for selectively addressing a peripheral device coupled thereto, and a data device such as a LCD module (1) having data lines to which data signals may be applied for transfer into the data device. Four of the data lines (D.sub.0,D.sub.1,D.sub.2,D.sub.3) are coupled to a sub-set of the microprocessor address lines (A.sub.2,A.sub.3,A.sub.4,A.sub.5) excluding the two address lines (A.sub.0,A.sub.1) associated with the least significant bits. The signals on the sub-set of address lines are thus applied as data signals to the data device. When data is to be transmitted to the data device the microprocessor (2) is caused to execute a sub-routine comprising instructions having addresses such that the signal appearing on the sub-set of address lines remains substantially stable over an extended period of time allowing data to be clocked into the device even when the write timing of the microprocessor is too fast for the device to accept data directly from the data output lines of the microprocessor.

BACKGROUND OF THE INVENTION 
As is conventional in the microprocessor art, the term "line" as used in 
the present specification refers to an individual input/output interface 
of a microprocessor or other device, e.g. in the form of a terminal or a 
conductor connected to such a terminal, on which signals such as address 
or data signals may be applied, and the terms "address line" and "data 
line" are used accordingly. 
A conventional microprocessor has a plurality of address lines on which 
signals may be applied by the microprocessor for selectively addressing a 
peripheral device coupled to the microprocessor. 8-bit microprocessors 
generally have 16 address lines allowing 2.sup.16 =65536 address numbers, 
whereas newer 16-bit microprocessors have either 20 or 24 address lines 
allowing much greater amounts of memory to be addressed more easily. 
Data-receiving devices, such as memories or display devices have a 
plurality of data lines for inputting data signals. Devices which are 
capable of accepting data at a very high rate may have the data lines 
connected directly to data output lines of the microprocessor. However, 
some data-receiving devices, such as for example a conventional liquid 
crystal display (LCD) module are not capable of accepting data at the fast 
write speeds associated with the high clock rates, e.g. 8 MHz, of current 
microprocessors. In this case, rather than slowing down the microprocessor 
clock, it is known to couple the data-receiving device to the 
microprocessor either via port lines on the microprocessor or to include a 
separate hardware latch which serves to slow down the rate at which data 
is input to the device. 
SUMMARY OF THE INVENTION 
According to the present invention there is provided a microprocessor 
controlled apparatus including a microprocessor having a plurality of 
address lines (A.sub.0,A.sub.1, . . . A.sub.n) on which signals may be 
applied by the microprocessor for selectively addressing a peripheral 
device coupled thereto, and a data device including data lines 
(D.sub.0,D.sub.1, . . . D.sub.m) to which data signals may be applied for 
transfer into the data device, wherein the data lines are coupled to a 
sub-set of the microprocessor address lines whereby the signals on the 
sub-set of address lines are applied as data signals to the data device. 
Apparatus in accordance with the invention has the data lines of the data 
device coupled directly to a sub-set of the microprocessor address lines 
so that part of the address appearing on the address lines is applied 
directly as data to the data device. No latch is needed and since a latch 
is a separate hardware device, the cost and space associated with such a 
latch is saved. Moreover, there is no need to use microprocessor port 
lines to latch the data. Consequently the present apparatus configuration 
minimizes the overall number of microprocessor port lines required to 
interface the data-receiving device with the microprocessor. More port 
lines thus remain available for other uses. 
Suitably the microprocessor is adapted to maintain a substantially stable 
signal on each of the sub-set of address lines while the signal on other 
of the address lines is changed. Hence the data signals applied to the 
data lines can be held at the same level over a period long enough to 
permit the data to be written into the data device. 
In a preferred embodiment this is achieved by arranging that the 
microprocessor executes a sub-routine comprising instructions having 
addresses such that the signal appearing on the sub-set of address lines 
remains substantially stable during the execution of said sub-routine. 
Generally the sub-set of address lines will exclude the address lines 
(A.sub.0, . . . A.sub.x) associated with the x least significant bits, 
where x is the number of digits in the binary representation of m+1, and 
m+1 is the number of data lines of the data device which are coupled to 
the sub-set of microprocessor address lines. In this way the signal 
applied to the address lines associated with the x least significant bits 
can be changed, specifically to increment the address and so execute the 
next instruction in the sub-routine, without changing the signal applied 
on the address lines coupled to the data lines of the data device. 
In the particular case where the data device is configured to receive a 
4-bit parallel input, the sub-set of address lines excludes the address 
lines (A.sub.0,A.sub.1) associated with the two least significant bit 
positions. In this case the data device has four data lines 
(D.sub.0,D.sub.1,D.sub.2,D.sub.3) coupled respectively to the address 
lines (A.sub.2,A.sub.3,A.sub.4,A.sub.5) associated with the third to the 
sixth least significant bit positions. 
In the case where the device is an 8-bit device, i.e. the device processes 
data received in blocks of eight bits, it is advantageous to apply data to 
four data lines of the device sequentially in two 4-bit segments or 
so-called "nibbles". This reduces the number of bus lines needed to 
connect to the data device. 
Preferably the sub-routine executed by the sub-routine comprises m "no 
operation" instructions where the microprocessor proceeds to execute the 
next instruction in the sub-routine without performing any specific 
operation; where m is one less than the number of data lines coupled to 
the sub-set of microprocessor address lines. Thus, in the case of a data 
device having four data lines (D.sub.0,D.sub.1,D.sub.2,D.sub.3) coupled 
respectively to the four address lines (A.sub.2,A.sub.3,A.sub.4,A.sub.5) 
the sub-routine comprises three "no operation" instructions. The final 
instruction of the subroutine is an instruction to return to the main 
routine. 
In a particular embodiment in which it is intended to write data into the 
data device, the data device includes a write line to which a write signal 
is applied from the microprocessor during the time the signals on the 
sub-set of address lines are held substantially stable whereby data is 
transferred to the data device from the data lines. 
A microprocessor controlled apparatus in accordance with the invention has 
particular application where the maximum speed at which the data device 
can accept data is less than the speed at which the microprocessor outputs 
data, i.e. the write timing of the microprocessor which is determined by 
the microprocessor's clock rate. A liquid crystal display device is an 
example of such a data device where the applicant has found that the 
invention can be used advantageously.

DETAILED DESCRIPTION OF THE INVENTION 
Referring to FIG. 1, a data device in the form of an LCD module is coupled 
to a microprocessor 2. The LCD module is used for displaying alphanumeric 
data to a user in accordance with display and control data applied 
thereto, as described in more detail. The LCD may form part of a 
user-interface including additionally, for example, a data-input device 
(typically a keyboard) of an electronic apparatus such as a calculator or 
a radio telephone. The LCD module is itself a conventional device. For 
example, the Applicant has used a SED1200F available from Seiko Epson 
which is an 8-bit device, i.e. it processes data received in blocks of 
8-bits. 
The microprocessor 2 is also a conventional device and the Applicant has 
used a Hitachi 68HC11 device available from Hitachi Limited, Tokyo, Japan. 
This microprocessor is a 8-bit device having 16 address lines. 
Other peripheral devices may also be coupled to the microprocessor 2 
depending on the particular apparatus concerned. 
In accordance with the present invention four of the data lines 
(D.sub.0,D.sub.1,D.sub.2,D.sub.3) of the LCD module are coupled to a 
sub-set of the micro-processor address lines 
(A.sub.2,A.sub.3,A.sub.4,A.sub.5) via a 4-line bus 3. Although the 
microprocessor has 16 address lines, only eight of these (A.sub.0,A.sub.1 
. . . A.sub.7) are shown in FIG. 1, for the sake of clarity. As is 
conventional the address lines are coupled via address buses to the 
various peripheral devices whereby selected devices may be addressed by 
the microprocessor. 
More specifically the data line D.sub.0 of the LCD module 1 is coupled to 
the address line A.sub.2 of the microprocessor 2; the data line D.sub.1 is 
coupled to the address line A.sub.3 ; the data line D.sub.2 is coupled to 
the address line A.sub.4 ; and the data line D.sub.3 is coupled to the 
address line A.sub.5. In this notation A.sub.0 represents the address line 
associated with the least significant bit, A.sub.1 represents the address 
line associated with the second least significant bit, and so on, i.e. the 
subscript indicates the bit position. Likewise D.sub.0 represents the data 
line associated with the least significant bit, and D.sub.2 represents the 
data line associated with the second least significant bit etc. 
It is noted that none of the data lines is connected to the address lines 
A.sub.0, A.sub.1, associated with the two least significant bits. 
As will be discussed in more detail below the write line WR of the LCD 
module 1 is coupled to the MASTER OUT/SLAVE IN (MOSI) line of the 
microprocessor 2. The MOSI line is part of the synchronous serial 
peripheral interface (SPI) function of the microprocessor. The mode line 
A.sub.0 of the LCD module 1 is coupled to the output port of the 
microprocessor 2 and the chip select line CS of the LCD module 1 is 
coupled to the output port of microprocessor 2. and are single 
lines coupled with port A in the microprocessor. In general each of these 
lines may be configured as an input or an output. In the present case they 
are set as outputs. 
When it is desired to write data to the LCD module 1 a "JUMP TO SUBROUTINE" 
instruction in the main programme directs the microprocessor to execute 
one of sixteen special sub-routines depending on the data value to be 
transmitted. The sixteen sub-routines, which are listed in FIG. 2, may be 
stored in EEPROM with the code for the main programme. 
Each subroutine is 4 bytes long and comprises three identical NO-OPERATION 
(NOP) instructions followed by a "RETURN TO SUB-ROUTINE" (RTS) 
instruction. As shown in the timing diagram of FIG. 3, the duration of 
each NOP instruction is two clock cycles. 
Exactly the same sub-routine, i.e. three NOP instructions and one RTS, is 
duplicated sixteen times in total and the sixty-four bytes of code are 
stored in consecutive address locations. As will become apparent from the 
following discussion the set of 16 sub-routines may be stored at any 64 
byte boundary in the main program. 
FIG. 2 shows the 8-bit address location of each sub-routine and of each 
instruction within the individual sub-routines. It can also be seen from 
FIG. 2 what state each address line A.sub.0,A.sub.1 . . . A.sub.7 of the 
microprocessor will be in when a particular instruction is being executed. 
Thus for example, when the instruction at address location 12.sub.10 
=00001100.sub.2 is being executed A.sub.0 =0; A.sub.1 =0; A.sub.2 =1; 
A.sub.3 =1; A.sub.4 =0; A.sub.5 =0; A.sub.6 =0; and A.sub.7 =0. 
Moreover, it can be seen from FIG. 2 that during the execution of any one 
sub-routine the state of the lines A.sub.2,A.sub.3,A.sub.4,A.sub.5 remains 
stable throughout the whole sub-routine. Only the two least significant 
bits on the address lines A.sub.0,A.sub.1 change as the address is 
incremented during execution of the programme. 
So, for example, the four bits 0011 will remain on the address lines for 
six clock cycles during the execution of the three NOP instructions 
starting at address location 12.sub.10 =00001100.sub.2. The corresponding 
data lines D.sub.0,D.sub.1,D.sub.2,D.sub.3 of the LCD module to which the 
address lines (A.sub.2,A.sub.3,A.sub.4,A.sub.5) are coupled will thus be 
held stable for a period long enough to write the data to the LCD module, 
as explained in more detail below. 
The LCD module has four data lines coupled to the microprocessor address 
lines and therefore it is possible to input sixteen combinations of data. 
It will be evident from FIG. 2 that any one of the sixteen combinations of 
data may be applied by executing the appropriate sub-routine having the 
desired bit configuration on the four inner address lines 
A.sub.2,A.sub.3,A.sub.4,A.sub.5. Thus for example, the bits 0101 will be 
applied to the data lines D.sub.0,D.sub.1,D.sub.2,D.sub.3 of the LCD 
module when the sub-routine at address location 20.sub.10 =00010100.sub.2 
is executed. Likewise the bits 1110 will be applied to the data lines 
D.sub.0,D.sub.1,D.sub.2,D.sub.3 when the sub-routine starting at location 
56.sub.10 =0011100 is executed. 
In view of the foregoing discussion it will be apparent that the 16 
sub-routines may be located at any 64 byte boundary without affecting the 
stability of the four bits on the central address lines 
A.sub.2,A.sub.3,A.sub.4,A.sub.5. For example, if the 16 sub-routines start 
at address 64.sub.10 then the bit on address line A.sub.6 would become 1, 
but otherwise the pattern would remain the same as in FIG. 2. Similarly if 
the 16 sub-routines start at any other address location which is a 
multiple of 64 the central four bits A.sub.2,A.sub.3,A.sub.4,A.sub.5 will 
remain stable throughout the execution of each four byte sub-routine. 
Since the LCD module 1 used in this example is an 8-bit device, data is 
transmitted to the module on the four data lines in two successive 4-bit 
segments or so-called "nibbles". 
The overall sequence for writing data to the LCD module will now be 
described, referring additionally to FIG. 3. 
The A.sub.0 line of the LCD module allows one of two modes to be selected, 
namely a display mode and a control mode. In the first mode the input data 
is displayed on the LCD as an alphanumeric character, in the second mode 
the input data determines which position on the LCD the data is displayed. 
The microprocessor output port is therefore set to select the 
appropriate mode. 
In order that the LCD module is addressed the chip select line CS has to be 
set low for the duration of both write steps (i.e. writing both nibbles). 
Hence the microprocessor output port to which the chip select line is 
coupled is set low at the start of the write cycle (see FIG. 3). 
Next, assuming that 8 bits of data are to be sent to the LCD, the upper 
nibble (4-bits) is masked, so that the lower nibble can be sent first to 
the LCD module. At this stage the program executed by the microprocessor 
jumps to the relevant sub-routine. The address of the respective 
sub-routine is calculated by multiplying the decimal version of the data 
value to be sent by 4 and adding as an offset the address location of the 
first sub-routine. So for example, if the first sub-routine is stored in 
location 00 (as shown in FIG. 2) and the data to be sent is 0011=3 the 
address location of the sub-routine is given by (3.times.4)+0=12. Hence 
the sub-routine at location 12 is executed which applies the bits 0011 on 
the address lines A.sub.5,A.sub.4,A.sub.3,A.sub.2 as can be seen from FIG. 
2. 
In order that the data applied to the data lines 
D.sub.0,D.sub.1,D.sub.2,D.sub.3 may be clocked into the LCD module it is 
necessary to apply a write pulse on write line WR during the execution of 
the sub-routine. More particularly the rising edge of the write pulse must 
occur mid-way through the execution of the three NOP instructions. It is 
not possible to apply the write pulse from any of the microprocessor ports 
because this will cause the address on the address lines to change thereby 
corrupting the data to the LCD module. 
The write pulse is therefore generated using the serial peripheral 
interface (SPI) data line from the microprocessor 2, which is known as 
MOSI (MASTER OUT/SLAVE IN) in the Hitachi 68HC11 device used by the 
Applicant. As can be seen from FIG. 3, transmission of one data word is 
started on MOSI just before the call to the particular sub-routine 
containing the three NOP instructions. The value of the word is selected 
so that the levels it generates on the MOSI line corresponding to the 
write pulse on WR causes a rising edge to occur during the execution of 
the NOP instructions, i.e. during the time that the data on the data lines 
is held stable. The data word is stored in the SPI data register in the 
microprocessor and the SPI transfer is then initiated. Each digit of the 
word is transmitted over 2 clock cycles starting with the most significant 
bit first. For example the Applicant has used the data word 00001111 to 
generate a rising edge on the write pulse at the boundary between the 
first and second NOP instructions; as shogun in FIG. 3. In this case the 
rising edge occurs 8 clock cycles after the start of the SPI signal. The 
data on the lines D.sub.0,D.sub.1,D.sub.2,D.sub.3 is thus clocked into the 
LCD module and the sequence is then repeated to clock in the data of the 
lower nibble. 
The whole process of transmitting data to the LCD module sequentially in 
two nibbles may then be repeated to write further data to the LCD module, 
either display or control data depending on the level of A.sub.0 /PA.sub.6 
as mentioned above. 
In view of the foregoing description it will be evident to a person skilled 
in the art that various modification may be made within the scope of the 
present invention. For example the invention is not restricted to data 
devices having four data lines. In this case of a device using eight data 
lines, these may be coupled to the address lines (A.sub.3,A.sub.4 . . . 
A.sub.9) of the microprocessor, excluding the address lines 
(A.sub.0,A.sub.1,A.sub.2) associated with the three least significant 
bits. It will be understood that in this case 256 (=2.sup.8) sub-routines 
are required, corresponding to 1 k byte of memory space, compared with 
only 64 bytes in the 4-line case. It will be apparent therefore that the 
arrangement using only 4 data lines is particularly advantageous since it 
is economic on the amount of memory required. 
Furthermore the invention may be used with peripheral devices other than 
LCD modules, which require data to be written to them, particularly where 
the write timing of the microprocessor is too fast for the device to be 
coupled directly to the data output lines.