Method of forming gate electrode with polycide structure in semiconductor device

A method of forming a gate electrode with a polycide structure in a semiconductor device which can improve the interface roughness between a polysilicon layer and a silicon layer, is disclosed. According to the present invention, a gate insulating layer and a doped polysilicon layer on the gate insulating layer are formed on a semiconductor substrate. A nitrogenous polysilicon layer is then formed on the surface of the polysilicon layer by ion-implanting nitrogen ions (N.sub.2.sup.+) into the surface of the polysilicon layer or by thermal-treating the surface of the polysilicon under the atmosphere of gas containing nitrogen. Next, a metal silicide layer is formed on the nitrogenous polysilicon layer. Thereafter, the metal silicide layer, the nitrogenous polysilicon layer and the polysilicon layer are etched sequentially to form a gate electrode.

BACKGROUND OF THE INVENTION
 1. Field of the Invention
 The present invention relates to a method of manufacturing a semiconductor
 device, particularly to a method of forming a gate electrode of a MOSFET,
 and more particularly to a method of forming a gate electrode with a
 polycide structure in semiconductor device.
 2. Description of the Related Art
 In general, a gate electrode of a MOS transistor has been formed of a doped
 polysilicon layer. However, as high integration of semiconductor device,
 the line widths of a gate electrode and other patterns become fine.
 Recently, the line width is reduced below 0.15 .mu.m. Therefore, there are
 problems that it is difficult to apply the doped polysilicon layer to a
 gate electrode material in a high speed device, since the doped
 polysiliocn layer has a high resistivity. These problems are also growing
 more and more serious as the high integration of the semiconductor. To
 overcome these problems, a gate electrode with a polycide structure in
 which a silicide layer using a refractory metal such as tungsten(W) and
 titanium(Ti) is formed on the polysilicon layer, has been researched.
 FIG. 1A to FIG. 1C show a method of forming a gate electrode with a
 titanium polycide structure in accordance with a prior art.
 As shown in FIG. 1A, a gate oxide layer 11 is grown on a semiconductor
 substrate 10 and a doped polysilicon layer 12 deposited thereon.
 As shown in FIG. 1B, a titanium silicide(TiSi.sub.x) layer of an amorphous
 phase is deposited on the polysilicon layer 12 by physical vapor
 deposition(PVD) using TiSix target. Next, the TiSi.sub.x layer of the
 amorphous phase is thermal-treated by rapid thermal processing(RTP) at a
 selected temperature for several seconds, to be transformed into a
 titanium silicide(TiSi.sub.2) layer 13 of a crystalline phase.
 As shown in FIG. 1C, an oxide(or nitride) layer 14 is formed on the
 TiSi.sub.2 layer 13, for a self-aligned contact(SAC) process which will be
 performed after. The oxide layer 14, the TiSi.sub.2 layer 13, the
 polysilicon layer 12 and the gate oxide layer 11 are patterned by
 photolithography and etching process to form a gate electrode.
 Conventionally several thermal processes such as a first thermal process
 for gate re-oxidation, a second thermal process for forming source/drain,
 a third thermal process for planarizing a intermediate insulating layer
 and a fourth thermal process for forming a capacitor and the like, are
 performed subsequently, after forming the gate electrode as above
 described.
 FIG. 2 shows a cross sectional view of a gate electrode with a titanium
 polycide structure in which a TiSi.sub.2 layer 23 is formed on a
 polysilicon layer 22 according to the prior art. However, when performing
 above thermal processes respectively, the TiSi.sub.2 layer 23 is
 agglomerated to generate stress, so that Ti of TiSi.sub.2 layer 23 is
 diffused into the polysilicon layer 22 and reacted with Si of the
 polysilicon layer 22, thereby deteriorating the interface roughness
 between the polysilicon layer 22 and the TiSi.sub.2 layer 23(TiSi.sub.2
 layer/polysilicon layer), as shown in FIG. 2, after performing above
 thermal processes.
 Furthermore, in case the interface roughness is extremely deteriorated, the
 TiSi.sub.2 layer 23 comes in contact with a gate oxide layer 21, thereby
 deteriorating the property of the gate oxide layer 21. As a result, the
 reliability of a device is deteriorated.
 As not above described, in FIG. 2, reference numbers 20, 24, 25 and 26
 indicate a silicon substrate, a mask oxide layer, a spacer oxide layer and
 source/drain regions, respectively.
 Moreover, although described on the gate electrode with the titanium
 polycide structure, these problems mostly occur in gate electrode with a
 polycide structure.
 SUMMARY OF THE INVENTION
 It is therefore an object of the present invention to provide a method of
 forming a gate electrode with a polycide structure in a semiconductor
 device which can improve the interface roughness between a polysilicon
 layer and a silicon layer by preventing a refractory metal of a silicide
 layer from diffusing into a polysilicon layer when performing thermal
 processing subsequently, for solving the problems in the conventional art.
 To accomplish this above object, in the present invention, a nitrogenous
 polysilicon layer is formed on the surface of the polysilicon layer, prior
 to forming the silicide layer, considering the refractory metal diffusing
 into the polysilicon layer because of the columnar structure of the
 polysilicon layer.
 According to the present invention, a gate insulating layer and a doped
 polysilicon layer on the gate insulating layer are formed on a
 semiconductor substrate. A nitrogenous polysilicon layer is then formed on
 the surface of the polysilicon layer by ion-implanting nitrogen
 ions(N.sub.2.sup.+) into the surface of the polysilicon layer or by
 thermal-treating the surface of the polysilicon under the atmosphere of
 gas containing nitrogen. Next, a metal silicide layer is formed on the
 nitrogenous polysilicon layer. Thereafter, the metal silicide layer, the
 nitrogenous polysilicon layer and the polysilicon layer are etched
 sequentially to form a gate electrode.
 Additional object, advantages and novel features of the invention will be
 set forth in part in the description which follows, and in part will
 become apparent to those skilled in the art upon examination of the
 following or may be learned by practice of the invention. The objects and
 advantages of the invention may be realized and attained by means of the
 instrumentalities and combinations particularly pointed out in the
 appended claims.

DETAILED DESCRIPTION OF THE INVENTION
 Hereinafter, preferred embodiment of the present invention will be
 explained with reference to accompanying drawings.
 FIG. 3A to FIG. 3E are cross sectional views showing a method of forming a
 gate electrode with a titanium polycide structure according to an
 embodiment of the present invention.
 Referring to FIG. 3A, a gate insulating layer 31 is grown on a silicon
 substrate 30 and a doped polysilicon layer 32 is deposited thereon.
 Referring to FIG. 3B, a nitrogenous polysilicon layer 32a is formed on the
 surface of the polysilicon layer 32 by ion-implanting nitrogen
 ions(N.sub.2.sup.+) into the surface of the polysilicon layer 32 or by
 thermal-treating the surface of the polysilicon under the atmosphere of
 gas containing nitrogen such as N.sub.2, NH.sub.3 and N.sub.2 O.
 Preferably, the ion-implantation is performed to the energy of 10 to 30
 keV and the dose of 1.times.10.sup.14 to 1.times.10.sup.16 ions/cm.sup.3.
 Furthermore, the thermal-treating is performed at the temperature of 700
 to 900.degree. C. for 10 to 60 minutes.
 Referring to FIG. 3C, a titanium silicide(TiSi.sub.x) layer of an amorphous
 phase is deposited on the nitrogenous polysilicon layer 32a by PVD using
 TiSi.sub.x target. Next, the TiSi.sub.x layer of the amorphous phase is
 thermal-treated by RTP at a selected temperature for several seconds, to
 be transformed into a titanium silicide(TiSi.sub.2) layer 33 of a
 crystalline phase.
 Referring to FIG. 3D, an oxide(or nitride) layer 34 is formed on the
 TiSi.sub.2 layer 33, for a conventional self-aligned contact(SAC) process
 which will be performed after. Thereafter, the oxide layer 34, the
 TiSi.sub.2 layer 33, the nitrogenous polysilicon layer 32a, the
 polysilicon layer 32 and the gate oxide layer 31 are etched sequentially
 to form a gate electrode, as shown in FIG. 3E.
 According to this embodiment, the nitrogenous polysilicon layer is formed
 on the surface of the polysilicon layer using ion-implantation or
 thermal-treating prior to forming the TiSi.sub.2 layer, so that TiSi.sub.2
 layer comes in contact with the nitrogenous polysilicon layer. Therefore,
 Ti of the TiSi.sub.2 layer is prevented from diffusing into the
 polysilicon layer by the nitrogenous polysilicon layer, although stress is
 generated due to agglomeration of the TiSi.sub.2 when performing thermal
 processing subsequently. As a result, the interface roughness between the
 polysilicon layer and the TiSi.sub.2 layer, is improved, thereby improving
 the reliability of a device.
 Furthermore, a method according to the present invention may be applied to
 a gate electrode with a polycide using a metal silicide such as a tungsten
 silicide(WSi.sub.2), a cobalt silicide(CoSi.sub.2), a vanadium silicide
 (VSi.sub.2), a chromium silicide(CrSi.sub.2), a zirconium
 silicide(ZrSi.sub.2), a niobium silicide(NbSi.sub.2), a molybdenum
 silicide(MoSi.sub.2), a hafnium silicide(HfSi.sub.2) as well as the
 TiSi.sub.2.
 Although the preferred embodiment of this invention has been disclosed for
 illustrative purpose, those skilled in the art will appreciate that
 various modifications, additions and substitutions are possible, without
 departing from the scope and spirit of the invention as described in the
 accompanying claims.