Parallel rounding for conversion from binary floating point to binary coded decimal

Embodiments of the invention are directed to a computer-implemented method of for parallel conversion to binary coded decimal format. The method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value. The FPU receives the rounding information and operates on the BCD value accordingly.

BACKGROUND

The present invention generally relates to conversion from binary floating point (BFP) to binary coded decimal format (BCD), and more specifically, to parallel rounding for conversion from BFP format to BCD format.

Modern high-performance computers typically operate internally in the binary number system. The binary system permits systems to cheaply, reliably, and accurately execute a modern application. However, a significant class of computer systems operates using the BCD format in which binary digits are divided into groups of four bits, with each of the groups, representing one of the decimal digits, zero through nine. These systems are often preferred in situations, in which large amounts of input data are processed.

SUMMARY

Embodiments of the present invention are directed to a computer-implemented method for parallel conversion to binary coded decimal format. A non-limiting example of the computer-implemented method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value.

Other embodiments of the present invention implement the features of the above-described methods in computer systems and in computer program products.

DETAILED DESCRIPTION

Embodiments of the present invention are directed to a floating point unit (FPU) that converts a binary floating point (BFP) value to a binary coded decimal (BCD) value. One of the embodiments described herein includes an FPU that converts a BFP value to a BCD value in parallel with a rounding operation on the BFP value. By performing the conversion in parallel to rounding, the FPU reduces the cycle time needed for outputting a rounded BCD value when compared to a conventional FPU. There are several advantages to performing operations using BCD values. BCD values are often used in banking and insurance related industries to help avoid calculation differences or errors that are common in calculations using BFP values. In addition, many non-integral values have an infinite representation in BFP, however some computer applications only operate on finite numbers and therefore require BCD values. These applications are further enhanced by speeding up the processing time to output a rounded BCD value.

In a modern computer application that processes large amounts of data, it can be advantageous to operate using BCD values over BFP values. In a typical microprocessor system, the FPU, also known as a math co-processor, is integrated with a central processing unit (CPU) and performs various mathematical operations such as addition, subtraction, multiplication, and division. In particular, the typical FPU is designed to perform the operation A*B+C, in which A, B, and C are floating point values. Some FPU hardware also provides built-in features to support other mathematical operations such as computation of transcendental functions.

A BFP value is expressed as a significand value multiplied by a base raised to an exponent (significand*(base∧exponent)). BFP values are aligned on the left, such that they are normalized so that only one non-zero number appears to the left of a radix point. (The radix point is not explicitly encoded in this initial BFP representation, but is assumed to lie between the leftmost non-zero bit and the bit to the immediate right of that non-zero bit.). During operation, a conventional FPU passes the significand value through different stages of a processor pipeline, in which each stage requires one or more clock cycles for completion.

The processor pipeline of a conventional FPU performs a rounding operation and then converts the BFP value to a BCD value. In other words, the conversion operation is idle until after the completion of the rounding operation. Depending upon the number of clock cycles between completion of the rounding operation and the beginning of the conversion operation, a conventional FPU is unnecessarily idle while waiting for the rounding operation to finish.

One or more embodiments of the present invention address the above-described shortcomings of the prior art by providing methods and systems that perform the conversion from a BFP value to a BCD value in parallel with rounding the BFP value. Depending upon the size of the BFP value, the rounding process will complete prior to the complete conversion of the BFP value to a BCD value. After conversion, the BCD value is rounded and output for further use. By parallelizing the conversions and rounding operations, the conversion operation is decoupled from the wait time required to complete the rounding operation and the FPU is more efficient.

FIG. 1depicts an FPU100that parallelizes the conversion and rounding operations according to embodiments of the present invention. The process is essentially divided into two parts, a conversion part and a rounding part. The FPU100receives instructions from an instruction fetch unit (not shown) and an instruction scheduling unit (not shown) to convert a BFP value to a BCD value. A BFP value is received at stage f0102from a register file (not shown), which has been loaded from a load store unit (not shown). At stage f1104, the BFP is decoded into the significand, base, and exponent. The significand includes an integer part and a fractional part that are separated by a radix point (implicitly defined as noted above as lying between the leftmost non-zero bit and the bit to the immediate right of that non-zero bit in the initial BFP representation). The FPU100is configured to receive BFP values individually or grouped together. Grouped BFP values include instructions relaying the number of bits in each individual BFP value. For example, the FPU100can process a 128-bit BFP value or two 64-bit BFP values. In the case of the two 64-bit values, the FPU100converts the two 64-bit BFP values sequentially. The FPU100is further configured to convert a BFP value having any number of bits. At stage f1104, the FPU100also determines whether the position of bits is shifted based on the exponent.

At stage f2106and stage f3108, the FPU100performs a bitwise operation to shift the bits to either the left or the right based on the exponent value. In some embodiments of the present invention, the shifting operation is performed in one stage and in other embodiments the shifting operation occurs in multiple stages.

The BFP value is transmitted to the conversion register110, which converts a subset of the total bits of the BFP during each cycle. For example, a conversion register that converted 8 bits per cycle requires 8 cycles to fully convert a 64-bit BFP value. In some embodiments of the present invention, only the integer part of the BFP value is transmitted to the conversion register. In some embodiments of the present invention, each subset is sequentially transmitted from the conversion register to the adder112and in other embodiments, the fully converted BCD value is transmitted to the adder112. For example, 8-bit converted subsets are transmitted until a full 64-bit BCD value is reassembled at the adder112. In some embodiments of the present invention, the BFP value is converted into an intermediate value prior to conversion to a BCD value. At stage f5114, the FPU100determines whether the value is a rounded BCD value that can be sent to stage f7 or if the BFP value needs to be sent to stage f6116for rounding.

In parallel to the conversion loop, a duplicated BFP value moves down the pipeline to stage f6 or the rounding operation116. Rounding information is then looped back to the adder112. In the instance that the conversion loop is transmitting duplicated subsets of the BCD value and the least significant bit has been transmitted, the adder112can add a rounding value to the least significant bit prior to conversion of the most significant bit of the BFP value. In the instance that the rounding information suggests that the BFP value does not need to be rounded up, the adder adds a 0. In the instance that the entire BCD is transmitted to the adder, the adder either adds or does not add a value to the full BCD value based on the rounding information. At stage f7118, the BCD value is output120. It should be appreciated by one of ordinary skill in the art that althoughFIG. 1depicts a seven-stage processor pipeline, an FPU100according to embodiments of the present invention could operate with a fewer or greater number of stages depending upon the functionality of each stage.

As an example, consider a BFP value 0×1.234A6*2∧12. For this example, the BFP value is written in hexadecimal, but should be understood to represent a value binary floating decimal format. In this example, “0×” is an indication that the value is written in hexadecimal, 1.234A6 is the significand in hexadecimal format, 2 is the base, and 12 is the exponent. For the significand, 1 is the integer part and 234A6 is the fractional part. The FPU100receives the BFP value and shifts the bits three places (as viewed in the hexadecimal format) such that the significand becomes 1234.A6. In this example, the bits are shifted three places because each digit would have been represented by four bits in binary format and four times three equals twelve. The significand in the BFP format is converted to an intermediate value and processed through the conversion loop. The conversion register110produces an unrounded BCD value, which is transmitted to the adder112. In parallel to the conversion operation, the BFP value is processed through the rounding operation. In the example, A6 is rounded up to a one. The rounding information is transmitted to the adder112and the adder112adds a 1 to the BCD value. The final BCD value is 0d4661, in which “0d” is an indication that the value is in BCD format and 4661 is the value.

FIG. 2depicts an FPU200configured to account for sign values in the rounding operation. The conversion process operates on positive numbers and therefore negative BFP values are changed to positive BFP values prior to conversion to BCD values. If the BFP value is a positive number, the FPU200operates as described above. If the rounding information indicates the BFP value does not need to be rounded up, the multiplexer200transmits a 0 value to the adder112. If the BFP value needs to be rounded up, the multiplexer transmits a 1 to the adder112.

In some embodiments, a negative BFP value is introduced for conversion to a BCD value. To account for a negative BFP value, the FPU200uses a two's complement scheme. In the instance of a negative BFP value, the negative BFP value is converted to a positive BFP value at stage f0102and a positive BFP value is converted to a positive BCD value. In the instance that the rounding information indicates that value does not need to be rounded up, the multiplexer200transmits a 1, which is added to the BCD value by the adder112. If the rounding information indicates that the BCD value needs to be rounded up, the multiplexer200transmits a 2 to be added to the BCD value.

FIG. 3depicts tables of values converted from a BCD value300to an intermediate value302. A 4-bit BCD value ranges from 0-9. Although 4 bits can be used to describe values 0-16, for BCD values 10-16 are illegal. The leftmost and first BCD bit304represents an eight. The second BCD bit306represents a four. The third BCD bit308represents a two. The fourth BCD bit310represents a one. To count higher than 9, the 4-bit BCD numbering system incorporates an additional 4 bits. In the intermediate format302, the numbers 0-9 are represented by six bits. The first five intermediate bits312-320include a single one bit and the rest are zero bits. The sixth intermediate bit322can be either a 1 or a 0 and represents a one or a zero. The first intermediate bit312represents an eight. The second intermediate bit314represents a six. The third intermediate bit316represents a four. The fourth intermediate bit318represents a two. The fifth intermediate bit320represents a zero. For example, a seven in BCD is represented as 0111. In the intermediate format, a seven is represented as 010001, in which there is a single 1 bit in the second intermediate bit314representing a six and a 1 bit in the sixth bit representing a one. The six is added to one to reach a seven. A transformation from a 5 and a 6 in BCD to a respective 5 and 6 in intermediate format is also shown inFIG. 3.

Referring toFIG. 4, there is shown an embodiment of a processing system400for implementing the teachings herein. In this embodiment, the system400has one or more central processing units (processors)21a,21b,21c, etc. (collectively or generically referred to as processor(s)21). In one or more embodiments, each processor21may include a reduced instruction set computer (RISC) microprocessor. Processors21are coupled to system memory34and various other components via a system bus33. Read only memory (ROM)22is coupled to the system bus33and may include a basic input/output system (BIOS), which controls certain basic functions of system400.

FIG. 4further depicts an input/output (I/O) adapter27and a network adapter26coupled to the system bus33. I/O adapter27may be a small computer system interface (SCSI) adapter that communicates with a hard disk23and/or external storage drive25or any other similar component. I/O adapter27, hard disk23, and external storage device25are collectively referred to herein as mass storage24. Operating system40for execution on the processing system400may be stored in mass storage24. A network adapter26interconnects bus33with an outside network36enabling data processing system400to communicate with other such systems. A screen (e.g., a display monitor)35is connected to system bus33by display adaptor32, which may include a graphics adapter to improve the performance of graphics intensive applications and a video controller. In one embodiment, adapters27,26, and32may be connected to one or more I/O busses that are connected to system bus33via an intermediate bus bridge (not shown). Suitable I/O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols, such as the Peripheral Component Interconnect (PCI). Additional input/output devices are shown as connected to system bus33via user interface adapter28and display adapter32. A keyboard29, mouse30, and speaker31all interconnected to bus33via user interface adapter28, which may include, for example, a Super I/O chip integrating multiple device adapters into a single integrated circuit.

Thus, as configured inFIG. 4, the system400includes processing capability in the form of processors21, storage capability including system memory34and mass storage24, input means such as keyboard29and mouse30, and output capability including speaker31and display35. In one embodiment, a portion of system memory34and mass storage24collectively store an operating system coordinate the functions of the various components shown inFIG. 4.

FIG. 5depicts a flow diagram of a method for a parallel conversion of a BFP value to a BCD value according to one or more embodiments of the invention. The method500includes receiving a BFP value at the FPU at block502. If the BFP value is negative, the FPU changes the negative BFP value to a positive BFP value. At block504the FPU performs a bit shifting operation based on an exponent of the BFP value. At this point, the FPU determines whether a decimal value remains or is the BFP value an integer. If the BFP value is an integer, the BFP value is converted to a BCD value and the BCD value is output at block506. At block508, the FPU adjusts the sign of the BCD value to negative to comport with an original negative BFP value. In some embodiments of the present invention, the FPU discards the fractional part and treats the BFP value as an integer. For example, an application may recognize a source of a BFP value and detect a number of significant digits in the BFP value that is greater than a threshold amount that the application requires. In other embodiments, the FPU adds a predetermined fractional part. For example, an application may recognize a source of a BFP value and detect a number of significant digits in the BFP value that is lower than a threshold amount that an application requires.

If the BFP value has a decimal part, the integer part of the BFP value is converted to a BCD value and the BCD value is sent to an adder at block510. In parallel to the conversion operation, the FPU rounds the BFP value and transmits rounding information at block512. The rounding information includes whether the BCD value remains the same or is rounded up. At block514, the FPU adjusts the value of the BCD value based on the rounding information. At block516, the FPU adjusts the sign of the BCD value to comport with the sign of the original BFP value.