Method and system for distributing work batches to processing units based on a number of enabled streaming multiprocessors

A work distribution unit distributes work batches to general processing clusters (GPCs) based on the number of streaming multiprocessors included in each GPC. Advantageously, each GPC receives an amount of work that is proportional to the amount of processing power afforded by the GPC. Embodiments include a method for distributing batches of processing tasks to two or more general processing clusters (GPCs), including the steps of updating a counter value for each of the two or more GPCs based on the number of enabled parallel processing units within each of the two or more GPCs, and distributing a batch of processing tasks to a first GPC of the two or more GPCs based on a counter value associated with the first GPC and based on a load signal received from the first GPC.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention generally relates to computer hardware and more specifically to a method and system for distributing work batches to processing units.

Description of the Related Art

A modern computer system may include one or more processing units that operate in parallel to perform a variety of processing tasks.FIG. 1illustrates one such computer system. As shown, computer system10includes processing units12-1,12-2, and12-n. A work distribution unit14is coupled to each of the processing units12and distributes work batches16-1,16-2, and16-nto processing units12-1,12-2, and12-n, respectively. As referred to herein, a “work batch” includes a set of processing tasks to be performed by a particular processing unit12. Work distribution unit14distributes work batch16-1to processing unit12-1, work batch16-2to processing unit12-2, and work batch16-nto processing unit12-n. Processing units12-1,12-2, and12-nthen perform the processing tasks specified by work batches16-1,16-2, and16-nusing processors18-1,18-2, and18-n, respectively.

Work distribution unit14may distribute work batches16to processing units12-1to12-nbased on a variety of well-known distribution policies. One example of a distribution policy is referred to in the art as a “round-robin” policy. According to the round-robin policy, the work distribution unit transmits a work batch to each processing unit12in the sequence of processing units12-1to12-n. When work distribution unit14reaches the end of the sequence (processing unit12-n), the work distribution unit returns to the beginning of the sequence (processing unit12-1) and continues to distribute additional work batches16to the sequence of processing units12-1to12-n, starting with processing unit12-1. When work distribution unit14reaches a processing unit12that has not yet finished processing a work batch16that was previously distributed to that processing unit12, work distribution unit14stalls until processing unit12has finished processing the previously distributed work batch16.

One problem with this approach is that processing units12may not all have equivalent processing capabilities. For example, processing unit12-1may include just one processor18-1, while processing units12-2and12-nmay each include more than one processing units. Thus, processing unit12-1may require a disproportionate amount of time to finish processing work batch16-1compared to the amount of time required by processing units12-2and12-nto finish processing work batches16-2and16-n, respectively. Consequently, work distribution unit14may repeatedly become stalled when attempting to distribute additional work batches to processing unit12-1, thereby reducing the processing throughput of the computer system10.

In addition, certain work batches16may require significantly more processing time to complete than others due to variance in the complexity of the processing tasks required to complete each batch16. Accordingly, the work distribution unit14may become stalled while waiting for a processing unit12to finish processing a batch16of increased complexity, thus further reducing the throughput of the computer system10. When a processing unit12that has diminished processing capabilities receives a batch16of increased complexity relative to other batches16, the processing throughput of the computer system10may be reduced dramatically.

A common solution to this problem is to cause each processing unit12to assert a “load” signal to work distribution unit14when the processing of a work batch16is complete. For example, processing unit12-1could assert a load signal20-1when the processing of work batch16-1is complete. Likewise, processing unit12-2could assert a load signal20-2when the processing of work batch16-2is complete, and processing unit12-ncould assert a load signal20-nwhen the processing of work batch16-nis complete. When a given processing unit12has not asserted the load signal20, work distribution unit14skips that processing unit12when distributing work batches16to the sequence of processing units12-1to12-n. Through this technique, work distribution unit14cannot be stalled by a processing unit12that has not yet finished processing a batch16because such a processing unit12is simply skipped.

However, work distribution unit14may have to wait for the transmission of load signal20to complete. Once transmission of load signal20is complete, work distribution unit404then requires additional time to transmit a batch16to the processing unit12that transmitted load signal20. These latencies correspond to idle cycles on the processors18, which inhibit the performance of the computer system10.

One approach to solving this problem is to include a work FIFO within each processing unit12. As shown, processing units12-1,12-2, and12-ninclude work FIFOs22-1,22-2, and22-n. Each work FIFO22stores a plurality of work batches16received from work distribution unit14. When space becomes available within a given FIFO22, work distribution unit14distributes an additional work batch16to that FIFO22. Although this approach may reduce the idle cycles on the processors18, it allows work to complete massively out of order and it may leave one processor with a large queue of long work when the computer system10is waiting for idle.

As the foregoing illustrates, what is needed in the art is a more effective technique for distributing work batches to processing units that have different processing capabilities.

SUMMARY OF THE INVENTION

Embodiments of the invention include a method for distributing batches of processing tasks to two or more general processing clusters (GPCs), including the steps of updating a counter value for each of the two or more GPCs based on the number of enabled parallel processing units within each of the two or more GPCs, and distributing a batch of processing tasks to a first GPC of the two or more GPCs based on a counter value associated with the first GPC and based on a load signal received from the first GPC.

Advantageously, each GPC receives an amount of work from the work distribution unit (WDU) that is proportional to the processing power afforded by the GPC. In addition, the WDU may abstain from distributing work batches to some or all of the GPCs in order to balance the workload across all of the GPCs.

DETAILED DESCRIPTION

System Overview

FIG. 2Ais a block diagram illustrating a computer system100configured to implement one or more aspects of the invention. Computer system100includes a central processing unit (CPU)102and a system memory104communicating via an interconnection path that may include a memory bridge105. Memory bridge105, which may be, e.g., a Northbridge chip, is connected via a bus or other communication path106(e.g., a HyperTransport link) to an I/O (input/output) bridge107. I/O bridge107, which may be, e.g., a Southbridge chip, receives user input from one or more user input devices108(e.g., keyboard, mouse) and forwards the input to CPU102via path106and memory bridge105. A parallel processing subsystem112is coupled to memory bridge105via a bus or other communication path113(e.g., a PCI Express, Accelerated Graphics Port, or HyperTransport link); in one embodiment parallel processing subsystem112is a graphics subsystem that delivers pixels to a display device110(e.g., a conventional CRT or LCD based monitor). A system disk114is also connected to I/O bridge107. A switch116provides connections between I/O bridge107and other components such as a network adapter118and various add-in cards120and121. Other components (not explicitly shown), including USB or other port connections, CD drives, DVD drives, film recording devices, and the like, may also be connected to I/O bridge107. Communication paths interconnecting the various components inFIG. 1may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s), and connections between different devices may use different protocols as is known in the art.

In one embodiment, the parallel processing subsystem112incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, the parallel processing subsystem112incorporates circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. In yet another embodiment, the parallel processing subsystem112may be integrated with one or more other system elements, such as the memory bridge105, CPU102, and I/O bridge107to form a system on chip (SoC).

FIG. 2Billustrates a parallel processing subsystem112, according to one embodiment of the invention. As shown, parallel processing subsystem112includes one or more parallel processing units (PPUs)202, each of which is coupled to a local parallel processing (PP) memory204. In general, a parallel processing subsystem includes a number U of PPUs, where U≧1. (Herein, multiple instances of like objects are denoted with reference numbers identifying the object and parenthetical numbers identifying the instance where needed.) PPUs202and parallel processing memories204may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or memory devices, or in any other technically feasible fashion.

Referring again toFIG. 2A, in some embodiments, some or all of PPUs202in parallel processing subsystem112are graphics processors with rendering pipelines that can be configured to perform various tasks related to generating pixel data from graphics data supplied by CPU102and/or system memory104via memory bridge105and bus113, interacting with local parallel processing memory204(which can be used as graphics memory including, e.g., a conventional frame buffer) to store and update pixel data, delivering pixel data to display device110, and the like. In some embodiments, parallel processing subsystem112may include one or more PPUs202that operate as graphics processors and one or more other PPUs202that are used for general-purpose computations. The PPUs may be identical or different, and each PPU may have its own dedicated parallel processing memory device(s) or no dedicated parallel processing memory device(s). One or more PPUs202may output data to display device110or each PPU202may output data to one or more display devices110.

In operation, CPU102is the master processor of computer system100, controlling and coordinating operations of other system components. In particular, CPU102issues commands that control the operation of PPUs202. In some embodiments, CPU102writes a stream of commands for each PPU202to a pushbuffer (not explicitly shown in eitherFIG. 1orFIG. 2) that may be located in system memory104, parallel processing memory204, or another storage location accessible to both CPU102and PPU202. PPU202reads the command stream from the pushbuffer and then executes commands asynchronously relative to the operation of CPU102.

Referring back now toFIG. 2, each PPU202includes an I/O (input/output) unit205that communicates with the rest of computer system100via communication path113, which connects to memory bridge105(or, in one alternative embodiment, directly to CPU102). The connection of PPU202to the rest of computer system100may also be varied. In some embodiments, parallel processing subsystem112is implemented as an add-in card that can be inserted into an expansion slot of computer system100. In other embodiments, a PPU202can be integrated on a single chip with a bus bridge, such as memory bridge105or I/O bridge107. In still other embodiments, some or all elements of PPU202may be integrated on a single chip with CPU102.

In one embodiment, communication path113is a PCI-EXPRESS link, in which dedicated lanes are allocated to each PPU202, as is known in the art. Other communication paths may also be used. An I/O unit205generates packets (or other signals) for transmission on communication path113and also receives all incoming packets (or other signals) from communication path113, directing the incoming packets to appropriate components of PPU202. For example, commands related to processing tasks may be directed to a host interface206, while commands related to memory operations (e.g., reading from or writing to parallel processing memory204) may be directed to a memory crossbar unit210. Host interface206reads each pushbuffer and outputs the work specified by the pushbuffer to a front end212.

Each PPU202advantageously implements a highly parallel processing architecture. As shown in detail, PPU202(0) includes a processing cluster array230that includes a number C of general processing clusters (GPCs)208, where C≧1. Each GPC208is capable of executing a large number (e.g., hundreds or thousands) of threads concurrently, where each thread is an instance of a program. In various applications, different GPCs208may be allocated for processing different types of programs or for performing different types of computations. For example, in a graphics application, a first set of GPCs208may be allocated to perform tessellation operations and to produce primitive topologies for patches, and a second set of GPCs208may be allocated to perform tessellation shading to evaluate patch parameters for the primitive topologies and to determine vertex positions and other per-vertex attributes. The allocation of GPCs208may vary dependent on the workload arising for each type of program or computation.

GPCs208receive processing tasks to be executed via a work distribution unit200, which receives commands defining processing tasks from front end unit212. Processing tasks include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). Work distribution unit200may be configured to fetch the indices corresponding to the tasks, or work distribution unit200may receive the indices from front end212. Front end212ensures that GPCs208are configured to a valid state before the processing specified by the pushbuffers is initiated.

When PPU202is used for graphics processing, for example, the processing workload for each patch is divided into approximately equal sized tasks to enable distribution of the tessellation processing to multiple GPCs208. A work distribution unit200may be configured to produce tasks at a frequency capable of providing tasks to multiple GPCs208for processing. By contrast, in conventional systems, processing is typically performed by a single processing engine, while the other processing engines remain idle, waiting for the single processing engine to complete its tasks before beginning their processing tasks. In some embodiments of the present invention, portions of GPCs208are configured to perform different types of processing. For example a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading in screen space to produce a rendered image. Intermediate data produced by GPCs208may be stored in buffers to allow the intermediate data to be transmitted between GPCs208for further processing.

Memory interface214includes a number D of partition units215that are each directly coupled to a portion of parallel processing memory204, where D≧1. As shown, the number of partition units215generally equals the number of DRAM220. In other embodiments, the number of partition units215may not equal the number of memory devices. Persons skilled in the art will appreciate that DRAM220may be replaced with other suitable storage devices and can be of generally conventional design. A detailed description is therefore omitted. Render targets, such as frame buffers or texture maps may be stored across DRAMs220, allowing partition units215to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processing memory204.

Any one of GPCs208may process data to be written to any of the DRAMs220within parallel processing memory204. Crossbar unit210is configured to route the output of each GPC208to the input of any partition unit215or to another GPC208for further processing. GPCs208communicate with memory interface214through crossbar unit210to read from or write to various external memory devices. In one embodiment, crossbar unit210has a connection to memory interface214to communicate with I/O unit205, as well as a connection to local parallel processing memory204, thereby enabling the processing cores within the different GPCs208to communicate with system memory104or other memory that is not local to PPU202. In the embodiment shown inFIG. 2B, crossbar unit210is directly connected with I/O unit205. Crossbar unit210may use virtual channels to separate traffic streams between the GPCs208and partition units215.

Again, GPCs208can be programmed to execute processing tasks relating to a wide variety of applications, including but not limited to, linear and nonlinear data transforms, filtering of video and/or audio data, modeling operations (e.g., applying laws of physics to determine position, velocity and other attributes of objects), image rendering operations (e.g., tessellation shader, vertex shader, geometry shader, and/or pixel shader programs), and so on. PPUs202may transfer data from system memory104and/or local parallel processing memories204into internal (on-chip) memory, process the data, and write result data back to system memory104and/or local parallel processing memories204, where such data can be accessed by other system components, including CPU102or another parallel processing subsystem112.

A PPU202may be provided with any amount of local parallel processing memory204, including no local memory, and may use local memory and system memory in any combination. For instance, a PPU202can be a graphics processor in a unified memory architecture (UMA) embodiment. In such embodiments, little or no dedicated graphics (parallel processing) memory would be provided, and PPU202would use system memory exclusively or almost exclusively. In UMA embodiments, a PPU202may be integrated into a bridge chip or processor chip or provided as a discrete chip with a high-speed link (e.g., PCI-EXPRESS) connecting the PPU202to system memory via a bridge chip or other communication means.

As noted above, any number of PPUs202can be included in a parallel processing subsystem112. For instance, multiple PPUs202can be provided on a single add-in card, or multiple add-in cards can be connected to communication path113, or one or more of PPUs202can be integrated into a bridge chip. PPUs202in a multi-PPU system may be identical to or different from one another. For instance, different PPUs202might have different numbers of processing cores, different amounts of local parallel processing memory, and so on. Where multiple PPUs202are present, those PPUs may be operated in parallel to process data at a higher throughput than is possible with a single PPU202. Systems incorporating one or more PPUs202may be implemented in a variety of configurations and form factors, including desktop, laptop, or handheld personal computers, servers, workstations, game consoles, embedded systems, and the like.

Processing Cluster Array Overview

Operation of GPC208is advantageously controlled via a pipeline manager305that distributes processing tasks to streaming multiprocessors (SPMs)310. Pipeline manager305may also be configured to control a work distribution crossbar330by specifying destinations for processed data output by SPMs310.

In one embodiment, each GPC208includes a number M of SPMs310, where M≧1, each SPM310configured to process one or more thread groups. Also, each SPM310advantageously includes an identical set of functional execution units (e.g., arithmetic logic units, and load-store units, shown as Exec units302and LSUs303inFIG. 3C) that may be pipelined, allowing a new instruction to be issued before a previous instruction has finished, as is known in the art. Any combination of functional execution units may be provided. In one embodiment, the functional units support a variety of operations including integer and floating point arithmetic (e.g., addition and multiplication), comparison operations, Boolean operations (AND, OR, XOR), bit-shifting, and computation of various algebraic functions (e.g., planar interpolation, trigonometric, exponential, and logarithmic functions, etc.); and the same functional-unit hardware can be leveraged to perform different operations.

The series of instructions transmitted to a particular GPC208constitutes a thread, as previously defined herein, and the collection of a certain number of concurrently executing threads across the parallel processing engines (not shown) within an SPM310is referred to herein as a “warp” or “thread group.” As used herein, a “thread group” refers to a group of threads concurrently executing the same program on different input data, with one thread of the group being assigned to a different processing engine within an SPM310. A thread group may include fewer threads than the number of processing engines within the SPM310, in which case some processing engines will be idle during cycles when that thread group is being processed. A thread group may also include more threads than the number of processing engines within the SPM310, in which case processing will take place over consecutive clock cycles. Since each SPM310can support up to G thread groups concurrently, it follows that up to G*M thread groups can be executing in GPC208at any given time.

Additionally, a plurality of related thread groups may be active (in different phases of execution) at the same time within an SPM310. This collection of thread groups is referred to herein as a “cooperative thread array” (“CTA”) or “thread array.” The size of a particular CTA is equal to m*k, where k is the number of concurrently executing threads in a thread group and is typically an integer multiple of the number of parallel processing engines within the SPM310, and m is the number of thread groups simultaneously active within the SPM310. The size of a CTA is generally determined by the programmer and the amount of hardware resources, such as memory or registers, available to the CTA.

Each SPM310contains an L1 cache (not shown) or uses space in a corresponding L1 cache outside of the SPM310that is used to perform load and store operations. Each SPM310also has access to L2 caches within the partition units215that are shared among all GPCs208and may be used to transfer data between threads. Finally, SPMs310also have access to off-chip “global” memory, which can include, e.g., parallel processing memory204and/or system memory104. It is to be understood that any memory external to PPU202may be used as global memory. Additionally, an L1.5 cache335may be included within the GPC208, configured to receive and hold data fetched from memory via memory interface214requested by SPM310, including instructions, uniform data, and constant data, and provide the requested data to SPM310. Embodiments having multiple SPMs310in GPC208beneficially share common instructions and data cached in L1.5 cache335.

Each GPC208may include a memory management unit (MMU)328that is configured to map virtual addresses into physical addresses. In other embodiments, MMU(s)328may reside within the memory interface214. The MMU328includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. The MMU328may include address translation lookaside buffers (TLB) or caches which may reside within multiprocessor SPM310or the L1 cache or GPC208. The physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. The cache line index may be used to determine whether of not a request for a cache line is a hit or miss.

In graphics and computing applications, a GPC208may be configured such that each SPM310is coupled to a texture unit315for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering the texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from the L1 cache within SPM310and is fetched from an L2 cache, parallel processing memory204, or system memory104, as needed. Each SPM310outputs processed tasks to work distribution crossbar330in order to provide the processed task to another GPC208for further processing or to store the processed task in an L2 cache, parallel processing memory204, or system memory104via crossbar unit210. A preROP (pre-raster operations)325is configured to receive data from SPM310, direct data to ROP units within partition units215, and perform optimizations for color blending, organize pixel color data, and perform address translations.

It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units, e.g., SPMs310or texture units315, preROPs325may be included within a GPC208. Further, while only one GPC208is shown, a PPU202may include any number of GPCs208that are advantageously functionally similar to one another so that execution behavior does not depend on which GPC208receives a particular processing task. Further, each GPC208advantageously operates independently of other GPCs208using separate and distinct processing units, L1 caches, and so on.

FIG. 3Bis a block diagram of a partition unit215within one of the PPUs202ofFIG. 2B, according to one embodiment of the invention. As shown, partition unit215includes a L2 cache350, a frame buffer (FB) DRAM interface355, and a raster operations unit (ROP)360. L2 cache350is a read/write cache that is configured to perform load and store operations received from crossbar unit210and ROP360. Read misses and urgent writeback requests are output by L2 cache350to FB DRAM interface355for processing. Dirty updates are also sent to FB355for opportunistic processing. FB355interfaces directly with DRAM220, outputting read and write requests and receiving data read from DRAM220.

In graphics applications, ROP360is a processing unit that performs raster operations, such as stencil, z test, blending, and the like, and outputs pixel data as processed graphics data for storage in graphics memory. In some embodiments of the present invention, ROP360is included within each GPC208instead of partition unit215, and pixel read and write requests are transmitted over crossbar unit210instead of pixel fragment data.

The processed graphics data may be displayed on display device110or routed for further processing by CPU102or by one of the processing entities within parallel processing subsystem112. Each partition unit215includes a ROP360in order to distribute processing of the raster operations. In some embodiments, ROP360may be configured to compress z or color data that is written to memory and decompress z or color data that is read from memory.

Persons skilled in the art will understand that the architecture described inFIGS. 2A, 2B, 3A, and 3Bin no way limits the scope of the present invention and that the techniques taught herein may be implemented on any properly configured processing unit, including, without limitation, one or more CPUs, one or more multi-core CPUs, one or more PPUs202, one or more GPCs208, one or more graphics or special purpose processing units, or the like, without departing the scope of the present invention.

In embodiments of the invention, it is desirable to use PPU122or other processor(s) of a computing system to execute general-purpose computations using thread arrays. Each thread in the thread array is assigned a unique thread identifier (“thread ID”) that is accessible to the thread during its execution. The thread ID, which can be defined as a one-dimensional or multi-dimensional numerical value controls various aspects of the thread's processing behavior. For instance, a thread ID may be used to determine which portion of the input data set a thread is to process and/or to determine which portion of an output data set a thread is to produce or write.

A sequence of per-thread instructions may include at least one instruction that defines a cooperative behavior between the representative thread and one or more other threads of the thread array. For example, the sequence of per-thread instructions might include an instruction to suspend execution of operations for the representative thread at a particular point in the sequence until such time as one or more of the other threads reach that particular point, an instruction for the representative thread to store data in a shared memory to which one or more of the other threads have access, an instruction for the representative thread to atomically read and update data stored in a shared memory to which one or more of the other threads have access based on their thread IDs, or the like. The CTA program can also include an instruction to compute an address in the shared memory from which data is to be read, with the address being a function of thread ID. By defining suitable functions and providing synchronization techniques, data can be written to a given location in shared memory by one thread of a CTA and read from that location by a different thread of the same CTA in a predictable manner. Consequently, any desired pattern of data sharing among threads can be supported, and any thread in a CTA can share data with any other thread in the same CTA. The extent, if any, of data sharing among threads of a CTA is determined by the CTA program; thus, it is to be understood that in a particular application that uses CTAs, the threads of a CTA might or might not actually share data with each other, depending on the CTA program, and the terms “CTA” and “thread array” are used synonymously herein.

FIG. 3Cis a block diagram of the SPM310ofFIG. 3A, according to one embodiment of the invention. The SPM310includes an instruction L1 cache370that is configured to receive instructions and constants from memory via L1.5 cache335. A warp scheduler and instruction unit312receives instructions and constants from the instruction L1 cache370and controls local register file304and SPM310functional units according to the instructions and constants. The SPM310functional units include N exec (execution or processing) units302and P load-store units (LSU)303.

SPM310provides on-chip (internal) data storage with different levels of accessibility. Special registers (not shown) are readable but not writeable by LSU303and are used to store parameters defining each CTA thread's “position.” In one embodiment, special registers include one register per CTA thread (or per exec unit302within SPM310) that stores a thread ID; each thread ID register is accessible only by a respective one of the exec unit302. Special registers may also include additional registers, readable by all CTA threads (or by all LSUs303) that store a CTA identifier, the CTA dimensions, the dimensions of a grid to which the CTA belongs, and an identifier of a grid to which the CTA belongs. Special registers are written during initialization in response to commands received via front end212from device driver103and do not change during CTA execution.

A parameter memory (not shown) stores runtime parameters (constants) that can be read but not written by any CTA thread (or any LSU303). In one embodiment, device driver103provides parameters to the parameter memory before directing SPM310to begin execution of a CTA that uses these parameters. Any CTA thread within any CTA (or any exec unit302within SPM310) can access global memory through a memory interface214. Portions of global memory may be stored in the L1 cache320.

Local register file304is used by each CTA thread as scratch space; each register is allocated for the exclusive use of one thread, and data in any of local register file304is accessible only to the CTA thread to which it is allocated. Local register file304can be implemented as a register file that is physically or logically divided into P lanes, each having some number of entries (where each entry might store, e.g., a 32-bit word). One lane is assigned to each of the N exec units302and P load-store units LSU303, and corresponding entries in different lanes can be populated with data for different threads executing the same program to facilitate SIMD execution. Different portions of the lanes can be allocated to different ones of the G concurrent thread groups, so that a given entry in the local register file304is accessible only to a particular thread. In one embodiment, certain entries within the local register file304are reserved for storing thread identifiers, implementing one of the special registers.

Shared memory306is accessible to all CTA threads (within a single CTA); any location in shared memory306is accessible to any CTA thread within the same CTA (or to any processing engine within SPM310). Shared memory306can be implemented as a shared register file or shared on-chip cache memory with an interconnect that allows any processing engine to read from or write to any location in the shared memory. In other embodiments, shared state space might map onto a per-CTA region of off-chip memory, and be cached in L1 cache320. The parameter memory can be implemented as a designated section within the same shared register file or shared cache memory that implements shared memory306, or as a separate shared register file or on-chip cache memory to which the LSUs303have read-only access. In one embodiment, the area that implements the parameter memory is also used to store the CTA ID and grid ID, as well as CTA and grid dimensions, implementing portions of the special registers. Each LSU303in SPM310is coupled to a unified address mapping unit352that converts an address provided for load and store instructions that are specified in a unified memory space into an address in each distinct memory space. Consequently, an instruction may be used to access any of the local, shared, or global memory spaces by specifying an address in the unified memory space.

The L1 cache320in each SPM310can be used to cache private per-thread local data and also per-application global data. In some embodiments, the per-CTA shared data may be cached in the L1 cache320. The LSUs303are coupled to a uniform L1 cache375, the shared memory306, and the L1 cache320via a memory and cache interconnect380. The uniform L1 cache375is configured to receive read-only data and constants from memory via the L1.5 Cache335.

FIG. 4is a conceptual diagram of a graphics processing pipeline400, that one or more of the PPUs202ofFIG. 2can be configured to implement, according to one embodiment of the invention. For example, one of the SPMs310may be configured to perform the functions of one or more of a vertex processing unit415, a geometry processing unit425, and a fragment processing unit460. The functions of data assembler410, primitive assembler420, rasterizer455, and raster operations unit465may also be performed by other processing engines within a GPC208and a corresponding partition unit215. Alternately, graphics processing pipeline400may be implemented using dedicated processing units for one or more functions.

Data assembler410processing unit collects vertex data for high-order surfaces, primitives, and the like, and outputs the vertex data, including the vertex attributes, to vertex processing unit415. Vertex processing unit415is a programmable execution unit that is configured to execute vertex shader programs, lighting and transforming vertex data as specified by the vertex shader programs. For example, vertex processing unit415may be programmed to transform the vertex data from an object-based coordinate representation (object space) to an alternatively based coordinate system such as world space or normalized device coordinates (NDC) space. Vertex processing unit415may read data that is stored in L1 cache320, parallel processing memory204, or system memory104by data assembler410for use in processing the vertex data.

Primitive assembler420receives vertex attributes from vertex processing unit415, reading stored vertex attributes, as needed, and constructs graphics primitives for processing by geometry processing unit425. Graphics primitives include triangles, line segments, points, and the like. Geometry processing unit425is a programmable execution unit that is configured to execute geometry shader programs, transforming graphics primitives received from primitive assembler420as specified by the geometry shader programs. For example, geometry processing unit425may be programmed to subdivide the graphics primitives into one or more new graphics primitives and calculate parameters, such as plane equation coefficients, that are used to rasterize the new graphics primitives.

In some embodiments, geometry processing unit425may also add or delete elements in the geometry stream. Geometry processing unit425outputs the parameters and vertices specifying new graphics primitives to a viewport scale, cull, and clip unit450. Geometry processing unit425may read data that is stored in parallel processing memory204or system memory104for use in processing the geometry data. Viewport scale, cull, and clip unit450performs clipping, culling, and viewport scaling and outputs processed graphics primitives to a rasterizer455.

Rasterizer455scan converts the new graphics primitives and outputs fragments and coverage data to fragment processing unit460. Additionally, rasterizer455may be configured to perform z culling and other z-based optimizations.

Fragment processing unit460is a programmable execution unit that is configured to execute fragment shader programs, transforming fragments received from rasterizer455, as specified by the fragment shader programs. For example, fragment processing unit460may be programmed to perform operations such as perspective correction, texture mapping, shading, blending, and the like, to produce shaded fragments that are output to raster operations unit465. Fragment processing unit460may read data that is stored in parallel processing memory204or system memory104for use in processing the fragment data. Fragments may be shaded at pixel, sample, or other granularity, depending on the programmed sampling rate.

Raster operations unit465is a processing unit that performs raster operations, such as stencil, z test, blending, and the like, and outputs pixel data as processed graphics data for storage in graphics memory. The processed graphics data may be stored in graphics memory, e.g., parallel processing memory204, and/or system memory104, for display on display device110or for further processing by CPU102or parallel processing subsystem112. In some embodiments of the present invention, raster operations unit465is configured to compress z or color data that is written to memory and decompress z or color data that is read from memory.

Batch Distribution Policy

FIG. 5is a system500configured to facilitate the distribution of work batches to GPCs208-0through208-2, according to one embodiment of the invention.FIG. 5illustrates multiple instances of specific units (e.g., GPCs208-0,208-1, and208-2, etc.). However, in the following description these units will be referred to generically (e.g., GPCs208).

As shown, system500includes WDU200coupled to GPCs208. WDU200is configured to distribute work batches506to GPCs208. When a given GPC208receives a work batch506, GPC208places the received work batch506in a work FIFO512included therein. Each GPC208also includes one or more SMs510. When work FIFO512includes one or more work batches506, SMs510residing within GPC208may perform processing operations involving those work batches to generate pixels for output to a display device. When work FIFO512includes an amount of work batches that is less than a predetermined amount, GPC208transmits a “load” signal516to WDU200. In response to load signal516, WDU200may transmit additional work batches506to the GPC208that issued the load signal516. In other implementations, GPC208transmits a “credit” or “done” signal which informs WDU200that the GPC208can receive another piece of work.

As shown, GPCs208include different numbers of SMs510. GPC208-0includes SMs510-0and510-1, GPC208-1includes SM510-2, and GPC208-2includes SM510-3. GPCs208may also include any number of disabled SMs510(not shown). Certain SMs510within a GPC208may be disabled due to manufacturing defects, or, alternatively, because the manufacturer of parallel processing subsystem112intentionally disabled those SMs510. For example, the manufacturer of parallel processing subsystem112may disable certain SMs510in order to provide a low-cost version of parallel processing subsystem112having reduced processing power. In addition, parallel processing subsystem112may dynamically cause certain SMs510to be disabled and/or may cause certain SMs510to be re-allocated for processing operations other than those associated with handling work batches506.

Those skilled in the art will recognize that the number of enabled SMs510shown inFIG. 5and the number of GPCs208that include those SMs corresponds to just one exemplary configuration of system500, and, further, that other configurations of system500comprising different numbers of enabled SMs510and GPCs208are equally within the scope of the invention.

WDU200is configured to distribute work batches506to GPCs208based on the number of enabled SMs510included within each GPC208, the maximum number of enabled SMs510included in any of the GPCs208, and load signals516received from GPCs208, as described in conjunction withFIG. 6.

FIG. 6is a flowchart of method steps for distributing work batches to GPCs, according to one embodiment of the invention. Although the method steps are described in conjunction with the systems ofFIGS. 1, 2, 3A, 3B, and 3C, and 5, persons skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the invention.

As shown, the method600begins at step602, where WDU200determines the number of enabled SMs510within each GPC208, referred to herein as “SM_count.” In the exemplary configuration shown inFIG. 5, the SM_count of GPCs208-0,208-1, and208-2are two, one, and one, respectively. At step604, WDU200identifies the maximum SM_count out of all GPCs208which, in the exemplary configuration shown inFIG. 5, is equal to two. At step606, WDU200distributes work batches506to GPCs208based on the SM_count for each GPC208, the max_SM_count, and load signals512received from GPCs208.

When performing step606, WDU200may implement one of several different work distribution policies, or simply “policies.” A first policy is described below in conjunction withFIG. 7. A second policy is described below in conjunction withFIG. 8, and a third policy is described below in conjunction withFIG. 9.

Referring back now toFIG. 5, when implementing a given policy to distribute work batches506, WDU200performs a “scheduling round” and one or more “distribution rounds.” When performing the scheduling round, WDU200determines which GPCs208, if any, are scheduled to receive work batches506. When performing the distribution rounds, WDU200distributes work batches506to the GPCs208scheduled to receive work batches506. Once all such GPCs208have received work batches506, WDU200again performs a scheduling round and determines which, if any, GPCs208are scheduled to receive work batches506during subsequent distribution rounds. In one embodiment, WDU200distributes one or more work batches506to GPCs208in a single distribution round and/or scheduling round.

WDU200determines whether to schedule each GPC208to receive a work batch506based on the policy implemented by WDU200and based on a counter514associated with the GPC208. Counter514-0corresponds to GPC208-0, counter514-1corresponds to GPC208-1, and counter514-1corresponds to GPC208-2. WDU200increments and decrements each counter at different times depending on the specific policy currently being implemented by WDU200. Then, based on the value of the counter514, WDU200determines whether to schedule the GPC208corresponding to that counter to receive a work batch506during a subsequent distribution round. The first policy is described below in conjunction withFIG. 7.

FIG. 7is a flowchart of method steps for distributing work batches to GPCs in a modified round-robin fashion, according to one embodiment of the invention. Although the method steps are described in conjunction with the systems ofFIGS. 1, 2, 3A, 3B, and 3C, and 5, persons skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the invention.

According to the first policy, as implemented by the method700described herein, WDU200increments each counter514at each scheduling round by the number of SMs510included in the corresponding GPC208(SM_count). When a given counter514is greater than or equal to the maximum number of SMs510included in any GPC208(max_SM_count), and when the GPC208associated with the counter514has issued load signal516, WDU200distributes a work batch506to the GPC208and decrements the counter514associated with the GPC208by max_SM_count.

The method700begins at step702, where, for each GPC208, WDU200adds SM_count associated with the GPC208to the counter514corresponding to the GPC208. SM_count represents the number of enabled SMs510within the GPC308. WDU200may update each counter514in parallel, or, alternatively, in serial. The counters514may have any initial value. For example, counters514could have a value left over from a previous series of distribution rounds. Counters514may also be set to zero initially, or, alternatively, initialized to a specific value when WDU200begins distribution.

The method700then iterates over steps704,706,708,710, and712for each GPC208in the sequence of GPCs208. For the sake of clarity, the following description of these steps is directed towards the sequence of steps performed for a single GPC208.

At step704, WDU200determines whether counter514corresponding to GPC208is greater than or equal to max_SM_count. If WDU200determines that counter514is not greater than or equal to max_SM_count, then the method700proceeds to step714. However, if WDU200determines that counter514is greater than or equal to max_SM_count, then the method700proceeds to step706.

At step706, WDU200determines whether GPC208received a work batch506during the previous distribution round. WDU200avoids distributing work batches to any GPC208twice in a row (i.e., on two or more consecutive distribution rounds). If WDU200determines that GPC208received a work batch506during the previous distribution round, then WDU200does not distribute a work batch506to GPC208and the method700proceeds to step714. In one embodiment, WDU200identifies a GPC that did not receive a work batch506during the previous distribution round and distributes a work batch506to that GPC instead of distributing to GPC208.

If WDU200determines that GPC208did not receive a work batch506during the previous distribution round, then the method700proceeds to step708. At step708, WDU200determines whether load signal516has been received from GPC208. If WDU200determines that load signal516has not been received from GPC208, then the method700proceeds to step714and WDU200does not schedule GPC208to receive a work batch506. However, if WDU200determines that load signal516has been received from GPC208, then the method700proceeds to step710and WDU200distributes a work batch506to GPC208. At step712, WDU200decrements counter514corresponding to GPC208by max_SM_count. The method700then proceeds to step714.

According to steps704,706, and708, at a given scheduling round, WDU200schedules GPC208to receive a work batch506when i) the counter514corresponding to the GPC208is greater than or equal to max_SM_count, ii) the GPC208did not receive a work batch506during the previous distribution round, and iii) the GPC208has issued load signal516, respectively. If any of i), ii), or iii) are not met, then WDU200does not implement steps710or712, and, thus, WDU200does not distribute a work batch506to the GPC208or decrement counter514associated with GPC208. In either case, the method700eventually proceeds to step714.

Step714is implemented for every GPC208in the sequence of GPCs. At step714, WDU200determines whether any load signals516have been received from GPCs208that have a counter514that is greater than or equal to max_SM_count. When any GPCs208i) have issued load signal516and ii) are associated with a counter514that exceeds max_SM_count, the method700returns to step704and proceeds as described above. Otherwise, the method700returns to step702and proceeds as described above.

In one embodiment, WDU200maintains a “greater than” mask, a “not previous” mask, and a “load” mask. The greater than mask specifies GPCs208associated with counters514that have a value greater than or equal to max_SM_count. The “not previous” mask specifies GPCs208that were not distributed to on the previous distribution round. The load mask specifies GPCs208that have issued the load signal. The greater than mask can be calculated at step704, the not previous mask can be calculated at step706, and the load mask can be calculated at step708. WDU200ANDs some or all of these masks to identify GPCs208that should receive work batches506. WDU200then decrements the counters514associated with those GPCs208. With any combination of masks, when the result of the AND operation is all zeros, the method700returns to step702and WDU200increments each counter514by the respective SM_count. Through the technique described herein, WDU200may perform steps704,706,708,710, and712for each GPC208in parallel.

WDU200may implement the first policy, as described above, in order to distribute work batches506to GPCs208based on the number of SMs510included within those GPCs. However, the first policy may be inefficient and/or ineffective when the processing time required to process a work batch506varies widely between different work batches. In such a situation, a single GPC208may become overloaded with processing tasks relative to the other GPCs. The second and third policies, described below in conjunction withFIGS. 8 and 9, respectively, address this specific issue.

FIG. 8is a flowchart of method steps for distributing work batches to GPCs when batch processing times vary significantly over time, according to one embodiment of the invention. Although the method steps are described in conjunction with the systems ofFIGS. 1, 2, 3A, 3B, and 3C, and 5, persons skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the invention.

According to the second policy, as implemented by the method800, WDU200increments each counter514by SM_count at each scheduling round, in similar fashion to the first policy. However, unlike the first policy, WDU200does not schedule GPCs208to receive work batches506based on whether counters514associated with those GPCs208exceed max_SM_count. Instead, WDU200identifies the GPC208that i) has the highest value of counter514and ii) has issued load signal516. When any of the counters514are greater than or equal to a maximum counter value (max_ctr), then WDU200stalls distribution to all GPCs208until load signals512are received from the GPCs208associated with the counters that are greater than or equal to the total number of SMs510in parallel processing subsystem112(SM_total). Through this technique, WDU200identifies a situation where a particular GPC208has received work batches506that require a disproportionate amount of time to process, and, in response, stalls distribution until that GPC “catches up” to the other GPCs208, as indicated by the load signal516.

As shown, the method800begins at step802, where WDU200adds SM_count to the respective counter514. As with the first policy, each counter514may have any initial value. At step804, WDU200determines whether any counters514exceed the maximum counter value, max_ctr. In one embodiment, max_ctr is equal to the maximum counter value that can physically be stored by counters514. In another embodiment, max_ctr may be different for each counter514.

If WDU200determines that none of counters514exceed max_ctr, the method800proceeds to step810. At step810, WDU200identifies the GPC208that i) has the highest counter value, ii) has issued a load signal516, and iii) has a counter value greater than or equal to SM_total. If condition iii is not met, then the distribution returns to step802. At step812, WDU200distributes a work batch506to the identified GPC. At step814, WDU200subtracts SM_total from the counter514associated with the identified GPC. The method then returns to step802and proceeds as described above.

At step804, if WDU200determines that any of counters514exceed max_ctr, then the method800proceeds to step806. At step806, WDU200determines whether a load signal516has been received from the GPCs208with counters514that exceed max_ctr. If WDU200determines that no load signals516have been received from the GPCs208with counters514that exceed max_ctr, then the method800proceeds to step808. At step808, WDU200stalls distribution to all GPCs208until load signals516are received from the GPCs208associated with counters514that exceed max_ctr. Once those load signals516are received, the method proceeds to step810and proceeds as described above.

WDU200may implement the second policy, as described above, when the time required to process work batches506varies significantly. In certain situations, though, stalling distribution according to the second policy is undesirable. As described in conjunction withFIG. 9, the third policy outlines an approach that does not involve stalling the distribution of work batches while still accounting for differences in batch processing times.

FIG. 9is a flowchart of method steps for distributing work batches506to GPCs208when batch processing times vary over time, according to one embodiment of the invention. Although the method steps are described in conjunction with the systems ofFIGS. 1, 2, 3A, 3B, and 3C, and 5, persons skilled in the art will understand that any system configured to perform the method steps, in any order, is within the scope of the invention.

According to the third policy, as implement by the method900, WDU200increments each counter514by SM_count at each scheduling round when the counter514does not exceed a “counter cap” value (ctr_cap). When a given counter514is greater that or equal to ctr_cap, WDU200stops incrementing that counter514until the corresponding GPC208issues a load signal516. WDU200identifies the GPC208that i) has the highest counter value and ii) has issued load signal516, and then distributes a work batch506to the identified GPC.

As shown, the method900begins at step902, where, for each GPC208having a counter514that is less than ctr_cap, WDU200adds SM_count to the counter514associated with that GPC. Since SM_count may be different for each GPC208and, thus, for each counter514, WDU200may add a different SM_count value to each counter514.

At step904, WDU200identifies the GPC208that i) is associated with the counter514having the highest counter value, ii) has issued load signal516, and iii) has a counter value greater than or equal to the total number of SMs510in parallel processing subsystem112(SM_total). WDU200then distributes a work batch506to the identified GPC. At step908, WDU200subtracts SM_total from the counter514associated with the identified GPC.

WDU200may implement the third policy, as described above, in situations where batch processing times vary over time and distribution should not be stalled.

WDU200may implement any of the three policies described herein to distribute work batches506to GPCs208. In one embodiment, WDU200dynamically determines a specific policy based on the work batches506to be processed.

In sum, a work distribution unit (WDU) distributes batches of processing tasks to general processing clusters (GPCs) according to one of three different work distribution policies. When implementing any of these policies, the WDU distributes work batches to the GPCs based on the number of streaming multiprocessors (SMs) included in each GPC and based on a counter that is maintained for each GPC.

When implementing the first policy, the WDU increments each counter by the number of SMs included in the GPC associated with the counter. When the counter meets or exceeds the maximum number of SMs in any GPC, the WDU distributes a work batch to the GPC and decrements the counter by that maximum number.

When implementing the second policy, the WDU increments each counter by the number of SMs included in the GPC associated with the counter. When any counter reaches a maximum counter value, the WDU stalls distribution until a load signal is received from the GPCs associated with the counters that have reached the maximum counter value. The WDU then distributes work batches to those GPCs following the policy described above.

When implementing the third policy, the WDU increments each counter by the number of SMs included in the GPC associated with the counter until the counter meets or exceeds a counter cap. The WDU then stops incrementing that counter until a load signal is received from the GPC associated with that counter. When the load signal is received, the WDU distributes a work batches to the GPC and decrements the counter accordingly.

Advantageously, when any of the three policies described herein are implemented by the WDU, each GPC receives an amount of work from the WDU that is proportional to the processing power afforded by the GPC. In addition, the WDU may abstain from distributing work batches to some or all of the GPCs in order to balance the workload across all of the GPCs.