Low-voltage differential signaling (differential signaling) driver circuit and method of enabling and disabling a differential signaling driver circuit

A Low-Voltage Differential Signaling (differential signaling) driver circuit (10) comprising enable circuitry for enabling and disabling the differential signaling driver circuit (10) in accordance with an control signal is described. The differential signaling driver circuit (10) comprises: a differential output (12, 13) connected or connectable to a differential signaling receiver circuit via a differential transmission line; current control circuitry (14) for driving a signal current through the differential output (12, 13) in accordance with a driver signal; feedback circuitry (16) for driving the current control circuitry (14) to counteract a difference between a common mode voltage of the differential output (12, 13) and a reference voltage from a reference voltage provider; and the enable circuitry (18). The feedback circuitry (16) comprises a common mode node (20) for providing the common mode voltage (Vcm), a reference input (22) connected or connectable to the reference voltage provider, and a feedback input (24). The enable circuitry (18) is arranged to connect the feedback input (24) to the common mode node (20) when the differential signaling driver circuit (10) is in an enabled state and to the reference voltage provider when the differential signaling driver circuit (10) is in a disabled state. A method of enabling (5.1) and disabling (5.2) a Low-Voltage Differential Signaling (differential signaling) driver circuit (10) is also proposed.

FIELD OF THE INVENTION

This invention relates to a differential signaling driver circuit and to a method of enabling and disabling a differential signaling driver circuit.

BACKGROUND OF THE INVENTION

Differential signaling is a way of transmitting a differential signal from a transmitter to a receiver via a differential transmission line, e.g., via a pair of wires, e.g., copper wires. A differential signaling driver circuit drives an electrical current through the transmission line in accordance with a driver signal. The electrical current in the transmission line is referred to herein as the signal current. The driver signal may, for example, be provided by a voltage, an electrical current or any other suitable physical quantity.

A differential signaling receiver circuit may comprise a resistive bridge connected across the differential output of the transmission line, i.e., between the two conductors of the transmission line at the end of the transmission line. The electrical current injected into the transmission line by the differential signaling driver circuit thus translates into a voltage across the resistive bridge at the end of the transmission line. This voltage may be further processed or analysed by the differential signaling receiver circuit or by circuitry connected to the differential signaling receiver circuit.

The driver signal is usually a bi-level signal, i.e. a binary signal. However, a differential signaling driver circuit may, in principle, be capable of translating any kind of waveform of the driver signal into a corresponding waveform of the signal current. In other words, a differential signaling driver circuit may be suitable for both continuous (i.e., analogue) and discrete (i.e., digital) driver signals.

Differential signaling may be performed in a low-voltage manner when a differential signal of low voltage amplitude is superimposed on a common mode DC voltage. For example a differential signal with a maximum amplitude of 0.5 V or less, e.g. 350 mV may be imposed on a common mode voltage of 1.5 V or less, such as 1.2 V or less, e.g. 0.9 V or less, e.g. 0.4 V. This is generally referred to as LVDS, for which several different standards have been developed, such as IEEE 1596.3, ANSI/TIA/EIA-644-A and several variations such as M-LVDS, sub-LVDS, etc.

SUMMARY OF THE INVENTION

The present invention provides a differential signaling driver circuit and a method as described in the accompanying claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now toFIG. 1, an example of a differential signaling driver circuit10is schematically shown. The differential signaling driver circuit10may for example be a low-voltage differential signaling driver circuit10suitable for low voltage differential signaling, for example as compliant with a LVDS standard, such as IEEE 1596.3 or ANSI/TIA/EIA-644-A. The differential signaling driver circuit10may comprise a differential output12,13for driving the signal current. The differential output12,13comprises a first output terminal12and a second output terminal13. The output terminals12,13may, for example, be provided by contact pads, contact pins or any other kind of conductive element connectable to an input of a differential transmission line. The differential signaling driver circuit10comprises current control circuitry14for controlling the signal current in accordance with a driver signal A. The driver signal A may, for example, be a driver voltage for controlling a voltage controlled control element, e.g., voltage controlled switches28,29,30,31, of the current control circuitry14. In other words, each of the switches28,29,30,31may be turned on and off in accordance with the driver signal A.

In the example, the differential signaling driver circuit comprises gate control logic40for generating the driver signal A and its inverse, an inverted driver signal Ā in accordance with, e.g., a digital data input stream. The digital data input stream may thus be translated into the driver signal A which in turn may be translated into the signal current injected into the transmission line (not shown) which connects the differential signaling receiver circuit to the differential signaling driver circuit10.

The differential signaling driver circuit10further comprises feedback circuitry16for driving the current control circuitry14to counteract a difference between a common mode voltage Vcm of the differential output12,13and a reference voltage from a reference voltage provider (not shown). In the example, the reference voltage is 1.2 volts above a low side voltage provider6, e.g., ground. However, it will be apparent that other voltages suitable for the specific implementation may be used as well. The current circuit element has a control input at which a voltage cab be provided and a current output at which the current circuit element provides a current which is controlled, e.g. by the voltage applied, and e.g. proportional to the voltage. The reference voltage provider may, for example, be a node of a voltage divider connected between a low side voltage provider6and a high side voltage provider8. The low side voltage provider6and the high side voltage provider8may, for example, be the terminals of a battery or other kind of DC power supply.

The differential signaling driver circuit10further comprises enable circuitry18for enabling and disabling the differential signaling driver circuit10in response to a control signal, e.g. which indicates ‘enable’ when it has a first value and which indicates ‘disable when it has a second value different from the first value. The first value may for example a first binary value and the second value the opposite binary value. Thus, the enable circuitry18enables the differential signaling driver circuit10in response to receiving the control signal indicating ‘enable’ and the enable circuitry18disables the differential signaling driver circuit10in response to receiving the control signal indicating “disable”.

When the differential signaling driver circuit is enabled, the differential signaling driver circuit10is operational to inject the signal current into the differential signaling receiver circuit connected to the differential output12,13, and to control the signal current in accordance with the driver signal A. In contrast, when the differential signaling driver circuit is disabled (in response to receiving the control signal indicating “disable”), one or more of its components are in a disabled state and the differential signaling driver circuit is then not capable of operating normally. The disabled state of the differential signaling driver circuit10may be considered a standby state, that is, a state in which the differential signaling driver circuit10is kept on power but does not provide its full functionality.

Depending on the specific implementation, the disabled state of the differential signaling driver circuit10may serve different purposes. In one example, the differential signaling driver circuit10may intentionally be disabled to interrupt the transmission of data from the differential signaling driver circuit10to the differential signaling receiver circuit. For example, the differential signaling driver circuit10may be disabled in order to save power without switching the differential signaling driver circuit10entirely off in response to detecting interference of the differential signaling driver circuit10with another device. This can be useful, for example, in the event of a temporary interruption of the digital data input stream.

The feedback circuitry16may be implemented in any manner suitable for the specific implementation. The feedback circuitry16may be arranged to minimize the difference between the reference voltage and the common mode voltage Vcm by controlling the current control element34in a negative feedback loop. As shown inFIG. 1, the feedback circuitry may comprise a common mode node20, a reference input22, and a feedback input24. The common mode node20may, for example, be connected between the first terminal12and the second terminal13of the differential output12,13, in order to feedback the common mode voltage. The reference input22is connected or connectable to the reference voltage provider in order to receive the reference voltage (not shown). The operational amplifier46has a first input providing the reference input22, a second input providing the feedback input24, and the output36connected to control the current control element34. More specifically, the operational amplifier46may be arranged to deliver an amplifier output voltage at its output36in dependence of a voltage difference between the first input and the second input, that is, in dependence of the voltage difference between the reference input22and the feedback input24.

In the example, the feedback circuitry16comprises an operational amplifier46and a current control element34. The current control element34may, for example, be connected between the high side voltage provider8and the current control circuitry14. In the example, the current control element34is a field effect transistor (FET), e.g., a PMOS FET with a source connected to the high side voltage provider8, a drain connected to the current control circuitry14, and a gate connected to an output36of the operational amplifier46. In another example (not shown), the current control element34can be an NMOS FET connected between the current control circuitry14and the low side voltage provider6, while the current source32is connected between the high side voltage provider8and the current control circuitry14.

Still referring toFIG. 1, the differential signaling driver circuit10may operate as follows, when enabled and when connected to a differential signaling receiver circuit via the differential outputs12,13. When the driver signal A is high, switches28and31are on, i.e., conductive, while switches29and30are off, i.e., not conductive. The current source32then drives a constant current from the high side voltage provider8to the low side voltage provider6through the current control element34, the switch28, the output terminal12, the differential signaling receiver circuit, the output terminal13, and the switch31. The current drawn by the current source32thus traverses the differential signaling receiver unit (not shown) in a forward direction. In contrast, when the driver signal A is low, the switches28and31are off and the switches29and30are on. The current source32then drives a suitable current from the high side voltage provider8to the low side voltage provider6through the current control element34, the switch29, the output terminal13, the differential signaling receiver circuit, the output terminal12, and the switch30. In this configuration, the current drawn by the current source32thus traverses the differential signaling receiver circuit in a reverse direction opposite to the forward direction. The current may have any suitable value, and for example be 10 mA or less, such as 5 mA. The current may have the same value for the reverse direction and the forward direction or be different for both directions.

When the differential signaling driver circuit10is enabled, a resistive bridge may be connected between the output terminal12and the output terminal13, a midpoint20of the resistive bridge serving as a pick-off point for providing the common mode voltage. This pick-off point, i.e., the midpoint of the resistive bridge, is referred to herein as the common mode node20. The common mode node20may be considered the midpoint of the resistive bridge in the sense that the electrical resistance between the common mode node20and the output terminal12equals the electrical resistance between the common mode node20and the output terminal13. For example, the common mode node20may be connected to the output terminal12by a first resistor26of resistance RFB and to the output terminal13by a second resistor27of the resistance RFB. It may thus be ensured that the voltage at the common mode node20is indeed the common mode voltage of the differential output12,13, that is, the mean value of the voltage at the output terminal12and the output terminal13. In other words, Vcm=(V1+V2)/2 wherein V1 and V2 are the voltage levels at the output terminal12and13, respectively. In the example, the resistive bridge is part of an H bridge which comprises the resistive bridge and four legs, each leg comprising one of the switches28,29,30,31.

As shown inFIG. 1, the common mode voltage Vcm may be applied at the feedback input24of the feedback circuitry16, thereby controlling the current control element34to provide more current when the common mode voltage Vcm is lower than the reference voltage and to provide less current when the common mode voltage Vcm is higher than the reference voltage.

When the differential signaling driver circuit10is disabled, e.g., in response to the control signal being low, the voltage at the feedback input24may drift. For example, when the voltage at the feedback input24is substantially equal to the reference voltage during the enabled state of the differential signaling driver circuit10, it may drift away from the reference voltage.

For example, still consideringFIG. 1, the switches38and39may be turned off when the differential signaling driver circuit10is disabled in order to reduce a leakage current across the resistive bridge and also to reduce a possible leakage current through the feedback input24. In this example, the feedback loop is therefore disrupted when the differential signaling driver circuit10is disabled, allowing the voltage at the feedback input24to drift. In another example (not shown), the resistive bridge comprising the common mode node20is not disrupted when the differential signaling driver circuit10is disabled, but some other component, e.g., the operational amplifier46, is turned off, also resulting in a disruption of the feedback loop and allowing the voltage at the feedback input24to drift.

This voltage drift may be reduced by a suitable operation of the enable circuitry. For example, the feedback input24and the reference input22may both be connected to the reference voltage provider when the differential signaling driver circuit10is disabled. The feedback input24may thus be provided with a voltage which as a predefined difference (ΔV) with the voltage provided to the reference input22, with ΔV for example being zero. The feedback circuitry16may thus be pre-set to a state identical or similar to a state expected to be reached by negative feedback control when the differential signaling driver circuit is enabled. It has been observed that pre-setting the feedback circuitry16in this manner tends to reduce the enable time of the differential signaling driver circuit10, that is, to reduce the duration of a transition from the disabled state to the enabled state.

Notably, pre-setting the feedback input24to the reference voltage, e.g. 1.2 volts, has been observed to make the common mode voltage of the differential output12,13settle more rapidly at the reference voltage as compared to, for example, the circuit shown inFIG. 1. Furthermore, signal overshoot, distortions and oscillations of the common mode voltage (which may occur during a transition from the disabled to the enabled state) may be reduced. It has been found that an enable time of the differential signaling driver circuit10shorter than ten nanoseconds or even shorter than five nanoseconds may be achieved. The differential signaling driver circuit10may thus be arranged, for example, to meet a timing requirement of a media local bus interface, namely the requirement of providing valid data no later than, e.g., two clock cycles after an control signal, wherein the media local bus interface may have an operation frequency of up to 400 megahertz, for example.

The reference voltage may be provided to the feedback node24in any manner suitable for the specific implementation. For example, as shown in the example ofFIG. 2, (in which the differential signaling driver circuit10may for example be a low-voltage differential signaling driver circuit10suitable for low voltage differential signaling, for example as compliant with a LVDS standard, such as IEEE 1596.3 or ANSI/TIA/EIA-644-A)., the enable circuitry18may further be arranged to connect the feedback input24to the common mode node20when the differential signaling driver circuit is in an enabled state and to the reference voltage provider (not shown) when the differential signaling driver circuit10is in a disabled state. The enable circuitry18may e.g. comprise a first switch42arranged to connect the feedback input24to the reference voltage provider when the control signal is negative and to isolate the feedback input24from the reference voltage provider when the control signal is positive (or high).

The enable circuitry18may further comprise a second switch44arranged to isolate the feedback input24from the common mode node20when the control signal is indicates ‘enable’ (e.g. negative (or low)) and to connect the feedback input24to the common mode node20when the control signal is ‘disable’ (e.g. positive (or high)). The second switch44may allow to avoid an electrical current from the reference voltage provider and through the common mode node20when the circuit10is disabled, such as for example in differential signaling driver circuits without switches between the common mode node20and the output terminals12,13. The first switch42and the second switch44may, for example, be transistors operated as switches, such as FETs.

Alternatively, or additionally, as in the example ofFIG. 2, the common mode node20may be isolated from the differential output12,13when the differential signaling driver circuit10is disabled. With such a design, the common mode node20may remain connected to the feedback node24when the differential signaling driver circuit10is disabled. This may be used as well when the differential signaling driver circuit10lacks the second switch44.

FIG. 3illustrates the time dependence of the common mode voltage Vcm observed in an example of a differential signaling driver circuit of the kind described in reference toFIG. 1(dashed line) and of the kind described in reference toFIG. 2(continuous line). The transition time of the common mode voltage Vcm in the event of enabling the differential signaling driver circuit is seen to be significantly shorter (<10 ns) with the circuit ofFIG. 2as compared to the circuit ofFIG. 1(>20 ns). Furthermore, the overshoot is reduced. Referring toFIG. 4, a similar reduction of transition time and overshoot of the differential output voltage is seen as well.

An example of a method of enabling and disabling a differential signaling driver circuit10is schematically represented by the flow chart inFIG. 5. The differential signaling driver circuit10, e.g., the one describe above in reference toFIG. 2, may be arranged to be enabled and disabled in accordance with a control signal. The control signal may, for example, be a binary signal, with values or levels true and false, or, equivalent, high and low, or one and zero. Enabling the differential signaling driver circuit10comprises setting the differential signaling driver circuit10into an enabled state, that is, a state in which the differential signaling driver circuit10is capable of driving the signal current through its output terminals12and13in accordance with the digital data input stream. In a variant of the example of a differential signaling driver circuit10shown inFIG. 2, the digital data input stream may be replaced by an analogue signal and the differential signaling driver circuit may be arranged to modulate the signal current in accordance with the analogue signal.

The method may start with enabling the differential signaling driver circuit10(Box5.1). Enabling the differential signaling driver circuit may, for example, comprise enabling the resistive bridge between the output terminals12and13, e.g., by turning the switches38and39on. Enabling (Box5.1) the differential signaling driver circuit10further comprises connecting the feedback input24of the feedback circuitry16to the common mode node20, thus applying the common mode voltage Vcm at the feedback input24. Enabling (Box5.1) the differential signaling driver circuit further comprises disconnecting the feedback input24from the reference voltage provider.

Enabling (Box5.1) the differential signaling driver circuit10may be followed by disabling (Box5.2) the differential signaling driver circuit10. Disabling (Box5.2) the differential signaling driver circuit10may, for example, comprise interrupting the resistive bridge between the output terminals12and13, e.g., by turning the switches38and39off. Disabling the differential signaling driver circuit10further comprises connecting the feedback input24to the reference voltage provider. It may further comprise disconnecting the feedback input24from the common mode node20. The operations of enabling and disabling the differential signaling driver circuit10may be repeated in an alternating manner.

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader scope of the invention as set forth in the appended claims, and that the claims are not limited to the specific examples described above. For example, the connections may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise the connections may for example be direct connections or indirect connections. Furthermore, although in the examples FET are shown, it will be apparent that other devices may be used when suitable, such as bipolar switches or MEMS switches.

Likewise, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

The conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa. Also, plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.

Those skilled in the art will recognize that boundaries between the operations described with reference toFIG. 5are merely illustrative. The multiple operations may be combined into a single operation, and/or a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.