Semiconductor device

A horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor substrate; a collector layer of the first conductivity type formed within the semiconductor region; a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other.

CROSS-REFERENCE TO RELATED APPLICATION

The disclosure of Japanese Patent Applications No. 2005-367544 filed on Dec. 21, 2005 and No. 2006-98740 filed on Mar. 31, 2006 including specification, drawings and claims are incorporated herein by reference in its entirely.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Technical Field

The present invention relates to a semiconductor device, and more particularly, to a high-voltage power semiconductor device.

2. Description of the Related Art

Background Art

FIG. 49is a top view of a conventional horizontal n-channel IGBT (Insulated Gate Bipolar Transistor) generally denoted at700.FIG. 50is a cross sectional view ofFIG. 49taken along the direction X-X.

As shown inFIG. 50, the IGBT700includes a p-type substrate1. The p-type substrate1seats an n−layer2in which an n-type buffer layer3is formed. There is a p-type collector layer4in the n-type buffer layer3.

A p-type base layer5is formed in the n−layer2, over a predetermined distance from the p-type collector layer4. In the p-type base layer5, an n-type emitter layer (n+)6is formed so that it is on the inner side relative to a peripheral portion of the p-type base layer5and shallower than the p-type base layer5. A p-type emitter layer (p+)7as well is formed in the p-type base layer5.

A field oxide film8is formed on the surface of the n−layer2which is located between the n-type buffer layer3and the p-type base layer5. On a channel region15formed in the p-type base layer5and located between the emitter layer6and the n−layer2, a gate wire10is disposed via a gate oxide film9. Further, there is a protection film11which is disposed covering the field oxide film8and the like.

A gate electrode12is disposed such that it is electrically connected with the gate wire10. An emitter electrode13is further disposed such that it is electrically connected with both the n-type emitter layer6and the p-type emitter layer7. In addition, a collector electrode14is disposed such that it is electrically connected with the p-type collector layer4. The emitter electrode13, the collector electrode14and the gate electrode12are electrically isolated from each other.

As shown inFIG. 49, the p-type collector layer4is located at the center of the IGBT700in which structure the n-type buffer layer3, the n−layer2, the p-type base layer5, the n-type emitter layer6and the p-type emitter layer7surround the p-type collector layer4in this order, and this structure has an endless shape which is defined by connecting two semi-circular sections by straight sections. For easy understanding,FIG. 49omits the field oxide film8, the gate oxide film9, the gate wire10, the gate electrode12, the protection film11, the emitter electrode13and the collector electrode14(JPB 3647802).

SUMMARY OF THE INVENTION

FIG. 51shows a collector-emitter current (ICE) characteristic which the IGBT1000exhibits upon application of a collector-emitter voltage (VCE) in a condition that a constant gate-emitter voltage (VGE) is applied upon the IGBT700. The collector-emitter voltage (VCE) is measured along the horizontal axis, whereas the vertical axis denotes the collector-emitter current (ICE). A room temperature is a temperature for measurement.

FromFIG. 51, one can see that as VCEgradually rises, ICEbecomes approximately 0.2 A when VCEreaches 6V or becomes close to 6V and beyond this, ICEtends to get saturated. This causes a problem that however high VCEbecomes, ICEwill not become sufficiently large. There is another problem that as the gradient expressing ICEremains moderate while VCEgrows from 0V to 6V and the ON-resistance (VCE/ICE) is therefore high.

FIG. 52shows the turn-off waveform of the IGBT700. The turn-off time is measured along the horizontal axis and the collector-emitter voltage (VCE) or the collector-emitter current (ICE) is measured along the vertical axis. InFIG. 52, the symbol (AV) denotes changes of the VCEvalue and the symbol (AI) denotes changes of the ICEvalue.

As one can tell fromFIG. 52, the fall time (i.e., the time needed for ICEto come down to 10% from 90% which is the maximum value) has a large value exceeding 1 μs. The junction-isolated (JI) horizontal IGBT700in which the IGBT is formed in the n−layer2on the p-type substrate1thus has problem that its switching speed is slow and it has a large switching loss.

The horizontal IGBT700has a further problem that a short-circuit in an inverter circuit or the like latches up a parasitic thyristor which is formed by the p-type collector layer4/the n-type buffer layer3/the n−layer2/the p-type base layer5/the n-type emitter layer6and increases the current density of the IGBT700so that the IGBT may get destroyed easily.

The present invention has been made to solve these problems, and accordingly, an object of the present invention is to provide a semiconductor device which exhibits an improved collector-emitter current characteristic, shortens the fall time and increases the latch-up tolerance of a parasitic thyristor.

The present invention is directed to a horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including:

a semiconductor substrate of a first conductivity type;

a semiconductor region of a second conductivity type formed on the semiconductor substrate;

a collector layer of the first conductivity type formed within the semiconductor region;

a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and

a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, wherein

the unit semiconductor elements are disposed adjacent to each other.

According to the present invention, it is possible to obtain a semiconductor device which exhibits an excellent collector-emitter current characteristic and has a short fall time and in which the latch-up tolerance of a parasitic thyristor is high.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a top view of a horizontal n-channel IGBT (Insulated Gate Bipolar Transistor) according to the embodiment 1 of the present invention generally denoted at100.FIG. 2is a cross sectional view ofFIG. 1taken along the direction A-A.

As shown inFIG. 2, the IGBT100includes a p-type substrate1of silicon or the like. The p-type substrate1seats an n−layer2in which an n-type buffer layer3is selectively formed. There is a p-type collector layer4selectively formed in the n-type buffer layer3.

The buffer layer3may be omitted (This similarly applies also to the embodiments described below.).

In the n−layer2, the p-type base layer5is selectively formed in over a predetermined distance from the p-type collector layer4. In the p-type base layer5, the n-type emitter layers (n+)6are selectively formed so that they are located on the inner side relative to a peripheral portion of the p-type base layer5and shallower than the p-type base layer5. A p-type emitter layer (p+)7as well is formed in the p-type base layer5.

A field oxide film8which may be a silicon oxide film for instance is formed on the surface of the n−layer2which is located between the n-type buffer layer3and the p-type base layer5. On a channel region15formed in the p-type base layer5and located between the emitter layer6and the n−layer2, a gate wire10is disposed via a gate oxide film9which may be a silicon oxide film for example. The gate wire10is made of aluminum for example. Further, a protection film11which may be a silicon nitride film for instance is disposed covering the field oxide film8, etc.

A gate electrode12is disposed such that it is electrically connected with the gate wire10. The gate electrode12is made of aluminum for example.

An emitter electrode13is further disposed such that it is electrically connected with both the n-type emitter layers6and the p-type emitter layer7. In addition, a collector electrode14is disposed such that it is electrically connected with the p-type collector layer4. The emitter electrode13and the collector electrode14are made of aluminum for instance. The emitter electrode13, the collector electrode14and the gate electrode12are electrically isolated from each other.

Further, as shown inFIG. 1, the IGBT100according to the embodiment 1 has a structure that ring-like multiple unit IGBTs, in each one of which the p-type collector layer4is located at the center and surrounded by the n-type buffer layer3, the n−layer2, the p-type base layer5, the n-type emitter layer6and the p-type emitter layer7in this order, are arranged adjacent to each other and disposed side by side. Although the foregoing has described that the unit IGBTs have circular shapes, the unit IGBTs may have oval shapes which are close to circles or polygonal shapes which are close to circles.

FIG. 3is a top view of another IGBT according to the embodiment 1 of the present invention generally denoted at150. This is the same structure as that of the IGBT100except for that the p-type emitter layers7of circle-like adjacent unit IGBTs partially overlap each other.

FIG. 4shows a relationship between the number of unit IGBTs and the total channel width, each in an instance that an IGBT is formed by a single conventional IGBT700which is long and thin and has an endless shape and an instance that an IGBT is like the IGBT150according to the embodiment 1 which is formed by plural circular unit IGBTs. InFIG. 4, the horizontal axis denotes the number of unit IGBTs and the vertical axis denotes the total channel width.

Where multiple circular unit IGBTs are disposed side by side, the total channel width is longer as compared with where only one thing and long IGBT is used: The total channel width in an instance that ten unit IGBTs are disposed side by side is approximately double the channel width of one IGBT.

FIG. 5shows a channel region of the conventional IGBT700over the IGBT150which is formed by three unit IGBTs. It is seen that use of the IGBT150according to the embodiment 1 increases the channel width.

FIG. 6is a graph which compares the surface area sizes (occupation area sizes) of the IGBT150according to the embodiment 1 and the conventional IGBT which are compared against each other inFIG. 5. The horizontal axis denotes the number of unit IGBTs, while the vertical axis denotes the surface area size of the IGBT. It is seen that more unit IGBTs in the structure, the smaller the surface area size is, as compared with the IGBT700which has the conventional structure.

As shown inFIG. 7, for instance, in the event that the IGBT150is formed by three unit IGBTs, the surface area size indicated by the shaded area can be reduced as compared with the IGBT700which has the conventional structure.

In the event that a horizontal IGBT is to be formed in an area of a limited space, use of the IGBT100or150according to the embodiment 1 reduces the surface area size (occupation area size) and extends the total channel width as compared with the IGBT700which has the conventional structure.

FIG. 8shows a collector-emitter current (ICE) characteristic which the IGBT1500according to the embodiment 1 exhibits upon application of a collector-emitter voltage (VCE) in a condition that a constant gate-emitter voltage (VGE) is applied upon the IGBT150. The collector-emitter voltage (VCE) is measured along the horizontal axis, whereas the vertical axis denotes the collector-emitter current (ICE). A room temperature is a temperature for measurement.

FromFIG. 8, one can see that as VCEgradually rises, ICEbecomes approximately 0.4 A when VCEreaches 6V or becomes close to 6V and around beyond this, ICEtends to get saturated, and ICEon that occasion has a large value which is about double that of the conventional IGBT (seeFIG. 51). It is also seen that the gradient is greater than in the conventional IGBT while VCEgrows from 0V to 6V and that the ON-resistance (VCE/ICE) is low.

The improved ICEcharacteristic is attributable to the longer total channel width than that of the IGBT700which has the conventional structure.

WhileFIGS. 4 through 8refer to the IGBT150, an approximately similar result is obtained on the IGBT100as well.

FIG. 9is a top view of a horizontal n-channel IGBT according to the embodiment 2 of the present invention generally denoted at200.FIG. 10is a cross sectional view ofFIG. 9taken along the direction B-B. InFIGS. 9 and 10, the same reference symbols as those appearing inFIGS. 1 and 2denote the same or corresponding portions.

As shown inFIG. 10, the IGBT200has an SOI structure in which a buried oxide film20which may be a silicon oxide film for example is formed between the p-type substrate1and the n−layer2. The structure is otherwise the same as that of the IGBT100. The structure of the IGBT200shown in the top view inFIG. 9is the same as the structure of the IGBT100shown inFIG. 2. In this structure, the conductivity type of the substrate1can be chosen irrespectively of the conductivity type of the n−layer2.

FIG. 11is a top view of another IGBT according to the embodiment 2 of the present invention generally denoted at250. This is the same structure as that of the IGBT200except for that the p-type emitter layers7of circle-like adjacent unit IGBTs partially overlap each other.

The IGBTs100and150according to the embodiment 1 may be called “the junction-isolated type” while the IGBTs200and250according to the embodiment 2 may be called “dielectric-isolated type”.

FIG. 12shows the turn-off waveform of the IGBT200. The turn-off time is measured along the horizontal axis and the collector-emitter voltage (VCE) or the collector-emitter current (ICE) is measured along the vertical axis. InFIG. 12, the symbols (1V) and (1C) denote changes of the VCEvalue and the ICEvalue in the IGBT100according to the embodiment 1, and the symbols (2V) and (2C) denote changes of the VCEvalue and the ICEvalue in the IGBT200according to the embodiment 2.

Although the fall time (tf: the time needed for ICEto come down to 10% from 90% which is the maximum value) has a large value exceeding 1 μs in the IGBT700which has the conventional structure shown inFIG. 50, the fall time is approximately 0.5 μs in the IGBT (See (2C).) according to the embodiment 2. The IGBT according to the embodiment 2 thus has a faster switching speed and a smaller switching loss than the conventional IGBT (FIG. 52). In the turn-off waveform as it is upon switching of a resistance load, as VCErises, ICEdecreases at about the same absolute value of falling rate as that of the rising rate of VCE.

FIG. 13shows a current distribution (solid lines) and a voltage distribution (dashed lines) and the boundary line of a depletion region (dotted-and-dashed line) as they are at the time of switching turn-off of a resistance load (10.6 μs) within the junction-isolated horizontal IGBT100according to the embodiment 1 described above, which drawing corresponds to the cross sectional view inFIG. 1.

In the case of the junction-isolated horizontal IGBT100, a depletion layer expanding from the emitter side spreads not only to the collector side but even to the p-type substrate, and therefore, the electric potential distribution and the current distribution as well spread to the p-type substrate. This suppresses depletion toward the collector side and makes the VCEincrease relatively moderate. As a result, the corresponding ICEdecrease as well is relatively moderate.

FIG. 14shows a hole distribution (solid lines) as it is at the time of switching turn-off of a resistance load (10.6 μs) within the junction-isolated horizontal IGBT100according to the embodiment 1 described above, which drawing corresponds to the cross sectional view inFIG. 1.

In the junction-isolated horizontal IGBT100, as shown inFIG. 13, depletion toward the collector side from the emitter side is suppressed, there are numerous holes distributed inside n−layer and the p-type substrate. When there are numerous holes distributed inside n−layer, the p-type substrate and the like, it takes time until the holes disappear and the fall time (tf) becomes relatively long.

FIG. 15shows (a) a hole distribution and (b) an electron distribution at the time of switching turn-off of a resistance load (10.6 μs) and (c) a concentration as it is in equilibrium within the junction-isolated horizontal IGBT100according to the embodiment 1 described above, which drawing shows the distributions from the collector side to the emitter side at a constant depth inside n−layer.

As shown inFIG. 13, since depletion toward the collector side from the emitter side is suppressed in the junction-isolated horizontal IGBT100, the n−layer excessively contains holes and electrons beyond their concentrations in equilibrium. Since there are numerous and excessive holes and electrons within the n−layer, it takes a long time before the excessive holes and electrons disappear from the n layer. Due to this, the fall time (tf) is only slightly faster than in the IGBT700which has the conventional structure.

Meanwhile,FIG. 16shows an electric potential distribution (solid lines), (b) a current distribution (dashed lines) and the boundary line of a depletion region (dotted-and-dashed line) at the time of switching turn-off of a resistance load (10.6 μs) within the dielectric-isolated horizontal IGBT200according to the embodiment 2, which drawing corresponds to the cross sectional view inFIG. 10.

In the dielectric-isolated horizontal IGBT200, due to the buried oxide film present between the n−layer and the p-type substrate, a depletion layer spreading from the emitter side will not expand to the p-type substrate but instead grows toward the collector side within the n−layer. The p-type substrate therefore does not have a current distribution or an electric potential distribution. This encourages depletion toward the collector side, which increases VCE. In consequence, the corresponding ICEas well increases, which quickens the fall time (tf).

FIG. 17shows a hole distribution (denoted at the solid lines) as it is at the time of switching turn-off of a resistance load (10.6 μs) within the dielectric-isolated horizontal IGBT200according to the embodiment 2, which drawing corresponds to the cross sectional view inFIG. 10.

In the dielectric-isolated horizontal IGBT200, as shown inFIG. 16, depletion toward the collector side from the emitter side is facilitated, and hence, there are a few holes distributed within the n−layer. Due to this, it takes only a short time before the holes distributed within the n−layer disappear and the fall time (tf) becomes short.

FIG. 18shows (a) a hole distribution and (b) an electron distribution at the time of switching turn-off of a resistance load (10.6 μs) and (c) a concentration as it is in equilibrium within the dielectric-isolated horizontal IGBT200, which drawing shows the distributions from the collector side to the emitter side at a constant depth inside n−layer.

In the dielectric-isolated horizontal IGBT200, as described above, since depletion toward the collector side from the emitter side is facilitated, an area free from the spreading depletion layer is narrow in the n−layer. Hence, with in the n−layer, there are only a few holes and electrons beyond their concentrations in equilibrium (excessive holes and excessive electrons). When there are only a few excessive holes and electrons in the n−layer, it takes only a short time before the excessive holes and electrons disappear, which quickens the fall time (tf).

The IGBT200according to the embodiment 2 thus shortens the fall time (tf), in addition to the improved emitter current (ICE) characteristic which is realized by the IGBT100according to the embodiment 1.

WhileFIGS. 16 through 18refer to the IGBT200, an approximately similar effect is attained by the IGBT250as well.

The structure of disposing the insulation film20between the p-type substrate1and the n−layer is applicable also to conventional IGBTs.

FIG. 19is a cross sectional view of a horizontal n-channel IGBT according to the embodiment 3 of the present invention generally denoted at300, which is illustration viewed from the same direction as the A-A direction inFIG. 1. InFIG. 19, the same reference symbols as those appearing inFIG. 2denote the same or corresponding portions.

The IGBT300shown inFIG. 19includes, on the emitter side, a p−layer30which is formed narrower and deeper than the p-type base layer5but not deep enough to reach the p-type substrate1in such a manner that it contacts the bottom surface of the p-type base layer5. The structure is otherwise the same as that of the IGBT100which is shown inFIG. 2.

FIG. 20is a cross sectional view of other horizontal n-channel IGBT according to the embodiment 3 of the present invention generally denoted at350, which is illustration viewed from the same direction as the B-B direction inFIG. 9. InFIG. 20, the same reference symbols as those appearing inFIG. 10denote the same or corresponding portions.

The IGBT350shown inFIG. 20includes, on the emitter side, a p−layer30whose width (the length along the right-to-left direction inFIG. 20) is narrower and which is deeper than the p-type base layer5but not deep enough to reach the buried insulation film20in such a manner that it contacts the bottom surface of the p-type base layer5. The structure is otherwise the same as that of the IGBT200which is shown inFIG. 10.

FIG. 21shows a current distribution (solid lines), an electric field distribution (dashed lines) and the boundary line of a depletion region (dotted-and-dashed line) as they are at the time of switching turn-off of a resistance load (10.6 μs) within the dielectric-isolated horizontal IGBT200according to the embodiment 2, which drawing corresponds to the cross sectional view inFIG. 10.

Meanwhile,FIG. 22shows a current distribution (solid lines) and an electric field distribution (dashed lines) as they are at the time of switching turn-off of a resistance load (10.6 μs) and the boundary line of a depletion region (dotted-and-dashed line) within the dielectric-isolated horizontal IGBT350according to the embodiment 3, which drawing corresponds to the cross sectional view inFIG. 20.

One can tell fromFIG. 21that in the dielectric-isolated structure including the buried insulation film, the current flows through the n−layer which is right above the buried oxide film.

Noting this, the p−layer may be disposed in a lower section of the p-type base layer, to thereby permit the hole current arriving at the n−layer on the emitter side easily flow into a section developing a high electric field at the bottom of the p−layer.

FIG. 22of the IGBT350shows that the hole current flowing immediately below the n-type emitter layer is less than in the IGBT250(FIG. 21). In consequence, a parasitic thyristor will not easily operate in the IGBT350unlike in the IGBT250, which improves the latch-up tolerance.

Further, the width of the p−layer is narrower than the p-type base layer in the IGBT350. Due to this, the hole current arriving at the n−layer on the emitter side flows approximately upward within the p−layer to the emitter electrode, which shortens the fall time (tf) than in the IGBT250which does not include the p−layer.

As described above, in the IGBTs300and350according to this embodiment, the p−layer formed in the lower section of the p-type base layer prevents latching-up of a parasitic thyristor and shortens the fall time (tf). This effect is remarkable particularly in the case of the IGBT350including the buried insulation film in particular.

The structure that the p−layer is formed in the lower section of the p-type base layer may be applied to a conventional IGBT to achieve a similar effect.

FIG. 23is a top view of a part of a horizontal n-channel IGBT according to the embodiment 4 of the present invention generally denoted at400, showing the n-type emitter (n+) layer6formed within the p-type base layer5(a connection region with an emitter electrode (emitter contact region)).

As shown inFIG. 23, the n-type emitter layer6includes multiple outwardly protruding projections (convex areas)16in the IGBT400. As shown inFIG. 23, the relationship W1>W2holds between the width of the projections16(W2) and the gap between the neighboring projections16(W1). The structure is otherwise the same as that of the IGBT100described earlier.

FIG. 24is a cross sectional view ofFIG. 23taken along the direction C-C, andFIG. 25is a cross sectional view ofFIG. 23taken along the direction D-D.FIGS. 24 and 25also show the flows of holes as they are upon turning off of the IGBT and during the steady ON-state.

The width of the n-type emitter layer in the cross sectional view inFIG. 24is approximately equal to the width of the n-type emitter layer of the IGBT100shown inFIG. 1. Meanwhile, the width of the n-type emitter layer in the cross sectional view inFIG. 25is narrower than the width of the n-type emitter layer6of the IGBT100shown inFIG. 1.

InFIG. 25, since the width of the n-type emitter (n+) is narrow, the width of the p-type base layer right under the n-type emitter layer of a parasitic npn bipolar transistor formed by the n−layer/the p-type base layer/the n-type emitter layer is narrow, and the base resistance of the p-type base region is low. This suppresses an operation of the parasitic npn bipolar transistor and prevents latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n−layer/the p-type base layer/the n-type emitter layer.

Thus, at the time of turning off or during the steady ON-state of the IGBT400according to the embodiment 4, the latch-up tolerance of a parasitic thyristor improves in the IGBT.

Further, in the IGBT400, the projections16are portions of the n-type emitter layer6and the both are connected electrically with each other, and hence, use of this structure will not reduce the channel width than in the IGBT100. For this reason, the collector-emitter current (ICE) characteristic upon application of the collector-emitter voltage (VCE) in a condition that the constant gate-emitter voltage (VGE) is applied is excellent as in the IGBT100.

In addition, the n-type emitter layer has the projections and their sizes satisfy the relationship W1>W2(FIG. 23) in the IGBT400. In short, with a gate electrode leading wire disposed between two projections as shown inFIG. 26makes it unnecessary to sever the n-type emitter layer which intersects gate electrode leading wires as in the conventional structure. This permits disposing gate electrode leading wires without reducing the channel width.

Hence, the collector-emitter current (ICE) characteristic upon application of the collector-emitter voltage (VCE) in a condition that the constant gate-emitter voltage (VGE) is applied is excellent

The n-type emitter layer having such a structure is applicable also to a conventional IGBT.

FIG. 27is a top view which shows the arrangement of the p-type emitter layer (denoted at the symbol “p+” inFIGS. 24 and 25) vis-à-vis the n-type emitter layer in the horizontal n-channel IGBT shown inFIG. 23.

As shown inFIG. 27A, the p-type emitter layer may be shaped like a stripe which surrounds the n-type emitter layer.

Alternatively, as shown inFIGS. 27A and 27B, the p-type emitter layer may be shaped like a ring which is along the n-type emitter layer. Shown inFIG. 27is the shape in which there is a predetermined gap between the p-type emitter layer and the n-type emitter layer, while shown inFIG. 27Cis the shape in which the p-type emitter layer and the n-type emitter layer contact each other.

Further, alternatively, as shown inFIG. 27D, the p-type emitter layer may be discontinuous along the n-type emitter layer.

Such a configuration of the p-type emitter layer is applicable also to the p-type emitter layers of the other embodiments.

FIG. 28is a top view of a part of a horizontal n-channel IGBT according to the embodiment 5 of the present invention generally denoted at500, showing a connection region (emitter contact region) between the n-type emitter layer and the emitter electrode.FIG. 29is a cross sectional view of the IGBT500shown inFIG. 28taken along the direction E-E.

As shown inFIG. 28, in the IGBT500according to the embodiment 5, the projections of the n-type emitter layer have T-shaped tips in addition to what the IGBT400(FIG. 25) includes, which increases the size of the area where the n-type emitter layer and emitter electrode wires contact each other. The structure is otherwise the same as the IGBT400.

The n-type emitter layer newly disposed in the IGBT500is formed to have a narrow width (the length along the horizontal direction inFIG. 29) as shown inFIG. 29. This lowers the base resistance in the p-type base region right under the n-type emitter layer in a parasitic npn bipolar transistor formed by the n−layer/the p-type base layer/the n-type emitter layer. This suppresses an operation of the parasitic npn bipolar transistor and prevents latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n−layer/the p-type base layer/the n-type emitter layer. In consequence, at the time of turning off or during the steady ON-state of the horizontal n-channel IGBT500, the latch-up tolerance of a parasitic thyristor improves in the IGBT.

Further, in the IGBT500, since the area where the n-type emitter layer and emitter electrode wires contact each other expands, the contact resistance between the n-type emitter layer and the emitter electrode wires is small.

As described above, in the horizontal n-channel IGBT500according to the embodiment 5, the projections of the n-type emitter layer are T-shaped unlike in the IGBT according to the embodiment 4, which increases the size of the area where the n-type emitter layer and the emitter electrode wires contact each other and reduces the contact resistance between the n-type emitter layer and the emitter electrode wires. The result of this is an improved collector-emitter current (ICE) characteristic upon application of the collector-emitter voltage (VCE) in a condition that the constant gate-emitter voltage (VGE) is applied.

The n-type emitter layer having this structure is applicable also to a conventional IGBT.

FIG. 30is a top view is an IGBT generally denoted at600which is a combination of two IGBTs150according to the embodiment 1.FIG. 31is a top view is an IGBT generally denoted at650which is a combination of two IGBTs700.FIG. 32is a cross sectional view of the IGBT600ofFIG. 30taken along the direction F-F. InFIGS. 30 and 31, the same reference symbols as those used inFIGS. 2 and 3denote the same or corresponding portions.

As denoted at the shade lines inFIGS. 30 and 31, in the IGBTs600and650according to the embodiment 6, there are p-type emitter layers17disposed in areas between a common contact line to adjacent two unit IGBTs and two IGBTs and areas enclosed by three adjacent unit IGBTs, which expands the area sizes of the contact between the p-type emitter layers and the emitter electrode wires.

In this structure, the p-type emitter layers7and17are relatively wider than the n-type emitter layer6. This reduces the contact resistance between the p-type emitter layers7and17and emitter wires, and ensures a smooth flow of holes to the contact region, where the p-type emitter (p+) layers and the emitter wires (emitter electrode) contact, without becoming stagnant immediately below the n-type emitter layer as shown inFIG. 32. An indirect reason behind this is the reduced base resistance at the p-type base region right under the n-type emitter layer.

This suppresses an operation of a parasitic npn bipolar transistor formed by the n−layer/the p-type base layer/the n-type emitter layer and prevents latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n−layer/the p-type base layer/the n-type emitter layer. In consequence, at the time of turning off or during the steady ON-state of the horizontal n-channel IGBT600, the latch-up tolerance of a parasitic thyristor improves in the IGBT.

FIG. 33is a cross sectional view of a horizontal n-channel IGBT according to the embodiment 7 of the present invention generally denoted at1100, which is illustration viewed from the same direction as the A-A direction inFIG. 1. InFIG. 33, the same reference symbols as those appearing inFIG. 19denote the same or corresponding portions.

As compared to the IGBT300according to the embodiment 3 (FIG. 19), the IGBT1100according to the embodiment 7 (FIG. 33) has a structure which does not include the p-type emitter layers7, except for which the structure is the same as that of the IGBT300. In the IGBT1100, there is no p-type emitter, but instead the p-type base layer5has a structure which serves also as a p-type emitter.

FIG. 34is a cross sectional view of other horizontal n-channel IGBT according to the embodiment 7 of the present invention generally denoted at1150, which is illustration viewed from the same direction as the A-A direction inFIG. 1. InFIG. 34, the same reference symbols as those appearing inFIG. 20denote the same or corresponding portions. The structure of the IGBT1150is the same that of the IGBT1100as it is modified to additionally include the buried insulation film20.

As compared to the IGBT350according to the embodiment 3 (FIG. 20), the IGBT1150according to the embodiment 7 (FIG. 34) has the same structure as that of the IGBT350except for omission of the p-type emitter layers7. In the IGBT1150as well, there is no p-type emitter, but instead the p-type base layer5serves also as a p-type emitter.

In the IGBTs1100and1150according to the embodiment 7, the p−layer disposed in a lower section of the p-type base layer prevents latching-up of a parasitic thyristor and shortens the fall time (tf). This effect is remarkable particularly in the case of the IGBT1150including the buried insulation film in particular.

The structure is simple as the p-type base layer5serves also as a p-type emitter, which in turn simplifies the manufacturing process.

FIG. 35is a top view of a part of a horizontal n-channel IGBT according to the embodiment 8 of the present invention generally denoted at1200, showing the n-type emitter (n+) layer6formed within the p-type base layer5(a connection region with an emitter electrode (emitter contact region)).

As in the IGBT400shown inFIG. 23, the n-type emitter layer6includes multiple outwardly protruding projections (convex areas)16in the IGBT1200, and the relationship W1>W2holds between the width of the projections16(W2) and the gap between the neighboring projections16(W1).

FIG. 36is a cross sectional view ofFIG. 35taken along the direction C-C, andFIG. 37is a cross sectional view ofFIG. 35taken along the direction D-D.

As compared to the IGBT400according to the embodiment 4 described above, the IGBT1200according to the embodiment 8 (FIGS. 36 and 37) has a structure which does not include the p-type emitter layers, except for which the structure is the same as that of the IGBT400. In the IGBT1200, there is no p-type emitter, but instead the p-type base layer5has a structure which serves also as a p-type emitter.

Having such a structure, the IGBT1200according to the embodiment 8 achieves an approximately similar effect to that according to the IGBT400described above. In addition, the structure is simple as the p-type base layer serves also as a p-type emitter, which in turn simplifies the manufacturing process.

In other words, since the width of the n-type emitter (n+) is narrow inFIG. 37, the width of the p-type base layer right under the n-type emitter layer of a parasitic npn bipolar transistor formed by the n−layer/the p-type base layer/the n-type emitter layer is narrow, and the base resistance of the p-type base region is low. This suppresses an operation of the parasitic npn bipolar transistor and prevents latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n−layer/the p-type base layer/the n-type emitter layer.

Thus, at the time of turning off or during the steady ON-state of the IGBT1200according to the embodiment 8, the latch-up tolerance of a parasitic thyristor improves in the IGBT.

FIG. 38is a top view of a part of a horizontal n-channel IGBT according to the embodiment 9 of the present invention generally denoted at1300, showing a connection region (emitter contact region) between the n-type emitter layer and the emitter electrode.FIG. 39is a cross sectional view of the IGBT1300shown inFIG. 38taken along the direction E-E.

As compared to the IGBT500according to the embodiment 5 (FIGS. 28 and 29), the IGBT1300according to the embodiment 9 (FIGS. 38 and 39) has a structure which does not include the p-type emitter layers, except for which the structure is the same as that of the IGBT500. In the IGBT1300, there is no p-type emitter, but instead the p-type base layer5has a structure which serves also as a p-type emitter.

Having such a structure, the IGBT1300according to the embodiment 9 achieves an approximately similar effect to that according to the IGBT500described above. In addition, the structure is simple as the p-type base layer5serves also as a p-type emitter, which in turn simplifies the manufacturing process.

In other words, in the IGBT1300, since the projections of the n-type emitter layer have T-shaped tips in addition to what the IGBT400according to the embodiment 4 includes, which increases the size of the area where the n-type emitter layer and emitter electrode wires contact each other and reduces the contact resistance between the n-type emitter layer and the emitter electrode wires. The result of this is an improved collector-emitter current (ICE) characteristic upon application of the collector-emitter voltage (VCE) in a condition that the constant gate-emitter voltage (VGE) is applied.

FIG. 40is a top view of a part of a horizontal n-channel IGBT according to the embodiment 10 of the present invention generally denoted at1400, in which the same reference symbols as those appearing inFIG. 30denote the same or corresponding portions.FIGS. 41 through 43are enlarged views of the portion denoted at A inFIG. 40.

In the IGBT1400according to the embodiment 10, there are the p-type emitter layers17disposed in areas between a common contact line to adjacent two unit IGBTs and two IGBTs, which expands the area of the contact between the p-type emitter layers and the emitter electrode wires (emitter contact region) (FIGS. 41 through 43show the emitter contact region.). This brings about a similar effect to that promised by the IGBT650according to the embodiment 6 described earlier (FIG. 31).

In short, it is possible to suppress an operation of a parasitic npn bipolar transistor formed by the n−layer/the p-type base layer/the n-type emitter layer and to prevent latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n−layer/the p-type base layer/the n-type emitter layer. In consequence, at the time of turning off or during the steady ON-state of the horizontal n-channel IGBT1400, the latch-up tolerance of a parasitic thyristor improves in the IGBT.

As shown inFIGS. 40 and 41, the n-type emitter layer6may be disposed discontinuously along the p-type base layer5in the IGBT1400. Alternatively, the n-type emitter layer6may be disposed in an endless shape although not shown.

Further alternatively, the n-type emitter layer6may have an endless-shape structure in which multiple outwardly-protruding projections (convex areas) are formed in the IGBT1400, as shown inFIG. 42.

Yet another alternative is to use a structure without any p-type emitter layer7in the structure which is shown inFIG. 42, as shown inFIG. 43.

The p-type emitter layers17of the IGBT1400according to this embodiment can be formed regardless of the shape of the n-type emitter layer6or whether there is the p-type emitter layers7, thereby improving the latch-up tolerance of a parasitic thyristor at the time of turning off or during the steady ON-state of the IGBT1400,

FIG. 44is a top view of other horizontal n-channel IGBT according to the embodiment 10 of the present invention generally denoted at1500, in which the same reference symbols as those appearing inFIG. 30denote the same or corresponding portions.FIGS. 45 through 47are enlarged views of the portion denoted at B inFIG. 44.

In the IGBT1500, there are the p-type emitter layers17disposed in areas between a common contact line to adjacent two unit IGBTs and two IGBTs and areas enclosed by adjacent three unit IGBTs, which expands the area of the contact between the p-type emitter layers and the emitter electrode wires (emitter contact region) (FIGS. 44 through 47show the emitter contact region.). This brings about a similar effect to that promised by the IGBT600according to the embodiment 6 described earlier (FIG. 30).

In short, it is possible to suppress an operation of a parasitic npn bipolar transistor formed by the n−layer/the p-type base layer/the n-type emitter layer and to prevent latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n−layer/the p-type base layer/the n-type emitter layer. In consequence, at the time of turning off or during the steady ON-state of the horizontal n-channel IGBT1500, the latch-up tolerance of a parasitic thyristor improves in the IGBT.

As shown inFIGS. 44 and 45, the n-type emitter layer6may be disposed discontinuously along the p-type base layer5in the IGBT1500. Alternatively, the n-type emitter layer6may be disposed in an endless shape although not shown.

Further alternatively, the n-type emitter layer6may have an endless-shape structure in which multiple outwardly-protruding projections (convex areas) are formed in the IGBT1400, as shown inFIG. 46.

Yet another alternative is to use a structure without any p-type emitter layer7in the structure which is shown inFIG. 46, as shown inFIG. 47.

In this structure, the p-type emitter layers7and17are relatively wider than the n-type emitter layer6. This reduces the contact resistance between the p-type emitter layers7and17and emitter wires, and ensures a smooth flow of holes to the contact region, where the p-type emitter (p+) layers and the emitter wires (emitter electrode) contact, without becoming stagnant immediately below the n-type emitter layer as shown inFIG. 48(the cross sectional view ofFIG. 46taken along the direction H-H). An indirect reason behind this is the reduced base resistance at the p-type base region right under the n-type emitter layer.

This suppresses an operation of a parasitic npn bipolar transistor formed by the n−layer/the p-type base layer/the n-type emitter layer and prevents latching-up of a parasitic thyristor formed by the p-type collector layer/the n-type buffer layer/the n−layer/the p-type base layer/the n-type emitter layer. In consequence, at the time of turning off or during the steady ON-state of the horizontal n-channel IGBT1500, the latch-up tolerance of a parasitic thyristor improves in the IGBT.

Although the embodiments 1 through 10 are directed to horizontal n-channel IGBTs, the present invention is applicable also to a horizontal p-channel IGBT in which case the p-type and the n-type appearing in the description above should be replaced with each other.

The present invention is further applicable to a horizontal MOSFET, a horizontal device using other MOS gate structure or the like.