Re-quantization in downlink receiver bit rate processor

A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.

FIELD OF THE INVENTION

This invention relates to wireless communication systems and, more particularly, to a downlink receiver bit rate processor for use in wireless systems. The invention is particularly useful in TDSCDMA wireless systems, but is not limited to TDSCDMA systems.

BACKGROUND OF THE INVENTION

TDSCDMA (Time Division Synchronous Code Division Multiple Access) is a wireless radio standard for the physical layer of a 3G (third generation) air interface. Different from WCDMA and CDMA2000, which adopt a frequency division duplex, TDSCDMA is designed for time division duplex/multiple access (TDD/TDMA) operation with synchronous CDMA technology.

TDSCDMA uses time domain duplexing in combination with multiple access techniques to support both symmetrical and asymmetrical traffic. The variable allocation of time slots for uplink or downlink traffic allows TDSCDMA to meet asymmetric traffic requirements and to support a variety of users. In TDSCDMA systems, multiple access techniques employ both unique codes and time signatures to separate the users in a given cell. The TDSCDMA standard defines a frame structure with three layers: the radio frame, the subframe and the time slot. The radio frame is 10 ms. The subframe is 5 ms. and is divided into seven time slots. A time slot has four parts: a midamble, two data fields on each side of the midamble and a guard period. The receiver uses the midamble to perform channel estimation.

In CDMA systems, many users access the same channel simultaneously. Each user is separated from the others by a code known as the spreading code. However, each new user added to the system produces interference with the other users. In CDMA systems, this multiple access interference (MAI) is the limiting factor in system capacity.

Multiple access interference equally affects all users in a CDMA system. To deal with this, other systems use detection schemes such as the rake receiver. However, rake receivers are suboptimal because they consider only the user's signal information in the detection process, with no attempt to characterize the interference from the other users. By contrast, joint detection algorithms process all users in parallel and thus include the interference information from the other users. Joint detection schemes are complex and computationally intensive. Complexity grows exponentially as the number of codes increases. Joint detection is well-suited to TDSCDMA systems because the number of users in a time slot is limited to 16. The result is a joint detector of reasonable complexity.

In traditional communication systems, the baseband receiver includes two main components: an inner receiver, also known as an equalizer or a chip rate processor, which mitigates the effects of multipath and interference, and an outer receiver which performs channel decoding and other symbol rate processing. Circuitry for implementing a TDSCDMA baseband processor may use different approaches, ranging from a programmable digital signal processor to application-specific integrated circuits (ASICs). The programmable digital signal processor has the advantage of flexibility for different applications but may not have sufficient computation speed to process TDSCDMA signals in real time. ASICs may have higher computation speed but have limited flexibility for different applications and different processing algorithms.

Accordingly, there is a need for TDSCDMA architectures and implementations which achieve high computation speed, flexibility and programmability.

SUMMARY OF THE INVENTION

According to a first aspect of the invention, a bit rate processor to process physical channel data in a wireless system is provided. The bit rate processor comprises a front end processor to process the physical channel data and to generate transport channel data associated with transport channels; a transport channel buffer to hold the transport channel data; and a back end processor to process the transport channel data from the transport channel buffer and to generate transport channel bits, the back end processor including a decoder and a scaling circuit, the scaling circuit being configured to scale transport channel data supplied to the decoder according to a scaling factor associated with each transport channel.

According to a second aspect of the invention, a method for scaling of transport channel data in a bit rate processor in a wireless system is provided. The method comprises processing the physical channel data to provide transport channel data; scaling the transport channel data according to a scaling factor associated with each transport channel; and decoding the scaled transport channel data to provide transport channel bits for each transport channel.

DETAILED DESCRIPTION

A block diagram of a downlink receiver for a TDSCDMA wireless device is shown inFIG. 1. A radio10receives signals via an antenna12and supplies the signals to an analog baseband (ABB) circuit14. The analog baseband circuit processes the received signals in the analog domain and supplies a digital signal at its output. The receiver further includes a digital baseband circuit20and a coprocessor22. The digital baseband circuit20may include a control processor such as a programmable digital signal processor (DSP)24. DSP24may include a core processor, memory, a DMA controller and various interface circuits. DSP24may communicate with coprocessor22via an external coprocessor bus30which is controlled by an external coprocessor interface (ECPI) master32in digital baseband circuit20and an ECPI slave34in coprocessor22. Coprocessor22may include a bit rate processor40and a joint detector42. Bit rate processor40and joint detector42communicate with DSP24via external coprocessor bus30.

In some embodiments, the components of coprocessor22may be incorporated in the digital baseband circuit20with DSP24. In these embodiments, DSP24, bit rate processor40and joint detector42may be interconnected by one or more internal buses, and external coprocessor bus30is not required.

A schematic representation of the TDSCDMA data structure is shown inFIG. 2. Data is transmitted as a series of radio frames60,62, etc., each having a duration of 10 ms (milliseconds). Each radio frame is divided into two subframes64and66, each having a duration of 5 ms. Each subframe is made up of seven time slots70,72, etc, each having a duration of 0.675 ms. Each time slot includes four parts, a midamble with 144 chips duration, two data fields with 352 chips duration before and after the midamble, followed by a guard period of 16 chips. The midamble carries known data and is used by the receiver to perform channel estimation. The seven time slots in each subframe may be divided between uplink and downlink traffic, according to the traffic in each direction.

The joint detector processes the received data for each downlink time slot and generates physical channel data. Each time slot may include up to 16 users and up to 16 spreading codes. The major function of the joint detector is to solve the linear equation
(THT+σ2I)x=THr,
where T is a matrix that represents the channel characteristics, r is a vector that represents the received signal and σ2represents noise. The joint detector processes all user signals in parallel and thus includes interference information from other users. The joint detector separates physical channel data according to user. In some embodiments, joint detection operations may be divided between joint detector42and DSP24. For example, DSP24can perform channel estimation and post processing, and joint detector42can perform matrix computations.

Referring again toFIG. 1, bit rate processor40and joint detector42are circuits that perform computations under control of DSP24. Joint detector42receives data, control parameters and control signals, such as triggers to begin processing, from DSP24. Joint detector42processes the data and returns the processed data to DSP24. Similarly, bit rate processor40receives physical channel data, control parameters and control signals, such as triggers to begin processing, from DSP24. Bit rate processor40processes the data in accordance with the control parameters and returns decoded transport channel bits to DSP24. As described below, the baseband processing functions may be divided between DSP24and coprocessor22. DSP24is programmable and can perform functions that can be modified and updated with relative ease, whereas coprocessor22is hard wired and performs fixed functions, with the parameters of the fixed functions being programmable. In general, joint detector42and bit rate processor40perform computation-intensive functions that are less likely to change, whereas DSP24performs functions that are less computation-intensive and which may be changed or which may be performed differently by different users.

A simplified block diagram of bit rate processor40in accordance with an embodiment of the invention is shown inFIG. 3. Bit rate processor40includes a front end processor300, a back end processor302and a transport channel buffer304coupled between front end processor300and back end processor302. Front end processor300receives physical channel data from DSP24(FIG. 1) and provides encoded transport channel data to transport channel buffer304. The physical channel data is generated by joint detector42and is provided to bit rate processor40by way of DSP24. The front end processor300involves processing at the coded composite transport channel (CCTrCH) level. The back end processor302processes the encoded transport channel data from transport channel buffer304and provides decoded transport channel bits to DSP24. The back end processor302operates on a transport channel (TrCH) basis. In cases where the physical channel data contains more than one coded composite transport channel, the coded composite transport channels are processed serially by the front end processor300. In cases where each coded composite transport channel contains more than one transport channel, the transport channels are processed serially by the back end processor302.

As shown inFIG. 3, the architecture of bit rate processor40includes computation stages and buffer memories. In the embodiment ofFIG. 3, bit rate processor40includes a first stage310and a second stage312in front end processor300, and a third stage314in back end processor302. Thus, front end processor300includes first stage310, second stage312, a frame buffer320and an intermediate frame buffer322. Back end processor302includes third stage314and an output buffer324. The operations performed by the first, second and third stages are discussed below.

Frame buffer320receives physical channel data generated by joint detector42(FIG. 1) and supplies the physical channel data to first stage310for processing. Intermediate frame buffer322receives de-mapped physical channel data from first stage310and supplies the de-mapped physical channel data to second stage312. Transport channel buffer304receives encoded transport channel data from second stage312and supplies the encoded transport channel data to third stage314. Output buffer324receives decoded transport channel bits from third stage314and supplies the decoded transport channel bits to DSP24. Each of frame buffer320, intermediate frame buffer322, transport channel buffer304and output buffer324is an independent, separately addressable memory. In some embodiments, these four buffers can be replaced by one larger memory or by another configuration of buffers.

As further shown inFIG. 3, first stage310, second stage312and third stage314each receive parameters and control signals from DSP24. The parameters specify how the data is processed in each of the stages, and the control signals control processing. For example, a control signal from DSP24may notify bit rate processor40that frame buffer320has been filled with data and that processing of the data can begin. As another example, an estimated scaling factor can be adjusted by an empirical parameter. The first and third stages also provide status signals to DSP24, for example to indicate that a processing task has been completed.

Operations associated with bit rate processing are illustrated in the flowchart ofFIG. 4. Block350indicates operations performed by the software in the digital signal processor, and block352indicates operations performed by bit rate processor40in coprocessor22. The DSP24performs rate matching parameter computation and decoding of control channels, and also supplies physical channel data to bit rate processor40. In bit rate processor40, physical channel de-mapping step354and subframe de-segmentation step355are performed by first stage310. The second de-interleaving, or CCTrCH de-interleaving step356, physical channel de-segmentation step357, soft decisions descrambling step358, transport channel demultiplexing step360, de-rate matching step362, radio frame concatenation step364and transport channel de-interleaving/de-equalization step366, are performed by second stage312. Channel decoding step370, code block concatenation step372and CRC checking step374are performed by third stage314. Thus, second stage312and third stage314each perform more than one operation of the bit rate processing. As shown, the data is split up into transport channels in transport channel demultiplexing step360.

An implementation of bit rate processor40is shown inFIG. 5. As shown, first stage310includes a physical channel de-mapping engine400. Second stage312includes a second de-interleaver410, a descrambler412, a de-rate matching engine414, and a first de-interleaver416. Third stage314includes a scaling circuit420, a turbo decoder422, a viterbi decoder424, a multiplexer426and a CRC checker428. Third stage314may perform turbo decoding, viterbi decoding, or no decoding. Parameters and control signals are provided to bit rate processor40via ECP bus30and ECPI slave interface34.

First stage310of the bit rate processor includes the de-mapping engine400in the embodiment ofFIG. 5. The de-mapping engine400reads physical channel data from the frame buffer320and writes de-mapped physical channel data to the intermediate frame buffer322. A dedicated frame buffer320, which is not used for storage of other data, reduces constraints placed on the DSP24. By placing the intermediate frame buffer322immediately after the de-mapping engine400, the frame buffer320can be emptied very early in the bit rate processing operation. Using a “frame buffer empty” interrupt, DSP24can overlap the loading of the frame buffer with the bit rate processing of a previous frame. This provides DSP24with flexibility to manage system bus bandwidths and frame throughputs. The frame buffer320is divided into areas for storing two subframes. The base address of each subframe is independent of frame content. By using concurrent de-mapping engines, the subframes can be simultaneously de-mapped and the subframe concatenation task can be absorbed without any penalty.

Second stage312of the bit rate processor performs several operations of the receiver chain. By using a streaming interface between tasks rather than dedicated memories for each of the tasks, substantial memory space is saved. The TDSCDMA standard specifies the size of the transport time interval (TTI) memory at the input of de-rate matching as 6.6 times the output data rate. This would place the TTI memory at the input of the de-rate matching engine. By positioning the de-rate matching engine414in the second stage312, more than fifty percent in memory space is saved. By placing the transport channel de-interleaver at the input of the transport channel buffer304and using a wider transport channel buffer memory with byte selects, the transport channel de-interleaver implementation is simplified as compared to an address lookup function at the output.

Third stage314of the bit rate processor includes the decoder, which performs the most computationally complex task in the bit rate processor. By isolating this task in the third stage314, the DSP24has the flexibility to bypass the tasks prior to the decoder. By placing the transport channel buffer304under control of DSP24, DSP24can control the decoding channels and their sequence or can decide not to activate decoding at all if channel decoding is not required for a particular frame.

By using output buffer324with two banks, the bit rate processor can hold the results of two frames of output data. The DSP thus has10ms more time to read the outputs. This helps the DSP24to manage system bus bandwidth more efficiently.

The architecture of the bit rate processor shown inFIG. 3facilitates the use of stage triggers and other special modes that provide flexibility to the DSP24. Every stage in the bit rate processor has an associated trigger register. Advantages of using the trigger register include giving the DSP24scheduling control over the stages of the bit rate processor, building a pause function around the stage triggers to halt the bit rate processor and read memory contents for debug, and the ability to bypass the third stage when decoding is not required. Since the decoder is computationally the most intensive, there may be applications where the DSP can perform the tasks associated with first stage310and second stage312and use only third stage314. The DSP loads the transport channel buffer304to achieve this operation. This situation may arise when certain application-specific requirements render the earlier stages irrelevant or the DSP24decides to use a different algorithm for one or more of the earlier tasks.

Frame Buffer

The inputs to bit rate processor40from joint detection operations are illustrated in the schematic diagram ofFIG. 6. Subframes450and452each have time slots454,456and458with downlink data. Additional time slots of each subframe may be used for uplink data or may be unused. In one embodiment, each subframe may include up to five downlink time slots. The joint detector42processes received data on a time slot basis. InFIG. 6, JD blocks460represent all joint detection operations, including channel estimation, processing performed by joint detector42and joint detection post processing by DSP24. The result of the joint detection operations is a set of physical channel data, in the form of soft decisions, for a selected user equipment (UE). In one embodiment, each soft decision is one byte. The JD operations are completed for each time slot of each subframe, and the soft decisions for each time slot are written to frame buffer320as they are completed. In the current embodiment, only soft decisions corresponding to data, and no control bits, are written to frame buffer320. The control information, including TFCI (Transport Format Combination Indicator), TPC (Transport Power Control) and SS (Synchronization Shift), can be removed by DSP24and processed as necessary.

The active code detection (ACD) which is part of joint detection may determine which codes among the potential active codes are indeed active. However, this mechanism may not be entirely reliable and can detect an inactive code as active and vice-versa. Only the decoded TFCI tells which user equipment codes were indeed present. The TFCI may not be available until after the last downlink time slot of the second subframe452. Therefore when soft decisions are transferred to bit rate processor40on a time slot basis, the bit rate processor supports the following cases: (1) the bit rate processor may have to discard some of the already received data which were mapped on a code determined by the ACD to be active but which is not active; (2) the bit rate processor may have to pad other data with zeros in the case where the ACD has incorrectly discarded one of the codes of the user equipment; and (3) all data received on a burst basis are kept when, in all time slots of the frame, all user equipment data and only user equipment data has been transferred to bit rate processor40.

An example of the format of inputs to frame buffer320from DSP24is shown inFIG. 7. A time slot470has a spreading factor of 16, and a time slot472as a spreading factor of one. In time slot470, the data for up to 16 physical channels appears in ascending order with respect to the physical channel number. The size of the data per spreading factor is fixed at 88 bytes in this example. In time slot470, a first physical channel has two soft decisions, and a second physical channel has three soft decisions. Dummy data is inserted as necessary to reach 88 bytes for each physical channel. It will be understood that an actual operating example is likely to have more soft decisions in each physical channel. Time slot472has a single spreading code and a data size of 1408 bytes. Dummy data may be inserted to reach 1408 bytes.

The current embodiment of the bit rate processor supports up to five time slots and up to 66 physical channels. The bit rate processor further supports any distribution of physical channels across the time slots.

An example of an organization of frame buffer320is shown schematically inFIG. 7A. Blocks480,482, etc., each having a size of 88 bytes for holding 88 soft decisions are allocated. Thus, new physical channels begin on 88 byte boundaries in the frame buffer320. In the example ofFIG. 7A, frame buffer320supports up to 66 physical channels. Areas484make contain dummy data when the corresponding physical channel contains less than 88 bytes.

Physical Channel De-Mapping Engine

Physical channel de-mapping is performed for every coded composite transport channel (CCTrCH) in a radio frame. In one embodiment, there can be up to four coded composite transport channels in every 10 ms radio frame. The physical channel de-mapping engine reads soft decisions which have been sent from the joint detector post processing module to the frame buffer320. The de-mapped soft decisions are output to the intermediate frame buffer322.

The physical channel de-mapping operation is illustrated schematically inFIG. 8. A rule for physical channel de-mapping is that a physical channel contains one and only one coded composite transport channel. Odd-numbered physical channels490are filled in a forward order, and even-numbered physical channels492are filled in a reverse order. In one embodiment, the physical channel de-mapping removes unuseful data (physical channels which are determined not to be directed to the user equipment after decoding the TFCI) and pads with zeros the physical channels which have been discarded by the joint detector but which belong to the user equipment. The quantity Utpshown inFIG. 8represents the number of soft decisions in time slot t and physical channel p (excluding control bits). The number of possible values for Utpdepends on the time slot format utilized. In the TDSCDMA protocol, spreading factors of 1 and 16 may be utilized. For a spreading factor of 16, the maximum value of Utpis 88, and for a spreading factor of 1 the maximum value of Utpis 1408 (88×16).

The parameters for physical channel de-mapping include: (1) for each time slot and each channelization code, the start address of the input soft decisions; (2) for each coded composite transport channel and each time slot, the number of channelization codes and a list of the channelization codes; and (3) for each time slot t and physical channel p, the value of Utp, the number of soft decisions.

A block diagram of physical channel de-mapping engine400is shown inFIG. 9. As shown inFIG. 9, de-mapping engine400includes a frame buffer descriptor memory500and a de-map block502. A state machine diagram of de-mapping engine400is shown inFIG. 10. The de-mapping engine400has two main functional components. A frame buffer descriptor read state machine510controls reads of a frame buffer descriptor memory500and configures the physical channel information for each CCTrCH in every time slot. The state machine510cycles through each CCTrCH across all time slots. In this way, soft decisions are written into the intermediate frame buffer322in subsequent buffer locations. In the process of reading the descriptor memory500, the state machine510also generates size information per slot and per CCTrCH that is passed to the second de-interleaver410to generate de-interleaving matrix information.

A de-map state machine512uses the physical channel information generated by frame buffer descriptor read state machine510and performs the de-mapping operation. It cycles through each physical channel, incrementing or decrementing frame buffer pointers depending on the channel number. The de-map state machine512de-maps subframe1followed by subframe2and thus also achieves subframe desegmentation.

Intermediate Frame Buffer

The intermediate frame buffer322receives de-mapped physical channel data from de-mapping engine400. The intermediate frame buffer322may have the same size as frame buffer320. As noted above, by placing the intermediate frame buffer322after de-mapping engine400, the frame buffer320can be emptied very early in the bit rate processing operation.

A block diagram of second de-interleaver410is shown inFIG. 11. A state machine diagram of second de-interleaver410is shown inFIG. 12. The second de-interleaver410is configured to perform frame-based de-interleaving520or slot-based de-interleaving522, as instructed by DSP24. In each case, the second de-interleaver410operates on a single CCTrCH at a time.

The frame-based second de-interleaving520is performed for every CCTrCH in a radio frame. In the current embodiment, there can be up to four CCTrCHs in each10ms radio frame. The frame-based de-interleaver reads soft decisions from the intermediate frame buffer322, and inputs the de-interleaved soft decisions to the physical channel concatenation. The de-interleaving formula, as set forth in the TDSCDMA specification, generally involves writing the input bit sequence into a matrix, performing intercolumn permutation of the matrix, and reading a bit sequence out of the matrix after permutation.

The slot-based de-interleaving522is performed for every CCTrCH in a radio frame per time slot, where a time slot is over the two subframes of the radio frame. The slot-based de-interleaver is executed the maximum number of time slots times the maximum number of CCTrCHs every 10 ms radio frame. The slot-based de-interleaver reads soft decisions from the intermediate frame buffer322and inputs the de-interleaved soft decisions to the physical channel concatenation. The slot-based de-interleaver formula is similar to the frame-based de-interleaver formula, but is executed more times per radio frame.

De-interleaver parameters include: (1) de-interleaver mode (frame-based or slot-based); (2) for the slot-based de-interleaver, the number of soft decisions in time slot t on physical channels belonging to CCTrCH n; (3) for the frame-based de-interleaver, the number of soft decisions belonging to CCTrCH n in the current radio frame; and (4) the start address of the de-mapped buffer for CCTrCH n.

The second de-interleaver410has two main computational blocks and one state machine to control the de-interleaver logic. Slot size and frame size generation logic includes a simple adder logic to generate frame size information using slot size information from the de-mapping engine400. Slot size information from the de-mapping engine400is used for slot-based de-interleaving. Matrix information logic involves the generation of row, remainder and column offset information based on the de-interleaving size.

Physical channel concatenation is performed for every CCTrCH in a radio frame. In the encoding chain, the physical channel segmentation separates the input bit sequence into time slots for the slot-based second interleaver. The inverse process, the physical channel concatenation, simply consists of writing the slot-based de-interleaved data so that the time slots appear consecutively in ascending order with respect to the time slot number. In practice, the slot-based de-interleaver can process each time slot starting from the first, then the second, etc. and write the outputs of each time slot consecutively. This process achieves physical channel concatenation.

A block diagram of descrambler412is shown inFIG. 13. Bit descrambling in descrambler412is performed for every CCTrCH in a radio frame. The process of scrambling bit j includes performing an exclusive OR with a polynomial element p[j] equal to 1 or 0. The bit is unchanged if p[j] is 0 and is negated if p[j] is 1. The bit descrambling process is applied to soft decisions. The soft decision descrambler is a 16-bit polynomial implementation with a feedback loop. As shown inFIG. 13, descrambler412may be implemented as a 16-stage linear feedback shift register530. The zero degree coefficient output by first stage532is applied to a data selector534used to determine if the soft decision is to be negated. Negation is a two's complement negation. The register is reset to 0x0001 at the start of a new CCTrCH every frame. The polynomial content is the same for all CCTrCHs of a particular length.

CCTrCH demultiplexing is performed for every CCTrCH in a radio frame. For a given CCTrCH, after the second de-interleaver for a radio frame, V1consecutive data belong to transport channel no. 1, V2consecutive data belong to transport channel no. 2, etc. In practice, CCTrCH demultiplexing is a convention between the descrambler412and the de-rate matching engine414. The demultiplexing itself is implicit.

Rate matching at the transmitter involves puncturing or repetition of bits so that the bit rate after rate matching exactly matches channel capacity. The inverse rate matching is performed in the downlink receiver, so that the bit rate after de-rate matching matches the input rate to the channel decoder. Inverse rate matching includes the following operations: (1) zero insertion in place of punctured bits; and (2) maximum likelihood combining of repeated bits. The implementation of rate matching involves two steps. The first is rate matching parameter calculation. Rate matching parameters are calculated after decoding the TFCI. The TFCI contains information about the number of transport channels and the data rate of each transport channel active during that radio frame. The transport channel parameters are used to calculate rate matching parameters. The second step is implementation of the rate matching algorithm. The rate matching algorithm is reasonably straightforward, after the rate matching parameters are determined. De-rate matching is performed on a frame-by-frame basis. If a transport channel spans multiple radio frames, the part of the transport channel belonging to each frame can have different rate matching parameters.

The de-rate matching engine414, shown inFIGS. 14-19, includes de-rate descriptor manager logic that reads a descriptor memory540(FIG. 14) and configures the de-rate matching engines. A state machine diagram of the descriptor manager logic is shown inFIG. 15. A state machine544controls operation of descriptor memory540. The de-rate matching engine414further includes select logic550(FIG. 16) that selects between three de-rate matching engines (FIG. 17), including: (1) bypass560for non-rate matched and systematic bits of turbo encoded data with puncturing; (2) engine562used for transport channel with repetition or puncturing; and (3) engine564used only for the second parity stream in the case of turbo encoded data with puncturing. An input FIFO542(FIG. 14) controls data flow coming from the second de-interleaver/descrambler. A transport channel buffer interface570(FIG. 18) gathers bytes from the de-rate matching engine and writes up to 8 bytes at a time into the transport channel buffer304. The transport channel buffer interface570also performs transport channel de-interleaving. A frame scaling factor estimation block580(FIG. 19), in this embodiment, sums the magnitude of all soft decisions and the total count of soft decisions per transport channel and passes the information to the scaling block in the back end processor302. This information is needed for scaling factor estimation for the complete transport time interval.

Transport Channel De-Interleaver

Transport channel de-interleaving is block de-interleaving with intercolumn permutation. The operation of the first de-interleaver416, or transport channel de-interleaver, involves writing data values into a matrix row wise, reordering columns of the matrix using a predefined permutation pattern and then reading data values column by column, starting with the first column.

Transport Channel Buffer

The transport channel buffer304is used for holding up to a transport time interval (TTI) of soft decisions of all active transport channels. Since the maximum TTI duration is 80 ms, the transport channel buffer304may hold up to 8 frames of soft decisions in some cases. In one embodiment, the memory organization of transport channel buffer304is under control of DSP24. In other embodiments, the organization of transport channel buffer304may be implemented in hardware.

The alignment of transport channels multiplexed into one CCTrCH is shown inFIG. 20A. Transport channels multiplexed into one CCTrCH have coordinated frame timing. As shown inFIG. 20A, a transport channel600has a TTI of 10 ms, a transport channel602has a TTI of 20 ms, a transport channel604has a TTI of 40 ms, and a transport channel608has a TTI of 80 ms. Transport channels600,602,604and608begin transmission at the same time.

In the case of multiple CCTrCHs, the frame start timing may or may not be aligned.FIG. 20Bshows an example of two CCTrCHs where the start timing of CCTrCH620and CCTrCH622differ by 20 ms.FIG. 20Cshows an example of two CCTrCHs where the start timing of CCTrCH630and CCTrCH632are the same.

The transport channel buffer memory organization for a group of CCTrCHs having two distinct frame timings can be viewed as two software stacks progressing from the two ends of the buffer (top and bottom). All transport channels belonging to CCTrCHs having the first distinct frame timing are organized from one end (the top) starting with transport channels having the longest duration TTI. Transport blocks smaller TTIs are then stored sequentially, as shown inFIGS. 21A and 21B. For example, transport channels having 80 ms TTIs are stored first at the top of the buffer, transport channels having 40 ms TTIs are stored second, transport channels having 20 ms TTIs are stored third, and transport channels having 10 ms TTIs are stored last. All transport channels belonging to CCTrCHs having the second distinct frame timings are organized from the other end (the bottom) starting with the transport channel having the longest duration TTI. The transport channels having smaller TTIs are then stored sequentially in the backward direction toward the top of the buffer. All transport channels belonging to a third fixed length CCTrCH are placed either at the top or the bottom of the transport channel buffer.

In the case of TDSCDMA systems, all dedicated CCTrCHs have a common frame timing and all common CCTrCHs have a common frame timing, which may be different from the dedicated CCTrCHs. So all dedicated transport channels can be organized from the top of the transport channel buffer, and all common transport channels can be organized from the bottom of the transport channel, as shown inFIG. 21B.

In the case of WCDMA systems, there are two variable length CCTrCHs. A first CCTrCH634may be organized from the top of the transport channel buffer and a second CCTrCH636may be organized from the bottom of the transport channel buffer, as shown inFIG. 21A. A third fixed length CCTrCH638is located in a fixed position, as shown inFIG. 21A. The fixed position may be at the top or the bottom of the transport channel buffer.

The transport channel buffer allocated for each transport channel is fixed for the duration of the TTI. For example, for a transport channel with 80 ms TTI, the buffer for eight frames is allocated during the first frame. The buffer allocated for this transport channel remains fixed for eight frames. After the TTI is completed, a new buffer size may be allocated depending on the transport channel size in the next TTI.

In the case of WCDMA systems, the TTI duration for a transport channel is a static parameter and remains fixed. For TDSCDMA systems, the TTI duration for a transport channel can change from frame to frame. The transport channel buffer304may be utilized for both cases.

An example is described with reference toFIGS. 20B and 21B. Transport channel4(80 ms TTI) of CCTrCH620inFIG. 20Bmay be allocated to area640at the top of transport channel buffer304, transport channel3(40 ms TTI) of CCTrCH620may be allocated to area642of transport channel buffer304, transport channel2(20 ms TTI) of CCTrCH620may be allocated to area644of transport channel buffer304, and transport channel1(10 ms TTI) of CCTrCH620may be allocated to area646of transport channel buffer304. Transport channel3of CCTrCH622inFIG. 20Bmay be allocated to area650in transport channel buffer304, transport channel2of CCTrCH622may be allocated to area652in transport channel buffer304, and transport channel1of CCTrCH622may be allocated to area656in transport channel buffer304. In this example, CCTrCH622does not have a transport channel of TTI 20 ms, and area656immediately follows area652.

In the foregoing example, CCTrCH620is allocated beginning at the top of transport channel buffer304and progressing toward the bottom of transport channel buffer304. The second CCTrCH622is allocated at a second address at or near the bottom of the transport channel buffer304and progressing toward the top of transport channel buffer304. Each buffer allocation is configured to store transport channels having the longest duration in TTI followed by transport channel data having successively shorter duration TTIs.

Transport Channel Buffer Manager

A block diagram of the back end processor302is shown inFIG. 22, with the exception that output buffer324is not shown. The transport channel buffer manager700controls the configuration of the back end blocks by reading a transport channel descriptor memory702and programming the turbo decoder422, the viterbi coder424, the scaling circuit420and the CRC checker428. The transport channel buffer manager700also contains computational elements to calculate code block size and number of code blocks. The transport channel decoding proceeds in increasing order of transport channel number. The transport channel buffer manager operates according to a transport channel buffer manager state machine710shown inFIG. 23.

Scaling Circuit

Scaling in the bit rate processor involves quantizing the soft decisions to 4 bits at the input of the channel decoder. All bit rate processing excluding channel decoders uses 8 bit input and output data. The scaling algorithm quantizes the soft decisions so that the input to the channel decoder can be represented using 4 bits. The scaling algorithm is implemented by scaling circuit420in third stage314and by a scaling factor estimation block in de-rate matching engine414of second stage312.

The channel decoders are the most computationally intense of elements in the bit rate processor. Thus, it is desirable to optimize the bit width of the channel decoder. Performance simulations show that both viterbi and turbo decoders perform well, even when soft decisions are quantized to 4 bits at the input.

The scaling operation includes two basic steps. The first is scaling factor estimation. The scaling factor is estimated based on the probability distribution of the signal amplitude or the effective value of the signal amplitude. In one embodiment, the scaling factor is a measure of the average amplitude of the soft decisions of the block. The scaling factor for each transport channel is determined on-the-fly as the de-rate matching engine414outputs rate-matched soft decisions and stores them in the transport channel buffer304. The second operation is soft decision scaling. Scaling involves selecting the correct 4-bit field from the 8-bit soft decision in this embodiment.

The scaling factor can be estimated in a variety of ways. The soft decisions belonging to a code block should have the same scaling factor. Scaling factor estimation can have three levels of granularity as follows.

1. The scaling factor can be estimated on a code block basis. The scaling factor is estimated based on the average of the absolute values of all soft decisions in a code block. If a transport channel includes two code blocks, each code block can have its own scaling factor.

2. The scaling factor can be estimated on a transport channel basis. The scaling factor is estimated based on the average of the absolute values of the soft decisions in the transport channel. If the transport channel includes only one code block, then the scaling factor is the same as estimated on a code block basis. If the transport channel includes more than one code block, all code blocks have the same scaling factor.

3. The scaling factor is estimated on a CCTrCH basis. The scaling factor is estimated based on the average of the absolute values of the soft decisions belonging to a CCTrCH. All channels having the same TTI duration have the same scaling factor. For example, if there are 10 transport channels and all have a 10 ms TTI duration, all transport channels have the same scaling factor.

The scaling algorithm is illustrated schematically inFIG. 25. A soft decision is scaled according to scaling factor S by selecting four bits starting with bit position S.

The scaling circuit420is illustrated inFIG. 24. The scaling circuit420includes a scaling factor estimation circuit720that determines a scaling factor based on the values determined by the circuit shown inFIG. 19and a soft decision scaling circuit722which applies the scaling factor to the soft decisions supplied to the decoders. The portion of the scaling factor estimation block located in de-rate matching engine414is illustrated inFIG. 19. In another embodiment, the scaling factor is supplied to the bit rate processor by the DSP24.

Decoder

As indicated above, the channel decoder includes turbo decoder422, viterbi decoder424and the option of no decoding. The turbo decoder422, shown inFIG. 26, may utilize a conventional turbo decoding circuit. Turbo configuration registers may be external to turbo decoder422and the parameters are supplied as signals to the turbo decoder. Similarly, viterbi decoder424, shown inFIG. 27, may utilize a conventional viterbi decoding circuit. Viterbi configuration registers may be external to viterbi decoder424, with parameters supplied to the viterbi decoder as signals. In the case of no decoding, the decoders422and424are simply bypassed.

CRC Checker

The CRC checker428may be a LFSR (linear feedback shift register) implementation of the CRC polynomial. The data component of the input stream, followed by zeros of CRC length size, is shifted into the LFSR to generate the expected CRC. The actual CRC is compared to the expected CRC to generate pass/fail information.

Output Buffer

An output buffer manager, shown inFIGS. 28 and 29, controls, reads and writes to the output buffer324.FIG. 28shows output buffer write logic740, andFIG. 29shows output buffer read logic742. The output buffer324includes two banks of memory to store two frames of decoded data plus CRC status. An internal bank select logic ping-pongs between the two buffers for read and write. The output buffer324can be read either by the DSP directly or through the coprocessor DMA.