Liquid crystal display panel

First and second gate lines respectively extend in first and second directions in a display area. The second gate line is electrically connected to the first gate line and extends in the second direction in the display area. The second gate line is electrically connected to the first gate line outside the display area. A conductive layer may be disposed between the second gate line and a source line, and the second gate line may be electrically connected to the first gate line in the display area. To the conductive layer, a potential identical to a common potential or a ground potential is applied. An arrangement where two or more second gate lines overlap the source line may be employed. Transition of a potential of a gate signal from an on potential to an off potential may be made in two or more stages.

BACKGROUND OF THE INVENTION

Field of the Invention

Description of the Background Art

In the past, cathode ray tube display devices were widely used, but at present, new display devices in place of the cathode ray tube display devices have been widely used. Many of such new display devices are provided with lightweight, flat display panels and accordingly have a feature of being lightweight and thin.

Examples of such new display devices include a liquid crystal display device, an electroluminescent display device, and the like. The liquid crystal display device displays an image using physical properties of liquid crystals. The electroluminescent display device displays an image using the principle of electroluminescence. The liquid crystal display device, a typical example of the new display device, has a feature of being low-voltage driven in addition to the feature of being lightweight and thin.

The liquid crystal display device includes an array substrate, a liquid crystal layer, and a counter substrate. The array substrate and the counter substrate face each other with the liquid crystal layer interposed therebetween. The array substrate includes a plurality of pixels. The plurality of pixels are arranged in a matrix to define a display area in which an image is displayed.

Examples of the liquid crystal display device include a thin film transistor (TFT) liquid crystal display device. In such a TFT liquid crystal display device, each pixel includes a TFT serving as a switching element, and holds a voltage for driving a liquid crystal layer independently from other pixels. Accordingly, the TFT liquid crystal display device has a feature of being capable of displaying a high-quality image without large crosstalk.

The TFT liquid crystal display device has a large number of gate lines and a large number of source lines. The gate lines are also referred to scan lines and transmit a gate signal to the TFT. The source lines are also referred to as signal lines and transmit a source signal to the TFT. Switching control of the TFT between an on state and an off state is performed in accordance with the gate signal. Image data is supplied to the TFT through the source signal. Each pixel is usually disposed in a region surrounded by two adjacent gate lines and two adjacent source lines.

Recently, a fringe field switching (FFS) mode that can realize a TFT liquid crystal display device having excellent viewing angle characteristics and high light transmittance has been proposed. The following description will be given by taking the FFS mode as an example.

In an FFS liquid crystal display device, when an image is displayed, a fringe electric field constituted by an oblique electric field having both transverse and longitudinal electric field components is applied to a liquid crystal layer. In the FFS liquid crystal display device, in order to apply the fringe electric field to the liquid crystal layer, the array substrate includes a pixel electrode, a common electrode, and an insulating film. The pixel electrode and the common electrode face each other with the insulating film interposed therebetween, and are disposed apart from each other in the thickness direction of the array substrate. In general, a lower layer electrode disposed below the insulating film has a plate-like shape, and an upper layer electrode disposed above the insulating film includes a plurality of gaps. Each of the gaps has a slit. The plurality of gaps overlap the upper layer electrode in plan view in the thickness direction of the array substrate. The lower electrode may have a plurality of rod-shaped bodies. In the FFS liquid crystal display device, orientations of liquid crystal molecules contained in the liquid crystal layer are controlled by an electric field from the lower layer electrode to the upper layer electrode through the slit. In the FFS liquid crystal display device, the pixel electrode and the common electrode are each made of a transparent conductive film to become a transparent pixel electrode and a transparent common electrode, respectively, which makes it possible to achieve high light transmittance.

Such an FFS liquid crystal display device having excellent viewing angle characteristics and high light transmittance is used in various applications. Therefore, for the FFS liquid crystal display device, great importance has been attached to product design, and narrowing the frame area around the display area has been strongly required.

On the other hand, the gate line and the source line are disposed in the display area and are orthogonal to each other in the display area. Further, the array substrate has, around the display area, an area where a driver integrated circuit (IC) that outputs the gate signal and the source signal is mounted, and an area where routing lines that respectively transmit the gate signal and the source signal output from the driver IC to the gate line and the source line are formed. Accordingly, the array substrate has an area where the driver IC is mounted along at least two of the four sides surrounding the display area. Therefore, in the FFS liquid crystal display device, it is difficult to narrow the frame area defined along three of the four sides surrounding the display area.

Therefore, proposed is a technique to dispose a routing line that extends in a direction parallel to a direction in which the source line extends and transmits the gate signal to the gate line in the display area and define the area where the driver IC is mounted along only one of the four sides surrounding the display area, thereby narrowing the frame area defined along three sides other than the one side. The technology described in WO 2014/155458 A is an example of the proposal.

However, when the routing line that transmits the gate signal to the gate line is disposed in the display area, the routing line is disposed along the source line and capacitively coupled to the source line. This causes a potential of the source signal transmitted through the source line to vary due to the gate signal transmitted through the routing line. For example, when the TFT is switched from the on state to the off state, the potential of the gate signal varies from a high potential to a low potential, so that the potential of the source signal also varies with the variation in the potential of the gate signal.

In a non-selection time in which the pixel electrode is not selected and the source signal is not transmitted to the pixel electrode, display abnormality does not occur even when the potential of the source signal varies. However, in a selection time in which the pixel electrode is selected and the source signal is transmitted to the pixel electrode, when the potential of the source signal varies, the potential of the source signal written to the pixel electrode varies, the pixel potential applied to the pixel electrode varies, and then display abnormality occurs. In particular, in a case where the routing line is electrically connected to the gate line through a through hole, the pixel in the vicinity of the through hole is easily affected by the variation in the potential of the source signal, and accordingly point defect failure occurs in the pixel.

SUMMARY

An object of the present invention is to provide a liquid crystal display panel capable of narrowing a frame area defined along three of four sides surrounding a display area and suppressing display abnormality.

First to fourth aspects of the present invention relate to a liquid crystal display panel.

The liquid crystal display panel includes an array substrate, a liquid crystal layer, and a counter substrate. The counter substrate faces the array substrate with the liquid crystal layer interposed therebetween.

The array substrate includes an insulating substrate, a plurality of first gate lines, a plurality of source lines, a plurality of switching elements, a plurality of transparent pixel electrodes, and a plurality of second gate lines. The plurality of first gate lines, the plurality of source lines, the plurality of switching elements, the plurality of transparent pixel electrodes, and the plurality of second gate lines are disposed above the insulating substrate.

The plurality of first gate lines extend in a first direction parallel to the insulating substrate in a display area where an image is displayed, and respectively transmit a plurality of gate signals.

The plurality of source lines extend in a second direction that is parallel to the insulating substrate and orthogonal to the first direction in the display area, form a plurality of intersections with the plurality of first gate lines in plan view in a thickness direction of the insulating substrate, and respectively transmit a plurality of source signals.

The plurality of switching elements respectively switch source signals transmitted through source lines that form the plurality of intersections in accordance with gate signals transmitted through gate lines that form the plurality of intersections to produce a plurality of pixel potentials.

The plurality of transparent pixel electrodes are disposed in the display area. To the plurality of transparent pixel electrodes, the plurality of pixel potentials are respectively applied.

The plurality of second gate lines extend in the second direction in the display, area, and are disposed at positions different from positions where the plurality of first gate lines are disposed in the thickness direction of the insulating substrate. The plurality of second gate lines are electrically connected to the plurality of first gate lines respectively and respectively transmit the plurality of gate signals to the plurality of first gate lines.

In the first aspect of the present invention, the array substrate further includes a common electrode. The common electrode produces electric fields in response to the plurality of pixel potentials respectively between the plurality of transparent pixel electrodes and the common electrode. Further, the plurality of second gate lines are electrically connected to the plurality of first gate lines outside the display area respectively.

The plurality of gate signals and the plurality of source signals can be supplied from one side in the second direction when viewed from the display area. Further, it is possible to prevent the plurality of second gate lines from being disposed on one side in the first direction, the other side in the first direction, and the other side in the second direction when viewed from the display area. This in turn makes it possible to narrow the frame area defined along three of the four sides surrounding the display area.

Further, the electrical connection of the second gate line to the first gate line that makes an influence of the gate signal on the source signal significant is made outside the display area. This in turn makes it possible to suppress display abnormality.

In the second aspect of the present invention, the plurality of second gate lines are electrically connected to the plurality of first gate lines in the display area respectively. The array substrate further includes a transparent common electrode and a plurality of conductive layers. The transparent common electrode is disposed above the insulating substrate, and produces fringe electric fields in response to the plurality of pixel potentials respectively between the plurality of transparent pixel electrodes and the transparent common electrode. The plurality of conductive layers are respectively disposed between the plurality of source lines and the plurality of second gate lines. To the plurality of conductive layers, a potential identical to a common potential applied to the transparent common electrode or a ground potential is applied.

The plurality of gate signals and the plurality of source signals can be supplied from one side in the second direction when viewed from the display area. Further, it is possible to prevent the plurality of second gate lines from being disposed on one side in the first direction, the other side in the first direction, and the other side in the second direction when viewed from the display area. This in turn makes it possible to narrow the frame area defined along three of the four sides surrounding the display area.

Further, stray capacitances produced between the plurality of source lines and the plurality of second gate lines are reduced, making it possible to suppress the influence of the gate signals on the source signals. This in turn makes it possible to suppress display abnormality.

In the third aspect of the present invention, the array substrate further includes a common electrode. The common electrode produces electric fields in response to plurality of pixel potentials respectively between the plurality of transparent pixel electrodes and the common electrode. Further, the plurality of second gate lines have an arrangement where two or more second gates lines overlap each of the plurality of source lines in the display area in plan view in the thickness direction of the insulating substrate.

The plurality of gate signals and the plurality of source signals can be supplied from one side in the second direction when viewed from the display area. Further, it is possible to prevent the plurality of second gate lines from being disposed on one side in the first direction, the other side in the first direction, and the other side in the second direction when viewed from the display area. This in turn makes it possible to narrow the frame area defined along three of the four sides surrounding the display area.

Two or more second gate lines are capacitively coupled to one source line to make the stray capacitance produced between one second gate line and one source line small, making it possible to suppress the influence of the gate signal on the source signal. This in turn makes it possible to suppress display abnormality.

In the fourth aspect of the present invention, the liquid crystal display panel further includes a gate signal source. The gate signal source outputs the plurality of gate signals and makes transition of a potential of each of the plurality of gate signals from an on potential to an off potential in two or more stages.

The plurality of gate signals and the plurality of source signals can be supplied from one side in the second direction when viewed from the display area. Further, it is possible to prevent the plurality of second gate lines from being disposed on one side in the first direction, the other side in the first direction, and the other side in the second direction when viewed from the display area. This in turn makes it possible to narrow the frame area defined along three of the four sides surrounding the display area.

The transition of the gate signal from the on potential to the off potential is made slowly, making it possible to suppress the influence of the gate signal on the source signal. This in turn makes it possible to suppress display abnormality.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

1 First Preferred Embodiment

1.1 Cross-Sectional Structure of Liquid Crystal Display Device

FIG. 1is a cross-sectional view schematically showing a liquid crystal display device including a liquid crystal display panel of the first preferred embodiment.

A liquid crystal display device1000illustrated inFIG. 1includes a liquid crystal display panel1020and a backlight1022. The liquid crystal display device1000may include components other than these components.

The liquid crystal display device1000is a transmissive liquid crystal display device. The following technology may be applied to a reflective or semi-transmissive liquid crystal display device.

The backlight1022emits light and causes the light thus emitted to impinge on a main surface1040on a back side of the liquid crystal display panel1020.

The liquid crystal display panel1020transmits the light that has impinged on the main surface1040on the back side of the liquid crystal display panel1020, and causes the light thus transmitted to exit from a main surface1042on a display surface side of the liquid crystal display panel1020. When transmitting the light, the liquid crystal display panel1020controls a pixel potential applied to each pixel in accordance with an electric signal input to the liquid crystal display panel1020to control light transmittance of each pixel in accordance with the pixel potential applied to each pixel.

This causes an image corresponding to the electric signal input to the liquid crystal display panel1020to be displayed on the main surface1042on the display surface side of the liquid crystal display panel1020.

1.2 Cross-Sectional Structure of Liquid Crystal Display Panel

The liquid crystal display panel1020illustrated inFIG. 1is a liquid crystal display panel of a fringe field switching (FFS) type.

The liquid crystal display panel1020includes, as illustrated inFIG. 1, a first polarizing plate1060, a liquid crystal cell1062, and a second polarizing plate1064. The liquid crystal display panel1020may include components other than these components.

The first polarizing plate1060selectively transmits light having a first polarization direction contained in the light that has impinged on the main surface1040on the back side of the liquid crystal display panel1020and causes the light thus transmitted to impinge on a main surface1080on a back side of the liquid crystal cell1062.

The liquid crystal cell1062transmits the light that has impinged on the main surface1080on the back side of the liquid crystal cell1062and causes the light thus transmitted to exit from a main surface1082on a display surface side of the liquid crystal cell1062. When transmitting light, the liquid crystal cell1062controls an amount of change in polarization direction in each pixel in accordance with the pixel potential applied to the pixel.

The second polarizing plate1064selectively transmits light having a second polarization direction contained in the light that has exited from the main surface1082on the display surface side of the liquid crystal cell1062and causes the light thus transmitted to exit from the main surface1042on the display surface side of the liquid crystal display panel1020.

This causes the light transmittance of each pixel to be controlled in accordance with the pixel potential applied to the pixel.

1.3 Cross-Sectional Structure of Liquid Crystal Cell

The liquid crystal cell1062includes, as illustrated inFIG. 1, an array substrate1100, a liquid crystal layer1102, and a counter substrate1104. The liquid crystal cell1062may include components other than these components.

The counter substrate1104faces the array substrate1100with the liquid crystal layer1102interposed therebetween. The liquid crystal layer1102is sealed in between the array substrate1100and the counter substrate1104. A color filter may be formed on the counter substrate1104.

The liquid crystal cell1062controls an electric field applied to the liquid crystal layer1102in each pixel in accordance with the pixel potential applied to the pixel, controls orientations of liquid crystal molecules contained in the liquid crystal layer1102in the pixel in accordance with the electric field thus applied to control the amount of change in polarization direction in the pixel using the orientations of liquid crystal molecules. This causes the amount of change in polarization direction in each pixel to be controlled in accordance with the pixel potential applied to the pixel.

1.4 Planar Structure of Array Substrate

FIG. 2is a plan view schematically showing the liquid crystal display panel of the first preferred embodiment.

As illustrated inFIG. 2, the liquid crystal display panel1020includes the array substrate1100described above, and further includes a circuit board1120and a flexible circuit board1122.

The liquid crystal display panel1020has a peculiar planar shape. The liquid crystal display panel1020may have a rectangular planar shape.

The liquid crystal display panel1020has a display area1140where an image is displayed. The liquid crystal display panel1020further has a frame area1142defined along three of four sides surrounding the display area1140.

A first direction D1is a horizontal direction parallel to the insulating substrate1160. A second direction D2is a vertical direction parallel to the insulating substrate1160. Therefore, the second direction D2is orthogonal to the first direction D1.

The plurality of first gate lines1162, the plurality of source lines1164, the plurality of second gate lines1166, the plurality of contact parts1168, the gate driver IC1170, and the source driver IC1172are disposed above the insulating substrate1160.

Main portions of the plurality of first gate lines1162are disposed in the display area1140. The plurality of first gate lines1162extend in the first direction D1in the display area1140and are arranged in the second direction D2.

Main portions of the plurality of source lines1164are disposed in the display area1140. The plurality of source lines1164extend in the second direction D2in the display area1140and are arranged in the first direction D1. This causes the plurality of source lines1164and the plurality of first gate lines1162to form a plurality of intersections1200in plan view in a thickness direction of the insulating substrate1160.

Main portions of the Plurality of second gate lines1166are disposed in the display area1140. The plurality of second gate lines1166extend in the second direction D2in the display area1140and are arranged in the first direction D1. The plurality of second gate lines1166are electrically connected to the plurality of first gate lines1162through the plurality of contact parts1168respectively. The plurality of contact parts1168are disposed outside the display area1140. This causes the plurality of second gate lines1166to be electrically connected to the plurality of first gate lines1162outside the display area1140respectively.

The gate driver IC1170is a gate signal source that outputs a plurality of gate signals. The plurality of second gate lines1166respectively transmit the plurality of gate signals thus output to the plurality of first gate lines1162. The plurality of first gate lines1162respectively transmit the plurality of gate signals thus transmitted.

The source driver IC1172is a source signal source that outputs a plurality of source signals. The plurality of source lines1164respectively transmit the plurality of source signals thus output.

The circuit board1120is electrically connected to the array substrate1100through the flexible circuit board1122.

In the first preferred embodiment, the plurality of gate signals and the plurality, of source signals can be supplied from one side in the second direction D2when viewed from the display area1140. This allows the gate driver IC1170and the source driver IC1172to be disposed only on one side in the second direction D2when viewed from the display area1140. It is also possible to prevent the plurality of second gate lines1166from being disposed on one side in the first direction D1, the other side in the first direction D1, and the other side in the second direction D2when viewed from the display area1140. This in turn makes it possible to narrow the frame area1142defined along three of the four sides surrounding the display area1140.

Further, in the first preferred embodiment, even when a resolution of the liquid crystal display panel1020is increased and accordingly the number of the plurality of first gate lines1162and the number of the plurality of second gate lines1166are increased, the frame area1142can be narrowed.

In the first preferred embodiment, the electrical connection of the second gate line1166to the first gate line1162that increases an influence of the gate signal on the source signal caused by a parasitic capacitance produced between the second gate line1166and the source line1164is made outside the display area1140. This makes it possible to suppress display abnormality and point defect failure.

In the first preferred embodiment, a degree of freedom in the shapes of three of the four sides surrounding the display area1140is increased. This makes it possible to easily design the liquid crystal display panel1020having a peculiar planar shape and high design characteristics.

1.5 Pattern on Array Substrate

FIG. 3is an enlarged plan view schematically illustrating a pattern on the array substrate provided in the liquid crystal display panel of the first preferred embodiment.FIG. 3is an enlarged view of a pattern located in a region R1illustrated in FIG.

The array substrate1100includes, as illustrated inFIG. 3, the plurality of first gate lines1162, the plurality of source lines1164, and the plurality of second gate lines1166described above, and further includes a transparent common electrode1220and a plurality of auxiliary capacitance (CS) lines1222.

The plurality of second gate lines1166extend along the plurality of source lines1164in the display area1140and overlap the plurality of source lines1164in the display area1140in plan view in the thickness direction of the insulating substrate1160.

The transparent common electrode1220is disposed above the insulating substrate1160, and disposed in the display area1140.

The array substrate1100includes a plurality of pixels1240. The plurality of pixels1240contributes to the display of an image, and are arranged in a matrix within the display area1140. Each of the plurality of pixels1240includes a transparent pixel electrode1260and a slit group1280of the transparent common electrode1220. Accordingly, the array substrate1100includes a plurality of the transparent pixel electrodes1260respectively provided in the plurality of pixels1240, and a plurality of the slit groups1280respectively provided in the plurality of pixels1240. The transparent pixel electrode1260provided in each of the plurality of pixels1240is disposed above the insulating substrate1160, and disposed in the display area1140. The slit group1280includes three slits. The slit group1280including three slits may be replaced with a slit group including two or less or four or more slits.

The array substrate1100further includes a plurality of dummy pixels1300. The plurality of dummy pixels1300do not contribute to the display of an image and are disposed outside the display area1140. Each of the plurality of dummy pixels1300includes the transparent pixel electrode1260, and the slit group1280of the transparent common electrode1220, as with each of the plurality of pixels1240. The transparent pixel electrode1260provided in each of the plurality of dummy pixels1300is disposed above the insulating substrate1160outside the display area1140.

The plurality of contact parts1168are provided in the plurality of dummy pixels1300. This causes the plurality of second gate lines1166to be electrically connected to the plurality of first gate lines1162in the plurality of dummy pixels1300respectively.

In the first preferred embodiment, the plurality of second gate lines1166are caused to overlap the plurality of source lines1164that neither transmit light nor overlap the slit group1280. Accordingly, even when the plurality of second gate lines1166are disposed in the display area1140, it is not necessary to reduce the number of slits constituting the slit group1280, and the plurality of second gate lines1166are prevented from causing a decrease in light transmittance and a decrease in display performance.

1.6 Cross-Sectional Structure of Array Substrate

FIG. 4is an enlarged cross-sectional view schematically illustrating the array substrate provided in the liquid crystal display panel of the first preferred embodimentFIG. 4illustrates a cross section taken along a cutting line A-A ofFIG. 3.

The array substrate1100includes, as illustrated inFIG. 4, the insulating substrate1160, the first gate line1162, the source line1164, the second gate line1166, the transparent pixel electrode1260, and the transparent common electrode1220described above, and further includes a gate insulating film1320, a channel layer1322, a source electrode1324, a drain electrode1326, a first interlayer insulating film1328, and a second interlayer insulating film1330. The first gate line1162includes a counter part1360. The channel layer1322, the counter part1360, the source electrode1324, and the drain electrode1326constitute a TFT1380. The array substrate1100may include components other than these components. A switching element constituted by the TFT1380may be replaced with a switching element of a different type.

The insulating substrate1160has an insulating property and a light transmitting property, and is made of a glass substrate, a quartz substrate, or the like.

The first gate line1162, the gate insulating film1320, the channel layer1322, the source line1164, the source electrode1324, the drain electrode1326, the transparent pixel electrode1260, the first interlayer insulating film1328, the second gate line1166, the second interlayer insulating film1330, and the transparent common electrode1220are disposed above the insulating substrate1160. Therefore, the TFT1380including the channel layer1322, the counter part1360, the source electrode1324, and the drain electrode1326is also disposed above the insulating substrate1160.

The first gate line1162is disposed above the insulating substrate1160.

The gate insulating film1320is disposed above the insulating substrate1160so as to overlap the first gate line1162. The gate insulating film1320separates, in the thickness direction of the insulating substrate1160, the first gate line1162from the channel layer1322, the source electrode1324, and the drain electrode1326that are disposed above the gate insulating film1320to electrically insulate the first gate line1162from the channel layer1322, the source electrode1324, and the drain electrode1326.

The channel layer1322is disposed above the gate insulating film1320. The channel layer1322is disposed above the counter part1360with the gate insulating film1320interposed therebetween, and faces the counter part1360with the gate insulating film1320interposed therebetween. This causes the counter part1360to function as a gate electrode of the TFT1380. The gate signal transmitted through the first gate line1162is supplied to the counter part1360.

The source line1164is disposed above the gate insulating film1320.

The source electrode1324branches off from the source line1164and is disposed over the gate insulating film1320and the channel layer1322. The source signal transmitted through the source line1164is supplied to the source electrode1324.

The drain electrode1326is disposed over the gate insulating film1320and the channel layer1322.

The TFT1380switches the source signal supplied to the source electrode1324in accordance with the gate signal supplied to the counter part1360to produce a pixel potential, and supplies the pixel potential thus produced to the drain electrode1326. Further, the TFT1380is disposed along each of the plurality of intersections1200. Therefore, the array substrate1100includes a plurality of the TFTs1380respectively disposed along the plurality of intersections1200. The plurality of TFTs1380respectively switch source signals transmitted through source lines1164forming the plurality of intersections1200in accordance with gate signals transmitted through gate lines1162forming the plurality of intersections1200to respectively produce a plurality of the pixel potentials.

The transparent pixel electrode1260is disposed above the gate insulating film1320. The transparent pixel electrode1260is in contact with the drain electrode1326. This causes the transparent pixel electrode1260to be electrically connected to the drain electrode1326and accordingly electrically connected to the TFT1380. Further, the plurality of pixel potentials thus produced are respectively applied to the plurality of transparent pixel electrodes1260, The plurality of transparent pixel electrodes1260are arranged in a matrix.

The first interlayer insulating film1328is disposed above the gate insulating film1320so as to overlap the source line1164, the channel layer1322, the source electrode1324, the drain electrode1326, and the transparent pixel electrode1260. The first interlayer insulating film1328separates, in the thickness direction of the insulating substrate1160, the source line1164from the second gate line1166disposed above the first interlayer insulating film1328to electrically insulate the source line1164from the second gate line1166.

The second gate line1166is disposed above the first interlayer insulating film1328. The second gate line1166is disposed between the source line1164and the transparent common electrode1220.

The second interlayer insulating film1330is disposed above the first interlayer insulating film1328so as to overlap the second gate line1166. The second interlayer insulating film1330separates, in the thickness direction of the insulating substrate1160, the second gate line1166from the transparent common electrode1220disposed above the second interlayer insulating film1330to electrically insulate the second gate line1166from the transparent common electrode1220. Further, an insulating film1400including the first interlayer insulating film1328and the second interlayer insulating film1330separates, in the thickness direction of the insulating substrate1160, the transparent pixel electrode1260from the transparent common electrode1220disposed above the insulating film1400to electrically insulate the transparent pixel electrode1260from the transparent common electrode1220.

The transparent common electrode1220is disposed above the second interlayer insulating film1330. A common potential is applied to the transparent common electrode1220. The transparent common electrode1220includes a counter part1420. The counter part1420has the slit group1280and faces the transparent pixel electrode1260with the insulating film1400interposed therebetween. This causes the transparent common electrode1220to produce fringe electric fields in response to the plurality of pixel potentials respectively between the plurality of transparent pixel electrodes1260and the transparent common electrode1220. The fringe electric field thus produced passes through the slit group1280. Further, a storage capacitance for stabilizing the pixel potential is produced between the transparent pixel electrode1260and the transparent common electrode1220.

1.7 Cross-Sectional Structure of Contact Part

FIG. 5is an enlarged cross-sectional view schematically illustrating the array substrate and the counter substrate provided in the liquid crystal display panel of the first preferred embodiment.FIG. 5illustrates a cross section taken along a cutting line B-B ofFIG. 3.

In the array substrate1100, as illustrated inFIG. 5, a first insulating film1460including the gate insulating film1320, the first interlayer insulating film1328, and the second interlayer insulating film1330is disposed between the plurality of first gate lines1162and the transparent common electrode1220. Further, a second insulating film1462including the second interlayer insulating film1330is disposed between the plurality of second gate lines1166and the transparent common electrode1220.

An insulating film1480including the gate insulating film1320and the first interlayer insulating film1328separates the plurality of second gate lines1166from the plurality of first gate lines1162in the thickness direction of the insulating substrate1160. This causes the plurality of second gate lines1166to be disposed in a layer different from a layer where the plurality of first gate lines1162are disposed and thus causes the plurality of second gate lines1166to be disposed at positions different from positions where the plurality of first gate lines1162are disposed in the thickness direction of the insulating substrate1160.

The array substrate1100further includes a plurality of first contact hole parts1500and a plurality of second contact hole parts1502.

The plurality of first contact hole parts1500pass through the first insulating film1460. Upper ends of the plurality of first contact hole parts1500are in contact with the transparent common electrode1220. Lower ends of the plurality of first contact hole parts1500are respectively in contact with the plurality of first gate lines1162. This causes the plurality of first gate lines1162to be electrically connected to the transparent common electrode1220through the plurality of first contact hole parts1500respectively.

The plurality of second contact hole parts1502pass through the second insulating film1462. Upper ends of the plurality of second contact hole parts1502are in contact with the transparent common electrode1220. Lower ends of the plurality of second contact hole parts1502are respectively in contact with the plurality of second gate lines1166. This causes the plurality of second gate lines1166to be electrically connected to the transparent common electrode1220through the plurality of second contact hole parts1502respectively.

Accordingly, the plurality of second gate lines1166are respectively connected to the plurality of first gate lines1162through the plurality of second contact hole parts1502, the transparent common electrode1220, and the plurality of first contact hole parts1500.

The plurality of first contact hole parts1500and the plurality of second contact hole parts1502are provided in the plurality of dummy pixels1300disposed outside the display area1140. Accordingly, a pixel prone to point defect failure is the dummy pixel1300disposed outside the display area1140. This makes it possible to suppress point defect failure in the display area1140and provide the liquid crystal display panel1020having high display quality.

The counter substrate1104includes a black matrix1520.

The plurality of first contact hole parts1500and the plurality of second contact hole parts1502overlap the black matrix1520in plan view in the thickness direction of the insulating substrate1160. Accordingly, the plurality of second gate lines1166are electrically connected to the plurality of first gate lines1162at positions where the second gate lines1166overlap the black matrix1520in plan view in the thickness direction of the insulating substrate1160respectively. This causes a pixel prone to point defect failure to be shielded by the black matrix1520and accordingly prevents the pixel from being visually recognized. This makes it possible to suppress visual recognition of point defect failure and provide the liquid crystal display panel1020having high display quality.

1.8 Manufacturing Method of Array Substrate

Hereinafter, a manufacturing method of the array substrate1100will be described. The array substrate1100may be manufactured by a manufacturing method different from the manufacturing method described below.

First, a first metal film is formed on the insulating substrate1160. The first metal film is formed by sputtering using a direct current (DC) magnetron. The first metal film may be a metal film composed of Mo, Cr, W, Al, or Ta, or an alloy film made of an alloy primarily composed of Mo, Cr, W, Al, or Ta. Further, pattering is performed on the first metal film thus formed to form the first gate line1162.

After the first gate line1162is formed, the gate insulating film1320is formed. The gate insulating film1320is formed by plasma-enhanced chemical vapor deposition (CVD). The gate insulating film1320is generally a silicon nitride film, but may be a silicon oxide film, a silicon oxynitride film, or the like.

After the gate insulating film1320is formed, an amorphous silicon (a-Si) film is formed. The a-Si film is formed by plasma CVD. The a-Si film is generally a laminated film including an intrinsic semiconductor layer and an impurity semiconductor layer containing phosphorus or the like. The intrinsic semiconductor layer constitutes the channel layer1322. The impurity semiconductor layer is provided to establish an ohmic contact with the source electrode1324and the drain electrode1326. Further, patterning is performed on the a-Si film thus formed to form the channel layer1322arranged like islands. The channel layer1322may be an oxide semiconductor such as In—Ga—Zn—O instead of a-Si or the like.

After the channel layer1322is formed, a second metal film is formed. The second metal film is formed by sputtering using a DC magnetron. The second metal film may be a metal film composed of Mo, Cr, W, Al, or Ta, or an alloy film made of an alloy primarily composed of Mo, Cr, W, Al, or Ta. Further, patterning is performed on the second metal film thus formed to form the source line1164, the source electrode1324, and the drain electrode1326. An impurity semiconductor layer may be etched with the source line1164, the source electrode1324, and the drain electrode1326serving as masks. This makes it possible to reduce the number of mask processes.

After the source line1164, the source electrode1324, and the drain electrode1326are formed, a first transparent conductive film is formed. The first transparent conductive film is formed by sputtering using a DC magnetron. The first transparent conductive film is composed of indium tin oxide (ITO), zinc tin oxide (ZTO), or the like. Further, patterning is performed on the first transparent conductive film to form the transparent pixel electrode1260.

After the transparent pixel electrode1260is formed, the first interlayer insulating film1328is formed. The first interlayer insulating film1328is formed by plasma CVD. The first interlayer insulating film1328is a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like. The first interlayer insulating film1328may be an organic resin film made of an acrylic resin or an imide resin. The organic resin film results from applying a fluid to form a coated film and curing the coated film thus formed. In a case where the first interlayer insulating film1328is such an organic resin film, it is possible to increase the thickness of the first interlayer insulating film1328with ease and accordingly secure the insulating property of the first interlayer insulating film1328with ease. The first interlayer insulating film1328may be a laminated film including an inorganic film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film, and an organic resin film.

After the first interlayer insulating film1328is formed, a third metal film is formed. The third metal film is formed by sputtering using a DC magnetron. The third metal film may be a metal film composed of Mo, Cr, W, Al, or Ta, or an alloy film made of an alloy primarily composed of Mo, Cr, W, Al, or Ta. Further, patterning is performed on the third metal film thus formed to form the second gate line1166.

After the second gate line1166is formed, the second interlayer insulating film1330is formed. The second interlayer insulating film1330is formed by plasma CVD. The second interlayer insulating film1330is a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like. The second interlayer insulating film1330may be an organic resin film made of an acrylic resin or an imide resin. The organic resin film results from applying a fluid to form a coated film and curing the coated film thus formed. In a case where the second interlayer insulating film1330is such an organic resin film, it is possible to increase the thickness of the second interlayer insulating film1330with ease and accordingly secure the insulating property of the second interlayer insulating film1330with ease. The second interlayer insulating film1330may be a laminated film including an inorganic film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film, and an organic resin film.

After the second interlayer insulating film1330is formed, a first contact hole extending from an upper surface of the second interlayer insulating film1330to the first gate line1162is formed, and a second contact hole extending from the upper surface of the second interlayer insulating film1330to the second gate line1166is formed.

After the first contact hole and the second contact hole are formed, a second transparent conductive film is formed. The second transparent conductive film is formed by sputtering using a DC magnetron. The second transparent conductive film is made of ITO, ZTO, or the like. Further, patterning is performed on the second transparent conductive film to form the transparent common electrode1220. When the second transparent conductive film is formed, a transparent conductive film is attached to inner surfaces of the first contact hole and the second contact hole to form the first contact hole part1500and the second contact hole part1502. When patterning is performed on the second transparent conductive film, the slit group1280is formed on the transparent pixel electrode1260.

1.9 Comparison with Reference Example

FIG. 16is a plan view schematically illustrating a liquid crystal display panel of a reference example.

In a liquid crystal display panel9020illustrated inFIG. 16, main portions of a plurality of second gate lines9166are disposed outside a display area9140and on one side in the first direction D1when viewed from the display area9140. In this configuration, as illustrated inFIG. 16, it is not possible to narrow a frame area9142defined along one of four sides surrounding the display area9140located on one side in the first direction D1. Comparison betweenFIG. 16andFIG. 2can lead to understanding of the reason why the frame area1142defined along three of the four sides surrounding the display area1140can be narrowed in the first preferred embodiment.

2 Second Preferred Embodiment

The second preferred embodiment is different from the first preferred embodiment mainly in the following point: in the first preferred embodiment, the plurality of second gate lines1166are electrically connected to the plurality of first gate lines1162through the plurality of second contact hole parts1502, the transparent common electrode1220, and the plurality of first contact hole parts1500respectively. On the other hand, in the second preferred embodiment, the plurality of second gate lines1166are electrically connected to the plurality f first gate lines1162only through a plurality of contact hole parts described below respectively.

Hereinafter, a configuration of a liquid crystal display panel of the second preferred embodiment related to the above difference will be described. With respect to a configuration of which no description will be given, the configuration employed for the liquid crystal display panel1020of the first preferred embodiment is employed for the liquid crystal display panel of the second preferred embodiment as it is or with modifications.

FIG. 1also serves as a cross-sectional view schematically illustrating the liquid crystal display device including the liquid crystal display panel of the second preferred embodiment.FIG. 2also serves as a plan view schematically illustrating the liquid crystal display panel of the second preferred embodiment.FIG. 4also serves as an enlarged cross-sectional view schematically illustrating an array substrate provided in the liquid crystal display panel of the second preferred embodiment.

FIG. 6is an enlarged plan view schematically illustrating a pattern on the array substrate provided in the liquid crystal display panel of the second preferred embodimentFIG. 6is an enlarged view of a pattern located in the region R1illustrated inFIG. 2.

FIG. 7is an enlarged cross-sectional view schematically illustrating the array substrate provided in the liquid crystal display panel of the second preferred embodiment.FIG. 7illustrates a cross section taken along a cutting line C-C ofFIG. 6.

In a liquid crystal display panel2020of the second preferred embodiment, as illustrated inFIG. 7, the insulating film1480including the gate insulating film1320and the first interlayer insulating film1328is disposed between the plurality of first gate lines1162and the plurality of second gate lines1166.

The array substrate1100includes a plurality of contact hole parts2504as illustrated inFIGS. 6 and 7.

The plurality of contact hole parts2504pass through the insulating film1480. Upper ends of the plurality of contact hole parts2504are respectively in contact with the plurality of second gate lines1166. Lower ends of the plurality of contact hole parts2504are respectively in contact with the plurality of first gate lines1162. This causes the plurality of second gate lines1166to be electrically connected to the plurality of first gate lines1162through the plurality of second contact hole parts2504respectively.

The plurality of contact hole parts2504are provided in the plurality of dummy pixels1300disposed outside the display area1140.

In the second preferred embodiment, the frame area1142defined along three of the four sides surrounding the display area1140can be narrowed, as in the first preferred embodiment. It is also possible to suppress display abnormality and point defect failure. It is also possible to easily design the liquid crystal display panel2020having a peculiar planar shape and high design characteristics. Further, the plurality of second gate lines1166are prevented from causing a decrease in display performance.

In the first preferred embodiment, the transparent co on electrode1220to which the plurality of gate signals are applied is in close proximity to the liquid crystal layer1102. Accordingly, in the vicinity of the transparent common electrode1220to which the plurality of gate signals are applied, the orientations of the liquid crystal molecules vary, which may deteriorate the display quality due to, for example, light leakage. On the other hand, in the second preferred embodiment, the second interlayer insulating film1330separates the plurality of second gate lines1166to which the plurality of gate signals are applied from the liquid crystal layer1102. This makes it possible to provide the liquid crystal display panel2020having high display quality.

3 Third Preferred Embodiment

The third preferred embodiment is different from the first preferred embodiment mainly in the following point: in the first preferred embodiment, the plurality of second gate lines1166are electrically connected to the plurality of first gate lines1162outside the display area1140respectively. On the other hand, in the third preferred embodiment, the plurality of second gate lines1166are electrically connected to the plurality of first gate lines1162in the display area1140respectively. Further, a plurality of conductive layers described below are respectively disposed between the plurality of source lines1164and the plurality of second gate lines1166, and a potential identical to the common potential or a ground potential is applied to the plurality of conductive layers thus disposed.

Hereinafter, a configuration of a liquid crystal display panel of the third preferred embodiment related to the above difference will be described. With respect to a configuration of which no description be given, the configuration employed for the liquid crystal display panel1020of the first preferred embodiment is employed for the liquid crystal display panel of the third preferred embodiment as it is or with modifications.

FIG. 1also serves as a cross-sectional view schematically illustrating the liquid crystal display device including the liquid crystal display panel of the third preferred embodiment.FIG. 4also serves as an enlarged cross-sectional view schematically, illustrating an array substrate provided in the liquid crystal display panel of the third preferred embodiment.FIG. 5also serves an enlarged cross-sectional view schematically illustrating the array substrate and a counter substrate provided in the liquid crystal display panel of the third preferred embodiment.

FIG. 8is a plan view schematically illustrating the liquid crystal display panel of the third preferred embodiment.

FIG. 9is an enlarged plan view schematically illustrating a pattern on the array substrate provided in the liquid crystal display panel of the third preferred embodiment.FIG. 9is an enlarged view of a pattern located in a region R2illustrated inFIG. 8.

FIG. 10is an enlarged cross-sectional view schematically illustrating the array substrate provided in the liquid crystal display panel of the third preferred embodiment.FIG. 10illustrates a cross section taken along a cutting line D-D ofFIG. 9.

In a liquid crystal display panel3020of the third preferred embodiment, as illustrated inFIGS. 8 and 9, the plurality of second gate lines1166are electrically connected to the plurality of first gate lines1162through the plurality of contact parts1168respectively. The plurality of contact parts1168are disposed in the display area1140. This causes the plurality of second gate lines1166to be electrically connected to the plurality of first gate lines1162in the display area1140respectively.

The plurality of contact parts1168are provided in the plurality of pixels1240. This causes the plurality of second gate lines1166to be electrically connected to the plurality of first gate lines1162in the plurality of pixels1240respectively.

The array substrate1100includes a plurality of conductive layers3600as illustrated inFIG. 10.

The plurality of conductive layers3600are respectively disposed between the plurality of source lines1164and the plurality of second gate lines1166. A potential identical to the common potential or a ground potential is applied to the plurality of conductive layers3600. The plurality of conductive layers3600are embedded in the first interlayer insulating film1328, and the first interlayer insulating film1328separates the plurality of conductive layers3600from the plurality of source lines1164and the plurality of second gate lines1166in the thickness direction of the insulating substrate1160to electrically insulate the plurality of conductive layers3600from the plurality of source lines1164and the plurality of second gate lines1166.

The ground potential is desirably applied to the plurality of conductive layers3600. Further, the plurality of second gate lines1166are disposed in a layer identical to a layer where the plurality of transparent pixel electrodes1260are disposed.

In the third preferred embodiment, the frame area1142defined along three of the four sides surrounding the display area1140can be narrowed, as in the first preferred embodiment. It is also possible to easily design the liquid crystal display panel3020having a peculiar planar shape and high design characteristics. Further, the plurality of second gate lines1166are prevented from causing a decrease in display performance.

Further, in the third preferred embodiment, a stray capacitance produced between the source line1164and the second gate line1166is reduced, making it possible to suppress the influence of the gate signal on the source signal. This in turn makes it possible to suppress display abnormality.

In addition, in the third preferred embodiment, even when the second gate line1166is electrically connected to the first gate line1162in the display area1140, display abnormality can be suppressed. This makes it possible to further narrow the frame area1142.

4 Fourth Preferred Embodiment

The fourth preferred embodiment is different from the first preferred embodiment mainly in the following point: in the first preferred embodiment, one second gate line1166overlaps one source line1164. On the other hand, in the fourth preferred embodiment, two second gate lines1166overlap one source line1164.

Hereinafter, a configuration of a liquid crystal display panel of the fourth preferred embodiment related to the above difference will be described. With respect to a configuration of which no description will be given, the configuration employed for the liquid crystal display panel1020of the first preferred embodiment is employed for the liquid crystal display panel of the fourth preferred embodiment as it is or with modifications.

FIG. 1also serves as a cross-sectional view schematically illustrating the liquid crystal display device including the liquid crystal display panel of the fourth preferred embodiment.FIG. 2also serves as a plan view schematically illustrating the liquid crystal display panel of the fourth preferred embodiment.FIG. 4also serves as an enlarged cross-sectional view schematically illustrating an array substrate provided in the liquid crystal display panel of the fourth preferred embodiment.FIG. 5also serves an enlarged cross-sectional view schematically illustrating the array substrate and a counter substrate provided in the liquid crystal display panel of the fourth preferred embodiment.

FIG. 11is a plan view schematically illustrating an arrangement of a plurality of first gate lines, a plurality of source lines, a plurality of second gate lines, and a plurality of contact parts provided in the liquid crystal display panel of the fourth preferred embodiment.

In a liquid crystal display panel4020of the fourth preferred embodiment, as illustrated inFIG. 11, the plurality of first gate lines1162are arranged in the second direction D2, and the second direction D2corresponds to a gate signal scan direction.

An n-th second gate line GVnof the plurality of second gate lines1166is electrically connected to an n-th first gate line GHnof the plurality of first gate lines1162through an n-th contact part CNnof the plurality of contact parts1168. n is a natural number. The n-th contact part CNnis disposed outside the display area1140, but may be disposed in the display area1140.

The n-th second gate line GVnextends, in the display area1140, over an n-th source line Snof the plurality of source lines1164in the second direction D2, extends over an (n+4)-th first gate line GHn+4in the first direction D1, and then extends over an (n−1)-th source line Sn−1in the second direction D2. Accordingly, the plurality of second gate lines1166have an arrangement where two second gates lines1166overlap each of the plurality of source lines1164in the display area1140in plan view in the thickness direction of the insulating substrate1160.

The n-th second gate line GVnextends over the n-th source line Snby a distance four times a pixel pitch in the second direction D2, extends over the (n+4)-th first gate line Gn+4by a distance equal to the pixel pitch in the first direction D1, and then extends over the (n−1)-th source line Sn−1by a distance four times the pixel pitch in the second direction D2. The distance four times the pixel pitch in the second direction D2may be changed to a different distance. However, the different distance is a distance expressed by a natural number multiple of the pixel pitch in the second direction D2. The distance equal to the pixel pitch in the first direction D1may be changed to a different distance. However, the different distance is a distance expressed by a natural number multiple of the pixel pitch in the first direction D1.

FIG. 12is a simplified circuit diagram simply illustrating electrical connections among the plurality of first gate lines, the plurality of source lines, the plurality of second gate lines, and the plurality of contact parts provided in the liquid crystal display panel of the fourth preferred embodiment.

In the following, on the assumption that the n-th source line Snis selected, the n-th first gate line GHnis referred to as a present-stage gate line, the (n−1)-th first gate line GHn+1that is scanned after the n-th first gate line GHnis referred to as a next-stage gate line, and the n-th source line Snis referred to as a selected source line.

As illustrated inFIG. 11, the second gate line GVnelectrically connected to the present-stage gate line GHnand the second gate line GVn+1electrically connected to the next-stage gate line GHn+1are disposed over the selected source line Sn. This causes, as illustrated inFIG. 12, the selected source line Snto be capacitively coupled to the second gate line GVnand the second gate line GVn+1. Accordingly, the selected source line Snproduces a stray capacitance Cnwith the second gate line GVn, and produces a stray capacitance Cn+1with the second gate line GVn+1. The stray capacitance Cnis smaller than a stray capacitance produced when the selected source line Snis capacitively coupled to only the second gate line GVn. The stray capacitance Cn+1is desirably equal to the stray capacitance Cn.

FIG. 13is a simplified circuit diagram simply illustrating electrical connections among the plurality of first gate lines, the plurality of source lines, the plurality of second gate lines, and the plurality of contact parts provided in a liquid crystal display panel of a modification of the fourth preferred embodiment.

In the following, on the assumption that the n-th source line Snis selected, the n-th first gate line GHnis referred to as a present-stage gate line, the (n+2)-th gate line CHn+2that is scanned second after the n-th first gate line GHnis referred to as a second-next-stage gate line, and the n-th source line Snis referred to as a selected source line.

In the modification, over the selected source line Sn, the second gate line GVnelectrically connected to the present-stage gate line GHnand the second gate line GVn+2electrically connected to the second-next-stage gate line GHn+2are disposed. This causes the selected source line Snto be capacitively coupled to the second gate line GVnand the second gate line GVn+2. Accordingly, as illustrated inFIG. 13, the selected source line Snproduces a stray capacitance Cnwith the second gate line GVn, and produces a stray capacitance Cn+2with the second gate line GVn+2. The stray capacitance Cnis smaller than a stray capacitance produced when the selected source line Snis capacitively coupled to only the second gate line GVn. The stray capacitance Cn+2is desirably equal to the stray capacitance Cn.

Instead of the arrangement where two second gate lines1166overlap each of the plurality of source lines1164, an arrangement where three or more second gate lines1166overlap each of the plurality of source lines1164may be employed.

In the fourth preferred embodiment, the frame area1142defined along three of the four sides surrounding the display area1140can be narrowed, as in the first preferred embodiment. It is also possible to suppress display abnormality and point defect failure. It is also possible to easily design the liquid crystal display panel4020having a peculiar planar shape and high design characteristics. Further, the plurality of second gate lines1166are prevented from causing a decrease in display performance.

Further, in the fourth preferred embodiment, two or more second gate lines1166are capacitively coupled to one source line1164to make the stray capacitance produced between one second gate line1166and one source line1164small, making it possible to suppress the influence of the gate signal on the source signal. This in turn makes it possible to suppress display abnormality.

5 Fifth Preferred Embodiment

The fifth preferred embodiment is different from the first preferred embodiment mainly in the following point: in the first preferred embodiment, transition of the plurality of gate signals from an on potential to an off potential is made in one stage. On the other hand, in the fifth preferred embodiment, the transition of the plurality of gate signals from the on potential to the off potential is made in two stages.

Hereinafter, a configuration of a liquid crystal display panel of the fifth preferred embodiment related to the above difference will be described. With respect to a configuration of which no description will be given, the configuration employed for the liquid crystal display panel1020of the first preferred embodiment is employed for the liquid crystal display panel of the fifth preferred embodiment as it is or with modifications.

FIG. 1also serves as a cross-sectional view schematically illustrating the liquid crystal display device including the liquid crystal display panel of the fifth preferred embodiment.FIG. 2also serves as a plan view schematically illustrating the liquid crystal display panel of the fifth preferred embodiment.FIG. 3is an enlarged plan view schematically illustrating a pattern on an array substrate provided in the liquid crystal display panel of the fifth preferred embodiment.FIG. 4also serves as an enlarged cross-sectional view schematically illustrating the array substrate provided in the liquid crystal display panel of the fifth preferred embodiment.FIG. 5also serves as an enlarged cross-sectional view schematically illustrating the array substrate and a counter substrate provided in the liquid crystal display panel of the fifth preferred embodiment.

FIGS. 14A and 14Bare simplified waveform charts showing waveforms of the gate signal and the source signal in the liquid crystal display panel of the fifth preferred embodiment.FIG. 14Ashows time variations in potential of the gate signal.FIG. 14Bshows time variations in potential of the source signal. InFIGS. 14A and 14B, the axis of ordinates represents the potential, and the axis of abscissas represents the time.

FIGS. 15A and 15Bare simplified waveform charts showing waveforms of the gate signal and the source signal in the liquid crystal display panel of the reference example.FIG. 15Ashows time variations in potential of the gate signal.FIG. 15Bshows time variations in potential of the source signal. InFIGS. 15A and 15B, the axis of ordinates represents the potential, and the axis of abscissas represents the time.

In a liquid crystal display panel5020of the fifth preferred embodiment, the plurality of second gate lines1166are electrically connected to the plurality of first gate lines1162outside the display area1140respectively, but may be electrically connected to the plurality of first gate lines1162in the display area1140respectively.

In the liquid crystal display panel5020of the fifth preferred embodiment, as illustrated inFIG. 14A, when the gate signal is made low, the transition of the potential of the gate signal from an on potential VONto an off potential VOFFis made in two stages including a first stage in which the potential of the gate signal is lowered from the on potential VONto an intermediate potential. V1, and a second stage in which the potential of the gate signal is lowered from the intermediate potential V1to the off potential VOFF. In a period from the end of the first stage to the start of the second stage, the potential of the gate signal is maintained at the intermediate potential V1for a set time. The transition of the potential of the gate signal from the on potential VONto the off potential VOFFmay be made in three or more stages. As described above, when the transition of the potential of the gate signal from the on potential VONto the off potential VOFFis made in two or more stages, the transition of the potential of the gate signal from the on potential VONto the off potential VOFFis made slowly, making it possible to suppress an influence5020of the gate signal on the source signal due to the capacitive coupling, as illustrated inFIG. 14B. This in turn makes it possible to suppress display abnormality.

On the other hand, as illustrated inFIG. 15A, when the transition of the potential of the gate signal from the on potential VONto the off potential VOFFis made in one stage, an influence5022of the gate signal on the source signal due to the capacitive coupling becomes larger.

In the fifth preferred embodiment, the frame area1142defined along three of the four sides surrounding the display area1140can be narrowed, as in the first preferred embodiment. It is also possible to suppress display abnormality and point defect failure. It is also possible to easily design the liquid crystal display panel5020having a peculiar planar shape and high design characteristics. Further, the plurality of second gate lines1166are prevented from causing a decrease in display performance.

Note that, according to the present invention, each of the preferred embodiments can be modified or omitted as appropriate within the scope of the present invention.

Although descriptions have been given of the examples in which the color filter is formed on the counter substrate1104of the first to fifth preferred embodiments, the color filter may be formed on the array substrate1100.

Although descriptions have been given of the configuration in which the common electrode1220is formed on the array substrate1100, the common electrode1220may be formed on the counter substrate1104like a TN type. In such a configuration, display is performed by producing electric fields in response to the plurality of pixel potentials in the liquid crystal layer1102between the plurality of transparent pixel electrodes and the common electrode.