Three-port SRAM cell and layout method

Semiconductor devices are provided. A write port circuit is configured to perform a write function according to the write word line and the first and second write bit lines. The first read port circuit is configured to perform first read function according to the first read bit line and the first read word line. The second read port circuit is configured to perform second read function according to the second read bit line and the second read word line. The transistors of the first and second read port circuits share a first active structure extending in the first direction. The first read bit line and the second read bit line extend in the first direction in a first metallization layer, and the first write bit line and the second write bit line extend in the first direction in a second metallization layer over the first metallization layer.

BACKGROUND

Memories are commonly used in integrated circuits. For example, a static random access memory (SRAM) is a volatile memory used in electronic applications where high speed, low power consumption, and simplicity of operation are needed. Embedded SRAM is particularly popular in high-speed communications, image processing, and system-on-chip (SOC) applications. SRAM has the advantage of being able to hold data without requiring a refresh.

SRAM includes a plurality of bit cells disposed in rows and columns to form an array. Each bit cell includes a plurality of transistors coupled to bit lines and word lines that are used to read and write a bit of data to the memory cell.

In deep sub-micron technology, the embedded SRAM has become a very popular storage unit for high-speed communication, image processing and SOC products. In particular, three-port SRAM allows parallel operations (e.g., 1 cycle may include two read operations) and therefore have higher bandwidth than the signal-port SRAM. In order to meet the shrink requirements, the low loading, high speed cell structure become very important factors in embedded memory and SOC products.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different nodes of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In some embodiments, the formation of a first node over or on a second node in the description that follows may include embodiments in which the first and the second nodes are formed in direct contact, and may also include embodiments in which additional nodes may be formed between the first and the second nodes, such that the first and the second nodes may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

FIG.1shows a schematic circuit diagram of a three-port memory cell10, in accordance with some embodiments of the disclosure. In some embodiments, the memory cell10is a static random access memory (SRAM) cell. The memory cell10includes a write port circuit12having data nodes ND and NDB, a first read port circuit14coupled to the data node NDB, and a second read port circuit16coupled to the data node ND.

The write port circuit12is configured to perform a write function according to a write word line WWL and the write bit lines WBLB and WBL. The write port circuit12includes the pull-up transistors WPU1and WPU2, the pull-down transistors WPD1and WPD2, and the pass-gate transistors WPG1and WPG2. The pull-up transistors WPU1and WPU2are P-type transistors, and the pull-down transistors WPD1and WPD2, and the pass-gate transistors WPG1and WPG2are N-type transistors. The pull-up transistors WPU1and WPU2and the pull-down transistors WPD1and WPD2form a cross latch having two cross-coupled inverters. The pull-up transistor WPU1and the pull-down transistor WPD1form a first inverter, and the pull-up transistor WPU2and the pull-down transistor WPD2form a second inverter. The drains of the pull-up transistor WPU1and the pull-down transistor WPD1are coupled together and form the data node ND. The drains of the pull-up transistor WPU2and the pull-down transistor WPD2are coupled together and form the data node NDB. The gates of the pull-up transistor WPU1and the pull-down transistor WPD1are coupled together and to the data node NDB. The gates of the pull-up transistor WPU2and the pull-down transistor WPD2are coupled together and to the data node ND. The sources of the pull-up transistors WPU1and WPU2are coupled to a supply voltage node that is configured to receive a supply voltage VDD. The sources of the pull-down transistors WPD1and WPD2are coupled to the ground VSS.

In the write port circuit12, the pass-gate transistor WPG1is coupled between the data node ND and a write bit line WBL, and the pass-gate transistor WPG2is coupled between the data node NDB and a write bit line WBLB. The gates of the pass-gate transistors WPG1and WPG2are coupled to a write word line WWL.

In the write port circuit12, the pull-up transistor WPU1and the pull-down transistor WPD1are coupled in series between the supply voltage VDD and the ground VSS, and the pull-up transistor WPU2and the pull-down transistor WPD2are coupled in series between the supply voltage VDD and the ground VSS. Furthermore, the pull-up transistor WPU1and the pass-gate transistor WPG1are coupled in series between the supply voltage VDD and the write bit line WBL, and the pull-up transistor WPU2and the pass-gate transistor WPG2are coupled in series between the supply voltage VDD and the write bit line WBLB.

In some embodiments, in a memory array having a plurality of memory cells each having a configuration the same as the memory cell10, the write bit lines WBLB and WBL are coupled to the pass-gate transistors WPG1and WPG2of memory cells in a column of the memory array, and the write word line WWL is coupled to each gate of the pass-gate transistors WPG1and WPG2of the memory cells in a row of the memory array.

In a write operation of memory cell10using the write port circuit12, data to be written to the memory cell10are applied to the write bit lines WBL and WBLB. The data in the write bit lines WBL and WBLB are complementary. The write word line WWL is then activated to turn on the pass-gate transistors WPG1and WPG2. As a result, the data on bit lines WBL and WBLB are transferred to the corresponding nodes ND and NDB for storage.

The first read port circuit14is configured to perform a first read function according to the first read bit line RBL1and the first read word line RWL1. The first read port circuit14includes the pass-gate transistor RPG1and the pull-down transistor RPD1connected in series. The pull-down transistor RPD1is coupled between the ground VSS and the pass-gate transistor RPG1. A gate of the pull-down transistor RPD1is coupled to the data node NDB. The pass-gate transistor RPG1is coupled between the pull-down transistor RPD1and the first read bit line RBL1. The gate of the pass-gate transistor RPG1is coupled to the first read word line RWL1.

In a read operation of memory cell10using the first read port circuit14, the read bit line RBL1is pre-charged with a high voltage (e.g., a high logic level). The first read word line RWL1is activated with a high voltage (e.g., a high logic level) to turn on the pass-gate transistor RPG1. The data stored in the node NDB turns on or off the pull-down transistor RPD1. For example, if the data with a high logic level is stored in the node NDB, the pull-down transistor RPD1is turned on. The turned-on transistors RPD1and RPG1then pull the first read bit line RBL1to the ground. On the other hand, if the data with a low logic level is stored in the node NDB, the pull-down transistor RPD1is turned off and operates as an open circuit. As a result, the first read bit line RBL1remains at the pre-charged high logic level. Detecting a logical value on the first read bit line RBL1therefore reveals the logical value of the data stored in the node NDB.

The second read port circuit16is configured to perform a second read function according to the second read bit line RBL2and the second read word line RWL2. The second read port circuit16includes the pass-gate transistor RPG2and the pull-down transistor RPD2connected in series. The pull-down transistor RPD2is coupled between the ground VSS and the pass-gate transistor RPG2. A gate of the pull-down transistor RPD2is coupled to the data node ND. The pass-gate transistor RPG2is coupled between the pull-down transistor RPD2and the second read bit line RBL2. The gate of the pass-gate transistor RPG2is coupled to the second read word line RWL2.

A read operation of memory cell10using the second read port circuit16is performed in a manner similar to performing a read operation of the first read port circuit14, and the detailed description thereof is thus omitted. As a result, if the data node ND stores a high logic level, the second read bit line RBL2is pulled to the ground. On the other hand, if the data node ND stores a low logic level, the second read bit line RBL2remains at the pre-charged high logic level. Detecting a logic level of the second read bit line RBL2therefore reveals the logic level of the data stored in the data node ND.

Memory cell10is illustrated as an example. In some embodiments, the present application is applicable to a multiple-port SRAM cell having one or more write ports and/or one or more read ports.

FIG.2shows a cross sectional view of a semiconductor device100, in accordance with some embodiments of the disclosure. In the semiconductor device100, one or more memory cells10as illustrated in the disclosure are formed. Furthermore, Some components of semiconductor device100are not depicted for clarity ofFIG.2.

The semiconductor device100includes a well region110. In some embodiments, the well region110is a P-type well region, and the material of the P-type well region includes Si with Boron (B) doping. In some embodiments, the well region110is an N-type well region, and the material of the N-type well region includes Si with Phosphorus (P) doping. The active structures (or the active regions)115are formed over the well region110, and the gate structures130are formed over the active structures115.

The gate vias VG are formed over and connected to the gate structures130(e.g., the gate structures). Isolation feature120is over the well region110and under the gate structure110. The isolation feature120is used for isolating the active structure115of a transistor from other devices. In some embodiments, the isolation feature120may include different structures, such as shallow trench isolation (STI) structure, deep trench isolation (DTI) structure. Therefore, the isolation feature120is also referred as to as a STI feature or DTI feature.

The semiconductor device100further includes the vias V1, V2, and V3and the metal lines M1, M2, M3and M4in an inter-metal dielectric (IMD). In some embodiments, the IMD may be multilayer structure, such as one or more dielectric layers. The metal lines M1, M2, M3and M4are formed in respective conductive layers, which are also referred to as metallization layers. Moreover, the vias VG, V0(not shown), V1, V2, and V3are formed in respective via layers over the gate structures130.

InFIG.2, the conductive layers of the semiconductor device100include a first metallization layer having first conductive features (e.g., the metal lines MD, a second metallization layer having second conductive features (e.g., the metal lines M2), a third metallization layer having third conductive features (e.g., the metal lines M3), and a fourth metallization layer having fourth conductive features (e.g., the metal lines M4).

The via layers of semiconductor device100include a base via layer having the vias V0(not shown) and the vias VG, a first via layer having the vias V1, a second via layer having the vias V2, and a third via layer having the vias V3. The vias V0and the vias VG are arranged to connect at least some of the conductive structures (contacts) and the gate structures130with corresponding first metal lines M1. The vias V1are arranged to connect at least some first metal lines M1with the corresponding second metal lines M2. The vias V2are arranged to connect at least some second metal lines M2with the corresponding third metal lines M3. The vias V3are arranged to connect at least some third metal lines M3with the corresponding fourth metal lines M4.

FIG.2is used as to demonstrate the spatial relationship among various metallization layers and via layers. In some embodiments, the numbers of conductive features at various layers are not limited to the example depicted inFIG.2. In some embodiments, there are one or more metallization layers and one or more via layers over the fourth metal lines M4.

FIG.3shows a top view of a memory cell10A in a semiconductor device100A, with all the depictions regarding components in and under the first metallization layer ofFIG.2, in accordance with some embodiments of the disclosure. Moreover, the memory cell10A is an implementation of the memory cell10depicted inFIG.1. In this embodiment, the transistors in the memory cell10A are fin-like field effect transistors (FinFETs).

The memory cell10A includes a substrate (not labeled) having a P-type well region110band an N-type well region110a. The memory cell10A includes the active structures115a,115b_1,115b_2,115c_1and115c_2extending along the Y-direction. The active structures115b_1,115b_2,115c_1and115c_2are formed in the P-type well region110b, and the active structure115ais formed in the N-type well region110a. In such embodiments, the active structures115a,115b_1,115b_2,115c_1and115c_2are the semiconductor fins formed on the substrate. The number of fins for each transistor is provided as an example. In some embodiments, any number of fins are within the scope of various embodiments. In some embodiments, the active structures115a,115b_1,115b_2,115c_1and115c_2are integrally formed with the substrate.

A gate structure130bforms the pull-up transistor WPU1with the underlying active structure115ain the N-type well region110a. In this embodiment, the gate structures115ais fin-based and includes one or more fins. The gate structure130bfurther forms the pull-down transistor WPD1with the underlying active structures115b_1and115b_2in the P-type well region110b, and the pull-down transistor RPD1with the underlying active structures115c_1and115c_2in the P-type well region110b. In other words, the gate structure130bis shared by the pull-up transistor WPU1and the pull-down transistors WPD1and RPD1, and the gate structure130bcorresponds to the data node NDB. In some embodiments, each of the active structures115b_1and115b_2and the active structures115c_1and115c_2is fin-based and includes one or more fins.

A gate structure130cforms the pull-up transistor WPU2with the underlying active structure115ain the N-type well region110a. In this embodiment, the active structure115ais shared by the pull-up transistors WPU1and WPU2. The gate structure130cfurther forms the pull-down transistor WPD2with the underlying active structures115b_1and115b_2in the P-type well region110b, and the pull-down transistor RPD2with the underlying active structures115c_1and115c_2in the P-type well region110b. In other words, the gate structure130cis shared by the pull-up transistor WPU2and the pull-down transistors WPD2and RPD2, and the gate structure130ccorresponds to the data node ND.

A gate structure130aforms the pass-gate transistor WPG1with the underlying active structures115b_1and115b_2in the P-type well region110b. A gate structure130dforms the pass-gate transistor WPG2with the underlying active structures115b_1and115b_2in the P-type well region110b. In this embodiment, the active structures115b_1and115b_2are shared by the pass-gate transistors WPG1and WPG2, and the pull-down transistors WPD1and WPD2. Furthermore, the number of the active structures115b_1and115b_2shared by the pass-gate transistors WPG1and WPG2, and the pull-down transistors WPD1and WPD2is provided as an example. The gate structure130ais electrically connected to the gate structure130dthrough the gate via140a, the metal line150aand the gate via140b.

A gate structure130eforms the pass-gate transistor RPG1with the underlying active structures115c_1and115c_2in the P-type well region110b. A gate structure130fforms the pass-gate transistor RPG2with the underlying active structures115c_1and115c_2in the P-type well region110b. In this embodiment, the active structures115c_1and115c_2are shared by the pass-gate transistors RPG1and RPG2, and the pull-down transistors RPD1and RPD2. In other words, the transistors in the first read port circuit14and the second read port circuit16share the same active structures. The gate structure130eis electrically connected to the metal line150jthrough the gate via140e. The gate structure130fis electrically connected to the metal line150kthrough the gate via140f. Furthermore, the number of the active structures115c_1and115c_2shared by the pass-gate transistors RPG1and RPG2, and the pull-down transistors RPD1and RPD2is provided as an example.

InFIG.3, the source/drain contacts135athrough135jextend in the X-direction, and the metal lines150athrough150kare formed in the first metallization layer and extend in the Y-direction.

The source/drain contacts135aand135boverlap the active structure115aand correspond to source and drain of the pull-up transistor WPU1. Furthermore, the source/drain contacts135band135coverlap the active structure115aand correspond to source and drain of the pull-up transistor WPU2. The source/drain contact135bis electrically connected to the metal line150bthrough the via145g. The source/drain contact135ais electrically connected to the gate structure130cthrough the via145a, the metal line150c, and the gate via140din sequence. The source/drain contact135cis electrically connected to the gate structure130bthrough the via145d, the metal line150f, and the gate via140cin sequence.

The source/drain contacts135eand135aoverlap the active structures115b_1and115b_2and correspond to source and drain of the pass-gate transistor WPG1. The source/drain contact135eis electrically connected to the metal line150ethrough the via145c. Furthermore, the source/drain contacts135aand135hoverlap the active structures115b_1and115b_2and correspond to source and drain of the pull-down transistor WPD1. The source/drain contact135ais shared by the pull-up transistor WPU1, the pass-gate transistor WPG1, and the pull-down transistor WPD1. The source/drain contact135his electrically connected to the metal line150gthrough the via145h.

The source/drain contacts135hand135coverlap the active structures115b_1and115b_2and correspond to source and drain of the pull-down transistor WPD2. The source/drain contact135cis shared by the pull-up transistor WPU2, the pass-gate transistor WPG2, and the pull-down transistor WPD2. Furthermore, the source/drain contacts135cand135doverlap the active structures115b_1and115b_2and correspond to source and drain of the pass-gate transistor WPG2. The source/drain contact135dis electrically connected to the metal line150dthrough the via145b.

The source/drain contacts135fand135goverlap the active structures115c_1and115c_2and correspond to source and drain of the pass-gate transistor RPG1. The source/drain contact135fis electrically connected to the metal line150ithrough the via145e. Furthermore, the source/drain contacts135gand135hoverlap the active structures115c_1and115c_2and correspond to source and drain of the pull-down transistor RPD1. The source/drain contact135gis shared by the pass-gate transistor RPG1and the pull-down transistor RPD1.

The source/drain contacts135hand135ioverlap the active structures115c_1and115c_2and correspond to source and drain of the pull-down transistor RPD2. The source/drain contact135his a longer contact shared by the pull-down transistors RPD1and RPD2, and the pull-down transistors WPD1and WPD2. Furthermore, the source/drain contacts135iand135joverlap the active structures115c_1and115c_2and correspond to source and drain of the pass-gate transistor RPG2. The source/drain contact135jis electrically connected to the metal line150hthrough the via145f. The source/drain contact135iis shared by the pass-gate transistor RPG2and the pull-down transistor RPD2.

The metal lines150athrough150kare formed in the first metallization layer that is the lowest level metallization layer. The metal line150ifunctions as the first read bit line RBL1, and the metal line150hfunctions as the second read bit line RBL2for the memory cell10A. In some embodiments, the memory cells10A arranged in the same column of the memory array share the same first read bit line RBL1through the metal line150iand the same second read bit line RBL2through the metal line150h.

The metal line150bfunctions as the VDD conductor and the metal line150gfunctions as the VSS conductor for the memory cell10A. In this embodiment, the VSS conductor is adjacent the second read bit line RBL2, and is disposed between the VDD conductor and the second read bit line RBL2. In some embodiments, the memory cells10A arranged in the same column of the memory array share the same VDD conductor through the metal line150band the same VSS conductor through the metal line150g.

The metal line150afunctions as a landing pad for the write word line WWL. The metal line150dfunctions as a landing pad for the write bit line WBL, and the metal line150efunctions as a landing pad for the write bit line WBLB. The metal line150jfunctions as a landing pad for the first read word line RWL1, and the metal line150kfunctions as a landing pad for the second read word line RWL2.

The memory cell10A has a cell width of X1measured along the X-direction and a cell height of Y1measured along the Y-direction. In such embodiments, the cell width X1is greater than the cell height Y1. In some embodiments, a memory macro is formed but repeating and abutting memory cells having a configuration identical or mirrored-identical to the memory cell10A. Thus, the cell width X1is also referred to as a cell pitch along the X-direction, and the cell height Y1is also referred to as a cell pitch along the Y-direction.

FIG.4Ashows a top view of the memory cell10A ofFIG.3, with all the depictions regarding components over the first metallization layer, in accordance with some embodiments of the disclosure.FIG.4Bshows a top view of the memory cell10A ofFIG.4A, with all the depictions regarding components under the third metallization layer, andFIG.4Cshows a top view of the memory cell10A ofFIG.4A, with all the depictions regarding components over the second metallization layer.

InFIGS.4A through4C, the same components in memory cell10A are given the same reference numbers, and a detailed description thereof is thus omitted. Some components of memory cell10A ofFIGS.4A through4Cthat are the same to those in the memory cell10A ofFIG.3may be omitted, or depicted in dotted lines, or not labeled for clarity.

InFIG.4B, the metal lines160athrough160gare formed in the second metallization layer and extend in the X-direction. The metal line160cis wider than the metal lines160a,160b,160dthrough160g. The vias155athrough155gare formed in the first via layer between the first and second metallization layers. The vias165athrough165hare formed in the second via layer over the second metallization layer.

The metal line150ais electrically connected to the metal line160cthrough the via155a. The metal line160cfunctions as the write word line WWL for the memory cell10A. Moreover, the write word line WWL has lower metal resistance due to wider metal width. In some embodiments, the memory cells10A arranged in the same row of the memory array share the same write word line WWL through the metal line160c.

The metal line160bis electrically connected to the metal line150g(VSS conductor) through the via155d, and the metal line160dis electrically connected to the metal line150g(VSS conductor) through the via155e. The metal line160ais electrically connected to the metal line150ethrough the via155b. In this embodiment, the metal line160afunctions as a landing pad for the write bit line WBLB. The metal line160eis electrically connected to the metal line150dthrough the via155c. In this embodiment, the metal line160efunctions as a landing pad for the write bit line WBL. The metal line160gis electrically connected to the metal line150kthrough the via155f. The metal line160fis electrically connected to the metal line150jthrough the via155g. The metal line160ffunctions as a landing pad for the first read word line RWL1, and the metal line160gfunctions as a landing pad for the second read word line RWL2.

InFIG.4C, the metal lines170athrough160fare formed in the third metallization layer and extend in the Y-direction. The metal lines170band170dare wider than the metal lines170a,170c,170eand170f. The vias165athrough165hare formed in the second via layer between the second and third metallization layers. The metal lines180athrough180dare formed in the fourth metallization layer and extend in the X-direction. The vias175athrough175fare formed in the third via layer between the third and fourth metallization layers.

The metal line170ais electrically connected to the metal lines160band160dofFIG.4Bthrough the vias165aand165b, respectively. Moreover, the metal line170ais further electrically connected to the metal lines180aand180dthrough the vias175aand175b, respectively. The metal line170bis electrically connected to the metal line160eofFIG.4Bthrough the via165c. The metal line170bfunctions as the write bit line WBL for the memory cell10A. Moreover, the write bit line WBL has lower metal resistance due to wider metal width. In some embodiments, the memory cells10A arranged in the same column of the memory array share the same write bit line WBL through the metal line170b.

The metal line170cis electrically connected to the metal lines160band160dofFIG.4Bthrough the vias165dand165f, respectively. Moreover, the metal line170cis further electrically connected to the metal lines180aand180dthrough the vias175cand175d, respectively. The metal line170dis electrically connected to the metal line160aofFIG.4Bthrough the via165e. The metal line170dfunctions as the write bit line WBLB for the memory cell10A. Moreover, the write bit line WBLB has lower metal resistance due to wider metal width. In some embodiments, the memory cells10A arranged in the same column of the memory array share the same write bit line WBLB through the metal line170d.

The metal lines170aand170cfunction as the VSS conductors for the memory cell10A. In the third metal line layer, the write bit line WBL (i.e., the metal line170b) is disposed between the two VSS conductors (i.e., the metal lines170aand170c). Moreover, the write bit line WBL (i.e., the metal line170b) is separated from the write bit line WBLB (i.e., the metal line170d) by the VSS conductor (i.e., the metal line170c). In other words, the metal line170cis disposed between the metal lines170band170d.

The metal line170eis electrically connected to the metal line160fofFIG.4Bthrough the via165g. Moreover, the metal line170eis further electrically connected to the metal line180bthrough the via175e. The metal line180bfunctions as the first read word line RWL1for the memory cell10A. In some embodiments, the memory cells10A arranged in the same row of the memory array share the same first read word line RWL1through the metal line180b.

The metal line170fis electrically connected to the metal line160gofFIG.4Bthrough the via165h. Moreover, the metal line170fis further electrically connected to the metal line180cthrough the via175f. The metal line180cfunctions as the second read word line RWL2for the memory cell10A. In some embodiments, the memory cells10A arranged in the same row of the memory array share the same second read word line RWL2through the metal line180c.

The metal lines180aand180dfunction as the VSS conductors for the memory cell10A. In the fourth metal line layer, the first read word line RWL1(i.e., the metal line180b) and the second read word line RWL2(i.e., the metal line180c) are disposed between the two VSS conductors (i.e., the metal lines180aand180d). In other words, the first read word line RWL1and the second read word line RWL2are surrounded by the two VSS conductors.

In the interconnect structure of the memory cell10A, the vias and metal lines corresponding to the supply voltage VDD form a VDD power mesh in the semiconductor device100A. Moreover, the vias and metal lines corresponding to the ground VSS form a VSS power mesh in the semiconductor device100A.

In SRAM application, the cell structure of the memory cell10A can meet both high density (i.e., fewer active structure regions and fewer metal lines in each layer) and high speed (lower RC delay for both bit lines and word lines of read and write ports). Furthermore, the first read bit line RBL1and the second read bit line RBL2are arranged in the lowest metallization layer, thus decreasing the capacitance of the first read bit line RBL1and the second read bit line RBL2, so as to increase the read port speed. On the other hand, the write bit lines WBL and WBLB are arranged in the higher metallization layer to obtain lower resistance, so as to improve the write margin for the memory cell10A. In general, the write margin is dominated by cell device setting (e.g., the ratio of turned-on current of the write pass-gate transistor to the write pull-up transistor) and the write bit-line resistance.

FIG.5Ashows a cross sectional view of the semiconductor device100A along a line A-AA inFIGS.3and4A through4C, in accordance with some embodiments of the disclosure. As described above, the memory cell10A has a cell height (or cell pitch) of Y1measured along the Y-direction. InFIG.5A, the cross sectional view of the pull-up transistors WPU1and WPU2are illustrated, and the pull-up transistors WPU1and WPU2are P-type Fin FETs. In this embodiment, the cell height Y1is the same as 4 times the contacted poly pitch (CPP), i.e., 4 times the gate pitch for the gate structures130athrough130f.

The N-type well region110ais formed over the substrate105. The substrate105may contains a semiconductor material, such as bulk silicon (Si). In some other embodiments, the substrate105may include other semiconductors such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate105may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GOI) structure. The isolation feature120is over the N-type well region110a.

The active structure115ais formed in the N-type well region110a. In some embodiments, the source/drain feature118is a source/drain region formed by the epitaxially-grown material. In some embodiments, for an N-type transistor, the epitaxially-grown materials may include SiP, SiC, SiPC, SiAs, Si, or a combination thereof. In some embodiments, for a P-type transistor, the epitaxially-grown materials may include SiGe, SiGeC, Ge, Si, a boron-doped SiGe, boron and carbon doped SiGe, or a combination thereof. Source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context.

In the memory cell10A, each of the gate structures130athrough130fincludes the gate feature (e.g., gate electrode)132, the gate dielectric layer134, the gate spacer136and the gate top dielectric layer138. In some embodiments, the gate feature132may include polysilicon or work function metal. The work function metal includes TiN, TaN, TiAl, TiAlN, TaAl, TaAlN, TaAlC, TaCN, WNC, Co, Ni, Pt, W, combinations thereof, or other suitable material.

In some embodiments, the gate feature132may include a capping layer, a barrier layer, an n-type work function metallization layer, a p-type work function metallization layer, and a fill material (not shown). In some embodiments, the P-type transistors and the N-type transistors are formed by the same work function material. In some embodiments, the P-type transistors and the N-type transistors are made of different work function materials.

The gate spacers136are on sidewalls of the gate dielectric layer134. The gate spacers136may include multiple dielectric materials and be selected from a group consisting of silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), carbon doped oxide, nitrogen doped oxide, porous oxide, air gap, or a combination thereof. In some embodiments, the gate spacers136may include a single layer or a multi-layer structure.

The gate top dielectric layer138is over the gate dielectric layer134and the gate feature132. The gate top dielectric layer138is used for contact etch protection layer. The material of gate top dielectric layer138is selected from a group consisting of oxide, SiOC, SiON, SiOCN, nitride base dielectric, metal oxide dielectric, Hf oxide (HfO2), Ta oxide (Ta2O5), Ti oxide (TiO2), Zr oxide (ZrO2), Al oxide (Al2O3), Y oxide (Y2O3), combinations thereof, or other suitable material.

The via145gis formed in the inter-layer dielectric (ILD)137, and the metal line150bis electrically connected to the source/drain contact135bof the pull-up transistors WPU1and WPU2through the via145g. The metal lines formed in the first through fourth metallization layers and the vias formed in the first through three via layers are formed in an inter-metal dielectric (IMD)152. In this embodiment, the metal line160cis formed over the via145gand is electrically separated from the via145g. In such embodiments, the metal line150bextends in the Y-direction and overlaps the pull-up transistors WPU1and WPU2.

FIG.5Bshows a cross sectional view of the semiconductor device100A along a line B-BB inFIGS.3and4A through4C, in accordance with some embodiments of the disclosure. As described above, the memory cell10A has a cell height (or cell pitch) of Y1measured along the Y-direction. InFIG.5B, the cross sectional view of the pull-down transistors WPD1and WPD2and the pass-gate transistors WPG1and WPG2are illustrated, and the pull-down transistors WPD1and WPD2and the pass-gate transistors WPG1and WPG2are N-type transistors.

The P-type well region110bis formed over the substrate105. The active structure115b_1is formed in the P-type well region110b. The gate structures130athrough130dare formed over the active structure115b_1.

The metal line170cextends in the Y-direction and overlaps the pull-down transistors WPD1and WPD2and the pass-gate transistors WPG1and WPG2. In this embodiment, the metal line170is electrically connected to the metal lines180aand180dthrough the vias175cand175d, respectively. Furthermore, the metal line170is further electrically connected to the metal lines160band160dthrough the via165dand165f, respectively.

FIG.5Cshows a cross sectional view of the semiconductor device100A along a line C-CC inFIGS.3and4A through4C, in accordance with some embodiments of the disclosure. As described above, the memory cell10A has a cell width (or cell pitch) of X1measured along the X-direction. InFIG.5C, the cross sectional view of the pull-up transistor WPU1, and the pull-down transistors WPD1and RPD2are illustrated, and the pull-down transistors WPD1and RPD2are N-type transistors and the pull-up transistor WPU1is P-type transistor. In the X-direction, less active structures (lower down to 3) are used in the memory cell10A, thereby having highly capability for cell scaling.

The P-type well region110band the N-type well region110aare formed over the substrate105. The active structure115ais formed on the N-type well region110a, and the active structures115b_1and115b_2and the active structures115c_1and115c_2are formed on the P-type well region110b. The active structures115a,115b_1,115b_2,115c_1and115c_2are separated from each other by the isolation feature120(e.g., the STI).

The gate feature132is formed over the gate dielectric layer134and is positioned over a top surface of the active structures115a,115b_1,115b_2,115c_1and115c_2. Moreover, the gate end dielectrics139are formed on opposite sides of the gate feature132. The active structures115aoverlapping the gate feature132may serve as a channel region of the pull-up transistor WPU2. Each of the active structures115b_1and115b_2overlapping the gate feature132may serve as a channel region of the pull-down transistor WPD2. Furthermore, each of the active structures115c_1and115c_2overlapping the gate feature132may serve as a channel region of the pull-down transistor WRD2. In some embodiments, the gate feature132is made of conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials.

The gate dielectric layer134may be a single layer or multiple layers. The gate top dielectric layer138is over the gate dielectric layer134and the gate feature132.

The gate dielectric layer134is made of silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), dielectric material(s) with high dielectric constant (high-k), or a combination thereof. In some embodiments, the gate dielectric layer134is deposited by a plasma enhanced chemical vapor deposition (PECVD) process or by a spin coating process. The high dielectric constant (high-k) material may be hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2) or another applicable material.

The gate via140dis formed over the gate feature132and extends through the top dielectric layer138and the ILD137. The gate feature132is electrically connected to the metal line150cthrough the gate via140d. In such embodiments, the metal line160cextends in the X-direction and overlaps the pull-up transistor WPU2and the pull-down transistors WPD2and RPD2. Furthermore, the metal line180calso extends in the X-direction and overlaps the pull-up transistor WPU2and the pull-down transistors WPD2and RPD2.

FIG.6shows is a top view of a memory cell10B in a semiconductor device100B, with all the depictions regarding components in and under the first metallization layer ofFIG.2, in accordance with some embodiments of the disclosure. Components in the memory cell10B that are the same or similar to those in the memory cell10A are given the same reference numbers, and a detailed description thereof is thus omitted. Some components of the memory cell10B that are the same or similar to those in the memory cell10A are not labeled for clarity. Moreover, the memory cell10B is an implementation of the memory cell10depicted inFIG.1.

The configuration of the memory cell10B is similar to the configuration of the memory cell10A inFIG.3, and the differences between the memory cell10B ofFIG.6and the memory cell10A ofFIG.3is that the positions of the metal lines150gand150hare interchanged, and the corresponding vias145hand145fare also moved. Furthermore, the corresponding vias connected to the upper metal lines, such as the vias155dand155einFIG.4B, are also moved. Therefore, the second read bit line RBL2(i.e., the metal line150h) is disposed between the VDD conductor (i.e., the metal line150b) and the VSS conductor (i.e., the metal line150g). Furthermore, the VSS conductor (i.e., the metal line150g) is disposed between the second read bit line RBL2(i.e., the metal line150h) and the first read bit line RBL1(i.e., the metal line150i).

FIG.7shows is a top view of a memory cell10C in a semiconductor device100C, with all the depictions regarding components in and under the first metallization layer ofFIG.2, in accordance with some embodiments of the disclosure. Components in the memory cell10C that are the same or similar to those in the memory cell10A are given the same reference numbers, and a detailed description thereof is thus omitted. Some components of the memory cell10C that are the same or similar to those in the memory cell10A are not labeled for clarity. Moreover, the memory cell10C is an implementation of the memory cell10depicted inFIG.1. In this embodiment, the transistors in the memory cell10C are gate-all-around field effect transistors (GAA FETs).

The configuration of the memory cell10C is similar to the configuration of the memory cell10A inFIG.3, and the differences between the memory cell10C ofFIG.7and the memory cell10A ofFIG.3is that the memory cell10C includes the active structures117athrough117cextending along the Y-direction.

The active structures117band117care formed in the P-type well region110b, and the active structure117ais formed in the N-type well region110a. In such embodiments, the active structures117athrough117care the nanostructures formed on the substrate.

In some embodiments, the nanostructures may also be referred to as channels, channel layers, nanosheets, or nanowires. The nanostructures may include a semiconductor material, such as silicon, germanium, silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, silicon germanium (SiGe), SiPC, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP. In some embodiments, the nanostructures include silicon for N-type GAA transistors. In other embodiments, the nanostructures include silicon germanium for P-type GAA transistors. In some embodiments, the nanostructures are all made of silicon, and the type of GAA transistors depend on work function metallization layer wrapping around the nanostructures.

The gate structure133aengages the active structure117bto form the pass-gate transistor WPG1. The gate structure133bengages the active structures117a,117band117cto form the pull-up transistor WPU1and the pull-down transistors WPD1and RPD1, respectively. The gate structure133cengages the active structures117a,117band117cto form the pull-up transistor WPU2and the pull-down transistors WPD2and RPD2, respectively. The gate structure133dengages the active structure117bto form the pass-gate transistor WPG2. The gate structure133eengages the active structure117cto form the pass-gate transistor RPG1. The gate structure133fengages the active structure117cto form the pass-gate transistor RPG2.

The memory cell10C has a cell width of X2measured along the X-direction and a cell height of Y2measured along the Y-direction. In some embodiments, a memory macro is formed but repeating and abutting memory cells having a configuration identical or mirrored-identical to the memory cell10C. Thus, the cell width X2is also referred to as a cell pitch along the X-direction, and the cell height Y2is also referred to as a cell pitch along the Y-direction. In some embodiments, the cell height Y2of the memory cell10C is equal to the cell height Y1of the memory cell10A, and the cell width X2of the memory cell10C is equal to the cell width X1of the memory cell10A. In this embodiment, the cell height Y2is the same as 4 times the contacted poly pitch (CPP), i.e., 4 times the gate pitch for the gate structures133athrough133f.

FIG.8shows a top view of the memory cell10C ofFIG.7, with all the depictions regarding components over the first metallization layer, in accordance with some embodiments of the disclosure.

The interconnect configuration of the memory cell10C is similar to that of the memory cell10A inFIG.4A, and the differences between the memory cell10C ofFIG.7and the memory cell10A ofFIG.4Ais that the memory cell10C includes the active structures117athrough117cextending along the Y-direction. In the memory cell10C, the same components as those in the memory cell10AFIG.4Aare given the same reference numbers, and a detailed description thereof is thus omitted.

In the first metallization layer of the semiconductor device100C ofFIG.8, the metal line150bfunctions as the VDD conductor and the metal line150gfunctions as the VSS conductor for the memory cell10C. The metal line150ifunctions as the first read bit line RBL1, and the metal line150hfunctions as the second read bit line RBL2for the memory cell10C.

In the second metallization layer of the semiconductor device100C ofFIG.8, the metal line160cfunctions as the write word line WWL for the memory cell10C.

In the third metallization layer of the semiconductor device100C ofFIG.8, the metal lines170aand170cfunction as the VSS conductors for the memory cell10C. The metal line170bfunctions as the write bit line WBL and the metal line170dfunctions as the write bit line WBLB for the memory cell10C.

In the fourth metallization layer of the semiconductor device100C ofFIG.8, the metal lines180aand180dfunction as the VSS conductors for the memory cell10C. The metal line180bfunctions as the first read word line RWL1and the metal line180cfunctions as the second read word line RWL2for the memory cell10C.

In SRAM application, the cell structure of the memory cell10C can meet both high density (i.e., fewer active structure regions and fewer metal lines in each layer) and high speed (lower RC delay for both bit lines and word lines of read and write ports). Furthermore, the first read bit line RBL1and the second read bit line RBL2are arranged in the lowest metallization layer, thus decreasing the capacitance of the first read bit line RBL1and the second read bit line RBL2, so as to increase the read port speed. On the other hand, the write bit lines WBL and WBLB are arranged in the higher metallization layer to obtain lower resistance, so as to improve the write margin for the memory cell10C.

FIG.9Ashows a cross sectional view of the semiconductor device100C along a line D-DD inFIG.7andFIG.8, in accordance with some embodiments of the disclosure. As described above, the memory cell10C has a cell height (or cell pitch) of Y2measured along the Y-direction. InFIG.9A, the cross sectional view of the pull-up transistors WPU1and WPU2are illustrated, and the pull-up transistors WPU1and WPU2are P-type GAA FETs.

FIG.9Bshows a cross sectional view of the semiconductor device100C along a line E-EE inFIG.7andFIG.8, in accordance with some embodiments of the disclosure. As described above, the memory cell10C has a cell height (or cell pitch) of Y2measured along the Y-direction. InFIG.9B, the cross sectional view of the pull-down transistors WPD1and WPD2and the pass-gate transistors WPG1and WPG2are illustrated, and the pull-down transistors WPD1and WPD2and the pass-gate transistors WPG1and WPG2are N-type GAA FETs.

FIG.9Cshows a cross sectional view of the semiconductor device100C along a line F-FF inFIG.7andFIG.8, in accordance with some embodiments of the disclosure. As described above, the memory cell10C has a cell width (or cell pitch) of X2measured along the Y-direction. InFIG.9C, the cross sectional view of the pull-up transistor WPU2, and the pull-down transistor WPD2and RPD2are illustrated.

As shown inFIGS.9A through9C, the gate top dielectric layers138are over the gate structures133athrough133f, the gate spacers136, and the nanostructures133. The material of the gate top dielectric layers138is discussed above.

The gate spacers136are on sidewalls of the gate structures133athrough133f, as shown inFIGS.9A and9B. The gate spacers136may include the top spacers and the inner spacers. The top spacers are over the nanostructures122and on top sidewalls of the gate structures133athrough133f. The top spacers may include multiple dielectric materials and be selected from a group consist of SiO2, Si3N4, carbon doped oxide, nitrogen doped oxide, porous oxide, air gap, or a combination thereof. The inner spacers may include a dielectric material having higher K value (dielectric constant) than the top spacers and be selected from a group consisting of silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), air gap, or a combination thereof.

The nanostructures122are wrapped by the gate structures133athrough133fto serve as channels or channel layers of the transistors in the memory cell10C. InFIGS.9A through9C, each GAA transistor has three nanostructures122vertically arranged (or stacked) in the Z-direction. In other embodiments, each GAA transistor may have more or fewer nanostructures122arranged vertically (or stacked) in the Z-direction.

In the memory cell10C, the active structures117athrough117cmay have different widths in the X-direction. In some embodiments, the widths of the active structures117athrough117care determined according to the channel width of the channel width corresponding to the respective nanostructures122.

As shown inFIG.9C, the nanostructures122of the pull-up transistor WPU2have a channel width W1in the X-direction, the nanostructures122of the pull-down transistor WPD2have a channel width W2in the X-direction, and the nanostructures122of the pull-down transistor RPD2have a channel width W3in the X-direction. In such embodiments, the channel widths W2and W3are greater than the channel width W1. The dimension ratio of the channel width W2to the channel width W1is about 1.2 to about 5. Moreover, the dimension ratio of the channel width W3to the channel width W2is about 0.75 to about 3.

Each source/drain feature118is disposed between two adjacent gate structures and contact the nanostructures122of the transistors, as shown inFIGS.9A and9B. Therefore, each source/drain feature118is shared by two adjacent gate structures. In some embodiments, the source/drain features118may be also referred to as common source/drain features. As described above, the source/drain features118is formed by the epitaxially-grown materials discussed above.

The ILD137and the IMD152may include one or more dielectric layers including dielectric materials, such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), a low-k dielectric material, other suitable dielectric material, or a combination thereof.

In some embodiments, the materials of the source/drain contact, the vias and metal lines in the memory cell10C are selected from a group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), platinum (Pt), aluminum (Al), copper (Cu), other conductive materials, or a combination thereof.

FIG.10shows is a top view of a memory cell10D in a semiconductor device100D, with all the depictions regarding components in and under the first metallization layer ofFIG.2, in accordance with some embodiments of the disclosure. Components in the memory cell10D that are the same or similar to those in the memory cell10C are given the same reference numbers, and a detailed description thereof is thus omitted. Some components of the memory cell10D that are the same or similar to those in the memory cell10C are not labeled for clarity. Moreover, the memory cell10D is an implementation of the memory cell10depicted inFIG.1.

The configuration of the memory cell10D is similar to the configuration of the memory cell10C inFIG.7, and the differences between the memory cell10D ofFIG.10and the memory cell10C ofFIG.7is that the positions of the metal lines150gand150hare interchanged, and the corresponding vias145hand145fare also moved. Furthermore, the corresponding vias connected to the upper metal lines, are also moved. Therefore, the second read bit line RBL2(i.e., the metal line150h) is disposed between the VDD conductor (i.e., the metal line150b) and the VSS conductor (i.e., the metal line150g). Furthermore, the VSS conductor (i.e., the metal line150g) is disposed between the second read bit line RBL2(i.e., the metal line150h) and the first read bit line RBL1(i.e., the metal line150i).

FIGS.11A and11Bshow the layout of a semiconductor device100E, in accordance with some embodiments of the disclosure. In the semiconductor device100E, two three-port memory cells are arranged in the same row and adjacent to each other. Furthermore, the two three-port memory cells have the same configuration as the memory cell10A ofFIGS.3A,4A through4C, and are therefore designated10A_1and10A_2. In other embodiments, the three-port memory cells have the same configuration as the memory cell10B,10C or10D in the disclosure.

FIG.11Ashows a top view of the memory cells10A_1and10A_2, with all the depictions regarding components in and under the first metallization layer ofFIG.2, in accordance with some embodiments of the disclosure.FIG.11Bshows a top view of the memory cells10A_1and10A_2, with all the depictions regarding components over the first metallization layer, in accordance with some embodiments of the disclosure.

In the semiconductor device100E, the two adjacent memory cells10A_1and10A_2are arranged in mirror symmetry along the Y-direction. In some embodiments, the two adjacent memory cells10A_1and10A_2are arranged in mirror symmetry along the X-direction.

The N-type well region110ais at the middle of memory cells10A_1and10A_2. The pull-up transistors WPU1and WPU2of the memory cells10A_1and10A_2are formed over the N-type well region110a. Moreover, the source/drain contact135b, the metal line150aand the metal line170aare shared by the pull-up transistors WPU1and WPU2of the memory cells10A_1and10A_2.

The gate structure130ais shared by the pass-gate transistors WPG1of the memory cells10A_1and10A_2, and the gate structure130dis shared by the pass-gate transistors WPG2of the memory cells10A_1and10A_2.

The first read bit line RBL1and the second read bit line RBL2are electrically connected to the corresponding transistors of the memory cells in the same column of the semiconductor device100E through respective metal lines extending in the Y-direction in the first metallization layer. For example, as shown inFIG.11A, the metal lines150i_1and150h_1function as the first read bit line RBL1and the second read bit line RBL2of the memory cells arranged in the same column as the memory cell10A_1. Moreover, the metal lines150i_2and150h_2function as the first read bit line RBL1and the second read bit line RBL2of the memory cells arranged in the same column as the memory cell10A_2.

The write bit lines WBL and WBLB are electrically connected to the corresponding transistors of the memory cells in the same column of the semiconductor device100E through respective metal lines extending in the Y-direction in the third metallization layer. For example, as shown inFIG.11B, the metal lines170b_1and170d_1function as the write bit lines WBL and WBLB of the memory cells arranged in the same column as the memory cell10A_1. Furthermore, the metal lines170b_2and170d_2function as the write bit lines WBL and WBLB of the memory cells arranged in the same column as the memory cell10A_2.

The write word line WWL is electrically connected to the corresponding transistors of the memory cells in the same row of the semiconductor device100E through the same metal line extending in the X-direction in the third second layer. For example, as shown inFIG.11B, the metal line160cis shared by the memory cells10A_1and10A_2, and the metal line160cfunction as the write word line WWL of the memory cells that arranged in the same row as the memory cells10A_1and10A_2.

The first read word line RWL1and the second read word line RWL2are electrically connected to the corresponding transistors of the memory cells in the same row of the semiconductor device100E through the respective metal lines extending in the X-direction in the fourth second layer. For example, as shown inFIG.11B, the metal line180bis shared by the memory cells10A_1and10A_2, and the metal line180bfunction as the first read word line RWL1of the memory cells that arranged in the same row as the memory cells10A_1and10A_2. Moreover, the metal line180cis shared by the memory cells10A_1and10A_2, and the metal line180cfunction as the second read word line RWL2of the memory cells that arranged in the same row as the memory cells10A_1and10A_2.

The present disclosure provides front-end-of-line (FEOL) process, middle-end-of-line (MEOL) process, and back-end-of-line (BEOL) process for fabricating a memory cell that can be implemented within a data storage device. The memory cell of the present disclosure represents a multiple port memory cell having at least three ports, such as a write-port, a first read-port, and a second read-port. The disclosed FEOL process is used to form semiconductor devices of the memory cell onto diffusion layers and polysilicon layers of a semiconductor layer stack. The disclosed MEOL process is used to form interconnections, such as one or more vias and/or one or more contacts to provide some examples, between the semiconductor devices and metallization layers of the semiconductor layer stack. The disclosed BEOL process is used to form the at least three ports onto the metallization layers of the semiconductor layer stack.

FIG.12shows a method for manufacturing a semiconductor device, in accordance with some embodiments of the disclosure, and the semiconductor device includes the memory cell of the embodiments.

In operation S310, the 10 transistors of the 3-port memory cell are formed in the FEOL and MEOL processes. As described above, the 3-port memory cell includes a write port circuit having data nodes ND and NDB, a first read port circuit coupled to the data node NDB, and a second read port circuit coupled to the data node ND. Furthermore, the write port circuit includes the pull-up transistors WPU1and WPU2, the pull-down transistors WPD1and WPD2, and the pass-gate transistors WPG1and WPG2. The first read port circuit includes the pass-gate transistor RPG1and the pull-down transistor RPD1, and the second read port circuit includes the pass-gate transistor RPG2and the pull-down transistor RPD2.

The transistors of the first and second read port circuits are formed on the same active structure extending in the first direction. The N-type transistors and the P-type transistors of the write port circuit are formed on the other two active structures extending in the first direction, respectively. The memory cells of the embodiments have fully symmetry layout for cell stability improvement and device match.

Moreover, the pull-down transistors WPD1and RPD1and the pull-up transistor WPU1share one gate structure extending in a second direction, while the pull-down transistors WPD2and RPD2and the pull-up transistor WPU2share another gate structure extending in the second direction, and the two gate structures are adjacent to each other. The first second direction is perpendicular to the second direction.

In some embodiments, the 10 transistors are formed by fin-base transistors, the transistors may be single-fin, multiple fins, or combination. In some embodiments, the 10 transistors are formed by the vertically stacked gate-all-around (VS-GAA) horizontal nanostructure transistors, and the transistors may be single channel, or multiple vertically stacked nano-sheet (or nano-wire), or combination.

In operation S320, the read bit lines RBL1and RBL2are formed in a first metallization layer over the transistors during the BEOL process. In the first metallization layer, the read bit lines RBL1and RBL2extend in the first direction. Furthermore, the memory cells arranged in the same column of array may share the same read bit lines RBL1and RBL2.

In operation S330, the write word line WWL is formed in a second metallization layer over the first metallization layer during the BEOL process. In the second metallization layer, the write word line WWL extends in the second direction. Furthermore, the memory cells arranged in the same row of array may share the same write word line WWL.

In operation S340, the write bit lines WBL and WBLB are formed in a third metallization layer over the second metallization layer during the BEOL process. In the third metallization layer, the write bit lines WBL and WBLB extend in the first direction. Furthermore, the memory cells arranged in the same column of array may share the same write bit lines WBL and WBLB.

In operation S350, the read word lines RWL1and RWL2are formed in a fourth metallization layer over the third metallization layer during the BEOL process. In the fourth metallization layer, the read word lines RWL1and RWL2extend in the second direction. Furthermore, the memory cells arranged in the same row of array may share the same read word lines RWL1and RWL2.

Embodiments of semiconductor devices are provided. The semiconductor devices include the 3-port memory cells arranged in a memory array. In each memory cell, all transistors of the first and second read port circuits share at least one first active structure. The N-type transistors of the write port circuit share at least one second active structure, and the P-type transistors of the write port circuit share a third active structure. Therefore, the fewer active structure regions and fewer metal lines in each layer are used in the memory cells. Furthermore, the write word line WWL and the read word lines RWL1and RWL2are arranged to different metal layers in the memory cell, thereby obtaining wider metal width and space for RC delay improvement.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a three-port memory cell. The three-port memory cell includes a write port circuit, a first read port circuit and a third read port circuit. The write port circuit is configured to perform a write function according to a write word line, a first write bit line and a second write bit line. The first read port circuit includes a first read pass-gate transistor and a first read pull-down transistor connected in series, and is configured to perform a first read function according to a first read bit line and a first read word line. The second read port circuit includes a second read pass-gate transistor and a second read pull-down transistor connected in series, and is configured to perform a second read function according to a second read bit line and a second read word line. The first and second read pass-gate transistors and the first and second read pull-down transistors share a first active structure extending in a first direction. The first read bit line and the second read bit line extend in the first direction in a first metallization layer over the first active structure, and the first write bit line and the second write bit line extend in the first direction in a second metallization layer over the first metallization layer. The write word line extends in a second direction in a third metallization layer, and the first read word line and the second read word line extend in the second direction in a fourth metallization layer. The first direction is perpendicular to the second direction, and the third and fourth metallization layers are different from the first and second metallization layers.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a three-port memory cell. The three-port memory cell includes a write port circuit, a first read port circuit, and a second read port circuit. The write port circuit is configured to perform a write function according to a write word line, a first write bit line and a second write bit line. The first read port circuit includes a first read pass-gate transistor and a first read pull-down transistor connected in series between a ground and a first read bit line, and is configured to perform a first read function according to and a first read word line. The second read port circuit includes a second read pass-gate transistor and a second read pull-down transistor connected in series between a ground and a second read bit line, and is configured to perform a second read function according to a second read word line. The first and second read pass-gate transistors and the first and second read pull-down transistors share a first active structure extending in a first direction. The first and second write pass-gate transistors share a second active structure extending in the first direction. The first and second write pass-gate transistors share a third active structure extending in the first direction. The second active structure is disposed between the first and third active structures. The first read bit line and the second read bit line extend in the first direction in a first metallization layer over the first active structure, and the first write bit line and the second write bit line extend in the first direction in a second metallization layer over the first metallization layer.

In some embodiments, a method for manufacturing a semiconductor device is provided. A three-port memory cell is formed. The three-port memory cell includes a write port circuit, a first read port circuit including a first read pass-gate transistor and a first read pull-down transistor connected in series, and a second read port circuit including a second read pass-gate transistor and a second read pull-down transistor connected in series. The first and second read pass-gate transistors and the first and second read pull-down transistors share a first active structure extending in a first direction. A first read bit line and a second read bit line extending in the first direction are formed in a first metallization layer over the first active structure. A write word line extending in a second direction is formed in a second metallization layer over the first metallization layer. A first write bit line and a second write bit line extending in the first direction are formed in a third metallization layer over the second metallization layer. A first read word line and a second read word line extending in the second direction are formed in a fourth metallization layer over the third metallization layer. The write port circuit is configured to perform a write function according to the write word line, the first write bit line and the second write bit line. The first read port circuit is configured to perform a first read function according to the first read bit line and the first read word line. The second read port circuit is configured to perform a second read function according to the second read bit line and the second read word line.