NON-VOLATILE MEMORY CELL OF ARRAY STRUCTURE AND ASSOCIATED CONTROLLING METHOD

A non-volatile memory cell includes a select transistor and a memory transistor. The first drain/source terminal of the select transistor is connected with a first control terminal. The second drain/source terminal of the select transistor is connected with the first drain/source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain/source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain/source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.

FIELD OF THE INVENTION

The present invention relates to an array structure, and more particularly to a non-volatile memory cell of an array structure and an associated controlling method for the non-volatile memory cell.

BACKGROUND OF THE INVENTION

Non-volatile memories have been widely used in a variety of electronic products. After the supplied power is interrupted, the data stored in the non-volatile memory is still retained.

Generally, the non-volatile memory comprises an array structure. The array structure comprises plural non-volatile memory cells. The non-volatile memory cell comprises a storage device. The storage device comprises a charge storage layer. According to the number of stored charges in the charge storage layer, the storage state of the non-volatile memory cell can be determined. For example, the storage device is a charge-trap transistor or a floating gate transistor.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides an array structure. The array structure includes a first non-volatile memory cell. The first non-volatile memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure and a second gate structure. The first doped region, the second doped region and the third doped region are formed under a surface of the well region. The first doped region is connected with a first control terminal. The third doped region is connected with a second control terminal. The first gate structure is formed over the surface of the well region and arranged between the first doped region and the second doped region. The first gate structure is connected with a first select gate terminal. The well region, the first doped region, the second doped region and the first gate structure are collaboratively formed as a first select transistor. The second gate structure is formed over the surface of the well region and arranged between the second doped region and the third doped region. The second gate structure is connected with a first memory gate terminal. The well region, the second doped region, the third doped region and the second gate structure are collaboratively formed as a first memory transistor. The second gate structure comprises a first charge storage layer. When a program action is performed on the first non-volatile memory cell, the second control terminal receives a first voltage, the first control terminal receives a second voltage, the first select gate terminal receives an on voltage, and the first memory gate terminal receives a program operation voltage. When the first select transistor is turned on, the second voltage is transmitted from the first doped region to the second doped region. Consequently, a tapered channel is formed between the second doped region and the third doped region. The tapered channel is pinched off near the second doped region, and plural hot carriers near a pinch off point are injected into the first charge storage layer of the second gate structure. Consequently, the first non-volatile memory cell is in a programmed state.

Another embodiment of the present invention provides an array structure. The array structure includes a first non-volatile memory cell. The first non-volatile memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure and a second gate structure. The first doped region, the second doped region and the third doped region are formed under a surface of the well region. The first doped region is connected with a first control terminal. The third doped region is connected with a second control terminal. The first gate structure is formed over the surface of the well region and arranged between the first doped region and the second doped region. The first gate structure is connected with a first select gate terminal, and the well region, the first doped region, the second doped region and the first gate structure are collaboratively formed as a first select transistor. The second gate structure is formed over the surface of the well region and arranged between the second doped region and the third doped region. The second gate structure is connected with a first memory gate terminal. The well region, the second doped region, the third doped region and the second gate structure are collaboratively formed as a first memory transistor. The second gate structure comprises a first charge storage layer. When a read action is performed on the first non-volatile memory cell, the well region receives a well voltage, the second control terminal receives a first voltage, the first control terminal receives a second voltage, the first select gate terminal receives an on voltage, and the first memory gate terminal receives a read operation voltage. The first voltage is higher than the second voltage. The well voltage is equal to the first voltage. When the first select transistor is turned on, the first non-volatile memory cell generates a read current. A storage state of the first non-volatile memory cell is determined according to a magnitude of the read current.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG.1is a schematic cross-sectional view illustrating an array structure with plural non-volatile memory cells according to an embodiment of the present invention. As shown inFIG.1, the array structure comprises two non-volatile memory cells Cell1and Cell2. For brevity, the non-volatile memory cells Cell1and Cell2are referred as memory cells. The memory cell Cell1comprises a select transistor MS1and a memory transistor MM1. The memory cell Cell2comprises a select transistor MS2and a memory transistor MM2. The memory transistors MM1and MM2are storage devices of the memory cells. For example, the memory transistors MM1and MM2are charge-trap transistors or floating gate transistors.

As shown inFIG.1, plural gate structures10,20,30and40are formed over a surface of an N-well region NW in a semiconductor substrate Sub. The gate structure10comprises a gate dielectric layer11and a gate layer13. The gate structure20comprises a charge storage structure26and a gate layer27. The charge storage structure26further comprises a gate dielectric layer21, a charge storage layer23and an isolation layer25. The gate structure30comprises a gate dielectric layer31and a gate layer33. The gate structure40comprises a charge storage structure46and a gate layer47. The charge storage structure46further comprises a gate dielectric layer41, a charge storage layer43and an isolation layer45.

Please refer toFIG.1again. In the gate structure10, the gate dielectric layer11is formed over the N-well region NW, and the gate layer13is formed over the gate dielectric layer11to cover the gate dielectric layer11. In the gate structure20, the gate dielectric layer21is formed over the N-well region NW, the charge storage layer23is formed over the gate dielectric layer21to cover the gate dielectric layer21, the isolation layer25is formed over the charge storage layer23to cover the charge storage layer23, and the gate layer27is formed over the isolation layer25to cover the isolation layer25. In the gate structure30, the gate dielectric layer31is formed over the N-well region NW, and the gate layer33is formed over the gate dielectric layer31to cover the gate dielectric layer31. In the gate structure40, the gate dielectric layer41is formed over the N-well region NW, the charge storage layer43is formed over the gate dielectric layer41to cover the gate dielectric layer41, the isolation layer45is formed over the charge storage layer43to cover the charge storage layer43, and the gate layer47is formed over the isolation layer45to cover the isolation layer45. Furthermore, plural spacers (not shown) are formed on sidewalls (not shown) of the gate structures10,20,30and40.

For example, the gate layers13,27,33and47are polysilicon layers. In addition, the gate dielectric layers11,21,31and41are oxide layers, the isolation layers25and45are oxide layers, and the charge storage layers23and43are nitride layers or polysilicon layers. In other words, each of the charge storage structures26and46is an oxide-nitride-oxide (ONO) structure or an oxide-polysilicon-oxide structure. In case that the charge storage structures26and46are oxide-nitride-oxide (ONO) structures, the memory transistors MM1and MM2are charge-trap transistors. In case that the charge storage structures26and46are oxide-polysilicon-oxide structures, the memory transistors MM1and MM2are floating gate transistors.

Furthermore, plural p-doped regions51,53,55,57and59are formed under the surface of the N-well region NW. The gate structure10is located over the region between the p-doped region51and the p-doped region53. The p-doped region51is located beside a first side of the gate structure10and under the surface of the N-well region NW. The p-doped region53is located beside a second side of the gate structure10and under the surface of the N-well region NW. The gate structure20is located over the region between the p-doped region53and the p-doped region59. The p-doped region53is located beside a first side of the gate structure20and under the surface of the N-well region NW. The p-doped region59is located beside a second side of the gate structure20and under the surface of the N-well region NW. The gate structure30is located over the region between the p-doped region55and the p-doped region57. The p-doped region55is located beside a first side of the gate structure30and under the surface of the N-well region NW. The p-doped region57is located beside a second side of the gate structure30and under the surface of the N-well region NW. The gate structure40is located over the region between the p-doped region57and the p-doped region59. The p-doped region57is located beside a first side of the gate structure40and under the surface of the N-well region NW. The p-doped region59is located beside a second side of the gate structure40and under the surface of the N-well region NW.

As shown inFIG.1, the N-well region NW, the gate structure10, the p-doped region51and the p-doped region53are collaboratively formed as the select transistor MS1. The N-well region NW, the gate structure20, the p-doped region53and the p-doped region59are collaboratively formed as the memory transistor MM1. The N-well region NW, the gate structure30, the p-doped region55and the p-doped region57are collaboratively formed as the select transistor MS2. The N-well region NW, the gate structure40, the p-doped region57and the p-doped region59are collaboratively formed as the memory transistor MM2. The select transistors MS1and MS2and the memory transistors MM1and MM2are p-type transistors. Consequently, in the memory cell Cell1, the p-doped region53is a shared p-doped region of the select transistor MS1and the memory transistor MM1. Similarly, in the memory cell Cell2, the p-doped region57is a shared p-doped region of the select transistor MS2and the memory transistor MM2. In addition, the p-doped region59is a shared p-doped region of the memory transistor MM1and the memory transistor MM2.

The p-doped regions51,59and55are electrically connected with control terminals TC1, TC2and TC3, respectively. The gate layers13and33are electrically connected with select gate terminals TSG1and TSG2, respectively. The gate layers27and47are electrically connected with the memory gate terminals TMG1and TMG2, respectively.

In the memory cell Cell1, the first drain/source terminal of the select transistor MS1is connected with the control terminal TC1, the second drain/source terminal of the select transistor MS1is connected with the first drain/source terminal of the memory transistor MM1, the gate terminal of the select transistor MS1is connected with the select gate terminal TSG1, the second drain/source terminal of the memory transistor MM1is connected with the control terminal TC2, and the gate terminal of the memory transistor MM1is connected with the memory gate terminal TMG1. In the memory cell Cell2, the first drain/source terminal of the select transistor MS2is connected with the control terminal TC3, the second drain/source terminal of the select transistor MS2is connected with the first drain/source terminal of the memory transistor MM2, the gate terminal of the select transistor MS2is connected with the select gate terminal TSG2, the second drain/source terminal of the memory transistor MM2is connected with the control terminal TC2, and the gate terminal of the memory transistor MM2is connected with the memory gate terminal TMG2. That is, the control terminal TC2is shared by the memory cell Cell1and the memory cell Cell2.

By providing proper bias voltages to the terminals TC1, TC2, TC3, TSG1, TSG2, TMG1and TMG2, a program action can be performed on any of the memory cells Cell1and Cell2. For example, in case that no carriers are stored in the memory transistor MM1of the memory cell Cell1, the memory cell Cell1is in an erased state. Whereas, in case that carriers are stored in the memory transistor MM1of the memory cell Cell1, the memory cell Cell1is in a programmed state. For example, the carriers are electrons or holes.

For allowing the normal operation of the array structure and preventing from the generation of the leakage current, the N-well voltage VNWreceived by the N-well region NW and each of the p-doped regions51,53,55,57and59cannot be forward biased. That is, the N-well voltage VNWreceived by the N-well region NW is higher than or equal to the voltage received by each of the p-doped regions51,53,55,57and59. That is, the N-well voltage NNWreceived by the N-well region NW is higher than or equal to the voltage of the terminals TC1, TC2and TC3.

FIG.2Aschematically illustrates the bias voltages for performing a program action on the memory cell of the array structure according to a first embodiment of the present invention. When the program action is performed on the array structure, a first voltage V1is provided to the control terminals TC1and TC3, and a second voltage V2is provided to the control terminal TC2. The first voltage V1is higher than the second voltage V2. For example, the first voltage V1is equal to 5V, and the second voltage V2is equal to a ground voltage (e.g., 0V). In addition, the N-well voltage VNWreceived by the N-well region NW is equal to the first voltage V1. Since the N-well region NW is equal to the first voltage V1(e.g., 5V) and the p-doped region59receives the second voltage V2(e.g., 0V), there is a reverse bias between the N-well region NW and the p-doped region59. In other words, a wider depletion region70indicated as dotted lines is formed in the junction between the N-well region NW and the p-doped region59.

In addition, a program operation voltage VPOPis provided to the memory gate terminals TMG1and TMG2, an on voltage VONis provided to the select gate terminal TSG1, and an off voltage VOFFis provided to the select gate terminal TSG2. Consequently, the memory cell Cell1is the selected memory cell, and the memory cell Cell2is the non-selected memory cell. For example, the on voltage VONis 0V, the off voltage VOFFis 5V, and the program operation voltage VPOPis 4.5V.

Please refer toFIG.2Aagain. In the non-selected memory cell Cell2, the select gate terminal TSG2receives the off voltage VOFF. Consequently, the select transistor MS2is turned off, and no channel is formed between the p-doped regions55and57. In the memory transistor MM2, no channel is formed between the p-doped regions57and59. Consequently, the program action is unable to be performed on the non-selected memory cell Cell2, and the non-selected memory cell Cell2is maintained in the erased state.

In the selected memory cell Cell1, the select gate terminal TSG1receives the on voltage VON. Consequently, the select transistor MS1is turned on, and a p-channel61is formed between the p-doped regions51and53. Under this circumstance, the first voltage V1(e.g., 5V) received by the p-doped region51is transmitted to the p-doped region53. In the memory transistor MM1, the memory gate terminal TMG1receives the program operation voltage VPOP, the p-doped region59receives the ground voltage (0V), and the p-doped region53receives the first voltage V1(e.g., 5V). Since the first voltage V1(e.g., 5V) received by the p-doped region53is higher than the ground voltage (e.g., 0V) received by the p-doped region59, a tapered p-channel62is formed between the p-doped regions53and59. In addition, the p-channel62is pinched off near the p-doped region59.

Please refer toFIG.2Aagain. The voltage difference between the p-doped regions53and59is 5V, i.e., V1−V2=5V. In addition, an electric field is generated. In the p-channel62, the holes are accelerated by the electric field to acquire higher energy. In the pinch off point71of the p-channel62, the high-speed holes impact the depletion region70. Consequently, electron-hole pairs are generated in the depletion region70. Due to the attraction of the program operation voltage VPOP, the generated electrons are transferred through the gate dielectric layer21and stored into the charge storage layer23of the memory transistor MM1. Consequently, the selected memory cell Cell1is changed to the programmed state, and the program action is completed. Under this circumstance, a channel hot hole induced hot electron injection effect (also referred as a CHHIHEI effect) is generated.

However, in the non-selected memory cell Cell2, the memory gate terminal TMG2of the memory transistor MM2receives the same program operation voltage VPOP, and there is a reverse bias between the N-well region NW and the p-doped region59. Consequently, a band-to-band tunneling effect (also referred as a BTBT effect) is generated. Consequently, portions of the electrons in the depletion region70are transferred through the gate dielectric layer41and stored into the charge storage layer43of the memory transistor MM2. Consequently, the program disturbance is generated, and the storage state of the non-selected memory cell Cell2is generated. Due to the program disturbance, the non-selected memory cell Cell2may be erroneously programmed. That is, during the program action, the program disturbance of the non-selected memory cell in the array structure is as small as possible.

FIG.2Bschematically illustrates the bias voltages for performing a program action on the memory cell of the array structure according to a second embodiment of the present invention. In comparison with the first embodiment, the magnitude of the program operation voltage VPOPprovided to the memory gate terminal TMG2of the memory transistor MM2is much lower. For example, the magnitude of the program operation voltage VPOPprovided to the memory gate terminal TMG2of the memory transistor MM2is 2.5V. Consequently, when the program action is performed, the BTBT effect will be effectively reduced. In other words, the program disturbance of the non-selected memory cell Cell2will be reduced.

In the biasing method ofFIG.2B, two different bias voltages are respectively provided to the memory gate terminal TMG1of the memory cell Cell1and the memory gate terminal TMG2of the memory cell Cell2when the program action is performed. Consequently, according to the conducting line layout, two separate conducting lines are connected with the corresponding driving circuits. That is, it is necessary to design the complicated conducting line layout of the metal layer over the semiconductor substrate. Furthermore, it is necessary to design two driving circuits (not shown) on the semiconductor substrate in order to provide two voltages to the memory gate terminal TMG1of the memory cell Cell1and the memory gate terminal TMG2of the memory cell Cell2through two conducting lines. Consequently, the use of the biasing method ofFIG.2Bresults in less program disturbance of the non-selected memory cell in the array structure when the program action is performed. However, since the number of the driving circuits increases, the conducting line layout is more complicated. In other words, the size of the non-volatile memory is larger.

In the biasing method ofFIG.2A, the program operation voltage VPOPprovided to the memory gate terminal TMG1of the memory cell Cell1and the program operation voltage VPOPprovided to the memory gate terminal TMG2of the memory cell Cell2are identical when the program action is performed. Consequently, the memory gate terminals TMG1and TMG2may be connected with each other, and the conducting line layout will be simplified. In addition, only a driving circuit on the semiconductor substrate to provide the program operation voltage VPOPis feasible. In other words, the use of the biasing method ofFIG.2Aresults in less driving circuits in the array structure when the program action is performed. In addition, the conducting line layout is simplified, and the size of the non-volatile memory is smaller. However, the non-selected memory cell in the array structure is readily subjected to the program disturbance.

As mentioned above, the biasing methods ofFIGS.2A and2Bhave some drawbacks. In other words, the biasing method for the array structure needs to be further improved.

FIG.3Aschematically illustrates the bias voltages for performing a program action on the memory cell of the array structure according to a third embodiment of the present invention. The array structure of this embodiment is identical to that ofFIG.1, and not redundantly described herein.

When the program action is performed on the array structure, a first voltage V1is provided to the control terminal TC2, and a second voltage V2is provided to the control terminals TC1and TC3. The first voltage V1is higher than the second voltage V2. For example, the first voltage V1is equal to 5V, and the second voltage V2is equal to a ground voltage (e.g., 0V). In addition, the N-well voltage VNWreceived by the N-well region NW is equal to the first voltage V1.

In addition, a program operation voltage VPOPis provided to the memory gate terminals TMG1and TMG2, an on voltage VONis provided to the memory gate terminal TMG1, and an off voltage VOFFis provided to the select gate terminal TSG2. Consequently, the memory cell Cell1is the selected memory cell, and the memory cell Cell2is the non-selected memory cell. For example, the on voltage VONis 0V, the off voltage VOFFis 5V, and the program operation voltage VPOPis 4.5V.

Please refer toFIG.3Aagain. In the non-selected memory cell Cell2, the select transistor MS2is turned off, and no channel is formed between the p-doped regions55and57. In the memory transistor MM2, no channel is formed between the p-doped regions57and59. Consequently, the program action is unable to be performed on the non-selected memory cell Cell2, and the non-selected memory cell Cell2is maintained in the erased state. In addition, since the voltage difference between the N-well region NW and the p-doped region59is 0V, no depletion region or a very narrow depletion region is formed in the junction between the N-well region NW and the p-doped region59.

Moreover, since the N-well voltage VNWis equal to the first voltage V1(e.g., 5V) and the p-doped region55receives the second voltage V2(e.g., 0V), there is a reverse bias between the N-well region NW and the p-doped region55. In other words, a wider depletion region74indicated as dotted lines is formed in the junction between the N-well region NW and the p-doped region55, which may generate the BTBT effect. However, since there is no charge storage layer in the select transistor MS2beside the depletion region74, the use of the biasing method ofFIG.3Awill not result in the program disturbance of the non-selected memory cell Cell2during the program action. In addition, the storage state of the Cell2will not be changed.

In the selected memory cell Cell1, the select gate terminal TSG1receives the on voltage VON. Consequently, the select transistor MS1is turned on, and a p-channel63is formed between the p-doped regions51and53. Under this circumstance, the second voltage V2(e.g., 0V) received by the p-doped region51is transmitted to the p-doped region53through the p-channel63after subtracting a threshold voltage (e.g., −0.7V) of the select transistor MS1. That is, the voltage on the p-doped region53is equal to 0.7V [0V−(−0.7V)]. Since the N-well region NW receives the first voltage V1(e.g., 5V), a wider depletion region72indicated as dotted lines is formed in the junction between the p-doped region51, the p-channel63, the p-doped region53and the N-well region NW.

In the memory transistor MM1, the memory gate terminal TMG1receives the program operation voltage VPOP, the p-doped region59receives the first voltage V1(e.g., 5V), and the p-doped region53receives 0.7V. Since the first voltage V1(e.g., 5V) received by the p-doped region59is higher than the voltage received by the p-doped region53(e.g., 0.7V), a tapered p-channel64is formed between the p-doped regions53and59. In addition, the p-channel64is pinched off near the p-doped region53.

Please refer toFIG.3Aagain. The voltage difference between the p-doped regions59and53is 4.3V, i.e., V1−(V2+0.7V)=4.3V. In addition, an electric field is generated. In the p-channel64, the holes are accelerated by the electric field to acquire higher energy. In the pinch off point73of the p-channel64, the high-speed holes impact the depletion region72.

Consequently, electron-hole pairs are generated in the depletion region72. Due to the CHHIHEI effect, electrons are attracted in response to the program operation voltage VPOP. Consequently, electrons near the pinch off point73are transferred through the gate dielectric layer21and stored into the charge storage layer23of the memory transistor MM1. Consequently, the selected memory cell Cell1is changed to the programmed state, and the program action is completed.

As shown inFIG.3A, the pinch off point73of the p-channel64is away from the non-selected memory cell Cell2. In addition, there is nearly no depletion region in the junction between the N-well region NW and the p-doped region59. The memory gate terminal TMG2of the memory transistor MM2also receives the same program operation voltage VPOP. However, the memory transistor MM2cannot generate the BTBT effect. In other words, the use of the biasing method ofFIG.3Awill not result in the program disturbance of the non-selected memory cell Cell2during the program action. In addition, the storage state of the Cell2will not be changed.

As mentioned above, the use of the biasing method of the third embodiment will not result in the program disturbance of the non-selected memory cell. In addition, the program operation voltage VPOPprovided to the memory gate terminal TMG1of the memory cell Cell1and the program operation voltage VPOPprovided to the memory gate terminal TMG2of the memory cell Cell2are identical when the program action is performed. Consequently, only a driving circuit on the semiconductor substrate to provide the program operation voltage VPOPis feasible. In addition, the memory gate terminals TMG1and TMG2may be connected with each other. Consequently, the conducting line layout will be simplified, a decoder can be omitted, and the size of the non-volatile memory can be effectively reduced.

As mentioned above, the select transistor MS1and the memory transistor MM1in the memory cell Cell1are p-type transistors. In order to allow the pinch off point73of the p-channel64in the memory transistor MM1to be located near the p-doped region53, the associated bias voltages are set according to the following rules.

Firstly, the N-well voltage VNWreceived by the N-well region NW is higher than or equal to the first voltage V1received by the p-doped region59. When the N-well voltage VNWis equal to the first voltage V1, there is no reverse bias between the N-well region NW and the p-doped region59, so the BTBT effect would not be generated. When the N-well voltage VNWis higher than the first voltage V1, there is a reverse bias between the N-well region NW and the p-doped region59. However, since there is a barrier voltage VBRdetermined according to the barrier height of the gate dielectric layer21and41, if the voltage difference between the N-well voltage VNWand the first voltage V1is lower than the barrier voltage VBR(e.g., 3V), the generation of the BTBT effect can be effectively avoided. In other words, 0V≤(VNW−V1)≤3V, and VNW≥V1. In the situation ofFIG.3A, (VNW−V1)=0V. That is, the above rule is satisfied.

Moreover, in case that the first voltage V1is higher than the second voltage V2and the voltage difference between the first voltage V1and the second voltage V2is higher than the barrier voltage VBR(e.g., 3V), the CHHIHEI effect can be generated. That is, (V1−V2)>3V, and V1>V2. In the situation ofFIG.3A, (V1−V2)=5V. That is, the above rule is satisfied.

In addition, the N-well voltage VNWis higher than the on voltage VON, and the voltage difference between the N-well voltage VNWand the on voltage VONis higher than the voltage difference between the first voltage V1and the second voltage V2. That is, (VNW−VON)≥(V1−V2). In the situation ofFIG.3A, (VNW−VON)=(V1−V2)=5V. That is, the above rule is satisfied.

The bias voltages shown inFIG.3Amay be adjusted according to the practical requirements. For example, when the program action is performed, the on voltage VONis lower than or equal to 0V. For example, the on voltage VONis −2V. Consequently, the select transistor MS1can be turned on completely. In addition, the program operation voltage VPOPis a fixed voltage, or the program operation voltage VPOPis a variable voltage. For example, when the program action is performed, the program operation voltage VPOPis gradually increased from 4.5V to 7.5V. Consequently, the CHHIHEI effect is generated continuously, and the program efficiency of the selected memory cell Cell1is increased.

By using the biasing method of the third embodiment to generate the CHHIHEI effect, electrons are injected into the charge storage layer23of the memory transistor MM1. In some other embodiments, another program operation voltage VPOPis provided, and thus holes are injected into the charge storage layer23of the memory transistor MM1.

FIG.3Bschematically illustrates the bias voltages for performing a program action on the memory cell of the array structure according to a fourth embodiment of the present invention. The array structure of this embodiment is identical to that ofFIG.1, and not redundantly described herein.

In comparison with the third embodiment, the magnitudes of the program operation voltage VPOPprovided to the memory gate terminals TMG1and TMG2are different. The bias voltages provided to the other terminals TC1, TC2, TC3, TSG1and TSG2are identical to those of the third embodiment, and not redundantly described herein. For example, when the program operation voltage VPOPis much lower than 5V (e.g., 0V), the memory transistor MM1is completely turned-on or nearly completely turned-on.

Please refer toFIG.3B. In the pinch off point73of the p-channel63, the high-speed holes impact the depletion region72. Consequently, electron-hole pairs are generated in the depletion region73, and a channel hot hole injection effect (also referred as a CHHI effect) is generated. Due to the CHHI effect, holes are transferred through the gate dielectric layer21and stored into the charge storage layer23of the memory transistor MM1. Consequently, the selected memory cell Cell1is changed to the erased state, and the program action is completed.

As mentioned above, by using the biasing method ofFIG.3Aand the biasing method ofFIG.3B, hot carriers can be injected into the charge storage layer23of the memory transistor MM1. The use of the biasing method ofFIG.3Aallows electrons to be injected into the charge storage layer23of the memory transistor MM1. The use of the biasing method ofFIG.3Ballows holes to be injected into the charge storage layer23of the memory transistor MM1.

FIG.4schematically illustrates the bias voltages for performing a read action on the memory cell of the array structure of the present invention. When the read action is performed on the array structure, a third voltage V3is provided to the control terminal TC2, and a fourth voltage V4is provided to the control terminals TC1and TC3. The third voltage V3is higher than the fourth voltage V4. For example, the third voltage V3is equal to 1.5V, and the fourth voltage V4is equal to the ground voltage (e.g., 0V). In addition, the N-well voltage VNWreceived by the N-well region NW is equal to the third voltage V3.

In addition, a read operation voltage VROPis provided to the memory gate terminals TMG1and TMG2, an on voltage VONis provided to the select gate terminal TSG1, and an off voltage VOFFis provided to the select gate terminal TSG2. Consequently, the memory cell Cell1is the selected memory cell, and the memory cell Cell2is the non-selected memory cell. For example, the on voltage VONis 0V, the off voltage VOFFis 1.5V, and the read operation voltage VROPis 2.0V.

Please refer toFIG.4again. In the non-selected memory cell Cell2, the select gate terminal TSG2receives the off voltage VOFF. Consequently, the select transistor MS2is turned off, and no read current is generated by the non-selected memory cell Cell2.

In the selected memory cell Cell1, the select gate terminal TSG1receives the on voltage VON. Consequently, the select transistor MS1is turned on, and a read current IRDis generated by the selected memory cell Cell1. In addition, the read current IRDflows from the control terminal TC2to the control terminal TC1. The storage state of the selected memory cell Cell1can be determined according to the magnitude of the read current IRD. For example, the non-volatile memory is equipped with a comparison circuit (not shown). The comparison circuit receives the read current IRDand a reference current IREF. If the read current IRDis higher than the reference current IREF, the selected memory cell Cell1is in the programmed state. Whereas, if the read current IRDis lower than the reference current IREF, the selected memory cell Cell1is in the erased state.

As mentioned above, the select transistor MS1and the memory transistor MM1in the memory cell Cell1are p-type transistors. The associated bias voltages for performing the read action are set according to the following rules.

Firstly, the N-well voltage VNWreceived by the N-well region NW is equal to the third voltage V3received by the p-doped region59. That is, VNW=V3. Since the N-well voltage VNWand the third voltage V3are both 1.5V, the above rule is satisfied.

Moreover, the third voltage V3is higher than the fourth voltage V4, and the voltage difference between the third voltage V3and the fourth voltage V4is lower than the barrier voltage VBR(e.g., 3V). Consequently, during the read action, the CHHIHEI effect is not generated, and the selected memory cell Cell1is not erroneously programmed. The voltage difference between the third voltage V3and the fourth voltage V4is lower than 3V, i.e., (V3−V4)213V. In the situation ofFIG.4, (V3−V4)=1.5V. That is, the above rule is satisfied.

In addition, the N-well voltage VNWis higher than the on voltage VON, and the voltage difference between the N-well voltage VNWand the on voltage VONis higher than the voltage difference between the third voltage V3and the fourth voltage V4. That is, (VNW−VON)≥(V3−V4). In the situation ofFIG.4, (VNW−VON)=(V3−V4)=1.5V. That is, the above rule is satisfied.

The bias voltages shown inFIG.4may be adjusted according to the practical requirements. When the read action is performed, the on voltage VON is lower than or equal to 0V. For example, the on voltage VONis −0.5V. Consequently, the select transistor MS1can be turned on completely. In addition, the read operation voltage VROPis higher than 0V and lower than 2.2V.

The bias voltages for performing the read action are not restricted to the bias voltages shown inFIG.4as long as the above rules are satisfied. For example, when the read action is performed, bias voltage of 2.0V is provided to the control terminal TC2, and the bias voltage of 0V is provided to the control terminals TC1and TC3. In addition, the N-well voltage VNWreceived by the N-well region NW is 2.0V. In addition, the read operation voltage VROPprovided to the memory gate terminals TMG1and TMG2is 2.2V, the on voltage VONprovided to the select gate terminal TSG1is 0V, and the off voltage VOFFprovided to the select gate terminal TSG2is 2.0V.

In the above embodiments, the transistors of the memory cell are p-type transistors. Of course, the technologies of the present invention can be also applied to the memory cell with n-type transistors.

FIG.5is a schematic cross-sectional view illustrating an array structure with plural non-volatile memory cells according to another embodiment of the present invention. The array structure as shown inFIG.5is similar to the array structure shown inFIG.1, and not redundantly described herein.

As shown inFIG.5, the array structure comprises two non-volatile memory cells Cell1and Cell2. The memory cell Cell1comprises a select transistor MS1and a memory transistor MM1. The memory cell Cell2comprises a select transistor MS2and a memory transistor MM2. The memory transistors MM1and MM2are storage devices of the memory cells. For example, the memory transistors MM1and MM2are charge-trap transistors or floating gate transistors.

As shown inFIG.5, plural gate structures110,120,130and140are formed over a surface of a P-well region PW in a semiconductor substrate (not shown). In addition, plural n-doped regions151,153,155,157and159are formed under the surface of the P-well region PW. The gate structure110is formed over the surface of the P-well region PW between the n-doped region151and the n-doped region153. The gate structure120is formed over the surface of the P-well region PW between the n-doped region153and the n-doped region159. The gate structure130is formed over the surface of the P-well region PW between the n-doped region157and the n-doped region155.

The gate structure140is formed over the surface of the P-well region of the n-doped region159and the n-doped region157.

The gate structure110comprises a gate dielectric layer111and a gate layer113. The gate structure120comprises a charge storage structure126and a gate layer87. The charge storage structure126further comprises a gate dielectric layer81, a charge storage layer83and an isolation layer85. The gate structure130comprises a gate dielectric layer131and a gate layer133. The gate structure140comprises a charge storage structure146and a gate layer97. The charge storage structure146further comprises a gate dielectric layer91, a charge storage layer93and an isolation layer95.

For example, the gate layers113,87,133and97are polysilicon layers. In addition, the gate dielectric layers81,91,111and131are oxide layers, the isolation layers85and95are oxide layers, and the charge storage layers83and93are nitride layers or polysilicon layers.

The P-well region PW, the gate structure110, the n-doped region151and the n-doped region153are collaboratively formed as the select transistor MS1. The P-well region PW, the gate structure120, the n-doped region153and the n-doped region159are collaboratively formed as the memory transistor MM1. The P-well region PW, the gate structure130, the n-doped region155and the n-doped region157are collaboratively formed as the select transistor MS2. The P-well region PW, the gate structure140, the n-doped region157and the n-doped region159are collaboratively formed as the memory transistor MM2. The select transistor MS1, the memory transistor MM1, the select transistor MS2and the memory transistor MM2are n-type transistors.

The n-doped regions151,159and155are electrically connected with control terminals TC1, TC2and TC3, respectively. The gate layers113and133are electrically connected with select gate terminals TSG1and TSG2, respectively. The gate layers87and97are electrically connected with the memory gate terminals TMG1and TMG2, respectively.

By providing proper bias voltages to the terminals TC1, TC2, TC3, TSG1,

TSG2, TMG1and TMG2, a program action can be performed on any of the memory cells Cell1and Cell2. For example, in case that no carriers are stored in the memory transistor MM1of the memory cell Cell1, the memory cell Cell1is in an erased state. Whereas, in case that the carriers are stored in the memory transistor MM1of the memory cell Cell1, the memory cell Cell1is in a programmed state.

FIG.6schematically illustrates the bias voltages for performing a program action on the memory cell of the array structure as shown inFIG.5. When the program action is performed on the array structure, a first voltage V1is provided to the control terminal TC2, and a second voltage V2is provided to the control terminals TC1and TC3. The first voltage V1is lower than the second voltage V2. For example, the first voltage V1is equal to a ground voltage (e.g., 0V), and the second voltage V2is equal to 5V. In addition, a P-well voltage VPWreceived by the P-well region PW is equal to the first voltage V1. Since the P-well voltage VPWis equal to the first voltage V1(e.g., 0V) and the n-doped region155receives the second voltage V2(e.g., 5V), there is a reverse bias between the P-well region PW and the n-doped region155. In other words, a wider depletion region174indicated as dotted lines is formed in the junction between the P-well region PW and the n-doped region155. In addition, both of the P-well region and the n-doped region159receive the first voltage V1(e.g., 0V), so no depletion region or a very narrow depletion region is formed in the junction between the P-well region PW and the n-doped region159.

In addition, a program operation voltage VPOPis provided to the memory gate terminals TMG1and TMG2, an on voltage VONis provided to the select gate terminal TSG1, and an off voltage VOFFis provided to the select gate terminal TSG2. Consequently, the memory cell Cell1is the selected memory cell, but the memory cell Cell2is the non-selected memory cell. For example, the on voltage VONis 5V, the off voltage VOFFis 0V, and the program operation voltage VPOPis 7V.

Please refer toFIG.6again. In the non-selected memory cell Cell2, the select gate terminal TSG2receives the off voltage VOFF. Consequently, the select transistor MS2is turned off, and no channel is formed between the n-doped regions155and157. In the memory transistor MM2, no channel is formed between the n-doped regions157and159. Consequently, the program action is unable to be performed on the on-selected memory cell Cell2, and the non-selected memory cell Cell2is maintained in the erased state.

In the selected memory cell Cell1, the select gate terminal TSG1receives the on voltage VON. Consequently, the select transistor MS1is turned on, and a n-channel161is formed between the n-doped regions151and153. Under this circumstance, the second voltage V2(e.g., 5V) received by the n-doped region151is transmitted to the n-doped region153through the n-channel161after subtracting a threshold voltage (e.g., 0.7V) of the select transistor MS1. That is, the voltage on the n-doped region153is equal to 4.37V [5V−(0.7V)]. Since the p-well region PW receives the first voltage V1(e.g., 0V), a wider depletion region172indicated as dotted lines is formed in the junction between the n-doped region151, n-channel161, the n-doped region153and the P-well region PW.

In the memory transistor MM1, the memory gate terminal TMG1receives the program operation voltage VPOP, the n-doped region159receives the first voltage V1(e.g., 0V), and the n-doped region153receives 4.3V. Since the first voltage V1(e.g., 0V) received by the n-doped region159is lower than the voltage received by the n-doped region153(e.g., 4.3V), a tapered n-channel163is formed between the n-doped regions159and153. In addition, the n-channel163is pinched off near the n-doped region153.

Please refer toFIG.6again. The voltage difference between the n-doped regions153and159is 4.3V, i.e., 5V−0.7V=4.3V. In addition, an electric field is generated. In the n-channel163, the electrons are accelerated by the electric field to acquire higher energy. In the pinch off point173of the n-channel163, the high-speed electrons impact the depletion region172. Consequently, electron-hole pairs are generated in the depletion region172.

Due to a channel hot electron injection effect (also referred as a CHEI effect), electrons are attracted in response to the program operation voltage VPOP. Consequently, electrons near the pinch off point173are transferred through the gate dielectric layer81and stored into the charge storage layer83of the memory transistor MM1. Consequently, the selected memory cell Cell1is changed to the programmed state, and the program action is completed. In conclusion, the use of the biasing method ofFIG.6will not result in the program disturbance of the non-selected memory cell Cell2during the program action. The reason is similar toFIG.3B, and not redundantly described herein.

As mentioned above, the select transistor MS1and the memory transistor MM1in the memory cell Cell1are n-type transistors. In order to allow the pinch off point173of the n-channel163in the memory transistor MM1to be located near the n-doped region153, the associated bias voltages are set according to the following rules.

Firstly, the first voltage Vi received by the n-doped region159is higher than or equal to the P-well voltage VPWreceived by the P-well region PW. When the first voltage V1 is equal to the P-well voltage VPW, there is no reverse bias between the P-well region PW and the n-doped region159, so the BTBT effect would not be generated. When the first voltage V1 is higher than the P-well voltage VPW, there is a reverse bias between the P-well region PW and the n-doped region159. In addition, the voltage difference between first voltage V1and the P-well voltage VPWis lower than a barrier voltage VBR. For example, in case that each of the barrier heights of the gate dielectric layers81and91of the memory transistors MM1and MM2is 3 eV (electron volt), the barrier voltage VBRis higher than or equal to 3V. Consequently, if the voltage difference between the first voltage V1and the P-well voltage VPWis lower than 3V, the generation of the BTBT effect can be effectively avoided. In other words, 0V ≤(V1−VPW)≤3V, and V1≥VPW. In the situation ofFIG.6, (V1−VPW)=0V. That is, the above rule is satisfied.

Moreover, in case that the second voltage V2is higher than the first voltage V1and the voltage difference between the second voltage V2and the first voltage V1is higher than the barrier voltage VBR(e.g., 3V), the CHEI effect can be generated. That is, (V2−V1)>3V. In the situation ofFIGS.6, (V2−V1) =5V. That is, the above rule is satisfied.

In addition, the on voltage VONis higher than the P-well voltage VPW, and the voltage difference between the on voltage VONand the P-well voltage VPWis higher than the voltage difference between the second voltage V2and the first voltage V1. That is, (VON−VPW)≥(V2−V1). In the situation ofFIG.6, (VON−VPW)=(V2−V1)=5V. That is, the above rule is satisfied.

The bias voltages shown inFIG.6may be adjusted according to the practical requirements. For example, when the program action is performed, the on voltage VONis higher than or equal to 5V. For example, the on voltage VONis 7V. Consequently, the select transistor MS1can be turned on completely.

FIG.7Aschematically illustrates the bias voltages for performing a read action on the memory cell of the array structure as shown inFIG.5. When the read action is performed on the array structure, a third voltage V3is provided to the control terminal TC2, and a fourth voltage V4is provided to the control terminals TC1and TC3. The third voltage V3is lower than the fourth voltage V4. For example, the third voltage V3is equal to the ground voltage (e.g., 0V), and the fourth voltage V4is 1.5V. In addition, the P-well voltage VPWreceived by the P-well region PW is equal to the third voltage V3(e.g., 0V).

In addition, a read operation voltage VROPis provided to the memory gate terminals TMG1and TMG2, an on voltage VONis provided to the memory gate terminal TMG1, and an off voltage VOFFis provided to the select gate terminal TSG2. Consequently, the memory cell Cell1is the selected memory cell, and the memory cell Cell2is the non-selected memory cell. For example, the on voltage VONis 1.5V, the off voltage VOFFis 0V, and the read operation voltage VROPis 0V.

Please refer toFIG.7Aagain. In the non-selected memory cell Cell2, the select gate terminal TSG2receives the off voltage VOFF. Consequently, the select transistor MS2is turned off, and no read current is generated by the non-selected memory cell Cell2.

In the selected memory cell Cell1, the select gate terminal TSG1receives the on voltage VON. Consequently, the select transistor MS1is turned on, and a read current IRDis generated by the selected memory cell Cell1. In addition, the read current IRDflows from the control terminal TC1to the control terminal TC2. The storage state of the selected memory cell Cell1can be determined according to the magnitude of the read current IRD. For example, the non-volatile memory is equipped with a comparison circuit (not shown). The comparison circuit receives the read current IRDand a reference current IREF. If the read current IRDis higher than the reference current IREF, the selected memory cell Cell1is in the erased state. Whereas, if the read current IRDis lower than the reference current IREF, the selected memory cell Cell1is in the programmed state.

As mentioned above, the select transistor MS1and the memory transistor MM1in the memory cell Cell1are n-type transistors. The associated bias voltages for performing the read action are set according to the following rules.

Firstly, the P-well voltage VPWreceived by the P-well region PW is equal to the third voltage V3received by the n-doped region159. That is, VPW=V3. Since the P-well voltage VPWand the third voltage V3are both 0V, the above rule is satisfied.

Moreover, the fourth voltage V4is higher than the third voltage V3, and the voltage difference between the fourth voltage V4and the third voltage V3is lower than the barrier voltage VBR(e.g., 3V). Consequently, during the read action, the CHEI effect is not generated, and the selected memory cell Cell1is not erroneously programmed. The voltage difference between the fourth voltage V4and the third voltage V3is lower than 3V. That is, (V4−V3)<3V. In the situation ofFIGS.4, (V3−V4)=1.5V. That is, the above rule is satisfied.

In addition, the on voltage VONis higher than the P-well voltage VPW, and the voltage difference between the on voltage VONand the P-well voltage VPWis higher than or equal to the voltage difference between the fourth voltage V4and the third voltage V3. That is, (VON−VPW)≥(V4−V3). In the situation ofFIG.7A, (VON−VPW)=(V4−V3)=1.5V. That is, the above rule is satisfied.

The bias voltages may be adjusted according to the practical requirements. When the read action is performed, the on voltage VONis higher than or equal to 1.5V. For example, the on voltage VONis 2.2V. Consequently, the select transistor MS1can be turned on completely. In addition, the read operation voltage VROPcan be higher than or lower than 0V, according to the programmed state and erased state distribution of the memory cell.

FIG.7Bschematically illustrates another bias voltages for performing a read action on the memory cell of the array structure as shown inFIG.5. In comparison with the biasing method ofFIG.7A, the magnitudes of the third voltage V3and the fourth voltage V4in the biasing method ofFIG.7Bare distinguished.

The third voltage V3provided to the control terminal TC2is 1.5V, and the fourth voltage V4provided to the control terminals TC1and TC3is the equal to the ground voltage (e.g., 0V). In addition, the bias voltages provided to the terminals TMG1, TMG2, TSG1and TSG2are not changed. In the selected memory cell Cell1, the read current IRDflows from the control terminal TC2to the control terminal TC1. The storage state of the selected memory cell Cell1can be determined according to the magnitude of the read current IRD.

According to the biasing methods ofFIG.7AandFIG.7B, there is a reverse bias between the n-doped region159and the P-well region PW, and the absolute value of the voltage difference between the fourth voltage V4and the third voltage V3is lower than the barrier voltage VBR(e.g., 3V). That is, |V4−V3|<VBR. In addition, the absolute value of the voltage difference between the on voltage VONand the P-well voltage VPWis higher than or equal to the absolute value of the voltage difference between the fourth voltage V4and the third voltage V3. That is, |VON−VPW≥[V4−V3].

In the array structure of the present invention, the biasing method of

FIG.7Aor the biasing method ofFIG.7Bcan be used to perform the read action according to the types of the memory transistors MM1and MM2. In case that the memory transistors MM1and MM2are floating gate transistors, the biasing method ofFIG.7Ais used to perform the read action. Whereas, in case that the memory transistors MM1and MM2are charge-trap transistors, the biasing method ofFIG.7Bis used to perform the read action.

From above descriptions, the present invention provides a non-volatile memory cell of an array structure and an associated controlling method for the non-volatile memory cell. The memory cell Cell1of the array structure comprises a select transistor MS1and a memory transistor MM1. The first drain/source terminal of the select transistor MS1is connected with a control terminal TC1. The second drain/source terminal of the select transistor MS1is connected with the first drain/source terminal of the memory transistor MM1. The gate terminal of the select transistor MS1is connected with the select gate terminal TSG1. The second drain/source terminal of the memory transistor MM1is connected with the control terminal TC2. The gate terminal of the memory transistor MM1is connected with the memory gate terminal TMG1. When the program action is performed on the memory cell, proper bias voltages are provided to the terminals TC1, TC2, TC3, TSG1, TSG2, TMG1and TMG2.

Consequently, the select transistor MS1is turned on, and a tapered channel is generated in the memory transistor MM1. The tapered channel is connected between the first drain/source terminal and the second drain/source terminal of the memory transistor MM1. Moreover, the tapered channel of the memory transistor MM1is pinched off near the first drain/source terminal of the memory transistor MM1. Consequently, the hot carriers near the pinch off point are injected into the charge storage layer of the memory transistor MM1.

Moreover, the memory transistor is the storage device in the memory cell. Of course, the storage device in the memory cell is implemented with other electronic components. For example, in case that the memory transistor MM1ofFIG.1is a floating gate transistor, the charge storage layer23of the memory transistor MM1may be regarded as a floating gate. In addition, the charge storage layer23connected with the gate layer27of the memory gate terminal TMG1may be regarded as a control gate. The structures of the charge storage layer23and the gate layer27are similar to two electrodes of a capacitor. Furthermore, the memory transistor of the storage device may be composed of a single-poly floating gate transistor and a coupling capacitor. The single-poly floating gate transistor only comprises two doped region and a floating gate layer, and single-poly floating gate transistor is not provided with the control gate layer. Consequently, the coupling capacitor is required. The first terminal of the coupling capacitor is connected with the floating gate layer of the single-poly floating gate transistor. The second terminal of the coupling capacitor is connected with the memory gate terminal TMG1. Consequently, the combination structure of the single-poly floating gate transistor and the coupling capacitor can be served as the memory transistor of the memory cell.