Address generator for generating addresses for testing a circuit

An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.

The invention relates to an address generator for generating addresses for testing an addressable circuit, and in particular for testing an addressable memory module.

U.S. Pat. No. 6,038,692 describes a memory system for error correction with an address generator. The address generator comprises a base address counter and a plurality of offset address generators, the base address counter being connected to an input of an addition circuit. The address generator furthermore contains a multiplexer circuit which, in a manner dependent on a selection control signal, through-connects an offset address generator to a further input of the addition circuit. The addition circuit adds the address present at the first input to the relative address value present at the second input.

DE 4 446 988 A1 describes a test pattern generator. The test pattern generator serves for generating addresses for testing an addressable circuit. In the test pattern generator, a plurality of arithmetic units are used for generating the addresses. The test pattern generator can be operated with a minimal number of control lines by a test device.

After the production operation, circuits are generally subjected to a test operation in order to test whether they are functional. Integrated semiconductor circuits, in particular, comprise a multiplicity of components in order to test their functionality in complicated test methods.

FIG. 1shows a test arrangement according to the prior art. A test device is connected via a data bus having the bus width D and an address bus having the bus width A to a circuit to be tested DUT (DUT: Device under test) and checks the functionality thereof. The circuit to be tested is, for example, a memory having a multiplicity of memory cells which are arranged in matrix form and can be addressed via the address bus. The test device generates, in an address generator, the addresses of the memory cells to be tested. In a test pattern generator, test data patterns are generated and applied via the data bus to the memory cells to be tested. Afterward, the data are read out again from the memory cells via the data bus and compared with the expected data in a test evaluation circuit within the test device. The circuit to be tested may be any desired digital circuit for example a memory, a logic circuit or a circuit which contains both logic elements and memory cells. If the data acquired by the test data evaluation circuit correspond to the expected data values, the test device recognizes that the circuit to be tested DUT is functional.

FIG. 2diagrammatically shows the construction of a memory having M×N memory cells SZ which are arranged in matrix form and can be addressed via row addresses X and column addresses Y. Integrated memories, for example DRAM memories, are complex circuit arrangements in which memory cells lying next to one another in the logical address space are remote front one another in the real circuitry arrangement, for example in a different layer of the semiconductor memory. Conversely, memory cells whose logical addresses have a large difference often adjoin one another. In order to test interactions between different memory cells, the test program carries out defined jumps from one memory cell SZAto another memory cell SZB. The functionality of the individual memory cells SZ is tested by writing in data and subsequently reading out data. In order to test interactions between the memory cells SZ, predetermined address patterns are applied to the memory.

The disadvantage of the conventional test arrangement illustrated inFIG. 1is that the address bus width A is relatively large, i.e. that many address bus lines have to be led from the test device to the circuit to be tested DUT. If the circuit to be tested DUT is an M×N memory, for example, the number A of address lines is:
A=1dM+1dN
where M is the number of column address lines and N is the number of row address lines of the memory to be tested DUT.

Synchronous DRAM memories already operate at operating frequencies of a few 100 MHz and must be tested by the test device with a corresponding clock frequency. The test arrangement according to the prior art as illustrated inFIG. 1has the disadvantage that the number of address lines or the address bus width A is relatively high and the length of the test lines leading from the test device to the circuit arrangement to be tested DUT is large. In order to enable testing of a circuit arrangement operated at high frequency, such as, for example, a DRAM memory, it is necessary, therefore, to use highly complex test devices in the test arrangement illustrated inFIG. 1, the test frequency of which test devices corresponds to the operating frequency of the circuit arrangement to be tested and which test devices have an address bus width A which is identical to the address bus width of the circuit to be tested (DUT).

The object of the present invention, therefore, is to provide an address generator for generating addresses for testing an addressable circuit which can be operated with a minimal number of control lines by a test device.

This object is achieved according to the invention by means of an address generator having the features specified in patent claim1.

The invention provides an address generator for generating addresses for testing an addressable circuit, having: at least one base address register for buffer-storing a base address, which base address register is in each case assigned to an associated offset register group having a plurality of offset registers for buffer-storing relative address values; a first multiplexer circuit, which, in a manner dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected top the circuit to be tested; a second multiplexer circuit, which, in a manner dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which, in a manner dependent on an offset register selection control signal, through-connects an offset register of the through-connected offset register group to a second input of the addition circuit; the addition circuit adding the base address present at the first input to the relative address value present at the second input to form an address which is written to the base address register.

In a preferred embodiment of the address generator according to the invention, the base address register and the associated offset registers can be initialized by an external test device, via initialization lines.

In a further preferred embodiment of the address generator according to the invention, the address signal switched through to the address bus can be inverted by a controllable inverting circuit.

In a further preferred embodiment of the address generator according to the invention, the number of offset registers of an offset register group is equal to the number of address test jump variants required for testing the circuit.

In a further preferred embodiment of the address generator according to the invention, the circuit to be tested is a synchronous memory which is operated with a high operating clock frequency.

The memory preferably has a multiplicity of memory cells which can be addressed via a multidimensional address space.

In this case, the number of base address registers preferably corresponds to the dimension of the address space of the memory to be tested.

In a particularly preferred embodiment of the address generator according to the invention, the base address register selection control signals and the offset register selection control signals are applied to the address generator by an external test device via an address control signal bus, the bus width of the address control signal bus between the test device and the address generator being less than the bus width of the address bus between the address generator and the circuit to be tested.

The length of the address bus lines between the address generator and the circuit to be tested is preferably much smaller than the length of the address control lines between the test device and the address generator.

In a particularly preferred embodiment, the address generator is integrated in the circuit to be tested.

FIG. 3illustrates a test arrangement in which the address generator1according to the invention is used. The address generator1serves for generating addresses for testing an addressable circuit2to be tested. The address generator1and the circuit2to be tested are connected to one another via an address bus3. The address generator1applies via the address bus3successive addresses of memory cells or addressable components to be tested within the circuit2. In the test arrangement illustrated inFIG. 3, the address generator1is situated in a test circuit4designed, for example, as an application-specific integrated circuit (ASIC). In addition to the address generator1, the test circuit4contains a circuit5for generating test data patterns and evaluating them. The circuit5is likewise connected to the circuit2to be tested, via a data bus6having the data bus width D. The data pattern generator5generates test data patterns which are written to the addressed memory cells via the data bus6and are subsequently read cut again via the data bus6. The data read out are compared with the expected data through test data of the evaluation circuit5. The test data pattern generator and evaluation circuit5is driven by an external conventional test device8via a data control line bus7having the bus width ZD. The test device8drives the address generator1according to the invention within the test circuit4via an address control line bus9. Furthermore, the test device8is connected to the address generator1via initialization lines10and via an inversion control line11.

In a first embodiment, in an application-specific integrated circuit ASIC, the test circuit4is provided as an autonomous semiconductor circuit between the actual rest device8and the circuit arrangement2to be tested. In an alternative embodiment, the test arrangement4is integrated into the circuit arrangement2to be tested. In both embodiments, the length off the address bus lines of the address bus3between the address generator1and the circuit arrangement2to be tested is significantly smaller than the length of the address control lines between the test device8and the address generator1. As a result of this, the address test signals present on the address bus3are significantly more robust relative to high-frequency interference signals which originate e.g. from other address lines. Furthermore, the address test signals are degraded to a much lesser extent by the address lines, so that the signal edges of the address signals which arrive at the circuit2to be tested are relatively steep, thereby avoiding errors during the testing of the circuit arrangement2.

FIG. 4shows a particularly preferred embodiment of the address generator1according to the invention. The address generator1contains a plurality of base address registers12a,12b, . . . The base address registers12serve for buffer-storing a base address which can be initialized by the external test device8via the initialization lines10. Each of the base address registers12is assigned an offset register group13. With the embodiment illustrated inFIG. 4, the offset register group13a, which has a plurality of offset registers13a-1,13a-2,13a-3,13a-4for buffer-storing relative address values, is assigned to the base address register12afor the X address or row address of the memory2to be tested. A second offset register group13b, which comprises a plurality of offset registers13b-1,13b-2,13b-3,13b-4, is assigned to the second base address register12bfor buffer-storing the Y address or column address of the memory2. The relative address values of the different offset registers of an offset register group13a,13bcan likewise be set or programmed by the test device8via initialization lines10.

The number of offset registers within an offset register group13a,13bis four in the exemplary embodiment illustrated inFIG. 4and corresponds to the number of required jump variants for testing the circuit arrangement2. A wide variety of test jump variants can be programmed into the address generator1according to the invention by the test device a via the initialization lines10. If, in one test jump variant, for example, the same memory cell is to be tested again, the relative address values which are written to the corresponding offset registers13a-i,13b-i of the offset register groups13a,13bare zero in each case. If, in a further test jump variant, the memory cell of the next column within the memory2is to be tested, the relative address value is zero in the offset register13a-i and one in the offset register13b-i. If, in a further test jump variant, for example, the memory cell of the next but one column and next row is to be tested, the relative address value of the offset register13a-i is one and the relative address value of the offset register13b-i is two.

In the exemplary embodiment illustrated inFIG. 4, it is possible to program four different test jump variants. In further embodiments (not illustrated) of the address generator1according to the invention, correspondingly more offset registers are provided for increasing the possible test jump variants.

The offset registers of the offset register groups13a,13bare connected via lines14a,14bto inputs15a,15bof multiplexers16within a first controllable multiplexer circuit17. The multiplexers16-1to16-4within the first multiplexer circuit17each have control inputs18, which are connected via lines19to a control input20of the first multiplexer circuit17. Furthermore, the multiplexers16-1to16-4within the first multiplexer circuit17have outputs21, which are connected via lines22to inputs23of multiplexers24within a multiplexer circuit25. The multiplexers24-1to24-2within the multiplexer circuit25have control inputs26, which are connected via control lines27to a control input28of the multiplexer circuit25. Furthermore, the multiplexers24-1,24-2have outputs29, which are connected via lines30to inputs31of a further multiplexer32connected downstream in a cascade-type manner within the multiplexer circuit25. The multiplexer32connected downstream has a control input33, which is connected via a control line34to a further control input29-2of the multiplexers25. The multiplexer32has an output35, which is connected via a line36to an output37of the multiplexer circuit25.

In addition to the multiplexer circuit17and the multiplexer circuit25, the address generator1according to the invention, as is illustrated in FIG.4, contains a further multiplexer circuit38, which, in manner dependent on the base register selection control signal present on the control line9switches through an address buffer-stored in the base address registers12-1,12-2from a first input of an addition circuit to an address bus of the circuit2to be tested. For this purpose, the multiplexer circuit38has a control input39, which is connected to the control line9. The multiplexer circuit30has a first input40, which is connected via a line41to the first base address register12afor buffer-storing the row address X, and a second input42, which is connected via a line43to the second bate address register12bfor buffer-storing the column address Y. The control inputs39of the multiplexer circuit38and the control input20of the multiplexer circuit17receive the same base register selection control signal via the control line9. For this purpose, the control input20of the multiplexer circuit17is likewise connected to the control line9to form a control line44. If, in a manner dependent on the base register selection control signal applied on the control line9, a base address register12-iis through-connected by the first multiplexer circuit38to the output45thereof, all the offset registers of the offset register group13associated with the through-connected base register12are simultaneously through-connected by the multiplexer circuit17to the multiplexer circuit25.

The control inputs28-1,28-2of the multiplexer circuit25are connected to a control terminal47of the address generator1via lines46. The control input20of the multiplexer circuit17is connected via a line44and the control input39of the multiplexer circuit38is connected via a line48to a further control terminal49of the address generator1according to the invention. The control inputs47,49are driven by the external test device8via address control lines of the address control line bus9.

Furthermore, the test device8is connected via initialization lines10to an initialization terminal50of the address generator1. The initialization terminal50is connected to the base address registers12a,12bvia internal initialization lines51and to the offset registers13via internal initialization lines52.

In the embodiment illustrated inFIG. 4, the output55of the multiplexer circuit38is connected via lines53to an inverting circuit54. The inverting circuit54is e.g. an XOR logic circuit connected via internal lines55to a control terminal56of the address generator1according to the invention. The control terminal56receives an inversion control signal from the external test device8through lines11. The inversion circuit54makes it possible, as required, to invert address signals for testing the circuit arrangement 2 bit by bit.

At the branching node57the address switched-through by the multiplexer circuit45is applied via lines58to a first input59of an addition circuit60. The addition circuit60has a second input61, which is connected via lines62to the output37of the multiplexer circuit25. The addition circuit60adds the switched-through base address present at the first input59to the relative address value which is present at the second input61and is switched through by the multiplexer circuit25in a manner dependent on the offset register selection control signal, to form a summation address value which is written via an output63and lines64to the base address register12for generating the next address. The controllable inversion circuit54has an output65, which is connected via internal lines66to an output67of the address generator1according to the invention.

In order to test the circuit arrangement2, firstly the base addresses are initialized by the test device8via the initialization lines10and written to the base address registers12. Furthermore, the relative jump values of the different test jump variants to be tested are initialized by the writing of relative address values to the offset registers13. A base address is selected by the application of a base register selection control signal to the control terminal49via address control lines9. Afterward, the desired test jump variant or the desired relative address value is selected by the application of an offset register selection control signal to the control input47of the address generator1. The addressed memory cell is subsequently tested by applying and reading out data. The operation is repeated until it is identified that the test operation has ended.

In the exemplary embodiment illustrated inFIG. 4, the number ZAof required control lines9of the address control signal bus9for controlling the address jumps is three.

Generally the number ZAof required control lines for the driving of the address generator1by the external test device8is:
ZA=1dd+1dp

where d is the dimension of the address space of the circuit arrangement2to be tested, and p is the number of desired test jump variants.

In the example illustrated inFIG. 4, a memory Z arranged in a matrix-type manner with a two-dimensional address space d=2 is tested, the number of possible test jump variants p being four in the example illustrated. The number of required control lines for the driving of the address generator is thus three.

In a memory2having 1024 (=210) column addresses and 1024 (=210) row addresses, the address bus width A of the address bus between the address generator1and the memory is at least ten, while the number ZAof required control lines for the driving of the address generator1by the external test device8comprises merely three lines. Consequently, the number ZAof required address control lines for the driving of the address generator1by the test device8is significantly less than the width of the address bus3. If the test arrangement4comprising the address generator1is positioned, as application-specific integrated circuit (ASIC), in spatial proximity to the circuit arrangement2or if the test arrangement4is even integrated into the circuit arrangement2, the length of the address control lines of the address control line bus9is significantly greater than the length of the address lines between the address generator1according to the invention and the circuit arrangement2to be tested. The control signals on the address control lines which are output from the test device8to the address generator1according to the invention have a significantly lower clock frequency than the clock frequency with which the generated addresses are applied from the address generator1to the circuit arrangement2for testing.

In the test arrangement according to the invention as illustrated inFIG. 3, it is therefore possible to use an external test device8with a relatively low operating frequency, the test device8, moreover, only having to have a very small number of address control lines. In the test arrangement according to the invention as illustrated inFIG. 3, it is therefore possible to use conventional test devices8which operate with a relatively low operating frequency, for testing memory modules2which operate with a considerably higher clock frequency of a few 100 MHz, without necessitating a considerable additional outlay on circuitry.

List of Reference Symbols

1. Address generator

2. Circuit to be tested

3. Address bus

4. Test circuit

5. Test pattern generator and evaluation circuit

6. Data bus

7. Data control line bus

8. Test device

9. Address control line bus

11. Inversion control line

12. Base address register

13. Offset register

18. Control inputs

19. Control line

20. Control input

26. Control input

27. Control line

28. Control input

33. Control input

34. Control line

39. Control input

44. Control line

46. Control lines

47. Control input

48. Control line

49. Control input

55. Control line

56. Control input

60. Addition circuit

67. Address output