Method for manufacturing fin field effect transistor

The present application discloses a method for manufacturing fin field effect transistors, comprising: step 1: performing first time etching to form top portions of fins, each of the top portions is divided into a first section and a second section; step 2: forming sacrificial sidewalls on the side surfaces of the second section but not on the side surfaces of the first section; step 3: forming a doped dielectric layer to coat the side surfaces of the first section; step 4: performing a dopant drive process to diffuse dopants of the doped dielectric layer into the first section; step 5: removing the doped dielectric layer and the sacrificial sidewalls; step 6: performing second time etching to form bottom portions of the fins; and step 7: forming a dielectric isolation layer between adjacent fins.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority to Chinese patent application No. CN202110273758.2, filed on Mar. 15, 2021, and entitled “METHOD FOR MANUFACTURING FIN FIELD EFFECT TRANSISTOR”, the disclosure of which is incorporated herein by reference in entirety.

TECHNICAL FIELD

The present application relates the field of semiconductor integrated circuit manufacturing, in particular, to a method for manufacturing a fin field effect transistor (FinFET).

BACKGROUND

With the development of the semiconductor process technology, the gate widths have been reduced continuously, and the conventional planar CMOS devices can no longer satisfy technology requirements, one important issue being controlling on the short channel effect. At a technology node below 20 nm, the fin field effect transistor structures have better electrical performance.FIG.1is a plan view of existing first type fin field effect transistors;FIG.2is a cross sectional view along a dashed line AA inFIG.1; andFIG.3is a cross sectional view along a dashed line BB inFIG.1. The method making the existing first type fin field effect transistor includes the following:

A fin2is formed on a semiconductor substrate such as a silicon substrate1, wherein the bottom of the fin2is isolated from the substrate by an insulation layer3, and the insulation layer3is generally the shallow trench isolation (STI).

The top surface and side surfaces of the fin2are covered with a metal gate (MG). Generally, a gate dielectric layer comprising a high dielectric-constant (HK) layer2042is provided between the metal gate and the material of the fin2for isolation, and the gate structure204in the dashed line box inFIG.3constitutes the HKMG. It can be seen from the plan view ofFIG.1that, there are a plurality of fins2arranged in parallel, there are a plurality of metal gates arranged in parallel, and the length direction of each metal gate is perpendicular to the length direction of each of the fins2. It can be seen fromFIG.3that, the gate structure is in the dashed line box204, and the gate dielectric layer of the gate structure204includes a stack of an interface layer2041, the high dielectric-constant layer2042, and the bottom bather metal2043. The metal gate of the gate structure204includes a work function layer2044, top barrier metal2045, and a metal conductive material layer4that are stacked up in sequence.FIG.1illustrates the metal conductive material layer4in a top view structure. Sidewalls203are formed on the side surfaces of the gate structure204, a contact etch stop layer (CESL)201covers the side surfaces of the sidewall203and the top surfaces of the silicon substrate1and the insulation layer3outside the gate structure204, in addition, a zeroth interlayer film202is formed in a spacing area between the adjacent gate structures204.

FIG.1illustrates an N-type fin field effect transistor101and a P-type fin field effect transistor102. A source area and a drain area are formed on two sides of the metal gate of the N-type fin field effect transistor101, and an embedded SiP epitaxial layer5is formed in each of the source area and the drain area. A source area and a drain area are formed on two sides of the metal gate of the P-type fin field effect transistor102, and an embedded SiGe epitaxial layer6is formed in each of the source area and the drain area. The embedded SiGe epitaxial layer6and the embedded SiP epitaxial layer5are formed by means of epitaxy growth after etching of the fins2.

The work function layer of the N-type fin field effect transistor101is an N-type work function layer. The work function layer of the P-type fin field effect transistor102is a P-type work function layer.

It can be seen fromFIG.2that, each of the fins2includes a bottom portion2aand a top portion2b, and the bottom portion2ais arranged in the insulation layer3. The metal gate covers the top surface and side surfaces of the top portion2bof each fin2. Referring toFIG.3, the top portion2bof the fin2covered by the metal gate serves as a channel area2c. As can be seen fromFIG.2, the height of the top portion2bof the fin2is h1, and h1is also the height of the channel area2c.FIG.3also shows that the height of the channel area2cis h1.

FIG.3is a cross sectional structural diagram of the N-type fin field effect transistor101. It can be seen that the source area5aand the drain area5bare formed on the two sides of the gate structure204, and the embedded SiP epitaxial layer5is formed in each of the source area5aand the drain area5b.

InFIG.3, the dashed line CC represents the line dividing the bottom portion2aand the top portion2bof the fin2, and the dashed line DD represents the line through the bottom surface of the bottom portion2aof the fin2. The control of the gate structure204from charge carriers in an area near the dashed line CC labeled as reference number205can be weakened, because the source area5aand the drain area5bare prone to depletion in this area205, the depleted area near205might cause connection of the source area5aand the drain area5bto each other, resulting in punchthrough. So electric leakage may occur between the source area5aand the drain area5bdue to the punchthrough of the depletion areas. Therefore an anti-punchthrough (APT) layer is generally required to prevent the punchthrough.

FIG.4is a schematic structural diagram of a fin of the second type fin field effect transistor with an existing anti-punchthrough layer.FIG.4illustrates a fin302and an insulation layer303composed of STI. An area between dashed lines EE and FF is a top area of the fin302, and the height h301of the top area of the fin302is the height of a channel area. An anti-punchthrough layer304is formed at the bottom of the top part of the fin302. In the existing technique, the anti-punchthrough layer304is generally formed by means of an ion implantation process. Existing data indicates that the anti-punchthrough layer304formed by the this method has the following defects.

First of all, the ion implantation causes implantation damage, and such ion implantation damage reduces the carrier mobility of the channel area, thereby degrading the device performance.

Secondly, as can be seen from the doping distribution morphology, which is represented by a reference numeral304a, of the anti-punchthrough layer304formed by the ion implantation, the doping concentration of the anti-punchthrough layer304gradually decreases from the peak position to the upper end and to the lower end, and an upper tail formed during a doping decreasing process enters the top area of the fin302. Since the channel area is formed in the top area of the fin302, the tail doping of the anti-punchthrough layer304affects the doping of the channel area, finally affecting the performance of the channel area, such as the threshold voltage and carrier mobility, and thereby degrading the device performance.

BRIEF SUMMARY

The technical problem to be solved by the present application is to provide a method for manufacturing a fin field effect transistor, to form a damage-free heavily-doped anti-punchthrough layer at the bottom of the channel layer, without affecting the carrier mobility of the channel layer.

The method for manufacturing a fin field effect transistor provided by the present application comprises the following steps:step 1: providing a semiconductor substrate, defining formation area of a fins, and performing the first time etching on the semiconductor substrate on the fins to form the top portions of the fins, each of the top portion has a first section and a second section, the second section is superposed on the top of the first section, andthe second section serves as a channel layer;step 2: forming sacrificial sidewalls on the side surfaces of the second section, wherein the sacrificial sidewalls are not disposed on the side surfaces of the first section;step 3: forming a doped dielectric layer to coat the side surfaces of the first section;step 4: performing a dopant drive process to diffuse dopants in the doped dielectric layer into the first section to achieve doping of the first section, wherein the doped first section serves as an anti-punchthrough layer;step 5: removing the doped dielectric layer and the sacrificial sidewalls;step 6: performing the second time etching on the semiconductor substrate to form a bottom portion of each fin, wherein each of the fins now has the bottom portion under the top portion; andstep 7: forming a dielectric isolation layer between adjacent two fins, wherein the top surface of the dielectric isolation layer aligns to between the top surface and the bottom surface of the anti-punchthrough layer.

In a further improvement, the semiconductor substrate comprises a silicon substrate.

In a further improvement, the fin field effect transistor comprises an N-type fin field effect transistor and a P-type fin field effect transistor.

In a further improvement, in a formation area of the N-type fin field effect transistor, the doped dielectric layer is a P-type doped dielectric layer, and the anti-punchthrough layer is a P-type anti-punchthrough layer.

In a further improvement, in the formation area of the N-type fin field effect transistor, the top portion is subjected to intrinsic doping or P-type doping in step 1.

In a further improvement, the P-type doped dielectric layer is a borosilicate glass (BSG) film.

In a further improvement, in a formation area of the P-type fin field effect transistor, the doped dielectric layer is an N-type doped dielectric layer, and the anti-punchthrough layer is an N-type anti-punchthrough layer.

In a further improvement, in the formation area of the P-type fin field effect transistor, the top portion is subjected to intrinsic doping or N-type doping in step 1.

In a further improvement, the N-type doped dielectric layer is a phosphosilicate glass (PSG) film.

In a further improvement, step 1 comprises the following sub-steps:step 11: forming a hard mask layer on the surface of the semiconductor substrate;step 12: forming a photoresist pattern, the photoresist pattern covering the formation area of the fin and opening an area other than the formation area of the fin;step 13: etching the hard mask layer to transfer a pattern structure of the photoresist pattern into the hard mask layer; andstep 14: performing the first time etching on the semiconductor substrate by using the hard mask layer as a mask.

The photoresist pattern is removed after the etching of the hard mask layer in step 13 is completed or after the first time etching in step 14 is completed.

In a further improvement, step 2 comprises the following sub-steps:depositing an organic dielectric layer (ODL), the organic dielectric layer arranged between spacing areas of the top portion for filling, and the organic dielectric layer having a height equal to the height of the first section;performing self-aligned deposition and etching processes to form the doped dielectric layer on the side surfaces of the top portion of the fins, wherein the doped dielectric layer covers the sacrificial sidewalls and the side surfaces of the first section; andremoving the organic dielectric layer.

In a further improvement, step 3 comprises the following sub-step:performing self-aligned deposition and etching processes to form the doped dielectric layer on the side surfaces of the top portions of the fins, so the doped dielectric layer covers the sacrificial sidewalls of the second section and the side surfaces of the first section.

In a further improvement, in step 4, the dopant drive process is implemented by means of thermal annealing, and process conditions of the dopant drive process comprise: a temperature of 1050° C., a time of 30 seconds, and an ambient atmosphere of oxygen.

In a further improvement, step 7 comprises the following sub-steps:step 71: depositing a material layer of the dielectric isolation layer to completely fill a spacing area between the fins, the material layer extending to the surface of the fin;step 72: performing a chemical mechanical planarization process to make the surface of the material layer of the dielectric isolation layer flush with the surface of the fin; andstep 73: etching back the material layer of the dielectric isolation layer to form the dielectric isolation layer.

In a further improvement, in step 71, the material layer of the dielectric isolation layer is deposited by means of a flowable chemical vapor deposition (FCVD) process.

In a further improvement, the top surface of the dielectric isolation layer is arranged at an intermediate position between the top surface and the bottom surface of the anti-punchthrough layer.

The fins of the present application are formed by two times of etching. After the first time etching is completed, the top portion of the fin is divided into two sections as needed to form the channel layer and the anti-punchthrough layer, and then the sacrificial sidewall is formed to cover the side surface of the top second section, so that the side surface of the bottom first section can be covered with the doped dielectric layer and the dopant of the doped dielectric layer can be diffused into the first section to achieve the doping of the first section and form the anti-punchthrough layer. Therefore, in the present application, the doping of the anti-punchthrough layer can be implemented by means of solid-phase source doping. Compared with ion implantation doping, the solid-phase source doping produces no ionic defects and can prevent the dopants from diffusing upwards into the channel layer. Finally, in the present application, the damage-free heavily-doped anti-punchthrough layer can be formed at the bottom of the channel layer, without affecting the carrier mobility of the channel layer, thereby achieving high carrier mobility and improving the device performance.

DETAILED DESCRIPTION OF THE DISCLOSURE

FIG.5is a flowchart of a method for manufacturing fin field effect transistors according to an embodiment of the present application.FIGS.6A-6Iare schematic diagrams of device structures in steps of the method of manufacturing fin field effect transistors according to the embodiment of the present application. The method of manufacturing fin field effect transistors according to the embodiment of the present application includes the following steps.

Step 1: Referring toFIG.6A, a semiconductor substrate401is provided, a formation area of fins402is defined, and first time etching is performed on the semiconductor substrate401to form top portions402aof the fins402.

In the method of the embodiment of the present application, the semiconductor substrate401includes a silicon substrate.

The fin field effect transistor includes an N-type fin field effect transistor and a P-type fin field effect transistor. InFIG.6A, the left side of the dashed line HH corresponds to a formation area601of the N-type fin field effect transistor, and the right side of the dashed line HH corresponds to a formation area602of the P-type fin field effect transistor.

The top portion402ais divided into a first section402a1and a second section402a2, and the second section402a2is on top of the first section402a1. InFIG.6A, the dashed line GG passes through the interfaces between the first section402a1and the second section402a2.

The second section402a2serves as a channel layer.

In the formation area601of the N-type fin field effect transistor, the top portion402ais subjected to intrinsic doping or P-type doping.

In the formation area602of the P-type fin field effect transistor, the top portion402ais subjected to intrinsic doping or N-type doping.

In some examples, step 1 includes the following sub-steps.Step 11: A hard mask layer501is formed on the surface of the semiconductor substrate401.

The hard mask layer501is formed by stacking an oxide layer501aand a nitride layer501b.Step 12: A photoresist pattern is formed, the photoresist pattern covers the formation area of the fins402and opens an area other than the formation area of the fins402.Step 13: The hard mask layer501is etched to transfer a pattern structure of the photoresist pattern into the hard mask layer501.Step 14: The first time etching is performed on the semiconductor substrate401by using the hard mask layer501as a mask.

The photoresist pattern is removed after the etching of the hard mask layer501in step 13 is completed or after the first time etching in step 14 is completed.

Step 2: Referring toFIG.6C, sacrificial sidewalls503are formed on the side surfaces of the second section402a2, however the sacrificial sidewalls503does not over the side surfaces of the first section402a1.

In the method of the embodiment of the present application, step 2 includes the following sub-steps.

Referring toFIG.6B, an organic dielectric layer502is disposed to fill into the spacing areas between adjacent top portions402a, and the thickness of the organic dielectric layer502equals to the height of the first section402a1, align to the dashed line GG.

Referring toFIG.6B, a deposition process of the sacrificial top surface and the sidewalls503ais performed with the material of the sacrificial sidewalls.

Referring toFIG.6C, an etching process of the sacrificial top surface and sidewalls503having the sacrificial material is performed to form the sacrificial sidewalls503on the side surfaces of the second section402a2in a self-alignment manner.

The organic dielectric layer502is removed. After the organic dielectric layer502is removed, the side surfaces of the first section402a1are exposed.

Step 3: Referring toFIG.6D, a doped dielectric layer is formed to coat the side surfaces of the first section402a1.

In the method of the embodiment of the present application, step 3 includes the following sub-step.

Self-aligned deposition and etching processes are performed to form the doped dielectric layer on the side surfaces of the top portion of the fins402a, so the doped dielectric layer covers the sacrificial sidewalls of the second section402a2and the side surfaces of the first section402a1.

In the formation area601of the N-type fin field effect transistor, the doped dielectric layer is subjected to P-type doping. In some examples, the doped dielectric layer is a BSG film504a.

In the formation area602of the P-type fin field effect transistor, the doped dielectric layer is subjected to N-type doping. In some examples, the doped dielectric layer is a PSG film504b.

In the method of the embodiment of the present application, the BSG film504aand the PSG film504bneed to be formed separately. For example, the BSG film504acan be formed first, and then the PSG film504bis formed; in this case, a process sequence is as follows: first, the formation area601of the N-type fin field effect transistor is opened and the formation area602of the P-type fin field effect transistor is covered, and then the BSG film504ais formed in the formation area601of the N-type fin field effect transistor; next, the formation area602of the P-type fin field effect transistor is opened and the formation area601of the N-type fin field effect transistor is covered, and then the PSG film504bis formed in the formation area602of the P-type fin field effect transistor. Alternatively, the PSG film504bis formed first, and then the BSG film504ais formed, in which case a process sequence is opposite to the sequence described above.

Step 4: Referring toFIG.6E, a dopant drive process is performed to diffuse dopants of the doped dielectric layer into the first section402a1to achieve doping of the first section402a1, wherein the doped first section402a1serves as an anti-punchthrough layer.

In the formation area601of the N-type fin field effect transistor, the doped dielectric layer is subjected to P-type doping, and the anti-punchthrough layer is a P-type anti-punchthrough layer403a.

In the formation area602of the P-type fin field effect transistor, the doped dielectric layer is subjected to N-type doping, and the anti-punchthrough layer is an N-type anti-punchthrough layer403b.

The dopant drive process is implemented by means of thermal annealing, and process conditions of the dopant drive process include: a temperature of 1050° C., a time of 30 seconds, and an ambient atmosphere of oxygen.

Step 5: Referring toFIG.6F, the doped dielectric layer and the sacrificial sidewalls503are removed.

Step 6: Referring toFIG.6G, second time etching is performed on the semiconductor substrate to form bottom portions402bof the fins402, wherein the fins402each includes the bottom portion402band the top portion402a.

Step 7: Referring toFIG.6I, a dielectric isolation layer404is formed between the fins402, wherein the top surface of the dielectric isolation layer404is arranged between the top surface and the bottom surface of the anti-punchthrough layer.

According to the method of the embodiment of the present application, step 7 includes the following sub-steps.

Step 71: Referring toFIG.6H, a material layer404aof the dielectric isolation layer404is deposited to fill spacing areas between adjacent fins402, here the material layer extends to the top surfaces of the fins402.

In some examples, the material layer404aof the dielectric isolation layer404is deposited by means of an FCVD process. After the FCVD process is completed, an annealing process is usually performed to cure the material layer404aof the dielectric isolation layer404.

Step 72: Referring toFIG.6H, a chemical mechanical planarization process is performed to make the top surface of the material layer404aof the dielectric isolation layer404flush with the top surfaces of the fins402. However, in the method of the embodiment of the present application, there is the hard mask layer501formed on the top surface of each of the fins402, thus the top surface of the material layer404aof the dielectric isolation layer404is flush with the top surfaces of the hard mask layer501on the surfaces of the fins402, after the chemical mechanical planarization process performed in step 72.

Step 73: Referring toFIG.6I, the material layer404aof the dielectric isolation layer404is etched back to form the dielectric isolation layer404. The hard mask layer501is removed before or after the etching-back of the dielectric isolation layer404.

In some examples, the top surface of the dielectric isolation layer404is arranged at an intermediate position between the top surface and the bottom surface of the anti-punchthrough layer.

The fin402provided with the anti-punchthrough layer can be formed via the steps described above.

Based on the formation of the fin402, the method further includes the formation of a gate structure of the fin field effect transistor, source and drain areas, and a metal interconnection structure. The formation processes of these structures are the same as those in the existing techniques and will not be described in detail herein.

The fins402of the embodiment of the present application are formed by two times of etching. After the first time etching is completed, the top portion402aof each fin402includes two different sections to form the channel layer and the anti-punchthrough layer, and then the sacrificial sidewalls503are formed to cover the side surfaces of the top second section402a2, so that the side surfaces of the bottom first section402a1can be attached to the doped dielectric layer and the dopants of the doped dielectric layer can diffuse into the first section402a1and form the anti-punchthrough layer. Therefore, according to the embodiment of the present application, the doping of the anti-punchthrough layer can be implemented by means of solid-phase source doping. Compared with doping via ion implantation, the solid-phase source doping produces no ionic defects and can prevent the dopant from diffusing upwards into the channel layer. Finally, in the embodiment of the present application, the damage-free heavily-doped anti-punchthrough layer can be formed at the bottom of the channel layer, without affecting the carrier mobility of the channel layer, thereby achieving high carrier mobility and improving the device performance.

The present application is described in detail above via specific embodiments, but these embodiments are not intended to limit the present application. Without departing from the principle of the present application, those skilled in the art can still make many variations and improvements, which should also be considered to fall into the protection scope of the present application.