Semiconductor device and method of forming the same

A semiconductor device includes a gate electrode on a gate insulating film over a semiconductor substrate, a first sidewall insulating film on a side surface of the gate electrode, and source and drain regions, each including a pocket diffusion layer of a first conductivity type, and first and second diffusion layers of a second conductivity type. The pocket diffusion layer is disposed in the semiconductor substrate. The first diffusion layer of a second conductivity type extends over the pocket diffusion layer. The first diffusion layer faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer over the first diffusion layer is higher in impurity concentration than the first diffusion layer. The second diffusion layer is separated by the first diffusion layer from the pocket diffusion layer, and has a side surface which faces toward the first sidewall insulating film through the first diffusion layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a semiconductor device and a method of forming the same.

Priority is claimed on Japanese Patent Application No. 2009-283947, filed Dec. 15, 2009, the content of which is incorporated herein by reference.

2. Description of the Related Art

As shrinkage of semiconductor devices has been progressed, the dimension (or gate length) of a gate electrode of a metal-oxide-semiconductor (MOS)-type transistor has been reduced, and the influence of a short channel effect on electrical characteristics has become more serious.

For suppressing the short channel effect of the MOS transistor, a silicon layer is formed in source and drain regions using an epitaxial growth process, which is disclosed in Japanese Patent Application Laid-Open No. 2007-134732.

For suppressing the short channel effect of the MOS transistor, a pocket layer of an opposite conductivity type to impurities for forming source and drain regions is formed, which is disclosed in Japanese Patent Application Laid-Open No. 6-196492.

SUMMARY

In one embodiment, a semiconductor device may include, but is not limited to, a semiconductor substrate, a gate insulating film formed on a surface of the semiconductor substrate, a gate electrode formed on the gate insulating film, a first sidewall insulating film formed on a side surface of the gate electrode, and source and drain regions. Each of the source and drain regions may include, but is not limited to, a pocket diffusion layer of a first conductivity type, a first diffusion layer of a second conductivity type, and a second diffusion layer of the second conductivity type. The pocket diffusion layer of a first conductivity type is disposed in the semiconductor substrate. The first diffusion layer of a second conductivity type extends over the pocket diffusion layer. The first diffusion layer faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer of the second conductivity type is higher in impurity concentration than the first diffusion layer. The second diffusion layer extends over the first diffusion layer. The second diffusion layer is separated by the first diffusion layer from the pocket diffusion layer. The second diffusion layer has a side surface which faces toward the first sidewall insulating film through the first diffusion layer.

In another embodiment, a semiconductor device may include, but is not limited to, a first circuit region comprising a first transistor, and a second circuit region comprising a second transistor. The second circuit region is isolated from the first circuit region. The first transistor may include, but is not limited to, a first active region, a first gate insulating film, a first gate electrode, a first sidewall insulating film, and first source and drain regions. The first gate insulating film is formed on a surface of the first active region. The first gate electrode is formed on the first gate insulating film. The first sidewall insulating film is formed on a side surface of the first gate electrode. Each of the first source and drain regions may include, but is not limited to, a pocket diffusion layer of a first conductivity type, a first diffusion layer of a second conductivity type, and a second diffusion layer of the second conductivity type. The pocket diffusion layer of a first conductivity type is disposed in the first active region. The first diffusion layer of a second conductivity type extends over the pocket diffusion layer. The first diffusion layer faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer of the second conductivity type is higher in impurity concentration than the first diffusion layer. The second diffusion layer extends over the first diffusion layer. The second diffusion layer is separated by the first diffusion layer from the pocket diffusion layer. The second diffusion layer has a side surface which faces toward the first sidewall insulating film through the first diffusion layer. The second transistor may include, but is not limited to, a second active region, a second gate electrode, and second source and drain regions. The second gate electrode is formed in the second active region. The semiconductor layer is formed on a surface of the second active region. The second source and drain regions are formed in the semiconductor layer and in the second active region. The second source and drain regions are lower in impurity concentration than the first diffusion layer.

In still another embodiment, a semiconductor device may include, but is not limited to, a semiconductor substrate, a gate insulating film, a gate electrode, a first sidewall insulating film, a pocket diffusion layer of a first conductivity type, a first diffusion layer of a second conductivity type, and a second diffusion layer of the second conductivity type. The gate insulating film is formed on a surface of the semiconductor substrate. The gate electrode is formed on the gate insulating film. The first sidewall insulating film is formed on a side surface of the gate electrode. The pocket diffusion layer of a first conductivity type is formed in the semiconductor device. The first diffusion layer of a second conductivity type faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer of the second conductivity type is higher in impurity concentration than the first diffusion layer. The second diffusion layer has a side surface which faces toward the first sidewall insulating film through the first diffusion layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before describing the present invention, the related art will be explained in detail with reference toFIGS. 21A,21B,21C and21D, in order to facilitate the understanding of the present invention.

An example of a method of fabricating a transistor including a silicon layer and a pocket layer is illustrated inFIGS. 21A through 21D. The fabrication method includes stacking a gate insulating layer94, a gate electrode95, and an insulating layer96on a semiconductor substrate91and performing a patterning process using an ordinary method to form a gate electrode.

As shown inFIG. 21A, a P-type impurity ion implantation process and an N-type impurity ion implantation process are sequentially performed, thereby forming a pocket impurity layer92and a lightly doped drain (LDD) impurity layer93.

As shown inFIG. 21B, sidewalls97are formed using an insulating layer on lateral surfaces of the gate electrode95.

As shown inFIG. 21C, an epitaxial growth process is performed on the LDD impurity layer93so that a silicon layer98where source and drain regions will be formed in a subsequent process can be gradually grown.

As shown inFIG. 21D, by performing an ion implantation process on the silicon layer98, a high-concentration impurity layer99is formed. The high-concentration impurity layer99is formed to reach the surface of the semiconductor substrate91so that the high-concentration impurity layer99can be electrically connected to the LDD impurity layer93. In a MOS transistor, to improve a channel length Lmin on which prediction of occurrence of a short channel effect is based, it is necessary to set source and drain regions including the LDD impurity layer93and the high-concentration impurity layer99to a shallow depth. However, in the conventional MOS transistor shown inFIGS. 21A through 21D, when the LDD impurity layer93is formed to a shallow depth, forming the high-concentration impurity layer99to a shallow depth than the LDD impurity layer93becomes difficult. Thus, a lower portion of the high-concentration impurity layer99is in contact with the pocket impurity layer92.

In the above-described transistor, from a viewpoint of electrical connection between the source/drain regions99and the LDD impurity layer93, even if the grown amount of the silicon layer98is increased, lower portions of the source/drain regions99must be set to positions shown inFIG. 21D. For this reason, a channel length Lmin of the source/drain regions99is improved only within a limited range. Since there is no method for improving the channel length Lmin beyond the limited range, it is difficult to suppress a short channel effect with the advancement of miniaturization.

Furthermore, it is necessary to suppress a short channel effect of a MOS transistor more than in the conventional case to keep up with the advancement of miniaturization. However, in conventional methods, a short channel effect of a downscaled device is not sufficiently suppressed, and it is difficult to fabricate semiconductor devices including downscaled MOS transistors due to their high integration density.

In one embodiment, a semiconductor device may include, but is not limited to, a semiconductor substrate, a gate insulating film formed on a surface of the semiconductor substrate, a gate electrode formed on the gate insulating film, a first sidewall insulating film formed on a side surface of the gate electrode, and source and drain regions. Each of the source and drain regions may include, but is not limited to, a pocket diffusion layer of a first conductivity type, a first diffusion layer of a second conductivity type, and a second diffusion layer of the second conductivity type. The pocket diffusion layer of a first conductivity type is disposed in the semiconductor substrate. The first diffusion layer of a second conductivity type extends over the pocket diffusion layer. The first diffusion layer faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer of the second conductivity type is higher in impurity concentration than the first diffusion layer. The second diffusion layer extends over the first diffusion layer. The second diffusion layer is separated by the first diffusion layer from the pocket diffusion layer. The second diffusion layer has a side surface which faces toward the first sidewall insulating film through the first diffusion layer.

In some cases, the second diffusion layer may have a bottom surface which is higher than the surface of the semiconductor substrate.

In some cases, the second diffusion layer may have a bottom surface which is higher than the gate insulating film.

In some cases, the first diffusion layer may contact the pocket diffusion layer.

In some cases, the semiconductor device may include, but is not limited to, a second sidewall insulating film extending along the first sidewall insulating film. The second sidewall insulates film being positioned on a top portion of the first diffusion layer.

In some cases, the semiconductor device may include, but is not limited to, an isolation layer in the semiconductor substrate. The isolation layer defines an active region in which the source and drain regions are positioned. The isolation layer has a bottom surface which is deeper than a bottom surface of the pocket diffusion layer.

In another embodiment, a semiconductor device may include, but is not limited to, a first circuit region comprising a first transistor, and a second circuit region comprising a second transistor. The second circuit region is isolated from the first circuit region. The first transistor may include, but is not limited to, a first active region, a first gate insulating film, a first gate electrode, a first sidewall insulating film, and first source and drain regions. The first gate insulating film is formed on a surface of the first active region. The first gate electrode is formed on the first gate insulating film. The first sidewall insulating film is formed on a side surface of the first gate electrode. Each of the first source and drain regions may include, but is not limited to, a pocket diffusion layer of a first conductivity type, a first diffusion layer of a second conductivity type, and a second diffusion layer of the second conductivity type. The pocket diffusion layer of a first conductivity type is disposed in the first active region. The first diffusion layer of a second conductivity type extends over the pocket diffusion layer. The first diffusion layer faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer of the second conductivity type is higher in impurity concentration than the first diffusion layer. The second diffusion layer extends over the first diffusion layer. The second diffusion layer is separated by the first diffusion layer from the pocket diffusion layer. The second diffusion layer has a side surface which faces toward the first sidewall insulating film through the first diffusion layer. The second transistor may include, but is not limited to, a second active region, a second gate electrode, and second source and drain regions. The second gate electrode is formed in the second active region. The semiconductor layer is formed on a surface of the second active region. The second source and drain regions are formed in the semiconductor layer and in the second active region. The second source and drain regions are lower in impurity concentration than the first diffusion layer.

In some cases, the second diffusion layer may have a bottom surface which is higher than the surface of the semiconductor substrate.

In some cases, the second diffusion layer may have a bottom surface which is higher than the gate insulating film.

In some cases, the first diffusion layer may contact the pocket diffusion layer.

In some cases, the semiconductor device may include, but is not limited to, a second sidewall insulating film extending along the first sidewall insulating film. The second sidewall insulating film is positioned on a top portion of the first diffusion layer.

In some cases, the first circuit region may include, but is not limited to, a peripheral circuit region. The second circuit region may include, but is not limited to, a memory cell region. The first transistor is a planer transistor. The second transistor is a trench transistor. The second gate electrode is partially buried in the semiconductor substrate.

In some cases, the semiconductor device may include, but is not limited to, a bit line connected to a first one of the second source and drain regions in the memory cell region; and a capacitor element connected to a second one of the second source and drain regions in the memory cell region.

In still another embodiment, a semiconductor device may include, but is not limited to, a semiconductor substrate, a gate insulating film, a gate electrode, a first sidewall insulating film, a pocket diffusion layer of a first conductivity type, a first diffusion layer of a second conductivity type, and a second diffusion layer of the second conductivity type. The gate insulating film is formed on a surface of the semiconductor substrate. The gate electrode is formed on the gate insulating film. The first sidewall insulating film is formed on a side surface of the gate electrode. The pocket diffusion layer of a first conductivity type is formed in the semiconductor device. The first diffusion layer of a second conductivity type faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer of the second conductivity type is higher in impurity concentration than the first diffusion layer. The second diffusion layer has a side surface which faces toward the first sidewall insulating film through the first diffusion layer.

In some cases, the first diffusion layer may include, but is not limited to, first and second portions. The first portion extends over the pocket diffusion layer. The second portion extends along the first sidewall insulating film. The second diffusion layer extends over the first portion of the first diffusion layer. The second diffusion layer is separated by the first portion of the first diffusion layer from the pocket diffusion layer. The second diffusion layer is separated by the second portion of the first diffusion layer and the first sidewall insulating film from the gate electrode.

In some cases, the second diffusion layer may have a bottom surface which is higher than the surface of the semiconductor substrate.

In some cases, the first diffusion layer may contact the pocket diffusion layer.

In some cases, the semiconductor device may include, but is not limited to, a second sidewall insulating film extending along the first sidewall insulating film. The second sidewall insulating film is positioned on a top portion of the side surface of the second diffusion layer.

In some cases, the semiconductor device may include, but is not limited to, a bit line connected to the second diffusion layer.

In some cases, the semiconductor device may include, but is not limited to, a capacitor element connected to the second diffusion layer.

In an additional aspect, a method of forming a semiconductor device may include, but is not limited to, the following processes. A gate insulating film is formed on a surface of a semiconductor substrate. A gate electrode is formed on the gate insulating film. Pocket impurity diffusion layers of a second conductivity type are formed in the semiconductor substrate. The pocket impurity diffusion layers are positioned in both sides of the gate electrode. First insulating sidewalls are formed on side surfaces of the gate electrode. Silicon layers are formed over the pocket impurity diffusion layers. The silicon layers are positioned in both sides of the gate electrode. Lightly doped drain diffusion layers of a first conductivity type are formed in lower portions of the silicon layers. Second insulating sidewalls are formed on side surfaces of the first insulating sidewalls. Diffusion layers of the first conductivity type are formed by introducing an impurity into upper portions of the silicon layers by using the second insulating sidewalls as masks. The diffusion layers are higher in impurity concentration than the lightly doped drain diffusion layers.

In some cases, the diffusion layers face toward the side surfaces of the first insulating sidewalls through the lightly doped drain diffusion layers.

In some cases, the lightly doped drain diffusion layers are formed by carrying out an ion implantation process that introduces ions of the first conductivity type, wherein Rp (projected range) of the ions is set to reach about an intermediate position in thickness direction of the silicon layers.

In some cases, the diffusion layers are formed by carrying out another ion implantation process that introduces ions of the first conductivity type, wherein Rp (projected range) of the ions is set to reach in the range from about an intermediate position in thickness direction of the silicon layers to the upper surface of the silicon layers.

In an additional aspect, a method of forming a semiconductor device that includes a first circuit region and a second circuit region may include, but is not limited to, the following processes. A gate insulating film is formed on a surface of each of the first and second circuit regions of the semiconductor substrate. A gate electrode is formed on the gate insulating film in each of the first and second circuit regions of the semiconductor substrate. Pocket impurity diffusion layers of a second conductivity type are formed in the first circuit region, while the second circuit region is masked. The pocket impurity diffusion layers are positioned in both sides of the gate electrode in the first circuit region. First insulating sidewalls are simultaneously formed on side surfaces of the gate electrodes in the first and second circuit regions. Silicon layers are formed in the first and second circuit regions. The silicon layers are simultaneously positioned in both sides of the gate electrodes in the first and second circuit regions. Lightly doped drain diffusion layers of a first conductivity type are formed in lower portions of the silicon layers in the first circuit region, while the second circuit region is masked. Second insulating sidewalls are simultaneously formed on side surfaces of the first insulating sidewalls in the first and second circuit regions. Diffusion layers of the first conductivity type are formed by introducing an impurity into upper portions of the silicon layers in the first circuit region by using the second insulating sidewalls as masks, while the second circuit region is masked. The diffusion layers are higher in impurity concentration than the lightly doped drain diffusion layers. A first inter-layer insulating film is formed, which covers both the first and second circuit regions. A contact hole is formed in the first inter-layer insulating film, wherein the contact hole is positioned over the silicon layer in the second circuit region. Lowly doped diffusion layers are formed in the silicon layer in the second circuit region by introducing an impurity of the first conductivity type. The lowly doped diffusion layers are lower in impurity concentration than the lightly doped drain diffusion layers.

In some cases, the diffusion layers face toward the side surfaces of the first insulating sidewalls through the lightly doped drain diffusion layers.

In some cases, the lightly doped drain diffusion layers are formed by carrying out an ion implantation process that introduces ions of the first conductivity type, wherein Rp (projected range) of the ions is set to reach about an intermediate position in thickness direction of the silicon layers.

In some cases, the diffusion layers are formed by carrying out another ion implantation process that introduces ions of the first conductivity type, wherein Rp (projected range) of the ions is set to reach in the range from about an intermediate position in thickness direction of the silicon layers to the upper surface of the silicon layers.

In some cases, lowly doped diffusion layers are formed by introducing the impurity into both the silicon layers in the second circuit region and the semiconductor substrate surfaces beneath the silicon layers in the second circuit region.

First Embodiment

Semiconductor Device

As an example of a semiconductor device according to a first embodiment of the present invention, a metal-oxide-semiconductor (MOS)-type transistor of an N-type channel, which is a first conductivity type, will be described with reference toFIG. 10.

As shown inFIG. 10, the semiconductor device according to the first embodiment of the present invention includes a semiconductor substrate1, a pocket impurity layer108aformed in the vicinity of the surface of the semiconductor substrate1, a gate electrode105formed on the semiconductor substrate1to overlap an end portion of the pocket impurity layer108a, a gate insulating layer5aformed between the semiconductor substrate1and the gate electrode105, an insulating layer5cformed on a top surface of the gate electrode105, first insulating-layer sidewalls5bformed on lateral surfaces of the gate electrode105, a silicon layer109formed on the pocket impurity layer108to contact the first insulating-layer sidewalls5b, second insulating-layer sidewalls5dformed on lateral surfaces of the first insulating-layer sidewalls5bto contact at least a portion of the silicon layer109, a lightly doped drain (LDD) impurity layer109formed in a lower portion of the silicon layer109, and a high-concentration source/drain impurity layer (or high-concentration impurity layer)109bformed in an upper portion of the silicon layer109.

Referring toFIG. 10, the semiconductor substrate1is formed of a semiconductor, for example, silicon, which contains impurities of a P-type, which is a second conductivity type, at a predetermined concentration. Isolation regions3with an insulating layer, such as a silicon oxide (SiO2) layer, buried therein are formed in the semiconductor substrate1. The isolation regions3are formed in portions other than active regions of the surface of the semiconductor substrate1and electrically insulate adjacent active regions from each other. The gate electrode105, and a source (or source region)108S and a drain (or drain region)108D formed located on both sides of the gate electrode105are included in the active region, and a silicon layer109formed by selective epitaxial growth (SEG) is stacked on the source108S and the drain108D. The source108S and the drain108D are connected to a metal interconnection13by contact plugs12formed on the silicon layer109. Also, the first insulating-layer sidewalls5band the second insulating-layer sidewalls5dare formed on the lateral walls of the gate electrode105. Furthermore, designations of the source and drain may be switched.

As shown inFIG. 10, in the semiconductor substrate1, the source108S and the drain108D are formed apart from each other in the active region defined by the isolation regions3, and the planar gate electrode105is formed between the source108S and the drain108D. The gate electrode105is formed of a multi-layer of a gate silicon layer5sand a metal layer5mto protrude upward from the semiconductor substrate1. The gate silicon layer5sis formed to contain impurities, such as phosphorus (P), during formation of a polysilicon (poly-Si) layer using a chemical vapor deposition (CVD) method. Also, in a subsequent process, N-type or P-type impurities may be introduced into a poly-Si layer formed not to contain impurities upon layer formation. The metal layer5mmay be formed of a metal having a high melting point, such as tungsten (W), tungsten nitride (WN), or tungsten silicide (WSi).

The gate insulating layer5ais formed between the gate electrode105and the semiconductor substrate1. For example, the gate insulating layer5amay be formed of a single SiO2layer, a high dielectric (high-k) layer containing, for example, hafnium (Hf), or a stack layer of a silicon nitride (Si3N4) layer and a SiO2layer.

The first insulating-layer sidewalls5band the second insulating-layer sidewalls5dare formed of an insulating layer, such as a Si3N4layer, on the lateral walls of the gate electrode105. An insulating layer5c, such as a Si3N4layer, is formed on the gate electrode105to protect a top surface of the gate electrode105. Also, the first insulating-layer sidewalls5bare formed on all lateral surfaces of the gate silicon layer5s, the metal layer5m, and the insulating layer5c, and the second insulating-layer sidewalls5dare formed in a lateral direction of the metal layer5mand the insulating layer5c.

The source108S and the drain108D include the P-type (or second conductivity type) pocket impurity layer108aformed in the semiconductor substrate1on both sides of the gate electrode105, the silicon layer109formed on the pocket impurity layer108using an SEG method, the N-type (or first conductivity type) LDD impurity layer109aformed in the lower portion of the silicon layer109, and the N-type (or first conductivity type) high-concentration source/drain impurity layer109bformed in the upper portion of the silicon layer109. The high-concentration source/drain impurity layer109bis set to have a higher impurity concentration than the LDD impurity layer109a. For example, boron (B) is introduced into the P-type pocket impurity layer108a, P is introduced into the N-type LDD impurity layer109a, and arsenic (As) is introduced into the N-type high-concentration source/drain impurity layer109b.

As shown inFIG. 10, a lower portion of the high-concentration source/drain impurity layer109bis formed to contact the LDD impurity layer109ain the silicon layer109. From a viewpoint of suppression of a short channel effect, it is preferable that the lower portion of the high-concentration source/drain layer109bremain within the silicon layer109, that is, that it be located over the top surface of the semiconductor substrate1. Also, the LDD impurity layer109ais formed not to spread outside a region of the pocket impurity layer108a.

Also, as shown inFIG. 10, an interlayer insulating layer11is formed of an insulating layer, such as a SiO2layer, on the semiconductor substrate1, and an upper metal interconnection13is formed of aluminum (Al) or copper (Cu) on the interlayer insulating layer11. In addition, contact plugs12are formed through the interlayer insulating layer11to connect the source108S and the drain108D with the metal interconnection13.

In the N-channel type MOS transistor having the above-described configuration, when a voltage is applied between the source108S and the drain108D and then a voltage is applied to the gate electrode105, a channel region9through which electrons move is formed near an interface with the gate insulating layer5aon the surface of the semiconductor substrate1between the source108S and the drain108D.

In the semiconductor device of the present invention, the pocket impurity layer108aof the second conductivity type is formed in the vicinity of the surface of the semiconductor substrate1on both sides of the gate electrode105. Also, the high-concentration source/drain impurity layer109bof the first conductivity type is formed on the pocket impurity layer108avia the LDD impurity layer109aof the first conductivity type. Thus, since the high-concentration source/drain impurity layer109bis formed apart from an end portion of the gate electrode105, it is possible to effectively suppress occurrence of the short channel effect in spite of miniaturization.

Also, in the semiconductor device of the present invention, the lower portion of the high-concentration source/drain impurity layer109bremains within the silicon layer109, that is, is located over the top surface of the semiconductor substrate1, thereby further suppressing the occurrence of the short channel effect.

Therefore, according to the semiconductor device of the present invention, it is possible to prevent power consumption from increasing due to a current increase in an off state of the transistor, and a circuit operation from failing due to a drop in threshold voltage. In other words, according to the present invention, a high-integrated high-performance semiconductor device may be obtained.

A method of fabricating the semiconductor device according to the first embodiment of the present invention, for example, a method of fabricating a MOS-type transistor of an N channel type, which is a first conductivity type, will now be described with reference toFIGS. 1 through 10.

FIGS. 1 through 9are cross-sectional views showing processes of the method of fabricating the semiconductor device according to the first embodiment of the present invention.FIG. 10is a schematic cross-sectional view showing an example of the semiconductor device according to the first embodiment of the present invention.

To begin with, an insulating layer, such as a SiO2layer, is buried, for example, using a shallow trench isolation (STI) method in a semiconductor substrate1formed of silicon and of a P-type (or a second conductivity type), which is formed by introducing impurities using a thermal oxidation method, thereby forming isolation regions3. Furthermore, in the present embodiment, a P-type well may be formed by ion implantation in a region of the semiconductor substrate1where a MOS transistor will be formed, in advance.

As shown inFIG. 1, a gate insulating layer5a, a gate silicon layer5s, a metal layer5msuch as a WSi layer, and an insulating layer5care sequentially formed.

The gate insulating layer5ais formed to a thickness of, for example, about 5 nm by oxidizing the silicon surface of the semiconductor substrate1into SiO2using a thermal oxidation method. The gate insulating layer5amay be formed of a stack layer of a SiO2layer and a Si3N4layer or a high dielectric (or high-k) layer, such as a silicon oxynitride (SiON) layer or a hafnium oxide (HfO2) layer.

The gate silicon layer5sis formed by depositing a poly-Si layer containing P as N-type (or first conductivity type) impurities to a thickness of, for example, about 40 nm using a CVD method. Furthermore, the gate silicon layer5smay be formed by forming a poly-Si layer free from impurities, such as P, and introducing impurities, such as P, into the poly-Si layer using an ion implantation method in a subsequent process.

The metal layer5mis formed by depositing a metal (e.g., W, WN, or WSi) having a high melting point, to a thickness of about 50 nm using a CVD method.

The insulating layer5cis formed by depositing a Si3N4layer to a thickness of, for example, about 100 nm using a CVD method.

As shown inFIG. 2, a photoresist layer7is formed as a patterning mask using a photolithography technique. The insulating layer5c, the metal layer5m, and the gate silicon layer5care sequentially patterned by an anisotropic dry etching technique using the photoresist layer7as a mask, thereby forming a gate electrode105. The gate electrode105is formed to intersect an active region, when viewed from the plan view. For example, the anisotropic dry etching is performed in an atmosphere of a pressure of about 10 to 50 mTorr using a gas mixture of, for example, chlorine (Cl2), hydrogen bromide (HBr), and oxygen (O2).

As shown inFIG. 3, after the photoresist layer7serving as the mask is removed, P-type (or second conductivity type) impurity ions are implanted into the semiconductor substrate1in self-alignment with the gate electrode105, thereby forming pocket impurity portions108bon both sides of the gate electrode105. Specifically, for example, B ions are implanted as impurities at an energy of about 10 Kev with a dose of 1.5×1013atoms/cm2.

A Si3N4layer is deposited on the semiconductor substrate1to cover the gate electrode105using a low-pressure CVD (LPCVD) method, thereby forming a first insulating layer. For example, the formation of the Si3N4layer is performed at a temperature of about 700° C. to a thickness of about 10 nm. Here, the pocket impurity portions108bdiffuse during the formation of the first insulating layer, thereby forming pocket impurity layers108a. The pocket impurity layers108adiffuse not only in a longitudinal direction (or vertical direction) but also in a traverse direction (or horizontal direction) and spread slightly inward from a lower end layer of the gate electrode105a(or spread into a lower end layer of the gate insulating layer5a). Then, the first insulating layer is etched back, thereby forming first insulating-layer sidewalls5bon lateral walls of the gate electrode105to a thickness of about 10 nm.

Subsequently, a cleaning process is performed using a cleaning solution having a low etch rate, such as diluted hydrogen fluoride (HF), to remove, for example, a native oxide layer from the surface of the semiconductor substrate and expose a clean surface (or silicon surface) of the semiconductor substrate1. A silicon layer109is formed on the exposed surface of the semiconductor substrate1using a vapor-phase SEG method. For example, the silicon layer109is formed using dichlorosilane (SiH2Cl2) gas and hydrochloric-acid (HCl)-containing gas and grown to a thickness of about 40 nm. The silicon layer109is formed in the vertical direction to the substrate1along the first insulating-layer sidewalls5bfrom the surface of the semiconductor substrate1using a vapor-phase SEG method. As shown inFIG. 5, the silicon layer109is selectively formed to be grown on a region in which the silicon surface of the semiconductor substrate1is exposed and slightly grown on the isolation regions3, and a top surface of the silicon layer109has a generally flat shape without a facet.

As shown inFIG. 6, N-type (or first conductivity type) impurity ions are implanted in self-alignment with the gate electrode105to form LDD impurity layers109a. At this time, ion implantation energy is set such that a projected range (Rp) upon ion implantation lies midway along the thickness of the silicon layer109. Specifically, for example, P ions are implanted as impurities at an energy of about 10 KeV with a dose of 2×1013atoms/cm2.

Subsequently, an insulating layer, such as a Si3N4layer, is formed on the semiconductor substrate1to a thickness of, for example, about 30 nm using an LPCVD method to cover the gate electrode105and the silicon layer109, thereby forming a second insulating layer. The second insulating layer is etched back to form second insulating-layer sidewalls5dto a thickness of about 30 nm on the silicon layer109disposed on sides of the first insulating-layer sidewalls5bformed on the lateral walls of the gate electrode105, as shown inFIG. 7. Here, the formation of the insulating layer, such as a Si3N4layer, is performed at a temperature of about 700° C., and the LDD impurity layers109adiffuse into the silicon layer109during the formation of the second insulating layer. Also, although lower portions of the LDD impurity layers109amay reach the inside of the semiconductor substrate1, the ion implantation energy is set such that the LDD impurity layers109ado not spread outside regions of the previously formed pocket impurity layers108a.

As shown inFIG. 8, N-type (or first conductivity type) impurity ions are implanted in self-alignment with the gate electrode105to form a high-concentration source/drain impurity layer109b. Impurity concentration of the high-concentration source/drain impurity layer109bis set to be higher than that of the previously formed LDD impurity layer109a. Also, during the ion implantation, the ion implantation energy is set such that a projected range (Rp) upon ion implantation ranges from a midway point in the thickness of the silicon layer109to the top surface of the silicon layer109. Specifically, for example, As ions are implanted as impurities at an energy of about 20 Kev with a dose of 5×1015atoms/cm2.

Subsequently, activation annealing of the implanted impurities is performed, for example, at a temperature of about 900° C. for 10 seconds in a nitride atmosphere using a rapid thermal annealing (RTA) method. Since the activation annealing is performed in a short period of time, diffusion of the high-concentration source/drain impurity layer109bis suppressed to be slightly spread from a position in the implanted silicon layer109. As shown inFIG. 9, lower portions of the high-concentration source/drain impurity layers109bare formed to contact the LDD impurity layers109awithin the silicon layer109. From a viewpoint of the suppression of the short channel effect, it is preferable that the thickness upon the formation of the silicon layer109and the ion implantation energy of the high-concentration source/drain impurity layer109bbe adjusted so that the lower portions of the high-concentration source/drain layers109bcan remain within the silicon layer109, that is, are located over a top surface of the semiconductor substrate1. Although the pocket impurity layer108aand the LDD impurity layer109adiffuse and spread to some extent due to the activation annealing, the LDD impurity layers109aare set not to spread outside regions of the pocket impurity layers108aby adjusting the implantation energy upon the formation of the LDD impurity layers109a.

An interlayer insulating layer11is formed of SiO2using a CVD method to cover the gate electrode105and the silicon layer109. Subsequently, contact holes connected to the silicon layer109as source and drain regions are opened. A titanium (Ti) layer, a titanium nitride (TiN) layer, and a W layer are sequentially formed in the contact holes and polished using a chemical mechanical polishing (CMP) method to form contact plugs12. A contact plug connected to the gate electrode105is formed in the same manner in another region not shown. Afterwards, a TiN layer and an Al layer are sequentially formed and patterned to form metal interconnections13connected to the contact plugs12.

In the above-described process, the MOS transistor, which is the semiconductor device according to the first embodiment of the present invention, is completed.

In the method of fabricating the semiconductor device of the present invention, after the pocket impurity layer108aof the second conductivity type opposite to the first conductivity type of the LDD impurity layer109ais previously formed in the vicinity of the surface of the semiconductor substrate1, the LDD impurity layer109ais introduced into the silicon layer109formed on the pocket impurity layer108a. Thereafter, the high-concentration source/drain impurity layer109bof the first conductivity type is introduced into regions of the silicon layer109that are not covered with the second insulating-layer sidewalls5dformed on the lateral surfaces of the gate electrode105. Thus, the LDD impurity layers109aand the high-concentration source/drain impurity layers109bare prevented from diffusing in the traverse direction (or horizontal direction), thereby suppressing occurrence of a short channel effect. In other words, in the present invention, the LDD impurity layers109aare introduced into the silicon layer109formed on the surface of the semiconductor substrate1using ion implantation instead of being directly introduced into the surface of the semiconductor substrate1using ion implantation. Thus, the LDD impurity layer109passes beyond the initially formed pocket impurity layer108aand diffuses into a lower region of the gate electrode105(or a region disposed inward from the end of the gate electrode105, that is, a lower end portion of the gate insulating layer5a), so that occurrence of a short channel effect may be prevented. Also, after the second insulating-layer sidewalls5dare formed, the high-concentration source/drain impurity layers109bare formed using the ion implantation process. Thus, the high-concentration source/drain impurity layers109bmay be formed apart from the ends of the gate electrode105so that the occurrence of the short channel effect can be prevented more effectively.

Also, in the method of fabricating the semiconductor device of the present invention, the high-concentration source/drain impurity layers109bcan be formed so that the lower portions of the high-concentration source/drain impurity layers109bremain within the silicon layer109, that is, are located over the top surface of the semiconductor substrate1, thereby further suppressing the occurrence of the short channel effect.

Accordingly, it is possible to prevent power consumption from increasing due to a current increase in an off state of the transistor, and a circuit operation from failing due to a drop in a threshold voltage. In other words, according to the present invention, a high-performance semiconductor device can be easily fabricated with high integration.

Although the N-channel transistor has been described in the present embodiment, the present invention may be applied to a P-channel transistor. In this case, an N-type well is previously formed in a region of a semiconductor substrate1where the P-channel transistor will be formed. Thus, N-type impurities, such as P, may be implanted as a pocket impurity layer108a, P-type impurities, such as B, may be implanted as an LDD impurity layer109a, and P-type impurities, such as boron fluoride (BF2), may be implanted as high-concentration source/drain impurity layers109b.

Since the ion implantation conditions described in the present embodiment are only an example, changes in implantation energy, dose, and kind of ions may be made without departing from the spirit and scope of the present invention. Also, materials and thicknesses of the insulating layer and the gate electrode may be changed.

In addition, a combination of methods for high performance used in, for example, a conventional planar MOS may be used without departing from the spirit and scope of the present invention.

Second Embodiment

In the present invention, the MOS transistor shown as the semiconductor device of the first embodiment may be applied to only a portion of the semiconductor device. A second embodiment of the present invention in which when a DRAM device is formed as a semiconductor device, a transistor provided in a memory cell region is a groove-type transistor (or trench-gate transistor) to which the present invention is not applied and the present invention is applied to a transistor provided in a peripheral circuit region will now be described. Furthermore, in the following description, the same reference numerals are used to denote the same components in the memory cell region of the second embodiment as in the first embodiment described above, and a description of the same components will be omitted.

An example of a semiconductor device according to the second embodiment will now be described with reference toFIGS. 11 through 13.

A dynamic random access memory (DRAM), which is the semiconductor device of the present embodiment, is largely comprised of a peripheral circuit region (or first circuit region) and a memory cell region (or second circuit region). The peripheral circuit region is disposed adjacent to the memory cell region. The peripheral circuit region includes, for example, a sense amplifier circuit, a word line driver circuit, and an input/output (I/O) circuit connected to the outside.

FIG. 11is a conceptual diagram showing a planar structure of the memory cell region of the DRAM, which is the semiconductor device of the present embodiment, in which only some elements of a memory cell are shown. A right portion ofFIG. 11is a transmitted cross-sectional view obtained on the basis of a surface that cuts a gate electrode (or second gate electrode)5, which will be a word line W, first insulating-layer sidewalls5b, and second insulating-layer sidewalls5d. A capacitor element is omitted inFIG. 11and illustrated only in the cross-sectional views ofFIGS. 13A and 13B.

FIG. 12is a conceptual diagram showing a plane structure of a principal portion of the peripheral circuit region of the DRAM.

FIG. 13Ais a schematic cross-sectional view corresponding to line A-A′ ofFIG. 11(or memory cell region), andFIG. 13Bis a schematic cross-sectional view corresponding to line B-B′ ofFIG. 12(or peripheral circuit region). Also, sinceFIGS. 12,13A, and13B are provided to describe the configuration of the semiconductor device, the sizes and dimensions of the respective portions shown inFIGS. 12,13A, and13B are different from those of actual semiconductor devices.

First, the memory cell region will be described with reference toFIGS. 11 and 13A. As shown inFIG. 13A, the memory cell region is generally comprised of a MOS transistor Tr1for a memory cell and a capacitor element (or capacitance unit)24connected to the MOS transistor Tr1via a substrate contact plug4A and a capacitor contact plug21A.

Referring toFIGS. 11 and 13A, the semiconductor substrate1is formed of a semiconductor containing P-type impurities at a predetermined concentration, for example, silicon. Isolation regions3are formed in the semiconductor substrate1. The isolation regions3are formed by burying an insulating layer, such as a SiO2layer, in the surface of the semiconductor substrate1using an STI method. The isolation regions3are formed in portions other than active regions (second active regions) K and electrically insulate adjacent active regions K from each other. The present embodiment shows an example of a case where the present invention is applied to a cell structure in which a 2-bit memory cell is disposed in a single active region K.

In the present embodiment, as shown in the planar structure ofFIG. 11, a plurality of active regions K in an elongated strip shape are spaced a predetermined distance apart from one another and aligned to be inclined rightward and downward. An impurity diffusion layer is disposed in each of both end portions and a central portion of each of the active regions K. Thus, a source (or source region)8S is formed in the central portion of each of the active regions K, drains (or drain regions)8D are respectively formed in the both end portions of each of the active regions K. Also, substrate contacts205a,205b, and205care defined as being disposed directly on the source8S and the drains8D.

Furthermore, although the arrangement of the active regions K in a planar shape as shown inFIG. 11is unique to the present embodiment, the shape and alignment direction of the active regions K may not be specially limited. The shape of the active regions K shown inFIG. 11may naturally be the shape of active regions applied to other typical transistors and is not limited to the shape of the present invention. Also, the designations of the source and drain may be switched.

A plurality of bit lines6are elongated in a bent-line shape in a traverse (or X) direction ofFIG. 11and spaced a predetermined distance apart from one another in a longitudinal (or Y) direction ofFIG. 11. Also, a plurality of word lines W are disposed in a straight-line shape and extend in the longitudinal (or Y) direction ofFIG. 11. The plurality of word lines W are spaced a predetermined distance apart from one another in the traverse (or X) direction ofFIG. 1, and the gate electrode5shown inFIG. 13Ais included in a portion in which the word line W intersects the active region K. Although a case where the MOS transistor Tr1includes a groove-type gate electrode5is illustrated as an example in the present embodiment, a transistor having another configuration may be used. The MOS transistor having the groove-type gate electrode may be replaced with a planar-type MOS transistor or a MOS transistor in which a channel region is formed on a lateral surface of a groove formed in a semiconductor substrate.

As shown in a cross-sectional structure ofFIG. 13A, the source8S and the drain8D are formed apart from each other in the active region K defined by the isolation regions3in the semiconductor substrate1, and the groove-type gate electrode5is formed between the source8S and the drain8D. The gate electrode5is formed of a multi-layer of a poly-Si layer and a metal layer to protrude upward from the semiconductor substrate1. The poly-Si layer may be formed to contain impurities, such as P, when formed using a CVD method. Alternatively, the poly-Si layer may be formed not to contain impurities, and N-type or P-type impurities may be implanted into the poly-Si layer using an ion implantation process in a subsequent process. The metal layer may be formed of a metal having a high melting point, such as W, WN, or WSi.

Also, as shown inFIG. 13A, a gate insulating layer5ais formed between the gate electrode5and the semiconductor substrate1. The gate insulating layer5amay be the same as that in the first embodiment.

First insulating-layer sidewalls5band second insulating-layer sidewalls5dmay be formed of an insulating layer, such as a Si3N4layer, on lateral walls of the gate electrode5, and an insulating layer5csuch as a Si3N4layer is formed on the gate electrode5to protect a top surface of the gate electrode5.

The source8S and the drain8D are comprised of a silicon layer (or second silicon layer)8formed to contact the active region K formed in the semiconductor substrate1and a cell impurity layer8aformed in the silicon layer8using an ion implantation process. The cell impurity layer8ais formed within the silicon layer8and also diffuses into the surface of the semiconductor substrate1so that a low-concentration impurity layer can be integrally formed within both the silicon layer8and the surface of the semiconductor substrate1. The silicon layer8is formed using an SEG method. For example, P ions are introduced as N-type impurities into the cell impurity layer8a.

Also, as shown inFIG. 13A, a first interlayer insulating layer4is formed of an insulating layer, such as a SiO2layer, on the semiconductor substrate1, and substrate contact plugs4A are formed through the first interlayer insulating layer4. The substrate contact plugs4A are respectively disposed in positions of the substrate contacts205c,205a, and205band formed to be connected to the silicon layer8formed as the source8S and the drain8D. The substrate contact plugs4A are formed of a poly-Si layer containing, for example, P.

In addition, a second interlayer insulating layer10formed using an insulating layer, such as a SiO2layer, is stacked on the first interlayer insulating layer. A bit line contact plug10A is formed in the second interlayer insulating layer10and connected to the substrate contact plug4A. The bit line contact plug10A is formed by stacking a W layer on a barrier layer (TiN/Ti) formed of a stack layer of TiN and Ti. A bit line6is formed to be connected to the bit line contact plug10A. The bit line6is formed of a stack layer of WN and W.

A third interlayer insulating layer21is formed of an insulating layer, such as a SiO2layer, to cover the bit line6. Capacitor contact plugs21A are formed through the second interlayer insulating layer10and the third interlayer insulating layer21and connected the substrate contact plugs4A. A fourth interlayer insulating layer22is formed of an insulating layer, such as a SiO2layer, on the third interlayer insulating layer21, and capacitor elements24are formed to be connected to the capacitor contact plugs21A.

The capacitor element24includes a lower electrode24a, an upper electrode24c, and a high-dielectric (or high-k) capacitor insulating layer24bformed of a high-k material between the lower and upper electrodes24aand24c. The high-k material may be, for example, zirconium oxide (ZrO2), aluminum oxide (Al2O3), HfO2, or a stack structure thereof. The lower electrode24aand the upper electrode24cmay be formed of a metal layer, such as a TiN layer. The lower electrode24aand the capacitor contact plug21A are electrically connected.

A fifth interlayer insulating layer30is formed of, for example, SiO2on the capacitor element24to cover the upper electrode24c. In addition, an upper metal interconnection layer31formed of Al or Cu and a surface protection layer32formed of SiON are formed on the fifth interlayer insulating layer30.

The memory cell region having the above-described configuration operates as a memory cell of a DRAM capable of performing a data storage operation, in which a determination can be made as to whether or not there are charges accumulated in the capacitor element24, via the bit line6, by turning the MOS transistor Tr1on.

Next, the peripheral circuit region will be described with reference toFIGS. 12 and 13B. The peripheral circuit region includes a planar-gate-type MOS transistor Tr2to which the present invention is applied, as shown inFIG. 13B. Hereinafter, a case where the transistor Tr2has an N-type (or first conductivity type) channel will be described.

FIG. 12is a conceptual diagram of a planar structure of the peripheral circuit region of the DRAM device, which is the semiconductor device of the present embodiment, in which only some elements constituting a peripheral circuit are shown.

As shown inFIGS. 12 and 13B, in the present embodiment, the peripheral circuit includes a gate electrode (or first gate electrode)105, a source108S, and a drain108D, which are disposed in an active region (or first active region) K, and a silicon layer (or first silicon layer)109formed using selective epitaxial growth is stacked on the source108S and the drain108D. The source108S and the drain108D are connected to another element by contact plugs10B formed on the silicon layer109. Also, first insulating-layer sidewalls5band second insulating-layer sidewalls5dare formed on lateral walls of the gate electrode105.

Furthermore, although the arrangement of the active regions K in a planar shape as shown inFIG. 12is unique to the present embodiment, the shape and alignment direction of the active regions K may not be specially limited. The shape of the active regions K shown inFIG. 12may naturally be the shape of active regions applied to other typical transistors and is not limited to the shape of the present invention. Also, the designations of the source and drain may be switched.

As shown in a cross-sectional structure ofFIG. 13B, the source108S and the drain108D are formed apart from each other in the active region K defined by isolation regions3in a semiconductor substrate1, and a planar gate electrode105is formed between the source108S and the drain108D. Like the above-described gate electrode5of the memory cell, the gate electrode105is formed of a stacked layer of a poly-Si layer and a metal layer.

A gate insulating layer5ais formed between the gate electrode105and the semiconductor substrate1, and the first insulating-layer sidewalls5band the second insulating-layer sidewalls5dare formed of an insulating layer, such as a Si3N4layer, on lateral walls of the gate electrode105. An insulating layer5c, such as a Si3N4layer, is formed on the gate electrode105.

The source108S and the drain108D are comprised of a P-type (or second conductivity type) pocket impurity layer108aformed in the semiconductor substrate1, a silicon layer109formed on the pocket impurity layer108a, an N-type (or first conductivity type) LDD impurity layer109aformed in a lower portion of the silicon layer109, and an N-type (or first conductivity type) high-concentration source/drain impurity layer109bformed in an upper portion of the silicon layer109. The impurity concentration of the high-concentration source/drain impurity layer109bis set to be higher than that of the LDD impurity layer109a. Also, the silicon layer109is formed at the same time as the silicon layer8of the memory cell region using a selective epitaxial growth method.

Also, as shown inFIG. 13B, a first interlayer insulating layer4and a second interlayer insulating layer10are formed on the semiconductor substrate1, and contact plugs10B are formed through the first interlayer insulating layer4and the second interlayer insulating layer10. The contact plugs10B are formed by stacking a W layer on a barrier layer formed of TiN/Ti. The contact plugs10B and the bit line contact plugs10A of the memory cell region may be formed at the same time. An interconnection layer6B is formed on the contact plugs10B using the same interconnection layer as the bit lines6of the memory cell region and connected to the contact plugs10B.

A third interlayer insulating layer21is formed to cover the interconnection layer6B. A fourth interlayer insulating layer22and a fifth interlayer insulating layer30are formed on the third interlayer insulating layer21, and a metal interconnection layer31is formed on the fifth interlayer insulating layer30. Peripheral contact plugs22B are formed through the third interlayer insulating layer21, the fourth interlayer insulating layer22, and the fifth interlayer insulating layer30to connect between the interconnection layer6B and the metal interconnection layer31.

A method of fabricating the semiconductor device of the present embodiment will be described with reference toFIGS. 14A through 20B.FIGS. 14A through 20Aare schematic cross-sectional views corresponding to line A-A′ of the memory cell region (ofFIG. 11), andFIGS. 14B through 20Bare schematic cross-sectional views corresponding to line B-B′ of the peripheral circuit region (ofFIG. 12). Furthermore, unless expressly defined herein, a process of fabricating the MOS transistor Tr1of the memory cell and a process of fabricating the MOS transistor Tr2of the peripheral circuit will now be simultaneously described.

First, as shown inFIGS. 14A and 14B, to define an active region K in a main surface of a semiconductor substrate1formed of P-type (or second conductivity type) silicon, isolation regions3with an insulating layer, such as a SiO2layer, buried therein are formed in the entire portion other than the active region K using an STI method.

As shown inFIG. 14A, groove patterns2for gate electrodes are formed in the memory cell region. The groove patterns2are formed by anisotropically dry-etching the silicon of the semiconductor substrate1using a photoresist layer (not shown) as a mask.

The silicon surface of the semiconductor substrate1is oxidized using a thermal oxidation method to form SiO2, thereby forming a gate insulating layer5ato a thickness of about 4 nm in a transistor forming region. The gate insulating layer5amay be a stacked layer of SiO2and Si3N4or a high-k layer.

A poly-Si layer containing N-type (or first conductivity type) impurities is formed on the gate insulating layer5aby a CVD process using mono-silane (SiH4) and phosphine (PH3) as source gases. In this case, in the memory cell region, the thickness of the poly-Si layer is set to completely fill the insides of the groove patterns2for gate electrodes with the poly-Si layer. Alternatively, a poly-Si layer is formed not to contain impurities, such as P, and desired impurities, such as P, may be implanted into the poly-Si layer using an ion implantation process in a subsequent process. Next, a metal layer formed of a metal having a high melting point, such as W, WN, or WSi, is deposited on the poly-Si layer to a thickness of about 50 nm using a sputtering method. The poly-Si layer and the metal layer are formed in gate electrodes5and105through a process described below.

A plasma CVD method is performed using SiH4and ammonia (NH3) as source gases so that an insulating layer5ccan be formed of Si3N4to a thickness of about 70 nm on the metal layer constituting the gate electrodes5and105. Next, a photoresist layer (not shown) is coated on the insulating layer5cand patterned by a photolithography method using a mask for forming the gate electrodes5and105, thereby forming a photoresist pattern for forming the gate electrodes5and105. Thus, the insulating layer5cis anisotropically etched using the photoresist pattern as a mask. After the photoresist pattern is removed, the metal layer and the poly-Si layer are etched using the insulating layer5cas a hard mask, thereby forming the gate electrodes5and105.

Thereafter, in a state where the entire memory cell region is covered with a pattern of a photoresist layer and the peripheral circuit region is exposed, B ions are implanted as P-type (or second conductivity type) impurities. Thus, a pocket impurity layer108ais formed in the surface of the semiconductor substrate1in the peripheral circuit region. The ion implantation conditions may be set as in the first embodiment. A state of the pocket impurity layer108aformed in the surface of the semiconductor substrate1is shown inFIGS. 15A and 15B.

As shown inFIGS. 16A and 16B, a Si3N4layer is deposited using an LPCVD process on the entire surface to a thickness of about 10 to 15 nm, and etched back to form first insulating-layer sidewalls5bon lateral walls of the gate electrodes5and105.

In a state where a pure silicon layer is exposed on the surface of the active region K formed in the semiconductor substrate1, silicon layers8and109are simultaneously formed using an SEG process to a thickness of about 30 to 50 nm. For example, the SEG process may be a selective CVD process performed using hydrogen chloride (HCl) and SiH2Cl2as reactive gases in a hydrogen (H2) atmosphere set at a temperature of about 800° C. The silicon layers8and109are formed and deposited upward on regions of the active region K uncovered by the gate electrodes5and105, and simultaneously, formed to have some extensions in a traverse direction in regions undefined by the first insulating-layer sidewalls5bas shown inFIGS. 16A and 16B.

In a state where the memory cell region is covered with a photoresist layer (not shown) and the peripheral circuit region is exposed, P ions are implanted as N-type (or first conductivity type) impurities, thereby forming an LDD impurity layer109ain the silicon layer109formed in the peripheral circuit region. The ion implantation condition may be set as in the first embodiment. During the ion implantation, ion implantation energy is set such that a projected range (Rp) for ion implantation lies midway along the thickness of the silicon layer109.

A Si3N4layer is deposited using an LPCVD process on the entire surface to a thickness of about 20 to 30 nm, and an etch-back process is performed to form second insulating-layer sidewalls5don lateral surfaces of the first insulating-layer sidewalls5b.

Similarly, in a state where the memory cell region is covered with a photoresist layer (not shown) and the peripheral circuit region is exposed, As ions are implanted as N-type (first conductivity type) impurities. Thus, a high-concentration source/drain impurity layer109bis formed in the silicon layer109formed in the peripheral circuit region. The ion implantation condition may be set as in the first embodiment. During the ion implantation process, ion implantation energy is set such that a projected range (Rp) for ion implantation ranges from a midway point in the thickness of the silicon layer109to the top surface of the silicon layer109. Also, the impurity concentration of the high-concentration source/drain impurity layer109bis set to be higher than that of the LDD impurity layer109a. Subsequently, activation annealing of impurities is performed using an RTA process in a short period of time (about 5 to 10 seconds). The RTA conditions may be set as in the first embodiment.

Thus, as shown inFIGS. 17A and 17B, a source108S and a drain108D of the MOS transistor Tr2of the peripheral circuit region are formed.

As shown inFIGS. 18A and 18B, a first interlayer insulating layer4is formed of SiO2using a CVD method to a thickness of, for example, about 600 nm to cover the gate electrodes5and105and the silicon layers8and109. Thereafter, to planarize roughness originating from the gate electrodes5and105, the first interlayer insulating layer4is polished using a CMP method to a thickness of, for example, about 300 nm.

Subsequently, openings (or contact holes)4A-a,4A-b, and4A-c are formed using an ordinary method in positions corresponding to substrate contacts205a,205b, and205cof the memory cell region (ofFIG. 11) to partially expose the surface of the silicon layer8of the memory cell region.

Subsequently, N-type (or first conductivity type) impurity ions are implanted via the openings4A-a,4A-b, and4A-c to form a cell impurity layer8ain the silicon layer8and the surface of the semiconductor substrate1. For example, when P ions are used, the ion implantation process may be performed at an energy of about 25 KeV to 40 KeV with a dose of 1×1013atoms/cm2to 6×1013atoms/cm2. The impurity concentration of the cell impurity layer8ais set to be lower than that of the LDD impurity layer109aof the peripheral circuit region. Furthermore, when the cell impurity layer8ais formed in the silicon layer8and both sides of the surface of the semiconductor substrate1, an ion implantation process may be performed plural times by varying ion implantation energy. Activation annealing may be performed on the cell impurity layer8ain a short period of time during activation annealing of impurities performed on the MOS transistor Tr2of the peripheral circuit region.

Also, in consideration of the influence of annealing of a subsequent fabrication process, the cell impurity layer8amay be formed in the surface portion of the semiconductor substrate1due to thermal diffusion from the silicon layer8. Thus, a source8S and a drain8D of the MOS transistor Tr1of the memory cell region are formed.

As a result, source and drain electrodes of the MOS transistor of the memory cell region are formed independently of the peripheral circuit region so that characteristics of the MOS transistor Tr1can be optimized and an off-state leakage current can be reduced.

By reducing the impurity concentration of the source8S and the drain8D formed in the memory cell region, although the source8S and the drain8D may also be formed to as shallow a depth as possible from the surface of the semiconductor substrate, good refresh characteristics may be obtained.

Substrate contact plugs4A are formed to fill the openings4A-a,4A-b, and4A-c. The formation of the substrate contact plugs4A is performed by forming a phosphorus-doped poly-Si layer on the entire surface and polishing the phosphorus-doped poly-Si layer using a CMP method until the surface of the first interlayer insulating layer4is exposed.

Substrate contact plugs4A are formed to fill the openings4A-a,4A-b, and4A-c. The formation of the substrate contact plugs4A is performed by forming a phosphorus-doped poly-Si layer on the entire surface and polishing the phosphorus-doped poly-Si layer using a CMP method until the surface of the first interlayer insulating layer4is exposed.

Openings are formed and filled with a layer obtained by stacking a W layer on a barrier layer formed of TiN/Ti, thereby forming bit line contact plugs10A and contact plugs10B using an ordinary method. The bit line contact plug10A is connected to the substrate contact plug4A (or a plug of the substrate contact205aformed in the center of the active region) in the memory cell region, and the contact plug10B is connected to the silicon layer109in the peripheral circuit region. The bit line contact plug10A and the contact plugs10B may be formed simultaneously or through separate processes. The resultant structure in which the bit line contact plug10A and the contact plugs10B are formed is illustrated inFIGS. 19A and 19B.

As shown inFIGS. 20A and 20B, a stacked layer of a WN layer and a W layer is deposited and patterned to form a bit line6connected to the bit line contact plug10A in the memory cell region and simultaneously, faun interconnection layers6B connected to the contact plugs10B in the peripheral circuit region. Next, a third interlayer insulating layer21is formed of SiO2to cover the bit line6of the memory cell region and the interconnection layers6B of the peripheral circuit region. Subsequently, capacitor contact plugs21A are formed to be connected to the substrate contact plugs4A (or plugs of the substrate contacts205band205cformed in end portions of the active region) in the memory cell region. The capacitor contact plug21may be formed by filling an opening with a layer obtained by stacking a W layer on a barrier layer formed of TiN/Ti.

Thereafter, as shown inFIGS. 13A and 13B, a fourth interlayer insulating layer22is formed of SiO2. Next, capacitor elements24are formed in the memory cell region. The capacitor element24may be formed by interposing a capacitor insulating layer24bformed of a high-k material, such as HfO2, ZrO2, or Al2O3between a lower electrode24aand an upper electrode24cthat are formed of TiN.

A fifth interlayer insulating layer30is formed of SiO2. Peripheral contact plugs22B are formed to be connected to the interconnection layers6B in the peripheral circuit region. A leading contact plug (not shown) for applying an electric potential to the upper electrode24cof the capacitor element24is formed in the memory cell region. Thereafter, upper metal interconnection layers31are formed of Al or Cu. The metal interconnection layers31are connected to the peripheral contact plugs22B in the peripheral circuit region. Subsequently, as shown inFIGS. 13A and 13B, a surface protection layer32is formed of SiON, thereby completing fabrication of a DRAM device as a semiconductor device.

In the present embodiment, although a case where the MOS transistor Tr2of the peripheral circuit is an N-channel transistor has been described, a P-channel MOS transistor to which the present invention is applied may be formed in the same manner and constitute a CMOS circuit. In this case, an N-type well is formed beforehand in a region of the semiconductor substrate1where the P-channel transistor will be formed. Thus, N-type impurities, such as P, may be implanted to form the pocket impurity layer108a, P-type impurities, such as B, are implanted to form the LDD impurity layer109a, and P-type impurities, such as BF2, may be implanted to form the high-concentration source/drain impurity layer109b.

Since the ion implantation conditions described in the present embodiment are only an example, changes in ion implantation energy, dose, and kind of ions may be made without departing from the spirit and scope of the present invention. Also, materials and thicknesses of the insulating layer and the gate electrode may be changed.

In the DRAM device formed according to the present invention, the MOS transistor disposed in the peripheral circuit region is the MOS transistor of the first embodiment of the present invention. Accordingly, it is possible to suppress the short channel effect of the MOS transistor of the peripheral circuit region, thereby easily keeping up with high-integration and high-performance of devices. Therefore, highly efficient DRAM devices having fast response and long-term reliability can be easily fabricated.

As used herein, the following directional terms “forward, rearward, above, downward, vertical, horizontal, below, and transverse” as well as any other similar directional terms refer to those directions of an apparatus equipped with the present invention. Accordingly, these terms, as utilized to describe the present invention should be interpreted relative to an apparatus equipped with the present invention.

Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.