Method for fabricating bump structure without UBM undercut

A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile.

TECHNICAL FIELD

This disclosure relates to the fabrication of semiconductor devices, and more particularly, to a method of forming a bump structure without of under-bump metallurgy (UBM) undercut.

BACKGROUND

Modern integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding. In a typical bumping process, interconnect structures are formed on metallization layers, followed by the formation of under-bump metallurgy (UBM), and the mounting of solder balls.

Flip-chip packaging utilizes bumps to establish electrical contact between a chip's I/O pads and the substrate or lead frame of the package. Structurally, a bump actually contains the bump itself and a so-called under bump metallurgy (UBM) located between the bump and an I/O pad. An UBM generally contains an adhesion layer, a barrier layer and a wetting layer, arranged in this order on the I/O pad. The bumps themselves, based on the material used, are classified as solder bumps, gold bumps, copper pillar bumps and bumps with mixed metals. Recently, copper interconnect post technology is proposed. Instead of using solder bump, the electronic component is connected to a substrate by means of copper post. The copper interconnect post technology achieves finer pitch with minimum probability of bump bridging, reduces the capacitance load for the circuits and allows the electronic component to perform at higher frequencies. A solder alloy is still necessary for capping the bump structure and jointing electronic components as well.

Usually, in wet etching the UBM Cu layer, an isotropic etch profile is produced, in which the etching is at the same rate in all directions, leading to undercutting of the etched Cu material. This action results in an undesirable loss of line width. The undercut caused by wet Cu etching process will induce the stress concentration, resulting in bump sidewall delamination and bump crack. Although the undercut is an inherent result of the etching process, the undercut is detrimental to the long-term reliability of the interconnection. The undercut compromises the integrity of the solder bump structure by weakening the bond between the solder bump and the bonding pad of the chip, thereby leading to premature failure of the chip.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

This disclosure provides a bump process used in semiconductor devices having solder bumps, Cu posts, post passivation interconnects, and/or through-silicon vias (TSVs) fabricated thereon, applied to flip-chip assembly, wafer-level chip scale package (WLCSP), three-dimensional integrated circuit (3D-IC) stack, and/or any advanced package technology fields. In the following description, numerous specific details are set forth to provide a thorough understanding of the disclosure. However, one having an ordinary skill in the art will recognize that the disclosure can be practiced without these specific details. In some instances, well-known structures and processes have not been described in detail to avoid unnecessarily obscuring the disclosure. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.

Herein, cross-sectional diagrams ofFIGS. 1 to 7depicting an exemplary embodiment of a method of forming a bump structure without UBM undercut.

With reference toFIG. 1, an example of a substrate10used for bump fabrication may comprise a semiconductor substrate as employed in a semiconductor integrated circuit fabrication, and integrated circuits may be formed therein and/or thereupon. The semiconductor substrate is defined to mean any construction comprising semiconductor materials, including, but is not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used. The substrate10may further comprise a plurality of isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation features may define and isolate the various microelectronic elements (not shown). Examples of the various microelectronic elements that may be formed in the substrate10include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.); resistors; diodes; capacitors; inductors; fuses; and other suitable elements. Various processes are performed to form the various microelectronic elements including deposition, etching, implantation, photolithography, annealing, and other suitable processes. The microelectronic elements are interconnected to form the integrated circuit device, such as a logic device, memory device (e.g., SRAM), RF device, input/output (I/O) device, system-on-chip (SoC) device, combinations thereof, and other suitable types of devices.

The substrate10further includes inter-layer dielectric layers and a metallization structure overlying the integrated circuits. The inter-layer dielectric layers in the metallization structure include low-k dielectric materials, un-doped silicate glass (USG), silicon nitride, silicon oxynitride, or other commonly used materials. The dielectric constants (k value) of the low-k dielectric materials may be less than about 3.9, or less than about 2.8. Metal lines in the metallization structure may be formed of copper or copper alloys. One skilled in the art will realize the formation details of the metallization layers. A contact region12is a top metallization layer formed in a top-level inter-layer dielectric layer, which is a portion of conductive routs and has an exposed surface treated by a planarization process, such as chemical mechanical polishing (CMP), if necessary. Suitable materials for the conductive region12may include, but are not limited to, for example copper (Cu), aluminum (Al), AlCu, copper alloy, or other mobile conductive materials. In one embodiment, the contact region12is a metal pad region12, which may be used in the bonding process to connect the integrated circuits in the respective chip to external features.

FIG. 1also depicts a passivation layer14formed on the substrate10and patterned to form a first opening15exposing a portion of the metal pad region12for allowing subsequent bump formation. In one embodiment, the passivation layer14is formed of a non-organic material selected from un-doped silicate glass (USG), silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof. In another embodiment, the passivation layer14is formed of a polymer layer, such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, although other relatively soft, often organic, dielectric materials can also be used.

FIG. 1further depicts a polymer layer16that is formed on the passivation layer14and patterned to form a second opening17exposing a portion of the metal pad region12for allowing subsequent bump formation. The second opening17may be smaller than, equal to, or greater than the first opening15. In one embodiment, the second opening17is positioned within the first opening15. The polymer layer16, as the name suggests, is formed of a polymer, such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, although other relatively soft, often organic, dielectric materials can also be used. In one embodiment, the polymer layer16is a polyimide layer. In another embodiment, the polymer layer16is a polybenzoxazole (PBO) layer. The polymer layer16is soft, and hence has the function of reducing inherent stresses on substrate. In addition, the polymer layer16is easily formed to thickness of tens of microns.

Referring toFIG. 2, the formation of a first under-bump-metallurgy (UBM) layer18is performed on the resulting structure. In details, the first UBM layer18is formed on the polymer layer16and the exposed portion of the metal pad region12, and lines the sidewalls and bottom of the second opening17. The first UBM layer18, also referred to as a diffusion barrier layer, may be formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), or the like. The formation methods include physical vapor deposition (PVD) or sputtering. The first UBM layer18is deposited to a thickness of between about 500 and 2000 angstrom and more preferably to a thickness of about 1000 Angstrom.

Next, inFIG. 3, a mask layer20is provided on the first UBM layer18and patterned with a third opening21exposing a portion of the first UBM layer18for bump formation. The diameter of the third opening21is greater or equal to the diameter of the second opening17. The mask layer20is a dry film or a photoresist film through the steps of coating, curing, descum and the like, followed by lithography technology and etching processes such as a dry etch and/or a wet etch process.

With reference toFIG. 4, a second UBM layer22is selectively formed on the first UBM layer18within the opening21of the mask layer20through an electroless deposition. In one embodiment, an electroless Cu deposition is performed to selectively plate a Cu layer on the exposed portion of the first UBM layer18. The second UBM layer22has a thickness about 1˜10 um, for example about 4˜6 um, although the thickness may be greater or smaller.

In the electroless Cu plating, Palladium (Pd) is often used as the activated base metal for electroless copper plating. After activation, electroless deposition of Cu occurs on the catalytic surface. In general, the coverage of the Cu deposit reaches 100% and the adsorptive amount of Pd is greatly increased by the conditioning process. However, in order to insure uniformity, the diffusion barrier layer must substantially be free of any metal oxide they may have formed prior to the electroless Cu plating process.

FIGS. 4A and 4Bdepicts an exemplary embodiment of performing an electroless Cu deposition on the first UBM layer18. Once the substrate10has been transferred to the chamber for deposition, an activation or initiation step is performed. In some embodiments, the activation or initiation step is a palladium (Pd) activation or Pd initiation. The pretreatments used in the Cu electroless plating process include the removal of the titanium oxide (TiO2) layer24from the diffusion barrier layer18using a HF solution, and the deposition of a Pd layer26to activate the diffusion barrier layer18. Then an electroless plated Cu layer28on the non-uniform or rough Pd layer26exhibits high resistivity and RMS roughness. Thus the second UBM layer22includes a Cu UBM layer28and a Pd layer26. Alternatively, the second UBM layer22is referred to as a Cu layer including Pd elements. The Pd element is detected at the interface between the first UBM layer18and the second UBM layer28by ICP and/or SEM-EDX.

Referring toFIG. 5, a solder layer30is then formed on the second UBM layer22within the opening21of the mask layer20. The solder layer30may be made of Sn, SnAg, Sn—Pb, SnAgCu (with Cu weight percentage less than 0.3%), SnAgZn, SnZn, SnBi—In, Sn—In, Sn—Au, SnPb, SnCu, SnZnIn, or SnAgSb, etc. Next, as shown inFIG. 6, the mask layer20is removed, exposing a portion of the first UBM layer18. In the case the mask layer20is a dry film, it may be removed using an alkaline solution. If the mask layer20is formed of photoresist, it may be removed using acetone, n-methyl pyrrolidone (NMP), dimethyl sulfoxide (DMSO), aminoethoxy ethanol, and the like.

With reference toFIG. 7, the exposed portion of the first UBM layer18is etched back using the solder layer30as a mask by a conventional wet and/or dry etching process depending on the metallurgy of the first UBM metallurgy. Standard reactive ion etch (RIE) procedures can be used to etch the first UBM layer18. A solder reflow process may be optionally performed on the solder layer30. The substrate10is then sawed and packaged onto a package substrate, or another die, with solder balls or Cu bumps mounted on a pad on the package substrate or the other die.

The completed bump structure32includes the first UBM layer18, the second UBM layer22and the solder layer30, in which the second UBM layer22is a Cu layer containing Pd elements. Compared with conventional bump processes, this disclosure provides a method of selectively forming the second UBM layer22by an electroless Cu deposition process after the formation of the mask layer20. There is no need to perform a wet etching process on the second UBM layer22after stripping the mask layer20, thus the resulted UBM scheme has an undercut-free profile.

FIGS. 8 to 10are cross-sectional diagrams depicting an exemplary embodiment of forming a Cu post bump structure without UBM undercut, while explanation of the same or similar portions to the description inFIGS. 1 to 7will be omitted.

After the formation of the second UBM layer22as depicted inFIG. 4, the opening21is then partially filled with a conductive material with solder wettability. With reference toFIG. 8, a copper (Cu) layer34is formed in the opening21to contact the underlying second UBM layer22. The Cu layer34is intended to include substantially a layer including pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium. The formation methods may include sputtering, printing, electro plating, electroless plating, and commonly used chemical vapor deposition (CVD) methods. For example, electro-chemical plating (ECP) is carried out to form the Cu layer28. In an exemplary embodiment, the thickness of the Cu layer34is greater than 30 um. In another exemplary embodiment, the thickness of the Cu layer34is greater than 40 um. For example, the Cu layer34is of about 40˜50 um thickness, or about 40˜70 μm thickness, although the thickness may be greater or smaller. The Cu layer34is referred to as a Cu post34hereinafter.

Next, a cap layer40is formed on the top surface of the Cu post34. The cap layer36could act as a barrier layer to prevent copper in the Cu post34to diffuse into bonding material, such as solder alloy, that is used to bond the substrate10to external features. The prevention of copper diffusion increases the reliability and bonding strength of the package. The cap layer34may include nickel, tin, tin-lead (SnPb), gold (Au), silver, palladium (Pd), In, nickel-palladium-gold (NiPdAu), nickel-gold (NiAu), other similar materials, or alloys. The cap layer34is a multi-layered structure or a single-layered structure. In some embodiments as depicted inFIG. 8, the cap layer40includes a first cap layer36and a second cap layer38. The first cap layer36is a nickel layer with a thickness about 1˜5 um. The second cap layer38is a solder layer or a gold (Au) layer.

Next, as shown inFIG. 9, the mask layer20is removed, exposing a portion of the first UBM layer18. The exposed portion of the first UBM layer18is etched back using the Cu post34and the cap layer40as a mask by a conventional wet and/or dry etching process depending on the metallurgy of the first UBM metallurgy, as shown inFIG. 10. A solder reflow process may be optionally performed depending on the material of the cap layer40. The substrate10is then sawed and packaged onto a package substrate, or another die, with solder balls or Cu bumps mounted on a pad on the package substrate or the other die.

The completed bump structure42includes the first UBM layer18, the second UBM layer22, the Cu post34, and the cap layer40, in which the second UBM layer22is a Cu layer containing Pd elements. Compared with conventional bump processes, this disclosure provides a method of selectively forming the second UBM layer22by an electroless Cu deposition process after the formation of the mask layer20. There is no need to perform a wet etching process on the second UBM layer22after stripping the mask layer20, thus the resulted UBM scheme has an undercut-free profile.

In the preceding detailed description, the disclosure is described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications, structures, processes, and changes may be made thereto without departing from the broader spirit and scope of the disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not restrictive. It is understood that the disclosure is capable of using various other combinations and environments and is capable of changes or modifications within the scope of the inventive concepts as expressed herein.