Semiconductor package and method of manufacturing the same

A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2018-0090056, filed on Aug. 1, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Inventive concepts relate to a semiconductor package and a method of manufacturing the same, and more particularly, a semiconductor package that includes a molding member surrounding a semiconductor chip and a method of manufacturing the same.

Nowadays, as demand on portable devices in the electronic product market has been rapidly increasing, there have been continuous requirements for small sizes and light weights of electronic components mounted on electronic products. For small sizes and light weights of electronic components, decreased sizes and capability of processing high capacity data are required by a semiconductor package loaded in the electronic components. Semiconductor chips loaded in such semiconductor packages are covered by being surrounded by molding members. In general, positions of fillers included in a molding member are fixed when the materials are randomly mixed, and thus, it is very difficult to selectively change the positions of the fillers in the molding member according to a type of a semiconductor package.

SUMMARY

Inventive concept provide, to efficiently protect semiconductor chips in a semiconductor package structure, a semiconductor package in which positions of fillers may be controlled in a molding member by using an electric field and/or a magnetic field.

Inventive concepts also provide, to efficiently protect semiconductor chips in a semiconductor package structure, a method of manufacturing a semiconductor package in which positions of fillers may be controlled in a molding member by using an electric field and/or a magnetic field.

Features and effects of inventive concepts are not limited to those described above, and other features and effects may be clearly understood to one of ordinary skill in the art by descriptions below.

According to an aspect of inventive concepts, a semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the semiconductor chip and including fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions that respectively have different distributions of the fillers.

According to another aspect of inventive concepts, a semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the semiconductor chip. The molding member includes fillers distributed in an epoxy material. Each of the fillers includes a core and a coating layer that covers the core. The core is a non-electromagnetic material and the coating layer is an electromagnetic material. The fillers are configured to be moved in a certain direction in the molding member by an electric field or a magnetic field that may be applied to the molding member, and the molding member includes regions respectively having different distributions of the fillers.

According to another aspect of inventive concepts, a method of manufacturing a semiconductor package includes mounting at least one semiconductor chip on a package substrate, coating a molding material including fillers on the package substrate to surround the at least one semiconductor chip, moving the fillers in a certain direction in the molding material by applying an electric field or a magnetic field to the molding material, and forming a molding member by curing the molding material. The fillers each include a core and a coating layer that surrounds the core. The core is a non-electromagnetic material, and the coating layer is an electromagnetic material that surrounds the core.

DETAILED DESCRIPTION

Hereinafter, embodiments of inventive concepts will be described in detail with reference to attached drawings.

FIG. 1is a cross-sectional view of a semiconductor package10according to an embodiment of inventive concepts.

Referring toFIG. 1, the semiconductor package10includes a package substrate100, a semiconductor chip200mounted on the package substrate100, and a molding member300that surrounds the semiconductor chip200.

The package substrate100, which is a supporting substrate, may include a body110, a lower protection layer, and an upper protection layer. The package substrate100may be formed based on a printed circuit board (PCB), a wafer substrate, a ceramic substrate, a glass substrate, an interposer substrate, and the like. In an embodiment according to inventive concepts, the package substrate100may be a PCB. However, the package substrate100is not limited to a PCB.

Meanwhile, an interconnect140is formed in the package substrate100, and the interconnect140may be electrically connected to the semiconductor chip200via at least one of a pillar structure, a solder bump, a solder ball, and a solder layer connected to an upper electrode pad120in an upper surface of the package substrate100.

In addition, an external connection terminal150may be placed at a lower electrode pad130in a lower surface of the package substrate100. The package substrate100may, via the external connection terminal150, be connected to a module substrate of an electronic device or a system board, via electrical connection.

The interconnect140is multi-layered or single-layered and may be formed in the body110, and the external connection terminal150and the semiconductor chip200may be electrically connected to each other via the interconnect140. The lower protective layer and the upper protective that protect the body110may, for example, include solder resist.

When the package substrate100is a PCB, the body110may generally be implemented by compressing a high-molecular material such as a thermosetting resin, an epoxy-based resin such as flame retardant 4 (FR-4), bismaleimide triazine (BT), and Ajinomoto Build up Film (ABF) in a certain thickness and forming the above-mentioned material, which is compressed, into a foil shape, coating copper foils on two surfaces of the foil shape, and forming, via patterning, the interconnect140that is a transmission path of electrical signals. Except for regions connected to terminals (the external connection terminals150and internal connection terminals250), for example, the upper electrode pads120and the lower electrode pads130, solder resist may be coated on the lower surface and the upper surface of the body110, and thus, the lower protective layer and the upper protective layer may be implemented.

A PCB may be classified into a single layer PCB in which the interconnect140is formed only in one surface of the PCB, and a double layer PCB in which the interconnect140is formed in two surfaces of the PCB. In addition, by using an insulator named prepreg, the copper foil may be designed to have at least three layers, and by forming at least three interconnects140according to the numbers of layers in the copper foil, a multi-layer PCB may be implemented. The package substrate100is not limited to the structure or materials of the PCB that is described above.

The semiconductor package10may have a structure in which the semiconductor chip200is mounted on the package substrate100. AlthoughFIG. 1shows the embodiment in which only one semiconductor chip200is mounted on the package substrate100, a plurality of semiconductor chips200may be mounted on the package substrate100.

The semiconductor chip200may be a memory chip or a logic chip.

The memory chip may be a volatile memory chip or a non-volatile memory chip. The volatile memory chip may include existing volatile memory chips, for example, dynamic random access memory (DRAM), static RAM (SRAM), thyristor RAM (TRAM), zero capacitor RAM (ZRAM), or twin transistor RAM (TTRAM), and volatile memory chips which are under development. The non-volatile memory chips may include existing non-volatile memory chips, for example, flash memory, magnetic RAM (MRAM), spin-transfer torque MRAM (SST-MRAM), ferroelectric RAM (FRAM), phase change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM, nano floating gate memory, holographic memory, molecular electronics memory, or insulator resistance change memory, and non-volatile memory chips under development.

The logic chip may be implemented, for example, as a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, or a system on chip (SoC), but the logic chip is not limited thereto. The microprocessor may, for example, include a single-core or a multi-core processor.

The semiconductor chip200may include a semiconductor substrate210, a semiconductor device layer220, lower connection pads230, a semiconductor interconnect layer240, and internal connection terminals250.

The semiconductor chip200may, in the semiconductor substrate210, have an active surface and an inactive surface that faces the active surface. The active surface in the semiconductor substrate210may be a surface that faces an upper surface of the package substrate100. A plurality of active/passive elements and the lower connection pads230may be formed in the active surface of the semiconductor substrate210.

The internal connection terminals250may be formed between the package substrate100and the active surface of the semiconductor chip200. The internal connection terminals250may respectively contact the lower connection pads230. The semiconductor chip200may be electrically connected to the package substrate100via the internal connection terminals250.

The semiconductor substrate210may include the semiconductor device layer220that is formed at the active surface of the semiconductor substrate210. The semiconductor interconnect layer240may be formed in the semiconductor device layer220and electrically connected to the internal connection terminals250via the lower connection pads230.

The semiconductor substrate210may, for example, include silicon. Alternatively, the semiconductor substrate210may include a semiconductor element such as germanium or a compound semiconductor like silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, the semiconductor substrate210may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate210may include a buried oxide (BOX) layer. The semiconductor substrate210may include a conductive region, for example, a well doped with an impurity or a structure doped with an impurity. In addition, the semiconductor substrate210may have various device isolation structures like a shallow trench isolation (STI) structure.

The semiconductor device layer220may include the semiconductor interconnect layer240that is used for connecting a plurality of individual devices to other interconnects formed in the semiconductor substrate210. The semiconductor interconnect layer240may include at least one metal interconnect layer and at least one via plug. For example, the semiconductor interconnect layer240may have a multi-layer structure in which at least two metal interconnect layers or at least two via plugs are alternately stacked.

The lower connection pads230may be placed on the semiconductor device layer220and electrically connected to the semiconductor interconnect layer240in the semiconductor device layer220. The semiconductor interconnect layer240may be electrically connected to the internal connection terminals250via the lower connection pads230. The lower connection pads230may, for example, include at least one of Al, Cu, Ni, W, Pt, and Au.

A passivation layer may be formed on the semiconductor device layer220to protect the semiconductor interconnect layer240on the semiconductor device layer220and another structure placed therebelow from external shocks or moisture. The passivation layer may expose at least a part of an upper surface of the lower connection pad230.

The internal connection terminals250may be respectively placed on the lower connection pads230. The internal connection terminals250may be used for electrically connecting the semiconductor chip200to the package substrate100. Via the internal connection terminals250, at least one of a control signal, a power signal, and a ground signal, which are signals for operations of the semiconductor chip200, may be provided from outside, a data signal that is to be stored in the semiconductor chip200may be provided from the outside, or data stored in the semiconductor chip200may be provided to the outside. The internal connection terminal250may, for example, include at least one of a pillar structure, a solder bump, a solder ball, and a solder layer.

The molding member300may be formed to surround sides, a lower surface, and an upper surface of the semiconductor chip200. However, unlike as shown inFIG. 1, the upper surface of the semiconductor chip200may be exposed via the upper surface of the molding member300.

The molding member300may, for example, be formed of epoxy molding compound. Epoxy molding compound may have a Young's Modulus from about 15 GPa to about 30 GPa and a coefficient of thermal expansion from about 3 ppm to about 30 ppm.

The molding member300is not limited to an epoxy molding compound and may also include various materials, for example, an epoxy material, a thermosetting material, a thermoplastic material, a UV-processed material, and the like. The thermosetting material may include a phenol type, an anhydride type, an amine type of curing agent and an acrylic polymer additive.

Meanwhile, the molding member300may be formed by using a molded underfill (MUF) process, and accordingly, a material covering an outer profile of the semiconductor chip200may be equal to a material that fills a region between the semiconductor chip200and the package substrate100. As shown, the internal connection terminals250may be placed between the semiconductor chip200and the package substrate100and the molding member300may surround the internal connection terminals250.

For the molding member300, an appropriate amount of molding material is injected onto the package substrate100by an injection process, and an outer shape of the semiconductor package10is formed by a curing operation. As needed, in a pressurization process, such as a press, the molding material may be pressed to form the outer shape of the semiconductor package10. In this case, process conditions such as a delay time between injection of the molding material and pressurization, an amount of the molding material that is injected, and pressurization temperature/pressure may be set considering a physical characteristic, for example, viscosity of the molding material.

A side and the top surface of the molding member300may have the form of a right angle which has an angle of about 90 degrees. In a process of cutting the package substrate100along dicing lines to make the semiconductor packages10, the side and the upper surface of the molding member300generally form a right angle. Although not shown, a marking pattern including data of the semiconductor chip (e.g., a bar code, a number, a character, a symbol, or the like) may be formed at a region of a side of the semiconductor package10.

The molding member300may protect the semiconductor chip200from external influences such as contamination and impacts. To do so, the molding member300may have a thickness which may, at least, completely surround the semiconductor chip200. As the molding member300completely surrounds the semiconductor chip200, a width of the molding member300may substantially be equal to a width of the semiconductor package10.

In addition, the molding member300, which is formed of epoxy molding compound, may include a large amount of fillers310in the epoxy molding compound. The fillers may be spherical. For example, the molding member300may be formed from an epoxy material including at least from about 50 wt % to about 90 wt % of the filler310. In this case, the filler310may be configured to have silica, which is a kind of silicon oxide, or an aluminum oxide-based material, as a core, and to include a coating layer313that surrounds the core311.

In an embodiment according to inventive concepts, the filler310may include a core, which is a non-electromagnetic material, and a coating layer313which is an electromagnetic material that surrounds the core311. The filler310may, to react to an electric field or a magnetic field, have the form of a sphere, a platelet, or a fiber, which are made by coating a metal, a metal oxide, a carbon material, a functional polymer, and the like. According to directions of the electric field or the magnetic field that is applied to the molding member300, flow and distribution of the filler310may be changed into desired directions.

In an embodiment according to inventive concepts, the molding member300may be employed as long as the molding member300includes the fillers310, regardless of the form of the molding member300such as powder, a granule, liquid, or a sheet.

More particularly, the coating layer313may include one of a metal, a metal oxide, a polymer, a polymer electrolyte, and a carbon composition material, and the coating layer313may be formed into a target structure by using a publicly known method such as a sol-gel method, a co-precipitation method, a thermal spray method, an emulsion method, a hydrothermal synthesis method, or a spray drying method.

The coating layer313may be formed from different materials according to a type of an external force applied to the molding member300. In some embodiments, the coating layer313may include one of a polymer, a polymer electrolyte, and a carbon composite material, which are materials reacting with the electric field. In other embodiments, the coating layer313may include one of a metal and a metal oxide which are materials reacting to the magnetic field.

Here, a case in which the coating layer313is formed from a material responding to the magnetic field is described in detail. The material that is included in the coating layer313and responds to the magnetic field may be construed not only as a material that has magnetism like a magnetic material that is magnetized but also as particles, such as iron or iron oxide, which are magnetized by the magnetic field and attracted to the magnetic field.

The coating layer313may be a powder particle that is formed of a ferromagnetic material, a soft magnetic material, or a paramagnetic material. The coating layer313may, for example, be iron oxide (FeO, Fe2O3, Fe2O4, Fe3O4), powder of ferrite materials such as Ni—Zn ferrite or Mn—Zn ferrite, permalloy, or sendust, and may include metal powder like nickel (Ni), zinc (Zn), manganese (Mn), cobalt (Co), magnesium (Mg), aluminum (Al), barium (Ba), copper (Cu), or iron (Fe). Alternatively, a mixture of ferrite powder and metal powder may be used for the coating layer313.

Particles of the material included in the coating layer313may have a granular structure of about 1 μm, several μms, or tens of μms.

In the molding member300, a region in which distribution of the fillers310is relatively high may be referred to as a filler dense layer RF, and a region in which distribution of the fillers310is relatively low may be referred to as an epoxy dense layer RE.

By using the electric field or the magnetic field, the fillers310may be controlled to be distributed in a localized region of the molding member300in a higher density than in other regions in the molding member300. As shown, the filler dense layer RF may be formed such that the fillers310are placed around the internal connection terminals250and have a relatively high distribution in a region between the semiconductor chip200and the package substrate100.

During or after a process of forming the molding member300including the fillers310, to surround the semiconductor chip200, the fillers310may be transmitted in a target direction in the molding member300by applying an electric field or a magnetic field to the molding member300.

The electric field unit420(seeFIG. 8A) and/or the magnetic field unit430(seeFIG. 8A) may be placed at the upper region or the lower region of the molding member300, and details thereof will be described hereinafter. In this case, the fillers310may be moved in a certain direction in the molding member300by the electric field that is formed by the electric field unit420(seeFIG. 8A) or the magnetic field that is formed by the magnetic field unit430(seeFIG. 8A). Accordingly, as shown inFIG. 1, the filler dense layer RF may be formed in the lower region of the molding member300, and the epoxy dense layer RE may be formed in the upper region of the molding member300.

Positions of the filler dense layer RF and the epoxy dense layer RE may be fixed by curing the molding member300. The curing may be thermosetting or photo-curing. The molding member300that is cured loses fluidity, and the positions of the filler dense layer RF and the epoxy dense layer RE may be maintained when the electric field unit420(seeFIG. 8A) and the magnetic field unit430(seeFIG. 8A) are removed.

Nowadays, as demand on portable devices in the electronic product market has been rapidly increasing, there have been continuous requirements for small sizes and light weights of electronic components loaded in electronic products. For small sizes and light weights of the electronic components, decreased sizes and capability of processing high capacity data are required by a semiconductor package loaded in the electronic components. Implementing high capacity memory in a limited structure of a semiconductor package requires a small thickness of semiconductor chip stack, and therefore, thicknesses of semiconductor packages are steadily decreasing. Semiconductor chips loaded in such semiconductor packages are protected by being surrounded by molding members.

In a common semiconductor package, which is different from the semiconductor package10according to inventive concepts, positions of fillers included in a molding member are fixed in a randomly mixed state, and accordingly, it is very difficult to selectively change the positions of the fillers in the molding member according to the type of the semiconductor package.

On the other hand, in the semiconductor package10according to inventive concepts, fillers310may be distributed in the molding member300, and in the process of forming the molding member300, the filler dense layer RF, which is a layer made by the fillers310placed in a high distribution, may be induced in a localized region of the molding member300by applying an electric field or a magnetic field to the molding member300that is maintained to be a fluid state or a liquid fluid state. Next, by curing the molding member300that has fluidity, the filler dense layer RF may be fixed in the molding member300, in a state of having fluidity.

In other words, in the semiconductor package10according to inventive concepts, positions of the fillers in the molding member300may be controlled by using the electric field or the magnetic field, and the semiconductor chips may be stacked in a small thickness, and as a result, a semiconductor package appropriate for high integration may be implemented.

Components included in the semiconductor packages20,30, and40to be described below and materials included in the components are substantially equal or similar to the components or materials described above with reference toFIG. 1. Therefore, for convenience of explanation, differences between the semiconductor package10(seeFIG. 1) and the semiconductor packages20,30, and40will be mainly described.

Referring toFIG. 2, in the semiconductor package20according to inventive concepts, the filler dense layer RF, which is a region in the molding member300where the fillers310are placed in a relatively high distribution, may be apart from the semiconductor chip200and placed at the upper region of the molding member300.

The fillers310may be moved in a certain direction in the molding member300by a force in a first direction (for example, a pulling force) of an electric field or a magnetic field. The fillers310may be controlled to be placed in a relatively high distribution in a localized region in the molding member300than in other regions in the molding member300. As it is shown inFIG. 2, the filler dense layer RF may be formed such that the fillers310are placed at an outermost region of the molding member300, and the epoxy dense layer RE may be formed such that the fillers310are placed in a relatively lower distribution at a peripheral region of the semiconductor chip200and a region between the semiconductor chip200and the package substrate100.

Positions of the filler dense layer RF and the epoxy dense layer RE may be fixed by curing the molding member300. When the electric field or the magnetic field is removed, the positions of the filler dense layer RF and the epoxy dense layer RE may be maintained.

Referring toFIG. 3, in the semiconductor package30according to inventive concepts, the filler dense layer RF, which is a region in the molding member300where the fillers310are placed in a relatively high distribution, may be placed at the peripheral region of the semiconductor chip200.

The fillers310may be moved in a certain direction in the molding member300by the force in the first direction of the electric field or the magnetic field. The fillers310may be controlled to be placed in a relatively high distribution in a localized region in the molding member300than in other regions in the molding member300. As shown, the filler dense layer RF may be formed such that the fillers310surround the peripheral region of the semiconductor chip200, and the epoxy dense layer RE may be formed such that the fillers310are placed in a relatively low distribution at an outer region of the semiconductor chip200except for the peripheral region of the semiconductor chip200.

The positions of the filler dense layer RF and the epoxy dense layer RE may be fixed by curing the molding member300. When the electric field or the magnetic field is removed, the positions of the filler dense layer RF and the epoxy dense layer RE may be maintained.

Referring toFIG. 4, in the semiconductor package40according to inventive concepts, the filler dense layer RF, which is a region in the molding member300where the fillers310are placed in a relatively high distribution, may be placed at the side wall regions of the molding member300.

The fillers310may be moved in a certain direction in the molding member300by the force in the first direction of the electric field or the magnetic field. The fillers310may be controlled to be placed in a relatively high distribution in a localized region in the molding member300than in other regions of the molding member300. As shown, the filler dense layer RF is formed such that the fillers310are placed at outermost regions of side walls of the molding member300, and the epoxy dense layer RE may be formed such that the fillers310are placed in a relatively low distribution in the peripheral region of the semiconductor chip200, the upper region of the molding member300, and the region between the semiconductor chip200and the package substrate100.

The positions of the filler dense layer RF and the epoxy dense layer RE may be fixed by curing the molding member300. When the electric field or the magnetic field is removed, the positions of the filler dense layer RF and the epoxy dense layer RE may be maintained.

In other words, the semiconductor packages20,30, and40according to inventive concepts, which are shown inFIGS. 2 through 4, may be configured to include the filler dense layers RF and the epoxy dense layers RF in positions that are different from the positions of the filler dense layer RF and the epoxy dense layer RF in the semiconductor package10(seeFIG. 1). As the fillers310may be moved in a certain direction in the molding member300due to the force in the first direction of the electric field or the magnetic field, the positions of the fillers310may be changed into target directions according to designs of the semiconductor packages.

FIGS. 5 and 6are cross-sectional views respectively showing semiconductor packages50and60according to other embodiments of inventive concepts.

Components included in the semiconductor packages50and60to be described below and materials in the components are substantially equal or similar to the components or materials described above with reference toFIG. 1. Therefore, for convenience of explanation, differences between the semiconductor package10(seeFIG. 1) and the semiconductor packages50and60will be mainly described.

Referring toFIG. 5, the semiconductor package50according to inventive concepts may have a first filler dense layer RF1, which is a region in the molding member300where the first fillers310are placed in a relatively high distribution, and a second filler dense layer RF2, which is a region in the molding member300where the second fillers320are placed in a relatively high distribution.

The first fillers310and the second fillers320, which are included in the molding member300included in the semiconductor package50, may respectively have a force in the first direction to the magnetic field and a force in a second direction (for example, a bouncing) that is opposite to the force in the first direction. Accordingly, the first fillers310and the second fillers320may be placed in different regions in the molding member300.

Meanwhile, materials included in the core311of the first fillers310may substantially be identical to materials included in the core321of the second fillers320. In addition, a diameter311D of the core311in the first fillers310may be substantially identical to a diameter321D of the core321in the second fillers320.

Differences between the first fillers310and the second fillers320may originate from coating layers. The material included in the coating layer313of the first fillers310may be different from the material included in the coating layer323of the second fillers320. However, in this case, a thickness313T of the coating layer313of the first fillers310may substantially be identical to a thickness323T of the coating layer323of the second fillers320.

More particularly, the material included in the coating layer313in the first fillers310may be a ferromagnetic material, and the material included in the coating layer323of the second fillers320may be a diamagnetic material. On the contrary, the material included in the coating layer313of the first fillers310may be a diamagnetic material, and the material included in the coating layer323of the second fillers320may be a ferromagnetic material.

A ferromagnetic material, for example, iron (Fe), cobalt (Co), and nickel (Ni), is a material which has a force in a first direction by being magnetized in a same direction as a direction of the magnetic field and maintains magnetism when the magnetic field is removed. On the other hand, a diamagnetic material, for example, copper (Cu), and gold (Au), is a material which has a force in a second direction by being magnetized in a direction that is opposite to the direction of the magnetic field and returns to an original state when the magnetic field is removed.

Therefore, by using the molding member300that includes the first fillers310and the second fillers320respectively having different characteristics, the first filler dense layer RF1, in which the first fillers310are placed in a relatively high distribution, and the second filler dense layer RF2, in which the second fillers320are placed in a relatively high distribution, may be placed in different regions in the molding member300. The epoxy dense layer RE may be placed between the first filler dense layer RF1and the second filler dense layer RF2.

In some embodiments, as shown, the first filler dense layer RF1may be placed in a region between the semiconductor chip200and the package substrate100and the second filler dense layer RF2may be apart from the semiconductor chip200and placed in the upper region of the molding member300. In other embodiments, although it is not shown, the first filler dense layer RF1may be placed at a region of a left side wall of the molding member300and the second filler dense layer RF2may be placed at a region of a right side wall of the molding member300. However, the placement of the first filler dense layer RF1and the second filler dense layer RF2is not limited thereto.

Referring toFIG. 6, the semiconductor package60according to inventive concepts may, in the molding member300, have a third filler dense layer RF3, in which third fillers330are placed in a relatively high distribution, and a fourth filler dense layer RF4, in which fourth fillers340are placed in a relatively high distribution.

The third fillers330and the fourth fillers340included in the molding member300included in the semiconductor package60may strongly react to the electric field weakly react to the electric field, respectively. In other words, the force in the first direction of the third fillers330with respect to the electric field may be greater than the force in the first direction of the fourth fillers340with respect to the electric field. Therefore, the third fillers330and the fourth fillers340may be placed in different regions in the molding member300.

Meanwhile, a core331of the third fillers330may include a material that is identical to a material included in a core341of the fourth fillers340. In addition, a diameter331D of the core331of the third fillers330may be substantially identical to a diameter341D of the core341of the fourth fillers340.

Differences between the third fillers330and the fourth fillers340may originate from coating layers. A thickness333T of a coating layer333of the third fillers330may be different from a thickness343T of a coating layer343of the fourth fillers340. However, in this case, the material included in the coating layer333of the third fillers330may be identical to the material included in the coating layer343of the fourth fillers340.

More particularly, all the materials included in the coating layer333of the third fillers330and the coating layer343of the fourth fillers340may be polyelectrolytes, and the third fillers330and the fourth fillers340may be manufactured by forming the thickness333T of the coating layer333of the third fillers330and a thickness343T of the coating layer343of the fourth fillers340to be different from each other.

Polyelectrolytes, for example, polystyrene, polyacrylate, polyallylamine hydrochloride, polylysine, are polymers having an electrolyte group in each repeat unit and being charged when dissolved in the water. Accordingly, polyelectrolytes exist in a positive charge state or a negative charge state and react to an electric field.

Therefore, by using the molding member300including the third fillers330and the fourth fillers340, which differently react to the electric field, the third filler dense layer RF3, in which the third fillers330are placed in a relatively high distribution, and the fourth filler dense layer RF4, in which the fourth fillers340are placed in a relatively high distribution, may be placed in different regions in the molding member300.

In some embodiments, as shown, the third filler dense layer RF3may be spaced apart from the semiconductor chip200and placed at an uppermost region in the upper region of the molding member300, and the fourth filler dense layer RF4may be placed under the third filler dense layer RF3in the upper region of the molding member300. An epoxy dense layer RE may be placed under the fourth filler dense layer RF4.

In other embodiments, although it is not shown, the third filler dense layer RF3may be placed at a lowermost end of a lower region of the molding member300and the fourth filler dense layer RF4may be placed on the third filler dense layer RF in the lower region of the molding member300. However, the placement of the third filler dense layer RF3and the fourth filler dense layer Rf4is not limited thereto.

In other words, the semiconductor packages50and60according to inventive concepts, which are shown inFIGS. 5 and 6, may be configured to include the filler dense layers RF and the epoxy dense layers RE in positions that are different from the positions of the filler dense layer RF and the epoxy dense layer RE in the semiconductor package10(seeFIG. 1).

In some embodiments, the first fillers310and the second fillers320may be formed to have coating layers respectively including different materials and, due to the magnetic field, may be moved in a certain direction in the molding member300. Therefore, according to the design of the semiconductor package, the positions of the first fillers310and the second fillers320may be controlled in target directions.

In some embodiments, the third fillers330and the fourth fillers340may be formed to have coating layers respectively having different thicknesses and, due to the electric field, may be moved into a certain direction in the molding member300. Therefore, according to the design of the semiconductor package, the positions of the third fillers330and the fourth fillers340may be controlled in target directions.

FIG. 7Ais a flowchart of a method of manufacturing a semiconductor package, according to an embodiment of inventive concepts, andFIG. 7Bis a group of graphs showing a process time in the method of manufacturing the semiconductor package according to an embodiment of inventive concepts.

Referring toFIG. 7A, the method of manufacturing a semiconductor package (S10) may include processes that are described below. When an embodiment is differently implemented, a certain process may be performed differently from the process that is described. For example, two processes that are described in succession may substantially be performed simultaneously, or the processes may be performed in an order that is opposite to an order of description.

The method of manufacturing the semiconductor package (S10) according to inventive concepts includes preparing a package substrate (S100), mounting at least one semiconductor chip on the package substrate (S200), coating, on the package substrate, a molding material having fillers each including a core including a non-electromagnetic material, and a coating layer including an electromagnetic material that covers the core, to surround the at least one semiconductor chip (S300), moving the fillers in certain directions within the molding material by applying an electric field or a magnetic field to the molding material (S400), and forming a molding member by curing the molding material (S500).

Technical features of each of the process will be described in detail with reference toFIGS. 8A through 9Dwhich will be described later.

In the method of manufacturing the semiconductor package S10(seeFIG. 7A) according to inventive concepts,FIG. 7Bshows a relationship between a processing time of applying an electric field or a magnetic field to a molding material T400and a processing time of hardening a molding material T500.

In some embodiments, after the process of applying the electric field or the magnetic field to the molding material, the process of curing the molding material may begin. In other words, a processing time of applying the electric field or the magnetic field to the molding material T400and a processing time of curing the molding material T500may be separated from each other.

In other embodiments, the process of applying the electric field or the magnetic field to the molding material may begin before the process of curing the molding material begins, and the process of applying the electric field or the magnetic field to the molding material and the process of curing the molding material may be finished at the same time. Alternatively, the process of applying the electric field or the magnetic field to the molding material may begin before the process of curing the molding material begins, and the process of curing the molding material may be finished after the process of applying the electric field or the magnetic field to the molding material is finished. In other words, the processing time of applying the electric field or the magnetic field to the molding material T400and the processing time of curing the molding material T500may at least partially overlap each other. However, the processing times T400and T500are not limited thereto.

FIGS. 8A through 8Dare cross-sectional views showing a method of manufacturing a semiconductor package, according to an embodiment.

Referring toFIG. 8A, a housing400that defines an internal region400S in which the molding member300(seeFIG. 8D) is to be formed is prepared, and the package substrate100, on which the semiconductor chip200is mounted, is placed in the internal region400S. The housing400may include the electric field unit420(e.g., RF generator) that generates an electric field and/or the magnetic field unit430(e.g., magnetron) that generates a magnetic field.

The molding member300(seeFIG. 8D) of the semiconductor package, which is formed by a transfer molding process, may be implemented according to the form that is defined by the housing400. Accordingly, the housing400may be previously determined according to the molding member300(seeFIG. 8D) that is to be formed.

Meanwhile, the housing400may include an injection path410, into which the molding material300M (seeFIG. 8B), and an ejection path (not shown), through which the molding material300M (seeFIG. 8B) filling the internal region400S of the housing400may be ejected.

Referring toFIG. 8B, the molding material300M may be injected into the internal region400S of the housing400. The molding material300M may include a large amount of the fillers310that are spherical and randomly scattered in epoxy molding compound. For example, the molding material300M may be formed from an epoxy based material including at least from about 50 wt % to about 90 wt % of the filler310.

The molding material300M is, in a fluid state, injected into the internal region400S of the housing400and may be injected until the internal region400S is completely filled. The process of injecting the molding material300M within the housing400may be performed in a vacuum condition.

By the injection process, an appropriate amount of the molding material300M is injected onto the package substrate100. As it is needed, via a pressurization process such as a press, a pressure may be applied to the molding material300M. In this case, process conditions such as a delay time between the injection of the molding material300M and pressurization, an amount of molding material300M that is injected, a pressurization temperature/pressure may be set considering a physical characteristic, for example, viscosity of the molding material300M.

The molding material300M is injected to fill the internal region400S without an empty region. Implementing high capacity memory in a limited structure of a semiconductor package requires a small thickness of semiconductor chip stack, and therefore, thicknesses of semiconductor packages are steadily decreasing. In the semiconductor package, a size of the internal connection terminal250also continually decreases, and a process of filling the region between the semiconductor chip200and the package substrate100may be very difficult to perform.

In the method of manufacturing the semiconductor package according to inventive concepts, when the molding material300M is injected, the electric field unit420to generate the electric field or the magnetic field unit430to generate the magnetic field may be operated, and the fillers310may, by the electric field or the magnetic field, be placed to fill between the semiconductor chip200and the package substrate100.

According to the movement of the fillers310, the molding material300M may move in a similar direction to the direction in which the fillers310move. In other words, by the electric field or the magnetic field, the fillers310are moved to be placed around the internal connection terminals250. Accordingly, the molding material300M, which may simultaneously be influenced by movements of the fillers310and an injection pressure, may be easily injected to surround the internal connection terminals250without an empty region.

Referring toFIG. 8C, after the internal region400S of the housing400is filled (e.g., completely filled) with the molding material300M, the molding material300M may be cured.

In the method of manufacturing the semiconductor package according to inventive concepts, after the molding material300M is injected, the electric field unit420to generate the electric field or the magnetic field unit430to generate the magnetic field may be operated, and the fillers310may, by the electric field or the magnetic field, be placed to fill between the semiconductor chip200and the package substrate100.

In this case, the filler310may be moved in a certain direction in the molding material300M by the force in the first direction between the electric field generated by the electric field unit420or between the magnetic field generated by the magnetic field unit430. Accordingly, as shown, the filler dense layer RF may be formed in the lower region of the molding material300M, and the epoxy dense layer RE may be formed in the upper region of the molding material300M.

Positions of the filler dense layer RF and the epoxy dense layer RE may be fixed by curing the molding material300M. The curing may be thermosetting or photo-curing. The molding material300M that is cured loses fluidity, and the positions of the filler dense layer RF and the epoxy dense layer RE may be maintained when the electric field or the magnetic field is removed.

By using the method of manufacturing the semiconductor package according to inventive concepts, the filler dense layer RF and the epoxy dense layer RE may respectively be formed in different regions within the molding material300M. As the fillers310may be moved in a certain direction in the molding member300due to the force in the first direction of the electric field or the magnetic field, the positions of the fillers310may be changed into target directions according to the design of the semiconductor package.

Unlike it is shown, the filler dense layer RF, which is the region in the molding material300M where the fillers310are placed in a relatively high distribution, may be spaced apart from the semiconductor chip200and placed in the upper region of the molding material300M, at the side wall regions of the molding material300M, or in the peripheral region of the semiconductor chip200.

Referring toFIG. 8D, a preparatory semiconductor package, in which the molding member300surrounding the semiconductor chip200is formed, may be manufactured on the package substrate100. The side and the top surface of the molding member300may have the form of a right angle which has an angle of about 90 degrees.

The preparatory semiconductor package, in which the molding member300is formed, may be separated from the housing400(seeFIG. 8C). Although it is not shown, a process of forming, at a region of the side of the molding member, a marking pattern including data of the semiconductor chip200, for example, a bar code, a number, a character, a symbol, and the like, may be performed.

FIGS. 9A through 9Dare cross-sectional views showing a method of manufacturing a semiconductor package, according to another embodiment;

Referring toFIG. 9A, a housing500, in which the molding member300(seeFIG. 9D) will be formed, may be prepared. The housing500may include a bottom housing500B and a top housing500T. The bottom housing500B is filled with the molding material300M, and the package substrate100, on which the plurality of semiconductor chips200are mounted, is placed in the top housing500T. The housing unit500may include an electric field unit520(e.g., RF generator) that generates an electric field and/or a magnetic field unit530(e.g., magnetron) that generates a magnetic field.

The molding member300(seeFIG. 9D) of the semiconductor package, which is formed by a compression molding process, may be implemented according to the form that is defined by the housing500. Accordingly, the housing500may be previously determined according to the molding member300(seeFIG. 9D) that is to be formed.

Meanwhile, the housing500may include the bottom housing500B that includes the molding material300M, and the top housing500T that includes, above the bottom housing500B, the package substrate100on which the plurality of semiconductor chips200are mounted.

Referring toFIG. 9B, the molding material300M may be moved into an internal region510of the housing500. The molding material300M may include a large amount of the fillers310that are spherical in epoxy molding compound. For example, the molding material300M may be formed from an epoxy based material including at least from about 50 wt % to about 90 wt % of the filler310.

The molding material300M is, in a fluid state, moved into the internal region510of the housing500and may be moved until the internal region510is completely filled with the molding material300M. The fillers310may be placed in a randomly scattered state in the molding material300M. In other words, the electric field unit520and/or the magnetic field unit530may not have generated an electric field or a magnetic field.

Referring toFIG. 9C, in the method of manufacturing the semiconductor package, when the molding material300M is moved, by operating the electric field unit420to generate the electric field or the magnetic field unit430to generate the magnetic field, the fillers310may be spaced apart from the plurality of semiconductor chips200due to the electric field or the magnetic field and placed in the upper region of the molding material300M.

In this case, the filler310may be moved in a certain direction in the molding material300M by the force in the first direction between the electric field generated by the electric field unit420or between the magnetic field generated by the magnetic field unit430. Accordingly, as shown, the filler dense layer RF may be formed in the upper region of the molding material300M, and the epoxy dense layer RE may be formed in the lower region of the molding material300M.

Positions of the filler dense layer RF and the epoxy dense layer RE may be fixed by curing the molding material300M. The curing may be thermosetting or photo-curing. The molding material300M that is cured loses fluidity, and the positions of the filler dense layer RF and the epoxy dense layer RE may be maintained when the electric field or the magnetic field is removed.

Unlike it is shown, the filler dense layer RF, which is the region in the molding material300M where the fillers310are placed in a relatively high distribution, may be placed to fill between the plurality of semiconductor chips200and the package substrate100, the filler dense layer RF may be placed at the side wall regions of the molding material300M, or alternatively, the filler dense layer RF may be placed in the peripheral region of the plurality of semiconductor chips200.

Referring toFIG. 9D, a preparatory semiconductor package, in which the molding member300surrounding the plurality of semiconductor chips200on the package substrate100, may be manufactured.

By a series of semiconductor processes, the preparatory semiconductor package may be provided in a form including the package substrate100, the plurality of semiconductor chip200, and the molding member300. By using a mechanical cutter or a razor cutter to perform a cutting process in dicing lines DL, semiconductor packages that are individually divided may be manufactured.

The dicing lines DL are used for dividing the preparatory semiconductor package into individual semiconductor packages. Accordingly, the side of the package substrate100and the side of the molding member300may substantially be placed on a same plane. In addition, the side and the top surface of the molding member300may have the form of a right angle which has an angle of about 90°.

FIGS. 10A through 10Care cross-sectional views showing warpage of a semiconductor package;

Referring together toFIGS. 10A through 10C, in the semiconductor package10, the plurality of semiconductor chips200are mounted on a top surface of the package substrate100, and the molding member300that surrounds the plurality of semiconductor chips200is formed. Accordingly, the top surface of the package substrate100is substantially and completely covered by the molding member300.

In the semiconductor package10having the above-described structure, materials included in the package substrate100, the plurality of semiconductor chips200, and the molding member300are different from one another and may have coefficients of thermal expansion that are different from one another. Accordingly, environmental changes in temperature, pressure, and the like during the process of manufacturing the semiconductor package10may result in warpage of the semiconductor package10.

For example, in the case of the package substrate100, under a room temperature or a high temperature, the molding member300may shrink or expand, thereby resulting in deformation such as warpage to the semiconductor package10. In addition, as shown inFIGS. 10A and 10B, when the fillers310included in the molding member300are arranged in a state of being randomly mixed-up, impacts to the fillers310may be ignored.

When coefficients of thermal expansion of the package substrate100and the molding member300in the semiconductor package10are different from each other, when a compressive stress is applied to the molding member300and a tensile stress is applied to the package substrate100, warpage may occur such that the semiconductor package10has a form in which a center region is curved downwards, as shown inFIG. 10A. On the other hand, when a tensile stress is applied to the molding member300and a compressive stress is applied to the package substrate100, warpage may occur such that the semiconductor package10has a form in which the center region is curved upwards, as shown inFIG. 10B. In other words, due to warpage of the semiconductor package10, the semiconductor package10may not be flat and there may be height differences WA and WB between the center region and the peripheral regions.

As shown inFIG. 10C, in the semiconductor package10according to inventive concepts, the coefficients of thermal expansion may be different in different regions according to distribution of the fillers310, and therefore, the coefficients of thermal expansion in the upper region and the lower region in the molding member300may be different from each other. Accordingly, by controlling the distribution of the fillers310in target directions, the warpage of the semiconductor package10may be alleviated compared to the warpage of the semiconductor package10that is described with reference toFIGS. 10A and 10B. In other words, when the fillers310are placed in a high distribution in the localized region of the molding member300, the warpage of the semiconductor package10may be alleviated due to influence of the fillers310. Although it is not shown, the fillers310in the molding member300may respectively include at least two kinds of materials having different coefficients of thermal expansion.

As a result, in the semiconductor package10according to inventive concepts, the positions of the fillers310are controlled by using an electric field or a magnetic field considering the coefficients of thermal expansion of the materials included in the package substrate100, the plurality of semiconductor chips200, and the molding member300, and thus, the tensile stress and the compressive stress applied to the semiconductor package10may be effectively controlled and the warpage of the semiconductor package10may be reduced and/or minimized.

FIG. 11is a top-plan view showing a semiconductor module1000including a semiconductor package1030according to an embodiment.

Referring toFIG. 11, the semiconductor module1000includes a module substrate1010, a control chip1020mounted on the module substrate1010, and a plurality of semiconductor packages1030mounted on the module substrate1010.

A plurality of input/output terminals1050, which may be coupled to sockets of a main board, are placed at one side of the module substrate1010. The plurality of semiconductor package1030may be the semiconductor packages10,20,30,40,50, and60according to inventive concepts. The plurality of semiconductor packages1030may be manufactured according to the method of manufacturing the semiconductor package (S10) according to inventive concepts.

FIG. 12is a schematic diagram showing a system1100of a semiconductor package that is manufactured in the method of manufacturing the semiconductor package according to the embodiments of inventive concepts.

Referring toFIG. 12, the system1100includes a controller1110, an input/output device1120, a memory1130, an interface1140, and a bus1150.

The system1100may be a system that transmits or receives data or a mobile system. In some embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

The controller1110, which is used for controlling programs executed in the system1100, may include a microprocessor, a digital signal processor, a microcontroller, or the like.

The input/output device1120may be used to input or output data of the system1100. The system1100is connected to an external device such as a personal computer or a network by using the input/output device1120and exchange data with the external device. The input/output device1120may, for example, be a touchpad, a keyboard, or a display.

The memory1130may store data for operation of the controller1110or data that is processed in the controller1110. The memory1130may be the semiconductor packages10,20,30,40,50, or60according to inventive concepts. In addition, the memory1130may be manufactured in the method of manufacturing the semiconductor package S10according to inventive concepts.

The interface1140may be a data transmission path between the system1100and an external device. The controller1110, the input/output device1120, the memory1130, and the interface1140may communicate with one another via the bus1150.

While inventive concepts has been particularly shown and described with reference to attached drawings, it will be understood by one of ordinary skill in the art that various changes in forms and details may be made therein without departing from the spirit and scope of inventive concepts. Hence, it will be understood that the embodiments described above are not limiting of the scope of inventive concepts.