Determining relative amount of usage of data retaining device based on potential of charge storing device

An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.

The current application is related to co-pending U.S. patent application Ser. No. 11/279,639, currently pending.

BACKGROUND OF THE DISCLOSURE

1. Technical Field

The disclosure relates generally to a usage of a data retaining device, and more particularly, to a method and system for determining a relative amount of usage of a data retaining device based on a potential of a charge storing device coupled to the data retaining device.

2. Background Art

An amount of usage of a data retaining device needs to be determined for various applications. For example, a multi-port cache is usually limited in size so that if the cache is full, some of the ports/word lines of the cache need to be refreshed to make room for new items. A cache replacement algorithm is usually used to select word lines to refresh. Examples of cache replacement algorithms include a Least Recently Used (LRU) algorithm which refreshes the least recently used word line first, and a Least Frequently Used (LFU) algorithm which refreshes the least frequently used word line first. These algorithms require keeping track of usage of a word line of the cache, which is very costly under the present state of the art technology.

Based on the above, there is a need in the art for a solution to determine a usage of a data retaining device in an inexpensive/efficient way.

SUMMARY OF THE DISCLOSURE

A first aspect of the disclosure provides a design structure embodied in a machine readable medium used in a design flow process, the design structure comprising a circuit, the circuit comprising: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.

A second aspect of the disclosure provides an integrated circuit comprising: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.

DETAILED DESCRIPTION

1. System Overview

FIG. 1shows a schematic diagram of one embodiment of a system10for determining a relative amount of usage of a data retaining device12. As shown inFIG. 1, data retaining sub-system11, e.g., a multi-port cache, includes multiple data retaining devices12(two are shown,12a,12b), e.g., ports/word lines of cache11. Each data retaining device12is coupled to a data access line14through a switch16(16a,16b, respectively). Each switch16is controlled/designed to act consistently with a corresponding switch18(18a,18b, respectively). According to one embodiment, specifically, a switch16and a corresponding switch18turn ON/OFF at substantially the same time, which is illustrated by a dotted line linking switches16and18. It should be appreciated that an activity of a switch18may be delayed from an activity of the corresponding switch16, which is controllable and is included in the current disclosure. It should be appreciated that switches16and18may include any mechanisms that control a connection and a disconnection between two components of a circuit.

A charge storing device20, e.g., capacitor (20a,20b), is couple between a charge source22(22a,22b, respectively), e.g., a positive voltage supply (VDD), and a ground24(24a,24b, respectively) through a switch18(18a,18b, respectively). Charge sources22may vary in value depending on, e.g., a weighting assigned to them, as will be described later. As such, in the following description, a charge source22will be referred to as a weighted charge source (WCS)22. Potentials, e.g., voltages, of capacitors20may be fed to comparator26as inputs to be compared therein.

The potential of a capacitor20and an output, e.g., a comparison result, of comparator26may be measured/obtained by a measuring device27. It is appreciated that measuring device27may include any mechanism[s] that is capable of measuring capacitor20potential and/or comparator26output.

In operation, when a data retaining device12, for example,12a, is accessed/used through data access line14, with switch16abeing turned on, the corresponding switch18ais also turned on, which enables a charging of capacitor20aby weighted charge source22a. As such, each use of data retaining device12atriggers a charging of capacitor20a, which causes an increase in the potential, e.g., voltage, of capacitor20a. On the other hand, during a period that data retaining device12aidles, with switches16aand18abeing turned off, charges on capacitor20adecay due to natural means, which causes a decrease in the voltage of capacitor20a. As a consequence, capacitor20ais functionally coupled to data retaining device12athrough the correspondence between switches16aand18a, and the potential, e.g., voltage, of capacitor20amay be used as an indicator of an amount of usage of data retaining device12a. In addition, a comparison of the potentials of capacitors20aand20bmay be a basis for determining a relative amount of usage of data retaining device12acompared to data retaining device12b. For example, a lower potential of capacitor20athan that of capacitor20bmay indicate that data retaining device12ahas been less used than data retaining device12b, and may be a candidate for a refresh to make room for new data items. In the following description, a voltage of a capacitor20will be used as an example of a potential of the same, for illustrative purposes. Please note, as a certain use of data retaining device12acauses a fixed amount of charges to be injected onto capacitor20a, the voltage of capacitor20ais mainly determined by the amount of usage of data retaining device12aand the initial voltage of the same. That is, in a given period, the exact time when a use of data retaining device12aoccurs does not make significant difference. As such, the current disclosure may be used with, inter alia, a Least Frequently Used algorithm for replacing cache.

According to one embodiment, a data retaining devices12, e.g.,12a, may be prioritized so that for the same amount of usages of data retaining devices12a,12b, capacitors20a,20b, respectively, may end with different voltage values. Various methods may used to achieve a priority. For example, the amount of charge injected onto a capacitor20may be controlled to reflect a priority of a data retaining device12. For example, the sizes of weighted charge sources22coupled to each data retaining device12may be tuned/weighed to achieve injection of different charges onto different capacitors20for the same usage of data retaining devices12. In addition, a decay rate of a capacitor20may be tuned/processed to reflect the priority of the related data retaining device12. For example, if data retaining device12ahas a priority over data retaining device12b, capacitor20amay be tuned to decay more slowly than capacitor20b.

As is appreciated, a capacitor20may be charged to an upper level such that the voltage of the capacitor20is no longer sensitive to further charging. In addition, a voltage of a capacitor20may decay to a lower level such that the voltage is no longer sensitive to further decay. As such, actions need to be taken to make sure that the voltage of a capacitor20has not reach the upper level or the lower level so that the voltage is valid to indicate a relative amount of usage of the related data retaining device12. That is, a comparison in comparator26needs to yield a valid result. According to one embodiment, voltage of a capacitor20(here20a,20b) may be input into a comparator28(28a,28b, respectively) to be compared with a signal30(30a,30b, respectively). A signal30may be controlled to represent a minimum voltage for a capacitor20to maintain sensitivity to further decay or a maximum voltage for the capacitor20to maintain sensitivity to further charging.

In addition, a voltage level of a capacitor20may indicate the validity of data in data retaining device12. For example, if the voltage of a capacitor20has decayed for a long time, the data stored in a data retaining device12may have also decayed to be invalid. As such, signal30may also be controlled to represent a minimum voltage level of a capacitor20to make sure that data stored in a data retaining device12is still valid.

A computer system200may be responsive to system10. For example, computer system200may control measuring device27in performing measurements, and may receive the measurement results as data inputs. Upon processing these data inputs, computer system200may control an action on a data retaining device12of data retaining sub-system11.

FIG. 2shows one embodiment of a hardware implementation100of the disclosure regarding one data retaining device, e.g.,12a(FIG. 1). As shown inFIG. 2, capacitor20ais coupled to multiple weighted charge sources110(110a,110b,110c) through transistor stacks120(120a,120b,120c, respectively). Please note, weighted charge sources110are collectively referred to as weighted charge source22ainFIG. 1. Each transistor stack120includes a transistor122(122a,112b,122c, respectively) and a transistor124(124a,124b,124c, respectively). A control signal130is coupled to the gates of transistors122through a one-shot-generator132including buffers134,136and a latch138. Outputs150(150a,150b,150c) of an address comparator140are coupled to the gates of transistors124(124a,124b,124c, respectively).

In operation, control signal130and outputs150(150a,150b,150c) of address comparator140are used together to achieve the correspondence between switches16and18(FIG. 1). Control signal130may be activated upon each selection of a data retaining device12, e.g.,12a, of data retaining sub-system11, e.g., a multi-port cache (FIG. 1). Control signal130may then be processed by one-shot-generator132to generate a signal to control the gates of transistors122(122a,122b,122c). As such, transistors122may be turned on by control signal130when data retaining device12ais selected for a use (whatever type). Each output150represents a specific type of use of data retaining device12a(FIG. 1). For example, output150amay represent a “WRITE” action; output150bmay represent a “READ” action; and output150cmay represent an “ACCESS” action. As such, a transistor124may be turned on by an output150that indicates a specific type of use of data retaining device12a. For example, in the case that data retaining device12ais selected to be used for a “WRITE”, signal130turns on all transistors122because data retaining device12ais selected for a use, and output150aturns on transistor124aas the type of use is a “WRITE”, which triggers/enables a charging of capacitor20aby weighted charge source110a. Similarly, a “READ” action of data retaining device12awill charge capacitor20aby weighted charge source110b; and an “ACCESS” action will charge capacitor20aby weighted charge source110c.

According to one embodiment, a use of data retaining device12amay be assigned with a priority over other types of uses of the same. For example, the amount of charges injected onto capacitors20athrough weighted charge source110a, which is related to “WRITE”, may be adjusted/controlled according to a certain policy, e.g., improving performance of data retaining sub-system11. The three actions mentioned above, i.e., “WRITE”, “READ”, and “ACCESS”, each may require different cost of resources for reloading and have a different impact on the performance of data retaining sub-system11(FIG. 1). Charges injected onto capacitor20afor each of the three types of uses may be controlled to reflect the differences in the cost of resources. For instance, when a “WRITE” is performed to data retaining device12a(FIG. 1) that is not already located in data retaining sub-system11, e.g., a multi-port cache, it may be controlled such that a larger amount of charges are injected into capacitor20ato reflect the performance loss of refetching that data from a memory, if the data is flushed and later refetched from the memory. The larger amount of charges make capacitor20aage/decay more slowly than, for example, data that has been recently fetched from the memory, since the latter is not “dirty” and does not need to be flushed back to memory. In this manner, a higher temporal weighting may be assigned to a “dirty” cache line/port, here12a(FIG. 1). In addition, it may also be controlled that the amount of charges injected onto capacitor20afor each different type of action, e.g., “WRITE”, “READ” and “ACCESS”, is different. For example, a higher temporal weighting may be assigned to a “READ” action over “WRITE” or “ACCESS” actions.

Various methods may be used to adjust/control the charges injected onto capacitor20a, and all are included in the current disclosure. For example, the size of weighted charge sources110may be tuned to differentiate the charges injected onto capacitor20aby each of them. For another embodiment, sizes of transistor stacks120may also be tuned to channel different amount of charges to capacitor20afor different uses. It should be appreciated that the various methods of controlling/adjusting charges injected onto capacitor20amay be used alone or in various combinations, which are all included in the current disclosure.

As has been described above, the operation of system10(FIG. 1), including the hardware implementation100(FIG. 2), may be controlled by computer system200. Details of computer system200will be described below.

2. Computer System

FIG. 3shows a block diagram of an illustrative computer system200according to one embodiment of the disclosure. In one embodiment, computer system200includes a memory220, a processing unit (PU)222, input/output devices (I/O)224and a bus226. A database228may also be provided for storage of data relative to processing tasks. Memory220includes a program product230that, when executed by PU222, comprises various functional capabilities described in further detail below. Memory220(and database228) may comprise any known type of data storage system and/or transmission media, including magnetic media, optical media, random access memory (RAM), read only memory (ROM), a data object, etc. Moreover, memory220(and database228) may reside at a single physical location comprising one or more types of data storage, or be distributed across a plurality of physical systems. PU222may likewise comprise a single processing unit, or a plurality of processing units distributed across one or more locations. I/O224may comprise any known type of input/output device including a network system, modem, keyboard, mouse, scanner, voice recognition system, CRT, printer, disc drives, etc. Additional components, such as cache memory, communication systems, system software, etc., may also be incorporated into computer system200.

As shown inFIG. 3, program product230may include a data retaining device (DRD) usage determining system232that includes a data collector240; a priority controller242including an activity priority controller244and a data retaining device (DRD) priority controller246; a measurement controller247; an implementer248including a comparison validity monitor250and a data validity monitor252; and other system components254. Other system components254may include any now known or later developed parts of a computer system200not individually delineated herein, but understood by those skilled in the art.

Inputs to computer system200include measurement result inputs260and user instruction inputs262. Measurement result inputs260include measurement results of measuring device27(FIG. 1) regarding, e.g., a voltage of a capacitor20and/or a comparison result of comparator26(FIG. 1). User instruction inputs262include instructions of a user of computer system200regarding the operation of, inter alia, DRD usage determining system232. For example, a user may instruct priority controller242with respect to a priority of a data retaining device12and a priority of a specific type of use (“WRITE”, “READ”, or “ACCESS”) of the data retaining device12. These inputs may be obtained by data collector240, and may be saved in database228. Outputs of computer system200include instruction outputs264that are communicated to, inter alia, data retaining sub-system11to perform an action on a data retaining device12, e.g., to refresh a data retaining device12(FIG. 1).

FIG. 4shows a flow diagram of an operation of data retaining device usage determining system232according to one embodiment of the disclosure. Referring toFIGS. 1-4, in process S1, priority controller242determines a priority of a use of a data retaining device12. Specifically, data retaining device (DRD) priority controller246determines a priority of a data retaining device, e.g.,12a, over other data retaining device, e.g.,12b. Activity priority controller244determines a priority of a type of use of data retaining device12a, e.g., a “WRITE”, over other types of use, e.g., “READ” or “ACCESS”. Various standards or policies may be used in determining priorities of a data retaining device12or a type of use of the data retaining device12, and are all included in the current disclosure. For example, improving performance of data retaining sub-system11may be a policy in determining a priority. As described above, various methods may be used to implement a priority determined by priority controller242, and are all included in the current disclosure.

Next in process S2, measurement controller247controls a measurement of a voltage of a capacitor20. Any means to measure a voltage of a capacitor20may be used with the disclosure and controlled by measurement controller247. The results of the measurements may be communicated to computer system200through measurement result inputs260and may be obtained by data collector240. In addition, results of the comparisons made in comparator26may also be communicated to computer system200and obtained by data collector240.

Next in process S3, implementer248determines a relative amount of usage of a data retaining device12based on the measured voltage of the related/coupled capacitor20, and determines an action upon the data retaining device12based on the usage determination, which may be implemented by data retaining sub-system11. As described above, a lower voltage of a capacitor20, e.g.,20a, indicates that the related data retaining device12ahas been used less then other data retaining devices, e.g.,12b. (FIG. 1). On the other hand, a higher voltage of capacitor20aindicates that data retaining device12ahas been used more then data retaining devices12b. Based on the determined relative amount of usage of data retaining device12a, an action upon data retaining device12amay be determined by implementer248. For example, in the case that data retaining sub-system11needs to refresh some of the data retaining devices12, implementer248may determine that a data retaining device12with a lower relative amount of usage be chosen to be refreshed.

According to an alternative embodiment, implementer248may compare a measured voltage of a capacitor20, e.g.,20a, with a preset threshold, e.g., a minimum voltage value. If the measured voltage of capacitor20ameets the threshold, e.g., lower than the minimum voltage value, the related data retaining device12ais selected to be taken action upon, e.g., to be refreshed.

In addition, in process S3, comparison validity monitor250may optionally monitor whether a measured voltage of a capacitor20is valid to indicate a relative amount of usage of data retaining device12. Specifically, comparison validity monitor250may control a signal30to represent an upper level threshold and a lower level threshold to be compared with a voltage of a capacitor20, here e.g.,20a. If the voltage of capacitor20ais lower than the upper level threshold and is higher than the lower level threshold, the voltage is considered valid to indicate a relative amount of usage of data retaining device12a. If voltage of capacitor20ais higher than the upper level threshold, or lower than the lower level threshold, voltage of capacitor20ais considered invalid to indicate a relative amount of usage of data retaining device12a. In addition, in the case that a comparison in comparator26does not generate a valid result, e.g., voltages of two capacitors20are the same, comparison validity monitor150may determine selecting a data retaining device12to take action upon based on other tests, e.g., a policy.

Moreover, data validity monitor252may optionally perform a data validity check. Specifically, data validity monitor252may determine whether a data in a data retaining device12, e.g.,12a, is valid by comparing a voltage of the related capacitor20ato a threshold which represents the minimum voltage of capacitor20ato indicate that the data in data retaining device12ais valid. Specifically, data validity monitor252may control signal30a(FIG. 1) to represent a least positive up-level (LPUL) voltage and/or a most positive down-level (MPDL) voltage of comparator20ato be compared with the voltage of capacitor20ain comparator28a. If voltage of capacitor20ais lower than the LPUL voltage and/or the MPDL voltage, data in data retaining device12amay be considered invalid and needs to be removed without consideration of the relative amount of usage of data retaining device12a.

A complete integrated circuit including circuit10and/or100, which may be referred to herein as a design structure, is created in a graphical computer programming language, and coded as a set of instructions on machine readable removable or hard media (e.g., residing on a graphical design system (GDS) storage medium). That is, design structure(s) is embodied in a machine readable medium used in a design process. (The design structure(s) may interface with any part of a machine readable media). The design structure(s) may include a netlist, which describes circuit10and/or100, and may include test data files, characterization data, verification data, or design specifications. If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design structure by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities as a foundry, directly or indirectly. The stored design is then converted into the appropriate format (e.g., graphic design system11(GDSII)) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

FIG. 5depicts a block diagram of an example design flow1000, which may vary depending on the type of IC being designed. For example, a design flow1000for building an application specific IC (ASIC) will differ from a design flow1000for designing a standard component. A design structure1020is an input to a design process1010and may come from an IP provider, a core developer, or other design company. The design structure1020comprises a circuit, e.g., circuits10,100, in the form of schematics or HDL, a hardware-description language, (e.g., Verilog, VHDL, C, etc.). The design structure1020may be on one or more of machine readable medium, e.g., memory220as shown inFIG. 3. For example, the design structure1020may be a text file or a graphical representation of circuit10and/or100. The design process1010synthesizes (or translates) the circuits10,100into a netlist1080, where the netlist1080is, for example, a list of fat wires, transistors, logic gates, control circuits, I/O, models, etc., and describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one machine readable medium220.

The design process1010includes using a variety of inputs; for example, inputs from library elements1030which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications1040, characterization data1050, verification data1060, design rules1070, and test data files1085, which may include test patterns and other testing information. The design process1010further includes, for example, standard circuit design processes such as timing analysis, verification tools, design rule checkers, place and route tools, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process1010without deviating from the scope and spirit of the disclosure.

Ultimately, the design process1010translates the circuit10and/or100along with the rest of the integrated circuit design (if applicable), into a final design structure1090(e.g., information stored in a GDS storage medium). The final design structure1090may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, test data, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce circuit10and/or100. The final design structure1090may then proceed to a stage1095of design flow1000; where stage1095is, for example, where final design structure1090: proceeds to tape-out, is released to manufacturing, is sent to another design house or is sent back to the customer.

While shown and described herein as a method and system for determining a relative amount of usage of a data retaining device, it is understood that the disclosure further provides various alternative embodiments. For example, in one embodiment, the disclosure provides a program product stored on a computer-readable medium, which when executed, enables a computer infrastructure to determine a relative amount of usage of a data retaining device. To this extent, the computer-readable medium includes program code, such as data retaining device usage determining system232(FIG. 3), which implements the process described herein. It is understood that the term “computer-readable medium” comprises one or more of any type of physical embodiment of the program code. In particular, the computer-readable medium can comprise program code embodied on one or more portable storage articles of manufacture (e.g., a compact disc, a magnetic disk, a tape, etc.), on one or more data storage portions of a computing device, such as memory220(FIG. 3) and/or database228(FIG. 3), and/or as a data signal traveling over a network (e.g., during a wired/wireless electronic distribution of the program product).

In another embodiment, the disclosure provides a method of generating a system for determining a relative amount of usage of a data retaining device. In this case, a computer infrastructure, such as computer system200(FIG. 3), can be obtained (e.g., created, maintained, having made available to, etc.) and one or more systems for performing the process described herein can be obtained (e.g., created, purchased, used, modified, etc.) and deployed to the computer infrastructure. To this extent, the deployment of each system can comprise one or more of: (1) installing program code on a computing device, such as computing system200(FIG. 3), from a computer-readable medium; (2) adding one or more computing devices to the computer infrastructure; and (3) incorporating and/or modifying one or more existing systems of the computer infrastructure, to enable the computer infrastructure to perform the process processes of the disclosure.

In still another embodiment, the disclosure provides a business method that performs the process described herein on a subscription, advertising supported, and/or fee basis. That is, a service provider could offer to determine a relative amount of usage of a data retaining device as described herein. In this case, the service provider can manage (e.g., create, maintain, support, etc.) a computer infrastructure, such as computer system200(FIG. 3), that performs the process described herein for one or more customers and communicates the results of the determination of the relative amount of usage of a data retaining device to the one or more customers. In return, the service provider can receive payment from the customer(s) under a subscription and/or fee agreement and/or the service provider can receive payment from the sale of advertising to one or more third parties.