PLL system and device with a low noise charge pump

According to an aspect, a phase locked loop system comprises a charge pump (CP) comprising a set of switching transistors and a set of non-switching transistor, in that the set of switching transistors operative at a low break down voltage and a high switching speed compared to that of the set of non-switching transistors, and comparative a voltage comprising a configured to generate a UP pulse when a first plurality of metal strips forming a first part of a closed contour enclosing a first area, and a phase frequency detector (PFD) providing a UP pulse swinging between a VDDL and a VDDH, wherein the PFD is interfaced with the CP such that, the UP pulse drives a first switching transistor in the CP to couple the VDDH to an output terminal through a first non-switching transistor that is biased for charge pump.

CROSS REFERENCES TO RELATED APPLICATIONS

This application claims priority from Indian patent application No.: 202041029768 filed on Jul. 13, 2020 which is incorporated herein in its entirety by reference.

BACKGROUND

Technical Field

Embodiments of the present disclosure relate generally to electronic systems more specifically to a phased locked loop (PLL) system and device with a low noise charge pump.

Related Art

PLL is referred to a system operative to match phase and/or frequency of a reference signal (a first signal) and a feedback signal (a second signal) as is well known in the art. The PLL is employed for in a communication system, radar system, object detection system, and other electronic systems for clock detection, reference clock/frequency generation, frequency conversion, modulation and demodulation of a signal, for example.

The PLL system generally employ a phase frequency detector (PFD), a charge pump (CP) and a loop filter (LP) and a voltage controlled oscillator (VCO) to match the frequency/phase (hereafter used interchangeably). In principal, the frequency of the VCO is altered to achieve the match/lock (as in the phase locked look).

In operation, the PFD detects a phase difference between the reference signal and the feedback signal to generate one of an UP, DOWN and a RESET signal (hereafter referred to as PFD output) representing the phase difference. The PFD output signal is provided to the CP for altering the voltage to the VCO. Often, the switching time of PFD and the voltage range of CP are compromised against one another, thus rendering the PLL operation less efficient at least for deployment in radar systems operative to perform object detection and mapping.

SUMMARY

According to an aspect of the present disclosure a phase locked loop system comprises a phase frequency detector (PFD) providing a shifted UP pulse swinging between a first low voltage and a first high voltage, and a charge pump (CP) comprising a set of switching transistors and a set of constant gate bias transistors, in that the set of switching transistors are rated with a first breakdown voltage and a first switching speed, and the set of constant gate bias transistors are rated at a second breakdown voltage and a second switching speed, in that, the first breakdown voltage is substantially half the second breakdown voltage and the first switching speed is greater than the second switching speed, wherein the PFD is coupled to the CP such that, the shifted UP pulse drives a first switching transistors in the set of switching transistors to provide a high voltage capable signal at an output terminal through a first constant bias transistor, in the set of constant gate bias transistors, that is biased for charge pump.

According to another aspect, in the phase locked loop system, the PFD comprising a level shifter shifting an UP pulse to provide the shifted UP pulse, in that the UP pulse swings between a second low voltage to second high voltage wherein the first low voltage is substantially equal to the second high voltage, the first high voltage is substantially equal to twice the second high voltage and second low voltage is substantially zero.

According to yet another aspect, the phase locked loop system further comprising a second switching transistor in the set of switching transistors, coupled to the first switching transistor such that the second switching transistor couples a first bias voltage to one of a drain and a source terminal while the other terminal is coupled to a voltage higher than the first breakdown voltage to maintaining corresponding drain to source voltage of the first switching transistor within the first breakdown voltage when the first switching transistor is in OFF state.

In yet another aspect, in the phase locked loop system the first switching transistor and the second switching transistors are respectively driven by the shifted UP pulse and its compliment such that the second switching transistor is turned OFF when the first switching transistor is ON and vice-e-versa.

Several aspects are described below, with reference to diagrams. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the present disclosure. One who skilled in the relevant art, however, will readily recognize that the present disclosure may be practiced without one or more of the specific details, or with other methods, etc. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the features of the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EXAMPLES

FIG. 1is an example block diagram of a radar receiver system in which various aspect of the present disclosure may be seen. As shown the example radar receiver system101may comprise, RF (Radio Frequency) signal source110, RF signal conditioner block120, Mixer130, Local oscillator140, an IF signal conditioner150, Demodulator160, Information processor170and I/O device180. Each element of the radar receiver system is described in further detail below.

The RF signal source110represents the Radar signal received from the object (for example reflected signal) on one or more receiving antenna operating independently or in the MIMO configuration. The radar signal may comprise the signal separated in time and/or in frequency centered at a high frequency (carrier frequency) as is well known in the art. RF signal source110may comprise any other Radar signal adapted for different applications such as object detection, geo mapping, etc. The RF signal source110may also comprise any other signal transmitted by a communication system over a communication channel. The signal from the RF signal source110may be provided to RF signal conditioner120.

The RF signal conditioner120conditions the RF signal for processing. The RF signal conditioner120may comprise at least one of a: low noise RF amplifier which provides initial gain and selectivity, RF frequency filter that may eliminate the noise, load balancing circuits etc. RF amplifiers may be implemented using a Bipolar and field effect transistors, or Integrated circuits (IC's), or similar kind. This block outputs desired frequency bands and these conditioned signal is provided to the mixer130.

The mixer130receives the conditioned signal from the RF signal conditioner120and performs mixing operation with the reference signals. In one embodiment the mixer may be employed as part of the range detection, object detection etc. The Mixer130may provide output that may be the sum and/or difference frequencies of input signal and reference local oscillator signal. The mixer converts RF signal into IF (Intermediate Frequency) signal.

The local oscillator140provides a reference signal/frequency to the mixer130for mixing operation. In one embodiment the local oscillator excites a frequency for mixing with the incoming RF signal to get the intermediate frequency. The local oscillator140may provide one or more reference signal for mixing operation. The frequency of the reference signal (reference frequency) may comprise signal of Megahertz and/or Gigahertz.

The IF signal conditioner150receives an IF signal from mixer130for processing. IF signal conditioner150may perform amplification, filtering and other signal conditioning operations. The filter operation may comprise eliminating frequency other than the ones that are centered at one or more IF frequencies.

The demodulator (or detector)160extracts information from the IF signal received from the IF signal conditioner. For example, operations of the demodulator may comprise extraction of range information, azimuth and/or elevation angle of the object etc. The demodulator may also perform extraction of audio and/or video information from the IF signals. The demodulator160may be implemented in any known ways for extraction of the respective information.

The Information processor170receives the information from the demodulator and performs the one or more action on the information. For example, the range, azimuth and elevation angels received from the demodulator160are employed to construct 3d/2d object shape and position, terrain mapping etc. In an alternative embodiment, the information processor may perform image processing and audio processing to generate the video and audio for playing and storing, for example.

The I/O device180operates to provide interface such as display, speaker, navigation controller, and transceiver. Accordingly, the information processed by the information processor170is provided to the I/O device for control and display as may be the case. For example, the position, shape and range information may be provided to navigation control unit (not shown) to avoid collision in an unmanned vehicle navigation system.

In the radar receiver system101, local oscillator140and demodulator160, for example, employ PLL system for generating stable local reference frequency signals, as frequency synthesizer to detect objects from the received radar signals. In particular, the radar receiver may employ a fractional and/or integer PLL for synthesizing a desired frequency. In case of a fractional PLL, a sigma delta modulator (SDM) is employed to provide an average division of frequency that is a fraction as is well known in the art. In one embodiment, the receiver system101operate at 60 Ghz range and/or millimeter wave signals for detecting objects and shape for navigation.

The performance of the conventional PLL system may affect the performance of the receiver system101at least in terms of accuracy in determining the range, Azimuth, elevation angle. Further, the performance of the conventional PLL system may perturb the reference frequency(ies) of the local oscillator140, frequency synthesizers in the demodulator160, for example, thereby affecting the range, azimuth and elevation.

Accordingly, in one embodiment, the radar receiver system101employs the PLL system and device with a low noise charge pump that at least overcome some of the disadvantages noted with the conventional PLL system, thereby providing enhanced efficiency/accuracy in the radar system101. The manner in which the PLL system may be implemented to provide the enhanced signal to noise ratio with a fast switching time in the radar receiver system101is further described below.

FIG. 2is an example PLL system in an embodiment. The PLL system200is shown comprising a Phase frequency detector (PFD)210, a charge pump (CP)220, a loop filter (LP)230, a voltage controlled oscillator (VCO)240and divider250. Each element of the PLL system200is further described below.

The phase frequency detector (PFD)210generates error signal representing the phase and/or frequency difference between the signal on path201(reference signal, for example) and the signal on path251(feedback signal, for example). The signal on the path251may be same as VCO240output or divided by a fraction or integer from the divider (250) that divides (by integer or fraction) the signal generated by VCO240by its frequency. In case of fraction divider, a sigma delta modulator (SDM, not shown) drives the divider to achieve the division by a fraction. The VCO240, divider, and the SDM may be implemented in any known way.

In one embodiment, the PFD210generates an UP pulse (212A) when the rising edge of the reference signal on path201arrives. The PFD210generates a DOWN pulse (212B) when the rising edge of the signal on path251arrives. The PFD210resets the UP and the DOWN pulse on reception of the rising edge of the other signal201and251respectively (in other words, when rising edge of both201and251are received).

The charge pump (CP)220sources and sinks a constant current to and from the loop filter230corresponding (for the duration of) to the UP and Down pulse respectively. The sourcing current increases and sinking current reduces a voltage at the input (223) of the loop filter230. The loop filter removes the undesired frequency components from the varying voltage (signal) on path223and the filtered voltage signal is provided to VCO240on path234. In an embodiment the loop filter230is implemented as a low pass filter. The voltage controlled oscillator (VCO)240provides a signal on path (299,245). The PLL200operate such that, the frequency/phase of the signal on path234/299is in lock with Reference signal (201).

It may be appreciated that, it is desirous that the voltage provided to loop filter accurately represent the phase mismatch detected by the PFD. However, in a conventional implementation, number of factors/elements contributes error (or noise) to the signal presented to loop filter. As is well known, in a conventional PLL implementation, there will be a delay between the arrival of rising edge of both signals (201,241) and the generation of reset. This is due to the finite speed of logic gates used to generate the reset signal. During this finite reset delay duration the equivalent signal of the CP is zero since both up and down pulse are active. As is known, the intrinsic noise of the signal or charge sources used to implement the CP will inject noise at the output when the UP or Down signals are active. During this reset duration the output of CP will have noise from both UP and Down components while the signal content is zero, resulting in a zero signal to noise ratio (SNR) phase of operation. It is necessary to reduce the duration of this zero SNR phase by reducing the reset delay for improving PLL noise performance.

For a given noise content at the node223, signal to noise ratio can be improved by allowing higher signal swing, as is well known in the art. This is achieved by employing higher supply voltage for the charge pump and correspondingly implementing the charge pump with thick gate oxide transistors (high voltage rating). Such implementation of CP require the PFD to be implemented with a similar rating transistors resulting in increased reset pulse width (as the higher voltage rating transistors exhibit higher switching time and correspondingly increased gate delay). As an alternative, another conventional technique employs a level shifter that is inserted between PFD with low voltage transistors and CP with high voltage transistors. However, in such implementation the level shifter between PFD and CP introduces noise as it require both set and reset phase to be fast switching.

In one embodiment, the PFD210and CP220together operate to provide high signal to noise ratio on path223, in that, the CP220employ high voltage source to provide high signal swing and the PFD operate with low voltage device to attain the high switching speed. Thus, in combination, both higher signal swing and reduction in the reset pulse width (or dead zone) are attained. The manner in which the PFD210and CP220are implemented in an embodiment is further described below.

FIG. 3is a circuit diagram illustrating an example PFD210in an embodiment. The PFD301is shown comprising D flip-flops310A and310B, AND gate320, inverters331-334, transistors341and342, capacitors351and352. The operation and connections are explained in further detail below.

The D flip-flops310A and310B together with the AND gate320, operate to compare the phase of the signal received on terminal REF and FB. In that, the D flip-flop310A generates a UP pulse on path328when the rising edge of a signal provided on the terminal REF is received. Similarly, the D flip-flop310B generates a DOWN pulse on path329when the rising edge of another signal provided on the terminal FB is received. The UP or DOWN pulse on path328and329is reset through the AND gate220when both the rising edges are received on the REF and FB terminal. The invertors333, and334operate to provide delayed DOWN and DOWN_BAR (Inverted DOWN pulse) on terminal399and path337respectively. Similarly, the invertors331, and332operate to provide delayed UP and UP_BAR (Inverted UP pulse) on path339and338respectively.

In the circuit301the VDDL represents the low supply voltage (at the drain terminal) and VSS representing the voltage at the source terminal. Accordingly, the D flip-flops310A&B, inverters331-334, and AND gate320operate at low voltage (VDDL) and employ fast switching devices/transistors (as is well known, the constructional benefits due to low voltage enable fast switching). Transistors341&342and capacitors351and352operate to shift the UP and UP_BAR signal at339and338to higher voltage level. For example, the signal UP on path339swings between zero and VDDL and the UP_BAR on path338swing correspondingly between VDDL and zero.

The transistors341&342and capacitors351and352configured as shown provides a shifted UP signal on terminal390that swing between VDDL and VDDH, and provides the shifted UP_BAR on terminal395that swing between VDDH and VDDL. Therefore, in one embodiment the PFD301provide UP signal on terminal390swinging between VDDL and VDDH, and a DOWN signal on terminal399that swing between Zero and VDDL. In one embodiment, the signal on path337and on terminal390,395and399are provided to the CP220.

It may be seen that, the voltage level at the drain terminals of the transistors341and342are maintained at either at VDDL (when transistors are off) or at VDDH (when transistors are on). Thus, the transistors drain to source voltage does not exceed VDDL (typically when VDDH is twice the VDDL). Thus, transistors341and342are low breakdown voltage transistors with higher switching speed. In other words, though VDDH is employed, the transistors do not experience the high drain to source voltage thus not requiring employing transistors with higher breakdown voltage compromising the switching speed.

Accordingly, the PFD301employs low voltage rating transistors for generating UP and DOWN signal to drive the CP220. As a result, the PFD301enables reduction of reset delay by not having to compromise on the maximum attainable switching speed for the lowest operable voltage range. The manner in which the CP220may be implemented such that, the higher voltage swing attained without compromising on the switching speed is further described below.

FIG. 4is a block diagram illustrating a charge pump in an embodiment. The CP401is shown comprising elements current source410, resistors441and442, capacitors451and452, the constant gate bias transistors421,422,431-434,481and482, and the switching gate voltage transistors (also referred to as switching transistors)461,462,471and472. The elements are interconnected as shown in theFIG. 4. The CP401is described in further detail below.

In one embodiment, constant gate bias transistors421,432,433,481and482are of high breakdown voltage transistors (for example, VDDH) and participate in providing desired high voltage charge pump at the output terminal499(corresponding to terminal223inFIG. 2). The switching transistors461,462,471and472are of low breakdown voltage transistors having an ability to operate at high switching speed. The constant gate bias transistors422(and434) and431are of type low voltage, used to replicate the state of472and471in ON state.

In one embodiment, the PFD301and the CP401are configured to operate in conjunction. Accordingly, the terminal390(shifted UP signal) is coupled to the terminal475, the terminal395(shifted UP_BAR) is coupled to terminal465, the terminal399(DOWN) is coupled to the terminal476and the path337(DOWN_BAR) is coupled to terminal466. Thus, when the transistor471is ON, the transistor461is OFF and vice-e-versa. Similarly, when the transistor472is ON, the transistor462is OFF and vice-e-versa. Thus, the PFD301drives the low breakdown voltage and high speed transistors of the CP401.

In operation, the current source410together with the non-switching transistors421,422, and431-434configured as shown, mirror the current410on to the arm430with the current ratio in relation to the size ratio of the transistors. The non-switching transistors432, together with resistor441and capacitor452configured as shown, provide a gate bias (say Vgp) to the constant gate bias transistor481, designed to be within VDDL volts of VDDH. Similarly, the constant gate bias transistors421, together with resistor442and capacitor451configured as shown, provide a gate bias (say Vgn) to the constant gate bias transistor482designed to be less than VDDL.

When the switching transistor461is turned on, a voltage close to Vgp is maintained at the terminal487A. Accordingly, the transistor471experiences a maximum drain to source voltage less than VDDL (i.e. VDDH-Vgp) when transistor471is off. When the shifted UP signal on the terminal390drives the transistor471to ON state and couples VDDH to the terminal487A resulting in a current signal to be produced from481to499that is equal in magnitude to the current in432multiplied by the ratio of the size of481to432. Similarly, when the switching transistor462is turned on, a voltage Vgn is maintained at the terminal487B. Accordingly, the transistor472experiences a maximum source to drain voltage less than VDDL when transistor472is off. Thus, DOWN signal on the terminal399drives the transistor472to ON state and couples VSS to the terminal487B resulting in a current signal to be produced from482to499that is equal in magnitude to the current in433multiplied by the ratio of the size of 482 to 433.

Operating in Conjunction, when PFD301provides an UP Pulse on path328and correspondingly shifted UP on terminal390and shifted UP_BAR on terminal395, the signal drives the transistor471to ON state, transistor461to OFF state and enables a signal current from high voltage capable481to the output terminal499. The charge pump401sources the current to the loop filter via transistor471and481and through terminal499. The transistor481configured with the larger metal oxide channel width with the capacity to handle higher voltage swing at499improves the signal to noise ratio on the terminal499.

Similarly, when PFD301provides a DOWN Pulse on path399and correspondingly DOWN_BAR terminal339, the signal drives the transistor472to ON state, transistor462to OFF state and enables a signal current from high voltage capable482to the output terminal499. The charge pump401sinks the current from the loop filter via transistor472and482and through terminal499. The transistor482configured with the larger metal oxide channel width with the capacity to handle higher voltage swing at499improves the signal to noise ratio on the terminal499.

When the PFD resets the UP/DOWN pulse, the corresponding transistors pairs (471,461) and (472,462) are mutually turned OFF and ON. For example, when the transistor471is turned OFF by reset of UP Pulse, the transistor461is turned ON maintaining a voltage less than VDDL across the drain-source nodes of471.

Accordingly, it may appreciated that, all switching transistors in the PFD301& CP401and the interface thereto are implemented with low voltage high speed transistors to reduce the Reset delay and charge pump bias transistors are implemented with high voltage transistors. Both high switching speed and high voltage swings are attained in the PFD and CP disclosed in the above paragraph. Accordingly, signal to noise ratio of the radar receiver101is enhanced. In one embodiment, in the PFD301, and CP401, the VDDL is set to 0.9 Volts, VDDH is set to 1.8 volts and VSS is set to ground potential (zero volts). The resistors are set to 1K Ohms and capacitors are set to 10's of Pico Farads in the CP401and 10's of Pico Farads in the PFD301.

FIG. 5illustrates an example signal levels at different terminal of PFD301and CP401. In that, the curve501representing example signal on terminal REF, the curve502representing example signal on FB terminal, curve503representing signal on path328and curve504representing signal on path329, curve505representing signal on path390and curve506representing signal on path399.

In one embodiment, the PLL200is configured to operate with varying bandwidth (loop bandwidth, as is well known) and the corresponding phase offset. For example, the radar receiver101may operate as continuous wave frequency modulated (CWFM) radar. In that, a varying frequency radar signal (Chirp, as is well known in the art) is transmitted and received, the chirp is characterized by the frequency change and the time window during which the change happens, together classified as modulation rate. Accordingly, the PLL200is required to be operated with varying loop bandwidth corresponding to the varying frequency modulation rate. Accordingly in one embodiment, the loop bandwidth of the PLL is varied in conjunction with the chirp signal modulation rate. In one embodiment, the required loop bandwidth (proportional to the inverse of the time taken by the PLL to respond to a change) is increased by driving multiple charge pumps for fast response time.

FIG. 6is a block diagram illustrating multiple charge pumps coupled to the PFD for varying loop bandwidth in one embodiment. The block diagram is shown comprising PFD610, charge pumps620A through620N, and a phase offset compensator (POC)630. Each element is further described below.

The PFD610provide UP and Down pulse representing phase/frequency error between a reference signal and feedback signal. In one embodiment, the PFD610operates similar to and/or employing one or more features described with reference the PFD210&301and descriptions ofFIG. 5.

The charge pumps620A through620N provide charging and discharging current on path699(to the loop filter230). In one embodiment, the PFD610may adaptively drive a selected numbers of charge pumps within620A through620N based on the loop bandwidth required. In one embodiment, the charge pump620A through620N may be implemented as the arm470of charge pump401. For example, the arm470may be repeated N number of times respectively coupling its gate parts to the UP, and DOWN pulses as illustrated in theFIG. 4.

In an alternative embodiment, each charge pump620A through620N may be implemented as/similar to charge pump401. In that, the output terminal499of all the charge pumps may be coupled together to form the output terminal699. As a result, when the loop bandwidth required is high, more numbers of charge pumps are operated by the PFD610. Accordingly, in case of FMCW radar, number of charge pumps may be dynamically increased or decreased to meet the loop bandwidth requirement. In another embodiment, a bandwidth switching signal may dynamically couple first set of charge pumps and second set of charge pumps to the PFD based on the FMCW signal.

The POC630provides an offset current on path699to provide phase offset correction to overcome the phase error due to bandwidth change. Further, the POC630may be operated with the bandwidth switching signal to turn ON and OFF the offset current (Ioffset). The signal on path699is provided to the LPF230for filtering.

FIG. 7is an example FMCW signal710and the bandwidth switching signal720in an embodiment. As shown there, the FMCW signal710is shown comprising fast downwards frequency sweep T1and chirp sweep T2+T3. In that, the fast downwards frequency sweep T1may require PLL to operate with the high loop bandwidth compared to the chirp sweep T2+T3. While T2is set aside for settling time, the T3is effective chirp time. Accordingly, the logic high (T1and T2) operate the PFD610and charge pumps620A-N in the high band width mode and the logic low (T3) operates the PFD610and charge pumps620A-N in the low bandwidth mode.

Similarly, the logic high of720operates the POC630to generate Ioffsetcurrent and logic low of720turns off the POC630. In one embodiment, at low bandwidth the charge pump current is provided is Icpand at high bandwidth the charge pump current provided is equal to (N*Icp) where N is an integer greater than one. The Ioffsetis set to a value equal to: ((Td−Td/N)/Trefclk)*N*Icp. In that, Tdrepresents the delay between the reference signal and the feedback signal in low bandwidth mode and Trefclkrepresenting time period of the reference clock.

FIG. 8illustrates the manner in which the POC630may be implemented in conjunction with the charge pump401. As shown there the elements of the charge pump401are retained with reference numerals. The POC part is shown comprising transistors810and820. The transistor810is biased to provide Ioffsetwhen the transistor820is turned on. In one embodiment, the transistor810is of high voltage rating similar to the transistor482. The transistor820is a low voltage and high speed transistor similar to transistor472. In one embodiment, the transistor820is driven by the switching signal720. That is terminal821is provided with signal720so that, the POC part is turned on and the offset current is provided on path899. The gate terminal811may be coupled to the terminal marked A for biasing the transistor810.

While various examples of the present disclosure have been described above, it should be understood that they have been presented by way of example, and not limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the above described examples, but should be defined in accordance with the following claims and their equivalents.