Parallel/series error correction circuit

In a data processing system, the subject error correcting circuit is connected in the bridging mode to the data bus which interconnects a processor and a memory for error detection. It is presumed that the memory words obtained from the memory are relatively error-free, and the subject circuit does not delay their transmission, but simply monitors the data. If an error in the data is detected, an error signal is generated on the next processor microcycle, the processor aborts its present operation and then fetches the corrected data from the error correction circuit. If the frequency of errors increases or if a permanent error is detected, the subject error correction circuit switches to an in-line mode where it functions much as prior art error correction circuits: delaying the transmission of each memory word until the error check is complete.

FIELD OF THE INVENTION 
This invention relates to a system for connecting error correction 
circuitry on the data bus between a memory and a processor and, in 
particular, for connecting the error correction circuitry in either a 
parallel (bridged) or series mode as appropriate. Unlike prior art error 
correction circuitry, in which the error correction circuit (ECC) is 
connected only in a series mode between a memory and a processor, the 
subject invention connects a conventional error correction circuit in 
parallel mode onto the data bus between a memory and a processor for error 
detection. A memory error signal from the error correction circuit casues 
the processor to branch to an error recovery routine that takes the 
corrected data from the error correction circuit. For soft errors, this 
would be a single event, while for permanent errors the processor causes 
an automatic switch-over to the series correcting mode. 
DESCRIPTION OF THE PRIOR ART 
With prior art read error correction circuitry, each time that data are 
read from memory, those data are passed through an error correction 
circuit that is connected in series between the memory and the processor. 
This error correction circuit verifies and corrects data before they are 
passed to the processor. This method of error checking and correcting adds 
a propagation delay to the time required to execute a memory read. 
Assuming a memory read operation requires a microcycle time of 320 ns. 
without error checking, the error checking operation of the error 
correction circuit adds a typical propagation delay of about 18% to each 
memory read operation. The problem with this arrangement is that every 
memory read operation suffers this propagation delay penalty even though 
the actual need for error correction may be infrequent. 
SUMMARY OF THE INVENTION 
The parallel/series error correction circuitry of this invention eliminates 
this propagation delay penalty from all error free data read from memory, 
while providing for full series error correction when a permanent error is 
detected. This is accomplished by the switching capability of the subject 
error correction circuit. When a memory read operation is executed, a 
memory word is placed on the processor input bus as if error free, while 
at the same time being checked for errors by the error correction circuit 
which is connected to the bus in the bridged mode. If the data contained 
in this memory word are error free, then no error correction is required 
and the propagation delay associated with prior art series error 
correction circuit will have been eliminated. 
When an error in the data is detected by the error correction circuit, the 
error correction circuit generates a Memory Error (MER) signal to indicate 
an error in the data and sends the MER signal to the processor during the 
following microcycle. Since the processor has accepted the data which 
contains an error, the processing of this data could cause destruction of 
existing valid processor data. Therefore, the MER signal is used to 
prevent the clock from strobing the processor, the data registers, and the 
status registers, thereby aborting the processor operation. The processor 
is then forced to branch to an error recovery routine, where error 
correction and error status operations are performed. The error correction 
circuit corrects the data and latches the corrected data. The processor 
momentarily switches the error correction circuit into the series mode, 
reads the corrected data from the error correction circuit and then 
returns the error correction circuit to the bridged mode. If a permanent 
error is detected, the error correction circuit is maintained in the 
series mode where each data transmission is delayed.

DETAILED DESCRIPTION 
FIG. 1 illustrates the circuitry required to connect processor 101, error 
correction circuit 102, and memory 103 in the conventional prior art 
series error correction circuit configuration. Processor 101 addresses 
memory 103 to read data from the memory by passing the desired control 
signals and memory address from processor 101 to memory 103 on control bus 
CBUS and address bus ABUS, respectively. The requested memory word which 
includes error correcting code bits are read from memory 103 and passed to 
error correction circuit 102 via the Read Data Bus (RDB). Error correction 
circuit 102 is a conventional error checking device such as the Intel 
Corporation's 8206 error detection and correction unit. Error correction 
circuit 102 delays the transfer of data to processor 101 while it verifies 
the data and, if necessary, corrects data errors that are detected. If an 
error is detected, error correction circuit 102 not only corrects the data 
but also generates a Memory Error signal and applies this signal to lead 
MER, thereby providing processor 101 with this bit of information for 
error logging purposes. The verified or corrected data are then latched by 
error correction circuit 102 on to Input Data Bus (IDB) where they are 
read into processor 101. 
Processor 101 
Processor 101 is virtually insulated from the occurrence of faults in the 
data by error correction circuit 102. The only fault indication that 
processor 101 receives is a memory error signal on lead MER, which signal 
may be used by processor 101 for maintenance functions. It is helpful at 
this point to discuss the basic structure of processor 101. 
FIG. 2 illustrates the relevant microlevel architecture of conventional 
microprogrammable processor 101 which is shown in FIG. 1. Processor 101 is 
driven by coded instructions which, along with data, are typically stored 
in memory 103. These coded instructions contain opcodes that are code bits 
which designate a function or operation that processor 101 is to perform. 
These opcodes are routed by processor 101 to its instruction decoder 201 
via the Input Data Bus (IDB). Instruction decoder 201 translates the 
received instruction opcode into the address of the microprogram entry 
point, which microprogram performs the function or operation designated by 
the opcode. The entry point address is passed to sequencer 202 via the 
Sequencer Branch Input (SBI) bus. Sequencer 202 uses these entry point 
addresses to sequence through control memory 203 via the Control Memory 
Address (CMA) bus. The control memory 203 outputs microinstructions that 
are loaded and latched every cycle in the MicroInstruction Register (MIR) 
204 via the Control Memory Output (CMO) bus. These microinstructions 
control the function input of sequencer 202 via the Sequencer Function 
Control (SFC) bus, the function input of Arithmetic Logic Unit (ALU) 205 
via the ALU function control (ALUC) bus, and the test select input of 
condition multiplexer (CMUX) 206 via the Test Select (TS) bus as well as 
other control functions not critical to this discussion. These units 
respond to these function input signals by performing the operation 
indicated by the microinstructions stored in microinstruction register 
204. The test select signal is passed from condition multiplexer 206 to 
sequencer 202 via the Sequencer Test Select Input (STSI) signal lead, 
which signal forces sequencer 202 to perform conditional branches (when 
necessary) within the processor. 
These above-mentioned elements are all well-known in the art and are 
illustrated, in block diagram form, in FIG. 2 to simply assist in the 
understanding of the subject invention. It is evident that there are many 
control, timing and data leads that are not illustrated in FIG. 2 but 
which are present in processor 101. 
DESCRIPTION OF THE PREFERRED EMBODIMENT 
FIG. 3 shows the circuitry required to interconnect processor 301, memory 
303, and error correction circuit 302 in the subject invention. When 
operating in the parallel error correction mode, processor 301 addresses 
memory 303 via control and address busses, CBUS and ABUS, respectively. 
The requested memory word that includes error correcting code bits is read 
from memory 303 and passed to error correction circuit 302 over the Read 
Data Bus (RDB). The requested memory word without the error correcting 
code bits is also passed to the parallel read gate 304 via the Read Data 
Bus (RDB). Error correction circuit 302 checks the memory word for errors 
while at the same time the data are passed through parallel read gate 304 
to processor 301 via the Input Data Bus (IDB). 
If data error(s) are detected, error correction circuit 302 sends a memory 
error signal on lead MER to processor 301, corrects the data, and latches 
the corrected data. Processor 301, in response to the signal on lead MER, 
branches to the error recovery routine and momentarily activates the 
Series/Parallel Mode Control (SPMC) lead to enable the corrected data to 
be read from error correction circuit 302 over output bus EDB through 
series read gate 305 into processor 301 via the Input Data Bus (IDB). Once 
the corrected data is read into processor 301, control lead SPMC is 
deactivated and the circuit resumes monitoring the data in bridged 
fashion. 
When an error diagnostic routine in processor 301 diagnoses a permanent 
error condition, a Hard Error Alarm is activated. This alarm causes 
processor 301 to leave the Series/Parallel Mode Control (SPMC) signal lead 
active. The signal on lead SPMC disables parallel read gate 304 and 
enables the series read gate 305. The SPMC signal switches the error 
correction circuitry of this invention into a series error correction 
mode. All data read from memory 303 are now passed via the Read Data Bus 
(RDB) to error correction circuit 302 for correction. Error correction 
circuit 302 verifies, corrects and latches the data. The data are then 
read out of error correction circuit 302 by processor 301 via the Input 
Data Bus (IDB). The error correction circuitry of this embodiment remains 
in the series error correction mode until the cause of the permanent error 
has been repaired and the alarm has been reset. 
Processor 301 
Since the error correction circuit 302 of the subject invention is 
connectable in either the series or parallel (bridged) modes, processor 
301 must control the circuit configuration to maximize the system 
efficiency. To accomplish this control function, the basic processor 
architecture of FIG. 2 must be expanded to that illustrated in FIG. 4. 
FIG. 4 illustrates the relevant microlevel architecture of a 
microprogrammable processor 301 which is shown in FIG. 3. As with 
processor 101, processor 301 is driven by coded instructions which along 
with data are typically stored in memory 303. These coded instructions 
contain opcodes that are code bits which designate a function or operation 
which processor 301 is to perform. These opcodes are routed by processor 
303 to its instruction decoder 401 via the Input Data Bus (IDB). 
Instruction decoder 401 translates the received instruction opcode into 
the address of the microprogram entry point, which microprogram performs 
the function or operation designated by the opcode. The entry point 
address is passed to sequencer 402 via Sequencer Branch Input (SBI) bus. 
Sequencer 402 uses these entry point addresses to sequence through Control 
memory 403 via the control Memory Address (CMA) bus. The CMA bus is also 
connected to the Return from Recovery Routine Register (RRRR) 404. The 
output of control memory 403 are the microinstructions that are loaded and 
latched every cycle into microinstruction register (MIR) 405 via the 
Control Memory Output (CMO) bus. These microinstructions control the 
function input of function multiplexer (FMUX) 406 via the Function Control 
Input (FCI) bus, the function input of arithmetic logic unit (ALU) 407 via 
the ALU function control (ALUC) bus, and the test select input of 
condition multiplexer (CMUX) 408 via the Test Select (TS) bus. These units 
respond to these function input signals by performing the operation 
indicated by the microinstructions stored in microinstruction register 
405. The Function signal is passed from function multiplexer 406 to 
sequencer 402 via the Function Select (FS) bus. The Test Select signal is 
passed from condition multiplexer 408 to sequencer 402 via the Sequencer 
Test Select (STS) signal lead, which signal forces sequencer 402 to 
perform conditional branches (when necessary) within the processor. 
Recovery Routine Address Register (RRAR) 409 contains the address of the 
recovery microroutine address. Return from Recovery Routine Register 
(RRRR) 404 contains the address of the microinstruction that was aborted 
(the microinstruction addressed by control memory 403). Clock gate 410 
requires that signal MER and the Enable Return from Routine Recovery 
Register Strobing (ERS) both be true in order for the Gated Clock Signal 
(GCS) to strobe Arithmetic Logic Unit (ALU) 407, Return from Recovery 
Routine Register (RRRR) 404, and the external data and status registers 
(not shown). 
Error Recovery Operation 
For explanation purposes, assume that a memory read has been executed 
during microcycle MC1, and that the data read contains an error. Within 
100 ns. of the beginning of the following microcycle (MC2), error 
correction circuit 302 detects the error, latches the corrected data, and 
generates a memory error signal on lead MER. 
The memory error signal disables clock gate 410. The Gated Clock Signal 
(GCS) lead is held false, and does not strobe microinstruction register 
405, Arithmetic Logic Unit 407, Return from Recovery Routine Register 404, 
and the external data and status registers. Since Return from Recovery 
Routine Register 404 has not been strobed, the address of the 
microinstruction that was executing during microcycle MC2 remains in 
Return from Recovery Routine Register 404. This address is retained 
because the microinstruction must be re-executed when the error recovery 
routine completes. 
The memory error signal on lead MER forces a system branch to the error 
recovery microroutine as explained next: 
1. The MER signal disables the microinstruction register branch address 
output (lead MBA) from microinstruction register 405 to sequencer 402. The 
recovery routine address is transmitted from recovery routine address 
register 409 on lead RRA to sequencer 402 via the SBI bus. 
2. The MER signal forces the FS output of function multiplexer 406 to 
output a function code directing sequencer 402 to perform an immediate 
branch to the Recovery routine using the address stored in recovery 
Routine Address Register 409 via the SBI bus. 
3. The recovery microroutine activates lead SPMC (refer to FIG. 3) to 
enable series read gate 305. The latched data from the output bus of error 
correction circuit 302 is enabled to the data input of processor 301 via 
the Input Data Bus (IDB). 
4. When the corrected data have been input, the firmware executes a 
diagnostic to determine if the error was a permanent error. If no 
permanent error condition is detected, the system returns to the original 
parallel error correction mode by processor 301 removing the connection 
control signal from lead SPMC. 
As part of this return to the original configuration, the last 
microinstruction in the recovery microroutine is an unconditional branch 
to the address contained in Return from Recovery Routine Register 404, 
which address represents the aborted microinstruction. A control bit (ERO) 
in the microinstruction disables the MBA output from microinstruction 
register 405 and enables the Return from Recovery Routine Address output 
(lead RRRA) from Return from Recovery Routine Register 404 to the SBI 
input of sequencer 402. Microinstruction register 405 now contains the 
aborted microinstruction which is re-executed. 
Permanent Error-Series Error Correction Mode 
From the previous explanation, it is evident that several microcycles are 
required in order to correct a memory read data error. When dealing with 
typical low error rates, these additional overhead microcycles present a 
negligible performance degradation. However, in the case of a permanent 
error, these additional microcycles for each read data error correction 
can significantly degrade system performance. To alleviate this 
performance degradation in the case of permanent errors, the parallel 
error correction circuitry is designed to switch to the series error 
correction mode when a permanent error is detected (refer to Detailed 
Description of FIG. 3 for additional details). 
When the diagnostic routine detects a permanent error, the system activates 
a conventional alarm circuit to indicate the permanent error condition. 
The processor has already disabled parallel read gate 304, and enabled 
series read gate 305 (refer to FIG. 3) and now maintains these gates in 
this mode by maintaining the connection control signal on lead SPMC. This 
maintains the error correction circuitry in the series error correction 
mode. The alarm signal remains active until the source of the permanent 
error has been corrected. Additionally, as long as the series error 
connection mode is activated, the diagnostic routine is disabled. The 
diagnostic routine mentioned above may be any one of a number of 
well-known evaluations. These include monitoring the frequency of errors 
to measure system performance. 
While a specific embodiment of the invention has been disclosed, variations 
in structural detail, within the scope of the appended claims, are 
possible and are contemplated. There is no intention of limitation to what 
is contained in the abstract or the exact disclosure as herein presented. 
The above-described arrangements are only illustrative of the application 
of the principles of the invention. Normally, other arrangements may be 
devised by those skilled in the art without departing from the spirit and 
the scope of the invention.