Methods and circuits for slew-rate calibration

Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.

TECHNICAL FIELD

The subject matter presented herein relates generally to high-speed electronic signaling.

BACKGROUND

Personal computers, workstations, and servers are general-purpose devices that can be programmed to automatically carry out arithmetic or logical operations. These devices include at least one processor, such as a central processing unit (CPU), and some form of memory system. The processor executes instructions and manipulates data stored in the memory.

Memory systems commonly include a memory controller that communicates with some number of memory modules via multi-wire physical connections called “channels.” Each memory module commonly includes dynamic random-access memory (DRAM) components mounted on a printed circuit board. Successive generations of DRAM components have benefitted from steadily shrinking lithographic feature sizes. Storage capacity and signaling rates within DRAM components have improved as a result. Signaling rates between the memory controller and the DRAM components must improve to take full advantage of these improvements.

Memory modules have been provided with buffer chips disposed between the memory controller and the memory components. The buffer chip separately optimizes the controller and memory interfaces. So-called “data buffers” buffer data communicated from and to the memory controller. A separate address-buffer component, also called a “registering clock driver” (RCD) is used to convey command, address, and clock signals from the controller to each memory component. The RCD has multiple clock transmitters, each transmitting a clock signal—a timing reference that periodically transitions between voltage levels—to multiple memory components over a transmission line. The RCD also has multiple command/address transmitters that each convey command and address signals over a respective transmission line. The RCD transmitters and memory components present impedance discontinuities on the transmission lines, discontinuities that generate signal reflections that distort signals and produce errors. The magnitude of the signal reflections, and thus the errors, for a given signal depends on the signal's slew rate, which is to say the speed at which the signal changes between voltage levels. Slew rates can be adjusted to reduce errors but the methods and circuits used to calibrate slew rate are inadequate for clocking and signal transmission at very high frequencies.

DETAILED DESCRIPTION

FIG.1depicts an integrated circuit (IC)100with a multi-link driving amplifier (driver)105capable of transmitting twenty-four clock signals YCK[23:0] and seventy command-and-address signals QCA[69:0]. These signals, each either single-ended or differential, express binary values by transitioning between relatively high and low voltages. Driver-calibration circuitry110and slew-rate (SR) calibration circuitry115control multi-link driver105to manage the slew rate for each signal. SR calibration circuitry115includes a ring oscillator120that issues four reference clock signals SR_Ck[3:0] to respective calibration input nodes of SR computation circuitry125, the frequencies of which signals provide measures of SR calibration for driver105. SR computation circuitry125computes SR calibration signals SCp0, SCn0, SCp1, and SCn1from those frequencies and impedance-calibration signals ZCalp0, ZCaln0, ZCalp1, and ZCaln1from driver-calibration circuitry115.

Multi-link driver105includes two sets of transmitters, a first set130of twenty-four clock transmitters135and a second set140of seventy command-and-address (CA) transmitters145. Transmitters135and145drive different loads and are thus sized differently. They can be physically different but are assumed to be similar for ease of illustration, each including SR adjustment circuitry150sending three pull-up signals Pu[2:0] and three pull-down signals Pd[2:0] to input nodes of a driver amplifier, or “driver,”155.

With reference to the uppermost clock transmitter135, SR adjustment circuitry150receives a clock signal YCK0′ and, from calibration output nodes of SR computation circuitry125, a pair of SR calibration codes SCp0and SCn0. SR adjustment circuitry150issues three delayed instances of signal YCK0′ as pull-up signals Pu[2:0], which stimulate driver155to pull output signal YCK0up toward its relatively high voltage. Three delayed versions of signal YCK0′, pull-down signals Pd[2:0], likewise pull output signal YCK0down toward its relatively low voltage. The phases of signals Pu[2:0] are offset from one another, and the offsets can be adjusted to change the slew rate of rising edges of transmitted signal YCK0. The phases of signals Pd[2:0] can likewise be adjusted to change the slew rate of falling edges.

Signals SCp0and SCn0from SR calibration circuitry115control the phase offsets for signals Pu[2:0] and Pd[2:0] in transmitters135, while signals SCp1and SCn1do the same for transmitters145. SR computation circuitry125computes the values for signals SCp0, SCn0, SCp1, and SCn1using four separate oscillators within oscillator120, one ring oscillator each for the pull-up and pull-down adjustments in sets130and140of the transmitters. The one ring depicted includes three SR delay elements160that are laid out to replicate the timing behavior of a pull-up multiphase generator within each instance of SR adjustment circuitry150in clock transmitters135. The details of how this is done are discussed below. The frequencies of signals SR_Ck[3:0] are functions of the phase offsets between pull-up and pull-down signals in SR adjustment circuitry150in each of transmitters135and145.

SR computation circuitry125also employs signals from driver-calibration block110to compute SR calibration signals SCp0/SCn0and SCp1/SCn1. Block110includes a finite-state machine (FSM)165, a pair of replica drivers170and175, and a reference impedance180. Impedance180is depicted using dashed lines to emphasize that it is not integrated with IC100but is rather an external 240-ohm reference resistor in this example. Recalling that the drivers155in transmitters135are different from those of transmitters145, and are thus calibrated separately, replica drivers170and175are replicas of drivers155in transmitters135and145, respectively. Replica circuits are generally formed on the same IC as the circuits they replicate and operate under the same or similar parameters. Process variables that lead to performance differences between ICs tend to cancel, as do the impacts of shared supply voltages and temperature. Replica circuits need not be identical to the circuits they replicate so long as their performance varies predictably with process, voltage, and temperature.

FSM165executes a calibration sequence that sets the output impedance, or driver impedance, of each of replica drivers170and175to match that of impedance180. Each driver170and175has pull-up and pull-down elements so there are four driver-calibration codes, signals ZCalp0and ZCaln0for calibrating drivers155in transmitters135, and signals ZCalp1and ZCaln1for calibrating drivers155in transmitters145. These driver-calibration codes are also conveyed to SR computation circuitry125to address the impact of output-impedance calibration on slew rate. An optional look-up table (LUT)185provides SR computation circuitry125with mode settings in support of e.g. selectable drive strengths, or drive powers, for transmitters135and145. The impact of drive strength on slew rates and the related manner of calibration are discussed below in connection withFIG.4.

FIG.2Adepicts a single instance of transmitter135, the functional equivalent to one of transmitters145. SR adjustment circuit150includes an input amplifier200, a pair of level shifters205and210, a pull-up multiphase generator215, and a pull-down multiphase generator220. Driver155is divided into a pull-up drive element225and a pull-down drive element230. Drive elements225and230are simplified to provide a functional description; practical drivers are more complex and are well understood by those of skill in the art. Also well known, parasitic capacitances Cpar on the output node and elsewhere vary and impact the slew rates of output signals, clock signal YCK0in this instance. The signal link from driver155terminates to a supply node vdd via a load resistor235. The link and load impedance also impact the SR of signal YCK0.

Beginning with input node YCK0′ and like-identified signal, input amplifier200amplifies signal YCK0′ and conveys its output to level shifters205and210, which shift the voltage ranges of the input signal to accommodate the input requirements of respective phase-generators215and220. The shifted input signal YCK0udrives pull-up multiphase generator215, which draws from supply nodes at 1V and 240 mV; the shifted input signal YCK0ddrives pull-down multiphase generator220, which draws from supply nodes at 760 mV and 0V. Pull-up multiphase generator215, responsive to each rising edge of signal YCK0u, pulls each signal Pu1, Pu1, and Pu2down in succession, thus turning on each corresponding transistor within pull-up drive element225in succession. Output signal YCK0is pulled up toward supply voltage vdd as a result.

SR calibration signal SCp0sets the phase offsets between signals Pu0, Pu1, and Pu2. These phase offsets determine how quickly the transistors are recruited in pulling up the output node, and consequently impact the slew rate of rising edges of signal YCK0. The pull-down aspect of transmitter135works similarly. Pull-down multiphase generator220, responsive to each falling edge of signal YCK0d, pulls each signal Pd0, Pd1, and Pd2up in succession, thus turning on each corresponding transistor within pull-down drive element230in succession. Output signal YCK0is pulled down toward ground potential (0V) as a result. Calibration signal SCn0sets the phase offsets between signals Pd0, Pd1, and Pd2, which determine how quickly the transistors are recruited in pulling down the output node, and consequently impact the slew rate of falling edges of signal YCK0.

FIG.2Bis a waveform diagram250illustrating how phase offsets between edges of signals Pu[2:0] impact the slew rate of rising edge of output signal YCK0and phase offsets between edges of signal Pd[2:0] impact the slew rate of falling edges of output signal YCK0. Because the focus is on timing, the input signals YCK0u/dare shown together, despite spanning different voltage ranges, and signals Pu[2:0] and Pd[2:0] are overlayed with emphasis on transitions that impact driver155.

Beginning with the first falling edge of signal YCK0u/dand the uppermost instance of output signal YCK0, pull-up multiphase generator215pulls signals Pu[2:0] down in succession. Per the setting of calibration signal SCp0, signals Pu1, Pu1, and Pu2are delayed by increments of a time D1, respectively D1,2D1, and3D1. The rising-edge slew rate of signal YCK0is a function of time D1. Next, at the first rising edge of signal YCK0u/d, pull-down multiphase generator20pulls signals Pd[2:0] up in succession, each phase delayed by an increment of D1under control of signal SCn0. The falling-edge slew rate of signal YCK0is thus also a function of time D1.

The lowermost instance of output signal YCK0illustrates the same slew-rate functionality but with calibration signals SCp0and SCn0set to reduce the incremental delay from D1to D2, a difference labeled ΔD. As before, multiphase generators215and220issue their respective signals in succession, but the reduced phase delay D2means transistors within driver155are recruited more quickly and the slew rates of signal YCK0are thus reduced. SC calibration signals SCp0and SCn0can thus be used to adjust and calibrate the slew rate of output signal YCK0.

Transmitter135is single-ended in this embodiment but can also be differential. A differential embodiment can replicate the circuitry ofFIG.2Awith inverting level shifters to provide a complementary signal half, an inverted version of output signal YCK0that can accompany that signal to the signal destination.

FIG.3details an embodiment of pull-up multiphase generator215ofFIG.2. The other multiphase generators can be similar. This instance includes N programmable delay elements Dly[N:1], N being three in the foregoing example. Considering delay element Dly1, a pair of CMOS inverters are separated by a signal trace300that is coupled to the lower supply voltage via a collection of CMOS pass gates305in series with capacitors C1. Control nodes, at the gates of the PMOS and NMOS transistors of pass gates305, receive binary control inputs from SR calibration signal SCp0. The more pass gates305are enabled, the higher the capacitive loading on trace300and the longer the delay through delay element Dly1. The remaining delay elements Dly[N:2] exhibit similar behavior responsive to the same calibration signal SCp0, except that the value of the capacitive loading, and therefore the delay, is incrementally increased by the capacitance of capacitors C1in delay element Dly1. Signal YCK0uis thus replicated as N phase-shifted output signals Pu[N:1].

SR calibration circuitry115computes calibration signal SCp0using driver calibration settings ZCalp0/ZCaln0, the pull-up and pull-down settings for clock drivers155in transmitters135, and the frequency of signal SR_Ck0from ring oscillator120. A clock-enable signal CkEn, asserted during calibration, causes an NAND gate320to feed the inverted output from one of delay elements160back to another. The resultant ring oscillates at a frequency that is a function of the delays through delay elements160. Each delay element160is an instance of element DlyN using the same supply nodes. Being physically and electrically similar, the delay through each element160is a similar function of process, voltage, and temperature to the delay through element DlyN. The frequency of signal SR_Ck0is a function of the delays through elements160, and therefore element DlyN. The frequency of signal SR_Ck0thus provides a measure of the incremental delay D1separating the phases of signals Pu[N:1]. The number of capacitors selected in each delay element160can be adjusted to set the oscillation frequency within some functional range of circuitry or instruments employed to measure the frequency.

A second oscillator, not shown, provides a measure of delay D2for pull-down multiphase generator220, and a second pair of oscillators provide similar delay measures for pull-up and pull-down drivers in CA transmitters145(FIG.1). The periods of signals SR_Ck[3:0] are merely the inverses of the frequencies so any measure of frequency is also a measure of period, and vice versa.

FIG.4is a flowchart400illustrating a process of SR calibration in accordance with one embodiment. To begin with, and with reference to IC100ofFIG.1, values ZCalp0_typ and ZCaln0_typ, typical values of calibrated driver-control signals ZCalp0and ZCaln0, are derived by simulation, testing, or a combination of the two. Typical values freq_pu_typ and freq_pd_typ are likewise obtained for the frequencies for signals SR_Ck[1:0] (step405). These typical values are stored with similar values for the circuitry of CA transmitters145and used for reference in calibrating instances of IC100.

The following discussion describes the calibration process for one of transmitters135, in particular pull-up multiphase generator215and pull-down multiphase generator220ofFIG.2Aand their respective and associated drive elements225and230. The process for calibrating transmitters145is the same or similar and is thus omitted for brevity. Step410marks the beginning of a calibration process. Drive strength is calibrated using driver calibration circuitry110, as described above, and the calibrated values of signals ZCalp0/ZCaln0and the frequencies freq_pu/freq_pd of ring-oscillator output signals SR_Ck[1:0] are measured and stored. Drive-strength signals ZCalp0and ZCaln0control respective drive elements225and230(FIG.2). The manner of drive-strength control is not shown in this simplification but is well known.

Next, in step415, SR computation circuitry125calculates values ron_effect_pu and ron_effect_pd, the contributions of the measured values of signals ZCalp0and ZCaln0on the slew rates of the signals from the corresponding calibrated driver155. In one embodiment, this calculation takes the difference between each measured and typical value and scales each result by a factor arrived at for IC100either empirically or by simulation, e.g. by dividing each difference by a constant B. Stated mathematically, ron_effect_pu=(ZCaln0−ZCaln0_typ)/B; and ron_effect_pd=(ZCalp0−ZCalp0_typ)/B. In one embodiment, B is five. The resulting values ron_effect_pu and ron_effect_pd for transmitter135are stored for use in subsequent computations.

A ring oscillator120for each of the four types of pull-up and pull-down circuitry in drive amplifiers155provides a measure of slew rate for the corresponding type. Being focused on just one transmitter135with its pull-up and pull-down drive elements, in step420SR computation circuitry125calculates slew-rate offsets for each of drive elements225and230by comparing the measured frequencies freq_pu and freq_pd of clock signals SR_Ck[1:0] with the typical ones freq_pu_typ and freq_pd_typ from step405. For each of the two types, SR computation circuitry125calculates a slew-rate offset by taking the difference between the measured frequency and the typical frequency and scaling the result by a constant for IC100, the constant derived either empirically or by simulation, and adding the corresponding drive-strength correction from step415. In one example, the slew-rate offset_pu for pull-up multiphase generator215is calculated as follows: offset_pu=Integer(freq_pu−freq_pu_typ)/A+ron_effect_pu; and the slew-rate offset_pd for pull-down multiphase generator220is calculated as offset_pd=Integer(freq_pd−freq_pd_typ)/A+ron_effect_pd, the constant A being e.g. 30.

In some embodiments, SR computation circuitry125conveys the calibration values from step420to each of the affected drivers. In other embodiments, amplifiers155are configurable in a manner that benefits from further calibration. Returning toFIG.1, for example, each of transmitters135and145can be one of N parallel slices working together to drive the same signal on the same output node. Drive strength can then be adjusted by enabling all or a subset of those slices. In an embodiment in which N is twenty-four, each transmitter can be programmed as strong (all twenty-four slices enabled), moderate (seventeen slices enabled), or light (twelve slices enabled) by writing configuration values in LUT185. Enabled slices share the task of transmitting a common signal, so the drive-strength setting can impact the slew rate of each output signal. For this reason, SR computation circuitry125reads a register (e.g. LUT185) that specifies the number of active slices in each driver of the configuration under test (decision425), branching to one of steps430,435, and440depending on the number of active slices in a given power mode.

Step430assumes twelve active slices in the transmitter135used in this illustration. SR computation circuitry125reads LUT185to receive a pair of base codes BCpu and BCpd for the pull-up and pull-down drive circuitry in the twelve-slice mode. An adjustment adj_ron is then calculated for the mode. In one embodiment, SR computation circuitry125calculates adj_ron as follows: adj_ron=Integer(Abs(offset_pu−offset_pd)*(240/RZQ)/12). RZQ is a constant and has a value of e.g. 240 Ohms. Steps435and440are similar to step430except that the denominator changes from twelve to seventeen or twenty-four, respectively. Whichever of step430,435, and440is selected produces a value adj_ron for use in step445.

In the final step445, SR computation circuit125calculates pull-up and pull-down skew codes SCp0and SCn0using the values slew_base_p, slew_base_n, and adj_ron from the prior step. In one embodiment, slew code SCp0=slew_base_p+offset_pu*adj_ron and slew code SCn0=slew_base_n+offset_pd*adj_ron. These values are passed respectively to PU phase generator215and PD multiphase generator220to control the slew rates of pull-up and pull-down drive circuitry225and230, and thus of driver155and corresponding output signal YCK0.

FIG.5depicts a memory system500in which a controller component505issues address and control signals to a memory module510to manage the flow of read and write data from and to a collection of memory components515. Controller component505issues complementary strobe signals DQSu± and DQSv± as timing-reference signals that accompany respective parallel, single-ended data signals DQu[3:0] and DQv[3:0] to a module connector517. Component505also provides a shared clock signal DCK±, likewise complementary in this embodiment, as a separate timing reference for command and address signals DCA. A data buffer520that manages the communication of data between controller component505and memory components515includes parallel decision-feedback equalizers (DFEs) for sampling incoming data symbols and adaptive tap-value generators (TVGs) that derive tap values for the DFEs based on the frequency response of the data signal paths. The DFEs forward data and timing signals to memory components515via data-buffer core logic. Memory interfaces, optionally including equalization circuitry, manage the flow of read data from memory components515to the core logic and, ultimately, to controller component505.

An address buffer535manages the communication of command and address signals between controller component505and memory components515. Address buffer535includes logic545that interprets signals command-and-address (CA) signals DCA from controller component505, timed to a complementary clock signal DCK±, to issue clock and CA signals to multi-link driving amplifier105(FIG.1), which responsively issues memory-side clock signals YCK and command/address signals QCA to memory components515to manage the flow of read and write data from and two memory components515. (Driver-calibration circuitry110and SR calibration circuitry115are also instantiated on RCD535but are not shown.) Logic545also issues data-buffer control signals DBC that direct the movement of read and write data through data buffers520. Data buffers520and address buffer535compensate for signal deterioration using specialized interface circuitry that can otherwise be incorporated into memory components515in other embodiments. This interface circuitry can include slew-rate calibration support of the type detailed above.

In the write direction, with the data and address buffers calibrated, controller component505directs command, address, and clock signals on primary ports DCA and DCK± to address buffer535, which responsively issues command and address signals YCK/QCA to memory components515and control signals DBC to data buffers520to prepare for the receipt of write data. Controller component505sends the data to data buffers520via two groups of four data links DQu[3:0] and DQv[3:0], each with an accompanying data strobe DQSu± and DQSv±, one link group for each memory component515. Address-buffer component535interprets control signals (e.g., commands, addresses, and chip-select signals) received in parallel on port CA and communicates appropriate command, address, chip-select, and clock signals to memory components515(e.g. DRAM packages or dies) via a secondary control interface YCK/QCA. Addresses associated with the commands on primary port DCA identify target collections of memory cells (not shown) in components515and chip-select signals associated with the commands allow address-buffer component535to select individual integrated-circuit DRAM dies, or “chips,” for both access and power-state management.

Data-buffer components520and address-buffer component535each act as a signal buffer to reduce loading on module connector517. This reduced loading is in large part because each buffer component presents a single load in lieu of the multiple memory components515each buffer component serves. The interfaces between data-buffer components520and memory components515can include slew-rate calibration support of the type detailed above.

While the present invention has been described in connection with specific embodiments, after reading this disclosure variations of these embodiments will be apparent to those of ordinary skill in the art. For example, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or “coupling,” establishes some desired electrical communication between two or more circuit nodes, or terminals. Such coupling may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.