TECHNIQUE FOR LIMITING TRANSMISSION OF PARTIAL SYMBOLS IN REPEATER DEVICE

A repeater device includes a packet input and a packet output. A first path extends from the packet input to the packet output. The first path includes a transmitter having a transmitter input coupled to the packet input, a transmitter output coupled to the packet output, and a transmitter enable. A second path extends in parallel with the first path and includes a variable delay circuit. The variable delay circuit has an input coupled to the packet input and an output coupled to the transmitter enable of the transmitter.

BACKGROUND

Universal Serial Bus (USB) is an industry standard that establishes specifications for cables and connectors, and protocols for connection interfacing, communication interfacing, and power supply interfacing between electronic devices. A broad variety of USB hardware exists, including 14 different connector types, of which USB-C is the most recent.

First released in 1996, the USB standards are maintained by the USB Implementers Forum (USB-IF). The four generations of USB are: USB 1.x, USB 2.0, USB 3.x, and USB4. There are also supplements to four generations of USB standards. Each of these standards and their specifications are hereby incorporated by reference in their entirety.

For example, the embedded USB2 (eUSB2) specification is a supplement to the Universal Serial Bus (USB) 2.0 specification. eUSB2 can support onboard inter-device connectivity through direct connection between two eUSB2 configured elements, as well as through an eUSB2 repeater. The eUSB2 repeater is a half-duplex bidirectional interconnect that enables integration of legacy USB devices (which operate with I/O voltages of 3.3 V) with advanced eUSB2 devices (which operate at I/O voltages of 1 V or 1.2 V). Thus, eUSB2 enables more power-efficient System on Chips (SoCs), which in turn, enables continued scaling of process nodes while increasing performance in electronic devices, e.g., smartphones, tablets and notebooks.

SUMMARY

Independent claims will be reproduced here once finalized.

The same reference numbers or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features.

DETAILED DESCRIPTION

The following description provides many different examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present description. The drawings are not drawn to scale.

While legacy USB 2.0 repeaters may use a clock data recovery (CDR) circuit or phase-locked loop (PLL) to re-clock the output states of Start of Packet (SOP) symbols or bits without transmitting a partial symbol or bit, the addition of the PLL increases power consumption, size and cost. Thus, some aspects of the present disclosure relate to a USB 2.0 repeater that can be implemented without a CDR circuit, PLL, or first-in-first-out (FIFO) component. Without such functionality, conventional eUSB2 repeaters cannot buffer and resynchronize the start of packet (SOP) synchronization symbols or bits to send via the output stage transmitter of the eUSB2 repeater, which can lead to SOP symbols or bits being truncated. This truncation stems at least in part from timing variations between a data path and control path in the repeater. Thus, the present disclosure provides a fixed delay circuit on the control path that accounts for these timing variations for a given temperature and voltage. The fixed delay circuit may have a fixed timing delay for a given supply voltage and temperature, but may vary over a range of supply voltages and temperatures. Therefore, the present disclosure further provides a variable delay circuit in series with the fixed delay circuit. The variable delay circuit has a variable delay that is adjusted to account for further timing variations due to fluctuations in temperature and voltage supply. This variable delay circuit further limits transmission of truncated symbols and/or partial bits, such that the disclosed techniques provide robust communication within communication networks.

FIG.1illustrates a repeater device100, andFIG.2illustrates some sample waveforms200consistent with repeater device100according to some examples. A brief structural overview of repeater device100is now provided, and then more detailed behavior and several advantages of repeater device100is provided with regards toFIG.2. Although some examples are mentioned below where the repeater device100is described in terms of a eUSB2 repeater, the repeater device100is also applicable to other USB communication standards, other industry communication standards, as well as propriety communication standards.

Referring toFIG.1, the repeater device100includes a packet input102and a packet output104. While packet input102and packet output104are illustrated as single conductors, one or both may include two or more conductors (for example, two conductors may be used for differential signaling). The packet input102can receive a stream of incoming data packets that contain data, and repeater device100can re-transmit and/or repeat, via the packet output104, the data as a stream of outgoing data packets. In some cases, the stream of incoming packets are received according to a first I/O voltage range, and the outgoing data packets are transmitted at a second I/O voltage range that differs from the first I/O voltage range. For example, in some implementations where the repeater device100is an eUSB2 repeater, the packet input102can receive a stream of eUSB2 high speed (HS) data packets that were sent by a System on Chip (SoC) operating at a first I/O voltage range of around 1V to 1.2V, and the repeater device100(via packet output104) can re-transmit a stream of USB2.0 HS data packets operating at a second I/O voltage range of around 3.3 V, and/or vice versa, such that the repeater device100provides interoperability between legacy 3.3 V USB2.0 systems and more advanced 1 V or 1.2 V eUSB2 systems. Further, the incoming data packets can be Start of Packet (SOP) synchronization bits.

To facilitate this functionality, the repeater device100includes a first path106and a second path108which extend in parallel with one another. In some examples, at least one other first path106(and, possibly, at least one other second path108) is incorporated in repeater device100(but configured in the opposite direction) for signal transmissions in the opposite direction. The first path106, which may be referred to as a data path in some contexts, extends between the packet input102and the packet output104. The first path106can include a receiver110, a buffer112, a pre-driver114, and a transmitter116which are arranged in series with one another along the first path106. The transmitter116can include a transmitter driver115and a switch117. The transmitter driver115provides intermediate packet data (tx_out_int), which contains the same data as the incoming packet data albeit delayed and, in some cases, with a different voltage range. The switch117enables and disables transmission of the intermediate packet data (tx_out_int), based on a state of the transmitter enable116e, thereby providing output packet data (tx_out_en3) from the packet output104.

The second path108includes a squelch detector118and repeater logic120which are arranged in series with one another on the second path108. A fixed delay circuit122and a variable delay circuit124are also included in series on the second path108, which may be referred to as a control path in some contexts. A control124cof the variable delay circuit124is coupled to a control circuit output of a control circuit126, and an output of the variable delay circuit124ois coupled to the transmitter enable116e. The control circuit126can include a temperature sensor128and/or a voltage supply sensor130whose outputs are coupled to the control124cof the variable delay circuit124. The repeater logic120provides a first enable signal (en1); the fixed delay circuit122provides a second enable signal (en2); and the variable delay circuit124provides a third enable signal (en3). The third enable signal enables and disables the switch117in a manner that promotes transmission of full symbols or bits and limits transmission of partial symbols even over changes in supply voltage and/or temperature.

Referring now toFIG.2and to various elements ofFIG.1, some sample waveforms200depict a first re-transmission operation201and a second re-transmission operation203. The first re-transmission operation201occurs while the repeater device100is subject to a first temperature T1 and a first supply voltage V1; and the second re-transmission operation203occurs while the repeater device100is subject to a second temperature T2 and a second supply voltage V2, where T1 differs from T2 and/or V1 differs from V2.

Incoming packet data202is received at the packet input102. The incoming packet data202has a voltage that varies in time over a first I/O voltage range. Thus, the voltage is modulated in time over the first I/O voltage range to define incoming packet data202, which is organized into symbols having respective unit intervals (UIs) or time slots. Each symbol corresponds to one or more bits of data for a respective UI. The UIs have equal durations in some examples. In some examples, incoming packet data202is USB data, such as eUSB2 HS data having a first I/O voltage range of 1V or 1.2V, and in particular can be Start of Packet (SOP) synchronization bits.

As the incoming packet data202propagates along the first path106, the incoming packet data202experiences a first path delay205before the transmitter driver115provides the intermediate packet data204(tx_out_int). Thus, while the intermediate packet data204has the same data content as the incoming packet data202, the intermediate packet data204has symbol/UI edges that are shifted by the first path delay205relative to that of the incoming packet data202, and can also have a voltage amplitude that is shifted to the second I/O voltage range, which differs from the first I/O voltage range. For example, the second I/O voltage range can be around 3.3V in some examples. Accordingly, whereas the incoming packet data202when initially received is compliant with a first standard (e.g., incoming packet data are eUSB2 HS data over a voltage range of around 1V to 1.2V), the intermediate packet data204when ready for re-transmission can be compliant with a second standard (e.g., USB2.0 HS data over voltage range of around 3.3 V). Nonetheless, the intermediate packet data204ideally represents the same symbols and same digital data as the incoming packet data202, albeit delayed relative to the incoming packet data202.

In addition to the incoming packet data202containing valid data, the incoming packet data202may also include unwanted noise, due to the highly sensitive nature of the receiver110. To help limit re-transmission of this noise further downstream, the second path108includes squelch detector118, which outputs an un-squelch signal at output of squelch detector118. This un-squelch signal is used by repeater logic120to help ensure that noise, which may have been amplified over multiple gain stages and is received as part of incoming packet data202, is not re-transmitted at the packet output104. That is, the squelch detector118does not activate the un-squelch signal until a high enough signal is detected to at the packet input102to distinguish valid incoming packet data202from noise, and the repeater logic120then provides a first enable signal206(en1) based on the un-squelch signal.

In principle, the first enable signal206(en1) could be provided directly to the transmitter enable116eto trigger transmission of the intermediate packet data204. However, as shown inFIG.2, due to a second delay217, which arises from the squelch detector118and repeater logic120, the rising edge of the first enable signal206(en1) is offset relative to edges of the intermediate packet data204(see207inFIG.2). Thus, if the first enable signal206(en1) were used directly to enable transmission of the intermediate packet data204by the transmitter enable116e, it would result in a truncated symbol (e.g.,209) being re-transmitted, as shown in waveform208. Such a truncated symbol may cause communication errors for some downstream receivers, and as such transmission of truncated symbols or bits is undesirable.

Therefore, to substantially account for this time delay difference between the first path delay (e.g.,110,112,114,115) and the second path delay (e.g.,118,120), the second path108includes the fixed delay circuit122. Thus, as shown inFIG.2, the fixed delay circuit122provides a second enable signal210(en2) whose edges are shifted relative to edges of the first enable signal206(en1) by fixed time delay219. Under some circumstances when a baseline temperature and voltage condition is present (e.g., T1 and V1 during first re-transmission operation201), this fixed time delay219causes the second enable signal210(en2) to align to a symbol edge of the intermediate packet data204(again see time211inFIG.2). Hence, under such a baseline temperature and voltage condition, the variable delay circuit124can be set to a substantially zero delay (e.g., a delay of less than 1 nanosecond, less than 0.1 nanoseconds, or even less than 0.01 nanoseconds), and en2 is aligned with en3 (see time211inFIG.2). In some cases, the fixed delay circuit122can be referred to as a partial bit filter, and can be implemented as provided in application Ser. No. 17/680,697 entitled “Partial Bit Filter for USB Interface” and filed on Feb. 25, 2022, and which is incorporated by reference in its entirety.

As appreciated in some aspects of the present disclosure, however, when the repeater device100experience changes in temperature, changes in voltage supply, and/or changes in other operating conditions (e.g., which deviate from the baseline temperature and voltage condition during first re-transmission operation201), these changes can cause timing shifts in the first path106and/or second path108. For example, during the second re-transmission operation203, the temperature has dropped to a second temperature (T2) and supply voltage has risen to a second voltage (V2). This supply voltage change and/or temperature change can cause the first path timing delay to shift from205to221, and/or can cause the control path timing delay to shift from217to223, and/or can shift the fixed time delay to shift from219to225. This timing shift moves edges of the second enable signal210(en2) so they are no longer aligned to symbol edges of the intermediate packet data204as previously shown by211during first re-transmission operation201, but now are offset from symbol edges of the intermediate packet data204(see line213). Hence, if the intermediate output data (tx_out_int) were transmitted using the second enable signal210(en2) during second re-transmission operation203, a partial symbol would again be retransmitted (see237).

Accordingly, to remedy this offset between the edges of the second enable signal210(en2) and the symbol edge of the intermediate packet data204due to changes in temperature or supply voltage, the control circuit126can adjust the timing delay of the variable delay circuit124based on a measured temperature of the repeater device provided by the temperature sensor128and/or a measured voltage supply of the repeater device provided by the voltage supply sensor130. Thus, in response to the control circuit126detecting a voltage supply change and/or temperature change, the control circuit126“tunes” the timing delay of the variable delay circuit124to adjust the variable time231, thereby keeping the edge of the third enable (en3) aligned to a symbol edge in the intermediate packet data204—see215. Thus, during second re-transmission operation203, the third enable signal214(en3) has an edge that is aligned to a symbol edge of the intermediate packet data204, resulting in re-transmission of full symbols and/or full bits over a wide range of temperatures and supply voltages for packet output data216(tx_out_en3). Because transmission of truncated symbols and/or partial bits is limited even over changes in temperature and/or voltage supply, these techniques provide robust communication within networks.

Thus, in both the first re-transmission operation201and the second re-transmission operation203, the packet output data216(tx_out_en3) is transmitted by using the third enable signal (en3) to enable the transmitter116, for example by closing switch117. In the first re-transmission operation201, the variable time of the variable delay circuit124is set to zero, while in the second re-transmission operation203, the variable time231of the variable delay circuit124is increased. As other temperature and/or supply voltage conditions arise, the control circuit126can tune the variable time231in response to the detected temperature and/or supply voltage variations. In some cases, using this variable time231may cause the first two symbols235to be omitted from the packet output data216relative to the incoming packet data202, but for the remaining symbols that are re-transmitted they are full symbols or bits that limit truncated symbol/bit issues for downstream devices. Thus, the USB outgoing packet data is bit-wise identical to the USB incoming packet data except the leading bit and consecutive following bits of the predetermined sync bit pattern of the USB outgoing packet data corresponds to the third bit and consecutive following bits of the predetermined sync bit pattern of the USB incoming packet data.

Although the repeater device100ofFIG.1has been illustrated and described in some regards as a unidirectional device (e.g., where data is received at the packet input and is transmitted at the packet output), it will be appreciated in other cases the repeater device100can be a bidirectional device that can receive data packets at the second voltage level at packet output and retransmit the data packets at the packet input (e.g., receive USB2.0 high speed data packets and re-transmit eUSB2 high speed data packets). Notwithstanding two synchronization symbols or bits that may be lost at the start of a packet due to the various internal delays, the data retransmitted in the eUSB2.0 high speed data packets is the same as the data in the eUSB2 high speed packets.

Further, though the variable delay circuit124ofFIG.1is illustrated at the end of the second path108between an output of the fixed delay circuit122and the transmitter enable116e, the variable delay circuit124can also be arranged at other positions on the second path108. For example, in another example, the variable delay circuit124can be arranged between the squelch detector118and the packet input102. In still another example, variable delay circuit124can be arranged between the squelch detector118and the repeater logic120, while in still other examples the variable delay circuit124can be arranged between the repeater logic120and the fixed delay circuit122. In other examples, fixed delay circuit122may be omitted and variable delay circuit124can compensate for such omission by suppling the appropriate delay. In some examples, the magnitude of delay (for the variable delay circuit124and/or the fixed delay circuit122) may be determined during device manufacturing and/or testing (e.g., wafer-level testing, singulated device testing and/or packaged device testing). The correlation between delay magnitude and external factors (e.g., temperature differences, device fabrication differences, voltage variations, etc.) may be stored in memory or a look-up table and later used during device operation.

In addition, the variable delay circuit124can also be split into multiple components that are directly adjacent to one another and/or spaced apart along the second path108. For example,FIG.3shows another example where a first variable delay circuit124aand a second variable delay circuit124bare arranged in series on the second path108. The first variable delay circuit124acan be adjusted based on the temperature sensor128, and the second variable delay circuit124bcan be adjusted based on the voltage supply sensor130. Although illustrated as directly adjacent to one another inFIG.3, the first variable delay circuit124aand second variable delay circuit124bcan also be interspersed between the packet input102, squelch detector118, repeater logic120, and fixed delay circuit122in various combinations, and can be flipped relative to one another along the second path108.

Referring now toFIG.4, repeater device400is an alternative embodiment of a repeater. In this example, the control circuit126includes a voltage supply/temperature selector402that selectively couples a temperature sensor128and a voltage supply sensor130to an analog-to-digital converter (ADC)404. The temperature sensor may be configured as a current source442and a resistor444coupled between a voltage supply (VCC)432and ground434; and the voltage supply sensor130may be implemented as a voltage divider, as shown inFIG.4, coupled between the voltage supply (VCC)432and ground434and including two resistors436,438, each having the same resistance value or a different resistance value (such as a 10 kohm resistor and a 20 kohm resistor)). An input of the ADC404is coupled to both an output of the voltage supply sensor130and an output of the temperature sensor128via the voltage supply/temperature selector402, and the ADC output is coupled to the control124cof the variable delay circuit124via decoder406. An input of the decoder406is coupled to the ADC output, and an output of the decoder406is coupled to the control124cof the variable delay circuit124.

The voltage supply/temperature selector402includes a switching network to couple the voltage supply sensor130to the control124cof the variable delay circuit124during a first time, and to couple the temperature sensor128to the control124cof the variable delay circuit124during a second time that differs from the first time. In the illustrated example, four switches are illustrated, and these switches can be implemented by transistors for example. A first switch408is coupled to a fixed reference voltage supply418(such as a bandgap reference that provides a fixed 1.2 V supply for example that is constant over temperature variations) and a second switch410is coupled to the voltage supply sensor130(e.g., to sensor voltage supply node435between the two resistors436,438). A third switch412is coupled to a reference temperature circuit420, and a fourth switch414is coupled to the output of the temperature sensor128.

Thus, during a first time, the first and second switches408,410can be closed (e.g., the switches are conducting) and the third and fourth switches412,414can be open (e.g., the switches are non-conducting) to couple first and second inputs of amplifier416to the fixed reference voltage supply418and the sensor voltage supply node435, respectively, and the amplifier416provides a first voltage to the ADC404. Hence, if the sensor voltage supply node435varies relative to the fixed reference voltage supply418, the voltage output provided by the amplifier416changes, and the ADC404changes its output digital signal accordingly. As this output digital signal is provided to the decoder406, which sets the control signal on control124cbased on the output digital signal, the control signal and hence the time delay of the variable delay circuit124is set to vary with changes in voltage supply for the first time. At a second time, the first and second switches408,410can be opened (e.g., switches are non-conducting) and the third and fourth switches412,414are closed (e.g., switches are conducting) to couple first and second inputs of the amplifier416to the reference temperature circuit420and the output of the temperature sensor128, respectively, causing the amplifier416to provide a second voltage to the ADC404. Hence, if the temperature to be measured varies relative to the reference temperature circuit, the voltage output provided by the amplifier416changes, and the ADC changes its output digital signal accordingly during the second time. As this output digital signal is provided to the decoder406, which sets the control signal on control124cbased on the output digital signal, the control signal and hence the time delay of the variable delay circuit124is set to vary with changes in temperature during the second time.

FIG.5depicts a more detailed example of the decoder406and the variable delay circuit124.

The variable delay circuit124includes a plurality of delay elements, such as invertors, buffers or the like, arranged in series along the second path. A plurality of switching elements each having a first switch terminal coupled to respective inputs of the plurality of delay elements, respectively, and each having a second switch terminal coupled to an output of the variable delay circuit (en3). The output of the variable delay circuit124(en3) is coupled to the transmitter enable116e(see e.g.,FIG.1).

In some embodiments, the decoder406is a one-hot decoder, though other decoding schemes can also be used. InFIG.5, for example, the decoder406receives 4 bits from the ADC404, and these 4 bits represent16possible binary states. Thus, the decoder406includes 16 output lines (e.g., a separate line for each binary state), such that when each of the16possible binary states is present a different line is activated. In this way, each digital state from the ADC enables a different switching element of the variable delay circuit, and provides a different timing delay from the variable delay circuit. For example, if a binary state of 0000 is provided from the ADC, the decoder could activate the first line and thereby close the first switching element, which provides a minimum delay (e.g., substantially zero delay) through the variable delay circuit. In contrast, if a binary state of 1111 is provided from the ADC, the decoder could activate the last line and thereby close the last switching element, which provides a maximum delay of 15 delay units through the variable delay circuit in this example.

FIG.6is a flow diagram600depicting a method for retransmitting signals in a communication system in accordance with some examples.

At602, incoming packet data is received. The incoming packet data starts with a predetermined sync bit pattern that includes N bits in N unit intervals, respectively. In some examples, the incoming data packet includes Start of Packet (SOP) synchronization bits in accordance with a Universal Serial Bus (USB) standard.

At604, intermediate packet data is provided after the receiving of the incoming packet data and prior to transmission of outgoing packet data.

At606, a transmission enable signal is provided based on the incoming packet data. The transmission enable signal has an edge that remains aligned to an edge of a unit interval of the intermediate packet data over different temperatures and over different supply voltages.

At608, outgoing packet data that is based on the incoming data packet is transmitted after the incoming packet has been received. The outgoing packet data includes N−k bits in N−k unit intervals whereas k can be any integer (e.g., 1, 2, 3, etc.), wherein the outgoing packet data is bit-wise identical with the incoming packet data except the first k bits of the predetermined sync bit pattern are omitted in the outgoing packet data. For example, the intermediate packet data can be selectively transmitted at the edge of the transmission enable signal, thereby transmitting the outgoing packet data so the USB outgoing packet data is bit-wise identical to the USB incoming packet data except a leading bit and consecutive bits following the leading bit of the predetermined sync bit pattern of the USB outgoing packet data correspond to a kthbit and consecutive bits following the third bit of the predetermined sync bit pattern of the USB incoming packet data. In the example ofFIG.2above, k=2 (see235).

In some cases, the incoming packet data is transmitted with a first voltage range and the outgoing packet data is transmitted with a second voltage range that differs from the first voltage range; and the respective unit intervals are equal in the incoming packet data and the outgoing packet data.

In some cases, the outgoing data packet includes only symbols or bits whose edges are aligned to edges of the N unit intervals, and no symbols or bits in the outgoing data packet have edges that are offset from the edges of the N unit intervals.

The methods are illustrated and described above as a series of acts or events, but the illustrated ordering of such acts or events is not limiting. For example, some acts or events may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Also, some illustrated acts or events are optional to implement one or more aspects or examples of this description. Further, one or more of the acts or events depicted herein may be performed in one or more separate acts and/or phases. In some examples, the methods described above may be implemented in a computer readable medium using instructions stored in a memory.

In this description, the term “couple” may cover connections, communications or signal paths that enable a functional relationship consistent with this description. Accordingly, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled directly to device B; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B, so device B is controlled by device A via the control signal generated by device A.

While the use of particular transistors are described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a metal-oxide-silicon FET (“MOSFET”) (such as an n-channel MOSFET, nMOSFET, or a p-channel MOSFET, pMOSFET), a bipolar junction transistor (BJT—e.g. NPN or PNP), insulated gate bipolar transistors (IGBTs), and/or junction field effect transistor (JFET) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other type of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).