Lateral persistence directory states

Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

BACKGROUND

The present invention generally relates to data processing, and more specifically, to lateral persistence director states in symmetric multiprocessing computers.

Contemporary high-performance computer systems are typically implemented as multi-node, symmetric multiprocessing (‘SMP’) computers with many compute nodes. SMP is a multi-processor computer hardware architecture where two or more, typically many more, identical processors are connected to a single shared main memory and controlled by a single operating system. Most multiprocessor systems today use an SMP architecture. In the case of multi-core processors, the SMP architecture applies to the cores, treating them as separate processors. Processors may be interconnected using buses, crossbar switches, mesh networks, and the like. Each compute node typically includes a number of processors, each of which may have at least some local memory, at least some of which is accelerated with cache memory. The cache memory can be local to each processor, local to a compute node shared across more than one processor, or shared across nodes.

SUMMARY

Embodiments of the present invention are directed to methods for lateral cache persistence. A non-limiting example computer-implemented method includes defining one or more processor units having a plurality of caches, wherein each processor unit comprises a processor having at least one cache from the plurality of caches, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class in the one or more congruence classes comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector for the first cache line, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

Embodiments of the present invention are directed to methods for lateral cache persistence. A non-limiting example computer-implemented method includes receiving a request to evict a first cache line from a first cache on a first microprocessor chip in a plurality of microprocessor chips in a processing drawer, the first cache line having a first set of lateral persistence bits tracking a scope for the first cache line, determining the scope of the first cache line, identifying a target cache having a saturation metric, wherein the target cache comprises a higher scope than the scope of the first cache line, and determining an action for the first cache line based on the saturation metric for the target cache and the scope of the first cache line.

Other embodiments of the present invention implement features of the above-described methods in computer systems and computer program products.

DETAILED DESCRIPTION

One or more embodiments of the present invention provide systems and methods for reducing memory accesses in an SMP environment. Traditionally, reductions in memory accesses are addressed utilizing large caches backing up smaller caches in an N-level vertical cache hierarchy. This includes drawbacks because at a particular cache level, not all the caches are utilized at the same rate. Because not all the caches are being utilized at the same rate, this opens up an opportunity to make use of any under-utilized cache space.

In one or more embodiments of the invention, in an SMP environment, aspects include defining lateral caches that can be used for persisting the cache evictions from a peer lateral cache. These peer lateral caches can be divided into clusters of caches with each cluster signifying a scope of persistence. A cache line that is evicted is allowed to persist, first, within a cluster of peer caches at the next scope of persistence. Then, as the cache line continues to be evicted from a cluster, other clusters can be utilized for storage of the cache line until the evicted cache line reaches a last cluster and can be evicted to main memory. Lateral persistence tag bits can be utilized for tracking the scope of cache persistence for each cache line. In the event of a cache fetch miss, when a cache line is installed for the first time in system caches, the lateral persistence directory tag is set to 0. As the cache line is installed in lateral caches within a cluster or in other clusters of caches, the directory tag is incremented and set to that corresponding scope of persistence where the target cache belongs to. A replacement algorithm/policy is implemented to determine at what level scope the cache line is to be evicted. A target cache is identifying within the scope level and an adaptive LRU (least recently used) replacement policy then determines where to install the cache line in the target cache's congruence class.

FIG.1depicts a distributed symmetric multiprocessing (SMP) system100(hereafter “system100”) in accordance with one or more embodiments. System100can include 4 processing units or “drawers.” Each drawer240-0,240-1,240-2,240-3includes eight (8) microprocessor (CP) chips (202-0-202-7). Each CP chip can include eight (8) cores204-0-204-7. Each core in the CP chip includes a private L1 cache206-0-206-7(including both instruction cache and data cache). These private L1 caches are backed by semi-private L2 caches208-0-208-7. In one or more embodiments of the invention, the semi-private L2 caches208can interact to provide an on-chip virtual L3 cache. Each processor drawer240contains up to 8 CP chips202with a fully connected topology providing a virtual L4 cache. The virtual L3 and virtual L4 caches can be implemented through a set of chip caching technologies that cluster the independent physical L2 caches208within a chip202and within a drawer240to act as a unified shared victim cache.

In one or more embodiments of the invention, the virtual L3/L4 caches are implemented by defining groups/clusters of L2 caches within a CP chip, group of CP chips, and/or drawers for evicting cache lines from peer caches. That is to say, a cache line is evicted from a first L2 to a peer L2 within the defined groups/clusters of L2 caches according to a defined replacement policy described herein.

In one or more embodiments of the invention, peer L2 caches (sometimes referred to as “lateral caches”) can be divided into clusters of caches214called primary, secondary, and tertiary, which can be extended into an infinite number of unique scopes. When a cache line is evicted from an L2 cache, this evicted cache line is allowed to persist within the cluster of caches214passing from one cluster after the other until it reaches a last cluster of caches. In one or more embodiments, lateral persistence (LP) tag bits can be utilized for identifying the scope of the persistence. That is to say, the tag bit can signify what is the current scope of persistence and how many scopes can the cache line hop before it is evicted to memory or re-referenced by a processor cache. In the event of a fetch miss when a cache line is installed for the first time into a system cache, the LP tag bit can be set to 0. And when the same cache line is evicted from the cache, the cache line is persisted in any of the other caches in the next scope of persistence (e.g., primary, secondary, or tertiary) within the lateral persistence tag bits being set to the respective scope of persistence.

In one or more embodiments of the invention, each drawer240includes one or more cache clusters214that are utilized for persisting cache lines when evicted from a cache within the cluster214. The illustrative example shows one configuration of the cache clusters214; however, in one or more embodiments, the clusters214can include any number of L2 caches in any type of configuration including across drawer L2 caches in a group/cluster. In one or more embodiments of the invention, wherein the data in the cache is arranged into congruence classes that contain a plurality of cache lines, and said congruence class contains a chronology vector used to determine which entry to evict, cache evictions occur using an adaptive LRU replacement policy. In the absence of an empty compartment for install on a local processor fetch miss, the replacement policy looks to evict a cache line from that L2 cache associated with the processor that is least recently used based on the chronology vector. A target L2 cache can be identified by examining the utilization of the target L2 cache with respect to the processing cores using the target L2 cache and any other metrics for the target L2 cache. The target L2 cache can be selected from among the L2 caches within the cluster214by having the lowest utilization of any L2 cache within the cluster of caches214. The utilization of the cache can be based on a number of factors including, but not limited, total cache accesses within a pre-defined time period, frequency of cache eviction and/or writes, time periods between cache accesses, evictions, and/or writes, the number of lateral persistent cache lines installed within the cache, invalidations from local/remote cores, and the like (these factors may be referred to as a saturation metric). The method to pick the lowest utilized cache can be implemented as the least within the group of counters tracking the activity per cache or it can be implemented as an LRU policy to determine the last used cache within a time window In one or more embodiments of the invention, when a cache line is first evicted to a lateral cache within a cluster of caches, the LP bit can be set to 1 which indicates that the cache line has been evicted from the first cache to the target cache in the cluster of caches that correspond to primary/first scope of persistence. When the same cache line is evicted from the target cache to a new target cache in the next scope of persistence (i.e., secondary castout (SCO)), the LP bit will be set to 2 and so on. When the same cache line is evicted from a target cache, the replacement policy can look to other clusters of caches to write the cache line using the same cache utilization determination within the new cluster of caches. The new cluster of caches can be within the same drawer240-0or in other drawers240-1,240-2,240-3depending on the way the caches are virtually identified/defined as clusters/scopes. In one or more embodiments of the invention, if the cache line is fetched by a processing core204, the cache line is written to the fetching core's L2 cache and the LP bit can be reset to 0. In one or more embodiments of the invention, the lateral persistence and replacement policy can be implemented using the cache controller212to manage cache evictions amongst the clusters of caches214and evictions to main memory220. The cache controller212can be local within a drawer240or may be a distributed element within an instance per cluster of caches.

In one or more embodiments of the invention, the replacement policy can be preferential for lateral caches208on a CP chip202. A CP chip202can have more than one defined cluster of caches214as there are eight on the CP chip. The replacement policy can first look to evict cache lines to L2 caches208local to a CP chip202prior to searching for other L2 caches that may be on other CP chips202. For example, consider three cache clusters214where a first cache cluster/primary scope and a second cache cluster/secondary scope exists on a first CP chip and a third cache cluster/tertiary scope is on a second CP chip. The replacement policy can look at utilization rates for the L2 caches within the first cache cluster which includes the cache that is evicting the cache line. This can be defined as the first scope of persistence. The first scope of persistence looks within the first cache cluster where the evicting cache exists. A second scope of persistence can be defined as any other group (e.g., the second cache cluster) that is on the CP chip where the evicting cache does not reside, but may not include the entire system. The third scope of persistence can look to groups on other CP chips within the drawer. The utilization of each L2 cache208within a cache cluster214can be analyzed for determining the target cache to persist the cache eviction. On a further eviction of the same cache line from the target cache on primary cluster, the replacement policy then tries to pick a cache from the secondary cluster for the castout to persist using the same prior utilization analysis. On the following castout from the last scope, the line would be written to memory if changed or else just dropped. In the absence of an empty compartment in the target cache, a persistence install might cause a castout in the target lateral cache (cascading castout), where the cascading castout is sent for persistence in the following scope until an empty compartment is available at the next scope or the chain of castouts reaches the last scope of persistence. The processor can decide to bypass all the cascading castouts to memory under certain utilization thresholds or contention in the system Several utilization thresholds can be used for determining whether to keep the cache eviction within a certain level of scope. For example, if the utilization rate for the caches in the first cache cluster is higher than a first threshold, then the replacement policy looks to the second cache cluster on the same CP chip for evicting the cache line. If the utilization rate of the L2 caches in the second cache cluster is also higher than the first threshold utilization rate, then the replacement policy looks to the third cache cluster on a different CP chip and so on and so forth.

In one or more embodiments of the invention, the replacement policy executed by the cache controller212can determine a target cache for an evicted cache line by keeping a counter (“saturation counter”) for each cache in the system200. The counter can track a saturation metric for each cache208in the system200. Initially, cache lines can be persisted by searching for target caches within the home cache cluster214of the cache line being evicted. The counter for each cache208can be used to track saturation metrics of the cache. This saturation metric (i.e., utilization) can include the number of installs in a cache from the core/cores attached to it (fetch misses), the number of installs of cast-outs from lateral caches (peer cache), etc. where the counter increments per install event. This counter provides a metric for the combined activity of the cores attached to the caches and the cast-outs the cache has received from peer lateral caches. In the event of a cache eviction from a cache, the cache line is sent to persist in a lateral cache with the lowest saturation counter value or a lateral cache with a saturation counter value less than the first cache doing the eviction or broadcast to a group of less active caches so that the less busy cache (at the time of eviction) accepts the cache line.

In one or more embodiments of the invention, the replacement policy determines a target cache for a cache eviction based on the LP bits for the cache line being evicted and the utilization of the lateral caches. Once a target cache is determined, the replacement policy further is utilized to determine where to place the cache line within the target cache.FIG.2depicts a block diagram of an exemplary target cache according to one or more embodiments of the invention. The exemplary target cache200is an 8-way cache which can store 8 cache lines. The exemplary cache200utilizes an adaptive least recently used (LRU) algorithm for managing the cache lines within the cache200. LRU is a cache replacement algorithm that discards the least recently used cache line first whenever there is a need to write to the cache200. The LRU algorithm supports multiple install positions including MRU, Mid-LRU, quarter-LRU, LRU and any partial install position in-between. Also, the LP tag bits can be used to discern the lines installed directly by the local processor versus the lateral castouts by peer caches from any scope. Scanning a given congruence class gives a gauge for activity distribution between the core/cores attached to the cache200and the castouts it has received from the lateral caches. At the time of install, all the castouts persisted from lateral caches get a partial placement in the LRU tree initially. All the lines installed by local processor fetches would get an MRU placement. Once the percentage of lines installed by lateral castouts crosses a threshold of total capacity of the congruence class, the newly persisted entries get a larger partial/MRU placement. The larger partial and partial placements can be configured based on the workload needs. This adaptive LRU placement policy dynamically accommodates the caches to contain more local installs and locally re-referenced lines when the local processor is active and more persisted entries when the local processor is dormant. For example, if the minimum capacity threshold for persisted entries in a cache was set to 50%, the persisted entries would get partial placement until the number of persisted entries (including the current install102) in the congruence class are less than 50% of congruence class capacity. Thereafter, they get a larger partial/MRU placement. In the illustrated example, with threshold set to 75%, the current install cache line102is a persisted install (LP greater than 0), and the total persisted installs are 4. So line102would still get a partial MRU placement. Once the persisted installs are 6, the about to be persisted install would get an MRU placement.

In one or more embodiments of the invention, the determined utilization rate of a target cache can dictate how a cache line is installed and how many peer cache lines can be installed within the target cache. For example, if the target cache has a very low utilization rate (e.g., is less than a pre-defined threshold), then the target cache can have most, if not all, lateral cache lines installed within the target cache. Multiple threshold utilization rates can be defined which dictate how many peer cache lines can be installed. The number of cache lines can be defined by a percentage of the memory available (50%, 75%, etc. of the cache memory) or a number.

In one or more embodiments of the invention, cache clusters214can be defined using a variety of means such as, for example, selecting a number of caches within a CP chip202, selecting a number of caches within a drawer240, and/or selecting a number of caches across drawers240. Defining the cache clusters in the system can be done based on the locality of peer caches like taking the data sourcing latency into effect and/or workload dispatch patterns and/or OS/software directive hints. Scopes/cache clusters can be changed over time based on hypervisor hints and/or processor types attached to a cache and/or including the directives mentioned above. Also, not all clusters have the same number of L2 caches.

FIG.3depicts a flow diagram of a method300for lateral cache persistence according to one or more embodiments of the invention. At least a portion of the method300can be executed, for example, by the processor601shown inFIG.6. The method300includes defining scopes and/or clusters for a plurality of caches in a symmetrical multiprocessing (SMP) system, as shown in block302. This includes having a data processing system including several processor units, wherein each processor unit contains a processor with an associated upper and lower-level cache (L2), coupled together by an interconnect fabric. The data in the cache is arranged into congruence classes that contain a number of cache lines, and theses congruence classes also include a chronology vector used to determine which entry to evict. The chronology vector (age bit) tracks the age of the cache line in the cache. The clusters of caches are arranged into a plurality of scope domains, called primary, secondary, and tertiary, which can be extended into an infinite number of unique scopes. In the event of a cache eviction and a cache has been determined to be evicted, the processing cache determines if the entry should be laterally castout (LCO) to a peer cache within a primary castout scope (PCO), a secondary castout scope (SCO), or written back to memory as a tertiary castout (TCO). At block304, the method300includes defining both a methodology and a metric to track the activity of the caches in the system. Upon determining which cache line to evict, the processing cache determines if the entry should be laterally castout (LCO) to a peer cache within a primary castout scope (PCO), a secondary castout scope (SCO), written back to memory as a tertiary castout (TCO). Within each of the target scope, the activity of the caches are tracked using a saturation counter that tracks the number of installs as defined by processor misses into each cache. At block306, the method300includes defining a threshold for the persisted entries capacity within a congruence class. Installed cache lines for a given cache can be tracked by various requester types such, for example, a local processor fetch versus a lateral castout from another cache. The install position of a cache line can be based on the percentage of lines installed by processor fetches versus lateral castouts. When the cache line is installed in the cache on a lateral castout, the cache line is placed in a non-MRU (most recently used) position initially. Once the percentage of cache lines installed by lateral castouts crosses a pre-defined threshold of the total capacity of the congruence class, the persisted cache entries get a larger partial/MRU placement. At block308, the method300includes receiving a request to evict a cache line (LCO) having lateral persistence bits tracking the current scope of persistence for the cache line. The current scope of a cache line is determined using the lateral persistence tag bits which are set to zero when the line is installed or re-referenced by a processor and incremented every time a line is evicted from a current cache and persisted in any of the caches at the next scope.

In one or more embodiments of the invention, the method300, at block310, includes determining a target cache for writing the LCO where the target cache is among the higher scope of persistence than the current scope. The current scope is determined based on the activity of the caches using counters that track the number of installs as defined by processor misses into each cache and least active cache is picked as a target to persist the castout. The castout can be sent to a group of less active caches. The counters track the number of invalidations from local and/or remote cores, the number of lateral castout installs, and the number of total castouts (as defined by local evictions and/or invalidations from local/remote cores and/or peer cache evictions). The counters can be implemented as an LRU tree algorithm, for example. In one or more embodiments of the invention, the method300includes decision block312which includes determining if the target cache has no empty compartments for an install and then determining the cascading castout methodology for making space for the LCO install. That is to say, the evicted entry being sent for persisting might cause a castout in the target lateral cache in the absence of an empty compartment. In this case, a cascading castout is sent for persistence in the following group until an empty compartment is available at the next scope and/or the chain of castouts reaches the last scope of persistence. In that case, if the replacement algorithm decides the system is under contention/busy, the cascading castouts are bypassed to main memory. Once a target cache is determined with or without cascading and the cache line is not written to memory, the method300includes writing the LCO to the target cache and setting the LP tag bits to the target cache's scope, as shown in block314. And at block316, the method300includes scanning the congruence class of the target cache for the number of persisted entries and based on the threshold, place the LCO in the target cache in the respective partial/larger partial MRU position. The chronology vector includes a cache replacement algorithm that supports multiple install positions including MRU, Mid-LRU, LRU, and any partial install position in-between. As the percentage of lines installed in lateral castouts crosses a threshold of the capacity of the congruence class, the persisted entries get a larger partial/MRU placement.

FIG.4depicts a flow diagram of a method400for lateral cache persistence according to one or more embodiments of the invention. At least a portion of the method400can be executed, for example, by the processor601shown inFIG.6. The method400includes defining one or more processor units having a plurality of caches, wherein each processor unit comprises a processor having at least one cache from the plurality of caches, and wherein each of the one or more processor units are coupled together by an interconnect fabric, as shown in block402. At block404, the method400includes for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class in the one or more congruence classes comprises a chronology vector. Then, the method400includes arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, as shown at block406. Also, at block408, the method400includes determining a first cache line to evict based on the chronology vector for the first cache line. And, at block410, the method400includes determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

FIG.5depicts a flow diagram of a method500for lateral cache persistence according to one or more embodiments of the invention. At least a portion of the method500can be executed, for example, by the processor601shown inFIG.6. The method500includes receiving a request to evict a first cache line from a first cache on a first microprocessor chip in a plurality of microprocessor chips in a processing drawer, the first cache line having a first set of lateral persistence bits tracking a scope for the first cache line, as shown at block502. At block504, the method500includes determining the scope of the first cache line. Also, the method500, at block506, includes identifying a target cache having a saturation metric, wherein the target cache comprises a higher scope than the scope of the first cache line. And at block508, the method500includes determining an action for the first cache line based on the saturation metric for the target cache and the scope of the first cache line.

As shown inFIG.6, the computer system600has one or more central processing units (CPU(s))601a,601b,601c, etc. (collectively or generically referred to as processor(s)601). The processors601can be a single-core processor, multi-core processor, computing cluster, or any number of other configurations. The processors601, also referred to as processing circuits, are coupled via a system bus602to a system memory603and various other components. The system memory603can include a read only memory (ROM)604and a random access memory (RAM)605. The ROM604is coupled to the system bus602and may include a basic input/output system (BIOS), which controls certain basic functions of the computer system600. The RAM is read-write memory coupled to the system bus602for use by the processors601. The system memory603provides temporary memory space for operations of said instructions during operation. The system memory603can include random access memory (RAM), read only memory, flash memory, or any other suitable memory systems.

The computer system600comprises an input/output (I/O) adapter606and a communications adapter607coupled to the system bus602. The I/O adapter606may be a small computer system interface (SCSI) adapter that communicates with a hard disk608and/or any other similar component. The I/O adapter606and the hard disk608are collectively referred to herein as a mass storage610.

Software611for execution on the computer system600may be stored in the mass storage610. The mass storage610is an example of a tangible storage medium readable by the processors601, where the software611is stored as instructions for execution by the processors601to cause the computer system600to operate, such as is described herein below with respect to the various Figures. Examples of computer program product and the execution of such instruction is discussed herein in more detail. The communications adapter607interconnects the system bus602with a network612, which may be an outside network, enabling the computer system600to communicate with other such systems. In one embodiment, a portion of the system memory603and the mass storage610collectively store an operating system, which may be any appropriate operating system, such as the z/OS or AIX operating system from IBM Corporation, to coordinate the functions of the various components shown inFIG.6.

Additional input/output devices are shown as connected to the system bus602via a display adapter615and an interface adapter616and. In one embodiment, the adapters606,607,615, and616may be connected to one or more I/O buses that are connected to the system bus602via an intermediate bus bridge (not shown). A display619(e.g., a screen or a display monitor) is connected to the system bus602by a display adapter615, which may include a graphics controller to improve the performance of graphics intensive applications and a video controller. A keyboard621, a mouse622, a speaker623, etc. can be interconnected to the system bus602via the interface adapter616, which may include, for example, a Super I/O chip integrating multiple device adapters into a single integrated circuit. Suitable I/O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols, such as the Peripheral Component Interconnect (PCI). Thus, as configured inFIG.6, the computer system600includes processing capability in the form of the processors601, and, storage capability including the system memory603and the mass storage610, input means such as the keyboard621and the mouse622, and output capability including the speaker623and the display619.

In some embodiments, the communications adapter607can transmit data using any suitable interface or protocol, such as the internet small computer system interface, among others. The network612may be a cellular network, a radio network, a wide area network (WAN), a local area network (LAN), or the Internet, among others. An external computing device may connect to the computer system600through the network612. In some examples, an external computing device may be an external webserver or a cloud computing node.

It is to be understood that the block diagram ofFIG.6is not intended to indicate that the computer system600is to include all of the components shown inFIG.6. Rather, the computer system600can include any appropriate fewer or additional components not illustrated inFIG.6(e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Further, the embodiments described herein with respect to computer system600may be implemented with any appropriate logic, wherein the logic, as referred to herein, can include any suitable hardware (e.g., a processor, an embedded controller, or an application specific integrated circuit, among others), software (e.g., an application, among others), firmware, or any suitable combination of hardware, software, and firmware, in various embodiments.