Semiconductor wafer with test key structure

A semiconductor wafer with a test key structure is provided. The semiconductor wafer includes a semiconductor substrate including a scribe line region, a chip region, and a seal ring region between the scribe line region and the chip region. A test pad structure and a test element are disposed over the semiconductor substrate corresponding to the scribe line region. A conductive line is disposed over the semiconductor substrate corresponding to the seal ring region, and has two ends extending to the scribe line region and electrically connected between the test pad structure and the test element.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan Patent Application No. 106143332, filed on Dec. 11, 2017, the entirety of which is incorporated by reference herein.

BACKGROUND

Field of the Disclosure

The disclosure relates to a semiconductor wafer, and in particular to a semiconductor wafer with a test key structure that is capable of increasing the available area of the semiconductor wafer.

Description of the Related Art

Generally speaking, test key structures are disposed in the scribe line regions. A test key structure includes test pads and test elements, and is fabricated simultaneously with the formation of actual or functional devices in the semiconductor chips. As a result, the quality of the actual or functional devices can be checked by electrically connecting the test probes to the test pads of a test key structure.

However, with the development of complicated circuits on the semiconductor chips, more test pads and more test elements are required on the scribe line regions, and thus each of the scribe line regions may get broader.

SUMMARY

An exemplary embodiment of a semiconductor wafer with a test key structure is provided. The semiconductor wafer includes a semiconductor substrate including a scribe line region, a chip region, and a seal ring region between the scribe line region and the chip region. A first test pad structure and a first test element are disposed over the semiconductor substrate corresponding to the scribe line region. A first conductive line is disposed over the semiconductor substrate corresponding to the seal ring region, and has two ends extending to the scribe line region and electrically connected between the first test pad structure and the first test element.

Another exemplary embodiment of a semiconductor wafer with a test key structure is provided. The semiconductor wafer includes a semiconductor substrate including a first seal ring region, a second seal ring region, and a scribe line region between the first seal ring region and the second seal ring region. A first test pad structure, a second test pad structure, a first test element, and a second test element are disposed over the semiconductor substrate corresponding to the scribe line region. A first conductive line is disposed over the semiconductor substrate corresponding to the first seal ring region, and has two ends extending to the scribe line region and electrically connected between the first test pad structure and the first test element. A second conductive line is disposed over the semiconductor substrate corresponding to the second seal ring region, and has two ends extending to the scribe line region and electrically connected between the second test pad structure and the second test element.

Yet another exemplary embodiment of a semiconductor wafer with a test key structure is provided. The semiconductor wafer includes a semiconductor substrate including a first scribe line region, a second scribe line region perpendicular to the first scribe line region, and a seal ring region between the first scribe line region and the second scribe line region. A first test pad structure and a first test element are disposed over the semiconductor substrate corresponding to the first scribe line region. A second test pad structure and a second test element are disposed over the semiconductor substrate corresponding to the second scribe line region. A first conductive line is disposed over the semiconductor substrate corresponding to the seal ring region, and has two ends respectively extending to the first scribe line region and the second scribe line region, and electrically connected between the first test element and the second test pad structure. A second conductive line is disposed over the semiconductor substrate corresponding to the seal ring region, and has two ends respectively extending to the first scribe line region and the second scribe line region, and electrically connected between the first test pad structure and the second test element.

DETAILED DESCRIPTION

The embodiments provide a semiconductor wafer with a test key structure. The semiconductor wafer employs the seal ring region between the scribe line region and the chip region for placement of the trace route of the test key structure, thereby effectively reducing the width of the scribe line region. Moreover, by forming openings in the test pad of the test key structure, the stress generated by performing dicing process and the area of the test pad are reduced.

Refer toFIGS. 1, 2, and 3, in whichFIG. 1is a plan view of a portion of a semiconductor wafer10with a test key structure according to some embodiments of the present invention,FIG. 2is a cross-sectional view taken along the line2-2′ inFIG. 1. In some embodiments, andFIG. 3is a cross-sectional view taken along the line3-3′ inFIG. 1. In some embodiments, the semiconductor wafer10with a test key structure includes a semiconductor substrate105, such as a silicon substrate, a SiGe substrate, a bulk semiconductor substrate, a compound semiconductor substrate, a silicon-on-insulator (SOI) substrate, or another well-known semiconductor substrate. The semiconductor substrate105includes at least one scribe line region101, at least one chip region103, and a seal ring region102therebetween. In some embodiment, the seal ring region102surrounds the chip region103. Moreover, the semiconductor substrate105corresponding to the seal ring region102has an isolation structure (such as a shallow trench isolation structure) therein, as shown inFIGS. 2 and 3. The isolation structure also surrounds the chip region103.

In some embodiments, the semiconductor wafer10with a test key structure further includes test pad structures and test elements disposed in a dielectric layer108over the semiconductor substrate105, as shown inFIGS. 2 and 3, and located at the scribe line region101. The dielectric layer108may include borosilicate glass (BSG), phosphosilicate glass (PSG), boron-doped phosphosilicate Glass (BPSG), fluoride-doped silicate glass (FSG), a low-k dielectric material, another porous dielectric material, or a combination thereof. In some embodiments, and may be formed by a chemical vapor deposition (CVD) process, a spin-on process, or a combination thereof.

It should be understood that the number of those test pad structures and test elements is based on the design demands. Herein, in order to simplify the diagram, only four test pad structures110a,110b,110c, and110dand two test elements120aand120bare depicted. In some embodiments, from a top-view perspective, the test pad structures110a,110b,110c, and110dand the test elements120aand120bare arranged along a central line (not shown). As shown inFIGS. 2 and 3, the test pad structures110a,110b,110c, and110dmay be formed by multi-metal layer structures. It should be understood that the number of metal layers and the number of conductive plugs in the multi-metal layer structure are based on the design demands and are not limited to the embodiments shown inFIGS. 2 and 3. For example, the test pad structures110a,110b,110c, and110drespectively include metal layers in different levels of the dielectric layer108and conductive plugs connected between the metal layers. The uppermost metal layer in the stack of the metal layers may serve as a test pad110for contacting a test probe head (not shown).

Refer to shown inFIG. 4, which illustrates a plan view of the test pad110according to some embodiments of the present invention. In some embodiments, the test pad110and the underlying metal layers are non-solid and include openings arranged in different lines. For example, the test pad110includes openings111arranged in a line111a, openings113arranged in a line113a, and openings115arranged in a line115a, in which those lines111,113, and115are parallel to each other and parallel to an extending direction of the scribe line region101.

In some embodiments, the openings113are shifted with respect to the openings111and115along a direction that is parallel to the line113a, so that each of the openings113overlaps two openings111and two openings115as viewed from a direction perpendicular to the lines111a,113a, and115a. Moreover, in some embodiments, the openings111,113, and115are rectangular-shaped and have a width W that is less than half of the maximum width of the contact area (not shown) between the test pad110and the test probe head. As a result, it can be ensured that the test probe head is capable of contacting the solid portion of the test pad111, so as to prevent failure during testing. Moreover, the openings111,113, and115are filled with the dielectric layer108and therefore the stress generated by the dicing process can be mitigated, so as to prevent cracks from extending into the seal ring region102and the chip region103. Additionally, when the width of the scribe line region101is reduced for reduction of the size of the test pad structures110a,110b,110c, and110d, the speed of dicing the semiconductor wafer10can be increased by the use of the test pad111with openings111,113, and115compared to the use of a solid test pad.

It should be understood that the number of openings in the test pad111is based on the size of the test pad111and is not limited to the embodiment shown inFIG. 4.

In some embodiments, the test elements120aand120b(such as transistors, diodes, resistors, capacitors, or an element parameter-extraction module) are electrically connected to the test pad structures110a,110b,110c, and110dvia traces. For example, the test element120ais electrically connected to the test pad structures110aand110b, and the test element120bis electrically connected to the test pad structures110cand110d.

In some embodiments, the semiconductor wafer10with a test key structure further includes at least two conductive lines125aand125bdisposed in the dielectric layer108over the semiconductor substrate105corresponding to the seal ring region102. Those conductive lines125aand125bserve as the traces between the test elements120aand120band the test pad structures110a,110b,110c, and110d. For example, two ends of the conductive line125aextend to the scribe line region101from the seal ring region102, and electrically connected between the test pad structure110aand the test element120a. Moreover, two ends of the conductive line125bextend to the scribe line region101from the seal ring region102, and electrically connected between the test pad structure110cand the test element120b. In some embodiments, the conductive lines125aand125bmay be located in the same level of the dielectric layer108. Alternatively, the conductive lines125aand125bmay be located in the different levels of the dielectric layer108. In those cases, the conductive line125amay be interlaced with the conductive line125b. In some embodiments, the conductive lines125aand125bmay be replaced by the metal layers located in the different levels of the dielectric layer108and the conductive plugs that connect these metal layers.

In some embodiments, the semiconductor wafer10with a test key structure further includes two seal ring structures130and140disposed in the dielectric layer108over the semiconductor substrate105corresponding to the seal ring region102. In some embodiments, the seal ring structure130surrounds the seal ring structure140and the seal ring structure140surrounds the chip region103. The seal ring structure140typically has a width greater than that of the seal ring structure130. The seal ring structures130and140are formed of multi-metal layer structures, as shown inFIG. 3, and are used for protection of integrated circuits104in the chip region103. In some embodiments, the integrated circuits104include memory arrays, peripheral driving circuits, or control circuits.

In some embodiments, the conductive lines125aand125bmay be between the seal ring structures130and140. Unlike the seal ring structure140having a continuous ring structure, the seal ring structure130may include gaps130ato form a non-continuous ring structure. Two ends of the conductive line125arespectively pass through the gaps130ato extend to the scribe line region101, so as to respectively and electrically connect the test pad structure110aand the test element120a. Similarly, two ends of the conductive line125brespectively pass through the gaps130ato extend to the scribe line region101, so as to respectively and electrically connect the test pad structure110cand the test element120b.

Refer toFIG. 5, which illustrates a plan view of a portion of a semiconductor wafer20with a test key structure according to some embodiments of the present invention. Elements inFIG. 5that are the same as those inFIG. 1are labeled with the same reference numbers as inFIG. 1and may not be described again for brevity. As shown inFIG. 5, the semiconductor wafer20is similar to the semiconductor wafer10shown inFIG. 1. In some embodiments, the semiconductor wafer20with a test key structure includes a semiconductor substrate105. The semiconductor substrate105may include a scribe line region101, seal ring regions102and202, and chip regions103and203. The scribe line region101may be interposed between the seal ring regions102and202. Moreover, the seal ring region102surrounds the chip region103and the seal ring region202surrounds the chip region203.

In some embodiments, the semiconductor wafer20with a test key structure further includes test elements120aand120b. Unlike the test key structure of the semiconductor wafer10shown inFIG. 1, the test element120ais electrically connected to the test pad structures110aand110cand the test element120bis electrically connected to the test pad structures110band110d.

Compared to the semiconductor wafer10with a test key structure, the semiconductor wafer20with a test key structure further includes a conductive line225a. The conductive line225amay be disposed in the dielectric layer108over the semiconductor substrate105corresponding to the seal ring region202. In some embodiments, two ends of the conductive line225aextend to the scribe line region101from the seal ring region202, and electrically connected between the test pad structure110band the test element120b. In some embodiments, the conductive lines125aand225aare located in the same level of the dielectric layer108. In some other embodiments, the conductive lines125aand225aare located in the different levels of the dielectric layer108. In some embodiments, the conductive lines125aand225amay be replaced by the metal layers located in the different levels of the dielectric layer108and the conductive plugs that connect these metal layers.

In some embodiments, compared to the semiconductor wafer10with a test key structure, the semiconductor wafer20with a test key structure further includes seal ring structures230and240disposed in the dielectric layer108over the semiconductor substrate105corresponding to the seal ring region202. In some embodiments, the seal ring structure230surrounds the seal ring structure240and the seal ring structure240surrounds the chip region203. The seal ring structure240typically has a width greater than that of the seal ring structure230. The seal ring structures230and240are formed of multi-metal layer structures, and are used for protection of integrated circuits204in the chip region203. In some embodiments, the integrated circuits204include memory arrays, peripheral driving circuits, or control circuits.

In some embodiments, the conductive line225amay be between the seal ring structures230and240. Unlike the seal ring structures140and240having a continuous ring structure, the seal ring structure130may include two gaps130ato form a non-continuous ring structure. Moreover, the seal ring structure230may include two gaps230ato form a non-continuous ring structure. Two ends of the conductive line125arespectively pass through the gaps130ato extend to the scribe line region101, so as to be electrically connected between the test pad structure110aand the test element120a. Similarly, two ends of the conductive line225arespectively pass through the gaps230ato extend to the scribe line region101, so as to be electrically connected between the test pad structure110band the test element120b.

Refer toFIG. 6, which illustrates a plan view of a portion of a semiconductor wafer30with a test key structure according to some embodiments of the present invention. In some embodiments, the semiconductor wafer30includes a semiconductor substrate305. The material and the structure of the semiconductor substrate305are the same as or similar to those of the semiconductor substrate105shown inFIG. 1. The semiconductor substrate305may include two scribe line regions301aand301b, a seal ring region302adjacent to the scribe line regions301aand301b, and a chip region303adjacent to the seal ring region302. In some embodiments, the scribe line region301amay be perpendicular to the scribe line region301b. Moreover, the seal ring region302is between the two scribe line regions301aand301band the chip region303and surrounds the chip region303.

In some embodiments, the semiconductor wafer30with a test key structure further includes test pad structures and test elements disposed in the dielectric layer303over the semiconductor substrate305corresponding to the scribe line regions301aand301b. The material and the structure of the dielectric layer308may be the same as or similar to those of the dielectric layer108shown inFIGS. 1 to 3.

Herein, in order to simplify the diagram, only four test pad structures310a,310b,310c, and310dand a test element320ain the scribe line region301a, and three test pad structures310e,310f, and310gand a test element320bin the scribe line region301bare depicted. In some embodiments, the material and the structure of the test pad structures310ato310gmay be the same as or similar to the test pad structures110ato110dshown inFIGS. 1 to 3, and the material and the structure of the test elements320aand320bmay be the same as or similar to the test elements120aand120bshown inFIG. 1. Similarly, the test pad structures310ato310grespectively include metal layers in different levels of the dielectric layer308and conductive plugs connected between the metal layers. The uppermost metal layer in the stack of the metal layers may serve as a test pad310for contacting a test probe head (not shown). In some embodiments, the structure of the test pad310may be the same as that of the test pad110shown inFIG. 4.

In some embodiments, the test elements320aand320bare electrically connected to the test pad structures310b,310c,310d,310f, and310gby traces. For example, the test element320amay be electrically connected to the test pad structures310b,310c, and310f, and the test element320bmay be electrically connected to the test pad structures310dand310g.

In some embodiments, the semiconductor wafer30with a test key structure further includes at least two conductive lines325aand325bdisposed in the dielectric layer308over the semiconductor substrate305corresponding to the seal ring region302. Those conductive lines325aand325bserve as the traces between the test elements320aand320band the test pad structures310ato310g. For example, two ends of the conductive line325aextend to the scribe line region301from the seal ring region302, and electrically connected between the test pad structure310aand the test element320f. Moreover, two ends of the conductive line325bextend to the scribe line region301from the seal ring region302, and electrically connected between the test pad structure310dand the test element320b. In some embodiments, the conductive lines325aand325bmay be located in the different levels of the dielectric layer308. In those cases, the conductive line325amay be interlaced with the conductive line325b, as shown inFIG. 6. In some other embodiments, the conductive lines325aand325bmay be located in the same level of the dielectric layer308. In some embodiments, the conductive lines325aand325bmay be replaced by the metal layers located in the different levels of the dielectric layer308and the conductive plugs that connect these metal layers.

In some embodiments, the semiconductor wafer30with a test key structure further includes two seal ring structures330and340disposed in the dielectric layer308over the semiconductor substrate305corresponding to the seal ring region302. In some embodiments, the seal ring structure330surrounds the seal ring structure340and the seal ring structure340surrounds the chip region303. The seal ring structure340typically has a width greater than that of the seal ring structure330. The material and the structure of the seal ring structures330and340are respectively the same as or similar to those of the seal ring structures130and140shown inFIG. 3, and are used for protection of integrated circuits304in the chip region303. In some embodiments, the integrated circuits304include memory arrays, peripheral driving circuits, or control circuits.

In some embodiments, the conductive lines325aand325bmay be between the seal ring structures330and340. Unlike the seal ring structure340having a continuous ring structure, the seal ring structure330may include gaps to form a non-continuous ring structure. For example, the seal ring structure330may include two gaps330arespectively corresponding to the scribe line region310aand the scribe line region310band two gaps330brespectively corresponding to the scribe line region310aand the scribe line region310b. Two ends of the conductive line325arespectively pass through the gaps330ato extend to the scribe line region301band the scribe line region301a, so as to respectively and electrically connect the test pad structure310fand the test element320a. Similarly, two ends of the conductive line325brespectively pass through the gaps330bto extend to the scribe line region301aand the scribe line region301b, so as to respectively and electrically connect the test pad structure310dand the test element320b.

According to the foregoing embodiments, the traces that are used for the test key structure are disposed in the seal ring region between the scribe line region and the chip region. Moreover, the size of the test pad of the test key structure is reduced. Therefore, the design flexibility of those traces can be increased and the width of the scribe line region can be effectively reduced. For example, the distance from two opposite edges of the test pad to the edge of the corresponding scribe line region can be reduced to about 1 μm. As a result, the available area on the wafer can be increased, thereby increasing the gross die per wafer.