Reduced floating body effect without impact on performance-enhancing stress

A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.

BACKGROUND

1. Technical Field

The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to reducing floating body effect in a gated device without impacting performance enhancing stress.

2. Background Art

Stress induced device performance enhancement by embedded silicon germanium (e-SiGe) and embedded carbon doped silicon (e-SiC) are used in new silicon-on-insulator (SOI) IC technology nodes, e.g., 45 nm and 32 nm. In these technologies, source/drain (S/D) diodes are made leaky such that a reverse bias at the drain tends to pull the body voltage toward the drain voltage, the body while the leaky forward bias at the source tends to pull the body toward the source voltage, thus achieving body equilibrium. The above-described technique reduces the floating body effect (FBE). Currently, one method by which S/D diodes are made leaky is by implanting species such as xenon (Xe) during S/D implantation and creating crystalline defects in the depletion region by S/D activation anneal. This implant and anneal process tends to relax the stress created to enhance the device performance achieved by the use of strained materials.

SUMMARY

A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.

A first aspect of the disclosure provides a method comprising: forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.

A second aspect of the disclosure provides a gated device comprising: a gate over a substrate; and a source/drain region and a channel region in the substrate, the source/drain region including a stress inducing material; wherein the substrate includes a damaged portion in or near the channel region to create a leakage current, and wherein the damaged portion does not extend into the stress inducing source/drain region.

A third aspect of the disclosure provides a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a gated device comprising: a gate over a substrate; and a source/drain region and a channel region in the substrate, the source/drain region including a stress inducing material; wherein the substrate includes a damaged portion in or near the channel region to create a leakage current, and wherein the damaged portion does not extend into the stress inducing source/drain region.

DETAILED DESCRIPTION

FIGS. 1-7show embodiments of a method according to the disclosure, withFIGS. 6 and 7showing embodiments of a gated device170,172, respectively, according to the disclosure.FIG. 1shows an initial structure100after trench isolation101formation in a semiconductor-on-insulator (SOI) substrate102(layer below buried insulator (BOX) layer omitted for clarity). Trench isolations101may be in the form of shallow trench isolations (STI) and may include silicon dioxide (SiO2). SOI layer104of SOI substrate102may include silicon, germanium, silicon germanium, silicon carbide, and those materials consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable materials for SOI layer104of substrate102include II-VI compound semiconductors having a composition ZnA1CdA2SeB1TeB2, where A1, A2, B1, and B2are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Furthermore, a portion of, or the entire SOI layer104may be strained.

Structure100also includes well implants (not shown) and a gate110. Gate110may include any now known or later developed structure such as a high dielectric constant (high-k) gate dielectric112, a gate conductor114(e.g., metal114and in-situ doped polysilicon116), gate capping layer117and spacer(s).

FIG. 2shows formation of damage120in a portion of substrate102(i.e., SOI layer104) adjacent to gate110. In one embodiment, this process includes implanting a species and annealing. The species may include xenon (Xe), silicon (Si), germanium (Ge), nitrogen (N), oxygen (O), carbon (C) or a combination thereof. The implant, as shown inFIG. 2, may include a dual directional damage inducing implant as well as Halo implant, forming symmetrical damaged portions120and halo doping area (not shown) about gate110. The dopant type of halo implant is same as SOI layer (body)104dopant and the halo doping improves the short channel effect of the device. In an alternative embodiment, as shown inFIG. 3, the implants may include single-directional implants, forming asymmetrical damaged portions122and halo doping area (not shown) about gate110. In either embodiment, annealing will re-crystallize the SOI layer104above damaged portions120,122.

FIG. 4shows a dual-directional source/drain extension126implant for the symmetrical embodiment ofFIG. 2. The doping type of the source/drain extension126is the opposite type of body and halo dopant. For NFET, the dopant is n-type dopant such as As and P, while for PFET the dopant is p-type dopant such B.

FIG. 5shows removing a portion130of damaged portion120(and source/drain extension126) to form a trench132, e.g., by directional reactive ion etching (RIE) with a new spacer133, leaving another portion134of damaged portion120(halo area and extension area126) at least adjacent to channel region140(in SOI layer104(FIG. 4).FIG. 5is shown relative to the symmetrical embodiment ofFIG. 2; however, those with skill in the art will recognize that it is equally applicable to the asymmetrical embodiment ofFIG. 3.

FIG. 6shows substantially filling trench132with a material150to form a source/drain region160. In one embodiment, the filling process may include performing an in-situ doped epitaxial growth from SOI layer104, resulting in the same material152as SOI layer104for source/drain region160of gate110. For NFET, the dopants are n-type dopant such as As and P and tensile stress inducing dopant of C, while for PFET the dopants are p-type dopant such as B and compressive stress inducing dopant of Ge. Hence, material152may generally include germanium doped silicon, carbon doped silicon or silicon depending on the type of device to be built. This filling process may also include forming a silicide154, e.g. nickel silicide, over material152. The silicide may be formed using any now known or later developed technique, e.g., depositing a metal, annealing, and removing any residual metal. Conventional interlayer contact formation (not shown) may then follow, e.g., deposition of an interlayer dielectric, contact patterning and forming.FIG. 7shows the same processing as inFIG. 6after application to the asymmetrical embodiment ofFIG. 3. In this embodiment, only one damaged portion134and the halo (not shown) remain. In any event, since the damaged portion that generates a leakage current to reduce FBE is formed prior to source/drain region formation, the impact of this formation on performance enhancing stress material152is eliminated.

FIG. 8shows a block diagram of an exemplary design flow900used for example, in semiconductor design, manufacturing, and/or test. Design flow900may vary depending on the type of IC being designed. For example, a design flow900for building an application specific IC (ASIC) may differ from a design flow900for designing a standard component. Design structure920is preferably an input to a design process910and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure920comprises an embodiment of the invention as shown inFIGS. 6or7in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure920may be contained on one or more machine readable medium. For example, design structure920may be a text file or a graphical representation of an embodiment of the invention as shown inFIGS. 6or7. Design process910preferably synthesizes (or translates) an embodiment of the invention as shown inFIGS. 6or7into a netlist980, where netlist980is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. For example, the medium may be a CD, a compact flash, other flash memory, a packet of data to be sent via the Internet, or other networking suitable means. The synthesis may be an iterative process in which netlist980is resynthesized one or more times depending on design specifications and parameters for the circuit.

Design process910may include using a variety of inputs; for example, inputs from library elements930which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications940, characterization data950, verification data960, design rules970, and test data files985(which may include test patterns and other testing information). Design process910may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process910without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.

Design process910preferably translates an embodiment of the invention as shown inFIGS. 6or7, along with any additional integrated circuit design or data (if applicable), into a second design structure990. Design structure990resides on a storage medium in a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design structures). Design structure990may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown inFIGS. 6or7. Design structure990may then proceed to a stage995where, for example, design structure990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.