Zener diode and method for production thereof

A zener diode circuit includes a semiconductor substrate having an N-doped region and a P-doped region that form a PN junction. The N-doped region and the P-doped region have areas with widths that decrease as the N-doped region and the P-doped region approach the PN junction. The zener diode circuit also includes a transistor that provides current to the zener diode, and circuitry that detects a state of the zener diode.

TECHNICAL FIELD

This patent application relates to a Zener diode having a semiconductor substrate having an N-doped region and a P-doped region, and in which the doped regions form a PN junction. This patent application also relates to a circuit including the Zener diode and to a method for manufacturing the Zener diode.

BACKGROUND

Zener diodes are known from publication U.S. Pat. No. 5,990,534, which have a PN junction arranged perpendicularly in a semiconductor substrate. A PN junction of this type has the disadvantage that it cannot be manufactured for integrated circuits using standard manufacturing methods because of varying depths of penetration required. Furthermore, known Zener diodes are not suitable as a PROM component, because their PN junctions have a relatively large surface and accordingly, a higher current would be necessary to burn through the PN junction.

Zener diodes are also known from publication U.S. Pat. No. 4,672,403, in which the PN junction is a lateral junction. The N-region is designed in the form of a point. Such a point makes it possible to concentrate currents flowing through the diode readily, for which reason a low current is required to burn through such a diode. However, such a known diode also has the disadvantage that it cannot be manufactured for integrated circuits using standard manufacturing methods because of varying depths of penetration required.

Zener diodes are used for PROM components. The Zener diode is burned through by an adequately high current or it is also shorted, which gives rise to a resistor instead of the Zener diode. The Zener diodes are loaded in the reverse direction during the burn-though.

Furthermore, known Zener diodes have the disadvantage that the overlap of the P-doped and N-doped region is relatively large, causing leakage currents of the Zener diodes to be high.

SUMMARY

A Zener diode is described herein, which has a semiconductor substrate. Located in the semiconductor substrate are N-doped and P-doped regions. Two of the doped regions form a lateral PN junction. The mutually facing sides of the doped regions have a width that diminishes toward the other doped region.

Such a Zener diode has the advantage that based on the diminishing width, the actual PN junction is relatively small, for which reason such a diode has a low leakage current. Low leakage currents are advantageous because for one thing, they make it possible to reduce the total current consumption of a circuit and, when used as a programmable element, the difference between the programmed state (low resistivity, high flow of current) and the unburned state (high resistivity, very low leakage current) is more distinct and therefore offers increased certainty of differentiation.

Furthermore, such Zener diodes have the advantage that because of the diminishing width of the doped regions, it is possible to concentrate a current flowing through the diode spatially to the junction between the two regions, resulting in an advantageous localization of the thermal energy produced by the current in the component. This makes it possible to use a relatively low current to achieve a burn-through of the diode in order to store data.

The mutually facing ends of the doped regions may have a minimum width. Accordingly, the doped regions have outlines in the form of trapezoids facing one another. These trapezoids originate from triangular regions, where points of triangles facing one another are flattened. Minimum widths at the ends of the doped regions may make it possible that, in the event of an alignment error of the masks used for the production of the doped region, the doped regions may still overlap in contrast to pointed ends of the doped regions, and thus it may still be possible to achieve a functioning PN junction. The minimum widths at the ends of the doped regions also make it possible to compensate for an alignment error in the production of the doped regions.

The ends of the doped regions may, for example, be defined by straight edges.

Furthermore, a Zener diode is described herein, which has an additional P-doped region. A Zener diode may also have an additional N-doped region. The N-doped region is situated between two P-doped regions. However, the P-doped region may also be situated between two N-doped regions. The N-doped region forms a lateral PN junction with each of the adjacent P-doped regions. In the same way, the N-doped region forms a lateral PN junction with each of the adjacent P-doped regions. In such a Zener diode, the two PN junctions may be connected in parallel. To that end, the P-doped regions are connected to a first external terminal and the N-doped regions are connected to a second external terminal. This results in a double Zener diode, which has properties similar to a single Zener diode. In particular, such a double Zener diode may be programmed by a current.

Double Zener diodes have the advantage that it is possible to compensate for alignment errors of masks used for manufacturing the diodes. A doped region lying between the two outer doped regions may migrate between the two outer regions within limits established by the precision of adjustment. It may lie closer to the one or the other of the doped regions. Because the other geometric variables are constant, the sum of the distances between the central doped region and the first outer doped region as well as between the central doped region and the other outer doped region is constant. A greater distance on the one side is compensated by a smaller distance on the other side. As a result, alignment errors may be compensated for within specific constraints defined by the technology.

In a Zener diode, all doped regions may also be situated within a single opening of a diffusion mask. Normally, field oxide masks of SiO2are used as diffusion masks. The placement of all doped regions in a single opening of a diffusion mask has the advantage that is not possible for other errors in the Zener diode to occur due to errors in the alignment of the diffusion mask.

The N-doped and P-doped regions may be designed so that each is symmetrical to a plane perpendicular to the substrate surface. Such symmetry simplifies the production of the doped regions, for one thing, because it is possible to reproduce structures once produced by reflection. Furthermore, the symmetrical design of the doped regions has the advantage that in the case of double Zener diode, an even improved compensation for alignment errors along the connection axis of the outer doped regions is possible.

The dopes regions may be doped P+ or N+. This increases the number of charge carriers in the particular doped regions, resulting in improved conductivity.

In order to form a PN junction, the P-doped and N-doped regions may overlap.

The Zener diode or the doped regions of the Zener diode may be produced using photolithographic masks. The minimum width may be adapted to the maximum expected alignment error of the masks with one another, in the direction of the width of the doped regions. In this regard, it is advantageous if the minimum width of the doped regions is greater than the alignment error to be expected in this direction. It is thus possible to ensure that even with maximum alignment error, the two doped regions overlap, making it possible to ensure a functioning diode.

In a similar manner, in a double Zener diode, it is possible to adapt a distance between the outer doped regions, i.e., the distance between those doped regions having the same doping polarity, to the maximum alignment error to be expected in the direction of the connection between the outer doped regions. This adaptation is performed in connection with the extension of the intermediate doped region. Overall, it must be ensured that, even with a maximum alignment error, a functioning PN junction will be produced. To that end, the distance of the outer doped regions or the size of the inner doped region must be selected in such a way that the size of the inner doped region, together with the maximum alignment error, produces roughly the distance of the two outer doped regions from one another.

A Zener diode circuit is described herein, in which the Zener diode is connected with means for impressing an electric current and in which the Zener diode is connected to means for reading out the condition of the Zener diode.

This makes it possible to program the Zener diode using a programmable current. This means that the Zener diode is changed from a condition before burn-through into a condition after burn-through, i.e., into a condition having resistance. This condition may now be read out to determine the programming state of the Zener diode.

Furthermore, a method for manufacturing a Zener diode is described herein, in which photolithography is used to create two masks on a semiconductor substrate. Such masks may be created, for example, by structuring a photoresist. The photoresist may be structured optically, for example, by using light. The first mask has a first opening on the substrate surface. The second mask has a second opening on the substrate surface. The width of the openings diminishes on the sides facing one another and diminishes to a finite minimum width. The minimum width must be adapted to the maximum expected alignment error of the openings with one another. The substrate is N-doped or P-doped below the first opening. Below the second opening, the substrate is doped with a doping opposite to the first opening. For example, the second substrate is P-doped below the second opening. Moreover, the following operations are performed:a) Production of the first mask,b) Alignment of the second mask relative to the first mask,c) Production of the second mask.

The method has the advantage that the geometric design of the masks corresponding to the procedural method makes it possible to compensate for alignment errors of the masks in relation to one another.

Furthermore, a method for manufacturing a Zener diode is described herein, in which photolithography is used to create two masks on a surface of a semiconductor substrate, and in which a first mask has a first opening on the surface of the semiconductor substrate. The second mask has two additional openings on the surface of the semiconductor substrate. The first opening is positioned between the two additional ones. The width of the openings diminishes on the sides facing one another and diminishes to a finite minimum width. The minimum width is adapted to the maximum expected alignment error of the masks in relation to one another in the direction of the width. The semiconductor substrate is N-doped or P-doped below the first opening. Below the two other openings, the semiconductor substrate is doped with an opposite doping, i.e., P-doping or N-doping. Moreover, the following steps are performed:a) Production of the first mask,b) Alignment of the second mask relative to the first mask,c) Production of the second mask

The method for producing the Zener diode has the advantage that it is even possible to compensate for alignment errors perpendicular to the width of the openings. This is successful, in particular, if the distance between the second openings and the length of the first opening between the second openings is adapted in such a way that the expected alignment error is less than the distance between the two outer openings minus the length of the center opening. Such a geometric design of the openings ensures that at least one functioning Zener diode is manufactured in any case.

DETAILED DESCRIPTION

FIG. 1shows a semiconductor substrate1, which has an N-doped region2and a P-doped region3. Each of doped regions2,3is provided with a contact surface13, which makes them electrically bondable. The semiconductor substrate may be, for example, a silicon substrate. Doped regions2,3may be, for example, situated in an N-well or even in a P-well. The N-doped region has N+ doping. The P-doped region has P+ doping. Doped regions2,3overlap after the completion of the manufacturing process and form a PN junction4in the overlap area. At their mutually facing ends, doped regions2,3have a width b, which diminishes toward the particular other doped region2,3. Doped regions2,3come together at a point. However, their mutually facing ends do not have points but instead, their mutually facing ends are defined by straight edges51,52. Doped regions2,3thus have flattened points. Advantageously they may have a trapezoidal shape. Minimum width b1of doped regions2,3at the mutually facing ends is selected in such a way that it is adapted to the maximum expected alignment error (see alsoFIG. 3in this regard). Due to the diminishing width, the doped regions and the Zener diode formed from them have the advantage that it is possible to concentrate a current used for programming the Zener diode spatially, making it possible to keep the current required for the burn-through of the diode relatively low. Cutting off the points of the doped regions makes it possible to compensate for alignment errors.

The layout drawing of the mask openings usually contains a bias, which is an intentional reduction or enlargement compared to the intended final size of the opening. It is intended to counteract displacements of the opening boundaries (by photoresist exposure and development, lateral outward diffusion), which are already known in the manufacturing method. It is therefore normally the case that the drawing of the P and N regions does not show the final distance of the two regions. However, all of these effects must already be considered in the drawing in order to guarantee an optimum functioning of the element. There are therefore production processes in which the drawings of the P and N regions already overlap (as shown, for example, inFIG. 1).

The doped regions may have dimensions from 1 to 10 μm.

FIG. 2shows a semiconductor substrate1having a diffusion mask6, which may be, for example, a field oxide (SiO2). Diffusion mask6has an opening18, in which two additional openings15,16are situated. These openings15,16are associated with masks used to structure the Zener diode. Semiconductor substrate1is N+ doped below first opening15. Semiconductor substrate1is P+ doped below second opening16. It must be noted that the shape of openings15,16does not necessarily coincide with the outlines of doped regions2,3because, for example, beam divergence or diffusion processes occurring after doping may result in changes in the shape of doped regions2.3. What was stated for doped regions2,3with respect to the shape of the mutually facing ends and with respect to the width or minimum width b1also applies to openings15,16of two different masks, which are used for manufacturing the Zener diode.

The doping in openings15,16may, for example, be the result of ion implantation or even diffusion.

FIG. 3shows two openings15,16opening15being associated with a first mask and opening16with a second mask. The two masks should be aligned in relation to one another.

In the direction of diminishing width b or in the direction of minimum width b1, the device used to align the masks, an exposure machine, for example, has a maximum alignment error f1. An appropriate selection of minimum widths b1of openings15,16makes it possible to compensate for such a maximum alignment error f1in such a way that even with a maximum alignment error, the doped regions produced by openings15,16overlap, and consequently a Zener diode is formed. For this purpose, it is necessary that:
b1>f1.

FIG. 4shows the production of a Zener diode using a first mask having an opening15. A second mask has openings16,17on the surface of a silicon substrate. Openings15or16and17are designed to have mirror symmetry to a vertical plane.

According toFIG. 4, the following is true of the maximum expected alignment error f2in the direction of the connection between openings16,17:
d-1≧f2.

In this arrangement, in the formula, the case was described in which openings16,17are spaced apart in the drawing.

In this arrangement, l is the length of opening15. Accordingly, distance d between openings16,17or length l of opening15is selected in such a way that opening15is only able to migrate back and forth between the particular right (opening16) or left (opening17) end when openings16,17are aligned. The position of opening15is a function of the alignment of the masks with one another.

FIGS. 5A and 5Bshow a double Zener diode having three doped regions each. According toFIG. 5A, a doped region2and a doped region21are N+ doped. A P+ doped region3is situated between doped regions2,21. The shaping of doped regions2,21,3is selected according toFIG. 1or according toFIG. 3. Each doped region2,3,21is provided with a contact surface21. Furthermore, terminal leads19to the double Zener diode are suggested, according to which a parallel circuit of the left Zener diode (formed by PN junction41) and the right Zener diode (formed by PN junction42) is provided.

FIG. 6shows a Zener diode circuit having a Zener diode8, which is connected to a device for impressing a current into Zener diode9,12. To that end, a programmable transistor9is connected to Zener diode8. A control logic12is connected to programming transistor9. Control logic12determines if programming transistor9is to become conductive. If this is the case, a high current flows through Zener diode8, which shorts Zener diode8and shifts the Zener diode into the programmable condition. The programming state of Zener diode8may be read out using a comparator10in conjunction with a pull-up resistor11. In addition, a contact surface13is provided, via which additional electrical or electronic modules or components may be connected to Zener diode8, or to which the required programming voltage may be fed.

A typical switching voltage applied to the Zener diode is between 3 and 5 volts.

The programming current required to short the Zener diode is typically 100 mA, the read-out current 50 μA. The programming voltage required is a function of the size of the programming transistor; however, it is typically between 5 and 8 volts.

The examples described herein are not limited to PROM components, but instead may be generally applied to any form of Zener diode or PN junction.