Extremum locator with measurement enable circuit

A controller for use in a power converter for transferring energy between an input and an output, the controller comprising a second controller to generate a request event and a request signal in response to a feedback signal and a switching window signal, the second controller to transmit the request event during a switching window of the switching window signal. The second controller comprising an extremum locator switching window generator to generate the switching window corresponding with an extremum in the winding signal and a measurement enable circuit to output an enable signal to enable the extremum locator switching window generator to measure a duration of a half cycle to generate the switching window. The measurement enable circuit to enable the extremum locator switching window generator in response to the feedback signal reaching a percentage of a target reference and output a quiet signal to prevent transmitting the request event.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates generally to switched mode power converters, and more specifically to an output-side controller for a switched mode power converter.

Discussion of the Related Art

Electronic devices use power to operate. Switched mode power converters are commonly used due to their high efficiency, small size and low weight to power many of today's electronics. Conventional wall sockets provide a high voltage alternating current. In a switching power converter, a high voltage alternating current (ac) input is converted to provide a well-regulated direct current (dc) output through an energy transfer element. The switched mode power converter controller usually provides output regulation by sensing one or more signals representative of one or more output quantities and controlling the output in a closed loop. In operation, a switch is utilized to provide the desired output by varying the duty cycle (typically the ratio of the on time of the switch to the total switching period), varying the switching frequency, or varying the number of pulses per unit time of the switch in a switched mode power converter.

Typical losses related to switched mode power converters are referred to as conduction losses and switching losses. Switching losses may also be referred to as crossover losses. Conduction losses and switching losses due to the electrical resistance in the circuit and the parasitic capacitance that is switched by the power converter, in particularly the power switch of the power converter. When the power switch of the power converter conducts current, the resistance of the power switch along with the current which passing in the power switch generates conduction loss. Switching losses are generally associated with the losses which occur while the power switch is transitioning between an ON state and an OFF state or vice versa. In one example, a switch that is ON (or closed) may conduct current while a switch that is OFF (or open) cannot conduct current. When the power switch is open, voltage across the switch stores energy in the parasitic capacitance. The parasitic capacitance discharges when the power switch closes, dissipating the energy stored in the parasitic capacitance in the resistance of the power switch to produce switching loss.

DETAILED DESCRIPTION

As mentioned above, one type of loss in power converters is switching loss due to the turning on and off of the power switch. For isolated power converters, high frequency turn on oscillations in the voltage and current of the power switch may occur due to the resonance between the leakage inductance of the transformer of the power converter and the parasitic capacitance of the power switch. Further, when the power converter is operating in discontinuous conduction mode (DCM), another lower frequency oscillation may also occur between the magnetic inductance of the transformer and the parasitic capacitance of the power switch in addition to the high frequency oscillations discussed. In general, operating the power converter to reduce the losses due to the lower frequency oscillation may be referred to as quasi resonance (QR) mode of operation. One method of QR mode of operation for reducing the switching losses related to turning ON the power switch in an isolated power converter operating in DCM may be quasi resonant valley switching of the power switch where an input parameter, such as the current of the power switch, is directly monitored so that a voltage across the power switch is at or near a minimum when the power switch is turned ON.

Safety requirements generally require for the input-side of a power converter to be galvanically isolated from the output-side of the power converter, generally referred to as isolated power converters. Isolated power converters generally utilize high frequency transformers to provide galvanic isolation. Further, some products and applications may require a low regulated output voltage, such as 5 volts (v) and below. In these low voltage cases, a power converter with synchronous rectification may be utilized to achieve higher efficiency and lower form factor for the power converter. Synchronous rectification replaces an output rectifier diode with a synchronized rectifier switch (e.g., a transistor) which is switched to behave like a rectifier to reduce voltage drop and power loss.

For an isolated power converter which includes synchronous rectification, the controller for the power converter generally includes a first controller, referenced to the input-side of the power converter, which controls the switching of the input-side power switch of the power converter to control the transfer of energy between the input and the output side of the power converter. The controller for the power converter may also include a second controller, referenced to the output-side of the power converter and galvanically isolated from the first controller, which controls switching of the synchronous rectifier switch coupled to the output-side of the power converter. The second controller may also sense the output of the power converter and provide output regulation by sending a request event to the first controller to turn on the input-side power switch. A second controller referenced to the output-side of the power converter may provide tighter output regulation and faster response to load transients.

As mentioned above, one method of QR mode of operation for reducing the switching losses may be quasi resonant valley switching of the power switch where the current of the power switch is directly monitored so that a voltage across the power switch is at or near a minimum when the power switch is turned ON. However, for a power converter which utilizes a second controller referenced to the output-side of the power converter to determine when to turn ON the power switch, the second controller does not have direct access to the current of the power switch to determine when to turn ON the power switch. However, an energy transfer element may have an input winding and an output winding and the voltages and currents of the input and output windings are related to the turns ratio of input and output windings. As such, the second controller may indirectly determine the voltage across the power switch by monitoring the output winding of the energy transfer element.

In operation of an example synchronous flyback power converter, the synchronous rectifier switch is conducting (e.g. transferring energy to the output) during at least a portion of the off-time of the power switch. During continuous conduction mode (CCM), the synchronous rectifier switch is still conducting when the power switch turns ON. During discontinuous conduction mode (DCM), the synchronous rectifier switch stops conducing before turning ON the power switch. As such, ringing occurs on the output winding (also referred to as a relaxation ring) due to the secondary parasitic inductances and capacitances. Each peak of the relaxation ring on the output winding represents a valley point of the power switch voltage, and vice versa. The peaks and valleys may be referred to as extremum. As used herein “extremum” or “extrema” includes any local maximum or minimum points or may be referred to as “peaks” and “valleys”, where mathematically, the slope (i.e., derivative of the ringing/oscillation waveform) approaches zero. As such, turning on the power switch during an extremum of the output winding may minimize switching losses of the power switch. For QR mode, switching losses may be minimized by turning ON the power switch near the peak of the output winding relaxation ring which represents a valley of the power switch voltage when the power converter is operating in DCM.

Another technique to reduce losses experienced by the power converter is to utilize an active clamp circuit to reduce the switching losses through the use of zero voltage (ZV) switching techniques. Similar to a passive clamp circuit, an active clamp circuit is coupled across the input winding of the energy transfer element of a power converter and includes a switch (such as a transistor) to enable current flow through the active clamp circuit. The switch for the active clamp circuit may be referred to as a clamp switch. The active clamp circuit facilitates the discharge of the parasitic capacitance associated with the power switch and the voltage across the power switch falls to substantially zero prior to the power switch turning ON and as such switching losses may be reduced.

The first and second controller and the power converter can operate in zero voltage switching (ZV) mode in which the clamp switch is turned ON to discharge the parasitic capacitance associated with the power switch prior to the power switch turning ON. Similar to the QR mode, during DCM the second controller monitors the output winding to determine when to turn on the clamp switch and the power switch. For the clamp switch to facilitate the discharge of the parasitic capacitance of the power switch, the voltage across the power switch should be non-zero when the clamp switch turns on. As such, the turning on the clamp switch during an extremum of the output winding may minimize switching losses of the power switch. For ZV mode, switching losses may be minimized by turning ON clamp switch near the valley of the output winding relaxation ring which represents a peak of the power switch voltage when the power converter is operating in DCM.

In embodiments, determining the extremum of the output winding includes measuring the half cycle of the relaxation ring to determine a switching window for the request events in a request signal. The switching window corresponds with the extremum of the output winding. Embodiments discussed herein may include a first controller configured to generate a drive signal to control switching of a power switch to control the transfer of energy between the input and the output of the power converter. The first controller may also generate a clamp drive signal to control the switching of a clamp switch of an active clamp circuit. The outputting of the drive signal and/or the clamp drive signal may be responsive to a request event in the request signal. Embodiments further include a second controller which generates the request signal and the request events. The second controller transmits a request event in the request signal during a switching window of the switching window signal. In embodiments, the switching window correlates with an extremum of a winding signal of the energy transfer element. Embodiments further included a measurement enable circuit which enables the second controller to determine the switching window for the switching window signal. In one embodiment, the second controller measures the half cycle of the relaxation ring to determine the switching window. The measurement enable circuit enables the measurement of the half cycle if the output of the power converter reaches a percentage amount of the target regulation value. Further, in embodiments the measurement enable circuit outputs a quiet signal which prevents the secondary controller from outputting any request events in the request signal. The quiet signal further allows the power converter to operate in DCM such that the half cycle of the relaxation ring may be measured.

To illustrate,FIG. 1is a diagram of an example power converter100with a first controller121and second controller122including an extremum locator switching window generator146and measurement enable circuit138, in accordance with an embodiment of the present disclosure. The illustrated example power converter100includes an energy transfer element T1106, an input winding108of the energy transfer element T1106, an output winding110of the energy transfer element T1106, a power switch S1112, an input return111, a clamp circuit114, an output rectifier S2114, an output capacitor CO115, an output return118, a feedback sense circuit120, a second controller122, and a first controller121. The second controller122is shown as including a synchronous rectifier (SR) control and request circuit132, a measurement enable circuit138, a discontinuous conduction mode (DCM) sense circuit145, extremum locator switching window generator146and comparators133,139, and147. A communication link199between the second controller122and first controller121is also shown.

Further shown inFIG. 1are an input voltage VIN102, an output voltage Vo116, an output current IO117, a winding signal FWD123, a feedback signal FB124, an output voltage signal VOUT116, a request signal REQ127, a current sense signal ISNS129, a switch current ID130, a power switch voltage VD150, a primary drive signal DR131. The example shown can also include a clamp drive signal CD184if the clamp circuit114is an active clamp circuit with a clamp switch.FIG. 1further illustrates a regulation reference REF134, a secondary control signal SEC_CTRL135, a quiet signal QUIET136, a switching window signal SW136a percentage of the regulation reference X % REF140, an synchronous on signal SR_ON141, a DCM signal142, a complete signal CMPL143, an enable signal EN144, and a trim signal QRZV148. In the illustrated example, the power converter100is shown as having a flyback topology. Further, the input of power converter100is galvanically isolated from the output of power converter100, such that input return111is galvanically isolated from output return118. Since the input and output of power converter100are galvanically isolated, there is no direct current (dc) path across the isolation barrier of energy transfer element T1106, or between input winding108and output winding110, or between input return111and output return118. It is appreciated that other known topologies and configurations of power converters may also benefit from the teachings of the present disclosure.

The power converter100provides output power to a load119from an unregulated input VIN102. In one embodiment, the input VIN102is a rectified and filtered ac line voltage. In another embodiment, the input voltage VIN102is a dc input voltage. The input VIN102is coupled to the energy transfer element106. In some embodiments, the energy transfer element106may be a coupled inductor, transformer, or an inductor. The example energy transfer element106is shown as including two windings, an input winding108(also referred to as a primary winding) and an output winding110(also referred to as a secondary winding). However, the energy transfer element106may have more than two windings. The input winding108of the energy transfer element is further coupled to the power switch S1112and the power switch S1112is further coupled to input return111. The voltage at the drain of the power switched S1112is denoted as power switch voltage VD150. Coupled across the input winding108is the clamp circuit114. The clamp circuit114limits the maximum voltage on the power switch S1112. Further, when the clamp circuit114includes active circuit components, such as a switch, the clamp circuit114may facilitate zero voltage switching of the power switch S1112(e.g., ZV control mode of the first controller121and second controller122).

Output winding110is coupled to the output rectifier S2114, which is exemplified as a transistor used as a synchronous rectifier. However, the output rectifier S2114may be a diode. Output capacitor CO115is shown as being coupled to the output rectifier S2114and the output return118. The power converter100further includes circuitry to regulate the output, which in one example may be the output voltage VOUT116, output current IO117, or a combination of the two. A feedback sense circuit120is coupled across the output capacitor CO115to provide the feedback signal FB124, representative of the output of the power converter100, to the second controller122. For the example shown, the feedback signal FB124is a scaled version of the output voltage VO116. The second controller122is further coupled to the output capacitor CO115to receive the output voltage VOUT116and the second controller122is coupled to the output winding110to receive the winding signal FWD123. The winding signal FWD123is representative of the voltage at one end of the output winding110. For the example shown, the winding signal FWD123is representative of the voltage at the non-dotted end of output winding110and the drain voltage of the output rectifier S2114, illustrated as a transistor utilized as a synchronous output rectifier.

The second controller122includes an SR control and request circuit132and comparator133. Comparator133is coupled to receive the feedback signal FB124and the regulation reference REF134. In particular, comparator133is coupled to receive the feedback signal FB124at its inverting input and the regulation reference REF134at its non-inverting input. The SR control and request circuit132is configured to receive the output of comparator133, the winding signal FWD123, and the switching window signal SW137. In response to the comparison of the feedback signal FB124to the regulation reference REF134and the winding signal FWD123, the SR control and request circuit132outputs the secondary drive signal SR126and the request signal REQ127. The secondary drive signal SR126is received by the output rectifier S2114and controls the turn on and turn off of the output rectifier S2114. The request signal REQ127is representative of a request to turn on the power switch S1112. The request signal REQ127may include request events128which are generated in response to the comparison of the feedback signal FB124to the regulation reference REF134. The request signal REQ127may be a rectangular pulse waveform which pulses to a logic high value and quickly returns to a logic low value. The logic high pulses may be referred to as request events128. The SR control and request circuit132also receives the switching window signal SW137. As will be further discussed, the switching window signal SW137is representative of the timing in which the SR control and request circuit132may output request events128in the request signal REQ127. In embodiments, the switching window signal SW137includes switching windows in which the SR control and request circuit132may output request events128. Further, when the second controller is operating in DCM, the switching windows in the switching window signal SW137may correspond with extremums in the winding signal FWD123. By synchronizing the timing of the request events128with extremums in the winding signal FWD123, the power converter100may operate in either quasi-resonant or zero-voltage control to minimize switching losses.

The first controller121is coupled to receive a current sense signal ISNS129representative of the switch current ID130of the power switch S1112and the request signal REQ127through a communication link199, shown as a dashed line, and outputs the primary drive signal D1134. The first controller121provides the primary drive signal DR131to the power switch S1112to control various switching parameters of the power switch S1112to control the transfer of energy from the input of to the output of the power converter100through the energy transfer element106. Example of such parameters include switching frequency (or switching period), duty cycle, on-time and off-times, or varying the number of pulses per unit time of the power switch S1112. In addition, the power switch S1112may be controlled such that it has a fixed switching frequency or a variable switching frequency. In one example of variable switching frequency control, the switching frequency may be reduced for light-load or no-load conditions. In one embodiment, the primary drive signal DR131is a rectangular pulse waveform with varying durations of logic high and logic low sections, logic high sections corresponding to the power switch S1112being ON and logic low sections corresponding to the power switch S1112being OFF. In one embodiment, the first controller121outputs the primary drive signal DR131to turn ON the power switch S1112in response to a request event128in the request signal REQ127. The first controller121outputs the primary drive signal DR131to turn OFF the power switch S1112when the switch current ID130provided by the current sense signal ISNS129reaches a current limit.

If the clamp circuit114includes active components, such as a transistor, the first controller121may also output a clamp drive signal CD184. The clamp drive signal CD184controls various switching parameters of the clamp switch, such as the on-times or off-times of the clamp switch. In one embodiment, the clamp drive signal CD184is a rectangular pulse waveform with varying durations of logic high and logic low sections, logic high sections corresponding to the clamp switch being ON and logic low sections corresponding to the clamp switch being OFF. In one example, in response to a request event128in the request signal REQ127, the first controller outputs the clamp drive signal CD184to turn ON the clamp switch for a duration which may be selected such that sufficient charge is provided from the clamp circuit114to the input winding108, which will be used to discharge the parasitic capacitance of the power switch S1112. In one embodiment, once the clamp drive signal CD84turns OFF the clamp switch of the clamp circuit114, the first controller121outputs the primary drive signal DR131to turn ON the power switch S1112. The first controller121outputs the primary drive signal DR131to turn OFF the power switch S1112when the switch current ID130provided by the current sense signal ISNS129reaches a current limit.

The second controller122and the first controller121may communicate via the communication link199. For the example shown, the second controller122is coupled to the secondary side of the power converter100and is referenced to the output return118while the first controller121is coupled to the primary side of the power converter100and is referenced to the input return111. In embodiments, the first controller121and the second controller122are galvanically isolated from one another and the communication link199provides galvanic isolation using an inductive coupling, such as a transformer or a coupled inductor, an optocoupler, capacitive coupling, or other device that maintains the isolation. However, it should be appreciated that in some embodiments, the second controller122is not galvanically isolated from the first controller121.

In one example, the first controller121and second controller122may be formed as part of an integrated circuit that is manufactured as either a hybrid or monolithic integrated circuit. In one example, the power switch S1112may also be integrated in a single integrated circuit package with the first controller121and the second controller122. In addition, in one example, first controller121and second controller122may be formed as separate integrated circuits. The power switch S1112may also be integrated in the same integrated circuit as the first controller121or could be formed on its own integrated circuit. Further, it should be appreciated that both the first controller121, the second controller122and power switch S1112need not be included in a single package and may be implemented in separate controller packages or a combination of combined/separate packages.

It is generally understood that a switch that is closed may conduct current and is considered on, while a switch that is open cannot conduct current and is considered off. In one example, the power switch S1112may be a transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET), bipolar junction transistor (BJT), silicon carbide (SiC) based transistor, gallium nitride (GaN) based transistor, or an insulated-gate bipolar transistor (IGBT).

The second controller122further includes measurement enable circuit138, comparator139, DCM sense circuit145, extremum locator switching window generator146, and comparator147. As shown, comparator139is configured to receive the feedback signal FB124and a percentage of the regulation reference X % REF140. In one example the percentage of the regulation reference X % REF140is substantially 90% of the regulation reference REF134. In particular, comparator139is coupled to receive the feedback signal FB124at its non-inverting input and percentage of the regulation reference X % REF140at its inverting input. The output of comparator139is received by the measurement enable circuit138. The measurement enable circuit138is also configured to receive a synchronous on signal SR_ON141, representative of a turn ON off the output rectifier S2114.

During start-up of the power converter100, the first controller121is generally in control of regulation of the output until the second controller122is ready to take control. Once the second controller122is ready to take control of regulation, the SR control and request circuit132outputs the secondary control signal SEC_CTRL135, representative of the second controller122having control of regulation of the output, to the measurement enable circuit138. In another embodiment, the SR control and request circuit132may also output the secondary control signal SEC_CTRL135to the extremum locator switching window generator146. The secondary control signal SEC_CTRL135to the extremum locator switching window generator146is shown as a dashed line to illustrate that this may be optional and/or another embodiment. In one example, the SR control and request circuit132determines that the second controller122may take control of the output regulation to load119by monitoring the winding signal FWD123.

Further, the measurement enable circuit138receives a DCM sense signal142, representative of the power converter100operating in DCM, from the DCM sense circuit145. In one example, the DCM sense circuit145receives the winding signal FWD123and determines if the power converter100is operating in DCM or continuous conduction mode (CCM). In one example, the winding signal FWD123is compared to a threshold to determine if the power converter100is operating in DCM or CCM. For example, if the winding signal FWD123is less than the output return118, this may indicate operation in CCM. The DCM sense signal142is provided to the measurement enable circuit138and the extremum locator switching window generator146. In one example, the DCM sense signal142may be a rectangular pulse waveform of varying lengths of logic high and logic low value. In one embodiment, the DCM sense signal142may pulse to a logic high value when the power converter100begins operating in DCM. In another embodiment, the DCM sense signal142may be logic high when operating in CCM and a trailing edge in the DCM sense signal142indicates that the power converter100has begun operating in DCM.

The measurement enable circuit138is also configured to output an enable signal EN144and a quiet signal136to the extremum locator switching window generator146. Alternatively, the measurement enable circuit138may output the quiet signal136to the SR control and request circuit132. The enable signal EN144is representative of enabling measurement of a half cycle of the relaxation ring of the winding signal FWD123. In one embodiment, the extremum locator switching window generator146outputs a complete signal CMPL143, representative of the measurement of the half cycle of the relaxation ring of the winding signal FWD123for the half cycle reference being complete, to the measurement enable circuit138. As shown, the complete signal CMPL143to the measurement enable circuit138is shown in a dashed line to illustrate that this may be optional or another embodiment. The quiet signal136is representative of a quiet duration in which request events128are prevented from being transmitted to the first controller121via the request signal REQ127.

In operation, the measurement enable circuit138is in an idle state until the secondary control signal SEC_CTRL135indicates that the second controller122has taken control of regulating the output of the power converter100. Once the secondary control signal SEC_CTRL135indicates that the second controller122has taken control of regulating the output (e.g., the secondary control signal SEC_CTRL135has been asserted), the measurement enable circuit138is a monitoring state in which the measurement enable circuit138monitors the comparison between the feedback signal FB124and the percentage of the regulation reference X % REF140and the synchronous on signal SR_ON141. In one embodiment, the enable signal EN144is asserted in response to the comparison between the feedback signal FB124and the percentage of the regulation reference X % REF140and the synchronous on signal SR_ON141. For example, the enable signal EN144is asserted when the feedback signal FB124is greater than the percentage of the regulation reference X % REF140. However, the assertion of the enable signal EN144is synchronized with the synchronous on signal SR_ON141. In one example, the synchronous on signal SR_ON141is a rectangular pulse waveform which quickly pulses to a logic high value then falls to a logic low value when the output rectifier S2114turns ON. If the feedback signal FB124is greater than the percentage of the regulation reference X % REF140prior to the synchronous on signal SR_ON141indicating that the output rectifier S2114has turned ON, the enable signal EN144is asserted when the turn on of the output rectifier S2114during the current switching cycle. If the feedback signal FB124is greater than the percentage of the regulation reference X % REF140after the synchronous on signal SR_ON141indicates that the output rectifier S2114has turned ON, the enable signal EN144is not asserted until the next switching cycle in which the output rectifier S2114turns ON. Once the enable signal EN144is asserted, the quiet signal136is asserted to prevent request events128from being sent to the first controller121.

The measurement enable circuit138is in an enabled measurement state once the enable signal EN144is asserted. During at least a portion of this state, both the enable signal EN144and the quiet signal136are asserted. Once the DCM signal142indicates that the power converter100is operating in DCM, a first duration is added to the current duration of the quiet signal136. In one embodiment, a monostable multivibrator (also referred to as a one-shot) is triggered by the DCM signal142indicating that the power converter100is operating in DCM to add the first duration. The quiet signal136is deasserted when the first duration ends. In one example, the first duration is selected to be long enough for one or two full cycles of the relaxation ring of the winding signal FWD123to occur. In one example, the first duration is substantially 10 μs. In another example, the first duration is within the range of 10 to 20 μs. In one embodiment, if the enable signal EN144is deasserted prior to the first duration ending, the quiet signal136is deasserted in response to the deassertion of the enable signal EN144. In one embodiment, the enable signal EN144is deasserted in response to the secondary control signal SEC_CTRL135being deasserted. The measurement enable circuit138returns to the idle state when the secondary control signal SEC_CTRL135indicates that the second controller122no longer has control of the output regulation (e.g., the secondary control signal SEC_CTRL135is deasserted). Once the measurement enable circuit138returns to the idle state, the enable signal EN144is deasserted.

In another embodiment in which the measurement enable circuit138receives the complete signal CMPL143, the measurement enable circuit138may dessert the enable signal EN when the complete signal CMPL143indicates that the half cycle measurement of the winding signal FWD123for the half cycle reference which generates the switching windows in the switching window signal SW137has been completed by the extremum locator switching window generator146. As will be further discussed for this embodiment, the extremum locator switching window generator146utilizes the secondary control signal SEC_CTRL135to return to an idle state of the extremum locator switching window generator146.

Extremum locator switching window generator146is coupled to receive the quiet signal136, the DCM signal142, enable signal EN144, the output of comparator147, and a trim signal QRZV148. Optionally and/or in one embodiment, the extremum locator switching window generator146may also receive the secondary control signal SEC_CTRL135, as shown by the dashed line. Comparator147is coupled to receive the winding signal FWD123and the output voltage VOUT116. As shown, the winding signal FWD123is received at the non-inverting input while the output voltage VOUT116is received at the inverting input of comparator147. The extremum locator switching window generator146outputs the switching signal SW137, which is representative of when the second controller122may output request events128in the request signal REQ127. In one example, the switching signal SW137may be a rectangular pulse waveform with varying durations of logic high and logic low sections. Logic high sections may correspond to a switching window in which the SR control and request circuit132may output request events128in the request signal REQ127. Logic low sections may correspond to windows of “no switching” in which the SR control and request circuit132is prevented from outputting request events128in the request signal REQ127.

When the power converter100is operating in DCM, the extremum locator switching window generator146outputs switching windows in the switching signal SW137which corresponds to extremums in the relaxation ring of the winding signal FWD123. The trim signal QRZV148is representative of the trim option between QR control mode and ZV control mode. As mentioned above, in ZV mode, switching losses may be minimized by sending request events128near the valley of the winding signal FWD123relaxation ring. In QR mode, switching losses may be minimized by sending request events128near the peak of the winding signal FWD123relaxation ring. As such, when the trim signal QRZV148indicates that the second controller122is operating in QR mode, the extremum locator switching window generator146outputs switching windows in the switching signal SW137which corresponds to peaks in the relaxation ring of the winding signal FWD123. When the trim signal QRZV148indicates that the second controller122is operating in ZV mode, the extremum locator switching window generator146outputs switching windows in the switching signal SW137which corresponds to valleys in the relaxation ring of the winding signal FWD123.

In embodiments, the extremum locator switching window generator146determines the extremum of the winding signal FWD123by measuring the half cycle of the relaxation ring of the winding signal FWD123. Once the half cycle of the relaxation ring is measured, the extremum locator switching window generator146determines a half cycle reference which is utilized to output the switching windows in the switching window signal SW137.

In operation, the extremum locator switching window generator146is in an idle state when the enable signal EN144is not asserted. The extremum locator switching window generator146transitions to a measurement state once the enable signal EN144is asserted. When the enable signal EN144is asserted, the extremum locator switching window generator146measures the half line cycle from the comparison of the winding signal FWD123to the output voltage VOUT116(e.g. the output of comparator147). The extremum locator switching window generator146begins the measurement of the half line cycle once the DCM signal142indicates that the power converter100is operating in DCM. Once measurement of the half line cycle has been completed, the extremum locator switching window generator146stores the measured half line cycle and converts it to a half cycle reference. The half cycle reference is utilized to generate the switching windows of the switching window signal SW137. In addition, the complete signal CMPL143indicates that the measurement of the half cycle for the half cycle reference has been completed.

If the trim signal QRZV148indicates QR control mode, the extremum locator switching window generator146measures the half line cycle once when the winding signal FWD123is greater than the output voltage VOUT116after the DCM sense signal142indicates the power converter100is operating in DCM. Further, the complete signal CMPL143indicates that the measurement has been completed when the winding signal FWD123has crossed the output voltage VOUT116twice after the DCM sense signal142indicates the power converter100is operating in DCM.

If the trim signal QRZV148indicates ZV control mode, the extremum locator switching window generator146measures the half line cycle once when the winding signal FWD123is less than the output voltage VOUT116after the DCM sense signal142indicates the power converter100is operating in DCM. Further, the complete signal CMPL143indicates that the measurement has been completed when the winding signal FWD123has crossed the output voltage VOUT116three times after the DCM sense signal142indicates the power converter100is operating in DCM.

Once the complete signal CMPL143indicates that the measurement has been completed (e.g. the complete signal CMPL143is asserted), the extremum locator switching window generator146is in a window generation state in which the winding signal FWD123is compared to the output voltage VOUT116to determine the half cycle for every switching cycle of the power converter100. The half cycle and the half cycle reference are utilized to determine the switching windows of the switching window signal SW137. The extremum locator switching window generator146returns to the idle state when the enable signal EN144is deasserted or the secondary control signal SEC_CTRL135is deasserted. As mentioned above, in one embodiment, the enable signal EN144is deasserted in response to the deassertion of the secondary control signal SEC_CTRL135. As such, the extremum locator switching window generator146returns to the idle state in response to either the enable signal EN144, which is responsive to the secondary control signal SEC_CTRL135. However, in another embodiment the enable signal EN144may be deasserted when the complete signal CMPL143is asserted. For that embodiment, the extremum locator switching window generator146returns to the idle state in response to the secondary control signal SEC_CTRL135. As such, the first controller121and second controller122may minimize switching losses by sending request events128in the request signal REQ127corresponding to extremums in the winding signal FWD123when the power converter100is operating in DCM.

FIG. 2Aillustrates timing diagram200with example waveforms of the power switch voltage VD150, winding signal FWD123, and switching signal SW137when the trim signal QRZV148indicates that the first controller121and second controller122are operating in zero-voltage (ZV) control and the power converter100is operating in discontinuous conduction mode (DCM).

Between times t1255and t2256, the power switch S1112is ON and the duration of time is denoted as the on-time TON251of power switch S1112. During the on-time TON251, the power switch voltage VD150is substantially zero. Further, the output rectifier S2114blocks current to the output of the power converter100and as such the voltage of the winding signal FWD123is substantially the input voltage VIN102times the turns ratio of the energy transfer element T1106, or mathematically:

At time t2256, the power switch S1112is turned OFF and the off-time TOFF252of power switch S1112begins. At the beginning of the off-time TOFF252while the body diode of the output rectifier S2114is conducting due to the energy transfer element T1106transferring energy between the input and the output of the power converter100, the power switch voltage VD150increases and is substantially equal to the sum of the input voltage VIN102and the reflected output voltage VOR. While the body diode of the output rectifier S2114is conducting, the voltage of the winding signal FWD123decreases to a value below zero due to the voltage drop across the body diode of the output rectifier S2114. Once the transfer of energy is complete, the body diode of the output rectifier S2114stops conducting and the relaxation ring occurs for both the power switch voltage VD150and the voltage of the winding signal FWD123. Due to the polarity of the transformer, the polarity of the power switch voltage VD150and the voltage of the winding signal FWD123are opposite of each other. As shown, a peak in the relaxation ring of the power switch voltage VD150corresponds to a valley in the relaxation ring of the winding signal FWD123. The relaxation ring for the power switch voltage VD150generally oscillates around the input voltage VIN102while the relaxation ring for the winding signal FWD123generally oscillates around the output voltage VOUT116. Further, as shown, a full cycle TFC253of the relaxation ring may be measured from a peak to peak (or valley to valley) of either the power switch voltage VD150or the winding signal FWD123. Alternatively, a full cycle TFC253of the relaxation ring may be as the duration between three crossings of the power switch voltage VD150with the input voltage VIN102or the duration between three crossings of the winding signal FWD123with the output voltage VOUT116. The half cycle THC254may be measured as the duration between consecutive crossings of the winding signal FWD123with the output voltage VOUT116, which correspond with consecutive crossings of the power switch voltage VD150with the input voltage VIN102. For a first controller121and second controller122operating in ZV control mode, the half cycle THC254may be measured as the duration with the winding signal FWD123falls below the output voltage VOUT116and then rises above the output voltage VOUT116. As such, the extremum locator switching window generator146may determine the approximate location of the valley of the relaxation ring of the winding signal FWD123.

In response to the comparison between the winding signal FWD123and the output voltage VOUT116, the extremum locator switching window generator146measures the half cycle THC254and determines the switching windows258,259,260of the switching window signal SW137. The switching windows correlate with an extremum in the relaxation ring of the winding signal FWD123. For a first controller121and second controller122operating in ZV control mode, the switching windows258,259,260correlate with valleys in the relaxation ring of the winding signal FWD123. In one embodiment, when the switching window signal SW137is logic low, the second controller122is prevented from sending request events128in the request signal REQ127. The logic high sections correspond to the switching windows258,259,260. When the switching window signal SW137is logic high, the second controller122may send a request event128in the request signal REQ127. At time t3257, a request event128is sent from the second controller122to the first controller121. For ZV control mode and the power converter100includes a clamp circuit114with active components, when the first controller121outputs a clamp drive signal CD184in response to a request event128in the request signal REQ127to turn on a clamp switch of the clamp circuit114. The clamp switch is turned ON for a duration such that sufficient charge is provided from the clamp circuit114to the input winding108to discharge the parasitic capacitance of the power switch S1112. Once the clamp drive signal CD184turns OFF the clamp switch of the clamp circuit114, the first controller121outputs the primary drive signal DR131to turn ON the power switch S1112and the off-time TOFF252of the power switch S1112has ended. The duration between times t2256and t3257is shown as the off-time TOFF252of power switch S1112, however, it should be appreciated that the delay between turning on and off the clmap switch of the clamp circuit114and the turn on of the power switch S1112is not illustrated.

FIG. 2Billustrates timing diagram201with example waveforms of the power switch voltage VD150, winding signal FWD123, and switching signal SW137when the trim signal QRZV148indicates that the first controller121and second controller122are operating in quasi-resonant (QR) control and the power converter100is operating in DCM. It should be appreciated that the waveforms for the power switch voltage VD150and the voltage of winding signal FWD123are similar to what is shown and described with respect toFIG. 2A. At least one difference, however, is the switching windows258,259, and260correlate with peaks of the relaxation ring of the winding signal FWD123when the first controller121and second controller122are operating in QR control mode.

The half cycle THC254may be measured as the duration between consecutive crossings of the winding signal FWD123with the output voltage VOUT116, which correspond with consecutive crossings of the power switch voltage VD150with the input voltage VIN102. For a first controller121and second controller122operating in QR control mode, the half cycle THC254may be measured as the duration with the winding signal FWD123increase above the output voltage VOUT116and then falls below the output voltage VOUT116. As such, the extremum locator switching window generator146may determine the approximate location of the peak of the relaxation ring of the winding signal FWD123.

In response to the comparison between the winding signal FWD123and the output voltage VOUT116, the extremum locator switching window generator146measures the half cycle THC254and determines the switching windows258,259,260of the switching window signal SW137. The switching windows correlate with an extremum in the relaxation ring of the winding signal FWD123. For a first controller121and second controller122operating in QR control mode, the switching windows258,259,260correlate with peaks in the relaxation ring of the winding signal FWD123. In one embodiment, when the switching window signal SW137is logic low, the second controller122is prevented from sending request events128in the request signal REQ127. The logic high sections correspond to the switching windows258,259,260. When the switching window signal SW137is logic high, the second controller122may send a request event128in the request signal REQ127. At time t3257, a request event128is sent from the second controller122to the first controller121. When operating in QR control mode, the first controller121outputs the primary drive signal DR131to turn ON the power switch S1112in response to a request event128. At time t3257, the off-time TOFF252of the power switch S1112has ended.

FIG. 3Aillustrates the second controller122including the SR control and request circuit132, comparator133, measurement enable circuit138, comparator139, DCM sense circuit145, extremum locator switching window generator146, and comparator147. It should be appreciated that similarly named and numbered elements couple and function as described above.

As mentioned above, comparator133is coupled to receive the feedback signal FB124and the regulation reference REF134. In particular, comparator133is coupled to receive the feedback signal FB124at its inverting input and the regulation reference REF134at its non-inverting input. The SR control and request circuit132is configured to receive the output of comparator133, the winding signal FWD123, and the switching window signal SW137. In response to the comparison of the feedback signal FB124to the regulation reference REF134and the winding signal FWD123, the SR control and request circuit132outputs the secondary drive signal SR126and the request signal REQ127. The secondary drive signal SR126is received by the output rectifier S2114and controls the turn on and turn off of the output rectifier S2114. The request signal REQ127is representative of a request to turn on the power switch S1112and includes request events128which are generated in response to the comparison of the feedback signal FB124to the regulation reference REF134. The SR control and request circuit132also receives the switching window signal SW137. As will be further discussed, the switching window signal SW137is representative of the timing in which the SR control and request circuit132may output request events128in the request signal REQ127. In embodiments, the switching window signal SW137includes switching windows in which the SR control and request circuit132may output request events128.

As discussed above and illustrated inFIGS. 2A and 2B, the switching window signal SW137may be a rectangular pulse waveform with varying durations of logic high and logic low sections. Logic high sections may be referred to as a “switching window” and corresponds to durations of time which the SR control and request circuit132may output request events128in the request signal. In one example, when the switching window signal SW137is logic low, the SR control and request circuit132is prevented from outputting request events128in the request signal REQ127. When the second controller122is operating in DCM, the switching windows in the switching window signal SW137may correspond with extremums in the winding signal FWD123. By synchronizing the timing of the request events128with extremums in the winding signal FWD123, the power converter100may operate in either quasi-resonant (QR) control or zero-voltage (ZV) control to minimize switching losses.

During start-up of the power converter100, the first controller121is generally in control of regulation of the output until the second controller122is ready to take control. Once the second controller122is ready to take control of regulation, the SR control and request circuit132outputs the secondary control signal SEC_CTRL135, representative of the second controller122having control of regulation of the output, to the measurement enable circuit138. Optionally, the SR control and request circuit132outputs the secondary control signal SEC_CTRL135to the extremum locator switching window generator146, as shown by the dashed line received by the half cycle windows circuit361. In one example, the SR control and request circuit132determines that the second controller122may take control of the output regulation to the load119by monitoring the winding signal FWD123.

Comparator139is configured to receive the feedback signal FB124and a percentage of the regulation reference X % REF140. In one example the percentage of the regulation reference X % REF140is substantially 90% of the regulation reference REF134. As shown, comparator139is coupled to receive the feedback signal FB124at its non-inverting input and percentage of the regulation reference X % REF140at its inverting input. The output of comparator139is received by the measurement enable circuit138. The measurement enable circuit138is also configured to receive a synchronous on signal SR_ON141, representative of a turn ON off the output rectifier S2114.

Further, the measurement enable circuit138receives a DCM sense signal142, representative of the power converter100operating in DCM, from the DCM sense circuit145. In one example, the DCM sense circuit145receives the winding signal FWD123and determines if the power converter100is operating in DCM or continuous conduction mode (CCM). In one example, the winding signal FWD123is compared to a threshold to determine if the power converter100is operating in DCM or CCM. For example, if the winding signal FWD123is less than the output return118, this may indicate operation in CCM. The DCM sense signal142is provided to the measurement enable circuit138and the extremum locator switching window generator146. In one example, the DCM sense signal142may be a rectangular pulse waveform of varying lengths of logic high and logic low value. In one embodiment, the DCM sense signal142may pulse to a logic high value when the power converter100begins operating in DCM. In another embodiment, the DCM sense signal142may be logic high when the power converter100is operating in CCM, and a trailing edge in the DCM sense signal142indicates that the power converter100has begun operating in DCM.

The measurement enable circuit138is configured to output an enable signal EN144and a quiet signal136to the extremum locator switching window generator146. Alternatively the measurement enable circuit138may output the quiet signal136to the SR control and request circuit132. The enable signal EN144is representative of enabling measurement of a half cycle of the relaxation ring of the winding signal FWD123. The quiet signal136is representative of a quiet duration in which request events128are prevented from being transmitted to the first controller121via the request signal REQ127.

FIG. 3Billustrates a state diagram300of the operation of the measurement enable circuit138. With reference toFIGS. 3A and 3B, the measurement enable circuit138is in an idle state377until the secondary control signal SEC_CTRL135indicates that the second controller122has taken control of regulating the output of the power converter100. During the idle state377, the enable signal EN144is not asserted. Once the secondary control signal SEC_CTRL135indicates that the second controller122has taken control of regulating the output (e.g., the secondary control signal SEC_CTRL135has been asserted), the measurement enable circuit138transitions to monitoring state378in which the measurement enable circuit138monitors the comparison between the feedback signal FB124and the percentage of the regulation reference X % REF140and the synchronous on signal SR_ON141. In one embodiment, the enable signal EN144is asserted in response to the comparison between the feedback signal FB124and the percentage of the regulation reference X % REF140and the synchronous on signal SR_ON141. For example, the enable signal EN144is asserted when the feedback signal FB124is greater than the percentage of the regulation reference X % REF140. However, the assertion of the enable signal EN144is synchronized with the synchronous on signal SR_ON141. In one example, the synchronous on signal SR_ON141is a rectangular pulse waveform which quickly pulses to a logic high value then falls to a logic low value when the output rectifier S2114turns ON. If the feedback signal FB124is greater than the percentage of the regulation reference X % REF140prior to the synchronous on signal SR_ON141indicating that the output rectifier S2114has turned ON during the same switching cycle, the enable signal EN144is asserted with the turn ON of the output rectifier S2114during the current switching cycle. If the feedback signal FB124is greater than the percentage of the regulation reference X % REF140after the synchronous on signal SR_ON141indicates that the output rectifier S2114has turned ON, the enable signal EN144is not asserted until the next switching cycle in which the output rectifier S2114turns ON (as shown in the example ofFIG. 4A). Once the enable signal EN144is asserted, the quiet signal136is asserted to prevent request events128from being sent to the first controller121. By preventing request events128from being sent, the power switch S1112is also prevented from turning ON, which may force the power converter100to operate in DCM such that the relaxation ring in the output winding FWD123.

The measurement enable circuit138transitions to an enabled measurement state378once the enable signal EN144is asserted. During at least a portion of this state379, both the enable signal EN144is and the quiet signal136are asserted. Once the DCM signal142indicates that the power converter100is operating in DCM, a first duration TOSis added to the duration of the quiet signal136(as will be shown inFIG. 4A). In one embodiment, a monostable multivibrator (also referred to as a one-shot) is triggered by the DCM signal142indicating that the power converter100is operating in DCM. The quiet signal136is deasserted when the first duration ends. However, in one embodiment, the enable signal EN144is deasserted prior to the ending of the first duration and the quiet signal136may be deasserted when the enable signal EN144is deasserted. In one embodiment, the enable signal EN144is deasserted is response to the secondary control signal SEC_CTRL135being is deasserted. The measurement enable circuit138returns to the idle state when the secondary control signal SEC_CTRL135indicates that the second controller122no longer has control of the output regulation (e.g., the secondary control signal SEC_CTRL135is deasserted). Once the measurement enable circuit138returns to the idle state, the enable signal EN144is deasserted.

In another embodiment in which the measurement enable circuit138receives the complete signal CMPL143, the measurement enable circuit138may dessert the enable signal EN when the complete signal CMPL143indicates that the half cycle measurement of the winding signal FWD123for the half cycle reference HC_REF370has been completed by the half cycle windows circuit361. For this embodiment, the extremum locator switching window generator146utilizes the secondary control signal SEC_CTRL135to return to an idle state of the extremum locator switching window generator146.

Returning toFIG. 3A, extremum locator switching window generator146is coupled to receive the quiet signal136, the DCM signal142, enable signal EN144, output of comparator147, and a trim signal QRZV148. Extremum locator switching window generator146may also optionally receive the secondary control signal SEC_CTRL135. Comparator147is coupled to receive the winding signal FWD123and the output voltage VOUT116. In one example, the winding signal FWD123is received at the non-inverting input while the output voltage VOUT116is received at the inverting input of comparator147. The extremum locator switching window generator146outputs the switching signal SW137, which is representative of when the second controller122may output request events128in the request signal REQ127. When the power converter100is operating in DCM, the extremum locator switching window generator146outputs switching windows in the switching signal SW137which corresponds to extremums in the relaxation ring of the winding signal FWD123. When the trim signal QRZV148indicates that the second controller122is operating in QR mode, the extremum locator switching window generator146outputs switching windows in the switching signal SW137which corresponds to peaks in the relaxation ring of the winding signal FWD123. When the trim signal QRZV148indicates that the second controller122is operating in ZV mode, the extremum locator switching window generator146outputs switching windows in the switching signal SW137which corresponds to valleys in the relaxation ring of the winding signal FWD123.

In embodiments, the extremum locator switching window generator146determines the extremum of the winding signal FWD123by measuring the half cycle of the relaxation ring of the winding signal FWD123. The extremum locator switching window generator146also determines half cycle reference HC_REF370from the measured half cycle, which is utilized to output the switching windows in the switching window signal SW137. As shown, the extremum locator switching window generator146includes a half cycle windows circuit361, a timer363, analog-to-digital converter (ADC) and memory circuit368, reference generator371, comparators374and375, AND gates376and398, and OR gate397.

Half cycle windows circuit361is coupled to receive DCM signal142, enable signal EN144, output of comparator147(e.g. the comparison result of the winding signal FWD123and output voltage VOUT116), and trim signal QRZV148. The half cycle windows circuit361may also optionally receive the secondary control signal SEC_CTRL135. In response to the comparison between the winding signal FWD123and output voltage VOUT116, the half cycle windows circuit361outputs the half cycle signal THC354. The half cycle signal THC354is representative of the half cycle of the relaxation ring of the winding signal FWD123. In one embodiment, the half cycle signal THC354is not outputted until the enable signal EN144is asserted. Once the enable signal EN144is asserted, the half cycle windows circuit361may output the half cycle signal THC354. The trim signal QRZV148indicates whether the half cycle windows circuit361is operating in QR control mode or ZV control mode. If the half cycle windows circuit361is operating in QR control mode, the half cycle signal THC354is representative of the half cycle of the relaxation ring of the winding signal FWD123when the winding signal FWD123is greater than the output voltage VOUT116. If the half cycle windows circuit361is operating in ZV mode, the half cycle signal THC354is representative of the half cycle of the relaxation ring of the winding signal FWD123when the winding signal FWD123is less than the output voltage VOUT116. Further, measurement of the half cycle relaxation ring does not begin until after the DCM signal142indicates that the power converter100is operating in DCM.

The timer363is shown as including a current source364, switch365, and capacitance366. The voltage across the capacitance366is referred to the half cycle voltage VHC367. The half cycle voltage VHC367is a voltage value representative of the duration of the half cycle signal THC354. In one example, the half cycle signal THC354is a rectangular pulse waveform of varying lengths of logic high and logic low sections. If the half cycle windows circuit361is operating in ZV control mode, the half cycle signal THC354is logic high when the winding signal FWD123is less than the output voltage VOUT116after the DCM sense signal142indicates the power converter100is operating in DCM. If the half cycle windows circuit361is operating in QR control mode, the half cycle signal THC354is logic high when the winding signal FWD123is greater than the output voltage VOUT116after the DCM sense signal142indicates the power converter100is operating in DCM. In one example, the switch365is ON when the half cycle signal THC354is logic high and turns OFF when the half cycle signal THC354is logic low. When the switch365is ON, the capacitance366is charged by the current source364and the half cycle voltage VHC367is representative of the duration which the half cycle signal THC354is logic high. Although not shown, once the switch365turns off, the capacitance366is discharged to an initial reference value.

In response to the enable signal EN144, the half cycle windows circuit361begins the process of measuring the half cycle of the relaxation ring and for the extremum locator switching window generator146to eventually store the half cycle signal THC354and generate a half cycle reference HC_REF370. The half cycle windows circuit361determines the measurement for the half cycle reference HC_REF370is complete in response to the number of crossings of the winding signal FWD123with the output voltage VOUT116. For example, if the half cycle windows circuit361is operating in QR control mode, the half cycle windows circuit361determines the measurement is complete when the winding signal FWD123has crossed the output voltage VOUT116twice after the DCM signal142indicates that the power converter100is operating in DCM. If the half cycle windows circuit361is operating in ZV control mode, the half cycle windows circuit361determines the measurement is complete when the winding signal FWD123has crossed the output voltage VOUT116three times after the DCM signal142indicates that the power converter100is operating in DCM. Once the half cycle windows circuit361determines the measurement for the half cycle reference HC_REF370is complete, the half cycle windows circuit361asserts the complete signal CMPL143indicating that the measurement of the half cycle is complete. As shown, the complete signal CMPL143is provided to the ADC and memory circuit368. Optionally, the complete signal CMPL143is provided to the measurement enable circuit138.

The ADC and memory circuit368is coupled to receive the half cycle voltage VHC367and the complete signal CMPL143and is configured to output the ready signal READY369and the half cycle reference HC_REF370. When the complete signal CMPL143is asserted, the ADC and memory circuit368converts the half cycle voltage VHC367into a digital value, the half cycle reference HC_REF370and stores the half cycle reference HC_REF370. The ready signal369is representative of the ADC and memory circuit368completing the conversion and storage of the half cycle reference HC_REF370. Once the ADC and memory circuit368has completed the conversion and storage of the half cycle reference HC_REF370, the ready signal369is asserted.

The reference generator371receives the half cycle reference HC_REF370and generates a first reference R1372and a second reference R2373. The first and second references R1372and R2373are utilized to determine the beginning and end of the switching windows of the switching signal SW137. The first and second references R1372and R2373are selected to be a certain percentage of the half cycle reference HC_REF370(and ergo the half cycle voltage VHC367), which corresponds to the extremum of the relaxation ring of the winding signal FWD123. In one example, the first reference R1372is selected to be the 30% of the half cycle reference HC_REF370and the second reference R2373is selected to be 50% of the half cycle reference HC_REF370.

Comparator374is coupled to receive the first reference R1372and the half cycle voltage VHC367. As shown, the first reference R1372is received and the inverting input of comparator374while the half cycle voltage VHC367is received at the non-inverting input of comparator374. Comparator375is coupled to receive the second reference R2373and the half cycle voltage VHC367. As shown, the second reference R2373is received at the non-inverting input while the half cycle voltage VHC367is received at the inverting input of comparator375. The outputs of comparator374and375are received by the AND gate376. In operation, the output of AND gate376is logic high when the half cycle voltage VHC367is greater than the first reference R1372and less than the second reference R2373, otherwise the output of AND gate376is logic low.

AND gates376and398and OR gate397comprise a logic circuit which outputs the switching window signal SW137, and specifically the switching windows in the switching window signal SW137. It should be appreciated that other combinations of logic gates may be used depending on how the various signals are defined. OR gate397is coupled to receive the output of AND gate376and the inverted ready signal369, as illustrated by the small circle at the input of OR gate397which received the ready signal369. Further, AND gate398is coupled to receive the output of OR gate397and the inverted quiet signal135, as illustrated by the small circle at the input of AND gate398which receives the quiet signal136.

As mentioned previously, in one example the SR control and request circuit132is not prevented from sending request events128when the switching signal SW137is logic high and is prevented from sending request events128when the switching signal SW137is logic low. In operation of the example shown, the switching signal SW137is logic low when the quiet signal136is logic high (e.g., asserted). However, if the quiet signal136is logic low (e.g. not asserted) and the ready signal369is logic low (e.g. not asserted), indicating that either the measurement and storage of the half cycle reference HC_REF370has not been completed but the quiet duration by the measurement enable circuit138is completed, the output of the switching signal SW137is logic high and the SR control and request circuit132is not prevented from sending request events128. However, once the ready signal is logic high (e.g. asserted), indicating that the measurement and storage of the half cycle reference HC_REF370has been completed, then the logic value of the switching signal SW137is responsive to the value of the half cycle voltage VHC367compared to the first reference R1372and the second reference R2373. Or in other words, the switching signal SW137is logic high when the half cycle voltage VHC367is greater than the first reference R1372and less than the second reference R2373. As such, the request events128may be synchronized with extremums in the winding signal FWD123.

FIG. 3Cillustrates a state diagram301of the operation of the half cycle window circuit361. With reference toFIGS. 3A and 3C, the half cycle window circuit361is in an idle state380when the secondary control signal enable signal EN144is not asserted. Once the enable signal EN144is asserted, the half cycle window circuit361transitions to a measurement state381. During the measurement state381, the half cycle window circuit361the half cycle window circuit361determines the half cycle THC354in response to the comparison of the winding signal FWD123to the output voltage VOUT116(e.g. the output of comparator147). However, the half cycle window circuit361does not measure the half line cycle until the DCM signal142indicates that the power converter100is in DCM. Further, during the measurement state381, the half cycle window circuit361compares the number of crossings of the winding signal FWD123to the output voltage VOUT116after the DCM signal142indicates that the power converter100is in DCM. The number of crossings determines whether the measurement of the half cycle signal THC354is complete. Once the expected number of crossings has occurred, the complete signal CMPL143is asserted. For QR control mode, the complete signal CMPL143is asserted after two crossings have occurred after the DCM signal142has been asserted. For ZR control mode, the complete signal CMPL is asserted after three crossings have occurred after the DCM signal142has been asserted.

When the complete signal CMPL143is asserted, the half cycle window circuit361transitions to the window generation state382. The previously measured half cycle THC354is stored as the half cycle reference HC_REF370. The half cycle window circuit361continues to compare the winding signal FWD123with the output voltage VOUT116to determine the half cycle signal THC354for subsequent switching cycles of the power switch S1112. If the trim signal QRZV148indicates QR control mode, half cycle window circuit361measures the half cycle signal THC354in response to the winding signal FWD123being greater than the output voltage VOUT116after the DCM sense signal142indicates DCM operation. If the trim signal QRZV148indicates ZV control mode, the half cycle window circuit361measures the half cycle signal THC354in response to the winding signal FWD123being less than the output voltage VOUT116after the DCM sense signal142indicates DCM operation. Both the measurement state381and the window generation state382return to the idle state380if the enable signal EN144is not asserted or the secondary control signal SEC_CTRL135indicates that the second controller122is not in control of output regulation (e.g. deasserted).

FIG. 4Aillustrates a timing diagram400of the winding signal FWD123, synchronous on signal SR_ON141, the output438of comparator139comparing the feedback signal FB124with the percentage of the regulation reference X % REF140, the enable signal EN144, the complete signal CMPL143, DCM signal142, quiet signal136, and the switching signal SW137. For the example shown, the waveforms correspond with the measurement enable circuit138enabling the extremum locator switching window generator146. Further, the secondary control signal SEC_CTRL135is asserted for the duration shown, indicating the second controller122has control of the output regulation. It should be appreciated that similarly named and numbered elements couple and function as described above.

At time t4403, the power switch S1112is ON and the voltage of the winding signal FWD123is substantially equal to the input voltage VIN102multiplied by the turns ratio of the energy transfer element T1106. The synchronous on signal SR_ON141, the output438of comparator139comparing the feedback signal FB124with the percentage of the regulation reference X % REF140, the enable signal EN144, the complete signal CMPL143, DCM signal142, and the quiet signal136are logic low between times t4403and t5404. During this time, the ready signal369is logic low, as such the switching signal SW137is logic high and the SR control and request circuit132is not prevented from sending request events128in the request signal REQ127.

At time t5404, the power switch S1112is turned off and the duration times t4403and t5404is denoted as the on-time TON451of the power switch S1112. The body diode of the output rectifier S2114begins conducting and the synchronous on signal SR_ON141pulses to a logic high value. In one example, the voltage of the winding signal FWD123may be utilized when the synchronous on signal SR_ON141should be asserted. For example, the voltage of the winding signal FWD123falling below a threshold (such as zero) could indicate that the synchronous on signal SR_ON141should be asserted. In another example, the slew rate of the winding signal FWD123may be utilized to determine if the synchronous on signal SR_ON141should be asserted.

At time t6405, the body diode of the output rectifier S2114stops conducting while the power switch S1112is still OFF. As such, the power converter100is operating in DCM and a relaxation ring is observable in the winding signal FWD123. The DCM signal142is asserted at time t6405. In the example shown, the DCM signal142pulses at time t6405. However, the DCM signal142may be a rectangular pulse waveform which is logic high when the winding signal FWD123is less than zero, indicating that the body diode of the output rectifier S2114is still conducting (CCM). For that example, the trailing edge at time t6405indicates that the power converter100is operating in DCM. However, at time t6405, the feedback signal FB124is less than the percentage of the regulation reference X % REF140and the output438of comparator139is logic low and the enable signal EN144remains logic low. At time t7406, the power switch S1112turns on and the off-time TOFF452of the power switch S1112ends.

During the off-time TOFF452of the power switch S1112between times t6405and t7406, the feedback signal FB124exceeds the percentage of the regulation reference X % REF140and the output438of comparator139is logic high. However, the enable signal EN144does not transition to a logic high value until the next time the synchronous on signal SR_ON141is asserted at time t8407(corresponding with the body diode e of the output rectifier S2114conducting for the next switching cycle).

At time t8407, the enable signal EN144and the quiet signal136transition to a logic high value. As a result, the switching signal SW137transitions to a logic low value to prevent the SR control and request circuit132from sending request events128. At time t9408, the DCM signal142is asserted and a first duration TOS483is triggered by the measurement enable circuit138for the quiet signal136. For the example shown, the quiet signal136remains logic high until the end of the first duration TOS483at time t13412and ergo the switching signal SW137remains logic low until time t13412. However alternatively, the quiet signal136can transition to the logic low value once the enable signal EN144is deasserted at time t12411and the switching signal SW137could remain logic low until time t12411.

The example shown inFIG. 4Aillustrates a second controller122operating in ZV control mode. As such, the extremum locator switching window generator146determines the half cycle measurement is complete after three crossings of winding signal FWD123with the output voltage VOUT116after the DCM signal142is asserted. As shown, the DCM signal142is asserted at time t9408. The first crossing of the winding signal FWD123with the output voltage VOUT116occurs at time t10409, the second crossing at time t11410, and the third crossing at time t12411. At time t12411, the complete signal CMPL143is asserted.

FIG. 4Billustrates a timing diagram401illustrating the winding signal FWD123, the enable signal EN144, DCM signal142, half cycle signal THC354, half cycle voltage VHC367, ready signal369and the switching signal SW137. For the example shown, the waveforms correspond with the extremum locator switching window generator146determining the half cycle reference HC_REF370to generate switching windows458and459which correspond to extremums in the winding signal FWD123in the switching signal SW137. Further, the secondary control signal SEC_CTRL135is asserted for the duration shown, indicating the second controller122has control of the output regulation. It should be appreciated that similarly named and numbered elements couple and function as described above. Further, the timing shown inFIG. 4Bis a continuation of the timing shown inFIG. 4A.

At time t8407, the enable signal EN144is logic high, enabling the half cycle window circuit361to output the half cycle signal THC354. Further, the quiet signal136is asserted (as shown inFIG. 4A) and the switching signal SW137is a logic low value. The example shown illustrates a second controller122operating in ZV control mode. As such, the half cycle signal THC354is logic high when the winding signal FWD123is less than the output voltage VOUT116. However, the half cycle window circuit361does not transition the half cycle signal THC354to a logic high value until after the DCM sense signal142is asserted per switching cycle, shown at time t9408and time t18417.

At time t11410, the winding signal FWD123is less than the output voltage VOUT116and the half cycle signal THC354transitions to a logic high value. The switch365of timer363is turned on and the capacitance366is charged by current source364. The voltage across the capacitance366, the half cycle voltage VHC367, is shown as linearly increasing after time t11410. The half cycle signal THC354remains logic high until time t12411, when the winding signal FWD123increases above the output voltage VOUT116. As mentioned with respect toFIG. 4A, the third crossing occurs at time t12411and the complete signal CMPL143is asserted. The half cycle voltage VHC367at time t12411is substantially the analog version of the half cycle reference HC_REF370.

The switching signal transitions to a logic high value at time t13412(as shown inFIG. 4A), but could optionally transition to a logic high value at time t12412as discussed above. While the ready signal369remains logic low, the switching signal SW137remains logic high. After time t12411the analog version of the half cycle reference HC_REF370is converted and stored as a digital value. Once the storing is complete, the ready signal369transitions to a logic high value. The half cycle signal THC354is logic high between times t14413and t15414and between times t16415and t17416. However, since the ready signal369is still logic low, there switching window in the switching window signal SW137does not correspond with the extremum of the winding signal FWD123.

At time t17416, the power switch S1112turns ON. At time t18417, the DCM signal142is asserted. Between times t17416and t18417, the ready signal369transitions to a logic high value, indicating the half cycle reference HC_REF370is converted and stored. The reference generator371outputs the first reference R1373and the second reference R2373, relating to the beginning and ending of the switching windows458and459.

Between times t19418and t20419and between times t21420and t22421, the winding signal FWD123is less than the output voltage VOUT116and the half cycle signal THC354is logic low. The half cycle voltage VHC367increases. Between times t19418and t20419and between times t21420and t22421, the half cycle voltage VHC367is greater than the first reference R1373and less than the second reference R2372and switching signal SW137transitions to a logic high value. The logic high sections are switching windows458and459, which correspond to extremums (in this example, valleys) in the relaxation ring of the winding signal FWD123. As such, switching losses may be minimized by sending request events128in the request signal REQ127corresponding to extremums in the winding signal FWD123when the power converter100is operating in DCM.

Although the present invention is defined in the claims, it should be understood that the present invention can alternatively be defined in accordance with the following examples: Example 1. A controller for use in a power converter having an energy transfer element for transferring energy between an input and an output of the power converter, the controller comprising a first controller configured to generate a first drive signal to control switching of a power switch of the power converter to control the transfer of energy between the input and the output of the power converter, the first controller coupled to receive a request signal and configured to generate the first drive signal in response to a request event in the request signal; and a second controller configured to generate the request event and the request signal in response to a feedback signal representative of an output of the power converter and a switching window signal, the second controller configured to transmit the request event in the request signal during a switching window of the switching window signal, the second controller further comprising: an extremum locator switching window generator configured to generate the switching window signal in response to a winding signal of the energy transfer element which oscillates in response to a completion of the transfer of energy to the output, the extremum locator switching window generator configured to generate the switching window corresponding with an extremum in the winding signal; and a measurement enable circuit configured to output an enable signal to enable the extremum locator switching window generator to measure a duration of a half cycle of a relaxation ring of the winding signal and to generate a half cycle reference utilized to generate the switching window of the switching window signal, the measurement enable circuit further configured to enable the extremum locator switching window generator in response to the feedback signal reaching a percentage of a target reference for regulating the output of the power converter, the measurement enable circuit further configured to output a quiet signal to prevent the second controller from transmitting the request event in the request signal in response to the quiet signal.

Example 2. The controller of example 1, wherein the enable signal is asserted when the feedback signal reaches the percentage of the target reference substantially with a turn-on of a rectifier.

Example 3. The controller of examples 2 or 3, wherein the rectifier is a synchronous rectifier (SR) and the enable signal is asserted with a synchronous on signal to turn on the synchronous rectifier, and the synchronous on signal is asserted when the winding signal falls below a synchronous rectifier (SR)-on threshold.

Example 4. The controller of any one of examples 1 to 3, wherein the SR-on threshold is substantially zero volts.

Example 5. The controller of any one of examples 1 to 4, wherein the quiet signal is asserted when the enable signal is asserted.

Example 6. The controller of any one of examples 1 to 5, the second controller further comprising: a discontinuous conduction mode (DCM) sense circuit coupled to receive the winding signal and configured to output a DCM signal in response to the winding signal, the DCM signal representative of the power converter operating in discontinuous conduction mode, the quiet signal asserted for at most a first duration after the DCM signal is asserted.

Example 7. The controller of any one of examples 1 to 6, wherein the quiet signal is deasserted when the first duration is completed or the enable signal is deasserted.

Example 8. The controller of any one of examples 1 to 7, wherein the first duration is a duration of a monostable multivibrator.

Example 9. The controller of any one of examples 1 to 8, the extremum locator switching window generator further comprising: a half cycle window circuit configured to output a half cycle signal representative of the duration of the half cycle of the relaxation ring in response to a DCM signal representative of the power converter operating in discontinuous conduction mode and a comparison between the winding signal and an output voltage of the power converter when the enable signal is asserted, the half cycle window circuit further configured to output a complete signal in response to the comparison of the winding signal and the output voltage; a timer coupled to receive the half cycle signal and configured to generate a half cycle voltage, the half cycle voltage representative of the duration of the half cycle of the relaxation ring in response to the half cycle signal; and a memory circuit coupled to receive the half cycle voltage and the complete signal, and configured to generate a half cycle reference in response to the half cycle voltage when the complete signal is asserted, the memory circuit further configured to output a ready signal indicating that the half cycle reference has been generated.

Example 10. The controller of any one of examples 1 to 9, wherein the half cycle window circuit is coupled to receive a trim signal, wherein the trim signal is representative of the second controller operating in either quasi-resonant control or zero-voltage control, wherein the half cycle window circuit outputs the half cycle signal in response to the winding signal being greater than the output voltage when the trim signal indicates quasi-resonant control and the switching window corresponds to peaks in the winding signal, and wherein the half cycle window circuit outputs the half cycle signal in response to the winding signal being less than the output voltage when the trim signal indicates zero-voltage control and the switching window corresponds to valleys in the winding signal.

Example 11. The controller of any one of examples 1 to 10, wherein when the trim signal indicates quasi-resonant control, the complete signal is asserted after the winding signal has crossed the output voltage twice after the DCM signal is asserted.

Example 12. The controller of any one of examples 1 to 11, wherein when the trim signal indicates zero-voltage control, the complete signal is asserted after the winding signal has crossed the output voltage three times after the DCM signal is asserted.

Example 13. The controller of any one of examples 1 to 12, the extremum locator switching window generator further comprising: a reference generator coupled to receive the half cycle reference and configured to generate a first reference and a second reference, wherein the switching window is generated in response to a comparison between the first reference and the half cycle voltage and a comparison between the second reference and the half cycle voltage.

Example 14. The controller of any one of examples 1 to 13, the second controller further comprising: an SR control and request circuit coupled to receive the winding signal and the switching window signal, the SR control and request circuit configured to generate the request event and the request signal in response to the feedback signal and the target reference, and to transmit the request event during the switching window of the switching window signal, the SR control and request circuit further configured to output a synchronous drive signal to control the switching of a synchronous rectifier coupled to the output of the power converter in response to the winding signal.

Example 15. The controller of any one of examples 1 to 16, wherein the first controller is configured to generate a clamp drive signal to control switching of a clamp switch of an active clamp circuit coupled across the energy transfer element, the first controller coupled to receive the request signal and further configured to generate the clamp drive signal in response to a request event in the request signal, wherein the first drive signal is outputted to turn on the power switch after the clamp drive signal is outputted to turn off the clamp switch.

Example 16. A method of determining a switching window for a request event in a request signal of a controller of a power converter, the method comprising: determining when a feedback signal representative of an output of the power converter is greater than a percentage of a target reference for regulating the output of the power converter; determining when a rectifier is turned on; enabling an extremum locator switching window generator to measure a duration of a half cycle of a relaxation ring of a winding signal representative of an output winding of an energy transfer element and to generate a half cycle reference; generating a quiet signal to prevent a power switch from turning on; determining that the power converter is operating in discontinuous conduction mode; measuring the duration of the half cycle by a switching window generator by comparing the winding signal to an output voltage of the power converter after determining that the power converter is operating in discontinuous conduction mode; storing the half cycle reference in response to the completion of the duration of the half cycle of the relaxation ring; and utilizing the half cycle reference to determine the switching window.

Example 17. The method of example 16, further comprising: asserting the quiet signal to prevent the turn on of the power switch from occurring after the enabling of the extremum locator switching window generator to measure the duration of the half cycle; triggering a mono stable multivibrator to continue asserting the quiet signal after determining that the power converter is operating in discontinuous conduction mode; and deasserting the quiet signal to allow turn on of the power switch after the triggering of the mono stable multivibrator has ended.

Example 18. The method of examples 16 or 17 wherein enabling an extremum locator switching window generator further comprises: synchronizing the enabling of the extremum locator switching generator when the feedback signal is greater than the percentage of the target reference corresponding with the determining that the rectifier is turned on.