SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device according to an embodiment includes first to ninth conductive layers, first and second insulating members, and first to fourth pillars. A distance between the first and second pillars in a cross section including the second conductive layer and the sixth conductive layer is smaller than a distance between the first and second pillars in a cross section including the third conductive layer and the seventh conductive layer. A distance between the third and fourth pillars in a cross section including the fourth conductive layer and the eighth conductive layer is greater than a distance between the third and fourth pillars in a cross section including the fifth conductive layer and the ninth conductive layer.

FIELD

An embodiment relates to a semiconductor memory device.

BACKGROUND

A NAND-type flash memory capable of storing data in a non-volatile manner is known.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor memory device includes first to ninth conductive layers, first and second insulating members, and first to fourth pillars. The second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer are stacked above the first conductive layer to be separated from each other in a first direction. The sixth conductive layer, a seventh conductive layer, an eighth conductive layer, and a ninth conductive layer are stacked above the first conductive layer, and are respectively provided in same layers as the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer, to be separated from the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in a second direction intersecting the first direction. The first insulating member is provided along the first direction, and comprises a portion provided between the second conductive layer and the sixth conductive layer and a portion provided between the third conductive layer and the seventh conductive layer. The second insulating member is provided along the first direction above the first insulating member, and comprises a portion provided between the fourth conductive layer and the eighth conductive layer and a portion provided between the fifth conductive layer and the ninth conductive layer. The first pillar and a second pillar are in contact with the second conductive layer, the third conductive layer, the sixth conductive layer, and the seventh conductive layer. The first pillar and the second pillar are provided to sandwich the first insulating member in a third direction intersecting both the first direction and the second direction. The third pillar and a fourth pillar are in contact with the fourth conductive layer, the fifth conductive layer, the eighth conductive layer, and the ninth conductive layer. The third pillar and the fourth pillar are provided to sandwich the second insulating member in the third direction. The first pillar is provided along the first insulating member, and comprises a first semiconductor layer coupled to the first conductive layer. The second pillar is provided along the first insulating member, and comprises a second semiconductor layer coupled to the first conductive layer. The third pillar is provided along the second insulating member, and comprises a third semiconductor layer coupled to the first semiconductor layer. The fourth pillar is provided along the second insulating member, and comprises a fourth semiconductor layer coupled to the second semiconductor layer. A distance between the first pillar and the second pillar in the third direction in a cross section including the second conductive layer and the sixth conductive layer is smaller than a distance between the first pillar and the second pillar in the third direction in a cross section including the third conductive layer and the seventh conductive layer. A distance between the third pillar and the fourth pillar in the third direction in a cross section including the fourth conductive layer and the eighth conductive layer is greater than a distance between the third pillar and the fourth pillar in the third direction in a cross section including the fifth conductive layer and the ninth conductive layer.

Hereinafter, an embodiment will be described with reference to the drawings. The embodiment exemplifies a device and a method for embodying the technical idea of the invention. The drawings are schematic or conceptual, and the dimensions, ratios, and the like in each drawing are not necessarily the same as actual ones. The technical idea of the present invention is not specified by the shapes, structures, arrangements, and the like of the constituent elements.

Note that, in the following description, constituent elements having substantially the same functions and configurations are denoted by the same symbols. Numbers after the letters constituting the reference symbols are referred to by reference symbols including the same letters, and are used to differentiate elements having similar configurations from each other. Similarly, letters after the numbers constituting the reference symbols are referred to by reference symbols including the same numbers, and are used to differentiate elements having similar configurations from each other. In a case where it is not necessary to differentiate elements denoted by reference symbols including the same letters or numbers from each other, each of these elements is referred to by the reference symbol including only the letters or the numbers.

Embodiment

Hereinafter, a semiconductor memory device1according to an embodiment will be described.

<1-1> Overall Configuration of Semiconductor Memory Device1

FIG.1illustrates a configuration example of the semiconductor memory device1according to the embodiment. The semiconductor memory device1is a NAND-type flash memory capable of storing data in a non-volatile manner, and can be controlled by an external memory controller2.

As illustrated inFIG.1, the semiconductor memory device1includes, for example, a memory cell array10, a command register11, an address register12, a sequencer13, a driver module14, a row decoder module15, and a sense amplifier module16.

The memory cell array10includes a plurality of blocks BLK0to BLKn (n being an integer of 1 or more). The block BLK is a set of a plurality of memory cells capable of storing data in a non-volatile manner, and is used as, for example, an erase unit of data. A plurality of bit lines and a plurality of word lines are provided in the memory cell array10. Each memory cell is associated with, for example, one bit line and one word line. A configuration of the memory cell array10will be described in detail later.

The command register11holds a command CMD that the semiconductor memory device1received from the memory controller2. The command CMD includes, for example, a command for causing the sequencer13to execute a read operation, a write operation, an erase operation, and the like.

The address register12holds address information ADD that the semiconductor memory device1received from the memory controller2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used for selecting a block BLK, a word line, and a bit line, respectively.

The sequencer13controls the overall operation of the semiconductor memory device1. For example, the sequencer13controls the driver module14, the row decoder module15, the sense amplifier module16, and the like based on the command CMD held in the command register11to execute the read operation, the write operation, the erase operation, and the like.

The driver module14generates a voltage used in the read operation, the write operation, the erase operation, and the like. Then, for example, the driver module14applies the generated voltage to a signal line corresponding to the word line selected based on the page address PAd held in the address register12.

The row decoder module15selects one block BLK in the corresponding memory cell array10based on the block address BAd held in the address register12. Then, the row decoder module15transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

In the write operation, the sense amplifier module16applies a predetermined voltage to each bit line according to write data DAT received from the memory controller2. In the read operation, the sense amplifier module16determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result as read data DAT to the memory controller2.

The semiconductor memory device1and the memory controller2described above may constitute one semiconductor device by combination thereof. As such a semiconductor device, for example, a memory card such as an SD™ card, a solid state drive (SSD), and the like are named.

<1-2> Circuit Configuration of Memory Cell Array10

FIG.2illustrates an example of a circuit configuration of the memory cell array10included in the semiconductor memory device1according to the embodiment. Each block BLK includes, for example, four string units SU0to SU3, and two string units SU0and SU1included in the same block BLK are depicted inFIG.2.

As illustrated inFIG.2, each string unit SU includes a plurality of memory groups MG. The plurality of memory groups MG are associated with bit lines BL0to BLm (m being an integer of 1 or more), respectively. Each memory group MG includes two NAND strings NSa and NSb. The NAND string NSa includes memory cell transistors MCa0to MCa7and select transistors STa1and STa2. The NAND string NSb includes memory cell transistors MCb0to MCb7and select transistors STb1and STb2.

The select transistors STa1and STb1and the select transistors STa2and STb2are each used for selecting each of the string units SU and the NAND strings NS. The memory cell transistors MCa and MCb each include a control gate and a charge storage layer, and hold data in a non-volatile manner. Hereinafter, an example of a specific coupling state of elements in the memory group MG will be described by focusing on one memory group MG.

In the NAND string NSa, the memory cell transistors MCa0to MCa7are coupled in series. A source of the select transistor STa1is coupled to one end of the memory cell transistors MCa0to MCa7coupled in series. The other end of the memory cell transistors MCa0to MCa7coupled in series is coupled to a drain of the select transistor STa2.

In the NAND string NSb, the memory cell transistors MCb0to MCb7are coupled in series. A source of the select transistor STb1is coupled to one end of the memory cell transistors MCb0to MCb7coupled in series. The other end of the memory cell transistors MCb0to MCb7coupled in series is coupled to a drain of the select transistor STb2.

Drains of the select transistors STa1and STb1are each coupled to the bit line BL associated with the memory group MG. Sources of the select transistors STa2and STb2are each coupled to a source line SL.

Gates of a plurality of the select transistors STa1included in the same block BLK are each coupled to a common select gate line SGDa for each string unit SU. Specifically, the select transistors STa1included in the string unit SU0are coupled to a select gate line SGDa0. The select transistors STa1included in the string unit SU1are coupled to a select gate line SGDa1. Similarly, the select transistors STa1included in the string units SU2and SU3(not illustrated) are coupled to select gate lines SGDa2and SGDa3, respectively.

Gates of a plurality of the select transistors STb1included in the same block BLK are each coupled to a common select gate line SGDb for each string unit SU. Specifically, the select transistors STb1included in the string unit SU0are coupled to a select gate line SGDb0. The select transistors STb1included in the string unit SU1are coupled to a select gate line SGDb1. Similarly, the select transistors STb1included in the string units SU2and SU3(not illustrated) are coupled to select gate lines SGDb2and SGDb3, respectively.

The respective control gates of the memory cell transistors MCa0to MCa7included in the same block BLK are coupled to word lines WLa0to WLa7, respectively. The respective control gates of the memory cell transistors MCb0to MCb7included in the same block BLK are coupled to word lines WLb0to WLb7, respectively.

Gates of a plurality of the select transistors STa2included in the same block BLK are each coupled to a select gate line SGSa. Gates of a plurality of the select transistors STb2included in the same block BLK are each coupled to a select gate line SGSb.

In the circuit configuration of the memory cell array described above, the bit line BL is shared by, for example, the memory groups MG (sets of the NAND strings NSa and NSb) to which the same column address is assigned. The source line SL is shared among, for example, the plurality of blocks BLK. The word lines WLa and WLb, the select gate lines SGDa and SGDb, and the select gate lines SGSa and SGSb may each be independently controlled.

Note that, in the above description, a case has been exemplified where the select gate lines SGDa0to SGDa3and SGDb0to SGDb3are independent of each other, but there may be a case where the select gate line SGD may be shared between adjacent string units SU. In this case, for example, functions of two types of select gate lines SGD from among the select gate lines SGDa0to SGDa3and SGDb0to SGDb3may be assigned to one interconnect corresponding to the select gate line SGD. Alternatively, a function of one type of select gate line SGD may be assigned to two or more interconnects.

<1-3> Structure of Memory Cell Array10

Hereinafter, an example of the structure of the memory cell array10included in the semiconductor memory device1according to the embodiment will be described. Note that, in the drawings referred to below, an X direction corresponds to an extending direction of the word lines WL, a Y direction corresponds to an extending direction of the bit lines BL, and a Z direction corresponds to a vertical direction with respect to a surface of a semiconductor substrate20used for forming the semiconductor memory device1. Hatching is appropriately added in plan views to make the drawings easier to see. The hatching added in the plan views is not necessarily related to materials or characteristics of constituent elements to which the hatching is added.

(Planar Layout of Memory Cell Array10)

FIG.3illustrates an example of a planar layout of the memory cell array10included in the semiconductor memory device1according to the embodiment by focusing on the select gate lines SGDa and SGDb. InFIG.3, a region corresponding to three blocks BLK0to BLK2arranged in order is extracted.

As illustrated inFIG.3, the region of the memory cell array10includes a cell region CA and replacement regions RA1and RA2. In addition, the memory cell array10includes a plurality of memory trenches MT, a plurality of memory pillars MP, and a plurality of replacement holes STH.

The cell region CA and the replacement regions RA1and RA2are each a region extending in the Y direction. The cell region CA is sandwiched between the replacement regions RA1and RA2in the X direction. The select gate lines SGDa and SGDb each include a portion extending along the X direction, and cross the cell region CA and the replacement regions RA1and RA2. The select gate lines SGDa and SGDb are alternately arranged in the Y direction.

Each memory trench MT is arranged between adjacent select gate lines SGDa and SGDb. The memory trench MT includes a portion extending along the X direction, and separates interconnect layers adjacent in the Y direction. The memory trench MT is filled with, for example, an insulator.

Each memory pillar MP functions as the memory group MG, and is arranged to overlap one memory trench MT in the cell region CA. Each memory pillar MP divides the overlapping memory trench MT, and is in contact with each of the select gate lines SGDa and SGDb adjacent to the divided memory trench MT. Portions where the memory pillars MP and the select gate lines SGDa face each other function as the select transistors STa1. Portions where the memory pillars MP and the select gate lines SGDb face each other function as the select transistors STb1.

At least one bit line BL is provided to overlap each memory pillar MP, and the one bit line BL is electrically coupled to the memory pillar MP. In a region corresponding to each block BLK, a plurality of memory pillars MP are arranged in four rows in a staggered manner, for example. The memory trench MT where the memory pillars MP do not overlap is arranged at a boundary portion between adjacent blocks BLK. In other words, the memory cell array10is divided into units of blocks BLK by being partitioned by the memory trenches MT where the memory pillars MP do not overlap.

Each replacement hole STH is used at the time of forming stacked interconnects. For example, the plurality of replacement holes STH include replacement holes STH arranged to overlap memory trenches MT at even-number-th rows (even-number-th memory trenches MT) in the replacement region RA1, and replacement holes STH arranged to overlap memory trenches MT at odd-number-th rows (odd-number-th memory trenches MT) in the replacement region RA2. Each replacement hole STH divides the overlapping memory trench MT, and is in contact with each of the select gate lines SGDa and SGDb adjacent to the divided memory trench MT. The replacement hole STH is filled with, for example, an insulator.

FIG.4illustrates an example of a planar layout of the memory cell array10included in the semiconductor memory device1according to the embodiment by focusing on the word lines WLa and WLb. InFIG.4, a region including the blocks BLK0to BLK2is extracted.

As illustrated inFIG.4, the word lines WLa and WLb each include a portion extending along the X direction, and cross the cell region CA and the replacement regions RA1and RA2. The word lines WLa and WLb are alternately arranged in the Y direction. The memory trenches MT are arranged between the word lines WLa and WLb.

The word lines WLa and WLb each include portions in contact with each of the memory pillars MP and the replacement holes STH. Portions where the memory pillars MP and the word lines WLa face each other function as the memory cell transistors MCa. Portions where the memory pillars MP and the word lines WLb face each other function as the memory cell transistors MCb.

The word lines WLa and the word lines WLb each have a structure in which their ends are electrically coupled to each other for each block BLK in a region not illustrated. For example, the word lines WL in the block BLK are electrically coupled by providing the word lines WL in a comb shape. The coupling is not limited thereto, and the word lines WL in the block BLK may be electrically coupled by coupling a set of line-shaped word lines WL via different interconnect layers.

(Cross-Sectional Structure of Memory Cell Array10)

FIG.5is a cross-sectional view taken along line V-V inFIG.4, and illustrates an example of a cross-sectional structure of the memory cell array10including the memory trench MT at the boundary portion between the blocks BLK0and BLK1and the memory pillars MP.

As illustrated inFIG.5, the memory cell array10includes, for example, conductive layers21to26, insulating layers30to37, and a plurality of contacts CV. Hereinafter, a cross-sectional structure of the memory cell array10will be described in detail in order from the lower layer.

The conductive layer21is provided above the semiconductor substrate20with the insulating layer30interposed therebetween. Although not illustrated, for example, a circuit such as the sense amplifier module16is provided inside the insulating layer30. The conductive layer21is formed in a plate shape spreading along an XY plane, for example, and is used as the source line SL. The conductive layer21contains, for example, silicon (Si) doped with phosphorous (P). The conductive layer21may include a plurality of types of semiconductor layers, or may include a metal layer.

The conductive layer22is provided above the conductive layer21with the insulating layer31interposed therebetween. The conductive layer22includes, for example, a portion provided to extend along the X direction, and is used as the select gate line SGS. The conductive layer22contains, for example, tungsten (W).

The insulating layers32and the conductive layers23are alternately stacked above the conductive layer22. The conductive layer23includes, for example, a portion provided to extend along the X direction. The plurality of stacked conductive layers23are used as the word lines WL0to WL3, respectively, in order from a semiconductor substrate20side. The conductive layer23contains, for example, tungsten (W).

The insulating layer33is provided above the uppermost conductive layer23. The insulating layer34is provided above the insulating layer33. The conductive layers24and the insulating layers35are alternately stacked above the insulating layer34. The conductive layer24includes, for example, a portion provided to extend along the X direction. The plurality of stacked conductive layers24are used as the word lines WL4to WL7, respectively, in order from the semiconductor substrate20side. The conductive layer24contains, for example, tungsten (W).

The conductive layer25is provided above the uppermost conductive layer24with the insulating layer35interposed therebetween. The conductive layer25includes, for example, a portion provided to extend along the X direction, and is used as the select gate line SGD. The conductive layer25contains, for example, tungsten (W).

The insulating layer36is provided above the conductive layer25. The conductive layer26is provided above the insulating layer36with the insulating layer37interposed therebetween. The conductive layer26includes, for example, a portion provided to extend along the Y direction, and is used as the bit line BL. That is, a plurality of conductive layers26are arrayed along the X direction in a region not illustrated. The conductive layer26contains, for example, copper (Cu).

The memory pillars MP are each provided to extend along the Z direction, and penetrate the conductive layers22to25and the insulating layers31to36. Specifically, the memory pillars MP each include, for example, a lower pillar LMP and an upper pillar UMP connected in the Z direction. Hereinafter, an example of a structure of the lower pillar LMP and the upper pillar UMP will be described by focusing on a set of the lower pillar LMP and the upper pillar UMP included in the same memory pillar MP.

The lower pillar LMP penetrates the conductive layers22and23and the insulating layers31to33. The lower pillar LMP includes a core member40, a semiconductor layer41, and a stacked film42. The core member40is provided to extend along the Z direction. The upper end of the core member40is included in a layer above the conductive layer23. The lower end of the core member40is included in a layer in which the conductive layer21is formed. The semiconductor layer41covers the periphery of the core member40. For example, the bottom of the semiconductor layer41is in contact with the conductive layer21. The stacked film42covers the side surface and the bottom surface of the semiconductor layer41except for the contact portion between the semiconductor layer41and the conductive layer21.

The upper pillar UMP penetrates the conductive layers24and25and the insulating layers34to36. The upper pillar UMP includes a core member50, a semiconductor layer51, and a stacked film52. The core member50is provided to extend along the Z direction. The upper end of the core member50is included in a layer above the conductive layer25. The lower end of the core member50is included, for example, in a layer in which the insulating layer34is formed. The semiconductor layer51covers the periphery of the core member50. For example, the bottom of the semiconductor layer51in the upper pillar UMP is in contact with the top of the semiconductor layer41in the lower pillar LMP. The stacked film52covers the side surface and the bottom surface of the semiconductor layer51except for the contact portion between the semiconductor layer41and the semiconductor layer51, for example.

A columnar contact CV is provided above the semiconductor layer51in the memory pillar MP. One conductive layer26(bit line BL) is in contact with the top of the contact CV. The memory pillars MP corresponding to the memory groups MG associated with the same column address are coupled to the common conductive layer26with the contacts CV interposed therebetween.

The memory trenches MT each divide the conductive layers22and23, the insulating layers31to33, conductive layers24and25, and the insulating layers34to36. As a result, the conductive layer22is separated into conductive layers22aand22bcorresponding to the select gate lines SGSa and SGSb, respectively. The conductive layers23are separated into conductive layers23aand23bcorresponding to the word lines WLa and WLb, respectively. The conductive layers24are separated into conductive layers24aand24bcorresponding to the word lines WLa and WLb, respectively. The conductive layer25is separated into conductive layers25aand25bcorresponding to the select gate lines SGDa and SGDb, respectively.

The memory trenches MT each include, for example, a lower trench LMT and an upper trench UMT arranged in the Z direction. Hereinafter, an example of a structure of the lower trench LMT and the upper trench UMT will be described by focusing on a set of the lower trench LMT and the upper trench UMT included in the same memory trench MT. Note that the lower trench LMT and the upper trench UMT may be in contact with each other, or may be separated from each other.

The lower trench LMT divides the conductive layers22and23and insulating layers31to33. The lower trench LMT includes insulating layers60and61. The insulating layer60is formed in a plate shape spreading along an XZ plane. The upper end of the insulating layer60is included in a layer above the conductive layer23. The lower end of the insulating layer60is included in a layer including the conductive layer21. The insulating layer61has a composition different from that of the insulating layer60, and is provided on the side surface of the insulating layer60. The insulating layer60, and the conductive layers22and23are separated with the insulating layer61interposed therebetween. In this manner, at least two types of insulating layers are provided in the lower trench LMT.

The upper trench UMT divides the conductive layers24and25and the insulating layers34to36. The upper trench UMT includes insulating layers70and71. The insulating layer70is formed in a plate shape spreading along the XZ plane. The upper end of the insulating layer70is included in a layer above the conductive layer25. The lower end of the insulating layer70is included in a layer between the conductive layer23and the conductive layer24. The insulating layer71has a composition different from that of the insulating layer70, and is provided on the side surface of the insulating layer70. The insulating layer70, and the conductive layers24and25are separated with the insulating layer71interposed therebetween. In this manner, at least two types of insulating layers are provided in the upper trench UMT.

Note that, in the structure of the memory cell array10described above, the total thickness of the insulating layers33and34including the joint portion between the lower pillar LMP and the upper pillar UMP is greater than that of the insulating layer32, and is greater than that of the insulating layer35. In other words, the distance between the uppermost conductive layer23aand the lowermost conductive layer24ain the Z direction is greater than the distance between adjacent conductive layers23a, and is greater than the distance between adjacent conductive layers24a.

In addition, a configuration for relaying the upper pillar UMP, the lower pillar LMP, and the joint portion may be provided between the upper pillar UMP and the lower pillar LMP. In each memory pillar MP, it suffices that at least the semiconductor layer51in the upper pillar UMP and the semiconductor layer41in the lower pillar LMP are electrically coupled to each other. An etching stopper for forming a structure corresponding to the upper pillar UMP may be provided between the insulating layer33and the insulating layer34.

FIG.6is a cross-sectional view taken along line VI-VI inFIG.4, and illustrates an example of a cross-sectional structure of the memory cell array10including the memory pillars MP and the replacement hole STH. Note that, in the semiconductor memory device1according to the embodiment, four memory pillars MP arranged in the X direction may be regarded as one set. Structures similar to the one set of the memory pillars MP are repeatedly arranged in the X direction. Hereinafter, the lower pillars LMP in the four memory pillars MP arranged in the X direction are referred to as “LMPo1”, “LMPe1”, “LMPo2”, and “LMPe2”, respectively, in order from one closest to the replacement hole STH. The upper pillars UMP in the four memory pillars MP arranged in the X direction are referred to as “UMPo1”, “UMPe1”, “UMPo2”, and “UMPe2”, respectively, in order from one closest to the replacement hole STH.

As illustrated inFIG.7, the lower trenches LMT are arranged between the lower pillars LMPo1and LMPe1, and between the lower pillars LMPo2and LMPe2, respectively. Holes LAH filled with insulators are arranged between the lower pillars LMPe1and LMPo2, and between the lower pillar LMPo1and the replacement hole STH.

The hole LAH is formed by removing portions of the insulating layers in the formed lower trench LMT. The hole LAH is used for forming the lower pillars LMP adjacent to the hole LAH. The memory cell array10is provided with a structure in which the holes LAH and the lower trenches LMT are alternately arranged in the X direction. Therefore, the lower pillars LMP are each arranged between the hole LAH and the lower trench LMT adjacent to each other.

Further, for example, in a cross section along the XZ plane, the hole LAH has a tapered shape, and the lower trench LMT has a reverse tapered shape. The lower pillar LMP arranged between the hole LAH and the lower trench LMT adjacent to each other has a shape along each of the hole LAH and the lower trench LMT adjacent to each other. The shape of the lower pillar LMP (for example, the inclination of the lower pillar LMP) is determined based on the shape of the hole LAH.

The upper trenches UMT are arranged between the upper pillar UMPe1and UMPo2, and between the upper pillar UMPo1and the replacement hole STH, respectively. Holes UAH filled with insulators are arranged between the upper pillars UMPo1and UMPe1, and between the upper pillars UMPo2and UMPe2.

The hole UAH is formed by removing portions of the insulating layers in the formed upper trench UMT. The hole UAH is used for forming the upper pillars UMP adjacent to the hole UAH. The memory cell array10is provided with a structure in which the holes UAH and the upper trenches UMT are alternately arranged in the X direction. Therefore, the upper pillars UMP are each arranged between the hole UAH and the upper trench UMT adjacent to each other.

Further, for example, in the cross section along the XZ plane, the hole UAH has a tapered shape, and the upper trench UMT has a reverse tapered shape. The upper pillar UMP arranged between the hole UAH and the upper trench UMT adjacent to each other has a shape along each of the hole UAH and the upper trench UMT adjacent to each other. The shape of the upper pillar UMP (for example, the inclination of the upper pillar UMP) is determined based on the shape of the hole UAH.

Further, the upper trench UMT is adjacent to the hole LAH in the Z direction. The hole UAH is adjacent to the lower trench LMT in the Z direction. That is, in plan view, the holes UAH and the holes LAH are arranged in a staggered manner in the X direction. Similarly, in plan view, the upper trenches UMT and the lower trenches LMT are arranged in a staggered manner in the X direction.

The replacement hole STH divides the memory trench MT (for example, the hole LAH and the upper trench UMT). The replacement hole STH is filled with an insulator. The upper end of the insulator in the replacement hole STH is in contact with the insulating layer37. The lower end of the insulator in the replacement hole STH is in contact with the conductive layer21.

Further, in a region not illustrated, the replacement hole STH is in contact with each of the conductive layers21,22a,22b,23a,23b,24a,24b,25a,25b, and26, and the insulating layers30to36. That is, the conductive layers22aand22badjacent to each other, the conductive layers23aand23badjacent to each other, the conductive layers24aand24badjacent to each other, and the conductive layers25aand25badjacent to each other are each electrically insulated from each other by a set of the insulators in the memory trench MT and the memory pillars MP that divide the insulators.

Further, in the semiconductor memory device1according to the embodiment, the memory trench MT divided by the replacement hole STH is provided to have a width in the X direction greater than those of the memory trenches MT provided in other regions. In this example, the hole LAH adjacent to the lower pillar LMPo1is provided to have a width in the X direction greater than those of other holes LAH, and the upper trench UMT adjacent to the upper pillar UMPo1is provided to have a width in the X direction greater than those of other upper trenches UMT. The replacement hole STH divides the set of the hole LAH and the upper trench UMT that have large widths.

FIG.7illustrates an example of a cross-sectional structure of the memory cell array10in the semiconductor memory device1according to the embodiment.FIG.7Acorresponds to a cross section parallel to the surface of the semiconductor substrate20and including the upper pillars UMP.FIG.7Bcorresponds to a cross section parallel to the surface of the semiconductor substrate20and including the lower pillars LMP.

As illustrated inFIG.7A, the upper pillars UMPo1, UMPe1, UMPo2, and UMPe2, and the replacement hole STH are each in contact with each of the word lines WLa and WLb. The stacked film52in the upper pillar UMP includes a tunnel insulating film53, an insulating film54, and a block insulating film55.

In the upper pillar UMP, the core member50is provided at the center of the upper pillar UMP. The semiconductor layer51surrounds the periphery of the core member50. The tunnel insulating film53surrounds the periphery of the semiconductor layer51. The insulating film54surrounds the periphery of the tunnel insulating film53. The block insulating film55surrounds the periphery of the insulating film54. The core member50includes, for example, an insulator such as silicon oxide. The semiconductor layer51contains, for example, silicon. The tunnel insulating film53and the block insulating film55each contain, for example, silicon oxide. The insulating film54contains, for example, silicon nitride.

The block insulating film55is in contact with each of the word lines WLa and WLb adjacent thereto. For example, the upper trench UMT divides portions of the insulating films54and portions of the block insulating films55in the contacting upper pillars UMP, and is in contact with the tunnel insulating films53. The hole UAH divides portions of the insulating films54and portions of the block insulating films55in the contacting upper pillars UMP, and is in contact with the tunnel insulating films53. Therefore, in this example, in each upper pillar UMP, a set of the insulating film54and the block insulating film55that is provided on a word line WLa side, and a set of the insulating film54and the block insulating film55that is provided on a word line WLb side are separated from each other.

As illustrated inFIG.7B, the lower pillars LMPo1, LMPe1, LMPo2, and LMPe2, and the replacement hole STH are each in contact with each of the word lines WLa and WLb. The stacked film42in the lower pillar LMP includes a tunnel insulating film43, an insulating film44, and a block insulating film45.

In the lower pillar LMP, the core member40is provided at the center of the lower pillar LMP. The semiconductor layer41surrounds the periphery of the core member40. The tunnel insulating film43surrounds the periphery of the semiconductor layer41. The insulating film44surrounds the periphery of the tunnel insulating film43. The block insulating film45surrounds the periphery of the insulating film44. The core member40includes, for example, an insulator such as silicon oxide. The semiconductor layer41contains, for example, silicon. The tunnel insulating film43and the block insulating film45each contain, for example, silicon oxide. The insulating film44contains, for example, silicon nitride.

The block insulating film45is in contact with each of the word lines WLa and WLb adjacent thereto. For example, the lower trench LMT divides portions of the insulating films44and portions of the block insulating films45in the contacting lower pillars LMP, and is in contact with the tunnel insulating films43. The hole LAH divides portions of the insulating films44and portions of the block insulating films45in the contacting lower pillars LMP, and is in contact with the tunnel insulating films43. Therefore, in this example, in each lower pillar LMP, a set of the insulating film44and the block insulating film45that is provided on the word line WLa side, and a set of the insulating film44and the block insulating film45that is provided on the word line WLb side are separated from each other.

In the semiconductor memory device1according to the embodiment described above, the memory cell transistors MCa and MCb use the insulating film44or54as a charge storage layer. The memory cell transistors MCa and MCb, and the select transistors STa1, STb1, STa2, and STb2share channels (semiconductor layers41and51). A set of the select transistors STa1and STa2and the memory cell transistors MCa0to MCa7that are arranged in the Z direction corresponds to the NAND string NSa. A set of the select transistors STb1and STb2and the memory cell transistors MCb0to MCb7that are arranged in the Z direction corresponds to the NAND string NSb.

Further, in the direction parallel to the surface of the semiconductor substrate20(for example, the Y direction), the memory cell transistors MCa0to MCa7respectively face the memory cell transistors MCb0to MCb7, and the select transistors STa1and STa2respectively face the select transistors STb1and STb2. In other words, the memory cell transistors MCa0to MCa7and the memory cell transistors MCb0to MCb7are respectively adjacent to each other, and the select transistors STa1and STa2and the select transistors STb1and STb2are respectively adjacent to each other, with the region divided by the memory trench MT interposed therebetween.

<2> Manufacturing Method

Hereinafter, a method of forming the memory pillar MP in the semiconductor memory device1according to the embodiment will be briefly described using manufacturing steps related to the lower pillar LMP as examples, with reference toFIGS.8to10.FIG.8illustrates an example of a flow of the method of forming the memory cell array10in the semiconductor memory device1according to the embodiment.FIGS.9and10illustrate examples of cross-sectional structures of the memory cell array10in the process of manufacturing the semiconductor memory device1according to the embodiment.FIGS.9and10depict regions similar to those inFIGS.6and7, respectively.

First, sacrificial members SM and insulating layers are alternately stacked. Then, as illustrated inFIG.8(1), a lower trench LMT that divides the sacrificial member SM is formed, and the insulating layers61and60are formed in this order in the lower trench LMT. Note that, inFIG.8, in the divided sacrificial member SM, a portion corresponding to the word line WLa side is indicated as “SM1”, and a portion corresponding to the word line WLb side is indicated as “SM2”.

Next, as illustrated inFIG.8(2), a hole LAH that divides the lower trench LMT is formed. It suffices that the space formed by the hole LAH is in contact with at least each of the insulating layers61, of the corresponding lower trench LMT, provided on both sides in the Y direction. Then, as illustrated inFIG.8(3), portions of the insulating layers61in the lower trench LMT are selectively removed through the hole LAH. In this step, for example, wet etching is performed under a condition that increases the etching selectivity between the insulating layer60and the insulating layer61. As a result, four recesses RP1are formed for each hole LAH.

Next, as illustrated inFIG.8(4), a sacrificial member80is formed in each recess RP1. Briefly, first, the sacrificial member80is formed in the hole LAH. Then, the sacrificial member80in the hole LAH is removed to separate the sacrificial members80in the recesses RP1from each other. As the sacrificial member80, for example, polysilicon is used. Then, as illustrated inFIG.8(5), the hole LAH is filled with an insulator81. As the insulator81, for example, a silicon oxide film is used.

Next, as illustrated inFIG.8(6), the sacrificial members80in the recesses RP1are selectively removed. In this step, for example, wet etching is performed under a condition that increases the etching selectivity between the sacrificial member80and each of the sacrificial members SM and other insulating layers. As a result, four spaces of the recesses RP1are formed adjacent to the hole LAH filled with the insulator81.

Next, as illustrated inFIG.8(7), memory holes MH including recesses RP2are formed. Briefly, first, portions of the sacrificial members SM1and SM2are selectively removed through the recesses RP1to form the recesses RP2. The recess RP2is provided so as not to be in contact with at least the recess RP2adjacent in the X direction. Then, the insulating layer60between the recesses RP2adjacent in the Y direction is selectively removed to form the memory hole MH including two recesses RP2adjacent in the Y direction.

Next, as illustrated inFIG.8(8), the block insulating films45and the insulating films44are formed in the recesses RP2. Briefly, first, the block insulating film45and the insulating film44are formed in this order in the memory hole MH. Then, the block insulating film45and the insulating film44formed in a region intersecting the lower trench LMT are removed. As a result, the block insulating films45and the insulating films44in the recesses RP2adjacent in the Y direction are separated from each other.

Next, as illustrated inFIG.8(9), the tunnel insulating films43, the semiconductor layers41, and the core members40are formed in this order in the memory holes MH. As a result, a layer structure corresponding to the memory cell transistor MCa and a layer structure corresponding to the memory cell transistor MCb are provided in each memory hole MH.

Structural bodies corresponding to the upper pillars UMP are similarly formed above structural bodies corresponding to the lower pillars LMP formed by the steps described above. Note that the steps corresponding to the lower pillar LMP and the steps corresponding to the upper pillar UMP are different mainly in that the holes LAH and the holes UAH are arranged in a staggered manner in plan view.

Thereafter, as illustrated inFIG.9, for example, the replacement hole STH penetrating the upper trench UMT and the insulator81in the hole LAH is formed. As illustrated inFIG.10, the replacement hole STH is formed so as to be in contact with each of the sacrificial members SM1and SM2corresponding to the upper pillar UMP and the sacrificial members SM1and SM2corresponding to the lower pillar LMP.

Then, although not illustrated, a process of replacing the stacked interconnects is performed. Briefly, first, the sacrificial members SM1and SM2are selectively removed through the replacement hole STH. Then, the spaces, from which the sacrificial members SM1and SM2are removed, are filled with conductors through the replacement hole STH. For example, the sacrificial member SM1is replaced with the conductive layer23a, and the sacrificial member SM2is replaced with the conductive layer23b. Thereafter, the conductors formed in the replacement hole STH are removed and the replacement hole STH is filled with an insulator. As a result, a plurality of conductive layers corresponding to the word lines WLa and WLb, and the select gate lines SGSa, SGSb, SGDa, and SGDb, respectively, are formed.

The memory pillars MP in the semiconductor memory device1according to the embodiment may be formed as described above. Note that the method of manufacturing the memory pillar MP described above is merely an example. For example, in a case where the arrangement of the holes LAH and the holes UAH is opposite in plan view, the replacement hole STH is provided so as to penetrate the insulator in the hole UAH and the insulator in the lower trench LMT. Further, the manufacturing method may be appropriately changed depending on the structure of the memory pillar MP. In the semiconductor memory device1according to the embodiment, it suffices that at least the holes LAH and the holes UAH are arranged in a staggered manner in plan view.

<3> Advantageous Effects of Embodiment

According to the semiconductor memory device1of the embodiment described above, a chip area of the semiconductor memory device1can be reduced. Hereinafter, advantageous effects of the semiconductor memory device1according to the embodiment will be described in detail.

In a semiconductor memory device in which memory cells are three-dimensionally stacked, it is conceivable to operate the semiconductor memory device by dividing the memory pillar MP into two regions in order to improve the storage density. For example, the semiconductor memory device can cause one memory pillar MP to function as two NAND strings NSa and NSb by independently controlling stacked interconnects such as word lines WL, which are in contact with the memory pillar MP and are divided into two. In such a semiconductor memory device, memory trenches MT are formed in order to divide the stacked interconnects.

As a method of improving the storage density, it is also conceivable to connect a plurality of memory pillars in the Z direction. In this method, the number of stacked memory cells can be increased by the plurality of connected memory pillars. In addition, since the processing of the memory pillars is divided into a plurality of times, the difficulty of deep hole processing for forming the memory holes MH may also be reduced.

In addition, as a method of improving the storage density, it is conceivable to form two memory holes MH from one hole AH using a memory trench MT. In this method, memory pillars MP can be arranged more densely than a processing pitch by lithography and etching. Connecting the plurality of memory pillars in the Z direction and forming two memory holes MH from one hole AH may be combined. Hereinafter, an example of a case where these methods are combined will be briefly described.

FIGS.11and12illustrate examples of cross-sectional structures of a memory cell array10in a semiconductor memory device according to a comparative example of the embodiment.FIG.11corresponds to a cross section perpendicular to a surface of a semiconductor substrate20, and depicts a region similar to that inFIG.6.FIG.12corresponds to a cross section parallel to the surface of the semiconductor substrate20, and depicts a region similar to that inFIG.7.

As illustrated inFIG.11, the semiconductor memory device according to the comparative example of the embodiment has a structure in which holes LAH and holes UAH are arranged to overlap in a Z direction, and lower trenches LMT and upper trenches UMT are arranged to overlap in the Z direction. Lower pillars LMP and upper pillars UMP are provided along the holes LAH and UAH, respectively. In this example, the lower trenches LMT and the upper trenches UMT, and the holes LAH and UAH each have a large taper.

As illustrated inFIG.12A, in a case where the upper trench UMT has a taper, the width of the upper trench UMT is smaller in a cross section including the lower portion of the upper pillar UMP than in a cross section including the upper portion of the upper pillar UMP. Further, arrangement of the upper pillars UMPo and UMPe may be changed depending on the position and the size of the holes UAH. As a result, the set of the upper pillars UMPo and UMPe is closer together as the hole UAH width is smaller, and is smaller as the upper trench UMT width is narrower.

In other words, the distance between two upper pillars UMP arranged on both sides of the hole UAH and the distance between two upper pillars UMP arranged between the adjacent holes UAH are changed depending on the change in shape of the holes UAH. For example, in the upper portion of the hole UAH, the distance between the two upper pillars UMP arranged on both sides of the hole UAH is large, and the distance between the two upper pillars UMP arranged between the adjacent holes UAH is small. On the other hand, in the lower portion of the hole UAH, the distance between the two upper pillars UMP arranged on both sides of the hole UAH is small, and the distance between the two upper pillars UMP arranged between the adjacent holes UAH is large.

Such a change in distance may similarly occur in the lower pillars LMPo and LMPe as illustrated inFIG.12B. Therefore, in a case where the holes UAH and the holes LAH have tapers with similar tendencies, overlay misalignment may occur at joint portions between the upper pillars UMP and the lower pillars LMP. Usually, the overlay misalignment is suppressed by aligning the structural body in an upper layer with respect to the structural body in a lower layer.

However, in the case where two memory holes MH are formed from one hole AH, and the holes UAH and holes LAH overlap each other, unconformity occurs between the shift direction of the joint position in the lower portion of the upper pillar UMP and the shift direction of the joint position in the upper portion of the lower pillar LMP. Such overlay misalignment cannot be resolved by simple alignment. Therefore, in the semiconductor memory device according to the comparative example of the embodiment, it is necessary to relax each of the pitch of the lower pillars LMP in the X direction and the pitch of the upper pillars UMP in the X direction in order to couple channels of the lower pillars LMP and channels of the upper pillars UMP. As a result, in the semiconductor memory device according to the comparative example of the embodiment, the area of the memory cell array10increases, so that the chip area may increase.

On the other hand, the semiconductor memory device1according to the embodiment has a structure in which the holes LAH corresponding to the lower pillars LMP and the holes UAH corresponding to the upper pillars UMP are provided in a staggered manner in the extending direction of the memory trench MT in plan view (for example, in the X direction). Here, a case will be described where the semiconductor memory device1according to the embodiment includes memory pillars MP having a large taper as in the comparative example with reference toFIGS.13and14.

FIGS.13and14illustrate examples of cross-sectional structures of the memory cell array10in the semiconductor memory device1according to the embodiment.FIG.13corresponds to a cross section perpendicular to the surface of the semiconductor substrate20, and depicts a region similar to that inFIG.6.FIG.14corresponds to a cross section parallel to the surface of the semiconductor substrate20, and depicts a region similar to that inFIG.7.

As illustrated inFIG.13, the semiconductor memory device1according to the embodiment has a structure in which the holes LAH and the upper trenches UMT are arranged to overlap in the Z direction, and the lower trenches LMT and the holes UAH are arranged to overlap in the Z direction. That is, the holes LAH and the holes UAH are arranged in a staggered manner in plan view. In other words, in the semiconductor memory device1according to the embodiment, the pitch of the holes LAH corresponding to the lower pillars LMP and the pitch of the holes UAH corresponding to the upper pillars UMP are shifted by 0.5 pitches. As a result, a direction in which the upper pillars UMPo are inclined and a direction in which the lower pillars LMPo are inclined are opposite, and a direction in which the upper pillars UMPe are inclined and a direction in which the lower pillars LMPe are inclined are opposite.

As a result, as illustrated inFIG.14, the semiconductor memory device1according to the embodiment can suppress the overlay misalignment due to non-uniform pitch change in the upper pillars UMP and non-uniform pitch change in the lower pillars LMP. Further, in the semiconductor memory device1according to the embodiment, the lower trenches LMT and the upper trenches UMT, and the holes LAH and UAH can each be arranged without relaxing each of the pitch of the lower pillars LMP in the X direction and the pitch of the upper pillars UMP in the X direction.

As described above, in the semiconductor memory device1according to the embodiment, the margin of the overlay can be reduced compared to the comparative example, and the pitch of the memory pillars MP can be reduced compared to the comparative example. Therefore, in the semiconductor memory device1according to the embodiment, the circuit area of the memory cell array10can be reduced, and the chip area of the semiconductor memory device1can be reduced.

<4> Modifications of Embodiment

The configuration of the semiconductor memory device1according to the embodiment described above can be variously modified. Hereinafter, a first modification and a second modification of the embodiment will be described in order.

<4-1> First Modification

FIG.15illustrates an example of a cross-sectional structure of a memory cell array10in a semiconductor memory device1according to a first modification of the embodiment, and depicts a region similar to that inFIG.6. As illustrated inFIG.15, the semiconductor memory device1according to the first modification of the embodiment is different from the semiconductor memory device1according to the embodiment in the structure of joint portions between lower pillars LMP and upper pillars UMP.

Specifically, in each memory pillar MP in the first modification of the embodiment, a core member40, a semiconductor layer41, and a stacked film42are each continuously provided between the lower pillar LMP and the upper pillar UMP. A contact CV is coupled to the upper surface of the semiconductor layer41in the upper pillar UMP. Other structures of the semiconductor memory device1according to the first modification of the embodiment are similar to those in the embodiment.

Here, an example of a method for forming such a structure will be briefly described. For example, first, the steps inFIGS.8(1) to (5) corresponding to the lower pillars LMP are performed. That is, recesses RP1corresponding to the lower pillars LMP are formed, so that the structure in which holes LAH are filled with insulators81is formed. Then, the steps inFIGS.8(1) to (5) corresponding to the upper pillars UMP are performed. That is, recesses RP1corresponding to the upper pillars UMP are formed, so that the structure in which holes UAH are filled with insulators81is formed. Thereafter, the steps inFIGS.8(6) to (9) are performed with respect to each of the lower pillars LMP and the upper pillars UMP. As a result, a structure in which channels of the lower pillars LMP and channels of the upper pillars UMP are continuously provided may be formed.

As described above, the semiconductor memory device1according to the first modification of the embodiment has a structure in which the joint portions between the lower pillars LMP and the upper pillars UMP are different from those in the embodiment. Even in such a case, the semiconductor memory device1according to the first modification of the embodiment can acquire similar advantageous effects as those of the embodiment, and the chip area of the semiconductor memory device1can be reduced.

Note that, in the first modification of the embodiment, it suffices that at least one layer continuously formed between the lower pillar LMP and the upper pillar UMP is included. In order to improve the characteristics of NAND string NS, it is preferable that the channel (for example, the semiconductor layer41) be continuously provided between the lower pillar LMP and the upper pillar UMP. In the semiconductor memory device according to the comparative example of the embodiment, the channel resistance of the NAND string NS can be reduced by providing the channel as an integral semiconductor layer, so that the power consumption of the semiconductor memory device1can be suppressed.

<4-2> Second Modification

FIGS.16and17illustrate examples of cross-sectional structures of a memory cell array10in a semiconductor memory device1according to a second modification of the embodiment.FIG.16corresponds to a cross section perpendicular to a surface of a semiconductor substrate20, and depicts a region similar to that inFIG.6.FIG.17corresponds to a cross section parallel to the surface of the semiconductor substrate20, and depicts a region similar to that inFIG.7. In the semiconductor memory device1according to the second modification of the embodiment, four memory pillars MP arranged in an X direction may be regarded as one set as in the embodiment.

As illustrated inFIG.16, in the semiconductor memory device1according to the second modification of the embodiment, the memory pillar MP has a structure in which pillars MP1to MP4are connected in a Z direction. Hereinafter, among a plurality of pillars MP1arranged in the X direction, odd-number-th arranged pillars MP1from a replacement hole STH are referred to as “MP1o”, and even-number-th arranged pillars MP1from the replacement hole STH are referred to as “MP1e”. Similarly, a plurality of pillars MP2include odd-number-th arranged pillars MP2o, and even-number-th arranged pillars MP2e. A plurality of pillars MP3include odd-number-th arranged pillars MP3o, and even-number-th arranged pillars MP3e. A plurality of pillars MP4include odd-number-th arranged pillars MP4o, and even-number-th arranged pillars MP4e.

In addition, hereinafter, memory trenches MT and holes AH corresponding to the layer provided with the pillars MP1are referred to as “MT1” and “AH1”, respectively. Memory trenches MT and holes AH corresponding to the layer provided with the pillars MP2are referred to as “MT2” and “AH2”, respectively. Memory trenches MT and holes AH corresponding to the layer provided with the pillars MP3are referred to as “MT3” and “AH3”, respectively. Memory trenches MT and holes AH corresponding to the layer provided with the pillars MP4are referred to as “MT4” and “AH4”, respectively.

In the semiconductor memory device1according to the second modification of the embodiment, the holes AH2are provided above the memory trenches MT1. The memory trenches MT3are provided above the holes AH2. The holes AH4are provided above the memory trenches MT3. That is, the memory trench MT1, the hole AH2, the memory trench MT3, and the hole AH4are arranged in the Z direction.

On the other hand, the memory trenches MT2are provided above the holes AH1. The holes AH3are provided above the memory trenches MT2. The memory trenches MT4are provided above the holes AH3. That is, the hole AH1, the memory trench MT2, the hole AH3, and the memory trench MT3are arranged in the Z direction.

In addition, the pillars MP1oand MP1eare provided in a shape along the holes AH1. The pillars MP2oand MP2eare provided in a shape along the holes AH2. The pillars MP3oand MP3eare provided in a shape along the holes AH3. The pillars MP4oand MP4eare provided in a shape along the holes AH4. Channels (for example, semiconductor layers41) of the pillars adjacent in the Z direction are electrically coupled to each other.

The replacement hole STH divides the holes AH1and AH3and the memory trenches MT2and MT4. The replacement hole STH is filled with an insulator as in the embodiment. It suffices that the replacement hole STH divides either the hole AH or the memory trench MT in a layer provided with the memory pillars MP. Other structures of the semiconductor memory device1according to the second modification of the embodiment are similar to those in the embodiment.

As described above, the semiconductor memory device1according to the second modification of the embodiment has a structure in which the holes AH provided in layers adjacent in the Z direction are arranged in a staggered manner in the X direction in plan view. Even in such a case, the semiconductor memory device1according to the second modification of the embodiment can suppress overlay misalignment in pillars adjacent in the Z direction as in the embodiment, so that the chip area of the semiconductor memory device1can be reduced.

Note that, in order to acquire similar advantageous effects as those of the embodiment, it suffices that at least the holes AH provided in layers adjacent in the Z direction are arranged in a staggered manner. That is, the memory pillar MP may have a structure in which three or five or more pillars are connected in the Z direction.

In the embodiment, a case has been exemplified where the semiconductor layers41in the memory pillars MP are electrically coupled to the conductive layer21(source line SL) via the bottom surfaces of the memory pillars MP, but the present invention is not limited thereto. For example, in the semiconductor memory device1, the semiconductor layers41in the memory pillars MP and the source line SL may be coupled via the side surfaces of the memory pillars MP. A configuration for relaying the upper pillars UMP, the lower pillars LMP, and the joint portions may be provided between the upper pillars UMP and the lower pillars LMP.

In the semiconductor memory device1according to the embodiment, for example, the distance between the lower pillars LMPe1and LMPo2in the X direction in the cross section including the conductive layer23aand the conductive layer23bon a lower side is smaller than the distance between the lower pillars LMPe1and LMPo2in the X direction in the cross section including the conductive layer23aand the conductive layer23bon an upper side. In addition, the distance between the upper pillars UMPe1and UMPo2in the X direction in the cross section including the conductive layer24aand the conductive layer24bon the lower side is greater than the distance between the upper pillars UMPe1and UMPo2in the X direction in the cross section including the conductive layer24aand the conductive layer24bon the upper side.

The distance between the lower pillars LMPe1and LMPo1in the X direction in the cross section including the conductive layer23aand the conductive layer23bon the lower side is greater than the distance between the lower pillars LMPe1and LMPo1in the X direction in the cross section including the conductive layer23aand the conductive layer23bon the upper side. In addition, the distance between the upper pillars UMPe1and UMPo1in the X direction in the cross section including the conductive layer24aand the conductive layer24bon the lower side is smaller than the distance between the upper pillars UMPe1and UMPo1in the X direction in the cross section including the conductive layer24aand the conductive layer24bon the upper side.

The distance between the lower pillars LMPo2and LMPe2in the X direction in the cross section including the conductive layer23aand the conductive layer23bon the lower side is greater than the distance between the lower pillars LMPo2and LMPe2in the X direction in the cross section including the conductive layer23aand the conductive layer23bon the upper side. In addition, the distance between the upper pillars UMPo2and UMPe2in the X direction in the cross section including the conductive layer24aand the conductive layer24bon the lower side is smaller than the distance between the upper pillars UMPe1and UMPo1in the X direction in the cross section including the conductive layer24aand the conductive layer24bon the upper side.

In the embodiment, a case has been exemplified where the charge storage layers of the memory cell transistors MC are insulating films, but conductors such as semiconductors or metals may be used as the charge storage layers. That is, the semiconductor memory device1may include a floating gate type memory cell transistors MC in which the insulating films44and54are replaced with conductors. The configuration of the memory cell transistor MC is designed according to the structure of the charge storage layers in the memory pillar MP.

For example, in a case where the charge storage layers in each memory pillar MP are separated for each memory cell transistor MC in both the Y direction and the Z direction, both the insulating film and the conductor can be used as the charge storage layer. The conductor used as the charge storage layer may have a stacked structure using two or more types from among a semiconductor, metal, and an insulator. On the other hand, in a case where the charge storage layers in each memory pillar MP are not separated for each memory cell transistor MC in both the Y direction and the Z direction, the insulating film is used as the charge storage layer.

Note that the tunnel insulating films and the block insulating films corresponding to the same memory group MG may each be shared by or separated for the transistors in the NAND strings NSa and NSb, regardless of whether or not the charge storage layers are separated in the Y direction and the Z direction for each memory cell transistor MC. In addition, in a case where the tunnel insulating film and the block insulating film corresponding to the same memory group MG each extend in the Z direction in the memory pillar MP, these insulating films may be separated for each memory cell transistor MC.

Note that the memory pillar MP may have a structure in which a pillar corresponding to the select gate line SGD and a pillar corresponding to the word line WL are connected to each other. In this case, the holes AH corresponding to the pillars corresponding to the select gate line SGD and the holes AH corresponding to the pillars coupled to the pillars in the Z direction are provided in a staggered manner in plan view. The arrangement of the memory pillars MP is not limited to a four-row staggered arrangement, and may be any arrangement. The number of bit lines BL overlapping each memory pillar MP may be designed to be any number.

In the embodiment, the memory cell array10may include one or more dummy word lines between the word line WL0and the select gate line SGS, and between the word line WL7and the select gate line SGD. In a case where the dummy word lines are provided, dummy transistors are provided corresponding to the number of dummy word lines between the memory cell transistor MCO and the select transistor ST2, and between the memory cell transistor MC7and the select transistor ST1. The dummy transistors are transistors having a structure similar to that of the memory cell transistor MC, and being not used for storing data. In a case where two or more memory pillars MP are connected in the Z direction, the memory cell transistors MC close to the connecting portion of the pillars may be used as the dummy transistors.

In the above embodiment, a case has been described as an example in which the semiconductor memory device1has a structure in which circuits such as the sense amplifier module16are provided under the memory cell array10, but the present invention is not limited thereto. For example, the semiconductor memory device1may have a structure in which a chip provided with the sense amplifier module16and the like and a chip provided with the memory cell array10are bonded.

In this specification, the “coupling” indicates electrical coupling, and does not exclude an intervention of another element. The “electrically coupled” may be made via an insulator as long as one can operate in the same manner as the one electrically coupled. The “columnar” indicates the structural body provided in the hole formed in the manufacturing steps of the semiconductor memory device1. A “cross section including two conductive layers provided in the same layer” corresponds to, for example, the cross section parallel to the surface of the semiconductor substrate20and including the two conductive layers. The “in plan view” corresponds to, for example, viewing an object in a direction perpendicular to the surface of the semiconductor substrate20.