RF SWITCH

A transistor suited for use as an RF switch includes a semiconductor layer and a stack of a gate insulator layer and a conductive gate layer. A length of the conductive gate layer is smaller on the side of a lower surface, located in the vicinity of the gate insulator layer, and is greater on the side of an upper surface, opposite to the lower surface. Lateral sides of the conductive gate layer are covered, on a lower portion, with a first material and, on an upper portion, with a second material. The first material has a Young's modulus greater than a Young's modulus of the second material.

PRIORITY CLAIM

This application claims the priority benefit of French Application for Patent No. 2308741, filed on Aug. 17, 2023, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

TECHNICAL FIELD

The present disclosure generally concerns electronic components and, more particularly, field-effect transistors of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) type.

BACKGROUND

MOSFET-type transistors are field-effect transistors comprising an electrically-conductive gate insulated from a semiconductor substrate by a dielectric layer referred to as a gate insulator.

Various implementations of MOSFET transistors have already been provided.

It would be desirable to at least partly overcome certain disadvantages of known implementations of MOSFET transistors.

There is a need in the art to improve the electric performance of MOSFET transistors intended for radio frequency (RF) signal switching applications. Such transistors are referred to as RF switches.

SUMMARY

An embodiment provides a transistor comprising, on a semiconductor layer, a stack of a gate insulator layer and of a conductive gate layer, wherein: the length of the conductive gate is smaller on the side of a lower surface, located in the vicinity of the gate insulator layer, and is larger on the side of an upper surface, opposite to the lower surface, and the lateral sides of the conductive gate layer are covered, on a lower portion, with a first material and covered, on an upper portion, with a second material, the first material having a Young's modulus greater than that of the second material.

According to an embodiment, the Young's modulus of the first material is greater than 200 GPa.

According to an embodiment, the Young's modulus of the second material is smaller than 100 GPa.

According to an embodiment, the first material has a dielectric constant greater than that of the second material.

According to an embodiment, the dielectric constant, relative with respect to80, of the first material is greater than 7.

According to an embodiment, the dielectric constant, relative with respect to80, of the second material is smaller than 4.

According to an embodiment, the conductive gate layer comprises a notch extending across the entire width on its lower surface side.

According to an embodiment, the difference between the length of the conductive gate layer on the lower surface side and the length of the conductive gate layer on the upper surface side is in the range from 5 nm to 40 nm.

According to an embodiment, the first material is based on nitride, on carbide, or on diamond.

According to an embodiment, the second material is based on tetraethylorthosilicate, on phosphosilicate glass, or on silicoboron carbonitride.

Another embodiment provides a radio frequency switch comprising a transistor such as described hereabove.

DETAILED DESCRIPTION

For the sake of clarity, only the steps and elements that are useful for the understanding of the described embodiments have been illustrated and described in detail.

Unless specified otherwise, the expressions “about”, “approximately”, “substantially”, and “in the order of” signify plus or minus 10%, preferably of plus or minus 5%.

FIG.1is a cross-section view partially and schematically illustrating a transistor10according to a first embodiment.

Transistor10comprises a semiconductor layer11topped with a dielectric layer13also referred to as a gate insulator layer. Transistor10further comprises a conductive layer17, also referred to as a conductive gate layer, on gate insulator layer13. As an example, transistor10comprises a buried insulating layer15, under semiconductor layer11. Layers11and15correspond, for example, to a stack of layers within a substrate of the Semiconductor On Insulator (SOI) type.

As an example, inFIG.1, semiconductor layer11is formed on top of and in contact with buried insulating layer15. Gate insulator layer13is, for example, formed on top of and in contact with semiconductor layer11. Conductive gate layer17is, for example, formed on top of and in contact with insulating layer13.

In the embodiment ofFIG.1, conductive gate layer17has a length that is relatively smaller on the side of a lower surface, located in the vicinity of gate insulator layer13, and relatively greater on the side of an upper surface, opposite to the lower surface. In this context, the reference to a “length” of a transistor corresponds to a direction extending between the source region and drain region of the transistor.

As an example, conductive gate layer17comprises a first portion171and a second portion173, located on top of and in contact with first portion171. The first portion171and second portion173each have, for example, different lengths. Here, the length L1of the first portion171being smaller than the length L3of the second portion173of conductive gate layer17. As an example, the first portion171has a length L1that is constant along its entire height. As an example, the second portion173has a length L3that is constant along its entire height.

Conductive gate layer17thus comprises across its entire width a lengthwise notch exposing a portion of the upper surface of gate insulator layer13. In this context, the reference to a “width” of a transistor corresponds to a direction extending parallel to each of the source region and drain region of the transistor, and perpendicular to the length of the transistor. The conductive gate layer17may include a notch in the width at either or both of the source side and drain side of the gate.

As an example, gate insulator layer13is local and does not extend over the entire surface of the upper side of semiconductor layer11. As an example, gate insulator layer13is formed vertically in line with conductive gate layer17. The length of gate insulator layer13is, for example, similar to that of the second portion173of conductive gate layer17, for example equal to the length L3.

Semiconductor layer11is, for example, made of silicon, for example of single-crystal silicon. Semiconductor layer11has, for example, a thickness in the range from 10 nm to 500 nm, for example from 50 nm to 200 nm, for example in the order of 60 nm or in the order of 160 nm.

As an example, gate insulator layer13is made of silicon dioxide (SiO2) and has, for example, a thickness e1in the range from 1 nm and 15 nm, for example, in the range from 3 nm and 7 nm.

As an example, buried oxide layer15is made of oxide, for example of silicon dioxide (SiO2). Buried insulating layer15has, for example, a thickness in the range from 100 nm to 400 nm, for example from 100 nm to 250 nm, for example in the order of 200 nm.

As an example, conductive gate layer17is etched in a single step, for example by modifying during the etching the bias parameters to form the notch. The first portion171and second portion173are, for example, identical by their compositions. As an example, conductive gate layer17is made of doped polysilicon.

As a variant, conductive gate layer17is etched in two successive steps, one enabling to form portion171and the other enabling to form portion173. In this variant, the two portions171and173of conductive gate layer17are, for example, made of two different materials, for example one of the portions is based on polysilicon and the other is based on germanium-doped polysilicon.

Layer17has, for example, a thickness in the range from 30 nm to 300 nm, for example in the range from 50 nm to 100 nm, for example in the range from 80 nm to 90 nm. As an example, the portions171and173of conductive gate layer17have a length in the range from 50 nm to 300 nm, for example in the range from 100 nm to 200 nm. As an example, the portions171and173of conductive gate layer17have a length difference (corresponding to the depth of the notch) in the range from 5 nm to 40 nm, for example in the order of 10 nm. Conductive gate layer17has, for example, a width in the range from 1 μm to 10 μm, for example in the order of 5 μm.

Transistor10comprises, for example, a source region21and a drain region23formed in semiconductor layer11. Source region21and drain region23are, for example, laterally separated from each other by a body region22. An upper portion of body region22forms the channel-forming region24of transistor10. Conductive gate layer17is, for example, located above channel-forming region24.

As an example, the source region21, drain region23, and body region22are flush with the upper surface of semiconductor layer11.

Transistor10is, for example, an N-channel MOS transistor (NMOS), that is, a transistor having N-type doped source21and drain23regions, for example doped with arsenic or phosphorus atoms, while the body region is P-type doped, for example doped with boron atoms.

As a variant, transistor10is, for example, a P-channel MOS transistor (PMOS) that is, a transistor having P-type doped source21and drain23regions, for example doped with boron atoms, while the body region is N-type doped, for example doped with arsenic or phosphorus atoms.

As an example, transistor10comprises an insulating layer25coating the sides of conductive gate layer17and the sides of gate insulator layer13. As an example, insulating layer25coats and is in contact with a portion of the upper surface of semiconductor layer11located in the vicinity of gate insulator layer13. Insulating layer25is, for example, made of oxide or of nitride. As an example, insulating layer25is made of silicon nitride (Si3N4).

As an example, the source21and drain23regions are topped with an insulating layer27, in line with insulating layer25. As an example, layer27is formed in contact with the upper surface of semiconductor layer11. As an example, layer27is made of an oxide.

Transistor10further comprises spacers29comprising a lower portion291and an upper portion293. As an example, a spacer29is formed on each of the lateral sides of conductive gate layer17. Each spacer29is, for example, in contact, by a lateral side with the lateral side of insulating layer25and by its lower surface with the upper surface of the portion of insulating layer25formed on semiconductor layer11. In each spacer29, the lower portion291is made of a first dielectric material and the upper portion293is made of a second dielectric material, the first material having a Young's modulus greater than a Young's modulus of the second material. As an example, the first material of the lower portion291of spacer29has a relatively higher Young's modulus, for example greater than 200 GPa, for example greater than 250 GPa. As an example, the second material of the upper portion293of spacer29has a relatively lower Young's modulus, for example smaller than 100 GPa, for example smaller than 80 GPa.

As an example, the first material of the lower portion291of spacer29has a dielectric constant greater than a dielectric constant of the second material of the upper portion293of spacer29. As an example, the first material of the lower portion291of spacer29has a relatively higher dielectric constant, for example greater than 7, for example greater than 8. As an example, the second material of the upper portion293of spacer29has a relatively lower dielectric constant, for example smaller than 5, for example smaller than 4. By dielectric constant of a material, there is here meant the ratio of the permittivity of the material to the permittivity of vacuum.

As an example, the first material is made of a nitride, for example of aluminum nitride. As an example, the first material is made of silicon carbide. As an example, the first material is made of diamond. As an example, the first material may be made of tungsten carbide, of silicon carbide, of aluminum oxide, of beryllium oxide, of silicon nitride, of magnesium oxide, of zirconium oxide, of silicon, of aluminum silicate, of silicon oxide, of borophosphosilicate glass, of borosilicate glass, of phosphosilicate glass, of fluorosilicate glass, and/or of non-doped silicate glass.

As an example, the second material is made of tetraethylorthosilicate (TEOS). As an example, the second material is made of phosphosilicate glass. As an example, the second material is made of silicoboron carbonitride (SiBCN). As an example, the second material is made of silicon oxide, of organosilicate glass, of polyimide, of borophosphosilicate glass, of borosilicate glass, of phosphosilicate glass, of fluorosilicate glass, and/or of non-doped silicate glass.

The lower portion291thus covers a lower portion of conductive gate layer17and the upper portion293covers an upper portion of conductive gate layer17. InFIG.1, spacer29has been shown so that the lower portion291of stack29covers the first portion171of conductive gate layer17and the upper portion293covers the second portion173of conductive gate layer17. In other words, the interface between the lower portion291and upper portion293of spacer29is located at the level of the upper wall of the notch formed in gate17.

As a variant, the lower portion291of spacer29may cover a portion of the second portion173of conductive gate layer17. Still as a variant, the upper portion293of spacer29may cover part of the first portion171of conductive gate layer17.

Transistor10further comprises an insulating layer31coating the sides of spacer29. As an example, the insulating layer31covers the sides of spacer29which are not covered with insulating layer25and the upper surface of layer27. As an example, insulating layer31is open in front of the upper surface of conductive gate layer17to be able to recover the contact therein. Insulating layer31is, for example, made of silicon nitride.

Transistors10are advantageously capable of operation as RF switches, for example intended to operate at frequencies in the range from 3 kHz to 300 GHz, for example from 100 MHz to 10 GHz, for example in the order of one GHz. In such an RF switching application, the operating parameters desired are for a low parasitic off-state capacitance COFFof the transistor and a low on-state resistance RONof the transistor.

In transistor10, capacitance COFFis influenced by the parasitic capacitances between the gate and the source and drain contacts which are themselves controlled by the dielectric constants of the spacers. Still in transistor10, resistance RONis influenced by the mobility of charge carriers, itself controlled by the mechanical stress applied to channel region24.

An advantage of the present embodiment is that spacer29enables to favor the transmission of mechanical stress, for example introduced by insulating layer31, to channel region24, and this due to the provision of a material having a relatively high Young's modulus located in the notch formed in the lower portion of the gate. This particularly enables to decrease the resistance RONof the switch.

Another advantage of the present embodiment is that the provision of a material having a relatively high dielectric constant in the lower portion of the spacer and in particular in the notch formed in the lower portion of the gate enables to decrease the capacitance COFFof the switch.

This embodiment thus enables to optimize the RONand COFFtradeoff for the RF switch, due to an increased transfer of stress to the channel and to decreased capacitances.

FIG.2is a cross-section view partially and schematically illustrating a transistor10′ according to a second embodiment.

The transistor10′ illustrated inFIG.2is similar to the transistor10illustrated inFIG.1, with the difference that transistor10′ does not comprise insulating layer25. In the embodiment illustrated inFIG.2, the lateral sides of conductive gate layer17are covered with spacer29, formed in contact with conductive gate layer17.

In the foregoing embodiments, transistors10and10′ comprise a layer27coating the upper surface of semiconductor layer11, but this layer27may be omitted. Additionally, the lower portion291and upper portion293may be formed in a manner where upper portion293covers lower portion291so that layer31is not in contact with lower portion291. Indeed, such a configuration could include an arrangement where the material of the lower portion291is contained only within the notch associate with length L1.

FIG.3is a cross-section view partially and schematically illustrating a transistor10″ according to a third embodiment.

The transistor10″ illustrated inFIG.3is similar to the transistor10illustrated inFIG.1, with the difference that the material291of higher Young's modulus is located only in the notch formed in the conductive gate17. In this embodiment, the material293of lower Young's modulus may extend vertically along the entire height of the conductive gate17. In this embodiment, the interface between the material291and the material293is vertical (not horizontal as in the embodiment ofFIG.1). In this embodiment, the material of higher Young's modulus291is not in contact with insulating layer31.

FIG.4is a cross-section view partially and schematically illustrating a transistor10′″ according to a fourth embodiment.

The transistor10′″ illustrated inFIG.4is similar to the transistor10″ illustrated inFIG.3, with the difference that transistor10′″ does not comprise insulating layer25.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art. In the foregoing embodiments, transistors10,10′,10″, and10′″ comprise a layer27coating the upper surface of semiconductor layer11, but this layer27may be omitted. Further, the described embodiments are not limited to the examples of materials and of dimensions mentioned in the present disclosure.

Finally, the practical implementation of the described embodiments and variants is within the abilities of those skilled in the art based on the functional indications given hereabove.