Power control circuit and electronic device

A basic and simple power control circuit for selectively controlling power to an electronic device is provided. The electronic device includes a power module, a system power port, and a processing unit, the processing unit includes a first and a second power control pins. The power control circuit includes a power switch, a trigger signal producing sub-circuit, a trigger-receiving sub-circuit, and a switch controlling sub-circuit. The switch is connected between the power module and the system power port. The trigger signal producing sub-circuit produces a trigger signal. When receiving a trigger signal, the trigger-receiving sub-circuit follows a first control signal output by the second power control pin to output the first control signal. The switch controlling sub-circuit turns off the power switch when receiving the first control signal.

BACKGROUND

1. Technical Field

The present disclosure relates to circuits, and particularly to a power control circuit and an electronic device with the power control circuit.

2. Description of Related Art

Electronic devices, such as computers, set-top boxes, include a power control circuit. When the electronic device is manually shut down, the power control circuit cuts off the power source after the electronic device is given a soft shutdown. The usual power control circuit also can control the electronic device to enter an active standby mode or a passive standby mode awaiting further user operation. In the active standby mode, the power control circuit maintains power to every element of the electronic device, and only shuts down programs currently running. In the passive standby mode, the power control circuit stops providing power to the elements of the electronic device except for a central processing unit and a memory of the electronic device, to maintain basic operating requirements. However, the usual power control circuit is constituted by a microcontroller and a power management chip and is expensive.

A power control circuit and an electronic device to overcome the described limitations are thus needed.

DETAILED DESCRIPTION

FIG. 1illustrates a block diagram of an embodiment of an electronic device100. The electronic device100includes a processing unit10, a power button20, a power module30, a memory40, a function module50, a power control circuit60, and a system power port P-system. The electronic device100is capable of managing the power of the power module30by using the power control circuit60with a simple structure.

The power button20produces a signal in response to user operation. The power module30powers the electronic device100via the system power port P-system. The power module30can be a battery or a power adapter.

The processing unit10includes a receive pin P1, a first on-off control pin P2, and a second on-off control pin P3. The processing unit10receives the signal produced by the power button20via the receive pin P1.

The power control circuit60includes an on-off control circuit61. The on-off control circuit61includes a trigger signal producing sub-circuit611, a trigger-receiving sub-circuit612, a switch control sub-circuit613, and a switch614. The trigger signal producing sub-circuit611is connected to the first on-off control pin P2. The trigger-receiving sub-circuit612is connected to the second on-off control pin P2and the trigger signal producing sub-circuit611. The switch control sub-circuit613is connected between the trigger-receiving sub-circuit612and the switch614. The switch614is connected between the power module30and the system power port P-system, and establishes or cuts off a connection between the power module30and the system power port P-system. The system power port P-system is a total power input port for the electronic device.

In the embodiment, when the processing unit10determines that a duration of the signal from the power button20is greater than a first predetermined time (such as 4 seconds) and the electronic device100is at a normal working state, the processing unit10controls the first on-off control pin P2and a second on-off control pin P3to both output a first control signal, and controls the electronic device100to carry out a soft shutdown, namely to store user data and then shut down running programs. The processing unit10also controls the first on-off control pin P2to output a second control signal after the soft shutdown is finished. The trigger signal producing sub-circuit611produces an edge trigger signal in response to the signals output by the first on-off control pin P2is changed from the first control signal to the second control signal. The trigger-receiving sub-circuit612follows the first control signal output by the second on-off control pin P3and then issues out the first control signal, when receiving the edge trigger signal from the trigger signal producing sub-circuit611. The switch control sub-circuit613turns off the switch614when receiving the first control signal from the trigger-receiving sub-circuit612, thus cutting off the connection between the power module30and the system power port P-system. Then, the electronic device100is shut down completely. In the embodiment, the processing unit10controls the second on-off control pin P3to output the first control signal all the time before the electronic device100is shut down completely.

In the embodiment, the power control circuit60also includes a standby control circuit62connected between the system power port P-system and the function module50.

The processing unit10also includes a standby control pin P4. The processing unit10controls the standby control pin P4to output a standby control signal to the standby control circuit62, when it is determined that the duration of the signal from the power button20is less than the first predetermined time but is greater than a second predetermined time (such as 2 seconds) and that the electronic device100is working normally. The standby control circuit62cuts off a connection between the system power port P-system and the function module50when receiving the standby control signal. Thus the system power port P-system stops providing power to the function module50and the electronic device100enters a passive standby mode. In the passive standby mode, the function module50is not in working state due to power supply being cut off. In the embodiment, the function module50includes all of function chips of the electronic device100except the processing unit10and the memory40, such as a codec chip, an audio processing chip, and the like.

Therefore, when the electronic device100is at the passive standby state, only the processing unit10and the memory40are being powered, and the other elements of the electronic device100are not powered, which greatly decreases power consumption. In the embodiment, the system power port P-system is connected to the processing unit10and the memory40directly and is always powering the processing unit10and the memory40when the system power port P-system obtains power from the power module30.

In the embodiment, the processing unit10controls the electronic device to enter an active standby state when determining that the duration of the signal from the power button20is less than the second predetermined time and that the electronic device100is working normally. When the electronic device100at the active standby state, the processing unit10shuts down the programs running currently and provides power to the function module50.

In the embodiment, the processing unit10also controls the electronic device100to resume a normal working state when determining that the duration of the signal from the power button20is less than the second predetermined time and that the electronic device100is at the active standby mode or at the passive standby mode.

In the embodiment, the processing unit10also controls the electronic device100to enter the active standby mode when determining that the electronic device100is turned on and that a duration of time during which no operations are carried out on the electronic device100is at least a third predetermined time, such as 1 hour.

Referring toFIG. 2, a circuit diagram of the on-off control circuit61is illustrated. In the circuit, the trigger signal producing sub-circuit includes resistors R1, R2, a diode D1, and a negative-positive-negative bipolar junction transistor (NPN BJT) Q1. The resistors R1and R2are connected between a voltage port Vcc and ground in series. A connection node N1of the resistors R1and R2constitutes an output port (not shown) of the trigger signal producing sub-circuit611. The diode D1is connected between the first on-off control pin P1and a base of the NPN BJT Q1, an emitter of the NPN BJT Q1is grounded, and a collector of the BPN BJT Q1is connected to the connection node N1.

The voltage port Vcc obtains a voltage by virtue of being connected to the power module30.

The trigger-receiving sub-circuit612includes a resistor R3and a D-flip flop T1. The D-flip flop T1includes an input terminal D, an output terminal Q, and a trigger terminal CP. The input terminal D is connected to the second on-off control pin P3, the trigger terminal CP is connected to the output port of the trigger signal producing sub-circuit611, namely, to the connection node N1of the resistors R1and R2. The resistor R3is connected between the input terminal D and ground. The output terminal Q is connected to the switch control sub-circuit613.

The switch control sub-circuit613includes resistors R4, R5, R6, an N-channel metal oxide semiconductor field effect transistor (NMOSFET) Q2, and an NPN BJT Q3. A gate of the NMOSFET Q2is connected to the output terminal Q of the D-flip flop T1and is grounded via the resistor R4. The resistor R5is connected between the voltage port Vcc and a drain of the NMOSFET Q2, a source of the NMOSFET Q2is grounded. The drain of the NMOSFET Q2is also connected to a base of the NPN BJT Q3, an emitter of the NPN BJT Q3is grounded. The resistor R6is connected between the power module30and a collector of the NPN BJT Q3.

In the embodiment, the switch614is a P-channel metal oxide semiconductor field effect transistor (PMOSFET) Q4, a source and a gate of the PMOSFET Q4are connected to two ends of the resistor R6, a drain of the PMOSFET Q4is connected to the system power port P-system. The source of the PMOSFET Q4is also connected to the power module30.

In the embodiment, the power button20is connected between the power module30and the receive pin P1of the processing unit10. In the embodiment, the signal from the power button20is a high level signal, when the power button20is being operated/pressed, the power button20connects the power module30and the receive pin P1, thus the receive pin P1receives the signal with high level voltage. In the embodiment, the power button20is a reset switch.

As described above, when the processing unit10determines that the duration of the power button20signal is greater than the first predetermined time and the electronic device100is working normally, the processing unit10controls the first on-off control pin P2and the second on-off control pin P3to both output the first control signal. The processing unit10controls the electronic device to carry out a soft shut down at this time. The processing unit10also controls the second on-off control pin P3to output the second control signal and maintains the first on-off control pin P2to output the first control signal, after a soft shutdown of the electronic device10has taken place. In the embodiment, the first control signal is a high level signal, the second control signal is a low level signal, and the D-flip flop T1is a rising-edge triggered flip flop.

When the first on-off control pin P2outputs the first control signal with high level voltage, a base of the NPN BJT Q1electrically connected to the first on-off control pin P2obtains the high level signal and the NPN BJT Q1is turned on accordingly. The trigger terminal CP of the D-flip flop T1is grounded via the turned-on NPN BJT Q1and is at a low level voltage. When the first on-off control pin P2outputs the second control signal with the low level voltage, the NPN BJT Q1is turned off because of the base of the NPN BJT Q1receives a low level voltage. The connection node N1of the resistors R1and R2is at high level voltage by dividing the voltage of the voltage port Vcc. Thus, the trigger terminal CP of the D-flip flop T1receives the high level voltage from the connection node N1and is at high level voltage. Therefore, the trigger signal producing sub-circuit611outputs a rising-edge trigger signal to the trigger terminal CP of the D-flip flop T1.

The output terminal Q of the D-flip flop T1follows the signal of the input terminal D when the trigger terminal CP of the D-flip flop T1receives the rising-edge trigger signal. That is, the output terminal Q of the D-flip flop T1outputs the first control signal when the trigger terminal CP of the D-flip flop T1receives the rising-edge trigger signal.

The gate of the NMOSFET Q2of the switch control sub-circuit613receives the first control signal with the high level voltage and the NMOSFET Q2is turned on accordingly. The base of the NPN BJT Q3is grounded via the NMOSFET Q2which is turned on and the NPN BJT Q3is turned off accordingly.

The gate of the PMOSFET Q4is electrically connected to the power module30and is at high level voltage via the resistor R3, thus the PMOSFET Q4is turned off. The connection between the power module30and the system power port P-system is cut off, thus none of elements of the electronic device100receive any power and the electronic device100is turned off completely.

As shown inFIG. 2, the trigger signal producing sub-circuit611also includes a diode D2, the diode D2is connected between the receive pin P1and the base of the NPN BJT Q1. Therefore, when the power button20is operated, the diode D2also conducts the high level voltage to the base of the NPN BJT Q1, and when the pressing of the power button20is stopped, the diode D2does not conduct a high level voltage to the base of the NPN BJT Q2. Therefore, if the power button20is released after the first on-off control pin outputs the second control signal with the low level voltage, the time that the trigger signal producing sub-circuit611outputs the rising-edge trigger signal is the time the power button20is released. Of course, if the power button20is released before the first on-off control pin outputs the second control signal with the low level voltage, the time that the trigger signal producing sub-circuit611outputs the rising-edge trigger signal is the time that the first on-off control pin outputs the second control signal. In another embodiment, the diode D2can be omitted, and the output time for the trigger signal producing sub-circuit611outputting the rising-edge trigger signal is the time that the first on-off control pin outputs the second control signal.

Referring toFIG. 3, a circuit diagram of the standby control circuit62is illustrated. In the embodiment, the standby control circuit62includes a number of MOSFETs Q5, the function module50includes a number of function chips, such as an audio processing chip51, a video processing chip52, and an antenna circuit53. Gates of the MOSFETs Q5are all connected to the standby control pin P4of the processing unit10, sources of the MOSFETs Q5are all connected to the system power port P-system, and drains of the MOSFETs Q5are respectively connected to the audio processing chip, the video processing chip, and the antenna circuit53.

As described above, when the processing unit10determines that the duration of the signal from the power button20is less than the first predetermined time but greater than the second predetermined time and that the electronic device100is working normally, the processing unit10controls the standby control pin P4to output the standby control signal to the gate of each MOSFET Q5, to turn off each of the MOSFETs Q5. Therefore, the connection between the system power port P-system and the function module50is cut off and the system power port P-system stops providing power to the function module50.

In the embodiment, the MOSFETs Q5are NMOSFETS, and the standby control signal is a low level signal. In another embodiment, the MOSFETs Q5are PMOSFETS, and the standby control signal is a high level signal.

In the embodiment, when the processing unit10determines that the duration of the signal from the power button20is less than the second predetermined time and the electronic device100is at the active standby mode or at the passive standby mode, the processing unit10controls the standby control pin P4to output a high level signal to the gates of the MOSFETs Q5, to turn on each of the MOSFETs Q5. Thus, the system power port P-system resumes a power supply to the function module50.

In the embodiment, the electronic device100can be a notebook computer, a tablet computer, a desktop computer, or a set top box.

Therefore, the very simple power control circuit60can control the electronic device100to turn on or turn off, or to switch between different standby modes and the normal working mode.

It is understood that the present embodiments and their advantages will be understood from the foregoing description, and various changes may be made thereto without departing from the spirit and scope of the disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being embodiments of the present disclosure.