NOVEL GATE STRUCTURE FOR AN LDMOS TRANSISTOR DEVICE

A device is disclosed that includes a source region positioned in a first doped well region in a semiconductor substrate and a drain region positioned in a second doped well region in the substrate, wherein there is a well gap between the first doped well region and the second doped well region. The device also includes a gate structure that includes a first gate insulation layer positioned above an upper surface of the substrate, wherein the first gate insulation layer extends from a drain-side sidewall of the gate structure to a location above the well gap, and a second gate insulation layer having a first portion positioned above the upper surface of the substrate and a second portion positioned above the first gate insulation layer.

BACKGROUND

Field of the Invention

The present disclosure generally relates to various novel embodiments of a gate structure for an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor device and various novel methods of making such a gate structure.

Description of the Related Art

There are two major structural categories of RF MOS transistors in use today. These transistors include DMOS (double-diffused Metal Oxide Semiconductor) devices and LDMOS (laterally diffused Metal Oxide Semiconductor) devices. DMOS and LDMOS devices have unique geometries, unique behaviors and require unique fabrication techniques to fabricate such devices. In recent years, LDMOS devices have been increasingly applied in high voltage and smart power applications. Generally, an LDMOS device has an asymmetric structure with a drift region located between the channel of the LDMOS and the drain region. The drift region includes an isolation structure that is formed in the substrate between the source/drain regions, wherein a portion of the isolation structure is positioned vertically below the gate structure of the LDMOS device. Device designers are under constant pressure to increase the performance capabilities of all transistor devices, including LDMOS devices.

The present disclosure is generally directed to various novel embodiments of a gate structure for an LDMOS device and various novel methods of making such a gate structure.

SUMMARY

Generally, the present disclosure is directed to various novel embodiments of a gate structure for an LDMOS device and various novel methods of making such a gate structure. An illustrative device disclosed herein includes a source region positioned in a first doped well region in a semiconductor substrate and a drain region positioned in a second doped well region in the substrate, wherein there is a well gap between the first doped well region and the second doped well region. The device also includes a gate structure that includes a first gate insulation layer positioned above an upper surface of the substrate, wherein the first gate insulation layer extends from a drain-side sidewall of the gate structure to a location above the well gap, and a second gate insulation layer having a first portion positioned above the upper surface of the substrate and a second portion positioned above the first gate insulation layer.

An illustrative method disclosed herein includes forming an initial gate structure that includes a first gate insulation layer positioned on a semiconductor substrate between a sidewall spacer, forming a patterned etch-mask that covers a first portion of the first gate insulation layer while leaving a second portion of the first gate insulation layer exposed, and performing an etching process to remove the second portion of the first gate insulation layer. In this example, the method also includes removing the patterned etch-mask and forming a conformal second gate insulation layer, wherein the conformal second gate insulation layer has a first portion positioned on the upper surface of the semiconductor substrate and a second portion positioned on the first gate insulation layer.

DETAILED DESCRIPTION

As will be readily apparent to those skilled in the art upon a complete reading of the present application, the presently disclosed method may be applicable to a variety of products, including, but not limited to, logic products, memory products, etc. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.

FIGS. 1-11depict various novel embodiments of a gate structure for an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device10and various novel methods of making such a gate structure. As will be appreciated by those skilled in the art after a complete reading of the present application, the LDMOS device10disclosed herein may be an N-type or a P-type device. Moreover, the LDMOS device10may come in a variety of different forms, e.g., the LDMOS device10may be a planar device, a FinFET device, etc. However, the various inventions disclosed herein should not be considered to be limited to the particular example shown in the attached drawings and described below.

The illustrative LDMOS device10disclosed herein will be formed above a semiconductor substrate11having an upper surface11A. In the case where the LDMOS device10is a FinFET device, the upper surface11A would be the upper surface of a fin. The gate length (GL) direction of the LDMOS device10is also depicted inFIG. 1. The substrate11may be a bulk semiconductor substrate or it may be a semiconductor-on-insulator (SOI) substrate that includes a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer, wherein transistor devices are formed in and above the active semiconductor layer. The substrate (irrespective of its form) may be made of silicon or it may be made of semiconductor materials other than silicon. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials. The various components, structures and layers of material depicted herein may be formed using a variety of different materials and by performing a variety of known process operations, e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), a thermal growth process, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application.

FIG. 1depicts the LDMOS device10after several process operations were performed. More specifically, an illustrative P-well13A and an illustrative N-well13B (collectively referenced using the numeral13) were formed in the substrate11by performing traditional ion implantation techniques through patterned implant masks (not shown) that were formed above the substrate11. Of course, the P-well13A comprises a P-type dopant (e.g., boron) while the N-well13B comprises an N-type dopant (e.g., arsenic). The concentration of dopant atoms in the wells13may vary depending upon the particular application, and the wells13need not have the same dopant concentration, but that may be the case in some applications. The physical depth of the wells13may vary depending upon the particular application. In the depicted example, the wells13are separated by a well gap14, the magnitude of which may vary depending upon the particular application.

Also depicted inFIG. 1is an isolation structure17that was formed in the substrate11. The isolation structure17may be comprised of a variety of different materials, e.g., silicon dioxide, etc., and it may be formed by performing traditional etching, deposition and planarization processes. The LDMOS device10also comprises a source region19S and a drain region19D (collectively referenced using the numeral19). The source region19S is formed in the P-well13A, while the drain region19D is formed in the N-well13B. In one embodiment, the source/drain regions19may be formed by performing traditional ion implantation techniques. In other embodiments (not shown), cavities may be formed in the substrate11and a doped epitaxial semiconductor material may be formed in the cavities to form the doped source/drain regions19.

The gate structure of the LDMOS device10will be formed by using replacement gate manufacturing techniques. Accordingly,FIG. 1depicts the LDMOS device10after an initial gate structure22was formed above the substrate11. The initial gate structure22comprises a first gate insulation layer23and a sacrificial gate electrode25. An initial gate cap29was formed above the sacrificial gate electrode25. A sidewall spacer27was formed adjacent the initial gate structure22. In an illustrative example, the first gate insulation layer23may be comprised of silicon dioxide, silicon nitroxide or silicon nitride and it may be formed by performing a deposition process or by performing a thermal growth process. The sacrificial gate electrode25may be comprised of a variety of materials, e.g., amorphous silicon, polysilicon, etc. The initial gate cap29may be comprised of a variety of different materials, e.g., silicon nitride. The sidewall spacer27may be comprised of a variety of different materials, e.g., silicon dioxide, a low-k material, silicon nitride, SiCN, SiCO, and SiOCN, etc. The sidewall spacer27is intended to be representative in nature in that, in some applications, multiple sidewall spacers may be formed adjacent the initial gate structure22. The vertical thickness of the first gate insulation layer23, the sacrificial gate electrode25and the initial gate cap29, as well as the lateral thickness of the sidewall spacer27, may vary depending upon the particular application. In an illustrative embodiment, based upon current-day technology, the first gate insulation layer23may have a thickness of about 3-4 nm. The techniques used to form the initial gate structure22, the initial gate cap29and the sidewall spacer27are well known to those skilled in the art. The lateral width (critical dimension) of the initial gate structure22(in the gate-length direction (GL) of the device) may vary depending upon the particular application.

In a cross-sectional view taken through the isolation structure17in a direction corresponding to the gate length direction of the LDMOS device10, the isolation structure17has a channel-side edge17C and a drain-side edge17D. As depicted, in an illustrative embodiment, a portion of the isolation structure17is positioned vertically below the initial gate structure22for the LDMOS device10. In an illustrative example, the isolation structure17may extend under the initial gate structure22by a distance of about 30-50 nm based upon current-day technology. Also depicted inFIG. 1is a layer of insulating material31(e.g., an ILD layer) formed across the substrate11. The layer of insulating material31may be formed by performing a blanket deposition process and thereafter performing one or more CMP process operations to planarize the upper surface of the layer of insulating material31with the upper surface of the initial gate cap29. The layer of insulating material31may be comprised of a variety of different materials, e.g., silicon dioxide, a low-k material, etc. Although not depicted, in many applications, a conformal contact etch stop layer (CESL), e.g., silicon nitride, would be formed on the substrate11prior to the formation of the layer of insulating material31.

FIG. 2depicts the LDMOS device10after several process operations were performed. First, one or more CMP process operations were performed to remove the initial gate cap29to expose the underlying sacrificial gate electrode25. At that point, an etching process was performed to remove the sacrificial gate electrode25selectively relative to the surrounding materials. This results in the formation of a replacement gate cavity33that is laterally bounded by the sidewall spacer27. As depicted, the removal of the sacrificial gate electrode25exposes the first gate insulation layer23.

FIG. 3depicts the LDMOS device10after a conformal deposition process (e.g., CVD, ALD, etc.) was performed to form a conformal sacrificial layer of material35on the device and within the replacement gate cavity33. The sacrificial layer of material35may be comprised of a variety of different materials, e.g., silicon dioxide, silicon nitride, etc., and it may be formed to any desired thickness, e.g., 3-5 nm.

FIG. 4depicts the LDMOS device10after a patterned etch mask37, e.g., a layer of photoresist or OPL, was formed above the sacrificial layer of material35. As depicted, the patterned etch mask37covers a portion of the sacrificial layer of material35while leaving a remaining portion of the sacrificial layer of material35exposed for further processing.

FIG. 5depicts the LDMOS device10after an etching process was performed through the patterned etch mask37to remove the exposed portion of the sacrificial layer of material35. This process exposes a portion of the first gate insulation layer23.

FIG. 6depicts the LDMOS device10after an etching process was performed through the patterned etch mask37to remove the exposed portion of the first gate insulation layer23within the replacement gate cavity33. This process exposes a portion of the upper surface11A of the substrate11within the replacement gate cavity33. As will be described more fully below, the remaining portion of the first gate insulation layer23shown inFIG. 6will be part of the final gate structure for the LDMOS device10.

FIG. 7depicts the LDMOS device10after the patterned etch mask37was removed, e.g., by performing an ashing process. This process exposes the remaining portion of the sacrificial layer of material35.

FIG. 8depicts the LDMOS device10after an etching process was performed to remove the remaining portion of the sacrificial layer of material35selectively relative to the surrounding materials. This process exposes the remaining portion of the first gate insulation layer23. The first gate insulation layer23has a dimension23L in the gate length direction of the LDMOS device10. In an illustrative embodiment, the dimension23L may be about 200-300 nm based upon current-day technology. Also depicted inFIG. 8is a dimension10L that corresponds to the gate length of the LDMOS device10(at the surface11A of the substrate11). In an illustrative embodiment, the gate length10L may be about 400-500 nm based upon current-day technology. In terms of percentage, the dimension23L of the first gate insulation layer23may be about 50-80% of the gate length10L of the transistor device.

The next major process operation involves the formation of additional materials for the final gate structure of the LDMOS device10. Accordingly,FIG. 9depicts the LDMOS device10after several process operations were performed. First, a second gate insulation layer39, a metal-containing layer41(e.g., a work function metal layer) and a bulk conductive material layer43were sequentially formed on the device10and in the replacement gate cavity33. In practice, there may be more than or less than the three illustrative layers (39,41and43) formed on a real-world LDMOS device10. The thickness and composition of these gate materials, i.e., the three illustrative layers39,41and43, may vary depending upon the particular application, and the relative thickness of these gate material layers shown in the drawings is not to scale. For example, in an illustrative embodiment, the second gate insulation layer39may be made of a high-k (k value of 10 or greater) insulating material, such as hafnium oxide, while the metal-containing layer41may be made of a material such as titanium nitride. The bulk conductive material layer43may be comprised of a material such as a metal, a metal alloy, tungsten or a doped polysilicon. The second gate insulation layer39and the metal-containing layer41may be formed by performing a conformal deposition process, such as an ALD process. The bulk conductive material layer43may be formed by performing a blanket deposition process.

FIG. 10depicts the LDMOS device10after several process operations were performed. First, one or more CMP processes were performed so as to remove excess portions of the various materials of the final gate structure47that are positioned above the upper surface of the layer of insulating material31and outside of the replacement gate cavity33. At that point, one or more recess etching processes were performed to recess the vertical height of the materials of the final gate structure47so as to make room for a final gate cap45. The final gate cap45may be formed by blanket depositing a layer of the material for the gate cap45above the device and in the space above the recessed gate materials for the final gate structure47and thereafter performing a CMP process to remove excess amounts of the gate cap material positioned outside the replacement gate cavity33.

With reference toFIG. 11, after the formation of the final gate structure47, traditional manufacturing operations are performed to complete the device. For example, conductive source/drain metallization structures51(e.g., trench silicide structures, tungsten structures) are formed to contact the source/drain regions19. In an illustrative embodiment, the source/drain metallization structures51may be essentially line-type features that extend into and out of the plan of the drawing inFIG. 11.

The channel region53and the drain extension region55of the LDMOS device10are depicted inFIG. 11. When viewed in a cross-section taken through the final gate structure47in the gate length direction of the LDMOS device10, the final gate structure47has a drain-side sidewall47D and a source-side sidewall47S. In the illustrative LDMOS device10depicted herein, the isolation structure17is positioned laterally between the final gate structure47and the drain region19D. As noted previously, in an illustrative embodiment, at least a portion of the isolation structure17is positioned vertically under at least a portion of the final gate structure47and under at least a portion of the first gate insulation layer23of the final gate structure47.

Also note that, when viewed in the cross-section shown inFIG. 11, the composition of the final gate structure47is not uniform across the final gate structure47, i.e., the first gate insulation layer23extends from the drain-side sidewall47D of the final gate structure47to a location above the well gap14, i.e., a substantially vertically oriented edge23A of the first gate insulation layer23is positioned above the well gap14. The first gate insulation layer23is also positioned vertically above a portion of the drain extension region55and a portion of the N-well13B. In contrast, the second gate insulation layer39extends from the source-side sidewall47S to the drain-side sidewall47D. Moreover, in an illustrative embodiment, a first portion39A of the second gate insulation layer39is positioned on and in contact with the surface11A of the substrate11above the channel region53and a portion of the P-well13A, while a second portion39B of the second gate insulation layer39is positioned on and in contact with the first gate insulation layer23. Also note that the first portion39A of the second gate insulation layer39is positioned between the first gate insulation layer23and the sidewall spacer27. The second gate insulation layer39also has a third substantially vertically oriented portion39C that is positioned on and in contact with the substantially vertically oriented edge23A of the first gate insulation layer23.

As will be appreciated by those skilled in the art, it is important for LDMOS devices to exhibit good MSG (Maximum Stable Gain) values in power amplifier applications (e.g., a sub-6 GHz WiFi application), particularly in 3.3V LDMOS applications. MSG values for an LDMOS device may be increased by improving the transconductance (gm) of the device without significantly increasing the gate-to-drain (Cgd) capacitance of the device. Simulation data has revealed that an LDMOS device10with the novel final gate structure47disclosed herein exhibits better performance characteristics as compared to a prior art LDMOS device with a gate structure wherein a gate insulation layer (corresponding to that of the first gate insulation layer23) extends across the entire bottom of the gate structure of the prior art LDMOS device. More specifically, by using the novel final gate structure47disclosed herein, the LDMOS device10described herein exhibited about a 10-15% improvement in MSG at 5 GHz and about a 70-90% improvement in the transconductance (gm) as compared to a prior art LDMOS device.