Method of forming an infrared filter associated with an image sensor

An image sensor having a portion including interconnection levels formed on a semiconductor substrate covered with a first layer of a dielectric material, including conductive tracks separated from one another by insulating layers interconnected by vias crossing the insulating layers, and an infrared bandpass filter comprising filter levels adjacent to the interconnection levels formed by an alternation of second layers of the dielectric material and of silicon layers, the refraction index of the dielectric material being smaller than 2.5 at the maximum transmission wavelength of the filter, one of the second dielectric layers of each filter level being identical to the insulating layer of the adjacent interconnection level.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of French patent application number 15/54830, which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

BACKGROUND

The present disclosure relates to a method of forming an infrared filter associated with an image sensor.

DISCUSSION OF THE RELATED ART

Image sensors formed of a pixel array are here considered.

FIG. 1schematically shows three pixels of a pixel array of a conventional color image sensor. A semiconductor substrate10has pixels of different colors formed thereon, in the shown example, a blue pixel12B, a green pixel12G, and a red pixel12R. Each pixel comprises a photodetection area14B,14G,14R formed in substrate10. Charge transfer elements16B,16G,16R, in the shown example, MOS transistors, are provided. The photodetection areas are insulated from one another by insulating trenches18formed in substrate10.

Substrate10has a stack of interconnection levels comprising metal tracks20embedded in an insulating material22provided thereabove. Color filters24B,24G,24R are formed at the surface of the stack of interconnection levels and are covered with microlenses25. Pixels provided with filters selecting a band in the red or near infrared range, particularly in a wavelength range between 600 nm and 1,100 nm are also sometimes provided, for example, for distance measurements between the sensor and an object, in which case the bandwidth should be narrow to suppress the signal originating from the scene.

Further, it is known that interference filters may be obtained by successive depositions of an alternation of dielectric layers having low and high optical indexes. The number of alternated layers and their thicknesses determine the properties of the filter.

As shown inFIG. 2which corresponds to FIG. 10 of U.S. Pat. No. 5,398,133, an infrared bandpass filter has been formed by the association of a high-pass filter26and of a low-pass filter28. An alternation of layers (26-1to26-14) of amorphous silicon (high optical index) and of silicon nitride (low optical index) forms the high-pass filter on a glass substrate6. An alternation of layers (28-1to28-13) of the same materials forms the low-pass filter on glass substrate6. The thickness of each layer is different. This type of filter has the advantage of having a high transmission and a narrow bandwidth.

Such filters may be deposited at the surface of the interconnection levels of an image sensor, but do not enable to filter a band of the visible range, particularly in a wavelength range between 400 nm and 600 nm, due to the absorption of amorphous silicon. Another disadvantage of the filter described in document U.S. Pat. No. 5,398,133 is that it comprises many layers and has a large total thickness. Another disadvantage is that, if such a filter is deposited at the surface of the interconnection levels of an image sensor, the presence of the filter increases all the more the distance of the microlenses to the silicon substrate. It may then be difficult to obtain an efficient focusing.

SUMMARY

There is a need for an image sensor incorporating filters in infrared and possibly, further, in the visible range, of simple structure.

Thus, an embodiment provides a method of simultaneously forming an infrared bandpass filter on a filter side and interconnection levels on an interconnect side of an image sensor, comprising the steps of:

a) forming a first layer of a dielectric material having a refraction index smaller than 2.5 at the maximum transmission wavelength of the filter on a semiconductor substrate;

c) depositing at least one silicon layer having a first thickness;

d) removing, on the interconnect side, said at least one silicon layer;

e) depositing a second layer of the dielectric material having a second thickness greater than the first thickness;

f) forming in the second layer metal tracks and interconnection vias, on the interconnect side;

g) planarizing the surface to a level corresponding to the level of the surface of the second layer, where the second layer does not cover said at least one silicon layer; and

h) repeating steps b) to g) at least once, the values of the first and second thicknesses being selected from one repetition to another, according to calculations implying a simulation step and/or according to the desired electric performances.

According to an embodiment, the silicon is amorphous silicon.

According to an embodiment, the dielectric material is silicon oxide.

According to an embodiment, the first and second layers and the silicon layer are deposited at a temperature in the range from 350° C. to 400° C.

According to an embodiment, the first and second layers and the silicon layer are deposited at the same temperature.

According to an embodiment, the method further comprises the step of removing the etch stop layer on the filter side before proceeding to step c).

According to an embodiment, said at least one silicon layer comprises an alternation of amorphous silicon layers and of silicon oxide layers.

According to an embodiment, the etch stop layer is made of silicon nitride, of SiCH, or of SiOCH.

According to an embodiment, the method further comprises forming, before step b), an electric connection with an element of the semiconductor substrate or with a gate of a field-effect transistor formed on the semiconductor substrate.

An embodiment also provides an image sensor having a portion comprising: interconnection levels formed on a semiconductor substrate covered with a first layer of a dielectric material, comprising conductive tracks separated from one another by insulating layers, interconnected by vias crossing the insulating layers; and an infrared bandpass filter comprising filter levels adjacent to the interconnection levels formed by an alternation of second layers of the dielectric material and of silicon layers, the refraction index of the dielectric material being smaller than 2.5 at the maximum transmission wavelength of the filter, one of the second dielectric layers of each filter level being identical to the insulating layer of the adjacent interconnection level.

According to an embodiment, the sensor comprises, at the surface of said portion of the image sensor and opposite the infrared bandpass filter, an alternation of third layers of materials having different optical indexes, adding at least one filter level to the infrared bandpass filter.

According to an embodiment, the sensor further comprises at least one optical filter formed by a resin layer opaque to the wavelengths of the visible range and transparent to infrared wavelengths, arranged at the surface of said portion and opposite the infrared bandpass filter.

According to an embodiment, the sensor comprises at least one optical filter, formed by an alternation of at least partially transparent metal layers and of fourth dielectric layers, arranged at the surface of said portion of the image sensor and opposite the infrared bandpass filter.

According to an embodiment, the sensor further comprises areas dedicated to the visible range comprising color filters arranged at the surface of said portion of the image sensor.

According to an embodiment, the color filters are formed of an alternation of at least partially transparent metal layers and of fifth dielectric layers.

According to an embodiment, the color filters are colored resins.

According to an embodiment, the sensor comprises first and second wafers, each having a front surface and a rear surface, the first wafer comprising on its rear surface a first semiconductor substrate having a first photodetection area sensitive to infrared radiation;

the second wafer comprising on its rear surface a second semiconductor substrate having a second area comprising pixels sensitive to visible radiation and having a third area transparent to the infrared radiation, at least one of the first wafer or of the second wafer comprising on its front surface side a structure comprising the interconnection levels and the filter levels; and

the front surface of the first wafer being placed against the front side of the second wafer, to align with the first area the third area, the filter levels, the alignment of said filter levels forming an infrared bandpass filter.

An embodiment also provides a system comprising:

a laser source intended to project an infrared radiation on at least one object; and

an image sensor such as previously defined, capable of detecting the radiation reflected by the object.

DETAILED DESCRIPTION

The same elements have been designated with the same reference numerals in the different drawings and, further, the various drawings are not to scale. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and are detailed herein.

In the following description, when reference is made to terms qualifying absolute positions, such as terms “left-hand”, “right-hand”, or relative positions, such as terms “upper”, “lower”, or to terms qualifying orientation, such as term “vertical”, reference is made to the orientation of the drawings. Unless otherwise specified, words “approximately”, “substantially” mean to within 10%, preferably to within 5%.

FIGS. 3A to 3Jillustrate steps of a first embodiment of a method of simultaneously manufacturing an alternation of layers forming, on the one hand, interconnection levels (left-hand side of the drawings) and, on the other hand, an infrared filter (right-hand side of the drawings).

This method particularly applies to the case where an image sensor having its structure comprising at least one pixel dedicated to infrared is desired to be formed. The following description will be made in the specific case where a semiconductor substrate1has been previously coated with an insulating layer2, for example, made of silicon oxide (SiO2), where an electric connection3with an element of semiconductor substrate1or a MOS transistor gate has been prepared.

In a first step illustrated inFIG. 3A, an etch stop layer4-1has been deposited on SiO2 layer2.

At the step ofFIG. 3B, etch stop layer4-1has been removed on the right-hand side so that it covers SiO2 layer2on the left-hand side only.

At the step ofFIG. 3C, a layer5-1of amorphous silicon (α-Si), of thickness e1, has been deposited.

At the step ofFIG. 3D, α-Si etch stop layer5-1has been removed on the left-hand side so that it covers SiO2 layer2on the right-hand side only.

At the step ofFIG. 3E, a layer6-1of a dielectric material having a low refraction index at the 850-nm wavelength, particularly having a refraction index smaller than 2.5, preferably smaller than 2, of thickness e2 greater than thickness e1, has been deposited. The dielectric material may be SiO2 or a dielectric of low permittivity (low-k), that is, having a relative permittivity smaller than that of SiO2, which is approximately from 3.6 to 850 nm, particularly a mineral-type material based on Si—O, comprising organic materials or hydrides, such as described in patent EP 1109221. Reference7-1designates the upper surface of layer6-1, where layer6-1covers none of layers4-1and5-1. In the case where the dielectric material is SiO2, the etch stop layer is for example a silicon nitride layer (SiN). In the case where the dielectric material is a material of low permittivity, the etch stop layer for example is a SiCH or SiOCH layer.

At the step ofFIG. 3F, a portion of layer6-1of SiO2 forming a recess10-1having a depth smaller than e2 has been etched on the left-hand side. Vertically in line with connection3, a second etching has been performed in recess10-1down to etch stop layer4-1, thus forming a recess11-1narrower than recess10-1. It should be understood that a plurality of recesses of different shapes and sizes may be simultaneously formed.

At the step ofFIG. 3G, the portion of etch stop layer4-1located at the bottom of recess11-1has been removed, after which a metal12-1, for example, copper, coming into contact with connection3at the bottom of recess11-1, has been deposited. Conventionally, this deposition may be preceded by the deposition of diffusion barrier layers (not shown) for example, Ti, Ta, TiN, TaN layers.

At the step ofFIG. 3H, the structure has been planarized to remove all the layers located above surface7-1. Such a planarization may be carried out, for example, by a chem.-mech. polishing method (CMP). The metal12-1remaining in recesses10-1and11-1respectively form a conductive track15-1and a via16-1connecting track15-1to connection3.

As a variation, the forming of layer6-1of SiO2 may successively comprise depositing a first SiO2 sub-layer, depositing an etch stop layer, for example, made of SiN, and depositing a second SiO2 sub-layer. The total thickness of the first SiO2 sub-layer and of the etch stop layer is equal to the desired thickness of via16-1and the thickness of the second SiO2 sub-layer is equal to the thickness of track15-1. This enables to better control the thicknesses of each SiO2layer. An example of a method of manufacturing conductive track15-1and via16-1by a method comprising depositing a plurality of insulating sub-layers is described in patent EP 1109221.

FIG. 3Iillustrates a repetition of the succession of steps ofFIGS. 3A to 3E, on the structure ofFIG. 3H. Thus, the following succession of steps has been carried out:depositing an etch stop layer4-2on layer6-1;removing etch stop layer4-2on the right-hand side;depositing a layer5-2of α-Si of thickness e12;removing layer5-2of α-Si on the left-hand side; anddepositing a layer6-2of SiO2 having a thickness e22 greater than thickness e12. Reference7-2designates the upper surface of layer6-2, where layer6-2covers none of layers4-2and5-2.

FIG. 3Jillustrates the result of the succession of steps ofFIGS. 3F to 3H, on the structure ofFIG. 3I. Thus, the following succession of steps has been carried out:etching in layer6-2of SiO2, on the interconnect side, a first recess having a depth smaller than e22;etching, inside of the first recess, a second recess in layer6-2, narrower than the first recess, all the way to etch stop layer4-2;removing the portion of etch stop layer4-2located at the bottom of the second recess;depositing a metal layer forming, in the recesses, a conductive track15-2and a via16-2connecting track15-2to track15-1; andplanarizing the structure at the level of surface7-2.

A stack of two interconnection levels on the left-hand side of the drawing and a stack of two infrared filter levels have thus been formed on the right-hand side of the drawing by using common steps.

The alternation of layers of SiO2 and of amorphous silicon forms an infrared filter having its filtering properties depending on the number of layers and on their thicknesses.

If a structure having more than two interconnection levels is provided, the process will be repeated and the number of alternated layers of amorphous silicon and of SiO2 will be increased. Optical simulation software is used to determine the thicknesses of the amorphous silicon layers to form infrared filters with the desired properties, according to the SiO2 thicknesses optimized to obtain the desired electric performance, particularly in terms of stray capacitances between levels, according to the interconnection density which can be achieved.

As a variation, if a structure having more than two interconnection levels is provided, an amorphous silicon layer may not be present at each interconnection level.

The inventors have shown that, surprisingly, it is possible to obtain an infrared filter having an adequate spectral response, despite the small number of layers of the infrared filter, and despite the specific constraints due to the fact that the infrared filter is formed simultaneously to interconnection levels, particularly the fact that each layer6-1,6-2of SiO2 has a thickness imposed after the planarization by the desired electric performances of the interconnection levels and that the position of the base of each layer5-1,5-2of α-Si is imposed by the desired electric performances of the interconnection levels.

If insulating layer2or insulating layers6-1,6-2had abrupt sides resulting, in particular, from an etching, there would be a risk, on etching of conformally-deposited amorphous silicon layer5-1,5-2, for amorphous silicon to remain in unwanted fashion on the abrupt sides of the insulating layer. Advantageously, in the present embodiment, insulating layer2,6-1,6-2is substantially planar and comprises no abrupt sides.

FIGS. 4A to 4Eillustrate steps of a second embodiment of a method of simultaneously manufacturing an alternation of layers forming, on the one hand, an infrared filter and, on the other hand, interconnection levels of an image sensor structure on a semiconductor substrate1.

As illustrated inFIG. 4A, it is started from a structure identical to that previously described in relation withFIG. 3A.

At the step ofFIG. 4B, a layer5-1of amorphous silicon (α-Si), having a thickness e1, has been deposited on etch stop layer4-1.

At the step ofFIG. 4C, the following succession of steps has been carried out:removing by etching layer5-1of α-Si on the left-hand side so that it covers etch stop layer4-1only on the right-hand side, where the etch stop layer is not etched; anddepositing a layer6-1of SiO2 having a thickness e2 greater than e1.

Reference8-1designates the upper surface of layer6-1, where layer6-1does not cover layer5-1of α-Si.

At the step ofFIG. 4D, the following succession of steps has been carried out:etching in layer6-1of SiO2, on the left-hand side, a first recess having a depth smaller than e2;etching, inside of the first recess and opposite connection3, a second recess in layer6-1, narrower than the first recess, all the way to etch stop layer4-1;removing the portion of etch stop layer4-1located at the bottom of the second recess;depositing a metal layer forming, in the recesses, a conductive track15-1and a via16-1connecting track15-1to connection3; andplanarizing the structure at the level of surface8-1.

At the step ofFIG. 4E, the succession of steps ofFIGS. 4A to 4Dhas been repeated on the structure ofFIG. 4D. Thus, the following succession of steps has been carried out:depositing an etch stop layer4-2on SiO2 layer6-2;depositing a layer5-2of α-Si of thickness e12;removing layer5-2of α-Si on the left-hand side;depositing a layer6-2of SiO2 having a thickness e22 greater than thickness e12. Reference8-2designates the upper surface of layer6-2, where layer6-2does not cover layer5-2of α-Si;etching in layer6-2of SiO2, on the left-hand side, a first recess having a depth smaller than e22;etching, inside of the first recess, a second recess in layer6-2, narrower than the first one, all the way to etch stop layer4-2;removing the portion of etch stop layer4-2located at the bottom of the second recess;depositing a metal layer forming, in the recesses, a conductive track15-2and a via16-2connecting track15-2to track15-1; andplanarizing the structure at the level of surface8-2.

A stack of two interconnection levels on the left-hand side of the drawing and a stack of two infrared filter levels on the right-hand side of the drawing have thus been formed by using common steps.

As in the case ofFIGS. 3A to 3J, if more than two interconnection levels are provided, the process will be repeated and the number of alternated amorphous silicon, SiO2, and etch stop layers will be increased. Similarly, simulation software is used to determine the thicknesses of the amorphous silicon layers, according to the thickness of the SiO2 and etch stop layers imposed by the forming of the interconnection levels, to form infrared filters having the desired properties. As in the case ofFIGS. 3A to 3J, if a structure having more than two interconnection levels is provided, the presence of an amorphous silicon layer at each interconnection level may not be necessary.

FIGS. 5A to 5Eillustrate steps of a third embodiment of a method of simultaneously manufacturing an alternation of layers forming, on the one hand, an infrared filter and, on the other hand, interconnection levels of an image sensor structure on a semiconductor substrate1.

As illustrated inFIG. 5A, it is started from a structure identical to that previously described in relation withFIG. 3A.

At the step ofFIG. 5B, instead of depositing a single amorphous silicon layer (α-Si) as in the case ofFIGS. 3C and 4B, an alternation20-1of layers of SiO2 and of α-Si has been deposited on etch stop layer4-1. This alternation20-1of layers comprises, in the shown example, a SiO2 layer21-1, a α-Si layer22-1, another SiO2 layer23-1, and another α-Si layer24-1. Alternation20-1of layers has a total thickness e3.

At the step ofFIG. 5C, the following succession of steps has been carried out:removing the alternation of layers20-1on the left-hand side; anddepositing a layer6-1of SiO2 having a thickness e2 greater than thickness e3. Reference8-1designates the upper surface of layer6-1, where layer6-1does not cover the alternation of layers20-1.

At the step ofFIG. 5D, the following succession of steps has been carried out: etching in layer6-1of SiO2, on the left-hand side, a first recess having a depth smaller than thickness e2;etching, inside of the first recess and vertically above connection3, a second recess in layer6-1, narrower than the first recess, all the way to etch stop layer4-1;removing the portion of etch stop layer4-1located at the bottom of the second recess;depositing a metal layer forming, in the recesses, a conductive track15-1and a via16-1connecting track15-1to connection3; andplanarizing the structure at the level of surface8-1.

At the step ofFIG. 5E, the succession of steps ofFIGS. 5A to 5Dhas been repeated on the structure ofFIG. 5D. Thus, the following succession of steps has been carried out:depositing an etch stop layer4-2on layer6-1;depositing an alternation of layers20-2of SiO2 and of α-Si on etch stop layer4-2. This alternation of layers20-1comprises, in the shown example, a SiO2 layer21-1, a α-Si layer22-1, another SiO2layer23-1, and another α-Si layer24-1. The alternation of layers20-1has a total thickness e32;removing the alternation of layers20-2on the left-hand side;depositing a layer6-2of SiO2 having a thickness e22 greater than thickness e32. Reference8-2designates the upper surface of layer6-2, where layer6-2does not cover the alternation of layers20-2;etching in layer6-2of SiO2, on the left-hand side, a first recess having a depth smaller than thickness e32;etching a narrower second recess in layer6-2, located inside of the first recess, all the way to etch stop layer4-2;removing the portion of etch stop layer4-2located at the bottom of the second recess;depositing a metal layer forming, in the recesses, a conductive track15-2and a via16-2connecting track15-2to track15-1; andplanarizing the structure at the level of surface8-2.

A stack of two interconnection levels on the left-hand side of the drawing and a stack of a plurality of infrared filter levels on the right-hand side of the drawing have thus been formed by using common steps.

As in the case ofFIGS. 3A to 3J and 4A to 4E, if more than two interconnection levels are provided, the process will be repeated and the number of alternated amorphous silicon, SiO2 and etch stop layers will be increased. Simulation software is used to determine the thicknesses of the alternated amorphous silicon and SiO2 layers, according to the thickness of the SiO2 and etch stop layers imposed by the forming of the interconnection levels, to form infrared filters having the desired properties.

In the previously-described embodiments, the depositions of the different layers should be performed at a temperature lower than or equal to 400° C. to avoid damaging the layers forming the interconnections already present. The metal, silicon oxide, and amorphous silicon layers are for example formed by physical vapor deposition (PVD). As a variation, the silicon oxide and amorphous silicon layers may be deposited by plasma-enhanced chemical vapor deposition (PECVD). In this case, the deposition temperature of these two materials alternately stacked in the filter should be identical and greater than 350° C. to give a mechanical, morphological and thermal stability to the stacks. This deposition method is advantageous in the context of a process comprising a final anneal at approximately 400° C. Indeed, the inventors have observed a tendency to delamination at certain α-Si and SiO2 interfaces after anneal at 400° C., for filter levels deposited at a temperature lower than 350° C. by PECVD.

In the previously-described embodiments, thicknesses e2, e22 of the SiO2 layers have values substantially in the range from 150 nm to 650 nm Thicknesses e1, e12, (or e3, e32) of the amorphous silicon layers (or of the alternations of α-Si and SiO2 layers) have values substantially in the range from 50 nm to 200 nm. The etch stop layers have values substantially in the range from 20 nm to 50 nm.

The total thickness of a stack of layers deposited according to an embodiment of the previously-described method is substantially in the range from 0.5 μm to 10 μm, preferably from 1 μm to 3 μm.

FIG. 6Ais a cross-section view of an image sensor formed on a semiconductor substrate1comprising photodetection areas100. The substrate is coated with a layer2of SiO2 where a connection3with an element of semiconductor substrate1or a MOS transistor gate has been prepared. A stack of interconnection levels is shown on the left-hand side of the drawing and a stack of filter levels is shown on the right-hand side of the drawing. These stacks are formed according to a method corresponding to the first embodiment described in relation withFIGS. 3A to 3J.

The left-hand side ofFIG. 6Acorresponds to a stack of four interconnection levels similar to the interconnection levels shown on the left-hand side ofFIG. 3J. This stack of levels comprises conductive tracks15-1,15-2,15-3separated from one another by insulating layers6-1,6-2,6-3,6-4and interconnected by vias16-1,16-2,16-3crossing the insulating layers. As an example of embodiment, the last interconnection level comprises a connection pad17protruding from the surface of the upper portion of the image sensor. Such an interconnection configuration has been shown as an example only. Various configurations of interconnection levels are possible.

The right-hand side of the drawing corresponds to two pixels dedicated to infrared P1. This side comprises a stack of four filter levels similar to the filter levels shown on the right-hand side ofFIG. 3J. This stack of levels comprises an alternation of insulating layers2,6-1,6-2,6-3,6-4and of amorphous silicon layers5-1,5-2,5-3,5-4forming an infrared filter.

Conventionally, at least one passivation layer30is deposited at the surface of the interconnection and filter levels. Layer30is open opposite pad17. A final anneal, for example, for 2 hours at 400° C. in a N2H2 atmosphere, may be carried out after the deposition of layer30.

A resin layer40substantially opaque for visible light and transparent to infrared, currently called “black resin” has been deposited at the surface of passivation layer30on the right-hand side of the drawing, above the stack of filter levels. A microlens41is arranged on resin layer40, vertically above each photodetection area100. Each pixel P1comprises a photodetection area, an infrared filter, a black resin, and a microlens.

FIG. 6Bis a diagram showing transmission T of the filter ofFIG. 6A, according to wavelength λ. Curve C1corresponds to the transmission of the filter with no black resin40and curve C2corresponds to the transmission of the filter in the presence of a black resin layer40. Black resin40enables to suppress the parasitic transmission of the filter in the visible range. These curves correspond to the case where the thicknesses of the deposited layers are the following:

In this configuration, the transmission peak is at a wavelength of substantially 850 nm and is greater than 80%. The width at half maximum of this peak is substantially 25 nm Such performances are compatible with the use of the image sensor as a distance sensor implementing a time-of-flight measurement or TOF method where the width at half maximum of the peak should be generally in the range from 20 nm to 50 nm and the transmission maximum should be greater than 80%.

FIG. 7is a cross-section view of an image sensor formed on a semiconductor substrate1comprising photodetection areas101,102,103, and104.

The left-hand side of the drawing, comprising interconnection levels and a pixel P1provided with an infrared filter, is identical to the representation ofFIG. 6A(for a single pixel P1). The common elements are designated with the same reference numerals and will not be detailed again herein.

The right-hand portion of the drawings shows pixels P2, P3, P4, dedicated to the visible range, each being provided with a visible light filter42,43,44arranged vertically above photodetection areas102,103, and104. The three filters42,43,44respectively filter the red, green, and blue colors (RGB). These filters are for example of the type illustrated inFIG. 4Bof US patent application No 2012/0085944 of the applicant and comprising an alternation of metal layers sufficiently thin to be transparent and of dielectric layers. The dielectric layers are selected to be transparent to the selected colors (RGB).

A planarization layer50places at a single level the surface above the three filters42,43,44and black resin layer40. For each of pixels P1, P2, P3, and P4, a microlens41is arranged on the planar surface formed by layer50. According to an embodiment, black resin layer40may be formed after the forming of filters42,43,44and of planarization layer50.

FIG. 8illustrates an alternative embodiment of an image sensor similar to that ofFIG. 7, comprising interconnection levels, one pixel dedicated to infrared and three pixels dedicated to the visible range. The elements common toFIGS. 8 and 7are designated with the same reference numerals and will not be detailed again herein. InFIG. 8, black resin layer40ofFIG. 7has been replaced with an infrared filter45formed by an alternation of metal and dielectric layers in the same way as filters42,43, and44ofFIG. 7. Advantageously, filter45may be formed at least partly simultaneously with filters42,43, and44. Infrared filter45cannot perform a filtering alone on a reduced frequency range, which is necessary for the use of the image sensor as a TOF-type distance sensor. Indeed, filter45cannot comprise a large number of insulating and metal layers due to the fact that the absorption rate of the metal layers may be large and that the thicknesses of filters42,43,44, and45should be equal. This is why infrared filter45should be associated with the infrared filer corresponding to the stack of amorphous layers5-1,5-2,5-3, and5-4and of silicon oxide layers6-1,6-2,6-3, and6-4.

According to another embodiment, filter45is replaced with an infrared filter comprising an alternation of SiO2 layers and of amorphous Si layers. This advantageously enables to increase the transmission of the infrared filter formed on passivation layer30. Preferably, each filter42,43, and44comprises amorphous silicon layers in addition to the insulating layers and to the metal layers, and the infrared filter may be formed at least partly simultaneously with filters42,43, and44, the metal layers being etched above infrared pixel P1after each deposition.

FIG. 9illustrates another embodiment of an image sensor similar to that ofFIG. 7. The elements common withFIGS. 9 and 7are designated with the same references and will not be detailed again herein. InFIG. 9, the filters formed by an alternation of metal and dielectric layers42,43,44ofFIG. 7have been replaced with resins52,53, and54respectively red, green and blue.

An image sensor similar to the embodiments ofFIG. 7, 8, or9may be provided, where the layers (40or45) deposited at the surface of passivation layer30and opposite the infrared bandpass filter are replaced with an alternation of amorphous silicon layers, of silicon oxide layers and, according to an embodiment, of etch stop layers. This alternation forms at least one filter level similar to the filter levels manufactured according to an embodiment of the previously-described method which collaborates with the filter levels to form the infrared bandpass filter.

Image sensors comprising a semiconductor substrate having a surface, called front surface, coated with an interconnection structure and intended to receive an illumination, has been described up to now.

Image sensors comprising a semiconductor substrate having a first surface, called front surface, and having a second surface, called rear surface, intended to receive an illumination, coated with an interconnection structure, are also known. This type of structure is currently used in the art for image sensors in the visible range. However, the photodetection areas dedicated to infrared need a significant semiconductor thickness which is little compatible with the forming of back-side illuminated sensors.

FIG. 10illustrates the association of a back-side illuminated visible light sensor and of a front-side illuminated infrared sensor. For the infrared sensor, the interconnection and filter levels are manufactured according to an embodiment of the previously-described method.

A first wafer60comprises a semiconductor substrate61coated with a SiO2 layer62and comprising a photodetection area64dedicated to infrared. A first interconnection structure65has been manufactured according to an embodiment of the previously-described method, comprising interconnection levels66and first infrared filter levels67. Infrared filter levels67are arranged opposite photodetection area64.

A second wafer70comprises a thinned semiconductor substrate71comprising photodetection areas72,73,74dedicated to the visible range and configured for a back-side illumination, as well as a transparent free space75. According to an embodiment, free space75advantageously corresponds to an area of semiconductor substrate71. Second wafer70comprises a second interconnection structure76placed, for example by molecular bonding, against the first interconnection structure65. Second structure76is manufactured according to an embodiment of the previously-described method and comprises interconnection levels77and second infrared filter levels78. This structure is arranged on the lower surface side of thinned semiconductor substrate74. Each photodetection area is coated with a color filter81,82,83, forming pixels P7, P8, P9dedicated to the visible range. Free space75is located opposite second filter levels78and is coated with a black resin layer84. Second filter levels78are aligned and cooperate with the first infrared filter levels67to form a single infrared bandpass filter. The alignment of free space75, of black resin84, and of filter levels67,78of the two structures placed against each other with photodetection area64forms a pixel P10dedicated to infrared. Pixel P10is similar to the pixels dedicated to infrared of the previously-discussed embodiments. As a variation, black resin layer84is not present. In this case, semiconductor substrate71may be thicker at the level of area75to form a planar surface with color filters81,82, and83. This advantageously enables to increase the absorption of the visible spectrum at the level of pixel P10. In the present embodiment, an infrared filter level67,78is formed in each wafer60,70. As a variation, an infrared filter level may be formed in one of wafers60or70only. This enables to decrease the number of steps of the sensor manufacturing method. However, the obtained spectral response of the infrared filter may then be less favorable than that obtained with the two infrared filter levels67,78.

This association thus forms an image sensor comprising pixels P7, P8, P9dedicated to the visible range intended to be illuminated on its back side and a pixel P10dedicated to infrared intended to be illuminated on its front side. In practice, configurations of this type are periodically repeated and form a pixel array of an image sensor.

FIG. 11shows a distance measurement system85comprising an image sensor86(Image Sensor), such as previously described, a projector87(Laser), for example, a laser source, and a processing unit88(Processing Unit) connected to laser source87and to image sensor86. Processing unit88may comprise a processor capable of executing a computer program stored in a memory. The operating principle of system85is the following. Laser source87emits a radiation89at the wavelength of the infrared filter of image sensor86. Incident radiation89is reflected on an object90. Image sensor86detects reflected radiation91. According to an embodiment, processing unit88is capable of determining the time taken by the radiation to travel from object90to image sensor86. Such a time-of-flight measurement may be performed independently by each pixel of the image sensor, thus enabling to obtain a full three-dimensional image of object90. According to another embodiment, laser source87is capable of projecting a pattern or a plurality of patterns on the object and image sensor86is capable of acquiring images of object90having the patterns projected thereon. Processing unit88is capable, based on an analysis of the acquired images, of determining a three-dimensional image of object90.

Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, the embodiments shown inFIGS. 7, 8, and 9may be manufactured according to the second embodiment of the method previously described in relation withFIGS. 4A to 4E, according to the third embodiment of the method previously described in relation withFIGS. 5A to 5E, or also according to a combination of the first, second, and third previously-described embodiments of the method.

Although amorphous silicon depositions to manufacture the infrared filter have been described, it should be understood that one may deposit polysilicon layers instead of amorphous silicon.

An antireflection layer formed of a SiO2 layer and of a SiN layer may also be deposited between semiconductor substrate1and layer2of SiO2. The thicknesses of these layers may be, for example substantially 25 nm for SiO2 and substantially 50 nm for SiN.

In the embodiments discussed inFIGS. 6, 7, 8, 9, and 10, it should be understood that the pixels formed by the photodetection areas and the associated filters may form an array of pixels according to a periodic repetition of a given pattern, such as, for example, a Bayer array.

It should be understood that the interconnections are associated with the photodetection areas of the substrates, and that connections17may be arranged at the surface around the pixel array.

It will be within the abilities of those skilled in the art to combine various elements of the various embodiments and variations described hereabove without showing any inventive step.