Power electronics assemblies having embedded power electronics devices

A power electronics assembly includes a circuit board assembly including a first electrically insulating layer, an electrically insulating substrate, a laminate panel provided between the first electrically insulating layer and the electrically insulating substrate, and one or more electrically conductive layers provided within the electrically insulating substrate. The laminate panel includes a power electronics device assembly including an S-cell and a power electronics device. The S-cell includes a graphite layer and a metal layer encasing the graphite layer. A recess is formed in an outer surface of the metal layer and the power electronics device is disposed within the recess of the outer surface of the S-cell.

TECHNICAL FIELD

The present specification generally relates to power electronic assemblies and, more specifically, apparatus and methods for power electronic assemblies having low overall thermal resistance while achieving a compact package size.

BACKGROUND

Due to the increased use of electronics in vehicles, there is a need to make electronic systems more compact. One component of these electronic systems is a power electronic device used as a switch in an inverter. Power electronic devices have large cooling requirements due to the heat generated.

Additionally, there has been a trend for power electronic devices conventionally composed of silicon to now be composed of silicon-carbide. The use of silicon-carbide causes a larger heat flux due to it defining a smaller device footprint. For these reasons, and more, there is a need to improve the cooling of power electronic devices while maintaining a compact package size.

SUMMARY

In one embodiment, a power electronics assembly includes: a circuit board assembly including: a first electrically insulating layer; an electrically insulating substrate; a laminate panel provided between the first electrically insulating layer and the electrically insulating substrate, the laminate panel including: a power electronics device assembly including: an S-cell including: a graphite layer; and a metal layer encasing the graphite layer, a recess formed in an outer surface of the metal layer; and a power electronics device disposed within the recess of the outer surface of the S-cell; and one or more electrically conductive layers provided within the electrically insulating substrate.

In another embodiment, a power electronics assembly includes: a circuit board assembly including: a first electrically insulating layer; an electrically insulating substrate; a laminate panel provided between the first electrically insulating layer and the electrically insulating substrate, the laminate panel including: a plurality of power electronics device assemblies, each power electronics device assembly including: an S-cell including: a graphite layer; and a metal layer encasing the graphite layer, a recess formed in an outer surface of the metal layer; and a power electronics device disposed within the recess of the outer surface of the S-cell; and one or more electrically conductive layers provided within the electrically insulating substrate a plurality of thermal vias thermally coupling each of the power electronics devices to the one or more electrically conductive layers; and a cold plate, the metal layer of each S-cell bonded to the circuit board assembly is bonded to a first surface of the cold plate via the first electrically insulating layer.

In yet another embodiment, a method includes: providing a first electrically insulating layer on a first surface of a cold plate; providing a laminate panel on the first electrically insulating layer opposite the cold plate, the laminate panel including: a power electronics device assembly including: an S-cell including: a graphite layer; and a metal layer encasing the graphite layer, a recess formed in an outer surface of the metal layer; and a power electronics device disposed within the recess of the outer surface of the S-cell; laminating a first two layer circuit pair onto the laminate panel opposite the first electrically insulating layer; laser drilling vias through the first two layer circuit pair; and filling the vias with an electrically conductive material to thermally couple the first two layer circuit pair to the power electronics device.

DETAILED DESCRIPTION

Embodiments described herein are generally directed to power electronics assemblies having a circuit board assembly coupled to a cold plate, the circuit board assembly including a power electronics device assembly that includes an S-cell. A power electronics device may be embedded within the S-cell.

The power electronics device assemblies of the present disclosure comprise a power electronics device affixed to a mounting substrate referred to herein as an S-cell. As described in more detail below, the S-cell includes a graphite layer that provides enhanced heat spreading capabilities. Further, embodiments of the present disclosure include one or more electrical isolation layers that electrically isolate the power electronics device(s) from a cold plate. For example, an electrically insulating layer of the S-cell enables the removal of an electrical insulation layer between the printed circuit board and the cold plate because the electrical isolation is provided by the S-cell itself.

As described in more detail below, the S-cells of the present disclosure provide enhanced thermal properties due to graphite layers that promote heat flux flow toward a cold plate. The S-cells described herein include stacked metal, graphite, and one or more electrically insulating layers in a compact package. The bonding materials described herein for bonding the S-cells are particularly adapted for increased thermal conductivity relative to other bonding technologies, while also maintaining an ability of electrically insulate the S-cells. The devices, systems, and apparatuses described herein improves the heat flux from the S-cell to the cold plate, thereby increasing heat spreading and cooling performance for the circuit board assembly.

The cold plates, power electronics device assemblies, circuit board assemblies, power electronics assemblies, and the like described herein may be used in electrified vehicles, such as and without being limited to, an electric vehicle, a hybrid electric vehicle, any electric motor, generators, industrial tools, household appliances, and the like. The various assemblies described herein may be electrically coupled to an electric motor and/or a battery, and may be configured as an inverter circuit operable to convert direct current (DC) electrical power to alternating current (AC) electrical power.

As used herein, a “power electronics device” means any electrical component used to convert DC electrical power to AC electrical power and vice-versa. Embodiments may also be employed in AC-AC converter and DC-DC converter applications. Non-limiting examples of power electronics devices include power metal-oxide-semiconductor field effect transistors (MOSFET), insulated-gate bipolar transistors (IGBT), thyristors, and power transistors.

As used herein, the phrase “fully embedded” means that each surface of a component is surrounded by a substrate. For example, when a power electronics device assembly is fully embedded by a circuit board substrate, it means that the material of the circuit board substrate covers each surface of the circuit board substrate. A component is “partially embedded” when one or more surfaces of the component are exposed.

As used herein, an “S-cell” is a mounting substrate operable to be affixed to a power electronics device and includes one or more of a metal layer, a graphite layer, and an electrically insulating layer.

Various embodiments of power electronics assemblies, power electronics device assemblies, and cold plates are described in detail below. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

Referring now toFIGS.1and2, an example power electronics assembly100is generally illustrated in an assembled view and an exploded view, respectively. The power electronics assembly100illustrated inFIGS.1and2includes a cold plate102and a circuit board assembly106. The cold plate102may be any device capable of removing heat flux from the power electronics devices140(seeFIG.4) coupled to a substrate material of the circuit board assembly106. Non-limiting examples for the cold plate102include heat sinks, single-phase liquid cooling, two-phase liquid cooling, and vapor chambers.FIGS.1and2illustrate the cold plate102has being configured as a single-phase liquid cooling device. The cold plate102includes a fluid inlet132and a fluid outlet134fluidly coupled to a fluid chamber115(FIG.7) within the cold plate102. WhileFIGS.1and2depict the fluid inlet132and the fluid outlet134as being on the same side of the cold plate102, the present disclosure is not limited to such an embodiment. That is, in other embodiments, the fluid inlet132and the fluid outlet134may be positioned on other surfaces.

Referring again toFIGS.1and2, the circuit board assembly106is coupled (e.g., affixed) to a first surface107of the cold plate102.FIGS.1and2illustrate the circuit board assembly106as being affixed to the first surface107of the cold plate102by way of fasteners101(e.g., bolts and nuts) extending through through-holes105of the cold plate102and through-holes109of the circuit board assembly106. It should be appreciated that, in other embodiments, the through-holes105,109and fasteners101may be omitted, as described below.

In embodiments, the circuit board assembly106may be 3D printed layers. It should be appreciated that in such embodiments, the 3D printed layers of the circuit board assembly106reduce overall thermal resistance. In embodiments, the circuit board assembly106may be laminated to the cold plate102. However, other additive manufacturing processes for affixing the circuit board assembly106to the cold plate102are also contemplated and included within the scope of the present disclosure. In addition, as described in more detail herein, via connections or vias may be made between the various components of the circuit board assembly106and the power electronics devices140(FIG.4) using laser drilling. That is, the vias are drilled through the circuit board assembly106to the top surface of each conductive layer and the power electronics devices140. As described in more detail herein, the vias are then filled with copper via an electroplating method to establish electrical connections between components. Although the circuit board assembly106is generally depicted inFIGS.1and2, the individual layers and various steps of assembly are depicted inFIGS.6-17.

Referring now toFIGS.3-17, the individual steps of manufacturing the power electronics assembly100is depicted. As shown inFIG.3, a first electrically insulating layer180is shown deposited onto the first surface107of the cold plate102to lower the thermal resistance between the circuit board assembly106and the cold plate102(FIG.1). The first electrically insulating layer180may generally be any layer that provides electrical insulation, such as ceramic or the like. In embodiments, the first electrically insulating layer180includes an insulation metal substrate (IMS) dielectric film. The IMS dielectric film may be a solid film layer. In other embodiments, the first electrically insulating layer180may be a thermal grease layer. It is noted that the first electrically insulating layer180may not have dedicated through-holes.

Referring now toFIGS.4and5an exploded top perspective view and an assembled cross-sectional view, respectively, of an example S-cell121is shown. The S-cell121includes a plurality of stacked layers. Particularly, the S-cell121illustrated inFIGS.4and5includes a metal layer122and a graphite layer124embedded within the metal layer122. The metal layer122includes an inner surface125and an outer surface128opposite the inner surface125. In embodiments, the metal layer122includes a first metal layer and a second metal layer with the graphite layer124positioned between the first metal layer and the second metal layer. The metal layer122includes a recess127disposed in the outer surface128of the metal layer122. The recess127is dimensioned to receive a power electronics device140. As described in more detail below, the metal layer122provides an electrically conductive surface to which electrodes on a bottom surface of the power electronics device140are connected (e.g., via a direct connection and/or via electrically connective vias). It should be appreciated that the various layers of the S-cell121depicted inFIGS.4and5is merely illustrative. That is, for example, the S-cell121may include a plurality of graphite layers and/or other layers disposed between metal layers in some embodiments.

It is noted that the S-cell121in the embodiment ofFIGS.4and5includes the graphite layer124embedded within the metal layer122to provide an S-cell121that is symmetrical along a z-axis of the coordinate axes depicted inFIGS.4and5. The symmetrical nature of the S-cell121balances forces on the S-cell121during the high-temperature bonding process. Because the metal layer122and the graphite layer124have different coefficients of thermal expansion, it may be desirable to have a symmetrical substrate stack to balance the thermally induced stresses during the bonding process.

The metal layer122may be made of any suitable metal or alloy. Copper and aluminum may be used as the metal layer as non-limiting examples. The metal layer122of the S-cell121has a recess127formed in the outer surface128thereof. The recess127may be formed by chemical etching, for example. The recess127has a size and shape to accept the power electronics device140. The outer surface128may generally be a second major face or surface of the metal layer122that is opposite the inner surface125(which is configured as a first major face or surface of the metal layer122). That is, the metal layer122may be a planar layer whereby the inner surface125faces the graphite layer124and the opposite outer surface128faces the power electronics device140and the circuit board assembly106(FIG.7).

The graphite layer124depicted in the embodiment ofFIG.5is provided to encourage heat spreading both across the S-cell121as well as toward the cold plate102(see, e.g.,FIG.7). The crystalline structure of graphite provides the graphite with high thermal conductivity, making it useful to conduct heat flux toward the cold plate102. However, graphite does not have an isothermal profile. Rather, graphite has an anisothermal profile with high conductivity along two axes and low thermal conductivity in a third axis. To account for the anisothermal profile of graphite, the S-cell121is designed to be rectangular in shape such that its length dimension is greater than its width dimension. Referring toFIG.5, the graphite layer124has high thermal conductivity along the x-axis and the z-axis of the coordinate axes depicted inFIG.5. Thus, the S-cell121is designed such that its dimension along the x-axis is larger than its dimension along the y-axis. Heat flux will travel along the x-axis and z-axis. As described in more detail below, heat flux is moved by the S-cell121along the x-axis toward the cold plate102. Heat flux will also travel along the z-axis toward the cold plate102.

Referring again toFIG.4, an exploded view of a power electronics device assembly146is depicted including the S-cell121and the power electronics device140.FIG.4depicts the power electronics device140and a bonding layer143with respect to the recess127of the S-cell121. The bonding layer143may be a solder layer, for example. As another example, the bonding layer143may be a transient liquid phase bonding layer143. The power electronics device140includes a plurality of large electrodes141and a plurality of small electrodes142on its top surface. The large electrodes141may be power electrodes, while the small electrodes142may be signal electrodes. It is noted that, although not visible inFIG.4, the power electronics device140further includes one or more electrodes on its bottom surface. The one or more electrodes on the bottom surface of the power electronics device140are electrically connected to the metal layer122by placement of the power electronics device140into the recess127. Thus, electrical connection to the bottom electrodes of the power electronics device140may be made by way of the metal layer122.

As stated above, the S-cell121is a substrate to which the power electronics device140is bonded. The S-cell121provides an electrically conductive surface area to make connections to electrodes on the bottom surface of the power electronics device140. The S-cell121further provides heat spreading functionality as well as electrical isolation.

Referring now toFIG.6, a laminate panel200including one or more power electronics device assemblies146surrounded by a laminate material202are provided on the first electrically insulating layer180opposite the cold plate102. In embodiments, the laminate material202includes FR-4, however, alternative materials are within the scope of the present disclosure. As shown, a total of six power electronics device assemblies146are provided and bonded to the cold plate102via the first electrically insulating layer180and the laminate material202in two rows of three. However, it should be understood that any number of power electronics device assemblies146may be utilized depending on the application.

Referring now toFIG.7, a cross-sectional view of the power electronics assembly100is illustrated. Cooling fluid (depicted as moving arrows135) from a reservoir (not shown) flows into the fluid chamber115through the fluid inlet132and out of the fluid chamber115through the fluid outlet134as warmed cooling fluid, where it is returned to the reservoir, such as after flowing through a heat exchanger (not shown) to remove heat from the cooling fluid135. Although not shown, an array of fins may be provided in the fluid chamber115to provide additional surface area for heat transfer to the cooling fluid135.

As shown, the laminate panel200is provided between the first electrically insulating layer180and a second electrically insulating layer204. It should be appreciated that the second electrically insulating layer204may include the same material as the first electrically insulating layer180.

Referring still toFIG.7, a first two layer circuit pair206is shown positioned above the second electrically insulating layer204forming the circuit board assembly106. The first two layer circuit pair206includes a first electrically conductive layer208and a second electrically conductive layer210laminated by a third electrically insulating layer212therebetween. In embodiments, the first electrically conductive layer208and the second electrically conductive layer210are copper layers. The first electrically conductive layer208is etched to the specified pattern to guide current while the second electrically conductive layer210remains unetched.

Referring now toFIG.8, the first two layer circuit pair206is positioned onto the second electrically insulating layer204. The first two layer circuit pair206is laminated to the second electrically insulating layer204in a high-temperature, high pressure chamber. During this lamination step, material from the second electrically insulating layer204and the third electrically insulating layer212fills gaps defined by the etching of the first electrically conductive layer208.

Referring now toFIG.9, vias112are formed to extend between any combination of the power electronics devices140of the power electronics device assemblies146, the first electrically conductive layer208, and the second electrically conductive layer210. For example, vias112are shown extending between the power electronics device140of each power electronics device assembly146and the second electrically conductive layer210and through the first electrically conductive layer208. Additionally, vias112(both electrically conducting vias and thermal vias) are shown extending between the first electrically conductive layer208and the second electrically conductive layer210without intersecting the power electronics devices140. The vias112may be formed in any suitable manner such as, for example, laser drilling. It should be appreciated that the scope of the present disclosure is not limited to the particular configuration of vias112depicted inFIG.9and other configurations are contemplated based on the specific needs of the circuit board assembly106.

The vias112may provide drive signals to the power electronics devices140, as well as provide a current path for switching current. It is noted that, in some embodiments, some of the vias112may be configured as thermal vias that do not conduct drive signals or switching current. In addition, the S-cell arrangement allows for flux movement from the power electronics device140to the cold plate102via the S-cell121, as described herein. In this way, heat flux is optimally directed away from the power electronics devices140and toward the cold plate102via the S-cell121.

Referring now toFIG.10, the vias112are filled with copper by electroplating to form electrical connections between each power electronics device assembly146, the first electrically conductive layer208, and the second electrically conductive layer210. However, it should be appreciated that the vias112may be filled in any other suitable manner other than electroplating.

Referring now toFIG.11, after the first two layer circuit pair206is laminated to the laminate panel200via the second electrically insulating layer204, the second electrically conductive layer210may be etched to the desired configuration based on the specifications of the circuit board assembly106. It should be appreciated that the circuit board assembly106may include any number of electrically conductive layers. For example, the circuit board assembly106may include only the first electrically conductive layer208and the second electrically conductive layer210. In such an embodiment, one or more surface mounted electronics (such as surface mounted electronics214depicted inFIG.17) such as, for example, transistors, resistors, capacitors, and the like, may be mounted to the second electrically conductive layer210. However, in other embodiments, the circuit board assembly106may include a plurality of two layer circuit pairs with the surface mounted electronics mounted to the upper most electrically conductive layer. In doing so, the steps described herein with respect toFIGS.7-11may be repeated with each additional two layer circuit pair to be laminated to a previous two layer circuit pair.

For example, referring now toFIG.12, a fourth electrically insulating layer216is provided on the second electrically conductive layer of the first two layer circuit pair206and a second two layer circuit pair218is shown positioned above the first two layer circuit pair206. The second two layer circuit pair218includes a third electrically conductive layer220and a fourth electrically conductive layer222laminated by a fifth electrically insulating layer224therebetween. In embodiments, the third electrically conductive layer220and the fourth electrically conductive layer222are copper layers. The third electrically conductive layer220is etched to the specified pattern to guide current while the fourth electrically conductive layer222remains unetched.

Referring now toFIG.13, the second two layer circuit pair218is positioned onto the first two layer circuit pair206. The second two layer circuit pair218is laminated to the first two layer circuit pair206in a high-temperature, high pressure chamber. During this lamination step, material from the second electrically insulating layer204and the third electrically insulating layer212fills gaps defined by the etching of the second electrically conductive layer210. Additionally, material from the fourth electrically insulating layer216and the fifth electrically insulating layer224fills gaps defined by the etching of the third electrically conductive layer220. It should be appreciated that, in embodiments, the electrically insulating layers204,212,216,224form a one-piece, monolithic electrically insulating substrate such that the laminate panel200, and specifically the power electronics device assemblies146, are provided within the electrically insulating substrate.

Referring now toFIG.14, additional vias112are formed to extend between any combination of the first electrically conductive layer208, the second electrically conductive layer210, the third electrically conductive layer220, and the fourth electrically conductive layer222. For example, vias112are shown extending between the second electrically conductive layer210and the fourth electrically conductive layer222through the third electrically conductive layer220. Additionally, vias112are shown extending between the third electrically conductive layer220and the fourth electrically conductive layer222without intersecting the power electronics devices140, the first electrically conductive layer208, or the second electrically conductive layer210. As described herein, it should be appreciated that the scope of the present disclosure is not limited to the particular configuration of the vias112depicted inFIG.14and other configurations are contemplated based on the specific needs of the circuit board assembly106.

Referring now toFIG.15, as described herein, the vias112are filled with copper by electroplating to form electrical connections between each power electronics device assembly146, the first electrically conductive layer208, the second electrically conductive layer210, the third electrically conductive layer220, and the fourth electrically conductive layer222, either directly or indirectly.

Lastly, as shown inFIG.16, after the second two layer circuit pair218is laminated to the first two layer circuit pair206via the fourth electrically insulating layer216, the fourth electrically conductive layer222may be etched to the desired configuration based on the specifications of the circuit board assembly106.

Referring now toFIG.17, one or more surface mounted electronics214may be mounted to the fourth electrically conductive layer222. As described herein, the surface mounted electronics214may include, for example, transistors, resistors, capacitors, and the like. Accordingly, it should be appreciated that the circuit board assembly106includes at least the laminate panel200, including the plurality of power electronics device assemblies146, the first two layer circuit pair206, the second two layer circuit pair218, and the surface mounted electronics214.

From the above, it is to be appreciated that defined herein are power electronics assemblies and methods for fabricating the same. Specifically, the power electronics assemblies disclosed herein include a circuit board assembly including a first electrically insulating layer, an electrically insulating substrate, a laminate panel provided between the first electrically insulating layer and the electrically insulating substrate, and one or more electrically conductive layers provided within the electrically insulating substrate. The laminate panel includes a power electronics device assembly including an S-cell and a power electronics device. The S-cell includes a graphite layer and a metal layer encasing the graphite layer. A recess is formed in an outer surface of the metal layer and the power electronics device is disposed within the recess of the outer surface of the S-cell.

It should now be understood that embodiments of the present disclosure are directed to power electronics assemblies having a circuit board assembly coupled to a power electronics device assembly that includes a cold plate containing an S-cell. A power electronics device may be embedded within the S-cell and/or within the circuit board assembly. Such power electronics assemblies are compact, provide increased thermal conductivity while maintaining the ability to electrically insulate S-cells, thereby improving heat flux from the S-cell to the cold plate, thereby increasing heat spreading and cooling performance of the circuit board assembly relative to conventional packages.