Switching between transmit and receive modes in a wireless transceiver

A wireless transceiver decodes a receive signal to extract data contained in the receive signal. A processing block contained in the wireless transceiver then initiates a power-ON of the transmit radio portions of the transceiver prior to initiating a power-OFF of the receive radio portions. The technique enables the transceiver to meet timing requirements when operating in environments that require an acknowledgement to be sent in response to receipt of data.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate generally to wireless transceivers, and more specifically to techniques for switching between transmit and receive modes in a wireless transceiver.

2. Related Art

A wireless transceiver is generally a device that contains both a receiver and a transmitter, and receives and transmits signals wirelessly on a wireless medium. The transmitter of a wireless transceiver may often be non-operational when the receiver is processing (e.g., down-converting and demodulating) a received signal, and the transceiver may be said to be in a receive mode. Similarly, the receiver of the wireless transceiver may be non-operational when the transmitter is processing (e.g., modulating, up-converting and power-amplifying) a signal to be transmitted, and the transmitter may said to be in a transmit mode.

To minimize power consumption, at least some of the components in the receiver may be powered-OFF when the transceiver is in the transmit mode. Similarly, at least some of the components in the transmitter may be powered-OFF when the transceiver is in the receive mode. Switching between transmit and receive modes may, therefore, require powering-ON and powering-OFF respectively of the corresponding receiver and transmitter portions or components. The powering-OFF and powering-ON may be complete or partial, based, for example, on the specific implementation of the wireless transceiver. Thus, powering-OFF may correspond to removal of power for all of the corresponding powered-OFF components/blocks, or only removal of power for some components/blocks (for example, high power-consumption components/blocks) while maintaining other components/blocks in a powered-ON (or low-power/idle) state. Alternatively, power-OFF may also correspond to setting all or some of the components/blocks in a low-power (e.g., idle) states. Similarly, powering-ON may correspond to restoration or application of power to all or only some of the corresponding components/blocks from a no-power, low-power or idle states to full/normal power. Switching between transmit and receive modes may need to be performed fast enough to conform to one or more operational requirements of the transceiver.

SUMMARY

According to an aspect, a wireless transceiver extracts data contained in a received signal. A processing block contained in the wireless transceiver then initiates a power-ON of the transmit radio portions prior to initiating a power-OFF of the receive radio portions of the transceiver.

The techniques enable the transceiver to meet timing requirements when operating in environments that require an acknowledgement to be sent in response to receipt of data. In an embodiment, the features are provided consistent with IEEE 802.11 standards.

The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

DETAILED DESCRIPTION

Various embodiments are described below with several examples for illustration.

1. Example Environment

FIG. 1is a block diagram illustrating an example environment in which several embodiments may be implemented. The example environment is shown containing only representative systems for illustration. However, real-world environments may contain many more systems/components as will be apparent to one skilled in the relevant arts. Further, in the description below, the transceivers and the environment are described as operating consistent with IEEE 802.11, merely for illustration. Implementations in other environments are also contemplated to be within the scope and spirit of various aspects of the present invention.

The diagram is shown containing two Basic Service Sets (BSS)110and120, wired network130, and wired network backbone140. In the example environment shown inFIG. 1, the respective components are assumed to be designed to operate consistent with the 802.11 WLAN standards (including revisions such as 802.11a, 802.11b, 802.11g., 802.11n, etc.). However, the features can be implemented in various other environments as well.

BSS110contains wireless transceivers110A through110E, and access point (AP)110F. Each of wireless transceivers110A through110E may be any electronic/computing device (mobile or fixed) equipped with a wireless network interface card (or similar hardware) that enables wireless communication. For example, wireless transceivers110A through110E may include devices such as laptops, desktops, Personal Digital Assistants (PDA), etc.

AP110F is connected by a wired medium (141) to wired network backbone140, which in turn is connected to wired network130. AP110F provides wireless transceivers110A through110E connectivity with each other. Thus, for example, if wireless transceiver110A is to communicate (transfer data to) with wireless transceiver110C it may do so by first communicating with AP110F, which in turn communicates with wireless transceiver110C. Thus, a wireless transceiver (any of110A-110E) wanting to communicate with another wireless transceiver in BSS110may do so via AP110F. AP110F also provides wireless transceivers110A-110E connectivity to wired network130and transceivers in BSS120. Each of wireless transceivers110A through110E in BSS110may also communicate with each other directly, without requiring the presence of AP110F.

BSS120and constituent components wireless transceivers120A through120E and AP120F operate in a manner similar to that described above with respect to BSS110, and the related description is not repeated here for the sake of conciseness.

All transceivers in BSS110and BSS120may communicate with each other on a shared frequency band such as the 2.4 GHz (or 5.1 GHz) band specified by the WLAN standard. The transceivers could be operating in the same channel or different channels (adjacent or overlapping) within the shared band.

To conserve power, the transmitters of transceivers inFIG. 1may be powered-OFF during a “receive time interval”. A receive time interval is an interval in which a device (e.g., wireless device110A) receives signals. The receivers in the transceivers may similarly be powered OFF during a “transmit time interval”. A transmit time interval is an interval in which a device (e.g., wireless device110A) transmits signals. Wireless communication environments and protocols often require that an acknowledgement be transmitted in response to receiving a “receive” signal, for example a received data packet. For example, IEEE 802.11 requires that an ACK (acknowledgement) signal be transmitted in response to reception of a valid data packet. Thus, after reception of valid “receive” data, the receiver portion of a transceiver ofFIG. 1may need to be powered OFF (to minimize power consumption), and its transmitter powered ON, so that the ACK can be transmitted. As noted above, the powering-OFF and powering-ON may be complete or partial. A power-OFF may correspond to removal of power for all or only some components/blocks, or to setting all or some of the components/blocks in a low-power (e.g., idle) states. Similarly, power-ON may correspond to restoration/application of power to the corresponding components/blocks from a no-power, low-power or idle states to full/normal power for all or only some components/blocks. How quickly the transceiver needs to start the acknowledgement (after end of receipt of the receive signal) may be stipulated by the specific operational environment, and hence the time interval in which to power-ON transmitter portions of a transceiver and power-OFF the receiver portions. For example, the requirements specified by the 802.11 standard are illustrated in the timing diagram ofFIG. 2.

With respect toFIG. 2, it is assumed that AP110F (or any of transceivers110B-110E) transmits a data frame addressed to transceiver110A in time interval t20-t21. Transceiver110A may thus be in “receive mode”, with the transmitter (transmit components or portion) being powered-OFF (to minimize power consumption), and the receiver (receive components or portion) being powered-ON in interval t20-t21. According to 802.11 standard, in DCF (Distributed Coordination Function) based medium access, wireless transceiver110A, on receiving the data frame, is required to transmit to the sender of the data frame an acknowledgment signal if the data frame is received and decoded without any errors. Further, the standard specifies that the acknowledgement signal must start at time instance t22, i.e., (exactly, or with predefined error tolerance) after a time interval t21-t22(also marked as t212inFIG. 2), termed an SIFS (Short Inter Frame Spacing) interval, as measured from the end (at t21) of the data frame. The interval t21-t22may be measured from the end (t21) of receipt of data at the antenna of transceiver110A to start (t22) of transmission of the acknowledgement also at the antenna of transceiver110A.

Hence, in interval t21-t22, the receive portion of transceiver110A may be required to be powered-OFF, the transmit portion powered-ON, and acknowledgement signal is to “start on air” at t22. The time taken to change operating modes, i.e., from receive portions ON (and transmit portions OFF) to transmit portions ON (and receive portions OFF), may be viewed as “receive-to-transmit turnaround time”. However, in addition to performing the required receive-to-transmit turnaround, interval t21-t22may also need to accommodate various other operations or delays, as shown with an example inFIG. 3.

As shown in table300ofFIG. 3, the time taken for the signal to travel from receiver RF (radio) portion to receiver (digital) baseband portion may consume 0.03 microseconds. The time taken for the last portion of the received signal (e.g., last data symbol transmitted on air) to be decoded in the receiver baseband may consume 5 microseconds. The time taken for the receiver to determine whether the received data are valid or not and if an acknowledgement is to be sent may consume 0.7 microseconds. Validity of data may be determined for, example, by comparing a received CRC checksum with a computed checksum. The time taken for the acknowledgment signal to travel from the transmitter baseband portion to the transmitter RF portion and to thence to be transmitted on air may consume 0.03 microseconds.

The operations shown in table300add up to 5.76 microseconds. Assuming, interval t212is 10 microseconds (as in the case of SIFS interval in the 802.11b context), the time available for performing the receive-to-transmit turnaround (receive-to-transmit turnaround time/interval) is 4.24 microseconds. The 4.24 microseconds includes time taken by analog/RF components in the transmit portions of a transceiver to ‘settle’ to their quiescent operating states (fully operational states) after power-ON. It is noted here that the 802.11 standard specifies only that the acknowledgement packet start at t22, and does not require the receive portions to be powered-OFF by t22. However, for minimizing power consumption, it may be desired that the receive portions be powered-OFF as soon as possible after end of receive operations.

According to a prior approach, a hardware state machine in a wireless transceiver performs the receive-to-transmit turnaround by first powering OFF the receive portions, followed by powering-ON of the transmit portions. However the approach may be associated with some drawbacks, such as increased implementation area, and lesser flexibility in controlling the time taken to execute the operations. Further, there may also be lesser flexibility in changing the sequence/order in which receive and transmit blocks/components are enabled/disabled. For example, any change in sequence/order may require redesign (silicon revision), and therefore have a higher cost associated with it.

In general, longer receive-to transmit turnaround time may require that the transceiver, and in particular the receiver baseband portions, be implemented to tighter specifications, thereby rendering the overall transceiver design more complex, expensive and which may consume more power. Further, the requirement for faster receive-to transmit turnaround may become even more critical when multiple receive chains (operating in parallel) need to be powered-OFF and multiple transmit chains powered-ON, as for example, in the context of IEEE 802.11n.

Several aspects of the present invention overcome one or more of the drawbacks noted above, as described next.

FIG. 4is a flow diagram illustrating the manner in which receive-to-transmit turnaround is performed, in an embodiment of the present invention. The flow diagram is described with respect to the environment ofFIG. 1, merely for illustration. However, various features described herein can be implemented in other environments and using other components, as will be apparent to one skilled in the relevant arts by reading the disclosure provided herein.

Further, the steps in the flow diagram are described in a specific sequence merely for illustration. Alternative embodiments using a different sequence of steps can also be implemented without departing from the scope and spirit of several aspects of the present invention, as will be apparent to one skilled in the relevant arts by reading the disclosure provided herein.

In step410according to the flow diagram, a wireless transceiver receives a signal (a receive signal) from another wireless device (e.g., an access point) over a wireless medium. The transmitter portions may be in a power-OFF state during reception of the ‘receive’ signal. Control then passes to step420.

In step420, the wireless transceiver decodes the ‘receive’ signal to extract data contained in the ‘receive’ signal. Control then passes to step430.

In step430, the wireless transceiver initiates power-ON of the transmitter portions prior to initiating power-OFF of the receiver portions. In an embodiment, the wireless transceiver performs the initiating of power-ON and power-OFF of the respective portions after the decoding of step420is complete.

Thus, according to an aspect of the present invention, (initiation of) power-ON of the transmitter portions of a transceiver is performed before power-OFF of the receiver portions. After power-ON of the transmitter portions, the wireless transceiver transmits an acknowledgement signal as a response to the received data, provided the data has been determined valid. Performing the power-ON of the transmitter portions prior to power-OFF of the receiver portions enables the wireless transceiver to comply with the requirement of being able to transmit an acknowledgement signal at the predetermined time instance. With respect to IEEE 802.11 standards, the predetermined time instance occurs at the end of the SIFS interval illustrated above with respect toFIG. 2.

It is noted that the powering OFF of the receive portions only after powering ON of the transmitter portions may translate to higher power consumption, at least during the interval in which both the receive and transmit portions are simultaneously in a power-ON state. However, performing the power-ON of the transmit portions first provides several benefits, in addition to enabling compliance with operational standards (such as 802.11), as illustrated in sections below.

FIG. 5shows a block diagram of a wireless transceiver500in an embodiment of the present invention. In addition,FIG. 5also shows a host501. Wireless transceiver500is shown containing processor510, memory515, transmit baseband block520, receive baseband block530, transmit radio block540, receive radio block550, switch560, antenna570, processing block580, memory585, state machine (also termed PHY sequencer)590and interrupt generation block595. The components/blocks of wireless transceiver500are shown merely by way of illustration. However, wireless transceiver500may contain more or fewer components/blocks, as well. For ease of reference, the combination of blocks/components540,550,560, and570may be viewed as a radio portion of wireless transceiver500. Components/blocks520and530may be viewed as a baseband portion of wireless transceiver500.

Similarly, the combination of blocks520and540may be viewed as a transmit portion (transmitter), while the combination of blocks530and550may be viewed as a receive portion (receiver). Further, processor510may execute instructions stored in memory515to implement medium access control (MAC) layer operations. Processor510in conjunction with transmit baseband block520and receive baseband block530implements (substantially most of the) the physical layer (PHY) operations of transceiver110A.

Host501may be any electronic device, and perform corresponding operations. For example, host unit501may be a PDA (personal digital assistant), and may contain various input/output (e.g., keys, display panels, audio/video output, etc.) components or just interfaces for the corresponding components. Host501communicates over a wireless medium through wireless transceiver500. Host501may be implemented only optionally, and the operations of host501may instead be performed by processor510and/or processing block580.

Antenna570operates to receive as well as transmit, in corresponding non-overlapping intervals, signals to a wireless medium. Switch560may be controlled by processor510(connection not shown) to connect antenna570either to receive radio block550via path556, or to transmit radio block540via path546depending on whether wireless device110-A is to receive or transmit. Alternatively, the above noted control of switch560may instead be performed by processing block580.

Receive radio block550receives an RF signal (receive signal) carrying data packets from a wireless medium on path556from antenna570, demodulates the RF signal, performs analog-to-digital conversion, and provides a down-converted baseband digital signal carrying data to receive baseband block530on path553. Receive baseband block530performs, on the baseband digital signal received on path553, operations such as filtering (to remove noise), DC offset removal, de-interleaving, error correction, and decoding the received signal (for example, using fast Fourier transform assuming OFDM techniques are employed) to extract data packets from the baseband signal. Receive baseband block530forwards the data packets to processor510on path531. The operation of some or all functions of (baseband blocks520and530may be controlled by processor510, via paths521and531respectively.10501Transmit baseband block520receives data to be transmitted from processor510on path521, performs operations on the data such as scrambling, interleaving, IFFT (inverse fast Fourier transform assuming OFDM techniques are employed), and sends digital data samples (in-phase and quadrature) to transmit radio block540on path524. Transmit radio block540receives the signal(s) from transmit baseband block520, performs operations such as digital-to-analog conversion of the signal(s), up-conversion, power amplification, transmit filtering, etc., to generate an RF signal. Transmit radio block540provides an up-converted RF signal carrying data packets to antenna570via switch560on path546.

Processor510receives data packets on path531from receive baseband block530, and processes the received data. Processing may include filtering of data in the data packets, Viterbi decoding, decryption of data (assuming data was transmitted in encrypted form), data integrity checks such as CRC checksum generation and comparison with the received checksum, etc. Processor510may forward the data to host501. If host501is not implemented, processor510operates on the extracted data to provide desired features. In particular, processor510performs data integrity checks on data extracted by receive baseband block530(and received on path531) to determine if an acknowledgement is to be transmitted or not.

Processor510generates data (or receives the data from host501, if host501is implemented) for transmission, performs various operations such as encryption of data (assuming data is to be transmitted in encrypted form), addition of data integrity checksums etc., and forwards processed data packets to transmit baseband block520on path521. In particular, processor510generates data/packets for an acknowledge signal if previously received data are determined to be valid (based, for example, on data integrity checks). Further, on determination that a received data packet is valid and hence requires an acknowledgment, processor510generates signals on path519to indicate to state machine590to power-ON transmit baseband block520and power-OFF receive baseband block530, and also to generate signals596(RX-EN) and597(TX-EN).

Processor510provides a select signal on path516to switch560, to connect antenna570either to receive radio block550or to transmit radio block540, based on the desired mode of operation (receive mode or transmit mode). The instructions and data required for processor510to perform the operations noted above are provided by memory5115, which may include volatile as well as non-volatile (e.g., ROM, Flash) memories.

State machine590receives commands from processor510, on path519, to control the power-ON/power-OFF states of transmit baseband block520and receive baseband block530via paths592and593respectively. In an embodiment, state machine590powers-OFF blocks520and530by gating-OFF (disabling) the respective clock signals (not shown) used to control the operations of blocks520and530. State machine590powers-ON blocks520and530by enabling the respective clock signals used to control the operations of blocks520and530. State machine590, in response to commands received from processor510(on path519), generates (or toggles) signal596(RX-EN) to indicate whether receive radio block550is to be powered-ON or powered-OFF. Similarly, state machine590, in response to commands received from processor510(on path519), generates (or toggles the level of) signal597(TX-EN) to indicate whether transmit radio block540is to be powered-ON or powered-OFF. In an alternative embodiment, processor510directly controls the ON/OFF states of transmit baseband block520and receive baseband block530, and also provides to processing block580(on path518, which may be connected to interrupt inputs of processing block580) signals specifying power-ON and power-OFF states to be set for blocks540and550.

Processing block580controls the power ON and/or power OFF of blocks540and550via corresponding control paths584and585. The power ON/OFF control may be performed in a known way. In an embodiment, the power ON/power OFF of blocks540and550is done via sequential register writes (for example, to corresponding registers located in respective blocks540and550) by processing block580. Processing block580may be implemented as a general purpose processor (microprocessor), application specific processor (ASIC) or as a finite state machine. In an alternative embodiment, processing block580may not be implemented, and processor510directly controls the powering-ON and powering-OFF of blocks540and550.

When processing block580is implemented as a microprocessor, the instructions and data required for processing block580to perform power ON and power OFF (as well as other desired functions) are provided by memory585via path588. Memory585may include volatile as well as non-volatile (e.g., ROM, Flash) memories. In particular, memory585and memory515store instructions and data to provide several features of the present invention, and constitute computer (or in general, machine) readable media. Also, when implemented as a microprocessor, signals on path598are connected to interrupt inputs of processing block580. In an embodiment, processing block580is implemented as ARM CORTEX M3 [™] processing core, the details of which are available at:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.cortexm/index.html. However, in other embodiments, processing block580may be implemented to correspond to other processors, or as a finite state machine (FSM). When implemented as a finite state machine (FSM), the operations performed by the instructions in memory585are implemented in hardware. Further, although processing block580is noted above as performing the power-On and power-OFF operations noted above, in other embodiments, processing block580may not be implemented, and the functions of processing block580may instead be performed by processor510.

Interrupt generation block595receives signals596and597and generates one or more interrupt signals on path598, which are provided to interrupt input(s) of processing block580. An embodiment of interrupt generation block595is shown in greater detail inFIG. 6. Interrupt generation block595is shown inFIG. 6as containing edge detection block610, OR gate620and register630. Edge detection block610generates a logic high signal on the corresponding ones of output paths611-614based on logic-level transitions of signals on path596and597.

Specifically, edge detection block610generates a logic high pulse on path611upon signal596(RX-EN) transitioning from logic low to logic high (the transition indicating that receive radio block550is to be powered ON), a logic high pulse on path612upon signal596(RX-EN) transitioning from logic high to logic low (the transition indicating that receive radio block550is to be powered OFF), a logic high pulse on path613upon signal597(TX-EN) transitioning from logic low to logic high (the transition indicating that transmit radio block540is to be powered ON), and a logic high pulse on path614upon signal597transitioning from logic high to logic low (the transition indicating that transmit radio block540is to be powered OFF).

OR gate620provides a logical OR output on path598(connected to an interrupt input of processing block580) of the inputs on paths611,612,613and614. The state transitions of signals596,597are registered in storage locations631,632,633,634(RX ON, RX OFF, TX ON, TX OFF) respectively of event status register630. Thus, a logic transition of signals596and/or597can generate an interrupt to processing block580.

The operations of wireless transceiver500in performing a receive-to-transmit turnaround are described next.

In an embodiment, receive-to-transmit turnaround is performed by the execution of instructions by processing block580implemented as an ARM CORTEX M3 [™] microprocessor.FIG. 7is a timing diagram illustrating the relevant operations and their timing relationships in the embodiment. However, it is noted that in other embodiments using processors (or FSM) other than ARM CORTEX M3 [™], the specific timing details may be different.

With respect toFIG. 7, it is assumed that the receive portion of transceiver500has decoded a ‘receive’ signal, and processor510has determined that the received data are valid sometime slightly prior to time instance t71. State transitions (to power-ON and power-OFF respectively) of baseband blocks520and530may occur (performed for example, by processor510via state machine590) parallely in time to state transitions (power-ON/OFF) of radio blocks540and550. It is further assumed that additional delays incurred in other operations, and as noted above with respect to the table ofFIG. 3, are incurred by wireless transceiver500, and that the available time (interval t71to t77inFIG. 7) for power-ON and stabilization of all components in the transmit portion is 4.24 microseconds. It is rioted that the specific values of the delays and hence the time available for receive-to-transmit turnaround are provided by way of example. The values can be different in other operational environments, and when other transceiver implementations are employed.

At t71, signal596(RX-EN) is shown as transitioning to logic low (indicating that receive radio block550is to be powered-OFF, and signal597(TX-EN) is shown as transitioning to logic high (indicating that transmit radio block540is to be powered-ON). The respective transitions indicate that the received data (similar to data in interval t20-t21inFIG. 2) have been determined to be valid, and that the receiver portion is to be powered OFF and the transmitter portions powered-ON, so that an acknowledgement (ACK) signal may be transmitted. The transitions of signals596and597generate logic high pulses on paths612and613(FIG. 6), and are also registered in locations632and633respectively of event status register630at t71.

In an embodiment, the logic level transitions750and760of signals596and597are each designed to occur not wider apart than a time interval equal to two clock cycles of the master clock of processing block580, although visually, zero delay is depicted inFIG. 7between the transitions. As a result of such generation of transitions750and760, OR gate620generates only a single pulse (denoted as703inFIG. 7) on output path598, which is provided as an interrupt to an interrupt input of processing block580. Signal704going to logic high at t71indicates that a change in logic level of one or more of signals596and597has occurred, i.e., at least one bit in event status register630is a logic high.

In response to interrupt signal703, an interrupt service routine (ISR) is invoked at t73. Interval t72-t73of waveform705represents the latency in actual start of the ISR, which occurs at t73. As is well known in the relevant arts, such latency may be incurred in saving the current execution context (e.g., values in the program counter, stack pointer, internal registers, etc.) of processing block580.

In the embodiment illustrated with respect toFIG. 7, in interval t73-t734, corresponding instructions in the ISR read event status register630to determine that receive radio block550is to be powered OFF and transmit radio block is to be powered-ON, by determining that bits in storage locations632and633are high. The reading of event status register630clears the bits in locations632and633, and signal704goes low at t734. Interval t734-t74is consumed by execution of code used to determine the state transition required (i.e., whether transmit portions ON and receive portions OFF are to be performed or not), since a same interrupt input is used to signal all possible state transitions.

According to an aspect of the present invention, instructions in the single ISR first initiate power-ON of transmit radio block540prior to initiating power-OFF of receive radio block550. In an embodiment, powering-ON of transmit radio block540is performed by a function called from within the ISR, while powering OFF of receive radio block550is performed by another function, also called from within the same ISR.

The first function call in the ISR performs, in interval712(t74to t75), initiation of power-ON of one or more components in transmit radio block540. T75represents the time instance by which all commands (e.g., register writes to registers in transmit radio block540, indicated as being performed on path584) are complete. It is noted that the registers may correspond to power-control registers, which are always in a powered-ON state (when transceiver500is operational).

On initiation of power-ON (e.g., via register writes on path584) the components within transmit radio block540may reach a full operational state after a short delay. The delay may include settling time for the analog/RF components in the block540, and fully operational status of the components may be reached slightly later than t75, but much earlier than t77. The first function exits (starting at) at t75after performing the power-ON operations noted above. Time interval713(t75to t76) represents the time taken for exiting from the first function.

The single ISR then invokes (at t76) a second function call for power-OFF of receive radio block550. The second function call performs power-OFF of one or more components of receive radio block550, for example by writing to corresponding registers in receive radio block550. T78represents a time instance by which all components in the receive portion have been powered-OFF. Interval715(t76to t78) is an interval in corresponding commands to power-OFF components in receive radio block550are provided. The second function exits at t78, followed by exit from the single ISR. It is noted that even though complete power-OFF of receive radio block550is effected later than t77(which represents the end of the SIFS interval), this does not constitute a problem.

Since all transmit portions are powered ON and stabilized before t77(i.e., at t75), the acknowledgement can be transmitted at the end of the SIFS interval (which occurs at t77), and the device to which the acknowledgement is addressed to can decode the acknowledgement correctly.

It is noted that in other embodiments, logic level transition750may be designed to occur much later than transition760. In such embodiments separate interrupt instances to processing block580are generated, and corresponding ISRs are generated, a first (earlier) ISR in which the power-ON of one or more components in transmit radio block540are performed, and a second (later) ISR in which power-OFF of one or more components in receive radio block550is performed. When processing block580is implemented as ARM CORTEX M3 [™], if transition750occurs prior to exit from the ISR for power-ON corresponding to the (earlier) transition760(i.e., time instance t75inFIG. 7), then no additional context saving is incurred in invoking the later ISR for power-OFF (as facilitated by the “tail-chaining” feature of ARM CORTEX M3 [™]. However, if transition750occurs after the exit from the ISR for power-ON corresponding to the (earlier) transition760, then additional context saving is incurred prior to invoking the later ISR for power-OFF.

In an alternative embodiment, delays in state machine590are adjusted such that control signal584is caused to be activated (in the single ISR noted above) to initiate power-ON of transmit radio block540prior to powering-ON block520(via state machine590and path592). In the alternative embodiment, delays in state machine590are also adjusted such that control signal585is caused to be activated to initiate power-OFF of receive radio block550prior to powering-OFF of block530(via state machine590and path593). In other embodiments, initiation of power-OFF of both the blocks530and550may be initiated simultaneously. Similarly, initiation of power-ON of both the blocks520and540may be initiated simultaneously.

It may be appreciated that the techniques of powering-ON the transmit portions prior to the receive portions (specifically powering-ON of transmit radio block540prior to powering-OFF of receive radio block550), and the technique of generating substantially simultaneously (or within a predetermined time interval of each other) interrupt events to indicate that receive radio block550is to be powered-OFF and transmit radio block540is to be powered-ON, so that both events are serviced in a single interrupt, enables transceiver500to meet the specified timing requirements of the SIFS interval.

In another embodiment, processing block580powers ON the components in transmit radio block540and powers-OFF components in receive radio block550in an interleaved manner, i.e., processing block580may power-ON some components of transmit radio block540, then power-OFF some components of receive radio block550, then power-ON the remaining components of transmit radio block540, and then power-OFF the remaining components of receive radio block550.

In yet another embodiment of the present invention illustrated with respect toFIG. 8, signals596and597are provided separately to two different interrupt inputs of processing block580. The interrupt input corresponding to signal597(TX-EN) is set to have a higher priority than the interrupt input corresponding to signal596(RX-EN). In such an embodiment, two OR gates may be implemented (instead of the single OR gate620ofFIG. 6), one with paths611and612as inputs, and the other with paths613and614as inputs. The output of each of the two OR gates (not shown) is provided to the two interrupt inputs (noted above) of processing block580.

In an embodiment, and as shown inFIG. 9, the transitions of signals596and597are designed to occur not wider apart in time than a time interval t910to t920, with the transition of signal597designed to occur later than the transition of signal596. Thus, in the embodiment, assuming signal596transitions at t910(as shown inFIG. 9), the transition of signal597is designed earlier than time instance t920. It is noted here that ARM CORTEX M3 [™] provides a feature by which a late-arriving interrupt can pre-empt a previous interrupt if the first instruction of the previous ISR has not entered the execute stage, and the late-arriving interrupt has a higher priority than the previous interrupt. Thus, in the embodiment, time interval t910to t920is designed to be not greater than a time interval from start of ISR corresponding to transition596to a time instance just prior to when the first instruction of the ISR enters the execution stage. In an embodiment, interval t910to t920(predetermined interval) equals the context saving time of processing block580.

Referring now toFIG. 8, transition of signal596occurs at t81and generates a corresponding interrupt signal803. Transition of signal597occurs at t82and generates a corresponding interrupt signal804. Assuming zero delay between the occurrence of transitions of signals596(and597) and the corresponding interrupt803(and804), interrupts803and804are thus designed to occur within a time interval t910-t920of each other. Assuming there are delays (e.g., unequal delays) from the transitions to the corresponding interrupt, the occurrences of the transitions of signals596and597are designed such that interrupts803and804occur within interval t910-t920of each other.

Since interrupt signal804is provided to a higher priority interrupt input compared to the interrupt input to which interrupt signal803is provided, the ISR corresponding to interrupt804is invoked first, shown as starting at time interval t83inFIG. 8. In interval812(t83-t84), processing block performs the powering-ON of one or more blocks in transmit radio block540, the powering-ON operations ending at t84. Context or state saving is not performed for the late-arriving interrupt804because it has already been performed for the initial interrupt803and so does not have to be repeated. Interval t81-t83represents a duration in which context saving is done (caused by interrupt803). In duration813, in which the ISR corresponding to interrupt803is executed, processing block580powers-OFF one or more components of receive radio block550. T85represents the time instance at which the ISR corresponding to interrupt803exits. Interval t81-t86represents the 4.24 microsecond interval noted above.

It may be appreciated that the use of separate interrupts for power-ON and power-OFF as illustrated with respect toFIGS. 8 and 9obviates the need for determination of the source of the interrupt, as is required (and performed in interval t73-t734) in the technique illustrated with respect toFIG. 7. As a result, the technique ofFIGS. 8 and 9may be able to perform transmit-to-receive-turnaround in an even shorten interval than the technique ofFIG. 7.

It is noted that in the technique illustrated with respect toFIGS. 8 and 9, the ISRs executed in intervals needs to determine whether transmit components are to be powered-ON or powered-OFF, and thus some time is consumed in interval812in making such determination by reading event status register630(FIG. 6). Similar time consumption occurs in interval813in determining whether the receive components are to be powered-OFF- or powered-ON. In yet another embodiment of the present invention, such overhead (time consumption noted above) is avoided by providing each of the four signals611-614(ofFIG. 6) to separate interrupt inputs of processing block580(with OR gate620not being implemented).

It is further noted that other variations of the approaches illustrated with respect toFIGS. 8 and 9are also possible. For example, the transition of signal597may be instead be designed to occur at or earlier than the transition of signal596. In such cases, the advantage of avoiding one context save (using the late arrival feature of ARM CORTEX) may not be obtainable. In such cases, the higher priority interrupt (corresponding to signal597) will be serviced first, followed by servicing of the lower priority interrupt (corresponding to signal596). In general, the specific interrupt order and the corresponding number of context restore/store operations depend on the specific implementation of processing block580. Irrespective of the specific implementation however, by performing the power-ON of the transmit components earlier than the power-OFF of the receive components, transmission of acknowledgement can be started by the end of SIFS interval.

It is noted here that it may not be desirable to power-ON the transmit portions and power-OFF the receive portions simultaneously (in parallel), for example by execution of a single processor instruction, as the current surge from simultaneous power-ON and power-OFF might exceed acceptable limits and damage wireless transceiver500. Further, the powering-ON and powering-OFF of at least some components in transmit radio block540and receive radio block550may need to be performed in a particular sequence, for example due to settling time constraints, design and stability constraints, etc. Hence, the power-ON and power-OFF described with respect toFIG. 7may need to be performed sequentially. However, it is noted that to some extent the power-ON and power-OFF can be parallelized by designing the power ON/OFF control bits for transmit radio block540and receive radio block550to be located in a same (single) register.

The reduced receive-to-transmit turnaround time achieved using techniques described in detail above, provides the additional benefit of relaxing the design requirements of blocks of the wireless transceiver. For example, the processing throughput requirements of receive baseband block530may be relaxed, and in general, the design of wireless transceiver500may be rendered less complex. In general, faster receive-to-transmit turnaround time may provide more time for baseband processing, which may be desirable as future wireless standards supporting higher bitrates may necessitate more complex designs with higher group delays/latencies.