Methods for forming a round bottom silicon trench recess for semiconductor applications

Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.

BACKGROUND

Embodiments of the present invention generally relate to a method for forming a round bottom silicon trench recess, more specifically, to a method for forming a round bottom silicon trench recess in semiconductor fabrication applications.

2. Description of the Related Art

Reliably producing submicron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the miniaturization of circuit technology is pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.

As circuit densities increase for next generation devices, the integration densities have been increased by decreasing transistor feature sizes, including gate length and channel length. Decreased channel length may result in short channel effects, which may increase an off-current threshold of the transistors ad can deteriorate refresh characteristics of memory devices having such transistors. In order to eliminate such problems, forming a recess channel for semiconductor device manufacture has been introduced to extend the channel length of the transistors. The recess channel increases a channel length and reduces an ion-implantation concentration, thereby improving a refresh property of the semiconductor device.

In some instances, recess channels may also be configured to have different shapes or features formed within a trench, instead of conventional vertical only trench shapes, so as to further increase surface area or length of the channels to further improve refresh properties. However, formation of such shapes or features often require complicated and multiple process steps to complete the manufacture process, resulting in increases of manufacturing cycle time and cost with decreased process throughput. Furthermore, poor etching selectivity and control occurring during manufacturing processes for such shapes or features in the recess channels may undesirably result in an inaccurate profile control, thereby eventually leading to device failure.

Thus, there is a need for a channel recess etch process for etching a recess area in a semiconductor substrate with low cost and precise process control.

SUMMARY

Embodiments of the present invention provide methods for etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.

In another embodiment, a method of forming a recess structure in a semiconductor substrate includes providing a silicon substrate into a processing chamber, wherein the silicon substrate has a patterned photoresist layer disposed thereon, exposing an active region formed in the silicon substrate, wherein the active region is defined between shallow trench isolations (STI) in the silicon substrate, supplying an etching gas mixture in the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, performing an anisotropic etching process by applying a RF bias power in the etching gas mixture, and performing an isotropic etching process by turning off the RF bias power in the etching gas mixture.

In yet another embodiment, a method of forming a recess structure in a semiconductor substrate includes providing a silicon substrate into a processing chamber, wherein the silicon substrate has a patterned photoresist layer disposed thereon, exposing an active region formed in the silicon substrate, wherein the active region is defined between shallow trench isolations (STI) in the silicon substrate, etching the active region in the silicon substrate with a RF bias power on to form a trench in the active region, and continuously etching the active region in the silicon substrate with the RF bias off to form a round feature to a bottom of the trench in the active region.

DETAILED DESCRIPTION

The present invention provides a method and apparatus for manufacturing a recess channel structure in a semiconductor substrate. More specifically, the invention relates to methods of utilizing a single etching step to manufacture a recess channel structure in a semiconductor substrate in semiconductor device applications. In one embodiment, the recess channel structure with a round bottom feature, e.g., a spherical-like structure, formed at a bottom of a trench is formed by using a single etching step to etch a silicon material defining the semiconductor substrate. The single etching step utilizes a pulsed RF bias power mode to incrementally etch the round bottom feature at the bottom of the trench, thereby forming a channel recess with round bottom feature, e.g., a spherical-like structure, in the semiconductor substrate.

FIG. 1is a sectional view of one embodiment of a processing chamber100suitable for manufacturing a recess channel structure in a semiconductor substrate. Suitable processing chambers that may be adapted for use with the teachings disclosed herein include, for example, a ENABLER® processing chamber, Decoupled Plasma Source (DPS®) II reactor, or other suitable reactors, available from Applied Materials, Inc. of Santa Clara, Calif. The particular embodiment of the processing chamber100shown herein is provided for illustrative purposes and should not be used to limit the scope of the invention. It is contemplated that the invention may be utilized in other plasma processing chambers, including those from other manufacturers.

The processing chamber100includes a chamber body102and a lid104which together enclose an interior volume106. The chamber body102is typically fabricated from aluminum, stainless steel or other suitable material. The chamber body102generally includes sidewalls108and a bottom110. A substrate access port (not shown) is generally defined in a sidewall108and a selectively sealed by a slit valve to facilitate entry and egress of a substrate101from the processing chamber100. An exhaust port126is defined in the chamber body102and couples the interior volume106to a pump system128. The pump system128generally includes one or more pumps and throttle valves utilized to evacuate and regulate the pressure of the interior volume106of the processing chamber100. In one embodiment, the pump system128maintains the pressure inside the interior volume106at operating pressures typically between about 10 mTorr to about 20 Torr.

The lid104is sealingly supported on the sidewall108of the chamber body102. The lid104may be opened to allow excess to the interior volume106of the processing chamber100. The lid104includes a window142that facilitates optical process monitoring. In one embodiment, the window142is comprised of quartz or other suitable material that is transmissive to a signal utilized by an optical monitoring system140.

The optical monitoring system140is positioned to view at least one of the interior volume106of the chamber body102and/or the substrate support pedestal assembly148positioned on a substrate support pedestal assembly148through the window142. In one embodiment, the optical monitoring system140is coupled to the lid104and facilitates an integrated deposition process that uses optical metrology to provide information that enables process adjustment to compensate for incoming substrate pattern feature inconsistencies (such as thickness, and the like), provide process state monitoring (such as plasma monitoring, temperature monitoring, and the like) as needed. One optical monitoring system that may be adapted to benefit from the invention is the EyeD® full-spectrum, interferometric metrology module, available from Applied Materials, Inc., of Santa Clara, Calif.

A gas panel158is coupled to the processing chamber100to provide process and/or cleaning gases to the interior volume106. In the embodiment depicted inFIG. 1, inlet ports132′,132″ are provided in the lid104to allow gases to be delivered from the gas panel158to the interior volume106of the processing chamber100.

A showerhead assembly130is coupled to an interior surface114of the lid104. The showerhead assembly130includes a plurality of apertures that allow the gases flowing through the showerhead assembly130from the inlet ports132′,132″ into the interior volume106of the processing chamber100in a predefined distribution across the surface of the substrate support pedestal assembly148being processed in the processing chamber100.

A remote plasma source177may be coupled to the gas panel158to facilitate dissociating gas mixture from a remote plasma prior to entering into the interior volume106for processing. A RF source power143is coupled through a matching network141to the showerhead assembly130. The RF source power143typically is capable of producing up to about 3000 W at a tunable frequency in a range from about 50 kHz to about 13.56 MHz.

The showerhead assembly130additionally includes a region transmissive to an optical metrology signal. The optically transmissive region or passage138is suitable for allowing the optical monitoring system140to view the interior volume106and/or substrate101positioned on the substrate support pedestal assembly148. The passage138may be a material, an aperture or plurality of apertures formed or disposed in the showerhead assembly130that is substantially transmissive to the wavelengths of energy generated by, and reflected back to, the optical monitoring system140. In one embodiment, the passage138includes a window142to prevent gas leakage from the passage138. The window142may be a sapphire plate, quartz plate or other suitable material. The window142may alternatively be disposed in the lid104.

In one embodiment, the showerhead assembly130is configured with a plurality of zones that allow for separate control of gas flowing into the interior volume106of the processing chamber100. In the embodimentFIG. 1, the showerhead assembly130has an inner zone134and an outer zone136that are separately coupled to the gas panel158through separate inlets132′,132″.

The substrate support pedestal assembly148is disposed in the interior volume106of the processing chamber100below the showerhead assembly130. The substrate support pedestal assembly148holds the substrate101during processing. The substrate support pedestal assembly148generally includes a plurality of lift pins (not shown) disposed therethrough that are configured to lift the101from the substrate support pedestal assembly148and facilitate exchange of the substrate101with a robot (not shown) in a conventional manner. An inner liner118may closely circumscribe the periphery of the substrate support pedestal assembly148.

In one embodiment, the substrate support pedestal assembly148includes a mounting plate162, a base164and an electrostatic chuck166. The mounting plate162is coupled to the bottom110of the chamber body102and includes passages for routing utilities, such as fluids, power lines and sensor leads, among others, to the base164and the electrostatic chuck166. The electrostatic chuck166comprises at least one clamping electrode180for retaining a substrate support pedestal assembly148below showerhead assembly130. The electrostatic chuck166is driven by a chucking power source182to develop an electrostatic force that holds the substrate support pedestal assembly148to the chuck surface, as is conventionally known. Alternatively, the substrate support pedestal assembly148may be retained to the substrate support pedestal assembly148by clamping, vacuum or gravity.

At least one of the base164or electrostatic chuck166may include at least one optional embedded heater176, at least one optional embedded isolator174and a plurality of conduits168,170to control the lateral temperature profile of the substrate support pedestal assembly148. The conduits168,170are fluidly coupled to a fluid source172that circulates a temperature regulating fluid therethrough. The heater176is regulated by a power source178. The conduits168,170and heater176are utilized to control the temperature of the base164, thereby heating and/or cooling the electrostatic chuck166, and thereby facilitating the operative control of the substrate101. The temperature of the electrostatic chuck166and the base164may be monitored using a plurality of temperature sensors190,192. The electrostatic chuck166may further comprise a plurality of gas passages (not shown), such as grooves, that are formed in a substrate support pedestal supporting surface of the chuck166and fluidly coupled to a source of a heat transfer (or backside) gas, such as He. In operation, the backside gas is provided at controlled pressure into the gas passages to enhance the heat transfer between the electrostatic chuck166and the substrate support pedestal assembly148.

In one embodiment, the substrate support pedestal assembly148is configured as a cathode and includes an electrode180that is coupled to a RF power bias source184. The RF bias power source184is coupled between the electrode180disposed in the pedestal assembly148and another electrode, such as the showerhead assembly130or lid104of the chamber body102. The RF bias power excites and sustains a plasma discharge formed from the gases disposed in the processing region of the chamber body102. In the embodiment depicted inFIG. 1, the RF bias power source184is coupled to the electrode180disposed in the pedestal assembly148through a matching network188. The signal generated by the RF bias power source184is delivered through matching network188to the substrate support pedestal assembly148through a single feed to ionize the gas mixture provided in the plasma processing chamber100, thereby providing ion energy necessary for performing a deposition or other plasma enhanced process. The RF bias power source184is generally capable of producing an RF signal having a frequency of from about 50 kHz to about 200 MHz and a power between about 0 Watts and about 5000 Watts. An additional bias power source189may be coupled to the electrode180to control the characteristics of the plasma. It is noted that although the example depicted inFIG. 1includes one RF bias power source184and an additional optional RF bias power source189, it is noted that the RF bias power included in the processing chamber100may be in any number as needed.

In one mode of operation, the substrate101is disposed on the substrate support pedestal assembly148in the plasma processing chamber100. A process gas and/or gas mixture is introduced into the chamber body102through the showerhead assembly130from the gas panel158. Furthermore, additional gases may be supplied from the remote plasma source177through the showerhead assembly130to the processing chamber100. A vacuum pump system128maintains the pressure inside the chamber body102while removing deposition by-products. The vacuum pump system128typically maintains an operating pressure between about 10 mTorr to about 20 Torr.

The RF source power143and the RF bias power sources184,189provide RF source and bias power at separate frequencies to the anode and/or cathode through the matching network141and188respectively, thereby providing energy to form the plasma and excite the gas mixture in the chamber body102into ions to perform a plasma process.

A controller150is coupled to the processing chamber100to control operation of the processing chamber100. The controller150includes a central processing unit (CPU)152, a memory154, and a support circuit156utilized to control the process sequence and regulate the gas flows from the gas panel158. The CPU152may be any form of general purpose computer processor that may be used in an industrial setting. The software routines can be stored in the memory154, such as random access memory, read only memory, floppy, or hard disk drive, or other form of digital storage. The support circuit156is conventionally coupled to the CPU152and may include cache, clock circuits, input/output systems, power supplies, and the like. Bi-directional communications between the controller150and the various components of the processing chamber100are handled through numerous signal cables.

FIG. 1only shows one exemplary configuration of various types of plasma processing chamber that can be used to practice the invention. For example, different types of microwave power, magnetic power and bias power can be coupled into the plasma chamber using different coupling mechanisms. In some applications, different types of plasma may be generated in a different chamber from the one in which the substrate is located, e.g., remote plasma source, and the plasma subsequently guided into the chamber using techniques known in the art.

FIG. 2is a flow diagram of a method200for manufacturing a recess channel structure313in a semiconductor substrate, which may be performed in a processing chamber, such as the processing chamber100depicted inFIG. 1.FIGS. 3A-3Dare schematic cross-sectional views illustrating a sequence for manufacturing the recess channel structure in the semiconductor substrate, such as the substrate101, depicted inFIG. 1, according to the method200. Although the method200is described below with reference to a semiconductor substrate utilized to fabricate a channel recess structure with round bottom features, the method200may also be used to advantage in other trench recess process, such as recess for shallow trench isolations (STI) or any other suitable structures for semiconductor device fabrications.

The method200, which may be stored in computer readable form in the memory154of the controller150or other storage medium, begins at block202when the substrate101is transferred to and placed on the substrate support pedestal assembly148disposed in the processing chamber100, as depicted inFIG. 1.

The substrate101may have shallow trench isolation (STI)302formed in the substrate101defining an active region304in between the shallow trench isolation (STI)302, as shown inFIG. 3A. The active region304may include different types of active dopants doped in silicon materials, such as a single crystalline silicon, from the substrate101. A patterned photoresist layer308along with a patterned hardmask layer306may be disposed on the substrate101with defined openings310in the patterned photoresist layer308and the patterned hardmask layer306, exposing a surface312of the active region304for processing. The patterned photoresist layer308may comprise any suitable photosensitive resist materials, such as an e-beam resist (for example, a chemically amplified resist (CAR)), and deposited and patterned in any suitable manner. The patterned photoresist layer308may be deposited to a thickness between about 100 nm and about 3000 nm. The hardmask layer306may be any suitable dielectric materials, such as amorphous carbon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, combinations thereof, and the like. In one particular embodiment, the hardmask layer306may include an amorphous carbon layer, or combinations of amorphous carbon layer and silicon oxide layer.

In one embodiment, the substrate101may have a substantially planar surface, an uneven surface, or a substantially planar surface having a structure formed thereon. The substrate101may be a material such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire. The substrate101may have various dimensions, such as 200 mm, 300 mm, 450 mm or other diameter wafers, as well as rectangular or square panels. Unless otherwise noted, embodiments and examples described herein are conducted on substrates having a diameter between about 200 mm and about 500 mm. In the embodiment wherein a SOI structure is utilized for the substrate101, the substrate101may include a buried dielectric layer disposed on a silicon crystalline substrate. In the embodiment depicted herein, the substrate101may be a crystalline silicon substrate. The photoresist layer308and the hardmask layer306may be patterned by any suitable patterning techniques.

At block204, an etching gas mixture is supplied into the processing chamber100to etch portions of the surface312of the active region304defined in the substrate101exposed by the patterned photoresist layer308and the hardmask layer306, as shown inFIG. 3B. In some embodiments, the hardmask layer306may be patterned/etched together with the active region304continuously in a single chamber with the same process step, such as a single etchant chemistry, or separately etched by multiple steps in one or different etching processes as needed. The patterns/openings310from the photoresist layer308and the hardmask layer306are then transferred into the active region304through the etching process.

In one embodiment, the etching gas mixture supplied to etch the active region304in the semiconductor substrate101includes at least one halogen containing gas and a chlorine containing gas. Suitable examples of the halogen containing gas include HBr, CF4, CHF3, CH2F2, C2F6, C2F8, C4F6, SF6, NF3, and the like. Suitable examples of the chlorine containing gas include HCl, Cl2, and the like. In some embodiments, HBr and Cl2are supplied in the etching gas mixture. Some halogen containing gases with carbon elements formed therein may also be utilized in the etching gas mixture. Halogen containing gases with carbon elements (e.g., a carbon and halogen containing gas) formed therein that may be supplied in the etching gas mixture include CF4, CHF3, CH2F2, C2F6, C2F8, C4F6and the like.

In one example, CF4, CHF3may be supplied with the HBr and Cl2gas in the etching gas mixture to etch the active region304to form desired features/openings, such as a trench318, as part of a recess channel structure313in the substrate101. As the fluorine, bromide and chlorine elements are aggressive etchants, these elements, included in the etching gas mixture, are utilized to etch away portions of the active region304, forming the trench318in the active region304of the semiconductor substrate101, as shown inFIG. 3B. Carbon elements from the CF4, CHF3gas may provide a polymer source to assist passivating sidewalls330of the trench318.

In an alternative embodiment, an inert gas may also be supplied as part of the etching gas mixture to assist the profile control as needed. Examples of the inert gas supplied in the gas mixture include Ar, He, Ne, Kr, Xe or the like.

In one embodiment, HBr gas and Cl2gas supplied in the etching gas mixture may be maintained at a predetermined ratio to yield an efficient etching rate. Carbon and halogen containing gas are supplied to protect the sidewalls from undesired etching. In an exemplary embodiment, the HBr gas and Cl2gas are supplied in the etching gas mixture at a HBr:Cl2ratio of between about 5:1 and about 1:5. Alternatively, HBr gas may be supplied at a flow rate by volume between about 5 sccm and about 70 sccm. Cl2gas may be supplied at a flow rate by volume between about 5 sccm and about 70 sccm.

Additionally, CF4gas and CHF3gas are supplied in the etching gas mixture at a CHF3:CF4ratio of between about 5:1 to about 10:1. Alternatively, CF4gas may be supplied at a flow rate by volume between about 10 sccm and about 100 sccm. CHF3gas may be supplied at a flow rate by volume between about 30 sccm and about 200 sccm.

At block206, after the etching gas mixture is supplied into the etching gas mixture, a RF source power and a pulsed RF bias power are supplied to form a plasma from the gas mixture to form the trenches318in the active region304of the substrate101. The RF power, including source and bias power, may be applied to the processing chamber to ignite a plasma in the etching gas mixture. In one embodiment, the RF bias power may be set to a pulsed mode, intermittently applying RF bias power over different time periods during the etching process. The RF bias power may maintain in the pulsed mode and intermittently applied into the processing chamber until the predetermined process time period is expired.

It is believed that utilizing pulse mode for applying RF bias power to produce plasma in the gas mixture may assist producing alternating isotropic and anisotropic etching process during the overall etching process. Pulsed RF bias power mode may maintain the RF bias power in an “on-off” pulsed mode. In the period when the RF bias power is on, ions, radicals, or active species generated in the plasma become directional and may be accelerated toward the substrate, performing an anisotropic etching process, e.g., with directional ions, radicals, or active species generated in the plasma, to etch the trench318with substantially vertical sidewalls330(i.e., with a specific controlled direction) at a predetermined length316, as shown inFIG. 3B. Subsequently, in the period when the RF bias power is off, ions, radicals, or active species may be uniformly distributed in the plasma, gradually falling onto the substrate without specific directionality, performing an isotropic etching process, e.g., with non-directional ions, to etch the substrate101. The isotropic etching process further etches the recess channel structure313outward of the sidewalls330, forming a round bottom feature320connecting to the vertical sidewall330of the recess channel structure313, as shown inFIG. 3C. As the ions, radicals, or active species generated by the isotropic etching process (e.g., with RF pulsed power off) are with no specific directions, the reactive ions may scatter radially and symmetrically to chemically react with the silicon materials in the active region304. Thus, the resultant round bottom feature320formed at the end of the recess channel structure313may have a lateral width322from a feature corner325of the round bottom feature320substantially similar to the vertical width323from a bottom326of the round bottom feature320, due the isotropic nature of the non-directional etching process.

Referring first toFIGS. 4A-4C, the etching process with pulsed RF bias mode is performed to form a recess channel structure313in the substrate101. When the etching process first starts, an anisotropic etching process with RF bias power on is performed for a first period of time to form a trench416with substantially vertical sidewalls410and a planar bottom411in the substrate101with a first width418and a first length402, as shown inFIG. 4A. After the first predetermined period of time, the RF bias power is then switched to be maintained in an off state to perform an isotropic etching process. As discussed above, the isotropic etching process etches the substrate101radially and symmetrically from the bottom411of the trench416, forming a bulb type, e.g., a sphere-like, round bottom feature412from the bottom411of the trench416with a first lateral width406that extends outward of the sidewalls410, as shown inFIG. 4B.

During the isotropic etching process (e.g., with RF bias power off), as the reactive ions randomly attack silicon materials in the substrate101without specific directionality, the silicon materials from the sidewall410of the recess channel structure313along with the bottom411may both chemically react with the reactive ions. As the lateral width406of the round bottom feature412increases during the isotropic etching process, the first length402of the trench416may be reduced by the growth of the round bottom feature412to a second length404. In the mean while, the carbon and halogen containing gas supplied in the etching gas mixture may provide a source of polymer protection, protecting sidewalls410of the trench416from being overly attacked. Thus, a desired vertical sidewall410of the trench416may be maintained even the length404of the trench416is shortened.

Subsequently, the pulsed mode of the RF bias power continues going on and off to interchangeably perform the anisotropic etching and isotropic etching process to the substrate101. The RF bias power switching causes a vertical width420along with the lateral width408of the round bottom feature412to grow until a desired dimension of the vertical width420and the lateral width408is reached, as shown inFIG. 4C. Similarly, the second length404of the trench416may be further reduced to a third length414as the growing size of the round bottom feature412may unavoidably erode some length414of the trench416. The width418of the trench is maintained substantially the same throughout the pulsed mode of the RF bias power etching process due to the polymer layer protection from the carbon and halogen containing gases supplied in the etching gas mixture.

Thus, by modulating the pulsed mode of the RF power applied to the etching gas mixture, the round bottom feature412extending outwards from the trench416with vertical profile, e.g., the recess channel structure313, may be obtained. Unlike the conventional practice utilizing several process steps, likely including deposition processes and several steps of etching processes, to fabricate both the vertical trench416and the round bottom feature412, a single etching process with modulated RF bias power pulsed mode as described herein may obtain the recess channel structure313with the desired vertical trench416and the round bottom feature412formed in-situ in an etching processing chamber.

Furthermore, it is believed that the flow rate of Cl2gas supplied in the gas mixture may also influence the formation of the round bottom feature412. Higher chlorine gas flow ratio in the etching gas mixture (e.g., a higher gas flow rate of Cl2gas) assists providing aggressive etchants, e.g., chlorine ions, during the isotropic etching process, thereby expediting the round bottom feature formation process. In one embodiment, the flow rate of the chlorine gas is controlled to be supplied in the etching gas mixture at about 5 percent to about 20 percent by volume to the total flow rate, including all gases supplied, in the etching gas mixture.

Referring back toFIG. 3C, the number of the RF bias power pulses provided during the etching process may be increased as many times as needed until desired dimensions of the recess channel structure313is formed. In one embodiment, the RF bias power pulse may have a duty cycle between about 5 percent (e.g., 5 percent on and 95 percent off) to about 70 percent (e.g., 70 percent on and 50 percent off), such as between about 5 percent and about 50 percent, such as between about 15 percent to 45 percent, at a RF bias frequency between about 500 Hz and about 10 kHz. Alternatively, the cycle of the RF bias power pulsed into the processing chamber may be controlled by a predetermined number of time periods performed. For example, the RF bias power may be pulsed between about every 0.1 milliseconds and about every 10 milliseconds. It is noted that the duty cycle of the RF bias power pulsed into the processing chamber may be repeated as many times as needed.

In one embodiment, the RF bias power may be controlled at about less than 500 Watts, such as less than 350 Watts, and a RF bias frequency between about 500 Hz and about 10 kHz. While maintaining the RF bias power in a pulsed mode, the RF source power and the etching gas mixture may be continuously applied to maintain smooth switch/transition between the anisotropic etching process and the isotropic etching process. In one embodiment, the RF source power may be supplied at the gas mixture between about 100 Watts and about 3000 Watts and at a frequency between about 400 kHz and about 13.56 MHz.

In one particular embodiment, the RF source power is maintained at about 1500 Watts while the RF bias power is maintained at about 170 Watts. The RF source power frequency is controlled at about 13.56 Hz and the RF bias power frequency is controlled at about 13.56 MHz or 2 MHz.

Several process parameters may also be controlled while supplying the etching gas mixture and the pulsed RF bias power mode to perform the etching process. The pressure of the processing chamber may be controlled at between about 0.5 milliTorr and about 500 milliTorr, such as between about 1 milliTorr and about 100 milliTorr, for example about 20 milliTorr.

The etching process is performed to etch the substrate101until desired dimensions of the vertical trench318and the round bottom feature320is formed, as shown inFIG. 3C. In one embodiment, the vertical trench318may have a width329between about 10 nm and about 25 nm, and a length340between about 60 nm and about 150 nm. The round bottom feature320may have a vertical width323between about 15 nm and about 50 nm and a lateral width322between about 15 nm and about 35 nm. The end point of the etching process may be controlled by time mode or other suitable methods. For example, the etching process may be terminated after performing between about 50 seconds and about 500 seconds. In this particular embodiment, the etching process may be performed between about 1 seconds and about 1000 seconds. In another embodiment, the etching process may be terminated by determination from an endpoint detector, such as an OES detector or other suitable detector as needed.

After the desired profile and/or the structure is formed in the active region304of the substrate101, the photoresist layer308along with the hardmask layer306may be removed. In one embodiment, the remaining photoresist layer308is removed by ashing. The removal process may be performed in-situ in the processing chamber100in which the etching method was performed. In the embodiment wherein the photoresist layer314is completely consumed during the etching process, the ashing or photoresist layer removal process may be eliminated.

After the photoresist layer308is removed, a gate structure350may then be formed on the recess channel structure313as needed, as shown inFIG. 3D. It is noted that although the recess structure as described herein is utilized to form a channel recess under a gate structure, it is contemplated that the recess structure may be used in any structure, substrates, or any applications as needed.

Thus, a method for manufacturing a recess channel structure in a semiconductor substrate has been provided that advantageously improves manufacture productivity, process control, and feature dimension accuracy. By using one single etching step, a channel recess structure may be formed in a semiconductor substrate in a single processing chamber. The method of forming the channel recess structure advantageously facilitates fabrication of channel recess structure to be connected to a gate structure with accurate critical dimensions for advanced memory fabrication and applications.