Method and apparatus for a package having multiple stacked die

A method of manufacturing a semiconductor package involves providing a substrate having a window. The substrate may include a leadframe having half-etched leads. First and second semiconductor devices are mounted to a top surface of the substrate on either side of the window using an adhesive. A third semiconductor device is mounted to the first and second semiconductor devices using an adhesive. The third semiconductor device is disposed over the window of the substrate. A wirebond or other electrical interconnect is formed between the third semiconductor device and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond or other electrical interconnect passes through the window of the substrate. An encapsulant is deposited over the first, second, and third semiconductor devices.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to an apparatus and method of fabricating a multiple-die system in a package (sip).

BACKGROUND OF THE INVENTION

Semiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.

The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.

One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level chip scale packages (WLCSP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die face down toward a chip carrier substrate or printed circuit board (PCB). WLCSPs combine a plurality of semiconductor die, semiconductor packages, or known good units (KGUs) over a single substrate. However, space limitations minimize the number of dies that can be integrated over a single substrate. Also, prior systems make use of spacers or dummy layers to control the configuration of the semiconductor die, further limiting the number of semiconductor die that can be combined over a single substrate.

SUMMARY OF THE INVENTION

A need exists for a semiconductor device having a plurality of integrated semiconductor die over a substrate. In addition, a need exists for manufacturing techniques for the system as described which reduce process steps and material costs resulting in shorter cycle time and lower overall cost.

In one embodiment, the present invention is a method of manufacturing a semiconductor package comprising providing a substrate having a window, mounting first and second semiconductor devices to a top surface of the substrate on either side of the window using an adhesive, and mounting a third semiconductor device to the first and second semiconductor devices using an adhesive. The third semiconductor device is disposed over the window of the substrate. The method includes forming a wirebond between the third semiconductor device and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond passes through the window of the substrate. The method includes depositing an encapsulant over the first, second, and third semiconductor devices.

In another embodiment, the present invention is a method of manufacturing a semiconductor package comprising providing a substrate having a window, stacking a plurality of semiconductor devices over a top surface of the substrate proximate to the window, and forming an electrical interconnect between one of the plurality of semiconductor devices and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The electrical interconnect passes through the window of the substrate.

In another embodiment, the present invention is a method of manufacturing a semiconductor package comprising providing a substrate having a window, mounting a plurality of semiconductor devices over a top surface of the substrate proximate to the window of the substrate, forming an electrical interconnect between one of the plurality of semiconductor devices and a contact pad formed over a surface of the substrate, and depositing an encapsulant over the plurality of semiconductor devices using a two-step molding process.

In another embodiment, the present invention is a semiconductor package comprising a substrate having a window, a plurality of semiconductor devices stacked over a top surface of the substrate proximate to the window, and a wirebond formed between one of the plurality of semiconductor devices and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond passes through the window of the substrate.

DETAILED DESCRIPTION OF THE DRAWINGS

A semiconductor device system-in-a-package (SIP) having a plurality of integrated semiconductor die or packages can be manufactured. Moreover, the semiconductor device can be manufactured using a shorter process, using less costly materials which contribute to shorter manufacturing time and lower overall cost. In one embodiment, semiconductor die are mounted over a substrate and electronically interconnected. One or more semiconductor die is electronically connected to the substrate.

A mounted semiconductor device is shown inFIG. 1. The semiconductor device involves mounting an active area12of die14face down toward a chip carrier substrate or printed circuit board (PCB)16. Active area12may contain active and passive devices, conductive layers, and dielectric layers according to the electrical design of die14. The electrical and mechanical interconnect between die14and substrate or PCB16is achieved through a solder bump structure20comprising a large number of individual conductive solder bumps or balls22. The solder bumps are formed on bump pads or interconnect sites24, which are disposed on active area12of die14. The bump pads24connect to the active circuits of die14by conduction tracks formed in active area12. The solder bumps22are electrically and mechanically connected to contact pads or interconnect sites26on carrier substrate or PCB16by a solder reflow process. The semiconductor device provides a short electrical conduction path from the active devices on die14to conduction tracks on carrier substrate or PCB16in order to reduce signal propagation distance, lower capacitance, and achieve overall better circuit performance.

FIGS. 2A-2Eillustrate a process for manufacturing an SiP with integrated semiconductor die or packages. Using the method, a plurality of die may be integrated over a single substrate. When mounting the die, rather than use spacers that take up vertical space, the die are stacked directly over one another using an adhesive. Many different die or IC chips may be combined over the substrate. They are connected to the substrate using wirebonding or another suitable mount technology. In one embodiment, the SiP device includes a cavity ball grid array (BGA) device with a plurality of dies disposed over a substrate. In another embodiment, the device includes a top package interconnect port for external known-good unit (KGU) or known-good-device (KGD) board-level stacking.

Turning toFIG. 2A, a first step in the manufacturing process is shown. Substrate30includes an epoxy-based laminate, printed circuit board, Bismaleimide-Triazine (BT) or other substrate material suitable for the connection of electronic components. Substrate30may include an interconnect structure to electronically connect a plurality of contact pads formed over a surface of substrate30. Furthermore, substrate30may include one or more devices or circuits formed within substrate30or over a surface of substrate30. Substrate30includes a center window or opening32. A plurality of contact pads is formed over substrate30. Contact pads34and36include a conductive material and are formed by a physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, or electroless plating process over a first side of substrate30. Contact pads38,40, and42are formed over a second side of substrate30. Die44is deposited over substrate30. Die44includes packaged semiconductor dies and other electronic packages or integrated circuits (ICs) such as memory, controllers, application specific integrated circuits (ASICs), processors, microcontrollers, or combinations thereof. Contact pad46is formed over a surface of die44using a PVD, CVD, electrolytic plating, or electroless plating process and includes a conductive material. Underfill, die attach material, or adhesive48bonds die44to substrate30. Die50having contact pad52is deposited over substrate30using adhesive54. Die56is deposited over dies44and50using adhesive60and62. Contact pad58is formed over a surface of die56.

FIG. 2Billustrates a second step in manufacturing an SiP with integrated semiconductor die or packages. Wirebond64is formed between contact pad46of die44and contact pad34of substrate30. In other embodiments, wirebonds may be replaced with alternative electrical interconnects such as solder bumps, pins, leads, and the like. Wirebond64includes a conductive material such as copper (Cu), aluminum (Al), gold (Au), or silver (Ag) and forms a physical and electrical connection between contact pad46and contact pad32. Wirebond66is formed between contact pad52of die50and contact pad36of substrate30. Die68is deposited over die56using adhesive74. Contact pads70and72are formed over a surface of die68. Wirebond76connects contact pad70of die68and contact pad34of substrate30. Wirebond78connects contact pad72of die68and contact pad36of substrate30.

FIG. 2Cillustrates a third step in manufacturing an SiP with integrated semiconductor die or packages. The device is inverted and supported by boat80. The shape of boat80is configured to support the device without damaging wirebonds64,66,76, and78. Wirebond82connects contact pad38of substrate30and contact pad58of die56through center window32. Wirebond84connects contact pad40of substrate30and contact pad58of die56.

FIG. 2Dillustrates a fourth step in manufacturing an SiP with integrated semiconductor die or packages. Encapsulant90is deposited around the device. Encapsulant90includes a mold compound, epoxy molding compound, or other insulative material and provides physical support and electrical insulation to the various components of the device. Encapsulant90is deposited using an injection molding, transfer molding, cavity molding, or other molding process. Encapsulant90may further include a filler material to assist in matching the coefficient of thermal expansion (CTE) of encapsulant90to that of the dies or other structures deposited or formed over substrate30. Molds86and88are placed around the device to facilitate deposition of encapsulant90and to control the placement and distribution of encapsulant90.

FIG. 2Eillustrates a final step in manufacturing an SiP with integrated semiconductor die or packages. Bumps92are formed over contact pads42of substrate30. Bumps92are connected to contact pads42by a reflow process applied to solder material deposited over the contact pads. Bumps92include Au, or Cu structures or another conductive material such as tin/lead (Sn/Pb), copper/zinc (CuZn), or copper/silver (CuAg) solder each containing an optional flux material. The solder material is deposited using a ball drop or stencil printing process. Additional system components are connected to bumps92and thereby electronically connect to the circuits and devices formed within dies44,50,56, or68. The device is singulated by shearing, cutting, or routing to physically separate it from other devices formed over the same substrate30or another connected substrate.

FIGS. 3A-3Eillustrate a second process for manufacturing an SiP with integrated semiconductor die or packages. Turning toFIG. 3A, a first step in the manufacturing process is shown. Substrate100includes a substrate material suitable for the connection of electronic components. Substrate100includes a center window or opening102. A plurality of contact pads is formed over substrate100. Contact pads104and106include a conductive material and are formed by a PVD, CVD, electrolytic plating, or electroless plating process over a first side of substrate100. Contact pads108,110, and112are formed over a second side of substrate100. Die114is deposited over substrate100. Die114includes packaged semiconductor dies and other electronic packages or ICs. Contact pad116is formed over a surface of die114using a PVD, CVD, electrolytic plating, or electroless plating process and include a conductive material. Underfill, die attach material, or adhesive118bonds die114to substrate100. Die120having contact pad122is deposited over substrate100using adhesive124. Die126is deposited over dies114and120using adhesive130and132. Contact pad128is formed over a surface of die126.

InFIG. 3C, additional die and wirebonds are connected to the device. The device is supported by boat138during die and wirebond attach. Boat138includes a recess140to protect wirebonds134and136. Wirebond142is formed between contact pad116of die114and contact pad104of substrate100. Wirebond144is formed between contact pad122of die120and contact pad106of substrate100. Die146is deposited over die126using adhesive152. Contact pads148and150are formed over a surface of die146. Wirebond154connects contact pad148of die146and contact pad104of substrate100. Wirebond156connects contact pad150of die146and contact pad106of substrate100.

InFIG. 3D, a molding process is used to form encapsulant162around the device. Molds158and160are placed around the device to facilitate deposition of encapsulant162and to control the placement and distribution of encapsulant162.

FIG. 3Eillustrates a final step in the manufacturing process. Bumps164are formed over contact pads112of substrate100. Bumps164are connected to contact pads112by a reflow process applied to solder material deposited over contact pads112. The solder material is deposited using a ball drop or stencil printing process. Additional system components are connected to bumps164and thereby electronically connect to the circuits and devices formed within dies114,120,126, and146. The device is singulated by shearing, cutting, or routing to physically separate it from other devices formed over the same substrate100or another connected substrate.

In an alternative embodiment, a two-step molding process is used in place of boats80and138. In the two step molding process, wirebonding is performed over one side of the device. That side of the device is then encapsulated. After the encapsulation, the opposite side of the device is wirebonded and encapsulated.

FIG. 4illustrates an SiP having substrate168. A plurality of contact pads is formed over substrate168. Contact pads170and171are formed over a first side of substrate168. Contact pads172,173and174are formed over a second side of substrate168. Die175having contact pad176is deposited over substrate168using underfill or adhesive177. In one embodiment, die175includes a packaged controller device. Wirebond181connects contact pad176to contact pad170of substrate168. Die178having contact pad179is deposited over substrate168using underfill or adhesive180. In one embodiment, die178includes a static random access memory (SRAM) chip. Wirebond182connects contact pad179to contact pad171of substrate168. Die183having contact pad184is deposited using adhesive185and186over both dies175and178. In one embodiment, die183includes a packaged memory device. Wirebond187connects contact pad184of die183to contact pad172of substrate168. Wirebond188connects contact pad184of die183to contact pad173of substrate168. Encapsulant189is deposited over the device. As shown inFIG. 4, encapsulant189covers dies175,178, and183, in addition to wirebonds181,182,187, and188. Bumps190are formed over contact pads174of substrate168. Bumps190may be connected to additional system components.

FIG. 6shows an SiP including a wafer-level chip scale package (WLCSP) or flip-chip stack. A plurality of contact pads is formed over substrate168. Die175having contact pad176is deposited over substrate168using underfill or adhesive177. Wirebond181connects contact pad176to contact pad170of substrate168. Die178having contact pad179is deposited over substrate168using underfill or adhesive180. Wirebond182connects contact pad179to contact pad171of substrate168. Die183having contact pad184is deposited using adhesive185and186over both dies175and178. Wirebond187connects contact pad184of die183to contact pad172of substrate168. Wirebond188connects contact pad184of die183to contact pad173of substrate168. Die197is deposited over die183using adhesive202. Contact pads198and200are formed over a surface of die197. Contact pads198and200include a conductive material and are formed using a PVD, CVD, electrolytic plating, or electroless plating process. Contact pad204is formed over a surface of die175. Contact pad206is formed over a surface of die178. A solder material is deposited between contact pads198and204and contact pads200and206and reflowed to form bumps208and210. Bumps208and210form a mechanical and electrical connection between contact pads198and204and contact pads200and206.

FIG. 7illustrates an SiP with a fan-in interposer suitable for package-on-package (POP) applications. A plurality of contact pads is formed over substrate168. Die175having contact pad176is deposited over substrate168using underfill or adhesive177. Wirebond181connects contact pad176to contact pad170of substrate168. Die178having contact pad179is deposited over substrate168using underfill or adhesive180. Wirebond182connects contact pad179to contact pad171of substrate168. Die183having contact pad184is deposited using adhesive185and186over both dies175and178. Wirebond187connects contact pad184of die183to contact pad172of substrate168. Wirebond188connects contact pad184of die183to contact pad173of substrate168. Substrate or interposer212is deposited over die183using adhesive220and includes a rigid or flexible substrate material. Contact pads214,216, and218are formed over a surface of interposer212. Wirebond222connects contact pad214of interposer212to contact pad170of substrate168. Wirebond224connects contact pad216of interposer212to contact pad171of substrate168. In one embodiment, contact pads218include a plurality of interconnect pads for POP applications. Accordingly, additional system components or KGDs may be stacked over interposer212and connected to contact pads218using solder bumps, wirebonds, or other mount technology.

FIG. 8illustrates an SiP with a fan-in interposer connected to a die stack by conductive bumps. A plurality of contact pads is formed over substrate168. Die175having contact pad176is deposited over substrate168using underfill or adhesive177. Wirebond181connects contact pad176to contact pad170of substrate168. Die178having contact pad179is deposited over substrate168using underfill or adhesive180. Wirebond182connects contact pad179to contact pad171of substrate168. Die183having contact pad184is deposited using adhesive185and186over both dies175and178. Wirebond187connects contact pad184of die183to contact pad172of substrate168. Wirebond188connects contact pad184of die183to contact pad173of substrate168. Substrate or interposer226is deposited over die183using adhesive234. Contact pads230and232are formed over a first surface of interposer226and contact pads228are formed over a second surface of interposer226. Contact pad236is formed over a surface of die175. Contact pad238is formed over a surface of die178. A solder material is deposited between contact pads230and236and contact pads232and238. The solder material is reflowed to form bumps240and242. Bumps240and242mechanically connect contact pads230and236and contact pads232and238. An interconnect structure electrically connects contact pads228to contact pads230and232and the devices formed within dies175,178, and183. In one embodiment, additional system components connect to contact pads228of interposer226and are placed in electrical communication with the devices formed within dies175,178, and183.

FIG. 9illustrates an SiP with a stacked heat spreader. A plurality of contact pads is formed over substrate168. Die175having contact pad176is deposited over substrate168using underfill or adhesive177. Wirebond181connects contact pad176to contact pad170of substrate168. Die178having contact pad179is deposited over substrate168using underfill or adhesive180. Wirebond182connects contact pad179to contact pad171of substrate168. Die183having contact pad184is deposited using adhesive185and186over both dies175and178. Wirebond187connects contact pad184of die183to contact pad172of substrate168. Wirebond188connects contact pad184of die183to contact pad173of substrate168. Die191having contact pads192and193is deposited over die183using adhesive194. Wirebond195connects contact pad192of die191to contact pad170of substrate168. Wirebond196connects contact pad193of die191to contact pad171of substrate168. Heat spreader244is connected to die191using adhesive246. Heat spreader244includes a heat spreader and/or heat sink structure to remove heat energy from the device and to normalize heat distribution over a surface of die191. Heat spreader244includes a metal such as Al or Cu or another material with high thermal conductivity.

FIG. 10illustrates an SiP with a stacked die having exposed pads for POP interconnect. A plurality of contact pads is formed over substrate168. Die175having contact pad176is deposited over substrate168using underfill or adhesive177. Wirebond181connects contact pad176to contact pad170of substrate168. Die178having contact pad179is deposited over substrate168using underfill or adhesive180. Wirebond182connects contact pad179to contact pad171of substrate168. Die183having contact pad184is deposited using adhesive185and186over both dies175and178. Wirebond187connects contact pad184of die183to contact pad172of substrate168. Wirebond188connects contact pad184of die183to contact pad173of substrate168. Die248is deposited over die183using adhesive256. Die248includes an IC die having a surface over which contact pads250,252and254are formed. Contact pads250,252and254include a conductive material and are formed using a PVD, CVD, electrolytic plating, or electroless plating process. Wirebond258connects contact pad250of die248to contact pad170of substrate168. Wirebond260connects contact pad252of die248to contact pad171of substrate168. Additional system devices, packages, or die may be connected to contact pads254of die248. In one embodiment, an additional semiconductor package is flip-chip mounted to contact pads254of die248. The deposition of encapsulant189is controlled to expose the contact pads formed over a surface of die248.

FIG. 11illustrates an SiP without a mold or encapsulant protrusion. The device includes substrate168. Substrate168includes recessed bond fingers262and264that are covered by encapsulant189. Contact pads266and268are formed over bond fingers262and264. Die175having contact pad176is deposited over substrate168using underfill or adhesive177. Wirebond181connects contact pad176to contact pad170of substrate168. Die178having contact pad179is deposited over substrate168using underfill or adhesive180. Wirebond182connects contact pad179to contact pad171of substrate168. Die183having contact pad184is deposited using adhesive185and186over both dies175and178. Wirebond270connects contact pad184of die183to contact pad266of substrate168. Wirebond272connects contact pad184of die183to contact pad268of substrate168. Die191having contact pads192and193is deposited over die183using adhesive194. Wirebond195connects contact pad192of die191to contact pad170of substrate168. Wirebond196connects contact pad193of die191to contact pad171of substrate168. Deposition of encapsulant189is controlled to prevent formation of a protrusion around a center window of substrate168. In all embodiments including encapsulant, the deposition of encapsulant may be controlled to prevent the formation of such a protrusion. In an alternative embodiment, encapsulant189is initially deposited with a protrusion which is later removed using an etching or planarization process.

Turning toFIG. 12, the device includes semiconductor die deposited over leadframe280. Leadframe280includes a conductive material such as Cu, or Al. Generally, the CTE of leadframe280is approximately matched to that of the dies, molding compound, and/or other structure deposited over leadframe280. Leadframe280includes a center window or opening282. As shown inFIG. 12, leadframe280includes half-etched leads284and286(the half-etched portion identified as288and290) for improved physical integrity of the device. Die292having contact pad294is deposited over lead284of leadframe280using underfill, die attach material, or adhesive296. In one embodiment, die292includes a packaged controller device. Wirebond304connects contact pad294of die292to lead284. Die298having contact pad300is deposited over lead286of leadframe280using adhesive302. In one embodiment, die298includes an SRAM chip. Wirebond306connects contact pad300of die298to lead286. Die308having contact pad310is deposited over dies292and298using adhesive312and314. In one embodiment, die308includes a memory IC. Wirebond315connects contact pad310to lead284of leadframe280. Wirebond316connects contact pad310to lead286of leadframe280. Wirebonds315and316are formed through window282of leadframe280. Encapsulant318is deposited over dies292,298, and308, and leadframe280. Encapsulant318includes a mold compound, epoxy molding compound, or other insulative material and provides physical support and electrical insulation to the various components of the device. Encapsulant318is deposited using an injection molding, transfer molding, cavity molding, or other molding process. Encapsulant318may further include a filler material to assist in matching the CTE of encapsulant318to that of the dies or other structure deposited over leadframe280.

FIG. 14shows an SiP with a half-etch leadframe and WLCSP or flip-chip stack. Die292having contact pad294is deposited over lead284of leadframe280using underfill, die attach material, or adhesive296. Wirebond304connects contact pad294of die292to lead284. Die298having contact pad300is deposited over lead286of leadframe280using adhesive302. Wirebond306connects contact pad300of die298to lead286. Die308having contact pad310is deposited over dies292and298using adhesive312and314. Wirebond315connects contact pad310to lead284of leadframe280. Wirebond316connects contact pad310to lead286of leadframe280. Die330having contact pads332and334is mounted over die308using adhesive336. Contact pad338includes a conductive material and is formed over a surface of die292. Contact pad340is formed over a surface of die298. Contact pads338and340may include redistributed UBM pads to facilitate the connection and reflow of solder material over a surface of contact pads338and340. Solder material is deposited between contact pads332and338and contact pads334and340and is reflowed to form bumps342and344. Bumps342and344form a mechanical and electrical connection between contact pads332and338and contact pads334and340.

Turning toFIG. 15, an SiP with an overhang stack and leadframe346is illustrated. Leadframe346includes a conductive material such as Cu, or Al. Generally, the CTE of leadframe346is approximately matched to that of the dies, molding compound, and/or other structure deposited over leadframe346. Leadframe346includes a center window or opening348. As shown inFIG. 15, leadframe346includes half-etched leads350and352for improved physical integrity of the device. Die354having contact pad356is deposited over lead350using underfill, die attach material, or adhesive358. In one embodiment, die354includes a packaged controller device. Wirebond366connects contact pad356of die354to lead350. Die360having contact pad362is deposited over lead352using adhesive364. In one embodiment, die360includes an SRAM chip. Wirebond368connects contact pad362of die360to lead352. Die370having contact pad372is deposited over dies354and360using adhesive374and376. In one embodiment, die370includes a memory IC. Wirebond378connects contact pad372of die370to contact pad356of die354. Wirebond380connects contact pad372of die370to lead350. Wirebond382connects contact pad372of die370to lead352. Wirebond384connects contact pad372of die370to contact pad362of die360. Die386having contact pads388and390is deposited over die370using adhesive392. Wirebond394connects contact pad388of die386to lead350. Wirebond396connects contact pad390of die386to lead352. Over dies354,360,370, and386and leadframe346, encapsulant398is deposited. Encapsulant398includes a mold compound, epoxy molding compound, or other insulative material and provides physical support and electrical insulation to the various components of the device. Encapsulant398is deposited using an injection molding, transfer molding, cavity molding, or other molding process. Encapsulant398may further include a filler material to assist in matching the CTE of encapsulant398to that of the dies or other structure deposited over leadframe346.

FIG. 18illustrates an SiP with an exposed die or laminate interposer for top interconnect. Die354having contact pad356is deposited over lead350using underfill, die attach material, or adhesive358. In one embodiment, die354includes a packaged controller device. Wirebond366connects contact pad356of die354to lead350. Die360having contact pad362is deposited over lead352using adhesive364. In one embodiment, die360includes an SRAM chip. Wirebond368connects contact pad362of die360to lead352. Die400having contact pad402is deposited over die354using adhesive404. Wirebond412connects contact pad402of die400to contact pad356of die354. Wirebond414connects contact pad402of die400to lead350. Die406having contact pad408is deposited over die360using adhesive410. Wirebond416connects contact pad408of die406to contact pad362of die360. Wirebond418connects contact pad408of die406to lead352. Wirebond420connects connect pad402of die400to contact pad408of die406. Die422having contact pads424and426is deposited over dies400and406using adhesive428and430. Wirebond432connects contact pad424of die422to lead350. Wirebond434connects contact pad426of die422to lead352. A plurality of contact pads438are formed over a top surface of die422using a PVD, CVD, electrolytic plating, or electroless plating process. Deposition of encapsulant398is controlled to expose the top surface of die422and contact pads438formed thereon. Die436is deposited over the top surface of die422using a surface mount technology (SMT). InFIG. 18, die436is a flip-chip mounted to die422using bumps440. Solder material is deposited between contact pads or UBM pads (not shown) formed over a surface of die436and contact pads438. The solder material is then reflowed to form bumps440that form a mechanical and electrical bond between die436and die422.

Semiconductor devices in the various embodiments shown can be manufactured using tools and equipment commonly known in the art, such as wire bonding, patterning, etching and similar equipment. Semiconductor devices serve to continue to advance integrated passive device technology at reduced fabrication cost, while resulting in larger overall repeatable quality.