Liquid crystal display device and method for manufacturing a same

A liquid crystal display device includes a first substrate spaced from a second substrate, a liquid crystal layer between the first and second substrates, a gate line, a data line, a first sub-pixel electrode, and a second sub-pixel electrode on the first substrate. The display device also includes a first switch and a second switch. The first switch is connected to the gate line, the data line, and the first sub-pixel electrode. The second switch is connected to the gate line, the data line, and the second sub-pixel electrode. The second switch includes a first gate electrode connected to the gate line and a second gate electrode not connected to the gate line.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2016-0044784, filed on Apr. 12, 2016, and entitled, “Liquid Crystal Display Device and Method for Manufacturing A Same,” is incorporated by reference herein in its entirety.

BACKGROUND

One or more embodiments herein relate to a liquid crystal display device and a method for manufacturing a liquid crystal display device.

2. Description of the Related Art

A liquid crystal display (LCD) has a liquid crystal layer between two substrates containing electrodes. When voltages are applied to the electrodes, liquid crystal molecules in the liquid crystal layer rearrange to transmit light to display an image.

In an attempt to improve visibility, each pixel may include two individual sub-pixel electrodes. In such a case, data signals of different levels may be applied to the sub-pixel electrodes, respectively. The data signal is applied to one of the two sub-pixel electrodes without modulation, and the data signal is divided and applied to the other of the two sub-pixel electrodes. The division is performed by a voltage-dividing transistor in the pixel.

The voltage-dividing transistor may cause problems. For example, the voltage-dividing transistor may decrease aperture ratio because it occupies a portion of the pixel. In addition, when the voltage-dividing transistor is turned on, a data line and a storage electrode are electrically connected to each other. As a result, a storage voltage of the storage electrode may vary based on the data signal.

SUMMARY

In accordance with one or more embodiments, a liquid crystal display device includes a first substrate spaced from a second substrate; a liquid crystal layer between the first and second substrates; a gate line, a data line, a first sub-pixel electrode, and a second sub-pixel electrode on the first substrate; a first switch connected to the gate line, the data line, and the first sub-pixel electrode; and a second switch connected to the gate line, the data line, and the second sub-pixel electrode, wherein the first switch includes a first gate electrode connected to the gate line and a first semiconductor layer spaced from the first gate electrode, the second switch includes a second gate electrode connected to the gate line and a second semiconductor layer spaced from the second gate electrode, a first distance between the first gate electrode and the first semiconductor layer is different from a second distance between the second gate electrode and the second semiconductor layer.

The second distance is greater than the first distance.

The second switch further includes a third gate electrode spaced from the second semiconductor layer.

The third gate electrode is connected to the gate line.

The third gate electrode does not contact any conductor including the gate line.

The device further comprising: a bias line to transmit a bias voltage to the third gate electrode.

The first switch further includes a fourth gate electrode connected to the gate line.

In a channel area of the second switch a distance between the second semiconductor layer and the second gate electrode of the second switch is longer than a distance between the second semiconductor layer and the third gate electrode.

The device further comprises a first insulating layer between the second semiconductor layer and the second gate electrode in the channel area; and a second insulating layer between the second semiconductor layer and the third gate electrode in the channel area, wherein the second insulating layer has a smaller thickness than the first insulating layer.

The first insulating layer and the second insulating layer have a unitary construction.

The second switch further includes: a drain electrode on the first substrate and connected to the data line; a source electrode on the drain electrode and connected to the second sub-pixel electrode; and the second semiconductor layer is between the drain electrode and the source electrode.

The device further comprises a first ohmic contact layer between the drain electrode and the second semiconductor layer; and a second ohmic contact layer between the source electrode and the second semiconductor layer.

The second switch further includes a third gate electrode spaced from the second semiconductor layer, and the second gate electrode and the third gate electrode extend in a perpendicular direction with respect to a surface of the first substrate.

The second switch further includes a third gate electrode spaced from the second semiconductor layer, a first portion of the second gate electrode and a first portion of the third gate electrode are on a same layer as the first ohmic contact layer, and a second portion of the second gate electrode and a second portion of the third gate electrode are on a same layer as the second ohmic contact layer.

The second switch further includes a third gate electrode spaced from the second semiconductor layer, and at least a portion of the second gate electrode and at least a portion of the third gate electrode are on a same layer as the second semiconductor layer.

The second switch further includes a third gate electrode spaced from the second semiconductor layer, a first portion of the second gate electrode and a first portion of the third gate electrode are on a same layer as the drain electrode, and a second portion of the second gate electrode and a second portion of the third gate electrode are on a same layer as the source electrode.

The second gate electrode and the gate line are on different layers.

The second gate electrode is on a same layer as one of the first sub-pixel electrode or the second sub-pixel electrode.

The second gate electrode includes a same material as one of the first sub-pixel electrode, the second sub-pixel electrode, or the gate line.

The device further comprises an insulating layer having a contact hole connecting the second gate electrode and the gate line.

In accordance with one or more other embodiments, a method for manufacturing a liquid crystal display device includes sequentially stacking a first metal layer, a first impurity semiconductor material layer, a semiconductor material layer, a second impurity semiconductor material layer, and a second metal layer on a substrate; forming a first photoresist pattern and a second photoresist pattern on the second metal layer, the second photoresist pattern having a thickness less than the first photoresist pattern; forming a drain electrode on the substrate, a first ohmic contact layer on the drain electrode, a semiconductor layer on the first ohmic contact layer, an impurity semiconductor pattern on the semiconductor layer, and a source metal layer on the impurity semiconductor pattern by removing the first metal layer, the first impurity semiconductor material layer, the semiconductor material layer, the second impurity semiconductor material layer, and the second metal layer using the first and second photoresist patterns as a mask; removing a portion of the first photoresist pattern and the second photoresist pattern; forming a second ohmic contact layer on the semiconductor layer and a source electrode on the second ohmic contact layer by removing the impurity semiconductor pattern and the source metal layer using the first photoresist pattern as a mask; removing the first photoresist pattern; forming a gate insulating layer on the substrate, the semiconductor layer, and the source electrode; defining a first hole in the gate insulating layer; forming a first gate electrode in the first hole of the gate insulating layer; forming a passivation layer on the gate line; defining a contact hole in the passivation layer, the contact hole exposing the source electrode; and forming a pixel electrode on the passivation layer, the pixel electrode connected to the source electrode through the contact hole.

The method may include forming, on the substrate, a data line connected to the drain electrode. The method may include forming, on the passivation layer, a gate line connected to the gate electrode. The method may include forming, on the passivation layer, a color filter having a contact hole corresponding to the source contact hole. The method may include defining a second hole in the gate insulating layer; and forming a second gate electrode in the second hole, the second gate electrode not connected to any conductor. A thickness of the gate insulating layer between a channel area of the semiconductor layer and the second gate electrode may be less than a thickness of the gate insulating layer between the channel area and the first gate electrode.

DETAILED DESCRIPTION

Throughout the specification, when an element is referred to as being “connected” to another element, the element is “directly connected” to the other element, or “electrically connected” to the other element with one or more intervening elements interposed therebetween. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

FIG. 1illustrates an equivalent circuit diagram of an embodiment of a pixel PX of an LCD device. As illustrated inFIG. 1, the pixel PX includes a first switching element TFT1, a second switching element TFT2, a first sub-pixel electrode PE1, a second sub-pixel electrode PE2, a first liquid crystal capacitor Clc1, a second liquid crystal capacitor Clc2, a first storage capacitor Cst1, and a second storage capacitor Cst2.

The first switching element TFT1is connected to a gate line GL, a data line DL, and the first sub-pixel electrode PE1. The first switching element TFT1is controlled based on a gate signal from the gate line GL and is connected between the data line DL and the first sub-pixel electrode PE1. The first switching element TFT1is turned on by a gate high voltage of the gate signal and, when turned on, applies a data voltage applied from the data line DL to the first sub-pixel electrode PE1In an implementation, the first switching element TFT1is turned off by a gate low voltage of the gate signal. The data voltage is an image data voltage.

The first switching element TFT1includes a first gate electrode GE1connected to the gate line GL, a first drain electrode DE1connected to the data line DL, and a first source electrode SE1connected to the second sub-pixel electrode PE2.

The first liquid crystal capacitor Clc1is between the first sub-pixel electrode PE1and a common electrode330. The first liquid crystal capacitor Clef includes a first electrode connected to the first sub-pixel electrode PE1, a second electrode connected to the common electrode330, and a liquid crystal layer between the first electrode and the second electrode. The first electrode of the first liquid crystal capacitor Clc1may be a portion of the first sub-pixel electrode PE1. The second electrode of the first liquid crystal capacitor Clc1may be a portion of the common electrode330.

A common voltage Vcom is applied to the common electrode330.

The first storage capacitor Cst1is between the first sub-pixel electrode PE1and a first storage electrode751. The first storage capacitor Cst1includes a first electrode connected to the first sub-pixel electrode PE1, a second electrode connected to the first storage electrode751, and a dielectric material between the first electrode of the first storage capacitor Cst1and the second electrode of the first storage capacitor Cst1. The dielectric material includes at least one insulating layer. The first electrode of the first storage capacitor Cst1may be a portion of the first sub-pixel electrode PE1. The second electrode of the first storage capacitor Cst1may be a portion of the first storage electrode751.

A first storage voltage Vcst1is applied to the first storage electrode751. The first storage voltage Vcst1may have a voltage level equal to that of the common voltage Vcom.

The second switching element TFT2is connected to the gate line GL, the data line DL, and the second sub-pixel electrode PE2. The second switching element TFT2is controlled by the gate signal from the gate line GL and is connected between the data line DL and the second sub-pixel electrode PE2. The second switching element TFT2is turned on by the gate high voltage of the gate signal, and, when turned on, applies a data voltage applied from the data line DL to the second sub-pixel electrode PE2. The second switching element TFT2is turned off by the gate low voltage of the gate signal. The data voltage is an image data voltage.

The second switching element TFT2includes a first gate electrode GE11(an auxiliary gate electrode) connected to the gate line GL, a second drain electrode DE2connected to the data line DL, a second source electrode SE2connected to the second sub-pixel electrode PE2, and a second gate electrode GE22(main gate electrode) having a floating structure.

The main gate electrode GE22may not physically contact any conductor including the gate line GL.

In a channel area CA2of the second switching element TFT2, a distance between a semiconductor layer322and the auxiliary gate electrode GE11of the second switching element TFT2may be a first distance and a distance between the semiconductor layer322and the main gate electrode GE22thereof may be a second distance. The first distance is greater than the second distance. Accordingly, when receiving the gate high voltage through the auxiliary gate electrode GE11, rather than through the main gate electrode GE22, the second switching element TFT2exhibits lower current driving capability. As illustrated inFIG. 1, since connected to the gate line GL through the auxiliary gate electrode GE11, the second switching element TFT2has relatively lower current driving capability.

In an implementation, the second switching element TFT2connected to the gate line GL through the main gate electrode GE22, rather than through the auxiliary gate electrode GE11, may have lower or higher current driving capability than that of the first switching element TFT1. In addition, the second switching element TFT2connected to the gate line GL through both of the auxiliary gate electrode GE11and the main gate electrode GE22may have lower or higher current driving capability than that of the first switching element TFT1.

The second liquid crystal capacitor Clc2is between the second sub-pixel electrode PE2and the common electrode330. The second liquid crystal capacitor Clc2includes a first electrode connected to the second sub-pixel electrode PE2, a second electrode connected to the common electrode330, and a liquid crystal layer between the first electrode of the second liquid crystal capacitor Clc2and the second electrode of the second liquid crystal capacitor Clc2. The first electrode of the second liquid crystal capacitor Clc2may be a portion of the second sub-pixel electrode PE2. The second electrode of the second liquid crystal capacitor Clc2may be a portion of the common electrode330.

The second storage capacitor Cst2is between the second sub-pixel electrode PE2and a second storage electrode752. The second storage capacitor Cst2includes a first electrode connected to the second sub-pixel electrode PE2, a second electrode connected to the second storage electrode752, and a dielectric material between the first electrode of the second storage capacitor Cst2and the second electrode of the second storage capacitor Cst2. The dielectric material includes at least one insulating layer. The first electrode of the second storage capacitor Cst2may be a portion of the second sub-pixel electrode PE2. The second electrode of the second storage capacitor Cst2may be a portion of the second storage electrode752.

A second storage voltage Vcst2is applied to the second storage electrode752. The second storage voltage Vcst2may have a voltage level equal to that of the common voltage Vcom.

The aforementioned gate high voltage is a high logic voltage of the gate signal and is set to be a voltage greater than or equal to a higher one of a threshold voltage of the first switching element TFT1or a threshold voltage of the second switching element TFT2. The aforementioned gate low voltage is a low logic voltage of the gate signal and is set to be an off-voltage of the first switching element TFT1and the second switching element TFT2.

In operation, when the gate high voltage is applied to the gate line GL, the first switching element TFT1and the second switching element TFT2are turned on. A data voltage from the data line DL is applied to the first sub-pixel electrode PE1through the turned-on first switching element TFT1. In such an implementation, due to a voltage drop arising from an inner resistance of the first switching element TFT1, a data voltage (first sub-pixel voltage) of the first sub-pixel electrode PE1has a lower voltage level than that of the data voltage of the data line DL.

A data voltage from the data line DL is applied to the second sub-pixel electrode PE2through the turned-on second switching element TFT2. In such an implementation, due to a voltage drop arising from an inner resistance of the second switching element TFT2, a data voltage (second sub-pixel voltage) of the second sub-pixel electrode PE2has a lower voltage level than that of the data voltage of the data line DL.

The turned-on first switching element TFT1and the turned-on second switching element TFT2both operate in a linear region. Based on the inner resistances of the first switching element TFT1and the second switching element TFT2, a ratio between the first sub-pixel voltage and the second sub-pixel voltage may be calculated.

As described hereinabove, the second switching element TFT2has lower current driving capability than that of the first switching element TFT1. Accordingly, the second switching element TFT2has greater inner resistance than that of the first switching element TFT1. Accordingly, the first sub-pixel voltage and the second sub-pixel voltage may have different values. For example, the second sub-pixel voltage is lower than the first sub-pixel voltage. Accordingly, visibility of a pixel may be improved.

In addition, only two switching elements (e.g., the first switching element TFT1and the second switching element TFT2) may be used to generate two sub-pixel voltages having different voltage levels. Thus, the aperture ratio of the pixel may increase.

The data line DL and the first and second storage electrodes751and752are not directly connected to one another. Thus, variation of the first storage voltage Vcst1and the second storage voltage Vcst2may be significantly reduced. For example, the first storage capacitor Cst1and the second storage capacitor Cst2are connected among respective ones of the storage electrodes751and752and the data line DL, respectively. Thus, variation of the first storage voltage Vcst1and the second storage voltage Vcst2may be significantly reduced.

Such a pixel circuit may be achieved through a pixel configuration to be described hereinbelow. Hereinbelow, a pixel configuration corresponding to the pixel circuit illustrated inFIG. 1will be described.

FIG. 2illustrates a plan or layout view of an embodiment of an LCD device including a pixel configuration corresponding to the pixel circuit ofFIG. 1.FIG. 3illustrates a cross-sectional view taken along line I-I′ ofFIG. 2.FIG. 4illustrates a cross-sectional view taken along line II-II′ ofFIG. 2.

As illustrated inFIGS. 2, 3, and 4, the LCD device includes a first substrate301, a gate line GL, a first gate electrode GE1, a main gate electrode GE22, an auxiliary gate electrode GE11, a first storage electrode751, a storage line750, a second storage electrode752, a gate insulating layer311, a first semiconductor layer321, a second semiconductor layer322, a first ohmic contact layer321a, a second ohmic contact layer321b, a third ohmic contact layer322a, a fourth ohmic contact layer322b, a data line DL, a first drain electrode DE1, a first source electrode SE1, a second drain electrode DE2, a second source electrode SE2, a passivation layer320, a capping layer391, a color filter354, a first sub-pixel electrode PE1, a second sub-pixel electrode PE2, a second substrate302, a light blocking layer376, an overcoat layer722, a common electrode330, and a liquid crystal layer333. In an implementation, at least one of the first ohmic contact layer321a, the second ohmic contact layer321b, the third ohmic contact layer322a, or the fourth ohmic contact layer322bmay be omitted.

As illustrated inFIGS. 2 and 3, the first switching element TFT1includes the first gate electrode GE1, the first semiconductor layer321, the first drain electrode DE1, and the first source electrode SE1.

As illustrated inFIGS. 2 and 4, the second switching element TFT2includes the main gate electrode GE22, the auxiliary gate electrode GE11, the second semiconductor layer322, the second drain electrode DE2, and the second source electrode SE2.

As illustrated inFIGS. 2 and 3, the gate line GL is on the first substrate301. For example, the gate line GL may be between a first sub-pixel area P1and a second sub-pixel area P2of the first substrate301.

As illustrated inFIGS. 2 and 3, the gate line GL is connected to the first gate electrode GE1. The gate line GL and the first gate electrode GE1may have a unitary construction, e.g., a one-piece, monolithic structure. In an implementation, an end portion of the gate line GL may be connected to another layer or an external driving circuit. The end portion of the gate line GL may have a larger area than an area of another portion thereof.

The gate line GL may include or be formed of, e.g., aluminum (Al) or alloys thereof, silver (Ag) or alloys thereof, copper (Cu) or alloys thereof, and/or molybdenum (Mo) or alloys thereof. In an implementation, the gate line GL may include or be formed of, e.g., one of chromium (Cr), tantalum (Ta) and titanium (Ti). In an implementation, the gate line GL may have a multilayer structure including at least two conductive layers having different physical properties from one another.

As illustrated inFIG. 2, the first gate electrode GE1may have a shape protruding from the gate line GL. The first gate electrode GE1may be a portion of the gate line GL. The first gate electrode GE1may include substantially a same material and may have a same structure (multilayer structure) as those of the gate line GL. In an implementation, the first gate electrode GE1and the gate line GL may be simultaneously formed in a same process.

As illustrated inFIG. 2, the main gate electrode GE22has a floating structure not connected to any conductor. The main gate electrode GE22may include substantially a same material and may have a same structure (multilayer structure) as those of the gate line GL. The main gate electrode GE22and the gate line GL may be simultaneously formed in a same process. In an implementation, the main gate electrode GE22may be connected to a bias line777. The bias line777transmits a constant direct current (DC) voltage (a bias voltage) to the main gate electrode GE22.

As illustrated inFIG. 2, the first storage electrode751may have a shape enclosing the first sub-pixel electrode PE1. The first storage electrode751may overlap an edge portion of the first sub-pixel electrode PE1. The first storage voltage Vcst1is applied to the first storage electrode751. The first storage voltage Vcst1may have a voltage level equal to that of the common voltage Vcom. The first storage electrode751may include substantially a same material and have a same structure (multilayer structure) as those of the gate line GL. In an implementation, the first storage electrode751and the gate line GL may be simultaneously formed in a same process.

The first storage electrode751is connected to the storage line750. As illustrated inFIG. 2, the storage line750is between the first sub-pixel area P1and the second sub-pixel area P2. The storage line750is parallel to the gate line GL. The first storage voltage Vcst1is applied to the storage line750. In such an implementation, the first storage electrode751and the storage line750may have a unitary construction, e.g., may have a one-piece, monolithic structure. The storage line750may include substantially a same material and have a same structure (multilayer structure) as those of the gate line GL. The storage line750and the gate line GL may be simultaneously formed in a same process.

As illustrated inFIG. 2, the second storage electrode752may have a shape enclosing the second sub-pixel electrode PE2. The second storage electrode752may overlap an edge portion of the second sub-pixel electrode PE2. The second storage electrode752may include substantially a same material and have a same structure (a multilayer structure) as those of the gate line GL. The second storage electrode752and the gate line GL may be simultaneously formed in a same process.

The second storage voltage Vcst2is applied to the second storage electrode752. The second storage voltage Vcst2may have a voltage level equal to that of the common voltage Vcom. In an implementation, the second storage electrode752and the first storage electrode751may have a unitary construction, e.g., a one-piece, monolithic structure. The second storage electrode752may include substantially a same material and have a same structure (a multilayer structure) as those of the gate line GL. In an implementation, the second storage electrode752and the gate line GL may be simultaneously formed in a same process.

As illustrated inFIGS. 3 and 4, the gate insulating layer311is on the gate line GL, the first gate electrode GE1, the main gate electrode GE22, the first storage electrode751, the second storage electrode752, and the storage line750. In such an implementation, the gate insulating layer311is over an entire surface of the first substrate301including the gate line GL, the first gate electrode GEL the main gate electrode GE22, the first storage electrode751, the second storage electrode752, and the storage line750. The gate insulating layer311has a hole corresponding to the gate line GL. The gate insulating layer311may include or be formed of, e.g., silicon nitride (SiNx) or silicon oxide (SiOx). The gate insulating layer311may have a multilayer structure including at least two insulating layers having different physical properties.

As illustrated inFIG. 3, the data line DL is on the gate insulating layer311. An end portion of the data line DL may be connected to another layer or an external driving circuit. The end portion of the data line DL may have a larger area than that of another portion of the data line DL.

The data line DL intersects the gate line GL and the storage line750. A portion of the data line DL intersecting the gate line GL may have a smaller line width than that of another portion of the data line DL. Similarly, a portion of the data line DL intersecting the storage line750may have a smaller line width than that of another portion of the data line DL. Accordingly, parasitic capacitance between the data line DL and the gate line GL and capacitance between the data line DL and the storage line750may be reduced.

The data line DL may include or be formed of, e.g., refractory metal, such as molybdenum, chromium, tantalum and titanium, or an alloy thereof. The data line DL may have a multilayer structure including a refractory metal layer and a low-resistance conductive layer. Examples of the multilayer structure may include: a double-layer structure including a chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer; and a triple-layer structure including a molybdenum (alloy) lower layer, an aluminum (alloy) intermediate layer, and a molybdenum (alloy) upper layer. In an implementation, the data line DL may include or be formed of suitable metals or conductors rather than the aforementioned materials.

As illustrated inFIG. 3, the first semiconductor layer321is on the gate insulating layer311. As illustrated inFIGS. 2 and 3, the first semiconductor layer321may overlap at least a portion of the first gate electrode GE1. The first semiconductor layer321may include or be formed of, e.g., amorphous silicon, polycrystalline silicon, or the like.

As illustrated inFIG. 3, the first ohmic contact layer321aand the second ohmic contact layer321bare on the first semiconductor layer321. The first ohmic contact layer321aand the second ohmic contact layer321bmay face or be laterally aligned with each other, with a channel area CA1of the first switching element TFT1therebetween. At least one of the first ohmic contact layer321aand the second ohmic contact layer321bmay include or be formed of silicide or n+ hydrogenated amorphous silicon doped with n-type impurity ions, e.g., phosphorus or hydrogen phosphide (PH3), at high concentration.

As illustrated inFIG. 4, the second semiconductor layer322is on the gate insulating layer311. As illustrated inFIGS. 2 and 4, the second semiconductor layer322overlaps at least a portion of the main gate electrode GE22and the auxiliary gate electrode GE11. The second semiconductor layer322may include or be formed of, e.g., amorphous silicon, polycrystalline silicon, or the like.

As illustrated inFIG. 4, the third ohmic contact layer322aand the fourth ohmic contact layer322bare on the second semiconductor layer322. The third ohmic contact layer322aand the fourth ohmic contact layer322bmay face or be laterally aligned with each other, with a channel area CA2of the second switching element TFT2therebetween. At least one of the third ohmic contact layer322aand the fourth ohmic contact layer322bmay include or be formed of silicide or n+ hydrogenated amorphous silicon doped with n-type impurities, such as phosphorus or hydrogen phosphide (PH3), at high concentration.

The third ohmic contact layer322aand the aforementioned first ohmic contact layer321aare connected to each other. For example, the third ohmic contact layer322aand the aforementioned first ohmic contact layer321amay have a unitary construction, e.g., a one-piece, monolithic structure.

As illustrated inFIG. 3, the first drain electrode DE1is on the first ohmic contact layer321a. In an implementation, the first drain electrode DE1may also be on the gate insulating layer311. The first drain electrode DE1, as illustrated inFIG. 2, may have a shape protruding from the data line DL. In an implementation, the first drain electrode DE1may be a portion of the data line DL. At least a portion of the first drain electrode DE1overlaps the first semiconductor layer321and the first gate electrode GE1. In an implementation, the first drain electrode DE1may have a predetermined shape, e.g., an I-shape, a C-shape, or a U-shape. The first drain electrode DE1inFIG. 2to have a U-shape. A convex portion of the first drain electrode DE1faces the second sub-pixel electrode PE2. The first drain electrode DE1may include substantially a same material and may have a same structure (multilayer structure) as those of the data line DL. In an implementation, the first drain electrode DE1and the data line DL may be simultaneously formed in a same process.

As illustrated inFIG. 3, the first source electrode SE1is on the second ohmic contact layer321band the gate insulating layer311. At least a portion of the first source electrode SE1overlaps the first semiconductor layer321and the first gate electrode GE1. The first source electrode SE1is connected to the first sub-pixel electrode PE1. The first source electrode SE1may include substantially a same material and may have a same structure (multilayer structure) as those of the data line DL. In an implementation, the first source electrode SE1and the data line DL may be simultaneously formed in a same process.

The channel area CA1of the first switching element TFT1is in a portion of the first semiconductor layer321between the first drain electrode DE1and the first source electrode SE1.

As illustrated inFIG. 4, the second drain electrode DE2is on the third ohmic contact layer322a. The second drain electrode DE2may also be on the gate insulating layer311. The second drain electrode DE2and the first drain electrode DE1may have a unitary construction, e.g., a one-piece, monolithic structure. At least a portion of the second drain electrode DE2overlaps the second semiconductor layer322, the main gate electrode GE22, and the auxiliary gate electrode GE11. In an implementation, the second drain electrode DE2has a predetermined shape, e.g., an I-shape, a C-shape, or a U-shape. The second drain electrode DE2inFIG. 2has a U-shape. A convex portion of the second drain electrode DE2faces the first sub-pixel electrode PE1. The second drain electrode DE2may include substantially a same material and may have a same structure (multilayer structure) as those of the data line DL. In an implementation, the second drain electrode DE2and data line DL may be simultaneously formed in a same process.

As illustrated inFIG. 4, the second source electrode SE2is on the fourth ohmic contact layer322band the gate insulating layer311. At least a portion of the second source electrode SE2overlaps the second semiconductor layer322and the main gate electrode GE22. The second source electrode SE2is connected to the second sub-pixel electrode PE2. The second source electrode SE2may include substantially a same material and may have a same structure (a multilayer structure) as those of the data line DL. In an implementation, the second source electrode SE2and the data line DL may be simultaneously formed in a same process.

The channel area CA2of the second switching element TFT2may be in a portion of the second semiconductor layer322between the second drain electrode DE2and the second source electrode SE2.

As illustrated inFIGS. 3 and 4, the passivation layer320is on the data line DL, the first drain electrode DE1, the second drain electrode DE2, the first source electrode SE1, and the second source electrode SE2. In such an implementation, the passivation layer320is on the entire surface of the first substrate301including the data line DL, the first drain electrode DE1, the second drain electrode DE2, the first source electrode SE1, and the second source electrode SE2. The passivation layer320has a first hole above the first source electrode SE1, a second hole above the second source electrode SE2, and a third hole above the hole of the gate insulating layer311.

The passivation layer320may include or be formed of, e.g., an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). In such an implementation, an inorganic insulating material having photosensitivity and a dielectric constant of, for example, about 4.0 may be used. In an implementation, the passivation layer320may have a double-layer structure, including a lower inorganic layer and an upper organic layer. Such a structure may impart improved insulating properties and also may help reduce and/or prevent damage to exposed portions of the first semiconductor layer321and the second semiconductor layer322. In an implementation, the passivation layer320may have a thickness greater than or equal to about 5,000 Å, e.g., about 6,000 Å to about 8,000 Å.

As illustrated inFIGS. 3 and 4, the color filter354is on the passivation layer320. The color filter354is in the first sub-pixel area P1and the second sub-pixel area P2, and in such an implementation, an edge portion of the color filter354is on the data line DL. An edge portion of one of the color filters354may overlap an edge portion of an adjacent one of the color filters354. Color filters having a same color are respectively disposed in the first sub-pixel area P1and the second sub-pixel area P2in a single pixel. The color filter354has a first hole, a second hole, and a third hole. In such an implementation, the first hole of the color filter354is above the first hole of the passivation layer320. The second hole of the color filter354is positioned the second hole of the passivation layer320. The third hole of the color filter354is above the third hole of the passivation layer320. The color filter354may include a photosensitive organic material.

As illustrated inFIGS. 3 and 4, the capping layer391is on the color filter354. The capping layer391may help reduce and/or prevent infiltration of undesirable materials, generated in the color filter354, into the liquid crystal layer333. The capping layer391has a first hole, a second hole, and a third hole. In such an implementation, the first hole of the capping layer391is above the first hole of the color filter354, the second hole of the capping layer391is above the second hole of the color filter354, and the third hole of the capping layer391is above the third hole of the color filter354. The capping layer391may include, for example, silicon nitride or silicon oxide.

A first contact hole H1includes the first hole of the passivation layer320, the first hole of the color filter354, and the first hole of the capping layer391. A portion of the first source electrode SE1is exposed through the first contact hole H1. The holes of the first contact hole H1have larger size as positioned more upwardly. Accordingly, the first sub-pixel electrode PE1on an inner wall of the first contact hole H1may have a plurality of curved portions. Accordingly, the first sub-pixel electrode PE1may not be damaged in the first contact hole H1which has a large depth. For example, the first sub-pixel electrode PE1may be prevented from being cut.

A second contact hole H2includes the second hole of the passivation layer320, the second hole of the color filter354, and the second hole of the capping layer392. A portion of the second source electrode SE2is exposed through the second contact hole112. In this regard, the holes of the second contact hole H2may have larger size as positioned more upwardly. Accordingly, the second sub-pixel electrode PE2on an inner wall of second contact hole H2may have a plurality of curved portions. Accordingly, the second sub-pixel electrode PE2may not be damaged in the second contact hole H2which has a large depth. For example, the second sub-pixel electrode PE2may be prevented from being cut.

A third contact hole H3includes the hole of the gate insulating layer311, the third hole of the passivation layer330, the third hole of the color filter354, and the third hole of the capping layer393. A portion of the gate line GL is exposed through the third contact hole H3. In this regard, the holes of the third contact hole113may increase in size in an upward direction. Accordingly, the auxiliary gate electrode GE11on an inner wall of the third contact hole H3may have a plurality of curved portions. Accordingly, the auxiliary gate electrode GE11may not be damaged in the third contact hole H3which has a large depth. For example, the auxiliary gate electrode GE11may be prevented from being cut.

In the channel area CA2of the second switching element TFT2, a distance between the second semiconductor layer322and the auxiliary gate electrode GE11of the second switching element TFT2is longer than a distance between the second semiconductor layer322and the main gate electrode GE22thereof. To this end, the thickness of the insulating layer between the second semiconductor layer322and the auxiliary gate electrode GE11in the channel area CA2may be larger than the thickness of the insulating layer between the second semiconductor layer322and the main gate electrode GE22in the channel area CA2. For example, as illustrated inFIG. 4, a thickness T1of the insulating layer (first insulating layer) between the second semiconductor layer322and the auxiliary gate electrode GE11may correspond to a total thickness of a thickness of the passivation layer320, a thickness of the color filter354, and a thickness of the capping layer391.

A thickness T2of the insulating layer (second insulating layer) between the second semiconductor layer322and the main gate electrode GE22may correspond to a thickness of the gate insulating layer311. In this regard, the first insulating layer has a larger thickness than that of the second insulating layer (T1>T2).

In an implementation, when the color filter354is on the second substrate302, rather than on the first substrate301, the first insulating layer only includes the passivation layer320. In such an implementation, the passivation layer320may have a larger thickness than that of the gate insulating layer311.

A distance (hereinafter, a first distance) between the first gate electrode GE1of the first switching element TFT1and the first semiconductor layer321of the first switching element TFT1at the channel area CA1of the first switching element TFT1is defined as T0. A distance (hereinafter, a second distance) between the auxiliary gate electrode GE11of the second switching element TFT2and the second semiconductor layer322of the second switching element TFT2at the channel area CA2of the second switching element TFT2is defined as T1. The first distance T0is different from the second distance T1. For example, the second distance T1may be greater than the first distance T0.

As illustrated inFIG. 2, the first sub-pixel electrode PE1is in the first sub-pixel area P1. In such an implementation, the first sub-pixel electrode PE1is on the capping layer391. The first sub-pixel electrode PE1is connected to the first source electrode SE1through the first contact hole H1.

The first sub-pixel electrode PE1may include or be formed of, e.g., a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). For example, ITO may be a polycrystalline or monocrystalline material and IZO may also be a polycrystalline or monocrystalline material. In an implementation, IZO may be an amorphous material.

FIG. 5illustrates an embodiment of the first sub-pixel electrode PE1ofFIG. 2. The first sub-pixel electrode PE1may include a stem electrode613and a plurality of branch electrodes601a,601b,601c, and601d. The stem electrode613and the branch electrodes601a,601b,601c, and601dmay be formed to have a unitary construction.

The stem electrode613divides the first sub-pixel area P1into a plurality of domains. In an implementation, the stem electrode613includes a horizontal portion611and a vertical portion612intersecting each other. The horizontal portion611divides the first sub-pixel area P1into two domains. The vertical portion612divides each of the divided two domains into another two smaller domains. A pixel area P is divided into four domains A, B, C, and D by the stem electrode613including the horizontal portion611and the vertical portion612.

The branch electrodes601a,601b,601c, and601dinclude first, second, third, and fourth branch electrodes601a,601b,601c, and601d, each extending from the stem electrode613into directions different from one another. For example, the first, second, third, and fourth branch electrodes601a,601b,601c, and601dextend from the stem electrode613into respective ones of the domains A, B, C, and D. For example, the first branch electrode601ais in the first domain A, the second branch electrode601bis in the second domain B, the third branch electrode601cis in the third domain C, and the fourth branch electrode601dis in the fourth domain D.

The first branch electrode601aand the second branch electrode601bmay form a symmetrical shape with respect to the vertical portion612. The third branch electrode601cand the fourth branch electrode601dmay form a symmetrical shape with respect to the vertical portion612. In addition, the first branch electrode601aand the fourth branch electrode601dmay form a symmetrical shape with respect to the horizontal portion611. The second branch electrode601band the third branch electrode601cmay form a symmetrical shape with respect to the horizontal portion611.

The first branch electrode601amay include a plurality of first branch electrodes601ain the first domain A. In such an implementation, the plurality of first branch electrodes601aare aligned parallel to one another. In this regard, part of the first branch electrodes601aextend from a side of the horizontal portion611contacting the first domain A in a diagonal direction with respect to the side thereof. In addition, other or remaining ones of the first branch electrodes601aextend from a side of the vertical portion612contacting the first domain A in a diagonal direction with respect to the side thereof.

The second branch electrode601bmay include a plurality of second branch electrodes601bin the second domain B. In such an implementation, the plurality of second branch electrodes601bare aligned parallel to one another. In this regard, part of the second branch electrodes601bextend from a side of the horizontal portion611contacting the second domain B in a diagonal direction with respect to the side thereof. In addition, the rest of the second branch electrodes601bextend from a side of the vertical portion612contacting the second domain B in a diagonal direction with respect to the side thereof.

The third branch electrode601cmay include a plurality of third branch electrodes601cin the third domain C. In such an implementation, the plurality of third branch electrodes601care aligned parallel to one another. In this regard, part of the third branch electrodes601cextend from a side of the horizontal portion611contacting the third domain C in a diagonal direction with respect to the side thereof. In addition, other or remaining ones of the third branch electrodes601cextend from a side of the vertical portion612contacting the third domain C in a diagonal direction with respect to the side thereof.

The fourth branch electrode601dmay include a plurality of fourth branch electrodes601din the fourth domain D. In such an implementation, the plurality of fourth branch electrodes601dare aligned parallel to one another. In this regard, a part of the fourth branch electrodes601dextend from a side of the horizontal portion611contacting the fourth domain D in a diagonal direction with respect to the side thereof. Further, the rest of the fourth branch electrodes601dextend from a side of the vertical portion612contacting the fourth domain D in a diagonal direction with respect to the side thereof.

In an implementation, the aforementioned stem electrode613may further include a first connecting portion614aand a second connecting portion614b. The first connecting portion614ais connected to one end portion of the horizontal portion611. The second connecting portion614bis connected to another end portion of the horizontal portion611. The first connecting portion614aand the second connecting portion614bmay be aligned parallel to the vertical portion612. The first connecting portion614aand the second connecting portion614bmay have a unitary construction with the stem electrode613.

End portions of at least two of the first branch electrodes601ain the first domain A and end portions of at least two of the fourth branch electrodes601din the fourth domain D may be connected to one another by the second connecting portion614b. Similarly, end portions of at least two of the second branch electrodes601bin the second domain B and end portions of at least two of the third branch electrodes601cin the third domain C may be connected to one another by the first connecting portion614a.

In an implementation, end portions of at least two of the first branch electrodes601ain the first domain A and end portions of at least two of the second branch electrodes601bin the second domain B may be connected to one another by another connecting portion. Further, end portions of at least two of the third branch electrodes601cin the third domain C and end portions of at least two of the fourth branch electrodes601din the fourth domain D may be connected to one another by still another connecting portion.

The first sub-pixel electrode PE1and the first storage electrode751may overlap each other. In an implementation, an edge portion of the first sub-pixel electrode PE1may be on the first storage electrode751.

As illustrated inFIG. 4, the second sub-pixel electrode PE2is in the second sub-pixel area P2. In such an implementation, the second sub-pixel electrode PE2is on the capping layer391. The second sub-pixel electrode PE2is connected to the second source electrode SE2through the second contact hole CH2. The second sub-pixel electrode PE2may include or be formed of a same material as that in the first sub-pixel electrode PE1. For example, the second sub-pixel electrode PE2and the first sub-pixel electrode PE1may be simultaneously formed in a same process.

The second sub-pixel electrode PE2has substantially a same structure as that of the first sub-pixel electrode PE1. In an implementation, the second sub-pixel electrode PE2includes a stem electrode which divides the second sub-pixel area P2into a plurality of domains and a branch electrode extending from the stem electrode into each corresponding one of the domains. In addition, the second sub-pixel electrode PE2may further include a first connecting portion and a second connecting portion. The stem electrode, the branch electrode, the first connecting portion, and the second connecting portion in the second sub-pixel electrode PE2may be the same as those in the first sub-pixel electrode PE1.

The second sub-pixel electrode PE2may have a larger area than or equal area relative to that of the first sub-pixel electrode PE1. In an implementation, the area of the second sub-pixel electrode PE2may be one time to two times the area of the first sub-pixel electrode PE1.

The second sub-pixel electrode PE2and the second storage electrode752may overlap each other. In an implementation, an edge portion of the second sub-pixel electrode PE2may be on the second storage electrode752.

As illustrated inFIGS. 1 and 4, the auxiliary gate electrode GE11is on the capping layer391to overlap the second semiconductor layer322, the second drain electrode DE2, and the second source electrode SE2. The auxiliary gate electrode GE11and the gate line GL may be on different layers. The auxiliary gate electrode GE11is connected to the gate line GL through the third contact holes H3of the insulating layer (gate insulating layer311), the passivation layer320, the color filter354, and the capping layer391. The auxiliary gate electrode GE11may include substantially a same material as that included in the aforementioned first sub-pixel electrode PE1. The auxiliary gate electrode GE11and first sub-pixel electrode PE1may be simultaneously formed in a same process.

The second switching element TFT2is connected to the gate line GL through the auxiliary gate electrode GE11which has a relatively large resistance. For example, a material (e.g., a transparent conductive material such as IZO) in the gate line GL and the first gate electrode GE1has a greater resistance than that of a material (e.g., a metal material such as aluminum) in the auxiliary gate electrode GE11. Accordingly, the second switching element TFT has a greater inner resistance (e.g., a greater threshold voltage) than that of the first switching element TFT1including the first gate electrode GE1which has a unitary construction with the gate line GL. Accordingly, although a same gate signal is applied to the auxiliary gate electrode GE11of the second switching element TFT2and the first gate electrode GE1of the first switching element TFT1, a voltage drop by the second switching element TFT2may be larger than that by the first switching element TFT1. Accordingly, the first sub-pixel voltage and the second sub-pixel voltage may have different values from each other. For example, the second sub-pixel voltage is less than the first sub-pixel voltage. Accordingly, visibility of the pixel may be improved.

In an implementation, the auxiliary gate electrode GE11may include substantially a same material as that in the gate line GL.

As illustrated inFIGS. 3 and 4, the light blocking layer376is on the second substrate302. The light blocking layer376may be in a portion aside from the first and second sub-pixel areas P1and P2. In an implementation, the light blocking layer376may be on the first substrate301.

The overcoat layer722is on the light blocking layer376. In such an implementation, the overcoat layer722may be on an entire surface of the second substrate302including the light blocking layer376. The overcoat layer722may help significantly reduce (or minimize) a height difference among elements between the overcoat layer722and the second substrate302, e.g., among elements of the second substrate302such as the aforementioned light blocking layer376. In an implementation, the overcoat layer722may be omitted.

The common electrode330is on the overcoat layer722. In such an implementation, the common electrode330may be on an entire surface of the second substrate302including the overcoat layer722. In an alternative implementation, the common electrode330may be on portions of the overcoat layer722corresponding to the first sub-pixel area P1and the second sub-pixel area P2. The common voltage Vcom may be applied to the common electrode330. The common electrode330may include the aforementioned transparent conductive material (e.g., ITO or IZO).

An implementation of an LCD device may further include a first polarizer and a second polarizer. When a surface of the first substrate301and a surface of the second substrate302that face each other are defined as upper surfaces of the corresponding substrates, respectively, and surfaces opposite to the upper surfaces are defined as lower surfaces of the corresponding substrates, respectively, the aforementioned first polarizer is on the lower surface of the first substrate301and the second polarizer is on the lower surface of the second substrate302.

A transmission axis of the first polarizer is perpendicular to a transmission axis of the second polarizer. One of the transmission axes thereof is oriented parallel to the gate line GL. In an alternative implementation, the LCD device may only include one of the first polarizer or the second polarizer.

An implementation of an LCD device may further include a shielding electrode. The shielding electrode may be on the capping layer391to overlap the data line DL. For example, the shielding electrode may have substantially a same shape as that of the data line DL and may be disposed along the data line DL. The shielding electrode may include or be formed of a same material as in the first sub-pixel electrode PE1. The common voltage Vcom may be applied to the shielding electrode. The shielding electrode may help prevent formation of an electric field between the data line DL and the sub-pixel electrode, for example, the first and second sub-pixel electrodes. In such an implementation, the shielding electrode and the common electrode330have an equivalent electric potential, such that light transmitted through the liquid crystal layer between the shielding electrode and the common electrode330is shielded by the second polarizer. Accordingly, light leakage may be significantly reduced or prevented at a portion corresponding to the data line DL.

The first substrate301and the second substrate302may be insulating substrates that include or are formed of glass or plastic. The liquid crystal layer between the first substrate301and the second substrate302include liquid crystal molecules. The liquid crystal molecules may have, for example, negative dielectric constants and may be homeotropic liquid crystal molecules.

FIG. 6illustrates two adjacent pixels having the configuration ofFIG. 2.FIG. 6illustrates a portion of the first pixel and a portion of the second pixel. In an implementation, the first pixel and the second pixel have a same structure as that of the pixel illustrated inFIG. 2.

As illustrated inFIG. 6, the first storage electrode751in the first pixel PX1may be connected to the second storage electrode752in the second pixel PX2. For example, the first storage electrode751of the first pixel PX1and the second storage electrode752of the second pixel PX2may be connected to each other. The first pixel PX1and the second pixel PX2may be adjacent to each other between two adjacent ones GL and GL′ of the gate lines. In such an implementation, the first storage electrode751of the first pixel PX1and the second storage electrode752of the second pixel PX2may have a unitary construction.

FIG. 7illustrates a plan or layout view of another implementation of an LCD device including a pixel configuration corresponding to the pixel circuit ofFIG. 1. As illustrated inFIG. 7, the second drain electrode DE2may have a predetermined shape, e.g. a U-like shape. In such an implementation, a convex portion of the second drain electrode DE2faces the second sub-pixel electrode PE2. The second drain electrode DE2is between the storage line750and the gate line GL.

Descriptions pertaining to other configurations illustrated inFIG. 7will make reference to descriptions pertaining to configurations illustrated inFIGS. 3 and 4.

FIG. 8illustrates a plan or layout view of another implementation of an LCD device including a pixel configuration corresponding to the pixel circuit ofFIG. 1.FIG. 9illustrates a cross-sectional view taken along line I-I′ ofFIG. 8.FIG. 10illustrates a cross-sectional view taken along line II-II′ ofFIG. 8.

As illustrated inFIGS. 8, 9, and 10, the LCD device includes a first substrate3301, a gate line GL0, a first gate electrode GE101, a main gate electrode GE222, an auxiliary gate electrode GE111, a first storage electrode7751, a storage line7750, a second storage electrode7752, a gate insulating layer3311, a first semiconductor layer3321, a second semiconductor layer3322, a first ohmic contact layer3321a, a second ohmic contact layer3321b, a data line DL0, a first drain electrode DE11, a first source electrode SE11, a second drain electrode DE22, a second source electrode SE22, a passivation layer3320, a capping layer3391, a color filter3354, a first sub-pixel electrode PE11, a second sub-pixel electrode PE22, a second substrate3302, a light blocking layer3376, an overcoat layer7722, a common electrode3330, and a liquid crystal layer3333. In an implementation, at least one of the first ohmic contact layer3321a, the second ohmic contact layer3321b, or the overcoat layer7722may be omitted.

As illustrated inFIGS. 8 and 9, the first switching element TFT11includes the first gate electrode GE101, the first semiconductor layer3321, the first drain electrode DE11, and the first source electrode SE11. As illustrated inFIG. 9, the first drain electrode DE11, the first semiconductor layer3321, and the first source electrode SE11have a vertically stacked structure. For example, the first semiconductor layer3321is on the first drain electrode DE11, and the first source electrode SE11is on the first semiconductor layer3321.

The first ohmic contact layer3321amay also be between the first drain electrode DE11and the first semiconductor layer3321. The second ohmic contact layer3321bmay also be between the first semiconductor layer3321and the first source electrode SE11. In such an implementation, the first drain electrode DE11, the first ohmic contact layer3321a, the first semiconductor layer3321, the second ohmic contact layer3321b, and the first source electrode SE11have a vertically stacked structure.

The first gate electrode GE101of the first switching element TFT11is adjacent to the first semiconductor layer3321. For example, as illustrated inFIGS. 8 and 9, the first gate electrode GE101and the first semiconductor layer3321are horizontally adjacent to each other. For example, the first gate electrode GE101horizontally overlaps the first semiconductor layer3321. The first gate electrode GE101may further overlap at least one of the first drain electrode DE11, the first ohmic contact layer3321a, the second ohmic contact layer3321b, or the first source electrode SE11.

FIG. 9illustrates an example in which the first gate electrode GE101further overlaps the first drain electrode DE11, the first ohmic contact layer3321a, the first semiconductor layer3321, the second ohmic contact layer3321b, and the first source electrode SE11, horizontally. In an example illustrated inFIG. 9, a portion of the first gate electrode GE101is on a same layer as a layer on which the first drain electrode DE11is disposed. Another portion of the first gate electrode GE101is on a same layer as a layer on which the first ohmic contact layer3321ais disposed. Another portion of the first gate electrode GE101is on a same layer as a layer on which the first semiconductor layer3321is disposed. Another portion of the first gate electrode GE101is on a same layer as a layer on which the second semiconductor layer3321bis disposed. And, another portion of the first gate electrode GE101is on a same layer as a layer on which the first source electrode SE11is disposed.

As illustrated inFIGS. 8, 9, and 10, the second switching element TFT22includes the main gate electrode GE222, the auxiliary gate electrode GE111, the second semiconductor layer3322, the second drain electrode DE22, and the second source electrode SE22. As illustrated inFIG. 9, the second drain electrode DE22, the second semiconductor layer3322, and the second source electrode SE22have a vertically stacked structure. For example, the second semiconductor layer3322is on the second drain electrode DE22, and the second source electrode SE22is on the second semiconductor layer3322.

A third ohmic contact layer3322amay also be between the second drain electrode DE22and the second semiconductor layer3322. A fourth ohmic contact layer3322bmay also be between the second semiconductor layer3322and the second source electrode SE22. In such an implementation, the second drain electrode DE22, the third ohmic contact layer3322a, the second semiconductor layer3322, the fourth ohmic contact layer3322b, and the second source electrode SE22have a vertically stacked structure.

The main gate electrode GE222of the second switching element TFT22is adjacent to the second semiconductor layer3322. For example, as illustrated inFIGS. 8and10, the main gate electrode GE222and the second semiconductor layer3322are horizontally adjacent to each other. For example, the main gate electrode GE222horizontally overlaps the second semiconductor layer3322. The main gate electrode GE222may also overlap at least one of the second drain electrode DE22, the first ohmic contact layer3321a, the second ohmic contact layer3321b, or the second source electrode SE22horizontally.

FIG. 10illustrates an example in which the main gate electrode GE222horizontally overlaps the second drain electrode DE22, the first ohmic contact layer3321a, the second semiconductor layer3322, the second ohmic contact layer3321b, and the second source electrode SE22. In the example illustrated inFIG. 10, a portion of the main gate electrode GE222is on a same layer as a layer on which the second drain electrode DE22is disposed. Another portion of the man gate electrode GE222is on a same layer as a layer on which the first ohmic contact layer3321ais disposed. Another portion of the main gate electrode GE222is on a same layer as a layer on which the second semiconductor layer3322is disposed. Another portion of the main gate electrode GE222is on a same layer as a layer on which the second ohmic contact layer3321bis disposed. Another portion of the main gate electrode GE222is on a same layer as a layer on which the second source electrode SE22is disposed.

The auxiliary gate electrode GE111of the second switching element TFT22is adjacent to the second semiconductor layer3322. For example, as illustrated inFIGS. 8 and 10, the auxiliary gate electrode GE111and the second semiconductor layer3322are horizontally adjacent to each other. For example, the auxiliary gate electrode GE111horizontally overlaps the second semiconductor layer3322. The auxiliary gate electrode GE111may also overlap at least one of the second drain electrode DE22, the first ohmic contact layer3321a, the second ohmic contact layer3321b, and the second source electrode SE22horizontally.

FIG. 10illustrates an example in which the auxiliary gate electrode GE111horizontally overlaps the second drain electrode DE22, the first ohmic contact layer3321a, the second semiconductor layer3322, the second ohmic contact layer3321b, and the second source electrode SE22. In the example illustrated inFIG. 10, a portion of the auxiliary gate electrode GE111is on a same layer as a layer on which the second drain electrode DE22is disposed. Another portion of the auxiliary gate electrode GE111is on a same layer as a layer on which the first ohmic contact layer3321ais disposed. Another portion of the auxiliary gate electrode GE111is on a same layer as a layer on which the second semiconductor layer3322is disposed. Another portion of the auxiliary gate electrode GE111is on a same layer as a layer on which the second ohmic contact layer3321bis disposed. Another portion of the auxiliary gate electrode GE111is on a same layer as a layer on which the second source electrode SE22is disposed.

The main gate electrode GE222does not physically contact any conductor including the gate line GL0. In an alternative implementation, the main gate electrode GE222may be connected to the aforementioned bias line.

In a channel area CA22of the second switching element TFT22, the distance between the second semiconductor layer3322and the auxiliary gate electrode GE111of the second switching element TFT22may correspond to a first distance W1and the distance between the second semiconductor layer3322and the main gate electrode GE222thereof may correspond to a second distance W2. The first distance W1is longer than the second distance W2. Accordingly, when receiving a gate high voltage through the auxiliary gate electrode GE111, rather than through the main gate electrode GE222, the second switching element TFT22exhibits relatively lower current driving capability. As illustrated inFIGS. 8 and 10, since connected to the gate line GL0through the auxiliary gate electrode GE11, the second switching element TFT2has relatively lower current driving capability.

A distance (hereinafter, a first distance) between the first gate electrode GE101of the first switching element TFT1and the first semiconductor layer3321of the first switching element TFT1at the channel area CA11of the first switching element TFT1is defined as W0. A distance (hereinafter, a second distance) between the auxiliary gate electrode GE111of the second switching element TFT2and the second semiconductor layer3322of the second switching element TFT2at the channel area CA22of the second switching element TFT2is defined as W1. The first distance W0is different from the second distance W1. For example, the second distance W1may be greater than the first distance W0.

As illustrated inFIGS. 9 and 10, the data line DL0, the first drain electrode DE11, and the second drain electrode DE22are on the first substrate3301. The data line DL0, the first drain electrode DE11, and the second drain electrode DE22respectively include same materials as materials in the aforementioned exemplary embodiment of the data line DL, the first drain electrode DE1, and the second drain electrode DE2, respectively.

As illustrated inFIGS. 9 and 10, the first ohmic contact layer3321ais on the data line DL0, the first drain electrode DE11, and the second drain electrode DE22. The first ohmic contact layer3321aon the data line DL0, the first ohmic contact layer3321aon the first drain electrode DE11, and the first ohmic contact layer3321aon the second drain electrode DE22are connected to one another. The first ohmic contact layer3321amay include substantially a same material as that in the aforementioned implementation of the first ohmic contact layer321a.

As illustrated inFIGS. 9 and 10, a semiconductor layer3420is on the first ohmic contact layer3321a. The data line DL0, the first ohmic contact layer3321a, and the first semiconductor layer3321may have substantially the same shape.

The semiconductor layer3420includes the first semiconductor layer3321and the second semiconductor layer3322. For example, the first semiconductor layer3321and the second semiconductor layer3322are portions of the semiconductor layer3420. For example, a portion of the semiconductor layer3420between the first drain electrode DE11and the first source electrode SE11may correspond to the first semiconductor layer3321. In addition, a portion of the semiconductor layer3420between the second drain electrode DE22and the second source electrode SE22may correspond to the aforementioned second semiconductor layer3322. The semiconductor layer3420including the first semiconductor layer3321and the second semiconductor layer3322may include substantially a same material as in the aforementioned implementation of the first semiconductor layer321.

As illustrated inFIGS. 9 and 10, the second ohmic contact layer3321bis on the first semiconductor layer3321and the second semiconductor layer3322. For example, the second ohmic contact layer3321bdoes not overlap the data line DL0. Accordingly, the second ohmic contact layer3321bon the first semiconductor layer3321and the second ohmic contact layer3321bon the second semiconductor layer3322are physically separated from each other. The second ohmic contact layer3321bmay include substantially a same material as in the aforementioned implementation of the second ohmic contact layer321b.

The first source electrode SE11and the second source electrode SE22are on the second ohmic contact layer3321b. For example, the first source electrode SE11is on the second ohmic contact layer3321bto overlap the first semiconductor layer3321. The second source electrode SE22is on the second ohmic contact layer3321bto overlap the second semiconductor layer3322. The first source electrode SE11and the second source electrode SE22are physically separated from each other. The first source electrode SE11and the second source electrode SE22may respectively include same materials as in the aforementioned implementation of the first source electrode SE1and the second source electrode SE2, respectively.

As illustrated inFIGS. 9 and 10, the gate insulating layer3311is on the first substrate3301, the semiconductor layer3420, the first source electrode SE11, and the second source electrode SE22. The gate insulating layer3311is over an entire surface of the first substrate3301including the semiconductor layer3420, the first source electrode SE11, and the second source electrode SE22. The gate insulating layer3311has first, second, third, fourth, and fifth holes. In such an implementation, the first hole of the gate insulating layer3311is on the first source electrode SE11, the second hole of the gate insulating layer3311is on the second source electrode SE22, and third, fourth, and fifth holes are on the first substrate3301. The gate insulating layer3311may include substantially a same material as in the aforementioned gate insulating layer311.

The gate line GL1, the first storage electrode7751, the second storage electrode7752, and the storage line7750are on the gate insulating layer3311. Respective shapes of the gate line GL1, the first storage electrode7751, the second storage electrode7752, and the storage line7750may be the same as in the aforementioned implementation of the gate line GL, the first storage electrode751, the second storage electrode752, and the storage line750. The gate line GL1, the first storage electrode7751, the second storage electrode7752, and the storage line7750may respectively include the same materials as in the aforementioned implementation of the gate line GL, the first storage electrode751, the second storage electrode752, and the storage line750, respectively.

As illustrated inFIGS. 9 and 10, the first gate electrode GE101, the main gate electrode GE222, and the auxiliary gate electrode GE111perpendicularly extend from the gate line GL0toward the first substrate3301. The first gate electrode GE101is in the third hole of the gate insulating layer3311, the main gate electrode GE222in the fourth hole of the gate insulating layer3311, and the auxiliary gate electrode GE111in the fifth hole of the gate insulating layer3311. The first gate electrode GE101may fill the entirety of the third hole. The main gate electrode GE222may fill the entirety of the fourth hole. The auxiliary gate electrode GE111may fill the entirety of the fifth hole. The first gate electrode GE101, the main gate electrode GE222, and the auxiliary gate electrode GE111may respectively include same materials as those in the aforementioned implementation of the first gate electrode GE1, the main gate electrode GE22, and the auxiliary gate electrode GE11, respectively.

In the channel area CA22of the second switching element, the width W1of the gate insulating layer3311between the second semiconductor layer3322and the auxiliary gate electrode GE11is larger than the width W2of the gate insulating layer3311between the second semiconductor layer3322and the main gate electrode GE222.

The passivation layer3320is on the gate insulating layer3311, the gate line GL0, the first storage electrode7751, the second storage electrode7752, the storage line7750, the first gate electrode GE101, the main gate electrode GE222, and the auxiliary gate electrode GE111. The passivation layer3320is over the entire surface of the first substrate3301including the gate insulating layer3311, the gate line GL0, the first storage electrode7751, the second storage electrode7752, the storage line7750, the first gate electrode GE101, the main gate electrode GE222, and the auxiliary gate electrode GE111. The passivation layer3320has a first hole and a second hole. In such an implementation, the first hole of the passivation layer3320is above the first hole of the gate insulating layer3311. The second hole of the passivation layer3320is above the second hole of the gate insulating layer3311. The passivation layer3320may include substantially a same material as in the aforementioned implementation of the passivation layer320.

As illustrated inFIGS. 9 and 10, the color filter3354is on the passivation layer3320. The color filter3354is in a first sub-pixel area P11and a second sub-pixel area P22. In such an implementation, an edge portion of the color filter3354is on the data line DL0. An edge portion of one of the color filters3354may overlap an edge portion of another of the color filters3354adjacent thereto. Color filters3354having a same color are respectively disposed in the first sub-pixel area P11and the second sub-pixel area P22in a single pixel. The color filter3354has a first hole and a second hole. In such an implementation, the first hole of the color filter3354is above the first hole of the passivation layer3320. The second hole of the color filter3354is above the second hole of the passivation layer3320. The color filter3354may include substantially a same material as in the color filter354.

As illustrated inFIGS. 9 and 10, the capping layer3391is on the color filter3354and helps reduce or prevent infiltration of impurities, generated from the color filter3354, into the liquid crystal layer3333. The capping layer3391has a first hole and a second hole. In such an implementation, the first hole of the capping layer3391is above the first hole of the color filter3354. The second hole of the capping layer3391is above the second hole of the color filter3354. The capping layer3391may include substantially a same material as in the aforementioned implementation of the capping layer391.

A first contact hole H11includes the first hole of the passivation layer3320, the first hole of the color filter3354, and the first hole of the capping layer3391. A portion of the first source electrode SE11is exposed through the first contact hole H11. As previously described, the sizes of the holes of the first contact hole H11increase in an upward direction.

A second contact hole H22includes the second hole of the passivation layer3320, the second hole of the color filter3354, and the second hole of the capping layer3391. A portion of the second source electrode SE22is exposed through the second contact hole H22. As previously described, the size of the holes of the second contact hole H22increase in an upward direction.

The distance W1between the channel area CA22and the auxiliary gate electrode GE111of the second switching element TFT22may be longer than the distance W2between the channel area CA22and the main gate electrode GE22thereof. To this end, the gate insulating layer3311between the channel area CA22and the auxiliary gate electrode GE111may have a larger width than that of the gate insulating layer3311between the channel area CA22and the main gate electrode GE222.

As illustrated inFIG. 9, the first sub-pixel electrode PE11is in the first sub-pixel area P11. In such an implementation, the first sub-pixel electrode PE11is on the capping layer3391. The first sub-pixel electrode PE11is connected to the first source electrode SE11through the first contact hole H11. The first sub-pixel electrode PE1may be substantially the same as the aforementioned implementation of the first sub-pixel electrode PE1.

As illustrated inFIG. 10, the second sub-pixel electrode PE22is in the second sub-pixel area P22. In such an implementation, the second sub-pixel electrode PE22is on the capping layer3392. The second sub-pixel electrode PE22is connected to the second source electrode SE22through the second contact hole H22. The second sub-pixel electrode PE22may be substantially the same as the aforementioned implementation of the second sub-pixel electrode PE2.

In an alternative implementation of the light blocking layer3376, the overcoat layer7722, the common electrode3330, and the liquid crystal layer3333may be substantially the same as the aforementioned implementation of the light blocking layer376, the overcoat layer722, the common electrode330, and the liquid crystal layer333.

In an alternative implementation of the LCD device may further include the aforementioned shielding electrode.

As illustrated inFIGS. 11A and 11B, a first metal layer481, a first impurity semiconductor material layer490a, a semiconductor material layer440, a second impurity semiconductor material layer490b, and a second metal layer482are sequentially deposited over an entire surface of a first substrate3301.

The first metal layer481and the second metal layer482may be deposited in a physical vapor deposition (PVD) method, e.g., sputtering. The first impurity semiconductor material layer490a, the semiconductor material layer440, and the second impurity semiconductor material layer490bmay be deposited in a chemical vapor deposition (CVD) method.

The first metal layer481and the second metal layer482may include substantially a same material as in the aforementioned data line DL0, the first and second impurity semiconductor material layers490aand490bmay include substantially a same material as in the first ohmic contact layer3321a, and the semiconductor material layer440may include substantially a same material as in the first semiconductor layer3321.

Subsequently, a photoresist PR is coated over an entire surface of the first substrate3301including the first metal layer481, the first impurity semiconductor material layer490a, the semiconductor material layer440, the second impurity semiconductor material layer490b, and the second metal layer482.

Subsequently, a mask M is disposed on the photoresist PR. The mask M includes a transmissive area TA which transmits light, a blocking area BA which blocks light, and a half-transmissive area HTA which partially transmits light. The half-transmissive area HTA may include a plurality of slits or a semi-transparent layer. In such an implementation, the transmittance of the half-transmissive area HTA is higher than that of the light blocking area BA and lower than that of the transmissive area TA.

Subsequently, light (e.g., ultraviolet light) is selectively irradiated to the photoresist PR through the mask M such that the photoresist PR is exposed. When the exposed photoresist PR is developed, a first photoresist pattern PP1and a second photoresist pattern PP2, having different thicknesses from each other, are formed on the second metal layer482as inFIGS. 12A and 12B.

The first photoresist pattern PP1is on the second metal layer482, corresponding to the light blocking area BA of the mask M, and the second photoresist pattern PP2is on the second metal layer482, corresponding to the half-transmissive area HTA of the mask M. In an implementation, a portion of the photoresist PR corresponding to the transmissive area TA of the mask M is completely removed. The thickness of the second photoresist pattern PP2may be less than the thickness of first photoresist pattern PP 1.

Subsequently, when the first and second photoresist patterns PP1and PP2are used as a mask, the second metal layer482, the second impurity semiconductor material layer490b, the semiconductor material layer440, the first impurity semiconductor material layer490a, and the first metal layer481are sequentially etched. In such an implementation, as illustrated inFIGS. 13A and 13B, a data line DL0, a first drain electrode DE11, and a second drain electrode DE22are formed on the first substrate3301. In addition, a first ohmic contact layer3321ais formed on the data line DL0, the first drain electrode DE11, and the second drain electrode DE22. In addition, a semiconductor layer3420including first and second semiconductor layers3321and3322is formed on the first ohmic contact layer3321a. In addition, an impurity semiconductor pattern590is formed on the semiconductor layer3420, and a source metal layer582is formed on the impurity semiconductor pattern590.

The first and second metal layers481and482may be removed in a wet-etching method using an etching solution. The first impurity semiconductor material layer490a, the semiconductor material layer440, and the second impurity semiconductor material layer490bmay be removed in a dry-etching method using an etching gas.

Subsequently, an ashing process is performed, for example, as illustrated inFIGS. 14A and 14B. In the ashing process, the first photoresist pattern PP1and the second photoresist pattern PP2are ashed by substantially the same extent. In such an implementation, the ashing process is performed until the second photoresist pattern PP2having a relatively small thickness is removed. For example, when the second photoresist pattern PP2is removed, the ashing process ends.

As the second photoresist pattern PP2is removed, the source metal layer582therebelow is exposed. In an implementation, a portion of the first photoresist pattern PP1is removed through the ashing process. Accordingly, the thickness of the first photoresist pattern PP1is reduced. The ashed first photoresist pattern PP1may be defined as a residual pattern PP1′.

Subsequently, when the residual pattern PP1′ is used as a mask, the source metal layer582and the impurity semiconductor pattern590therebelow are sequentially patterned through an etching process such that a second ohmic contact layer3321b, a first source electrode SE11, and a second source electrode SE22are formed as inFIGS. 15A and 15B.

In an implementation, in the etching process performed on the aforementioned impurity semiconductor pattern590, a portion of the semiconductor layer3420below the impurity semiconductor pattern590is removed.

Subsequently, as illustrated inFIGS. 16A and 16B, the residual pattern PP1′ is removed. The residual pattern PP1′ may be removed using a strip solution, which, for example, may include ethylene carbonate.

Subsequently, as illustrated inFIGS. 17A and 17B, a gate insulating layer3311is deposited on the first substrate3301, the semiconductor layer3420, the first source electrode SE11, and the second source electrode SE22. The gate insulating layer3311is deposited over the entire surface of the first substrate3301including the semiconductor layer3420, the first source electrode SE11, and the second source electrode SE22.

The gate insulating layer3311may be deposited in a chemical vapor deposition (CVD) method. The gate insulating layer3311may include a material in the aforementioned gate insulating layer311.

Subsequently, as illustrated inFIGS. 18A and 18B, a third hole913, a fourth hole914, and a fifth hole915are defined in the gate insulating layer3311. A surface of the first substrate3301is exposed through the third hole913, the fourth hole914, and the fifth hole915.

Subsequently, a gate metal layer may be deposited over the entire surface of the first substrate3301including the gate insulating layer3311. The gate metal layer may be deposited in a physical vapor deposition (PVD) method such as sputtering.

Subsequently, the gate metal layer is patterned through a photolithography process and an etching process such that a first gate electrode GE101, a main gate electrode GE222, and an auxiliary gate electrode GE111are respectively formed in the third hole913, the fourth hole914, and the fifth hole915, respectively, as illustrated inFIGS. 19A and 19B. In addition, a gate line GL0, a first storage electrode7751, a second storage electrode7752, and a storage line7750are formed on the gate insulating layer3311.

Subsequently, as illustrated inFIGS. 20A and 20B, a passivation layer3320is deposited over the entire surface of the first substrate3301including the gate line GL0, the first storage electrode7751, the second storage electrode7752, the storage line7750, the main gate electrode GE222, and the gate insulating layer3311.

The passivation layer3320may include substantially a same material as that in the passivation layer3320.

Subsequently, a photosensitive organic material is formed over the entire surface of the first substrate3301including the passivation layer3320.

Subsequently, the photosensitive organic material is patterned through a photolithography process such that a color filter3354is formed in a first sub-pixel area P11and a second sub-pixel area P22as illustrated inFIGS. 21A and 21B. The color filter3354has a first hole931and a second hole932. A portion of the passivation layer3320is exposed through the first hole931and the second hole932of the color filter3354.

Subsequently, as illustrated inFIGS. 22A and 22B, a capping layer3391is deposited over the entire surface of the first substrate3301including the color filter3354. The capping layer3391may include substantially a same material as in the capping layer3391.

Subsequently, the capping layer3391and the passivation layer3320are selectively removed through a photolithography process and an etching process such that a first hole941and a second hole942are defined in the capping layer3391, a first hole921and a second hole922are defined in the passivation layer3320, and a first hole911and a second hole912are defined in the gate insulating layer3311, as illustrated inFIGS. 23A and 23B.

A first contact hole H11includes the first hole911of the gate insulating layer3311, the first hole921of the passivation layer3320, the first hole931of the color filter3354, and the first hole941of the capping layer3391. A portion of the first source electrode SE11is exposed through the first contact hole H11.

A second contact hole H22includes the second hole912of the gate insulating layer3311, the second hole922of the passivation layer3320, the second hole932of the color filter3354, and the second hole942of the capping layer3391. A portion of the second source electrode SE22is exposed through the second contact hole H22.

Subsequently, a transparent metal layer is deposited over the entire surface of the first substrate3301including the capping layer3391, the first source electrode SE11, and the second source electrode SE22. The transparent metal layer may include substantially a same material as in the first sub-pixel electrode PE1.

Subsequently, the transparent metal layer is patterned by a photolithography process and an etching process, such that a first sub-pixel electrode PE11connected to the first source electrode SE11through the first contact hole H11is formed in the first sub-pixel area P11and a second sub-pixel electrode PE22connected to the second source electrode SE22through the second contact hole H22is formed in the second sub-pixel area P22.

FIG. 25illustrates an equivalent circuit diagram of a pixel provided in an alternative implementation of an LCD device. As illustrated inFIG. 25, a first switching element TFT1may further include an auxiliary gate electrode GE2, and the auxiliary gate electrode GE2may be connected to a gate line GL. Other features inFIG. 25may be substantially the same as configurations illustrated inFIG. 1.

FIGS. 26A and 26Billustrate an effect of an implementation of an LCD device.

As illustrated inFIG. 26A, when a gate signal maintains a gate high voltage, a first switching element TFT1and a second switching element TFT2are turned on. In such an implementation, a first sub-pixel voltage Vpx1and a second sub-pixel voltage Vpx2are generated by a data voltage Vdata from a data line DL to a pixel.

A first reference voltage Vref1refers to a voltage which may be applied to a first sub-pixel electrode PE1based on the data voltage Vdata, and a second reference voltage Vref2refers to a voltage which needs to be applied to a second sub-pixel electrode PE2based on the data voltage Vdata.

As illustrated inFIG. 26, the first sub-pixel voltage Vpx1is higher than the first reference voltage Vref1. The second sub-pixel voltage Vpx2is higher than the second reference voltage Vref2. As such, the first switching element TFT1and the second switching element TFT2of an implementation of an LCD device may stably divide the data voltage to apply the divided voltages to the first sub-pixel electrode PE1and the second sub-pixel voltage PE2. In addition, as the first and second sub-pixel voltages Vpx1and Vpx2are higher than the first and second reference voltages Vref1and Vref2, respectively, a charging ratio of a pixel may be improved.

As illustrated inFIG. 26B, a kick-back voltage (2.4 [V]) to the second sub-pixel voltage Vpx2is lower than a kick-back voltage (2.7 [V]) to the second reference voltage Vref2. Accordingly, one or more embodiments described herein may significantly reduce image sticking and flickering.

FIGS. 27A and 27billustrate another embodiment of an LCD device. As illustrated inFIG. 27A, both of an image981having a middle gray level and an image982having a highest gray level may be displayed on a display screen925of an LCD device. The image981having a middle gray level refers to an image having a middle brightness. The image982having a highest gray level refers to an image having a highest brightness, e.g., an image having a white gray level.

A reference mark “V1” inFIG. 27Bdenotes a storage voltage (a first storage voltage or a second storage voltage) of an implementation of an LCD device. A reference mark “V2” denotes a storage voltage of a conventional LCD device.

In one type of LCD device which has been proposed, a storage electrode is directly connected to a data line. Accordingly, a storage voltage varies by a large extent based on a polarity of a data voltage applied to a pixel. For example, as illustrated in FIG.27B, a voltage drop (IR drop) of about 200 [mV] occurs in a storage voltage. Accordingly, in the case that the image981having a middle gray level and the image982having a highest gray level are displayed together as illustrated inFIG. 27A, pixels in an area “{circle around (a)}” right next to an area in which the image982having a highest gray level is displayed displays an image that has a gray level close to a white gray level rather than the middle gray level. Thus, the pixels in area {circle around (a)} display an incorrect image. Accordingly, the brightness of an image displayed in area {circle around (a)} differs from the brightness of an image displayed in area {circle around (b)}. Thus, horizontal crosstalk may occur.

However, in accordance with one or more embodiments descried herein, even when a first switching element TFT1and a second switching element TFT2are turned on, a data line DL and a storage electrode (a first storage electrode and a second storage electrode) are not directly connected to one another. For example, a first storage capacitor Cst1is between the data line DL and the first storage electrode751, and a second storage capacitor Cst2is between the data line DL and the second storage electrode752. Accordingly, even though the polarity of the data voltage applied to a pixel is changed, variation of a storage voltage (a first storage voltage and a second storage voltage) may be significantly reduced. Accordingly, horizontal crosstalk may be suppressed.

In accordance with one or more of the aforementioned embodiments, an LCD device and a method of manufacturing the LCD device may provide the following effects. First, a data voltage may be divided by a first switching element and a second switching element that have different current driving capabilities. Accordingly, a first sub-pixel electrode and a second sub-pixel electrode may have different pixel voltages such that visibility of a pixel may be improved.

Second, a gate electrode of the first switching element and a gate electrode of the second switching element may include different resistive materials, respectively. In such an implementation, the first sub-pixel electrode and the second sub-pixel electrode may have different pixel voltages. Accordingly, visibility of the pixel may be improved.

Third, one pixel may generate two different sub-pixel voltages using two switching elements. Accordingly, an aperture ratio of the pixel may increase.

Fourth, a data line and a storage electrode are not directly connected. In such an implementation, variation of a first storage voltage and a second storage voltage may be significantly reduced. Accordingly, the occurrence of horizontal crosstalk may be significantly suppressed.

Fifth, a drain electrode, a first ohmic contact layer, a semiconductor layer, a second ohmic contact layer, and a source electrode are vertically stacked. Thus, a horizontal occupying area of a switching element including the drain electrode, the first ohmic contact layer, the semiconductor layer, the second ohmic contact layer, and the source electrode may be reduced. Accordingly, an aperture ratio of the pixel may further be improved.