A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.

BACKGROUND

Description of the Related Art

A processing system typically employs random access memory (RAM) to store data used for processing operations. The memory has a plurality of entries (e.g., rows or lines), whereby each entry includes a set of bitcells to store the individual bits of the entry. In response to a read access request, the processing system can read data from an entry using a read operation having two phases: a precharge phase and an evaluate phase. During the precharge phase, the memory applies a charge to bitlines of the memory bitcells to a defined voltage representing an asserted logic level (e.g., a logic value of “1”). During the evaluate phase, the memory stops precharging the bitcells of the entry to be read, so that the bitlines connected to the bitcells are each set to a voltage level representing the data stored at their corresponding bit cell. However, current spikes during precharging can consume a relatively large amount of power and negatively impact the power efficiency of the processing system.

DETAILED DESCRIPTION OF EMBODIMENTS

FIGS. 1-4illustrate techniques for reducing current spikes at a processing system by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. However, precharging all of the bitlines simultaneously results in a large current spike and a subsequent drop in the local power grid voltage. As wire resistance increases and decoupling capacitance per area decreases, large current spikes become more difficult to ameliorate. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines. A current measurement module analyzes a current spike associated with precharging each subset of bitlines, and the precharge control unit modulates delays between precharge signals applied to each subset of bitlines based on the current measurement module analysis, so that the current spikes remain below a threshold and so that overlap between the current spikes is minimized.

FIG. 1illustrates a block diagram of a processing system100in accordance with some embodiments. In some embodiments, the processing system100is a part of one of a desktop computer, laptop, server, computing-enabled phone, game console, set-top box, or any other device that employs a processor to execute sets of instructions. In particular, the processing system100includes one or more processor cores (not shown) that together execute sets of instructions (e.g., computer programs) in order to carry out operations defined by the instruction sets. To facilitate completion of the operations, the processing system100includes memory devices, including the illustrated cache110, that store data to be used by the executing sets of instructions.

In the course of executing particular instructions, referred to as memory access instructions, the processing system100generates memory access operations to store or retrieve data from the memory devices. For example, in response to executing a read instruction, the processing system100generates a read operation to retrieve data from the memory devices. In response to executing a write instruction, the processing system100generates a write operation to store data at the memory devices. The read and write operations generated by the processing system100are collectively referred to as “memory access operations.”

Each memory access operation targets a particular location associated with the memory devices, wherein the location is identified by a memory address. In some embodiments, a memory address is associated with entries at different memory devices that store the same data. For example, in some embodiments the memory devices are arranged in a memory hierarchy, wherein the cache110is located at the highest level of the memory hierarchy and other memory devices (e.g., one or more lower level caches, system random access memory (RAM), disk drives, and the like) are located at lower levels of the memory hierarchy. A given memory address identifies an entry at each level of the memory hierarchy that stores data corresponding to the memory address.

The processing system100includes a cache controller105configured to decode address information for read operations. For each read operation, the cache controller105receives the corresponding base address and offset and performs an addition of these memory address components to identify a memory address. The cache controller105decodes the memory address to identify the particular one of the entries151-158that is the read entry. In some embodiments, the cache controller105identifies the memory address by generating two or more values, referred to herein as “memory address components”. For example, in some embodiments the memory address components identified by the cache controller105include a base address value and an offset value, wherein the memory address for the memory access operation is the sum of the base address value and the offset value. As described further herein, in response to a memory access operation, the cache controller105combines the memory address components to identify the memory address. This combining of the memory address components and generating the signaling that identifies a particular memory entry is referred to herein as “decoding” the memory address. For example, if the memory address components are a base address value and an offset value, the cache controller105decodes the memory address by adding the base address value and the offset value.

The cache110includes multiple entries, also referred to as cache lines, such as entries151-158. Each of the entries151-158includes a set of bitcells connected to corresponding bitlines and a corresponding wordline. For example, entry158includes bitcells160-162connected to wordline165. Bitcell160is connected to differential bitlines170and171, bitcell161is connected to differential bitlines172and173, and bitcell162is connected to differential bitlines174and175. To facilitate access to the entries151-158, the cache110includes a precharge control module120and a line select module112. For a read operation, the cache110implements two phases: a precharge phase and an evaluate phase.

During the precharge phase, a wake signal to the precharge control module120begins the precharge process of the bitlines for a set of entries including the entry corresponding to the decoded memory address of the read operation (i.e., to bitlines of an affected region). The precharge control module120allows the bitlines of the affected region to begin precharging at least one cycle earlier than when the bitlines of the affected region will be accessed. The precharge control module120then asserts control signaling PCH_1121to precharge a first subset of the bitlines for the entries151-158. After a first delay after the assertion of control signaling PCH_1, the precharge control module120asserts control signaling PCH_2122to precharge a second subset of the bitlines for the entries151-158. The precharge control module120continues asserting control signaling with delays for each subset of bitlines of the affected region through the assertion of control signaling PCH_N123to precharge an Nth subset of the bitlines for the entries151-158. Each of the N assertions of control signaling brings the corresponding subset of bitlines to a defined voltage.

During the evaluate phase, the precharge control module120sends control signaling to discontinue precharging at the bitlines for the set of entries including the entry corresponding to the decoded memory address of the read operation. In addition, the line select module112identifies the entry corresponding to the decoded memory address and asserts a signal at the wordline for the identified entry. In response, the bitlines of the identified entry are each set to states corresponding to the data stored at the corresponding bit line. For example, if the bitcell160stores an asserted logic value (e.g., a logic value of “1”) the bitline170remains at the precharged level while the bitline171is pulled to a voltage representing a negated logic value. Read combine logic and latch180logically combines the bitlines of different ones of the entries151-158to identify the values stored at each of the bitcells in the read entry, and latches the resulting read data for subsequent access by the processor.

In some embodiments, the bitcells of a precharge subset share corresponding bitlines. For example, in some embodiments a precharge subset includes entries156,157, and158. Accordingly, in this example, bitlines170and171are connected to bitcell160for entry158, another bitcell (not shown) for entry157, and still another bitcell (not shown) for entry156. Similarly, bitlines172and173are connected to bitcell161for entry158, another bitcell (not shown) for entry157, and still another bitcell (not shown) for entry156. Thus, each bitline of the precharge subset is connected to a corresponding bitcell for each of the entries156-158. Each of the entries156-158is connected to a different wordline, allowing the entries to be read individually.

To facilitate limiting the magnitude of a current spike associated with precharging the bitlines, the precharge control120groups entries151-158into multiple subsets, or regions. For example, in some embodiments, entries151-153are in one precharge subset, entries154-156are in a different precharge subset, and entries157and158are in still another precharge subset. In some embodiments, the entries151-158of the cache110are divided into banks, and each bank includes a plurality of columns of entries. In some embodiments, a first subset includes alternating columns of entries of a bank (e.g., odd-numbered columns), and a second subset includes the remaining columns of entries of the bank (e.g., even-numbered columns). In some embodiments, each subset includes a single column, such that the number of subsets equals the number of columns. Grouping the entries into different precharge subsets allows the precharge control120to apply a different precharge control signal to each of the plurality of precharge subsets. The different precharge control signals PCH_1121, PCH_2122, through PCH_N123, each initiate precharging of the respective precharge subsets as a different time, such that the current spikes from precharging each subset of bitlines are maintained below a threshold.

In operation, the precharge control module120receives a wake signal from the cache controller105to allow the bitlines of the affected region to begin precharging at least one cycle earlier than when the bitlines of the affected region will be accessed. The precharge control module120then asserts control signaling PCH_1121to precharge a first subset of the bitlines for the entries151-158. After a first delay after the assertion of control signaling PCH_1, the precharge control module120asserts control signaling PCH_2122to precharge a second subset of the bitlines for the entries151-158. The precharge control module120continues asserting control signaling with delays for each subset of bitlines of the affected region through the assertion of control signaling PCH_N123to precharge an Nth subset of the bitlines for the entries151-158. Each of the N assertions of control signaling brings the corresponding subset of bitlines to a defined voltage. By dividing the bitlines of the affected region into N subsets and applying separate precharge control signaling to each subset with a delay between the application of each precharge control signaling to each subset, the precharge control module120reduces the magnitudes of the current spikes resulting from precharging.

FIG. 2illustrates a block diagram of the precharge control module120of the cache110of the processing system100ofFIG. 1in accordance with some embodiments. The cache110includes the precharge control module120and a plurality of bitlines divided into regions, or banks,1-N (e.g., bitline bank1213, bitline bank2214, through bitline bank N216). The cache110receives a clock signal CLK from a clock generator205.

The clock generator205is a module configured to generate the CLK signal based on a timing signal (not shown) that is phase locked to a stable oscillating signal provided by a clock source (not shown), such as a reference crystal. In some embodiments, the clock generator205generates the CLK signal by selectively combining multiple clock signals based on control signaling that establishes the clock frequency for the CLK signal.

The precharge control module120is configured to receive a wake signal220from the cache controller105(not shown) in response to which the precharge control module120asserts a series of precharge control signaling for each subset of bitlines for a set of entries including the entry corresponding to the decoded memory address of the read operation. The wake signal220allows the bitlines of the affected region to begin precharging a cycle earlier than when the bitlines of the affected region will be accessed. The precharge control module120includes a timer235and, in the example illustrated inFIG. 2, the precharge control module120further includes a current measurement module230. The current measurement module230includes a current spike analyzer232and a threshold234. The current spike analyzer232is configured to analyze simulations and/or data indicating a magnitude and duration of current spikes resulting from precharging each of bitline bank1213, bitline bank2214, through bitline bank N216. The current measurement module230compares the magnitudes and durations of the current spikes to the threshold234. If the magnitudes and/or durations of the current spikes exceed the threshold234, the current measurement module230provides a current status flag233to the timer235indicating that one or more of the current spikes exceeds the threshold234. In some embodiments, the current measurement module230is incorporated in a circuit simulator (not shown) that analyzes simulations of current spikes on the basis of which the timer235controls precharge control signaling.

The timer235is configured to control the timing of assertion of precharge control signaling PCH_1to bitline bank1213, assertion of PCH_2to bitline bank2214, through assertion of PCH_N to bitline bank N216. The timer235asserts precharge control signaling PCH_1at a first time. After a first delay, the timer235asserts precharge control signaling PCH_2at a second time. After a second delay, the timer235asserts the next precharge control signaling to the next bitline bank, until, after an N−1th delay, the timer235asserts precharge control signaling PCH_N. If the timer235receives a current status flag233indicating that that the current (e.g., due to one or more current spikes resulting from precharging) exceeds the threshold234, the timer235adjusts one or more of the delays between the precharge control signals until the current measurement module230ceases providing the current status flag233. In this way, the timer235stages precharging of the bitline banks1-N213-216so that the current spikes remain below the threshold234.

FIG. 3is a diagram illustrating an example of the precharge control module120applying staged clock signals for precharging subsets, or regions, of bitlines of the cache110ofFIG. 2in accordance with some embodiments.FIG. 3illustrates waveforms302,304,306,308,310, and312, corresponding to examples of the CLK, PCH_1, PCH_2, PCH_N−1, PCH_N, and WL signals, respectively. At a time T1320, the CLK signal302from the clock generator205is high, coinciding with a wake signal (not shown). During clock phase315, while the CLK signal302is still high, at a time T2325, delayed from time T1320, the timer235of the precharge control module120ofFIG. 2asserts precharge control signaling PCH_1304to the bitlines of bitline bank1213. At a time T3330, delayed from time T2325, and during clock phase316, while the CLK signal302is low, the timer235asserts precharge control signaling PCH_2306to the bitlines of bitline bank2214. At a time T4335, delayed from time T3330, and during clock phase317, while the CLK signal302is high, the timer235asserts precharge control signaling PCH_N−1308to the bitlines of bitline bank N−1 (not shown inFIG. 2). At a time T5340, delayed from time T4335, and during clock phase318, while the CLK signal302is low, the timer235asserts precharge control signaling PCH_N310to the bitlines of bitline bank N216.

At time T6345, at the rising edge of clock phase319of the CLK signal302, after all of the bitline banks1-N213-216have been precharged, the precharge control module120sends control signaling to discontinue precharging at the bitlines for the set of entries including the entry corresponding to the decoded memory address of the read operation. In addition, the line select module112ofFIG. 1identifies the entry corresponding to the decoded memory address and asserts a signal WL312at the wordline for the identified entry.

FIG. 4is a flow diagram illustrating a method400of staging precharging of subsets of bitlines in accordance with some embodiments. The method400is implemented in some embodiments of the precharge control module120shown inFIG. 2. At step402, the current measurement module230models current spikes for precharging bitlines, based on analysis of simulations and/or measured data, to determine if any current spikes exceed the threshold234. At step404, the precharge control module120allocates bitlines to subsets, or regions. At step406, the cache controller105receives address components for a read operation. At step408, the cache controller105asserts a wake signal220to the precharge control module120for bitlines corresponding to the address components. At step410, the precharge control module120asserts staged precharge control signaling to each subset of bitlines for bitlines corresponding to the address components. At step412, during the evaluate phase, the precharge control module120disables precharging for bitlines corresponding to address components. The method flow then continues back to step406for the next read operation.