Superjunction trench device and method

Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52-9) interleaved first (70-1, 70-2, 70-3, 70-4, etc.) and second (74-1, 74-2, 74-3, etc.) spaced-apart regions of first (70) and second (74) semiconductor materials of different conductivity type and different mobilities so that, in a first embodiment, the second semiconductor material (74) has a higher mobility for the same carrier type than the first semiconductor material (70), and providing (52-14) an overlying third semiconductor material (82) in which a trench (90, 91) is formed with sidewalls (913) having thereon a fourth semiconductor material (87) that has a higher mobility than the third material (82), adapted to carry current (50) between source regions (86), through the fourth (87) semiconductor material in the trench (91) and the second semiconductor material (74) in the device drift space (42) to the drain (56). In a further embodiment, the first (70) and third (82) semiconductor materials are relaxed materials and the second (74) and fourth (87) semiconductor materials are strained semiconductor materials.

TECHNICAL FIELD

The present invention generally relates to semiconductor structures, and more particularly relates to trench-type semiconductor structures incorporating a superjunction.

BACKGROUND

Superjunction structures are well known in the art and are described, for example, by Fujihira, “Theory of Semiconductor Superjunction Devices,”Jpn J. Appl. Phys., Vol., 36 (1997), pp. 6254-6262; Fujihira and Miyasaka, “Simulated Superior Performance of Semiconductor Superjunction Devices,”Proc. of1998Symposium on Power Semiconductor Devices&ICs, Kyoto, Japan, pp. 423-426; Strollo and Napoli, “Optimal ON-Resistance Versus Breakdown Voltage Tradeoff in Superjunction Power Devices. A Novel Analytical Model,”IEEE Transactions on Electron Devices, Vo. 48, No. 9, September 2001, pp. 2161-2167; and Gerald Deboy, “The Superjunction Principle as Enabling Technology for Advanced Power Solutions”,IEEE ISIE2005, Jun. 20-23, 2005, Dubrovnik, Croatia, pages 469-472. In its simplest form, superjunction structures employ a number of alternatively arranged P and N doped semiconductor layers or regions, with the condition that the doping of these layers are charge-balanced, or Na*Wa=Nd*Wd, in which Na and Nd are the doping concentrations of the P and N layers, and Wa, Wd, the widths of these same layers. Current flow through such superjunction structures is for the most part parallel to the planes of the P-N junctions. Superjunction structures are often employed in high voltage (and high power) semiconductor (SC) devices in order to obtain comparatively high breakdown voltages while minimizing series ON-resistance. The superjunction structures facilitate this desirable combination of properties. Superjunction devices are also available on the open market, as for example, the CoolMOS™ family of devices produced by Infineon of Villach, Austria.

While the structure illustrated inFIG. 1is useful, it is desirable to improve its properties. Accordingly, there is a need for improved device structures and methods of fabrication that can provide improved performance. It is desirable to provide trench and superjunction type semiconductor devices that offer, for example, improved carrier mobility while still being able to be fabricated using conventional processing equipment and process chemistry. Further it is desirable to provide an improved device structure and method of fabrication that is useful with a variety of semiconductor materials. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

DETAILED DESCRIPTION

For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawings figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in some of the figures may be exaggerated relative to other elements or regions of the same or other figures to help improve understanding of embodiments of the invention.

The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of use in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms “left,” right,” “in,” “out,” “front,” “back,” “up,” “down, “top,” “bottom,” “over,” “under,” “above,” “below” and the like in the description and the claims, if any, are used for describing relative positions and not necessarily for describing permanent positions in space. It is to be understood that the embodiments of the invention described herein may be used, for example, in other orientations than those illustrated or otherwise described herein. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner.

For convenience of explanation and not intended to be limiting, the present invention is described for superjunction structures formed using Si and Ge as exemplary semiconductor materials, but the present invention is not limited merely to this combination of materials. The principles taught herein apply to a wide variety of semiconductor materials of different lattice constants and/or band gaps that can be combined to produce regions of improved mobility in the active regions of the devices. Non-limiting examples of other suitable semiconductor material combinations are GaN and Si, SiGe and GaAs, GaAs and Ge, Si and Si1-yCy, SiC and AlN, SiC and BP, InGaN and GaN, and various other type IV, III-V and II-VI compounds and mixtures thereof and organic semiconductors. Accordingly, while Si and Ge are identified as a suitable pair of semiconductor materials to obtain the improved properties described herein, the present invention is not limited thereto.

FIG. 2is a simplified schematic perspective view of trench-type semiconductor device40employing superjunction structure41in drift space42, according to an embodiment of the present invention. For convenience of explanation an N-channel trench-type metal-oxide-semiconductor (Trench-MOS) semiconductor device is described. Device40employs superjunction structure41in drift space42between trench-type channels45and substrate drain56. Device40comprises N+ substrate (e.g., drain)56, of for example, silicon, on which has been formed transition or buffer layer58of varying composition, as is described in detail in connection withFIG. 3. Superjunction structure41comprises multiple parallel vertically arranged P-type regions70and N-type regions74with intervening PN junctions76. Lower portion44of superjunction structure41contacts buffer layer58which in turn contacts substrate56, which together with electrical contact561forms the drain of Trench-MOS device40. Superjunction structure41of device40ofFIG. 2differs from superjunction structure21of device20ofFIG. 1in that P-type regions70and N-type regions74are made from different materials, chosen so that the mobility of the principal current carriers in drift space42through superjunction41is higher than what would otherwise be obtained using a homogenous material (with different doping for the N and P regions) for superjunction structure41. In a preferred embodiment for constructing an N-channel device, P-type regions70are formed from relaxed SiGe and N-type regions74are formed from strained Si, as is described for example in connection withFIGS. 3-10. Strained Si has an electron mobility that is about twice that of ordinary relaxed silicon as is typically found in prior art superjunction structure21. Since the RDSON for such devices is inversely proportional to the electron mobility in drift space42, doubling the principal carrier mobility in device42will significantly lower the device RDSON, which is highly advantageous.

Region82located substantially above superjunction structure41comprises N-region83in contact with upper portion43of superjunction structure41and P-type body region84extending from N-region83to upper surface88of device40. Trench91extends from upper surface88through body region84and through N-region83to upper portion43of superjunction structure41. In an alternative embodiment, trench91extends from upper surface88through body region84alone, making contact with N-region83. Sidewalls89of trench91are formed from higher mobility material87compared to the material of body region84. For example and not intended to be limiting, body region84is conveniently formed of relaxed SiGe and material87is conveniently of strained silicon. In this way, channels45of device40preferentially form in higher mobility material87, and the device ON-resistance is further reduced compared to prior art device20. Trench91is lined with gate dielectric (e.g., SiO2)46analogous to gate dielectric36ofFIG. 1. The interior portion of trench91within gate dielectric46is filled with gate (e.g., doped poly-silicon)48having gate contact481. N+ source regions86with source contact861are formed in P-type body region84on either side of trench91, in much the same manner as for source regions34ofFIG. 1, insulated from gate48by gate dielectric46. When appropriately biased, source-drain current50(abbreviated as “ID”) flows from source contact861and source regions86through substantially vertical channels45in higher mobility material87on trench sidewalls89of P-type body region84into drift space42formed by N-type regions74of superjunction structure41to drain region56and drain contact561. Long dimension49of trench91, gate48, source regions86and body contact regions85is substantially perpendicular to the planes of parallel N and P regions70,74and intervening PN-junctions76of superjunction structure41. Body contact regions85are conveniently but not essentially coupled to source regions86and source contact861. The structure illustrated inFIG. 2will be understood more fully in connection withFIGS. 3-18following.

FIGS. 3-17are simplified schematic cross-sectional views of a trench-type semiconductor device employing a superjunction structure, according to further embodiments of the present invention, at different stages of manufacture52-3through52-17. Manufacturing stages52-3through52-10shown respectively inFIGS. 3-10illustrate embodiments useful for formation of superjunction structure41in drift space42of device40ofFIG. 2, and are views looking substantially in direction410inFIG. 2. Manufacturing stages52-11through52-17ofFIGS. 11-17illustrate further embodiments useful for formation of trench portion82of device40ofFIG. 2in combination with superjunction structure41, and are views looking substantially in direction411ifFIG. 2. In a preferred embodiment, directions410and411are substantially orthogonal but this is not essential. However, for convenience of explanation, it is assumed hereafter that directions410and411are substantially orthogonal but this not is intended to be limiting.

Referring now toFIG. 3illustrating manufacturing stage52-3, structure54-3ofFIG. 3comprises substrate56conveniently about 0.05 to 0.5 mm thickness with upper surface57on which is formed buffer layer58having upper surface59. The choice between N or P doping of substrate56and buffer layer58will depend upon the particular type of device that is being fabricated. For example, in the case of an N-channel Trench-MOS device, such as is shown by way of example herein, substrate56is desirably N+. For an insulated gate bipolar transistor (IGBT) type of device, substrate56is desirably P+. For a P-channel Trench-MOS device, substrate56is desirably P+. Persons of skill in the art will understand how to choose the doping type of substrate56according to the type of device they wish to fabricate and use of N+ for substrate56herein by way of example is not intended to be limiting. Buffer layer58is conveniently, for example, either N or P-type according to the conductivity type of substrate56and preferably of graded SiGe with thickness55of about 1 to 5 micrometers. For convenience of explanation, it is assumed in connection withFIGS. 3-18that layer58and substrate56are both N-type as would be used in forming an N-channel Trench-MOS device, but this is not essential. Chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), and molecular beam epitaxy (MBE) are well known methods useful for forming layer58. LPCVD is preferred. The purpose of buffer layer58is to provide a transition zone from semiconductor (SC) substrate56of a suitable substrate material, e.g., silicon, having a first lattice constant, to further semiconductor (SC) materials having different lattice constants that are applied in subsequent steps so as to provide the desired regions of improved mobility. In the case of Si and SiGe mixtures, when substrate56is silicon, layer58is desirably graded from substantially pure Si at surface57(e.g., 100% Si) to a X % Si to Y % Ge mixture at surface59, where the ratio X:Y at surface59is usefully in the range of about 60:40 to 95:05, more conveniently about 70:30 to 90:10 and preferably about 80:20.

In FIG,4showing manufacturing stage52-4and resulting structure54-4, substantially uniform refractory mask layer60having thickness61is applied on surface59. Thickness61can be used to determine the (vertical) extent of superjunction structure41in the direction of conduction of source-drain current50(seeFIG. 2). Thickness61in the range of about 2 to 50 micrometers is useful, with the exact range being dependent upon the targeted breakdown voltage. Persons of skill in the art will understand how to choose the thickness range that best suits their particular design targets. Silicon dioxide is a non-limiting example of a suitable material for mask layer60, but other generally refractory inert materials can also be used. Non-limiting examples, of other useful materials for mask layer60are low temperature silicon oxide (LTO), oxide formed by plasma enhanced reaction of tetra-ethyl-ortho-silicate (PETEOS), silicon nitride, combinations thereof, etc. Etch mask62of, for example, photo-resist, is applied over layer60and patterned to provide protected areas62-1,62-2,62-3etc., of widths63-1,63-2,63-3, etc., (collectively widths63) separated by openings64-1,64-2,64-3,64-4, etc., (collectively openings64) of widths65-1,65-2, etc., (collectively widths65). Protected areas of etch mask62of widths63and openings64of widths65will determine the thicknesses (widths) of the parallel, oppositely-doped layers of eventual superjunction structure41.

Referring now toFIG. 6showing manufacturing stage52-6and resulting structure54-6, first semiconductor material70is epitaxially grown or deposited on exposed regions59-1,59-2,59-3,59-4, etc., of surface59of transition layer58desirably but not essentially to thickness71equal or greater than thickness61of layer60. Chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), and atmospheric pressure chemical vapor deposition (APCVD), are well known methods useful for forming material70. LPCVD is preferred. Relaxed SiGe is a non-limiting example of a suitable material for first semiconductor material70for use in connection with an N-channel device. Semiconductor material70is formed on surface59of transition layer58. In the case of SiGe, material70is desirably a mixture of X % Si to Y % Ge, wherein X:Y is usefully in the range of about 60:40 to 95:05, more conveniently about 70:30 to 90:10 and preferably about 80:20, corresponding substantially to the composition mixture at surface59of buffer layer58. Assuming by way of example, that substrate56is single crystal silicon with surface57having, for example, [100] orientation, then layer58is desirably graded in composition from substantially 100% Si at surface57to the desired SiGe composition ratio of layer70at surface59. This insures that when SiGe material70of substantially the same composition is grown on surface regions59-1,59-2,59-3,59-4, etc., of surface59, that the resulting SiGe regions70-1,70-2,70-3,70-4, etc., will be substantially strain free, i.e., “relaxed.” It is desirable to dope SC material70during deposition according to the desired device functions. In the example presented inFIGS. 6-11, SC material70is desirably P-doped to concentrations usefully about 1E15 to 1E19, depending on the targeted breakdown voltage. In manufacturing stage52-7ofFIG. 7, structure54-6ofFIG. 6is planarized so that excess portion70′ if any of region70lying above upper surface67of mask60is removed. Chemical-mechanical polishing (CMP) is a well known suitable technique. Structure54-7shown inFIG. 7results. Persons of skill in the art will understand that it is not essential that thickness71exceed thickness61of mask layer60, since even if thickness71is less than thickness61, structure54-7may be obtained during planarizing step52-7by removing any excess material of mask layer60.

In manufacturing stage52-8shown inFIG. 8, structure54-7ofFIG. 7is etched to substantially remove remaining portions60-1,60-2,60-3, etc., of mask layer60, thereby exposing previously protected regions59-5,59-6,59-7, etc., of surface59of transition layer58in spaces (i.e., trenches)66-1,66-2,66-3, etc., (collectively trenches66). Selective etching that removes remaining portions of mask60without significantly attacking material70is preferred. Structure54-8with trenches66results. In manufacturing stage52-9ofFIG. 9, second semiconductor (SC) material74is deposited in trenches66, thereby forming SC regions74-1,74-2,74-3, etc., lying between SC regions70-1,70-2,70-3,70-4, etc. Layer74is desirably epitaxially grown on exposed regions59-5,59-6,59-7, etc., of surface59of transition layer58, desirably but not essentially to thickness75equal or greater than thickness61of layer60. Chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), and atmospheric pressure chemical vapor deposition (APCVD) are well known methods useful for forming material74. LPCVD is preferred. In manufacturing stage52-10ofFIG. 10, structure54-9is desirably planarized in generally the same manner as described in connection withFIG. 7. Structure54-10results.

Non-relaxed (e.g., “strained”) silicon is a non-limiting example of a suitable SC material for second SC material74in combination with first (e.g., “relaxed”) semiconductor (e.g., SiGe) material70, but this is not intended to be limiting. What is convenient is that SC material74be strained relative to SC material70, for example as a consequence of having a different lattice constant because of its different composition. Thus, SC materials70and74should be sufficiently different in composition and/or crystal structure so that regions74-1,74-2,74-3, etc., are strained with respect to regions70-1,70-2,70-3,70-4, etc. Assuming that material70is P-type, then material74should be N-type or vice-versa, that is, whatever the doping of first SC material70, second SC material74should be of opposite conductivity type in order to provide improved superjunction structure41comprising interleaved regions70,74ofFIG. 10. For convenience of description regions70-1,70-2,70-3,70-4, etc., are labeled as P-type inFIGS. 6-11and regions74-1,74-2,74-3, etc., are labeled as N-type, but this is not intended to be limiting, and the illustrated doping types may be interchanged. Further, while the terms “first” SC material and “second” SC material are used herein in connection with materials70and74respectively, this is merely for purposes of identifying different materials or regions and does not imply that they must be applied in any particular order. Persons of skill in the art will understand based on the teachings herein that materials70and74and resulting interleaved regions70-1,70-2,70-3,70-4, etc., and74-1,74-2,74-3, etc., of superjunction structure41may be formed in either order. By adjusting the composition of materials70,74relative to surface59of transition layer58, either material may be arranged to be relaxed or strained and either may be P or N type. Similarly, layer58may be P or N type or intrinsic, depending upon the type of device desired to be formed.

Stated another way, those portions of superjunction structure41that are intended to be the primary current carrying portions of drift space42of device40should be formed from a material having higher mobility than would be obtained from an otherwise homogeneous superjunction structure (e.g., all the same semiconductor material merely with different doping in the N and P regions). This is conveniently accomplished according to the above-described embodiment of the present invention by providing strained semiconductor material in the current carrying drift space regions, e.g., regions74for an N-channel device, taking advantage of the increase in mobility obtainable with strained semiconductor material. For example, an improvement in electron mobility of a factor of about two can be obtained by using strained Si in N-type regions74of superjunction structure41of an N-channel Trench-MOS device relative to the unstrained SiGe of P-type regions70of superjunction structure41associated with the N-type Trench-MOS device. Stated still another way, the present inventions provides a trench-type semiconductor device including superjunction structure41of improved properties by using materials of different composition for the N and P regions of superjunction structure41so that the primary current carrying material (either N or P) in drift space42has higher mobility than what would otherwise be obtained using a homogeneous but differentially doped semiconductor material. Strained materials usually exhibit increased mobility for one type of carrier and decreased mobility for the opposite type of carrier depending upon whether they are in tension or compression. As explained in connection with the foregoing examples, the material combinations leading to tension or compression should be arranged so that the mobility increase for electrons occurs in the N-type drift regions of the superjunction structure for N-type devices and the mobility increase for holes occurs in the P type drift regions of the superjunction structure for P-type devices. While use of strained semiconductor to obtain the mobility increase is convenient, such mobility increase can also be obtained by using other higher mobility materials in the primary current carrying drift space of the superjunction structure. Thus, for N-channel devices, the higher mobility material should be used for the N-type regions of the superjunction structure and for P-channel devices, the higher mobility material should be used for the P-type regions of the superjunction structure. Thus, strained or unstrained material may be used provided that the carrier mobility is increased in the superjunction drift space portions where principal current conduction occurs.

Manufacturing stages52-11through52-17ofFIGS. 11-17illustrate further embodiments useful for formation of trench portion82of device40ofFIG. 2in combination with superjunction structure41, and are views looking substantially in direction411inFIGS. 2 and 10.FIGS. 11-18are simplified schematic cross-sectional views of Trench-MOS semiconductor structures54-11through54-17at different stages52-11through52-17of manufacture, according to such further embodiments of the present invention. For convenience of explanation,FIGS. 11-17illustrate an N-channel device but this is merely by way of example and not intended to be limiting. Persons of skill in the art will understand that by interchanging the various dopant types, P-channel devices can also be made according to still further embodiments of the present invention. Other types of devices, such as for example and not intended to be limiting, IGBT devices can also be fabricated using the principals taught herein. Referring now to manufacturing stage52-11ofFIG. 11, structure54-11comprises structure54-10ofFIG. 10having upper surface412on which is formed pillar-shaped epi-growth mask80. Epi-growth mask pillar80with upper surface801, thickness802and width803is conveniently formed on upper surface412of superjunction structure41. Silicon dioxide is a non-limiting example of a convenient material for epi-growth mask pillar80, but other generally refractory materials adapted to withstand subsequent process steps may also be used. SiN, LTO, and TEOS are non-limiting examples of other suitable materials. Accordingly, use of the word “oxide” in connection with epi-growth mask pillar80is merely for convenience of identification and not intended to be limiting and should be understood to include such other alternatives. Pillar80is conveniently but not essentially formed by depositing a layer of oxide, masking the portion where pillar80is desired and etching away the remainder of the oxide layer. Chemical vapor deposition (CVD) or low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) are examples of suitable techniques for forming epi-growth mask pillar80, but other formation techniques are not precluded. LPCVD is preferred. It is desirable to use an anisotropic etch process that preferentially etches substantially perpendicular to surface412rather than isotropically so as to leave pillar80of substantially uniform width803and height802on surface412. It is also desirable to etch epi-growth mask pillar80selectively so as to leave underlying semiconductor surface412substantially unaffected. Structure54-11results.

Referring now to manufacturing stage52-12ofFIG. 12, trench portion82of relaxed semiconductor is deposited on surface412of superjunction structure41, to thickness821desirably exceeding thickness or height802. Portion82is conveniently formed of the same material as region70. Portion82may be N or P type depending upon the particular device structure that is desired. Such doping does not significantly affect the lattice constant and band gap. Portion82desirably comprises initial (e.g., phosphorous doped) N-region83of about 0.05-0.15 micrometers thickness, preferably about 0.1 micrometers thickness, and doping densities usefully of about 5E15 to 1E17 per cm3, depending on the desired breakdown voltage, followed by (e.g., boron doped) P-type body region84of sufficient thickness so that thickness821equals or exceeds thickness802. Region84has doping densities usefully of about 1E17 to 1E18 per cm3and preferably about 2E17 to 5E17 per cm3but lower and higher doping density can also be used depending upon the particular device characteristics that are desired for the body formation. Portion82may be in-situ doped during formation or doped after formation using conventional doping techniques. Either arrangement is useful, depending upon the type of device being formed and whether graded or uniform doping is desired. Persons of skill in the art will understand how to choose appropriate doping densities and profiles for portion82depending upon the particular type of device they intend to fabricate. It is desirable that body region84is the same material as the drift region70to ensure that there is no crystal dislocation between the drift and the body region that would create electrical leakage. Selective epitaxial deposition is a preferred means of forming portion82. Selective epitaxial deposition is conveniently performed by LPCVD, RPCVD or APCVD using di-chlorosilane or tri-chorosilane. UHV-CVD can also be used. Selectivity is improved by use of GeH4gas mixtures. Some epitaxial lateral overgrowth (ELO) can occur when thickness821of portion82exceeds pillar height802. Structure54-12results.

Depending upon the planarity obtained for upper surface821of the material of trench portion82, trench portion82may be used as-is following deposition or it may be grown to a thickness greater than thickness802and lapped back to thickness823, as shown in manufacturing stage52-13, so that region84has a thickness841and upper surface842substantially coplanar with surface801of epi-mask pillar80. Alternatively, if trench portion82is not as thick as thickness802, pillar80may be lapped so that surfaces842and801(after lap) are substantially coplanar. Either arrangement is useful. Persons of skill in the art will be able to determine without undue experimentation whether such a lap-back step is needed. Chemical-mechanical polishing (CMP) is an example of a well known suitable planarization technique. Other techniques can also be used. Epi-growth mask pillar80is then removed, e.g., by selective etching, thereby creating cavity or trench90. Structure54-13results. Since pillar80is of, for example, silicon oxide, it may be selectively etched without affecting adjacent semiconductor regions83,84. Thus, amorphization of the interior walls of trench90is avoided.

In manufacturing stage52-14, the semiconductor material of adjacent regions83,84surrounding trench90is desirably but not essentially slightly etched to round the corners of trench90so as to avoid high electric field concentrations at any sharp corners that may be left from the removal of pillar80and that might degrade the sustaining voltage of the finished device. As a consequence, modified trench91of width910slightly greater than width803of pillar80and depth911slightly greater than height802of pillar80is obtained, as shown in structure54-14ofFIG. 14. Persons of skill in the art will understand how to perform such etching in order to produce the amount of corner rounding that they desire for their particular device application. Wet etching is a suitable technique for such corner rounding wherein the etchant depends upon the particular semiconductor materials being used. For the exemplary SiGe materials described herein, buffered hydrofluoric acid, hydrogen peroxide and acetic acid, is a suitable etchant mixture. As a consequence of the corner rounding etch, bottom portion912of trench91generally extends slightly below interface412between regions or layer83and superjunction structure41. Higher mobility material87is then deposited so as to line the interior walls of trench91, at least on sides913. Structure54-14results.

As noted earlier, strained silicon is suitable for material87in connection with SiGe mixtures for body region84. Material87is conveniently deposited in trench91to thickness871, at least on sides913. It may also be deposited on bottom surface912of trench91and on outer surface842of layer or region84of structure54-13but this is not essential. It is arranged that material87be strained by using a material of different composition and therefore different lattice constant than the material of region84. If provided, the portions of material87on surface842can be later removed, but this is not essential. Thickness871is usefully in the range of about 30 to 100 nanometers with about 50 nanometers being preferred. Material87may be intrinsic, in which case it will tend to take up the doping type of the material on which it is deposited, or it may be doped during or after formation. Doping of material87in trench91is especially convenient for controlling the threshold voltage and determining whether the resulting device is an enhancement or depletion mode device. Vapor phase epitaxy or molecular beam epitaxy are examples of suitable deposition techniques for strained semiconductor material87. LPCVD is preferred. Silicon (doped or undoped) is a non-limiting example of a suitable semiconductor (SC) for material87that will be strained relative to the relaxed SiGe semiconductor material of body region84. Material87may be N or P type depending upon the type of finished device that is desired. For an N-channel Trench-MOS device, material87is preferably N-type with a doping density usefully in the range of about 1E16 per cm3, more conveniently of a similar value as the drift region70that depends on the breakdown voltage targeted by the application. Structure54-14results. While material87is described as a strained material, this is merely a way of obtaining higher mobility material than that of body region84where body region84is of a relaxed material. Material87may be any material that provides a higher mobility than what would ordinarily be encountered in a channel induced in body region84. Thus, use of a strained semiconductor for material87is convenient but not essential provided that material87has a higher mobility than the material of body region84for the type of carriers than will flow in channels45(e.g., seeFIG. 2).

Manufacturing stage52-15ofFIG. 15,52-16of FIG.16and52-17ofFIG. 17illustrates how structure54-14ofFIG. 14may be used to form N-channel Trench-MOS device40ofFIG. 2having improved properties compared to device20ofFIG. 1. Exemplary material87lining trench91is identified as “N(s)” meaning that material87in trench91is desirably formed of a material (e.g., Si) that becomes strained when epitaxially deposited on the relaxed material (e.g., SiGe) of regions83,84. It is the lattice mismatch between regions83,84and material87that creates the strain in material87during epitaxial growth in trench91. P(r) regions84act as P-body regions analogous to P-body regions32ofFIG. 1extending from surface842into N(r) regions83. P+ body contacts85are conveniently formed extending from surface842into P(r) region84to reduce contact resistance to P-body regions84and N+ source regions86analogous to regions34ofFIG. 1are formed extending from surface842into P(r) region84and contacting higher mobility (e.g., strained) material87. Gate dielectric46analogous to gate dielectric36ofFIG. 1is conveniently formed on the portions of N(s) layer78on sides913and bottom912of trench91. Channel regions45analogous to channel regions23ofFIG. 1are located in the portions of material87between source regions86and N-type regions83. Gate48is formed on gate dielectric46in proximity to channel regions45in trench91, analogous to gate38ofFIG. 1. Ion implantation is a non-limiting example of a suitable technique for forming regions85,86with a dose of about 1E15 to 4E15 per square centimeter being suitable for body contact regions85, and about 2E15 to 5E15 per centimeter square being suitable for source regions86, but lower and higher doping may also be used. Thermally grown or deposited silicon oxide of about 200 to 600 Angstrom Units thickness is conveniently used for gate dielectric46. Doped polycrystalline silicon is suitable for gate48, but other conductors can also be used. Gate contact98(seeFIG. 17) of for example AlSiCu is provided on gate48. Source-body contact95of for example AlSiCu is provided in electrical communication with source region86and body contact region85. Drain contact96is provided on substrate56. Source, drain and gate connections861,481and561are provided in electrical communication with source, gate and drain contacts95,98, and96respectively.

What is different between device40(also device structure54-17) and device20is the presence of higher mobility (e.g., strained) semiconductor material87in channels regions45and relaxed semiconductor materials83,84on which strained material87is formed, and, the presence of higher mobility (e.g., strained) semiconductor material regions74in contact with relaxed semiconductor material70in superjunction structure41in drift space42of device40. When device40is appropriately biased, current50flows from sources86through channels45in higher mobility (e.g., strained) material87and through the higher mobility (e.g., strained) material of regions74of carrier drift space and through transition or buffer layer58to substrate56which acts as the drain of improved Trench-MOS device40. RDSON comprises the combined resistances of the various device regions through which currents50ofFIG. 2flow, analogous to currents30ofFIG. 1. Because the carrier mobility of channel regions45in material87in trench91and in drift space regions74of superjunction structure41is higher than the carrier mobility in comparable regions of prior art device20, RDSON is reduced. For the same device geometry, e.g., gate area, gate dielectric thickness, etc., Qgd is substantially the same, but the figure of merit (FOM)=RDSON*Qgd is improved. The FOM can be further improved by including thicker dielectric region47in the bottom of trench91, thereby further decoupling gate48from superjunction structure41and drain56. This provides additional improvement in the FOM by further reducing Qgd. Region47may also be made of a material with a lower permittivity than gate dielectric46, thus, still further reducing Qgd. Other things being equal, the lower the figure of merit the faster the device can operate.

Structure54-14shown inFIG. 14is preferably obtained through the manufacturing sequence illustrated in manufacturing stages52-11through52-14. This has the advantage that an anisotropic semiconductor etch is not required and the risk of amorphization of the trench surfaces where higher mobility material87is intended to be deposited and wherein the device channels will form is avoided. Further, the depth of trench90may be more carefully controlled since it is determined by thickness or height802of pillar80, which provides a convenient etch and/or lap stop in conjunction with any back-lap steps. This is in contrast to merely etching trench90where etch depth is usually determined merely by etch time, a less precise means of control of trench depth. However, trench90may also be formed in other ways. For example, structure54-13illustrated inFIG. 13can be formed without epi-growth mask pillar80, that is, layers83,84merely deposited or grown on surface412without involving epi growth mask pillar80. Then trench90is etched into surface842of layers83,84, thereby yielding structure54-13ofFIG. 13. From that point on, manufacturing stages52-14through52-17are performed as previously described. As previously noted, such process is prone to undesirable amorphization of the trench sidewalls during RIE of trench90. However, if the RIE damaged side-wall material is removed using the relatively gentle isotropic etch step to obtain structure54-14depicted in manufacturing stage52-14, higher mobility (e.g., strained) semiconductor material87can be deposited on a fresh surface unaffected by RIE and the adverse affects of amorphization avoided. With this approach, the substantially isotropic etch step included in manufacturing stage52-14should remove not only enough material for corner rounding but also enough material to remove any RIE etch damage, whichever is greater. Either approach is useful.

The manufacturing sequence illustrated by manufacturing stages52-12through52-17, show body contact region85and source regions86being provided after material87is deposited in trench91. While this is preferred it is not essential. Body contact regions85and sources86may be formed, for example, by ion implantation (or other doping technique) into structure54-13ofFIG. 13when body region84is formed, followed by the remainder of manufacturing stages52-14through52-17or at other manufacturing stages. Also, while it is convenient to use in-situ doping during growth of trench region82to provide body region84, this also is not essential. trench region82may be formed of a single conductivity type (e.g., N-type) and then (e.g., P) body region84formed by ion implantation or other doping means into, for example, substantially planarized structure54-13of stage52-13. Either arrangement is useful.

FIGS. 18-19are simplified flow diagram illustrating methods100and200for forming the structures illustrated inFIGS. 3-17, according to still further embodiments of the present invention. Referring now toFIG. 18, method100begins with START102and initial PROVIDE A SUBSTRATE step104, e.g., substrate56with or without buffer layer58. Single crystal silicon is a non-limiting example of a suitable substrate material, but other materials can also be used. Non-limiting examples are SiC, Ge, GaAs, GaN, AlN, InN, BP, InP, etc. As has already been explained, SiGe is an example of a suitable material for buffer layer58, but other materials such as those listed above may also be used. In step106, comprising sub-steps107,108that may be performed in either order, the first and second spaced-apart, interleaved semiconductor regions (e.g., regions70,74) having, for example, relaxed and strained lattice characteristics are formed. In sub-step107, first spaced-apart (e.g., relaxed) semiconductor (abbreviated as “SC”) regions of a first doping type (either N or P) are formed on the substrate. In sub-step108, second spaced-apart (e.g., strained) semiconductor (SC) regions of a second doping type opposite the first doping type are formed interleaved with the first spaced-apart regions to form a superjunction structure. The first and second interleaved SC regions may be formed in either order, that is, the first (e.g., relaxed) SC regions may be formed first and the second (e.g., strained) SC regions may be formed second. This is the sequence illustrated inFIGS. 3-10, but this is not essential. Alternatively, the second (e.g., strained) spaced-apart SC regions may be formed first and the first (e.g., relaxed) spaced-apart SC regions may be formed second, interleaved with the second regions. Either arrangement is useful. This provides superjunction structure54-10ofFIG. 10. In subsequent step110, a further region of for example, substantially relaxed semiconductor (SC) (e.g., regions83,84) is formed over the superjunction structure, and having an outer surface, e.g., surface842. In step112, a trench is formed extending from the outer surface through the further region substantially to the superjunction structure. As previously described an isotropic etch may optionally be used to round the corners of this trench and/or eliminate any amorphous surface material resulting from trench formation, depending upon the particular process used to form the trench. In step114, at least the trench sides are lined with e.g., strained semiconductor (SC) material (e.g., material87) relative to the body region through which the trench passes, and in communication with the superjunction structure. Then in step116, the gate dielectric is formed over the e.g., strained SC material, the remainder of the trench desirably filled with the gate material and source regions and body contract regions provided in the further region so that the source regions are electrically coupled to the e.g., strained SC material and spaced apart from the superjunction structure so that current flow is via the e.g., strained SC material between the source regions and the drift space provided by the superjunction structure. Method100then proceeds to END118, however, persons of skill in the art will understand that various post-processing steps may also be performed to provide electrodes or electrical contacts to the various device regions, surface passivation, packaging and so forth. Such post-processing steps are well known in the art.

Referring now toFIG. 19, method200begins with START202and initial PROVIDE A SUBSTRATE step204, e.g., substrate56with or without buffer layer58. Single crystal silicon is a non-limiting example of a suitable substrate material, but other materials can also be used. Non-limiting examples are SiC, Ge, GaAs, GaN, AlN, InN, BP, InP, etc. As has already been explained, SiGe is an example of a suitable material for buffer layer58, but other materials, for example, one or more of those listed above may also be used. In step206, comprising sub-steps207,208that may be performed in either order, the first and second spaced-apart, interleaved semiconductor regions (e.g., regions70,74) having first and seconds mobilities are formed. In sub-step207, first spaced-apart semiconductor (abbreviated as “SC”) regions (e.g., regions70) of a first doping type (either N or P) and a first mobility are formed on the substrate. In sub-step208, second spaced-apart semiconductor (SC) regions (e.g., regions74) of a second doping type opposite the first doping type and a higher second mobility for the same carriers are formed interleaved with the first spaced-apart regions to form a superjunction structure. The first and second interleaved SC regions may be formed in either order, that is, the first (e.g., relaxed) SC regions may be formed first and the second (e.g., strained) SC regions may be formed second. This is the sequence illustrated inFIGS. 3-10, but this is not essential. Alternatively, the second higher mobility spaced-apart SC regions may be formed first and the first spaced-apart SC regions of the first (lower) mobility may be formed second, interleaved with the second regions. Either arrangement is useful. This provides superjunction structure54-10ofFIG. 10. In subsequent step210, a body region of a third SC having a third mobility, communicating with the superjunction structure and having an outer surface (e.g., surface842) is formed over the superjunction structure. In step212, a trench (e.g., trench90,91) is formed extending from the outer surface through the body region to communicate with the superjunction structure. The first and third SC regions may be formed of substantially the same material, but this is not essential, provided they have higher mobility than their counterpart second and fourth SC material or regions. As previously described an isotropic etch may optionally be used to round the corners of this trench and/or eliminate any amorphous surface material resulting from trench formation, depending upon the particular process used to form the trench. In step214, at least the trench sides are lined with a fourth semiconductor (SC) material of a fourth higher mobility than the third mobility of the body region through which the trench passes. Then in step216, the gate dielectric is formed over the fourth SC material, the remainder of the trench desirably filled with the gate material insulated from the trench sides by the gate dielectric, and source regions and body contract regions provided so that the source regions are electrically coupled to the fourth SC material and spaced apart from the superjunction structure so that current flow is via the fourth SC material between the source regions and the drift space provided by the superjunction structure. Method200then proceeds to END218, however, persons of skill in the art will understand that various post-processing steps may also be performed to provide electrodes or electrical contacts to the various device regions, surface passivation, packaging and so forth. Such post-processing steps are well known in the art. As previously noted the source regions and body contact regions may be formed at any stage of the method200after formation of the body region.

According to a first embodiment, there is provided a method for forming a trench-type semiconductor device embodying a superjunction structure, comprising, in either order, forming first spaced-apart regions of a first semiconductor material having a first conductivity type and a first lattice constant, forming second spaced-apart regions of a second semiconductor material interleaved with the first space-apart regions, and having a second different conductivity type and a second different lattice constant so that the second semiconductor material in the second regions is strained with respect to the first semiconductor material in the first regions and one or more PN junctions exists therebetween, and providing a further region of substantially relaxed semiconductor material in contact with the first and second spaced-apart interleaved regions and having an outer surface, forming a trench in the further region extending from the outer surface substantially to the first and second spaced-apart interleaved regions, providing a strained semiconductor material on at least the side-walls of the trench, forming a gate dielectric over the strained semiconductor material, providing a gate in contact with the gate dielectric, spaced apart thereby from the strained semiconductor material, and providing one or more source regions communicating with the strained semiconductor material and separated from the first and second spaced-apart interleaved regions by a portion of the strained semiconductor material. In a yet further embodiment, the method further comprises before the forming steps, providing a substrate of a predetermined lattice constant having a principal surface, and providing on the principal surface a graded semiconductor layer having an inner surface against the principal surface and an outer surface distant from the inner surface adapted to receive the first spaced-apart regions and having a lattice constant at the outer surface that substantially matches the first lattice constant so that the first semiconductor material of the first regions formed on a first part of the outer surface is substantially relaxed. In a yet still further embodiment, the lattice constant at the outer surface is different from the second lattice constant so that the second material of the second regions formed on a second part of the outer surface is strained. In still further embodiment, the first semiconductor material comprises SiGe and the second semiconductor material comprises Si with less than 5% Ge. In a still yet further embodiment the first semiconductor material comprises Si:Ge ratios in the range of about 60:40 to 95:05. In another embodiment, the first semiconductor material comprises Si:Ge ratios in the range of about 70:30 to 90:10. In a yet another embodiment, the first semiconductor material comprises a Si:Ge ratios of about 80:20 to 85:15.

In a second embodiment there is provided a method for forming a semiconductor device, comprising, providing a substrate having an outer surface, forming on the outer surface, first spaced-apart semiconductor regions of a first conductivity type and first mobility\, forming on the outer surface second semiconductor regions of a second opposite conductivity type and higher second mobility, interleaved with the first spaced-apart semiconductor regions to form a superjunction structure, forming over the superjunction structure a first conductivity type body region of a third semiconductor having a third mobility, communicating with the superjunction structure and having an outer surface, providing a trench extending through the body region from the outer surface to communicate with the superjunction structure, and forming a fourth semiconductor region of a fourth mobility higher than the third mobility at least on the trench sidewalls. In a further embodiment the method further comprises forming a gate dielectric in contact with the fourth semiconductor region. In a still further embodiment, the method comprises forming a gate within the trench separated from the fourth semiconductor material by the gate dielectric. In a still yet further embodiment the method further comprises anytime after forming the body region, providing one or more source regions within the body region in contact with the fourth semiconductor region and separated from the superjunction structure by a portion of the fourth semiconductor region.

In a third embodiment there is provided a semiconductor device, comprising, a superjunction structure having interleaved regions of first and second semiconductor materials of opposite conductivity type and first and second mobilities, wherein the first and second semiconductor materials are separated by substantially parallel PN junctions and terminated at a first end by a substrate region substantially perpendicular to the PN junctions, wherein the superjunction structure has a second end spaced apart from the first end and wherein the second mobility is higher than the first mobility for the same carrier type, a body regions of a third semiconductor material of a third mobility, coupled to the second end and having an outer surface opposed to the second end, a trench having sidewalls extending from the outer surface at least to the second end, and a fourth material of a fourth mobility higher than the third mobility for the same type of carrier at least on the sidewalls, and communicating with the superjunction structure. In a further embodiment the first semiconductor material is a relaxed semiconductor material and the second semiconductor material is a strained semiconductor material. In a still further embodiment the third semiconductor material is a relaxed semiconductor material and the fourth semiconductor material is a strained semiconductor material. In a yet still further embodiment, the first and third semiconductor materials comprise SiGe and the second and fourth material is substantially silicon with less than 5% Ge. In a yet further embodiment the first and third semiconductor materials comprise Si:Ge in the ratio of X fraction Si to Y fraction Ge where X:Y ratios are in the range of 60:40 to 95:05. In a still yet further embodiment, Si:Ge ratios are in the range 70:30 to 90:10. In another embodiment, the substrate comprises a first substantially silicon region with a Si:Ge transition layer of varying composition located between the first substantially silicon region and the superjunction structure. In yet another embodiment, the transition has a composition next to the first substantially silicon region of substantially silicon and a composition next to the superjunction structure that substantially matches the composition of the first semiconductor material. In still another embodiment, the device further comprises, a first dielectric material at least on the fourth material on the sidewalls of the trench, and in a bottom portion of the trench, a second dielectric material of lower capacitance per unit area than the first dielectric.

While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist, especially with respect to choices of device types and materials and sequence of steps. The above-described invention is especially useful for formation of Trench-MOS devices, but persons of skill in the art will understand based on the description here in that other types of devices can also be fabricated using the principles described herein. For example, and not intended to be limiting, the present invention is useful for fabrication of Diode, BJT, IGBT and Thyristor devices as well as those described herein. Further, while Si and SiGe are provided as examples of suitable materials for use in combination to produce the adjacent relaxed (lower mobility) and strained (higher mobility) semiconductor regions described herein, this is merely be way of example and not intended to be limiting. The following is a non-limiting list of other suitable semiconductor materials that can be used in combination to achieve analogous lower mobility regions and higher mobility regions in a superjunction and trench configuration, specifically: GaN and Si, InGaN and GaN, InAsP and InP, SiC and AlN, SiC and BP, SiGe and GaAs, GaAs and Ge, Si and Si1-yCyand so forth. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiment or exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the invention as set forth in the appended claims and the legal equivalents thereof.