Data path training and timing signal compensation for non-volatile memory device interface

Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a device that includes an interface for communication with a host. The device includes components that can operate during at least one of read link training and duty cycle distortion compensation operation.

TECHNICAL FIELD

Embodiments described herein pertain to communication between devices in electronic systems. Some embodiments relate to interface training between integrated circuit devices.

BACKGROUND

Many electronic systems, such as computers, tablets, and cellular phones, include different devices. Examples of such devices include a host (e.g., a processor device), a memory device, and other integrated circuit (IC) device. The devices communicate with each other using signals (e.g., data signals and timing signals (e.g., strobe signals)). To improve accuracy in signals communicated between these devices, many conventional techniques are available for calibration of circuitry (e.g., receivers and transmitters) in these devices. In some conventional techniques, one device (e.g., a host) may perform all or a major portion of such calibration. Such conventional techniques may be burdensome on the device that performs the calibration.

DETAILED DESCRIPTION

The techniques described herein relate to NAND Flash interface. However, the described techniques may also be used in other Input/Output (I/O) communication with a memory device (e.g., a NAND memory device).

Open NAND Flash Interface (ONFI) standards, which is one of the interface for NAND interface include communications between NAND flash memory device and other devices (e.g., a host, such as a processor device). Techniques defined NAND memory device input/output interface (NAND interface) run maximum speed up to 800 megatransfers per second (MT/s). Future storage solutions targeted host interfaces, such as Peripheral Component Interconnect Express (PICe) Gen 3 and Gen 4 (PCIe-Gen3/4) and Universal Flash Storage version 3.0 (UFS 3.0) or beyond for NAND interface in order to have large storage capacity. In order to saturate PCIe/UFS host interfaces with a lower number of channels, a NAND IO interface speed needs to scale up much faster (e.g., up to 1600 MT/s or higher) than the IO interface speed defined by NAND Interfaces. Some recently developed NAND interfaces (e.g., the Toggle-mode NAND interface) can have an increased speed of up to 1200 MT/s.

Operating IO interfaces at a relatively high speed (e.g., up to 1600 MT/s or higher) suffers significant AC timing margin loss due to channel losses, NAND internal variations (e.g., due to process, voltage, and temperature (PVT) and internal timing mismatches) and host-side inherit losses (e.g., due to host-side DQ (data) and DQS (clock) mismatches). These factors can result in read AC timing margin loss or incorrect read data (e.g., data transferred from NAND device to the host). These losses may be much worse especially for higher multi-die stacking NAND memory device. Overcoming these losses can result in excessive power consumption. Another NAND implementation involves using an intermediate device (e.g., interface chip/repeater/retimer) between a host and NAND memory device in order accommodate a higher number of die stacks. Running such an intermediate device at a relatively higher speed can also suffer significant AC timing margin loss that can lead to read timing margin loss or incorrect read data.

The techniques described herein include solutions to resolve above-mentioned challenges for read operation in a memory device (e.g., NAND device) by providing a read link training mechanism (e.g., circuitry) at the memory device (e.g., NAND) side (or alternatively interface-chip side, repeater side, and retimer side). The read link training mechanism can improve read system AC timing margin loss. In this mechanism, the device (e.g., NAND/interface chip/repeater/retimer) coupled to the host is responsible for detecting read command from the host, generating internal data (e.g., 32 bits stress data pattern) based on mask information (sent by host), and storing the internal generated data in a memory circuit (e.g., a first-in first-out (FIFO)) in the device. The device is also responsible for sending back to the host (upon a request from the host) the internal generated data (stored in the FIFO of the memory device) in which the data is aligned with strobe signals (provided by the device). The host can use the read data (internally generated data from the FIFO of the device) to calibrate the host's internal timing. Unlike some conventional interface training techniques where the burden of the interface training is implemented in the host-side only, the interface training described herein can be performed in part by the device coupled to the host. This interface training technique can reduce burden for the host to implement and perform interface training.

Operating IO interfaces in NAND/interface chip/repeater/retimer at a relatively high speed (e.g., up to 1600 MT/s or higher) also suffers significant duty cycle distortion (DCD) related to timing margin loss due to the above-mentioned factors (e.g., channel losses, NAND internal PVT variations). The techniques described herein also include solutions to resolve above-mentioned challenges by providing DCC link training mechanism at the NAND/interface chip/repeater/retimer side to improve system DCD-related AC timing margin loss. In this mechanism, the device (e.g., NAND/interface chip/repeater/retimer) coupled to the host is responsible for performing automatic RE detection (e.g., read enable detection) and calibrating duty cycle of RE buffer and generating improved DQS signals (e.g., DCD free DQS signals). The device is also responsible for sending to the host (upon a request from the host) a status indication that includes information of whether DCD is completed. The device also takes advantage of toggling of RE to calibrate internal oscillating signal (e.g., ring oscillating (OSC) signal). Unlike some conventional calibration techniques where the burden of the calibration (e.g., calibration for the link coupled to the double-data rate (DDR) memory device and embedded MultiMediaCard (eMMC) memory device (DDR/eMMC) devices) implemented in the host-side only, the calibration described herein can be performed in part by the device coupled to the host. This calibration technique can reduce burden for the host to implement and perform calibration.

Other improvements and benefits of the read link training and DCC link training are described below.

FIG. 1shows an apparatus including a host101, a device102, and a channel103between host101and device102, according to some embodiments described herein. Host101can include or can be included in a processor (e.g., a general-purpose processor, or an application-specific integrated circuit (ASIC)), a computer (e.g., a server), a networking device, a computer storage system, or other electronic devices or systems. Device102can include a memory device (e.g., a flash memory device (e.g., NAND flash memory device)), an interface device (e.g., an interface chip), a repeater, a retimer, or other devices. Channel103can include conductive paths to carry signals that are communicated between host101and device102. The conductive paths of channel103can include metal wires (e.g., metal traces on a circuit board). As shown inFIG. 1, host101and device102can include interfaces111and112, respectively, coupled to channel103. Each of interfaces111and112can include circuitry (e.g., physical layer (PHY) circuitry) to transmit and receive signals through channel103.

Host101and device102can communicate with each other to exchange information (e.g., data, clock, and control information) in the form of signals. Examples of such signals include CE_b (chip enable signal), CLE (command latch enable), ALE (address latch enable), CLK (clock signal), WE_b (write enable), RE/RE_b (read enable), W/R_n (read/write direction), DQ (data signals), and DQS (strobe signals). The signals shown in FIG. between host101and device102(and the signals shown in other figures in this description) can be based on ONFI specification. One skilled in the art would readily recognize that host101and device102can communicate with each using other signals (not shown). Device102can include any of the devices described below with reference toFIG. 2throughFIG. 18.

FIG. 2shows a memory device202including read training circuitry210, according to some embodiments described herein. As shown inFIG. 2, memory device202can receive signals that are similar to those described above with reference toFIG. 1, including signals CE_b, CLE, ALE, CLK, WE_b, RE/RE_b, W/R_n, DQin [7:0], DQout [7:0]. DQSIN_T, and DQSIN_C, DQSOUT_T, and DQSOUT_C. Signals DQin [7:0] and DQout [7:0] can be represented by signals DQ ofFIG. 1. Signals DQSIN_T, and DQSIN_C, DQSOUT_T, and DQSOUT_Ccan be represented by signals DQS ofFIG. 1.

As shown inFIG. 2, memory device202can include control signal path circuitry251(e.g., which can include components such as buffers and latches) to provide signals CE_b, ALE, CLE, and WE_b to control unit216. Memory device202can perform memory operations (e.g., read, write, and read link training operations) based on timing (e.g., signal levels) of signals CE_b, CLE, ALE, CLK, WE_b, and RE/RE_b.

Memory device202can include DQ buffer (e.g., input data buffer (receiver (RX))221to receive data signals (e.g., input data signals) DQin [7:0] from another device (e.g., host101). Data signals DQin [7:0] can be provided to memory device202during a write operation of memory device202. Memory device202can include input circuitry231to provide data signals DQin [7:0] (from DQ buffer221) to control unit216. Data signals DQin [7:0] can include eight bits (e.g., bit0through bit7(denotes as [7:0])) that can be provided concurrently (e.g., transferred in parallel) on paths (circuit paths)221aand221b. Thus, DQ buffer221can include eight separate receiver circuits to concurrently receive (e.g., receive in parallel) eight bits carried by (included in) signals DQin [7:0]. Input circuitry231can include a serial-in parallel-out (SIPO) circuit231ato receive signals DQin [7:0] from DQ buffer221and provide them to path221b. Thus, each of paths221aand221bcan include eight separate circuit paths to concurrently carry the bits (e.g., eight bits) of data signals DQin [7:0].

Memory device202can include DQ buffer (e.g., output data buffer (transmitter (TX)))222to provide data signals (e.g., output data signals) DQout [7:0] to another device (e.g., host101). Data signals DQout [7:0] can be provided by memory device202during a read operation of memory device202. Memory device202can include output circuitry232to receive data signals DQout [7:0] (from internal components (e.g., memory circuit such as FIFO215)) of memory device202and provide data signals DQout [7:0] to DQ buffer222. Data signals DCout [7:0] can include eight bits (e.g., bit0through bit7(denoted as [7:0])) that can be provided concurrently (e.g., transferred in parallel) on paths (circuit paths)222aand222b. Thus, DQ buffer222can include eight separate receiver circuits to concurrently receive (e.g., receive in parallel) eight bits carried by (included in) signals DQout [7:0]. Output circuitry232can include a parallel-in serial-out (PISO) circuit232ato receive signals DQout [7:0] on path222bfrom internal components (e.g., FIFO215) of memory device202. Thus, each of paths222aand222bcan include eight separate circuit path to concurrently carry the bits (e.g., eight bits) of data signals DQout [7:0].

FIG. 2shows each data signal DQin [7:0] and DQout [7:0] including eight bits (e.g., bit0through bit7) as an example. However, the number of bits concurrently carried by data signals DQin [7:0] can vary, and the number of bits of concurrently carried by data signals DQout [7:0] can vary. For example, data signals DQin [7:0] may carry 16 bits in parallel, and data signals DQout [7:0] may carry 16 bits in parallel.

As shown inFIG. 2, memory device202can include DQS buffer (e.g., input strobe buffer (receiver (RX)))241to receive strobe signals (e.g., input strobe signals) DQSin_Tand DQSIN_Cfrom another device (e.g., host101). Strobe signals DQSIN_Tand DQSIN_Ccan be true and complement signals (two separate clock signals). Strobe signals DQSIN_Tand DQSIN_Ccan be provided to memory device202during a write operation. DQS buffer241can generate clock signals CLK and CLK_B that can have the same frequency as strobe signals DQSOUT_Tand DQSOUT_C. Memory device202can receive data signals DQin [7:0] based on timing of clock signals CLK and CLK_B. Memory device202can include a divider (e.g., divided by four)253to divide clock signals CLK and CLK_B. Input circuitry231can use the divided clock signals (not shown) at the output of divider253to sample data signals DQin [7:0] and provide them to control unit216.

Memory device202can include DQS buffer (e.g., strobe output buffer (transmitter (TX)))242to provide strobe signals (e.g., output strobe signals) DQSOUT_Tand DQSOUT_Cto another device (e.g., host101). Strobe signals DQSOUT_Tand DQSOUT_Ccan be true and complement signals (two separate clock signals). Strobe signals DQSOUT_Tand DQSOUT_C can be provided by memory device202to another device (e.g., host101) during a read operation. Another device (e.g., host101) can receive data signals DQout [7:0] from memory device202on timing of strobe signals DQSOUT_Tand DQSOUT_C.

As shown inFIG. 2, read training circuitry210can include read calibration controller logic211, clock generators212and213, a pattern generator214, and a memory circuit such as a FIFO215. Read calibration controller logic211can be part of a control unit216of memory device202. In operation, read training circuitry210of memory device202can operate to detect a read command sent by a host (e.g., host101ofFIG. 1)) during a read link training mode. Then, read training circuitry210can generate internal data pattern (e.g., stress data pattern) DATAINTbased on mask information (e.g., mask bits or mask byte (or bytes)) provided by the host. As an example, internal data DATAINTcan include 32 bytes of data). Read training circuitry210can store internal data pattern DATAINTin FIFO215. Upon request from the host, read training circuitry210can send internal data pattern DATAINT(sent as data signals DQout [7:0]) and output strobe signals DQSOUT_Tand DQSOUT_C(generated by memory device202) to the host. Data signals DQout [7:0]) and strobe signals DQSOUT_Tand DQSOUT_Ccan be aligned (e.g., edge aligned) when they are sent to the host. The host can use the data pattern included in data signals DQout [7:0] (which are generated based on (e.g., are the same as) internal data pattern DATAINTin memory device202) to calibrate internal timing of the host. Details of the operation of read training circuitry21is described below with reference toFIG. 2,FIG. 3, andFIG. 4.

FIG. 3shows an example timing diagram of some of the signals of memory device202ofFIG. 2during a read link training operation, according to some embodiments described herein. The following description refers toFIG. 2andFIG. 3. As shown inFIG. 3, the read link training operation can include a command detection phase, a pattern detect and generation phase, and data transfer to host phase. Timing intervals tCS, tCALS, and tRPREindicate relative timing intervals (e.g., setup time intervals) based on the switching levels (e.g., edge transitions) of the respective signals as shown inFIG. 3corresponding to signals ALE, CLE, and WE_b. The level of the signals during command detection phase ofFIG. 3can indicate a presence of a command for the read link training described herein. For example, the levels of signals ALE, CLE, and WE_b during command detection phase ofFIG. 3can indicate that a request by a host (e.g., host101) has been issued to memory device202to cause memory device202to perform the read link training operation.

During the command detection phase inFIG. 3, read calibration controller logic211(FIG. 2) can detect commands (e.g., a read command) based on the combination of the levels of signals ALE, CLE, and WE_b. Specific combinations of the levels of signals ALE, CLE, and WE_b can allow memory device202to determine different operations (e.g., read, write, and read link training) of memory device202.

Data signals DQ [7:0] inFIG. 3can represent either data signals sent by the host or data to be provided to the host, depending on which phase of the read link training that memory device202operates. For example, during command detection phase and the pattern detect and generation phase inFIG. 3, data signals DQ [7:0] can represent data signals DQin [7:0] (e.g., sent by host101to memory device202) that can include information311, LUN information312, mask information (e.g., mask byte)313, and data patterns341and342. Information311can be user-defined information, which can include a command CMD to perform the read link training. Based on mask information313and data patterns341and342inFIG. 3, read training circuitry210can generate internal data pattern DATAINT(FIG. 2) to be stored in FIFO215(FIG. 2). During the data transfer to host phase inFIG. 3, data signals DQ [7:0] (which include a number of bits (e.g., bits D0through D15as shown inFIG. 3)) can represent data signals DQout [7:0] sent from memory device202to host101. As described above, data signals DQout [7:0] sent from memory device202to the host are generated based on internal data pattern DATAINTstored in FIFO215.

Referring toFIG. 2, during the read link training mode, read calibration controller logic211ofFIG. 2can enable (e.g., activate) pattern generator214and clock generator213. Pattern generator214can operate to generate internal data pattern DATAINT(e.g., 32 bytes of data) based on control information CTL1, data information DATA provided by control unit216, and clock signal PAT_CLK provided by clock generator213. Data information DATA can be generated based on data patterns341and342(FIG. 3) received from the host. Clock generator213can generate clock signals PAT_CLK and WE_CLK based on an internal oscillating clock signal OSC of memory device202. Read calibration logic211ofFIG. 2can provide control information CTL2to FIFO215. FIFO215can operate to store internal data pattern DATA_INT (generated by pattern generator214) using timing provided by clock signal WE_CLK.

Read training circuitry210can wait for the toggling of signals RE/REb. The toggling of signals RE/REb is an indication of a command (e.g., a request) sent by the host to read the data pattern DATAINT(stored in FIFO215). Read training circuitry210can generate strobe signals DQSOUT_Tand DQSOUT_Cbased on the timing (e.g., the toggling) of signals RE/Reb. Clock generator212can respond to the toggling of signals RE/Reb and generate clock signals RE_CLK and RD_CLK, and strobe signal DQSOUT. DQS buffer242can generate strobe signals DQSOUT_Tand DQSOUT_cbased on strobe signal DQSOPUT. FIFO215can use clock signal RE_CLK to read (e.g., unload) internal data pattern DATAINT. A divider (e.g., divided by four)261can divide clock signal RD_CLK and provide a divided clock signal RD_CLK_DIV to output circuitry232, which can use divided clock signal RD_CLK_DIV to receive internal data pattern DATAINTfrom FIFO215and clock signal DQSOUTto provide internal data pattern DATAINTto DQ buffer222. During the data transfer to host phase, data signals DQout [7:0] and strobe signals DQSOUT_Tand DQSOUT_Ccan be aligned (e.g., edge aligned) and sent to the host. As mentioned above, the host can use data signals DQout [7:0] to calibrate internal timing of the host.

FIG. 4is flowchart showing a method400of performing a read link training, according to some embodiments described herein. Method400can be performed by memory device202ofFIG. 2(e.g., performed by at least read training circuitry210of memory device202). As shown inFIG. 4, method400can start the read link training operation at activity402and complete the read link training operation at activity418. Method400can include activity404that can include detecting a read command (e.g., a read command sent by a host). If activity404does not detect a read command (indicated by “NO” inFIG. 4), then method400can skip the rest of the read link training operation and go to activity418. This means that method400may terminate the read link training (e.g., not perform the read link training) because of lack of information to perform the read link training. If activity404detects a read command (indicated by “YES” inFIG. 4), then method400can continue with activity406.

Activity406can include determining whether the logic unit number (LUN) information (e.g., LUN address) associated with the read command sent by the host match the LUN information associated with (e.g., assigned to) memory device202. If activity406determines that the LUN information sent by the host does not match the LUN information associated with memory device202(indicated by “NO” inFIG. 4), then method400can skip the rest of the read link training operation and go to activity418. This means that method400may terminate the read link training (e.g., not perform the read link training) because of lack of information to perform the read link training. If activity406determines that the LUN information sent by the host matches the LUN information associated with memory device202(indicated by “YES” inFIG. 4), then method400can continue with activity408.

Activity408can include detecting mask information (e.g., mask bytes sent by a host). If activity408does not detect the mask information (indicated by “NO” inFIG. 4), then method400can skip the rest of the read link training operation and go to activity418. This means that method400may terminate the read link training (e.g., not perform the read link training) because of lack of information to perform the read link training. If activity408detects the mask information, then method400can continue with activity410.

Activity410can include receiving data (e.g., data patterns241and242) sent to memory device202from the host. Activity410can include sending the received data to the control unit (e.g., control unit216ofFIG. 2) of memory device202.

Activity412of method400can include generating internal data based on the received data and the mask information. Activity412can include storing the generated internal data in a FIFO (e.g., FIFO215) of the memory device202.

Activity414can include detecting get data command. The get data command can be in the form of the toggling of signal RE. For example, if the RE signal toggles after an amount of time has elapsed from the end of the command detection phase (e.g., from when the mask information is detected), then it can be determined that the get data command is detected. In this example, if the RE signal does not toggle after an amount of time has elapsed from the end of the command detection phase (e.g., from when the mask information is detected), then it can be determined that the get data command is not detected. If activity414does not detect the get data command (indicated by “NO” inFIG. 4), then method400can skip the rest of the read link training operation and go to activity418. This means that method400may terminate the read link training (e.g., not perform the read link training) because of lack of information to perform the read link training. If activity414detects the get data command (indicated by “YES” inFIG. 4), then method400can continue with activity416.

Activity416can include retrieving (e.g., unloading) the internal data stored in the FIFO of the memory device202and enabling output circuitry, which can include a Parallel In Serial Out (PISO) circuit (e.g., a half rate PISO circuit) and transmitters. Activity416can also include sending the internal data from the FIFO to the output circuitry and from the output circuitry to the host. Then, method400can complete the read link training at activity418.

Some of the improvements and benefits of the read link training described above with reference toFIG. 1throughFIG. 4include improving interfaces' scalability for solid-state drive (SSD) solution and operating link beyond a relatively high data transfer rate (e.g., 1600 MT/s or higher), increasing storage capacity and improving (e.g., reducing) latency, improving read link AC timing margin, reducing internal timing error at memory device side due to mismatches and PVT variations, and mitigating channel losses. The read link training of memory device202also helps in saving significant post-silicon validation effort cost to improve AC margin and may avoid software- or firmware-based trimming. Further, improvements and benefits of the read link training described above with reference toFIG. 1throughFIG. 4can help the host to calibrate the host's data transmission timing.

FIG. 5shows a memory device502including duty cycle distortion (DCD) compensation circuitry510, according to some embodiments described herein. Memory device502can include elements (e.g., physical components (e.g., buffers and circuitry) and signals) that are similar to or identical to some of the elements of memory device202ofFIG. 2. Thus, for simplicity, similar or identical elements betweenFIG. 2andFIG. 5are given the same labels and their descriptions are not repeated.

As shown inFIG. 5, compensation circuitry510can include RE buffer (e.g., input buffer (receiver (RX))511to receive signals (complementary read enable signals) RE_t and RE_t_c and generate clock signals (complementary signals) RE_CLK and RE_CLK_B based on signals RE_t and RE_t_c. Compensation circuitry510can include a clock generator512to generate clock signals (complementary signals) CLK and CLK_B based on signals RE_CLK and RE_CLK_B. Clock signals (complementary signals) CLK and CLK_B can be used to generate strobe signals DQSOUT_Tand DQSOUT_C, respectively. For example, clock signals CLK and CLK_B can be provided to DQS buffer242through a serializer515DQS buffer242can operate to provide signals (complementary signals) DQSOUT_Tand DQSOUT_Cbased on clock signals CLK and CLK_B. Memory device502can send (e.g., send to host101) data signals DQSOUT[7:0] and strobe signals DQSOUT_Tand DQSOUT_Cduring a read operation of memory device202.

As shown inFIG. 5, compensation circuitry510can include a monitor513and DCC logic514(e.g., logic circuitry). Memory device502can include a control unit526that can operate to detect the levels of signals ALE and CLE that indicate a command (e.g., request by a host) has been issued to memory device502to cause memory device502to perform the DCC calibration operation. Based on the detection, control unit526can enable (e.g., by using information DCC_EN) DCC logic514to detect the toggling of signals RE_t and RE_t_c (e.g., by monitoring clock signals CLK and CLK_B) and begin part of the DCC calibration operation. DCC logic may provide information DCC_DONE to control unit526when the DCC calibration operation is done.

Monitor513can operate to detect the toggling of signals RE_t and RE_t_c (e.g., by monitoring the levels of clock signals CLK and CLK_B). Monitor513can compare the average value (e.g., average voltage value) of clock signals CLK and CLK_B with a reference voltage. Since clock signals CLK and CLK_B are generated based on signals RE_CLK and RE_CLK_B, the average of clock signals CLK and CLK_B can also be the average of signals RE_CLK and RE_CLK_B. Further, since signals RE_CLK and RE_CLK_B are generated based on signals RE_t and RE_t_c, the average of signals RE_CLK and RE_CLK_B can also be the average of signals RE_t and RE_t_c. Thus, the average of clock signals CLK/CLK_B, the average of signals RE_CLK/RE_CLK_B, and the average of signals RE_t and RE_t_c can have the same relationship with a specific (e.g., predetermined) reference value. For example, the average of each of clock signals CLK/CLK_B, signals RE_CLK/RE_CLK_B, and signals RE_t and RE_t_c can be less than a reference value. In another example, the average of each of signals CLK/CLK_B, signals RE_CLK/RE_CLK_B, and signals RE_t and RE_t_c can be equal to a reference value. In a further example, the average each of clock signals CLK/CLK_B, signals RE_CLK/RE_CLK_B, and signals RE_t and RE_t_c can be greater than a reference value.

As shown inFIG. 5, compensation circuitry510can include DCC logic (e.g., circuitry)514to control (e.g., adjust) RE buffer511based on the result of the comparison performed by monitor513. As mentioned above, monitor513can compare the average values of clock signals CLK and CLK_B with a reference voltage and provide the result of the comparison. Based on the result of the comparison, DCC logic514can adjust RE buffer511to reduce or eliminate duty cycle distortion of clock signals CLK and CLK_B, so that the values of clock signals CLK and CLK_B are be within an acceptable (e.g., predetermined values) duty cycle value. As an example, DCC logic514can adjust RE buffer511by providing different values for code DCC_CODE (a digital code that can include multiple bits) to decrease, hold (keep the same), or increase the frequency of signals RE_CLK and RE_CLK_B (which are used to generate clock signals CLK and CLK_B) until monitor513determines (e.g., based on the result of the comparison) that the values (e.g., average values) of clock signals CLK and CLK_B are within an acceptable duty cycle value.

Compensation circuitry510can also operate to adjust the frequency of a signal OSC (an internal oscillating) that can be internally generated by an internal oscillator (e.g., a local ring oscillator)521. The frequency of signal OSC can be set (e.g., programmed) to be N times (where N is a real number) the frequency of clock signals CLK and CLK_B (which is also N times the frequency of signals RE_t and RE_t_c).

Compensation circuitry510can include a frequency detector522that can operate to determine (e.g., compare) the relationship between the frequency of clock signals CLK and CLK_B and frequency of signal OSC. Compensation circuitry510can include a control circuit523(which can include a finite state machine (FSM)) that can operate to control (e.g., adjust) the frequency of signal OSC based on the relationship between the frequency of clock signals CLK and CLK_B and frequency of signal OSC. For example, control circuit523can use different values of a code OSC_CODE (digital code) to control internal oscillator521in order to decrease, hold (keep the same), or increase the frequency of signal OSC, such that the frequency of signal OSC can be N times (e.g., a predetermined value) frequency of clock signals CLK and CLK_B.

Compensation circuitry510can include a multiplexer532that can respond to select information (e.g., signal) SEL to selectively provide output data DQout [7:0] to DQ buffer222. Data signals DQout [7:0] can be either data signals DQ [0:7] from control unit526or serialized data signals from a serializer533.

FIG. 6shows an example timing diagram of some of the signals of memory device502ofFIG. 5during a DCC training operation, according to some embodiments described herein. The following description refers toFIG. 5andFIG. 6. InFIG. 6, timing intervals tCS, tCALS, and tRPRE(which are different from those ofFIG. 3) indicate relative timing intervals (e.g., setup time intervals) based on the switching levels (e.g., edge transitions) of corresponding signals ALE, CLE, and WE_b. Timing intervals tCS, tCALS, and tRPREindicate relative timing intervals (e.g., setup time intervals) based on the switching levels (e.g., edge transitions) of the respective signals as shown inFIG. 3corresponding to signals ALE, CLE, and WE_b. The level of the signals during the command detection phase ofFIG. 3can indicate a presence of a command for the DCC training operation described herein.

As shown inFIG. 6, the DCD compensation operation can include a command detection phase, a training phase, and data transfer to host phase. During the command detection phase inFIG. 6, compensation circuitry510(FIG. 5) can detect commands (e.g., a DCC command) based on the combination of the levels of signals ALE, CLE, and WE_b. The host can send information611(e.g., DCC Enable indication) to memory device502and cause memory device502to enable DCC link training, and LUN information612to indicate that the enable DCC link training is for memory device502. During the training phase, the host can continue to drive signals RE_t and RE_t_c for a time interval equivalent to one page cycle (or alternatively for a time interval different from one page cycle). During the DCC training phase inFIG. 6, data signals DQ [7:0] (which include a number of bits (e.g., bits D0through D15shown inFIG. 6)) can represent data signals DQout [7:0] sent from memory device202to a host (e.g., host101). During the training phase, the host is not sampling DQ signals or Mask DQ signal. During the training phase, compensation circuitry510can adjust RE buffer511based on training (e.g., based on code DCC_CODE provided by DCC logic514, as described above with reference toFIG. 5). During the training phase, compensation circuitry510can also adjust OSC generator521(as described above). During data transfer to host phase, memory device502can send an indication of DCC training status upon request from the host.

FIG. 7is flowchart showing method700of performing clock signal calibration, according to some embodiments described herein. Method700can include activity712that can include starting the clock signal calibration. For example, activity712can be performed during DCC training phase (FIG. 6). Method700can include activity714that can include calculating an average of clock signals. The clock signals can include clock signals CLK and CLK_B (FIG.6). As described above, the average of clock signals CLK/CLK_B is also the average of signals RE_CLK/RE_CLK_B, and the average of signals RE_t and RE_t_c. InFIG. 7, method700can include activities716,717, and718that can respectively determine whether the average (calculated in activity)714is equal to, greater than, or less than a reference value (e.g., a predetermined value). Method700can control (e.g., adjust) the code (e.g., DCC_CODE inFIG. 5) that controls the buffer (e.g., RE buffer511inFIG. 5) that generates the clock signals clock signals CLK/CLK_B) in activity714or the signals (signals RE_t/RE_t_c or RE_CLK/RE_CLK_B). For example, method700can include activities720,721, and722that can perform respective operations of locking the buffer codes that control biasing of the buffer, incrementing the buffer codes that control biasing of the buffer, or decrementing the buffer codes that control biasing of the buffer if the average is equal to, greater than, or less than a reference value, respectively.

FIG. 8is a flowchart showing a method800of performing DCC training, according to some embodiments described herein. Method800can be performed by memory device502ofFIG. 5(e.g., performed by at least compensation circuitry510of memory device502). As shown inFIG. 8, method800can start the DCC training operation at activity802and complete the DCC training operation at activity818. Method800can include activity804that can include detecting a DCC command (e.g., a DCC command sent by a host). If activity804does not detect a DCC command (indicated by “NO” inFIG. 8), then method800can skip the rest of the DCC training operation and go to activity818. This means that method800may terminate the DCC training (e.g., not perform the DCC training) because of lack of information to perform the DCC training. If activity804detects a DCC command (indicated by “YES” inFIG. 8), then method800can continue with activity806.

Activity806can include determining whether the LUN information (e.g., LUN address) associated with the DCC command sent by the host matches the LUN information associated with (e.g., assigned to) memory device502. If activity806determines that the LUN information sent by the host does not match the LUN information associated with memory device502(indicated by “NO” inFIG. 8), then method800can skip the rest of the DCC training operation and go to activity818. This means that method800may terminate the DCC training (e.g., not perform the DCC training) because of lack of information to perform the DCC training. If activity806determines that the LUN information sent by the host matches the LUN information associated with memory device202(indicated by “YES” inFIG. 8), then method800can continue with activity808.

Activity808can include enabling DCC logic (e.g., DCC logic514) and a monitor (e.g., monitor513). Activity810of method800can include detecting the toggling of clock signals (e.g., clock signals CLK and CLK_B). If activity810does not detect the toggling of clock signals (indicated by “NO” inFIG. 8), then method800can skip the rest of the DCC training operation and go to activity818. This means that method800may terminate the DCC training (e.g., not perform the DCC training) because of lack of information to perform the DCC training. If activity810detects the toggling of clock signals, then method800can continue with activity812.

Activity812can include calibration of internal clock signals. Activity812can include the activities of method700shown inFIG. 7.

Activity814can include detecting a status command request from the host. If activity814does not detect the status command request from the host (indicated by “NO” inFIG. 8), then method800can skip the rest of the DCC training operation and go to activity818. This means that method800may terminate the DCC training (e.g., not perform the DCC training) because of lack of information to perform the DCC training. If activity814detects the status command request, then method800can continue with activity816.

Activity816can include updating DCC to compare complete information over DQ lane (e.g., through DQ buffer inFIG. 8) and send information of DCC training status to the host. Then, method800can complete the DCC training at activity818.

FIG. 9is a flowchart showing a method900of performing an internal oscillating signal calibration, according to some embodiments described herein. Method900can be performed by memory device502ofFIG. 5(e.g., performed by at least compensation circuitry510of memory device502). As shown inFIG. 9, method900can include activity902that can include starting the DCC training operation. Method900can include activity904that can include comparing clock signals (e.g., clock signals CLK and CLK_B) with an internal oscillating signal (e.g., signal OSC inFIG. 5). The clock signals can be clock signals CLK and CLK_B inFIG. 5(which are generated based on signals RE_CLK and RE_CLK_B, which are generated based on signals RE_t and RE_t_c). Method900can include activity906that can adjust the internal oscillating signal based on the result of the comparison. For example, activity can906can increase the frequency of the internal oscillating signal if the frequency of the internal oscillating signal is less than N times the frequency of the clock signals (N can be one or greater than one). In another example, activity can906can decrease the frequency of the internal oscillating signal if the frequency of the internal oscillating signal is greater than N times the frequency of the clock signals.

Method900can include activity908that can include determining whether the frequency of the internal oscillating signal is equal to N times the frequency of the clock signals. If frequency of the internal oscillating signal is not equal to N times the frequency of the clock signals (indicated by “NO” inFIG. 9), then method900can repeat activities904and906. If the frequency of the internal oscillating signal is equal to N times the frequency of the clock signals (indicated by “YES” inFIG. 9), then method900can continue with activity910, which can include ending the internal oscillating signal calibration.

Some of the improvements and benefits of the DCC training described above with reference toFIG. 5throughFIG. 9include improving interfaces' scalability for SSD solution and operating links beyond a relatively high data transfer rate (e.g., 1600 MT/s or higher), improving DCD related link AC timing margin, reducing internal timing error at the memory device side due to mismatches and PVT variations, and mitigating channel losses. The DCC training of memory device202also helps in saving significant post-silicon validation effort cost to improve AC margin and may avoid software- or firmware-based trimming.

The above description with reference toFIG. 5throughFIG. 9describes DCC training for RE buffer511. However, similar (or identical) techniques can also be used for DCC training for DQS buffer241. For example, memory device502can use monitor513and DCC logic514to generate code DCC_CODE (as described above with reference toFIG. 5) to adjust DQS buffer241in order to reduce or eliminate duty cycle distortion of clock signals CLK and CLK_B at the output of DQS buffer241.

FIG. 10shows a device1002including read training circuitry1010and compensation circuitry1020, according to some embodiments described herein. Device1002can include device102ofFIG. 1. For example, device1002can include a memory device (e.g., a flash memory device (e.g., NAND flash memory device)) that can include a control unit1016and memory cells (e.g., non-volatile memory cells including flash memory cells)1004. Control unit1016can perform the functions control unit216(FIG. 2) and control units526(FIG. 5). Alternatively, device1002can include an interface device (e.g., an interface chip), a repeater, a retimer, or other devices. Read training circuitry1010and DCD compensation circuitry1020can be read training circuitry210ofFIG. 2and compensation circuitry510ofFIG. 5, respectively. Although device1002includes read training circuitry1010and DCD compensation circuitry1020, one of circuitry1010and1020can be omitted from device1002.

ADDITIONAL NOTES AND EXAMPLES

In Example 1 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including an interface to communicate with a host, a calibration logic to detect signals indicating a training operation from the host, a buffer to receive data and mask information sent by the host for the training operation, a data pattern generator to generate internal data based on the data and the mask information, a memory circuit to store the internal data, and output circuitry to send the internal data to the host based on a request from the host.

In Example 2, the subject matter of Example 1 may optionally include, further comprising a read calibration logic to enable the memory circuit to provide the internal data to the output circuit upon toggling of a signal indicating the request from the host.

In Example 3, the subject matter of Example 2 may optionally include, further comprising an additional buffer to send strobe signals with data signals to the host, the data signal carrying bits of the internal data.

In Example 4, the subject matter of Example 2 or 3 may optionally include, further comprising a clock generator to generate a first clock signal and a second clock signal based on the signal indicating the request from the host, wherein the memory circuit is to provide the internal data to the output circuit based on timing of the first clock signal, and the output circuitry is to provides the internal data to the host based on timing of the second clock signal.

In Example 5, the subject matter of Example 4 may optionally include, further comprising an additional clock generator to generate a third first clock signal based on timing of an oscillating signal, and the data pattern generator is to generate the internal data based on timing of the third clock signal.

In Example 6, the subject matter of Example 4 may optionally include, wherein the memory circuit is a first-in first-out memory circuit.

In Example 7, the subject matter of Example 1 may optionally include, wherein the apparatus comprises a memory device.

Example 8 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including an interface to communicate with a host, a buffer to receive a signal sent by the host and to receive code, a calibration logic to detect signals indicating a training operation from a host coupled to the interface, and to detect toggling of the signal after signals indicating a training operation are detected, a clock generator to generate clock signals based on the signal received by the buffer, a monitor to compare an average value of the clock signals with a reference voltage to generate a comparison result, and a logic to control value of the code based on the comparison result to control timing of the clock signals.

In Example 9, the subject matter of Example 8 may optionally include, wherein the logic is to adjust the value of the code during a time interval when the signal toggles.

In Example 10, the subject matter of Example 8 or 9 may optionally include, wherein the logic is to increase the value of the code if an average value of the clock signals are greater than the reference voltage, and the logic is to decrease the value of the code if the average value of the clock signals are less than the reference voltage.

In Example 11, the subject matter of Example 8 or 9 may optionally include, further comprising a control circuit to generate an additional code to adjust the frequency of an oscillating signal based on the frequency of the signal received by the buffer.

In Example 12, the subject matter of Example 8 may optionally include, further comprising an additional buffer to provide strobe signals generated by the clock signals.

In Example 13, the subject matter of Example 8 may optionally include, wherein the logic is to provide a status of the training to the host based a request from the host.

In Example 14, the subject matter of Example 8 may optionally include, further comprising additional buffers to provide data signals to the host, wherein the host is to refrain from sampling data signals at the additional buffers.

In Example 15, the subject matter of Example 8 may optionally include, wherein the apparatus comprises a flash memory device.

Example 16 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including a host, a communication channel coupled to the host, and a non-volatile memory device coupled to the communication channel, the non-volatile memory device including a calibration logic to detect signals indicating a training operation from the host, a buffer to receive data and mask information sent by the host for the training operation, a data pattern generator to generate internal data based on the data and the mask information, a memory circuit to store the internal data, and output circuitry to send the internal data to the host based on a request from the host.

In Example 17, the subject matter of Example 16 may optionally include, further comprising an additional buffer to receive a signal sent by the host and to receive code, a clock generator to generate clock signals based on the signal received by the additional buffer, a monitor to compare an average value of the clock signals with a reference voltage to generate a comparison result, and a logic to control value of the code based on the comparison result to control timing of the clock signals.

In Example 18, the subject matter of Example 17 may optionally include, wherein the additional buffer includes an input strobe buffer to receive an input strobe signal from the host.

In Example 19, the subject matter of Example 16 may optionally include, wherein the communication channel includes metal wires on a circuit board.

In Example 20, the subject matter of Example 16 may optionally include, wherein the apparatus comprises a processor.

Example 21 includes subject matter (such as a method of operating a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including detecting, at a memory device, signals from a host that indicate a training operation from the host, receiving data and mask information sent by the host for the training operation, generating internal data at the memory device based on the data and the mask information received from the host, storing the internal data in the memory device, and sending the internal data to the host based on a request from the host.

In Example 22, the subject matter of Example 22 may optionally include, wherein further comprising enabling the memory circuit to provide the internal data to the host based on a toggling of a signal indicating the request from the host.

In Example 23, the subject matter of Example 22 may optionally include, further comprising sending strobe signals with data signals to the host in response to the toggling of the signal, the data signal carrying bits of the internal data.

Example 24 includes subject matter (such as a method of operating a device, an electronic apparatus (e.g., circuit, electronic system, or both), or a machine) including receiving a code at a buffer, detecting, at a memory device, signals from a host that indicates a training operation from the host, detecting toggling of an additional signal after the signals sent by the host are detected, generating clock signals based on the additional signal, comparing an average value of the clock signals with a reference voltage to generate a comparison result, and controlling a value of the code based on the comparison result in order to control timing of the clock signals.

In Example 25, the subject matter of Example 22 or 23 may optionally include, wherein further comprising generating an additional code to adjust the frequency of an oscillating signal at the memory device based on the frequency of the signal received by the buffer.

Example 26 includes subject matter (such as a device, an electronic apparatus (e.g., circuit, electronic system, or both), or machine) including means for performing any of the subject matter of Examples 1 through 25.

The subject matter of Examples 1 through 26 may be combined in any combination.

The above description and the drawings illustrate some embodiments to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Therefore, the scope of various embodiments is determined by the appended claims, along with the full range of equivalents to which such claims are entitled.