Semiconductor device

According to one embodiment, a semiconductor device includes lower layer wirings formed on a semiconductor chip, a protection film arranged on the lower layer wirings, an upper layer wiring arranged on the protection film and across a plurality of lower layer wirings, and connected to the lower layer wirings, wherein the upper layer wiring is larger than the lower layer wirings in terms of wiring line width and wiring line thickness, and a stress relaxing portion configured to reduce a stress at an in-corner portion of the upper layer wiring on the protection film, as compared with a case where the in-corner portion is set in 90°.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-52197, filed on Mar. 16, 2015; the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

As regards semiconductor elements, such as a power transistor, through which a large current flows, there is a case where a Cu plate wiring is used to reduce the ON-resistance.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includes a semiconductor chip, lower layer wirings, a protection film, an upper layer wiring, and a stress relaxing portion. The lower layer wirings are disposed over the semiconductor chip. The protection film is disposed over the lower layer wirings. The upper layer wiring is disposed over the protection film and across a plurality of lower layer wirings, and connected to the lower layer wirings. The upper layer wiring is larger than the lower layer wirings in terms of wiring line width and wiring line thickness. The stress relaxing portion is configured to reduce a stress at an in-corner portion of the upper layer wiring on the protection film, as compared with a case where the in-corner portion is set in 90°.

Exemplary embodiments of a semiconductor device will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

First Embodiment

FIG. 1is a sectional view showing a schematic configuration of a semiconductor device according to a first embodiment.

As shown inFIG. 1, the semiconductor chip1is soldered on a heat sink2via a solder material3. Here, the semiconductor chip1may be provided with a power transistor through which a current of 1 A or more flows, for example. This power transistor may be formed of a DMOS (Diffused MOS) transistor to effect that the ON-resistance is reduced while the breakdown voltage is ensured. The solder material3may be a Pb/Sn alloy or the like, for example. The heat sink2may be made of Cu plated with Au or the like, for example. The semiconductor chip1is connected to lead terminals4through bonding wires5. Further, the semiconductor chip1, the solder material3, and the bonding wires5are sealed by a sealing resin6. In this case, the respective joint faces between the bonding wires5and the lead terminals4are also sealed by the sealing resin6. The lead terminals4may be made of Cu plated with Au or the like, for example. The bonding wires5may be formed of Cu wires or the like, for example. The sealing resin6may be made of a thermosetting resin, such as epoxy resin, for example.

FIG. 2Ais a plan view showing an example of a wiring layout in the semiconductor chip shown inFIG. 1, andFIG. 2Bis a plan view showing a portion B ofFIG. 2Ain an enlarged state.

As shown inFIG. 2A, lower layer wirings HA are formed on the semiconductor chip1. A protection film30is formed on the lower layer wirings HA. An upper layer wiring HB is formed on the protection film30, and is connected to the lower layer wirings HA. Here, an opening portion30K is formed in the protection film30. Thus, the upper layer wiring HB can be connected to the lower layer wirings HA through the opening portion30K. The upper layer wiring HB may be designed to be larger than the lower layer wirings HA, in both of the wiring line width and the wiring line thickness. For example, the upper layer wiring HB may be set such that each of the wiring line width and the wiring line thickness is ten or more times as large as that of the lower layer wirings HA. In this respect, each of the wiring line width and wiring line thickness of the lower layer wirings HA may be set to 1 μm or less, the wiring line width of the upper layer wiring HB may be set to 10 μm or more, and the wiring line thickness of the upper layer wiring HB may be set to 5 μm or more. The upper layer wiring HB may be used to reduce the ON-resistance of the power transistor provided in the semiconductor chip1. The upper layer wiring HB may be formed by use of plating to increase the wiring line thickness. This upper layer wiring HB may be arranged to be present across a plurality of lower layer wirings HA, and so a plate wiring may be constituted.

Here, as shown inFIG. 2B, the in-corner portion of the upper layer wiring HB on the protection film30is formed with a chamfer portion K1, which serves to relax a stress at the in-corner portion. As compared with a case where the in-corner portion of the upper layer wiring HB is set in 90° in designing the pattern, the chamfer portion K1can reduce a stress at the in-corner portion. Here, in order to effectively reduce the stress at the in-corner portion, the chamfering may be preferably set to 5 μm or more, and more preferably set to 20 μm or more.

The upper layer wiring HB may be constituted by a three-layer structure. In this case, the first layer of the upper layer wiring HB may be made of a material having a conductivity equal to or higher than that of the lower layer wirings HA. The second layer of the upper layer wiring HB may be made of a material that prevents corrosion of the first layer of the upper layer wiring HB and serves as an underlying layer for the third layer of the upper layer wiring HB. The third layer of the upper layer wiring HB may be made of a material capable of being in close contact with the bonding wires. For example, the upper layer wiring HB may have a three-layer structure formed of Cu/Ni/Au. In order to avoid use of expensive Au, the upper layer wiring HB may have a three-layer structure formed of Cu/Ni/Pd. As the material of the protection film30, for example, an inorganic film made of, e.g., SiO2or SiN may be used, or an organic film made of, e.g., polyimide (PI) may be used.

Here, Ni has a higher Young's modulus than Cu. Accordingly, if both of Ni and Cu are used for the upper layer wiring HB, when a thermal stress is applied to the upper layer wiring HB, the thermal stress concentrates at an in-corner portion of the upper layer wiring HB. Further, the adhesiveness between the upper layer wiring HB and the protection film30is poorer than the adhesiveness between the upper layer wiring HB and the lower layer wirings HA. Accordingly, in a state where the protection film30is present under the upper layer wiring HB, when a thermal stress concentrates at an in-corner portion of the upper layer wiring HB, the upper layer wiring HB is peeled from the protection film30and the Ni of the upper layer wiring HB is cracked, as the case may be. At this time, however, the chamfer portion K1arranged at the in-corner portion can relax the concentration of the thermal stress at the in-corner portion of the upper layer wiring HB. Consequently, it becomes possible to prevent the upper layer wiring HB from being peeled from the protection film30, and to prevent the Ni of the upper layer wiring HB from being cracked. Thus, as shown inFIG. 1, even in a case where the semiconductor chip1is soldered on the heat sink2, the semiconductor chip1can ensure its reliability.

FIG. 3Ais a plan view showing a portion A ofFIG. 2Ain an enlarged state, andFIG. 3Bis a sectional view showing a configuration taken along a line E-E ofFIG. 3A. Here,FIG. 3AandFIG. 3Bshow an example in which the semiconductor chip1is provided with DMOS transistors, each of which is of an STI (Shallow Trench Isolation) offset type.

As shown inFIG. 3AandFIG. 3B, an epitaxial semiconductor layer13is formed on a semiconductor substrate11. At the boundary between the semiconductor substrate11and the epitaxial semiconductor layer13, a high-concentration impurity diffusion layer12is embedded. As the material of the semiconductor substrate11and the epitaxial semiconductor layer13, for example, Si, Ge, SiGe, GaAs, GaAlAs, InP, GaP, GaN, SiC, or InGaAsP may be used. They may be set such that the conductivity type of the semiconductor substrate11is P-type, the conductivity type of the epitaxial semiconductor layer13is N-type, and the conductivity type of the high-concentration impurity diffusion layer12is N+-type.

In the epitaxial semiconductor layer13, STIs15are embedded. Around the STIs15, DTIs (Deep Trench Isolation)14are embedded such that they penetrate the epitaxial semiconductor layer13and reach the semiconductor substrate11. As the material of the STIs15and the DTIs14, for example, SiO2or the like may be used.

In the epitaxial semiconductor layer13, source layers S and drain layers D are formed in an active region between the DTIs14. The conductivity type of the source layers S and drain layers D may be set in P+-type. Gate electrodes16are arranged on the active region respectively at portions between the source layers S and the drain layers D. In this case, in order to increase the breakdown voltage of each of the DMOS transistors, the portion between the drain layer D and the channel region under each of the gate electrodes16may be provided with an offset by an amount corresponding to an STI15.

On the epitaxial semiconductor layer13, an interlayer insulating film19is formed such that the gate electrodes16are embedded therein. Further, in the interlayer insulating film19, wiring lines21S and21D arranged above the gate electrodes16are embedded. Each of the wiring lines21S is connected to the corresponding source layer S through a plug electrode20S, and each of the wiring lines21D is connected to the corresponding drain layer D through a plug electrode20D. On the wiring lines21S and21D, an interlayer insulating film22is formed. In the interlayer insulating film22, wiring lines24S and24D are embedded. Each of the wiring lines24S is connected to the corresponding wiring line21S through a plug electrode23S, and each of the wiring lines24D is connected to the corresponding wiring line21D through a plug electrode23D. On the wiring lines24S and24D, an interlayer insulating film25is formed. In the interlayer insulating film25, wiring lines27S and27D are embedded. Each of the wiring lines27S is connected to the corresponding wiring line24S through a plug electrode26S, and each of the wiring lines27D is connected to the corresponding wiring line24D through a plug electrode26D. On the wiring lines27S and27D, an interlayer insulating film28is formed. In the interlayer insulating film28, opening portions28K are formed such that the wiring lines27D are exposed therein. On the interlayer insulating film28, a pad electrode29is formed. The pad electrode29is connected to the wiring lines27D through the opening portions28K. In this case, in order to reduce the ON-resistance, a plurality of drain layers D may be connected in parallel with each other, through the wiring lines21D,24D, and27D. As the material of the gate electrodes16, for example, polycrystalline silicon may be used. As the material of the wiring lines21S,21D,24S,24D,27S, and27D, for example, a metal, such as Al or Cu, may be used. As the material of the plug electrodes20S,20D,23S,23D,26S, and26D, for example, a metal, such as W, Al, or Cu, may be used. As the material of the pad electrode29, for example, a metal, such as Al, may be used. As the material of the interlayer insulating films19,22,25, and28, for example, SiO2or the like may be used. The wiring line width of the wiring lines21S,21D,24S,24D,27S, and27D may be set to about 0.5 to 1 μm, for example. The wiring line thickness of the wiring lines21S,21D,24S,24D,27S, and27D may be set to about 0.2 to 0.3 μm, for example. The wiring lines21S,21D,24S,24D,27S, and27D may be formed by use of sputtering or CVD.

On the pad electrode29, a protection film30is formed. In the protection film3, an opening portion30K is formed such that the pad electrode29is exposed therein. On the protection film30, a plate wiring34is formed through an under-barrier metal film33. The plate wiring34is connected to the pad electrode29through the opening portion30K. The plate wiring34may be designed to be larger than the wiring lines21S,21D,24S,24D,27S, and27D, in both of the wiring line width and the wiring line thickness. The plate wiring34may be arranged to be present across a plurality of wiring lines21S,21D,24S,24D,27S, and27D. In order to improve the heat dissipation of the DMOS transistors, the plate wiring34may be arranged to cover the DMOS transistors. The plate wiring34may be set such that each of the wiring line width and the wiring line thickness is ten or more times as large as that of the wiring lines21S,21D,24S,24D,27S, and27D. In this respect, the wiring line width of the plate wiring34may be set to 10 μm or more, and the wiring line thickness of the plate wiring34may be set to 5 μm or more. As the material of the under-barrier metal film33, for example, a two-layer structure formed of Ti/Cu may be used. The wiring lines21S,21D,24S,24D,27S, and27D may be used as the lower layer wirings HA shown inFIG. 2, (a). The plate wiring34may be used as the upper layer wiring HB shown inFIG. 2A.

Second Embodiment

FIG. 4is a plan view showing an example of an upper layer wiring layout applied to a semiconductor device according to a second embodiment.

As shown inFIG. 4, the in-corner portion of the upper layer wiring HB is formed with a round portion K2in place of the chamfer portion K1shown inFIG. 2B. As compared with a case where the in-corner portion of the upper layer wiring HB is set in 90° in designing the pattern, the round portion K2can reduce a stress at the in-corner portion. Here, in order to effectively reduce the stress at the in-corner portion, the rounding may be preferably set to 5 μm or more, and more preferably set to 20 μm or more.

FIG. 5Ais a view showing a thermal stress distribution at 250° C. in a case where the chamfer shape or round shape is changed, andFIG. 5Bis a view showing a thermal stress distribution at 390° C. in a case where the chamfer shape or round shape is changed. Here, as regardsFIG. 5AandFIG. 5B, a simulation was performed by use of a model having a five-layer structure formed of Si/PI/Cu/Ni/Au and including a pattern formed in the Ni/Au, to obtain a stress applied to the Ni. Further, inFIG. 5AandFIG. 5B, P1and P1′ indicate a case without any chamfering, P2and P2′ indicate a case with chamfering of 5 μm, P3and P3′ indicate a case with chamfering of 20 μm, P4and P4′ indicate a case with rounding of 5 μm, and P5and P5′ indicate a case with rounding of 20 μm. Here, the horizontal axis denotes a distance from the stress peak position.

As shown inFIG. 5AandFIG. 5B, the stress applied to the Ni is larger at 390° C. than at 250° C. With an increase in the chamfering or rounding, the stress is lowered. Since the rounding brings about no angles, it provides a larger effect of relaxing the stress, as compared with the chamfering. Accordingly, in designing the pattern, the in-corner portion of the upper layer wiring HB is preferably formed with rounding of 5 μm or more, and more preferably of 20 μm or more.