Systems and methods for non-volatile flip flops

A non-volatile flip flop integrated circuit includes a master latch circuit, a slave latch circuit coupled to the master latch circuit, and a non-volatile memory array coupled to the slave latch circuit. The non-volatile memory array includes a first pair of memory cells coupled to the slave latch circuit, and a second pair of memory cells coupled to the slave latch circuit in parallel with the first pair of memory cells. The first and second pair of memory cells are configured to store data from the slave latch circuit, and to restore data to the slave latch circuit.

BACKGROUND

Field

This disclosure relates generally to flip flop circuits, and more specifically, to non-volatile flip flop circuits.

Related Art

In current systems, data in flip flop circuits is retained by supplying auxiliary backup or back-bias voltage to a portion of the flip-flop circuitry. Instead of consuming power to retain flip flop data, it is desirable to provide non-volatile flip flop circuitry that operates efficiently and is practical to fabricate within process, voltage and temperature variations.

DETAILED DESCRIPTION

An array of non-volatile cells using programmable resistive elements is used to provide non-volatile master-slave flip flop circuitry. The array of non-volatile (NV) cells includes a number or rows, in which each row includes two NV cells, corresponding to the true data output and complementary data output of the slave latch. Each NV cell includes a programmable resistive element, which can be formed from carbon nanotubes. Compared to other programmable resistive elements, carbon nanotubes provide a greater resistance variation between a high resistive state (HRS) and a low resistive state (LRS). CNT devices also have low current requirements. Each row of NV cells stores the data corresponding to both the true and complementary outputs of the slave latch. The data in the slave latch can be stored to the NV memory cells, as needed, and restored back to the slave latch from the NV memory cells, as needed. During testing, if a row of the NV cells is found to be defective, the defective row of cells can be disabled. The use of multiple rows of NV cells for providing NV storage for each flip flop allows for boosting the read current for the restore operation and provides redundancy in the NV storage of the flip flop data.

FIG. 1is a block diagram of a NV flip flop system10in accordance with selected embodiments of the invention that includes flip flops (FFs)12,14, and16, and NV resistive memory cell arrays20and24, and store/restore circuitry18and22. Each flip flop has corresponding store/restore circuitry and an array of NV memory cells. InFIG. 1, store/restore circuitry22and NV array24corresponds to flip flop16. Store/restore circuitry18and NV array20include store/restore circuitry and an NV array corresponding to each of flip flops12and14. System10may include any number of flip flops, along with store/restore circuitry and an NV array for each flip flop. Each NV array for a corresponding flip flop includes an array of m rows, each including 2 NV bit cells. Therefore, each array includes 2*m NV bit cells to provide NV storage for the one flip flop. Each row is coupled to a corresponding row select (RS) line RS1-RSm. In the illustrated embodiment, the row select lines are shared among multiple NV arrays such that when a defective row is deselected, it is deselected in all NV arrays receiving the same row select lines.

FIG. 2is a schematic diagram of a portion of FF16, store/restore circuitry22, and NV array24ofFIG. 1. Also included inFIG. 2is clock control circuitry36(also referred to as clock circuitry) and RS line setting circuitry34. FF16includes a master portion30and a slave portion32. A select signal, sel, and an inverse of the select signal, sel*, a restore signal, res, and an inverse of the restore signal, res*, are provided to the circuitry ofFIG. 2. Clock control circuitry36receives a system clock, clk, and generates clock signals, clkf, clkf* (which is the inverse of clkf), clkq, and clkq* (which is the inverse of clkq). Clock control circuitry36includes NAND gates124and130and inverters126,128, and132. NAND gate124receives clk at a first input and sel* at a second input. An output of NAND gate124is coupled to an input of inverter126and a first input of NAND gate130. A second input of NAND gate130is coupled to receive res*. An output of NAND gate130provides clkq and is coupled to an input of inverter132, and an output of inverter132provides clkq*. An output of inverter126provides clkf and is coupled to an input of inverter128. An output of inverter128provides clkf*. Note that clkf* is an inverse of clkf, and clkq* is an inverse of clkq.

FF16includes a master portion30and a slave portion32. Master portion30includes inverters38,40, and42. An input of inverter38is coupled to receive the data input, d, of FF16. An enable input of tri-state inverter38receives clkf* and an inverting enable input receives clkf. An output of tri-state inverter40is coupled to an input of inverter42, and an output of tri-state inverter38. An output of inverter42is coupled to an input of tri-state inverter40. Enable inputs of tri-state inverter40receives clkf and inverting enable inputs receive clkf*. Note that tri-state inverter40and inverter42may be referred to as a master latch.

Slave portion32includes transmission gates48and50, inverters52and54, P-channel transistors44,56, and60, and N-channel transistors58,62, and46. An output of tri-state inverter38is coupled to a first terminal of transmission gate48and a second terminal of transmission gate38is coupled to an input of inverter52. The first terminal of transmission gate48receives the complementary input from the master latch, qp*. An enable input of transmission gate48receives clkf, and an inverting enable input receives clkf*. An output of inverter42is coupled to a first terminal of transmission gate50and a second terminal of transmission gate50is coupled to an input of inverter54. The first terminal of transmission gate50receives the true input from the master latch, qp. An enable input of transmission gate50receives clkf, and an inverting enable input receives clkf*. A first current electrode of transistor44is coupled to a first voltage supply node, such as Vdd. A control electrode of transistors44is coupled to receive clkq. A first current electrode of transistor56and a first current electrode of transistors60is coupled to a second current electrode of transistor44. A second current electrode of transistors56is coupled to a first current electrode of transistor58and control electrodes of transistors60and62. A second current electrode of transistor60is coupled to a first current electrode of transistor62and to control electrodes of transistors56and58. A second current electrode of transistors58and62are coupled to a first current electrode of transistor46. A control electrode of transistor46is coupled to receive clkq*, and second current electrode is coupled to a second voltage supply node, such as ground. Note that transistors56,58,60, and62form two inverters coupled to form a latch and may be referred to as a slave latch. The input of inverter52and the second terminal of transmission gate48may be referred to as a circuit node A, and the input of inverter54and the second terminal of transmission gate50may be referred to as a circuit node B.

Store/restore circuitry22includes transmission gates64and66, and P-channel transistors65,68,70, and72. A first terminal of transmission gate64is coupled to the input of inverter52at node A. A first terminal of transmission gate66is coupled to the input of inverter54at node B. A second terminal of transmission gate64is coupled to a bit line, BLleft, of NV array24, and a second terminal of transmission gate66is coupled to another bit line, BLright, of NV array24. A first current electrode of transistors65and70are coupled to the first voltage supply node. A first current electrode of transistor68is coupled to a second current electrode of transistor65, a second current electrode of transistor68is coupled to BLleft of array24, and a control electrode of transistors68is coupled to receive a bias voltage. A first current electrode of transistor72is coupled to a second current electrode of transistor70, a second current electrode of transistor72is coupled to BLright of array24, and a control electrode of transistor72is coupled to receive the bias voltage.

NV array24includes m rows of 2 NV bit cells each. (Note that NV bit cells may also be referred to as NV memory cells.) Row 1 includes a pair of NV bit cells, NV bit cell90and NV bit cell92, and row m includes a pair of NV bit cells, NV bit cell96and NV bit cell98. These pairs of NV bit cells are coupled in parallel to one another. Bit cell90is coupled to RS1and BLleft, bit cell96is coupled to RSm and BL left, bit cell92is coupled to BLright and RS1, and bit cell98is coupled to BLright and RSm. Bit cell90includes a programmable resistive element74and an N-channel transistor76(also referred to as an access transistor or pass transistor) in which a first terminal of programmable resistive element74is coupled to BLleft, a first current electrode of transistor76is coupled to a second terminal of programmable resistive element74, and a control electrode of transistor76is coupled to RS1. Bit cell92includes a programmable resistive element78and an N-channel transistor80(also referred to as an access transistor or pass transistor) in which a first terminal of programmable resistive element78is coupled to BLright, a first current electrode of transistor80is coupled to a second terminal of programmable resistive element78, and a control electrode of transistor80is coupled to RS1. Bit cell96includes a programmable resistive element82and an N-channel transistor84(also referred to as an access transistor or pass transistor) in which a first terminal of programmable resistive element82is coupled to BLleft, a first current electrode of transistor84is coupled to a second terminal of programmable resistive element82, and a control electrode of transistor84is coupled to RSm. Bit cell98includes a programmable resistive element86and an N-channel transistor88(also referred to as an access transistor or pass transistor) in which a first terminal of programmable resistive element86is coupled to BLright, a first current electrode of transistor88is coupled to a second terminal of programmable resistive element86, and a control electrode of transistor88is coupled to RSm. A second current electrode of the access transistors of the bit cells, such as transistor76,80,84, and88, are coupled to an output of an inverter100. An input of inverter100is coupled to an output of a NAND gate102which receives sel at a first input, res* at a second input, and clk at a third input.

Row select setting circuitry34provides an enable output to each row select line, RS1-RSm, based on a per row select signal, sel1*-selm*, and programmable resistors. (Note that sel1*-selm* are active low signals and are inverses of sel1-selm, respectively.) If the row select line is a logic level high, the corresponding row is enabled and if the row select line is a logic level low, the corresponding row is disabled. The row setting circuitry for RS1includes programmable resistors106,108,110, and112coupled in series between the first voltage supply node and the second voltage supply node and a NOR gate104having a first input which receives sel1* and a second input coupled to the node between resistors108and110. An output of NOR gate104provides RS1. Similarly, the row setting circuitry for RSm includes programmable resistors114,116,118, and120coupled in series between the first voltage supply node and the second voltage supply node and a NOR gate122having a first input which receives selm* and a second input coupled to the node between resistors116and118. An output of NOR gate122provides RSm. Each row select line may therefore have similar row setting circuitry. When a store or restore operation is occurring, one of sel1*-selm*, corresponding to the selected row, is asserted to a logic level low. Therefore, the output of the NOR gate, when the corresponding sel1*-selm* is a logic level low, is based on the settings of the resistors in series. Note that sel* is equivalent to a logical ANDing of each of sel*-selm*, and therefore, as will be discussed further below, during a store or restore operation, sel* is a logic level low (and sel is a logic level high).

The programmable resistors of circuitry34for each row can be programmed, as needed, to cause the output of the corresponding NOR gate to be a logic level high or low. In one embodiment, at test time, each row of NV bit cells can be tested, and if any row is determined to be defective, the resistors of the corresponding row setting circuitry can be programmed such that, when sel is high, the output of the NOR gate, and thus the corresponding row select line, is low. The row select line being low disables the corresponding row of NV bit cells. For example, referring to programmable resistors106,108,110, and112for RS1, if row 1 is found to be good and not defective, resistors108and106can be programmed to a high resistance and resistors110and112to a low resistance. That is, resistors106and108have an opposite polarity to resistors110and112. This results in enabling row 1 (with RS1being high) when sel1* is low. If, however, row 1 is found to be defective, resistors106and108can be programmed to a low resistance and resistors110and112to a high resistance. This results in disabling row 1 (with RS1being low) when sel1* is low. The error rate is generally low for the NV bit cells, meaning that ideally, at most only one row of rows 1-m will be disabled.

Operation ofFIG. 2will be described in reference to the timing diagrams ofFIGS. 3 and 4.FIG. 3illustrates a restore operation in accordance with one embodiment of the present invention, andFIG. 4illustrates a store operation in accordance with one embodiment of the present invention. As discussed above, a store operation from flip flop16to NV array24can be performed anytime there is a need to store the data of the flip flop in NV storage so the data can be maintained, such as for reduced power operation or a power down. A restore operation can be performed to restore the previously stored value from NV array24to flip flop16. In this manner, there can be provided a flip flop with NV storage capabilities. In the illustrated embodiment, each NV bit cell is implemented with a programmable resistive element which may be, for example, a carbon nanotube resistive element. When a sufficient current is provided in a first direction through the resistive element, the resistive element is programmed to a HRS (for example, 1 MOhm), and when a sufficient current is provided in a second and opposite direction through the resistive element, the resistive element is programmed to a LRS (for example, 200 KOhms). In the illustrated embodiment, it is assumed that a HRS corresponds to a logic level 1 and a LRS to a logic level 0. To read a state of the NV cell, a current is provided through the resistive elements (but not a current sufficient to change the state of the resistive element) resulting in a voltage drop over the resistive element. This voltage drop may then be sensed to determine the state.

Referring first toFIG. 2in which flip flop16is operating normally, sel is a logic level low and res* is also a logic level high. This turns off transmission gates64and66, thus decoupling store/restore circuitry22and array24from flip flop16. Also, the second input to logic gate124is a logic level one and the second input of logic gate130is a logic level one. Therefore, clkf=clkq, and flip flop16operates as a master slave flip flop, as known in art. During a first phase of the clock, data at data input d gets stored in the master latch and during the second phase of the clock, the data in the master latch gets transferred to the slave latch, which outputs the data as q or q* (the inverse of q). In the illustrated embodiment, the output of inverter52provides q and the output of inverter54provides q*.

Referring toFIGS. 2 and 3, it is assumed that each row in NV array24stores a logic level 1, which is the value that was previously stored from the slave latch of flip flop16. In this case, each programmable resistive element of array24coupled to BLleft was previously programmed during a store operation to a LRS and each programmable resistive element of array24coupled to BLright was previously programmed during the store operation to a HRS. Note that at this time, the programmable resistors of row setting circuitry34have be previously programmed to the desired state to enable or disable the corresponding row select line.

At time t0, it is assumed that system10is in a low power state. Therefore, at this time, clk, clkq, and clkf are off, and in a low state, sel is low and res* is high. The output of flip flop q is an indeterminate state. A restore operation begins at time t1, in which sel is set to a logic level high and res* to a logic level 0. Also, clkq goes high due to NAND gate130and turns off transistors44and46in slave portion32With sel set high, the NOR gates of row select setting circuitry34enables or disables each row select line of array24accordingly. In the example ofFIG. 3, the value of RS1is provided. However, the value of any enabled row select line of array24would match the values of RS1. Since RS1is enabled, it is a logic level high.

During the restore, the bias voltage is first applied to the control electrodes of transistors68and72. Also, transmission gates48and50are off, tri-state inverter40is disabled, and transmission gates64and66are high such that node A communicates with BLleft and node B with BLright. Transistors65and70are turned on and the second current electrodes (the source terminals in this case) of transistors76and80are coupled to ground (i.e. set to 0). As a result of the bias voltage, transistors68and72provide known currents down through resistive elements74and78, respectively. The current through programmable resistive element74results in a voltage drop, and the current through programmable resistive element78results in a voltage drop. Since in the current example, resistive element78is in a HRS and resistive element74in a LRS, the voltage drop over resistive element78is higher. The voltage drop over resistive element74, via transmission gate64, appears on node A of the slave latch, and the voltage drop over resistive element78(which is programmed to the opposite state of resistive element74) appears, via transmission gate66, at node B of the slave latch.

In NV array24, there are multiple rows (the enabled rows of row 1-row m) coupled to BLleft and BLright. In this example, the programmable resistive element of each row that is coupled to BLright is in a HRS, and the programmable resistive element of each row that is coupled to BLleft is in a LRS. Therefore, all of these receive the current from transistors72and68, respectively, and all result in a corresponding voltage drop. Thus, the restore is performed in parallel by all the enabled row lines. The AND configuration of all the NV cells along each bit line allows for boosting the current for the restore operation. From time t1to time t2, while the bias voltage is being applied, nodes A and B are being placed at their appropriate levels by all enabled rows of array24. Node A, which started at Vdd/2 at time t0, is pulled to close to0V and node B, which started at Vdd at time t0, is pulled to Vdd/2. Therefore, at time t2, sel is set to a logic level low and res* to a logic level high which turns off transistors66and70and transmission gates64and66. At this point, nodes A and B are set as needed to complete the restore operation, and thus the values at nodes A and B get latched into the slave latch of flip flop16. This restores the state of flip flop16and the output q is set to a logic level high again. Normal operation then commences. At time t3, clk is again enabled, such that clk, clkf, and clkq operate normally for flip flop16, in which clkf=clkq.

Referring toFIG. 4, a store operation is performed in which a logic level one is stored in flip flop16at the time of the store operation. At time t0to time t1, flip flop16operates normally in which clkf=clkq, sel is a logic level low, and res* is a logic level high, as was discussed above in reference toFIG. 3. At time t1, clkf and clkq are disabled and thus placed at a logic level low, but clk remains enabled. At time t2, after clkf and clkq are disabled, thus disabling the master latch and turning off transmission gates48and50, the store operation commences.

The store operation is performed serially for each row of NV array24. This helps minimize the write current being supplied by the slave latch of flip flop16. The example ofFIG. 4is performing a store operation to row 1. During the store, transistors44and46are turned on by clkq, sel and res* are high, and the enabled row select line for the current row, RS1, goes high. Also, during the store, transmission gates64and66are turned on, thus communicating nodes A and B with BLleft and BLright, respectively. Since in the current example flip flop16was storing a logic level one, node A, and thus BLleft, is at a logic level low and node B, and thus BLright, is at a logic level high.

To use the values at nodes A and B to program the programmable resistive elements of array24, the second current electrodes (the source terminals) of the access transistors along the current row are pulsed between a logic level high and logic level low to run current in the appropriate directions through the programmable resistive elements. For example, at time t3, the clk signal causes the output of inverter100to be a logic level high, thus setting the second current electrodes (i.e. source terminals) of transistors76and80to Vdd. Since node A is a logic level 0, this results in current flowing up through programmable resistive element74coupled to BLleft, thus programming it to a LRS. Since node B is a logic level 1, no or little current flows up through programmable resistive element78coupled to BLright. At time t4, clk goes low which causes the output of inverter100to be a logic level low, thus setting the second current electrodes of transistors76and80to ground. Since node B is a logic level 1, this results in current flow down through programmable resistive element78coupled to BLright, thus programming it to a HRS. Since node A is a logic level 0, no or little current flows down through programmable resistive element74coupled to BLleft.

As illustrated in the example ofFIG. 4, after a single pulse of the source terminals for achieving each resistive state (such as pulse140for achieving the LRS and pulse142for achieving the HRS), resistive elements74and78are correctly placed in their desired respective states. Programmable resistive element74is set to the LRS before time t4, and programmable resistive element78is set to HRS before time t5. However, multiple pulses are illustrated, and in some embodiments, multiple pulses are needed to fully program the resistive elements of a selected row. After a predetermined number of pulses for each state (which can be one or more pulses), the store operation for the current row is complete. Therefore, in the illustrated embodiment, at time t5, the store operation for RS1is complete, and sel and RS1are set low again.

After the store operation for row 1 is complete, a store operation is performed for each remaining enabled row select line of NV array24. The store operations can be performed in the same manner as was described for row 1. After a store operation has been performed for all enabled row select lines, the store operation is complete and the logic state of flip flop16has been transferred to each row of NV array24. At this point, power can be safely reduced or removed, since the state of flip flop16is saved in NV array24.

By now, it can be appreciated how an array of NV bit cells can be used to provide NV storage for each flip flop within a data processing system. By using carbon nanotubes for the programmable resistive elements, a greater resistance variation can be achieve between a HRS and a LRS. CNT devices also have low current requirements, thus minimizing power for the NV storage. The use of multiple rows of NV bit cells to backup each flip flop allows for a boost in the read current for the restore operation and provides redundancy in the NV storage. Also, through this use of multiple rows, a defective row can be disabled without losing functionality.

Because the apparatus implementing the present disclosure is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present disclosure and in order not to obfuscate or distract from the teachings of the present disclosure.

The following are embodiments of the present invention.

In one embodiment, a non-volatile flip-flop integrated circuit includes a master latch; a slave latch coupled to the master latch and configured to store a copy of data in the master latch; a first pair of non-volatile memory cells coupled to the slave latch; a second pair of non-volatile memory cell coupled to the slave latch and the first pair of non-volatile memory cells; and store/restore circuitry, coupled to first and second bit lines between the slave latch and the first and second pairs of non-volatile memory cells, and configured to couple the first and second pairs of memory cells to the slave latch circuit to store data from the slave latch to the first and second pairs of non-volatile memory cells, and to restore data from the first and second pairs of non-volatile memory cells to the slave latch. In one aspect of the above embodiment, the integrated circuitry further includes a first row select line coupled to a control gate of a pass transistor in each of the first pair of non-volatile memory cells; a second row select line coupled to a control gate of a pass transistor in each of the second pair of non-volatile memory cells. In another aspect, the first and second pair of non-volatile memory cells include carbon nanotube elements configured to store the data from the slave latch. In another aspect, the integrated circuitry further includes a source circuit coupled to a source electrode of an N-channel pass transistor in each of the first and second pairs of non-volatile memory cells, wherein an output of the source circuit is high when a select signal is asserted, a restore signal is not asserted, and a clock signal is high. In a further aspect, the first and second pairs of non-volatile memory cells are coupled in parallel to one another. In yet a further aspect, each non-volatile memory cell in the first and second pairs of non-volatile memory cells includes a non-volatile programmable storage element with a first terminal coupled to the first bit line and a second terminal coupled to a drain electrode of the N-channel pass transistor. In another aspect, the store/restore circuitry includes a first transmission gate including a first terminal coupled to a first data node of the slave latch and a second terminal coupled to the first bit line; a first P-channel transistor including a source electrode coupled to a supply voltage, a drain electrode, and a control gate coupled to a complement of a restore signal; a second P-channel transistor including a source electrode coupled to the drain electrode of the first P-channel transistor, a drain electrode coupled to the first bit line, and a control gate coupled to a bias signal; a second transmission gate including a first terminal coupled to a second data node of the slave latch and a second terminal coupled to the second bit line; a third P-channel transistor including a source electrode coupled to the supply voltage, a drain electrode, and a control gate coupled to a complement of a restore signal; a fourth P-channel transistor including a source electrode coupled to the drain electrode of the third P-channel transistor, a drain electrode coupled to the second bit line, and a control gate coupled to the bias signal. In a further aspect, the integrated circuitry further includes row select circuitry coupled to the first and second row select lines, the row select circuitry including: a first set of resistive elements coupled in series between a first supply voltage and a second supply voltage, a first logic gate including a first input coupled between a first and second of the first set of resistive elements, a second input coupled to a complement of a select signal, and an output coupled to the first row select line; a second set of resistive elements coupled in series between the first supply voltage and the second supply voltage, a second logic gate including a first input coupled between a first and second of the second set of resistive elements, a second input coupled to a complement of a select signal, and an output coupled to the second row select line. In yet another aspect of the above embodiment, the integrated circuitry further includes clock circuitry configured to generate first and second clock signals, wherein the first and second clock signals alternate between first and second values during normal operation when the slave latch stores data from the master latch, and the first clock signal is at a constant first value and the second clock signal is at a constant second value when data from the first or second pair of non-volatile memory cells is restored to the slave latch. In a further aspect, the integrated circuitry further includes row select circuitry including a first set of resistive elements coupled in series, and a second set of resistive elements coupled in series with opposite polarity as the first set of resistor elements; and a logic gate including a first input coupled between the first and second sets of resistive elements and an output coupled to the first row select line.

In another embodiment, a method of operating a slave latch circuit coupled to a master latch and non-volatile memory includes during normal operation: copying data from the master latch to the slave latch; during a restore operation: coupling first and second pairs of non-volatile memory cells to the slave latch circuit; transferring data from the first and second pairs of non-volatile memory cells to the slave latch circuit, wherein the first and second pairs of non-volatile memory cells are coupled in parallel with one another; decoupling the first and second pairs of non-volatile memory cells from the slave latch circuit after the data is transferred from the first and second pairs of non-volatile memory cells to the slave latch circuit; during a store operation: coupling the first and second pairs of non-volatile memory cells to the slave latch circuit; transferring data from the slave latch to the first and second pairs of non-volatile memory cells; decoupling the first and second pairs of non-volatile memory cells from the slave latch circuit after the data is transferred from the latch circuit to the first and second pairs of non-volatile memory cells. In one aspect of the above another embodiment, the method further includes generating a first clock signal for the slave latch circuit that is a first constant value during the store and restore operations, and alternates between high and low values during normal operation; generating a second clock signal for the slave latch circuit that is a second constant value during the restore operation, the first value during the store operation, and alternates between the high and low values during normal operation. In another aspect, the method further includes coupling the slave latch circuit to the first and second pairs of non-volatile memory cells via first and second transmission gates, wherein the first transmission gate includes a first terminal coupled to a first data node of the slave latch circuit and a second terminal coupled to a first bit line, and the second transmission gate includes a first terminal coupled to a second data node of the slave latch circuit and a second terminal coupled to a second bit line. In a further aspect, the method further includes during the restore and store operations: providing a first row select signal to a row select line coupled to a gate electrode of a pass transistor in each of the memory cells of the first pair of non-volatile memory cells; and providing a second row select signal to a row select line coupled to a gate electrode of a pass transistor in each of the memory cells of the second pair of non-volatile memory cells. In another further aspect, the method further includes during the store operation: coupling source electrodes of N-channel pass transistors in each of the memory cells of the first and second pairs of non-volatile memory cells to a source signal at high voltage. In another aspect, the method further includes detecting operational status of the memory cells of the first and second pairs of non-volatile memory cells and storing indicators of the operational status of the first and second pairs of non-volatile memory cells. In yet another aspect, the method further includes boosting read current for the restore operation with the first and second pairs of non-volatile memory cells coupled in parallel with one another.

In yet another embodiment, a non-volatile flip flop integrated circuit includes a master latch circuit; a slave latch circuit coupled to the master latch circuit; a non-volatile memory array coupled to the slave latch circuit, where the non-volatile memory array includes: a first pair of memory cells coupled to the slave latch circuit; a second pair of memory cells coupled to the slave latch circuit in parallel with the first pair of memory cells, wherein the first and second pair of memory cells are configured to store data from the slave latch circuit, and to restore data to the slave latch circuit. In one aspect of the above yet another embodiment, the integrated circuitry further includes a store/restore circuit coupled between the first and second pairs of memory cells and the slave latch circuit, wherein the store/restore circuit includes: a first transmission gate having a first terminal coupled to the slave latch circuit, a second terminal coupled to a first bit line; a first P-channel transistor including a source electrode coupled to a supply voltage, a drain electrode, and a gate electrode coupled to a complement of a restore signal; a second P-channel transistor including a source electrode coupled to the drain electrode of the first P-channel transistor, a drain electrode coupled to the first bit line, and a gate electrode coupled to a bias signal; a second transmission gate having a first terminal coupled to the slave latch circuit, a second terminal coupled to a second bit line; a third P-channel transistor including a source electrode coupled to the supply voltage, a drain electrode, and a gate electrode coupled to the complement of the restore signal; a fourth P-channel transistor including a source electrode coupled to the drain electrode of the third P-channel transistor, a drain electrode coupled to the second bit line, and a gate electrode coupled to the bias signal. In another aspect, the non-volatile memory array includes a first carbon nanotube resistor including a first terminal coupled to the first bit line and a second terminal coupled to a drain electrode of a first N-channel transistor, the first N-channel transistor further having a source electrode coupled to a source voltage and a gate electrode coupled to a first restore/store signal; a second carbon nanotube resistor including a first terminal coupled to the first bit line and a second terminal coupled to a drain electrode of a second N-channel transistor, the second N-channel transistor further having a source electrode coupled to the source voltage and a gate electrode coupled to a second restore/store signal; a third carbon nanotube resistor including a first terminal coupled to the second bit line and a second terminal coupled to a drain electrode of a third N-channel transistor, the third N-channel transistor further having a source electrode coupled to the source voltage and a gate electrode coupled to the first restore/store signal; a fourth carbon nanotube resistor including a first terminal coupled to the second bit line and a second terminal coupled to a drain electrode of a fourth N-channel transistor, the fourth N-channel transistor further having a source electrode coupled to the source voltage and a gate electrode coupled to the second restore/store signal.