Programmable filter

In several embodiments of the invention, a programmable architecture for FIR filters includes a tapped delay chain and a number of different slices. Each slice has a multiplexer that receives all of the tapped input-signal samples and a programmable current driver. Each slice can be independently programmed to correspond to any one of the taps in the delay chain, such that zero, one, or more slices can be associated with any of the delay-chain taps. Moreover, the current driver in each slice can be independently programmed to contribute any available driver strength level for the selected tap, where the combination of one or more drive strengths associated with a given tap corresponds to the effective tap coefficient for that tap. In this way, the architecture can be programmed to provide a variety of different filters having not just transfer functions with different coefficient values, but also transfer functions having different numbers of pre-cursor and/or post-cursor taps.

BACKGROUND

1. Field of the Invention

The present invention relates to electronics and, more specifically, to filters such as finite impulse response (FIR) filters.

2. Description of the Related Art

FIG. 1shows a schematic block diagram of a typical implementation of a generic, conventional finite impulse response (FIR) filter100that converts an input, serial bitstream102into a filtered, output signal110. The z-domain transfer function H(z) for a discrete-time implementation of FIR filter100is given by the following equation:
H(z)=Y(z)/X(z)=c−m*z−m+ . . . +c−1*z−1+c0+c1*z1+ . . . +cn*zn,
where X(z) is the z-domain input signal102, Y(z) is the z-domain output signal110, c0is the current tap coefficient; c−1, . . . , c−mare the m pre-cursor tap coefficients; and c1, . . . , cnare the n post-cursor tap coefficients. The number m of pre-cursor tap coefficients and the number n of post-cursor tap coefficients will depend on the desired filter characteristics. Note that, depending on the particular filter transfer function, either m or n could be, but do not have to be, zero.

As shown inFIG. 1, the input bitstream102is sequentially delayed by a delay chain consisting of (m+n) delays104. The corresponding delayed 1-bit samples are multiplied by corresponding tap coefficient values c−m, . . . , cnat multipliers106, and the resulting weighted samples are combined at summation node108to generate the filtered, output signal110.

An integrated circuit may need to be able to apply different FIR filters having different transfer functions with different numbers of pre-cursor and/or post-cursor taps to a data stream at different times. For example, for some communications applications, pre-de-emphasis filtering is applied to compensate for losses due to transmit channel characteristics. For such applications, it is desirable to implement transmit drivers having flexible FIR filters to compensate for different channel characteristics.

One conventional solution is to implement the integrated circuit with multiple FIR filters, each one having a different configuration of pre-cursor and post-cursor taps. Another conventional solution is to implement the integrated circuit with a single FIR filter having the maximum number of pre-cursor taps for any supported transfer function and the maximum number of post-cursor taps for any supported transfer function so that any of the different supported transfer functions can be implemented by assigning coefficient values of zero to any taps that are not needed for a particular FIR filter. These conventional solutions are not optimally efficient.

DETAILED DESCRIPTION

FIG. 2shows a schematic block diagram of an exemplary three-tap FIR filter200of the disclosure having one pre-cursor tap, one current tap, and one post-cursor tap. Like FIR filter100ofFIG. 1, FIR filter200converts an input bitstream202into a filtered output signal210. Although FIR filter200appears to have an architecture similar to that of prior-art FIR filter100ofFIG. 1, with delays204and multipliers204, as explained below, FIR filter200is implemented very differently from FIR filter100.

FIG. 3shows a schematic block diagram of one possible implementation of FIR filter200ofFIG. 2. As described further below, FIR filter200can implement transfer functions having any combination of (i) zero or one pre-cursor tap, (ii) zero or one current tap, and (iii) zero or one post-cursor tap. In theory, the architecture of FIR filter200can be extended to provide FIR filters of the present disclosure that can implement transfer functions having any combination of (i) zero up to any suitable maximum number of pre-cursor taps, (ii) zero or one current tap, and (iii) zero up to any suitable maximum number of post-cursor taps.

FIR filter200has a delay chain310consisting of the two delays204ofFIG. 2and three taps: one pre-cursor tap312, one current tap314, and one post-cursor tap316. Delay chain310receives the input, serial bitstream202and provides three sample values pre, cur, and post. In one possible implementation, each delay204applies a delay of one unit interval (UI). In other possible implementations, each delay204applies a delay other than one UI, such as ½ UI or two or more UIs. In some implementations, the magnitude of the delay is programmable.

As shown inFIG. 3, FIR filter200has a set of six slices320(0)-320(5), each slice320(i) having a 3:1 multiplexer (mux)322(i) and a programmable current driver324(i). In addition, FIR filter200has summation node208, which combines the outputs from the six slices320to generate the filtered output signal210.

As shown inFIG. 3, each mux322(i) (i) receives the three tapped samples pre, cur, and post from the three taps312,314, and316, respectively, of delay chain310and (ii) selects one of those three samples based on a 2-bit control signal3210. The selected sample3230is then applied to programmable current driver324(i). Note that, in this exemplary implementation, current drivers324(0) and324(1) each can be independently programmed to drive at any drive strength from a minimum of 0.1 mA to a maximum of 0.8 mA, in eight 0.1 mA increments, while current drivers324(2)-324(5) each can be independently programmed to drive at any drive strength from a minimum of 0.8 mA to a maximum of 3.2 mA in four 0.8 mA increments. Other implementations may have other current drivers that operate with different maximum currents and/or different increments.

Each slice320(i) is independently programmable with regard to both (i) the selection by mux322(i) and (ii) the drive strength of current driver324(i). As such, zero, one, two, or more slices320can be programmed (i.e., configured) to select the pre-cursor sample pre. Similarly, zero, one, two, or more of the remaining slices320, if any, can be programmed to select the current sample cur. And, lastly, zero, one, two, or more of the remaining slices320, if any, can be programmed to select the post-cursor sample post. Moreover, each current driver3240can be independently programmed to any of its available drive strengths.

In this way, FIR filter200can be programmed to implement a variety of different transfer functions consisting of any combination of one, two, or all three of the tapped data samples pre, cur, and post. For example, FIR filter200can be programmed to implement the following transfer function:
H1(z)=c−1*z−1+c0+c1*z1,
where each tap coefficient cicorresponds to the sum of the programmed drive strengths of the different current drivers324selected for that tap. Note that FIR filter200can also be programmed to implement either of the following two transfer functions:
H2(z)=c−1*z−1+c0
H3(z)=c0+c1*z1
For example, for transfer function H2(z), none of the muxes322would be programmed to select the tap value post. Similarly, for transfer function H3(z), none of the muxes322would be programmed to select the tap value pre. In theory, FIR filter200can be programmed to support other transfer functions (e.g., single-tap transfer functions and transfer functions without a current tap) even if those transfer functions might not necessarily be useful.

Note further that all six slices320do not have to be used for every transfer function. Any slices320that are not needed for a particular transfer function can be turned off, thereby avoiding unnecessary power consumption.

FIG. 4shows a schematic block diagram illustrating slice320(i) for a differential implementation of FIR filter200ofFIGS. 2 and 3, in which the input bitstream202and the filtered output signal210are both differential signals comprising complementary positive and negative components.

As shown inFIG. 4, current driver3240is implemented using a differential amplifier404(i) connected between a programmable current source402(i) and a programmable current sink406(i), where each programmable current source/sink can be programmed at a specified current level CSi corresponding to the desired drive strength for that current driver. Although not shown inFIG. 4, current drivers324(0) and324(1) ofFIG. 3each receive a dedicated 3-bit control signal that selects one of the eight different available drive strengths from 0.1 mA to 0.8 mA at 0.1 mA increments, while current drivers324(2)-324(5) ofFIG. 3each receive a dedicated 2-bit control signal that selects one of the four different available drive strengths from 0.8 mA to 3.2 mA in 0.8 mA increments.

As shown inFIG. 4, (6×2) mux3220receives three pairs of tapped, complementary samples: (i) pre_p and pre_n from tap312ofFIG. 3, cur_p and cur_n from tap314, and post_p and post_n from tap316and selects one of those three pairs based on 2-bit control signal321(i). Differential amplifier404(i) receives the selected pair of complementary samples selp and seln from mux322(i) and generates the corresponding amplified, complementary output signals hdoutp and hdoutn (aka filtered signal components) based on the programmed drive current CSi applied by the source and sink current drivers402(i) and406(i). Although not show inFIG. 4, those two amplified, complementary output signals hdoutp and hdoutn are combined at summation node208ofFIGS. 2 and 3with up to five other pairs of amplified, complementary output signals from the other slices320of FIR filter200to generate the complementary output signal210.

FIG. 5shows a schematic circuit diagram of a transconductance amplifier500that can be used to implement differential amplifier404(i) ofFIG. 4. Amplifier500has four tri-stated switches, where each tri-stated switch comprises a tri-state buffer (e.g., T1), a pull-up/pull-down cell (e.g., P3/N3), and an MOS switch transistor (e.g., P1).

FIG. 6shows a schematic circuit diagram of a tri-state buffer600, instances of which can be used to implement each of tri-state buffers T1-T4ofFIG. 5. Tri-state buffer600is enabled by setting enable signal en high (i.e., logic 1) and complementary enable signal enb low (i.e., logic 0). With tri-state buffer600enabled, when input signal in is high, the output from NAND gate602is low and the output from NOR gate604is low, which turns on PMOS606and turns off NMOS608, which drives output signal out high. With tri-state buffer600enabled, when input signal in is low, the output from NAND gate602is high and the output from NOR gate604is high, which turns off PMOS606and turns on NMOS608, which drives output signal out low.

Tri-state buffer600is disabled by setting enable signal en low and complementary enable signal enb high. With tri-state buffer600disabled, when input signal in is high, the output from NAND gate602is high and the output from NOR gate604is low, which turns off both PMOS606and NMOS608, which leaves output signal out indeterminate. With tri-state buffer600disabled, when input signal in is low, the output from NAND gate602is again high and the output from NOR gate604is again low, which again turns off both PMOS606and NMOS608, which again leaves output signal out indeterminate.

Thus, when tri-state buffer600is enabled, output signal out matches input signal in, and, when tri-state buffer600is disabled, output signal out is indeterminate independent of the value of input signal in.

To enable slice320(i) ofFIG. 4, (i) the four tri-state buffers T1-T4ofFIG. 5are all enabled (i.e., by setting en=1 and enb=0) as described above in reference toFIG. 6and (ii) the four pull-up/pull-down cells are all disabled by setting sel_slice=1. Setting sel_slice=1, ensures that p-type transistors P3and P5are off and that n-type transistors N4and N6are also off. Since the gates of n-type transistors N3and N5are permanently connected to VSS, and the gates of p-type transistors P4and P6are permanently connected to VCC, those four transistors will always be off. In that case, the selected sample selp will be applied to the gates of P1and N1as selp_pmos and selp_nmos, respectively, and the complementary selected sample seln will be applied to the gates of P2and N2as seln_pmos and seln_nmos, respectively.

With all of the tri-state buffers T1-T4enabled and all of the pull-up/pull-down cells disabled, when (i) the selected sample selp is high and (ii) the complementary selected sample seln is low, then (iii) selp_pmos and selp_nmos are high, (iv) seln_pmos and seln_nmos are low, (v) p-type transistor P2and n-type transistor N1are on, (vi) p-type transistor P1and n-type transistor N2are off, (vii) output component hdoutp is driven high at the selected drive strength CSi, and (viii) complementary output component hdoutn is driven low at the selected drive strength CSi. Alternatively, with all of the tri-state buffers T1-T4enabled and all of the pull-up/pull-down cells disabled, when (i) selp is low and (ii) seln is high, then (iii) selp_pmos and selp_nmos are low, (iv) seln_pmos and seln_nmos are high, (v) P2and N1are off, (vi) P1and N2are on, (vii) hdoutp is driven low at the selected drive strength CSi, and (viii) hdoutn is driven high at the selected drive strength CSi.

To disable slice320(i) ofFIG. 4, (i) the four tri-state buffers T1-T4ofFIG. 5are all disabled (i.e., by setting en=0 and enb=1) as described above in reference toFIG. 6and (ii) the four pull-up/pull-down cells are all enabled by setting sel_slice=0. Setting sel_slice=1 turns on transistors P3and P5as well as transistors N4and N6are also off. In that case, selp_pmos and seln_pmos will both be driven high, and selp_nmos and seln_nmos will both be driven low (independent of the values of selp and seln), thereby ensuring that transistors P1, N1, P2, and N2will all be off, and that the slice320(i) will be powered down and not draw any current.

The configuration shown inFIG. 5corresponds to a positive tap coefficient value. The selp and seln inputs can be swapped to achieve a negative tap coefficient value having the same magnitude.

Referring again toFIG. 4, if slice320(i) is not needed for a particular transfer function, then the two-bit mux control signal3210is set to the unused value (e.g., 00) to turn off and power down both mux322(i) and current driver3240. Note that the mux control signal321(i) can be used to generate the control signals sel_slice ofFIG. 5and en and enb ofFIG. 6using appropriate control logic.

FIG. 7shows transconductance amplifiers for three slices320(0)-320(2) implemented in a single circuit. Note that the three slices share the same load, thereby saving power. Although not explicitly shown inFIG. 7, each transistor P1(0)-P1(2), N1(0)-N1(2), P2(0)-P2(2), N2(0)-N2(2) is driven by a tri-state buffer with a pull-up/pull-down cell (as appropriate) as inFIG. 5to turn on and off independently the different slices. When a slice is not used, it does not add to the load of the other used slices. This implies that the pre-driver needed to drive these slices can be smaller, thereby saving power.

Although the present invention has been described in the context of FIR filter200ofFIGS. 2 and 3, which can implement transfer functions having up to one pre-cursor tap and up to one post-cursor tap in addition to the current tap, the invention is not so limited. In theory, the present invention can be extrapolated to implement FIR filters having any suitable maximum number of pre-cursor taps and any suitable maximum number of post-cursor taps by:Implementing a delay chain having an appropriate number of delay elements and taps;Changing the number of slices; andChanging the mux ratio for each slice's mux to be based on the total number of taps.
In addition, the variety of different tap coefficient values (i.e., drive current levels) that can be supported by the FIR filters can be changed by implementing suitable programmable current drivers that can be combined to provide those different coefficient values.

FIR filters of this disclosure can provide one or more of the following advantages. By creating a common set of drivers that can be used for any tap (pre, cur, and post), this architecture can utilize less area and less power than prior-art solutions, thereby eliminating the need for dedicated pre-cursor and post-cursor tap drivers. Further, this architecture enables more flexibility when choosing the values for the pre-cursor, current, and post-cursor taps, because all drivers are available to any tap. The modularity of the architecture enables easy insertion or deletion of taps for future products. Using multiple drivers for the same tap enables slew-rate change without affecting the voltage levels of the signal. This architecture can save power by allowing drivers to be turned off completely when not in use.

The unspecified nature of the slices allows them to be used for other pairings. For example, although FIR filter200ofFIGS. 2 and 3has been characterized as having one pre-cursor tap, one current tap, and one post-cursor tap, that same configuration can be programmed to function (i) as two pre-cursor taps and one current tap or (ii) as one current tap and two post-cursor taps.

Although embodiments have been described in the context of programmable current drivers, other embodiments may be based on other programmable drivers, such as programmable voltage drivers

Also, for purposes of this disclosure, it is understood that all gates are powered from a fixed-voltage power domain (or domains) and ground unless shown otherwise. Accordingly, all digital signals generally have voltages that range from approximately ground potential to that of one of the power domains and transition (slew) quickly. However and unless stated otherwise, ground may be considered a power source having a voltage of approximately zero volts, and a power source having any desired voltage may be substituted for ground. Therefore, all gates may be powered by at least two power sources, with the attendant digital signals therefrom having voltages that range between the approximate voltages of the power sources.

Signals and corresponding nodes, ports, or paths may be referred to by the same name and are interchangeable for purposes here.

Transistors are typically shown as single devices for illustrative purposes. However, it is understood by those with skill in the art that transistors will have various sizes (e.g., gate width and length) and characteristics (e.g., threshold voltage, gain, etc.) and may consist of multiple transistors coupled in parallel to get desired electrical characteristics from the combination. Further, the illustrated transistors may be composite transistors.

As used in this specification and claims, the term “channel node” refers generically to either the source or drain of a metal-oxide semiconductor (MOS) transistor device (also referred to as a MOSFET), the term “channel” refers to the path through the device between the source and the drain, and the term “control node” refers generically to the gate of the MOSFET. Similarly, as used in the claims, the terms “source,” “drain,” and “gate” should be understood to refer either to the source, drain, and gate of a MOSFET or to the emitter, collector, and base of a bi-polar device when an embodiment of the invention is implemented using bi-polar transistor technology.

It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain embodiments of this invention may be made by those skilled in the art without departing from embodiments of the invention encompassed by the following claims.