Semiconductor device and method of manufacture

A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.

BACKGROUND

As semiconductor technologies further advance, stacked and bonded semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits and the like are fabricated at least partially on separate substrates and then physically and electrically bonded together in order to form a functional device. Such bonding processes utilize sophisticated techniques, and improvements are desired.

DETAILED DESCRIPTION

FIGS. 1-7illustrate the formation of an embodiment of a first interconnect structure711and a second interconnect structure713. In some embodiments, the first interconnect structure711and a second interconnect structure713may be an embedded dual side IPD (eDS-IPD). With reference now toFIG. 1, there is shown a first substrate101, integrated passive devices (IPDs)103, and a first metallization layer105. The first substrate101may comprise bulk silicon, doped or undoped, a silicon-on-insulator (SOI) substrate, silicon dioxide (SiO2) or other insulating material, or another material. The IPDs103may comprise a wide variety of passive devices such as capacitors, resistors, inductors and the like. In the embodiments shown inFIG. 1-7, the IPDs103are shown as deep-trench capacitors, though in other embodiments the IPDs103may comprise one or more other types of passive devices as described above.

The IPDs103may be formed using any suitable methods either within or else on the first substrate101. For example, a deep-trench capacitor may be formed by first forming trenches into the first substrate101. The trenches may be formed by any suitable photolithographic mask and etching process. For example, a photoresist may be formed and patterned over the first substrate101, and one or more etching processes (e.g., a dry etch process) may be utilized to remove those portions of the first substrate101where the deep-trench capacitors are desired. A first capacitor electrode may be formed by forming a first conductive electrode material into a trench, such as through a deposition process or another process. The first conductive electrode material may be a conductive material such as doped silicon, polysilicon, copper, tungsten, an aluminum or copper alloy, or another conductive material. A dielectric layer may be formed over the first conductive electrode material within the trench. The dielectric layer may comprise high-K dielectric materials, an oxide, a nitride, or the like, or combinations or multiple layers thereof, and be formed using any suitable deposition process, such as a CVD process. A second conductive electrode material may be formed over the dielectric layer in the trench to form a second capacitor electrode, such as through a deposition process or another process. The second conductive electrode material may be a conductive material such as doped silicon, polysilicon, copper, tungsten, an aluminum or copper alloy, or another conductive material. As one of ordinary skill in the art will recognize, the above described process for forming deep-trench capacitors is merely one method of forming the deep-trench capacitors, and other methods are also fully intended to be included within the scope of the embodiments.

Returning toFIG. 1, the first metallization layer105is formed over the first substrate101and is designed to connect the various IPDs103. In an embodiment the first metallization layer105comprises one or more layers of dielectric and conductive material and may be formed through any suitable process (such as a suitable photolithographic mask and etching process, deposition, damascene, dual damascene, etc.). The conductive material in the first metallization layer105may comprise a conductive material such as copper, although other conductive materials, such as tungsten, aluminum or copper alloy, or the like may be used.

FIG. 2illustrates the formation of through-substrate-vias (TSVs)201in the first substrate101. The TSVs201may be formed, for example, by etching openings into the first metallization layer105and the first substrate101and then depositing a conductive material203into the openings. Openings into the first metallization layer105and the first substrate101may be formed using a suitable photolithographic mask and etching process. For example, a photoresist may be formed and patterned over the first metallization layer105, and one or more etching processes (e.g., a wet etch process or a dry etch process) are utilized to remove those portions of the first metallization layer105and the first substrate101where the TSVs201are desired.

Once the openings for the TSVs201have been formed, the openings for the TSVs201may be filled with, e.g., a barrier layer205and the conductive material203. The barrier layer205may comprise a conductive material such as titanium nitride, although other materials, such as tantalum nitride, titanium, a dielectric, or the like may be utilized. The barrier layer205may be formed using a CVD process, such as PECVD. However, other alternative processes, such as sputtering or metal organic chemical vapor deposition (MOCVD), may be used. The barrier layer205may be formed so as to contour to the underlying shape of the opening for the TSVs201.

The conductive material203may comprise one or more conductive materials, such as copper, tungsten, other conductive metals, or the like. The conductive material203may be formed, for example, by depositing a seed layer (not separately illustrated) and using electroplating, electroless plating, or the like to deposit conductive material onto the seed layer, filling and overfilling the openings for the TSVs201. Once the openings for the TSVs201have been filled, excess barrier layer205and excess conductive material203outside of the openings for the TSVs201may be removed through a grinding process such as chemical mechanical polishing (CMP), although any suitable removal process may be used. In an embodiment, the TSVs201have a width of between about 5 μm and about 60 μm, such as about 10 μm. As one of ordinary skill in the art will recognize, the above described process for forming the TSVs201is merely one method of forming the TSVs201, and other methods are also fully intended to be included within the scope of the embodiments.

With reference now toFIG. 3, there is shown a first passivation layer301, a second passivation layer307, a third passivation layer309, first metal contacts305, and connection terminals311. The first passivation layer301may be formed on the first metallization layer105over the TSVs201and the IPDs103. The first passivation layer301may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, combinations of these, or the like. In some embodiments, the first passivation layer301may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, may be utilized. The first passivation layer301may be placed using, e.g., a spin-coating process to a thickness of between about 5 μm and about 25 μm, such as about 7 μm, although any suitable method and thickness may be used. In other embodiments, the first passivation layer301may be formed through a process such as chemical vapor deposition (CVD).

The first metal contacts305are located in the first passivation layer301. The first metal contacts305connect to the TSVs201and the IPDs103through the first metallization layer105. The first metal contacts305may comprise a conductive material such as copper, although other conductive materials, such as tungsten, aluminum or copper alloy, or the like may be used. Openings into the first passivation layer301may be formed using a suitable photolithographic mask and etching process. The first metal contacts305may be formed in the openings in the first passivation layer301using a suitable process such as deposition, damascene, dual damascene, or another process. In some cases, components such as the first metal contacts305, TSVs201, IPDs103, and other components described herein may be connected to other components without directly contacting the other components. For example, a first component may be electrically or communicatively connected to a second component through a third component without directly contacting the second component.

In other embodiments, the first metal contacts305may be formed using a deposition process, such as sputtering, to form a layer of material (e.g., aluminum or another conductive material) and portions of the layer of material may then be removed through a suitable process (such as photolithographic masking and etching) to form the first metal contacts305. However, any other suitable process may be utilized to form the first metal contacts305. One the first metal contacts305are formed, the first passivation layer301may be formed over the first metal contacts305.

The second passivation layer307may be formed over the first passivation layer301and the first metal contacts305in order to protect the first passivation layer301and the first metal contacts305from physical and environmental damage during subsequent processing and environments. The second passivation layer307may be formed of similar materials and through similar processes as the first passivation layer301, although the second passivation layer307may be formed of different materials than the first passivation layer301. In some embodiments, the second passivation layer307is planarized, e.g., using a chemical mechanical polish (CMP) process.

Once the second passivation layer307has been formed over the first passivation layer301and the first metal contacts305, openings may be formed through the second passivation layer307in order to expose a portion of the first metal contacts305for further connections. The openings may be formed through a suitable masking and removal process, such as a suitable photolithographic masking and etching process. The disclosed patterning process discussed, however, is merely intended as a representative process, and any other suitable patterning process may be utilized to expose a portion of the first metal contacts305.

Once the first metal contacts305have been exposed through the second passivation layer307, the connection terminals311may be formed in electrical contact with the first metal contacts305through the second passivation layer307. In some embodiments, the connection terminals311comprise one or more bonding pads, such as an Al pad, an AlCu pad, or pads of other suitable materials. In some embodiments, the connection terminals311further comprise underbump metallization (UBMs). The UBMs may comprise three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBMs. Any suitable materials or layers of material that may be used for the UBMs are fully intended to be included within the scope of the current application.

The connection terminals311may be created by forming each sub-layer of the connection terminals311over the second passivation layer307and along the interior of the openings through the second passivation layer307. The forming of each sub-layer may be performed using a plating process, such as electrochemical plating, although other processes of formation, such as sputtering, evaporation, or PECVD process, may be used depending upon the desired materials.

The third passivation layer309may be formed over the first passivation layer301, the second passivation layer307and the connection terminals311in order to protect the first passivation layer301, the second passivation layer307, and the connection terminals311from physical and environmental damage during subsequent processing and environments. The third passivation layer309may be formed of similar materials and through similar processes as the first passivation layer301and the second passivation layer307, although the third passivation layer309may be formed of different materials than the first passivation layer301and the second passivation layer307.

Once the third passivation layer309has been formed over the first passivation layer301and second passivation layer307and the connection terminals311, openings may be formed through third passivation layer309in order to expose a portion of the connection terminals311for further connections. The openings may be formed through a suitable masking and removal process, such as a suitable photolithographic masking and etching process. The disclosed patterning process discussed, however, is merely intended as a representative process, and any other suitable patterning process may be utilized to expose a portion of the connection terminals311.

With reference now toFIG. 4, there is shown a protective coating401, first external connections403, and solder balls405. The protective coating401may be formed on the third passivation layer309and the connection terminals311. The protective coating401may be formed by coating on the third passivation layer309and the connection terminals311with an insulating material, such as polyimide, polybenzoxazole (PBO), or epoxy. The protective coating401may be formed by any suitable method, such as spraying a polyimide solution, immersing into a polyimide solution, spin-coating, or another method. In other embodiments, the protective coating401is not a polyimide but is a material such as comprises the first passivation layer301, the second passivation layer307, and the third passivation layer309.

In an embodiment the first external connections403may be conductive pillars and may be formed by initially forming a photoresist (not shown) over the protective coating401. The photoresist may be patterned to expose portions of the protective coating401through which the first external connections403will extend. Once patterned, the photoresist may then be used as a mask to remove the desired portions of the protective coating401, forming openings exposing those portions of the underlying connection terminals311to which the first external connections403will make contact.

The first external connections403may be formed within the openings of both the protective coating401and the photoresist to provide electrical connection to the connection terminals311. In an embodiment the first external connections403may be, e.g., copper pillars or copper posts. However, the embodiments are not limited to these, and may be solder bumps, copper bumps, or comprise one or more conductive materials, such as copper, tungsten, other conductive metals, or the like. Other suitable first external connections403may be made to provide electrical connection. All such external contacts are fully intended to be included within the scope of the embodiments.

The first external connections403may be formed, for example, by deposition, electroplating, electroless plating, or the like. Once the first external connections403have been formed using the photoresist, the photoresist may be removed using a suitable removal process. In an embodiment, a plasma ashing process may be used to remove the photoresist, whereby the temperature of the photoresist may be increased until the photoresist experiences a thermal decomposition and may be removed. However, any other suitable process, such as a wet strip, may alternatively be utilized. The removal of the photoresist may expose the first external connections403such that the first external connections403protrude past the surface of the protective coating401.

In an embodiment, optional solder balls405may be placed on the first external connections403and may comprise a eutectic material such as solder, although any suitable materials may alternatively be used. The solder balls405may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, and then performing a reflow is preferably performed in order to shape the material into the desired bump shape. In another embodiment, the solder balls405may be formed using a ball drop method, such as a direct ball drop process.

At this stage, a circuit probe test may be performed in order to check for defective structures. In an embodiment of the circuit probe test one or more probes (not illustrated) are electrically connected to the solder balls405or the first external connections403and signals are sent into the first external connections403and into, e.g., the IPDs103. If there are no significant defects, the probes will receive a predetermined output from the first external connections403, and defective structures and Known Good Die (KGD) can be identified. Defective structures and KGD can be identified prior to further processing in order to make the overall process more efficient. For example, only KGD may be used for further processing as described below with reference toFIGS. 7-15.

With reference now toFIG. 5, there is shown a carrier substrate501and a first adhesive layer503. The carrier substrate501comprises, for example, silicon based materials, such as glass or silicon oxide, or other materials, such as aluminum oxide, combinations of any of these materials, or the like. The carrier substrate501is planar in order to accommodate an attachment of semiconductor devices such as those illustrated and discussed with respect toFIGS. 1-4.

The first adhesive layer503is placed on the carrier substrate501in order to assist in the adherence of overlying structures (e.g., the protective coating401, the first external connections403, the solder balls405). In an embodiment the first adhesive layer503may comprise an ultra-violet glue, which loses its adhesive properties when exposed to ultra-violet light. However, other types of adhesives, such as pressure sensitive adhesives, radiation curable adhesives, epoxies, combinations of these, or the like, may also be used. The first adhesive layer503may be placed onto the carrier substrate501in a semi-liquid or gel form, which is readily deformable under pressure.

FIG. 5also illustrates a thinning of the first substrate101in order to expose the TSVs201for further processing. The thinning may be performed, e.g., using a mechanical grinding or chemical mechanical polishing (CMP) process whereby chemical etchants and abrasives are utilized to react and grind away the first substrate101until the conductive material203of the TSVs201has been exposed. In this manner, the TSVs201may be formed to have a first thickness of between about 50 μm and about 200 μm, such as about 100 μm. In an embodiment, the TSVs201have a cross-sectional thickness:width aspect ratio of between about 3:1 and about 10:1, such as about 5:1.

While the CMP process described above is presented as one illustrative embodiment, it is not intended to be limiting to the embodiments. Any other suitable removal process may alternatively be used to thin the first substrate101. For example, a series of chemical etches may be utilized. This process and any other suitable process may alternatively be utilized to thin the first substrate101, and all such processes are fully intended to be included within the scope of the embodiments. Optionally, after the first substrate101has been thinned, the TSVs201may be recessed within the first substrate101. In an embodiment the TSVs201may be recessed using, e.g., an etching process that utilizes an etchant that is selective to the material of the TSVs201(e.g., selective to copper).

With reference now toFIG. 6, there is shown a fourth passivation layer601, a first redistribution layer (RDL)603, a fifth passivation layer605, and second metal contacts607. The first redistribution layer603and the second metal contacts607may be formed in order to interconnect the TSVs201and an external semiconductor device (an example described below with reference toFIGS. 8 to 15). In an embodiment, the fourth passivation layer601is formed over the first substrate101in a process and with materials similar to the first passivation layer301, the second passivation layer307, and the third passivation layer309. Alternatively, the fourth passivation layer601may be formed differently than the first passivation layer301, the second passivation layer307, and the third passivation layer309. In an embodiment the fourth passivation layer601is thinned to expose the conductive material203of the TSVs201. The thinning may be performed, e.g., using a mechanical grinding or CMP process.

In an embodiment the first redistribution layer603may be formed by initially forming a seed layer (not shown) of a titanium copper alloy through a suitable formation process such as CVD or sputtering. A photoresist (also not shown) may then be formed to cover the seed layer, and the photoresist may then be patterned to expose those portions of the seed layer that are located where the first redistribution layer603is desired to be located.

Once the photoresist has been formed and patterned, a conductive material, such as copper, may be formed on the seed layer through a deposition process such as plating. However, while the material and methods discussed are suitable to form the conductive material, these materials are merely exemplary. Any other suitable materials, such as AlCu or Au, and any other suitable processes of formation, such as CVD or PVD, may alternatively be used to form the first redistribution layer603.

Once the conductive material has been formed, the photoresist may be removed through a suitable removal process such as ashing. Additionally, after the removal of the photoresist, those portions of the seed layer that were covered by the photoresist may be removed through, for example, a suitable etch process using the conductive material as a mask.

In an embodiment, a fifth passivation layer605is formed over the first redistribution layer603in a process and with materials similar to the first passivation layer301, the second passivation layer307, the third passivation layer309, and the fourth passivation layer601. Alternatively, the fifth passivation layer605may be formed differently than the first passivation layer301, the second passivation layer307, the third passivation layer309, and the fourth passivation layer601. In an embodiment the fifth passivation layer605is thinned, e.g., using a mechanical grinding or CMP process.

After the first redistribution layer603has been formed, openings may be made through into the first redistribution layer603by removing portions of the first redistribution layer603to expose at least a portion of the underlying conductive material. The openings may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of the first redistribution layer603may alternatively be used.

The second metal contacts607may be formed on the first redistribution layer603to form electrical connections to the first redistribution layer603. The second metal contacts607may comprise aluminum, but other materials, such as copper, may alternatively be used. The second metal contacts607may be formed using a deposition process, such as sputtering, to form a layer of conductive material and portions of the layer of material may then be removed through a suitable process (such as photolithographic masking and etching) to form the second metal contacts607. However, any other suitable process may be utilized to form the second metal contacts607.

With reference now toFIG. 7, there is shown a frame701and a second adhesive layer703. The second adhesive layer703is used to attach the first redistribution layer603and the second metal contacts607to the frame701for a singulation process. The frame701comprises, for example, silicon based materials, such as glass or silicon oxide, or other materials, such as aluminum oxide, metal, ceramic, polymer, combinations of any of these materials, or the like. In an embodiment, the second adhesive layer703comprises a die attach film (DAF) such as an epoxy resin, a phenol resin, acrylic rubber, silica filler, or a combination thereof, and is applied using a lamination technique. However, any other suitable alternative material and method of formation may alternatively be utilized.

FIG. 7also illustrates a singulation705of a first interconnect structure711and a second interconnect structure713. In an embodiment the singulation705may be performed by using a saw blade to slice through the second adhesive layer703and other layers described above with respect toFIGS. 1-6(e.g., the first substrate101, the first metallization layer105, etc.), thereby separating one interconnect structure from another.

However, as one of ordinary skill in the art will recognize, utilizing a saw blade to singulate the first interconnect structure711and the second interconnect structure713is merely one illustrative embodiment and is not intended to be limiting. Alternative methods for singulating the first interconnect structure711and the second interconnect structure713, such as utilizing one or more etches, may alternatively be utilized. These methods and any other suitable methods may alternatively be utilized to singulate the first interconnect structure711and the second interconnect structure713.

In some embodiments, the first interconnect structure711and the second interconnect structure713may be incorporated in an integrated fan out package-on-package (InFO-POP), discussed below with respect toFIGS. 8-16. With reference now toFIG. 8, there is shown a carrier substrate801with a third adhesive layer803, a polymer layer805, and a first seed layer807over the carrier substrate801. The carrier substrate801comprises, for example, silicon based materials, such as glass or silicon oxide, or other materials, such as aluminum oxide, combinations of any of these materials, or the like. The carrier substrate801is planar in order to accommodate an attachment of semiconductor devices such as the first interconnect structure711, the second interconnect structure713and a first semiconductor device901and a second semiconductor device1001(not illustrated inFIG. 9but illustrated and discussed below with respect toFIGS. 10-15).

The third adhesive layer803is placed on the carrier substrate801in order to assist in the adherence of overlying structures (e.g., the polymer layer805). In an embodiment the third adhesive layer803may comprise an ultra-violet glue, which loses its adhesive properties when exposed to ultra-violet light. However, other types of adhesives, such as pressure sensitive adhesives, radiation curable adhesives, epoxies, combinations of these, or the like, may also be used. The third adhesive layer803may be placed onto the carrier substrate801in a semi-liquid or gel form, which is readily deformable under pressure.

The polymer layer805is placed over the third adhesive layer803and is utilized in order to provide protection to, e.g., the first semiconductor device901and the second semiconductor device1001once the first semiconductor device901and the second semiconductor device1001have been attached. In an embodiment the polymer layer805may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, Solder Resistance (SR), or Ajinomoto build-up film (ABF) may alternatively be utilized. The polymer layer805may be placed using, e.g., a spin-coating process to a thickness of between about 2 μm and about 15 μm, such as about 5 μm, although any suitable method and thickness may alternatively be used.

The first seed layer807is formed over the polymer layer805. In an embodiment the first seed layer807is a thin layer of a conductive material that aids in the formation of a thicker layer during subsequent processing steps. The first seed layer807may comprise a layer of titanium about 1,000 Å thick followed by a layer of copper about 5,000 Å thick. The first seed layer807may be created using processes such as sputtering, evaporation, or PECVD processes, depending upon the desired materials. The first seed layer807may be formed to have a thickness of between about 0.3 μm and about 1 μm, such as about 0.5 μm.

FIG. 8also illustrates a placement and patterning of a photoresist809over the first seed layer807. In an embodiment the photoresist809may be placed on the first seed layer807using, e.g., a spin coating technique to a height of between about 50 μm and about 250 μm, such as about 120 μm. Once in place, the photoresist809may then be patterned by exposing the photoresist809to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist809exposed to the patterned light source. A developer is then applied to the exposed photoresist809to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist809or the unexposed portion of the photoresist809, depending upon the desired pattern.

In an embodiment the pattern formed into the photoresist809is a pattern for vias811. The vias811are formed in such a placement as to be located on different sides of subsequently attached devices such as the first semiconductor device901and the second semiconductor device1001. However, any suitable arrangement for the pattern of vias811, such as by being located such that the first semiconductor device901and the second semiconductor device1001are placed on opposing sides of the vias811, may alternatively be utilized.

In an embodiment the vias811are formed within the photoresist809. In an embodiment the vias811comprise one or more conductive materials, such as copper, tungsten, other conductive metals, or the like, and may be formed, for example, by electroplating, electroless plating, or the like. In an embodiment, an electroplating process is used wherein the first seed layer807and the photoresist809are submerged or immersed in an electroplating solution. The first seed layer807surface is electrically connected to the negative side of an external DC power supply such that the first seed layer807functions as the cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the solution and is attached to the positive side of the power supply. The atoms from the anode are dissolved into the solution, from which the cathode, e.g., the first seed layer807, acquires the dissolved atoms, thereby plating the exposed conductive areas of the first seed layer807within the opening of the photoresist809.

Once the vias811have been formed using the photoresist809and the first seed layer807, the photoresist809may be removed using a suitable removal process (not illustrated inFIG. 8but seen inFIG. 10below). In an embodiment, a plasma ashing process may be used to remove the photoresist809, whereby the temperature of the photoresist809may be increased until the photoresist809experiences a thermal decomposition and may be removed. However, any other suitable process, such as a wet strip, may alternatively be utilized. The removal of the photoresist809may expose the underlying portions of the first seed layer807.

Once exposed a removal of the exposed portions of the first seed layer807may be performed (not illustrated inFIG. 8but seen inFIG. 10below). In an embodiment the exposed portions of the first seed layer807(e.g., those portions that are not covered by the vias811) may be removed by, for example, a wet or dry etching process. For example, in a dry etching process reactants may be directed towards the first seed layer807using the vias811as masks. In another embodiment, etchants may be sprayed or otherwise put into contact with the first seed layer807in order to remove the exposed portions of the first seed layer807. After the exposed portion of the first seed layer807has been etched away, a portion of the polymer layer805is exposed between the vias811.

FIG. 9illustrates a first semiconductor device901that will be attached to the polymer layer805within the vias811(not illustrated inFIG. 9but illustrated and described below with respect toFIG. 10). In an embodiment the first semiconductor device901comprises a third substrate903, first active devices (not individually illustrated), second metallization layers905, first contact pads907, a sixth passivation layer911, and second external connections909. The third substrate903may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.

The first active devices comprise a wide variety of active devices and passive devices such as capacitors, resistors, inductors and the like that may be used to generate the desired structural and functional requirements of the design for the first semiconductor device901. The first active devices may be formed using any suitable methods either within or else on the third substrate903.

The second metallization layers905are formed over the third substrate903and the first active devices and are designed to connect the various active devices to form functional circuitry. In an embodiment the second metallization layers905are formed of alternating layers of dielectric and conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, etc.). In an embodiment there may be four layers of metallization separated from the third substrate903by at least one interlayer dielectric layer (ILD), but the precise number of second metallization layers905is dependent upon the design of the first semiconductor device901.

The first contact pads907may be formed over and in electrical contact with the second metallization layers905. The first contact pads907may comprise aluminum, but other materials, such as copper, may alternatively be used. The first contact pads907may be formed using a deposition process, such as sputtering, to form a layer of material (not shown) and portions of the layer of material may then be removed through a suitable process (such as photolithographic masking and etching) to form the first contact pads907. However, any other suitable process may be utilized to form the first contact pads907. The first contact pads907may be formed to have a thickness of between about 0.5 μm and about 4 μm, such as about 1.45 μm.

The sixth passivation layer911may be formed on the third substrate903over the second metallization layers905and the first contact pads907. The sixth passivation layer911may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, combinations of these, or the like. The sixth passivation layer911may be formed through a process such as chemical vapor deposition (CVD), although any suitable process may be utilized, and may have a thickness between about 0.5 μm and about 5 μm, such as about 9.25 KÅ.

The second external connections909may be formed to provide conductive regions for contact between the first contact pads907and, e.g., a second redistribution layer1201(not illustrated inFIG. 9but illustrated and described below with respect toFIG. 12). In an embodiment the second external connections909may be conductive pillars and may be formed by initially forming a photoresist (not shown) over the sixth passivation layer911to a thickness between about 5 μm to about 20 μm, such as about 10 μm. The photoresist may be patterned to expose portions of the first passivation layers through which the conductive pillars will extend. Once patterned, the photoresist may then be used as a mask to remove the desired portions of the sixth passivation layer911, thereby exposing those portions of the underlying first contact pads907to which the second external connections909will make contact.

The second external connections909may be formed within the openings of both the sixth passivation layer911and the photoresist. The second external connections909may be formed from a conductive material such as copper, although other conductive materials such as nickel, gold, or metal alloy, combinations of these, or the like may also be used. Additionally, the second external connections909may be formed using a process such as electroplating, by which an electric current is run through the conductive portions of the first contact pads907to which the second external connections909are desired to be formed, and the first contact pads907are immersed in a solution. The solution and the electric current deposit, e.g., copper, within the openings in order to fill and/or overfill the openings of the photoresist and the sixth passivation layer911, thereby forming the second external connections909. Excess conductive material and photoresist outside of the openings of the sixth passivation layer911may then be removed using, for example, an ashing process, a chemical mechanical polish (CMP) process, combinations of these, or the like.

However, as one of ordinary skill in the art will recognize, the above described process to form the second external connections909is merely one such description, and is not meant to limit the embodiments to this exact process. Rather, the described process is intended to be merely illustrative, as any suitable process for forming the second external connections909may alternatively be utilized. All suitable processes are fully intended to be included within the scope of the present embodiments.

On an opposite side of the third substrate903than the second metallization layers905, a die attach film (DAF)913may be formed in order to assist in the attachment of the first semiconductor device901to the polymer layer805. In an embodiment the die attach film is an epoxy resin, a phenol resin, acrylic rubber, silica filler, or a combination thereof, and is applied using a lamination technique. However, any other suitable alternative material and method of formation may alternatively be utilized.

FIG. 10illustrates a placement of the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001onto the polymer layer805. In an embodiment the second semiconductor device1001may comprise a fourth substrate1003, second active devices (not individually illustrated), third metallization layers1005, second contact pads1007, a seventh passivation layer1011, a second die attach film (DAF)1013, and third external connections1009. In an embodiment the fourth substrate1003, second active devices (not individually illustrated), third metallization layers1005, second contact pads1007, a seventh passivation layer1011, and third external connections1009may be similar to the third substrate903, the first active devices, the second metallization layers905, the first contact pads907, the sixth passivation layer911, and the second external connections909, although they may also be different.

In an embodiment the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001may be placed onto the polymer layer805using, e.g., a pick-and-place process. However, any other alternative method of placing the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001may be used.

FIG. 11illustrates an encapsulation of the vias811, the first semiconductor device901and the second semiconductor device1001. The encapsulation may be performed in a molding device (not individually illustrated inFIG. 11), which may comprise a top molding portion and a bottom molding portion separable from the top molding portion. When the top molding portion is lowered to be adjacent to the bottom molding portion, a molding cavity may be formed for the carrier substrate801, the vias811, the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001.

During the encapsulation process the top molding portion may be placed adjacent to the bottom molding portion, thereby enclosing the carrier substrate801, the vias811, the first semiconductor device901, and the second semiconductor device1001within the molding cavity. Once enclosed, the top molding portion and the bottom molding portion may form an airtight seal in order to control the influx and outflux of gasses from the molding cavity. Once sealed, an encapsulant1101may be placed within the molding cavity. The encapsulant1101may be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinations of these, or the like. The encapsulant1101may be placed within the molding cavity prior to the alignment of the top molding portion and the bottom molding portion, or else may be injected into the molding cavity through an injection port.

The encapsulant1101may be placed into the molding cavity such that the encapsulant1101encapsulates the carrier substrate801, the vias811, the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001. For example, the encapsulant1101may surround the vias811, directly contacting conductive material of the vias811and/or oxidized conductive material present on the surface of the vias811. Once the encapsulant1101has been placed into the molding cavity, the encapsulant1101may be cured in order to harden the encapsulant1101for optimum protection. While the exact curing process is dependent at least in part on the particular material chosen for the encapsulant1101, in an embodiment in which molding compound is chosen as the encapsulant1101, the curing could occur through a process such as heating the encapsulant1101to between about 100° C. and about 130° C., such as about 125° C. for about 60 sec to about 3000 sec, such as about 600 sec. Additionally, initiators and/or catalysts may be included within the encapsulant1101to better control the curing process.

However, as one having ordinary skill in the art will recognize, the curing process described above is merely an exemplary process and is not meant to limit the current embodiments. Other curing processes, such as irradiation or even allowing the encapsulant1101to harden at ambient temperature, may alternatively be used. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

FIG. 11also illustrates a thinning of the encapsulant1101in order to expose the vias811, the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001for further processing. The thinning may be performed, e.g., using a mechanical grinding or chemical mechanical polishing (CMP) process whereby chemical etchants and abrasives are utilized to react and grind away the encapsulant1101, the first semiconductor device901and the second semiconductor device1001until the vias811, the second external connections909(on the first semiconductor device901), the third external connections1009(on the second semiconductor device1001), and the (optional) solder balls405or the first external connections403(on the first interconnect structure711and the second interconnect structure713) have been exposed. As such, the first semiconductor device901, the second semiconductor device1001, the first interconnect structure711, the second interconnect structure713, and the vias811may have a planar surface that is also planar with the encapsulant1101.

However, while the CMP process described above is presented as one illustrative embodiment, it is not intended to be limiting to the embodiments. Any other suitable removal process may alternatively be used to thin the encapsulant1101, the first semiconductor device901, and the second semiconductor device1001. For example, a series of chemical etches may be utilized. This process and any other suitable process may alternatively be utilized to thin the encapsulant1101, the first semiconductor device901, and the second semiconductor device1001, and all such processes are fully intended to be included within the scope of the embodiments.

FIG. 12illustrates a cross-sectional view of a formation of a second redistribution layer (RDL)1201, a third redistribution layer1205, and a fourth redistribution layer1209in order to interconnect the first semiconductor device901, the second semiconductor device1001, the vias811, the first interconnect structure711, the second interconnect structure713, and a fourth external connection1221.FIG. 12also illustrates a formation of an eighth passivation layer1203over the encapsulant1101, the first semiconductor device901, the second semiconductor device1001, the vias811, the first interconnect structure711, and the second interconnect structure713in order to provide protection and isolation for the other underlying structures. In an embodiment the eighth passivation layer1203may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, may alternatively be utilized. The eighth passivation layer1203may be placed using, e.g., a spin-coating process to a thickness of between about 5 μm and about 25 μm, such as about 7 μm, although any suitable method and thickness may alternatively be used.

After the eighth passivation layer1203has been formed, first openings1204(only one of which is illustrated inFIG. 12for clarity) may be made through the eighth passivation layer1203by removing portions of the eighth passivation layer1203to expose at least a portion of the underlying second external connections909(on the first semiconductor device901), the third external connections1009(on the second semiconductor device1001), and the (optional) solder balls405or first external connections403(on the first interconnect structure711and the second interconnect structure713). The first openings1204allow for contact between the second redistribution layer1201and the underlying structures. The first openings1204may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose the underlying structures may also be used.

In an embodiment the second redistribution layer1201may be formed by initially forming a seed layer (not shown) of a titanium copper alloy through a suitable formation process such as CVD or sputtering. A photoresist (also not shown) may then be formed to cover the seed layer, and the photoresist may then be patterned to expose those portions of the seed layer that are located where the second redistribution layer1201is desired to be located.

Once the photoresist has been formed and patterned, a conductive material, such as copper, may be formed on the seed layer through a deposition process such as plating. The conductive material may be formed to have a thickness of between about 1 μm and about 10 μm, such as about 5 μm. However, while the material and methods discussed are suitable to form the conductive material, these materials are merely exemplary. Any other suitable materials, such as AlCu or Au, and any other suitable processes of formation, such as CVD or PVD, may alternatively be used to form the second redistribution layer1201.

Once the conductive material has been formed, the photoresist may be removed through a suitable removal process such as ashing. Additionally, after the removal of the photoresist, those portions of the seed layer that were covered by the photoresist may be removed through, for example, a suitable etch process using the conductive material as a mask.

FIG. 12also illustrates a formation of a ninth passivation layer1207over the second redistribution layer1201in order to provide protection and isolation for the second redistribution layer1201and the other underlying structures. In an embodiment the ninth passivation layer1207may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, may alternatively be utilized. The ninth passivation layer1207may be placed using, e.g., a spin-coating process to a thickness of between about 5 μm and about 25 μm, such as about 7 μm, although any suitable method and thickness may alternatively be used.

After the ninth passivation layer1207has been formed, second openings1206(only one of which is illustrated inFIG. 12for clarity) may be made through the ninth passivation layer1207by removing portions of the ninth passivation layer1207to expose at least a portion of the underlying second redistribution layer1201. The second openings1206allow for contact between the second redistribution layer1201and a third redistribution layer1205(described further below). The second openings1206may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of the second redistribution layer1201may alternatively be used.

The third redistribution layer1205may be formed to provide additional routing and connectivity and in electrical connection with the second redistribution layer1201. In an embodiment the third redistribution layer1205may be formed similar to the second redistribution layer1201. For example, a seed layer may be formed, a photoresist may be placed and patterned on top of the seed layer, and conductive material may be plated into the patterned openings through the photoresist. Once formed, the photoresist may be removed, the underlying seed layer may be etched, the third redistribution layer1205may be covered by a tenth passivation layer1211(which may be similar to the ninth passivation layer1207), and the tenth passivation layer1211may be patterned to form third openings1208(only one of which is illustrated inFIG. 12for clarity) and expose an underlying conductive portion of the third redistribution layer1205.

The fourth redistribution layer1209may be formed to provide additional routing along with electrical connection between the third redistribution layer1205and the fourth external connection1221. In an embodiment the fourth redistribution layer1209may be formed using materials and processes similar to the second redistribution layer1201. For example, a seed layer may be formed, a photoresist may be placed and patterned on top of the seed layer in a desired pattern for the fourth redistribution layer1209, conductive material is plated into the patterned openings of the photoresist, the photoresist is removed, and the seed layer is etched.

Turning now toFIGS. 12 and 13, after the fourth redistribution layer1209has been formed, an eleventh passivation layer1213may be formed over the fourth redistribution layer1209in order to protect the fourth redistribution layer1209and other underlying structures. In an embodiment the eleventh passivation layer1213, similar to the eighth passivation layer1203, may be formed from a polymer such as PBO, or may be formed of a similar material as the eighth passivation layer1203(e.g., polyimide or a polyimide derivative). The eleventh passivation layer1213may be formed to have a thickness of between about 2 μm and about 15 μm, such as about 5 μm.

After the eleventh passivation layer1213has been formed, an opening may be made through the eleventh passivation layer1213by removing portions of the eleventh passivation layer1213to expose at least a portion of the underlying fourth redistribution layer1209. The opening allows for contact between the fourth redistribution layer1209and the second UBMs1219. The opening may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of the fourth redistribution layer1209may be used.

Once the fourth redistribution layer1209has been exposed through the eleventh passivation layer1213, the second UBMs1219may be formed in electrical contact with the eleventh passivation layer1213. The second UBMs1219may comprise three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the second UBMs1219. Any suitable materials or layers of material that may be used for the second UBMs1219are fully intended to be included within the scope of the current application.

The second UBMs1219may be created by forming each layer over the eleventh passivation layer1213and along the interior of the opening through the eleventh passivation layer1213. The forming of each layer may be performed using a plating process, such as electrochemical plating, although other processes of formation, such as sputtering, evaporation, or PECVD process, may alternatively be used depending upon the desired materials. The second UBMs1219may be formed to have a thickness of between about 0.7 μm and about 10 μm, such as about 5 μm. Once the desired layers have been formed, portions of the layers may then be removed through a suitable photolithographic masking and etching process to remove the undesired material and to leave the second UBMs1219in a desired shape, such as a circular, octagonal, square, or rectangular shape, although any desired shape may alternatively be formed.

The fourth external connection1221may be utilized to provide an external connection point for electrical connection to the fourth redistribution layer1209and may be, for example, a contact bump, although any suitable connection may be utilized. In an embodiment in which the fourth external connection1221is a contact bump, the fourth external connection1221may comprise a material such as tin, or other suitable materials, such as silver, lead-free tin, or copper. In an embodiment in which the fourth external connection1221is a tin solder bump, the fourth external connection1221may be formed by initially forming a layer of tin through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc., to a thickness of, e.g., about 100 μm. Once a layer of tin has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shape.

FIG. 13illustrates a debonding of the carrier substrate801from the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001. In an embodiment the fourth external connection1221and, hence, the structure including the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001, may be attached to a ring structure1301. The ring structure1301may be a metal ring intended to provide support and stability for the structure during and after the debonding process. In an embodiment the fourth external connection1221, the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001are attached to the ring structure1301using, e.g., a ultraviolet tape1303, although any other suitable adhesive or attachment may alternatively be used.

Once the fourth external connection1221and, hence, the structure including the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001are attached to the ring structure1301, the carrier substrate801may be debonded from the structure including the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001using, e.g., a thermal process to alter the adhesive properties of the third adhesive layer803. In a particular embodiment an energy source such as an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser, is utilized to irradiate and heat the third adhesive layer803until the third adhesive layer803loses at least some of its adhesive properties. Once performed, the carrier substrate801and the third adhesive layer803may be physically separated and removed from the structure comprising the fourth external connection1221, the first interconnect structure711, the second interconnect structure713, the first semiconductor device901, and the second semiconductor device1001.

FIG. 13additionally illustrates a patterning of the polymer layer805in order to expose the vias811(along with the associated first seed layer807), the first interconnect structure711, and the second interconnect structure713. In an embodiment the polymer layer805may be patterned using, e.g., a laser drilling method. In such a method a protective layer, such as a light-to-heat conversion (LTHC) layer or a hogomax layer (not separately illustrated inFIG. 13) is first deposited over the polymer layer805. Once protected, a laser is directed towards those portions of the polymer layer805which are desired to be removed in order to expose the underlying vias811, the first interconnect structure711, and the second interconnect structure713. During the laser drilling process the drill energy may be in a range from 0.1 mJ to about 30 mJ, and a drill angle of about 0 degree (perpendicular to the polymer layer805) to about 85 degrees to normal of the polymer layer805. In an embodiment the patterning may be formed to form fourth openings1305over the vias811to have a width of between about 100 μm and about 300 μm, such as about 200 μm.

In another embodiment, the polymer layer805may be patterned by initially applying a photoresist (not individually illustrated inFIG. 13) to the polymer layer805and then exposing the photoresist to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending upon the desired pattern, and the underlying exposed portion of the polymer layer805are removed with, e.g., a dry etch process. However, any other suitable method for patterning the polymer layer805may be utilized.

FIG. 14illustrates a placement of a backside ball pad1401within the fourth openings1305in order to protect the now exposed vias811and the second metal contacts607. In an embodiment the backside ball pads1401may comprise a conductive material such as solder on paste or an oxygen solder protection (OSP), although any suitable material may alternatively be utilized. In an embodiment the backside ball pads1401may be applied using a stencil, although any suitable method of application may alternatively be utilized, and then reflowed in order to form a bump shape.

FIG. 14also illustrates a placement and patterning of a backside protection layer1403over the backside ball pads1401, effectively sealing the joint between the backside ball pads1401and the vias811from intrusion by moisture. In an embodiment the backside protection layer1403may be a protective material such as a PBO, Solder Resistance (SR), Lamination Compound (LC) tape, Ajinomoto build-up film (ABF), non-conductive paste (NCP), non-conductive film (NCF), patterned underfill (PUF), warpage improvement adhesive (WIA), liquid molding compound V9, combinations of these, or the like. However, any suitable material may also be used. The backside protection layer1403may be applied using a process such as screen printing, lamination, spin coating, or the like, to a thickness of between about 1 μm to about 200 μm.

FIG. 14also illustrates that, once the backside protection layer1403has been placed, the backside protection layer1403may be patterned in order to expose the backside ball pads1401. In an embodiment the backside protection layer1403may be patterned using, e.g., a laser drilling method, by which a laser is directed towards those portions of the backside protection layer1403which are desired to be removed in order to expose the backside ball pads1401. During the laser drilling process the drill energy may be in a range from 0.1 mJ to about 30 mJ, and a drill angle of about 0 degree (perpendicular to the backside protection layer1403) to about 85 degrees to normal of the backside protection layer1403. In an embodiment the exposure may form openings with a diameter of between about 30 μm and about 300 μm, such as about 150 μm.

In another embodiment, the backside protection layer1403may be patterned by initially applying a photoresist (not individually illustrated inFIG. 14) to the backside protection layer1403and then exposing the photoresist to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending upon the desired pattern, and the underlying exposed portion of the backside protection layer1403are removed with, e.g., a dry etch process. However, any other suitable method for patterning the backside protection layer1403may be utilized.

FIG. 14also illustrates a bonding of the backside ball pads1401to a first package1400. In an embodiment the first package1400may comprise a fifth substrate1405, a third semiconductor device1407, a fourth semiconductor device1409(bonded to the third semiconductor device1407), third contact pads1411, a second encapsulant1413, and fifth external connections1415. In an embodiment the fifth substrate1405may be, e.g., a packaging substrate comprising internal interconnects (e.g., through substrate vias1417) to connect the third semiconductor device1407and the fourth semiconductor device1409to the backside ball pads1401.

Alternatively, the fifth substrate1405may be an interposer used as an intermediate substrate to connect the third semiconductor device1407and the fourth semiconductor device1409to the backside ball pads1401. In this embodiment the fifth substrate1405may be, e.g., a silicon substrate, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. However, the fifth substrate1405may alternatively be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that may provide a suitable protection and/or interconnection functionality. These and any other suitable materials may alternatively be used for the fifth substrate1405.

The third semiconductor device1407may be a semiconductor device designed for an intended purpose such as a memory die (e.g., a DRAM die), a logic die, a central processing unit (CPU) die, combinations of these, or the like. In an embodiment the third semiconductor device1407comprises integrated circuit devices, such as transistors, capacitors, inductors, resistors, first metallization layers (not shown), and the like, therein, as desired for a particular functionality. In an embodiment the third semiconductor device1407is designed and manufactured to work in conjunction with or concurrently with the first semiconductor device901.

The fourth semiconductor device1409may be similar to the third semiconductor device1407. For example, the fourth semiconductor device1409may be a semiconductor device designed for an intended purpose (e.g., a DRAM die) and comprising integrated circuit devices for a desired functionality. In an embodiment the fourth semiconductor device1409is designed to work in conjunction with or concurrently with the first semiconductor device901and/or the third semiconductor device1407.

The fourth semiconductor device1409may be bonded to the third semiconductor device1407. In an embodiment the fourth semiconductor device1409is only physically bonded with the third semiconductor device1407, such as by using an adhesive. In this embodiment the fourth semiconductor device1409and the third semiconductor device1407may be electrically connected to the fifth substrate1405using, e.g., wire bonds1419, although any suitable electrical bonding may be alternatively be utilized.

Alternatively, the fourth semiconductor device1409may be bonded to the third semiconductor device1407both physically and electrically. In this embodiment the fourth semiconductor device1409may comprise sixth external connections (not separately illustrated inFIG. 14) that connect with seventh external connections (also not separately illustrated inFIG. 14) on the third semiconductor device1407in order to interconnect the fourth semiconductor device1409with the third semiconductor device1407.

The third contact pads1411may be formed on the fifth substrate1405to form electrical connections between the third semiconductor device1407and, e.g., the fifth external connections1415. In an embodiment the third contact pads1411may be formed over and in electrical contact with electrical routing (such as through substrate vias1417) within the fifth substrate1405. The third contact pads1411may comprise aluminum, but other materials, such as copper, may alternatively be used. The third contact pads1411may be formed using a deposition process, such as sputtering, to form a layer of material (not shown) and portions of the layer of material may then be removed through a suitable process (such as photolithographic masking and etching) to form the third contact pads1411. However, any other suitable process may be utilized to form the third contact pads1411. The third contact pads1411may be formed to have a thickness of between about 0.5 μm and about 4 μm, such as about 1.45 μm.

The second encapsulant1413may be used to encapsulate and protect the third semiconductor device1407, the fourth semiconductor device1409, and the fifth substrate1405. In an embodiment the second encapsulant1413may be a molding compound and may be placed using a molding device (not illustrated inFIG. 14). For example, the fifth substrate1405, the third semiconductor device1407, and the fourth semiconductor device1409may be placed within a cavity of the molding device, and the cavity may be hermetically sealed. The second encapsulant1413may be placed within the cavity either before the cavity is hermetically sealed or else may be injected into the cavity through an injection port. In an embodiment the second encapsulant1413may be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinations of these, or the like.

Once the second encapsulant1413has been placed into the cavity such that the second encapsulant1413encapsulates the region around the fifth substrate1405, the third semiconductor device1407, and the fourth semiconductor device1409, the second encapsulant1413may be cured in order to harden the second encapsulant1413for optimum protection. While the exact curing process is dependent at least in part on the particular material chosen for the second encapsulant1413, in an embodiment in which molding compound is chosen as the second encapsulant1413, the curing could occur through a process such as heating the second encapsulant1413to between about 100° C. and about 130° C., such as about 125° C. for about 60 sec to about 3000 sec, such as about 600 sec. Additionally, initiators and/or catalysts may be included within the second encapsulant1413to better control the curing process.

However, as one having ordinary skill in the art will recognize, the curing process described above is merely an exemplary process and is not meant to limit the current embodiments. Other curing processes, such as irradiation or even allowing the second encapsulant1413to harden at ambient temperature, may alternatively be used. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

In an embodiment the fifth external connections1415may be formed to provide an external connection between the fifth substrate1405and, e.g., the backside ball pads1401. The fifth external connections1415may be contact bumps such as microbumps or controlled collapse chip connection (C4) bumps and may comprise a material such as tin, or other suitable materials, such as silver or copper. In an embodiment in which the fifth external connections1415are tin solder bumps, the fifth external connections1415may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc., to a thickness of, e.g., about 100 μm. Once a layer of tin has been formed on the structure, a reflow is performed in order to shape the material into the desired bump shape.

Once the fifth external connections1415have been formed, the fifth external connections1415are aligned with and placed into physical contact with the backside ball pads1401, and a bonding is performed. For example, in an embodiment in which the fifth external connections1415are solder bumps, the bonding process may comprise a reflow process whereby the temperature of the fifth external connections1415is raised to a point where the fifth external connections1415will liquefy and flow, thereby bonding the first package1400to the backside ball pads1401once the fifth external connections1415resolidifies.

FIG. 14additionally illustrates the bonding of a second package1421to the backside ball pads1401. In an embodiment the second package1421may be similar to the first package1400, and may be bonded to the backside ball pads1401utilizing similar processes. However, the second package1421may also be different from the first package1400. AsFIG. 14shows, the first package1400may be electrically connected to the second redistribution layer1201through the vias811and the TSVs201in the first interconnect structure711. Similarly, the second package1421may be electrically connected to the second redistribution layer1201through the vias811and the TSVs201in the second interconnect structure713.

FIG. 15illustrates a debonding of the fourth external connection1221from the ring structure1301and a singulation of the structure to form an integrated fan out package-on-package (InFO-POP) structure1500. In an embodiment the fourth external connection1221may be debonded from the ring structure1301by initially bonding the first package1400and the second package1421to a second ring structure using, e.g., a second ultraviolet tape. Once bonded, the ultraviolet tape1303may be irradiated with ultraviolet radiation and, once the ultraviolet tape1303has lost its adhesiveness, the fourth external connection1221may be physically separated from the ring structure1301.

Once debonded, a singulation of the structure to form the InFO-POP structure1500is performed. In an embodiment the singulation may be performed by using a saw blade (not shown) to slice through the encapsulant1101and the polymer layer805between the vias811, thereby separating one section from another to form the InFO-POP structure1500with the first semiconductor device901. However, as one of ordinary skill in the art will recognize, utilizing a saw blade to singulate the InFO-POP structure1500is merely one illustrative embodiment and is not intended to be limiting. Alternative methods for singulating the InFO-POP structure1500, such as utilizing one or more etches to separate the InFO-POP structure1500, may alternatively be utilized. These methods and any other suitable methods may alternatively be utilized to singulate the InFO-POP structure1500.

FIG. 16illustrates an example cross-section of the InFO-POP structure1500through A-A′ as shown inFIG. 15. AsFIG. 16illustrates, the first semiconductor device901is surrounded by the vias811, the first interconnect structure711, a third interconnect structure1601, and a fourth interconnect structure1603.FIG. 16illustrates the InFO-POP structure1500including three interconnect structures, though in other embodiments the InFO-POP structure1500includes another number of interconnect structures (e.g., one interconnect structure, two interconnect structures, five interconnect structures, or another number of interconnect structures). In an embodiment the third interconnect structure1601and the fourth interconnect structure1603may be similar to the first interconnect structure711, and may be formed and incorporated into the InFO-POP structure1500utilizing similar processes. However, the third interconnect structure1601and the fourth interconnect structure1603may also be different from the first interconnect structure711. For example, the first interconnect structure711, the third interconnect structure1601, and the fourth interconnect structure1603may have different sizes, different shapes, different arrangement, number, or types of IPDs, different arrangement or numbers of the TSVs201, or be different in other aspects. In an embodiment, the first interconnect structure711, the third interconnect structure1601, and the fourth interconnect structure1603are located adjacent to the vias811between the first semiconductor device901and the edge of the InFO-POP structure1500. In an embodiment, the vias811form a “ring” of vias811surrounding the first semiconductor device901, and the first interconnect structure711, the third interconnect structure1601, and the fourth interconnect structure1603may be disposed in the “ring.” In an embodiment, the first interconnect structure711, the third interconnect structure1601, and the fourth interconnect structure1603can be used in place of the vias811in the InFO-POP structure1500. AsFIG. 16illustrates, in an embodiment the TSVs201of the first interconnect structure711, the third interconnect structure1601, and the fourth interconnect structure1603may have a smaller width and/or have a greater density than the vias811of the InFO-POP structure1500.

The interconnect structure disclosed herein may be an embedded dual side IPD (eDS-IPD). By incorporating integrated passive devices (IPDs) and through substrate vias (TSVs) in the same structure, the interconnect structure (e.g., the eDS-IPD) can serve both as an IPD device and an interconnect path between a semiconductor device (e.g., the first semiconductor device901) and a package (e.g., the first package1400). For example, the interconnect structure may serve as an IPD and an interconnect path between a semiconductor device and a DRAM, simultaneously. The interconnect structure (e.g., the first interconnect structure711) can replace vias (e.g., the vias811) in an InFO-PoP structure (e.g., the InFO-PoP structure1500) to enhance routing flexibility and save penalty area. For example, positioning the interconnect structure with the vias can reduce area for the IPDs and the semiconductor device placed side-by-side. The interconnect structure can also provide better capacitance performance due to smaller path inductance.

In an embodiment, a semiconductor device includes a redistribution layer (RDL) and a die disposed on the RDL. The semiconductor device also includes a first set of through vias between and connecting a top substrate and the RDL, the first set of through vias in physical contact with a molding compound and separated from the die by the molding compound. The semiconductor device also includes a first interconnect structure between and connecting the top substrate and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes at least one passive device and a second set of through vias within the first interconnect structure.

In another embodiment, a semiconductor device includes a layer between a package and a redistribution layer (RDL). The layer includes a semiconductor die connected to the RDL. A first side of the semiconductor die is connected to the RDL and a second side of the semiconductor die is attached to a polymer layer by an adhesive layer. The layer also includes at least one first via extending from a first side of the layer to a second side of the layer, a first passive device structure, and a second passive device structure. The first passive device structure includes at least one passive device and at least one second via disposed within the first passive device structure. The second passive device structure includes at least one passive device and at least one third via disposed within the second passive device structure The semiconductor device also includes a molding compound surrounding the semiconductor die, the at least one first via, the first passive device structure, and the second passive device structure, wherein the first passive device structure is separated from the at least one first via and the second passive device structure by the molding compound and wherein the at least one first via extends from a first side of the molding compound to a second side of the molding compound. The at least one first via, the at least one second via, and the at least one third via connect the RDL and the package, wherein the at least one second via and the at least one third via are through substrate vias (TSVs).

In yet another embodiment, a method of manufacturing a semiconductor device is provided. The method includes forming a set of vias on a redistribution layer (RDL), placing a die on the RDL separated from the set of vias, and placing a first interconnect structure on the RDL. The first interconnect structure is separated from the die and the vias, and the first interconnect structure includes a substrate, at least one through conductive element extending from one side of the substrate to a second side of the substrate, and at least one integrated passive device. The method also includes encapsulating the set of vias, the die, and the first interconnect structure in an encapsulant, wherein the encapsulant is in physical contact with the set of vias, the die, and the first interconnect structure, and planarizing the set of vias, the die, and the first interconnect structure.