Metal gate transistor and method for fabricating the same

A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for fabricating transistor, and more particularly, to a method for fabricating metal gate transistor.

2. Description of the Prior Art

In the field of semiconductor fabrication, the use of polysilicon material is diverse. Having a strong resistance for heat, polysilicon materials are commonly used to fabricate gate electrodes for metal-oxide semiconductor transistors. The gate pattern fabricated by polysilicon materials is also used to form self-aligned source/drain regions as polysilicon readily blocks ions from entering the channel region.

However, devices fabricated by polysilicon still have many drawbacks. In contrast to most metal, polysilicon gates are fabricated by semiconductor materials having high resistance, which causes the polysilicon gate to work under a much lower rate than other metal gates. In order to compensate for slightly lowered rate of performance, a significant amount of silicides is applied during the fabrication of polysilicon processes, such that the performance of the device could be increased to an acceptable level.

Gate electrodes fabricated by polysilicon also causes a depletion effect. In most circumstances, the optimum doping concentration for polysilicon is between about 2×2020/cm3and 3×1020/cm3. As most gate electrodes have a doping concentration of at least 5×1021/cm3, the limited doping concentration of polysilicon gates often results in a depletion region at the interface between the gate and the gate dielectric layer. This depletion region not only thickens the gate dielectric layer, but also lowers the capacitance of the gate and ultimately reduces the driving ability of the device.

In order to resolve this issue, work function metal gates have been developed to replace conventional polysilicon gates. The conventional approach for fabricating metal gates typically forms a dummy gate composed primarily of polysilicon on a substrate, removes the polysilicon material of the dummy gate through dry etching or wet etching, and then deposits a metal into the depleted dummy gate for forming a metal gate.

However, the conventional approach of depleting the polysilicon material from the dummy gate often damages the gate insulating layer underneath. As a result, another thermal oxidation has to be carried out to form another gate insulating layer afterwards. This not only extends the overall fabrication time but also disrupts the distribution of the dopants within the lightly doped drain or source/drain region. Hence, how to effectively resolve the above issue has become an important task.

SUMMARY OF THE INVENTION

It is an objective of the present invention to provide a method for fabricating metal gate transistor for solving the aforementioned problem.

According to a preferred embodiment of the present invention, a method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.

DETAILED DESCRIPTION

Referring toFIGS. 1-5,FIGS. 1-5illustrate a method for fabricating a metal gate transistor according to a preferred embodiment of the present invention. As shown inFIG. 1, a substrate12, such as a silicon substrate or a silicon-on-insulator substrate is provided, in which at least one transistor region14is defined on the substrate12.

A gate insulating layer (not shown) composed of dielectric material such as oxides or nitrides is then formed on the surface of the substrate12. According to an embodiment of the present invention, the gate insulating layer could also be composed of pad oxide or a high-k dielectric layer consisting of HfSiO, HfSiON, HfO, LaO, LaAlO, ZrO, ZrSiO, HfZrO, or combination thereof.

A stacked film (not shown) composed of an etching stop layer, a polysilicon layer, and a hard mask is formed on the gate insulating layer. Preferably, the etching stop layer is composed of a silicon nitride layer having a thickness of less than 100 Angstroms, and the polysilicon layer serving as dummy gate layer preferably has a thickness of about 1000 Angstroms. The polysilicon layer could be composed of undoped polysilicon or polysilicon having N+ dopants therein, and the hard mask could be composed of SiO2, silicon nitride, or SiON, which are all within the scope of the present invention.

Next, a patterned photoresist (not shown) is formed on the hard mask, and a pattern transfer is conducted by using the patterned photoresist as mask through single or multiple etching processes to remove a portion of the hard mask, the polysilicon layer, the etching stop layer, and the gate insulating layer. After stripping the patterned photoresist, a dummy gate24composed of patterned gate insulating layer16, patterned etching stop layer18, patterned polysilicon layer20, and patterned hard mask22is formed on the substrate12of the transistor region14.

As shown inFIG. 2, a first stage of spacer formation is carried out by first depositing a dielectric layer composed of silicon nitride or both silicon oxide and silicon nitride on the dummy gate24, and then etching back the deposited dielectric layer to form a first spacer26on the sidewall of the dummy gate24.

Next, a light doping process is performed to form a lightly doped drain. For instance, a patterned photoresist (not shown) is formed on the region outside the transistor region14, and an ion implantation is carried out by using the patterned photoresist as mask to implant n-type or p-type dopants into the substrate12adjacent to two sides of the dummy gate24to form a lightly doped drain28.

Next, a second stage of spacer formation is conducted by sequentially depositing a silicon oxide layer30and a silicon nitride layer32on the substrate12and the dummy gate24, and then etching back the deposited silicon oxide layer30and silicon nitride layer32to form a second spacer34around the first spacer26.

Next, a heavy doping process is performed to form a source/drain region. Similar the above approach of forming the lightly doped drain28, a patterned photoresist (not shown) could be formed on regions outside the transistor region14, and an ion implantation is carried out by using the patterned photoresist as mask to implant n-type or p-type dopants into the substrate12adjacent to two sides of the second spacer34. After thermally diffusing the implanted dopants, a source/drain region36is formed in the substrate12adjacent to two sides of the second spacer34, and the patterned photoresist is stripped thereafter.

Next, a silicon substrate etching back process accompanying a selective epitaxial growth (SEG) process could be performed before or after the formation of the aforementioned source/drain region to form an epitaxial layer (not shown) comprising of silicon and other materials partially in the source/drain region. A salicide process is carried out thereafter to forma silicide layer on the source/drain region36. As the selective epitaxial growth process and the salicide process are commonly known to those skilled in the art in this field, the details of which are omitted herein for the sake of brevity. Moreover, despite the first spacer, the lightly doped drain, the second spacer, and the source/drain region are formed sequentially in the above embodiment, the order for fabricating the spacers and doping regions could also be adjusted according to the demand of the product, which are all within the scope of the present invention.

Next, an interlayer dielectric layer38primarily composed of oxides is formed to cover the entire dummy gate24. The interlayer dielectric layer38could include nitrides, oxides, carbides, low-k dielectric materials, or combination thereof.

As shown inFIG. 3, a chemical mechanical polishing (CMP) process or a dry etching process is performed to remove a portion of the interlayer dielectric layer38, part of the first spacer26, part of the second spacer34, and the hard mask22such that the top of the polysilicon layer20is exposed and substantially even with the surface of the interlayer dielectric layer38.

As shown inFIG. 4, a selective dry etching or wet etching process is carried out by using etchant such as NH4OH or TMAH to empty the polysilicon layer20of the dummy gate24while stopping on the etching stop layer18. Next, a wet etching process is performed by using phosphoric acid to remove the etching stop layer18composed of silicon nitride. The removal of the etching stop layer18preferably forms an opening40in the dummy gate24while exposing the gate insulating layer16underneath.

It should be noted that the present invention preferably forms an etching stop layer18composed of silicon nitride between the gate insulating layer16and the polysilicon layer20. This etching stop layer18could be used to protect the gate insulating layer16by preventing plasma or etchant used during the removal of polysilicon layer20from damaging the gate insulating layer16underneath as the polysilicon layer20is emptied

Also, as part of the second spacer34is composed of silicon nitride, the present embodiment preferably removes part of the silicon nitride layer32of the second spacer34while the etching stop layer18is removed by the wet etching process, as shown inFIG. 4.

Moreover, as the etching stop layer18is preferably composed of silicon nitride, the first spacer26is preferably to be fabricated with a material having different etching selectivity from the etching stop layer18. By doing so, the wet etching process carried out to remove the silicon nitride etching stop layer18would not be used to damage the first spacer26adjacent to the etching stop layer18simultaneously.

Next, as shown inFIG. 5, a high-k dielectric layer42is formed in the opening40to cover the gate insulating layer16, the first spacer26, the second spacer34, and the interlayer dielectric layer38. In this embodiment, the high-k dielectric layer42is selected from HfSiO, HfSiON, HfO, LaO, LaAlO, ZrO, ZrSiO, HfZrO, or combination thereof.

Next, a work function metal layer (not shown) could be deposited selectively on the surface of the high-k dielectric layer42according to the nature of the transistor. If the transistor fabricated were to be a NMOS transistor, a n-type metal layer could be deposited on the high-k dielectric layer42, in which the n-type metal layer is selected from a group consisting of TiN, TaC, TaN, TaSiN, and Al. If the transistor fabricated were to be a PMOS transistor, a p-type metal layer could be deposited on the high-k dielectric layer42, in which the p-type metal layer is selected from a group consisting of TiN, W, WN, Pt, Ni, Ru, TaCN, and TaCNO.

Next, a conductive layer44composed of low resistance material is deposited on the high-k dielectric layer42and into the opening40. In this embodiment, the conductive layer44is selected from Al, W, TiAl, CoWP, or combination thereof. A chemical mechanical polishing process is conducted thereafter to remove a portion of the conductive layer44and high-k dielectric layer42on the first spacer26, second spacer34, and interlayer dielectric layer38to form a metal gate transistor in the transistor region14.

Overall, the present invention preferably forms an etching stop layer composed of silicon nitride between the gate insulating layer and the dummy polysilicon layer. By doing so, the etching stop layer could be used to protect the gate insulating layer from plasma or etchant used during the removal of polysilicon layer. As the gate insulating layer is protected from damage caused by the removal of the polysilicon layer, the present invention also eliminates the need of conducting an additional thermal oxidation to form another gate insulating layer, thereby reducing overall fabrication time and cost substantially.