Low jitter delay cell

A delay cell for a delay locked loop, DLL, based serial link is disclosed. The delay cell has a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter, R-DAC and the second stage comprising a current starved delay cell.

BACKGROUND

Field of the Disclosure

Presented herein is an apparatus for a programmable low-jitter delay cell suitable for use, for example, with delay locked loop, (DLL) based serial links.

Description of Related Art

Delay-cell jitter can be a significant limiting factor for achieving high data rates in a DLL (Delay Locked Loop) based serial link design. CMOS Transistor channel thermal in the delay cell noise is the primary source of jitter. A typical solution to this problem is to provide a power-noise trade-off. This is generally achieved by burning more current in the devices to reduce jitter. However, this is at the expense of increased power consumption. Current solutions involve the use of current starved delay cells, supply tuned delay cells or analog replica cells, however these solutions are limited by MOS device thermal noise.

It is therefore desirable to provide a topology which provides improved low jitter performance at low power.

SUMMARY

A delay cell for a delay locked loop, DLL, based serial link is provided, comprising: a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter, R-DAC and the second stage comprising a current starved delay-cell.

This hybrid delay cell combines an inherent lower jitter delay generation using an RDAC with an area efficient delay configurability in a current starved delay cell. Combining the two provides for a low jitter configurable delay generation at low power.

The first stage may comprise a first field effect transistor, FET, and a second field effect transistor, FET and wherein a drain of the first transistor may be coupled to a drain of the second FET, and wherein a gate of the first FET is coupled to a gate of the second FET and to the input. This first stage provides a lower level of jitter than a device based delay cell.

The delay cell may further comprise a first resistor coupled in series between a first voltage level and the source of the first FET and a second resistor coupled in series between a source of the second FET and a second voltage level.

The first FET may be a pFET and the second FET may be a nFET.

This first stage provides fixed delay, coarse tuning, providing for low jitter and low noise. The first stage provides low noise performance.

The second stage may comprise n sections coupled in series, each section comprising: a third field effect transistor, FET, and a fourth field effect transistor, FET, wherein a drain of the third FET is coupled to a drain of the fourth FET and to an output of the section, and wherein a gate of the third FET is coupled to a gate of the fourth FET and to an input of the section.

The second stage may further comprise a fifth FET, wherein a drain of the fifth FET is coupled to a source of the third FET, wherein a source of the fifth FET is coupled to a first voltage level and wherein a gate of the fifth FET is coupled to a third voltage level.

The second stage may further comprise a sixth FET, wherein a drain of the sixth FET is coupled to a source of the fourth FET, wherein a source of the sixth FET is coupled to a second voltage level and wherein a gate of the sixth FET is coupled to a fourth voltage level.

The third FET and the fifth FET may be pFET and the fourth FET and sixth FET may be nFET.

The number of sections n, may be greater than or equal to 3. It will be appreciated that this allows for varying the delay provided.

The output of the second stage may be coupled to the output of the nth section and the input to the second stage may be coupled to the input of the first section of the n sections.

The second stage provides fine control with a programmable current starved delay cell for fine tuning. The combination of the first stage providing coarse tuning and second stage providing fine tuning optimizes the performance of the delay line. The hybrid combination provides lower jitter than a conventional current starved delay cell at comparable power in a comparable process, for example a 7 nm process.

The delay cell may further comprise an inverter coupled to an output of the second stage.

The delay cell may be manufactured in accordance with a 7 nanometer lithography process. It will however be appreciated that the topology is not restricted as such.

A method of providing a delay cell for use in a delay locked loop, DLL based serial link is claimed herein, comprising: providing a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter and the second stage comprising a current starved delay-cell.

The first stage may comprise a first field effect transistor, FET, and a second field effect transistor, FET and wherein a drain of the first FET is coupled to a drain of the second FET, and wherein a gate of the first FET is coupled to a gate of the second FET and to the input.

The above method may further comprise coupling a first resistor in series between a first voltage level and the source of the first FET and a second resistor (204) coupled in series between a source of the second FET and a second voltage level.

The first FET may be a pFET and the second FET may be a nFET.

The second stage may comprise n sections coupled in series, each section comprising: a third field effect transistor, FET, and a fourth field effect transistor, FET, wherein a drain of the third FET is coupled to a drain of the fourth FET and to an output of the section, and wherein a gate of the third FET is coupled to a gate of the fourth FET and to an input of the section.

The second stage may further comprise a fifth FET, wherein a drain of the fifth FET is coupled to a source of the third FET, wherein a source of the fifth FET is coupled to a first voltage level and wherein a gate of the fifth FET is coupled to a third voltage level.

The second stage may further comprise a sixth FET, wherein a source of the sixth FET is coupled to a drain of the fourth FET, wherein a drain of the sixth FET is coupled to a source of the fourth FET, wherein a source of the sixth FET is coupled to a second voltage level and wherein a gate of the sixth FET is coupled to a fourth voltage level.

The third FET and the fifth FET may be pFET and the fourth FET and sixth FET may be nFET.

The number of sections n, may be greater than or equal to 3.

Each section of the plurality of sections may be serially coupled such that the input of the second stage is the input to a first section of the plurality of sections and the output of the second stage is the output of a final section of the plurality of sections.

The method may further comprise coupling an inverter to the output of the second stage.

In a further configuration there is provided a delay lock loop, DLL comprising a plurality of delay cells having the features as outlined above.

In a further configuration there is provided a serial link comprising the delay lock loop according to the present invention.

DETAILED DESCRIPTION

The invention will now be described with reference to the accompanying drawings.FIG.1is a representation of one example of a hybrid delay cell,100. The hybrid delay cell,100comprises a first stage,101and a second stage102is serially coupled to the first stage. The output of the first stage104is an input to the second stage102. In a preferred configuration, the first stage,101comprises a resistive digital to analog converter, R-DAC,201. The second stage comprises a current starved delay cell,301. Both the first and the second stages will be described in further detail below. The input to the first stage,101may be a clock signal. An output of the second stage is a delayed clock signal.

An exemplary configuration for the first stage,101is shown inFIG.2. The first stage,101comprises a first field effect transistor, FET,201. A second FET,202, is also provided. The drain of the first FET201is coupled to the drain of the second FET202. The output104from the first stage,101is coupled to the drain of the first FET and the drain of the second FET. The gates of the first FET201and second FET202are coupled together and to an input103. The first and second FETs form an inverter. A first resistor203is coupled to the source of the first FET201. The first resistor203is coupled in series between a first voltage level, Vddfx, provided by a first voltage input (not shown), and the source of the first FET,201. The first resistor203is a variable resistor. A second resistor,204is coupled to the source of the second FET202. The second resistor204is coupled in series between the source of the second FET,202, and a second voltage level, Vssfx. The second voltage level is provided at a second voltage input. The first FET is a pFET and the second FET is a nFET.

In one configuration Vssfx may be ground or 0V. Vddfx is a supply voltage and is variable depending on the relevant process technology used in the manufacture of the delay cell. For example for 6 nm to 14 nm processes Vddfx may be in the range of 0.7V to 0.9V.

While a single inverter section is shown in the first stage,101, it will be appreciated that the inverter configuration may be replicated to provide n sections where n>1.

Equivalent circuits for the first stage101are shown inFIG.3. While shown inFIG.3as a four-bit resistive digital to analog converter cell, it will be appreciated that circuit elements are readily repeatable to expand the resistive DAC cell.

In a first configuration, there is provided a first stage,101. The first stage101includes a first field effect transistor, FET,201. A second FET,202, is also provided. The drain of the first FET is coupled to the drain of the second FET. The output104from the first stage,101is coupled to the drain of the first FET and the drain of the second FET. The gates of the first and second FET are coupled together and to an input103. The first and second FET form an inverter. A first resistor203is coupled to the source of the first FET201. The first resistor203is coupled in series between a first voltage level, Vddfx, provided by a first voltage input (not shown), and the source of the first FET,201. The first resistor203may be a variable resistor. A second resistor,204is coupled to the source of the second FET. The second resistor204is coupled in series between the source of the second FET,202, and a second voltage level, Vssfx. The second voltage level is provided at a second voltage input. The first FET is a pFET and the second FET is a nFET.

In a second equivalent configuration, shown in3(b), the first resistor203is depicted as a 4-stage binary weighted resistive ladder or bank. The inverter comprising the first FET201and the second FET202is the same as that described in relation to3(a). The weighted resistors have values which are multiples of two. The resistor in the most significant bit position has the value R, the next has the value 2R, etc. It will be appreciated that this can be extended to 2N, where N is the number of bits (in this case4). Each resistor is coupled to a switching FET for switching in response to the respective digital input. In the configuration shown in3(b) the source of each switching FET is coupled to Vdd (Vddfx). The drain of the switching FET is coupled to the respective resistor in the ladder. Rdac[3:0] is provided to the gate. It will be appreciated that rdac_b as shown inFIG.3is an inversion of rdac[3:0].

Similarly, the second resistor204is depicted with a 4-stage binary weighted resistive ladder or bank. The weighted resistors have values which are multiples of two. The resistor in the most significant bit position has the value R, the next has the value 2R, etc. It will be appreciated that this can be extended to 2N. Each resistor is coupled to a switching FET for switching between binary 1 and 0. In the configuration shown in3(b) the source of each switching FET is coupled to ground. The drain of the switching FET is coupled to the respective resistor in the ladder. Rdac[3:0] is provided to the gate. It will be appreciated that rdac_b as shown inFIG.3is an inversion of rdac[3:0].

The configuration shown in3(c) provides an alternative equivalent arrangement where the position of the resistors and the switching transistors are switched. The first resistor203is depicted by a resistive ladder, where the resistor is coupled between Vdd and the source of its respective switching transistor. Similarly the second resistor is depicted by a resistive ladder where the resistor element is positioned between the source of the respective switching transistor and ground. As with the configurations of3b, the weighted resistors have values which are multiples of two. The resistor in the most significant bit position has the value R, the next has the value 2R, etc. It will be appreciated that this can be extended to 2N, where N is the number of bits (in this case4).

The equivalent circuit of3(d) positions the resistive ladder at the output of the inverter circuit formed by the first FET201and the second FET202. As with the equivalent circuits of3(b) and3(c), the resistors are weighted resistors having values which are multiples of two. The resistor in the most significant bit position has the value R, the next has the value 2R, etc. It will be appreciated that this can be extended to 2N, where N is the number of bits (in this case4).

An exemplary configuration of the second stage102is shown inFIG.4. The second stage comprises n sections. The n sections are serially coupled. In one configuration n is equal to three however, it will be appreciated that n is not restricted as such, and may also be greater than or less than three. The value n is chosen to optimize the performance of the second stage.

Each of the n sections includes a third FET301, and a fourth FET302. A drain of the third FET301is coupled to a drain of the fourth FET302and to an output303of the section. A gate of the third FET301is coupled to a gate of the fourth FET302and to an input of the section. Each of the n sections further includes a fifth FET,304. A drain of the fifth FET304is coupled to a source of the third FET301. The source of the fifth FET3040is coupled to the first voltage level, Vddfx. The gate of the fifth FET is coupled to a third voltage level, Vgp. The third voltage level is provided at a third voltage input. This third voltage level, Vgp may in one configuration, be in the range of 0.25V to 0.35V below Vddfx (supply voltage level).

A fourth voltage input is also provided. This fourth voltage input supplies the fourth voltage at a fourth voltage level. The fourth voltage level in one configuration is 0.25V to 0.35V above ground level. This fourth voltage is shown inFIG.4as Vgn

Each of the n sections further comprises a sixth FET,305. The drain of the sixth FET305is coupled to a source of the fourth FET302and a source of the sixth FET305is coupled to the second voltage level, Vssfx. A gate of the sixth FET305is coupled to the fourth voltage level.

In one configuration the third FET301and the fifth FET304are pFET and the fourth FET302and the sixth FET305are nFET.

The output of the second stage105is coupled to the output of the nth section of the n sections. The input to the second stage is the input to the first section of the n sections. The n sections of the second are serially coupled such that the output of one stage is the input to the following stage.

FIG.5provides an example of the delay cell comprising the first stage,101and the second stage where the first and second stage are serially coupled.

The first stage,101comprises a first FET,201. A second FET,202, is also provided. The drain of the first FET is coupled to the drain of the second FET. The output104from the first stage,101is coupled to the drain of the first FET201and the drain of the second FET202. The gates of the first FET201and second FET202are coupled together and to an input103. The first and second FET form an inverter. A first resistor203is coupled to the source of the first FET201. The first resistor203is coupled in series between a first voltage level, Vddfx, provided by a first voltage input (not shown), and the source of the first FET,201. The first resistor203is a variable resistor. A second resistor,204is coupled to the source of the second FET. The second resistor204is coupled in series between the source of the second FET,202, and a second voltage level, Vssfx. The second voltage level is provided at a second voltage input. The first FET is a pFET and the second FET is a nFET. The second stage comprises n sections. The n sections are serially coupled. In one configuration n is equal to three however, it will be appreciated that n is not restricted as such, and may also be greater than or less than three. The value n is chosen to optimize the performance of the second stage.

In one configuration Vssfx may be ground or 0V. Vddfx is a supply voltage and is variable depending on the relevant process technology used in the manufacture of the delay cell. For example for 6 nm to 14 nm processes Vddfx may be in the range of 0.7V to 0.9V.

The second stage comprises n sections. Each of the n sections includes a third FET301, and a fourth FET302. A drain of the third FET301is coupled to a drain of the fourth FET302and to an output303of the section. A gate of the third FET301is coupled to a gate of the fourth FET302and to an input of the section. Each of the n sections further includes a fifth FET,304. A drain of the fifth FET304is coupled to a source of the third FET301. The source of the fifth FET304is coupled to the first voltage level, Vddfx. The gate of the fifth FET is coupled to a third voltage level, Vgp. The third voltage level is provided at a third voltage input. This third voltage level, Vgp may in one configuration, be in the range of 0.25V to 0.35V below Vddfx (supply voltage level).

A fourth voltage input is also provided. This fourth voltage input supplies the fourth voltage at a fourth voltage level. The fourth voltage level in one configuration is 0.25V to 0.35V above ground level. This fourth voltage is shown inFIG.5as Vgn

Each of the n sections further comprises a sixth FET,305. The drain of the sixth FET305is coupled to a source of the fourth FET302and a source of the sixth FET305is coupled to the second voltage level, Vssfx. A gate of the sixth FET305is coupled to the fourth voltage level, Vgn.

In one configuration the third FET301and the fifth FET304are pFET and the fourth FET302and the sixth FET305are nFET.

In one configuration, Vssfx may be ground or 0V. Vddfx is a supply voltage and is variable depending on the relevant process technology used in the manufacture of the delay cell. For example for 6 nm to 14 nm processes Vddfx may be in the range of 0.7V to 0.9V.

In the configuration ofFIG.5a first inverter401is coupled to the output of the second stage providing a first output of the delay cell. A second inverter402serially coupled to the first inverter provides a second output of the delay cell. The first and second inverters are coupled between the supply voltage, Vddfx and the ground voltage Vssfx.

An example circuit for a delay locked loop (DLL)500incorporating a N-stage delay line501is shown inFIG.6. It will be appreciated that a DLL of the configuration shown inFIG.6may have applications in DLL based serializer/deserializer (SerDes), DLL based clock multipliers, time to digital converters or the like.

Each delay stage in the N-stage delay line in the configuration ofFIG.6, includes a p-bit first stage, e.g., p-bit coarse DAC (first stage) in each delay line stage and a q-bit fine current-starved delay element (second stage) in each delay line stage. The first and second stages ofFIG.6may be implemented using the cell configuration ofFIGS.2,3,4and5.

The input to the DLL ofFIG.6is the input clock Clk_in. The input to the N stage delay line is shown as Clk_in and the output from the N-stage delay line is a phase shifted output clock signal, Phi_out having multiple phases spanning one clock generation period. The phase detector503is configured to sense the phase difference between the output of the N-stage delay line and the input clock, Clk_in. The loop filter502controls the N-stage delay line according to the sensed phase difference. The first stage may be implemented in accordance with any of the configurations shown inFIG.2orFIG.3where N=p in the resistive ladders of the equivalent circuits ofFIG.3.

The hybrid combination proposed herein provides lower jitter than a conventional current starved delay cell at comparable power in a comparable process. For example in a 7 nm lithography process, at 250 uA in a 10 Gbps serializer, it is anticipated that the present combination provides approximately 3 times less jitter than a current starved delay cell at comparable power. While a 7 nm lithography process is provided as an example, it will be appreciated that the topology for a delay cell provided herein is applicable to other processes.

As shown inFIG.7, there is also provided herein a method of providing a delay cell for use in a delay locked loop, DLL based serial link, comprising: providing a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter and the second stage comprising a current starved delay-cell.