Semiconductor device and manufacturing method of the same

After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H2, thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese Patent Application No. JP 2007-316545 filed on Dec. 7, 2007, the content of which is hereby incorporated by reference into this application.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor device and a manufacturing method of the same, and more particularly to a technology effectively applied to a semiconductor device provided with a complementary MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a manufacturing method of the same.

BACKGROUND OF THE INVENTION

Japanese Patent Application Laid-Open Publication No. 2003-282875 (Patent Document 1) discloses a complementary MISFET that uses an aluminum oxide (Al2O3) film as its gate insulating film and a manufacturing process thereof.

SUMMARY OF THE INVENTION

In recent years, with the increasing demands for high integration of semiconductor devices including the MISFET, it is required to minutely process a semiconductor device. Since the characteristics of the MISFET are influenced by the electrostatic capacitance of its gate insulating film, in order to have the same characteristics even when the MISFET is minutely processed, it is required to process the MISFET so that the electrostatic capacitance of the gate insulating film is not changed. Since the area of the gate insulating film becomes small with the microfabrication, in order to maintain the electrostatic capacitance thereof, the method of reducing the film thickness of the gate insulating film is employed.

Here, when a silicon oxide film is selected as a gate insulating film, there is a fear of occurrence of the so-called tunnel current, in which electrons flowing in a channel penetrate through a barrier wall formed of the gate insulating film due to the reduction in film thickness and flow into the gate electrode. Therefore, the method has been examined in which a thin film with a larger dielectric constant than that of a silicon oxide film (hereinafter, referred to as a high dielectric constant film) is used as a gate insulating film so as to maintain the electrostatic capacitance of the gate insulating film without reducing the film thickness in comparison with the case of using a silicon oxide film.

Meanwhile, when the complementary MISFET is manufactured by use of such a high dielectric constant film as its gate insulating film, suitable high dielectric constant films and gate electrode materials are respectively selected for a p-channel MISFET and an n-channel MISFET, thereby realizing the threshold voltages required for the respective ones. Therefore, it is difficult to easily realize the threshold voltages required for both the p-channel MISFET and the n-channel MISFET.

An object of the present invention is to provide a complementary MISFET that uses a high dielectric constant film as its gate insulating film and can easily realize the threshold voltages required for both the p-channel MISFET and the n-channel MISFET, and a manufacturing method of the same.

The above and other objects and novel characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

The typical ones of the inventions disclosed in this application will be briefly described as follows.

(1) A semiconductor device according to the present invention is a semiconductor device comprising: a MISFET having a first gate insulating film whose dielectric constant is relatively larger than that of silicon oxide and a first gate electrode including a first metal film having a reduction catalyst effect to hydrogen on a main surface of a semiconductor substrate,

wherein the first gate insulating film is formed by laminating an silicon oxide layer, an oxygen deficiency adjustment layer, and a high dielectric constant layer whose dielectric constant is relatively larger than that of the silicon oxide layer in this order from below, and

the oxygen deficiency adjustment layer is an oxide containing 2A group elements, 3A group elements, 3B group elements, 4A group elements, or 5A group elements.

(2) Also, a manufacturing method of a semiconductor device according to the present invention is a manufacturing method of a semiconductor device having a complementary MISFET, the method comprising the steps of:

(a) forming a silicon oxide layer on a main surface of a semiconductor substrate;

(b) forming an oxygen deficiency adjustment layer on the silicon oxide layer;

(c) removing the oxygen deficiency adjustment layer in a second region on the main surface of the semiconductor substrate, while leaving the oxygen deficiency adjustment layer in a first region on the main surface of the semiconductor substrate;

(d) after the step (c), forming a high dielectric constant layer whose dielectric constant is relatively larger than that of the silicon oxide layer on the main surface of the semiconductor substrate;

(e) forming a first metal film having a reduction catalyst effect to hydrogen on the high dielectric constant layer in the first region;

(f) forming a second metal film on the high dielectric constant layer in the second region;

(g) after the step (e), performing a heat treatment to the semiconductor substrate;

(h) forming a compound film of silicon and a metal on the first metal film in the first region and on the second metal film in the second region; and

(i) patterning the compound film, the first metal film, the high dielectric constant layer, the oxygen deficiency adjustment layer and the silicon oxide layer, thereby forming a first gate electrode and a first gate insulating film of a p-channel MISFET in the first region, and patterning the compound film, the second metal film, the high dielectric constant layer, and the silicon oxide layer, thereby forming a second gate electrode and a second gate insulating film of an n-channel MISFET in the second region,

wherein the oxygen deficiency adjustment layer is an oxide containing 2A group elements, 3A group elements, 3B group elements, 4A group elements, or 5A group elements.

Further, a manufacturing method of a semiconductor device according to the present invention is a manufacturing method of a semiconductor device having a complementary MISFET, the method comprising the steps of:

(a) forming a silicon oxide layer on a main surface of a semiconductor substrate;

(b) forming an oxygen deficiency adjustment layer on the silicon oxide layer;

(c) after the step (b), forming a high dielectric constant layer whose dielectric constant is relatively larger than that of the silicon oxide layer on the main surface of the semiconductor substrate;

(d) forming a first metal film having a reduction catalyst effect to hydrogen on the high dielectric constant layer in the first region and the second region on the main surface of the semiconductor substrate;

(e) after the step (d), forming a second metal film on the first metal film in the second region;

(f) after the step (e), performing a heat treatment to the semiconductor substrate;

(g) forming a compound film of silicon and a metal on the first metal film in the first region and on the second metal film in the second region; and

(h) patterning the compound film, the second metal film, the first metal film, the high dielectric constant layer and the silicon oxide layer, thereby forming a first gate electrode and a first gate insulating film of an n-channel MISFET in the second region, and patterning the compound film, the first metal film, the high dielectric constant layer, the oxygen deficiency adjustment layer and the silicon oxide layer, thereby forming a second gate electrode and a second gate insulating film of a p-channel MISFET in the first region,

wherein the oxygen deficiency adjustment layer is an oxide containing 2A group elements, 3A group elements, 3B group elements, 4A group elements, or 5A group elements.

The effects obtained by typical aspects of the present invention will be briefly described below.

It is possible to easily control the threshold voltage of a complementary MISFET using a high dielectric constant film as its gate insulating film.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

In the embodiments described below, the invention will be described in a plurality of sections or embodiments when required as a matter of convenience. However, these sections or embodiments are not irrelevant to each other unless otherwise stated, and the one relates to the entire or a part of the other as a modification example, details, or a supplementary explanation thereof.

Also, in the embodiments described below, when referring to the number of elements (including number of pieces, values, amount, range, and the like), the number of the elements is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle, and the number larger or smaller than the specified number is also applicable.

Further, in the embodiments described below, it goes without saying that the components (including element steps) are not always indispensable unless otherwise stated or except the case where the components are apparently indispensable in principle. Also, even when mentioning that constituent elements or the like are “made of A” or “comprise A” in the embodiments below, elements other than A are not excluded except the case where it is particularly specified that A is the only element.

Similarly, in the embodiments described below, when the shape of the components, positional relation thereof, and the like are mentioned, the substantially approximate and similar shapes and the like are included therein unless otherwise stated or except the case where it can be conceived that they are apparently excluded in principle. The same goes for the numerical value and the range described above.

Further, when referring to the material or the like, the specified material is a main material thereof unless otherwise stated or except the case where it is not so in principle and in situation, and other subsidiary element, additives, additional elements and others are not excluded. For example, a silicon member contains not only pure silicon but also additive impurities and binary and ternary alloys mainly made of silicon (for example, SiGe) unless otherwise stated.

Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

Also, in the drawings used in the embodiments, hatching is used in some cases even in a plan view so as to make the drawings easy to see.

First Embodiment

A semiconductor device according to a first embodiment is, for example, a semiconductor device having a complementary MISFET. Such a semiconductor device according to the first embodiment and a manufacturing method of the same will be described with reference toFIG. 1toFIG. 17.

First, as shown inFIG. 1, a semiconductor substrate made of, for example, p-type single crystal silicon (hereinafter, simply referred to as a substrate)1is prepared. In the cross section of the substrate1shown inFIG. 1, a region in which an n-channel MISFET is formed (second region) ANM and a region in which a p-channel MISFET is formed (first region) APM are shown.

Subsequently, element isolation trenches2are formed in the element isolation region of the main surface of the substrate1. The element isolation trenches2are formed by, for example, forming trenches in the main surface of the substrate1by dry etching, depositing an insulating film such as a silicon oxide film on the substrate1including the insides of the trenches by the CVD method, and then polishing and removing the unnecessary silicon oxide film outside the trenches by the chemical mechanical polishing (CMP) method to leave the silicon oxide film inside the trenches.

Then, an n-type impurity (for example, P (phosphorous)) is ion implanted into the main surface of the substrate1in the region APM, and a p-type impurity (for example, B (boron)) is ion implanted into the main surface of the substrate1in the region ANM. Subsequently, the substrate1is subjected to a heat treatment so that these impurities are diffused in the substrate1, thereby forming an n-type well3in the main surface of the substrate1in the region APM and a p-type well4in the main surface of the substrate1in the region ANM.

Then, the main surface of the substrate1(the n-type well3and the p-type well4) is wet cleaned by use of hydrofluoric-acid-based cleaning solution, and thereafter, a pure silicon oxide film5is formed on the respective surfaces of the n-type well3and the p-type well4by thermal oxidation.

Next, as shown inFIG. 2, by use of the ALD (Atomic Layer Deposition) method, an Al2O3film with the film thickness of approximately 0.5 nm is formed on the main surface of the substrate1to form an oxygen deficiency adjustment layer6. As this oxygen deficiency adjustment layer6, a single layer film, a lamination film, or an alloy film of oxides of 2A group elements (for example, MgO, CaO, SrO and BaO), oxides of 3A group elements (for example, Y2O3and La2O3), oxides of 3B group elements, oxides of 4A group elements (for example, HfO2), oxides of 5A group elements and the like may be employed besides the Al2O3film. The oxygen deficiency adjustment layer6is left only in the region APM in the later process, and the material of the oxygen deficiency adjustment layer6can be appropriately selected in accordance with the characteristics of the p-channel MISFET to be manufactured.

Then, the oxygen deficiency adjustment layer6other than that on the n-type well3(region APM) is etched and removed with using a photoresist film7patterned by photolithography technique as a mask.

Next, as shown inFIG. 3, an HfO2film is formed on the main surface of the substrate1by, for example, the ALD method, and a high dielectric constant film (high dielectric constant layer)8to be the gate insulating film of the complementary MISFET is formed. Then, a PDA (Post Deposition Anneal) process at, for example, approximately 850° C. is performed to the substrate1.

Next, as shown inFIG. 4, after covering the regions other than the region ANM with the photoresist film9patterned by the photolithography technique, a tantalum nitride film (second metal film)10with the film thickness of, for example, approximately 20 nm is deposited on the main surface of the substrate1. Although illustration thereof is omitted, the tantalum nitride film10of the regions other than the region ANM can be removed by removing the photoresist film9thereafter (so-called lift-off method).

Next, after removing the tantalum nitride film10of the regions other than the region ANM by removing the photoresist film9, as shown inFIG. 5, the regions other than the region ANM are covered with a photoresist film11patterned by the photolithography technique, and then, a Pt (platinum) film with the film thickness of, for example, approximately 20 nm is formed on the main surface of the substrate1as a conductive film having an reduction catalyst effect to hydrogen (first metal film)12. In the first embodiment, although a Pt film is used as an example of the conductive film12that has the reduction catalyst effect to hydrogen, it is also preferable to use a Re (rhenium) film or a lamination film of a Pt film and a Re film.

Next, as shown inFIG. 6, the conductive film12of the regions other than the region APM is removed by removing the photoresist film11by the liftoff method.

Then, the substrate1is heat treated at approximately 450° C. in the atmosphere containing approximately 3% of H2(hydrogen). By this means, it is possible to control the effective work function of the p-channel MISFET to be completed at a later process. This principle will be described in detail below.

As mentioned above, the conductive film12has the reduction catalyst effect to hydrogen, and as shown inFIG. 7, O (oxygen) that composes the high dielectric constant film8formed of an HfO2film is reduced to generate H2O (water) by the heat treatment in the atmosphere containing approximately 3% of H2. Although the high dielectric constant film8has a composition in which O is deficient by the reduction, O is taken in from the underlying oxygen deficiency adjustment layer6formed of the Al2O3film, thereby compensating the deficiency of O. Therefore, the oxygen deficiency adjustment layer6has a composition in which O is deficient, and a dipole (2e−, Vo2+) is formed between the oxygen deficiency adjustment layer6and the silicon oxide film5.

Herein,FIG. 8shows the relation between the temperature in the heat treatment in which the above-described reduction to hydrogen is performed and the effective work function φm, eff (eV) of the p-channel MISFET to be completed at a later process, in which the case where Al2O3described with reference toFIG. 2is used for the oxygen deficiency adjustment layer6, the case where HfO2is used therefor, and the case where Y2O3is used therefor are shown. InFIG. 8, 400° C. to 600° C. is shown as the range of the actually measured temperature of the heat treatment, and this is because these temperatures are the upper limit and the lower limit at which the reduction catalyst effect to hydrogen of the conductive film12can be acquired. Further,FIGS. 9 and 10show the relation between the temperature in the heat treatment in which the above-described reduction to hydrogen is performed and the change amount (AVFB (V)) of the flat band voltage (threshold voltage) VFB(V) of the p-channel MISFET to be completed at a later process (with 400° C. as a reference). InFIG. 9, the case where Al2O3described with reference toFIG. 2is used for the oxygen deficiency adjustment layer6, the case where SiO2(silicon oxide) is used therefor, the case where HfO2is used therefor, and the case where the lamination film of Al2O3and HfO2is used therefor (two cases where Al2O3is the upper layer and Al2O3is the lower layer) are shown. InFIG. 10, the case where Al2O3described with reference toFIG. 2is used for the oxygen deficiency adjustment layer6, the case where SiO2(silicon oxide) is used therefor, the case where Y2O3is used therefor, and the case where the lamination film of Al2O3and Y2O3is used therefor (two cases where Al2O3is the upper layer and Al2O3is the lower layer) are shown. Note thatFIG. 9shows the case where the PDA processing temperature after the formation of the high dielectric constant film8(refer to the description with reference toFIG. 2) is 850° C., andFIG. 10shows the case where the PDA processing temperature after the formation of the high dielectric constant film8(refer to the description with reference toFIG. 2) is 650° C. Moreover, inFIG. 11, the change of the work function φm (eV) of the p-channel MISFET by the formation of the dipole (2e−, Vo2+) between the oxygen deficiency adjustment layer6and the silicon oxide film5is shown by use of an energy band, and the effective work function φm, eff (eV) is also shown. Note that VL, Ev, and Ec inFIG. 11show the vacuum level, the conduction band, and the valence band, respectively. Furthermore,FIG. 12shows the relation between the gate voltage of the p-channel MISFET by the formation of the dipole (2e−, Vo2+) between the oxygen deficiency adjustment layer6and the silicon oxide film5and the capacitance value between the gate electrode and the substrate1(n-type well3), in which a graph in the case where the dipole (2e−, Vo2+) is formed and a graph in the case where the dipole (2e−, Vo2+) is not formed are shown.

As shown inFIGS. 8 to 12mentioned above, by the heat treatment in the atmosphere containing H2(hydrogen) after the formation of the conductive film12having the reduction catalyst effect to hydrogen, the above-described dipole (2e−, Vo2+) caused by the oxygen deficiency (Vo) of the oxygen deficiency adjustment layer6that is in contact with the silicon oxide film5is formed, and the effective work function φm, eff (eV) of the p-channel MISFET falls, and the flat band voltage (threshold voltage) also falls. Moreover, as shown inFIGS. 8 to 10, when the magnitudes of the changes of the flat band voltage (threshold voltage) of the p-channel MISFET to the changes of the temperature of the heat treatment in the atmosphere containing H2(hydrogen) after the formation of the conductive film12are compared with regard to the main materials used as the oxygen deficiency adjustment layer6, the relation Al2O3>HfO2>Y2O3is established. When the p-channel MISFET formed on the main surface of the substrate1made of single crystal silicon forms the complementary MISFET, the effective work function is, for example, approximately 4.95 eV to 5.15 eV, and it is found fromFIG. 8that it is preferable to use Al2O3or HfO2as the oxygen deficiency adjustment layer6. More specifically, when the high dielectric constant film8like an HfO2film is used as a gate insulating film, by appropriately selecting the material of the oxygen deficiency adjustment layer6and the temperature of the heat treatment in the atmosphere containing H2(hydrogen) after the formation of the conductive film12, the flat band voltage (threshold voltage) of the p-channel MISFET can be precisely controlled in a wide range, and a desired flat band voltage (threshold voltage) of the p-channel MISFET can be obtained.

Next, as shown inFIG. 13, after depositing an amorphous silicon film on the substrate1, the amorphous silicon film is heat treated, thereby forming a polycrystalline silicon film13. Herein, the polycrystalline silicon film may be deposited by, for example, the CVD method while omitting the deposition of the amorphous silicon film. The above-described heat treatment in the atmosphere containing H2(hydrogen) after the formation of the conductive film12may be carried out immediately after the formation of this polycrystalline silicon film13.

Next, as shown inFIG. 14, the polycrystalline silicon film13, the conductive film12, the tantalum nitride film10, the high dielectric constant film8, the oxygen deficiency adjustment layer6, and the silicon oxide film5are etched with using a photoresist film (not illustrated) patterned by the photolithography technique as a mask. By this means, a gate electrode16A formed of the tantalum nitride film10and the polycrystalline silicon film13and a gate insulating film (second gate insulating film)17A formed of the silicon oxide film5and the high dielectric constant film8are formed in the region ANM, and a gate electrode16B formed of the conductive film12and the polycrystalline silicon film13and a gate insulating film (first gate insulating film)17B formed of the silicon oxide film5, the oxygen deficiency adjustment layer6, and the high dielectric constant film8are formed in the region APM.

Next, as shown inFIG. 15, for example, B is ion implanted into the n-type well3as a p-type impurity, thereby forming comparatively low-concentration p−type semiconductor regions18, and P or As is ion implanted into the p-type well4as an n-type impurity, thereby forming comparatively low-concentration n−type semiconductor regions19. The p−type semiconductor regions18and the n−type semiconductor regions19are formed in order to make the LDD (Lightly Doped Drain) structure for the source and drain of the p-channel MISFET and the n-channel MISFET.

Then, sidewall spacers20formed of an insulating film are formed on the sidewalls of the gate electrodes16A and16B. The sidewall spacers20are formed by depositing a silicon oxide film on the substrate1by, for example, the CVD method and then anisotropically etching this silicon oxide film.

Next, B is ion implanted into the n-type well3as a p-type impurity, thereby forming comparatively high-concentration p+type semiconductor regions21, and P or As is ion implanted into the p-type well4as an n-type impurity, thereby forming comparatively high-concentration n+type semiconductor regions22. The p+type semiconductor regions21and the n+type semiconductor regions22constitute the source and drain of the p-channel MISFET and the n-channel MISFET, respectively. Through the processes so far, a p-channel MISFET Qp and an n-channel type MISFET Qn can be formed. The heat treatment process at approximately 1000° C. or more for activating the introduced impurities may be performed respectively at the fabrication process of the p−type semiconductor regions18and the n−type semiconductor regions19and the fabrication process of the p+type semiconductor regions21and the n+type semiconductor regions22or collectively at the end of the processes as long as these semiconductor regions can be formed.

Next, as shown inFIG. 16, after depositing an embedding silicon oxide film on the entire surface of the above-described transistor element structure by, for example, the CVD method, the film is planarized by the CMP technique so as to expose the upper surface of the polycrystalline silicon film13. The heat treatment in the atmosphere containing H2(hydrogen) may be performed at this stage.

Then, on the polycrystalline silicon film13, for example, an Ni (nickel) film is deposited to form a metal film. As this metal film, a Ti (titanium) film, a W (tungsten) film, a Ta (tantalum) film, a nickel (Ni) film, a Pt (platinum) film, or a Ru (ruthenium) film may be employed besides the Ni film. Subsequently, the substrate1is heat treated at approximately 400° C. for around 10 minutes to react the metal film with the polycrystalline silicon film13, thereby forming a metal silicide film (compound film)15. Then, the unreacted metal film is removed by wet etching or the like.

The p-channel MISFET Qp and the n-channel MISFET Qn of the first embodiment formed as mentioned above include the high dielectric constant film8, the dielectric constant of which is higher than that of the silicon oxide film, in the gate insulating films17A and17B, and therefore, it is possible to keep the electrostatic capacitance of the gate insulating films17A and17B without reducing the film thickness in comparison with the case where an silicon oxide film is used. Accordingly, since it is possible to restrain the occurrence of the tunnel current in the gate insulating films17A and17B, it becomes possible to save the power consumption of the p-channel MISFET Qp and the n-channel MISFET Qn.

Next, as an insulating film to cover the p-channel MISFET Qp and the n-channel MISFET Qn, a silicon oxide film23is deposited by, for example, the CVD method, and the surface of the silicon oxide film23is planarized by the chemical mechanical polishing method.

Next, the silicon oxide film23is dry etched with using the photoresist film as a mask, thereby forming contact holes24on the sources and drains of the p-channel MISFET Qp and the n-channel MISFET Qn (the p+type semiconductor regions21and the n+type semiconductor regions22). Then, plugs25are formed in the contact holes24. The plugs25are formed by, for example, depositing a Ti film and a TiN (titanium nitride) film by the sputtering method on the silicon oxide film23including the inside of the contact holes24, depositing a TiN film and a W film as a metal film by the CVD method, and then removing the W film, the TiN film, and the Ti film outside the contact holes24by the chemical mechanical polishing method.

Subsequently, by forming wirings26on the silicon oxide film23and the plugs25, the semiconductor device of the first embodiment is manufactured. The wirings26are formed by, for example, sequentially depositing a Ti film, an Al (aluminum) alloy film, and a TiN film on the silicon oxide film23by the sputtering method, and then patterning the Ti film, the Al alloy film and the TiN film by the dry etching using the photoresist film as a mask.

Note that wirings may be formed in multiple layers by repeating the process of forming the plugs25and the wirings26.

Second Embodiment

A semiconductor device according to a second embodiment also has a complementary MISFET similarly to the semiconductor device according to the first embodiment. Hereinafter, the semiconductor device according to the second embodiment and a manufacturing method of the same will be described with reference toFIG. 17toFIG. 21.

The manufacturing processes of the semiconductor device of the second embodiment are the same as those of the first embodiment up to the process of forming the oxygen deficiency adjustment layer6described in the first embodiment (refer toFIG. 2). Thereafter, as shown inFIG. 17, a high dielectric constant film8that is the same as the high dielectric constant film8described in the first embodiment (also refer toFIG. 3) is formed on the main surface of the substrate1.

Next, as shown inFIG. 18, a conductive film12that is the same as the conductive film12having the reduction catalyst effect to hydrogen described in the first embodiment (also refer toFIG. 5) is formed on the main surface of the substrate1.

Subsequently, as shown inFIG. 19, after covering the regions other than the region ANM with a photoresist film (not illustrated) patterned by the photolithography technique, a tantalum nitride film10with the film thickness of approximately 20 nm is deposited on the conductive film12. Then, the tantalum nitride film10of the regions other than the region ANM is removed by the lift-off method. In other words, by removing the above-mentioned photoresist film, the tantalum nitride film10of the regions other than the region ANM is removed.

Then, the substrate1is heat treated at approximately 450° C. in the atmosphere containing approximately 3% of H2(hydrogen). By this means, based on the same principle as that in the case of the p-channel MISFET Qp described in the first embodiment, it is possible to control the effective work function also in the n-channel MISFET Qn formed in the region ANM. More specifically, the conductive film12has the reduction catalyst effect to hydrogen, and O (oxygen) that composes the high dielectric constant film8is reduced to generate H2O (water) by the heat treatment in the atmosphere containing approximately 3% of H2. Although the high dielectric constant film8has a composition in which O is deficient by the reduction, O is taken in from the underlying oxygen deficiency adjustment layer6, thereby compensating the deficiency of O. Therefore, the oxygen deficiency adjustment layer6has a composition in which O is deficient, and a dipole (2e−, Vo2+) is formed between the oxygen deficiency adjustment layer6and the silicon oxide film5. As a result, as described with reference toFIG. 8toFIG. 12in the first embodiment, it is possible to control the effective work function of the MISFET, and in the case of the n-channel MISFET Qn, it is possible to reduce the effective work function and also reduce the flat band voltage (threshold voltage). In other words, it is possible to obtain a desired flat band voltage (threshold voltage) of the n-channel MISFET Qn.

Next, as shown inFIG. 20, after forming the polycrystalline silicon film13through the same process as that described with reference toFIG. 13andFIG. 14in the first embodiment, the polycrystalline silicon film13, the conductive film12, the tantalum nitride film10, the high dielectric constant film8, the oxygen deficiency adjustment layer6, and the silicon oxide film5are etched with using the photoresist film (not illustrated) patterned by the photolithography technique as a mask. By this means, a gate electrode (first gate electrode)16A formed of the tantalum nitride film10, the polycrystalline silicon film13, and the conductive film12and a gate insulating film (first gate insulating film)17A formed of the silicon oxide film5, the oxygen deficiency adjustment layer6, and the high dielectric constant film8are formed in the region ANM, and a gate electrode (second gate electrode)16B formed of the conductive film12and the polycrystalline silicon film13and a gate insulating film (second gate insulating film)17B formed of the silicon oxide film5, the oxygen deficiency adjustment layer6, and the high dielectric constant film8are formed in the region APM. By forming the respective gate electrodes16A and16B and the gate insulating films17A and17B of the p-channel MISFET Qp and the n-channel MISFET Qn through such processes, the materials of the gate electrode and the gate insulating film can be shared by the p-channel MISFET Qp and the n-channel MISFET Qn (except for the tantalum nitride film10). Accordingly, it becomes possible to control the threshold voltage of the complementary MISFET in a wide range and precisely, while preventing the increase in the number of manufacturing processes.

Thereafter, through the same process as that described with reference toFIG. 15andFIG. 16in the first embodiment, the semiconductor device according to the second embodiment is manufactured (refer toFIG. 21).

Third Embodiment

A semiconductor device according to a third embodiment has a complementary MISFET formed by use of an SOI (Silicon On Insulator) substrate. Hereinafter, the semiconductor device according to the third embodiment and a manufacturing method of the same will be described with reference toFIG. 22toFIG. 24.

As shown inFIG. 22, the SOI substrate used in the third embodiment is formed by bonding a base substrate1A made of, for example, single crystal silicon and a bond substrate made of single crystal silicon and having a silicon oxide film formed on its surface, and the silicon oxide film on the surface of the bond substrate serves as a BOX (Buried Oxide) layer1B and the single crystal silicon part of the bond substrate serves as an SOI layer1C.

After forming element isolation trenches2in the SOI layer1C of the SOI substrate through the same process as that described with reference toFIG. 1in the first embodiment, for example, U trenches that reach the BOX layer1B are formed in the main surface of the SOI substrate and an silicon oxide film is embedded in the trenches, thereby forming U-trench element isolation regions2A. Thereafter, an n-type well3is formed in the SOI layer1C of the region APM, and a p-type well4is formed in the SOI layer1C of the region ANM. The process to form these n-type well3and p-type well4is same as that in the first embodiment (refer toFIG. 1).

A cross section showing the principal part at the time when the gate electrodes16A and16B and the gate insulating films17A and17B are formed thereafter through the same process as that described in the first embodiment (refer toFIGS. 1 to 6,FIG. 13, andFIG. 14) is shown inFIG. 23, and a cross section showing the principal part at the time when the gate electrodes16A and16B and the gate insulating films17A and17B are formed through the same process as that described in the second embodiment (refer toFIGS. 17 to 20) is shown inFIG. 24.

In the complementary MISFET formed by use of the SOI substrate, the effective work function is, for example, approximately 4.4 eV to 4.8 eV. Therefore, in the case where the flat band voltage (threshold voltage) of the p-channel MISFET is to be controlled, it is preferable that the structure shown inFIG. 23is employed, Al2O3or HfO2is used as the oxygen deficiency adjustment layer6, and the temperature of the heat treatment in the atmosphere containing H2(hydrogen) after the formation of the conductive film12is set to approximately 500° C. to 600° C. from the graph shown inFIG. 8in the first embodiment. On the other hand, in the case where the flat band voltage (threshold voltage) of the n-channel MISFET is to be controlled, it is preferable that the structure shown inFIG. 24is employed, Y2O3is used as the oxygen deficiency adjustment layer6, and the temperature of the heat treatment in the atmosphere containing H2(hydrogen) after the formation of the conductive film12is set to approximately 400° C. to 600° C. from the graph shown inFIG. 8in the first embodiment.

After forming the gate electrodes16A and16B and the gate insulating films17A and17B, through the same processes as those described with reference toFIG. 15andFIG. 16in the first embodiment, the semiconductor device according to the third embodiment can be manufactured.

The semiconductor device and the manufacturing method of the same according to the present invention can be widely applied to the semiconductor device provided with a complementary MISFET and the manufacturing processes thereof.