Fuse-fetching circuit and method for using the same

A fuse-fetching circuit comprises a plurality of fuses, a plurality of first switches and a shift register. Each of the first switches includes a first data end, a second data end and a control end. The first data end is connected to the fuse, and the control end is controlled by a fuse-fetching signal. The shift register includes a plurality of registers, each of which includes a first latch, a first transmission gate, a second latch and a second transmission gate. The first latch is connected to the second data end of the first switch.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a fuse-fetching circuit, and more particularly, to a highly cost-effective fuse-fetching circuit.

2. Description of the Related Art

Fuses have been widely used in memory devices or consumer product integrated circuits (ICs) to store operations of a semiconductor component. For example, ID fuses are embedded in memory devices or consumer product ICs to record the manufacturing process, such as wafer lot number, positions on the X-axis and Y-axis of the wafer from which the dies of the memory devices or consumer product IC come. Another common practice is that if memory devices install internal recovery circuits, the fuses are used to record (melted and blown by a laser) the locations of defective memory cells. Since there are usually more ID fuses than the output pins of a semiconductor component upon a test mode, serial output from a single or a few pins is commonly seen. After the supply voltage is switched on, the fuse information is read one by one through the single or a few pins.

U.S. Pat. No. 6,215,351 discloses a traditional fuse-latch circuit, which needs additional delay element and latch element to store or control the fuse information, and thus its hardware is costly. U.S. Pat. No. 7,091,564 discloses another traditional fuse-fetching circuit. Please refer toFIG. 1. A fuse unit10includes a fuse11, a latch circuit12and a transfer circuit13, and many fuse units10are repeated and arranged in a row to form a fuse unit group. Signals bBP, AN and bTR are used to control or initiate the fuse unit10. Before the latch information is read, the signal bBP is initiated to reset the latch12. Then the signal AN is turned on to load the content of the fuse11into the latch12. Next, the signal bTR is initiated to load the content of the latch12into the transfer circuit13. Following each transition of the shifting clock, the fuse information is captured by an external controller. Although the fuse unit10can complete the fuse-fetch tasks, its hardware is too costly. Because the structure of the fuse unit10is replicated repeatedly to form the fuse unit group, it is necessary to develop a more cost-effective structure of the fuse unit10to save the space in the chip area.

SUMMARY OF THE INVENTION

The above-mentioned problems are addressed by the present invention. The structure and method of the present invention will be understood according to the disclosure of the following specification and drawings.

According to one embodiment of the present invention, the fuse-fetching circuit comprises a plurality of fuses, a plurality of first switches and a shift register. Each of the first switches includes a first data end, a second data end and a control end. The first data end is connected to the fuse, and the control end is controlled by a fuse-fetching signal. The shift register includes a plurality of registers, each of which includes a first latch, a first transmission gate, a second latch and a second transmission gate. The first latch is connected to the second data end of the first switch.

According to one embodiment of the present invention, the fuse-fetching circuit comprises a plurality of fuses, a shift register and a plurality of first switches. The shift register includes a plurality of registers. The first switches couple the fuses to the registers.

According to one embodiment of the present invention, the method for using a fuse-fetching circuit comprises the steps of: resetting a shift register, which has a plurality of registers; receiving a fuse-fetching signal from a controller to turn on first switches, which couple fuses to the registers; loading the contents of the fuses into the registers in parallel; and serially reading the shift register to obtain the contents of the fuses.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2(a) shows a fuse-fetching circuit20in accordance with the present invention. The fuse-fetching circuit20includes a shift register29, first switches24, second switches25and fuses28. The shift register29includes a plurality of registers21, and each register21includes a first latch22, a first transmission gate26, a second latch23and a second transmission gate27. The first transmission gate26and the second transmission gate27are controlled by a clock K and its reverse clock KN. When clock K is at logic high, the transmission gate26passes the content of the first latch22to the second latch23. When the reverse clock KN is at logic high, the transmission gate27passes the content of the second latch23to the first latch22of the next register21. The second switch25, a PMOS transistor, directly couples voltage power to the first latch22of the register21. The second switch25is controlled by a reset signal from a controller (not shown). Before the fuses are read, the content of the shift register29is filled with logic high signals so as to differentiate it from the fuse content, which is arranged in a logic low state. The first switch24, a NMOS transistor, directly couples the fuse28to the first latch22of the register21. The first switch24is controlled by a fuse-fetching signal from a controller.

Please refer toFIG. 2(b). In a fetching cycle, a fuse-fetching signal is sent from a controller when clock K is at logic high. The fuse-fetching signal turns on the first switch24and loads the content of the fuses28in parallel into the first latches22of the registers21. After the clock K turns to logic low, the fetching cycle ends and a shifting cycle commences. Generally speaking, during the shifting cycle the shift register29forwards the contents of the registers21to its serial output end, where the contents of the fuses are read one by one when clock K is at logic high.

The first latch22of the embodiment can store the fuse information and receive previous stage data and then pass them to serial output of the shift register29. In comparison with all prior arts which install additional fuse-latch elements to store fuse information before the fuse information is transferred to the serial output port, the present invention can eliminate unnecessary hardware cost and effectively reduce the layout area.

The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments can be devised by those skilled in the art without departing from the scope of the following claims.