Pulse generation circuit and semiconductor device

Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, a driving method of the semiconductor device, and the like. The present invention particularly relates to a circuit for a display device.

Note that in this specification, a semiconductor device means a circuit including a semiconductor element (e.g., a transistor or a diode) and a device including the circuit. The semiconductor device also means any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip having an integrated circuit, a display device, a light-emitting device, a lighting device, and an electronic device are all semiconductor devices.

2. Description of the Related Art

A screen of an active matrix display device includes a plurality of pixels arranged in an array. The pixels are each configured with a circuit. The pixel circuits in the same row are connected to a gate line in that row, and the pixel circuits in the same column are connected to a source line in that column. The pixel circuit is provided with a switch which controls an on or off state by a gate signal input to the gate line. Pulse signals are sequentially supplied to the gate lines arranged in a vertical direction from a gate driver, so that pixels are selected row by row. To the pixel circuits of the selected row, a source signal corresponding to an image signal is input from a source line.

Further, as one of means of downsizing, weight saving, and obtaining narrowed frame of an active matrix display device, it has been known to form a gate driver and a pixel portion on one substrate. Pixel circuits of the display device can be formed with either an n-channel transistor or a p-channel transistor. However, it is preferable to design a gate driver with a single conductivity type transistor instead of using a CMOS circuit in order to manufacture a display device having a narrow bezel width with reduced number of manufacturing steps and manufacturing cost.

Main circuits of the gate driver are shift registers. For example, Patent documents 1 and 2 each disclose a shift register including single conductivity type transistors. Patent document 1 discloses a gate driver in which a demultiplexer is connected to an output terminal of a shift register. Patent document 2 discloses a gate driver capable of partial driving by which data displayed on the screen is partly rewritten.

REFERENCE

Patent Document

SUMMARY OF THE INVENTION

In view of the above, one object of one embodiment of the present invention is to provide a novel circuit which has a function of generating pulse signals output to a plurality of wirings from an output signal of a one-stage shift register and includes single conductivity type transistors. Another object of one embodiment of the present invention is to provide a display device having a narrow frame width by designing the layout of gate drivers. Moreover, another object of one embodiment of the present invention is to provide a novel gate driver capable of partial driving of a display device.

Note that the description of a plurality of objects does not mutually preclude the existence. Note that one embodiment of the present invention does not necessarily achieve all the objects listed above. Objects other than those listed above are apparent from the description of the specification, drawings, and claims, and also such objects could be an object of one embodiment of the present invention.

One embodiment of the present invention is a pulse generation circuit, which has a function of sequentially outputting pulse signals to a plurality of wirings and includes a single conductivity type transistor. The pulse generation circuit includes k (k is an integer of 2 or more)-stage first unit circuits connected in cascade and k second unit circuits in each of which an input is connected to one of the first unit circuits and an output is connected to M (M is an integer of 2 or more) wirings. In the first unit circuit, a first signal is generated and output to the first unit circuit in a next stage, a second signal is generated and output to the first unit circuit in a previous stage, output of a third signal to the second unit circuit is started in accordance with the first signal input from the first unit circuit in the previous stage, the output of the third signal to the second unit circuit is stopped in accordance with the second signal input from the first unit circuit in the next stage, and the second unit circuit generates M pulse signals from the third signal and output the M pulse signals to the M wirings.

In the pulse generation circuit of the above embodiment, the first unit circuit may generate a fourth signal and output the fourth signal to the second unit circuit, and the second unit circuit may input a constant voltage to the M wirings in accordance with the fourth signal.

In the pulse generation circuit of the above embodiment, the second unit circuit may generate the M pulse signals having pulsed widths corresponding to pulse widths of M control signals.

By applying the pulse generation circuit of the above embodiment to a gate driver for generating a gate signal, a display device can be provided.

According to one embodiment of the present invention, it is possible to provide a novel circuit which has a function of generating pulse signals output from an output signal of a one-stage shift register to a plurality of wirings and includes single conductivity type transistors. According to one embodiment of the present invention, it is possible to provide a display device having a narrowed frame width by designing the layout of gate drivers.

DETAILED DESCRIPTION OF THE INVENTION

In the drawings used for the description of embodiments of the present invention, the same portions or portions having a similar function are denoted by the same reference numerals, and the repeated description thereof is omitted.

In this embodiment, as an example of a semiconductor device, a liquid crystal display device (hereinafter referred to as LCD) will be described.

<Structural Example of LCD>

The LCD is a semiconductor device including a liquid crystal panel (LC panel), a controller, a power supply circuit, a backlight module, and the like.FIG. 1is a block diagram illustrating a structural example of an active matrix LCD.FIGS. 2A and 2Beach illustrate a structural example of a liquid crystal panel (LC panel) for forming the LCD.

As shown inFIG. 1, an LCD10includes a pixel portion20, a gate driver21, a gate driver22, a source driver23, and a controller24.FIG. 2Aillustrates a structural example of an LC panel in which the pixel portion20and all of the drivers21,22, and23are formed over one substrate, andFIG. 2Billustrates a structural example of an LC panel in which the pixel portion20and the gate drivers21and22are formed over one substrate.

The LC panel is also referred to as a liquid crystal (LC) module. The LC panel, a control circuit thereof, a power supply circuit, a backlight module, and the like are incorporated in a housing, so that a liquid crystal display device is completed.

FIG. 2Ais a structural example of an LC panel in the case where the pixel portion20and the drivers21,22, and23are circuits including the same conductivity type transistors. An LC panel51includes two substrates61and62. The pixel portion20, the drivers21,22, and23, and terminal portions65are formed over the substrate61.

A plurality of terminals for connecting the pixel portion20and the drivers21,22, and23to external circuits are formed on the terminal portion65. The terminal portion65is connected to flexible printed circuits (FPCs)66. Here, a structure in which the FPC66is not connected to the terminal portion65is also included in the LC panel.

The substrate61and the substrate62face each other with a space (cell gap) for providing a liquid crystal layer held therebetween by a spacer. Either the substrate61or the substrate62is provided with the spacer. Alternatively, the spacer is sealed between the substrate61and the substrate62.

A sealing member63is provided in the periphery of a region where the substrate61and the substrate62face each other. With the sealing member63, a liquid crystal layer is sealed between the substrate61and the substrate62. The frame width of the LC panel51, which does not contribute to display, can be narrowed by providing the sealing member63so that the drivers21,22, and23overlap therewith.

In the LC panel51, the pixel portion20and the drivers21,22, and23include the same conductivity type transistors. Note that in the case where the source driver23includes both an n-channel transistor and a p-channel transistor, an IC chip, which incorporates the source driver23, may be mounted on the substrate61instead of forming the source driver23over the substrate61, together with the pixel portion20and the gate drivers21and22.

An LC panel having such a structural example is shown inFIG. 2B. As shown inFIG. 2B, in an LC panel52, an IC chip including the source driver23is mounted on a tape carrier package (TCP)68. Note that an FPC connected to the IC chip is not illustrated in the TCP68. A terminal portion67connected to the TCP68is formed over the substrate61. A plurality of terminals for connecting source lines of the pixel portion20to the TCP68are formed in the terminal portion67. Note that a structure without the TCP68is also regarded as one of structural examples of the liquid crystal panel of this embodiment.

Moreover, in the case where some circuits of the source driver23are formed with transistors of the same conductivity type as the transistors of the pixel portion20and the gate drivers21and22, such circuits may be formed over the substrate61and other circuits may be incorporated in an IC chip.

Note that a mounting method of the IC chip is not particularly limited. A method for directly mounting a bare chip on the substrate61(a chip on glass (COG)) may be employed. Alternatively, instead of TCP, a system on film (SOF), which incorporates an IC chip, may be attached to the substrate61.

[Pixel Portion and Pixel Circuit]

As shown inFIG. 1, the pixel portion20includes a plurality of pixel circuits30arranged in an array, a plurality of gate lines31arranged in a vertical direction, and a plurality of source lines32arranged in a horizontal direction. The pixel circuits30in the same row are connected to the gate line31in that row, and the pixel circuits30in the same column are connected to the source line32in that column.

FIG. 2Cis a circuit diagram illustrating a structural example of the pixel circuit30. The pixel circuit30includes a liquid crystal element33, a transistor34, and a capacitor35.

The liquid crystal element33includes two electrodes and a liquid crystal layer between the two electrodes. One electrode is connected to the transistor34, and voltage VCOM_T is input to the other electrode. The transistor34functions as a switch that connects the liquid crystal element33to the source line32. The capacitor35functions as a storage capacitor that holds voltage between the two electrodes of the liquid crystal element33.

When the transistor34is turned on, the liquid crystal element33and the capacitor35are charged or discharged depending on the potential of the source line32. Depending on the voltage held in the liquid crystal element33and the capacitor35, the orientation state of the liquid crystal layer changes, resulting in a change in transmittance of the liquid crystal element33.

Note that a display device other than an LCD can be obtained by changing the circuit structure of the pixel circuit30. For example, in obtaining electronic paper, the liquid crystal element33ofFIG. 2Cmay be substituted with a display element that performs display by an electronic liquid powder method or the like.

In obtaining an electroluminescence (EL) display device, a pixel circuit40ofFIG. 2Dmay be provided in the pixel portion20. The pixel circuit40includes an EL element41, a transistor42, a transistor43, and a capacitor44.

The EL element41includes two electrodes (an anode and a cathode) and a light-emitting layer between the two electrodes. One electrode is connected to a wiring45to which a constant voltage is input. The light-emitting layer includes at least a light-emitting substance. Examples of the light-emitting substance include an organic EL material, an inorganic EL material, and the like. Light emission from the light-emitting layer includes light emission (fluorescence) which is generated in returning from a singlet excited state to a ground state and light emission (phosphorescence) which is generated in returning from a triplet excited state to a ground state.

The EL element41is capable of changing emission intensity with current flowing between the two electrodes. Here, the emission intensity of the EL element41is adjusted by current flowing through the transistor43. That is, the emission intensity of the EL element41is adjusted by a gate voltage of the transistor43.

The capacitor44connects a gate of the transistor43and a wiring46supplied with a constant voltage. The capacitor44functions as a storage capacitor that holds the gate voltage of the transistor43. The transistor42functions as a switch that connects the gate of the transistor43and the source line32. When the transistor42is turned on, the capacitor44connected to the gate of the transistor43is charged or discharged depending on the current flowing through the transistor42.

The controller24is used to control the LCD10. An image signal, a synchronization signal for controlling rewriting of the screen, and the like are input to the controller24. Examples of the synchronization signal include a horizontal synchronization signal, a vertical synchronization signal, a reference clock signal, and the like.

The source lines32are connected to the source driver23. The source driver23has a function of generating a data signal from an image signal input thereto from the controller24and outputting the data signal to the source line32.

Transistors of the gate drivers21and22are single conductivity type transistors.

The gate drivers21and22each have a function of outputting a gate signal to the gate line31in accordance with a control signal input thereto from the controller24. The gate signal is a signal for selecting the pixel circuits30to which a data signal is to be input. The gate line31is connected to either the gate driver21or the gate driver22.

In the conventional case where gate drivers are provided on the left and right sides of a pixel portion as in the LCD10, gate lines in odd-numbered rows are connected to one of the gate drivers and gate lines in even-numbered rows are connected to the other gate driver. That is, a gate driver to which a gate line is connected alternates in every row.

On the other hand, in the LCD10, the gate lines31are alternately connected to the gate driver21and the gate driver22in every M rows (M is an integer of 2 or more). In the example ofFIG. 1, M is 4.

As shown inFIG. 1, the gate lines31are alternately connected to the gate driver21and the gate driver22in every 4 rows. In other words, in the pixel portion20, the gate lines31are grouped in every M rows, and gate line groups are alternately connected to the gate driver21and the gate driver22.

The structures of the gate drivers21and22are more specifically described below with reference toFIG. 3.

<Structural Example of Gate Driver>

FIG. 3is a block diagram illustrating a structural example of the gate drivers21and22.

Note that in the description below, the circuit and wiring arrangement inFIG. 1is used as references of terms showing positions (right, left, top, and bottom) and the row and column numbers. For example, the gate driver21is to be referred to as the left-side gate driver and the gate driver22is to be referred to as the right-side gate driver. In order to make clear the arrangement of the gate drivers21and22, the gate driver21is to be referred to as a “GDL21” and the gate driver22is to be referred to as a “GDR22”.

In order to distinguish whether signals and wirings are related to the GDL21or the GDR22, “R” and “L” are added to the terms and reference numerals.

Moreover, in the same element (signal or circuit), identification numbers such as “—1” and “[L1]” are added to the terms to show row and column numbers, the order, and the like. For example, identification numbers of GL_9and GL_R5are added to the same gate lines31, and, in the entire pixel portion20, GL_9denotes the gate line31in the ninth row and GL_R5denotes the gate line31in the fifth row connected to the GDR22.

As shown inFIG. 3, the GDL21and the GDR22each have the same structure. The GDL21and the GDR22each include a shift register100and a demultiplexer110. The shift register100includes m-stage (m is an integer of 2 or more) unit circuits (GSR)101connected in cascade. The demultiplexer110includes m unit circuits (DEMUX)111.

The unit circuits101are each a one-stage shift register. The unit circuit101has a function of transferring an input start pulse signal (SP) to the unit circuit101in the next stage in accordance with a control signal (CLK).

The unit circuit101is hereinafter abbreviated to GSR101. Similarly, terms of other circuits, other signals, and the like are sometimes abbreviated as terms in drawings.

The GSR101has a function of generating at least a first pulse signal, a second pulse signal, and a third pulse signal. The first pulse signal is a signal corresponding to a start pulse signal to be transferred, and is also a control signal (set signal) serving as a trigger of a set operation. The first pulse signal is output to the GSR101in the next stage. The second pulse signal is a control signal (reset signal) serving as a trigger of a reset operation and output to the GSR101in the previous stage. The third pulse signal is a pulse signal for generating a gate signal and is output to the DEMUX111.

Note that to the GSR101in the last stage (in the m-th stage), a dummy unit circuit (dmyGSR)102is connected. The dmyGSR102is a circuit for outputting a second pulse signal (reset signal) to the GSR101in the last stage, and a first pulse signal (set signal) is input thereto from the GSR101in the last stage.

The shift register100is connected to an input of the demultiplexer110, and a third pulse signal is input from the shift register100. A plurality of gate lines31(here, 4m gate lines31) are connected to outputs of the demultiplexer110. The demultiplexer110has a function of selecting one or more gate lines which output a signal among 4m gate lines31and outputting a signal input from the shift register100to the selected gate line(s)31. An output signal of the demultiplexer110is a gate signal.

The demultiplexer110includes m unit circuits (DEMUX)111. The unit circuit111has a function of a demultiplexer; therefore, the demultiplexer110can also be referred to as a demultiplexer group.

The DEMUX11has a function of generating a plurality of pulse signals (here, four pulse signals) from one input signal and sequentially outputting the plurality of generated pulse signals to a plurality of wirings. The operation is described by giving a DEMUX [L1] as an example. In accordance with four control signals PWCL1to PWCL4, the DEMUX [L1] generates four pulse signals from the third pulse signal input thereto from a GSR [L1] and sequentially outputs these four pulse signals to gate lines GL_L1to GL_L4.

In the GDL21, to a DEMUX111[Lk], gate lines31in a (8k-7)-th row to a (8k-4)-th row are connected (k is an integer of 1 or more). Moreover, in the GDR22, to a DEMUX111[Rk] (a k-th stage unit circuit111), gate lines31in a (8k-3)-th row to a (8k)-th row are connected.

Note that although, in the example ofFIG. 3, every four gate lines31are connected to the corresponding DEMUX111, in general, every M gate lines31(M is an integer of 2 or more) can be connected to the corresponding DEMUX111. In such a case, to the DEMUX111[Lk] (1≦k≦m, k is an integer), gate lines31in a (2Mk−2M+1)-th row to a (2Mk−M)-th row are connected. To the DEMUX111[Rk], gate lines31in a (2Mk−M+1)-th row to a (2Mk)-th row are connected. In accordance with M control signals, the corresponding DEMUX111selects one or more gate lines31and outputs an input signal from the GSR101to the selected gate line31.

The demultiplexer110includes a dummy unit circuit (dmyDEMUX)112connected to the dummy unit circuit (dmyGSR)102. Two dummy gate lines37are connected to the dmyDEMUX112. The dmyDEMUX112has a function similar to that of the DEMUX111, i.e. a function of sequentially inputting an output signal of the dmyGSR102to the two dummy gate lines37in accordance with the two control signals PWCL1and PWCL2.

Note that the dmyDEMUX112is not necessarily provided. When the dmyDEMUX112is provided, the dummy gate line37is not necessarily provided. When the dummy gate line37is provided, the pixel circuit30connected to the dummy gate line37may be provided in the pixel portion20, or is not necessarily provided. When the pixel circuit30is provided, the pixel circuits30may be provided in all columns or some columns.

The GDL21and the GDR22are each a circuit including m unit circuits (PGC)121and one dummy unit circuit (dmyPGC)122.

The PGC121is a circuit including the GSR101and the DEMUX111, the dmyPGC is a circuit including the dmyGSR102and the dmyDEMUX112. These circuits each have a function of generating a plurality of pulse signals. The PGC121is a circuit for outputting a gate signal to the plurality of gate lines31, and the dmyPGC122is a circuit for outputting a gate signal to one or more dummy gate lines37.

As shown inFIG. 3, since gate signals can be output to the plurality of gate lines31from one-stage GSR101(one-stage PGC121), an area occupied by a circuit and a wiring group per row can be reduced in each of the gate drivers21and22. This is described with reference toFIGS. 4A and 4B.

FIGS. 4A and 4Bare schematic diagrams for illustrating a difference between this embodiment and a conventional example in the layout of the gate drivers.FIG. 4A10illustrates a layout example of the gate drivers in this embodiment, andFIG. 4Billustrates a layout example of the gate drivers in the conventional example. Note that the terms and reference numerals used inFIG. 3,FIG. 10B, and the like are used also inFIG. 4Bfor easy understanding.

In the conventional example, one-stage GSR is provided for one gate line. On the other hand, in this embodiment, one-stage GSR can be provided for four gate lines. Thus, a gate driver width Wgd of this embodiment is narrower than a gate driver width Wpa of the conventional example. That is, employment of the gate drivers21and22of this embodiment enables a frame width of the LCD10to be narrower.

<Gate Driver: Example of Driving Method of GDR and GDL>

Examples of the driving methods of the GDL21and the GDR22are described with reference toFIG. 5,FIG. 6, andFIG. 7. Moreover, partial driving by which data displayed on the pixel portion20(screen) of the LCD10is partly rewritten is also described.

FIG. 5is a block diagram illustrating an example of a more specific structure of the GDL21, andFIG. 6is a block diagram illustrating an example of a more specific structure of the GDR22.FIG. 7is a timing chart of the GDL21and the GDR22.

<Structural Examples of GDL and GDR>

Since the GDL21and the GDR22have similar structures as shown inFIG. 5andFIG. 6, only the structure of the GDL21is described here. Clock signals CLKL1and CLKL2are input to the GSR101in odd-numbered stages, and clock signals CLKL3and CLKL4are input to the GSR101in even-numbered stages. To the dmyGSR102, the clock signals CLKL1and CLKL2are input. Note that in the case where the clock signals CLKL1and CLKL2are input to the GSR101in the last stage, the clock signals CLKL3and CLKL4are input to the dmyGSR102.

Note that in the description below, the “clock signal CLKL1” is abbreviated to a “signal CLKL1” or “CLKL1” in some cases. Voltage, a circuit, and a terminal as well as a signal are abbreviated in some cases.

The start pulse signal SPL is input to the GSR [L1]. The GSR101in each stage outputs the start pulse signal SPL which is shifted in accordance with the signal CLKL2or CLKL4to the GSR101in the next stage. Moreover, the GSR101and the dmyGSR102each output a reset signal to the GSR101in the previous stage in accordance with the signal CLKL1or CLKL3.

To the DEMUX111, the clock signals PWCL1to PWCL4and two signals generated in the GSR101are input. In accordance with the signals PWCL1to PWCL4, the DEMUX111generates four pulse signals from a signal input from the GSR101and sequentially outputs the pulse signals to four output terminals. InFIG. 5, gate lines to which four output signals GOUT of the DEMUX111are output are distinguished by row numbers.

In accordance with the other output signal of the GSR101, the DEMUX111outputs constant voltages to the four output terminals. That is, constant voltages are supplied to the four output terminals in a period during which a pulse signal (gate signal) is not generated in the DEMUX111, whereby the voltage of the gate line31can be set to an L level during such a period. In such a manner, the voltage of the gate line31can be surely held at a voltage at which the pixel circuit30is not selected; therefore, high quality display can be obtained in the LCD10.

To the dmyDEMUX112, the signals PWCL1and PWCL2and two output signals from the dmyGSR102are input to output two dummy gate signals dmyGOUT, which is different from the DEMUX111.

<Example of Driving Method of GDL and GDR>

Examples of the driving methods of the GDL and the GDR are described with reference to a timing chart inFIG. 7.FIG. 7shows waveforms of the control signals input to the GDL21inFIG. 5and the GDR22inFIG. 6and the output signals of the GDL21and GDR22. Note that inFIG. 7, output signals GOUT1[L1] to GOUT4[L4] from the GSR101[L1] are shown as the output signals of the GDL21, and output signals GOUT5[R1] to GOUT8[R4] from the GSR101[R1] are shown as the output signals of the GDR22.

Note thatFIG. 7is a timing chart in the case where the transistor34of the pixel circuit30is an n-channel transistor in which case the gate line31is selected by an input of a gate signal (GOUT) at a high level (H level) to the gate line31.

To the GDL21, the start pulse signal SPL, the clock signals CLKL1to CLKL4, and the clock signals PWCL1to PWCL4are input. To the GDR22, the start pulse signal SPR, the clock signals CLKR1to CLKR4, and the clock signals PWCR1to PWCR4are input.

[Input Signal of Shift Register]

The CLKL1to CLKL4are clock signals having the same cycles as the CLKR1to CLKR4.

The CLKL1, CLKL3, CLKR1, and CLKR3are each a signal having the same waveform with a pulse width of a 1/2 cycle. The CLKL3is an inversion signal of the CLKL1, and the CLKR3is an inversion signal of the CLKR1. The CLKR1is a signal whose phase is delayed from the CLKL1by a 1/4 cycle. This phase delay is the same as the phase delay of the signal SPR from the signal SPL.

The CLKL2, CLKL4, CLKR2, and CLKR4are each a signal having the same waveform with a pulse width the same as those of the start pulse signals SPL and SPR (in a period during which the signals are at an H level), which is a 3/8 cycle.

The CLKL2is a signal that is at an H level in a period during which the CLKL1is at an H level, and the CLKL1and CLKL2fall at the same timing. The CLKL4is a signal that is at an H level in a period during which the CLKL3is at an H level, and the CLKL3and CLKL4fall at the same timing. The same applies to the CLKR2and CLKR4.

[Input Signal Of Demultiplexer]

The signals PWCL1to PWCL4and the signals PWCR1to PWCR4are each a clock signal for determining the timing at which an H-level signal is output from the DEMUX111to the gate line31. Therefore, partial driving is possible by changing some pulse widths of the signals PWCL1to PWCL4and the signals PWCR1to PWCR4.

In normal driving, the signals PWCL1to PWCL4and the signals PWCR1to PWCR4are clock signals each having the same cycle and the same pulse width, and the cycles are 1/2 cycles of the signals CLKL1to CLKL4and the signals CLKR1to CLKR4. As shown inFIG. 7, in the order of the signals PWCL1to PWCL4and in the order of the signals PWCR1to PWCR4, a pulse of one signal overlaps with a pulse of a subsequent signal. Here, the length of a period where pulses overlap with each other is a 1/2 pulse width. Thus, in the case where the PWCL1serves as a reference, the phase delays of other signals are as follows: the PWCL2is a 1/2 pulse width thereof, the PWCL3is a 2/2 pulse width thereof, and the PWCL4is a 3/2 pulse width thereof. Further, the phase delays of the PWCR1is a 4/2 pulse width of the PWCL1, the PWCR2is a 5/2 pulse width thereof, the PWCR3is a 6/2 pulse width thereof, and the PWCR4is a 7/2 pulse width thereof.

In a period ToutL1, the DEMUX [L] distributes the input signal from the GSR [L1] to four output terminals and outputs the GOUT1to the GOUT4. The period ToutL1starts at rising of the CLKL1and terminates at rising of the CLKL2. In a period during which the PWCL1is at an H level, the DEMUX [L1] outputs the GOUT1at an H level. In a similar manner, the DEMUX [L1] outputs the GOUT2, GOUT3, and GOUT4by inputs of the PWCL2, PWCL3, and PWCL4at an H level, respectively.

In a period ToutR1, the DEMUX [R1] operates in a manner similar to that of the DEMUX [L] and outputs the GOUT5to the GOUT8.

By such an operation of the demultiplexer110, the gate signals GOUT1, GOUT2, GOUT3, GOUT4, GOUT5, GOUT6, GOUT7, and GOUT8are output to the gate lines GL_1, GL_2, GL_3, GL_4, GL_5, GL_6, GL_7, and GL_8, respectively, with a phase delay being a 1/2 pulse width of each gate signal.

In order to perform partial driving, the GDL21and GDR22may be driven so that gate signals GOUT at en H level are output only to some gate lines31. In this embodiment, partial driving is achieved by controlling the pulse widths of the signals PWCL1to PWCL4and the signals PWCR1to PWCR4.

Specifically, in a certain period during one frame period, in which the pulse widths of some or all of the signals PWCR1to PWCR4and the signals PWCL1to PWCL4are set to zero, the signals are set at an L level. Such signals in one or more rows of the gate lines31which are selected in this period are not at an H level; therefore, data displayed on the pixel circuits30in such row(s) cannot be rewritten. For example, the pixel circuits30in the fifth to eighth rows are not selected when the PWCR1to PWCR4are at an L level in the period ToutR1; therefore, data displayed on the pixel circuits30in such rows are not rewritten and an image in a pervious frame period is to be displayed.

As described above, employment of the gate drivers of this embodiment enables a display device having a narrowed frame and partial driving of the display device.

Single conductivity type transistors can be included in the gate drivers of this embodiment. A specific circuit structure of such a gate driver will be described below in Embodiment 2.

In this embodiment, the circuit structures of the unit circuits GSR, dmyGSR, DEMUX, and dmyDEMUX included in the GDL21and GDR22will be described. Here, an example in which an n-channel transistor is included in each of the unit circuits GSR, dmyGSR, DEMUX, and dmyDEMUX is shown.

Note that in this embodiment, in some cases, input signals and output signals in the GDL21and GDR22are not distinguished for simple description. In such a case, signals CLKL1to CLKL4and signals CLKR1to CLKR4are abbreviated to CLK1to CLK4. Moreover, in some cases, the same term is used for both a terminal and a signal for easy understanding of the structures and operations of circuits.

FIG. 8Ais a circuit diagram illustrating a structural example of the GSR101, andFIG. 8Bis a block diagram of the GSR101.

The GSR101includes four input terminals CK1, CK2, SETIN, and RESIN and four output terminals SROUT(S), SROUT (R), FNOUT1, and FNOUT2.

The terminal CK1is an input terminal of the clock signal CLK1or CLK3, and the terminal CK2is an input terminal of the clock signal CLK2or CLK4.

The terminal SETIN is an input terminal to which a set signal SRSET of the GSR101is input, and the SROUT(S) is an output terminal from which the set signal is output. The voltage change in a node FNS is output from the terminal SROUT(S) as the signal SRSET. The terminal SETIN is connected to the terminal SROUT(S) in the previous stage. Note that a start pulse signal SP is input to the SETIN in a first stage. The terminal SROUT(S) in the last stage is connected to the terminal SETIN of the dmyGSR102.

The terminal RESIN is an input terminal to which a reset signal SRRES of the GSR101is input, and the SROUT(R) is an output terminal from which the reset signal is output. The terminal RESIN is connected to the terminal SROUT(R) in the next stage. The terminal RESIN in the last stage is connected to the terminal SROUT(R) of the dmyGSR102.

The terminals FNOUT1and FNOUT2are connected to the DEMUX111.

The GSR101includes eight transistors M1to M8. Here, a source and a drain of the transistor are distinguished for easy understanding of the structures and operations of circuits. However, in some cases, the functions of the source and drain of the transistor are interchanged depending on voltage supplied to the transistor. Thus, in the semiconductor device of one embodiment of the present invention, the distinction between the source and drain of the transistor is not limited to that described in this embodiment. Here, the circuit of the GSR101includes n-channel transistors; therefore, a terminal (electrode) to which a signal at an H level and a power source voltage are mainly input is referred to as a drain, and a terminal (electrode) to which a signal at an L level and a power source voltage are mainly input is referred to as a source.

As the power source voltage, a high power source voltage VDD and a low power source voltage VSS are supplied to the GSR101. Wirings201and202for supplying the power source voltages VDD and VSS are included. Drains of the transistors M1and M3are connected to the wiring201. Sources of the transistors M2, M4, M6, and M8are connected to the wiring202. Drains of the transistors M5and M7are connected to the terminals CK1and CK2.

Here, a drain of the transistor M2is regarded as a node FN1, and a gate of the transistor M2is regarded as a node FN2. The FN1and FN2are connected to the DEMUX111, and the voltage changes in the FN1and FN2are output to the DEMUX111as signals. As will be described later, the FN1is a node whose voltage gets higher than that of a VDD by a bootstrap effect.

The transistor M1functions as a circuit that changes the node FN1to an H level, and the transistor M2functions as a circuit that changes the node FN1to an L level. The transistor M1connects the wiring201and the FN1, and the set signal SRSET is input from the terminal SETIN to a gate of the transistor M1. The transistor M2connects the FN1and the wiring202, and the gate of the transistor M2is connected to the FN2.

The transistor M3functions as a circuit that changes the node FN2to an H level, and the transistor M4functions as a circuit that changes the node FN2to an L level. The transistor M3connects the wiring201and the FN2, and the reset signal SRRES is input from the terminal RESIN to a gate of the transistor M3. The transistor M4connects the FN2and the wiring202, and the set signal SRSET is input from the terminal SETIN to the gate of the transistor M4.

The transistor M5functions as a circuit that changes a node FNR to an H level, and the transistor M6functions as a circuit that changes the node FNR to an L level. Here, a source of the transistor M5is regarded as the node FNR. The transistor M5connects the FNR and the terminal CK1to which the clock signal CLK1or CLK3is input, and a gate of the transistor M5is connected to the FN1. The transistor M6connects the FNR and the wiring202, and a gate of the transistor M6is connected to the FN2.

The transistor M7functions as a circuit that changes the node FNS to an H level, and the transistor M8functions as a circuit that changes the node FNS to an L level. Here, a source of the transistor M7is regarded as the node FNS. The transistor M7connects the FNS and the terminal CK2to which the clock signal CLK2or CLK4is input, and a gate of the transistor M7is connected to the FN1. The transistor M8connects the FNS and the wiring202, and a gate of the transistor M8is connected to the FN2.

FIG. 9Ais a circuit diagram illustrating a structural example of the dmyGSR102, andFIG. 9Bis a block diagram of the dmyGSR102.

The dmyGSR102is a circuit in which some elements of the GSR101are removed because some functions of the GSR101are not necessary. The dmyGSR102does not output a set signal; therefore, the terminals SROUT(S) and RESIN and the transistors M7and M8are not included. The dmyGSR102differs from the GSR101in that the gate of the transistor M3is connected to the terminal CK2. Although the clock signal CLK2is input to the terminal CK2of the dmyGSR102in the structural examples of the GDL21inFIG. 5and the GDR22inFIG. 6, a reset signal can be input to the terminal CK2from outside.

<Structural Examples 1 of DEMUX and dmyDEMUX>

FIGS. 10A and 10Bare block diagrams of the DEMUX111, andFIGS. 10C and 10Dare block diagrams of the dmyDEMUX112.

The input terminals FNOUT1and FNOUT2of the DEMUX111are connected to the GSR101, and signals PWC1to PWC4are input to input terminals PWC1to PWC4. The gate lines31are connected to the output terminals GOUT1to GOUT4. Moreover, the DEMUX111includes four unit circuits (BUF)131(FIG. 10B). Note that in the DEMUX111, the four unit circuits BUF131are referred to as BUF1to BUF4for distinction.

The dmyDEMUX112includes two unit circuits BUF (BUF1and BUF2)131to output pulse signals to two dummy gate lines (dmyGL) (FIG. 10D).

As shown inFIG. 10B, the output terminals FNOUT1and FNOUT2of the GSR101are connected to the BUF1to BUF4of the DEMUX111. The signals PWC1, PWC2, PWC3, and PWC4are input to terminals PWC of the BUF1, BUF2, BUF3, and BUF4, respectively. A unit circuit from which a signal input from the FNOUT1(the voltage of the FN1) is output is selected from the BUF1to BUF4. Moreover, the voltage of the output terminals GOUT1to GOUT4is set at an L level in accordance with a signal input from the FNOUT2.

FIG. 11Ais a block diagram of the BUF131, andFIG. 11Bis a circuit diagram illustrating a structural example of the BUF131. Note thatFIG. 11Cis a circuit diagram illustrating another structural example of the BUF131, which will be described later.

The BUF131is a circuit which outputs the voltage change in a node FNG from a terminal GOUT as a signal. The BUF131functions as a buffer circuit, and has a function of outputting the signal input from the terminal FNOUT1from the terminal GOUT in accordance with a signal input to a terminal PWC. Moreover, the BUF131has a function of changing the terminal GOUT to an L level in accordance with a signal input to the terminal FNOUT2.

The BUF131includes two transistors M111and M12connected in series. The transistor M11has a function of changing the node FNG to an H level, and the transistor M12has a function of discharging the node FNG to be changed to an L level. The transistor M11connects the terminal PWC and the FNG, and a gate of the transistor M11is connected to the terminal FNOUT1(a node FN1). The transistor M12connects the FNG and a wiring204, and a gate of the transistor M12is connected to the terminal FNOUT2(a node FN2).

The BUF131is supplied with VSS from the wiring204. Note that the wiring204may be used in common with the wiring202of the GSR101.

Note that there is also a case where in each of the GDL21and GDL22, instead of one transistor, a plurality of transistors connected in series and/or in parallel for the purpose of adjusting channel widths or channel lengths thereof are used as the transistors M1to M8, M11, and M12. The same applies to another structural example which will be described later.

<Operation Examples of GSR and DEMUX>

Operation examples of the GSR101and DEMUX111are described below with reference toFIG. 12.FIG. 12is a timing chart of the GDL21. Here, the operations of the GSR101and DEMUX111are described by giving the GDL21as an example, and the GDR22operates in the same manner.

FIG. 12shows waveforms of the input signals CLKL1to CLKL4and SPL of the shift register100and the input signals PWCL1to PWCL4of the demultiplexer110. The voltages of these input signals at an H level are VDD, and those at an L level are VSS. Note that VDD are voltages that can turn on the transistors M1to M8, M11, and M12by being input to gates of the transistors M1to M8, M11, and M12. Moreover, VSS can turn off these transistors.

Further,FIG. 12shows output signals SRSET, SRRES, ΦFN1, and ΦFN2of the GSR [L1] to the GSR [L3] and output signals GOUT of the DEMUX [L1] and the DEMUX [L2]. The signals SRSET and SRRES correspond to the voltage changes in the nodes FNS and FNR of the GSR101, respectively. Note that the ΦFN1and ΦFN2correspond to the voltage changes in the nodes FN1and FN2, respectively. Further,FIG. 12shows the output signals SRSET, SRRES, ΦFN1, and ΦFN2of the GSR [L1] to the GSR [L3] and output signals GOUT of the DEMUX [L1] and the DEMUX [L2] in a period t0-t9.

First, the operations of the GSR [L1] to the GSR [L3] (the shift register100) are described.

The nodes FN1, FN2, FNR, and FNS of the GSR [L1] to the GSR [L3] are each in an initial state by a reset operation in one frame period before. An initial state is a state in which only the node FN2is at an H level and other nodes are each at an L level.

The signal SPL is input to the terminal SETIN of the GSR [L1]. The transistor M4is turned on, and a node FN2_L1is changed to an L level. At the time t2, the terminal SETIN is changed to an L level and the transistor M4is turned off; therefore, the FN2_L1is in an electrically floating state.

Moreover, by the input of the signal SPL, the transistor M1is turned on and the FN1is changed to an H level in the GSR [L1]. The voltage of the FN1is lower than that of VDD by a threshold voltage of the transistor M1. After the time t2, the transistor M1is turned off.

In a period t2-t3, a bootstrap operation in which the voltage of the gate of the transistor M5(FN1) in the GSR [L1] is made higher than that of VDD is performed. The drain of the transistor M5is at an H level by the signal CLKL1. The FN1is at an H level; therefore, the transistor M5is on and VDD is applied to the drain thereof. The voltages of the source and drain of the transistor M5are VDD. The voltage of the gate of the transistor M5(ΦFN1_L1) gets higher than that of VDD because of a bootstrap effect by a capacitance between the gate and the source and a capacitance between the gate and the drain.

A set signal SRSET_L1is generated in the GSR [L1]. The transistor M7is turned on by inputting the CLKL2at an H level to the terminal CK2so that the node FNS is changed to an H level. The voltage of the FNS is input to a terminal SETIN of the GSR [L2] in a next stage as the signal SRSET_L1at an H level. That is, in the shift register100, a shift operation of transferring a start pulse signal SPL to the GSR [L2] in a next stage is performed. Moreover, in the GSR [L2], the above set operation is started by the input of the SRSET_L1.

In a period during which the CLKL1is at an H level, the GSR [L1] generates a reset signal SRRES_L1. The terminal CK1is supplied with VDD with the transistor M6being on; therefore, the node FNR is at an H level.

In this period, a reset signal SRRES_L2is generated in the GSR [L2] and is output to the GSR [L1]. The reset operation of the GSR [L1] is performed with input of the SRRES_L2at an H level serving as a trigger. When the transistor M3is turned on, the FN2is changed to an H level. Thus, the transistor M2is turned on. When the transistor M2is turned on, the FN1is changed to an L level. In a period t6, the SRRES_L2is changed to an L level, whereby the nodes FN1, FN2, FNR, and FNS are each in an electrically floating state. Such a voltage level is maintained until a signal SPL is input to the terminal SETIN. The node FN2is changed to an H level and the nodes FN1, FNR, and FNS are changed to an L level by the reset operation.

As shown inFIG. 12, in the GSR [L1], when the FN2is at an L level, the FN1is at an H level, and when the FN2is at an H level, the FN1is at an L level. The GSR [L1] outputs two pulse signals, the voltage levels of which have an inverted relationship, to the DEMUX [L1].

The above operations are sequentially performed in the GSR [L2] and the GSR [L3].

Next, the operations of the DEMUX [L1] and the DEMUX [L2] (the demultiplexer110) are described.

In the DEMUX111(BUF1to BUF4), when one of the terminals FNOUT1and FNOUT2is at an H level, the other terminal is at an L level by the operation of the GSR101. Thus, as seen from the circuit diagram of the BUF131inFIG. 11B, when one of the transistors M11and M12of the BUF131is turned on, the other transistor is turned off. Accordingly, the level of the node FNG of the BUF131is controlled by the voltage of the terminal PWC in a period during which the transistor M11is on, whereas the level of the node FNG is changed to an L level because VSS is supplied to the node FNG from the wiring202in a period during which the transistor M12is on.

Specifically, as shown inFIG. 12, signals GOUT [L1] to GOUT [L4] are output from a DEMUX111[L1] (BUF1[L1] to BUF4[L1]) in the period t2-t3, and signals GOUT [L5] to GOUT [L8] are output from a DEMUX [L2] (BUF1[L2] to BUF4[L2]) in the period t4-t6.

As shown inFIG. 12, a period during which the DEMUX [L1] and the DEMUX [L2] output the signals GOUT at an H level is also a period during which bootstrap operations of the GSR [L1] and the GSR [L2] are performed. In such a bootstrap period, the voltage of the signal GOUT (the voltage of the FNG) can be prevented from being lower than that of VDD because the signal GOUT at an H level is made output. Therefore, the pixel circuits30in the selected row can be surely connected to the source line; thus, high quality display can be obtained in the LCD10.

Other structural examples of the GSR101and BUF131are described below.

FIG. 13is a circuit diagram illustrating a structural example of the GSR101. A unit circuit (GSR)103is a circuit corresponding to the GSR101to which a transistor M21is added. The transistor M21connects the node FN1and the gate of the transistor M5, and the wiring201supplied with VDD is connected to a gate of the transistor M21. That is, the transistor M21is a switch that is always on. With the transistor M21, deterioration of the transistor M2can be suppressed.

Alternatively, as in a unit circuit (GSR)104ofFIG. 14, a transistor M22for connecting the node FN1and the gate of the transistor M7may be further provided for the purpose of preventing deterioration of the transistor M2. A gate of the transistor M22is connected to the wiring201supplied with VDD. Further alternatively, a structure without the transistor M21may be employed for the GSR104. The block diagrams of the GSR103and the GSR104are the same as that of the GSR101inFIG. 8B.

As shown inFIG. 12, the voltage of the node FN2of the GSR101is at an H level in most of the periods. Therefore, the GSR101may be provided with a circuit for regularly charging the node FN2to suppress voltage drop of the node FN2.FIG. 15Ais a circuit diagram of a unit circuit (GSR) having such a circuit, andFIG. 15Bis a block diagram of the GSR.

As shown inFIG. 15A, a unit circuit (GSR)105is a circuit corresponding to the GSR104to which an input terminal CK3, a transistor M31, and a capacitor Cp31are added. The transistor M31connects the wiring201and the node FN2, and the terminal CK3is connected to a gate of the transistor M31. An inverted clock signal of a clock signal input to the terminal CK1is input to the terminal CK3. That is, in the case where the clock signals CLKL1and CLKR1are input to the terminal CK1, the clock signals CLKL3and CLKR3are input to the terminal CK3, and in the case where the clock signals CLKL3and CLKR3are input to the terminal CK1, the clock signals CLKL1and CLKR1are input to the terminal CK3.

The capacitor Cp31connects the node FN2and the wiring202and functions as a storage capacitor of the node FN2. A structure without the capacitor Cp31may be employed for the GSR105.

The operation of the transistor M31of the GSR105is described with reference to the timing chart ofFIG. 12. The on or off state of the transistor M31is controlled by the signal CLKL3in the GSR [L1]. In the GSR [L1], the transistor M31is turned on every time the signal CLKL3is changed to an H level, which enables voltage rise of the FN2to VDD. Since the FN2is regularly supplied with VDD in the GSR105in this manner, the gate line31can be surely changed to an L level in a non-selected period and accordingly high quality display can be obtained in the LCD10.

A unit circuit (GSR)106shown inFIG. 16Ais a circuit corresponding to the GSR105to which an input terminal INIRES and a transistor M41are added.FIG. 16Bis a block diagram of the GSR106. The transistor M41serves as a switch which connects the wiring201and the node FN2, and the input terminal INIRES is connected to a gate of the transistor M41.

FIG. 17andFIG. 18are block diagrams of the gate drivers GDL21and GDR22each including the GSR106and its dummy unit circuit (dmyGSR)107.

Common reset signal is input from the terminal INIRES to the GSR106and the dmyGSR107provided in each of the GDL21and the GDR22. By input of reset signal at an H level, the nodes FN2in all of the unit circuits (GSR)106and the dmyGSR107are changed to an H level. Accordingly, signals in all of the gate lines31are changed to an L level at the same timing and are initialized. Therefore, the signals in all of the gate lines31in the pixel portion20can be changed to an L level by input of the reset signal from the terminal INIRES even in the middle of a frame period, whereby the operation mode of the LCD10can be changed flexibly.

Dummy unit circuits (dmyGSR) corresponding to the GSR103to the GSR106may be formed in a manner similar to that of the dmyGSR102inFIG. 9A. The dmyGSR corresponding to each of the GSR103and the GSR104is a circuit in which the gate of the transistor M3is connected to the terminal CK2with the terminals SROUT(S) and RESIN and the transistors M7and M8removed from the respective unit circuits103and104. The dmyGSR corresponding to the GSR105and the GSR106are circuits in each of which the terminals CK2, SROUT(S), and RESIN and the transistors M3, M7, and M8are removed from the respective unit circuits105and106.

FIG. 11Cillustrates another structural example of the BUF131. A unit circuit (BUF)132inFIG. 11Cis a circuit corresponding to the BUF131(FIG. 11B) to which a transistor M51and a capacitor Cp51are added.

Similar to the transistor M21inFIG. 13, the transistor M51is provided to suppress deterioration of the transistor M11. The transistor M51connects the node FN1(terminal FNOUT1) and the gate of the transistor M11, and VDD is supplied to a gate of the transistor M51from a wiring203. That is, the transistor M51functions as a switch that is always on. Note that the wiring203can also be a wiring used in common with the wiring201of the GSR101and the like.

The capacitor Cp51connects the gate of the transistor M11and the node FNG and functions as a storage capacitor that holds the potential of the gate of the transistor M11. Note that the capacitor Cp51is not necessarily provided.

In this embodiment, the structure of an LC panel (a pixel circuit and drivers) and a manufacturing method thereof will be described. Moreover, in this embodiment, a transistor whose channel is formed using an oxide semiconductor (hereinafter referred to as an OS transistor) is used as a transistor. The OS transistor described in this embodiment is an n-channel transistor.

This embodiment illustrates an example in which the source driver23is incorporated in an IC chip as in the LC panel52ofFIG. 2B, instead of being formed together with the pixel circuits30.

FIG. 19is a top view illustrating a structural example of the pixel circuit30. In this embodiment, the pixel circuit30can be applied to the LCD10of a TN mode or a VA mode.

<Structural Example 1 of Driver and Pixel Circuit>

FIG. 20is a cross-sectional view for describing the cross-sectional structure of the LC panel.FIG. 20illustrates a cross-sectional structure of the gate drivers21and22and the pixel circuit30. Here, a transistor301and a connection portion302for connecting a wiring in a first layer and a wiring in a second layer are illustrated as a typical example of the gate drivers21and22. Further,FIG. 20illustrates a cross section taken along line C-D ofFIG. 19as the pixel circuit30. Note thatFIG. 19illustrates elements of the pixel circuit30formed over a substrate401(element substrate).

A transistor303, a capacitor304, and a liquid crystal element305inFIG. 20correspond to the transistor34, the capacitor35, and the liquid crystal element33of the pixel circuit30inFIG. 2C, respectively.

As illustrated inFIG. 19, a gate line413, a source line424, an electrode425, a wiring426, a pixel electrode432, and an electrode444are formed in the pixel circuit30. The wiring426corresponds to a wiring36inFIG. 2C. The pixel electrode432forms one electrode of each of the capacitor304and the liquid crystal element305. The electrode444serves as the other electrode of the capacitor304and is in contact with the wiring426. A region where the electrode444and the pixel electrode432overlap with each other with an insulating film454provided therebetween functions as the capacitor304. Here, the electrode444and the pixel electrode432are each formed with a light-transmitting conductive film. Therefore, since the capacitor304itself has a light-transmitting property, the capacitor304having large capacitance value can be formed without a decrease of an aperture ratio of a pixel.

An oxide semiconductor film442forms a semiconductor film of the transistor303where a channel is formed. A gate electrode of the transistor303is formed using the gate line413. A source electrode and a drain electrode thereof are formed using the source line424and the electrode425, respectively. Note that in the transistor303, depending on the voltage of the source line424, in some cases, the source line functions as the drain electrode and the electrode425functions as the source electrode. As illustrated inFIG. 20, a gate insulating film of the transistor303is formed using an insulating film451and an insulating film452.

InFIG. 19, a rectangular region over the source line424illustrates a spacer470with which a substrate402is provided. More precisely, the rectangular region illustrates a region where the source line424and the spacer470overlap with each other. The spacer470is not necessarily provided in all pixel circuits30. For example, one spacer470may be provided in pixel circuits30in two rows and two columns.

As illustrated inFIG. 20, a region where a counter electrode433and the pixel electrode432overlap with each other with a liquid crystal layer460provided therebetween functions as the liquid crystal element305. The counter electrode433is in some cases referred to as a common electrode. The liquid crystal element305further includes alignment films461and462for controlling alignment of the liquid crystal layer460.

The liquid crystal layer460is sealed between the substrate401and the substrate402by a sealing member (not illustrated, seeFIG. 2B). The substrate402is provided with a light-blocking film471, a colored film472, and an insulating film473in addition to the counter electrode433, the alignment film462, and the spacer470. Note that the spacer470may be formed over the substrate401. Moreover, the light-blocking film471and/or the colored film472may be formed over the substrate401.

The transistor301of each of the gate drivers21and22has a stacked-layer structure similar to that of the transistor303of the pixel circuit30. The transistor301includes an oxide semiconductor film441where a channel is formed, a gate line411, a source line421, a drain line422, and a gate insulating film including the insulating films451and452.

The connection portion302of each of the gate drivers21and22is a connection portion of a wiring412in a first layer and a wiring423in a second layer. The wiring412and the wiring423are connected to each other through an electrode431in a third layer.

The components of the LC panel inFIG. 19andFIG. 20are described below.

There is no particular limitation on the material and the like of the substrate401as long as the material and the like have heat resistance enough to withstand manufacturing processes of the pixel circuits30and the drivers. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. Alternatively, in the case where the pixel electrode432is a reflective pixel electrode, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, an SOI substrate, or the like may be used. For example, in the case where a glass substrate is used as the substrate401, a large-sized glass substrate having any of the following sizes can be used: the 6th generation (1500 mm×1850 mm), the 7th generation (1870 mm×2200 mm), the 8th generation (2200 mm×2400 mm), the 9th generation (2400 mm×2800 mm), and the 10th generation (2950 mm×3400 mm). Thus, a large-sized LCD can be manufactured.

Alternatively, a flexible substrate such as a resin film can be used as the substrate401. In that case, circuits may be formed directly on the flexible substrate. Alternatively, the following steps may be employed: a substrate is used in the manufacturing process of the circuits, and the circuits are separated from the substrate after completion of the manufacturing process and attached to a flexible substrate with an adhesive layer. In that case, a separation layer and an insulating film may be formed over a substrate for manufacture of the circuits, and the pixel circuits and the drivers may be formed on the insulating film.

For the substrate402, a substrate similar to the substrate401can be used.

<Wiring and Electrodes in First Layer>

The wiring412, and the gate lines411and413in the first layer are formed using one or two or more conductive films. As the conductive film, a metal film of aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or the like; a film in which another metal element is added to such a metal film; a film including an alloy or a compound containing one kind or plural kinds of the above metal elements; or the like can be used. Alternatively, as the conductive film, a light-transmitting oxide conductive film of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

As an example of a conductive film having a single-layer structure, there is a single-layer film of an aluminum film containing silicon. In the case of a two-layer structure, for example, the following combinations can be given: an aluminum film and a titanium film; a titanium nitride film and a titanium film; a titanium nitride film and a tungsten film; a tantalum nitride film and a tungsten film; and a tungsten nitride film and a tungsten film. In the case of a three-layer structure, for example, a combination of a titanium film, an aluminum film, and a titanium film can be given. Alternatively, a film, an alloy film, or a nitride film which contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

In the transistors301and303, an oxynitride semiconductor film having a nitrogen concentration higher than those of the oxide semiconductor film441and the oxide semiconductor film442may be formed between the gate lines411and413and the insulating film451. As examples of such a film, there are an In—Ga—Zn-based oxynitride semiconductor film, an In—Sn-based oxynitride semiconductor film, an In—Ga-based oxynitride semiconductor film, an In—Zn-based oxynitride semiconductor film, a Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, and a film of metal nitride (such as InN or ZnN). These oxynitride semiconductors each have a work function higher than or equal to 5 eV or higher than or equal to 5.5 eV, which is higher than the electron affinity of an oxide semiconductor. With such an oxynitride semiconductor film, the threshold voltages of the transistors301and303can be shifted to the positive direction. For example, in the case where an In—Ga—Zn-based oxynitride semiconductor film is formed, the nitrogen concentration may be set to 7 atomic % or higher.

<Wirings and Electrodes in Second Layer>

The wirings423and426, the source line421, the drain line422, the source line424, and the electrode425in the second layer are formed using one or two or more conductive films. As examples of the conductive film, a metal film of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, tungsten, or the like; an alloy film or a compound film containing one or more kinds of the above metal elements; and a light-transmitting oxide conductive film containing indium oxide, tin oxide, or zinc oxide can be given. In the case of a single-layer structure, for example, an aluminum film containing silicon can be used. In the case of a two-layer structure, for example, the following combinations can be given: an aluminum film and a titanium film; a tungsten film and a titanium film; and a copper-magnesium-aluminum alloy film and a copper film. In the case of a three-layer structure, for example, a combination of a titanium film, an aluminum film, and a titanium film can be given. In that case, a titanium nitride film may be formed in the first layer and/or the third layer. Alternatively, a copper film may be formed in the second layer. In the case of a three-layer structure, alternatively, a combination of a molybdenum film, an aluminum film, and a molybdenum film can be given. In that case, a molybdenum nitride film may be formed in the first layer and/or the third layer, or a copper film may be formed in the second layer.

<Electrodes in Third Layer and Counter Electrode>

The electrode431and the pixel electrode432in the third layer and the counter electrode433are formed using one or two or more light-transmitting conductive films. As an example of the light-transmitting conductive film, a conductive film including indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (ITO), indium tin oxide containing titanium oxide, indium tin oxide to which silicon oxide is added, indium zinc oxide, or indium zinc oxide containing tungsten oxide can be given.

<Oxide Semiconductor Film and Electrode of Capacitor>

As the oxide semiconductor films441and442and the electrode444, one or two or more oxide films of an In—Ga oxide, an In—Zn oxide, an In-M-Zn oxide (M represents Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), or the like are formed. Note that the electrode444is formed using a conductive film which is the oxide film for forming the oxide semiconductor films441and442having low resistance.

For example, in the case where the oxide semiconductor films441and442are formed using an In-M-Zn oxide, the atomic ratio of In to M in the oxide when summation of In and M is assumed to be 100 atomic % is as follows: the proportion of In is preferably higher than or equal to 25 atomic % and the proportion of M is lower than 75 atomic %, further preferably the proportion of In is higher than or equal to 34 atomic % and the proportion of M is lower than 66 atomic %.

The oxide semiconductor films441and442can be each formed using an In—Ga—Zn oxide film whose atomic ratio of In to Ga and Zn is 1:1:1 or 3:1:2. Note that in the oxide film, the proportions of atoms in the atomic ratio vary within a range of ±20% as a margin.

The oxide semiconductor films441and442are each formed using an oxide film whose energy gap is greater than or equal to 2 eV, for example. The energy gap is preferably greater than or equal to 2.5 eV, further preferably greater than or equal to 3 eV. The off-state current of the transistors301and303can be reduced by using an oxide film having a wide energy gap.

An oxide semiconductor film with low carrier density is used as the oxide semiconductor films441and442. For example, an oxide semiconductor film whose carrier density is lower than or equal to 1×1017/cm3, preferably lower than or equal to 1×1015/cm3, further preferably lower than or equal to 1×1013/cm3, still further preferably lower than or equal to 1×1011/cm3is used as the oxide semiconductor films441and442.

When silicon or carbon, which is one of elements belonging to Group 14, is contained in the oxide semiconductor films441and442, the number of oxygen vacancies is increased in the oxide semiconductor films441and442, and the oxide semiconductor films441and442become n-type films. Thus, the concentrations of silicon and carbon in the oxide semiconductor films441and442are set to be less than or equal to 2×1018atoms/cm3, preferably less than or equal to 2×1017atoms/cm3. These concentrations can be measured by secondary ion mass spectrometry (SIMS).

Moreover, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor films441and442is preferably lower than or equal to 1×1018atoms/cm3, further preferably lower than or equal to 2×1016atoms/cm3. This is because when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, carriers are generated in some cases, which causes an increase in off-state current of the OS transistors.

It is preferable that nitrogen be not contained in the oxide semiconductor films441and442as much as possible. Nitrogen causes an electron that is a carrier. When the concentration of nitrogen gets higher, the carrier density in the oxide semiconductor film is increased and the oxide semiconductor film easily becomes an n-type film. Therefore, when the concentrations of nitrogen in the oxide semiconductor films441and442are high, the transistors301and303tend to have normally-on characteristics. The concentrations of nitrogen in the oxide semiconductor films441and442are preferably lower than or equal to 5×1018atoms/cm3.

The concentrations of impurities (nitrogen, an alkali metal, or the like) in the oxide semiconductor films441and442can be measured by secondary ion mass spectrometry (SIMS).

The thicknesses of the oxide semiconductor films441and442and the electrode444are greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, further preferably greater than or equal to 3 nm and less than or equal to 50 nm.

Both the oxide semiconductor films441and442and the electrode444are formed over the insulating film452but differ in impurity concentration. The oxide semiconductor films441and442each have a lower concentration of impurities than the electrode444. For example, the concentration of hydrogen in each of the oxide semiconductor films441and442is lower than 5×1019atoms/cm3, preferably lower than 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, still further preferably lower than or equal to 5×1017atoms/cm3, yet still further preferably lower than or equal to 1×1016atoms/cm3. The concentration of hydrogen in the electrode444is higher than or equal to 8×1019atoms/cm3, preferably higher than or equal to 1×1020atoms/cm3, further preferably higher than or equal to 5×1020atoms/cm3. The concentration of hydrogen in the oxide film for forming the electrode444is 2 times or more, preferably 10 times or more those of hydrogen in the oxide semiconductor films441and442. By improving the concentration of hydrogen in such a manner, the resistivity of the oxide film can be reduced sufficiently.

That is, the resistivity of the electrode444is lower than those of the oxide semiconductor films441and442. The resistivity of the electrode444is set to 1/10 times those of the oxide semiconductor films441and442. The resistivity of the electrode444is preferably reduced to approximately 1×10−8times those of the oxide semiconductor films441and442. The resistivity of the electrode444is typically greater than or equal to 1×10−3Ωcm and less than 1×104Ωcm, preferably greater than or equal to 1×10−3Ωcm and less than 1×10−1Ωcm.

Note that the oxide semiconductor film for forming the oxide semiconductor films441and442are not limited to that described in this embodiment. A film having an appropriate composition may be selected depending on semiconductor characteristics and electrical characteristics (e.g., field-effect mobility and threshold voltage) of the OS transistors. Further, in order to obtain needed semiconductor characteristics of the OS transistors, for example, the carrier density, the impurity concentration, the defect density, the atomic ratio of a metal element to oxygen, the interatomic distance, the density, and the like of the oxide semiconductor films441and442are preferably set to be appropriate.

When an oxide semiconductor film in which the impurity concentration is low and density of defect states is low is used for the oxide semiconductor films441and442, the transistors301and303can have excellent electrical characteristics.

A crystal structure of an oxide semiconductor film for forming the oxide semiconductor films441and442is described below.

In this specification, a term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 100, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, a term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 800 and less than or equal to 1000, and accordingly includes the case where the angle is greater than or equal to 85° and less than or equal to 950.

In this specification, the trigonal and rhombohedral crystal systems are included in the hexagonal crystal system.

An oxide semiconductor film is classified roughly into a single-crystal oxide semiconductor film and a non-single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film includes any of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film, and the like.

The amorphous oxide semiconductor film has disordered atomic arrangement and no crystalline component. A typical example thereof is an oxide semiconductor film in which no crystal part exists even in a microscopic region, and the whole of the film is amorphous.

The microcrystalline oxide semiconductor film includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Thus, the microcrystalline oxide semiconductor film has a higher degree of atomic order than the amorphous oxide semiconductor film. Hence, the density of defect states of the microcrystalline oxide semiconductor film is lower than that of the amorphous oxide semiconductor film.

The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm. Thus, there is a case where a crystal part included in the CAAC-OS film fits inside a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm. The density of defect states of the CAAC-OS film is lower than that of the microcrystalline oxide semiconductor film. The CAAC-OS film is described in detail below.

Further, the degree of crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where crystal growth leading to the CAAC-OS film occurs from the vicinity of the top surface of the film, the degree of the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the formation surface in some cases. Further, when an impurity is added to the CAAC-OS film, the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS film varies depending on regions.

In a transistor using the CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Thus, the transistor has high reliability.

Note that an oxide semiconductor film may be a stacked film including two or more films of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

The film of the electrode444has the same crystallinity as the oxide semiconductor films441and442.

The insulating film451is preferably formed using a nitride insulating film of silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide, for example.

As the insulating film452, a film capable of improving characteristics of an interface with the oxide semiconductor films441and442is preferably formed. The insulating film452can be formed to have a single-layer structure or a stacked-layer structure using, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a gallium oxide film, a Ga—Zn-based metal oxide film, or a film including a high-k material such as hafnium oxide. The use of the film including a high-k material enables a reduction in gate leakage current in the transistors301and303. As a high-k material, there is hafnium silicate (HfSixOy), hafnium silicate to which nitrogen is added, hafnium aluminate (HfAlxOy), hafnium aluminate to which nitrogen is added, yttrium oxide, or the like.

The total thickness of the insulating films451and452is greater than or equal to 5 nm and less than or equal to 400 nm, preferably greater than or equal to 10 nm and less than or equal to 300 nm, further preferably greater than or equal to 50 nm and less than or equal to 250 nm.

For the insulating film453, in a manner similar to that of the insulating film452, a material capable of improving characteristics of the interface with the oxide semiconductor films441and442is preferably used. The insulating film453can be formed using an oxide insulating film, for example. Here, the insulating film453is formed to have a stacked-layer structure of an insulating film453aand an insulating film453b. The insulating film453afunctions as a film that relieves damage to the oxide semiconductor films441and442and the electrode444at the time of forming the insulating film453b.

It is preferable that the insulating film453abe formed using an insulating film which transmits oxygen. When the insulating film which transmits oxygen is formed as the insulating film453a, oxygen released from the insulating film453bcan be transferred to the oxide semiconductor films441and442through the insulating film453a, so that oxygen vacancies in the oxide semiconductor films441and442can be reduced. Note that all oxygen atoms entering the insulating film453afrom the outside are not moved to the outside of the insulating film453aand some oxygen atoms remains in the insulating film453ain some cases. Further, transfer of oxygen occurs in the insulating film453ain some cases in such a manner that oxygen enters the insulating film453aand oxygen contained in the insulating film453ais moved to the outside of the insulating film453a.

As the insulating film453a, a silicon oxide film, a silicon oxynitride film, or the like having a thickness greater than or equal to 5 nm and less than or equal to 150 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm can be used. In this specification, oxynitride refers to a substance which includes more oxygen than nitrogen, and nitride oxide refers to a substance which includes more nitrogen than oxygen.

The insulating film453bis formed using an insulating film including oxide or oxynitride. The oxide or oxynitride for forming the insulating film453bpreferably contains oxygen at a higher proportion than that in the stoichiometric composition. With such a composition, the insulating film453bis in a state that some oxygen atoms are likely to be released therefrom when heated. The insulating film containing oxygen at a higher proportion than that in the stoichiometric composition is a film of which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018atoms/cm3, preferably greater than or equal to 3.0×1020atoms/cm3in TDS analysis.

As the insulating film453b, a silicon oxide film, a silicon oxynitride film, or the like having a thickness greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 50 nm and less than or equal to 400 nm can be used.

Further, it is preferable that the amount of defects at the interface between the insulating film453aand the oxide semiconductor films441and442be small. In order to achieve that, it is preferable that the electron spin density of a signal which appears at g=1.93 due to the defects in the oxide semiconductor films441and442be lower than or equal to 1×1017spins/cm3, further preferably lower than or equal to the lower limit of detection. Note that a g factor of the electron spin and density thereof can be calculated from an electron spin resonance (ESR) spectrum. The same applies to the description below.

Further, it is preferable that the insulating films453aand453bhave few defects. This is because if the density of defects in the insulating films453aand453bis high, oxygen is bonded to the defects and the amount of oxygen that is transmitted through the insulating film453ais decreased. Different from the insulating film453a, the insulating film453bdoes not have an interface with the oxide semiconductor films441and442and the electrode444; thus, the insulating film453bmay have higher defect density than the insulating film453a. The electron spin density of the insulating film453aof a signal which appears at g=2.001 is preferably lower than or equal to 3×1017spins/cm3, and that of the insulating film453bis preferably lower than 1.5×1018spins/cm3, further preferably lower than or equal to 1×1018spins/cm3. The electron spins of the signal which appears at g=2.001 are due to a dangling bond of silicon.

It is preferable to form the insulating film454using a film having a blocking effect against impurities such as oxygen, hydrogen, water, an alkali metal, and an alkaline earth metal. As such an insulating film, there are a nitride insulating film and a nitride oxide insulating film, specifically a film including silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. When the insulating film454having the blocking effect is formed, oxygen can be prevented from diffusing from the oxide semiconductor films441and442and the electrode444to the outside.

The insulating film454can be a stacked film in which an oxide insulating film or an oxynitride insulating film having a blocking effect against impurities such as oxygen, hydrogen, and water is formed over the nitride insulating film having the blocking effect. As the oxide insulating film having such a blocking effect, there is an insulating film including aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride.

In order to adjust the capacitance value of the capacitor304, an insulating film including nitride, nitride oxide, or oxide may be provided over the nitride insulating film having the blocking effect as the insulating film454.

An alignment film461can be formed using an organic resin such as polyimide. The thickness of the alignment film461is preferably greater than or equal to 40 nm and less than or equal to 100 nm, further preferably greater than or equal to 50 nm and less than or equal to 90 nm. With such a thickness, the pretilt angles of the liquid crystal material of the liquid crystal layer460can be made large, which can reduce disclination.

<Color Filter and Black Matrix>

The colored film472having a colored property is formed on the substrate402. The colored film472functions as a color filter. The colored film472is not necessarily provided in the case where the LCD10is a monochrome display device or a field-sequential method is employed as the display method, for example.

The colored film472is a colored film that transmits light in a specific wavelength range. For example, a red (R) color filter for transmitting light in a red wavelength range, a green (G) color filter for transmitting light in a green wavelength range, a blue (B) color filter for transmitting light in a blue wavelength range, or the like can be used.

Further, the light-blocking film471adjacent to the colored film472is formed on the substrate402. The light-blocking film471functions as a black matrix. Here, the gate driver is covered with the light-blocking film471. The light-blocking film471preferably has a function of blocking light in a specific wavelength region, and can be formed using a metal film, an organic insulating film including a black pigment, or the like.

An example of a method for manufacturing the LC panel illustrated inFIG. 20is described below.

<Manufacture of Element Substrate>

First, a method for manufacturing the element substrate which serves as a backplane of the LC panel is described with reference toFIGS. 21A to 21C,FIGS. 22A to 22C,FIGS. 23A to 23C, andFIGS. 24A to 24C.

Here, a glass substrate is used as the substrate401. In order to form the wiring412and the gate lines411and413in the first layer, a conductive film having a single-layer structure or a stacked-layer structure of two or more layers is formed over the substrate401. Examples of a formation method of the conductive film include a CVD method, a sputtering method, and a spin coating method. The gate line411, the wiring412, and the gate line413are formed from the conductive film through a photolithography process and an etching step (FIG. 21A).

Next, the insulating film451is formed over the wiring412and the gate lines411and413in the first layer, and the insulating film452is formed over the insulating film451(FIG. 21A). The insulating films451and452can be formed by a sputtering method, a CVD method, or the like. Note that it is preferable that the insulating films451and452be formed in succession without exposure to the air, in which case entry of impurities is suppressed.

Next, an oxide semiconductor film440is formed over the insulating film452(FIG. 21B).

The oxide semiconductor film440can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, or the like.

The oxide semiconductor film440is processed into island-shaped oxide semiconductor films441to443by a photolithography process and an etching step. In the etching step, either or both of dry etching and wet etching may be performed (FIG. 21C).

After that, hydrogen, water, and the like may be released from the oxide semiconductor films441to443by heat treatment and hydrogen and water in the oxide semiconductor films441to443may be reduced. Through such heat treatment, the oxide semiconductor films441to443can be highly purified. The heat treatment is performed typically at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C. Note that in the case where a large-sized substrate is used as the substrate401, the heat treatment is performed typically at a temperature higher than or equal to 300° C. and lower than or equal to 400° C., preferably higher than or equal to 320° C. and lower than or equal to 370° C. In such a temperature range, a warp or shrink of the substrate can be reduced and a decrease in yield can be suppressed.

An electric furnace, an RTA apparatus, or the like can be used for the heat treatment. With the use of the RTA apparatus, only in a short time, the heat treatment can be performed at a temperature higher than or equal to the strain point of the substrate401. Thus, cycle time of the heat treatment can be shortened, which is particularly preferable in a large-sized substrate.

The heat treatment may be performed under an atmosphere of nitrogen, oxygen, ultra-dry air (air in which a water content is 20 ppm or less, preferably 1 ppm or less, further preferably 10 ppb or less), or a rare gas (argon, helium, or the like). It is preferable that the above atmosphere do not contain hydrogen, water, or the like. The atmosphere can be changed. For example, heat treatment can be first performed in a nitrogen atmosphere or a rare gas atmosphere and then heat treatment can be additionally performed in an oxygen atmosphere or an ultra-dry air atmosphere. In that case, hydrogen, water, and the like can be released from the oxide semiconductor films441to443through the first heat treatment and oxygen can be supplied to the oxide semiconductor films441to443through the second heat treatment. Thus, oxygen vacancies in the oxide semiconductor films441to443can be reduced.

Next, a conductive film420is formed over the insulating film452and the oxide semiconductor films441to443by a sputtering method or the like (FIG. 22A).

Next, the source line421, the drain line422, the wiring423, the source line424, the electrode425, and the wiring426are formed from the conductive film420through a photolithography process and an etching step (FIG. 22B). The wiring423and the wiring412are formed so as to overlap with each other, so that areas occupied by the wiring423and the electrode431for connecting the wiring423to the wiring412can be made small.

Next, the insulating film453is formed so as to cover the insulating film452, the oxide semiconductor films441to443, and the wirings423and426, the source line421, the drain line422, the source line424, and the electrode425in the second layer (FIG. 22C).

Here, for the formation of the insulating film453, the insulating film453ais formed, and then the insulating film453bis formed in succession without exposure to the air. After the formation of the insulating film453a, the insulating film453bis formed in succession by adjusting at least one of the flow rate of the source gas, the pressure, the high-frequency power, and the substrate temperature without exposure to the air, whereby the concentration of impurities attributed to the air at the interface between the insulating film453aand the insulating film453bcan be reduced.

As the insulating film453a, a silicon oxide film or a silicon oxynitride film can be formed under the following conditions: the substrate placed in a treatment chamber of a plasma CVD apparatus, which is vacuum-evacuated, is held at a temperature higher than or equal to 180° C. and lower than or equal to 400° C., preferably higher than or equal to 200° C. and lower than or equal to 370° C., the pressure of the treatment chamber to which a source gas is introduced is greater than or equal to 20 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 250 Pa, and a high-frequency power is supplied to an electrode provided in the treatment chamber.

The bonding strength of silicon and oxygen in the silicon oxide film or the silicon oxynitride film becomes strong in the above temperature range. Thus, a silicon oxide film and a silicon oxynitride film which are dense and hard and which transmit oxygen can be formed. Typically, a silicon oxide film or a silicon oxynitride film of which etching using hydrofluoric acid of 0.5 wt % at 25° C. is performed at a rate of lower than or equal to 10 nm/min, preferably lower than or equal to 8 nm/min can be formed.

As a source gas of the silicon oxide film or the silicon oxynitride film, a deposition gas containing silicon and an oxidizing gas are preferably used. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide can be given as examples.

It is preferable to reduce the concentration of hydrogen in the insulating film453ain order to reduce the concentrations of hydrogen in the oxide semiconductor films441and442. For example, in the case of using a silicon oxide film or a silicon oxynitride film as the insulating film453a, the amount of the oxidizing gas is 100 or more times the amount of a deposition gas containing silicon.

With the use of the above conditions, an oxide insulating film which transmits oxygen can be formed as the insulating film453a. Further, with the insulating film453a, damage to the oxide semiconductor films441to443can be reduced in a step of forming the insulating film453bwhich is formed later.

The oxide semiconductor films441to443are heated by the formation of the insulating film453ain the above substrate temperature range, so that hydrogen, water, or the like can be released from these films.

Further, time for heating in a state where the oxide semiconductor films441to443are exposed can be shortened because heating is performed in a step of forming the insulating film453a. Thus, the amount of oxygen released from the oxide semiconductor films441to443by heat treatment can be reduced. Accordingly, an increase of oxygen vacancies in the oxide semiconductor films441to443is suppressed.

Note that by setting the pressure in the treatment chamber to be greater than or equal to 100 Pa and less than or equal to 250 Pa, the amount of water contained in the insulating film453ais reduced; thus, fluctuations in electrical characteristics of the transistors301and303can be reduced and changes in threshold voltage can be suppressed. Moreover, damage to the oxide semiconductor films441to443at the time of forming the insulating film453acan be reduced.

Note that when the ratio of the amount of the oxidizing gas to the amount of the deposition gas containing silicon is 100 or higher, the hydrogen content of the insulating film453acan be reduced. Consequently, the amount of hydrogen entering the oxide semiconductor films441to443can be reduced; thus, the negative shift in the threshold voltage of the transistor can be suppressed.

Here, as the insulating film453b, a silicon oxide film or a silicon oxynitride film is formed with a plasma CVD apparatus. As the film formation conditions, the substrate temperature is higher than or equal to 180° C. and lower than or equal to 280° C., preferably higher than or equal to 200° C. and lower than or equal to 240° C. The pressure of the treatment chamber to which a source gas is introduced is preferably greater than or equal to 100 Pa and less than or equal to 250 Pa, further preferably greater than or equal to 100 Pa and less than or equal to 200 Pa. A high-frequency power is higher than or equal to 0.17 W/cm2and lower than or equal to 0.5 W/cm2, preferably higher than or equal to 0.25 W/cm2and lower than or equal to 0.35 W/cm2.

As a source gas of the silicon oxide film or the silicon oxynitride film, a deposition gas containing silicon and an oxidizing gas may be used. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide can be given as examples.

The flow rate of the deposition gas containing silicon relative to the oxidizing gas can be increased, whereby the amount of defects in the insulating film453bcan be reduced. The electron spin density of the insulating film453bis preferably lower than 6×1017spins/cm3, preferably lower than or equal to 3×1017spins/cm3, further preferably lower than or equal to 1.5×1017spins/cm3.

The high-frequency power having such a high power density as described above is supplied, whereby the decomposition efficiency of the source gas in plasma is increased, oxygen radicals are increased, and oxidation of the source gas proceeds; therefore, the oxygen content of the silicon oxide film or the silicon oxynitride film can be made higher than that in the stoichiometric composition. When the substrate temperature is in the above temperature range, the bonding strength of silicon and oxygen is weak; therefore, part of oxygen is likely to be released by heating. Thus, it is possible to form a silicon oxide film or a silicon oxynitride film which contains oxygen at a higher proportion than that in the stoichiometric composition and from which part of oxygen is released by heating. Such a silicon oxide film or a silicon oxynitride film may be formed as the insulating film453b.

The oxide semiconductor films441to443are protected by the insulating film453aeven when the insulating film453bis formed by high-frequency power having a high power density; therefore, the insulating film453bwhich is effective in improving characteristics of the OS transistors can be formed while damage to the oxide semiconductor films441to443is suppressed.

Next, heat treatment is performed. The heating temperature is typically higher than or equal to 150° C. and lower than the strain point of the substrate, preferably higher than or equal to 200° C. and lower than or equal to 450° C., further preferably higher than or equal to 300° C. and lower than or equal to 450° C. Note that in the case where a large-sized substrate is used as the substrate401, the heat treatment is performed typically at a temperature higher than or equal to 300° C. and lower than or equal to 400° C., preferably higher than or equal to 320° C. and lower than or equal to 370° C. In such a temperature range, a warp or shrink of the large-sized substrate can be reduced.

An electric furnace, an RTA apparatus, or the like can be used for the heat treatment. With the use of the RTA apparatus, only in a short time, the heat treatment can be performed at a temperature higher than or equal to the strain point of the substrate401. Therefore, the heat treatment time can be shortened.

The heat treatment may be performed under an atmosphere of nitrogen, oxygen, ultra-dry air (air in which a water content is 20 ppm or less, preferably 1 ppm or less, further preferably 10 ppb or less), or a rare gas (argon, helium, or the like). Impurities for the oxide semiconductor films441to443, such as hydrogen and water, are prevented as much as possible from entering the atmosphere.

By the heat treatment, part of oxygen contained in the insulating film453bis transferred to the oxide semiconductor films441to443, so that the oxygen vacancies in the oxide semiconductor films441to443can be reduced.

Although, in some cases, the oxide semiconductor films441and442are damaged by etching of the conductive film420at the formation of the wirings423and426, the source line421, the drain line422, the source line424, and the electrode425in the second layer and oxygen vacancies are generated on the back channel sides of the transistors301and303, the oxygen vacancies can be repaired by the heat treatment. Therefore, reliability of the transistors301and303can be improved.

It is preferable to perform the heat treatment before the formation of the insulating film454. This is because since the insulating film454is formed as a blocking film against water, hydrogen, and the like, when the heat treatment is performed with the insulating film454, water, hydrogen, and the like which are contained in the insulating film453cannot be released to the atmosphere, and thus they are transferred to the oxide semiconductor films441to443.

In the case where the insulating film453bis formed while being heated, the heat treatment is not necessarily performed as long as the oxygen vacancies of the oxide semiconductor films441to443are reduced by the formation of the insulating film453b. Alternatively, the heat treatment may be performed after formation of an opening491and an opening492in the insulating film453.

Next, the openings491and492are formed in the insulating film453by a photolithography process and an etching step (FIG. 23A). The opening491is formed in the connection portion302to expose the surface of the wiring423. The opening492is formed in the capacitor304to expose the surface of the oxide semiconductor film443.

Next, the insulating film454is formed over the insulating films452and453and the oxide semiconductor film443(FIG. 23B).

The insulating film454may be formed using a material which can prevent diffusion of impurities from the outside, for example, oxygen, hydrogen, water, an alkali metal, and an alkaline earth metal into the oxide semiconductor film. In addition, the insulating film454preferably contains hydrogen. Hydrogen is contained in the insulating film454to reduce the resistance of the oxide semiconductor film443by supply of hydrogen thereto. When the insulating film454contains hydrogen and the hydrogen diffuses into the oxide semiconductor film443, hydrogen is bonded to oxygen in the oxide semiconductor film443, thereby generating an electron serving as a carrier. Thus, the oxide semiconductor film443has higher conductivity, thereby serving as the electrode444formed with a conductive film.

For example, a silicon nitride film or a silicon nitride oxide film may be formed by a plasma CVD method as the insulating film454. The substrate temperature at the deposition of the insulating film454is set at a range within which a phenomenon in which carrier concentrations of the oxide semiconductor films441and442are increased by release of oxygen therefrom is not caused.

Next, an opening493and an opening494are formed in the insulating films451,452, and454by a photolithography process and an etching step (FIG. 23C). The surfaces of the wirings412and423are exposed by the formation of the opening493in the connection portion302. Moreover, the opening494is formed in the transistor303to connect the electrode425and the pixel electrode432.

A conductive film430is formed over the insulating film454by a sputtering method or the like (FIG. 24A). The electrode431and the pixel electrode432are formed from the conductive film430by a photolithography process and an etching step (FIG. 24B).

Circuits (pixel circuits and gate drivers) are formed over the substrate401through the above process. In the process, the terminal portion is also formed over the substrate401. Further, the alignment film461is formed as needed over the substrate401in a sealing process (FIG. 24C).

In the method for manufacturing the element substrate of this embodiment, in the gate driver, the electrode431in the third layer (in the same layer as the pixel electrode) connects the wiring in the first layer and the wiring in the second layer. Therefore, it is not necessary to form the opening for connecting the wiring in the first layer and the wiring in the second layer in the insulating films451and452; thus, the number of light-exposure masks can be reduced by one. Therefore, in this embodiment, the element substrate can be formed with six sheets of light-exposure masks.

<Manufacture Of Counter Substrate>

An example of a manufacturing process of the counter substrate of the LC panel is described with reference toFIGS. 25A to 25C. The counter substrate is also referred to as a color filter substrate and the like.

The light-blocking film471and the colored film472are formed over the substrate402(seeFIG. 25A). The insulating film473is formed over the light-blocking film471and the colored film472(seeFIG. 25B).

As the insulating film473, an organic insulating film of an acrylic resin, an epoxy resin, polyimide, or the like can be used, for example. The insulating film473is formed as an overcoat of the color filter and the black matrix. The insulating film473may be formed as needed.

Next, the counter electrode433is formed over the insulating film473. The counter electrode433is formed using a light-transmitting conductive film formed by a sputtering method or the like. A spacer470is formed over the counter electrode433. The spacer470can be formed in such a manner that the counter electrode433is coated with a photosensitive resin and subjected to developing treatment. Through the above process, the counter substrate is formed. In the sealing process described later, the counter substrate is provided with the alignment film.

A process of sealing the liquid crystal layer460between the element substrate and the counter substrate to manufacture the LC panel is described.

The alignment film461is formed over the element substrate (substrate401). After the element substrate is cleaned, a surface of the element substrate is coated with a polyimide resin by a printing method or the like and then baked to form the alignment film461. Alignment treatment is performed on the alignment film461through rubbing or irradiation with light. The counter substrate is provided with the alignment film462in a similar manner.

Next, the counter substrate is coated with a sealant to seal the liquid crystal layer460. Here, an ultraviolet curable sealant for a one drop filling (ODF) method is used. Next, the liquid crystal material is dropped in a region of the counter substrate surrounded by the sealant. This step is performed in a nitrogen atmosphere. Then, the element substrate and the counter substrate are attached to each other. Then, irradiation with ultraviolet rays is performed to cure the sealant, so that the sealing member is completed.

Through the above sealing process, the LC panel in which the liquid crystal layer460is sealed between the element substrate and the counter substrate is manufactured. A member such as an FPC, which is needed, may be further attached to the LC panel.

This embodiment can be combined as appropriate with the other embodiment in this specification.

In this embodiment, another structural example of the pixel circuit30is described. Specifically, another structural example of the transistor and other structural examples of the capacitor are described.

FIG. 26Aillustrates another structural example of the transistor. In a transistor313, the insulating film453functioning as a channel protective film is provided over the oxide semiconductor film442. Therefore, the insulating film453is formed before the formation of the conductive film420. A portion of the insulating film453other than the portion functioning as the channel protective film is removed by etching. After the etching step, the conductive film420is formed.

Since the insulating film453is provided over the oxide semiconductor film442, the oxide semiconductor film442can be prevented from being damaged in the etching step of the conductive film420. Therefore, the insulating film453is called as an etching stop film. A gate insulating film of the transistor313is a stack film of the insulating film451and the insulating film452in a manner similar to that of the gate insulating film of the transistor303; however, in the transistor313, the insulating film452exists only in a region overlapping with the oxide semiconductor film442and the electrode444by the formation of the channel protective film.

The transistor of each of the gate drivers21and22is formed in a manner similar to that of the transistor313.

FIG. 26Billustrates another structural example of the capacitor. A capacitor314includes the pixel electrode432, an electrode501, and the insulating film454. The electrode501is formed using a conductive film similar to that used for the pixel electrode432, which has a light-transmitting property. Note that inFIG. 26B, the transistor313ofFIG. 26Acan be used.

FIG. 26Cillustrates another structural example of the capacitor. As illustrated inFIG. 26C, an insulating film510is formed so as to cover the transistor303. The insulating film510is formed as a planarization film. An electrode511, an insulating film513, and a pixel electrode512are formed over the insulating film510. A capacitor315includes the electrode511, the pixel electrode512, and the insulating film513.

The electrode511and the pixel electrode512can be formed in manners similar to that of the pixel electrode432. The insulating film513can be formed in a manner similar to that of the insulating film454.

For the insulating film510, a resin film of acrylic, polyimide, epoxy, or the like can be used. The thickness of the insulating film510is preferably greater than or equal to the thickness of the insulating film453and less than or equal to 1500 nm, further preferably greater than or equal to the thickness of the insulating film453and less than or equal to 1000 nm. The thickness of the insulating film510is greater than or equal to the thickness of the insulating film453, so that a depressed portion of the pixel electrode512can be filled with the insulating film510and unevenness of a region where the alignment film461is formed can be reduced. As the insulating film510gets thicker, voltage for controlling the alignment of the liquid crystal layer460, which is applied to the pixel electrode432, becomes higher and power consumption of the LCD10becomes higher. Therefore, it is preferable that the thickness of the insulating film510be less than or equal to 1500 nm.

This embodiment can be combined as appropriate with the other embodiment in this specification.

The display device of one embodiment of the present invention can be applied to a display portion of any of a variety of electronic devices (including game machines). Examples of electronic devices include television sets (also referred to as televisions or television receivers), monitors of computers, cameras such as digital cameras or digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, audio reproducing devices, and game machines (e.g., pachinko machines or slot machines). Examples of such electronic devices are illustrated inFIGS. 27A to 27C.

FIG. 27Aillustrates a table9000having a display portion. In the table9000, a display portion9003is incorporated in a housing9001and an image can be displayed on the display portion9003. Note that the housing9001is supported by four leg portions9002. Further, a power cord9005for supplying power is provided for the housing9001.

The display portion9003has a touch-input function. When a user touches displayed buttons9004which are displayed on the display portion9003of the table9000with his/her finger or the like, the user can carry out operation of the screen and input of information. Further, when the table9000may be made to communicate with home appliances or control the home appliances, the table9000may serve as a control device which controls the home appliances by operation on the screen. For example, with the use of a semiconductor device having an image sensor function, the display portion9003can have a touch-input function.

Further, the screen of the display portion9003can be placed perpendicular to a floor with a hinge provided for the housing9001; thus, the table9000can also be used as a television device. When a television device having a large screen is set in a small room, an open space is reduced; however, when a display portion is incorporated in a table, a space in the room can be efficiently used.

FIG. 27Billustrates a television set9100. In the television set9100, a display portion9103is incorporated in a housing9101and an image can be displayed on the display portion9103. Note that here, the housing9101is supported by a stand9105.

The television set9100can operate with an operation switch of the housing9101or a separate remote controller9110. Volume and receiving channels can be controlled with an operation key9109of the remote controller9110so that an image displayed on the display portion9103can be controlled. Further, the remote controller9110may be provided with a display portion9107for displaying data on the operation of the television set9100, the time, a date, and the like.

The television set9100is provided with a receiver, a modem, and the like. With the use of the receiver, the television set9100can receive general TV broadcasts. Moreover, when the television set9100is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can be performed.

FIG. 27Cillustrates a computer9200. The computer9200includes a main body9201, a housing9202, a display portion9203, a keyboard9204, an external connection port9205, a pointing device9206, and the like.

The semiconductor device described in any of the above embodiments can be used for the display portion9203. Thus, the display quality of the computer9200can be improved.

FIGS. 28A and 28Billustrate a foldable tablet terminal9600. The foldable tablet terminal9600includes a housing9630, a display portion96311a, a display portion9631b, a display-mode switching button9034, a power button9035, a power-saving-mode switching button9036, a clip9033, an operation button9038, and the like.

Further, the foldable tablet terminal9600includes a solar battery9633and a charge and discharge control circuit9634. Note thatFIG. 28Billustrates an example in which the charge and discharge control circuit9634includes a battery9635and a DCDC converter9636.

Part of the display portion96311acan be a touch panel region9632a, and data can be input by touching operation keys9638that are displayed. Note thatFIG. 28Ashows, as an example, that half of the area of the display portion9631ahas only a display function, and the other half of the area has a touch panel function. However, the structure of the display portion96311ais not limited to this, and all the area of the display portion9631amay have a touch panel function. For example, all the area of the display portion96311acan display keyboard buttons and function as a touch panel while the display portion9631bcan be used as a display screen.

In the display portion9631b, as in the display portion9631a, part of the display portion9631bcan be a touch panel region9632b. When a finger, a stylus, or the like touches the place where a button9639for switching to keyboard display is displayed in the touch panel, keyboard buttons can be displayed on the display portion9631b.

Touch input can be performed concurrently on the touch panel regions9632aand9632b.

The display-mode switching button9034allows switching between a portrait mode and a landscape mode, and between monochrome display and color display, for example. With the power-saving-mode switching button9036, the luminance of display can be optimized in accordance with the amount of external light at the time when the tablet terminal is in use, which is detected with an optical sensor incorporated in the tablet terminal. The tablet terminal may include another detection device such as a sensor for detecting orientation (e.g., a gyroscope or an acceleration sensor) in addition to the optical sensor.

InFIG. 28A, the specification of the display portion9631bmay be different from that of the display portion9631a. For example, the screen size or resolution may be different.

Since the tablet terminal can be foldable, the housing9630can be closed when the tablet terminal is not in use. Thus, the display portions9631aand9631bcan be protected, whereby a tablet terminal with high endurance and high reliability for long-term use can be provided.

The tablet terminal illustrated inFIGS. 28A and 28Bcan also have a function of displaying various kinds of data (e.g., a still image, a moving image, and a text image) on the display portion, a function of displaying a calendar, a date, the time, or the like on the display portion, a touch-input function of inputting data by touching the display portion with a finger or the like, a function of executing various kinds of software (programs), and the like.

The solar battery9633, which is attached to the surface of the tablet terminal, supplies electric power to a touch panel, a display portion, an image signal processor, and the like. Note that the solar battery9633can be provided on one or both surfaces of the housing9630, so that the battery9635can be charged efficiently. When a lithium ion battery is used as the battery9635, there is an advantage of downsizing or the like.

FIG. 28Cis a block diagram of the charge and discharge control circuit9634. The structure and operation are described with reference to the block diagram. As shown inFIG. 28C, the charge and discharge control circuit9634is a control circuit for supplying electric power generated by the solar battery9633to the display portion9631. Here, the charge and discharge control circuit9634includes the battery9635, the DCDC converter9636, a converter9637, and switches SW1to SW3.

In the case where the electric power generated by the solar battery9633is charged to the battery9635, the switch SW2is turned on. The DCDC converter9636steps up or down an output voltage from the solar battery9633to a voltage appropriate for charge of the battery9635. The switch SW1is turned on when the electric power generated by the solar battery9633is supplied, and the switch SW3is turned on when the electric power is supplied from the battery9635to the display portion9631. The converter9637steps up or down an input voltage to a voltage necessary for driving the display portion9631.

Note that the solar battery9633is illustrated as an example of a power generation means; however, there is no particular limitation on the power generation means, and a piezoelectric element, a thermoelectric conversion element (Peltier element), or the like may be provided. Alternatively, a non-contact power transmission module which is capable of charging by transmitting and receiving power by wireless (without contact) may be provided.

This embodiment can be combined as appropriate with the other embodiment in this specification.

This application is based on Japanese Patent Application serial No. 2013-078202 filed with the Japan Patent Office on Apr. 4, 2013, the entire contents of which are hereby incorporated by reference.