Dynamic integration based current limiting for power converters

This application relates to a power converter for a computing device. The power converter can maintain an average output current while also allowing the output current to reach a peak current limit for periods of time. The average output current is maintained by enforcing a dynamic current limit on the output current. The dynamic current limit can change over time depending on whether the average output current is above or below an average current threshold. The changes to the dynamic current limit can occur at a rate defined by one or more time constants in order to reduce electromigration and maintain a temperature of the power converter below a predetermined temperature threshold.

FIELD

The described embodiments relate generally to power converters. More particularly, the present embodiments relate to power converters that can dynamically adjust an output current of the power converter to maintain an average current output for the power converter.

BACKGROUND

Power distribution within consumer electronics has become increasingly difficult to manage since the inception of electronic devices into consumer markets. For example, many mobile computing devices have been developed to take on responsibilities that require designers to incorporate more power consuming hardware into the devices. Although, a solution to the lack of available power within a device at any given time can be to include a larger power supply within the device, constraints due to physical size, thermal operating envelope, and battery capacity of a device can limit the size of certain device power supplies. As a result, many devices can occasionally experience frequent faults that can shorten the lifespan of a device or result in unpredictable behavior that could cause loss of data or other undesirable consequences.

SUMMARY

This paper describes various embodiments that relate to a power converter configured to allow for higher peak power delivery while enforcing an average current output and/or a direct current (DC) limit. In some embodiments, the power converter can include a logic component. The logic component can be configured to dynamically adjust a threshold current level according to whether an integrated current output signal is changing, in order to maintain a predetermined average current output of the power converter. Additionally, the logic component can be configured to throttle an output of the power converter when the output exceeds the threshold current level, wherein the output relates to a current provided by the power converter.

In other embodiments, a method is set forth for dynamically adjusting a current limit for a power converter to maintain an average current output for the power converter. The power converter can perform steps that include dynamically adjusting the current limit of the power converter according to whether previous output current values for the power converter correlate to the average current output that is above or below a predetermined average current threshold. Additionally, the steps can include throttling an output of the power converter when the output exceeds the current limit, wherein the output relates to a current provided by the power converter.

In yet other embodiments, a computing device is set forth. The computing device can include a power source and a power converter. The power converter can include one or more switches that are configured to toggle between switch states. A period between each switch state can be dynamically adjusted according to a rate of change of a summation of current signals. Additionally, the rate of change of the summation of current signals can be at least partially based on one or more predetermined time constants.

DETAILED DESCRIPTION

The described embodiments relate to power supplies that allow for a higher peak current limit while enforcing an average current and/or direct current (DC) limit. By allowing for a higher peak current, a device receiving power from a power supply can operate as a higher load without concern for exceeding a peak current limit. Furthermore, by enforcing the average current limit, degradation of the power supply can be mitigated over time. Certain devices, such as power supplies and power converters, can degrade as a result of temperature changes and electromigration. When electromigration and temperature are not controlled well within a device, certain components and connections between components can be compromised, rendering them inoperable. Electromigration of metal particles within a device can be most detrimental when fluctuations in current density are not adequately controlled. However, both thermal damage and electromigration can be mitigated by enforcing certain current limits within a device.

A peak current limit can be set within a device in order to prevent any currents transmitted within a device from exceeding the peak current limit. Additionally, an average current limit can be set within the device to ensure that any currents transmitted within the device stay at or near the average current limit, thereby controlling the current density within the device. In order to enforce the average current limit, one or more timers can be incorporated into the logic of the device. For example, when a peak current limit of a component of the device is reached by an output current of the component, the component can continue providing the output current at the peak current limit for a predetermined time limit. Once the predetermined time limit has expired, the output current can be reduced below the average current limit for another predetermined time limit. Each time limit can be set such that the total output current above the average current limit and below the average current limit over time averages to approximately the average current limit. Although this timer based approach can adequately enforce the average current limit, there are disadvantages to only allowing the output current to stay above the average current limit for only a predetermined amount of time. For example, performance of the device can be limited when the device treats all currents that exceed the average current limit the same. In order to optimize the performance of the device while also enforcing an average current limit, an integral based logic can be used.

An integral based logic for limiting the current of a device to an average current limit can be accomplished using a feedback loop for tracking the current over time. The current can be integrated or otherwise sequentially summed and used to adjust a dynamic current limit during operation of the device. For example, when an average output current of the device exceeds the average current limit, the dynamic current limit can be reduced as the integral of the output current increases. In this way, the output current is able to exceed the average current limit up to a peak current limit without a finite period being used for limiting how long the output current can remain above the average current limit. Once the average output current has been reduced to the average current limit or the integral of the output current has been reduced to a predetermined threshold, the dynamic current limit can thereafter be raised. By raising the dynamic current limit, the output current is able to increase as needed by a device receiving the output current without being restricted by how long the output current should remain at the average current limit. In some embodiments, the rate at which the dynamic current limit decreases can be set by one or more time constants, and the rate at which the dynamic current limit increases can be set by one or more of the same or different time constants.

The integral based logic for limiting the current of a device can be programmed or hardwired into a power converter of the device in order to limit an output current of the power converter. For example, the power converter can be a direct current (DC) to DC converter that includes one or more operational amplifiers, switches, inductors, and/or capacitors for effectively enforcing an average current limit on the power converter. The arrangement of these circuit components can depend on whether the one or more time constants are being enforced when reducing and/or raising the dynamic current limit. In some embodiments of the power converter where at least one time constant is used, one or more resistors and/or capacitors of an integrator circuit can define the time constant by which the dynamic current limit is reduced. The integrator circuit can be designed to integrate a difference between a sensed or filtered output current of the power converter and a current threshold for the power converter. An output of the integrator circuit can be connected to a multiplexer, which can also receive inputs corresponding to an instantaneous current limit and a voltage error limit. The multiplexer can output one of the inputs according to a configuration of the multiplexer. For example, the multiplexer can be configured to output the lowest of the three inputs. The output of the multiplexer can thereafter be provided to a comparator for comparing a signal representing the output current to the output of the multiplexer (e.g., the output of the multiplexer corresponding to either the instantaneous current limit, the voltage error limit, or the integrator circuit output). In some embodiments, when the output current is less than the multiplexer output, the output of the power converter will be unaffected by the comparator. However, when then the output current is greater than the multiplexer output, the output current of the power converter will be limited according to the multiplexer output. For example, the power converter can operate according to a clock signal that can control switching cycles of the power converter, and as a result, the multiplexer output can dynamically affect a period of some switching cycles of the power converter more or less than other switching cycles. Changes in the multiplexer output can be at least partially based on the time constant associated with the integrator circuit.

The integrator circuit can determine a rate at which the dynamic current limit of the output current of the power converter increases and decreases. For example, a single time constant (i.e., single pole) can provide a basis for the rate at which the dynamic current limit for the output current decreases or increases. Furthermore, the single time constant can be programmed or hardwired into the power converter. The single time constant can be based on the value of one or more resistors, capacitors, and/or inductors connected to the integrator circuit such that the dynamic current limit will scale according to the rate of increase or decrease of the output of the integrator circuit. In some embodiments of the power converter, multiple time constants (i.e., multiple poles) can be programmed or hardwired into the power converter. In this way, rates at which the dynamic current limit of the output current of the power converter increase and decrease can be the same or different.

In the multiple time constant embodiments of the power converter, a comparator and switch can be connected to the integrator circuit for selecting a time constant to increase or decrease the dynamic current limit. Depending on a state of the power converter, the comparator can cause the switch to select between one or more resistors, capacitors, and/or inductors connected to the integrator circuit to define the time constant to be employed at a given time. For example, when the output current of the power converter is decreasing towards the average current limit, the rate at which the output current is decreasing can be determined by a first time constant. When the output current of the power converter is increasing away from the average current limit, the rate at which the output current is increasing can be determined by a second time constant. In some embodiments, the increase and/or decrease of the output current can be based on multiple different time constants. Each time constant can be set according to any suitable number of characteristics exhibited by the power converter. For example, one or more time constants can be set to reduce an amount of electromigration occurring as a result of operating the power converter. Specifically, reducing the amount of the electromigration can be accomplished by setting one or more time constants to effectively maintain an average current or current density over the lifetime of the power converter. In some embodiments, one or more time constants can be set to maintain a thermal output of the power converter or other component at or below a suitable thermal limit. For example, the rate at which the output current decreases can be faster than a rate at which the output current increases. In this way, because increases in current correlate to increases in temperature, the time constant that governs the increase in output current for the power converter can be set to gradually increase the output current so as to not cause a harmful temperature increase. In some embodiments, one or more of the time constants can be variable or dynamic. For example, when a measured temperature is below a predetermined temperature threshold, the time constant that governs the increase in output current can allow the output current to increase faster than when the measured temperature is above the predetermined threshold. Similarly, when the output current is determined to be below the average current limit, the time constant(s) that governs the increase and decrease in output current can allow the output current to increase and/or decrease faster or slower compared to when the output current is above the average current limit.

FIG. 1Aillustrates a perspective view100of a computing device102that can incorporate logic for maintaining an average current limit for a component of the computing device102, as discussed herein. By maintaining an overall current output of the component at or near an average current limit, electromigration at certain portions of the computing device102can be mitigated thereby increasing a time to failure for the computing device102. The computing device102can be a cell phone, laptop, table computer, display, desktop computer, media player, or any other suitable electronic device in which electromigration can occur. Furthermore, it should be noted that the logic for maintaining the average current limit can also be incorporated into accessory devices such as power supplies, battery packs, wireless charging devices, or any other suitable accessory device that operates using electrical current. In some embodiments, the logic for maintaining the average current limit can be implemented as an analog or digital circuit that is hardwired or programmed into a device.

FIG. 1Billustrates a system diagram104of a power converter108that can regulate an amount of output current112from the power converter108according to an average current limit. The power converter108can be internal or external to the computing device102and a power source106that provides input current110to the power converter108can be internal or external to the computing device. For example, each of the power source106and the power converter108can be external to the computing device102in order to regulate an amount of current and/or voltage that can be received by the computing device102. In some embodiments, the power converter108is internal to the computing device102and the power source106is external to the computing device102. In this way, the power source106can be either a power adapter or a portable power source. In other embodiments, both the power source106and the power converter108are incorporated into the computing device102.

The power converter108can operate using a feedback loop. The feedback loop can be a hardwired or programmed feedback loop that causes a sensed current value of the output current112of the power converter108to be fed back as an input to the power converter108. The sensed current value is thereafter tracked over time to determine whether an average current limit for computing device102is being exceeded. Depending on whether the average current limit is being exceed or not, the power converter can regulate the output current112. In this way, the power converter108can ensure that the average current over the lifetime of the computing device102is at or near the average current limit. As a result, although the power converter108can allow current spikes to occur from time to time in order to boost performance of the computing device102, the average current for the power converter108will be kept at a level that promotes longevity for the computing device102.

FIG. 2illustrates a method200that can be performed by the power converter108in order to maintain the output current112of the power converter108at or near an average current limit. The method200can be performed by a logic component of the power converter, or any other suitable logic component that is internal or external to the computing device. The logic component can be hardwired to include components that are configured to perform the method200, or the logic component can include a processor and a memory for performing the method200according to instructions stored in the memory. The method200can include a step202of sensing a current signal. The current signal of step202can be the output current112that is sensed by a current sensor connected to the power converter108. The current sensor can track the output current112of the power converter108over time in order for the power converter108to make appropriate decisions about how to regulate the output current112. At step204of method200, a determination is made whether the current signal is above a first threshold. The first threshold can correspond to an average current limit stored by or accessible to the power converter108. The average current limit can be set in order mitigate any detrimental effects that can be caused by providing too much current over a conductor for a period of time. If the current signal is above the first threshold, then a dynamic current limit can be decreased in order to reduce the output current112of the power converter108. The dynamic current limit can be decreased and/or increased at a rate that is set to prevent high density currents from being output by the power converter108. For example, the rate at which the dynamic current limit increases and/or decreases can be associated with one or more time constants, as further discussed herein. As the dynamic current limit is increased at step206, the current signal can be sensed and step204can be repeated, similar to a feedback loop.

At step204, if the current signal is not above the first threshold, then at step208, a determination is made whether the dynamic current limit is equal to or above a second threshold. The second threshold can correspond to a maximum current limit or an instantaneous current limit. The second threshold can therefore be an upper limit for the output current112for protecting the power converter108. Although the power converter108can occasionally output a current that reaches or exceeds the second threshold, the output current112should not remain at the second threshold long enough to cause damage to the power converter and/or computing device102. Therefore, the second threshold can be based on a power specification of the power converter108, the computing device102, the power source106, and/or any other suitable component that can be connected to the computing device102. If the dynamic current limit is equal to or above the second threshold at step208, then the current signal will continue to be sensed at step202. If the dynamic current limit is not equal to or above the second threshold, then at step210, the dynamic current limit can be increased. The increase and decrease of the dynamic current limit at step210and step206, respectively, can be performed at one or more different rates that are based on one or more different time constants, as discussed herein.

FIG. 3illustrates a circuit diagram300of corresponding to different embodiments of the power converter108using a timer based approach for limiting current to an predetermined current threshold. The power converter108can be a buck converter or direct current (DC) to DC converter for stepping down a power supply input318. The power converter108can operate in cycles according to a clock input322provided to a flip flop308of the power converter108. During operation of the power converter108, the power supply input318will be provided to the high switch304and low switch320, which will periodically open and close according to the flip flop308output. The high switch304can periodically open when the low switch320is closed, and the high switch304can periodically close when the low switch320is open. In this way, a capacitor332and inductor326will charge and discharge periodically in manner that causes an output DC voltage, that is less than a DC component of the power supply input318, to be provided from the power converter108. An output current306corresponding to the output DC voltage can be fed back to a portion of the power converter108in order to determine whether to limit the output current306of the power converter108based on the output current306.

The output current306can be provided to a first comparator330for determining whether a voltage component of the output current306has fallen below a reference voltage312. The reference voltage312can correspond to a value for a minimum voltage threshold that the power converter108and/or the computing device102can operate at without harming the power converter108and/or the computing device102. If the voltage component of the output current306is above the reference voltage312, a voltage error signal314from the first comparator330will not limit the output current306. If the voltage component of the output current306is below the reference voltage312, the voltage error signal314of the first comparator330can limit the output current306. In this way, any remaining voltage from the power supply input318can be preserved until voltage of the power supply input318increases above the minimum voltage threshold.

The voltage error signal314can be provided to a switch328of the power converter108for further limiting the output current306according to a current limit signal310that is also provided to the switch328. In some embodiments, the switch328is a multiplexer that is configured to output a lowest input provided to the switch328. For example, if the current limit signal310is less than the voltage error signal314, then the current limit signal310will be output to a second comparator324. Otherwise, if the current limit signal310is greater than the voltage error signal314, the voltage error signal314will be provided to the second comparator324. The second comparator324can cause the flip flop308to turn off the high switch304when the sensed current302is greater than the signal being output from the switch328. Additionally, the second comparator324can cause the flip flop308to turn on the high switch304according to the clock input322and when the sensed current302is less than the signal being output from the switch328. For each cycle or period of the clock input322, the high switch304can be toggled or not toggled depending the output of the second comparator324. In this way, if the sensed current302remains at a value that does not indicate (i) the voltage of the power supply input318has dropped below the reference voltage and (ii) the output current306is not larger than the current limit signal310, the high switch304can toggle according to the clock input322. Otherwise, the high switch304will be turned off as long as the sensed current302remains at a value indicating that the voltage of the power supply input318has dropped below the reference voltage312. As a result of the high switch304being turned off during multiple cycles of the clock input322, the output current306will be reduced until either the voltage component of the output current306is above the reference voltage312or the output current306is at or below the current limit signal310.

FIG. 4illustrates a circuit diagram400of embodiments of the power converter108incorporating an integrator circuit402for limiting the output current306of the power converter108. The circuit diagram400can include many of the same elements of circuit diagram300ofFIG. 3. However, the circuit diagram400can include a switch406for switching between at least three different inputs and outputting at least one of the inputs into the second comparator324. At least one of the inputs to the switch406can be an integrator output410, which can define a dynamic current limit for the power converter108. The integrator circuit402can be configured to integrate a difference between a current limit412and an input current signal408corresponding to a sensed current output of the power converter108. In this way, the integrator circuit402will affect the output current306of the power converter108only when the integrator output410of the integrator circuit402reaches a certain value, or is otherwise increasing or decreasing. For example, if the input current signal408is approximately equal to the current limit412, a difference between the input current signal408and the current limit412, and thus the integrator output410, will initially be close to zero. However, as the integrator circuit402begins integrating the difference between the input current signal408and the current limit412, the integrator output410will begin to gradually increase thereby causing the dynamic current limit to decrease. In some embodiments, the current limit412can correspond to an average current threshold or a maximum current limit at which the power converter108is configured to maintain the output current at or below, respectively.

A rate at which the integrator output410increases can be at least partially defined by one or more time constants. The one or more time constants can be established using circuit component404, which can include one or more resistors, capacitors, and/or inductors, or any combination thereof. For example, in some embodiments the circuit component404can include a single capacitor, and in other embodiments the circuit component404can include multiple capacitors connected in series or parallel. The time constant can be a programmed value or hardwired value that corresponds to an average current level that is to be maintained at the output of the power converter108. Additionally, the time constant can correspond to a thermal output that is to maintained at the power converter108, or any other suitable component that the power converter108is connected to. In this way, a rate at which the output current306increases or decreases can be set so that the average current level and/or the thermal output of the power converter108does not exceed a predetermined threshold associated with the time constant(s).

During operation of the power converter108, the power converter108can selectively throttle the output current306according to the integrator output410. For example, the power converter108can allow the output current306to reach a value corresponding to the current limit signal310, which can be an upper current limit for the power converter108. At this point, the switch406can provide the current limit signal310as an output for comparing to the sensed current302at the second comparator324. If the sensed current302exceeds the current limit signal310, the second comparator324can output a signal to the flip flop308that can cause the high switch304to turn off for one or more cycles of the clock input322. As a result, the output current306of the power converter108can decrease to a value that is less than a value of the current limit signal310. However, because the integrator circuit402would have been integrating the input current signal408at least since the output current reached the current limit signal310, the switch406will output the integrator output410to the second comparator324. As a result, the integrator output410will act as the dynamic current limit for the output current306. The integrator output410can be a value that scales with a summation of a difference between the current limit signal310and the sensed current302. In this way, the integrator output410can change as the output current306changes. For example, as a result of the integrator output410decreasing, the second comparator324can eventually change its output to allow the high switch304to turn on again. In other words, once the sensed current302falls below the dynamic current limit (i.e., the integrator output410) to the extent that the average output current is at a predetermined average current threshold, the second comparator324will provide an output to the flip flop308. The output to the flip flop308can cause the high switch304to turn on or otherwise toggle according to the clock input322again.

If the output current306reaches a certain level indicating that the voltage of the power supply input318has dropped to or below a minimum voltage threshold, the high switch304can remain off until the voltage of the power supply input318rises above the minimum voltage threshold. For example, the voltage error signal314supplied to the switch406can be selected as an output by the switch406. The voltage error signal314can thereafter be compared to the sensed current302at the second comparator324. If the sensed current302is less greater than the voltage error signal314, then the second comparator324can provide a signal to the flip flop308that causes the flip flop308to shut off the high switch304. The high switch304can remain off until the sensed current302is equal to or greater than the voltage error signal314, indicating that the power supply input318has a suitable amount of voltage to continue operating. In this way, the power converter108can (i) prevent the output current306from exceeding a maximum current limit (e.g., the maximum current limit set by the current limit signal310), (ii) ensure that the power supply input318does not fall below a predetermined voltage level (e.g., the voltage level corresponding to the reference voltage312), and (iii) maintain the output current306at a level corresponding to a predetermined average current.

FIG. 5illustrates a circuit diagram500of embodiments of the power converter108incorporating an integrator circuit502for limiting a rate at which the output current306of the power converter108increases and decreases. The integrator circuit502can be programmed as a digital circuit in the power converter108or hardwired as an analog circuit in the power converter. The integrator circuit502can switch between one or more time constants depending on whether the integrator output410is increasing or decreasing. Each time constant can be defined by one or more of the components506,508, and510, which can each include a resistor, capacitor, inductor, conductor, semiconductor, or any other suitable component for defining a time constant of a signal. During operation of the integrator circuit502, an integrator comparator504can cause an integrator switch512to be closed or open depending whether the input current signal408is causing the integrator output410to be increasing or decreasing in amplitude. In other words, when the integrator output410(i.e., the dynamic current limit) is increasing, one or more of the components506,508, and510can define the time constant that governs the increase of the integrator output410. Additionally, when the integrator output410is decreasing, one or more of the components506,508, and510can define the time constant that governs the decrease of the integrator output410. In this way, the output current306can be caused to decrease faster than increase, or be caused to increase faster than decrease.

The current limit412provided to the integrator circuit502can also provide a basis for when the output current306will increase or decrease. The current limit412can correspond to a maximum current threshold or average current limit for the output current306of the power converter108. A difference between the current limit412and the input current signal408can be integrated over time in order to gage an average for the input current signal408. The integrator comparator504can be configured such that when the input current signal408is less than the current limit412, the integrator comparator504can cause the integrator switch512to be in a first state (e.g., opened or closed). Additionally, when the input current signal408is greater than the current limit412, the integrator comparator504can cause the integrator switch512to be in a second state (e.g., opened or closed) that is different than the first state. As a result, certain components of the components506,508, and510will define a time constant for the output current306depending on a relationship between the input current signal408and current limit412. Therefore, if the output current306stays above an average current threshold and causes the average current output to be above the average current threshold, the integrator circuit502can be configured to reduce the average current output back to the average current threshold.

FIG. 6illustrates a method600for controlling an increase of electrical current based on an average current threshold. The method600can be performed by the power converter108, computing device102, a power management unit of the computing device102, or any other suitable device, component, apparatus, processor capable of regulating current. The method600can include a step602of setting an output current below an average current threshold. The average current threshold can be based on a material composition, temperature specification, power output, and/or any other suitable metric related to the device performing method600. At step604, a dynamic current limit is set equal to or below the average current threshold. The dynamic current limit can be set equal to or below the average current threshold, for example, in response to an average current output being above the average current threshold for a period of time. At step606, the dynamic current limit can be increased according to a predetermined time constant and as an integral of the output current changes. The integral of the output current can be calculated using real time and/or historical output current values. For example, in some embodiments the integral can be calculated based on a summation of a difference between a current threshold and the output current, and the dynamic current limit can increase when the integral decreases. Additionally, the integral of the output current can be calculated using an analog or digital circuit, as discussed herein. At step608, the output current can be increased above the average current threshold as the dynamic current limit is increased or decreased. Eventually, and if needed to maintain a level of performance for the device performing method600, the output current will reach a maximum current limit for the device. At step610, the dynamic current limit can be set to the maximum current limit when the dynamic current limit reaches the maximum current limit.

FIG. 7illustrates a method700for controlling a decrease of electrical current based on an average current threshold. The method700can be performed by the power converter108, computing device102, a power management unit of the computing device102, or any other suitable device, component, apparatus, processor capable of regulating current. It should be noted that method700can be performed before or after method600. Furthermore, it should be noted that method600can be a continuation of method700and method700can be a continuation of method600. The method can include a step702of setting an output current that is above an average current threshold. At step704, a dynamic current limit is set equal to or greater than the output current. In this way, an amplitude of the output current will be limited to values that are equal to or less than the dynamic current limit. The dynamic current limit can be decreased, at step706, according to a predetermined time constant and when an integral of the output current changes. For example, in some embodiments, the integral can be calculated based on a summation of a difference between a current threshold and the output current, and the dynamic current limit can decrease when the integral increases. The predetermined time constant of method700can be the same or a different time constant than the predetermined time constant of method600. Additionally, the dynamic current limit can be decreased in order to maintain an average of the output current equal to or approximately equal to the average current threshold. At step708, the output current can be decreased in response to the dynamic current limit decreasing. When the dynamic current limit reaches the average current threshold, at step710, the dynamic current limit can be set equal to or below the average current threshold. In this way, the output current will be able to remain at or below the average current threshold without being limited by the dynamic current limit. However, if the output current starts to increase, method600can be performed in order to increase the dynamic current limit and the output current thereby allowing the output currents above the average current threshold to occur as need to improve performance of a device.

FIG. 8illustrates a plot800of an output current804being controlled by a power converter according to some embodiments discussed herein. Specifically, the plot800illustrates a dynamic current limit808associated with an integrator circuit of the power converter. The dynamic current limit808can scale with an integral of the output current804. However, in some embodiments, the dynamic current limit808can scale according to a difference between the output current804and a current threshold, as discussed herein. As illustrated in plot800, the output current804initially increases toward a maximum current limit802and eventually the output current804exceeds the dynamic current limit808. In response to the output current804exceeding the dynamic current limit808, the output current804will decrease at a rate based on a first time constant, as discussed herein. The output current804will decrease for a first period810until the output current804falls below the dynamic current limit808. Once the output current804is below the dynamic current limit808, the dynamic current limit808can begin to increase at rate that is based on a second time constant. At any point during operation of the power converter the output current804can be decreased if (i) the maximum current limit802is exceeded by the output current804(ii), the dynamic current limit808is exceeded by the output current804, or a voltage component of the output current804falls below a minimum voltage threshold, as discussed herein. Decreasing and increasing the output current804in this way will enforce an average current threshold806at the power converter, which in turn can extend the lifetime of the power converter while improving performance a device being supplied the output current804.

FIG. 9is a block diagram of a computing device900that can represent the components of the computing device and/or power converter discussed herein. It will be appreciated that the components, devices or elements illustrated in and described with respect toFIG. 9may not be mandatory and thus some may be omitted in certain embodiments. The computing device900can include a processor902that represents a microprocessor, a coprocessor, circuitry and/or a controller910for controlling the overall operation of computing device900. Although illustrated as a single processor, it can be appreciated that the processor902can include a plurality of processors. The plurality of processors can be in operative communication with each other and can be collectively configured to perform one or more functionalities of the computing device900as described herein. In some embodiments, the processor902can be configured to execute instructions that can be stored at the computing device900and/or that can be otherwise accessible to the processor902. As such, whether configured by hardware or by a combination of hardware and software, the processor902can be capable of performing operations and actions in accordance with embodiments described herein.

The computing device900can also include user input device904that allows a user of the computing device900to interact with the computing device900. For example, user input device904can take a variety of forms, such as a button, keypad, dial, touch screen, audio input interface, visual/image capture input interface, input in the form of sensor data, etc. Still further, the computing device900can include a display908(screen display) that can be controlled by processor902to display information to a user. Controller910can be used to interface with and control different equipment through equipment control bus912. The computing device900can also include a network/bus interface914that couples to data link916. Data link916can allow the computing device900to couple to a host computer or to accessory devices. The data link916can be provided over a wired connection or a wireless connection. In the case of a wireless connection, network/bus interface914can include a wireless transceiver.

The computing device900can also include a storage device918, which can have a single disk or a plurality of disks (e.g., hard drives) and a storage management module that manages one or more partitions (also referred to herein as “logical volumes”) within the storage device918. In some embodiments, the storage device918can include flash memory, semiconductor (solid state) memory or the like. Still further, the computing device900can include Read-Only Memory (ROM)920and Random Access Memory (RAM)922. The ROM920can store programs, code, instructions, utilities or processes to be executed in a non-volatile manner. The RAM922can provide volatile data storage, and store instructions related to components of the storage management module that are configured to carry out the various techniques described herein. The computing device900can further include data bus924. Data bus924can facilitate data and signal transfer between at least processor902, controller910, network/bus interface914, storage device918, ROM920, and RAM922.