Interposer and electronic device including the same

An example electronic device includes a housing, a first board and a second board disposed in an interior of the housing and disposed to face each other in a first direction, an interposer extending to surround an interior space between the first board and the second board, a first conductive layer disposed to face the first board and including a first conductive area, a second conductive layer disposed to face the second board and including a second conductive area, an insulation layer disposed between the first conductive layer and the second conductive layer, a first insulation part disposed between the first conductive layer and the first board and covering the first conductive area, a second insulation part disposed between the second conductive layer and the second board and covering the second conductive area, a first plating area extending from the first conductive layer to the second conductive layer, on a first side surface of the insulation layer, and a second plating area extending from the first conductive layer to the second conductive layer, on a second side surface of the insulation layer.

BACKGROUND

Field

The disclosure relates to an interposer and an electronic device including the same.

Description of Related Art

As more functions are provided in an electronic device, clock frequencies of electric elements become higher and data transmission speeds become higher. Due to the electric elements that are operated at high frequencies, electromagnetic interferences (EMIs) may occur. A malfunction of the electronic device may be caused by the electromagnetic interferences.

An electronic device may include two or more boards, on which the electric elements are mounted. The two or more boards may be disposed to overlap each other and the electronic device may include an interposer for electrically connecting the two or more boards.

The interposer may include a plurality of layers, and vias that pass through at least some of the plurality of layers. The interposer may include a plating area connected to a ground of the board for a shielding function. The plating area may include a conductive material (e.g., copper) and a metal (e.g., gold) that has a low reactivity for preventing corrosion of the conductive material. This may, for example, cause an increase in costs of a plating process.

SUMMARY

Embodiments of the disclosure provide an interposer that includes a large number of vias as compared with a conventional interposer, and in which an added via may be utilized as a signal via.

Embodiments of the disclosure provide an interposer that may stably maintain a side plating area without a plating process that uses relatively expensive gold.

An electronic device according to an example embodiment disclosed in the disclosure may include: a housing, a first board and a second board disposed in an interior of the housing and disposed to face each other in a first direction, an interposer extending to surround an interior space between the first board and the second board, a first conductive layer disposed to face the first board and including a first conductive area, a second conductive layer disposed to face the second board and including a second conductive area, an insulation layer disposed between the first conductive layer and the second conductive layer, a first insulation part disposed between the first conductive layer and the first board and covering the first conductive area, a second insulation part disposed between the second conductive layer and the second board and covering the second conductive area, a first plating area extending from the first conductive layer to the second conductive layer, on a first side surface of the insulation layer, a second plating area extending from the first conductive layer to the second conductive layer, on a second side surface of the insulation layer, a ground via including a first part passing through the first insulation part and connected to the first conductive area, and a second part passing through the second insulation part and connected to the second conductive area, wherein the first conductive area and the second conductive area are electrically connected to each other through the first plating area, and a signal via passing from the first insulation part to the second insulation part.

According to various example embodiments disclosed in the disclosure, corrosion of the plating area may be prevented because the interposer includes a plating area and an insulation part that covers the plurality of layers. Accordingly, costs for the plating process may be decreased. Furthermore, a larger number of signal vias may be provided through laser machining of the insulation part. In addition, the disclosure may provide various effects that are directly or indirectly recognized.

With regard to description of drawings, the same or similar components may be marked by the same or similar reference numerals.

DETAILED DESCRIPTION

Hereinafter, various example embodiments of the disclosure will be described in greater detail with reference to the accompanying drawings. Accordingly, those of ordinary skill in the art will recognize that modification, equivalent, and/or alternative on the various embodiments described herein can be variously made without departing from the scope and spirit of the disclosure.

FIG.1is a front perspective view of an example electronic device100according to an embodiment.FIG.2is a rear perspective view of the example electronic device100according to an embodiment.FIG.3is an exploded perspective view of the example electronic device100according to an embodiment.

Referring toFIGS.1and2, the electronic device100may include a housing110including a first surface (or a front surface)110A, a second surface (or a rear surface)110B, and a side surface110C that surrounds a space between the first surface110A and the second surface110B.

In another embodiment (not illustrated), the housing110may refer, for example, to a structure that defines some of the first surface110A, the second surface110B, and the side surface110C.

According to an embodiment, the first surface110A may be defined by a front plate102(e.g., a front plate120ofFIG.3), at least a portion of which is substantially transparent. In an embodiment, the front plate102, for example, may include a glass plate or a polymer plate including various coating layers. According to an embodiment, the second surface110B may be defined by a rear plate111(e.g., a rear plate180ofFIG.3), which is substantially opaque. The rear plate111, for example, may be formed of coated or colored glass, ceramics, a polymer, a metal (e.g., aluminum, stainless steel (STS), or magnesium), or a combination of at least two thereof. The side surface110C may be coupled to the front plate102and the rear plate111, and may be defined by a side bezel structure118including a metal and/or a polymer.

In another embodiment, the rear plate111and the side bezel structure118may be integrally formed and may include the same material (e.g., a metallic material such as aluminum).

In the illustrated embodiment, the front plate102may include two first areas110D that are deflected from a partial area of the first surface110A toward the rear plate111and extend seamlessly. The first areas110D may be respectively located at both ends of a long edge of the front plate102.

In the illustrated embodiment, the rear plate111may include two second areas110E that are deflected from a partial area of the second surface110B toward the front plate102and extend seamlessly. The second areas110E may be included at both ends of a long edge of the rear plate111respectively.

In another embodiment, the front plate102(or the rear plate111) may include only one of the first areas110D (or the second areas110E). Furthermore, in another embodiment, the front plate102(or the rear plate111) may not include some of the first areas110D (or the second areas110E).

In an embodiment, when viewed from a side of the electronic device100, the side bezel structure118may have a first thickness (width) on a lateral side (e.g., a short edge), on which neither the first areas110D nor the second areas110E are included, and may have a different second thickness that is smaller than the first thickness on a lateral side (e.g., a long edge), on which the first areas110D or the second areas110E are included.

In an embodiment, the electronic device100may include at least one of a display101, audio modules103,104, and107, a sensor module (not illustrated), camera modules105and112, a key input device117, a light emitting element (not illustrated), and a connector hole108. In another embodiment, at least one (e.g., the key input device117or the light emitting element (not illustrated)) of the elements may be omitted from the electronic device100and/or another component may be additionally included in the electronic device100.

In an embodiment, the display101may be exposed through at least a portion of the front plate102. For example, at least a portion of the display101may be exposed through the front plate102that defines the first surface110A, and the first areas110D of the side surface110C.

In an embodiment, a shape of the display101may have a shape that is substantially the same as the adjacent outer shape of the front plate102. In other embodiments (not illustrated), in order to expand the area to which the display101is exposed, when viewed from above the front plate102, the outer perimeter of the display101and the outer perimeter of the front plate102may formed to be substantially the same, but is not limited thereto.

In an embodiment, a surface (or the front plate102) of the housing110may include a screen display area, through which the display101is visually exposed and in which contents are displayed through pixels. For example, the screen display area may include the first surface110A, and the first areas110D of the side surface.

In another embodiment (not illustrated), the display areas110A and110D may include a sensing area (not illustrated) configured to acquire biometric information of a user. Here, the expression that “the display areas110A and110D include a sensing area” may be understood to refer, for example to at least a portion of the sensing area overlapping the display areas110A and110D. For example, the sensing area (not illustrated) may display contents on the display101like other areas of the screen display areas110A and110D, and additionally, may refer to an area that may acquire biometric information (e.g., a fingerprint) of the user.

In an embodiment, the display areas110A and110D of the display101may include a camera area106. For example, the camera area106may be an area, through which light reflected by a subject and received by the first camera module105passes. For example, the camera area106may be an area, through which an optical axis of the first camera module105passes. Here, the expression that “the display areas110A and110D include the camera area106” may be understood to refer, for example, to at least a portion of the camera area106overlapping the display areas110A and110D. For example, in the camera area106, contents may be displayed on the display101as in another area of the display areas110A and110D.

In various embodiments (not illustrated), the screen display areas110A and110D of the display101may include an area, in which the first camera module105(e.g., a punch hole camera) may be visually exposed. For example, at least a portion of an edge of the exposed area of the first camera module105may be surrounded by the screen display areas110A and110D. In an embodiment, the first camera module105may include a plurality of camera modules.

In an embodiment, at least one of the audio modules103,104, and107, the sensor modules (not illustrated), the camera module (e.g., the first camera module105), and the light emitting elements (not illustrated) may be included on the rear surfaces of the screen display areas110A and110D of the display101. For example, in the electronic device100, the camera module (e.g., the first camera module105) may be disposed on the first surface110A (e.g., the first surface) and/or a rear surface (e.g., a surface that faces the −X axis direction) of the side surface110C (e.g., at least one surface of the first area110D) to face the first surface110A and/or the side surface110C. For example, the first camera module105may not be visually exposed to the screen display areas110A and110D, and may include an under display camera (UDC).

In other embodiments (not illustrated), the display101may include or be disposed to be adjacent to a touch detection circuit, a pressure sensor that may measure the strength (the pressure) of a touch, and/or a digitizer that detects a stylus pen of a magnetic field type.

According to an embodiment, the audio modules103,104, and107may include the microphone holes103and104and the speaker hole107.

In an embodiment, the microphone holes103and104may include the first microphone hole103formed in a partial area of the side surface110C, and the second microphone hole104formed in a partial area of the second surface110B. Microphones for obtaining external sound may be disposed in interiors of the housing110. The microphones may include a plurality of microphones to sense a direction of sound. In an embodiment, the second microphone hole104formed in a partial area of the second surface110B may be disposed to be adjacent to the camera modules105and112. For example, the second microphone hole104may acquire sound during use of the camera modules105and112or may acquire sound during use of another function.

In an embodiment, the speaker hole107may include a call receiver hole (not illustrated). The speaker hole107may be formed at a portion of the side surface110C of the electronic device100. In another embodiment, the speaker hole107and the microphone hole103may be implemented with one hole. Although not illustrated, the call receiver hole (not illustrated) may be formed at another portion of the side surface110C. For example, the call receiver hole (not illustrated) may be formed at a portion (e.g., a portion that faces the +Y axis direction) of the side surface110C, which faces a portion (e.g., a portion that faces the −Y axis direction) of the side surface110C, at which the speaker hole107is formed.

In an embodiment, the electronic device100may include a speaker fluid-communicated with the speaker hole107. In another embodiment, the speaker may include a piezoelectric speaker, from which the speaker hole107is omitted.

In an embodiment, the sensor module (not illustrated) may generate an electrical signal or a data value corresponding to an operation state of the interior of the electronic device100or an environmental state of the outside. In an embodiment, the sensor module (not illustrated) may be disposed at at least a portion of the first surface110A, the second surface110B, and the side surface110C (e.g., the first areas110D and/or the second areas110E) of the housing110, and may be disposed (e.g., a fingerprint sensor) on the rear surface of the display101. For example, at least a portion of the sensor module (not illustrated) may be disposed under the display areas110A and110D not to be visually exposed, and a sensing area (not illustrated) may be formed at at least a portion of the display areas110A and110D. For example, the sensor module (not illustrated) may include an optical fingerprint sensor. In some embodiments (not illustrated), the fingerprint sensor may be disposed not only on the first surface110A (e.g., the screen display areas110A and110D) but also on the second surface110B of the housing110. For example, the sensor module may include at least one of a proximity sensor, an HRM sensor, a fingerprint sensor, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, and an illumination sensor.

In an embodiment, the key input device117may be disposed in the side surface110C (e.g., the first areas110D and/or the second areas110E) of the housing110. In another embodiment, the electronic device100may not include some or all of the above-mentioned key input devices117and the key input devices117, which are not included, may be realized in different forms, such as a soft key, on the display101. In another embodiment, the key input device may include a sensor module (not illustrated) that defines a sensing area (not illustrated) included in the display areas110A and110D.

In an embodiment, the connector hole108may accommodate connectors. The connector hole108may be disposed on the side surface110C of the housing110. For example, the connector hole108may be disposed on the side surface110C to be adjacent to at least a portion of the audio modules (e.g., the microphone hole103and the speaker hole107). In another embodiment, the electronic device100may include the first connector hole108that may accommodate a connector (e.g., a USB connector) for transmitting and receiving electric power and/or data to and from an external electronic device and/or a second connector hole (not illustrated) that may accommodate a connector (e.g., an earphone jack) for transmitting and receiving an audio signal to and from the external device.

In an embodiment, the electronic device100may include a light emitting element (not illustrated). For example, the light emitting element (not illustrated) may be disposed on the first surface110A of the housing110. The light emitting element (not illustrated) may provide state information on the electronic device100in the form of light. In another embodiment, the light emitting element (not illustrated) may provide a light source that interworks with an operation of the first camera module105. For example, the light emitting element (not illustrated) may include an LED, an IR LED, and/or a xenon lamp.

In an embodiment, the camera modules105and112may include the first camera module105(e.g., an under display camera) that receives light through the camera area106of the first surface110A of the electronic device100, the second camera module112that receives light through a partial area (e.g., a rear camera area184ofFIG.3) of the second surface110B, and a flash113.

In an embodiment, the first camera module105may include an under display camera (UCD) disposed on a rear surface of the display101. For example, the first camera module105may be located in some layers of the display101, or may be located such that an optical axis of a lens passes through the display areas110A and110D. In various embodiments, the first camera module105may be configured to receive light though the camera area106included in the display areas110A and110D. For example, the camera area106may be configured to display contents like other areas of the display areas110A and110D when the first camera module105is not operated. For example, when the first camera module105is operated, the camera area106does not display contents and the first camera module105may receive light through the camera area106.

In various embodiments (not illustrated), the first camera module105(e.g., a punch hole camera) may be exposed through a portion of the display areas110A and110D of the display101. For example, the first camera module105may be exposed through a partial area of the screen display areas110A and110D through an opening formed at a portion of the display101.

In an embodiment, the second camera module112may include a plurality of camera modules (e.g., a dual camera, a triple camera, or a quad camera). However, the second camera module112is not limited to including a plurality of camera modules, and may include one camera module.

In an embodiment, the first camera module105and/or the second camera module112may include one or a plurality of lenses, an image sensor, and/or an image signal processor. The flash113, for example, may include a light emitting diode or a xenon lamp. In another embodiment, two or more lenses (an infrared ray camera, and a wide angle/telephoto lens), and image sensors may be disposed in an interior of the housing to face a direction, which one surface (e.g., the second surface110B) of the electronic device100faces.

Referring toFIG.3, the electronic device100may include the side bezel structure118, a first support member140(e.g., the bracket), the front plate120(e.g., the front plate102ofFIG.1), a display130(e.g., the display101ofFIG.2), a printed circuit board150(e.g., a printed circuit board (PCB), a flexible PCB (FPCB), or a rigid-flexible PCB (RFPCB)), a battery152, a second support member160(e.g., the rear case), an antenna170, and/or the rear plate180(e.g., the rear plate111ofFIG.2). In some embodiments, at least one (e.g., the first support member140or the second support member160) of the elements may be omitted from the electronic device100and/or another component may be additionally included in the electronic device100. At least one of the components of the electronic device100may be the same as or similar to at least one of the components of the electronic device100ofFIGS.1and2, and the description will not be repeated here.

In an embodiment, the first support member140may be disposed in the interior of the electronic device100to be connected to the side bezel structure118or to be integrally formed with the side bezel structure118. The first support member140, for example, may be formed of a metal material and/or a nonmetal material (e.g., a polymer). The display130may be coupled to or located on one surface of the first support member140, and the printed circuit board150may be coupled to or located on an opposite surface of the first support member140.

In an embodiment, a processor, a memory, and/or an interface may be mounted on the printed circuit board150. The processor, for example, may include one or more of a central processing unit, an application processor, a graphic processing unit, an image signal processor, a sensor hub processor, or a communication processor.

In an embodiment, the memory, for example, may include a volatile and/or nonvolatile memory.

In an embodiment, the interface, for example, may include a high definition multimedia interface (HDMI), a universal serial bus (USB), an SD card interface, and/or an audio interface. The interface, for example, may electrically or physically connect the electronic device100to an external electronic device, and may include a USB connector, an SD card/MMC connector, and an audio connector.

According to an embodiment, the battery152is a device for supplying electric power to at least one component of the electronic device100, and for example, may include a primary battery that cannot be recharged, a secondary battery that may be recharged, or a fuel cell. At least a portion of the battery152, for example, may be disposed on substantially the same plane as the printed circuit board150. The battery152may be integrally disposed in the interior of the electronic device100, and may be disposed to be detachable from the electronic device100.

According to an embodiment, the antenna170may be disposed between the rear plate180and the battery152. The antenna170, for example, may include a near field communication (NFC) antenna, a wireless charging antenna, and/or a magnetic secure transmission (MST) antenna. The antenna170, for example, may perform short-range communication with an external device, or may wirelessly transmit and receive electric power that is necessary for charging. In another embodiment, an antenna structure may be formed by one or a combination of the side bezel structure118and/or the first support member140.

In an embodiment, the first camera module105may be coupled to the rear surface of the display130to receive light through the camera area106of the front plate120. For example, at least a portion of the first camera module105may be disposed in the first support member140. For example, an image sensor of the first camera module105may receive light that passes through the camera area106, and a pixel array included in the display130. For example, the camera area106may at least partially overlap the display area, on which contents are displayed. For example, an optical axis OA the first camera module105may pass through a partial area of the display130and the camera area106of the front plate120. For example, the partial area may include a pixel array including a plurality of light emitting elements. In an embodiment, a partial area of the display130, which faces the first camera module105, may be a portion of the display area, on which the contents are displayed, and may be a transmission area having a specific transmittivity. In an embodiment, the transmission area may be formed to have a transmittivity ranging from about 5% to about 25%. In an embodiment, the transmission area may be formed to have a transmittivity ranging from about 25% to about 50%. In an embodiment, the transmission area may be formed to have a transmittivity of about 50% or more. The transmission area may include an area that overlaps an effective area (e.g., a field of view (FOV)) of the first camera module105, through which light for generating an image by forming the image with an image sensor. For example, the transmission area of the display130may include an area having a low density and/or a low wiring density of pixels.

In an embodiment, the second camera module112may be disposed such that the lens is exposed through the rear camera area184of the rear plate180(or the rear surface110B ofFIG.2) of the electronic device100. The rear camera area184may be formed at at least a portion of a surface (e.g., the rear surface110B ofFIG.2) of the rear plate180. In an embodiment, the rear camera area184may be formed to be at least partially transparent such that the second camera module112receives external light through the rear camera area184. In an embodiment, at least a portion of the rear camera area184may protrude from the surface of the rear plate180by a specific height. However, the disclosure is not limited thereto, and the rear camera area184may define a plane that is substantially the same as the surface of the rear plate180.

FIG.4is a view illustrating an electronic device according to an embodiment.

Referring toFIG.4, the electronic device100may include an interposer200(e.g., a shielding member) that electrically connects the first board150(e.g., the printed circuit board150ofFIG.3) and the second board190. In an embodiment, the interposer200may define a shielding space203that may shield noise generated between the first board150and the second board190or introduced from an outside. In an embodiment, the interposer200may be provided in various shapes. For example, the interposer200may be provided in a polygonal shape. The interposer200may be provided in a ring shape that surrounds the shielding space203. The shielding space203may include a partial area of the first board150and a partial area of the second board190. A shape of the interposer200disclosed in the disclosure is not limited to those illustrated in the drawings.

In an embodiment, the first board150(e.g., the printed circuit board150ofFIG.3) may include one or more electric elements152and154, a signal line that electrically connects the electric elements152and154, and a ground. In an embodiment, the one or more electric elements152and154may include the first electric element152located in an interior of the shielding space203and the second electric element154located on an outside of (external to) the shielding space203. In an embodiment, the first board150may include a first upper surface1501that faces a second lower surface1902of the second board190, and a first lower surface1502that is opposite to the first upper surface1501. Referring to the drawings, a partial area of the first upper surface1501of the first board150may be included in the shielding space203. The first electric element152and the second electric element154may be disposed on the first upper surface1501.

In an embodiment, the second board190may be located in a first direction from the first board150. For example, the second board190may be disposed above the first upper surface1501of the first board150or may be disposed below the first lower surface1502of the first board150. A location of the second board190may differ according to a kind and/or a function of a third electric element192mounted on the second board190. The third electric element192may be located in an interior of the shielding space203. Referring to the drawings, the third electric element192may be disposed on the second lower surface1902of the second board190. The second board190may include the second lower surface1902that faces the first upper surface1501of the first board150, and a second upper surface1901that is opposite to the second lower surface1902. Referring to the drawings, at least a partial area of the second lower surface1902of the second board190may be included in the shielding space203.

In an embodiment, the interposer200may extend to surround the shielding space203defined between the first board150and the second board190. For example, the interposer200may include a first surface201that at least partially contacts the first upper surface1501of the first board150, a second surface202that at least partially contacts the second lower surface1902of the second board190, and a side surface204that surrounds a space between the first surface201and the second surface202.

In various embodiments, the second board190may have various sizes. For example, the second board190may have the same size as that of the first board150, may have a size that is smaller than that of the first board150, or may have a size that is larger than that of the first board150. The second board190may have a shape corresponding to the shape of the interposer200. The shapes of the first board150and the second board190illustrated in the drawings are merely examples, and the boards may have various shapes.

In an embodiment, each of the first electric element152, the second electric element154, and the third electric element192may include an integrated circuit, an active element, or a passive element. For example, the first electric element152and the third electric element192disposed in an interior of the shielding space may include an electric element that requires shielding due to a high noise vulnerability as compared with the second electric element154or generates much noise.

According to an embodiment, because some electric elements are disposed in the second board190, the interior space of the electronic device100may be efficiently utilized. According to an embodiment, the interposer200may not require a separate shield can in an aspect that the interposer200performs a shielding function, in addition to the electrical connection of the first board150and the second board190.

FIG.5is a view illustrating an interposer of an example electronic device according to an embodiment.

Referring toFIG.5, the interposer200may include an insulation part including an insulation material. For example, the insulation material may include a preimpregnated material (PREPREG) (PPG) (e.g., an insulation resin). The insulation part may define at least a portion of an external appearance of the interposer200. For example, the insulation part may be provided through a PPG filling process.

In an embodiment, the insulation part may include a first insulation part240that defines the first surface201of the interposer200, a second insulation part250that defines the second surface202of the interposer200, a first side insulation part260that defines an outer surface204a, and a second side insulation part270that defines an inner surface204b.

In an embodiment, conductive pads (not illustrated inFIG.5) (e.g., a first conductive pad241and a second conductive pad242ofFIGS.8and9) electrically connected to the first board150may be disposed in the first insulation part240. For example, when the first surface201of the interposer200is viewed from the top, it may correspond to the first insulation part240except for the conductive pads

In an embodiment, conductive pads (not illustrated inFIG.5) (e.g., a third conductive pad251and a fourth conductive pad252ofFIGS.8and9) electrically connected to the second board190may be disposed on the second insulation part250. For example, when the second surface202of the interposer200is viewed from the top, it may correspond to the second insulation part250except for the conductive pads.

In an embodiment, the interposer200may extend in a closed form to surround the shielding space203. An extension direction “E” of the interposer200may be a direction that is substantially perpendicular to the Z axis direction. The interposer200may include a linear section that extends substantially in a straight line, and/or a curved section that extends in a curved line.

FIG.6is a cross-sectional view illustrating a layer structure of an interposer and an insulation part according to an embodiment.FIG.6is a cross-sectional view illustrating a cross-section that is perpendicular to the extension direction “E”.

In an embodiment, the interposer200may include a layer structure, and an insulation part that surrounds the layer structure. In an embodiment, the layer structure may include a plurality of layers that are laminated in a first direction. For example, the layer structure may include a first conductive layer220, an insulation layer210, and a second conductive layer230.

In an embodiment, the first conductive layer220may be disposed on a first surface (e.g., a surface in the −Z axis direction) of the insulation layer210. The first conductive layer220may be covered by the first insulation part240. The first conductive layer220may be disposed to face the first board150. For example, the first insulation part240may be disposed between the first conductive layer220and the first board150.

In an embodiment, the second conductive layer230may be disposed on a second surface (e.g., a surface in the Z axis direction) of the insulation layer210. The second conductive layer230may be covered by the second insulation part250. The second conductive layer230may be disposed to face the second board190. For example, the second insulation part250may be disposed between the second conductive layer230and the second board190.

In an embodiment, the insulation layer210may be disposed between the first conductive layer220and the second conductive layer230. A first plating area211may be formed on a first side surface210aof the insulation layer210, and a second plating area212may be formed on a second side surface210b. The first plating area211may be covered by the first side insulation part260, and the second plating area212may be covered by the second side insulation part270. The first plating area211may extend from the first conductive layer220to the second conductive layer230along the first side surface210aof the insulation layer. The second plating area212may extend from the first conductive layer220to the second conductive layer230along the second side surface210bof the insulation layer. In various embodiments, a plurality of via holes (e.g., a fifth part293of the signal via Vs ofFIGS.8and9) may be formed in the insulation layer210. In an embodiment, the insulation layer210may be formed of various materials. For example, the insulation layer210may include at least one of polyimide, polyester, or polytetrafluoroethylene.

In an embodiment, the first insulation part240may be disposed between the first conductive layer220and the first board150. The first insulation part240may, for example, be integrally formed with the first side insulation part260and the second side insulation part270. In various embodiments, the conductive pads (e.g., the first conductive pad241and the second conductive pad242ofFIGS.8and9) may be formed on a surface of the first insulation part240. A plurality of via holes (e.g., a first part281and a third part291ofFIGS.8and9) that pass through the first insulation part240may be formed in the first insulation part240.

In an embodiment, the second insulation part250may be disposed between the second conductive layer230and the second board190. The second insulation part250may, for example, be integrally formed with the first side insulation part260and the second side insulation part270. In various embodiments, the conductive pads (e.g., the third conductive pad251and the fourth conductive pad252ofFIGS.8and9) may be formed on a surface of the second insulation part250. A plurality of via holes (e.g., a second part282and a fourth part292ofFIGS.8and9) that pass through the second insulation part250may be formed in the second insulation part250.

In an embodiment, the first side insulation part260may cover the first plating area211. For example, the first side insulation part260may define an outer surface (e.g., the outer surface204aofFIG.5) of the interposer200. The first side insulation part260may, for example, be integrally formed with the first insulation part240and the second insulation part250.

In an embodiment, the second side insulation part270may cover the second plating area212. For example, the second side insulation part270may define an inner surface (e.g., the inner surface204bofFIG.5) of the interposer200. The second side insulation part270may be integrally formed with the first insulation part240and the second insulation part250.

In an embodiment, the first plating area211may be disposed substantially in parallel to the outer surface of the interposer200. The first plating area211may be connected to grounds of the first board150and the second board190to provide a shielding performance for the outer surface of the interposer200. Because the first side insulation part260covers the first plating area211, the first plating area211may be prevented from being oxidized.

In an embodiment, the second plating area212may be disposed substantially in parallel to the inner surface of the interposer200. The second plating area212may be connected to grounds of the first board150and the second board190to provide a shielding performance for the inner surface of the interposer200. Because the second side insulation part270covers the second plating area212, the second plating area212may be prevented from being oxidized.

FIG.7is a plan view of an example interposer according to an embodiment.FIG.7is a view of a first surface of the interposer, viewed from the top, according to an embodiment.

Hereinafter, the contents on the first surface201, the first conductive pad241, the second conductive pad242, and the first insulation part240may be applied to the second surface202, the third conductive pad (e.g., the third conductive pad251ofFIGS.8and9), the fourth conductive pad (e.g., the fourth conductive pad252ofFIGS.8and9), and the second insulation part (e.g., the second insulation part250ofFIGS.8and9) in substantially the same manner.

In an embodiment, the first conductive pad241and the second conductive pad242may be exposed from the first surface201of the interposer200. The first conductive pad241and the second conductive pad242may be electrically connected to the first board (e.g., the first board150ofFIG.6). For example, the first conductive pad241and the second conductive pad242may be surface-mounted on the first board150.

In an embodiment, the first conductive pad241may include a ground path. For example, the first conductive pad241may be connected to the ground via (e.g., a ground via Vg ofFIGS.8and9) that passes through at least a portion of the interposer200, and the ground of the first board150.

In an embodiment, the first conductive pad241may be surrounded by the first insulation part240. The first conductive pad241may contact a ground pad of the first board150. A plurality of first conductive pads241may be formed. For example, when viewed in the extension direction “E”, some of the second conductive pads242may be disposed between the first conductive pads241that are adjacent to each other.

In an embodiment, the first conductive pad241may be disposed to be adjacent to the inner surface204bor the outer surface204aof the interposer200. For example, the first conductive pad241may be disposed to be adjacent to the first plating area211or the second plating area212located in an interior of the interposer200.

In an embodiment, the second conductive pad242may be included in a signal transmission path. For example, the second conductive pad242may be connected to the signal via (e.g., the signal via Vs ofFIGS.8and9) that passes through at least a portion of the interposer200, and the signal line of the first board150.

In an embodiment, the second conductive pad242may be surrounded by the first insulation part240. The second conductive pad242may contact a signal pad of the first board150. A plurality of second conductive pads242may be formed. When viewed in the extension direction, some of the second conductive pads242may be disposed between the first conductive pads241.

In an embodiment, the first plating area211and the second plating area212may extend substantially in parallel to each other. The first plating area211and the second plating area212may extend along the extension direction “E” of the interposer200to surround the shielding space (e.g., the shielding space203ofFIG.5).

In an embodiment, the first conductive pad241and the second conductive pad242may be arranged in the extension direction “E” of the interposer while forming three columns. For example, when viewed in a direction that is perpendicular to the extension direction “E”, at least three first conductive pads241and/or at least three second conductive pads242may be disposed to at least partially overlap each other.

In an embodiment, the interposer200may include a first area “A”, a second area “B”, and a third area “C” defined along the extension direction “E”. For example, the first area “A” may include only the first conductive pad241. For example, each of the second area “B” and the third area “C” may include the first conductive pad241and the second conductive pad242. For example, the first conductive pad241included in the second area “B” may be disposed to be adjacent to the first plating area211or the outer surface204a. For example, the first conductive pad241included in the third area “C” may be disposed to be adjacent to the second plating area212or the inner surface204b. Referring to the drawings, the second area “B” and the third area “C” may be disposed between two first areas “A”. Referring to the drawings, the second area “B” and the third area “C” may be disposed alternately when viewed in the extension direction “E”. That is, the first conductive pad241may be disposed in zigzags when viewed in the extension direction “E”.

FIG.8is a cross-sectional view illustrating an interposer of an example electronic device according to an embodiment. For example,FIG.8is a cross-sectional view of the second area “B” ofFIG.7.

FIG.9is a cross-sectional view illustrating an interposer of an example electronic device according to an embodiment. For example,FIG.9is a cross-sectional view of the third area “C” ofFIG.7.

In an embodiment, the first conductive pad241and the second conductive pad242may be formed on a surface of the first insulation part240. For example, each of the first conductive pad241and the second conductive pad242may be electrically connected to the first board150. An insulation material may be disposed between the first conductive pad241and the second conductive pad242. For example, the first conductive pad241and the second conductive pad242may be surrounded by a coating layer disposed on the surface of the first insulation part240.

In various embodiments, the first insulation part240may be provided as a layer that is substantially parallel to the insulation layer210. For example, a thickness of the first insulation part240may be approximately 100 micrometers. For example, a thickness of the coating layer disposed on the surface of the first insulation part240may be approximately 20 micrometers. In various embodiments, a thickness of the insulation layer210may be approximately 435 micrometers.

In various embodiments, the first conductive pad241and the second conductive pad242may have a size (e.g., a diameter) of approximately 300 micrometers. Furthermore, the conductive pads241and242may be disposed at an interval of approximately 300 micrometers from other adjacent conductive pads. However, the numbers mentioned in the disclosure are merely examples, and the disclosure is not limited to these numbers.

In an embodiment, the third conductive pad251and the fourth conductive pad252may be formed on a surface of the second insulation part250. For example, each of the third conductive pad251and the fourth conductive pad252may be electrically connected to the second board190. An insulation material may be disposed between the third conductive pad251and the fourth conductive pad252. For example, the third conductive pad251and the fourth conductive pad252may be surrounded by a coating layer disposed on the surface of the second insulation part250. In various embodiments, the second insulation part250may be provided as a layer that is substantially parallel to the insulation layer210. For example, a thickness of the second insulation part250may be about 100 micrometers. For example, a thickness of the coating layer disposed on the surface of the second insulation part250may be about 20 micrometers. In various embodiments, a thickness of the insulation layer210may be about 435 micrometers.

In various embodiments, the third conductive pad251and the fourth conductive pad252may have a size (e.g., a diameter) of about 300 micrometers. Furthermore, the conductive pads251and252may be disposed at an interval of approximately 300 micrometers from other adjacent conductive pads. However, the numbers mentioned in the disclosure are merely examples, and the disclosure is not limited to these numbers.

In an embodiment, the first conductive layer220may include a first conductive area221and a second conductive area222. The first conductive area221and the second conductive area222may be electrically insulated from each other. The first insulation part240may be disposed between the first conductive area221and the second conductive area222. In an embodiment, the first conductive area221may be formed on a first surface of the insulation layer210. The first conductive area221may extend to the first plating area211formed on the first side surface (e.g., the first side surface210aofFIG.6) of the insulation layer210. In an embodiment, the second conductive area222may be formed on the first surface of the insulation layer210. For example, the first conductive area221and the first conductive pad241may at least partially overlap each other when viewed in the first direction. Here, the first direction may be defined as the Z axis direction. Furthermore, the first direction may be defined as a direction that faces the second board (e.g., the second board190ofFIG.6) from the first board (e.g., the first board150ofFIG.6). The first direction may be a direction that is substantially perpendicular to the extension direction “E” of the interposer200. For example, the second conductive area222and the second conductive pad242may at least partially overlap each other when viewed in the first direction.

In various embodiments, a thickness of the first conductive layer220may be approximately 35 micrometers. For example, thicknesses of the first conductive area221and the second conductive area222may be approximately 35 micrometers. In various embodiments, the first conductive area221and the second conductive area222may have a size (e.g., a diameter) of approximately 400 micrometers. The conductive areas221and222may be spaced apart from the adjacent conductive areas by approximately 250 micrometers or less. In various embodiments, the second conductive area222may be spaced apart from the first plating area211by approximately 700 micrometers. In various embodiments, the second plating area212may be spaced apart from the first plating area211by approximately 2 millimeters. In various embodiments, a thickness of the interposer200may be approximately 780 micrometers. Through the spacing distances, short-circuits between the pads and the conductive areas may be reduced and/or prevented. However, the numbers mentioned in the disclosure are merely examples, and the disclosure is not limited to these numbers.

In an embodiment, the second conductive layer230may include a third conductive area231and a fourth conductive area232. The third conductive area231and the fourth conductive area232may be electrically insulated from each other. The second insulation part250may be disposed between the third conductive area231and the fourth conductive area232. In an embodiment, the third conductive area231may be formed on the second surface of the insulation layer210. The third conductive area231may extend to the first plating area211formed on the first side surface (e.g., the first side surface210aofFIG.6) of the insulation layer210. In an embodiment, the fourth conductive area232may be formed on the second surface of the insulation layer210. For example, the third conductive area231and the third conductive pad251may at least partially overlap each other when viewed in the first direction. For example, the fourth conductive area232and the fourth conductive pad252may at least partially overlap each other when viewed in the first direction.

In various embodiments, a thickness of the second conductive layer230may be approximately 35 micrometers. For example, thicknesses of the third conductive area231and the fourth conductive area232may be approximately 35 micrometers.

In various embodiments, the third conductive area231and the fourth conductive area232may have a size (e.g., a diameter) of approximately 400 micrometers. The conductive areas231and232may be spaced apart from the adjacent conductive areas by approximately 250 micrometers or less. In various embodiments, the fourth conductive area232may be spaced apart from the first plating area211by approximately 700 micrometers. In various embodiments, the second plating area212may be spaced apart from the first plating area211by approximately 2 millimeters. In various embodiments, a thickness of the interposer200may be approximately 780 micrometers. Through the spacing distances, short-circuits between the pads and the conductive areas may be reduced and/or prevented. However, the numbers mentioned in the disclosure are merely examples, and the disclosure is not limited to these numbers.

In an embodiment, the interposer200may include a plurality of conductive vias for providing an electrical connection of the first board150and the second board190. The plurality of conductive vias may be defined according to applied signals. For example, the plurality of conductive vias may include the ground via Vg connected to the grounds of the first board150and the second board190, and a signal via Vs connected to signal lines of the first board150and the second board190.

In an embodiment, the ground via Vg may include a first part281that passes through the first insulation part240, and a second part282that passes through the second insulation part250. For example, the first part281may include a first via hole281hthat passes through the first insulation part240, and a conductive material filled in the first via hole281h. The first part281may electrically connect the first conductive pad241and the first conductive area221. For example, the second part282may include a second via hole282hthat passes through the second insulation part250, and a conductive material filled in the second via hole282h. The second part282may electrically connect the third conductive pad251and the third conductive area231.

In an embodiment, the first conductive area221and the third conductive area231may be electrically connected to each other by the first plating area211. Accordingly, the interposer200may provide a ground path including the first part281, the second part282, the first conductive area221, the third conductive area231, and the first plating area211of the ground via Vg. The first conductive pad241may be coupled to the ground pad of the first board150. For example, the first conductive pad241may be surface-mounted on the ground pad of the first board150. The third conductive pad251may be coupled to the ground pad of the second board190. For example, the third conductive pad251may be surface-mounted on the ground pad of the second board190. When viewed in a cross-section, the ground path may have a “C” shape that at least partially surrounds the insulation layer210.

In an embodiment, the first part281may be configured such that a cross-sectional area thereof decreases as it becomes closer to the insulation layer210. The cross-sectional area may refer, for example, to an area when the first part281is viewed in a cross-section that is perpendicular to the first direction (e.g., the Z axis direction). For example, a cross-sectional area of a portion of the first part281, which is adjacent to the first conductive area221, may be smaller than a cross-sectional area of a portion of the first part281, which is adjacent to the first conductive pad241. In an embodiment, the first part281may have a cross-sectional area that is smaller than that of the first conductive pad241. In an embodiment, the first part281may be formed by machining a laser hole in the first insulation part240.

In an embodiment, the second part282may be configured such that a cross-sectional area thereof decreases as it becomes closer to the insulation layer210. The cross-sectional area may refer, for example, to an area of the second part282when viewed in a cross-section that is perpendicular to the first direction. For example, a cross-sectional area of a portion of the second part282, which is adjacent to the third conductive area231, may be smaller than a cross-sectional area of a portion of the second part282, which is adjacent to the third conductive pad251. In an embodiment, the second part282may have a cross-sectional area that is smaller than that of the third conductive pad251. In an embodiment, the second part282may be formed by machining a laser hole in the second insulation part250.

In an embodiment, the signal via Vs may include the third part291that passes through the first insulation part240, the fourth part292that passes through the second insulation part250, and the fifth part293that passes through the insulation layer210.

In an embodiment, the third part291may include a third via hole291hthat passes through the first insulation part240, and a conductive material filled in the third via hole291h. The third part291may electrically connect the second conductive pad242and the second conductive area222.

In an embodiment, the fourth part292may include a fourth via hole292hthat passes through the second insulation part250, and a conductive material filled in the fourth via hole292h. The fourth part292may electrically connect the fourth conductive pad252and the fourth conductive area232.

In an embodiment, the fifth part293may electrically connect the third part291and the fourth part292. The fifth part293may include a fifth via hole293hthat passes through the insulation layer210, and a conductive material2931that is plated on an inner wall of the fifth via hole293hand a peripheral area of the fifth via hole293h. For example, the conductive material2931plated on the peripheral area of the fifth via hole293hmay form the second conductive area222and the fourth conductive area232. In an embodiment, the fifth part293may further include an insulation material2932located in an interior of the fifth via hole293h. The insulation material2932may be filled in the fifth via hole293hto firmly maintain the conductive material2931plated on an inner wall of the fifth via hole293h. In an embodiment, the conductive material2931may include at least one of copper, silver paste, aluminum, silver-aluminum, carbon paste, or carbon nanotube paste, but the disclosure is not limited thereto.

In an embodiment, the interposer200may provide a signal transmission path including the second conductive pad242, the third part291, the second conductive area222, the fifth part293, the fourth conductive area232, the fourth part292, and the fourth conductive pad252. For example, the signal transmission path may transmit signals between the first board150and the second board190. For example, the second conductive pad242may at least partially contact a signal pad of the first board150. The second conductive pad242may be surface-mounted on the first board150. For example, the fourth conductive pad252may at least partially contact a signal pad of the second board190. The fourth conductive pad252may be surface-mounted on the second board190.

In an embodiment, the third part291may be configured such that a cross-sectional area thereof decreases as it becomes closer to the insulation layer210. The cross-sectional area may refer, for example, to an area of the second part282when viewed in a cross-section that is perpendicular to the first direction. For example, a cross-sectional area of a portion of the third part291, which is adjacent to the second conductive area222, may be smaller than a cross-sectional area of a portion of the third part291, which is adjacent to the second conductive pad242. In an embodiment, the third part291may have a cross-sectional area that is smaller than that of the second conductive pad242. In an embodiment, the third part291may be formed by machining a laser hole in the first insulation part240.

In an embodiment, the fourth part292may be configured such that a cross-sectional area thereof decreases as it becomes closer to the insulation layer210. The cross-sectional area may refer, for example, to an area of the second part282when viewed in a cross-section that is perpendicular to the first direction. For example, a cross-sectional area of a portion of the fourth part292, which is adjacent to the fourth conductive area232, may be smaller than a cross-sectional area of a portion of the fourth part292, which is adjacent to the fourth conductive pad252. In an embodiment, the fourth part292may have a cross-sectional area that is smaller than that of the fourth conductive pad252. In an embodiment, the fourth part292may be formed by machining a laser hole in the second insulation part250.

In an embodiment, the fifth part293may have a cross-sectional area that is relatively uniform as compared with that of the third part291or the fourth part292. The cross-sectional area may refer, for example, to an area when viewed in a cross-section that is perpendicular to the first direction.

In an embodiment, a cross-sectional area of the fifth part293may be larger than a cross-sectional area of the third part291or the fourth part292. For example, the fifth part293may be formed through machining (e.g., drilling or sawing) of the insulation layer210, and the third part291or the fourth part292may be formed through laser hole forming of the insulation parts240and250.

In an embodiment, a center axis of the fifth part293may be biased (offset) from a center axis of the third part291or the fourth part292by a specific distance. This may be understood that at least two different processes are performed to form the signal via. For example, portions of the signal via may have center axes that are parallel to each other but do not coincide with each other.

According to an embodiment, machining methods for the first to fifth parts281to293may be variously used. For example, the ground via Vg and the signal via Vs may be implemented by a plated through hole, a laser via hole, a buried via hole, or a stacked via.

In an embodiment, the conductive pads (e.g., the first conductive pad241, the second conductive pad242, the third conductive pad251, or the fourth conductive pad252) may be electrically connected to the boards (e.g., the first board150or the second board190) through a joining member such as pre-solder. For example, the pre-solder may fasten the conductive pads and the pads (e.g., the ground pad or the signal pad) of the board, through a reflow process, when the first board150and the second board190are coupled to the interposer200. According to an embodiment, a reflow process is a process of supplying solder to a land (e.g., the pad) of the board in advance and fusing the solder with an external heat source for connection, and may include a soldering process for soldering the land to the board. In some embodiments, the soldering process is not limited to the reflow soldering, but various methods such as flow soldering in addition to the reflow soldering may be used.

FIG.10is a view illustrating an example of a method for manufacturing an interposer of an electronic device according to an embodiment.

Referring toFIG.10, a method1000for manufacturing the interposer200may include forming first via holes310in the layer structure including the insulation layer210, the first conductive layer220, and the second conductive layer230, plating the inner walls of the first via holes310, forming the conductive areas221,222,231, and232in the first conductive layer220and the second conductive layer230, filling an insulation material320, and forming the vias330(e.g., the first part281, the second part282, the third part291, the fourth part292), and the conductive pads241,242,251, and252.

For example, the layer structure may include the first conductive layer220, the second conductive layer230, and the insulation layer210formed between the first conductive layer220and the second conductive layer230. For example, the first via hole310may be formed through a mechanical process such as a drilling process. The first via holes310may pass through the first conductive layer220, the second conductive layer230, and the insulation layer210. The first via holes310may pass in a direction (e.g., the Z axis direction) that is perpendicular to the first conductive layer220, the second conductive layer230, and the insulation layer210.

In an embodiment, a conductive material311(e.g., the conductive material2931ofFIG.8orFIG.9) may be located on the inner wall of the first via hole310through a plating process. The conductive material311may include copper. The conductive material311may not include gold. In various embodiments, the conductive material311may form the conductive material2931located in the side plating areas211and212illustrated inFIG.8orFIG.9or an the inner wall of the fifth via hole293hof the signal via. In an embodiment, the first conductive area221and the second conductive area222may be formed in the first conductive layer220. The first conductive area221and the second conductive area222may be formed by removing a partial area312of the first conductive layer220. In an embodiment, the third conductive area231and the fourth conductive area232may be formed in the second conductive layer230. The third conductive area231and the fourth conductive area232may be formed by removing a partial area312of the second conductive layer230. In an embodiment, the conductive areas221,222,231, and232are areas that surround the first via hole310, and may be connected to the conductive material311of the inner wall of the first via hole310. For example, the conductive areas may be electrically insulated from the other areas due to the removed areas312. In various embodiments, the conductive areas221,222,231, and232may be provided through an etching process of etching partial areas (e.g., the removed areas312) of the conductive layers220and230.

In an embodiment, the filling of the insulation material320may include filling the interior of the first via holes310, and laminating the insulation material320on a surface of the first conductive layer220and a surface of the second conductive layer230. For example, an insulation material321filled in the interior of the first via hole310may firmly attach the conductive material311to an inner wall.

In various embodiments, a portion of the insulation material321filled in the first via hole310may form the first side insulation part (e.g., the first side insulation part260ofFIG.8orFIG.9) or the second side insulation part (e.g., the second side insulation part270ofFIG.8orFIG.9). In various embodiments, a portion of the insulation material320may be laminated on a surface of the first conductive layer220to form the first insulation part240. A portion of the insulation material320may be laminated on a surface of the second conductive layer230to form the second insulation part250.

In an embodiment, the first conductive pad241and the second conductive pad242may be disposed on the surface of the first insulation part240. The first conductive pad241and the second conductive pad242may be provided by etching a portion of the conductive layer additionally laminated on the first insulation part240.

In an embodiment, the third conductive pad251and the fourth conductive pad252may be disposed on the surface of the second insulation part250. The third conductive pad251and the fourth conductive pad252may be provided by etching a portion of the conductive layer additionally laminated on the second insulation part250.

In an embodiment, vias330(e.g., the first part281and the third part291) that pass through the first insulation part240may be formed. The vias330may connect the first conductive pad241and the first conductive area221, or connect the second conductive pad242and the second conductive area222. The vias330may include the first via hole281hand the third via hole291hillustrated inFIGS.8and9.

In an embodiment, vias330(e.g., the second part282and the fourth part292) that pass through the second insulation part250may be formed. The second vias330may connect the third conductive pad251and the third conductive area231, or connect the fourth conductive pad252and the fourth conductive area232. The second vias may include the second via hole282hand the fourth via hole292hillustrated inFIGS.8and9.

In an embodiment, as the structure, in which the second vias330are finished, is cut, a portion of the filled insulation material321may be exposed to a side surface of the interposer200. The portion exposed to the side surface may define the first side insulation part260and the second side insulation part270.

The interposer200according to embodiments disclosed in the disclosure may enhance a shielding performance because the ground via Vg is disposed in an area, in which the side plating area included in a conventional interposer is opened. Furthermore, because the side plating area is covered by the first side insulation part260and the second side insulation part270, a gold plating process of covering a side plating area may be omitted, and production costs of the interposer200may be decreased.

Furthermore, the interposer200according to embodiments of the disclosure includes laser machined vias (e.g., the first via hole281h, the second via hole282h, the third via hole291h, and the fourth via hole292h) as compared with the conventional interposer, and thus sizes of the vias may be decreased. The conductive pads are spaced apart from each other at a sufficient interval due to the vias having the reduced sizes, and concerns about short-circuits may be decreased. Furthermore, while the number signal vias is insufficient in a conventional interposer, the interposer200includes a larger number of vias and a sufficient number of signal vias may be provided.

An electronic device100according to an embodiment disclosed in the disclosure may include the housing110, the first board150and the second board190disposed in an interior of the housing110and disposed to face each other in a first direction, the interposer200extending to surround an interior space between the first board150and the second board190, the first conductive layer220disposed to face the first board and including the first conductive area221, the second conductive layer230disposed to face the second board190and including the second conductive area231, the insulation layer210disposed between the first conductive layer220and the second conductive layer230, the first insulation part240disposed between the first conductive layer220and the first board150and covering the first conductive area221, the second insulation part250disposed between the second conductive layer230and the second board190and covering the second conductive area231, the first plating area211extending from the first conductive layer220to the second conductive layer230, on a first side surface of the insulation layer210, the second plating area212extending from the first conductive layer220to the second conductive layer230, on a second side surface of the insulation layer210, the ground via Vg including the first part281passing through the first insulation part240and connected to the first conductive area221, and the second part282passing through the second insulation part250and connected to the second conductive area231, wherein the first conductive area221and the second conductive area231are electrically connected to each other through the first plating area211, and the signal via Vs passing from the first insulation part240to the second insulation part250.

In various embodiments, the interposer may include the first side insulation part260extending from the first insulation part240to the second insulation part250and covering the first plating area211, and the second side insulation part270extending from the first insulation part240to the second insulation part250and covering the second plating area212.

In various embodiments, the first side insulation part260and the second side insulation part270may be integrally formed with the first insulation part240and the second insulation part250.

In various embodiments, the first side insulation part260may define an outer surface of the interposer, and the second side insulation part270may define an inner surface of the interposer.

In various embodiments, the first conductive pad241electrically connected to the first board150may be formed in the first insulation part240, the first conductive pad241may be connected to the first conductive area221through the first part281of the ground via Vg, a second conductive pad251electrically connected to the second board190may be formed in the second insulation part250, and the second conductive pad251may be connected to the second conductive area231through the second part282of the ground via Vg.

In various embodiments, the ground via Vg may electrically connect a ground of the first board150and a ground of the second board190, the first conductive pad241may at least partially contact a ground pad of the first board150, and the second conductive pad251may at least partially contact a ground pad of the second board190.

In various embodiments, the first plating area211and the second plating area212may extend long along the extension direction “E” of the interposer200to surround the interior space.

In various embodiments, the first part281of the ground via Vg may be provided in a form, in which a cross-sectional area thereof becomes smaller as it becomes closer to the first conductive area221, and the second part282of the ground via Vg may be provided in a form, in which a cross-sectional area thereof becomes smaller as it becomes closer to the second conductive area.

In various embodiments, the interposer200may include a first surface at least partially contacting the first board, a second surface at least partially contacting the second board, the inner surface204afacing the interior space, and the outer surface204bbeing opposite to the inner surface and facing an outside of the interior space, the ground via Vg may be located adjacent to any one of the inner surface204aor the outer surface204b, when the first surface is viewed from a top, and the signal via Vs may be located between the other one of the inner surface204aor the outer surface204band the ground via Vg, when the first surface is viewed from the top.

In various embodiments, the interposer200may further include a second ground via Vg, the second ground via Vg may include the third part281passing through the first insulation part240and connected to the third conductive area221included in the first conductive layer220, and the fourth part282passing through the second insulation part250and connected to the fourth conductive area231included in the second conductive layer230, and the third conductive area221and the fourth conductive area231may be electrically connected to each other through the second plating area212.

In various embodiments, the second ground via Vg may be located adjacent to any one of the inner surface204aor the outer surface204b, when the first surface is viewed from the top.

In various embodiments, a plurality of ground vias Vg may be provided, and the signal via Vs may be disposed between any one of the plurality of ground vias Vg and another adjacent one of the plurality of ground vias Vg, when viewed in an extension direction “E” of the interposer200.

In various embodiments, the signal via Vs may include a fifth part293passing through the insulation layer210, a sixth part291passing through the first insulation part240, and a seventh part292passing through the second insulation part250.

In various embodiments, the fifth part293and the sixth part291may be electrically connected to the fifth conductive area222included in the first conductive layer220, and the fifth part293and the seventh part292may be electrically connected to the sixth conductive area232included in the second conductive layer230.

In various embodiments, a cross-sectional area of the fifth part293may be larger than a cross-sectional area of the sixth part291or the seventh part292.

In various embodiments, the fifth part293may have a uniform cross-sectional area.

In various embodiments, the sixth part291and the seventh part292may be provided in a form, in which a cross-sectional area thereof becomes smaller as it becomes closer to the insulation layer210.

In various embodiments, a center axis of the fifth part293may be biased (offset) from a center axis of the sixth part291or the seventh part292at a specific interval.

In various embodiments, the interposer may include a first area “A”, in which the ground via is disposed between the first plating area211and the second plating area212, a second area “B” that is an area, in which the ground via Vg and the signal via Vs are disposed between the first plating area211and the second plating area212, and in which the ground via Vg is adjacent to the first plating area211, and a third area “C” that is an area, in which the ground via Vg and the signal via Vs are disposed between the first plating area211and the second plating area212, and in which the ground via Vg is adjacent to the second plating area212.

In various embodiments, the second area “B” and the third area “C” may be disposed be disposed between two first areas “A”, when viewed in the extension direction “E”.

In various embodiments, the second area “B” and the third area “C” may be disposed between two first areas, when viewed in the extension direction “E”.

The various embodiments of the disclosure and the terms used herein do not limit the technology described in the disclosure to specific forms, and should be construed to include various modifications, equivalents, and/or replacements of the embodiments. With regard to description of drawings, similar components may be marked by similar reference numerals. The terms of a singular form may include plural forms unless otherwise specified. In the disclosure disclosed herein, the expressions “A or B”, or “at least one of A or/and B”, “A, B, or C”, or “at least one of A, B, or/and C”, and the like used herein may include any and all combinations of one or more of the associated listed items. The terms, such as “first”, “second”, and the like used herein may refer to various elements of various embodiments of the disclosure, but do not limit the elements. For example, such terms are used only to distinguish an element from another element and do not limit the order and/or priority of the elements. If it is mentioned that an element (e.g., a first element) is (functionally or communicatively) “connected” to another element (e.g., a second element), the first element may be directly connected to the second element or may be connected to the second element through another element (e.g., a third element).

In the disclosure, the expression “configured to” may be interchangeably used with, for example, “suitable for”, “capable of”, “modified to”, “made to”, “able to”, or “designed to” according to a situation in a hardware or software way. In some situations, the expression “a device configured to” may refer, for example, to the device being “capable of” operating together with another device or other components. CPU, for example, a “processor configured to (or set to) perform A, B, and C” may mean a dedicated processor (e.g., an embedded processor) for performing a corresponding operation or a generic-purpose processor (e.g., a central processing unit (CPU) or an application processor) which may perform corresponding operations by executing one or more programs which are stored in a memory device<0}

The term “module” used in the disclosure may include a unit configured in a hardware, software, or firmware or any combination thereof, and for example, may be used interchangeably with the terms such as logic, a logic block, a component, or a circuit. The “module” may be an integral component, or a minimum unit or a part which performs one or more functions. The “module” may be implemented mechanically or electronically, and for example, may include an application-specific integrated circuit (ASIC) chip, field-programmable gate arrays (FPGSs), or a programmable logic device that is known or to be developed in the future, which performs some operations.

At least some of the devices (e.g., modules or functions) or methods (e.g., operations) according to various embodiments of the disclosure may be implemented by an instruction stored in a computer-readable storage medium (e.g., the memory), for example, in the form of a program module. When the instruction is executed by the processor (for example, the processor), the at least one processor may perform a function corresponding to the instruction. The computer-readable recording medium may include a hard disk, a floppy disk, a magnetic medium (e.g., a magnetic tape), an optical recording medium (e.g., a CD-ROM or a DVD), an magneto-optical medium (e.g., a floptical disk), and an embedded memory. The instruction may include a code made by a compiler or a code that may be executed by an interpreter.

Each of the elements (e.g., a module or a program) according to various embodiments may include a single or a plurality of entities, and some of the corresponding sub-elements may be omitted or another sub-element may be further included in various embodiments. Alternatively or additionally, some elements (e.g., a module or a program module) may be integrated into one entity to perform functions performed by the corresponding elements before the integration in the same way or similarly. The operations performed by a module, a program module, or another element according to various embodiments may be executed sequentially, in parallel, repeatedly, or heuristically, or at least some operations may be executed in another sequence or may be omitted, or another operation may be added.