Method of writing data to a memory device and reading data from the memory device

A method of writing data to a memory device and reading data from the memory device includes issuing a challenge to a PUF device during a power-up process in order to derive a PUF response, error correcting the PUF response, providing delinearized addresses via a delinearization algorithm to the memory device using the error corrected PUF response, masking data, which is written to the memory device, via a masking module using the error corrected PUF response, de-masking data, which is read from the memory device, via the masking module (19) using the error corrected PUF response; and performing a check-sum verification of read data such that address delinearization and data masking are used together to obfuscate the memory content.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a U.S. national stage of application No. PCT/EP2016/050667 filed 14 Jan. 2016, and claims priority to European application No. 15464002 filed Jan. 15, 2015, the content of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method of writing data to a memory device and reading data from the memory device, and to a system on chip for implementing the method.

2. Description of the Related Art

Generally, an interaction of a system on chip (SoC) with an external memory device constitutes threats. In order to avoid security attacks, such as sniffing, the memories need to be protected.

A common solution to provide protection is cryptography. In some circumstances, however, this approach is not the right choice. An alternative solution is address obfuscation. US2009/0327709-A1 discloses a method of address obfuscation, which is simple to apply but leaves the actual data unprotected. If the instruction set is known and a memory dump can be executed the memory can be de-obfuscated easily and therefore the original memory content is reconstructed.

SUMMARY OF THE INVENTION

In view of the foregoing, it is an object of the invention to provide an improved method for protecting external memory content.This and other objects and advantages are achieved in accordance with the invention by a method of writing data to a memory device and reading data from the memory device, which includes issuing a challenge to a PUF device during a power-up process to derive a PUF response, error correcting the PUF response, providing delinearized addresses via a delinearization algorithm to the memory device using the error corrected PUF response masking data, which is written to the memory device, via a masking module using the error corrected PUF response-masking data, which is read from the memory device, via the masking module using the error corrected PUF response and performing a check-sum verification of read data.

In order to mitigate attacks, such as sniffing, the method in accordance with the invention uses a delinearization approach for an address bus and a masking approach for the data. Thus, address delinearization and data masking are used together to obfuscate the memory content.

With a Physical Unclonable Function (PUF), a unique response is challenged. With this unique response, the delinearization of the addresses and the masking or de-masking of data is performed.

In an advantageous embodiment of the method, the check-sum verification is performed by using a cyclic error-correcting code. Error-correcting codes provide the ability to identify and to locate any error, whereas a cyclic code is an especially useful kind of error-correcting code.

An improvement of the method comprises an additional step of generating a reset signal in case of data falsification to reset a processor that interacts with the memory device. Thus, a reset occurs immediately, if a device with this implemented method is corrupted.

Moreover, it is advantageous if the data is masked with the error corrected PUF response using the XOR operator, and if the data is revealed out of masked data with the error corrected PUF response using an XOR operator. Such a data transformation is fast and needs little computing power.

An advantageous embodiment of the method utilizes a PUF device with silicon physical unclonable functions of a system on chip that comprises a processor and a memory controller. Thus, the achieved memory obfuscation relies on the PUF device that exploits unique physical characteristics of a silicone device.

Each silicon device is uniquely characterized yielding the same unique memory patterns, making reverse engineering attacks, based on memory dumps, practically impossible.

As no enrollment phase is needed, the silicon device can be directly shipped to a customer. The solution can even be applied to a bootloader. Changes to the bootloader would be detected, if the bootloader is stored in the ROM memory via the memory controller and thus the memory obfuscation module.

It is also an object of the invention to provide a system on chip which comprises a processor, a memory controller and a memory obfuscation module that is connected to a data bus and to a address bus, where the memory obfuscation module is set up to implement the above-described method in accordance with the disclosed embodiments.

In a specific embodiment, the obfuscation module comprises the PUF device, an address delinearization module and a data masking module. Thus, the inventive structure is implemented in hardware and is adjacent to the memory controller without modifying it.

In order to correct an insufficient PUF response the obfuscation module comprises an error correction module connected to the PUF device.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

FIG. 1shows a system on chip (SoC) with a memory controller1that is connected to an address bus2and a data bus3. Via theses busses2,3, addresses and data are exchanged with various memory devices4,5,6, such as RAM4, rewritable memory5or ROM6. For this purpose the memory controller1and the memory devices4,5,6comprise address connections7and data connections8.

The RAM4and the rewritable memory5comprise R/W′-inputs9, which are connected to a corresponding output10of the memory controller1. Additionally, each memory device4,5,6comprises a CE-input11that is respectively connected to a corresponding CS-output12,13,14of the memory controller1.

The memory controller1is responsible for accessing the external memories4,5,6attached to the SoC. The memory controller1sets the address on the address bus2and reads or writes the data via data bus3.

Adjacent to the memory controller1the inventive obfuscation module15is connected to the busses2,3. In particular, the obfuscation module15is arranged between the memory controller1and the memory devices4,5,6.

The obfuscation module15is shown inFIG. 2in detail. Obfuscation module15comprises a PUF device16that responds to a challenge with a unique output by utilizing a silicon physical unclonable function.

The PUF device16utilizes the fact that no integrated circuit (IC) is similar to another because of production process variations. For example, path delays vary enough across ICs to use them for identification. Therefore, PUF provides a direct link between the physical properties of the silicon device and the security level provided.

The output of the PUF device16is input to an error correction module17to make the PUF response consistent.

The error corrected PUF response is used in the obfuscation structure as such, i.e., in an address delinearization module18and in a data masking module19.

The address delinearization module18is connected to the address bus2and delinearizes the exchanged addresses. The data masking module19is connected to the data bus3and masks or de-masks the exchanged data.

The different method steps are described with reference to the flowchart shown inFIG. 3.

During power-up (step20) the PUF device16is challenged (step21). As a result the PUF response is derived22. In a next step (23), the PUF response is error corrected. Next, the error corrected PUF response is then passed to the address delinearization (address obfuscation) (step24) and data masking or de-masking is performed (step25).

Address delinearization (step24) and masking or de-masking (step25) are implemented with any known mathematically proven theory in order to realize the needed functionality. Address delinearization (step24) randomizes the addresses of code and data segments. For this purpose, the error corrected PUF response is considered as random response.

During the write operation, the addresses are delinearized and the data to be written is masked with the error corrected PUF response. During the read operation, the same addresses are selected as before but the data is de-masked, thus revealing the original data.

In order to check the validity of the read data, check-sum verification (step26) is performed. For this purpose the cyclic error-correcting code (CRC) is preferred.

If the silicon device is subject to any physical attacks, the PUF response changes, thus yielding wrong addresses and wrong data during the de-masking operation. In this case, the validity decision (step27) of the check-sum is NO.

There are different possibilities for a reaction (step28). The simplest way is to issue an alarm. A more sophisticated approach is to reset a processor (CPU) of the SoC, whereas any attack is blocked immediately.

If the check-sum verification (step26) results in a YES-decision, an execution (step29) of the loaded code is performed.