Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on and claims priority to Japanese Patent Application No. 2010-224695 filed on Oct. 4, 2010, the contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a semiconductor device including a semiconductor substrate having an electrode portion constructed with two conductors that are spaced by an insulator and located in a hole of the semiconductor substrate. The present invention also relates to a method of manufacturing the semiconductor device.

BACKGROUND

As disclosed in, for example, JP-A-2006-19455 corresponding to US 2006/0001174 and JP-A-2007-81100, a semiconductor device including a semiconductor substrate having a through electrode portion for electrically connecting front and back surfaces of the semiconductor substrate has been known. Such a semiconductor device can be reduced in size.

The electrode portion is formed as follows. Firstly, a through hole extending from the front surface to the back surface of the semiconductor substrate is formed by, for example, an etching technique. Then, a first conductor, an insulation layer, and a second conductor are formed in the through hole by, for example, a sputtering technique and a chemical vapor deposition (CVD) technique. The first conductor has a tube shape and is formed on an inner surface of the through hole. The insulation layer has a tube shape and is formed on an inner surface of the first conductor. The second conductor has a column shape and is formed in a hollow of the insulation layer so that the hollow can be filled with the second conductor.

For example, the first conductor is used as a signal line, and the second conductor is used as a ground line. The second conductor is shielded by the first conductor so that noise in the first conductor as a signal line can be reduced.

To increase such a shield effect, it is preferable to increase a capacitance of a capacitor constructed with the first and second conductors spaced by the insulation layer.

The capacitance can be increased by increasing the area of the first and second conductors. However, in the conventional semiconductor device, an increase in the area of the first and second conductors results in an increase in a diameter of the through hole. As a result, the through electrode is increased in size, and the semiconductor device is increased in size.

SUMMARY

In view of the above, it is an object of the present invention to provide a semiconductor device including a semiconductor substrate having an electrode portion constructed with two conductors that are spaced by an insulator and located in a hole of the semiconductor substrate in such a manner that a capacitance between the conductors is increased. It is another object of the present invention to provide a method of manufacturing the semiconductor device.

According to an aspect of the present invention, a semiconductor device includes a semiconductor substrate, a first conductor, an insulator, and a second conductor. The semiconductor substrate has a front surface and a back surface opposite to the front surface. The semiconductor substrate includes a first region and a second region located adjacent to the first region. The first region includes a plurality of blind holes, each of which has an opening on the front surface and a bottom defined by the back surface. The second region includes a through hole extending through the semiconductor substrate from the front surface to the back surface. A width of each blind hole is less than a width of the through hole. The first conductor includes a first portion located on an inner surface of each blind hole, a second portion located on the first surface around the opening of each blind hole, and a third portion located on an inner surface of the through hole. The insulator includes a first portion located on the first portion of the first conductor, a second portion located on the second portion of the first conductor, and a third portion located on the third portion of the first conductor. The second conductor includes a first portion located on the first portion of the insulator and electrically insulated from the first portion of the first conductor, a second portion located on the second portion of the insulator and electrically insulated from the second portion of the first conductor, and a third portion located on the third portion of the insulator and electrically insulated from the third portion of the first conductor. The first portion and the second portion of the first conductor are joined to form a first single continuous conductor. The first portion and the second portion of the second conductor are joined to form a second single continuous conductor. The first portion and the second portion of the insulator are joined to form a single continuous insulator. The first single continuous conductor, the second single continuous conductor, and the single continuous insulator form a capacitor having a predetermined capacitance. The third portion of the first conductor is electrically connected to the first portion and the second portion of the first conductor so that the first portion and the second portion of the first conductor are drawn through the third portion of the first conductor to the back surface of the semiconductor substrate. The third portion of the second conductor is electrically connected to the first portion and the second portion of the second conductor so that the first portion and the second portion of the second conductor are drawn through the third portion of the second conductor to the back surface of the semiconductor substrate.

According to another aspect of the present invention, a method of manufacturing a semiconductor device includes preparing a semiconductor substrate having a front surface and a back surface opposite to the front surface, forming first blind holes and a second blind hole on the front surface side of the semiconductor substrate in such a manner that a depth of the second blind hole is less than a depth of each first blind hole measured from the front surface of the semiconductor substrate, and forming a first single continuous conductor on the front surface side of the semiconductor substrate. The first single continuous conductor has a first portion formed on an inner surface of each first blind hole, a second portion formed on the first surface around an opening of each first blind hole, and a third portion formed on an inner surface of the second blind hole, and a fourth portion formed on the first surface around an opening of the second blind hole. The method further includes forming a single continuous insulator on the front surface side of the semiconductor substrate. The single continuous insulator has a first portion formed on the first portion of the first single continuous conductor, a second portion formed on the second portion of the first single continuous conductor, a third portion formed on the third portion of the first single continuous conductor, and a fourth portion formed on the fourth portion of the first single continuous conductor. The method further includes forming a second single continuous conductor on the front surface side of the semiconductor substrate. The single continuous insulator has a first portion formed on the first portion of the single continuous insulator, a second portion formed on the second portion of the single continuous insulator, a third portion formed on the third portion of the single continuous insulator, and a fourth portion formed on the fourth portion of the single continuous insulator. The method further includes thinning the semiconductor substrate from the back surface side until the third portion of the first single continuous conductor and the third portion of the single continuous insulator are exposed to the back surface of the semiconductor substrate, and removing the third portion of the single continuous insulator exposed to the back surface of the semiconductor substrate so that the third portion of the second single continuous conductor is exposed to the back surface of the semiconductor substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A semiconductor device according to a first embodiment of the present invention is described below with reference toFIGS. 1 and 2.FIG. 1is a diagram illustrating a cross-sectional view of the semiconductor device, andFIG. 2is a diagram illustrating a cross-sectional perspective view of the semiconductor device from a front surface11side of a semiconductor substrate10of the semiconductor device.

The semiconductor substrate10has a plate-like shape. The semiconductor substrate10has the front surface11and a back surface12opposite to the front surface11. As described in detail below, an electrode portion constructed with two conductors40,60spaced by an insulator50is formed in blind and through holes of the semiconductor substrate10.

The semiconductor substrate10has a first region1and a second region2. The semiconductor substrate10is a typical semiconductor substrate such as a silicon substrate. It is preferable that a resistivity of each of the first region1and the second region2be 0.1 Ω·cm or less. In such an approach, the semiconductor substrate10itself can serve as a current path of the semiconductor device. The resistivity of each of the first region1and the second region2can be easily reduced to 0.1 Ω·cm or less by adjusting the concentration of impurities doped into the semiconductor substrate10.

The first region1has blind holes20. The blind holes20are arranged as a group in the first region1. Each blind hole20is circular and extends from the front surface11toward the back surface12. The blind hole20has an opening on the front surface11. The blind hole20does not reach the back surface12and has a bottom inside the semiconductor substrate10. That is, the bottom of the blind hole20is defined by the back surface12.

The second region2is located adjacent to the first region1and has through holes30. Each through hole30is circular and penetrates the semiconductor substrate10in a thickness direction of the semiconductor substrate10perpendicular to each of the front surface11and the back surface12. That is, the through hole30extends through the semiconductor substrate10from the front surface11to the back surface12. Thus, the through hole30has an opening on each of the front surface11and the back surface12. According to the first embodiment, the first region1is substantially circular in plane, and the second region2is located around the first region1so that the first region1can be surrounded by the second region2. Thus, the group of the blind holes20is surrounded by the through holes30.

As described above, the blind hole20and the through hole30are circular. The blind hole20is smaller in diameter than the through hole30. It is noted that the blind hole20and the through hole30can have a shape other than a circular shape. In such a case, the blind hole20is smaller in width than the through hole30.

As described later, according to the first embodiment, the blind hole20and the through hole30are formed at the same time by trench etching by using the fact that the etching rate increases with an increase in the hole diameter.

In the first region1of the semiconductor substrate10, a first conductor40having a tube shape with a bottom is located in the blind hole20so that an inner surface of the blind hole20can be covered with the first conductor40. A second conductor60is located inside the tube-shaped first conductor40in the blind hole20. An insulator50is located between the first conductor40and the second conductor60in the blind hole20in such a manner that the first conductor40and the second conductor60can be electrically insulated from each other by the insulator50. Thus, each blind hole20is filled with the first and second conductors40,60spaced by the insulator50.

Specifically, the first conductor40is located on the inner surface of the blind hole20. The insulator50has a tube shape with a bottom and is located on an inner surface of the first conductor40. The second conductor60has a column shape and is located in a hollow of the insulator50so that the hollow of the insulator50can be filled with the second conductor60.

More specifically, the first conductor40, the insulator50, and the second conductor60are stacked in this order from the inner surface of the blind hole20to the center of the blind hole20to form a sandwich structure extending in a depth direction of the blind hole20(i.e., in the thickness direction of the semiconductor substrate10). That is, a stacked direction in which the first conductor40, the insulator50, and the second conductor60are stacked is perpendicular to the depth direction of the blind hole20.

It is preferable that the first conductor40and the second conductor60have a resistivity less than that of the semiconductor substrate10. For example, the first conductor40and the second conductor60can be made of metal such as copper (Cu), aluminum (Al), or tungsten (W). For example, the first conductor40and the second conductor60can be formed by a sputtering technique, a CVD technique, or a plating technique. It is preferable that the insulator50have a permittivity (i.e., dielectric constant) of three or more. For example, the insulator50can be made of silicon oxide or tantalum oxide. For example, the insulator50can be formed by a sputtering technique or a CVD technique.

In the first region1of the semiconductor substrate10, each of the first conductor40, the insulator50, and the second conductor60is formed not only in the blind hole20but also on the front surface11between adjacent blind holes20. Thus, each of the first conductor40, the insulator50, and the second conductor60continuously extends between adjacent blind holes20.

In other words, each of the first conductor40, the insulator50, and the second conductor60extends from the inside of the blind hole20to the front surface11around the opening of the blind hole20, extends along the front surface11, and then enters an adjacent blind hole20. That is, the sandwich structure, in which the first conductor40, the insulator50, and the second conductor60are stacked, continuously extends between adjacent blind holes20through the front surface11of the semiconductor substrate10.

Although a planar shape of the first conductor40viewed from the front surface11side of the semiconductor substrate10is recessed at the blind hole20and the through hole30, the first conductor40is formed as a single continuous layer extending over the front surface11of the first region1and the second region2of the semiconductor substrate10.

A planar shape of the insulator50viewed from the front surface11side of the semiconductor substrate10follows the planar shape of the first conductor40on which the insulator50is located. The second conductor60extends between the blind hole20and the through hole30through the front surface11of the semiconductor substrate10. Thus, the second conductor60is formed as a single continuous layer extending over the front surface11of the first region1and the second region2of the semiconductor substrate10to fill the blind hole20and the through hole30and to cover a portion of the front surface11between adjacent blind holes20and a portion of the front surface11between the blind hole20and the through hole30.

In this way, the sandwich structure, in which the first conductor40, the insulator50, and the second conductor60are stacked, continuously extends over the front surface11of the semiconductor substrate10and the inner surface of each of the blind hole20and the through hole30.

Thus, the sandwich structure continuously extends between all the blind holes20to form one capacitor (capacitance section) having a predetermined capacitance.

That is, the first region1of the semiconductor substrate10is configured as a capacitor section for providing the capacitance that is formed with the sandwich structure including the first and second conductors40,60spaced by the insulator50.

In the second region2of the semiconductor substrate10, the first conductor40is located in the through hole30so that an inner surface of the through hole30can be covered with the first conductor40. The second conductor60is located inside the first conductor40in the through hole30. The insulator50is located between the first conductor40and the second conductor60in the through hole30so that the first conductor40and the second conductor60can be electrically insulated from each other by the insulator50. Thus, the sandwich structure formed in the blind hole20is also formed in the through hole30.

Specifically, the first conductor40has a tube shape and is located on the inner surface of the through hole30. The insulator50has a tube shape and is located on the inner surface of the first conductor40in the through hole30. The second conductor60has a column shape and is located in a hollow of the insulator50in the through hole30so that the hollow of the insulator50can be filled with the second conductor60. In the through hole30, each of the first conductor40, the insulator50, and the second conductor60extends from the front surface11to the back surface12.

The first conductor40in the blind hole20is electrically connected to the first conductor40in the through hole30. Likewise, the second conductor60in the blind hole20is electrically connected to the second conductor60in the through hole30. Thus, the first conductor40and the second conductor60in the blind hole20are drawn to both the front surface11and the back surface12of the semiconductor substrate10through the first conductor40and the second conductor60in the through hole30.

That is, the second region2of the semiconductor substrate10is configured as an electrode drawing section for drawing the first conductor40and the second conductor60of the capacitor section of the first region1to both the front surface11and the back surface12of the semiconductor substrate10. According to the first embodiment, the first conductor40and the second conductor60in the blind hole20are electrically connected though the front surface11of the semiconductor substrate10to the first conductor40and the second conductor60in the through hole30.

Specifically, the first conductor40and the second conductor60in the blind hole20are electrically connected though the first conductor40and the second conductor60on the front surface11of the semiconductor substrate10between the blind hole20and the through hole30to the first conductor40and the second conductor60in the through hole30. Thus, the first conductor40and the second conductor60in the blind hole20are drawn to both the front surface11and the back surface12through the first conductor40and the second conductor60in the through hole30.

As described above, the second conductor60is formed as a single continuous layer extending over the front surface11of the semiconductor substrate10and the inside of each of the blind hole20and the through hole30. Further, the second conductor60extends from the front surface11to the back surface12by passing the through hole30. Thus, the second conductor60is drawn to not only the front surface11but only to the back surface12.

The second conductor60on the front surface11of the semiconductor substrate10is configured as a front-surface side signal terminal71. According to the first embodiment, the front-surface side signal terminal71electrically connects the second conductor60in the blind hole20to the second conductor60in an adjacent blind hole20and also electrically connects the second conductor60in the blind hole20to the second conductor60in the through hole30.

InFIG. 2, the front-surface side signal terminal71is partially illustrated as a semicircle. However, the front-surface side signal terminal71as a whole has a circular planar shape over the first region1and the second region2.

Further, as described above, each of the first conductor40and the insulator50continuously extends between the blind boles20and extends from the front surface11of the semiconductor substrate10between the blind hole20and the through hole30to the inside of the through hole30. Each of the first conductor40and the insulator50extends from the front surface11to the back surface12by passing the through hole30. Thus, each of the first conductor40and the insulator50is drawn to not only the front surface11but only to the back surface12.

A back-surface side connection layer75is formed on the back surface12of the semiconductor substrate10. The first conductor40, which is drawn to the back surface12through the through hole30, is electrically connected to the back-surface side connection layer75.

The back-surface side connection layer75is formed as a single continuous layer extending over the back surface12of the first region1and the second region2of the semiconductor substrate10. The back-surface side connection layer75is in contact with and covers the first conductor40in the through hole30. The back-surface side connection layer75has an opening communicating with the through hole30. A width of the opening of the back-surface side connection layer75is less than the width of the opening of the first conductor40in the through hole30so that the opening of the back-surface side connection layer75can be located inside the opening of the first conductor40(seeFIG. 6).

According to the first embodiment, the back-surface side connection layer75is made of the same material as that of the first conductor40. Alternatively, the back-surface side connection layer75can be made of a different material from that of the first conductor40, as long as the back-surface side connection layer75can have almost the same electrical conductivity as the first conductor40. For example, when the first conductor40is made of copper (Cu), the back-surface side connection layer75can be made of aluminum (Al).

An insulation cover layer77is formed on the back surface12side of the semiconductor substrate10to cover the back-surface side connection layer75. Further, the cover layer77is joined to the insulator50in the through hole30.

According to the first embodiment, the cover layer77is made of the same material as that of the insulator50. Alternatively, the cover layer77can be made of a different material from that of the insulator50, as long as the cover layer77can have almost the same electrical insulation property as the insulator50.

The cover layer77has an opening where the second conductor60in the through hole30is exposed and an opening where the back-surface side connection layer75jointed to a back-surface side ground terminal82is exposed. The back-surface side ground terminal82is described in detail later.

Further, a back-surface side signal terminal72is formed as a single continuous layer on the back surface12side of the semiconductor substrate10. The back-surface side signal terminal72is located corresponding to the front-surface side signal terminal71and covers the cover layer77. It is noted that the back-surface side signal terminal72is in contact with the second conductor60in the through hole30through the opening of the cover layer77. On the back surface12of the semiconductor substrate10, the second conductor60in the through hole30is electrically connected through the back-surface side signal terminal72to the second conductor60in an adjacent through hole30.

The back-surface side signal terminal72has almost the same circular planar shape as the front-surface side signal terminal71over the first region1and the second region2. The front-surface side signal terminal71and the back-surface side signal terminal72are electrically connected together through the second conductor60in the through hole30.

The back-surface side ground terminal82is located on the back surface12of the second region2of the semiconductor substrate10and separated from the through hole30. The back-surface side ground terminal82has a ring shape and surrounds the back-surface side signal terminal72.

The back-surface side ground terminal82is in contact with and electrically connected to the back-surface side connection layer75though the opening of the cover layer77. In contrast, the back-surface side ground terminal82is separated and electrically isolated from the back-surface side signal terminal72by the cover layer77.

A front-surface side ground terminal81is formed on the front surface11of the second region2of the semiconductor substrate10and located corresponding to the back-surface side ground terminal82. The front-surface side ground terminal81has almost the same ring shape as the back-surface side ground terminal82and surrounds the front-surface side signal terminal71. It is noted thatFIG. 2illustrates a half of the front-surface side ground terminal81.

The first conductor40and the insulator50in the through hole30extends to the front surface11of the semiconductor substrate10and is interposed between the front surface11and the front-surface side ground terminal81.

The front-surface side ground terminal81is in contact with and electrically connected to the first conductor40through the opening of the insulator50. In contrast, the front-surface side ground terminal81is separated and electrically isolated from the front-surface side signal terminal71by the insulator50.

The semiconductor device according to the first embodiment is summarized below. The first conductor40formed in the blind hole20of the first region1, which is configured as a capacitor section, is electrically connected through the front surface11to the first conductor40formed in the through hole30of the second region2, which is configured as an electrode drawing section.

On the front surface11of the semiconductor substrate10, the first conductor40is drawn to the front-surface side ground terminal81that is located around the opening of the through hole30. In contrast, on the back surface12of the semiconductor substrate10, the first conductor40is drawn to the back-surface side ground terminal82through the back-surface side connection layer75.

On the other hand, the second conductor60formed in the blind hole20of the first region1, which is configured as a capacitor section, is electrically connected through the front surface11to the second conductor60formed in the through hole30of the second region2, which is configured as an electrode drawing section.

On the front surface11of the semiconductor substrate10, the second conductor60is drawn to the front-surface side signal terminal71that is located on the through hole30. In contrast, on the back surface12of the semiconductor substrate10, the second conductor60is drawn to the back-surface side signal terminal72.

Thus, the first conductor40in the blind hole20is drawn to each of the front surface11and the back surface12through the first conductor40in the through hole30and connected to each of the front-surface side ground terminal81and the back-surface side ground terminal82. Likewise, the second conductor60in the blind hole20is drawn to each of the front surface11and the back surface12through the second conductor60in the through hole30and connected to each of the front-surface side signal terminal71and the back-surface side signal terminal72.

The first and second conductors40,60drawn to the front and back surfaces11,12can be connected to another device through the signal terminals71,72and the ground terminals81,82.

For example, the signal terminals71,72and the ground terminals81,82can be electrically connected to a semiconductor element (not shown) formed in the semiconductor substrate10, an electrical component mounded on the semiconductor substrate10, or a terminal of an external substrate.

According to the first embodiment, as shown inFIG. 1, the front-surface side signal terminal71is configured as a signal input terminal, and the back-surface side signal terminal72is configured as a signal output terminal. When a signal containing noise is inputted to the front-surface side signal terminal71, the noise flows to the ground terminals81,82through a capacitor formed between the signal terminal and the ground terminal. Thus, the amount of noise contained in the signal outputted from the back-surface side signal terminal72is less than the amount of noise contained in the signal inputted to the front-surface side signal terminal71.

By the way, according to the first embodiment, the second region2of the semiconductor substrate10is configured as an electrode drawing section for drawing the first conductor40and the second conductor60of the capacitor section to both the front surface11and the back surface12of the semiconductor substrate10.

In the first region1for providing the capacitance section, a group of the blind holes20is formed, and the first and second conductors40,60spaced by the insulator50are located in each blind hole20. The first and second conductors40,60in all of the blind holes20are connected so that the area between the first and second conductors40,60can be increased. Thus, the capacitance of the capacitor section can be increased.

Further, since the width of each blind hole20is smaller than the width of the through hole30, an increase in size of the capacitance section can be reduced as much as possible. Further, since the blind holes20are located close to each other, the effect of parasitic inductance and resistance component due to the wiring drawing can be reduced as much as possible. Thus, the capacitance section can effectively remove high-frequency noise.

Next, a method of manufacturing the semiconductor device according to the first embodiment is described below with further reference toFIGS. 3A-3C,FIGS. 4A-4C,FIGS. 5A and 5B,FIG. 6, andFIGS. 7A and 7B.

Firstly, the semiconductor substrate10having the front surface11and the back surface12is prepared. Then, in a first process shown inFIG. 3A, first holes21and second holes31are formed in the front surface11of the semiconductor substrate10. A depth of each second hole31is greater than a depth of each first hole21measured from the front surface11. It is noted that the depths of the first hole21and the second hole31are less than a thickness of the semiconductor substrate10. That is, each of the first hole21and the second hole31is a blind hole.

The first hole21and the second hole31are formed at the same time by a dry etching technique by setting a width of the first hole21less than a width of the second hole31. According to the first embodiment, the first hole21and the second hole31are circular and formed at the same time by a dry etching technique by setting a diameter of the first hole21less than a diameter of the second hole31. In such an approach, the depth of the second hole31can become greater than the depth of the first hole21.

The diameter of the first hole21can be easily set less than the diameter of the second hole31by using an etching mask in which a diameter of a first opening for the first hole21is less than a diameter of a second opening for the second hole31. The etching mask having the first opening and the second opening can be formed by a photolithography technique, for example. When the first hole21and the second hole31are formed at the same time by a dry etching technique using the etching mask having the first opening and the second opening, the depth of the second hole31becomes greater than the depth of the first hole21.

Specifically, since the first opening for the first hole21is less than the second opening for the second hole31, an etching rate at which the first hole21is etched in the semiconductor substrate10is less than an etching rate at which the second hole31is etched in the semiconductor substrate10. Therefore, when the first hole21and the second hole31are formed at the same time by a dry etching technique using the etching mask having the first opening and the second opening, the depth of the second hole31becomes greater than the depth of the first hole21. For example, the dry etching technique can use sulfur hexafluoride (SF6) gas.

Then, in a second process shown inFIG. 3B, the first conductor40is formed on the semiconductor substrate10from the front surface11side. As a result, the first conductor40is formed on an inner surface of each first hole21, on an inner surface of each second hole31, on a portion of the front surface11between adjacent first holes21, and on a portion of the front surface11between the first hole21and the second hole31.

Thus, in the second process, the first conductor40is formed as a single continuous layer extending over the front surface11to follow the shapes of the first hole21and the second hole31. That is, the first conductor40has a tube shape with a bottom in each of the first hole21and the second hole22. For example, the first conductor40can be formed by a sputtering technique, a CVD technique, or a plating technique by using Cu, Al, or W.

Next, in a third process shown inFIG. 3C, the insulator50is formed on the semiconductor substrate10from the front surface11side. As a result, the insulator50is formed on the first conductor40.

Specifically, the insulator50is formed on the first conductor40in each first hole21, on the first conductor40in each second hole31, on the first conductor40on the portion of the front surface11between adjacent first holes21, and on the first conductor40on the portion of the front surface11between the first hole21and the second hole31.

Thus, in the third process, the insulator50is formed as a single continuous layer extending over the first conductor40to follow the shape of the first conductor40. That is, the insulator50has a tube shape with a bottom in each of the first hole21and the second hole22. For example, the insulator50can be formed by a sputtering technique or a CVD technique by using silicon oxide or tantalum oxide.

Then, in a fourth process shown inFIG. 4A, the second conductor60is formed on the semiconductor substrate10from the front surface11side. As a result, the second conductor60is formed on the insulator50so that a hollow of the tube-shaped insulator50in each of the first hole21and the second hole31can be filled with the second conductor60.

Specifically, the second conductor60is formed on the insulator50in each first hole21, on the insulator50in each second hole31, on the insulator50on the portion of the front surface11between adjacent first holes21, and on the insulator50on the portion of the front surface11between the first hole21and the second hole31.

Thus, in the fourth process, the second conductor60is formed as a single continuous layer extending over the insulator50to fill the first hole21and the second hole31. For example, the second conductor60can be formed by a sputtering technique, a CVD technique, or a plating technique by using Cu, Al, or W.

Then, as shown inFIG. 4B, the front-surface side signal terminal71is formed by patterning the second conductor60on the front surface11by a photolithography technique or the like.

Further, an opening51is formed in the insulator50by patterning the insulator50exposed to the front surface11around the front-surface side signal terminal71by a photolithography technique or the like. As a result, the first conductor40is exposed through the opening51. Like the front-surface side ground terminal81, which is formed on the opening51in a next process, the opening51can have a continuous ring shape. Alternatively, the opening51can have portions that are arranged at intervals in a ring shape.

Then, as shown inFIG. 4C, the front-surface side ground terminal81is formed on the opening51of the insulator50by the same technique as the first conductor40and by using the same material as the first conductor40. As a result, the front-surface side ground terminal81and the first conductor40are electrically connected together through the opening51.

Next, in a fifth process shown inFIG. 5A, the semiconductor substrate10is thinned from the back surface12side until the first conductor40and the insulator50in the second hole31are exposed to the back surface12.

For example, the semiconductor substrate10can be thinned by polishing the back surface12side of the semiconductor substrate by a chemical mechanical polishing (CMP) technique.

As a result of the fifth process, the first hole21is formed into the blind hole20, and the second hole31is formed into the through hole30. The first conductor40and the insulator50in the through hole30are exposed to the back surface12of the semiconductor substrate10. In contrast, the second conductor60in the through hole30remains covered with the insulator50on the back surface12side and thus is not exposed to the back surface12side.

Then, as shown inFIG. 5B, the back-surface side connection layer75is formed on the back surface12of the semiconductor substrate10by the same technique as the second conductor60and by using the same material as the second conductor60.

Specifically, as shown in detail inFIG. 6, on the back surface12of the semiconductor substrate10, the insulator50in the through hole30is exposed outside the back-surface side connection layer75, and the first conductor40in the through hole30is in contact with and electrically connected to the back-surface side connection layer75.

Then, as shown inFIG. 7A, the cover layer77is formed on the back surface12of the semiconductor substrate10by the same technique as the insulator50and by using the same material as the insulator50.

Specifically, the cover layer77is formed over the entire back surface12of the first region1and the second region2of the semiconductor substrate10and then patterned so that the insulator50in the through hole30and a portion of the first conductor40to be connected to the back-surface side ground terminal82can be exposed outside the cover layer77.

Further, as a sixth process, the insulator50, which is located in the through hole30and exposed outside the cover layer77, is removed at the same time as the cover layer77is patterned. As a result, the second conductor60in the through hole30can be exposed outside the cover layer77.

Next, as shown inFIG. 7B, the back-surface side signal terminal72is formed by a photolithography technique or the like by using the same material as the second conductor60, and the back-surface side ground terminal82is formed by a photolithography technique or the like by using the same material as the first conductor40. In this way, the semiconductor device according to the first embodiment is manufactured.

As described above, according to the first embodiment, the first hole21and the second hole31are formed at the same time by a dry etching technique by setting the width of the first hole21less than the width of the second hole31. In such an approach, the depth of the first hole21can be smaller than the depth of the second hole31.

Alternatively, the first hole21and the second hole31can be separately formed. In such an approach, the depth of the first hole21can be smaller than the depth of the second hole31without setting the width of the first hole21less than the width of the second hole31.

A semiconductor device according to a second embodiment of the present invention is described below with reference toFIG. 8.FIG. 8is a diagram illustrating a cross-sectional perspective view of the semiconductor device. A difference between the first embodiment and the second embodiment is the shape of the blind hole20.

As shown inFIG. 8, according to the second embodiment, each blind hole20has a hexagonal shape. The blind holes20are grouped and arranged to form a honeycomb structure. Thus, a group of the blind holes20has a honeycomb structure.

Like the first embodiment, the width of each blind hole20is less than the width of each through hole30. According to the second embodiment, the maximum width of the blind hole20(i.e., the length of a diagonal of the hexagonal shape) is less than the diameter of the through hole30.

As described above, according to the second embodiment, the blind holes20are arranged to form a honeycomb structure. In such an approach, the area of the semiconductor substrate10occupied by the blind holes20can be reduced so that a decrease in a mechanical strength of the semiconductor substrate10can be reduced. Like the first embodiment, since the width of the blind hole20is less than the width of the through hole30, the blind hole20and the through hole30can be easily formed by using the fact that the etching rate increases with an increase in the hole width.

The semiconductor device according to the second embodiment can be manufactured in the same method as the semiconductor device according to the first embodiment except that the first hole21is formed into a hexagonal shape.

A semiconductor device according to a third embodiment of the present invention is described below with reference toFIG. 9.FIG. 9is a diagram illustrating a cross-sectional perspective view of the semiconductor device. A difference between the first embodiment and the third embodiment is the shape of the blind hole20.

As shown inFIG. 9, according to the third embodiment, each blind hole20has a rectangular shape such as a trench. Like the first embodiment, the width of each blind hole20is less than the width of each through hole30. Specifically, the length of the shorter side of the rectangular blind hole20is less than the diameter of the through hole30. Therefore, like the first embodiment, the blind hole20and the through hole30can be easily formed by using the fact that the etching rate increases with an increase in the hole width.

The semiconductor device according to the third embodiment can be manufactured in the same method as the semiconductor device according to the first embodiment except that the first hole21is formed into a rectangular shape.

A semiconductor device according to fourth embodiment of the present invention is described below with reference toFIG. 10.FIG. 10is a diagram illustrating a cross-sectional perspective view of the semiconductor device. A difference between the first embodiment and the fourth embodiment is as follows.

In the first embodiment, as shown inFIG. 1, the second region2is located around the first region1so that the first region1can be surrounded by the second region2. In contrast, in the fourth embodiment, as shown inFIG. 10, the first region1is located around the second region2so that the second region2can be surrounded by the first region1.

That is, the first region1, where the blind holes20are formed, is located outside the second region2, where the through holes30are formed. The first and second conductors40,60in the blind hole20and the through hole30are configured in the same manner as the first embodiment.

That is, the first conductor40in the blind hole20is drawn to the surface-side ground terminal81on the front surface11of the semiconductor substrate10and electrically connected through the front surface11to the first conductor40in the through hole30. The first conductor40in the through hole30is drawn through the back-surface side connection layer75on the back surface12to the back-surface side ground terminal82.

The second conductor60in the blind hole20is drawn to the front surface-side ground terminal71on the front surface11of the semiconductor substrate10and electrically connected through the front surface11to the second conductor60in the through hole30. The second conductor60in the through hole30is drawn to the back-surface side signal terminal72on the back surface12.

Thus, according to the fourth embodiment, the first conductor40in the blind hole20is drawn to each of the front surface11and the back surface12through the first conductor40in the through hole30and connected to each of the front-surface side ground terminal81and the back-surface side ground terminal82. Likewise, the second conductor60in the blind hole20is drawn to each of the front surface11and the back surface12through the second conductor60in the through hole30and connected to each of the front-surface side signal terminal71and the back-surface side signal terminal72.

The semiconductor device according to the fourth embodiment can be manufactured in the same method as the semiconductor device according to the first embodiment except that a relative position between the first hole21and the second hole31is reversed.

In an example shown inFIG. 10, the blind hole20is circular. The blind hole20can have a shape other than a circular shape. For example, the blind hole20can have a hexagonal shape of the second embodiment or a rectangular shape of the third embodiment.

A semiconductor device according to a fifth embodiment of the present invention is described below with reference toFIG. 11.FIG. 11is a diagram illustrating a cross-sectional perspective view of the semiconductor device. A difference between the first embodiment and the fifth embodiment is the shape of the blind hole20.

In the first embodiment, as shown inFIG. 2, the blind holes20are independently arranged in the first region1of the semiconductor substrate10without overlapping each other.

In contrast, in the fifth embodiment, as shown inFIG. 11, the blind holes20are arranged in a concentric pattern. One blind hole20is located in the center of the concentric pattern, and the other blind holes20are located around the center blind hole20.

In an example shown inFIG. 11, the center blind hole20has a circular shape. Alternatively, the center blind hole20can have a ring shape. Each of the other blind holes20located around the center blind hole20has a ring shape, and the other blind holes20are arranged with one inside the other. The width of each blind hole20is less than the width of the through hole30.

Like the first embodiment, in each blind hole20, the first conductor40, the insulator50, and the second conductor60are stacked in this order from the inner surface of the blind hole20to the center of the blind hole20to form a sandwich structure.

The sandwich structure continuously extends between all the blind holes20through the front surface11of the semiconductor substrate10to form the capacitance section.

As described above, according to the fifth embodiment, the blind holes20are arranged in a concentric pattern like the annual rings of a tree trunk. In such an approach, the area between the first and second conductors40,60can be increased. Thus, the capacitance of the capacitor section can be increased.

FIG. 12illustrates a semiconductor device according to a modification of the fifth embodiment.FIG. 11is a diagram illustrating a cross-sectional perspective view of the semiconductor device.

Like the fourth embodiment, according to the modification of the fifth embodiment, the first region1, where the blind holes20are formed, is located outside the second region2, where the through holes30are formed.

In an example shown inFIG. 12, each blind hole20has a ring shape, and the through hole30has a circular shape. The blind holes20and the through hole30are arranged in a concentric pattern in such a manner that the through hole30is located in the center of the concentric pattern and that the blind holes20are located around the through hole30with one inside the other.

The semiconductor device according to the fifth embodiment can be manufactured in the same method as the semiconductor device according to the first embodiment except the arrangement and shape of the first hole21.

A semiconductor device according to a sixth embodiment of the present invention is described below with reference toFIG. 13.FIG. 13is a diagram illustrating a cross-sectional view of the semiconductor device. The semiconductor device shown inFIG. 13is formed by stacking two semiconductor devices, each of which is shown inFIG. 1, on top of each other.

Specifically, the back-surface side signal terminal72and the back-surface side ground terminal82of one semiconductor device are electrically connected to the front-surface side signal terminal71and the surface-side ground terminal81of the other semiconductor device, respectively. In such an approach, the capacitance of the capacitance section can be increased. It is noted that three or more semiconductor devices can be stacked.

A semiconductor device according to a seventh embodiment of the present invention is described below with reference toFIGS. 14 and 15. As can be seen fromFIGS. 14 and 15, two electrode portions B, C are formed in a single semiconductor substrate10.

The first electrode portion B is configured as a signal input electrode, and the second electrode portion C is configured as a signal output electrode. As shown inFIG. 15, each of the first electrode portion B and the second electrode portion C is configured in almost the same manner as the electrode portion of the first embodiment. According to the seventh embodiment, the semiconductor device further has an insulation securing film100and an electrode connection film101on the back surface12side of the semiconductor substrate10.

Like the insulator50, the insulation securing film100is made of silicon oxide and covers the back-surface side ground terminal82.

The electrode connection film101is made of metal. For example, the electrode connection film101can be made of the same metal as the first and second conductors40,60. The electrode connection film101connects the back-surface side signal terminal72of the first electrode portion B to the back-surface side signal terminal72of the second electrode portion C. The electrode connection film101is electrically insulated by the insulation securing film100from the back-surface side ground terminal82of each of the first electrode portion B and the second electrode portion C.

As described above, according to the seventh embodiment, the back-surface side signal terminals72of the first electrode portion B and the second electrode portion C are electrically connected together by the electrode connection film101. In such an approach, connection is performed on only the first surface11of the semiconductor substrate10. Thus, there is no need to draw the electrode to the back surface12of the semiconductor substrate10. Specifically, the signal inputted to the front-surface side signal terminal71of the first electrode portion B is outputted from the front-surface side signal terminal71of the second electrode portion C.

The embodiments described above can be modified in various ways, for example, as follows.

In the embodiments, the sandwich structure extending between the blind holes20, between the blind hole20and the through hole30, and between the through holes30has a sheet shape. The sandwich structure can have a shape other than a sheet shape. For example, the sandwich structure can have a line (i.e., strip) shape.

In the embodiments, the back-surface side connection layer75extending between the through holes30has a sheet shape. The back-surface side connection layer75can have a shape other than a sheet shape. For example, the back-surface side connection layer75can have a line (i.e., strip) shape.

That is, the shapes of the conductors, the insulator, the layers on the front surface11and the back surface12of the semiconductor substrate10is not limited to those of the embodiments.

In the embodiments, the first and second conductors40,60extend between the blind hole20and the through hole30through the front surface11of the semiconductor substrate10. Alternatively, the first and second conductors40,60extend between the blind hole20and the through hole30inside the semiconductor substrate10. For example, the semiconductor substrate10can have a communication hole that is located inside the semiconductor substrate10and extends between the blind hole20and the through hole30. In this case, the first and second conductors40,60can extend between the blind hole20and the through hole30inside the semiconductor substrate10through the communication path.