Ultra-thin oxide for semiconductors

A semiconductor device having a transistor or capacitor with an ultra-thin oxide, which is thinner than 10 angstrom in thickness, is manufactured by eliminating a gate oxidation step in the processing and using the polysilicon reoxidation step to create the ultra-thin gate oxide by diffusion after formation of the gate.

TECHNICAL FIELD 
The present invention relates generally to semiconductors and more 
specifically to thin oxides for sub-100 nanometer semiconductors. 
BACKGROUND ART 
In the past, as semiconductor devices were scaled down in size, thinner and 
thinner oxides were required for proper operation of the smaller and 
smaller transistors. The reductions in oxide thickness were achieved by 
reduction in oxidation time, decreases in oxidation temperature, and 
decreases in oxygen flow or concentration during processing of the 
semiconductor wafer. 
This approach has been successful as the semiconductor devices were scaled 
down from micron to submicron levels. As the semiconductor devices are 
scaled down to the sub-100 nanometer range, even thinner oxides are 
required and it is apparent that there are limits to how much the 
oxidation time can be reduced, the oxidation temperature decreased, and 
the oxygen flow decreased. 
At one minute of oxidation time, a maximum oxidation temperature of 
800.degree. C., and low oxygen flow, which are the practical limits of the 
various parameters, the theoretical limit of the thinnest oxide is still 
greater than 10 angstrom. Further reductions in time, increases in 
temperature, or reductions in oxygen flow eliminate manufacturing 
reproducibility and make the oxide thickness undependable. 
Thus, there appear to be practical limits on the ability to scale down 
semiconductor devices using the conventional approach. 
For sub-100 nanometer semiconductor devices, it is absolutely necessary 
that the transistor gate oxide thickness be below 10 angstroms in 
thickness. And there is apparently no way of reaching this thickness. 
DISCLOSURE OF THE INVENTION 
The present invention further provides an ultra-thin oxide in a 
semiconductor device by eliminating the gate oxide deposition and relying 
on the former polysilicon reoxidation step to create the gate oxide. 
The present invention provides a semiconductor device having a transistor 
or capacitor with an ultra-thin oxide which is thinner than 10 angstroms 
in thickness manufactured by eliminating a gate oxide step in the 
processing and using the polysilicon reoxidation step to create the 
ultra-thin gate oxide after formation of the gate. 
An advantage of the present invention is to provide a simplification to the 
process of manufacturing semiconductors.

BEST MODE FOR CARRYING OUT THE INVENTION 
Referring now to FIG. 1 (PRIOR ART), therein is shown a prior art silicon 
substrate 10 which has been cleaned. It should be understood that, 
although the silicon has been cleaned, there will be residual oxides on 
the surface of the silicon substrate 10. 
Referring now to FIG. 2 (PRIOR ART), therein is shown the prior art silicon 
substrate 10 having grown thereon an oxide 12. The oxide 12 of silicon 
dioxide is generally grown as thinly as possible which in the prior art 
was thicker than 15 angstroms. 
Referring now to FIG. 3 (PRIOR ART), therein is shown the prior art silicon 
substrate 10 and the oxide 12 having prior art polysilicon 14 deposited on 
the oxide 12. 
Referring now to FIG. 4 (PRIOR ART), therein is shown the prior art gate 
mask formed of photoresist 16. The photoresist 16 has been patterned and 
etched in a conventional photolithographic process to form the gate mask 
which is the remaining photoresist 16. 
Referring now to FIG. 5 (PRIOR ART), therein is shown the prior art 
semiconductor after gate etching. The gate etching has converted the 
polysilicon 14 into the polysilicon gate 18, and the oxide 12 into gate 
oxide 20. 
Referring now to FIG. 6 (PRIOR ART), therein is shown the prior art 
semiconductor after the photoresist 16 has been removed and after 
polysilicon reoxidation which lays down an oxide 22 on to the silicon 
substrate 10 in preparation for other steps in the manufacturing process. 
Referring now to FIG. 7 (PRIOR ART), therein is shown the finished prior 
art transistor having the polysilicon gate 18 and the gate oxide 20 of 
thicker than 15 angstroms thickness disposed over the silicon substrate 10 
with two subsequently implanted source and drain regions 24 and 26. It 
should be understood that the above processing is also used to manufacture 
semiconductor capacitors with the oxide as the dielectric. 
Referring now to FIG. 8 through FIG. 13, it should be noted that they have 
been placed side by side with certain of the prior art figures, FIG. 1 
(PRIOR ART) and FIG. 3 (PRIOR ART) through FIG. 7 (PRIOR ART), to show 
that the same process step is being performed in both figures. The same 
numbers are used to refer to the same portions except that the portions of 
the present invention are designated by prime symbols. 
Referring now to FIG. 8, therein is shown a silicon substrate 10' which has 
been cleaned through conventional preprocessing. Again, it should be 
understood that, although the silicon has been cleaned, there will be 
residual oxides on the surface of the silicon substrate 10'. 
Before referring to FIG. 9, it should be noted that there is no figure side 
by side with FIG. 2 because this step has been eliminated in the present 
invention. 
Referring now to FIG. 9, therein is shown the silicon substrate 10' having 
polysilicon 14' deposited directly on the silicon substrate 10'. 
Referring now to FIG. 10, therein is shown the gate mask formed of 
photoresist 16'. The photoresist 16' has been patterned and etched in a 
conventional photolithographic process to form the gate mask which is the 
remaining photoresist 16'. 
Referring now to FIG. 11, therein is shown the semiconductor after gate 
etching. The gate etching has converted the polysilicon 14' into the 
polysilicon gate 18'. 
Referring now to FIG. 12, therein is shown the semiconductor after the 
photoresist 16' has been removed and after polysilicon reoxidation which 
lays down an oxide 22' on to the silicon substrate 10' in preparation for 
other steps in the manufacturing process. It should be noted that the 
residual oxide on the surface of the silicon substrate assists the oxide 
22' to diffuse under the polysilicon gate 18' in an ultra-thin film of 
less than 10 angstroms thickness. 
Referring now to FIG. 13, therein is shown the finished transistor having 
the polysilicon gate 18' and the ultra-thin gate oxide 20' disposed over 
the silicon substrate 10' with two subsequently implanted source and drain 
regions 24' and 26'. 
The prior art processing starts with various preprocessing steps to arrive 
at the silicon substrate 10 shown in FIG. 1 (PRIOR ART) which is cleaned 
of contaminants. Since silicon is so reactive with oxygen, it is known 
that there will be residual oxides on the surface of the silicon which 
will not be removed. 
The silicon substrate 10 will be subject to a thermal oxidation process in 
a quartz furnace where a flow of dry oxygen or an oxygen-argon mixture 
converts the silicon to silicon dioxide. It is understood by those skilled 
in the art that there is a region of silicon and silicon dioxide rather 
than the line shown in the figures but that there are well known ways of 
measuring the thickness of the oxide 12. The furnace will be at a constant 
temperature below 800.degree. C. and brought up to 800.degree. C. for 60 
seconds and cooled down in order to create the silicon dioxide oxide 12. 
It is also understood by those skilled in the art that the oxide thickness 
is related to the amount of oxygen, the flow speed of the oxygen, and the 
pressure that the oxygen is under. With less oxygen, slower flow, or less 
oxygen pressure, the oxide layer will be thinner. The precise 
relationships are well known in the art. 
It is generally recognized that higher oxidation temperatures mean that the 
silicon dioxide will be of greater density and thus have a higher 
dielectric strength. However, higher temperatures result in thicker 
depositions of oxide with all other conditions remaining the same. 
Next, the prior art has the deposition of polysilicon 14 on top of the 
oxide 12. The polysilicon 14 is polycrystalline silicon which is silicon 
with only a short-range crystal structure. This generally done in a 
chemical vapor deposition (CVD) process which is controlled to provide the 
thickness desired for the transistor gate. 
Once the polysilicon 14 is laid down, the photoresist 16 placed on top of 
the polysilicon 14. The photoresist 16 is patterned and exposed to light 
in a conventional photolithographic process and hardened. The soft 
photoresist 16 is then etched away to leave the hard photoresist 16 over 
the desired gate area. 
The polysilicon 14 and the oxide 12 are then subject to a conventional 
anisotropic etch which forms the polysilicon gate 18 and the gate oxide 20 
as shown in FIG. 5 (PRIOR ART) by etching down to the silicon substrate 
10. The photoresist 16 is subsequently removed. 
Next, a polysilicon reoxidation is performed in the quartz furnace where a 
flow of dry oxygen or an oxygen-argon mixture converts the silicon to 
silicon dioxide. The furnace will be at a constant temperature below 
900.degree. C. and brought up to 900.degree. C. for between 30 to 100 
minutes and cooled down in order to create a 100 angstrom thick silicon 
dioxide oxide 22. Since the oxide 22 thickness is not as critical as the 
gate oxide 20 thickness, the parameters are much less critical so the 
temperature can be as low as 800.degree. C. and as high as 1000.degree. C. 
and the time can be anything less than around 100 minutes. 
This polysilicon reoxidation is performed as preprocessing to the formation 
of the subsequently implanted source and drain regions 24 and 26. 
After further processing, the prior art transistor as shown in FIG. 7 
(PRIOR ART) is formed. 
The present invention processing starts with the same preprocessing steps 
as the prior art to arrive at the silicon substrate 10' shown in FIG. 8 
which is cleaned of contaminants. There will be 1 to 2 angstroms of 
residual oxides on the surface of the silicon which will not be removed. 
The silicon substrate 10' will be not be subject to a thermal oxidation 
process at this step. Instead, the polysilicon 14' is deposited directly 
on top of the residual oxides on the silicon substrate 10' by CVD. This 
leaves the residual oxide sandwiched between the polysilicon 14' and the 
silicon substrate 10'. 
Once the polysilicon 14' is laid down, the photoresist 16' placed on top of 
the polysilicon 14'. The photoresist 16' is patterned and exposed to light 
in a conventional photolithographic process and hardened. The soft 
photoresist 16' is then etched away to leave the hard photoresist 16' over 
the desired gate area. 
The polysilicon 14' is then subject to an anisotropic etch which forms the 
polysilicon gate 18' but without the gate oxide 20' in place. This is 
shown in FIG. 11. The photoresist 16' is subsequently removed. 
The polysilicon reoxidation is performed at this step. The polysilicon 
reoxidation can be at higher temperatures and over longer periods of time 
which allows the residue of surface oxide to be the precursor for 
diffusion of oxygen and silicon dioxide between the polysilicon 14' and 
the silicon substrate 10'. This is shown in FIG. 11. 
Simulations have shown that a polysilicon reoxidation at 900.degree. C. and 
40 minutes will grow a gate oxide 20' of approximately 2 angstroms thick. 
This would indicate that extremely close control of gate oxide 20' 
thickness is possible since the oxidation time could be in the range of 30 
to 100 minutes. 
After further processing, the transistor of the present invention as shown 
in FIG. 13 is formed. As would be evident to those skilled in the art, 
this approach could be used to provide the thinner dielectric required for 
other scaled semiconductor components. For example, the gate 18' would be 
one plate of a capacitor having an implanted substrate as the other and 
the gate oxide 20' as the dielectric. 
While the invention has been described in conjunction with a specific best 
mode, it is to be understood that many alternatives, modifications, and 
variations will be apparent to those skilled in the art in light of the 
aforegoing description. Accordingly, it is intended to embrace all such 
alternatives, modifications, and variations which fall within the spirit 
and scope of the appended claims. All matters set forth herein or shown in 
the accompanying drawings are to be interpreted in an illustrative and 
non-limiting sense.