Nonvolatile memory device having cell and peripheral regions and method of making the same

A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

PRIORITY STATEMENT

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0030468, filed on Mar. 28, 2007, in the Korean Intellectual Property Office (KIPO), the entire contents of which are herein incorporated by reference.

BACKGROUND

Example embodiments relate to a nonvolatile semiconductor memory device and a method of making the same. Other example embodiments relate to a nonvolatile semiconductor memory device wherein characteristics of a memory cell and a peripheral cell may be optimized or improved and a method of making the same.

2. Description of the Related Art

Nonvolatile semiconductor memory devices may be capable of storing data even after an external power supply is removed. To achieve this function, nonvolatile devices may be supplied with a floating layer upon which charges may be stored or removed depending on a program or erase status of the device. Two types of such floating layer devices may include a floating gate type device and a floating trap type device.

A floating gate type device may include a conductive gate layer that floats due to its isolation by a surrounding insulating layer. The floating gate may be isolated from a substrate channel below and from a control gate above. The floating gate type device may be respectively programmed and erased by storing and removing charges as free carriers on the conductive floating gate. A floating trap type device may include a non-conductive layer that may be floating between a substrate channel and a control gate. The floating trap type device may be programmed and erased by storing and removing charges in traps in the non-conductive floating layer.

A known type of floating trap type device may be a silicon-oxide-nitride-oxide-semiconductor (SONOS) device. A SONOS device may include a tunneling insulating layer on a substrate, a charge storage layer on the tunneling layer, a blocking insulating layer on the charge storage layer and a gate electrode on the blocking layer. The substrate may include a P-type silicon substrate having N-type impurity layers formed on either side of the gate electrode as a source and drain. Thermal oxide may be used to form the tunneling layer and silicon nitride may be used as the charge storage layer. During operation, charges may be moved to and from the charge storage layer from and to the substrate in order to program and erase the memory cell.

To address certain shortcomings of SONOS technology, a floating trap type memory device including a metal (e.g. tantalum) layer, a high-k dielectric (e.g. aluminum oxide) layer, and a nitride-oxide-semiconductor layered structure (TANOS) has been introduced. In a TANOS device, a gate may be made of a metal, for example tantalum, and a blocking layer may be made of a high-k dielectric material, for example, aluminum oxide. The use of a high-k dielectric material as a blocking layer may be a significant feature of the TANOS architecture. Additional features of a TANOS device may include a high work function layer and a barrier metal layer as part of the gate electrode structure. TANOS technology may be disclosed in U.S. Pat. No. 6,858,906, and various additional TANOS related technologies have been proposed, for example in U.S. Patent Application Publications 2004/0169238 and 2006/0180851, the entire disclosures of all of which are hereby incorporated by reference. Efforts towards improving the performance and function of the TANOS technology and optimizing or improving the architecture of the TANOS device, including its gate structure, are continuing.

Along with the floating trap type memory cells, e.g., a TANOS cell, a nonvolatile memory device may also be formed having peripheral regions. The peripheral regions may include various devices, e.g., MOS transistors, which may be used for programming, erasing and otherwise controlling the memory cells. Typically, the MOS transistors of the peripheral region have gate electrodes formed of a silicon material, e.g., doped poly-silicon.

As the demand for capacity of such nonvolatile memories increases, a line width of patterns used to form the transistors may be decreasing. The reduction in line widths correlates to an increase in the resistance of the conductive patterns, e.g., the gate electrodes of the peripheral transistors, and causes a corresponding increase in the resistance-capacitance (RC) delay. For example, if a line width of a transistor's gate electrode may be decreased and its resistance increased, an RC delay associated with the transistor may be increased, thus causing an increased operating time of the transistor and its corresponding circuit.

One proposed method to address the increased resistance is to include a material having a decreased resistivity as part of the peripheral gate electrode, e.g., tungsten (W). Compared to doped poly-silicon which has a resistivity of about 10−5Ω-m, tungsten has a resistivity of about 5.5×10−8Ω-m which may be several orders of magnitude less than that of doped poly-silicon. Therefore, the line widths of the peripheral devices may be decreased without an increase in RC delay. Moreover, a processing convenience is provided in that a relatively high conductivity metal, e.g., tungsten or tantalum, used in a TANOS cell may also be used in forming the peripheral cell.

However, in a peripheral MOS transistor, tungsten and other relatively low resistivity metals may react and diffuse with underlying layers, e.g., poly-silicon, and may cause deterioration of the transistor's reliability. To address this concern, a barrier metal layer may be placed between the tungsten layer and underlying poly-silicon layer. Generally, a metal nitride may be used as the barrier metal to prevent or retard reaction and diffusion of tungsten. Using the barrier metal layer may provide another processing convenience because a same barrier metal used in the TANOS process may be used in forming the peripheral transistors. However, the use of the metal nitride layer between the tungsten and poly-silicon layers may cause an increase in the interface resistance between the poly-silicon and the tungsten. Because the interface resistance may be increased, a program voltage pulse may not be sufficient for programming the memory cell and the RC delay may again be increased.

In a conventional TANOS memory circuit having a peripheral region, a relatively low resistivity metal layer used in the TANOS memory cell may also be used as an overlying layer in the peripheral transistor. For example, in the peripheral region, the relatively low resistivity layer may overlay a poly-silicon gate layer so as to lower the gate resistance. However, use of the relatively low resistivity metal layer may require that a barrier metal layer be used to avoid reaction and/or diffusion. Unfortunately, the use of the barrier metal layer may cause an increase in the interface resistance, thereby causing a voltage drop and potential failure to generate an appropriate level of program voltage pulse.

SUMMARY

Example embodiments may address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below. Accordingly, example embodiments may provide a nonvolatile memory device and method for making a nonvolatile memory device in which characteristics of both a memory cell and a peripheral cell may be optimized or improved. Example embodiments provide a process for integrating an optimized or improved TANOS cell in a memory region with an optimized or improved transistor in a peripheral region by an optimized or improved gate forming process.

In accordance with example embodiments, a nonvolatile memory device may be provided. The memory device may include a semiconductor substrate having a cell region and a peripheral region. A cell gate may be in the cell region and the cell gate may include a tunnel insulating layer on the semiconductor substrate, a charge storage insulating layer on the tunnel insulating layer, a blocking insulating layer on the charge storage insulating layer and a low resistance layer, having a first resistivity, above the blocking layer. A peripheral gate may be in the peripheral region and the peripheral gate may include a gate insulating layer on the semiconductor substrate, a lower gate electrode on the gate insulating layer, and an upper gate electrode, having a second resistivity, on the lower gate electrode, wherein the second resistivity may be greater than the first resistivity.

In accordance with example embodiments, the low resistance layer may have a first thickness, and the upper gate electrode may have a second thickness, wherein the second thickness may be greater than the first thickness.

In accordance with example embodiments, a method of manufacturing a nonvolatile memory device may be provided. The method may include forming a semiconductor substrate having a cell region and a peripheral region, and forming a cell gate in the cell region and a peripheral gate in the peripheral region, wherein forming the cell gate may include forming a tunnel insulating layer on the semiconductor substrate, a charge storage insulating layer on the tunnel insulating layer, a blocking insulating layer on the charge storage insulating layer and a low resistance layer, having a first resistivity, above the blocking insulating layer, and forming the peripheral circuit gate may include forming a gate insulating layer on the semiconductor substrate, a lower gate electrode on the gate insulating layer, and an upper gate electrode, having a second resistivity, on the lower gate electrode, wherein the second resistivity may be greater than the first resistivity.

In accordance with example embodiments, the method may include forming the low resistance layer to have a first thickness, and the upper gate electrode to have a second thickness, wherein the second thickness may be greater than the first thickness.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

The following description with reference to the accompanying drawings may be provided to assist in a comprehensive understanding of example embodiments as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely examples. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of example embodiments. Also, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

Hereinafter, example embodiments will be described in detail with reference to the attached drawings. Reference now should be made to the drawings, in which the same reference numerals are used throughout the different drawings to designate the same or similar components. In the drawings, the thicknesses and widths of layers are exaggerated for clarity. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art.

In example embodiments, a conventional overlying metal layer may be replaced by a metal silicide layer in peripheral region transistor such that the barrier metal layer may no longer be required. Because the metal silicide layer for structuring the gate in the peripheral region has a resistance greater than that of the metal layer, the metal silicide layer may be formed to have a thickness greater than that of the low resistivity metal layer. Accordingly, example embodiments concurrently provide a TANOS memory cell transistor and a peripheral cell transistor, wherein characteristics of both transistors may be optimized or improved.

FIG. 1is a plan view illustrating a nonvolatile memory device according to example embodiments. As illustrated inFIG. 1, a device may be formed in a substrate100. The substrate100may include a single crystal silicon layer, a poly-silicon layer, a silicon-on-insulator (SOI) substrate, and/or a silicon on silicon-germanium (SiGe) substrate. Formed in the substrate100may be a region “c” which may include a cell region and a region “p” which may include a peripheral region. Furthermore, the peripheral region “p” may include a high voltage region “pH” and a low voltage region “pL”. The cell region and the peripheral region may include a plurality of active areas106, e.g.106c,106pHand106pL. As illustrated inFIG. 1, the active areas106cof the cell region may be formed to extend in a first direction and formed generally in parallel to one another. Similarly, low voltage active area106pLand high voltage active area106pHmay be formed parallel to each other and may be formed parallel to other low and high voltage active areas and the cell active areas. The low and high voltage active areas may also be formed in different configurations as the circuit requirements or other layout constraints may dictate. The active areas106c,106pL, and106pHmay have their boundaries defined by a device isolation layer102. In example embodiments, the device isolation layer102may be a shallow trench isolation layer. However, a deep trench isolation layer or a field oxide layer may also be used.

The cell region “c” may include a Common Source Line (CSL) and bitline plugs DC separated from each other by a distance. The CSL may extend across the active areas106cin a second direction, which may be generally orthogonal to the first direction. The CSL may be a conductive structure that contacts underlying active areas106c. The bitline plugs DC, while being electrically discontinuous with each other, may be generally formed to extend in a line that may be parallel to the CSL in the second direction. A String Selection Line (SSL) and a Ground Selection Line (GSL) may be formed generally in parallel with each other and generally in parallel with the CSL and bitline plugs DC. The SSL and GSL may extend in the second direction over the active areas106cbetween the CSL and bitline plugs DC. The SSL may be adjacent to the bitline plugs DC while the GSL may be adjacent the CSL. It should be understood that the terms CSL, SSL and GSL may be merely labels which do not imply specific functionality or arrangement to the respective structures.

A plurality of word lines WL, e.g. WL1-WLN, may be formed between and generally parallel to the SSL and GSL to extend in the second direction across the active areas106c. The word lines may include a floating trap structure that may store charges and may be a part of the nonvolatile memory structure which may be used for programming the device. The cell region “c” may also include a bit line104which generally run in the first direction and, as illustrated inFIG. 1, may be formed so as to shadow the active areas106c. The bit line104may make contact to underlying active areas through corresponding bit line plugs DC.

The peripheral region “p” may include the low voltage region “pL” and the high voltage region “pH”. The low voltage region and the high voltage region may be formed to accommodate various devices, e.g., transistors, which may be used to program, erase and otherwise control the memory cell transistors of region “c”. The low and high voltage regions pLand pHmay include active areas106pLand106pH, respectively. The active areas106pLand106pHmay be defined by isolation layer102. As illustrated, the low voltage region may include a gate electrode230pLand the high voltage region may similarly include a gate electrode230pH.

FIG. 2illustrates a non-volatile memory device according to example embodiments.FIG. 2is a cross-sectional view taken along lines IIc-IIc′, IIpL-IIpL′ and IIpH-IIpH′ ofFIG. 1. In cell region “c”, each cell gate, corresponding to one of WL1-WLN, may include a layered insulating structure210as a floating trap structure and a layered conducting structure220as a control gate. The cell gates may further include a hard mask layer240. In example embodiments as illustrated inFIG. 2, the layered insulating structure210may extend under and between each of the plurality of cell gates WL. The SSL gates, as well as the GSL gates which may not be shown inFIG. 2, may be similar in structure to the cell gates WL. For example, the SSL and GSL gates may include the layered insulating structure210as a dielectric layer as well as the layered conducting structure220as a gate electrode and the layered insulating structure210may extend under and between the SSL and GSL gates. As further illustrated inFIG. 2, the insulating structure210may extend from under the SSL gate to the bitline contact DC and may similarly extend from under the GSL to the CSL, though not shown in the figure.

Cell spacers251c, which may include a single or multi-layered structure of, for example, silicon oxide, silicon nitride and/or a low dielectric material, may be formed on either side of the cell gates (WL) as well as the SSL and GSL gates. The cell spacers251cmay extend from an upper portion of the gates, for example, the top of the gates, to a location above the layered insulating structure210. An interlayer dielectric260may be formed to generally cover the nonvolatile device. The interlayer dielectric may include a single or multi-layered structure, for example, a silicon oxide layer, a silicon nitride layer, a polymer layer, and/or a low dielectric layer. A bit line104may be formed overlying the interlayer dielectric260and may make contact to an underlying active area through bit line plug DC. As illustrated, the bitline plug DC may penetrate through the interlayer dielectric260.

Impurity layers202cmay be formed in active areas106cto form source/drain regions and contact regions. More specifically, impurity layers202cmay be formed on either side of the SSLs and WLs and under the bitline contact DC as illustrated and may be formed on either side of the GSL as well as under the CSL though not shown. In conjunction with associated gates of the WL, SSL and GSL, the impurity layers202cmay form transistors. Impurity layers202cmay also form contact regions in conjunction with an overlying bitline contact DC and the CSL. The impurity layers202cmay have different structures depending on their use with the WL, SSL, GSL, CSL, and bitline contact. For example, the impurity regions may have different doping concentration levels, different depths or widths and different impurity types depending on the needs of the associated transistor or contact region.

The layered insulating structure210may include a tunnel insulating layer212, a charge storage insulating layer214and a blocking insulating layer216. The tunnel insulating layer212may be formed above the substrate100and may include one or more layers of, for example, silicon oxide, silicon oxynitride (SiON), silicon nitride, a silicon oxide layer having a nitride portion, aluminum oxide (Al2O3), hafnium aluminate (HfAlO), hafnium aluminum oxynitride (HfAlON), hafnium silicate (HfSiO) and hafnium silicon oxynitride (HfSiON).

The charge storage insulating layer214may be formed above the tunnel insulating layer and may be used to trap or store charges for use in programming each cell gate WL. The charge storage insulating layer214may include one or more layers of, for example, poly-silicon, silicon nitride, silicon oxynitride, silicon rich oxide, ferroelectric materials, nano-crystalline silicon, nano-crystalline silicon germanium, nano-crystalline metal, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium aluminate (HfAlO), hafnium aluminum oxynitride (HfAlON), hafnium silicate (HfSiO) and/or hafnium silicon oxynitride (HfSiON). The charge storage insulating layer214may include a quantum-dot layer. For example, charge storage insulating layer214may include a layer of silicon, germanium, and/or metal quantum-dots.

The blocking insulating layer216may be formed above the charge storage insulating layer214and may have a dielectric constant greater than that of the tunnel insulating layer212. The blocking insulating layer216may include a metallic oxide or a metallic oxynitride of a Group III element or a Group VB element. According to other example embodiments, the blocking insulating layer216may include a doped metal oxide or a doped metal oxynitride in which the metal oxide may be doped with a Group IV element. The Group IV element may reduce leakage current from the memory cell. The Group IV element may be doped in the metal oxide to about 0.1 to about 30 weight percent. The blocking insulating layer216may include one or more layers of, for example, silicon oxide, silicon oxynitride (SiON), silicon nitride, and metallic oxide, e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium aluminate (Hf1-xAlxOy) hafnium aluminum oxynitride (HfAlON), hafnium silicate (HfxSi1-xO2), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrxSi1-xO2), and/or zirconium silicon oxynitride (ZrSiON).

The material Al2O3may have a dielectric constant of about 10 and an energy band gap of about 8.3 eV and the material ZrO2may have a dielectric constant of about 25 and an energy band gap of about 8.3 eV. The blocking insulating layer216may also comprise one or more layers of AlO, Ta2O5, TiO2, PZT[(Pb(Zr, Ti)O3)), PbTiO3, PbZrO3, PLZT[(Pb,La)(Zr, TiO3)], PbO, SrTiO3, BaTiO3, V2O5, BST[(Ba,Sr)TiO3], SBT(SrBi2Ta2O9), Bi4Ti3O12, and combinations thereof.

In example embodiments, the blocking insulating layer216may include a layer similar to that of the charge storage insulating layer214. For example, both the blocking insulating layer216and the charge storage insulating layer214may include a layer of hafnium aluminate (HfAlO), hafnium aluminum oxynitride (HfAlON), hafnium silicate (HfSiO) and/or hafnium silicon oxynitride (HfSiON). In such a case, a relative stoichiometric amount of hafnium in the charge storage insulating layer214may be higher than the relative stoichiometric amount of hafnium in the blocking insulating layer216so as to increase a trap density in the charge storage insulating layer214and to enhance an insulation characteristic of the blocking insulating layer216.

In example embodiments, the blocking insulating layer216may have a dielectric constant higher than that of the tunnel insulating layer212. For example, the blocking insulating layer216may include at least one layer of material having a dielectric constant that may be higher than any layer included in the tunnel insulating layer212. In example embodiments, the blocking insulating layer216and the tunnel insulating layer212may be formed of materials having substantially similar dielectric constants, for example, they may be formed of the same material. In that case, the blocking insulating layer216may have a thickness that may be greater than a thickness of the tunnel insulating layer212.

The layered conducting structure220may include an energy barrier layer222, a barrier metal layer224and a low resistance layer226. The energy barrier layer222may be formed above the blocking insulating layer216and may include a metal having a work function greater than about 4 eV. For example, the energy barrier layer222may include one or more layers of, for example, tantalum (Ta), tantalum nitride (TaN), tantalum titanium (TaTi), tantalum platinum (TaPt), tantalum silicon nitride (TaSiN), titanium (Ti), titanium nitride (TiN), titanium aluminide (Ti3Al), titanium aluminum nitride (Ti2AlN), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), molybdenum (Mo), molybdenum nitride (Mo2N), ruthenium (Ru), ruthenium dioxide (RuO2) nickel silicide (NiSi), palladium (Pd), iridium (Ir), platinum (Pt), cobalt (Co), cobalt silicide (CoSi) and/or aluminum silicide (AlSi).

The barrier metal layer224may be formed above the energy barrier layer222. The barrier metal layer224may be formed of a material that reduces or prevents an interfacial reaction and/or mutual diffusion between the blocking insulating layer216or energy barrier layer222and the low resistance layer226. The barrier metal layer224may include one or more layers of, for example, tungsten nitride (WN), tungsten silicon nitride (WSiN) titanium nitride (TiN) or any other metal nitride that aides in preventing or reducing an interfacial reaction and/or mutual diffusion.

The low resistance layer226may be formed above the barrier metal layer224. The low resistance layer may include one or more layers of, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), molybdenum (Mo), titanium (Ti), platinum (Pt), palladium (Pd) and other low resistance materials.

According to example embodiments, forming the cell region “c” provides optimization or improvement of certain characteristics of the cell gates WL. For example, the layered insulating structure210may be configured such that the blocking insulating layer216has a higher dielectric constant than that of the tunnel insulating layer212. Accordingly, when a cell gate WL may be programmed, a higher electric field intensity may be provided for the tunnel insulating layer212as compared to the electric field intensity provided for the blocking insulating layer216. Therefore, electrons may be more easily injected through the tunnel insulating layer212from the substrate100as compared to holes from the layered conducting structure220, which will result in faster programming of the cell gate WL. Similarly, the relative dielectric constants will provide for faster erase times. Similar results may be obtained, and the characteristics optimized or improved, if the tunnel insulating layer212and the blocking insulating layer216may be formed of the same material or formed to have substantially the same dielectric constant but the blocking insulating layer may be made thicker than the tunnel insulating layer212.

Furthermore, characteristics of the cell gate WL may be optimized or improved by the layered conducting structure220. For example, the energy barrier layer222may be provided by using a material having a work function greater than about 4 eV which may be the work function of N-type poly-silicon. By using an energy barrier layer with a higher work function, it becomes more difficult for electrons to move from the low resistance layer226to the charge storage insulating layer214. Accordingly, during an erase process of the cell gate WL, while holes in the substrate100may be tunneling through the tunnel insulating layer212into the charge storage insulating layer214as desired, an amount of electrons tunneling from the low resistance layer226to the charge storage insulating layer214may be lowered. Accordingly, an erase process may become faster.

The cell gate WL may also be optimized or improved by using a low resistance layer226formed of a material, e.g., tungsten. Because tungsten has a lower resistivity than, for example, poly-silicon, the resistance of the cell gate WL may be reduced and therefore RC delays may similarly be reduced. Generally, the low resistance layer226may be formed to have a first resistance which may be lower than a resistance of an upper gate electrode of the peripheral region and formed to have a first thickness which may be less than a thickness of the upper gate electrode layer236. Furthermore, the low resistance layer226may be made to have a relatively thin profile which provides improved surface topology for overlying layers.

Referring again toFIG. 2, the peripheral region “p” may include a low voltage region pLand a high voltage region pH, which may include a low voltage transistor and a high voltage transistor, respectively. The low voltage transistor, formed in low voltage region pL, may include a low voltage peripheral gate electrode230pLand impurity layers202pL. The high voltage transistor formed in the high voltage region pHmay include a high voltage peripheral gate electrode230pHand impurity layers202pH. Similar to layers202c, impurity layers202pLand202pHmay have different structures depending on their use in the low voltage transistor or the high voltage transistor. Also, the impurity layers202pLand202pHmay have different doping concentration levels, different depths or widths and different impurity types depending on the needs of the associated transistor.

Cell spacers250pLand250pHmay be similar to spacers251cand may include a single or multi-layered structure of, for example, silicon oxide, and silicon nitride and/or a low dielectric material. The cell spacers250pLand250pHmay be formed on either side of the peripheral gate electrodes230pLand230pHand may extend from an upper location of the respective gates, for example, the top of the gates, to a location above the respective impurity layers202pLand202pH. The interlayer dielectric260may be formed to generally cover the peripheral area of the nonvolatile device. Again, the interlayer dielectric260may include a single or multi-layered structure, for example, a silicon oxide layer, a silicon nitride layer, a polymer layer, and/or a low dielectric layer.

The low voltage gate electrode230pLmay include a low voltage dielectric layer232pL, a lower gate electrode layer234pLand an upper gate electrode layer236pL. The low voltage gate electrode230pLmay also include a hard mask layer240. The high voltage gate electrode230pHmay include a high voltage dielectric layer232pH, a lower gate electrode layer234pHand an upper gate electrode layer236pH. The high voltage gate electrode230pHmay also include the hard mask layer240. In both the low voltage gate and the high voltage gate, the dielectric layer232may be formed above the substrate, the lower gate electrode layer234may be formed above the dielectric layer232, and the upper gate electrode layer236may be formed above the lower gate electrode layer234.

As illustrated inFIG. 2, the low voltage gate electrode230pLand the high voltage gate electrode230pHmay be formed above the substrate100and have similar structures and features. The low voltage gate electrode230pLmay be formed for use at a lower voltage than the high voltage gate. Accordingly, the dielectric layer232pHof the high voltage gate electrode230pHmay have a thickness greater than that of the dielectric layer232pLof the low voltage transistor. Similarly, the lower gate electrode layer234pHof the high voltage transistor may have a thickness greater than that of the lower gate electrode layer234pLof the low voltage transistor and the upper gate electrode layer234pHmay have a thickness greater than that of upper gate electrode layer234pL. The low voltage dielectric layer232pLand the high voltage dielectric layer232pHmay include the same material as each other and may include one or more layers of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric, e.g., hafnium oxide or zirconium oxide.

In example embodiments, the lower gate electrode layer234pLof the low voltage gate electrode230pLand the lower gate electrode layer234pHof the high voltage gate electrode230pHmay include a semiconductor material, for example poly-silicon. Furthermore, the lower gate electrodes layer234pLand234pH, which include a semiconductor material, may be doped either N-type or P-type according to a desired work function of the transistor.

According to example embodiments, forming the peripheral region “p” provides optimization or improvement of certain characteristics of the peripheral gate electrodes230. For example, the use of a metal silicide as the upper gate electrode layer236in the peripheral region may reduce the resistance of the gate electrodes while providing a higher quality interface with the underlying lower gate electrode layer234formed of poly-silicon. The use of the metal silicide may further provide for forming the peripheral gate electrodes without the use of a barrier metal overlying the lower gate electrode of poly-silicon. Accordingly, the interface resistance of the peripheral gate electrodes may not be increased by use of the barrier layer. Generally, the upper gate electrode layer236may be formed to have a second resistance which, although optimized or improved for the peripheral region, has a higher value than the resistance of the low resistance layer226of the cell region. Also, the upper gate electrode layer236may be generally formed to have a thickness which may be greater than a thickness of the low resistance layer236.

Referring now toFIGS. 3A-3I, a method of forming a non-volatile memory device according to example embodiments will be described.FIGS. 3A-3Iare cross-sectional views taken along lines IIc-IIc′, IIpL-IIpL′ and IIpH-IIpH′ ofFIG. 1and illustrate a sequence of processing operations that may be used to manufacture a non-volatile memory device.

Referring toFIG. 3A, a substrate100may be prepared having a cell region “c” and a peripheral region “p” wherein the peripheral region may include a low voltage peripheral region pLand a high voltage peripheral region pH. Preparation of the substrate may include doping of the active areas106c,106pLand106pHaccording to the characteristics of the transistors and other devices that will be formed therein. Preparation of the substrate may further include forming the isolation layer102so as to define locations of the active areas and to provide electrical isolation between them. In example embodiments, formation of the isolation layer102may include a shallow trench isolation process. Alternatively, the isolation layer102may be formed using a deep trench process or a field oxide isolation process.

Still referring toFIG. 3A, a gate dielectric layer232may be formed on the substrate100. More specifically, the gate dielectric layer may be formed on the substrate100in both the cell region as232pLand the peripheral region including both the low and high voltage peripheral regions as232pLand232pH, respectively. The gate dielectric layer232may be formed over the substrate using a variety of methods. For example, a first dielectric sub-layer may be formed over the substrate so as to have a thickness which may be relatively thin such as that which may be used for the low voltage gate electrode230pL. The cell region “c” and the low voltage peripheral region pLmay be masked and a second sub-layer of dielectric formed in only the high voltage peripheral region pH. With the mask removed, a thicker dielectric layer may be formed in the high voltage peripheral region pHas compared to that formed in the cell region “c” and the low voltage peripheral region pL. Alternatively, a first dielectric layer may be formed over the substrate having a thickness which may be relatively thick such as that which will be used for the high voltage gate electrode230pH. A mask may be formed over cell region “c” and/or high voltage region pH, the thick dielectric removed from the low voltage region pL, a thinner dielectric formed in low voltage region pLand the mask removed so that the low and high voltage regions may be formed having dielectrics with appropriate thicknesses.FIG. 3Ashows dielectric232pLformed in the low voltage peripheral region pLas well as the cell region “c” but this must be understood as merely an example.

A lower gate electrode layer234may be formed over the dielectric layer232and an upper gate electrode layer236may be formed over the lower gate electrode layer234. The layers234and236may be formed in sequence over the substrate100. The lower gate electrode layer234may be formed of a semiconductor material, for example, poly-silicon, which may be doped either in-situ or using ion implantation after it is deposited.

The upper gate electrode layer236may be formed on the lower gate electrode layer234. The upper gate electrode layer236may be formed to have one or more layers and may be formed of, for example, a metal-silicide, e.g., tungsten silicide (WSi), titanium silicide (TiSi), tantalum silicide (TaSi), cobalt silicide (CoSi) and other known silicides. By using a metal silicide as the upper gate electrode layer236, the upper gate electrode will have a lower resistivity than the lower gate electrode layer234formed of doped poly-silicon, and thus, the overall resistance of the peripheral gate may be lowered. Furthermore, the metal silicide may interface well with the underlying poly-silicon without substantial material diffusion. Accordingly, a barrier metal layer may not be necessary between the metal silicide layer and the underlying poly-silicon and therefore an interface resistance between the metal silicide layer and underlying poly-silicon layer may remain low. As further illustrated inFIG. 3A, a first mask pattern310may be formed overlying the upper gate electrode layer236. The first mask pattern310may include one or more layers of, for example, oxide, nitride, oxynitride, and/or doped glass. As illustrated inFIG. 3B, the first mask pattern310may be removed from the cell region “c”, leaving peripheral regions pLand pHcovered.

As illustrated inFIG. 3C, the upper gate electrode layer236, the lower gate electrode layer234and the dielectric layer232pLmay be removed from cell region “c”. These layers may be removed by known processes, e.g., wet etching. The upper gate electrode layer236, the lower gate electrode layer234and the dielectric layer232may not be removed from the peripheral regions pLand pHbecause they remain covered by first mask pattern310. After the removal, active areas106cin the cell area of substrate100may be exposed.

As illustrated inFIG. 3D, a layered insulating structure210and a layered conducting structure220may be formed overlying the substrate100in both the cell region and the peripheral region. As illustrated, the layered insulating structure210and the layered conducting structure220may be formed in sequence on the exposed active areas106cin the cell region and may be formed on the first mask pattern310in the peripheral regions pLand pH. The layered insulating structure210may include a tunnel insulating layer212, a charge storage insulating layer214and a blocking insulating layer216. The tunnel insulating layer212may be formed above the substrate100in cell region “c” and may include one or more layers of, for example, silicon oxide, silicon oxynitride (SiON), silicon nitride, a silicon oxide layer having a nitrided portion, aluminum oxide (Al2O3), hafnium aluminate (HfAlO), hafnium aluminum oxynitride (HfAlON), hafnium silicate (HfSiO) and hafnium silicon oxynitride (HfSiON). The tunnel insulating layer212may be formed by known methods.

The charge storage insulating layer214may be formed above the tunnel insulating layer212and may be used to trap or store charges for use in programming each cell gate WL. The charge storage insulating layer214may include one or more layers of, for example, poly-silicon, silicon nitride, silicon oxynitride, silicon rich oxide, ferroelectric materials, nano-crystalline silicon, nano-crystalline silicon germanium, nano-crystalline metal, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium aluminate (HfAlO), hafnium aluminum oxynitride (HfAlON), hafnium silicate (HfSiO) and/or hafnium silicon oxynitride (HfSiON). The charge storage insulating layer214may include a quantum-dot layer. For example, the charge storage insulating layer214may include a layer of silicon, germanium, and/or metal quantum-dots.

The blocking insulating layer216may be formed above the charge storage insulating layer214and may be chosen to have a dielectric constant greater than that of the tunnel insulating layer212. The blocking insulating layer216and may include a metallic oxide or a metallic oxynitride of a Group III element or a Group VB element. According to other example embodiments, the blocking insulating layer216may include a doped metal oxide or a doped metal oxynitride in which the metal oxide may be doped with a Group IV element. The Group IV element may reduce leakage current from the memory cell. The Group IV element may be doped in the metal oxide to about 0.1 to 30 weight percent. The blocking insulating layer216may include one or more layers of, for example, silicon oxide, silicon oxynitride (SiON), silicon nitride, and metallic oxide, e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium aluminate (Hf1-xAlxOy), hafnium aluminum oxynitride (HfAlON), hafnium silicate (HfxSi1-xO2), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrxSi1-xO2), and/or zirconium silicon oxynitride (ZrSiON). The material Al2O3may have a dielectric constant of about 10 and an energy band gap of about 8.3 eV and the material ZrO2has a dielectric constant of about 25 and an energy band gap of about 8.3 eV. The blocking insulating layer216may also include one or more layers of AlO, Ta2O5, TiO2, PZT[(Pb(Zr, Ti)O3)), PbTiO3, PbZrO3, PLZT[(Pb,La) (Zr, TiO3)], PbO, SrTiO3, BaTiO3, V2O5, BST[(Ba,Sr)TiO3], SBT(SrBi2Ta2O9), Bi4Ti3O12, and combinations thereof.

In example embodiments, the blocking insulating layer216may include a layer similar to that of the charge storage insulating layer214. For example, both the blocking insulating layer216and the charge storage insulating layer214may include a layer of hafnium aluminate (HfAlO), hafnium aluminum oxynitride (HfAlON), hafnium silicate (HfSiO) and/or hafnium silicon oxynitride (HfSiON). In such a case, a relative stoichiometric amount of hafnium in the charge storage insulating layer214may be made higher than the relative stoichiometric amount of hafnium in the blocking insulating layer216so as to increase a trap density in the charge storage insulating layer214and to enhance an insulation characteristic of the blocking insulating layer216.

In example embodiments, the blocking insulating layer216may have a dielectric constant higher than that of the tunnel insulating layer212. For example, the blocking insulating layer216may include at least one layer of material having a dielectric constant that may be higher than any layer included in the tunnel insulating layer212. In example embodiments, the blocking insulating layer216and the tunnel insulating layer212may be formed of materials having substantially similar dielectric constants, for example, they may be formed of the same material. In that case, the blocking insulating layer216may have a thickness that may be greater than a thickness of the tunnel insulating layer212.

As further illustrated inFIG. 3D, a layered conducting structure220may be formed on the layered insulating structure210. The layered conducting structure220may include an energy barrier layer222, a barrier metal layer224and a low resistance layer226. The energy barrier layer222may be formed above the blocking insulating layer216and may include a metal having a work function greater than about 4 eV. For example, the energy barrier layer222may include one or more layers of, for example, tantalum (Ta), tantalum nitride (TaN), tantalum titanium (TaTi), tantalum platinum (TaPt), tantalum silicon nitride (TaSiN), titanium (Ti), titanium nitride (TiN), titanium aluminide (Ti3Al), titanium aluminum nitride (Ti2AlN), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), molybdenum (Mo), molybdenum nitride (Mo2N), ruthenium (Ru), ruthenium dioxide (RuO2) nickel silicide (NiSi), palladium (Pd), iridium (Ir), platinum (Pt), cobalt (Co), cobalt silicide (CoSi) and/or aluminum silicide (AlSi). By using an energy barrier layer222having a work function greater than about 4 eV, charges from the overlying low resistance layer226may be prevented or retarded from moving to the charge storage insulating layer214during an erase function of the memory cell.

The barrier metal layer224may be formed above the energy barrier layer222. The barrier metal layer224may be formed of a material that reduces or prevents an interfacial reaction and/or diffusion between the blocking insulating layer216or energy barrier layer222and the overlying low resistance layer226. The barrier metal layer224may include one or more layers of, for example, tungsten nitride (WN), tungsten silicon nitride (WSiN) titanium nitride (TiN) or any other metal nitride that aides in preventing or reducing an interfacial reaction and/or mutual diffusion.

The low resistance layer226may be formed above the barrier metal layer224. The low resistance layer may include one or more layers of, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), molybdenum (Mo), titanium (Ti), platinum (Pt), palladium (Pd) and other low resistance materials. The low resistance layer226in the cell region may be formed of a material having a lower resistivity than the upper electrode layer236of the peripheral region. Also, the low resistance layer226in the cell region may have a thickness which may be less than a thickness of the upper electrode layer236. Generally, the low resistance layer226may be formed of a material different from that of the upper electrode layer236.

Also illustrated inFIG. 3D, a second mask pattern320may be formed to overly the conducting structure220. Ultimately, the second mask pattern320may overlay only the conducting structure220in the cell region “c”. To achieve this end, the second mask pattern320may be selectively deposited only in the cell region “c” or may be blanket deposited over both the cell region “c” and the peripheral region “p” and then selectively removed in the peripheral region “p”. Either way, as illustrated inFIG. 3D, the second mask pattern320may be formed such that the conducting structure220in the peripheral region may be exposed. Similar to the first mask pattern310, the second mask pattern320may include one or more layers of, for example, oxide, nitride, oxynitride, and/or doped glass. The second mask pattern320may be formed of the same material or a different material from that of first mask pattern310.

As illustrated inFIG. 3E, the conducting structure220and the insulating structure210may be removed from the peripheral region “p”. By using the second mask pattern320, the conducting structure220and the insulating structure210may be selectively removed from the peripheral region “p” while remaining in the cell region “c”. The selective removal may be performed until the first mask pattern310in the peripheral region is exposed. The first mask pattern310in the peripheral region may perform as an etch stop.

As illustrated inFIG. 3F, the first mask pattern310may be removed from the peripheral region while the second mask pattern320may be removed from the cell region. Both mask layers may be completely removed by known wet-etching or dry-etching methods. With the mask layers removed, the upper gate electrode layer236may be exposed in the peripheral region while the low resistance layer226may be exposed in the cell region. As illustrated inFIG. 3G, a hard mask layer240may be formed over the upper gate electrode layer236in the peripheral region and the low resistance layer226in the cell region. The hard mask layer240may be formed of, for example, oxide, nitride, and/or oxynitride.

As illustrated inFIG. 3H, the hard mask layer240and conducting structure220may be patterned in the cell region “c” to form the SSL and WLs as shown, as well as the GSL, which is not shown. In example embodiments, the patterning of the hard mask layer240and the conducting structure220may be performed by etching, using the blocking insulating layer216as an etch stop. Accordingly, the SSLs, WLs and GSLs may be formed having an insulating structure210that includes a tunnel insulating layer212, charge storage insulating layer214and blocking insulating layer216and having a conducting structure220including an energy barrier222, a barrier metal layer224and a low resistance layer226. Because the blocking insulating layer216is used as an etch stop, the insulating structure210may be formed underlying and extending between the SSLs and WLs as shown and the GSL though not shown.

As further illustrated inFIG. 3H, the hard mask layer240, the upper gate electrode layer236, and the lower gate electrode layer234may be patterned in the peripheral region “p” to form the low voltage gate electrode230pLand the high voltage gate electrode230pH. The dielectric layer232may be used as an etch stop in the peripheral region. Each of the low voltage gate electrode230pLand the high voltage gate electrode230pHinclude a dielectric layer232pLor232pH, lower gate electrode layer234, upper gate electrode layer236and hard mask layer240. In example embodiments, the etching of the cell region may be performed simultaneously with the etching of the peripheral region so that the SSLs, WLs, and GSLs may be formed at the same time as the low voltage gate electrode230pLand high voltage gate electrode230pH, wherein the blocking insulating layer216may be used as an etch stop in the cell region “c” and the dielectric layer232may be used as an etch stop in the peripheral region “p”.

As illustrated inFIG. 3I, impurity layers202c,202pLand202pHmay be formed on either sides of the gates SSL, WL, GSL in the cell region as well as the gate electrodes230pLand230pHin the peripheral region. The impurity layers202may be formed as source and drain regions as well as contact regions as necessary. The impurity regions may be formed using a well known ion implantation process and may be formed simultaneously or at different times depending on the requirements of each impurity region. For example, if certain impurity regions require different types of impurities, different concentrations, different implantation angles or other differing variables, the impurity layers202may be formed at different times.

As further illustrated inFIG. 3I, spacers250c,250pLand250pHmay be formed on the sidewalls of the conductive structures SSL, WL and GSL in the cell region as well as the low voltage gate electrode230pLand the high voltage gate electrode230pHin the peripheral region. The spacers250may be formed using a conformal deposition of, for example, oxide, followed by an etch process. The spacers may include one or more layers of, for example, silicon oxide, silicon nitride and/or a low dielectric material. Following the formation of spacers250, additional implantation may be performed in the source/drain regions, for example, to form lightly doped drain (LDD) regions, as necessary.

Following the process illustrated inFIG. 3I, an interlayer dielectric260(illustrated inFIG. 2) may be formed overlying the structure formed heretofore. The interlayer dielectric may include one or more layers of, for example, silicon oxide, silicon nitride, a polymer layer, and/or a low dielectric layer. The bitline contact DC and the CSL may be formed in the interlayer dielectric260so as to make contact with their respective impurity layers202. Finally, the bit line104may be formed overlying the interlayer dielectric260so as to make contact with the bitline contact DC so that the formation of the non-volatile device may be substantially finished.

As illustrated inFIGS. 3A-3Eand as discussed above, in example embodiments, the dielectric layer232, the lower gate electrode layer234, the upper gate electrode layer236and first mask pattern310may be first formed over the exposed substrate100followed by removal of the same layers in the cell region to expose the substrate100in the cell region while leaving the layers remaining in the peripheral region. After removal of the layers232,234,236and310from the cell region, the insulating structure210, conducting structure220and second mask pattern320may be formed over the exposed substrate100in the cell region and over the first mask pattern310in the peripheral region. Subsequently, the insulating structure, conducting structure and second mask pattern320may be removed from the peripheral region to thus form the structure illustrated inFIG. 3E.

In example embodiments, the formation order may be substantially reversed. For example, the insulating structure210, the conducting structure220and second mask pattern320may first be formed overlying the exposed substrate100followed by selective removal of these layers from the peripheral region only. The dielectric layer232, the lower gate electrode layer234, upper gate electrode layer236and the first mask pattern310may be formed overlying the exposed substrate100in the peripheral region as well as overlying the second mask pattern320in the cell region. In that case, selective etching of the first mask pattern310, upper electrode layer236, lower electrode layer234and dielectric layer232may be performed for their removal in the cell region using the second mask pattern320as an etch stop. Accordingly, the structure ofFIG. 3Emay be achieved by an alternative method and processing as to the method ofFIGS. 3F-3I.

FIG. 4illustrates other example embodiments.FIG. 4is a cross-sectional view taken along lines IIc-IIc′, IIpL-IIpL′ and IIpH-IIpH′ ofFIG. 1. Example embodiments as illustrated inFIG. 4are substantially similar to that illustrated inFIG. 2. For example, as illustrated in bothFIG. 2andFIG. 4, an insulating structure210and a conducting structure220may be formed in the cell region and a dielectric layer232, a lower gate electrode layer234and an upper gate electrode layer236may be formed in the peripheral region. However, as illustrated inFIG. 4, the cell spacers251cmay be formed to extend from an upper location of the conducting structure220, for example, the top of the conductive structure, to the surface of substrate100. Accordingly, as illustrated inFIG. 4, the sidewall spacers251cmay be formed along an entire side of the SSLs, WLs and GSLs (not shown). For example, the spacers251cmay be formed on a side of the tunnel insulating layer212, charge storage insulating layer214and blocking insulating layer216of the insulating structure210as well as the energy barrier layer222, barrier metal layer224and low resistance layer226of the conducting structure220.

FIGS. 5A and 5Billustrate a method of fabricating the device ofFIG. 4. The process ofFIGS. 5A and 5Bmay include operations included inFIGS. 3A-3Iwhich will be referred to accordingly. As an example, a process of forming the device ofFIG. 4may include the processing operations ofFIGS. 3A-3G. For example, prior to the processing illustrated inFIG. 5A, the processes ofFIGS. 3A-3Ghave been completed. Moreover, the process ofFIG. 5Ais similar to that illustrated inFIG. 3H. More specifically,FIG. 5Aillustrates the formation of the SSLs, WLs and GSLs (not shown) in the cell region as well as the low voltage gate electrode230pLand the high voltage gate electrode230pHin the peripheral region. Example embodiments may include a two-operation etching process regarding the formation of the gate lines in the cell region. As illustrated inFIG. 3H, a first etching operation may be used to form individual conducting structures220of the SSLs and WLs while the underlying layered insulating structure210remain common. In a second operation, the layered insulating structure210may be etched to form insulating layers (e.g. tunnel insulating layer212, charge storage insulating layer214and blocking insulating layer216) for each of the SSLs and WLs. For example, after the first etching operation has been completed, a mask layer may be formed overlying the peripheral region in which the low and high voltage gate electrodes have already been formed. After formation of the overlying mask in the peripheral region, a second etch operation may proceed in the cell region. Therefore, the layered insulating structure210will be etched to form the individual SSLs, WLs and GSLs as illustrated inFIG. 5A.

FIG. 5Billustrates a process similar to that ofFIG. 3Iwherein cell spacers250pL,250pHand251cmay be formed in the peripheral regions and cell region. For example, a dielectric layer may be deposited over the substrate and appropriately etched so as to form the spacers. The processing to form the spacers250pL,250pHand251cmay be substantially similar to that discussed regarding FIG.3I. Also,FIG. 5Bmay include the interlayer dielectric260, bit line contact DC, and bit line104.

FIG. 6illustrates another nonvolatile memory device according to example embodiments.FIG. 6is a cross-sectional view taken along lines IIc-IIc′, IIpL-IIpL′ and IIpH-IIpH′ ofFIG. 1. As shown inFIG. 6, the SSL gates in the cell region “c”, as well as the GSL gates not shown, may have a structure substantially similar to that of the low voltage gate electrode230pLof the peripheral region pL. For example, the SSL and GSL gates may include a dielectric layer232pL, a lower electrode layer234pLand an upper electrode layer236pLas does the low voltage gate electrode230pLformed in the peripheral region pL. The SSL and GSL gates may further include a hard mask layer240. Forming of the SSL and GSL gates similar to that of the low voltage gate electrode230pLallows greater choice in the design of the nonvolatile memory device.

FIGS. 7A and 7Billustrate a process of manufacturing the device ofFIG. 6according to example embodiments. The processes ofFIGS. 7A and 7Bmay include operations included inFIGS. 3A-3Iwhich will be referred to accordingly. For example, fabrication of the device ofFIG. 6may include the process illustrated inFIG. 3Aand a process similar to that illustrated inFIG. 3B. However, in the process ofFIG. 3B, a modification may be made such that first mask pattern310remains over the peripheral region as well as over the SSL and GSL sub-regions within the cell region. For example, a location in the cell region in which the SSL and GSL will be later patterned may remain covered with first mask pattern310. Using the first mask pattern310, the dielectric layer232, lower gate electrode layer234and upper gate electrode layer236may be removed only selectively from cell region “c” to expose the substrate100in areas where cell gates WL may be formed. Subsequently, the insulating structure210and conducting structure220may be formed overlying the exposed substrate100in the cell region. In example embodiments and similar to example embodiments illustrated and explained with reference toFIGS. 3A-3E, the formations in the cell region and the peripheral regions may be alternated. For example, the insulating structure210and the conducting structure220may first be formed over the substrate100. The insulating structure210and the conducting structure220may then be selectively masked in the cell region, specifically in the cell region where cell gates WL may be formed and selectively etched leaving the insulating structure210and the conducting structure220only in the cell gate area. Thereafter, the dielectric layer232, lower gate electrode layer234and upper gate electrode layer236may be formed overlying the substrate including the conducting structure220. Of course, the formation of these layers may include first and second mask patterns310and320as appropriate.

FIG. 7Aillustrates a processing operation which follows the deposition and selective etching of the insulating structure210and conducting structure220in cell region “c”.FIG. 7Ais similar in processing to that illustrated inFIG. 3HandFIG. 5A. More specifically,FIG. 7Aillustrates the formation of the SSLs, WLs and GSLs (not shown) in the cell region as well as the low voltage gate electrode230pLand the high voltage gate electrode230pHin the peripheral region. The process may include a two-operation etching process regarding the formation of the cell gates WL in the cell region. That is, as illustrated inFIG. 3H, a first etching operation may be used to form individual conducting structures220of the WLs while the underlying insulating structure210remains common. In a second operation, the layered insulating structure may be etched to form insulating layers (e.g. tunnel insulating layer212, charge storage insulating layer214and blocking insulating layer216) for each of the WLs. For example, after the first etching operation has been completed, a mask layer may be formed overlying the peripheral region in which the low and high voltage gate electrodes have already been formed as well as the area of the cell region in which the SSLs and GSLs may be formed. After formation of the overlying mask, the second etch operation may proceed in the cell region. Therefore, the layered insulating structure210may be etched to form the individual WLs as illustrated inFIG. 7Awhile the SSLs and GSLs have been etched and formed coincident with the formation of the low voltage gate electrode230pLand the high voltage gate electrode230pH.

FIG. 7Billustrates a process similar to that ofFIG. 3IandFIG. 5Bwherein cell spacers250pL,250pHand251cmay be formed in the peripheral regions and cell region. That is, a dielectric layer may be deposited over the substrate and appropriately etched so as to form the spacers. The processing to form the spacers250pL,250pHand251cmay be substantially similar to that discussed regardingFIG. 3IandFIG. 5B. Following the formation of the cell spacers, the interlayer dielectric260and remaining metallization may be formed.

Although example embodiments have been shown inFIG. 6, wherein the SSL and GSL may be formed similar to the low voltage gate electrode230pL, the SSL and GSL may also be formed similar to that of the high voltage gate electrode230pH.

While example embodiments have been shown and described with reference to certain example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims and their equivalents.