Semiconductor device package

A semiconductor device package includes a first conductive base, a first semiconductor die, a dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The first conductive base defines a first cavity. The first semiconductor die is on a bottom surface of the first cavity. The dielectric layer covers the first semiconductor die, the first surface and the second surface of the first conductive base and fills the first cavity. The first patterned conductive layer is on a first surface of the dielectric layer. The second patterned conductive layer is on a second surface of the dielectric layer.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor device package and a method of manufacturing the same. In particular, the present disclosure relates to a semiconductor device package structure including an improved conductive base and a method for manufacturing the same.

2. Description of the Related Art

In some embedded semiconductor device packages, where one or more semiconductor devices are disposed in a die paddle of a leadframe, it can be challenging to integrate a large number of components and/or input/outputs (I/Os) (e.g. conductive lines/vias/traces) into the embedded semiconductor device package while preventing or mitigating parasitic capacitance.

SUMMARY

In one or more embodiments in accordance with a first aspect of the present disclosure, a semiconductor device package includes a first conductive base, a first semiconductor die, a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, a plurality of first interconnection structures and a plurality of second interconnection structures. The first conductive base has a first surface and a second surface opposite to the first surface. A first cavity is defined by the first conductive base and formed in the first surface of the first conductive base. The first cavity has a bottom surface. The first semiconductor die is disposed on the bottom surface of the first cavity. The dielectric layer is disposed on the first semiconductor die, the first surface and the second surface of the first conductive base and fills the first cavity. The dielectric layer has a first surface and a second surface opposite to the first surface. The first patterned conductive layer is disposed on the first surface of the dielectric layer. The second patterned conductive layer is disposed on the second surface of the dielectric layer. The plurality of first interconnection structures are disposed in the dielectric layer and electrically connected to the first semiconductor die and the first patterned conductive layer. The plurality of second interconnection structures are disposed in the dielectric layer and electrically connected to the second surface of the first conductive base and the second patterned conductive layer.

In one or more embodiments in accordance with another aspect of the present disclosure, a semiconductor device package includes a conductive base, a first semiconductor die, a second semiconductor die, a dielectric layer, a first patterned conductive layer, a plurality of first interconnection structures and a plurality of second interconnection structures. The conductive base has a first surface and a second surface opposite to the first surface. The conductive base defines a cavity formed in the first surface of the first conductive base. The cavity has a bottom surface. The first semiconductor die is disposed on the bottom surface of the cavity. The second semiconductor die is disposed on the bottom surface of the cavity. The dielectric layer is disposed on the first surface of the conductive base, the first semiconductor die and the second semiconductor die and fills the cavity. The dielectric layer has a first surface. The first patterned conductive layer and a second patterned conductive layer are disposed on the first surface of the dielectric layer. The plurality of first interconnection structures are disposed in the dielectric layer and electrically connected to the first semiconductor die and the first patterned conductive layer. The plurality of second interconnection structures are disposed in the dielectric layer and electrically connected to the second semiconductor die and the second patterned conductive layer.

In one or more embodiments in accordance with another aspect of the present disclosure, a semiconductor device package includes a conductive base, a first semiconductor die, a first dielectric layer, a first patterned conductive layer, a second semiconductor die, a second dielectric layer and a second patterned conductive layer. The conductive base has a first surface and a second surface opposite to the first surface. The conductive base defines a cavity formed in the first surface of the conductive base. The cavity has a bottom surface. The first semiconductor die is disposed on the bottom surface of the cavity. The first dielectric layer is disposed on the first surface of the conductive base and the first semiconductor die. The first dielectric layer has a first surface. The first patterned conductive layer is disposed on the first dielectric layer and electrically connected to the first semiconductor die. The second semiconductor die is disposed on the first patterned conductive layer. The second dielectric layer is disposed on the first patterned conductive layer, the first surface of the first dielectric layer, and the second semiconductor die. The second patterned conductive layer is disposed on the second dielectric layer and electrically connected to the second semiconductor die.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. Embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

Described in this disclosure are embodiments of techniques for providing devices with reduced package sizes. For example, the present disclosure describes embodiments of a semiconductor device package structure including an improved conductive base structure for mitigating or eliminating parasitic capacitance when one or more semiconductor devices are disposed in a die paddle of a leadframe.

FIG. 1is a cross-sectional view of some embodiments of a semiconductor device package1in accordance with a first aspect of the present disclosure. The semiconductor device package1includes a substrate10, semiconductor dies20,22,24and26, conductive adhesive layers48, a protection layer70(e.g. a dielectric layer) that can, in at least some embodiments, function as a support layer, insulating layers50and52, patterned conductive layers80and82, interconnection structures801and821, a connecting element90, and conductive connects75.

The substrate10includes a conductive base101and a conductive base102. In some embodiments, the conductive bases101and102can constitute, or can be a part of, a leadframe. The conductive base101has a first surface101uand a surface101bopposite to the first surface101u. The conductive base102has a first surface102uand a surface102bopposite to the first surface102u. A material of the conductive bases101and102may include, for example, copper (Cu), or another metal, or a metal alloy, or other conductive material. In some embodiments, the conductive bases101and102can constitute, or can be a part of, a die paddle. Implementation of structure that is, at least in part, substantially symmetric including the conductive base101and the conductive base102can provide for reduced warpage of the semiconductor device package1. In addition, a large number of components can be integrated into a leadframe having a substantially symmetrical structure. In some embodiments, by disposing the conductive base101and the conductive base102on opposite sides of a connecting element90, each conductive base having a substantially same minimum distance from the connecting element90, can provide for reduced warpage of the semiconductor device package1, and for integration of a large number of components into a leadframe.

In some embodiments, the conductive bases101and102defines one or more curved structures60(e.g. smoothed or rounded corners) that can help to reduce or minimize stress at the respective curved structures60during a manufacturing operation (e.g. reduced stress relative to stresses involved in formation of the protection layer70). The curved structures60may further help to redistribute stress across the conductive bases101and102, to more evenly apportion stress across the conductive bases101and102, or to transfer a stress point from one portion of the conductive bases101and102to another portion of the conductive bases101and102. Different curved structures60may have different radii of curvature and/or may form different angles of taper with respect to the surface101bof the conductive base101or the first surface102uof the conductive base102.

The conductive base101defines a cavity30in the first surface101uof the conductive base101, and the conductive base102defines a cavity32in the first surface102uof the conductive base102. The cavity30has a bottom surface301and the cavity32has an upper surface321. A semiconductor die20and a semiconductor die24are disposed on the bottom surface301of the cavity30. A semiconductor die22is disposed on the upper surface321of the cavity32.

The cavities30and32are respectively formed in the conductive base101and the conductive base102and can receive the semiconductor dies20,22and24, which can help to decrease package thickness. Some embodiments of a compact three-dimensional (3-D) embedded package can be achieved by a design that includes the cavities30and32.

In some embodiments, the semiconductor die20has a first surface201and a second surface202opposite the first surface201. The surface202of the semiconductor die20is bonded to the bottom surface301of the cavity30through the conductive adhesive layer48. The conductive adhesive layer48may be, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material), or other conductive material. In some embodiments, the semiconductor die24has a first surface241and a second surface242opposite the first surface241and the semiconductor die22has a first surface221and a second surface222opposite the first surface221. The semiconductor die24is also bonded to the bottom surface301of the cavity30through the conductive adhesive layer48. The semiconductor die26has a first surface261and a second surface262opposite the first surface261. The surface262of the semiconductor die26is bonded to the surface102bof the conductive base102through the conductive adhesive layer48.

The semiconductor die24is bonded to the bottom surface301of the cavity30through the conductive adhesive layer48and the semiconductor die22is bonded to the upper surface321of the cavity32through the conductive adhesive layer48. The semiconductor dies20and22may be, for example, power dice, and the semiconductor die24may be, for example, a control die. The die26is disposed on the surface102bof the conductive base102. The die26is electrically connected to the patterned conductive layer80through the interconnection structure801.

The conductive adhesive layer48is disposed between the surface202of the semiconductor die20and the bottom surface301of the cavity30. In some embodiments, the conductive adhesive layer48covers a portion of the bottom surface301of the cavity30, and/or covers substantially the entire bottom surface301. In some embodiments, the conductive adhesive layer48may contact a portion of one or more sidewalls of the semiconductor die20. The conductive adhesive layer48attaches the semiconductor die20to the conductive base101. The arrangement of the semiconductor die24is similar to the semiconductor die20(e.g. the semiconductor die24is similarly attached to the bottom surface301via conductive adhesive).

For the semiconductor die22, the conductive adhesive layer48is disposed between the surface222of the semiconductor die22and the upper surface321of the cavity32. In some embodiments, the conductive adhesive layer48covers a portion of the upper surface321of the cavity32and/or covers substantially the entire upper surface321. In some embodiments, the conductive adhesive layer48may contact a portion of one or more sidewalls of the semiconductor die22. The conductive adhesive layer48attaches the semiconductor die22to the conductive base102.

The protection layer70is disposed on the conductive bases101and102and is disposed on the semiconductor dies20,22and24. The protection layer70has a first surface701and a second surface702opposite to the first surface701. The protection layer70encapsulates the first surface101uand the second surface101bof the conductive base101and encapsulates at least a portion of the semiconductor dies20and24. The protection layer70also encapsulates and/or covers at least a portion of the first surface102uand the surface102bof the conductive base102and encapsulates at least a portion of the semiconductor die22. In some embodiments, a material of the protection layer70may include a polypropylene resin; however, other suitable materials may be additionally or alternatively used.

The interconnection structures801respectively electrically connect respective patterned conductive layers80to the first surface201of the semiconductor die20and to the first surface241of the semiconductor die24. The interconnection structure821electrically connects the patterned conductive layer82to the first surface221of the semiconductor die22. The interconnection structure801is electrically connected to the first surface101uof the conductive base101and the interconnection structure821is electrically connected to the first surface102uof the conductive base102. The surface102bof the conductive base102is electrically connected to the patterned conductive layer80through the plurality of interconnection structures801. The semiconductor die22is electrically connected to the conductive layer82through the plurality of interconnection structures821. In some embodiments, the die20is electrically connected to the die22through the conductive base101and the interconnection structures821.

In some embodiments, the interconnection structures801and821are conductive vias formed through the protection layer70. A material of interconnection structures801and821and patterned conductive layer80and82may include, for example, copper or another metal, or a metal alloy, or other conductive material.

The insulating layer50is disposed on at least a portion of the first surface701of the protection layer70and over the interconnection structures801. The insulating layer52is disposed on at least a portion of the second surface702of the protection layer70and over the interconnection structures821. In some embodiments, the insulating layers50and52may include a solder mask. A material of one or both of the insulating layers50and52may include a polypropylene resin and/or other insulating materials. Conductive connects75(e.g., solder balls) are disposed on the patterned conductive layers80.

The conductive base101defines curved structures60and the conductive base102defines curved structures60. The curved structures60can include rounded corners of the conductive bases. The curved structures60can include recesses defined by one or more of the conductive bases (e.g. recesses formed in an outer sidewall or other sidewall of one or more of the conductive bases), and the recesses can include a rounded corner. The recesses can be defined by a bottom portion of a sidewall of a conductive base (e.g. can extend to a corner where the sidewall and the surface101bor the surface102uconnect). In another embodiment, the curved structures60of conductive base101and conductive base102may be filled with protection layer70. The curved structures can help to reduce or prevent damage to the protection layer70during separation (e.g. singulation) of individual semiconductor device packages1from a larger package (e.g., from a panel).

The connecting element90is disposed in the protection layer70. The connecting element90is electrically connected to at least one of the patterned conductive layer80and the patterned conductive layer82(e.g. through one of the interconnection structures801or821). The material of the connecting element90may include, for example, copper or another metal, or a metal alloy, or other conductive material. In some embodiments, the connecting element90is a metal component (e.g., a metal frame) or a through hole filled with a conductive material.

One example current path (indicated by arrows inFIG. 1) in the semiconductor device package1flows from the patterned conductive layer80through the conductive base101to the patterned conductive layer82. By providing for such a path, one or more vias of reduced height can be implemented (as compared to, for example, a via extending from the top patterned conductive layer80to the bottom patterned conductive layer82). It can be easier to manufacture such a relatively short via. Such a reduction of the conductive/current path can also help to avoid signal attenuation or interference.

FIGS. 2A-2Hillustrate some embodiments of a method of manufacturing the semiconductor device package1depicted inFIG. 1. Referring toFIG. 2A, conductive bases101and102are provided. The conductive base101has a first surface101uand a surface101bopposite to the first surface101u. The conductive base102has a first surface102uand a surface102bopposite to the first surface102u. The material of the conductive bases101and102include, for example, copper or another metal, or a metal alloy, or other conductive material. The connecting element90is formed, for example, by drilling (e.g. by drilling at least two holes into an initial conductive base, thereby forming the separate conductive bases101and102and the connecting element90). The first surface101udefines the cavity30(e.g. the first surface101uis provided with the cavity30, or the cavity30is formed in the first surface101u). The first surface102udefines the cavity32(e.g. the first surface102uis provided with the cavity32, or the cavity32is formed in the first surface102u). The cavity30has bottom surface301. The cavity32has an upper surface321. In some embodiments, the conductive base101is provided with the cavity30and is not etched to form the cavity30(e.g. is not etched subsequent to the above-described provision of the conductive base101). That is, the first surface101uof the conductive base101is not removed by an etching technique. The unetched structure of the conductive base101, which may provide a relatively robust or strong structure, is relatively easier to be handled to facilitate subsequent electrical measurements/tests. The conductive base101defines one or more curved structures60. Curved structures60of the conductive base101are smoothed and can help to redistribute stress to avoid damage to the protection layer70during lamination. The structure of the conductive base102may be formed in a similar manner.

Referring toFIG. 2B, conductive adhesive layers48are disposed on the bottom surface301of the cavity30and on the upper surface321of the cavity32. The conductive adhesive layer48may include, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material). A semiconductor die20is disposed on the conductive adhesive layer48in cavity30. The conductive adhesive48is used to attach the semiconductor die20to the bottom surface301of the cavity30. The semiconductor dies22,24and26may be disposed in a similar manner.

Referring toFIG. 2C, a protection layer70is formed on the conductive bases101and102and the semiconductor dies20,22,24and26by, for example, a lamination technique. The protection layer70also covers or fills in the curved structures60. A material of the protection layer70may include, for example, a polypropylene resin or other suitable material. A portion of the protection layer70is melted during lamination. A conductive layer80′ is disposed on the first surface701of the protection layer70by coating, sputtering, plating or another suitable technique. A conductive layer82′ is disposed on the second surface702of the protection layer70by coating, sputtering, plating or another suitable technique. The conductive layers80′ and82′ may include, for example, aluminum or copper, or an alloy thereof (such as AlCu).

Referring toFIG. 2D, vias38are formed through the protection later70from the surface of the conductive layer80′ and vias39are formed through the protection later70from the surface of the conductive layer82′. The vias38and39may be formed, for example, by drilling.

Referring toFIG. 2E, a patterned photoresist layer74is disposed on the conductive layer80′ and a patterned photoresist layer76is disposed on the conductive layer82′. The patterned photoresist layers74and76may be formed by coating or another suitable technique. The patterned photoresist layers74and76may include a positive photoresist or other suitable material.

Referring toFIG. 2F, the thickness of conductive layers80′ and82′ are increased by coating, sputtering, plating or another suitable technique. The conductive layers80and82and the interconnection structures801and821are formed by, for example, such plating.

Referring toFIG. 2G, the patterned photoresist layers74and76are removed by a suitable technique, such as an etching process. After etching, a portion of the first surface701of the protection layer70is exposed and a portion of the second surface702of the protection layer70is exposed.

Referring toFIG. 2H, an insulating layer50is disposed on the first surface701of the protection layer70and an insulating layer52is disposed on the second surface702of the protection layer70. The insulating layer50covers at least a portion of the patterned conductive layers80and the insulating layer52covers at least a portion of the patterned conductive layers82. A material of one or both of the insulating layers50and52may include a polypropylene resin or other insulating materials used additionally or alternatively. Next, the conductive connects75are disposed on, or formed on, vias37defined by the insulating layer50to form the semiconductor device package1as illustrated inFIG. 1. The conductive connects75may include, for example, one or more solder balls. The vias37are disposed over the patterned conductive layers80.

FIGS. 3A-3Jillustrate some embodiments of a method of manufacturing the semiconductor device package1depicted inFIG. 1. Referring toFIG. 3A, conductive bases101and102are provided. The conductive base101has a first surface101uand a surface101bopposite to the first surface101u. The conductive base102has a first surface102uand a surface102bopposite to the first surface102u. The material of the conductive bases101and102include, for example, copper or another metal, or a metal alloy, or other conductive material. The connecting element90is formed, for example, by drilling (e.g. by drilling at least two holes into an initial conductive base, thereby forming the separate conductive bases101and102and the connecting element90). The first surface101udefines the cavity30(e.g. the first surface101uis provided with the cavity30, or the cavity30is formed in the first surface101u). The first surface102udefines the cavity32(e.g. the first surface102uis provided with the cavity32, or the cavity32is formed in the first surface102u). The conductive bases101and102define one or more curved structures60.

Referring toFIG. 3B, conductive adhesive layers48are disposed on the bottom surface301of the cavity30and on the upper surface321of the cavity32. The conductive adhesive layer48may include, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material). A semiconductor die20is disposed on the conductive adhesive layer48in cavity30. The conductive adhesive48is used to attach the semiconductor die20to the bottom surface301of the cavity30. The semiconductor dies22,24and26may be disposed in a similar manner.

Referring toFIG. 3C, a protection layer70is formed on the conductive bases101and102and the semiconductor dies20,22,24and26by, for example, a lamination technique. The protection layer70also covers or fills in the curved structures60. A material of the protection layer70may include, for example, a polypropylene resin or other suitable material. A portion of the protection layer70is melted during lamination. A conductive layer80′ is disposed on the first surface701of the protection layer70by coating, sputtering, plating or another suitable technique. A conductive layer82′ is disposed on the second surface702of the protection layer70by coating, sputtering, plating or another suitable technique.

Referring toFIG. 3D, vias38are formed through the protection later70from the surface of the conductive layer80′ and vias39are formed through the protection later70from the surface of the conductive layer82′. The vias38and39may be formed, for example, by drilling.

Referring toFIG. 3E, the conductive layers80′ and82′ are formed and fill the vias38. The conductive layers80′ and82′ are formed by coating, sputtering, plating or another suitable technique. Referring toFIG. 3F, a patterned photoresist layer74is disposed on the conductive layer80′ and a patterned photoresist layer76is disposed on the conductive layers82′. The patterned photoresist layers74and76may be formed by coating or another suitable technique. The patterned photoresist layers74and76may include a positive photoresist or other suitable material.

Referring toFIG. 3G, a portion of the conductive layer80′ which is not covered by the patterned photoresist layer74is removed by, for example, etching or drilling. A portion of the conductive layer82′ which is not covered by the patterned photoresist layer76is removed by, for example, etching or drilling. After etching, the formation of the patterned conductive layers80and82, and the interconnection structures801and821is completed.

Referring toFIG. 3H, the patterned photoresist layers74and76are removed by a suitable technique, such as an etching process. After etching, a portion of the first surface701of the protection layer70is exposed and a portion of the second surface702of the protection layer70is exposed.

Referring toFIG. 3I, an insulating layer50is disposed on at least a portion of the first surface701of the protection layer70and an insulating layer52is disposed on at least a portion of the second surface702of the protection layer70. The insulating layer50covers at least a portion of the patterned conductive layers80and the insulating layer52covers at least a portion of the patterned conductive layers82. A material of one or both of the insulating layers50and52may include a polypropylene resin and/or other insulating materials. Referring toFIG. 3J, the conductive connects75are disposed in, or formed in the vias37to form the semiconductor device package1as illustrated inFIG. 1. The conductive connects75may include one or more solder balls.

FIG. 4Ais a cross-sectional view of some embodiments of a semiconductor device package2in accordance with a second aspect of the present disclosure. The semiconductor device package2is similar in some ways to the semiconductor device package1depicted inFIG. 1, and some same-numbered components are not described again with respect toFIG. 4A. In the semiconductor device package2, the conductive base101is included, while omitting an additional conductive base. A material of the conductive base101includes, for example, copper or another metal, or a metal alloy, or other conductive material. The semiconductor device package2includes a surface finish layer78on the surface101bof the conductive base101. The surface finish layer78may include any suitable conductive material (such as including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), Cu, and combinations of metals).

The conductive base101defines a cavity30in the first surface101uof the conductive base101. The cavity30has a bottom surface301. The semiconductor die20has an active surface201electrically connected to the patterned conductive layer80and a surface202disposed on the bottom surface301of the cavity30. The semiconductor die22has an active surface221electrically connected to the patterned conductive layer82and a surface222disposed on the active surface201of the semiconductor die20. The semiconductor die20is disposed on the bottom surface301of the cavity30and the semiconductor die22is disposed on the active surface201of the semiconductor die20.

The semiconductor die24has an active surface241electrically connected to the patterned conductive layer84and a surface242on the bottom surface301of the cavity30. The semiconductor die24is disposed on the bottom surface301of the cavity30. At least one of the semiconductor dies20,22and24may be a power die, and at least one of the semiconductor die20,22and24may be a control die. The first surface101uof the conductive base101is electrically connected to the active surface201of the semiconductor die20and the active surface221of the stacked semiconductor die22through the interconnection structures801and821. The stacked die structure provides for integrating a large number of components in the leadframe and a low area (e.g. surface area) of the leadframe. The active surface201of the semiconductor die20is substantially coplanar with the surface222of the semiconductor die22. The active surface201of the semiconductor die20extends along the side of the surface222of the semiconductor die22.

The protection layer70has a surface701. The patterned conductive layer80and the patterned conductive layer82are formed on the surface701of the protection layer70. The protection layer70covers at least a portion of the surface101uof the conductive base101and the semiconductor dies20,22and24and fills, at least in part, the cavity30. The interconnection structures801in the protection layer70are electrically connected to the semiconductor die20and the patterned conductive layer80. The interconnection structures821in the protection layer70are electrically connected to the semiconductor die22and the patterned conductive layer82. The interconnection structures841in the protection layer70are electrically connected to the semiconductor die24and the patterned conductive layer84. The interconnection structures841are electrically connected to the surface101uof the conductive base101and one of the patterned conductive layers80and the patterned conductive layers82.

FIG. 4Billustrates a top view of some embodiments of the semiconductor device package2depicted inFIG. 4A. InFIG. 4B, the semiconductor die20and the semiconductor die22are at least slightly laterally offset and do not perfectly overlap (e.g. corresponding sides or surfaces of the semiconductor die20and the semiconductor die22do not align). A current output by the semiconductor die20may be transferred to the conductive base101through the conductive adhesive layer48and transferred to the interconnection structures801through the patterned conductive layers80. A current output by the semiconductor die22may be transferred to the conductive base101through the semiconductor die20and the conductive adhesive layer48and transferred to the interconnection structures821through the patterned conductive layers82. The offset of the semiconductor dies20and22may be implemented as desired (e.g. may be made large or small).

FIGS. 5A-5Iillustrate some embodiments of a method of manufacturing the semiconductor device package2depictedFIG. 4A. Referring toFIG. 5A, a conductive base101is provided. The conductive base101has a first surface101uand a surface101bopposite to the first surface101u. The material of the conductive base101is, for example, copper or another metal, or a metal alloy, or other conductive material. The conductive base101defines a cavity30in the first surface101uof the conductive base101. The cavity30has a bottom surface301.

Referring toFIG. 5B, conductive adhesive layers48is disposed on the bottom surface301of the cavity30. The conductive adhesive layer48may include, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material). A semiconductor die20is disposed on the conductive adhesive layer48on the bottom surface301of the cavity30. The conductive adhesive48is used to attach the semiconductor die20to the bottom surface301of the cavity30. The semiconductor die20has an active surface201and a second surface202opposite the first surface201. A semiconductor die22has an active surface221and a second surface222opposite the first surface221. The semiconductor die22is stacked on the active surface201of the semiconductor die20through a conductive adhesive layer48. The semiconductor die24has an active surface241and a second surface242opposite the first surface241. The semiconductor die24is disposed on the conductive adhesive layer48on the bottom surface301of the cavity30.

Referring toFIG. 5C, a protection layer70is disposed on the semiconductor dies20,22and24and fills, at least in part, the cavity30. The protection layer70has a surface701. In some embodiments, the material of the protection layer70may include a polypropylene resin; however, other suitable materials may be additionally or alternatively used. The conductive layer80′ is disposed on the surface701of the protection layer70. A material of conductive layer80′ may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 5D, vias38are formed through the protection later70from the surface of the patterned conductive layer80′. The vias38may be formed, for example, by drilling. After the vias38are formed, a portion of the surface201of the semiconductor die20, a portion of the surface221of the semiconductor die22, a portion of the surface241of the semiconductor die24and a portion of the surface101uof the conductive base101are exposed.

Referring toFIG. 5E, the vias38are filled with the conductive material84, which is similar to or the same as the material of the conductive layer80′. The thickness of conductive layer80′ is increased by coating, sputtering, plating or another suitable technique.

Referring toFIG. 5F, a patterned photoresist layer74is disposed on the conductive layers80′, the surface101bof the conductive base101and the bottom surface of a portion of the protection layer70that fills in the curved structure60. The patterned photoresist layer74may include a positive photoresist or other suitable material.

Referring toFIG. 5G, vias36are formed through the protection later70from the surface of the conductive layer80′. After the vias36are formed, the conductive layers80and82and the interconnection structures801and802are formed. The material of interconnection structures801and802and conductive layers80and82may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 5H, the patterned photoresist layer74is removed by a suitable technique, such as an etching process. The upper surfaces of the interconnection structures801and821are exposed.

Referring toFIG. 5I, an insulating layer50is disposed on the first surface701of the protection layer70. The insulating layer50covers at least a portion of the patterned conductive layers80. A material of one or both of the insulating layer50may include a polypropylene resin or other insulating materials used additionally or alternatively. A surface finish layer78is disposed on the second surface101bof the conductive base101and is filled into, or is formed in the vias37. The surface finish layer78may include any suitable conductive material (such as, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), Cu, and/or combinations of metals). In at least one embodiment, the surface finish layer78may be disposed on the second surface101bof the conductive base101and cover a portion of the protection layer70that fills, at least in part, the curved structure60. In the at least one embodiment, the surface finish layer is, for example, an insulating layer, such as a solder mask. Next, the conductive connects75are filled into or formed in the vias37, thus forming the semiconductor device package2as illustrated inFIG. 4A.

FIG. 6Ais a cross-sectional view of some embodiments of a semiconductor device package3in accordance with a third aspect of the present disclosure. The semiconductor device package3is similar in some ways to the semiconductor device package2depicted inFIG. 4A, and some same-numbered components are not described again with respect toFIG. 4A. The conductive base101defines a cavity30in the first surface101uof the conductive base101. The cavity30has a bottom surface301. The semiconductor die22has an active surface221connected to the patterned conductive layer80and a surface222on the bottom surface301of the cavity30. The semiconductor die20has an active surface201connected to the patterned conductive layer82and a surface202on the active surface221of the semiconductor die22. The semiconductor die22is disposed on the bottom surface301of the cavity30and the semiconductor die20is disposed on the active surface221of the semiconductor die22.

The semiconductor die24has an active surface241connected to the patterned conductive layer84and a surface242on the bottom surface301of the cavity30. The semiconductor die24is disposed on the bottom surface301of the cavity30. One of the semiconductor dies20,22and24may be a power die, and one of the semiconductor die20,22and24may be a control die. The first surface101uof the conductive base101is electrically connected to the active surface221of the semiconductor die22and the active surface201of the stacked semiconductor die20through the interconnection structures801and821.

FIG. 6Billustrates a top view of some embodiments of the semiconductor device package3depicted inFIG. 6A. InFIG. 6B, the semiconductor die20and the semiconductor die22are at least slightly offset and do not perfectly overlap. A current output by the semiconductor die22may be transferred to the conductive base101through the conductive adhesive layer48and transferred to the interconnection structures801through the patterned conductive layers80. A current output by the semiconductor die20may be transferred to the conductive base101through the semiconductor die22and the conductive adhesive layer48and transferred to the interconnection structures821through the patterned conductive layers82. The offset of the semiconductor dies20and22may implemented as desired (e.g. may be made large or small).

FIGS. 7A-7Iillustrate some embodiments of a method of manufacturing the semiconductor device package3depicted inFIG. 6A. Referring toFIG. 7A, a conductive base101is provided. The conductive base101has a first surface101uand a surface101bopposite to the first surface101u. The material of the conductive base101includes, for example, copper or another metal, or a metal alloy, or other conductive material. The conductive base101defines a cavity30in the first surface101uof the conductive base101. The cavity30has a bottom surface301. The conductive base101defines curved structures60.

Referring toFIG. 7B, conductive adhesive layers48are disposed on the bottom surface301of the cavity30. The conductive adhesive layer48may include, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material). A semiconductor die22is disposed on the conductive adhesive layer48in the bottom surface301of the cavity30. The conductive adhesive48is used to attach the semiconductor die22to the bottom surface301of the cavity30. The semiconductor die22has an active first surface221and a second surface222opposite the first surface221. A semiconductor die20has an active surface201and a surface202opposite the first surface201. The semiconductor die20is stacked on the active surface221of the semiconductor die22through a conductive adhesive layer48. The semiconductor die24has an active first surface241and a second surface242opposite the first surface241. The semiconductor die24is disposed on the conductive adhesive layer48on the bottom surface301of the cavity30.

Referring toFIG. 7C, a protection layer70is disposed on the semiconductor dies20,22and24and fills, at least in part, the cavity30. The protection layer70has a surface701. In some embodiments, the material of the protection layer70may include a polypropylene resin; however, other suitable materials may be additionally or alternatively used. The conductive layer80′ is disposed on the surface701of the protection layer70. A material of conductive layer80′ may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 7D, vias38are formed through the protection later70from the surface of the conductive layer80′. The vias38may be formed, for example, by drilling. After the vias38are formed, a portion of the surface201of the semiconductor die20, a portion of the surface221of the semiconductor die22, a portion of the surface241of the semiconductor die24and a portion of the surface101uof the conductive base101are exposed.

Referring toFIG. 7E, the vias38are filled with the conductive material similar to, or the same as, the material of the conductive layer80′. The thickness of conductive layer80′ is increased by coating, sputtering, plating or another suitable technique.

Referring toFIG. 7F, a patterned photoresist layer74is disposed on the conductive layers80′, on the surface101bof the conductive base101, and on the bottom surface of a portion of the protection layer70that fills, at least in part, the curved structure60. The patterned photoresist layer74may include a positive photoresist or other suitable material.

Referring toFIG. 7G, vias36are formed through the protection later70from the surface of the conductive layer80′. After the vias36are formed, the conductive layers80and82and the interconnection structures801and802are formed. The material of interconnection structures801and802and conductive layers80and82may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 7H, the patterned photoresist layer74is removed by a suitable technique, such as an etching process. The first surfaces of the interconnection structures801and821are exposed.

Referring toFIG. 7I, an insulating layer50is disposed on the first surface701of the protection layer70. The insulating layer50covers at least a portion of the patterned conductive layers80. A material of one or both of the insulating layer50may include a polypropylene resin or other insulating materials used additionally or alternatively. A surface finish layer78is disposed on the surface101bof the conductive base101and filled into the vias37. The protection layer70filled in the curved structure60is exposed from the surface finish layer78when the surface finish layer78may include any suitable conductive material (such as including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), Cu, and combinations of metals). In one embodiment, the surface finish layer may be disposed on the surface101bof the conductive base101and cover the protection layer70that fills, at least in part, the curved structure60. In some embodiments, the surface finish layer is, for example, an insulating layer, such as a solder mask. Next, the conductive connects75are filled into the vias37to complete the semiconductor device package3as illustrated inFIG. 6A.

FIG. 8is a cross-sectional view of some embodiments of a semiconductor device package4in accordance with a fourth aspect of the present disclosure. The semiconductor device package4is similar in some ways to the semiconductor device package1ofFIG. 1, and some same-numbered components are not described again with respect toFIG. 8. InFIG. 8, the semiconductor device package4includes a conductive base101, semiconductor dies20,22and24, conductive adhesive layers48, protection layers70aand72a, an insulating layer50, patterned conductive layers80,82,84and86, interconnection structures801,821,841and861, and conductive connects75.

The protection layer70acovers at least a portion of the surface101uof the conductive base101and the semiconductor die20. The protection layer70ahas a surface701a. The protection layer70acovers at least a portion of the semiconductor dies22and24. The patterned conductive layer80is formed on the protection layer70aand is electrically connected to the semiconductor die20. The semiconductor die22is bonded to the patterned conductive layer80through the conductive adhesive layer48. The semiconductor die24is bonded to the patterned conductive layer80through the conductive adhesive layer48. The protection layer72ais formed on the patterned conductive layer80and on the surface701aof the protection layer70a. The protection layer72acovers at least a portion of the semiconductor die22. The patterned conductive layer82is disposed on the dielectric layer72aand is electrically connected to the semiconductor die22.

The semiconductor die20has an active surface201and a surface202. The conductive base101defines a cavity30in the first surface101uof the conductive base101. The semiconductor die20is bonded to a bottom surface301of the cavity30through the conductive adhesive layer48. The interconnection structures801are formed in the protection layer70a. The interconnection structures801are electrically connected to the surface101uof the conductive base101and the patterned conductive layer80. The active surface201of the semiconductor die20is electrically connected to the patterned conductive layer80through the interconnection structures801. The semiconductor die22has an active surface221and a surface222. The semiconductor die20is bonded to the active surface201of the semiconductor die20through the conductive adhesive layer48. The interconnection structures821are formed in the protection layer72a. The interconnection structures821are connected to the patterned conductive layer80and the patterned conductive layer82. The active surface222of the semiconductor die22is connected to the patterned conductive layer82through the interconnection structures821. The semiconductor die24has an active surface241and a surface242. The semiconductor die24is bonded to the bottom surface301of the cavity30through the conductive adhesive layer48. The active surface201of the semiconductor die20is connected to the active surface241of the semiconductor die24through the patterned conductive layers80and the interconnection structures801. A material of interconnection structures801and821and patterned conductive layer80and82may include, for example, copper or another metal, or a metal alloy, or other conductive material.

FIGS. 9A-9Lillustrate some embodiments of a method of manufacturing the semiconductor device package4depicted inFIG. 8. Referring toFIG. 9A, a conductive base101is provided. The conductive base101has a first surface101uand a surface101bopposite to the first surface101u. The conductive base101defines curved structures60. The material of the conductive base101is, for example, copper or another metal, or a metal alloy, or other conductive material. The conductive base101defines a cavity30in the first surface101uof the conductive base101. The cavity30has a bottom surface301.

Referring toFIG. 9B, a conductive adhesive layer48and a die attach film49are disposed on the bottom surface301of the cavity30. The conductive adhesive layer48may include, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material). In some embodiments, the conductive adhesive layer48may include a die attach film. A semiconductor die20is disposed on the conductive adhesive layer48in the bottom surface301of the cavity30. The conductive adhesive48is used to attach the semiconductor die20to the bottom surface301of the cavity30. The semiconductor die20has an active first surface201and a second surface202opposite the first surface201. A semiconductor die24is disposed on the die attach film49in the bottom surface301of the cavity30. The die attach film49is used to attach the semiconductor die24to the bottom surface301of the cavity30. The semiconductor die24has an active first surface241and a second surface242opposite the first surface201.

Referring toFIG. 9C, a protection layer70ais disposed on the semiconductor dies20and24and fills, at least in part, the cavity30and the curved structures60. The protection layer70ahas a surface701a. In some embodiments, the material of the protection layer70amay include a polypropylene resin; however, other suitable materials may be additionally or alternatively used. The conductive layer80′ is disposed on the surface701aof the protection layer70a. A material of conductive layer80′ may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 9D, vias38are formed through the protection later70afrom the surface of the patterned conductive layer80′. The vias38may be formed, for example, by drilling. After the vias38are formed, a portion of the surface201of the semiconductor die20, a portion of the surface241of the semiconductor die24, and a portion of the surface101uof the conductive base101are exposed.

Referring toFIG. 9E, the vias38are filled with a conductive material similar to or the same as the material of the conductive layer80′. The thickness of conductive layer80′ is increased by coating, sputtering, plating or another suitable technique.

Referring toFIG. 9F, the conductive layers80and the interconnection structures801are formed by photo-lithography techniques. The material of interconnection structures801and conductive layers80may include, for example, copper or another metal, or a metal alloy, or other conductive material. Referring toFIG. 9G, a semiconductor die22is disposed on the interconnection structures801through the conductive adhesive layer48. The semiconductor dies20and22may be a power die, and the semiconductor die24may be a control die.

Referring toFIG. 9H, a protection layer72ais disposed on the semiconductor die22and covers the interconnection structures801. The protection layer72ahas a surface721a. In some embodiments, the material of the protection layer72amay include a polypropylene resin; however, other suitable materials may be additionally or alternatively used. A conductive layer82′ is disposed on the surface721aof the protection layer72a. A material of conductive layer82′ may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 9I, vias38′ are formed through the protection later72afrom the surface of the patterned conductive layer82′. The vias38′ may be formed, for example, by drilling. After the vias38′ are formed, a portion of the surface221of the semiconductor die22and a portion of the surface of the interconnection structures801are exposed.

Referring toFIG. 9J, the vias38are filled with the conductive material similar to, or the same as, the material of the conductive layer82′. The thickness of conductive layer82′ is increased by coating, sputtering, plating or another suitable technique.

Referring toFIG. 9K, the conductive layers82and the interconnection structures821are formed by photo-lithography techniques. The material of interconnection structures821and conductive layers82may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 9L, an insulating layer50is disposed on the first surface721of the protection layer72a. The insulating layer50covers at least a portion of the patterned conductive layers82. A material of one or both of the insulating layer50may include a polypropylene resin or other insulating materials used additionally or alternatively. Next, the conductive connects75are filled into or formed in the vias37, thus forming the semiconductor device package4as illustrated inFIG. 8.

FIGS. 10A-10Millustrate some embodiments of a method of manufacturing a semiconductor device package5according to a fifth aspect of the present disclosure. Referring toFIG. 10A, a conductive base101is provided. The conductive base101has a first surface101uand a surface101bopposite to the first surface101u. The conductive base101defines upper curved structures60′. The material of the conductive base101is, for example, copper or another metal, or a metal alloy, or other conductive material. The cavity30is defined from the first surface101uof the conductive base101. The cavity30has a bottom surface301.

Referring toFIG. 10B, conductive adhesive layers48is disposed on the bottom surface301of the cavity30. The conductive adhesive layer48may include, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material). A semiconductor die20is disposed on the conductive adhesive layer48in the bottom surface301of the cavity30. The conductive adhesive48is used to attach the semiconductor die20to the bottom surface301of the cavity30. The semiconductor die20has an active first surface201and a second surface202opposite the first surface201. A semiconductor die24is disposed on the conductive adhesive layer48in the bottom surface301of the cavity30. The conductive adhesive48is used to attach the semiconductor die24to the bottom surface301of the cavity30. The semiconductor die24has an active first surface241and a second surface242opposite the first surface201. In some embodiments, the conductive adhesive layer48may be a die attach film. In some embodiments, the semiconductor die20may be a power die and the semiconductor die24may be a controller.

Referring toFIG. 10C, a protection layer70ais disposed on the semiconductor dies20and24and fills, at least in part, the cavity30and the upper curved structures60′. The protection layer70ahas a surface701a. In some embodiments, the material of the protection layer70amay include a polypropylene resin; however, other suitable materials may be additionally or alternatively used. The conductive layer80′ is disposed on the surface701aof the protection layer70a. A material of conductive layer80′ may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 10D, vias38are formed through the protection later70afrom the surface of the patterned conductive layer80′. The vias38may be formed, for example, by drilling. After the vias38are formed, a portion of the surface201of the semiconductor die20, a portion of the surface241of the semiconductor die24, and a portion of the surface101uof the conductive base101are exposed.

Referring toFIG. 10E, the vias38are filled with the conductive material similar to, or the same as, the material of the conductive layer80′. The thickness of conductive layer80′ is increased by coating, sputtering, plating or another suitable technique.

Referring toFIG. 10F, the conductive layers80and the interconnection structures801are formed by photo-lithography techniques. The material of interconnection structures801and conductive layers80may include, for example, copper or another metal, or a metal alloy, or other conductive material. A portion of the conductive base101below the upper curved structures60′ is removed by etching to form the curved structures60.

Referring toFIG. 10G, a semiconductor die22is disposed on the interconnection structures801through the conductive adhesive layer48. At least one of the semiconductor dies20,22and24may be a power die, and at least one of the semiconductor die20,22and24may be a control die.

Referring toFIG. 10H, a protection layer72ais disposed on the semiconductor die22and the surface101bof the conductive base101. The protection layer72aalso covers the interconnection structures801and fills, at least in part, the curved structures60. The protection layer72ahas a surface721aand a surface721b. In some embodiments, the material of the protection layer72amay include a polypropylene resin; however, other suitable materials may be additionally or alternatively used. A conductive layer82′ is disposed on the surface721aof the protection layer72aand a conductive layer84is disposed on the surface721bof the protection layer72a. A material of conductive layer82′ and84may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 10I, vias38′ are formed through the protection later72afrom the surface of the patterned conductive layer82′. The vias38′ may be formed, for example, by drilling. After the vias38′ are formed, a portion of the surface221of the semiconductor die22and a portion of the surface of the interconnection structures801are exposed.

Referring toFIG. 10J, the vias38are filled with the conductive material similar to, or the same as, the material of the conductive layer82′. The thickness of conductive layer82′ is increased by coating, sputtering, plating or another suitable technique. Referring toFIG. 10K, the conductive layers82and the interconnection structures821are formed by photo-lithography techniques. The material of interconnection structures821and conductive layers82may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 10L, an insulating layer50is disposed on the first surface721of the protection layer72a. The insulating layer50covers at least a portion of the patterned conductive layers82. A material of one or both of the insulating layer50may include a polypropylene resin or other insulating materials used additionally or alternatively. Referring toFIG. 10M, the conductive connects75are filled into the vias37. Next, a surface finish layer78is formed on the conductive layer84to form the semiconductor device package5. The surface finish layer78may include any suitable conductive material (such as, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), Cu, and combinations of metals).

FIGS. 11A-11Iillustrate some embodiments of a method of manufacturing a semiconductor device package6according to a sixth aspect. Referring toFIG. 11A, conductive bases101and102are provided. The conductive base101has a first surface101uand a surface101bopposite to the first surface101u. The conductive base102has a first surface102uand a surface102bopposite to the first surface102u. The material of the conductive bases101and102includes, for example, copper or another metal, or a metal alloy, or other conductive material. The connecting element90is formed, for example, by drilling (e.g. by drilling at least two holes into an initial conductive base, thereby forming the separate conductive bases101and102and the connecting element90). The conductive base101defines a cavity30in the first surface101uof the conductive base101, and the conductive base102defines a cavity in the first surface102uof the conductive base102. The cavity30has bottom surface301. The cavity32has an upper surface321. The conductive base101defines one or more curved structures60. Curved structures60of the conductive base101are smoothed and can help to redistribute stress to avoid damage to the protection layer70during lamination. The structure of the conductive base101may be formed in a same or similar manner as the conductive base102, such as in any appropriate manner of forming a conductive based described herein.

Referring toFIG. 11B, conductive adhesive layers48are disposed on the bottom surface301of the cavity30, on the surface101bof the conductive base101and on the upper surface321of the cavity32. The conductive adhesive layer48may include, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material). A semiconductor die20is disposed on the conductive adhesive layer48in cavity30. The conductive adhesive48is used to attach the semiconductor die20to the bottom surface301of the cavity30. The semiconductor dies22,24and26may be disposed through the attaching of the conductive adhesive layer48.

Referring toFIG. 11C, a protection layer70is disposed on the semiconductor dies20,22and24and fills, at least in part, the cavities30and32. The protection layer70has a first surface701and a second surface702. In some embodiments, the material of the protection layer70may include a polypropylene resin; however, other suitable materials may be additionally or alternatively used. The conductive layer80′ is disposed on the surface701of the protection layer70and the conductive layer82′ is disposed on the second surface702of the protection layer70. A material of conductive layer80′ and82′ may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 11D, vias38are formed through the protection later70from the surface of the patterned conductive layers80′ and82′. The vias38may be formed, for example, by drilling. After the vias38are formed, a portion of the surface201of the semiconductor die20, a portion of the surface221of the semiconductor die22, a portion of the surface241of the semiconductor die24and a portion of the surface101uof the conductive base101are exposed.

Referring toFIG. 11E, the vias38are filled, at least in part, with the conductive material similar to or the same as the material of the conductive layers80′ and82′. The thickness of conductive layers80′ and82′ are increased by coating, sputtering, plating or another suitable technique.

Referring toFIG. 11F, a patterned photoresist layer74is disposed on the conductive layers80′ and a patterned photoresist layer76is disposed on the conductive layer82′. The patterned photoresist layers74and76may include a positive photoresist or other suitable material.

Referring toFIG. 11G, a portion of each of the conductive layers80′ and82′ is removed. After the removal, the conductive layers80and82and the interconnection structures801and821are formed. Referring toFIG. 11H, the patterned photoresist layers74and76are removed by a suitable technique, such as an etching process. After etching, a portion of the first surface701of the protection layer70is exposed and a portion of the second surface702of the protection layer70is exposed.

Referring toFIG. 11I, an insulating layer50is disposed on the first surface701of the protection layer70and an insulating layer52is disposed on the second surface702of the protection layer70. The insulating layer50covers at least a portion of the patterned conductive layers80and the insulating layer52covers at least a portion of the patterned conductive layers82. A material of one or both of the insulating layers50and52may include a polypropylene resin or other insulating materials used additionally or alternatively. Next, the conductive connects75are filled into or formed in the vias37, thus forming the semiconductor device package6. The conductive connects75may include one or more solder balls. The vias37are disposed on the patterned conductive layers80.

FIGS. 12A-12Iillustrate some embodiments of a method of manufacturing a semiconductor device package7according to a seventh aspect. Referring toFIG. 12A, conductive bases101and102are provided. The conductive base101has a first surface101uand a surface101bopposite to the first surface101u. The conductive base102has a first surface102uand a surface102bopposite to the first surface102u. The material of the conductive bases101and102include, for example, copper or another metal, or a metal alloy, or other conductive material. The connecting element90is formed, for example, by drilling (e.g. by drilling at least two holes into an initial conductive base, thereby forming the separate conductive bases101and102and the connecting element90). The cavity30is defined from the first surface101uof the conductive base101. The cavity32is defined from the first surface102uof the conductive base102. The cavity30has bottom surface301. The cavity32has an upper surface321. The conductive base101defines one or more curved structures60. Curved structures60of the conductive base101are smoothed, and can help to redistribute stress to avoid damage to the protection layer70during lamination. The structure of the conductive base101may be formed in a same or similar manner as the conductive base102, such as in any appropriate manner described herein.

Referring toFIG. 12B, conductive adhesive layers48are disposed on the bottom surface301of the cavity30, on the surface101bof the conductive base101and on the upper surface321of the cavity32. The conductive adhesive layer48may include, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material). A semiconductor die20is disposed on the conductive adhesive layer48in cavity30. The conductive adhesive48is used to attach the semiconductor die20to the bottom surface301of the cavity30. The semiconductor dies22,24and26may be disposed through the attaching of the conductive adhesive layer48.

Referring toFIG. 12C, a protection layer70is disposed on the semiconductor dies20,22and24and fills, at least in part, the cavities30and32. The protection layer70has a first surface701and a second surface702. In some embodiments, the material of the protection layer70may include a polypropylene resin; however, other suitable materials may be additionally or alternatively used. The conductive layer80′ is disposed on the surface701of the protection layer70and the conductive layer82′ is disposed on the second surface702of the protection layer70. A material of conductive layer80′ and82′ may include, for example, copper or another metal, or a metal alloy, or other conductive material.

Referring toFIG. 12D, vias38are formed through the protection later70from the surface of the patterned conductive layers80′ and82′. The vias38may be formed, for example, by drilling. After the vias38are formed, a portion of the surface201of the semiconductor die20, a portion of the surface221of the semiconductor die22, a portion of the surface241of the semiconductor die24and a portion of the surface101uof the conductive base101are exposed.

Referring toFIG. 12E, the vias38are filled with the conductive material similar to, or the same as, the material of the conductive layers80′ and82′. The thickness of conductive layers80′ and82′ are increased by coating, sputtering, plating or another suitable technique.

Referring toFIG. 12F, a patterned photoresist layer74is disposed on the conductive layers80′ and a patterned photoresist layer76is disposed on the conductive layer82′. The patterned photoresist layers74and76may include a positive photoresist or other suitable material.

Referring toFIG. 12G, a portion of the conductive layers80′ and82′ is removed. After the removal, the conductive layers80and82and the interconnection structures801and821are formed. Referring toFIG. 12H, the patterned photoresist layers74and76are removed by a suitable technique, such as an etching process. After etching, a portion of the first surface701of the protection layer70is exposed and a portion of the second surface702of the protection layer70is exposed.

Referring toFIG. 12I, an insulating layer50is disposed on the first surface701of the protection layer70and an insulating layer52is disposed on the second surface702of the protection layer70. The insulating layer50covers at least a portion of the patterned conductive layers80and the insulating layer52covers at least a portion of the patterned conductive layers82. A material of one or both of the insulating layers50and52may include a polypropylene resin or other insulating materials used additionally or alternatively. Next, the conductive connects75are filled into or formed in the vias37to form the semiconductor device package7. The conductive connects75may include one or more solder balls. The vias37are disposed on the patterned conductive layers80.

Two surfaces or sides can be deemed to be aligned if a displacement between the two surfaces is no greater than 0.5 μm, no greater than 1 μm, no greater than 5 μm, no greater than 10 μm, or no greater than 15 μm. In the description of some embodiments, a component provided “on” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.