Motor driving circuit

In a motor driving circuit in which a first NMOS and a second NMOS coupled in series to the final output stage to drive a motor are driven and a common node of the source of the first NMOS and the drain of the second NMOS serves as the final output, the motor driving circuit comprises: a first PMOS and a third NMOS having a common node of drains thereof coupled to the gate of the first NMOS; a second PMOS and a fourth NMOS having a common node of drains thereof coupled to the gate of the third NMOS; one or more PMOSs having drains coupled to the gate of the third NMOS which are turned on to charge the gate capacity of the third NMOS when the final output is low and a returned off when gate capacity of the third NMOS is charged; and one or more NMOSs having drains coupled to the gate of the third NMOS which are turned on to discharge the gate capacity of the third NMOS when the final output is high and are turned off when the gate capacity of the third NMOS is discharged and is characterized in that the gate of the first NMOS is coupled to the final output through a clamp circuit and the source of the third NMOS and the gate of the third NMOS through a clamp circuit are coupled to the final output.

TECHNICAL FIELD

The present invention relates to a motor driving circuit that can drive a transistor used as a driver for a motor with a low electric power consumption and operating at high speed.

BACKGROUND ART

FIG. 4shows a conventional motor driving circuit. A coil as a load is coupled to the outputs of transistors NMOS101and NMOS102which are provided at the final output stage of this motor driving circuit. The motor control is performed by controlling the current supplied to the coil (The motor is not shown in the drawing). The configuration of the motor driving circuit shown inFIG. 4will be described as follows. The NMOS101and the NMOS102are drivers provided at the final output stage and a common node of the source of NMOS101and the drain of NMOS102constitutes the final output. A supply voltage107is coupled to the drain of NMOS101, while an output from a common drain node of PMOS103and NMOS104is coupled to the gate of NMOS101. Further, a logic circuit112is coupled to the gate of NMOS102, and a logic circuit110is coupled to the gate of the PMOS103respectively. Here, Zener diodes108and109functioning as clamp circuits are also used for ensuring a potential difference (VgS) between the gate and the source of NMOS101and a potential difference between the gate and the source of NMOS104until a reverse saturation current starting to be supplied respectively to the Zener diodes. At the same time, the Zener diodes are also functioning to prevent an over-voltage being applied to respective VgSof NMOS101and the NMOS104. Finally, the gate of a PMOS105is coupled to a logic circuit111and the gate voltage of an NMOS106is coupled to a logic circuit113. The final output is determined in accordance with the state of an input voltage from the logic circuits110,111,112and113.

Now, an operation of the conventional motor driving circuit shown inFIG. 4will be described below together with a voltage wave form diagrams of the motor driving circuit shown inFIG. 5. The wave form diagram ofFIG. 5shows, from an upper part, the low/high of the final output and the gate voltages of NMOS101, the NMOS102, the PMOS103, the NMOS104, the PMOS105and the NMOS106(that is, when the gate voltage of NMOS is high, the NMOS is turned on). In a section of (A) shown inFIG. 5, the final output is high. That is, the NMOS101as the driver constituting the final output stage is in on-state and the NMOS102is in off-state. Since the NMOS101is in on-state, the output from the common drain node of the PMOS103and the NMOS104is high. Consequently, the PMOS103is in on-state and the NMOS104is in off-state, that is, the gate voltage of the PMOS103and the NMOS104is low. Further, since the NMOS104is in off-state, the PMOS105is in on-state and the NMOS106is in a state of being tuned off. Further, in a section (B) shown inFIG. 5, the final output is low. In comparison with the section (A) in which the final output is high, the on/off states of NMOS101, the NMOS102, the PMOS103, the NMOS104, the PMOS105and the NMOS106and the states of input voltage to the gates of the respective transistors come to be the inverted states to those described in the case of the section (A).

The final output is fed back to the gate of NMOS101through the Zener diode108, and to the gate of NMOS104through the Zener diode109and the source of NMOS104in order to control the gage voltage of NMOS101based on the source of NMOS101and the source of NMOS104as the references. Thus, the abnormal state of the final output can be detected by the transistor used for the motor driving circuit, on top of this, using the transistors together with the clamp circuits eliminates the need of designing the devices used for the motor with a high voltage tolerance level.

In the above-described circuit operation, as to the high/low switching of the low of the final output from the common node of NMOS101and the NMOS102, the NMOS104needs to be switched to on from off-state to on-state. On the other hand, in order to switch the final output from Low to High, the NMOS104needs to be switched from on-state to off-state. Accordingly, one of the requirements of rapid reflection of the input is to the final output is to switch the NMOS104on and off rapidly, that is, the gate capacity and the parasitic capacity of NMOS104need to be charged and discharged at high speed.

Here, from Q=IT (Q: quantity of electric charge; I: current, T: time), quick electric charge of the gate capacity and the parasitic capacity of a MOS transistor can be performed by increasing the quantity of current that is supplied to the gate of the MOS transistor. In order to solve this problem, current flow amount from the drain of the PMOS105, which is coupled to NMOS104, needs to increase so as to improve a charging speed of the gate capacity and the parasitic capacity of NMOS104. On the other hand, if the drain current of the drain of NMOS106coupled to the gate of NMOS104is increased, a discharging speed of the gate capacity and the parasitic capacity of NMOS104can be improved. Therefore, from a current equation of a MOS transistor in a saturated state Ids=K(Vgs−Vth)2(K: constant, Vth: threshold voltage of PMOS), one of the solution is to increase the drain current of the PMOS105so as to increase Vgs, however, since a drive operation with a low electric power consumption is desirable today, it is not preferable to increase a supply voltage115coupled to a source. In the above-described formula, as K is a constant proportional to the width of the gate forming the transistor, the quantity of current can be also increased by expanding the width of the gate. Further, from I=R/V in accordance with the Ohm's law, by lowering the resistance value of a resistance114, which is coupled to the source of the PMOS105, it is possible to increase the current from the drain of the PMOS105.

DISCLOSURE OF THE INVENTION

Problems that the Invention is to Solve

Here, in case of the output being in low-state, the gate capacity and the parasitic capacity of NMOS104are charged with the drain current of the PMOS105so that the NMOS104needs to be kept turned on. However, when the size (W/L ratio) of the transistor of the PMOS105is changed to drive the NMOS104at high speed or the resistance114of the source side of the PMOS105is changed for the purpose of increasing the drain current of the PMOS105, a quantity of the reverse saturation current flow of the Zener diode circuit109is increased for keeping the NMOS104with on-state, resulting in the generation of a current flowing in an output direction at the final output stage. Thus, a electric power consumption is increased. Further, in case of increasing the supply voltage115and an input signal of the gate voltage of the PMOS105, a high speed driving operation of NMOS104can be realized. However, this method is not preferable in view of the electric power consumption. This is because when the drain current of the PMOS105decreases, a reverse saturation current comes to decrease in the Zener diode109to lower a electric power consumption, however, the NMOS104cannot be driven at high speed. Further, the NMOS transistors101and102constituting the final output stage might be simultaneously turned on due to the delay of the input, which causes a through current flow, resulting that the electric power consumption is increased. Accordingly, there is a possibility of the device being broken.

By considering the above-described conventional circumstances, the present invention is devised to solve drawbacks contemplated in the related arts, and accordingly, it is a first object of the present invention to provide a motor driving circuit having low electric power consumption and operating at high speed. It is a second object to provide a semiconductor device having the above-described motor driving circuit. It is a third object of the present invention to provide a motor device including the above-described semiconductor device, a coil controlled by the semiconductor device and a motor in which the rotating speed of a rotor is determined by a magnetic field generated in the coil.

Means for Solving the Problems

The above-described first object can be realized by a motor driving circuit for driving a motor by driving a first NMOS and a second NMOS coupled in series to the final output stage where a common node of the source of the first NMOS and the drain of the second NMOS serves as the final output. The motor driving circuit comprises: a first PMOS and a third NMOS having a common node of drains thereof coupled to the gate of the first NMOS; a second PMOS and a fourth NMOS having a common node of drains thereof coupled to the gate of the third NMOS; one or more PMOSs having drains coupled to the gate of the third NMOS which are turned on to charge the gate capacity of the third NMOS when the final output is low and are turned off when gate capacity of the third NMOS is charged; and one or more NMOSs having drains coupled to the gate of the third NMOS which are turned on to discharge the gate capacity of the third NMOS when the final output is high and are turned off when the gate capacity of the third NMOS is discharged and is characterized in that the gate of the first NMOS is coupled to the final output through a clamp circuit and the source of the third NMOS and the gate of the third NMOS through a clamp circuit are coupled to the final output. According to this structure, a switching speed can be accelerated with low electric power consumption.

The first object can be achieved by the motor driving circuit according to claim1, wherein the clamp circuit is a Zener diode as the invention defined in claim2.

The first object can be also achieved by the motor driving circuit according to claim1or2, characterized in that the motor driving circuit includes the first NMOS and the second NMOS as the invention defined in claim3.

The second object can be achieved by a semiconductor device having the motor driving circuit according to any one of claims1to3, as the invention defined in claim4.

The NMOS provided in the final output stage is provided separately from a circuit part for driving the NMOS of the final output stage or provided in the same semiconductor device. Since a large quantity of current is ordinarily supplied to the NMOS in the final output stage, the circuit part for driving the NMOS of the final output stage is provided in an external part. Thus, even when an over-current is supplied to the NMOS in the final output stage, the circuit part for driving the NMOS in the final output stage hardly receives its influence.

The third object can be achieved by a motor device including the semiconductor device according to claim4and a motor having a coil driven by the semiconductor device, as the invention defined in claim5.

Advantage of the Invention

The motor driving circuit can be realized in which a high speed operation can be performed with a low consumer electric power and a through current is not supplied to a transistor forming the final output state so that there is no fear that elements used for the structure may be possibly broken.

DESCRIPTION OF REFERENCE NUMERALS AND SIGNS

BEST MODE FOR CARRYING OUT THE INVENTION

Now, the best mode for carrying out the present invention will be described below.FIG. 1shows a motor driving circuit according to the present invention. A coil as a load is coupled to an output from an NMOS1and an NMOS2which are provided at the final output of the motor driving circuit. An electric current supplied to the coil is controlled to control a motor which is not shown in the drawing. An output at the final output stage might be within a range between a zero potential of a ground coupled to the source of NMOS2and a potential of a supply voltage7coupled to the drain of NMOS1.

In comparing the motor driving circuit according to the present invention shown inFIG. 1with the conventional motor driving circuit shown inFIG. 4, a plurality of charging means and a plurality of discharging means are provided as compared withFIG. 4, where the PMOS105corresponds to a charging means and the NMOS106corresponds to a discharging means. Those means are respectively provided for charging the gate capacity and the parasitic capacity of NMOS4, which is corresponding to the NMOS104inFIG. 4, whose drain is coupled to the gate of NMOS1coupled in series to the final output stage, which is corresponding to the NMOS101inFIG. 4. Now, the structure of the motor driving circuit according to the present invention will be described below.

InFIG. 1, the final output stage includes the NMOS1and the NMOS2. A common node of the source of NMOS1and the drain of NMOS2constitutes the final output. A common node of the drain of a PMOS3and the drain of NMOS4is coupled to the gate of NMOS1. A logic circuit12is coupled to the gate of NMOS2, and a logic circuit10is coupled to the gate of the PMOS3. A clamp circuit8ais a protecting the circuit for preventing Vgsof NMOS1from exceeding a predetermined level, where a Zener diode or a diode might be employed. A clamp circuit9ais provided between the gate and the source of NMOS4for the same purpose. A common node of the drains of a PMOS5aand a PMOS5band a common node of the drains of an NMOS6aand an NMOS6bare coupled to the gate of NMOS4. The gate capacity and the parasitic capacity of NMOS4are charged by the drain current of the PMOS5aand the PMOS5band discharged by the drain current of NMOS6aand the NMOS6b. A logic circuit11ais coupled to the gate of the PMOS5a. Further, to the source of the PMOS5a, a supply voltage15is coupled through a resistance14a, to the gate of the PMOS5b, a logic circuit11bis coupled, to the source of the PMOS5b, the supply voltage15is coupled through a resistance14b, to the gate of NMOS6a, a logic circuit13ais coupled, and to the gate of NMOS6b, a logic circuit13bis coupled where the sources of NMOS6aand the NMOS6bare respectively grounded.

The final output is fed back to the gate of NMOS1through the clamp circuit8a, and fed back to the gate of NMOS4through the source of NMOS4and the clamp circuit9. This is because it is possible to control the gage voltage of NMOS1in accordance with the source potential of NMOS1and the NMOS4which are used for reference voltages. Thus, the abnormal state of the final output can be detected by the transistors that are used for the motor driving circuit, using said transistors together with the clamping circuits can prevent the devices used for the motor drive circuit from being applied a voltage that is exceeding a withstanding voltage.

Now, an operation of the motor driving circuit according to the present invention shown inFIG. 1will be described below by employing a voltage wave form diagram of the motor driving circuit according to the present invention shown inFIG. 2. The wave form diagram ofFIG. 2shows, from an upper part, the states of low/high of the final output and the gate voltages of NMOS1, the NMOS2, the PMOS3, the NMOS4, the PMOS5a, the PMOS5b, the NMOS6aand the NMOS6b(that is, when the gate voltage of NMOS is high, the NMOS is turned on). In a section of (A1) shown inFIG. 2, the final output is high, and the NMOS1as a driver constituting the final output stage is held in a on-state except a moment immediately before the section of (A1) is changed to a section shown in (B), in other words, a section immediately before the final output is switched from the high to the low. On the other hand, the NMOS2is always held in off-state in the same section (A1). When the NMOS1is turned on, an output from the common node of the drains of the PMOS3and the NMOS4is high, so that the PMOS3is on-state and the NMOS4is off-state. When the NMOS4is turned off, the PMOS5aand the PMOS5bare off-states. On the other hand, as for the NMOS6aand the NMOS6bas discharging means of NMOS4, the NMOS6ais in on-state except a section immediately before the change from the section (A1) to the section (B) and the NMOS6bis always in a off-state. In this operation, discharging the gate capacity and the parasitic capacity in order to maintain the final output in a high level, in other words, in order to maintain the NMOS4in a off-state, this is carried out only by the NMOS6a. An operation of NMOS6bwill be described below.

At the moment immediately before the section (A1) is changed to the section (B) shown inFIG. 2, that is, at the moment immediately before the final output is switched from the high to the low, the NMOS6ais turned off and the PMOS5aand the PMOS5bare turned on. The gate capacity and the parasitic capacity of NMOS4are charged by two sets of the charging means. After the gate capacity and the parasitic capacity are charged, the on-state of NMOS4is maintained only by a voltage from the drain of the PMOS5ain order to keep the final output in a low level where the PMOS5bis off-state. Here, to ensure Vgsof NMOS4for maintaining the NMOS4in a on-state, the drain current of the PMOS5ais desirably at the level slightly more than a threshold of a reverse current being generated in the clamp circuit9. Further, the drain current from the drain of the PMOS5bthat is turned on only when the gate capacity and the parasitic capacity of NMOS4are charged is determined depending on factors such as the resistance14band the supply voltage15. Further, inFIG. 2, when the state of NMOS4is changed from off to on, the state of the PMOS3is changed from on to off at the same time. Thus, the gate voltage of NMOS1is determined. The NMOS2has a little delay to a timing of NMOS1for switching from on to off not to generate a through current to the NMOS1. Then, the final output becomes a low level simultaneously with the change of NMOS2from off to on.

In the section of (B) shown inFIG. 2, the final output is low where the NMOS1is in off-state and the NMOS2is in on-state except a section immediately before the section of (B) is changed to a section of (A2). In the section shown in (B), since the NMOS1is always off-state, the outputs from the PMOS3and the NMOS4are low, and the PMOS3is in off-state and the NMOS4is in on-state. Since the NMOS4is turned on, the charging means for the gate capacity and the parasitic capacity of NMOS4are activated. However, as described previously, after the NMOS4is turned on, Vgsof NMOS4is ensured only by the PMOS5a, so that only the PMOS5ais in on-state. The NMOS2is turned off at a timing earlier than that of NMOS1, being described later on, so that a through current by the supply voltage7and the NMOS1is not generated.

When the section of (B) is changed to the section of (A2), that is, the final output is switched from the low to the high, the NMOS1is turned on, so that the PMOS3is in on-state and the NMOS4is in off-state. Accordingly, the discharging means for discharging the gate capacity and the parasitic capacity of NMOS4are activated. At this time, from the need of operating the final output at high speed, which requires discharging the gate capacity and the parasitic capacity of NMOS4instantaneously by activating the two discharging means of NMOS6aand the NMOS6b. After the parasitic capacity of NMOS4is discharged, the NMOS6bis stopped. Even when a voltage is applied to the gate voltage to control the discharging means, any factor of consuming an electric power hardly exists except a leakage current between the gate and the source of NMOS4. In this regards, the generation of a current in the output direction of the final output is not suppressed thereby to decrease the electric power consumption. However, due to a plurality of applying means for the gate voltage being provided, the high speed discharge of the gate capacity and the parasitic capacity of NMOS4can be achieved. This is especially effective when the supply voltage15is not a large power source sufficiently from the need of achieving a driving operation by a low voltage or when the large gate voltage of NMOS6aand the NMOS6bcannot be obtained from the logic circuits13aand13b.

In the conventional motor driving circuit, a circuit design choice must be selected from large electric power consumption for ensuring high speed characteristics, or low electric power consumption by spoiling the high speed characteristics. However, the motor driving circuit according to the present invention ensures the high speed characteristics of an output in response to an input without spoiling the low electric power consumption.

As for the continuous generation of drain current of NMOS of a ground side in the final output stage or a current in the output direction of the final output, this is inevitable thing for the motor driving circuit having the final output stage constituted only by NMOS. This is because the voltage of the gate of NMOS provided in the final output stage must be driven by referring to the source of NMOS of a power source side, which is provided in the final output stage, and for this reason, the final output is reflected to the motor driving circuit. In such a case, since the final output is coupled to the source of NMOS for discharging the NMOS at the power source side, being provided in the final output stage, the gate voltage of NMOS for turning off the NMOS at the power source side must be continuously held. Therefore, the drain current of NMOS of a ground side in the final output stage or a current in the output direction of the final output is continuously generated. As to the above-described PMOS5bor the NMOS6b, such as used for activating only for a predetermined period, it is possible to employ a plurality sets of charging means or discharging means.

A second embodiment of the present invention is shown inFIG. 3. InFIG. 3, Zener diodes are used for the clamp circuits of the motor driving circuit, and the discharging means are modified in comparison of the present invention as has been shown inFIG. 1. More specifically to say, as compared with the motor driving circuit according to the present invention shown inFIG. 1, the NMOS6band the logic circuit13bare removed, while provided are an NMOS6and an NMOS16mirror-coupled thereto, a PMOS18aand a PMOS18bcoupled to the gates of NMOS6and the NMOS16, logic circuits19aand18b, and resistances20aand20b. Since the characteristics of the reverse breakdown voltage of the Zener diodes are desirable for the clamp circuits, the Zener diodes are used for the clamp circuits. As the charging means for the gate capacity and the parasitic capacity of an NMOS4, there provided a single path for a drain current of a PMOS. As a discharging means for the gate capacity and the parasitic capacity of NMOS4, the gate voltage of the mirror-coupled NMOS is adjusted in the levels of three stages. InFIG. 3, components corresponding to those shown inFIG. 1are designated by the same reference numerals shown inFIG. 1.

By employing the second embodiment of the motor driving circuit according to the present invention shown inFIG. 3, an inventor of this invention can reduce a time change at the output in response to an input from 1 μ second to about 0.4 μ second as compared with the motor driving circuit shown inFIG. 4, and a current in the output direction from the final output for maintaining the final output in a low level was reduced to 0.3 mA from 0.7 mA, resulting in that a switching operation at high speed and a low power consumption can be achieved.

Further, though not shown in the drawing, if the motor device including a semiconductor device having the motor driving circuit of the present invention and the motor having a coil driven by the semiconductor device are employed for an electronic device with having the motor device, such as a printer, a good operation performance can be seen since a control signal for the semiconductor device with the motor driving circuit can reach a desired rotating speed as an output of the motor device more faster than that of being performed in a conventional device.

The present invention is not limited to the above-described embodiments but any modification in design shall be within a scope of this invention such as described in claims.