Semiconductor package and method for manufacturing the same

A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a semiconductor package structure and a manufacturing method, and more particularly to a semiconductor package structure including a conductive pillar exposed from an encapsulant, and a method for manufacturing the semiconductor package structure.

2. Description of the Related Art

In the present fan-out process, a semiconductor die is disposed in a “face up” manner on a carrier. The semiconductor die includes a plurality of conductive pillars on an active surface opposite to the carrier. Then, a molding compound is applied to cover the semiconductor die, the conductive pillars, and the carrier. After such molding operation, the molding compound is thinned to expose upper surfaces of the conductive pillars (by, e.g., a grinding process). Then, a redistribution layer (RDL) is formed on the molding compound to contact the conductive pillars. However, since the conductive pillars may not have a consistent height, it is challenging to thin the molding compound to ensure that all the upper surfaces of the conductive pillars are exposed.

SUMMARY

In some embodiments, a semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.

In some embodiments, a semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant, a dielectric layer and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the die. The encapsulant covers the semiconductor die and the conductive pillar. The dielectric layer is disposed on the encapsulant. The dielectric layer includes a protrusion surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.

In some embodiments, a method for manufacturing a semiconductor package structure includes (a) disposing a sacrificial component on a carrier and disposing a dielectric material to cover the sacrificial component and the carrier; (b) attaching a semiconductor die to the carrier, wherein the semiconductor die includes at least one conductive pillar disposed adjacent to an active surface of the semiconductor die, and the conductive pillar penetrates through the dielectric material to contact the sacrificial component; (c) forming an encapsulant to cover the semiconductor die; (d) removing the carrier, the sacrificial component and the dielectric material to expose the conductive pillar; and (e) forming a circuit structure to electrically connect to the conductive pillar.

DETAILED DESCRIPTION

At least some embodiments of the present disclosure disclose a semiconductor package structure includes at least one semiconductor die, at least one conductive pillar disposed on the semiconductor die, and an encapsulant covering the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the respective conductive pillar. At least some embodiments of the present disclosure further disclose techniques for manufacturing the semiconductor package structure.

In a comparative fan-out process, a semiconductor die is disposed in a “face up” manner on a carrier. That is, the semiconductor die has an active surface and a back side surface opposite to the active surface, and the back side surface of the semiconductor die is attached (e.g., adhered) to the carrier. The semiconductor die includes a plurality of conductive pillars on the active surface. Then, a molding compound is applied to cover the semiconductor die, the conductive pillars, and the carrier. In other words, an upper surface of the molding compound is higher than upper surfaces of the conductive pillars, since the molding compound covers the conductive pillars.

After the molding operation, a grinding operation is conducted to remove an upper part of the molding compound that is disposed on the upper surfaces of the conductive pillars, to thin the molding compound and expose the upper surfaces of the conductive pillars. In one embodiment, after grinding, the upper surface of the molding compound may be substantially coplanar with the upper surfaces of the conductive pillars if the conductive pillars have a consistent height. However, in some embodiments, the conductive pillars may not have a consistent height, especially when the aforementioned process is used for packaging a plurality of semiconductor dice having different sizes at the same time. As a result, the upper surfaces of the conductive pillars of the semiconductor dice may not be coplanar with each other. Thus, after the grinding operation, a portion of the conductive pillars may still be embedded in the molding compound and the upper surfaces of these conductive pillars may not be exposed from the molding compound. A redistribution layer (RDL) is formed on the molding compound and may not contact and electrically connect the unexposed conductive pillars, which results in an open circuit.

The present disclosure addresses at least the above concerns and provides an improved semiconductor package structure, and improved techniques for manufacturing the semiconductor package structure. In the manufacturing process of the semiconductor package structure, the grinding operation can be omitted, while each one of upper surfaces of conductive pillars can be exposed.

FIG. 1illustrates a cross-sectional view of a semiconductor package structure1according to some embodiments of the present disclosure.FIG. 2illustrates an enlarged view of an area A inFIG. 1. The semiconductor package structure1may include at least one semiconductor die (e.g., a first semiconductor die12and a second semiconductor die13), at least one conductive pillar (e.g., a first conductive pillar14and a second conductive pillar15), an encapsulant16, a first dielectric layer24, a first circuit structure22, a second dielectric layer28, a second circuit structure26, a third dielectric layer29, and at least one external connector294.

As shown inFIG. 1, the semiconductor package structure1may include the first semiconductor die12and the second semiconductor die13. The first semiconductor die12has an active surface121, a back side surface122opposite to the active surface121, and a lateral surface123extending between the active surface121and the back side surface122. A structure of the second semiconductor die13is similar to that of the first semiconductor die12. In some embodiments, a size of the second semiconductor die13may be substantially the same as, or similar to, a size of the first semiconductor die12. The back side surface122of the first semiconductor die12may be substantially coplanar with the back side surface of the second semiconductor die13. However, in some other embodiments, the size of the second semiconductor die13may be different from the size of the first semiconductor die12, and the back side surface122of the first semiconductor die12may be not substantially coplanar with the back side surface of the second semiconductor die13.

As shown inFIG. 1, the semiconductor package structure1may include at least one first conductive pillar14and at least one second conductive pillar15. Materials of the first conductive pillar14and the second conductive pillar15may include a conductive metal, such as copper (Cu). A size of the first conductive pillar14may be substantially the same as or different from a size of the second conductive pillar15. The first conductive pillar14is disposed adjacent to the active surface121of the first semiconductor die12and electrically connected to the first semiconductor die12. Similarly, the second conductive pillar15is disposed on and electrically connected to the second semiconductor die13. A height H1of the first conductive pillar14may be substantially the same, or different from, a height H2of the second conductive pillar15. As shown inFIG. 1, the height H1of the first conductive pillar14is smaller than the height H2of the second conductive pillar15. The first conductive pillar14has an end surface141. The second conductive pillar15has an end surface151. The end surface141of the first conductive pillar14is substantially coplanar with the end surface151of the second conductive pillar15.

The encapsulant16may be a molding compound. The encapsulant16covers at least a portion of the first semiconductor die12and at least a portion of the first conductive pillar14. As show inFIG. 1, the encapsulant16covers the active surface121, the back side surface122and the lateral surface123of the first semiconductor die12. The encapsulant16defines a groove164adjacent to and surrounding the respective first conductive pillar14. For example, the groove164may be an annular groove.

As shown inFIG. 1, the encapsulant16may also cover the second semiconductor die13and at least a portion of the second conductive pillar15. Besides, the encapsulant16may define another groove166adjacent to and surrounding the respective second conductive pillar15. For example, the groove166may be an annular groove. As shown inFIG. 1, in some embodiments, a maximum depth of the groove164surrounding the first conductive pillar14may be substantially the same as a maximum depth of the groove166surrounding the second conductive pillar15. However, in some other embodiments, the maximum depth of the groove164surrounding the first conductive pillar14may differ from that of the groove166surrounding the second conductive pillar15.

The encapsulant16has a first surface161and a second surface162opposite to the first surface161. The first surface161is adjacent to the active surface121of the first semiconductor die12. The second surface162may be above the first semiconductor die12and the second semiconductor die13.

The first dielectric layer24is disposed on the first surface161of the encapsulant16and in the grooves164,166of the encapsulant16. As shown inFIG. 1, in some embodiments, the first conductive pillar14and the second conductor pillar15do not extend fully through the first dielectric layer24. However, in some other embodiments, the first conductive pillar14and the second conductor pillar15may extend fully through the first dielectric layer24, which is described in following passages referring toFIG. 4. The first dielectric layer24includes a protrusion244surrounding the first conductive pillar14. As shown inFIG. 1, the protrusion244of the first dielectric layer24may be conformal with and filled in the grooves164,166defined by the encapsulant16. The first dielectric layer24defines a plurality of openings246to expose the end surface141of the first conductive pillar14and the end surface151of the second conductive pillar15. A material of the first dielectric layer24may be epoxy or polyimide (PI) including photoinitiators, and the opening246may be formed by, e.g., lithography techniques.

The first circuit structure22may include a redistribution layer (RDL). As shown inFIG. 1, the first circuit structure22is disposed on the first dielectric layer24and in the openings246of the first dielectric layer24. The first circuit structure22is electrically connected to the first conductive pillars14and the second conductive pillars15. For example, the first circuit structure22may include a plurality of vias224disposed in the openings246of the first dielectric layer24and contacting the end surface141of the first conductive pillar14and the end surface151of the second conductive pillar15.

The second dielectric layer28is disposed on the first dielectric layer24and covers at least a portion of the first circuit structure22. The second dielectric layer28defines at least one opening284to expose a portion of the first circuit structure22. A material of the second dielectric layer28may be epoxy or PI including photoinitiators, and the opening284may be formed by, e.g., lithography techniques. The material of the second dielectric layer28may be the same as, or different from, that of the first dielectric layer24.

The second circuit structure26may include a redistribution layer (RDL). As shown inFIG. 1, the second circuit structure26is disposed on the second dielectric layer28and in the opening284of the first dielectric layer28. The second circuit structure26is electrically connected to the first circuit structure22. For example, the second circuit structure26may include at least one via264disposed in the opening284of the second dielectric layer28and contacting the first circuit structure22. A line width/line space (L/S) of the second circuit structure26may be substantially the same as, or different from, a line width/line space (L/S) of the first circuit structure22.

The third dielectric layer29is disposed on the second dielectric layer28and covers at least a portion of the second circuit structure26. The third dielectric layer29defines at least one opening292to expose a portion of the second circuit structure26. A material of the third dielectric layer29may be epoxy or PI including photoinitiators, and the opening292may be formed by, e.g., lithography techniques. The material of the third dielectric layer29may be the same as, or different from, those of the first dielectric layer24and the second dielectric layer28.

The external connector294is disposed in the opening292of the third dielectric layer29and electrically connected to the second circuit structure26. The external connector294may include an under bump metallization (UBM) layer295and a solder ball296. The UBM layer295is disposed in the opening292of the third dielectric layer29and contacts the second circuit structure26. The solder ball296is disposed on the UBM layers295for external connection, and is electrically connected to the second circuit structure26through the UBM layer295.

FIG. 2illustrates an enlarged view of the area A inFIG. 1. As shown inFIG. 2, the first dielectric layer24has a first thickness T1at a first position P1and a second thickness T2at a second position P2. The first position P1is closer to the first conductive pillar14than the second position P2. The first thickness T1is greater than the second thickness T2, such as about 1.1 times or greater, about 1.2 times or greater, about 1.3 times or greater, or about 1.5 times or greater. As shown inFIG. 2, a height h of a portion of the first conductive pillar14protruding from the encapsulant16is smaller than a minimum thickness of the first dielectric layer24(e.g., the second thickness T2of the first dielectric layer24at the second position P2). The encapsulant16may include a plurality of fillers (e.g., filler particles) with an average diameter. In some embodiment, the average diameter refers to an average diameter of filler particles of the encapsulant16. A distance D is defined between the first surface161of the encapsulant16and the active surface121of the first semiconductor die12. In some embodiments, the distance D is greater than, or substantially equal to, about three times the average diameter of the fillers so that the fillers of the encapsulant16can enter a space between the first surface161of the encapsulant16and the active surface121of the first semiconductor die12smoothly. In some embodiments, if the semiconductor package structure1includes a plurality of semiconductor dice, the distance D may be defined as a minimum distance between the first surface161of the encapsulant16and the active surfaces of the semiconductor dice.

The semiconductor package structure1of the present disclosure can be manufactured without the grinding operation to expose the conductive pillars (e.g., the first conductive pillar14and the second conductive pillar15). Accordingly, manufacturing cost of the grinding operation can be eliminated. Even though semiconductor package structure1includes plural semiconductor dice (e.g., the first semiconductor die12and the second semiconductor die13) which may include conductive pillars (e.g., the first conductive pillar14and the second conductive pillar15) having different heights, end surfaces141,151of the conductive pillars14,15are substantially coplanar with each other. Hence, the conductive pillars14,15can be properly connected to the first circuit structure22.

FIG. 3illustrates a cross-sectional view of a semiconductor package structure1aaccording to some embodiments of the present disclosure. The semiconductor package structure1ais similar to the semiconductor package structure1shown inFIGS. 1 and 2, except that the end surface141of the first conductive pillar14defines a recess portion148. Accordingly, the first circuit structure22extends into the recess portion148defined by the end surface141of the first conductive pillar14. For example, the via224of the first circuit structure22extends into the recess portion148defined by the end surface141of the first conductive pillar14.

FIG. 4illustrates a cross-sectional view of a semiconductor package structure1baccording to some embodiments of the present disclosure.FIG. 5illustrates an enlarged view of an area B inFIG. 4. The semiconductor package structure1bis similar to the semiconductor package structure1shown inFIGS. 1 and 2, except that the first conductive pillar14and the second conductive pillar15extend fully through the first dielectric layer24, and the via224of the first circuit structure22(as shown inFIG. 1) may be omitted. As shown inFIG. 4, the first conductive pillar14protrudes from the first dielectric layer24, and the end surface141of the first conductive pillar14is embedded in the first circuit structure22. Accordingly, referring toFIG. 5, the height h of the portion of the first conductive pillar14protruding from the encapsulant16may be greater than the minimum thickness of the first dielectric layer24(e.g., the second thickness T2of the first dielectric layer24at the second position P2).

FIG. 6illustrates a cross-sectional view of a semiconductor package structure1caccording to some embodiments of the present disclosure. The semiconductor package structure1cis similar to the semiconductor package structure1shown inFIGS. 1 and 2, except that a roughness (Ra) of the first surface161of the encapsulant16is greater than about 0.008 micrometers (μm), such as about 0.01 μm or greater, or about 0.02 μm or greater. The roughness of the first surface161provides for an improved adhesion between the encapsulant16and the first dielectric layer24.

FIG. 7toFIG. 16illustrate various stages of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a semiconductor package structure such as the semiconductor package structure1shown inFIGS. 1 and 2. In the initial stages of some embodiments, a carrier60, a sacrificial component62and a dielectric material64are provided as follows.

Referring toFIG. 7, the carrier60is provided. The carrier60may include, for example, a metal or a glass material, or may be another substrate. The carrier60may optionally include a layer or film of material disposed thereon, such as a thermal release material.

Referring toFIG. 8, a sacrificial component62is formed or disposed on the carrier60. The sacrificial component62may be a metal pad, and may be formed by, e.g., lithography techniques. For example, the sacrificial component62may be formed by applying a seed layer over the carrier60, plating a metal layer over the seed layer, disposing a mask over the metal layer, and etching portions of the metal layer exposed by the mask. One or both of the seed layer and the metal layer may include copper or another metal or metal alloy. As disclosed in the subsequent stages, the sacrificial component62helps to define a surface of an encapsulant (such as the encapsulant16shown inFIG. 1) and a height of a portion of a conductive pillar protruding from the encapsulant (such as the height h of the portion of the first conductive pillar14shown inFIG. 2).

The sacrificial component62may be made of a plastic material, such as polypropylene (PP) or polystyrene (PS). As illustrated inFIG. 8, in some embodiments, the sacrificial component62may bond tightly to carrier60. However, in some other embodiments, the bonding strength between the sacrificial component62and the carrier60may be weak. As shown inFIG. 8, a plurality of sacrificial components62is formed or disposed on the carrier60, and top surfaces of the sacrificial components62may be substantially coplanar. In some other embodiment, the sacrificial components62may be formed integrally with the carrier60. That is, there are no boundaries between the sacrificial components62and the carrier60. The carrier60with the sacrificial components62may be formed by etching an initial carrier that is thicker than the carrier60as illustrated inFIG. 8. In some embodiments, the sacrificial components62may include, for example, a metal or a glass material, or another substrate material. The sacrificial components62may optionally include, e.g., a thermal release material.

Referring toFIG. 9, a dielectric material64is provided on the carrier60and covers the carrier60and the sacrificial components62. The dielectric material64includes an exposed surface641away from the carrier60. The dielectric material64may be an adhesive material, such as an adhesive film or a glue (e.g., A4012 produced by Tokyo Ohka Kogyo Co., Ltd. (TOK)). The dielectric material64may be a dry film or may be applied in a liquid form. After being applied on the carrier60, the dielectric material64may be pre-cured or partially cured (e.g., about 180° C., about 10 minutes) to be in a B-stage.

Referring toFIG. 10, a first semiconductor die12is attached to the carrier60. The first semiconductor die12includes an active surface121, a back side surface122opposite to the active surface121, and a lateral surface123extending between the active surface121and the back side surface122. The first semiconductor die12includes at least one first conductive pillar14disposed adjacent to the active surface121. The first conductive pillar14includes an end surface141. When attaching the first semiconductor die12to the carrier60, the first conductive pillar14penetrates through the dielectric material64to contact the sacrificial component62.

The vertical position of the first semiconductor die12relative to the carrier60may be determined by the dielectric material64and the sacrificial component62. The sacrificial component62positions the first conductive pillar14in a manner that the first conductive pillar14will be exposed from a surface of an encapsulant (e.g., the first surface161of the encapsulant16, as shown inFIG. 11) at a subsequent stage, thus the grinding operation for exposing the first conductive pillar14can be omitted.

The end face141of the first conductive pillar14physically contacts a respective sacrificial component62. However, in some other embodiments, multiple conductive pillars (e.g., multiple first conductive pillars14, or the first conductive pillar14and the second conductive pillar15) can be disposed on and contact a sacrificial component62.

Due to capillary phenomenon, a portion of the dielectric material64may flow along the first conductive pillar14towards the first semiconductor die12, forming a protrusion644adjacent to the first conductive pillar14as shown inFIG. 10. That is, the dielectric material64, which may be in the B-stage, includes the protrusion644surrounding the first conductive pillar14.

Similarly, a second semiconductor die13may be attached to the carrier60. The second semiconductor die13includes at least one second conductive pillar15. A height H2of the second conductive pillar15may differ from a height H1of the first conductive pillar14. The second conductive pillar15penetrates through the dielectric material64, and an end surface151of the second conductive pillar15physically contacts another one of the sacrificial components62. Since the top surfaces of the sacrificial components62are substantially coplanar, the end surface151of the second conductive pillar15is thus substantially coplanar with the end surface141of the first conductive pillar14. After attaching the first semiconductor12(and the second semiconductor13, if applicable) to the carrier60, the dielectric material64may be fully cured (e.g., 220° C., 30 min) to be in a C-stage.

Referring toFIG. 11, an encapsulant16is formed on the dielectric material64and covers the first semiconductor die12, the second semiconductor13, the first conductive pillar14and the second conductive pillar15. The encapsulant16may cover the active surface121, the back side surface122and the lateral surface123of the semiconductor die12. The encapsulant16has a first surface161and a second surface162opposite to the first surface161. The first surface161is disposed on the exposed surface641of dielectric material64. The second surface162may be above the first semiconductor die12and the second semiconductor die13. In other words, the first semiconductor die12and the second semiconductor die13may be embedded in the encapsulant16. The first surface161of the encapsulant16may be conformal with the exposed surface641of the dielectric material64. Accordingly, a groove164is defined between the encapsulant16and the first conductive pillar14. The groove164is adjacent to and surrounds the first conductive pillar14, and is filled by the protrusion644of the dielectric material64. Similarly, another groove166is defined between the encapsulant16and the second conductive pillar15disposed on the second semiconductor die13.

The encapsulant16may include a plurality of fillers with an average diameter. A distance D is defined between the first surface161of the encapsulant16and the active surface121of the first semiconductor die12. The distance D is greater than, or substantially equal to, about three times the average diameter of the fillers, such that the fillers in the encapsulant16can flow smoothly into a space between the active surface121of the semiconductor die12and the exposed surface641of the dielectric material64. If a plurality of semiconductor dice are included in the semiconductor package structure, the distance D may be defined as a minimum distance between the first surface161of the encapsulant16and the active surfaces of the semiconductor dice.

Referring toFIG. 12, the carrier60is removed by, for example, stripping. Since the sacrificial component62bonds tightly to the carrier60, in some embodiments, the sacrificial component62may also be removed along with the carrier60. Alternatively, in some other embodiments, the sacrificial component62may be removed by, e.g., etching. As shown inFIG. 12, with the carrier60and the sacrificial component62removed, the end surface141of the first conductive pillar14and the end surface151of the second conductive pillar15are exposed.

Referring toFIG. 13, the dielectric material64is removed by, for example, washing or chemical etching, to expose the first conductive pillar14and the second conductive pillar15. Accordingly, a portion of the first conductive pillar14and a portion of the second conductive pillar15protrude from the first surface161of the encapsulant16. It is noteworthy that by adjusting a thickness of the sacrificial component62, a height h of the portion of the first conductive pillar14that protrudes from the encapsulant16can be precisely controlled. In some embodiments, a promoter layer may be further disposed on the first surface161of the encapsulant16for enhancing adhesion between the first surface161and a layer (e.g., a first dielectric layer24) formed or disposed thereon.

Referring toFIG. 14, a first dielectric layer24is formed or disposed on the encapsulant16. The first dielectric layer24is disposed on the first surface161of the encapsulant16and in the grooves164,166of the encapsulant16. As shown inFIG. 14, the first conductive pillar14and the second conductive pillar15do not extend fully through the first dielectric layer24. The first dielectric layer24includes a plurality of protrusions244surrounding the first conductive pillar14and the second conductive pillar15and filled in the grooves164,166defined by the encapsulant16. The first dielectric layer24defines a plurality of openings246to expose the end surface141of the first conductive pillar14and the end surface151of the second conductive pillar15. A material of the first dielectric layer24may be epoxy or PI including photoinitiators, and the openings246may be formed by, e.g., lithography techniques.

As shown inFIG. 14, the first dielectric layer24has a first thickness T1(as illustrated inFIG. 2) at a first position P1and a second thickness T2(as illustratedFIG. 2) at a second position P2. The first position P1is closer to the first conductive pillar14than the second position P2. The first thickness T1is greater than the second thickness T2.

Referring toFIG. 15, a first circuit structure22is formed on the first dielectric layer24and electrically connected to the first conductive pillar14and the second conductive pillar15. The first circuit structure22may include a redistribution layer. The first circuit structure22may include a plurality of vias224disposed in the openings246of the first dielectric layer24and contacting the end surface141of the first conductive pillar14and the end surface151of the second conductive pillar15.

Referring toFIG. 16, a second dielectric layer28, a second circuit structure2and a third dielectric layer29are formed or disposed on the first dielectric layer24. Then, at least one external connector294(e.g., including a UBM layer295and a solder ball296) is formed or disposed in the opening292of the third dielectric layer29and electrically connected to the second circuit structure26. Therefore, the semiconductor package structure1as shown inFIGS. 1 and 2is manufactured.

According to the manufacturing method of the present disclosure, such as that described above, a grinding operation can be omitted, thus eliminating a manufacturing cost of the grinding operation. Besides, such manufacturing method insures that the end surface(s) of the conductive pillar(s) (e.g., the end surface141of the first conductive pillar14and the end surface151of the second conductive pillar15) can be exposed. In the case that the semiconductor package structure includes multiple semiconductor dice (e.g., the first semiconductor die12and the second semiconductor13) having conductive pillars (e.g., the first conductive pillar14and the second conductive pillar15) having different heights, end surfaces (e.g., the end surface141and the end surface151) of the conductive pillars are substantially coplanar.

In some other embodiments, in the stage shown inFIG. 9, after pre-curing of the dielectric material64, the method may further include pre-treating the exposed surface641of the dielectric material64by, for example, plasma etching wet etching or bombardment, so as to provide a roughness of the exposed surface641greater than about 0.008 such as about 0.01 or greater, or about 0.02 μm or greater. Hence, a roughness of the first surface161of the encapsulant16formed on the exposed surface641of the dielectric material64may be greater than about 0.008 such as about 0.01 μm or greater, or about 0.02 μm or greater. Accordingly, the semiconductor package structure1cas shown inFIG. 6can be manufactured.

FIG. 17toFIG. 22illustrate a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a semiconductor package structure such as the semiconductor package structure1ashown inFIG. 3. The initial stages of the illustrated method may be the same as the stages illustrated inFIG. 7toFIG. 11. However, in the method illustrated inFIG. 17toFIG. 22, the bonding strength between the sacrificial component62and the carrier60may be weaker than the bonding strength between the sacrificial component62and the carrier60in the method illustrated inFIG. 12toFIG. 16.FIG. 17depicts a stage subsequent to that depicted inFIG. 11.

Referring toFIG. 17, the carrier60is removed by, for example, stripping. Since bonding strength between the sacrificial component62and the carrier60is relatively weak, the sacrificial component62may remain embedded in the dielectric material64.

Referring toFIG. 18, the sacrificial component62is removed. Since the sacrificial component62may be a metal pad, removing the sacrificial component62may include removing the metal pad by etching and forming a recess portion148on the end surface141of the first conductive pillar14. That is, a portion of the first conductive pillar14may also be removed during the etching process, thus forming the recess portion148on the end surface141of the first conductive pillar14.

Referring toFIG. 19, the dielectric material64is removed by, for example, washing or chemical etching, to expose the first conductive pillar14and the second conductive pillar15. Accordingly, a portion of the first conductive pillar14and a portion of the second conductive pillar15protrude from the encapsulant16.

Referring toFIG. 20, a first dielectric layer24is formed or disposed on the encapsulant16. The first dielectric layer24is disposed on the first surface161of the encapsulant16and in the grooves164,166of the encapsulant16. As shown inFIG. 20, the first conductive pillar14and the second conductive pillar15do not extend fully through the first dielectric layer24. The first dielectric layer24includes a plurality of protrusions244surrounding the first conductive pillar14and the second conductive pillar15and filled in the grooves164,166defined by the encapsulant16. The first dielectric layer24defines a plurality of opening246to expose at least a portion of the end surface141of the conductive pillar14and at least a portion of the end surface151of the second conductive pillar15.

Referring toFIG. 21, the first circuit structure22is formed on the first dielectric layer24and electrically connected to the first conductive pillar14and the second conductive pillar15. The first circuit structure22further extends into the recess portion148defined by the end surface141of the first conductive pillar14. The first circuit structure22may include a plurality of vias224disposed in the openings246of the first dielectric layer24and extending into the recess portion148to contact the end surface141of the first conductive pillar14.

Referring toFIG. 22, a second dielectric layer28, a second circuit structure2, a third dielectric layer29and at least one external connector294(e.g., including an UBM layer295and a solder ball296) are formed or disposed on the first dielectric layer24. Thus, the semiconductor package structure1aas shown inFIG. 3is manufactured.

FIG. 23toFIG. 25illustrate a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a semiconductor package structure such as the semiconductor package structure1bshown inFIGS. 4 and 5. The initial stages of the illustrated method may be the same as the stages illustrated inFIG. 7toFIG. 13.FIG. 23depicts a stage subsequent to that depicted inFIG. 13.

Referring toFIG. 23, a first dielectric layer24is formed or disposed on the encapsulant16. The first dielectric layer24is disposed on the first surface161of the encapsulant16and in the grooves164,166of the encapsulant16. The first dielectric layer24includes a protrusion244surrounding the first conductive pillar14and the second conductive pillar15and filled in the grooves164,166defined by the encapsulant16. As shown inFIG. 23, the first conductive pillar14and the second conductive pillar15extend fully through the first dielectric layer24. That is, the first conductive pillar14includes a portion protruding from the first dielectric layer24. Similarly, the second conductive pillar15also includes a portion protruding from the first dielectric layer24.

Referring toFIG. 24, a first circuit structure22is formed on the first dielectric layer24and electrically connected to the first conductive pillar14and the second conductive pillar15. The portion of the first conductive pillar14protruding from the first dielectric layer24is thus embedded in the first circuit structure22. Similarly, the portion of the second conductive pillar15protruding from the first dielectric layer24is also embedded in the first circuit structure22.

Referring toFIG. 25, a second dielectric layer28, a second circuit structure2, a third dielectric layer29and at least one external connector294(e.g., including an UBM layer295and a solder ball296) are formed or disposed on the first dielectric layer24. Thus, the semiconductor package structure1bas shown inFIGS. 4 and 5is manufactured.