Micro-pillar assisted semiconductor bonding

Micro pillars are formed in silicon. The micro pillars are used in boding the silicon to hetero-material such as III-V material, ceramics, or metals. In bonding the silicon to the hetero-material, indium is used as a bonding material and attached to the hetero-material. The bonding material is heated and the silicon and the hetero-material are pressed together. As the silicon and the hetero-material are pressed together, the micro pillars puncture the bonding material. In some embodiments, pedestals are used in the silicon as hard stops to align the hetero-material with the silicon.

BACKGROUND

Silicon integrated circuits have dominated the development of electronics and many technologies based upon silicon processing have been developed over the years. Their continued refinement led to nano-scale feature sizes that can be important for making metal oxide semiconductor CMOS circuits. On the other hand, silicon is not a direct-bandgap material. Although direct-bandgap materials, including III-V compound semiconductor materials, have been developed, there is a need in the art for improved methods and systems related to photonic integrated circuits utilizing silicon substrates.

This application relates to bonding a first semiconductor to a second semiconductor. More specifically, and without limitation, to bonding a III-V semiconductor to a silicon semiconductor.

BRIEF SUMMARY OF THE INVENTION

Embodiments generally relate to bonding a first semiconductor to a second semiconductor, wherein the first semiconductor, and/or the second semiconductor, have micro pillars to assist in bonding. An example of bonding a first semiconductor to a second semiconductor is disclosed in commonly owned U.S. patent application Ser. No. 14/262,529, filed on Apr. 25, 2014, which is incorporated by reference in its entirety for all purposes.

This application discloses devices and methods used for bonding a first semiconductor to a second semiconductor. Though not limiting, in some embodiments micro pillars on a silicon substrate are used to penetrate a bonding material (e.g., indium) when attaching a hetero-material (e.g., III-V; from the periodic table of the elements, group III elements include: B, Al, Ga, In, Tl, and group V elements include: N, P, As, Sb, and Bi) device to a silicon semiconductor structure. Bonding a planar silicon surface to a planar III-V material using indium has some challenges. For example, in some embodiments, a bond between silicon and the hetero-material device is used as an electrical contact (e.g., ohmic contact). Yet indium oxide can form on indium before or during bonding, thus reducing functionality of the electrical contact. In some embodiments, pillars help break indium oxide and penetrate into the indium during bonding. Second, in some embodiments, heat is applied to the III-V material to heat the indium to a desired temperature (e.g., near, at, or above a melting point of the bonding material). If the silicon is planar, the silicon acts as a heat sink, making heating of the indium more difficult. In some embodiments, pillars are used to reduce an initial surface-contact area between the silicon and the indium so that not as much heat is transferred to the silicon during bonding (e.g., making it easier to melt the indium). Though silicon, indium, and III-V material are used as examples of bonding, similar processes and device structures can be applied to other bonding techniques.

DETAILED DESCRIPTION

The ensuing description provides preferred exemplary embodiment(s), and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the preferred exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing a preferred exemplary embodiment. It is understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope as set forth in the appended claims.

Referring toFIG. 1, a side view of an embodiment of a first semiconductor100comprising a substrate104and a plurality of pillars108is shown. The pillars108extend from the substrate104in a direction normal to a top surface112of the substrate104. In some embodiments, the substrate104and/or the pillars108are made of silicon (e.g., crystalline silicon). The pillars108can be formed using lithography (e.g., etched from a same wafer, such as a silicon-on-insulator (SOI) wafer, as the substrate104). In this embodiment, the pillars108are rectangular and arranged in an array. But other shapes and patterns may be used. Each of the plurality of pillars108have a thickness, t. But in some embodiments, pillars108have varying thicknesses. The pillars108, in some embodiments, are coated with one or more layers of a dielectric and/or metal (e.g., for under-bump metallization). InFIG. 1, only a portion of the substrate104is shown. In some embodiments, other components (e.g., waveguides, couplers, gratings, and/or thermal diodes) are layered above and/or in the substrate104. In this embodiment, the top surface112of the substrate104forms a bottom of a recess, or pit, for insertion of a second semiconductor (e.g., a chip comprising a gain medium) comprising material that is not in the first semiconductor. For example, the substrate104is made of silicon and the second semiconductor is a chip made of ceramics, metals, or composite hetero-material such as III-V material (e.g., InP or GaAs).

Each pillar108comprises a proximal end116, a distal end120, and one or more sides124between the proximal end116and the distal end120. The distal end120is opposite the proximal end116. The proximal end116is closer to the substrate104than the distal end120. The thickness t is measured from the proximal end116to the distal end120.

Referring toFIG. 2, a top view of an embodiment of the first semiconductor100is shown. In this embodiment, the pillars108are formed in an array. In some embodiments, the pillars108are arranged in a different pattern and/or randomized. The pillars108, in aggregate, have a fill ratio between 5% and 95% of at least a portion of the top surface112of the substrate104. In some embodiments, having a fill ratio between 15% and 40% (e.g., 15, 20, 25, 30, 33, 35, or 40%) provides good penetration of bonding material by the pillars108. The top view of the embodiment of the first semiconductor100shows cross sections of the pillars108. The pillars108are rectangular, have a width, a (measured along an x axis), and a length, b (measured along a y axis). Centers of adjacent pillars108are separated by a first distance, m (measured along an x axis) and a second distance, n (measured along a y axis). In this embodiment, a=b and m=n. Thus with m=2*a, there is a fill ratio of 25%; m=sqrt(2)*a there is a 50% fill ratio; and m=(2/sqrt(3))*a, there is a fill ratio of 75%.

The pillars108have four sides124since the pillars108are rectangular. Other cross-sectional shapes can be used. For example, a pillar108that is tubular (e.g., circular cross section), may have only one side124. Whereas a pillar108that is triangular has three sides124.

The width a of pillars108and the length b of pillars108can vary (e.g., a=0.2, 0.5, 0.75, 1, 2, 3, 4, 5, 10, 20, or 30 μm). In some embodiments, width a and/or length b are less than thickness t (e.g., a<½t, ⅓t, or ¼t).

Referring toFIGS. 3A-3D, examples of different shapes of pillars108(sometimes referred to as micro pillars) are shown. In some embodiments, pillars108help break and/or penetrate through an oxide (e.g., indium oxide) of a bonding material. InFIG. 3A, a rectangular pillar300is shown. In some embodiments, a rectangular cross section is used for more uniform etching. The rectangular pillar300has a thickness t, a width a, and a length b. InFIG. 3B, a pointed pillar304is shown. the pointed pillar304has a rectangular cross section at the proximal end116, and a point at the distal end120. In some embodiments, the point at the distal end120is formed by wet etching along one or more crystal axes of the first semiconductor100. Besides improving penetration of the oxide for bonding, the point at the distal end120can also reduce heat transfer from bonding material to the substrate104as the bonding material is heated during bonding.

InFIGS. 3C and 3D, pillars108having a first portion316and a second320are shown. The first portion316comprises the proximal end116. The second portion320comprises the distal end120. The first portion316has the width a and the length b. The second portion320has a width c and a length d. Cross sections are planes of the pillar108that are parallel to the top surface112of the substrate104.

InFIG. 3C, a t-shaped pillar324is shown. For the t-shaped pillar324, the first portion316has a first cross section330-1that is smaller than a second cross section330-2of the second portion320. Put another way, a<c, b<d, and/or (a×b)<(c×d). In some embodiments, a t-shaped pillar324is used to act as a hook to trap bonding material between the second portion320and the substrate104(e.g., for improving adhesion). In some embodiments, the second portion320tapers to the first portion316. In some embodiments, the t-shaped pillar324is formed by a dry etch to make an undercut328between the second portion320and the first portion316.

InFIG. 3D, a fin pillar334is shown. For the fin pillar334, the first portion316has a first cross section340-1that is larger than a second cross section340-2of the second portion320. Put another way, a>c, b>d, and/or (a×b)>(c×d). In some embodiments, the second portion320of the fin pillar334is used to more easily penetrate the bonding material (e.g., an oxide formed on the bonding material) because the second portion320of the fin pillar334has a smaller cross section than the first portion316of the fin pillar334; and the first portion316of the fin pillar334provides more surface area for bonding. In some embodiments, the first portion316of the fin pillar334is contiguous with the first portion316of another (second) fin pillar334(e.g., a=m and b<n; and/or b is equal to or less than a/2). In some embodiments, having the first portion316of the fin pillar334contiguous with the first portion316of another fin pillar334is used to channel bonding material.

In some embodiments, shapes and density of pillars108are optimized to modulate heat transfer. Bonding material is placed on the second semiconductor. Heat is applied to the bonding material by applying heat to the second semiconductor. The second semiconductor is pressed against the first semiconductor100while applying heat to the second semiconductor. Heat is used to melt the bonding material. The first semiconductor100acts as a heat sink, drawing heat away from the bonding material. Heat transfer is modulated by adjusting the fill ratio of an aggregate of cross-sectional areas of pillars108to an exposed area of the substrate104(i.e., parts of the top surface112not covered by pillars108. The smaller the fill ratio (up to a limit of mechanical breakdown of the pillars), the lower the heat transfer to the first semiconductor, and the easier it is to melt the bonding material (e.g., indium) while heat is applied to the second semiconductor. But a smaller fill ratio reduces contact area that the first semiconductor100has with the bonding material.

In some embodiments, shapes and density of pillars108are optimized for pressure transfer to break an outer layer (e.g., oxide) formed on the bonding material. Optimization for pressure transfer is done by also changing the fill ratio and shape of the pillars108. The smaller the fill ratio (up to the limit of mechanical breakdown of the pillars), the higher the pressure is applied to the outer layer by the pillars108, and the easier it becomes to break the outer layer of the bonding material. Additionally, the distal end120of pillars108can be made small (e.g., pointy and/or small cross section) to improve the ability of the pillars108to break the outer layer of the bonding material. Maximum widths (e.g., a, or c if the second portion320is used) and/or lengths (e.g., b or d if the second portion320is used) of pillars108for puncturing the bonding material can depend on one or more factors including alloy used as bonding material (e.g., density and/or viscosity), proximal end120shape (e.g., whether or not there is a point) bond temperature, bond pressure, and fill ratio. Thus, in some embodiments, a maximum pillar width and/or length for puncturing (e.g., a and/or b, or c and/or d if the second portion320is used) is equal to and/or less than 30, 25, 20, and/or 15 μm.

Elements of the rectangular pillar300, the pointed pillar304, the t-shaped pillar324, and/or the fin pillar334, can be combined with each other to form new pillar designs. For example, the second portion320of the t-shaped pillar324or the fin pillar334can be made with a point similar to the pointed pillar304to provide better penetration of the bonding material.

Referring next toFIG. 4, a side view of an embodiment of the first semiconductor100and a second semiconductor404before bonding is shown. InFIG. 4, the second semiconductor404(e.g., a chip made of III-V material) has a bonding material408(e.g., indium) attached to a bottom surface412of the second semiconductor404. The first semiconductor100comprises the substrate104and the plurality of pillars108. The second semiconductor404and the first semiconductor100are to be pressed together (e.g., by pushing the second semiconductor404toward the first semiconductor100).

As the second semiconductor404is pressed toward the first semiconductor100, local force on the bonding material408is increased due to reduced contact area of the pillars108. Further, local heat transfer between the bonding material408and the first semiconductor100is reduced due to a reduced contact area of the pillars108, thus making it easier to melt the bonding material408. In some embodiments, both force and heat are applied to the second semiconductor404. In some embodiments, an oxide forms an outer layer of the bonding material408(forming a crust on the bonding material408). Pillars108help break the crust of the bonding material408to facilitate bonding and/or extend past the outer layer for increasing connectivity of the first semiconductor100to the second semiconductor404.

Referring toFIG. 5, a side view of an embodiment of the first semiconductor100and the second semiconductor404after bonding is shown. The pillars108penetrated the bonding material408such that the bonding material408surrounds each of the plurality of pillars108by contacting the one or more sides124of each pillar108of the plurality of pillars108. The bonding material408fastens the first semiconductor100to the second semiconductor404. In some embodiments, the pillars108are used as a stop for pressing the second semiconductor404to the first semiconductor (e.g., to align the second semiconductor404to the first semiconductor100). In some embodiments, the pillars108don't stop the second semiconductor such that bonding material408contacts (e.g., covers) the distal end120, as well as sides124, of pillars108. In some embodiments, one or more coatings are applied to pillars108before bonding; and the one or more coatings become part of the pillars108. In some embodiments, a number of pillars108is equal to or greater than 10 to puncture the bonding material408and/or provide more surface area for bonding and/or contact.

Referring toFIG. 6, a side view of an embodiment of a first semiconductor600comprising a substrate104, pillars108, and pedestals604is shown. The pedestals604extend from the top surface112of the substrate104to a height H (e.g., 0.1 μm≤H≤50 μm; H=0.1, 1, 4, 10, 20, 30, 40, or 50 μm). In some embodiments, the pedestals604are made by etching. In some embodiments, pedestals are made by etching and have a height H less than or equal to 1.3, 1.0, and/or 0.6 μm to reduce an amount of etching needed while providing alignment (e.g., height registration) between the first semiconductor600and the second semiconductor404. In some embodiments, the pedestals604are made by growing material on the substrate104. In some embodiments, pedestal604widths and lengths are set so that an aggregate area of the pedestals604can mechanically support and act as a stop positioning/blocking surface for the second semiconductor while pressure is applied to the second semiconductor404. For example, in some embodiments a width of a pedestal is greater than or equal to 20, 25, and/or 30 μm to provide mechanical support. In some embodiments, the thickness t of pillars108is less than the height H of the pedestals604. In some embodiments, the pedestals604are used similarly to pedestals in the '529 application.FIG. 6shows the first semiconductor600having a first pedestal604-1, a second pedestal604-2, and a third pedestal604-3. Pillars108are between the first pedestals604-1and the second pedestal604-2. Pillars108are between the second pedestals604-2and the third pedestal604-3. In some embodiments, pedestals604have a width that is greater than twice the width a and or length b of pillars108so that the pedestals604provide structural support for the second semiconductor404and the pillars108puncture the bonding material408and/or increase surface area for the bonding material408to bond the second semiconductor404to the first semiconductor600.

Referring toFIG. 7, a side view of an embodiment of the first semiconductor600and the second semiconductor404before bonding is shown. Bonding material408(e.g., indium) is attached to the bottom surface412of the second semiconductor404. The bonding material408is positioned on the bottom surface412of the second semiconductor404to avoid bonding material408getting on top of pedestals604.

The second semiconductor404and the first semiconductor600are to be pressed together (e.g., by pushing the second semiconductor404toward the first semiconductor600). As the second semiconductor404is pressed toward the first semiconductor600, local force on the bonding material408is increased due to reduced contact area of the pillars108. Further, local heat transfer between the bonding material408and the first semiconductor600is reduced due to a reduced contact area of the pillars108, thus making it easier to melt the bonding material408. In some embodiments, both force and heat are applied to the second semiconductor404during bonding.

Referring toFIGS. 8A, 8B, and 8C, side views of embodiments of a first semiconductor600, which has pillars108and pedestals604, bonded to a second semiconductor404(e.g., a chip made of III-V material) are shown. Precise height-positioning of the second semiconductor404is achieved by resting the second semiconductor404on pedestals604(the pedestals604being used as a hard stop). The pillars108penetrate the bonding material408such that the bonding material408surrounds each of the plurality of pillars108, contacting the one or more sides124of each pillar108of the plurality of pillars108. The bonding material408fastens the first semiconductor600to the second semiconductor404. Bonding material408is pushed to edges of the second semiconductor404. Local heat transfer increases after the second semiconductor404and the first semiconductor600are pressed together and the bonding material408fills between the substrate104and the second semiconductor404, which helps in cooling the bonding material408. In some embodiments, trenches (e.g., fin pillars334and/or features similar to fin pillars334, such as the first portion316of the fin pillars334) are used to channel the bonding material408toward edges of the second semiconductor404. InFIG. 8A, the second semiconductor404rests directly on tops of pedestals604.

In some embodiments, layer material804, for example as depicted inFIGS. 8B and 8C, is positioned between the top surfaces of the pedestals604and the second semiconductor404. For example, the layer material804is deposited on the first semiconductor600or the second semiconductor404before bonding. The layer material804is a rigid material, or a material with some amount of compliance. In some embodiments, the layer material804is used to reduce the risk of fracturing the first semiconductor100and/or the second semiconductor404while bonding. InFIG. 8B, layer material804is applied to the first semiconductor600before bonding. InFIG. 8C, the layer material804is applied to the second semiconductor404before bonding. InFIG. 8C, the layer material804is applied to the second semiconductor404and the bonding material408is applied to the layer material804.

InFIG. 8D, a side view of an embodiment of a first semiconductor850having a pit is shown. The pit is formed by etching the first semiconductor850. The pit is defined by walls854and the top surface112of the substrate104. A first pedestal604-1and a second pedestal604-2are formed in the pit. Pillars108are formed in the pit between the first pedestal604-1and the second pedestal604-2. A first waveguide858-1extends to a first wall854-1of the pit. A second waveguide858-2extends to a second wall854-2of the pit. The second semiconductor404comprises a feature862(e.g., a quantum well region and/or a waveguide). The pedestals604help position the second semiconductor404(e.g., height registration similar to alignment discussed in the '529 application,FIG. 1B) in relation to the first semiconductor850such that the feature862of the second semiconductor404is aligned to the first waveguide858-1and/or the second waveguide858-2. In some embodiments, the feature862of the second semiconductor404is aligned to other features of the first semiconductor850instead of waveguides858. In some embodiments, an insulating layer (e.g., SiO2) is between the waveguides858and the substrate104(e.g., the substrate104, pedestals604, and/or pillars108being formed in a handle portion of an SOI wafer and the waveguides858being formed in a device layer of the SOI wafer).

In some embodiments, bonding is enhanced by using pillars108in the pit. For example, heat transfer from the bonding material408(e.g., indium), which is attached to the second semiconductor404, to the first semiconductor850(e.g., made of silicon) is initially reduced because a contact area between the bonding material408and the first semiconductor850(or the first semiconductor100, or the first semiconductor600) is reduced until the bonding material408is heated to a threshold temperature that the bonding material408begins to melt. The fill ratio area can be varied from 5% to 95% with the control of the density and shape of the pillars108. In some embodiments, fill ratio is measured using an area for bonding material (e.g., an area between pedestals624filled with pillars108). Reducing the contact area between the bonding material408and the first semiconductor850helps melt the bonding material408because less heat is transferred from the bonding material408to the first semiconductor850. In a further example, once the bonding material408melts and the oxide surface is broken and/or penetrated by the pillars108, space between the pillars108is filled with bonding material408to the bottom of the pit. Heights and/or shapes of the pillars108increases the bond area going from 2D bonding (e.g., bonding to a flat surface of a substrate) to 3D bonding; sides124of the pillars108provide an increased bond surface area.

Referring next toFIG. 9, a flowchart of an embodiment of a bonding process900for bonding a first semiconductor to a second semiconductor is shown. The bonding process900begins in step904where a first semiconductor (e.g., the first semiconductor100, the first semiconductor600, or the first semiconductor850). comprising pillars is provided. In some embodiments, a silicon wafer is provided and etched to form pillars. In some embodiments, the first semiconductor further comprises pedestals used as hard stops for aligning the first semiconductor with the second semiconductor. In some embodiments, the first semiconductor comprises a pit (or recess) and the pillars (e.g., pillars108) and/or pedestals (e.g., pedestals604) are in the pit.

In step908, a second semiconductor is provided (e.g., second semiconductor404). A bonding material (e.g., bonding material408, such as indium) is applied to the second semiconductor, step912. In some embodiments, the bonding material is applied so that the bonding material does not contact top surfaces of the pedestals but does contact distal ends of the pillars. In step916, heat is applied, using a heating source, to the second semiconductor so that a temperature of the bonding material is increased.

In step920, the first semiconductor and the second semiconductor are pressed together so that the pillars puncture the bonding material. In some embodiments, the pillars are engulfed within the bonding material as the first semiconductor and the second semiconductor are pressed together, so that surfaces of pillars are surrounded by the bonding material. In some embodiments, the pillars are coated with a second material (e.g., a conducting material used for under-bump metallization) before the first semiconductor and the second semiconductor are pressed together. In some embodiments, the heating source is removed from being applied to the second semiconductor before the first semiconductor and the second semiconductor are pressed together.

In step924, the bonding material is allowed to cool. In some embodiments, the bonding material contacts more surface area of the first semiconductor as compared to before the pillars punctuate the bonding material, thus increasing heat transfer from the bonding material to the first semiconductor, and the bonding material cools faster.

The above description of exemplary embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. For example, similar methods could be used to bond electronic devices and/or metal to the first semiconductor. The embodiments were chosen and described in order to explain the principles of the invention and its practical applications to thereby enable others skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated.

Further, in some embodiments, the second semiconductor comprises an active region for a detector or a modulator. For example, a mach-zehnder interferometer structure could be made in the first semiconductor (e.g., of silicon) and one or more second semiconductors (e.g., made of III-V material) could be used to modulate a phase change in the interferometer. In some embodiments, the first semiconductor comprises at least one of a CMOS device, a BiCMOS device, an NMOS device, a PMOS device, a detector, a CCD, diode, heating element, or a passive optical device (e.g., a waveguide, an optical grating, an optical splitter, an optical combiner, a wavelength multiplexer, a wavelength demultiplexer, an optical polarization rotator, an optical tap, a coupler for coupling a smaller waveguide to a larger waveguide, a coupler for coupling a rectangular silicon waveguide to an optical fiber waveguide, and a multimode interferometer).

All patents, patent applications, publications, and descriptions mentioned here are incorporated by reference in their entirety for all purposes. None is admitted to be prior art.