Methods and apparatus to improve power factor at light-load

Methods and apparatus to improve power factor are disclosed. An example method includes detecting power provided to a power factor corrector; detecting power provided by the power factor corrector; and disabling the power factor corrector from correcting a power factor of a load for at least one period when the power provided by the power factor corrector is below a light-load threshold.

FIELD OF THE DISCLOSURE

This disclosure relates generally to power factor correction, and, more particularly, to methods and apparatus to improve power factor at light-load.

BACKGROUND

In electric power systems, power consuming loads are connected to power generating devices. While ideal loads are purely resistive, many loads have some level of reactance (e.g., capacitive reactance or inductive reactance.) When a load is reactive, energy storage within the load causes a phase shift between the voltage and current components of the power being provided to the load. This phase shift results in an increase in the current being provided, which in turn results in an increased apparent power supplied to the load compared to the real power that is being utilized by the load. The difference between apparent power and real power is quantified by a displacement power factor. The displacement power factor is one component of the true power factor. Additionally, Total Harmonic Distortion (THD) can contribute significantly to the power factor of a load. THD occurs in nonlinear loads which introduce harmonics into the power drawn from the power generating device. These additional harmonics result in increased apparent power being drawn by the load.

Purely resistive loads have a unity power factor (i.e., a power factor of one), while reactive loads have a power factor of less than unity. Power companies charge based on apparent power and, therefore, charge more for increased levels of apparent power consumption. Thus, loads with a power factor less than unity may be more expensive to operate than loads with a unity power factor for the same real power input to the load.

DETAILED DESCRIPTION

Many loads have different power factors. For example, resistive loads such as electric heaters have a power factor close to unity, while reactive loads such as electric motors have a power factor that is less than unity (e.g., 0.8, 0.7, etc.). Typically, devices having a reactance of opposite sign are added to the load to correct the power factor and bring the power factor closer to unity. For example, a bank of capacitors may be added to a large inductive load to bring the power factor closer to unity.

In some examples, the reactance of the load may be constant over a number of variables. For example, the reactance may be constant over time or power consumption levels. However, not all loads exhibit constant reactance. When the reactance of the load is constant (e.g., the load continually exhibits the same reactance) a reactive element of opposite sign can easily be added to the circuit of the load to correct the power factor. When the reactance of the load is non-constant (e.g., the load does not exhibit the same reactance over time, frequency, etc.), alternate methods of correcting the power factor are required such as, for example, active power factor correction.

Switching power supplies, like those typically found in computer power supplies, exhibit a non-constant reactive load. For example, the activation and deactivation of individual devices, components, and/or circuitry within the computer and/or computer power supply may vary the reactance of the load while additionally adding harmonics which can contribute to Total Harmonic Distortion (THD). When the reactance of the load varies, the reactive components of opposite sign added to the load must also vary to correct the power factor of the load.

When the reactance of the load varies, active power factor correction may be necessary to correct the power factor. Active power factor correction may involve switching opposite reactive components (e.g., capacitors, inductors, etc.) into the circuit of the load based on the reactance of the load. In some example circuits the reactance can vary quickly, causing the active power correction circuitry to switch the reactive components into and/or out of the circuit of the load rapidly. Rapidly switching power factor correction circuitry can result in switching losses and distortion of the power provided to the load. Switching losses result in an increase in apparent power provided to the load.

In addition to power factor caused by reactance of the load, power factor is also dependent on the THD created by the load. When power is provided to the load, it is provided as a sinusoid. When components of the load are activated and deactivated, the sinusoid is disrupted and harmonics are introduced. The harmonics result in extra power being drawn by the load, and cause a lower power factor. It is important not only to address the displacement power factor (based on the phase shift), but to also address the distortion power factor (based on the THD).

In some examples, non-constant reactivity of the load can be caused when the load is light relative to a maximum rating. Light-load conditions may arise when, for example, devices enter power saving modes. Light-load conditions may give rise to other problems, such as poor efficiency and poor Total Harmonic Distortion (THD). For example, while in terms of the displacement power factor (the power factor resulting from a displacement between the voltage and current provided to the load) the power factor of a load might be near unity, the power factor might in fact be far from unity due to the effects of THD. The example power factor correction systems of the examples illustrated below improve efficiency at light-load conditions by reducing the switching losses experienced. Further, THD is decreased at light-load conditions by period enabling modulating the operation of a current loop on a line-cycle basis.

FIG. 1is a block diagram of an example power factor correction system100. The example power factor correction system100includes a power factor corrector105and a power factor correction controller115. The power factor corrector105and the power factor correction controller115are connected via a power factor correction enable110. The power factor correction system100of the illustrated example receives power via a rectifier140and an alternating current (AC) source130. In the illustrated example, both the power factor corrector105and the power factor correction controller115receive power via the rectifier140; however the power factor correction controller115may additionally or alternatively receive power via the AC source130. The power factor correction system100of the illustrated example outputs a rectified power to a load150.

The power factor corrector105of the illustrated example includes an inductor, a transistor, a diode, and a capacitor. Additionally or alternatively, the power factor corrector105may include analog components such as resistors and/or digital components such as a microcontroller. Further, the power factor corrector105of the illustrated example is a boost topology. However, any other topology might additionally or alternatively be used such as, for example, a buck topology, a flyback topology, a buck-boost topology, etc. Further, in the illustrated example, the power factor corrector105is an active power factor corrector. However, the power factor corrector105could be a passive power factor corrector, or alternatively, might not be present at all.

The power factor correction controller115of the illustrated example is an Application Specific Integrated Circuit (ASIC). However, the power factor correction controller115may additionally or alternatively comprise any other processing circuitry such as, for example, a microprocessor, a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), etc. Further, the power factor correction controller115may include analog circuitry such as, for example, resistors, inductors, capacitors, etc.

The power factor correction enable110of the illustrated example is an electronic interface connecting the power factor correction controller115to the power factor corrector105. The electronic interface of the illustrated example controls a transistor of the power factor corrector105to selectively enable and/or regulate power factor correction. However, in alternative implementations the power factor correction controller115may be integrated with the power factor corrector105such that an enable interface is not necessary. Further, in some implementations, the power factor correction enable110might be connected to a relay external to the power factor corrector105which may cause AC power to bypass the power factor corrector105before being provided to the load150.

The AC source130of the illustrated example is a commercial power source. The AC source provides one hundred and twenty volts alternating at sixty hertz. However, any other power source (e.g., a commercial power source, a non-commercial power source, etc.) utilizing any voltage and frequency may be used.

The load150of the illustrated example is a load that exhibits non-constant reactivity. For example, the load150may be a computer including a switching power supply. However, the load150may represent any type of load such as, for example, a load exhibiting non-constant reactance and/or a load exhibiting constant reactance.

FIG. 2is a block diagram of the example power factor correction system100ofFIG. 1. The power factor correction controller115of the illustrated example includes a PFC input receiver210, a PFC output receiver220, a line synchronizer230, a PFC disable controller240, a mode controller250, and a light-load detector260.

The PFC input receiver210of the illustrated example receives an input from the rectifier140. The input received by the PFC input receiver210is also tied to the power factor corrector105. The PFC input receiver210forwards the received signal to the line synchronizer230, the mode controller250, and the light-load detector260.

The PFC output receiver220of the illustrated example receives an input from the output of the power factor corrector105. The input received by the PFC output receiver220is also tied to the load150. The PFC output receiver220forwards the received signal to the mode controller250and the light-load detector260.

The line synchronizer230of the illustrated example synchronizes to an AC period of a received input power signal. The line synchronizer230receives an input from the PFC input receiver210and transmits an output to the PFC disable controller. In the illustrated example, the line synchronizer is a timing circuit that synchronizes an output to the period of an input. In the illustrated example, the timing circuit is at least one comparator that compares the input AC voltage to a reference voltage. When the input AC voltage is greater than, or alternatively lesser than, the reference voltage, the timing circuit outputs a signal indicating that. In effect, the comparator creates pulses indicative of alternating (e.g., positive and/or negative) periods of the AC signal. Further, the timing circuit might include other components such as, for example, a memory device, an oscillator, etc. Including such additional components may enable the timing circuit to output pulses indicative of the start of an AC period.

Additionally or alternatively, the line synchronizer230might indicate the start of periods of alternating sign of the AC voltage. In the illustrated example, the line synchronizer230receives and synchronizes to input indicative of un-rectified power provided by the AC source130. However, the line synchronizer230might receive and synchronize to input indicative of rectified power provided by the AC source130. The rectified signal of the AC source130might be rectified by, for example, a full bridge rectifier; and the frequency of the rectified power might be twice the frequency of the un-rectified power of the AC source130. In another example, the line synchronizer230could be another component such as, for example, a voltage-controlled oscillator, a crystal oscillator, a phase locked loop, etc.

The PFC disable controller240of the illustrated example controls whether the power factor corrector105corrects the power factor of the power provided to the load by selectively enabling and/or disabling the power factor corrector105via the power factor correction enable110. The PFC disable controller240causes the power factor corrector105to become disabled for at least one AC period when the power factor requires cycle-skipping. The AC period is synchronized by the line synchronizer230, and is an input received by the PFC disable controller240. When the power factor corrector105is disabled, power provided to the load is comprised of power that was stored within the power factor corrector105. Further, the PFC disable controller240of the illustrated example receives inputs from the light-load detector260and the mode controller250.

The mode controller250of the illustrated example outputs a control signal to the PFC disable controller240and receives inputs from the PFC input receiver210and the PFC output receiver220. The mode controller250of the illustrated example provides a control signal to the power factor corrector105via the power factor correction disable controller240. In the illustrated example, the mode controller250ensures that current flowing through the power factor corrector105is in phase with the input voltage provided to the power factor corrector105. This phase correction is related to the displacement power factor described above. In the illustrated example, the mode controller250is a fixed frequency continuous conduction mode controller. However, the mode controller250may additionally or alternatively be a transition mode controller, a discontinuous mode controller, etc.

The light-load detector260of the illustrated example analyzes the input power signal and determines if light-load conditions exist. The light-load detector260receives inputs from the PFC input receiver210and the PFC output receiver220, and provides an output to the PFC disable controller240. Cycle-skipping may be required when, for example, the observed power is low. When the light-load detector260detects that light-load conditions exist, the light-load detector260transmits a signal to the PFC disable controller240to disable power factor correction.

FIG. 3is a diagram300of an example power factor correction boundary305that may be implemented by the power factor correction controller115ofFIGS. 1 and 2. The diagram300illustrates a change in power302drawn by a load over time. The horizontal axis of the diagram300represents time, and the vertical axis of the diagram300represents power output by the power factor correction system100. The power factor correction boundary305represents the light-load boundary implemented by the power factor correction controller115. The power factor correction boundary305is typically between 10 and 25 percent of the maximum power output by the power factor correction system100. However, any other limit may be used for the power factor correction boundary305. For example, the limit might be anything below one third of the maximum power output by the power factor correction system100. Further, the power factor correction boundary305may change over time and alternatively may be configurable based on, for example, the load150. When the power302output by the power factor correction system100is below the power factor correction boundary305, light-load conditions are present, and the power factor correction system100reacts by implementing cycle-skipping as illustrated inFIG. 4. In the illustrated example, the power302output by the power factor correction system100changes over time. In some instances, the power302is high (e.g., near the maximum output power), while at other times, the power302is low (e.g., nearly no power output to the load). In the illustrated example, the power302crosses below the power factor correction boundary305for short periods of time. However, the power302may remain in any state (whether above or below the power factor correction boundary305) for any period of time.

FIG. 4is a diagram400illustrating a cycle-skipping sequence performed by the power factor correction controller115ofFIGS. 1 and 2. The diagram400illustrates components of the power output to the load from the power factor correction system100.

In particular, the diagram illustrates a rectified input current405and an output voltage410. The input current405shows a rectified current provided to the load150. The output voltage410is bounded by an upper voltage limit415and a lower voltage limit420. Further, the diagram400includes a power factor correction disable signal425.

Initially, the power factor correction disable signal425is low, resulting in the power factor corrector being enabled and power being transferred to the load150. When the output voltage410is above the upper voltage limit415and at a zero-crossing of the input current405, the power factor correction disable signal425becomes active, and the power factor corrector is disabled426. Power that is being provided to the load is then sourced from stored energy of the power factor corrector. The voltage410decreases based on the power drawn by the load. When the output voltage410is below the lower voltage limit420, at a zero-crossing of the input current405the power factor correction disable signal425becomes inactive427, and the power factor corrector is enabled.

When a load is light (e.g., below the light-load power boundary described in connection withFIG. 3), the power stored in the power factor corrector will decline slowly until the voltage is lower than the lower voltage limit420. When the load is not light, the power stored in the power factor corrector will decline more quickly. The time required for the output voltage410to decrease to the lower voltage threshold420is proportional to the lightness of the load. Thus, in some examples, there may be one period where the power factor corrector is disabled, while in some other examples, there may be many periods where the power factor corrector is disabled.

Changing the state of the power factor disable signal425at zero-crossings of the input current405ensures no effect on the THD. Switching at a time other than a zero-crossing introduces additional harmonics to be added to the signal, thus reducing the power factor. Further, in the illustrated example, the input current405is rectified and shows two zero-crossings for every AC period.

In the illustrated example, alternating zero-crossings are used to ensure that no DC bias is introduced. Because periods of the power provided to the load are modulated as complete units, this is known as period enabling modulating. Positive periods of the AC power might create a positive DC bias, while negative periods of the AC power might create a negative DC bias. However, enabling and/or disabling the power factor correction disable signal425on half cycles could lead to a finer resolution in output. For example, when switching on half cycles, the difference between the lower voltage limit420and the upper voltage limit415might be reduced. To reduce DC bias, alternating periods of the AC signal might be used to keep the DC bias as close to zero as possible.

FIG. 5is an example schematic500for the power factor corrector105and power factor correction controller115of the example power factor correction system100ofFIG. 1. The example schematic500illustrates a circuit diagram that may be used to implement the example power factor correction system100. As inFIGS. 1 and 2, the example schematic includes the power factor corrector105, the power factor correction controller115, and an enable line between the power factor corrector105and the power factor correction controller115. Additionally, the example schematic500shows the AC source130and the rectifier140.

In the illustrated example, the rectifier140is represented by a full bridge rectifier; however any other type of rectifier may additionally or alternatively be used. Further, in the illustrated example, discrete components (e.g., resistors, capacitors, traces, etc.) are used to join inputs and outputs from the AC source130, the rectifier140, the power factor correction controller115, and the power factor corrector105. However, any other method of interconnecting components may additionally or alternatively be used.

The power factor corrector105of the illustrated example is implemented by an inductor, a diode, a transistor, and a capacitor. However any other method of correcting a power factor may additionally or alternatively be used. For example, the power factor corrector105may be implemented by banks of capacitors and or inductors connected to relays to correct the power factor of the output power.

The power factor correction controller115of the illustrated example is implemented by an integrated circuit having sixteen pins. However, any number of pins may be used. For example, the power factor correction controller115may have eight pins, twenty pins, etc. Further, in the illustrated example, the power factor correction controller115of the illustrated example is a small outline integrated circuit (SOIC), however any other form factor integrated circuit may additionally or alternatively be used. For example, a thin shrink small outline package (TSSOP), or a plastic dual inline package (PDIP) may alternatively be used. Further, while in the illustrated example, the power factor correction controller115is an application specific integrated circuit (ASIC), the power factor correction controller115may be any other type of computing and/or processing device. For example, the power factor correction controller115may be implemented by a digital signal processor (DSP), a field programmable gate array (FPGA), a microprocessor, etc.

FIG. 5Ais an example schematic550for the power factor correction controller115of the example power factor correction system100ofFIG. 1. The example schematic550illustrates a circuit diagram that may be used to implement the example power factor correction controller115. As shown inFIG. 2, the example schematic includes the PFC input receiver210, the PFC output receiver220, the line synchronizer230, the PFC disable controller240, the mode controller250, and the light-load detector260.

In the illustrated example, the PFC input receiver210is shown as a voltage input210V (shown as VINAC) and a voltage input210I (shown as CAI). The voltage input210I of the illustrated example receives a voltage that is proportional to a current that is flowing through the power factor corrector105. The voltage input210V provides an input to the mode controller250and minimizes any phase shift component associated with the received input. Further, the voltage input210V is provided to the line synchronizer230and the light load detector. While in the illustrated example the PFC input receiver210is shown as two voltage inputs, any other type of inputs may additionally or alternatvely be used. For example, the PFC input receiver210might include an operational amplifier to amplify the input; a resistor, an inductor, and/or a capacitor to filter the input; etc.

The PFC output receiver220of the illustrated example is shown as an operational amplifier that receives inputs from a reference voltage, a sensed voltage, and/or a soft-start voltage may be used. However, alternative implementations may use other circuitry. The PFC output receiver220of the illustrated example generates an output proportional to a difference between the sensed voltage and the reference voltages or the soft-start voltage (whichever is lower).

In the illustrated example, the line synchronizer230is a timing circuit that synchronizes an output to the period of an input. In the illustrated example, the line synchronizer230is one or more comparators that compare the input AC voltage to a reference voltage. In turn, the comparators create an output indicative of the start of an AC period. Additionally or alternatively, the line synchronizer230might indicate the start of periods of alternating sign of the AC voltage. The output of the line synchronizer230is passed to the PFC disable controller240. In the illustrated example, the line synchronizer230receives an input from the light load detector250. However, in some examples, the line synchronizer230might not receive an input from the light load detector250. When the input from the light load detector250indicates that light load conditions exist, the line synchronizer230enables and/or disables the power factor corrector105in synchronization with the line voltage.

In the illustrated example, the line synchronizer230receives and synchronizes to input indicative of power provided by the AC source130via the PFC input receiver210V. However, the line synchronizer230might receive and synchronize to input indicative of rectified power provided by the AC source130. The rectified power of the AC source130might be rectified by, for example, a full bridge rectifier; and the frequency of the rectified power might be twice the frequency un-rectified power of the AC source130. In some examples, the line synchronizer230is an oscillator such as, for example, a voltage-controlled oscillator, a crystal oscillator, a phase locked loop, etc.

In the illustrated example, the PFC disable controller240is shown as a Set-Reset latch coupled with a gate driver. The PFC disable controller240controls the signal provided to the power factor corrector105via the power factor correction enable110. In alternative implementations, other circuitry may additionally or alternatively be used to control the signal provided to the power factor corrector105. For example, an operational amplifier utilizing a switched feedback circuit might be used.

The mode controller250of the illustrated example includes a multiplier, a current amplifier, and a comparator. However, some example implementations may use additional or alternative components. The mode controller of the illustrated example receives input signals from the PFC input receiver210(e.g., the voltage input210V and/or the voltage input210I), a voltage feed-forward circuit, reference voltages, and the output of the PFC output receiver220. The mode controller250of the illustrated example processes the received inputs and provides an output to the PFC disable controller240. Additionally or alternatively, other circuitry might be used to create the output to the light-load detector260.

The light-load detector260of the illustrated example analyzes the input power signal and determines if light-load conditions exist. The light-load detector260receives inputs from the PFC input receiver210V and210I (shown as VINAC and CAI), and the PFC output receiver220(shown as VAO), and provides an output to the line synchronizer230. When the light-load detector260detects that light-load conditions exist, the light-load detector260transmits a signal to the PFC disable controller240via the line synchronizer230to disable the power factor corrector105via the power factor correction enable110.

While an example manner of implementing the power factor correction system100ofFIG. 1has been illustrated inFIGS. 2,3,4,5, and5A, one or more of the elements, processes and/or devices illustrated inFIGS. 2,3,4,5, and5A may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way. Further, the example power factor corrector105, the example power factor correction controller115, the PFC input receiver210, the example PFC output receiver220, the example line synchronizer230, the example PFC disable controller240, the example mode controller250, the example light-load detector260, and/or, more generally, the example power factor correction system100ofFIGS. 1 and 2may be implemented by hardware, software, firmware and/or any combination of hardware, software and/or firmware. Thus, for example, any of the example power factor corrector105, the example power factor correction controller115, the PFC input receiver210, the example PFC output receiver220, the example line synchronizer230, the example PFC disable controller240, the example mode controller250, the example light-load detector260, and/or, more generally, the example power factor correction system100ofFIGS. 1 and 2may be implemented by one or more circuit(s), programmable processor(s), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)) and/or field programmable logic device(s) (FPLD(s)), etc. When any of the appended apparatus claims are read to cover a purely software and/or firmware implementation, at least one of the example power factor corrector105, the example power factor correction controller115, the PFC input receiver210, the example PFC output receiver220, the example line synchronizer230, the example PFC disable controller240, the example mode controller250, and/or the example light-load detector260are hereby expressly defined to include a computer-readable medium such as a memory, DVD, CD, etc. storing the software and/or firmware. Further still, the example power factor correction system100ofFIGS. 1 and 2may include one or more elements, processes and/or devices in addition to, or instead of, those illustrated inFIGS. 1 and 2, and/or may include more than one of any or all of the illustrated elements, processes and devices.

A flowchart representative of an example process for implementing the example power factor correction controller115ofFIGS. 1 and 2is shown inFIG. 6. In the examples illustrated above, the example power factor correction controller115ofFIGS. 1 and 2is an integrated circuit implementing the process shown inFIG. 6. However, the power factor correction controller115might be a device capable of executing machine-readable instructions implementing the process shown inFIG. 6. In such examples, the machine-readable instructions comprise a program for execution by a processor such as the processor712shown in the example computer800discussed below in connection withFIG. 7. The program may be embodied in software stored on a computer-readable medium such as a CD-ROM, a floppy disk, a hard drive, a digital versatile disk (DVD), or a memory associated with the processor712, but the entire program and/or parts thereof could alternatively be executed by a device other than the processor712and/or embodied in firmware or dedicated hardware. Further, although the example program is described with reference to the flowchart illustrated inFIG. 6, many other methods of implementing the example power factor correction system100may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined.

FIG. 6is a flowchart representative of a process that may be used to implement the example power factor correction controller115ofFIG. 1. The example process instructions600begin execution when the power factor corrector105operates normally. The PFC disable controller240sets power factor correction enable110to enable the power factor corrector105(block605). Next, the PFC disable controller240receives input from the light-load detector260to determine if light-load conditions are met (block610). If light-load conditions are not met, the output of the PFC disable controller240(the power factor correction enable110) remains enabled. If light-load conditions are met, the PFC disable controller240determines if the power factor corrector105is disabled (block615). If the power factor corrector105is not disabled, the PFC disable controller240determines if the current input state is the beginning of an AC period by receiving an input from the line synchronizer230(block620). As described in connection withFIG. 4, the beginning and/or start of the AC period in the illustrated example is based on the un-rectified AC signal. However, additionally or alternatively, the beginning and/or start of the AC period might be based on the rectified AC signal. If the power factor corrector105is disabled, control proceeds to block630. If the current input state is not the beginning of an AC period, control returns to block610. Assuming the light-load conditions and power factor corrector105enabled/disabled state have not changed, in effect the PFC disable controller240waits for the start of an AC period. Upon the start of the AC period, the PFC disable controller240disables the power factor corrector105via the power factor correction enable110(block625). Control then proceeds to block630. At block630, the PFC disable controller240determines if the output voltage is below a low threshold by inspecting the input received from the mode controller250. If the output voltage is not below the low voltage threshold420, control returns to block610. If the output voltage is below the low voltage threshold420, control proceeds to block635.

Next, the PFC disable controller240determines if light-load conditions are met by evaluating the input received from the light-load detector260(block635). If light-load conditions are not met, control proceeds to block605. If light-load conditions are met, the PFC disable controller240proceeds to determine if the power factor corrector105is disabled (block640). If the power factor corrector105is enabled, control proceeds to block655. If the power factor corrector105is not enabled, the PFC disable controller240determines if the current input state is the beginning of an AC period (block645). If the current input state is not the beginning of the AC period, control proceeds to block635. Again, assuming that the light-load conditions and the power factor corrector105enabled/disabled state do not change, the PFC disable controller240in effect proceeds to wait until the start of an AC period. Upon the start of the AC period, the PFC disable controller240enables the power factor corrector105via the power factor correction enable110(block650), and control proceeds to block655. At block655, the PFC disable controller240determines if the output voltage is above a high threshold415. If the output voltage is not above the high threshold415, control proceeds to block635. If the output voltage is above the high threshold415, control proceeds to block610.

As mentioned above, the example process ofFIG. 6may be implemented using coded instructions (e.g., computer-readable instructions) stored on a tangible computer-readable medium such as a hard disk drive, a flash memory, a read-only memory (ROM), a compact disk (CD), a digital versatile disk (DVD), a cache, a random-access memory (RAM) and/or any other storage media in which information is stored for any duration (e.g., for extended time periods, permanently, brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the term tangible computer-readable medium is expressly defined to include any type of computer-readable storage and to exclude propagating signals. Additionally or alternatively, the example process ofFIG. 6may be implemented using coded instructions (e.g., computer-readable instructions) stored on a non-transitory computer-readable medium such as a hard disk drive, a flash memory, a read-only memory, a compact disk, a digital versatile disk, a cache, a random-access memory and/or any other storage media in which information is stored for any duration (e.g., for extended time periods, permanently, brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the term non-transitory computer-readable medium is expressly defined to include any type of computer-readable medium and to exclude propagating signals.

FIG. 7is a block diagram of an example computer700capable of executing the instructions ofFIG. 6to implement the power factor correction controller115ofFIGS. 1 and 2. The computer700can be, for example, a server, a personal computer, a mobile device (e.g., a cellular phone), or any other type of computing device.

The system700of the instant example includes a processor712. For example, the processor712can be implemented by one or more microprocessors or digital controllers. Other processors may also be appropriate.

The processor712is in communication with a main memory714including a volatile memory718and a non-volatile memory720via a bus722. The volatile memory718may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM) and/or any other type of random access memory device. The non-volatile memory720may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory714is typically controlled by a memory controller (not shown).

The computer700also includes an interface circuit724. The interface circuit724may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), and/or a PCI express interface.

One or more input devices726are connected to the interface circuit724. The input device(s)726permit a user to enter data and commands into the processor712. The input device(s) can be implemented by, for example, a keyboard, a mouse, a touchscreen, a track-pad, a trackball, isopoint and/or a voice recognition system.

One or more output devices728are also connected to the interface circuit724. The output devices728can be implemented, for example, by display devices (e.g., a liquid crystal display, a cathode ray tube display (CRT), a printer and/or speakers). The interface circuit724, thus, typically includes a graphics driver card.

The interface circuit724also includes a communication device (e.g., the request servicer310) such as a modem or network interface card to facilitate exchange of data with external computers via a network (e.g., an Ethernet connection, a digital subscriber line (DSL), a telephone line, coaxial cable, a cellular telephone system, etc.).

The computer700also includes one or more mass storage devices730for storing software and data. Examples of such mass storage devices730include floppy disk drives, hard drive disks, compact disk drives, and digital versatile disk (DVD) drives.

The coded instructions732ofFIGS. 4 and 5may be stored in the mass storage device730, in the volatile memory718, in the non-volatile memory720, in the local memory714, and/or on a removable storage medium such as a CD or DVD. The coded instructions ofFIG. 7may be stored in the mass storage device728, in the volatile memory714, in the non-volatile memory716, and/or on a removable storage medium such as a CD or DVD.

From the foregoing, it will be appreciated that the above disclosed methods and apparatus allow for improved power factors when delivering electricity to a load.