Semiconductor device and method of manufacturing same

In one embodiment, a semiconductor device includes a first insulator, a plurality of interconnections provided in the first insulator. The device further includes a second insulator provided on the first insulator and the plurality of interconnections, and a conductor provided on a first interconnection among the plurality of interconnections and having a shape that is projected upwardly with respect to the first interconnection in the second insulator. The device further includes a plug provided on the first interconnection via the conductor. The device further includes a first pad provided above the plug and electrically connected to the plug, and a second pad provided on the first pad and electrically connected to the first pad.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior International Patent Application No. PCT/JP2018/031321, filed on Aug. 24, 2018, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor device and a method of manufacturing same.

BACKGROUND

To achieve high integration, semiconductor devices such as three-dimensional memories that are each formed of layered memory cells have been developed. With the progress of such layering, some of the three-dimensional memories are manufactured by joining metal pads on a wafer and metal pads on another wafer by a bonding process. In such semiconductor devices, interconnections may be thinned to further improve the integration, or a plug may be formed on a thin interconnection to be connected to an upper-layer interconnection to shorten the interconnection length. In such a case, there are problems that positioning a plug and a corresponding interconnection is difficult, and a short between the plug and another interconnection easily occurs. The same problems may occur in a case where a plug is formed on an interconnection in semiconductor devices other than the three-dimensional memories.

DETAILED DESCRIPTION

In one embodiment, a semiconductor device includes a first insulator, a plurality of interconnections provided in the first insulator. The device further includes a second insulator provided on the first insulator and the plurality of interconnections, and a conductor provided on a first interconnection among the plurality of interconnections and having a shape that is projected upwardly with respect to the first interconnection in the second insulator. The device further includes a plug provided on the first interconnection via the conductor. The device further includes a first pad provided above the plug and electrically connected to the plug, and a second pad provided on the first pad and electrically connected to the first pad.

Embodiments will now be explained with reference to the accompanying drawings. ThroughoutFIGS.1to15B, an identical or similar component is denoted by the same reference numeral, and an overlapping explanation thereof is omitted.

First Embodiment

FIG.1is a cross-sectional view showing the structure of a semiconductor device of a first embodiment. The semiconductor device inFIG.1is a three-dimensional memory in which an array chip1and a circuit chip2are joined together.

The array chip1includes a memory cell array11including a plurality of memory cells, an insulating layer12(e.g., silicon nitride layer) disposed on the memory cell array11, an insulating layer13(e.g., silicon oxide layer) disposed on the insulating layer12, and an inter layer dielectric14disposed under the memory cell array11.

The circuit chip2is disposed below the array chip1via an insulating layer15. The circuit chip2includes an inter layer dielectric16and a substrate17disposed under the inter layer dielectric16. For example, the substrate17is a semiconductor substrate such as a silicon substrate. InFIG.1, an X direction and a Y direction that are parallel to a surface of the substrate17and are perpendicular to each other, and a Z direction that is perpendicular to the surface of the substrate17are shown. The +Z direction and the −Z direction herein are regarded as an upward direction and a downward direction, respectively. However, the −Z direction may match the gravity direction but does not need to match the gravity direction.

The array chip1includes a plurality of word lines WL, a source line SL, and a selection gate SG, as electrode layers in the memory cell array11.FIG.1illustrates a stepped structure21in the memory cell array11. As illustrated inFIG.1, the word lines WL are electrically connected to word interconnection layers23via contact plugs22, the source line SL is electrically connected to a source interconnection layer25via a contact plug24, and the selection gate SG is electrically connected to a selection gate interconnection layer27via a contact plug26. A columnar portion CL passing through the word lines WL, the source line SL, and the selection gate SG is electrically connected to a bit line BL via a plug28.

The circuit chip2includes a plurality of transistors31. The transistors31each include a gate electrode32that is disposed on the substrate17via a gate insulator, and a source diffusion layer and a drain diffusion layer (not illustrated) that are disposed in the substrate17. The circuit chip2further includes a plurality of plugs33that are disposed on the source diffusion layers or drain diffusion layers of the transistors31, interconnection layer34that include a plurality of interconnections and that are disposed on the plugs33, and interconnection layers35that include a plurality of interconnections and that are disposed on the interconnection layers34. A plurality of metal pads36disposed in the insulating layer15are disposed on the interconnection layers35. The array chip1includes interconnection layers37that are disposed on the metal pads36and that include a plurality of interconnections. The word lines WL and the bit lines BL of the present embodiment are electrically connected to the corresponding interconnection layers37.

The array chip1further includes a pad41that is electrically connected to the interconnection layers37via a via plug (not illustrated), an external connection electrode42that is disposed on the pad41, and an external connection pad43that is disposed on the external connection electrode42. The external connection pad43can be connected to a mounting substrate or another device via a solder ball, a metal bump, a bonding wire, or the like.

FIG.2is a cross-sectional view showing the structure of the columnar portion CL of the first embodiment.

As illustrated inFIG.2, the memory cell array11includes a plurality of the word lines WL and a plurality of insulating layers51that are alternately layered on the inter layer dielectric14. The word lines WL are W (tungsten) layers, for example. The insulating layers51are silicon oxide layers, for example.

The columnar portion CL includes a block insulator52, a charge storage layer53, a tunnel insulator54, a channel semiconductor layer55, and a core insulator56. The charge storage layer53is a silicon nitride layer, for example, and is formed on a side face of the word lines WL and the insulating layers51via the block insulator52. The channel semiconductor layer55is a silicon layer, for example, and is formed on a side face of the charge storage layer53via the tunnel insulator54. The block insulator52, the tunnel insulator54, and the core insulator56are silicon oxide layers or metal insulating layers, for example.

FIG.3is a cross-sectional view showing a method of manufacturing the semiconductor device of the first embodiment.

FIG.3illustrates an array wafer W1including a plurality of the array chips1, and a circuit wafer W2including a plurality of the circuit chips2.FIG.3further illustrates a first insulating layer61and a plurality of first metal pads62that are disposed on the lower face of the array wafer W1, and a second insulating layer71and a plurality of second metal pads72that are disposed on the upper face of the circuit wafer W2. The first metal pads62are disposed on the lower faces of the interconnection layers37. The second metal pads72are disposed on the upper faces of the interconnection layers35. In addition, the array wafer W1includes a substrate18on the insulating layer13.

The first insulating layer61is formed on the lower face of the inter layer dielectric14inFIG.3, but the first insulating layer61may be integrally included in the inter layer dielectric14. Similarly, the second insulating layer71is formed on the upper face of the inter layer dielectric16inFIG.3, but the second insulating layer71may be integrally included in the inter layer dielectric16.

First, the array wafer W1and the circuit wafer W2are bonded under a mechanical pressure. As a result, the first insulating layer61and the second insulating layer71are adhered to each other so that the insulating layer15is formed. Next, the array wafer W1and the circuit wafer W2are annealed at 400° C. As a result, the first metal pads62and the second metal pads72are joined so that a plurality of the metal pads36are formed.

Subsequently, the substrate18is removed by CMP (Chemical Mechanical Polishing) or wet etching, and the array wafer W1and the circuit wafer W2are cut into a plurality of chips. In the aforementioned manner, the semiconductor device inFIG.1is manufactured. The external connection electrode42and the external connection pad43are formed on the pad41after the substrate18is removed, for example.

In the present embodiment, the array wafer W1and the circuit wafer W2are joined together. Alternatively, the array wafers W1may be joined together. The above explanation which has been given with reference toFIGS.1to3, and an explanation which will be given later with reference toFIGS.4to15Bare also applicable to a case in which the array wafers W1are joined together. The array wafer W1is also called a memory wafer, and the circuit wafer W2is also called a CMOS wafer.

FIG.4is a cross-sectional view showing the structure of the array chip1of the first embodiment. However, it is to be noted that the upward direction and the downward direction inFIG.4are opposite to those inFIG.1.FIG.4illustrates a state in which the array chip1illustrated inFIG.1is turned upside down. The same applies toFIGS.5A to15B.

As illustrated inFIG.4, the array chip1includes a first inter layer dielectric101which is one example of a first insulator, a plurality of metal interconnections102, a stopper insulator103which is one example of a second insulator, a metal bump104which is one example of a conductor, a spacer insulator105, a second inter layer dielectric106, a via plug107, a metal interconnection108, and a third inter layer dielectric109.FIG.4further illustrates a first insulating layer61and a first metal pad62in the array chip1, and a second metal pad72in the circuit chip2.

The first inter layer dielectric101is an SiO2layer (silicon oxide layer), for example, and constitutes the aforementioned inter layer dielectric14together with the second inter layer dielectric106and the third inter layer dielectric109. The metal interconnection102is a Cu (copper) interconnection, for example, and is formed in the first inter layer dielectric101. The metal interconnection102of the present embodiment is the aforementioned bit line BL.

The stopper insulator103is an SiN layer (silicon nitride layer), for example, and is formed on the first inter layer dielectric101and the metal interconnections102. Reference character103adenotes an opening formed above one metal interconnection102among the metal interconnections102. Hereinafter, the one metal interconnection102is referred to as “first metal interconnection102”. Reference character S1denotes the upper face of the first metal interconnection102. Reference character S2denotes the upper face of the stopper insulator103.

The metal bump104is made from Cu, CoWPB, CoWB, or Sn (Co, B, P, and Sn represent cobalt, boron, phosphorus, and tin, respectively), for example, and is formed in the opening103aof the stopper insulator103. Specifically, the metal bump104is formed on the first metal interconnection102, and has a shape that is projected upwardly with respect to the first metal interconnection102. A plan shape of the metal bump104is a circle, a square, a nearly circular shape, or a nearly square shape, for example. The metal bump104of the present embodiment is formed on the first metal interconnection102by plating. Reference character E2denotes the upper end (highest portion) of the metal bump104.

The spacer insulator105is a plasma SiN layer, for example, and is formed, on the upper face S2of the stopper insulator103and in the opening103aof the stopper insulator103, between the stopper insulator103and the metal bump104. The second inter layer dielectric106is an SiO2layer, for example, and is formed on the spacer insulator105.

In the second inter layer dielectric106, the via plug107is formed on the stopper insulator103, the metal bump104, and the spacer insulator105, and is formed above the first metal interconnection102via the metal bump104. The via plug107includes a barrier metal layer107athat is formed on surfaces of the stopper insulator103, the metal bump104, and the spacer insulator105, and a plug material layer107bthat is formed on the surfaces via the barrier metal layer107a. The barrier metal layer107ais a conductive layer containing Ti (titanium) or Ta (tantalum), for example. The plug material layer107bis a W (tungsten) layer, for example. Like the plan shape of the metal bump104, the plan shape of the via plug107is a circle, a square, a nearly circular shape, or a nearly square shape, for example. However, the area of the upper face of the via plug107is set to be larger than the area of the lower face of the metal bump104. Reference character E1denotes the lower end (lowest portion) of a contact face between the metal bump104and the via plug107.

The metal interconnection108is formed on the via plug107. The third inter layer dielectric109is formed on the second inter layer dielectric106so as to cover the metal interconnection108. The first insulating layer61is formed on the third inter layer dielectric109.

The first metal pad62in the first insulating layer61is formed on the metal interconnection108, is positioned above the via plug107, and is electrically connected to the via plug107via the metal interconnection108. InFIG.4, the area of the upper face of the first metal pad62of the present embodiment is illustrated to be substantially equal to the area of the upper face of the via plug107for easy understanding. However, the area of the upper face of the first metal pad62is set to be two times or more (e.g. ten times or more) larger than the area of the upper face of the via plug107.

The second metal pad72in the second insulating layer71is formed on the first metal pad62, and is electrically connected to the first metal pad62. The area of the lower face of the second metal pad72of the present embodiment is substantially equal to the area of the upper face of the first metal pad62.

As explained so far, the via plug107of the present embodiment is formed above the first metal interconnection102via the metal bump104. Therefore, a contact face between the via plug107and an interconnection disposed therebelow is located to be higher than the upper face S1of the first metal interconnection102. Specifically, the lower end E1of the contact face between the metal bump104and the via plug107is set at a position higher than the upper face S1of the first metal interconnection102.

Accordingly, the distance between the via plug107for the first metal interconnection102and the metal interconnections102excluding the first metal interconnection102can be made long in the up-down direction, whereby a short therebetween and aging deterioration of the stopper insulator103can be inhibited. According to the present embodiment, this distance is made long in the up-down direction even in a case where the metal interconnections102are thin or a case where the distance between the metal interconnections102is narrow. Accordingly, the aforementioned short and aging deterioration can be effectively inhibited. Moreover, according to the present embodiment, even when the positioning accuracy in lithography for the via plug107is low, the aforementioned short can be easily inhibited so that the lithography cost can be reduced.

The metal bump104may be housed in the opening103a. However, it is desirable that the metal bump104is upwardly protruded from the opening103a. Therefore, in the present embodiment, the upper end E2of the metal bump104is set at a position higher than the upper face S2of the stopper insulator103, and the lower end E1of the contact face between the metal bump104and the via plug107is set at a position lower than the upper end E2of the metal bump104. Consequently, a wider short margin between the via plug107for the first metal interconnection102and the metal interconnections102excluding the first metal interconnection102can be ensured.

The metal interconnections102of the present embodiment are the bit lines BL, and are disposed near the columnar portion CL, for example. In a region near the columnar portion CL, it is general that the bit lines BL are thin and the distance between the bit lines BL is narrow. However, according to the present embodiment, the via plug107can be formed on a metal interconnection102that is thin. Therefore, the via plug107can be formed on a metal interconnection102near the columnar portion CL. This results in reduction of the interconnection lengths of the metal interconnections102. The reason for this is that the metal interconnection102does not need to be extended to a point distant from the columnar portion CL so as to allow the via plug107to be formed on that point. Consequently, the integration of the semiconductor device can be further improved, and electrostatic capacitance between the metal interconnections102can be reduced. Further, in the present embodiment, the first metal pad62is disposed directly above (+Z direction) the via plug107, whereby the interconnection length between the first metal pad62and the via plug107can be shortened, and the integration of the semiconductor device can be further improved.

FIGS.5A to8Bare cross-sectional views showing a method of manufacturing the array wafer W1of the first embodiment.

First, a plurality of the metal interconnections102are formed in the first inter layer dielectric101, and the stopper insulator103is formed on the first inter layer dielectric101and the metal interconnections102(FIG.5A). The thickness of the stopper insulator103is 20 to 30 nm, for example.

Next, a resistor111is formed on the stopper insulator103, and an opening111ais formed in the resistor111by lithography and etching (FIG.5B). Next, the stopper insulator103in the opening111ais removed by etching, whereby an opening103ais formed in the stopper insulator103(FIG.5C). Thereafter, the resistor111is removed.

Next, the metal bump104is formed on the metal interconnection102that is exposed to the inner side of the opening103ain the stopper insulator103(FIG.6A). The metal bump104of the present embodiment is formed on the metal interconnection102by electroless plating. As a result, the metal bump104grows so as to have a shape that is projected upwardly with respect to the metal interconnections102. InFIG.6A, the upper end E2of the metal bump104is located at a position higher the upper face S2of the stopper insulator103. Two metal interconnections102disposed under the two metal bumps104inFIG.6Acorrespond to the first metal interconnections102.

Since the metal bump104of the present embodiment is formed by plating, the metal bump104can be formed on the metal interconnection102in a self-alignment manner even in a case where the opening103ais formed at a position slightly deviated from the metal interconnection102. Each of the metal bumps104may be selectively formed only on the upper face of the metal interconnection102, or may be formed, in the opening103a, on the entire upper face of the first inter layer dielectric101and the metal interconnection102.

Next, the spacer insulator105is formed on the entire substrate18(not illustrated) (FIG.6B). As a result, the spacer insulator105is formed on the first inter layer dielectric101, the stopper insulator103, and the surface of the metal bumps104, and in the gap, in the opening103a, between the stopper insulator103and the metal bump104. In a case where such a gap does not exist or is filled with another layer before the spacer insulator105is formed, the spacer insulator105does not need to be formed. The thickness of the spacer insulator105is 2 to 3 nm, for example.

Next, the second inter layer dielectric106is formed on the spacer insulator105(FIG.6C). Next, a base layer112and a resistor113are formed in order on the second inter layer dielectric106(FIG.7A). For example, the base layer112is an organic layer, an antireflection layer (e.g., SiO2layer), or a laminate layer including the organic layer and the antireflection layer.

Next, an opening113ais formed in the resistor113by lithography and etching (FIG.7B). Next, the base layer112in the opening113ais removed by etching so that an opening112ais formed in the base layer112(FIG.7B).

Next, the second inter layer dielectric106in the opening112ais removed by etching so that an opening106ais formed in the second inter layer dielectric106(FIG.8A). Further, the spacer insulator105in the opening106ais removed (FIG.8A). As a result, the metal bump104is exposed to the inside of the opening106a.

Next, the barrier metal layer107aand the plug material layer107bare formed in order in the opening106a(FIG.8B). As a result, the via plug107is formed on the metal interconnection102via the metal bump104. Thereafter, the base layer112is removed, and the resistor113is also removed if the resistor113remains.

FIG.8Billustrates the state in which the via plug107on the right side is formed with a positional deviation. Even if such a positional deviation occurs, the distance between the via plug107and the metal interconnection102is long, as described above. Therefore, a short between the via plug107and the metal interconnection102and aging deterioration of the stopper insulator103can be inhibited. Accordingly, the positioning accuracy of lithography in the step ofFIG.7Bmay be low. For this reason, the lithography cost can be reduced. For example, ArF lithography or KrF lithography may be used in the step ofFIG.7B.

Thereafter, the metal interconnection108, the third inter layer dielectric109, the first insulating layer61, and the first metal pad62, etc. are formed so that the array chip1is manufactured. Moreover, the method illustrated inFIG.3is performed so that the semiconductor device of the present embodiment is manufactured.

In the aforementioned manner, the via plug107is formed above the metal interconnection102via the metal bump104in the present embodiment. Consequently, according to the present embodiment, the via plug107can be suitably formed above the metal interconnection102since a short between the via plug107and the metal interconnection102and aging deterioration of the stopper insulator103can be inhibited.

The via plug107of the present embodiment can be formed by various methods. For example, the via plug107may be formed by single damascene, or may be formed by dual damascene. Alternatively, like the metal bump104, the via plug107may be formed by plating. In addition, in the present embodiment, a surface of the spacer insulator105and a surface of the metal bump104may be polished by CMP (Chemical Mechanical Polishing) at a timing between the step ofFIG.6Band the step ofFIG.6C. In this case, it is desirable that CMP is performed until the upper face of the stopper insulator103is exposed.

Second Embodiment

FIGS.9A to9Care cross-sectional views and a plan view for explaining the structure of a semiconductor device of a second embodiment.

FIGS.9A and9Bare a cross-sectional view and a plan view of the step ofFIG.5C, respectively. LikeFIG.6A,FIG.9Cis a cross-sectional view showing the metal bump104formed on the first metal interconnection102.

FIGS.10A to10Care cross-sectional views and a plan view for explaining the structure of the semiconductor device of the second embodiment.

FIGS.10A to10Ccorrespond toFIGS.9A to9C, respectively. However, the metal bump104inFIG.9Cis formed on the first metal interconnection102that is thick, and the metal bump104inFIG.10Cis formed on the first metal interconnection102that is thin.

As described above, the metal bump104can be formed on the first metal interconnection102that is thin by the method of the first embodiment. However, when the metal bump104is formed on the first metal interconnection102that is thin, a disadvantage such as reduction in the growing speed of the metal bump104is brought about. Therefore, in the present embodiment, an explanation is given of a method for enabling formation of the metal bump104on the first metal interconnection102that is thick while enjoying the benefits of the first embodiment.

FIG.11is a plan view showing the structure of the semiconductor device of the second embodiment.

The semiconductor device of the present embodiment includes a plurality of interconnections L1extending in the X direction, a plurality of the columnar portion CL, and a plurality of the plugs28. The plugs28each include a contact plug28aand a via plug28bthat is disposed on the contact plug28a. One columnar portion CL, one contact plug28adisposed on the one columnar portion CL, and one via plug28bdisposed on the one contact plug28aconstitute one columnar structure. The semiconductor device of the present embodiment includes a plurality of the columnar structures each having this shape.

LikeFIG.4,FIG.11further illustrates a plurality of the metal interconnections102including metal interconnections102ato102d, the metal bump104that is disposed on the metal interconnection102c, and the via plug107that is disposed on the metal bump104. The metal interconnections102extend in the Y direction, and are disposed on the via plugs28b.

The metal interconnections102of the present embodiment each include a first portion P1and a second portion P2each having a first width (W) and a third portion P3that is disposed between the first portion P1and the second portion P2and having a second width (3W) larger than the first width. In the present embodiment, the third portion P3is used for disposition of the metal bump104.FIG.11illustrates the metal bump104that is disposed on the third portion P3of the metal interconnection102c. The second width is set to be three times larger than the first width in the present embodiment, but may be set to be any other value.

In the present embodiment, a majority part of each of the metal interconnections102has the first width, and a minority part of each of the metal interconnections102has the second width. However, since the metal bump104is formed on the second-width part, the growing speed of the metal bump104is high. Therefore, according to the present embodiment, the growing speed of the metal bump104can be made high while the integration is increased with use of the metal interconnections102that are thin.

Hereinafter, regarding the details of the shape of each of the metal interconnections102, the metal interconnection102cis explained as an example.

In the metal interconnection102c, the first portion P1extends in the Y direction, and is connected, at the upper right corner of the third portion P3, to the third portion P3. In addition, the second portion P2extends in the Y direction, and is connected, at the lower left corner of the third portion P3, to the third portion P3. Hereinafter, the upper right corner is referred to as a first point, and the lower left corner is referred to as a second point. In the metal interconnection102c, the position of the first point P1is deviated, in the X direction, from the position of the second point P2. Specifically, these positions are deviated from each other by the X coordinate of 2W.

In the +X direction from the metal interconnection102c, the metal interconnection102dis adjacent to the metal interconnection102c. The position of the third portion P3of the metal interconnection102dis deviated, in the −Y direction, from the position of the third portion P3of the metal interconnection102c. In the −X direction from the metal interconnection102c, the metal interconnection102bis adjacent to the metal interconnection102c. The position of the third portion P3of the metal interconnection102bis deviated, in the +Y direction, from the position of the third portion P3of the metal interconnection102c. The ±Y direction is an example of a first direction, and the ±X direction is an example of the second direction.

This arrangement has an advantage that a region occupied by the metal interconnections102can be reduced while the metal interconnections102include the respective third portions P3, for example. In a case where a certain columnar portion CL in the memory cell array11is selected when writing or the like is executed, this selection needs to be made by selection of one bit line BL and one selection gate SG. This bit line BL and this selection gate SG need to be electrically connected to only one columnar portion CL. For this reason, not only a columnar structure including the columnar portion CL, the contact plug28a, and the via plug28bbut also a structure that is obtained by eliminating the contact plug28aand/or the via plug28bfrom the columnar structure is provided under the third portion P3in FIG.11. The columnar portion CL in this structure is a dummy columnar portion that is not electrically activated. Alternatively, a structure obtained by eliminating at least the columnar portion CL from the columnar structure may be provided under the third portion P3inFIG.11.

FIG.12is a cross-sectional view showing the structure of the semiconductor device of the second embodiment.

FIG.12illustrates a cross section similar to that inFIG.4. It is to be noted that the width of the first metal interconnection102under the metal bump104is 3W. This illustrates a cross section of the third portion P3of the first metal interconnection102.

FIG.13is a plan view schematically showing the structure of the semiconductor device of the second embodiment.

FIG.13illustrates the selection gates SG. These selection gates SG each extend in the X direction, and are adjacent to each other in the Y direction. InFIG.13, the third portion P3of each of the metal interconnections102(bit lines BL) is disposed on any one of the selection gates SG.

FIGS.14A to15Bare planar views showing the method of manufacturing the semiconductor device of the second embodiment. Hereinafter, an explanation is given of a method for forming the metal interconnections102each including the first to third portions P1to P3.

First, a plurality of first core material interconnections121extending in the Y direction are formed on the first inter layer dielectric101(FIG.14A). The first core material interconnections121each include a portion having the first width (W) and a portion having the second width (3W). The first core material interconnections121are formed by lithography or slimming, for example.

Next, a plurality of second core material interconnections122extending in the Y direction are formed on side faces of the first core material interconnections121(FIG.14B). The second core material interconnections122each have a shape including a bent portion near the second-width portion of the corresponding first core material interconnection121.

Next, the first core material interconnections121are removed (FIG.15A). Next, a plurality of the metal interconnections102are formed in gaps between the second core material interconnections122by damascene (FIG.15B). As a result, the metal interconnections102are each formed into a shape including the first to third portions P1to P3. In the present embodiment, the second core material interconnections122are used as a part of the first inter layer dielectric101.

As explained so far, the metal interconnections102of the present embodiment each include a portion having the first width and a portion having the second width that is larger than the first width, and the metal bump104is formed on the portion having the second width. Consequently, according to the present embodiment, the metal bump104can be formed on the metal interconnection102that is thick while the benefits of the first embodiment are enjoyed.