SEMICONDUCTOR DEVICE

A semiconductor device according to an embodiment includes: an element region; and an outer peripheral region surrounding the element region, the outer peripheral region including a semiconductor layer having a first face and a second face opposite to the first face, a first annular conductor provided on a side of the first face with respect to the semiconductor layer and surrounding the element region, a second annular conductor provided on the side of the first face with respect to the semiconductor layer and surrounding the first annular conductor, and at least one first connection conductor provided between the first annular conductor and the second annular conductor and connected to the first annular conductor and the second annular conductor.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-049039, filed on Mar. 24, 2022, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

In a semiconductor chip, a chip ring (seal ring) surrounding an element region may be provided in an outer peripheral region surrounding the element region. The chip ring is formed using a contact layer or a wiring layer constituting the semiconductor chip. Providing the chip ring prevents, for example, intrusion of moisture and movable ions from the outside into the element region, and thus, the reliability of the semiconductor chip is improved.

DETAILED DESCRIPTION

A semiconductor device according to one aspect of the present disclosure includes: an element region; and an outer peripheral region surrounding the element region, the outer peripheral region including a semiconductor layer having a first face and a second face opposite to the first face, a first annular conductor provided on a side of the first face with respect to the semiconductor layer and surrounding the element region, a second annular conductor provided on the side of the first face with respect to the semiconductor layer and surrounding the first annular conductor, and at least one first connection conductor provided between the first annular conductor and the second annular conductor and connected to the first annular conductor and the second annular conductor.

In the present specification, the same or similar components are denoted by the same reference numerals, and redundant description may be omitted.

In the present specification, in order to indicate a positional relationship of components and the like, an upward direction in the drawings may be described by the term “upper”, and a downward direction in the drawings may be described by the term “lower”. In the present specification, the concepts of “upper” and “lower” are not necessarily terms indicating the relationship with the direction of gravity.

First Embodiment

A semiconductor device according to the first embodiment includes: an element region; and an outer peripheral region surrounding the element region, the outer peripheral region including a semiconductor layer having a first face and a second face opposite to the first face, a first annular conductor provided on a side of the first face with respect to the semiconductor layer and surrounding the element region, a second annular conductor provided on the side of the first face with respect to the semiconductor layer and surrounding the first annular conductor, and at least one first connection conductor provided between the first annular conductor and the second annular conductor and connected to the first annular conductor and the second annular conductor.

FIG.1is a schematic top view of the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment is a semiconductor chip100. The semiconductor chip100includes an element region100aand an outer peripheral region100b.

The element region100aincludes, for example, semiconductor elements such as a transistor or a diode (not illustrated). The element region100aincludes, for example, a contact layer and a wiring layer for electrically connecting the semiconductor elements. The element region100ais surrounded by the outer peripheral region100b.

The outer peripheral region100bsurrounds the element region100a. The outer peripheral region100bis provided with, for example, a termination structure (not illustrated). The termination structure has a function of improving the breakdown voltage of the semiconductor chip100.

The outer peripheral region100bincludes a first chip ring10(first annular conductor), a second chip ring20(second annular conductor), and a first connection conductor25.

The first chip ring10surrounds the element region100a. The first chip ring10includes a first region10a, a second region10b, a third region10c, and a fourth region10d.

The first region10aand the second region10bextend in a first direction. The element region100ais provided between the first region10aand the second region10b.

The third region10cand the fourth region10dextend in a second direction. The second direction is orthogonal to the first direction. The element region100ais provided between the third region10cand the fourth region10d.

The second chip ring20surrounds the element region100a. The second chip ring20surrounds the first chip ring10. The second chip ring20includes a fifth region20a, a sixth region20b, a seventh region20c, and an eighth region20d.

The fifth region20aand the sixth region20bextend in the first direction. The element region100ais provided between the fifth region20aand the sixth region20b.

The seventh region20cand the eighth region20dextend in the second direction. The element region100ais provided between the seventh region20cand the eighth region20d.

The fifth region20ais adjacent to the first region10a. The sixth region20bis adjacent to the second region10b. The seventh region20cis adjacent to the third region10c. The eighth region20dis adjacent to the fourth region10d.

The first connection conductor25is provided between the first chip ring10and the second chip ring20. The first connection conductor25is connected to the first chip ring10and the second chip ring20.

The first connection conductor25is provided between the first region10aand the fifth region20a. The first connection conductor25is provided between the second region10band the sixth region20b. The first connection conductor25is provided between the third region10cand the seventh region20c. The first connection conductor25is provided between the fourth region10dand the eighth region20d.

FIGS.2A and2Bare enlarged schematic cross-sectional views of the semiconductor device according to the first embodiment.FIGS.2A and2Bare cross-sectional views of the outer peripheral region100b.

FIG.2Aillustrates a cross section taken along a line AA′ inFIG.1.FIG.2Billustrates a cross section taken along a line BB′ inFIG.1.

The outer peripheral region100bincludes a semiconductor layer50and an interlayer insulating layer51(insulating layer). The semiconductor layer50includes a first face F1and a second face F2. The second face F2faces the first face F1.

The first direction is parallel to the first face F1. The second direction is parallel to the first face F1. The third direction is perpendicular to the first face F1.

The semiconductor layer50is made of, for example, single crystal silicon.

The interlayer insulating layer51is provided on the first face F1side with respect to the semiconductor layer50. The interlayer insulating layer51is provided on the semiconductor layer50. The interlayer insulating layer51is provided between the first chip ring10and the second chip ring20.

The interlayer insulating layer51has, for example, a stacked structure of a plurality of insulating layers (not illustrated). The interlayer insulating layer51is made of, for example, an oxide, an oxynitride, or a nitride. The interlayer insulating layer51contains, for example, silicon oxide or silicon nitride.

The first chip ring10is provided on the first face F1side with respect to the semiconductor layer50. The first chip ring10is provided on the semiconductor layer50. The first chip ring10is in contact with the semiconductor layer50. The first chip ring10is provided in the interlayer insulating layer51.

The first chip ring10includes a first contact layer11(first layer), a first wiring layer12(second layer), a second contact layer13, and a second wiring layer14. The first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14are stacked in this order in the third direction.

The first chip ring10is a conductor. The first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14are conductors.

For example, the chemical composition of the first contact layer11is different from the chemical composition of the first wiring layer12. The first contact layer11is made of, for example, tungsten (W). In addition, the first wiring layer12is made of, for example, copper (Cu).

The minimum width (Wmin inFIG.2A) of the first chip ring10is, for example, equal to or less than 1.0 μm. The minimum width Wmin of the first chip ring10is, for example, the width of the first contact layer11in the second direction.

The second chip ring20is provided on the first face F1side with respect to the semiconductor layer50. The second chip ring20is provided on the semiconductor layer50. The second chip ring20is in contact with the semiconductor layer50. The second chip ring20is provided in the interlayer insulating layer51.

The second chip ring20includes the first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14. The first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14are stacked in this order in the third direction.

The second chip ring20is a conductor. The first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14are conductors. The second chip ring20and the first chip ring10are made of the same material.

The minimum width of the second chip ring20is, for example, equal to or less than 1.0 μm. The minimum width Wmin of the second chip ring20is, for example, the width of the first contact layer11in the second direction.

The first connection conductor25is provided on the first face F1side with respect to the semiconductor layer50. The first connection conductor25is provided on the semiconductor layer50. The first connection conductor25is in contact with the semiconductor layer50. The first connection conductor25is provided in the interlayer insulating layer51.

The first connection conductor25includes the first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14. The first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14are stacked in this order in the third direction.

The first connection conductor25is a conductor. The first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14are conductors. The first connection conductor25and the first chip ring10are made of the same material. The first connection conductor25and the second chip ring20are made of the same material.

Next, functions and effects of the semiconductor chip100according to the first embodiment will be described.

FIG.3is a schematic top view of a semiconductor device according to a comparative example.FIG.3is a diagram corresponding toFIG.1of the first embodiment.

The semiconductor device according to the comparative example is a semiconductor chip900. The semiconductor chip900according to the comparative example is different from the semiconductor chip100according to the first embodiment in that the outer peripheral region100bdoes not include the first connection conductor25.

Similar to the semiconductor chip100according to the first embodiment, the semiconductor chip900according to the comparative example includes a first chip ring10and a second chip ring20in an outer peripheral region100b. Providing the first chip ring10and the second chip ring20prevents intrusion of moisture and movable ions from the outside into an element region100a, and thus, the reliability of the semiconductor chip900is improved.

FIG.4is an explanatory diagram of a problem of the semiconductor device according to the comparative example. The first chip ring10and the second chip ring20of the semiconductor chip900may have, for example, a pattern unformed region X1or a pattern unformed region X2. The pattern unformed region X1and the pattern unformed region X2are generated due to, for example, a collapse of a resist pattern during, for example, the formation of patterns of the first chip ring10and the second chip ring20by a photolithography method. The collapse of the resist pattern occurs notably as the size of the pattern decreases. For example, when the pattern width and the pattern interval are equal to or less than 1.0 μm, the collapse of the resist pattern occurs notably.

When the pattern unformed region X1and the pattern unformed region X2are generated, moisture and movable ions may enter the element region100afrom the outside via the pattern unformed region X1and the pattern unformed region X2. Therefore, the reliability of the semiconductor chip900may be lowered.

The semiconductor chip100according to the first embodiment includes the first connection conductor25between the first chip ring10and the second chip ring20. The pattern of the first connection conductor25functions as a support pattern that supports a resist when the patterns of the first chip ring10and the second chip ring20are formed using a photolithography method.

Therefore, the collapse of the resist pattern during the formation of the patterns of the first chip ring10and the second chip ring20with the photolithography method is suppressed. Accordingly, the generation of the pattern unformed region is suppressed, and the intrusion of moisture and movable ions from the outside into the element region100ais prevented. Thus, the reliability of the semiconductor chip100is improved.

FIG.5is an explanatory diagram for describing functions and effects of the semiconductor device according to the first embodiment.

Due to the first connection conductor25provided between the first chip ring10and the second chip ring20, the semiconductor chip100according to the first embodiment can block a path of entry of moisture and movable ions into the element region100afrom the outside, even if the pattern unformed region X1or the pattern unformed region X2is generated as illustrated inFIG.5. Accordingly, the intrusion of moisture and movable ions from the outside into the element region100ais prevented, whereby the reliability of the semiconductor chip100is improved.

As described above, according to the first embodiment, a semiconductor device capable of preventing intrusion of moisture or movable ions from the outside into the element region100aand having improved reliability can be obtained.

Second Embodiment

A semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that the outer peripheral region further includes a third annular conductor provided on the first face side with respect to the semiconductor layer and surrounding the second annular conductor, and at least one second connection conductor provided between the second annular conductor and the third annular conductor and connected to the second annular conductor and the third annular conductor. In the following, the description overlapping the description of the first embodiment may be partially omitted.

FIG.6is a schematic top view of a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is a semiconductor chip200. The semiconductor chip200includes an element region200aand an outer peripheral region200b.

The outer peripheral region200bincludes a first chip ring10(first annular conductor), a second chip ring20(second annular conductor), a third chip ring30(third annular conductor), a first connection conductor25, and a second connection conductor35.

The third chip ring30surrounds the element region200a. The third chip ring30surrounds the second chip ring20. The third chip ring30includes a ninth region30a, a tenth region30b, an eleventh region30c, and a twelfth region30d.

The ninth region30aand the tenth region30bextend in the first direction. The element region200ais provided between the ninth region30aand the tenth region30b.

The eleventh region30cand the twelfth region30dextend in the second direction. The element region200ais provided between the eleventh region30cand the twelfth region30d.

The ninth region30ais adjacent to the fifth region20a. The tenth region30bis adjacent to the sixth region20b. The eleventh region30cis adjacent to the seventh region20c. The twelfth region30dis adjacent to the eighth region20d.

The second connection conductor35is provided between the second chip ring20and the third chip ring30. The second connection conductor35is connected to the second chip ring20and the third chip ring30.

The second connection conductor35is provided between the fifth region20aand the ninth region30a. The second connection conductor35is provided between the sixth region20band the tenth region30b. The second connection conductor35is provided between the seventh region20cand the eleventh region30c. The second connection conductor35is provided between the eighth region20dand the twelfth region30d.

The third chip ring30is provided on the first face F1side with respect to the semiconductor layer50. The third chip ring30is provided on the semiconductor layer50. The third chip ring30is in contact with the semiconductor layer50. The third chip ring30is provided in the interlayer insulating layer51.

The third chip ring30includes a first contact layer11, a first wiring layer12, a second contact layer13, and a second wiring layer14. The first contact layer11(first layer), the first wiring layer12(second layer), the second contact layer13, and the second wiring layer14are stacked in this order in the third direction.

The third chip ring30is a conductor. The first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14are conductors. The third chip ring30, the first chip ring10, and the second chip ring20are made of the same material.

The minimum width of the third chip ring30is, for example, equal to or less than 1.0 μm. The minimum width Wmin of the third chip ring30is, for example, the width of the first contact layer11in the second direction.

The second connection conductor35is provided on the first face F1side with respect to the semiconductor layer50. The second connection conductor35is provided on the semiconductor layer50. The second connection conductor35is in contact with the semiconductor layer50. The second connection conductor35is provided in the interlayer insulating layer51.

The second connection conductor35includes the first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14. The first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14are stacked in this order in the third direction.

The second connection conductor35is a conductor. The first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14are conductors. The second connection conductor35and the second chip ring20are made of the same material. The second connection conductor35and the third chip ring30are made of the same material.

FIG.7is an explanatory diagram for describing functions and effects of the semiconductor device according to the second embodiment.

Since the semiconductor chip200according to the second embodiment includes the first connection conductor25between the first chip ring10and the second chip ring20, the reliability of the semiconductor chip200is improved as in the semiconductor chip100according to the first embodiment.

In addition, due to the third chip ring30being provided, the semiconductor chip200according to the second embodiment can block a path of entry of moisture and movable ions into the element region200afrom the outside, even if the pattern unformed region X1and the pattern unformed region X2are generated adjacent to each other in the first chip ring10and the second chip ring20as illustrated inFIG.7. Accordingly, the intrusion of moisture and movable ions from the outside into the element region200ais prevented, whereby the reliability of the semiconductor chip200is further improved.

FIG.8is a schematic top view of a semiconductor device according to a modification of the second embodiment. The semiconductor device according to the modification of the second embodiment is a semiconductor chip201. The semiconductor chip201includes an element region200aand an outer peripheral region200b.

The semiconductor chip201according to the modification is different from the semiconductor chip200according to the second embodiment in that a plurality of at least one first connection conductors is repeatedly provided in the first direction between the first region and the fifth region, a plurality of at least one second connection conductors is repeatedly provided in the first direction between the fifth region and the ninth region, and the plurality of at least one first connection conductors and the plurality of at least one second connection conductors are alternately disposed in the first direction.

The semiconductor chip201includes a plurality of first connection conductors25repeatedly provided in the first direction between the first region10aand the fifth region20a. In addition, the semiconductor chip201includes a plurality of second connection conductors35repeatedly provided in the first direction between the fifth region20aand the ninth region30a. In the first direction, the plurality of first connection conductors25and the plurality of second connection conductors35are alternately displaced.

In the semiconductor chip201, the plurality of first connection conductors25and the plurality of second connection conductors35are alternately displaced, so that the pattern of the first connection conductors25and the pattern of the second connection conductors35more robustly function as a support pattern for supporting the resist during the formation of the pattern of the first chip ring10, the second chip ring20, or the third chip ring30using the photolithography method.

Therefore, collapse of the resist pattern during the formation of the patterns of the first chip ring10, the second chip ring20, and the third chip ring30with the photolithography method is further suppressed. Accordingly, the generation of the pattern unformed region is further suppressed, and the intrusion of moisture and movable ions from the outside into the element region200ais prevented. Thus, the reliability of the semiconductor chip201is further improved.

As described above, according to the second embodiment and the modification, a semiconductor device capable of preventing intrusion of moisture or movable ions from the outside into the element region200aand having improved reliability can be obtained.

The first and second embodiments have described, as an example, the case where the first chip ring10, the second chip ring20, and the first connection conductor25are constituted by four layers which are the first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14. However, the first chip ring10, the second chip ring20, and the first connection conductor25may be constituted by, for example, three layers or less or five layers or more.

The first and second embodiments have described, as an example, the case where the first connection conductor25is formed using all of the four layers which are the first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14. However, the first connection conductor25may include at least one layer among the first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14. In other words, the first connection conductor25may not include one or more layers among the first contact layer11, the first wiring layer12, the second contact layer13, and the second wiring layer14.