Semiconductor memory device and method for manufacturing the same

According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: first device regions divided by first isolation films and second device regions divided by second isolation films a gate insulating film formed on the semiconductor substrate; a first element including: a first gate formed on the gate insulating film in the first device regions, a first inter-electrode insulating film formed on the first gate and on the first isolation films, and a second gate formed on the first inter-electrode insulating film; and a second element including: a third gate formed on the gate insulating film in the second device regions, and a fourth gate formed on the third gate and on the second isolation films; wherein a thickness of the third gate is larger than a thickness of the first gate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The entire disclosure of Japanese Patent Application No. 2006-346171 filed on Dec. 22, 2006 including specification, claims, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

An aspect of the present invention relates to a semiconductor memory device and a method for manufacturing the same.

2. Description of the Related Art

NAND-type nonvolatile memories have a structure in which a plurality of memory cell transistors formed on element regions of a semiconductor substrate is serially connected to each other, and select gate transistors are arranged on both sides of the plurality of memory cell transistors. To simplify the manufacturing process steps for the NAND-type nonvolatile memories, the memory cell transistors and the select gate transistors are fabricated simultaneously (see JP-A-2002-176114, for example).

In the fabrication method, a first electrode layer is formed on a memory cell region and a select gate region of the semiconductor substrate. Then, an inter-electrode insulating film is formed on the first electrode layer. The inter-electrode insulating film of the select gate region is partially removed to form an opening that exposes a lower gate electrode layer, while the inter-electrode insulating film of the memory cell region is not removed. Next, a second electrode layer is formed on the semiconductor substrate so that, in the memory cell region, the first and second electrode layers are electrically isolated, and so that, in the select gate region, the first and second electrode layers are electrically connected through the opening. With this, a memory cell gate electrode having a double-layer gate structure including a floating gate electrode layer and a control gate electrode layer is formed in the memory cell region. Meanwhile, a select gate electrode having a single-layer gate structure in which a lower gate electrode layer and an upper gate electrode layer are electrically connected via the opening is formed in the select gate region.

Through the forming of the opening that exposes the lower gate electrode layer in the select gate region, a natural oxide film is formed on the exposed portion of the lower gate electrode layer, causing a conduction failure between the upper gate electrode layer and the lower gate electrode layer. In order to remove the natural oxide film, the exposed portion of the lower gate electrode layer is cleaned with hydrofluoric acid. However, at the time of removing the natural oxide film from the surface of the lower gate electrode layer, the portion of the element isolation insulating film exposed from the opening is also removed. Thus, there is a possibility that the upper surface of the element isolation insulating film exposed from the opening becomes lower than the surface of the semiconductor substrate. As a result, there is a fear that the lower gate electrode layer of the select gate region and the semiconductor substrate are short-circuited.

In the NAND-type nonvolatile memories, there is a problem, known as inter-cell interference, which is accompanied by miniaturization. To suppress the inter-cell interference, it is effective to decrease the thickness of the floating gate electrode layer of the memory cell transistor (see IEEE Non-Volatile Semiconductor Memory Workshop 2006, pages 9 to 11, for example).

However, when the thin floating gate electrode layer is subjected to the hydrofluoric acid cleaning, the following problems may arise. The removal of the inter-electrode insulating film in the select gate region is carried out on the element isolation insulating film as well as on the lower gate electrode layer. Therefore, the element isolation insulating film where the inter-electrode insulating film is removed is also removed by the hydrofluoric acid cleaning. Here, the element isolation insulating film is formed so as to be lower than the upper surface of the floating gate electrode layer in order to increase the capacitive coupling ratio between the control gate electrode layer and the floating gate electrode layer of the memory cell transistor in the memory cell region. Also, the element isolation insulating film is formed so as to protrude from the surface of the semiconductor substrate in order to prevent the control gate electrode layer of the memory cell transistor and the upper gate electrode layer of the select gate transistor from being short-circuited to the semiconductor substrate in the memory cell region and in the select gate region. In this case, if the thickness of the floating gate electrode layer is decreased in order to suppress the inter-cell interference, the element isolation insulating film is over-etched by the hydrofluoric acid cleaning, decreasing the amount of protrusion and thus lowering the upper surface of the element isolation insulating film to be lower than the surface of the semiconductor substrate. As a result, there is a fear that the lower gate electrode layer of the select gate region and the semiconductor substrate are short-circuited.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: first device regions on which circuit elements having a double-layer gate structure is formed, and second device regions on which a circuit elements having a single-layer gate structure is formed; first element isolation insulating films that divide the first device regions with one another; second element isolation insulating films that divide the second device regions with one another; a gate insulating film formed on the semiconductor substrate; a first circuit element including: a first gate electrode layer formed on the gate insulating film in the first device regions, a first inter-electrode insulating film formed on the first gate electrode layer and on the first element isolation insulating films, and a second gate electrode layer formed on the first inter-electrode insulating film; and a second circuit element including: a third gate electrode layer formed on the gate insulating film in the second device regions, and a fourth gate electrode layer formed on the third gate electrode layer and on the second element isolation insulating films; wherein a thickness of the third gate electrode layer is larger than a thickness of the first gate electrode layer.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, the method including: forming a gate insulating film on a semiconductor substrate having a first region in which a first circuit element having a double-layer gate structure is formed and a second region in which a second circuit element having a single-layer gate structure is formed; forming, in the first region, a first gate electrode layer on the gate insulating film; forming, in the second region, a third gate electrode layer having a thickness larger than that of the first gate electrode layer on the gate insulating film; forming, in the first and second regions, the element isolation grooves so as to penetrate through the first and third gate electrode layers and the gate insulating film and so as to reach into the semiconductor substrate; forming, in the first and second regions, first and second element isolation insulating films in the element isolation grooves, respectively; removing upper portions of the first and second element isolation insulating films so that upper surfaces of the first and second element isolation insulating films are aligned with an upper surface of the third gate electrode layer; selectively removing the upper portions of the first element isolation insulating films so that the upper surfaces of the first element isolation insulating films are lower than an upper surface of the first gate electrode layer; forming an inter-electrode insulating film on the first gate electrode layer and on the first element isolation insulating films; removing a natural oxide film formed on a surface of the third gate electrode layer; forming a second gate electrode layer on the inter-electrode insulating film; and forming a fourth gate electrode layer on the third gate electrode layer and on the second element isolation insulating films.

According to still another aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a double-layer gate electrode including: a first gate electrode that has a first thickness and that is formed on the gate insulating film, a first inter-electrode insulating film formed on the first gate electrode, and a second gate electrode formed on the first inter-electrode insulating film; and a single-layer gate electrode including: a third gate electrode that has a second thickness larger than the first thickness and that is formed on the gate insulating film, and a fourth gate electrode formed on the third gate electrode.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, identical or similar parts will be denoted by the same or similar reference numerals. Since the drawings are schematically shown, it should be noted that the relationship between thickness and planar dimension, thickness ratios of respective layers or the like are different from the actual ones. It goes without saying that the dimensional relationship and ratio may differ from drawing to drawing.

First Embodiment

A first embodiment is directed to a NAND-type nonvolatile memory in which the thickness of a third gate electrode layer of a select gate transistor and a MOS transistor is larger than the thickness of a first gate electrode layer of a memory cell transistor.

FIGS. 1A and 1Bare views schematically showing the structure of a NAND-type nonvolatile memory according to the first embodiment, in whichFIG. 1Ais a top view of a memory cell region and a select gate region, andFIG. 1Bis a top view of a peripheral circuit region. As used herein, the term, “memory cell region,” refers to a region on which a first circuit element, i.e., a memory cell transistor, is disposed, and is also referred to as a first region. The term, “select gate region,” refers to a region on which a second circuit element, i.e., a select gate transistor, is disposed, and is also referred to as a second region. The term, “peripheral circuit region,” refers to a region on which a third circuit element, i.e., a peripheral circuit element such as a MOS transistor that is disposed outside the memory cell region and drives the memory cell transistor or the select gate transistor, and is also referred to as a second region. In addition, the term, “third circuit element,” refers to a MOS transistor, a resistor element, a capacitor element, and other dummy patterns.

As shown inFIG. 1A, in a memory cell region1and a select gate region2, a plurality of lines of active areas4aserving as an element forming region is parallely arranged in stripes along the Y direction in the drawing with an element isolation insulating film14interposed between adjacent lines. In the memory cell region1, a plurality of lines of word lines W1, W2, . . . , and W8is parallely arranged in stripes along the X direction in the drawing, perpendicular to the Y direction. At each intersection of the active areas4aand the word lines W1, W2, . . . , and W8, a memory cell transistor6is formed.

In the select gate region2close to the word line W1, a select gate SG1is formed parallel to the word line W1. In the select gate region2close to the word line W8, a select gate SG2is formed parallel to the word line W8. At each intersection of the select gates SG1and SG2and the active areas4a, a select gate transistor7for designating a memory cell block to be accessed is disposed. As used herein, the term, “memory cell block,” refers to a region that includes the memory cell transistors6sandwiched between arbitrary select gate transistors7. On each of the active areas4aoutside the select gate transistors7, a contact10athat connects the memory cell transistor6to a bit line (not shown) is disposed. Under each of the select gates SG1and SG2, an inter-electrode insulating film to be described later is disposed. The inter-electrode insulating film has an opening45with a width smaller than that of the select gates SG1and SG2and extending the total length of the select gates SG1and SG2. Although this embodiment describes and illustrates the memory cell blocks each having eight word lines, an arbitrary number, such as 16, 32, or more, of word lines may be provided. Similarly, an arbitrary number, such as five, or more, of active areas4amay be provided.

Next, the improvement on the inter-cell interference accompanied by the higher integration will be described using the NAND-type nonvolatile memory as an example. As used herein, the term, “inter-cell interference,” refers to a phenomenon in which data written to an intended memory cell changes when data is written to other memory cell adjacent to the intended memory cell. For example, for the memory cell transistors6a,6band6cthat are formed at the intersections of the word line W5and the active areas4a, the case can be contemplated in which electric charges are injected to the floating gates of the memory cell transistors6aand6cin a state that electric charges are not injected to the floating gate of the memory cell transistor6b. In this case, a high electric field is generated when the electric charges are injected to the memory cell transistors6aand6c. The high electric field causes electric charges to be injected to the floating gate of the memory cell transistor6b, thus changing the data written in the memory cell transistor6b. Such a phenomenon becomes conspicuous as the distance between memory cells decreases with the miniaturization because the influence of the electric field generated at the time of writing data to the adjacent memory cell increases.

As shown inFIG. 1B, in a peripheral circuit region3a, there are provided a single active area4bsurrounded by the element isolation insulating film14, and a single gate electrode50disposed on the active area4bso as to across the active area4band reach the element isolation insulating film14. At the intersection of the active area4band the gate electrode50, a MOS transistor8is formed. On the active area4b, impurity diffusion layer regions26serving as a source/drain region are formed with the gate electrode50interposed between adjacent diffusion layer regions. On each of the impurity diffusion layer regions26, a contact10bthat electrically connects the impurity diffusion layer region26to a metal wiring (not shown) is formed. Also, a contact11is formed on the gate electrode50so that the gate electrode50is electrically connected to a metal wiring (not shown) via the contact11. Within the gate electrode50, an inter-electrode insulating film to be described later is provided having an opening45and continuously formed over the active area4band the region of the element isolation insulating film14. Although this embodiment describes and illustrates only one MOS transistor8, a plurality of MOS transistors may be provided. The opening may have an arbitrary shape as long as the opening removes at least a portion of an inside of the gate electrode50.FIGS. 2A to 2Dand3A to3B are sectional views schematically showing the structure of the NAND-type nonvolatile memory of the first embodiment, in whichFIG. 2Ais a sectional view taken along the line A-A inFIG. 1A,FIG. 2Bis a sectional view taken along the line B-B inFIG. 1A,FIG. 2Cis a sectional view taken along the line C-C inFIG. 1A,FIG. 2Dis a sectional view taken along the line D-D inFIG. 1A,FIG. 3Ais a sectional view taken along the line E-E inFIG. 1B, andFIG. 3Bis a sectional view taken along the line F-F inFIG. 1B. Those parts identical or similar to those ofFIGS. 1A and 1Bwill be denoted by the same or similar reference numerals and thus descriptions thereof will be omitted.

As shown inFIGS. 2A to 2Dand3A to3B, a gate insulating film21is formed on a semiconductor substrate20of the memory cell region1, the select gate region2, and the peripheral circuit region3a. On the gate insulating film21of the memory cell region1, a plurality of gate electrodes30of the memory cell transistors6are formed at predetermined intervals. Each of the gate electrodes30of the memory cell transistors6includes a first gate electrode layer (a floating gate electrode layer)22formed on the gate insulating film21, a first inter-electrode insulating film23formed on the first gate electrode layer22, and a second gate electrode layer (a control gate electrode layer)24formed on the first inter-electrode insulating film23. On the second gate electrode layer24, an insulating film25formed of, for example, a silicon nitride film is formed. With this arrangement, the gate electrodes30of the memory cell transistors6have a double-layer gate structure in which the first gate electrode layer22and the second gate electrode layer24are electrically isolated from each other by the first inter-electrode insulating film23. The impurity diffusion layer regions26are formed in the near-surface of the semiconductor substrate20with the gate electrodes30of the memory cell transistors6interposed between adjacent diffusion layer regions.

On the gate insulating film21of the select gate region2, a gate electrode40of the select gate transistor7is formed. The gate electrode40of the select gate transistor7includes a lower gate electrode layer (a third gate electrode layer)43aincluding a first lower gate electrode layer41aformed on a gate insulating film21band having the same thickness as the first gate electrode layer22and a second lower gate electrode layer42aformed on the first lower gate electrode layer41a, a second inter-electrode insulating film44aformed on the second lower gate electrode layer42aand having the same thickness as the first inter-electrode insulating film23, and an upper gate electrode layer (a fourth gate electrode layer)46aformed on the second inter-electrode insulating film44aand having the same thickness as the second gate electrode layer24. The second inter-electrode insulating film44ahas an opening45athat exposes the surfaces of the second lower gate electrode layer42aand a second element isolation insulating film14bdescribed later. The width of the opening45ais smaller than the width of the second lower gate electrode layer42a. On the surface of the second lower gate electrode layer42aexposed from the opening45a, an upper gate electrode layer46ais formed. The insulating film25is formed on the upper gate electrode layer46a. With this arrangement, the gate electrode40of the select gate transistor7has a single-layer gate structure in which the upper gate electrode layer46aand the lower gate electrode layer43aare electrically connected to each other. The impurity diffusion layer regions26are also formed in the near-surface of the semiconductor substrate20with the gate electrode40of the select gate transistor7interposed between adjacent diffusion layer regions.

Here, when comparing the gate electrodes30of the memory cell transistors6and the gate electrode40of the select gate transistor7with each other, the height of the second inter-electrode insulating film44aof the select gate transistor7as observed from the upper surface of the semiconductor substrate20is higher than the height of the first inter-electrode insulating film23of the memory cell transistor6by the amount corresponding to the thickness of the second lower gate electrode layer42a. That is, the thickness of the lower gate electrode layer43aof the select gate transistor7is larger than the thickness of the first gate electrode layer22of the memory cell transistor6.

As shown inFIGS. 2B to 2D, element isolation trenches are formed on portions of the semiconductor substrate20outside the active areas4aand4bon which an element isolation insulating film14is to be formed. The element isolation insulating film14is buried in the element isolation trenches so as to protrude from the upper surface of the semiconductor substrate20. In this embodiment, the element isolation insulating film14that isolates the memory cell transistors6of the memory cell region1from each other is referred to as the first element isolation insulating film14a, and the element isolation insulating film14that isolates the select gate transistors7of the select gate region2is referred to as the second element isolation insulating film14b.

As shown inFIG. 2B, in the opening45aof the second inter-electrode insulating film44aof the select gate region2, the upper gate electrode layer (a fourth gate electrode layer)46ais directly formed on the upper surface of the second element isolation insulating film14bthat includes the upper surface of the lower gate electrode layer43a. The height of the upper surface of the second element isolation insulating film14bas observed from the upper surface of the semiconductor substrate20is lower than the height of the upper surface of the lower gate electrode layer43aand higher than the height of the upper surface of the semiconductor substrate20.

As shown inFIG. 2C, in other areas outside the opening45aof the second inter-electrode insulating film44a, the upper gate electrode layer46ais formed above the upper surface of the second element isolation insulating film14band above the upper surface of the lower gate electrode layer43a, through the second inter-electrode insulating film44ainterposed therebetween. The height of the upper surface of the second element isolation insulating film14bas observed from the upper surface of the semiconductor substrate20is substantially the same as the height of the upper surface of the lower gate electrode layer43a.

As shown inFIG. 2D, in the memory cell region1, the height of the upper surface of the first element isolation insulating film14aas observed from the upper surface of the semiconductor substrate20is lower than the height of the upper surface of the first gate electrode layer22. The first inter-electrode insulating film23is formed on the surfaces of the first inter-electrode insulating film14aand the first gate electrode layer22, and the second gate electrode layer24is formed above the surfaces of the first gate electrode layer22and the first element isolation insulating film14a, through the first inter-electrode insulating film23interposed therebetween.

As shown inFIG. 3A, in the peripheral circuit region3a, the gate electrode50of the MOS transistor8is formed. The gate electrode50of the MOS transistor8includes, similar to the gate electrodes40of the select gate region2, a lower gate electrode layer (a third gate electrode layer)43bincluding a first lower gate electrode layer41bformed above the semiconductor substrate20with a gate insulating film21interposed therebetween and having the same thickness as the first gate electrode layer22and a second lower gate electrode layer42bformed on the first lower gate electrode layer41band having the same thickness as the second lower gate electrode layer42a, a second inter-electrode insulating film44bformed on the lower gate electrode layer43b, and an upper gate electrode layer (a fourth gate electrode layer)46bformed on the second inter-electrode insulating film44b. On the upper gate electrode layer46b, the insulating film25formed of, for example, a silicon nitride film is formed. The second inter-electrode insulating film44bhas an opening45bthat exposes the surfaces of the second lower gate electrode layer42band a second element isolation insulating film14cdescribed later. The width of the opening45bis smaller than the width of the second lower gate electrode layer42b. On the surface of the second lower gate electrode layer42bexposed from the opening45b, an upper gate electrode layer46bis formed. With this arrangement, the gate electrode50of the peripheral circuit region3ahas a single-layer gate structure in which the upper gate electrode layer46band the lower gate electrode layer43bare electrically connected to each other. The impurity diffusion layer regions26are also formed in the near-surface of the semiconductor substrate20with the gate electrode50of the MOS transistor8interposed between adjacent diffusion layer regions.

As shown inFIG. 3B, an element isolation trenches is formed on a portion of the semiconductor substrate20outside the active area4bof the peripheral circuit region3a. The element isolation insulating film14is buried in the element isolation trenches so as to protrude from the upper surface of the semiconductor substrate20. In this embodiment, the element isolation insulating film14that isolates the memory cell transistor8of the MOS transistor8is referred to as the second element isolation insulating film14c. Similar to the case of the select gate region2, the height of the upper surface of the second element isolation insulating film14con which the upper gate electrode layer46bis formed, as observed from the upper surface of the semiconductor substrate20, is lower than the height of the upper surface of the lower gate electrode layer43b.

FIG. 4is a perspective view schematically showing the shape of the second element isolation insulating film14bof the select gate SG1shown inFIGS. 1A to 1Band2A to2D. InFIG. 4, those parts identical or similar to those ofFIGS. 1A to 1Band2A to2D will be denoted by the same or similar reference numerals and thus descriptions thereof will be omitted. As shown inFIG. 4, the select gate SG1extends along the X direction, and the active area4aextends along the Y direction perpendicular to the X direction. At the intersection of the select gate SG1and the active area4a, the select gate transistor7is formed. The second inter-electrode insulating film44ahas the opening45athat exposes the surfaces of the lower gate electrode layer43aand the second element isolation insulating film14b. When removing a natural oxide film formed on the surface of the lower gate electrode layer43aexposed from the opening45a, the upper surface of the second element isolation insulating film14bexposed from the opening45ais removed. In this case, however, the height of the upper surface of the second element isolation insulating film14bwithin the opening45aas observed from the upper surface of the semiconductor substrate20becomes lower than the height of the upper surface of the lower gate electrode layer43abut is higher than the height of the upper surface of the semiconductor substrate20.

Next, a fabrication method of the NAND-type nonvolatile memory will be described with reference toFIGS. 5A to 36B.FIGS. 5A to 36Bare sectional views schematically showing the fabrication process steps of the NAND-type nonvolatile memory.

As shown inFIGS. 5A to 5Dand6A to6B, on the semiconductor substrate (for example, a silicon substrate)20, the gate insulating film21formed of, for example, a silicon oxide film (herein after referred to as SiO2) is formed to a thickness of about 50 Å to about 100 Å. On the gate insulating film21, the first gate electrode layer22formed of, for example, polycrystalline silicon is formed to a thickness of about 30 Å to about 50 Å. Here, the first gate electrode layer22constitutes the first gate electrode layer22of the memory cell region1, and the first lower gate electrode layers41aand41bof the select gate region2and the peripheral circuit region3a, respectively. In the following descriptions, the first gate electrode layer22of the memory cell region1will be referred to as the first gate electrode layer22, and the first gate electrode layer22of the select gate region2and the peripheral circuit region3awill be referred to as the first lower gate electrode layers41aand41b. On the first gate electrode layer22and the first lower gate electrode layers41aand41b, a first mask material27formed of, for example, a silicon nitride film (SiN) is formed to a thickness of 20 nm or more.

As shown inFIGS. 7A to 7Dand8A to8B, a photoresist (not shown) is deposited onto the first mask material27and is lithographically patterned so as to cover the memory cell region1, thereby forming a photoresist pattern that exposes other areas outside the memory cell region1. Using the photoresist as a mask, the first mask material27outside the memory cell region1is etched and removed. Thereafter, the photoresist pattern on the memory cell region1is removed.

As shown inFIGS. 9A to 9Dand10A to10B, on the first gate electrode layer22and the first mask material27, the second lower gate electrode layers42aand42bformed of, for example, polycrystalline silicon is formed to such a thickness that the upper surfaces thereof are 20 nm or more higher than the upper surface of the first mask material27on the first gate electrode layers41aand41b.

As shown inFIGS. 11A to 11Dand12A to12B, the second lower gate electrode layers42aand42bare polished by a CMP (Chemical Mechanical Polishing) process until the upper surface of the first mask material27is exposed. At this time, as a result of over-etching, the second lower gate electrode layers42aand42bare also removed by about 5 nm to about 10 nm.

As shown inFIGS. 13A to 13Dand14A to14B, on the first mask material27and the second lower gate electrode layers42aand42b, a second mask material28formed of, for example, the same material as the first mask material27is formed to a thickness of about 40 nm. As shown inFIGS. 15A to 15Dand16A to16B, the second mask material28is lithographically patterned. Thereafter, using the patterned, second mask material28as a mask, the first gate electrode layer22and the gate insulating film21of the memory cell region1, the first and second lower gate electrode layers41aand42aand the gate insulating film21of the select gate region2, and the first and second lower gate electrode layers41band42band the gate insulating film21of the peripheral circuit region3aare etched to form the element isolation trenches15in respective regions1,2and3a, reaching into the semiconductor substrate20.

As shown inFIGS. 17A to 17Dand18A to18B, the element isolation insulating film14formed of, for example, a silicon oxide film (SiO2) is buried in the element isolation trenches15. Thereafter, using the second mask material28as a stopper, the element isolation insulating film14is planarized by a CMP process. In this way, in the memory cell region1, the first element isolation insulating film14afor isolating the memory cell transistors6from each other is formed. In the select gate region2, the second element isolation insulating film14bfor isolating the select gate transistors7from each other is formed. In the peripheral circuit region3a, the second element isolation insulating film14cfor isolating the MOS transistor8from other elements is formed.

As shown inFIGS. 19A to 19Dand20A to20B, the upper portion of the element isolation insulating film14is etched so that the height of the upper surfaces of the first element isolation insulating film14aand the second element isolation insulating films14band14cas observed from the upper surface of the semiconductor substrate20is controlled so as to be the same as the height of the upper surfaces of the second lower gate electrode layers42aand42b. In this way, the height of the upper surfaces of the second element isolation insulating films14band14cfrom the upper surface of the semiconductor substrate20is about 40 nm or more.

As shown inFIGS. 21A to 21Dand22A to22B, in a state in which other areas outside the memory cell region1are masked with a photoresist29, the upper portion of the first element isolation insulating film14ais etched so that the height of the upper surface of the first element isolation insulating film14ais higher than the height of the upper surface of the semiconductor substrate20and lower than the height of the upper surface of the first gate electrode layer22, as shown inFIG. 21D. In this case, since the second element isolation insulating films14band14care covered with the photoresist29, the films are not etched and thus their heights are not changed.

As shown inFIGS. 23A to 23Dand24A to24B, after removing the photoresist29and the second mask material28, on the first and second element isolation insulating films14a,14band14c, the first gate electrode layer22, and the second lower gate electrode layers42aand42b, the inter-electrode insulating film23formed of, for example, an ONO (Oxide-Nitride-Oxide) film is formed to a thickness of about 12 nm to about 17 nm. Here, the inter-electrode insulating film23constitutes the first inter-electrode insulating film23of the memory cell region1, and the second inter-electrode insulating films44aand44bof the select gate region2and the peripheral circuit region3a, respectively. In the following descriptions, the inter-electrode insulating film23of the memory cell region1will be referred to as the first inter-electrode insulating film23, and the inter-electrode insulating film23of the select gate region2and the peripheral circuit region3awill be referred to as the second inter-electrode insulating films44aand44b. Subsequently, on the first and second inter-electrode insulating films23,44aand44b, the second gate electrode lower layer24aformed of, for example, polycrystalline silicon is formed to a thickness of about 30 nm to about 60 nm. Here, the second gate electrode lower layer24aconstitutes a portion of the second gate electrode layer24of the memory cell region1and portions of the upper gate electrode layers46aand46bof the select gate region2and the peripheral circuit region3a, respectively. In the following descriptions, the second gate electrode layer24of the memory cell region1will be referred to as the second gate electrode lower layer24a, and the second gate electrode lower layer24aof the select gate region2and the peripheral circuit region3awill be referred to as the upper gate electrode lower layers46a-1and46b-1, respectively.

As shown inFIGS. 25A to 25Dand26A to26B, in order to form the openings45aand45bin the second inter-electrode insulating films44aand44b, a photoresist (not shown) is deposited onto the second gate electrode lower layer24aand the upper gate electrode lower layers46a-1and46b-1and is lithographically patterned. Thereafter, using the patterned photoresist as a resist mask, portions of the upper gate electrode lower layer46a-1and the second inter-electrode insulating film44aof the select gate region2and portions of the upper gate electrode lower layer46b-1and the second inter-electrode insulating film44bof the peripheral circuit region3aare removed to form the openings45aand45bin the respective regions2and3a, exposing the surfaces of the lower gate electrode layers43aand43band the surfaces of the second inter-electrode insulating films14band14cto the second inter-electrode insulating films44aand44b, respectively. Thereafter, the resist mask is removed.

As shown inFIGS. 27A to 27Dand28A to28B, in order to remove a natural oxide film (not shown), such as SiO2, formed on the surfaces of the lower gate electrode layers43aand43bexposed from the openings45aand45bof the second inter-electrode insulating films44aand44bof the select gate region2and the peripheral circuit region3a, a cleaning treatment is performed using a hydrofluoric acid-based solution, such as a solution of hydrogen fluoride or fluorinated acid. In this case, as shown inFIGS. 27B and 28B, the surfaces of the second element isolation insulating films14band14cformed of SiO2, exposed from the openings45aand45bof the second inter-electrode insulating films44aand44bare also removed by about 30 nm by the cleaning treatment using the hydrofluoric acid-based solution. However, the height of the upper surfaces of the element isolation insulating films14band14cfrom the upper surface of the semiconductor substrate20is at least 10 nm and is higher than the height of the upper surface of the semiconductor substrate20. The height of the upper surfaces of the second element isolation insulating films14band14cas observed from the upper surface of the semiconductor substrate20may be lower than the height of the upper surfaces of the first lower gate electrode layers41band41cas long as it is higher than the height of the upper surface of the semiconductor substrate20.

As shown inFIGS. 29A to 29Dand30A to30B, on the surface of the second gate electrode lower layer24a, the surfaces of the lower gate electrode layers43aand43bexposed from the openings45aand45bof the second inter-electrode insulating films44aand44b, and the surfaces of the second element isolation insulating films14band14c, the second gate electrode upper layer24bis formed to a thickness of about 60 nm to about 100 nm. Here, the second gate electrode upper layer24bconstitutes a remaining portion of the second gate electrode layer24of the memory cell region1and the remaining portions of the upper gate electrode layers46aand46bof the select gate region2and the peripheral circuit region3a. In the following descriptions, the second gate electrode upper layer24bof the memory cell region1will be referred to as the second gate electrode upper layer24b, and the second gate electrode upper layer24bof the select gate region2and the peripheral circuit region3awill be referred to as the upper gate electrode upper layers46a-2and46b-2, respectively.

As shown inFIGS. 31A to 31Dand32A to32B, on the second gate electrode layer24of the memory cell region1and the upper gate electrode layers46aand46bof the select gate region2and the peripheral circuit region3a, the insulating film25formed of, for example, a silicon nitride film (SiN) is formed to a thickness of about 100 nm to about 200 nm. As shown inFIGS. 33A to 33Dand34A to34B, a third mask material31formed of, for example, a silicon oxide film (SiO2) is formed on the insulating film25. Thereafter, the third mask material31is lithographically patterned.

As shown inFIGS. 35A to 35Dand36A to36B, using the third mask material31as a mask, the insulating film25, the second gate electrode layer24, the upper gate electrode layers46aand46b, the first and second inter-electrode insulating films23,44aand44b, the first gate electrode layer22, and the lower gate electrode layers43aand43bare anisotropically etched to form the gate electrodes30,40,50of the memory cell transistors6, the select gate transistors7, and the MOS transistor8, respectively. Thereafter, the third mask material31is removed, and using the gate electrodes30,40and50as a mask, the impurity diffusion layer regions26are formed in the semiconductor substrate20by an ion implantation method. In some cases, the third mask material31may be completely removed by the anisotropic etching of the insulating film25when forming the gate electrodes30,40and50.

In this way, the memory cell transistors6having a double-layer gate structure are formed on the semiconductor substrate20, wherein each of the memory cell transistors6includes the first gate electrode layer22formed on the semiconductor substrate20with the gate insulating film21interposed therebetween and the second gate electrode layer24formed on the first gate electrode layer22with the first inter-electrode insulating film23interposed therebetween. At the same time, the select gate transistors7and the MOS transistor8having a single-layer gate structure are formed on the semiconductor substrate20, wherein each of the transistors7and8includes the lower gate electrode layers (the third gate electrodes)43aand43bhaving a stacked structure of the first lower gate electrode layers41aand41bformed on the semiconductor substrate20with the gate insulating film21interposed therebetween and the second lower gate electrode layers42aand42bstacked on the first lower gate electrode layers41aand41b, the second inter-electrode insulating films44aand44bhaving the openings45aand45band formed on the lower gate electrode layers43aand43b, and the upper gate electrode layers46aand46bformed on the second inter-electrode insulating films44aand44band electrically connected to the lower gate electrode layers43aand43b.

An inter layer insulating film (not shown) is formed on the entire surface of the semiconductor substrate20so as to cover the gate electrodes30,40and50. Thereafter, the contacts10aand10bare penetrated through the inter layer insulating film and the gate insulating film21so as to be connected to the surfaces of the impurity diffusion layer regions26, and the contact11is penetrated through the inter layer insulating film and the insulating film25so as to be connected to the upper gate electrode layers46aand46b. Subsequently, an upper metal wiring (not shown) is formed on the inter layer insulating film for transferring electrical signals. In this way, a NAND-type nonvolatile memory is obtained.

According to this embodiment, the thicknesses of the lower gate electrode layers43aand43bof the select gate region2and the peripheral circuit region3aare larger than the thickness of the first gate electrode layer22of the memory cell region1. That is, the lower gate electrode layers43aand43bare constructed in a laminated structure in which the second lower gate electrode layers42aand42bare stacked on the first lower gate electrode layers41aand41bthat are the same as the first gate electrode layer22, so that the thicknesses of the lower gate electrode layers43aand43bare larger than the thickness of the first gate electrode layer22of the memory cell region1. In addition, the height of the upper surfaces of the second element isolation insulating films14band14cis controlled so as to be substantially the same as the height of the upper surfaces of the lower gate electrode layers43aand43b. When removing the natural oxide film formed on the surfaces of the lower gate electrode layers43aand43bexposed from the openings45aand45bof the second inter-electrode insulating films44aand44b, the upper portions of the second element isolation insulating films14band14cexposed from the openings45aand45bare removed. In this case, however, the height of the upper surfaces of the second element isolation insulating films14band14cwithin the openings45aand45bas observed from the upper surface of the semiconductor substrate20becomes lower than the height of the upper surfaces of the lower gate electrode layers43aand43bbut is higher than the height of the upper surface of the semiconductor substrate20. For this reason, it is possible to prevent the upper gate electrode layers46aand46bof the select gate transistors7and the MOS transistor8from being electrically short-circuited to the semiconductor substrate20.

The height of the upper surfaces of the second element isolation insulating films14band14con which the upper gate electrode layers46aand46bare formed, as observed from the upper surface of the semiconductor substrate20can be increased by increasing the thickness of the second lower gate electrode layers42aand42b. That is, even when the first gate electrode layer22of the memory cell transistor6is made thin, by forming the second lower gate electrode layers42aand42bon the first lower gate electrode layers41aand41band by increasing the thicknesses of the second lower gate electrode layers42aand42b, it is possible to maintain the height, as observed from the upper surface of the semiconductor substrate20, of the upper surfaces of the second element isolation insulating films14band14cwhich are adjacent to the select gate transistors7and the MOS transistor8of the peripheral circuit region3aand on which the upper gate electrode layers46aand46bare formed. Accordingly, by increasing the thicknesses of the second lower gate electrode layers42aand42b, the first gate electrode layer22of the memory cell transistor6can be made thin enough to suppress the inter-cell interference.

In the above-described embodiment, the lower gate electrode layers43aand43bof the select gate transistors7and the MOS transistor8may be formed in a different manner. That is, after the first gate electrode layer22(the first lower gate electrode layers41aand41b) and the second lower gate electrode layers42aand42bare formed, in a state that other areas outside the memory cell region1masked with a resist mask, the second lower gate electrode layer of the memory cell region1is removed by an RIE (Reactive Ion Etching) or wet etching process to form the lower gate electrode layers43aand43b.

The removal of the natural oxide film from the surfaces of the lower gate electrode layers43aand43bexposed from the openings45aand45bof the second inter-electrode insulating films44aand44bmay be performed using any solution other than the hydrofluoric acid-based solution if the solution can etch an oxide film.

On the upper surface of the second gate electrode layer24of the memory cell transistors6and the upper surfaces of the upper gate electrode layers46aand46bof the select gate transistors7and the MOS transistor8, metals such as tungsten may be laminated to decrease the electric resistance of the gate electrodes. For example, polycrystalline silicon is used in the second gate electrode layer24and the upper gate electrode layers46aand46b, metals such as cobalt, manganese or magnesium are deposited onto the second gate electrode layer24and the upper gate electrode layers46aand46b, and a heat treatment is performed to form a silicide layer thereon.

The element isolation trenches or the gate electrodes may be formed using a soft mask such as a photoresist.

At the time of forming the second gate electrode layer24and the upper gate electrode layers46aand46b, the second gate electrode lower layer24aand the upper gate electrode lower layers46a-1and46b-1, and the second gate electrode upper layer24band the upper gate electrode upper layers46a-2and46b-2may be sequentially formed after the openings45aand45bare formed in the second inter-electrode insulating films44aand44b.

The opening45bof the second inter-electrode insulating film44bof the peripheral circuit region3amay be formed in a different shape. As shown inFIG. 37A, the opening45bmay have the same width as that of the gate electrode50(the lower gate electrode layer43b) and be shaped to expose a portion of the second element isolation insulating film14con one side of the active area4band a portion of the gate electrode50. As shown inFIG. 37B, the opening45bmay have an H-letter shape that partially exposes the gate electrode50on the active area4band the second element isolation insulating film14cin the vicinity of the active area4b. As shown inFIG. 37C, the opening45bmay be multiple slits that expose a portion of the gate electrode50on the active area4band a portion of the second element isolation insulating film14cin the vicinity of the active area4b.

During processing of the gate electrodes30,40and50, as shown inFIGS. 38A to 38Dand39A to39B, the insulating film25may be planarized by a CMP process before forming the third mask material31on the insulating film25. In this case, it is possible to improve the lithography margin and the process margin in patterning the gate electrodes.

The active area4bof the peripheral circuit region3amay be provided with a plurality of MOS transistors8, and alternatively, a plurality of active areas4bmay be provided so that a plurality of MOS transistors8may be formed. The type of the MOS transistor8may be either N-type or P-type.

In the fabrication method of the above-described embodiment, the element isolation insulating film14is formed after forming the gate insulating film21. However, a so-called post-gate process may be employed in which the element isolation insulating film14is formed before forming the gate insulating film21.

The first gate electrode layer22may be formed of a material different from that of the second gate electrode layer24.

Even when the height of the upper surface of the element isolation insulating film14aof the memory cell region1as observed from the upper surface of the semiconductor substrate20is decreased to be lower than the height of the upper surface of the semiconductor substrate20, by controlling the thickness of the second lower gate electrode layer42a, it is possible to provide the same advantages as provided by this embodiment.

Second Embodiment

A second embodiment is directed to a NAND-type nonvolatile memory in which a resistor element is constructed in a single-layer gate structure similar to the MOS transistor, the resistor element formed in a peripheral circuit region different from the peripheral circuit region on which the MOS transistor is formed.

FIGS. 40A to 40Care views schematically showing the structure of a resistor element of a NAND-type nonvolatile memory according to the second embodiment, in whichFIG. 40Ais a top view schematically showing the structure of the resistor element,FIG. 40Bis a sectional view taken along the line A-A inFIG. 40A, andFIG. 40Cis a sectional view taken along the line B-B inFIG. 40A. Those parts identical or similar to those of the first embodiment will be denoted by the same or similar reference numerals, and thus only characteristic portions of this embodiment will be described.

As shown inFIG. 40A, in this embodiment, a resistor element100is formed a peripheral circuit region3bdifferent from the peripheral circuit region3aon which the MOS transistor is formed. The resistor element100includes a gate electrode60formed on an active area4csurrounded by the second element isolation insulating film14cand extending along the Y direction in the drawing onto the second element isolation insulating film14cwhile dividing the active area4cinto left and right regions, and contacts16aand16bprovided at both end portions of the gate electrode60, respectively, for giving electric potential to the gate electrode60.

As shown inFIGS. 40B and 40C, the gate electrode60includes the lower gate electrode layer43bformed on the semiconductor substrate20with the gate insulating film21interposed therebetween and having a stacked structure of the first and second lower gate electrode layers41band42b, i.e., having substantially the same structure as the MOS transistor8of the first embodiment, the second inter-electrode insulating film44bhaving the opening45band formed on the lower gate electrode layer43b, the upper gate electrode layer46bformed on the second inter-electrode insulating film44b, and the insulating film25formed on the upper gate electrode layer46b.

The opening45bof the second inter-electrode insulating film44bextends over the lower gate electrode layer43band the second element isolation insulating film14b. The height of the upper surface of the second element isolation insulating film14bon which the second inter-electrode insulating film44bis formed, as observed from the upper surface of the semiconductor substrate20is substantially the same as the height of the upper surface of the lower gate electrode layer43b, The height of the upper surface of the second element isolation insulating film14bon which the upper gate electrode layer46bis formed, as observed from the upper surface of the semiconductor substrate20is lower than the height of the upper surface of the lower gate electrode layer43band higher than the height of the upper surface of the semiconductor substrate20.

The contacts16aand16bare disposed at both end portions of the gate electrode60, respectively, and are penetrated through the insulating film25, reaching into the upper gate electrode layer46b.

The structures of the memory cell transistors6, the select gate transistors7and the MOS transistor8are the same as those of the first embodiment. The fabrication method of the resistor element is the same as that of the NAND-type nonvolatile memory of the first embodiment, and thus descriptions thereof will be omitted.

According to this embodiment, it is possible to provide the same advantages as provided by the first embodiment. Besides, by constructing the lower and upper gate electrode layers43band46bas a resistor body and providing the contacts16aand16bat both end portions of the gate electrode60, it is possible to obtain a resistor element in an easy manner.

In this embodiment, the resistance of the resistor element can be easily changed by changing the distance between the contacts16aand16band the number of contacts, the thickness of the second lower gate electrode layer42b, the shape of the opening45bof the second inter-electrode insulating film44b, or the shape of the gate electrode60.

A plurality of resistor elements may be provided in series or parallel and be connected to the upper metal wiring, thereby making various resistor elements.

Third Embodiment

A third embodiment is directed to a NAND-type nonvolatile memory in which a capacitor element is constructed in a single-layer gate structure similar to the MOS transistor, the resistor element formed in a peripheral circuit region different from the peripheral circuit region on which the MOS transistor is formed.

FIGS. 41A to 41Care views schematically showing the structure of a capacitor element of a NAND-type nonvolatile memory according to a third embodiment, in whichFIG. 41Ais a top view showing the structure of the capacitor element,FIG. 41Bis a sectional view taken along the line A-A inFIG. 41A, andFIG. 41Cis a sectional view taken along the line B-B inFIG. 41A. Those parts identical or similar to those of the first embodiment will be denoted by the same or similar reference numerals, and thus only characteristic portions of this embodiment will be described.

As shown inFIG. 41A, in this embodiment, a capacitor element110is formed in a peripheral circuit region3cdifferent from the peripheral circuit region3aon which the MOS transistor is formed. The capacitor element110includes the second element isolation insulating film14cdisposed within a first active area4d, a gate electrode70having a second active area4esurrounded by the second element isolation insulating film14cand formed on the second element isolation insulating film14cand the second active area4eso as to cover the second element isolation insulating film14cand the second active area4e, a contact17aformed in the gate electrode70on the second element isolation insulating film14c, an inter-gate insulating film33formed of, for example, SiN or BPSG (Boron Phosphorous Silicon Glass) and provided on the first active area4don which the gate electrode70is not formed, and a contact17bfor giving electric potential to the gate electrode70and the semiconductor substrate20.

As shown inFIGS. 41B and 41C, the gate electrode70includes the lower gate electrode layer43bformed on the semiconductor substrate20with the gate insulating film21interposed therebetween and having a stacked structure of the first and second lower gate electrode layers41band42b, i.e., having substantially the same structure as the MOS transistor8of the first embodiment, a second inter-electrode insulating film44cextending over the lower gate electrode layer43band the second element isolation insulating film14cand having three openings45carranged parallel with each other, and the upper gate electrode layer46bformed on the second inter-electrode insulating film44c. The lower and upper gate electrode layers43band46bare constructed in a single-layer gate structure by being electrically connected to each other by the openings45cof the second inter-electrode insulating film44c.

The contact17ais penetrated through the insulating film25within the opening45, reaching into the upper gate electrode layer46b. Meanwhile, the contact17bis penetrated through the gate insulating film21, reaching the surface of the semiconductor substrate20. In this way, the capacitor element110is constructed in which the gate electrode70functions as one terminal of the capacitor, the semiconductor substrate20functions as the other terminal of the capacitor, and the gate insulating film21formed on the second active area4efunctions as an insulator

The fabrication method of the capacitor element is the same as that of the NAND-type nonvolatile memory of the first embodiment, and thus descriptions thereof will be omitted.

According to this embodiment, it is possible to provide the same advantages as provided by the first embodiment. Besides, by providing the contact17ato the gate electrode70and providing the contact17bto the semiconductor substrate20, it is possible to obtain a capacitor element in an easy manner.

In this embodiment, the capacitance of the capacitor element may be easily changed by changing the thickness of the gate insulating film21or the size of the second active area4e.

A plurality of capacitor elements may be provided in series or parallel and be connected to the upper metal wiring, thereby making various capacitor elements.

The openings45cmay be provided in a singular form and may have other shapes such as an elliptical shape, other than a rectangular shape. In addition, the openings45cmay not contain the contact17a.

The contact17aprovided to the gate electrode70and the contact17bprovided to the semiconductor substrate20may be provided in a plural form.

Fourth Embodiment

A fourth embodiment is directed to, as similarly to the first embodiment, the NAND-type nonvolatile memory in which the second inter-electrode insulating films between the lower gate electrode layers and the upper gate electrode layers of the select gate region and the peripheral circuit region are removed.

FIGS. 42A to 44Bare views schematically showing the structure of a NAND-type nonvolatile memory according to the fourth embodiment, in whichFIG. 42Ais a top view of a memory cell region and a select gate region,FIG. 42Bis a top view schematically showing the structure of a MOS transistor of a peripheral circuit region,FIG. 43Ais a sectional view taken along the line A-A inFIG. 42A,FIG. 43Bis a sectional view taken along the line B-B inFIG. 42A,FIG. 43Cis a sectional view taken along the line C-C inFIG. 42A,FIG. 44Ais a sectional view taken along the line D-D inFIG. 42B, andFIG. 44Bis a sectional view taken along the line E-E inFIG. 42B. Those parts identical or similar to those of the first embodiment will be denoted by the same or similar reference numerals, and thus only characteristic portions of this embodiment will be described.

As shown inFIGS. 43A to 43C, in the memory cell region1, the first inter-electrode insulating film23is formed between the first gate electrode layer22and the second gate electrode layer24. However, as shown inFIGS. 43A to 43Cand44A to44B, in the select gate region2and the peripheral circuit region3a, the upper gate electrode layers46aand46bare directly formed on the lower gate electrode layers43aand43bthat include the first lower gate electrode layers41aand41bformed on the gate insulating films21band21cand having the same thickness as the first gate electrode layer22and the second lower gate electrode layers42aand42bformed on the first lower gate electrode layers41aand41b, such that the height of the upper gate electrode layers46aand46bare substantially the same as the height of the upper surface of the second gate electrode layer24of the memory cell region1. That is, in the select gate region2and the peripheral circuit region3a, the second inter-electrode insulating films44aand44bwhich are formed between the lower gate electrode layers43aand43band the upper gate electrode layers46aand46bare removed. Other structures are the same as those of the first embodiment.

Next, a fabrication method of the NAND-type nonvolatile memory will be described with reference toFIGS. 45A to 56B.

FIGS. 45A to 56Bare sectional views schematically showing the fabrication process steps of the NAND-type nonvolatile memory according to the fourth embodiment.FIGS. 45A to 45C,47A to47C,49A to49C,51A to SiC,53A to53C, and55A to55C are sectional views taken along the lines A-A, B-B, and C-C inFIG. 42A, respectively, andFIGS. 46A and 46B,48A and48B,50A and50B,52A and52B,54A and54B, and56A and56B are sectional views taken along the lines D-D and E-E inFIG. 42B, respectively. Those parts identical or similar to those of the first embodiment will be denoted by the same or similar reference numerals and thus detailed descriptions thereof will be omitted.

In a manner similar to the first embodiment, a series of process steps from the step of forming the gate insulating film21on the semiconductor substrate20to the step of forming the second gate electrode lower layer24aon the first and second inter-electrode insulating films23,44aand44bare performed. In this embodiment, however, the thickness of the second lower gate electrode layers42aand42bare 10 nm or more larger than the thicknesses of the second inter-electrode insulating films44aand44b.

As shown inFIGS. 45A to 45Cand46A to46B, on the first element isolation insulating film14a, the second element isolation insulating films14band14c, the first gate electrode layer22, and the second lower gate electrode layers42aand42b, the first and second inter-electrode insulating films23,44aand44bformed of, for example, an ONO film are formed to a thickness of about 12 nm to about 17 nm. Subsequently, on the first and second inter-electrode insulating films23,44aand44b, the second gate electrode lower layer24aformed of, for example, polycrystalline silicon and the first and upper gate electrode lower layers46a-1and46b-1are formed. In this case, the upper surface of the second gate electrode lower layer24aand the first and upper gate electrode lower layers46a-1and46b-1are formed so as to be about 10 nm to about 50 nm higher than the upper surfaces of the lower gate electrode layers43aand43b.

As shown inFIGS. 47A to 47Cand48A to48B, using the second element isolation insulating films14band14cas a stopper, a CMP process is performed to remove the second gate electrode lower layer24aand the second inter-electrode insulating films44aand44bformed on the upper surfaces of the second element isolation insulating films14band14cin the select gate region2and the peripheral circuit region3a, thereby exposing the upper surfaces of the lower gate electrode layers43aand43band the second element isolation insulating films14band14c. In this case, the first inter-electrode insulating film23of the memory cell region1shown inFIGS. 47A and 47Cis not removed because the second gate electrode lower layer24afunctions as a protective film. The upper surface of the second gate electrode lower layer24aof the memory cell region1is planarized.

As shown inFIGS. 49A to 49Cand50A to SOB, in order to remove a natural oxide film (not shown) formed on the surfaces of the lower gate electrode layers43aand43bexposed by the CMP process, a cleaning treatment is performed using a hydrofluoric acid-based solution such as a solution of hydrogen fluoride or fluorinated acid. In this case, as shown inFIGS. 49B and 50B, the upper portion of the surfaces of the second element isolation insulating films14band14cformed of SiO2, exposed by the CMP process are also removed by about 30 nm by the cleaning treatment using the hydrofluoric acid-based solution. However, the height of the upper surfaces of the element isolation insulating films14band14cfrom the upper surface of the semiconductor substrate20is at least 10 nm and is higher than the height of the upper surface of the semiconductor substrate20. The height of the upper surfaces of the second element isolation insulating films14band14cas observed from the upper surface of the semiconductor substrate20may be lower than the height of the upper surface of the first gate electrode layer22as long as it is higher than the height of the upper surface of the semiconductor substrate20.

As shown inFIGS. 51A to 51Cand52A to52B, on the surface of the second gate electrode lower layer24a, the surfaces of the lower gate electrode layers43aand43b, and the surfaces of the second element isolation insulating films14band14c, the second gate electrode upper layer24band the upper gate electrode layers46aand46bare formed to a thickness of about 80 nm to about 200 nm. Subsequently, on the second gate electrode upper layer24band the upper gate electrode layers46aand46b, the insulating film25formed of, for example, SiN is formed to a thickness of about 50 nm to about 150 nm.

As shown inFIGS. 53A to 53Cand54A to54B, the third mask material31formed of, for example, a silicon oxide film (SiO2) is formed on the insulating film25. Thereafter, the third mask material31is lithographically patterned. As shown inFIGS. 55A to 55Cand56A to56B, using the third mask material31as a mask, the insulating film25, the second gate electrode upper layer24b, the upper gate electrode layers46aand46b, the first inter-electrode insulating film23, the first gate electrode layer22, and the lower gate electrode layers43aand43bare removed by an anisotropic etching process, thereby forming the gate electrodes30,40,50of the memory cell transistors6, the select gate transistors7, and the MOS transistor8, respectively. Thereafter, using the gate electrodes30,40and50as a mask, the impurity diffusion layer regions26are formed by an ion implantation method. In some cases, the third mask material31may be completely removed by an anisotropic etching process subsequent to the anisotropic etching of the insulating film25when forming the gate electrodes30,40and50. The subsequent process steps are the same as those of the first embodiment and thus descriptions thereof will be omitted.

According to this embodiment, the lower gate electrode layers43aand43bof the select gate region2and the peripheral circuit region3aare constructed in a laminated structure in which the second lower gate electrode layers42aand42bare stacked on the first lower gate electrode layers41aand41bhaving the same thickness as the first gate electrode layer22of the memory cell region1. In addition, the height of the upper surfaces of the second element isolation insulating films14band14cas observed from the upper surface of the semiconductor substrate20is substantially the same as the height of the upper surfaces of the lower gate electrode layers43aand43b. Accordingly, it is possible to provide a NAND-type nonvolatile memory having the same advantages as provided by the first embodiment.

Since the second inter-electrode insulating films44aand44bbetween the lower gate electrode layers43aand43band the upper gate electrode layers46aand46bof the select gate transistors7and the MOS transistor8are completely removed, it is possible to decrease the resistance of the gate electrode layers. Accordingly, it is possible to increase the operating speed of the MOS transistor and to decrease the influence of the gate leakage on the potential drop.

Since it is not necessary to perform the lithography and patterning processes for forming the openings45aand45bof the second inter-electrode insulating films44aand44b, it is possible to decrease the number of process steps required.

It goes without saying that the resistor element and the capacitor element of the second and third embodiments may be applied to this embodiment.

Fifth Embodiment

A fifth embodiment is directed to, as similarly to the first embodiment, the NAND-type nonvolatile memory in which the width of the second lower gate electrode layer of the lower gate electrode layer is smaller than the width of the first lower gate electrode layer.

FIGS. 57A to 57B,58A to58D and59A to59B are views schematically showing the structure of a NAND-type nonvolatile memory according to the fifth embodiment, in whichFIG. 57Ais a top view of a memory cell region and a select gate region,FIG. 57Bis a top view showing the structure of a MOS transistor of a peripheral circuit region,FIG. 58Ais a sectional view taken along the line A-A inFIG. 57A,FIG. 58Bis a sectional view taken along the line B-B inFIG. 57A,FIG. 58Cis a sectional view taken along the line C-C inFIG. 57A,FIG. 58Dis a sectional view taken along the line D-D inFIG. 57A,FIG. 59Ais a sectional view taken along the line E-E inFIG. 57B, andFIG. 59Bis a sectional view taken along the line F-F inFIG. 57B. Those parts identical or similar to those of the first embodiment will be denoted by the same or similar reference numerals, and thus only characteristic portions of this embodiment will be described.

As shown inFIGS. 58A to 58Dand59A and59B, the lower gate electrode layers43aand43bof the select gate region2and the peripheral circuit region3ainclude the first lower gate electrode layers41aand41bhaving the same thickness as the first gate electrode layer22and second lower gate electrode layers52aand52bformed on the first lower gate electrode layers41aand41b. However, in this embodiment, the widths of the second lower gate electrode layers52aand52bare smaller than the widths of the first lower gate electrode layers41aand41b. In addition, second inter-electrode insulating films54aand54bare formed on the upper surfaces of the first lower gate electrode layers41aand41band on the side surfaces of the second lower gate electrode layers52aand52b, and openings55aand55bare formed on the upper surfaces of the second lower gate electrode layers52aand52b. Other structures are the same as those of the first embodiment.

Next, a fabrication method of the NAND-type nonvolatile memory will be described with reference toFIGS. 60A to 73B.

FIGS. 60A to 73Bare sectional views showing the fabrication process steps of the NAND-type nonvolatile memory according to the fifth embodiment.FIGS. 60A to 60D,62A to62D,64A to64D,66A to66D,68A to68D,70A to70D, and72A to72D are sectional views taken along the lines A-A, B-B, C-C, and D-D inFIG. 57A, respectively, andFIGS. 61A and 61B,63A and63B,65A and65B,67A and67B,69A and69B,71A and71B, and73A and73B are sectional views taken along the lines E-E and F-F inFIG. 57B, respectively. Those parts identical or similar to those of the first embodiment will be denoted by the same or similar reference numerals and thus detailed descriptions thereof will be omitted.

In a manner similar to the first embodiment, a series of process steps from the step of forming the gate insulating film21on the semiconductor substrate20to the step of forming the first mask material27on the first gate electrode layer22are performed. Thereafter, as shown inFIGS. 60A to 60Dand61A to61B, the first mask material27is lithographically patterned to form openings27aand27bthat expose predetermined areas of the first lower gate electrode layers41aand41b.

As shown inFIGS. 62A to 62Dand63A to63B, on the upper surfaces of the first lower gate electrode layers41aand41bexposed from the openings27aand27band on the first mask material27, second lower gate electrode layers52aand52bformed of, for example, polycrystalline silicon are formed. In this case, the upper surfaces of the second lower gate electrode layers52aand52bwithin the openings27aand27bare formed so as to be 20 nm or more higher than the upper surface of the first mask material27.

As shown inFIGS. 64A to 64Dand65A to65B, the second lower gate electrode layers52aand52bare polished by a CMP (Chemical Mechanical Polishing) process until the upper surface of the first mask material27is exposed. In this way, the second lower gate electrode layers52aand52bare formed in the select gate region2and the peripheral circuit region3a. At this time, as a result of over-etching, the second lower gate electrode layers52aand52bare also removed by about 5 nm to about 10 nm.

As shown inFIGS. 66A to 66Dand67A to67B, on the first mask material27and the second lower gate electrode layers52aand52b, a second mask material28formed of the same material as the first mask material27is formed to a thickness of about 40 nm. Subsequent process steps until the step of controlling the height of the upper surfaces of the first element isolation insulating film14aand the second element isolation insulating films14band14cas observed from the upper surface of the semiconductor substrate20so as to be higher than the height of the upper surfaces of the second lower gate electrode layers52aand52bare the same as those of the first embodiment, and thus descriptions thereof will be omitted.

As shown inFIGS. 68A to 68Dand69A to69B, in a state in which other areas outside the memory cell region1are masked with a photoresist29, the height of the upper surface of the first element isolation insulating film14ais made so as to be higher than the height of the upper surface of the semiconductor substrate20and lower than the height of the upper surface of the first gate electrode layer22, as shown inFIG. 68D. In this case, since the second element isolation insulating films14band14care covered with the photoresist29, their heights are not lowered.

As shown inFIGS. 70A to 70Dand71A to71B, after removing the photoresist29and the second mask material28, on the first element isolation insulating film14a, the second element isolation insulating films14band14c, the first gate electrode layer22, and the second lower gate electrode layers52aand52b, the first inter-electrode insulating film23formed of, for example, an ONO (Oxide-Nitride-Oxide) film is formed to a thickness of about 12 nm to about 17 nm. Subsequently, on the first inter-electrode insulating film23, the second gate electrode lower layer24aformed of, for example, polycrystalline silicon is formed. In this case, the upper surface of the second gate electrode lower layer24ais formed so as to be about 10 nm to about 50 nm higher than the upper surfaces of the lower gate electrode layers53aand53b.

As shown inFIGS. 72A to 72Dand73A to73B, using the second element isolation insulating films14band14cas a stopper, the second gate electrode lower layer24aand the second inter-electrode insulating films44aand44bformed on the upper surfaces of the second element isolation insulating films14band14cof the select gate region2and the peripheral circuit region3aare removed by a CMP process to expose the upper surfaces of the second element isolation insulating films14band14cand the second lower gate electrode layers52aand52b. In this case, the first inter-electrode insulating film23of the memory cell region1shown inFIGS. 72A and 72Cis not removed because the second gate electrode lower layer24afunctions as a protective film. The upper surface of the second gate electrode lower layer24aother than the second lower gate electrode layers42aand42b1is planarized. Subsequent process steps are the same as those of the first embodiment, and thus descriptions thereof will be omitted.

In this embodiment, it is possible to provide a NAND-type nonvolatile memory having the same advantages as provided by the first embodiment.

In the etching of the second inter-electrode insulating films54aand54bduring processing of the gate electrodes, since it is not necessary to etch the steps of the second inter-electrode insulating films54aand54b, it is possible to prevent etching residues of the second inter-electrode insulating films54aand54b.

It goes without saying that the resistor element and the capacitor element of the second and third embodiments may be applied to this embodiment.

In the select gate transistors7, the widths of the second lower gate electrode layers52aand52bmay be the same as the widths of the first lower gate electrode layers41aand41b. Moreover, in the MOS transistor, the resistor element, or the capacitor element of the peripheral circuit region, the widths of the second lower gate electrode layers52aand52bmay be smaller than the widths of the first lower gate electrode layers41aand41b.

Sixth Embodiment

A sixth embodiment is directed to a NAND-type nonvolatile memory in which two MOS transistors are provided in different peripheral circuit regions, the respective gate insulating films of the MOS transistors being of different thicknesses.

FIGS. 74A and 74Bare views schematically showing the structure of a MOS transistor of two different peripheral circuit regions of the NAND-type nonvolatile memory according to a sixth embodiment, in whichFIG. 74Ais a top view showing the structure of the MOS transistor, andFIG. 74Bis a sectional view taken along the line A-A inFIG. 74A. Those parts identical or similar to those of the first embodiment will be denoted by the same or similar reference numerals, and thus only characteristic portions of this embodiment will be described.

As shown inFIG. 74A, a low-voltage MOS (LV-MOS) transistor121is formed in a first peripheral circuit region3d, and a high-voltage MOS (HV-MOS) transistor122is formed in a second peripheral circuit region3e. The gate insulating film21dof the LV-MOS transistor121is formed to a thickness of about 50 Å to about 100 Å, which is the same as the gate insulating films21aand21bof the memory cell region1and the select gate region3a. Meanwhile, the gate insulating film21eof the HV-MOS transistor122is formed to a thickness of about 350 Å to about 450 Å, which is larger than that of the gate insulating film21dof the LV-MOS transistor121. Other structures are the same as those of the first embodiment.

Next, a fabrication method of the LV and HV MOS transistors in which the thickness of the gate insulating film is different will be described with reference toFIG. 75.

FIGS. 75A to 75Care sectional views schematically showing the fabrication process steps of the LV- and HV-MOS transistors of the NAND-type nonvolatile memory according to this embodiment, taken along the line A-A inFIG. 74A. Those parts identical or similar to those of the first embodiment will be denoted by the same or similar reference numerals, and thus descriptions thereof will be omitted.

As shown inFIG. 75A, on the semiconductor substrate (for example, a silicon substrate)20, the gate insulating film21eformed of, for example, SiO2is formed to a thickness of about 300 Å to about 400 Å through a process such as thermal oxidation.

As shown inFIG. 75B, in a state in which the gate insulating film21eof the peripheral circuit region3efor forming the HV-MOS transistor122is covered with a photoresist (not shown), the gate insulating film21eof the peripheral circuit region3dfor forming the LV-MOS transistor121is etched and removed. Thereafter, the photoresist is removed.

As shown inFIG. 75C, on the semiconductor substrate20of the peripheral circuit region3dfor forming the LV-MOS transistor121, the gate insulating film21dis formed to a thickness of about 50 Å to about 100 Å through a process such as thermal oxidation. At this time, since the peripheral circuit region3efor forming the HV-MOS transistor122is also thermally oxidized, the thickness of the gate insulating film21eof the peripheral circuit region3efor forming the HV-MOS transistor122becomes about 350 Å to about 450 Å. The above-described process steps may be repeated when it is desired to form three or more different gate insulating films.

Subsequent process steps are the same as those of the first embodiment, and thus descriptions thereof will be omitted.

The height of the upper surface of the second lower gate electrode layer42bof the HV-MOS transistor122as observed from the upper surface of the semiconductor substrate20is higher than the height of the upper surface of the second lower gate electrode layer42bof the LV-MOS transistor121as observed from the upper surface of the semiconductor substrate20. Therefore, it is preferable to control the upper surface of the second element isolation insulating film14cof the LV-MOS transistor121to be aligned with the upper surface of the second lower gate electrode layer42bof the HV-MOS transistor122.

This embodiment can provide the same advantages as provided by the first embodiment. It goes without saying that the resistor element of the second embodiment or the capacitor element of the third embodiment may be applied to this embodiment.

The peripheral circuit region3dfor forming the LV-MOS transistor and the peripheral circuit region3efor forming the HV-MOS transistor may be provided in a single active area, and additionally, a plurality of MOS transistors may be provided in the single active area.

The thickness of the gate insulating film of the memory cell transistors6may be different from the thickness of the gate insulating film of the select gate transistors7.

The upper surface of the second element isolation insulating film14cof the HV-MOS transistor may be aligned with the upper surface of the second lower gate electrode layer42bof the LV-MOS transistor.

The second lower gate electrode layer may be formed in only one of the HV-MOS transistor and the LV-MOS transistor, and alternatively, the second lower gate electrode layer may be formed only in the select gate transistors.

Seventh Embodiment

A seventh embodiment is directed to the case in which the present invention is applied to a NOR-type nonvolatile memory.

FIGS. 76A to 76Dare views schematically showing the structure of a memory cell region of the NOR-type nonvolatile memory according to the seventh embodiment, in whichFIG. 76Ais a top view of the memory cell,FIG. 76Bis a top view showing the structure of a MOS transistor of a peripheral circuit region,FIG. 76Cis a sectional view taken along the line A-A inFIG. 76A, andFIG. 76Dis a sectional view taken along the line B-B inFIG. 76B. Those parts identical or similar to those of the first embodiment will be denoted by the same or similar reference numerals and thus detailed descriptions thereof will be omitted.

As shown inFIG. 76A, in the memory cell region1, a plurality of lines of word lines W1, W2, . . . , and W4is parallely arranged in stripes along the X direction in the drawing, and a plurality of lines of active areas4mserving as an element forming region is parallely arranged along the Y direction in the drawing with an element isolation insulating film14interposed between adjacent lines. The active areas4mare combine with each other at an area between the word line W2and the word line W3; the area where the active areas4mcombine with each other is referred to as a source region126. At each intersection of the active areas4mand the word lines W1, W2, . . . , and W4, perpendicular to the Y direction, a memory cell transistor136is formed. Between the word lines W1and W2, and between the word lines W3and W4, contacts135that connect the memory cell transistors136to bit lines (not shown) are disposed.

Although this embodiment describes and illustrates four word lines, a larger number of word lines, for example, 16, 32, or more may be provided. Similarly, the number of active areas4mmay be larger than two.

As shown inFIGS. 76B and 76C, the structure of the MOS transistor8of a peripheral circuit region3fis the same as that of the MOS transistor of the peripheral circuit region of the NAND-type nonvolatile memory according to the first embodiment, and thus descriptions thereof will be omitted.

As shown inFIGS. 76C and 76D, the memory cell transistor136of the NOR-type nonvolatile memory is constructed in a double-layer gate structure in the same manner as the memory cell transistor6of the NAND-type nonvolatile memory of the first embodiment. Meanwhile, the MOS transistor of the peripheral circuit region3fis constructed in a single-layer gate structure in the same manner as the MOS transistor8of the peripheral circuit region3aof the first embodiment.

According to the embodiment, the present invention may be applied to the NOR-type nonvolatile memory as well as the NAND-type nonvolatile memory. Similarly, the present invention may be applied to nonvolatile memories of various types such as AND or DiNOR.

It goes without saying that the resistor element of the second embodiment and the capacitor element of the second third embodiments may be applied to this embodiment.

According to an aspect of the present invention, it is possible to prevent the element isolation insulating film from being lower than the surface of the semiconductor substrate and to thus prevent short-circuiting of the gate electrode and the semiconductor substrate when removing the natural oxide film on the exposed surface of the lower gate electrode layer or when removing the floating gate electrode layer.