Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer

Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a serializer-deserializer in conjunction with a second XOR decompressor in a second stage.

TECHNICAL FIELD

The present application relates to systems and methods for generating test patterns to be used in testing integrated circuit designs.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 14/754,386, entitled “Method and System for Improving Efficiency of Sequential Test Compression Using Overscan,” U.S. patent application Ser. No. 14/737,331, entitled “Elastic Compression—Optimizing Tester Bandwidth with Compressed Test Stimuli Using Overscan and Variable Serialization,” and U.S. patent application Ser. No. 14/754,403, entitled “Method for Construction of a Highly Efficient and Predictable Sequential Test Decompression Logic”.

BACKGROUND

Automatic test pattern generation (“ATPG”) was developed to explicitly test each gate and path in an integrated circuit (“IC”) design. As ICs have become larger and more complex, the amount of logic to be tested per input/output test pin has increased dramatically, increasing test time and cost.

When an ATPG tool generates a scan test for a fault, or a set of faults, only a small percentage of scan cells in the scan channel need to take specific values (e.g., care bits). The rest of the cells in the scan channel are “don't care”, and are usually filled with random values. Relatively few bits in an ATPG generated test pattern are “care” bits.

Test Compression takes advantage of the small number of significant values (care bits) to reduce test data and test time. However, as Test Compression decreases channel lengths, the number of specified bits (e.g., care bits) per time slice increases. An ATPG process for a certain test pattern may specify certain bits (e.g., care bits) across multiple time slices of the test pattern in order to reduce toggling, and, therefore, power consumption. There can be a large variance in the number of care bits across time slices.

For a spreader network of a plurality of XOR logic gates (e.g., XOR decompressor), the maximum number of care bits that can be solved for each scan cycle is limited by the total number of scan inputs. Therefore, XOR decompressors cannot solve for slices that have more care bits than the available scan data (e.g., input variables). Further, XOR decompressors are also limited in that they are restricted to using only the scan data available in the same scan cycle.

Accordingly, there is a need for generating “extra” variables in the event the ATPG is presented with faults that require a much higher number of care-bits than can be supported efficiently by the current hardware (e.g., XOR decompressors).

DESCRIPTION OF EMBODIMENTS

One aspect of the present disclosure is to provide systems and methods for generating “extra” variables during the ATPG process in the event the ATPG is presented with faults that require a much higher number of care-bits than can be supported efficiently by the current test decompression hardware. The methods and apparatuses herein address at least one of the ATPG problems described above. Accordingly, a multi-stage decompressor network system with a serializer-deserializer (“SerDes”) is provided.

According to an embodiment, an automatic test pattern generation system includes: a controller, configured to receive m scan inputs from a tester, and providing a first control signal; an i-bit serializer-deserializer; a decompressor network, configured to receive the m scan inputs from the tester, the decompressor network comprising first and second parts, the first part of the decompressor network including a first spreading network of XOR logic gates configured to receive the m scan inputs from the tester and output 2m-1outputs, the second part of the decompressor network including a broadcast network configured to receive each of the m scan inputs from the tester and output each of the m scan inputs to the corresponding i-bit serializer-deserializer, wherein i is an integer greater than 1; a second spreading network of XOR logic gates receiving an output of the i-bit serializer-deserializer; and a multiplexer stage including at least one multiplexer, the at least one multiplexer having a first multiplexer input configured to receive at least one of the outputs of the first spreading network, a second multiplexer input configured to receive an output from the second spreading network, and a third multiplexer input configured to receive the first control signal, wherein, based on the first control signal, the multiplexer selects one of the first and second multiplexer inputs to output to a plurality of scan channels.

Aspects of the invention include a method performing the functions as just described.

FIG. 1illustrates elements of a system100utilized during ATPG. System100, utilizing scan cube101(which includes one of many scan slices101a), includes scan-in pins102, decompressor103, producing test cube104(which includes a test slice104aamong a plurality of test slices, as well as care bits104b, and an indication104cof a faulty AND gate). In an embodiment, scan cube101is the generated test pattern that will be applied to a circuit design in order to identify potential defects. Accordingly, in an embodiment, scan slice101awill be applied to flip-flops associated with the location of scan slice101aduring the test of the digital circuit. In an embodiment, during the automatic test pattern generation process, care bits104bare placed throughout the test slices104of the scan channels of test cube104in order to test for faults. For example, in order to properly detect fault104c, care bit104b(as well as other care bits indicated by a binary value of either 1 or 0) are required to be placed in specified locations in the scan channels as illustrated inFIG. 1. In an embodiment, the fault to be tested for in the digital circuit is an AND gate104cwhich is stuck-at 1 (e.g., an individual pin is stuck at a logical ‘1’). Further, as depicted inFIG. 1, the compression ratio of decompressor103refers to the ratio of the number of the channels N to the number of the scan-in pins M.

In an embodiment, each scan cycle with care bits is solved one at a time from the earliest scan cycle with care bits (e.g., closer to the bottom of the test cube104) to the last scan cycle with care bits (e.g., closer to the bottom of the decompressor103), so that the ATPG process focuses on solving just the scan cycle of interest. Specifically, the equation solver solves for the variables (e.g., scan-in pin102inputs) necessary to generate the desired care bits (e.g.,104b) at each scan slice of the scan channels. Each channel input of the scan slice generally corresponds to a different Boolean combination (e.g., due to the decompressor103) of the input bit variables (e.g., scan-in pin102inputs). Accordingly, each scan slice corresponds to a plurality of linear equations (e.g., ax=b). With the Boolean combinations provided by the decompressor103(e.g., the “a”) and the corresponding care bit values (e.g., the “b”) for each of the scan channels of the scan cycle, the equation solver can solve for the desired scan input variables (e.g., the “x”). After the equation solver determines the desired scan input variables, the variables are extracted to a corresponding location in the scan pattern.

FIG. 2is a graph depicting the total number of care bits that can be solved for, per scan slice, with a standard XOR decompressor. For example, assuming 8 scan-in inputs, the XOR decompressor would shift in 8 variables every scan cycle (see curve202). Accordingly, the equation solver can solve a maximum of 8 care bits per scan slice (e.g., 3 care bits or less is usually guaranteed). Thus, as depicted inFIG. 2, many scan slices with care bits exceeding 8 will not be solved (see curve201). Specifically, with the XOR decompressor, many of the 154 care bits in the test pattern will not be solved. Further, as depicted inFIG. 2, the test data volume (e.g., the product of the number of scan-in inputs M and the scan length L) of the compressed test pattern stored on the tester is 160 bits (e.g., area under curve202).

FIG. 3illustrates the elements of a multi-stage decompressor network system including a serializer-deserializer. In an embodiment, system300includes M scan-in pins301(e.g., to receive inputs from the tester), decompressor network302, controller303, SerDes304, XOR decompressor305(e.g., a spreading network of XOR logic gates), clock gate306, multiplexer stage307and scan channels308. In an embodiment, decompressor network302includes an XOR decompressor (e.g., a spreading network of XOR logic gates). In an embodiment, the traditional decompressor outputs 2(M-1)decompressed outputs from the M scan-in inputs. In another embodiment, decompressor network302also includes a broadcast mode, in which the decompressor network302directly connects each of the M scan-in inputs to a corresponding i-bit (e.g., 2 or 3-bit) SerDes304. In an embodiment, the output of the i-bit SerDes304feeds an XOR decompressor305. In an embodiment, a multiplexer (“MUX”) stage307allows the scan channels308to be fed by either the XOR decompressor of decompressor network302(e.g., the first stage) or XOR decompressor305(e.g., the second stage). In an embodiment, a multiplexer of MUX stage307receives at a first input, the output of the XOR decompressor of decompressor network302and, at a second input, the output of the XOR decompressor305. Specifically, depending on a signal input (e.g., signal303aof controller303) on a third input of the multiplexer (e.g., the select line), the scan channels308are fed by either the XOR decompressor of decompressor network302or XOR decompressor305. For example, if the ATPG process runs into a group of linear of equations for a certain scan slice that cannot be solved (e.g., because of correlation of certain channels), the ATPG process would switch to the second stage of the system (e.g., SerDes304w/ XOR decompressor305) to directly load the channels. Otherwise, the ATPG process would normally operate with the first stage of the system (e.g., the XOR decompressor of decompressor network302). In an embodiment, the ATPG process would utilize the second stage of the system after the equation solver initially solves for all of the other solvable scan slices of the scan channels308. In an embodiment, the ATPG process determines if a system of equations is unsolvable for a certain scan slice. In an embodiment, after (i) the equation solver solves for all of the solvable scan slices and (ii) it is determined by the equation solver that certain scan slices are unsolvable, the tester (not shown) transmits a signal (e.g.,0000,0000) to controller303to initiate the second stage of the system. In an embodiment, in response to the signal to initiate the second stage of the system, the controller303transmits (i) signal303ato the MUX stage307and (ii) signal303bto clock gate306(e.g., clock gate connected to the clocks of all of the flip-flops in the scan chains308). If signal303ais high, the MUX stage307will only allow the scan channels308to be fed by XOR decompressor305. In an embodiment, when the scan channels308are only fed by XOR decompressor305(e.g., the second stage), the equation solver is provided with more variables (e.g., the product of the number of scan-in inputs and the value of i for the i-bit SerDes) to utilize in the system of equations for the particular scan slice. On the other hand, if signal303ais low, MUX stage307will only allow the scan channels308to be fed by the XOR decompressor of decompressor network302(e.g., the first stage). In an embodiment, if signal303bis high, scan channels308will continue to shift down values. Otherwise, if signal303bis low, the clocks to scan channels308will freeze and, thus, no values will shift down scan channels308. In an embodiment, the clocks to the flip-flops of the scan chains are frozen in order for the SerDes to initialize each value in the i-bit shift register of the SerDes. In an embodiment, the SerDes can dynamically alter the value of the i for the i-bit shift register depending on the number of care bits required for the particular scan slice. In another embodiment, either the XOR decompressor of decompressor network302or the XOR decompressor305can include a hierarchical XOR gate structure. In an embodiment, an extractor (not shown) (i) extracts the solution (e.g., the required spread of input variables to detect the desired care bits) after the system of equations corresponding to the certain scan slice is solved and (ii) transmits the solution to a corresponding scan cycle location in a test pattern stored in a database. In an embodiment, during the second stage, once the system of equations corresponding to the certain scan slice is solved, the appropriate variables (e.g., the required spread of input variables to detect the desired care bits) are parsed out and extracted to a corresponding scan cycle location in a test pattern stored in a database.

FIG. 4is a graph depicting the total number of care bits that can be solved for, per scan slice, with a multi-stage decompressor network system including the SerDes. For example, assuming 8 scan-in inputs and a SerDes width of 3 (or a 3-bit SerDes), the combination of a XOR decompressor and the SerDes would shift in 24 bits per scan slice (e.g., the product of number of scan-in inputs and the SerDes width). Accordingly, the equation solver can now solve up to 24 care bits per scan slice. Thus, as depicted inFIG. 4, many of the 154 care bits in the test pattern will now be solved (see curve401). Further, as depicted inFIG. 4, the data volume (e.g., area under curve402) of the XOR decompressor and the SerDes is 254 bits (e.g., (8×14)+24×6).

The description of the foregoing embodiments may refer to algorithms, sequences, macros, and operations that require processor execution of instructions stored in memory. The processor may be specific to an apparatus, such as automated test equipment (ATE). The processing device executes, or selectively activates in order to execute, a computer program. The computer program is stored in memory associated with the apparatus. Memory available on the apparatus may include a computer readable storage medium, which is not limited to, but may include, any type of disk, including floppy disks, optical disks, CD-ROMs, magnetic-optical disks, and other memory such as read-only memory (ROMs), random access memory (RAMs), electrically erasable programmable read-only memory (EEPROM), flash memory, and yet other storage such as magnetic or optical cards, or any type of media that stores program instructions. Each of the memory devices implemented in the apparatus is further connected to or coupled to a system bus or a network connection, wired or unwired, capable of facilitating or driving communications.

Moreover, it will be apparent to those skilled in the art from consideration of the specification and practice of the present disclosure that various modifications and variations can be made to the disclosed systems and methods without departing from the scope of the disclosure, as claimed. Thus, it is intended that the specification and examples be considered as exemplary only, with a true scope of the present disclosure being indicated by the following claims and their equivalents.