Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same

Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.

BACKGROUND

1. Technical Field

This invention relates in to a field effect device having a channel of carbon nanofabric, a static random access memory (SRAM) made of such, and a method of making the same.

2. Discussion of Related Art

SRAM, both stand alone and embedded, requires increasingly dense cells with every technology generation, increased performance, and lower leakage currents. Six transistor SRAM cells may be designed for very low power operation including very low leakage currents. Six transistor SRAM cells may also be designed for high performance applications, such as cache memory, with higher leakage tolerance, but still requiring low leakage currents.

Six transistor SRAM cells comprise two NFET cell access transistors, as well as two NFET pull-down devices and two PFET pull-up (load) devices, all co-planar, and cross coupled to form a flip flop storage cell as is well known in the semiconductor industry. Stacking of load devices can reduce SRAM cell size (area) by 30 to 50%. Stacking of load devices has been used in earlier generations of SRAMs for density enhancement. For example, stacking of SRAM cell load devices using polysilicon resistors has been used to shrink cell size. However, stacked poly load resistors are no longer used in new SRAM products because of high leakage currents due to poor scalability, and because polyresistors always conduct current. Stacked thin film PFET devices were also tried in earlier SRAM generations, however, such stacked thin film PFETs are no longer used due to high leakage currents and poor scalability.

FIG. 1illustrates a schematic of a prior art coplanar six device SRAM memory cell100, including storage cell110and connections to word line WL, bit lit BL, and complimentary bit line Blb (bit line-bar). Inverter120comprising NFET pull-down device T2and PFET pull-up (load) device T3, and inverter130comprising NFET pull-down devices T4and P-FET pull-up device T5are interconnected in the conventional manner (“cross coupled”) to form a flip flop storage cell. Transfer devices T1and T6connect are connected to both inverters120and130to form memory cell110, and also connected to array lines WL, BL and BLb, in the conventional manner. Basic SRAM cell and chip operation is described in K. Itoh, “VLSI Memory Chip Design,” Springer Publishing, 2001, pp. 26-31.

SUMMARY

The invention provides hybrid carbon nanotube FET(CNFET)-FET Static RAM (SRAM) and method of making same.

Under one aspect of the invention, a static ram memory cell includes two semiconductor-type field effect transistors (FETs), and two nanotube FETs (NTFETs). Each FET has a semiconductor drain region and a semiconductor source region of a first type of semiconductor material, and each FET having a semiconductor channel region positioned between respective drain and source regions. The channel region are made of a second type of semiconductor material; each FET further has a gate node in proximity to a respective channel region so as to be able to modulate the conductivity of the channel by electrically stimulating the gate. The two semiconductor-type FETs are cross-coupled so that gate of one FET connects to the drain or source of the other. Each NTFET has a channel region made of at least one semiconductive nanotube, connected to a respective source and drain region of a corresponding NTFET. A first NTFET is connected to the drain or source of the first semiconductor-type FET and the second NTFET is connected to the drain or source of the second semiconductor-type FET.

Under another aspect of the invention, the two semiconductor-type FETs are formed in a substrate, and the two NTFETs are positioned above the two semiconductor-type FETs.

Under another aspect of the invention, the NTFETs are vertically aligned with a corresponding semiconductor-type FET.

Under another aspect of the invention, the semiconductor-type FETs is an N-type FET and the channel of the NTFET is formed of p-type nanotubes.

Under another aspect of the invention, the semiconductor-type FETs is an N-type FET and the channel of the NTFET is formed of ambipolar-type nanotubes.

Under another aspect of the invention, NTFETs also include a back control gate.

Under another aspect of the invention, an intermediate SRAM structure includes an organized and structured arrangement of SRAM cells. Each SRAM cell has two semiconductor-type field effect transistors (FETs). Each FET has a semiconductor drain region and a semiconductor source region of a first type of semiconductor material, and each FET has a semiconductor channel region positioned between respective drain and source regions. The channel region is made of a second type of semiconductor material. Each FET further has a gate node in proximity to a respective channel region so as to be able to modulate the conductivity of the channel by electrically stimulating the gate, wherein the two semiconductor-type FETs are cross-coupled so that gate of one FET connects to the drain or source of the other. The cells also include two nanotube FETs (NTFETs), each having a channel region made of nanotubes including nanotubes of semiconductive and metallic type, connected to a respective source and drain region of a corresponding NTFET. A first NTFET is connected to the drain or source of the first semiconductor-type FET and the second NTFET is connected to the drain or source of the second semiconductor-type FET. The intermediate SRAM structure further includes burn-off circuitry to electrically stimulate the channel regions of the NTFETs to fail nanotubes of metallic type while leaving at least one nanotube of semiconductor type.

Under another aspect of the invention, a method of electrically connecting two conductive or semiconductive entities vertically displaced relative to each other includes forming a void to create a pathway between the two entities, in which an upper opening of the void is in proximity to the first entity and a bottom of the void abuts the second entity. A conformal fabric of nanotubes is deposited to adhere to a top surface next to the upper opening of the void to contact the first entity, and to adhere conformally to the vertical surface of the void, and to adhere to the bottom surface of the void to contact the second entity.

DETAILED DESCRIPTION

Stackable, scalable, low leakage SRAM cell load devices are needed for new SRAM generations. Carbon nanotube FET (CNFET) transistors, more specifically, P-Type CNFET transistors (P-CNFETs) make excellent stackable load devices. P-CNFETs do not require a silicon substrate, are scalable, and have very low leakage currents. Research has demonstrated that a single (one) SWNT fiber spanning the distance between source and drain device regions exhibits 10× greater mobility than a PFET device, is scalable to sub-20 nm source-to-drain channel lengths, and has low OFF state leakage current. See Durkorp et al., “Extraordinary Mobility in Semiconducting Carbon Nanotubes,” Nano Lett. 2004, Vol. 4 No. 135-39. In spite of high single SWNT fiber current density carrying capability, replacing PFET load devices requires multiple SWNTs spanning the distance between source and drain regions to carry the total ON state load current. Also, these multiple SWNT P-CNFET devices must be made compatible and integrated with CMOS technology used in SRAM fabrication. This includes multiple SWNT deposition, patterning at desired locations, and interconnecting with NFET devices in the SRAM cell. Since SWNTs may be semiconducting or metallic, under certain embodiments metallic SWNTs in the P-CNFET channel region spanning the distance between source and drain must be burned-off. Finally, the electrical characteristics of the CNFET devices must be optimized for operation in the voltage range required for product design.

Preferred embodiments of the present invention provide fabrication solutions and corresponding structures for the controlled placement, patterning, and integration of stacked P-CNFET devices with CMOS technology to enable the design of scalable, dense, high performance and very low power hybrid CNFET-FET SRAM memory products. Preferred embodiments of the present invention provide P-CNFETs with multiple SWNTs spanning the distance between source and drain to form the channel region of the P-CNFETs. Preferred embodiments of the present invention optimize the electrical characteristics of these P-CNFETs for high performance and low leakage. Preferred embodiments of the present invention provide a means of burning-off metallic SWNTs in the P-CNFET channel region such that only semiconducting SWNTs spanning the region between source and drain remain in the channel region. Preferred embodiments of the present invention optimize the electrical characteristics of the combined P-CNFET and FET devices and ensure operation in the voltage range required SRAM memory products, both stand alone and embedded.

Overview of SRAM Memory Cells

FIG. 2Aillustrates a schematic of memory cell200, including storage cell210with stacked P-CNFET load devices and connections to array lines WL, BL, and BLb. Inverter215in storage cell210replaces coplanar PFET load device T3with stacked P-CNFET device T3SB. Inverter220in storage cell210replaces coplanar PFET load device T5with stacked P-CNFET load device T5SB. Connections between inverters215and220with transfer devices T1and T6, NFET pull-down devices T2and T4, and array lines WL, BL, BLb remain the same. P-CNFET load devices T3SB and T5SB each have a back (bottom) gate225that electrostatically couples to the SWNTs spanning the distance between device source and drain electrodes. Back (bottom) gates225are connected by connection230to back bias connection235, which is connected to voltage source VBB. The gate of transistor T3SB is connected to node245by connection240, which may be a NT fabric (nanofabric) connection, as explained further below. The gate of transistor T5SB is connected to node255by connection250, which may be a nanofabric connection as explained further below.

FIG. 2Billustrates a schematic of memory cell252, including storage cell260with stacked P-CNFET load devices and connections to array lines WL, BL, and BLb. Inverter270in storage cell260replaces coplanar PFET load device T3with stacked P-CNFET device T3S. Inverter275in storage cell260replaces coplanar PFET load device T5with stacked P-CNFET load device T5S. Connections between inverters270and275with transfer devices T1and T6, NFET pull-down devices T2and array lines WL, BL, BLb remain the same. P-CNFET load devices T3S and T5S do not have a back (bottom) gate225that electrostatically couples to the SWNTs spanning the distance between device source and drain electrodes, therefore the electrical characteristics of P-CNFET devices T3S and T5S are determined by chemical means (doping, annealing, and other methods). Further description of memory cell252is found further below. The gate of transistor T3S is connected to node285by connection280, which may be a NT fabric(nanofabric) connection, as explained further below. The gate of transistor T5S is connected to node295by connection290, which may be a nanofabric connection as explained further below.

Prior Art Single-Gate and Dual-Gate FET Device Operation and Characteristics

Historically, the electrical properties of FETs, NFETs and PFETs, have been controlled by chemical means only (doping concentrations, annealing steps, and other means), or by chemical and electrostatic means, using charge coupling between the semiconductor substrate and the FET device channel region, to set threshold voltage and optimize device electrical (I-V) characteristics. Similarly, the electrical properties of CNFETs, including P-CNFETs, can also be controlled by chemical means, or by chemical and electrostatic means. Illustrations of P-CNFET devices and structures accommodating both chemical and electrostatic means of optimizing electrical characteristics are illustrated further below. Illustrations of P-CNFET devices and structures with electrical characteristics optimized by chemical means only are also illustrated below. In all cases, burn-off means are incorporated in the device structure to eliminate metallic SWNTs in the P-CNFET device channel region between source and drain as illustrated further below.

In the mid to late 1960's, PMOS-based products with non-self-aligned aluminum gates became available. PMOS had the advantage that when fabricated the devices were in the normally OFF state, with no channel between the P+ source—drain regions. PMOS devices had negative threshold voltages and operated between ground and minus VDD(−VDD). Threshold voltages were high, −5 volts for example, and VDDapplied voltages were in the −12 to −20 V range. Also, the mobility was 2.5 to 3× lower than NMOS mobility. Threshold voltages were reduced with PMOS device scaling. The difference in mobility between PMOS and NMOS devices remain due to the relative mobility of p-type and n-type carriers in the FET channel region. Prior art PMOS device300is illustrated inFIG. 3A. Device300is an example of a PMOS device having an N substrate308(or N well) a depletion region310, source302, gate304and drain306. FIG.3A1is a typical Early NMOS device characteristic I-V curve.

There was strong interest in using N-type FETs because of much lower NMOS channel resistance for the same geometries due to the superior electron mobility, 2.5 to 3× higher than PFET hole mobility. Bipolar circuits (TTL) were operating at positive 5 volts power supply so there was strong interest in FET products operating with positive 5 volt power supply for ease of mixing new FET-based products with the existing bipolar technology. A major problem was that NMOS devices were in the ON state as fabricated. Positive ions both fixed and mobile, combined with the work function of the aluminum gate and p-substrate doping, plus defects in the Si/SiO2interface made it impossible to find a fabrication-only solution to the fabricated normally-ON NMOS problem (it took well over 10 years to find a fabrication-only solution). Products designers needed a way to use normally-ON NMOS FETs or remain with an inferior P-type FET technology. The NFET problem of these prior art devices is described in the text book by J. Millman & C. Halkias, “Integrated Electronics: Analog and Digital Circuits and Systems,” McGraw-Hill Book Company, 1972, pages 322-328.

Prior artFIG. 4Aillustrates an early NMOS structure400having a P substrate408(or P well) a depletion region410, source402, gate404, drain406and inverted channel412. Prior artFIG. 4Ashows the cross section of early NMOS devices normally ON as fabricated and associated I-V characteristics in FIG.4A1, with the NMOS having a negative threshold voltage. Prior artFIG. 4Billustrates an early NMOS structure414having a P substrate408, an N channel418and a depletion region416. Prior artFIG. 4Bcross section and associated FIG.4B1show the operation of the device using a signal VSIG applied between source S and gate G. (Undesirable operating range409is as shown in FIG.4B1) The gate to source voltage must be negative to modulate the channel region by creating a depletion region between the channel and the surface (Si—SiO2interface). This method of operation could not meet the requirement of operating voltages in the zero to VDDrange, with a positive threshold voltage.FIG. 4Cillustrates prior art structure420having a P substrate408, depletion region416and N Channel422. Prior artFIG. 4Ccross section and associated FIG.4C1I-V characteristics shows the effect of introducing a substrate bias voltage VBIASthat is used to electrostatically alter the electrical properties of the channel region422. Using the substrate as common back-gate biased negative with respect to NFET source diffusions, the normally-ON FET channel resulting from process-only fabrication techniques was turned OFF and NFET threshold voltage was set using electrostatic coupling in the depletion region between the substrate region and the channel region. The electrical I-V characteristic of FIG.4B1was translated to the electrical characteristic shown in FIG.4C1using VBIAS(desirable operating region424as illustrated). The NFET gate404voltage operating range for NFET product design was in the 0 to 5 volt range (5 volt power supply compatible), achieved using a combination of process (chemical) means and electrostatic (electrical) means as illustrated in prior artFIG. 4C.

While illustrated using NFET device characteristics, electrostatic channel region control applies to both NFET and PFET device types. These same principles are applied to P-CNFETs in this invention.

Integrating SWNTs and CMOS Processes

FIG. 5describes a basic method500of fabricating preferred embodiments of the invention. The following paragraphs describe methods with respect to fabricating certain exemplary carbon nanotube FET (CNFET) device structures where semiconducting SWNTs form a channel region for CNFET devices, replacing silicon substrates used for conventional FET devices.

In general, preferred methods form 510 pre-nanotube integration structures created using known techniques and thus is not described here. Under preferred embodiments, pre-NT integration structures contain all CMOS devices, including NFET memory cell devices, and a subset of local interconnections required to build an SRAM product as illustrated further below. A surface layer is prepared for deposition of a non-woven matted carbon nanotubes referred to as a nanofabric layer as illustrated further below. The surface layer planarity is not critical because the nanofabric layer is conformal.

Next, preferred methods520form a layer (monolayer) of matted carbon nanotubes600illustrated inFIG. 6Areferred to as a nanofabric layer. This may be done with spin-on technique or other appropriate technique as described in U.S. Pat. Nos. 6,574,130, 6,643,165, 6,706,402, 6,784,028, 6,835,591, 6,911,682, 6,919,592, 6,924,538 and 6,942,921; and U.S. patent application Ser. Nos. 10/341,005, 10/341,054, 10/341,055, 10/341,130, 10/774,682, 10/776,059, 10/860,334, 10/860,433, 10/864,186, 11/007,752, 11/010,491 and 11/304,315, the contents of which are hereby incorporated by reference in their entireties (hereinafter and hereinbefore, the “incorporated patent references”).FIG. 6Aillustrates a single layer of spun-on nanotubes.

Multiple layers of nanotubes may be spun-on. Nanofabric layer thickness is typically in the range of 0.5 to 5 nm for SWNT layers, and 5 to 20 nm thick for MWNT layers. The resistivity of the spun-on nanotubes may be controlled in the range of 500 to 10,000 ohms per square, for example, as measured by four-point probe measurements. The nanotube layer consists of non-woven metallic and semiconducting SWNT fibers as described in the above references. Burn-off measurements of deposited fibers described further below indicate a typical mix of 2 semiconducting SWNTs for every 1 metallic SWNT. For CNFET devices of preferred embodiments, metallic SWNTs are burned-off in the channel region as described further below. Such burn-off techniques while suitable for the devices described herein may be obviated through a variety of other means, primarily through the use of solely semiconducting SWNTs. The inventors have foreseen that purified semiconducting SWNTs as well as purified metallic nanotubes may be available for bulk usage and would become a preferred embodiment for a CNFET. Such semiconducting SWNTs would make the process of doping to generate n- or p-type semiconducting SWNTs substantively more facile as can be seen by those skilled in the art.

At this point in the process, a metallic contact layer may be deposited on the nanotube fabric layer. The contact layer may be patterned and act as a masking layer for etching the nanotube nanofabric layer. This method is described in U.S. patent application Ser. No. 10/864,186 entitled, “Non-volatile Electromechanical Field Effect Devices and Circuits using same and Methods of Forming Same.” Alternatively, the nanotube layer may be patterned first as illustrated in method500,FIG. 5, followed by contacts to the patterned nanotube layer.

Next, preferred methods530apply a photo or e-beam sensitive resist layer, for example, using well known industry techniques.

Next, preferred methods540expose and develop the resist layer in a desired pattern using a masking layer and optical exposure, or direct-write e-beam, or other suitable means following standard industry practices.

Next, preferred methods550etch the nanofabric layer defining the desired pattern using industry standard techniques. Ashing may be used, for example.

Next, preferred methods560strip (remove) the resist using an industry standard solvent. The resulting patterned nanofabric layer602is illustrated inFIG. 6B. The nanofabric layer illustrated inFIG. 6Bis planar and is used to define planar CNFET devices as shown further below. However, nanofabric layers604are highly conformal, as illustrated inFIG. 6C, display excellent edge coverage, and may be used for interconnections as well as devices. Although not shown in this invention, the conformal properties of nanofabrics may be used to fabricate CNFET devices with a vertical orientation, with channel lengths defined by the insulator step605illustrated inFIG. 6C, for example.

Next, preferred methods570complete the integration of the device as explained further below.

Nanofabric Metallic SWNT Burn-Off and Resulting CNFET Electrical Characteristics

U.S. Pat. No. 6,141,245, U.S. Pat. No. 6,219,215, and U.S. Pat. No. 6,243,283 by C. Bertin et al. illustrate conductor burn-off in selected portions of a patterned conductive layer. A gap is introduced below a portion of the patterned conductive layer as illustrated by structure606in prior artFIG. 7A, or below and above a portion of the patterned conductive layer as illustrated by structure620in prior artFIG. 7B. The gap substantially reduces thermal flow between the patterned conductor layer and a thermal sink such a silicon substrate layer, a portion of the conductor in the gap region is vaporized when current is passed through the patterned conducting layer, and the conducting path is interrupted as explained in U.S. Pat. Nos. 6,141,245, 6,219,215, and 6,243,283.

FIG. 7Aillustrates prior art structure606having a first insulating layer608, gap regions610, a silicon substrate612, a second insulator region614, a third insulator region616and a conducting metal layer618.FIG. 7Billustrates prior art structure620having a first insulating layer608, gap regions610′, a silicon substrate612, a second insulator region614, a third insulator region616and a conducting metal layer618. Gap region610′ may be above and below conductor618for additional thermal isolation.

The prior art technique illustrated inFIGS. 7A-Bmay be adapted to eliminate metallic SWNTs in the channel region of a CNFET device formed using the patterned nanofabric illustrated inFIG. 6B. This was confirmed experimentally as described further below. Nanofabric width WNT-LAYERmay vary from 200 to 300 nm to dimensions as small as less than 20 nm, for example. Nanofabric line-to-line spacing WNT-NT SPACINGmay vary from 200 to 300 nm to dimensions as small as less than 20 nm, for example. SWNTs in the channel region span the region between source and drain regions, which may be separated by a spacing in the range of 200 to 300 nm, to a spacing smaller than 20 nm, for example. Source and drain regions are formed when a conductor such as palladium, titanium, tungsten, or other conductor material, contact individual SWNTs as illustrated further below.

FIGS. 8A-Dillustrates a structure800having integrated SWNT nanofabric with air dielectric; structure800having a source contact802, a front (top) gate804, a drain contact806, a gap808, a nanotube channel810, a first insulator814and a second insulator812, a bottom (back) gate816and a second gap818. (FIGS. 8B-Dare micrographs of exemplary devices fabricated using semiconductor processing steps, including a semiconductor process-compatible patterned nanofabric layer; configurations other than those illustrated in the micrographs are contemplated by the inventors.)FIGS. 8A-Dillustrate a structure fabricated on a silicon substrate used as a bottom(back) gate, with insulator814of about 20 nm thickness, and a gap between insulator814and the NT channel of approximately 20 nm. Source and drain contacts to the SWNTs forming the NT channel region may be formed using Ti, Pd, W, combinations of these and other metals such as aluminum, copper, and other conductors. The NT channel suspended length may be in the range of 200 to 300 nm, for example. SWNT fibers in the patterned nanofabric layer ofFIGS. 6A and 6Bare typically in the range of 1 to 4 um in length, for example. Thus, the conductive layer between source and drain contacts consists of suspended semiconducting and metallic SWNTs. More specifically, experiments were carried out with fully suspended and partially suspended semiconducting and metallic SWNTs between source and drain contacts. In the case of fully suspended SWNTs, semiconducting and metallic SWNTs were only in contact with the source and drain electrodes. In the case of partially suspended SWNTs semiconducting and metallic SWNTs were in contact with source and drain electrodes, with SWNTs suspended in the vicinity of source and drain regions, but in physical contact with a portion of an underlying dielectric layer. Both types of devices exhibited similar electrical characteristics. The structure illustrated inFIG. 8Aalso has a front (top) gate804separated from the NT channel by a gap in the range of 30 to 60 nm. Structures similar to those illustrated inFIG. 8Aare described in more detail in U.S. patent application Ser. No. 10/864,186 entitled, “Non-volatile Electromechanical Field Effect Devices and Circuits using same and Methods of Forming Same” and 60/543,497 entitled “EEPROMS using Carbon Nanotubes,” both of which are incorporated by reference in their entireties and are commonly assigned to the assignee of the present invention. There is a gap region above and below the metallic SWNTs as illustrated in prior artFIG. 7B.

FIGS. 9A-Billustrate burn-off of the metallic SWNTs. First, the semiconducting SWNTs are turned off using the bottom (back) gate silicon substrate. These SWNTs are p-type because exposure of SWNTs to oxygen results in the adsorption of oxygen atoms on the surface of the nanotubes. The prior art concept of using a back gate electrostatic coupling to turn OFF the semiconductor channel region (explained above with respect toFIGS. 3 and 4) is applied to the NT-channel region turning SWNTs OFF, such that only the metallic SWNTs conduct, forming a porous patterned SWNT conductor layer.

FIG. 9A, top curve, illustrates the conduction of the channel region as the voltage VGATEis swept from −10 to +10 volts with a drain to source voltage of 2 volts. The voltage range is relatively high because the oxide and gap thicknesses are relatively high. The voltages can be scaled to smaller values by scaling gap and oxide values. In the presence of both metallic and semiconducting SWNTs in parallel, the ION/IOFFcurrent ratio is very small, approximately 1.5 times, for example. A back bias voltage is applied turning OFF the semiconducting SWNTs, and current is forced through the metallic SWNTs in the channel region.FIG. 9Billustrates current flow to nearly 35 uA, at which point nanotubes fail (become open-circuited) and are eliminated from the conductive path. The source-drain voltage VSDincreases to up to 8 volts before metallic SWNTs are open, with a maximum total current is approximately 35 uA. The maximum burn-off current per metallic SWNT is estimated as 10 to 20 uA. The current may be applied in steady state (DC) mode or may be a series of pulses.FIG. 9A, bottom curve, of ISDVS. VGATEillustrates P-CNFET behavior with an ION/IOFFratio>105times, confirming that only semiconducting SWNTs remain in the channel region. In other words, a non-woven SWNT nanofabric layer may be deposited (spun-on, for example), patterned, a CNFET device region defined, and metallic SWNTs burned-off, resulting in a P-CNFET device with a channel region formed by one or more semiconducting SWNTs spanning the space between source and drain regions.

Once metallic SWNT burn-off is complete, P-CNFET devices remain. These devices may be left as P-CNFETs, or may be converted by chemical processes to Ambipolar CNFETs and/or N-CNFETs. For this hybrid SRAM invention, stacked P-CNFETs are integrated into CMOS structures to form stacked low leakage P-CNFET load devices in SRAM cell regions as illustrated further below.

FIG. 11Aillustrates the conversion of a P-CNFET shown inFIG. 8Ato an Ambipolar-CNFET using the desorption of oxygen illustrating the role of oxygen adsorption in forming P-CNFET devices. Various I-V characteristics described above used bottom (back) gate electrostatic channel region modulation.FIG. 11Billustrates that the top gate, in addition to the back (bottom) gate, can also be used to control the I-V characteristic in the channel region. The top gate voltages are relatively large because of the large spacing and air “dielectric,” however, scaling of geometries and introduction of dielectric layers during integration with CMOS will significantly reduce voltage levels to the 1 to 3 volts range of operation.

SRAM Cell Structures Using Stacked P-CNFET Load Devices with Back (Bottom) Gate Structures

Stacked (non-coplanar) P-CNFET pull-up (load) devices are positioned in layers above NFET devices embedded in a semiconductor substrate. These devices may use a back (bottom) gate to turn off semiconductor SWNTs in the channel region during burn-off of metallic SWNTs. After metallic SWNT burn-off is complete, back gates may also be used to set (control) P-CNFET electrical properties of semiconductor SWNTs using electrostatic coupling to the channel region, while top (front) gates are connected to NFET devices to complete the SRAM storage cell configuration. Storage cell210inFIG. 2Ashows a schematic diagram of stacked P-CNFET devices with bottom gates, NFET devices, and interconnections to form the SRAM cell.

FIG. 12illustrates a plan view1200of a prior art cell layout corresponding to prior art schematic100illustrated inFIG. 1. Coplanar transistors T1-T6in plan view1200corresponds to transistors T1-T6in schematic100. Bit line connections to T1and T6are shown, but bit lines orthogonal to the word line WL are not shown so as to not increase plan view complexity. Local wiring1220interconnects FET T1diffusion with the diffusions of FETs T2and T3, and gates of FETs T4and T5, corresponding to interconnections shown in schematic100. Local wiring1230interconnects FET T6diffusion with the diffusions of FETs T4and T5, and the gates of FETs T2and T3, corresponding to interconnections shown in schematic100. Transistors T1and T6are transfer devices that write (set the memory to a “1” state or “0” state) or read the memory state of the cell. FETs T1and T6are typically 2.5× wider than NFETs T2and T6(assuming the same channel length for transistors T1, T2, T4, and T6) such that in the write mode, transistors T1and T6can force a change in the stored state held by the flip flop formed by “cross coupled” inverters120and130. Plan view1200is one example of an SRAM memory cell configuration. Other cell memory layouts (plan views) may be used, however, FET devices and their interconnections all correspond to schematic100.

The coplanar PFET load devices are placed in an NWELL region, and NFET devices are placed in a P substrate region. Layout ground rules require separation between the P+ diffusions of PFET devices and the P substrate region, and separation between the N+ diffusions of NFET devices and the NWELL region results in a larger cell area and complicates scaling of cell size as technology dimensions shrink. Substituting stacked P-CNFET load devices above the NFET devices in the cell region can reduce cell area by 30 to 50% by eliminating the coplanar PFET devices and the corresponding NWELL region.

FIG. 13illustrates prior art bottom structure cross section1300with corresponding surface1300S, where structure1300illustrates cross section AA′ of structure1200. Structure1300is fabricated using conventional semiconductor processing well known in the industry. Cross section1300shows gate, source, and drain regions of NFET device T2, along with cross sections of local interconnect wiring1220and1230. The source of NFET T2is grounded.

Burn-Off Back Gate Structures with Suspended SWNTs and Gap

FIG. 14is an illustration of schematic1400of a cell with fully integrated NFET devices, and partially fabricated stacked load devices T3BB and T5BB with back (bottom) gates225. The channel regions of devices T3BB and T5BB contain both metallic and semiconducting SWNTs spanning the entire separation between source and drain regions. Gates225are wired to back bias control line235using connections230as described with respect to schematic200ofFIG. 2A. T3BB front (top) gate and connection240to node245, as well as T5BB front gate and connections250to node255, are omitted and are added after metallic SWNT burn-off has been completed, as illustrated inFIG. 9.

FIG. 15Aillustrates plan view1500of schematic1400.FIG. 15Billustrates a cross section structure1500′ corresponding to cross section BB′. NFETs T1, T2, T4, and T6are fully fabricated and interconnected with local wiring. Devices T3BB and T5BB are stacked over the NFETs as shown further below. T3BB includes channel region1540having a back gate225′ corresponding to back gate225in schematic1400with insulating and gap regions described further below, and a plurality of individual metallic and semiconducting SWNT fibers1520spanning the distance between source1535and drain1530. Back gate225′ is connected to back bias control line235′ (corresponds to line235in schematic1400) by connection230′ (corresponds to line230in schematic1400). The diffusion of transfer NFET T1is connected to the drain of NFET T2, the gate of NFET T4, and the drain1530of stacked device T3BB by local wiring1220S. Sources1535and1538are connected to power supply V. T5BB includes channel region1543having a back gate225′ corresponding to back gate225in schematic1400with insulating and gap regions described further below, and a plurality of individual metallic and semiconducting SWNT fibers1520′ spanning the distance between drain1533and source1538. Back gate225′ is connected to back bias control line235′ (corresponds to line235in schematic1400) by connection230′ (corresponds to line230in schematic1400). The diffusion of transfer NFET T6is connected to the drain of NFET T4, the gate of NFET T2, and the drain1533of stacked device T5BB by local wiring1230S.

FIG. 15Billustrates a cross section structure1500′ corresponding to cross section BB′ shown in plan view1500,FIG. 15A.FIG. 15Bincludes bottom structure1300formed using well known semiconductor fabrication techniques and shows NFET T2in the cell region, but also includes other coplanar devices (not shown). Cross section structure1500′ also includes stacked device T3BB. Top cross section structure2470described further below includes channel region1540with suspended SWNTs1520, source1535, and drain region1530. Top structure2470is supported by intermediate structure2050′ and contacts surface2050S′ discussed further below. Intermediate structure2050′ is a modification of structure2050described further below in reference toFIG. 20C. Conductor1535′ contacts SWNTs1520and forms source terminal1535of device T3BB. Conductor1570contacts conductor1535′ and is used for interconnections. Insulator1565separates conductor1570from the channel region such that a top gate shown further below has minimum capacitive coupling to conductor1570. Conductor1530′ contacts SWNTs1520and forms drain terminal1530. Conductor1590contacts conductor1530′ and is used as a segment of local wiring1220S. Insulator1560, described further below with respect toFIG. 24G, separates conductor1590from the channel region such that a top gate shown further below has minimum capacitive coupling to conductor1590. Source1538and drain1533of device T5BB shown inFIG. 15Aare also formed in the same way as those of device T3BB. Channel region1540includes a plurality of SWNTs1520spanning the distance between source1535and drain1530as illustrated inFIGS. 15A and 15B. A gap1575is formed in intermediate structure2050′, below the channel region formed by SWNTs1520, as described further below. The SWNTs consist of metallic and semiconducting SWNTs exposed to anenvironment of air, oxygen, or other gas as needed. The semiconducting SWNTs are P-type as explained above. Back bias connection235′ is used to apply voltage to back (bottom) gate225′ using connection230′. The back gate voltage225′ electrostatically couples to semiconducting SWNTs in the channel region and turns them OFF. Metallic SWNTs remain conducting. At this point, the metallic SWNTs have gap regions above and below (also side to side because of the porous nature of the SWNT region) and are structurally similar to prior art structure620inFIG. 7B. The thermal conduction between SWNTs and the silicon substrate is greatly reduced by gap1575facilitating metallic SWNT heating and burn-off. Wafer-level burn-off means described further below are used to pass current through the metallic SWNTs in the channel region of device T3BB and T5BB. Metallic SWNTs are burned-off as illustrated inFIG. 9and only semiconducting SWNTs remain. At this point, structure1500′ is ready for further processing as illustrated further below.

Preferred methods are used to fabricate structure1500′ illustrated inFIG. 15B. The starting point is bottom structure1300fabricated using conventional semiconductor fabrication techniques.

Next, preferred methods deposit an insulating layer such as SiO2on surface1300S of bottom structure1300.

Next, preferred methods etch an interconnecting region in the SiO2layer reaching the top of interconnect segment1220S″. Then, preferred methods planarize the surface, forming interconnect segment1220S″ with top surface exposed, and an adjacent planar dielectric region.

At this point in the process, preferred methods form intermediate structure2050′ as described further below.

Next, intermediate structure2050′ is modified by using preferred methods to etch via hole to the top of interconnect segment1220S″ and fill via hole with metal completing the formation of local interconnect1220S′″ using well known semiconductor processing techniques.

Next, preferred methods form top structure2470as described further below. Top structure2470is in contact with top surface2050S′ of modified intermediate structure2050′. A portion of local wiring1220S composed of conductor segments1220S′,1220S″,1220S′″, and1590interconnects the drain diffusion of NFET T2with the drain1530′ of device T3BB.

Next, preferred methods etch gap region1575in insulator1555using insulator1550as an etch stop. The opening for etching gap region1575is defined by openings in the insulator illustrated by the vertical sides of insulators1560and1565(SiO2for example) and the vertical sides of SWNT contact conductors1530′ and1535′ defining the opening above the SWNT channel region. Insulator1555may be 1 to 10 nm of SiN, for example, and insulator1550may be 1 to 10 nm of Al2O3, for example. The etch must be selective to SiO2and conductors such as palladium, titanium, tungsten, and others, and also to Al2O3. Means of etching through a porous nanofabric layer uses methods described in described in more detail in U.S. patent application Ser. No. 10/864,186 entitled, “Non-volatile Electromechanical Field Effect Devices and Circuits using same and Methods of Forming Same” and 60/543,497 entitled “EEPROMS using Carbon Nanotubes.”

Burn-Off Back Gate Structures with Non-Suspended SWNTs and Gap

FIG. 15Cillustrates a cross section structure1500″ corresponding to cross section BB′ shown in plan view1500,FIG. 15A.FIG. 15Cincludes bottom structure1300formed using well known semiconductor fabrication techniques and shows NFET T2in the cell region, but also includes other coplanar devices (not shown). Cross section structure1500″ also includes stacked device T3BB. Top cross section structure2470described further below with respect toFIG. 24Gincludes channel region1540′ with non-suspended SWNTs1520, which differs from channel region1540because SWNTs1520are not suspended between source region1535, and drain region1530. Top structure2470is supported by intermediate structure2150′ and contacts surface2150S′ discussed further below. Intermediate structure2150′ is a modification of structure2150described further below With respect toFIG. 21B. Conductor1535details are as described above with respect to structure1500′. Source and drain structures and interconnections for devices T3BB and T5BB in structure1500″ are the same as described above with respect to structure1500′. Channel region1540′ includes a plurality of SWNTs1520deposited on insulator insulating layer1580spanning the distance between source1535and drain1530regions as illustrated inFIGS. 15A and 15C. Deposition of SWNTs1520on insulating layer1580facilitates deposition of a channel region insulator over the SWNTs1520later in the process, after metallic SWNTs have been burned-off, as described further below. A gap1585is formed in intermediate structure2150′, between insulator1580and back gate225′ by removing a portion of insulator1550, as described further below. The SWNTs consist of metallic and semiconducting SWNTs exposed to an environment of air, oxygen, or other gas as needed. The semiconducting SWNTs are P-type as explained above. Back bias connection235′ is used to apply voltage to back (bottom) gate225′ using connection230′. The back gate voltage225′ electrostatically couples to semiconducting SWNTs in the channel region and turns them OFF. Metallic SWNTs remain conducting. At this point, the heat flow to the silicon substrate from metallic SWNTs on insulator1580is blocked by gap1585. The SWNT structure is a variation of prior art structure606,FIG. 7A. The thermal conduction between SWNTs and the silicon substrate is greatly reduced by gap1585facilitating metallic SWNT heating and burn-off. Wafer-level burn-off means described further below are used to pass current through the metallic SWNTs in the channel region of device T3BB and T5BB. Metallic SWNTs are burned-off as illustrated inFIG. 9and only semiconducting SWNTs remain. At this point, structure1500″ is ready for further processing as illustrated further below.

Preferred methods are used to fabricate structure1500″ illustrated inFIG. 15C. The starting point is bottom structure1300fabricated using conventional semiconductor fabrication techniques.

Next, preferred methods deposit an insulating layer such as SiO2on surface1300S of bottom structure1300.

Next, preferred methods etch an interconnecting region in the SiO2layer reaching the top of interconnect segment1220S″. Then, preferred methods planarize the surface, forming interconnect segment1220S″ with top surface exposed, and an adjacent planar dielectric region.

At this point in the process, preferred methods form intermediate structure2150as described further below with respect toFIG. 21B.

Next, intermediate structure2150is modified by using preferred methods to etch via hole to the top of interconnect segment1220S″ and fill via hole with metal completing the formation of local interconnect1220S′″ using well known semiconductor processing techniques. Local wiring1230S is formed in the same way.

Next, preferred methods form top structure2470as described further below with respect toFIG. 24G. Top structure2470is in contact with top surface2150S′ of modified intermediate structure2150′. A portion of local wiring1220S composed of conductor segments1220S′,1220S″,1220S′″, and1590interconnects the drain diffusion of NFET T2with the drain1530′ of device T3BB.

Next, preferred methods form gap region1585by removing (etching) sacrificial layer2110illustrated further below with respect toFIG. 21B, composed of silicon, for example, in intermediate structure2150by etching the sacrificial layer using fluidic means through an opening to the sacrificial layer (not shown) using methods described in more detail in U.S. patent application Ser. No. 10/864,186 entitled, “Non-volatile Electromechanical Field Effect Devices and Circuits using same and Methods of Forming Same” and Ser. No. 11/053,135 entitled “EEPROMS using Carbon Nanotubes,” thus modifying intermediate structure2150to create intermediate structure2150′. The dimensions of gap1585correspond to those of back gate225′, for example, as described further below.

SRAM Cell Structure with Back Insulator Deposited through Porous SWNT Channel Region Prior to Gate Insulator Deposition

FIG. 16Aillustrates plan view1600of fully fabricated stacked P-CNFET devices referred to as T3SB and T5SB, integrated (interconnected) with corresponding NFETs T1, T2, T4, and T6to form storage structure210as illustrated in schematic200shown inFIG. 2A. Interconnections between source and drain portions of partially fabricated stacked P-FET devices T3BB and T5BB and underlying NFETs remain as described above with respect toFIGS. 15A and 15B. Fabrication of the top gate region1610including gate1660on a post metallic SWNT burn-off T3BB device structure results in a completed P-CNFET device with a plurality of semiconducting SWNT fibers referred to as device T3SB as illustrated by combined top view1600and cross section structures1600′ inFIGS. 16A and 16Brespectively. Combined top view1600and cross section structure1600′ and associated descriptions illustrate a first preferred embodiment of storage cell210illustrated schematically inFIG. 2A. Fabrication of the top gate region1615including gate1670on a post metallic SWNT burn-off T5BB device structure results in a complete P-CNFET device with a plurality of semiconducting SWNT fibers referred to as device T5SB as illustrated inFIGS. 16A and 16B. Local interconnect1620is deposited and patterned to connect the drain of T3SB, which is also connected to local wiring1220S, at contact1630and top gate1615of T5SB thereby completing local wiring1220S. Local interconnect1625is deposited and patterned to connect the drain of T5SB, which is also connected to local interconnect1230S, at contact1635and top gate1610of T3SB thereby completing local wiring1230S. Local interconnect1620and1625may use patterned nanofabric layers as described in more detail in U.S. patent application Ser. No. 10/936,119 entitled, “Patterning of Nanoscopic Articles” and related applications, all of which are incorporated by reference in their entireties and are commonly assigned to the assignee of the present invention.

FIG. 16Billustrates cross section structure1600′ corresponding to cross section CC′ shown in plan view1600,FIG. 16A.FIG. 16Bincludes structures1500′ illustrated inFIG. 15Bplus additional structure added after metallic SWNT burn-off that in total form structure1600′ illustrated inFIG. 16B. Insulator1640deposited through the porous NT layer1520, results in intermediate structure2050″ with surface2050S″. Insulator1650forms the top gate oxide between gate1660and semiconducting SWNTs1520. Via hole1685in insulating layer1680exposes the top surface of top gate1660, which is contacted at contact1635by local interconnect1625. Via hole1690in insulating layer1680exposes the top surface2490S of interconnect layer1220S, which is contacted at contact1630by local wiring1620. Plan layout structures1600and cross section structures1600′ illustrate the elements (structures) and the interconnections used to fabricate a first preferred embodiment of storage cell210illustrated schematically inFIG. 2A.

Preferred methods are used to fabricate structure1600′ illustrated inFIG. 16B. The starting point is structure1500′ illustrated inFIG. 15B.

Preferred methods fill the gap region below nanotube layer1520with an insulator through the porous (90% porous, for example) nanotube layer. The gap layer may be in the range of 1 nm to 20 nm. For shallow gap heights in the 1-3 nm range, for example, preferred methods deposit an insulator such SiO2using atomic layer deposition (ALD). For medium gap heights in the 3 to 20 nm range, for example, preferred methods deposit an insulator such as SiO2using chemical vapor deposition (CVD) techniques; those skilled in the art will understand such deposition techniques.

Next, preferred methods deposit gate insulator1650of thickness in the 2 to 10 nm range. The interface region between semiconductor SWNTs and insulators is not a critical factor in device operation as is the case for the Si/SiO2interface used for conventional FETs. Gate dielectrics such as SiO2or high-k insulators may be used.

Next, preferred methods deposit the gate conductor (or semiconductor), pattern, and planarize. The gate conductor may be tungsten, aluminum, copper, and titanium, alloys of metals, polysilicon, or silicides of silicon.

Next, preferred methods etch via holes in insulating layer1680and exposes the top surface of top gate1660, which is contacted at contact1635by local interconnect1625. Also, via hole1690in insulating layer1680exposes the top surface2490S of interconnect layer2490, which is contacted at contact1630by local wiring1620. Local interconnect wiring may use patterned nanofabric layers as described in more detail in U.S. Patent Appl. Ser. No. 10/936,119 entitled “Patterned Nanoscopic Articles and Methods of Making the Same,” and related applications.

SRAM Cell Structure Gate Insulator Deposited on SWNTs with Back Insulator

FIG. 16Aillustrates plan view1600of fully fabricated stacked P-CNFET devices referred to as T3SB and T5SB, integrated (interconnected) with corresponding NFETs T1, T2, T4, and T6to form storage structure210as illustrated in schematic200shown inFIG. 2A. Interconnections between source and drain portions of partially fabricated stacked P-FET devices T3BB and T5BB and underlying NFETs remain as described above with respect toFIGS. 15A and 15C. Fabrication of the top gate region1610including gate1660on a post metallic SWNT burn-off T3BB device structure results in a completed P-CNFET device with a plurality of semiconducting SWNT fibers referred to as device T3SB as illustrated by combined top view1600and cross section structures1600″ inFIGS. 16A and 16Crespectively. Combined top view1600and cross section structures1600″ and associated descriptions illustrate a second preferred embodiment of storage cell210illustrated schematically inFIG. 2A. Fabrication of the top gate region1615including gate1670on a post metallic SWNT burn-off T5BB device structure results in a complete P-CNFET device with a plurality of semiconducting SWNT fibers referred to as device T5SB as illustrated inFIGS. 16A and 16C. Local interconnect1620is deposited and patterned to connect the drain of T3SB, which is also connected to local wiring1220S, at contact1630and top gate1615of T5SB thereby completing local wiring1220S. Local interconnect1625is deposited and patterned to connect the drain of T5SB, which is also connected to local interconnect1230S, at contact1635and top gate1610of T3SB thereby completing local wiring1230S.

FIG. 16Cillustrates cross section structure1600″ corresponding to cross section CC′ shown in plan view1600,FIG. 16A.FIG. 16Cincludes structures1500″ illustrated inFIG. 15Cplus additional structure added after metallic SWNT burn-off that in total form structure1600″ illustrated inFIG. 16C. Insulator1650deposited on semiconductor SWNTs after burn-off forms the top gate oxide between gate1660and semiconducting SWNTs1520. Via hole1685in insulating layer1680exposes the top surface of top gate1660, which is contacted at contact1635by local interconnect1625. Via hole1690in insulating layer1680exposes the top surface2490A of interconnect layer2490, which is contacted at contact1630by local wiring1620. Plan layout structures1600and cross section structures1600″ illustrate the elements (structures) and the interconnections used to fabricate a second preferred embodiment of storage cell210illustrated schematically inFIG. 2A.

Preferred methods are used to fabricate structure1600″ illustrated inFIG. 16C. The starting point is structure1500″ illustrated inFIG. 15C.

Next, preferred methods deposit gate insulator1650of thickness in the 2 to 10 nm range. The interface region between semiconductor SWNTs and insulators is not a critical factor in device operation as is the case for the Si/SiO2interface used for conventional FETs. Gate dielectrics such as SiO2or high-k insulators may be used.

Next, preferred methods deposit the gate conductor (or semiconductor), pattern, and planarize.

Next, preferred methods etch via holes in insulating layer1680and exposes the top surface of top gate1660, which is contacted at contact1635by local interconnect1625. Also, via hole1690in insulating layer1680exposes the top surface2490S of interconnect layer2490S, which is contacted at contact1630by local wiring1620. Local interconnect wiring may use patterned nanofabric layers as described in more detail in U.S. patent application Ser. No. 10/936,119 entitled “Patterned Nanoscopic Articles and Methods of Making the Same,” and related applications.

SRAM Cell Structure Using Top and Bottom Gates and Gap Prior to Burn-Off

FIG. 16Dillustrates cross section structure1600′″ in which, unlike first and second embodiments described above, a third embodiment is described in which a gate region1610is formed prior to metallic SWNT burn-off with a gap between SWNTs1520and back gate225′.FIG. 16Dincludes bottom structure1300formed using well known semiconductor fabrication techniques and shows NFET T2in the cell region, but also includes other coplanar devices (not shown). Cross section structure1600′″ also includes stacked device T3SB′ in which the channel region includes both metallic and semiconducting SWNTs. Top cross section structure2490described further below includes channel region1540(FIGS. 15B,15C), source region1535, and drain region1530. Top structure2490is supported by intermediate structure2350′ and contacts surface2350S′ discussed further below. Intermediate structure2350′ is a modification of structure2350described further below with respect toFIG. 23D. Channel region1540includes a plurality of SWNTs1520deposited on sacrificial layer2300of structure2350illustrated further below with SWNTs1520spanning the distance between source and drain regions. Gap1693is formed in intermediate structure2350′ between SWNTs1520and back gate225′ as described further below. Fluid (or vapor) communication paths are formed from the surface to the sacrificial gap material2300and sacrificial layer material, silicon for example, is removed as explained in U.S. patent application Ser. No. 10/864,186 entitled, “Non-volatile Electromechanical Field Effect Devices and Circuits using same and Methods of Forming Same” and 60/543,497 entitled “EEPROMS using Carbon Nanotubes.” The SWNTs in structure1600′″ consist of metallic and semiconducting SWNTs because the top gate structure was formed prior to metallic SWNT burn-off. Fluid (or vapor) communications paths are left open during wafer-level burn-off and SWNTs1520are exposed to an environment of air, oxygen, or other gas as needed. The voltage applied to back gate225′, or to top gate1660by temporary interconnection1695contacting gate1660at contact1697, or to both back and front gates electrostatically couples to semiconducting SWNTs in the channel region and turns them OFF. Metallic SWNTs remain conducting. At this point, the heat flow to the silicon substrate from metallic SWNTs is blocked by gap1693. The SWNT structure is similar to prior art structure606,FIG. 7A. The thermal conduction between SWNTs and the silicon substrate is greatly reduced by gap1693facilitating metallic SWNT heating and burn-off. Wafer-level burn-off means described further below are used to pass current through the metallic SWNTs in the channel region of device T3SB′ and T5SB′. Metallic SWNTs are burned-off as illustrated inFIG. 9and only semiconducting SWNTs remain.

Preferred methods are used to fabricate structure1600′″ illustrated inFIG. 16D. The starting point is bottom structure1300fabricated using conventional semiconductor fabrication techniques.

Next, preferred methods deposit an insulating layer such as SiO2on surface1300S of bottom structure1300.

Next, preferred methods etch an interconnecting region in the SiO2layer reaching the top of interconnect segment1220S″. Then, preferred methods planarize the surface, forming interconnect segment1220S″ with top surface exposed, and an adjacent planar dielectric region.

At this point in the process, preferred methods form intermediate structure2350as described further below. Intermediate structure2350includes sacrificial layer2300, silicon for example, upon which SWNTs1520are deposited. Sacrificial layer2300is removed after fabrication of the gate structure, modifying intermediate structure2350to include gap1693, resulting in intermediate structure2350′ as described further below.

Next, preferred methods form top structure2490as described further below. Top structure2490is in contact with top surface2350S′ of modified intermediate structure2350′. A portion of local wiring1220S composed of conductor segments1220S′,1220S″,1220S′″, and1682interconnects the drain diffusion of NFET T2with the drain1530of device T3SB.

Next, preferred methods etch fluid (or vapor) communication paths from the surface to the sacrificial gap material2300and sacrificial layer material, silicon for example, is removed as explained in U.S. patent application Ser. No. 10/864,186 entitled, “Non-volatile Electromechanical Field Effect Devices and Circuits using same and Methods of Forming Same” and U.S. patent application Ser. No. 11/053,135 entitled “EEPROMS using Carbon Nanotubes.” The SWNTs in structure1800′ consist of metallic and semiconducting SWNTs because the top gate structure was formed prior to metallic SWNT burn-off. Fluid (or vapor) communications paths are left open during wafer-level burn-off and SWNTs1520are exposed to an environment of air, oxygen, or other gas as needed.

SRAM Cell Structure Using Top and Bottom Gates and Gap After Burn-Off and Wired for SRAM Cell Operation

FIG. 16Eillustrates cross section structure1600″″ corresponding to cross section CC′ shown in plan view1600ofFIG. 16A.FIG. 16Eincludes structure1600′″ illustrated inFIG. 16Dwith modified local wiring to complete local interconnections required to complete SRAM storage structure210as illustrated schematically inFIG. 2A. Local wiring layer1695is removed, a second opening1699is formed, and new local wiring1625contacting gate1660at contact1635, and local wiring1620contacting local wiring segment1680at contact1630is deposited and patterned to complete SRAM storage structure210. Local interconnections1620and1625may use patterned nanofabric layers as described in more detail in U.S. patent application Ser. No. 10/936,119 entitled “Patterned Nanoscopic Articles and Methods of Making the Same,” and related applications.

Preferred methods are used to fabricate structure1600″″ illustrated inFIG. 16E. The starting point is structure1600′″ illustrated inFIG. 16D.

Preferred methods remove local wiring layer1695.

Next, preferred methods etch a hole1699reaching local interconnect segment2490using conventional methods.

Next, preferred methods deposit a conductive layer. The conductive layer is patterned to form local interconnect segments1620and1625. Local interconnect segments1620and1625may use patterned nanofabric layers as described in more detail in U.S. patent application Ser. No. 10/936,119 entitled “Patterned Nanoscopic Articles and Methods of Making the Same,” and related applications.

Burn-Off with Top Gate Structures with Suspended SWNTs and Gap (No Back Gates)

FIG. 17is an illustration of schematic1700of a cell with fully integrated NFET devices and fully fabricated pre-burn-off top gate stacked devices T3BT and T5BT with channel region SWNTs1520having both semiconducting and metallic SWNTs. No back gate is used. Electrical characteristics of devices T3BT and T5BT are controlled by chemical means only, so there is no need for a back gate to electrostatically set the operating point of the devices after burn-off.FIG. 10Billustrates a P-CNFET device with post-burn-off electrical characteristics such that the P-CNFET device is normally OFF when gate-to-source voltage is zero. Schematic1700shows all devices interconnected as the storage cell260schematic shown inFIG. 2B, except that the stacked devices T3BT and T5BT of interconnected inverters1720and1730are connected to burn-off control line1750by connections1740.

FIG. 18Aillustrates plan view1800of the circuit of schematic1700.FIG. 18Billustrates a cross section structure1800′ corresponding to cross section DD′.FIG. 18Billustrates cross section structure1800′ in which, unlike first, second, and third embodiments described above, a fourth embodiment is described in which a gate region1805is formed prior to metallic SWNT burn-off with a gap1850below SWNTs1520.FIG. 18Bincludes bottom structure1300formed using well known semiconductor fabrication techniques and shows NFET T2in the cell region, but also includes other coplanar devices (not shown). Cross section structure1800′ also includes stacked device T3BT in which the channel region includes both metallic and semiconducting SWNTs1520, source1810, and drain1820. Top structure2490is supported by intermediate structure2350′ and contacts surface2350S″ discussed further below. Intermediate structure2350″ is a modification of structure2350described further below. The channel region is formed by a plurality of SWNTs1520deposited on sacrificial layer2300of structure2350illustrated further below with respect toFIG. 23Dand with SWNTs1520spanning the distance between source1810and drain1820electrodes. Gap1850is formed in intermediate structure2350″ below SWNTs1520as described further below. Fluid (or vapor) communication paths are formed from the surface to the sacrificial gap material2300and sacrificial layer material, silicon for example, is removed as explained in U.S. patent application Ser. No. 10/864,186 entitled, “Non-volatile Electromechanical Field Effect Devices and Circuits using same and Methods of Forming Same” and U.S. patent application Ser. No. 11/053,135 entitled “EEPROMS using Carbon Nanotubes.” The SWNTs in structure1800′ consist of metallic and semiconducting SWNTs because the top gate structure was formed prior to metallic SWNT burn-off. Fluid (or vapor) communications paths are left open during wafer-level burn-off and SWNTs1520are exposed to an environment of air, oxygen, or other gas as needed. Voltage top gate1840is used to turn semiconducting SWNTs OFF. The voltage applied to top gate1840by temporary connection1740′ contacting burn-off control line1750′. Top gate1840electrostatically couples to semiconducting SWNTs in the channel region and turns them OFF. Metallic SWNTs remain conducting. At this point, the heat flow to the silicon substrate from metallic SWNTs is blocked by gap1850. The SWNT structure is similar to prior art structure606,FIG. 7A. The thermal conduction between SWNTs and the silicon substrate is greatly reduced by gap1850facilitating metallic SWNT heating and burn-off. Wafer-level burn-off means described further below are used to pass current through the metallic SWNTs in the channel region of device T3SB′ and T5SB′. Metallic SWNTs are burned-off as illustrated inFIG. 9and only semiconducting SWNTs remain.

Preferred methods are used to fabricate structure1800′ illustrated inFIG. 18B. The starting point is bottom structure1300fabricated using conventional semiconductor fabrication techniques.

Next, preferred methods deposit an insulating layer such as SiO2on surface1300S of bottom structure1300.

Next, preferred methods etch a via hole in the SiO2layer reaching the top of interconnect segment1220S′. Then, fill the via hole with a conducting layer and planarize the surface, forming interconnect segment1220S″ with top surface exposed, and an adjacent planar dielectric region.

At this point in the process, preferred methods form intermediate structure2350as described further below. Intermediate structure2350includes sacrificial layer2300, silicon for example, upon which SWNTs1520are deposited. Sacrificial layer2300is removed after fabrication of the gate structure, modifying intermediate structure2350to include gap1850, resulting in intermediate structure2350″ as described further below.

Next, preferred methods form top structure2490as described further below. Top structure2490is in contact with top surface2350S″ of modified intermediate structure2350″. A portion of local wiring1220S composed of conductor segments1220S′ and1220S″ interconnects the drain diffusion of NFET T2with the drain1820of device T3SB.

Next, preferred methods etch fluid (or vapor) communication paths from the surface to the sacrificial gap material2300and sacrificial layer material, silicon for example, is removed as explained in U.S. patent application Ser. No. 10/864,186 entitled, “Non-volatile Electromechanical Field Effect Devices and Circuits using same and Methods of Forming Same” and U.S. patent application Ser. No. 11/053,135 entitled “EEPROMS using Carbon Nanotubes.” The SWNTs in structure1800′ consist of metallic and semiconducting SWNTs because the top gate structure was formed prior to metallic SWNT burn-off. Fluid (or vapor) communications paths are left open during wafer-level burn-off and SWNTs1520are exposed to an environment of air, oxygen, or other gas as needed.

FIG. 19Billustrates cross section structure1900′ corresponding to cross section EE′ shown in plan view1900ofFIG. 19A.FIG. 19Bincludes structure1800′ illustrated inFIG. 18Bwith modified local wiring to complete local interconnections required to complete SRAM storage structure260as illustrated schematically inFIG. 2B. Local wiring layer1740′ is removed, a second opening1970is formed, and new local wiring1910and local wiring1920are patterned from a deposited conducting layer to complete SRAM storage structure260. Local interconnections1910and1920may use patterned nanofabric layers as described in U.S. patent application Ser. No. 10/936,119 entitled“Patterned Nanoscopic Articles and Methods of Making the Same,” and related applications.

Preferred methods are used to fabricate structure1900′ illustrated inFIG. 19B. The starting point is structure1800′ illustrated inFIG. 18B.

Preferred methods remove local wiring layer1740′.

Next, preferred methods etch a hole1970reaching local interconnect segment2490using conventional methods.

Next, preferred methods deposit a conductive layer. The conductive layer is patterned to form local interconnect segments1910and1920. Local interconnect segments1910and1920may use patterned nanofabric layers as described in more detail in U.S. patent application Ser. No. 10/936,119 entitled “Patterned Nanoscopic Articles and Methods of Making the Same,” and related applications.

Fabrication of Structure2050

Preferred methods deposit and pattern a conductor225′ using well known industry techniques, that may be used as a back gate electrode, on substrate2000as illustrated inFIG. 20A. Conductor225′ may be 20 to 200 nm thick, for example, fabricated using tungsten, titanium, aluminum, copper, a metal alloy, a semiconductor, and a silicided semiconductor. Substrate2000may contain other structures such as structure1300.

Next, preferred methods directionally etch and planarize insulator2010until the surface of conductor225′ is exposed. Then, preferred methods deposit insulating layer1550, Al2O3, for example, 2 to 50 nm thick, for example. Then, preferred methods deposit insulating layer1555, SiN for example, 2 to 50 nm thick, for example completing the fabrication of structure2050with surface2050S as illustrated inFIG. 20C.

Fabrication of Structure2150

Preferred methods deposit a sacrificial layer2100′, silicon of thickness 2 to 50 nm, for example, on a planar surface including insulator2105, SiO2 for example, and a conductor225′. Conductor225′ may be 20 to 200 nm thick, for example, fabricated using tungsten, titanium, aluminum, copper, a metal alloy, a semiconductor, or a silicided semiconductor as illustrated inFIG. 21A.

Fabrication of Structure2250

Preferred methods deposit insulating layer1550, SiN for example, 2 to 50 nm thick, for example, using well known industry techniques on a planar surface including insulator2205, SiO2 for example, and a conductor225′. Conductor225′ may be 20 to 200 nm thick, for example, fabricated using tungsten, titanium, aluminum, copper, a metal alloy, a semiconductor, or a silicided semiconductor. Then, preferred methods deposit sacrificial layer2200′, silicon of thickness 2 to 50 nm, for example as illustrated inFIG. 22A.

Next, preferred methods pattern sacrificial layer2200′ to form sacrificial structure2200, as illustrated inFIG. 22B.

Next, preferred methods deposit insulating layer2210, SiO2, for example, of thickness 2 to 50 nm, for example as illustrated inFIG. 22C.

Fabrication of Structure2350

Preferred methods deposit sacrificial layer2300′, silicon, for example, of thickness 2 to 50 nm, for example, on a planar surface of insulator2310, SiO2for example, as illustrated inFIG. 23A.

Preferred methods deposit a monolayer 0.5 to 5 um layer of non-woven nanofabric of SWNT on substrate2000using methods in U.S. Pat. Nos. 6,643,165, 6,574,130, 6,706,402, 6,784,028, 6,835,591, 6,911,682, 6,919,592 and 6,924,538 and U.S. patent application Ser. Nos. 10/341,005, 10/341,055, 10/341,054, 10/341,130 and 10/776,059. Preferred methods pattern the nanotube fabric layer. Alternatively, conducting layer1560′ is deposited on nanofabric layer1520. Conducting layer1560′ contacts SWNTs in nanofabric layer1520and forms source and drain of CNFET devices. Conducting layer1560′ may be 2 to 50 nm thick, and may be titanium, palladium, tungsten, or other conductors that form contacts with desirable electrical characteristics with nanotubes, Ohmic for example, or Schottky with low barrier heights, for example, as illustrated inFIG. 24A.

Next, preferred methods deposit an insulator layer1565and pattern as illustrated inFIG. 24B.

Next preferred methods deposit and pattern a sacrificial layer2410, such as silicon, alumina, resist, or other suitable material as illustrated inFIG. 24C.

Next, preferred methods planarize the structure ofFIG. 24D, with sacrificial region2410′ in the opening in insulator1565, and conductor1570forming an interconnecting wiring layer in contact with conductor layer1560′ as illustrated inFIG. 24E.

Next, preferred methods remove (etch) sacrificial region2410′ exposing SWNTs1220to expose a nanotube channel region containing metallic and semiconducting SWNTs as illustrated inFIG. 24F.

Next, preferred methods etch the exposed portion of conductor layer1560′ and forming conductor1560, defining the region between source and drain regions and the channel region as illustrated inFIG. 24G.

Next, deposit gate insulator1650in the channel region. Insulator1650may be SiO2, SiN, high-k dielectric. The insulator to SWNT interface is not critical for CNFET transistors, as is the interface between gate SiO2 and Si for NFET and PFET transistors. Then, deposit conductor1660′ as illustrated inFIG. 24H.

Fabricated metallic SWNT burn-off structures for devices with gaps (effective dielectric constant of 1) using nanofabric are illustrated inFIG. 8.FIG. 9illustrates burn-off conditions (current and voltage), and post-burn-off P-CNFET electrical characteristics are illustrated above inFIGS. 10A and 10B.FIGS. 14-24illustrate structures and preferred fabrication methods that may be used to integrate a large number (a megabit, for example) of denser hybrid stacked P-CNFET SRAM cells within a chip, with multiple chips per wafer. Gap regions exposed to an environment such as air, oxygen, or other during burn-off are illustrated for use during wafer-level burn-off. Post-burn-off structures with optimized P-CNFET devices having gate dielectrics such as SiO2 with εR=3.9, SiN with εR=7.5, and with high-k (high εR) dielectrics such as tantalum pentoxide (TaO5) with εR=20 are also illustrated.

FIG. 25illustrates schematic2500, which is schematic1400with burn-off current paths illustrated, shows the use of integrated NFET transfer devices T1and T6to select pre-optimized integrated P-CNFET devices having a back control gate225connected to applied back bias voltage VBBpower supply connection235by connector230to turn-off semiconducting SWNTs during metallic SWNT burn-off. From the burn-off results illustrated inFIG. 9, the per-cell burn-off current IBO-Cis estimated as 100 uA, with I′BO=50 uA for each half. NFET transfer devices T1and T6are capable of carrying such currents, including scaling, to at least the 45 nm node. Transfer NFETs T1and T6are typically 2.5 times the width of storage cell NFETs T2and T4. Generations of FET scaling have indicated that the current carrying capability of scaled NFET devices is in the range of 700 to 900 uA/um. Assuming a current carrying capability based on 700 uA/um, the burn-off current carrying capability of transfer NFET devices T1and T6as a function of technology node may be summarized as follows:180 nm technology node: I′BO-MAX=315 uA;130 nm technology node: I′BO-MAX=227 uA;90 nm technology node: I′BO-MAX=157 uA;65 nm technology node: I′BO-MAX=113 uA; and45 nm technology node: I′BO-MAX=78 uA.

The ratio of semiconducting SWNTs to metallic SWNTs for CNFET devices is expected to increase over time, and perhaps eventually eliminate the need for burn-off, so the technique is expected to scale for even smaller technology nodes than 45 nm.

The burn-off requirements are that T1and T6devices are turned to the ON state. NFET channel resistance is expected to be much lower (10×, for example) than the resistance of the metallic SWNTs to be burned-off, the voltage at nodes2520and2530is expected to remain quite low with NFET devices T2and T4remaining in the OFF state. However, if the voltage on nodes2520and2530exceed T2and T4threshold voltages, these devices will provide an additional path for burn-off current, but too small a burn-off current to provide a significant increase in current carrying capability. Metallic SWNTs in multiple cells in parallel are burned-off increasing the total burn-off current to be supplied during wafer-level burn-off as discussed further below.

FIG. 26illustrates schematic2600, which is schematic1400with burn-off current paths illustrated, shows the use of integrated NFET transfer devices T1and T6to select near-optimized integrated P-CNFET devices having a front gate control to turn-off semiconducting SWNTs during metallic SWNT burn-off, with front gate connected to burn-off voltage connection1750by connector1740, supplying gate voltage VBT. Burn-off currents and cell operation during burn-off are the same as described with respect to schematic2500,FIG. 25above.

FIG. 27illustrates a sub-array burn-off architecture using cells 1′−cell N′×M′. These cells may be the same as illustrated in schematic2500or as illustrated in cell2600. Some differences in cell current value IBO-Cmay occur as a function of the corresponding structures, however, for purpose of illustrating wafer level burn-off, IBO-C=100 um will be used. The SRAM product circuits such as word decode, bit decode and sense amplifier, timing circuits, etc. are not fully wired at this point and are not powered. In addition to wafer-level burn-off, it is desirable to monitor post burn-off currents to ensure complete burn-off of metallic SWNTs. Since only cell regions are powered, significant cell currents after burn-off are only caused by incomplete burn-off of metallic SWNTs, and additional burn-off cycles may be used to complete the wafer-level burn-off operation. Only burn-off select devices and simple select pads and circuits are operational at this point in the fabrication cycle as illustrated inFIG. 27. The burn-off current flow IBO-A is the cumulative current flow at the sub-array level as illustrated inFIG. 27.

Wafer-level burn-off current to multiple chips in parallel is supplied at the wafer level. The number of parallel burn-off cells allowed depends on the current carrying capability of the wafer probe. Wafer probing of pads is discussed in detail by G. Das et al., “Wafer-Level Test,” Chapter 3, or reference book “Area Array Interconnections Handbook,” Editors K. Puttlitz and P. Totta, Kluwer Academic Publishers, 2001. A more recent application note by Otto Weeden, “Probe Card Tutorial,” Keithly Instruments, Inc., at www.keithley.com/servlet/Data? Id=13263, 2004 pp. 19-20 gives current carrying capability of probes as a function of probe material and probe diameter as a function of application conditions such as duty cycle. Current carrying capability, in this case for purposes of burn-off of parallel cells, of a probe of 5 mil tip diameter as function of duty cycle at steady state (DC), 10%, and 1% duty cycle is shown in the table ofFIG. 31. The same 5 mil diameter probe can carry 10× the current at 1% duty cycle as it can carry in steady state (DC) operation. A burn-off tester is a simple in-line wafer-level tester connected to wafer-level probes, with individual probe current carrying capabilities as shown in table 1. Based on 100 um burn-off current per cell, the maximum number of parallel cells per probe may be calculated. The number of probes per chip required to supply the burn-off current for a million cells (or more accurately, 220=1,048,576) is then calculated and 5 additional pads are added for common ground, mode selection, burn-off, timing, etc. A common ground may be used by powering burning-off one subsection of memory at a time to ensure that the ground probe does not exceed the per probe maximum current carrying requirement. Note that the number of additional bits to satisfy redundancy requirements for yield is typically very small, and may be ignored in terms of contribution to total burn-off current. The number of devices that may be simultaneously burned-off is then calculated. Assuming 200 chips per wafer, the number of stepping per wafer is then calculated, all as a function of duty cycle, all shown in table 1. Duty cycle is a major factor in the number of stepping operations, a reduction from 25 multi-chip probing operations for steady state conditions to 3 stepping operations for a 1% duty cycle. Optimum burn-off conditions will vary for the various cell structures described above.

FIG. 28illustrates that a simple burn-off decode structure may be added to control the number of cells that are ON and OFF along a bit line segment, for example. More sophisticated methods such as the use of burn-in self-test (BIST) engines (not shown) may also be introduced for each chip. Use of BIST engines for wafer-level test and burn-in (or in this case adapted for burn-off) are described in U.S. Pat. No. 6,426,904 where C. Bertin is a co-inventor. The BIST engine controls a level sensitive (LSSD) protocol. The use of BIST may require more interconnections than those for the methods described above, and may be more effectively used for burn-off of near-optimized cells such as illustrated in schematic2600,FIG. 26. The advantage of BIST is that the wafer-level tester requirements are greatly reduced, that the number of probes per chip is reduced to 10, 5 for the BIST engine, and 5 for power supply, ground, etc. The on-chip circuits switch individual cell blocks sequentially and enable the use of only one burn-off probe by limiting the number of metallic SWNTs burned in parallel. With 10 pads per chip, 200 chips on a wafer may be simultaneously burned-off and tested with a 2000 Terminal wafer-level probe. Full-wafer probing techniques are discussed by C. Bertin et al, “Known Good Die (KDG),” Chapter 4, of reference book “Area Array Interconnection Handbook,” editors K. Puttlitz and P. Totta, Kluwer Academic publishers, 2001.

Burn-off methods that use on-chip electronic selection may expose the cell NFET devices to relatively high voltage if transfer device NFETs T1and T6are turned OFF without also removing the burn-off voltage from the cells, as is done for burn-off architecture described with respect toFIG. 27. One option is to increase the breakdown voltage of all cell NFET devices with modified diffused N+ junctions. Some density gain due to stacking of P-CNFET devices may be lost; however, cell stability is increased because of additional node capacitance. The bit line capacitance is unchanged because the increased junction capacitance is not on bit-line connection side of transfer devices T1and T6.FIG. 29gives an example of a modified cross section for NFET device T2. A similar change for devices T4, T1and T6would also occur. The high-voltage diffusion is designed to tolerate the relatively high voltage of 8 volts that can occur during metallic SWNT burn-off by using a deeper and more rounded doping profile, as is used to meet the high-voltage requirements of EEPROM devices described in the reference book K. Itoh, “VLSI Memory Chip Design,” Springer Publisher, pp. 37-46, 2001. Structure2900with surface2900S can be interchanged with structure1300and1300S in all structures illustrated in all figures above.

FIG. 30illustrates the architecture3000, which is the same as the architecture2800ofFIG. 28, except that burn-off select devices are in the OFF state for normal SRAM operation.

Preferred embodiments of the invention provide a process and design scheme that is manufacturable and that can yield a SRAM that has electrical characteristics that outperform the figures of merit of current and future state-of-the-art semiconductor-based devices.

While the embodiments above were illustrated with suspended fabrics to facilitate burn-off of metallic nanotubes, the inventors envision that burn-off may be achieved with partially suspended fabrics and non-suspended fabrics as well.

While all of the figures in the present application suggest that the nanotube fabric channel is horizontally oriented, other embodiments of the present invention utilize vertical or non-horizontally oriented nanofabric channels along with adjacent gates, arranged in appropriate geometries. Such non-horizontally oriented fabrics may be fabricated according to the methods described in U.S. Pat. No. 6,924,538, entitled, Electro-Mechanical Switches and Memory Cells Using Vertically-Disposed Nanofabric Articles and Methods of Making the Same, which is incorporated by reference in its entirety.

Other embodiments include a double-gated FET having multi-walled carbon nanotubes alone or in combination with SWNTs.

The gates need not be opposed vertically, but may be opposed horizontally. An alternate embodiment of the present invention therefore would include horizontally opposed gates surrounding the channel.

It will be further appreciated that the scope of the present invention is not limited to the above-described embodiments but rather is defined by the appended claims, and that these claims will encompass modifications and improvements to what has been described.