Flip-flops having strong transistors and weak transistors

An integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors in at least one strong active-region structure. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented with weak transistors in at least one weak active-region structure. The integrated circuit further includes a first inverter cross coupled with the first clocked inverter and a second inverter cross coupled with the second clocked inverter. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application relates to U.S. application Ser. No. 18/160,630 filed Jan. 27, 2023, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The recent trend in miniaturizing integrated circuits (ICs) has resulted in smaller devices which consume less power yet provide more functionality at higher speeds. The miniaturization process has also resulted in stricter design and manufacturing specifications as well as reliability challenges. Various electronic design automation (EDA) tools generate, optimize and verify standard cell layout designs for integrated circuits while ensuring that the standard cell layout design and manufacturing specifications are met.

DETAILED DESCRIPTION

In some embodiments, a master-slave flip-flop includes a first latch having a first inverter cross coupled with a first clocked inverter and a second latch having a second inverter cross coupled with a second clocked inverter. The first clocked inverter and the second clocked inverter are implemented with weak transistors. The master-slave flip-flop also includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors. The output of the first clocked forwarding-switch is conductively connected with the input of the first inverter. The output of the second clocked forwarding-switch is conductively connected with the input of the second inverter.

In some embodiments, the first clocked forwarding-switch is a transmission gate which is coupled between the output of an input device and the input of the first inverter. In some embodiments, the second clocked forwarding-switch is a transmission gate which is coupled between the output of the first inverter and the input of the second inverter. In some embodiments, the second clocked forwarding-switch is a third clocked inverter which is coupled between the input of the first inverter and the input of the second inverter.

The average gate width of the strong transistors with p-channels is larger than the average gate width of the weak transistors with p-channels. The average gate width of the strong transistors with n-channels is larger than the average gate width of the weak transistors with n-channels. The strong transistors are implemented with strong active-region structures, and the weak transistors are implemented with weak active-region structures. Specifically, the strong PMOS transistors are implemented with strong PMOS active-region structures, and the weak PMOS transistors are implemented with weak PMOS active-region structures. The strong NMOS transistors are implemented with strong NMOS active-region structures, and the weak NMOS transistors are implemented with weak NMOS active-region structures.

In some embodiments, a strong PMOS active-region structure has more fins than a weak PMOS active-region structure, and a strong NMOS active-region structure has more fins than a weak NMOS active-region structure. In some embodiments, a strong PMOS active-region structure has more nano-sheets than a weak PMOS active-region structure, and a strong NMOS active-region structure has more nano-sheets than a weak NMOS active-region structure. In some embodiments, a strong PMOS active-region structure has more nano-wires than a weak PMOS active-region structure, and a strong NMOS active-region structure has more nano-wires than a weak NMOS active-region structure.

The master-slave flip-flops in this disclosure include both strong transistors and weak transistors, thereby the RC delay in the forward signal path of a master-slave flip-flops is reduced while the driving strengths of the first clocked inverter and the second clocked inverter in the backward signal paths are reduced. The master-slave flip-flops in this disclosure have improved switching speeds, as compared with alternative designs in which the transistors with same type of channel (i.e., p-channel or n-channel) have uniform gate widths.

FIGS.1A1-1C1are block diagrams of integrated circuits100A-100C having a master-slave flip-flop and the associated supporting circuits, in accordance with some embodiments. FIGS.1A2-1C2are circuit diagrams of integrated circuits100A-100C having a master-slave flip-flop and the associated supporting circuits, in accordance with some embodiments. The master-slave flip-flop is formed with an input device101, a first clocked forwarding-switch103, a master latch104, a second clocked forwarding-switch105, a slave latch106, and an output driver109. The first clocked forwarding-switch103is configured to receive input signals from the input device101. The master latch104is coupled between the first clocked forwarding-switch103and the second clocked forwarding-switch105. The slave latch106is coupled between the second clocked forwarding-switch105and the output driver109. The associated supporting circuits include inverters110A-110C which are configured to generate an inverted clock signal CPB and an in-phase clock signal CPBB.

In FIG.1A1and FIG.1A2, the first clocked forwarding-switch103is implemented as a transmission gate110F1and the second clocked forwarding-switch105is implemented as a gated inverter105H1. In FIGS.1B1-1C1and FIGS.1B2-1C2, the first clocked forwarding-switch103is implemented as a transmission gate110F1and the second clocked forwarding-switch105is implemented as a transmission gate110H1.

In FIGS.1A1-1C1and FIGS.1A2-1C2, the master latch104is implemented with an inverter110G and a clocked inverter110F2which are cross coupled with each other, and the slave latch106is implemented with an inverter1101and a clocked inverter110H2which are cross coupled with each other. In FIG.1C1and FIG.1C2, the inverter110G in the master latch104is a resettable inverter, and the clocked inverter110H2in the slave latch106is a resettable clocked inverter.

In FIGS.1A1-1C1and FIGS.1A2-1C2, the input device101includes a gated inverter110D and a gated inverter110E. The gated inverter110D is configured to receive a data signal D, and the gated inverter110E is configured to receive a scan signal SI. Each of the gated inverter110D and the gated inverter110E includes a first part (labeled correspondingly as110Dp and110Ep) having the PMOS transistors and a second part (labeled correspondingly as110Dn and110En) having the NMOS transistors. In some embodiments, the input device101includes the gated inverter110D but excludes the gated inverter110E.

In FIGS.1A1-1C1and FIGS.1A2-1C2, the transmission gate110F1is configured to receive the inverted clock signal CPB and the in-phase clock signal CPBB. When the inverted clock signal CPB is at logic LOW (and the in-phase clock signal CPBB is at logic HIGH), none of the data signal D from the gated inverter110D and the scan signal SI from the gated inverter110E is transmitted to the input node ml_ax of the master latch104. When the inverted clock signal CPB is at logic HIGH (and the in-phase clock signal CPBB is at logic LOW), the inverse of the data signal D or the scan signal SI is transmitted to the input node ml_ax of the master latch104.

In FIGS.1A1-1C1and FIGS.1A2-1C2, the master latch104includes an inverter110G and a clocked inverter110F2driven by the clock signals CPB and CPBB. The output of the inverter110G is connected to the input of the clocked inverter110F2, while the output of the clocked inverter110F2is connected to the input of the inverter110G. When the clock signal CPB is at logic HIGH (and the clock signal CPBB is at logic LOW), the master latch104is at the unlatched state, the signal at the output node ml_b of the master latch104is the inverse of the signal at the input node ml_ax of the master latch104. Consequently, the signal at the output node ml_b becomes the inverse of the selected input signal (which is either the data signal D received from the input device101or the scan signal SI received from the input device101). Meanwhile, the second clocked forwarding-switch105is set to the non-connected state by the clock signals CPB and CPBB, and the input node sl_a of the slave latch106is decoupled from the master latch104. Thereafter, when the inverted clock signal CPB is changed to logic LOW (and the in-phase clock signal CPBB is changed to logic HIGH), the master latch104is changed to the latched state, the signal in the master latch104is maintained during the time period that the clock signal CPB at logic LOW (and the clock signal CPBB at logic HIGH). The latched signal value at the output node ml_b is the signal value of the selected input signal (received from the input device101) at a first falling edge of the clock signal CPB, as the clock signal CPB is changed to logic LOW.

When the clock signal CPB is changed to logic LOW (and the clock signal CPBB is changed to logic HIGH), the second clocked forwarding-switch105is changed to the connected state by the clock signals CPB and CPBB, and the latched signal in the master latch104is either transmitted from the input node ml_ax to the input node sl_a of the slave latch106(as in FIG.1A1and FIG.1A2) or from the output node ml_b to the input node sl_a of the slave latch106(as in FIGS.1B1-1C1and FIGS.1B2-1C2).

In FIGS.1A1-1C1and FIGS.1A2-1C2, the slave latch106includes an inverter110I and a clocked inverter110H2driven by the clock signals CPB and CPBB. The output of the inverter110I is connected to the input of the clocked inverter110H2, while the output of the clocked inverter110H2is connected to the input of the inverter110I. When the clock signal CPB is at logic LOW (and the signal CPBB is at logic HIGH), the slave latch106is at the unlatched state, and the signal at the output node sl_bx of the slave latch106is the inverse of the signal at the input node sl_a of the slave latch106. Consequently, the inverse of the latched signal at the output node ml_b of the master latch104is transmitted to the output node sl_bx of the slave latch106. Thereafter, when the clock signal CPB is changed to logic HIGH (and the signal CPBB is changed to logic LOW), the slave latch106is changed to the latched state, the signal at the output node sl_bx of the slave latch106is maintained, and the latched signal value at the output node sl_bx after the current rising edge of the clock signal CPB is the inverse of the latched signal at the output node ml_b which is latched after the previous falling edge (the first falling edge) of the clock signal CPB.

During the time period when the clock signal CPB is at logic HIGH after the current rising edge of the clock signal CPB, the signal value Qn+1at the output Q of the output driver109(which is implemented as an inverter110J) is equal to the signal value of the selected input signal (received from the input device101) at the previous falling edge (the first falling edge) of the clock signal CPB.

In FIGS.1A1-1C1and FIGS.1A2-1C2, at least the first clocked forwarding-switch103and the second clocked forwarding-switch105are implemented with strong transistors, while the clocked inverter110F2and the clocked inverter110H2are implemented with weak transistors. A CMOS inverter implemented with strong transistors has larger driving strength than a CMOS inverter implemented with weak transistors. A CMOS buffer implemented with strong transistors has larger driving strength than a CMOS buffer implemented with weak transistors. In some embodiments, the input device101and/or the output driver109are also implemented with strong transistors. In some embodiments, at least one of the inverter110G of the master latch104and the inverter1101of the slave latch106is implemented with strong transistors as well.

FIG.2is a floor plan of the integrated circuits100A-100C in FIGS.1A1-1C1and FIGS.1A2-1C2, in accordance with some embodiments. InFIG.2, the input device101, the first clocked forwarding-switch103, the second clocked forwarding-switch105, and the output driver109are implemented correspondingly in layout areas “D”, “F1”, “F2”, and “J”. The clocked inverter110F2and the clocked inverter110H2are implemented correspondingly in layout areas “F2” and “H2”.

The integrated circuits inFIG.2includes a strong PMOS active-region structure220P extending in the X-direction, a strong NMOS active-region structure220N extending in the X-direction, a weak PMOS active-region structure230P extending in the X-direction, and a weak NMOS active-region structure230N extending in the X-direction. Each of the input device101, the first clocked forwarding-switch103, the second clocked forwarding-switch105, and the output driver109(correspondingly in the layout areas “D”, “F1”, “F2”, and “J”) is constructed with p-channel strong transistors in the strong PMOS active-region structure220P and n-channel strong transistors in the strong NMOS active-region structure220N. Each of the clocked inverter110F2and the clocked inverter110H2(correspondingly in the layout areas “F2” and “H2”) is constructed with p-channel weak transistors in the weak PMOS active-region structure230P and n-channel weak transistors in the weak NMOS active-region structure230N. Each of the input device101, the first clocked forwarding-switch103, the second clocked forwarding-switch105, and the output driver109is implemented as a class-one device, while each of the clocked inverter110F2and the clocked inverter110H2is implemented as a class-two device. In some alternative embodiments, at least one of the input device101and the output driver109is not implemented as a class-one device.

In the circuit cell ofFIG.2, the average gate width of the strong transistors with p-channels in the class-one devices is larger than the average gate width of the weak transistors with p-channels in the class-two devices, and the average gate width of the strong transistors with n-channels in the class-one devices is larger than the average gate width of the weak transistors with n-channels in the class-two devices.

In some embodiments, when the active-region structures are formed with fin structures, the transistors fabricated in the strong PMOS active-region structure220P and in the weak PMOS active-region structures230P are correspondingly strong p-channel FinFETs and weak p-channel FinFETs, while the transistors fabricated in the strong NMOS active-region structure220N and in the weak NMOS active-region structures230N are correspondingly strong n-channel FinFETs and weak n-channel FinFETs. The number of fins in the strong PMOS active-region structure220P having p-channel strong transistors is larger than the number of fins in the weak PMOS active-region structure230P having p-channel weak transistors, and the number of fins in the strong NMOS active-region structure220N having n-channel strong transistors is larger than the number of fins in the weak NMOS active-region structure230N having n-channel weak transistors. In one specific example, each of the strong PMOS active-region structure220P and the strong NMOS active-region structure220N has three fins, while each of the weak PMOS active-region structure230P and the weak NMOS active-region structure230N has two fins.

In some embodiments, when the active-region structures are formed with nano-sheet structures, the transistors fabricated in the active-region structures are nano-sheet transistors. The number of nano-sheets in the strong PMOS active-region structure220P having p-channel strong transistors is larger than the number of nano-sheets in the weak PMOS active-region structure230P having p-channel weak transistors, and the number of nano-sheets in the strong NMOS active-region structure220N having n-channel strong transistors is larger than the number of nano-sheets in the weak NMOS active-region structure230N having n-channel weak transistors.

In one example implementation, each of the strong PMOS active-region structure220P and the strong NMOS active-region structure220N has two nano-sheets which have a width of 32 nanometers along the Y-direction, while each of the weak PMOS active-region structure230P and the weak NMOS active-region structure230N has one nano-sheet which has a width of 32 nanometers along the Y-direction.

In another example implementation, each of the strong PMOS active-region structure220P and the strong NMOS active-region structure220N has two nano-sheets which have a width of 32 nanometers along the Y-direction, while each of the weak PMOS active-region structure230P and the weak NMOS active-region structure230N has one nano-sheet which has a width along the Y-direction that is less than 32 nanometers (e.g., 26 nanometers or 19 nanometers).

In still another example implementation, each of the strong PMOS active-region structure220P, the strong NMOS active-region structure220N, the weak PMOS active-region structure230P, and the weak NMOS active-region structure230N has two nano-sheets. The width of the nano-sheets in the strong PMOS active-region structure220P (e.g., 42 nanometers) is larger than the width of the nano-sheets in the weak PMOS active-region structure230P (e.g., 32 nanometers), and the width of the nano-sheets in the strong NMOS active-region structure220N (e.g., 30 nanometers) is larger than the width of the nano-sheets in the weak NMOS active-region structure230N (e.g., 16 nanometers).

In some embodiments, when the active-region structures are formed with nano-wire structures, the transistors fabricated in the active-region structures are nano-wire transistors. The number of nano-wires in the strong PMOS active-region structure220P having p-channel strong transistors is larger than the number of nano-wires in the weak PMOS active-region structure230P having p-channel weak transistors, and the number of nano-wires in the strong NMOS active-region structure220N having n-channel strong transistors is larger than the number of nano-wires in the weak NMOS active-region structure230N having n-channel weak transistors.

In some embodiments, each of the active-region structures is characterized with a structure-width measured along the Y-direction which is perpendicular to the X-direction. The structure-width of the strong PMOS active-region structure220P having p-channel strong transistors is larger than the structure-width of the weak PMOS active-region structure230P having p-channel weak transistors, and the structure-width of the strong NMOS active-region structure220N having n-channel strong transistors is larger than the structure-width of the weak NMOS active-region structure230N having n-channel weak transistors. As one specific example, in some embodiments, when the number of fins in the strong PMOS active-region structure220P is larger than the number of fins in the weak PMOS active-region structure230P, the structure-width of the strong PMOS active-region structure220P is also larger than the structure-width of the weak PMOS active-region structure230P; when the number of fins in the strong NMOS active-region structure220N is larger than the number of fins in the weak NMOS active-region structure230N, the structure-width of the strong NMOS active-region structure220N is also larger than the structure-width of the weak NMOS active-region structure230N.

InFIG.2, for driving the first clocked forwarding-switch103(e.g., the transmission gate110F1), the in-phase clock signal CPBB is applied to a gate-conductor272F1intersecting the strong PMOS active-region structure220P, and the inverted clock signal CPB is applied to a gate-conductor274F1intersecting the strong NMOS active-region structure220N. For driving the clocked inverter110F2, the in-phase clock signal CPBB is applied to a gate-conductor272F2intersecting the weak NMOS active-region structure230N, and the inverted clock signal CPB is applied to a gate-conductor274F2intersecting the weak PMOS active-region structure230P. The output of the first clocked forwarding-switch103(e.g., the transmission gate110F1) is conductively connected to the output of the clocked inverter110F2through a connection conductor250extending in the Y-direction.

InFIG.2, for driving the second clocked forwarding-switch105(e.g., the gated inverter105H1or the transmission gate110H1), the in-phase clock signal CPBB is applied to a gate-conductor272H1intersecting the strong NMOS active-region structure220N, the inverted clock signal CPB is applied to a gate-conductor274H1intersecting the strong PMOS active-region structure220P. For driving the clocked inverter110H2, the in-phase clock signal CPBB is applied to a gate-conductor272H2intersecting the weak PMOS active-region structure230P, and the inverted clock signal CPB is applied to a gate-conductor274H2intersecting the weak NMOS active-region structure230N. The output of the second clocked forwarding-switch105(e.g., the gated inverter105H1or the transmission gate110H1) is conductively connected to the output of the clocked inverter110H2through a connection conductor260extending in the Y-direction.

FIGS.3A-3D,FIGS.4A-4D, andFIGS.5A-5Dare schematics of the cross-sectional views in various cutting planes of the integrated circuit inFIG.2, in accordance with some embodiments. In the cross-sectional views of the cutting plane A-A′, as shown inFIG.3A,FIG.4AandFIG.5A, the gate-conductors272F1and274H1intersect the strong PMOS active-region structure220P correspondingly at the p-channel regions of strong transistors TpF1and TpH1. In the cross-sectional views of the cutting plane B-B′, as show inFIG.3B,FIG.4BandFIG.5B, each of the gate-conductors274F1and272H1intersects the strong NMOS active-region structure220N correspondingly at the n-channel region of strong transistors TnF1and TnH1. In the cross-sectional views of the cutting plane C-C′, as show inFIGS.3C-5C, the gate-conductors272F2and274H2intersect the weak NMOS active-region structure230N correspondingly at the n-channel regions of weak transistors TnF2and TnH2. In the cross-sectional views of the cutting plane D-D′, as show inFIGS.3D-5D, each of the gate-conductors274F2and272H2intersects the weak PMOS active-region structure230P correspondingly at the p-channel regions of weak transistors TpF2and TpH2.

In some embodiments, as shown inFIGS.3A-3D, the connection conductor250and the connection conductor260are correspondingly implemented as terminal-conductors350MD and360MD. The terminal-conductor350MD intersects the strong active-region structures220P and220N correspondingly at the drain regions of the strong transistors TpF1and TnF1. The terminal-conductor350MD also intersects the weak active-region structures230N and230P correspondingly at the drain regions of the weak transistors TnF2and TpF2. The terminal-conductor360MD intersects the strong active-region structures220P and220N correspondingly at the drain regions of the strong transistors TpH1and TnH1. The terminal-conductor360MD also intersects the weak active-region structures230N and230P correspondingly at the drain regions of the weak transistors TnH2and TpH2. The terminal-conductors350MD and360MD are covered with an interlayer dielectric ILD0, and a first metal layer (e.g., metal layer M0) having conducting lines is deposited on the interlayer dielectric ILD0. The interlayer dielectric ILD0also covers various gate-conductors.

In some embodiments, as shown inFIGS.4A-4D, the connection conductor250and the connection conductor260are implemented as vertical conducting lines450M0and460M0extending along the Y-direction in a first metal layer (e.g., metal layer M0) that is deposited on the interlayer dielectric ILD0(which covers various gate-conductors and terminal-conductors). In some embodiments, as shown inFIGS.5A-5D, the connection conductor250and the connection conductor260are implemented as vertical conducting lines550M1and560M1extending along the Y-direction in a second metal layer (e.g., metal layer M1) that is deposited on the interlayer dielectric ILD1(which covers various conducting lines in the first metal layer).

InFIG.4AandFIG.5A, the terminal-conductors dTpF1and dTpH1intersect the strong PMOS active-region structure220P correspondingly at the drain regions of the transistors TpF1and TpH1. InFIG.4BandFIG.5B, the terminal-conductors dTnF1and dTnH1intersect the strong NMOS active-region structures220N correspondingly at the drain regions of the strong transistors TnF1and TH1. InFIG.4CandFIG.5C, the terminal-conductors dTnF2and dTnH2intersect the weak NMOS active-region structures230N correspondingly at the drain regions of the weak transistors TnF2and TnH2. InFIG.4DandFIG.5D, the terminal-conductors dTpF2and dTpH2intersect the weak PMOS active-region structures230P correspondingly at the drain regions of the weak transistors TpF2and TpH2.

InFIGS.4A-4D, the vertical conducting lines450M0and460M0extending in the Y-direction are in the first metal layer (e.g., metal layer M0). The vertical conducting line450M0is conductively connected to the terminal-conductors dTpF1, dTnF1, dTnF2, and dTpF2with via connectors VD passing through the interlayer dielectric ILD0. The vertical conducting line460M0is conductively connected to the terminal-conductors dTpH1, dTnH1, dTnH2, and dTpH2with via connectors VD passing through the interlayer dielectric ILD0.

InFIGS.5A-5D, the vertical conducting lines550M1and560M1extending in the Y-direction are in the second metal layer (e.g., metal layer M1). The vertical conducting line550M1is consecutively connected to the terminal-conductors dTpF1, dTnF1, dTnF2, and dTpF2through a first set of metal stubs in the first metal layer (e.g., metal layer M0), and the vertical conducting line560M1is conductively connected to the terminal-conductors dTpH1, dTnH1, dTnH2, and dTpH2through a second set of metal stubs in the first metal layer (e.g., metal layer M0).

Specifically, the vertical conducting line550M1is conductively connected to the metal stubs m50pF1, m50nF1, m50nF2, and m50pF2with via connectors V0passing through the interlayer dielectric ILD1, while each of the metal stubs m50pF1, m50nF1, m50nF2, and m50pF2is conductively connected to one of the terminal-conductors dTpF1, dTnF1, dTnF2, and dTpF2correspondingly with a via connector VD passing through the interlayer dielectric ILD0. Similarly, the vertical conducting line560M1is conductively connected to the metal stubs m60pH1, m60nH1, m60nH2, and m60pH2with via connectors V0passing through the interlayer dielectric ILD1, while each of the metal stubs m60pH1, m60nH1, m60nH2, and m60pH2is conductively connected to one of the terminal-conductors dTpH1, dTnH1, dTnH2, and dTpH2correspondingly with a via connector VD passing through the interlayer dielectric ILD0.

In the embodiments ofFIG.2, class-one devices (such as, the first clocked forwarding-switch103and the second clocked forwarding-switch105) are constructed with p-channel strong transistors and n-channel strong transistors. The p-channel strong transistors are fabricated in the strong PMOS active-region structure220P and the n-channel strong transistors are fabricated in the strong NMOS active-region structure220N. In some alternative embodiments, the p-channel strong transistors for constructing class-one devices are fabricated in at least two strong PMOS active-region structures. In some alternative embodiments, the n-channel strong transistors for constructing class-one devices are fabricated in at least two strong NMOS active-region structures.

FIG.6is a floor plan of the integrated circuits100A-100C in FIGS.1A1-1C1and FIGS.1A2-1C2, in accordance with some embodiments. The integrated circuits inFIG.6includes two strong PMOS active-region structures220P [1]-220P [2] extending in the X-direction, two strong NMOS active-region structure220N [1]-220N [2] extending in the X-direction, a weak PMOS active-region structure230P extending in the X-direction, and a weak NMOS active-region structure230N extending in the X-direction. Each of the input device101, the first clocked forwarding-switch103, the second clocked forwarding-switch105, and the output driver109(correspondingly in the layout areas “D”, “F1”, “F2”, and “J”) is constructed with p-channel strong transistors in the strong PMOS active-region structures220P [1]-220P [2] and with n-channel strong transistors in the NMOS active-region structures220N [1]-220N [2]. Each of the clocked inverter110F2and the clocked inverter110H2(correspondingly in the layout areas “F2” and “H2”) is constructed with p-channel weak transistors in the weak PMOS active-region structure230P and with n-channel weak transistors in the weak NMOS active-region structure230N.

InFIG.6, for driving the first clocked forwarding-switch103(e.g., the transmission gate110F1), the in-phase clock signal CPBB is applied to the gate-conductors272F1[1]-272F1 [2], and the inverted clock signal CPB is applied to the gate-conductors274F1[1]-274F1 [2]. For driving the second clocked forwarding-switch105(e.g., the gated inverter105H1or the transmission gate110H1), the in-phase clock signal CPBB is applied to the gate-conductors272H1[1]-272H1[2], and the inverted clock signal CPB is applied to the gate-conductors274H1[1]-274H1[2].

InFIG.6, for driving the clocked inverter110F2and the clocked inverter110H2, the in-phase clock signal CPBB and the inverted clock signal CPB are applied to various gate-conductors in the same way as inFIG.2. Additionally, in bothFIG.6andFIG.2, the output of the first clocked forwarding-switch103is conductively connected to the output of the clocked inverter110F2through the connection conductor250, and the output of the second clocked forwarding-switch105is conductively connected to the output of the clocked inverter110H2through the connection conductor260.

InFIG.6, two strong transistors with the gate-conductors272F1[1]-272F1[2] are parallelly connected with each other and two strong transistors with the gate-conductors274F1[1]-274F1[2] are parallelly connected with each other. The two strong transistors with the gate-conductors272F1[1]-272F1[2] substitute the strong transistor TpF1with the gate-conductor272F1inFIG.2, and the two strong transistors with the gate-conductors274F1[1]-274F1[2] substitute the strong transistor TnF1with274F1inFIG.2, thereby the driving strength at the output of the first clocked forwarding-switch103inFIG.6is increased. Here, increasing the driving strength of the first clocked forwarding-switch103improves the switching speed of the master-slave flip-flop implemented according to the floor design ofFIG.6.

Similarly, inFIG.6, two strong transistors with the gate-conductors272H1[1]-272H1[2] are parallelly connected with each other and two strong transistors with the gate-conductors274H1[1]-274H1[2] are parallelly connected with each other. The two strong transistors with the gate-conductors272H1[1]-272H1[2] substitute the strong transistor TnH1with the gate-conductor272H1inFIG.2, and the two strong transistors with the gate-conductors274H1[1]-274H1[2] substitute the strong transistor TpH1with the gate-conductor274H1inFIG.2, thereby the driving strength at the output of the second clocked forwarding-switch105inFIG.6is increased. Here, increasing the driving strength of the second clocked forwarding-switch105improves the switching speed of the master-slave flip-flop implemented according to the floor design ofFIG.6.

Additionally, because of the two strong PMOS active-region structures220P [1]-220P [2] and the two strong NMOS active-region structures220N [1]-220N [2], more strong transistors are available for constructing the input device101and the output driver109(which are correspondingly in layout areas “D” and “J”) to increase the driving strengths of the input device101and the output driver109. Increasing the driving strength at the output of the input device101improves the switching speed of the master-slave flip-flops in FIGS.1A1-1C1and FIGS.1A2-1C2implemented according to the floor design ofFIG.6. Increasing the driving strength at the output of the output driver109decreases the RC delay at the output of the output driver109.

In some alternative embodiments, the integrated circuits implemented according to the floor design ofFIG.6are modified, whereby some of the strong active-region structure are merged.FIG.7is a floor plan of the integrated circuits100A-100C in FIGS.1A1-1C1and FIGS.1A2-1C2, in accordance with some embodiments. The strong PMOS active-region structure220Pm inFIG.7is obtained by merging the strong PMOS active-region structures220P [1] and220P [2] inFIG.6. Furthermore, the gate-conductors272F1[1] and272F1[2] are substituted with a merged gate-conductor272F1m, and the gate-conductors274H1[1] and274H1[2] are substituted with a merged gate-conductor274H1m.

InFIG.6, the strong PMOS active-region structures220P [1] and220P [2] are adjacent to each other, and the strong PMOS active-region structures220P [1] and220P [2] are positioned between the two strong NMOS active-region structures220N [1] and220N [2]. In some alternative embodiments (not shown in figures), the strong NMOS active-region structures220N [1] and220N [2] are adjacent to each other, and the strong NMOS active-region structures220N [1] and220N [2] are positioned between the two strong PMOS active-region structures220P [1] and220P [2]. In some alternative embodiments (not shown in figures), the strong NMOS active-region structures220N [1] and220N [2] are merged as one strong NMOS active-region structure220Nm, which is positioned between the two strong PMOS active-region structures220P [1] and220P [2].

FIG.8is a flowchart of a method800of fabricating an integrated circuit, in accordance with some embodiments. The sequence in which the operations of method800are depicted inFIG.8is for illustration only; the operations of method800are capable of being executed in sequences that differ from that depicted inFIG.8. It is understood that additional operations may be performed before, during, and/or after the method800depicted inFIG.8, and that some other processes may only be briefly described herein.

In operation810of method800, a strong type-one active-region structure and a weak type-one active-region structure extending in the X-direction are fabricated. In operation820of method800, a strong type-two active-region structure and a weak type-two active-region structure extending in the X-direction are fabricated. In the example embodiments as shown inFIG.2andFIGS.3A-3D, the strong PMOS active-region structure220P and the weak PMOS active-region structure230P are fabricated in operation810(or alternatively in operation820), and the strong NMOS active-region structure220N and the weak NMOS active-region structure230N are fabricated in operation820(or alternatively in operation810). After operations810and820, the fabrication process proceeds to operation830and840.

In operation830of method800, a first clocked forwarding-switch and a second clocked forwarding-switch are formed with strong type-one transistors in the strong type-one active-region structure and strong type-two transistors in the strong type-two active-region structure. In the example embodiments as shown inFIG.2andFIGS.3A-3D, the first clocked forwarding-switch F1and the second clocked forwarding-switch F2are formed with strong PMOS transistors in the strong PMOS active-region structure220P and strong NMOS transistors the strong NMOS active-region structure220N. In operation840of method800, a first clocked inverter and a second clocked inverter are formed with weak type-one transistors in the weak type-one active-region structure and weak type-two transistors in the weak type-two active-region structure. In the example embodiments as shown inFIG.2andFIGS.3A-3D, the clocked inverter110F2and the clocked inverter110H2are formed with weak PMOS transistors in the weak PMOS active-region structure230P and weak NMOS transistors in the weak NMOS active-region structure230N. After operations830and840, the fabrication process proceeds to operation850and860.

In operation850of method800, an output of the first clocked forwarding-switch is connected with an output of the first clocked inverter. In operation860of method800, an output of the second clocked forwarding-switch is connected with an output of the second clocked inverter. In a first example embodiment as shown inFIG.2andFIGS.3A-3D, when the terminal-conductor350MD is fabricated intersecting the strong active-region structures (i.e.,220P and220N) and the weak active-region structures (i.e.,230P and230N), the output of the first clocked forwarding-switch F1is connected with the output of the first clocked inverter F2. When the terminal-conductor360MD is fabricated intersecting the strong active-region structures (i.e.,220P and220N) and the weak active-region structures (i.e.,230P and230N), the output of the second clocked forwarding-switch H1is connected with the output of the second clocked inverter H2.

In another example embodiment as shown inFIG.2andFIGS.4A-4D, as the vertical conducting line450M0is fabricated in operation860, the vertical conducting line450M0is fabricated connected to each of the terminal-conductors dTpF1, dTnF1, dTnF2, and dTpF2with a via connector, whereby the output of the first clocked forwarding-switch F1is connected with the output of the first clocked inverter F2. As the vertical conducting line460M0fabricated, the vertical conducting line460M0is connected to each of the terminal-conductors dTpH1, dTnH1, dTnH2, and dTpH2with a via connector VD, whereby the output of the second clocked forwarding-switch H1is connected with the output of the second clocked inverter H2.

FIG.9is a block diagram of an electronic design automation (EDA) system900in accordance with some embodiments.

In some embodiments, EDA system900includes an automatic placement and routing (APR) system. Methods described herein of designing layout diagrams represent wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system900, in accordance with some embodiments.

In some embodiments, EDA system900is a general purpose computing device including a hardware processor902and a non-transitory, computer-readable storage medium904. Storage medium904, amongst other things, is encoded with, i.e., stores, computer program code906, i.e., a set of executable instructions. Execution of instructions906by hardware processor902represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods).

Processor902is electrically coupled to computer-readable storage medium904via a bus908. Processor902is also electrically coupled to an I/O interface910by bus908. A network interface912is also electrically connected to processor902via bus908. Network interface912is connected to a network914, so that processor902and computer-readable storage medium904are capable of connecting to external elements via network914. Processor902is configured to execute computer program code906encoded in computer-readable storage medium904in order to cause system900to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor902is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, storage medium904stores computer program code906configured to cause system900(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium904also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium904stores library907of standard cells including such standard cells as disclosed herein. In one or more embodiments. storage medium904stores one or more layout diagrams909corresponding to one or more layouts disclosed herein.

EDA system900also includes network interface912coupled to processor902. Network interface912allows system900to communicate with network914, to which one or more other computer systems are connected. Network interface912includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems900.

System900is configured to receive information through I/O interface910. The information received through I/O interface910includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor902. The information is transferred to processor902via bus908. EDA system900is configured to receive information related to a user interface (UI) through I/O interface910. The information is stored in computer-readable medium904as UI942.

InFIG.10, IC manufacturing system1000includes entities, such as a design house1020, a mask house1030, and an IC manufacturer/fabricator (fab)1050, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1060. The entities in system1000are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1020, mask house1030, and IC fab1050is owned by a single larger company. In some embodiments, two or more of design house1020, mask house1030, and IC fab1050coexist in a common facility and use common resources.

Design house (or design team)1020generates an IC design layout diagram1022. IC design layout diagram1022includes various geometrical patterns designed for an IC device1060. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1060to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram1022includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1020implements a proper design procedure to form IC design layout diagram1022. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram1022is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1022can be expressed in a GDSII file format or DFII file format.

Mask house1030includes data preparation1032and mask fabrication1044. Mask house1030uses IC design layout diagram1022to manufacture one or more masks1045to be used for fabricating the various layers of IC device1060according to IC design layout diagram1022. Mask house1030performs mask data preparation1032, where IC design layout diagram1022is translated into a representative data file (RDF). Mask data preparation1032provides the RDF to mask fabrication1044. Mask fabrication1044includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1045or a semiconductor wafer1053. The design layout diagram1022is manipulated by mask data preparation1032to comply with particular characteristics of the mask writer and/or requirements of IC fab1050. InFIG.10, mask data preparation1032and mask fabrication1044are illustrated as separate elements. In some embodiments, mask data preparation1032and mask fabrication1044can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation1032includes a mask rule checker (MRC) that checks the IC design layout diagram1022that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1022to compensate for photolithographic implementation effects during mask fabrication1044, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation1032includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab1050to fabricate IC device1060. LPC simulates this processing based on IC design layout diagram1022to create a simulated manufactured device, such as IC device1060. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram1022.

It should be understood that the above description of mask data preparation1032has been simplified for the purposes of clarity. In some embodiments, data preparation1032includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1022according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1022during data preparation1032may be executed in a variety of different orders.

After mask data preparation1032and during mask fabrication1044, a mask1045or a group of masks1045are fabricated based on the modified IC design layout diagram1022. In some embodiments, mask fabrication1044includes performing one or more lithographic exposures based on IC design layout diagram1022. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1045based on the modified IC design layout diagram1022. Mask1045can be formed in various technologies. In some embodiments, mask1045is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask1045includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask1045is formed using a phase shift technology. In a phase shift mask (PSM) version of mask1045, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1044is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer1053, in an etching process to form various etching regions in semiconductor wafer1053, and/or in other suitable processes.

IC fab1050includes fabrication tools1052configured to execute various manufacturing operations on semiconductor wafer1053such that IC device1060is fabricated in accordance with the mask(s), e.g., mask1045. In various embodiments, fabrication tools1052include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

An aspect of the present disclosure relates to an integrated circuit. The integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors and includes a first clocked inverter and a second clocked inverter each implemented with weak transistors. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter. The integrated circuit also includes strong active-region structures extending in a first direction and weak active-region structures extending in the first direction. Each of the strong active-region structures has a portion of the strong transistors, and each of the weak active-region structures has a portion of the weak transistors. The integrated circuit further includes a first inverter having an input conductively connected to the output of the first clocked inverter and having an output conductively connected to an input of the first clocked inverter. The integrated circuit still includes a second inverter having an input conductively connected to the output of the second clocked inverter and having an output conductively connected to an input of the second clocked inverter.

Another aspect of the present disclosure relates to an integrated circuit. The integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors and includes a first clocked inverter and a second clocked inverter each implemented with weak transistors. The integrated circuit also includes strong active-region structures extending in a first direction and having the strong transistors therein and weak active-region structures extending in the first direction and having the weak transistors therein. An average gate width of the strong transistors with p-channels is larger than an average gate width of the weak transistors with p-channels, and an average gate width of the strong transistors with n-channels is larger than an average gate width of the weak transistors with n-channels. The integrated circuit further includes a first connection conductor and a second connection conductor each extending in a second direction that is perpendicular to the first direction. The first connection conductor conductively connects an output of the first clocked forwarding-switch with an output of the first clocked inverter. The second connection conductor conductively connects an output of the second clocked forwarding-switch with an output of the second clocked inverter. The integrated circuit still includes a first inverter coupled between an input of the first clocked inverter and the first connection conductor, wherein the first inverter having an input conductively connected to the first connection conductor. The integrated circuit still includes a second inverter coupled between an input of the second clocked inverter and the second connection conductor, wherein the second inverter having an input conductively connected to the second connection conductor.

Still another aspect of the present disclosure relates to a method. The method includes fabricating a strong type-one active-region structure and a weak type-one active-region structure extending in a first direction, and fabricating a strong type-two active-region structure and a weak type-two active-region structure extending in the first direction. The method also includes forming a first clocked forwarding-switch and a second clocked forwarding-switch with strong type-one transistors in the strong type-one active-region structure and strong type-two transistors in the strong type-two active-region structure, and forming a first clocked inverter and a second clocked inverter with weak type-one transistors in the weak type-one active-region structure and weak type-two transistors in the weak type-two active-region structure. An average gate width of the strong type-one transistors is larger than an average gate width of weak type-one transistors, and an average gate width of the strong type-two transistors is larger than an average gate width of weak type-two transistors. The method still includes connecting an output of the first clocked forwarding-switch with an output of the first clocked inverter, and connecting an output of the second clocked forwarding-switch with an output of the second clocked inverter.