Predictive modeling of contact and via modules for advanced on-chip interconnect technology

A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via.

TECHNICAL FIELD

The present disclosure generally relates to semiconductor technology. More specifically, the present disclosure relates to predicting electrical characteristics of semiconductor components, such as on-chip contact or via technology.

BACKGROUND

Interconnect technology, such as contacts and vias, has become increasingly important for designing integrated circuits (ICs) (also referred to as chips). Interconnects are part of the back-end-of-the-line (BEOL) processing in multi-layered semiconductor devices. On-chip interconnect technology distributes clock and data signals as well as power and ground signals to various functional blocks in an IC. As the IC designs become smaller and more compact, the size, dimensions, materials, and positioning of interconnect structures become increasingly significant factors in overall performance.

As seen inFIG. 2, front end of line (FEOL) processing results in semiconductor components20, such as transistor elements (e.g., gates), on a semiconductor substrate. Back end of line (BEOL) processing results in BEOL structures, such as contacts22, and vias24,26, as well as conductive layers M1, M2, M3including conductive traces.

The contact and via resistances become a growing concern as device dimensions continue to shrink, where they are a significant fraction of the total local line resistance. As such, the delay associated with the signals traveling through the contacts and vias becomes a significant portion of the overall delay of the local interconnection of the IC.

Modeling tools are used by IC designers to estimate the resistance properties of complex interconnect systems, including structures such as the contact and via. Conventional modeling tools perform high-level simulations using finite element method calculations for the interconnect structure. However, existing modeling tools measure models of the contacts and vias based on average resistivity, thus providing an incomplete assessment of the total resistance.

Another characteristic of existing modeling tools is their requirement to recreate a simulation environment for a different technology node. Since existing modeling tools conventionally extract coefficients from existing silicon data (i.e., the coefficients are dependent on the physical dimensions), it is difficult to skew and scale with physical dimensions because the coefficients are restricted to simulating the contacts and vias for only a specific technology node and specific dimensions.

Further, employing existing modeling tools to extract resistance results occurs late in the development cycle, because the actual silicon data is available towards the end of the development cycle. As a result, changes to designs based on the results from the modeling tools delay the development cycle.

For the foregoing reasons, there is a need for providing a more physical scalable and accurate model of contacts and vias earlier in the development cycle.

SUMMARY

The present disclosure is directed to a computer software program that satisfies the need of providing a more physical, scaleable and accurate model of the contact/via earlier in the development cycle than conventional projections. In accordance with the present disclosure, the computer software program provides performance predictions in future technology generations based on a relationship between a model and existing wafer data by deriving values of the model's coefficients using the existing wafer data. The computer software program begins execution of a method to model an on-chip interconnect by providing physical dimensions of a contact/via in an existing semiconductor wafer for an existing technology node. The physical dimensions of the contact/via provide a starting point in developing a model of the contact/via. The information about the physical dimensions can be entered into a third party interconnect analysis tool, such as the RAPHAEL tool by SYNOPSYS. This tool simulates the contact/via as developed in the existing semiconductor wafer and extracts specific measurements about its electrical characteristics, such as resistance data.

The method includes generating the model, which is provided by a set of equations defining a possible contact/via similar to the contact/via in the existing wafer. The set of equations include computations of scattering effects that increase resistivity as device dimensions shrink. The set of equations also include information about the angular shape of the possible contact/via. More importantly, the model can predict both the physical dimensions and performance of the possible contact/via across multiple technology nodes. The set of equations includes a set of coefficients, which can be configured as constant factors that allows the model to be employed constantly across multiple technology nodes. In other words, the model can analytically represent the possible contact/via in more than one technology node by accepting multiple physical dimension inputs without the need of recreating the simulation environment.

In one aspect, a computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). The computer program product is tangibly stored on a computer-readable medium, and includes code executing on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure.

In another aspect, a system estimates performance of a BEOL structure of a semiconductor integrated circuit (IC). The system includes means for dynamically predicting resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure.

DETAILED DESCRIPTION

A detailed description of one or more embodiments is provided below along with accompanying figures that illustrate the principles of the embodiments. The scope of the embodiments is limited only by the claims and encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description. These details are provided solely for the purposes of example and the embodiments may be practiced according to the claims without some or all of these specific details.

FIG. 1shows an exemplary wireless communication system100in which an embodiment of the disclosure may be advantageously employed. For purposes of illustration,FIG. 1shows three remote units120,130, and150and two base stations140. It will be recognized that conventional wireless communication systems may have many more remote units and base stations. Remote units120,130, and150include semiconductor devices125A,125B and125C, which are embodiments of the disclosure as discussed further below.FIG. 1shows forward link signals180from the base stations140and the remote units120,130, and150and reverse link signals190from the remote units120,130, and150to base stations140.

InFIG. 1, a remote unit120is shown as a mobile telephone, a remote unit130is shown as a portable computer, and a remote unit150is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, navigation devices (such as GPS enabled devices), set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. AlthoughFIG. 1illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. Embodiments of the disclosure may be suitably employed in any device which includes integrated circuitry and associated interconnect technology.

The foregoing disclosed devices and methods are commonly designed and configured into a hardware description language, such as VHDL and Verilog computer files, stored on a computer-readable media. These files are in turn provided to fabrication handlers who fabricate devices based on these files. The resulting products are semiconductor wafers that are then cut into semiconductor die and packaged. The packaged die are employed in the devices described above.

FIG. 3is a block diagram illustrating across section view of an exemplary back end of line (BEOL) structure200. The BEOL structure200can be a contact or a via having a generally cylindrical shape with a circular cross section. For the purposes of predicting resistance of various configurations of BEOL structures, two layers are considered: an outer liner30, and an inner filler32. The liner30is the portion of the BEOL structure200between the inner filler32(often a conductive material such as a metal) and an oxide (not shown) that acts as an isolation barrier to protect the inner filler32(o(ten a conductive material such as a metal).

In order to increase the accuracy of the prediction, a slope profile of the BEOL structure is considered. That is, the top radius r1differs from the bottom radius r2, resulting in an angle θ (discussed below) that is not 90 degrees. The slope profile is associated with the angle θ.

Finally, the prediction considers the electron scattering effect of the inner filler material of the BEOL structure. Scattering effects are based upon grain size and edge roughness of the BEOL structure. As interconnects continue to shrink, the scattering effect has an increasing effect on resistivity. Thus, a model that accounts for the scatter effect is more accurate when evaluating future technology nodes. That is, whenever scaling the width of the BEOL structure, resistivity increases and the prediction reflects such increases.

The equation to determine the width dependent resistivity, ρ1, is:
ρ1=ρ10(1+d1/W)  (1)where ρ10is the bulk resistivity,d1is the normalized coefficient that relates the resistivity with the variations in width caused by scattering effects of the specific material, andW is the width of the structure.

In the case of doped copper, equation (1) simplifies to:
2.1+32e−9/W(m)(μ-Ωcm)  (2)where 2.1 is the known bulk resistivity of the doped copper material, andW is the width of the structure.

For other materials, such as tungsten, the bulk resistivity, ρ10, and the material coefficient, d1, can be obtained from known sources.

According to an aspect of the disclosure, a model is provided for predicting contact and via resistance. The model accounts for the slope profile of the BEOL structure. To account for the slope of the BEOL structure, the angle θ is defined based upon the following equation:

tan⁢⁢θ=Hr1-r2=2⁢⁢HD1-D2(3)where H is the height,r1is the top radius,r2is the bottom radius,D1is the top diameter, andD2is the bottom diameter.

An effective width, CDeff, is defined as:

CDeff=CDtop+CDbottom2(4)where CDtop(also referred to as Top CD) is the top width, including the liner thickness, andCDbottom(also referred to as Bottom CD) is the bottom width, including the liner thickness.

Deff=Dtop+Dbottom2⇔reff=rtop+rbottom2(5)where Dtop(or D1) is the top diameter, excluding the liner thickness,Dbottom(or D2) is the bottom diameter, excluding the liner thickness,rtop(or r1) is the top radius, excluding the liner thickness, andrbottom(or r2) is the bottom radius, excluding the liner thickness.

The effective width, CDeff, can also be defined as:
CDeff=Deff+2Tt=2reff+2Tt(6)where Ttis the liner thickness,Deffis the effective diameter, andreffis the effective radius.

Inline measurement generally allows measuring of the top of a BEOL structure, whereas measuring the bottom of a BEOL structure can be difficult. Thus, in another embodiment the effective width is defined based upon the top effective width as:
CDeff=2(reff+Tt)=CDt−Htgθ(6a)where reffis the effective radius (excluding the liner)Ttis the liner thickness,CDtis the top effective width,H is the height of the BEOL structure,θ is the slope angle.

The effective width, CDeff, or the effective diameter, Deff, is used to model the BEOL structure, as discussed in more detail.

The width dependent resistivity, ρ1, equation (equation (1)) can be modified to be based upon the diameter, D, or the radius, r, as follows:

ρ1=ρ10⁡(1+d2D)=ρ10⁡(1+d3r)(7)where ρ10is the bulk resistivity,d2the material coefficient is equal to 2d3,D is the effective diameter, andR is the effective radius.

In order to calculate the overall resistance of the BEOL structure, an inner filling material resistance, a bottom resistance, and a liner resistance should be calculated.

The inner filling material resistance calculation will now be discussed. In one embodiment, the inner material for via structures is copper, and for contact structures the material is tungsten. In order to obtain the inner filling material resistance, the bulk resistivity, ρ10, and the width coefficient, d3, corresponding to the material are determined.

In addition, an incremental inner filling resistivity, ΔR1, is defined. The incremental inner filling resistivity, ΔR1, represents a thin piece of the resistivity of the BEOL structure. An incremental distance, Δy, is also defined to enable analysis of thin cylindrical slices of the BEOL structure. The incremental inner filling resistivity, ΔR1, is defined as:

The incremental inner filling resistivities, ΔR1, of each slice are summed by integrating over the height of the BEOL structure from the top to the bottom. It is noted that the inner filling material resistivity accounts for the surface scatter effect.

An outer liner metal resistance, ΔR2, is also defined. The outer liner metal resistance, ΔR2, does not account for any scatter effect. Such an assumption is realistic due to the fact that the liner is quite thin. Thus the width dependent resistivity, ρ2, is set equal to the bulk resistivity, ρ20. The outer liner resistivity, ΔR2, is defined as:

The incremental liner resistivities, ΔR2, of each slice are summed by integrating over the height of the BEOL structure from the top to the bottom. It is noted that the liner material resistivity does not account for the surface scatter effect.

The bottom of the BEOL structure is actually a portion of the liner. Thus, the bottom liner resistance, Rbottom, is derived as:

Rbottom=ρ2⁢Ttπ⁡(r2+Tt)2≈ρ2⁢Ttπ⁡(reff+Tt)2(10)where ρ2is the bulk resistivity (without scatter effect),Ttis the liner thickness,r2is the bottom radius, andreffis the effective radius.

By integrating the incremental inner filling resistivity, ΔR1, and the outer liner resistivity, ΔR2, the effective incremental resistance, ΔR, can be obtained. To calculate the effective incremental resistance, ΔR. an effective liner coefficient, d4, is defined as
d4=ρ10/ρ2*Tt(11)where ρ10is the bulk resistivity,ρ2is the liner bulk resistivity, andTtis the liner thickness.

In order to calculate the integral, the effective incremental resistance, ΔR, is defined. The effective incremental resistance, ΔR, is defined as:

Because of the computational complexity of integrating equation (12), a cylinder can be assumed (as seen inFIG. 4) to approximate the shape of the BEOL structure. Thus, an effective resistance, Reff, based upon the cylinder approximation is defined as:

Equation (13) can be simplified when ρ1is close to ρ2, i.e., the inner width dependent resistivity, ρ1, is increased to the liner bulk resistivity, ρ2, as:

R=Reff≈ρ1⁢Hπ⁡(reff+Tt)2(14)(if ρ1≈ρ2, inner width effect increase ρ1close to ρ2)where Reffis the effective resistanceρ1is the inner material width dependent resistivity,H is the height of the BEOL structure,reffis the effective radius, andTtis the liner thickness.

A general total resistance of the BEOL structure can then be defined as:

Rtotal=⁢Reff+Rbottom=⁢ρ1⁢Hπ⁡(reff2+(2⁢reff+Tt)⁢Tt⁢ρ1ρ2)+ρ2⁢Ttπ⁡(r2+Tt)2(15)where Reffis the effective resistance,Rbottomis the bottom liner resistance,ρ1is the inner material width dependent resistivity,H is the height of the BEOL structure,r2is the bottom radius,Ttis the liner thickness, andρ2is the liner bulk resistivity.

Equation (15) can be simplified when the inner material width dependent resistivity, ρ1, is approximately equal to the outer material bulk resistivity, ρ2. The simplified equation is:

Rtotal=Reff+Rbottom≈4⁢(ρ1⁢H+ρ2⁢Tt)π⁢⁢CDeff2(16)where Reffis the effective resistance,Rbottomis the bottom liner resistance,ρ1is the inner material width dependent resistivity,H is the height of the BEOL structure,ρ2is the liner bulk resistivity,Ttis the liner thickness, andCDeffis the effective width.

In one embodiment the simplified equation (i.e., equation (16) is sufficiently accurate, even when the inner material width dependent resistivity, ρ1, is not similar to the liner material bulk resistivity, ρ2. Consequently, the resistance for a BEOL structure can be determined based on the inner material width dependent resistivity, ρ1, the liner material bulk resistivity, ρ2, the height of the BEOL structure, H, the effective width, CDeff, and the liner thickness, Tt. As noted above, in one embodiment, the inner material width dependent resistivity, ρ1, accounts for the width scatter effect.

Based upon the general total resistivity model of equation (16), a specific resistivity model can be derived for a particular foundry. The specific resistivity model includes constant coefficients that can be derived for each specific foundry or in the case manufacturing processes or processing conditions (e.g., film properties) significantly differ. The equation for the specific resistivity, Rspecific, is as follows:

In one embodiment, the bottom radius, r2, is approximated as the effective radius, reff. In this case the following simplified equation can be used (especially when the inner material width dependent resistivity, ρ1, is close to the liner material bulk resistivity, ρ2:

Rspecific≈a3(ρ1⁢H+ρ2⁢TtCDeff2)+b3⁢(if⁢⁢ρ1≈ρ2)(18)where ρ1is the inner material width dependent resistivity,H is the height of the BEOL structure,ρ2is the liner bulk resistivity,Ttis the liner thickness,CDeffis the effective width,a3is a constant coefficient correlated to slope profile and process related information, andb3is a constant coefficient correlated to material and interface resistance.

It is noted that even when the inner material width dependent resistivity, ρ1, is not close to the liner material bulk resistivity, ρ2, the resulting error is small, based upon actual data analysis. However, in some applications such as when scaling to smaller dimensions, it may be desirable to use equation (17) (i.e., non-simplified version).

Derivation of the coefficient values a2, a3, b2, b3will now be explained with reference to the process500ofFIG. 5. Initially, at block510general technology scaling information is input. For example, the general dimensions and material are received. Then, at block520typical dimensions, such as thickness and other dimensions of the BEOL structure, as well as the typical resistance information of the inner and outer materials are received. At block530corner information of the thickness and other dimensions of the BEOL structure, as well as the corner resistance information of the inner and outer materials are received.

At block540the inner material width dependent resistivity, ρ1, is determined. Then, at block550the coefficients a2, a3, b2, b3are extracted based upon actual past data (e.g., silicon data). That is, actual data is used to fit the equation. If the error is determined to be unacceptable at block570, the coefficients are tuned at block560, and the process returns to block550. If the error is acceptable (less than 5%-10% in one embodiment), at block570, the process ends.

Thus, according to an aspect of the present disclosure a methodology for extracting analytical models for scaling BEOL structures (such as a contact or via) considers a liner width, the width scatter effect, and the slope profile of the BEOL structure. A general model can be fitted for particular foundries based on actual foundry data. Once fitted, different input conditions (e.g., different height or liner thickness, etc.) can be provided for different BEOL structures and the expected resistance of the BEOL structures can be predicted. Thus, the effects of various changes to the BEOL structure can be predicted, i.e., contact and via variability studies are enabled as technology scales.

Some advantages to take note from the analytical representation of the projection model are that multiple foundries (or semiconductor fabrication vendors) may adopt the projection model to either define or provide production input parameters for the production (or fabrication) of interconnect structures. The projection model can provide data points representative of design trends and/or performance trends for interconnects in technology nodes not yet in production or in researching stages. Therefore, production delays for the design and development of integrated circuits are substantially eliminated.

The model can calculate one or more data points of performance values. In particular embodiments, the data points may be visually presented, such as with plots, tables, matrices, charts, or other types of visually presented processed data. The data points can present trends in design and performance for experimental interconnects in technology nodes projected for development. Although the model is derived from existing wafer data, delays in modeling proposed interconnect designs or interconnect technology is reduced or eliminated.

As a result of applying the model, estimates in propagation delay of experimental interconnect design choices can be provided, even in advanced technology nodes. In other words, it can be seen how variations in dimension and material composition affect interconnect behavior. In some instances, the results may include alternative designs with proposed physical dimensions to produce a specific performance, such as to lower power consumption or lower propagation delay. Of course, there may be alternative ways to display the results. The model may also update the results substantially concurrently with the receipt of new input data, such as physical dimensions, to provide a timely response without the need to generate a new model when new input data is available. This reduces the amount of time needed to run on-chip interconnect simulations early in the development cycle of integrated circuits.

The model provides a quick estimation of interconnect behavior beyond existing nodes and provides an accurate picture of the effects on performance by shrinking devices. The model accounts for variations in width, which increase the resistance in shrinking devices. Although the model is derived from existing wafer data, thereafter the model simulates interconnects without using existing wafer data therefore not delaying the development cycle. The model, as configured, can be used by multiple foundries manufacturing interconnects with similar materials to explore their best suited options. In addition, the model can provide users with information on manufacturing optimized interconnects.

FIG. 6is a diagram illustrating an exemplary computer system suitable for predicting interconnect behavior relative to technology scaling. The computer system600may be used to implement computer programs, applications, methods, processes, or other software to perform the above-described techniques. The computer system600includes a bus602or other communication mechanism for communicating information, which interconnects subsystems and devices, such as a processor604, a system memory606(e.g., RAM), a storage device608(e.g., ROM), a disk drive610(e.g., magnetic or optical), a communication interface612(e.g., modem or Ethernet card), a display614(e.g., CRT or LCD), an input device616(e.g., keyboard), and a cursor control618(e.g., mouse or trackball).

The computer system600performs specific operations by the processor604executing one or more sequences of one or more instructions stored in the system memory606. Such instructions may be read into the system memory606from another computer readable medium, such as the static storage device608or the disk drive610. In some examples, hard-conductive traced circuitry may be used in place of or in combination with software instructions for implementation.

Moreover, execution of the sequences of instructions may be performed by a single computer system600. According to some examples, two or more computer systems600coupled by a communication link (e.g., LAN, public switched telephone network, or conductive traceless network) may perform the sequence of instructions in coordination with one another. The computer system600may transmit and receive messages, data, and instructions, including program, i.e., application code, through the communication link and the communication interface612. The processor604may execute received program code, stored program code as in a disk drive610, or other non-volatile storage for later execution.

Computer program code for carrying out operations of the present disclosure may be written in any combination of one or more programming languages, include an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to a external computer (for example, through the Internet using an Internet Service Provider). Although the foregoing examples have been described in some detail for purposes of clarity of understanding, the disclosure is not limited to the details provided. There are many alternative ways of implementing the disclosure. The disclosed examples are illustrative and not restrictive.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations could be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specified function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. §112, ¶6. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such alternative environment and later developed processes, machines, manufacture, compositions of matter, means, methods, or steps.