Sense amplifier control

A sense amplifier control system includes a precharge control switch configured to receive a precharge signal. A reference cell is configured to receive a reference word line signal. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.

BACKGROUND

Integrated circuit memory devices typically include an array of memory cells that each store data signals representing one or more bits of data. Access to the memory cells may be controlled during read and write operations by selectively connecting the cell to bit lines in response to a received word line signal. In a read operation, for example, the bit lines may be precharged to a predefined voltage level. When the word line is enabled, a sense amplifier connected to the bit lines senses and outputs the stored data.

DETAILED DESCRIPTION

Integrated circuit memory devices typically include an array of memory cells that each store data signals representing one or more bits of data. Access to the memory cells may be controlled during read and write operations by selectively connecting the cell to bit lines in response to a received word line signal. In a read operation, for example, the bit lines may be precharged to a predefined voltage level. When the word line is enabled, a sense amplifier connected to the bit lines senses and outputs the stored data.

For certain types of memory cells, the bit lines are connected to input nodes of sense amplifiers of corresponding input/output (IO) circuits. Such sense amplifiers include an inverter and a latch circuit. A DC reference current is used to precharge the sense amplifier input node (i.e. the bit line) of a corresponding memory cell to the predetermined voltage level (e.g., VDD) during a precharge phase. In a sensing phase subsequent to the precharge phase, word line signal goes high and the input node voltage level VIN (i.e. the bit line voltage) increases if the data signal stored in the memory cell is logic 0, and decreases if the data signal is logic 1. If VIN is greater than a threshold voltage level, the output of the inverter will be logic 0. If the VIN is less than the threshold voltage, the output of the inverter will be logic 1 and the output of the inverter is latched as the data output signal. Inverter circuits used in such conventional sense amplifiers include a PMOS transistor and an NMOS transistor and as such, consume additional power during sensing because the operation of the inverter uses DC current as well in addition to the DC current used for precharging the bit lines.

Moreover, the latch circuit of the sense amplifier is controlled by a timer circuit. To sense and latch the data signal by the sense amplifier, sufficient time must be allowed for the data signal to fall below the threshold voltage (in the case of logic 1), and the rate at which the bit line voltage falls may vary among the IO circuits. Accordingly, the latching timing needs to correspond to the IOs having the slowest rates during the sensing stage, otherwise some IOs may not properly latch the VIN signal. However, for IOs having faster rates (i.e. VIN falls below the threshold level well before the timer), power is consumed unnecessarily.

Thus, for convention IO circuits both the latch and the timer of the sense amplifier require DC current and consume power. For large or “wide” memory arrays (e.g. arrays having over 256 columns), power consumption can be significant.

In accordance with aspects of the present disclosure, a sense amplifier control system is provided that controls the latching timing of all of the sense amplifiers for a memory array based on a reference signal generated by a reference cell, rather than using a timer. This facilitates an IO system where DC current used during a read precharge phase is reduced or eliminated. Further, DC current used during much of a read sensing phase is greatly reduced. This results in decreased power consumption for the memory device, particularly for memory devices having a wide IO.

In some disclosed examples, data is stored in memory cells of a memory array. The memory cells are coupled to IO circuits via bit lines. A sense amplifier control circuit is coupled sense amplifiers of the IO circuits, and has a reference cell configured to generate a reference signal. The sense amplifier control circuit outputs a trigger signal to the sense amplifiers in response to the reference signal, and the sense amplifiers latch the data signals in response to the trigger signal. Thus, the sense amplifiers latch the data signals based on the trigger signal output by the sense amplifier control circuit, rather than based on a timer. Accordingly, the timer circuit (and the DC current consumed thereby) is eliminated. This allows operating the sense amplifiers only as long as is needed to sense and latch the data signals, rather than for an entire time period determined by the timer circuit. This further reduces power consumption of the device.

FIG.1is a block diagram illustrating an example of a memory device10in accordance with some embodiments. In the example shown, the memory device10includes a memory array100, which has a plurality of memory cells110. The memory cells110are coupled to bit lines BL, and data can read from and written to the memory cells110via the bit lines BL. The bit lines BL are further connected to an IO system12that includes a plurality of sense amplifiers120connected to respective bit lines BL. The IO system12further includes a sense amplifier control circuit or controller130that has an output terminal connected to each of the sense amplifiers120.

The memory cells110of the memory cell array100are arranged in rows, each of which has a corresponding word line106, and columns, each of which has a corresponding bit line BL. Each memory cell110stores 1-bit data, though other examples may employ multi-bit memory cells. The memory cell array100may be implemented to have a single-layer array structure (i.e. two-dimensional array structure) or a multi-layer array structure (i.e. a vertical or stack-type three-dimensional array structure).

The memory device10further includes a row selector102, and a column selector104. The row selector circuit102is configured to perform selecting and driving operations on rows of the memory cell array100, including outputting WL control signals to the memory cells110. The column selector circuit104is configured to select columns of the memory cell array100during reading/programming operations. The row selector102and column selector104may be controlled by control logic in response to received memory addresses. During a read operation, for example, WL control signals are output to a selected row of the memory array100, and data bits stored in the memory cells110of the selected row are output to the corresponding bit lines BL. The sense amplifiers120receive the data bits output to their corresponding bit lines BL, and sense and latch the data accordingly. InFIG.1, only two rows and three columns are illustrated for simplicity. The sense amplifiers120include sense amplifiers120-1,120-2. . .120-ncorresponding to the corresponding columns of the illustrated array110.

As will be discussed further below, rather than controlling the sense amplifiers120by a timer, the sense amplifier control circuit130outputs a trigger signal to each of the sense amplifiers120, which senses and latches the received data in response to the trigger signal received from the sense amplifier control circuit130.

In some examples, the memory cells110are nonvolatile memory cells, and as such are capable of retaining data even after power is removed. In other examples, the memory cells may be volatile memory cells. In some examples, the memory cells110illustrated herein are flash memory cells, though other types of memory cells such as one time programmable (OTP) memory cells, multi time programmable memory (MTP) cells, resistive random access memory (RRAM) cells, magnetic random access memory (MRAM) cells, etc. are within the scope of this disclosure.

In some embodiments, the flash memory cells110are implemented using a floating gate MOS transistor device. A floating gate MOS transistor device includes a floating gate that is formed between a control gate and the channel region (the substrate) of the MOS device and at least partially vertically aligned with the control gate. Charge storage on the floating gate determines the stored data state (“0” or “1”) of the memory cell.

In a flash memory cell implemented using a floating gate MOS device, programming or writing data to the memory cell is accomplished by transferring charge carriers from the semiconductor substrate (the source or the drain) to the floating gate by tunneling through the thin gate oxide layer. Typically, a block of flash memory cells is first erased by applying bias conditions to remove the charges stored on the floating gate. Then, the flash memory cells can be written or programmed by applying the bias conditions opposite to the erase operation.

A flash memory cell is read by applying a gate bias to the control gate and sensing the stored data state on the drain terminal of the flash memory cell, which is coupled to a corresponding bit line BL of the memory array100. The sensing of the stored data on the bit lines BL is accomplished using the sense amplifiers120, which compare the current on the bit line BL with a reference current. The reference current may be generated using a reference cell having the same construction as the flash memory cell110in the memory array100.

FIG.2illustrates further aspects of an example of the IO circuit12of the memory device10shown inFIG.1. In the embodiment shown inFIG.2, a data precharge control switch112is connected to the memory cell110at a data input node DIN (i.e. the bit line BL). The data precharge switch112is configured to connect the memory cell110to a power input terminal and precharge the data input node DIN to a predetermined voltage level (e.g. VDD) in response to a precharge signal PCH received at its control terminal. The particular memory cell110is selected and outputs data in response to a received word line signal WL.

The sense amplifier120is coupled to the data input node DIN (i.e. bit line BL) and has a latch circuit122configured to latch the data signal from the memory cell110received on the bit line BL. The sense amplifier control circuit130is coupled the sense amplifier120and also receives the precharge signal PCH as well as a reference word line signal WLREF, discussed further below. The sense amplifier control circuit130outputs a trigger signal to the latch circuit122of the sense amplifier120, and the sense amplifier is configured to latch the data signal in response to the trigger signal.

FIG.3illustrates aspects of an example of the sense amplifier control circuit130. The sense amplifier control circuit130includes a precharge control switch132having a control terminal coupled to receive the precharge signal, which in some examples is the same precharge signal PCH received by the data precharge circuit112that is connected to the memory cell110. The precharge control switch132is connected to a reference cell134at a reference input node RIN. The reference cell134is configured to generate a reference current in response to a received reference word line signal, and in some examples is structured similarly to the memory cell110. A trigger circuit136has an input terminal coupled to the reference input node RIN and an output terminal that outputs the trigger signal to the sense amplifier120.

In a precharge phase, the precharge control switch132is controlled in response to the precharge signal PCH to precharge the reference input node RIN to a predetermined precharge level, such as VDD, by connecting the reference cell134to the VDD power input terminal. In a sensing phase subsequent to the pre-charge phase, the trigger circuit136outputs the triggering signal to the sense amplifier120in response to the reference input node RIN reaching a triggering level, discussed further below.

FIG.4illustrates further aspects of the memory10, showing one of the memory cells110of the memory array100, along with portions of an embodiment of the10circuit12. In the example shown inFIG.4, the memory cell110is a flash memory cell configured to store one bit of data. Other types of memory cells are within the scope of the disclosure. The memory cell110has its gate terminal connected to receive a word line signal WL output on the word line106of the memory cell's110corresponding row. A bit line BL is coupled to the memory cell110, such that the memory cell110outputs its stored data signal to the bit line BL. In the example ofFIG.4, the data precharge switch112includes a PMOS precharge transistor212that receives the precharge signal PCH at its gate terminal. Other types of precharge switches are within the scope of the disclosure. One source/drain terminal of the precharge transistor212is connected to the VDD terminal to receive the power input voltage signal VDD, and the other source/drain terminal of the precharge transistor212is connected to the memory cell at the data input node DIN (i.e. the bit line BL).

The sense amplifier120includes the latch122, with a latch input circuit in the form of a NAND gate220connected to its input, though other configurations of the latch input circuit are within the scope of the disclosure. One input terminal of the NAND gate220is coupled to the data input node DIN and its other input terminal receives a pulse signal from a pulse generator222. The latch122and the pulse generator222each receive the trigger signal from the sense amplifier control circuit130.

The sense amplifier control circuit130ofFIG.4includes the reference cell134, which may be a reference flash memory cell with a configuration that matches the memory cell110. The reference cell134has its gate terminal connected to receive the word line reference signal WLREF. The reference precharge switch132includes a PMOS precharge transistor232that receives the precharge signal PCH at its gate terminal. Other types of precharge switches are within the scope of the disclosure. One source/drain terminal of the reference precharge transistor232is connected to the VDD terminal and the other source/drain terminal of the reference precharge transistor232is connected to the reference cell134at the reference input node RIN.

The trigger circuit136includes a NAND gate236, which has one input terminal coupled to the VDD terminal and another input terminal coupled to the reference input node RIN. As noted above, the reference cell134is configured to generate a reference signal, and the trigger circuit136is configured to output the trigger signal to the sense amplifier120based to the reference signal generated at the node RIN, and the sense amplifier120is configured to latch the data signal in response to the trigger signal.

FIG.5is a wave diagram illustrating various signals generated by the memory device10. Referring toFIG.4andFIG.5, the NAND gate236of the sense amplifier control circuit130provides the trigger signal, which controls the pulse generator222and the latch122of the sense amplifier120. A data read operation includes a precharge phase, where the word line reference signal WLREF and the word line signal WL respectively received by the reference cell134and the memory cell110are both low, or logic 0. The precharge signal PCH is also low during the precharge phase. As such, current flows through the reference precharge transistor232and the data precharge transistor212, and the reference input node RIN and the data input node DIN both are charged to a high level (VDD). Thus, the NAND gate236receives high inputs at both of its inputs and therefore outputs a low signal. Since the trigger signal is low, the pulse signal is not output by the pulse generator222, and the NAND gate220of the sense amplifier120receives a logic low signal at one of its inputs. Further, since the trigger signal is low the latch122is not enabled, and the signal output by the NAND gate220is not latched.

A sensing phase follows the precharge phase as shown inFIG.5, where the word line reference signal WLREF and the word line signal WL corresponding to the selected row both go high. Current flows through both the reference cell134and the memory cell110, and the reference input node RIN and the data input node DIN both begin to fall from the precharge voltage level. If the data signal stored in the memory cell110is logic 0, the data input node DIN voltage level falls from the precharge level at a first rate. If the data signal stored in the memory cell110is logic 1, the data input node DIN falls at a second rate that is greater than the first rate.

As noted above, the reference input node RIN is also pre-charged high (VDD) during the precharge phase. During the sensing phase, the reference input node RIN falls at a third rate, which is between the first speed and the second rates. The third rate at which the reference input node RIN falls from the precharge level is determined based on the configuration of the reference cell134. More particularly, the third rate is determined by trimming the reference current Iref that flows through the reference cell134when the reference word line signal WLREF is asserted to be between the reference cell's134on current I_on and its off current I_off. In some examples, the on current I_on is 30 uA and the off current I_off is 0.5 uA, though other on/off current levels apply in other embodiments, depending on factors such as the memory cell configuration.

In the sensing phase, when the reference input RIN reaches the triggering voltage Vtrig (e.g., VDD/2), the NAND gate236of the sense amplifier control circuit130outputs the trigger signal (i.e. logic 1) to the pulse generator222and the latch122of the sense amplifier120. The pulse generator222correspondingly generates the pulse signal as one input of the NAND gate220. The other input of the NAND gate220is thus inverted and latched as the data output signal DOUT of the sense amplifier120.

More particularly, if the data signal stored in the memory cell110is logic 0, the data input node DIN voltage level falls from the precharge level at the first rate, which is slower than the third rate of the reference signal. Thus, when the reference signal reaches the trigger level Vtrig, the data signal at the data input node DIN is still at a high level when the trigger signal is output to the pulse generator222and latch122. Accordingly, the NAND gate220outputs a logic low signal that is latched and output as the DOUT signal by the latch122. If the data signal stored in the memory cell110is logic 1, the data input node DIN falls at the second rate, which is faster than the third rate. Therefore, the data signal at the data input node DIN falls to a low level before the reference signal reaches the trigger level Vtrig, and the DIN signal input to NAND gate220is low when the pulse generator222outputs the pulse in response to the trigger signal. Accordingly, the NAND gate220outputs a logic high signal that is latched and output as the DOUT signal by the latch122.

Thus, during the sensing phase, a DC current is required for outputting the data signal DOUT only for the duration of the pulse. Further, a timer is not used for controlling the latch during the sensing phase, eliminating the power that would be consumed by the timer.

As shown in the example ofFIG.1, the sense amplifier control circuit130may be coupled to a plurality of sense amplifiers120.FIG.6illustrates an embodiment where the sense amplifier130shown inFIG.4provides the trigger output to n sense amplifiers (n is a positive integer). This facilitates reducing power consumed by a plurality of the sense amplifiers120while only adding one sense amplifier controller130.

FIG.7illustrates another example where the trigger circuit136includes an inverter237. The reference input node RIN is connected to the input of the inverter237, which inverts the reference signal and outputs it as the trigger signal to the pulse generator222and the latch122.

Thus, when the reference input node RIN has been precharge high during the precharge phase, the inverter237output is low. During the sensing phase, the reference signal at the reference input node RIN falls at the third rate, which is between the first and second rates as shown inFIG.5. When the reference signal falls to the trigger level Vtrig, the output of the inverter237(i.e. the trigger signal) goes high. As with the example shown inFIG.4, if the data signal stored in the memory cell110is logic 0, the data input node DIN voltage level falls from the precharge level at the first rate, which is slower than the third rate of the reference signal. Thus, when the reference signal reaches the trigger level Vtrig and the inverter237outputs the trigger signal, the data signal at the data input node DIN is still at a high level so the NAND gate220outputs a logic low signal that is latched and output as the DOUT signal by the latch122. If the data signal stored in the memory cell110is logic 1, the data input node DIN falls at the second rate, which is faster than the third rate. Therefore, the data signal at the data input node DIN falls to a low level before the inverter237outputs the trigger signal to the NAND gate220. Accordingly, the NAND gate220outputs a logic high signal that is latched and output as the DOUT signal by the latch122.

As with the example shown inFIG.4, DC current is required during the sensing phase for outputting the data signal DOUT only for the duration of the pulse, and a timer is not used for controlling the latch during the sensing phase, eliminating the power that would be consumed by the timer.

FIG.8illustrates another example where the sense amplifier130shown inFIG.7provides the trigger output to n sense amplifiers. As such, the output of the inverter237is provided as the trigger signal to each of the pulse generators222and latches122of the plurality of sense amplifiers120. This facilitates reducing power consumed by a plurality of the sense amplifiers120while only adding one sense amplifier controller130.

FIG.9illustrates an example of a method300for sensing and latching data in accordance with disclosed embodiments. The method ofFIG.9includes an operation310in which a data signal is stored in a memory cell, such as the memory cell110disclosed above. In operation312, the precharge signal PCH is received by the reference precharge control switch132/232and the data precharge control switch112/212. In response to the received precharge signal, the reference input node RIN of the trigger circuit136and the data input node DIN are precharged at operation316. In some examples, the reference input node RIN and the data input node DIN are pre-charged to the VDD voltage level. After pre-charging, at operation316the precharge signal is compared to a trigger level Vtrig. If the precharge signal at the reference input node RIN has fallen from the predetermined precharge level (e.g. VDD) to the triggering level Vtrig, a triggering signal is output to the sense amplifier120that operation318. Based on the triggering signal, the data signal is latched by the sense amplifier120at operation320.

Disclosed examples thus include a sense amplifier control system that controls the latching timing of one or more the sense amplifiers for a memory array based on a reference signal generated by a reference cell, rather than using a timer. This facilitates an 10 system where DC current used during a read precharge phase is reduced or eliminated. Further, DC current used during much of a read sensing phase is greatly reduced. This results in decreased power consumption for the memory device, particularly for memory devices having a wide IO.

In accordance with some disclosed examples, a sense amplifier control system includes a precharge control switch having a first terminal, a second terminal and a control terminal. The control terminal is configured to receive a precharge signal. A reference cell has a first terminal, a second terminal and a control terminal, and the control terminal is configured to receive a reference word line signal. The first terminal of the reference cell is coupled to the second terminal of the control switch at a reference input node. A trigger circuit has a first input terminal and an output terminal. The first input terminal of the trigger circuit is coupled to the reference input node. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.

In accordance with further aspects, a memory device includes a memory cell configured to store data. A word line is coupled to the memory cell and is configured to receive a word line signal. A bit line is coupled to the memory cell and is configured to receive a data signal from the memory cell. A sense amplifier is coupled to the bit line and is configured to latch the data signal received on the bit line. A sense amplifier control circuit is coupled the sense amplifier. A reference cell is configured to generate a reference signal, and the sense amplifier control circuit is configured to output a trigger signal to the sense amplifier in response to the reference signal. The sense amplifier is configured to latch the data signal in response to the trigger signal.

In accordance with still further disclosed aspects, a method for controlling a sense amplifier of a memory array includes storing a data signal in a memory cell. A precharge signal is received, and in response to the precharge signal, a reference input node of a trigger circuit and a data input node of a sense amplifier are precharged to a predetermined precharge level. In response to the reference input node falling from the predetermined precharge level to a triggering level, a triggering signal is output to the sense amplifier. The data signal is latched by the sense amplifier in response to the triggering signal.