Highly stable high-voltage output buffer using CMOS technology

A highly stable high-voltage output buffer is provided which may be manufactured using standard CMOS technology. As part of the invention, the effects of voltage drift at one or more of the nodes formed between series connected P or N-channel MOSFET devices are generally reduced or eliminated. The present invention includes compensation circuitry which reduces the effects of parasitic coupling within the MOSFET devices, and which serves to compensate for any voltage drift which may occur at the nodes between series connected devices. In addition, the present invention provides a method and apparatus for increasing the current sourcing capability of a CMOS high-voltage output buffer, even under low supply V.sub.vf conditions, without necessarily increasing the size of the output device. Furthermore, the present invention provides a method and apparatus for reducing the effects of coupling along a shared bias line between a plurality of high-voltage output buffers in accordance with the present invention.

TECHNICAL FIELD 
The present invention relates generally to integrated circuit devices, and 
more specifically, to high-voltage complementary metal oxide semiconductor 
(CMOS) integrated circuit devices. Even more particularly, the present 
invention relates to a high-voltage CMOS output buffer which may be 
fabricated using standard CMOS technology. 
BACKGROUND OF THE INVENTION 
Metal-oxide-semiconductor field effect transistors (MOSFETs) are known in 
the art. FIG. 1 shows a cross-section of a typical P-channel MOSFET device 
10 which includes a lightly doped N- type substrate 11. Two highly doped 
P+ regions 12 and 14 are diffused or implanted into the substrate 11 to 
form a source and drain, respectively, as is known in the art. The P+ 
region 12 serves as a source through which majority carriers ("holes" in 
the case of a P-channel device or alternatively, electrons in the case of 
an N-channel device) enter the MOSFET device 10. The P+ region 14 serves 
as a drain through which the majority carriers, i.e., holes, exit the 
MOSFET device 10. A voltage bias V.sub.g, which is applied at the gate 16 
of the MOSFET device 10, controls the amount of current flow of the 
majority carriers through the MOSFET device 10 between the source 12 and 
the drain 14. More specifically, the gate 16 in conjunction with a 
dielectric oxide layer 18 and the substrate 11 form a parallel plate 
capacitor, such that, by applying an appropriate gate voltage V.sub.g to 
the gate 16, an induced charge is created within a channel region of the 
substrate 11 located between the source 12 and drain 14 of the MOSFET 
device 10. As the gate voltage V.sub.g increases, so does the magnitude of 
the induced charge. As a result, the conductivity of the substrate 11 
between the source 12 and drain 14 increases, and current is permitted to 
flow through the induced channel when a proper drain voltage is presented 
as is known. 
When utilizing a P-channel MOSFET device, both the source 12 and substrate 
11 typically are connected to the source voltage V.sub.s. The drain 14 is 
connected to the drain voltage V.sub.d which is at a lower potential than 
the source voltage V.sub.s. Thus, when the gate voltage V.sub.g is 
negative in relation to the source voltage V.sub.s, a positive charge is 
induced within the substrate 11 adjacent the dielectric layer 18. As is 
explained above, the induced positive charge creates a channel between the 
source 12 and drain 14 through which the majority carriers are permitted 
to travel, therefore resulting in current flow within the device 10. 
An N-channel device is analogous to its P-channel counterpart described 
above. The N-channel device comprises a lightly doped P- type substrate 
into which two highly doped N+ type regions are diffused or implanted to 
form the source and drain. In the case of an N-channel device, an 
appropriate applied gate voltage V.sub.g will cause a negative induced 
charge to form between the N+ type source and drain. This negative induced 
charge permits the majority carriers, i.e., the electrons, to travel 
between the source and drain. Like the P-channel device, the substrate of 
the N-channel MOSFET device is typically connected along with the source 
region to the source voltage V.sub.s. The drain voltage V.sub.d, on the 
other hand, is at a higher potential than the source voltage V.sub.s. As a 
result, when a gate voltage V.sub.g is applied which is positive with 
respect to the source voltage V.sub.s, current is permitted to flow 
through the N-channel device. 
Therefore, a MOSFET device, whether a P-channel or N-channel type, is 
commonly referred to as being turned "on" when the appropriate drain and 
gate biases V.sub.g and V.sub.d are present such that current is permitted 
to travel between source 12 and drain 14. When the appropriate gate and 
drain bias voltages are not present, the device is commonly referred to as 
being "off", due primarily to the very large impedance presented by the 
substrate 11 between the source 12 and drain 14. 
As is described in detail in commonly assigned U.S. Pat. No. 4,490,629 
entitled "High Voltage Circuits in Low Voltage CMOS Process", when the 
MOSFET device 10 is off and the drain 14 is connected through an external 
load device (not shown) to ground, a depletion region 20 in which the free 
majority charge carriers are depleted forms in the substrate 11 around the 
drain 14 as is shown in FIG. 1. Electrons are forced away from the drain 
14 due to its relatively low voltage with respect to the substrate 11, 
which, as was previously described, is connected to a relative positive 
voltage V.sub.s in the case of a P-channel device. As the voltage 
difference between the drain 14 and the substrate 11 increases, the width 
of the depletion region increases, as is known in the art. However, as is 
shown in FIG. 1, the gate 16 of the P-channel device causes electrons to 
be attracted near the gate-substrate-drain interface. The influence of the 
gate voltage V.sub.g tends to force the electric fields to taper in near 
the edge of the drain at the gate interface. As is known in the art, this 
pinching or narrowing of the depletion region near the gate causes a 
reduction in the width of the depletion region to a width d. 
Thus, for an increasing voltage differential between the drain 14 and the 
substrate 11, the effect of the gate voltage V.sub.g at the gate-drain 
interface results in a decreased depletion width d in which the electric 
field between the drain 14 and the substrate 11 increases in the area 
close to the surface. This forms the weakness for conventional MOSFET 
devices in high voltage applications. When the electric field between the 
drain 14 and the substrate 11 becomes sufficiently high, due to a high 
drain voltage V.sub.d for example, the PN junction formed between drain 14 
and the substrate 11 breaks down under reverse-bias and current flows from 
the substrate 11 to the drain 14 near the gate interface. This phenomenon 
is hereinafter referred to as drain to bulk reverse-bias breakdown. 
A more detailed description of the reverse-bias breakdown phenomenon is 
provided in the '629 patent. 
The entire disclosure of U.S. Pat. No. 4,490,629 is hereby incorporated by 
reference. 
For the reasons explained above, the reverse-bias breakdown voltage of a 
P-channel or N-channel MOSFET device 10 is an important parameter to 
consider when designing high voltage switching circuitry using CMOS 
technology. For example, FIG. 2 shows a conventional CMOS inverter 25 
which provides an output voltage V.sub.out which is equal to either the 
voltage indicated as V.sub.dd or the voltage indicated as V.sub.ss, 
depending on the applied input voltage V.sub.in. As is shown in FIG. 2, 
input voltage V.sub.in is applied to the respective gates of devices M1 
and M2. When the input voltage V.sub.in is a logic 1 (typically 5 volts), 
the P-channel device designated M1 turns off while the N-channel device 
designated M2 turns on. Therefore, the MOSFET device M1 exhibits a very 
high impedance, whereas, the device M2 exhibits a very low impedance, thus 
allowing current to flow only through the device M2. As a result, the 
output voltage V.sub.out is pulled down to what is sometimes referred to 
as the V.sub.ss rail, and the output V.sub.out therefore assumes the value 
of V.sub.ss. In the alternative, when the input voltage V.sub.in is a 
logic 0 (typically 0 volts), device M1 turns on and device M2 turns off, 
thereby causing the output voltage V.sub.out to be pulled up to the value 
of voltage V.sub.dd. 
Regardless of whether the output voltage V.sub.out is equal to voltage 
level V.sub.dd or V.sub.ss at a particular moment in time, the MOSFET 
device in inverter 25 which happens to be off at that moment is subjected 
to a reverse bias voltage of approximately V.sub.dd, where V.sub.ss is 
considered to be digital ground. In the event voltage V.sub.dd is a 
substantially high voltage, the reverse bias voltage which will be imposed 
across the particular MOSFET device could result in a reverse bias 
breakdown of the device in the manner described above. 
The '629 patent describes a CMOS high voltage push-pull output buffer which 
is designed to prevent high voltages from being applied across a given 
MOSFET device so as to avoid the occurrence of bulk to drain reverse-bias 
breakdown. The '629 patent described an output buffer in which a number of 
P-channel and N-channel devices are connected in source-to-drain series 
such that the voltage which is to be switched by the output buffer becomes 
evenly distributed across each series connected device, thus avoiding a 
large voltage being applied across a given device and resultantly 
increasing the switching capability of the overall circuit. 
Referring now to FIG. 3, shown is a high voltage output buffer in 
accordance with the teachings of the '629 patent. In FIG. 3, P-channel 
devices designated M3 and M4 are connected in source-to-drain series with 
the similarly connected N-channel devices designated M5 and M6, forming a 
high voltage output buffer 30. As described in the '629 patent, gate 
voltages for the P-channel and N-channel devices are selected such that 
the relatively high supply voltage V.sub.vf substantially equally divides 
across the series connected P-channel devices in the event the P-channel 
devices are off and the N-channel devices are on. Alternatively, the high 
supply voltage V.sub.vf substantially equally divides across the series 
connected N-channel devices when the N-channel transistors are off and the 
P-channel devices on. In this manner, large reverse bias voltages across 
the MOSFET devices tend to be avoided. 
As an example, when a logic 1 signal is applied to the control inputs 
designated CTRL1 and CTRL2, devices M5 and M6 are turned on while devices 
M3 and M4 are turned off, resulting in output voltage V.sub.out =V.sub.ss. 
As is taught in the '629 patent, with a bias voltage (from an appropriate 
source) of V.sub.bias =0.5 V.sub.vf applied to the gate of device M4, the 
source of device M4 will tend to remain at a voltage of approximately 0.5 
V.sub.vf +V.sub.t, wherein V.sub.t is the threshold voltage of the MOSFET 
device. Meanwhile, the voltage at the source of device M3 will tend to 
remain at the value of supply voltage V.sub.vf as is shown in FIG. 3. As a 
result, the supply voltage V.sub.vf becomes substantially equally divided 
across each respective source to drain of the P-channel devices M3 and M4. 
More specifically, the voltage across each of the MOSFET devices which 
remain off is equal to one-half V.sub.vf. 
Alternatively, in the case where a logic 0 control input signal is applied 
to control lines CTRL1 and CTRL2, devices M3 and M4 turn on and devices M5 
and M6 turn off, thereby causing the output voltage V.sub.out to switch or 
be pulled up to the level of supply voltage V.sub.vf. The voltage at the 
drain of device M5 becomes that of the output voltage V.sub.out, or 
approximately the supply V.sub.vf. The voltage at the source of M5 remains 
at a value of approximately 0.5 V.sub.vf -V.sub.t, which corresponds to 
the source to drain voltage across device M6. In this case, therefore, the 
supply voltage designated V.sub.vf will be substantially equally divided 
across devices M5 and M6. As in the above case, the magnitude of the 
voltage across a given MOSFET device is limited to that of 0.5 V.sub.vf. 
According to the explanatory embodiment shown in FIG. 3, where two 
P-channel and two N-channel devices are connected in series, a single bias 
voltage applied to the gates of M3 and M4 is sufficient to enable the 
supply voltage V.sub.vf to be substantially equally divided across the 
P-channel devices M3 and M4 when they are off, and alternatively, across 
the N-channel devices M5 and M6 in the event they are off. As is described 
in the '629 patent, the appropriate bias voltage V.sub.bias for the 
embodiment shown in FIG. 3 is V.sub.bias =0.5 V.sub.vf. This bias voltage 
is applied to the gates of both the P-channel device M4 and the N-channel 
device M5. Because an identical bias voltage ordinarily is applied to 
devices M4 and M5, in order that the supply voltage V.sub.vf will 
substantially equally divided across either the P or N-channel devices, M4 
and M5 are referred to herein as forming a corresponding P-channel and 
N-channel pair. 
More generally, a P-channel device and an N-channel device in the 
series-connected stack are referred to herein as forming a corresponding 
pair when an approximately equal bias voltage is applied to the respective 
gate in each of the devices in the pair in order that the output voltage 
V.sub.out becomes substantially equally divided across either the 
series-connected P-channel device or the N-channel device in the output 
buffer. The embodiment shown in FIG. 3 includes the corresponding pair of 
devices M4 and M5. 
In an output buffer such as that shown in FIG. 3 of the drawings of the 
'629 patent, the output buffer may include three P-channel devices and 
three N-channel devices connected in series. In such an embodiment having 
three of each type of devices connected in series, two separate 
corresponding pairs are formed, each including a single P-channel and 
N-channel device. A bias voltage of 1/3 V.sub.vf is applied to the gates 
of a first P-channel device and a first N-channel device which make up a 
first corresponding pair. A bias voltage of 2/3 V.sub.vf is applied to the 
gates of a second P-channel device and a second N-channel device in the 
series connection which in turn make up a second corresponding pair. In 
the teachings of the '629 patent, a single bias line is utilized to 
provide the voltage to each gate in the corresponding pair. 
While the exemplary prior art output buffer 30 shown in FIG. 3 utilizes two 
P-channel and two N-channel devices connected in series, other prior art 
embodiments included additional series-connected MOSFET devices so that 
the voltage across a given individual device was further reduced. As is 
taught in the '629 patent, in the event additional devices were connected 
in series, appropriate bias voltages which were typically approximately 
equal to integer fractions of V.sub.vf, were applied in a similar fashion 
to that described above to the gates of the additional corresponding pairs 
of P-channel and N-channel devices. The exact number and values of the 
addition bias voltages depended on the number of MOSFET devices which were 
connected in series in the output buffer 30. Therefore, while the 
background of the invention as well as the invention itself is described 
herein as involving primarily a high voltage output buffer having only two 
P-channel and two N-channel devices connected in series, it will be 
appreciated that such a configuration is intended to be merely exemplary. 
The various aspects of the present invention equally apply to high voltage 
output buffers having additional series connected devices with related 
bias voltages. As a result, the scope of the present invention is not 
intended to be limited to that of the exemplary embodiment. 
As is evident in the above example, the '629 patent describes a push-pull 
output buffer 30 capable of switching high voltages using standard CMOS 
technology and/or processes. Complex fabrication processes for increasing 
the bulk to drain reverse bias breakdown voltage of the individual MOSFET 
devices are not required. The buffer 30 employs a plurality of P and 
N-channel devices connected in series in addition to appropriate gate 
biasing in order to distribute evenly the voltage across each device so 
that reverse bias breakdown voltage of each device may be avoided, even in 
the presence of high voltages. 
There have been, however, a number of drawbacks associated with 
high-voltage output buffers of the type described in the '629 patent. For 
example, the voltages at the nodes between the series connected devices 
have been found to drift upon a switching of the output voltage V.sub.out. 
More specifically, a drift voltage node has been observed, for example, at 
a location indicated as node N1 of the output buffer 30, as is shown in 
FIG. 3. As is explained in detail below, such voltage drift at node N1 can 
stress the gate at the drain end of device M3. Under high voltage 
conditions, this stress can eventually lead to the failure of device M3 as 
well as the entire circuit 30. As an example, such stress related problems 
have often been found to arise in those applications in which the supply 
voltage V.sub.vf is greater than 30 volts. 
Another problem which has been associated with prior high-voltage output 
buffers has been their inability to source sufficient current under low 
V.sub.vf conditions, for example, V.sub.vf .ltoreq.8 volts. In the 
exemplary output buffer shown in FIG. 3, the sourcing ability of each 
MOSFET device is proportional to its gate bias, or V.sub.gs -V.sub.t, 
where V.sub.gs is the gate to source voltage of the device and V.sub.t is 
its threshold voltage. Because the gate to source voltage V.sub.gs of each 
device is dependent on the value of the supply voltage V.sub.vf, the 
sourcing ability of these devices has been found to suffer under low 
V.sub.vf conditions. In the past, the above problem has been dealt with by 
increasing the size of each MOSFET device, thus increasing the channel 
width of each device so that a greater number of majority charge carriers 
are enabled to travel under low supply voltage V.sub.vf conditions. 
However, this increase in the size of each MOSFET device resulted, 
unfortunately, in both the inefficient use of the substrate 11 and in the 
increased cost of the output buffer. 
Related to the inability of output buffers in the past to source sufficient 
current under low V.sub.vf voltage conditions was their restricted 
switching speed. More specifically, because the gate voltage typically 
applied was insufficient to turn the respective device fully "on", each 
device represented a relatively large impedance even in the "on" 
condition. This large impedance hindered the switching response time of 
the output buffer, as will be appreciated by one of ordinary skill in the 
art. 
Yet another problem associated with such prior high-voltage output buffers 
has been the problem of noise on one or more of the bias lines. 
Oftentimes, multiple high-voltage output buffers 30 were driven by the 
same bias lines, these bias lines providing the appropriate bias voltages 
to similar corresponding pairs of P and N-channel MOSFETS. However, when 
the output voltage V.sub.out would be switched, for example, in a single 
output buffer with respect to the other output buffers 30 sharing the same 
bias line, the parasitic coupling occurring in the MOSFET devices in the 
switching buffer 30 tended to cause the voltage on the individual bias 
line or lines to be pulled up or down. As a result, it is evident that the 
effect of other output buffers 30 switching would be seen as noise on the 
bias line for a given high voltage output buffer 30. 
Thus, there remains a strong need in the art for a method and apparatus for 
providing a highly stable high-voltage output buffer using conventional 
CMOS technology. More specifically, there remains a strong need for a 
method and apparatus for reducing or eliminating the problems caused by 
drift voltage nodes in a high-voltage output buffer without requiring 
elaborate processing of the CMOS device. 
Furthermore, there is a need for a high-voltage output buffer which is 
capable of sourcing the necessary current under low V.sub.vf voltage 
conditions, without having to increase the size of the output device. In 
addition, there remains a strong need for a high-voltage output buffer 
capable of operating at a high switching speed. Even more, there remains a 
strong need for a high-voltage output buffer whose performance at low 
voltages is comparable to its performance at high voltages. 
In addition, there remains a strong need for a high-voltage output buffer 
which may share one or more common bias lines with other of such output 
buffers while reducing the noise occurring along the shared bias lines. 
SUMMARY OF THE INVENTION 
Accordingly, the present invention has been developed to over-come the 
foregoing shortcomings of existing CMOS high-voltage output buffers. 
In the present invention, there is provided a highly stable high-voltage 
output buffer which may be manufactured using standard CMOS technology. As 
part of the invention, the effects of voltage drift at one or more of the 
nodes formed between series connected P or N-channel MOSFET devices are 
greatly reduced or eliminated. The present invention includes compensation 
circuitry which reduces the effects of parasitic coupling within the 
MOSFET devices, and which serves to compensate for any voltage drift which 
may occur at the nodes between series connected devices. In addition, the 
present invention provides a method and apparatus for increasing the 
current sourcing capability of a CMOS high-voltage output buffer, even 
under low supply V.sub.vf conditions, without necessarily increasing the 
size of the output device. Furthermore, the present invention provides a 
method and apparatus for reducing the effects of coupling along a shared 
bias line between a plurality of high-voltage output buffers in accordance 
with the present invention. 
In accordance with one aspect of the present invention, an apparatus is 
provided for a high-voltage complementary metal oxide semiconductor (CMOS) 
push-pull output buffer, comprising: at least one P-channel transistor and 
at least one N-channel transistor connected in series; and compensation 
means for reducing voltage drift at one or more nodes located between said 
series connected transistors. 
In accordance with another aspect there is provided a high-voltage CMOS 
push-pull output buffer, comprising: at least one P-channel transistor and 
at least one N-channel transistor connected in series; and means for 
compensating for voltage drift at a node located between said series 
connected transistors, said compensation means comprising means for 
decreasing a feedback voltage between a gate and drain in at least one of 
said transistors, and means for charging a node experiencing voltage drift 
as a result of said feedback voltage back to its appropriate potential. 
In accordance with a further aspect there is provided a high-voltage CMOS 
push-pull output buffer, comprising: at least one P-channel transistor and 
at least one N-channel transistor connected in series; and separate bias 
lines which provide bias voltages to a corresponding P-channel and 
N-channel transistor pair, said bias voltages being substantially equal 
under normal voltage conditions, and said bias voltages being different 
under low voltage conditions. 
In accordance with yet another aspect there is provided a method for 
increasing the stability of a high-voltage CMOS push-pull output buffer 
having at least one P-channel transistor and at least one N-channel 
transistor connected in series, said method comprising the step of 
compensating for voltage drift at a node located between said series 
connected transistors. 
In accordance with a still further aspect there is provided a method for 
increasing the current sourcing ability of a high-voltage CMOS push-pull 
output buffer having at least one P-channel transistor and at least one 
N-channel transistor connected in series, said method comprising the step 
of: providing separate bias voltages to the gates of a corresponding 
P-channel and N-channel transistor pair within the series connected 
transistors, and controlling the magnitude of the bias voltages relative 
to one another so as to increase the current sourcing ability of the 
buffer. 
These and other aspects, features, and embodiments of the invention will 
become apparent as the following description proceeds. 
To the accomplishment of the foregoing and related ends, the invention, 
then, comprises the features hereinafter fully described and particularly 
pointed out in the claims, the following description and the annexed 
drawings setting forth in detail certain illustrative embodiments of the 
invention, these being indicative, however, of but a few of the various 
ways in which the principles of the invention may be employed. 
While the present invention is described with reference to a particular 
embodiment, the invention is not limited to the specific examples given, 
and other embodiments and modifications can be made by those skilled in 
the art without departing from the spirit and scope of the invention. It 
will be appreciated that the scope of the invention is determined by the 
claims and equivalents thereof.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring now to FIG. 4, a highly stable high-voltage output buffer 40 in 
accordance with the present invention is shown. The output buffer 40 
includes two P-channel MOSFET devices M7 and M8 which are connected in 
series with two N-channel MOSFET devices M9 and M10, as is described 
above, and further includes a compensation device 42. The output voltage 
V.sub.out is located at the node between the series connected drains of 
the P-channel device M8 and the N-channel device M9. The control inputs 
CTRL1 and CTRL2 are located at the gates of devices M7 and M10, 
respectively. A separate set of bias lines V.sub.b1 and V.sub.b2 are 
provided to the gates of devices M8 and M9, respectively, and serve to 
provide the appropriate bias voltages from a bias generator (not shown) as 
is described in further detail below. 
The compensation device 42 is utilized in the present invention to reduce 
or eliminate any voltage swing along the bias lines V.sub.b1 and V.sub.b2. 
In addition, the compensation device 42 is utilized to reduce or to 
eliminate the effects of voltage drift which may occur, for example, at 
the node designated N2 in the output buffer 40. As is mentioned above, the 
voltages at the various nodes between the series connected MOSFET devices 
in the output buffer have been found to drift, especially when the output 
voltage V.sub.out is transitioned. Compensation device 42 prevents the 
devices M7-M8 from being overly stressed in the manner described below so 
as to avoid failure of the individual devices and the output buffer 40 
itself. 
Describing now the operation of output buffer 40, when the supply voltage 
V.sub.vf is a relatively high voltage, i.e., greater than 20 volts, the 
voltages of bias lines V.sub.b1 and V.sub.b2 are predetermined in 
accordance with the principles set forth in the '629 patent. Thus, for the 
output buffer 40 shown in FIG. 4 as having two P- and two N-channel 
devices connected in series, the bias voltages on bias lines V.sub.b1 and 
V.sub.b2 are set approximately to 0.5 V.sub.vf. As a result, when control 
lines CTRL1 and CTRL2 receive a logic 1 signal, for example, devices M9 
and M10 will turn on and devices M7 and M8 will turn off, thereby causing 
the output voltage V.sub.out to be pulled down to the V.sub.ss rail. In 
such a case, the reverse bias voltage across the two P-channel devices M7 
and M8 will be approximately equal to 0.5 V.sub.vf +V.sub.t, as is 
described above. Alternatively, if a logic 0 signal is applied to the 
control lines CTRL1 and CTRL2, devices M9 and M10 will turn off and 
devices M7 and M8 will turn on, such that the output voltage V.sub.out 
will be pulled up to the supply voltage V.sub.vf rail. In such case, the 
supply voltage V.sub.vf will be substantially equally distributed across 
devices M9 and M10 rather than devices M7 and M8. 
During the operation of output buffers having series connected MOSFET 
devices, voltage drift has tended to occur at one or more nodes between 
the series connected MOSFET devices. For example, it is believed that the 
voltage drift at the node designated N2 is brought on, at least in part, 
by an output feedback effect which coupled through the parasitic 
capacitance of the drain of device M8. More specifically, the parasitic 
capacitance C.sub.gd between the gate and drain of device M8 (shown in 
phantom in FIG. 4), causes what is referred to as output feedback to occur 
when the output voltage V.sub.out changes from the value of V.sub.vf to 
that of V.sub.ss. This happens, for example, when the applied voltage on 
control lines (CTRL1 and CTRL2 goes from a logic 0 to a logic 1 state as 
is detailed above. When the output voltage V.sub.out changes from the 
value of V.sub.vf to that of V.sub.ss, a rapid, relatively large voltage 
change is experienced at the drain of device M8, which is then coupled 
through the parasitic capacitance C.sub.gd to the gate of device M8. This 
voltage surge oftentimes is greater than the applied bias voltage on bias 
line V.sub.b1 and acts to decrease the voltage on the bias line V.sub.b1. 
As a result of the decreased bias voltage, device M8 is turned on more 
heavily than it would be were the voltage on the bias line V.sub.b1 to 
remain constant. Node N2 is therefore discharged to a low potential 
(approximately the minimum transient value of V.sub.b1 +V.sub.t), which 
can result in an unreasonably large reverse bias voltage occurring across 
device M7, possibly exceeding its reverse bias breakdown voltage. Such a 
stress can eventually lead to the failure of device M7. Furthermore, once 
device M7 fails, the entire circuit 40 could follow. 
In the preferred embodiment, the present invention utilized the 
compensation device 42 in the output buffer 40 to reduce the effects of 
output feedback by reducing the magnitude of the voltage coupled onto the 
bias lines V.sub.b1 and V.sub.b2. Furthermore, the present invention 
utilizes the compensation device 42 to recharge node N2 to its appropriate 
potential in the event such potential is discharged undesirably, for 
example, due to the aforesaid capacitive coupling. In previous output 
buffers such as those described in the '629 patent, there was no source of 
current at node N2 to provide the necessary charge to recharge node N2 and 
thereby alleviate the stress on device M7. 
FIG. 5A shows an output feedback model which represents the coupling which 
occurs between the output voltage V.sub.out and the voltage on the bias 
line V.sub.b1 through the parasitic capacitance C.sub.gd, as is described 
above. 
The voltage on the bias line V.sub.b1 can be described by the following 
equation: 
EQU V.sub.b1 (t)=V.sub.p * exp(-t/W.sub.O)+V.sub.b1.phi., 
where 
W.sub.O =1(R.sub.BO * C.sub.gd), 
R.sub.BO is the output impedance of the bias generator; 
V.sub.p is the peak voltage; and 
V.sub.b1.phi. =steady state value of V.sub.b1, typically approximately 0.5 
V.sub.vf. 
In the preferred embodiment, the compensation device 42 includes a shunt 
capacitor C.sub.vb1 between the bias line V.sub.b1 and ground V.sub.ss to 
reduce the peak voltage V.sub.p which is coupled through to the gate of 
device M8 as is shown in FIG. 5B. Using the shunt capacitor C.sub.vb1, the 
feedback model may be described as follows: 
##EQU1## 
where W.sub.1 =1/[R.sub.bo (C.sub.vb1 +C.sub.gd)] 
The addition of the shunt capacitor C.sub.vb1 between bias line V.sub.b1 
and digital ground V.sub.ss therefor reduces or eliminated the effects of 
any output feedback caused by the parasitic capacitance C.sub.gd of MOSFET 
device M8. Should the output feedback present a rapid change in the 
voltage on the bias line V.sub.b1, the voltage change will be shunted to 
ground and, as a result, device M8 will not be turned on so heavily, if at 
all. Instead, the voltage on the bias line V.sub.b1 will preferably remain 
at its desired value as is described above. Moreover, while the shunt 
capacitor C.sub.vb1 is described in the preferred embodiment as being tied 
to V.sub.ss, it will be apparent that in alternate embodiments, C.sub.vb1 
can be tied to V.sub.vf or any low impedance power supply. 
In the preferred embodiment, the composition device 42 further includes 
circuitry for recharging node N2 to its appropriate potential 
(approximately 0.5 V.sub.vf +V.sub.t in the described exemplary 
embodiment), in the event it is discharged to a low potential due to 
output feedback. The compensation device 42 serves as a current source 
which provides additional charge to node N2 such that the node is returned 
to its appropriate potential. In the preferred embodiment, the 
compensation device 42 utilized a diode or bipolar transistor for 
providing charge to node N2. In most of today's standard CMOS processes, 
diodes and bipolar transistors are inherently present in the CMOS chip 
where various p-n-p or n-p-n junctions are formed. Thus, the present 
invention may be implemented using most standard CMOS processes. However, 
other embodiments may use other current or charge sourcing devices, using 
standard or non-standard CMOS processes, without departing from the 
intended scope of the present invention. While it is preferred that 
standard CMOS processes be utilized, it will be apparent to one of 
ordinary skill that various devices and/or processes may be utilized to 
reduce or to eliminate coupling on the bias lines as well as voltage drift 
at the various nodes. 
FIG. 6 shows a detailed schematic diagram of a highly stable high voltage 
driver circuit 60 including a CMOS high-voltage push-pull output buffer 61 
using standard CMOS technology in accordance with the present invention. 
Devices M7-M10 are connected in a series configuration forming the output 
buffer 61 as is described above, and the bias lines V.sub.b1 and V.sub.b2 
provide the appropriate bias voltages to the gates of M8 and M9 
respectively. Shunt capacitors C.sub.vb1 and C.sub.vb2 are respectively 
located between digital ground V.sub.ss and the bias lines V.sub.b1 and 
V.sub.b2. Devices M11-M14 and M15-M18 form two secondary output buffers 
62, 63 which serve as a predriver or amplifier 64 between the control 
inputs CTRL1 and CTRL2 and the output buffer 61 devices M7-M10, which make 
up the primary output buffer. 
Thus, for example, a logic 1 signal of 5 volts on the control line CTRL2 
would clearly be sufficient to turn on device M10 in the output buffer 61. 
However, this same 5 volt signal on the control line CTRL1 would not be 
sufficient to turn off device M7 as is necessary in order for the output 
buffer 60 to function properly. Of course, this is due to the fact that 
the source of device M7 is at the supply voltage V.sub.vf which typically 
would be much greater than the 5 volt input signal. Therefore, devices 
M11-M18 are used to increase the value of the control inputs to the 
high-voltage output buffer 61 where necessary. 
The predriver or amplifier 64 formed by devices M11-M18 is configured in 
the form of a cross-coupled inverter stage. As a result, the amplifier 
does not use as much current as would a traditional amplifier. However, 
while the preferred embodiment uses such an amplifier, it is not meant to 
limit the scope of the invention. 
In accordance with the preferred embodiment of the present invention shown 
in FIG. 6, the compensation device 42 includes compensation circuitry for 
reducing possible voltage drift at nodes N2-N7. It is noted that such 
voltage drift tends not only to occur at the nodes between the series 
connected devices M7-M10, but also at the nodes between the series 
connected devices M11-M18 for one or more of the above described reasons. 
The compensation device 42 includes shunt capacitors C.sub.vb1 and 
C.sub.vb2 for reducing the peak voltage V.sub.p which ordinarily would 
tend to be coupled to the bias lines V.sub.b1 and V.sub.b2 through devices 
M8, M12, and M16 (with respect to bias line V.sub.b1), and devices M9, 
M13, and M17 (with respect to bias line V.sub.b2). Thus shunt capacitors 
C.sub.vb1 and C.sub.vb2 preferably are FET devices connected with their 
source, drain and substrate each tied to ground and their gate coupled to 
a respective bias line V.sub.b1, V.sub.b2 as is shown in FIG. 6. 
Since the shunt capacitors preferably are formed of field effect transistor 
(FET) devices, and since those FET devices can be formed with the other 
FET or MOSFET devices of the circuit 60, no special CMOS processes would 
be necessary to make the shunt capacitors. Alternatively, the shunt 
capacitors may be made using other monolithic techniques, either standard 
or non-standard. The above equations preferably are utilized in order to 
determine the desired capacitance for providing sufficient coupling 
between the bias lines and ground in a given application, as will be 
apparent to one of ordinary skill. 
In order to recover the voltage at nodes N2, N3 and N4 in the event they 
are undesirably discharged due to, for example, a swing in the bias line 
voltage as is described above, the preferred embodiment of the 
compensation device 42 includes bipolar devices Q1, Q2 and Q3. Thus, for 
example, when node N2 is discharged to a low potential due to output 
feedback or the like, device Q1 would turn on causing a charge to build up 
at node N2 until the voltage at node N2 becomes approximately equal to the 
bias voltage V.sub.b1. Similarly, should nodes N3 and N4 be discharged to 
a low voltage due to parasitic capacitance or the like, devices Q2 and Q3 
would serve to charge each respective node back to the appropriate 
voltage. 
In an analogous manner to that which is described above, node N5 (as well 
as nodes N6 and N7) may also experience voltage drift due to, for example, 
the output feedback effect which couples through the parasitic capacitance 
of each respective MOSFET device. More specifically, using device M9 as an 
example, when output voltage V.sub.out changes from that of digital ground 
V.sub.ss to the supply voltage V.sub.vf, the transitioning output voltage 
will couple through the parasitic capacitance C.sub.gd to the gate of 
device M9. As is described above, this coupled voltage will cause a swing 
in the bias line voltage V.sub.b2, causing device M9 to turn on heavily, 
and thus causing node N5 to be pulled up to an undesirably high level. As 
a result, a large voltage or stress is placed across device M10. 
As is described above, shunt capacitor C.sub.vb2 helps to slow down or to 
eliminate the effects of such undesirable output feedback by reducing or 
eliminating swing in the bias line voltage. Moreover, by carefully timing 
the application of the control signals on control lines CTRL1 and CTRL2 
during a switching operation, it is possible to shut off device M10 and 
turn on device M7 such that node N5 may properly charge up to avoid the 
voltage stress on the gate of device M9. This enables the effects of 
voltage stress to be avoided at nodes N5, N6 and N7 in the output buffer 
60. 
Alternatively, the compensation device 42 may also include a bipolar 
transistor or the like which is configured to remove excess charge from 
node N5. For example, the compensation device 42 may include a bipolar 
transistor which is configured in a complementary fashion to that of Q1. 
Thus, the bipolar transistor will discharge excess charge from node N5 
until the voltage at node N5 becomes approximately equal to the bias line 
V.sub.b2 voltage. 
In addition to reducing or eliminating the effects of voltage drift and/or 
swing in the bias line voltages in the output buffer 61, the preferred 
embodiment of the present invention offers enhanced performance of the 
output buffer 61 under low V.sub.vf conditions. This is accomplished in 
part by utilizing separate bias lines V.sub.b1, V.sub.b2 for biasing each 
MOSFET device in the corresponding pair. 
In the past, a single bias line has been utilized to provide the desired 
bias voltage to a corresponding pair of MOSFET devices as is described 
above. For example, the above mentioned '629 patent teaches a single fixed 
bias line V.sub.bb =0.5 V.sub.vf for biasing corresponding devices M4 and 
M5 as is shown in FIG. 3. Because the bias voltage applied to the devices 
in the corresponding pair were equal, a single bias line was sufficient. 
The present invention utilizes separate bias lines V.sub.b1 and V.sub.b2 
rather than the single line V.sub.bb for providing the bias voltages to 
the corresponding P and N-channel devices M8 and M9. The present invention 
utilizes separate bias lines such that the gate voltages on corresponding 
P and N-channel devices in the series connected stack may be controllably 
optimized both under low and high supply voltage V.sub.vf conditions. As a 
result, the performance of the output buffer at low voltage conditions is 
comparable to that at high voltage conditions. 
The preferred embodiment of the present invention is designed in such a 
manner that the bias voltages on the respective bias lines to the buffers 
61-63 are switched in the event the supply voltage V.sub.vf drops below a 
predetermined reference voltage. Specifically, by switching the applied 
bias voltages when the supply voltage V.sub.vf passes through a reference 
voltage, V.sub.switch, the performance of the buffers is enhanced as is 
described in detail below. 
In order to predetermine the reference voltage V.sub.switch, one must take 
into account the critical voltage of the MOSFET devices. The critical gate 
voltage (V.sub.crit) for a given MOSFET device may be defined as the 
applied gate voltage at which reliability problems may occur in the MOSFET 
device. More specifically, V.sub.crit is the maximum value of V.sub.vf at 
which the bias voltage to the device can change. Therefore, the described 
invention preferably is designed such that the above-mentioned switching 
voltage V.sub.switch is a voltage V.sub.crit. Otherwise, the precise value 
of V.sub.switch is limited only by circuit operation constraints. 
In the event the supply voltage V.sub.vf is greater than or equal to 
V.sub.crit, the bias lines in the present invention are preferably 
automatically set such that V.sub.b1 =V.sub.b2 =0.5 V.sub.vf, which would 
be the appropriate bias voltage for the single bias line as is taught in 
the '629 patent. In the event, however, that the supply voltage V.sub.vf 
is lower than the predetermined voltage V.sub.switch, the bias lines in 
the present invention are set such that V.sub.b1 =0 V and V.sub.b2 
=V.sub.vf volts. 
Thus, in the high-voltage driver circuit shown in FIG. 6, when the control 
line CTRL2 receives a logic 1 and CTRL1 receives a logic zero signal and 
the supply voltage V.sub.vf is greater than or equal to V.sub.switch, 
devices M7 and M8 are turned off and devices M9 and M10 are turned on. The 
bias voltage on bias line V.sub.b2 =0.5 V.sub.vf provides an applied gate 
to source voltage of approximately 0.5 V.sub.vf, which would sufficiently 
bias devices M9 and M10 to conduct the necessary current. However, in the 
event that the supply voltage V.sub.vf is less than switching voltage 
V.sub.switch, the bias line values are automatically switched to V.sub.b1 
=0 V and V.sub.b2 =V.sub.vf in order to maximize the applied gate to 
source voltages of the P- and N-channel devices. By maximizing the applied 
gate to source voltages on the respective devices, the conductivity of the 
devices when on is increased, and therefore the sourcing ability and 
switching speed of the output buffer is also increased as will be 
appreciated. As an example, if a logic 1 signal were applied to the 
control line CTRL2 and logic zero on CTRL1, both devices M7 and M8 turn 
off and devices M9 and M10 turn on. In the situation where the supply 
voltage V.sub.vf is less than the switching voltage V.sub.switch, the 
entire supply voltage V.sub.vf is applied to the gate of device M9 such 
that the gate to source voltage is approximately the entire value of the 
supply voltage V.sub.vf, thus turning on device M9 as heavily as possible. 
Hence, the use of separate bias lines in the present invention allows 
differing voltages to be applied to corresponding P- and N-channel device 
pairs in the series connected stack, thus enhancing the current driving 
ability of the output buffer 61 in low supply voltage V.sub.vf 
applications, and thereby reducing the size and cost of the overall 
circuit 60, especially output buffer 61, as well as increasing the speed. 
While the present invention is described with reference to a particular 
embodiment, the invention is not limited to the specific examples given, 
and other embodiments and modifications can be made by those skilled in 
the art without departing from the spirit and scope of the invention. It 
will be appreciated that the scope of the invention is determined by the 
claims and equivalents thereof. 
For example, while the output buffers shown in FIGS. 4 and 6 utilize a 
series configuration of two P- and two N-channel devices, in view of the 
present invention it will be appreciated by one of ordinary skill in the 
art that any number of P- and N-channel devices may be similarly connected 
in series such that the high supply voltage V.sub.vf is preferably 
substantially evenly distributed across either the P- or N-channel 
devices. Likewise, the present invention may include multiple sets of 
separate bias lines, each set biasing an appropriate corresponding pair of 
MOSFET devices. While the voltage on each bias line in the set is equal 
under normal supply voltage V.sub.vf conditions, the voltage on each bias 
line may be adjusted to maximize performance under low supply voltage 
V.sub.vf conditions. 
In addition, the inventive aspects of the compensation device 42 need not 
be limited to use in a high-voltage output buffer, but may also be 
included in various other circuits or applications in which a two or more 
MOSFET or other type devices are connected in series and are subjected to 
a high voltage being switched across one or more of their outputs.