Systems, apparatuses, and methods for broadcast compare addition

Systems, apparatuses, and methods for executing an instruction. The instruction includes fields for a first source operand, a second source operand, and a destination operand. A decoded instruction causes a reduction of broadcasted packed data elements of a first packed data source with a reduction operation and store a result of each of the reductions in a packed data destination, wherein the packed data elements of the first packed data source to be used in the reduction are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source without broadcasting.

FIELD OF INVENTION

The field of invention relates generally to computer processor architecture, and, more specifically, to instructions which when executed cause a particular result.

BACKGROUND

Vectorization of sparse update pattern using a conflict detection package has its limitations. Consider an example code of sparse update:

This loop cannot be vectorized with a straightforward approach because it may have potential data dependencies when idx[i] has equal values on different iterations of the loop (referencing to the same memory address).

A conventional way to vectorize the loop is to check for conflicts of indexes with a conflict instruction that generates a result of comparing each index in a vector to each other, and based on this result values are loaded from B[ ] to a vector, permuted, accumulated, and stored to A[ ]. Accumulation is usually done in an inner while loop by permuting values based on a special permute control, which is generated based on the conflict result. This process is iterative and repeated as shown below:

The body and number of iterations of the inner while loop vary depending on the instruction set available and algorithm implementation. For example, if there are 16 equal indexes (corner case), then a simple algorithm implies 15 permutations and 15 additions.

DETAILED DESCRIPTION

Unfortunately, typical solutions to the vectorization of a sparse update pattern necessarily have this loop with permutations and mask computations. The most problematic cases are with a large number of conflicts, which may result in slower code than scalar execution. Detailed herein are embodiments of an instruction to broadcast values to a set of temporal vectors with zeroing unset elements, and then do a reduction (addition) of all temporal vectors to a single one. For example, in the above code, the set of masks generated by the conflict instruction are used for sparse reduction operation to a set of temporal vectors with zeroing unset elements.

The problem with typical conflict instructions is that they support only doubleword and quadword data types for an input vector of indexes. For smaller data types there is not enough space to keep all the bits of pairwise comparisons in the destination vector. For example, for byte indexes there are 64 elements in a 512-bit register. For comparing 64 elements with a single element, one would need 64 bits to keep output result for a single element, and a total of 4,096 bits (64-bit×64-bits) for the entire result, which is eight times larger than a 512-bit register can accommodate.

Moreover, there are actually two data types in play: type of indexes and type of data for reduction and they might be different sizes. For example, A[ ] and B[ ] are byte integers and idx[ ] is quadword integer. Thus, in a 512-bit B register there can be 64 elements for reduction loaded from array B[ ] and only 8 indexes in a 512-bit indexes loaded from idx[ ]. With the current conflict based approach only 8 elements from the 512-bit B can be processed meaning there is only ⅛ vector efficiency. Generally, the embodiments detailed herein combine a comparison of indexes with data reduction in a single instruction.

Some exemplary advantage of using this instruction in a sparse update pattern may include, but are not limited to: no permutations; no overhead for generating permute control; no overhead for mask computations; no inner while loop at all; support for different index types; and vector efficiency for combinations of index/data type.

Detailed herein are embodiments a broadcast compare arithmetic instruction. The arithmetic operation includes, but is not limited to, addition, subtraction, multiplication, and division. The execution of this instruction causes an execution circuit (execution unit) to perform an arithmetic operation (e.g., sum) of broadcasted packed data elements of a first packed data source and store the result of each of the operations in a packed data destination. In some embodiments, the packed data elements of the first source to be broadcast are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source (without broadcasting). As such, only the broadcasted packed data elements of the first packed data source101are subject to the arithmetic operation. In some embodiments, broadcasted packed data elements of the first source to be selected for the arithmetic operation are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source (without broadcasting). For example, in some embodiments, each index from a given vector of indexes (packed data source2) is broadcasted to a separate temporal vector from a first set of temporal vectors, the first set of temporal vectors are compared to the given vector of indexes (packed data source2) to generate a set of masks, the set of masks is used to broadcast values provided for reduction (packed data elements of packed data source1) to a second set of temporal vectors with zeroing unset elements, and a reduction of all temporal vectors to a single one is done via addition. Additionally, in some embodiments, to support index types larger than data type of updated elements, vectors from the first set of temporal vectors may have increased vector length, but having the same number of elements as vectors from the second set of temporal vectors. The comparison may be many types such as equal, less than, greater than, less than or equal, greater than or equal, not equal, etc. The arithmetic operation may also be of many types such as addition, subtraction, division, and multiplication. Typically, the comparison type and arithmetic operation are defined by the opcode or an immediate. Note for some arithmetic operations (e.g., add), when using the mask, a zero is used in place of a packed data element not used, but for other arithmetic operations (e.g., multiplication), a one is used in place of a packed data element not used. Which approach, zeroing or one, may be set by the opcode of the instruction. In some embodiments, triangle based comparisons are made.

With this instruction, the algorithm for vectorizing a sparse update pattern looks like:zmm_A=Gather (A+zmm_index)zmm_res=BROADCASTCMPADD(zmm_index, zmm_values)zmm_A=VADD(zmm_A, zmm_res)Scatter (A, zmm_A, zmm_index)

FIG. 1illustrates an exemplary execution of a broadcast compare add instruction. While this illustration is in little endian format, the principles discussed herein work in big endian format. Further, in this example, each packed data element position of the packed data destination131does not include an original value of stored in that position. The broadcast compare add instruction includes fields for a destination (packed data destination (DST)131) and two sources (packed data source1(SRC1)101and packed data source2(SRC2)103). The size of the data elements of the index (packed data source2103) and data (packed data source1101) are detailed by the instruction itself.

Packed data source1101includes four packed data elements (shown at packed data element positions0-3). Depending upon the implementation, packed data source1101is a packed data register (e.g., a XMM, YMM, ZMM, vector, SIMD, D, S, etc. register), or a memory location.

Packed data source2103includes four packed data elements (shown at packed data element positions0-3). Depending upon the implementation, packed data source2103is a packed data register (e.g., a XMM, YMM, ZMM, vector, SIMD, D, S, etc. register), or a memory location.

Packed data source101is fed into execution circuitry109to be operated on. In particular, execution circuitry109performs sums of selected broadcasted packed data elements of the first packed data source101and stores the result of the sums in packed data destination131. In some embodiments, which packed data elements of the first packed data source101are broadcast are dictated by a result of a comparison of broadcasted values of packed data elements stored in the second packed data source103to the packed data elements stored in the second packed data source103(without broadcasting). As such, only the broadcasted packed data elements of the first packed data source101are subject to the arithmetic operation. In other embodiments, which packed data elements of the first packed data source101are selected for the arithmetic operation are dictated by a result of a comparison of broadcasted values of packed data elements stored in the second packed data source103to the packed data elements stored in the second packed data source103(without broadcasting). Packed data element selection circuitry113performs this selection by way of comparison of the packed data elements of the second packed data source103against a broadcast of those packed data elements of the second packed data source103to generate a mask105. Broadcasting is done using a crossbar in some embodiments.

In some embodiments, when the index data type is larger than the data type of values for reduction, the packed data source2103is taken from memory and broadcasted to temporal vectors of increased overall length S*KL, where S is the index packed data elements size and KL is the number of packed data elements in packed data source1101.

Selection and broadcast circuitry111uses the mask105to select how packed data elements of packed data source1101are used by one or more adder circuits121,123,125,127. Note while a plurality of adders is shown, in some embodiments, the same adder is reused. Adders121,123,125,127add its input packed data element values and the output of each adder121,123,125,127is placed into a corresponding packed data element position of the packed data destination131. In some embodiments, selection and broadcast circuitry111is a configurable crossbar.

As such, as illustrated, for each packed data element position of packed data destination operand131, there is an adder that takes in packed data elements from packed data source1101based on the mask105. For example, in packed data element position0of mask105the value is 0x1. As such, only one bit position (the least significant) is set in this element. This set bit indicates that for packed data element position0of packed data source1101that the value in this position (A) is to be operated on by only one adder (in this example, that adder corresponds to adder[0]127which is the adder in the same “position” as the set bit). In packed data element position3of mask105the value is 0x6. As such, only 2 bits are set in this element (0b0110). These set bits indicate that for packed data element position3of packed data source1101that the value in this position (D) is to be operated on by the two adders that correspond to the set bit positions (in this example, those adders corresponds to adder[1]125and adder [2]123). The results of the adders are stored into a corresponding packed data element position of the packed data destination131as shown.

FIG. 2illustrates an exemplary execution of a broadcast compare add instruction. While this illustration is in little endian format, the principles discussed herein work in big endian format. Further, in this example, each packed data element position of the packed data destination231does not include an original value of stored in that position. The broadcast compare add instruction includes fields for a destination (packed data destination (DST)231) and two sources (packed data source1(SRC1)101and packed data source2(SRC2)103).

Packed data source1101includes four packed data elements (shown at packed data element positions0-3). Depending upon the implementation, packed data source1101is a packed data register (e.g., a XMM, YMM, ZMM, vector, SIMD, D, S, etc. register), or a memory location.

Packed data source2103includes four packed data elements (shown at packed data element positions0-3). Depending upon the implementation, packed data source2103is a packed data register (e.g., a XMM, YMM, ZMM, vector, SIMD, D, S, etc. register), or a memory location.

Packed data source101is fed into execution circuitry209to be operated on. In particular, execution circuitry209performs sums of selected broadcasted packed data elements of the first packed data source101and stores the result of the sums in packed data destination231. In some embodiments, which packed data elements of the first packed data source101to broadcast are dictated by a result of a comparison of broadcasted values of packed data elements stored in the second packed data source103to the packed data elements stored in the second packed data source103(without broadcasting). As such, only the broadcasted packed data elements of the first packed data source101are subject to the arithmetic operation. In other embodiments, which packed data elements of the first packed data source101to be selected for the arithmetic operation are dictated by a result of a comparison of broadcasted values of packed data elements stored in the second packed data source103to the packed data elements stored in the second packed data source103(without broadcasting). Packed data element selection circuitry113performs this selection by way of comparison of the packed data elements of the second packed data source103against a broadcast of those packed data elements of the second packed data source103to generate a mask105. Broadcasting is done using a crossbar in some embodiments.

In some embodiments, when the index data type is larger than the data type of values for reduction, the packed data source2103is taken from memory and broadcasted to temporal vectors of increased overall length S*KL, where S is the index packed data elements size and KL is the number of packed data elements in packed data source1101. The size of the data elements of the index (packed data source2103) and data (packed data source1101) are detailed by the instruction itself.

Selection and broadcast circuitry111uses the mask105to select how packed data elements of packed data source1101are broadcast to one or more adder circuits221,223,225,227. Note while a plurality of adders is shown, in some embodiments, the same adder is reused. Adders221,223,225,227add its input packed data element values and the output of each adder221,223,225,227is placed into a corresponding packed data element position of the packed data destination231. In some embodiments, a packed data element from the packed data destination231is included in the addition. In some embodiments, selection and broadcast circuitry111is a configurable crossbar.

As such, as illustrated, for each packed data element position of packed data destination operand231, there is an adder that takes in packed data elements from packed data source1101based on the mask105. For example, in packed data element position0of mask105the value is 0x1. As such, only one bit position (the least significant) is set in this element. This set bit indicates that for packed data element position0of packed data source1101that the value in this position (A) is to be operated on by only one adder (in this example, that adder corresponds to adder[0]227which is the adder in the same “position” as the set bit). In packed data element position3of mask105the value is 0x6. As such, only 2 bits are set in this element (0b0110). These set bits indicate that for packed data element position3of packed data source1101that the value in this position (D) is to be operated on by the two adders that correspond to the set bit positions (in this example, those adders corresponds to adder[1]225and adder [2]223). The results of the adders (including the initial value from the packed data destination231) are added to a corresponding packed data element position of the packed data destination231as shown.

FIG. 3illustrates an exemplary execution of a broadcast compare arithmetic instruction. While this illustration is in little endian format, the principles discussed herein work in big endian format. Further, in this example, each packed data element position of the packed data destination331does not include an original value of stored in that position. The broadcast compare add instruction includes fields for a destination (packed data destination (DST)331) and two sources (packed data source1(SRC1)101and packed data source2(SRC2) 103). The arithmetic operation may be addition, subtraction, multiplication, division, etc.

Packed data source1101includes four packed data elements (shown at packed data element positions0-3). Depending upon the implementation, packed data source1101is a packed data register (e.g., a XMM, YMM, ZMM, vector, SIMD, D, S, etc. register), or a memory location.

Packed data source2103includes four packed data elements (shown at packed data element positions0-3). Depending upon the implementation, packed data source2103is a packed data register (e.g., a XMM, YMM, ZMM, vector, SIMD, D, S, etc. register), or a memory location.

Packed data source101is fed into execution circuitry309to be operated on. In particular, execution circuitry309performs the arithmetic operation on selected broadcasted packed data elements of the first packed data source101and stores the result of the operations in packed data destination331. In some embodiments, which packed data elements of the first packed data source101are broadcast are dictated by a result of a comparison of broadcasted values of packed data elements stored in the second packed data source103to the packed data elements stored in the second packed data source103(without broadcasting). As such, only the broadcasted packed data elements of the first packed data source101are subject to the arithmetic operation. In other embodiments, which packed data elements of the first packed data source101to be selected for the arithmetic operation are dictated by a result of a comparison of broadcasted values of packed data elements stored in the second packed data source103to the packed data elements stored in the second packed data source103(without broadcasting). Packed data element selection circuitry113performs this selection by way of comparison of the packed data elements of the second packed data source103against a broadcast of those packed data elements of the second packed data source103to generate a mask105. Broadcasting is done using a crossbar in some embodiments.

In some embodiments, when the index data type is larger than the data type of values for reduction, the packed data source2103is taken from memory and broadcasted to temporal vectors of increased overall length S*KL, where S is the index packed data elements size and KL is the number of packed data elements in packed data source1101. The size of the data elements of the index (packed data source2103) and data (packed data source1101) are detailed by the instruction itself.

Selection and broadcast circuitry111uses the mask105to select how packed data elements of packed data source1101are broadcast to one or more arithmetic circuit circuits321,323,325,327. Note while a plurality of arithmetic circuits is shown, in some embodiments, the same arithmetic circuit is reused. Arithmetic circuits321,323,325,327perform operations their input packed data element values and the output of each arithmetic circuit321,323,325,327is placed into a corresponding packed data element position of the packed data destination331. In some embodiments, a packed data element from the packed data destination331is included in the addition. In some embodiments, selection and broadcast circuitry111is a configurable crossbar.

As such, as illustrated, for each packed data element position of packed data destination operand331, there is an arithmetic circuit that takes in packed data elements from packed data source1101based on the mask105. For example, in packed data element position0of mask105the value is 0x1. As such, only one bit position (the least significant) is set in this element. This set bit indicates that for packed data element position0of packed data source1101that the value in this position (A) is to be operated on only one arithmetic circuit (in this example, that arithmetic circuit corresponds to arithmetic circuit[0]327which is the arithmetic circuit in the same “position” as the set bit). In packed data element position3of mask105the value is 0x6. As such, only 2 bits are set in this element (0b0110). These set bits indicate that for packed data element position3of packed data source1101that the value in this position (D) is to be operated on by the two arithmetic circuits that correspond to the set bit positions (in this example, those arithmetic circuits corresponds to arithmetic circuit[1]325and arithmetic circuit [2]323). The results of the arithmetic circuits (including the initial value from the packed data destination331if configured as such) are added to a corresponding packed data element position of the packed data destination331as shown.

FIG. 4illustrates an embodiment of an execution of a broadcast compare add instruction. Note that each vertical column is the same lane of a vector register. As shown, a first packed data source1401will supply packed data elements to be added. The “offset” refers to each packed data element position of the first packed data source1401. In this example, there are 8 (KL=8) packed data elements.

A second packed data source403provides a vector of indexes. These indexes are broadcasted at407. The broadcasted indexes are compared against the indexes of the second packed data source403to generate a set of masks409.

The set of masks are used to select values from the first packed data source301to at least one adder which adds the broadcasted values to form a result at411.

At each packed data element position of the packed data destination413, a resulting sum of the broadcasted elements at that position are stored.

FIG. 5illustrates an embodiment of an execution of a broadcast compare add instruction. Note that each vertical column is the same lane of a vector register. As shown, a first packed data source1501will supply packed data elements to be added. The “offset” refers to each packed data element position of the first packed data source1501. In this example, there are 8 (KL=8) packed data elements.

A second packed data source503provides a vector of indexes. These indexes are broadcasted at507. The broadcasted indexes are compared against the indexes of the second packed data source503to generate a set of masks509. This comparison is triangular based.

The set of masks are used to select values from the first packed data source301to at least one adder which adds the broadcasted values to form a result at511.

At each packed data element position of the packed data destination513, a resulting sum of the broadcasted elements at that position are stored.

FIG. 6illustrates an embodiment of hardware to process an instruction such as a broadcast compare arith instruction. As illustrated, storage603stores a broadcast compare arith instruction601to be executed.

The instruction601is received by decode circuitry605. For example, the decode circuitry605receives this instruction from fetch logic/circuitry. The instruction includes fields for an opcode, first and second packed data sources, and a packed data destination. In some embodiments, the sources and destination are registers, and in other embodiments one or more are memory locations. In some embodiments, an opcode or prefix of the instruction601includes an indication of data element size {B/W/D/Q} for element sizes of byte, word, doubleword, and quadword. For example, the size of the data elements of the index (packed data source2103) and data (packed data source1101) are detailed by the instruction itself. In some embodiments, the opcode includes the arithmetic function, and in others this is dictated by an immediate. Typically, the comparison type and arithmetic operation are defined by the opcode or an immediate. The comparison may be many types such as equal, less than, greater than, less than or equal, greater than or equal, not equal, etc. The arithmetic operation may also be of many types such as addition, subtraction, division, and multiplication.

More detailed embodiments of at least one instruction format will be detailed later. The decode circuitry605decodes the instruction into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry609). The decode circuitry605also decodes instruction prefixes.

In some embodiments, register renaming, register allocation, and/or scheduling circuitry607provides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution on execution circuitry out of an instruction pool (e.g., using a reservation station in some embodiments). Additionally, in some embodiments, to support index types larger than data type of updated elements, vectors from the first set of temporal vectors may have increased vector length, but having the same number of elements as vectors from the second set of temporal vectors.

Registers (register file) and/or memory608store data as operands of the instruction to be operated on by execution circuitry609. Exemplary register types include packed data registers, general purpose registers, and floating point registers.

Execution circuitry609executes the decoded instruction. Exemplary detailed execution circuitry was shown inFIGS. 1, 2, and 3. The execution of the decoded instruction causes the execution circuitry to perform an arithmetic operation (reduction) of broadcasted packed data elements of a first packed data source and store the result of each of the arithmetic operations in a packed data destination. In some embodiments, the packed data elements of the first source to be broadcast are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source (without broadcasting). As such, only the broadcasted packed data elements of the first packed data source101are subject to the arithmetic operation. In some embodiments, broadcasted packed data elements of the first source to be selected are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source (without broadcasting). For example, in some embodiments, each index from a given vector of indexes (packed data source2) is broadcasted to a separate temporal vector from a first set of temporal vectors, the first set of temporal vectors are compared to the given vector of indexes (the second packed data source) to generate a set of masks, the set of masks is used to select broadcasted values provided for reduction (packed data elements of the first packed data source) to a second set of temporal vectors (with zeroing unset elements for addition and subtraction, and 1s for multiplication and division), and a reduction of all temporal vectors to a single one is done. In some embodiments, an initial value from the destination is another input used in the sum generation. The comparison may be many types such as equal, less than, greater than, less than or equal, greater than or equal, not equal, etc. The arithmetic operation may also be of many types such as addition, subtraction, division, and multiplication. Typically, the comparison type and arithmetic operation are defined by the opcode or an immediate. Note for some arithmetic operations (e.g., add), when using the mask, a zero is used in place of a packed data element not used, but for other arithmetic operations (e.g., multiplication), a one is used in place of a packed data element not used. Which approach, zeroing or one, may be set by the opcode of the instruction. In some embodiments, triangle based comparisons are made.

In some embodiments, retirement/write back circuitry611architecturally commits the destination register into the registers or memory608and retires the instruction.

An embodiment of a format for a broadcast compare add instruction is BROADCAST CMP ARITH{INDEX B/W/D/Q}{DATA B/W/D/Q} DSTREG, SRC1, SRC2. In some embodiments, BROADCAST CMP ARITH{INDEX B/W/D/Q}{DATA B/W/D/Q} is the opcode mnemonic of the instruction. B/W/D/Q indicates the data element sizes of the sources/destination as byte, word, doubleword, and quadword. For example, the size of source2(index) and source1(data). In other embodiments, the data element and/or index sizes are a part of a prefix. DSTREG is a field for the packed data destination register operand. SRC2and SRC2are fields for the sources such as packed data registers and/or memory. The comparison (CMP) and arithmetic (ARITH) functions are dictated by the opcode and/or an immediate.

In some embodiments, the broadcast compare add instruction includes a field for a writemask register operand (k) (e.g., BROADCAST CMP ARITH{INDEX B/W/D/Q}{DATA B/W/D/Q}{k} DSTREG, SRC1, SRC2). A writemask is used to conditionally control per-element operations and updating of results. Depending upon the implementation, the writemask uses merging or zeroing masking. Instructions encoded with a predicate (writemask, write mask, or k register) operand use that operand to conditionally control per-element computational operation and updating of result to the destination operand. The predicate operand is known as the opmask (writemask) register. In some embodiments, the opmask is a set of architectural registers of size 64-bit. Note that from this set of architectural registers, only k1through k7can be addressed as predicate operand. k0can be used as a regular source or destination but cannot be encoded as a predicate operand. Note also that a predicate operand can be used to enable memory fault-suppression for some instructions with a memory operand (source or destination). As a predicate operand, the opmask registers contain one bit to govern the operation/update to each data element of a vector register. In general, opmask registers can support instructions with element sizes: single-precision floating-point (float32), integer doubleword(int32), double-precision floating-point (float64), integer quadword (int64). The length of a opmask register, MAX_KL, is sufficient to handle up to 64 elements with one bit per element, i.e. 64 bits. For a given vector length, each instruction accesses only the number of least significant mask bits that are needed based on its data type. An opmask register affects an instruction at per-element granularity. So, any numeric or non-numeric operation of each data element and per-element updates of intermediate results to the destination operand are predicated on the corresponding bit of the opmask register. In most embodiments, an opmask serving as a predicate operand obeys the following properties: 1) the instruction's operation is not performed for an element if the corresponding opmask bit is not set (this implies that no exception or violation can be caused by an operation on a masked-off element, and consequently, no exception flag is updated as a result of a masked-off operation); 2). a destination element is not updated with the result of the operation if the corresponding writemask bit is not set. Instead, the destination element value must be preserved (merging-masking) or it must be zeroed out (zeroing-masking); 3) for some instructions with a memory operand, memory faults are suppressed for elements with a mask bit of 0. Note that this feature provides a versatile construct to implement control-flow predication as the mask in effect provides a merging behavior for vector register destinations. As an alternative the masking can be used for zeroing instead of merging, so that the masked out elements are updated with 0 instead of preserving the old value. The zeroing behavior is provided to remove the implicit dependency on the old value when it is not needed.

In embodiments, encodings of the instruction include a scale-index-base (SIB) type memory addressing operand that indirectly identifies multiple indexed destination locations in memory. In one embodiment, an SIB type memory operand may include an encoding identifying a base address register. The contents of the base address register may represent a base address in memory from which the addresses of the particular destination locations in memory are calculated. For example, the base address may be the address of the first location in a block of potential destination locations for an extended vector instruction. In one embodiment, an SIB type memory operand may include an encoding identifying an index register. Each element of the index register may specify an index or offset value usable to compute, from the base address, an address of a respective destination location within a block of potential destination locations. In one embodiment, an SIB type memory operand may include an encoding specifying a scaling factor to be applied to each index value when computing a respective destination address. For example, if a scaling factor value of four is encoded in the SIB type memory operand, each index value obtained from an element of the index register may be multiplied by four and then added to the base address to compute a destination address.

In one embodiment, an SIB type memory operand of the form vm32{x,y,z} may identify a vector array of memory operands specified using SIB type memory addressing. In this example, the array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements, each of which is a 32-bit index value. The vector index register may be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit (e.g., YMM) register (vm32y), or a 512-bit (e.g., ZMM) register (vm32z). In another embodiment, an SIB type memory operand of the form vm64{x,y,z} may identify a vector array of memory operands specified using SIB type memory addressing. In this example, the array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements, each of which is a 64-bit index value. The vector index register may be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit (e.g., YMM) register (vm64y) or a 512-bit (e.g., ZMM) register (vm64z).

FIG. 7illustrates an embodiment of method performed by a processor to process a broadcast compare arith instruction. For example, a processor core as shown inFIGS. 1-3 and 6, a pipeline as detailed below, etc. performs this method.

At701, an instruction is fetched. For example, a broadcast compare arith instruction is fetched. The broadcast compare add instruction includes fields for an opcode, a first and a second source operand, and a destination operand. In some embodiments, the instruction further includes a field for a writemask. In some embodiments, the instruction is fetched from an instruction cache. The source operands and destination operand are packed data. The size of the data elements of the index (second packed data source) and data (first packed data source) are detailed by the instruction.

The fetched instruction is decoded at703. For example, the fetched broadcast compare add instruction is decoded by decode circuitry such as that detailed herein.

Data values associated with the source operands of the decoded instruction are retrieved at705. For example, when one or more of the source operands are memory operands, the data from the indicated memory location is retrieved. Additionally, in some embodiments, to support index types larger than data type of updated elements, vectors from the first set of temporal vectors may have increased vector length, but having the same number of elements as vectors from the second set of temporal vectors.

At707, the decoded instruction is executed by execution circuitry (hardware) such as that detailed herein. For the broadcast compare add instruction, the execution will cause execution circuitry to perform a reduction packed data elements of a first packed data source and store the result of each of the reductions in a packed data destination. In some embodiments, the packed data elements of the first packed data source to be broadcast are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source. In other embodiments, the broadcasted packed data elements of the first packed data source to be selected are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source. For example, in some embodiments, each index from a given vector of indexes (the second packed data source) is broadcasted to a separate temporal vector from a first set of temporal vectors, the first set of temporal vectors are compared to the given vector of indexes (the second packed data source) to generate a set of masks, the set of masks is used to broadcast values provided for reduction (packed data elements of the first packed data source) to a second set of temporal vectors (with zeroing unset elements for addition and subtraction and using a 1 for multiplication and division), and a reduction of all temporal vectors to a single one is done via the reduction operation. In some embodiments, an initial value from the destination is another input used in the reduction. The reduction may be one of addition, multiplication, subtraction, and division. The comparison may be many types such as equal, less than, greater than, less than or equal, greater than or equal, not equal, etc. The arithmetic operation may also be of many types such as addition, subtraction, division, and multiplication. In some embodiments, triangle based comparisons are made.

In some embodiments, the instruction is committed or retired at709.

An example of pseudocode for broadcast compare add is as follows:

KL is number of elements given for reduction in the input source 1 vector. While the reduction is shown as a serialized sequence of accumulation in one temporal vector, but in other implementation it can be done through KL temporal vectors (thus, broadcast operations are parallelized) with reduction performed by a tree.

Another example of pseudocode for broadcast compare add is as shown below. To support any combination of index/data types, including cases when the index data type is larger than data type of values for reduction, indexes can be taken from memory and broadcasted to temporal vectors of increased overall length (S*KL):

Yet another example of pseudocode for broadcast compare add is as shown below. This is for a triangle comparison.

Examples of embodiments are detailed herein.

1. An apparatus comprising: a decoder to decode an instruction having fields for a first source operand and a second source operand, and a destination operand, and execution circuitry to execute the decoded instruction to perform a reduction of broadcasted packed data elements of a first packed data source with a reduction operation and store a result of each of the reductions in a packed data destination, wherein the packed data elements of the first packed data source to be used in the reduction are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source.

2. The apparatus of example 1, wherein the first source operand is a packed data register and the second source operand is a memory location.

3. The apparatus of example 1, wherein the first source operand is a packed data register and the second source operand is a packed data register.

4. The apparatus of example 1, wherein the values of packed data elements stored in the second source operand form a mask.

5. The apparatus of example 1, wherein to execute the decoded instruction, the execution circuitry is to, broadcast each index from a given vector of indexes from the second packed data source to a separate temporal vector from a first set of temporal vectors, compare the first set of temporal vectors to the given vector of indexes from the second packed data source to generate a set of masks, use the set of masks to broadcast values provided for reduction to a second set of temporal vectors and to reduce all of the second set of temporal vectors to a single one by a reduction operation.

6. The apparatus of example 1, wherein the reduction is one of addition, subtraction, multiplication, and division

7. The apparatus of example 1, wherein the comparison is one or more of equal to, not equal, less than, greater than, less than or equal to, and greater than or equal to, and triangular.

8. An method comprising: decoding an instruction having fields for a first source operand and a second source operand, and a destination operand, and executing the decoded instruction to perform a reduction of broadcasted packed data elements of a first packed data source with a reduction operation and store a result of each of the reductions in a packed data destination, wherein the packed data elements of the first packed data source to be broadcast are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source.

9. The method of example 8, wherein the first source operand is a packed data register and the second source operand is a memory location.

10. The method of example 8, wherein the first source operand is a packed data register and the second source operand is a packed data register.

11. The method of example 8, wherein the values of packed data elements stored in the second source operand form a mask.

12. The method of example 8, wherein for each packed data element position of the destination operand, broadcasting each index from a given vector of indexes from the second packed data source to a separate temporal vector from a first set of temporal vectors, comparing the first set of temporal vectors to the given vector of indexes from the second packed data source to generate a set of masks, using the set of masks to broadcast values provided for reduction to a second set of temporal vectors and to reduce all of the second set of temporal vectors to a single one by a reduction operation.

13. The method of example 8, wherein an initial value from the destination is another input used in the reduction generation.

14. The method of example 8, further comprising: translating the instruction from a first instruction set into an instruction of a second instruction set prior to a decode, wherein the instruction to be decoded is of the second instruction set.

15. A non-transitory machine-readable medium storing an instruction which when executed by a processor causes the processor to perform a method, the method comprising: decoding an instruction having fields for a first source operand and a second source operand, and a destination operand, and executing the decoded instruction to perform a reduction of broadcasted packed data elements of a first packed data source with a reduction operation and store a result of each of the reductions in a packed data destination, wherein the packed data elements of the first packed data source to be broadcast are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source.

16. The non-transitory machine-readable medium of example 15, wherein the first source operand is a packed data register and the second source operand is a memory location.

17. The non-transitory machine-readable medium of example 15, wherein the first source operand is a packed data register and the second source operand is a packed data register.

18. The non-transitory machine-readable medium of example 15, wherein the values of packed data elements stored in the second source operand form a mask.

19. The non-transitory machine-readable medium of example 15, wherein for each packed data element position of the destination operand, broadcasting each index from a given vector of indexes from the second packed data source to a separate temporal vector from a first set of temporal vectors, comparing the first set of temporal vectors to the given vector of indexes from the second packed data source to generate a set of masks, using the set of masks to broadcast values provided for reduction to a second set of temporal vectors and to reduce all of the second set of temporal vectors to a single one by a reduction operation.

20. The non-transitory machine-readable medium of example 15, wherein an initial value from the destination is another input used in the reduction generation.

21. The non-transitory machine-readable medium of example 15, further comprising: translating the instruction from a first instruction set into an instruction of a second instruction set prior to a decode, wherein the instruction to be decoded is of the second instruction set.

22. An apparatus comprising:a decoder means for decoding an instruction having fields for a first and a second source operand, and a destination operand, andexecution means for executing the decoded instruction to perform a reduction of broadcasted packed data elements of a first packed data source with a reduction operation and store a result of each of the reductions in a packed data destination, wherein the packed data elements of the first packed data source to be used in the reduction are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source.

23. The apparatus of example 22, wherein the first source operand is a packed data register and the second source operand is a memory location.

24. The apparatus of example 22, wherein the first source operand is a packed data register and the second source operand is a packed data register.

25. The apparatus of any of examples 22-24, wherein the values of packed data elements stored in the second source operand form a mask.

26. The apparatus of any of examples 22-25, wherein to execute the decoded instruction, the execution circuitry is to, broadcast each index from a given vector of indexes from the second packed data source to a separate temporal vector from a first set of temporal vectors, compare the first set of temporal vectors to the given vector of indexes from the second packed data source to generate a set of masks, use the set of masks to broadcast values provided for reduction to a second set of temporal vectors and to reduce all of the second set of temporal vectors to a single one by a reduction operation.

27. The apparatus of any of examples 22-26, wherein the reduction is one of addition, subtraction, multiplication, and division

28. The apparatus of any of examples 22-27, wherein the comparison is one or more of equal to, not equal, less than, greater than, less than or equal to, and greater than or equal to, and triangular.

The figures below detail exemplary architectures and systems to implement embodiments of the above. In some embodiments, one or more hardware components and/or instructions described above are emulated as detailed below, or implemented as software modules.

Instruction Sets

Exemplary Instruction Formats

Generic Vector Friendly Instruction Format

FIGS. 8A-8Bare block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to embodiments of the invention.FIG. 8Ais a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to embodiments of the invention; whileFIG. 8Bis a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to embodiments of the invention. Specifically, a generic vector friendly instruction format800for which are defined class A and class B instruction templates, both of which include no memory access805instruction templates and memory access820instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set.

The class A instruction templates inFIG. 8Ainclude: 1) within the no memory access805instruction templates there is shown a no memory access, full round control type operation810instruction template and a no memory access, data transform type operation815instruction template; and 2) within the memory access820instruction templates there is shown a memory access, temporal825instruction template and a memory access, non-temporal830instruction template. The class B instruction templates inFIG. 8Binclude: 1) within the no memory access805instruction templates there is shown a no memory access, write mask control, partial round control type operation812instruction template and a no memory access, write mask control, vsize type operation817instruction template; and 2) within the memory access820instruction templates there is shown a memory access, write mask control827instruction template.

The generic vector friendly instruction format800includes the following fields listed below in the order illustrated inFIGS. 8A-8B.

Base operation field842—its content distinguishes different base operations.

Augmentation operation field850—its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment of the invention, this field is divided into a class field868, an alpha field852, and a beta field854. The augmentation operation field850allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions.

Scale field860—its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses 2scale*index+base).

Displacement Field862A—its content is used as part of memory address generation (e.g., for address generation that uses 2scale*index+base+displacement).

Displacement Factor Field862B (note that the juxtaposition of displacement field862A directly over displacement factor field862B indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2scale*index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field874(described later herein) and the data manipulation field854C. The displacement field862A and the displacement factor field862B are optional in the sense that they are not used for the no memory access805instruction templates and/or different embodiments may implement only one or none of the two.

Class field868—its content distinguishes between different classes of instructions. With reference toFIGS. 8A-B, the contents of this field select between class A and class B instructions. InFIGS. 8A-B, rounded corner squares are used to indicate a specific value is present in a field (e.g., class A868A and class B868B for the class field868respectively inFIGS. 8A-B).

Instruction Templates of Class A

In the case of the non-memory access805instruction templates of class A, the alpha field852is interpreted as an RS field852A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round852A.1and data transform852A.2are respectively specified for the no memory access, round type operation810and the no memory access, data transform type operation815instruction templates), while the beta field854distinguishes which of the operations of the specified type is to be performed. In the no memory access805instruction templates, the scale field860, the displacement field862A, and the displacement scale filed862B are not present.

In the no memory access full round control type operation810instruction template, the beta field854is interpreted as a round control field854A, whose content(s) provide static rounding. While in the described embodiments of the invention the round control field854A includes a suppress all floating point exceptions (SAE) field856and a round operation control field858, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field858).

SAE field856—its content distinguishes whether or not to disable the exception event reporting; when the SAE field's856content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler.

In the no memory access data transform type operation815instruction template, the beta field854is interpreted as a data transform field854B, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast).

In the case of a memory access820instruction template of class A, the alpha field852is interpreted as an eviction hint field852B, whose content distinguishes which one of the eviction hints is to be used (inFIG. 8A, temporal852B.1and non-temporal852B.2are respectively specified for the memory access, temporal825instruction template and the memory access, non-temporal830instruction template), while the beta field854is interpreted as a data manipulation field854C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access820instruction templates include the scale field860, and optionally the displacement field862A or the displacement scale field862B.

Memory Access Instruction Templates—Temporal

Memory Access Instruction Templates—Non-Temporal

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field852is interpreted as a write mask control (Z) field852C, whose content distinguishes whether the write masking controlled by the write mask field870should be a merging or a zeroing.

In the case of the non-memory access805instruction templates of class B, part of the beta field854is interpreted as an RL field857A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round857A.1and vector length (VSIZE)857A.2are respectively specified for the no memory access, write mask control, partial round control type operation812instruction template and the no memory access, write mask control, VSIZE type operation817instruction template), while the rest of the beta field854distinguishes which of the operations of the specified type is to be performed. In the no memory access805instruction templates, the scale field860, the displacement field862A, and the displacement scale filed862B are not present.

In the no memory access, write mask control, partial round control type operation810instruction template, the rest of the beta field854is interpreted as a round operation field859A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler).

Round operation control field859A—just as round operation control field858, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field859A allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the invention where a processor includes a control register for specifying rounding modes, the round operation control field's850content overrides that register value.

In the no memory access, write mask control, VSIZE type operation817instruction template, the rest of the beta field854is interpreted as a vector length field859B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte).

In the case of a memory access820instruction template of class B, part of the beta field854is interpreted as a broadcast field857B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field854is interpreted the vector length field859B. The memory access820instruction templates include the scale field860, and optionally the displacement field862A or the displacement scale field862B.

With regard to the generic vector friendly instruction format800, a full opcode field874is shown including the format field840, the base operation field842, and the data element width field864. While one embodiment is shown where the full opcode field874includes all of these fields, the full opcode field874includes less than all of these fields in embodiments that do not support all of them. The full opcode field874provides the operation code (opcode).

The augmentation operation field850, the data element width field864, and the write mask field870allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.

Exemplary Specific Vector Friendly Instruction Format

FIG. 9Ais a block diagram illustrating an exemplary specific vector friendly instruction format according to embodiments of the invention.FIG. 9Ashows a specific vector friendly instruction format900that is specific in the sense that it specifies the location, size, interpretation, and order of the fields, as well as values for some of those fields. The specific vector friendly instruction format900may be used to extend the x86 instruction set, and thus some of the fields are similar or the same as those used in the existing x86 instruction set and extension thereof (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD R/M field, SIB field, displacement field, and immediate fields of the existing x86 instruction set with extensions. The fields fromFIG. 8into which the fields fromFIG. 9Amap are illustrated.

It should be understood that, although embodiments of the invention are described with reference to the specific vector friendly instruction format900in the context of the generic vector friendly instruction format800for illustrative purposes, the invention is not limited to the specific vector friendly instruction format900except where claimed. For example, the generic vector friendly instruction format800contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format900is shown as having fields of specific sizes. By way of specific example, while the data element width field864is illustrated as a one bit field in the specific vector friendly instruction format900, the invention is not so limited (that is, the generic vector friendly instruction format800contemplates other sizes of the data element width field864).

The generic vector friendly instruction format800includes the following fields listed below in the order illustrated inFIG. 9A.

Format Field840(EVEX Byte 0, bits [7:0])—the first byte (EVEX Byte 0) is the format field840and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in one embodiment of the invention).

The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fields providing specific capability.

Data element width field864(EVEX byte 2, bit [7]—W)—is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the datatype (either 32-bit data elements or 64-bit data elements).

EVEX.U868Class field (EVEX byte 2, bit [2]—U)—If EVEX.U=0, it indicates class A or EVEX.U0; if EVEX.U=1, it indicates class B or EVEX.U1.

Alpha field852(EVEX byte 3, bit [7]—EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustrated with α)—as previously described, this field is context specific.

Real Opcode Field930(Byte 4) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD R/M Field940(Byte 5) includes MOD field942, Reg field944, and R/M field946. As previously described, the MOD field's942content distinguishes between memory access and non-memory access operations. The role of Reg field944can be summarized to two situations: encoding either the destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field946may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, the scale field's850content is used for memory address generation. SIB.xxx954and SIB.bbb956—the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.

Displacement field862A (Bytes 7-10)—when MOD field942contains 10, bytes 7-10 are the displacement field862A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity.

Full Opcode Field

FIG. 9Bis a block diagram illustrating the fields of the specific vector friendly instruction format900that make up the full opcode field874according to one embodiment of the invention. Specifically, the full opcode field874includes the format field840, the base operation field842, and the data element width (W) field864. The base operation field842includes the prefix encoding field925, the opcode map field915, and the real opcode field930.

Register Index Field

FIG. 9Cis a block diagram illustrating the fields of the specific vector friendly instruction format900that make up the register index field844according to one embodiment of the invention. Specifically, the register index field844includes the REX field905, the REX′ field910, the MODR/M.reg field944, the MODR/M.r/m field946, the VVVV field920, xxx field954, and the bbb field956.

Augmentation Operation Field

FIG. 9Dis a block diagram illustrating the fields of the specific vector friendly instruction format900that make up the augmentation operation field850according to one embodiment of the invention. When the class (U) field868contains 0, it signifies EVEX.U0 (class A868A); when it contains 1, it signifies EVEX.U1 (class B868B). When U=0 and the MOD field942contains 11 (signifying a no memory access operation), the alpha field852(EVEX byte 3, bit [7]—EH) is interpreted as the rs field852A. When the rs field852A contains a 1 (round852A.1), the beta field854(EVEX byte 3, bits [6:4]—SSS) is interpreted as the round control field854A. The round control field854A includes a one bit SAE field856and a two bit round operation field858. When the rs field852A contains a 0 (data transform852A.2), the beta field854(EVEX byte 3, bits [6:4]—SSS) is interpreted as a three bit data transform field854B. When U=0 and the MOD field942contains 00, 01, or 10 (signifying a memory access operation), the alpha field852(EVEX byte 3, bit [7]—EH) is interpreted as the eviction hint (EH) field852B and the beta field854(EVEX byte 3, bits [6:4]—SSS) is interpreted as a three bit data manipulation field854C.

When U=1, the alpha field852(EVEX byte 3, bit [7]—EH) is interpreted as the write mask control (Z) field852C. When U=1 and the MOD field942contains 11 (signifying a no memory access operation), part of the beta field854(EVEX byte 3, bit [4]—S0) is interpreted as the RL field857A; when it contains a 1 (round857A.1) the rest of the beta field854(EVEX byte 3, bit [6-5]—S2-1) is interpreted as the round operation field859A, while when the RL field857A contains a 0 (VSIZE857.A2) the rest of the beta field854(EVEX byte 3, bit [6-5]—S2-1) is interpreted as the vector length field859B (EVEX byte 3, bit [6-5]—L1-0). When U=1 and the MOD field942contains 00, 01, or 10 (signifying a memory access operation), the beta field854(EVEX byte 3, bits [6:4]—SSS) is interpreted as the vector length field859B (EVEX byte 3, bit [6-5]—L1-0) and the broadcast field857B (EVEX byte 3, bit [4]—B).

Exemplary Register Architecture

FIG. 10is a block diagram of a register architecture1000according to one embodiment of the invention. In the embodiment illustrated, there are 32 vector registers1010that are 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. The specific vector friendly instruction format900operates on these overlaid register file as illustrated in the below tables.

In other words, the vector length field859B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field859B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format900operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

Write mask registers1015—in the embodiment illustrated, there are 8 write mask registers (k0through k7), each 64 bits in size. In an alternate embodiment, the write mask registers1015are 16 bits in size. As previously described, in one embodiment of the invention, the vector mask register k0cannot be used as a write mask; when the encoding that would normally indicate k0is used for a write mask, it selects a hardwired write mask of 0xFFFF, effectively disabling write masking for that instruction.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

InFIG. 11A, a processor pipeline1100includes a fetch stage1102, a length decode stage1104, a decode stage1106, an allocation stage1108, a renaming stage1110, a scheduling (also known as a dispatch or issue) stage1112, a register read/memory read stage1114, an execute stage1116, a write back/memory write stage1118, an exception handling stage1122, and a commit stage1124.

FIG. 11Bshows processor core1190including a front end unit1130coupled to an execution engine unit1150, and both are coupled to a memory unit1170. The core1190may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core1190may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit1130includes a branch prediction unit1132coupled to an instruction cache unit1134, which is coupled to an instruction translation lookaside buffer (TLB)1136, which is coupled to an instruction fetch unit1138, which is coupled to a decode unit1140. The decode unit1140(or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit1140may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core1190includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit1140or otherwise within the front end unit1130). The decode unit1140is coupled to a rename/allocator unit1152in the execution engine unit1150.

The execution engine unit1150includes the rename/allocator unit1152coupled to a retirement unit1154and a set of one or more scheduler unit(s)1156. The scheduler unit(s)1156represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)1156is coupled to the physical register file(s) unit(s)1158. Each of the physical register file(s) units1158represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit1158comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s)1158is overlapped by the retirement unit1154to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit1154and the physical register file(s) unit(s)1158are coupled to the execution cluster(s)1160. The execution cluster(s)1160includes a set of one or more execution units1162and a set of one or more memory access units1164. The execution units1162may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)1156, physical register file(s) unit(s)1158, and execution cluster(s)1160are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)1164). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units1164is coupled to the memory unit1170, which includes a data TLB unit1172coupled to a data cache unit1174coupled to a level2(L2) cache unit1176. In one exemplary embodiment, the memory access units1164may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit1172in the memory unit1170. The instruction cache unit1134is further coupled to a level 2 (L2) cache unit1176in the memory unit1170. The L2 cache unit1176is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline1100as follows: 1) the instruction fetch1138performs the fetch and length decoding stages1102and1104; 2) the decode unit1140performs the decode stage1106; 3) the rename/allocator unit1152performs the allocation stage1108and renaming stage1110; 4) the scheduler unit(s)1156performs the schedule stage1112; 5) the physical register file(s) unit(s)1158and the memory unit1170perform the register read/memory read stage1114; the execution cluster1160perform the execute stage1116; 6) the memory unit1170and the physical register file(s) unit(s)1158perform the write back/memory write stage1118; 7) various units may be involved in the exception handling stage1122; and 8) the retirement unit1154and the physical register file(s) unit(s)1158perform the commit stage1124.

Specific Exemplary in-Order Core Architecture

FIG. 12Ais a block diagram of a single processor core, along with its connection to the on-die interconnect network1202and with its local subset of the Level 2 (L2) cache1204, according to embodiments of the invention. In one embodiment, an instruction decoder1200supports the x86 instruction set with a packed data instruction set extension. An L1 cache1206allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit1208and a vector unit1210use separate register sets (respectively, scalar registers1212and vector registers1214) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache1206, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

FIG. 12Bis an expanded view of part of the processor core inFIG. 12Aaccording to embodiments of the invention.FIG. 12Bincludes an L1 data cache1206A part of the L1 cache1204, as well as more detail regarding the vector unit1210and the vector registers1214. Specifically, the vector unit1210is a 16-wide vector processing unit (VPU) (see the 16-wide ALU1228), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit1220, numeric conversion with numeric convert units1222A-B, and replication with replication unit1224on the memory input. Write mask registers1226allow predicating resulting vector writes.

FIG. 13is a block diagram of a processor1300that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes inFIG. 13illustrate a processor1300with a single core1302A, a system agent1310, a set of one or more bus controller units1316, while the optional addition of the dashed lined boxes illustrates an alternative processor1300with multiple cores1302A-N, a set of one or more integrated memory controller unit(s)1314in the system agent unit1310, and special purpose logic1308.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units1306, and external memory (not shown) coupled to the set of integrated memory controller units1314. The set of shared cache units1306may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit1312interconnects the integrated graphics logic1308(integrated graphics logic1308is an example of and is also referred to herein as special purpose logic), the set of shared cache units1306, and the system agent unit1310/integrated memory controller unit(s)1314, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units1306and cores1302-A-N.

In some embodiments, one or more of the cores1302A-N are capable of multi-threading. The system agent1310includes those components coordinating and operating cores1302A-N. The system agent unit1310may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores1302A-N and the integrated graphics logic1308. The display unit is for driving one or more externally connected displays.

Exemplary Computer Architectures

Referring now toFIG. 14, shown is a block diagram of a system1400in accordance with one embodiment of the present invention. The system1400may include one or more processors1410,1415, which are coupled to a controller hub1420. In one embodiment the controller hub1420includes a graphics memory controller hub (GMCH)1490and an Input/Output Hub (IOH)1450(which may be on separate chips); the GMCH1490includes memory and graphics controllers to which are coupled memory1440and a coprocessor1445; the IOH1450couples input/output (I/O) devices1460to the GMCH1490. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory1440and the coprocessor1445are coupled directly to the processor1410, and the controller hub1420in a single chip with the IOH1450.

The optional nature of additional processors1415is denoted inFIG. 14with broken lines. Each processor1410,1415may include one or more of the processing cores described herein and may be some version of the processor1300.

The memory1440may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub1420communicates with the processor(s)1410,1415via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection1495.

In one embodiment, the coprocessor1445is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub1420may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources1410,1415in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor1410executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor1410recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor1445. Accordingly, the processor1410issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor1445. Coprocessor(s)1445accept and execute the received coprocessor instructions.

Referring now toFIG. 15, shown is a block diagram of a first more specific exemplary system1500in accordance with an embodiment of the present invention. As shown inFIG. 15, multiprocessor system1500is a point-to-point interconnect system, and includes a first processor1570and a second processor1580coupled via a point-to-point interconnect1550. Each of processors1570and1580may be some version of the processor1300. In one embodiment of the invention, processors1570and1580are respectively processors1410and1415, while coprocessor1538is coprocessor1445. In another embodiment, processors1570and1580are respectively processor1410coprocessor1445.

Processors1570and1580are shown including integrated memory controller (IMC) units1572and1582, respectively. Processor1570also includes as part of its bus controller units point-to-point (P-P) interfaces1576and1578; similarly, second processor1580includes P-P interfaces1586and1588. Processors1570,1580may exchange information via a point-to-point (P-P) interface1550using P-P interface circuits1578,1588. As shown inFIG. 15, IMCs1572and1582couple the processors to respective memories, namely a memory1532and a memory1534, which may be portions of main memory locally attached to the respective processors.

Processors1570,1580may each exchange information with a chipset1590via individual P-P interfaces1552,1554using point to point interface circuits1576,1594,1586,1598. Chipset1590may optionally exchange information with the coprocessor1538via a high-performance interface1592. In one embodiment, the coprocessor1538is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

Chipset1590may be coupled to a first bus1516via an interface1596. In one embodiment, first bus1516may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown inFIG. 15, various I/O devices1514may be coupled to first bus1516, along with a bus bridge1518which couples first bus1516to a second bus1520. In one embodiment, one or more additional processor(s)1515, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus1516. In one embodiment, second bus1520may be a low pin count (LPC) bus. Various devices may be coupled to a second bus1520including, for example, a keyboard and/or mouse1522, communication devices1527and a storage unit1528such as a disk drive or other mass storage device which may include instructions/code and data1530, in one embodiment. Further, an audio I/O1524may be coupled to the second bus1520. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 15, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 16, shown is a block diagram of a second more specific exemplary system1600in accordance with an embodiment of the present invention. Like elements inFIGS. 15 and 16bear like reference numerals, and certain aspects ofFIG. 15have been omitted fromFIG. 16in order to avoid obscuring other aspects ofFIG. 16.

FIG. 16illustrates that the processors1570,1580may include integrated memory and I/O control logic (“CL”)1572and1582, respectively. Thus, the CL1572,1582include integrated memory controller units and include I/O control logic.FIG. 16illustrates that not only are the memories1532,1534coupled to the CL1572,1582, but also that I/O devices1614are also coupled to the control logic1572,1582. Legacy I/O devices1615are coupled to the chipset1590.

Referring now toFIG. 17, shown is a block diagram of a SoC1700in accordance with an embodiment of the present invention. Similar elements inFIG. 13bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. InFIG. 17, an interconnect unit(s)1702is coupled to: an application processor1710which includes a set of one or more cores1302A-N, which include cache units1304A-N, and shared cache unit(s)1306; a system agent unit1310; a bus controller unit(s)1316; an integrated memory controller unit(s)1314; a set or one or more coprocessors1720which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit1730; a direct memory access (DMA) unit1732; and a display unit1740for coupling to one or more external displays. In one embodiment, the coprocessor(s)1720include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.